Patent ID: 12191328

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Unless explicitly stated otherwise, each element having the same reference numeral is presumed to have the same material composition and to have a thickness within a same thickness range.

The present disclosure is directed to photodetector sensor devices with reduced dark current sensitivity. To improve dark current sensitivity, photodetector sensors may be formed with a germanium (Ge) detection region disposed over a semiconductor substrate. However, such a configuration may limit the number of Ge layers that may be integrated into a device, which may reduce device resolution and/or increase device size and complexity. By recessing the semiconductor substrate and depositing the Ge material therein to form a detection region, a photodetector device with improved device resolution and/or increased device size and complexity characteristics may be formed. The recess in the semiconductor substrate may be formed using a first etchant gas that includes a first halogen series. However, such an etchant gas may leave the first halogen series implanted in the semiconductor substrate. The implanted first halogen series may diffuse into the subsequently formed Ge material in the detection region. In order to mitigate against the diffusion of the first halogen series, a second etch process using a second etchant gas including a second halogen series may be performed. The resulting implanted second halogen series may act as a barrier layer to the implanted first halogen series, thus preventing the diffusion of the first halogen series into the subsequently formed detection region.

A photodiode may be used to detect optical signals and convert the optical signals to electrical signals that may be further processed by another circuitry. Photodiodes may be used in consumer electronics products, image sensors, data communications, time-of-flight (TOF) applications, medical devices, and many other suitable applications. The photodiodes convert the detected light into electrical charges. Each photodiode may include multiple gates that are controlled to collect the electrical charges.

A typical image sensor comprises a two-dimensional array of photodetectors (called a focal plane array) in combination with a readout integrated circuit (ROIC). The photodetectors are sensitive to incoming radiation. The ROIC quantitatively evaluates the outputs from the photodetectors and processes them into an image. Common image sensing device defects include optical cross-talk, electrical cross-talk, and dark current. These defects become more impactful as the image pixel sizes and the spacing between neighboring image pixels continues to shrink. Optical cross-talk refers to photon interference from neighboring pixels that degrades the light-sensing reliability and accuracy of the pixels. Dark current may be defined as the existence of pixel current when no actual illumination is present. In other words, the dark current is the current that flows through the photodiode despite no photons entering the photodiode. White pixels occur where an excessive amount of current leakage causes an abnormally high signal from the pixels.

In photo sensors, such as TOF sensors that include a Ge layer as an image sensor material, excessive dark current may be generated if the Ge layer is not properly formed. For example, defects in the crystal structure and/or impurities in the Ge layer may increase the potential for dark current.

Germanium is chemically compatible with silicon and optically responsive to radiation in the visible spectrum from blue light to wavelengths of about 1.6 μm. Conventional detectors have relied upon Ge layer formed over a semiconductor substrate. However, such a configuration may limit the number of Ge layers that may be integrated into a device, which may reduce device resolution and/or increase device size and complexity. Accordingly, there is a need for a new method of forming Ge detection regions that are integrated directly into a semiconductor substrate to provide photodetectors that have improved sensitivity, dynamic range, and/or efficiency.

According to various embodiments,FIG.1is a flow diagram illustrating the operations of a method of forming a photo detector including Ge-based detection regions that are epitaxially grown directly in recesses formed in a semiconductor substrate, according to various embodiments of the present disclosure.FIGS.2A-2Kare cross-sectional views illustrating the various intermediary structures that may be formed through the operations of the method ofFIG.1.

Referring toFIGS.1and2A, in operation10, the method may include forming a hard mask layer104on a semiconductor substrate102, which may also be referred to herein as a “first semiconductor substrate”. The semiconductor substrate102may be a silicon substrate; however, any suitable semiconductor material may be used. The semiconductor substrate102may include doped regions (not shown) including P-type or N-type dopants implanted therein. The doped regions may form elements of photodiodes, in some embodiments. The semiconductor substrate102may have a thickness ranging from about 2 μm to about 5 μm, such as about 3 μm, although thicker or thinner dimensions may be used.

The hard mask layer104may be an oxide layer, such as a SiO2layer, formed on an upper surface of the semiconductor substrate102. However, the present disclosure is not limited to any particular type of hard mask material. Other hard mask materials are within the contemplated scope of disclosure. In various embodiments, the hard mask layer104may be formed by oxidizing the surface of the semiconductor substrate102, or may be formed by depositing a hard mask layer104material on the semiconductor substrate102using any suitable deposition method. Herein, “suitable deposition processes” may include a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a high density plasma CVD (HDPCVD) process, a metalorganic CVD (MOCVD) process, a plasma enhanced CVD (PECVD) process, a sputtering process, laser ablation, or the like.

A photoresist layer106may be deposited over the hard mask layer104using any suitable deposition process. The photoresist layer106may be patterned, for example, through a photolithographic process to cover portions of the upper surface of the hard mask layer104and to expose other portions of the hard mask layer104. Although not shown, the patterning may expose multiple portions of the hard mask layer104, and the exposed portions may be arranged in an array.

Referring toFIGS.1and2B, in operation12, the method may include performing a patterning process to pattern the hard mask layer104, using the photoresist layer106as a mask, to expose a portion of the upper surface of the semiconductor substrate102. Although not shown, the patterning process may expose multiple portions of the semiconductor substrate102, with the portions being arranged in an array. The patterning process may include any suitable wet or dry etching process to pattern the hard mask layer104.

Referring toFIGS.1and2C, in operation14, the method may include performing a first etching process. The first etching process may include etching the semiconductor substrate102, using the hard mask layer104as a mask, to form a recess108in the semiconductor substrate102. Although not shown, an array of recesses108may be formed in the semiconductor substrate102.

The first etching process may include dry etching, wet etching, or combination thereof. In the present embodiment, the first etching process may be a dry etching process, such as reactive ion etching, which utilizes a gaseous first etchant, optionally in combination with oxygen gas (O2) and/or helium gas (He). In various embodiments, the gaseous first etchant may include elements selected from a first halogen species. For example, the halogen species may include six nonmetallic elements that constitute Group 17 (Group VIIa) of the periodic table. The halogen elements include fluorine (F), chlorine (Cl), bromine (Br), iodine (I), astatine (At), and tennessine (Ts). However, the first etchant may preferably include F, Cl, Br, and I as more common etchants. For example, the first etchant may include halogen gasses, such as F2, Cl2, Br2, or I2, or halogen-containing gasses, such as CHF4, CH2F2, CH3F, NF3, SiF4, CF4, SF6F, S2F2, XeF2, CBr4, or the like. However, the embodiments disclosed herein are not intended to be limited to these exemplary etchants. Other suitable etchants are within the contemplated scope of disclosure.

The first etching process may be conducted using a pressure ranging from about 1 mT to about 1000 mT, although lesser or greater pressures may be used. The first etching process may be performed using a power ranging from about 50 W to about 1000 W, although less or more power may be used. The first etching process may use a bias voltage ranging from about 100 V to about 500 V, although a lesser or greater bias voltage may be used. The first etching process may use a first etchant gas flow rate ranging from about 10 sccm to about 500 sccm, although a lesser or greater first etchant gas flow rate may be used. The first etching process may use an O2flow rate ranging from about 0 sccm to about 100 sccm, although a lesser or greater flow rate of O2may be used. The first etching process may use a He flow rate ranging from about 0 sccm to about 1000 sccm, although a lesser or greater flow rate of He may be used.

In an embodiment, the recess108may have substantially vertical sidewalls due to the directional/anisotropic etching. In another embodiment, the sidewalls may be tapered. In addition, first halogen species110may remain in the substrate102, adjacent to the sidewalls and/or the bottom of the recess108. In various embodiments, the depth of the recess108may be in a range from 0.5 micron to 10 microns, such as from 1 micron to 6 microns, although lesser and greater depths may also be used. The lateral dimension of the recess108may be in a range from 0.5 micron to 30 microns, such as from 1 micron to 15 microns, although lesser and greater lateral dimensions may also be used.

Referring toFIGS.1and2D, in operation16, the method may include performing a second etching process. In particular, the second etching process may be a dry etching process, such as reactive ion etching, that utilizes a gaseous second etchant, optionally in combination with O2and/or He. In various embodiments, the gaseous second etchant may include elements selected from a second halogen species. As noted above, the halogen species may include six nonmetallic elements that constitute Group 17 (Group VIIa) of the periodic table. The halogen elements include fluorine (F), chlorine (Cl), bromine (Br), iodine (I), astatine (At), and tennessine (Ts). However, the second etchant may preferably include F, Cl, Br, and I as more common etchants. For example, the second etchant may include halogen gasses as noted above. However, the embodiments disclosed herein are not intended to be limited to these exemplary etchants. Other suitable etchants are within the contemplated scope of disclosure.

The second etching process may be a surface etching processes that lightly etches the sidewalls and/or the bottom of the recess108. In particular, the second etching process may not significantly increase the etching depth of the recess108, e.g., the depth and/or width of the recess108. For example, the second etching process may increase the etching depth of the recess108by an amount of less than about 10%, or less than about 5%. Second halogen species112generated from the second etchant during the second etching process may remain in the substrate102, adjacent to the sidewalls and bottom of the recess108, after the second etching process is complete.

The second etching process may be conducted using a pressure ranging from about 1 mT to about 1000 mT, although lesser or greater pressures may be used. The second etching process may be performed using a power ranging from about 50 W to about 1000 W, although less or more power may be used. The second etching process may use a bias voltage ranging from about 100 V to about 500 V, although a lesser or greater bias voltage may be used. The second etching process may use a second etchant gas flow rate ranging from about 10 sccm to about 250 sccm, although a lesser or greater second etchant gas flow rate may be used. The second etching process may use an O2flow rate ranging from about 0 sccm to about 100 sccm, although a lesser or greater flow rate of O2may be used. The second etching process may use a He flow rate ranging from about 0 sccm to about 1000 sccm, although a lesser or greater flow rate of He may be used.

In various embodiments, the second etching process may be configured such that the second halogen species112may be disposed, on average, closer to the sidewalls and bottom of the recess108than the first halogen species110. In other words, the penetration depth of the second halogen species112into the substrate102(e.g., bottom and/or sidewalls of the recess108) may be less than a penetration depth of the first halogen species110. For example, the first etchant and second etchant may be selected such that the second halogen species112has a lower diffusion coefficient with respect to silicon than the first halogen species110. In some embodiments, the second etching process may be conducted at a lower power and/or for a shorter duration than the first etching process. For example, the second etching process may have a lower bias voltage than the first etching process. Accordingly, the second halogen species112may effectively form a barrier layer114that surrounds the sidewalls and bottom of the recess108.

According to various embodiments, the first etchant and the second etchant may be selected such that the second halogen species112may be larger (e.g., have a larger atomic radius) than the first halogen species110. For example, in some embodiments, the first halogen species110may comprise F and/or Cl, and the second halogen species112may comprise Br and/or Ir. In other embodiments, the first halogen species110may comprise F, and the second halogen species112may comprise Cl and/or Br. For example, the first etchant and the second etchant may be selected such that the halogen atoms generated by the second etchant are larger than the halogen atoms generated by the first etchant. For example, the first etchant may comprise Cl2, or a Cl-containing etchant, and the second etchant may comprise Br2, or a Br-containing etchant, and the first halogen species110may include Cl atoms, and the second halogen species112may include relatively larger Br atoms. As such, the second halogen species112may form the barrier layer114surrounding the recess108.

Referring toFIGS.1and2E-2G, in operation18, a detection region120may be grown in the recess108. In particular, a germanium-containing layer120L may be grown on the semiconductor substrate102and in the recess108. The germanium-containing layer120L may include germanium at an atomic percentage greater than 50%. In one embodiment, the germanium-containing layer120L may include doped or undoped germanium such that the atomic percentage of germanium is at least 99%, and is essentially free of silicon. In another embodiment, the germanium-containing layer120L may include a silicon-germanium alloy in which the atomic percentage of germanium is greater than 50%, and the atomic percentage of silicon is less than 50%, such as from 1% to 30%.

The germanium-containing layer120L may be formed by a selective deposition process or a non-selective deposition process. The selective deposition process or the non-selective deposition process may be an epitaxial deposition process, i.e., a deposition process that provides alignment of crystallographic structure of the deposited germanium-containing material to the crystalline structure at the physically exposed surfaces of the underlying material portions. Thus, at least the portion of the germanium-containing layer120L that is deposited in the recess108may be formed as a single crystal that is epitaxially aligned to the crystalline structure of the semiconductor substrate102.

The location and/or size of the second halogen species112may allow the barrier layer114to limit the diffusion of the first halogen species110into the germanium-containing layer120L, as compared to a similar structure that was formed without a second etching process and did not include a barrier layer114formed of the second halogen species112. As such, only a relatively small number of the first halogen species110D may diffuse into the germanium-containing layer120L, as shown inFIG.2E. In other words, the barrier layer114reduces diffusion of the first halogen species110into the germanium-containing layer120L from the first semiconductor substrate102. Further discussion of the properties of the barrier layer114are discussed in detail below with respect toFIGS.4A and4B.

Excess portions of the germanium-containing layer120L may be removed from above the horizontal plane including the top surface of the hard mask layer104, to form the detection region120in the recess108. In one embodiment, a chemical mechanical planarization (CMP) process may be performed to remove portions of the germanium-containing layer120L located above the horizontal plane including the top surface of the hard mask layer104. As shown inFIG.2F, the detection region120and hard mask layer104may be co-planar.

As shown inFIG.2G, a recess etching process may be performed to vertically recess the detection region120. In some embodiments, the vertical recess distance may be greater than the thickness of the hard mask layer104, in order to prevent direct contact between the hard mask layer104and the detection region120.

Referring toFIGS.1and2H, in operation20a selective epitaxy process may be performed to grow a silicon passivation layer340from the top surface of the detection region120. The silicon passivation layer340may include single crystalline silicon. Alternatively, a selective or non-selective silicon deposition process may be performed under conditions that forms polycrystalline silicon. In such embodiments, the passivation layer340may include, and/or may consist essentially of, polysilicon.

The silicon passivation layer340may include undoped silicon. As used herein, undoped silicon refers to silicon without dopants that are intentionally introduced during a deposition process. Thus, the level of electrical dopants in undoped silicon may be present at a residual level. For example, undoped silicon may be intrinsic, or may include electrical dopants at a dopant concentration less than 1.0×1016/cm3, such as from 1.0×1012/cm3to 1.0×1015/cm3. Undoped silicon provides relatively high resistivity and may be effective in suppressing leakage current. Undoped silicon may be grown by a selective deposition process or a non-selective deposition process. In embodiments in which a non-selective deposition process is used, excess portions of the deposited undoped silicon material may be removed from above the horizontal plane including the top surface of the hard mask layer104. Remaining portions of the deposited undoped silicon comprises a silicon passivation layer340. The top surface of the silicon passivation layer340may be within the horizontal plane including the top surface of the hard mask layer104. In embodiments in which undoped silicon is deposited using a selective deposition process, a planarization process may not be necessary. The silicon passivation layer340functions as a silicon-containing capping structure for the germanium-containing well.

Accordingly, an array of detection regions120may be formed in the semiconductor substrate102. In some embodiments, the detection regions120may include materials other than germanium-containing materials for detecting different wavelengths of light. In some embodiments, a pre-cleaning process may be performed to clean the recesses108with Hydrogen Fluoride (HF) or other suitable solution, prior to forming the detection region120. Other suitable pre-clean solutions are within the contemplated scope of disclosure.

Referring toFIGS.1and2I, in operation22, dopants may be implanted into the silicon passivation layer340and the detection region120. For convenience of illustration, the first halogen species110, the second halogen species112, and the diffused first halogen species110D are not shown inFIGS.21-2K. Dopants of a first conductivity type may be implanted into a portion of the silicon passivation layer340and an upper portion of the detection region120, using a first masked ion implantation process. The implanted portion of the silicon passivation layer340comprises a first-conductivity-type silicon region341, and the implanted portion of the detection region120comprises a first-conductivity-type germanium-containing region301. The first-conductivity-type silicon region341and the first-conductivity-type germanium-containing region301may be heavily doped. For example, each of the first-conductivity-type silicon region341and the first-conductivity-type germanium-containing region301may include electrical dopants of the first conductivity type at an atomic concentration in a range from 1.0×1019/cm3to 2.0×1021/cm3.

Dopants of a second conductivity type may be implanted into another portion of the silicon passivation layer340and another upper portion of the detection region120using a second masked ion implantation process. The implanted portion of the silicon passivation layer340comprises a second-conductivity-type silicon region342, and the implanted portion of the detection region120comprises a second-conductivity-type germanium-containing region302. The second-conductivity-type silicon region342and the second-conductivity-type germanium-containing region302may be heavily doped. For example, each of the second-conductivity-type silicon region342and the second-conductivity-type germanium-containing region302may include electrical dopants of the second conductivity type at an atomic concentration in a range from 1.0×1019/cm3to 2.0×1021/cm3.

The remaining portion of the silicon passivation layer340may provide lateral isolation between the first-conductivity-type silicon region341and the second-conductivity-type silicon region342. The un-implanted portion of the detection region120is herein referred to as an intermediate germanium-containing region308. The intermediate germanium-containing region308may be intrinsic or may have a doping with an atomic concentration of dopants in a range from 1.0×1013/cm3to 1.0×1018/cm3. The intermediate germanium-containing region308provides lateral spacing between the first-conductivity-type germanium-containing region301and the second-conductivity-type germanium-containing region302.

Referring toFIGS.1and2J, in operation24, the hard mask layer104may be removed, for example, by performing an isotropic etch process such as a wet etch process, and a first interconnect structure190may be formed on the first semiconductor substrate102. In particular, the first interconnect structure190may include first dielectric material layers192, metal interconnect structures80, and first bonding pads188. The interconnect structure190may include through-substrate via structures504and insulating spacers502that laterally surround the through-substrate via structures504may be formed over the semiconductor substrate102.

Referring toFIGS.1and2K, in operation26, an array of photodetector sensing circuits may be formed. For example, various field effect transistors (610,630,640) may be formed in the second semiconductor substrate202. For example, a transfer transistor610, p-type field effect transistors630, and n-type field effect transistors640may be formed on the second semiconductor substrate202. In the alternative, sensing circuits may be formed on the first semiconductor substrate102.

Each of the field effect transistors (610,630,640) may include a respective gate dielectric50, a respective gate electrode52, a respective gate dielectric50, a respective gate electrode52, and a respective pair of a source region and a drain region. The source regions and the drain regions are collectively referred to as source/drain regions. For example, the p-type field effect transistors630may include p-doped source/drain regions42, and the n-type field effect transistors640may include n-doped source/drain regions44. The transfer transistor610may include a source region48to be electrically connected to the second-conductivity-type germanium-containing region302, and a floating drain region46. The second-conductivity-type germanium-containing region302and the floating drain region46may have a doping of the second conductivity type.

Shallow trench isolation structures20may be formed in an upper portion of the second semiconductor substrate202. The shallow trench isolation structures20may include a dielectric fill material such as silicon oxide, and provide electrical isolation for the field effect transistors (610,630,640). While the present disclosure illustrates only two field effect transistors630,640, it is understood that a full set of field effect transistors for providing a sensing circuit for a subpixel may be formed in the second semiconductor substrate202. The field effect transistors include transistors such as a reset transistor, a source follower transistor, and a select transistor. Any sensing circuit for sensing stored electrical charges in the second-conductivity-type germanium-containing region302may be formed.

In operation28, a second interconnect structure290may be formed on the second semiconductor substrate202. In particular, metal interconnect structures80may be formed within second dielectric material layers292to provide electrical wiring to and from the various semiconductor devices on the second semiconductor substrate202. Second bonding pads288may be formed on the second interconnect structure290.

In operation30, a first wafer including the first semiconductor substrate102and the first interconnect structure190may be bonded to a second wafer including the second semiconductor substrate202and the second interconnect structure290by wafer-to-wafer bonding. For example, the first bonding pads188and be aligned to, and disposed upon, the second bonding pads288, and metal-to-metal bonding may be induced on each mating pair of a first bonding pad188and a second bonding pad288.

Subsequently, the backside of the first semiconductor substrate102may be thinned to physically expose top surfaces of the through-substrate via structures504. A filter layer506may be formed on the backside of the first semiconductor substrate102, and a lens layer508may be formed on the filter layer506. Furthermore, the shape of the lenses of the lens layer508may be concave, convex, planar with surface structure, or other shapes, and should not be limited by the exemplary drawings here.

External bonding pads198may be formed on the through-substrate via structures504. The bonded assembly of the first wafer and the second wafer may be diced to provide bonded semiconductor dies. Each bonded semiconductor die may include a first semiconductor die510including diced portions of the first semiconductor substrate102and the first interconnect structure190, and a second semiconductor die520including diced portions of the second semiconductor substrate202and the second interconnect structure290.

FIG.3is a cross-sectional view of a photodetector600according to various embodiments of the present disclosure that may be formed by bonding the first semiconductor die510and the second semiconductor dies520shown inFIG.2K. Referring toFIGS.2K and3, the photodetector600may be a time-of-flight sensor (TOF), such as a direct time-of-flight (DToF) sensor or an indirect time-of flight (IToF) sensor.

The photodetector600may include a first semiconductor substrate102, a first interconnect structure190, a second interconnect structure290, and a second semiconductor substrate202, as described above. Incoming light that is to be detected by the detection regions120may be focused, collimated, expanded, or processed according to the lens design at the lens layer508. The incoming detected light may then enter the filter layer506. The filter layer506may be configured to pass light having a specific wavelength range. Photodiodes in the second semiconductor substrate202may convert the incident light into free carriers. The transistors (610,630,640) process free carriers received through the metal interconnect structures80and the bonding pads188,288and process the free carriers according to the specific application.

The first semiconductor layer102may include photodetector sensors comprising the Ge detection regions120. However, the first semiconductor layer102may include multiple groups of photodetector sensors for detecting light of different wavelength ranges. For example, a group of photodetector sensors that includes the Ge detection regions120may be configured to detect light of a NIR wavelength range (e.g., 810 nm to 890 nm). Although not shown, the first semiconductor layer102may include photodetector sensors configured to detect light of a blue wavelength range (e.g., 420 nm to 500 nm), a green wavelength range (e.g., 500 nm to 580 nm), and/or a red wavelength range (e.g., 580 nm to 660 nm). The detection regions120of the photodetector sensors may be isolated by insulating sidewall spacers, trenches, or other suitable isolation structures. In some implementations, the groups of photodetector sensors that are configured to detect visible light (e.g., red, green, and blue) may include silicon detection regions, (e.g., may be silicon photodetector sensors).

FIG.4Ais a graph showing halogen concentration with respect to depth in the semiconductor substrate102and the detection region120of the structure ofFIG.2H, andFIG.4Bis a cross-sectional view showing halogen concentration with respect to depth in a comparative semiconductor layer that includes a detection region and was etched using only a first halogen species.

Referring toFIGS.2G,4A, and4B, since the second halogen species112has a larger atomic radius and/or smaller implantation depth, the second halogen species112forms the barrier layer114that reduces diffusion of the first halogen species110into the detection region120. As such, only a relatively small amount of the first halogen species110may diffuse into the detection region120and as diffused halogen species110D.

In contrast, since the comparative semiconductor substrate was not subjected to the second etching process no barrier layer was formed. As such, a relatively large amount of the first halogen species110can diffuse into the Ge-containing detection region formed in the comparative semiconductor layer, since the comparative semiconductor did not include a barrier layer114to limit such diffusion.

In particular, secondary ion mass spectrometry (SIMS) testing has shown that a peak first halogen species (e.g., Cl) atomic concentration of greater than 10 at % may occur when no barrier layer is present around a Ge layer that was grown in a recess formed using only a Cl2-based reactive ion etching process. In contrast, Ge layers formed in a detection region using the present method may have a peak Cl atomic concentration of less than 10 at %, such as less than 5 at %, less than 4 at %, less than 3 at %, or less than 1 at %, based on a total at % of the Ge-containing detection region. Accordingly, the present etching process reduces halogen species diffusion, and allows for the growth of unexpectedly pure Ge regions. In this manner, an improved detection region120of a photodetector sensor that is less susceptible to dark current may be formed.

By etching a recess in the semiconductor substrate102, an increased number of Ge layers may be formed over the semiconductor substrate to form a detection region120of the photodetector substrate. Typically, the recess108may be etched with a first etchant gas that contains a first halogen series110. However, this first etchant process may result in remnants of the first halogen series110implanted into the bottom and side surfaces of the recess108. These implanted first halogen series110particles may subsequently diffuse into the deposited Ge material of the detection region120and contaminate the detection region120. By performing a second etchant process using a second etchant gas that contains a second halogen series112, a barrier layer114of the second halogen series112may be implanted into the bottom and side surfaces of the recess108. This barrier layer114may prevent and/or mitigate the diffusion of the first halogen series110into the subsequently deposited Ge material of the detection region120. In particular, the first etching process and the second etching process may be performed such that a peak concentration of the second halogen species112in the semiconductor layer102occurs closer to the recess108than a peak concentration of the first halogen species110in the semiconductor layer102. In this manner, an improved detection region120of a photodetector sensor that is less susceptible to dark current may be formed.

Referring toFIGS.1-3, various embodiments provide a method of forming a semiconductor device, comprising: forming a patterned hard mask layer104on a semiconductor substrate102; performing a first etching process to form a recess108in an exposed portion of the semiconductor substrate102, using a first etchant comprising a first halogen species110; performing a second etching process using a second etchant comprising a second halogen species112, such that the second halogen species112forms a barrier layer114in the semiconductor substrate102, surrounding the recess108; and growing a detection region120in the recess108using an epitaxial growth process, wherein the barrier layer114is configured to reduce diffusion of the first halogen species110into the detection region120.

In one embodiment, the first halogen species110may have smaller atomic radii than the second halogen species112. In another embodiment, the first halogen species110may have a higher diffusion coefficient with respect to silicon than the second halogen species112. In another embodiment, the semiconductor substrate102comprises Si; and the detection region120comprises single-crystal Ge. In another embodiment, a peak concentration of the first halogen species110in the detection region120may be less than 10 atomic percent (at %). In another embodiment, a peak concentration of the first halogen species110in the detection region120may be less than 5 atomic percent (at %). In another embodiment, the first halogen species110comprise F or Cl; and the second halogen species112comprise Br or I. In another embodiment, the second etching process may be an etching process that does not increase an etching depth of the recess108by more than about 10%, such as more than about 5%. In an embodiment, the first and second etching processes may comprise reactive ion etching processes. In various embodiments, the first etching process and the second etching process are performed such that a peak concentration of the second halogen species in the semiconductor substrate occurs closer to the recess than a peak concentration of the first halogen species in the semiconductor substrate.

In another embodiment, various embodiments provide for a method of forming a photodetector, including the operations of forming a patterned hard mask layer104on a front side of a first semiconductor substrate102; performing a first etching process to form recesses108in exposed portions of the front side of the semiconductor substrate102, using a first etchant comprising a first halogen species110; performing a second etching process using a second etchant comprising a second halogen species112, such that the second halogen species112forms barrier layers114in the semiconductor substrate102, surrounding the recesses108; and growing detection regions120in the recesses108using an epitaxial growth process. The first etching process comprises implanting the first halogen species110in the first silicon substrate102to a first depth, the second etching process comprises implanting the second halogen species112in the first silicon substrate102to a second depth that is less than the first depth, and the first halogen species110has a higher diffusion coefficient with respect to silicon than the second halogen species.

In an embodiment, the detection regions120may comprise single crystal Ge. In one embodiment, the first halogen species110may comprise F or Cl; and the second halogen species112comprise Br. In one embodiment method, the detection regions120may be disposed in an array on the semiconductor substrate102. In one embodiment method, the first halogen species110may have a higher diffusion coefficient with respect to silicon than the second halogen species112. In one embodiment, the first etching process comprises implanting the first halogen species110in the semiconductor substrate102to a first depth; and the second etching process comprises implanting the second halogen species112in the semiconductor substrate102to a second depth that is less than the first depth.

Various embodiments provide a photodetector600comprising: a first semiconductor substrate102; detection regions120comprising epitaxial germanium (Ge) and disposed in recesses108formed in a front side of the first semiconductor substrate102; a first halogen species110implanted in the first semiconductor substrate102around the recesses; barrier layers114surrounding the recesses108and comprising second halogen species112, wherein the barrier layers114are configured to reduce diffusion of the first halogen species110into the detection regions120from the semiconductor substrate102, wherein the first halogen species110has a smaller atomic radius than the second halogen species112. In some embodiments, the photodetector600may also include: a second semiconductor substrate202comprising photodetector sensing circuits (610,630,640); and an interconnect structure (190,290) electrically connecting the detection regions120to the photodetector sensing circuits (610,630,640).

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.