Patent ID: 12205901

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Generally, plasma used in anisotropic etch processes that form openings through a dielectric material layer during semiconductor manufacturing may provide collateral damage to underlying metal interconnect structures and underlying semiconductor devices such as field effect transistors. Among the adverse effects of the plasma damage from anisotropic etch processes include shift in the threshold voltage and the on-current of underlying field effect transistors.

According to an aspect of the present disclosure, plasma damage to underlying semiconductor devices and metal interconnect structures may be reduced or eliminated by physically exposing only metallic compound material portions within underlying metal interconnect structures during formation of an opening through a dielectric material layer. To provide sufficient contact area for a metal interconnect structure to be subsequently formed, stepped metal interconnect structures may be used in the underlying metal interconnect level. The stepped metal interconnect structures may be formed, for example, by forming stepped cavities having respective deep cavity and a respective shallow cavity such that the thickness of the shallow cavity is not greater than the thickness of a metallic compound material to be subsequently deposited. Thus, a laterally-protruding portion of each stepped metal interconnect structure may include a planar top barrier liner segment consisting essentially of a metallic compound material that is resistant to oxidation and provides sufficiently high electrical resistivity to avoid excessive electrical current flow into underlying semiconductor devices during a subsequent anisotropic etch process. The high resistivity of the metallic compound material reduces the antenna effect (i.e., plasma Induced gate oxide damage) during a subsequent reactive ion etch process, and reduces plasma damage during the reactive ion etch process. The various embodiment methods and structures are now described with reference to accompanying figures.

FIG.1is a vertical cross-sectional view of an exemplary structure after formation of complementary metal oxide-semiconductor (CMOS) transistors, metal interconnect structures formed within dielectric material layers, and a connection-via-level dielectric layer according to embodiments of the present disclosure. The exemplary structure may include complementary metal oxide-semiconductor (CMOS) transistors and metal interconnect structures formed in dielectric material layers. Specifically, the exemplary structure may include a substrate9. The substrate9may be a semiconductor substrate such as a commercially available silicon wafer. Shallow cavity isolation structures720including a dielectric material such as silicon oxide may be formed in an upper portion of the substrate9. Suitable doped semiconductor wells, such as p-type wells and n-type wells, may be formed within each area that may be laterally enclosed by a portion of the shallow cavity isolation structures720. Field effect transistors may be formed over the top surface of the substrate9. For example, each field effect transistor may include a source region732, a drain region738, a semiconductor channel735that includes a surface portion of the substrate9extending between the source region732and the drain region738, and a gate structure750. Each gate structure750may include a gate dielectric752, a gate electrode754, a gate cap dielectric758, and a dielectric gate spacer756. A source-side metal semiconductor alloy region742may be formed on each source region732, and a drain-side metal semiconductor alloy region748may be formed on each drain region738. While planar field effect transistors are illustrated in the drawings, embodiments are expressly contemplated herein in which the field effect transistors may additionally or alternatively include fin field effect transistors (FinFET), gate-all-around field effect (GAA FET) transistors, or any other type of field effect transistors (FETs).

The exemplary structure illustrated inFIG.1may include a memory array region100in which an array of memory elements may be subsequently formed (e.g., back-end-of-line (BEOL) devices and elements), and a peripheral region200in which logic devices that support operation of the array of memory elements may be formed. In one embodiment, devices (such as field effect transistors) in the memory array region100may include bottom electrode access transistors that provide access to bottom electrodes of memory cells to be subsequently formed. Top electrode access transistors that provide access to top electrodes of memory cells to be subsequently formed may be formed in the peripheral region200at this processing step. Devices (such as field effect transistors) in the peripheral region200may provide functions that may be needed to operate the array of memory cells to be subsequently formed. Specifically, devices in the peripheral region200may be configured to control the programming operation, the erase operation, and the sensing (read) operation of the array of memory cells. For example, the devices in the peripheral region200may include a sensing circuitry and/or a top electrode bias circuitry. The devices formed on the top surface of the substrate9may include complementary metal oxide-semiconductor (CMOS) transistors and optionally additional semiconductor devices (such as resistors, diodes, capacitors, etc.), and are collectively referred to as CMOS circuitry700.

Various metal interconnect structures formed within dielectric material layers may be subsequently formed over the substrate9and the devices (such as field effect transistors). The dielectric material layers may include, for example, a contact-level dielectric material layer601, a first metal line-level dielectric material layer610, a second line-and-via-level dielectric material layer620, a third line-and-via-level dielectric material layer630, and a fourth line-and-via-level dielectric material layer640. The metal interconnect structures may include device contact via structures612formed in the contact-level dielectric material layer601and contact a respective component of the CMOS circuitry700, first metal line structures618formed in the first metal line-level dielectric material layer610, first metal via structures622formed in a lower portion of the second line-and-via-level dielectric material layer620, second metal line structures628formed in an upper portion of the second line-and-via-level dielectric material layer620, second metal via structures632formed in a lower portion of the third line-and-via-level dielectric material layer630, third metal line structures638formed in an upper portion of the third line-and-via-level dielectric material layer630, third metal via structures642formed in a lower portion of the fourth line-and-via-level dielectric material layer640, and fourth metal line structures648formed in an upper portion of the fourth line-and-via-level dielectric material layer640.

Each of the dielectric material layers (601,610,620,630,640) may include a dielectric material such as undoped silicate glass, a doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (612,618,622,628,632,638,642,648) may include at least one conductive material, which may be a combination of a metallic barrier liner layer (such as a metallic nitride or a metallic carbide) and a metallic fill material. Each metallic barrier liner layer may include TiN, TaN, WN, TiC, TaC, and WC, and each metallic fill material portion may include W, Cu, Co, Ru, Mo, Ta, Ti, alloys thereof, and/or combinations thereof. Other suitable metallic barrier liner and metallic fill materials may be within the contemplated scope of disclosure. In one embodiment, the first metal via structures622and the second metal line structures628may be formed as integrated line and via structures by a dual damascene process, and/or the second metal via structures632and the third metal line structures638may be formed as integrated line and via structures, and/or the third metal via structures642and the fourth metal line structures648may be formed as integrated line and via structures.

In one embodiment, the metallic fill material portions of the metal interconnect structures (612,618,622,628,632,638,642,648) may be based on a metallic element other than aluminum. In one embodiment, the metallic fill material portions of the metal interconnect structures (612,618,622,628,632,638,642,648) may be copper-based. In this embodiment, the metallic fill material portions of the metal interconnect structures (612,618,622,628,632,638,642,648) may include copper at an atomic percentage greater than 50%, which may be greater than 90% and/or may be greater than 98%. Generally, a set of metal interconnect structures (612,618,622,628,632,638,642,648) embedded in dielectric material layers (601,610,620,630) may be formed. The set of metal interconnect structures (612,618,622,628,632,638,642,648) may be based on a metal other than aluminum. In one embodiment, the set of metal interconnect structures (612,618,622,628,632,638,642,648) may be transition-metal based, i.e., based on a transition metal and may include the transition metal at an atomic percentage greater than 50%, such as greater than 90% and/or greater than 98%. For example, the set of metal interconnect structures (612,618,622,628,632,638,642,648) may be copper-based. While the present disclosure is described using an embodiment in which three line-levels are present within transition-metal based metal interconnect structures (612,618,622,628,632,638,642,648), embodiments are expressly contemplated herein in which a lesser number or a greater number of metal interconnect structures (612,618,622,628,632,638,642,648) may be formed prior to formation of aluminum-based metal interconnect structures.

According to an aspect of the present disclosure, a dielectric material layer may be formed over the transition-metal based metal interconnect structures (612,618,622,628,632,638,642,648). This dielectric material layer is herein referred to as a first stepped-interconnect-level dielectric material layer650, or as a first dielectric material layer. In one embodiment, aluminum-based metal interconnect structures may be subsequently formed in the dielectric material layer. In this embodiment, the first stepped-interconnect-level dielectric material layer650is also referred to as a first aluminum-based-interconnect-level dielectric material layer. The first stepped-interconnect-level dielectric material layer650may include a dielectric material such as undoped silicate glass or a doped silicate glass, and may have a thickness in a range from 100 nm to 2,000 nm, such as from 200 nm to 1,000 nm, although lesser and greater thicknesses may also be used. The first stepped-interconnect-level dielectric material layer650may be deposited, for example, by chemical vapor deposition.

While the present disclosure is described using an embodiment in which the first stepped-interconnect-level dielectric material layer650is formed above, and on, the fourth line-and-via-level dielectric material layer640, other embodiments are expressly contemplated herein in which the first stepped-interconnect-level dielectric material layer650is formed at a different level. For example, the first stepped-interconnect-level dielectric material layer650may be formed directly on a top surface of the first metal line-level dielectric material layer610, directly on a top surface of a second line-and-via-level dielectric material layer620, directly on a top surface of a third line-and-via-level dielectric material layer630, directly on a top surface of a fourth line-and-via-level dielectric material layer640, or directly on a top surface of any other line-and-via-level dielectric material layer (not shown) that may be formed over the fourth line-and-via-level dielectric material layer640. Alternatively, the first stepped-interconnect-level dielectric material layer650may be formed on a top surface of any line-level dielectric material layer or on a top surface of any via-level dielectric material layer in embodiments in which such a line-level dielectric material layer or such a via-level dielectric material layer is used.

The first stepped-interconnect-level dielectric material layer650is a dielectric material layer in which first stepped metal interconnect structures are subsequently formed, and as such, is also referred to as a first dielectric material layer. Generally, the set of all dielectric material layers that underlie the first stepped-interconnect-level dielectric material layer650is herein referred to as underlying interconnect-level dielectric material layers. The set of all metal interconnect structures embedded in the underlying interconnect-level dielectric material layers is herein referred to as underlying metal interconnect structures. The first stepped-interconnect-level dielectric material layer650is an interconnect-level dielectric material layer that is formed over the underlying interconnect-level dielectric material layers.

Referring toFIGS.2A-2D, a first photoresist layer11may be applied over the top surface of the first stepped-interconnect-level dielectric material layer650. The first photoresist layer11may be lithographically patterned to form openings within areas in which planar top barrier liner segments of first stepped metal interconnect structures are to be subsequently formed. A first anisotropic etch process may be performed to transfer the pattern of the openings in the first photoresist layer11into a surface region of the first stepped-interconnect-level dielectric material layer650.

Unmasked portions of the first stepped-interconnect-level dielectric material layer650are recessed relative to a horizontal plane including the top surface of the first stepped-interconnect-level dielectric material layer650by a first recess depth. First shallow cavities12may be formed in volumes from which the material of the first stepped-interconnect-level dielectric material layer650is removed. According to an aspect of the present disclosure, the first recess depth is equal to, or is less than the thickness of a first metallic nitride liner to be subsequently deposited. For example, the first recess depth may be in a range from 2 nm to 50 nm, such as from 5 nm to 30 nm, although lesser and greater first recess depths may also be used. Each first shallow cavity12may have a respective horizontal cross-sectional shape of a circle, an ellipse, a rectangle, a rounded rectangle, or any two-dimensional curvilinear shape having a closed periphery. The first photoresist layer11may be subsequently removed, for example, by ashing.

Referring toFIGS.3A-3D, a second photoresist layer13may be applied over the top surface of the first stepped-interconnect-level dielectric material layer650. The second photoresist layer13may be lithographically patterned to form openings within areas that may be adjoined to, and may be laterally offset from, a respective one of the first shallow cavities12, which are filled with a respective remaining portion of the second photoresist layer13. In other words, each area of the openings in the second photoresist layer13may be adjoined to, and may be adjacent to, an area of a respective one of the first shallow cavities12.

A second anisotropic etch process may be performed to transfer the pattern of the openings in the second photoresist layer13through the first stepped-interconnect-level dielectric material layer650. Unmasked portions of the first stepped-interconnect-level dielectric material layer650may be etched during the second anisotropic etch process down to a top surface of a respective one of the underlying metal interconnect structures (such as a respective one of the fourth metal line structures648). First deep cavities14may be formed in volumes from which the material of the first stepped-interconnect-level dielectric material layer650is removed.

According to an aspect of the present disclosure, the each first deep cavity14may be formed adjacent to a respective one of the first shallow cavities12such that a bottom surface of the respective one of the first shallow cavities12is adjoined to a sidewall of each first deep cavity14. A top surface of an underlying metal interconnect structures (such as a fourth metal line structure648) may be physically exposed underneath each first deep cavity14. In one embodiment, an entirety of a bottom surface of a first deep cavity14may be located within, and may be laterally offset inward from, a periphery of an underlying metal interconnect structures (such as a fourth metal line structure648). Each first deep cavity14may have at least one sidewall (such as a plurality of sidewalls) that vertically extends from a bottom surface of the first stepped-interconnect-level dielectric material layer650to a topmost surface of the first stepped-interconnect-level dielectric material layer650, and a sidewall that vertically extends from a bottom surface of the first stepped-interconnect-level dielectric material layer650to a recessed surface of the first stepped-interconnect-level dielectric material layer650that is a bottom surface of a respective one of the first shallow cavities12. The bottom surface of each first deep cavity14may be located at the horizontal plane including the bottom surface of the first stepped-interconnect-level dielectric material layer650, or may be located below the horizontal plane including the bottom surface of the first stepped-interconnect-level dielectric material layer650in embodiments in which top surfaces of the underlying metal interconnect structures (such as a fourth metal line structure648) are collaterally recessed during the second anisotropic etch process. The second photoresist layer13may be subsequently removed, for example, by ashing.

While the present disclosure is described employing an embodiment in which the first shallow cavities12are formed prior to formation of the first deep cavities14, embodiments are expressly contemplated herein in which the first deep cavities14are formed prior to formation of the first shallow cavities12. In other words, the order of the processing steps ofFIGS.2A-2Dand the processing steps ofFIGS.3A-3Dmay be optionally reversed.

Referring toFIGS.4A-4D, the exemplary structure is illustrated after removal of the second photoresist layer13. Each contiguous volume that includes a volume of a first shallow cavity12and a first deep cavity14constitutes a first stepped cavity15. Surfaces of a first stepped cavity15comprises a bottom surface of a first shallow cavity12which is a recessed surface of the first stepped-interconnect-level dielectric material layer650, a bottom surface at which an underlying metal interconnect structure (such as a fourth metal line structure648) may be physically exposed, at least one sidewall (which may comprise a plurality of sidewalls or a single curved sidewall) vertically extending from a respective portion of a bottom periphery of the bottom surface to a top surface of the first stepped-interconnect-level dielectric material layer650, a sidewall vertically extending from a respective portion of the bottom periphery of the bottom surface to an edge of the recessed surface, and at least one recess sidewall vertically extending from a periphery of the recessed surface of the first stepped-interconnect-level dielectric material layer650to a top surface of the first stepped-interconnect-level dielectric material layer650.

In one embodiment, each first shallow cavity12of a first stepped cavity15may have a tab configuration such that the area of the first shallow cavity12is adjoined to an outer periphery of a polygonal shape, a circular shape, or an elliptical shape of the first deep cavity14. In one embodiment, the first deep cavity14of a first stepped cavity15may have a horizontal cross-sectional shape of a rectangle or a rounded rectangle, and the first shallow cavity12of the first stepped cavity15may have a horizontal cross-sectional shape of another rectangle or another rounded rectangle.

Generally, a first stepped cavity15may be formed through the first stepped-interconnect-level dielectric material layer650. The first stepped cavity15comprises a first deep cavity14vertically extending at least from a first horizontal plane HP1including a bottom surface of the first stepped-interconnect-level dielectric material layer650(which is an interconnect-level dielectric material layer) to a second horizontal plane HP2including a top surface of the first stepped-interconnect-level dielectric material layer650, and a first shallow cavity12vertically extending from a third horizontal plane HP3located between the first horizontal plane and the second horizontal plane to the second horizontal plane HP2.

Referring toFIGS.5A-5D, a first metallic barrier liner layer16L and a first metallic fill material layer17L may be sequentially deposited in the first stepped cavities15and over the top surface of the first stepped-interconnect-level dielectric material layer650. According to an aspect of the present disclosure, the thickness of horizontally-extending portions of the first metallic barrier liner layer16L may be the same as, or may be greater than, the vertical distance between the third horizontal plane HP3and the second horizontal plane HP2. Thus, the thickness of horizontally-extending portions of the first metallic barrier liner layer16L may be the same as, or may be greater than, the first recess distance by which bottom surfaces of the first shallow cavities12are vertically recessed relative to the top surface of the first stepped-interconnect-level dielectric material layer650at the processing steps ofFIGS.2A-2D. Thus, the first metallic barrier liner layer16L may fill an entire volume of each first shallow cavity12and a peripheral region of each first deep cavity14.

In one embodiment, the first metallic barrier liner layer16L comprises, and/or consists essentially of, a conductive metallic compound material, at least one refractory metal, or a stack there of. In an illustrative example, the first metallic barrier liner layer16L may comprise, and/or may consist essentially of, a conductive metallic compound material of at least one metal element and at least one non-metal element such as TiN, TaN, WN, TiC, TaC, or WC. Alternatively or additionally, the first metallic barrier liner layer16L may include at least one refractory metal such as tungsten, tantalum, niobium, molybdenum, and rhenium, which may function as an effective diffusion barrier due to a high melting point (which is greater than 2,000 degrees Celsius). Alternatively or additionally, the first metallic barrier liner layer16L may include titanium. The first metallic barrier liner layer16L may be deposited by physical vapor deposition or chemical vapor deposition. The thickness of the first metallic barrier liner layer16L may be in a range from 5 nm to 100 nm, such as from 10 nm to 50 nm, although lesser and greater thicknesses may also be used.

The first metallic fill material layer17L includes a first metallic fill material in remaining volumes of the first deep cavities14and over the first stepped-interconnect-level dielectric material layer650. The first metallic fill material has a different material composition than the first metallic barrier liner layer16L, and may include a metallic material having lesser hardness (for example, as measured by Young's modulus) and a lower melting point than the material of the first metallic barrier liner layer16L. In one embodiment, the first metallic fill material may comprise, and/or may consist essentially of, a material selected from aluminum, an aluminum-containing alloy including aluminum at a weight percentage greater than 90%, copper, a copper-containing alloy including copper at a weight percentage greater than 50%, tungsten, molybdenum, ruthenium, cobalt, nickel, silver, gold, and intermetallic alloys thereof. In one embodiment, the first metallic fill material layer17L may include, and/or may consist essentially of, an aluminum-containing alloy including aluminum at an atomic percentage, which may be in a range from 90% to 100%. In this case, the aluminum-containing alloy may include copper and/or silicon. In one embodiment, the aluminum-containing alloy may be an aluminum-copper alloy, an aluminum-silicon alloy, or an aluminum-copper-silicon alloy. In one embodiment, the atomic percentage may be in a range from 95% to 99.99%, such as from 98% to 99.9% and/or from 99.0% to 99.8%. The thickness of the first metallic fill material layer17L over the top surface of the first metallic barrier liner layer16L may be in a range from 100 nm to 2,000 nm, such as from 200 nm to 1,000 nm, although lesser and greater thicknesses may also be used.

Referring toFIGS.6A-6D, portions of the first metallic fill material of the first metallic fill material layer17L and the material of the first metallic barrier liner layer16L may be removed from above the second horizontal plane HP2by performing a chemical mechanical polishing (CMP) process. The top surface of the first stepped-interconnect-level dielectric material layer650may be used as a stopping surface during the CMP process. Remaining portions of the first metallic fill material layer17L and the first metallic barrier liner layer16L comprise first stepped metal interconnect structures18. Each first stepped metal interconnect structure18includes a combination of a first metallic barrier liner16and a first metallic fill material portion17. Each first metallic barrier liner16comprises a patterned remaining portion of the first metallic barrier liner layer16L. Each first metallic fill material portion17comprises a patterned remaining portion of the first metallic fill material layer17L.

Within each first stepped metal interconnect structure18, each first metallic barrier liner16comprises a planar bottom barrier liner segment16B underlying the first metallic fill material portion17and having a bottom surface located at, or below, the first horizontal plane HP1, sidewall segments16S adjoined to a periphery of the planar bottom barrier liner segment16B and vertically extending to the second horizontal plane HP2, and a planar top barrier liner segment16P adjoined to an outer sidewall of one of the sidewall segments16S, having a top surface located within the second horizontal plane HP2, and laterally extending by a greater lateral distance than a lateral thickness of each of the sidewall segments16S. The planar top barrier liner segment16P has a same thickness as, or has a lesser thickness than, the planar bottom barrier liner segment16B. The difference between the thickness of the planar bottom barrier liner segment16B and the thickness of the planar top barrier liner segment16P may be in a range from 1 nm to 25 nm, such as from 3 nm to 10 nm, although lesser and greater differences may also be employed. In one embodiment, the planar top barrier liner segment16P The thickness of the planar bottom barrier liner segment16B may be in a range from 2 nm to 50 nm, such as from 5 nm to 30 nm, although lesser and greater first recess depths may also be used. The thickness of the planar top barrier liner segment16P may be in a range from 1 nm to 40 nm, such as from 4 nm to 25 nm, although lesser and greater first recess depths may also be used. In one embodiment, the ratio of the thickness of the planar top barrier liner segment16P to the thickness of the planar bottom barrier liner segment16B may be in a range from 0.5 to 1.0, such as from 0.6 to 0.95, and/or from 0.7 to 0.9.

In one embodiment, the first metallic fill material portion17within each first stepped metal interconnect structure18has a different material composition than the first metallic barrier liner16, and comprises a material selected from aluminum, an aluminum-containing alloy including aluminum at a weight percentage greater than 90%, copper, a copper-containing alloy including copper at a weight percentage greater than 50%, tungsten, molybdenum, ruthenium, cobalt, nickel, silver, gold, and intermetallic alloys thereof. In one embodiment, an underlying dielectric material layer (such as a fourth line-and-via-level dielectric material layer640) may contact a bottom surface of the first stepped-interconnect-level dielectric material layer650. A metal interconnect structure (such as a fourth metal line structure648) embedded in the underlying dielectric material layer may contact a bottom surface of the planar bottom barrier liner segment16B of the first stepped metal interconnect structure18(which is also referred to as a first metal interconnect structure).

Referring toFIGS.7A-7D, a second stepped-interconnect-level dielectric material layer660(which is also referred to as a second dielectric material layer) may be formed over the first stepped-interconnect-level dielectric material layer650. In one embodiment aluminum-based metal interconnect structures may be subsequently formed in the dielectric material layer. In this embodiment, the second stepped-interconnect-level dielectric material layer660is also referred to as a second aluminum-based-interconnect-level dielectric material layer. The second stepped-interconnect-level dielectric material layer660may include a dielectric material such as undoped silicate glass or a doped silicate glass, and may have a thickness in a range from 100 nm to 2,000 nm, such as from 200 nm to 1,000 nm, although lesser and greater thicknesses may also be used. The second stepped-interconnect-level dielectric material layer660may be deposited, for example, by chemical vapor deposition.

The processing steps ofFIGS.2A-2D,3A-3D, and4A-4Dmay be performed mutatis mutandis to form second stepped cavities25. Each of the second stepped cavities25may include a respective second shallow cavity22and a second deep cavity24. According to an aspect of the present disclosure, an entirety of the bottom surface of each second deep cavity24may be located within a top surface of a respective one of the first metallic barrier liners16.

The second stepped-interconnect-level dielectric material layer660includes a dielectric material in which second stepped metal interconnect structures are subsequently formed, and as such, is also referred to as a second dielectric material layer. Surfaces of a second stepped cavity25comprises a bottom surface of a second shallow cavity22which may be a recessed surface of the second stepped-interconnect-level dielectric material layer660, a bottom surface at which a planar top barrier liner segment16P of a first metallic barrier liner16is physically exposed, at least one sidewall (which may comprise a plurality of sidewalls or a single curved sidewall) vertically extending from a respective portion of a bottom periphery of the bottom surface to a top surface of the second stepped-interconnect-level dielectric material layer660, a sidewall vertically extending from a respective portion of the bottom periphery of the bottom surface to an edge of the recessed surface, and at least one recess sidewall vertically extending from a periphery of the recessed surface of the second stepped-interconnect-level dielectric material layer660(underlying a second shallow cavity22) to a top surface of the second stepped-interconnect-level dielectric material layer660.

In one embodiment, each second shallow cavity22of a second stepped cavity25may have a tab configuration such that the area of the second shallow cavity22is adjoined to an outer periphery of a polygonal shape, a circular shape, or an elliptical shape of the second deep cavity24. In one embodiment, the second deep cavity24of a second stepped cavity25may have a horizontal cross-sectional shape of a rectangle or a rounded rectangle, and the second shallow cavity22of the second stepped cavity25may have a horizontal cross-sectional shape of another rectangle or another rounded rectangle. Generally, a second stepped cavity25may be formed through the second stepped-interconnect-level dielectric material layer660.

Referring toFIGS.8A-8D, the processing steps ofFIGS.5A-5D and6A-6Dmay be performed mutatis mutandis to form second stepped metal interconnect structure28. For example, a second metallic barrier liner layer and a second metallic fill material layer may be sequentially deposited in the second stepped cavities25and over the top surface of the second stepped-interconnect-level dielectric material layer660. According to an aspect of the present disclosure, the thickness of horizontally-extending portions of the second metallic barrier liner layer may be the same as, or may be greater than, a second recess distance by which bottom surfaces of the second shallow cavities22are vertically recessed relative to the top surface of the second stepped-interconnect-level dielectric material layer660. The second metallic barrier liner layer may comprise, and/or may consist essentially of, any conductive material that may be used for the first metallic barrier liner16. The second metallic fill material layer may comprise, and/or may consist essentially of, any conductive material that may be used for the first metallic fill material layer17L.

Portions of the second metallic fill material layer and the second metallic barrier liner layer may be removed from above the horizontal plane including the top surface of the second stepped-interconnect-level dielectric material layer660by performing a chemical mechanical polishing (CMP) process. The top surface of the second stepped-interconnect-level dielectric material layer660may be used as a stopping surface during the CMP process. Remaining portions of the second metallic fill material layer and the second metallic barrier liner layer comprise second stepped metal interconnect structures28. Each second stepped metal interconnect structure28includes a combination of a second metallic barrier liner26and a second metallic fill material portion27. Each second metallic barrier liner26comprises a patterned remaining portion of the second metallic barrier liner layer. Each second metallic fill material portion27comprises a patterned remaining portion of the second metallic fill material layer.

Generally, an overlying dielectric material layer (such as a second stepped-interconnect-level dielectric material layer660) may be formed over a dielectric material layer (such as the first stepped-interconnect-level dielectric material layer650) embedding first stepped metal interconnect structures18. A second stepped metal interconnect structure28(which may also be referred to as a second metal interconnect structure) may be formed in a cavity in the overlying dielectric material layer on a top surface of the first metal interconnect structure (such as the first stepped metal interconnect structures18) embedded within the dielectric material layer (such as the first stepped-interconnect-level dielectric material layer650). In one embodiment, the second metal interconnect structure contacts a top surface of the planar top barrier liner segment16P of the first stepped metal interconnect structure18, and does not contact the first metallic fill material portion17of the first stepped metal interconnect structure18. In one embodiment, the entirety of a top surface of the first metallic fill material portion17may be in contact with a bottom surface of the overlying dielectric material layer (such as the second stepped-interconnect-level dielectric material layer660).

Referring toFIGS.9A-9D, a pad-level dielectric material layer670may be deposited over the second stepped-interconnect-level dielectric material layer660. Pad-level cavities may be formed through the pad-level dielectric material layer670such that a surface of a planar top barrier liner segment of a second stepped metal interconnect structure28is physically exposed at the bottom of each pad-level cavity through the pad-level dielectric material layer670.

A pad-level metallic barrier liner layer and a pad-level metallic fill material layer may be sequentially deposited in the pad-level cavities and over the top surface of the pad-level dielectric material layer670. The pad-level metallic barrier liner layer may comprise, and/or may consist essentially of, any conductive material that may be used for the first metallic barrier liner16. The pad-level metallic fill material layer may comprise, and/or may consist essentially of, a material selected from aluminum, an aluminum-containing alloy including aluminum at a weight percentage greater than 90%, copper, a copper-containing alloy including copper at a weight percentage greater than 50%, tungsten, molybdenum, ruthenium, cobalt, nickel, silver, gold, and intermetallic alloys thereof. In one embodiment, the pad-level metallic fill material layer may include, and/or may consist essentially of, an aluminum-containing alloy including aluminum at an atomic percentage, which may be in a range from 90% to 100%. In one embodiment, the atomic percentage may be in a range from 95% to 99.99%, such as from 98% to 99.9% and/or rom 99.0% to 99.8%. The thickness of the pad-level metallic fill material layer over the top surface of the pad-level metallic barrier liner layer may be in a range from 500 nm to 5,000 nm, such as from 1,000 nm to 3,000 nm, although lesser and greater thicknesses may also be used.

A photoresist layer (not shown) may be applied over the pad-level metallic fill material layer, and may be lithographically patterned to cover discrete portions of the pad-level metallic fill material layer. An anisotropic etch process may be performed to remove unmasked portions of the pad-level metallic fill material layer and the pad-level metallic barrier liner layer. The pad-level dielectric material layer670may be used as an etch stop layer. Remaining portions of the pad-level metallic fill material layer and the pad-level metallic barrier liner layer comprise bonding pads38, which may be used for wire bonding. A lead wire (not shown) may be subsequently bonded to each of the bonding pads38. Each bonding pad38includes a combination of a pad-level metallic barrier liner36and a pad-level metallic fill material portion37. Each pad-level metallic barrier liner36comprises a patterned remaining portion of the pad-level metallic barrier liner layer. Each pad-level metallic fill material portion37comprises a patterned remaining portion of the pad-level metallic fill material layer.

Generally, an overlying dielectric material layer (such as a pad-level dielectric material layer670) may be formed over a dielectric material layer (such as the second stepped-interconnect-level dielectric material layer660) embedding stepped metal interconnect structures (such as second stepped metal interconnect structures28). A bonding pad38may be formed in, and over, a cavity in the dielectric material layer on a top surface of a stepped metal interconnect structure (such as the second stepped metal interconnect structures28) embedded within the dielectric material layer (such as the second stepped-interconnect-level dielectric material layer660). In one embodiment, the bonding pad38contacts a top surface of the planar top barrier liner segment of the second stepped metal interconnect structure28, and does not contact the second metallic fill material portion of the second stepped metal interconnect structure28. In one embodiment, the entirety of a top surface of the second metallic fill material portion27may be in contact with a bottom surface of the overlying dielectric material layer (such as the pad-level dielectric material layer670).

Referring toFIGS.10A-10D, a first alternative configuration of the exemplary structure is illustrated, which may be derived from the exemplary structure ofFIGS.9A-9Dby omitting the second stepped metal interconnect structure28and the second stepped-interconnect-level dielectric material layer660, and by modifying the layout of the bonding pads38and/or the first stepped metal interconnect structures18such that a bottom surface of each bonding pad38contacts a planar top barrier liner segment16P of a first metallic barrier liner16.

Generally, an overlying dielectric material layer (such as a pad-level dielectric material layer670) may be formed over a dielectric material layer (such as the first stepped-interconnect-level dielectric material layer650) embedding stepped metal interconnect structures (such as the first stepped metal interconnect structures18). A bonding pad38may be formed in, and over, a cavity in the dielectric material layer on a top surface of a stepped metal interconnect structure (such as a first stepped metal interconnect structure18) embedded within the dielectric material layer (such as the first stepped-interconnect-level dielectric material layer650). In one embodiment, the bonding pad38contacts a top surface of the planar top barrier liner segment16P of the first stepped metal interconnect structure18, and does not contact the first metallic fill material portion of the first stepped metal interconnect structure18. In one embodiment, the entirety of a top surface of the first metallic fill material portion17may be in contact with a bottom surface of the overlying dielectric material layer (such as the pad-level dielectric material layer670).

Various layouts may be used for the first stepped metal interconnect structures18and/or for the second stepped metal interconnect structures28. Generally, each shallow cavity (12or22) within a stepped cavity (15or25) is formed adjacent to, and is adjoined to, a respective deep cavity (14or24) such that a shallow cavity (12or22) is connected to a deep cavity (14or24) upon formation of a stepped cavity (15or25). In one embodiment, a pair of first stepped metal interconnect structures18may be formed with a two-fold rotational symmetry around a vertical axis passing through a geometrical center of the pair of first stepped metal interconnect structures18as illustrated inFIG.6A. In this embodiment, each planar top barrier liner segment16P laterally extends from a first metallic fill material portion17toward the other first metallic fill material portion17.

Referring toFIGS.11A-11D, a second alternative configuration of the exemplary structure may be derived from the exemplary structure by arranging multiple first stepped metal interconnect structures18as a one-dimensional periodic array that is repeated along a horizontal direction. In this embodiment, each planar top barrier liner segment16P laterally extends from a first metallic fill material portion17along a same horizontal direction.

In the configurations ofFIGS.9A-9D,10A-10D, and11A-11D, a second metal interconnect structure (such as a second stepped metal interconnect structure28or a bonding pad38) may contact a planar top barrier liner segment16P of the first metal interconnect structure (such as a first stepped metal interconnect structure18). In one embodiment, an outer periphery of a top surface of the first metallic fill material portion17is located within the second horizontal plane, and has a rectangular shape, and an entirety of a bottom surface of the second metal interconnect structure is located outside an area of the rectangular shape, and does not contact any first metallic fill material portion17.

Referring toFIGS.12A-12D, a third alternative configuration of the exemplary structure may be derived from the configuration ofFIGS.9A-9Dor from the configuration ofFIGS.10A-10Dby forming a first shallow cavity12inside a rectangular area. The area of a first deep cavity14may be the complement of the area of the first shallow cavity12within the rectangular area. Thus, the entire area of a first stepped cavity15may be a rectangular area. In one embodiment, the area of the first shallow cavity12may be adjoined to a side of the rectangle that defines the rectangular area of the first stepped cavity15.

In the configuration ofFIGS.12A-12D, an outer periphery of a top surface of the first metallic fill material portion17of a first stepped metal interconnect structure18is located within the second horizontal plane HP2, and has an indented rectangular shape that is derived from a rectangular shape by removing an indentation area that is adjoined to a side of the rectangular shape. An entirety of a bottom surface of the second metal interconnect structure (such as a second stepped metal interconnect structure28or a bonding pad38) is located within the indentation area.

Referring toFIGS.13A-13D, a fourth alternative configuration of the exemplary structure may be derived from the configuration ofFIGS.9A-9Dor from the configuration ofFIGS.10A-10Dby forming a first shallow cavity12such that the area of the first shape cavity straddles a rectangular area. In other words, a portion of the first shallow cavity12may be located within the rectangular area, and another portion of the first shallow cavity12may be located outside the rectangular area. The area of a first deep cavity14may be the complement of the area of the first shallow cavity12within the rectangular area. Thus, the entire area of a first stepped cavity15may be the union of a rectangular area and the area of the first shallow cavity12, and is larger than the rectangular area.

In one embodiment, an outer periphery of a top surface of the first metallic fill material portion17is located within the second horizontal plane HP2, and has an indented rectangular shape that is derived from a rectangular shape by removing an indentation area that is adjoined to a side of the rectangular shape. A second metal interconnect structure (such as a second stepped metal interconnect structure28or a bonding pad38) may be embedded in an overlying dielectric material layer (such as a second stepped-interconnect-level dielectric material layer660or a pad-level dielectric material layer670) and may contact a top surface of the first metallic barrier liner16. An entirety of a top surface the first metallic fill material portion17contacts a bottom surface of the overlying dielectric material layer. A first portion of a bottom surface of the second metal interconnect structure (such as a second stepped metal interconnect structure28or a bonding pad38) is located within the indentation area; and a second portion of the bottom surface of second metal interconnect structure is located outside an area of the rectangular shape and within an area that is adjacent to the indentation area.

Referring toFIG.14, a flowchart illustrates a sequence of processing steps for manufacturing a device structure of the present disclosure. Referring to step1410andFIG.1, underlying interconnect-level dielectric material layers (601,610,620,630,640) embedding underlying metal interconnect structures (612,618,622,628,632,638,642,648) may be formed over a substrate8. Referring to step1420andFIG.1, an interconnect-level dielectric material layer (such as a first stepped-interconnect-level dielectric material layer650) may be formed over the underlying interconnect-level dielectric material layers (601,610,620,630,640). Referring to step1430andFIGS.2A-4D, a stepped cavity (such as a first stepped cavity15) may be formed through the interconnect-level dielectric material layer. The stepped cavity comprises a deep cavity (such as a first deep cavity14) vertically extending from a first horizontal plane HP1including a bottom surface of the interconnect-level dielectric material layer to a second horizontal plane HP2including a top surface of the interconnect-level dielectric material layer and a shallow cavity (such as a first shallow cavity12) vertically extending from a third horizontal plane HP3located between the first horizontal plane HP1and the second horizontal plane HP2to the second horizontal plane HP2.

Referring to step1440andFIGS.5A-5D, a first metallic barrier liner layer16L may be deposited in the stepped cavity. The first metallic barrier liner layer16L fills an entire volume of the shallow cavity and a peripheral region of the deep cavity. Referring to step1450andFIGS.5A-5D, a first metallic fill material (comprising a first metallic fill material layer17L) may be deposited in a remaining volume of the deep cavity. Referring to step1460andFIGS.6A-13D, portions of the first metallic fill material and the first metallic barrier liner layer16L may be removed from above the second horizontal plane HP2by performing a planarization process such as a chemical mechanical polishing process. A first stepped metal interconnect structure18including a first metallic barrier liner16and a first metallic fill material portion17is formed in the stepped cavity. The first metallic barrier liner16includes a remaining portion of the first metallic barrier liner layer16L, and the first metallic fill material portion17includes a remaining portion of the first metallic fill material.

Referring to all drawings and according to various embodiments of the present disclosure, a device structure is provided, which comprises: an interconnect-level dielectric material layer (such as a first stepped-interconnect-level dielectric material layer650) located over a substrate8; and a first metal interconnect structure (such as a first stepped metal interconnect structure18) embedded in the interconnect-level dielectric material layer and comprising a first metallic barrier liner16and a first metallic fill material portion17, wherein the first metallic barrier liner16comprises a planar bottom barrier liner segment16B underlying the first metallic fill material portion17and having a bottom surface located at, or below, a first horizontal plane HP1including a bottom surface of interconnect-level dielectric material layer, sidewall segments16S adjoined to a periphery of the planar bottom barrier liner segment16B and vertically extending to a second horizontal plane HP2including a top surface of the interconnect-level dielectric material layer, and a planar top barrier liner segment16P adjoined to an outer sidewall of one of the sidewall segments16S, having a top surface located within the second horizontal plane HP2, and laterally extending by a greater lateral distance than a lateral thickness of each of the sidewall segments16S. The lateral thickness of a sidewall segment16S refers to a lateral distance between an inner sidewall and an outer sidewall.

In one embodiment, the device structure comprises: an overlying dielectric material layer (such as a second stepped-interconnect-level dielectric material layer660or a pad-level dielectric material layer670) that contacts a top surface of the interconnect-level dielectric material layer (such as the first stepped-interconnect-level dielectric material layer650); and a second metal interconnect structure (such as a second stepped metal interconnect structure28or a bonding pad38) embedded in the overlying dielectric material layer and contacting a top surface of the first metal interconnect structure. In one embodiment, the second metal interconnect structure contacts a top surface of the planar top barrier liner segment16P of the first stepped metal interconnect structure18, and does not contact the first metallic fill material portion17.

In one embodiment, an entirety of a top surface of the first metallic fill material portion17contacts a bottom surface of the overlying dielectric material layer (such as a second stepped metal interconnect structure28or a bonding pad38). In one embodiment, a bottom periphery of the second metal interconnect structure (such as the second stepped metal interconnect structure28or the bonding pad38) is located entirely within, and is laterally spaced inward from, an outer periphery of the first metallic barrier liner16located within the second horizontal plane HP2. Thus, the second metal interconnect structure (such as the second stepped metal interconnect structure28or the bonding pad38) does not contact the interconnect-level dielectric material layer (such as the first stepped-interconnect-level dielectric material layer650). In one embodiment, the bottom periphery of the second metal interconnect structure (such as the second stepped metal interconnect structure28or the bonding pad38) is laterally spaced from a top periphery of an interface between the first metallic barrier liner16and the first metallic fill material portion17located within the second horizontal plane HP2. Thus, the second metal interconnect structure (such as the second stepped metal interconnect structure28or the bonding pad38) does not contact the first metallic fill material portion17.

According to another aspect of the present disclosure, a device structure is provided, which comprises: an interconnect-level dielectric material layer (such as a first stepped-interconnect-level dielectric material layer650) located over a substrate8; and a first metal interconnect structure (such as a first stepped metal interconnect structure18) embedded in the interconnect-level dielectric material layer and comprising a first metallic barrier liner16and a first metallic fill material portion17that is laterally surrounded by the first metallic barrier liner16; an overlying dielectric material layer (such as a second stepped-interconnect-level dielectric material layer660or a pad-level dielectric material layer670) that contacts a top surface of the interconnect-level dielectric material layer; and a second metal interconnect structure (such as a second stepped metal interconnect structure28or a bonding pad38) embedded in the overlying dielectric material layer and contacting a top surface of the first metallic barrier liner16, wherein an entirety of a top surface the first metallic fill material portion17contacts a bottom surface of the overlying dielectric material layer.

In one embodiment, the first metallic barrier liner16comprises a planar bottom barrier liner segment16B underlying the first metallic fill material portion17and having a bottom surface located at, or below, a first horizontal plane HP1including a bottom surface of interconnect-level dielectric material layer, sidewall segments16S adjoined to a periphery of the planar bottom barrier liner segment16B and vertically extending to a second horizontal plane HP2including a top surface of the interconnect-level dielectric material layer, and a planar top barrier liner segment16P adjoined to an outer sidewall of one of the sidewall segments16S, having a top surface located within the second horizontal plane HP2, and laterally extending by a greater lateral distance than a lateral thickness of each of the sidewall segments16S.

In one embodiment, a bottom periphery of the second metal interconnect structure (such as the second stepped metal interconnect structure28or the bonding pad38) is located entirely within, and is laterally spaced inward from, an outer periphery of the first metallic barrier liner16located within the second horizontal plane HP2.

In one embodiment, the first metallic barrier liner16comprises a conductive metallic compound material, at least one refractory metal, or a stack there of; and the first metallic fill material portion17has a different material composition than the first metallic barrier liner16, and comprises a material selected from aluminum, an aluminum-containing alloy including aluminum at a weight percentage greater than 90%, copper, a copper-containing alloy including copper at a weight percentage greater than 50%, tungsten, molybdenum, ruthenium, cobalt, nickel, silver, gold, and intermetallic alloys thereof.

In one embodiment, the device structure comprises: an underlying dielectric material layer (such as a fourth line-and-via-level dielectric material layer640) that contacts a bottom surface of the interconnect-level dielectric material layer; and a third metal interconnect structure (such as a fourth metal line structure648) embedded in the underlying dielectric material layer and contacting a bottom surface of the planar bottom barrier liner segment16B of the first stepped metal interconnect structure18.

The various embodiments of the present disclosure may be used to reduce plasma-induced damage to underlying semiconductor devices (such as field effect transistors701) and to avoid collateral oxidation of metal interconnect structures. Particularly, aluminum, an aluminum-containing alloy, or copper is prone to surface oxidation, and provides high electrical conductivity to induce flow of large electrical current into the underlying semiconductor devices. In contrast, materials for a metallic barrier liner (such as a conductive metallic compound material or at least one refractory metal) is resistant to oxidation. Further, conductive metallic compound materials provide a resistivity that is at least one order of magnitude higher than elemental metals. Thus, physically exposing only the metallic barrier liner and covering a metallic fill material portion of a metal interconnect structure during an anisotropic etch process may protect the underlying semiconductor devices and may suppress oxidation of the metal interconnect structure. Suppression of oxidation may provide lower contact resistance between the metal interconnect structure and an overlying metal interconnect structure that is formed directly on the top surface of the metal interconnect structure. Providing a planar top barrier liner segment16P has the benefit of increasing the area in which only the material of the metallic barrier liner is present, and thus, provides a direct contact on a top surface of the planar top barrier liner segment16P.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.