Patent ID: 12206365

DETAILED DESCRIPTION

The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Embodiments of the disclosure relate to voltage ripple suppression in a transmission circuit. Specifically, the transmission circuit includes a power amplifier circuit configured to amplify a radio frequency (RF) signal based on a modulated voltage, and an envelope tracking (ET) integrated circuit (ETIC) configured to generate and provide the modulated voltage to the power amplifier circuit via a conductive path. Notably, the ETIC and the conductive path can present a large source impedance to the power amplifier circuit, which can cause a ripple in the modulated voltage received by the power amplifier circuit to potentially distort the RF signal. In a conventional approach, the large source impedance may be isolated by a large decoupling capacitor at the expense of increased voltage switching time and battery current drain. In contrast, the ETIC disclosed herein can determine and apply a correction term to the modulated voltage generated by the ETIC to thereby suppress the ripple without requiring the large decoupling capacitor. By eliminating the large decoupling capacitor, the transmission circuit can thus achieve fast voltage switching with lower battery current drain.

FIG.1is a schematic diagram of an exemplary transmission circuit10that can be configured based on various embodiments of the present disclosure to support voltage ripple suppression. The transmission circuit10includes a power amplifier circuit12and an ETIC14. The ETIC14is configured to generate a modulated voltage VCCat an ETIC output16based on a modulated target voltage VTGT. The power amplifier circuit12is configured to receive the modulated voltage VCCat a power amplifier input18. The power amplifier input18is coupled to the ETIC output16via a conductive path20, which can be a conductive trace, as an example. Accordingly, the power amplifier circuit12can be configured to amplify an RF signal22based on the modulated voltage VCC. In a non-limiting example, the modulated target voltage VTGTand the RF signal22can be generated by a transceiver circuit24.

For distinction, the modulated voltage VCCgenerated by the ETIC14at the ETIC output16is hereinafter referred to as “generated modulated voltage VCC.” In contrast, the modulated voltage VCCreceived by the power amplifier circuit12at the power amplifier input18is hereinafter referred to as “received modulated voltage VPA.”

In a non-limiting example, the ETIC14has an inherent ETIC impedance ZETIC, the conductive path20has an inherent trace impedance ZTRACE(e.g., an inductive impedance), and the power amplifier circuit12has an inherent power amplifier impedance ZPA. In this regard, the ETIC14and the conductive path20can collectively present a large source impedance (ZETIC+ZTRACE) to the power amplifier circuit12. The power amplifier circuit12, on the other hand, is configured to operate as a current source to draw a modulated current ICC. As such, the large source impedance (ZETIC+ZTRACE) in conjunction with the modulated current ICCcan cause a ripple in the received modulated voltage VPAto potentially distort the RF signal22.

Conventionally, it may be possible to isolate the large source impedance (ZETIC+ZTRACE) from the power amplifier circuit12, and thereby suppress the ripple in the received modulated voltage VPA, by coupling a decoupling capacitor (not shown) with a large-enough capacitance to the power amplifier input18. However, doing so can cause some obvious issues.
ICC=C*dVCC/dt(Eq. 1)

As shown in equation (Eq. 1), the larger capacitance (C) the decoupling capacitor has, the larger amount of the modulated current ICCwould be needed to change the modulated voltage VCCat a required change rate (dVCC/dt). As a result, the transmission circuit10may cause a negative impact on battery life. On the other hand, if the modulated current ICCis kept at a low level to prolong battery life, the transmission circuit10may have difficulty meeting the required change rate (dVCC/dt). Consequently, the transmission circuit10may not be able to change the modulated voltage VCCbetween orthogonal frequency division multiplexing (OFDM) symbols, especially when the RF signal22is modulated with a higher modulation bandwidth (e.g., >200 NHz). Hence, it is desirable to suppress the ripple in the received modulated voltage VPAwithout employing the large-capacitance decoupling capacitor to thereby improve battery life and enable fast switching of the modulated voltage VCC.

In this regard,FIG.2is a schematic diagram providing an exemplary illustration of the ETIC14inFIG.1, which can be configured according to embodiments of the present disclosure to suppress the ripple in the received modulated voltage VPAwithout requiring the large-capacitance decoupling capacitor. Common elements betweenFIGS.1and2are shown therein with common element numbers and will not be re-described herein.

In an embodiment, the ETIC14includes a voltage modulation circuit26and a control circuit28. The voltage modulation circuit26is configured to generate the modulated voltage VCC(a.k.a. the generated modulated voltage VCC) at the ETIC output16based on the modulated target voltage VTGTand a feedback signal30. As described in various embodiments inFIGS.3to7, the feedback signal30can indicate a selected one of the generated modulated voltage VCCand the received modulated voltage VPA. The control circuit28, which can be a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), as an example, is configured to generate a correction term CTERMbased on a voltage differential ΔV between the generated modulated voltage VCCand the received modulated voltage VPA(ΔV=VCC−VPA). As further described in various embodiments inFIGS.3to7, the control circuit28can apply the correction term CTERMto a selected one of the modulated target voltage VTGTand the feedback signal30to cause the voltage modulation circuit26to modify the generated modulated voltage VCCto thereby suppress the ripple in the received modulated voltage VPA. By suppressing the ripple in the received modulated voltage VPAbased on the correction term CTERM, as opposed to employing the large-capacitance decoupling capacitor, the transmission circuit10can thus improve battery life and enable fast switching of the modulated voltage VCC.

The ETIC14can be configured according to various embodiments of the present disclosure. Specific embodiments of the ETIC14are described now with reference toFIGS.3to7. Common elements betweenFIGS.1to7are shown therein with common element numbers and will not be re-described herein.

FIG.3is a schematic diagram of an exemplary ETIC14A configured according to one embodiment of the present disclosure. The voltage modulation circuit26includes a voltage amplifier32(denoted as “VPA”). In a non-limiting example, the voltage amplifier32can be an operational amplifier (op-amp) having a positive input34P (denoted as “+”) and a negative input34M (denoted as “−”). Herein, the positive input34P is configured to receive the modulated voltage VTGTand the negative input34M is configured to receive the feedback signal30and the correction term CTERM. Accordingly, the voltage amplifier32is configured to generate an initial modulated voltage VAMPbased on the modulated target voltage VTGT, the feedback signal30, the correction term CTERM, and a supply voltage VSUP.

The voltage modulation circuit26also includes an offset capacitor COFF, which is coupled between the voltage amplifier32and the ETIC output16. The offset capacitor COFFis configured to raise the initial modulated voltage VAMPby an offset voltage VOFFto thereby generate the modulated voltage VCC(VCC=VAMP+VOFF) at the ETIC output16. Notably, by providing the offset capacitor COFF, the initial modulated voltage VAMPwill be lower than the modulated voltage VCC. As a result, an output stage of the voltage amplifier32(not shown) can be implemented using a smaller transistor(s) to thereby reduce footprint and improve operating efficiency.

The ETIC14A includes a feedback circuit36coupled between the ETIC output16and the negative input34M. Accordingly, the feedback circuit36is configured to generate the feedback signal30to indicate the generated modulated voltage VCCand provide the feedback signal30to the negative input34M.

In this embodiment, the control circuit28is coupled to the negative input34M via an input circuit38. Accordingly, the control circuit28is configured to generate the correction term CTERMbased on the voltage differential ΔV and provides the correction term CTERMto the input circuit38.

The input circuit38receives the correction term CTERMfrom the control circuit28. Accordingly, the input circuit38can apply the correction term CTERMto the feedback signal30, which indicates the generated modulated voltage VCC, to thereby cause the voltage modulation circuit26to modify the generated modulated voltage VCCto suppress the ripple in the received modulated voltage VPA. In an embodiment, the input circuit38may include a time advance circuit40, which can be a resistor-capacitor (RC) circuit, as an example. The time advance circuit40is configured to provide a time advance in the correction term CTERMbefore applying the correction term CTERMto the feedback signal30. In a non-limiting example, the time advance can be so determined to compensate for a processing delay in the voltage amplifier32.

In a non-limiting example, the control circuit28can generate the correction term CTERMas a function of the voltage differential ΔV, as expressed in equation (Eq. 2) below.
CTERM=−K*ΔV(Eq. 2)

In the equation (Eq. 2), K represents a gain factor, which can be expressed in equation (Eq. 3) below.
K=(1+ZETIC/ZTRACE)/(Z2/Z1)  (Eq. 3)

In the equation (Eq. 3), Z1represents an inherent impedance of the input circuit38and Z2represents an inherent impedance of the feedback circuit36. As a function of the voltage differential ΔV, the correction term CTERMis a voltage correction term. In this regard, the correction term CTERMcan be applied directly to the feedback signal30that indicates the generated voltage VCC.

In an alternative embodiment, the control circuit28may also be configured to generate the correction term CTERMas a current correction term. In this regard,FIG.4is a schematic diagram of an exemplary ETIC14B configured according to another embodiment of the present disclosure.

Herein, the feedback circuit36is also configured to generate the feedback signal30to indicate the generated modulated voltage VCC. The input circuit38, however, is coupled between the negative input34M and a ground (GND). The control circuit28, on the other hand, is coupled directly to the negative input34M and configured to provide the correction term CTERMdirectly to the negative input34M. Herein, the control circuit28is configured to generate the correction term CTERMas a current correction term, as expressed in equation (Eq. 4).
CTERM=−Gm*ΔV(Eq. 4)

In the equation (Eq. 4), Gmrepresents a transconductance that converts the voltage differential ΔV into the current correction term. The transconductance Gmmay be determined based on equation (Eq. 5) below.
Gm=(1+ZETIC/ZTRACE)/Z2(Eq. 5)

Notably, when the current correction term is provided to the negative input34M, the inherent impedance Z1of the input circuit38can cause the current correction term to be converted back to a voltage correction term.

In an embodiment, the voltage amplifier32may generate a sensed current ISENSEto indicate the modulated current ICCbeing sourced or sunk by the voltage amplifier32. The sensed current ISENSEmay be used by a stability circuit42to help improve stability of the correction term CTERMacross a modulation bandwidth of the RF signal22.

Alternative to applying the correction term CTERMto the feedback signal30, it is also possible to apply the correction term CTERMto the modulated voltage VTGT, as described next inFIGS.5and6.

FIG.5is a schematic diagram of an exemplary ETIC14C configured according to another embodiment of the present disclosure. The ETIC14C includes a target voltage circuit44. The target voltage circuit44is configured to receive the modulated target voltage VTGTand the correction term CTERMfrom the control circuit28. Accordingly, the target voltage circuit44modifies the modulated target voltage VTGTbased on the correction term CTERMto generate a modified target voltage V′TGTand provides the modified target voltage V′TGTto the positive input34P to thereby cause the voltage modulation circuit26to modify the generated modulated voltage VCC.

In a non-limiting example, the modified target voltage V′TGTcan be expressed in equation (Eq. 6) below.
V′TGT=VTGT+VCORRECTION(Eq. 6)

In the equation (Eq. 6), VCORRECTIONrepresents a target voltage correction term to be added to the modulated voltage VTGT. Herein, the control circuit28is configured to generate the correction term CTERMas a current correction, as expressed in equation (Eq. 7) below.
CTERM=Gm*ΔV(Eq. 7)

In the equation (Eq. 7), Gmrepresents a transconductance that converts the voltage differential ΔV into the current correction term. In this regard, the target voltage circuit44, which as an inherent impedance Z0, needs to convert the correction term CTERMinto the target voltage correction term VCORRECTIONto be added to the modulated voltage VTGT.

The target voltage circuit44may be replaced by a resistor circuit with the inherent impedance Z0. In this regard,FIG.6is a schematic diagram of an exemplary ETIC14D configured according to another embodiment of the present disclosure.

The ETIC14D includes a resistor circuit45coupled between the positive input34P and the GND. Notably, the resistor circuit45can effectively convert the correction term CTERM, which was generated as the current correction term based on the equation (Eq.7), into the target voltage correction term VCORRECTIONto be added to the modulated voltage VTGT.

Alternative to generating the feedback signal30to indicate the generated modulated voltage VCC, as described inFIGS.3to6, it is also possible to generate the feedback signal30to indicate the received modulated voltage VPA. In this regard,FIG.7is a schematic diagram of an exemplary ETIC14E configured according to another embodiment of the present disclosure.

Herein, the feedback circuit36is configured to generate the feedback signal30to indicate the received modulated voltage VPAat the power amplifier input18. In this regard, the control circuit28can determine the correction term CTERMin accordance with equation (Eq. 8) below.
CTERM=−K*ΔV(Eq. 8)

In the equation (Eq. 8), K represents a gain factor, which can be expressed in equation (Eq. 9) below.
K=[(ZETIC+ZPA)/ZTRACE]*(Z1/Z2)  (Eq. 9)

With reference back toFIG.1, although it is undesirable to couple a large-capacitance decoupling capacitor to the power amplifier input18, it is nevertheless possible to provide a much smaller decoupling capacitor CPAinside the power amplifier circuit12to help provide some level of impedance isolation. As such, the correction term CTERMmay need to take into consideration the possible interaction between the decoupling capacitor CPAand the modulated current ICC. As such, the control circuit28may be configured to add a compensation term to the correction term CTERMto compensate for impact caused by the decoupling capacitor CPA.

In this regard,FIG.8is a schematic diagram providing an exemplary illustration of the control circuit28inFIGS.2to7according to an embodiment of the present disclosure. Common elements betweenFIGS.2to8are shown therein with common element numbers and will not be re-described herein.

The control circuit28includes an op-amp46. The op-amp46includes a positive op-amp input48P and a negative op-amp input48M. The negative op-amp input48M is coupled to the ETIC output16to receive the generated modulated voltage VCC. The positive op-amp input48P is coupled to the power amplifier input18to receive the received modulated voltage VPA. The op-amp46is configured to generate the correction term CTERMas a function of the voltage differential ΔV and output the correction term CTERMvia an op-amp output50. Notably, the op-amp46is configured to generate the correction term CTERMas a voltage correction term. In this regard, the op-amp46may be further configured to include or be coupled to a transconductance stage (not shown) to convert the voltage correction term into a current correction term, as needed.

The control circuit28may further include a compensation circuit52coupled between the positive op-amp input48P and the negative op-amp input48M. In a non-limiting example, the compensation circuit52includes a compensation op-amp54, which includes a positive compensation input56P, a negative compensation input56M, and a compensation output58. The compensation circuit52also includes multiple resistor-capacitor (RC) circuits60(1)-60(4).

The RC circuit60(1) may be provided between the ETIC output16and the negative op-amp input48M. The RC circuits60(2) and60(4) may be provided in series between the power amplifier input18and the positive op-amp input48P. The RC circuit60(3) may be provided between the compensation output58and the negative op-amp input48M. The negative compensation input56M is coupled to the positive op-amp input48P via a capacitor C1and the RC circuits60(2) and60(3). The positive compensation input56P may be coupled to the GND.

In an embodiment, the compensation circuit52is configured to generate a compensation term VCORRin the correction term CTERMto thereby offset a variation in the voltage differential ΔV resulting from the decoupling capacitor CPA. Specifically, the correction term CTERMcan be determined based on a second order transfer function as expressed in equation (Eq. 10) below.
CTERM=−ΔV*(R4/R2)*(1+R2*C2*s)+VPA*(R1*R4*C1*C3*s2)/(1+R3*C3*s)  (Eq. 10)

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.