Patent ID: 12262539

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed features may be in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

FIG.1Ais a cross-sectional view of a 3D-NAND memory device100, andFIG.1Bis a top down view of the 3D-NAND memory device100where the cross-sectional view of the 3D-NAND memory device100inFIG.1Ais obtained from a line A-A′ along a Z-direction (i.e., height direction) of a substrate inFIG.1B. Dashed lines inFIG.1Bindicate a perspective view.

As shown inFIG.1A, the memory device100can have a substrate10made of silicon, a high voltage P-type Well (HVPW)14formed on a top portion of the substrate10, and a deep N-type Well12that is disposed below the HVPW. The HVPW14extends from a top surface of the substrate10and into the substrate with a depth from 0.5 um to 5 um according to the design requirements. The HVPW14can have a top portion and a bottom portion. The top portion (not shown) of the HVPW14is level with the top surface of the substrate10and is doped with boron at a dopant concentration from 10e11 cm−3to 10e14 cm−3. The top portion of the HVPW14forms the array (i.e., memory cell region) P-Well. The array P-Well is also known as ‘active tub’ since voltages are applied to the tub during erasing or programming the memory device. The top portion can also be configured to create bipolar junction transistor (BJT) devices in periphery where control circuits occupy. The bottom portion (not shown) of the HVPW14is formed under the top portion and is doped with phosphorus at a dopant concentration from 10e11 cm−3to 10e14 cm−3. The bottom portion creates a deep ‘N-Tub’ that helps isolate the array P-Well (i.e., the top portion) from the periphery P-Wells. The bottom portion can also be configured to create BJT devices in periphery.

The deep N-type Well12illustrated inFIG.1Acan be doped through a high energy implantation with phosphorus at a dopant concentration from 10e11 cm−3to 10e14 cm−3. The deep N-type Well12is formed under the HVPW14, and extends into the substrate with a depth from 0.1 um 1 um according to design requirements. In some embodiments, the deep N-type Well12can surround the HVPW14to isolate the HVPW14from adjacent components.

Still referring toFIG.1A, the memory device100can also have one or more P+ regions24aand24bformed in the HVPW14. The P+ regions extend from the top surface of the substrate10and into the substrate with a depth from 0.01 um to 0.2 um. The P+ regions can be doped with boron at a dopant concentration from 10e14 cm−3to 10e18 cm−3. In subsequent manufacturing steps, a respective array contact can be formed over each of the P+ regions, and the P+ regions are configured to reduce resistance between the array contacts and the HVPW.

Similarly, one or more N+ regions18and22can be formed in the substrate10. The N+ regions18and22extend from the top surface of the substrate and extend into the substrate with a depth from 0.01 um to 0.2 um. The N+ regions can be doped with phosphorus at a dopant concentration from 10e14 cm−3to 10e18 cm−3. Over the N+ regions, one or more substrate contacts (not shown) can be formed in subsequent manufacturing steps, and the N+ regions are configured to reduce resistance between the substrate contacts and the substrate.

The disclosed memory device100can also include one or more high voltage N-type Wells (HVNW). Each of the N+ regions can be surrounded by a respective high voltage N-type Well (HVNW). For example, the N+ region22is surrounded by a HVNW20, and the N+ region18is surrounded b a HVNW16. The HVNWs can be formed by doping the substrate with phosphorus at a dopant concentration from 10el11 cm−3to 10e14 cm−3. The HVNWs extend from the top surface of the substrate and extend into the substrate10with a depth from 0.1 um to 1 um. The HVNWs are configured to isolate the N+ regions from adjacent components.

Still referring toFIG.1A, a bottom select gate (BSG)62p, one or more dummy BSGs (or bottom dummy word lines, such as62n-62o), a plurality of word lines (e.g.,62d-62m), one or more dummy top select gates (TSGs) (or top dummy word lines, such as62b-62c), and a TSG62aare disposed sequentially over the substrate. In addition, a plurality of insulating layers, such as 17 insulating layers60a-60q, are disposed between the substrate10, the BSG, the dummy BSGs, the word lines, the dummy TSGs and the TSG to separate the substrate10, the BSG, the dummy BSGs, the word lines, the dummy TSGs and the TSG from each other.

In some embodiments, the insulating layers60, the BSG, the dummy BSGs, the word lines, the dummy TSGs and the TSG are alternatively stacked over the substrate10with a staircase configuration in which the TSG62aand a uppermost insulating layer60ahave the smallest length, and the BSG62pand a lowermost insulating layer60qhave the largest length.

It should be understood thatFIG.1Ais merely an exemplary 3D-NAND memory device100, and the 3D-NAND memory device100can include any number of the BSG, the dummy BSG, the word line, the dummy TSG, and the TSG. For example, the 3D-NAND memory device100can have three BSGs, three TSGs, and 64 word lines.

In some embodiments (i.e. Gate-last Formation Technology), the BSG62p, the dummy BSGs62n-62o, the word lines62d-62m, the dummy TSGs62b-62c, and the TSG62aillustrated inFIG.1Aare formed firstly using sacrificial layers (i.e. SiN). The sacrificial layers can be removed and replaced with a high K layer, glue layers and one or more metal layers. The high K layer can be made of aluminum oxide (Al2O3) and/or Hafnium oxide (HfO2) and/or Tantalum oxide (Ta2O5), and/or something of high K (Dielectric Constant). The metal layer can be made of tungsten (W), Cobalt (Co), for example. The word lines can have a thickness in a range from 10 nm to 100 nm, according to requirements of product specification, device operation, manufacturing capabilities, and so on. In an embodiment ofFIG.1, the insulating layers60can be made of SiO2with a thickness from 5 nm to 50 nm.

Still referring toFIG.1A, one or more first dielectric trenches (or first trenches), such as two first trenches26and28, are formed in the one or more BSGs (e.g.,62p) and the one or more dummy BSGs (e.g.,62n-62o). The first trenches26and28extends in an X-direction (i.e., length direction) of the substrate10to separate the BSG62pand the dummy BSGs62n-62olayers into a plurality of sub-BSGs and sub-dummy BSGs, or to say, a plurality of cell strings. For example, three sub-BSGs62p-1,62p-2, and62p-3are included in embodiment shown inFIG.1A. In addition, one or more second dielectric trenches (or second trenches), such as the two second trenches56and58illustrated inFIG.1A, are formed in the one or more TSGs (e.g.,62a) and the one or more dummy TSGs (e.g.,62b-62c). The second trenches also extend in the X-direction (length direction) of the substrate10to separate the TSG62aand dummy TSGs62b-62cinto a plurality of sub-TSGs and sub-dummy TSGs. For example, a sub-TSG62a-1, two sub-dummy TSGs62b-1and62c-1are illustrated inFIG.1A. In some embodiments, the first trenches and the second trenches are optically aligned with each other in a Y-direction (i.e., a width direction, top-down view) of the substrate10and are spaced apart by the plurality of word lines62d-62m. In some embodiments, the first and second trenches can have a CD 50 nm to 150 nm and are filled with SiO2, SiON, SiOCN, or other suitable dielectric materials. In some embodiments, the first trenches26and28can extend into the HVPW14with a depth between 10 nm and 100 nm.

By introducing the first and second trenches into the memory device100, the BSG and TSG are separated into a plurality of sub-BSGs and sub-TSGs. The sub-BSGs and sub-TSGs can divide the memory device100into a plurality of sub-blocks, or to say, a plurality of cell strings. Each of the sub-blocks has a respective sub-BSG and a respective sub-TSG. The each of the sub-blocks can be operated individually through controlling the respective sub-BSG and respective sub-TSG. Correspondingly, the disclosed 3D-NAND memory device100can precisely control a desired sub-block/array region so as to effectively reduce a programming time, a reading time, an erasing time and data transfer time, and significantly improve data storage efficiency.

Still referring toFIG.1A, one or more common source regions (CSRs), such as one common source region52, is formed over the substrate and extend in the X-direction (length direction) of the substrate. The common source region52passes through the BSG62p, the dummy BSGs62n-62o, the plurality of word lines62d-62m, the dummy TSGs62b-62c, the TSG62a, and the plurality of insulating layers60, and is electrically coupled with the substrate10via a doped region54. The common source region52, the first trenches26and28, and the second trenches56and58extend parallel to each other in the X-direction (length direction) of the substrate10. The common source region52can have side portions and a bottom portion to be electrically coupled with the dope region54. A dielectric spacer68is formed along the side portions and in direct contact with the word lines62d-62mand insulating layers60. A conductive layer70is formed along the dielectric spacer68and over the doped region54. The common source region52further includes a top contact64that is formed along the dielectric spacer68and over the conductive layer70. The doped region54can be N-type doped through one or more ion implantation processes. In an embodiment ofFIG.1A, the dielectric spacer68is made of SiO2, the conductive layer70is made of polysilicon, and the top contact64is made of tungsten.

In some embodiments, the common source region52can have a continuous configuration to extend along the X-direction (length direction) of the substrate. In some embodiments, the common source region52can be separated into two or more sub-CSRs. The sub-CSRs are aligned with each other in the X-direction of the substrate.

In the 3D-NAND memory device100, a plurality of channel structures are formed over the substrate10along a Z-direction (or height direction) of the substrate. As shown inFIG.1A, five contact structures30,32,34,36and38are included. Each of the channel structures passes through the BSG, the dummy BSGs, the word lines, the dummy TSGs, the TSG and the insulating layers, and is electrically coupled with the substrate via a respective bottom channel contact that extends into the substrate. For example, a contact structure30is electrically coupled with the substrate via a bottom contact202that is shown inFIG.1C. In addition, each of the channel structures further includes a channel layer206, a tunneling layer208, a charge trapping layer210, and a barrier layer212, which has been shown inFIGS.1C and1Dfor details.

The memory device100can further include a plurality of dummy channel structures that are formed along the Z-direction (height direction) of the substrate. For example, six dummy channel structures40,42,44,46,48, and50are included in the memory device100. In some embodiments, the memory device100can be divided into three regions: Two staircase regions100A and100C and a core region100B. As shown, the staircase regions100A and100C can be arranged on single or both sides of the central core region100B of the memory device100. The staircase regions100A and100C do not include any channel structures, and the core region100B includes the plurality of channel structures. In some embodiments, the dummy channel structures are formed in the staircase regions100A and100C only, and pass through the BSG, the dummy BSGs, the word lines and the insulating layers to extend into the substrate. In other embodiments, the dummy channel structures can be formed in both the staircase regions100A and100C and the core region100B. When the dummy channel structures are formed in the core region100B, the dummy channel structures pass through the TSG, the dummy TSGs, the word lines, the dummy BSGs, and the BSG, and extend into the substrate. The dummy channel structures serve as sustain components to support the staircase regions and/or the core regions when sacrificial word lines are removed. In an embodiment ofFIG.1A, the dummy channel structures are made of SiO2.

FIG.1Bis a top down view of the 3D NAND memory device100in accordance with some embodiments of the disclosure. As shown inFIG.1B, the memory device100can have three common source regions52a-52cthat extend along the X-direction (length direction) of the substrate10. The common source regions52band52C are disposed at two boundaries of the memory device100with a continuous configuration. The common source regions52band52C can serve as common source regions for the memory device100, and further isolate the memory device100from adjacent components. In some embodiments, the memory device100is one of memory cell blocks of a 3D-NAND chip (not shown). The common source regions52band52C accordingly isolate the memory device100(or the memory cell block100) from adjacent memory cell blocks of the 3D-NAND chip. The common source region52ais disposed at a middle position of the memory device100. The common source region52ais separated into two or more sub-CSRs by one or more “H-Cuts”. As shown inFIG.1B, the CRS52ais separated by an H-cut72into two sub-CSRs52a-1and52a-2.

Still referring toFIG.1B, the first trenches26and28, and the second trenches56and58are optionally aligned with each other at the Y direction (width direction) of the substrate10. The first trenches and the second trenches are disposed between two adjacent common source regions. For example, the first trench26and the second trench56are aligned and disposed between a common source region52aand a common source region52b. In addition, the dummy channel structures40,42, and44are positioned at the staircase region100A, and the dummy structures46,48, and50are positioned at the staircase region100C. A plurality of channel structures, such as channel structures30,32, are disposed in the core region100B.

By introducing the first/second trenches, the 3D-NAND memory device100(or memory cell block100) can be divided into a plurality of sub-blocks. For example, three sub-blocks SUB-BLK1-3are formed inFIG.1B. Each sub-block can have a respective sub-BSG and a respective sub-TSG. The sub-BSG is formed by separating the BSG62pinto three sub-BSGs (i.e.,62p-1,62p-2, and62p-3) by the first trenches, and the sub-TSG is formed by separating the TSG62ainto three sub-TSGs by the second trenches. It should be mentioned that the SUB-BLK2can have two portions SUB-BLK2_1and SUB_BLK_2that are electrically connected with each other through the H-Cut72. Accordingly, The SUB-BLK2can have a larger size than the SUB-BLK land SUB-BLK3. Without the introduction of the first/second trenches, the memory device100(or the memory cell block100) has a shared BSG, such as62p, and a shared TSG, such as62a.

It should be understood thatFIG.1Bis merely an exemplary 3D NAND memory device100, and the 3D NAND memory device100can include any number of first trenches or second trenches between two adjacent common source regions. For example, two or more first trenches or two or more second trenches can be disposed between two adjacent common source regions. The 3D NAND memory device100can also include any number of common source regions.

FIG.1C-1is a first cross-sectional view of the channel structure30in the 3D-NAND memory device100, andFIG.1D-1is a first top down view of the channel structure30where the cross-sectional view ofFIG.1C-1is obtained from a line B-B′ along a Z-direction (height direction) of a substrate inFIG.1D-1.FIG.1C-2is a second cross-sectional view of the channel structure30andFIG.1D-2is a second top down view where the cross-sectional view ofFIG.1C-2is obtained from a line C-C′ along a Z-direction (height direction) of a substrate inFIG.1D-2.

As shown inFIGS.1C-1/1D-1, the channel structure30can have a cylindrical shape with sidewalls and a bottom region. Of course, other shapes are possible. The channel structure30is formed along a Z-direction perpendicular to the substrate10, and electrically coupled with the substrate10via a bottom channel contact202that is positioned at the bottom region of the channel structure. The channel structure30further includes a channel layer206, a tunneling layer208, a charge trapping layer210, and a barrier layer212. The barrier layer212is formed along the sidewalls of the channel structure30and over bottom channel contact202. The barrier layer212is in direct contact with the word lines62d-62mand the insulating layers60. The charge trapping layer210is formed along the barrier layer212and over the bottom channel contact202, and the tunneling layer208is formed along the charge trapping layer210and over the bottom channel contact202. The channel layer206has side portions that is formed along the tunneling layer208and has a T-shape bottom portion that extends through bottom portions of the tunneling layer208, the charge trapping layer210, and the barrier layer212that are positioned over the bottom channel contact202. The T-shape bottom portion of the channel layer206further is positioned over the bottom contact206and is in direct contact with the bottom channel contact202. In addition, the tunneling layer208, the charge trapping layer210, and the barrier layer212can form an “L-foot” configuration in the channel structure30. The L-foot configuration can include side portions that are formed along the sidewalls of the channel structure and a bottom portion over the bottom channel contact202.

The channel structure30can also have a channel insulating layer204that is formed along the channel layer206to fill the channel structure30. The channel insulating layer204can have a T-shape bottom portion that extends through bottom portions of the channel layer206, the tunneling layer208, the charge trapping layer210, and the barrier layer212and lands on the channel layer206. In some embodiments, the channel insulating layer204can include a void that is positioned in a middle position of the channel insulating layer204. The channel structure30can further include a top channel contact214that is formed along the channel insulating layer204and in direct contact with the channel layer206. The top channel contact214is positioned above the TSG62ato prevent any electrical interference between the top channel contact214and the TSG62a. In the channel structure30, a gate dielectric layer216is further formed between the BSG62pand the bottom channel contact202. The gate dielectric layer216can be positioned between the insulating layer60pand60q, and have an annular shape to surround the bottom channel contact202.

In an embodiment ofFIGS.1C-1/1D-1, the barrier layer212is made of SiO2. In another embodiment, the barrier layer212can include multiple layers, such as SiO2and Al2O3. In an embodiment ofFIGS.1C-1/1D-1, the charge trapping layer210is made of SiN. In another embodiment, the charge trapping layer210can include a multi-layer configuration, such as a SiN/SiON/SiN multi-layer configuration. In some embodiments, the tunneling layer208can include a multi-layer configuration, such as a SiO/SiON/SiO multi-layer configuration. In an embodiment ofFIGS.1C-1/1D-1, the channel layer206is made of polysilicon via a furnace low pressure chemical vapor deposition (CVD) process. The channel insulating layer204can be made of SiO2, and the top and bottom channel contacts can be made of polysilicon.

As shown inFIGS.1C-1/1D-1, the channel structure30can have a cylindrical shape. However, the present disclosure is not limited thereto, and the channel structures30may be formed in other shapes, such as a square pillar-shape, an oval pillar-shape, or any other suitable shapes.

FIGS.1C-2/1D-2provides another configuration to dispose the top channel contact214in the channel structure30. As shown inFIGS.1C-2/1D-2, the top channel contact214is formed along the insulating layer60aand over the channel layer206, tunneling layer208, charge trapping layer210, barrier layer212, and channel insulating layer204. A bottom surface of the top channel contact214is in direct contact with a top surface of the channel layer206. Comparing to the top channel contact214inFIGS.1C-1/1D-1, the top channel contact214inFIGS.1C-2/1D-2has a larger size which in turn provides a bigger process window to dispose a subsequently formed Via over the top channel contact.

FIG.1Eis an equivalent circuit diagram of a 3D NAND memory device, in accordance with exemplary embodiments of the disclosure. As shown inFIG.1E, the circuit diagram includes a memory cell block200or memory cell array200. The memory cell block200can include a plurality of vertical NAND memory cell strings ST0-ST17. Each of the memory cell strings can have one or more bottom select transistors (BSTs), one or more dummy BSTs (DUMBSTs), a plurality of memory cells (MCs), one or more dummy top select transistors (DUMTSTs), and one or more TSTs. For example, a memory cell string ST0can have a BST, two dummy BSTs (DUMBST0and DUMBSTn), 64 memory cells MC0-MC63, two dummy TSTs (DUMTST0and DUMTSTn), and two TSTs (TST0and TSTn). A top end of each of the memory cell strings can be a drain region that is connected to a bit line (BL), and a bottom end of each of the memory cell strings can be a source region that is connected to a common source line (CSL). For example, the memory cell string ST0is connected to a bit line BL1through the drain region of the TSTn and is connected to a CSL through the source region of the BST.

The memory cell block200can be divided into six sub-blocks from SUB-BLK0to SUB-BLK5by the first and second trenches that are illustrated inFIG.1A. Each of the sub-blocks can have a respective set of memory cell strings. For example, SUB-BLK0can include a set of memory cell strings ST0, ST6and ST12, and SUB-BLK1can include another set of memory cell strings ST1, ST7and ST13.

In a related memory cell block, such as a memory cell block400shown inFIG.3B, a bottom select gate (BSG) of each of the memory cell strings are connected to each other and shared. Similarly, a dummy BSG of each of the memory cell strings is also connected to each other and shared. In the memory cell block200, the bottom select gate BSG and the dummy BSGs (e.g., DUMBSG0and DUMBSGn) can be separated into a plurality of sub-BSGs and sub-dummy BSGs by the first trenches, such as26and28illustrated inFIG.1A. For example, the BSG can be separated by the first trenches into a plurality of sub-BSGs from BSG0to BSG5. In addition, the top select gates TSGs (e.g., TSG0and TSGn), and the dummy TSGs (e.g., DUMTSG and DUMTSGn) can be separated into a plurality of sub-TSGs and sub-dummy TSGs by the second trenches, such as56and58illustrated inFIG.1A. For example, the TSG0can be separated by the second trenches into a plurality of sub-TSGs from TSG0-0to TSG0-5.

Accordingly, the BSTs, the dummy BSTs, the dummy TSTs, and the TSTs in each of the sub-blocks can have respective control gates that are sub-BSGs, sub-dummy BSGs, sub-dummy TSGs and sub-TSGs respectively. For example, in SUB-BLK0, the BSTs of the strings ST0, ST6and ST12have an individual control gate of BSG0that is formed by the first trenches to separate the control gate BSG, and the TST0sof the strings ST0, ST6, ST12have an individual control gate of TSG0-0that is formed by the second trenches to separate the control gate TSG. Similarly, in SUB-BLK1, the BSTs of ST1, ST7and ST13have a control gate of BSG1and the TST0sof ST1, ST7and ST13have a control gate of TSG0-1. Without the introduction of the first/second trenches, the memory cell block200has shared BSG, dummy BSGs, dummy TSGs, and TSG. An exemplary shared BSG is illustrated inFIGS.3A and3Bwhere the BSG of each of the memory cell strings are connected to each other and shared.

By introducing such a divided BSG structure, the disclosed 3D-NAND memory device can effectively reduce parasitic capacitance and coupling effects between the BSG and adjacent dielectric layers, and significantly improve Vtperformance of the bottom select transistors (BSTs). In addition, the divided BSG structure allows erasing a specific sub-block rather than the entire block200. Accordingly, the erasing time and data transfer time could be reduced significantly, and data storage efficiency can be improved as well. Further, the divided TSG structure allows reading/programming a specific sub-block rather than the entire block200, which in turn reduces the reading/programming time and improves the data transfer/storage efficiency.

In the memory cell block200, the sub-blocks can share one or more word lines. For example, as shown inFIG.1E, 18 MCns in six sub-blocks are connected to each other and have a common/shared word line WLn. Similarly, other MCs in all six sub-blocks can also have common/shared word lines.

The each of the sub-blocks can have one or more bit line connections. For example, in sub-block SUB-BLK0, the memory cell string ST0is connected to BL1, the memory cell string ST6is connected to BL2, and the memory cell string ST12is connected to BLn. In the disclosed memory cell block200, all the 18 memory cell strings are connected to a same CSL (or common source region).

Still referring toFIG.1E, each of the memory cell strings can be constituted by one or more sub-BSGs, one or more sub-dummy BSGs, a plurality of word lines, one or more sub-dummy TSGs, one or more sub-TSGs, and a channel structure that pass through the sub-TSGs, sub-dummy TSGs, word lines, sub-dummy BSGs, and sub-BSGs, and is electrically coupled to a substrate/a same common source region (i.e., CSL). For example, a memory cell string ST0can be constituted by a channel structure30, a sub-BSG62p-1(i.e., BSG0inFIG.1E), two sub-dummy BSGs62n-1and62o-1, word lines62d-62m, two sub-dummy TSGs62b-1and62c-1, and a sub-TSG62a-1(i.e., TSG0-1inFIG.1E), which are illustrated inFIG.1A. It should be noted that the TSGn is not illustrated inFIG.1A. Accordingly, the bottom select transistor (BST) of the string ST0can be constituted by the channel structure30and the sub-BSG62p-1. A memory cell, such as MC63can be constituted by the channel structure30and the world line62d. The top select transistor TST0can be formed by the channel structure30and the sub-TSG62a-1. The DUMSTST0can be formed by the channel structure30and the sub-dummy TSG62c-1. The common source line (CSL) illustrated inFIG.1Ecan be the common source region52illustrated inFIG.1A.

FIG.2is a schematic perspective view of a 3D NAND memory device, in accordance with exemplary embodiments of the disclosure. As shown inFIG.2, a plurality of dummy channel structures, such as40,42,44,46,48, and50are disposed in the staircase regions. A plurality of channel structures, such as30and38, are positioned in the core region. Two first trenches (26and28) and two second trenches (56and58) are formed along the X-direction, aligned at the Y-direction, and spaced apart from each other by a plurality of word lines62d-62m. The first trenches separate the BSG62p, the dummy BSGs (62nand62o) into a plurality of sub-BSGs and a plurality of sub-dummy BSGs respectively. For example, three sub-BSGs62p-1,62p-2, and62p-3are included in embodiment shown inFIG.2. Similarly, the second trenches separate the TSG62a, the dummy TSGs (62band62c) into a plurality of sub-TSGs and a plurality of sub-dummy TSGs respective. A plurality of insulating layers60a-60qare formed between the substrate, the BSG, the dummy BSGs, the word lines, the dummy TSGs, and the TSG. A common source region52is formed along the X-direction and disposed with the first and second trenches in parallel. The common source region52passes through the TSG, the dummy TSGs, the word lines, the dummy BSGs, and the BSG, and extends into the substrate10. The common source region52is separated by the H-Cut72into two sub common source regions.

FIG.3Ais a cross-sectional view of a related 3D NAND memory device300that is obtained along a Z-direction (height direction) of a substrate. Comparing to the memory device100, the related memory device300does not include the first trenches, such as26and28that are illustrated inFIG.1A.

FIG.3Billustrates an equivalent circuit diagram of the related 3D NAND memory device300. As shown inFIG.3B, the circuit diagram includes a memory cell block or memory cell array400. The memory cell block400can include six sub-blocks from SUB-BLK0to SUB-BLK5by the second trenches, such as56and58inFIG.3A. Similar to the memory device100, the top select gates TSGs (e.g., TSG0and TSGn), and the dummy TSGs (e.g., DUMTSG0and DUMTSGn) can be separated into a plurality of sub-TSGs and sub-dummy TSGs by the second trenches. For example, the TSG0can be separated by the second trenches into a plurality of sub-TSGs from TSG0-0to TSG0-5. Accordingly, each of the sub-blocks can have respective sub-TSGs and respective sub-dummy TSGs. For example, a sub-block SUB-BLK0can have a sub-TSG TSG0-0, and a sub-block SUB-BLK1can have a sub-TSG TSG0-1. The difference between the related memory device300and the disclosed memory device100is that in the related memory device300, the BSG or dummy BSGs (e.g., DUMBSG0and DUMBSGn) in each of the sub-blocks are connected to each other and shared.

FIG.4Ais a schematic diagram of an operation parameter to erase a related 3D NAND memory device300, in accordance with exemplary embodiments of the disclosure.FIG.4Bis a schematic diagram of another operation parameter to erase a 3D-NAND memory device100, in accordance with exemplary embodiments of the disclosure.

As shown inFIG.4A, during erasing the related 3D-NAND memory device300, the word lines that control the memory cells (MCs) are set to an operating voltage equal to zero volt (V). An input voltage applied to the HVPW, such as the HVPW14inFIG.3A, can be set to a first operating voltage V1. The first operating voltage V1can be positive and have a value between 18 V and 22 V. An input voltage to a selected BSG of a specific sub-block, such as SUB-BLK0inFIG.3B, can be set to a second operating voltage V2that can be lower than the first operating voltage but still positive. For example, the second operating voltage V2can be in a range from zero volt to 13 V. In addition, the dummy BSGs in the specific sub-block can be set to a switch voltage (not shown inFIG.4A) that is 0.5 V-2 V lower than the second operating voltage V2. In some embodiments, the selected BSG and the selected dummy BSGs in the specific sub-block can be set to float.

A detailed erasing process can be described base on the channel structure30that is illustrated inFIGS.1C and1Dand the memory cell string ST0/sub-block SUB-BLK0that is illustrated inFIGS.1E and3B. It should be mentioned again, the memory cell string ST0can be constituted by the channel structure30and the surrounding BSG, dummy BSGs, word lines, dummy TSGs, and TSG that are illustrated inFIGS.1C and1D.

As shown inFIGS.1C and1D, when the first operating voltage is applied to the HVPW14, the first operating voltage V1is electrically coupled to the channel layer206via the bottom channel contact202. Because the word lines62d-62mare all set to an operating voltage equal to zero volt, the channel layer206forms a relatively high electric potential with respect to the word lines. The formed high electric potential attracts the electrons that are trapped in the trapping layer210back to the channel layer206. In addition, holes can be injected into the channel layer by the first operating voltage V1from the HVPW14/common source region52. The injected holes can sustain a positive potential in the channel layer and further recombine with the attracted electrons in the channel layer206. When the electron-hole recombination is completed, the memory cell string ST0is erased. Accordingly, the input voltages V1, V2are set to zero volt.

During the easing operation, the selected BSG is either set to float or set to the second operating voltage V2that allows the selected BSG to stay at a positive voltage relatively lower than the first voltage V1that is applied to the HVPW14. Such a relative lower voltage can reduce the electric filed across the gate dielectric (e.g., gate dielectric layer216shown inFIG.1C) and the reduced electric field in turn can prevent the gate dielectric layer from breaking down. In some embodiments, the second voltage V2applied to the selected BSG can further help generate hole through a gate induced drain leak (GIDL) effect and improve the holes to flow from the substrate to a top portion of the channel layer206(e.g., a position close to the TSG).

In some embodiments, the dummy BSGs are either set to float or set to the switch voltages (not shown). The applied switch voltages can be reduced gradually in the direction from BSG62ptoward word line62m. A gradual reduction in the voltage on dummy BSGs in the direction from BSG toward word lines may reduce the electric field between the BSG (set at a high voltage) and word lines (set at a low voltage, such as zero), hence reducing carrier generation between BSG and word lines and eliminating erase disturb.

Since the related memory device300has a common or shared BSG, when the second voltage V2is applied to the BSG of string ST0/SUB-BLK0during the easing operation, the bottom select transistors (BSTs) in rest of 17 memory cell strings ST1-ST17can also be affected and turned on by the second operating voltage V2. Correspondingly, the erasing operation can take place in all six sub-blocks. As the 3D-NAND memory device migrates to higher capacity with an increasing block size, the common/shared BSG can induce longer erasing time, longer data transfer time, and lower storage efficiency.

FIG.4Bis a schematic diagram of another operation parameter to erase a 3D NAND memory device100. As shown inFIG.1E, each of the sub-blocks illustrated inFIG.1Ecan have a respective sub-BSG that is formed by introducing the first trenches to separate the BSG. When an erasing operation is started, the second voltage V2can be applied to a respective sub-BSG of a selected sub block. For example, if the SUB-BLK0is selected, the second voltage V2can be applied to the corresponding sub-BSG BSG0. In addition, a third voltage V3can be applied to a respective sub-BSG of an un-selected sub block. For example, if the SUB-BLK1is un-selected, the third voltage V3can be applied to the corresponding sub-BSG BSG1. The third voltage V3can be close to the first voltage V1and higher than the second voltage V2. For example, the V3can be ranged from 18 V to 25 V. The relative higher third voltage V3with respect to the second voltage V2can repeal the holes that are generated from the HVPW/substrate and inhibiting the holes from flowing into the channel layer of the un-selected sub-block. Accordingly, the erasing process can take place in the selected sub-block only, and the erasing time and data transfer time could be reduced significantly, and data storage efficiency can be improved as well.

FIGS.5A through11Dare cross-sectional and top down views of various intermediary steps of manufacturing a 3D-NAND memory device100in accordance with exemplary embodiments of the disclosure.

FIG.5Ais a cross-sectional view that is obtained along a Z-direction (i.e., height direction) of a substrate. As shown inFIG.5A, a plurality of doped regions12,14,16,18,20,22, and24are formed in a substrate10based on a photolithography process and a doping and/or ions implantation process. The doped regions inFIG.5Amay be substantially similar to the doped regions discussed above with reference toFIG.1A. In order to form the doped regions, a patterned mask can be formed over the substrate by the photolithography process. The patterned mask exposes desired regions of the substrate that need dopant. A doping process, such as an ion implantation process, an in situ doped epitaxial growth, a plasma doping process (PLAD), or other methods as known in the art, can be applied to transfer suitable dopant into the exposed regions of the substrate10. A dopant concentration, a doping profile, and a doping depth can be controlled by adjusting the energy, angle and dopant type of the doping process.

Over the substrate10, a bottom select gate (BSG)62p, two dummy BSGs62n-62o, and a plurality of first insulating layers62n-62qcan be subsequently formed. The substrate10, BSG62pand the dummy BSGs62n-62oare spaced apart from each other by the first insulating layers60n-60q.

The BSG62pand the two dummy BSGs62n-62ocan be sacrificial layers that are made of SiN. The sacrificial layers can be removed and replaced with a high K layer and a metal layer in future manufacturing steps. The BSG62pand the two dummy BSGs62n-62ocan have a thickness in a range from 10 nm to 100 nm. The first insulating layer can include SiO, SiCN, SiOCN, or other suitable materials. The first insulating layers60n-60qcan have a thickness from 5 nm to 50 nm. Any suitable deposition process can be applied to form the BSG, the dummy BSGs and the first insulating layers, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), diffusion, or any combination thereof.

Still referring toFIG.5A, two first trenches26and28can be formed in the BSG62pand dummy BSGs62n-62owhen the BSG, dummy BSGs and the first insulating layers are stacked over the substrate10. The first trenches26and28extends in a X-direction (i.e., a length direction) of the substrate10to separate the BSG62pand the dummy BSGs62n-62ointo a plurality of sub-BSGs and sub-dummy BSGs. For example, three sub-BSGs62p-1to62p-3, and three sub-dummy BSGs62n-1to62n-3are included inFIG.5A.

The first trenches26and28can have a CD from 50 nm to 150 nm. The first trenches can be filled with SiO2, SiON, SiOCN, or other suitable dielectric materials. In some embodiments, the first trenches26and28can extend into the HVPW14with a depth between 10 nm and 100 nm. The first trenches can be formed by a photolithography process, a subsequent etching process, filling with dielectric materials then CMP (Chemical Mechanical Polish) when necessary. For example, a patterned mask stack can be formed over the insulating layer60nby the photolithography process. A subsequent etching processing can be introduced to etch through the insulating layers, the BSG, the dummy BSGs and further extend into the HVPW14to form two trench openings. The trench openings then can be filled with a dielectric material, such as SiO2, SiON, SiOCN, or other suitable materials by applying a chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), diffusion, or any combination thereof. A surface planarization may be performed to remove any excessive dielectric materials over the insulating layer60n.

FIG.5Bis cross-sectional view that is obtained along an X-direction (a length direction) of the substrate, andFIG.5Cis a top down view to illustrate a final structure when the first trenches26and28are formed. As shown inFIG.5B, the first trenches26and28cannot be observed when the cross-sectional view is made along the X-direction (length direction) of the substrate10. InFIG.5C, the insulating layer60nis shown as a top surface and the two first trenches26and28extend along the length direction of the substrate and further separate the substrate10into three equal regions.

InFIG.6, a plurality of word lines62d-62m, two dummy top select gates (TSGs)62b-62c, and a TSG62aare sequentially formed on the first insulating layer60n. A plurality of second insulating layers60a-60mare also deposited over the first insulating layer60n. The world lines62d-62m, the dummy TSGs62b-62c, and the TSG62aare spaced apart from each other by the second insulating layers60a-60m. The world lines62d-62m, the dummy TSGs62b-62c, and the TSG62acan be sacrificial layers that are made of SiN and have a thickness in a range from 10 nm to 100 nm. The sacrificial layers can be removed and replaced with a high K layer and a metal layer in the future manufacturing steps. The second insulating layers60a-60mcan have a thickness between 5 nm and 50 nm, and include SiO2, SiCN, SiOCN, or other suitable materials. Any suitable deposition process can be applied to form the TSG, the dummy TSGs and the second insulating layers, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), diffusion, or any combination thereof.

InFIG.7A, two staircase regions100A and100C are formed. The formation of the two staircase regions100A and100C can be illustrated in exemplary manufacturing steps that are shown inFIGS.7B-7F. As shown inFIG.7B, a plurality of word sacrificial lines62a-62cand a plurality of insulating layers60a-60ccan be formed and disposed alternatively. A patterned mask stack702can be formed on the insulating layer60a. The patterned mask stack702exposes two end portions of the insulating layer60a. The mask stack702can include an amorphous carbon hard-mask layer, a dielectric anti-reflective coating (DARC), a bottom anti-reflective coating (BARC) layer, and a photoresist layer. In some other embodiments, the mask stack702can be only photoresist for staircase formation. The mask stack702can be patterned according to any suitable technique, such as a lithography process (e.g., photolithography or e-beam lithography) which may further include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), and the like.

InFIG.7C, a first plasma etching process can be performed to remove the exposed end portions of the insulating layer60a. The first plasma etching process further removes portions of underlying word line62athat are not protected by the mask stack702and stops on the insulating layer60bby a precise process control. InFIG.7D, a trim process can be applied to remove portions of the mask stack702from two ends to expose the insulating layer60afurther. The exposed portions of the insulating layer60acan be two end portions60a-A and60a-B. In addition, the insulating layer60bcan have exposed end portions60b-A and60b-B.

InFIG.7E, a second etching process can be performed. The second etching process can remove the exposed end portions60a-A and60a-B from insulation layer60a. By precisely controlling the second etching process either through an etching time or end point traces, the second etching process further removes portions of word line62aunder the60a-A and60a-B and stops on the insulating layer60b. In the meanwhile, the exposed end portions60b-A and60b-B from insulating layer60band portions of word line62bunder the60b-A and60b-B can be removed simultaneously. Upon the completion of the second etching process, two staircase regions can be formed at two sides. InFIG.7F, a subsequent plasma ashing can be applied to remove the remaining mask stack702. Briefly, a multi-cycle Trim-Etch process on multiple masks (As illustrated inFIGS.7B-7F) can be applied to form the staircase100A and100C inFIG.7A.

InFIG.8A, two second trenches56and58can be formed in the TSG62aand dummy TSGs62b-62c. The second trenches56and58extend in the X-direction (i.e., a length direction) of the substrate10to separate the TSG62aand the dummy TSGs62b-62cinto a plurality of sub-BSGs, and a plurality of sub-dummy BSGs respectively. For example, three sub-BSGs62a-1,62a-2, and62a-3can be included inFIG.8A. In some embodiments, the second trenches56and58can be aligned with the first trenches26and28in the Y-direction (width direction) of the substrate.

The second trenches56and58can have a CD 50 nm to 150 nm and include SiO2, SiON, SiOCN, or other suitable dielectric materials. The second trenches can be formed by a photolithography process and a subsequent etching process. For example, a patterned mask stack can be formed over the insulating layer60abased on the photolithography process. The subsequent etching processing is introduced to etch through the insulating layers60a-60d, the TSG62a, the dummy BSGs62b-62cand stop on the word line62dto form two trench openings. The trench openings then can be filled with a dielectric material, such as SiO2, SiON, SiOCN, or other suitable materials by applying a chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), diffusion, or any combination thereof. A surface planarization, such as a CMP process, can be performed to remove any excessive dielectric materials over the insulating layer60a. After the surface planarization, the dielectric material that remains in the trench openings forms the second trenches.

FIG.8Bis cross-sectional view that is obtained along the X-direction (length direction) of the substrate, andFIG.8Cis a top down view to illustrate a final structure when the second trenches56and58are formed. As shown inFIG.8B, both the first and the second trenches cannot be observed when the cross-sectional view is made along the X-direction (length direction) of the substrate10. InFIG.8C, the insulating layer60ais a top layer. The second trenches56and58are formed along the length direction of the substrate and further are aligned with the first trenches26and28in the Y-direction (width direction) of the substrate10. The first trenches and the second trenches together separate the substrate10into three regions (or sub-blocks). In addition, two staircase regions100A and100C are positioned at two sides and a core region100C is positioned in middle of the substrate.

FIG.9Ais a cross-sectional view obtained in the Z-direction (height direction) of the substrate to illustrate the formation of a plurality of channel structures. In order to form the channel structures, a plurality of channel openings can be formed firstly. The channel openings can be formed through a photolithography process to form a patterned mask and a subsequent etching process to transfer the patterns of the mask. The formed channel openings can pass through the TSG, the dummy TSGs, the word lines, the dummy BSGs, and the BSG, and further extend into the HVPW14. Each of the channel openings can have side portions and a bottom portion to expose the HVPW14. When the channel openings are formed, a plurality of bottom channel contacts, such as the bottom channel contact202illustrated inFIG.1C, can be formed at the bottom portions of the channel openings. Each of the channel openings can have a respective bottom contact at the bottom portion. The bottom channel contacts can protrude from the BSG62p, and a top surface of each of the bottom channel contacts can be positioned between the BSG62pand the dummy BSG62o.

Still referring toFIG.9A, once the bottom channel contacts are formed, a barrier layer, a charge trapping layer, and a tunneling layer can be formed sequentially along the side portions of the channel openings and over the bottom channel contacts. A subsequent anisotropic plasm etching can be applied to remove portions of the barrier layer, the charge trapping layer, and the tunneling layer that are disposed over the bottom channel contacts to form a plurality of interconnect opening. Each interconnect opening exposes a respective bottom channel contact. A channel layer can be formed subsequently along the side portions of the channel openings and further extends through the interconnect openings to connect the bottom channel contacts.

Once the channel layer is formed, the channel layer can have side portions that are formed along the tunneling layer and a T-shape bottom portion that extends through bottom portions of the tunneling layer, the charge trapping layer, and the barrier layer that are positioned over the bottom channel contact. The T-shape bottom portion of the channel layer is in direct contact with the bottom channel contact, which can be shown inFIGS.1C and1D. In addition, the tunneling layer, the charge trapping layer, and the barrier layer can form an L-foot configuration in the channel openings. The L-foot configuration can include side portions that are formed along the sidewalls of the channel openings and a bottom portion over the bottom channel contacts.

In some embodiments, once the channel layer is formed, a subsequent annealing process can be applied, one is to release wafer stress, the other is to reduce defects (dangling bonds), in some cases, it's also to transform the channel layer into polycrystalline. In some embodiments, the formation of the channel structure further includes forming a channel insulating layer over the channel layer to fill the channel openings, and forming a top channel contact over the channel insulating layer and the top channel contact is in direct contact with the channel layer. A detailed channel structure can be illustrated inFIGS.1C and1D.

FIG.9Bis top down view to illustrate the formation of a plurality of channel structures. As shown inFIG.9B, the plurality of channel structures can be formed in the core region100B and separated by the second trenches56and58into 3 sub-blocks.

FIG.10Ais a cross-sectional view obtained in the Z-direction (height direction) of the substrate to illustrate the formation of a plurality of dummy channel structures40,42,44,46,48, and50. The dummy channel structures serve as sustain components to support the staircase regions100A and100C and/or the core regions100B when sacrificial word lines are removed and replaced with metals. In order to form the dummy channel structures, a plurality of dummy channel openings can be formed firstly. The dummy channel openings can be formed through a photolithography process to form a patterned mask and a subsequent etching process to transfer the patterns of the mask. The dummy channel openings can be formed in the staircase regions. The formed dummy channel openings can pass through the word lines, the dummy BSGs, and the BSG, and further extend into the HVPW14. Each of the dummy channel openings can have side portions and a bottom portion to expose the HVPW14. When the dummy channel openings are formed, a dielectric layer can be formed to fill the dummy channel openings. The dielectric layer can include SiO2, SiCN, SiOCN, or other suitable materials. A subsequent surface planarization, such as a CMP process, may be required to remove any excessive dielectric layer over the insulating layer60a. Once the surface planarization is completed, the dielectric layer that remains in the dummy channel openings forms the dummy channel structures.

In some embodiments, the dummy channel structures can have a critical dimension (CD) between 50 nm and 200 nm. In some embodiments, the dummy channel structures can extend into the HVPW14with a depth between 10 nm and 200 nm. The dummy channel structures can have a circular shape. In some embodiments, the dummy channel structures can have non-circular shapes, such as a capsule shape, a rectangular shape, an arc shape, a bone shape, and the like. The non-circular shapes can be adjusted by two or more parameters, such as width, length, arc radius, arc angle, and the like. Further, in some embodiments, the non-circular shapes can be arranged in a symmetric pattern or in a non-symmetric pattern with regard to other contacts in the staircase regions.

In some embodiments, the dummy channel structures can be formed before the staircase region is formed. In some embodiments, the dummy channel structures can be formed in the core region. Accordingly, the dummy channel structures can pass through the BSG, the dummy BSGs, the plurality of word lines, the dummy TSGs, the TSG and the plurality of insulating layers to extend into the substrate. In some embodiments, the dummy channel structures can be formed with the channel structure together and have a similar structure to the channel structure. For example, the dummy structure can also include a barrier layer, a trapping layer, a tunneling layer, and a channel layer.

FIG.10Bis top down view to illustrate the formation of the plurality of dummy channel structures. As shown inFIG.10B, the plurality of dummy channel structures can be formed in the two staircase regions100A and100C, and also core array region100B (Especially, at the transition zones of core to staircase regions).

FIG.11Ais a cross-sectional view obtained in the Z-direction (height direction) of the substrate to illustrate the formation of one or more common source regions. In order to form the channel structures, one or more common source openings can be formed firstly. The common source openings can be formed through a photolithography process to form a patterned mask and a subsequent etching process to transfer the patterns of the mask. The formed common source openings pass through the TSG, the dummy TSGs, the word lines, the dummy BSGs, and the BSG, and further extend into the HVPW14. Each of the common source openings can have side portions and a bottom portion that extend into the HVPW. The common source openings can further extend along the X-direction (Length direction) of the substrate, and are parallel disposed with the first and second trenches.

FIG.11Bshows an exemplary embodiment of the formation of the common source openings. As shown inFIG.11B, two common source openings52b′ and52C′ are formed at two boundaries of the substrate with a continuous configuration. The common source regions52aand52ccan be subsequently formed within the common source openings52b′ and52c′ respectively. A common source opening52a′ is formed at a middle position of the substrate. The common source opening52a′ can include two or more sub-openings based on the formed pattern of mask. For example, two sub-openings52a-1′ and52a-2′ are included inFIG.11B. A space between the two sub-openings52a-1′ and52a-2′ forms an H-Cut, such as the H-Cut72inFIG.11B. Common source regions52a-1and52a-2can be formed within the two sub-openings52a-1′ and52a-2′ respectively.

After the common source openings are formed, subsequent manufacturing steps to complete the formation of the common source regions can be different between a gate first manufacturing flow and a gate last manufacturing flow. In the gate first manufacturing flow, an ion implantation can be subsequently applied to form a dope region, such as the doped region54, at the bottom portion of each of the common source openings. A dielectric spacer, such as the dielectric spacer68, can be formed along the side portions of the common source openings and over the doped regions. An anisotropic plasm etching can be implemented to remove bottom portion of the dielectric spacer formed over the doped regions to expose the doped regions. A conductive layer, such as the conductive layer70, can be deposited along the dielectric spacer and fill the common source openings. The conductive layer can be recessed afterward by an etching process, and a top contact, such as the top contact64, can be formed along the dielectric spacer and over the conductive layer. When the top contact is formed, formation of a common source region is completed and the complete common source region52can be illustrated inFIG.11A.

However, in the gate last manufacturing flow, when the common source openings are formed, the BSG, dummy BSGs, word lines, dummy TSGs, and TSG are subsequently removed to form a plurality of vacancies by a wet etching chemical that is introduced through the common source openings. An ion implantation can be thereafter applied to form the dope region (e.g.,54) at the bottom portion of each of the common source openings. Following the implantation step, the BSG, dummy BSGs, word lines, dummy TSGs, and TSG are re-formed by filling the vacancies with a high-K layer plus metal layers through the common source openings. Next, a dielectric spacer, such as the dielectric spacer68, can be formed along the side portions of the common source openings and over the doped regions. A followed anisotropic plasm etching can be implemented to remove bottom portion of the dielectric spacer formed over the doped regions to expose the doped regions. A conductive layer, such as the conductive layer70, can be deposited along the dielectric spacer and fill the common source openings. The conductive layer can be recessed afterward by an etching process, and a top contact, such as the top contact64, can be formed along the dielectric spacer and over the conductive layer. When the top contact is formed, formation of the common source regions is completed and the complete common source regions can be illustrated inFIG.11A.

After the formation of the common source regions, a final memory device100is formed which is identical to the memory device100illustrated inFIG.1A.

FIG.11Cis top down view to illustrate the formation of one or more common source regions. As shown inFIG.11C, the memory device100can have three common source regions52a-52c. The common source regions52a-52care formed along the X-direction (length direction) of the substrate10and are disposed at two boundaries and a middle position of the memory device100. The common source regions52band52C are disposed at two boundaries of the memory device100with a continuous configuration. The common source region52ais disposed at a middle position of the memory device100. The common source region (CSR)52ais separated by the H-cut72into two sub-CSRs52a-1and52a-2. The first trenches26and28, and the second trenches56and58are aligned with each other at the Y direction (width direction) of the substrate10. The first trenches and the second trenches are disposed between two adjacent common source regions.

FIG.11Dis a cross-sectional view obtained in the X-direction (length direction) of the substrate to illustrate the final structure of the memory device100. As shown inFIG.11D, the first trenches, the second trenches and the common source regions cannot be observed from the cross-sectional view that is obtained in the X-direction (length direction) of the substrate.

FIG.12is a flowchart of a process1200for manufacturing a 3D NAND memory device100in accordance with some embodiments. The process1200begins at step1204where one or more BSGs and one or more dummy BSGs are formed sequentially over a substrate. In addition, a plurality of first insulating layers are formed between the substrate, the BSGs and the dummy BSGs. The substrate can include a plurality of doped regions to reduce the resistance between the substrate and subsequently formed contact structures. The substrate, BSGs and dummy BSGs are spaced apart from each other by the first insulating layers.

In step1206of the process1200, one or more first trenches are formed in the BSGs and dummy BSGs. The first trenches pass through the BSGs, dummy BSGs, and the first insulating layers, and extend into the substrate. The first trenches further extend along a X-direction (length direction) of the substrate. The first trenches separate the BSGs, the dummy BSGs into a plurality of sub-BSGs, and sub-dummy BSGs. In some embodiments, steps1204and1206can be performed as illustrated with reference toFIGS.5A-5C.

The process1200then proceeds to step1208where a plurality of word lines, one or more dummy TSGs, and one or more TSGs are stacked over the dummy BSGs sequentially. In addition, a plurality of second insulating layers are formed over the dummy BSGs and disposed between the dummy BSGs, the word lines, the dummy TSGs, and TSGs. In some embodiments, step1208can be performed as illustrated with reference toFIG.6.

In step1210, one or more staircase regions can be formed. The staircase regions are configured to provide spaces to form dummy channel structure as well as word line contacts (not shown). The formation of the staircase regions can be implemented by alternatively repeating a mask patterning process and a plasma etching process. The formed staircase regions are positioned at two sides of the substrate and a core region is position in the middle. In some embodiments, step1208can be performed as illustrated with reference toFIGS.7A-7F.

The process1200proceeds to step1212where one or more second trenches are formed in the dummy TSGs and the TSGs. The second trenches extend along the length direction of the substrate. The second trenches further pass through the dummy TSG, the TSGs and a portion of the second insulating layers therebetween. The first trenches and the second trenches are aligned with each other in a width direction of the substrate and are spaced apart by the plurality of word line layers. The TSGs are separated by the second trenches into a group of sub-TSGs, and the TSGs are separated by the second trenches into a group of sub-dummy TSGs. In some embodiments, step1212can be performed as illustrated with reference toFIGS.8A-8C.

In step1214of the process1200, a plurality of channel structures can be formed in the core region. The formation of the channel structures can be performed as illustrated with reference toFIGS.9A-9B. Next, a plurality of dummy channel structures can be formed in the staircase regions. The formation of the dummy channel structures can be performed as illustrated with reference toFIGS.10A-10B.

It should be understood that the channel structures can also be formed before the staircase region is formed. In some embodiments, the dummy channel structures can be formed in the core region. In some embodiments, the dummy channel structures can be formed with the channel structure together and have a similar structure to the channel structure. For example, the dummy structure can also include a barrier layer, a trapping layer, a tunneling layer, and a channel layer.

Still in step1214, one or more common source regions can be formed after the formation of the dummy channel structures. The common source regions extend through the BSGs, the dummy BSGs, the word lines, the dummy TSGs, the TSGs, and the first and second insulating layers. Each of the common source regions is electrically coupled with the substrate via a respective doped region. The common source regions, the first trenches and the second trenches further extend parallel to each other along the length direction of the substrate. In some embodiments, the formation of the common source regions further includes removing the BSGs, the dummy BSGs, the word lines, the dummy TSGs, and the TSGs, and re-forming the BSGs, the dummy BSGs, the word lines, the dummy TSGs, and the TSGs with a high-K layer and metal layers. In some embodiments, the formation of the common source regions can be performed as illustrated with reference toFIGS.11A-11D.

It should be noted that additional steps can be provided before, during, and after the process1200, and some of the steps described can be replaced, eliminated, or performed in different order for additional embodiments of the process1200. In subsequent process steps, various additional interconnect structures (e.g., metallization layers having conductive lines and/or vias) may be formed over the semiconductor device1200. Such interconnect structures electrically connect the semiconductor device1200with other contact structures and/or active devices to form functional circuits. Additional device features such as passivation layers, input/output structures, and the like may also be formed.

The various embodiments described herein offer several advantages over related memory devices. For example, in the related memory devices, a plurality of memory cell blocks or memory cell arrays can be included. Each of the blocks can include a plurality of vertical NAND memory cell strings. In the related memory device, the vertical NAND memory cell strings in a same block can have a common/shared bottom select gate (BSG). The shared BSG accordingly controls all the bottom select transistors (BSTs) of the vertical NAND memory cell strings in that block simultaneously during operating the related 3D-NAND memory device, such as erasing the related 3D-NAND memory device. As the related 3D-NAND memory device migrates to higher capacity with an increasing block size, the shared BSG can induce longer erasing time, longer data transfer time, and lower storage efficiency.

In the disclosed memory device, each of the blocks is separated into a plurality of sub-blocks by dividing the shared BSG into a plurality of sub-BSGs through one or more first trenches. Each of the sub-blocks has a respective sub-BSG, and each of the sub-blocks can be operated individually through controlling the respective sub-BSG. By introducing such a divided BSG structure, the disclosed 3D-NAND memory device can effectively reduce parasitic capacitance and coupling effects between the BSG and adjacent dielectric layers, and significantly improve Vtperformance of the bottom select transistors (BSTs). In addition, the erasing time and data transfer time could be reduced significantly, and data storage efficiency can be improved as well.

In the disclosed memory device, the each of sub-blocks can further have a respective sub-top select gate (sub-TSG) by dividing a shared TSG into a plurality of sub-TSGs through one or more second trenches. Each of the sub-TSGs can control a respective sub-block during a reading/programming operation. In some embodiments, the first and second trenches can be formed via a same reticle set so that a manufacturing cost can be reduced.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.