Patent ID: 12261088

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a second feature over or on a first feature in the description that follows may include embodiments in which the second and first features are formed in direct contact, and may also include embodiments in which additional features may be formed between the second and first features, such that the second and first features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath”, “below”, “lower”, “on”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.

FIGS.1,2,3,4,5,6A,6B,7A,7B,7C,8A,8B,8C,8D,8E,8F,9,10and11illustrate varying views of manufacturing a package structure in accordance with some embodiments of the disclosure.

Referring toFIG.1, a carrier100is provided. The carrier100may be a glass carrier, a ceramic carrier, or the like. In some embodiments, the carrier100has a de-bonding layer101formed thereon. The de-bonding layer101is formed by, for example, a spin coating method. In some embodiments, the de-bonding layer101may be formed of an adhesive such as an Ultra-Violet (UV) glue, a Light-to-Heat Conversion (LTHC) glue, the like, or other types of adhesives. The de-bonding layer101is decomposable under the heat of light to thereby release the carrier100from the overlying structures that will be formed in subsequent processes.

A dielectric layer102is formed on the de-bonding layer101over the carrier100. In some embodiments, the dielectric layer102includes silicon oxide, or TEOS, while other dielectric material such as silicon carbide, silicon oxynitride, silicon oxy-carbo-nitride, PSG, BSG, BPSG, or the like may also be used. The dielectric layer102may be formed by a deposition process, a spin-on coating process, or the like. In other embodiments, the dielectric layer102includes a molding compound, a molding underfill, a resin such as epoxy, or the like, and may be formed by a molding process. In other embodiments, the dielectric layer102includes a polymer material, such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), or the like, and may be formed by a deposition process, a lamination process, a spin-on coating process, or the like.

Still referring toFIG.1, conductive vias103are formed on the dielectric layer102. The conductive vias103may be referred to as “through integrated fan-out vias (TIVs)” in some examples. The conductive vias103include copper, titanium, nickel, solder, an alloy thereof, the like, or a combination thereof. In some embodiments, each of the conductive vias103includes a seed layer and a conductive post formed thereon (not individually shown). In some embodiments, the seed layer includes a first metal layer such as a titanium layer and a second metal layer such as a copper layer over the first metal layer. In some embodiments, the conductive post includes copper or other suitable metal.

In some embodiments, the conductive vias103may be formed by the following processes: a seed material layer is firstly formed on the dielectric layer102by a sputtering process, and a patterned mask layer such as a patterned photoresist is formed on the seed material layer. The patterned mask layer includes openings that expose portions of seed material layer at the locations where the conductive vias103are to be formed. The conductive posts are then formed on the seed material layer exposed by the patterned mask layer. The patterned mask layer is stripped, and the portions of the seed material layer not covered by the conductive posts are removed.

Referring toFIG.2, a die110is mounted to the carrier100by a pick and place process, for example. In some embodiments, the die110is attached to the dielectric layer102through an adhesive layer104such as a die attach film (DAF), silver paste, or the like. In some embodiments, the die110is one of a plurality of dies cut apart from a wafer, for example. In some embodiments, the die110is a logic chip, a sensor chip or an imaging chip, but the disclosure is not limited thereto. In other embodiments, the die110may be an application-specific integrated circuit (ASIC) chip, an analog chip, a wireless and radio frequency chip, a voltage regulator chip, a memory chip, or any other suitable type of die. The number of the die110shown inFIG.2is merely for illustration, and the disclosure is not limited thereto. In some embodiments, multiple dies110may be mounted over the carrier100, and the dies110may have the same or different functions.

The die110is disposed between the conductive vias103; that is, the conductive vias103are located aside or around the die110. In some embodiments, the die110may include a semiconductor substrate105, a plurality of conductive pads106, and a passivation layer107.

The semiconductor substrate105includes an elementary semiconductor such as silicon, germanium and/or a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, gallium nitride or indium phosphide. For example, the semiconductor substrate105is a silicon-on-insulator (SOI) substrate or a silicon substrate. In various embodiments, the semiconductor substrate105may take the form of a planar substrate, a substrate with multiple fins, nanowires, or other forms known to people having ordinary skill in the art. Depending on the requirements of design, the semiconductor substrate105may be a P-type substrate or an N-type substrate and may have doped regions therein. In some embodiments, at least one device (not shown) is formed in and/or on the semiconductor substrate105. The device may be an integrated active device, an integrated passive device, or a combination thereof. The device may include a transistor, such as fin field effect transistor (FinFET), a gate all around FET (GAA-FET) or the like.

In some embodiments, an interconnection structure (not shown) is formed over the device on the semiconductor substrate105. The interconnection structure may include conductive features embedded in dielectric layers, so as to electrically connect different components in and/or on the semiconductor substrate105to form a functional circuit. In some embodiments, the dielectric layers include an inter-layer dielectric (ILD) layer and one or more inter-metal dielectric (IMD) layers. The conductive features may include multiple layers of conductive lines and conductive plugs (not shown). The conductive plugs include contact plugs and via plugs. The contact plugs are located in the ILD layer to connect the metal lines to the device. The via plugs are located in the IMD layers to connect the metal lines in different layers. The dielectric layers include silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material, or a combination thereof. The conductive features include metal, a metal alloy or a combination thereof, such as tungsten (W), copper (Cu), copper alloy, aluminum (Al), aluminum alloy, or a combination thereof.

The conductive pads106may be electrically connected to a top conductive feature of the interconnection structure and the underlying device. In some embodiments, the conductive pads106are aluminum pads, but the disclosure is not limited to. In other embodiments, the conductive pads106may include other metal or metal alloy, such as copper, nickel, or an alloy thereof.

The passivation layer107is formed over the semiconductor substrate105and partially covers the conductive pads106. Portions of the conductive pads106are exposed by the passivation layer107and serve as external connections of the die110. In some embodiments, the passivation layer107includes an insulating material such as silicon oxide, silicon nitride, silicon, silicon carbide, the like, or a combination thereof. However, the disclosure is not limited thereto. In other embodiments, the passivation layer107includes a polymer material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), the like, or a combination thereof.

In some embodiments, the die110is a sensor chip and includes a plurality of sensing regions108. The sensing regions108may be pixel regions in some embodiments. The sensing regions108may extend from the top surface107aof the passivation layer107to the underlying device. In some embodiments, the sensing regions108are disposed between the conductive pads106. It is noted that, the shape, size and location of the sensing regions108shown in the figures are merely for illustration, and the disclosure is not limited thereto.

In the embodiments in which the die110is a sensor chip, the die110may further include a sacrificial film109formed over the semiconductor substrate105and covering the sensing regions108. In some embodiments, the sacrificial film109overlays a portion of passivation layer107without covering the conductive pads106. Specifically, the width of the sacrificial film109may be less than the width of the die110, but the disclosure is not limited thereto. In other embodiments, the sacrificial film109may further extend to cover the conductive pads106. For example, the sacrificial film109may completely cover the passivation layer107and the conductive pads106. The width of the sacrificial film109may be substantially equal to the width of the die110. In some embodiments, the material of the sacrificial film109is different from the materials of the passivation layer107and the subsequently formed encapsulation layer. For example, the sacrificial film109may include a polymer such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), the like, or a combination thereof, but the disclosure is not limited thereto. In some embodiments, the die110is free of a connector (e.g., metal pillar) on the conductive pads106, but the disclosure is not limited thereto.

Referring toFIG.3, an encapsulation material layer112is formed over the carrier100to encapsulate the die110and the conductive vias103. In some embodiments, the encapsulation material layer112includes a molding compound, a molding underfill, a resin such as epoxy, the like, or a combination thereof. In other embodiments, the encapsulation material layer112includes a photo-sensitive material such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), the like, or a combination thereof. In other embodiments, the encapsulation material layer112includes nitride such as silicon nitride, oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), the like, or a combination thereof. In some embodiments, the encapsulation material layer112includes a molding compound which is a composite material including a base material (such as polymer) and fillers distributed in the base material. Each filler may be a single element, a compound such as nitride, oxide, or a combination thereof. The fillers may include silicon oxide, aluminum oxide, boron nitride, alumina, silica, or the like, for example. The cross-section shape of the filler may be circle, oval, or any other suitable shape.

In some embodiments, the encapsulation material layer112is formed by an over-molding process, such that the encapsulation material layer112has a top surface higher than top surfaces of the conductive vias103and the die110. In other words, the encapsulation material layer112encapsulates the sidewalls and top surfaces of the die110and the conductive vias103.

Referring toFIG.4, a planarization process is performed to remove a portion of the encapsulation material layer112, and the remaining encapsulation layer112aexposes the conductive vias103and the sacrificial film109. The planarization process includes a chemical mechanical polishing (CMP) process, for example. In some embodiments, a portion of the sacrificial film109and/or portions of the conductive vias103may also be removed by the planarization process. After the planarization process is performed, the top surfaces of the encapsulation layer112a, the conductive vias103and the sacrificial film109are substantially coplanar with each other. In some embodiments in which the sacrificial layer109partially covers the passivation layer107, a portion of the encapsulation layer112ais located on the die110to encapsulate and physically contact a portion of the passivation layer107and portion of the conductive pads106uncovered by the sacrificial layer109. In other embodiments in which the sacrificial layer109completely covers the top surfaces of the passivation layer107and the conductive pads106, the encapsulation layer112ais laterally aside the die110(as shown inFIG.14).

Referring toFIG.5, the sacrificial film109is removed to expose the sensing regions108of the die110. The sacrificial film109may be removed by a suitable technique such as an etching process, a laser irradiation process, or the like. The etching process may include a dry etching, a wet etching or a combination thereof.

In some embodiments, after the sacrificial film109is removed, a portion of the passivation layer107is exposed, while the other portion of the passivation layer107and the conductive pads106are covered by the encapsulation layer112. The top surfaces of the passivation layer107and the conductive pads106constitute the first surface FS of the die110. The first surface FS is referred to as a front surface, an active surface or a sensing surface of the die110in some examples. In some embodiments, the first surface FS of the die110is lower than the top surface of the encapsulation layer112aand the top surfaces of the conductive vias103, and a portion of the first surface FS of the die110is encapsulated by the encapsulation layer112a. The die110has a second surface BS opposite to the first surface FS. The second surface BS is a bottom surface of the semiconductor substrate105, and may also be referred to as a back surface of the die110.

Still referring toFIG.5, a recess115is formed at the position previously occupied by the removed sacrificial film109. The recess115is located over the die110and within the encapsulation layer112a, and a portion of the sidewall of the encapsulation layer112ais exposed by the recess115. In other words, the recess115is defined by a portion of the first surface FS of the die110and the sidewall of the encapsulation layer112a.

Referring toFIG.6AandFIG.6B, a redistribution layer structure120is formed on the die110, the conductive vias103and the encapsulation layer112a, and electrically connected to the die110and the conductive vias103. The sensing regions108of the die110may be exposed by the redistribution layer structure120. In some embodiments, the redistribution layer structure120is also referred to as a “front-side redistribution layer structure” formed on the front side of the die110. Herein, the term “front-side” refers to a side close to the conductive pads106of the die110.

In some embodiments, the redistribution layer structure120includes polymer layers and redistribution layers alternatively stacked on one another. For example, the redistribution layer structure120includes polymer layers PM1, PM2, and redistribution layers RDL1, RDL2. The number of the polymer layers or the redistribution layers shown inFIG.6Ais merely for illustration, and the disclosure is not limited thereto. The redistribution layers are disposed in the polymer layers and electrically connected to each other.

In some embodiments, each polymer layer PM1, PM2includes polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), the like, or a combination thereof. The polymer layers PM1, PM2may be replaced by dielectric layers or insulating layers as needed. In some embodiments, the metal features of each of the redistribution layers RDL1, RDL2includes metal vias and/or metal lines. The metal vias may be formed between and in contact with two metal lines. Each of the redistribution layers RDL1, RDL2may include tungsten (W), copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy or a combination thereof. In some embodiments, a barrier layer (not shown) is formed between each metal feature and the adjacent polymer layer to prevent the material of the metal feature from migrating to the neighboring device. The barrier layer may include Ta, TaN, Ti, TiN, CoW or a combination thereof. In some embodiments, a seed layer (not shown) is further formed between each metal feature and the barrier layer. The seed layer may include Cu, Ag or the like.

In some embodiments, the redistribution layer RDL1penetrates through the polymer layer PM1and the encapsulation layer112ato connect to the conductive vias103and the conductive pads106of the die110. The redistribution layer RDL2penetrates through the polymer layer PM2to connect to redistribution layer RDL1. A portion of the redistribution layer structure120, such as a portion of the polymer layer PM1may fill into the recess115and covers a portion of the top surface of the passivation layer107. In some embodiments, the redistribution layer structure120has an opening121overlapped and in spatial communication with the recess115, so as to expose the sensing regions108of the die110. The opening121may be defined by a portion of front surface FS of the die110and the surface (i.e., inner sidewall or inner surface) S of the redistribution layer structure120. It is noted that, although the redistribution layer structure120is shown to have two separate parts on opposite sides of the opening121in the cross-sectional viewFIG.6A, the redistribution layer structure120is actually a continuous structure. When viewed in a top view, the redistribution layer structure120may be a continuous structure with the opening121disposed in a center region thereof. As shown in the simplified top view inFIG.6B, the polymer layers PM1, PM2of the redistribution layer structure120expose a portion of the passivation layer107.

In some embodiments, the inner surface S of the redistribution layer structure120has a stepped profile. In other words, a portion (e.g., edge portion) of the redistribution layer structure120is step shaped. The inner surface S may include a first inner sidewall landing on the die110, a second inner sidewall over the first inner sidewall, and a substantially planar surface connecting the first inner sidewall and the second inner sidewall. The first inner sidewall is laterally shifted from the second inner sidewall and closer to a center of the die110than the second inner sidewall in a horizontal direction. The planar surface may be lower than, substantially coplanar with or higher than the top surface of the polymer layer PM1. The first inner sidewall may include at least a portion of an inner sidewall of the polymer layer PM1. The second inner sidewall may include at least a portion of an inner sidewall of the polymer layer PM2. In some embodiments, a portion of the polymer layer PM1may laterally protrude from the polymer layer PM2and/or another portion of the polymer layer PM1. However, the disclosure is not limited thereto. In other embodiments, the inner surface S (i.e., inner sidewall) of the redistribution layer structure120may be substantially straight or inclined.

In some embodiments, the redistribution layer structure120may be formed by the following processes: a first polymer material layer is formed over the carrier100to cover die110and the encapsulation layer112athrough a suitable technique such as spin coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), lamination or the like. Thereafter, the redistribution layer RDL1is formed to penetrate through the first polymer material layer and the encapsulation layer112ato connect to the conductive vias103and the conductive pads106. The forming method of the redistribution layer RDL1may include a physical vapor deposition (PVD) such as sputtering process followed by an electroplating process. The formation of the redistribution layer RDL1may avoid the region directly over the sensing region108of the die110. Thereafter, processes for forming the polymer material layer and redistribution layer are repeated to form a second polymer material layer and the redistribution layer RDL2. The first polymer material layer and/or the second polymer material layer may fill in the recess115and overlay the sensing regions108. In some embodiments, thereafter, the second and first polymer material layers are patterned to form the polymer layers PM1, PM2having the opening121, thereby exposing the sensing regions108. The patterning method may include an exposure and development process, a laser drilling process, the like, or a combination thereof. In other embodiments, the patterning of the polymer material layer may be performed before the formation of the corresponding redistribution layer. In some embodiments, upon the patterning of the second and first polymer material layers, an interface I exists between the polymer layer PM1and the passivation layer107. However, the disclosure is not limited thereto. In other embodiments, upon the patterning of the second and first polymer material layers, an interface may exist between the polymer layer PM2and the passivation layer107.

In some embodiments, the polymer layer PM1is disposed on the encapsulation layer112aand may partially fill into the recess115(FIG.5). The polymer layer PM1may cover the top surface of the encapsulation layer112aand a portion of the front surface FS of the die110. In some embodiments, a portion of the polymer layer PM1fills into the recess115to cover the sidewall (i.e., inner sidewall) of the encapsulation layer112a. The top corners of the encapsulation layer112amay be covered by the polymer layer PM1. In some embodiments, the polymer layer PM1may be not filled in the recess115, and the inner sidewall of the polymer layer PM1may be substantially aligned with or laterally shifted from the inner sidewall of the encapsulation layer112a.

The redistribution layer RDL1penetrates through the polymer layer PM1and the encapsulation layer112ato electrically connect to the conductive pads106of the die110and the conductive vias103. In some embodiments, the redistribution layer RDL1includes vias V1, vias V2and traces T1electrically connected to each other. The traces T1are located on and extending on the top surface of the polymer layer PM1. The vias V1penetrate through the polymer layer PM1and the underlying encapsulation layer112a, so as to connect the traces T1to the conductive pads106of the die110. The vias V2penetrate through the polymer layer PM1, so as to connect the traces T1to the conductive vias103. The height of the via V1is larger than the height of the via V2, and the bottom surface of the via V1is lower than the bottom surface of the via V2. Upper portions of the vias V1are embedded in polymer layer PM1, while bottom portions of the vias V1are laterally encapsulated by the encapsulation layer112aand laterally aside the conductive vias103.

The polymer layer PM2is disposed on the polymer layer PM1to cover the redistribution layer RDL1. In some embodiments, a portion of the polymer layer PM2may be laterally surrounded by the vias V1and may have a bottom surface (i.e., the bottommost surface of the polymer layer PM2) lower than a top surface of the encapsulation layer112a. However, the disclosure is not limited thereto. The bottommost surface of polymer layer PM2may be higher than or substantially coplanar with the top surface of the encapsulation layer112a, which is at least partially depending on the configuration of the via V1. In some embodiments, the redistribution layer RDL2may be a conductive via or conductive pillar protruding from the top surface of the polymer layer PM2for further electrical connection. The cross-sectional shape of the redistribution layer RDL2may be inverted trapezoid, square, rectangle, the like, or any other suitable shape.

Referring toFIGS.7A,7B and7C, an adhesive material A1is applied along the interface I between the polymer layer PM1and the passivation layer107. Specifically, the adhesive material A1is formed as a spacer on the sidewall of the opening121(e.g., the inner surface S of the Redistribution layer structure120).

In some embodiments, the adhesive material A1includes a molding compound, a molding underfill, a resin (e.g., epoxy, silicone or both), or the like. In other embodiments, the adhesive material A1includes a polymer material, such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), or the like. In some embodiments, the adhesive material A1is formed by a stencil printing process with a stencil mask M11(seeFIG.12) with openings OP11corresponding to a location where the adhesive material A1is to be printed. In other embodiments, the adhesive material A1is formed by a screen printing process with a screen mask M12(seeFIG.13) with openings OP12corresponding to a location where the adhesive material A1is to be printed.

The printing process may be formed by the following processes: a stencil or screen mask M11/M12is placed onto the redistribution layer structure120. The stencil or screen mask M11/M12has openings OP11/OP12that expose the inner surface S of the redistribution layer structure120and a portion of the passivation layer107. The printing process is performed using the stencil or screen mask M11/M12, such that the adhesive material A1is applied or printed on the inner surface S of the redistribution layer structure120and on the exposed portion of the passivation layer107.

In some embodiments, when a stencil printing process is performed with a stencil mask M11, the adhesive material A1is formed as separate islands arranged along the interface I between the polymer layer PM1and the passivation layer107, as shown in the simplified top view inFIG.7B. In other embodiments, when a screen printing process is performed with a screen mask M12, the adhesive material A1is formed as a ring shape with grid patterns along the interface I between the polymer layer PM1and the passivation layer107, as shown in the simplified top view inFIG.7C.

Referring toFIGS.8A and8B, after the adhesive printing process, a curing process P1is performed to the adhesive material A1. In some embodiments, the curing process P1is performed at a temperature of about 120° C. to 150° C. for about 1 hour to 2 hours. Upon the curing process P1, the adhesive material A1is formed as an enclosed shape along the interface I between the polymer layer PM1and the passivation layer107, as shown in the simplified top view inFIG.8B. For example, the enclosed shape includes a continuous ring shape such as a rectangular ring shape or a circular ring shape. In some embodiments, the adhesive material A1is configured to provide sealing protection for the interface between two different materials (e.g., between the polymer layer and the passivation layer), so as to prevent the film delamination issue and therefore improve the reliability of the device. The adhesive material A1is referred to a “sealing protection structure”, “protection sealant” or “interface sealing structure” in some examples.

Each ofFIG.8CtoFIG.8Fshows local enlarged views of a region122ofFIG.8Ain accordance with some embodiments of the disclosure, in which the partial cross-sectional view is shown on the upper side of the figure, and the partial top view is shown on the lower side of the figure.

As shown inFIG.8C, the adhesive material A1is formed on the sidewall S of the redistribution layer structure120and extend onto a portion of the top surface of the redistribution layer structure120. In some embodiments, the adhesive material A1has an unsymmetrical sidewall profile. For example, the adhesive material A1has a stepped sidewall close to the redistribution layer structure120, an inclined sidewall away from the redistribution layer structure120, and a mesa connecting the stepped sidewall and the inclined sidewall. Specifically, the adhesive material A1not only covers the interface I between the polymer layer PM1and the passivation layer107, but covers two exposed polymer steps of the redistribution layer structure120. From another point of view, the adhesive material A1has a curvy sidewall with multiple turning points close to the redistribution layer structure120, and a substantially smooth sidewall away from the redistribution layer structure120.

In some embodiments, as shown inFIG.8C, the adhesive material A1has a total width L of about 200-1000 um. In some embodiments, the total width L of the adhesive material A1is divided into different types: a width L1on the polymer layer (including an extending width L11and a bleeding width L12), and a width L2on the passivation layer (including an extending width L21and a bleeding width L22). For example, the extending width L11on the polymer layer PM1/PM2is about 50-250 um, and the bleeding width L22on the polymer layer PM2is about 30-250 um, the extending width L21on the passivation layer107is about 50-250 um, the bleeding width L22on the passivation layer107is about 70-250 um or less. The sensing regions108are not covered by the adhesive material A1. Specifically, the adhesive material A1is separated from the sensing regions108by a non-zero horizontal distance. In some embodiments, the distance (e.g., keep out zone) from the edge of the adhesive material A1to the sensing regions108is at least about 50 um or more. In some embodiments, as shown inFIG.8C, the adhesive material A1has a total height H1ranging from about 30 um to 100 um. In some embodiments, the top surface of the adhesive material A1is higher than the top surface of the redistribution layer structure120by a non-zero distance d. For example, the non-zero distance d ranges from about 1 um to 30 um.

In the embodiment ofFIG.8C, the adhesive material A1has a top surface higher than that of the redistribution layer structure. However, the disclosure is not limited thereto. In other embodiments, the top surface of the adhesive material A1is substantially level with or less than the top surface of the redistribution layer structure, as shown inFIG.8DtoFIG.8F. For example, the print amount of the adhesive material A1inFIG.7Amay be tuned or adjusted for cost reduction. The cross-sectional shapes of the adhesive materials A1inFIG.8CtoFIG.8Fare provided for illustration purposes, and are not construed as limiting the present disclosure. The cross-sectional shape of the adhesive material A1is not limited by the disclosure, as long as the cured adhesive material A1covers the interface I between the polymer layer PM1and the passivation layer107.

As shown inFIG.8DandFIG.8E, the adhesive material A1is formed on the sidewall S of the redistribution layer structure120without extending onto the top of the redistribution layer structure120. In some embodiments, the adhesive material A1has an unsymmetrical sidewall profile. For example, the adhesive material A1has a stepped sidewall close to the redistribution layer structure120, an inclined sidewall away from the redistribution layer structure120, and a mesa connecting the stepped sidewall and the inclined sidewall. Specifically, the adhesive material A1not only covers the interface I between the polymer layer and the passivation layer107, but covers one exposed polymer step of the redistribution layer structure120. From another point of view, the adhesive material A1has a curvy sidewall with multiple turning points close to the redistribution layer structure120, and a substantially smooth sidewall away from the redistribution layer structure120.

In some embodiments, as shown inFIG.8DandFIG.8E, the adhesive material A1has a total width L of about 170-1000 um. In some embodiments, the total width L of the adhesive material A1is divided into different types: a width L1(e.g., extending width) on the polymer layer, and a width L2on the passivation layer (including an extending width L21and a bleeding width L22). For example, the width L1on the polymer layer PM1is about 30-250 um, the extending width L21on the passivation layer107is about 50-250 um, the bleeding width L22on the passivation layer107is about 70-250 um or less. In some embodiments, the distance (e.g., keep out zone) from the edge of the adhesive material A1to the sensing regions108is at least about 50 um or more. In some embodiments, as shown inFIG.8D, the adhesive material A1has a total height H2ranging from about 30 um to 90 um. In some embodiments, as shown inFIG.8E, the adhesive material A1has a total height H3ranging from about 30 um to 80 um. In some embodiments, the top surface of the adhesive material A1is substantially level with the top surface of the redistribution layer structure120, as shown inFIG.8D. In other embodiments, the top surface of the adhesive material A1is less than the top surface of the redistribution layer structure120, as shown inFIG.8E.

In some embodiments, as shown inFIG.8F, the adhesive material A1is formed on the lower sidewall S of the redistribution layer structure120. In some embodiments, the adhesive material A1has an unsymmetrical sidewall profile. For example, the adhesive material A1has a substantially vertical sidewall close to the redistribution layer structure120, an inclined sidewall away from the redistribution layer structure120, and a mesa connecting the substantially vertical sidewall and the inclined sidewall. Specifically, the adhesive material A1merely covers the interface I between the polymer layer PM1and the passivation layer107, without covering any exposed polymer step of the redistribution layer structure120. In some embodiments, as shown inFIG.8F, the adhesive material A1has a total width L of about 120-1000 um. In some embodiments, the total width L of the adhesive material A1is the width L2on the passivation layer (including an extending width L21and a bleeding width L22). For example, the extending width L21on the passivation layer107is about 50-250 um, the bleeding width L22on the passivation layer107is about 70-250 um or less. In some embodiments, the distance (e.g., keep out zone) from the edge of the adhesive material A1to the sensing regions108is at least about 50 um or more. In some embodiments, as shown inFIG.8F, the adhesive material A1has a total height H4ranging from about 30 um to 70 um. The top surface of the adhesive material A1is less than the top surface of the redistribution layer structure120, as shown inFIG.8F.

In some embodiments, as shown inFIG.8CtoFIG.8F, the adhesive material A1has a residue RS protruding from a sidewall and/or a top thereof. In some embodiments, the residue RS has a width W1of about 1 to 20 um. In some embodiments, the adhesive material A1has at least one void or bubble B therein. In some embodiments, the bubble B has a width W2of about 1 to 20 um. The void or bubble may be in a vacuum state or filled with air or an inert gas. Multiple residues RS or bubbles B may be distributed randomly with different sizes.

Referring toFIG.9, an adhesive material A2is applied onto the redistribution layer structure120around the exposed metal features (e.g., conductive vias or conductive pillars) of the redistribution layer RDL2.

In some embodiments, the adhesive material A2includes a molding compound, a molding underfill, a resin (e.g., epoxy, silicone or both), or the like. In other embodiments, the adhesive material A2includes a polymer material, such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), or the like. In some embodiments, the adhesive material A2is formed by a stencil printing process with a stencil mask M2with openings OP2corresponding to a location where the adhesive material A2is to be printed. In some embodiments, when the previously formed adhesive material A1is provided with a top surface higher than that of the redistribution layer structure120, the stencil mask M2is designed to have a recess R corresponding to a location where the adhesive material A1is disposed. The recess R does not penetrate through the stencil mask M2. In other embodiments, when the adhesive material A1is formed with a top surface no higher than that of the redistribution layer structure120, the recess resign of the stencil mask M2for the adhesive material A1may be omitted.

In some embodiments, the printing process may be formed by the following processes: a stencil mask M2is placed onto the redistribution layer structure120. The stencil mask M2has openings OP2that expose the redistribution layer RDL2and a portion of the polymer layer PM2adjacent to the redistribution layer RDL2. The printing process is performed using the stencil mask M2, such that the adhesive material A2is applied or printed on the redistribution layer RDL2exposed by the openings OP2of the stencil mask M2. In some embodiments, the adhesive material A2is different from the adhesive material A1. In some embodiments, the flowability of the adhesive material A2is greater than the flowability of the adhesive material A1. In some embodiments, the viscosity of the adhesive material A2is less than the viscosity of the adhesive material A1.

Referring toFIG.10, integrated passive devices130are electrically bonded to metal features of the redistribution layer RDL2of the redistribution layer structure120. The integrated passive devices130are further electrically coupled to the die110through the redistribution layer structure120. Each integrated passive device130may be an integrated passive device (IPD), a surface mount device (SMD), the like, or a combination thereof, but the disclosure is not limited thereto. In some embodiments, each integrated passive device130includes connectors128electrically connected to conductive pads127thereof. The conductive pads127may include metal, such as aluminum, copper, an alloy thereof, or any other suitable metallic material. The connectors128may be solder bumps, solder balls or other suitable metallic connectors. In some embodiments, the connectors128may also be referred to as conductive terminals of the integrated passive device130. The connectors128are electrically bonded to the redistribution layer RDL2.

In some embodiments, the mounting of the integrated passive devices130includes: placing the integrated passive device130onto the redistribution layer RDL2, and the adhesive material A2may be pushed outward to surround the connectors128and/or the conductive pads127of the integrated passive device130and the redistribution layer RDL2. Thereafter, a reflow process P2is performed. In some embodiments, the reflow process P2is performed at a temperature of about 200° C. to 300° C. for about 5 minutes to 15 minutes. During the reflow process, a portion of the adhesive material A2is reacted with connectors128to facilitate the bonding process, and the other portion of the adhesive material A2is unreacted and remained as a filling layer. The adhesive material A2is referred to a “flux material”, “filling layer” or “underfill layer” in some examples.

As shown inFIG.10, the adhesive material A2is configured to fill the space between the integrated passive device13, laterally surround the connectors128and/or the conductive pads127of the integrated passive device130, and may further laterally surround a portion of the redistribution layer RDL2of the redistribution layer structure120.

Referring toFIG.11, the carrier100is de-bonded from the backside of the structure ofFIG.10. In some embodiments, the de-bonding layer101is decomposed under heat of light, and the carrier100is then released from the structure formed thereon.

Thereafter, the dielectric layer102is patterned such that openings136are formed to expose the bottom surfaces of the conductive vias103. In some embodiments, the number of the openings136corresponds to the number of the conductive vias103. In some embodiments, the openings of the dielectric layer102are formed by a laser drilling process or another suitable patterning process.

In some embodiments, a plasma cleaning process may be performed to the openings136of the dielectric layer102, and connectors138are formed on the dielectric layer102and fill into the openings136to electrically connect to the conductive vias103. The connectors138may be conductive balls, micro bumps, or the like, or combinations thereof. In some embodiments, the connectors138are solder balls formed by a suitable technique, such as ball mounting process, or a printing process followed by a reflow process. The connectors138are electrically connected to the die110through the conductive vias103and the redistribution layer structure120. A package structure PKG1is thus formed at this stage.

In some embodiments, another package including a device (e.g., memory device, logic device or another suitable semiconductor device) or a board (e.g., printed circuit board) is provided and bonded to the package structure PKG1through the connectors138.

FIG.14illustrates a cross-sectional view of a package structure according to other embodiments of the disclosure. The present embodiment is similar to the foregoing embodiment inFIG.11, except that the encapsulation layer112adoes not cover the first surface FS of the die110.

Referring toFIG.14, as described above inFIG.11, in some embodiments, the sacrificial layer109may be formed to cover the entire surface of the passivation layer107and the conductive pads106of the die110, and the encapsulation layer112amay be formed laterally aside the die110without covering the first surface FS of the die110. In such an embodiment, the redistribution layer structure120is accordingly formed to cover a portion of the first surface FS the die110and laterally surrounded by the encapsulation layer112a. For example, a portion of the polymer layer PM1is formed to cover and physically contact the conductive pads106and a portion of the passivation layer107. The conductive vias V1may merely penetrate through the polymer layer PM1to connect to the conductive pads106. The other features of the package structure PKG2are substantially the same as those of the package structure PKG1described inFIG.11, which are not described again here.

In the above embodiments, the interface sealing structure (e.g., adhesive material A1) and the underfill layer (e.g., adhesive material A2) are performed separately with different materials by two printing processes. However, the disclosure is not limited thereto. In other embodiments, the interface sealing protection structure and the unerfill layer can be formed with the same material by a single printing process.

FIGS.15to17illustrate schematic cross-sectional views of manufacturing a package structure in accordance with other embodiments of the disclosure.

In some embodiments, after the operations ofFIG.1toFIG.6Bare implemented, as shown inFIG.15toFIG.16, an adhesive material A21is applied onto the redistribution layer structure120around the interface I between the polymer layer PM1and the passivation layer107, and an adhesive material A22is applied onto the redistribution layer structure120around the exposed metal features (e.g., conductive vias or conductive pillars) of the redistribution layer RDL2.

In some embodiments, the adhesive materials A21and A22are formed of the same material by the same printing process. In some embodiments, each of the adhesive materials A21and A22includes a molding compound, a molding underfill, a resin (e.g., epoxy, silicone or both), or the like. In other embodiments, the adhesive material A1includes a polymer material, such as polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), or the like. In some embodiments, an adhesive material A21is formed by a stencil printing process with a stencil mask M2′ with openings OP21corresponding to a location where the adhesive material A21is to be printed, and an adhesive material A22is formed by the same stencil printing process with the same stencil mask M2′ with openings OP22corresponding to a location where the adhesive material A22is to be printed.

In some embodiments, a printing process may be formed by the following processes: a stencil mask M2′ is placed onto the redistribution layer structure120. The stencil mask M2′ has openings OP21that expose the interface I between the polymer layer PM1and the passivation layer107, and openings OP21that expose the redistribution layer RDL2and a portion of the polymer layer PM2adjacent to the redistribution layer RDL2. The printing process is performed using the stencil mask M2′, such that the adhesive material A21is applied or printed at the interface I between the polymer layer PM1and the passivation layer107exposed by the openings OP21of the stencil mask M2′, and the adhesive material A22is applied or printed on the redistribution layer RDL2exposed by the openings OP22of the stencil mask M2′.

Referring toFIG.16, the mounting of the integrated passive devices130includes placing the integrated passive device130onto the redistribution layer RDL2, and the adhesive material A2may be pushed outward to surround the connectors128and/or the conductive pads127of the integrated passive device130and the redistribution layer RDL2. Thereafter, a reflow process P2is performed. In some embodiments, the reflow process P2is performed at a temperature of about 200° C. to 300° C. for about 5 minutes to 15 minutes. During the reflow process, the adhesive material A22is hardened to serve as a sealing protection structure at the interface between the polymer layer PM1and the passivation layer107, a portion of the adhesive material A22is reacted with connectors128to facilitate the bonding process, and the other portion of the adhesive material A22is unreacted and remained as a filling layer.

Referring toFIG.17, the operation similar to the operation inFIG.11is implemented, so as to form a package structure PKG3.

FIG.18illustrates a cross-sectional view of a package structure PKG4according to other embodiments of the disclosure. The present embodiment is similar to the foregoing embodiment inFIG.17, except that the encapsulation layer112adoes not cover the first surface FS of the die110.

In some embodiments, the adhesive material A21inFIGS.17-18has a top surface higher than that of the top surface of the redistribution layer structure120, but the disclosure is not limited thereto. The adhesive material A21inFIGS.17-18may have a top surface equal to or less than that of the top surface of the redistribution layer structure120, and the profiles of adhesive material A21are similar to those described inFIG.8DtoFIG.8F. Besides, the adhesive material A21may have at least one bubble and/or at least one residue, similar to those described inFIG.8CtoFIG.8F. Besides, the adhesive material A21has an enclosed shape in a top view, similar to the adhesive material A1described inFIG.8B.

FIG.19illustrates a method of forming a package structure in accordance with some embodiments. Although the method is illustrated and/or described as a series of acts or events, it will be appreciated that the method is not limited to the illustrated ordering or acts. Thus, in some embodiments, the acts may be carried out in different orders than illustrated, and/or may be carried out concurrently. Further, in some embodiments, the illustrated acts or events may be subdivided into multiple acts or events, which may be carried out at separate times or concurrently with other acts or sub-acts. In some embodiments, some illustrated acts or events may be omitted, and other un-illustrated acts or events may be included.

At act202, a die is attached to a carrier, wherein the die has a passivation layer on a first side thereof.FIG.1toFIG.2illustrate varying views corresponding to some embodiments of act202.

At act204, an encapsulation layer is formed to encapsulate a sidewall of the die.FIG.3toFIG.5illustrate varying views corresponding to some embodiments of act204.

At act206, a redistribution layer structure is formed on the encapsulation layer and the die, wherein the redistribution layer structure is in physical contact with a portion of the passivation layer of the die.FIG.6AtoFIG.6Billustrate varying views corresponding to some embodiments of act206.

At act208, a sealing protection structure is formed to cover at least an interface between the redistribution layer structure and the passivation layer.FIG.7AtoFIG.8Fillustrate varying views corresponding to some embodiments of act208.

In some embodiments, a method (e.g., the method shown inFIG.7AtoFIG.8F) of forming the sealing protection structure includes performing a stencil printing process and a screen printing process. In some embodiments, the method further includes, after performing the stencil printing process or the screen printing process, performing a curing process at a temperature of 120° C. to 150° C. for about 1 hour to 2 hours.

In other embodiments, a method (e.g., the method shown inFIG.15toFIG.16) of forming the sealing protection structure includes performing a stencil printing process. In some embodiments, the method further includes, after performing the stencil printing process, performing a reflow process at a temperature of 200° C. to 300° C. for about 5 minutes to 15 minutes.

At act210, an integrated passive device is bonded to the redistribution layer structure.FIG.9toFIG.10andFIG.16illustrate varying views corresponding to some embodiments of act210.

At act212, the die is released from the carrier.FIG.11andFIG.17illustrate cross-sectional views corresponding to some embodiments of act212.

At act214, conductive terminals are formed at a second side of the die opposite to the first side.FIG.11andFIG.17illustrate cross-sectional views corresponding to some embodiments of act214.

The structures of the disclosure are described below with reference toFIG.1toFIG.18.

In some embodiments, as shown inFIG.11,FIG.14,FIG.17andFIG.18, a package structure PKG1/PKG2/PKG3/PKG4includes a die110, an encapsulation layer112a, a redistribution layer structure120and an adhesive material A1/A21. The die110includes a semiconductor substrate105, conductive pads106disposed over the semiconductor substrate105and a passivation layer107disposed over the semiconductor substrate105and around the conductive pads106. The encapsulation layer112alaterally encapsulates the die110. The redistribution layer structure120is disposed on the die110and the encapsulation layer112a, and includes at least one redistribution layer RDL1/RDL2embedded in at least one polymer layer PM1/PM2, and the polymer layer PM1contacts a portion of the passivation layer107. The adhesive material A1/A21is disposed on the die110and covers an interface I between the polymer layer PM1and the passivation layer107.

In some embodiments, the adhesive material A1has an enclosed shape in a top view, as shown inFIG.8B.

In some embodiments, the die110has at least one sensing region108extending from a top surface107aof the passivation layer107to the semiconductor substrate105, and the adhesive material A1/A21is separated from the at least one sensing region108by a non-zero horizontal distance

In some embodiments, a top surface of the adhesive material is higher than a top surface of the redistribution layer structure, as shown inFIG.8C. In some embodiments, a top surface of the adhesive material is substantially level with a top surface of the redistribution layer structure, as shown inFIG.8D. In some embodiments, a top surface of the adhesive material is lower than a top surface of the redistribution layer structure, as shown inFIG.8EandFIG.8F.

In some embodiments, the adhesive material A1/A21has at least one residue RS protruding from a sidewall or a top surface thereof. In some embodiments, the adhesive material A1/A21has at least one void or bubble B therein.

In some embodiments, the package structure PKG1/PKG2/PKG3/PKG4further includes an integrated passive device130disposed on and electrically bonded to the redistribution layer structure120.

In some embodiments, the encapsulation layer112aextends onto a portion of the passivation layer107. In some embodiments, the vias V1of the redistribution layer structure120penetrate through the encapsulation layer112aand are electrically connected to the conductive pads106of the die110.

In some embodiments, as shown inFIG.11,FIG.14,FIG.17andFIG.18, a package structure PKG1/PKG2/PKG3/PKG4includes a die110, an encapsulation layer112a, a redistribution layer structure120and a sealing protection structure (e.g., adhesive material A1/A21). The die110has a first surface FS. The encapsulation layer112aencapsulates a sidewall of the die110. the redistribution layer structure120is disposed on the encapsulation layer112aand defines an opening121that exposes a portion of the first surface of the die110. The sealing protection structure (e.g., adhesive material A1/A21) is disposed on the die110and along a sidewall S of the opening121defined by the redistribution layer structure120.

In some embodiments, the sealing protection structure includes epoxy, silicone or epoxy-silicone hybrid resin. For example, the adhesive material A1may be epoxy-silicone hybrid resin. For example, the adhesive material A21may be epoxy.

In some embodiments, the package structure PKG1/PKG2/PKG3/PKG4further includes an integrated passive device130disposed on and electrically bonded to the redistribution layer structure120. In some embodiments, a filling layer (e.g., adhesive material A2/A22) is disposed to fill a space between the integrated passive device130and the redistribution layer structure120, and the filling layer laterally surrounds a connector128of the integrated passive device130and a conductive pillar (e.g., RDL2) of the redistribution layer structure120.

In some embodiments, an edge of the encapsulation layer112ais aligned with the sidewall of the die110, as shown inFIG.14andFIG.18.

In some embodiments, the sealing protection structure (e.g., adhesive material A2/A22) has a stepped sidewall close to the redistribution layer structure120, an inclined sidewall away from the redistribution layer structure120, as shown inFIG.8CandFIG.8E.

In some embodiments of the disclosure, an adhesive material is configured to provide sealing protection for the interface between two different materials (e.g., between the polymer layer and the passivation layer), so as to prevent the film delamination issue and therefore improve the reliability of the device. The adhesive material may be one or mix of several kinds of polymer. In some embodiments, the adhesive material may be an epoxy-silicone hybrid resin. In other embodiments, the adhesive material may be an epoxy resin. Other polymer may be used instead of the epoxy-based adhesive material. In some embodiments, one of two different materials includes silicon nitride, silicon, silicon carbide, or the like, and the other of the two different materials includes low-temperature polyimide (LTPI), solder mask, or the like.

In accordance with some embodiments of the disclosure, a package structure includes a die, an encapsulation layer, a redistribution layer structure and an adhesive material. The die includes a semiconductor substrate, conductive pads disposed over the semiconductor substrate and a passivation layer disposed over the semiconductor substrate and around the conductive pads. The encapsulation layer laterally encapsulates the die. the redistribution layer structure is disposed on the die and the encapsulation layer, and includes at least one redistribution layer embedded in at least one polymer layer, and the polymer layer contacts a portion of the passivation layer. The adhesive material is disposed on the die and covers an interface between the polymer layer and the passivation layer.

In accordance with other embodiments of the disclosure, a package structure includes a die, an encapsulation layer, a redistribution layer structure and a sealing protection structure. The die has a first surface. The encapsulation layer encapsulates a sidewall of the die. the redistribution layer structure is disposed on the encapsulation layer and defines an opening that exposes a portion of the first surface of the die. The sealing protection structure is disposed on the die and along a sidewall of the opening defined by the redistribution layer structure.

In accordance with some embodiments of the disclosure, a method of forming a package structure includes: attaching a die to a carrier, wherein the die has a passivation layer on a first side thereof; forming an encapsulation layer to encapsulate a sidewall of the die; forming a redistribution layer structure on the encapsulation layer and the die, wherein the redistribution layer structure is in physical contact with a portion of the passivation layer of the die; and forming a sealing protection structure to cover at least an interface between the redistribution layer structure and the passivation layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the disclosure.