Patent ID: 12237342

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor device comprises: an insulating substrate; a first semiconductor layer located above the insulating substrate; a second semiconductor layer located above the insulating substrate and formed of a material different from a material of the first semiconductor layer; an insulating layer which is located above the insulating substrate, covers the first semiconductor layer and the second semiconductor layer, and comprises a first contact hole reaching the first semiconductor layer and a second contact hole reaching the second semiconductor layer; a barrier layer which covers one of the first semiconductor layer inside the first contact hole and the second semiconductor layer inside the second contact hole, and is conductive; and a first conductive layer which is in contact with the barrier layer.

According to another embodiment, a method for manufacturing a semiconductor device comprises: an insulating substrate; a first insulating layer; a second insulating layer located above the first insulating layer; a first semiconductor layer located between the insulating substrate and the first insulating layer; and a second semiconductor layer located between the first insulating layer and the second insulating layer and formed of a material different from a material of the first semiconductor layer, the method comprising: forming a first contact hole in the second insulating layer so as to reach the second semiconductor layer; forming a barrier layer on the second insulating layer and on the second semiconductor layer inside the first contact hole; forming a second contact hole in the barrier layer, the first insulating layer and the second insulating layer so as to reach the first semiconductor layer; and forming a first conductive layer which is in contact with the barrier layer inside the first contact hole, and is in contact with the second semiconductor layer inside the second contact hole, wherein the barrier layer is conductive.

According to another embodiment, a method for manufacturing a semiconductor device comprises: an insulating substrate; a first insulating layer; a second insulating layer located above the first insulating layer; a first semiconductor layer located between the insulating substrate and the first insulating layer; and a second semiconductor layer located between the first insulating layer and the second insulating layer and formed of a material different from a material of the first semiconductor layer, the method comprising: forming a first contact hole in the first insulating layer and the second insulating layer so as to reach the first semiconductor layer; forming a barrier layer on the second insulating layer and on the first semiconductor layer inside the first contact hole; forming a second contact hole in the barrier layer and the second insulating layer so as to reach the second semiconductor layer; and forming the first conductive layer which is in contact with the barrier layer inside the first contact hole, and is in contact with the second semiconductor layer inside the second contact hole, wherein the barrier layer is conductive.

Embodiments will be described hereinafter with reference to the accompanying drawings. The disclosure is merely an example, and proper changes in keeping with the spirit of the invention, which are easily conceivable by a person of ordinary skill in the art, come within the scope of the invention as a matter of course. In addition, in some cases, in order to make the description clearer, the widths, thicknesses, shapes, etc., of the respective parts are illustrated schematically in the drawings, rather than as an accurate representation of what is implemented. However, such schematic illustration is merely exemplary, and in no way restricts the interpretation of the invention. In addition, in the specification and drawings, structural elements which function in the same or a similar manner to those described in connection with preceding drawings are denoted by like reference numbers, detailed description thereof being omitted unless necessary.

In the explanation of the embodiments, an upward direction (or upper side) is equivalent to the direction of arrow Z. A downward direction (or lower side) is equivalent to a direction opposite to that of arrow Z.

FIG.1is a cross-sectional view showing an example of the structure of a semiconductor device1according to a first embodiment. The semiconductor device1shown inFIG.1is a thin-film transistor (TFT) substrate comprising a plurality of thin-film transistors TR1and TR2.

The semiconductor device1comprises an insulating substrate10, an undercoat layer UC, a semiconductor layer SC1, an insulating film11, a gate electrode ML1, a metal layer SL, an insulating film12, an insulating film13, a semiconductor layer SC2, an insulating film14, a gate electrode ML2, and an insulating film15. In the following explanation, the undercoat layer UC and insulating films11,12,13,14and15stacked on the insulating substrate10may be collectively called an insulating layer IL. In the insulating layer IL, insulating films11,12and13located between semiconductor layers SC1and SC2may be called an insulating interlayer. Insulating films11,12and13may be collectively called a first insulating layer. Insulating films14and15may be collectively called a second insulating layer.

The insulating substrate10is formed of, for example, a phototransmissive glass substrate or resin substrate. The undercoat layer UC is an insulating layer, and is located on the insulating substrate10. The undercoat layer UC may have either a single-layer structure or a multilayer structure. For example, the undercoat layer UC comprises a silicon nitride film and a silicon oxide film.

Semiconductor layer SC1is located above the insulating substrate10. In the example ofFIG.1, semiconductor layer SC1is formed on the undercoat layer UC. Semiconductor layer SC1is a silicon semiconductor. For example, semiconductor layer SC1is formed of polycrystalline silicon. Semiconductor layer SC1comprises a high-resistive area SCc1, and low-resistive areas SCa1and SCb1in which the electric resistance is lower than that of high-resistive area SCc1. Although not shown in the drawings, a light-shielding film may be provided between the insulating substrate10and semiconductor layer SC1.

Insulating film11covers semiconductor layer SC1. In the example ofFIG.1, insulating film11is located on the undercoat layer UC as well as semiconductor layer SC1. For example, insulating film11is formed of silicon oxide.

Gate electrode ML1is located on insulating film11, and faces semiconductor layer SC1via insulating film11. Gate electrode ML1faces high-resistive area SCc1of semiconductor layer SC1. The metal layer SL is located on insulating film11, and is located away from gate electrode ML1. Each of gate electrode ML1and the metal layer SL is formed of a conductive metal material. In the example ofFIG.1, gate electrode ML1and the metal layer SL are located in the same layer. Therefore, they may be simultaneously formed using the same material. Gate electrode ML1is electrically connected to a first scanning line (not shown). The metal layer SL is located right under semiconductor layer SC2. The metal layer SL may function as a light-shielding film which prevents irradiation of semiconductor layer SC2with light having passed through the insulating substrate10and the undercoat layer UC. The metal layer SL may function as a gate electrode. The metal layer SL may function as the electrode of storage capacitance. The pattern area of the metal layer SL may be changed depending on the purpose. When the metal layer SL functions as a light-shielding film, the metal layer SL may be replaced by a layer formed of a material other than metal. When the semiconductor device1is applied to an organic electroluminescent (EL) display device, the metal layer SL may be omitted.

Insulating film12is located on insulating film11, and covers gate electrode ML1and the metal layer SL. For example, insulating film12is formed of silicon nitride.

Insulating film13is located on insulating film12. In the example ofFIG.1, insulating film13is located between insulating films12and14. For example, insulating film13is formed of silicon oxide.

With respect to the insulating substrate10, semiconductor layer SC2is located on an upper side in comparison with semiconductor layer SC1. In the example ofFIG.1, semiconductor layer SC2is located on insulating film13, and faces the metal layer SL via insulating films12and13. Semiconductor layer SC2is a semiconductor formed of metal oxide. In terms of semiconductivity, the metal oxide of semiconductor layer SC2preferably contains at least one metal selected from indium, gallium, zinc and tin. Semiconductor layer SC2comprises a high-resistive area SCc2, and low-resistive areas SCa2and SCb2in which the electric resistance is lower than that of high-resistive area SCc2.

Insulating film14is located on insulating film13, and covers semiconductor layer SC2. For example, insulating film14is formed of silicon oxide.

Gate electrode ML2is located on insulating film14, and faces semiconductor layer SC2via insulating film14. Gate electrode ML2faces high-resistive area SCc2of semiconductor layer SC2. Gate electrode ML2is formed of a conductive metal material. Gate electrode ML2is electrically connected to a second scanning line (not shown). Insulating film15covers gate electrode ML2. In the example ofFIG.1, insulating film15is located on insulating film14as well as gate electrode ML2. Insulating film15may have either a single-layer structure or a multilayer structure. For example, insulating film15is formed of silicon nitride or silicon oxide.

The semiconductor device1further comprises terminals T1a, T1b, T2a, T2band T3. Terminals T1a, T1b, T2a, T2band T3are located on insulating film15. Terminals T1a, T1b, T2a, T2band T3are electrically connected to lines (not shown), etc. In the example ofFIG.1, terminals T1a, T1b, T2a, T2band T3comprise barrier layers BC1a, BC1b, BC2a, BC2band BC3, respectively, and conductive layers MC1a, MC1b, MC2a, MC2band MC3, respectively.

Barrier layers BC1a, BC1b, BC2a, BC2band BC3are formed of the same conductive metal, alloy or low-resistive oxide. In the present embodiment, a barrier layer BC is preferably resistant to a material used for cleaning in the manufacturing method explained later, such as hydrofluoric acid. Barrier layers BC1a, BC1b, BC2a, BC2band BC3may have either a single-layer structure or a multilayer structure, and are formed of, for example, titanium (Ti). Barrier layers BC1a, BC1b, BC2a, BC2band BC3may be called conductive layers.

Conductive layers MC1a, MC1b, MC2a, MC2band MC3are formed of, for example, a conductive metal material, and may have either a single-layer structure or a multilayer structure. For example, conductive layers MC1a, MC1b, MC2a, MC2band MC3have a multilayer structure of titanium/aluminum/titanium.

As seen in plan view, the end portions of terminals T1a, T1b, T2a, T2band T3are formed such that conductive layers MC1a, MC1b, MC2a, MC2band MC3overlap barrier layers BC1a, BC1b, BC2a, BC2band BC3.

Terminals T1aand T1bcover the inside of contact holes CH1aand CH1b, respectively, penetrating insulating films11,12,13,14and15, and are electrically connected to semiconductor layer SC1. In the following explanation, the surface including insulating films11,12,13,14and15inside contact hole CH1ais called a side surface S1a. The surface including insulating films11,12,13,14and15inside contact hole CH1bis called a side surface S1b. In the example ofFIG.1, with respect to terminals T1aand T1b, barrier layers BC1aand BC1bare located on the top surface TP of insulating film15(or the insulating layer IL) on which contact holes CH1aand CH1bare formed. Neither barrier layer BC1anor barrier layer BC1bis present on semiconductor layer SC1in contact hole CH1aor CH1b. Above insulating film15, conductive layers MC1aand MC1bare partially located on barrier layers BC1aand BC1b.Conductive layers MC1aand MC1bcover inner surface S1aof contact hole CH1aand inner surface S1bof contact hole CH1b, and cover semiconductor layer SC1inside contact holes CH1aand CH1b. Conductive layer MC1ais in contact with inner surface S1aand low-resistive area SCa1in contact hole CH1a. Conductive layer MC1bis in contact with inner surface S1band low-resistive area SCb1in contact hole CH1b. The thickness of the layer of each of terminals T1aand T1bmay differ between the top surface TP of insulating film15and the inside of contact hole CH1aor CH1b.

Terminals T2aand T2bcover the inside of contact holes CH2aand CH2b, respectively, penetrating insulating films14and15, and are electrically connected to semiconductor layer SC2. In the following explanation, the surface including insulating films14and15inside contact hole CH2ais called a side surface S2a. The surface including insulating films14and15inside contact hole CH2bis called a side surface S2b. In the example ofFIG.1, with respect to terminals T2aand T2b, barrier layers BC2aand BC2bare partially located on the top surface TP of insulating film15, cover inner surface S2aof contact hole CH2aand inner surface S2bof contact hole CH2b, and cover semiconductor layer SC2inside contact holes CH2aand CH2b. Conductive layers MC2aand MC2bare located on barrier layers BC2aand BC2babove insulating film15, and are located on barrier layers BC2aand BC2binside contact holes CH2aand CH2b. Barrier layer BC2ais in contact with inner surface S2aand low-resistive area SCa2in contact hole CH2a. Conductive layer MC2ais in contact with barrier layer BC2ain contact hole CH2a. Barrier layer BC2bis in contact with inner surface S2band low-resistive area SCb2in contact hole CH2b. Conductive layer MC2bis in contact with barrier layer BC2bin contact hole CH2b.

Terminal T3covers the inside of contact hole CH3penetrating insulating films12,13,14and15, and is electrically connected to the metal layer SL. In the following explanation, the surface including insulating films12,13,14and15inside contact hole CH3is called a side surface S3. In the example ofFIG.1, with respect to terminal T3, barrier layer BC3is located on the top surface TP of insulating film15, and is not present in contact hole CH3. Above insulating film15, conductive layer MC3is partially located on barrier layer BC3. Conductive layer MC3covers inner surface S3of contact hole CH3, and covers the metal layer SL inside contact hole CH3. The thickness of the layer of terminal T3may differ between on insulating film15and inside contact hole CH3. For example, terminal T3may be electrically connected to the power line of fixed potential and a scanning line (not shown). When terminal T3is connected to the power line, the metal layer SL is configured to function as a light-shielding film, a capacitive electrode, etc. When terminal T3is electrically connected to a scanning line, the metal layer SL is configured to functions as the gate electrode of thin-film transistor TR2. The metal layer SL may be electrically floating. In this case, terminal T3and contact hole CH3may be omitted.

In the example ofFIG.1, thin-film transistors TR1and TR2have a top-gate structure in which gate electrodes ML1and ML2are located above semiconductor layers SC1and SC2, respectively. However, the structures of thin-film transistors TR1and TR2are not particularly limited. Thin-film transistors TR1and TR2may have a bottom-gate structure.

Now, this specification explains a method for manufacturing the semiconductor device1of the present embodiment, referring toFIG.2A,FIG.2B,FIG.2CandFIG.2D.

FIG.2Ais a cross-sectional view showing a step for forming contact holes CH2aand CH2baccording to the present embodiment.FIG.2Bis a cross-sectional view showing a step for forming barrier layer BC according to the present embodiment.FIG.2Cis a cross-sectional view showing a step for forming contact holes CH1aand CH1baccording to the present embodiment.FIG.2Dis a cross-sectional view showing a step for forming a conductive layer MC according to the present embodiment.

As shown inFIG.2A, contact holes CH2aand CH2bare formed after the insulating layer IL, semiconductor layers SC1and SC2, the metal layer SL and gate electrodes ML1and ML2are formed on the insulating substrate10. More specifically, a photoresist patterned by a photolithography process is formed on insulating film15. Subsequently, contact holes CH2aand CH2bare formed in the insulating layer IL to semiconductor layer SC2by a photo-etching process (hereinafter, simply referred to as photo-etching) for etching the area exposed from the photoresist.

Subsequently, as shown inFIG.2B, barrier layer BC is formed on the insulating layer IL in the state shown inFIG.2A, and is formed on semiconductor layer SC2via inner surface S2aof contact hole CH2aand inner surface S2bof contact hole CH2b. Barrier layer BC is a layer in a state before processing into barrier layers BC1a, BC1b, BC2a, BC2band BC3.

Subsequently, as shown inFIG.2C, contact holes CH1aand CH1bare formed by etching barrier layer BC and the insulating layer IL all together so as to reach semiconductor layer SC1. For example, photo-etching is used for this process. Subsequently, cleaning using, for example, hydrofluoric acid (HF), is performed to remove the natural oxide film of semiconductor layer SC1, such as a silicon (Si) oxide film. At this time, semiconductor layer SC2is protected by barrier layer BC from hydrofluoric acid as a substance for cleaning. As shown inFIG.2C, when contact holes CH1aand CH1bare formed, contact hole CH3may be formed by applying photo-etching to barrier layer BC and the insulating layer IL all together so as to reach the metal layer SL in a manner similar to that of contact holes CH1aand CH1b.

As shown inFIG.2D, conductive layer MC is formed on barrier layer BC shown inFIG.2C, and is formed on semiconductor layer SC1via inner surface S1aof contact hole CH1aand inner surface S1bof contact hole CH1b. Conductive layer MC is formed on barrier layer BC shown inFIG.2C, and is formed on the metal layer SL via inner surface S3of contact hole CH3. Conductive layer MC is a layer in a state before processing into conductive layers MC1a, MC1b, MC2a, MC2band MC3. Lastly, barrier layer BC and conductive layer MC shown inFIG.2Dare patterned all together by, for example, photo-etching. In this way, for example, terminals T1a, T1b, T2a, T2band T3of the semiconductor device1shown inFIG.1are formed.

As explained above, according to the present embodiment, contact holes CH1aand CH1bare formed by etching barrier layer BC and the insulating layer IL all together after barrier layer BC is formed in contact holes CH2aand CH2b. Thus, in the semiconductor device1, the natural oxide film of semiconductor layer SC1formed of polycrystalline silicon can be removed by cleaning in a state where oxide semiconductor layer SC2is protected. Since barrier layer BC is conductive, there is no need to remove barrier layer BC from contact hole CH2aor CH2b. Thus, it is possible to form terminals T2aand T2belectrically connected to semiconductor layer SC2. Moreover, the number of manufacturing steps can be reduced by etching barrier layer BC and the insulating layer IL all together. When thin-film transistor TR2has a top-gate structure in the semiconductor device1, a step for forming, on semiconductor layers SCa2and SCb2, a conductive layer which prevents the contact holes from penetrating the semiconductor layers at the time of forming the contact holes, such as a metal layer, is not required. Thus, the semiconductor device1can prevent decrease in reliability and improve productivity.

Now, this specification explains semiconductor devices according to other embodiments. In the following embodiments, the same elements as those of the first embodiment are denoted by the same reference numbers, detailed description thereof being omitted. Elements different from those of the first embodiment are mainly explained in detail. Effects similar to those of the first embodiment can be obtained by the following embodiments.

FIG.3is a cross-sectional view showing an example of the structure a semiconductor device according to a second embodiment. The semiconductor device1of the second embodiment is different from that of the first embodiment in terms of the positions of barrier layers BC1a, BC1b, BC2aand BC2band conductive layers MC1a, MC1b, MC2aand MC2b. In the example ofFIG.3, neither a contact hole CH3nor a terminal T3is provided in the semiconductor device1. However, the semiconductor device1may comprises these elements in the same manner as that of the second embodiment.

In the example ofFIG.3, with regard to terminals Tia and T1b, barrier layers BC1aand BC1bare partially located on the top surface TP of an insulating film15, cover an inner surface Sla of a contact hole CH1aand an inner surface Sib of a contact hole CH1b, and cover a semiconductor layer SC1inside contact holes CH1aand CH1b. Conductive layers MC1aand MC1bare located on barrier layers BC1aand BC1b, respectively. In the example ofFIG.3, with regard to terminals T2aand T2b, barrier layers BC2aand BC2bare located on the top surface TP of insulating film15on which contact holes CH2aand CH2bare formed. Neither barrier layer BC2anor barrier layer BC2bis present inside contact hole CH2aor CH2b. Conductive layers MC2aand MC2bare partially located on barrier layers BC2aand BC2b, cover an inner surface S2aof contact hole CH2aand an inner surface S2bof contact hole CH2b, and cover a semiconductor layer SC2inside contact holes CH2aand CH2b.

Now, this specification explains a method for manufacturing the semiconductor device1of the present embodiment, referring toFIG.4A,FIG.4B,FIG.4CandFIG.4D.

FIG.4Ais a cross-sectional view showing a step for forming contact holes CH1aand CH1baccording to the present embodiment.FIG.4Bis a cross-sectional view showing a step for forming a barrier layer BC according to the present embodiment.FIG.4Cis a cross-sectional view showing a step for forming contact holes CH2aand CH2baccording to the present embodiment.FIG.4Dis a cross-sectional view showing a step for forming a conductive layer MC according to the present embodiment.

As shown inFIG.4A, contact holes CH1aand CH1bare formed in an insulating layer IL so as to reach semiconductor layer SC1by photo-etching (or a photo-etching process). Subsequently, cleaning is performed to remove the natural oxide film of semiconductor layer SC1.

Subsequently, as shown inFIG.4B, to prevent oxidation of semiconductor layer SC1, barrier layer BC is formed on the insulating layer IL in the state shown inFIG.4A, and is formed on semiconductor layer SC1via inner surface Sla of contact hole CH1aand inner surface S1bof contact hole CH1b.

Subsequently, as shown inFIG.4C, contact holes CH2aand CH2bare formed by etching barrier layer BC and the insulating layer IL all together to semiconductor layer SC2. For example, photo-etching is used for this process.

Further, as shown inFIG.4D, conductive layer MC is formed on barrier layer BC in the state shown inFIG.4C, and is formed on semiconductor layer SC2via inner surface S2aof contact hole CH2aand inner surface S2bof contact hole CH2b. Lastly, barrier layer BC and conductive layer MC shown inFIG.4Dare patterned all together by, for example, photo-etching. In this way, for example, terminals T1a, T1b, T2aand T2bof the semiconductor device1ofFIG.3are formed.

Effects similar to those of the first embodiment are obtained by the second embodiment.

FIG.5is a cross-sectional view showing an example of the structure of a semiconductor device according to a third embodiment.

The semiconductor device1of the third embodiment is different from that of the above embodiments in respect that the distance between thin-film transistors TR1and TR2is shorter than that of the above embodiments.

The semiconductor device1of the present embodiment comprises a contact hole CH12bformed inside the edge of a contact hole CH12a, and comprises a terminal T12in place of terminals T1band T2aof the above embodiments. Terminal T12comprises a barrier layer BC12and a conductive layer MC12. Terminal T12covers the inside of contact holes CH12aand CH12b, and is electrically connected to semiconductor layers SC1and SC2. The surface including insulating films14and15inside contact hole CH12ais called a side surface S12a. The surface including insulating films11and12inside contact hole CH12bis called a side surface S12b. In the example ofFIG.5, with respect to terminal T12, barrier layer BC12is partially located on insulating film15, covers inner surface S12aof contact hole S12a, and covers semiconductor layer SC2inside contact hole CH12a. Above insulating film15, conductive layer MC12is partially located on barrier layer BC12. Conductive layer MC12covers inner surface S12bof contact hole S12b, and covers semiconductor layer SC1inside contact hole CH12bformed inside the edge of contact hole CH12a. Thus, conductive layer MC12electrically connects semiconductor layers SC1and SC2.

FIG.6is a plan view when terminal T12is viewed from line A-A ofFIG.5.

As shown inFIG.6, contact holes CH12aand CH12bare formed so as to overlap each other in a plan view. Contact holes CH12aand CH12bdo not need to entirely overlap each other in a plan view. Contact holes CH12aand CH12bshould be at least partially overlap each other. As shown inFIG.6, in terminal T12, the end surfaces of barrier layer BC12and conductive layer MC12are formed so as to be aligned with each other in a plan view.

Now, this specification explains a method for manufacturing the semiconductor device1of the present embodiment, referring toFIG.7A,FIG.7B,FIG.7CandFIG.7D. A manufacturing process similar to that of the first embodiment can be used to manufacture terminals T1aand T2b. Thus, detailed description thereof is omitted.

FIG.7Ais a cross-sectional view showing a step for forming contact hole CH12aaccording to the present embodiment.FIG.7Bis a cross-sectional view showing a step for forming a barrier layer BC according to the present embodiment.FIG.7Cis a cross-sectional view showing a step for forming contact hole CH12baccording to the present embodiment.FIG.7Dis a cross-sectional view showing a step for forming a conductive layer MC according to the present embodiment.

As shown inFIG.7A, contact hole CH12ais formed in an insulating layer IL to semiconductor layer SC2by photo-etching (or a photo-etching process). In the example ofFIG.7A, contact hole CH12ais formed by etching insulating films14and15from the portion above a low-resistive area SCa2of semiconductor layer SC2to the portion above semiconductor layer SC1. Contact hole HC12ais wider than contact hole CH2aof the above embodiments.

Subsequently, as shown inFIG.7B, barrier layer BC is formed on the insulating layer IL in the state shown inFIG.7A, and is formed on semiconductor layer SC2via inner surface S12aof contact hole CH12a.

Subsequently, as shown inFIG.7C, contact hole CH12bis formed by etching barrier layer BC and the insulating layer IL all together to semiconductor layer SC1in the bottom portion inside the edge of contact hole CH12a. For example, photo-etching is used for this process. Subsequently, cleaning is performed to remove the natural oxide film of semiconductor layer SC1.

Further, as shown inFIG.7D, conductive layer MC is formed on barrier layer BC shown inFIG.7C, and is formed on semiconductor layer SC1via inner surface S12aof contact hole CH12aand inner surface S12bof contact hole CH12b. Lastly, barrier layer BC and conductive layer MC shown inFIG.7Dare patterned all together by, for example, photo-etching. In this way, for example, terminals T1a, T2band T12of the semiconductor device1shown inFIG.5are formed.

Effects similar to those of the first embodiment are obtained by the third embodiment. In the semiconductor device1of the third embodiment, contact hole CH12bis formed inside the edge of contact hole CH12a. A single terminal T12located in contact holes CH12aand CH12belectrically connects semiconductor layers SC1and SC2. Thus, the third embodiment can form contact holes CH12aand CH12bin a small area to electrically connect thin-film transistors TR1and TR2in comparison with a case where contact hoes CH12aand CH12bare formed at different positions. In this way, it is possible to provide a structure advantageous to high fineness.

As explained above, the present embodiment can provide a semiconductor device which prevents decrease in reliability and is effectively manufactured.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.