Patent ID: 12230541

DETAILED DESCRIPTION

Embodiments of the element chip manufacturing method according to the present disclosure will be described below by way of examples. However, the present disclosure is not limited to the examples described below. Although examples of specific numerical values and materials may be given in the following description, other numerical values and materials may be used as long as the effects of the present disclosure can be achieved.

Element Chip Manufacturing Method

The element chip manufacturing method according to the present disclosure includes a preparing process, a groove forming process, and a grinding process. These processes will be described below.

Preparing Process

In the preparing process, a substrate is prepared. The substrate includes a plurality of element regions, and a dividing region that defines the element regions. The substrate has a first principal surface, and a second principal surface located opposite to the first principal surface. The substrate may also include a semiconductor layer, and a device layer stacked on the first principal surface side of the semiconductor layer.

Groove Forming Process

In the groove forming process, a groove is formed in the dividing region from the first principal surface side of the substrate. The groove includes a first region and a second region. The first region is constituted by a side surface having a first surface roughness. The second region is constituted by a side surface having a second surface roughness larger than the first surface roughness. The second surface roughness may be greater than or equal to 10 times the first surface roughness. The groove may be formed halfway in the thickness direction of the semiconductor layer.

Note that the surface roughness as used herein is an arithmetic mean roughness Ra defined in JIS B 0601. That is, the surface roughness as used herein is obtained as follows: A portion of a roughness curve obtained by measuring a groove surface using a roughness meter is cut out at a reference length, and the state of unevenness of the cut-out section is represented by an average value.

Grinding Process

In the grinding process, the substrate is ground from the second principal surface side, to divide the substrate into a plurality of element chips. Thus, the element chip manufacturing method according to the present disclosure is a manufacturing method using a DBG process.

In the grinding process, grinding of the substrate is performed until reaching the first region of the groove. That is, in the grinding process, grinding of the substrate is performed until reaching the first region having a relatively small surface roughness, out of the first region and the second region. A tool used for grinding, such as a grinding wheel, is less likely to be caught on the side surfaces of the first region. Accordingly, with the element chip manufacturing method according to the present disclosure, chipping is less likely to occur.

As described above, according to the present disclosure, it is possible to inhibit chipping in a DBG process.

The groove forming process may include a first plasma processing process of trenching the substrate by continuously etching the substrate, to form the first region; and a second plasma processing process of trenching the substrate by repeating an etching step of etching the substrate, a depositing step of depositing a protection film, and a protection film removing step of removing at least a portion of the protection film, to form the second region. In other words, a first region having no scallop may be formed by a non-Bosch process, and a second region having scallops may be formed by a Bosch process.

The groove forming process may be started from the first plasma processing process. In this case, on side surfaces of each of the finished element chips, end portions on both the first principal surface side and the second principal surface side become relatively smooth. Accordingly, it is possible to increase the transverse rupture strength of the element chips. Note that the groove forming process may be started from the second plasma processing process.

In the groove forming process, the first plasma processing process and the subsequent second plasma processing process may be performed at the end. In the grinding process, grinding of the substrate may be performed until reaching the first region of the groove, the first region having been formed in the first plasma processing process performed last. In this case, the second region formed in the second plasma processing process performed last functions as a preparatory region in the grinding process. That is, even if grinding cannot be performed for a portion of the groove until reaching the first region formed in the first plasma processing process performed last, grinding can be performed until reaching the second region. Accordingly, the substrate can be easily divided into a plurality of element chips.

Note that in the present specification, even if grinding cannot be performed for the entirety of a groove until reaching the first region, it is regarded that grinding is performed until reaching the first region of the groove as long as grinding is performed for most of the groove until reaching the first region (e.g., 85% or more of the entire area of the groove).

In the groove forming process, the first plasma processing process may be performed last. In the grinding process, grinding of the substrate may be performed until reaching the first region of the groove, the first region having been formed in the first plasma processing process performed last. In this case, the second region is formed by the second plasma processing process performed before the first plasma processing process performed last. Since the second region is formed by the second plasma processing process, which is less likely to cause side etching, increasing the length of the second region in the depth direction of the groove has little harmful effect. By adjusting the length of the second region, a groove having a high aspect ratio (e.g., a groove having an aspect ratio of 20 or more) can be easily formed.

As used herein, an aspect ratio refers to a value (D/W) obtained by dividing a depth D of the groove formed in the groove forming process by an opening width W of the groove.

In the groove forming process, the number of times the first plasma processing process and the second plasma processing process are performed may be set freely. In other words, in the groove forming process, the first plasma processing process may be performed once, or twice or more, and the second plasma processing process may be performed once, or twice or more.

In the following, examples of the element chip manufacturing method according to the present disclosure will be described in detail with reference to the drawings. The above-described processes can be applied to the processes of the examples of the element chip manufacturing method described below. The processes of the examples of the element chip manufacturing method described below can be changed based on the above description. The matters described below may be applied to the above-described embodiment. Of the processes of the examples of the element chip manufacturing method described below, processes that are not essential to the element chip manufacturing method according to the present disclosure may be omitted. Note that the drawings described below are schematic views, and do not accurately reflect the actual shapes and the actual numbers of components.

Embodiment 1

As shown inFIG.1, the element chip manufacturing method includes a preparing process, a groove forming process, a mask removing process, an attaching process, and a grinding process.

Preparing Process

In the preparing process, a substrate1is prepared (shown in the left-most view inFIG.1). The substrate1has a first principal surface1X, and a second principal surface1Y located opposite to the first principal surface1X. The substrate1includes a plurality of element regions EA, and dividing regions DA that define the element regions EA.

The substrate1includes a semiconductor layer11, and a device layer12stacked on the first principal surface1X side of the semiconductor layer11. Examples of the semiconductor forming the semiconductor layer11include silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC). The device layer12is formed in each of the element regions EA.

In each of the element regions EA, a mask M is formed on the device layer12. Resist, an SiO2film, a silicon nitride film, a metal thin film, or the like can be used as the mask M. The mask M is formed by a known method according to the type of the constituent material thereof.

Groove Forming Process

In the groove forming process, a groove13is formed in each of the dividing regions DA from the first principal surface1X side of the substrate1(shown in the second view from the left inFIG.1). Each of these grooves13includes a first region13aconstituted by a side surface having a first surface roughness, and a second region13bconstituted by a side surface having a second surface roughness. Here, the second surface roughness is larger than the first surface roughness.

The groove forming process includes a first plasma processing process of forming the first regions13a, and a second plasma processing process of forming the second regions13b. The groove forming process of the present embodiment is started from the first plasma processing process, and each of the first plasma processing process and the second plasma processing process is performed once. Consequently, grooves13each including one first region13aand one second region13bin this order from the first principal surface1X side are formed on the substrate1.

According to the present embodiment, grooves13each having a relatively low aspect ratio are formed. For example, the opening width W of each groove13may be 5 to 6 μm, and the depth D of each groove13may be 45 to 50 μm. For example, in the depth direction of the grooves13, the length of each first region13amay be 30 to 35 μm, and the length of each second region13bmay be 10 to 20 μm.

Plasma Processing Apparatus

Here, a plasma processing apparatus100used for the plasma processing processes will be specifically described with reference toFIG.2. However, the plasma processing apparatus is not limited thereto.

The plasma processing apparatus100includes a stage111. The substrate1is placed on the stage111, together with a transport carrier10that supports the substrate1, such that the first principal surface1X faces upward. Here, the transport carrier10is made up of a holding sheet3that holds the substrate1from the second principal surface1Y side, and a frame2to which the holding sheet3is fixed. The stage111has a size sufficient to allow the entire transport carrier10to be placed thereon.

A cover124that covers the frame2and at least a portion of the holding sheet3, and that includes a window portion124W exposing at least a portion of the substrate1is disposed above the stage111. A retaining member107for pressing the frame2when the frame2is placed on the stage111is disposed on the cover124.

The stage111and the cover124are disposed inside a vacuum chamber103. The vacuum chamber103has a substantially cylindrical shape with an opening at the top. The opening at the top is closed by a dielectric member108serving as a lid member. Examples of the material forming the vacuum chamber103include aluminum, stainless steel (SUS), and aluminum having an anodized surface. Examples of the material forming the dielectric member108include dielectric materials such as yttrium oxide (Y2O3), aluminum nitride (AlN), alumina (Al2O3), and quartz (SiO2). A first electrode109serving as an upper electrode is disposed above the dielectric member108. The first electrode109is electrically connected to a first high-frequency power supply110A. The stage111is disposed on the bottom side in the vacuum chamber103.

The vacuum chamber103includes a gas introduction port103a. A process gas source112serving as a supply source of a plasma generating gas and an ashing gas source113are connected to the gas introduction port103avia their respective pipes. In addition, the vacuum chamber103includes an exhaust port103b. A pressure reducing mechanism114including a vacuum pump for evacuating the gas inside the vacuum chamber103is connected to the exhaust port103b. Plasma is generated inside the vacuum chamber103as a result of high-frequency power being supplied from the first high-frequency power supply110A to the first electrode109in a state in which a process gas is supplied in the vacuum chamber103.

The stage111includes an electrode layer115and a metal layer116each having a substantially circular shape, a base117that supports the electrode layer115and the metal layer116, and an outer peripheral portion118that surrounds the electrode layer115, the metal layer116, and the base117. The outer peripheral portion118is formed of a metal having conductivity and etching resistance, and protects the electrode layer115, the metal layer116, and the base117from plasma. An annular outer peripheral ring129is disposed on an upper surface of the outer peripheral portion118. The outer peripheral ring129serves to protect the upper surface of the outer peripheral portion118from plasma. The electrode layer115and the outer peripheral ring129are formed of any of the above-described dielectric materials, for example.

An electrostatic chucking electrode (hereinafter referred to as an “ESC electrode119”), and a second electrode120electrically connected to the second high-frequency power supply110B are disposed inside the electrode layer115. A direct-current (DC) power supply126is electrically connected to the ESC electrode119. The ESC electrode119and the DC power supply126constitute an electrostatic chucking mechanism. The holding sheet3is pressed against and fixed to the stage111by the electrostatic chucking mechanism. Although the following describes a case where the electrostatic chucking mechanism is provided as a fixing mechanism for fixing the holding sheet3to the stage111, the present disclosure is not limited thereto. The holding sheet3may be fixed to the stage111by means of a clamp, which is not shown.

The metal layer116is formed of, for example, aluminum having an alumite coating formed on the surface thereof. A refrigerant flow path127is formed inside the metal layer116. The stage111is cooled by a refrigerant flowing through the refrigerant flow path127. As a result of cooling the stage111, the holding sheet3mounted on the stage111is cooled, and the cover124, a portion of which is in contact with the stage111, is also cooled. This can prevent the substrate1and the holding sheet3from being damaged due to overheating during plasma processing. The refrigerant in the refrigerant flow path127is circulated by the refrigerant circulation device125.

A plurality of support portions122extending through the stage111are disposed in the vicinity of the outer periphery of the stage111. The support portions122support the frame2of the transport carrier10. The support portions122are driven to be lifted and lowered by an elevation mechanism123A. When the transport carrier10is transported into the vacuum chamber103, the transport carrier10is transferred to the support portions122that are lifted to a predetermined position. By lowering the upper end surfaces of the support portions122to the same level as, or a level lower than, that of the stage111, the transport carrier10is placed at a predetermined position on the stage111.

A plurality of elevation rods121that allow the cover124to be lifted and lowered are coupled to an end portion of the cover124. The elevation rods121are driven to be lifted and lowered by an elevation mechanism123B. The operation performed by the elevation mechanism123B to lift and lower the cover124can be performed independently of the operation of the elevation mechanism123A.

A control device128controls operations of the constituent elements of the plasma processing apparatus100, including the first high-frequency power supply110A, the second high-frequency power supply110B, the process gas source112, the ashing gas source113, the pressure reducing mechanism114, the refrigerant circulation device125, the elevation mechanism123A, the elevation mechanism123B, and the electrostatic chucking mechanism. The control device128includes a computation device, and a storage device in which a program that can be executed by the computation device is stored.

First Plasma Processing Process

In the first plasma processing process, the substrate1is trenched by continuously etching the substrate1, to form the first regions13a.

The first plasma processing process is performed, for example, under processing conditions that the pressure inside the vacuum chamber103is adjusted to 35 Pa, power of 3600 W is applied to the first electrode109from the first high-frequency power supply110A, and power of 200 W is applied to the second electrode120from the second high-frequency power supply110B, while supplying SF6at 90 sccm, O2at 60 sccm, and He at 850 sccm as a raw material gas. Each of the first regions13athat are formed by etching at this time constitutes a substantially smooth side wall having no scallop.

Second Plasma Processing Process

In the second plasma processing process, the substrate1is trenched by repeatedly performing an etching step of etching the substrate1, a depositing step of depositing a protection film, and a protection film removing step of removing at least a portion of the protection film (e.g., a portion of the protection film that is deposited at the bottom portion of each of the grooves13), to form the second regions13b.

The etching step is performed under conditions under which the substrate1can be relatively isotropically etched. The etching step is performed, for example, under processing conditions that the pressure inside the vacuum chamber103is adjusted to 5 to 25 Pa, power of 1500 to 5000 W is applied to the first electrode109from the first high-frequency power supply110A, power of 20 to 500 W is applied to the second electrode120from the second high-frequency power supply110B, and the etching time is 8 to 15 seconds, while supplying SF6at 200 to 400 sccm as a raw material gas.

The depositing step is performed, for example, under processing conditions that the pressure inside the vacuum chamber103is adjusted to 15 to 25 Pa, power of 1500 to 5000 W is applied to the first electrode109from the first high-frequency power supply110A, power of 0 to 50 W is applied to the second electrode120from the second high-frequency power supply110B, and the deposition time is 2 to 10 seconds, while supplying C4F8at 150 to 250 sccm as a raw material gas.

In the protection film removing step, the power applied to the second electrode120is higher than the power applied to the second electrode120in the etching step. This enables anisotropic etching. The protection film removing step is performed, for example, under processing conditions that the pressure inside the vacuum chamber103is adjusted to 5 to 25 Pa, power of 1500 to 5000 W is applied to the first electrode109from the first high-frequency power supply110A, power of 80 to 800 W is applied to the second electrode120from the second high-frequency power supply110B, and the processing time is 2 to 5 seconds, while supplying SF6at 200 to 400 sccm as a raw material gas.

Thus, in the second plasma processing process, deep trenching in the depth direction is performed by repeating the etching step, the depositing step, the protection film removing step. Since the substrate1is likely to be relatively isotropically etched under the etching conditions used in the etching step, the etching of the substrate1also proceeds in the horizontal direction (a direction orthogonal to the depth direction) when the substrate1is trenched in the depth direction by the etching step. Accordingly, by repeating the etching step, the depositing step, and the protection film removing step, horizontal stripe-like projections and recesses (scallops) are inevitably formed on side walls of each groove13. Thus, each of the second regions13bformed by the second plasma processing process constitute a side wall having scallops.

Mask Removing Process

In the mask removing process, the mask M is removed by a known method (shown in the third view from the left inFIG.1). For example, when the mask M is a resist mask, the mask M may be removed by ashing.

Attaching Process

In the attaching process, a holding tape T is attached to the first principal surface1X of the substrate1(shown in the fourth view from the left inFIG.1). The area of the holding tape T is the same as, or larger than, the area of the substrate1. A known holding tape may be used as the holding tape T.

Grinding Process

In the grinding process, the substrate1is ground from the second principal surface1Y side, to divide the substrate1into a plurality of element chips20(shown in the fifth view from the left inFIG.1). In the grinding process, grinding of the substrate1is performed until reaching the first region13aof each of the grooves13. For the grinding process, it is possible to use a known grinding device including a grinding wheel, for example.

Embodiment 2

Embodiment 2 will now be described. The present embodiment is different from Embodiment 1 above with regard to the configuration of the groove forming process and so forth. The following description focuses mainly on differences from Embodiment 1 above.

As shown inFIG.3, a groove forming process (shown in the second view from the left inFIG.3) according to the present embodiment is started from the first plasma processing process, and also, the first plasma processing process, the second plasma processing process, and the first plasma processing process are performed a total of three times in this order. Consequently, grooves13each including a total of three regions, namely, a first region13a, a second region13b, and a first region13ain this order from the first principal surface1X side are formed on the substrate1.

According to the present embodiment, grooves13each having a relatively high aspect ratio are formed. For example, the opening width W of each groove13may be 5 to 6 μm, and the depth D of each groove13may be 150 μm or more. For example, in the depth direction of each groove13, the length of each of the first regions13amay be 10 to 15 μm, and the length of the second region13bmay be 120 to 130 μm. In the grinding process (shown in the fifth view from the left inFIG.3) of the present embodiment, grinding of the substrate1is performed until reaching the first region13aformed in the first plasma processing process performed for the second time, or in other words, the first plasma processing process performed last.

The present disclosure is applicable to an element chip manufacturing method.

REFERENCE NUMERALS

1: Substrate1X: First principal surface1Y: Second principal surface11: Semiconductor layer12: Device layer13: Groove13a: First region13b: Second region10: Transport carrier2: Frame3: Holding sheet20: Element chip100: Plasma processing apparatus103: Vacuum chamber103a: Gas introduction port103b: Exhaust port107: Retaining member108: Dielectric member109: First electrode110A: First high-frequency power supply110B: Second high-frequency power supply111: Stage112: Process gas source113: Ashing gas source114: Pressure reducing mechanism115: Electrode layer116: Metal layer117: Base118: Outer peripheral portion119: ESC electrode120: Second electrode121: Elevation rod122: Support portion123A,123B: Elevation mechanism124: Cover124W: Window portion125: Refrigerant circulation device126: DC power supply127: Refrigerant flow path128: Control device129: Outer peripheral ringDA: Dividing regionEA: Element regionM: MaskT: Holding tape