Patent ID: 12261928

DETAILED DESCRIPTION

While specific embodiments are given in the drawings and the following description, keep in mind that they do not limit the disclosure. On the contrary, they provide the foundation for one of ordinary skill to discern the alternative forms, equivalents, and modifications that are encompassed in the claim scope.

High bandwidth receivers, or “deserializers” are used in many contexts ranging from intrachip communications to long distance wireless, wired, and fiberoptic communications. To provide one specific example,FIG.1shows an illustrative active Ethernet cable (“AEC”) that may be used to provide a high-bandwidth communications link between devices in a routing network such as those used in data centers, server farms, and interconnection exchanges. The routing network may be part of, or may include, for example, the Internet, a wide area network, a local area network, or a storage area network. The linked devices may be computers, switches, routers, and the like. The illustrative cable includes a first connector100and a second connector101that are connected via electrical conductors106in a cord. The electrical conductors106may be arranged in a paired form such as with twinaxial conductors. (Twinaxial conductors can be likened to coaxial conductors, but with two inner conductors instead of one.) The inner conductors may be driven with a differential signal and their shared shield may operate to reduce crosstalk with other twinaxial conductors in the cable. Depending on the performance criteria, it may be possible to employ other paired conductor or single-ended conductor implementations.

Pursuant to the Ethernet standard, each conductor pair may provide unidirectional transport of a differential signal. To enable robust performance over even extended cable lengths, each connector100,101may include a powered transceiver that performs clock data recovery (“CDR”) combined with demodulation and re-modulation of the data streams moving in each direction. Such powered transceivers are also known as data recovery and re-modulation (“DRR”) devices. The connectors100,101may be pluggable modules compliant with any one of the pluggable module standards, e.g., SFP, SFP-DD, QSFP, QSFP-DD, OSFP. In at least one contemplated embodiment, the cable connectors100,101are quad small form-factor pluggable (“QSFP”) transceiver modules that can exchange an 800GAUI-8 data stream with the host using PAM4 signaling at a nominal baud rate of 56 Gbd in each of the eight lanes.

FIG.2is a block diagram of an illustrative AEC. Connector100includes a plug200adapted to fit a standard-compliant Ethernet port in a first host device to receive an electrical input signal carrying a data stream from the host device and to provide an electrical output signal carrying a data stream to the host device. Similarly, connector101includes a plug201that fits an Ethernet port of a second host device. Connector100includes a first DRR device202to perform CDR, demodulation, and re-modulation of the data streams entering and exiting the cable at connector100, and connector101includes a second DRR device204to perform CDR, demodulation, and re-modulation of the data streams entering and exiting the cable at connector101. The DRR devices202,204may be integrated circuits mounted on a printed circuit board and connected to edge connector contacts via circuit board traces. The electrical conductors106and shields may be soldered to corresponding pads on the printed circuit board that electrically connect to the DRR devices.

In at least some contemplated embodiments, the printed circuit boards each also support a micro-controller unit (“MCU”)206. Each DRR device202,204is coupled to a respective MCU device206which configures the operation of the DRR device via a first two-wire bus. At power-on, the MCU device206loads equalization parameters and/or other operating parameters from Flash memory207into the DRR device's configuration registers208. The host device can access the MCU device206via a second two-wire bus that operates in accordance with the I2C bus protocol and/or the faster MDIO protocol. With this access to the MCU device206, the host device can adjust the cable's operating parameters and monitor the cable's performance.

Each DRR device202,204, includes a set220of transmitters and receivers for communicating with the host device and a set222of transmitters and receivers for sending and receiving via conductor pairs running the length of the cable. The cable-facing transceivers222preferably send and receive using differential PAM4 at 56 Gbd in each direction over each lane. The illustrated host-facing transceivers220support eight lanes LN0-LN7for bidirectional communication with the host device, each bidirectional lane formed by two unidirectional connections with differential PAM4 signaling at 56 Gbd, such as may be achieved with 800GBASE-KR8. The DRR devices include a memory224to provide first-in first-out (FIFO) buffering between the transmitter & receiver sets220,222. An embedded controller228coordinates the operation of the transmitters and receivers by, e.g., setting initial equalization parameters and ensuring the training phase is complete across all lanes and links before enabling the transmitters and receiver to enter the data transfer phase. The embedded controller228employs a set of registers208to receive commands and parameter values, and to provide responses potentially including status information and performance data.

FIG.3is a first illustrative digital receiver that may be used as part of the transceiver sets220,222. It includes an analog-to-digital converter (“ADC”)304that samples an analog receive signal302at sample times corresponding to transitions in a sampling clock signal305, thereby providing samples of a digital receive signal to a filter (“feed forward equalizer” or FFE)306, which converts the digital receive signal samples into equalized signal samples having reduced intersymbol interference. A slicer307compares the equalized signal samples to suitable decision thresholds to determine which symbol was transmitted in each symbol interval. The resulting stream of demodulated symbols308may be processed in accordance with the relevant communications protocol to recover the relevant information from the data stream, e.g., using frame alignment, de-interleaving, error-correction, and descrambling operations.

The illustrative receiver includes a clock recovery circuit to generate a suitable sampling clock signal305. InFIG.3, the clock recovery circuit includes a phase and frequency acquisition module309and a feedback loop that begins with timing error estimator310. The timing error estimator310can use any suitable timing error estimation technique, e.g., the formulas in Mueller-Müller, “Timing Recovery in Digital Synchronous Data Receivers”, IEEE Trans. Commun., v24 n5, May 1976. A timing loop filter312filters the estimated timing error signal to obtain a timing control signal for a phase interpolator320. In the embodiment ofFIG.3, the timing loop filter312is a second order proportional-integration (PI) filter having a summer314, which receives along a first path a proportional (i.e., scaled by a constant coefficient kP) component of the timing error signal, and receives along a second path an integrated (i.e., scaled by a constant coefficient kIand integrated by integrator316) component of the timing error signal. The received components are added and provided to a second integrator318, which integrates the sum to provide the timing control signal to the phase interpolator320.

The phase interpolator320also receives a clock signal from a phase lock loop (PLL)322. The timing control signal causes the phase interpolator320to produce the sampling signal by adjusting the phase of the clock signal in a fashion that minimizes an expected value of the timing error. In other words, the timing control signal compensates for both the frequency offset and phase error of the PLL output signal relative to the analog data signal302, thereby phase-aligning the sampling clock305with the data symbols in the analog receive signal.

The clock signal produced by PLL322is a frequency-multiplied version of a reference clock signal from a reference oscillator324or other clock source. A voltage-controlled oscillator (“VCO”)326supplies the clock signal to both the phase interpolator320and to a counter328that divides the frequency of the clock signal by a constant or variable modulus N that provides a specified division ratio. The counter supplies the divided-frequency clock signal to a phase-frequency detector (“PFD”)330. PFD330may use a charge pump (“CP”) as part of determining which input (i.e., the divided-frequency clock signal or the reference clock signal) has transitions earlier or more often than the other. A low pass filter332filters the output of PFD330to provide a control voltage to VCO326. The filter coefficients are chosen so that the divided frequency clock becomes phase aligned with the reference oscillator.

Note that for at least some contemplated uses, the reference clock used by the receiver will often drift relative to the reference clock used by the transmitter and may differ by hundreds of ppm. In the embodiment ofFIG.3, the resulting frequency offset between the PLL's clock signal output and the analog data signal can be corrected by adjusting the modulus N of the counter328and/or by suitably setting the integrator316to provide continuous phase rotation in the phase interpolator320. Other feedback loop implementations are available in the open literature and would also be suitable for use in the disclosed embodiments.

The inherent loop delay of the feedback loop is stabilized with suitable design of the timing loop filter to limit the response bandwidth, but this limit can cause an undesirable delay in achieving minimal timing error. The phase and frequency acquisition module309addresses this issue by estimating an initial frequency offset and phase offset of the sampling clock signal305during a preamble phase in which the transmitter sends symbol doublets that alternate in sign, e.g., +1, +1, −1, −1, +1, +1, −1, −1, . . . . Preferably the transmitter uses the maximum amplitude symbols for the preamble, so that for PAM4, the preamble would be a sequence of +3, +3, −3, −3, repetitions. As explained further below, the phase and frequency acquisition module309enables the initial frequency offset and initial phase offset to be determined and corrected in less than about 200 symbols, shortening the normal convergence time of the feedback loop by a couple orders of magnitude. The phase and frequency acquisition module309can perform this determination based on the receive signal samples or optionally on the equalized signal samples. The equalized signal samples can be the output of the FFE filter306as shown inFIG.3, or they can be the input of the slicer307as shown in the decision feedback equalizers ofFIGS.4-5.

FIG.4shows one illustrative implementation of a decision feedback equalizer-based receiver. Prior to sampling, the analog channel signal302is filtered by a continuous time linear equalizer (“CTLE”)440to attenuate out-of-band noise and to optionally provide some spectral shaping to improve a response to high-frequency components of the receive signal. (The receiver ofFIG.3may also include a similar analog filter.) ADC304is provided to digitize the receive signal, and an FFE filter306performs further equalization to further shape the overall channel response of the system and minimize the effects of leading ISI on the current symbol. As part of the shaping of the overall channel response, the FFE filter306may also be designed to shorten the channel response of the filtered signal while minimizing any attendant noise enhancement.

An adder442subtracts an optional feedback signal from the output of FFE306to minimize the effects of trailing ISI on the current symbol, yielding an equalized signal that is coupled to a decision element (“slicer”)307. The decision element307includes one or more comparators that compare the equalized signal to corresponding decision thresholds to determine for each symbol interval which constellation symbol the signal's value most closely corresponds to. The input of slicer307may also be termed a “combined signal” herein.

The decision element307accordingly produces a sequence of symbol decisions308. In certain contemplated embodiments, the signal constellation is a bipolar (non-return-to-zero) constellation representing −1 and +1, necessitating only one comparator using a decision threshold of zero. In certain other contemplated embodiments, the signal constellation is PAM4 (−3, −1, +1, +3), necessitating three comparators employing the respective decision thresholds −2, 0, and +2. (The unit for expressing symbol and threshold values is omitted for generality, but for explanatory purposes may be presumed to be volts. In practice, a scale factor will be employed.) The comparator outputs can be taken collectively as a thermometer-coded digital representation of the output symbol decision, e.g., with 000 representing −3, 100 representing −1, 110 representing +1, and 111 representing +3. Alternatively, the comparator outputs could be converted into a binary or Gray-coded representation.

A feedback filter (“FBF”)444derives the feedback signal using a series of delay elements (e.g., latches, flip flops, or registers) that store the recent output symbol decisions. Each stored symbol is multiplied with a corresponding filter coefficient fi, and the products are combined to obtain the feedback signal.

The DFE-based receiver also includes a clock recovery circuit having a phase and frequency acquisition module309and a feedback loop that begins with timing error estimator310. As an aside, we note here that the receivers each also includes a filter coefficient adaptation unit, but such considerations are addressed in the literature and are well known to those skilled in the art. Nevertheless, we note here that at least some contemplated embodiments include one or more additional comparators in the decision element307to be employed for comparing the equalized or combined signal to one or more of the symbol values, thereby providing an error signal that can be used for timing recovery and/or coefficient adaptation.

As the symbol rates increase into the gigahertz range, it becomes increasingly difficult for the various receiver components to perform their required operations completely within each symbol interval, at which point it becomes advantageous to parallelize their operations. Parallelization generally involves the use of multiple components that share the workload by taking turns, and thereby providing more time for each of the individual components to complete their operations. Such parallel components are driven by staggered versions of a clock signal such as those shown inFIG.6. A four-fold parallelization employs a set of four clock signals, each having a frequency that is one-fourth of the symbol rate so that each symbol interval contains only one upward transition in the set of staggered clock signals. Though a four-fold parallelization is used for discussion purposes here, the actual degree of parallelization can be higher, e.g., 8-, 16-, 32-, or 64-fold. Moreover, the degree of parallelization is not limited to powers-of-two.

FIG.5shows an illustrative receiver having a parallelized equalizer implementation (including the optional feedback filters for DFE). As with the implementation ofFIG.4, the CTLE440filters the channel signal to provide a receive signal, which is supplied in parallel to a set of analog-to-digital converters (ADC0-ADC3). Each of the ADC elements is provided with a respective one of the staggered clock signals fromFIG.6to provide a parallel set of sampled receive signals. The clock signals have different phases, causing the ADC elements to take turns sampling and digitizing the receive signal, so that only one of the ADC element outputs is transitioning at any given time.

An array of FFEs (FFE0-FFE3), each forms a weighted sum of the ADC element outputs. The weighted sums employ filter coefficients that are cyclically shifted relative to each other. FFE0operates on the held signals from ADC3(the element operating prior to CLK0), ADC0(the element responding to CLK0), and ADC1(the element operating subsequent to CLK0), such that during the assertion of CLK2, the weighted sum produced by FFE0corresponds to the output of FFE306(FIG.4). FFE1operates on the held signals from ADC0(the element operating prior to CLK1), ADC1(the element responding to CLK1), and ADC2(the element operating subsequent to CLK1), such that during the assertion of CLK3, the weighted sum corresponds to that of FFE306. And the operation of the remaining FFEs in the array follow the same pattern with the relevant phase shifts. In practice, the number of filter taps may be smaller, or the number of elements in the array may be larger, so as to offer a longer window of valid output.

As with the receiver ofFIG.4, an adder may combine the output of each FFE with a feedback signal to provide an equalized signal to a corresponding decision element.FIG.5shows an array of decision elements (Slicer0-Slicer3), each operating on an equalized signal derived from a respective FFE output. As with the decision element ofFIG.4, the illustrated decision elements employ comparators to determine which symbol the equalized signal most likely represents. The decisions are made while the respective FFE outputs are valid (e.g., Slicer0operates while CLK2is asserted, Slicer1operates while CLK3is asserted, etc.). Preferably the decisions are provided in parallel on an output bus to enable a lower clock rate to be used for subsequent operations.

An array of feedback filters (FBF0-FBF3) operates on the preceding symbol decisions to provide the feedback signals for the summers. As with the FFEs, the inputs for the FBFs are shifted cyclically and provide a valid output only when the inputs correspond to the contents of the FBF444(FIG.4), coinciding with the time window for the corresponding FFE. In practice, the number of feedback filter taps may be smaller than what is shown, or the number of array elements may be larger, so as to offer a longer window of valid output.

As with the decision element ofFIG.4, the decision elements inFIG.5may each employ additional comparators to provide timing recovery info, coefficient training info, and/or precomputation to unroll one or more taps of the feedback filter. In the embodiment ofFIG.5, the digital timing circuit is also parallelized, with a phase and frequency acquisition module509operating on receive signal samples during a training preamble to determine and correct initial phase and frequency offsets similar to module309, a timing error estimator510accepting symbol decisions and equalized signals in parallel to determine the timing error estimates that would be produced by estimator310. A timing loop filter512generates the timing control signal that would be produced by filter312, and the phase interpolator520operates similarly to phase interpolator320to convert the PLL clock signal into a set of staggered clock signals having evenly spaced phases with symbol-aligned transitions. A set of delay lines (DL0-DL3) is provided for fine-tuning the individual clock phases relative to each other as needed to, e.g., compensate for different propagation delays of individual ADC elements.

InFIG.5, the phase and frequency acquisition module509is shown inhibiting operation of the timing error estimator510(and accordingly the feedback loop) during initial acquisition, but this inhibition is optional in view of the limited loop bandwidth. Once the module509has determined the initial phase and frequency offsets, it can adjust the PLL322and phase interpolator520to compensate for the initial offsets before enabling the timing error estimator (and accordingly the feedback loop). Alternatively, or in addition, the phase and frequency acquisition module509may adjust contents of the integrators in the loop filter512to compensate for the initial offsets.

FIG.7shows an illustrative method that may be implemented by the phase and frequency acquisition modules mentioned above, but certain derivations may be helpful to understanding the method and are accordingly described first. The acquisition may be performed while the transmitter sends a preamble pattern consisting of alternating doublets, also known as a 2T pattern, e.g., repetitions of the sequence [−3, −3, +3, +3]. On the receive side, the receive signal samples (provided by the analog to digital converter) or optionally, the equalized signal samples output by the FFE filter or DFE adder, will resemble a sinusoid:
xk=A·cos(2π·fb·kT/4+Π0)  (1)
where A is the 2T tone amplitude, fbthe baud rate at the transmit side, 1/T the ADC sampling frequency, k the ADC sample index, and Ø0the initial sampling phase. This equation can be rewritten as:

xk=A·cos⁡(π2·fb·k⁡(Tb+Δ⁢T)+∅0)(2)
where Tb=1/fb, and the ADC sampling period T=Tb+ΔT. Then (2) can be rewritten as:

xk=A·cos⁡(π2·k⁡(1+Δ)+∅0)(3)
where Δ=ΔT/Tb.

From (3) we have:

xk+1=A·cos⁡(π2·(k+1)⁢(1+Δ)+∅0)=A·cos⁡(π2·k⁡(1+Δ)+π2+π2·Δ+∅0)=-A·sin⁡(π2·k⁡(1+Δ)+π2·Δ+∅0)(4)
Equations (3) and (4) can be combined:

xk+1xk≈-tan⁡(π2·k⁡(1+Δ)+∅0)(5)
Based on this equation, we can estimate the present ADC sampling phase as:

pk=atan⁡(-xk+1xk)(6)

The sampling frequency acquisition is done as follows. Let pk, pk+1, . . . be the, unwrapped phase sequence from (6). Extending (4) and (5), we have the following:

pk+D-pk=π2·(k+D)⁢(1+Δ)+∅0-[π2·k⁡(1+Δ)+∅0]=π2·D·(1+Δ)(7)
where D is an integer number of sample intervals. From (7) we have:

1+Δ=1+Δ⁢TTb=TTb=fbfs=(pk+D-pk)·2π·D(8)
where fs=1/T is the ADC sampling frequency. From (8) we can estimate the normalized frequency offset Δf as:

Δ⁢f=fs-fbfb=11+Δ-1=π·D2⁢(pk+D-pk)-1(9)
Averaging may be used to improve the estimate, either by averaging the estimated rate of change in the unwrapped phase sequence or by averaging the estimated normalized frequency offset over a given interval.

After the frequency offset has been corrected, or in situations where the ADC sampling frequency can be assumed to be close to the transmit baud rate, e.g., within a few hundred parts per million, the ADC sampling phase will be relatively constant and can be estimated by averaging the phase estimates pkover a given interval to obtain the average phase Øavg. The target sampling phase at the input to the decision element is

π4.
If we are deriving the phase estimate using receive signal samples, it is desirable to account for any phase shifts that may be created by the FFE filter. Representing the frequency response of the FFE at frequency f as F(f), let the phase shift of the FFE filter at F(fb/4) be denoted Øffe. The target sampling phase for the ADC is then

∅target=π4-∅ffe(10)
and can be predetermined for a given set of filter coefficients. The sampling phase offset ØΔbecomes
ØA=Øtarget−Øavg(11)
The phase and frequency acquisition module can use this sampling phase offset to quickly correct the sampling phase by, e.g., adjusting the setting of the phase interpolator to compensate.

The foregoing derivation presumed the transmitter's use of a 2T preamble pattern. Another popular preamble pattern that may be used by the transmitter is the Nyquist pattern (a sequency of alternating polarity symbols such as −3, +3, −3, +3, . . . ). In this case, the receive signal sinusoid can be represented as

r⁡(t)=A·cos⁡(2⁢π·fb·t/2+∅0)(12)r⁡(kT)=A·cos⁡(2⁢π·fb·k⁢T2+∅0)=A·cos⁡(k⁢π·(1+Δ)+∅0)=(-1)k·A·cos⁡(k⁢π⁢Δ+∅0)(13)r⁡(kT+T2)=A·cos(2⁢π·fb·(k+12)⁢T2+∅0)=A·cos⁡(k⁢π·(1+Δ)+∅0+π2+π2·Δ)=(-1)k·A·(-1)·sin⁡(k⁢π⁢Δ+∅0+π2·Δ)(14)

Assume each ADC sampling cycle generates M samples, and the ADC sampling phase remains the same within one cycle. Let xnm+ibe the ithsample of the nthADC sampling cycle. At the nthADC sampling cycle, we sample the ADC input signal as
xnM+i=r(nMT+iT)=(−1)nM+i˜A·cos((nM+i)πΔ+Ø0)  (15)
and at the (n+1)thADC sampling cycle, we have

x(n+1)⁢M+i=r⁡((n+1)⁢M⁢T+i⁢T+T2)=(-1)n⁢M+i·A·(-1)·sin⁡((n⁢M+M+i)⁢π⁢Δ+∅0+π2·Δ)(16)
From (15) and (16), we have

x(n+1)⁢M+ixnM+i≈-tan⁡((n⁢M+i)⁢π⁢Δ+∅0)(17)
Let

pn,i=atan⁡(-x(n+1)⁢M+ixnM+i),(18)
so that
pn,i≈(nM+i)πΔ+Ø0(19)
pn,i+D−pn,i=DπΔ(20)
Then, the normalized frequency offset Δf is given as

Δ⁢f≈pn,i+D-pn,iπ⁢D(21)
The estimated normalized frequency offset can be improved by averaging the estimates over a given interval.

After the frequency offset has been corrected, or in situations where the ADC sampling frequency can be assumed to be close to the transmit baud rate, e.g., within a few hundred parts per million, the ADC sampling phase will be relatively constant and can be estimated by averaging the phase estimates pn,ifrom equation (18) over a given interval to obtain the average phase Øavg. For sampling phase acquisition, the target sampling phase should be the phase such that the power of sampled tone of Nyquist frequency, fb/2, is maximized, which is equivalent to sampling at the peak of the tone. Taking the target sampling phase as

∅target=π2-∅ffe(22)
the sampling phase offset ØΔbecomes
ØΔ=Øtarget−Øavg(23)
If acquiring phase and frequency offsets is performed using equalized samples rather than receive signal samples, the phase shift of the FFE filter is already taken into account, and in equations 10 and 22, Øffe=0.

Returning now toFIG.7, the phase and frequency acquisition module may be used during link initiation when the remote transmitter is expected to be transmitting a preamble. In block702, the module optionally disables the feedback loop by, e.g., disabling the timing error detector. In block704, the module obtains receive signal sample(s), either one at a time as provided inFIGS.3and4, or in batches as provided inFIG.5. The sampling clock for obtaining the samples has an initial phase and frequency that may be offset from the transmit baud rate and from the target sampling phase.

In block706, the module obtains additional receive signal sample(s), combining them with the previous receive signal sample(s) to obtain a sampling phase estimate. In block708, the module obtains still more receive signal sample(s) to obtain an updated sampling phase estimate. The module derives an estimated frequency offset from the trend in sampling phase estimates. In block710, more receive signal sample(s) are obtained to provide updated sampling phase estimates and new estimates of the frequency offset which may be combined with previous estimates, e.g., by averaging, to improve the reliability of the frequency offset estimate. In block712, the module determines whether the estimate is sufficiently reliable by, e.g., determining whether enough estimates have been averaged together. Blocks710and712may be repeated until sufficient reliability is achieved.

In block714, the module uses the estimated frequency offset to adjust the frequency of the sample clock. This adjustment may take the form of adjusting a control voltage of a voltage-controlled oscillator, adjusting a phase-lock loop frequency divider, and/or adjusting an accumulator value in a clock recovery feedback loop. In each case, the adjustment is readily derived from the estimated frequency offset.

In block716, the module obtains receive signal sample(s) using the sample clock with the adjusted frequency and estimates the sampling phase. In block718, the module determines whether the phase estimate is sufficiently reliable, e.g., whether enough estimates have been averaged together. Blocks716and718may be repeated until sufficient reliability is achieved. In block720, the module uses the estimated phase to calculate a phase offset and adjusts the sample clock phase to compensate for the phase offset. This adjustment may take the form of adjusting a sample clock delay, adjusting a phase interpolator setting, and/or adjusting an accumulator value in a clock recovery feedback loop. In each case, the adjustment is readily derived from the estimated phase offset.

In block722, the module enables the clock recovery feedback loop, e.g., by enabling the timing error calculator. Thereafter, the clock recovery feedback loop operates to minimize timing error in the usual fashion, and the receiver can proceed with training of equalizer coefficients, if needed. Though the operations ofFIG.7have been shown and described in a sequential fashion, the operations may be reordered and/or implemented concurrently. For example, the phase offset estimation may be performed before, or concurrently with, the frequency offset estimation.

Simulations were carried out to verify the performance of the proposed fast sampling phase and frequency acquisition. The PAM4 2T patterns [−3, −3, +3, +3] at 52.125 Gbd were transmitted over a channel with 13 dB loss at the Nyquist frequency. The ADC digitized the receive signal with 7-bit resolution. For sampling phase acquisition, 64 PAM4 symbols were used for the phase offset estimation. The average phase estimation error magnitude is less than 0.014 channel symbol intervals (UI) and mostly below 0.010 UI. For the sampling frequency acquisition, 128 PAM4 symbols were used to estimate the frequency offset. The frequency estimation error had a root-mean-square value of 18.58 ppm for an initial 100 ppm frequency offset, and 19.27 ppm for an initial 200 ppm frequency offset. In these experiments, fewer than 200 channel symbols (less than 2.3 nanoseconds) were required for the phase and frequency acquisition module to provide reasonably good sampling phase and frequency matching.

The phase and frequency acquisition module may be implemented as application specific integrated circuitry. The arctangent calculation for phase estimation may be implemented using an iterative calculation circuit that implements the coordinate rotation digital computer (CORDIC) technique, or by using a non-iterative polynomial approximation technique. Alternatively, the method may be implemented as firmware programming for a microcontroller or programmable digital signal processor.

It is contemplated that the disclosed phase and frequency acquisition module can be incorporated into SerDes cores for use by integrated circuit designers and manufacturers creating devices for a host of applications that might benefit from cost-, complexity-, and power-efficient high-bandwidth communications. Numerous alternative forms, equivalents, and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. For example, the disclosed principles are applicable to both PAM, QAM, and PSK modulation, and to larger signal constellations including 8-PSK, 16-PAM, etc. It is intended that the claims be interpreted to embrace all such alternative forms, equivalents, and modifications that are encompassed in the scope of the appended claims.

The foregoing integrated circuits would typically be created using masks for patterning layers on semiconductor substrates during an integrated circuit manufacturing process. The mask patterns can be generated using commercially available software for converting the semiconductor IP cores (usually expressed using a hardware description language such as Verilog) into semiconductor process masks. The circuits may be sub-units of more complex integrated circuit devices whose designs have been built up from modular components in a design database which resides on nontransient information storage media. Once the circuits are fully designed, software may convert the integrated circuits into semiconductor mask patterns also stored on a nontransient information storage medium and conveyed to the various process units in a suitable assembly line of an integrated circuit manufactory.