Patent ID: 12232331

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

FIG.1illustrates a cross-sectional view of some embodiments of a memory device.

Referring toFIG.1, a memory device100includes a memory cell110and a selector120. In some embodiments, the memory cell110is surrounded by an inter-level dielectric (ILD) structure104arranged over a substrate102. The substrate102may be any type of semiconductor body such as a semiconductor wafer and/or one or more die on a wafer, as well as any other type of semiconductor and/or epitaxial layers, associated therewith. The semiconductor body may include silicon, SiGe, SOI, or the like. The ILD structure104may be a single layered or multiple layered structure, and include silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), silicon carbide (SiC), or the like.

The memory cell110includes a first electrode112, a dielectric data storage layer114, and a second electrode116. The first electrode112is separated from the substrate102by one or more first interconnect layers106. The first interconnect layer106may be a metal via and/or a metal wire. In some embodiments, the first interconnect layer106is electrically coupled to underlying electric components, such as a transistor, a resistor, a capacitor, a selector, and/or a diode. The dielectric data storage layer114is arranged over the first electrode112, and the second electrode116is disposed between the dielectric data storage layer114and a second interconnect layer130. The second interconnect layer130may be a metal via and/or a metal wire.

In some embodiments, the memory cell110is a RRAM cell and is configured to store data by a resistance of the dielectric data storage layer114. In some embodiments, the dielectric data storage layer114having a variable resistance is configured to store data states by undergoing reversible changes between a high resistance state associated with a first data state (e.g., a ‘0’) and a low resistance state associated with a second data state (e.g., a ‘1’). For example, to achieve a low resistance state within the dielectric data storage layer114, a first set of bias conditions may be applied to the first electrode112and the second electrode116. The first set of bias conditions drive oxygen from dielectric data storage layer114to the second electrode116, thereby forming conductive filaments of oxygen vacancies across the dielectric data storage layer114. Alternatively, to achieve a high resistance state within the dielectric data storage layer114, a second set of bias conditions may be applied to the first electrode112and the second electrode116. The second set of bias conditions break the conductive filaments by driving oxygen from the second electrode116to the dielectric data storage layer114.

In some alternative embodiments, the dielectric data storage layer114is replaced with some other suitable data storage structure, such that the memory cell110is another type of memory cell. For example, the memory cell110may be a phase change memory (PCM) cell, a magnetoresistive random-access memory (MRAM) cell, a conductive-bridging random-access memory (CBRAM) cell, or some other suitable memory cell.

In some embodiments, the first electrode112may be or include titanium nitride (TiN), titanium tungsten (TiW), titanium tungsten nitride (TiWN), titanium tantalum nitride (TiTaN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), hafnium nitride (HfN), tungsten titanium (WTi), tungsten titanium nitride (WTiN), hafnium tungsten nitride (HfWN), hafnium tungsten (HfW), titanium hafnium nitride (TiHfN), or the like. In some embodiments, the second electrode116may be or include titanium nitride (TiN), titanium tungsten (TiW), titanium tungsten nitride (TiWN), titanium tantalum nitride (TiTaN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), hafnium nitride (HfN), tungsten titanium (WTi), tungsten titanium nitride (WTiN), hafnium tungsten nitride (HfWN), hafnium tungsten (HfW), titanium hafnium nitride (TiHfN), or the like. In some embodiments, the second electrode116and the first electrode112are the same material. In some alternative embodiments, the second electrode116and the first electrode112have different materials.

The selector120overlies the memory cell110. In some embodiments, the selector120and the memory cell110form a one-selector one-memory cell (1S1MC) stack. The selector120includes the second electrode116, a first work function metal layer122, a selector layer124, a second work function metal layer126and a third electrode128. The selector layer124is disposed over the second electrode116, and the third electrode128is disposed between the selector layer124and the second interconnect layer130. The second interconnect layer130is disposed over and electrically coupled to the third electrode128. The second interconnect layer130is electrically coupled to overlying metal wires.

The selector layer124is configured to switch between a low resistance state and a high resistance state depending on whether a voltage applied across the selector120is greater than a threshold voltage. In some embodiments, the selector120may be a threshold-type selector. For example, the selector120may have a high resistance state if a voltage across the selector120is less than the threshold voltage, and the selector120may have a low resistance state if a voltage across the selector120is greater than the threshold voltage. In some embodiments, an electron affinity (the energy from vacuum level to conduction band) of the selector layer124is in a range of about 3.5 eV to about 4.5 eV. The selector layer124may include a chalcogenide material such as CdS, Ce2S3, CuInS2, CuIn5S8, In2S3, PbS, Sb2S3, ZnS, CdSe, CdTe, Sb2Se3, a combination thereof or the like. In some embodiments, the selector layer124includes an ovonic threshold switch (OTS) material or a voltage conductive bridge (VCB) material. The OTS material may include a binary material such as SiTe, GeTe, CTe, BTe, ZnTe, AlTe, GeSe, GeSb, SeSb, SiAs, GeAs, AsTe and BC, a ternary material such as GeSeAs, GeSeSb, GeSbTe, GeSiAs, GeAsSb, SeSbTe and SiTeSe, or a quadruple material such as GeSeAsTe, GeSeTeSi, GeSeTeAs, GeTeSiAs, GeSeAsSb and GeSeSbSi. The binary material may be doped with N, O or the like, and the ternary material and the quadruple material may be doped with N, O, C or the like. The VCB material may include at least one metal and at least one oxide, the at least one metal may be selected from Ag, Cu, Al, As, Te and the like, and the oxide may be SiO2, TiO2, Al2O3, TaO2, ZrO2, a combination thereof or the like.

In some embodiments, the third electrode128may be or include titanium nitride (TiN), titanium tungsten (TiW), titanium tungsten nitride (TiWN), titanium tantalum nitride (TiTaN), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), hafnium nitride (HfN), tungsten titanium (WTi), tungsten titanium nitride (WTiN), hafnium tungsten nitride (HfWN), hafnium tungsten (HfW), titanium hafnium nitride (TiHfN), or the like. In some embodiments, the third electrode128and the second electrode116are the same material. In some alternative embodiments, the third electrode128and the second electrode116have different materials.

In some embodiments, the first work function metal layer122is disposed between the selector layer124and the second electrode116, and the second work function metal layer126is disposed between the selector layer124and the third electrode128. In some embodiments, the first work function metal layer122is directly disposed on the selector layer124, that is, the first work function metal layer122is in direct contact with the selector layer124. Similarly, the second work function metal layer126is directly disposed under the selector layer124, and the second work function metal layer126is in direct contact with the selector layer124. In some embodiments, a band offset between an electron affinity of the selector layer124and a work function of the first work function metal layer122is in a range of about 0.2 eV to about 0.5 eV. A band offset between an electron affinity of the selector layer124and a work function of the second work function metal layer126is in a range of about 0.2 eV to about 0.5 eV. For example, a work function of the first work function metal layer122and the second work function metal layer126is respectively in a range of about 4.0 eV to about 5.6 eV while an electron affinity energy (Ec) of the selector layer124is in a range of about 3.5 eV to about 4.5 eV. Thus, a material of the first work function metal layer122and the second work function metal layer126is selected based on a material of the selector layer124. In some embodiments, the first work function metal layer122and the second work function metal layer126may include Al, Mn, Zr, Bi, Pb, Ta, Ag, V, Zn, Ti, Nb, Sn, W, Cr, Fe, TiN, Mo, Cu, Ru, Sb, Os, Te, Re, Rh, Be, Co, TiN, TaN, Ta/Si/N, Ti/Si/N, Au, Pd, Ni, Pt or a combination thereof.

In some embodiments, a thickness of the selector layer124is larger than a thickness of the first work function metal layer122and the second work function metal layer126. A thickness of the selector layer124may be in a range of about 10 nm to about 50 nm, and a thickness of the first work function metal layer122and the second work function metal layer126may be in a range of about 1 nm to about 5 nm. In some embodiments, the first work function metal layer122and the second work function metal layer126may be respectively a single layer. However, the disclosure is not limited thereto. In some alternative embodiments, as shown inFIG.6, at least one of the first work function metal layer122and the second work function metal layer126may be a multiple layered structure. That is, the first work function metal layer122and/or the second work function metal layer126may include a plurality of layers. In the multiple layered structure of the work function metal layer, a work function of the layer may increase as the layer becomes closer to the selector layer124, and a thickness of the layer may decrease as the layer becomes closer to the selector layer124. In some embodiments, the first work function metal layer122and the second work function metal layer126are disposed on opposite sides of the selector layer124, in other words, the selector120has a bi-polar element. However, the disclosure is not limited thereto. In some alternative embodiments, as shown inFIGS.2A and2B, in the memory device100a,100b, the work function metal layer (e.g., the first work function metal layer122or the second work function metal layer126) is disposed at only one side of the selector layer124, in other words, the selector120has an uni-polar element. In addition, in above embodiments, the memory cell110is disposed under the selector120. However, the disclosure is not limited thereto. In some alternative embodiments, the memory cell110is disposed above the selector120. For example, the selector120is disposed between the memory cell110and the first interconnect layer106, and the selector120is electrically coupled to the first interconnect layer106. The memory cell110may be disposed between the second interconnect layer130and the selector120, and the memory cell110may be electrically coupled to the second interconnect layer130.

In some embodiments, a width of the first electrode112, the dielectric data storage layer114, the second electrode116, the first work function metal layer122, the first barrier layer123, the selector layer124, the second barrier layer125, the second work function metal layer126and the third electrode layer128is substantially the same. However, the disclosure is not limited thereto. In some alternative embodiments, the width of the first electrode112, the dielectric data storage layer114, the second electrode116, the first work function metal layer122, the first barrier layer123, the selector layer124, the second barrier layer125, the second work function metal layer126and the third electrode layer128may be different.

In some embodiments, a word line (WL) or a word plane extending along a first direction is electrically coupled to one end of the memory device100-100b(for example, through the third electrode128and the second interconnect layer130), and a bit line (BL) extending along a second direction substantially perpendicular to the first direction is electrically coupled to an opposite end of the memory device100-100b(for example, through the first electrode112and the first interconnect layer106). Consequently, by providing suitable bias conditions, the memory cell110can be switched between two states of electrical resistance, a first state with a low resistance and a second state with a high resistance, to store data.

It is known that the threshold-type selector blocks the off-state current by its thickness and a barrier height. However, for aggressive scaled memory array, the total thickness of the selector should be reduced, which will increase the off-state current too much. In some embodiments, the work function metal layer is disposed between the selector layer and the electrode of the selector. The work function metal layer is configured to provide certain work function with respect to the electron affinity of the selector layer. Therefore, when the selector is turned on, carriers go through the work function metal layer by FN (Fowler Nordheim) tunneling, which will not increase the on-state resistance of the selector significantly. Accordingly, performance such as stability and reliability of the memory device may be improved by reducing the subthreshold leakage of the selector and thereby reducing the off-state current of the memory cell.

FIG.3illustrates a cross-sectional view of some embodiments of a memory device. The arrangement and material of the memory device100care similar to the arrangement and material of the memory device100and thus details thereof are omitted herein. A main difference between the memory device100cand the memory device100lies in that the selector120of the memory device100chas at least one barrier layer between the work function metal layer and the selector layer. In some embodiments, the selector120has a first barrier layer123between the first work function metal layer122and the selector layer124and a second barrier layer125between the second work function metal layer126and the selector layer124. In some embodiments, the first barrier layer123and the second barrier layer125are respectively in direct contact with the selector layer124.

In some embodiments, a band offset between an electron affinity of the selector layer124and a conduction band of the first barrier layer123is in a range of about 0.2 eV to about 0.5 eV. A band offset between an electron affinity of the selector layer124and a conduction band of the second barrier layer125is in a range of about 0.2 eV to about 0.5 eV. An energy offset between the conduction band of the first barrier layer123and the Fermi level of the first work function metal layer122is in a range of about 0.2 eV to about 0.5 eV. An energy offset between the conduction band of the second barrier layer125and the Fermi level of the second work function metal layer126is in a range of about 0.2 eV to about 0.5 eV. For example, a conduction band of the first barrier layer123and the second barrier layer125is respectively in a range of about 3.0 eV to about 4.0 eV while an electron affinity of the selector layer124is in a range of about 3.5 eV to about 4.5 eV and a work function of the first work function metal layer122and the second work function metal layer126is in a range of about 3.5 eV to about 4.5 eV. For example, the first barrier layer123and the second barrier layer125includes CaF2O4, Ce2O3, Cu2O, In2O3, LaTi2O7, NiO, SrTiO3, Ta2O5, TiO2, ZnO, ZrO2, CaFe2O4, YFeO3, Bi4Ti3O12, K4Nb6O17, Nb2O5, Bi2MoO4, BiVO4, InVO4, BaTiO3or a combination thereof. The material of the first barrier layer123is different from the material of the first work function metal layer122, and the material of the second barrier layer125is different from the material of the second work function metal layer126. The material of the first barrier layer123may be the same as or different from the material of the second barrier layer125. In some embodiments, a thickness of the selector layer124is larger than a thickness of the first work function metal layer122and the second work function metal layer126respectively. A thickness of the selector layer124may be in a range of about 10 nm to about 50 nm, and a thickness of the first work function metal layer122and the second work function metal layer126may be in a range of about 1 nm to about 5 nm. In some embodiments, the first barrier layer123and the second barrier layer125may be respectively a single layer. However, the disclosure is not limited thereto. In some alternative embodiments, as shown inFIG.6, at least one of the first barrier layer123and the second barrier layer125may be a multiple layered structure. That is, the first barrier layer123and/or the second barrier layer125may include a plurality of layers. In the multiple layered structure of the barrier layer, a work function of the layer may increase as the layer becomes closer to the selector layer124, and a thickness of the layer may decrease as the layer becomes closer to the selector layer124.

In some embodiments, the first work function metal layer122and the first barrier layer123and the second work function metal layer126and the second barrier layer125are disposed on opposite sides of the selector layer124, in other words, the selector120has a bi-polar element. However, the disclosure is not limited thereto. In some alternative embodiments, as shown inFIG.4A, in the memory device100d, the first work function metal layer122and the first barrier layer123are disposed at only one side of the selector layer124, in other words, the selector120has an uni-polar element. Similarly, as shown inFIG.4B, in the memory device100e, the second work function metal layer126and the second barrier layer125are disposed at only one side of the selector layer124. In addition, in above embodiments, the memory cell110is disposed under the selector120. However, the disclosure is not limited thereto. In some alternative embodiments, the memory cell110is disposed above the selector120. For example, the selector120is disposed between the memory cell110and the first interconnect layer106, and the selector120is electrically coupled to the first interconnect layer106. The memory cell110may be disposed between the second interconnect layer130and the selector120, and the memory cell110may be electrically coupled to the second interconnect layer130.

In some embodiments, the barrier layer is disposed between the selector layer and the work function metal layer of the selector. The barrier layer is configured to provide certain conduction band with respect to the electron affinity of the selector layer. Therefore, when the selector is turned on, carriers go through the barrier layer by FN (Fowler Nordheim) tunneling, which will not increase the on-state resistance of the selector significantly. Accordingly, performance such as stability and reliability of the memory device may be improved by reducing the subthreshold leakage of the selector and thereby reducing the off-state current of the memory cell.

FIGS.5A to5Dillustrate cross-sectional views of some embodiments of a method of forming a memory device. Although the cross-sectional views shown inFIGS.5A to5Dare described with reference to a method, it will be appreciated that the structures shown inFIGS.5A to5Dare not limited to the method but rather may stand alone separate of the method. AlthoughFIGS.5A to5Dare described as a series of acts, it will be appreciated that these acts are not limiting in that the order of the acts can be altered in other embodiments, and the methods disclosed are also applicable to other structures. In other embodiments, some acts that are illustrated and/or described may be omitted in whole or in part.

Referring toFIG.5A, a first interconnect layer106is formed within a first inter-level dielectric (ILD) layer104aover a substrate102. The first ILD layer104amay include an oxide, a low-k dielectric, or an ultra low-k dielectric. In some embodiments, the first interconnect layer106may be formed by selectively etching the first ILD layer104ato define an opening within the first ILD layer104a. A metal such as copper and aluminum is then deposited to fill the opening, and a planarization process such as a chemical mechanical planarization process is performed to remove excess metal.

Referring toFIG.5B, a first electrode film212, a dielectric data storage film214, a second electrode film216, a first work function metal film222, a first barrier film223, a selector film224, a second barrier film225, a second work function metal film226and a third electrode film228are sequentially formed over the first interconnect layer106and the first ILD layer104a. In some embodiments, the above layers may be formed using a deposition process such as, for example, CVD, PVD, PE-CVD, sputtering, ALD, some other suitable deposition process(es), or any combination of the foregoing. In some alternative embodiments, in the method of forming the memory device100,100a,100b,100d,100eofFIGS.1,2A,2B,4A and4B, at least one of the first work function metal film222, the second work function metal film226, the first barrier film223and the second barrier film225may be omitted.

Referring toFIG.5C, a patterning process is performed to form a first electrode112, a dielectric data storage layer114, a second electrode116, a first work function metal layer122, a first barrier layer123, a selector layer124, a second barrier layer125, a second work function metal layer126and a third electrode layer128. In some embodiments, a memory cell110and a selector120is formed after the patterning process. In some embodiments, the patterning process includes forming a masking layer (not shown) over the third electrode film228. In some embodiments, the masking layer may include silicon-oxide (SiO2), silicon-oxynitride (SiON), silicon-nitride (SiN) silicon-carbide (SiC), or a similar material. The substrate is then exposed to an etchant, configured to define the memory cell and the selector by selectively removing unmasked parts of the first electrode film212, the dielectric data storage film214, the second electrode film216, the first work function metal film222, the first barrier film223, the selector film224, the second barrier film225, the second work function metal film226and the third electrode film228. In some embodiments, the etchant may include a dry etchant or a wet etchant. In some alternative embodiments, according to the requirements, the first electrode film212, the dielectric data storage film214, the second electrode film216, the first work function metal film222, the first barrier film223, the selector film224, the second barrier film225, the second work function metal film226and the third electrode film228may be patterned separately or some of them may be patterned simultaneously.

Referring toFIG.5D, a second ILD layer104bis formed over the memory device100. In some embodiments, the second ILD layer104bdirectly contacts sidewalls of the memory cell110and the selector120and covers a portion of the third electrode film228. Then, a second interconnect layer130is formed within the second ILD layer104b. The second ILD layer104bmay, for example, be formed by CVD, PVD, some other suitable deposition process(es), or any combination of the foregoing. In some embodiments, the second interconnect layer130may be formed by selectively etching the second ILD layer104bto define an opening within the second ILD layer104b. A metal such as copper and aluminum is then deposited to fill the opening, and a planarization process such as a chemical mechanical planarization process is performed to remove excess metal. Then, the memory device100ofFIG.3is formed.

The present disclosure relates to a RRAM device having an inserted selector including a work function metal layer and/or a barrier layer. The work function metal layer and the barrier layer are configured to provide certain electron affinity and work function, so as to reduce the subthreshold leakage of the threshold-type selector. Therefore, the off-state current of the RRAM device is reduced and a reliability of the RRAM device can be improved.

According to some embodiments, a memory device includes a memory cell, a selector layer and a first work function metal layer. The selector layer is disposed between a first electrode and a second electrode over the memory cell. The first work function metal layer is disposed between the selector layer and the first electrode.

According to some embodiments, a memory device includes a first electrode, a dielectric data storage layer, a second electrode, a selector layer, a third electrode and a first work function metal layer. The dielectric data storage layer is disposed over the first electrode. The second electrode is disposed over the dielectric data storage layer. The selector layer is disposed over the second electrode. The third electrode is disposed over the selector layer. The first work function metal layer is disposed between the selector layer and one of the second electrode and the third electrode.

According to some embodiments, a method of forming a memory device includes: forming a first electrode; forming a dielectric data storage layer over the first electrode; forming a second electrode over the dielectric data storage layer; forming a selector layer over the second electrode; forming a third electrode over the selector layer; and forming a first work function metal layer between the selector layer and one of the second electrode and the third electrode.

According to some embodiments, a memory device includes a first electrode, a selector layer and a plurality of first work function layers. The first work function layers are disposed between the first electrode and the selector layer, and a work function of the first work function layer increases as the first work function layer becomes closer to the selector layer.

According to some embodiments, a memory device includes a first electrode, a selector layer and a plurality of first work function layers. The first work function layers are disposed between the first electrode and the selector layer, and a thickness of the first work function layer decreases as the first work function layer becomes closer to the selector layer.

According to some embodiments, a method of forming a memory device includes the following steps. A first electrode is formed. A plurality of first work function layers are formed over the first electrode. A selector layer is formed over the plurality of first work function layers. A work function of the first work function layer increases as the first work function layer becomes closer to the selector layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.