Patent ID: 12230720

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a feature on, connected to, and/or coupled to another feature in the present disclosure that follows may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the features, such that the features may not be in direct contact. In addition, spatially relative terms, for example, “lower,” “upper,” “horizontal,” “vertical,” “above,” “over,” “below,” “beneath,” “up,” “down,” “top,” “bottom,” etc. as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) are used for ease of the present disclosure of one features relationship to another feature. The spatially relative terms are intended to cover different orientations of the device including the features.

Furthermore, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range including the number described, such as within +/−10% of the number described or other values as understood by person skilled in the art. For example, the term “about 5 nanometers” encompasses the dimension range from 4.5 nanometers to 5.5 nanometers. Still further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

GAA FETs have demonstrated attractive qualities over single-gate devices in terms of control over short-channel effects (SCEs) and driving ability. A GAA FET may generally include a stack of channel layers in a multi-layer structure (ML) disposed over a substrate, epitaxial S/D features formed over or in an active region (e.g., a fin), and a metal gate structure interleaved with the stack of channel layers and interposed between the S/D features. However, in some instances, GAA FETs may suffer current leakage at the bottommost portion of the stack of channel layers between the S/D features. To address this issue, some existing implementations introduce a doped well in the semiconductor substrate to reduce the extent of current leakage. While this and other approaches have been generally adequate, they are not entirely satisfactory in all aspects. For example, dopants from the doped well may inadvertently diffuse into the stack of the channel layers (especially the bottommost channel layer) and cause degradation in carrier mobility. In other existing implementations, a buried isolation layer between two semiconductor layers (e.g., an oxide layer buried between two silicon layers in a silicon-on-isolator substrate) may be introduced as the substrate to curtail any potential current punch-through between the S/D features. In this regard, however, because the top semiconductor layer of the substrate also serves as the bottommost channel layer, reducing current leakage may be improved at the expense of other issues related to the fabrication of the GAA FETs. Thus, for at least these reasons, improvements in methods of forming GAA FETs with improved processing feasibility and reduced current leakage are desired.

Referring toFIG.1, a flowchart of a method150of forming a semiconductor structure200(hereafter simply referred to as the “structure200”) is illustrated according to various aspects of the present disclosure. Method150is merely an example and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, and after method150, and some operations described can be replaced, eliminated, or moved around for additional embodiments of the method. Method150is described below in conjunction withFIGS.3-14B, which are cross-sectional views of the structure200taken along the dashed lines AA′ and BB′ shown inFIGS.2A and2Bat intermediate steps of method150. The structure200may be an intermediate device fabricated during processing of an IC, or a portion thereof, that may comprise static random-access memory (SRAM) and/or other logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as GAA FETs, FinFETs, metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, and/or other transistors. The present disclosure is not limited to any particular number of devices or device regions, or to any particular device configurations. For example, though the structure200as illustrated is a three-dimensional device, the present disclosure may also provide embodiments for fabricating planar devices. Additional features can be added to the structure200, and some of the features described below can be replaced, modified, or eliminated in other embodiments of the structure200.

Referring toFIGS.1,2A,2B, and3, method150at operation152provides (or is provided with) a semiconductor substrate202(hereafter referred to as the “substrate202”). In the present embodiments, referring toFIG.3, the substrate202includes a top semiconductor layer202cdefined by a thickness t1, an isolation layer202bdefined by a thickness t0, and a bottom semiconductor layer202ahaving a thickness that is much greater than t0and t1, where the isolation layer202bis sandwiched or buried between the bottom semiconductor layer202aand the top semiconductor layer202c.

The top semiconductor layer202cand the bottom semiconductor layer202amay each include an elemental (single element) semiconductor, such as silicon (Si), germanium (Ge), and/or other suitable materials; a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), and/or other suitable materials; and/or an alloy semiconductor, such as SiGe, GaAsP, AnnAs, AlGaAs, GalnAs, GaInP, GaInAsP, and/or other suitable materials. In the present embodiments, the top semiconductor layer202cand the bottom semiconductor layer202aare each free of a dielectric material. In the present embodiments, the isolation layer202bincludes a dielectric material, such as silicon oxide (SiO and/or SiO2), silicon nitride (SiN), oxygen-containing silicon nitride (SiON), and/or other suitable materials. In the present embodiments, the top semiconductor layer202chas substantially the same composition as the bottom semiconductor layer202aand both include silicon, where the isolation layer202bincludes SiOx.

In some examples where the structure200includes FETs, various doped regions may be disposed in or on the substrate202. The doped regions may be doped with n-type dopants, such as phosphorus or arsenic, and/or p-type dopants, such as boron or BF2, depending on design requirements. The doped regions may be formed directly on the substrate202, in a p-well structure, in an n-well structure, in a dual-well structure, or in a raised structure. Doped regions may be formed by implantation of dopant atoms, in-situ doped epitaxial growth, and/or other suitable techniques. Of course, these examples are for illustrative purposes only and are not intended to be limiting.

Referring toFIGS.1and4A, method150at operation154oxidizes a top portion of the top semiconductor layer202cin a process420A to form an oxidized top portion202d. The top portion of the top semiconductor layer202cmay be oxidized utilizing any suitable method. In some embodiments, the oxidizing process includes thermal oxidation, chemical oxidation, and/or other suitable methods. In some embodiments, the oxidized top portion202dhas a thickness t that is about 35% to about 55% (e.g., about 45%) of the thickness t1. In some examples, the thickness t may be about 7 nanometers to about 11 nanometers (e.g., about 9 nanometers), while t1may be about 20 nanometers.

Referring toFIGS.1and4B, method150at operation156removes the oxidized top portion202din an etching process420B to form a recessed top semiconductor layer202c′. The oxidized top portion202dmay be etched utilizing any suitable method. In some embodiments, the etching process includes dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes. Prior to the process420A and the etching process420B, t1is greater than or equal to t0. In some examples, t1may be about 15 nanometers to 40 nanometers (e.g., 20 nanometers) and to may be about 10 nanometers to 30 nanometers (e.g., 20 nanometers). After performing the process420A and the etching process420B, the recessed top semiconductor layer202c′ has a thickness t2that is less than the thickness t0. In some embodiments, the thickness t2is about 45% to about 65% (e.g., about 55%) of the thickness t0. In some embodiments, the thickness t2is about 35% to about 75% of the thickness t1. In some examples, t2may be about 9 nanometers to about 13 nanometers. In one such example, t2may be about 11 nanometers while to may be about 20 nanometers.

As will be discussed in detail below, the recessed top semiconductor semiconductor layer202c′ serves as one of the channel layers (e.g., the bottommost channel layer) of a multi-layer stack subsequently formed over the substrate202. If the percentage of the thickness t2with respect to the thickness t0is greater than about 65%, a metal gate structure formed in subsequent processes may not have sufficient gate control over the recessed top semiconductor layer202c′, especially at its bottom portion that is closest to the substrate202. The insufficient gate control increases current leakage between two adjacent S/D features and results in poor device performance. On the other hand, if the percentage of the thickness t2with respect to the thickness t0is less than about 45%, the process control may become challenging during subsequent fabricating processes. For example, the isolation layer202bmay be inadvertently exposed when forming S/D recesses, thus inhibiting the uniform growth of epitaxial S/D features in the S/D recesses.

Referring toFIGS.1,2A,2B,5A, and5B, method150at operation158forms fin active regions204(hereafter referred to as the “fins204”) over the substrate202in a process520. In the present embodiments, each fin204includes a portion of the recessed top semiconductor layer202c′ protruding from the isolation layer202b, and a stack of alternating layers204aand204b(collectively referred to as the “multi-layer stack” or ML) disposed thereover, where the ML has a thickness t3. Each fin204includes S/D regions and channel regions adjacent to the S/D regions along the fins204. The channel regions include the ML, which interleaves with a metal gate stack formed in subsequent processes over the fins204. The S/D regions are subsequently recessed to expose the recessed top semiconductor layer202c′ (which is also the bottom most layer of the fins204), from where epitaxial features are formed. In the present embodiments, each layer204aincludes a semiconductor material such as, for example, Si, Ge, SiC, SiGe, GeSn, SiGeSn, SiGeCSn, and/or other suitable semiconductor materials, while each layer204bis a sacrificial layer having a different composition from that of the layers204a. In one such example, the layers204amay include elemental Si but is free, or substantially free, of Ge, and the layers204bmay include SiGe. In another example, the layers204amay include elemental Si but is free, or substantially free, of Ge, while the layers204bmay include elemental Ge but is free, or substantially free, of Si. In the present embodiments, the recessed top semiconductor layer202c′ and the layers204aof the ML are configured to have substantially the same composition (e.g., elemental Si and free, or substantially free, of Ge). Stated differently, in some embodiments, the recessed top semiconductor layer202c′ is considered the bottommost layer of the fins204. In some examples, the fins204may include a total of three to ten pairs of alternating layers204aand204b; of course, other configurations may also be applicable depending upon specific design requirements.

In the present embodiments, forming the ML includes alternatingly growing the layers204aand204bin a series of epitaxy processes, including chemical vapor deposition (CVD) techniques (for example, vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), low-pressure CVD (LP-CVD), and/or plasma-enhanced CVD (PE-CVD)), molecular beam epitaxy, and/or other suitable selective epitaxial growth (SEG) processes. The epitaxy process may use gaseous and/or liquid precursors containing Si and/or Ge. In some examples, the layers204aand204bmay be formed into nanosheets, nanowires, or nanorods. A sheet (or wire) formation process may then remove the layers204bto form multiple openings between the layers204a. A metal gate structure is subsequently formed in the openings and over the ML, thereby providing a GAA FET. For this reason, the layers204aare hereafter referred to as channel layers204a, and the layers204bare hereafter referred to as non-channel layers204b.

The fins204may be fabricated using suitable processes including photolithography and etch processes. The photolithography process may include forming a photoresist layer (resist) overlying the ML, exposing the resist to a pattern, performing post-exposure bake processes, and developing the resist to form a masking element (not shown) including the resist. The masking element is then used for etching recesses206in the ML and the recessed top semiconductor layer202c′, thereby exposing portions of the isolation layer202band leaving the fins204protruding from the isolation layer202b. It is noted that the recessed top semiconductor layer202c′ servesas the bottommost channel layer of the fins204. The etching process may include dry etching, wet etching, RIE, and/or other suitable processes.

Numerous other embodiments of methods for forming the fins204may be suitable. For example, the fins204may be patterned using double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the fins204.

Now referring toFIGS.1,6A, and6B, the method150at operation160forms a dielectric layer203over the structure200in a process620. In some embodiments, the dielectric layer203fills the recesses206between the fins204. In some embodiments, portions of the dielectric layer203is formed over a top surface of the fins204. The dielectric layer203may include silicon oxide (SiO and/or SiO2), silicon nitride (SiN), oxygen-containing silicon nitride (SiON), fluoride-doped silicate glass (FSG), a low-k dielectric material, and/or other suitable materials. In some embodiments, the dielectric layer203includes the same composition as that of the isolation layer202b. In some embodiments, the dielectric layer203includes a multi-layer structure, for example, having one or more thermal oxide liner layers. The dielectric layer203may be deposited by any suitable method, such as CVD, flowable CVD (FCVD), spin-on-glass (SOG), and/or other suitable methods.

Referring toFIGS.1,7A, and7B, the method150at operation162recesses the dielectric layer203to form isolation structures208in a process720. In some embodiments, the process720includes applying a chemical mechanical planarization (CMP) process to remove the portions of the dielectric layer203formed over the fins204, followed by recessing the dielectric layer203to form the isolation structures208, thereby re-exposing the recesses206between the fins204. The isolation structures208may include different structures, such as shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, and/or local oxidation of silicon (LOCOS) structures. The recessing process may include dry etching, wet etching, RIE, and/or other suitable processes.

Referring toFIG.7C, a portion205of the structure200shown inFIG.7Bis enlarged to depict various components after the recessing of the dielectric layer203. The process720forms the isolation structures208to a thickness t4by recessing the dielectric layer203by a depth t5. The thickness t4is configured to control the depth of subsequently-formed S/D recesses in the S/D regions of each fin204, as will be described in detail later. In some embodiments, the thickness t4is less than the thickness t0. In some examples, the thickness t4may be about 45% to about 65% (e.g., about 55%) of the thickness t0. In some embodiments, the thickness t4is less than or equal to the thickness t2. In some examples, the thickness t4may be about 50% to about 100% (e.g., about 75%) of the thickness t2. In the present embodiments, the thickness t4is about the same as the thickness t2, such that the isolation structures208substantially cover sidewalls of the recessed top semiconductor layer202c′(which is also the bottommost layer of the fins204). In other words, the depth t5of the recess206is substantially the same as a thickness t3of the ML. In one example, the thickness t4is about 9 nanometers to about 13 nanometers (e.g., about 11 nanometers).

If the thickness t4is too large, i.e., greater than about 65% of the thickness t0or greater than the thickness t2, the metal gate structure formed in subsequent processes may not have sufficient control over the bottommost layer of the fins204. If the thickness t4is too small, i.e., less than about 45% of the thickness t0or less than about 50% of the thickness t2, forming the S/D recesses may inadvertently penetrate both the isolation structures208and the isolation layer202b, thereby inadvertently exposing the bottom semiconductor layer202aas will be discussed below.

In some embodiments, the isolation structures208include a curved top surface adjacent to the fins204. In some embodiments, the curved top surface is above a top surface of the recessed top semiconductor layer202c′. The curved top surface defines feet201of the isolation structures208adjacent to the fins204protruding from the isolation structures208. The feet201are each defined by a width w1in a horizontal direction and a height t7in a vertical direction as depicted inFIG.7C. The feet201cover sidewalls of the bottom portion of the ML, thereby leaving an exposed portion of the fins204(i.e., ML) having a thickness t6. In some embodiments, t6is less than t3and/or t5. In one example, the feet201may cover sidewalls of the non-channel layers204bimmediately above the recessed top semiconductor layer202c′. In a further example, the height t7does not exceed a thickness of the non-channel layer204bimmediately above the recessed top semiconductor layer202c′. In some embodiments, at least portions of the feet201remain in the structure200. For examples, portions of the feet201in the S/D regions of the fins204(as depicted inFIGS.7B and7C) may remain in the structure200after the forming of the S/D recesses, such that fin spacers may be formed thereover. In some embodiments, portions of the feet201are removed from the structure200by subsequent processes. For example, portions of the feet201in the channel regions of the fins204may be removed along with the non-channel layers204bof the ML before forming the metal gate structure.

Referring toFIGS.1,8A, and8B, method150at operation164forms one or more dummy gate stacks (i.e., a placeholder gate)210that includes polysilicon over the fins204in a process820. In the present embodiments, portions of the dummy gate stacks210are replaced with a metal gate stacks after forming other components of the structure200. The process820may include a series of deposition and patterning processes. For example, the process820may include depositing a polysilicon layer over the fins204and performing an anisotropic etching process (e.g., a dry etching process) to remove portions of the polysilicon layer, resulting in the dummy gate stacks210disposed over the channel regions of the fins204. In the present embodiments, the structure200further includes an interfacial layer211, which is formed over the fins204before depositing the polysilicon layer by a suitable method, such as thermal oxidation, chemical oxidation, and/or other suitable methods. Though not depicted, one or more hard mask layers may be formed over the dummy gate stacks210to protect the dummy gate stacks210from being damaged during subsequently operations. The one or more hard mask layers are later removed before removing the dummy gate stacks210to form the metal gate stacks.

Thereafter, still referringFIGS.8A and8B, method150forms gate spacers212and fin spacers207over sidewalls of the dummy gate stacks210and sidewalls of the fins204(e.g., over the portions of the feet201as depicted herein), respectively. The spacer layer may include silicon oxide (SiO and/or SiO2), silicon nitride (SiN), silicon carbide (SiC), oxygen-containing silicon nitride (SiON), carbon-containing silicon oxide (SiOC), and/or other suitable materials. The spacer layer may be a single-layer structure or a multi-layer structure including a combination of the dielectric materials provided herein. The method150may form the gate spacers212and the fin spacers207by first depositing a spacer layer over the structure200and subsequently removing portions of the spacer layer in an anisotropic etching process (e.g., a dry etching process), leaving behind portions of the spacer layer on the sidewalls of the dummy gate stacks210as the gate spacers212and on the sidewalls of the fins204as fin spacers207.

Referring toFIGS.1,9A, and9B, method150at operation166forms S/D recesses213in S/D regions of the fins204to expose the recessed top semiconductor layer202c′in a recessing process920. In the present embodiments, the recessing process920is a dry etching process employing a suitable etchant capable of removing Si (i.e., the channel layers204a) and SiGe (i.e., the non-channel layers204b) of the ML. In some embodiments, the dry etchant is a chlorine-containing etchant including Cl2, SiCl4, BCl3, and/or other chlorine-containing gas. In some embodiments, the recessing process920is tuned by adjusting duration, temperature, pressure, source power, bias voltage, bias power, etchant flow rate, and/or other suitable parameters. A cleaning process may subsequently be performed to clean the S/D recesses213with a hydrofluoric acid (HF) solution or other suitable solution.

As shown inFIG.9A, the S/D recesses213penetrate the recessed top semiconductor layer202c′by a depth t8, such that and a remaining portion of the recessed top semiconductor layer202c′under the S/D recesses213has a thickness t2′. The S/D recesses213are formed between adjacent dummy gate stacks210along the X direction. The endpoint of the recessing process920may be gauged by either the depth t8or the thickness t2′. In some embodiments, the depth t8may be about 15% to about 35% (e.g., about 25%) of the thickness t0or about 25% to about 65% (e.g., about 45%) of the thickness t2. In some examples, the depth t8may be about 3 nanometers to about 7 nanometers (e.g., 5 nanometers). In some embodiments, the thickness t2′ is less than the thickness t0. In some embodiments, the thickness t2′ is about 20% to about 40% of the thickness t0or about 35% to about 75% (e.g., about 55%) of the thickness t2. In some examples, the thickness t2′ may be about 4 nanometers to about 8 nanometers (e.g., 6 nanometers). If the depth t8is too small (i.e., the thickness t2′ is too large), e.g., less than about 15% of the thickness t0or less than about 25% of the thickness t2, the ability of the isolation layer202bto impede current leakage between the S/D features subsequently formed in the S/D recesses213may be weakened. On the other hand, if the depth t8is too large (i.e., the thickness t2′ is too small), e.g., over about 35% of the thickness t0or over about 65% of the thickness t2, the process control may become challenging. For example, the forming of the S/D recess213may inadvertently expose a portion of the isolation layer202bin the S/D recesses213where are not suitable for the epitaxial S/D features216to grow from in subsequent processes.

In the present embodiments, referring toFIG.9B, forming the S/D recesses213removes portions of the isolation structures208adjacent to the S/D regions of the fins204along the Y direction, thereby forming a recess215. In some embodiments, the recess215penetrates the isolation structures208without penetrating the isolation layer202b, i.e., the isolation layer202bis not exposed in the recess215. In some embodiments, the recess215penetrates the isolation structure208to expose a top surface of the isolation layer202b. In some embodiments, as depicted herein, the recess215further penetrates the isolation layer202bby a depth t9after penetrating through the isolation structures208, where the depth t9is less than the thickness t0. In some embodiments, t9might be 0 nanometer. In other words, the recess215does not penetrate the isolation layer202b. In some examples, the depth t9may be less than or equal to about 95% of the thickness t0. In other words, a thickness t0′ of the remaining portion of isolation layer202bunder the recess215may be at least about 5% of the thickness t0. In some examples, the thickness t0′ may be about 1 nanometer to about 20 nanometers. If the thickness t0′ is too small, i.e., less than about 5% of the thickness t0, the isolation layer202bmay be inadvertently penetrated through, thereby exposing a portion of the bottom semiconductor layer202ain the recess215. In this case, an epitaxial semiconductor feature may inadvertently grow from the exposed portion of the bottom semiconductor layer202ain the recess215in addition to the desired growth from the portion of the recessed top semiconductor layer202c′exposed in the S/D recesses213. The inadvertently grown epitaxial semiconductor features in the recess215may connect adjacent epitaxial S/D features along the Y direction, thereby causing shorting issues in the structure200.

Still referring toFIG.9B, the dotted profile outlines each fin204before performing the recessing process920to illustrate a depth t10of the S/D recesses213in comparison to a height t11(i.e., fin height) of the fins204, the thickness t4, and the thickness t9. In some embodiments, the height t10is about 85% to about 95% (e.g., about 90%) of the thickness t11. In some embodiments, the height t10is greater than a sum of the thickness t4and the thickness t9. In some examples, the sum of the thickness t4and the thickness t9may be less than about 65% of the thickness t10. In some examples, t10may be about 52 nanometers to about 56 nanometers (e.g., about 54 nanometers), while t11may be about 60 nanometers, t4may be about 6 nanometers, and t9may be about 29 nanometers.

As explained above regardingFIGS.9A and9B, the recessing process920removes the S/D regions of the fins204to form the S/D recesses213, while removes the isolation structures208and the isolation layers202bto form recess215. However, the ML, the isolation structures208, and the isolation layer202bare configured with different materials and thus have different etching rates during the recessing process920. When a desired value of the thickness t2′ is reached, the recess215may be too deep such that the bottom semiconductor layer202ais inadvertently exposed. To compensate for the differences in the etching rate such that the depth of the recess215can be controlled in a reasonable range (i.e., the thicknesses t0′ and t9are within the ranges as discussed above), the isolation structures208are configured to the thickness t4that is about 45% to about 65% of the thickness t0as discussed above. If the thickness t4of the isolation structures208is too small, e.g., less than about 45% of the thickness t0, the recessing process920may etch through the isolation layer202band thus expose a portion of the bottom semiconductor layer202ain the recess215. The exposed portion of the bottom semiconductor layer202amay serve as a growth surface for unintentional epitaxial growth between adjacent fins204when forming S/D features in the S/D recesses213. On the other hand, if t4is too large, e.g., greater than about 65% of the thickness t0, the metal gate structure formed in subsequent processes may not cover the sidewalls of the recessed top semiconductor layer202c′(which is also the bottommost layer of the fins204) sufficiently, thus weakening the gate control of the metal gate structure.

Referring toFIGS.10A and10B, method150forms inner spacers214on portions of the non-channel layers204bexposed in the S/D recesses213. The inner spacers214may include any suitable dielectric material comprising silicon, carbon, oxygen, nitrogen, and/or other suitable elements. For example, the inner spacers214may include silicon nitride (SiN), silicon oxide (SiO and/or SiO2), carbon-containing silicon nitride (SiCN), carbon-containing silicon oxide (SiOC), oxygen-containing silicon nitride (SiON), silicon (Si), carbon-and-oxygen-doped silicon nitride (SiOCN), a low-k dielectric material, tetraethylorthosilicate (TEOS), doped silicon oxide (e.g., borophosphosilicate glass (BPSG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), etc.), air, and/or other suitable dielectric material. The inner spacers214may each be configured as a single-layer structure or a multi-layer structure including a combination of the dielectric materials provided herein. In some embodiments, the inner spacers214have a different composition from that of the gate spacers212.

Method150may form the inner spacers214in a series of etching and deposition processes. For example, forming the inner spacers214may begin with selectively removing portions of the non-channel layers204b(without removing or substantially removing portions of the channel layers204aand the recessed top semiconductor layer202c′) to form trenches (not depicted). The non-channel layers204bmay be removed by any suitable process, such as a dry etching process. Subsequently, one or more dielectric layers are formed in the trenches, followed by one or more etching processes to remove (i.e., etch back) excess dielectric layer(s) deposited on exposed surfaces of the channel layers204aand the recessed top semiconductor layer202c′, thereby forming the inner spacers214as depicted inFIG.10A. The one or more dielectric layers may be deposited by any suitable method, such as atomic layer deposition (ALD), CVD, physical vapor deposition (PVD), and/or other suitable methods.

Still referring toFIGS.10A and10B, method150at operation168forms an epitaxial S/D feature216in each S/D recess213in a process1020. Each of the epitaxial S/D features216may be suitable for forming a p-type FET device (e.g., including a p-type epitaxial material) or alternatively, an n-type FET device (e.g., including an n-type epitaxial material). The p-type epitaxial material may include one or more epitaxial layers of silicon germanium (epi SiGe), where the silicon germanium is doped with a p-type dopant such as boron, germanium, indium, and/or other p-type dopants. The n-type epitaxial material may include one or more epitaxial layers of silicon (epi Si) or silicon carbon (epi SiC), where the silicon or silicon carbon is doped with an n-type dopant such as arsenic, phosphorus, and/or other n-type dopants. In some embodiments, one or more epitaxy growth processes are performed to grow an epitaxial material in each S/D recess213. For example, method150may implement the epitaxy growth process as discussed above with respect to forming the layers204aand204bof the ML. In some embodiments, the epitaxial material is doped in-situ by adding a dopant to a source material during the epitaxy process. In some embodiments, the epitaxial material is doped by an ion implantation process after performing the epitaxy process. In some embodiments, an annealing process is subsequently performed to activate the dopants in the epitaxial S/D features216.

Referring toFIGS.11A and11B, after forming the epitaxial S/D features216, method150forms an interlayer dielectric (ILD) layer220over the structure200by CVD, FCVD, SOG, and/or other suitable methods. The ILD layer220may include silicon oxide, a low-k dielectric material, TEOS, doped silicon oxide (e.g., BPSG, FSG, PSG, BSG, etc.), and/or other suitable dielectric materials. In the depicted embodiments, method150first forms an etch-stop layer (ESL)218over the epitaxial S/D features216and the dummy gate stacks210before forming the ILD layer220. The ESL218may include silicon nitride (SiN), oxygen-containing silicon nitride (SiON), oxygen-doped silicon nitride (SiON), carbon-doped silicon nitride (SiCN), and/or other suitable materials, and may be formed by CVD, PVD, ALD, and/or other suitable methods. Thereafter, method150may planarize the ILD layer220and the ESL218in one or more CMP processes to expose a top surface of the dummy gate stacks210.

Thereafter, method150at operation170replaces the dummy gate stacks210and the non-channel layers204bwith a metal gate structure230as shown inFIGS.11A to13B. Firstly, as shown inFIGS.11A and11B, at least portions of the dummy gate stacks210are removed from the structure200to form the gate trenches222in an etching process1120. The etching process1120may include a dry etching process. In some embodiments, the interfacial layer211remains over the ML after removing the dummy gate stacks210.

Referring toFIGS.12A and12B, method150removes the non-channel layers204bfrom the ML in an etching process1220, thereby forming openings224between the channel layers204aand the recessed top semiconductor layer202c′. The non-channel layers204bmay be selectively removed by any suitable etching process, such as dry etching, wet etching, RIE, or combinations thereof, without removing, or substantially removing the channel layers204a. In one example, a wet etching process employing ammonia (NH3) and/or hydrogen peroxide (H2O2) may be performed to selectively remove the non-channel layers204b. In another example, a dry etching process employing HF and/or other fluorine-based etchant(s), such as CF4, SF6, CH2F2, CHF3, C2F6, and/or other fluorine-containing etchants, may be implemented to remove the non-channel layers204b. Portions of the feet201in the channel regions of the fins204under the dummy gate may be removed or substantially removed in the etching process1220, such that the gate control over the channel regions of the fins204may not be compromised. A cleaning process may be subsequently performed to remove any etching residue from the openings224.

Referring toFIGS.13A and13B, method150subsequently forms the metal gate structure230over the interfacial layer211in the gate trenches222and in the openings224in a process1320, such that the metal gate structure230is interposed between the epitaxial S/D features216. The metal gate structure230includes at least a high-k dielectric layer (not depicted) disposed in the gate trenches222and in the openings224and a metal gate electrode (not depicted) disposed over the high-k dielectric layer. The high-k dielectric layer may include any suitable high-k dielectric material, such as hafnium oxide, lanthanum oxide, and/or other suitable materials. The metal gate electrode may include at least one work function metal layer and a bulk conductive layer disposed over the work function metal layer. The work function metal layer includes a p-type and/or an n-type work function metal layer. Example work function materials include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, and/or other suitable work function materials. The bulk conductive layer may include Cu, W, Al, Co, Ru, and/or other suitable materials. The metal gate structure230may further include numerous other layers (not depicted), such as a capping layer, a barrier layer, and/or other suitable layers. Various layers of the metal gate structure230may be deposited by any suitable method, such as ALD, CVD, PVD, plating, and/or other suitable methods.

Thereafter, referring toFIGS.14A and14B, method150at operation172performs additional processing steps to the structure200. For example, method150may form S/D contacts242over the epitaxial S/D features216. Each S/D contact242may include any suitable conductive material, such as Co, W, Ru, Cu, Al, Ti, Ni, Au, Pt, Pd, and/or other suitable conductive materials. Method150may form an S/D contact hole (or trench) in the ILD layer220via a series of patterning and etching processes and subsequently deposit a conductive material in the S/D contact hole using any suitable method, such as CVD, ALD, PVD, plating, and/or other suitable processes. In some embodiments, a silicide layer (not depicted) is formed between the epitaxial S/D features216and the S/D contact242. The silicide layer may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, and/or other suitable silicide. The silicide layer may be formed over the epitaxial S/D feature216by a series of deposition, thermal, and etching processes. Subsequently, method150may form additional features over the structure200including, for example, an ESL250disposed over the ILD layer220, an ILD layer252disposed over the ESL250, a gate contact254in the ILD layer252to contact the metal gate structure230, vertical interconnect features (e.g., vias; not depicted), horizontal interconnect features (e.g., conductive lines; not depicted), additional intermetal dielectric layers (e.g., ESLs and ILD layers; not depicted), and/or other suitable features.

Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to a semiconductor device and the formation thereof. For example, the present disclosure provides a semiconductor structure that includes a substrate having a top semiconductor layer over an isolation layer, where the top semiconductor layer is recessed to a desired thickness to reduce current leakage. In the present embodiments, the recessed top semiconductor layer has a thickness less than that of the isolation layer. Furthermore, in the present embodiments, isolation features (e.g., STI) are configured as an etching buffer, such that the forming of the S/D recess does not penetrate the bottom semiconductor layer of the substrate inadvertently. Embodiments of the disclosed methods can be readily integrated into existing processes and technologies for manufacturing GAA FETs.

In one aspect, the present disclosure provides a method that includes providing a substrate including a first semiconductor layer over a dielectric layer, thinning the first semiconductor layer to a thickness less than a thickness of the dielectric layer, forming a stack of alternating second semiconductor layers and third semiconductor layers over the thinned first semiconductor layer, and forming a fin active region protruding from the substrate, where the fin active region includes a portion of the thinned first semiconductor layer and the stack of alternating second semiconductor layers and third semiconductor layers disposed thereon, and where the forming of the fin active region exposes a portion of the dielectric layer. The method then proceeds to forming isolation features over the exposed portion of the dielectric layer, where the isolation features cover sidewalls of the thinned first semiconductor layer, forming a dummy gate stack over the fin active region, forming a source/drain (S/D) recess in the fin active region adjacent to the dummy gate stack, where forming the S/D recess removes a portion of the thinned first semiconductor layer, and forming an epitaxial S/D feature in the S/D recess. Thereafter, the method removes the second semiconductor layers to form openings between the third semiconductor layers, where the openings are formed adjacent to the epitaxial S/D feature and forms a metal gate stack in the openings and in place of the dummy gate stack.

In another aspect, the present disclosure provides a method that includes providing a semiconductor layer over an oxide layer, oxidizing a portion of the semiconductor layer, etching the oxidized portion of the semiconductor layer, such that the etched semiconductor layer is defined by a thickness less than a thickness of the oxide layer, forming a multi-layer structure (ML) including alternating channel layers and non-channel layers over the etched semiconductor layer, patterning the ML and the etched semiconductor layer to form a fin active region, thereby exposing a portion of the oxide layer, and forming an isolation structure surrounding a bottom portion of the fin active region, where the forming includes: depositing an isolation material over the exposed portion of the oxide layer, and recessing the isolation material to form the isolation structure having a thickness less than that of the oxide layer. The method then proceeds to forming a placeholder gate stack over the fin active region, forming a source/drain (S/D) recess in the fin active region and adjacent to the placeholder gate stack to penetrate the etched semiconductor layer, where a depth of the penetration in the etched semiconductor layer is less than a thickness of the oxide layer, and forming an S/D feature in the S/D recess. Thereafter, the method forms a metal gate stack in place of the placeholder gate stack and the non-channel layers of the ML.

In yet another aspect, the present disclosure provides a semiconductor structure including a substrate having a dielectric layer over a semiconductor layer, a fin protruding from the dielectric layer, where the fin includes a stack of channel layers, and a metal gate structure disposed over the fin and interleaved with the stack of channel layers. In the present embodiments, the semiconductor structure includes an isolation structure over the dielectric layer covering sidewalls of a bottommost channel layer, and an epitaxial source/drain (S/D) feature disposed adjacent to the metal gate structure, where a bottom surface of the epitaxial S/D feature is defined by the bottommost channel layer, and where a portion of the bottommost channel layer under the epitaxial S/D feature has a thickness less than a thickness of the dielectric layer.

The foregoing outlines features of several embodiments so that those of ordinary skill in the art may better understand the aspects of the present disclosure. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.