Patent ID: 12205797

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

DETAILED DESCRIPTION

Embodiments herein are generally directed electronic device manufacturing and, more particularly, to systems and methods for forming low resistivity tungsten features in a semiconductor device manufacturing scheme.

The present disclosure includes a metal oxide semiconductor field effect transistor (MOSFET)-based three-stage topology configured to produce customizable multilevel output waveforms and increase the effective output frequency while masking the switching frequency limitation of the current generation MOSFETs. The embodiments of the present disclosure produce customizable voltage output waveforms catered towards dynamic Ion Energy Distribution Function (IEDF) to add unique tuning knobs in plasma etch recipes. Further, the effective output efficiency of the pulser is increased based on the number of stages and gating signal patterns. The embodiments in the present disclosure also mask the switching frequency limitation of the current generation MOSFETs and reducing the corresponding cooling requirements while generating pulses with different widths in a single output burst and produce a lighter and faster alternative to inductive adder-based pulsers.

FIG.1is a schematic cross-sectional view of a processing system10configured to perform one or more of the plasma processing methods set forth herein. In some embodiments, the processing system10is configured for plasma-assisted etching processes, such as a reactive ion etch (RIE) plasma processing. However, it should be noted that the embodiments described herein may be also be used with processing systems configured for use in other plasma-assisted processes, such as plasma-enhanced deposition processes, for example, plasma-enhanced chemical vapor deposition (PECVD) processes, plasma-enhanced physical vapor deposition (PEPVD) processes, plasma-enhanced atomic layer deposition (PEALD) processes, plasma treatment processing or plasma-based ion implant processing, for example, plasma doping (PLAD) processing.

As shown, the processing system10is configured to form a capacitively coupled plasma (CCP), and includes a processing chamber100that includes an upper electrode (e.g., chamber lid123) disposed adjacent a processing volume129facing a lower electrode (e.g., substrate support assembly136) disposed in the processing volume129opposite the upper electrode. In a typical capacitively coupled plasma (CCP) processing system, a radio frequency (RF) source (e.g., RF generator118) is electrically coupled to one of the upper or lower electrode (inFIG.1, the lower electrode), and delivers an RF signal configured to ignite and maintain a plasma (e.g., plasma101). In this configuration, the plasma is capacitively coupled to each of the upper and lower electrodes and is disposed in the processing volume129between the upper and lower electrodes. Typically, the opposing one of the upper or lower electrodes (inFIG.1, the upper electrode) is coupled to ground or to a second RF power source. In one embodiment as shown inFIG.1, one or more components of the substrate support assembly136, such as the support base107is electrically coupled to a plasma generator assembly163, which includes the RF generator118, and the chamber lid123is electrically coupled to ground. As shown, the processing system10includes the processing chamber100, the support assembly136, and a system controller126.

The processing chamber100typically includes a chamber body113that includes the chamber lid123, one or more sidewalls122, and a chamber base124, which collectively define the processing volume129. The one or more sidewalls122and chamber base124generally include materials that are sized and shaped to form the structural support for the elements of the processing chamber100and are configured to withstand the pressures and added energy applied to them while the plasma101is generated within a vacuum environment maintained in the processing volume129of the processing chamber100during processing. In one example, the one or more sidewalls122and chamber base124are formed from a metal, such as aluminum, an aluminum alloy, or a stainless steel alloy.

A gas inlet128disposed through the chamber lid123is used to deliver one or more processing gases to the processing volume129from a processing gas source119that is in fluid communication therewith. A substrate103is loaded into, and removed from, the processing volume129through an opening (not shown) in one of the one or more sidewalls122, which is sealed with a slit valve (not shown) during plasma processing of the substrate103. The substrate103is supported by the substrate support assembly136. The substrate support assembly136includes a substrate support105configured to support the substrate103thereon, the support base107disposed below the substrate support105, an insulator plate111disposed below the support base107, and a ground plate112disposed below the insulator plate111.

In some embodiments, the processing chamber100further includes a quartz pipe110, or collar, that at least partially circumscribes portions of the substrate support assembly136to prevent the substrate support105and the support base107from contact with corrosive processing gases or plasma, cleaning gases or plasma, or byproducts thereof. Typically, the quartz pipe110, the insulator plate111, and the ground plate112are circumscribed by a liner108. In some embodiments, a plasma screen109is positioned between the liner108and the one or more sidewalls122to prevent plasma from forming in a volume underneath the plasma screen109between the liner108and the one or more sidewalls122.

The system controller126, also referred to herein as a processing chamber controller, includes a central processing unit (CPU)133, a memory134, and support circuits135. The system controller126is used to control the process sequence used to process the substrate103, including the substrate biasing methods described herein. The CPU133is a general-purpose computer processor configured for use in an industrial setting for controlling the processing chamber and sub-processors related thereto. The memory134described herein, which is generally non-volatile memory, may include random access memory, read-only memory, floppy or hard disk drive, or other suitable forms of digital storage, local or remote. The support circuits135are conventionally coupled to the CPU133and comprise cache, clock circuits, input/output subsystems, power supplies, and the like, and combinations thereof. Software instructions (program) and data can be coded and stored within the memory134for instructing a processor within the CPU133. A software program (or computer instructions) readable by CPU133in the system controller126determines which tasks are performable by the components in the processing system10.

Typically, the program, which is readable by CPU133in the system controller126, includes code, which, when executed by the processor (CPU133), performs tasks relating to the plasma processing schemes described herein. The program may include instructions that are used to control the various hardware and electrical components within the processing system10to perform the various process tasks and various process sequences used to implement the methods described herein.

The processing system may include the plasma generator assembly163, and a first pulsed voltage (PV) source assembly196for establishing a first PV waveform at a bias electrode104disposed within the substrate support105as described in more detail herein with respect toFIGS.4-8B. In some embodiments, the plasma generator assembly163delivers an RF signal to the support base107(e.g., power electrode or cathode) which may be used to generate (maintain or ignite) the plasma101in the processing volume129disposed between the substrate support assembly136and the chamber lid123. The bias electrode104is capacitively coupled to the plasma101through a dielectric layer105B of the substrate support105. In some embodiments, the RF generator118is configured to deliver an RF signal having a frequency that is greater than 1 MHz or more, or about 2 MHz or more, such as about 13.56 MHz or more.

As discussed above, in some embodiments, the plasma generator assembly163, which includes the RF generator118and an RF generator assembly160, is generally configured to deliver a desired amount of a continuous wave (CW) or pulsed RF power at a desired substantially fixed sinusoidal waveform frequency to the support base107of the substrate support assembly136based on control signals provided from the system controller126. During processing, the plasma generator assembly163is configured to deliver RF power (e.g., an RF signal) to the support base107disposed proximate to the substrate support105, and within the substrate support assembly136. The RF power delivered to the support base107is configured to ignite and maintain the processing plasma101using the processing gases disposed in the processing volume129and fields generated by the RF power (RF signal) delivered to the support base107by the RF generator118.

In some embodiments, the support base107is an RF electrode that is electrically coupled to the RF generator118via an RF matching circuit162and a first filter assembly161, which are both disposed within the RF generator assembly160.

The processing volume129is fluidly coupled to one or more dedicated vacuum pumps through a vacuum outlet120, which maintain the processing volume129at sub-atmospheric pressure conditions and evacuate processing and other gases therefrom. In some embodiments, the substrate support assembly136, disposed in the processing volume129, is disposed on a support shaft138that is grounded and extends through the chamber base124.

The substrate support assembly136generally includes the substrate support105(e.g., electrostatic chuck substrate support) and the support base107. In some embodiments, the substrate support assembly136can additionally include the insulator plate111and the ground plate112, as is discussed further below. The support base107is electrically isolated from the chamber base124by the insulator plate111, and the ground plate112is interposed between the insulator plate111and the chamber base124. The substrate support105is thermally coupled to and disposed on the support base107. In some embodiments, the support base107is configured to regulate the temperature of the substrate support105, and the substrate103disposed on the substrate support105, during substrate processing.

Typically, the substrate support105is formed of a dielectric material, such as a bulk sintered ceramic material, such as a corrosion-resistant metal oxide or metal nitride material, for example, aluminum oxide (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y2O3), mixtures thereof, or combinations thereof. In embodiments herein, the substrate support105further includes the bias electrode104embedded in the dielectric material thereof.

In one configuration, the bias electrode104is a chucking pole used to secure (i.e., chuck) the substrate103to the substrate supporting surface105A of the substrate support105and to bias the substrate103with respect to the processing plasma101using one or more of the pulsed-voltage biasing schemes described herein. Typically, the bias electrode104is formed of one or more electrically conductive parts, such as one or more metal meshes, foils, plates, or combinations thereof.

In some embodiments, the bias electrode104is electrically coupled to a bias voltage source150, which provides a chucking voltage or pulsed biasing voltage153thereto, such as a pulsed DC voltage between about −5000 V and about 5000 V, using an electrical conductor, such as the coaxial power delivery line106(e.g., a coaxial cable).

A power delivery line157electrically connects the output of the bias voltage source150of the first bias voltage source assembly196to an optional filter assembly151and the bias electrode104. The electrical conductors within the various parts of the power delivery line157may include: (a) one or a combination of coaxial cables, such as a flexible coaxial cable that is connected in series with a rigid coaxial cable, (b) an insulated high-voltage corona-resistant hookup wire, (c) a bare wire, (d) a metal rod, (e) an electrical connector, or (f) any combination of electrical elements in (a)-(e). The optional filter assembly151includes one or more electrical elements that are configured to substantially prevent a current generated by the output of the RF generator118from flowing through the power delivery line157and damaging the bias voltage source150. The optional filter assembly151acts as a high impedance (e.g., high Z) to RF signal generated by the RF generator118, and thus inhibits the flow of current to the bias voltage source150.

FIG.2Ais a schematic diagram of the bias voltage source150. As shown inFIG.2A, the bias voltage source150comprises a DC voltage source210, a first capacitor220connected to the positive terminal of the DC voltage source210, and a first diode230connected with the first capacitor220. The bias voltage source150further includes a first resistor240connected to the positive terminal of the DC voltage source210, a first MOSFET250connected in series to the first resistor240, a first gate voltage source260connected to a gate terminal of the first MOSFET250, and a first blocking diode270connected to a source terminal251of the first MOSFET250. The bias voltage source150may also include a second capacitor222connected in series between the first diode230and ground228, and a second diode232connected in series between the second capacitor222and ground228. As shown, the second capacitor222is connected in series between the first diode230and the second diode232. A second resistor242may be connected at the common point of the first diode230and the second capacitor222. A second MOSFET252, a second gate voltage source262, and second blocking diode272may also be connected in series with the second resistor242, where the cathode of the second blocking diode272is connected to the cathode of the first blocking diode270. As shown, the bias voltage source150may also include a third capacitor224connected in series between the second diode232and ground228. Further, a third resistor244may be connected at the common point of the second diode232and the third capacitor224. A third MOSFET254, a third gate voltage source264, and third blocking diode274may also be connected in series with the third resistor244, where the cathode of the third blocking diode274is connected to the bias electrode104. The full supply voltage will be applied to the load when all the MOSFETs are gated ON at the same time and the widths of the gating signals are identical.

The effective output frequency can be increased three times by turning the MOSFETs (e.g.,250,252, and254) on at different time stamps. Although the effective output frequency is increased using this scheme, each MOSFET operates at a switching frequency which is one-third of the effective output switching frequency. In addition, using a combination of the widths and delays of the gate signals, a wide range of multilevel output voltage waveforms can be generated that corresponds to unique IEDFs that can be a unique addition in plasma etch recipes. By leveraging these features offered by the present disclosure, the selectivity, uniformity, and throughput of the RIE can be increased significantly.

Alternatively, as shown inFIG.2B, the bias voltage source150may comprise the first resistor240to the positive terminal of the DC voltage source210, the first MOSFET250connected in series to the first resistor240, the first gate voltage source260connected to the gate terminal of the first MOSFET250, and the first blocking diode270connected to the source terminal251of the first MOSFET250. Further, the second capacitor222may be connected in series between the first diode230and ground228. The bias voltage source152may also include the second resistor242connected at the common point of the first diode230and the second capacitor222. The second MOSFET252may be connected in series to the second resistor242, the second gate voltage source262connected to a gate terminal of the second MOSFET252, and a second blocking diode272connected to the source terminal253of the second MOSFET252. In this embodiment, the electrode140is electrically coupled to the second blocking diode272of the bias voltage source152.

FIG.3is a schematic diagram of a pulsed signal source device300. The pulsed signal source device300includes a substrate support (e.g., electrostatic chuck)305made of a dielectric material and configured to support a substrate303on a substrate support surface305A, a support base307, an insulator plate, a ground plate312, and a support shaft338. The pulsed signal source device300further includes an electrode304disposed in the substrate support305and configured to be capacitively coupled to a plasma through a dielectric layer305B and a bias voltage source301configured to supply a pulsed biasing voltage to the electrode304. The bias voltage source301includes a DC voltage source310, a first capacitor320connected in series with the DC voltage source310, a first diode330connected with the first capacitor320, a first resistor340connected to the positive terminal of the DC voltage source310at one end, a first MOSFET350connected in series to the first resistor340, a first gate voltage source360connected to a gate terminal of the first MOSFET350, and a first blocking diode370connected to a source terminal351of the first MOSFET350. The bias voltage source301further includes a second capacitor322connected in series between the first diode330and a second diode332that is connected in series between the second capacitor322and ground328, a second resistor342connected at the common connection point between the first diode330and the second capacitor322, a second MOSFET352connected in series to the second resistor342, a second gate voltage source362connected to a gate terminal of the second MOSFET352, and a second blocking diode372connected to a source terminal353of the second MOSFET352. Further, a third capacitor324is connected in series between the second diode332and ground328, and a third resistor344is connected at the common connection point between the second diode332and the third capacitor324. Additionally, a third MOSFET354is connected in series to the third resistor344, a third gate voltage source364connected to a gate terminal of the third MOSFET354, and a third blocking diode374connected to a source terminal of the third MOSFET354. The memory334, the CPU333, and the support circuits335of the system controller326(which is similar to the system controller126) may alter the pulse width, duration, and amplitude according to the present disclosure as further described below.

FIG.4illustrates a pulsed voltage-biasing scheme using a waveform400, according to certain embodiments of the present disclosure. As shown, waveform400comprises a plurality of pulses410. Each of the plurality of pulses410comprises a total pulse width412. Within each of the plurality of pulses410, a first MOSFET, a second MOSFET, and a third MOSFET generate a first signal420having a first pulse width421, second signal422having a second pulse width423, and a third signal424having a third pulse width425. Each signal also includes an OFF-time (Toff) where each signal is in an OFF state, such as a first Toff430for the first signal420, a second Toff432for the second signal422, and a third Toff434for the third signal434. The first Toff430may be the duration between pulses or before the beginning of an initial pulse where at least the first MOSFET is gated OFF and, typically, where all MOSFETs are gated OFF. Additionally, each signal has its respective amplitude, such as a first amplitude440, a second amplitude442, and a third amplitude444.

InFIG.4, each of the MOSFETs are gated ON simultaneously and provide the same voltage, resulting in the first signal420, the second signal422, and the third signal424having the same amplitude (e.g.,440,442, and444are equal), Toff(e.g.,430,432, and434are equal), and pulse width (e.g.,421,423and425are equal).

FIG.5illustrates a pulsed voltage-biasing scheme using a waveform500, according to certain embodiments of the present disclosure. As shown, waveform500comprises a plurality of pulses510. The plurality of pulses510comprises a total pulse width512. Within the plurality of pulses510, a first MOSFET, a second MOSFET, and a third MOSFET generate a first signal520having a first pulse width521, second signal522having a second pulse width523, and a third signal524having a third pulse width525. Each signal also includes a Toff, such as a first Toff530for the first signal520, a second Toff532for the second signal522, and a third Toff534for the third signal534. Additionally, each signal has its respective amplitude, such as a first amplitude540, a second amplitude542, and a third amplitude544.

InFIG.5, each of the MOSFETs are gated ON then OFF sequentially, but each MOSFET provides the same voltage at the same pulse width. This results in the first signal520, the second signal522, and the third signal524having the same amplitude (e.g.,540,542, and544are equal) and pulse width (e.g.,521,523and525are equal), but each Toffis progressively greater (e.g.,534is greater than532, and532is greater than530). Each sequential Toffis also greater than the previous pulse width. For example, second Toff532is greater than the sum of first Toff530and the first pulse width521. Further, the third Toff534is greater than the sum of the first Toff530, the first pulse width521, the second Toff532, and the second pulse width523.

FIG.6Aillustrates a pulsed voltage-biasing scheme using a waveform600, according to certain embodiments of the present disclosure. As shown, waveform600comprises a plurality of pulses610. The plurality of pulses610comprises a total pulse width612. Within the plurality of pulses610, a first MOSFET, a second MOSFET, and a third MOSFET generate a first signal620having a first pulse width621, second signal622having a second pulse width623, and a third signal624having a third pulse width625. Each signal also includes a Toff, such as a first Toff630for the first signal620, a second Toff632for the second signal622, and a third Toff634for the third signal634. Additionally, each signal has its respective amplitude, such as a first amplitude640, a second amplitude642, and a third amplitude644.

InFIG.6A, each of the MOSFETs are gated ON then OFF sequentially and each MOSFET provides a different voltage, but at the same pulse width. This results in the first signal620, the second signal622, and the third signal624having the same pulse width (e.g.,621,623and625are equal) but each Toffis progressively greater (e.g.,634is greater than632, and632is greater than630) and, in this embodiment, each amplitude is progressively decreased (e.g.,640is greater than642, and642is greater than644). Each sequential Toffis also greater than the previous pulse width. For example, second Toff632is greater than the sum of first Toff630and the first pulse width621. Further, the third Toff634is greater than the sum of the first Toff630, the first pulse width621, the second Toff632, and the second pulse width623.

FIG.6Billustrates a pulsed voltage-biasing scheme using a waveform650, according to certain embodiments of the present disclosure. As shown, waveform650comprises a plurality of pulses660. The plurality of pulses660comprises a total pulse width662. Within the plurality of pulses660, a first MOSFET, a second MOSFET, and a third MOSFET generate a first signal670having a first pulse width671, second signal672having a second pulse width673, and a third signal674having a third pulse width675. Each signal also includes a Toff, such as a first Toff680for the first signal670, a second Toff682for the second signal672, and a third Toff684for the third signal684. Additionally, each signal has its respective amplitude, such as a first amplitude690, a second amplitude692, and a third amplitude694.

InFIG.6B, each of the MOSFETs are gated ON then OFF sequentially but each MOSFET provides a different voltage and at a different pulse width. This results in the first signal670, the second signal672, and the third signal674having different pulse widths (e.g.,671,673and675are not equal), each Toffis progressively greater (e.g.,684is greater than682, and682is greater than680), and, in this embodiment, each amplitude is progressively decreased (e.g.,690is greater than692, and692is greater than694). Each sequential Toffis also greater than the previous pulse width. For example, second Toff682is greater than the sum of first Toff680and the first pulse width671. Further, the third Toff684is greater than the sum of the first Toff680, the first pulse width671, the second Toff682, and the second pulse width673.

FIG.7illustrates a pulsed voltage-biasing scheme using a waveform700, according to certain embodiments of the present disclosure. As shown, waveform700comprises a plurality of pulses710. Each of the plurality of pulses710comprises a total pulse width712. Within the plurality of pulses710, a first MOSFET, a second MOSFET, and a third MOSFET generate a first signal720having a first pulse width721that may be equal to the total pulse width712(e.g., the first MOSFET is gated ON for the duration of the pulse), second signal722having a second pulse width723, and a third signal724having a third pulse width725. As shown, the second pulse width723and the third pulse width725may be equal. Each signal also includes a Toff, such as a first Toff730for the first signal720, a second Toff732for the second signal722, and a third Toff734for the third signal724. Additionally, each signal has its respective amplitude, such as a first amplitude740, a second amplitude742, and a third amplitude744.

InFIG.7, the first MOSFET is gated ON before the second and third MOSFETs. As shown, the first MOSFET is gated ON at the beginning of the pulse. The second and third MOSFETs are gated ON simultaneously after the first MOSFET then gated OFF before the first MOSFET such that their entire pulse width723,725lies within the first pulse width721of the first signal720. In this embodiment, the first, second, and third amplitudes740,742,744produce an output signal726with an amplitude746equal to the sum of the first, second, and third amplitudes740,742,744while the second and third MOSFETs are gated ON. In this embodiment, the second and third pulse widths723,725overlap as a result of their respective Toff732,734being equal and greater than the first Toff730.

FIG.8Aillustrates a pulsed voltage-biasing scheme using a waveform800, according to certain embodiments of the present disclosure. As shown, waveform800comprises a plurality of pulses810. The plurality of pulses810comprises a total pulse width812. Within the plurality of pulses810, a first MOSFET, a second MOSFET, and a third MOSFET generate a first signal820having a first pulse width821, second signal822having a second pulse width823, and a third signal824having a third pulse width825. Each signal also includes a Toff, such as a first Toff830for the first signal820, a second Toff832for the second signal822, and a third Toff834for the third signal824. Additionally, each signal has its respective amplitude, such as a first amplitude840, a second amplitude842, and a third amplitude844.

InFIG.8A, each of the MOSFETs are gated ON sequentially then gated OFF simultaneously at the end of the pulse. As shown, the first signal820, the second signal822, and the third signal824have different pulse widths (e.g.,821,823and825are not equal). Each Toffis progressively greater (e.g.,834is greater than832, and832is greater than830), and, in this embodiment, output voltage amplitude (e.g., combination of840,842, and844) increases in a step-wise manner as the second and third MOSFETs are gated ON. For example, when the second MOSFET is gated ON after Toff832, the first signal820and the second signal822combine to create a first output voltage signal826. The first output voltage signal826has an amplitude843equal to the sum of the first amplitude840and the second amplitude842. Similarly, when the third MOSFET is gated ON, the combination of the first signal820, second signal822, and the third signal824creates a second output voltage signal828with an amplitude845equal to the sum of the first amplitude840, the second amplitude842, and the third amplitude844.

FIG.8Billustrates a pulsed voltage-biasing scheme using a waveform850, according to certain embodiments of the present disclosure. As shown, waveform850comprises a plurality of pulses860. The plurality of pulses860comprises a total pulse width862. Within the plurality of pulses860, a first MOSFET, a second MOSFET, and a third MOSFET generate a first signal870having a first pulse width871, second signal872having a second pulse width873, and a third signal874having a third pulse width875. Each signal also includes a Toff, such as a first Toff880for the first signal870, a second Toff882for the second signal872, and a third Toff884for the third signal884. Additionally, each signal has its respective amplitude, such as a first amplitude890, a second amplitude892, and a third amplitude894.

InFIG.8B, each of the MOSFETs are gated ON simultaneously then gated OFF sequentially. In this embodiment, the first signal870, the second signal872, and the third signal874have different pulse widths (e.g.,871,873and875are not equal), and, in this embodiment, the output voltage amplitude (e.g., combination of890,892, and894) is progressively decreased. For example, all three MOSFETs are gated on at the beginning of the pulse creating a first output voltage signal878by combining the first signal870, the second signal872, and the third signal874. The first output voltage signal has an amplitude895equal to the sum of the first amplitude890, the second amplitude892, and the third amplitude894. Because the first output voltage signal is a combination of all three signals870,872, and873, the pulse width of the first output voltage signal is equal to the shortest pulse width of the three signals (e.g., the third pulse width875). When the third MOSFET is gated OFF, a second output voltage signal876is created by the combination of the first signal870and the second signal874. The second output voltage signal has an amplitude893equal to the sum of the first amplitude890and the second amplitude892. Because the second output voltage876is a combination of the first signal870and the second signal872, the second output voltage876has a pulse width equal to the shortest pulse width between the first signal870and the second signal872(e.g., the second pulse width873).

FIG.9is a process flow diagram illustrating a method900for etching using a pulsed waveform. In operation910, a plasma101is generated in a chamber body124. In operation920, a pulsed DC voltage153is applied to the plasma101using a bias electrode104capacitively coupled to the plasma101through a dielectric layer105B.

Applying a pulsed DC voltage in operation920may include using a DC voltage source (e.g., DC voltage source210) connected to a first capacitor (e.g., first capacitor220) via its positive terminal and a first diode (e.g., first diode230), the positive terminal of the DC voltage source (e.g., DC voltage source210) further connected to a first resistor (e.g., first resistor240), first MOSFET (e.g., first MOSFET250), and first blocking diode (e.g., first blocking diode270). A second capacitor (e.g., second capacitor222) may be connected in series with between the first diode (e.g., first diode230) and ground (e.g., ground228). The DC voltage source (e.g., DC voltage source210) may also be coupled to a second diode (e.g., second diode232) connected in series between the second capacitor (e.g., second capacitor222) and ground (e.g., ground228). A second resistor (e.g., second resistor242) may be connected at the common point of the first diode (e.g., first diode230) and the second capacitor (e.g., second capacitor222). A second MOSFET (e.g., second MOSFET252) may be connected in series to the second resistor (e.g., second resistor242), a second gate voltage source (e.g., second gate voltage source262) connected to a gate terminal of the second MOSFET (e.g., second MOSFET252), and a second blocking diode (e.g., second blocking diode272) connected to a source terminal (e.g.,253) of the second MOSFET (e.g., second MOSFET252). Further, a third resistor (e.g., third resistor244) may be connected at the common point of the second diode (e.g., second diode232) and the third capacitor (e.g., third capacitor224) between the second diode (e.g., second diode232) and third capacitor (third capacitor224). A third MOSFET (e.g., third MOSFET254), a third gate voltage source (e.g., third gate voltage source264), and third blocking diode (e.g., third blocking diode274) may also be connected in series with the third resistor (e.g., third resistor244), where the cathode of the third blocking diode (e.g., third blocking diode274) is connected to the bias electrode (e.g., bias electrode104). The full supply voltage will be applied to the load when all the MOSFETs are gated ON at the same time and the widths of the gating signals are identical.

In operation920, applying a pulsed DC voltage source (e.g., DC voltage source210) may further include switching the first MOSFET (e.g., first MOSFET250) ON for a first duration (e.g., first duration620), switching the second MOSFET (e.g., second MOSFET252) ON for a second duration (e.g., second duration622), and switching the third MOSFET (e.g., third MOSFET254) for a third duration (e.g., third duration624). In some embodiments, the first duration (e.g., first duration420), second duration (e.g., second duration622), the third duration (e.g., third duration624), or a combination thereof may overlap. Alternatively, the first duration (e.g., first duration620), second duration (e.g., second duration422), and the third duration (e.g., third duration624) may not overlap. In operation920, the first gate voltage source (e.g., first gate voltage source260) may provide a first Toff(e.g., first Toff630), the second gate voltage source (e.g., second gate voltage source262) may provide a second Toff(e.g., second Toff632), and the third gate voltage source (e.g., third gate voltage source264) may provide a third Toff(e.g., third Toff634). In operation920, the first MOSFET (e.g., first MOSFET250) receives a first gating signal from the first gate voltage source (e.g., first gate voltage source260), where the first gating signal has a first pulse width (e.g., first pulse width620). Further, the second MOSFET (e.g., second MOSFET252) may receive a second gating signal from the second gate voltage source (e.g., second gate voltage source262), where the second gating signal has a second pulse width (e.g., second pulse width622). Further, the third MOSFET (e.g., third MOSFET254) may receive a third gating signal from the third gate voltage source (e.g., third gate voltage source264), where the third gating signal has a third pulse width (e.g., third pulse width624). In some embodiments, the first pulse width (e.g., first pulse width620), the second pulse width (e.g., second pulse width622), and the third pulse width (e.g., third pulse width624) are different. The memory134, the CPU133, and the support circuits135of the system controller126may implement method900in an embodiment of the present disclosure. In operation930, a substrate103is etched in the chamber body124using the pulsed DC voltage153applied to the plasma101.

The term “coupled” is used herein to refer to the direct or indirect coupling between two objects. For example, if object A physically touches object B and object B touches object C, the objects A and C may still be considered coupled to one another—even if objects A and C do not directly physically touch each other. For instance, a first object may be coupled to a second object even though the first object is never directly in physical contact with the second object.

While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.