Patent ID: 12261208

DETAILED DESCRIPTION

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings Like numeral references refer to like elements, and their repetitive descriptions may be omitted.

FIG.1is a plan layout diagram illustrating some elements of an integrated circuit device100according to embodiments.FIG.2Ais a cross-sectional view illustrating some elements of a cross-sectional surface taken along line X1-X1′ ofFIG.1,FIG.2Bis a cross-sectional view illustrating some elements of a cross-sectional surface taken along line X2-X2′ ofFIG.1,FIG.2Cis a cross-sectional view illustrating some elements of a cross-sectional surface taken along line Y1-Y1′ ofFIG.1, andFIG.2Dis a cross-sectional view illustrating some elements of a cross-sectional surface taken along line Y2-Y2′ ofFIG.1.

Referring toFIGS.1and2A to2D, the integrated circuit device100may include a substrate102, including a first device region RX1and a second device region RX2, and a plurality of fin-type active regions FA protruding from the first device region RX1and the second device region RX2of the substrate102. The plurality of fin-type active regions FA may extend in parallel in a first horizontal direction (an X direction).

The substrate102may include a semiconductor, such as silicon (Si) or germanium (Ge), or a compound semiconductor such as SiGe, SiC, GaAs, InAs, InGaAs, or InP. The terms “SiGe”, “SiC”, “GaAs”, “InAs”, “InGaAs”, and “InP” used herein may each denote a material including elements included in a corresponding term and may not be a chemical formula representing a stoichiometric relationship. The substrate102may include a conductive region (for example, an impurity-doped well) or an impurity-doped structure.

An isolation layer112covering both sidewalls of each of the plurality of fin-type active regions FA may be disposed on the substrate102. An inter-device isolation region DTA defining the first device region RX1and the second device region RX2may be provided by a deep trench DT. The deep trench DT may be filled with an inter-device isolation layer114. The isolation layer112and the inter-device isolation layer114may each include oxide, nitride, or a combination thereof. In the first device region RX1and the second device region RX2, the plurality of fin-type active regions FA may protrude in a fin shape to a portion on the isolation layer112.

InFIG.1, an example in which two fin-type active regions FA are included in each of the first device region RX1and the second device region RX2is illustrated, but the inventive concept is not limited to the illustration ofFIG.1. One or more fin-type active regions FA may be disposed in each of the first device region RX1and the second device region RX2.

A gate line160may extend long in a second horizontal direction (a Y direction) intersecting with a first horizontal direction (an X direction) in the plurality of fin-type active regions FA. A plurality of nanosheet stacks NSS may be disposed on a fin top surface FT of each of the plurality of fin-type active regions FA in regions where the plurality of fin-type active regions FA intersect with the gate line160. Each of the plurality of nanosheet stacks NSS may face the fin top surface FT at a position apart from a corresponding fin-type active region FA in a vertical direction (a Z direction). The term “nanosheet” used herein may denote a conductive structure including a cross-sectional surface substantially vertical to a direction in which a current flows. The nanosheet has to be understood as including a nanowire.

Each of the plurality of nanosheet stacks NSS may include a plurality of nanosheets N1to N3which overlap one another in the vertical direction (the Z direction) on the fin top surface FT of a corresponding fin-type active region FA. The plurality of nanosheets N1to N3may have different vertical distances (Z-direction distances) from the fin top surface FT. The plurality of nanosheets N1to N3may include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3, which are sequentially stacked on the fin top surface FT of the fin-type active region FA.

In the present embodiment, an example in which one nanosheet stack NSS and one gate line160are formed on each of the plurality of fin-type active regions FA is illustrated. However, the number of nanosheet stacks NSS and gate lines160disposed on one fin-type active region FA is not limited thereto. For example, a plurality of nanosheet stacks NSS and gate lines160may be disposed on one fin-type active region FA.

The number of nanosheets included in a nanosheet stack NSS on a fin-type active region FA in the first device region RX1may be the same as the number of nanosheets N1to N3included in a nanosheet stack NSS on a fin-type active region FA in the second device region RX2. In the present embodiment, an example in which each of the plurality of nanosheet stacks NSS includes three nanosheets N1to N3is illustrated, but in the inventive concept, the number of nanosheets configuring each nanosheet stack NSS is not limited thereto. For example, each of the plurality of nanosheet stacks NSS may include or more nanosheets. Each of the plurality of nanosheets N1to N3may include a channel region. For example, each of the plurality of nanosheets N1to N3may have a thickness which is selected within a range of about 4 nm to about 6 nm, but is not limited thereto. Here, a thickness of each of the plurality of nanosheets N1to N3may denote a size in the vertical direction (the Z direction). In embodiments, the plurality of nanosheets N1to N3may have substantially the same thickness in the vertical direction (the Z direction). In other embodiments, at least some of the plurality of nanosheets N1to N3may have different thicknesses in the vertical direction (the Z direction).

As illustrated inFIGS.2A and2B, each of the plurality of nanosheets N1to N3may have the same thickness in the first horizontal direction (the X direction). In other embodiments, at least some of the plurality of nanosheets N1to N3may have different thicknesses in the first horizontal direction (the X direction). For example, a length of each of the first nanosheet N1and the second nanosheet N2, which are relatively close to the fin top surface FT, of the plurality of nanosheets N1to N3in the first horizontal direction (the X direction) may be less than that of the third nanosheet N3farthest from the fin top surface FT. In this case, an effective channel length of a channel formed in each of the first and second nanosheets N1and N2relatively close to the fin top surface FT may be less than an effective channel length of a channel formed in the third nanosheet N3, and thus, based on the same operating voltage, the amount of current flowing through the first and second nanosheets N1and N2may increase.

A plurality of first recesses R1may be formed in a top of a fin-type active region FA in the first device region RX1, and a plurality of second recesses R2may be formed in a top of a fin-type active region FA in the second device region RX2. InFIGS.2A and2B, an example is illustrated in which a level of a lowermost surface of each of the plurality of first recesses R1and the plurality of second recesses R2is lower than that of the fin top surface FT of the fin-type active region FA, but the inventive concept is not limited thereto. A level of the lowermost surface of each of the plurality of first recesses R1and the plurality of second recesses R2may be approximately equal or similar to that of the fin top surface FT of the fin-type active region FA.

A plurality of first source/drain regions SD1may be formed on the plurality of first recesses R1in the first device region RX1, and a plurality of second source/drain regions SD2may be formed on the plurality of second recesses R2in the first device region RX2.

The gate line160may extend long in the second horizontal direction (the Y direction) on the fin-type active region FA and the isolation layer112in the first device region RX1and the second device region RX2. The gate line160may cover the nanosheet stack NSS and may surround each of the plurality of nanosheets N1to N3, on the fin-type active region FA. A plurality of nanosheet transistors TR may be formed at a plurality of portions, where the plurality of fin-type active regions FA intersect with the gate line160, on the substrate102.

The gate line160may include a main gate portion160M and a plurality of sub gate portions160S. The main gate portion160M may cover a top surface of the nanosheet stack NSS and may extend long in the second horizontal direction (the Y direction). The plurality of sub gate portions160S may be connected to the main gate portion160M as one body and may each be disposed between two adjacent nanosheets of the plurality of nanosheets N1to N3and between the fin-type active region FA and the first nanosheet N1.

The main gate portion160M of the gate line160may include a connection protrusion portion160P, which includes a protrusion top surface160U at a first vertical level LV1on the substrate102, and a recess top surface160L which extends long in the second horizontal direction (the Y direction) from the connection protrusion portion160P at a second vertical level LV2, which is lower than the first vertical level LV1. In embodiments, a height difference between the first vertical level LV1and the second vertical level LV2may be about 2 nm to about 20 nm, but is not limited thereto.

The main gate portion160M may extend long in the second horizontal direction (the Y direction) in the first device region RX1, the inter-device isolation region DTA, and the second device region RX2. The recess top surface160L of the main gate portion160M in the vertical direction (the Z direction) may be higher than an uppermost surface of the nanosheet stack NSS, namely, an uppermost surface of the third nanosheet N3. In the vertical direction (the Z direction), a thickness of each of the plurality of sub gate portions160S may be less than that of the main gate portion160M.

The recess top surface160L of the main gate portion160M may overlap the plurality of fin-type active regions FA and the plurality of nanosheet stacks NSS in the vertical direction (the Z direction) in the first device region RX1and the second device region RX2. The connection protrusion portion160P of the main gate portion160M may overlap the inter-device isolation layer114in the vertical direction (the Z direction) in the inter-device isolation region DTA. The connection protrusion portion160P of the main gate portion160M may include a portion which overlaps the plurality of fin-type active regions FA and the plurality of nanosheet stacks NSS in the vertical direction (the Z direction) in the first device region RX1and the second device region RX2.

The gate line160may include metal, metal nitride, metal carbide, or a combination thereof. The metal may be selected from among titanium (Ti), tungsten (W), ruthenium (Ru), niobium (Nb), molybdenum (Mo), hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), and palladium (Pd). The metal nitride may be selected from among TiN and TaN. The metal carbide may include TiAlC.

A gate dielectric layer152may be disposed between the nanosheet stack NSS and the gate line160. The gate dielectric layer152may include a portion, which covers a surface of each of the plurality of nanosheets N1to N3, and a portion which covers sidewalls of the main gate portion160M. In embodiments, the gate dielectric layer152may include a stack structure of an interface layer and a high-k dielectric layer. The interface layer may include a low-k dielectric material layer having a dielectric constant of about 9 or less, and for example, may include silicon oxide, silicon oxynitride, or a combination thereof. In embodiments, the interface layer may be omitted. The high-k dielectric layer may include a material which has a greater dielectric constant than silicon oxide. For example, the high-k dielectric layer may have a dielectric constant of about 10 to about 25. The high-k dielectric layer may include hafnium oxide, but is not limited thereto.

In embodiments, the plurality of nanosheets N1to N3may include a semiconductor layer including the same element. For example, each of the plurality of nanosheets N1to N3may include a Si layer. The plurality of nanosheets N1to N3in the first device region RX1may be doped with the same conductive dopant as that of the first source/drain region SD1. The plurality of nanosheets N1to N3in the second device region RX2may be doped with the same conductive dopant as that of the second source/drain region SD2. For example, the plurality of nanosheets N1to N3in the first device region RX1may include a Si layer doped with an n-type dopant, and the plurality of nanosheets N1to N3in the second device region RX2may include a Si layer doped with a p-type dopant.

Both sidewalls of each of the gate line160may be covered by a plurality of outer insulation spacers118, on the fin-type active region FA, the isolation layer112, and the inter-device isolation layer114. The plurality of outer insulation spacers118may cover both sidewalls of the main gate portion160M, on top surfaces of the plurality of nanosheet stacks NSS. Each of the plurality of outer insulation spacers118may be apart from the gate line160with the gate dielectric layer152therebetween. Each of the plurality of outer insulation spacers118may include silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof. The terms “SiCN”, “SiBN”, “SiON”, “SiOCN”, “SiBCN”, and “SiOC” used herein may each denote a material including elements included in a corresponding term and may not be a chemical formula representing a stoichiometric relationship.

As illustrated inFIG.2A, a plurality of inner insulation spacers120may be disposed between two adjacent nanosheets of the plurality of nanosheets N1to N3in the first device region RX1and may be disposed between the plurality of sub gate portions160S and the first source/drain region SD1, and between the fin-type active region FA and the first nanosheet N1. Both sidewalls of each of the plurality of sub gate portions160S in the first device region RX1may be covered by the inner insulation spacer120with the gate dielectric layer152therebetween. Each of the plurality of sub gate portions160S may be apart from the first source/drain region SD1with the gate dielectric layer152and the inner insulation spacer120therebetween. Each of the plurality of inner insulation spacers120may contact the first source/drain region SD1. At least some of the plurality of inner insulation spacers120may overlap the outer insulation spacer118in the vertical direction (the Z direction). The inner insulation spacers120may include silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof. The inner insulation spacer120may further include an air gap. In embodiments, the inner insulation spacer120may include the same material as that of the outer insulation spacer118. In other embodiments, the outer insulation spacer118and the inner insulation spacer120may include different materials.

Each of the plurality of first source/drain regions SD1in the first device region RX1may face the plurality of sub gate portions160S with the inner insulation spacer120therebetween in the first horizontal direction (the X direction). The plurality of first source/drain regions SD1may not include a portion which contacts the gate dielectric layer152.

As illustrated inFIG.2B, both sidewalls of each of the plurality of sub gate portions160S may be apart from the second source/drain region SD2with the gate dielectric layer152therebetween, between two adjacent nanosheets of the plurality of nanosheets N1to N3in the second device region RX2and between the fin-type active region FA and the first nanosheet N1. The gate dielectric layer152may include a portion which contacts the second source/drain region SD2. Each of the plurality of second source/drain regions SD2may face the nanosheet stack NSS and the plurality of sub gate portions160S in the first horizontal direction (the X direction).

In embodiments, the gate line160may have a structure in which a metal nitride layer, a metal layer, a conductive capping layer, and a gap-fill metal layer are sequentially stacked. The metal nitride layer and the metal layer may include at least one metal selected from among Ti, Ta, W, Ru, Nb, Mo, and Hf. The gap-fill metal layer may include a W layer or an Al layer. The gate lines160may each include a work function metal containing layer. The work function metal containing layer may include at least one metal selected from among Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, and Pd. In some embodiments, each of the gate lines160may include a stack structure of TiAlC/TiN/W, a stack structure of TiN/TaN/TiAlC/TiN/W, or a stack structure of TiN/TaN/TiN/TiAlC/TiN/W, but is not limited thereto.

As illustrated inFIGS.2A to2C, a top surface of each of the gate line160and the gate dielectric layer152may be covered by a capping insulation pattern164. The capping insulation pattern164may cover the protrusion top surface160U and the recess top surface160L of the main gate portion160M. The capping insulation pattern164may include silicon nitride.

In the first device region RX1, the main gate portion160M of the gate line160may be apart from the first source/drain region SD1with the outer insulation spacer118therebetween. In the second device region RX2, the main gate portion160M of the gate line160may be apart from the second source/drain region SD2with the outer insulation spacer118therebetween.

In embodiments, the first device region RX1may be an NMOS transistor region, and the second device region RX2may be a PMOS transistor region. In this case, the plurality of first source/drain regions SD1in the first device region RX1may include a Si layer doped with an n-type dopant, and the plurality of second source/drain regions SD2in the second device region RX2may include a SiGe layer doped with a p-type dopant. The n-type dopant may be selected from among phosphorus (P), arsenic (As), and antimony (Sb). The p-type dopant may be selected from among boron (B) and gallium (Ga).

As illustrated inFIG.2D, the plurality of first source/drain regions SD1in the first device region RX1and the plurality of second source/drain regions SD2in the second device region RX2may have different shapes and sizes. However, the inventive concept is not limited thereto, and the plurality of first and second source/drain regions SD1and SD2having various shapes and sizes may be formed in the first device region RX1and the second device region RX2.

The plurality of first and second source/drain regions SD1and SD2may be covered by an insulation liner142. The insulation liner142may conformally cover a surface of each of the plurality of first and second source/drain regions SD1and SD2and the outer insulation spacer118. The insulation liner142may include SiN, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, SiO2, or a combination thereof.

An inter-gate insulation layer144and an insulation structure190may be formed on the insulation liner142. The inter-gate insulation layer144may include silicon nitride, silicon oxide, SiON, SiOCN, or a combination thereof. The insulation structure190may include an etch stop layer190A and an inter-layer insulation layer190B, which are sequentially stacked on the inter-gate insulation layer144. The etch stop layer190A may include silicon carbide (SiC), SiN, nitrogen-doped silicon carbide (SiC:N), SiOC, AN, AlON, AlO, AlOC, or a combination thereof. The inter-layer insulation layer190B may include an oxide layer, a nitride layer, an ultra low-k (ULK) layer having an ultra low dielectric constant K of about 2.2 to about 2.4, or a combination thereof. For example, the inter-layer insulation layer190B may include a tetraethylorthosilicate (TEOS) layer, a high density plasma (HDP) layer, a boro-phospho-silicate glass (BPSG) layer, a flowable chemical vapor deposition (FCVD) oxide layer, a SiON layer, a SiN layer, a SiOC layer, a SiCOH layer, or a combination thereof.

A plurality of source/drain contacts174and a plurality of source/drain via contacts192may be formed on the plurality of first and second source/drain regions SD1and SD2. The plurality of first and second source/drain regions SD1and SD2may be connected to an upper conductive line through the plurality of source/drain contacts174and the plurality of source/drain via contacts192. The plurality of source/drain contacts174may include an uppermost surface at a third vertical level LV3, which is higher than the first vertical level LV1.

A metal silicide layer172may be formed between the first and second source/drain regions SD1and SD2and the source/drain contact174. In embodiments, the metal silicide layer172may include Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. For example, the metal silicide layer172may include titanium silicide. The plurality of source/drain contacts174may pass through the inter-gate insulation layer144and the insulation liner142in the vertical direction (the Z direction) and may contact the metal silicide layer172. The plurality of source/drain via contacts192may pass through the insulation structure190in the vertical direction (the Z direction) and may contact the source/drain contact174.

As illustrated inFIG.2C, a gate contact184and a gate via contact194may be formed on the gate line160. The gate line160may be connected to an upper conductive line through the gate contact184and the gate via contact194. The gate contact184and the gate via contact194may be configured to be connected to the connection protrusion portion160P of the main gate portion160M in the inter-device isolation region DTA. The gate contact184may pass through the capping insulation pattern164in the vertical direction (the Z direction) and may contact a top surface of the connection protrusion portion160P of the gate line160. The gate via contact194may pass through the insulation structure190in the vertical direction (the Z direction) and may contact a top surface of the gate contact184. A vertical level of an uppermost surface of the gate contact184may be the same as or similar to that of an uppermost surface of each of the plurality of source/drain contacts174.

A stack structure of the gate contact184and the gate via contact194each disposed on the gate line160and a stack structure of the source/drain contact174and the source/drain via contact192each disposed in at least one source/drain region of the first and second source/drain regions SD1and SD2disposed adjacent to the gate line160may be arranged to be staggered to not be disposed on a straight line in the first horizontal direction (the X direction).

InFIGS.1and2C, in the integrated circuit device100, an example is illustrated in which the connection protrusion portion160P of the gate line160aand the gate contact184and the gate via contact each connected to the gate line160through the connection protrusion portion160P are disposed in the inter-device isolation region DTA, but the inventive concept is not limited thereto. For example, the connection protrusion portion160P of the gate line160, the gate contact184, and the gate via contact194may be disposed in either one or both of the first device region RX1and the second device region RX2.

The plurality of source/drain contacts174may each include a conductive barrier layer174A and a metal plug174B. The plurality of source/drain via contacts192may each include a conductive barrier layer192A and a metal plug192B. The gate contact184may include a conductive barrier layer184A and a metal plug184B. The gate via contact194may include a conductive barrier layer194A and a metal plug194B. The conductive barrier layers174A,184A,192A, and194A may each include Ti, Ta, TiN, TaN, or a combination thereof. The metal plugs174B,184B,192B, and194B may each include W, Co, Cu, Ru, Mn, or a combination thereof. However, materials of the conductive barrier layers174A,184A,192A, and194A and the metal plugs174B,184B,192B, and194B are not limited thereto.

In embodiments, a sidewall of each of the plurality of source/drain contacts174and gate contacts184may be surrounded by a contact insulation spacer. The contact insulation spacer may include SiCN, SiCON, silicon nitride (SiN), or a combination thereof, but is not limited thereto.

As illustrated inFIGS.2A,2B, and2D, the plurality of source/drain contacts174may have different heights on the basis of a position. Each of the plurality of source/drain contacts174may include a first segment S1and a second segment S2, which have different heights and are connected to each other as one body in the vertical direction (the Z direction).

In the source/drain contact174, a height of the first segment S1in the vertical direction (the Z direction) may be greater than that of the second segment S2in the vertical direction (the Z direction). In embodiments, in the vertical direction (the Z direction), a height of an uppermost surface of the first segment S1may be greater than that of an uppermost surface of the gate line160. A height of an uppermost surface of the second segment S2may be the same as or different from that of the uppermost surface of the gate line160. For example, a height of the uppermost surface of the second segment S2may be lower or higher than that of the uppermost surface of the gate line160. Each of the plurality of source/drain via contacts192may contact a top surface of the first segment S1of the source/drain contact174.

A top surface of the second segment S2of the source/drain contact174may be covered by a buried insulation layer176. The buried insulation layer176may fill an upper space of the second segment S2of the source/drain contact174. A top surface of the buried insulation layer176and a top surface of the capping insulation pattern164may be covered by the insulation structure190. The buried insulation layer176may include silicon oxide, SiOC, SiOCN, SiON, SiCN, SiN, or a combination thereof, but is not limited thereto.

In the integrated circuit device100illustrated inFIGS.1and2A to2D, the connection protrusion portion160P including the protrusion top surface160U at the first vertical level LV1, which is relatively high, may be included in a portion, connected to the gate contact184, of the gate line160, and another portion, which is near the connection protrusion portion160P, of the gate line160may include the recess top surface160L at the second vertical level LV2, which is lower than the first vertical level LV1. Therefore, in the integrated circuit device100, an undesired parasitic capacitance between conductive regions (i.e., a gate and a source/drain contact) adjacent to each other may be reduced. Further, a parasitic capacitance occurring due to different nodes adjacent to each other may be reduced. Also, a height difference in the vertical direction (the Z direction) between the protrusion top surface160U at the first vertical level LV1and the recess top surface160L at the second vertical level LV2may be variously adjusted, and thus, a work function for transistors including the gate line160may be easily controlled. Therefore, by using the gate line160including the protrusion top surface160U and the recess top surface160L, which are at various vertical levels, and have various sizes on the basis of a desired condition, the reliability of an integrated circuit device may be enhanced by a relatively simple method.

FIG.3is a cross-sectional view for describing an integrated circuit device100A according to other embodiments. InFIG.3, some elements of a portion corresponding to a cross-sectional surface taken along line Y1-Y1′ ofFIG.1is illustrated.

Referring toFIG.3, the integrated circuit device100A may have substantially the same configuration as that of the integrated circuit device100described above with reference toFIGS.1and2A to2D. The integrated circuit device100A may include a gate line160A instead of the gate line160of the integrated circuit device100.

The gate line160A may have substantially the same configuration as that of the gate line160described above with reference toFIGS.2A to2C. A main gate portion160AM of the gate line160A may include a connection protrusion portion160AP, which includes a protrusion top surface160AU extending long in a second horizontal direction (a Y direction) at a first vertical level LV1on a substrate102, and a recess top surface160AL, which extends long in the second horizontal direction (the Y direction) from the connection protrusion portion160AP at a second vertical level LV2, which is lower than the first vertical level LV1. The connection protrusion portion160AP of the main gate portion160AM may be disposed in only the first device region RX1among the first device region RX1and the second device region RX2and may not be disposed in the second device region RX2. The recess top surface160AL of the main gate portion160AM may be disposed in only the second device region RX2among the first device region RX1and the second device region RX2and may not be disposed in the first device region RX1. A stepped portion ST2between the connection protrusion portion160AP and the recess top surface160AL of the main gate portion160AM may overlap an inter-device isolation layer114in a vertical direction (a Z direction) in an inter-device isolation region DTA.

The connection protrusion portion160AP of the main gate portion160AM may overlap a plurality of fin-type active regions FA and a plurality of nanosheet stacks NSS in the vertical direction (the Z direction) in the first device region RX1. The recess top surface160AL of the main gate portion160AM may overlap a plurality of fin-type active regions FA and a plurality of nanosheet stacks NSS in the vertical direction (the Z direction) in the second device region RX2.

FIGS.4A and4Bare cross-sectional views for describing an integrated circuit device100B according to other embodiments. InFIG.4A, some elements of a portion corresponding to a cross-sectional surface taken along line X1-X1′ ofFIG.1is illustrated. InFIG.4B, some elements of a portion corresponding to a cross-sectional surface taken along line Y1-Y1′ ofFIG.1is illustrated.

Referring toFIGS.4A and4B, the integrated circuit device100B may have substantially the same configuration as that of the integrated circuit device100A described above with reference toFIG.3. In the integrated circuit device100B, a stack structure of a gate contact184and a gate via contact194each connected to a gate line160A may be disposed in a first device region RX1. The gate contact184may contact a protrusion top surface160AU of a connection protrusion portion160AP included in a main gate portion160AM in the first device region RX1. The stack structure of the gate contact184and the gate via contact194each connected to the gate line160A may overlap a plurality of fin-type active regions FA and a plurality of nanosheet stacks NSS in a vertical direction (a Z direction) in the first device region RX1.

As illustrated inFIG.4A, the stack structure of the gate contact184and the gate via contact194each disposed on the gate line160A and a stack structure of a source/drain contact174and a source/drain via contact192each disposed on a first source/drain region SD1disposed adjacent to the gate line160A may be disposed on a straight line in a first horizontal direction (an X direction).

FIG.5is a cross-sectional view for describing an integrated circuit device100C according to other embodiments. InFIG.5, some elements of a portion corresponding to a cross-sectional surface taken along line Y1-Y1′ ofFIG.1is illustrated.

Referring toFIG.5, the integrated circuit device100C may have substantially the same configuration as that of the integrated circuit device100described above with reference toFIGS.1and2A to2D. The integrated circuit device100C may include a gate line160C instead of the gate line160of the integrated circuit device100.

The gate line160C may have substantially the same configuration as that of the gate line160described above with reference toFIGS.2A to2C. A main gate portion160CM of the gate line160C may include a connection protrusion portion160CP, which includes a protrusion top surface160CU extending long in a second horizontal direction (a Y direction) at a first vertical level LV1on a substrate102, and a recess top surface160CL, which extends long in the second horizontal direction (the Y direction) from the connection protrusion portion160CP at a second vertical level LV2, which is lower than the first vertical level LV1. The connection protrusion portion160CP of the main gate portion160CM may be disposed in only a second device region RX2among a first device region RX1and the second device region RX2and may not be disposed in the first device region RX1. The recess top surface160CL of the main gate portion160CM may be disposed in only the first device region RX1among the first device region RX1and the second device region RX2and may not be disposed in the second device region RX2. A stepped portion ST3between the connection protrusion portion160CP and the recess top surface160CL of the main gate portion160CM may overlap an inter-device isolation layer114in a vertical direction (a Z direction) in an inter-device isolation region DTA.

The connection protrusion portion160CP of the main gate portion160CM may overlap a plurality of fin-type active regions FA and a plurality of nanosheet stacks NSS in the vertical direction (the Z direction) in the second device region RX2. The recess top surface160CL of the main gate portion160CM may overlap a plurality of fin-type active regions FA and a plurality of nanosheet stacks NSS in the vertical direction (the Z direction) in the first device region RX1.

FIGS.6A and6Bare cross-sectional views for describing an integrated circuit device100D according to other embodiments. InFIG.6A, some elements of a portion corresponding to a cross-sectional surface taken along line X2-X2′ ofFIG.1is illustrated. InFIG.6B, some elements of a portion corresponding to a cross-sectional surface taken along line Y1-Y1′ ofFIG.1is illustrated.

Referring toFIGS.6A and6B, the integrated circuit device100D may have substantially the same configuration as that of the integrated circuit device100C described above with reference toFIG.5. In the integrated circuit device100D, a stack structure of a gate contact184and a gate via contact194each connected to a gate line160C may be disposed in a second device region RX2. The gate contact184may contact a connection protrusion portion160CP of a protrusion top surface160CU included in a main gate portion160CM in the second device region RX2. The stack structure of the gate contact184and the gate via contact194each connected to the gate line160C may overlap a plurality of fin-type active regions FA and a plurality of nanosheet stacks NSS in a vertical direction (a Z direction) in the second device region RX2.

As illustrated inFIG.6A, the stack structure of the gate contact184and the gate via contact194each disposed on the gate line160C and a stack structure of a source/drain contact174and a source/drain via contact192each disposed on a second source/drain region SD2disposed adjacent to the gate line160C may be disposed on a straight line in a first horizontal direction (an X direction).

FIG.7is a cross-sectional view for describing an integrated circuit device100E according to other embodiments. InFIG.7, some elements of a portion corresponding to a cross-sectional surface taken along line X2-X2′ ofFIG.1is illustrated.

Referring toFIG.7, the integrated circuit device100E may have substantially the same configuration as that of the integrated circuit device100D described above with reference toFIGS.6A and6B. The integrated circuit device100E may include a source/drain contact174E instead of the source/drain contact174of the integrated circuit device100D.

The source/drain contact174E may have substantially the same configuration as that of the source/drain contact174described above with reference toFIGS.2A to2D. The source/drain contact174E may not include a second segment S2of the source/drain contact174. A height of a top surface of the source/drain contact174E may be approximately constant. The top surface of the source/drain contact174E may extend to be flat at a third vertical level LV3.

A stack structure of a gate contact184and a gate via contact194each disposed on a gate line160C and a pair of source/drain contacts174E disposed on a pair of second source/drain regions SD2disposed adjacent to the gate line160C at both sides of the gate line160C may be disposed on a straight line in a first horizontal direction (an X direction).

FIG.8is a cross-sectional view for describing an integrated circuit device200according to other embodiments. InFIG.8, some elements of a portion corresponding to a cross-sectional surface taken along line Y1-Y1′ ofFIG.1is illustrated.

Referring toFIG.8, the integrated circuit device200may have substantially the same configuration as that of the integrated circuit device100described above with reference toFIGS.1and2A to2D. The integrated circuit device200may include a gate line260instead of the gate line160of the integrated circuit device100.

The gate line260may have substantially the same configuration as that of the gate line160described above with reference toFIGS.2A to2C. A main gate portion260M of the gate line260may include a connection protrusion portion260P, which includes a protrusion top surface260U at a first vertical level LV1on a substrate102, and a recess top surface260L, which extends long in a second horizontal direction (a Y direction) from the connection protrusion portion260P at a second vertical level LV2, which is lower than the first vertical level LV1. In embodiments, a height difference between the first vertical level LV1and the second vertical level LV22may be about 2 nm to about 20 nm, but is not limited thereto.

The recess top surface260L of the main gate portion260M in a vertical direction (a Z direction) may be higher than an uppermost surface of a nanosheet stack NSS, namely, an uppermost surface of a third nanosheet N3. A vertical level of the recess top surface260L of the main gate portion260M may be the same as or similar to a vertical level of a top surface of a portion, covering an uppermost surface of the third nanosheet N3, of a gate dielectric layer152. A top surface of the gate dielectric layer152at the same vertical level as the recess top surface260L of the main gate portion260M may include an interface layer or a high-k dielectric layer configuring the gate dielectric layer152. Detailed descriptions of the interface layer and the high-k dielectric layer each configuring the gate dielectric layer152will be described below with reference toFIGS.2A to2C.

The recess top surface260L of the main gate portion260M may include a recess portion260R at a position overlapping a fin-type active region FA and a nanosheet stack NSS in a vertical direction (a Z direction) in a first device region RX1and a second device region RX2. The recess portion260R may be filled with the third nanosheet N3and a gate dielectric layer152covering a side surface, a bottom surface, and a top surface of the third nanosheet N3. In embodiments, the gate dielectric layer152filling the recess portion260R may contact a capping insulation pattern164at the second vertical level LV22, and the third nanosheet N3may be apart from the capping insulation pattern164with the gate dielectric layer152therebetween. A portion, contacting the capping insulation pattern164, of the gate dielectric layer152filling the recess portion260R may include the interface layer or the high-k dielectric layer configuring the gate dielectric layer152.

InFIG.8, a structure is illustrated in which the main gate portion260M of the gate line260includes the recess top surface260L which extends long in the second horizontal direction (the Y direction) at the same second vertical level LV22as a top level of the gate dielectric layer152covering an uppermost surface of the third nanosheet N3, but the inventive concept is not limited thereto. In other embodiments, the main gate portion260M of the gate line260may include a recess top surface which extends long in the second horizontal direction (the Y direction) at the same third vertical level LV23as the top level of the gate dielectric layer152covering an uppermost surface of the second nanosheet N2instead of the recess top surface260L. In this case, the third nanosheet N3illustrated inFIG.8may be omitted. In other embodiments, the main gate portion260M of the gate line260may include a recess top surface which extends long in the second horizontal direction (the Y direction) at the same fourth vertical level LV24as the top level of the gate dielectric layer152covering an uppermost surface of the first nanosheet N1instead of the recess top surface260L. In this case, the second and third nanosheets N2and N3illustrated inFIG.8may be omitted.

In the integrated circuit device200, regardless of a vertical level of the recess top surface260L included in the main gate portion260M of the gate line260, the number of nanosheets included in the nanosheet stack NSS in the first device region RX1may be the same as the number of nanosheets included in the nanosheet stack NSS in the second device region RX2.

FIG.9is a cross-sectional view for describing an integrated circuit device200A according to other embodiments. InFIG.9, some elements of a portion corresponding to a cross-sectional surface taken along line Y1-Y1′ ofFIG.1is illustrated.

Referring toFIG.9, the integrated circuit device200A may have substantially the same configuration as that of the integrated circuit device200described above with reference toFIG.8. The integrated circuit device200A may include a gate line260A instead of the gate line260of the integrated circuit device200.

The gate line260A may have substantially the same configuration as that of the gate line260described above with reference toFIG.8. A main gate portion260AM of the gate line260A may include a connection protrusion portion260AP, which includes a protrusion top surface260AU extending long in a second horizontal direction (a Y direction) at a first vertical level LV1on a substrate102, and a recess top surface260AL which extends long in the second horizontal direction (the Y direction) from the connection protrusion portion260AP at a third vertical level LV23, which is lower than the first vertical level LV1. The connection protrusion portion260AP of the main gate portion260AM may be disposed in only a first device region RX1among the first device region RX1and a second device region RX2and may not be disposed in the second device region RX2. The recess top surface260AL of the main gate portion260AM may be disposed in only the second device region RX2among the first device region RX1and the second device region RX2and may not be disposed in the first device region RX1. A stepped portion ST21between the connection protrusion portion260AP and the recess top surface260AL of the main gate portion260AM may overlap an inter-device isolation layer114in a vertical direction (a Z direction) in an inter-device isolation region DTA.

The third vertical level LV23of the recess top surface260AL of the main gate portion260AM may be lower than a vertical level of a top surface of a third nanosheet N3, which is a nanosheet of an uppermost layer among a plurality of nanosheets N1to N3included in a plurality of nanosheet stacks NSS in the first device region RX1.

The connection protrusion portion260AP of the main gate portion260AM may overlap a plurality of fin-type active regions FA and a plurality of nanosheet stacks NSS in the vertical direction (the Z direction) in the first device region RX1. The recess top surface260AL of the main gate portion260AM may overlap a plurality of fin-type active regions FA and a plurality of nanosheet stacks NSS in the vertical direction (the Z direction) in the second device region RX2. In the integrated circuit device200A, the number of nanosheets included in a nanosheet stack NSS in the second device region RX2may be less than the number of nanosheets included in a nanosheet stack NSS in the first device region RX1.

InFIG.9, for example, a structure is illustrated in which the main gate portion260AM of the gate line260A includes the recess top surface260AL extending long in the second horizontal direction (the Y direction) at the third vertical level LV23, which is the same as a top level of the gate dielectric layer152covering an uppermost surface of the second nanosheet N2, but the inventive concept is not limited thereto. In other embodiments, the main gate portion260AM of the gate line260A may include a recess top surface extending long in the second horizontal direction (the Y direction) at the second vertical level LV22or a recess top surface extending long in the second horizontal direction (the Y direction) at the fourth vertical level LV24, instead of the recess top surface260AL.

FIG.10is a cross-sectional view for describing an integrated circuit device200B according to other embodiments. InFIG.10, some elements of a portion corresponding to a cross-sectional surface taken along line Y1-Y1′ ofFIG.1is illustrated.

Referring toFIG.10, the integrated circuit device200B may have substantially the same configuration as that of the integrated circuit device200described above with reference toFIG.8. The integrated circuit device200B may include a gate line260B instead of the gate line260of the integrated circuit device200.

The gate line260B may have substantially the same configuration as that of the gate line260described above with reference toFIG.8. A main gate portion260BM of the gate line260B may include a connection protrusion portion260BP, which includes a protrusion top surface260BU extending long in a second horizontal direction (a Y direction) at a first vertical level LV1on a substrate102, and a recess top surface260BL, which extends long in the second horizontal direction (the Y direction) from the connection protrusion portion260BP at a third vertical level LV23, which is lower than the first vertical level LV1. The connection protrusion portion260BP of the main gate portion260BM may be disposed in only a second device region RX2among a first device region RX1and the second device region RX2and may not be disposed in the first device region RX1. The recess top surface260BL of the main gate portion260BM may be disposed in only the first device region RX1among the first device region RX1and the second device region RX2and may not be disposed in the second device region RX2. A stepped portion ST22between the connection protrusion portion260BP and the recess top surface260BL of the main gate portion260BM may overlap an inter-device isolation layer114in a vertical direction (a Z direction) in an inter-device isolation region DTA.

The third vertical level LV23of the recess top surface260BL of the main gate portion260BM may be lower than a vertical level of a top surface of a third nano sheet N3, which is a nanosheet of an uppermost layer among a plurality of nanosheets N1to N3included in a plurality of nanosheet stacks NSS in the second device region RX2.

The connection protrusion portion260BP of the main gate portion260BM may overlap a plurality of fin-type active regions FA and a plurality of nanosheet stacks NSS in the vertical direction (the Z direction) in the second device region RX2. The recess top surface260BL of the main gate portion260BM may overlap a plurality of fin-type active regions FA and a plurality of nanosheet stacks NSS in the vertical direction (the Z direction) in the first device region RX1. In the integrated circuit device200B, the number of nanosheets included in a nanosheet stack NSS in the first device region RX1may be less than the number of nanosheets included in a nanosheet stack NSS in the second device region RX2.

InFIG.10, for example, a structure is illustrated in which the main gate portion260BM of the gate line260B includes the recess top surface260BL extending long in the second horizontal direction (the Y direction) at the third vertical level LV23, which is the same as a top level of the gate dielectric layer152covering an uppermost surface of the second nanosheet N2, but the inventive concept is not limited thereto. In other embodiments, the main gate portion260BM of the gate line260B may include a recess top surface extending long in the second horizontal direction (the Y direction) at the second vertical level LV22or a recess top surface extending long in the second horizontal direction (the Y direction) at the fourth vertical level LV24, instead of the recess top surface260BL.

FIG.11is a cross-sectional view for describing an integrated circuit device200C according to other embodiments. InFIG.11, some elements of a portion corresponding to a cross-sectional surface taken along line Y1-Y1′ ofFIG.1is illustrated.

Referring toFIG.11, the integrated circuit device200C may have substantially the same configuration as that of the integrated circuit device200described above with reference toFIG.8. The integrated circuit device200C may include a gate line260C instead of the gate line260of the integrated circuit device200.

The gate line260C may have substantially the same configuration as that of the gate line260described above with reference toFIG.8. A main gate portion260CM of the gate line260C may include a connection protrusion portion260CP, which includes a protrusion top surface260CU extending long in a second horizontal direction (a Y direction) at a first vertical level LV1on a substrate102, and a recess top surface260CL, which extends long in the second horizontal direction (the Y direction) from the connection protrusion portion260CP at a second vertical level LV22, which is lower than the first vertical level LV1.

The connection protrusion portion260CP of the main gate portion260CM may extend long in the second horizontal direction (the Y direction) in a portion of the first device region RX1, an inter-device isolation region DTA, and a portion of the second device region RX2. A first stepped portion ST2A between one end of the connection protrusion portion260CP and the recess top surface260CL may overlap a plurality of fin-type active regions FA and a plurality of nanosheet stacks NSS in a vertical direction (a Z direction) in the first device region RX1, and a second stepped portion ST2B between the other end of the connection protrusion portion260CP and the recess top surface260CL may overlap a plurality of fin-type active regions FA and a plurality of nanosheet stacks NSS in the vertical direction (the Z direction) in the second device region RX2.

InFIG.11, for example, a structure is illustrated in which the main gate portion260CM of the gate line260C includes the recess top surface260CL extending long in the second horizontal direction (the Y direction) at the second vertical level LV22which is the same as a top level of the gate dielectric layer152covering an uppermost surface of the third nanosheet N3, but the inventive concept is not limited thereto. In other embodiments, the main gate portion260CM of the gate line260C may include a recess top surface extending long in the second horizontal direction (the Y direction) at the third vertical level LV23or a recess top surface extending long in the second horizontal direction (the Y direction) at the fourth vertical level LV24, instead of the recess top surface260CL.

FIG.12is a cross-sectional view for describing an integrated circuit device300according to other embodiments. InFIG.12, some elements of a portion corresponding to a cross-sectional surface taken along line Y1-Y1′ ofFIG.1is illustrated.

Referring toFIG.12, the integrated circuit device300may have substantially the same configuration as that of the integrated circuit device100described above with reference toFIGS.1and2A to2D. The integrated circuit device300may include a gate line360instead of the gate line160of the integrated circuit device100.

The gate line360may have substantially the same configuration as that of the gate line160described above with reference toFIGS.2A to2C. A main gate portion360M of the gate line360may include a connection protrusion portion360P, which includes a protrusion top surface360U at a first vertical level LV1on a substrate102, and a recess top surface360L which extends long in a second horizontal direction (a Y direction) from the connection protrusion portion360P at a second vertical level LV32which is lower than the first vertical level LV1. In embodiments, a height difference between the first vertical level LV1and the second vertical level LV32may be about 2 nm to about 20 nm, but is not limited thereto. A vertical level of the recess top surface360L of the main gate portion360M may be the same as or similar to a vertical level of an uppermost surface of a nanosheet stack NSS, namely, an uppermost surface of a third nanosheet N3.

The recess top surface360L of the main gate portion360M may include a recess portion360R formed at a position overlapping a fin-type active region FA and a nanosheet stack NSS in a vertical direction (a Z direction) in a first device region RX1and a second device region RX2. The recess portion360R may be filled with the third nanosheet N3and a gate dielectric layer152covering a side surface and a bottom surface of the third nanosheet N3. In embodiments, the gate dielectric layer152filling the recess portion360R may contact a capping insulation pattern164at the second vertical level LV32.

InFIG.12, a structure is illustrated in which the main gate portion360M of the gate line360includes the recess top surface360L which extends long in the second horizontal direction (the Y direction) at the same second vertical level LV32as a vertical level of an uppermost surface of the third nanosheet N3, but the inventive concept is not limited thereto. In other embodiments, the main gate portion360M of the gate line360may include a recess top surface which extends long in the second horizontal direction (the Y direction) at the same third vertical level LV33as a level of an uppermost surface of the second nanosheet N2instead of the recess top surface360L. In this case, the third nanosheet N3illustrated inFIG.12may be omitted. In other embodiments, the main gate portion360M of the gate line360may include a recess top surface which extends long in the second horizontal direction (the Y direction) at the same fourth vertical level LV34as a level of an uppermost surface of the first nanosheet N1instead of the recess top surface360L. In this case, the second and third nanosheets N2and N3illustrated inFIG.12may be omitted.

In the integrated circuit device300, regardless of a vertical level of the recess top surface360L included in the main gate portion360M of the gate line360, the number of nanosheets included in the nanosheet stack NSS in the first device region RX1may be the same as the number of nanosheets included in the nanosheet stack NSS in the second device region RX2.

In embodiments, a process of manufacturing the integrated circuit device300may include a process of oxidizing the third nanosheet N3filling the recess portion360R. In this case, the integrated circuit device300illustrated inFIG.12may include a semiconductor oxide piece having a configuration similar to that of a semiconductor oxide piece420B which will be described below with reference toFIG.15, instead of the third nanosheet N3.

FIGS.13A,13B and13Care cross-sectional views for describing an integrated circuit device400according to other embodiments. InFIG.13A, some elements of a portion corresponding to a cross-sectional surface taken along line X1-X1′ ofFIG.1is illustrated. InFIG.13B, some elements of a portion corresponding to a cross-sectional surface taken along line X2-X2′ ofFIG.1is illustrated. InFIG.13C, some elements of a portion corresponding to a cross-sectional surface taken along line Y1-Y1′ ofFIG.1is illustrated.

Referring toFIGS.13A to13C, the integrated circuit device400may have substantially the same configuration as that of the integrated circuit device100described above with reference toFIGS.1and2A to2D. The integrated circuit device400may include a gate line460instead of the gate line160of the integrated circuit device100.

The gate line460may have substantially the same configuration as that of the gate line160described above with reference toFIGS.2A to2C. A main gate portion460M of the gate line460may include a connection protrusion portion460P, which includes a protrusion top surface460U at a first vertical level LV1on a substrate102, and a recess top surface460L which extends long in a second horizontal direction (a Y direction) from the connection protrusion portion460P at a second vertical level LV42which is lower than a first vertical level LV1.

Each of a plurality of nanosheet stacks NSS covered by the gate line460may include two nanosheets N1and N2(for example, a first nanosheet N1and a second nanosheet N2), in a first device region RX1and a second device region RX2. The recess top surface460L of the main gate portion460M may be higher than an uppermost surface of the second nanosheet N2of the nanosheet stack NSS, in a vertical direction (a Z direction). An uppermost surface of each of the nanosheet stack NSS and a gate dielectric layer152covering the nanosheet stack NSS may be at a vertical level which is lower than a second vertical level LV42of the recess top surface460L of the main gate portion460M.

As illustrated inFIGS.13A and13B, a plurality of semiconductor oxide pieces420may be disposed at a position overlapping the nanosheet stack NSS in the vertical direction (the Z direction), in the first device region RX1and the second device region RX2. A top surface of the semiconductor oxide piece420may contact an outer insulation spacer118.

The plurality of semiconductor oxide pieces420may each be disposed between a first source/drain region SD1and a capping insulation pattern164, in the first device region RX1. The plurality of semiconductor oxide pieces420may each include a portion contacting the first source/drain region SD1and a portion contacting the capping insulation pattern164. The plurality of semiconductor oxide pieces420may each be disposed between a second source/drain region SD2and the capping insulation pattern164, in the second device region RX2. The plurality of semiconductor oxide pieces420may each include a portion contacting the second source/drain region SD2and a portion contacting the capping insulation pattern164.

The plurality of semiconductor oxide pieces420may include the same semiconductor material as a semiconductor material included in the first and second nanosheets N1and N2included in the nanosheet stack NSS. In embodiments, the plurality of semiconductor oxide pieces420may each include silicon oxide. In embodiments, a semiconductor oxide piece420disposed in the first device region RX1among the plurality of semiconductor oxide pieces420may include silicon oxide including an n-type dopant, and a semiconductor oxide piece420disposed in the second device region RX2among the plurality of semiconductor oxide pieces420may include silicon oxide including a p-type dopant. The n-type dopant may be selected from among P, As, and Sb, and the p-type dopant may be selected from among B and Ga.

In embodiments, a portion of a third nanosheet N3which is an uppermost nanosheet of the plurality of nanosheets N1to N3may be removed in an etching process included in a process of forming a connection protrusion portion460P in a process of manufacturing the integrated circuit device400. Each of the plurality of semiconductor oxide pieces420may be a resultant material which is obtained by oxidizing a remaining portion of the third nanosheet N3from which a portion thereof is removed in a process of forming the connection protrusion portion460P.

InFIGS.13A to13C, a structure is illustrated in which the main gate portion460M of the gate line460includes a recess top surface460L extending long in a second horizontal direction (a Y direction) at a second vertical level LV42, but the inventive concept is not limited thereto. In other embodiments, the main gate portion460M of the gate line460may include a recess top surface extending long in the second horizontal direction (the Y direction) at a third vertical level LV43which is a vertical level between the first nanosheet N1and the second nanosheet N2, instead of the recess top surface460L. In this case, the second nanosheet N2illustrated inFIGS.13A to13Cmay be omitted.

In the integrated circuit device400, regardless of a vertical level of the recess top surface460L included in the main gate portion460M of the gate line460, the number of nanosheets included in the nanosheet stack NSS in the first device region RX1may be the same as the number of nanosheets included in the nanosheet stack NSS in the second device region RX2. In other embodiments, like the integrated circuit device200A or200B described above with reference toFIG.9or10, the connection protrusion portion460P may be formed in one of the first device region RX1and the second device region RX2. In this case, the number of nanosheets included in the nanosheet stack NSS in the first device region RX1may differ from the number of nanosheets included in the nanosheet stack NSS in the second device region RX2.

FIG.14is a cross-sectional view for describing an integrated circuit device400A according to other embodiments. InFIG.14, some elements of a portion corresponding to a cross-sectional surface taken along line Y1-Y1′ ofFIG.1is illustrated.

Referring toFIG.14, the integrated circuit device400A may have substantially the same configuration as that of the integrated circuit device400described above with reference toFIGS.13A to13C. The integrated circuit device400A may include a gate line460A instead of the gate line460of the integrated circuit device400.

The gate line460A may have substantially the same configuration as that of the gate line460described above with reference toFIGS.13A to13C. A main gate portion460AM of the gate line460A may include a connection protrusion portion460AP, which includes a protrusion top surface460AU extending long in a second horizontal direction (a Y direction) at a first vertical level LV1on a substrate102, and a recess top surface460AL which extends long in the second horizontal direction (the Y direction) from the connection protrusion portion460AP at a second vertical level LV42which is lower than the first vertical level LV1.

The connection protrusion portion460AP of the main gate portion460AM may extend long in the second horizontal direction (the Y direction) in a portion of the first device region RX1, an inter-device isolation region DTA, and a portion of the second device region RX2. A first stepped portion ST4A between one end of the connection protrusion portion460AP and the recess top surface460AL may overlap a plurality of fin-type active regions FA and a plurality of nanosheet stacks NSS in a vertical direction (a Z direction) in the first device region RX1, and a second stepped portion ST4B between the other end of the connection protrusion portion460AP and the recess top surface460AL may overlap a plurality of fin-type active regions FA and a plurality of nanosheet stacks NSS in the vertical direction (the Z direction) in the second device region RX2.

A lateral recess portion460R, which is locally recessed in a first horizontal direction (an X direction) at a position overlapping a plurality of nanosheets N1and N2included in each of the nanosheet stacks NSS in the vertical direction (the Z direction), may be formed in each of a protrusion sidewall SWA at one end of the connection protrusion portion460AP and a protrusion sidewall SWB at the other end of the connection protrusion portion460AP.

InFIG.14, a configuration is illustrated in which the lateral recess portion460R is formed in each of the protrusion sidewall SWA at the one end of the connection protrusion portion460AP and the protrusion sidewall SWB at the other end of the connection protrusion portion460AP, but the inventive concept is not limited thereto. In other embodiments, only one of the protrusion sidewalls SWA and SWB respectively disposed at the one end and the other end of the connection protrusion portion460AP may overlap the plurality of nanosheets N1and N2included in each nanosheet stack NSS in the vertical direction (the Z direction), and the lateral recess portion460R may be formed in only one of the protrusion sidewalls SWA and SWB.

InFIG.14, a structure is illustrated in which the main gate portion460AM of the gate line460A includes a recess top surface460AL extending in the second horizontal direction (the Y direction) at the second vertical level LV42, but the inventive concept is not limited thereto. In other embodiments, the main gate portion460AM of the gate line460A may include a recess top surface which extends in the second horizontal direction (the Y direction) at the third vertical level LV43, instead of the recess top surface460AL. In this case, in the integrated circuit device400A, the nanosheet stack NSS covered by the gate line460A may include only one nanosheet (for example, the first nanosheet N1), and two lateral recess portions460R, which are apart from each other in the vertical direction (the Z direction) at a position overlapping the first nanosheet N1in the vertical direction (the Z direction), may be respectively formed in the protrusion sidewalls SWA and SWB respectively disposed at the one end and the other end of the connection protrusion portion460AP.

FIG.15is a cross-sectional view for describing an integrated circuit device400B according to other embodiments. InFIG.15, some elements of a portion corresponding to a cross-sectional surface taken along line Y1-Y1′ ofFIG.1is illustrated.

Referring toFIG.15, the integrated circuit device400B may have substantially the same configuration as that of the integrated circuit device400A described above with reference toFIG.14. The integrated circuit device400B may include a plurality of semiconductor oxide pieces420B.

Each of the plurality of semiconductor oxide pieces420B may include a portion, which is buried into the lateral recess portion460R formed in each of protrusion sidewalls SWA and SWB of a connection protrusion portion460AP, and a portion which protrudes in a second horizontal direction (a Y direction) from the protrusion sidewalls SWA and SWB. Each of the plurality of semiconductor oxide pieces420B may include a gate dielectric layer152. The plurality of semiconductor oxide pieces420B may be respectively disposed at positions which overlap a plurality of nanosheets N1and N2included in a nanosheet stack NSS in a vertical direction (a Z direction). A material of each of the plurality of semiconductor oxide pieces420B may be substantially the same as that of the semiconductor oxide piece420described above with reference toFIGS.13A to13C.

InFIG.15, a configuration is illustrated in which the semiconductor oxide pieces420B are respectively disposed at positions adjacent to the protrusion sidewalls SWA and SWB at the one end and the other end of the connection protrusion portion460AP, but the inventive concept is not limited thereto. In embodiments, only one of the protrusion sidewalls SWA and SWB of the one end and the other end of the connection protrusion portion460AP may overlap the plurality of nanosheets N1and N2included in the nanosheet stack NSS in the vertical direction (the Z direction), and the semiconductor oxide piece420B may be formed at only a position adjacent to a protrusion sidewall, overlapping the plurality of nanosheets N1and N2in the vertical direction (the Z direction), of the protrusion sidewalls SWA and SWB.

InFIG.15, a structure is illustrated in which a main gate portion460AM of the gate line460A includes a recess top surface460AL extending in a second horizontal direction (a Y direction) at a second vertical level LV42, but the inventive concept is not limited thereto. In other embodiments, the main gate portion460AM of the gate line460A may include a recess top surface which extends in the second horizontal direction (the Y direction) at a third vertical level LV43, instead of the recess top surface460AL. In this case, in the integrated circuit device400B, the nanosheet stack NSS covered by the gate line460A may include only one nanosheet (for example, a first nanosheet N1), and two semiconductor oxide pieces420B apart from each other in the vertical direction (the Z direction) may be formed at positions adjacent to the protrusion sidewalls SWA and SWB of the one end and the other end of the connection protrusion portion460AP.

FIG.16is a cross-sectional view for describing an integrated circuit device500according to other embodiments. InFIG.16, some elements of a portion corresponding to a cross-sectional surface taken along line Y1-Y1′ ofFIG.1is illustrated.

Referring toFIG.16, the integrated circuit device500may have substantially the same configuration as that of the integrated circuit device100described above with reference toFIGS.1and2A to2D. The integrated circuit device500may include a gate line560instead of the gate line160of the integrated circuit device100.

The gate line560may have substantially the same configuration as that of the gate line160described above with reference toFIGS.2A to2C. A main gate portion560AM of the gate line560may include a connection protrusion portion560P, which includes a protrusion top surface160U at a first vertical level LV1on a substrate102, and a recess top surface160L which extends long in a second horizontal direction (a Y direction) from the connection protrusion portion560P at a second vertical level LV52which is lower than the first vertical level LV1.

The connection protrusion portion560P of the main gate portion560M may be disposed in only a first device region RX1among the first device region RX1and a second device region RX2and may not be disposed in the second device region RX2. The recess top surface560L of the main gate portion560M may be disposed in only the second device region RX2among the first device region RX1and the second device region RX2and may not be disposed in the first device region RX1. A stepped portion ST5between the connection protrusion portion560P and the recess top surface560L of the main gate portion560M may overlap an inter-device isolation layer114in a vertical direction (a Z direction) in an inter-device isolation region DTA.

The connection protrusion portion560P of the main gate portion560M may overlap a plurality of fin-type active regions FA and a plurality of nanosheet stacks NSS in the vertical direction (the Z direction) in the first device region RX1. The recess top surface560L of the main gate portion560M may overlap a plurality of fin-type active regions FA and a first nanosheet N1in the vertical direction (the Z direction) in the second device region RX2.

In the integrated circuit device500, a stack structure of a gate contact184and a gate via contact194each connected to a gate line560may be disposed in the first device region RX1. The gate contact184may contact the protrusion top surface560U of the connection protrusion portion560P included in the main gate portion560M in the first device region RX1. A stack structure of the gate contact184and the gate via contact194each connected to the gate line560may overlap a plurality of fin-type active regions FA and a plurality of nanosheet stacks NSS in the vertical direction (the Z direction) in the first device region RX1. In the integrated circuit device600, the number of nanosheets included in the nanosheet stack NSS in the second device region RX2may be less than the number of nanosheets included in the nanosheet stack NSS in the first device region RX1. InFIG.16, an example in which only the first nanosheet NS is included in the nanosheet stack NSS in the second device region RX2is illustrated, but the inventive concept is not limited thereto. For example, the recess top surface560L of the main gate portion560M may extend in the second horizontal direction (the Y direction) which is lower than the first vertical level LV1and is higher than a second vertical level LV52, and the nanosheet stack NSS in the second device region RX2may include a plurality of nanosheets including at least one first nanosheet NS.

InFIG.16, an example in which the connection protrusion portion560P is in the first device region RX1and the recess top surface560L is in the second device region RX2is illustrated, but the inventive concept is not limited thereto. For example, like the integrated circuit devices100C,100D, and200B illustrated inFIGS.5,6A,6B, and10, the connection protrusion portion560P may be in the second device region RX2, and the recess top surface560L may be in the first device region RX1. In this case, the number of nanosheets included in the nanosheet stack NSS in the first device region RX1may be less than the number of nanosheets included in the nanosheet stack NSS in the second device region RX2.

FIGS.17A,17B and17Care cross-sectional views for describing an integrated circuit device600A,600B or600C according to other embodiments. InFIG.17A, some elements of a portion corresponding to a cross-sectional surface taken along line Y1-Y1′ ofFIG.1is illustrated.

Referring toFIG.17A, the integrated circuit device600A may have substantially the same configuration as that of the integrated circuit device200described above with reference toFIG.8. The integrated circuit device600A may include a gate line660A instead of the gate line260of the integrated circuit device200.

The gate line660A may have substantially the same configuration as that of the gate line260described above with reference toFIG.8. A main gate portion660AM of the gate line660A may not include a connection protrusion portion260P. The main gate portion660AM may include a recess top surface660AT which extends to be flat in a second horizontal direction (a Y direction) at a second vertical level LV6A which is lower than the first vertical level LV1illustrated inFIG.8. The recess top surface660AT may extend to be fat over a total length of the gate line660A in the second horizontal direction (the Y direction).

The recess top surface660AT of the main gate portion660AM, like the description of the recess top surface260L of the main gate portion260M described above with reference toFIG.8, may include a recess portion260R which is formed at a position overlapping a fin-type active region FA and a nanosheet stack NSS in a vertical direction (a Z direction) in a first device region RX1and a second device region RX2. The recess portion260R may be filled with a third nanosheet N3and a gate dielectric layer152which covers a side surface, a bottom surface, and a top surface of the third nanosheet N3.

In embodiments, a process of manufacturing the integrated circuit device600A may include a process of oxidizing the third nanosheet N3filling the recess portion260R. In this case, the integrated circuit device600A illustrated inFIG.17Amay include a semiconductor oxide piece having a configuration similar to that of the semiconductor oxide piece420B illustrated inFIG.15, instead of the third nanosheet N3.

InFIG.17A, a structure in which the main gate portion660AM of the gate line660A includes the recess top surface660AT extending long in in the second horizontal direction (the Y direction) at a second vertical level LV6A, but the inventive concept is not limited thereto. In other embodiments, the gate line660A may include a recess top surface which extends long in the second horizontal direction (the Y direction) at the third vertical level LV23or the fourth vertical level LV24illustrated inFIG.8, instead of the recess top surface660AT. In this case, either one or both of the second and third nanosheets N2and N3illustrated inFIG.17Amay be omitted.

In the integrated circuit device600A, a stack structure of a gate contact684A and a gate via contact194each connected to the gate line660A may be disposed in an inter-device isolation region DTA. In other embodiments, the stack structure of the gate contact684A and the gate via contact194may be disposed in one of the first device region RX1and the second device region RX2. A vertical length H6A (i.e., a height in a vertical direction (a Z direction)) of the gate contact684A may be greater than a vertical length of the gate contact184illustrated inFIG.8.

InFIG.17B, some elements of a portion corresponding to a cross-sectional surface taken along line Y1-Y1′ ofFIG.1is illustrated.

Referring toFIG.17B, the integrated circuit device600B may have substantially the same configuration as that of the integrated circuit device400described above with reference toFIGS.13A to13C. The integrated circuit device600B may include a gate line660B instead of the gate line460of the integrated circuit device400.

The gate line660B may have substantially the same configuration as that of the gate line460described above with reference toFIGS.13A to13C. A main gate portion660BM of the gate line660B may not include a connection protrusion portion460P. The main gate portion660BM may include a recess top surface660BT which extends to be flat in a second horizontal direction (a Y direction) at a second vertical level LV6B which is lower than the first vertical level LV1illustrated inFIG.13C. The recess top surface660BT may extend to be fat over a total length of the gate line660B in the second horizontal direction (the Y direction).

Descriptions of the recess top surface660BT of the main gate portion660BM and peripheral elements thereof may be substantially the same as the descriptions of the recess top surface460L and the peripheral elements thereof described above with reference toFIG.13C.

In the integrated circuit device600B, a stack structure of a gate contact684B and a gate via contact194each connected to the gate line660B may be disposed in an inter-device isolation region DTA. In other embodiments, the stack structure of the gate contact684B and the gate via contact194may be disposed in one of the first device region RX1and the second device region RX2. A vertical length H6B (i.e., a height in a vertical direction (a Z direction)) of the gate contact684B may be greater than a vertical length of the gate contact184illustrated inFIG.13C.

InFIG.17C, some elements of a portion corresponding to a cross-sectional surface taken along line Y1-Y1′ ofFIG.1is illustrated.

Referring toFIG.17C, the integrated circuit device600C may have substantially the same configuration as that of the integrated circuit device500described above with reference toFIG.16. The integrated circuit device600C may include a gate line660C instead of the gate line560of the integrated circuit device500.

The gate line660C may have substantially the same configuration as that of the gate line560described above with reference toFIG.16. A main gate portion660CM of the gate line660C may not include a connection protrusion portion560P. The main gate portion660CM may include a recess top surface660CT which extends to be flat in a second horizontal direction (a Y direction) at a second vertical level LV6C which is lower than the first vertical level LV1illustrated inFIG.16. The recess top surface660CT may extend to be fat over a total length of the gate line660C in the second horizontal direction (the Y direction).

Descriptions of the recess top surface660CT of the main gate portion660CM and peripheral elements thereof may be substantially the same as the descriptions of the recess top surface560L and the peripheral elements thereof described above with reference toFIG.16.

In the integrated circuit device600C, a stack structure of a gate contact684C and a gate via contact194each connected to the gate line660C may be disposed in an inter-device isolation region DTA. In other embodiments, the stack structure of the gate contact684C and the gate via contact194may be disposed in one of the first device region RX1and the second device region RX2. A vertical length H6C (i.e., a height in a vertical direction (a Z direction)) of the gate contact684C may be greater than a vertical length of the gate contact184illustrated inFIG.16.

FIG.18is a block diagram of an integrated circuit device700according to embodiments.

Referring toFIG.18, the integrated circuit device700may include a substrate including a first region I and a second region II. The first region I and the second region II of the substrate102may denote different regions and may be regions for performing different operations on the substrate102. The first region I and the second region II may be regions which are apart from each other, or may be regions connected to each other.

In some embodiments, each of the first region I and the second region II may be a region selected from among a memory region and a non-memory region. The memory region may be a region configuring a volatile memory device, such as dynamic random access memory (DRAM) or static random access memory (SRAM), or a non-volatile memory device such as read only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable ROM (EPROM), electrically erasable ROM (EEPROM), ferromagnetic ROM (FRAM), phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or flash memory. The non-memory region may include a logic region. The logic region may include a plurality of standard cells, performing a desired logical function, such as a counter and a buffer. The standard cells may include various kinds of logic cells including a plurality of circuit elements such as a transistor and a register. The logic cells may configure, for example, an AND gate, a NAND gate, an OR gate, a NOR gate, an exclusive OR (XOR) gate, an exclusive NOR (XNOR) gate, an inverter (INV), an adder (ADD), a buffer (BUF), a delay (DLY), a filter (FIL), and a multiplexer (MXT/MXIT). The logic cells may configure OR/AND/INVERTER (OAI), AND/OR (AO), AND/OR/INVERTER (AOI), a D flip-flop, a reset flip-flop, a master-slave flip-flop, and a latch.

FIGS.19A,19B and19Care cross-sectional views for describing some elements of a first region I of the integrated circuit device700illustrated inFIG.18. InFIG.19A, some elements of a portion corresponding to a cross-sectional surface taken along line X1-X1′ ofFIG.1is illustrated. InFIG.19B, some elements of a portion corresponding to a cross-sectional surface taken along line X2-X2′ ofFIG.1is illustrated. InFIG.19C, some elements of a portion corresponding to a cross-sectional surface taken along line Y1-Y1′ ofFIG.1is illustrated.

Referring toFIGS.19A to19C, in the first region I of the integrated circuit device700, a substrate102may have substantially the same structure as that of the integrated circuit device100described above with reference toFIGS.1and2A to2D. A gate line760, instead of the gate line160, may be formed on the substrate102in the first region I of the integrated circuit device700.

The gate line760may have substantially the same configuration as that of the gate line160described above with reference toFIGS.1and2A to2D. The gate line760may include a main gate portion760M including a top surface760T which extends to be flat in a second horizontal direction (a Y direction) at a first vertical level LV1. The top surface760T of the main gate portion760M included in the gate line760may extend to be flat over a total length of the gate line760in the second horizontal direction (the Y direction). A protrusion portion may not be formed in the top surface760T of the gate line760.

In the first region I of the integrated circuit device700, a stack structure of a gate contact184and a gate via contact194each connected to the gate line760may be disposed in an inter-device isolation region DTA. In other embodiments, the stack structure of the gate contact184and the gate via contact194may be disposed in one of a first device region RX1and a second device region RX2.

In embodiments, a vertical length H7(i.e., a height in a vertical direction (a Z direction)) of the gate contact184may be the same as or similar to a vertical length of the gate contact184illustrated inFIG.2C. In other embodiments, a vertical length H7of the gate contact184may be less than vertical lengths H6A, H6B, and H6C of the gate contacts684A,684B, and684C illustrated inFIGS.17A to17C.

Referring again toFIG.18, in the second region II of the integrated circuit device700, the substrate102may include at least one structure selected from among the structures of the integrated circuit devices100,100A,100B,100C,100D,100E,200,200A,200B,200C,300,400,400A,400B,500,600A,600B, and600C described above with reference toFIGS.2A to17. In embodiments, the first region I of the integrated circuit device700may include a nanosheet stack NSS including at least one nanosheet surrounded by the gate line760described above with reference toFIGS.19A to19C, and the second region II may include a nanosheet stack NSS including at least one nanosheet surrounded by one of the gate lines260A,260B,460,460A,560,660B, and660C described above with reference toFIGS.9,10,13A to13C,14,15,16,17B, and17C. Also, the number of nanosheets included in a nanosheet stack NSS in the second region II may be less than the number of nanosheets included in a nanosheet stack NSS in the first region I.

In the integrated circuit device700described above with reference toFIGS.18and19A to19C, at least a portion of a gate line disposed in the second region II may include a recess top surface which is lower than a top surface of the gate line760disposed in the first region I. Therefore, in the second region II of the integrated circuit device700, an undesired parasitic capacitance between conductive regions adjacent to each other may be reduced, and a work function for transistors including a gate line including the recess top surface may be easily controlled.

In the integrated circuit devices described above with reference toFIGS.1to19C, a configuration in which any one or any combination of the plurality of nanosheets N1to N3is provided on the fin-type active region FA has been described for example, but the inventive concept is not limited thereto. For example, in the integrated circuit devices described above with reference toFIGS.1to19C, a semiconductor body having a nanowire shape instead of a nanosheet may be formed on the fin-type active region FA.

FIG.20Ais a plan layout diagram for describing an integrated circuit device800according to embodiments.FIG.20Bis a cross-sectional view illustrating some elements of a cross-sectional surface taken along line Y8-Y8′ ofFIG.20A.

Referring toFIGS.20A and20B, the integrated circuit device800may configure a logic cell including a fin field effect transistor (FinFET). The integrated circuit device800may include a logic cell LC which is formed in a region limited by a cell boundary BN on a substrate802. A more detailed description of the substrate802may be substantially the same as the description of the substrate102given above with reference toFIGS.2A to2D.

The logic cell LC may include a first device region RX81and a second device region RX82. A plurality of fin-type active regions FB protruding from the substrate802may be formed in each of the first device region RX81and the second device region RX82. An inter-device isolation region DTA8may be disposed between the first device region RX81and the second device region RX82.

The plurality of fin-type active regions FB may extend in parallel in a width direction of the logic cell LC (i.e., a first horizontal direction (an X direction)). An isolation layer812may be formed on the substrate802between two adjacent fin-type active regions FB of the plurality of fin-type active regions FB, and an inter-device isolation layer814may be formed on the substrate802in the inter-device isolation region DTA8. The isolation layer812and the inter-device isolation layer814may respectively have substantially the same configurations as those of the isolation layer812and the inter-device isolation layer814described above with reference toFIGS.2A to2D. The plurality of fin-type active regions FB may protrude to a portion on the isolation layer812in a fin shape, in the first device region RX81and the second device region RX82.

A plurality of gate dielectric layers832and a plurality of gate lines860may extend in a height direction (i.e., a second horizontal direction (a Y direction)) of the logic cell LC on the substrate802. The plurality of gate dielectric layers832and the plurality of gate lines860may cover a top surface and both sidewalls of each of the plurality of fin-type active regions FB, a top surface of the isolation layer812, and a top surface of the inter-device isolation layer814. A plurality of MOS transistors may be formed along the plurality of gate lines860in the first device region RX81and the second device region RX82. Each of the plurality of MOS transistors may be an MOS transistor having a three-dimensional (3D) structure in which a channel is formed at each of the top surfaces and the both sidewalls of the plurality of fin-type active regions FB.

A dummy gate line DGL may extend along a cell boundary BN extending in the second horizontal direction (the Y direction). The dummy gate line DGL may include the same material as that of each of the plurality of gate lines860. The dummy gate line DGL may maintain an electric floating state while an operation of the integrated circuit device800is operating, and thus, may function as an electrical isolation region between the logic cell LC and another peripheral logic cell thereof. The plurality of gate lines860and the plurality of dummy gate lines DGL may each have the same width in the first horizontal direction (the X direction) and may be arranged at a pitch in the first horizontal direction (the X direction).

The plurality of gate dielectric layers832may have the same configuration as that of the gate dielectric layer152described above with reference toFIGS.2A to2D. The plurality of gate lines860and the plurality of dummy gate lines DGL may each have the same configuration as that of the gate line160described above with reference toFIGS.2A to2D.

The gate line860may include a connection protrusion portion860P, which includes a protrusion top surface860U at a first vertical level LV81on a substrate802, and a recess top surface860L which extends long in the second horizontal direction (the Y direction) from the connection protrusion portion860P at a second vertical level LV82which is lower than the first vertical level LV81. The gate line860may extend long in the second horizontal direction (the Y direction) in the first device region RX81, the inter-device isolation region DTA8, and the second device region RX82. The recess top surface860L of the gate line860may be higher than an uppermost surface of the fin-type active region FB in a vertical direction (a Z direction). A top surface of the gate line860may be covered by an insulation capping line864. The insulation capping line864may contact the protrusion top surface860U and the recess top surface860L. A plurality of insulation capping lines864may include silicon nitride.

A plurality of source/drain regions may be formed at both sides of each of the gate lines860, on top surfaces of the plurality of fin-type active regions FB. In embodiments, the first device region RX81may be an NMOS transistor region, and the second device region RX82may be a PMOS transistor region. In this case, a plurality of source/drain regions in the first device region RX81may have substantially the same configuration as that of the first source/drain region SD1described above with reference toFIGS.2A to2D, and a plurality of source/drain regions in the second device region RX82may have substantially the same configuration as that of the second source/drain region SD2described above with reference toFIGS.2A to2D.

A plurality of source/drain contacts874may be formed on the plurality of source/drain regions, in the first device region RX81and the second device region RX82. A plurality of source/drain via contacts892may be formed on the plurality of source/drain contacts874. The plurality of source/drain contacts874and the plurality of source/drain via contacts892may respectively have the same configurations as those of the source/drain contact174and the source/drain via contact192described above with reference toFIGS.2A to2D.

An insulation structure890may be formed on the insulation capping line864. The insulation structure890may include an etch stop layer890A and an interlayer insulation layer890B, which are sequentially stacked on the insulation capping line864.

A gate contact884and a gate via contact894may be formed on the gate line860. The gate line860may be connected to an upper conductive line through the gate contact884and the gate via contact894. The gate contact884and the gate via contact894may be configured to be connected to the connection protrusion portion860P in the inter-device isolation region DTA8. The gate contact884may pass through the capping insulation pattern164in the vertical direction (the Z direction) and may contact a top surface of the connection protrusion portion860P of the gate line860. The gate via contact894may pass through the insulation structure890in the vertical direction (the Z direction) and may contact a top surface of the gate contact884. A vertical level of an uppermost surface of the gate contact884may be the same as or similar to a vertical level of an uppermost surface of each of the plurality of source/drain contacts874. The gate contact884and the gate via contact894may respectively have the same configurations as those of the gate contact184and the gate via contact194described above with reference toFIGS.2A to2D.

The connection protrusion portion860P of the gate line860and a stack structure of the gate contact884and the gate via contact894each disposed on the gate line860may be disposed in the second device region RX2. However, the inventive concept is not limited to the illustrations ofFIGS.20A and20B. For example, the connection protrusion portion860P of the gate line860and the stack structure of the gate contact884and the gate via contact894each disposed on the gate line860may be disposed in the inter-device isolation region DTA or the first device region RX81.

In the logic cell LC, a ground line VSS may be connected to a fin-type active region FB, disposed in the first device region RX81, through some of the plurality of source/drain contacts874, and a power line VDD may be connected to a fin-type active region FB, disposed in the second device region RX82, through the other source/drain contacts874of the plurality of source/drain contacts874. The ground line VSS and the power line VDD may be formed at a level which is higher than a top surface of each of the plurality of source/drain contacts874and the plurality of gate contacts894. The ground line VSS and the power line VDD may respectively include a conductive barrier layer and a wiring conductive layer. The conductive barrier layer may include Ti, Ta, TiN, TaN, or a combination thereof. The wiring conductive layer may include Co, Cu, W, an alloy thereof, or a combination thereof.

In the integrated circuit device800illustrated inFIGS.20A and2B, the connection protrusion portion860P including the protrusion top surface860U at the first vertical level LV81which is relatively high may be included in a portion, connected to the gate contact884, of the gate line860, and another portion, which is near the connection protrusion portion860P, of the gate line860may include the recess top surface860L at the second vertical level LV82which is lower than the first vertical level LV81. Therefore, in the integrated circuit device800, an undesired parasitic capacitance between conductive regions adjacent to each other may be reduced. Also, a height difference in the vertical direction (the Z direction) between the protrusion top surface860U at the first vertical level LV81and the recess top surface860L at the second vertical level LV82may be variously adjusted, and thus, a work function for transistors including the gate line860may be easily controlled. Therefore, by using the gate line860including the protrusion top surface860U and the recess top surface860L which are at various vertical levels and have various sizes on the basis of a desired condition, the reliability of an integrated circuit device may be enhanced by a relatively simple method.

FIGS.21A,21B,21C,22A,22B,22C,23A,23B,23C,24A,24B,24C,25A,25B,25C,26A,26B,26C,27A,27B,27C,28A,28B,28C,29A,29B,29C,30A,30B,30C,31A,31B and31C are cross-sectional views illustrating a method of manufacturing an integrated circuit device in a process sequence, according to embodiments.FIGS.21A,22A, . . . , and31A are cross-sectional views illustrating some elements, based on a process sequence, of a portion corresponding to a cross-sectional surface taken along line X1-X1′ ofFIG.1.FIGS.21B,22B, . . . , and31B are cross-sectional views illustrating some elements, based on a process sequence, of a portion corresponding to a cross-sectional surface taken along line X2-X2′ ofFIG.1.FIGS.21C,22C, . . . , and31C are cross-sectional views illustrating some elements, based on a process sequence, of a portion corresponding to a cross-sectional surface taken along line Y1-Y1′ ofFIG.1. A method of manufacturing the integrated circuit device100illustrated inFIGS.1and2A to2Dwill be described below with reference toFIGS.21A to31C. InFIGS.21A to31C, the same reference numerals asFIGS.1and2A to2Drefer to like elements, and their detailed descriptions may be omitted.

Referring toFIGS.21A to21C, a plurality of sacrificial semiconductor layers104and a plurality of nanosheet semiconductor layers NS may be alternately stacked on a substrate102, and then, a plurality of fin-type active regions FA which protrude upward in a vertical direction (a Z direction) from the substrate102and extend in parallel in a first horizontal direction (an X direction) may be formed by etching the plurality of sacrificial semiconductor layers104, the plurality of nanosheet semiconductor layers NS, and a portion of the substrate102, in the first device region RX1and the second device region RX2, and an isolation layer112covering lower both sidewalls of each of the plurality of fin-type active regions FA may be formed. A deep trench DT defining the first device region RX1and the second device region RX2may be formed by etching a portion of the isolation layer112and a portion of the substrate102, and the deep trench DT may be filled with an inter-device isolation layer114. A top surface of the isolation layer112and a top surface of the inter-device isolation layer114may be approximately equal or similar to a fin top surface FT of each of the plurality of fin-type active regions FA.

A stack structure of the plurality of sacrificial semiconductor layers104and the plurality of nanosheet semiconductor layers NS may remain on the fin top surface FT of each of the plurality of fin-type active regions FA, in the first device region RX1and the second device region RX2.

The plurality of sacrificial semiconductor layers104and the plurality of nanosheet semiconductor layers NS may include semiconductor materials having different etch selectivity. In embodiments, the plurality of nanosheet semiconductor layers NS may include a Si layer, and the plurality of sacrificial semiconductor layers104may include a SiGe layer. In embodiments, a Ge content may be constant in the plurality of sacrificial semiconductor layers104. The SiGe layer configuring the plurality of sacrificial semiconductor layers104may have a constant Ge content which is selected within a range of about 5 at. % to about 60 at. % (for example, about 10 at. % to about 40 at. %). A Ge content of the SiGe layer configuring the plurality of sacrificial semiconductor layers104may be variously selected depending on the case.

Referring toFIGS.22A to22C, a dummy gate structure DGS and an outer insulation spacer118covering both sidewalls of the dummy gate structure DGS may be formed on a stack structure of a plurality of sacrificial semiconductor layers104and a plurality of nanosheet semiconductor layers NS.

The dummy gate structure DGS may extend long in a second horizontal direction (a Y direction) intersecting with a fin-type active region FA, on a substrate102. The dummy gate structure DGS may have a structure in which an oxide layer D112, a dummy gate layer D114, and a capping layer D116are sequentially stacked. In embodiments, the dummy gate layer D114may include polysilicon, and the capping layer D116may include silicon nitride.

Subsequently, a first mask pattern MP1including a first opening MH1exposing a first device region RX1may be formed on a resultant material in which the dummy gate structure DGS and the outer insulation spacer118are formed, and then, in a state in which a second device region RX2is covered by the first mask pattern MP1, a portion of each of the plurality of sacrificial semiconductor layers104and the plurality of nanosheet semiconductor layers NS may be removed by using the dummy gate structure DGS and the outer insulation spacer118as an etch mask in the first device region RX1and thus the plurality of nanosheet semiconductor layers NS may be divided into a plurality of nanosheet stacks NSS. Each of the plurality of nanosheet stacks NSS may include first to third nanosheets N1to N3. A plurality of first recesses R1may be formed on the fin-type active region FA by etching the fin-type active region FA exposed between two adjacent nanosheet stacks NSS of the plurality of nanosheet stacks NSS, in the first device region RX1. To form the plurality of first recesses R1, the fin-type active region FA may be etched by using a dry etching process, a wet etching process, or a combination thereof.

Subsequently, by selectively removing a portion of each of the plurality of sacrificial semiconductor layers104exposed at both sides of each of the plurality of nanosheet stacks NSS through the plurality of first recesses R1, a plurality of intent regions104D may be formed between the first to third nanosheets N1to N3and between the first nanosheet N1and the fin-type active region FA, and then, a plurality of inner insulation spacers120filling the plurality of intent regions104D may be formed. To form the plurality of intent regions104D, a portion of each of the plurality of sacrificial semiconductor layers104may be selectively etched by using an etch selectivity difference between the plurality of sacrificial semiconductor layers104and the first to third nanosheets N1to N3. An atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, an oxidization process, or a combination thereof may be used for forming a plurality of inner insulation spacers120.

Subsequently, a plurality of first source/drain regions SD1may be formed on the fin-type active region FA at both sides of each of the plurality of nanosheet stacks NSS. A semiconductor material may be epitaxially grown from a surface of the fin-type active region FA exposed at a bottom surface of each of the plurality of first recesses R1and a sidewall of each of the first to third nanosheets N1to N3, to form the plurality of first source/drain regions SD1. In embodiments, to form the plurality of first source/drain regions SD1, a low-pressure chemical vapor deposition (LPCVD) process, a selective epitaxial growth (SEG) process, or a cyclic deposition and etching (CDE) process may be performed by using source materials including an element semiconductor precursor. In embodiments, the plurality of first source/drain regions SD1may include a Si layer doped with an n-type dopant. Silane (SiH4), desilane (Si2H6), trisilane (Si3H8), and dichlorosilane (SiH2Cl2) may be used as a Si source, to form the plurality of first source/drain regions SD1. The n-type dopant may be selected from among P, As, and Sb.

Referring toFIGS.23A to23C, a first mask pattern MP1may be removed from a resultant material ofFIGS.22A to22C, and then, a second mask pattern MP2including a second opening MH2exposing a second device region RX2may be formed. In a state in which a first device region RX1is covered by the second mask pattern MP2, a portion of each of a plurality of sacrificial semiconductor layers104and the plurality of nano sheet semiconductor layers NS may be removed by using a dummy gate structure DGS and an outer insulation spacer118as an etch mask in the second device region RX2and thus the plurality of nanosheet semiconductor layers NS may be divided into a plurality of nanosheet stacks NSS. Each of the plurality of nanosheet stacks NSS may include first to third nanosheets N1to N3. A plurality of second recesses R2may be formed on a fin-type active region FA by etching the fin-type active region FA exposed between two adjacent nanosheet stacks NSS of the plurality of nanosheet stacks NSS, in the second device region RX2. A method of forming the plurality of recesses R2may be the same as a method of forming the plurality of first recesses R1described above with reference toFIGS.22A to22C.

Subsequently, a plurality of second source/drain regions SD2may be formed on the fin-type active region FA at both sides of each of the plurality of nanosheet stacks NSS. Like the plurality of first source/drain regions SD1described above with reference toFIGS.22A to22C, a semiconductor material may be epitaxially grown from a surface of the fin-type active region FA exposed at a bottom surface of each of the plurality of second recesses R2and a sidewall of each of the first to third nanosheets N1to N3, to form the plurality of second source/drain regions SD2. In embodiments, the plurality of second source/drain regions SD2may include a SiGe layer doped with a p-type dopant. A Si source and a Ge source may be used for forming the plurality of second source/drain regions SD2. Silane (SiH4), desilane (Si2H6), trisilane (Si3H8), and dichlorosilane (SiH2Cl2) may be used as the Si source. Germanium (GeH4), degermanium (Ge2H6), trigermanium (Ge3H8), tetragermanium (Ge4H10), and dichlorogermanium (Ge2H2Cl2) may be used as the Ge source. The p-type dopant may be selected from among B and Ga.

Referring toFIGS.24A to24C, a second mask pattern MP2may be removed from a resultant material ofFIGS.23A to23C, an insulation liner142covering a resultant material in which a plurality of first and second source/drain regions SD1and SD2are exposed may be formed subsequently, an inter-gate insulation layer144may be formed on the insulation liner142subsequently, the insulation liner142and the inter-gate insulation layer144may be planarized subsequently, and a top surface of the dummy gate layer D114may be exposed by removing the capping layer D116. Subsequently, a gate space GS may be formed on the nanosheet stack NSS by removing the dummy gate layer D114and the oxide layer D112thereunder.

Referring toFIGS.25A to25C, by removing the plurality of sacrificial semiconductor layers104, remaining on the fin-type active region FA through the gate space GS on the nanosheet stack NSS, from a resultant material ofFIGS.24A to24C, the gate space GS may extend to a space between the plurality of nanosheets N1to N3and a space between the first nanosheet N1and the fin top surface FT.

In embodiments, an etch selectivity difference between the first to third nano sheets N1to N3and the plurality of sacrificial semiconductor layers104may be used for selectively removing the plurality of sacrificial semiconductor layers104. A liquid or gaseous etchant may be used for selectively removing the plurality of sacrificial semiconductor layers104. In embodiments, a CH3COOH-based etchant (for example, an etchant including a compound of CH3COOH, HNO3, and HF or an etchant including a compound of CH3COOH, H202, and HF) may be used for selectively removing the plurality of sacrificial semiconductor layers104, but the inventive concept is not limited thereto.

Referring toFIGS.26A to26C, a gate dielectric layer152covering the first to third nanosheets N1to N3and exposed surfaces of the fin-type active region FA may be formed from a resultant material ofFIGS.25A to25C, a gate-forming conductive layer GCL which fills the gate space GS (seeFIG.18) and covers a top surface of the inter-gate insulation layer144may be formed on the gate dielectric layer152, and then, a top surface of the inter-gate insulation layer144may be exposed by planarizing an obtained resultant material. An ALD process or a CVD process may be used for forming the gate dielectric layer152and the gate-forming conductive layer GCL.

Referring toFIGS.27A to27C, by removing a portion of each of the gate-forming conductive layer GCL and the gate dielectric layer152from a top surface of a resultant material ofFIGS.26A to26C, a height of a top surface of each of the gate-forming conductive layer GCL and the gate dielectric layer152may be lowered to a first level LV1. As a result, a portion of the gate space GS (seeFIGS.25A to25C) may be empty on each of the gate-forming conductive layer GCL and the gate dielectric layer152again. Subsequently, the empty gate space GS may be filled with an insulation mask162again, and a mask pattern MP3may be formed on the insulation mask162. The mask pattern MP3may be formed to cover a top surface of the insulation mask162, in a region corresponding to a region where a gate contact184is to be formed in a post process. The insulation mask162may include oxide, nitride, or a combination thereof. The mask pattern MP3may include a photoresist pattern.

Referring toFIGS.28A to28C, the insulation mask162may be etched by using the mask pattern MP3as an etch mask in a resultant material ofFIGS.27A to27C, and then, by etching a portion of each of the gate-forming conductive layer GCL and the gate dielectric layer152which are exposed, a height of a top surface of each of the gate-forming conductive layer GCL and the gate dielectric layer152may be lowered to a second level LV2. As a result, the gate line160having different heights based on positions may be formed. The gate line160may include a main gate portion160M and a plurality of sub gate portions160S, and the main gate portion160M may include a connection protrusion portion160P which protrudes upward in a vertical direction (a Z direction) in a partial region of the main gate portion160M. The connection protrusion portion160P may be a portion which is connected to the gate contact184in a post process. In the main gate portion160M, the connection protrusion portion160P may include a protrusion top surface160U at a first level LV1, and a peripheral portion of the connection protrusion portion160P of the main gate portion160M may include a recess top surface160L at a second level LV2which is lower than the first level LV1.

Referring toFIGS.29A to29C, the protrusion top surface160U of the connection protrusion portion160P may be exposed by removing the mask pattern MP3and the insulation mask162from a resultant material ofFIGS.28A to28C, and then, a capping insulation pattern164which covers the protrusion top surface160U and the recess top surface160L of the gate line160and a top surface of the gate dielectric layer152may be formed.

Referring toFIGS.30A to30C, a plurality of source/drain contact holes CAH which pass through the inter-gate insulation layer144and the insulation liner142to expose the plurality of first and second source/drain regions SD1and SD2may be formed in the first device region RX1and the second device region RX2, and then, a plurality of metal silicide layers172covering the plurality of first and second source/drain regions SD1and SD2and a plurality of source/drain contacts174filling the plurality of source/drain contact holes CAH may be formed under the plurality of source/drain contact holes CAH. The plurality of source/drain contacts174may be formed to include a conductive barrier layer174A and a metal plug174B.

In embodiments, a process of forming a contact insulation spacer covering an inner sidewall of each of the plurality of source/drain contact holes CAH may be further formed before the plurality of source/drain contacts174. To form the contact insulation spacer, an insulation spacer layer conformally covering an inner wall of each of the plurality of source/drain contact holes CAH may be formed, and then, an anisotropic etching process may be performed on the insulation spacer layer so that the plurality of first and second source/drain regions SD1and SD2are exposed through the plurality of source/drain contact holes CAH. As a result, the plurality of contact insulation spacers may remain on sidewalls of the plurality of source/drain contact holes CAH. In this case, the plurality of source/drain contacts174may be formed in a space, limited by the plurality of contact insulation spacers, of an inner space of the source/drain contact hole CAH.

In embodiments, the following processes may be performed for forming the metal silicide layer172and the plurality of source/drain contacts174. First, a metal liner conformally covering the plurality of first and second source/drain regions SD1and SD2may be formed in the plurality of source/drain contact holes CAH. The metal liner may include Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, Pd, or a combination thereof. Subsequently, a conductive barrier layer174A which covers an exposed surface of the metal liner and the inner walls of the plurality of source/drain contact holes CAH may be formed. The metal liner and the conductive barrier layer174A may be formed by using a CVD process, an ALD process, or a physical vapor deposition (PVD) process. Subsequently, by performing thermal treatment on a resultant material in which the metal liner and the conductive barrier layer174A are formed, a reaction between a semiconductor material of the plurality of first and second source/drain regions SD1and SD2and a metal material of the metal liner may be induced, and thus, a plurality of metal silicide layers172covering the plurality of first and second source/drain regions SD1and SD2may be formed. In embodiments, after the metal silicide layer172is formed, a portion of the metal liner may remain between the metal silicide layer172and the conductive barrier layer174A. In embodiments, all of the metal liner may be used to form the metal silicide layer172while the metal silicide layer172is being formed, and thus, the metal liner may not remain between the metal silicide layer172and the conductive barrier layer174A.

A metal layer having a thickness sufficient to fill an inner portion of each of the plurality of source/drain contact holes CAH may be formed on a resultant material in which the metal silicide layer172and the conductive barrier layer174A are formed. A CVD process, a PVD process, or an electroplating process may be used for forming the metal layer. Subsequently, undesired portions of the conductive barrier layer174A and the metal layer may be removed through a chemical mechanical polishing (CMP) process so that a top surface of the inter-gate insulation layer144is exposed, and thus, a metal plug174B including the metal layer remaining on the conductive barrier layer174A may be formed in each of the plurality of source/drain contact holes CAH.

Subsequently, an etch stop layer covering a top surface of a resultant material in which the plurality of source/drain contacts174are formed may be formed, and then, a plurality of local mask patterns covering partial regions of the plurality of source/drain contacts174may be formed on the etch stop layer. The etch stop layer and the plurality of local mask patterns may include different materials. In embodiments, the etch stop layer may include SiOC, SiN, or a combination thereof and the plurality of local mask patterns may include a silicon oxide layer, a spin on hardmask (SOH) layer, a photoresist layer, or a combination thereof, but the inventive concept is not limited thereto.

By using the plurality of local mask patterns as an etch mask, heights of partial regions of the plurality of source/drain contacts174may be lowered by etching a partial region of each of the etch stop layer and the source/drain contact174. As a result, the plurality of source/drain contacts174may have different heights based on positions. Each of the plurality of source/drain contacts174may be formed to include a first segment S1and a second segment S2, which have different heights and are connected to each other as one body in a vertical direction (a Z direction). A height of a top surface of the second segment S2may be lower than a top surface of the first segment S1. The first segment S1and the second segment S2each included in one source/drain contact174may be disposed on a straight line in a second horizontal direction (a Y direction).

The plurality of source/drain contacts174including the first segment S1and the second segment S2may be formed, and then, a buried insulation layer176may fill a space remaining on the second segment S2. A top surface of each of the buried insulation layer176, the first segment S1of the source/drain contact174, and the inter-gate insulation layer144may extend to be flat at the same level.

Referring toFIGS.31A to31C, a gate contact hole CBH exposing a top surface of the connection protrusion portion160P included in the main gate portion160M of the gate line160may be formed by etching a partial region of a capping insulation pattern164in a resultant material ofFIGS.30A to30C, and a gate contact184filling the gate contact hole CBH may be formed. The gate contact184may be formed to include a conductive barrier layer184A and a metal plug184B. The conductive barrier layer184A and the metal plug184B may be formed by a method similar to a method of forming the conductive barrier layer174A and the metal plug174B of the source/drain contact174described above with reference toFIGS.30A to30C.

Subsequently, as illustrated inFIGS.2A to2D, an insulation structure190may be formed on a resultant material in which the source/drain contact174and the gate contact184are formed. The insulation structure190may include an etch stop layer190A and an interlayer insulation layer190B. Subsequently, a plurality of source/drain via contacts192which pass through the insulations structure190and are connected to the first segments S1of the plurality of source/drain contacts174and a gate via contact194which passes through the insulation structure190and is connected to the gate contact184may be formed. The plurality of source/drain via contacts192may include a conductive barrier layer192A and a metal plug192B. The gate via contact194may include a conductive barrier layer194A and a metal plug194B. The conductive barrier layers192A and194A and the metal plugs192B and194B may be formed by a method similar to the method of forming the conductive barrier layer174A and the metal plug174B of the source/drain contact174described above with reference toFIGS.30A to30C.

In embodiments, the plurality of source/drain via contacts192and the gate via contact194may be sequentially formed. In this case, the plurality of source/drain via contacts192may be first formed and then the gate via contact194may be formed, or the gate via contact194may be first formed and then the plurality of source/drain via contacts192may be formed. In other embodiments, the plurality of source/drain via contacts192and the gate via contact194may be simultaneously formed.

Hereinabove, the method of manufacturing the integrated circuit device100illustrated inFIGS.1and2A to2Dhas been described above with reference toFIGS.21A to31C, but is not limited thereto and it may be easily understood by those of ordinary skill in the art that the integrated circuit devices100A,100B,100C,100D,100E,200,200A,200B,200C,300,400,400A,400B,500,600A,600B,600C,700, and800illustrated inFIGS.3A to20Band various integrated circuit devices having a structure similar thereto are manufactured by performing various modifications and changes from the descriptions ofFIGS.11A to21Cwithin the scope of the inventive concept.

In the method of manufacturing the integrated circuit device100described above with reference toFIGS.21A to31C, an example in which three nanosheets N1to N3are formed in a process described above with reference toFIGS.21A to21C, but the inventive concept is not limited thereto. For example, four nanosheets overlapping one another in a vertical direction (a Z direction) may be formed in a process described above with reference toFIGS.21A to21C, and then, the integrated circuit devices100A,100B,100C,100D,100E,200,200A,200B,200C,300,400,400A,400B,500,600A,600B,600C,700, and800illustrated inFIGS.3A to20Band various integrated circuit devices having a structure similar thereto may be manufactured by performing various modifications and changes on processes of forming the gate line160including the connection protrusion portion160P as described above with reference toFIGS.27A to28C, within the scope of the inventive concept.

While the inventive concept has been shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.