Patent ID: 12206022

DETAILED DESCRIPTION

Hereinafter, example embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The disclosure may, however, be exemplified in many different forms and should not be construed as being limited to the specific example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the drawings, the shapes and dimensions of elements may be exaggerated for clarity, and the same reference numerals will be used throughout to designate the same or like elements.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” to another element, it can be directly connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between”, “adjacent” versus “directly adjacent”, etc.).

Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. The thickness of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” “comprising,” “includes”, “including”, “have” and/or “having (and variants thereof) when used herein, specify the presence of stated elements or steps but do not preclude the presence or addition of one or more other elements or steps.

FIGS.1and2are a plan view and a perspective view, respectively, illustrating a semiconductor device according to example embodiments of the present inventive concepts.FIGS.3A and3Bare cross-sectional views taken along line A-A′ and line B-B′ of a semiconductor device ofFIG.2. For convenience of description,FIG.1illustrates only the major configuring elements, andFIG.2is illustrated omitting first and second interlayer insulating layers162and164.

Referring toFIGS.1to3B, a semiconductor device100may include a substrate101, active fins105, source/drain regions110, a gate structure140, contact plugs170F and170S, and wiring lines180F and180S. The semiconductor device100may further include isolation layers107and first and second interlayer insulating layers162and164.

The semiconductor device100in the example embodiment of the present inventive concepts may be provided as a FinFET with the active fins105having a fin structure.

The substrate101may have an upper surface extending in x and y directions. The substrate101may include a semiconductor material such as a group IV semiconductor material, a group III-V compound semiconductor material and/or a group II-VI semiconductor material. For example, a group IV semiconductor material may include silicon, germanium and/or silicon-germanium. The substrate101may be provided as a bulk wafer, an epitaxial layer, a Silicon-on-Insulator (SOI) layer, a Semiconductor-on-Insulator (SeOI) layer, or the like.

The isolation layers107may define the active fins105in the substrate101. The isolation layers107may contain an insulating material. The isolation layers107may be, for example, formed by a shallow trench element isolation (STI) process. The isolation layers107may be, for example, oxides, nitrides, or combinations thereof.

The active fins105may be defined by the isolation layers107in the substrate101, and may be disposed to be extended in a first direction, for example, in the y-direction. The active fins105may have an active fin structure protruding from the substrate101. The active fins105may be formed by a portion of the substrate101and may include an epitaxial layer grown from the substrate101. However, on both sides of the gate structure140, the active fins105on the substrate101may be partially removed and the source/drain regions110may be disposed.

The source/drain regions110may be disposed on the active fins105on both sides of the gate structure140. The source/drain regions110may be provided as source regions or drain regions of the semiconductor device100. The source/drain regions110may be in an elevated source/drain form in which the upper surface thereof is located higher than the lower surface of the gate structure140. In the example embodiment of the present inventive concepts, the source/drain regions110are illustrated in a pentagonal shape, but the source/drain regions110may have various shapes such as any one of a polygonal, circular, or rectangular shape. Further, in the example embodiment of the present inventive concepts, the source/drain regions110are illustrated as having a structure of being connected to each other or merged together on the three active fins105, but are not limited thereto. The source/drain regions110may include, for example, silicon and/or silicon germanium (SiGe).

The gate structure140may be disposed so as to intersect the active fins105on the upper portion of the active fins105, and may include a gate insulating layer142, first and second gate electrodes145and147, and a spacer144.

The gate insulating layer142may be disposed between the active fins105and the first and second gate electrodes145and147. The gate insulating layer142may include an oxide, a nitride and/or a high-k dielectric (high-k) material. The high-k material may indicate a dielectric material having a higher dielectric constant than that of silicon dioxide (SiO2). The high-k material may be, for example, any one or more of aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSixOy), hafnium oxide (HfO2), hafnium silicon oxide (HfSixOy), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlxOy), hafnium lanthanum oxides (LaHfxOy), hafnium aluminum oxide (HfAlxOy), or praseodymium oxide (Pr2O3). In another example embodiment of the present inventive concepts, the gate insulating layer142may be formed only on a lower portion of the first and second gate electrodes145and147.

The first and second gate electrodes145and147may be sequentially disposed on the gate insulating layer142. When the semiconductor device100is a transistor, a channel region may be formed in the active fins105intersecting the first and second gate electrodes145and147. The first and second gate electrodes145and147may be formed of different materials from each other. The first gate electrode145may include, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN) and/or tungsten nitride (WN). The second gate electrode147may include, for example, a metal material such as aluminum (Al), tungsten (W), molybdenum (Mo) and/or the like, and/or a semiconductor material such as doped polysilicon. The first gate electrode145may serve as a diffusion barrier layer for the second gate electrode147, but is not limited thereto. In another example embodiment of the present inventive concepts, the gate electrode may be formed of a single layer.

The spacer144may be disposed on the gate insulating layer142on both sides of the first and second gate electrodes145and147. The spacer144may isolate the source/drain regions110from the first and second gate electrodes145and147. The spacer144may be formed using an oxide, a nitride, or an oxynitride, and may also be configured of a multilayer film.

The contact plugs170F and170S may be disposed on the source/drain regions110, and may electrically connect the source/drain regions110and the wiring lines180F and180S. The contact plugs170F and170S may penetrate the first and second interlayer insulating layers162and164, but are not limited thereto.

Referring toFIG.1, one ends of the contact plugs170F and170S may be extended outwardly by a first length L1 from one ends of the source/drain regions110, respectively. The other ends of the contact plugs170F and170S may be extended by a second length L2, which is less than the first length L1, from the other ends of the source/drain region110, respectively. According to example embodiments of the present inventive concepts, the first and second lengths L1 and L2 may be changed in various ways. However, the first length L1 may be determined so that the contact plugs170F and170S may be connected to the wiring lines180F and180S located on one sides of the source/drain regions110, respectively.

The contact plugs170F and170S may have elongated shapes. For example, the contact plugs170F and170S may have a shape extending in an extended direction of the gate structure140, for example, in an x-direction, and may have a rectangular, an oval shape and/or the like. A third length L3, a length in a y direction, may be less than a fourth length L4, a length in the x-direction; for example, the fourth length L4 may be more than three times the third length L3.

Referring toFIGS.2and3A, both sides of the contact plugs170F and/or170S in the x-direction may have an asymmetric shape on the upper portion of the source/drain regions110. For example, the contact plug may have a vertical or an inclined side on the source/drain regions110, and the other side thereof may have a step portion ST having a step shape. As used herein, a “step portion” may refer to an area of a drastically differing width between a top portion and a bottom portion of the contact plugs extending in a single direction with different lengths. The step portion ST may be located outwardly of the source/drain regions110. The contact plugs170F and170S may be step-shaped in reverse toward the substrate101with a narrowing width toward the substrate101by the step portion ST of the example embodiment of the present inventive concepts. However, in the present specification, unless specified otherwise, the term “step-shaped” may be used to refer to all of a step shape and a step shape in reverse toward the substrate101. The step portions ST formed in the sides of the contact plugs170F and170S may be located in the side surfaces thereof provided in different directions with respect to each other. Thus, the contact plugs170F and170S may be stably coupled respectively to the wiring lines180F and180S. The contact plugs170F and170S may also be regarded as having at least one side that comprises a plurality of line segments LS, when viewed in cross-section.

The contact plugs170F and170S may include a first region on the source/drain regions110, and a second region having a width wider than the first region on the first region. At an interface of the first and second regions, a step surface SP in which the second region is extended to be longer than the first region by a fifth length L5 may be formed. The step surface SP may be located within the second interlayer insulating layer164, whereby a parasitic capacitance between the contact plugs170F and170S and the first and the second gate electrodes145and147may be significantly lessened. However, the location of the step surface SP is not limited thereto, and in an example embodiment of the present inventive concepts, the step surface SP may also be located within the first interlayer insulating layer162.

On sides of the contact plugs170F and170S having step portions (ST), the first region may have a side having a gradient of a first angle θ1 with respect to a direction perpendicular to the substrate101, and the second region may have a side having a gradient of a second angle θ2. The first and second angles θ1 and θ2 may be the same as or different from each other. The step portion ST may refer to a region including the step surface SP and upper and lower portions of the step surface SP perpendicular or inclined to the step surface SP. The step surface SP may be located outwardly of the source/drain regions110in the x-direction and may be parallel to the upper surface of the substrate101, or may have a gradient. The fifth length L5 may be determined in consideration of the distance between the source/drain regions110and the wiring lines180F and180S, and the gradient of the sides of the contact plugs170F and170S.

The contact plugs170F and170S may be on, and in some embodiments may cover, a portion of the upper surface of the source/drain regions110. For example, the contact plugs170F and170S may cover the entire upper surface of the source/drain regions110on a cross section in an x-z direction as inFIG.3A. Further, the contact plugs170F and170S may cover at least portions of the upper and side surfaces of the source/drain regions110. In the example embodiment of the present inventive concepts, the contact plugs170F and170S may cover at least two surfaces of the respective pentagonal areas forming the source/drain regions110. The contact plugs170F and170S may be spaced apart by first and second distances D1 and D2 respectively from both ends of the source/drain regions110, but are not limited thereto. The first and second distances D1 and D2 may be the same as or different from each other, or may be zero. In another example embodiment of the present inventive concepts, the contact plugs170F and170S may cover the end portions of the source/drain regions110and may be extended to the lower portion thereof.

The contact plugs170F and170S may include a barrier layer BM and a conductive layer CM. The barrier layer BM may function as a diffusion barrier layer on a metal material forming the conductive layer CM. The barrier layer BM may be formed along the upper portion of the source/drain regions110, the side walls of the contact plugs170F and170S, and the step surface SP. The barrier layer BM may include, for example, at least one metal nitride among titanium nitride (TiN), tantalum nitride (TaN) and/or tungsten nitride film (WN). The conductive layer CM may include a conductive material such as aluminum (Al), copper (Cu), tungsten (W) and/or molybdenum (Mo).

The first and second interlayer insulating layers162and164may be disposed on, and in some embodiments to cover, the substrate101, the source/drain regions110, and the gate structure140. A height H1 of the first interlayer insulating layer162may be substantially the same as a height of the gate structure140. However, as the first and second interlayer insulating layers162and164may be layers formed in the different process steps, relative heights and relative locations thereof with respect to the step surface SP are not limited to those illustrated in the drawings. In another example embodiment of the present inventive concepts, the first and second interlayer insulating layers162and164may be formed of a single layer. The first and second interlayer insulating layers162and164may be formed of an insulating material, and may include at least one of an oxide film, a nitride film, and/or an oxynitride film. For example, the first interlayer insulating layer162may be provided as a tonen silazene (TOZ) film, and the second interlayer insulating layer164may be a tetraethyl ortho silicate (TEOS) film.

The wiring lines180F and180S may be disposed to be connected to the contact plugs170F and170S. Referring toFIGS.1and3A, the wiring lines180F and180S may be located on upper portions of one side of the contact plugs170F and170S, and may be contacted therewith by a sixth length L6. The sixth length L6 may be determined in consideration of the third length L3, which is the width of the contact plugs170F and170S, the resistance of the contact plugs170F and170S, and the like. The wiring lines180F and180S may include a conductive material such as aluminum (Al), copper (Cu) and/or tungsten (W), and the like.

FIGS.4to7are cross-sectional views illustrating a semiconductor device according to example embodiments of the present inventive concepts.FIGS.4to7illustrate cross sections corresponding toFIG.3A.

Referring toFIG.4, a semiconductor device100amay include a substrate101, active fins105, source/drain regions110, a gate structure140, a contact plug170Fa, and a wiring line180F. The semiconductor device100amay further include isolation layers107, and an interlayer insulating layer160.

The contact plug170Fa may be disposed on the source/drain regions110, and may electrically connect the source/drain regions110and the wiring line180F. The contact plug170Fa may penetrate the interlayer insulating layer160. In example embodiments of the present inventive concepts below, the contact plug170Fa is illustrated in a simplified form, but as in the example embodiments of the present inventive concepts inFIGS.3to4B, the contact plug170Fa may include a barrier layer BM, and a conductive layer CM.

In the semiconductor device100ain the example embodiment of the present inventive concepts, both sides of the contact plug170Fa of on the upper portion of the source/drain regions110may have step portions STa and STb having a step shape. Both sides of the contact plug170Fa may be step-shaped in reverse toward the substrate101, by the step portions STa and STb.

The step portions STa and STb may be located outwardly of the source/drain regions110. The step portions STa and STb may have the same shape as each other or have different shapes. For example, in the step portions STa and STb, the length of step surfaces SPa and SPb, and the gradients of the sides of the contact plug170Fa on the upper and lower portions of the step surfaces SPa and SPb may be the same as or different from each other. The contact plug170Fa may also be regarded as having at least one side that comprises a plurality of line segments LS, when viewed in cross-section.

The wiring line180F is illustrated as being connected to the contact plug170Fa only on one side of the contact plug170Fa, but is not limited thereto. For example, an additional wiring line180F may be disposed on the right side of the contact plug170Fa.

Referring toFIG.5, a semiconductor device100bmay include a substrate101, active fins105, source/drain regions110, a gate structure140, a contact plug170Fb, and a wiring line180F. The semiconductor device100bmay further include isolation layers107and an interlayer insulating layer160.

In the semiconductor device100bin the example embodiment of the present inventive concepts, both sides of the contact plug170Fb on the upper portion of the source/drain regions110may have step portions STa and STc having a step shape. Of the step portions STa and STc, the step portion STa on the left side inFIG.5may be formed so that a width of the contact plug170Fb may widen toward the upper portion thereof in the z direction, and the step portion STc on the right side inFIG.5may be formed so that a width thereof may narrow. Thus, the left side of the contact plug170Fb may be step-shaped in reverse toward the substrate101, and the right side thereof may be step-shaped by the step portions STa and STc. The step portion STa on the left side of the contact plug170Fb may be located outwardly of the source/drain regions110, and the step portion STc on the right side may be located above the source/drain regions110. Lengths of the step surfaces SPa and SPc may be the same or different from each other. For example, the length of the step surface SPc on the right side may be greater than the length of the step surface SPa on the left side.

In the example embodiment of the present inventive concepts, the step portions STa and STc may be formed on the left and right sides of the contact plug170Fb as described above in a direction of expanding and a direction of decreasing the width of the contact plug170Fb respectively, allowing for a volume and a cross-sectional area of a plane in x-z directions of the contact plug170Fb to be reduced. Since the cross-sectional area of the plane in x-z directions of the contact plug170Fb decreases, a parasitic capacitance between the contact plug170Fb and the first and second gate electrodes145and147(seeFIG.2) may be reduced. The contact plug170Fb may also be regarded as having at least one side that comprises a plurality of line segments LS, when viewed in cross-section.

The wiring line180F may be connected to the contact plug170Fb on the upper portion of the step portion STa on the left side.

Referring toFIG.6, a semiconductor device100cmay include a substrate101, active fins105, source/drain regions110, a gate structure140, a contact plug170Fc, and a wiring line180F. The semiconductor device100cmay further include isolation layers107and an interlayer insulating layer160.

In the semiconductor device100cin the example embodiment of the present inventive concepts, both sides of the contact plug170Fc on the upper portion of the source/drain regions110may have step portions STd1, STd2, STe1, and STe2 having a step shape, respectively. A plurality of step portions STd1, STd2, STe1, and STe2 may be formed on a single side of the contact plug170Fc. The step portions STd1 and STd2 on the left side of the contact plug170Fc may be formed so that the width of the contact plug170Fc may widen toward the upper portion in the z direction, and the step portions STe1 and STe2 on the right side may be formed so that the width thereof may narrow. Thus, the step portions STd1 and STd2 on the left side may be located outwardly of the source/drain regions110, and the step portions STe1 and STe2 on the right side may be located above the source/drain regions110. The length of the step surfaces may be the same or different from each other. The contact plug170Fc may also be regarded as having at least one side that comprises a plurality of line segments LS, when viewed in cross-section.

The example embodiment of the present inventive concepts illustrates two step portions STd1, STd2, Ste1, and Ste2 being formed on the left side and the right side of the contact plug170Fc, respectively, but the number of step portions is not limited thereto, and may be selected in various ways. The numbers of the step portions STd1, STd2, Ste1, and Ste2 formed on the left side and the right side of the contact plug170Fc, respectively, may also be different from each other.

In the example embodiment of the present inventive concepts, a plurality of step portions STd1, STd2, Ste1, and Ste2 may be formed on the left and right sides of the contact plug170Fc, respectively, as described above, allowing a more detailed shape of the contact plug170Fc.

The wiring line180F may be connected to the contact plug170Fc on the upper portion of the step portions STd1 and STd2 on the left side of the contact plug170Fc.

Referring toFIG.7, a semiconductor device100dmay include a substrate101, active fins105, source/drain regions110, a gate structure140, a contact plug170Fd, and a wiring line180F. The semiconductor device100dmay further include isolation layers107and an interlayer insulating layer160.

In the semiconductor device100dof the example embodiment of the present inventive concepts, the maximum length L8 of the contact plug170Fd in an x direction may be shorter than the maximum length L7 of the source/drain regions110. One ends on the left side of the contact plug170Fd may be extended outwardly from one end of the source/drain regions110, and other ends on the right side of the contact plug170Fd may be located above the source drain regions110. Thus, the contact plug170Fd be on, and in some embodiments may cover, only a portion of the upper surface of the source/drain regions110. The contact plug170Fd may also be regarded as having at least one side that comprises a plurality of line segments LS, when viewed in cross-section.

In the example embodiment of the present inventive concepts, the contact plug170Fd may be formed on, and in some embodiments to cover, only a portion of the upper surface of the source/drain regions110as described above, allowing for a volume and a cross-sectional area in the plane x to z of the contact plug170Fd to be reduced. Thus, a parasitic capacitance between the contact plug170Fd and the first and second gate electrodes144and147(seeFIG.2) may be reduced. However, since resistance may increase according to the reduction of the volume of the contact plug170Fd, the size of the contact plug170Fd may be determined in consideration of the material of the contact plug170Fd and the desired contact resistance.

The contact plug170Fd may have step-shaped step portions STf and STg on both sides on the upper portion of the source/drain regions110. Of the step portions STf and STg, the step portion STf on the left side may be formed so that the width of the contact plug170Fd may widen toward the upper portion in the z direction, and the step portion STg on the right side may be formed so that the width may narrow. The length of the step surfaces may be the same or different from each other. In addition, the side of the contact plug170Fd may be perpendicular to the substrate101, forming step portions STf and STg in a perpendicular form. However, the example embodiment of the present inventive concepts is not limited thereto, and the side of the contact plug170Fd may be formed to have a desired gradient.

The wiring line180F may be connected to the contact plug170Fd on the upper portion of the step portion STf on the left side.

FIGS.8and9are perspective views illustrating a semiconductor device according to example embodiments of the present inventive concepts.

Referring toFIG.8, a semiconductor device100emay include a substrate101, active fins105, source/drain regions110a, a gate structure140, and contact plugs170Fe and170Se. The semiconductor device100dmay further include isolation layers107.

In the example embodiment of the present inventive concepts, the source/drain regions110aof the semiconductor device100emay have a hexagonal shape. The shape of the source/drain regions110amay be determined by a processing time and thickness or the like in a forming process of the source/drain regions110a. For example, in a case in which the source/drain regions110aare formed of an epitaxial layer, the source/drain regions110amay have a hexagonal shape by a crystal orientation and the like of the epitaxy as in the example embodiment of the present inventive concepts, or may have a pentagonal shape as illustrated inFIG.2.

The source/drain regions110amay be disposed to be spaced apart from each other on the two adjacent active fins105. The number of active fins105intersecting with a single gate structure140may be modified in various ways according to the example embodiment of the present inventive concepts.

The contact plugs170Fe and170Se may be disposed on the source/drain regions110a, and may electrically connect the source/drain regions110aand the wiring lines180F and180S (seeFIG.1). The two sides of the contact plugs170Fe and170Se in the x direction may have an asymmetric shape on an upper portion of the source/drain region110a. For example, one side may have a perpendicular or an inclined side with respect to the source/drain regions110a, and the other side may have a step-shaped step portion ST.

The contact plugs170Fe and170Se may be on, and in some embodiments may cover, at least portions of upper surfaces and sides of the source/drain regions110a. In the example embodiment of the present inventive concepts, the contact plugs170Fe and170Se may be on, and in some embodiments may cover, portions of the upper surface and the inclined sides of both sides of the upper surfaces in the respective hexagonal area of the source/drain regions110a. The lower surfaces of the contact plugs170Fe and170Se may be located at a second height H2 from the upper surface of the substrate101, between the upper portions of the source/drain regions110aadjacent to each other in the x direction. The second height H2 may be modified in various ways within a range of not coming into contact with the upper surface of the substrate101.

Referring toFIG.9, a semiconductor device100fmay include a substrate101, active fins105, a source/drain region110a, a gate structure140, and contact plugs170Ff and170Sf. The semiconductor device100fmay further include isolation layers107.

The source/drain region110amay have a hexagonal shape as in the example embodiment of the present inventive concepts ofFIG.8. In the example embodiment of the present inventive concepts, the semiconductor device100fmay include only one active fin105, and the source/drain region110amay be disposed on the active fin105. The contact plugs170Ff and170Sf may be on, and in some embodiments may cover, a portion of the upper surface and the inclined sides of both sides of the upper surfaces of the source/drain region110a.

FIGS.10to22Bare views illustrating a process sequence to illustrate a method of manufacturing a semiconductor device according to example embodiments of the present inventive concepts.

Referring toFIG.10, trenches TI defining active fins105may be formed by patterning a substrate101.

First, a pad oxide pattern122and a mask pattern124may be formed on the substrate101. The pad oxide pattern122may be a layer protecting the upper surface of the active fins105, and may be omitted according to an example embodiment of the present inventive concepts. The mask pattern124may be a mask layer patterning the substrate101, and may include silicon nitride and/or a carbon-containing material, and the like. The mask pattern124may be formed of a multi-layer structure.

The trenches TI may be formed by anisotropic etching of the substrate100using the pad oxide pattern122and the mask pattern124. Since the trenches TI may have high aspect ratios, widths thereof may gradually narrow toward the lower portion; thereby, the active fins105may have a shape of narrowing towards the upper portion thereof.

Referring toFIG.11, an isolation layer107in, and in some embodiments filling, the trenches TI may be formed.

First, processes of filling the trenches TI with an insulating material and planarization may be performed. At least portions of the pad oxide pattern122and the mask pattern124may be removed during the planarization process. In another example embodiment of the present inventive concepts, the trenches TI may be filled after first forming a relatively thin liner layer within the trenches TI.

Next, by removing a portion of the insulating material for filling the trenches TI, a process of projecting the active fins105from the substrate101may be performed. This process may be performed, for example, as a wet etching process using at least a portion of the pad oxide pattern as an etching mask. As a result, the active fins105may be projected by a height H3 toward the upper portion, and the projecting height H3 may be modified in various ways. During the etching process, the pad oxide pattern122may also be removed.

Referring toFIG.12, a dummy gate insulating layer132and a dummy gate electrode135extended by intersecting active fins105may be formed.

The dummy gate insulating layer132and the dummy gate electrode135may be formed, for example, by performing an etching process using a mask pattern layer136.

The dummy gate insulating layer132and the dummy gate electrode135may be formed on a region where the gate insulating layer142and the first and second gate electrodes145and147(seeFIG.2) are to be formed, and may be removed during a subsequent process. For example, the dummy gate insulating layer132may include silicon oxide, and the dummy gate electrode135may include polysilicon.

Referring toFIG.13, a spacer144may be formed on both sides of a dummy gate insulating layer132, a dummy gate electrode135, and a mask pattern layer136. Next, active fins105on both sides of the spacer144may be selectively removed.

The spacer144may be formed by forming a film having a uniform thickness on the upper portion of the dummy gate insulating layer132, the dummy gate electrode135, and the mask pattern layer136, and by anisotropically etching of the film.

Recesses may be formed by removing the active fins105from both sides of the spacer144. The recesses may be formed by etching portions of the active fins105by forming a separate masking layer or using the mask pattern layer136and the spacer144as a mask. The recess may be formed, for example, by sequentially applying a dry etching process and a wet etching process thereto. Selectively, after the formation of the recesses, a process of curing the surfaces of the recessed active fins105may be performed by a separate process. In the example embodiment of the present inventive concepts, the upper surfaces of the recessed active fins105are illustrated as being at the same level as the upper surface of the isolation layer107, but are not limited thereto. In another example embodiment of the present inventive concepts, the upper surface of the recessed active fins105may be higher or lower than the upper surface of the isolation layer107.

Before or after the formation of the recesses, a process of implanting impurities in the active fins105on both sides of the dummy gate electrode135may be performed. The process of implanting impurities may be performed using the mask pattern layer136and the spacer144as a mask.

Referring toFIG.14, a source/drain region110may be formed on recessed active fins105on both sides of the spacer144.

The source/drain region110may be formed, for example, using a selective epitaxial growth (SEG) process. The source/drain region110may have a pentagonal or a hexagonal shape as illustrated by growing along a crystallographically stable surface in a growth process. However, the size and shape of the source/drain region110are not limited to the illustration.

The source/drain region110may be, for example, a silicon germanium (SiGe) layer. In a case in which SiGe is grown on active fins105formed of silicon (Si), compressive stress may be generated in a channel region of the semiconductor device. Such a compressive stress may be increased as a concentration of germanium (Ge) increases. In some example embodiments of the present inventive concepts, the concentration of Ge within the source/drain region110may be formed differently according to the height.

The source/drain region110may contain impurities. The impurities may be contained by in-situ implantation of ions during growth of the source/drain region110and/or by a separate implantation of ions after growth. The grown source/drain region110may be provided as a source region or a drain region of the semiconductor device.

Referring toFIG.15, a first interlayer insulating layer162may be formed on a source/drain region110.

The first interlayer insulating layer162may be formed by forming a layer on, and in some embodiments covering, a mask pattern layer136, a spacer144, and a source/drain region110with an insulating material, and by allowing the upper surface of a dummy gate electrode135to be exposed through a planarization process. Thus, the mask pattern layer136may be removed during this process.

The first interlayer insulating layer162may include, for example, at least one oxide, nitride and/or oxynitride.

Referring toFIG.16, a dummy gate insulating layer132and a dummy gate electrode135may be removed.

The dummy gate insulating layer132and the dummy gate electrode135may be selectively removed with respect to an isolation layer107and active fins105of the lower portion, and an opening E exposing the isolation layer107and the active fins105may be formed.

The removal process of the dummy gate insulating layer132and the dummy gate electrode135may be through at least one of a dry etching process and/or a wet etching process.

Referring toFIG.17, a gate structure140may be formed by forming a gate insulating layer142and first and second gate electrodes145and147within the opening E.

The gate insulating layer142may be formed substantially in a conformal manner along the sidewalls and the lower surface of the opening E. The gate insulating layer142may include an oxide, a nitride and/or a high-k material.

The first and second gate electrodes145and147may include a metal or a semiconductor material.

FIGS.18A to22Billustrate a perspective view along with a cross section cut along line X-X′.

Referring toFIGS.18A and18B, a second interlayer insulating layer164on, and in some embodiments covering, the first and second gate electrodes145and147and a source/drain region110, and a first mask layer192having a first open region P1, may be formed.

The second interlayer insulating layer164may include, for example, at least one oxide, nitride and/or oxynitride. The second interlayer insulating layer164may be formed of the same material as the first interlayer insulating layer162.

The first mask layer192may be a layer for patterning the first and second insulating layers162and164. The first mask layer192may be, for example, a photoresist layer. The first mask layer192may expose the second interlayer insulating layer164through a first open region P1. The length of the first open region P1 in an extending direction of the first and second gate electrodes145and147may be shorter than a length L4 (seeFIG.1), the length of the contact plugs170F and170S.

Referring toFIGS.19A and19B, first and the second interlayer insulating layers162and164may be patterned using the first mask layer192.

A first etching region OP1 may be formed by removing the second interlayer insulating layer164exposed through the first open region P1, and removing the first interlayer insulating layer162exposed after removing the second interlayer insulating layer164.

The first etching region OP1 may be formed to have a predetermined depth D3 from the upper surface of the second interlayer insulating layer164. The depth D3 of the first etching region OP1 may be less than the depth to the source/drain region110, but is not limited thereto, and may be modified in various ways.

Referring toFIGS.20A and20B, a second mask layer194having a second open region P2 may be formed.

The second mask layer194may be a layer for patterning the first and second interlayer insulating layers162and164. The second mask layer194may be, for example, a photoresist layer. The second mask layer194may expose portions of the first etching region OP1 and the second interlayer insulating layer164adjacent to the first etching region OP1 through the second open region P2. The length of the second open region P2 in an extending direction of the first and second gate electrodes145and147may be substantially the same as the length L4 (seeFIG.1), the length of the contact plugs170F and170S.

In an example embodiment of the present inventive concepts, the second mask layer194may not be a layer separate from the above-mentioned first mask layer192with reference toFIGS.18A and18B, but may be a layer formed by enlarging the first open region P1 of the first mask layer192using a trimming process.

For example, the semiconductor device100aas described above with reference toFIG.4may be manufactured using such a trimming process. In this case, in the contact plug170Fa, the second region of the upper portion of the step surfaces Spa and SPb may have a width expanded also in the y-direction, not illustrated, further than the width of the first region of the lower portion. The semiconductor device100aof the example embodiment of the present inventive concepts inFIG.4, in this case, may be formed by adjusting the location and width of the second open region P2. In detail, the semiconductor device100ahaving step portions formed on both sides of the device as illustrated inFIG.4may be manufactured by the second open region P2 inFIG.20Bbeing formed to expose the second interlayer insulating layer164on the right side as well.

Referring toFIGS.21A and21B, first and second interlayer insulating layers162and164may be patterned using a second mask layer194.

A second etching region OP2 may be formed by removing the exposed first and second interlayer insulating layers162and164through a second open region P2. At least a portion of the upper and side surfaces of the source/drain region110may be exposed through the second etching region OP2. A portion of the exposed source/drain region110from the upper surface may be removed during an etching process, and a portion of the upper surface may have a curved surface from being etched as illustrated. The second etching region OP2 may be an expanded region of the first etching region OP1, and a step portion may be formed between the region where the first etching region OP1 was formed and the surrounding regions. The height of the step portion may vary depending on the relative etched depths in the first and the second etching regions OP1 and OP2.

In the example embodiment of the present inventive concepts, over-etching of the first interlayer insulating layer162to the sides of the source/drain region110during an etching process may be reduced or prevented, by sequentially forming the first and second etching regions OP1 and OP2 having different sizes from each other through two etching processes, compared to forming an opening exposing the upper surface of the source/drain region110in just one process. Therefore, since the etched depth may be easily adjusted, the contact plugs170F and170S may be controlled so that the depth thereof may not be formed unnecessarily deeply or extended to the substrate101in the rear.

Referring toFIGS.22A and22B, contact plugs170F and170S may be formed by providing a conductive material in, and in some embodiments filling, a second etching region OP2.

The contact plug170F, for convenience of explanation, may be distinguished as a first region170F1of the lower portion, and a second region170F2of the upper portion, based on the step portion. The step portion may be formed by the second region170F2being extended longer than the first region170F1from one side of the contact plug170F. In the formation of the contact plug170F, first, a barrier layer BM may be formed, and a conductive layer CM may be formed on the barrier layer BM. The contact plug170F may also be regarded as having at least one side that comprises a plurality of line segments LS, when viewed in cross-section.

Next, with reference toFIG.3A, wiring lines180F crossing one side of the contact plugs170F may be formed. By the step portion, the contact plugs170F may be stably connected to the wiring lines180F by being extended outwardly of the source/drain region110in one direction.

FIGS.23to26are views illustrating a process sequence to illustrate a method of manufacturing a semiconductor device according to example embodiments of the present inventive concepts.FIGS.23to26illustrate processes after the above-described processes with reference toFIGS.10to17.

Referring toFIG.23, a first mask layer192′ may be formed, and a first interlayer insulating layer162may be patterned using the first mask layer192′.

The first interlayer insulating layer162on the source/drain region110may be exposed by the first mask layer192′. Thus, a first etching region OP1′ may be formed by removing the exposed first interlayer insulating layer162. The source/drain region110may be exposed through the first etching region OP1′.

Referring toFIG.24, a first region170Fb1of the contact plug170Fb (seeFIG.5) may be formed by providing a conductive material in, and in some embodiments filling, a first etching region OP1′. The first region170Fb1may include a barrier layer BM and a conductive layer CM. The barrier layer BM may be formed first. Afterwards, the conductive layer CM may be formed, and the barrier layer BM may be formed again on the upper surface of the conductive layer CM.

Next, a second interlayer insulating layer164′ on, and in some embodiments covering, the first region170Fb1may be formed. As necessary, prior to the formation of the second interlayer insulating layer164′, a flattening process may be further performed.

Referring toFIG.25, a second interlayer insulating layer164′ may be patterned using a second mask layer194′.

A second etching region OP2′ may be formed by removing the second interlayer insulating layer164′ exposed by the second mask layer194′. The second etching region OP2′ may expose a first region170Fb1of the contact plug170Fb.

The second etching region OP2′ may expose a portion of the first region170Fb1, and may be formed to be shifted toward one direction based on a source/drain region110. In one example embodiment of the present inventive concepts, a barrier layer BM exposed through the second etching region OPT may also be at least partially removed.

Referring toFIG.26, a second region170Fb2of a contact plug170Fb may be formed by filling a second etching region OPT with a conductive material.

The second region170Fb2may include a barrier layer BM and a conductive layer CM. The barrier layer BM may be formed first, and the conductive layer CM may be formed afterwards. In detail, the barrier layer BM may be prevented from forming on the upper surface of a first region170Fb1where the second region170Fb2is formed, or may be removed after formation. However, the shape and disposition of the barrier layer BM are not limited thereto, and may be modified in various ways.

Thereby, a contact plug170Fb including the first and second regions170Fb1and170Fb2may be formed. Step portions may be formed on both sides of the contact plug170Fb above the source/drain region110. One of the step portions may be formed to narrow toward a substrate101, and the other may be formed to widen. The contact plug170Fb may also be regarded as having at least one side that comprises a plurality of line segments LS, when viewed in cross-section.

Next, with reference toFIG.5, a wiring line180F passing one side of the contact plug170Fb may be formed. The contact plug170F may be stably connected to the wiring line180F by being extended outwardly of the source/drain region110in one direction while securing a contact region with the source/drain region110by the step portions.

Using the above-mentioned manufacturing method with reference toFIGS.23to26, semiconductor devices100cand100dofFIGS.6and7of the example embodiment of the present inventive concepts may be manufactured. For example, the semiconductor device100cofFIG.6may be manufactured by carrying out the process described above with reference toFIGS.25and26once more. The semiconductor device100dofFIG.7may be manufactured by controlling an etching process so that the side surface thereof may be etched perpendicularly, and by adjusting an etching region during the formation of first and a second etching regions OP1′ and OPT.

FIGS.27to28Bare a top view and a cross-sectional view of a semiconductor device according to an example embodiment of the present inventive concepts.FIGS.28A and28Billustrate a section along lines A-A′ and B-B′ inFIG.27, respectively.

Referring toFIGS.27to28B, the semiconductor device200may include a substrate201, an active region205extending in a first direction, for example, an x-direction on the substrate201, source/drain regions210on the active region205, a gate structure240extending in a second direction, for example, a y-direction, and contact plugs270F and270S. The semiconductor device200may further include isolation layers207and an interlayer insulating layer260.

The semiconductor device200of the example embodiment of the present inventive concepts may be a planar transistor having a flat upper surface without the active region205being projected toward the gate structure240, unlike the semiconductor device100ofFIGS.1to3B.

The substrate201may have an upper surface extending in x and y directions. The substrate201may include a semiconductor material, such as a group IV semiconductor material, a group III-V compound semiconductor material, or a group II-IV oxide semiconductor material.

The isolation layers207may be formed of an insulating material. The isolation layers207may be formed of, for example, an oxide, a nitride, or a combination of both. The active area205may be defined by the isolation layers207in the substrate201. The active region205may be recessed and the source/drain regions210may be disposed on the side surface of the gate structure240.

The source/drain regions210may be disposed on the active region205from both sides of the gate structure240. The source/drain regions210may be in an elevated source/drain form in which the upper surface of the source/drain regions210is located higher than the lower surface of the gate structure240. The source/drain regions210may be provided as source/drain regions of the semiconductor device200. However, the source/drain regions210in the present inventive concepts are not limited to the elevated form, and in other example embodiments of the present inventive concepts, the source/drain regions210of the semiconductor device200may be formed as impurity regions within the active region205.

The gate structure240may disposed to intersect the active region205on the upper portion of the active region205, and may include a gate insulating layer242, a gate electrode245, and spacers244. The gate insulating layer242may be formed of an oxide, a nitride and/or an oxynitride. The gate electrode245may include a metal, a metal nitride and/or a doped polysilicon. The spacers244may be disposed on both sides of the gate electrode245. The spacer244may be formed of an oxide, a nitride, or an oxynitride, and may be formed of a multi-layer film.

An interlayer insulating layer260may be disposed on, and in some embodiments to cover, the substrate201, the source/drain regions210and the gate structure240. The interlayer insulating layer260may be formed of an insulating material, such as at least one of an oxide film, a nitride film, and an oxynitride film.

The contact plugs270F and270S may be disposed on the source/drain regions210, and may electrically connect the source/drain regions210and a wiring structure of the upper portion by penetrating the interlayer insulating layer260. One ends of the contact plugs270F and270S may be extended outwardly of the source/drain regions210by a predetermined length D4 in the y-direction from one ends of the source/drain regions210. The length D4 may be determined according to the disposition of the wiring structure. The contact plugs270F and270S, by such a structure, may be connected to the wiring structure which is spaced apart in the y-direction from the source/drain regions210.

The contact plugs270F and270S may have an extended shape in an extended direction of the gate structure240, for example, in the y-direction, and may have a rectangular shape, an oval shape, or the like. A ninth length L9, a length in the x direction, may be shorter than a tenth length L10, a length in the y-direction. For example, the tenth length L10 may be three times longer or more than the ninth length L9.

The two sides of the contact plugs270F and270S may have an asymmetric shape in the y-direction above the source/drain regions210. For example, one side of the contact plugs270F and270S may have a side perpendicular to the source/drain regions210, or may be continuously extended having a gradient, and another side of the contact plugs270F and270S may have a step-shaped step portion ST. The step portion ST may be located outwardly of the source/drain regions210. The step portion ST may include a step surface SP being perpendicular to the upper surface of the substrate201or having a gradient. The step surface SP may be located outwardly of the source/drain regions210in the y-direction. The contact plugs270F and270S may also be regarded as having at least one side that comprises a plurality of line segments LS, when viewed in cross-section.

The contact plugs270F and270S may be on, and in some embodiments cover, portions of the upper and side surfaces of the source/drain regions210. However, the example embodiment of the present inventive concepts is not limited thereto, and in other example embodiments of the present inventive concepts, the contact plugs270F and270S may be on, and in some embodiments may cover, only the upper surface of the source/drain regions210.

The contact plugs270F and270S may include a conductive material such as aluminum (Al), copper (Cu), tungsten (W) and/or the like.

FIG.29is a circuit diagram of an SRAM cell including a semiconductor device according to example embodiments of the present inventive concepts.

Referring toFIG.29, a cell in SRAM elements may include first and second drive transistors TN1 and TN2, first and second load transistors TP1 and TP2, and first and second access transistors TN3 and TN4. Here, a source of the first and second drive transistors TN1 and TN2 may be connected to a ground voltage line Vss, and a source of the first and second load transistors TP1 and TP2 may be connected to a power supply voltage line Vdd.

The first drive transistor TN1 including a NMOS transistor and the second load transistor TP1 including a PMOS transistor may provide a first inverter, and the second drive transistor TN2 including a NMOS transistor and the second load transistor TP2 including a PMOS transistor may provide a second inverter. The first and/or second drive transistors TN1 and/or TN2, the first and/or second load transistors TP1 and/or TP2, and/or the first and/or second access transistors TN3 and/or TN4 may include the semiconductor device according to various example embodiments of the present inventive concepts as described above with reference toFIGS.1to9andFIGS.27to28B.

An output terminal of the first and second inverters may be connected to the source of the first access transistor TN3 and the second access transistor TN4. Further, an input terminal and the output terminal of the first and second inverters may be connected by intersecting each other to configure a single latch circuit. Also, a drain of the first and second access transistors TN3 and TN4 may be connected to first and second bit lines BL and/BL, respectively.

FIG.30is a block diagram illustrating a storage device including a semiconductor device according to example embodiments of the present inventive concepts.

Referring toFIG.30, a storage device1000according to the example embodiment of the present inventive concepts may include a controller1010communicating with a host, and memories1020-1,1020-2, and1020-3storing data. Each memory1020-1,1020-2and/or1020-3, and/or the controller1010may include the semiconductor device according to various example embodiments of the present inventive concepts as described above with reference toFIGS.1to9andFIGS.27to28B.

The host communicating with the controller1010may be a variety of electronic devices provided with the storage device1000, for example, a smart phone, a digital camera, a desktop computer, a laptop computer, a media player, or the like. The controller1010may receive and store writing data or read requests transmitted from the host to the memories1020-1,1020-2, and1020-3, or may generate a command to retrieve data from the memories1020-1,1020-2, and1020-3.

As illustrated inFIG.30, one or more of the memories1020-1,1020-2, and1020-3may be connected in parallel to the controller1010in the storage device1000. By connecting a plurality of memories1020-1,1020-2, and1020-3in parallel to the controller1010, the storage device1000having a large capacity such as an SSD (Solid State Drive) may be realized.

FIG.31is a block diagram illustrating an electronic apparatus including a semiconductor device according to example embodiments of the present inventive concepts.

Referring toFIG.31, an electronic device2000, according to the example embodiment of the present inventive concepts, may include a communication unit2010, an input unit2020, an output unit2030, a memory2040, and a processor2050.

The communication unit2010may include a wired/wireless communication module, and a wireless internet module, a short-range communication module, a GPS module and/or a mobile communication module. The wired/wireless communication module included in the communication unit2010may transmit and receive data by being connected to an external communication network by a variety of communications standards.

The input unit2020is a module provided for the user to control operations of the electronic device2000, and may include a mechanical switch, a touch screen, a voice recognition module and/or the like. Further, the input unit2020may include a mouse operating in a trackball and/or a laser pointer method and the like and/or a finger mouse device, and may further include a variety of sensor modules allowing the user to input data.

The output unit2030may output information processed by the electronic device2000in the form of sound and/or video, and the memory2040may store a program for process and control of the processor2050, or data. The processor2050may store or retrieve data by transmitting a command to the memory2040according to the required action.

The memory2040may be provided in the electronic device2000or may communicate with the processor2050via a separate interface. When communicating with the processor2050via a separate interface, the processor2050may store or retrieve data from the memory2040via a variety of interface standards, such as SD, SDHC, SDXC, MICRO SD and/or USB.

The processor2050may control operations of each unit included in the electronic device2000. The processor2050may perform control and processes related to voice calling, video calling, data communications and/or the like, and/or may also perform control and processes for multimedia playback and management. Further, the processor2050may process input transmitted from the user via the input unit2020, and may output the results via the output unit2030. In addition, the processor2050, as previously described, may store data necessary in controlling the operation of the electronic device2000in the memory2040, or retrieve the data from the memory2040. The processor2050, the memory2040and/or any of the other units ofFIG.31may include the semiconductor device according to various example embodiments of the present inventive concepts as described above with reference toFIGS.1to9andFIGS.27to28B.

FIG.32is a schematic diagram illustrating a system including a semiconductor device according to example embodiments of the present inventive concepts.

Referring toFIG.32, a system3000may include a controller3100, an input/output device3200, a memory3300and an interface3400. The system3000may be a mobile system and/or a system transmitting and/or receiving information. The mobile system may be a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player and/or a memory card.

The controller3100may run a program and/or control the system3000. The controller3100may be, for example, a microprocessor, a digital signal processor, a microcontroller and/or a similar device.

The input/output device3200may be used to input or output data of the system3000. The system3000may be connected to an external device, such as a personal computer and/or a network using the input/output device3200, and may exchange data with the external device. The input/output device3200may be, for example, a keypad, a keyboard and/or a display device.

The memory3300may store a code and/or data for the operation of the controller3100, and/or may store data processed by the controller3100. The memory3300and/or any of the other blocks ofFIG.32may include the semiconductor device according to any one of the example embodiments of the present inventive concepts.

The interface3400may be a data transmission path between the system3000and other external devices. The interface3400may communicate with the controller3100, the input/output device3200, and the memory3300via a bus3500.

The controller3100, the memory3300and/or any of the other blocks ofFIG.32may include at least one of the semiconductor devices according to various example embodiments of the present inventive concepts as described above with reference toFIGS.1to9andFIGS.27to28B.

As set forth above, by forming step portions on sides of contact plugs, a semiconductor device may have improved degree of integration and reliability, and a method of manufacturing the same may also be provided.

While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present inventive concepts as defined by the appended claims.