Patent ID: 12224034

DESCRIPTION OF THE EMBODIMENTS

FIG.1is a schematic view of a memory device according to an embodiment of the disclosure Referring toFIG.1, a memory device100includes multiple memory cell string pairs MS1to MS2, multiple selection switch pairs formed by multiple selection switches SW1A, SW1B, SW2A, and SW2B, a sense amplifier120, and a page buffer110. The memory cell string pair MS1includes memory cell strings MS1A and MS1B. The memory cell strings MS1A and MS1B have selection switches SW1A and SW1B, respectively. The memory cell strings MS1A and MS1B are respectively coupled to the global bit line GBL through the selection switches SW1A and SW1B. The memory cell string pair MS2includes memory cell strings MS2A and MS2B. The memory cell strings MS2A and MS2B have selection switches SW2A and SW2B, respectively. The memory cell strings MS2A and MS2B are respectively coupled to the global bit line GBL through the selection switches SW2A and SW2B. The memory cell strings MS1A, MS1B, MS2A, and MS2B are coupled to a common source line CSL.

During the data searching operation, search data SB1and SB2with multiple bits may search in the memory device100time-divisionally or synchronizedly. Corresponding to the search data SB1, a pair of search data SSL1and SSL1B may be generated and provided to the control ends of the selection switches SW1A and SW1B, respectively. The search data SSL1may have the same logic value as the search data SB1, and the search data SSL1B may have a complementary logic value to the search data SSL1. In addition, corresponding to the search data SB2, a pair of search data SSL2and SSL2B may be generated and provided to the control ends of the selection switches SW2A and SW2B, respectively. The search data SSL2may have the same logic value as the search data SB2, and the search data SSL2B may have a complementary logic value to the search data SSL2.

During the data searching operation, in each of the memory cell strings MS1A, MS1B, MS2A, and MS2B, a read voltage may be received, for example, by using word lines WL1A, WL1B, WL2A, WL2B. In addition, in memory cell strings MS1A, MS1B, MS2A, and MS2B, memory cells respectively corresponding to the word lines WL1A, WL1B, WL2A, and WL2B are selected memory cells.

Taking memory cell strings MS1A and MS1B as examples, corresponding to the search data SB1with a logic value of 1, in response to the search data SSL1with a logic value of 1 and the search data SSL1B with a logic value of 0, if the selected memory cell in the memory cell string MS1A records a high logic level (H), and the selected memory cell in the memory cell string MS1B records a low logic level (L), the search result is a match, and the memory cell strings MS1A and MS1B do not generate current on the global bit line GBL. Corresponding to the search data SB1with a logic value of 1, if the selected memory cell in the memory cell string MS1A records a low logic level (L), and the selected memory cell in the memory cell string MS1B records a high logic level (H), the search result is not a match, and the memory cell string MS1A may generate current on the global bit line GBL.

On the other hand, corresponding to the search data SB1with a logic value of 0, in response to the search data SSL1with a logic value of 0 and the search data SSL1B with a logic value of 1, if the selected memory cell in the memory cell string MS1A records a high logic level (H), and the selected memory cell in the memory cell string MS1B records a low logic level (L), the search result is not a match, and the memory cell string MS1B may generate current on the global bit line GBL. Corresponding to the search data SB1with a logic value of 0, if the selected memory cell in the memory cell string MS1A records a low logic level (L), and the selected memory cell in the memory cell string MS1B records a high logic level (H), the search result is a match, and the memory cell strings MS1A and MS1B do not generate current on the global bit line GBL.

To further illustrate, during data searching operation, the sense amplifier120is used to measure a magnitude of the current on the global bit line GBL to obtain a similarity between the search data and data stored in the selected memory cell. The sense amplifier120may obtain a search result of the data searching operation by comparing the current on the global bit line GBL with one or more reference currents. In this embodiment, the memory device100may make multiple memory cell string pairs formed by memory cell strings MS1A, MS1B, MS2A, and MS2B perform a data searching operation to the search data with multiple bits time-divisionally or synchronizedly within a time interval. The sense amplifier120may correspondingly obtain multiple search results time-divisionally. The search results generated by the sense amplifier120may be transmitted to the page buffer110. The page buffer110may record the search results. Further, the page buffer110may generate similarity information by counting the obtained search results.

It should be noted, the sense amplifier120may set one or more reference currents corresponding to one or more similarities with different degrees, respectively, and obtains a data search result corresponding to one of the similarities by comparing the current on the global bit line GBL with the reference currents. Specifically, the sense amplifier120is configured to sense a magnitude of the current on the global bit line GBL to generate the data search result. That is, the sense amplifier120executes a sensing operation in analog type.

For example, in response to the sense amplifier120determining that the current of the global bit line GBL is smaller than a reference threshold corresponding to a similarity, the sense amplifier120may determine that the data searching result is a match and generate a search result such as a logic value of 0. The page buffer110may records a value of the similarity according to the data searching result of the sense amplifier120. The page buffer110may further obtain the similarity information between the search data and the data stored in the memory device100in the searching operation by accumulating multiple data searching results generated by the sense amplifier120within a certain time interval. In this embodiment, the smaller the value of the similarity information accumulated by the page buffer110is, the higher the similarity between the search data and the data stored in the memory device100is. In contrast, the greater the value of the similarity information accumulated by the page buffer110is, the lower the similarity between the search data and the data stored in the memory device100is.

In other embodiments of the disclosure, the page buffer110may also accumulate inverted search results generated by the sense amplifier120. In this case, the greater the value of the similarity information accumulated by the page buffer110is, the higher the similarity between the search data and the data stored in the memory device100is. In contrast, the smaller the value of the similarity information accumulated by the page buffer110is, the lower the similarity between the search data and the data stored in the memory device100is.

In the embodiment of present invention, by sharing the sense amplifiers and the page buffer110with a plurality of memory cell strings MS1to MS2, a dimension of the data search operation can be improved. Take number of the memory cell strings is 128 as example, by executing search operation on the128memory cell strings 16 times, the search operation with 128×16 (=2048) bits can be complete. Correspondingly, the page buffer110may set resisters with 4 bits to record the similarity information generated correspondingly. It is worth mentioned, by increasing the registers with one bit, the bit numbers of the similarity information recorded by the page buffer110may be doubled.

FIG.2AandFIG.2Bare schematic views of a memory device according to another embodiment of the disclosure, referring toFIG.2AandFIG.2B, a memory device200includes multiple memory cell string pairs MS1to MS2, multiple selection switch pairs formed by multiple selection switches SW1A, SW1B, SW2A, and SW2B, and a page buffer210. The memory cell string pair MS1includes memory cell strings MS1A and MA1B, and the memory cell string pair MS2includes memory cell strings MS2A and MA2B. The memory cell string MS1A, MA1B, MS2A, and MA2B are respectively coupled to the global bit line GBL through the selection switches SW1A, SW1B, SW2A, and SW2B. The selection switches SW1A and SW1B form a selection switch pair and receive a pair of search data SSL1and SSL1B, respectively. The selection switches SW2A and SW2B form another selection switch pair and receive a pair of search data SSL2and SSL2B, respectively.

In this embodiment, the memory cell strings MS1A and MA1B may first perform the data searching operation and search for the data stored in selected memory cells MC1A and MC1B based on the search data SB1. Based on the search data SB1having a logic value of 1, the search data SSL1may have a logic value of 1, and the search data SSL1B may have a logic value of 0. Taking the selected memory cells MC1A and MC1B storing high logic level (H) and low logic level (L) respectively as examples, the data searching operation of the memory cell strings MS1A and MA1B is a match, and the memory cell strings MS1A and MA1B do not generate current on the global bit line GBL.

Correspondingly, the search result with a logic value of 0 may be recorded in a first register in the page buffer210. In this embodiment, the page buffer210may have a second register and a third register. The second register may record an initial value (e.g., equal to a logic value of 1), and the page buffer210may generate a logic value recorded in the third register based on a logic operation. For example, the page buffer210may invert the logic value in the first register, and perform an AND operation with the logic value in the second register to generate the logic value recorded in the third register. In the case that the search result matches, the first register records a logic value of 0, and the page buffer210may calculate that the logic value recorded in the third register is a logic value of 1.

On the other hand, the page buffer210includes an adder211. The adder211may accumulate the logic values recorded in the third register in each searching operation, thereby generating similarity information. In response to the logic value recorded in the third register being the logic value of 1, the adder211may increase the similarity information by 1.

InFIG.2B, the memory cell strings MS2A and MA2B may execute the next data searching operation and search for the data stored in selected memory cells MC2A and MC2B based on the search data SB2.

Based on the search data SB2having a logic value of 0, the search data SSL2may have a logic value of 0, and the search data SSL2B may have a logic value of 1. Taking the selected memory cells MC2A and MC2B storing high logic level (H) and low logic level (L) respectively as examples, the data searching operation of the memory cell strings MS2A and MA2B is not a match, and the memory cell string MS2B generates current on the global bit line GBL.

Correspondingly, the search result with a logic value of 1 may be recorded in the first register in the page buffer210. In this embodiment, the second register may record the value recorded in the first register previously (equal to the logic value of 1), and the page buffer210may generate a logic value recorded in the third register based on the logic operation. For example, the page buffer210may invert the logic value in the first register, and perform an AND operation with the logic value in the second register to generate the logic value recorded in the third register. In the case that the search result matches, the first register records a logic value of 1, and the page buffer210may calculate that the logic value recorded in the third register is a logic value of 0.

In this embodiment, after the logic value recorded in the third register is recorded as a logic value of 0, the logic value recorded in the second register is set to a logic value of 0. Thus, in subsequent searching operations, the logic value recorded in the third register is always equal to the logic value of 0. Thus, in this embodiment, the logic value recorded in the third register may be a logic value of 1 only when all the search results match.

On the other hand, the adder211may continuously accumulate the logic values recorded in the third register in multiple searching operations, thereby generating the similarity information. In this embodiment, the greater the value of the similarity information calculated by the adder211is, the higher the similarity between the search data and the stored data in multiple data searching operations. In contrast, the lower the value of the similarity information calculated by the adder211is, the lower the similarity between the search data and the stored data in multiple data searching operations.

In other embodiments of the disclosure, the adder211may also accumulate inverted logic values recorded in the third register. Under such a circumstance, the lower the value of the similarity information calculated by the adder211is, the higher the similarity between the search data and the stored data in multiple data searching operations; the greater the value of the similarity information calculated by the adder211is, the lower the similarity between the search data and the stored data in multiple data searching operations.

In other embodiments of the disclosure, the adder211may not perform the accumulation for the logic values recorded in the third register. In contrast, the adder211may perform accumulation for the logic values recorded in the first register, or the inverted logic values recorded in the first register. After multiple accumulations, the adder211may record the generated multiple bits of addition result in multiple registers, thereby obtaining the similarity information. For example, four registers may be disposed in the page buffer210, and the adder211may generate similarity information ranging from0to15.

Please refer toFIG.3AandFIG.3B.FIG.3Ashows a relationship between currents on a global bit line and word line voltages generated by a memory cell string under different similarity information and with a large amount of memory cell strings.FIG.3Bis a schematic view of currents on a global bit line corresponding to different Hamming distance. The Hamming distance is the amount information of difference bits calculated by performing exclusive OR operation on the search data and the data stored in the memory cell. For example, in response to the search data being 10011011 in binary and the data stored in the memory cell being 01111001 in binary, the Hamming distance may be the sum of the exclusive OR operation between 10011011 and 01111001, which is, for example, equal to 4.

InFIG.3A, assuming that there are 128 memory cell strings on the global bit line, the normalized Hamming distance may be directly proportional to the current on the global bit line.

Corresponding to a position where the word line voltage is approximately equal to-1 volt, a distribution curve310has a 50% Hamming distance correspondingly, which may generate a current of about 170 nanoamperes on the global bit line; a distribution curve320has a 25% Hamming distance correspondingly, which may generate a current of about 95 nanoamperes on the global bit line.

The vertical axis ofFIG.3Bis the cumulative probability, and the horizontal axis is the currents on the global bit line. Curves331to335are schematic views of the current relationship on the global bit line that respectively correspond to different Hamming distances. The curves331to335correspond to the normalized Hamming distance of 0%, 12.5%, 25%, 37.5%, and 50%, respectively. In present embodiment, according to current distribution ranges corresponding to curves331to335, the memory device may set one or more reference currents corresponding to one or more similarities, respectively. Wherein, the similarities respectively correspond the Hamming distances in the figure. Take the curves331and332as an example, by setting the reference current to 30 nA, whether the normalized Hamming distance of the data search result larger than 0% can be determined.

It may be clearly seen fromFIG.3AandFIG.3Bthat under the condition of a sufficiently large amount of memory cell strings, the similarity of the search result of the data searching may be clearly judged by judging the current interval on the global bit line.

FIG.4is a schematic view of a memory device according to another embodiment of the disclosure, referring toFIG.4, the memory device400includes multiple memory cell string pairs

MS1and MS2, multiple selection switches SW1A, SW1B, SW2A, and SW2B, a drive circuit420, and a random number generator430. The memory cell string pair MS1includes the memory cell strings MS1A and MS1B, and the memory cell string pair MS2includes the memory cell strings MS2A and MS2B. The memory cell strings MS1A and MS1B are respectively coupled to a global bit line GBL1through the selection switches SW1A and SW1B, and the memory cell strings MS2A and MS2B are respectively coupled to the global bit line GBL1through the selection switches SW2A and SW2B. In this embodiment, the memory device400may have the rest of a global bit line GBL2, and the global bit line GBL2may also be coupled to multiple memory cell strings with the same structure as the memory cell strings MS1A, MS1B, MS2A, and MS2B. The memory cell strings MS1A, MS1B, MS2A, and MS2B on the global bit line GBL1may correspond to the memory cell strings on the global bit line GBL2, respectively, and are connected in parallel. The memory cell strings may share the same common source line CSL.

The drive circuit420is coupled to the selection switches SW1A, SW1B, SW2A, and SW2B and configured to generate the search data SSL1, SSL1B, SSL2, and SSL2B according to source data SBx. The source data SBx includes the search data SB1and SB2. In addition, the random number generator430is coupled to the drive circuit420for setting at least one of the search data pairs generated by the drive circuit420to be a wild card signal.

It is worth mentioning that in response to the search data pair being a wild card signal, the search data SSL1and SSL1B generated by the drive circuit420may both have a logic value of 0. That is, in response to the search data pair being a wild card signal, the search result of the corresponding memory cell strings (e.g., memory cell strings MS1A and MS1B) has to be a match, and current is not provided on the corresponding global bit line GBL1.

Please refer toFIG.5.FIG.5is a flowchart of a data approximation search method according to an embodiment of the disclosure. In step S510, the selection switch pairs receive multiple search data pairs, respectively. In step S520, multiple memory cell string pairs are coupled to a global bit line through the selection switch pairs, respectively. In step S530, each of the memory cell string pairs determines whether to provide current on the global bit line according to stored data of a selected memory cell pair and each of the search data pairs. In step S540, multiple search results are obtained time-divisionally according to the current on the global bit line. In addition, in step S550, the search results are recorded and similarity information is generated by accumulating the search results.

The implementation details of the above steps have been described in detail in the aforementioned embodiments, and will not be repeated here.

To sum up, the memory device of the disclosure provides multiple memory cell string pairs, and receives multiple search data pairs through the selection switch pairs, so as to perform data searching operation between the search data pairs and the stored data of the selected memory cell pair. The page buffer of the disclosure may record the search results generated by multiple data searching operations and generate similarity information by accumulating the search results generated time-divisionally.