Patent ID: 12261244

Description of Reference Signs: first conductivity semiconductor layer1; stress releasing layer3; V-shaped layer3; V-shaped groove301; multi-quantum well layer4; barrier layer401; potential well layer402; second conductivity semiconductor layer5; substrate6; buffer layer7; first electrode8; second electrode9.

DETAILED DESCRIPTION

Here, example embodiments will be described in detail, and examples thereof are shown in the accompanying drawings. In the following description, which refers to the drawings, the same numbers in different drawings represent the same or similarity elements unless otherwise represented. The embodiments described in the following example embodiments do not represent all the embodiments consistent with the present disclosure. On the contrary, they are merely examples of devices consistent with some aspects of the present disclosure as detailed in the appended claims.

The present embodiment provides a method of preparing an LED structure and an LED structure. As shown inFIG.1, the method of preparing the LED structure can include steps S100to S130.

At step S100, a stress releasing layer is grown on a first conductivity semiconductor layer, and a material of the stress releasing layer is a III-V group semiconductor material.

At step S110, a V-shaped layer is grown on the stress releasing layer during which V-shaped grooves are formed in the V-shaped layer under a control of the stress releasing layer.

At step S120, a multi-quantum well layer is grown to conformally cover a surface of the V-shaped layer away from the stress releasing layer.

At step S130, a second conductivity semiconductor layer is grown on a side of the multi-quantum well layer away from the first conductivity semiconductor layer, and a conductivity type of the second conductivity semiconductor layer is different from a conductivity type of the first conductivity semiconductor layer.

In the method of preparing the LED structure according to the embodiments of the present disclosure, as shown inFIG.2andFIG.3, stress releasing layer2causes a surface of V-shaped layer3to form V-shaped grooves301, and multi-quantum well layer4fills the V-shaped grooves301, by controlling a temperature change during the growth of the multi-quantum well layer4, material compositions of different potential well layers402located from bottom to top in the multi-quantum well layer4are changed, that is, the material compositions of different potential well layers402located from bottom to top in the multi-quantum well layer4are different; and the existence of the V-shaped grooves301can cause that carriers in the second conductivity semiconductor layer5are injected into the potential well layers402of the multi-quantum well layer4from sidewalls of the V-shaped grooves301, therefore, the light emitting wavelength of the LED structure is changed and a multi-wavelength LED structure is realized.

Steps of the method of preparing the LED structure in the embodiment of the present disclosure are described in detail below.

At step S100, the stress releasing layer is grown on the first conductivity semiconductor layer, and the material of the stress releasing layer is a III-V group semiconductor material.

As shown inFIG.2, the first conductivity semiconductor layer1can be formed on a substrate6. The substrate6can be one of a sapphire substrate, a silicon carbide substrate and a silicon substrate, which is not limited in this embodiment. In addition, before forming the first conductivity semiconductor layer1, a buffer layer7can also be formed on the substrate6in the embodiment. The first conductivity semiconductor layer1can be grown on the buffer layer7. The buffer layer7can be an intrinsic semiconductor layer, and a material of the buffer layer7can be U-type GaN or U-type AlInGaN, which is not limited in the embodiments of the present disclosure.

As shown inFIG.2, the first conductivity semiconductor layer1can be an n-type semiconductor layer. The material of the first conductivity semiconductor layer1can be a III-V group semiconductor material, such as, GaN. The first conductivity semiconductor layer1can be formed in a reaction chamber by Atomic Layer Deposition (ALD), or Chemical Vapor Deposition (CVD), or Molecular Beam Epitaxy (MBE), or Plasma Enhanced Chemical Vapor Deposition (PECVD), or Low Pressure Chemical Vapor Deposition (LPCVD), or Metal Organic Chemical Vapor Deposition (MOCVD), or a combination thereof.

As shown inFIG.2, the material of the stress releasing layer2can be a III-V group semiconductor material. The stress releasing layer2can be an intrinsic semiconductor layer, or a weak n-type semiconductor layer. A concentration of n-type carriers in the stress releasing layer2can be less than 5×1018/cm3, that is, a number of n-type carriers of the stress releasing layer2in per cubic centimeter is less than 5×1018. In some embodiments, the material of the stress releasing layer2can be InxGa1-xN, where 0.01≤x≤0.5, and further, 0.01≤x≤0.3. The growth process of the stress releasing layer2can refer to the growth process of the first conductivity semiconductor layer1. For example, taking the material of the stress releasing layer2being InxGa1-xN as an example, the growth method of the stress releasing layer2can include: simultaneously injecting Indium source, Gallium source, ammonia gas, and carrier gas into the reaction chamber to grow the stress releasing layer2. A ratio of an amount of substance for injecting the Indium source per unit time to an amount of substance for injecting the Gallium source can be x/1−x. An epitaxial growth temperature of the stress releasing layer2can range from 700° C. to 850° C., such as, 700° C., 720° C., 760° C., 780° C., 800° C., and so on. An epitaxial growth rate of the stress releasing layer2can range from 0.5 μm/h to 2 μm/h, such as, 0.5 μm/h, 1 μm/h, 1.5 μm/h, 2 μm/h, and so on. A thickness of the stress releasing layer2can range from 10 nm to 500 nm, such as, 10 nm, 200 nm, 400 nm, 500 nm, and so on. An Indium content of the stress releasing layer2changes gradually in a thickness direction of the stress releasing layer2, for example, the Indium content of the stress releasing layer2decreases gradually from bottom to top, or increases gradually from the bottom to the top. Since the Indium content of the stress releasing layer2changes gradually in the thickness direction of the stress releasing layer2, the forming process of the V-shaped grooves301during the growth of the V-shaped layer3can be controlled, and thus depths of the V-shaped grooves301can be controlled. A structure of the stress releasing layer2can be a multilayer superlattice structure.

At step S110, the V-shaped layer is grown on the stress releasing layer during which V-shaped grooves are formed in the V-shaped layer.

As shown inFIG.2, a material of the V-shaped layer3can be a III-V group compound. A structure of the V-shaped layer3can be a single-layer structure or a multi-layer structure, for example, a material of the single-layer structure can include InGaN, and the multi-layer structure can include InGaN layers and GaN layers that are alternately distributed. The V-shaped layer3can be doped with n-type ions to exhibit n-type conductivity. The growth process of the V-shaped layer3can refer to the growth process of the first conductivity semiconductor layer1. The V-shaped layer3is formed on the surface of the stress releasing layer2away from the first conductivity semiconductor layer1. Due to differences in the thermal expansion coefficient, lattice constant, and built-in stress between the V-shaped layer3and the stress releasing layer2, the V-shaped grooves301are formed on the surface of the V-shaped layer3away from the first conductivity semiconductor layer1. At least two of the V-shaped grooves301have different depths. In addition, one or more of the V-shaped grooves301can penetrate through a part of the V-shaped layer3in the thickness direction.

By adjusting the material composition of the stress releasing layer2, the concentration of n-type carriers in the stress releasing layer2and the epitaxial growth temperature of the stress releasing layer2, the V-shaped grooves301with a controllable number and size can be formed. In some embodiments, a density of the V-shaped grooves301with a smaller depth on the V-shaped layer3is positively correlated with the Indium content of the stress releasing layer2, that is, the greater the Indium content of the stress releasing layer2is, the greater the density of the V-shaped grooves301with the smaller depth on the V-shaped layer3is. A density of the V-shaped grooves301with a larger depth on the V-shaped layer3is positively correlated with the concentration of n-type carriers of the stress releasing layer2, that is, the greater the concentration of the n-type carriers of the stress releasing layer2is, the greater the density of the V-shaped grooves301with the larger depth on the V-shaped layer3is. The density of the V-shaped grooves301with the larger depth on the V-shaped layer3is positively correlated with the epitaxial growth temperature of the stress releasing layer2, that is, the greater the epitaxial growth temperature of the stress releasing layer2is, the greater the density of the V-shaped grooves301with the larger depth on the V-shaped layer3is. The Indium content can be a percentage of an amount of substance for Indium to a sum of amounts of substances for all positively charged elements in the stress releasing layer2. For example, the material of the stress releasing layer2can include InxGa1-xN, and the Indium content refers to the percentage of the amount of substance for Indium to a sum of amount of substance for Indium and amount of substance for Gallium. In the present disclosure, the V-shaped grooves301with a depth less than 3 nm can be determined as the V-shaped grooves301with the smaller depth, and the V-shaped groove301with a depth greater than or equal to 3 nm can be determined as the V-shaped groove301with the larger depth, the embodiments of the present disclosure are not particularly limited to this. A structure of the V-shaped layer3can be a multilayer superlattice structure.

In addition, before growing the V-shaped layer3, the method of preparing the LED structure further includes etching the stress releasing layer2to form V-shaped recesses on the stress releasing layer2. The V-shaped layer3can conformally cover the stress releasing layer2, and a region on the V-shaped layer3corresponding to the V-shaped recesses can form the V-shaped grooves301. Before etching the stress releasing layer2, a dislocation density of the stress releasing layer2can be tested, and then a region with a large dislocation density in the stress releasing layer2can be selected to be etched.

At step S120, a multi-quantum well layer is grown to conformally cover the surface of the V-shaped layer away from the stress releasing layer.

As shown inFIG.3, the multi-quantum well layer4can include one or more potential well layers402and one or more barrier layers401alternately arranged. A material of the one or more potential well layers402can include InGaN, and a material of the one or more barrier layers401can include GaN or AlGaN, the embodiments of the present disclosure are not particularly limited to this. The growth processes of the potential well layers402and the barrier layers401can refer to the growth process of the first conductivity semiconductor layer1.

In embodiments of the present disclosure, by controlling the temperature change during the growth of the multi-quantum well layer4, material compositions of different potential well layers402located from bottom to top in the multi-quantum well layer4are changed, for example, by controlling the temperature change during the growth of the multi-quantum well layer4, Indium contents of the different potential well layers402located from bottom to top in the multi-quantum well layer4are changed. The multi-quantum well layer4can conformally cover the surface of the V-shaped layer3disposed with the V-shaped grooves301, that is, shapes of the filled V-shaped grooves301are still V-shaped.

An Aluminum content of a region where the V-shaped grooves301are located in the barrier layer401is less than an Aluminum content of other region in the barrier layer401, where the other region refers to a region in the barrier layer401without the V-shaped grooves301, thereby it is easier for holes to penetrate through the V-shaped grooves301in the barrier layer401. In this way, the holes are injected into a light-emitting region (the region where the V-shaped grooves are not located) in deeper potential well layers402through sidewalls of the V-shaped grooves301to combine with electrons to emit light, thereby improving a luminous efficiency.

In addition, in the process of epitaxially growing a barrier layer401, a growth rate of the region where the V-shaped grooves301are located in the barrier layer401is less, so that a thickness of the region where the V-shaped grooves301are located in the barrier layer401is less. In this way, with this arrangement, it is easier for holes to penetrate through the region where the V-shaped grooves301are located in the barrier layer401to be injected into deeper potential well layers402to combine with the electrons to emit light, thereby improving the luminous efficiency. It should be noted that the region where the V-shaped grooves301are located in the potential well layer402is not a light-emitting region. The holes are injected into the potential well layers402without the V-shaped grooves, through sidewalls of the light-emitting region exposed by the V-shaped grooves301, and due to Indium contents are different in different potential well layers402, emitting wavelengths of the LED structure are different, thereby implementing a multi-wavelength LED structure.

In an embodiment of the present disclosure, an Aluminium content of a barrier layer401located at the bottom is uniform in the thickness direction. In another embodiment of the present disclosure, for a plurality of barrier layers401, the Aluminium contents of the barrier layers401gradually decrease from bottom to top, in other words, Aluminium contents of the barrier layers401located at lower are greater than Aluminium contents of the barrier layers401located at upper. In other embodiments of the present disclosure, the Aluminium content of the barrier layer401located at the bottom is gradually changed in the thickness direction and gradually decreases from bottom to top, for example, the Aluminium content of the region where the V-shaped grooves301are located in the barrier layer401gradually decreases from 5% to 0, and the Aluminium content of other region in the barrier layer401gradually decreases from 20% to 0, where the other region refers to a region in the barrier layer401without the V-shaped grooves301. The Aluminium content can be a percentage of an amount of substance for Aluminium to a sum of amounts of substances for all positively charged elements in the barrier layer401.

In another embodiment, before growing the multi-quantum well layer4, the method of preparing the LED structure further includes etching the V-shaped layer3having the V-shaped grooves301to further expand depths of the V-shaped grooves301, to facilitate that carriers of the second conductivity semiconductor layer5are injected into a potential well layer located at the bottom from sidewalls of the V-shaped grooves301. In some embodiments of the present disclosure, after the V-shaped layer3is formed, a dislocation density of the V-shaped layer3can be tested, and a region with a larger dislocation density in the V-shaped layer3can be selected to be etched.

In addition, an Indium content of the V-shaped grooves301with a smaller depth in the potential well layer402is different from an Indium content of the V-shaped groove301with a larger depth in the potential well layer402. The Indium content of the potential well layer402will affect the emitting wavelength of the multi-quantum well layer4. The greater the Indium content of the potential well layer402is, the longer the emitting wavelength of the multi-quantum well layer4is; the smaller the Indium content of the potential well layer402is, the shorter the emitting wavelength of the multi-quantum well layer4is; in the present disclosure, because the Indium contents of the multi-quantum well layer4with different depths are different, the LED structure can emit light of different wavelengths, and thereby implementing white light illumination or display.

At step S130, a second conductivity semiconductor layer is grown on a side of the multi-quantum well layer away from the first conductivity semiconductor layer, and a conductivity type of the second conductivity semiconductor layer is different from a conductivity type of the first conductivity semiconductor layer.

As shown inFIG.3, the second conductivity semiconductor layer5can be a p-type semiconductor layer. A material of the second conductivity semiconductor layer5can be a III-V group semiconductor material, such as, GaN. The growth process of the first conductivity semiconductor layer1can refer to the growth process of the first conductivity semiconductor layer1.

The present disclosure further provides an LED structure. The LED structure is manufactured by the above-mentioned method of preparing the LED structure, and therefore, the LED structure has same beneficial effects, which will not be repeated in this disclosure.

The LED structure and a preparation method thereof in some embodiments of the present disclosure are substantially the same as the LED structure and the preparation method thereof in above-mentioned embodiments of the present disclosure, except for the material of the stress releasing layer2. The material of the stress releasing layer2can be AlyGa1-yN, where 0.01≤y≤0.5, and further, 0.01≤y≤0.3.

The LED structure and a preparation method thereof in some embodiments of the present disclosure are substantially the same as the LED structure and the preparation method thereof in above-mentioned embodiments of the present disclosure, except for the material of the stress releasing layer2. The material of the stress releasing layer2can be AlyInxGa1-yN, where 0.01≤x≤0.3, 0.01≤y≤0.3, and further, 0.01≤x≤0.5, 0.01≤y≤0.5.

The LED structure and a preparation method thereof in some embodiment of the present disclosure are substantially the same as the LED structure and the preparation method thereof in above-mentioned embodiments of the present disclosure, except that: as shown inFIG.4, the method of preparing the LED structure includes forming a first electrode8electrically connected with the first conductivity semiconductor layer1and a second electrode9electrically connected with the second conductivity semiconductor layer5. The substrate6can be removed or not. Taking the first conductivity semiconductor layer1as an n-type semiconductor layer and the second conductivity semiconductor layer5as a p-type semiconductor layer as an example, the first electrode8is an n-type electrode, and the second electrode9is a p-type electrode. A material of the first electrode8and a material of the second electrode9can be selected from at least one of gold, silver, aluminium, chromium, nickel, platinum, or titanium.

The above-mentioned is only preferred embodiments of the present disclosure and does not limit the present disclosure in any form. Although the present disclosure has been disclosed as above in the preferred embodiments, it is not intended to limit the present disclosure. Any skilled person familiar with the art without departing from the scope of the technical solution of the present disclosure, shall be able to make some changes or modifications to the above disclosed technical contents into equivalent embodiments with equivalent changes by using the above disclosed technical content. Any simple modifications, equivalent changes, and modifications to the above embodiments according to the technical essence of the present disclosure without departing from the scope of the technical solution of the present disclosure still belong to the scope of the technical solution of the present disclosure.