Patent ID: 12199097

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Terms indicative of relative degree, such as “about,” “substantially,” and the like, should be interpreted as one having ordinary skill in the art would in view of current technological norms. Generally, the term “substantially” indicates a tighter tolerance than the term “about.” For example, a thickness of “about 100 units” will include a larger range of values, e.g., 70 units to 130 units (+/−30%), than a thickness of “substantially 100 units,” which will include a smaller range of values, e.g., 95 units to 105 units (+/−5%). Again, such tolerances (+/−30%, +/−5%, and the like) may be process- and/or equipment-dependent, and should not be interpreted as more or less limiting than a person having ordinary skill in the art would recognize as normal for the technology under discussion, other than that “about” as a relative term is not as stringent as “substantially” when used in a similar context.

It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “exemplary,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of one skilled in the art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.

The present disclosure is generally related to semiconductor devices, and more particularly to field-effect transistors (FETs), such as planar FETs, three-dimensional fin-line FETs (FinFETs), or gate-all-around (GAA) devices. In accordance with embodiments of the present disclosure, semiconductor device structures, e.g., isolation structures formed using hard masks of dielectric materials, e.g., high-k and low-k dielectric materials are described. Examples of isolation structures include inactive fins including dielectric material structures that electrically isolate portions of adjacent conductive structures, such as adjacent gate structures from each other or adjacent source/drain structures from each other. The processes for forming the semiconductor device structures in accordance with the present disclosure do so utilizing gate isolation structures or hybrid fins, e.g., dielectric features, designed to protect the inactive fins during semiconductor processing steps, that are free of seams or voids that could otherwise negatively impact the performance of the isolation structures and the semiconductor device structures formed using such isolation structures. Such isolation structures are formed by a sequence of deposition and etching steps that result in isolation structures free of seams or voids. As used herein, the term “high-k” refers to a high dielectric constant. In some embodiments, high-k refers to a dielectric constant that is greater than the dielectric constant of SiO2(e.g., greater than 7.0). As used herein, the term “low-k” refers to a small dielectric constant. In some embodiments, low-k refers to a dielectric constant that is less than the dielectric constant of SiO2(e.g., less than 7.0).

Fins associated with fin field effect transistors (finFETs) or nano-sheet FETs may be patterned by any suitable method. For example the fins of a finFET or a nano-sheet FET, e.g., a gate all around (GAA) transistor structure may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.

FIG.1is an isometric view of a device100A, according to some embodiments. Device100A can be a collection of one or more FinFETs, a collection of one or more nano-sheet FETs, a collection of one or more nano-wire FETs, or collection of one or more of any other type of FETs. Device100A can be included in a microprocessor, memory cell, or other integrated circuit. The view of device100A inFIG.1is shown for illustration purposes and may not be drawn to scale.

As shown in the embodiment ofFIG.1, device100A is formed on a substrate102and includes one or more field-effect transistors (FETs)106and multiple isolation structures108separating portions of one FET106from portions of an adjacent FET106. Device100A further includes multiple shallow trench isolation (STI) regions104, multiple gate structures110, and multiple interlayer dielectric (ILD) structures130formed on opposite sides of two gate structures110illustrated inFIG.1.

Substrate102is a physical material on which FETs106and isolation structures108are formed. Substrate102can be a semiconductor material, such as silicon. In some embodiments, substrate102can include a crystalline substrate, such as a silicon substrate (e.g., wafer). In some embodiments, substrate102includes (i) an elementary semiconductor, such as germanium; (ii) a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; (iii) an alloy semiconductor including silicon germanium carbide, silicon germanium, gallium arsenic phosphide, gallium indium phosphide, gallium indium arsenide, gallium indium arsenic phosphide, aluminum indium arsenide, and/or aluminum gallium arsenide; or (iv) a combination thereof. Further, substrate102can be doped depending on design requirements of the FETs (e.g., p-type substrate or n-type substrate). In some embodiments, substrate102can be doped with p-type dopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants (e.g., phosphorus or arsenic). In some embodiments, substrate102can include a glass substrate. In some embodiments, substrate102can include a flexible substrate made of, for example, plastic.

InFIG.1, STI regions104provide electrical isolation to FETs106from each other and from neighboring active and passive elements (not illustrated herein) integrated with or deposited onto substrate102. STI regions104can be made of a dielectric material. In some embodiments, STI regions104can include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), fluorine-doped silicate glass (FSG), a low-k dielectric material, and/or other suitable electrically insulating material. In some embodiments, STI regions104can include a multi-layered structure. In some embodiments, a liner116, made of a suitable insulating material, can be placed between STI region104and the adjacent FETs106.

As illustrated inFIG.1, each FET106is a vertical structure traversing along an x-axis and through gate structures110. In some embodiments, FET106can be a vertical structure oriented along <110>, <111>, or <100> crystal direction of substrate102. In the embodiment illustrated inFIG.1, FETs106includes a buffer region120formed over substrate102. In the embodiment ofFIG.1, FETs106also include a channel region122formed over buffer region120. Channel region122includes at least one channel layer that is made of at least one semiconductor layer. For example,FIG.1illustrates FETs106including six channel layers122A-122F, where each of the six channel layers can include at least a silicon layer or a silicon germanium layer. AlthoughFIG.1shows six channel layers122A-122F, any number of channel layers can make up channel region122. FETs106horizontally (e.g., in the x-direction) traverse through gate structure110, so a portion of channel region122is present under gate structure110and another portion of channel region122(covered by source-drain region124; not shown inFIG.1) extends horizontally (e.g., in the x-direction) outside gate structure110. In some embodiments, device100A can be a collection of one or more FinFETs, where a top surface and side surfaces of the portion of channel regions122under gate structure110can be in physical contact with gate structure110. In some embodiments, as shown inFIG.1, device100A is a collection of one or more nano-sheet FETs where a top surface, side surfaces, and the bottom surface of the portion of channel regions122under gate structure110can be in physical contact with gate structure110. In some embodiments, device100A is a collection of one or more nano-wire FETs where a circumferential surface of the portion of channel regions122under gate structure110can be in physical contact with gate structure110.

In some embodiments, device100A can be a collection of one or more nano-sheet FETs or a collection of one or more nano-wire FETs, where channel region122can include a first portion with alternating channel layers (not shown inFIG.1; buried within source-drain124) and a second portion with the alternating channel layers (e.g., channel layers122A-122F). The second channel layers from the first portion of channel region122can extend through the second portion of channel region122. Gate structure110can be formed over the second portion of the channel region122. In some embodiments, gate structure110can surround the second channel layers of the second portion of channel region122.

FETs106further include a source-drain region124formed over a portion of channel region122and over buffer region120. For example, source-drain124can wrap around the portion of channel region122that is horizontally (e.g., in the x-direction) outside gate structure110, e.g., not under the gate structure110. In some embodiments, channel region122and source-drain region124can be positioned above top surfaces of STI regions104. In some embodiments, bottom surfaces of channel region122and bottom surfaces of source-drain region124can be above or substantially coplanar with top surfaces of STI regions104.

Channel regions122can be current-carrying structures for device100A. Source-drain region124that covers portions of channel region122can be configured to function as source/drain (S/D) regions of device100A. Channels of device100A can be formed in portions of channel region122under gate structures110.

Each of buffer region120and channel region122can include materials similar to substrate102. For example, each of buffer region120and channel region122can include a semiconductor material having lattice constant substantially closed to (e.g., lattice mismatch within 1%) that of substrate102. In some embodiments, each of buffer region120and channel region122can include material similar to (e.g., lattice mismatch within 1%) or different from each other. In some embodiments, buffer region120can include an elementary semiconductor, such as silicon and germanium. In some embodiments, channel region122can include an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenic phosphide, gallium indium phosphide, gallium indium arsenide, gallium indium arsenic phosphide, aluminum indium arsenide, and aluminum gallium arsenide.

Each of buffer region120and channel region122can be p-type, n-type, or un-doped. In some embodiments, a portion of channel region122under gate structure110and another portion of channel region122horizontally (e.g., in the x-direction) outside gate structure110can have different doping type. For example, a portion of channel region122under gate structure110can be un-doped, and another portion of channel region122that is outside gate structure110can be n-type doped. In some embodiments, buffer region120and a portion of channel region122under gate structure can have same doping type.

Source-drain region124can include an epitaxially-grown semiconductor material. In some embodiments, the epitaxially-grown semiconductor material can be the same material as the material of substrate102. In some embodiments, the epitaxially-grown semiconductor material can include a different material from the material of substrate102. The epitaxially-grown semiconductor material can include: (i) a semiconductor material, such as germanium (Ge) and silicon (Si); (ii) a compound semiconductor material, such as gallium arsenide and aluminum gallium arsenide; or (iii) a semiconductor alloy, such as silicon germanium (SiGe) and gallium arsenide phosphide. In some embodiments, device100A can include a FET106having a first source-drain region124(e.g., source-drain region124A) and another FET106having a second source-drain region124(e.g., source-drain region124B), where the first and the second source-drain regions124(e.g.,124A and124B) can be made of the same or different semiconductor material.

Source-drain region124can be p-type or n-type doped. In some embodiments, source-drain region124can be doped with p-type dopants, such as boron, indium, gallium, zinc, beryllium, and magnesium. In some embodiments, source-drain region124can be doped with n-type dopants, such as phosphorus, arsenic, silicon, sulfur, and selenium. In some embodiments, each of n-type source-drain region124can have a plurality of n-type sub-regions. Except for the type of dopants, the plurality of n-type sub-regions can be similar to the respective plurality of p-type sub-regions, in thickness, relative Ge concentration with respect to Si, dopant concentration, and/or epitaxial growth process conditions.

Source-drain region124can be grown over portions of channel regions122that extend beyond gate structure110and/or buffer regions120via an epitaxial growth process. In some embodiments, source-drain regions124can be epitaxially grown on portions of FETs106that are horizontally (e.g., in the x-direction) outside gate structures110. The epitaxial growth process for source-drain region124can include (i) chemical vapor deposition (CVD), such as low pressure CVD (LPCVD), rapid thermal chemical vapor deposition (RTCVD), metal-organic chemical vapor deposition (MOCVD), atomic layer CVD (ALCVD), ultrahigh vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), or any suitable CVD; (ii) molecular beam epitaxy (MBE) processes; (iii) any suitable epitaxial process; or (iv) a combination thereof. In some embodiments, source-drain region124can be grown by an epitaxial deposition/partial etch process, which repeats the epitaxial deposition/partial etch process at least once. Such repeated deposition/partial etch process is also called a “cyclic deposition-etch (CDE) process.” In some embodiments, source-drain region124can be grown by selective epitaxial growth (SEG), where an etching gas can be added to promote the selective growth of semiconductor material on the exposed surfaces of FETs106, but not on insulating material (e.g., dielectric material of STI regions104).

Doping of source-drain regions124can be achieved by introducing one or more precursors during the above-noted epitaxial growth process. For example, source-drain region124can be in-situ p-type doped during the epitaxial growth process using p-type doping precursors, such as diborane (B2H6) and boron trifluoride (BF3). In some embodiments, source-drain region124can be in-situ n-type doped during an epitaxial growth process using n-type doping precursors, such as phosphine (PH3) and arsine (AsH3).

InFIG.1, isolation structures108are vertical structures formed over STI region104and placed horizontally (e.g., in the y-direction) between FETs106. Isolation structures108can include a dielectric stack to electrically insulate multiple FETs106from one another. In some embodiments, the dielectric stacks of the isolation structures108can be vertical extensions of STI region104to electrically insulate portions of FETs106. For example, isolation structures108can be-include dielectric inactive fin structures having dielectric features on top of the inactive fin structures and placed between two FETs106to isolate, for example, metal gates of the two FETs106from one another. In some embodiments, each of FETs106and each of isolation structures108can be alternatively and horizontally (e.g., in the y-direction) placed next to each other. In some embodiments, isolation structures108can include fin structures to isolate source-drain regions124of the two FETs106from one another. Isolation structures108can have a vertical dimension (e.g., height) that is substantially equal to or greater than a height of channel region122. In some embodiments, isolation structures108can have horizontal dimensions (e.g., width along the y-direction) that are substantially equal to or less than a spacing between two horizontally (e.g., in the y-direction) adjacent FETs106.

As shown inFIG.1, gate structure110is a vertical structure traversing along a y-axis and through one or more FETs106. AlthoughFIG.1shows two gate structures110traversing six FETs106, any number of gate structures110can be included in device100A, where each of the gate structures110can be parallel to each other and can traverse any number of FETs106. In some embodiments, gate structure110can surround a portion of a top surface and a portion of side surfaces of channel region122(e.g., when device100A is a collection of one or more FinFETs). In some embodiments, gate structure110can surround a portion of a top surface, a portion of side surfaces, and a portion of a bottom surface of channel region122(e.g., when device100A is a collection of one or more nano-sheet FETs) or can surround a portion of the circumferential surface (e.g., when device100A is a collection of one or more nano-wire FETs). Gate structure110can include a gate electrode114and a dielectric layer112disposed between the surrounded channel region122and gate electrode114. In some embodiments, gate structure110can have a horizontal dimension (e.g., gate length) Lgthat ranges from about 5 nm to about 30 nm. In some embodiments, gate structure110can be formed by a gate replacement process. In some embodiments, gate structure110can be formed by a gate first process.

Dielectric layer112can be adjacent to and in contact with gate electrode114. Dielectric layer112can have a thickness in a range from about 1 nm to about 5 nm. Dielectric layer112can include silicon oxide and may be formed by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), e-beam evaporation, or any other suitable process. In some embodiments, dielectric layer112can include (i) a layer of silicon oxide, silicon nitride, and/or silicon oxynitride, (ii) a high-k dielectric material, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium aluminum oxide (HfAlOx), titanium oxide (TiO2), hafnium zirconium oxide (HfZrOx), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), hafnium silicon oxide (HfSiOx), zirconium oxide (ZrO2), zirconium silicate (ZrSiO2), (iii) a high-k dielectric material having oxides of lithium (Li), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), scandium (Sc), yttrium (Y), zirconium (Zr), aluminum (Al), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu), or (iv) a combination thereof. High-k dielectric layers may be formed by ALD and/or other suitable methods. In some embodiments, dielectric layer112can include a single layer or a stack of insulating material layers. Based on the disclosure herein, other materials and formation methods for dielectric layer112are within the scope and spirit of this disclosure.

Gate electrode114can include a gate work function metal layer (not shown) and a gate metal fill layer (not shown). In some embodiments, the gate work function metal layer can be disposed on dielectric layer112. The gate work function metal layer can include a single metal layer or a stack of metal layers. The stack of metal layers can include metals having work functions similar to or different from each other. In some embodiments, the gate work function metal layer can include, for example, aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), silver (Ag), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), tantalum carbon nitride (TaCN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tungsten nitride (WN), metal alloys, and/or combinations thereof. The gate work function metal layer can be formed using a suitable process, such as ALD, CVD, PVD, plating, or combinations thereof. In some embodiments, the gate work function metal layer can have a thickness in a range from about 2 nm to about 15 nm. Based on the disclosure herein, other materials, formation methods, and thicknesses for the gate work function metal layer are within the scope and spirit of this disclosure.

The gate metal fill layer of gate electrode114can include a single metal layer or a stack of metal layers. The stack of metal layers can include metals different from each other. In some embodiments, the gate metal fill layer can include a suitable conductive material, such as Ti, silver (Ag), Al, titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten nitride (WN), copper (Cu), tungsten (W), cobalt (Co), nickel (Ni), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), metal alloys, and/or combinations thereof. The gate metal fill layer can be formed by ALD, PVD, CVD, or other suitable deposition process. Based on the disclosure herein, other materials and formation methods for the gate metal fill layer are within the scope and spirit of this disclosure.

InFIG.1, ILD structure130includes one or more insulating layers to provide electrical isolation to structural elements it surrounds or covers—for example, gate structure110, source-drain regions124, and source/drain contact structures (not shown inFIG.1) that will be formed adjacent to the gate structures110. Each of the insulating layers can include an insulating material, such as silicon oxide, silicon dioxide (SiO2), silicon oxycarbide (SiOC), silicon oxynitride (SiON), silicon oxy-carbon nitride (SiOCN), or silicon carbonitride (SiCN) that can be formed by low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), flowable CVD (FCVD), or high-aspect-ratio process (HARP). ILD structure130can have a thickness (e.g., along the z-direction) in a range from about 50 nm to about 200 nm. Based on the disclosure herein, other insulating materials, thicknesses, and formation methods for ILD structure130are within the scope and spirit of this disclosure.

FIG.2is a flow diagram of a method300for fabricating device100A as described with reference toFIG.1, according to some embodiments of the present disclosure. For illustrative purposes, the operations illustrated inFIG.2will be described with reference to an example fabrication process for fabricating device100A with reference toFIGS.3A-3M, which are isometric or cross-sectional views of device100A at various stages of its fabrication, according to some embodiments. Operations can be performed in a different order or not performed depending on specific applications. It should be noted that method300does not manufacture a complete device100A. Accordingly, it is understood that additional processes may be provided before, during, and after method300, and that some other processes may only be briefly described herein. Elements inFIGS.3A-3Mwith the same annotations as elements inFIG.1are described above.

In operation305, a first and a second vertical structure are formed on a substrate. For example, as shown inFIG.3F, multiple vertical structures402(e.g., fin stacks) and multiple vertical structures902(e.g., isolation structures108ofFIG.1) can be respectively formed on substrate102.FIGS.3A and3Gare isometric views of partially fabricated structures that can be used to describe the fabrication stages of operation305. As shown inFIG.3A, the process of forming vertical structures402can include forming a patterned hard mask layer406over substrate102and forming recess structures410within substrate102via an etching process using patterned hard mask layer406. The process of forming patterned hard mask layer406can include patterning a blanket film using a lithography process and/or an etching process. By way of example and not limitation, the blanket film can be silicon nitride, silicon carbon nitride, silicon oxide, or any other suitable material, and can be deposited using, LPCVD, RTCVD, ALD, or PECVD. The etching process for forming recess structures410can be a dry etch process, a wet etch process, or a combination thereof. In some embodiments, the dry etch process can use reactive ion etching using a chlorine or fluorine based etchant. Each vertical structure402can include buffer region120made of a same or similar material as substrate102. In some embodiments, vertical structure402can have a width W1ranging from about 3 nm to about 50 nm. In some embodiments, vertical structure402can have a width W1ranging from about 5 nm to about 40 nm. In some embodiments, a spacing P1(e.g., pitch size) between two adjacent vertical structures402can range from about 14 nm to about 40 nm. Based on the disclosure herein, any width and spacing associated with vertical structures402are within the scope and spirit of this disclosure.

In some embodiments, the process of forming vertical structure402can further include epitaxially growing at least one channel layer (e.g.,122A-122F) on substrate102to form channel region122, before forming patterned hard mask layer406. By way of example and not limitation, each channel layer122A-122F can include Si or SiGe and can be grown using an epitaxial growth process, such as LPCVD, RTCVD, MOCVD, ALD, PECVD, or a combination thereof. AlthoughFIG.3Ashows six channel layers122A-122F, any number of channel layers can be epitaxially grown on substrate102to form channel region122. In some embodiments, multiple sacrificial layers404can be epitaxially grown and interleaved with the epitaxially grown channel layers. In some embodiments, sacrificial layer404can include SiGe. In the embodiment illustrated inFIG.2C, the uppermost sacrificial layer404has a dimension in the Z direction, e.g., a height, that is similar to the height of other sacrificial layers404below the uppermost sacrificial layer. In another embodiment the uppermost sacrificial layer404has a height in the Z-direction that is greater than the height of the other sacrificial layers404below the uppermost sacrificial layer. For example, the height of the uppermost sacrificial layer404has a height that is similar in dimension to the height of hard mask layer406. In such embodiment, uppermost sacrificial layer404serves as a hard mask similar to hard mask406and replaces hard mask406. The description herein with respect to further processing of hard masks406applies to the upper sacrificial layer404when the upper sacrificial layer replaces the hard mask406. In some embodiments, each vertical structure402can include buffer region120, channel region122, and sacrificial layers404.

Further, in operation305, STI regions104are formed. For example, STI regions104can be formed as described with reference toFIGS.3A and3D. In some embodiments, as shown inFIG.3D, the process of forming STI region104can include depositing a protective layer408(e.g., conformally) over recess structures410. Protective layer408can include a nitride material (e.g., SiNx) and can be deposited using, for example, ALD or LPCVD. Furthermore, as shown inFIG.3B, the process of forming STI regions104can include depositing an insulating material over recess structures410, annealing the insulating material, polishing (e.g., chemical mechanical polishing (CMP)) the annealed insulating material, and recessing the polished insulating material to form STI regions104. In some embodiments, protective layer408can prevent oxidation of vertical structures402during the annealing of the insulating material. By way of example and not limitation, the insulating material can include, silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), or a low-k dielectric material. In some embodiments, the process of depositing the insulating material can include any deposition method suitable for flowable dielectric materials (e.g., flowable silicon oxide). For example, flowable silicon oxide can be deposited for STI regions104using a flowable CVD (FCVD) process. The FCVD process can be followed by a wet anneal process. In some embodiments, the process of depositing the insulating material can include depositing a low-k dielectric material to form liner116.

The annealing of the insulating material can include annealing the deposited insulating material in a steam at a temperature in a range from about 200° C. to about 700° C. for a period in a range from about 30 min to about 120 min. The anneal process can be followed by the polishing process that can remove portions of the layer of the insulating material. The polishing process can further remove all or portions of patterned hard mask layer406. When all of patterned hard mask406is removed, the uppermost sacrificial layer404is exposed. As noted above, in some embodiments, the uppermost sacrificial layer404can have a height that is similar to the height of hard mask406. Removing only a portion of patterned hard mask406forms patterned hard mask layer506, where a top surface of the insulating material after the polishing process can be substantially coplanarized with a top surface of patterned hard mask layer506. The polishing process can be followed by the etching process to recess the polished insulating material to form STI regions104. The recessing of the polished insulating material can be performed, for example, by a dry etch process, a wet etch process, or a combination thereof which has higher selectivity for the STI region material compared to the hard mask of uppermost sacrificial layer404. In some embodiments, the dry etch process for recessing the polished insulating material can include using a plasma dry etch with a gas mixture that can include octafluorocyclobutane (C4F8), argon (Ar), oxygen (O2), helium (He), fluoroform (CHF3), carbon tetrafluoride (CF4), difluoromethane (CH2F2), chlorine (Cl2), hydrogen bromide (HBr), or a combination thereof with a pressure ranging from about 1 mTorr to about 5 mTorr. In some embodiments, the wet etch process for recessing the polished insulating material can include using a diluted hydrofluoric acid (DHF) treatment, an ammonium peroxide mixture (APM), a sulfuric peroxide mixture (SPM), hot deionized water (DI water), or a combination thereof. In some embodiments, the wet etch process for recessing the polished insulating material can include using an etch process that uses ammonia (NH3) and hydrofluoric acid (HF) as etchants and inert gases, such as Ar, xenon (Xe), He, or a combination thereof. In some embodiments, the flow rate of HF and NH3used in the etch process can each range from about 10 sccm to about 100 sccm (e.g., about 20 sccm, 30 sccm, or 40 sccm). In some embodiments, the etch process can be performed at a pressure ranging from about 5 mTorr to about 100 mTorr (e.g., about 20 mTorr, about 30 mTorr, or about 40 mTorr) and a temperature ranging from about 50° C. to about 120° C.

Further, in operation305, vertical structures902are formed. For example, vertical structures902can be formed as described with reference toFIGS.3C-3F. In referring toFIG.3C, the process of forming vertical structures902(shown inFIG.3F) can include depositing seed layer602over recess structures410(shown inFIG.3B). Seed layer602can be in contact with side surfaces of vertical structures402. In some embodiments, seed layer602can be in contact with a top surface and side surfaces of pattern hard mask layers506. In other embodiments, patterned hard mask layer506may be removed from the surface of the uppermost sacrificial layer404and the seed layer602maybe deposited over the exposed surfaces of the uppermost sacrificial layer404. Seed layer602can include any suitable semiconductor material, such as SiGe, and can be deposited using any suitable deposition process, such as CVD or ALD. In referring toFIG.3D, the process of forming vertical structures902can include depositing (e.g., conformally) a liner layer and a dielectric stack142over vertical structures402and patterned hard mask layer506(if present), polishing (e.g., CMP) the liner layer and the dielectric stack, and recessing the polished liner and the dielectric stack (e.g., an inactive fin) to form recess structure710between vertical structures402via an etching process. The etching process for forming recess structures710can form liners704and dielectric stack142illustrated in the structure ofFIG.3D. The material, the deposition process, the polishing process, and the etching process associated with the liner layer and the dielectric stack142can be similar to those used to form STI regions104. In some embodiments, dielectric stack142can have a height H6ranging from about 10 nm to about 100 nm. In some embodiments, dielectric stack142can have a height H6ranging from about 20 nm to about 80 nm.

The process of forming vertical structure902can further include depositing an insulating dielectric layer into recess structures710, polishing the insulating dielectric layer to form insulating block144(shown inFIG.3E) over dielectric stack142, and etching patterned hard mask layer506(when present as shown inFIG.3F). Insulating block144forms a dielectric feature above and over dielectric stack142. The dielectric feature extends away from an upper surface of the dielectric stack142. In some embodiments, a portion of seed layer602can be removed during polishing the insulating dielectric layer to form seed layer802inFIG.3E. The insulating dielectric layer can include a high-k material or any other suitable dielectric material which has high selectivity (e.g., larger than 1) to dielectric stack142. For example, the insulating dielectric layer can include materials such as silicon oxycarbide (SiOC), silicon oxynitride (SiON), silicon oxy-carbon nitride (SiOCN), or silicon carbonitride (SiCN). It has been observed that when an insulating dielectric layer is deposited into recess structures710having an aspect ratio above a particular threshold, e.g., greater than 1.5 or more, or greater than 2 or more, seams or voids are present in the deposited insulating dielectric layer. Such seams or voids can result in rejection of the formed device which adversely affects product yield. In addition the presence of such seams or voids negatively affects the ability of the insulating dielectric material to protect features of the underlying dielectric stack142, seed layer602or liner704. In accordance with embodiments of the present disclosure, the insulating dielectric layer is deposited in recess structure710utilizing a plurality of alternating deposition and etching processes as described below. In accordance with embodiments of the present disclosure, recess structures710have a depth ranging from about 5 to 50 nm and a width ranging from about 5 to 50 nm. In other embodiments, recess structures710have a depth ranging from about 5 to 30 nm and a width ranging from about 5 to 30 nm.

Referring toFIGS.3D and6A, in accordance with an embodiment, the insulating dielectric layer is deposited into recess structure710utilizing a plurality of repetitive deposition and etching steps described below with reference toFIGS.6B-6E. For example, in some embodiments, such as illustrated inFIGS.6B-6E, at least two repetitive cycles of deposition and etching are carried out. In other words, in accordance with such embodiments, the sequence of deposition and etching is as follows: deposition, etching, deposition, etching. In other embodiments, more than two repetitive deposition and etching steps are carried out. Embodiments in accordance with the present disclosure are not limited to one sequence of the repetitive etching and deposition steps being carried out under identical conditions as another subsequent repetitive etching and deposition sequence. In other words, conditions under which the etching and deposition steps are carried out in the respective etching and deposition sequences can differ.

Referring toFIG.6B, in one embodiment, the deposition of a first insulating dielectric layer610is accomplished using methods suitable for flowable dielectric materials (e.g., flowable silicon oxide). For example, flowable silicon oxide can be deposited using a flowable CVD (FCVD) process. The FCVD process can be followed by a wet anneal process. Embodiments in accordance with the present disclosure are not limited to use of FCVD to deposit the insulating dielectric layer, for example, other processes such as other CVD or ALD processes can be utilized. In an embodiment, when an ALD process is utilized to deposit the insulating dielectric layer610into recess structure710that forms insulating block144inFIG.3E, the ALD process is carried out under conditions that result in the deposition of the insulating dielectric layer610that has a thickness that results in a ratio of a thickness of the deposited insulating dielectric material removed by the etching step described below in more detail and a thickness of the insulating dielectric material deposited by the depositing step that is between about 1:4 and 1:1. In some embodiments, the thickness of the deposited insulating dielectric layer610in a single deposition step is about 5 to 8 nm. Embodiments in accordance with the present disclosure are not limited to deposition steps that deposit 5 to 8 nm of the insulating dielectric layer610in a single deposition step. For example, in other embodiments, the insulating dielectric layer610deposited in a single deposition step of the plurality of repetitive deposition and etching cycles is less than 5 nm thick or more than 8 nm. In one embodiment, the thickness of the deposited insulating dielectric layer610that is etched in a single etching step of the plurality of repetitive deposition and etching cycles is an amount that results in a ratio of a thickness of the deposited insulating dielectric layer610removed by the etching step and a thickness of the insulating dielectric material deposited by the depositing step that is between about 1:4 and 1:1. In some embodiments, the thickness of the deposited insulating dielectric layer610removed in a single etching step is between about 2 to 5 nm. Embodiments in accordance with the present disclosure are not limited to etching steps that remove 2 to 5 nm of the insulating dielectric layer610. For example, in other embodiments, the thickness of the deposited insulating dielectric layer610that is removed by a single etching step is less than 2 nm or greater than 5 nm.

Referring toFIG.6C, etching or removal of a portion of the deposited insulating layer610, in one embodiment, is accomplished by contacting the deposited insulating layer610with a mixture of sulfuric acid (e.g., 96 wt % sulfuric acid) and hydrogen peroxide (e.g., 30 wt % hydrogen peroxide) (SPM). Examples of a suitable SPMs are characterized by a volume ratio of sulfuric acid to hydrogen peroxide that is between 1:4 and 4:1. Embodiments in accordance with the present disclosure are not limited to use of SPMs that have a volume ratio of sulfuric acid to hydrogen peroxide between 1:4 and 4:1. For example, in other embodiments, SPMs having a volume ratio of sulfuric acid to hydrogen peroxide that is less than 1:4 or greater than 4:1 can be used. In accordance with some embodiments, the SPM is contacted with the deposited insulating dielectric layer for a period of between 1 to 10 minutes. In some embodiments, the contacting of the SPM with the deposited insulating dielectric layer610is carried out at temperatures between about 50° C. to 180° C. Embodiments in accordance with the present disclosure are not limited to contacting the SPM with the deposited insulating dielectric layer for these described periods of time at these described temperatures. For example, in accordance with other embodiments, the SPM is contacted with the deposited insulating dielectric layer for a period of time less than one minute or a period of time greater than 10 minutes. In other embodiments, the SPM is contacted with the deposited insulating dielectric layer610at temperatures less than 50° C. and temperatures greater than 180° C. Generally, as the temperature at which the SPM is contacted with the deposited insulating dielectric layer is increased, the length of time of the contacting can be decreased and vice versa. The volume ratio of sulfuric acid to hydrogen peroxide of the SPM will also affect the length of time and temperature for the etching process. Typically, as the ratio of sulfuric acid to hydrogen peroxide of the SPM increases, the length of time of the etching step can decrease, the temperature of the etching step can decrease, or both, and the same amount of etching will still be achieved.

In accordance with other embodiments, the SPM can be diluted with water. For example, the SPM can be diluted with water at a ratio of 1:1 up to 1:10 depending upon the ratio of the sulfuric acid to hydrogen peroxide of the undiluted SPM. Embodiments in accordance with the present disclosure are not limited to diluting the SPM at a ratio in the range of 1:1 up to 1:10. For example, in other embodiments, the SPM can be diluted at a ratio less than 1:1 or a ratio greater than 1:10.

In some embodiments as illustrated inFIG.6C, the etched first layer612includes a sloped transition614between a surface of vertical portions611and a surface of horizontal portions613of dielectric material layer610. Such sloping of surface614is a function of the rate of etching at surface614compared to the rate of etching at the surfaces of the horizontal portions611and the vertical portions613and the shape of layer610prior to etching.

Referring toFIG.6D, in accordance with an embodiment of the present disclosure, a second dielectric material layer616is deposited over the etched first layer612of dielectric material. The description above regarding the deposition of first dielectric layer610is applicable to the deposition of second dielectric material layer616. Second layer of dielectric material616is then etched to produce an etched second dielectric material layer618. The description above regarding etching of first dielectric material layer610is applicable to the etching of second dielectric material layer616. In the embodiment illustrated inFIG.6D, the second dielectric material layer618includes a sloped surface624at the transition from a vertical portions620and a horizontal portions622of etched second dielectric material layer618. In accordance with the embodiments ofFIGS.6A-6E, at least one additional cycle of dielectric material deposition and dielectric material etching is carried out prior to planarization in order to complete formation of dielectric feature560inFIG.5. In accordance with embodiments of the present disclosure, the combination of deposition of a single layer of the insulating dielectric material and etching of the deposited single layer of dielectric material layer defines a cycle of formation of insulating block144/dielectric feature. In accordance with embodiments of the present disclosure, this cycle is repeated at least twice and in other embodiments more than two times in order to form sequentially a plurality of layers of the dielectric material which ultimately form a dielectric feature free of seams and voids. Formation of a dielectric feature free of seams and voids reduces the number of wafers that are rejected due to the presence of seams or voids in the dielectric feature. As noted above, the presence of seams or voids in the dielectric feature can result in rejection of the device which includes the dielectric feature with seams or voids. In addition, the presence of seams or voids in the dielectric feature negatively impacts the ability of the dielectric feature to protect features underlying the dielectric feature, for example, the dielectric stack142, seed layer602or liner704.

Referring toFIG.5, in accordance with an embodiment of the present disclosure, the dielectric feature560forms an upper portion of a gate isolation feature and includes a plurality of layers510,520and530of dielectric material and a plurality of interfaces540and550. Each of the layers510,520and530is formed by a deposition step and a subsequent etching step. This results in an interface540between layers510and520and an interface550between layers520and530. Embodiments in accordance with the present disclosure are not limited to a dielectric feature that includes three layers and two interfaces. In accordance with other embodiments, more layers and more interfaces may be present. In accordance with embodiments of the present disclosure an interface between two layers of the dielectric material is characterized by the presence of elemental oxygen or elemental nitrogen. This elemental oxygen or nitrogen can be detected using various techniques including energy dispersive x-ray spectroscopy or other similar technique. The presence of the elemental oxygen or elemental nitrogen at these interfaces is believed to be a result of the deposition and/or etching of the dielectric material of the insulating dielectric layer being carried out in the presence of oxygen or nitrogen.

Referring toFIG.7, illustrates an alternative embodiment in accordance with the present disclosure. In accordance with embodiments ofFIG.7, features that are in common withFIGS.5and6A-6Eare identified by the reference numbers used inFIGS.5and6A-6E. The description of these common features is not reproduced here. For the embodiment illustrated inFIG.7, the description above regarding deposition of layers610and616with reference toFIGS.6A-6Eis also applicable to deposition of layers610,616and530of dielectric plug560illustrated inFIG.7. In accordance with the embodiment illustrated inFIG.7, etching of first dielectric material layer610described above with reference toFIGS.6B and6Cnot only etches a portion of first dielectric material layer610at surface614inFIG.6Clocated at the transition between horizontal portions612and vertical portions613position, but also etches/removes a portion of underlying fin side wall spacer650at a transition between vertical and horizontal portions of fin side wall spacer650. The degree to which a portion of underlying fin side wall spacer650is etched may vary. For example, in the embodiment illustrated inFIG.7, the vertical portion of fin side wall spacer650is etched to a varying degree along its entire length, thus producing a sloped surface652. In other embodiments less than the entire length of vertical portion of fin side wall spacer650is removed. The result of etching underlying fin side wall spacer650along an entire length of its vertical portion613is that dielectric feature560has a width that is greater at its upper surface654than the width of the dielectric feature560at its lower surface656. In other embodiments, the entire length of vertical portion613of underlying fin side wall spacer650is not etched and only a portion of the length of vertical's portion613is etched. In such other embodiments, dielectric feature560includes a width at its upper surface654that is greater than its width at lower surface656.

As illustrated inFIG.3E, a top surface of insulating block144can be substantially coplanar to a top surface of patterned hard mask layer506after the polishing. Namely, insulating block144can have a height H7that can be determined based on a height of patterned hard mask layer506or in other embodiments, the height of the uppermost sacrificial layer404. In some embodiments, insulating block144can have a height H7substantially similar to that of hard mask layer506or the uppermost sacrificial layer404. In some embodiments, insulating block144can have a height H7ranging from about 1 nm to about 50 nm, or from about 4 nm to about 30 nm. In some embodiments, a ratio between dielectric stack142's height H6(shown inFIG.3D) and insulating block144's height H7can range from about 0.05 and 20, or from about 0.125 and 8.

In referring toFIG.3F, patterned hard mask layer506or the uppermost sacrificial layer404can be selectively removed from the fabricated structure shown inFIG.3E. The etching of patterned hard mask layer506can use any suitable wet etching process or dry etching process that has high selectivity (e.g., larger than 1) to sacrificial layer404, e.g., of SiGe, and insulating block144. In other embodiments, where the thicker uppermost sacrificial layer404is present, the etching of patterned hard mask layer506can use any suitable wet etching process or dry etching process that has high selectivity (e.g., larger than 1) to sacrificial layer404, e.g., of SiGe, and insulating block144. In other embodiments, the etching of the patterned hard mask andFIG.3Fuses an etching process that does not have high selectivity relative to sacrificial layer404such that the uppermost sacrificial layer404is removed, thus exposing the underlying channel layer122A. In some embodiments, the etching process for removing patterned hard mask layer506does not substantially change insulating block144's height H7. In some embodiments, after forming insulating block144, each vertical structure902can include liner704, dielectric stack142, and insulating block144formed over dielectric stack142. In some embodiments, after forming insulating block144, each vertical structure902can include seed layer802, dielectric stack142, liners704that are in contact with seed layer802and dielectric stack142, and insulating block144formed over dielectric stack142.

Referring toFIG.2, in operation310, a first gate structure is formed over the first and the second vertical structures. For example, as shown inFIG.3M, multiple gate structures1602are formed on vertical structures1402.FIGS.3G-3Mare isometric and/or cross-sectional views of partially fabricated structures that can be used to describe the fabrication stages of operation310. In referring toFIG.3G, multiple sacrificial gate structures1002can be formed along a horizontal direction (e.g., y-axis) perpendicular to a longitudinal direction of vertical structures402(e.g., fin stacks) and902. Sacrificial gate structure1002can include a sacrificial gate dielectric1004and a sacrificial gate electrode1012. In some embodiments, a vertical dimension of sacrificial gate electrode1012can be in a range from about 90 nm to about 200 nm. AlthoughFIG.3Gshows two sacrificial gate structures1002, any number of sacrificial gate structures1002can be formed parallel to each other. In some embodiments, sacrificial gate structure1002can further include capping layer1006and hard mask layer1008. By way of example and not limitation, sacrificial gate dielectric1004can be deposited prior to deposition of sacrificial gate electrode1012and can be interposed between vertical structures402and sacrificial gate electrode1012. In some embodiments, sacrificial gate dielectric1004can be interposed between vertical structures902and sacrificial gate electrode1012. According to some embodiments, sacrificial gate dielectric1004can include a low-k dielectric material, such as silicon oxide or silicon oxynitride, and sacrificial gate electrode1012can include polycrystalline silicon (polysilicon). By way of example and not limitation, sacrificial gate dielectric1004and sacrificial gate electrode1012can be deposited as blanket layers using any suitable deposition process (e.g., PVD or CVD) and patterned with lithography and etching operations to form sacrificial gate structure1002over vertical structures402and902.

Further, in operation310, spacer structures1304can be formed (shown inFIG.3J), as described with reference toFIG.3H-3J. In referring toFIG.3H, the process of forming spacer structures1304can include forming a gate spacer1154over sacrificial gate structure1002.FIG.3His a cross-sectional view of the structure along line C-C ofFIG.3Gafter forming gate spacer1154over sacrificial gate structure1002. AlthoughFIG.3Hshows four channel layers122A-122D, any number of channel layers can be included in each vertical structure402. In addition, although gate spacer1154inFIG.3Hincludes two spacer layers (spacers1154A and1154B), any number of spacer layers can be included in gate spacer1154. The process of forming gate spacer1154can include a surface treatment and a deposition of spacer material. In some embodiments, the surface treatment can include exposing sacrificial gate structure1002to an inhibitor to form H- or F-terminated surfaces on the sidewalls of sacrificial gate structure1002. The H- or F-terminated surfaces can facilitate the deposition of the spacer material. The spacer material can be deposited using, for example, CVD or ALD. The surface treatment can be performed before or during the deposition process. The deposition process can be followed by, for example, an oxygen plasma treatment to remove a hydrophobic component on sacrificial gate structure1002. In some embodiments, the spacer material can include (i) a dielectric material, such as silicon oxide, silicon carbide, silicon nitride, and silicon oxy-nitride, (ii) an oxide material, (iii) a nitride material, (iv) a low-k material, or (v) a combination thereof. In some embodiments, the spacer material of each spacer layer (e.g., spacer1154A and1154B) of gate spacer1154can be same or different from each other. The process of forming gate spacer1154can further include an etching process to remove a portion of the deposited spacer material. In some embodiments, the etching process can be an anisotropic etch that removes the spacer material faster on horizontal surfaces (e.g., on the x-y plane) compared to vertical surfaces (e.g., on the y-z or x-z planes). In some embodiments, each spacer1154A and1154B can have a thickness in a range from about 2 nm to about 5 nm.

After forming gate spacer1154, multiple recess structures1201can be formed along each vertical structure402to form vertical structure1202. For example, as shown inFIG.3I, a process of forming recess structures1201can include removing channel layers within channel region122, sacrificial layers404, and buffer region120via an etching back process using sacrificial gate structure1002and gate spacer1154as hard masks. The etching back process can be an etching process using similar techniques as forming recess structures410. For example, the etching process can be a dry etch process, a wet etch process, or a combination thereof. In some embodiments, the dry etch process can use reactive ion etching using a chlorine or fluorine based etchant. In some embodiments, the process of forming recess structures1201can remove a portion of gate spacer1154to form gate spacer1254. For example, spacer1254A and1254B can be formed by respectively etching an upper portion of gate spacer1154A and1154B (e.g., portions of gate spacer1154that is placed at or near sacrificial gate structure1002's top surface) during the process of forming recess structure1201. In some embodiments, gate spacer1254can be substantially the same as gate spacer1154after forming recess structures1201(e.g., the etching processes for the process of forming recess structures1201has a lower etching rate towards gate spacer1154).

In some embodiments, the process of forming spacer structures1304can further include forming inner spacers254. The process of forming inner spacer254can include forming recess structures1203and filling each recess structure1203with a spacer material. As shown inFIG.3I, the process of forming recess structures1203can include recessing sacrificial layers404under sacrificial gate structures1002to form sacrificial layers1204via a selective etching process. By way of example and not limitation, channels layers within channel region122can be Si layers and sacrificial layers404can be SiGe layers, where the selective etching process can be a drying etching process that is selective towards SiGe. For example, halogen-based chemistries can exhibit etch selectivity that is higher for Ge and lower for Si. Therefore, halogen gases can etch Ge faster than Si. Further, halogen gases can etch SiGe faster than Si. Thus, the selective etching process can be designed not to remove the channel layers after forming recess structures1203. In some embodiments, the halogen-based chemistries can include fluorine-based and/or chlorine-based gasses. Alternatively, a wet etch chemistry with high selectivity towards SiGe can be used. By way of example and not limitation, a wet etch chemistry can include a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) (SPM), or a mixture of ammonia hydroxide with H2O2and water (APM). The filling of each recess structure1203can include depositing a blanket film in recess structures1201and1203, and removing the blanket film that is outside recess structures1203. The processes for forming and removing the blanket film can use similar techniques as forming gate spacer1154. For example, the process of forming the blanket film can include depositing a dielectric material using CVD or ALD; the process of removing the blanket film can include using a dry etch process, a wet etch process, or a combination thereof. In some embodiments, as shown inFIG.13, each inner spacer254can have a thickness t1range from about 1 nm to about 9 nm.

In some embodiments, the process of forming inner spacer254can also remove a portion of gate spacer1254to form gate spacer1354. For example, spacers1354A and1354B can be formed by respectively removing an upper portion of spacers1254A and1254B during the process of forming inner spacers254. In some embodiments, gate spacer1354can be substantially the same as gate spacer1254after forming inner spacers254. As a result, spacer structure1304can include gate spacer1354and inner spacers254.

Referring toFIG.2, in operation310, after forming spacer structure1304, source-drain regions124can be formed by epitaxially growing source-drain stacks in recess structures1201. The epitaxial growth of source-drain regions124can use a similar epitaxial growth process as growing channel layers for forming channel region122and/or sacrificial layers404. In some embodiments, the epitaxial growth process can grow at least one SiGe layer or at least one Si layer to form source-drain regions124. For example, as shown inFIG.3K, the epitaxial growth process can grow three SiGe layers in recess structures1201. The epitaxial growth process can in-situ dope source-drain regions124using p-type doping precursors or n-type doping precursors. By way of example and not limitation, the p-type doping precursors can include diborane (B2H6), boron trifluoride (BF3), and the n-type doping precursors can include phosphine (PH3), arsine (AsH3), or other suitable materials. In some embodiments, the epitaxial growth process can form source-drain regions124, where a top of source-drain regions124can be above a top of topmost channel layer (e.g.,122A) within channel region122. In some embodiments, the epitaxial growth process can form source-drain regions124, where a top of source-drain regions124can be substantially coplanar with a bottom of sacrificial gate structures1002. In some embodiments, the epitaxial growth process for forming source-drain regions124can form vertical structures1402from vertical structures1202, where vertical structure1402can be an embodiment of FET106.

Further, in operation310, a CESL1622and insulating layer206can be formed as described with reference toFIGS.3L-3M. The process of forming CESL1622and insulating layer206can include depositing a CESL1522and an insulating layer1506(shown inFIG.15). CESL1522can include silicon nitride, silicon oxynitride, silicon carbide, boron nitride, silicon boron nitride, a composite of boron nitride and silicon carbide, or a combination thereof, and can be formed using any suitable deposition process such as LPCVD, PECVD, CVD, or ALD.

Insulating layer1506can be a low-k dielectric material deposited using a deposition method suitable for flowable dielectric materials (e.g., flowable silicon oxide). For example, flowable silicon oxide can be deposited for insulating layer1506using FCVD. The process of forming CESL1622and insulating layer206can further include applying a polishing process (e.g., CMP) to remove a portion of CESL1522and a portion of insulating layer1506. In some embodiments, the polishing process can also remove sacrificial gate structure1002to form gate structures1602. For example, the polishing process can remove hard mask layer1008, capping layer1006, an upper portion of sacrificial gate electrode1012, and an upper portion of gate spacer1354. As a result, as shown inFIG.3M, the process of forming CESL1622and insulating layer206can concurrently form gate structure1602that includes sacrificial gate dielectric1004, sacrificial gate electrode1612placed over sacrificial gate dielectric1004, and spacers1604embedding sacrificial gate electrode1612and sacrificial gate dielectric1004, where spacers1604can include inner spacers254and gate spacer1654. In some embodiments, the polishing process can remove a portion of gate spacers1354A and1354B to respectively form gate spacers1654A and1654B. In some embodiments, referring toFIG.3M, a vertical dimension Hg of gate structure1602can be in a range from about 50 nm to about 120 nm.

Continuing to refer toFIG.2, in operation315, a recess structure is formed in each of the first gate structures1602inFIG.3M. Such recess structure is formed horizontally (e.g., in the x-direction) between insulating layers206(e.g., ILD structure130) to expose a portion of the insulating layers206. The process of forming recess structure can include recessing a portion of gate electrode1612inFIG.3Musing a dry etching process (e.g., reaction ion etching) or a wet etching process that has a higher etching rate towards gate electrode1612and a lower etching rate (e.g., selectivity larger than 1) towards gate spacer1654inFIG.3M(e.g., gate spacers1654A and1654B). In some embodiments, the gas etchants used in the dry etching process for removing gate electrode1612can include chlorine, fluorine, or bromine. In some embodiments, an NH4OH wet etch can be used to remove the portion of gate electrode1612. In some embodiments, a dry etch followed by a wet etch can be used to remove the portion of gate electrode1612.

The process of forming the recess structure can further include removing a portion of spacer1604inFIG.1604and a portion of gate spacer1654. In some embodiments, portions of spacer1654A and a portion of gate spacer1654B are removed. The process of removing the portion of spacer1604can include a dry etching process or a wet etching process that has a low etching rate (e.g., selectivity larger than 1) towards the remaining portion of gate electrode1612. In some embodiments, the dry etching process or the wet etching process for removing the portion of spacer1604can have low etching rate (e.g., selectivity larger than 1) towards CESL1622inFIG.3Mor insulating layer206. In some embodiments, the process of forming the recess structure can also include forming a CESL by removing a portion of CESL1622using similar etching process that removes the portion of spacer1604, such as a dry etch process or a wet etch process that has a higher etching rate towards CESL1622and a lower etching rate (e.g., selectivity larger than 1) towards insulating layer206and/or gate spacer1654.

The process of forming the recess structure further includes removing remaining portions of gate electrode1612via an etching process that techniques similar to the techniques used to the remove the other portions of gate electrode1612. For example, the etching process can include a dry etching process (e.g., reactive ion etching) or a wet etching process that has a higher etching rate towards gate electrode1612and a lower etching rate (e.g., selectivity larger than 1) towards sacrificial layer1204. The process of forming the recess structure can further include removing sacrificial gate dielectric1004to expose topmost of sacrificial layers1204inFIG.3Ivia any suitable etching process, such as a wet etching process. The removal of the remaining portions of the gate electrode and sacrificial gate dielectric1004can also expose side surfaces of portions of spacer1304. In some embodiments, portions of spacer1304inFIG.3Jcan represent a spacer structure. In some embodiments, a portion of spacer1304can be removed to form a spacer structure using any suitable etching process, such as a wet etching process or a dry etching process. For example, a portion of the bottom of these spacers can be removed. As a result, each gate structure1602can include recess structure that exposes a top of topmost sacrificial layer1204, the spacer structure's side surfaces, the spacer structure's a top surface, and ILD structure130's side surfaces of insulating layers206. In some embodiments, recess structure exposes a topmost channel layer within channel region122.

Further, in operation315, after forming the just described recess structure multiple isolation structures are formed. The process of forming isolation structures108can include removing one or more insulating blocks144from respective one or more vertical structures902. The process of removing the one or more insulating blocks144can include patterning a hard mask stack on a selected vertical structure902and etching insulating blocks144using the hard mask stack. As a result, after the etching process, the one or more insulating blocks144outside the hard mask stack can be removed and other insulating blocks144covered by the hard mask stack can remain in vertical structures902. By way of example and not limitation, the etching of the group of insulating blocks can include any suitable dry etching process or a wet etching process that has low etching rate (e.g., selectivity larger than 1) towards seed layer802and/or sacrificial layer404.

The process of forming isolation structure108can further include removing seed layer802and removing a portion of liners704to expose sidewalls of dielectric stack142and/or sidewalls of insulating block144. The process of removing seed layer802can include any suitable etching process that has a higher etching rate towards seed layer802and a lower etching rate towards channel regions122. For example, channel region122can include Si, and seed layer802can include SiGe. Therefore, seed layer802can be removed using a selective etching process that selectively etches SiGe from Si. The process of removing liners704can form liner under dielectric stack142; the removal of liners704can be via a dry etch process, a wet etch process, or a combination thereof. In some embodiments, the process of forming isolation structure108can also include a trimming process to reduce a width (W2) of isolation structure108. In some embodiments, isolation structure108can have a width W2equal to or larger than 6 nm, or equal to or larger than 3 nm.

In some embodiments, the process of forming isolation structure108can further include removing sacrificial layers1204using similar techniques as removing seed layer802. For example, sacrificial layer1204can be removed using a selective etching process that has a higher etching rate towards sacrificial layer1204and a lower etching rate towards channel layers122. As a result, channel layers (e.g.,122A-122D) within channel region122can become a nano-sheet structure or a nano-wire structure under each gate structure1602. In some embodiments, the process of forming the nano-sheet or the nano-wire structure for channel regions122can form vertical structures from vertical structures1202, where the vertical structure can be an embodiment of FET106. In some embodiments, the vertical structure can be a fin structure (e.g., device100A is a finFET).

Referring toFIG.2, in operation320, the first gate structure1602is replaced with a second gate structure110. The process of replacing gate structure1602with gate structure110can include filling a dielectric layer and a gate electrode in recess structures between insulating layer206of ILD structures130. The filling of a dielectric layer can include depositing (e.g., conformally) a dielectric layer over ILD structure130's side surfaces, top surface of the spacer structures, and the spacer structures's side surface. Further, the filling of a dielectric layer can further include depositing (e.g., conformally) a dielectric layer over a top and sides of each insulating block144, side surfaces of each dielectric stack142, and a top and sides of each channel layer (e.g.,122A-122D) within channel region122. In some embodiments, the filling of a dielectric layer can also include depositing (e.g., conformally) a dielectric layer over a top of a group of dielectric stack142and a bottom of each channel layers (e.g.,122A-122D) within channel region122. In some embodiments, the filling of dielectric layer can also include depositing (e.g., conformally) a dielectric layer and a gate electrode over a portion of a top of each STI region104.

The dielectric layer of gate structure110can include silicon oxide and can be formed by CVD, ALD, PVD, e-beam evaporation, or other suitable process. In some embodiments, the dielectric layer can include (i) a layer of silicon oxide, silicon nitride, and/or silicon oxynitride, (ii) a high-k dielectric material, such as hafnium oxide (HfO2), TiO2, HfZrO, Ta2O3, HfSiO4, and ZrO2, ZrSiO2, (iii) a high-k dielectric material having oxides of lithium (Li), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), scandium (Sc), yttrium (Y), Zr, Al, lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), or lutetium (Lu), or (iv) a combination thereof. The High-k dielectric material can be formed by ALD and/or other suitable processes. In some embodiments, the dielectric layer can include a single layer or a stack of insulating material layers.

After the filling of a dielectric layer, the filling of a gate electrode can include depositing a gate electrode over the dielectric layer. The gate electrode can include a single metal layer or a stack of metal layers. The stack of metal layers can include metals different from each other. In some embodiments, a gate electrode can include a suitable conductive material, such as Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, Cu, W, Co, Ni, TiC, TiAlC, TaAlC, metal alloys, and/or combinations thereof. The gate electrode can be formed by ALD, PVD, CVD, or other suitable deposition process.

The process of replacing of gate structure1602with gate structure110can also include planarizing the deposited dielectric layer and gate electrode via a polishing process (e.g., CMP). The polishing process can planarize top surfaces of the dielectric layer and the gate electrode with the top surface of ILD structure130(e.g., insulating layer206).

The process of replacing gate structure1602with gate structure110can further include recessing a portion of the planarized dielectric layer to form dielectric layer112, and recessing a portion of the planarized gate electrode. For example, a portion of the planarized dielectric layer and a portion of the planarized gate electrode that are formed over ILD structure130's side surfaces and a top surface of the spacer structures can be removed by a metal-gate-dielectric etching process. By way of example and not limitation, the metal-gate-dielectric etching process can be any suitable dry etching process and/or any suitable wet etching process that etch both the dielectric layer and the gate electrode.

After forming dielectric layer112, the process of replacing gate structure1602with gate structure110can also include forming recess structure for dielectric layer112by further recessing an upper portion of the recessed gate electrode to form gate electrode114by a metal-gate etching process. By way of example and not limitation, the metal-gate etching process can be any suitable dry etching process and/or any suitable wet etching process that can selectively etch gate electrode from dielectric layer112(e.g., etching selectivity larger than 1). For example, the metal-gate etching process can selectively remove the gate electrode, formed over dielectric layer112's upper portion from dielectric layer112. After such metal-gate etching process, dielectric layer112's upper portion can be exposed while dielectric layer112's lower portion can still be covered by the remaining gate electrode114. Since the metal-gate etching process has negligible etching effect on dielectric layer112, after the process of forming gate electrode114, dielectric layer112can remain covering the spacer structure side surfaces. As a result, dielectric layer112can protect the spacer structure's integrity during subsequent fabrication steps of integrated circuits, such as forming metal contacts/interconnections.

Further, the metal-gate etching process can be configured to selectively etch the gate electrode from insulating blocks144. For example, after the process of forming gate electrode114, gate electrode114's top surface can be substantially coplanar with or below insulating block144's top surface. In other words, insulating block144can protect the underlying dielectric stack142during the process of forming gate electrode114, thus protecting the dielectric stack's integrity after replacing gate structure1602with gate structure110.

In some embodiments, after the metal-gate etching process that forms gate electrode114, the process of forming gate electrode114can further include growing an upper electrode over gate electrode114. The upper electrode can include a low resistance metal, such as tungsten, and can be grown via a plating or a deposition using similar techniques that forms gate electrode114, such as ALD, PVD, and CVD.

Referring toFIG.2, in operation325, source/drain contact structures are formed. The process of forming S/D contact structures can include forming S/D contact openings within insulating layer206(e.g., ILD structure130). The process of forming the S/D contact openings can include removing portions of insulating layer206that are overlying source-drain regions124and removing portions of the CESL under the etched portions of insulating layer206. The process of removing the portions of insulating layer206can include patterning using photolithography to expose areas on top surface of insulating layer206corresponding to the portions of insulating layer206that are to be removed. The portions of insulating layer206can be removed by a dry etching process. The etching of the portions of insulating layer206can be followed by a dry etching of portions of the CESL under the etched portions of ILD layer130. In some embodiments, the dry etching process for removing insulating layer206and/or CESL can be a fluorine-based process.

The process of forming S/D contact structures can further include forming metal silicide layers and/or conductive regions within the S/D contact openings. In some embodiments, the metal used for forming the metal silicide layers can include Co, Ti, and Ni. In some embodiments, the metal is deposited by ALD or CVD to form diffusion barrier layers along surfaces of the S/D contact openings. This deposition of diffusion barrier layers is followed by a rapid thermal annealing process at a temperature in a range from about 700° C. to about 900° C. to form the metal silicide layers.

The process of forming conductive regions within the S/D contact openings can include deposition of a conductive material followed by a polishing process to coplanarize top surfaces of the conductive regions with top surfaces of ILD structure130. The conductive materials can be, for example, W, Al, Co, Cu, or a suitable conductive material, and can be deposited by, for example, PVD, CVD, or ALD. The polishing process for coplanarizing the conductive region with ILD structure130's top surface can be a CMP process. In some embodiments, the CMP process, can use a silicon or an aluminum abrasive with abrasive concentrations ranging from about 0.1% to about 3%. In some embodiments, the silicon or aluminum abrasive may have a pH level less than 7 for W metal in the conductive regions or can have a pH level greater than 7 for cobalt (Co) or copper (Cu) metals in the conductive regions.

Further, in operation325, an interconnect structure can be formed over gate structures110and the S/D contact structures124inFIG.1. For example, the interconnect structure can be formed over gate structures110and the S/D contact structures. In some embodiments, the process of forming the interconnect structure can include depositing a MEOL insulating layer over the S/D contact structures, forming multiple trench openings within the MEOL insulating layer to expose a portion of gate electrode114and a portion of the S/D contact structure, and forming a trench conductor into the trench openings and in contact with gate electrode114and/or S/D contact structure. In some embodiments, the process of forming the trench opening can use similar techniques as forming the S/D contact openings, such as a photolithography process, a wet etch process, or a dry etch process. In some embodiments, the process of forming trench conductor can use similar techniques as forming the contact regions for the S/D contact structure, such as a deposition process and a polishing process.

Referring toFIG.4, an embodiment of a method450in accordance with the present disclosure includes operation452of forming a first fin stack and forming a second fin stack. Examples of a forming a first fin stack and a second fin stack include the methods described for forming the multiple vertical structures402described above with reference toFIG.3F. Method450includes operation454of forming an inactive fin in an opening between the first and second fin stacks. An example of forming an inactive fin in an opening between the first and second fin stacks includes forming isolation structure108inFIG.1and portions of vertical structure902inFIG.3D. Method450includes operation456of forming a dielectric feature over the inactive fin by alternating repetitive deposition and etching steps. An example of forming a dielectric feature over the inactive fin by alternating repetitive deposition and etching steps is the process described above for forming insulating block144. In operation458of method450, gate structures are formed over the first fin stack and the second fin stack. An example of forming gate structures over the first fin stack and the second fin stack include the steps described with respect to forming gate structures1602inFIG.3M.

FIG.8is a perspective illustration of another embodiment of an IC device800at an intermediate stage of manufacturing. The device800ofFIG.8is similar to the device described above with reference toFIGS.1-7and includes three dielectric features560a,560band560cformed over inactive fin142and four metal gate structures114a-114disolated in part from each other by the combination of the three dielectric features560a,560band560cin combination with three of the inactive fins142. Device800includes shallow trench isolation features104similar to the shallow trench isolation features104described above with reference toFIGS.1,3and5formed in substrate102. Device800also includes channels122, source/drain regions124, gate electrode114, liner702and a dielectric stack or inactive fin142, such as those described above with reference toFIGS.1,3and5. Device800at this intermediate stage of manufacturing also includes an interlayer dielectric802, an etch stop layer804, a gate spacer806, an interconnect structure808(e.g., MEOL interconnect) and an insulating layer810(e.g., MEOL insulating feature). The description of dielectric feature560and its formation with reference toFIGS.1and3applies to dielectric feature560a-560cofFIG.8. Dielectric feature560bofFIG.8, includes an upper portion560U within the insulating layer810. Upper portion560U is formed in insulating layer810by a combination of patterning insulating layer810, depositing dielectric material into the patterned insulating layer810, etching the depositing dielectric material and planarizing the etched dielectric material. The formation of upper portion560U can utilize the cyclical deposition and etching of dielectric material described above with respect to the formation of dielectric feature560. Dielectric feature560balso includes a lower portion560L between gate features114band114c(which includes a metal gate structure that is common to two gate fin structures, e.g., two vertical stacks of nanosheet gate structures. In accordance with some embodiments, lower portion560L correspondence to the dielectric feature560described above. In the embodiment illustrated inFIG.8, upper portion560U has a width in the y direction that is less than the width of the lower portion560L in the y direction. In other embodiments of the present disclosure, upper portion560U has a width in the Y direction that is greater than the width of the lower portion560L in the Y direction. In accordance with embodiments of the present disclosure, end devices formed in accordance with the present disclosure include dielectric feature560bincluding upper portion560U and lower portion560L having the width characteristics described above. In accordance with embodiments of the present disclosure, the foregoing description regarding upper portion560U and lower portion560L of dielectric feature560bapplies equally to dielectric features560aand560c. In the illustrated embodiment ofFIG.8, dielectric feature560aseparates and isolates portions of gate structure114afrom portions of gate structure114b. Similarly, dielectric feature560cseparates and isolates portions of gate structure114cfrom portions of gate structure114d.

In one embodiment of the present disclosure, a device is described that includes a substrate. A first semiconductor channel is over the substrate and a second semiconductor channel, laterally offset from the first semiconductor channel, is over the substrate. A first gate structure is over and laterally surrounds the first semiconductor channel and the second gate structure is over and laterally surrounding the second semiconductor channel. An isolation structure is between the first gate structure and the second gate structure. The isolation structure includes an inactive fin and a dielectric feature extending away from an upper surface of the inactive fin. The dielectric feature is free of voids and includes multiple layers of dielectric material which are formed through alternating deposition and etching steps.

In another embodiment, the devices described include a substrate, a first semiconductor channel over the substrate and a second semiconductor channel over the substrate. The second semiconductor channel is laterally offset from the first semiconductor channel. A first gate structure is over the first semiconductor channel and a second gate structure is over the second gate structure. An inactive fin is between the first gate structure and the second gate structure. A dielectric feature is above the inactive fin and includes multiple layers of a dielectric material. The multiple layers of the dielectric material are formed via three or more atomic layer depositions and include at least one interface between adjacent layers of the multiple layers that is characterized by the presence of elemental oxygen or nitrogen.

In another embodiment of the present disclosure, a method includes forming a first fin stack and a second fin stack over a substrate. An inactive fin is formed in an opening between the first fin stack and the second fin stack. A dielectric feature is formed over the inactive fin by depositing a dielectric material over the inactive fin, etching the deposited dielectric material and repeating such depositing and etching steps at least twice. In accordance with this embodiment, a first gate structure is formed over the first fin stack and a second gate structure is formed over the second fin stack wherein the first gate structure is isolated from the second gate structure by the combination of the inactive fin and the dielectric feature.

The foregoing disclosure outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.