Patent ID: 12262532

DETAILED DESCRIPTION

The following description provides specific details, such as material compositions, shapes, and sizes, in order to provide a thorough description of embodiments of the disclosure. However, a person of ordinary skill in the art would understand that the embodiments of the disclosure may be practiced without employing these specific details. Indeed, the embodiments of the disclosure may be practiced in conjunction with conventional microelectronic device fabrication techniques employed in the industry. In addition, the description provided below does not form a complete process flow for manufacturing a microelectronic device (e.g., a memory device). The structures described below do not form a complete microelectronic device. Only those process acts and structures necessary to understand the embodiments of the disclosure are described in detail below. Additional acts to form a complete microelectronic device from the structures may be performed by conventional fabrication techniques.

Drawings presented herein are for illustrative purposes only, and are not meant to be actual views of any particular material, component, structure, device, or system. Variations from the shapes depicted in the drawings as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes or regions as illustrated, but include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as box-shaped may have rough and/or nonlinear features, and a region illustrated or described as round may include some rough and/or linear features. Moreover, sharp angles that are illustrated may be rounded, and vice versa. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of a region and do not limit the scope of the present claims. The drawings are not necessarily to scale. Additionally, elements common between figures may retain the same numerical designation.

As used herein, a “memory device” means and includes microelectronic devices exhibiting memory functionality, but not necessarily limited to memory functionality. Stated another way, and by way of non-limiting example only, the term “memory device” includes not only conventional memory (e.g., conventional volatile memory; conventional non-volatile memory), but also includes an application specific integrated circuit (ASIC) (e.g., a system on a chip (SoC)), a microelectronic device combining logic and memory, and a graphics processing unit (GPU) incorporating memory.

As used herein, the term “configured” refers to a size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one apparatus facilitating operation of one or more of the structure and the apparatus in a pre-determined way.

As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” are in reference to a major plane of a structure and are not necessarily defined by earth's gravitational field. A “horizontal” or “lateral” direction is a direction that is substantially parallel to the major plane of the structure, while a “vertical” or “longitudinal” direction is a direction that is substantially perpendicular to the major plane of the structure. The major plane of the structure is defined by a surface of the structure having a relatively large area compared to other surfaces of the structure. With reference to the figures, a “horizontal” or “lateral” direction may be perpendicular to an indicated “Z” axis, and may be parallel to an indicated “X” axis and/or parallel to an indicated “Y” axis; and a “vertical” or “longitudinal” direction may be parallel to an indicated “Z” axis, may be perpendicular to an indicated “X” axis, and may be perpendicular to an indicated “Y” axis.

As used herein, features (e.g., regions, structures, devices) described as “neighboring” one another means and includes features of the disclosed identity (or identities) that are located most proximate (e.g., closest to) one another. Additional features (e.g., additional regions, additional structures, additional devices) not matching the disclosed identity (or identities) of the “neighboring” features may be disposed between the “neighboring” features. Put another way, the “neighboring” features may be positioned directly adjacent one another, such that no other feature intervenes between the “neighboring” features; or the “neighboring” features may be positioned indirectly adjacent one another, such that at least one feature having an identity other than that associated with at least one the “neighboring” features is positioned between the “neighboring” features. Accordingly, features described as “vertically neighboring” one another means and includes features of the disclosed identity (or identities) that are located most vertically proximate (e.g., vertically closest to) one another. Moreover, features described as “horizontally neighboring” one another means and includes features of the disclosed identity (or identities) that are located most horizontally proximate (e.g., horizontally closest to) one another.

As used herein, spatially relative terms, such as “beneath,” “below,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” “right,” and the like, may be used for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Unless otherwise specified, the spatially relative terms are intended to encompass different orientations of the materials in addition to the orientation depicted in the figures. For example, if materials in the figures are inverted, elements described as “below” or “beneath” or “under” or “on bottom of” other elements or features would then be oriented “above” or “on top of” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below, depending on the context in which the term is used, which will be evident to one of ordinary skill in the art. The materials may be otherwise oriented (e.g., rotated 90 degrees, inverted, flipped) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

As used herein, “and/or” includes any and all combinations of one or more of the associated listed items.

As used herein, the phrase “coupled to” refers to structures operatively connected with each other, such as electrically connected through a direct Ohmic connection or through an indirect connection (e.g., by way of another structure).

As used herein, the term “substantially” in reference to a given parameter, property, or condition means and includes to a degree that one of ordinary skill in the art would understand that the given parameter, property, or condition is met with a degree of variance, such as within acceptable tolerances. By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be at least 90.0 percent met, at least 95.0 percent met, at least 99.0 percent met, at least 99.9 percent met, or even 100.0 percent met.

As used herein, “about” or “approximately” in reference to a numerical value for a particular parameter is inclusive of the numerical value and a degree of variance from the numerical value that one of ordinary skill in the art would understand is within acceptable tolerances for the particular parameter. For example, “about” or “approximately” in reference to a numerical value may include additional numerical values within a range of from 90.0 percent to 110.0 percent of the numerical value, such as within a range of from 95.0 percent to 105.0 percent of the numerical value, within a range of from 97.5 percent to 102.5 percent of the numerical value, within a range of from 99.0 percent to 101.0 percent of the numerical value, within a range of from 99.5 percent to 100.5 percent of the numerical value, or within a range of from 99.9 percent to 100.1 percent of the numerical value.

As used herein, “conductive material” means and includes electrically conductive material such as one or more of a metal (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), an alloy (e.g., a Co-based alloy, an Fe-based alloy, an Ni-based alloy, an Fe— and Ni-based alloy, a Co— and Ni-based alloy, an Fe— and Co-based alloy, a Co— and Ni— and Fe-based alloy, an Al-based alloy, a Cu-based alloy, a magnesium (Mg)-based alloy, a Ti-based alloy, a steel, a low-carbon steel, a stainless steel), a conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide), and a conductively-doped semiconductor material (e.g., conductively-doped polysilicon, conductively-doped germanium (Ge), conductively-doped silicon germanium (SiGe)). In addition, a “conductive structure” means and includes a structure formed of and including conductive material.

As used herein, “insulative material” means and includes electrically insulative material, such one or more of at least one dielectric oxide material (e.g., one or more of a silicon oxide (SiOx), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, an aluminum oxide (AlOx), a hafnium oxide (HfOx), a niobium oxide (NbOx), a titanium oxide (TiOx), a zirconium oxide (ZrOx), a tantalum oxide (TaOx), and a magnesium oxide (MgOx)), at least one dielectric nitride material (e.g., a silicon nitride (SiNy)), at least one dielectric oxynitride material (e.g., a silicon oxynitride (SiOxNy)), at least one dielectric oxycarbide material (e.g., silicon oxycarbide (SiOxCy)), at least one hydrogenated dielectric oxycarbide material (e.g., hydrogenated silicon oxycarbide (SiCxOyHz)), and at least one dielectric carboxynitride material (e.g., a silicon carboxynitride (SiOxCzNy)). Formulae including one or more of “x,” “y,” and “z” herein (e.g., SiOx, AlOx, HfOx, NbOx, TiOx, SiNy, SiOxNy, SiOxCy, SiCxOyHz, SiOxCzNy) represent a material that contains an average ratio of “x” atoms of one element, “y” atoms of another element, and “z” atoms of an additional element (if any) for every one atom of another element (e.g., Si, Al, Hf, Nb, Ti). As the formulae are representative of relative atomic ratios and not strict chemical structure, an insulative material may comprise one or more stoichiometric compounds and/or one or more non-stoichiometric compounds, and values of “x,” “y,” and “z” (if any) may be integers or may be non-integers. As used herein, the term “non-stoichiometric compound” means and includes a chemical compound with an elemental composition that cannot be represented by a ratio of well-defined natural numbers and is in violation of the law of definite proportions. In addition, an “insulative structure” means and includes a structure formed of and including insulative material.

As used herein, the term “homogeneous” means relative amounts of elements included in a feature (e.g., a material, a structure) do not vary throughout different portions (e.g., different horizontal portions, different vertical portions) of the feature. Conversely, as used herein, the term “heterogeneous” means relative amounts of elements included in a feature (e.g., a material, a structure) vary throughout different portions of the feature. If a feature is heterogeneous, amounts of one or more elements included in the feature may vary stepwise (e.g., change abruptly), or may vary continuously (e.g., change progressively, such as linearly, parabolically) throughout different portions of the feature. The feature may, for example, be formed of and include a stack of at least two different materials.

Unless the context indicates otherwise, the materials described herein may be formed by any suitable technique including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the technique for depositing or growing the material may be selected by a person of ordinary skill in the art. In addition, unless the context indicates otherwise, removal of materials described herein may be accomplished by any suitable technique including, but not limited to, etching (e.g., dry etching, wet etching, vapor etching), ion milling, abrasive planarization (e.g., chemical-mechanical planarization (CMP)), or other known methods.

FIGS.1through12are various views (described in further detail below) illustrating different processing stages of a method of forming a microelectronic device (e.g., a memory device, such as a DRAM device), in accordance with embodiments of the disclosure. With the description provided below, it will be readily apparent to one of ordinary skill in the art that the methods described herein may be used for forming various devices. In other words, the methods of the disclosure may be used whenever it is desired to form a microelectronic device. With the description provided below, it will be readily apparent to one of ordinary skill in the art that the methods and structures described herein may be used to form various devices and electronic systems.

FIG.1shows a simplified plan view of a first microelectronic device structure100(e.g., a first wafer) at an early processing stage of a method of forming a microelectronic device (e.g., a memory device, such as a DRAM device), in accordance with embodiments of the disclosure. As shown inFIG.1, the first microelectronic device structure100may be formed to include array regions102, digit line exit regions104(also referred to as “digit line contact socket regions”) interposed between pairs of the array regions102horizontally neighboring one another in a first horizontal direction (e.g., the Y-direction), word line exit regions106(also referred to as “word line contact socket regions”) interposed between additional pairs of the array regions102horizontally neighboring one another in a second horizontal direction (e.g., the X-direction) orthogonal to the first horizontal direction, and one or more socket regions108(also referred to as “back end of line (BEOL) contact socket regions”) horizontally neighboring some of the array regions102in one or more of the first horizontal direction and the second horizontal direction. The array regions102, the digit line exit regions104, the word line exit regions106, and the socket regions108are each described in further detail below.

The array regions102of the first microelectronic device structure100may comprise horizontal areas of the first microelectronic device structure100configured and positioned to have arrays of memory cells (e.g., arrays of DRAM cells) subsequently formed within horizontal boundaries thereof, as described in further detail below. In addition, the array regions102may also be configured and positioned to have desirable arrangements of control logic devices subsequently formed within horizontal boundaries thereof, as also described in further detail below. The control logic devices tare to be formed within the horizontal boundaries of the array regions102may be formed to be vertically offset (e.g., in the Z-direction) from the memory cells to be formed within the horizontal boundaries of the array regions102.

The first microelectronic device structure100may be formed to include a desired quantity of the array regions102. For clarity and ease of understanding of the drawings and related description,FIG.1depicts the first microelectronic device structure100as being formed to include four (4) array regions102: a first array region102A, a second array region102B, a third array region102C, and a fourth array region102D. As shown inFIG.1, the second array region102B may horizontally neighbor the first array region102A in the Y-direction, and may horizontally neighbor the fourth array region102D in the X-direction; the third array region102C may horizontally neighbor the first array region102A in the X-direction, and may horizontally neighbor the fourth array region102D in the Y-direction; and the fourth array region102D may horizontally neighbor the third array region102C in the Y-direction, and may horizontally neighboring the second array region102B in the Y-direction. In additional embodiments, the first microelectronic device structure100is formed to include a different number of array regions102. For example, the first microelectronic device structure100may be formed to include greater than four (4) array regions102, such as greater than or equal to eight (8) array regions102, greater than or equal to sixteen (16) array regions102, greater than or equal to thirty-two (32) array regions102, greater than or equal to sixty-four (64) array regions102, greater than or equal to one hundred twenty eight (128) array regions102, greater than or equal to two hundred fifty six (256) array regions102, greater than or equal to five hundred twelve (512) array regions102, or greater than or equal to one thousand twenty-four (1024) array regions102.

In addition, the first microelectronic device structure100may be formed to include a desired distribution of the array regions102. As shown inFIG.1, in some embodiments, the first microelectronic device structure100is formed to include rows103of the array regions102extending in the X-direction, and columns105of the array regions102extending in the Y-direction. The rows103of the array regions102may, for example, include a first row including the first array region102A and the third array region102C, and a second row including the second array region102B and the fourth array region102D. The columns105of the array regions102may, for example, include a first column including the first array region102A and the second array region102B, and a second column including the third array region102C and the fourth array region102D.

With continued reference toFIG.1, the digit line exit regions104of the first microelectronic device structure100may comprise horizontal areas of the first microelectronic device structure100configured and positioned to have at least some subsequently formed digit lines (e.g., bit lines, data lines) horizontally terminate therein. For an individual digit line exit region104, at least some subsequently formed digit lines operatively associated with the array regions102flanking (e.g., at opposing boundaries in the Y-direction) the digit line exit region104may have ends within the horizontal boundaries of the digit line exit region104. In addition, the digit line exit regions104may also be configured and positioned to include contact structures and routing structures with the horizontal boundaries thereof that are operatively associated with at least some of the subsequently formed digit lines. As described in further detail below, some of the contact structures to be formed within the digit line exit regions104may couple the subsequently formed digit lines to control logic circuitry of control logic devices (e.g., sense amplifier (SA) devices) to subsequently be formed within the array regions102. As shown inFIG.1, in some embodiments, the digit line exit regions104horizontally extend in the X-direction, and are horizontally interposed between horizontally neighboring rows of the array regions102in the Y-direction. The digit line exit regions104may, for example, horizontally alternate with the rows of the array regions102in the Y-direction.

An individual digit line exit region104may be divided into multiple subregions. For example, as shown inFIG.1, an individual digit line exit region104may include first digit line exit subregions104A and second digit line exit subregions104B. In some embodiments, the first digit line exit subregions104A horizontally alternate with the second digit line exit subregions104B in the X-direction. A pair (e.g., two (2)) of horizontally neighboring array regions102within an individual column of the array regions102may include one (1) of the first digit line exit subregions104A and one (1) of the second digit line exit subregions104B positioned horizontally therebetween in the Y-direction. By way of non-limiting example, the first array region102A and the second array region102B of a first column of the array regions102may include one (1) of the first digit line exit subregions104A and one (1) of the second digit line exit subregions104B positioned therebetween in the Y-direction. The one (1) of the first digit line exit subregions104A and the one (1) of the second digit line exit subregions104B may be at least partially (e.g., substantially) confined with horizontal boundaries in the X-direction of the first array region102A and the second array region102B.

As described in further detail below, an individual first digit line exit subregion104A may be configured and positioned to facilitate electrical connections between a group of digit lines (e.g., odd digit lines or even digit lines) and a group of control logic devices (e.g., odd SA devices or even SA devices) operatively associated with a portion (e.g., a half portion in the X-direction) of one (1) array region102(e.g., the first array region102A) of a pair of horizontally neighboring array regions102, and to also facilitate electrical connections between a group of additional digit lines (e.g., additional odd digit lines or additional even digit lines) and a group of additional control logic devices (e.g., additional odd SA devices or additional even SA devices) operatively associated with a corresponding portion (e.g., a corresponding half portion in the X-direction) of an additional array region102(e.g., the second array region102B) of the pair of horizontally neighboring array regions102. In addition, as also described in further detail below, an individual second digit line exit subregion104B may be configured and positioned to facilitate electrical connections between a group of further digit lines and a group of further control logic devices operatively associated with another portion (e.g., another half portion in the X-direction) of the one (1) array region102(e.g., the first array region102A), and to also facilitate electrical connections between a group of yet further digit lines and a group of yet further control logic devices operatively associated with a corresponding another portion (e.g., a corresponding another half portion in the X-direction) of the additional array region102(e.g., the second array region102B).

Still referring toFIG.1, the word line exit regions106of the first microelectronic device structure100may comprise horizontal areas of the first microelectronic device structure100configured and positioned to have at least some subsequently formed word lines (e.g., access lines) horizontally terminate therein. For an individual word line exit region106, at least some subsequently formed word lines operatively associated with the array regions102flanking (e.g., at opposing boundaries in the X-direction) the word line exit region106may have ends within the horizontal boundaries of the word line exit region106. In addition, the word line exit regions106may also be configured and positioned to include contact structures and routing structures within the horizontal boundaries thereof that are operatively associated with the subsequently formed word lines. As described in further detail below, some of the contact structures to be formed within the word line exit regions106may couple the subsequently formed word lines to control logic circuitry of additional control logic devices (e.g., sub-word line driver (SWD) devices) to subsequently be formed within the array regions102. As shown inFIG.1, in some embodiments, the word line exit regions106horizontally extend in the Y-direction, and are horizontally interposed between horizontally neighboring columns of the array regions102in the X-direction. The word line exit regions106may, for example, horizontally alternate with the columns of the array regions102in the X-direction.

An individual word line exit region106may be divided into multiple subregions. For example, as shown inFIG.1, an individual word line exit region106may include first word line exit subregions106A and second word line exit subregions106B. In some embodiments, the first word line exit subregions106A horizontally alternate with the second word line exit subregions106B in the Y-direction. A pair (e.g., two (2)) of horizontally neighboring array regions102within an individual row of the array regions102may include one (1) of the first word line exit subregions106A and one (1) of the second word line exit subregions106B positioned horizontally therebetween in the X-direction. By way of non-limiting example, the first array region102A and the third array region102C of a first row of the array regions102may include one (1) of the first word line exit subregions106A and one (1) of the second word line exit subregions106B positioned therebetween in the X-direction. The one (1) of the first word line exit subregions106A and the one (1) of the second word line exit subregions106B may be at least partially (e.g., substantially) confined with horizontal boundaries in the Y-direction of the first array region102A and the third array region102C.

As described in further detail below, an individual first word line exit subregion106A may be configured and positioned to facilitate electrical connections between a group of word lines (e.g., odd word lines or even word lines) and a group of control logic devices (e.g., odd SWD devices or even SWD devices) operatively associated with a portion (e.g., a half portion in the Y-direction) of one (1) array region102(e.g., the first array region102A) of a pair of horizontally neighboring array regions102, and to also facilitate electrical connections between a group of additional word lines (e.g., additional odd word lines or additional even word lines) and a group of additional control logic devices (e.g., additional odd SWD devices or additional even SWD devices) operatively associated with a corresponding portion (e.g., a corresponding half portion in the Y-direction) of a further array region102(e.g., the third array region102C) of the pair of horizontally neighboring array regions102. In addition, as also described in further detail below, an individual second word line exit subregion106B may be configured and positioned to facilitate electrical connections between a group of further word lines and a group of further control logic devices operatively associated with another portion (e.g., another half portion in the Y-direction) of the one (1) array region102(e.g., the first array region102A), and to also facilitate electrical connections between a group of yet further word lines and a group of yet further control logic devices operatively associated with a corresponding another portion (e.g., a corresponding another half portion in the Y-direction) of the further array region102(e.g., the third array region102C).

With continued reference toFIG.1, the socket regions108of the first microelectronic device structure100may comprise horizontal areas of the first microelectronic device structure100configured and positioned to facilitate electrical connections (e.g., by way of contact structures and routing structures formed within horizontal boundaries thereof) between subsequently formed control logic circuitry and additional subsequently formed structures (e.g., BEOL structures), as described in further detail below. The socket regions108may horizontally neighbor one or more peripheral horizontal boundaries (e.g., in the Y-direction, in the X-direction) of one or more groups of the array regions102. For clarity and ease of understanding of the drawings and related description,FIG.1depicts the first microelectronic device structure100as being formed to include one (1) socket region108horizontally neighboring a shared horizontal boundary of the second array region102B and the fourth array region102D. However, the first microelectronic device structure100may be formed to include one or more of a different quantity and a different horizontal position of socket region(s)108. As a non-limiting example, the socket region108may horizontally neighbor a shared horizontal boundary of a different group of the array regions102(e.g., a shared horizontal boundary of the third array region102C and the fourth array region102D, a shared horizontal boundary of the first array region102A and the third array region102C, a shared horizontal boundary of the first array region102A and the second array region102B). As another non-limiting example, the first microelectronic device structure100may be formed to include multiple (e.g., a plurality of, more than one) socket regions108horizontally neighboring different groups of the array regions102than one another. In some embodiments, multiple socket regions108collectively substantially horizontally surround (e.g., substantially horizontally circumscribe) the array regions102.

FIGS.2A through2Dillustrate simplified, partial longitudinal cross-sectional views of different regions of the first microelectronic device structure100previously described with reference toFIG.1.FIG.2Aillustrates a simplified, partial longitudinal cross-sectional view from the perspective of the Y-direction (so as to depict an XZ-plane) of one of the array regions102(e.g., the first array region102A) of the first microelectronic device structure100shown inFIG.1.FIG.2Billustrates a simplified, partial longitudinal cross-sectional view from the perspective of the Y-direction (so as to depict an XZ-plane) of one of the digit line exit regions104of the first microelectronic device structure100shown inFIG.1.FIG.2Cillustrates a simplified, partial longitudinal cross-sectional view from the perspective of the X-direction (so as to depict an YZ-plane) of one of the word line exit regions106of the first microelectronic device structure100shown inFIG.1.FIG.2Dillustrates a simplified, partial longitudinal cross-sectional view from the perspective of the X-direction (so as to depict an YZ-plane) of one of socket regions108of the first microelectronic device structure100shown inFIG.1.

Referring collectively toFIGS.2A through2D, the first microelectronic device structure100may be formed to include a first base semiconductor structure110, filled trenches112, and a first isolation material114. The filled trenches112vertically extend (e.g., in the Z-direction) into the first base semiconductor structure110. The first isolation material114covers and surrounds surfaces of the first base semiconductor structure110.

The first base semiconductor structure110comprises a base material or construction upon which additional features (e.g., materials, structures, devices) of the first microelectronic device structure100are formed. The first base semiconductor structure110may comprise a semiconductor structure (e.g., a semiconductor wafer), or a base semiconductor material on a supporting structure. For example, the first base semiconductor structure110may comprise a conventional silicon substrate (e.g., a conventional silicon wafer), or another bulk substrate comprising a semiconductor material. In some embodiments, the first base semiconductor structure110comprises a silicon wafer. The first base semiconductor structure110may include one or more layers, structures, and/or regions formed therein and/or thereon.

The filled trenches112may comprise trenches (e.g., openings, vias, apertures) within the first base semiconductor structure110that are at least partially (e.g., substantially) filled with the first isolation material114. The filled trenches112may, for example, be employed as shallow trench isolation (STI) structures within the first base semiconductor structure110. The filled trenches112may be formed to vertically extend partially (e.g., less than completely) through the first base semiconductor structure110. Each of the filled trenches112may be formed to exhibit substantially the same dimensions and shape as each other of the filled trenches112, or at least one of the filled trenches112may be formed to exhibit one or more of different dimensions and a different shape than at least one other of the filled trenches112. As a non-limiting example, each of the filled trenches112may be formed to exhibit substantially the same vertical dimension(s) and substantially the same vertical cross-sectional shape(s) as each other of the filled trenches112; or at least one of the filled trenches112may be formed to exhibit one or more of different vertical dimension(s) and different vertical cross-sectional shape(s) than at least one other of the filled trenches112. In some embodiments, the filled trenches112are all formed to vertically extend to and terminate at substantially the same depth within the first base semiconductor structure110. In additional embodiments, at least one of the filled trenches112is formed to vertically extend to and terminate at a relatively deeper depth within the first base semiconductor structure110than at least one other of the filled trenches112. As another non-limiting example, each of the filled trenches112may be formed to exhibit substantially the same horizontal dimension(s) and substantially the same horizontal cross-sectional shape(s) as each other of the filled trenches112; or at least one of the filled trenches112may be formed to exhibit one or more of different horizontal dimension(s) (e.g., relatively larger horizontal dimension(s), relatively smaller horizontal dimension(s)) and different horizontal cross-sectional shape(s) than at least one other of the filled trenches112. In some embodiments, at least one of the filled trenches112is formed to have one or more different horizontal dimensions (e.g., in the X-direction and/or in the Y-direction) than at least one other of the filled trenches112.

The first isolation material114may be formed of and include at least one insulative material. By way of non-limiting example, the first isolation material114may be formed of and include one or more of at least one dielectric oxide material (e.g., one or more of SiOx, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlOx, HfOx, NbOx, and TiOx), at least one dielectric nitride material (e.g., SiNy), at least one dielectric oxynitride material (e.g., SiOxNy), at least one dielectric carboxynitride material (e.g., SiOxCzNy), and amorphous carbon. In some embodiments, the first isolation material114is formed of and includes SiOx(e.g., SiO2). The first isolation material114may be substantially homogeneous, or the first isolation material114may be heterogeneous. In some embodiments, the first isolation material114is substantially homogeneous. In additional embodiments, the first isolation material114is heterogeneous. The first isolation material114may, for example, be formed of and include a stack of at least two different dielectric materials.

Referring next toFIGS.3A through3D, illustrated are simplified, partial longitudinal cross-sectional views, from the directional perspectives previously described, of the array region102(FIG.3A), the digit line exit region104(FIG.3B), the word line exit region106(FIG.3C), and the socket region108(FIG.3D) at a processing stage of the method of forming the microelectronic device following the processing stage previously described with reference toFIGS.1and2A through2D. As collectively depicted inFIGS.3A through3D, access devices116(FIG.3A) (e.g., access transistors) may be formed within the array region102(FIG.3A). In addition, digit lines118(FIGS.3A and3B) (e.g., data lines, bit lines) may be formed to be coupled to the access devices116(FIG.3A) and to horizontally extend in the Y-direction through the array region102(FIG.3A). At least some of the digit lines118(FIGS.3A and3B) may terminate (e.g., end) within the digit line exit region104(FIG.3B). Furthermore, word lines120(e.g., access lines) may be formed to be coupled to the access devices116(FIG.3A) and to horizontally extend in the X-direction through the array region102(FIG.3A). At least some of the word lines120(FIGS.3A and3C) may terminate within the word line exit region106(FIG.3C).

Referring toFIG.3A, the access devices116formed within the array region102may be employed as components of memory cells (e.g., DRAM cells) to be formed within the array region102. By way of non-limiting example, each access device116may individually be formed to include a channel region comprising a portion of the first base semiconductor structure110; a source region and a drain region each individually comprising one or more of at least one conductively doped portion of the first base semiconductor structure110and/or at least one conductive structure formed in, on, or over the first base semiconductor structure110; and at least one gate structure comprising a portion of at least one of the word lines120. Each access device116may also include a gate dielectric material (e.g., a dielectric oxide material) formed to be interposed between the channel region thereof and the gate structure thereof.

The digit lines118may exhibit horizontally elongate shapes extending in parallel in the Y-direction; and the word lines120may exhibit horizontally elongate shapes extending in parallel in the X-direction orthogonal to the Y-direction. As used herein, the term “parallel” means substantially parallel. The digit lines118and the word lines120may each individually be formed of and include conductive material. By way of non-limiting example, the digit lines118and the word lines120may each individually be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, the digit lines118and the word lines120are each individually formed of and include one or more of W, Ru, Mo, and titanium nitride (TiNy). Each of the digit lines118and each of the word lines120may individually be substantially homogeneous, or one or more of the digit lines118and/or one or more of the word lines120may individually be substantially heterogeneous. In some embodiments, each of the digit lines118and each of the word lines120are formed to be substantially homogeneous.

Still referring toFIG.3A, within the array region102, additional features (e.g., structures, materials) are also formed on, over, and/or between the access devices116, the digit lines118, and the word lines120. For example, as shown inFIG.3A, first contact structures122(e.g., digit line contact structures, also referred to as so-called “bitcon” structures) may be formed to vertically extend between and couple the access devices116to the digit lines118; second contact structures124(e.g., cell contact structures, also referred to as so-called “cellcon” structures) may be formed in contact with the access devices116and may configured and positioned to couple the access devices116to subsequently formed storage node devices (e.g., capacitors); dielectric cap structures126may be formed on or over the digit lines118; and additional dielectric cap structures128may be formed on or over the word lines120. In addition, dielectric structures (e.g., dielectric spacers, such as low-k dielectric spacers formed of and including one or more low-k dielectric materials) may be formed to intervene (e.g., horizontally intervene) between and isolate the second contact structures124and digit lines118; and further dielectric structures (e.g., gate dielectric structures, such as gate dielectric oxide structures) may be formed to intervene (e.g., horizontally intervene) between and isolate the first contact structures122and the word lines120.

The first contact structures122and the second contact structures124may individually be formed of and include at least one conductive material. In some embodiments, the first contact structures122and the second contact structures124are individually formed of and include one or more of at least one metal (e.g., W), at least one alloy, at least one conductive metal silicide (e.g., one or more of titanium silicide (TiSix), cobalt silicide (CoSix), tungsten silicide (WSix), tantalum silicide (TaSix), molybdenum silicide (MoSix), and nickel silicide (NiSix)), and at least one conductive metal nitride (e.g., one or more of TiNy, tungsten nitride (WNy), tantalum nitride (TaNy), cobalt nitride (CoNy), molybdenum nitride (MoNy), and nickel nitride (NiNy)). In addition, the dielectric cap structures126and the additional dielectric cap structures128may individually be formed of and include at least one insulative material. In some embodiments, the dielectric cap structures126and the additional dielectric cap structures128are individually formed of and include a dielectric nitride material (e.g., SiNy, such as Si3N4).

Referring toFIG.3B, within the digit line exit region104, at least some of the digit lines118may horizontally terminate (e.g., end) in the Y-direction. Each of the digit lines118horizontally extending through the array region102(FIG.3A) and horizontally terminating within the digit line exit region104may be formed to terminate at substantially the same horizontal position in the Y-direction; or at least one of the digit lines118horizontally terminating within the digit line exit region104may be formed to terminate at a different horizontal position in the Y-direction within the digit line exit region104than at least one other of the digit lines118horizontally terminating within the digit line exit region104. In some embodiments, at least some digit lines118horizontally neighboring one another in the X-direction have terminal ends (e.g., terminal surfaces) horizontally offset from one another in the Y-direction. Horizontally offsetting the terminal ends of some of the digit lines118from the terminal ends of some other of the digit lines118within the digit line exit region104may, for example, promote or facilitate desirable contact structure arrangements within the digit line exit region104.

As shown inFIG.3B, within the digit line exit region104, dummy word lines121may, optionally, be formed vertically below the digit lines118. If formed, the dummy word lines121may be formed at substantially the same vertical position (e.g., vertical elevation) within the first microelectronic device structure100(e.g., within the first base semiconductor structure110thereof) as the word lines120(FIGS.3A and3C), and may be formed to horizontally extend orthogonal to the digit lines118(e.g., in the X-direction). A material composition of the dummy word lines121may be substantially the same as a material composition of the word lines120(FIGS.3A and3C). If formed, the dummy word lines121may be electrically isolated from one another and other components (e.g., the word lines120(FIGS.3A and3C), the digit lines118) of the first microelectronic device structure100. The dummy word lines121(if any) within the digit line exit region104may not be employed as part of data paths during use and operation of a microelectronic device formed through the methods of the disclosure. In additional embodiments, the dummy word lines121are absent (e.g., omitted) from the digit line exit region104.

Referring next toFIG.3C, within the word line exit region106, at least some of the word lines120may horizontally terminate (e.g., end) in the X-direction. Each of the word lines120horizontally extending through the array region102(FIG.3A) and horizontally terminating within the word line exit region106may be formed to terminate at substantially the same horizontal position in the X-direction; or at least one of the word lines120horizontally terminating within the word line exit region106may be formed to terminate at a different horizontal position in the X-direction within the word line exit region106than at least one other of the word lines120horizontally terminating within the word line exit region106. In some embodiments, at least some word lines120horizontally neighboring one another in the Y-direction have terminal ends (e.g., terminal surfaces) horizontally offset from one another in the X-direction. Horizontally offsetting the terminal ends of some of the word lines120from the terminal ends of some other of the word lines120within the word line exit region106may, for example, promote or facilitate desirable contact structure arrangements within the word line exit region106.

As shown inFIG.3C, within the word line exit region106, dummy digit lines119may, optionally, be formed vertically above the word lines120. If formed, the dummy digit lines119may be formed at substantially the same vertical position (e.g., vertical elevation) within the first microelectronic device structure100(e.g., within the second isolation material130thereof) as the digit lines118(FIGS.3A and3B), and may be formed to horizontally extend orthogonal to the word lines120(e.g., in the Y-direction). A material composition of the dummy digit lines119may be substantially the same as a material composition of the digit lines118(FIGS.3A and3B). If formed, the dummy digit lines119may be electrically isolated from one another and the other components (e.g., the digit lines118(FIGS.3A and3B), the word lines120) of the first microelectronic device structure100. The dummy digit lines119(if any) within the word line exit region106may not be employed as part of data paths during use and operation of a microelectronic device formed through the methods of the disclosure. In additional embodiments, the dummy digit lines119are absent (e.g., omitted) from the word line exit region106.

Referring collectively toFIGS.3A through3D, the second isolation material130may be formed on or over portions of at least the first base semiconductor structure110, the access devices116(FIG.3A), the digit lines118(FIGS.3A and3B), the word lines120(FIGS.3A and3C), the second contact structures124, and the first isolation material114. The second isolation material130may be formed of and include at least one insulative material. A material composition of second isolation material130may be substantially the same as a material composition of the first isolation material114, or the material composition of the second isolation material130may be different than the material composition of the first isolation material114. In some embodiments, the second isolation material130is formed of and includes a dielectric oxide material, such as SiOx(e.g., SiO2). The second isolation material130may be substantially homogeneous, or the second isolation material130may be heterogeneous. In some embodiments, the second isolation material130is substantially homogeneous. In additional embodiments, the second isolation material130is heterogeneous. The second isolation material130may, for example, be formed of and include a stack of at least two different dielectric materials.

Referring next toFIGS.4A through4D, illustrated are simplified, partial longitudinal cross-sectional views, from the directional perspectives previously described, of the array region102(FIG.4A), the digit line exit region104(FIG.4B), the word line exit region106(FIG.4C), and the socket region108(FIG.4D) at a processing stage of the method of forming the microelectronic device following the processing stage previously described with reference toFIGS.3A through3D. As shown inFIG.4C, third contact structures132may be formed within at least the word line exit region106(FIG.4C). The third contact structures132may be formed to vertically extend (e.g., in the Z-direction) to and contact at least some of the word lines120horizontally extending (e.g., in the X-direction) into the word line exit region106. The third contact structures132may be considered to be word line contact structures (e.g., a so-called “edge of array” word line contact structures).

Referring toFIG.4C, within the word line exit region106, individual third contact structures132may be formed to be coupled to individual word lines120. Each third contact structure132may be formed to physically contact an individual word line120. For example, within the word line exit region106, each third contact structure132may be formed to vertically extend through each of the second isolation material130and a portion of the first isolation material114, and to physically contact one of the word lines120. Each third contact structure132may individually be formed to vertically terminate on, within, or below one of the word lines120. In some embodiments, each third contact structure132is individually formed to terminate at an upper surface of one of the word lines120, such that the third contact structure132is located on (e.g., physically contacts) the upper surface of the word line120. In additional embodiments, each of third contact structures132is individually formed to terminate within one of the word lines120, such that a lower boundary of the third contact structure132is positioned within vertical boundaries (e.g., between an upper boundary and a lower boundary) of the word line120. In further embodiments, each of third contact structures132is individually formed to terminate below one of the word lines120, such that a lower boundary of the third contact structure132is positioned below a lower boundary of the word line120. Outer sidewalls of each third contact structure132may physically contact inner sidewalls of an individual word line120.

The third contact structures132may be formed of and include conductive material. By way of non-limiting example, the third contact structures132may each individually be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, the third contact structures132are each individually formed of and include W. Each of the third contact structures132may be substantially homogeneous, or one or more of the third contact structures132may individually be heterogeneous. In some embodiments, each of the third contact structures132is substantially homogeneous. In additional embodiments, each of the third contact structures132is heterogeneous. Each third contact structure132may, for example, be formed of and include a stack of at least two different conductive materials.

Referring next toFIGS.5A through5D, illustrated are simplified, partial longitudinal cross-sectional views, from the directional perspectives previously described, of the array region102(FIG.5A), the digit line exit region104(FIG.5B), the word line exit region106(FIG.5C), and the socket region108(FIG.5D) at a processing stage of the method of forming the microelectronic device following the processing stage previously described with reference toFIGS.4A through4D. As collectively depicted inFIGS.5A through5D, at least one first routing tier134including first routing structures136may be formed over the access devices116(FIG.5A); storage node devices138(e.g., capacitors) may be formed over and in electrical communication with at least some of the first routing structures136within the array region102(FIG.5A); and a third isolation material140may be formed on or over portions of at least the second isolation material130, the first routing structures136(FIG.5A), and the storage node devices138(FIG.5A).

Referring toFIG.5A, the first routing structures136of the first routing tier134may be employed to facilitate electrical communication between additional features (e.g., structures, materials, devices) coupled thereto. The first routing structures136may each individually be formed of and include conductive material. By way of non-limiting example, the first routing structures136may be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, the first routing structures136are formed of and include W.

At least some of the first routing structures136may be formed and configured to couple the access devices116(e.g., access devices) to the storage node devices138(e.g., capacitors) to form memory cells142(e.g., DRAM cells) within the array region102. Each memory cell142may individually include one of the access devices116; one of the storage node devices138; one of the second contact structures124interposed between the access device116and the storage node device138; and one of the first routing structures136interposed between the second contact structure124and the storage node device138. At least some of the first routing structures136within the array region102may, for example, be configured and employed as redistribution material (RDM) structures (also referred to as “redistribution layer” (RDL) structures) to effectively shift (e.g., stagger, adjust, modify) lateral positions of semiconductor pillars of the access devices116to accommodate a desired arrangement (e.g., a hexagonal close packed arrangement) of the storage node devices138vertically over and in electrical communication with the access devices116.

WhileFIG.5Ashows the formation of a single (e.g., only one) first routing tier134including first routing structures136, multiple (e.g., more than one) first routing tiers134each individually including a desired arrangement (e.g., pattern) of first routing structures136may be formed. By of non-limiting example, two or more (e.g., three or more) of the first routing tiers134may be formed, wherein different first routing tiers134are vertically offset from one another and each individually include a desired arrangement of first routing structures136therein. At least some of the first routing structures136within at least one of the first routing tiers134may be coupled to at least some of the first routing structures136within at least one other of the first routing tiers134by way of conductive interconnect structures. In addition, whileFIGS.5A through5Dshow the first routing structures136of the first routing tier134as only being formed within the array region102(FIG.5A), the disclosure is not so limited. Rather, at least some of the first routing structures136of the first routing tier134may be formed to be at least partially positioned within one or more other regions of the first microelectronic device structure100, such as within the socket region108(FIG.5D).

Still referring toFIG.5A, within the array region102, the storage node devices138may individually be formed and configured to store a charge representative of a programmable logic state of the memory cell142including the storage node device138. In some embodiments, the storage node devices138comprise capacitors. During use and operation, a charged capacitor may represent a first logic state, such as a logic 1; and an uncharged capacitor may represent a second logic state, such as a logic 0. Each of the storage node devices138may, for example, be formed to include a first electrode (e.g., a bottom electrode), a second electrode (e.g., a top electrode), and a dielectric material between the first electrode and the second electrode.

With collective reference toFIGS.5A through5D, the third isolation material140may be formed of and include at least one insulative material. A material composition of the third isolation material140may be substantially the same as a material composition of the second isolation material130, or the material composition of the third isolation material140may be different than the material composition of the second isolation material130. In some embodiments, the third isolation material140is formed of and includes a dielectric oxide material, such as SiOx(e.g., SiO2). The third isolation material140may be substantially homogeneous, or the third isolation material140may be heterogeneous. In some embodiments, the third isolation material140is substantially homogeneous. In additional embodiments, the third isolation material140is heterogeneous. The third isolation material140may, for example, be formed of and include a stack of at least two different dielectric materials. As shown inFIGS.5A through5D, an upper surface of third isolation material140may be formed to be substantially planar and to vertically overlie upper surfaces of the storage node devices138.

Referring next toFIGS.6A through6D, illustrated are simplified, partial longitudinal cross-sectional views of different regions of a second microelectronic device structure144(e.g., a second wafer) formed separate from the first microelectronic device structure100(FIGS.5A through5D). The second microelectronic device structure144may be formed to have an arrangement of different regions (e.g., array regions, digit line exit regions, word line exit regions, socket regions) corresponding to (e.g., substantially the same as) the arrangement of different regions (e.g., the array regions102, the digit line exit regions104, the word line exit regions106, the socket regions108) previously described with reference toFIGS.1through5D.FIG.6Aillustrates a simplified, partial longitudinal cross-sectional view from the perspective of the Y-direction (so as to depict an XZ-plane) of an array region102′ of the second microelectronic device structure144.FIG.6Billustrates a simplified, partial longitudinal cross-sectional view from the perspective of the Y-direction (so as to depict an XZ-plane) of a digit line exit region104′ of the second microelectronic device structure144.FIG.6Cillustrates a simplified, partial longitudinal cross-sectional view from the perspective of the X-direction (so as to depict an YZ-plane) of a word line exit region106′ of the second microelectronic device structure144.FIG.6Dillustrates a simplified, partial longitudinal cross-sectional view from the perspective of the X-direction (so as to depict an YZ-plane) of a socket region108′ of the second microelectronic device structure144.

As shown inFIGS.6A through6D, the second microelectronic device structure144may be formed to include a second base semiconductor structure146, additional filled trenches148, transistors150(FIGS.6A and6D), a fourth isolation material152, fourth contact structures154(FIGS.6A and6D), fifth contact structures156(FIGS.6A and6D), and at least one second routing tier158(FIGS.6A and6D) including second routing structures160(FIGS.6A and6D). The additional filled trenches148vertically extend (e.g., in the Z-direction) into the second base semiconductor structure146. The transistors150at least partially vertically overlie the second base semiconductor structure146and the additional filled trenches148. The fourth contact structures154and fifth contact structures156contact the transistors150. Some of the second routing structures160contact some of the fourth contact structures154, and some other of the second routing structures160contact some of the fifth contact structures156. The fourth isolation material152may substantially cover and surround the second base semiconductor structure146, the transistors150, the fourth contact structures154, the fifth contact structures156, and the second routing structures160.

The second base semiconductor structure146comprises a base material or construction upon which additional features (e.g., materials, structures, devices) of the second microelectronic device structure144are formed. The second base semiconductor structure146may comprise a semiconductor structure (e.g., a semiconductor wafer), or a base semiconductor material on a supporting structure. For example, the second base semiconductor structure146may comprise a conventional silicon substrate (e.g., a conventional silicon wafer), or another bulk substrate comprising a semiconductor material. In some embodiments, the second base semiconductor structure146comprises a silicon wafer. The second base semiconductor structure146may include one or more layers, structures, and/or regions formed therein and/or thereon.

The additional filled trenches148may comprise trenches (e.g., openings, vias, apertures) within the second base semiconductor structure146that are at least partially (e.g., substantially) filled with the fourth isolation material152. The additional filled trenches148may, for example, be employed as STI structures within the second base semiconductor structure146. The additional filled trenches148may be formed to vertically extend partially (e.g., less than completely) through the second base semiconductor structure146. Each of the additional filled trenches148may be formed to exhibit substantially the same dimensions and shape as each other of the additional filled trenches148, or at least one of the additional filled trenches148may be formed to exhibit one or more of different dimensions and a different shape than at least one other of the additional filled trenches148. As a non-limiting example, each of the additional filled trenches148may be formed to exhibit substantially the same vertical dimension(s) and substantially the same vertical cross-sectional shape(s) as each other of the additional filled trenches148; or at least one of the additional filled trenches148may be formed to exhibit one or more of different vertical dimension(s) and different vertical cross-sectional shape(s) than at least one other of the additional filled trenches148. In some embodiments, the additional filled trenches148are all formed to vertically extend to and terminate at substantially the same depth within the second base semiconductor structure146. In additional embodiments, at least one of the additional filled trenches148is formed to vertically extend to and terminate at a relatively deeper depth within the second base semiconductor structure146than at least one other of the additional filled trenches148. As another non-limiting example, each of the additional filled trenches148may be formed to exhibit substantially the same horizontal dimension(s) and substantially the same horizontal cross-sectional shape(s) as each other of the additional filled trenches148; or at least one of the additional filled trenches148may be formed to exhibit one or more of different horizontal dimension(s) (e.g., relatively larger horizontal dimension(s), relatively smaller horizontal dimension(s)) and different horizontal cross-sectional shape(s) than at least one other of the additional filled trenches148. In some embodiments, at least one of the additional filled trenches148is formed to have one or more different horizontal dimensions (e.g., in the X-direction and/or in the Y-direction) than at least one other of the additional filled trenches148.

Referring collectively toFIGS.6A and6D, the transistors150may individually be formed to include conductively doped regions162, a channel region164, a gate structure166, and a gate dielectric material168. For an transistor150, the conductively doped regions162may be formed within the second base semiconductor structure146(e.g., formed within portions (e.g., relatively elevated portions) of the second base semiconductor structure146horizontally neighboring the additional filled trenches148horizontally neighboring at least one of the additional filled trenches148); the channel region164may be within the second base semiconductor structure146and may be horizontally interposed between the conductively doped regions162thereof; the gate structure166may vertically overlie the channel region164; and the gate dielectric material168(e.g., a dielectric oxide) may be vertically interposed (e.g., in the Z-direction) between the gate structure166and the channel region164. The conductively doped regions162of an individual transistor150may include a source region162A and a drain region162B.

Referring collectively toFIGS.6A and6D, for an individual transistor150, the conductively doped regions162thereof may comprise semiconductor material of the second base semiconductor structure146doped with one or more desired conductivity-enhancing dopants. In some embodiments, the conductively doped regions162of the transistor150comprise semiconductor material (e.g., silicon) doped with at least one N-type dopant (e.g., one or more of phosphorus, arsenic, antimony, and bismuth). In some of such embodiments, the channel region164of the transistor150comprises the semiconductor material doped with at least one P-type dopant (e.g., one or more of boron, aluminum, and gallium). In some other of such embodiments, the channel region164of the transistor150comprises substantially undoped semiconductor material (e.g., substantially undoped silicon). In additional embodiments, for an individual transistor150, the conductively doped regions162thereof comprise semiconductor material (e.g., silicon) doped with at least one P-type dopant (e.g., one or more of boron, aluminum, and gallium). In some of such additional embodiments, the channel region164of the transistor150comprises the semiconductor material doped with at least one N-type dopant (e.g., one or more of phosphorus, arsenic, antimony, and bismuth). In some other of such additional embodiments, the channel region164of the transistor150comprised substantially undoped semiconductor material (e.g., substantially undoped silicon).

Still referring collectively toFIGS.6A and6D, the gate structures166(e.g., gate electrodes) may individually horizontally extend (e.g., in the X-direction) between and be employed by multiple transistors150. The gate structures166may be formed of and include conductive material. The gate structures166may individually be substantially homogeneous, or the gate structures166may individually be heterogeneous. In some embodiments, the gate structures166are each substantially homogeneous. In additional embodiments, the gate structures166are each heterogeneous. Individual gate structures166may, for example, be formed of and include a stack of at least two different conductive materials.

Still referring toFIGS.6A and6D, the fourth contact structures154may individually be formed to vertically extend between and couple the gate structures166(and, hence, the transistors150) to one or more of the second routing structures160of the second routing tier158. The fourth contact structures154may individually be formed of and include conductive material. By way of non-limiting example, the fourth contact structures154may be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, the fourth contact structures154are formed of and include W. In additional embodiments, the fourth contact structures154are formed of and include Cu.

As also shown inFIGS.6A and6D, the fifth contact structures156may be formed to vertically extend between and couple the conductively doped regions162(e.g., the source region162A, the drain region162B) of the transistors150to some of the second routing structures160of the second routing tier158. The fifth contact structures156may individually be formed of and include conductive material. By way of non-limiting example, the fifth contact structures156may be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). A material composition of the fifth contact structures156may be substantially the same as a material composition of the fourth contact structures154, or the material composition of one or more of the fifth contact structures156may be different than the material composition of one or more of the fourth contact structures154. In some embodiments, the fifth contact structures156are formed of and include W. In additional embodiments, the fifth contact structures156are formed of and include Cu.

Referring collectively toFIGS.6A through6D, the second routing structures160of the second routing tier158may be formed of and include conductive material. By way of non-limiting example, the second routing structures160may be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, the second routing structures160are formed of and include W. In additional embodiments, the second routing structures160are formed of and include Cu. At least some of the second routing structures160may be employed as local routing structures of a microelectronic device (e.g., a memory device, such as a DRAM device).

WhileFIGS.6A through6Dshow the formation of a single (e.g., only one) second routing tier158including second routing structures160, multiple (e.g., more than one) second routing tiers158each individually including a desired arrangement (e.g., pattern) of second routing structures160may be formed. By of non-limiting example, two or more (e.g., three or more) of the second routing tiers158may be formed, wherein different second routing tiers158are vertically offset from one another and each individually include a desired arrangement of second routing structures160therein. At least some of the second routing structures160within at least one of the second routing tiers158may be coupled to at least some of the second routing structures160within at least one other of the second routing tiers158by way of conductive interconnect structures.

With continued collective reference toFIGS.6Athough6D, the transistors150, the second routing structures160, the fourth contact structures154, the fifth contact structures156may form control logic circuitry of various control logic devices170(FIGS.6A and6D) configured to control various operations of various features (e.g., the memory cells142(FIG.6A)) of a microelectronic device (e.g., a memory device, such as a DRAM device) to be formed through the methods of disclosure. In some embodiments, the control logic devices170comprise CMOS circuitry. As a non-limiting example, the control logic devices170may include one or more (e.g., each) of charge pumps (e.g., VCCP charge pumps, VNEGWLcharge pumps, DVC2 charge pumps), delay-locked loop (DLL) circuitry (e.g., ring oscillators), Vddregulators, drivers (e.g., main word line drivers, sub word line drivers (SWD)), page buffers, decoders (e.g., local deck decoders, column decoders, row decoders), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSAs), PMOS sense amplifiers (PSAs)), repair circuitry (e.g., column repair circuitry, row repair circuitry), I/O devices (e.g., local I/O devices), memory test devices, array multiplexers (MUX), error checking and correction (ECC) devices, self-refresh/wear leveling devices, and other chip/deck control circuitry. Different regions (e.g., the array region102′ (FIG.6A), the socket region108′ (FIG.6D)) may have different control logic devices170formed within horizontal boundaries thereof.

Still referring toFIGS.6A through6D, the fourth isolation material152covering and surrounding the second base semiconductor structure146, the transistors150(FIGS.6A and6D), the gate structures166(FIGS.6A and6D), the fourth contact structures154(FIGS.6A and6D), the fifth contact structures156(FIGS.6A and6D), and the second routing structures160(FIGS.6A and6D) may be formed of and include at least one insulative material. A material composition of the fourth isolation material152may be substantially the same as a material composition of the third isolation material140(FIGS.5A through5D) of the first microelectronic device structure100(FIGS.5A through5D), or the material composition of the fourth isolation material152may be different than the material composition of the third isolation material140(FIGS.5A through5D). In some embodiments, the fourth isolation material152is formed of and includes a dielectric oxide material, such as SiOx(e.g., SiO2). The fourth isolation material152may be substantially homogeneous, or the fourth isolation material152may be heterogeneous. In some embodiments, the fourth isolation material152is substantially homogeneous. In additional embodiments, the fourth isolation material152is heterogeneous. The fourth isolation material152may, for example, be formed of and include a stack of at least two different dielectric materials. An upper surface of the fourth isolation material152may be formed to vertically overlie upper boundaries (e.g., upper surfaces) of the second routing structures160(FIGS.6A through6D).

As collectively shown inFIGS.6A through6D, at least one first sacrificial material172may be formed on or over the fourth isolation material152. In some embodiments, the first sacrificial material172is formed on an upper surface of the fourth isolation material152. The first sacrificial material172may be formulated and configured to bond to additional material of an additional microelectronic device structure (e.g., a third microelectronic device structure) to be attached to the second microelectronic device structure144, as described in further detail below. The first sacrificial material172may, for example, be employed to protect or otherwise mitigate damage to features (e.g., materials, structures, devices) of the second microelectronic device structure144during subsequent processing acts, as also described in further detail below. In some embodiments, the first sacrificial material172is formed of and includes at least one insulative material. A material composition of the first sacrificial material172may be substantially the same as a material composition of the fourth isolation material152, or the material composition of the first sacrificial material172may be different than the material composition of the fourth isolation material152. In some embodiments, the first sacrificial material172is formed of and includes a dielectric oxide material, such as SiOx(e.g., SiO2). The first sacrificial material172may be substantially homogeneous, or the first sacrificial material172may be heterogeneous. In some embodiments, the first sacrificial material172is substantially homogeneous. In additional embodiments, the first sacrificial material172is heterogeneous. The first sacrificial material172may, for example, be formed of and include a stack of at least two different dielectric materials. An upper surface of the first sacrificial material172may be formed to be substantially planar and to vertically overlie an upper boundary (e.g., an upper surface) of the fourth isolation material152. In additional embodiments, the first sacrificial material172is not formed on or over the fourth isolation material152.

Referring next toFIGS.7A through7D, illustrated are simplified, partial longitudinal cross-sectional views, from the directional perspectives previously described, of the array region102′ (FIG.7A), the digit line exit region104′ (FIG.7B), the word line exit region106′ (FIG.7C), and the socket region108′ (FIG.7D) at a processing stage of the method of forming the microelectronic device following the processing stage previously described with reference toFIGS.6A through6D. As collectively depicted inFIGS.7A through7D, a third microelectronic device structure174(e.g., a third wafer) including an additional base structure176and a second sacrificial material178may be attached to the first sacrificial material172(or the fourth isolation material152, if formation of the first sacrificial material172is omitted) of the second microelectronic device structure144to form a first microelectronic device structure assembly180.

The additional base structure176of the third microelectronic device structure174comprises a base material or construction upon which additional features (e.g., materials, structures, devices) are formed. In some embodiments, the additional base structure176comprises a wafer. The additional base structure176may be formed of and include one or more of semiconductor material (e.g., one or more of a silicon material, such as monocrystalline silicon or polycrystalline silicon (also referred to herein as “polysilicon”); silicon-germanium; germanium; gallium arsenide; a gallium nitride; gallium phosphide; indium phosphide; indium gallium nitride; and aluminum gallium nitride), a base semiconductor material on a supporting structure, glass material (e.g., one or more of BSP, PSG, FSG, BPSG, aluminosilicate glass, an alkaline earth boro-aluminosilicate glass, quartz, titania silicate glass, and soda-lime glass), and ceramic material (e.g., one or more of p-AlN, SOPAN, AlN, aluminum oxide (e.g., sapphire; α-Al2O3), and silicon carbide). By way of non-limiting example, the additional base structure176may comprise a semiconductor wafer (e.g., a silicon wafer), a glass wafer, or a ceramic wafer. The additional base structure176may include one or more layers, structures, and/or regions formed therein and/or thereon.

The second sacrificial material178of the third microelectronic device structure174may be formed on or over the additional base structure176. The second sacrificial material178may be formulated and configured to bond to the first sacrificial material172(or the fourth isolation material152, if formation of the first sacrificial material172is omitted) of the second microelectronic device structure144. In some embodiments, the second sacrificial material178is formed of and includes at least one insulative material. A material composition of the second sacrificial material178may be substantially the same as a material composition of the first sacrificial material172(and/or the fourth isolation material152) of the second microelectronic device structure144; or the material composition of the second sacrificial material178may be different than the material composition of the first sacrificial material172(and/or the fourth isolation material152). In some embodiments, the second sacrificial material178is formed of and includes a dielectric oxide material, such as SiOx(e.g., SiO2). The second sacrificial material178may be substantially homogeneous, or the second sacrificial material178may be heterogeneous. In some embodiments, the second sacrificial material178is substantially homogeneous. In additional embodiments, the second sacrificial material178is heterogeneous. The second sacrificial material178may, for example, be formed of and include a stack of at least two different dielectric materials.

To attach the third microelectronic device structure174to the second microelectronic device structure144, the third microelectronic device structure174may be vertically inverted (e.g., flipped upside down in the Z-direction), the second sacrificial material178thereof may be provided in physical contact with the first sacrificial material172(or the fourth isolation material152, if formation of the first sacrificial material172is omitted), and the second sacrificial material178and the first sacrificial material172(and/or the fourth isolation material152) may be exposed to annealing conditions to form bonds (e.g., oxide-to-oxide bonds) between the second sacrificial material178and the first sacrificial material172(or the fourth isolation material152). By way of non-limiting example, the second sacrificial material178and the first sacrificial material172(and/or the fourth isolation material152) may be exposed to a temperature greater than or equal to about 400° C. (e.g., within a range of from about 400° C. to about 800° C., greater than about 800° C.) to form oxide-to-oxide bonds between the fourth isolation material152and the first sacrificial material172(or the fourth isolation material152). In some embodiments, the first sacrificial material172and the second sacrificial material178are exposed to at least one temperature greater than about 800° C. to form oxide-to-oxide bonds between the first sacrificial material172and the second sacrificial material178.

As shown inFIGS.7A through7D, bonding the second sacrificial material178to the first sacrificial material172(or the fourth isolation material152, if formation of the first sacrificial material172is omitted) may form a connected sacrificial structure182. InFIGS.7A through7D, the second sacrificial material178and the first sacrificial material172of the connected sacrificial structure182are distinguished from one another by way of a dashed line. However, the second sacrificial material178to the first sacrificial material172(or the fourth isolation material152) may be integral and continuous with one another. Put another way, the connected sacrificial structure182may be a substantially monolithic structure including the second sacrificial material178as a first region thereof, and the first sacrificial material172(or the fourth isolation material152) as a second region thereof. For the connected sacrificial structure182, the second sacrificial material178thereof may be attached to the first sacrificial material172(or the fourth isolation material152) thereof without a bond line.

Referring next toFIGS.8A through8D, illustrated are simplified, partial longitudinal cross-sectional views, from the directional perspectives previously described, of the array region102′ (FIG.8A), the digit line exit region104′ (FIG.8B), the word line exit region106′ (FIG.8C), and the socket region108′ (FIG.8D) at a processing stage of the method of forming the microelectronic device following the processing stage previously described with reference toFIGS.7A through7D. As collectively depicted inFIGS.8A through8D, the first microelectronic device structure assembly180may be vertically inverted (e.g., flipped upside down in the Z-direction), and an upper portion of the second base semiconductor structure146(FIGS.7A through7D) may be removed to expose (e.g., uncover) the fourth isolation material152within the additional filled trenches148(FIGS.7A through7D) and form a second semiconductor tier184(FIGS.8A and8D) including second semiconductor structures186separated from one another by remaining portions of the fourth isolation material152. Thereafter, a fifth isolation material188may be formed on or over surfaces of the second semiconductor structures186and the fourth isolation material152.

The upper portion of the second base semiconductor structure146(FIGS.7A through7D) vertically overlying the additional filled trenches148(FIGS.7A through7D) following the vertical inversion of the first microelectronic device structure assembly180may be removed using at least one conventional wafer thinning process (e.g., a conventional CMP process; a conventional etching process, such as a conventional dry etching process, or a conventional wet etching process). The second semiconductor structures186may be formed to exhibit a desired vertical height (e.g., in the Z-direction) through the material removal process. The material removal process may also remove portions (e.g., upper portions following the vertical inversion of the first microelectronic device structure assembly180) of the fourth isolation material152.

Referring collectively toFIGS.8A through8D, the fifth isolation material188formed to cover the second semiconductor structures186(FIGS.8A and8D) and the fourth isolation material152may be formed of and include at least one insulative material. A material composition of the fifth isolation material188may be substantially the same as a material composition of the fourth isolation material152, or the material composition of the fifth isolation material188may be different than the material composition of the fourth isolation material152. In some embodiments, the fifth isolation material188is formed of and includes a dielectric oxide material, such as SiOx(e.g., SiO2). The fifth isolation material188may be substantially homogeneous, or the fifth isolation material188may be heterogeneous. In some embodiments, the fifth isolation material188is substantially homogeneous. In additional embodiments, the fifth isolation material188is heterogeneous. The fifth isolation material188may, for example, be formed of and include a stack of at least two different dielectric materials. As shown inFIGS.8A through8D, an upper surface of the fifth isolation material188may be formed to be substantially planar.

Referring next toFIGS.9A through9D, illustrated are simplified, partial longitudinal cross-sectional views, from the directional perspectives previously described, of the array region102(FIG.9A), the digit line exit region104(FIG.9B), the word line exit region106(FIG.9C), and the socket region108(FIG.9D) previously described with reference toFIGS.2A through2Dat a processing stage of the method of forming the microelectronic device following the processing stages previously described with reference toFIGS.5A through5DandFIGS.8A through8D. As depicted inFIGS.9A through9D, following the processing stage previously described with reference toFIGS.8A through8D, the first microelectronic device structure assembly180may be vertically inverted (e.g., flipped upside down in the Z-direction) and the fifth isolation material188thereof may be attached (e.g., bonded, such as through oxide-oxide bonding) to the third isolation material140of the first microelectronic device structure100to form a second microelectronic device structure assembly190. Attaching (e.g., bonding) the fifth isolation material188of the first microelectronic device structure assembly180to the third isolation material140of the first microelectronic device structure assembly180may form a second connected isolation structure192of the second microelectronic device structure assembly190. Following the attachment of the fifth isolation material188to the third isolation material140, at least the additional base structure176(FIGS.8A through8D) of the first microelectronic device structure assembly180may be removed.

As depicted inFIGS.9A through9D, the first microelectronic device structure assembly180may be attached to the first microelectronic device structure100such that array regions102′ (FIG.8A), digit line exit regions104′ (FIG.8B), word line exit region106′ (FIG.8C), and socket regions108′ (FIG.8D) of the first microelectronic device structure assembly180horizontally overlap (e.g., are substantially horizontally aligned with) array regions102(FIG.5A), digit line exit regions104(FIG.5B), word line exit regions106(FIG.5C), and socket regions108(FIG.5D) of the first microelectronic device structure100, respectively. Thus, inFIGS.9A through9D, the array region102(FIG.9A), the digit line exit region104(FIG.9B), the word line exit region106(FIG.9C), and the socket region108(FIG.9D) respectively include features of the array region102′ (FIG.8A), the digit line exit region104′ (FIG.8B), the word line exit region106′ (FIG.8C), and the socket region108′ (FIG.8D) of the first microelectronic device structure assembly180following the processing stage previously described with reference toFIGS.8A through8D. While the different regions shown inFIGS.9A through9Dwere previously described as different regions of the first microelectronic device structure100(FIGS.1and5A through5D) formed by processing the first microelectronic device structure100according to the methods of the disclosure, it will be understood that these regions become regions of a microelectronic device of the disclosure formed using the first microelectronic device structure100and the first microelectronic device structure assembly180, as described in further detail below. Thus, these different regions are not limited to the features (e.g., structures, materials, devices) and/or portions of features of the first microelectronic device structure100. Instead, these regions evolve through the methods of the disclosure to encompass and include additional features (e.g., additional structures, additional materials, additional devices), portions of additional features, and/or modified features.

To form the second microelectronic device structure assembly190, the fifth isolation material188of the first microelectronic device structure assembly180may be provided in physical contact with the third isolation material140of the first microelectronic device structure100, and then the fifth isolation material188and the third isolation material140may be exposed to annealing conditions to form bonds (e.g., oxide-to-oxide bonds) between the fifth isolation material188and the third isolation material140. By way of non-limiting example, the fifth isolation material188and the third isolation material140may be exposed to a temperature greater than or equal to about 400° C. (e.g., within a range of from about 400° C. to about 800° C., greater than about 800° C.) to form oxide-to-oxide bonds between the fifth isolation material188and the third isolation material140. In some embodiments, the fifth isolation material188and the third isolation material140are exposed to at least one temperature greater than about 800° C. to form oxide-to-oxide bonds between the fifth isolation material188and the third isolation material140.

InFIGS.9A through9D, the fifth isolation material188and the third isolation material140of the second connected isolation structure192are distinguished from one another by way of a dashed line. However, the fifth isolation material188and the third isolation material140may be integral and continuous with one another. Put another way, second connected isolation structure192may be a substantially monolithic structure including the fifth isolation material188as a first region (e.g., an upper region) thereof, and the third isolation material140as a second region (e.g., a lower region) thereof. For the second connected isolation structure192, the fifth isolation material188thereof may be attached to the third isolation material140thereof without a bond line.

As shown inFIGS.9A through9D, following the removal of the additional base structure176(FIGS.8A through8D), the connected sacrificial structure182may be at least partially maintained. In some such embodiments, at least one additional isolation material (e.g., dielectric oxide material, such as SiOx; dielectric nitride material, such as SiNy) may be formed (e.g., deposited, grown) on or over the maintained portion of the connected sacrificial structure182. In further embodiments, in addition to the additional base structure176(FIGS.8A through8D), the connected sacrificial structure182is also substantially removed (e.g., is not at least partially maintained). In some such further embodiments, at least one additional isolation material (e.g., dielectric oxide material, such as SiOx; dielectric nitride material, such as SiNy) may be formed on or over remaining portions of the fourth isolation material152following the substantial removal of the connected sacrificial structure182.

Referring next toFIGS.10A through10D, illustrated are simplified, partial longitudinal cross-sectional views, from the directional perspectives previously described, of the array region102(FIG.10A), the digit line exit region104(FIG.10B), the word line exit region106(FIG.10C), and the socket region108(FIG.10D) at a processing stage of the method of forming the microelectronic device following the processing stage previously described with reference toFIGS.9A through9D. As collectively depicted inFIGS.10B and10C, sixth contact structures194may be formed within the digit line exit region104(FIG.10B) and the word line exit region106(FIG.10C). As described in further detail below, some of the sixth contact structures194may be formed to be coupled to digit lines118(FIG.10B) within the digit line exit region104(FIG.10B), and some other of the sixth contact structures194may be formed to be coupled to word lines120(FIG.10C) within the word line exit region106(FIG.10C). The formation of the sixth contact structures194may reduce contact misalignment risks and/or alleviate the need for relatively complex contact alignment operations and systems as compared to conventional methods of the forming contact structures coupled to conductive line structures (e.g., digit lines, word lines). Registration marks for the formation of the sixth contact structures194may be clearly observed through the isolation materials (e.g., dielectric oxide materials, such as SiOx) of the second microelectronic device structure assembly190.

Referring toFIG.10B, within the digit line exit region104, a first group194A of the sixth contact structures194may be formed to contact at least some of the digit lines118horizontally extending (e.g., in the Y-direction) into the digit line exit region104. Each sixth contact structure194of the first group194A of sixth contact structures194may be considered to be a digit line contact structure (e.g., a so-called “edge of array” digit line contact structure). As shown inFIG.10B, each sixth contact structure194of the first group194A of sixth contact structures194may be formed to physically contact an individual digit line118. For example, within the digit line exit region104, each sixth contact structure194of the first group194A may be formed to vertically extend through each of a remainder of the connected sacrificial structure182(if any), the fourth isolation material152, the second connected isolation structure192, and the third isolation material140, and to physically contact one of the digit lines118. Each sixth contact structure194of the first group194A may individually be formed to vertically terminate on, within, or below one of the digit lines118. In some embodiments, each sixth contact structure194of the first group194A is individually formed to terminate at an upper surface of one of the digit lines118, such that the sixth contact structure194is located on (e.g., physically contacts) the upper surface of the digit line118. In additional embodiments, each sixth contact structure194of the first group194A is individually formed to terminate within one of the digit lines118, such that a lower boundary of the sixth contact structure194is positioned within vertical boundaries (e.g., between an upper boundary and a lower boundary) of the digit line118. In further embodiments, each sixth contact structure194of the first group194A is individually formed to terminate below one of the digit lines118, such that a lower boundary of the sixth contact structure194is positioned below a lower boundary of the digit line118. Outer sidewalls of each sixth contact structure194of the first group194A may physically contact inner sidewalls of an individual digit line118.

Referring next toFIG.10C, within the word line exit region106, a second group194B of the sixth contact structures194may be formed to be coupled to at least some of the word lines120horizontally extending (e.g., in the X-direction) into the word line exit region106. Each sixth contact structure194of the second group194B of sixth contact structures194may be considered to be a word line contact structure (e.g., a so-called “edge of array” word line contact structure). As shown inFIG.10C, each sixth contact structure194of the second group194B may be formed to physically contact an individual third contact structure132contacting an individual word line120within the word line exit region106. For example, within the word line exit region106, each sixth contact structure194of the second group194B may be formed to vertically extend through each of a remainder of the connected sacrificial structure182(if any), the fourth isolation material152, the second connected isolation structure192, and the third isolation material140, and to physically contact one of the third contact structures132. In some embodiments, each sixth contact structure194of the second group194B is individually formed to terminate at an upper surface of one of the third contact structures132, such that the sixth contact structure194is located on (e.g., physically contacts) the upper surface of the third contact structure132. In additional embodiments, each sixth contact structure194of the second group194B is individually formed to terminate within one of the third contact structures132, such that a lower boundary of the sixth contact structure194is positioned within vertical boundaries (e.g., between an upper boundary and a lower boundary) of the third contact structure132.

Referring collectively toFIGS.10B and10C, the sixth contact structures194(including the first group194A (FIG.10B) and the second group194B (FIG.10C) thereof) may be formed of and include conductive material. By way of non-limiting example, the sixth contact structures194may each individually be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, the sixth contact structures194are each individually formed of and include W. Each of the sixth contact structures194may be substantially homogeneous, or one or more of the sixth contact structures194may individually be heterogeneous. In some embodiments, each of the sixth contact structures194is substantially homogeneous. In additional embodiments, each of the sixth contact structures194is heterogeneous. Each sixth contact structure194may, for example, be formed of and include a stack of at least two different conductive materials.

Referring next toFIGS.11A through11D, illustrated are simplified, partial longitudinal cross-sectional views, from the directional perspectives previously described, of the array region102(FIG.11A), the digit line exit region104(FIG.11B), the word line exit region106(FIG.11C), and the socket region108(FIG.11D) at a processing stage of the method of forming the microelectronic device following the processing stage previously described with reference toFIGS.10A through10D. As collectively depicted inFIGS.11A through11D, BEOL structures may be formed over the second routing tier158and the sixth contact structures194(FIGS.11B and11C). For example, at least one third routing tier196(FIGS.11A and11D) including third routing structures198(FIGS.11A and11D) may be formed over the second routing tier158; at least one fourth routing tier200including fourth routing structures202may be formed over the third routing tier196(FIGS.11A and11D); and at least one fifth routing tier204including fifth routing structures206may be formed over the fourth routing tier200. One or more of the third routing structures198(FIGS.11A and11D) of the third routing tier196(FIGS.11A and11D) may be coupled to one or more of the second routing structures160of the second routing tier158by way of seventh contact structures208(FIGS.11A and11D). In addition, one or more of the fourth routing structures202of the fourth routing tier200may be coupled to one or more of the third routing structures198(FIGS.11A and11D) of the third routing tier196(FIGS.11A and11D) by way of eighth contact structures210(FIGS.11A and11D). Furthermore, one or more of the fifth routing structures206(e.g., one or more conductive pad structures) of the fifth routing tier204may be coupled to one or more of the fourth routing structures202of the fourth routing tier200by way of ninth contact structures212(FIG.11D). In additional embodiments, at least some (e.g., all) of the ninth contact structures212(FIG.11D) are omitted (e.g., are not formed), and one or more of the fifth routing structures206of the fifth routing tier204are formed to directly physically contact one or more of the fourth routing structures202of the fourth routing tier200.

The third routing structures198(FIGS.11A and11D), the fourth routing structures202, the fifth routing structures206, the seventh contact structures208(FIGS.11A and11D), the eighth contact structures210(FIGS.11A and11D), and the ninth contact structures212(FIG.11D) (if any) may each be formed of and include conductive material. By way of non-limiting example, the third routing structures198(FIGS.11A and11D), the fourth routing structures202, the fifth routing structures206, the seventh contact structures208(FIGS.11A and11D), the eighth contact structures210(FIGS.11A and11D), and the ninth contact structures212(FIG.11D) may individually be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, the third routing structures198(FIGS.11A and11D) are each formed of and include W; the fourth routing structures202are each formed of and include Cu; the fifth routing structures206are formed of and include Al; and the seventh contact structures208(FIGS.11A and11D), the eighth contact structures210(FIGS.11A and11D), and the ninth contact structures212(FIG.11D) are each formed of and include W.

Still referring to collectively toFIGS.11A through11D, a sixth isolation material214may be formed on or over portions of at least the third routing structures198(FIGS.11A and11D), the fourth routing structures202, the fifth routing structures206, the seventh contact structures208(FIGS.11A and11D), the eighth contact structures210(FIGS.11A and11D), and the ninth contact structures212(FIG.11D) (if any). The sixth isolation material214may be formed of and include at least one insulative material. In some embodiments, the sixth isolation material214is formed of and includes a dielectric oxide material, such as SiOx(e.g., SiO2). The sixth isolation material214may be substantially homogeneous, or the sixth isolation material214may be heterogeneous. In some embodiments, the sixth isolation material214is substantially homogeneous. In additional embodiments, the sixth isolation material214is heterogeneous. The sixth isolation material214may, for example, be formed of and include a stack of at least two different dielectric materials. In addition, one or more openings may be formed within the sixth isolation material214to expose (and, hence, facilitate access to) one or more portions of one or more of the fifth routing structures206(e.g., one or more conductive pad structures) of the fifth routing tier204.

As shown inFIGS.11A through11D, the method described above with reference toFIGS.1and2A through11Dmay effectuate the formation of a microelectronic device216(e.g., a memory device, such as a DRAM device) including the features (e.g., structures, materials, devices) previously described herein. In some embodiments, at least some of the third routing structures198(FIGS.11A and11D), the fourth routing structures202, and the fifth routing structures206are employed as global routing structures for the microelectronic device216. The third routing structures198(FIGS.11A and11D), the fourth routing structures202, and the fifth routing structures206may, for example, be configured to receive global signals from an external bus, and to relay the global signals to other features (e.g., structures, devices) of the microelectronic device216.

Thus, in accordance with embodiments of the disclosure, a method of forming a microelectronic device comprises forming a microelectronic device structure comprising memory cells, digit lines, word lines, and at least one isolation material covering and surrounding the memory cells, the digit lines, and the word lines. An additional microelectronic device structure comprising control logic devices and at least one additional isolation material covering and surrounding the control logic devices is formed. The additional microelectronic device structure is attached to the microelectronic device structure to form an assembly. The control logic devices overlie the memory cells within the assembly. Contact structures are formed to extend through the at least one isolation material and the at least one additional isolation material after forming the assembly. Some of the contact structures are coupled to some of the digit lines and some of the control logic devices. Some other of the contact structures are coupled to some of the word lines and some other of the control logic devices.

Referring next toFIG.12, depicted is a simplified plan view of the microelectronic device216illustrating an arrangement of different control logic sections (described in further detail below) within individual different regions (e.g., the array regions102, such as the first array region102A, the second array region102B, the third array region102C, and the fourth array region102D; the socket regions108) of the microelectronic device216, as well as routing arrangements to different control logic devices (e.g., corresponding to the control logic devices170(FIGS.11A and11D)) within the different control logic sections, in accordance with embodiments of the disclosure. The different control logic devices of the different control logic sections may be positioned vertically above (e.g., in the Z-direction) the memory cells142(FIG.11A) of the microelectronic device216. At least some of the different control logic devices may be coupled to the memory cells142(FIG.11A) in the manner previously described with reference toFIGS.11A through11D. For clarity and ease of understanding the description, not all features (e.g., structures, materials, devices) of the microelectronic device216previously described with reference toFIGS.11A through11Dare illustrated inFIG.12.

As shown inFIG.12, within a horizontal area of each array region102, the microelectronic device216may be formed to include a desired arrangement of sense amplifier (SA) sections218and sub-word line driver (SWD) sections220. The SA sections218may include SA devices coupled to the digit lines118of the microelectronic device216, as described in further detail below. The digit lines118may vertically underlie (e.g., in the Z-direction) the SA devices of the SA sections218within the microelectronic device216. The SWD sections220may include SWD devices coupled to the word lines120of the microelectronic device216, as also described in further detail below. The word lines120may vertically underlie (e.g., in the Z-direction) the SWD devices of the SWD sections220within the microelectronic device216.

The SA sections218within a horizontal area of an individual array region102(e.g., the first array region102A, the second array region102B, the third array region102C, or the fourth array region102D) may include a first SA section218A and a second SA section218B. For an individual array region102, the first SA section218A and the second SA section218B may be positioned at or proximate opposite corners (e.g., diagonally opposite corners) of the array region102than one another. For example, as shown inFIG.12, for an individual array region102, the first SA section218A may be positioned at or proximate a first corner222A of the array region102, and the second SA section218B may be positioned at or proximate a second corner222B of the array region102located diagonally opposite (e.g., kitty-corner) the first corner222A.

For each SA section218(e.g., the first SA section218A, the second SA section218B) within an individual array region102, the SA devices of the SA section218may be coupled to a group of the digit lines118horizontally extending (e.g., in the Y-direction) through the array region102by way of digit line routing and contact structures224. The digit line routing and contact structures224may, for example, correspond to some of the routing structures (e.g., some of the second routing structures160(FIGS.11A and11B)) and some of the contact structures (e.g., some of the first group194A (FIG.11B) of the sixth contact structures194(FIG.11B)) previously described herein.

The SA devices of the SA sections218of array regions102horizontally neighboring one another in the Y-direction (e.g., the first array region102A and the second array region102B; the third array region102C and the fourth array region102D) may be coupled to different groups of digit lines118than one another. For example, each of the SA sections218(e.g., each of the first SA section218A and the second SA section218B) of the first array region102A may include so-called “even” SA devices coupled to even digit lines118B of the microelectronic device216by way of the digit line routing and contact structures224associated with the SA sections218; and each of the SA sections218(e.g., each of the first SA section218A and the second SA section218B) of the second array region102B may include so-called “odd” SA devices coupled to odd digit lines118A of the microelectronic device216by way of the digit line routing and contact structures224associated with the SA sections218; or vice versa. The even digit lines118B of the microelectronic device216may horizontally alternate with the odd digit lines118A of the microelectronic device216in the X-direction. The SA devices of each of the SA sections218of the first array region102A may not be coupled to any odd digit lines118A; and the SA devices of each of the SA sections218of the second array region102B may not be coupled to any even digit lines118B; or vice versa. Similarly, each of the SA sections218(e.g., each of the first SA section218A and the second SA section218B) of the third array region102C horizontally neighboring the first array region102A in the X-direction may include additional even SA devices coupled to additional even digit lines118B of the microelectronic device216by way of the digit line routing and contact structures224associated with the SA sections218; and each of the SA sections218(e.g., each of the first SA section218A and the second SA section218B) of the fourth array region102D horizontally neighboring the second array region102B in the X-direction may include additional odd SA devices coupled to additional odd digit lines118A of the microelectronic device216by way of the digit line routing and contact structures224associated with the SA sections218; or vice versa.

As shown inFIG.12, the SA devices (e.g., odd SA devices or even SA devices) within an individual SA section218of an individual array region102may be coupled to digit lines (e.g., odd digit lines118A or even digit lines118B) horizontally extending through the array region102, and may also be coupled to additional digit lines (e.g., additional odd digit lines118A or additional even digit lines118B) horizontally extending through another array region102horizontally neighboring the array region102in the Y-direction. For example, some odd SA devices within the first SA section218A of the second array region102B may be coupled to odd digit lines118A horizontally extending through the second array region102B by way of some digit line routing and contact structures224extending to and through the first digit line exit subregion104A horizontally neighboring the second array region102B in the Y-direction; and some additional odd SA devices within the first SA section218A of the second array region102B may be coupled to additional odd digit lines118A horizontally extending through the first array region102A by way of some additional digit line routing and contact structures224extending to and through the first digit line exit subregion104A. As another example, some even SA devices within the second SA section218B of the first array region102A may be coupled to even digit lines118B horizontally extending through the first array region102A by way of some digit line routing and contact structures224extending to and through the second digit line exit subregion104B horizontally neighboring the first array region102A in the Y-direction; and some additional even SA devices within the second SA section218B of the first array region102A may be coupled to additional even digit lines118B horizontally extending through the second array region102B by way of some additional digit line routing and contact structures224extending to and through the second digit line exit subregion104B.

With maintained reference toFIG.12, the SWD sections220within a horizontal area of an individual array region102(e.g., the first array region102A, the second array region102B, the third array region102C, or the fourth array region102D) may include a first SWD section220A and a second SWD section220B. For an individual array region102, the first SWD section220A and the second SWD section220B may be positioned at or proximate different corners than the first SA section218A and a second SA section218B. In addition, the corner of the array region102associated with first SWD section220A may oppose (e.g., diagonally oppose) the corner of the array region102associated with second SWD section220B. For example, as shown inFIG.12, for an individual array region102, the first SWD section220A may be positioned at or proximate a third corner222C of the array region102, and the second SWD section220B may be positioned at or proximate a fourth corner222D of the array region102located diagonally opposite (e.g., kitty-corner) the third corner222C.

For each SWD section220(e.g., the first SWD section220A, the second SWD section220B) within an individual array region102, the SWD devices of the SWD section220may be coupled to a group of the word lines120horizontally extending (e.g., in the X-direction) through the array region102by way of word line routing and contact structures226. The word line routing and contact structures226may, for example, correspond to some of the routing structures (e.g., some of the second routing structures160(FIGS.11A and11C)) and some of the contact structures (e.g., some of the third contact structures132(FIG.11C); some of the second group194B (FIG.11C) of the sixth contact structures194(FIG.11C)) previously described herein.

The SWD devices of the SWD sections220of array regions102horizontally neighboring one another in the X-direction (e.g., the first array region102A and the third array region102C; the second array region102B and the fourth array region102D) may be coupled to different groups of word lines120than one another. For example, each of the SWD sections220(e.g., each of the first SWD section220A and the second SWD section220B) of the first array region102A may include so-called “even” SWD devices coupled to even word lines120B of the microelectronic device216by way of the word line routing and contact structures226associated with the SWD sections220; and each of the SWD sections220(e.g., each of the first SWD section220A and the second SWD section220B) of the third array region102C may include so-called “odd” SWD devices coupled to odd word lines120A of the microelectronic device216by way of the word line routing and contact structures226associated with the SWD sections220; or vice versa. The even word lines120B of the microelectronic device216may horizontally alternate with the odd word lines120A of the microelectronic device216in the Y-direction. The SWD devices of each of the SWD sections220of the first array region102A may not be coupled to any odd word lines120A; and the SWD devices of each of the SWD sections220of the third array region102C may not be coupled to any even word lines120B; or vice versa. Similarly, each of the SWD sections220(e.g., each of the first SWD section220A and the second SWD section220B) of the second array region102B horizontally neighboring the first array region102A in the Y-direction may include additional even SWD devices coupled to additional even word lines120B of the microelectronic device216by way of the word line routing and contact structures226associated with the SWD sections220; and each of the SWD sections220(e.g., each of the first SWD section220A and the second SWD section220B) of the fourth array region102D horizontally neighboring the third array region102C in the Y-direction may include additional odd SWD devices coupled to additional odd word lines120A of the microelectronic device216by way of the word line routing and contact structures226associated with the SWD sections220; or vice versa.

As shown inFIG.12, the SWD devices (e.g., odd SWD devices or even SWD devices) within an individual SWD section220of an individual array region102may be coupled to word lines (e.g., odd word lines120A or even word lines120B) horizontally extending through the array region102, and may also be coupled to additional word lines (e.g., additional odd word lines120A or additional even word lines120B) horizontally extending through another array region102horizontally neighboring the array region102in the X-direction. For example, some odd SWD devices within the first SWD section220A of the third array region102C may be coupled to odd word lines120A horizontally extending through the third array region102C by way of some word line routing and contact structures226extending to and through the second word line exit subregion106B horizontally neighboring the third array region102C in the X-direction; and some additional odd SWD devices within the first SWD section220A of the third array region102C may be coupled to additional odd word lines120A horizontally extending through the first array region102A by way of some additional word line routing and contact structures226extending to and through the second word line exit subregion106B. As another example, some even SWD devices within the second SWD section220B of the first array region102A may be coupled to even word lines120B horizontally extending through the first array region102A by way of some word line routing and contact structures226extending to and through the first word line exit subregion106A horizontally neighboring the first array region102A in the X-direction; and some additional even SWD devices within the second SWD section220B of the first array region102A may be coupled to additional even word lines120B horizontally extending through the third array region102C by way of some additional word line routing and contact structures226extending to and through the first word line exit subregion106A.

With maintained reference toFIG.12, within a horizontal area of each array region102, the microelectronic device216may include additional control logic sections individually including additional control logic devices (e.g., control logic devices other than SA devices and SWD devices). For example, for each array region102, additional control logic sections228may be positioned horizontally between (e.g., at relatively more horizontally central positions within the array region102) the SA sections218and the SWD sections220. The additional control logic sections228may include, but are not limited to, column decoder device sections including column decoder device, and main word line (MWD) sections including MWD devices.

Still referring toFIG.12, within a horizontal area of each socket region108, the microelectronic device216may include further control logic sections230individually including further control logic devices (e.g., control logic devices in addition to those located within the horizontal areas of the array regions102). At least some of the further control logic devices within the further control logic sections230may have different configurations and different operational functions than the control logic devices located within the horizontal areas of the array regions102. By way of non-limiting example, the further control logic sections230may include bank logic sections including bank logic devices.

Thus, in accordance with embodiments of the disclosure, a method of forming a microelectronic device comprises forming a first semiconductor wafer comprising memory cells within array regions, digit lines coupled to the memory cells and terminating within digit line exit regions neighboring the array regions, and word lines coupled to the memory cells and terminating within word line exit regions neighboring the array regions. A second semiconductor wafer comprising control logic devices is formed. The second semiconductor wafer is attached to the first semiconductor wafer through oxide-oxide bonding such that some of the control logic devices are positioned within the array regions. Digit line contact structures are formed within the digit line exit regions after attaching the second semiconductor wafer to the first semiconductor wafer. The digit line contact structures are coupled to the digit lines and some of the control logic devices. Word line contact structures are formed within the word line exit regions after attaching the second semiconductor wafer to the first semiconductor wafer. The word line contact structures are coupled to the word lines and some other of the control logic devices.

Furthermore, in accordance with embodiments of the disclosure, a microelectronic device comprises array regions, digit line exit regions, and word line exit regions. The array regions individually comprise memory cells, digit lines, word lines, and control logic devices. The memory cells comprise access devices and storage node devices. The digit lines are coupled to the access devices and extend in a first direction. The word lines are coupled to the access devices and extend in a second direction orthogonal to the first direction. The control logic devices are over and in electrical communication with the memory cells. The digit line exit regions horizontally alternate with the array regions in the first direction. The digit line exit regions individually comprise portions of the digit lines extending beyond the array regions adjacent thereto, and digit line contact structures individually continuously vertically extending from the portions of the digit lines to routing structures vertically overlying transistors of the control logic devices. The word line exit regions horizontally alternate with the array regions in the second direction. The word line exit regions individually comprise portions of the word lines extending beyond the array regions adjacent thereto, conductive contact structures on the portions of the word lines, and word line contact structures individually continuously vertically extending from the conductive contact structures to the routing structures vertically overlying the transistors of the control logic devices.

Microelectronic devices (e.g., the microelectronic device216(FIGS.11A through11D)) in accordance with embodiments of the disclosure may be used in embodiments of electronic systems of the disclosure. For example,FIG.13is a block diagram illustrating an electronic system300according to embodiments of disclosure. The electronic system300may comprise, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular telephone, a digital camera, a personal digital assistant (PDA), portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet such as, for example, an iPAD® or SURFACE® tablet, an electronic book, a navigation device, etc. The electronic system300includes at least one memory device302. The memory device302may comprise, for example, a microelectronic device (e.g., the microelectronic device216(FIGS.11A through11D and12)) previously described herein. The electronic system300may further include at least one electronic signal processor device304(often referred to as a “microprocessor”). The electronic signal processor device304may, optionally, comprise a microelectronic device (e.g., the microelectronic device216(FIGS.11A through11D and12)) previously described herein. While the memory device302and the electronic signal processor device304are depicted as two (2) separate devices inFIG.13, in additional embodiments, a single (e.g., only one) memory/processor device having the functionalities of the memory device302and the electronic signal processor device304is included in the electronic system300. In such embodiments, the memory/processor device may include a microelectronic device (e.g., the microelectronic device216(FIGS.11A through11D and12)) previously described herein. The electronic system300may further include one or more input devices306for inputting information into the electronic system300by a user, such as, for example, a mouse or other pointing device, a keyboard, a touchpad, a button, or a control panel. The electronic system300may further include one or more output devices308for outputting information (e.g., visual or audio output) to a user such as, for example, a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device306and the output device308comprise a single touchscreen device that can be used both to input information to the electronic system300and to output visual information to a user. The input device306and the output device308may communicate electrically with one or more of the memory device302and the electronic signal processor device304.

Thus, in accordance with embodiments of the disclosure, an electronic system comprises an input device, an output device, a processor device operably connected to the input device and the output device, and a memory device operably connected to the processor device. The memory device comprises memory array regions, a digit line contact region between two of the memory array regions neighboring one another in a first direction, and a word line contact region between two other of the memory array regions neighboring one another in a second direction perpendicular to the first direction. The memory array regions each comprise dynamic random access memory (DRAM) cells, digit lines coupled to the DRAM cells, word lines coupled to the DRAM cells, and control logic circuitry overlying and in electrical communication with the DRAM cells. The control logic circuitry comprises transistors including gate structures vertically overlying channel structures. The digit line contact region comprises end portions of some of the digit lines extending past horizontal boundaries of the two of the memory array regions; and digit line contacts on the end portions of the some of the digit lines and continuously extending to a vertical position of the control logic circuitry. The word line contact region comprises end portions of some of the word lines extending past horizontal boundaries of the two other of the memory array regions; conductive contacts on the end portions of the some of the word lines; and word line contacts on the conductive contacts and continuously extending to the vertical position of the control logic circuitry.

The structures, devices, and methods of the disclosure advantageously facilitate one or more of improved microelectronic device performance, reduced costs (e.g., manufacturing costs, material costs), increased miniaturization of components, and greater packaging density as compared to conventional structures, conventional devices, and conventional methods. The structures, devices, and methods of the disclosure may also improve scalability, efficiency, and simplicity as compared to conventional structures, conventional devices, and conventional methods.

While the disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, the disclosure is not limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the scope of the following appended claims and their legal equivalent. For example, elements and features disclosed in relation to one embodiment may be combined with elements and features disclosed in relation to other embodiments of the disclosure.