Patent ID: 12190829

DETAILED DESCRIPTION

Advantages and features of the present disclosure, and implementation methods thereof will be clarified through following example embodiments described with reference to the accompanying drawings. The present disclosure may, however, be embodied in different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure may be sufficiently thorough and complete to assist those skilled in the art to fully understand the scope of the present disclosure.

A shape, a size, a ratio, an angle, and a number disclosed in the drawings for describing embodiments of the present disclosure are merely an example. Thus, the present disclosure is not limited to the illustrated details. Like reference numerals refer to like elements throughout. In the following description, when the detailed description of the relevant known function or configuration is determined to unnecessarily obscure an important point of the present disclosure, the detailed description of such known function or configuration may be omitted. In a case where terms “comprise,” “have,” and “include” described in the present specification are used, another part may be added unless a more limiting term, such as “only,” is used. The terms of a singular form may include plural forms unless referred to the contrary.

In construing an element, the element is construed as including an error or tolerance range even where no explicit description of such an error or tolerance range.

In describing a position relationship, when a position relation between two parts is described as, for example, “on,” “over,” “under,” or “next,” one or more other parts may be disposed between the two parts unless a more limiting term, such as “just” or “direct(ly),” is used.

It will be understood that, although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.

The term unit as used herein includes, a circuit, a functional block, a module in a circuit, or a system including one or more circuits or functional elements.

Features of various embodiments of the present disclosure may be partially or overall coupled to or combined with each other, and may be variously inter-operated with each other and driven technically as those skilled in the art can sufficiently understand. Embodiments of the present disclosure may be carried out independently from each other, or may be carried out together in co-dependent relationship.

Hereinafter, an organic light emitting diode display device including a selecting unit according to embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, like reference numerals designate like elements throughout. When a detailed description of well-known functions or configurations related to this document is determined to unnecessarily cloud a gist of the inventive concept, the detailed description thereof may be omitted or may be made brief.

FIG.1is a view showing an organic light emitting diode display device according to an embodiment of the present disclosure.

InFIG.1, an organic light emitting diode (OLED) display device110according to an embodiment of the present disclosure includes a timing controlling unit120, a data driving unit130, a gate driving unit140, a selecting unit150and a display panel160. Each of the timing controlling unit120, data driving unit130, gate driving unit140, and selecting unit150may comprise circuits or portions of circuits.

The timing controlling unit120generates an image data, a data control signal and a gate control signal using an image signal and a plurality of timing signals including a data enable signal, a horizontal synchronization signal, a vertical synchronization signal and a clock signal transmitted from an external system such as a graphic card or a television system. The image data and the data control signal are transmitted on line125to the data driving unit130, and the gate control signal is transmitted to the gate driving unit140on line127.

The data driving unit130generates a data voltage (data signal) using the data control signal and the image data transmitted to it from the timing controlling unit120and transmits the data voltage to a data line DL of the display panel160.

The gate driving unit140generates a gate1voltage (gate1signal) Scan1(ofFIG.2), a gate2voltage (gate2signal) Scan2(ofFIG.2), a gate3voltage (gate3signal) Scan3(ofFIG.2), an emission1voltage (emission1signal) Em1(ofFIG.2) and an emission2voltage (emission2signal) Em2(ofFIG.2) using the gate control signal transmitted on line127from the timing controlling unit120and applies the gate1voltage Scan1, the gate2voltage Scan2, the gate3voltage Scan3, the emission1voltage Em1and the emission2voltage Em2to a gate line GL of the display panel160. However, it is to be noted that, various gate voltages other than Scan1, Scan2, Scan3and various emission voltages other than Em1and Em2may be generated by the gate driving unit to drive the subpixel of the display device, and embodiments of the present disclosure are not limited thereto.

The gate driving unit140may have a gate in panel (GIP) type to be formed in a non-display area NDA of a substrate of the display panel160having the gate line GL, the data line DL and a subpixel SP.

The selecting unit150selectively connects the data driving unit130and the subpixel SP of the display panel160. The detailed structure of the selecting unit150will be illustrated with reference toFIGS.2to10.

The display panel160includes a display area DA at a central portion thereof and a non-display area NDA surrounding the display area DA. The display panel160displays an image using the gate voltage, the emission voltage and the data voltage. For displaying an image, the display panel160includes a plurality of subpixels SP, a plurality of gate lines GL and a plurality of data lines DL in the display area DA.

For example, the plurality of subpixels SP may include red, green and blue subpixels.

The gate line GL and the data line DL cross each other to define the subpixel SP, and the subpixel SP is connected to the gate line GL and the data line DL.

The data driving unit130, the selecting unit150and the subpixel of the display panel160of the OLED display device110will be illustrated with reference to a drawing.

FIG.2is a circuit diagram showing a data driving unit, a selecting unit and a subpixel of an organic light emitting diode display device according to an embodiment of the present disclosure.

InFIG.2, the OLED display device110according to an embodiment of the present disclosure includes the data driving unit130, the selecting unit150and the subpixel SP.

The data driving unit130includes first and second switches SW1and SW2, analog-digital converter ADC and an output channel CH.

The first switch SW1is connected among a pre-charge voltage Vpr, the second switch SW2and the output channel CH, and the second switch SW2is connected among the first switch SW1, the analog-digital converter ADC and the output channel CH. For example, the first switch SW1may be connected between the pre-charge voltage Vpr and the output channel CH, and the second switch SW2may be connected between the analog-digital converter ADC and a common node of the first switch SW1and the output channel CH, as shown inFIG.2.

The analog-digital converter ADC is connected between the second switch SW2and the timing controlling unit120(ofFIG.1), and the output channel CH is connected among the first and second switches SW1and SW2and the selecting unit150.

The selecting unit150includes first, second and third mux transistors Tm1, Tm2and Tm3.

The first mux transistor Tm1is connected to a first selection signal Se1, an anode reset voltage Var and a reset line RL and switches a connection between the anode reset voltage Var and the reset line RL according to the first selection signal Se1.

The second mux transistor Tm2is connected to a second selection signal Se2, the output channel CH and the reset line RL and switches a connection between the output channel CH and the reset line RL according to the second selection signal Se2.

The third mux transistor Tm3is connected to a third selection signal Se3, the output channel CH and the data line DL and switches a connection between the output channel CH and the data line DL according to the third selection signal Se3.

The subpixel SP includes a driving transistor Td, first, second, third, fourth, fifth, sixth, and seventh transistors T1, T2, T3, T4, T5, T6, and T7(also referred to as first to seventh transistors T1to T7for descriptive purposes), a storage capacitor Cst, an anode reset capacitor Car and a light emitting diode De.

For example, the driving transistor Td and the second to seventh transistors T2to T7may be a polycrystalline silicon thin film transistor (TFT) of a positive type, and the first transistor T1may be an oxide semiconductor TFT of a negative type.

The driving transistor Td is switched (turned on and off) according to a voltage of a first electrode of the storage capacitor Cst. A gate electrode of the driving transistor Td is connected to the first electrode of the storage capacitor Cst and a drain electrode of the first transistor T1, a source electrode of the driving transistor Td is connected to a drain electrode of the second transistor T2and a source electrode of the third transistor T3, and a drain electrode of the driving transistor Td is connected to a source electrode of the first transistor T1, a source electrode of the fourth transistor T4and a drain electrode of the fifth transistor T5.

The first transistor T1as a sampling transistor is switched according to a gate1 voltage Scan1. A gate electrode of the first transistor T1is connected to the gate1 voltage Scan1, the source electrode of the first transistor T1is connected to the drain electrode of the driving transistor Td, the source electrode of the fourth transistor T4and a drain electrode of the fifth transistor T5, and the drain electrode of the first transistor T1is connected to the first electrode of the storage capacitor Cst and the gate electrode of the driving transistor Td.

The second transistor T2as a switching transistor is switched according to a gate2 voltage Scan2. A gate electrode of the second transistor T2is connected to the gate2 voltage Scan2, a source electrode of the second transistor T2is connected to the data line DL (data voltage Vdata), and the drain electrode of the second transistor T2is connected to the source electrode of the driving transistor Td and the source electrode of the third transistor T3.

The third transistor T3is switched according to an emission1 voltage Em1. A gate electrode of the third transistor T3is connected to the emission1 voltage Em1, the source electrode of the third transistor T3is connected to the source electrode of the driving transistor Td and the drain electrode of the second transistor T2, and a drain electrode of the third transistor T3is connected to a high level voltage Vdd and a second electrode of the storage capacitor Cst.

The fourth transistor T4as an emission transistor is switched according to the emission1voltage Em1. A gate electrode of the fourth transistor T4is connected to the emission1voltage Em1, the source electrode of the fourth transistor T4is connected the drain electrode of the driving transistor Td, the source electrode of the first transistor T1and the drain electrode of the fifth transistor T5, and a drain electrode of the fourth transistor T4is connected to a source electrode of the sixth transistor T6and a source electrode of the seventh transistor T7.

The fifth transistor T5is switched according to a gate3voltage Scan3. A gate electrode of the fifth transistor T5is connected to the gate3voltage Scan3, a source electrode of the fifth transistor T5is connected to an initial voltage Vini, and the drain electrode of the fifth transistor T5is connected to the drain electrode of the driving transistor Td, the source electrode of the first transistor T1and the source electrode of the fourth transistor T4.

The sixth transistor T6is switched according to the gate2voltage Scan2. A gate electrode of the sixth transistor T6is connected to the gate2voltage Scan2, the source electrode of the sixth transistor T6is connected to the drain electrode of the fourth transistor T4and the source electrode of the seventh transistor T7, and a drain electrode of the sixth transistor T6is connected to the reset line RL (reset voltage Var) and a first electrode of the anode reset capacitor Car.

The seventh transistor T7as an emission transistor is switched according to the emisson2voltage Scan2. A gate electrode of the seventh transistor T7is connected to the emission2voltage Scan2, the source electrode of the seventh transistor T7is connected to the drain electrode of the fourth transistor T4and the source electrode of the sixth transistor T6, and a drain electrode of the seventh transistor T7is connected to an anode of the light emitting diode De.

The storage capacitor Cst stores the data voltage Vdata and a threshold voltage Vtht of the driving transistor Td. The first electrode of the storage capacitor Cst is connected to the gate electrode of the driving transistor Td and the drain electrode of the first transistor T1, and the second electrode of the storage capacitor Cst is connected to the drain electrode of the third transistor T3and the high level voltage Vdd.

The anode reset capacitor Car stores the anode reset voltage Var. The first electrode of the anode reset capacitor Car is connected to the reset line RL (reset voltage Var) and the drain electrode of the sixth transistor T6, and a second electrode of the anode reset capacitor Car is connected to a ground voltage GND.

The light emitting diode De is connected between the seventh transistor T7and a low level voltage Vss and emits a light of a luminance proportional to a current of the driving transistor Td. The anode of the light emitting diode De is connected to the drain electrode of the seventh transistor T7, and a cathode of the light emitting diode De is connected to the low level voltage Vss.

In the OLED display device110according to an embodiment of the present disclosure, the selecting unit150transmits the pre-charge voltage Vpr to the reset line RL and transmits a threshold voltage Vthd of the light emitting diode De to the analog-digital converter ADC to compensate deterioration of the light emitting diode De.

FIG.3is a view showing a plurality of signals of an emission compensation frame of an organic light emitting diode display device according to an embodiment of the present disclosure,FIGS.4A and4Bare views showing operation of first and second time periods, respectively, of an organic light emitting diode display device according to an embodiment of the present disclosure, andFIGS.5A and5Bare views showing a threshold voltage variation of a light emitting diode of an organic light emitting diode display device according to an embodiment of the present disclosure.

InFIG.3, an emission compensation frame ECF for compensating the light emitting diode De includes a first time period TP1where the pre-charge voltage Vpr is applied to the light emitting diode De and a second time period TP2where the threshold voltage Vthd of the light emitting diode De is detected.

InFIGS.3and4A, during the first time period TP1, the first switch SW1of the data driving unit130has an on state and the second switch SW2of the data driving unit130has an off state, and the pre-charge voltage Vpr is connected to the output channel CH.

The first and third selection signals Se1and Se3become a high level voltage, the second selection signal Se2becomes a low level voltage, the first and third mux transistors Tm1and Tm3are turned off, and the second mux transistor Tm2is turned on. The output channel CH of the data driving unit130is connected to the reset line RL of the subpixel SP.

The emission1voltage Em1, the gate1voltage Scan1and the gate3voltage Scan3of the subpixel SP become a high level voltage Vh, the emission2voltage Em2and the gate2voltage Scan2of the subpixel SP become a low level voltage Vl, the first, third, fourth and fifth transistors T1, T3, T4and T5are turned off, and the second, sixth and seventh transistors T2, T6and T7are turned on. Further, the initial voltage Vini becomes a first voltage V1.

Accordingly, the pre-charge voltage Vpr of the data driving unit130is transmitted to the anode of the light emitting diode De of the subpixel SP.

InFIGS.3and4B, during the second time period TP2, the first switch SW1of the data driving unit130has an off state, the second switch SW2of the data driving unit130has an on state, and the analog-digital converter ADC is connected to the output channel CH.

The first and third selection signals Se1and Se3of the selecting unit150become a high level voltage, the second selection signal Se2of the selecting unit150becomes a low level voltage, the first and third mux transistors Tm1and Tm3are turned off, and the second mux transistor Tm2is turned on. The output channel CH of the data driving unit130is connected to the reset line RL of the subpixel SP.

The emission1voltage Em1, the gate1voltage Scan1and the gate3voltage Scan3of the subpixel SP become a high level voltage Vh, the emission2voltage Em2and the gate2voltage Scan2of the subpixel SP become a low level voltage Vl, the first, third, fourth and fifth transistors T1, T3, T4and T5are turned off, and the second, sixth and seventh transistors T2, T6and T7are turned on. Further, the initial voltage Vini becomes a first voltage V1.

Accordingly, a voltage of the anode of the light emitting diode De is transmitted to the analog-digital converter ADC of the data driving unit130.

The voltage at the anode of the light emitting diode De may be interpreted as the threshold voltage Vthd.

InFIG.5A, when the light emitting diode De is charged by applying the pre-charge voltage Vpr to the anode of the light emitting diode De as during the first time period TP1, a current flows through the light emitting diode De at a voltage equal to or greater than the threshold voltage Vthd. As a usage time of the light emitting diode De increases, a current capability of the light emitting diode De decreases and the threshold voltage Vthd of the light emitting diode De increases.

For example, the current of the light emitting diode De may decrease from a first current I1to a second current I2, and then to a third current I3, and the threshold voltage Vthd of the light emitting diode De may increase from a first threshold voltage Vthd1to a second threshold voltage Vthd2, and then to a third threshold voltage Vthd3.

InFIG.5B, when the light emitting diode De is discharged by stopping application of the pre-charge voltage Vpr to the light emitting diode De as during the second time period TP2, a current flows through the light emitting diode De until a voltage of the anode of the light emitting diode De becomes the threshold voltage Vthd (during a discharging time tpr) and then the light emitting diode De becomes an off state. As a usage time of the light emitting diode De increases, the threshold voltage Vthd of the light emitting diode De increases.

For example, the threshold voltage Vthd of the light emitting diode De may increase from the first threshold voltage Vthd1to the second threshold voltage Vthd2, and then to the third threshold voltage Vthd3.

The pre-charge voltage Vpr is applied to the anode of the light emitting diode De during the first time period TP1, and the light emitting diode De is discharged and the voltage of the anode of the light emitting diode De becomes the threshold voltage Vthd during the second time period TP2.

For obtaining a sufficient application time of the pre-charge voltage Vpr and a sufficient discharging time tpr of the light emitting diode De, a sum of the first and second time periods TP1and TP2may be equal to or greater than 1000 times one horizontal period1H for an image display, and each of the first and second time periods TP1and TP2may be within a range of about 40% to about 60% of the sum of the first and second time periods TP1and TP2.

In the OLED display device110according to an embodiment of the present disclosure, the pre-charge voltage Vpr of the data driving unit130is applied to the anode of the light emitting diode De of the subpixel SP through the selecting unit150during the first time period TP1of the emission compensation frame ECF, and the threshold voltage Vthd of the light emitting diode De is transmitted to the analog-digital converter ADC of the data driving unit130through the selecting unit150during the second time period TP2of the emission compensation frame ECF.

Further, the analog-digital converter ADC of the data driving unit130converts the threshold voltage Vthd of an analog type into the threshold voltage Vthd of a digital type to output the threshold voltage Vthd of a digital type via line125to the timing controlling unit120. The timing controlling unit120adjusts the image data based on the threshold voltage Vthd of the light emitting diode De to generate a compensated image data and outputs the compensated image data to the data driving unit130. The data driving unit130generates a compensated data voltage Vdata using the compensated image data and applies the compensated data voltage Vdata to the data line DL of the display panel160. The display panel160displays an image using the compensated data voltage Vdata.

As a result, deterioration such as a variation of the threshold voltage Vthd of the light emitting diode De is compensated, and a display quality of an image is improved. In addition, deterioration such as a stain is minimized, and a uniformity of an image is improved.

In the OLED display device110according to an embodiment of the present disclosure, the selecting unit150transmits the current of the driving transistor Td to the analog-digital converter ADC to compensate deterioration of the first transistor T1of a sampling transistor.

FIG.6is a view showing a plurality of signals of a sampling compensation frame of an organic light emitting diode display device according to an embodiment of the present disclosure,FIGS.7A to7Care views showing operation of third to fifth time periods, respectively, of an organic light emitting diode display device according to an embodiment of the present disclosure.

InFIG.6, a sampling compensation frame SCF for compensating the first transistor T1of a sampling transistor includes a third time period TP3where the initial voltage Vini is applied to the gate electrode of the driving transistor Td, a fourth time period TP4where the data voltage Vdata and the threshold voltage Vtht are applied to the gate electrode of the driving transistor Td and a fifth time period TP5where the current of the driving transistor Td is detected.

InFIGS.6and7A, during the third time period TP3, the first and second switches SW1and SW2of the data driving unit130have an off state, and the data voltage Vdata is connected to the output channel CH.

The first and second selection signals Se1and Se2of the selecting unit150become a high level voltage, the third selection signal Se3of the selecting unit150becomes a low level voltage, the first and second mux transistors Tm1and Tm2are turned off, and the third mux transistor Tm3is turned on. The output channel CH of the data driving unit130is connected to the data line DL of the subpixel SP.

The emission1voltage Em1, the emission2voltage Em2, the gate1voltage Scan1and the gate2voltage Scan2of the subpixel SP become a high level voltage Vh, the gate3voltage Scan3of the subpixel SP becomes a low level voltage Vl, the first and fifth transistors T1and T5are turned on, and the second, third, fourth, sixth and seventh transistors T2, T3, T4, T6and T7are turned off. Further, the initial voltage Vini becomes a first voltage V1.

Accordingly, the data voltage Vdata of the data driving unit130is transmitted to the data line DL of the display panel160and the initial voltage Vini is applied to the gate electrode of the driving transistor Td and the first electrode of the storage capacitor Cst so that the gate electrode of the driving transistor Td and the first electrode of the storage capacitor Cst are initialized.

InFIGS.6and7B, during the fourth time period TP4, the first and second switches SW1and SW2of the data driving unit130have an off state, and the data voltage Vdata is connected to the output channel CH.

The first and second selection signals Se1and Se2of the selecting unit150become a high level voltage, the third selection signal Se3of the selecting unit150becomes a low level voltage, the first and second mux transistors Tm1and Tm2are turned off, and the third mux transistor Tm3is turned on. The output channel CH of the data driving unit130is connected to the data line DL of the subpixel SP.

The emission1 voltage Em1, the emission2voltage Em2, the gate1voltage Scan1and the gate3voltage Scan3of the subpixel SP become a high level voltage Vh, the gate2voltage Scan2of the subpixel SP becomes a low level voltage Vl, the first, second and sixth transistors T1, T2and T6are turned on, and the third, fourth, fifth and seventh transistors T3, T4, T5and T7are turned off. Further, the initial voltage Vini becomes a second voltage V2greater than the first voltage V1.

Accordingly, a sum (Vdata+Vtht) of the data voltage Vdata and the threshold voltage Vtht of the driving transistor Td is applied to and stored in the gate electrode of the driving transistor Td and the first electrode of the storage capacitor Cst.

InFIGS.6and7C, during the fifth time period TP5, the first switch SW1of the data driving unit130has an off state, the second switch SW2of the data driving unit130has an on state, and the analog-digital converter ADC is connected to the output channel CH.

The first and third selection signals Se1and Se3of the selecting unit150become a high level voltage, the second selection signal Se2of the selecting unit150becomes a low level voltage, the first and third mux transistors Tm1and Tm3are turned off, and the second mux transistor Tm2is turned on. The output channel CH of the data driving unit130is connected to the reset line RL of the subpixel SP.

The emission1 voltage Em1, the gate1voltage Scan1and the gate2voltage Scan2of the subpixel SP become a low level voltage Vl, the emission2voltage Em2and the gate3voltage Scan3of the subpixel SP become a high level voltage Vh, the first, fifth and seventh transistors T1, T5and T7are turned off, and the second, third, fourth and sixth transistors T2, T3, T4and T6are turned on. Further, the initial voltage Vini becomes the first voltage V1.

Accordingly, a current flows through the driving transistor Td turned on by the sum (Vdata+Vtht) of the data voltage Vdata and the threshold voltage Vtht of the driving transistor Td from the high level voltage Vdd, and the current of the driving transistor Td of the subpixel SP is transmitted to the analog-digital converter ADC of the data driving unit130.

Here, the current of the driving transistor Td reflects deterioration such as property degradation of the first transistor T1of a sampling transistor.

When the OLED display device110is driven for a relatively long time, an element property of the first transistor T1may be deteriorated due to a voltage stress. When the element property of the first transistor T1connected to the gate electrode and the drain electrode of the driving transistor Td is deteriorated, a current property of the driving transistor Td may be deteriorated.

For example, when the element property of the first transistor T1is deteriorated, the current of the driving transistor Td may be reduced.

In the OLED display device110according to an embodiment of the present disclosure, the initial voltage Vini is applied to the first electrode of the storage capacitor Cst and the gate electrode of the driving transistor Td during the third time period TP3of the sampling compensation frame SCF, the data voltage Vdata of the data driving unit130and the threshold voltage Vtht of the driving transistor Td are applied to the first electrode of the storage capacitor Cst and the gate electrode of the driving transistor Td of the subpixel SP through the selecting unit150during the fourth time period TP4of the sampling compensation frame SCF, and the current of the driving transistor Td is transmitted to the analog-digital converter ADC of the data driving unit130through the selecting unit150during the fifth time period TP5of the sampling compensation frame SCF.

Further, the analog-digital converter ADC of the data driving unit130converts the current of an analog type into the current of a digital type to output the current of a digital type to the timing controlling unit120. The timing controlling unit120adjusts the image data based on the current of the driving transistor Td corresponding to a deterioration degree of the first transistor T1as a sampling transistor to generate a compensated image data and outputs the compensated image data to the data driving unit130. The data driving unit130generates a compensated data voltage Vdata using the compensated image data and applies the compensated data voltage Vdata to the data line DL of the display panel160. The display panel160displays an image using the compensated data voltage Vdata.

As a result, deterioration such as deterioration of the element property of the first transistor T1of a sampling transistor is compensated, and a display quality of an image is improved. In addition, deterioration such as a stain is minimized, and a uniformity of an image is improved.

In the OLED display device110according to an embodiment of the present disclosure, the selecting unit150transmits the data voltage Vdata to the driving transistor Td to compensate deterioration of the driving transistor Td and display an image.

FIG.8is a view showing a plurality of signals of a driving compensation frame of an organic light emitting diode display device according to an embodiment of the present disclosure,FIG.9is a view showing operation of a sixth time period of an organic light emitting diode display device according to an embodiment of the present disclosure.

InFIG.8, a driving compensation frame DCF for compensating the driving transistor Td and displaying an image includes the third time period TP3where the initial voltage Vini is applied to the gate electrode of the driving transistor Td, the fourth time period TP4where the data voltage Vdata and the threshold voltage Vtht are applied to the gate electrode of the driving transistor Td and a sixth time period TP6where the light emitting diode De emits a light.

The third and fourth time periods TP3and TP4ofFIG.8are the same as the third and fourth time periods TP3and TP4ofFIG.6, the third and fourth time periods TP3and TP4will be illustrated with reference toFIGS.7A and7B.

InFIGS.8and7A, during the third time period TP3, the first and second switches SW1and SW2of the data driving unit130have an off state, and the data voltage Vdata is connected to the output channel CH.

The first and second selection signals Se1and Se2of the selecting unit150become a high level voltage, the third selection signal Se3of the selecting unit150becomes a low level voltage, the first and second mux transistors Tm1and Tm2are turned off, and the third mux transistor Tm3is turned on. The output channel CH of the data driving unit130is connected to the data line DL of the subpixel SP.

The emission1voltage Em1, the emission2voltage Em2, the gate1voltage Scan1and the gate2voltage Scan2of the subpixel SP become a high level voltage Vh, the gate3voltage Scan3of the subpixel SP becomes a low level voltage Vl, the first and fifth transistors T1and T5are turned on, and the second, third, fourth, sixth and seventh transistors T2, T3, T4, T6and T7are turned off. Further, the initial voltage Vini becomes a first voltage V1.

Accordingly, the data voltage Vdata of the data driving unit130is transmitted to the data line DL of the display panel160and the initial voltage Vini is applied to the gate electrode of the driving transistor Td and the first electrode of the storage capacitor Cst so that the gate electrode of the driving transistor Td and the first electrode of the storage capacitor Cst are initialized.

InFIGS.8and7B, during the fourth time period TP4, the first and second switches SW1and SW2of the data driving unit130have an off state, and the data voltage Vdata is connected to the output channel CH.

The first and second selection signals Se1and Se2of the selecting unit150become a high level voltage, the third selection signal Se3of the selecting unit150becomes a low level voltage, the first and second mux transistors Tm1and Tm2are turned off, and the third mux transistor Tm3is turned on. The output channel CH of the data driving unit130is connected to the data line DL of the subpixel SP.

The emission1voltage Em1, the emission2voltage Em2, the gate1voltage Scan1and the gate3voltage Scan3of the subpixel SP become a high level voltage Vh, the gate2voltage Scan2of the subpixel SP becomes a low level voltage Vl, the first, second and sixth transistors T1, T2and T6are turned on, and the third, fourth, fifth and seventh transistors T3, T4, T5and T7are turned off. Further, the initial voltage Vini becomes a second voltage V2greater than the first voltage V1.

Accordingly, a sum (Vdata+Vtht) of the data voltage Vdata and the threshold voltage Vtht of the driving transistor Td is applied to and stored in the gate electrode of the driving transistor Td and the first electrode of the storage capacitor Cst.

InFIGS.8and9, during the sixth time period TP6, the first and second switches SW1and SW2of the data driving unit130have an off state, and the data voltage Vdata is connected to the output channel CH.

The first and second selection signals Se1and Se2of the selecting unit150become a high level voltage, the third selection signal Se3of the selecting unit150becomes a low level voltage, the first and second mux transistors Tm1and Tm2are turned off, and the third mux transistor Tm3is turned on. The output channel CH of the data driving unit130is connected to the data line DL of the subpixel SP.

The emission1voltage Em1, the emission2voltage Em2and the gate1voltage Scan1of the subpixel SP become a low level voltage Vl, the gate2voltage Scan2and the gate3voltage Scan3of the subpixel SP become a high level voltage Vh, the first, second, fifth and sixth transistors T1, T2, T5and T6are turned off, and the third, fourth and seventh transistors T3, T4and T7are turned on.

Accordingly, a current flows through the driving transistor Td turned on by the sum (Vdata+Vtht) of the data voltage Vdata and the threshold voltage Vtht of the driving transistor Td from the high level voltage Vdd, and the current of the driving transistor Td of the subpixel SP is transmitted to the light emitting diode De. As a result, the light emitting diode De emits a light to display an image.

Here, since the current of the driving transistor Td is proportional to a square of a value (Vgs−Vtht=Vdata+Vtht−Vdd−Vtht=Vdata−Vdd) obtained by subtracting the threshold voltage Vtht from a gate-source voltage Vgs, a factor corresponding to the threshold voltage Vtht is removed from the current of the driving transistor Td and deterioration such as a variation of the threshold voltage Vtht of the driving transistor Td is compensated.

In the OLED display device110according to an embodiment of the present disclosure, the initial voltage Vini is applied to the first electrode of the storage capacitor Cst and the gate electrode of the driving transistor Td during the third time period TP3of the driving compensation frame DCF, the data voltage Vdata of the data driving unit130and the threshold voltage Vtht of the driving transistor Td are applied to the first electrode of the storage capacitor Cst and the gate electrode of the driving transistor Td of the subpixel SP through the selecting unit150during the fourth time period TP4of the driving compensation frame DCF, and the light emitting diode De emits a light to display an image in a state where deterioration such as a variation of the threshold voltage Vtht of the driving transistor Td is compensated during the sixth time period TP6of the driving compensation frame DCF.

As a result, deterioration such as a variation of the threshold voltage Vtht of the driving transistor Td is compensated, and a display quality of an image is improved. In addition, deterioration such as a stain is minimized, and a uniformity of an image is improved.

In the OLED display device110according to an embodiment of the present disclosure, the anode reset voltage Var is transmitted to the light emitting diode to reset the anode of the light emitting diode De.

FIG.10is a view showing a plurality of signals of an anode reset frame of an organic light emitting diode display device according to an embodiment of the present disclosure,FIG.11is a view showing operation of a seventh time period of an organic light emitting diode display device according to an embodiment of the present disclosure.

InFIG.10, an anode reset frame ARF for resetting the anode of the light emitting diode De includes a seventh time period TP7where the initial voltage Vini is applied to the drain electrode and the source electrode of the driving transistor Td and the anode reset voltage Var is applied to the anode of the light emitting diode De.

InFIGS.10and11, during the seventh time period TP7, the first and second switches SW1and SW2of the data driving unit130have an off state.

The first selection signal Se1of the selecting unit150becomes a low level voltage, the second and third selection signals Se2and Se3of the selecting unit150become a high level voltage, the first mux transistor Tm1is turned on, and the second and third mux transistors Tm2and Tm3are turned off. The anode reset voltage Var is connected to the reset line RL of the subpixel SP.

The emission1voltage Em1become a high level voltage Vh and the emission2voltage Em2, the gate1voltage Scan1, the gate2voltage Scan2and the gate3voltage Scan3of the subpixel SP become a low level voltage Vl, the first, third and fourth transistors T1, T3and T4are turned off and the second, fifth, sixth and seventh transistors T2, T5, T6and T7are turned on. Further, the initial voltage Vini becomes a second voltage V2greater than a first voltage V1.

Accordingly, the initial voltage Vini is applied to the drain electrode and the source electrode of the driving transistor Td so that the drain electrode and the source electrode of the driving transistor Td are pre-charged, and the anode reset voltage Var is applied to the anode of the light emitting diode De so that the anode of the light emitting diode De is reset.

In the OLED display device110according to an embodiment of the present disclosure, the initial voltage Vini is applied to the drain electrode and the source electrode of the driving transistor Td during the seventh time period TP7of the anode reset frame ARF, and the drain electrode and the source electrode of the driving transistor Td are pre-charged with the initial voltage Vini. In addition, the anode reset voltage Var is applied to the anode of the light emitting diode De of the subpixel SP using the selecting unit150, and the anode of the light emitting diode De is reset.

Since the driving transistor Td is pre-charged and the anode of the light emitting diode De is reset, a driving speed is improved.

Consequently, in the OLED display device110according to an embodiment of the present disclosure, since a signal is transmitted from the data driving unit130to the subpixel SP or from the subpixel SP to the data driving unit130using the selecting unit150, deterioration of the light emitting diode De and the sampling transistor T1is compensated.

In addition, since a property of the light emitting diode De and the sampling transistor T1partially driven is selectively detected and compensated using the selecting unit150, deterioration such as a stain is minimized and a uniformity of an image is improved.

In the descriptions herein, as an illustrative example, the transistors are described as being turned off by a high logic level voltage on the gate and being turned on by a low logic level voltage on the gate, which does not limit the scope of the disclosure. The techniques of the disclosure may be implemented using various type of transistors, which may be controlled by various mechanisms. For example, an NMOS transistor may be used, which is turned on by a high logic level voltage on the gate or a PMOS transistor, which has been shown, that is turned on by a low logic level and turn off by a high logic level. Further, a current-controlled transistor may also be used to implement the techniques of the disclosure, and is included in the scope of the disclosure.

It will be apparent to those skilled in the art that various modifications and variation can be made in the present disclosure without departing from the scope of the disclosure. Thus, it is intended that the present disclosure cover the modifications and variations of this disclosure.

The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.

These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.