Patent ID: 12198986

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Moreover, the formation of a feature on, connected to, and/or coupled to another feature in the present disclosure that follows may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the features, such that the features may not be in direct contact. In addition, spatially relative terms, for example, “lower,” “upper,” “horizontal,” “vertical,” “above,” “over,” “below,” “beneath,” “up,” “down,” “top,” “bottom,” etc., as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) are used for ease of the present disclosure of one features relationship to another feature. The spatially relative terms are intended to cover different orientations of the device including the features. Still further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range including the number described, such as within +/−10% of the number described or other values as understood by person skilled in the art. For example, the term “about 5 nm” encompasses the dimension range from 4.5 nm to 5.5 nm.

The present disclosure is generally related to semiconductor devices and fabrication methods thereof, and more particularly to dual channel gate all around transistor device and fabrication methods thereof.

Presented herein are embodiments of a type of multi-gate transistor referred to as a gate-all-around (GAA) device. A GAA device includes any device that has its gate structure, or portion thereof, formed on four sides of a channel region (e.g., surrounding a portion of a channel region). GAA devices may be used to realize n-type and p-type transistors, often called dual channel transistors, which have vertically stacked n-type channels and p-type channels located on two close fins. GAA dual channel transistors are useful in many integrated circuits (ICs), but some methods of fabrication suffer from various problems. For instance, some methods require separate epitaxial growth and separate patterning of stacked semiconductor layers to realize GAA dual channel transistors. However, such an approach often increases the difficulty of processes (e.g., difficult to use an etchant to remove n-type semiconductor layers and to use another etchant to remove p-type semiconductor layers in the same device) and leads to defects.

The present disclosure addresses the above problems by providing improved methods of forming dual channel GAA field effect transistors (FETs) on multiple fins. According to some embodiments, after growing a stack of alternating first semiconductor layers (e.g., silicon) and second semiconductor layers (e.g., silicon germanium), a method directly patterns the stack to create first and second fins, and then removes the second semiconductor layers to create suspended nanostructures (e.g., nanowires or nanosheets) on both fins. The method avoids various steps such as blocking and etching the first stack, growth of a second stack of n-type and p-type semiconductor layers that alternate differently from the first stack, and removing the n-type semiconductor layers (while retaining p-type layers) from the second stack. Instead, to construct a p-type FinFET on the second fin, a method converts the suspended p-type nanostructures of the second fin to p-type nanostructures by growing thin p-type semiconductor layers (e.g., silicon germanium) that wrap around the suspended p-type nanostructures and then performing an anneal process to drive germanium into the suspended p-type nanostructures. In an example, germanium atoms are driven from a silicon germanium layer into an n-type channel made of silicon. The driven-in germanium forms distinctive distribution within the channel (e.g., distributed in the middle section of the channel but not in end sections of the channel). As a result, dual channel GAA FETs can be achieved with a simplified fabrication process.

It should be understood at the outset that the channel region of a GAA device may include nanowire channels, bar-shaped channels, and/or other suitable channel configurations. In some embodiments, the channel region of a GAA device has multiple horizontal nanowires, nanosheets, and/or nanobars vertically spaced, making the GAA device a stacked horizontal GAA device. The GAA devices presented herein include p-type metal-oxide-semiconductor GAA devices or n-type metal-oxide-semiconductor GAA devices. Further, the GAA devices have one or more channels (e.g., nanowires) associated with a single, contiguous gate structure, or multiple gate structures. One of ordinary skill may recognize other examples of semiconductor devices that may benefit from aspects of the present disclosure.

FIGS.1A and1Bare top and perspective views, respectively, of a semiconductor structure100that is formed using embodiments disclosed herein. As illustrated inFIGS.1A and1B, the semiconductor structure100includes two fins102and104, and an example n-type FET110and an example p-type FET120are formed on the fins102and104, respectively. Specifically, the n-type FET110includes source/drain (S/D) regions112and114as well as a gate stack116interposed between the S/D regions112and114. Similarly, the p-type FET120includes S/D regions122and124, and a gate stack126interposed between the S/D regions122and124. One or more FETs may be formed on each fin feature. The channel region for each FET, which underlies the gate, is the portion of the corresponding fin interposed between the source and drain regions. In the present embodiment, the n-type FET110has a first channel region118in the fin102, and the p-type FET120has a second channel region128in the fin104. As shown inFIG.1A, the channel regions118and128each comprise nanowire or bar-shaped channels for current conduction, which are wrapped around by the gate stack126. For the n-type FET110, current carriers (electrons) flow through the channel region118along stacked silicon nanowire or bar-shaped channels (e.g., Si layers), which are considered n-type channels herein. For the p-type FET120, current carriers (holes) flow through the channel region128along silicon germanium nanowire or bar-shaped channels (e.g., Si1-yGeylayers), which are considered p-type channels herein. By providing the semiconductor structure100having n-type FETs and p-type FETs with respective channel material compositions, the carrier mobility for both are enhanced and device performance is improved.

FIG.2is a flowchart of a method200of forming the semiconductor device structure100, according to various aspects of the present disclosure. The method200is merely an example and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, and after the method200, and some operations described can be replaced, eliminated, or moved around for additional embodiments of the method. Some embodiments of method200are described below in conjunction withFIGS.1and3-12Band the semiconductor structure100.FIGS.8A,9A,10A, and11Aare X-cut cross-sectional views of the semiconductor structure100(taken along the line A-A′ inFIG.1A) at intermediate operations of the method200, andFIGS.3-7,8B,9B,10B, and11Bare Y-cut cross-sectional views of the semiconductor structure100(taken along the line B-B′ inFIG.1A) at intermediate operations of the method200.FIGS.15A and16Aare X-cut cross-sectional views of the semiconductor structure100(taken along the line A-A′ inFIG.1A) in some other embodiments at intermediate operations of the method200, andFIGS.13,14,15B, and16Bare Y-cut cross-sectional views of the semiconductor structure100(taken along the line B-B′ inFIG.1A) in some other embodiments at intermediate operations of the method200.

In FinFET devices, fins extend in a first direction called an X-cut direction, and metal gates extend in a second direction called a Y-cut direction. Thus, the Y-cut cross-sectional views run in parallel with a length direction of the metal gates and perpendicular to a length direction of the fins.

At operation202, the method200(FIG.2) provides a starting semiconductor structure100. In an embodiment, the semiconductor structure100includes a substrate302and a stack of alternatingly disposed semiconductor layers308and310(FIG.3). The semiconductor structure100is provided for illustration purposes and does not necessarily limit the embodiments of the present disclosure to any number of devices, any number of regions, or any configuration of structures or regions. Furthermore, the semiconductor structures as shown inFIGS.3-12Bare intermediate devices fabricated during processing of an IC, or a portion thereof, that may comprise static random access memory (SRAM) and/or logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as p-type field effect transistors (PFETs), n-type FETs (NFETs), multi-gate FETs such as FinFETs, metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, other memory cells, and combinations thereof.

Referring toFIG.3, the substrate302may be a semiconductor substrate such as a silicon substrate. In some embodiments, the substrate302includes various layers, including conductive or insulating layers formed on a semiconductor substrate. The substrate302may include various doping configurations. For example, different doping profiles (e.g., n wells, p wells) may be formed on the substrate302in regions designed for different device types (e.g., n-type field effect transistors (NFET), p-type field effect transistors (PFET)). In some embodiments, the substrate302includes other semiconductors such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate302includes a compound semiconductor and/or an alloy semiconductor. Further, the substrate302may optionally include an epitaxial layer, may be strained for performance enhancement, may include a silicon-on-insulator structure, and/or have other suitable enhancement features.

Still referring toFIG.3, the semiconductor structure100includes a stack of semiconductor layers308and310in an interleaving or alternating fashion (e.g., a semiconductor layer310disposed over a semiconductor layer308, then another semiconductor layer308disposed over the semiconductor layer310, and so on). In some embodiments, the semiconductor layers308and310are alternatingly disposed in a vertical direction, forming a semiconductor stack. In various embodiments, the stack includes any number of alternately disposed semiconductor layers308and310. In some embodiments, the semiconductor layers308and310have different thicknesses. Further, the semiconductor layers308may have different thicknesses from one layer to another layer, and the semiconductor layers310may have different thicknesses from one layer to another layer. In some embodiments, the thickness of each of the semiconductor layers308and310ranges from several nanometers to tens of nanometers. In an embodiment, each semiconductor layer308has a thickness ranging from about 5 nm to about 10 nm, and each semiconductor layer310has a thickness ranging from about 5 nm to about 10 nm. Note that, althoughFIG.2illustrates a semiconductor layer308as the bottom layer of the stack, a semiconductor layer310may be the bottom layer as well. The first layer of the stack may be thicker than other semiconductor layers308and310.

The two types of semiconductor layers308and310have different compositions. In various embodiments, the semiconductor layers308have compositions that provide for different oxidation rates and/or different etch selectivity from the semiconductor layers310. In an embodiment, the semiconductor layers308include silicon germanium (Si1-xGex), while the semiconductor layers310include silicon (Si). In an embodiment, each semiconductor layer310is silicon undoped or substantially dopant-free (i.e., having an extrinsic dopant concentration from about 0 cm−3to about 1×1017cm−3), where no intentional doping is performed when forming the semiconductor layer310(e.g., of silicon). Alternatively, each semiconductor layer310is intentionally doped. In an example, the semiconductor layer310is made of silicon doped with either a p-type dopant such as boron (B), aluminum (Al), indium (In), and gallium (Ga), or an n-type dopant such as phosphorus (P), arsenic (As), antimony (Sb). In some embodiments, each semiconductor layer308is Si1-xGexthat includes less than 50% (x<0.5) Ge in molar ratio. For example, Ge comprises about 15% to about 35% of the semiconductor layer308of Si1-xGexin molar ratio. Further, the semiconductor layers308may include different compositions among them, and the semiconductor layers310may include different compositions among them.

In various embodiments, either of the semiconductor layers308and310includes other materials such as a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide), or an alloy semiconductor (e.g., GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP), or combinations thereof. The materials of the semiconductor layers308and310may be chosen based on providing differing oxidation rates and/or etch selectivity. The semiconductor layers308and310may be doped or undoped, as discussed above.

In some embodiments, the semiconductor layers308and310are epitaxially grown layer-by-layer from a top surface of the substrate302. In an example, each of the semiconductor layers308and310are grown by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process such as a metal organic CVD (MOCVD) process, and/or other suitable epitaxial growth processes. During the epitaxial growth, the crystalline structure of the substrate302extends upwardly, resulting in the semiconductor layers308and310having the same crystal orientation with the substrate302.

At operation204, the method200(FIG.2) patterns the alternating semiconductor layers308and310to form one or more fins extending from the substrate302. Referring to the example ofFIG.4, the semiconductor structure100includes a fin102in a first region320and a fin104in a second region322. The fins102and104each include a stack of the semiconductor layers308and310. Although two fins are illustrated for illustration, any suitable number of fins may be formed. The two fins102and104are spaced by a distance annotated as spacing S. In some embodiments, the spacing S is in a range from about 40 nm to about 100 nm. In furtherance of some embodiments, the spacing S is in a range from about 15 nm to about 40 nm, for tight device integration. In an embodiment, the first region320is a region of the substrate302defined for one or more n-type FETs and the second region322is a region of the substrate302defined for one or more p-type FETs. Note that the semiconductor structure100may alternatively have a p-type FET form in the region320and an n-type FET to form in the region322.

The operation204includes a variety of processes such as photolithography and etching. In an embodiment, the operation204first forms a masking element over the semiconductor structure100through a photolithography process. The photolithography process may include forming a photoresist (or resist) over the semiconductor structure100, exposing the resist to a pattern that defines various geometrical shapes, performing post-exposure bake processes, and developing the resist to form the masking element. Subsequently, the operation204etches the semiconductor layers308and310in the regions320and322through the masking element to form trenches323therein. The etching processes may include one or more dry etching processes, wet etching processes, and other suitable etching techniques. For example, a dry etching process may implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCl3), a bromine-containing gas (e.g., HBr and/or CHBr3), an iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof. In an example, a wet etching process includes etching in diluted hydrofluoric acid (DHF); potassium hydroxide (KOH) solution; ammonia; a solution containing hydrofluoric acid (HF), nitric acid (HNO3), and/or acetic acid (CH3COOH); or other suitable wet etchants. After etching, the remaining portions of the semiconductor layers308and310become the fins102and104, defining the trenches323between and surrounding the fins102and104. The etching process may further recess into the substrate302. In some embodiments, the etching process is designed to over-etch into the substrate302to ensure that the substrate302is exposed throughout the trenches323.

In an embodiment, the fins102and104are formed simultaneously using the same pattering steps (instead of being formed sequentially one after another using separate patterning steps). For example, the same photolithography and etching processes are used to form the fins102and104, on which n-type and p-type dual channel GAA transistors may then be formed. Such a simple patterning approach provides advantages over other methods that use separate epitaxial growth and separate patterning of stacked semiconductor materials to realize dual channel use separate epitaxial growth and separate patterning of stacked semiconductor materials to realize GAA transistors.

At operation206, the method200(FIG.2) forms isolation features324between and surrounding the fins102and104. Referring toFIG.5, the isolation features324is formed of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass, a low-k dielectric material, and/or other suitable insulating material. In some embodiments, the isolation features324are shallow trench isolation (STI) features. The operation206includes a variety of processes such as deposition and etching. In some embodiments, the operation206of the method200deposits a dielectric material, such as silicon oxide, into the trenches323. The dielectric material is formed by chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), thermal oxidation, or other techniques. In some embodiments, a CMP process is performed to planarize a top surface of the semiconductor structure100. Thereafter, the dielectric material is recessed by selective etching to form the isolation features324, which isolates various portions of the substrate302and/or epitaxial stacks308/310. The selective etching may include wet etching and/or dry etching to selectively etch back the isolation features324.

The method200then proceeds to forming FETs on the fins102and104. In an example, the method200forms the n-type FET110on the fin102within the first region320and the p-type FET120on the fin104within the second region322. Forming the FETs includes various procedures and operations, which are described next.

At operation208, the method200forms dummy gate stacks over the fins102and104, respectively. In an embodiment, the dummy gate stacks will be removed in a later gate-replacement process. The dummy gate stacks engage the fins102and104at the channel regions118and128. The dummy gate stack includes one or more material layers. In the present embodiment, the dummy gate stacks include a polysilicon (or poly) layer. In an embodiment, the dummy gate stacks further include an interfacial layer (e.g., silicon oxide) underneath the poly layer. The poly layer is formed by suitable deposition processes such as low-pressure chemical vapor deposition (LPCVD) and PECVD. In an embodiment, the material layers of the dummy gate stack are first deposited as blanket layers, and then patterned with one or more photolithography and etching processes to form the dummy gate stacks.

Gate spacers (e.g., gate spacers330shown inFIG.8A) are formed on sidewalls on the dummy gate stacks after the dummy gate stacks are patterned. The gate spacer includes one or more dielectric materials such as silicon nitride, silicon oxide, silicon carbide, silicon oxycarbide (SiOC), silicon oxycarbon nitride (SiOCN), other suitable low-k dielectric materials, or combinations thereof. In some embodiments, the gate spacer is formed by depositing a spacer layer blanketing the semiconductor structure100with suitable methods, such as chemical oxidation, thermal oxidation, ALD, or CVD, then etching the spacer layer by an anisotropic etching process to remove portions of the spacer layer from a top surface of the dummy gate stacks and from top and sidewall surfaces of the fins (e.g., fins102and104). Portions of the spacer layer on the sidewall surfaces of the dummy gate stacks substantially remain and become the gate spacer. In an embodiment, the anisotropic etching process is a dry (e.g., plasma) etching process.

At operation210, the method200forms source/drain (S/D) features in the S/D regions112and114of the n-type FET110and the S/D regions122and124of the p-type FET120. In an embodiment, forming the S/D features includes epitaxially growing a semiconductor layer by an MBE process, a chemical vapor deposition process, and/or other suitable epitaxial growth processes. In a further embodiment, the S/D features are in-situ or ex-situ doped with an n-type dopant or a p-type dopant. For example, in some embodiments, the S/D features includes silicon-germanium (SiGe) doped with boron for forming S/D features for a p-type FET. In some embodiments, the S/D features include silicon doped with phosphorous for forming S/D features for an n-type FET.

At operation212, the dummy gate stacks are removed to expose channel regions, such as the channel region118of the fin102and the channel region128of the fin104. The dummy gate stacks, which include the poly layer and any other layers thereunder, are removed to form respective openings. In an embodiment, removing the dummy gate stack includes one or more etching processes, such as wet etching and/or dry etching.

At operation213, the method200forms suspended nanostructures (nanowire or nano sheet) in the exposed channel regions. The formation of suspended nanostructures includes a selective etching process to selectively remove one semiconductor layer from the respective channel region (or channel and source/drain regions) of the FETs. Referring to the example ofFIG.6, the semiconductor layers308(e.g., Si1-xGex) are removed from the channel regions of the fins102and810while the semiconductor layers310(e.g., Si) substantially remain as the channels. In other words, in the channel regions118and128, the semiconductor layers308(or portions thereof) are removed. As a result, portions of the semiconductor layers310in the channel regions118and128are suspended in the respective openings. Therefore, after operation213, the semiconductor layers310(and layers converted from the semiconductor layers310) are also called suspended nanostructures in the channel regions118and128.

In an embodiment, the semiconductor layers to be removed are etched by a selective wet etching process while the other semiconductor layers with different composition remain substantially unchanged. In some embodiments, the selective wet etching process includes a hydro fluoride (HF) or NH4OH etchant. In an embodiment where the semiconductor layers308includes SiGe and the semiconductor layers310includes Si, the selective removal of the SiGe layers308includes a SiGe oxidation process followed by a SiGeOxremoval. In an example, the SiGe oxidation process includes forming and patterning various masking layers such that the oxidation is controlled to the SiGe layers308. In other embodiments, the SiGe oxidation process is a selective oxidation due to the different compositions of the semiconductor layers308and310. In some examples, the SiGe oxidation process is performed by exposing the semiconductor structure100to a wet oxidation process, a dry oxidation process, or a combination thereof. Thereafter, the oxidized semiconductor layers308, which include SiGeOx, are removed by an etchant such as NH4OH or diluted HF. The semiconductor layer can be also removed by a selective dry etching process while other semiconductor layers with different composition remain substantially unchanged. In some embodiments, the selective dry etching process includes a hydro fluoride (HF), fluoride (F2), Carbon fluoride (CFx), hydrogen (H2)-based etchant.

In the Y-cut view ofFIG.6, the remaining semiconductor layers310are illustrated as having oval shapes (due to partial etching of the semiconductor layers310), but it is understood that the semiconductor layers310may be bar-shaped, or rectangle-shaped (nanosheet), or any other suitable shape in this view, such as an alternative embodiment illustrated inFIG.13, which will be further discussed below. In some embodiments, each remaining layer310has a thickness (denoted as T inFIG.6) of about 3 to about 8 nm, and each remaining layer310has a width (denoted as W inFIG.6) of about 5 to about 30 nm.

To realize n-type and p-type dual channels, the method200then proceeds to converting the channel region128in the fin104from a first type to a second type (e.g., from n-type to p-type, or vice versa). In an example, the method200forms a first-type (e.g., n-type) channel region118in the fin102and a second-type (e.g., p-type) channel region128in the fin104. The conversion of the channel region128includes various procedures and operations, such as operations214,216, and218, which are described next.

At operation214, the method200(FIG.2) forms a patterned mask on the top surface of the semiconductor structure100. As shown inFIG.7, the patterned mask covers the fin102in the first region320and includes an opening that exposes the fin104in the second region322of the semiconductor structure100. In one embodiment, the patterned mask includes a hard mask336(instead of a soft mask such as a patterned resist layer) disposed on the region320. In some examples, the hard mask336includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, silicon carbide oxynitride, other semiconductor material, and/or other dielectric material. In an embodiment, the hard mask336has a thickness ranging from about 1 nm to about 40 nm. The hard mask336is formed by thermal oxidation, chemical vapor deposition (CVD), atomic layer deposition (ALD), or any other appropriate method. The hard mask336is patterned using any suitable methods such as a photolithography process, which may include forming a resist layer on the hard mask336, exposing the resist by a lithography exposure process, performing a post-exposure bake process, developing the photoresist layer to form the patterned photoresist layer that exposes part of the hard mask336, patterning the hard mask336, and finally removing the patterned resist layer. The lithography process may be alternatively replaced by other suitable techniques, such as e-beam writing, ion-beam writing, maskless patterning or molecular printing.

At operation216, the method200forms a semiconductor layer312around each of the nanowire or bar-shaped layers310located in the fin104(but not those in the fin102). Since semiconductor layers312are used to convert the channel region128in the fin104from a first-type (e.g., n-type) to a second-type (e.g., p-type), the semiconductor layer312have different compositions from the semiconductor layers310. In various embodiments, the semiconductor layers312have compositions that provide for different oxidation rates and/or different etch selectivity from the semiconductor layers310. In an embodiment, the semiconductor layers312include silicon germanium (Si1-xGex), while the semiconductor layers310include silicon (Si). In some embodiments, each layer312is Si1-xGexthat includes about 10% to about 100% (0.1≤x≤1) Ge in molar ratio. A sufficient amount of Ge in each layer312helps convert the channel region128in the fin104from a first-type (e.g., n-type) to a second-type (e.g., p-type). For example, Ge may comprise about 60% to about 80% of the layer312of Si1-xGexin molar ratio. Such a range of Gexcombined with subsequent processing steps, effectively converts the channel region128from the first-type to the second-type. Further, the semiconductor layers312may include different compositions among them.

In some embodiments, the semiconductor layers312are epitaxially grown from the surfaces of the semiconductor layers310. For example, each semiconductor layer312is grown by an MBE process, a CVD process such as a MOCVD process, and/or other suitable epitaxial growth processes. The epitaxial growth approach allows materials in the semiconductor layer312to form crystalline lattices that are consistent with those of the semiconductor layers310. In some embodiments, each semiconductor layer312is a conformal layer that has a substantially uniform thickness. As shown inFIGS.8A and8B, each semiconductor layer312has a thickness of about 2 to about 5 nm. In some embodiments, a thickness ratio between a semiconductor layer310and its surrounding semiconductor layer312is about 2:1 to about 4:1. In other words, the semiconductor layer312is thinner than its corresponding semiconductor layer310. Such a thickness ratio provides the suitable amount of germanium needed to convert the semiconductor layers310from n-type to p-type.

As shown inFIG.8A, each semiconductor layer310includes a middle section310aand two end sections310b, where the middle section310ais suspended in space (and to be wrapped around by the gate stack126in subsequent steps), and the end sections310bare engaged (e.g., surrounded or wrapped around) by the gate spacers330. In an embodiment, since only middle sections310aare exposed, the semiconductor layers312are epitaxially grown only in the middle sections310a, and not in the end sections310b, of the suspended nanostructures. In other words, the semiconductor layers312are only formed at the gate contact region and stop at the gate spacers330(i.e., not extending horizontally into the gate spacers330or portions of the semiconductor layers310surrounded by the gate spacers330).

Note thatFIG.8Ashows other features that have been previously formed, including S/D regions122and124, gate spacers330, a contact etch stop layer (CESL)332, and an interlayer dielectric (ILD) layer334. The formation process of the S/D regions122and124and the gate spacers330have been described above. CESL332includes silicon nitride, silicon oxide, silicon oxynitride (SiON), and/or other suitable materials. CESL332is formed after dummy gate stacks, and CESL332is formed by one or more methods including PECVD, ALD, and/or other suitable methods. In some embodiments, ILD layer334is formed over CESL332, and includes materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), a low-k dielectric material, and/or other suitable dielectric materials. ILD layer334is formed by FCVD, PECVD, or other suitable methods. Further, to tailor characteristics of the p-type transistor on the fin104, in some embodiments, after operation216(FIGS.8A and8B), n-type dopants such as phosphorus (P), arsenic (As), antimony (Sb) may also be introduced into the semiconductor layers312and corresponding semiconductor layers310.

Referring toFIGS.1,9A, and9B, the method200at operation218removes the patterned mask (e.g., the hard mask336) from the semiconductor structure100. Any suitable removal processes including dry etching, wet etching, and/or reactive ion etching (RIE) may be used.

Referring toFIGS.1,10A, and10B, the method200at operation220performs an anneal process to drive germanium contained in the semiconductor layers312into their corresponding semiconductor layers310. The semiconductor structure100is exposed to a gas that contains nitrogen (N), phosphorus, or other suitable elements. To avoid oxidation of the semiconductor layers312(e.g., silicon germanium), in some embodiments, the gas contains no oxygen content. The conditions of the anneal process are adjusted to control the profile and characteristics of the resulting channel. In an example, the anneal process is performed at temperatures between about 700 degrees Celsius (V) to about 1200. The anneal process410may be performed for a relatively long period such as 10 seconds to 100 seconds (called “soaking”) or a relatively short period such as hundreds of milliseconds to a few seconds (e.g., 200 milliseconds to 2 seconds) (called “spiking”).

The anneal process causes germanium atoms, and possibly silicon atoms, contained in the semiconductor layers312to diffuse or migrate into the corresponding semiconductor layers310. On the other hand, silicon atoms contained in the semiconductor layers310may also diffuse or migrate into the corresponding semiconductor layers312. As a result of the migration of atoms, the semiconductor layers312decrease in germanium content, and the semiconductor layers310increase in germanium content. In an embodiment, after the anneal process, each of the semiconductor layers312is Si1-xGexthat includes more than 0% but equal to or less than about 70% (0.1<x≤0.7) Ge in molar ratio. Such a range of Ge is a result of diluting the initial concentration of Ge in the layer312(e.g. about 10% to about 80%, as described above) and effectively converts the channel region128from a first-type (e.g., n-type) to a second-type (e.g., p-type). In an embodiment, the germanium content in the semiconductor layers312changes the semiconductor layers310from n-type to p-type. Each semiconductor layers312and its corresponding semiconductor layer310may effectively combine to form a new suspended channel340, as the material compositions of the semiconductor layers310and312become the same or similar (e.g., when germanium gets uniformly distributed throughout the semiconductor layers310and312).

Since the suspended nanostructures340are formed as a combination of corresponding semiconductor layers310and312, the suspended nanostructures340in the fin104may be thicker and wider than the suspended nanostructures310in the fin102. Referring toFIGS.1,11A, and11B, the method200at operation222optionally performs a trimming operation to reduce the thickness and/or width of the layers. The trimming operation uses any suitable etching process such as dry etching, wet etching, and/or RIE. In an embodiment, the suspended nanostructures340in the fin104are trimmed to have about the same dimensions (e.g., thickness and/or width) as the suspended nanostructures310in the fin102.

According to some embodiments disclosed herein, the driven-in germanium atoms get distributed in the suspended nanostructures340in various ways, which may be tailored by controlling the conditions of the anneal process. As described above and shown inFIG.8A, when the semiconductor layers312were epitaxially grown, they attached to the middle sections310aof the suspended nanostructures. Thus, during the anneal process, germanium atoms in the semiconductor layers312may diffuse mostly into the middle sections310a(and not the end sections310b) of corresponding suspended nanostructures.FIG.12Aillustrates an example concentration profile of germanium in the X-cut direction (along the line taken inFIG.11A). As shown inFIG.12A, a concentration of germanium in the middle section of each channel340is higher than a concentration of the germanium in the two end sections of the channel340. Any suitable methods of determining concentration may be used (e.g., by determining an average concentration or median concentration). In an embodiment, the concentration of the germanium in the middle section of each channel340is substantially uniform, while the concentration of the germanium in the end sections of each channel340takes a gradient profile (e.g., gradually decreasing from the high concentration in the middle section until the concentration becomes zero). Note that, due to the spreading nature of germanium migration in the anneal process, the concentration of germanium may start to decrease at points C and C′ shown inFIG.12A, which may be a few nanometers off from the interface between the middle section and an end section. In some embodiments (for example, when the anneal process has a short duration and/or low temperatures), germanium does not reach far enough under the gate spacers330to reach the source region122and the drain region124. Instead, the concentration of germanium drops to zero at the points D and D′ shown inFIG.12A. Thus, at least a portion of the two end sections—which is in direct contact with the gate spacers330, the source region122, and the drain region124—is substantially devoid of germanium. In an embodiment, the entire end sections of the channel340are substantially devoid of germanium.

FIG.12Billustrates an example simulated concentration profile of germanium in the Y-cut direction (along the line taken inFIG.11B). As shown inFIG.12B, a concentration of germanium in a core portion of each channel340may be equal to or lower than a concentration of germanium in an edge portion of the channel340. Different concentration profiles may be realized by controlling various parameters such as the thickness of a semiconductor layer312, the concentration of germanium in the semiconductor layer312, and/or conditions of its anneal process. For example, a thicker semiconductor layer312supplies more germanium atoms, and a longer anneal process (or performed at higher temperatures) drives germanium further into a core of the channel340, thereby leading to a more uniform concentration of germanium.FIG.12Billustrates an example of how to control the concentration profile of the semiconductor layer312.

InFIG.12B, profiles1210-1260represent six different sets of parameters that illustrate how each specific set of parameters leads to a distinctive concentration profile of germanium in a semiconductor layer312. Specifically, profile1210represents the case where the layer312is about 4.5 to about 5.5 nm thick, contains about 50% to about 60% of germanium, and is annealed at a spiking temperature of about 1200 to about 1300 Celsius. A uniform germanium concentration of about 34% to 38% is achieved in both the core portion and the edge portion of the channel340. In profile1220, the layer312is about 2.5 nm to about 3.5 thick, contains about the same concentration of germanium as in profile1210, and is annealed at a spiking temperature of about 1030 to about 1070 Celsius. A germanium concentration of 26% to about 30% is achieved in the edge portion of the channel340, and a slightly lower germanium concentration (about 1% lower) is achieved in the core portion of the channel340. In profile1230, the layer312is about 1.3 to about 1.7 nm thick, contains about the same concentration of germanium as in profile1210/1220, and is annealed at a temperature of about 1030 to about 1070 Celsius for about 4 to about 6 seconds. A germanium concentration of about 18% to about 22% is achieved in the edge and core portions of the channel340. In profile1240, the layer312is about 1.3 to about 1.7 nm thick, contains about the same concentration of germanium as in profile1210/1220/1230, and is annealed at about the same temperature as in profile1220. The germanium concentration follows a gradient profile that decreases from a maximal concentration of about 18% to about 22% at the edge of the channel340to a minimal concentration of about 11% to about 13% at the core of the channel340. In some embodiments, such a gradient profile is caused by the relatively short duration of the anneal process (e.g., insufficient time for germanium to migrate all the way to the core). In profile1250, the layer312of about 1.3 to about 1.7 nm thick and containing about 23% to about 23% of germanium is annealed at a spiking temperature of about 1150 to about 1250 Celsius. A germanium concentration of about 9% to about 11% is achieved in the edge and core portions of the channel340. Lastly, profile1260represents a reference case where a p-type channel made of SiGe contains about 26% to 30% of germanium in its edge and core portions. As illustrated inFIG.12B, different distribution profiles of germanium are achieved by controlling one or more parameters including the thickness of a semiconductor layer312, the concentration of germanium in the semiconductor layer312, and/or conditions of its anneal process. Each specific set of parameters leads to a distinctive concentration profile of germanium in the layer312.

In an embodiment, at operation224(FIG.2), the method200continues to form the gate stacks116and126over the channel regions118and128of the fins102and104, respectively. Referring to the example ofFIG.1A, the gate stacks116and126fill the openings in the channel regions and wrap around each of the exposed semiconductor layers (e.g., nanowires), such as the semiconductor layers310in the channel region118and the semiconductor layers312in the channel regions128. The gate stacks116and126have similar structures but in some embodiments use different metals and/or different thicknesses of layers. In the present embodiment, the gate stacks include a dielectric layer which may include one or multiple layers of dielectric materials on interior surfaces of the opening and directly wrapping over each of the channel semiconductor layers. The dielectric layer includes a dielectric material such as silicon oxide or silicon oxynitride, and is formed by chemical oxidation, thermal oxidation, ALD, CVD, and/or other suitable methods. In some embodiments, the dielectric layer also includes a high-k dielectric layer such as hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, yttrium oxide, strontium titanate, other suitable metal-oxides, or combinations thereof; and is formed by ALD and/or other suitable methods. The gate stacks further include a gate metal stack which may include one or multiple layers over the dielectric layer(s), and a metal fill layer over the gate metal stack. In some embodiments, the gate metal stack includes a work function metal layer, which is a p-type work function metal layer or an n-type work function metal layer. The p-type work function metal layer comprises a metal selected from, but not limited to, the group of titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or combinations thereof. The n-type work function metal layer comprises a metal selected from, but not limited to, the group of titanium, aluminum, tantalum carbide, tantalum carbide nitride, tantalum silicon nitride, or combinations thereof. In some embodiments, the p-type or n-type work function metal layer includes a plurality of layers deposited by CVD, PVD, and/or other suitable process. The metal fill layer includes aluminum, tungsten, cobalt, copper, and/or other suitable materials, and is formed by CVD, PVD, plating, and/or other suitable processes. In some embodiments, the gate stacks wrap around the vertically-stacked horizontally-oriented channel semiconductor layers. Hence, the semiconductor structure100is a stacked horizontal gate-all-around (S-HGAA) device. In an embodiment, after the gate stacks are deposited, a CMP process is performed to planarize a top surface of the semiconductor structure100.

In various embodiments, the method100may optionally skip operation222without reducing thickness and/or width of the suspended nanostructures for p-type channels. Accordingly, a cross-sectional area of the suspended nanostructures in the fin104may be larger than that in the fin102. Since p-type channel relies on holes for conduction, which has slower mobility than electrons in n-type channel, a larger cross-sectional area in p-type channel helps increasing channel effective width and thus higher current and better transistor performance.

Referring back to operation213of the method200(FIG.2), yet another embodiment of the semiconductor structure100after the formation of suspended nanostructures is illustrated inFIG.13. In the Y-cut view ofFIG.13, the remaining semiconductor layers310are illustrated as having rectangle-shaped (may have rounded corners due to partial etching of the semiconductor layers310, which are not shown), but it is understood that the semiconductor layers310may have oval shapes as already discussed above in association withFIG.6, or any other suitable shape in this view. In some embodiments, each remaining layer310in either the fin102or104has substantially the same dimensions, such as a thickness (denoted as T inFIG.13) of about 3 to about 8 nm and a width (denoted as W inFIG.13) of about 5 to about 30 nm, and accordingly substantially the same cross-sectional area.

At operation214, the method200(FIG.2) forms a patterned mask on the top surface of the semiconductor structure100. As shown inFIG.14, the patterned mask covers the fin102in the first region320and includes an opening that exposes the fin104in the second region322of the semiconductor structure100. In one embodiment, the patterned mask includes a hard mask336(instead of a soft mask such as a patterned resist layer) disposed on the region320. In an embodiment, the hard mask336has a thickness ranging from about 1 nm to about 40 nm. The hard mask336is patterned using any suitable methods such as a photolithography process. The lithography process may be alternatively replaced by other suitable techniques, such as e-beam writing, ion-beam writing, maskless patterning or molecular printing.

At operation216, the method200forms a semiconductor layer312around each of the semiconductor layers310located in the fin104(but not those in the fin102). The semiconductor layer312also covers a top surface of the substrate302directly under the bottommost semiconductor layer310in the fin104. Since semiconductor layers312are used to convert the channel region128in the fin104from a first-type (e.g., n-type) to a second-type (e.g., p-type), the semiconductor layer312have different compositions from the semiconductor layers310. In various embodiments, the semiconductor layers312have compositions that provide for different oxidation rates and/or different etch selectivity from the semiconductor layers310. In an embodiment, the semiconductor layers312include silicon germanium (Si1-xGex), while the semiconductor layers310include silicon (Si). In some embodiments, each layer312is Si1-xGexthat includes about 10% to about 100% (0.1≤x≤1) Ge in molar ratio. In a particular example, each layer312is Si1-xGexthat includes no less than 25% Ge (0.25≤x≤1) in molar ratio. A sufficient amount of Ge in each layer312helps convert the channel region128in the fin104from a first-type (e.g., n-type) to a second-type (e.g., p-type).

In some embodiments, the semiconductor layers312are epitaxially grown from the surfaces of the semiconductor layers310. For example, each semiconductor layer312is grown by an MBE process, a CVD process such as a MOCVD process, and/or other suitable epitaxial growth processes. The epitaxial growth approach allows materials in the semiconductor layer312to form crystalline lattices that are consistent with those of the semiconductor layers310. In some embodiments, the semiconductor layer312has a first thickness (denoted as L1inFIG.15B) on vertical sidewalls of the respective semiconductor layer310and a second thickness (denoted as L2inFIG.15B) on horizontal (i.e., top and bottom) surfaces of the respective semiconductor layer310. The overall size of each suspended nanostructure in the fin104has a thickness T′≈T+2*L2and a width W′≈W+2*L1. In other words, a cross-sectional area of the suspended nanostructure in the fin104becomes larger than that in the fin102. In some embodiments, a cross-sectional area ratio between the suspended nanostructure in the fin104and that in the fin102is from about 1:1 to about 3:1.

In some embodiments, the first thickness L1and the second thickness L2of the semiconductor layer312may have different values. For example, the horizontal surfaces and vertical sidewalls may have different orientations that results in different epitaxial growth rate. In one example, the semiconductor layer310has a (110) surface in the horizontal surfaces and a (100) surface in the vertical sidewalls. The method200at operation216may be tuned to excite a higher epitaxial growth rate at the (100) surface than the (110) surface, such that L1is larger than L2. A ratio between L1and L2may range from about 1:1 to about 2:1, such as 1.5:1. A relatively larger L1and a relatively smaller L2help to keep the cross-sectional area enlargement with the deposition of the semiconductor layer312mainly in the horizontal directions, while maintain a suitable vertical distance between adjacent suspended nanostructures. In yet another example, the semiconductor layer310has a (100) surface in the horizontal surfaces and a (110) surface in the vertical sidewalls. The method200at operation216may include a cyclic process that alternates an epitaxial growth and a selective etching process to achieve an effective higher epitaxial growth rate at the (110) surface than the (100) surface, such that L1is larger than L2. The cyclic process may first epitaxial grow the (100) and (110) surfaces at the same time with a faster epitaxial growth rate at the (100) surface, such as an epitaxial growth ratio between (100) and (110) surfaces ranging from about 1:1 to about 5:1. The cyclic process then apply a selective etching process that is tuned to target at the (100) surface such that the epitaxial growth at (100) surface is thinned down to be smaller than the (110) surface, such as with an etching selectivity between (100) and (110) surfaces ranging from about 6:1 to about 2:1. The selective etching process keeps the effective epitaxial growth on the (110) surface larger than on the (100) surface. The cyclic process may repeat the epitaxial growth and selective etching process for about 2 to 10 times. After the cyclic process, a ratio between L1and L2may range from about 1:1 to about 2:1, such as 1.5:1.

In some embodiments, each semiconductor layer312is a conformal layer that has a substantially uniform thickness (L1=L2). As shown inFIGS.15A and15B, each semiconductor layer312may have a thickness of about 1.5 nm to about 5 nm, such as 2 nm. In some embodiments, a thickness ratio between a semiconductor layer310and its surrounding semiconductor layer312is about 2:1 to about 4:1. In other words, the semiconductor layer312is thinner than its corresponding semiconductor layer310. Such a thickness ratio provides the suitable amount of germanium needed to convert the semiconductor layers310from n-type to p-type.

As shown inFIG.15A, each semiconductor layer310includes a middle section310aand two end sections310b, where the middle section310ais suspended in space (and to be wrapped around by the gate stack126in subsequent steps), and the end sections310bare engaged (e.g., surrounded or wrapped around) by the gate spacers330. In an embodiment, since only middle sections310aare exposed, the semiconductor layers312are epitaxially grown only in the middle sections310a, and not in the end sections310b, of the suspended nanostructures. In other words, the semiconductor layers312are only formed at the gate contact region and stop at the gate spacers330(i.e., not extending horizontally into the gate spacers330or portions of the semiconductor layers310surrounded by the gate spacers330). A cross section of the end sections310bremains in a rectangular shape with a width W and a thickness T, which is substantially the same as the dimensions of the semiconductor layer310in the fin102.

Subsequently, the method200at operation218removes the patterned mask (e.g., the hard mask336) from the semiconductor structure100. Any suitable removal processes including dry etching, wet etching, and/or reactive ion etching (RIE) may be used.

Referring toFIGS.16A and16B, the method200at operation220performs an anneal process to drive germanium contained in the semiconductor layers312into their corresponding semiconductor layers310. The germanium contained in the semiconductor layer312that covers a top surface of the substrate302directly under the bottommost semiconductor layer310in the fin104is also driven into the substrate302. The semiconductor structure100is exposed to a gas that contains nitrogen (N), phosphorus, or other suitable elements. To avoid oxidation of the semiconductor layers312(e.g., silicon germanium), in some embodiments, the gas contains no oxygen content. The conditions of the anneal process are adjusted to control the profile and characteristics of the resulting channel. In an example, the anneal process is performed at temperatures between about 700 degrees Celsius (° C.) to about 1200. The anneal process410may be performed for a relatively long period such as 10 seconds to 100 seconds (called “soaking”) or a relatively short period such as hundreds of milliseconds to a few seconds (e.g., 200 milliseconds to 2 seconds) (called “spiking”).

The anneal process causes germanium atoms, and possibly silicon atoms, contained in the semiconductor layers312to diffuse or migrate into the corresponding semiconductor layers310. On the other hand, silicon atoms contained in the semiconductor layers310may also diffuse or migrate into the corresponding semiconductor layers312. As a result of the migration of atoms, the semiconductor layers312decrease in germanium content, and the semiconductor layers310increase in germanium content. In an embodiment, the germanium content in the semiconductor layers312changes the semiconductor layers310from n-type to p-type. Each semiconductor layers312and its corresponding semiconductor layer310may effectively combine to form a new suspended nanostructure340, as the material compositions of the semiconductor layers310and312become the same or similar (e.g., when germanium gets uniformly distributed throughout the semiconductor layers310and312). In an embodiment, after the anneal process, each of the suspended nanostructure340is Si1-xGexthat includes more than 10% but equal to or less than about 70% (0.1<x≤0.7) Ge in molar ratio, such as from about 10% to about 50% in a particular example. Such a range of Ge is a result of diluting the initial concentration of Ge in the layer312and effectively converts the channel region128from a first-type (e.g., n-type) to a second-type (e.g., p-type).

Since the suspended nanostructures340are formed as a combination of corresponding semiconductor layers310and312, the suspended nanostructures340in the fin104becomes thicker and wider than the suspended nanostructures310in the fin102. The inventors of the present disclosure have observed that under certain anneal process conditions, driving germanium atoms, and possibly silicon atoms, contained in the semiconductor layers312into the corresponding semiconductor layers310will also cause surface reconstruction of the resulted suspended nanostructure340. In some embodiments, the anneal temperature is set slightly below the melting point of germanium but far below the melting point of silicon, such as at a spiking temperature of about 1200 to about 1300 Celsius to facilitate the surface reconstruction. In the illustrated embodiments inFIG.16B, a cross section of the suspended nanostructure340in the channel region transforms from a rectangular shape to an oval shape (including a circular shape). The geometry of end sections310band semiconductor layers310in the fin102remains unchanged. As silicon and/or germanium atoms at the crystal surface lack neighbors, surface reconstruction may occur by absorption of foreign atoms (e.g., germanium atoms). The surface reconstruction may be due to the reduction of surface energy such that solid surfaces are intrinsically less energetically favorable than the bulk of a material (otherwise there would be a driving force for surfaces to be created, removing the bulk of the material). As a result, silicon atoms at the crystal surface have a tendency to move away from unfavorable high energy positions and to bond with more neighbors in order to reduce surface energy level. The matter flow thus changes the geometry of surface layers and reconstructs the original surface to have a curvature shape. A region350containing one suspended nanostructure340is depicted to further illustrate the surface reconstruction. The oval solid line represents the cross section of the suspended nanostructure340after the surface reconstruction. The two dotted rectangular boxes represent the suspended nanostructure before and after the deposition of the semiconductor layer312, prior to the surface reconstruction, respectively. The surface reconstruction causes the four corners of the suspended nanostructure340to retreat, centers of the upper and lower surfaces to protrude, and centers of the vertical sidewalls to expand. As a result, the oval shape has an enlarged thickness T″ (T″>T′, e.g., about 5% larger) and an enlarged width W″ (W″>W′, e.g., about 5% larger). Even though the oval shape has enlarged thickness T″ and enlarged width W″, the cross-sectional area substantially remains the same, due to the retreat of the four corner areas. In some embodiments, after the surface reconstruction, a cross-sectional area ratio between the suspended nanostructure in the fin104and that in the fin102is from about 1.4:1 to about 2:1. If the ratio is less than 1.4:1, the low carrier mobility of holes in p-type channel may not be sufficiently compensated by larger effective width. If the ratio is larger than 2:1, the distance between adjacent suspended nanostructures may become small and cause filling issues during the metal gate stack formation later on. Comparing with the suspended nanostructures in the fin102, in some embodiments, a ratio of T″/T is no less than 1.2:1, such as from about 1.2:1 to about 2:1; a ratio of W″/W is no less than 1.2:1, such as from about 1.2:1 to about 2:1.

During the anneal process, germanium atoms in the semiconductor layers312may diffuse mostly into the middle sections310a(and not the end sections310b) of corresponding the suspended nanostructures.FIG.17illustrates an example concentration profile of germanium in the X-cut direction (along the line taken inFIG.16A). As shown inFIG.17, a concentration of germanium in the middle section of each channel340is higher than a concentration of the germanium in the two end sections of the channel340. Any suitable methods of determining concentration may be used (e.g., by determining an average concentration or median concentration). In an embodiment, the concentration of the germanium in the middle section of each channel340is substantially uniform, while the concentration of the germanium in the end sections of each channel340takes a gradient profile (e.g., gradually decreasing from the high concentration in the middle section until the concentration becomes zero). Note that, due to the spreading nature of germanium migration in the anneal process, the concentration of germanium may start to decrease at points C and C′ shown inFIG.17, which may be a few nanometers (e.g., about 1 nm to about 2 nm) off from the interface between the middle section and an end section. In some embodiments (for example, when the anneal process has a short duration and/or low temperatures), germanium does not reach far enough under the gate spacers330to reach the source region122and the drain region124. Instead, the concentration of germanium drops to zero at the points D and D′ shown inFIG.17. Thus, at least a portion of the two end sections—which is in direct contact with the gate spacers330, the source region122, and the drain region124—is substantially devoid of germanium. In an embodiment, the entire end sections of the channel340are substantially devoid of germanium. The various concentration profiles of germanium in the Y-cut direction (along the line taken inFIG.16B) has been discussed above in association withFIG.12Band would be skipped herein for the sake of simplicity.

The method200subsequently may skip operation222without trimming thickness and/or width of the suspended nanostructures in the fin104. With a relatively larger cross-sectional area in p-type transistor channels than in n-type transistor channels, the p-type transistor has a larger effective width, which compensates the relatively slow hole mobility in p-type channels and increase p-type transistor performance. In an embodiment, the method200continues to operation224in forming the gate stacks116and126, as illustrated inFIG.1A.

FIG.18is a flowchart of a method300of forming the semiconductor device structure100with high germanium concentration in p-type channels, according to various aspects of the present disclosure. The method300is merely an example and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, and after the method300, and some operations described can be replaced, eliminated, or moved around for additional embodiments of the method. Some embodiments of method300are described below in conjunction withFIGS.19A-19Cwhich are Y-cut cross-sectional views of the semiconductor structure100(taken along the line B-B′ inFIG.1A). Some aspects of the method300are the same as the method200, and will be briefly discussed below. Other aspects of the method300are different from the method200, and will be described in more details.

The method300includes operations202-224which are the same as those as discussed above with reference to method200inFIG.2. One of the differences between methods300and200is that the method300reiterate operations216,220, and222to achieve a high germanium concentration which is otherwise hard to achieve by depositing and anneals germanium containing layer312for only once. In some embodiments, after operations216and220, the method300forms suspended nanostructure340with a first germanium concentration in molar ratio, as shown inFIG.19A. In various embodiments, the first germanium concentration is more than 10% but equal to or less than about 70% (0.1<x≤0.7), such as from about 10% to about 50% in a particular example. To achieve an even higher germanium concentration, the method300proceeds to operation222to reduce the thickness and width of the suspended nanostructure340in order to spare space for a deposition of germanium containing layer312for another round, as shown inFIG.19B. The trimming operation uses any suitable etching process such as dry etching, wet etching, and/or RIE. In an embodiment, the suspended nanostructures340in the fin104are trimmed to have about the same thickness and/or width as the suspended nanostructures310in the fin102. Subsequently, the method300repeats operation216to deposit a germanium containing layer312wrapping around the trimmed suspended nanostructures340, as shown inFIG.19C. The germanium containing layer312includes a germanium concentration sufficiently higher than a predetermined germanium concentration value to achieve in the suspended nanostructures340. In some embodiments, a predetermined target value is about 80% germanium in molar ratio and the germanium containing layer312may include a germanium concentration larger than 80%, such as about 90%. The method300then repeats operation222to drive germanium into the suspended nanostructures340and operation222to trim the suspended nanostructures340to spare space for deposition of next round. Each iteration increases the germanium concentration in the suspended nanostructures340towards the predetermined target concentration. Once the predetermined target concentration is achieved, the method300may either perform one last round of operation222to trim the suspended nanostructures340or optionally skip operation222to keep a relatively larger cross-sectional area in p-channels.

In either method200or method300, further processes may be performed to complete the fabrication of the semiconductor structure100. For example, the method may continue to form contact openings, contact metal, as well as various contacts, vias, wires, and multilayer interconnect features (e.g., metal layers and interlayer dielectrics) over the substrate302, configured to connect the various features to form a functional circuit that may include one or more multi-gate devices.

Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to a semiconductor device and a formation process thereof. For example, embodiments of the present disclosure form dual channel GAA FET devices on multiple fins. According to some embodiments, after growing a stack of alternating n-type and p-type semiconductor layers, a method directly patterns the stack to create first and second fins, and then removes the p-type semiconductor layers to create suspended p-type nanostructures on both fins. The method then converts the suspended p-type nanostructures of the second fin to p-type nanostructures by growing thin p-type semiconductor (e.g., germanium or silicon germanium) layers that wrap around the suspended p-type nanostructures and then performing an anneal process to drive germanium atoms into the suspended p-type nanostructures. As a result, dual channel GAA FETs are achieved with a simplified fabrication process. In some embodiments, the channels only have germanium at a gate contact region (not end sections under gate spacers). Further, embodiments of the present disclosure may be integrated into existing CMOS fabrication flow, providing for improved process window.

In one example aspect, the present disclosure provides a method of forming a semiconductor device. The method includes providing a substrate having a plurality of first semiconductor layers and a plurality of second semiconductor layers disposed over the substrate, wherein the first and second semiconductor layers have different material compositions and are alternatingly disposed with respect to each other in a vertical direction, wherein each of the first and second semiconductor layers extends over first and second regions of the substrate; patterning the first semiconductor layers and the second semiconductor layers to form a first fin in the first region and a second fin in the second region; removing the first semiconductor layers from the first and second fins such that a first portion of the patterned second semiconductor layers becomes first suspended nanostructures in the first fin and that a second portion of the patterned second semiconductor layers becomes second suspended nanostructures in the second fin; forming a plurality of third semiconductor layers on the second suspended nanostructures in the second fin; and performing an anneal process to drive materials contained in the third semiconductor layers into corresponding second suspended nanostructures in the second fin.

In another example aspect, the present disclosure provides a method that includes forming a plurality of first suspended layers in a first fin and a plurality of second suspended layers in a second fin, wherein the first and second suspended layers include a same first semiconductor material; epitaxially growing a plurality of third layers on the second suspended layers in the second fin, wherein the third layers include a second semiconductor material that differs from the first semiconductor material; and driving the second semiconductor material to migrate from the third layers into corresponding second layers in the second fin.

In yet another example aspect, the present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate; a fin disposed on the substrate, the fin comprising a source region, a drain region, and a channel region disposed between the source and drain regions, the channel region comprising a plurality of channels vertically stacked over one another, the channels comprising germanium distributed therein; a gate stack engaging the channel region of the fin; and gate spacers disposed between the gate stack and the source and drain regions of the fin. Each of the channels includes a middle section wrapped around by the gate stack and two end sections engaged by the gate spacers. A concentration of germanium in the middle section of each channel is higher than a concentration of germanium in the two end sections of the channel.

The foregoing outlines features of several embodiments so that those of ordinary skill in the art may better understand the aspects of the present disclosure. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.