Patent ID: 12191335

DETAILED DESCRIPTION

Hereinafter, example embodiments of the disclosure will be described in more detail with reference to the accompanying drawings.

FIG.1is a schematic block diagram illustrating an image sensor according to some example embodiments of the disclosure.

Referring toFIG.1, an image sensor may include an active pixel sensor array1001, a row decoder1002, a row driver1003, a column decoder1004, a timing generator1005, a correlated double sampler (CDS)1006, an analog-to-digital converter (ADC)1007, and an input/output (I/O) buffer1008.

The active pixel sensor array1001may include a plurality of unit pixels two-dimensionally arranged and may convert optical signals into electrical signals. The active pixel sensor array1001may be driven by a plurality of driving signals (e.g., a pixel selection signal, a reset signal, and a charge transfer signal) provided from the row driver1003. In addition, the converted electrical signals may be provided to the correlated double sampler1006.

The row driver1003may provide a plurality of driving signals for driving a plurality of the unit pixels to the active pixel sensor array1001based on signals decoded in the row decoder1002. When the unit pixels are arranged in a matrix form, the driving signals may be provided in the unit of row of the matrix.

The timing generator1005may provide timing signals and control signals to the row decoder1002and the column decoder1004.

The correlated double sampler1006may receive electrical signals generated from the active pixel sensor array1001and may hold and sample the received electrical signals. The correlated double sampler1006may doubly sample a specific noise level and a signal level of the electrical signal to output a difference level corresponding to a difference between the noise level and the signal level.

The analog-to-digital converter1007may convert an analog signal, which corresponds to the difference level outputted from the correlated double sampler1006, into a digital signal and may output the digital signal.

The I/O buffer1008may latch the digital signals and may sequentially output the latched digital signals to an image signal processing unit (not shown) based on signals decoded in the column decoder1004.

FIG.2is a circuit diagram illustrating an active pixel sensor array of an image sensor according to some example embodiments of the disclosure.

Referring toFIGS.1and2, the active pixel sensor array1001may include a plurality of unit pixel regions PX, and the plurality of unit pixel regions PX may be arranged in a matrix form. Each of the unit pixel regions PX may include a transfer transistor TX and logic transistors RX, SX and DX. The logic transistors may include a reset transistor RX, a selection transistor SX, and a source follower transistor DX. The transfer transistor TX may include a transfer gate TG. Each of the unit pixel regions PX may further include a photoelectric conversion element PD and a floating diffusion region FD.

The photoelectric conversion element PD may generate photocharges (or charges) in proportion to the amount of light incident from the outside and may accumulate the generated photocharges. The photoelectric conversion element PD may include a photodiode, a photo transistor, a photo gate, a pinned photodiode, or a combination thereof. The transfer transistor TX may transfer charges generated in the photoelectric conversion element PD to the floating diffusion region FD. The floating diffusion region FD may receive the charges generated in the photoelectric conversion element PD and may cumulatively store the received charges. The source follower transistor DX may be controlled according to the amount of the photocharges accumulated in the floating diffusion region FD.

The reset transistor RX may periodically reset the charges accumulated in the floating diffusion region FD. A drain electrode of the reset transistor RX may be connected to the floating diffusion region FD, and a source electrode of the reset transistor RX may be connected to a power voltage VDD. When the reset transistor RX is turned on, the power voltage VDD connected to the source electrode of the reset transistor RX may be applied to the floating diffusion region FD. Thus, when the reset transistor RX is turned on, the charges accumulated in the floating diffusion region FD may be discharged to reset the floating diffusion region FD.

The source follower transistor DX may function as a source follower buffer amplifier. The source follower transistor DX may amplify a potential change in the floating diffusion region FD and may output the amplified potential change to an output line VOUT.

The selection transistor SX may select the unit pixel regions PX to be sensed in the unit of row. When the selection transistor SX is turned on, the power voltage VDD may be applied to a drain electrode of the source follower transistor DX.

FIG.3is a plan view illustrating an image sensor according to some example embodiments of the disclosure.FIG.4is a cross-sectional view taken along a line A-A′ ofFIG.3according to some embodiments of the disclosure.FIGS.5A to5Dare enlarged views of a portion ‘P1’ ofFIG.4according to some example embodiments of the disclosure.

Referring toFIGS.3and4, an image sensor500according to some embodiments of the disclosure may include a first substrate1. For example, the first substrate1may be a single-crystalline silicon wafer, a silicon epitaxial layer, or a silicon-on-insulator (SOI) substrate. For example, the first substrate1may be doped with dopants of a first conductivity type. For example, the first conductivity type may be a P-type. The first substrate1may include a first surface1aand a second surface1bwhich are opposite to each other. The first substrate1may include a pixel array region APS and an edge region EG. The pixel array region APS may include a plurality of unit pixels UP. The edge region EG may correspond to a portion of a connection region CNR ofFIGS.15and17, which will be described later.

A pixel isolation portion DTI may be disposed in the first substrate1to isolate and/or define the unit pixels UP in the pixel array region APS. The pixel isolation portion DTI may extend into the edge region EG. The pixel isolation portion DTI may have a mesh shape when viewed in a plan view.

A photoelectric conversion portion PD may be disposed in the first substrate1of each of the unit pixels UP. The photoelectric conversion portions PD may be doped with dopants of a second conductivity type opposite to the first conductivity type. The second conductivity type may be, for example, an N-type. The N-type dopants included in the photoelectric conversion portion PD may form a PN junction with the P-type dopants included in the first substrate1around the photoelectric conversion portion PD, and thus a photodiode may be provided.

A shallow device isolation portion STI adjacent to the first surface1amay be disposed in the first substrate1. The pixel isolation portion DTI may penetrate the shallow device isolation portion STI. The shallow device isolation portion STI may define active regions ACT adjacent to the first surface1ain each of the unit pixels UP. The active regions ACT may be provided for the transistors TX, RX, DX and SX ofFIG.2.

A transfer gate TG may be disposed on the first surface1a of the first substrate1of each of the unit pixels UP. A portion of the transfer gate TG may extend into the first substrate1. The transfer gate TG may be a vertical type gate. Alternatively, the transfer gate TG may not extend into the first substrate1but may be a planar type gate having a flat shape. A gate insulating layer Gox may be disposed between the transfer gate TG and the first substrate1. A floating diffusion region FD may be disposed in the first substrate1at a side of the transfer gate TG. For example, the floating diffusion region FD may be doped with dopants of the second conductivity type.

The image sensor500may be a backside illuminated image sensor. Light may be incident into the first substrate1through the second surface1bof the first substrate1. Electron-hole pairs (EHPs) may be generated in a depletion region of the PN junction by the incident light. The generated electrons may move into the photoelectric conversion portion PD. When a voltage is applied to the transfer gate TG, the electrons may be moved into the floating diffusion region FD.

In one unit pixel UP, a reset gate RG may be disposed on the first surface1aand may be adjacent to the transfer gate TG. In another unit pixel UP, a source follower gate SF and a selection gate SEL may be disposed on the first surface1aand may be adjacent to the transfer gate TG. The gates TG, RG, SF and SEL may correspond to gates of the transistors TX, RX, DX and SX ofFIG.2, respectively. The gates TG, RG, SF and SEL may overlap the active regions ACT.

The first surface1amay be covered with first interlayer insulating layers IL. Each of the first interlayer insulating layers IL may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a porous low-k dielectric layer. First interconnection lines15may be disposed between or in the first interlayer insulating layers IL. The floating diffusion regions FD may be connected to the first interconnection lines15through first contact plugs17. The first contact plugs17may penetrate a first interlayer insulating layer IL, closest to the first surface1a, of the first interlayer insulating layers IL in the pixel array region APS.

Referring toFIGS.4and5A, the pixel isolation portion DTI may be disposed in a deep trench10which is formed to extend from the first surface1ato the second surface1bin the first substrate1. A width of the deep trench10may progressively decrease from the first surface1atoward the second surface1b. The pixel isolation portion DTI may include a first filling insulation pattern16, a conductive structure20, an insulating liner12, a second filling insulation pattern22, and an air gap region AG. The first filling insulation pattern16may extend from the first surface1ato the second surface1band may have the air gap region AG therein. The first filling insulation pattern16may include a first sidewall16S1and a second sidewall16S2which are opposite to each other. Although not shown in the drawings, the first filling insulation pattern16and the air gap region AG may have mesh shapes overlapping the pixel isolation portion DTI when viewed in a plan view.

The conductive structure20may include a first conductive pattern14aon the first sidewall16S1, a second conductive pattern14bon the second sidewall16S2, and a connection conductive pattern18connecting the first conductive pattern14aand the second conductive pattern14b. In some embodiments, the connection conductive pattern18may be in contact with a bottom surface of the first filling insulation pattern16.

The first conductive pattern14amay be referred to as a first conductive portion14a, the second conductive pattern14bmay be referred to as a second conductive portion14b, and the connection conductive pattern18may be referred to as a connection conductive portion18. The first and second conductive patterns14aand14bmay be spaced apart from each other. Each of the first and second conductive patterns14aand14bmay have a ring shape surrounding a unit pixel UP adjacent thereto when viewed in a plan view. For example, in the plan view ofFIG.3, the first conductive pattern14amay surround a first unit pixel UP(1), and the second conductive pattern14bmay surround a second unit pixel UP(2). The connection conductive pattern18may have a mesh shape in the plan view ofFIG.3.

The first conductive pattern14aand the second conductive pattern14bmay include the same material. The first conductive pattern14aand the second conductive pattern14bmay be formed at the same time and may include poly-silicon doped with the same dopants at the same concentration. For example, the dopants may be boron, phosphorus, or arsenic. In particular, the dopants may be boron. The connection conductive pattern18may include the same material as or a different material from that of the first and second conductive patterns14aand14b. For example, the connection conductive pattern18may include poly-silicon doped with dopants, or a metal. When the connection conductive pattern18includes poly-silicon doped with the dopants of which a kind is different from or the same as that of the first and second conductive patterns14aand14b, a dopant concentration of the connection conductive pattern18may be different from that of the first and second conductive patterns14aand14b. For example, each of the first and second conductive patterns14aand14bmay have a thickness of 100 Å to 300 Å. If the thickness is less than 100 Å, the first and second conductive patterns14aand14bmay be insufficient to function as a common bias line. If the thickness is greater than 300 Å, a modulation transfer function (MTF) characteristic may be deteriorated.

A negative bias voltage may be applied to the first conductive pattern14aand the second conductive pattern14bthrough the connection conductive pattern18. Thus, the first conductive pattern14aand the second conductive pattern14bmay function as a common bias line. As a result, it is possible to capture holes which may exist at a surface of the first substrate1being in contact with the pixel isolation portion DTI, and thus a dark current may be reduced or minimized.

The connection conductive pattern18may function as an interconnection line for applying a voltage to the first conductive pattern14aand the second conductive pattern14b. An electrical resistance of the material of the connection conductive pattern18may be less than an electrical resistance of the material of the first and second conductive patterns14aand14b. Thus, a voltage may be quickly applied to the first conductive pattern14aand the second conductive pattern14bthrough the connection conductive pattern18. As a result, an operating speed of the image sensor500may be improved.

The insulating liner12may be disposed between the conductive structure20and the first substrate1. Each of the insulating liner12and the first filling insulation pattern16may include an insulating material of which a refractive index is different from that of the first substrate1. Here, a density of the insulating material included in the insulating liner12may be greater than a density of the insulating material included in the first filling insulation pattern16. For example, the insulating liner12and the first filling insulation pattern16may include silicon oxide. Here, a density of the silicon oxide included in the insulating liner12may be greater than a density of the silicon oxide included in the first filling insulation pattern16.

The second filling insulation pattern22may be disposed between the conductive structure20and the interlayer insulating layer IL. For example, the second filling insulation pattern22may include silicon oxide. The insulating liner12may be disposed between the shallow device isolation portion STI and the second filling insulation pattern22. Although not shown in the drawings, the second filling insulation pattern22may have a mesh shape overlapping the pixel isolation portion DTI when viewed in a plan view. Bottom surfaces of the shallow device isolation portion STI, the insulating liner12and the second filling insulation pattern22may be substantially coplanar with each other and may protrude below the first surface1a.

The pixel isolation portion DTI may prevent crosstalk between adjacent unit pixels UP and improve a modulation transfer function (MTF) characteristic. When a difference in refractive index between the pixel isolation portion DTI and the first substrate1increases, the effect of preventing the crosstalk may be increased and the MTF characteristic may be more improved. To this end, the pixel isolation portion DTI may include the air gap region AG corresponding to an air layer having the greatest refractive index difference from silicon of the first substrate1. However, if the pixel isolation portion DTI includes only the air gap region AG, durability of the image sensor500may be deteriorated and a crack may occur at the first substrate1. According to the embodiments of the disclosure, the pixel isolation portion DTI may further include the first filling insulation pattern16, the insulating liner12, and the conductive structure20, and thus a crack of the first substrate1may be prevented and the durability of the image sensor500may be improved. The first filling insulation pattern16may maintain the air gap region AG in the pixel isolation portion DTI.

If the pixel isolation portion DTI includes the insulating liner12and a poly-silicon pattern in the deep trench10without the air gap region AG, poly-silicon may have a property of partially absorbing light, and thus the MTF characteristic may be deteriorated. Photosensitivity may be reduced by the deterioration of the MTF characteristic. If the insulating liner12has a relatively thick thickness to prevent the deterioration of the MTF characteristic, a voltage applied to the poly-silicon pattern may not affect the first substrate1by a strong insulating property of the insulating liner12, and thus a dark current may be increased. In some embodiments, the insulating liner12may have a thickness of, for example, 100 Å to 250 Å, and thus the dark current may be reduced and/or minimized and the deterioration of the MTF characteristic may be minimized and/or prevented. As a result, the photosensitivity may be improved.

The pixel isolation portion DTI of the image sensor500according to some embodiments may include the insulating liner12, the conductive structure20, the first filling insulation pattern16, and the air gap region AG. Thus, the crosstalk may be prevented, the MTF characteristic may be improved, and the dark current may be reduced or minimized. In addition, a crack of the first substrate1may be prevented, and the durability of the image sensor500may be improved.

As illustrated inFIG.5A, in the conductive structure20, lower portions of the first and second conductive patterns14aand14bmay protrude below a bottom surface of the connection conductive pattern18. A top surface and the bottom surface of the connection conductive pattern18may be flat. Alternatively, as illustrated inFIG.5B, each of the top and bottom surfaces of the connection conductive pattern18may be convex upward. Alternatively, as illustrated inFIG.5C, bottom surfaces of the first and second conductive patterns14aand14bmay be coplanar with the bottom surface of the connection conductive pattern18, and the bottom surfaces of the conductive patterns14a,14band18may be flat.

The air gap region AG may be spaced apart from entire inner sidewalls of the first and second conductive patterns14aand14bas illustrated inFIGS.5A to5C. Alternatively, the air gap region AG may expose portions of the inner sidewalls of the first and second conductive patterns14aand14bas illustrated inFIG.5D.

The second surface1bmay be in contact with a first fixed charge layer24. A protrusion24pof the first fixed charge layer24may protrude downward to define a top end portion of the air gap region AG. The protrusion24pof the first fixed charge layer24may be referred to as a fixed charge layer protrusion24p. The first fixed charge layer24may be formed of a single layer or multi-layer including at least one of a metal oxide layer containing insufficient oxygen in terms of a stoichiometric ratio or a metal fluoride layer containing insufficient fluorine in terms of a stoichiometric ratio. Thus, the first fixed charge layer24may have negative fixed charges. The first fixed charge layer24may be formed of a single layer or multi-layer including a metal oxide layer and/or metal fluoride layer including at least one of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium (Y), or a lanthanoid. For example, the first fixed charge layer24may include a hafnium oxide layer and/or an aluminum oxide layer. A dark current and a white spot may be minimized or prevented by the first fixed charge layer24.

A second fixed charge layer42and a first protective layer44may be sequentially stacked on the first fixed charge layer24. The second fixed charge layer42may include a single layer or multi-layer including at least one of a metal oxide layer or a metal fluoride layer. For example, the second fixed charge layer42may include a hafnium oxide layer and/or an aluminum oxide layer. The second fixed charge layer42may reinforce the first fixed charge layer24or may function as an adhesive layer. For example, the first protective layer44may include at least one of PETEOS, SiOC, SiO2, SiN, a hafnium oxide layer, or an aluminum oxide layer. The first protective layer44may function as an anti-reflection layer and/or a planarization layer.

Referring toFIGS.3and4, in the edge region EG, a connection contact BCA may penetrate the first protective layer44, the second fixed charge layer42, the first fixed charge layer24and a portion of the first substrate1so as to be in contact with the first and second conductive patterns14aand14bof the conductive structure20. The connection contact BCA may be disposed in a first trench46. The connection contact BCA may include a diffusion barrier pattern48bconformally covering an inner sidewall and a bottom surface of the first trench46, a first metal pattern52on the diffusion barrier pattern48b, and a second metal pattern54filling the first trench46. The diffusion barrier pattern48bmay include, for example, titanium. The first metal pattern52may include, for example, tungsten. The second metal pattern54may include, for example, aluminum. The diffusion barrier pattern48band the first metal pattern52may extend onto the first protective layer44so as to be electrically connected to other interconnection lines or vias and/or contacts. In the edge region EG, a portion48pof the diffusion barrier pattern48bmay protrude into the air gap region AG of the pixel isolation portion DTI to fill the air gap region AG. The portion48pof the diffusion barrier pattern48bmay be referred to as a diffusion barrier protrusion48p. The diffusion barrier protrusion48pmay not be in contact with the conductive structure20but may be spaced apart from the conductive structure20by the first filling insulation pattern16. Alternatively, when the air gap region AG has the shape ofFIG.5Dto expose the inner sidewalls of the first and second conductive patterns14aand14b, the diffusion barrier protrusion48pmay be in contact with the inner sidewalls of the first and second conductive patterns14aand14b.

In the pixel array region APS, a light blocking pattern48aand a low-refractive index pattern50amay be sequentially stacked on the first protective layer44. In the pixel array region APS, the light blocking pattern48aand the low-refractive index pattern50amay have mesh shapes in a plan view and may overlap the pixel isolation portion DTI. The light blocking pattern48amay have the same material and the same thickness as the diffusion barrier pattern48b. The light blocking pattern48amay include, for example, titanium. The low-refractive index pattern50amay include an organic material. The low-refractive index pattern50amay have a refractive index lower than those of color filters CF1and CF2. For example, the low-refractive index pattern50amay have a refractive index of about 1.3 or less. A sidewall of the low-refractive index pattern50amay be aligned with a sidewall of the light blocking pattern48a. The light blocking pattern48aand the low-refractive index pattern50amay prevent crosstalk between the unit pixels UP adjacent to each other.

A second protective layer56may be stacked on the first protective layer44. The second protective layer56may conformally cover the low-refractive index pattern50a, the light blocking pattern48a, and the connection contact BCA. In the pixel array region APS, color filters CF1and CF2may be disposed between portions of the low-refractive index pattern50aand may be arranged in an array form. Each of the color filters CF1and CF2may correspond to one of a blue color, a green color and a red color. The color filters CF1and CF2may be arranged, for example, in the form of a Bayer pattern, a 2×2 tetra-pattern, or a 3×3 nona-pattern. Alternatively, each of the color filters CF1and CF2may correspond to another color such as a cyan color, a magenta color, or a yellow color.

In the edge region EG, a first optical black pattern CFB may be disposed on the second protective layer56. For example, the first optical black pattern CFB may include the same material as the blue color filter. A micro lens array layer ML may be disposed on the color filters CF1and CF2. The micro lens array layer ML may include convex lens portions overlapping the unit pixels UP, respectively. A portion of the micro lens array layer ML may extend onto the first optical black pattern CFB.

FIGS.6A to6Kare cross-sectional views illustrating a method of manufacturing an image sensor ofFIG.4.

Referring toFIG.6A, a first substrate1including a pixel array region APS and an edge region EG may be prepared. The first substrate1may include a first surface1aand a second surface1bwhich are opposite to each other. The first substrate1may be a single-crystalline silicon wafer or a silicon epitaxial layer. A first mask layer may be formed on the first surface1aof the first substrate1and then may be patterned to form a first mask pattern3. The first mask pattern3may have an opening defining a position of a shallow device isolation portion. For example, the first mask pattern3may include silicon nitride. The first substrate1may be etched using the first mask pattern3as an etch mask to form a shallow trench5.

Referring toFIG.6B, a device isolation layer may be stacked on the first surface1aof the first substrate1to fill the shallow trench5and then may be patterned to form a device isolation pattern7. The device isolation pattern7may cover the first mask pattern3. The device isolation pattern7may include, for example, a silicon oxide layer. The device isolation pattern7may have an opening defining a position of a deep trench10. The device isolation pattern7may cover a portion of a bottom surface and a sidewall of the shallow trench5. The first substrate1may be etched using the device isolation pattern7as an etch mask to form the deep trench10.

Next, an insulating liner12and a first conductive layer14may be sequentially and conformally stacked on the whole of the first surface1aof the first substrate1in which the deep trench10is formed. The insulating liner12and the first conductive layer14may not completely fill the deep trench10. The insulating liner12and the first conductive layer14may be formed by a deposition process having excellent step coverage characteristics. For example, the insulating liner12may be formed by a thermal oxidation process or an atomic layer deposition (ALD) process. The insulating liner12may be formed of, for example, silicon oxide. The first conductive layer14may be formed of poly-silicon doped with dopants. A first filling insulation layer16L may be formed on the first conductive layer14. At this time, the first filling insulation layer16L may be formed by a deposition process having poor step coverage characteristics. For example, the first filling insulation layer16L may be formed by a low-pressure chemical vapor deposition (LPCVD) process. Thus, the first filling insulation layer16L may be formed to include an air gap region AG in the deep trench10. The first filling insulation layer16L may be formed of, for example, silicon oxide or tetraethylorthosilicate (TEOS). Here, a density of silicon oxide of the first filling insulation layer16L may be less than a density of silicon oxide of the insulating liner12.

Referring toFIGS.6B and6C, an etch-back process may be performed on the first filling insulation layer16L to remove the first filling insulation layer16L provided on the device isolation pattern7and to leave a first filling insulation pattern16corresponding to a portion of the first filling insulation layer16L in the deep trench10. At this time, the air gap region AG may not be exposed. In this state, a second conductive layer18L may be formed on the first surface1aof the first substrate1. The second conductive layer18L may be formed of poly-silicon doped with dopants, or a metal containing layer. The second conductive layer18L may fill an upper portion of the deep trench10. At this time, due to the first filling insulation pattern16, the second conductive layer18L may not enter the air gap region AG. Thus, the air gap region AG may be maintained by the first filling insulation pattern16. If the first filling insulation pattern16is not provided, the second conductive layer18L may fill the deep trench10, and thus formation of an air gap may be difficult. In addition, it may be difficult to form the air gap region AG in a process of depositing a poly-silicon layer, or even if the air gap region AG is formed, it may be difficult to uniformly adjust a thickness of the poly-silicon layer on an inner sidewall of the deep trench10.

Referring toFIGS.6C and6D, an etch-back process may be performed on the second conductive layer18L and the first conductive layer14to remove portions of the first and second conductive layers14and18L provided on the device isolation pattern7. Thus, the insulating liner12may be exposed, and a first conductive pattern14a, a second conductive pattern14band a connection conductive pattern18may be formed in the deep trench10. As a result, a conductive structure20may be formed.

Referring toFIG.6E, a second filling insulation layer22L may be formed on the insulating liner12to fill an upper portion of the deep trench10. The second filling insulation layer22L may be formed of a middle temperature oxide (MTO) or a high density plasma (HDP) oxide. In addition, an annealing process may be performed. By the annealing process, dopants in the conductive structure20may be activated and a phase of the poly-silicon may be changed from an amorphous state into a crystalline state.

Referring toFIG.6F, a chemical mechanical polishing (CMP) process may be performed to remove the device isolation pattern7, the insulating liner12and the second filling insulation layer22L on the first mask pattern3and to expose the first mask pattern3. At this time, a shallow device isolation portion STI corresponding to a portion of the device isolation pattern7may be formed. The first mask pattern3may function as a CMP stop layer.

Referring toFIG.6G, the first mask pattern3may be removed to expose the first surface1aof the first substrate1. An ion implantation process, etc. may be performed on the first substrate1to form photoelectric conversion portions PD. A gate insulating layer Gox, transfer gates TG, floating diffusion regions FD, first contact plugs17, first interconnection lines15and first interlayer insulating layers IL may be formed on the first surface1aof the first substrate1through various processes.

Referring toFIG.6H, a back grinding process may be performed to remove a portion of the first substrate1and a portion of the pixel isolation portion DTI, which are adjacent to the second surface1b. At this time, portions of the insulating liner12, the first and second conductive patterns14aand14band the first filling insulation pattern16of the pixel isolation portion DTI may be removed, and the air gap region AG may be exposed.

Referring toFIG.6I, a first fixed charge layer24may be formed or stacked on the second surface1b. At this time, a portion24pof the first fixed charge layer24may protrude to an entrance of the air gap region AG and may close the entrance of the air gap region AG. A second fixed charge layer42and a first protective layer44may be sequentially stacked on the first fixed charge layer24. A second mask pattern MK may be formed on the first protective layer44. The second mask pattern MK may have a first opening OP1exposing a portion of the edge region EG.

Referring toFIG.6J, in the edge region EG, the first protective layer44, the second fixed charge layer42, the first fixed charge layer24, the first substrate1and a portion of the pixel isolation portion DTI may be etched using the second mask pattern MK as an etch mask to form a first trench46exposing the first and second conductive patterns14aand14bof the pixel isolation portion DTI. At this time, the air gap region AG may be exposed at a bottom surface of the first trench46.

Referring toFIGS.6J and6K, the second mask pattern MK may be removed. A diffusion barrier layer and a first metal layer may be sequentially formed on the first protective layer44. At this time, a portion48pof the diffusion barrier layer may enter the air gap region AG exposed at the bottom surface of the first trench46and thus may fill the air gap region AG. The first metal layer may be etched to form a first metal pattern52in the edge region EG. The diffusion barrier layer may be etched to form a light blocking pattern48ain the pixel array region APS and a diffusion barrier pattern48bin the edge region EG at the same time. A low-refractive index pattern50amay be formed on the light blocking pattern48ain the pixel array region APS. A second metal pattern54filling the first trench46may be formed. The second metal pattern54, the first metal pattern52and the diffusion barrier pattern48bmay constitute a connection contact BCA.

Subsequently, referring toFIG.4, a second protective layer56may be conformally formed on the first protective layer44and the connection contact BCA.

Color filters CF1and CF2may be formed between portions of the low-refractive index pattern50aon the second protective layer56. At this time, a first optical black pattern CFB may also be formed in the edge region EG. A micro lens array layer ML may be formed on the color filters CF1and CF2and the first optical black pattern CFB. Thus, the image sensor500ofFIG.4may be manufactured.

In the method of manufacturing the image sensor according to the embodiments of the disclosure, the image sensor having the pixel isolation portion, which improves the MTF characteristics and reduces or minimizes the dark current, may be stably manufactured without a process defect, and a yield may be improved.

FIG.7is a cross-sectional view taken along the line A-A′ ofFIG.3according to some embodiments of the disclosure.FIGS.8A and8Bare enlarged views of a portion ‘P1’ ofFIG.7according to some embodiments of the disclosure.

Referring toFIGS.7and8A, in an image sensor501according to some embodiments, portions24pof the first fixed charge layer24of the pixel array region APS and the edge region EG may enter the air gap regions AG to fill the air gap regions AG, respectively. The portions24pof the first fixed charge layer24may be referred to as fixed charge layer protrusions24p. UnlikeFIG.4, in the edge region EG, a portion of the diffusion barrier pattern48bmay not enter the air gap region AG. In some embodiments, a bottom surface of the diffusion barrier pattern48bmay be in contact with a top surface of the fixed charge layer protrusion24p. The protrusion24pof the first fixed charge layer24may not be in contact with the conductive structure20but may be spaced apart from the conductive structure20by the first filling insulation pattern16. Alternatively, when the air gap region AG of some embodiments has the shape ofFIG.5Dto expose the inner sidewalls of the first and second conductive patterns14aand14b, the protrusion24pof the first fixed charge layer24may be in contact with the inner sidewalls of the first and second conductive patterns14aand14b. Other structures and/or components of the image sensor501according to some embodiments may be the same or similar to those described above.

Even if the air gap region AG is filled with the fixed charge layer protrusion24p, the first fixed charge layer24may include a material (e.g., an aluminum oxide layer and/or a hafnium oxide layer) having a high refractive index, and thus light obliquely incident to a sidewall of the pixel isolation portion DTI may be totally reflected. As a result, crosstalk between the unit pixels UP may be prevented and the MTF characteristics may be improved.

Alternatively, as illustrated inFIG.8B, a protrusion24pof the first fixed charge layer24, a protrusion42pof the second fixed charge layer42and a protrusion44pof the first protective layer44may be inserted in the air gap region AG. The protrusion24pof the first fixed charge layer24, the protrusion42pof the second fixed charge layer42and the protrusion44pof the first protective layer44may conformally cover an inner sidewall of the first filling insulation pattern16in the air gap region AG. The protrusion44pof the first protective layer44may fill the air gap region AG. In some embodiments, for example, the first fixed charge layer24may include aluminum oxide, the second fixed charge layer42may include hafnium oxide, and the first protective layer44may include aluminum oxide. When the pixel isolation portion DTI has the structure ofFIG.8B, in the edge region EG, the connection contact BCA may be in contact with the protrusion24pof the first fixed charge layer24, the protrusion42pof the second fixed charge layer42and the protrusion44pof the first protective layer44.

FIGS.9A and9Bare cross-sectional views illustrating a method of manufacturing an image sensor ofFIG.7.

Referring toFIG.9A, when a first fixed charge layer24is formed on the second surface1bin the step ofFIG.6H, a portion (or a protrusion)24pof the first fixed charge layer24may be inserted into the exposed air gap region AG to fill the air gap region AG. A second fixed charge layer42and a first protective layer44may be sequentially formed on the first fixed charge layer24. A second mask pattern MK may be formed on the first protective layer44.

Referring toFIG.9B, in the edge region EG, the first protective layer44, the second fixed charge layer42, the first fixed charge layer24, the first substrate1and a portion of the pixel isolation portion DTI may be etched using the second mask pattern MK as an etch mask to form a first trench46exposing the first and second conductive patterns14aand14bof the pixel isolation portion DTI. At this time, the protrusion24pof the first fixed charge layer24may be exposed at a bottom surface of the first trench46. Subsequently, the processes described with reference toFIG.6Kmay be performed.

FIG.10is a cross-sectional view taken along the line A-A′ ofFIG.3according to some embodiments of the disclosure.

Referring toFIG.10, in an image sensor502according to some embodiments, a conductive structure20may include a first conductive portion14a, a second conductive portion14b, and a connection conductive portion14c. The first conductive portion14a, the second conductive portion14band the connection conductive portion14cmay be formed of the same material in one body. The first conductive portion14a, the second conductive portion14band the connection conductive portion14cmay include poly-silicon doped with the same kind of dopants at the same concentration. The connection conductive portion14cmay have the same planar shape as the connection conductive pattern18ofFIG.3. The connection conductive portion14cmay be disposed between the first filling insulation pattern16and the first fixed charge layer24and may be in contact with the first filling insulation pattern16and the first fixed charge layer24. A top surface of the insulating liner12may be lower than a top surface of the connection conductive portion14cand/or the second surface1b. A protrusion24pof the first fixed charge layer24may be disposed between the first substrate1and the conductive structure20and may be in contact with the top surface of the insulating liner12. Other structures and/or components of the image sensor502according to some embodiments may be the same or similar to those described above.

FIGS.11A to11Dare cross-sectional views illustrating a method of manufacturing an image sensor ofFIG.10.

Referring toFIG.11A, in the step ofFIG.6C, after the formation of the first filling insulation pattern16, the second conductive layer18L may not be formed, but an etching process may be performed on the first conductive layer14to remove the first conductive layer14provided on the device isolation pattern7and to form a conductive structure20including a first conductive portion14a, a second conductive portion14b, and a connection conductive portion14c. The etching process may be anisotropically or isotropically performed. The processes described with reference toFIGS.6E to6Gmay be performed in the state ofFIG.11A.

Referring toFIGS.11B and11C, a back grinding process may be performed on a portion of the first substrate1adjacent to the second surface1bto expose the insulating liner12. A wet isotropic etching process may be performed to remove the exposed insulating liner12and to expose a top surface and an upper sidewall of the connection conductive portion14cand an upper sidewall of the first substrate1. At this time, a top surface of the insulating liner12may be lowered from the second surface1b, and thus a recess region R1may be formed on the insulating liner12.

Referring toFIGS.11C and11D, a first fixed charge layer24may be formed on the second surface1b. At this time, a portion24pof the first fixed charge layer24may be inserted into the recess region R1. A second fixed charge layer42and a first protective layer44may be sequentially formed on the first fixed charge layer24. A second mask pattern MK may be formed on the first protective layer44. Subsequently, the processes described with reference toFIGS.6J and6Kmay be performed.

FIG.12is a cross-sectional view taken along the line A-A′ ofFIG.3according to some embodiments of the disclosure.

Referring toFIG.12, in an image sensor503according to some embodiments, a conductive structure20included in the pixel isolation portion DTI may include only a first conductive pattern14aand a second conductive pattern14b. The second surface1bmay be covered with a first fixed charge layer24. A connection conductive pattern18may penetrate the first fixed charge layer24so as to be in contact with the first conductive pattern14aand the second conductive pattern14b. Other structures and/or components of the image sensor503according to some embodiments may be the same or similar to those described above.

FIGS.13A and13Bare cross-sectional views illustrating a method of manufacturing an image sensor ofFIG.12.

Referring toFIG.13A, the processes described with reference toFIGS.6E to6Gmay be performed in the state ofFIG.11A, and then, a back grinding process may be performed on a portion of the first substrate1adjacent to the second surface1bto expose the first filling insulation pattern16. At this time, a portion of the insulating liner12and the connection conductive portion14cof the conductive structure20may also be removed. However, the air gap region AG may not be exposed. Alternatively, the connection conductive portion14cof the conductive structure20in the state ofFIG.11Cmay be removed to expose the first filling insulation pattern16. Subsequently, a first fixed charge layer24may be formed on the second surface1b.

Referring toFIG.13B, the first fixed charge layer24may be etched to form a second opening OP2exposing the first conductive pattern14aand the second conductive pattern14bof the conductive structure20. The second opening OP2may have a mesh shape overlapping the pixel isolation portion DTI when viewed in a plan view. A conductive layer may be deposited on the first fixed charge layer24and then may be etched to form a connection conductive pattern18which is in contact with the first and second conductive patterns14aand14bthrough the second opening OP2. The deposition process of the conductive layer for the formation of the connection conductive pattern18may be performed at a temperature of, for example, 400 degrees Celsius or less, and thus the interconnection lines15on the first surface1amay not be damaged. In addition, the etching process may be performed on the conductive layer provided on the first fixed charge layer24, and thus the first fixed charge layer24may protect the second surface1bof the first substrate1from an etchant. As a result, the second surface1bmay not be damaged. Subsequently, the processes described with reference toFIGS.61to6Kmay be performed.

FIG.14is a cross-sectional view taken along the line A-A′ ofFIG.3according to some embodiments of the disclosure.

Referring toFIG.14, an image sensor504according to some embodiments may include at least one substrate trench TC formed in the second surface1bof the first substrate1. The substrate trench TC may have at least one of various shapes such as a polygonal shape (e.g., a triangular shape, a tetragonal shape, a pentagonal shape, etc.), a cross shape, and a star shape when viewed in a plan view. The substrate trench TC may be formed at a position at which incident light is focused by the lens portion of the micro lens array layer ML. The first fixed charge layer24may be partially inserted into the substrate trench TC to conformally cover an inner sidewall and a bottom surface of the substrate trench TC. When the substrate trench TC has a relatively narrow width, the substrate trench TC may be filled with the first fixed charge layer24. A portion of the second fixed charge layer42may also be inserted into the substrate trench TC.

The substrate trench TC may function as a light splitter for scattering incident light provided to the second surface1b. Thus, the incident light may be scattered in the first substrate1to cause multiple reflections and to increase a light path. Therefore, a quantum efficiency may be increased or improved. As a result, a sensing sensitivity of light having a relatively long wavelength (e.g., infrared light or red light) may be improved. The image sensor504may be referred to as an infrared sensor. Other structures and/or components of the image sensor504according to some embodiments may be the same or similar to those described above.

FIG.15is a cross-sectional view illustrating an image sensor according to some embodiments of the disclosure.

Referring toFIG.15, an image sensor505according to some embodiments may have a structure in which a first sub-chip CH1and a second sub-chip CH2are bonded to each other. For example, the first sub-chip CH1may perform an image sensing function. For example, the second sub-chip CH2may include circuits for driving the first sub-chip CH1and/or for storing electrical signals generated from the first sub-chip CH1.

The second sub-chip CH2may include a second substrate100, a plurality of transistors TR disposed on the second substrate100, a second interlayer insulating layer110covering the second substrate100, and second interconnection lines112disposed in the second interlayer insulating layer110. The second interlayer insulating layer110may have a single-layered or multi-layered structure including at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a porous insulating layer. The first sub-chip CH1and the second sub-chip CH2may be bonded to each other. Thus, a first interlayer insulating layer IL of the first sub-chip CH1may be in contact with the second interlayer insulating layer110.

The first sub-chip CH1may include a first substrate1including a pad region PAD, a connection region CNR, an optical black region OB, and a pixel array region APS. The first sub-chip CH1in the pixel array region APS and a portion of the connection region CNR may have the same structure as described with reference toFIGS.3and4. In other words, the pixel array region APS may include a plurality of unit pixels UP. In the pixel array region APS, a pixel isolation portion DTI may be disposed in the first substrate1to isolate the unit pixels UP from each other. A shallow device isolation portion STI may be disposed adjacent to the first surface1ain the first substrate1. The pixel isolation portion DTI may penetrate the shallow device isolation portion STI. A photoelectric conversion portion PD may be disposed in the first substrate1in each of the unit pixels UP. A transfer gate TG may be disposed on the first surface1aof the first substrate1of each of the unit pixels UP. A floating diffusion region FD may be disposed in the first substrate1at a side of the transfer gate TG. The first surface1amay be covered with first interlayer insulating layers IL.

The pixel isolation portion DTI may include the insulating liner12, the first filling insulation pattern16, the conductive structure20, the second filling insulation pattern22and the air gap region AG, described with reference toFIGS.3to5D. The structure of the pixel isolation portion DTI is not limited to the structures ofFIGS.3to5D. In some embodiments, the pixel isolation portion DTI may have one of the structures described with reference toFIGS.7to8B,10and12.

Light may not be incident into the first substrate1of the optical black region OB. The pixel isolation portion DTI may extend into the optical black region OB to isolate a first black pixel UPO1and a second black pixel UPO2from each other. The photoelectric conversion portion PD may be disposed in the first substrate1of the first black pixel UPO1. The photoelectric conversion portion PD may not exist in the first substrate1of the second black pixel UPO2. A transfer gate TG and a floating diffusion region FD may be disposed in each of the first and second black pixels UPO1and UPO2. The first black pixel UPO1may sense the amount of charges generated from the photoelectric conversion portion PD into which light is not incident, and thus the first black pixel UPO1may provide a first reference charge amount. The first reference charge amount may be used as a relative reference value when the amounts of charges generated from the unit pixels UP are calculated. The second black pixel UPO2may sense the amount of charges generated in a state in which the photoelectric conversion portion PD does not exist, and thus the second black pixel UPO2may provide a second reference charge amount. The second reference charge amount may be used as data for removing process noise.

The first fixed charge layer24, the second fixed charge layer42, the first protective layer44and the second protective layer56may extend onto the second surface1bof the optical black region OB, the connection region CNR and the pad region PAD. The edge region EG described with reference toFIGS.3to5D,7to8B,10and12may correspond to a portion of the connection region CNR ofFIG.15.

Referring toFIGS.4and15, in the connection region CNR, a connection contact BCA may penetrate the first protective layer44, the second fixed charge layer42, the first fixed charge layer24and a portion of the first substrate1so as to be in contact with the first conductive pattern14aand the second conductive pattern14bof the pixel isolation portion DTI. The connection contact BCA may be disposed in a first trench46. The connection contact BCA may include a first diffusion barrier pattern48bconformally covering an inner sidewall and a bottom surface of the first trench46, a first metal pattern52on the first diffusion barrier pattern48b, and a second metal pattern54filling the first trench46. A protrusion48pof the first diffusion barrier pattern48bmay be inserted into the air gap region AG.

A portion of the first diffusion barrier pattern48bmay extend onto the first protective layer44of the optical black region OB to provide a first optical black pattern48c. A portion of the first metal pattern52may extend onto the first optical black pattern48cof the optical black region OB to provide a second optical black pattern52a. The second protective layer56may cover the second optical black pattern52aand the connection contact BCA. A third optical black pattern CFB may be disposed on the second protective layer56of the optical black region OB and the connection region CNR.

In the connection region CNR, a first via V1may be disposed at a side of the connection contact BCA. The first via V1may be referred to as a back bias stack via. The first via V1may penetrate the first protective layer44, the second fixed charge layer42, the first fixed charge layer24, the first substrate1, the first interlayer insulating layers IL and a portion of the second interlayer insulating layer110so as to be in contact with at least one of the first interconnection lines15and at least one of the second interconnection lines112.

The first via V1may be disposed in a first via hole H1. The first via V1may include a second diffusion barrier pattern48dand a first via pattern52bon the second diffusion barrier pattern48d. The second diffusion barrier pattern48dmay be connected to the first diffusion barrier pattern48b. The first via pattern52bmay be connected to the first metal pattern52. The connection contact BCA may be connected to at least one of the first interconnection lines15and at least one of the second interconnection lines112through the first via V1.

Each of the second diffusion barrier pattern48dand the first via pattern52bmay conformally cover an inner surface of the first via hole H1. The second diffusion barrier pattern48dand the first via pattern52bmay not completely fill the first via hole H1. A first low-refractive index residual layer50bmay fill the first via hole H1. A color filter residual layer CFR may be disposed on the first low-refractive index residual layer50b.

An external connection pad62and a second via V2which are connected to each other may be disposed in the pad region PAD. The external connection pad62may penetrate the first protective layer44, the second fixed charge layer42, the first fixed charge layer24, and a portion of the first substrate1. The external connection pad62may be disposed in a second trench60. The external connection pad62may include a third diffusion barrier pattern48eand a first pad pattern52cwhich sequentially and conformally cover an inner sidewall and a bottom surface of the second trench60, and a second pad pattern54afilling the second trench60.

The second via V2may penetrate the first protective layer44, the second fixed charge layer42, the first fixed charge layer24, the first substrate1, the first interlayer insulating layers IL and a portion of the second interlayer insulating layer110so as to be in contact with at least one of the second interconnection lines112. The external connection pad62may be connected to at least one of the second interconnection lines112through the second via V2. The second via V2may be disposed in a second via hole H2. The second via V2may include a fourth diffusion barrier pattern48fand a second via pattern52dwhich sequentially and conformally cover an inner sidewall and a bottom surface of the second via hole H2. The fourth diffusion barrier pattern48fand the second via pattern52dmay not completely fill the second via hole H2. A second low-refractive index residual layer50cmay fill the second via hole H2. A color filter residual layer CFR may be disposed on the second low-refractive index residual layer50c.

The light blocking pattern48a, the first diffusion barrier pattern48b, the first optical black pattern48cand the second to fourth diffusion barrier patterns48dto48fmay have the same thickness and the same material (e.g., titanium). The first metal pattern52, the second optical black pattern52a, the first via pattern52b, the first pad pattern52cand the second via pattern52dmay have the same thickness and the same material (e.g., tungsten). The second metal pattern54and the second pad pattern54amay have the same material (e.g., aluminum).

The low-refractive index pattern50a, the first low-refractive index residual layer50band the second low-refractive index residual layer50cmay have the same material. The color filter residual layer CFR may have the same color and material as one of the color filters CF1and CF2.

The second protective layer56may extend into the pad region PAD and may have an opening exposing the second pad pattern54a. The micro lens array layer ML may extend into the optical black region OB, the connection region CNR and the pad region PAD. The micro lens array layer ML may have an opening35exposing the second pad pattern54ain the pad region PAD.

FIG.16is a plan view illustrating an image sensor according to some embodiments of the disclosure.FIG.17is a cross-sectional view taken along a line A-A′ ofFIG.16. An optical black region, a pad region and a portion of a connection region are omitted inFIG.16. A cross-sectional view taken along a line C-C′ ofFIG.16may include the pixel isolation portion DTI ofFIG.4, instead of a through-contact structure CX ofFIG.17. The cross-sectional view taken along the line C-C′ ofFIG.16may be the same or similar to those asFIG.4.

Referring toFIGS.4,16and17, an image sensor506according to some embodiments may be an example of an organic CMOS image sensor. In the plan view ofFIG.16, a through-contact structure CX penetrating the pixel isolation portion DTI may be disposed at a side of each of the unit pixels UP. The through-contact structure CX may include a contact pattern242extending from the first surface1a toward the second surface1b, a contact insulating layer244surrounding the contact pattern242, and a third filling insulation pattern246between the contact pattern242and a first interlayer insulating layer IL, which is closest to the first surface1a among the first interlayer insulating layers IL. The contact pattern242may include a conductive material. The contact pattern242may be insulated from the conductive structure20of the pixel isolation portion DTI.

A second contact plug67may penetrate the first interlayer insulating layer IL closest to the first surface1aand the third filling insulation pattern246so as to be in contact with the contact pattern242. The second contact plug67may be connected to one of the first interconnection lines15. Each of the color filters CF1and CF2may correspond to a blue color or a red color. A planarization layer51may cover the color filters CF1and CF2. For example, the planarization layer51may include silicon oxide and/or plasma-enhanced tetraethylorthosilicate (PETEOS). In the pixel array region APS and the optical black region OB, pixel electrodes PE may be disposed on the planarization layer51and may be spaced apart from each other. The pixel electrodes PE may overlap the unit and black pixels UP, UPO1and UPO2, respectively. A third contact plug53may penetrate the planarization layer51and may electrically connect the pixel electrode PE to the through-contact structure CX.

The pixel electrodes PE may be covered with an organic photoelectric conversion layer OPD. The organic photoelectric conversion layer OPD may include a P-type organic semiconductor material and an N-type organic semiconductor material, which form a PN junction. Alternatively, the organic photoelectric conversion layer OPD may include quantum dots or a chalcogenide. The organic photoelectric conversion layer OPD may perform photoelectric conversion of light having a specific color (e.g., a green color). A common electrode CE may be disposed on the organic photoelectric conversion layer OPD. The pixel electrodes PE and the common electrode CE may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and/or an organic transparent conductive material.

A micro lens array layer ML may be disposed on the common electrode CE. An optical black pattern OBP may be disposed in the micro lens array layer ML in the optical black region OB. The optical black pattern OBP may include, for example, an opaque metal (e.g., aluminum). Other components may be the same or similar to those described with reference toFIGS.4and15. The image sensor506according to some embodiments may include the organic photoelectric conversion layer OPD, and thus each of the unit pixels UP may sense two colors of light at the same time.

The pixel isolation portion of the image sensor according to the disclosure may include the insulating liner, the conductive structure, the first filling insulation pattern, and the air gap region. Thus, the crosstalk may be prevented, and the MTF characteristics may be improved to increase the photosensitivity. In addition, the dark current may be reduced or minimized, a crack of the substrate may be prevented, and the durability of the image sensor may be improved.

Descriptions of features or aspects within each example embodiment should typically be considered as available for other similar features or aspects in other example embodiments. For example, one of ordinary skill in the art to which the inventive concept pertains would understand that the configuration of an image sensor described with reference toFIGS.3to17may be changed in various ways, and one or more features described in the embodiments ofFIGS.3to17may be combined or replaced with each other.

In the method of manufacturing the image sensor according to the embodiments of the disclosure, the image sensor having the pixel isolation portion capable of improving the MTF characteristics and of reducing or minimizing the dark current may be stably manufactured without a process defect, and a yield may be improved.

While the disclosure have been described with reference to example embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure. Therefore, it should be understood that the above embodiments are not limiting, but illustrative. Thus, the scopes of the disclosure are to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing description.