Patent ID: 12218139

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

The disclosure provides an optimized layout and metal structure to achieve both high density and high speed applications.FIG.1is a sectional view of a semiconductor structure100constructed in accordance to some embodiments. In some examples, semiconductor structure100is formed on fin active regions and includes Fin Field-Effect Transistors (FinFETs). In other examples, semiconductor structure100is firmed on flat fin active regions and include Field-Effect Transistors (FETs) and Gate All Around (GAA) transistors. Semiconductor structure100includes one or more standard cells to be incorporated and repeatedly used to Integrated Circuit (IC) designs. Those standard cells may include various basic circuit devices, such as, an inverter, a NAND gate, NOR gate, an AND gate, an OR gate, and a flip-flop, which are popular in digital circuit design for applications, such as, Central Processing Unit (CPU), Graphic Processing Unit (GPU), and System-on-Chip (SOC) designs. For example, semiconductor structure100includes a cell defined in dashed lines101.

Semiconductor structure100includes a substrate102. In examples, substrate102includes silicon. Alternatively, substrate102may include an elementary semiconductor, such as silicon or germanium in a crystalline structure; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; or combinations thereof. In other examples, substrate102may also include a Silicon-on-Insulator (SoI) substrate. The SoI substrates are fabricated using Separation by Implantation of Oxygen (SIMOX), wafer bonding, and/or other suitable methods.

Substrate102also includes various isolation features, such as isolation features104formed on semiconductor substrate102and defining various active regions on substrate102, such as an active region108. Isolation features104utilizes isolation technology, such as Shallow Trench Isolation (STI), to define and electrically isolate the various active regions. Isolation features104may include silicon oxide, silicon nitride silicon oxynitride, other suitable dielectric materials, or combinations thereof. Isolation features104are formed by any suitable process. For example, forming STI features includes a lithography process to expose a portion of the substrate (for example, by using a dry etching and/or wet etching), filling the trench (for example, by using a chemical vapor deposition process) with one or more dielectric materials, and planarizing the substrate and removing excessive portions of the dielectric material(s) by a polishing process, such as a chemical Mechanical Polishing (CMP) process. In some examples, the filled trench may have a multilayer structure, such as a thermal oxide linear layer and filling layer(s) of silicon nitride or silicon oxide.

In some examples, active region108is a region with semiconductor surface wherein various doped features are formed and configured to one or more device, such as a diode, a transistor, and/or other suitable devices. Active region108may include a semiconductor material similar to that (such as silicon) of the bulk semiconductor material of substrate102or different semiconductor material, such as Silicon Germanium (SiGe), Silicon Carbide (SiC), or multiple semiconductor material layers (such as alternative silicon and silicon germanium layers) formed on substrate102by epitaxial growth, for performance enhancement, such as strain effect to increase carrier mobility.

In examples, active region108is three dimensional, such as a fin active region extended above isolation features104. The fin active region is extruded from semiconductor substrate102and has a three dimensional profile for more effective coupling between the channel and the gate electrode of a FET. Active region108may be formed by selective etching of recess isolation features104, or selective epitaxial growth to grow active regions with a semiconductor same or different from that of semiconductor substrate102, or a combination thereof.

Substrate102further includes various doped features, such as n-types doped wells, p-type doped wells, source and drain features, other doped features, or a combination thereof configured to form various devices or components of the devices, such as source and drain features of a field-effect transistor. Semiconductor structure100includes various IC devices formed on semiconductor substrate102. The IC devices includes Fin Field-Effect Transistors (FinFETs), Gate All Around (GAA) transistors, diodes, bipolar transistors, imaging sensors, resistors, capacitors, inductors, memory cells, or a combination thereof. InFIG.1, exemplary FETs are provided only for illustration.

Semiconductor structure100further includes a gate (or gate stack)110having elongated shape oriented in a first direction (X direction). In examples, X-direction and Y direction are orthogonal and define a top surface112of substrate102. A gate is a feature of a FET and functions with other features, such as source/drain (S/D) features and a channel; wherein the channel is in the active region and is directly underlying the gate; and the S/D features are in the active region and are disposed on two sides of the gate.

Semiconductor structure100also includes one or more interconnection gates114formed on semiconductor substrate102. Interconnection gates114also has an elongated shape oriented in the X direction. Interconnection gates114are similar to gate110in terms of structure, composition, and formation. For example, gate110and interconnection gates114are collectively and simultaneously formed by a same procedure, such as a gate last process. However, interconnection gates114are disposed and configured differently and therefore functions differently. In some examples, interconnection gates114are at least partially landing on isolation features104. For example, interconnection gates114are partially landing on active region108and partially landing on isolation features104. Interconnection gates114, therefore provide isolation between adjacent IC devices and additionally provides pattern density adjustment for improved fabrication, such as etching, deposition and Chemical Mechanical Polishing (CMP). In some examples, interconnection gates114, therefore, are formed on boundary lines between the adjacent cells. Furthermore, interconnection gates114are connected to metal lines through gate contacts and therefore functions as a location interconnection as well.

Gate110and interconnection gates114have same compositions, formed by a same procedure, and may have a same structure. For example, gate110may include a gate dielectric layer (such as silicon oxide) and a gate electrode (such as doped polysilicon) disposed on the gate dielectric layer. In some examples, gate110includes other proper material for circuit performance and manufacturing integration. For example, the dielectric layer includes an interfacial layer (such as silicon oxide) and a high k dielectric material layer. The gate electrode includes metal, such as aluminum, copper, tungsten, metal silicide, doped polysilicon, other proper conductive material or a combination thereof. The gate electrode may include multiple conductive films designed such as a capping layer, a work function metal layer, a blocking layer and a filling metal layer (such as aluminum or tungsten). The multiple conductive films are designed for work function matching to n-type FET (nFET) and p-type FET (pFET), respectively.

In some examples, gate110is formed by a different method with a different structure. For example, gate110may be formed by various deposition techniques and a proper procedure, such as gate-last process, wherein a dummy gate is first formed, and then is replaced by a metal gate after the formation the source and drain features. Alternatively, the gate is formed by a high-k-last process, wherein the both gate dielectric material layer and the gate electrode are replaced by high k dielectric material and metal, respectively, after the formation of the source and drain features. In a high-k-last process, a dummy gate is first formed by deposition and patterning; then source/drain features are formed on gate sides and an inter-layer dielectric layer is formed on the substrate; the dummy gate is removed by etching to result in a gate trench; and then the gate material layers are deposited in the gate trench.

Continuing withFIG.1semiconductor structure100further includes a Multilayer Interconnection (MLI) structure130. MLI structure130is designed and configured to couple various FETs and other devices to form an IC having various logic gates, such as inverters, NAND gates, NOR gates, AND gates, OR gates, flip-flops, or a combination thereof. It is noted that various logic gates each may include multiple FETs and each FET includes a source, a drain and a gate110. Gate110should not be confused with a logic gate. For clarification, sometime, gate110is also referred to as transistor gate.

MLI structure130includes a first metal layer132, a second metal layer134over first metal layer132, and a third metal layer136over second metal layer134. Each metal layer of MLI structure130includes a plurality of metal layer structures (also referred to as metal lines), such as first metal layer structure (“M1”) in first metal layer132, second metal layer structures (“M2”) in second metal layer134, and third metal layer structures (“M3”) in third metal layer136.

In examples, MLI structure130may include more metal layers, such as a fourth metal layer, a fifth metal layer, and so on. In examples, the metal layer structures in each metal layer are oriented in a same direction. For example, first metal layer structures in first metal layer132are oriented in the Y direction, second metal layer structures in second metal layer134are oriented in the X direction, and third metal layer structures in third metal layer136are oriented in the Y direction. The metal layer structures in different metal layers are connected through vertical conductive features (also referred to as vias or via features). The metal layer structures are further coupled to substrate102(such as source and drain (S/D) features) through vertical conductive features. In some examples, the S/D features are connected to the first metal layer structures through contact features (“contact”)116and 0thvia features (“via-0”)142. Furthermore, the first metal layer structures of first metal layer132are connected to the second metal layer structures of second metal layer134through first via features (“via-1”)144; and the second metal layer structures of second metal layer134are connected to the third metal layer structures of third metal layer136through second via features (“via-2”)146. In some example, the third metal layer structures of third metal layer136are connected to fourth metal layer structures of a fourth metal layer through third via features (“via-3”) and the fourth metal layer structures of the fourth metal layer are connected to fifth metal layer structures of a fifth metal layer through fourth via features (“via-4”).

Among those contacts and via features, both contacts116and via-0 features142are conductive features to provide vertical interconnection paths between substrate102and the first metal layer structures of first metal layer132but they are different in terms of composition and formation. In addition, contacts116and via-0 features142may be formed separately. For examples, contacts116are formed by a procedure that includes patterning an Interlayer Dielectric (ILD) layer to form contact holes; depositing to fill in the contact holes to form contacts; and may further include a chemical mechanical polishing (CMP) to remove the deposited metal materials from the ILD layer and planarize the top surface. Via-0 features142are formed by an independent procedure that includes a similar procedure to form contacts116or alternatively a dual damascene process to collectively form via-0 features142and the first metal layer structures of first metal layer132. In some examples, contacts116include a barrier layer and a first metal material layer (not shown); and via-0 features142include a barrier layer and a second metal material layer (not shown). In various examples, the barrier layer includes titanium, titanium nitride, tantalum, tantalum nitride, other suitable material, or a combination thereof. The first metal material layer includes cobalt, the second metal material layer includes ruthenium, cobalt, copper, or a combination thereof.

In one example, the first metal material layer includes cobalt; the second metal material layer includes tungsten; and the barrier layer includes a first barrier film of tantalum nitride and a second barrier film of tantalum film. In another example, via-0 features142are collectively formed with the first metal layer structures of first metal layer132in a dual-damascene process, in which via-0 features142(and the first metal layer structures as well) include the barrier layer and the second metal material layer of copper (or copper aluminum alloy).

In yet another example, via-0 features142include only tungsten. In some other examples where both via-0 features142and the first metal layer structures are formed a dual-damascene process, both via-0 features142and the first metal layer structures include a material layer stack of a titanium nitride film, titanium film, and cobalt; or a material stack of a titanium nitride film, a titanium film, and a ruthenium film; or a material film stack of a tantalum nitride film and a copper film.

In example embodiments, in MLI structure130, the metal layer structures in different layers have different dimensional parameters. For example, the first metal layer structures in first metal layer132have a first thickness T1, the second metal layer structures in second metal layer134have a second thickness T2, and the third metal layer structures in third metal layer136have a third thickness T3. The second thickness T2is greater than the first thickness T1and the third thickness T3. The third thickness T3is greater than the first thickness T1. In some examples, a first thickness ratio T2/T1is in an approximate range of 1.1 and 2. Similarly, a second thickness ratio T2/T3is in an approximate range of 1.1 and 2. In the disclosed structure, those parameters and other subsequently introduced parameters are provided with design values or ranges. The manufactured circuits may experience small variation, such as less than 5% variation. In some embodiments, the first thickness ratio T2/T1and second thickness ratio T2/T3both range approximately between 1.2 and 2. In yet some other embodiments, the first thickness ratio T2/T1and second thickness ratio T2/T3both range approximately between 1.3 and 1.8. The ratios are constrained in those ranges such that to effectively increase the routing efficiency and the chip packing density on one side and decrease the intra-cell coupling capacitance and the power lines resistance on another side.

The pitches and widths of various features are further described below. Gates110have a minimum pitch Pg, the first metal layer structures in first metal layer132have a minimum pitch P1, the second metal layer structures in second metal layer134have a minimum pitch P2, and the third metal layer structures in third metal layer136have a minimum pitch P3. Gates110have a width Wg, the first metal layer structures in first metal layer132have a width W1, the second metal layer structures in second metal layer134have a width W2, and the third metal layer structures in third metal layer136have a width W3. In some examples, W2is greater than both the W1and the W3. For examples, a width ratio of W2/W3(which is equal to W2/W1) is greater than or equal to 1.2.

A pitch of features is defined as the dimension between two adjacent features (measured from same locations, such as center to center, or left edge to left edge). For examples, the gate pitch is the dimension from one gate to an adjacent gate, and the second metal layer structures pitch is the dimension from one to an adjacent one of the second metal layer structures of second metal layer134. Since pitch may not be a constant, the minimum pitch is defined and constrained above in the disclosed structure. Both gates110and the second metal layer structures are oriented in the X direction. The first metal layer structures and the third metal layer structures are oriented in the Y direction.

In example embodiments, interconnection gates114and the second metal layer structures in second metal layer134have a same minimum pitch but different widths. Particularly, the first pitch ratio Pg/P2is 1 but W2usually does not equal to Wg. In some examples, the minimum pitch of gates110is determined when gates110and interconnection gates114are collectively considered. Furthermore, the minimum pitch of the second metal layer structures in second metal layer134is greater than the minimum pitch P3of the third metal layer structures in third metal layer136which in turn in greater than the minimum pitch P1of the first metal layer structures in first metal layer132. For example, a second pitch ration P2/P3is in an approximate range of 1.1-2.0. A third pitch ratio P3/P1is in an approximate range of 1.1-2.0. In some examples, each of the Pgand the P2are in an approximate range of 36 nm-52 nm, the P1is in an approximate range of 20 nm-28 nm, and the P3are in an approximate range of 25 nm-35 nm.

By utilizing the disclosed structure, the second metal layer structures have a large thickness and large minimum pitch. Thus, the aspect ratio of the second metal layer structures is reduced by the increased minimum pitch and the thickness of the second layer metal structures. In examples, the power lines (such as Vddand Vss) are routed in the second metal layer structures, taking the advantages of the greater dimensions and less resistance of the second metal layer structures. The power line routing includes horizontal routing of the power lines being substantially distributed in the second metal layer structures.

In addition, because the second metal layer structures has greater thickness than the first metal layer structures and the third metal layer structures, the second metal layer structures have low resistance and therefore provide design freedom and performance improvement (for example, IR drop reduction). The first metal layer structures and the third metal layer structures with lower thickness and denser pitch provides routing efficiency improvement.

Moreover, the second metal layer structures have a larger minimum metal pitch than the first metal layer structures and the third metal layer structures creating a sandwich metal pitches design (narrow (M1)-wide (M2)-narrow (M3)) provides additional via design features. For example, it enables the vias to be square, slot, or larger. In addition, this also reduces RC (contact resistance) of the vias and provides extra space for via-2146layout optimization (either larger slot via or single patterning opportunity from double patterning).

In some examples, semiconductor structure100cam include a fourth metal layer having fourth metal layer structures, a fifth metal layer having fifth metal layer structures, a sixth metal layer having sixth metal layer structures. Moreover, semiconductor structure100can include third via features (via-3) connecting the third metal layer structures with the fourth metal layer structures, fourth via features (via-4) connecting the fourth metal layer structures with the fifth metal layer structures, and fifth via features (via-5) connecting the fifth metal layer structures with the sixth metal layer structures.

FIG.2Ais a first layout of an example semiconductor device200in accordance with some embodiments.FIG.2Bis a cross-sectional view of line A-A′ of semiconductor device200ofFIG.2A.FIG.2Cis a cross-sectional view of line B-B′ of semiconductor device200ofFIG.2A.FIG.2Dis a cross-sectional view of line C-C′ of semiconductor device200ofFIG.2A. In some examples, semiconductor device200is an FinFET invertor. The invertor includes a N-type metal oxide semiconductor (NMOS) FET and a P-type metal oxide semiconductor (PMOS) FET. In some examples, semiconductor device200can include complementary metal oxide semiconductor (CMOS) FETs, or a combination thereof. In some alternative examples, semiconductor device200may include 2D-FinFET, 3D-FinFET, or a combination thereof.

Semiconductor device200is one embodiment of semiconductor structure100. Various metal layer structures and gates are oriented, configured, and designed with dimensions as described in semiconductor structure100. For example, the thickness of second metal layer structures is greater than the thickness of the third metal layer structures which in turn are greater than the thickness of the first metal layer structures. Similarly, the pitch of the second metal layer structures is greater than the pitch of the third metal layer structures which in turn are greater than the pitch of the first metal layer structures.

Referring toFIGS.2A-2D, semiconductor device200includes a plurality of gate structures (that is, a first gate structure202a, a second gate structure202b, and a third gate structure202c(collectively referred to as gate structures202)), a plurality of first metal layer structures (that is, a first first metal layer structure204a, a second first metal layer structure204b, a third first metal layer structure204c, a fourth first metal layer structure204d, and a fifth first metal layer structure204e(collectively referred to as first metal layer structures204)), a plurality of second metal layer structures (that is, a first second metal layer structure206aand a second second metal layer structure206b(collectively referred to as second metal layer structures206)), a plurality of third metal layer structures (that is, a first third metal layer structure208a, a second third metal layer structure208b, a third third metal layer structure208c, a fourth third metal layer structure208d, a fifth third metal layer structure208e, and a sixth third metal layer structure208f(collectively referred to as third metal layer structures208), a gate electrode210, a plurality of fins (that is, a first fin212a, a second fin212b, a third fin212c, and a fourth fin212d(collectively referred to as fins212), a gate via214, a plurality of via-0s (that is, a first via-0216a(also referred to as source via v0-vss216a), a second via-0216b(also referred to as drain via v0-vdd216b), and a third via-0216c), a plurality of via-1s (that is, a first via-1218aand a second via-1218b), and a plurality of contact structures (that is, a first contact structure220a, a second contact structure220b, and a third contact structure220c(collectively referred to as contact structures220). The plurality of fins are also referred to as Oxide Diffusion (OD).

Referring toFIGS.2A-2Dsemiconductor device200further includes a substrate222, a plurality of well regions (that is, a first well region224a, a second well region224b, a third well region224c, and a fourth well region224b(collectively referred to as well regions224), an isolation structure228, a plurality of S/D structures (that is, a first S/D structure230a, a second S/D structure230b, a third S/D structure230c, and a fourth S/D structure230d(collectively referred to as S/D structures230)), a first dielectric layer232, a second dielectric layer234, a gate dielectric layer238, a first work-function metal240a, a second work-function metal240b, a first gate end dielectric242a, a second gate end dielectric242b, and a gate top dielectric244.

In examples, substrate222may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. Substrate222may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some examples, the semiconductor material of the substrate222may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. In some other examples, substrate222includes bulk-Si, SiP, SiGe, SiC, SiPC, Ge, SOI-Si, SOI-SiGe, III-V material, or a combination thereof.

In addition, well regions224are formed on substrate222. In some examples, first well region224aand third well region224cinclude p-type substrate and second well region224band fourth well region224dinclude a n-type substrate. For example, first well region224aand third well region224cmay be doped with p-type dopants, such as phosphorus or arsenic. Second well region224band fourth well region224dcan be doped with n-type dopants, such as boron or BF2. The fabrication includes performing one or more doping processes, such as implantation processes to form well regions224in substrate222. In some examples, a conductive type of well regions224is different from a conductive type of substrate224, while the conductive type of well regions224is the same as a conductive type of fins212.

In examples, fins212(also referred to channels212) are formed on well regions224. For example, first fin212aand second fin212bare formed on first well region224aand third fin212cand fourth fin212dare formed on second well region224b. In examples, fins212are semiconductor strips extending along a second direction Y. In some examples, fins212may be formed on substrate222by etching trenches in substrate222. The etching may be any acceptable etching process, such as a reactive ion etching (RIE) process, neutral beam etching (NBE) process, the like, or a combination thereof. In other examples, the etching process may be an anisotropic process. In the case, as shown inFIGS.2D, fins212protrude from a top surface of well regions224. In some examples, first fin212aand second fin212bincludes silicon channels and third fin212cand fourth fin212dinclude silicon channel or silicon-germanium channel. InFIGS.2A-2D, four fins are illustrated, but the disclosure is not limited thereto. In some examples, fins212include at least three semiconductor fins, such as three, four, five, six, or more semiconductor fins.

Isolation structure228is disposed over well regions224, In examples, isolation structure228may be an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), the like, or a combination thereof, and may be formed by depositing an insulation material in an acceptable deposition process, such as a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD), or the like; planarizing the insulation material in an acceptable planarization process, such as a chemical mechanical polish (CMP), an etch back process, or the like; and recessing the insulation material in an acceptable etching process, such as a dry etching, a wet etching, or a combination thereof. In the case, fins212protrude from isolation structure228. That is, top surfaces of isolation structure228are lower than top surfaces of fins212. Further, the top surfaces of isolation structure228may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. In some examples, isolation structure228may be a Shallow Trench Isolation (STI) structure.

Gate structures are disposed across fins212and extends along the X direction. In some examples, the Y direction and the X direction are different. For example, the Y direction is perpendicular or orthogonal to the X direction. In detail, as shown inFIGS.2A-2D, one of the gate structures includes gate dielectric layer238and gate electrode210(that is, first work-function metal240aand second work-function metal240b) over gate dielectric layer238. Gate dielectric layer238conformally covers surfaces of plurality of fins212exposed by isolation structures228. In examples, gate dielectric layer238may be a high-k dielectric material having a k value greater than about 7, and may include a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, or a combination thereof. The formation methods of gate dielectric layer238may include Molecular-Beam Deposition (MBD), ALD, PECVD, or the like. In other examples, gate dielectric layer238may include SiON, Ta2O5, Al2O3, nitrogen-containing oxide layer, nitrided oxide, metal oxide dielectric material, Hf-containing oxide, Ta-containing oxide, Ti-containing oxide, Zr-containing oxide, Al-containing oxide, La-containing oxide, high k material (k>5) or a combination thereof. In some examples, gate dielectric layer238may include polysilicon, a metal-containing material, such as TiN, TaN, TaC, Co, Ru, Al, a combination thereof, or multi-layers thereof. Although a single gate electrode238is shown, any number of work function tuning layers may be disposed between gate dielectric layer238and the gate electrode. For example, the gate structure may include a multiple material structure selected from a group consisting of polysilicon/SiON structure, metals/high-k dielectric structure, Al/refractory metals/high-k dielectric structure, silicide/high-k dielectric structure, or a combination thereof, from top to bottom.

Further, gate end dielectrics242aand242b(also referred to as spacers) are disposed along sidewalls of the gate structures. Gate end dielectrics242a,242bmay be formed by conformally depositing a dielectric material and subsequently anisotropically etching the dielectric material. The dielectric material of gate end dielectrics242a,242bmay include silicon oxide, silicon nitride, silicon oxynitride, SiCN, the like, or a combination thereof. The formation methods of gate end dielectrics242a,242bmay include forming dielectric material by a deposition such as ALD, PECVD, or the like, and then performing an etch such as an anisotropic etching process.

First S/D structure230a, second S/D structure230b, third S/D structure230c, and fourth S/D structure230d(collectively referred to as S/D structures230) are disposed directly over well regions224. In some examples, S/D structures230may be epitaxial structures formed by growing epitaxial layers over exposed surfaces of well regions224. Growing the epitaxy layers on exposed surfaces of well regions224may include performing a pre-clean process to remove the native oxide on the surface of well regions224. Next, an epitaxy process is performed to grow the epitaxial S/D structures230on the surfaces of well regions224. In examples, second S/D structure230bmay be epitaxial structures including SiGe, SiGeC, Ge, Si, or a combination thereof for the PMOS FET. In other examples, first S/D structure230amay be epitaxial structures including SiP, SiC, SiPC, Si, or a combination thereof for the NMOS FET. In some examples, S/D structures230may have facets or may have irregular shapes. The SEG process may use any suitable epitaxial growth method such as, vapor phase epitaxy (VPE), metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), and liquid phase epitaxy (LPE). In some examples, S/D structures230may be implanted with dopants using patterned photoresist masks. In some examples, S/D structures230may be in situ doped during epitaxial growth.

First contact220a, second contact220b, and third contact220c(collectively referred to as contacts220) are disposed over S/D structures230and physically and electrically coupled to S/D structures230. In some examples, first contact220ais formed over first S/D structure230a, second contact220bis formed over second S/D structure230b, and third contact220cis formed over both third S/D structure230cand fourth S/D structure230d. Thus, third contact230cis a longer contact than both first contact220aand second contact220b. In some examples, contacts220are formed in first dielectric layer232between adjacent two gate structures202. For example, first contact220aand second contact220bare formed between second gate structure202band third gate structure202cand third contact220cis formed between first gate structure202aand second gate structure202b. In some examples, contact structures220includes a liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material. The liner may include Ti, TiN, Ta, TaN, the like, or a combination thereof. The conductive material may be Ti, TiN, TaN, Co, Ru, Pt, W, Al, Cu, or a combination thereof. Contact structures220may be formed by an electro-chemical plating process, CVD, PVD or the like. The formation of contact structures220may include the following steps. First dielectric layer232is patterned to form contact trenches (not shown) through a photolithography process and an etching process such as anisotropic process. The conductive material is formed on first dielectric layer232and filled in the contact trenches. The conductive material is then planarized in an acceptable planarization process, such as a chemical mechanical polish (CMP), an etch back process, or the like to remove the conductive material over first dielectric layer232. Therefore, in some examples, contact structures220(including first contact structure220a, second contact structure220b, and third contact structure230c) may be substantially at a same level.

In examples, each of contact structures220is a rectangular contact having a long side and a short side. The long side of contact structures220extends in a same direction as second metal layer structures206. In some examples, a ratio of the long side to the short side is greater than 2. In the cross-sectional views ofFIGS.2B and2C, each of contact structures220is a slot shape or a trapezoidal shape. That is, a top area of each of contact structures220is greater than a bottom area of each of contact structures220. In some examples, a plurality of silicide layers (not shown) may be formed respectively between contact structures220and S/D structures230to reduce a resistance between contact structures220and S/D structures230. The silicide layer may include TiSi2, NiSi, PtSi, CoSi2, or combination thereof.

First dielectric layer232(also referred to as an Interlayer Dielectric (ILD) layer) is disposed along contact structures220and S/D structures230. In some examples, first dielectric layer232may be formed after source via V0-Vss216a, drain via V0-Vdd216b, third via V0216c, and gate via214are formed. First dielectric layer232may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), borosilicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), the like, or a combination thereof. In some examples, first dielectric layer232may include a single layer dielectric material or a multi-layer dielectric material.

Second dielectric layer234(also referred to as an Inter-Metal dielectric (IMD) layer) is formed over first dielectric layer232. Second dielectric layer234may include a single layer dielectric material or a multi-layer dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), borosilicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), the like, or a combination thereof. In some examples, first dielectric layer232and second dielectric layer234may have a same material or different materials. In some examples, gate top dielectric244may include multiple dielectric material. For example, gate top dielectric244can include one or more of SiO2, Si3N4, carbon doped oxide, nitrogen doped oxide, porous oxide, air gap, or combination.

First metal layer structures204, second metal layer structures206, and third metal layer structures208are disposed in second dielectric layer234. In detail, as shown inFIG.1, first metal layer structures204and third metal layer structures208extend along the Y direction and second metal layer structures206extend along the X direction. In some examples, first metal layer structures204are referred to as metal one (M1), second metal layer structures206are referred to as metal two (M2), and third metal layer structures208are referred to as metal three (M3). That is, each of first metal layer structures204, second metal layer structures206, and third metal layer structures208are at a different level.

Herein, when elements are described as “at substantially the same level”, the elements are formed at substantially the same height in the same layer, or having the same positions embedded by the same layer. In some examples, the elements at substantially the same level are formed from the same material(s) with the same process step(s). In some other examples, the tops of the elements at substantially the same level are substantially coplanar.

In examples, each of first metal layer structures204, second metal layer structures206, and third metal layer structures208may include a metal material, such as aluminum, copper, nickel, gold, silver, tungsten, or a combination thereof and formed by an electro-chemical plating process, CVD, PVD or the like. In some examples, first metal layer structures204, second metal layer structures206, and third metal layer structures208are formed before second dielectric layer234is formed. First metal layer structures204, second metal layer structures206, and third metal layer structure208may be formed by forming a metal material on first dielectric layer232, and patterning the metal material by a photolithography process and an etching process such as anisotropic process. In other examples, first metal layer structures204, second metal layer structures206, and third metal layer structures208are formed after second dielectric layer234is formed.

First metal layer structures204, second metal layer structures206, and third metal layer structures208may be formed by the following processes. Second dielectric layer234is patterned by a photolithography process and an etching process such as anisotropic process to form metal trenches in second dielectric layer234. A metal material is then formed on second dielectric layer234and filled in the metal trenches. The metal material is then planarized in an acceptable planarization process, such as a chemical mechanical polish (CMP), an etch back process, or the like to remove the metal material over second dielectric layer234.

Each of source via v0-vss216a, drain via v0-vdd216b, and third via V0216care formed in first dielectric layer232. Source via v0-vss216ais disposed between and electrically connects first first metal layer structure204aand first contact220arespectively. Drain via v0-vdd216bis disposed between and electrically connects fifth first metal layer structure204eand second contact220b. Thus, each of source via v0-vss216a, drain via v0-vdd216b, and third via V0216cland directly on corresponding contacts. In examples, source via v0-vss216aand drain via v0-vdd216bhave a larger size than third via V0216c. For example, a ratio of a top area of source via v0-vss216a, drain via v0-vdd216bto a top area of third via V0216cis within an approximate range of 1.2-4.0.

In some examples, each of source via v0-vss216a, drain via v0-vdd216b, and third via V0216cmay include a liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material. The liner may include Ti, TiN, Ta, TaN, the like, or a combination thereof. The conductive material may be Ti, TiN, TaN, Co, Ru, Pt, W, Al, Cu, or a combination thereof. In some examples, source via v0-vss216a, drain via v0-vdd216b, and third via V0216cmay be formed by an electro-chemical plating process, CVD, PVD or the like. The formation of source via v0-vss216a, drain via v0-vdd216b, and third via V0216cmay include the following steps. First dielectric layer232is patterned to form via openings (not shown) through a photolithography process and an etching process such as anisotropic process. The conductive material is filled in the via openings and on first dielectric layer232. The conductive material is then planarized in an acceptable planarization process, such as a chemical mechanical polish (CMP), an etch back process, or the like to remove the conductive material over first dielectric layer232. Therefore, in some examples, source via v0-vss216a, drain via v0-vdd216b, and third via V0216cmay be substantially at a same level.

Gate via214is formed in first dielectric layer232. Gate via214is disposed between and electrically connects third first metal layer structure204cand first work-function metal240aand second work-function metal240b. Although only one gate via214is illustrated inFIG.2A-2D, the number of gate via214is not limited thereto. In general, gate via214are disposed between the gate structures and the first metal layer structures204, which means the number of gate via214is able be adjusted by the number of the gate structures. In examples, gate via214includes a liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material. The liner may include Ti, TiN, Ta, TaN, the like, or a combination thereof. The conductive material may be Ti, TiN, TaN, Co, Ru, Pt, W, Al, Cu, or a combination thereof. Gate via214may be formed by an electro-chemical plating process, CVD, PVD or the like.

First first metal layer structure204aand second second metal layer structure206bare used as Vss conductors and fifth first metal layer structure204eis used as Vdd conductor. First first metal layer structure204ais connected to second second metal layer structure206bthrough first via218a. Shorter contacts connect source nodes of the NMOSFET and the PMOSFET. For example, first contact220aconnects to the source node of the NMOSFET and second contact220bconnects to the source node of the PMOSFET. The source node of the NMOSFET eventually connects to the VSS conductor and the source node of the PMOSFET eventually connects to the VDD conductor. Longer contact (that is, third contact220cconnects drain nodes of the NMOSFET and the PMOSFET. The drain nodes of the NMOSFET and the PMOSFET connect to first second metal layer structure206a.

FIG.3Ais a second layout of an example semiconductor device300in accordance with some embodiments.FIG.3Bis a cross-sectional view of line D-D′ of semiconductor device300ofFIG.3A.FIG.3Cis a cross-sectional view of line E-E′ of semiconductor device300ofFIG.3A.FIG.3Dis a cross-sectional view of line F-F′ of semiconductor device300ofFIG.3A. In some examples, semiconductor device300is a GAA invertor.

Semiconductor device300is one embodiment of semiconductor structure100. Various metal layer structures and gates are oriented, configured, and designed with dimensions as described in semiconductor structure100. For example, the thickness of second metal layer structures is greater than the thickness of the third metal layer structures which in turn are greater than the thickness of the first metal layer structures. Similarly, the pitch of the second metal layer structures is greater than the pitch of the third metal layer structures which in turn are greater than the pitch of the first metal layer structures.

FIGS.3A-3Dfollow a similar numbering scheme to that ofFIGS.2A-2D. Though corresponding, some components also differ. To help identify components which correspond but nevertheless have differences, the numbering convention uses 3-series numbers forFIGS.3A-3DwhileFIGS.2A-2Duses 2-series numbers. For brevity, the discussion will focus more on differences betweenFIGS.3A-3DandFIGS.2A-2Dthan on similarities.

For example, semiconductor device300includes first channels312aand second channel312bfor the NMOSFET and PMOSFET respectively. Each of first channels312aand second channels312bmay include multiple sheets, for example, between 2-6, preferably 3. First channels312amay be Si channels while second channels312bmay be either Si channels or SiGe channels. The channels are surrounded by a layer of gate dielectric238.

In examples, a thickness of first channels312ais represented as T4 and a width of first channels312ais represented by W4. A distance between two consecutive sheets (also referred to as spacer thickness) of first channels312ais represented as S1. A thickness of second channels312bis represented as T5 and a width of second channels312bis represented by W5. A distance between two consecutive sheets of second channels312bis represented as S2. In examples, length of each of channels of first channels312aand second channels312bis within an approximate range of 6 nm-20 nm. In some examples, a width of each of channels of first channels312aand second channels312bis within an approximate range of 4 nm-70 nm. In other examples, the distance between two consecutive sheets for each of first channels312aand second channels312bis within an approximate range of 4 nm-12 nm.

In examples, an effective dielectric constant of an inner spacer has higher K (dielectric constant) value than a top spacer. The material of the inner spacer is selected from of SiO2, Si3N4, SiON, SiOC, SiOCN base dielectric material, air gap, or combination. The top spacer includes multiple dielectric material and selected from SiO2, Si3N4, carbon doped oxide, nitrogen doped oxide, porous oxide, air gap, or combination. The channel region of the vertically stacked multiple channels transistors have a vertical sheet pitch (P=T+S) and is within an approximate range of 10-23 nm. The channel thickness (T) is in an approximate range of 4-8 nm. The vertical sheet pitch is defined by a first channel space(S) and the first channel space(S) is in an approximate range of 6-15 nm.

FIG.4is a top view of an example cell array400constructed in accordance with some embodiments. Various metal lines and gates of cell array400are oriented, configured and designed with dimension as described in semiconductor structure100. For example, the thickness of the second metal layer structures is greater than the thickness of the third metal layer structures which in turn are greater than the thickness of the first metal layer structures. Similarly, the pitch of the second metal layer structures is greater than the pitch of the third metal layer structures which in turn are greater than the pitch of the first metal layer structures.

Cell array400includes multiple rows for cells, for example, a first row402a, a second row402b, a third row402c, and a fourth row402d(collectively referred to as rows402). Each of rows402includes multiple cells. For example, first row402aincludes a cell1-1, a cell1-2, a cell1-3, and a cell1-4. Similarly, second row402bincludes a cell2-1, a cell2-2, a cell2-3, a cell2-4, and a cell2-5. Moreover, third row402cincludes a cell3-1, a cell3-2, a cell3-3, a filler cell, and a cell3-4. In addition, fourth row402dincludes a cell4-1, a cell4-2, a cell4-3, a filler cell, a cell4-4, and cell4-5. Each cell of cell array400is separated from each other by an isolations structure404. Each cell in a row may have a same cell height “H1”.

Particularly, cell array400further includes two N-wells410with a P-well408interposed between. Various pFETs are formed in the N-wells410and various nFETs are formed in the P-well408. Those PMOSFETs and NMOSFETs are configured and connected to form various cells in cell array400. Those cells are configured in an abutment mode. With such a configuration, the standard cells can be arranged more efficiently with high packing density.

FIGS.5A and5Bare schematic views of a Static Random Access Memory (SRAM) cell500in accordance with some embodiments. In examples, various metal lines and gates of SRAM cell500are oriented, configured and designed with dimension as described in semiconductor structures100,200, and300. For example, the thickness of the second metal layer structures is greater than the thickness of the third metal layer structures which in turn are greater than the thickness of the first metal layer structures. Similarly, the pitch of the second metal layer structures is greater than the pitch of the third metal layer structures which in turn are greater than the pitch of the first metal layer structures.

As shown inFIG.5, SRAM cell500includes a cross-coupled inverters502. Cross couped inverters502includes a first inverter502aand a second inverter502b. First inverter502aand second inverter502bare cross coupled to each other at a first node Q and a second node QB. For example, an output of first inverter502ais connected to an input of second inverter502bat the first node Q, and an output of second inverter502bis connected to an input of first inverter502aat the second node QB. The first node Q is complementary to the second node QB, and each of the first node Q is complementary to the second node QB are operative to store one bit of data. SRAM cell500further includes a first pass gate transistor PG1 coupled to the output of first inverter502aand the input of second inverter502b, and a second pass gate transistor PG2 coupled to the output of second inverter502band the input of first inverter502a. Gate electrodes of the first and second pass-gate transistors PG1 and PG2 are coupled to a wordline WL, a source region of the first pass-gate transistor PG1 is coupled to a bitline BL, and a source region of the second pass-gate transistor PG2 is coupled to a complementary bitline BLB, which is the complement of the bitline BL. The data stored at the first node Q accessible through the bitline BL and the first pass gate transistor PG1. The data stored at the second node QB is accessible through the complementary bitline BLB and the second pass gate transistor PG2.

First inverter502aincludes a first pull-up transistor PU1 and a first pull-down transistor PD1. Second inverter502bincludes a second pull-up transistor PU2 and a second pull-down transistor PD2. A pull-up transistor is a P-type transistor of which source/drain is connected to a first voltage potential and a pull-down transistor is an N-type transistor of which source/drain is connected to a second power supply voltage lower than the first voltage potential. For example, source regions of the first and second pull-up transistors PU1 and PU2 are connected to a voltage potential Vdd and source regions of the first and second pull-down transistors PD1 and PD2 are connected to another voltage potential Vss lower than Vdd provided by the power supply circuit. Drain regions of the first pull-up transistor PU1, the first pull-down transistor PD1, and the first pass-gate transistor PG1, and gate electrodes of the second pull-up transistor PU2 and the second pull-down transistor PD2, are connected by the first node Q. Drain regions of the second pull-up transistor PU2, the second pull-down transistor PD2, and the second pass-gate transistor PG2, and gate electrodes of the first pull-up transistor PU1 and the first pull-down transistor PD1, are connected by second node QB. Such features will be more apparent with reference toFIG.6which will be described later.

FIG.6is an example layout600of SRAM cell500in accordance with some embodiments. In examples, various metal lines and gates of SRAM cell500are oriented, configured and designed with dimension as described in semiconductor structures100,200, and300. For example, the thickness of the second metal layer structures is greater than the thickness of the third metal layer structures which in turn are greater than the thickness of the first metal layer structures. Similarly, the pitch of the second metal layer structures is greater than the pitch of the third metal layer structures which in turn are greater than the pitch of the first metal layer structures.

As shown inFIG.6, layout600includes two P-well regions602a1and602a2with a N-well region602binterposed between. The first and second pull-up transistors PU1 and PU2 are formed in N-well region602b. The first pull-down transistor PD1 and the first gate transistor PG1 are formed in first P-well region602a1. The second pull-down transistor PD2 and the second gate transistor PG2 are formed in second P-well region602a2.

Layout600includes multiple first metal layer structures604a-604g, multiple second metal layer structures606a-606c, multiple third metal layer structures608a-608b, multiple gate electrodes610a-610d, multiple oxide diffusion structures612a-612f, multiple gate vias614a-614b, multiple via-0's616a-616f, multiple via-1's618a-618d, multiple contact structures620a-620h, multiple butt-contact structures622a-622b, and multiple via-2's624a-624b.

In examples, in layout600, first metal layer structures604a-604gare used as bit lines, a VDD conductor, and as landing pads. For example, and as shown in layout600, a third first metal layer structure604cis used as a bit line BL and fifth first metal layer structure604eis used as a complimentary bit line BLB. In addition, fourth first metal layer structure604dis used as a VDD conductor. Remaining of first metal layers structures, that is, first first metal layer structure604a, second first metal layer structure604b, sixth first metal layer structure604f, and seventh first metal layer structure604gare used as landing pads.

In examples, in layout600, second metal layer structures606a-606care used as a word line and VSS landing pads. For example, and as shown in layout600, a second second metal layer structure606bis used as a word line WL and remaining of second metal layers structures, that is, first second metal layer structure606aand third second metal layer structure606care used as VSS landing pads.

Moreover, in layout600, third metal layer structures608a-606bare used as a VSS conductors. For example, and as shown in layout600, both a first third metal layer structure608aand second third metal layers structures608bare used as VSS conductors. In addition, fourth metal layer structures (not shown) can be used for an additional word line WL and VSS power mesh layers.

FIG.7is a second layout700of a SRAM cell in accordance with some embodiments. Layout700is one embodiment of semiconductor structure100. Various metal layer structures and gates are oriented, configured, and designed with dimensions as described in semiconductor structure100. For example, the thickness of second metal layer structures is greater than the thickness of the third metal layer structures which in turn are greater than the thickness of the first metal layer structures. Similarly, the pitch of the second metal layer structures is greater than the pitch of the third metal layer structures which in turn are greater than the pitch of the first metal layer structures.

FIG.7follows a similar numbering scheme to that ofFIG.6. Though corresponding, some components also differ. To help identify components which correspond but nevertheless have differences, the numbering convention uses 7-series numbers forFIG.7. For brevity, the discussion will focus more on differences betweenFIG.7andFIG.6than on similarities.

For example, semiconductor device700ofFIG.7includes a fourth metal layer structure702(also referred to a metal line four (M4)). Fourth metal layer structure702is used as a second word line WL2 for the SRAM cell. In examples, fourth metal layer structure702can include TiN, TaN, TiAl, TiAlN, TaAl, TaAlN, TaAlC, TaCN, WNC, Co, Ni, Pt, W, or a combination.

FIG.8is a cross-sectional view of line G-G′ of the SRAM cell ofFIG.7in accordance with some embodiments. As shown inFIG.8, fourth metal layer structure702is connected to third third metal layer structure608cthrough a via-3804. Third third metal layer structure608cin turn is connected to second second metal layer structure606b(which is used as a first word line WL1 for the SRAM cell) through a via-2624c.

In some example, a shape of a top layer of each of first via-0616aand sixth via-0616fis oval have a first diameter D1 and a second diameter D2. The first diameter D1 is longer than the second diameter D2. A ratio of D1/D2 is in an approximate range of 1.5-4.0.

FIG.9Ais a schematic view of an inverter902in accordance with some embodiments.FIG.9Bis a schematic view of a NAND gate904in accordance with some embodiments.FIG.9Cis a schematic view of a NOR gate906in accordance with some embodiments. As noted above, those gates, contact features, via features and metal lines are configured with dimensions, pitches, and width as described in semiconductor structure100ofFIG.1. Those contact features, via features and metal layer structures are routed to connect various gates, sources and drains to form various logic gates that include an inverter902, a NAND gate904, and a NOR gate906. In examples, inverter902includes one NMOSFET and one PMOSFET (labeled as “NMOSFET” and “PMOSFET” respectively, inFIG.9A). NAND gate904includes two NMOSFETs and two PMOSFETs (labeled as “NMOFET1”, “NMOSFET2”, “PMOSTET1”, and “PMOSFET2”, respectively, inFIG.9B). NOR gate906includes two NMOSFETs and two PMOSFETs (labeled as “NMOSFET1”, “NMOSFET2”, “PMOSFET1”, and “PMOSFET2”, respectively, inFIG.9C). Those NMOSFETs and PMOSFETs are connected as illustrated inFIG.9A-9Cto form inverter902, NAND gate904, and NOR gate906, respectively. Furthermore, each of NAND gate904and NOR gate906includes a common drain and a common active region (“common OD”). High and low power lines are referred to as “Vdd” and “Vss”, respectively, inFIGS.9A-9C.

In various embodiments, the standard cells include logic gates, such as an inverter, an NAND logic gate, NOR logic gate. However, the standard cells are not limited to those and may include other standard cells. Those standard cells may be further configured and connected to form another standard cell with a circuit with a different function. For example, a standard cell may be a flip-flop device.FIGS.10A and10Billustrates schematic views of two flip-flop devices according two embodiments. First flip-flop device1002is formed by two NOR logic gates cross-coupled together according to one embodiment. Second flip-flop device1004is formed by two NAND logic gates cross-coupled together according to another embodiment.

In accordance with example embodiments, a semiconductor device comprises: a plurality of gate structures, wherein each gate structure of the plurality of gate structures is arranged to be a gate terminal of a transistor; a plurality of first metal layer structures formed above the plurality of gate structures, wherein each of the plurality of first metal layer structures and one of the plurality of gate structures are crisscrossed from a top view, and wherein each of the plurality of first metal layer structures have a first thickness; a plurality of second metal layer structures formed above the plurality of first metal layer structures, wherein each of the plurality of second metal layer structures and one of the plurality of first metal layer structures are crisscrossed from the top view, and wherein each of the plurality of second metal layer structures have a second thickness; and a plurality of third metal layer structures formed above the plurality of second metal layer structures, wherein each of the plurality of third metal layer structures and one of the plurality of second metal layer structures are crisscrossed from the top view, wherein each of the plurality of third metal layer structures have a third thickness, and wherein the second thickness is greater than both the first thickness and the third thickness.

In example embodiments, a semiconductor device comprises: a substrate having a first region and a second region; a first active region disposed in the first region of the substrate; a second active region disposed in the second region of the substrate; a first gate stack disposed over the first active region and a second gate stack disposed over the second active region, wherein the first gate stack and the second gate stack have elongated shapes oriented in a first direction; a first metal layer disposed over the first gate stack and the second gate stack, wherein the first metal layer comprises a plurality of first metal layer structures oriented in a second direction, the second direction being orthogonal to the first direction; a second metal layer disposed over the first metal layer, wherein the second metal layer comprises a plurality of second metal layer structures oriented in the first direction; and a third metal layer disposed over the second metal layer, wherein the third metal layer comprises a plurality of third metal layer structures oriented in the second direction, wherein: the plurality of first metal layer structures have a first minimum pitch P1, the plurality of second metal layer structures have a second minimum pitch P2, the plurality of third metal layer structures have a third minimum pitch P3, and the second minimum pitch P2 is greater than both the first minimum pitch P1 and the third minimum pitch P3.

In accordance with example embodiments, a semiconductor device comprises: a substrate; a first active region and a second active region over the substrate and oriented lengthwise generally along a first direction; a gate electrode over the substrate and oriented lengthwise generally along a second direction perpendicular to the first direction, wherein the first gate electrode engages the first active region to form a first transistor and engages the second active region to form a second transistor; a first source contact oriented lengthwise generally along the second direction, the first source contact directly contacting a source feature of the first transistor; a second source contact oriented lengthwise generally along the second direction, the second source contact directly contacting a source feature of the second transistor; and a drain contact oriented lengthwise generally along the second direction, the drain contact directly contacting both a drain feature of the first transistor and a drain feature of the second transistor.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.