Patent ID: 12210451

DETAILED DESCRIPTION

Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. Throughout the specification, reference to “an embodiment,” “another embodiment” or the like is not necessarily to only one embodiment, and different references to any such phrase are not necessarily to the same embodiment(s). The term “embodiments” when used herein does not necessarily refer to all embodiments.

Various embodiments of the present disclosure are described below in more detail with reference to the accompanying drawings. However, the present disclosure may be embodied in different forms and variations, and should not be construed as being limited to the embodiments set forth herein. Rather, the described embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the present invention to those skilled in the art to which this disclosure pertains. Throughout this disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present disclosure.

The methods, processes, and/or operations described herein may be performed by code or instructions to be executed by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device may be those described herein or one in addition to the elements described herein. Because the algorithms that form the basis of the methods (or operations of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments may transform the computer, processor, controller, or other signal processing device into a special-purpose processor for performing the methods herein.

When implemented at least partially in software, the controllers, processors, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, generators and other signal generating and signal processing features may include, for example, computer-readable media (such as a memory or other storage device) for storing code or instructions to be executed, for example, by a computer, processor, microprocessor, controller, or other signal processing device.

FIG.1is a diagram illustrating the schematic configuration of a memory system100based on an embodiment of the present disclosure.

In some implementations, the memory system100may include a memory device110configured to store data, and a memory controller120configured to control the memory device110.

The memory device110may include multiple memory blocks each including a plurality of memory cells for storing data. The memory device110may be configured to operate in response to control signals received from the memory controller120. Operations of the memory device110may include, for example, a read operation, a program operation (also referred to as a “write operation”), an erasure operation, and the like.

The memory cells in the memory device110are used to store data and may be arranged in a memory cell array. The memory cell array may be divided into memory blocks of memory cells and each block includes different pages of memory cells. In typical implementations of NAND flash memory devices, a page of memory cells is the smallest memory unit that can be programmed or written, and the data stored in memory cells can be erased at the block level.

In some implementations, the memory device110may be implemented as various types, such as a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate4 (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, a low power DDR (LPDDR), a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase-change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), or a spin transfer torque random access memory (STT-RAM).

The memory device110may be implemented in a three-dimensional array structure. Some embodiments of the present disclosure are applicable to any type of flash memory devices having an electric charge storage layer. In an implementation, the electric charge storage layer may be formed of a conductive material, and such an electric charge storage layer can be called a floating gate. In another implementation, the electric charge storage layer may be formed of an insulating material, and such a flash memory device can be called a charge trap flash (CTF).

The memory device110may be configured to receive a command and an address from the memory controller120to access an area of the memory cell array selected using the address. That is, the memory device110may perform an operation corresponding to the received command on a memory area of the memory device having a physical address corresponding to the received address from the memory controller120.

In some implementations, the memory device110may perform a program operation, a read operation, an erasure operation, and the like. During the program operation, the memory device110may write data in the area selected by the address. During the read operation, the memory device110may read data from a memory area selected by the address. During the erasure operation, the memory device110may erase data stored in a memory area selected by the address.

The memory controller120may control write (program), read, erasure, and background operations that are performed on the memory device110. The background operation may include, for example, operations that are implemented to optimize the overall performance of the memory device110, such as a garbage collection (GC) operation, a wear leveling (WL) operation, and a bad block management (BBM) operation.

The memory controller120may control the operation of the memory device110at the request of a host. In addition, the memory controller120may control the operation of the memory device110even in the absence of a request from the host, such as when the memory controller120performs background operations of the memory device.

The memory controller120and the host may be separate devices. In some implementations, the memory controller120and the host may be integrated and implemented as a single device. In the examples included in the following description, the memory controller120and the host will be discussed as separate devices, but embodiments are not limited thereto.

Referring toFIG.1, the memory controller120may include a memory interface (memory I/F)122, a control circuit123, and a host interface (host I/F)121.

The host interface121may be configured to provide an interface for communication with the host.

When receiving a command from the host HOST, the control circuit123may receive the command through the host interface121and may perform an operation of processing the received command.

The memory interface122may be directly or indirectly connected to the memory device110to provide an interface for communication with the memory device110. That is, the memory interface122may be configured to provide the memory device110and the memory controller120with an interface for the memory controller120to perform memory operations on the memory device110based on control signals and instructions from the control circuit123.

The control circuit123may be configured to control the operation of the memory device110through the memory controller120. For example, the control circuit123may include a processor124and a working memory125. The control circuit123may further include an error detection/correction circuit (ECC circuit)126and the like.

The processor124may control the overall operation of the memory controller120. The processor124may perform a logical operation. The processor124may communicate with the host HOST through the host interface121. The processor124may communicate with the memory device110through the memory interface122.

The processor124may be used to perform operations associated with a flash translation layer (FTL) to effectively manage the memory operations on the memory system100. The processor124may translate a logical block address (LBA) provided by the host into a physical block address (PBA) through the FTL. The FTL may receive the LBA and translate the LBA into the PBA by using a mapping table.

There are various address mapping methods which may be employed by the FTL, based on the mapping unit. Typical address mapping methods may include a page mapping method, a block mapping method, and a hybrid mapping method.

The processor124may be configured to randomize data received from the host to write the randomized data to the memory cell array. For example, the processor124may randomize data received from the host by using a randomizing seed. The randomized data is provided to the memory device110and written to the memory cell array.

The processor124may be configured to derandomize data received from the memory device110during a read operation. For example, the processor124may derandomize data received from the memory device110by using a derandomizing seed. The derandomized data may be output to the host HOST.

The processor124may execute firmware (FW) to control the operation of the memory controller120. That is, the processor124may control the overall operation of the memory controller120and, in order to perform a logical operation, may execute (drive) firmware loaded into the working memory125during booting.

The firmware refers to a program or software stored on a certain nonvolatile memory and is executed inside the memory system100.

In some implementations, the firmware may include various functional layers. For example, the firmware may include at least one of a flash translation layer (FTL) configured to translate a logical address in the host HOST requests to a physical address of the memory device110, a host interface layer (HIL) configured to interpret a command that the host HOST issues to a data storage device such as the memory system100and to deliver the command to the FTL, and a flash interface layer (FIL) configured to deliver a command issued by the FTL to the memory device110.

For example, the firmware may be stored in the memory device110, and then loaded into the working memory125.

The working memory125may store firmware, program codes, commands, or pieces of data necessary to operate the memory controller120. The working memory125may include, for example, at least one of a static RAM (SRAM), a dynamic RAM (DRAM), and a synchronous RAM (SDRAM) as a volatile memory.

The error detection/correction circuit126may be configured to detect and correct one or more erroneous bits in the data by using an error detection and correction code. In some implementations, the data that is subject to the error detection and correction may include data stored in the working memory125, and data retrieved from the memory device110.

The error detection/correction circuit126may be implemented to decode data by using the error correction code. The error detection/correction circuit126may be implemented by using various decoding schemes. For example, a decoder that performs nonsystematic code decoding or a decoder that performs systematic code decoding may be used.

In some implementations, the error detection/correction circuit126may detect one or more erroneous bits on a sector basis. That is, each piece of read data may include multiple sectors. In the present disclosure, a sector may refer to a data unit that is smaller than the read unit (e.g., page) of a flash memory. Sectors constituting each piece of read data may be mapped based on addresses.

In some implementations, the error detection/correction circuit126may calculate a bit error rate (BER) and determine whether the number of erroneous bits in the data is within the error correction capability sector by sector. For example, if the BER is higher than a reference value, the error detection/correction circuit126may determine that the erroneous bits in the corresponding sector are uncorrectable and the corresponding sector is marked “fail.” If the BER is lower than or equals to the reference value, the error detection/correction circuit126may determine that the corresponding sector is correctable or the corresponding sector can be marked “pass.”

The error detection/correction circuit126may perform error detection and correction operations successively on all read data. When a sector included in the read data is correctable, the error detection/correction circuit126may move on to the next sector to check whether an error correction operation is needed on the next sector. Upon completion of the error detection and correction operations on all read data in this manner, the error detection/correction circuit126may acquire information as to which sector is deemed uncorrectable in the read data. The error detection/correction circuit126may provide such information (e.g., address of uncorrectable bits) to the processor124.

The memory system100may also include a bus127to provide a channel between the constituent elements121,122,124,125, and126of the memory controller120. The bus127may include, for example, a control bus for delivering various types of control signals and commands, and a data bus for delivering various types of data.

By way of example,FIG.1illustrates the above-mentioned constituent elements121,122,124,125, and126of the memory controller120. It is noted that some of those illustrated in the drawings may be omitted, or some of the above-mentioned constituent elements121,122,124,125, and126of the memory controller120may be integrated into a single element. In addition, in some implementations, one or more other constituent elements may be added to the above-mentioned constituent elements of the memory controller120.

FIG.2is a block diagram schematically illustrating a memory device110in accordance with an embodiment of the present disclosure.

In some implementations, the memory device110may include a memory cell array210, an address decoder220, a read/write circuit230, a control logic240, and a voltage generation circuit250.

The memory cell array210may include multiple memory blocks BLK1-BLKz, where z is a natural number equal to or larger than 2.

In the multiple memory blocks BLK1-BLKz, multiple word lines WL and multiple bit lines BL may be disposed in rows and columns, and multiple memory cells MC may be arranged.

The multiple memory blocks BLK1-BLKz may be connected to the address decoder220through the multiple word lines WL. The multiple memory blocks BLK1-BLKz may be connected to the read/write circuit230through the multiple bit lines BL.

Each of the multiple memory blocks BLK1-BLKz may include multiple memory cells. For example, the multiple memory cells are nonvolatile memory cells. In some implementations, such nonvolatile memory cells may be arranged in a vertical channel structure.

The memory cell array210may be configured as a memory cell array having a two-dimensional structure. In some implementations, the memory cell array210may be arranged in a three-dimensional structure.

Each of the multiple memory cells included in the memory cell array210may store at least one bit of data. For example, each of the multiple memory cells included in the memory cell array210may be a single-level cell (SLC) configured to store one bit of data. As another example, each of the multiple memory cells included in the memory cell array210may be a multi-level cell (MLC) configured to store two bits of data per memory cell. As another example, each of the multiple memory cells included in the memory cell array210may be a triple-level cell (TLC) configured to store three bits of data per memory cell. As another example, each of the multiple memory cells included in the memory cell array210may be a quad-level cell (QLC) configured to store four bits of data per memory cell. As another example, the memory cell array210may include multiple memory cells, each of which may be configured to store at least five bits of data per memory cell.

Referring toFIG.2, the address decoder220, the read/write circuit230, the control logic240, and the voltage generation circuit250may operate as peripheral circuits configured to drive the memory cell array210.

The address decoder220may be connected to the memory cell array210through the multiple word lines WL.

The address decoder220may be configured to operate in response to command and control signals of the control logic240.

The address decoder220may receive addresses through an input/output buffer inside the memory device110. The address decoder220may be configured to decode a block address among the received addresses. The address decoder220may select at least one memory block based on the decoded block address.

The address decoder220may receive a read voltage Vread and a pass voltage Vpass from the voltage generation circuit250.

The address decoder220may, during a read operation, apply the read voltage Vread to a selected word line WL inside a selected memory block and apply the pass voltage Vpass to the remaining non-selected word lines WL.

The address decoder220may apply a verification voltage generated by the voltage generation circuit250to a selected word line WL inside a selected memory block, during a program verification operation, and may apply the pass voltage Vpass to the remaining non-selected word lines WL.

The address decoder220may be configured to decode a column address among the received addresses. The address decoder220may transmit the decoded column address to the read/write circuit230.

The memory device110may perform the read operation and the program operation page by page. Addresses received when the read operation and the program operation are requested may include at least one of a block address, a row address, and a column address.

The address decoder220may select one memory block and one word line based on the block address and the row address. The column address may be decoded by the address decoder220and provided to the read/write circuit230.

The address decoder220may include at least one of a block decoder, a row decoder, a column decoder, and an address buffer.

The read/write circuit230may include multiple page buffers PB. The read/write circuit230may operate as a “read circuit” when the memory cell array210performs a read operation, and may operate as a “write circuit” when the memory cell array210performs a write operation.

The above-mentioned read/write circuit230is also referred to as a page buffer circuit including multiple page buffers PB, or a data register circuit. The read/write circuit230may include a data buffer that participates in a data processing function and, in some implementations, may further include a cache buffer for data caching.

The multiple page buffers PB may be connected to the memory cell array210through the multiple bit lines BL. In order to detect or sense the threshold voltage Vth of the memory cells during a read operation and a program verification operation, the multiple page buffers PB may continuously supply a sensing current to the bit lines BL connected to the memory cells to detect, at a sensing node, a change proportional to the amount of current that varies depending on the program state of a corresponding memory cell, and may hold or latch the corresponding voltage as sensing data.

The read/write circuit230may operate in response to page buffer control signals output from the control logic240.

During a read operation, the read/write circuit230senses a voltage value of a memory cell and the voltage value is read out as data. The read/write circuit230temporarily stores the retrieved data, and outputs the data DATA to the input/output buffer of the memory device110. In an embodiment, the read/write circuit230may include a column selection circuit, in addition to the page buffers PB or page registers.

The control logic240may be connected to the address decoder220, the read/write circuit230, and the voltage generation circuit250. The control logic240may receive a command CMD and a control signal CTRL through the input/output buffer of the memory device110.

The control logic240may be configured to control the overall operation of the memory device110in response to the control signal CTRL. The control logic240may output a control signal for adjusting the voltage level of sensing nodes of multiple page buffers PB to a pre-charge voltage level.

The control logic240may control the read/write circuit230to perform a read operation in the memory cell array210. The voltage generation circuit250may generate a read voltage Vread and a pass voltage Vpass, which are used during the read operation, in response to a voltage generation circuit control signal output from the control logic240.

A memory block BLK included in the memory device110may include multiple pages PG. In some implementations, a plurality of memory cells arranged in columns form memory cell strings, and a plurality of memory cells arranged in rows form memory blocks. Each of the multiple pages PG is coupled to one of word lines WL, and each of the memory cell strings STR is coupled to one of bit lines BL.

In the memory block BLK, multiple word lines WL and multiple bit lines BL may be arranged in rows and columns. For example, each of the multiple word lines WL may be arranged in the row direction, and each of the multiple bit lines BL may be arranged in the column direction. As another example, each of the multiple word lines WL may be arranged in the column direction, and each of the multiple bit lines BL may be arranged in the row direction.

In some implementations, the multiple word lines WL and the multiple bit lines BL may intersect with each other, thereby addressing a single memory cell in the array of multiple memory cells MC. In some implementations, each memory cell MC may include a transistor TR that includes a material layer that can hold an electrical charge.

For example, the transistor TR arranged in each memory cell MC may include a drain, a source, and a gate. The drain (or source) of the transistor TR may be connected to the corresponding bit line BL directly or via another transistor TR. The source (or drain) of the transistor TR may be connected to the source line (which may be the ground) directly or via another transistor TR. The gate of the transistor TR may include a floating gate (FG) surrounded by an insulator, and a control gate (CG) to which a gate voltage is applied from a word line WL.

In each of the multiple memory blocks BLK1-BLKz, a first selection line (also referred to as a source selection line or a drain selection line) may be additionally arranged outside the first outermost word line, which is closer to the read/write circuit230among two outermost word lines, and a second selection line (also referred to as a drain selection line or a source selection line) may be additionally arranged outside the other second outermost word line.

In some implementations, at least one dummy word line may be additionally arranged between the first outermost word line and the first selection line. In addition, at least one dummy word line may be additionally arranged between the second outermost word line and the second selection line.

A read operation and a program operation (write operation) of the memory block may be performed page by page, and an erasure operation may be performed memory block by memory block.

FIG.3is a diagram illustrating a structure of word lines WL and bit lines BL of a memory device110in accordance with an embodiment of the present disclosure.

Referring toFIG.3, the memory device110has a core area in which memory cells MC are arranged, and an auxiliary area (the remaining area other than the core area) to include circuitry that is used to perform the operations of the memory cell array210.

In the core area, a certain number of memory cells arranged in one direction can be called “page” PG, and a certain number of memory cells that are coupled in series can be called “memory cell string” STR.

The word lines WL1-WL9may be connected to a row decoder310. The bit lines BL may be connected to a column decoder320. A data register330, which corresponds to the read/write circuit230ofFIG.2, may exist between the multiple bit lines BL and the column decoder320.

The multiple word lines WL1-WL9may correspond to multiple pages PG.

For example, each of the multiple word lines WL1-WL9may correspond to one page PG as illustrated inFIG.3. When each of the multiple word lines WL1-WL9has a large size, each of the multiple word lines WL1-WL9may correspond to at least two (e.g., two or four) pages PG. Each page PG is the smallest unit in a program operation and a read operation, and all memory cells MC within the same page PG may perform simultaneous operations when conducting a program operation and a read operation.

The multiple bit lines BL may be connected to the column decoder320. In some implementations, the multiple bit lines BL may be divided into odd-numbered bit lines BL and even-numbered bit lines BL such that a pair of an odd-numbered bit line and an even-numbered bit line is coupled in common to a column decoder320.

In accessing a memory cell MC, the row decoder310and the column decoder320are used to locate a desired memory cell based on the address.

In some implementations, the data register330plays an important role because all data processing by the memory device110, including program and read operations, occurs via the data register330. If data processing by the data register330is delayed, all of the other areas need to wait until the data register330finishes the data processing, degrading the overall performance of the memory device110.

Referring to the example illustrated inFIG.3, in one memory cell string STR, multiple transistors TR1-TR9may be connected to multiple word lines WL1-WL9, respectively. In some implementations, the multiple transistors TR1-TR9correspond to memory cells MC. In this example, the multiple transistors TR1-TR9include control gates CG and floating gates FG.

The multiple word lines WL1-WL9include two outermost word lines WL1and WL9. A first selection line DSL may be additionally arranged outside the first outermost word line WL1, which is closer to the data register330and has a shorter signal path compared to the other outermost word line WL9. A second selection line SSL may be additionally arranged outside the other second outermost word line WL9.

The first selection transistor D-TR, which is controlled to turn on/off by the first selection line DSL, has a gate electrode connected to the first selection line DSL, but includes no floating gate FG. The second selection transistor S-TR, which is controlled to turn on/off by the second selection line SSL, has a gate electrode connected to the second selection line SSL, but includes no floating gate FG.

The first selection transistor D-TR is used as a switch circuit that connects the corresponding memory cell string STR to the data register330. The second selection transistor S-TR is used as a switch circuit that connects the corresponding memory cell string STR to the source line SL. That is, the first selection transistor D-TR and the second selection transistor S-TR can be used to enable or disable the corresponding memory cell string STR.

In some implementations, the memory system100applies a predetermined turn-on voltage Vcc to the gate electrode of the first selection transistor D-TR, thereby turning on the first selection transistor D-TR, and applies a predetermined turn-off voltage (e.g., 0V) to the gate electrode of the second selection transistor S-TR, thereby turning off the second selection transistor S-TR.

The memory system100turns on both of the first and second selection transistors D-TR and S-TR during a read operation or a verification operation. Accordingly, during a read operation or a verification operation, an electric current may flow through the corresponding memory cell string STR and drain to the source line SL, which corresponds to the ground, such that the voltage level of the bit line BL can be measured. However, during a read operation, there may be a time difference in the on/off timing between the first selection transistor D-TR and the second selection transistor S-TR.

The memory system100may apply a predetermined voltage (e.g., +20V) to the substrate through a source line SL during an erasure operation. The memory system100applies a certain voltage to allow both the first selection transistor D-TR and the second selection transistor S-TR to float during an erasure operation. As a result, the applied erasure voltage can remove electrical charges from the floating gates FG of the selected memory cells.

FIG.4illustrates an example of an operation in which the memory system100calculates a first data size DATA_SIZE_1 according to embodiments of the present disclosure.

Referring toFIG.4, the memory controller120of the memory system100may calculate a first data size DATA_SIZE_1, which is the sum of sizes of data requested to be written from outside the memory system100(e.g., host HOST) after a first reference time point REF_TP1. The first reference time point REF_TP1 is a reference time point at which the calculation of the first data size DATA is started.

The above-described first reference time point REF_TP1 may be arbitrarily determined or may be determined by another way. For example, the first reference time point REF_TP1 may be a time point when booting of the memory system100is completed. As another example, the first reference time point REF_TP1 may be a time point when a communication link is established between the memory system100and a device located outside the memory system100. As another example, the first reference time point REF_TP1 may be a time point when the memory system100starts to receive a write request from outside of the memory system100.

InFIG.4, when the size of data requested to be written by a first write request from outside of the memory system100after the first reference time point REF_TP1 is A, the first data size DATA_SIZE_1 is A.

Subsequently, when the size of data additionally requested to be written by a second write request from outside the memory system100is B, the first data size DATA_SIZE_1 is A+B.

Subsequently, when the size of data additionally requested to be written by a third write request from outside the memory system100is C, the first data size DATA_SIZE_1 is A+B+C.

Each write request from outside of the memory system100may be a write request for new data or an update request for data already stored in the memory device110of the memory system100.

FIG.5illustrates an example of an operation in which the memory system100calculates a second data size DATA_SIZE_2 according to embodiments of the present disclosure.

Referring toFIG.5, the memory controller120of the memory system may calculate a second data size DATA_SIZE_2, which is the sum of sizes of data updated by write requests from outside of the memory system100(e.g., host HOST) among data already stored in the memory device110of the memory system100after a second reference time point REF_TP2. The second reference time point REF_TP2 is a reference time point at which the calculation of the second data size DATA_SIZE_2 is started.

The update of data already stored in the memory device110means that, in a state in which valid data corresponding to a specific logical address exists in the memory device110, new data corresponding to the logical address is written to the memory device110. Note that when new data corresponding to the logical address is written after data corresponding to that logical address is deleted due to a specific operation (e.g., an erase operation or a trim operation), data already stored in the memory device110is not considered to be updated.

In embodiments, the second reference time point REF_TP2 may be the same as the first reference time point REF_TP1 or may be a time point after the first reference time point REF_TP1.

InFIG.5, when the size of data requested to be written by a first write request from outside of the memory system100after the first reference time point REF_TP1 is A and the size of data to be updated among data already stored in the memory device110is A′, the first data size DATA_SIZE_1 is A and the second data size DATA is A′.

Subsequently, when the size of data additionally requested to be written by a second write request from outside the memory system100is B and the size of data to be updated among data already stored in the memory device110is B′, the first data size DATA_SIZE_1 is A+B, and the second data size DATA_SIZE_2 is A′+B′.

Subsequently, when the size of data additionally requested to be written by a third write request from outside the memory system100is C and the size of data to be updated among data already stored in the memory device110is C′, the first data size DATA_SIZE_1 is A+B+C, and the second data size DATA is A′+B′+C′.

In embodiments of the present disclosure, the memory controller120of the memory system100may control execution of garbage collection on data stored in the memory device110based on the first data size DATA and the second data size DATA_SIZE_2. For example, the memory controller120may determine whether to execute garbage collection on data stored in the memory device110based on the first data size DATA_SIZE_1 and the second data size DATA_SIZE_2 when the first data size DATA_SIZE_1 becomes equal to or greater than a multiple of predetermined reference data size. Garbage collection is process for creating free spaces for writing data in the memory device110. Typically the free spaces are one or more blocks, and are created by erasing the one or more blocks after moving any valid data in them to other blocks.

The memory controller120may control execution of garbage collection on data stored in the memory device110based on the number of free memory blocks of the memory device110. For example, the memory controller120may execute garbage collection on data stored in the memory device110when the number of free memory blocks of the memory device110is equal to or less than a preset threshold free memory block number.

In embodiments of the present disclosure, the memory controller120may consider the first data size DATA_SIZE_1 and the second data size DATA_SIZE_2 as well as the number of free memory blocks of the memory device110when controlling garbage collection execution. Hereinafter, this will be described in detail.

FIG.6illustrates an example of how the memory system100determines whether to execute garbage collection according to embodiments of the present disclosure.

Referring toFIG.6, the memory controller120of the memory system100may execute garbage collection on data stored in the memory device110when the first data size DATA_SIZE_1 becomes equal to or greater than a multiple of a predetermined reference data size REF_DATA_SIZE.

The reference data size REF_DATA_SIZE may be determined in various ways. For example, the reference data size REF_DATA_SIZE may be determined based on the write throughput of the memory system100.

The write throughput of the memory system100is the maximum value of the size of data that an external device (e.g., host HOST) of the memory system100can write to the memory system100during a predetermined time. For example, if the external device of the memory system100can write up to 256 megabytes (MB) of data to the memory system100in one second, the write throughput of the memory system100is 256 megabytes per second (MB/s).

The reference data size REF_DATA_SIZE may be determined as a multiple of the write throughput of the memory system100. For example, the reference data size REF_DATA_SIZE may be determined to be 1 GB, which is 4 times of 256 MB, corresponding to data written by 4 seconds of writing at a write throughput of 256 MB/s.

As another example, the reference data size REF_DATA_SIZE may be determined in the process of optimizing the performance of the memory system100when the memory system100is developed. That is, the performance (e.g., execution speed of a read operation/write operation/erase operation) of the memory system100according to the various reference data size REF_DATA_SIZE may be measured. And as a result, the value that produces the highest performance may be set as the reference data size REF_DATA_SIZE.

When the first data size DATA_SIZE_1 becomes equal to or greater than a multiple of the predetermined reference data size REF_DATA_SIZE, the memory controller120may execute garbage collection by determining that it is necessary to secure a free space in which data can be newly written in the memory device110.

InFIG.6, when the first data size DATA_SIZE_1 becomes equal to or greater than N times (N is a natural number) the reference data size REF_DATA_SIZE, the memory controller120may execute garbage collection on the data stored in the memory device110.

Thereafter, when the first data size DATA_SIZE_1 becomes greater than or equal to M times (M is a natural number different from N) the reference data size REF_DATA_SIZE, the memory controller120may re-execute garbage collection on data stored in the memory device110.

As such, the memory controller120may secure a free space in which data can be written in the memory device110by executing garbage collection according to the size of data requested to be written from outside the memory system100.

However, if the memory controller120always executes garbage collection whenever the first data size DATA_SIZE_1 becomes greater than or equal to a multiple of the predetermined reference data size REF_DATA_SIZE, there is a possibility that the memory controller120executes unnecessary garbage collection.

If the write request from outside of the memory system100is a request to update data already stored in the memory device110, there is no need to separately execute garbage collection on the data to be updated. The memory device110does not overwrite data to the same (physical) location. Accordingly, when the memory device110processes a request for updating data already stored, the data already stored in the memory device110is invalidated and the updated data is written to a new location. As a result, even if a separate garbage collection is not performed for the updated data, the same effect as executing garbage collection may occur.

Accordingly, when the first data size DATA_SIZE_1 becomes a multiple of the predetermined reference data size REF_DATA_SIZE, the memory controller120may determine, based on the second data size DATA_SIZE_2, whether it is necessary to execute garbage collection. And, if it is determined that there is no need to execute garbage collection, the memory controller120may skip garbage collection. Skipping garbage collection means not executing garbage collection.

Through this, the memory controller120of the memory system100may prevent unnecessary garbage collection from being executed, which may increase the write performance of the memory system100and extend the lifespan of the memory system100.

FIG.7illustrates a flow chart of an operation in which the memory system determines whether to skip garbage collection according to embodiments of the present disclosure.

Referring toFIG.7, the memory controller120of the memory system100determines whether the first data size DATA_SIZE_1 is greater than or equal to a multiple of the reference data size REF_DATA_SIZE (S710). If the first data size DATA_SIZE_1 is not greater than or equal to multiple of the reference data size REF_DATA_SIZE (S710-N), the memory controller120may end the operation of determining whether to skip garbage collection.

If the first data size DATA_SIZE_1 is equal to or greater than a multiple of the reference data size REF_DATA_SIZE (S710-Y), the memory controller120may determine whether the second data size DATA_SIZE_2 is equal to or greater than a predetermined threshold data size (S720).

In this case, the threshold data size may be the same as the reference data size REF_DATA_SIZE. That is, the memory controller120may determine whether the second data size DATA_SIZE_2 is equal to or greater than a reference size for executing one garbage collection. This is because, when the second data size DATA_SIZE_2 becomes equal to or greater than a reference size for executing one garbage collection, a gain of skipping garbage collection once occurs.

If the second data size DATA_SIZE_2 is equal to or greater than the threshold data size (S720-Y), the memory controller120may skip garbage collection for data stored in the memory device110(S730).

On the other hand, if the second data size DATA_SIZE_2 is less than the threshold data size (S720-N), the memory controller120may execute garbage collection for data stored in the memory device110(S740).

FIG.8illustrates an example of an operation in which the memory system100skips garbage collection according to embodiments of the present disclosure.

Referring toFIG.8, the memory controller120of the memory system100may check the second data size DATA_SIZE_2 when the first data size DATA_SIZE_1 becomes equal to or greater than N times the reference data size REF_DATA_SIZE.

When, after a first write request to write data of size A of which data of size A′ is updated data, the first data size DATA_SIZE_1 is A, since the first data size DATA_SIZE_1 has not become equal to or greater than N times the reference data size REF_DATA_SIZE, the memory controller120does not execute garbage collection on data stored in the memory device110.

When, after a second write request to write data of size B of which data of size B′ is updated data, the first data size DATA_SIZE_1 is A+B, the first data size DATA_SIZE_1 becomes equal to or greater than N times the reference data size REF_DATA_SIZE, and in this example, the second data size DATA_SIZE_2, A′+B′, is less than the threshold data size THR.

In this case, the memory controller120may execute garbage collection on data stored in the memory device110.

Subsequently, the memory controller120of the memory system100may check the second data size DATA_SIZE_2 when the first data size DATA is M times the reference data size REF_DATA_SIZE. In this case, after a third write request to write data of size C of which data of size C′ is updated data, the second data size DATA_SIZE_2, A′+B′+C′, is greater than or equal to the threshold data size THR.

In this case, the memory controller120may skip garbage collection on data stored in the memory device110. That is, the memory controller120may execute another operation (e.g., a read operation or a write operation) requested from outside of the memory system100instead of executing garbage collection. Accordingly, the memory controller120may prevent a problem in which the performance of the memory system100is degraded due to the garbage collection being executed.

In embodiments, the memory controller120may reset the second reference time point REF_TP2 and the second data size DATA_SIZE_2 after skipping garbage collection. This is to prevent the memory controller120from continuously skipping garbage collection when the memory system100receives an additional write request from outside of the memory system100.

FIG.9illustrates an example of an operation in which the memory system100resets the second reference time point REF_TP2 and the second data size DATA_SIZE_2 after skipping garbage collection according to embodiments of the present disclosure

Referring toFIG.9, the memory controller120of the memory system100may reset the second reference time point REF_TP2 after a time point at which the memory controller120determined to skip garbage collection.

The memory controller120may reset the second data size DATA_SIZE_2 to 0. Thereafter, when data already stored in the memory device110is updated, the second data size DATA_SIZE_2 may increase again.

In embodiments, the memory controller120of the memory system100may change the execution time of garbage collection instead of skipping garbage collection as was described with reference toFIG.8.

FIG.10illustrates an example of an operation in which the memory system100changes an execution time of garbage collection according to embodiments of the present disclosure.

Referring toFIG.10, after first and second write requests with respective sizes of updated data A′ and B′, the memory controller120of the memory system100may check the second data size DATA_SIZE_2 when the first data size DATA_SIZE_1 becomes N times or more the reference data size REF_DATA_SIZE. In the example shown, the second data size DATA_SIZE_2, A′+B′, is less than the threshold data size THR.

In this case, the memory controller120may execute garbage collection on data stored in the memory device110for a first time T1.

Subsequently, after a third write request with a respective size of updated data C′, the memory controller120may check the second data size DATA_SIZE_2 when the first data size DATA_SIZE_1 becomes M or more times the reference data size REF_DATA_SIZE. In the example shown, the second data size DATA_SIZE_2, A′+B′+C′, is greater than or equal to the threshold data size THR.

In this case, the memory controller120may execute garbage collection on data stored in the memory device110for a second time T2. In this case, the second time T2 is shorter than the first time T1.

That is, the memory controller120may reduce the maximum allowed time execution time for the garbage collection instead of skipping the garbage collection, thereby preventing the problem of degradation of the write performance of the memory system100.

FIG.11illustrates an operating method of the memory system100according to embodiments of the present disclosure.

Referring toFIG.11, the operating method of the memory system100may include calculating a first data size DATA_SIZE_1, which is the sum of sizes of data requested to be written from outside the memory system100after a first reference time point REF_TP1 (S1110).

The operating method of the memory system100may further include calculating a second data size DATA_SIZE_2, which is the sum of sizes of data updated by write requests from outside of the memory system100among data already stored in the memory device110from a second reference time point REF_TP2 (S1120).

The operating method of the memory system100may further include controlling execution of garbage collection on data stored in the memory device110based on the first data size DATA_SIZE_1 and the second data size DATA_SIZE_2 (S1130).

For example, the operation S1130may determine whether to execute garbage collection on data stored in the memory device110when the first data size DATA_SIZE_1 becomes greater than or equal to a multiple of a predetermined reference data size REF_DATA_SIZE.

In this case, the reference data size REF_DATA_SIZE may be determined based on the write throughput of the memory system100.

For example, the operation S1130may skip the garbage collection when the second data size DATA_SIZE_2 is greater than or equal to a predetermined threshold data size, and execute the garbage collection when the second data size DATA_SIZE_2 is less than the threshold data size.

In this case, the threshold data size may be equal to the reference data size REF_DATA_SIZE.

In embodiments, the operating method of the memory system100may further include resetting the second reference time point REF_TP2 and the second data size DATA_SIZE_2 after skipping the garbage collection in response to the second data size is greater than or equal to the threshold data size.

As another example, the operation S1130may change, when the second data size DATA_SIZE_2 is equal to or greater than a predetermined threshold data size, an allocated time during which the garbage collection is executed from a first time T1 to a second time T2. The second time T2 may be shorter than the first time T1.

FIG.12is a diagram illustrating the configuration of a computing system1200based on an embodiment of the disclosed technology.

Referring toFIG.12, the computing system1200based on an embodiment of the disclosed technology may include: a memory system100electrically connected to a system bus1260; a CPU1210configured to control the overall operation of the computing system1200; a RAM1220configured to store data and information related to operations of the computing system1200; a user interface/user experience (UI/UX) module1230configured to provide the user with a user environment; a communication module1240configured to communicate with an external device as a wired and/or wireless type; and a power management module1250configured to manage power used by the computing system1200.

The computing system1200may be a personal computer (PC) or may include a mobile terminal such as a smartphone, a tablet or various electronic devices.

The computing system1200may further include a battery for supplying an operating voltage, and may further include an application chipset, a graphic-related module, a camera image processor, and a DRAM. Other elements would be obvious to a person skilled in the art.

The memory system100may include not only a device configured to store data in a magnetic disk such as a hard disk drive (HDD), but also a device configured to store data in a nonvolatile memory such as a solid state drive (SSD), a universal flash storage device, or an embedded MMC (eMMC) device. The non-volatile memory may include a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a flash memory, a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), and the like. In addition, the memory system100may be implemented as storage devices of various types and mounted inside various electronic devices.

Based on embodiments of the disclosed technology described above, the operation delay time of the memory system may be advantageously reduced or minimized. In addition, based on an embodiment of the disclosed technology, an overhead occurring in the process of calling a specific function may be advantageously reduced or minimized. Although various embodiments of the disclosed technology have been described with particular specifics and varying details for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions may be made based on what is disclosed or illustrated in the present disclosure without departing from the spirit and scope of the invention as defined in the following claims.