Patent ID: 12232326

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

FIG.1illustrates a cross-sectional view of a semiconductor device10in accordance with some embodiments. In some embodiments, the semiconductor device10is formed with integrated memory devices120and130. The semiconductor device10may include active devices110and three-dimensional (3D) memory devices120,130. The active devices110may be field effect transistor (FET) devices. In one embodiment, the active devices110are formed through the front-end-of-line (FEOL) manufacturing processes and include fin field effect transistors (FinFETs). The at least one of the memory devices120,130may include three-dimensional (3D) ferroelectric random access memory (FeRAM) devices formed through the back-end-of-line (BEOL) manufacturing processes. It is understood that FinFETs are used as examples, and other kinds of FEOL devices such as planar transistors or gate-all-around (GAA) transistors may be used herein and included within the scope of the present disclosure. That is, the 3D memory devices120,130may be integrated with or in any suitable semiconductor devices. InFIG.1, the details of the memory devices120,130are not shown and further details will be described later in subsequent figures.

As illustrated inFIG.1, the semiconductor device10includes different regions for forming different types of circuits. For example, the semiconductor device10includes a first region102for forming logic circuits and a second region104for forming peripheral circuits, input/output (I/O) circuits, electrostatic discharge (ESD) circuits, and/or analog circuits. The semiconductor device10may also include other regions for forming other types of circuits which are fully intended to be included within the scope of the present disclosure. The semiconductor device10includes a substrate101. In some embodiments, the substrate101is a bulk substrate, such as a silicon substrate, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. In some embodiments, the substrate101includes other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. For example, additional electrical components, such as resistors, capacitors, inductors, diodes, or the like, is formed in or on the substrate101during the FEOL manufacturing processes.

As seen inFIG.1, the active devices110are formed on the substrate101, and isolation regions103, such as shallow trench isolation (STI) regions, are formed between or around the active devices110. In some embodiments, the active device110includes a gate electrode107and source/drain regions105/106. The gate electrode107may be formed over the substrate101with gate spacers108along sidewalls of the gate electrode107. The source/drain regions105/106such as doped or epitaxial source/drain regions are formed on opposing sides of the gate electrode107. In some embodiments, conductive contacts109, such as gate contacts and source/drain contacts, are formed over and electrically coupled to respective underlying electrically conductive features (e.g., gate electrodes107or source/drain regions105/106). In some embodiments, a dielectric layer116, such as an inter-layer dielectric (ILD) layer, is formed over the substrate101and covering the source/drain regions105/106, the gate electrode107and the contacts109, and other electrically conductive features, such as conductive interconnect structures including conductive vias112and conductive lines114, are embedded in the dielectric layer116. It is understood that the dielectric layer116may include more than one dielectric layers of the same or different dielectric materials. Collectively, the substrate101, the active devices110, the contacts109, conductive features112/114, and the dielectric layers116shown inFIG.1may be referred to as the front-end level12L.

Referring toFIG.1, dielectric layers118and dielectric layers122are formed over the dielectric layer116in alternation. In one embodiment, at least one of the dielectric layers118includes an etch stop layer (ESL). In some embodiments, the materials of the dielectric layers118is different from the materials of the dielectric layers116and122. In some embodiments, the material of the dielectric layer(s)118includes silicon nitride or carbide formed by plasma-enhanced physical vapor deposition (PECVD). In some embodiments, one or more of the dielectric layers118is omitted. In some embodiments, the dielectric layers116and122is formed of any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or low-k materials, formed by a suitable method, such as spin coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), or the like. InFIG.1, memory devices120and130, each of which may include a plurality of memory cells, are formed in the dielectric layer122and coupled to electrically conductive features (e.g., conductive vias124and conductive lines125) in the dielectric layer122.

InFIG.1, the memory devices120and130are formed at different layers of the dielectric layers122. The memory device120is formed at the lower layer, and the memory device130is formed at the upper layer. In some embodiments, the memory devices120and130have the same or similar structure. In some embodiments, the memory devices120and130have different structure designs. Although two layers of memory devices are depicted inFIG.1, other numbers of layers of memory devices, such as one layer, three layers, or more, are also possible and are encompassed within the scope of the present disclosure. Collectively, the layers of memory device120and130are referred to as the memory device level14L or a memory region of the semiconductor device10. The memory device level14L may be formed in the BEOL processes of semiconductor manufacturing. The memory devices120and130may be formed in the BEOL processes at any suitable locations within the semiconductor device10, such as over the first region102, over the second region104, or over a plurality of regions.

After the memory device level14L is formed, an interconnect level16L including electrically conductive interconnecting features (e.g., conductive vias126and conductive lines127) embedded in the dielectric layer(s)122is formed over the memory device level14L. Any suitable methods may be employed to form the interconnect level16L, and the details are not described herein. In some embodiments, the interconnect level16L is electrically connect the electrical components formed in/on the substrate101to form functional circuits. In some embodiments, the interconnect structure16L is also electrically coupled the memory devices120,130to the active devices110and/or the components in/on the substrate101. In addition, the memory devices120and130may be electrically coupled to an external circuit or an external device through the structure of the interconnect level16L. In some embodiments, the memory devices120and130are electrically coupled to the active devices110of the front-end level12L and/or other electrical components formed in the substrate101, and are controlled or accessed (e.g., written to or read from) by functional circuits of the semiconductor device10. Alternatively, the memory devices120,130are electrically coupled to (e.g., controlled or accessed) an external circuit of another semiconductor device through the structure of the interconnect level16L.

FIG.2toFIG.27show schematic three-dimensional views of structures produced at various stages of a manufacturing method of a memory device according to some embodiments of the present disclosure.FIG.28is a schematic cross-sectional view showing the structure ofFIG.27along crossline I-I′. According to some embodiments, the memory device may be a three-dimensional (3D) memory device with a ferroelectric material. The memory devices depicted in the following paragraphs may be used as the memory devices120and130inFIG.1.

InFIG.2, a plurality of conductive vias144are formed over the front-end level12L. In some embodiments, the conductive vias144are formed on conductive lines140, to electrically connect to the conductive lines140respectively. The conductive lines140may be parts of underlying FEOL circuits or device such as part of the front-end level12L as described in the previous embodiments. For example, the conductive lines140are electrically connected to conductive features such as the conductive lines114or the conductive lines125, or the conductive lines140are the conductive lines114or the conductive lines125. The conductive lines140may be formed in a dielectric layer142(shown inFIG.28), and the conductive vias144may be formed in a dielectric layer146(shown inFIG.28) on the dielectric layer142. In some embodiments, the conductive lines140extend along a first direction D1 (e.g., X direction) and arranged in parallel along a second direction D2 (e.g., Y direction) substantially perpendicular to the first direction D1. The conductive vias144are directly formed on the conductive lines140, that is, the conductive vias144are in physical contact with the conductive lines140, for example. The conductive vias144may be formed using a single damascene process. For example, the dielectric layer146is patterned utilizing a combination of photolithography and etching techniques with a mask to form openings corresponding to the desired patterns of the conductive vias144. The openings may respectively expose the conductive lines140. An optional diffusion barrier and/or optional adhesion layer may be deposited and the openings may then be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, combinations thereof, or the like, and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, combinations thereof, or the like. In an embodiment, the conductive vias144are formed by depositing a seed layer of copper or a copper alloy, and filling the openings by electroplating. A chemical mechanical planarization (CMP) process or the like may be used to remove excess conductive material from a surface of the dielectric layer146and to planarize surfaces of the dielectric layer146and the conductive vias144for subsequent processing. In some embodiments, as shown inFIG.2, adjacent conductive vias144are not aligned with each other in the second direction. However, the disclosure is not limited thereto. From a top view, the conductive vias144may be circular, square, rectangular or ring-shaped.

InFIG.3, a plurality of conductive lines148are formed on the conductive vias144, to electrically connect to the conductive vias144respectively. In some embodiments, the conductive lines148are formed in a dielectric layer (not shown) on the conductive vias144. The conductive lines148are directly formed on the conductive vias144, that is, the conductive lines148are in physical contact with the conductive vias144, for example. In some embodiments, the conductive lines148extend along the first direction D1 and arranged in parallel along the second direction D2. The conductive lines148may be formed using a single damascene process. For example, the dielectric layer is patterned utilizing a combination of photolithography and etching techniques with a mask to form trenches corresponding to the desired patterns of the conductive lines148. The trenches expose the conductive vias144respectively. An optional diffusion barrier and/or optional adhesion layer may be deposited and the trenches may then be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, combinations thereof, or the like, and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, combinations thereof, or the like. In an embodiment, the conductive lines148are formed by depositing a seed layer of copper or a copper alloy, and filling the trenches by electroplating. A chemical mechanical planarization (CMP) process or the like may be used to remove excess conductive material from a surface of the dielectric layer and to planarize surfaces of the dielectric layer and the conductive lines148for subsequent processing. In some embodiments, the conductive vias144and the conductive lines148are formed separately. However, the disclosure is not limited thereto. In alternative embodiments, the conductive vias144and the conductive lines148are formed simultaneously by a dual damascene process. In such embodiments, the conductive vias144and the conductive lines148are integrally formed in a dielectric layer.

InFIG.4, an etch stop layer160is formed on the conductive lines148, and a plurality of openings162are formed in the etch stop layer160to expose the conductive lines148, respectively. In some embodiments, the etch stop layer160is formed on the dielectric layer150to cover the conductive lines148. For example, the etch stop layer160is in physical contact with surfaces (e.g., entire top surfaces) of the conductive lines148. The etch stop layer160provides etching selectivity for subsequent etching processes. The etch stop layer160may include silicon carbide (SiC), silicon carbonitride, metal oxides such as aluminum oxide, or titanium oxide, metal nitrides such as aluminum nitride, titanium nitride, or the combination thereof. The etch stop layer160may be formed by a suitable formation method such as atomic layer deposition (ALD), CVD, PVD, or the like. The etch stop layer160may be patterned utilizing a combination of photolithography and etching techniques with a mask, to form the openings162therein. In some embodiments, the openings162are formed at locations where conductive pillars of source lines or bit lines are to be formed. In some embodiments, the openings162are arranged in an array. However, the disclosure is not limited thereto.

In some embodiments, a plurality of dielectric patterns164are then formed in the openings162of the etch stop layer160respectively. The dielectric patterns164may be formed by a deposition process and a planarization process. Accordingly, top surfaces of the dielectric patterns164are substantially coplanar with a top surface of the etch stop layer160, for example. In some embodiments, materials of the dielectric patterns164and the etch stop layer160are selected so that they are etched selectively relative each other. In some embodiments, the dielectric patterns164include silicon oxide. However, other materials are also possible. In some embodiments, the dielectric patterns164are sacrificial patterns (or dummy patterns), which will be etched off in later processes. As seen inFIG.4, the dielectric patterns164are formed with a width W1 (along the first direction) and a height H1 (along the third direction) that is substantially the same as a thickness (along the third direction) of the etch stop layer160. From a top view, the dielectric patterns164may be circular, square or rectangular.

InFIG.5, a stack202is formed on the etch stop layer160. In some embodiments, the stack202is a stack of multiple alternating dielectric layers and may also be referred to as a multilayered stack. In some embodiments, the multilayered stack202includes alternating first dielectric layers203and second dielectric layers204along a third direction (e.g., Z direction). In some embodiments, the dielectric materials for forming the first dielectric layers203and the second dielectric layers204include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, or the combination thereof. In some embodiments, the first dielectric layers203and the second dielectric layers204are formed by any compatible formation method, such as CVD, PVD, ALD, or the like. InFIG.5, the multilayered stack202includes five layers of the first dielectric layers203and four layers of the second dielectric layers204. It is comprehended that the number of the first dielectric layers203and the number of the second dielectric layers204may be any suitable number and may be adjusted based on product design.

In some embodiments, the materials of the first dielectric layers203are different from the materials of the second dielectric layers204. As the multilayered stack202will be patterned and etched in subsequent processes, the dielectric materials of the first dielectric layers203and the dielectric materials of the second dielectric layers204are chosen to have high or acceptable etching selectivity between each other or one another. In some embodiments, the second dielectric layers204are sacrificial layers (or dummy layers), which will be etched off in later processes and replaced with word lines for the memory cells, while the patterned first dielectric layers203are used as isolation layers for isolating later formed memory cells. In one embodiment, the etch stop layer160is formed of titanium nitride, the dielectric patterns164is formed of silicon oxide, the first dielectric layers203is formed of silicon oxide, and the second dielectric layers204is formed of silicon nitride. Other combinations of dielectric materials having acceptable etching selectivity from one another may also be used.

Referring toFIG.6, a trench forming process is performed and first trenches206are formed in the multilayered stack202. In some embodiments, the trenches206are trenches extending in parallel along the second direction. For example, the first trenches206penetrate through four first dielectric layers203and four second dielectric layers204(counted from the top) and expose the bottommost first dielectric layer203. In other embodiments, the first trenches206penetrate through the whole multilayered stack202and expose the etch stop layer160. The formation of the first trenches206involves using photolithographic and etching techniques, such as using a time-controlled etching process so as to stop at the bottommost first dielectric layer203. For example, the etch process includes a dry etching process such as reactive ion etch (RIE) process. In some embodiments, the first dielectric layers203are formed of silicon oxide, and the second dielectric layers204are formed of silicon nitride, and the first trenches206are formed using an anisotropic etching process such as a dry etching process with fluorine-based reactants. In one embodiment, the etch process includes a RIE process using reactants including CF4, CHF3, CCl4, CHCl3, F2, Cl2, H2, C4F8, Ar, He or mixtures thereof. Although sidewalls of the first trenches206are shown as straight vertical sidewalls, the sidewalls may have sloped profiles, or concave or convex surfaces. The aspect ratio of the first trenches206and the separation distance of the first trenches206are finely selected to allow the subsequently formed memory array having acceptable memory cell density.

Referring toFIG.7, an etching process is performed to remove portions of the second dielectric layers204from their sidewalls exposed by the first trenches206. That is, the second dielectric layers204are laterally recessed. In some embodiments, the recessed sidewalls204RS of the second dielectric layers204are recessed from the sidewalls of the first dielectric layers203to form first sidewall recesses207. The etching process may include an isotropic or an anisotropic etching process, which selectively etches the material of the second dielectric layers204at a faster rate than the material of the first dielectric layers203. In some embodiments, the etching process may be isotropic, and a wet etching process using phosphoric acid may be performed to form the concave first sidewall recesses207. In another embodiment, a dry etch process highly selective to the material of the second dielectric layers204may be used.

Referring toFIG.8, a seed layer208is formed over exposed surfaces of the first trenches206covering the bottommost first dielectric layer203. In some embodiments, the seed layer208is conformally formed over the first trenches206and the first sidewall recesses207, so that the seed layer208directly covers the topmost and bottommost first dielectric layers203and the sidewalls of the first dielectric layers203, and covers the recessed sidewalls204RS of the second dielectric layers204without filling up the first sidewall recesses207. In some embodiments, the seed layer208is formed of an electrically conductive material such as a metal nitride, e.g., titanium nitride, tantalum nitride, molybdenum nitride, zirconium nitride, hafnium nitride, or the like, and may be formed using CVD, ALD, or the like. In some embodiments, the material of the seed layer208includes titanium nitride or tantalum nitride.

Referring toFIG.9, a conductive material layer209is formed over the seed layer208. In some embodiments, the material of the conductive material layer209includes metals such as tungsten, ruthenium, molybdenum, cobalt, aluminum, nickel, copper, silver, gold, or alloys thereof, or the combinations thereof. In some embodiments, the material of the conductive material layer209includes tungsten. The conductive material layer209may be formed by a suitable deposition method, such as CVD, PVD, ALD, or the like. In some embodiments, the conductive material layer209at least fills the first sidewall recesses207but not filling up the first trenches206.

Referring toFIG.10, dielectric layers210are formed on the conductive material layer209and filling up the first trenches206. The formation of the dielectric layers210involves forming a dielectric material (not shown) over the conductive material layer209and filling the first trenches206and then performing a planarization process to remove the extra dielectric material, the conductive material layer209and the seed layer208above the topmost first dielectric layer203so as to form fin-shaped dielectric strips respectively in the first trenches206. In some embodiments, the material of the dielectric layers210is the same as the material of the first dielectric layers203. In some embodiments, the material of the dielectric layers210is different from the material of the first dielectric layers203. In some embodiments, the dielectric layers210is formed by any compatible formation method, such as CVD, PVD, ALD, or the like. In some embodiments, the planarization process includes a chemical mechanical polishing (CMP) process, an etching-back process or a combination thereof.

Referring toFIG.11, another trench forming process is performed and second trenches212(only one is shown inFIG.11) are formed in the stack202between the dielectric layers210in the first trenches206(seeFIG.10). In some embodiments, the trenches212are trenches extending in parallel, and the configurations of the second trenches212are similar to those of the first trenches206. As seen inFIG.11, the second trench212penetrates through four first dielectric layers203and four second dielectric layers204(counted from the top) and expose the bottommost first dielectric layer203. The formation of the trenches212may involve similar techniques and process used for forming the trenches206, and the details will not be repeated herein. In other embodiments, the trenches212penetrate through the whole multilayered stack202and expose the etch stop layer160.

Referring toFIG.12, in some embodiments, an etching process is performed to remove portions of the second dielectric layers204from their sidewalls exposed by the second trench(es)212. That is, the second dielectric layers204are laterally etched until the seed layer208is exposed. In some embodiments, after etching off the remaining second dielectric layer204, second sidewall recesses211are formed between the protruded portions of the first dielectric layer203and the sidewalls208RS of the seed layer208are exposed. The etching process may include an isotropic or an anisotropic etching process, which selectively etches the material of the second dielectric layers204at a faster rate than the material of the first dielectric layers203. In some embodiments, the etching process is similar to the etching process described inFIG.7, and such etching process stops at the seed layer208. In general, the second dielectric layers204are completely removed without remaining residues.

Referring toFIG.13, a seed layer214is formed over exposed surfaces of the second trench(es)212covering the bottommost first dielectric layer203. In some embodiments, the seed layer214conformally covers the second trench(es)212and the second sidewall recesses211, so that the seed layer214conformally covers the protruded portions of the first dielectric layers203, and covers the sidewalls208RS of the seed layer208without filling up the second sidewall recesses211. Later, a conductive material layer215is formed over the seed layer214. In some embodiments, the conductive material layer215at least fills the second sidewall recesses211but not filling up the second trench(es)212. In some embodiments, a dielectric layer216is later formed on the conductive material layer215and filling up the second trench212. In some embodiments, the dielectric layer216is formed as a fin-shaped dielectric strip individually located in the second trench212. In some embodiments, the material of the dielectric layer216is the same as the material of the dielectric layer210or the material of the first dielectric layers203. The formation of the seed layer214, the conductive material layer215and the dielectric layer216involves similar methods and materials used for forming the seed layer208, the conductive material layer209and the dielectric layer210described fromFIG.8toFIG.10, and the details will be skipped herein.

Referring toFIG.14, a pulling back process is performed to remove the dielectric layers210and216. In some embodiments, the dielectric layers210and216within the trenches206and212are removed to expose the conductive material layers209and215. Also, the topmost first dielectric layer203is removed during the pulling back process. In some embodiments, the pulling back process including a suitable etching process to remove the exposed first dielectric layer203(i.e. the topmost first dielectric layer), so that the seed layers208and214are exposed. The etching process may include an isotropic or an anisotropic etching process, which selectively etches the material of the first dielectric layers203and/or the material of the dielectric layer210and216, and such etching process stops at the seed layers208,214and the conductive material layers209and215.

Referring toFIG.15, a patterning process is performed to remove the extra seed layers208and214and the conductive material layers209and215above the fourth first dielectric layer203(counted upward from the etch stop layer160) and beyond the protruded portions of the first dielectric layers203in the first and second trenches206and212until the bottommost first dielectric layer203is exposed from the trenches206and212. InFIG.15, after the patterning process, portions of the seed layers208and214and portions of the conductive material layers209and215disposed within the sidewall recesses (or disposed within lateral coverage of the first dielectric layers203) remain and become respectively the seed portions208A and214A and conductive portions209A and215A, and other portions of the seed layers208and214and the conductive material layers209and215(e.g., portions disposed outside the sidewall recesses) are removed through the patterning process. As illustrated inFIG.15, after patterning, the seed portions208A/214A extends along three sides (e.g., the top surface, a sidewall, and the bottom surface) of corresponding conductive portions209A/215A. In some embodiments, the seed portions208A and214A are referred to as seed liners218, while the seed liners218and the conductive portions209A and215A are referred to as conductive features220. InFIG.15, after the patterning process, the sidewalls209RS and215RS of the conductive portions209A and215A are exposed through the first and second trenches206and212. In some embodiments, the sidewalls203RS of the first dielectric layers203are vertically substantially aligned with the sidewalls209RS and215RS of the conductive portions209A and215A. In some embodiments, the patterning process includes performing one or more etching processes. In some embodiments, the patterning process involve using suitable photolithography and etching techniques, such as performing an anisotropic etching process using a mask and followed by a planarization process (such as CMP). Herein, the trenches formed during the patterning process are major trenches but may be referred to as the trenches206and212, it is because these trenches have the similar dimensions and locations of the first and second trenches206and212in this embodiment. The formation of these trenches involves using photolithographic and etching techniques, such as using a time-controlled etching process so as to stop at the bottommost first dielectric layer203. For example, the etch process includes a dry etching process such as a RIE process.

The above-described processes may be regarded the replacement process for replacing the second dielectric layers204with the conductive features220, and the conductive features220may function as word lines of the memory device. InFIG.15, four stacks2021are shown located on the bottommost first dielectric layer203and these stacks2021are separated by the major trenches (i.e., first and second trenches206and212), but the number of the stacks2021depends on the number of the trenches and may vary depending on the layout design. Although the four stacks2021are shown with straight sidewalls, it is understood that the sidewall profiles may be slanted or slightly curved. InFIG.15, each multilayered stack2021includes three layers of the first dielectric layers203and three layers of the composite structure of the conductive features220which are alternately sandwiched between the first dielectric layers203. It is comprehended that the number of the first dielectric layers203and the layer number of the conductive features220may be any suitable number and may be adjusted based on product design. In some embodiments, the conductive features220have a same or similar overall thickness as the second dielectric layers204, and have a width the same with or similar to the lateral depth of the sidewall recesses207.

Referring toFIG.16, in some embodiments, a memory material layer223is formed on the sidewalls and bottoms of the trenches206and212, a channel material layer224is formed over the memory material layer223and a gate dielectric layer225is formed over the channel material layer224, and then a dielectric layer226is formed to fill the trenches206and212. In some embodiments, the formation process involves forming a ferroelectric material (not shown) conformally to line the sidewalls and bottoms of the trenches206and212, forming a channel material (not shown) conformally over the ferroelectric material, forming a gate dielectric material (not shown) conformally over the channel material, patterning the ferroelectric material, the channel material and the gate dielectric material to form inner trenches IT and to expose the bottommost first dielectric layer203, and then a dielectric material (not shown) is formed to fill up the inner trenches IT. In some embodiments, the inner trenches IT have a width W2 (along the first direction DO substantially the same as the width W1 of the dielectric patterns164. However, the disclosure is not limited thereto. Through the formation of the inner trenches IT, the later filled dielectric layers226physically split up the sequentially formed ferroelectric material, channel material and gate dielectric material into two parts (i.e. left and right parts located respectively on left and right sidewalls of the trenches206,212). Afterwards, a planarization process, such as a CMP process, may be performed to remove excess portions of the ferroelectric material, the channel material, the gate dielectric material and the dielectric material from the upper surfaces of the multilayered stack2021. As a result, the upper surfaces of the stacks2021are coplanar with the memory material layer(s)223, the channel material layer(s)224, the gate dielectric layer(s)225and the dielectric layer(s)226. In some embodiments, as depicted inFIG.16, the memory material layer223, the channel material layer224, the gate dielectric layer225located at left side of the dielectric layer226are physically separate from the memory material layer223, the channel material layer224, the gate dielectric layer225located at right side of the dielectric layer226in the same trench. In alternative embodiments, depending on the trench depth in the multilayered stack, although the channel material formed in the trench is split up by the later-formed dielectric material but the ferroelectric material formed in the same trench is intact but not split by the dielectric material.

In some embodiments, the memory material layer223is ferroelectric material and includes hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO), undoped hafnium oxide (HfO) or HfO doped with lanthanum (La), silicon (Si), aluminum (Al), or the like. In some embodiments, the memory material layer223is formed by a suitable deposition process such as ALD, CVD, PVD, or the like. In some embodiments, the channel material of the channel material layer224includes zinc oxide (ZnO), indium tungsten oxide (InWO), indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium tin oxide (ITO) or zinc tin oxide (ZTO). In some embodiments, the formation of the channel material layer224includes performing one or more deposition processes selected from CVD, ALD, and PVD. In some embodiments, the material of the gate dielectric layer225includes one or more high-k dielectric materials, such as ZrO2, Gd2O3, HfO2, BaTiO3, Al2O3, LaO2, TiO2, Ta2Os, Y2O3, STO, BTO, BaZrO, HfZrO, HfLaO, HfTaO, HfTiO, or combinations thereof. In some embodiments, the gate dielectric layer225includes one or more materials selected from aluminum oxide, hafnium oxide, tantalum oxide and zirconium oxide. In some embodiments, the formation of the gate dielectric layer225includes performing one or more deposition processes selected from CVD (such as, PECVD and laser-assisted CVD), ALD and PVD (such as, sputtering and e-beam evaporation).

In some embodiments, the dielectric layer226is formed of one or more acceptable dielectric materials including silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or the like. In some embodiments, the material of the dielectric layers226is the same as the material of the first dielectric layers203. In some embodiments, the material of the dielectric layers226is different from the material of the first dielectric layers203.

Referring toFIG.17, an etching process is performed to the dielectric layers226to form trench openings228in the dielectric layers226. In some embodiments, the etching process is selective and does not remove the memory material layers223, the channel material layers224and the gate dielectric layers225. In some embodiments, the trench openings228vertically extend through the dielectric layers226and beyond the stack2021and penetrate through the bottommost first dielectric layer203. In some embodiments, at the locations where the dielectric patterns164are disposed in the etch stop layer160, the etching process further removes the dielectric patterns164. Thus, the trench openings228partially penetrate through the etch stop layer160. The performed etching process may selectively remove the materials of the dielectric layers226and203and the dielectric patterns164and stop on the etch stop layer160and the conductive lines148. From the enlarged partial 3D view of a portion (enclosed by the dotted line to represent a cell unit) of the structure as shown at the right side ofFIG.17, it is seen that each trench opening228may have a width W2 (along the first direction DO and two depths Dp1, Dp2 (along the third direction D3) larger than the height of the stack2021. In some embodiments, the width W2 of the trench opening228is substantially the same as the width W1 of the dielectric patterns164and the trench opening228exposes the dielectric patterns164, and thus the etching process substantially removes the dielectric patterns164entirely. Accordingly, inner sidewalls ISW1 of the etch stop layer160are substantially flush with inner sidewalls ISW2 of the memory material layer223, the channel material layer224, the gate dielectric layer225and the bottommost first dielectric layer203. The depth Dp1 is substantially equal to a total of the height H2 of the stack2021and the thickness of the bottommost first dielectric layer203, and the depth Dp2 is substantially equal to a total of the height H2 of the stack2021, the thickness of the bottommost first dielectric layer203and the height H1 of the etch stop pattern164. The trench openings228may be formed using the same or similar processes for the previous trenches, and thus details are not repeated herein. As illustrated inFIG.17, since the trench openings228penetrate through the dielectric layers226and the bottommost first dielectric layer203, the remained dielectric blocks230vertically extend through the stack2021and the bottommost first dielectric layer203. InFIG.17, each dielectric block230is sandwiched between the opposing gate dielectric layers225of the corresponding trench, and the dielectric blocks230are separate from one another with a distance.

Referring toFIG.18, insulation layers232are formed to fill up the trench openings228. For example, the formation of the insulation layers232involves forming an insulating material over the stacks2021and filling up the trench openings228and performing a planarization process to remove the extra insulating material outside the trench openings228. In some embodiments, the material for forming the insulation layer232includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, or the combination thereof. In one embodiment, the insulating material of the insulation layers232includes silicon nitride. In some embodiments, the insulation layers232are formed by any compatible formation method, such as coating, CVD, PVD, ALD or the like.

Referring toFIG.19, an etching process is performed to the insulation layers232to form trench openings234in the insulation layers232, and the gate dielectric layers225are exposed. In some embodiments, the etching process is selective and does not remove the memory material layers223, the channel material layers224and the gate dielectric layers225. In some embodiments, the trench openings234vertically extend through insulation layers232to expose the etch stop layer160or the conductive lines148. The performed etching process may selectively remove the materials of the insulation layers232and stop at the etch stop layer160or the conductive lines148. The trench openings234may be formed using the same or similar processes for the previous trenches, and thus details are not repeated herein. As illustrated inFIG.19, since the trench openings234penetrate through the insulation layers232to expose the etch stop layer160or the conductive lines148, the remained insulation blocks232A vertically extend along the dielectric blocks230to reach the etch stop layer160or the conductive lines148. InFIG.19, the insulation blocks232A are separate from one another with a distance, and each dielectric block230is sandwiched between two insulation blocks232A in the corresponding trench to form a mask pattern MP1.

Referring toFIG.20, using the mask patterns MP1 (the combination of dielectric blocks230and the insulation blocks232A) as the etching masks, the exposed gate dielectric layers225are selectively removed by a selective etching process. In some embodiments, the selective etching process selectively removes the exposed gate dielectric layers225and does not remove the adjacent channel material layers224and memory material layers223. In some embodiments, the remained gate dielectric layers225A do not extend beyond the mask patterns MP1 along the extending direction (second direction D2). That is, the extending length of the gate dielectric layer225A is substantially the same as the total lengths of the mask pattern MP1 along the trench extending direction (second direction D2). In some embodiments, by selectively removing the exposed gate dielectric layer225, the trench openings234are enlarged to become the trench openings234′, the channel material layers224are exposed, and the trench openings234′ are located between the opposing channel material layers224.

Referring toFIG.21, insulation layers236are formed to fill up the trench openings234′ and are in contact with the exposed channel material layers224. For example, the formation of the insulation layers236involves forming an insulating material over the stacks2021and filling up the enlarged trench openings234′ and performing a planarization process to remove the extra insulating material outside the trench openings234′. In some embodiments, the material for forming the insulation layer236includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon carbonitride, or the combination thereof. In one embodiment, the insulating material of the insulation layers236includes silicon nitride. In some embodiments, the insulation layers236are formed by any compatible formation method, such as coating, CVD, PVD, ALD or the like. In some embodiments, the insulation layers236filled in the trench openings234′ are located between the insulation blocks232A and between the channel material layers224. The insulation layers236and the insulation blocks232A vertically (along the third direction D3) penetrate through the stacks2021and the bottommost first dielectric layer203to reach the etch stop layer160or further through the etch stop layer160to reach the conductive lines148. As shown inFIG.21, two separate gate dielectric layers225A are located on two opposing sidewalls of the insulation block232A.

Referring toFIG.22, an etching process is performed to the insulation layers236to form trench openings238in the insulation layers236, and the channel material layers224are exposed by the trench openings238. In some embodiments, the etching process is selective and does not remove the memory material layers223, the channel material layers224and the gate dielectric layers225A. In some embodiments, the trench openings238vertically extend through insulation layers236to expose the etch stop layer160. The performed etching process may selectively remove the materials of the insulation layers236and stop at the etch stop layer160. The trench openings238may be formed using the same or similar processes for the previous trenches, and thus details are not repeated herein. As illustrated inFIG.22, since the trench openings238penetrate through the insulation layers236to expose the etch stop layer160, the remained insulation blocks236A vertically extend along the dielectric blocks230and the insulation blocks232A to reach the etch stop layer160. InFIG.22, the insulation blocks236A are separate from one another with a distance. The blocks232A/230/232A (i.e. mask pattern MP1) and the gate dielectric layers225A located at their both sides are sandwiched by two insulation blocks236A to form a mask pattern MP2.

Referring toFIG.23, using the mask patterns MP2 as the etching masks, the exposed channel material layer224are removed by a selective etching process. In some embodiments, the selective etching process selectively removes the exposed channel material layer224and does not remove or damage the adjacent conductive features220and the first dielectric layers203. In some embodiments, the remained channel material layers224A do not extend beyond the mask patterns MP2 along the extending direction (second direction D2). That is, the extending length of the channel material layer(s)224A is substantially the same as the total lengths of the mask pattern MP2 along the trench extending direction (second direction D2). In some embodiments, by selectively removing the exposed channel material layer224, the trench openings238are enlarged to become the trench openings238′, sidewalls of the conductive features220and the first dielectric layers203are exposed from the openings238′, and the trench openings238′ are located between the opposing conductive features220. In alternative embodiments, the exposed memory material layers223are removed by a selective etching process using the mask patterns MP2 as the etching masks. In such embodiments, the remained memory material layers223do not extend beyond the mask patterns MP2 along the extending direction.

Referring toFIG.24, dielectric layers240are formed to fill up the trench openings238′ and the sidewall recesses239, so that the dielectric layers240are in direct contact with the remained conductive features220as well as in direct contact with the memory material layers223, channel material layers224A and insulation blocks236A. For example, the formation of the dielectric layers240involves forming a dielectric material over the stacks2021and filling up the enlarged trench openings238′ and the sidewall recesses239and performing a planarization process to remove the extra dielectric material outside the trench openings238′. In some embodiments, the material for forming the dielectric layers240includes silicon oxide, or one or more low-k dielectric materials or extra low-k (ELK) dielectric materials. In one embodiment, the low-k dielectric material has a dielectric constant of about less than 3.9. Examples of low-k or ELK dielectric materials include silicate glass such as fluoro-silicate-glass (FSG), phospho-silicate-glass (PSG) and boro-phospho-silicate-glass (BPSG), BLACK DIAMOND®, SILK®, FLARE®, hydrogen silsesquioxane (HSQ), fluorinated silicon oxide (SiOF), amorphous fluorinated carbon, parylene, BCB (bis-benzocyclobutenes), or a combination thereof. In one embodiment, the material of the dielectric layers240includes silicon oxide or SiOF. In some embodiments, the dielectric layers240are formed by any compatible formation method, such as coating, CVD, PVD, ALD or the like. InFIG.24, the dielectric layers240extend vertically through the stacks2021and the bottommost first dielectric layer203to reach the etch stop layer160. In some embodiments, the dielectric layers240function as isolators for cell units.

Referring toFIG.25, an etching process is performed to remove the insulation blocks236A and232A to form trench openings242,244. In some embodiments, the openings242,244are formed at locations where bits lines and source lines are to be formed, e.g., using suitable photolithography and etching techniques. InFIG.25, the gate dielectric layers225A, the channel material layers224A and the dielectric blocks230are exposed by the trench openings242,244. In some embodiments, the etching process is selective and does not remove the gate dielectric layers225A, the channel material layers224A and the dielectric blocks230. In some embodiments, the trench openings242vertically extend through the stacks2021and the bottommost first dielectric layer203(and the etch stop layer160) to expose the etch stop layer160, and the trench openings244vertically extend through the stacks2021, the bottommost first dielectric layer203and the etch stop layer160to expose the conductive lines148. The performed etching process may selectively remove the materials of the insulation blocks236A and232A and stop at the etch stop layer160or the conductive lines148. In some embodiments, the openings242do not extend through the etch stop layer160, in which case the later-formed source lines and/or bit lines are connected to electrically conductive features overlying the memory device. In some embodiments, the openings244extend through the etch stop layer160, which may allow the subsequently formed source lines and/or bit lines to directly connect to the conductive lines148. In some embodiments, the memory material layer223, the channel material layer224A, the gate dielectric layer225A and the dielectric block230are located between two dielectric layers240and the openings242,244are defined.

Referring toFIG.26, conductive pillars252and254are formed filling up the trench openings242and244respectively. In some embodiments, the conductive pillars252and254respectively functioning as the source and drain terminals. In some embodiments, the conductive pillars252are source lines (e.g., local source lines) and the conductive pillars254are bit lines (e.g., local bit lines). In some other embodiments, the conductive pillars252are bit lines (e.g., local bit lines) and the conductive pillars254are source lines (e.g., local source lines). In some embodiments, the source lines and the bit lines are conductive pillars filled in the trench openings242and244. In some embodiments, the conductive pillars254penetrate through the etch stop layer160to be in physical contact with the conductive lines148, so as to electrically connect to the conductive lines148. In some embodiments, the conductive pillars254are electrically connected to the underlying FEOL circuits or devices through the conductive lines148and the conductive vias144.

In some embodiments, the formation of the conductive pillars252and254involves forming an electrically conductive material (not shown) over the stacks and filling up the openings242and244, and then the extra outside the openings is removed by performing a planarization process (such as CMP), an etching-back process, or other suitable processes. In some embodiments, the conductive materials of the conductive pillars252and254include one or more materials selected from tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), tantalum (Ta), titanium (Ti), copper, alloys thereof, and nitrides thereof, for example. In some embodiments, the formation of the conductive conductive material includes forming seed/barrier materials and performing a plating process (such as electrochemical plating (ECP)) or CVD processes. In some embodiments, the barrier material includes titanium nitride (TiN) formed by the metal organic CVD (MOCVD) process, the seed material includes tungsten formed by CVD, and the conductive material includes tungsten formed by the CVD process (especially tungsten CVD processes).

In some embodiments, the conductive pillars252and254are connected with the gate dielectric layers225A, the conductive pillars252extend from a first surface (e.g., a top surface)2021ato a second surface (e.g., a bottom surface)2021bopposite to the first surface2021aof the stacks2021and reach the etch stop layer160. The conductive pillars254may extend from the first surface (e.g., a top surface)2021ato the second surface (e.g., a bottom surface)2021bof the stacks and further extend into the etch stop layer160, so as to reach the conductive lines148. In some embodiments, sidewalls of the conductive pillars254are in direct contact with the etch stop layer160. In some embodiments, the conductive pillars252and254extend along and through the channel material layers224A, and extend along and through the gate dielectric layers225A. In one embodiment, the conductive pillars252and254also extend through the memory material layer223. In some embodiments, a width W2 (shown inFIG.28) of the conductive pillar254in the bottommost first dielectric layer203is substantially the same as a width W1 of the conductive pillar254in the etch stop layer160.

From the enlarged partial 3D view of a portion (enclosed by the dotted line to represent a cell unit) of the structure as shown at the right side ofFIG.26, it is seen that each memory cell TT includes a transistor with a memory material layer/film. For each transistor of the memory cell, the conductive feature(s)220(the word line) functions as the gate electrode of the transistor, and the conductive pillars252,254(the source line and the bit line) function as the source/drain regions of the transistor, and the channel material layer224A functions as the channel layer of the transistor. For each transistor, the dielectric block230disposed between the source/bit lines252and254functions as an isolation region. In some embodiments, the memory material layer223and the channel material layer224A are sandwiched between and isolated by the two dielectric layers240, and the memory material layer223works as the memory layer of the memory cell TT. That is, the memory material layer223is used to store the digital information (e.g., a bit “1” or “0”) stored in the memory cell TT. From the top view ofFIG.26, the memory cells of the 3D memory device in different trenches are staggered, such that the memory cells in neighboring trenches are disposed along different rows, or the memory cells in alternating trenches are laterally aligned along the first direction D1. The memory material layer223, the channel material layer224A and the dielectric layer225A extend along the conductive pillars252,254.

As shown inFIG.26, each of the conductive pillars252and254(e.g. source lines/bit lines254/252) has a T-shaped cross-section in the top planar view. Due to the relative configurations of the gate dielectric layer225A and the channel material layer224A, the conductive pillars252and254respectively have confined regions252A and254A that are defined between the gate dielectric layers225A and the dielectric block230and extend along the opposing sidewalls of the gate dielectric layers225A and the sidewalls of the dielectric block230. In some embodiments, the configuration of the gate dielectric layers225A allow the other regions of the conductive pillars252and254to contact the channel material layers224A, but keeps the confined regions252A and254A separated from the channel material layers224A that work as channel regions. As such, the confined regions252A and254A act as back gates without shorting the channel regions. In the embodiments, the memory material layers223and the channel material layers224A of the transistors are disposed between the back gates and the word lines for the transistors. During a write operation (e.g., an erase or programming operation) for a transistor, the back gates can help reduce the surface potential of the channel material layers, which further improves the performance of the memory array.

Referring toFIG.27andFIG.28, conductive vias260and conductive lines262are formed over the stacks2021to electrically connect the conductive pillars252. In some embodiments, the conductive vias260are formed in a dielectric layer261, and the conductive lines262are formed on the dielectric layer261to electrically connect to the conductive vias260. In some embodiments, the conductive lines262and the conductive lines148are formed at opposite sides of the stacks2021. In some embodiments, the conductive lines262are source lines (e.g., global source lines) and the conductive lines148are bit lines (e.g., global bit lines). In some other embodiments, the conductive lines262are bit lines (e.g., global bit lines) and the conductive lines148are source lines (e.g., global source lines). In some embodiments, the conductive lines262extend along the first direction D1 and arranged in parallel along the second direction D2. The conductive vias260and the conductive lines262may be formed using a single damascene process respectively or a dual damascene process simultaneously. For example, a dielectric layer is patterned utilizing a combination of photolithography and etching techniques to form trenches corresponding to the desired patterns of the conductive vias260and/or the conductive lines262. An optional diffusion barrier and/or optional adhesion layer may be deposited and the trenches may then be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, combinations thereof, or the like, and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, combinations thereof, or the like. In an embodiment, the conductive vias260and/or the conductive lines262are formed by depositing a seed layer of copper or a copper alloy, and filling the trenches by electroplating. A chemical mechanical planarization (CMP) process or the like may be used to remove excess conductive material from a surface of the dielectric layer and to planarize surfaces of the dielectric layer and the conductive lines262for subsequent processing.

In some embodiments, the conductive lines148(e.g., global bit lines) is in physical contact with the etch stop layer160and the conductive vias144. Thus, the conductive pillars254(e.g., local bit lines) on the etching stop layer160may be electrically connected to the underlying FEOL circuits (e.g., conductive lines140) through two layered interconnecting structure (e.g., the conductive lines148and the conductive vias144). In such embodiments, there may be only two masks required for forming bit line routing structure, which reduces the cost and time for manufacturing the memory device.

FIG.29toFIG.31show schematic three-dimensional views of structures produced at various stages of a manufacturing method of a memory device according to some embodiments of the present disclosure.FIG.32is a schematic cross-sectional view showing the structure ofFIG.31along crossline I-I′. The memory device ofFIG.31andFIG.32is similar to the memory device ofFIG.27andFIG.28, and the difference lies in dielectric patterns164A. Referring toFIG.29, in some embodiments, after performing the steps similar toFIG.2toFIG.16, the inner trenches IT are formed as having a width W2 (along the first direction DO smaller than a width W1 of the dielectric patterns164. Then, the dielectric layers226are filled in the inner trenches IT.

Referring toFIG.30, an etching process is performed to the dielectric layers226to form trench openings228in the dielectric layers226. In some embodiments, the trench openings228have the width W2 smaller than the width W1 of the dielectric patterns164, and thus the trench openings228expose portions of the dielectric patterns164. The etching process removes portions of the exposed dielectric patterns164. InFIG.30, after the etching process, portions of the dielectric patterns164covered by the memory material layer223, the channel material layer224, the gate dielectric layer225and the bottommost first dielectric layer203(and the stacks2021) remain and become respectively the dielectric patterns164A. As shown inFIG.30, the dielectric patterns164A are exposed to the trench openings228, and inner sidewalls ISW3 of the dielectric patterns164A are substantially flush with inner sidewalls ISW2 of the memory material layer223, the channel material layer224, the gate dielectric layer225and the bottommost first dielectric layer203.

Referring toFIG.31andFIG.32, after performing the steps similar toFIG.18toFIG.26, the memory device is formed. In some embodiments, as shown inFIG.31andFIG.32, the conductive pillars254extend into the etch stop layer160, and the dielectric patterns164A are disposed on opposite sidewalls of the conductive pillars254. For example, the dielectric patterns164A surround the conductive pillars254. In some embodiments, sidewalls of the conductive pillars254are separated from the etch stop layer160by the dielectric patterns164A. For example, the dielectric patterns164A are in physical contact with the etch stop layer160and the conductive pillars254. In some embodiments, as shown inFIG.32, a width W2 of the conductive pillar254in the bottommost first dielectric layer203is substantially the same as a width W1 of the conductive pillar254between the dielectric patterns164A in the etch stop layer160.

FIG.33toFIG.35show schematic three-dimensional views of structures produced at various stages of a manufacturing method of a memory device according to some embodiments of the present disclosure.FIG.36is a schematic cross-sectional view showing the structure ofFIG.35along crossline I-I′. The memory device ofFIG.35andFIG.36is similar to the memory device ofFIG.27andFIG.28, and the difference lies in configurations of the conductive pillars254. Referring toFIG.33, in some embodiments, after performing the steps similar toFIG.2toFIG.16, the inner trenches IT are formed as having a width W2 (along the first direction DO larger than a width W1 of the dielectric patterns164. Then, the dielectric layers226are filled in the inner trenches IT.

Referring toFIG.34, an etching process is performed to the dielectric layers226to form trench openings228in the dielectric layers226. In some embodiments, the trench openings228have the width W2 larger than the width W1 of the dielectric patterns164, and thus the trench openings228expose the dielectric patterns164entirely. The etching process removes the exposed dielectric patterns164. InFIG.34, after the etching process, the trench openings228extend into the etch stop layer160, and the trench openings228further have a width W1 formed by removing the dielectric patterns164.

Referring toFIG.35andFIG.36, after performing the steps similar toFIG.18toFIG.26on the structure ofFIG.34, the memory device is formed. In some embodiments, as shown inFIG.35andFIG.36, the conductive pillars254extend into the etch stop layer160and are in physical contact with the etch stop layer160. In some embodiments, as shown inFIG.32, a width W2 of the conductive pillar254in the bottommost first dielectric layer203is larger than a width W1 of the conductive pillar254in the etch stop layer160.

FIG.37toFIG.39show schematic three-dimensional views of structures produced at various stages of a manufacturing method of a memory device according to some embodiments of the present disclosure.FIG.40is a schematic cross-sectional view showing the structure ofFIG.39along crossline I-I′. The memory device ofFIG.39andFIG.40is similar to the memory device ofFIG.27andFIG.28, and the difference lies in conductive vias166in the etch stop layer160. Referring toFIG.37, in some embodiments, after forming a plurality of openings162in the etch stop layer160, a plurality of conductive vias166are formed in the openings162respectively. The conductive vias166may be formed using a single damascene process. For example, the etch stop layer160is patterned utilizing a combination of photolithography and etching techniques with a mask to form openings corresponding to the desired patterns of the conductive vias166. The openings may respectively expose the conductive lines140. An optional diffusion barrier and/or optional adhesion layer may be deposited and the openings may then be filled with a conductive material. Suitable materials for the barrier layer include titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, combinations thereof, or the like, and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, combinations thereof, or the like. In an embodiment, the conductive vias166are formed by depositing a seed layer of copper or a copper alloy, and filling the openings by electroplating. A chemical mechanical planarization (CMP) process or the like may be used to remove excess conductive material from a surface of the etch stop layer160and to planarize surfaces of the etch stop layer160and the conductive vias166for subsequent processing. As seen inFIG.4, the conductive vias166are formed with a width W1 (along the first direction) and a height H1 (along the third direction) that is substantially the same as a thickness (along the third direction) of the etch stop layer160. From a top view, the conductive vias166may be circular, square, rectangular or ring-shaped.

Referring toFIG.38, after performing the steps similar toFIG.5toFIG.16on the structure ofFIG.37, an etching process is performed to the dielectric layers226to form trench openings228in the dielectric layers226. In some embodiments, the etching process is selective and does not remove the memory material layers223, the channel material layers224, the gate dielectric layers225and the conductive vias166. In some embodiments, the trench openings228vertically extend through the dielectric layers226and beyond the stack2021and penetrate through the bottommost first dielectric layer203. The etching process stop at the etch stop layer160and the conductive vias166, for example. In some embodiments, the trench openings228have a width W2 substantially the same as the width W1 of the conductive vias166.

Referring toFIG.39andFIG.40, after performing the steps similar toFIG.18toFIG.26, the memory device is formed. In some embodiments, as shown inFIG.39andFIG.40, the conductive pillars254are in physical contact with the conductive vias166in the etch stop layer160, so as to electrically connected to the conductive vias166. As shown inFIG.39andFIG.40, an interface exists between the conductive pillars254and the conductive vias166. In some embodiments, the conductive pillars254is electrically connected to the underlying FEOL circuits (e.g., conductive lines140) through the conductive vias166, the conductive lines148and the conductive vias144. In some embodiments, lower portions of the conductive pillars254have a width W2 substantially the same as the width W1 of the conductive vias166. However, the disclosure is not limited thereto. In alternative embodiments, lower portions of the conductive pillars254may have a width W2 larger than the width W1 of the conductive vias166(as shown inFIG.41) or a width W2 smaller than the width W1 of the conductive vias166(as shown inFIG.42).

FIG.43illustrates a method of forming a memory device in accordance with some embodiments. Although the method is illustrated and/or described as a series of acts or events, it will be appreciated that the method is not limited to the illustrated ordering or acts. Thus, in some embodiments, the acts may be carried out in different orders than illustrated, and/or may be carried out concurrently. Further, in some embodiments, the illustrated acts or events may be subdivided into multiple acts or events, which may be carried out at separate times or concurrently with other acts or sub-acts. In some embodiments, some illustrated acts or events may be omitted, and other un-illustrated acts or events may be included.

At act S300, a first conductive line is formed on a first conductive via.FIG.3illustrates a view corresponding to some embodiments of act S300.

At act S302, an etch stop layer is formed on the first conductive line, wherein the etch stop layer is in physical contact with the first conductive line.FIG.4illustrates a view corresponding to some embodiments of act S302.

At act S304, a plurality of stacks are formed on the etch stop layer.FIG.5illustrates a view corresponding to some embodiments of act S304.

At act S306, a first conductive pillar is formed between the stacks, wherein the first conductive pillar extends from a first surface to a second surface opposite to the first surface of the stacks, to electrically connect to the first conductive line.FIG.6toFIG.27,FIG.29toFIG.32,FIG.33toFIG.36,FIG.37toFIG.40,FIG.41andFIG.42illustrate varying views corresponding to some embodiments of act S306.

In accordance with some embodiments of the disclosure, a memory device includes a first conductive via, a first conductive line, an etch stop layer, a plurality of stacks and a first conductive pillar. The first conductive line is disposed on and in physical contact with the first conductive via. The etch stop layer is disposed on and in physical contact with the first conductive line. The stacks are disposed on the etch stop layer. The first conductive pillar are disposed between the stacks. The first conductive pillar extends between opposite surfaces of the stacks to be in physical contact with the first conductive line.

In accordance with some embodiments of the disclosure, a memory device includes a first conductive via, a first conductive line, an etch stop layer, a second conductive via, a plurality of stacks and a first conductive pillar. The first conductive line is disposed on the first conductive via. The etch stop layer is disposed on the first conductive line. The second conductive via is disposed in the etch stop layer. The stacks are disposed on the etch stop layer. The first conductive pillar is disposed between the stacks. The first conductive pillar is electrically connected to the first conductive line through the second conductive via, and an interface exists between the first conductive pillar and the second conductive via.

In accordance with some embodiments of the disclosure, a method of forming a memory device includes the following steps. A first conductive line is formed on a first conductive via. An etch stop layer is formed on the first conductive line, wherein the etch stop layer is in physical contact with the first conductive line. A plurality of stacks are disposed on the etch stop layer. A first conductive pillar is disposed between the stacks, wherein the first conductive pillar extends from a first surface to a second surface opposite to the first surface of the stacks, to electrically connect to the first conductive line.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.