Patent ID: 12253895

DETAILED DESCRIPTION

In the present disclosure, “connected” or “coupled” may refer to “electrically connected” or “electrically coupled.” “Connected” or “coupled” may also refer to operations or actions between two or more elements.

Reference is made toFIG.1.FIG.1is a schematic diagram of an electronic system100capable of determining a reason of a cold boot event according to some embodiments of the present disclosure.

In some embodiments, the electronic system100is a server, a smart phone, a desktop computer, a laptop computer, a smart phone, or a smart TV, but the present disclosure is not limited thereto. Various electronic devices or various electronic systems are within the contemplated scopes of the present disclosure.

As illustrated inFIG.1, the electronic system100includes a main chip110, a clock circuit120, a non-volatile storage circuit130, a detector circuit140, a display panel150, a power supply circuit160, and a voltage converter circuit170.

In some embodiments, the main chip110can be implemented by a Central Processing Unit (CPU) or other circuits capable of processing data or controlling. The main chip110is mainly used to control overall operations of the electronic system100. For example, the main chip110can control the clock circuit120, the non-volatile storage circuit130, the detector circuit140, and the display panel150. In some embodiments, the clock circuit120can be implemented by a Real-Time Clock (RTC) circuit or other circuits capable of outputting real time. In some embodiments, the non-volatile storage circuit130can be implemented by a flash memory or other non-volatile storage elements. In some embodiments, the display panel150can be implemented by a display screen, a touch and display screen, or other elements with displaying functions. In some embodiments, the power supply circuit160and the voltage converter circuit170can be implemented by Application Specific Integrated Circuit (ASICs). In some embodiments, the power supply circuit160can be an adaptor or other circuits capable of providing power. In some embodiments, the voltage converter circuit170can be a buck converter. The power supply circuit160is used to output a voltage V1(e.g., 5 volts) and the voltage converter circuit170is used to convert the voltage V1into a lower voltage V2(e.g., 3.3 volts) less than the voltage V1. The voltage V1and the voltage V2can be inputted into the electronic system100such that some circuits or elements in the electronic system100can operate normally.

Regarding coupling relationship, the main chip110is coupled to the clock circuit120, the non-volatile storage circuit130, the detector circuit140, and the display panel150. In the example ofFIG.1, the clock circuit120is disposed outside the main chip110. In some embodiments, the main chip110and the clock circuit120are coupled to each other through the Inter-Integrated Circuit bus (I2C) bus. In some embodiments, the main chip110and the detector circuit140are coupled to each other through General Purpose Input/Output (GPIO) pins. As illustrated inFIG.1, the detector circuit140includes an input terminal IN, an output terminal OUT1, and an output terminal OUT2. The input terminal IN, the output terminal OUT1, and the output terminal OUT2conform the GPIO standard. The input terminal IN, the output terminal OUT1, and the output terminal OUT2can be coupled to the main chip110.

Regarding operating, the clock circuit120can output real time as a clock. The main chip110can read the real time outputted from the clock circuit120, and the main chip110can store it into the non-volatile storage circuit130. For example, the main chip110reads time T1outputted from the clock circuit120with a fixed period (e.g., 1 second) and stores the time T1into the non-volatile storage circuit130. Since the non-volatile storage circuit130is non-volatile, the data stored in the non-volatile storage circuit130will not disappear even if a clod boot event occurs. Accordingly, the main chip110can determine a reason of the clod boot event according to the time T1stored in the non-volatile storage circuit130, time T2after the clod boot event, and a logic value at the output terminal OUT1.

The details about how the main chip110determines the reason of the clod boot event are described in following paragraphs.

Reference is made toFIG.2.FIG.2is a flow diagram of a determination method200capable of determining the reason of the cold boot event according to some embodiments of the present disclosure.

In some embodiments, the determination method200can be applied to the electronic system100inFIG.1, but the present disclosure is not limited thereto. However, for better understanding, the determination method200is described with reference toFIG.1in following paragraphs.

As illustrated inFIG.2, the determination method200includes operations S210, S220, S230, S240, S250, S260, S270, S280, and S290.

In operation S210, a clod boot event occurs. For example, the clod boot event occurs in the electronic system100when the electronic system100is normally turned on after being turned off normally, when the mains power is restored after the mains power is stopped, when a user inserts a plug again after unplugging it by mistake, when a user presses a reset key on the hardware, or when the power supply circuit160fails in a short time duration (the power supply circuit160is unstable or the power supply circuit160provides insufficient power).

In operation S220, the main chip110reads the time T1stored in the non-volatile storage circuit130. In some embodiments, the time T1is the last time the main chip110reads from the clock circuit120before the cold boot event. As describe above, since the non-volatile storage circuit130is non-volatile, the time T1stored in the non-volatile storage circuit130will not disappear even if a cold boot event occurs in the electronic system100.

In operation S230, the main chip110determines whether the reason of the cold boot event is a normal power-off event. For example, there is flag information corresponding to the normal power-off event in the non-volatile storage circuit130when a user shuts down the electronic system100normally (the normal power-off event). On the contrary, there is no flag information corresponding to the normal power-off event in the non-volatile storage circuit130when the mains power is stopped, when a user unplugs a plug by mistake, when a user presses a reset key on the hardware, or when a power supply circuit fails (not normal power-off event). Accordingly, when there is the flag information corresponding to the normal power-off event in non-volatile storage circuit130, the determination method200enters operation S240. In operation S240, the main chip110determines that the reason of the cold boot event is the normal power-off event.

When there is no flag information corresponding to the normal power-off event in non-volatile storage circuit130, the determination method200enters operation S250. In operation S250, the main chip110determines whether a time difference is greater than a threshold time Tth. Since the clock circuit120consumes very little power (almost no power), the clock circuit120can continue to operate during the aforementioned condition (e.g., there is a capacitor or other power storage element in the clock circuit120to provide power required by the clock circuit120). Accordingly, after the cold boot event, the main chip110can read the time T2from the clock circuit120. Then, the main chip110can calculate the time difference between the time T2and the time T1, and can determine whether the time difference between the time T2and the time T1is greater than the threshold time Tth. In some embodiments, it is assumed that the main chip110reads the time outputted from the clock circuit120with a fixed period of M seconds (e.g., 1 second). In addition, it is assumed that it takes N seconds (e.g., 3 seconds) from the timing when the cold event occurs to the timing when the main chip110reads out the time stored in non-volatile storage circuit130. The threshold time Tth is (M+N) seconds (e.g., 4 seconds).

When the main chip110determines that the time difference between the time T2and the time T1is greater than the threshold time Tth, the determination method200enters operation S260. In operation S260, the main chip110determines that the reason of the cold boot event is an abnormal power-off event (the mains power is stopped or a user unplugs a plug by mistake). In general, when the mains power is stopped or a user unplugs a plug by mistake, the power interruption period will not be too short (e.g., not shorter than 4 seconds). Thus. when the time difference between the time T2and the time T1is greater than the threshold time Tth, the main chip110can determine that the reason of the cold boot event is the abnormal power-off event (the mains power is stopped or a user unplugs a plug by mistake).

When the main chip110determines that the time difference between the time T2and the time T1is less than or equal to the threshold time Tth, the determination method200enters S270. In operation S270, the main chip110determines whether the output terminal OUT1the detector circuit140has a low logic value so as to determine whether the reason of the cold boot event is a power failure event (the power supply circuit160is unstable or the power supply circuit160provides insufficient power) or a reset-key event (a user presses a reset key on the hardware).

The details about the detector circuit140are described in following paragraphs. It takes a low logic value as logic value 0 and a high logic value as logic value 1 as an example.

Reference is made toFIG.3.FIG.3is a schematic diagram of the detector circuit140according to some embodiments of the present disclosure.

As illustrated inFIG.3, the detector circuit140includes a backup voltage establishment circuit142, a voltage divider circuit143, a comparator circuit144, a resistor-capacitor circuit145, a latch circuit146, and a voltage divider circuit147.

The backup voltage establishment circuit142is used to establish a backup voltage VBAK (e.g., 3 volts) according to the voltage V2(e.g., 3.3 volts). As illustrated inFIG.3, the backup voltage establishment circuit142includes a diode D1and a capacitor C1. An anode terminal of the diode D1is used to receive the voltage V2, a cathode terminal of the diode D1couples a first terminal of the capacitor C1at a node N1, and a second terminal of the capacitor C1is coupled to a ground terminal GND. When the diode D1is turned on, the backup voltage VBAK is generated at the node N1in response to the voltage V2.

The voltage divider circuit143is used to generate a voltage-divided voltage VD according to the voltage V1. As illustrated inFIG.3, the voltage divider circuit143includes a resistor R1and a resistor R2. A first terminal of the resistor R1is used to receive the voltage V1, a second terminal of the resistor R1couples a first terminal of the resistor R2at node N2, and a second terminal of the resistor R2is coupled to the ground terminal GND. Based on a resistance ratio of the resistor R1and the resistor R2, the voltage-divided voltage VD is generated at the node N2in response to the voltage V1. When the voltage V1is fully supplied, the voltage-divided voltage VD is greater than the backup voltage VBAK.

The comparator circuit144is used to compare the backup voltage VBAK with the voltage-divided voltage VD to generate a comparison voltage VC. In some embodiments, the comparator circuit144is implemented by a comparator. As illustrated inFIG.3, the comparator circuit144includes a positive input terminal, a negative input terminal, and an output terminal. The positive input terminal of the comparator circuit144is coupled to the node N1to receive the backup voltage VBAK. The negative input terminal of the comparator circuit144is coupled to the node N2to receive the voltage-divided voltage VD. When the voltage-divided voltage VD is greater than or equal to the backup voltage VBAK, the comparator circuit144outputs the comparison voltage VC with a low logic value. When the voltage-divided voltage VD is less than the backup voltage VBAK, the comparator circuit144outputs the comparison voltage VC with a high logic value.

The resistor-capacitor circuit145is used to generate a set voltage VS according to the comparison voltage VC. As illustrated inFIG.3, the resistor-capacitor circuit145includes a resistor R3and a capacitor C2. A first terminal of the resistor R3is used to receive the comparison voltage VC, a second terminal of the resistor R3couples a first terminal of the capacitor C2at a node N3, and a second terminal of the capacitor C2is coupled to the ground terminal GND. Based on a time constant of the resistor-capacitor circuit145, the set voltage VS is generated at the node N3in response to the comparison voltage VC.

The latch circuit146is used to generate a latch signal Q and an inversion latch signal Q′ according to the set voltage VS and a reset voltage VR. In the embodiment ofFIG.3, the latch circuit146is a SR latch, but the present disclosure is not limited thereto. As illustrated inFIG.3, the latch circuit146includes a NOR gate1461and a NOR gate1462. A first input terminal of the NOR gate1461is coupled to the node N3to receive the set voltage VS, a second input terminal of the NOR gate1461is coupled to an output terminal of the NOR gate1462, and an output terminal of the NOR gate1461is coupled to a capacitor C3. An output terminal of the NOR gate1461is the output terminal OUT1of the detector circuit140, and the output terminal OUT1is used to output the inversion latch signal Q′. A first input terminal of the NOR gate1462is coupled to the output terminal of the NOR gate1461, a second input terminal of the NOR gate1462is coupled to a node N4to receive the reset voltage VR. An output terminal of the NOR gate1462is the output terminal OUT2of the detector circuit140, and the output terminal OUT2is used to output the latch signal Q.

The voltage divider circuit147is used to generate the reset voltage VR according to a reset signal CM from the main chip110. As illustrated inFIG.3, the voltage divider circuit147includes a resistor R4and a resistor R5. A first terminal of the resistor R4is coupled to the input terminal IN to receive the reset signal CM from the main chip110, a second terminal of the resistor R4couples a first terminal of the resistor R5at the node N4, and a second terminal of the resistor R5is coupled to the ground terminal GND. Based on a resistance ratio of the resistor R4and the resistor R5, the reset voltage VR is generated at the node N4in response to the reset signal CM.

In general, when the power supply circuit160provides power normally, the voltage V1is established earlier than the voltage V2. It is assumed that when the power supply circuit160provides power normally, a maximum voltage of the voltage V1is 5 volts, a maximum voltage of the voltage V2is 3.3 volts, a maximum voltage of the backup voltage VBAK is 3 volts, and a maximum voltage of the voltage-divided voltage VD is 3.75 volts. When a user presses the reset key on the hardware, the power supply circuit160still provides power normally. In other words, the voltage V1has sufficient power. Under this condition, since the voltage-divided voltage VD at the negative input terminal of the comparator circuit144is greater than the backup voltage VBAK at the positive input terminal of the comparator circuit144, the comparison voltage VC has the low logic value. At this time, the reset signal CM from the main chip110also has the low logic value. Thus, the reset voltage VR has the low logic value. Accordingly, the inversion latch signal Q′ at the output terminal OUT1has the high logic value, and the latch signal Q at the output terminal OUT2has the low logic value.

However, when the power supply circuit160fails (the power supply circuit160is unstable or the power supply circuit160provides insufficient power), the voltage V1is with insufficient power. Under this condition, the voltage-divided voltage VD at the node N2decreases (e.g., less than 3 volts). However, the backup voltage VBAK at the node N1will maintain at its maximum voltage value (e.g., 3 volts) for a period of time due to the power storage characteristic of the capacitor C1and the low power consumption of the overall circuit. Under this condition, since the voltage-divided voltage VD at the negative terminal of the comparator circuit144is less than the backup voltage VBAK at the positive terminal of the comparator circuit144, the comparison voltage VC has the high logic value. At this time, the reset signal CM from the main chip110also has the low logic value. Thus, the reset voltage VR has the low logic value. Accordingly, the inversion latch signal Q′ at the output terminal OUT1has the low logic value, and the latch signal Q at the output terminal OUT2has the high logic value.

Based on principles above, when the output terminal OUT1of the detector circuit140has the high logic value (the determination of operation S270is “NO”), the determination method200enters operation S280. In operation S280, the main chip110determines that the reason of the cold boot event is the reset-key event. When the output terminal OUT1of the detector circuit140has the low logic value (the determination of operation S270is “YES”), the determination method200enters operation S290. In operation S290, the main chip110determines that the reason of the cold boot event is the power failure event.

In some embodiments, when the main chip110determines the reason of the cold boot event, the main chip110can automatically generate an electronic document and the electronic document can record the reason of the cold boot event. The main chip110can optimize the operations of the electronic system100according to this electronic document. In some embodiments, the display panel150can display this electronic document (to display the reason of the cold boot event) for a designer to quickly know the reason of the cold boot event. In some embodiments, there are multiple electronic systems100, and the electronic systems100can send the reasons of the cold boot events to a server respectively. This server can analyze the data sent from the electronic systems100to determine the environment condition (whether the mains power is stable) of the electronic systems100or determine quality of the power supply circuit (whether the power supply circuit160is stable) so as to optimize the operations of the electronic systems100according to the determination.

In some embodiments, when the main chip110determines that the reason of the cold boot event, the main chip110can send the reset signal CM with the high logic value to reset the latch circuit146. For example, the main chip110can send the reset signal CM with the high logic value to generate a reset voltage VR with the high logic value at the node N4to reset the latch circuit146. When the latch circuit146is reset, the detector circuit140is able to determine the reason of a next cold boot event.

In some related approaches, an external microcontroller and an additional power supply for providing power to the external microcontroller are disposed to monitor the electronic system (e.g., recording the cold boot event and determining the reason of the cold boot event). However, the cost will increase due to the external microcontroller and the additional power supply.

Compared to the aforementioned related approaches, in the present disclosure, the main chip110(for controlling overall operations of the electronic system100) is utilized to work with the detector circuit140to determine the reason of the cold boot event. Since the present disclosure does not need the external microcontroller and the additional power supply for providing power to the external microcontroller, the present disclosure can lower the cost. In addition, compared to the external microcontroller and the additional power supply for providing power to the external microcontroller, the cost of the components in the detector circuit140is low, so the present disclosure has the advantage of low cost. Further, since the current of the detector circuit140is smaller, the present disclosure has the advantage of low power consumption and does not need to dispose other power supplies.

It takes the main chip110to read the output terminal OUT1of the detector circuit140in operation S270in the aforementioned embodiments above, but the present disclosure is not limited thereto. In some other embodiments, the main chip110can read the output terminal OUT2of the detector circuit140. When the output terminal OUT2of the detector circuit140has the high logic value, the main chip110determines that the reason of the cold boot event is the power failure event. When the output terminal OUT2of the detector circuit140has the low logic value, the main chip110determines that the reason of the cold boot event is the reset-key event. However, when the power failure event occurs, compared to reading the output terminal OUT2, reading the output terminal OUT1has the advantage of less power consumption. The reason is that the output terminal OUT1outputs the inversion latch signal Q′ with the low logic value when the power failure event occurs. The inversion latch signal Q′ with the low logic value is driven by a lower side transistor in the NOR gate1461according to a ground voltage at the ground terminal GND. Thus, this method has lower power consumption.

Reference is made toFIG.4.FIG.4is a schematic diagram of an electronic system400capable of determining a reason of a cold boot event according to some embodiments of the present disclosure.

The electronic system400inFIG.4is similar to the electronic system100inFIG.1. One of major differences between the electronic system400and the electronic system100is that a clock circuit420is disposed in a main chip410. The structure inFIG.4is simpler. Since operations of the electronic system400are similar to those of the electronic system100, they are nor described herein again.

As described above, in the present disclosure, the main chip can work with the detector circuit to determine the reason of the cold boot event. Thus, there is no need to dispose an external microcontroller and an additional power supply providing power to the external microcontroller in the present disclosure. Thus, the present disclosure can lower the cost.

Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein. It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims.