Patent ID: 12205846

DETAILED DESCRIPTION

The following description provides specific details, such as material compositions, shapes, and sizes, in order to provide a thorough description of embodiments of the disclosure. However, a person of ordinary skill in the art would understand that the embodiments of the disclosure may be practiced without employing these specific details. Indeed, the embodiments of the disclosure may be practiced in conjunction with conventional microelectronic device fabrication techniques employed in the industry. In addition, the description provided below does not form a complete process flow for manufacturing a microelectronic device (e.g., a memory device, such as 3D NAND Flash memory device). The structures described below do not form a complete microelectronic device. Only those process acts and structures necessary to understand the embodiments of the disclosure are described in detail below. Additional acts to form a complete microelectronic device from the structures may be performed by conventional fabrication techniques.

Drawings presented herein are for illustrative purposes only, and are not meant to be actual views of any particular material, component, structure, device, or system. Variations from the shapes depicted in the drawings as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes or regions as illustrated, but include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as box-shaped may have rough and/or nonlinear features, and a region illustrated or described as round may include some rough and/or linear features. Moreover, sharp angles that are illustrated may be rounded, and vice versa. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of a region and do not limit the scope of the present claims. The drawings are not necessarily to scale. Additionally, elements common between figures may retain the same numerical designation.

As used herein, a “memory device” means and includes microelectronic devices exhibiting memory functionality, but not necessarily limited to memory functionality. Stated another way, and by way of non-limiting example only, the term “memory device” includes not only conventional memory (e.g., conventional volatile memory, such as conventional dynamic random access memory (DRAM); conventional non-volatile memory, such as conventional NAND memory), but also includes an application specific integrated circuit (ASIC) (e.g., a system on a chip (SoC)), a microelectronic device combining logic and memory, and a graphics processing unit (GPU) incorporating memory.

As used herein, the term “configured” refers to a size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one apparatus facilitating operation of one or more of the structure and the apparatus in a predetermined way.

As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” are in reference to a major plane of a structure and are not necessarily defined by earth's gravitational field. A “horizontal” or “lateral” direction is a direction that is substantially parallel to the major plane of the structure, while a “vertical” or “longitudinal” direction is a direction that is substantially perpendicular to the major plane of the structure. The major plane of the structure is defined by a surface of the structure having a relatively large area compared to other surfaces of the structure. With reference to the figures, a “horizontal” or “lateral” direction may be perpendicular to an indicated “Z” axis, and may be parallel to an indicated “X” axis and/or parallel to an indicated “Y” axis; and a “vertical” or “longitudinal” direction may be parallel to an indicated “Z” axis, may be perpendicular to an indicated “X” axis, and may be perpendicular to an indicated “Y” axis.

As used herein, features (e.g., regions, structures, devices) described as “neighboring” one another means and includes features of the disclosed identity (or identities) that are located most proximate (e.g., closest to) one another. Additional features (e.g., additional regions, additional structures, additional devices) not matching the disclosed identity (or identities) of the “neighboring” features may be disposed between the “neighboring” features. Put another way, the “neighboring” features may be positioned directly adjacent one another, such that no other feature intervenes between the “neighboring” features; or the “neighboring” features may be positioned indirectly adjacent one another, such that at least one feature having an identity other than that associated with at least one the “neighboring” features is positioned between the “neighboring” features. Accordingly, features described as “vertically neighboring” one another means and includes features of the disclosed identity (or identities) that are located most vertically proximate (e.g., vertically closest to) one another. Moreover, features described as“horizontally neighboring” one another means and includes features of the disclosed identity (or identities) that are located most horizontally proximate (e.g., horizontally closest to) one another.

As used herein, spatially relative terms, such as “beneath,” “below,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” “right,” and the like, may be used for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Unless otherwise specified, the spatially relative terms are intended to encompass different orientations of the materials in addition to the orientation depicted in the figures. For example, if materials in the figures are inverted, elements described as “below” or “beneath” or “under” or “on bottom of” other elements or features would then be oriented “above” or “on top of” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below, depending on the context in which the term is used, which will be evident to one of ordinary skill in the art. The materials may be otherwise oriented (e.g., rotated 90 degrees, inverted, flipped) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

As used herein, “and/or” includes any and all combinations of one or more of the associated listed items.

As used herein, the phrase “coupled to” refers to structures operatively connected with each other, such as electrically connected through a direct Ohmic connection or through an indirect connection (e.g., by way of another structure).

As used herein, the term “substantially” in reference to a given parameter, property, or condition means and includes to a degree that one of ordinary skill in the art would understand that the given parameter, property, or condition is met with a degree of variance, such as within acceptable tolerances. By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be at least 90.0 percent met, at least 95.0 percent met, at least 99.0 percent met, at least 99.9 percent met, or even 100.0 percent met.

As used herein, “about” or “approximately” in reference to a numerical value for a particular parameter is inclusive of the numerical value and a degree of variance from the numerical value that one of ordinary skill in the art would understand is within acceptable tolerances for the particular parameter. For example, “about” or “approximately” in reference to a numerical value may include additional numerical values within a range of from 90.0 percent to 110.0 percent of the numerical value, such as within a range of from 95.0 percent to 105.0 percent of the numerical value, within a range of from 97.5 percent to 102.5 percent of the numerical value, within a range of from 99.0 percent to 101.0 percent of the numerical value, within a range of from 99.5 percent to 100.5 percent of the numerical value, or within a range of from 99.9 percent to 100.1 percent of the numerical value.

As used herein, “conductive material” means and includes electrically conductive material such as one or more of a metal (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), an alloy (e.g., a Co-based alloy, an Fe-based alloy, an Ni-based alloy, an Fe- and Ni-based alloy, a Co- and Ni-based alloy, an Fe- and Co-based alloy, a Co- and Ni- and Fe-based alloy, an Al-based alloy, a Cu-based alloy, a magnesium (Mg)-based alloy, a Ti-based alloy, a steel, a low-carbon steel, a stainless steel), a conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide), and a conductively-doped semiconductor material (e.g., conductively-doped polysilicon, conductively-doped germanium (Ge), conductively-doped silicon germanium (SiGe)). In addition, a “conductive structure” means and includes a structure formed of and including conductive material.

As used herein, “insulative material” means and includes electrically insulative material, such one or more of at least one dielectric oxide material (e.g., one or more of a silicon oxide (SiOx), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, an aluminum oxide (AlOx), a hafnium oxide (HfOx), a niobium oxide (NbOx), a titanium oxide (TiOx), a zirconium oxide (ZrOx), a tantalum oxide (TaOx), and a magnesium oxide (MgOx)), at least one dielectric nitride material (e.g., a silicon nitride (SiNy)), at least one dielectric oxynitride material (e.g., a silicon oxynitride (SiOxNy)), at least one dielectric oxycarbide material (e.g., silicon oxycarbide (SiOxCy)), at least one hydrogenated dielectric oxycarbide material (e.g., hydrogenated silicon oxycarbide (SiCxOyHz)), and at least one dielectric carboxynitride material (e.g., a silicon carboxynitride (SiOxCzNy)). Formulae including one or more of “x,” “y,” and “z” herein (e.g., SiOx, AlOx, HfOx, NbOx, TiOx, SiNy, SiOxNy, SiOxCy, SiCxOyHz, SiOxCzNy) represent a material that contains an average ratio of “x” atoms of one element, “y” atoms of another element, and “z” atoms of an additional element (if any) for every one atom of another element (e.g., Si, Al, Hf, Nb, Ti). As the formulae are representative of relative atomic ratios and not strict chemical structure, an insulative material may comprise one or more stoichiometric compounds and/or one or more non-stoichiometric compounds, and values of “x,” “y,” and “z” (if any) may be integers or may be non-integers. As used herein, the term “non-stoichiometric compound” means and includes a chemical compound with an elemental composition that cannot be represented by a ratio of well-defined natural numbers and is in violation of the law of definite proportions. In addition, an “insulative structure” means and includes a structure formed of and including insulative material.

Unless the context indicates otherwise, the materials described herein may be formed by any suitable technique including, but not limited to, spin coating, blanket coating, chemical vapor deposition (“CVD”), atomic layer deposition (“ALD”), plasma enhanced ALD, physical vapor deposition (“PVD”) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the technique for depositing or growing the material may be selected by a person of ordinary skill in the art. In addition, unless the context indicates otherwise, removal of materials described herein may be accomplished by any suitable technique including, but not limited to, etching (e.g., dry etching, wet etching, vapor etching), ion milling, abrasive planarization, or other known methods.

FIGS.1A through6Bare simplified partial cross-sectional (i.e.,FIGS.1A,2A,3A,4A,5A, and6A) and simplified partial plan (i.e.,FIGS.1B,2B,3B,4B,5B, and6B) views illustrating embodiments of a method of forming a microelectronic device structure (e.g., a memory device structure) for a microelectronic device (e.g., a memory device, such as a 3D NAND Flash memory device). With the description as provided below, it will be readily apparent to one of ordinary skill in the art that the methods described herein may be used in various applications. In other words, the methods of the disclosure may be used whenever it is desired to form a microelectronic device.

Referring toFIG.1A, a microelectronic device structure100may be formed to include conductive line structures102on or over a base structure101, insulative line structures104on or over the conductive line structures102, and trenches106horizontally alternating (e.g., in the X-direction) with the conductive line structures102(and, hence, the insulative line structures104). The base structure101, the conductive line structures102, the insulative line structures104, and the trenches106are described in further detail below.FIG.1Bis a simplified plan view of the microelectronic device structure100at the process stage depicted inFIG.1A.

The base structure101may comprise a base material or construction upon which additional materials may be formed. The base structure101may be formed of and include one or more of a semiconductive material, a conductive material, and a dielectric material. For example, the base structure101may comprise a semiconductive structure (e.g., a semiconductor substrate); a base semiconductive material on a supporting structure; a conductive structure (e.g., a metal electrode); a dielectric structure; a structure including one or more of different materials, structures, and regions; another base material; or another construction. In some embodiments, the base structure101comprises a stack structure for a memory device (e.g., a 3D NAND Flash memory device), as described in further detail below. The stack structure may, for example, include a vertically alternating sequence of conductive structures and insulative structures arranged in tiers.

The conductive line structures102may exhibit horizontally elongated shapes extending in parallel in a first horizontal direction (e.g., the Y-direction). As used herein, the term “parallel” means substantially parallel. The conductive line structures102may each exhibit substantially the same dimensions (e.g., width in the X-direction, length in a Y-direction, height in the Z-direction), shape, and spacing (e.g., in the X-direction). In additional embodiments, one or more of the conductive line structures102may exhibit one or more of at least one different dimension (e.g., a different length, a different width, a different height) and a different shape than one or more other of the conductive line structures102, and/or the spacing (e.g., in the X-direction) between at least two horizontally neighboring conductive line structures102may be different than the spacing between at least two other horizontally neighboring conductive line structures102. In some embodiments, the conductive line structures102are employed as digit line structures (e.g., data line structures, bit line structures) for a memory device, as described in further detail below.

The conductive line structures102may be formed of and include conductive material. By way of non-limiting example, the conductive line structures102may each individually be formed of and include a metallic material comprising one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, the conductive line structures102are each individually formed of and include W. Each of the conductive line structures102may individually be substantially homogeneous, or one or more of the conductive line structures102may individually be substantially heterogeneous. As used herein, the term “homogeneous” means relative amounts of elements included in a feature (e.g., a structure, a material) do not vary throughout different portions (e.g., different horizontal portions, different vertical portions) of the feature. Conversely, as used herein, the term “heterogeneous” means relative amounts of elements included in a feature (e.g., a material, a structure) vary throughout different portions of the feature. If a conductive line structure102is heterogeneous, amounts of one or more elements included in the conductive line structure102may vary stepwise (e.g., change abruptly), or may vary continuously (e.g., change progressively, such as linearly, parabolically) throughout different portions of the conductive line structure102. In some embodiments, each of the conductive line structures102is substantially homogeneous. In additional embodiments, each of the conductive line structure102is heterogeneous. Each conductive line structure102may, for example, be formed of and include a stack (e.g., laminate) of at least two different conductive materials.

As shown inFIG.1A, the insulative line structures104may vertically overlie (e.g., directly vertically overlie) the conductive line structures102. The insulative line structures104may serve as insulative cap structures (e.g., dielectric cap structures) for the conductive line structures102. The insulative line structures104may have horizontally elongated shapes extending in parallel in the first horizontal direction (e.g., the Y-direction). Horizontal dimensions, horizontal pathing, and horizontal spacing of the insulative line structures104may be substantially the same as the horizontal dimensions, horizontal pathing, and horizontal spacing of the conductive line structures102.

The insulative line structures104may be formed of and include insulative material. By way of non-limiting example, the insulative line structures104may each individually be formed of and include a dielectric nitride material, such as SiNy(e.g., Si3N4). The insulative line structures104may each be substantially homogeneous, or one or more of the insulative line structures104may be heterogeneous. If an insulative line structure104is heterogeneous, amounts of one or more elements included in the insulative line structure104may vary stepwise (e.g., change abruptly), or may vary continuously (e.g., change progressively, such as linearly, parabolically) throughout different portions of the insulative line structure104. In some embodiments, each of the insulative line structures104is substantially homogeneous. In additional embodiments, each of the insulative line structures104is heterogeneous. Each insulative line structures104may, for example, be formed of and include a stack (e.g., laminate) of at least two different dielectric materials.

With continued reference toFIG.1A, the trenches106may horizontally intervene (e.g., in the X-direction) between and separate horizontally neighboring conductive line structures102(and, hence, horizontally neighboring insulative line structures104). The trenches106may extend in parallel in the horizontal direction (e.g., the Y-direction) in which the conductive line structures102extend. In addition, as shown inFIG.1A, the trenches106may vertically extend (e.g., in the Z-direction) from upper vertical boundaries (e.g., upper surfaces) of the insulative line structures104to lower vertical boundaries (e.g., lower surfaces) of the conductive line structures102. Side surfaces of the conductive line structures102and the insulative line structures104may define horizontal boundaries of the trenches106, lower surface of the conductive line structures102may define lower vertical boundaries of the trenches106, and upper surfaces of the insulative line structures104may define upper vertical boundaries of the trenches106.

The conductive line structures102, insulative line structures104, and the trenches106may be formed using conventional processes (e.g., conventional deposition processes, such as one or more of in situ growth, spin-on coating, blanket coating, CVD, PECVD, ALD, and PVD; conventional patterning processes, such as conventional photolithography processes; conventional material removal processes, such as conventional etching processes) and conventional processing equipment, which are not described in detail herein.

Referring next toFIG.2A, an isolation material108may be formed over exposed surfaces of the microelectronic device structure100. The isolation material108may exhibit a substantially planar upper boundary (e.g., upper surface), and a non-planar lower boundary at least partially defined by the topography of the surfaces (e.g., upper surfaces, side surfaces) of the base structure101, the conductive line structures102, and the insulative line structures104. The isolation material108may partially (e.g., less than completely) fill the trenches106(FIGS.1A and1B). Accordingly, as shown inFIG.2A, air gaps110corresponding to portions of the trenches106(FIGS.1A and1B) remaining unfilled with the isolation material108may horizontally intervene (e.g., in the X-direction) between horizontally neighboring conductive line structures102and horizontally neighboring insulative line structures104following the formation of the isolation material108. The air gaps110may serve as an insulator having a dielectric constant (k) of about 1. The air gaps110may limit capacitance (e.g., parasitic capacitance, stray capacitance) and increase shorts margin between horizontally neighboring conductive line structures102, and may reduce cross-talk between horizontally neighboring conductive line structures102.FIG.2Bis a simplified plan view of the microelectronic device structure100at the process stage depicted inFIG.2A.

The isolation material108may be formed of and include at least one insulative material. By way of non-limiting example, the isolation material108may be formed of and include one or more of at least one dielectric oxide material (e.g., one or more of SiOx, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlOx, HfOx, NbOx, and TiOx), at least one dielectric nitride material (e.g., SiNy), at least one dielectric oxynitride material (e.g., SiOxNy), at least one dielectric carboxynitride material (e.g., SiOxCzNy), and amorphous carbon. In some embodiments, the isolation material108is formed of and includes SiOx(e.g., SiO2).

As shown inFIG.2A, the air gaps110may vertically extend (e.g., in the Z-direction) from a location vertically at or vertically below upper vertical boundaries of the insulative line structures104to additional locations vertically at or vertically above lower vertical boundaries of the conductive line structures102. In some embodiments, the air gaps110vertically extend from locations vertically below upper surfaces of the insulative line structures104and vertically above upper surfaces of the conductive line structures102to additional locations vertically above lower surfaces of the conductive line structures102. The air gaps110may each individually be substantially surrounded by (e.g., buried within, embedded within) the isolation material108. In addition, the air gaps110may be positioned about horizontal centerlines (e.g., in the X-direction) of the trenches106(FIG.1A), and may horizontally extend (e.g., in the X-direction) outward from the horizontal centerlines of the trenches106(FIG.1A).

The isolation material108and the air gaps110may be formed using conventional processes (e.g., conventional deposition processes, conventional material removal processes) and conventional processing equipment, which are not described in detail herein. For example, the isolation material108(and, hence, the air gaps110) may be formed on or over portions of the exposed surfaces of the microelectronic device structure100using one or more conventional non-conformal deposition processes (e.g., at least one conventional non-conformal PVD process). Thereafter, the isolation material108may be subjected to at least one conventional planarization process (e.g., at least one conventional CMP process) to facilitate or enhance the planarity of an upper boundary (e.g., upper surface) of the isolation material108. Forming the air gaps110in the manner described above may effectuate a reduction in undesirable capacitive coupling between horizontally neighboring electrically conductive features (e.g., the conductive line structures102) of the microelectronic device structure100, while circumventing undesirable damage to the horizontally neighboring electrically conductive features that may be otherwise occur if the air gaps110were formed through other processes, such as by etching insulative material formed between the conductive line structures102. Thus, forming the air gaps110in manner described above may preserve the integrity of both the horizontally neighboring electrically conductive features and the air gaps110.

Referring next toFIG.3A, portions of the isolation material108vertically overlying the insulative line structures104may be removed (e.g., etched) to expose (e.g., uncover) portions of the insulative line structures104. As shown inFIG.3A, the material removal process may form openings112vertically extending (e.g., in the Z-direction) from an upper surface of the isolation material108to the insulative line structures104. In some embodiments, the material removal process removes predetermined portions of the isolation material108without removing portions of the insulative line structures104. In additional embodiments, the material removal process removes the predetermined portions of the isolation material108and also partially removes portions of the insulative line structures104vertically underlying and horizontally overlapping (e.g., at least partially horizontally aligned with) the predetermined portions of the isolation material108.FIG.3Bis a simplified plan view of the microelectronic device structure100at the process stage depicted inFIG.3A.

As shown inFIG.3B, individual openings112may be at least partially (e.g., substantially) horizontally aligned in the X-direction with individual insulative line structures104(and, hence, individual conductive line structures102(FIG.3A)). For example, horizontal centerlines of the openings112in the X-direction may be substantially aligned with horizontal centerlines of the insulative line structures104in the X-direction. Each opening112may be horizontally positioned between two air gaps110horizontally neighboring one another in the X-direction. In addition, individual openings112may be positioned at desired locations in the Y-direction along the individual insulative line structures104(and, hence, individual conductive line structures102(FIG.3A)). In some embodiments, at least some of the openings112are provided at different positions in the Y-direction than one another. For example, a first of the openings112may be provided at different position along a length in the Y-direction of a first of the insulative line structures104as compared to a position of a second of the openings112along a length in the Y-direction of a second of the insulative line structures104. Put another way, at least some (e.g., all) of the openings112may be horizontally offset from one another in the Y-direction. In additional embodiments, two or more of the openings112are horizontally aligned with one another in the Y-direction.

The openings112may each individually be formed to exhibit geometric configurations (e.g., dimensions, shapes) facilitating desired geometric configurations of additional features (e.g., additional structures, additional materials) to subsequently be formed therein. As shown inFIG.3B, in some embodiments, individual openings112are formed to be relatively wider in the X-direction than individual insulative line structures104(and, hence, individual conductive line structures102(FIG.3A)) vertically thereunder. For example, each opening112may horizontally extend in the X-direction beyond horizontal boundaries in the X-direction of the insulative line structure104associated therewith (e.g., exposed thereby). In some embodiments, a width in the X-direction of each opening112is up to two times (2×) a width in the X-direction of the insulative line structure104associated therewith, such as within a range of from about one and one quarter times (1.25×) the width in the X-direction of the insulative line structure104to about two times (2×) the width in the X-direction of the insulative line structure104. The openings112may horizontally terminate in the X-direction between horizontal boundaries of the insulative line structures104and the air gaps110horizontally neighboring the insulative line structures104, such that the openings112do not horizontally overlap the air gaps110; or the openings112may horizontally terminate in the X-direction within horizontal boundaries of the air gaps110horizontally neighboring the insulative line structures104, such that the openings112partially horizontally overlap the air gaps110. In additional embodiments, one or more (e.g., each) of the openings112are individually formed to exhibit a width in the X-direction less than or equal to a width in the X-direction of the insulative line structure104associated therewith. In addition, as shown inFIG.3B, individual openings112may be formed to have lengths in the Y-direction less than lengths in the Y-direction than individual insulative line structures104(and, hence, individual conductive line structures102(FIG.3A)) vertically thereunder. In some embodiments, each opening112is formed to have a substantially square horizontal cross-sectional shape. In additional embodiments, one or more (e.g., each) of the openings112is formed to have a different (e.g., non-square) horizontal cross-sectional shape, such as one or more of a circular horizontal cross-sectional shape, a different tetragonal horizontal cross-sectional shape, an ovular horizontal cross-sectional shape, an elliptical horizontal cross-sectional shape, and a triangular horizontal cross-sectional shape. Each of the openings112may be formed to exhibit substantially the same geometric configuration as each other of the openings112, or one or more of the openings112may be formed to exhibit a different geometric configuration than one or more other of the openings112.

The openings112may be formed using one or more conventional material removal processes (e.g., a conventional anisotropic etching process), which are not described in detail herein. For example, predetermined portions of the isolation material108may be removed by one or more of anisotropic dry etching (e.g., reactive ion etching (RIE), deep RIE, plasma etching, reactive ion beam etching, chemically assisted ion beam etching) and anisotropic wet etching (e.g., hydrofluoric acid (HF) etching, a buffered HF etching, buffered oxide etching).

Referring next toFIG.4A, a spacer material114may, optionally, be formed on or over surfaces of the isolation material108and the insulative line structures104inside and outside of the openings112. For example, as shown inFIG.4A, the spacer material114may be conformally formed on surfaces (e.g., side surfaces) of the isolation material108defining horizontal boundaries of the openings112, on surfaces of the insulative line structures104and the isolation material108defining lower vertical boundaries of the openings112, and on surfaces (e.g., upper surfaces) of the isolation material108outside of the openings112. As shown inFIG.4A, the spacer material114(if any) may partially (e.g., less than completely) fill the openings112.FIG.4Bis a simplified plan view of the microelectronic device structure100at the process stage depicted inFIG.4A. For clarity and ease of understanding the drawings and associated description, portions of the spacer material114outside of the horizontal boundaries of the openings112are omitted inFIG.4B. However, as shown inFIG.4Aand as described above, the spacer material114(if any) may be formed to horizontally extend beyond the horizontal boundaries of the openings112.

The spacer material114, if any, may be formed of and include at least one insulative material having different etch selectivity than the insulative line structures104. The spacer material114may be selectively etchable relative to the insulative line structures104during common (e.g., collective, mutual) exposure to a first etchant, and the insulative line structures104may be selectively etchable relative to the spacer material114during common exposure to a second, different etchant. As used herein, a material is “selectively etchable” relative to another material if the material exhibits an etch rate that is at least about three time (3×) greater than the etch rate of another material, such as about five times (5×) greater, about ten times (10×) greater, about twenty times (20×) greater, or about forty times (40×) greater. By way of non-limiting example, the spacer material114may be formed of and include one or more of at least one dielectric oxide material (e.g., one or more of SiOx, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlOx, HfOx, NbOx, TiOx, ZrOx, TaOx, and a MgOx), at least one dielectric nitride material (e.g., SiNy), at least one dielectric oxynitride material (e.g., SiOxNy), and at least one dielectric carboxynitride material (e.g., SiOxCzNy). In some embodiments, such as some embodiments wherein the insulative line structures104are formed of and include at least one dielectric nitride material (e.g., SiNy, such as Si3N4), the spacer material114is formed of and includes at least one dielectric oxide material (e.g., SiOx, such as SiO2).

The spacer material114, if any, may be formed to any desired thickness, at least partially depending on the horizontal distances (e.g., in the X-direction) between individual insulative line structures104(and, hence, the conductive line structures102) and individual air gaps110horizontally neighboring the insulative line structures104. The spacer material114may be employed to form spacer structures that at least partially protect (e.g., preserve, maintain) the air gaps110during subsequent processing of the microelectronic device structure100, as described in further detail below. By way of non-limiting example, the spacer material114, if any, may be formed to have a thickness within a range of from about 10 nanometers (nm) to about 100 nm, such as from about 20 nm to about 75 nm, or from about 30 nm to about 50 nm. In some embodiments, the spacer material114is formed to exhibit a thickness within a range of from about 30 nm to about 50 nm.

The spacer material114, if any, may be formed using conventional processes and conventional processing equipment, which are not described in detail herein. By way of non-limiting example, the spacer material114may be conformally formed on exposed surfaces of the microelectronic device structure100through one or more of a conformal CVD process and an ALD process.

Referring next toFIG.5A, the spacer material114(FIGS.4A and4B), if any, and portions of the insulative line structures104within horizontal boundaries of the openings112(FIGS.4A and4B) may be subjected to at least one material removal process to form spacer structures116from the spacer material114(FIGS.4A and4B) and to selectively remove the portions of the insulative line structures104. As shown inFIG.5A, the material removal process may form extended openings118vertically extending to and exposing (e.g., uncovering) portions of the conductive line structures102.FIG.5Bis a simplified plan view of the microelectronic device structure100at the process stage depicted inFIG.5A.

As shown inFIG.5A, the material removal process may substantially (e.g., completely) remove portions of the spacer material114, if any, on or over upper surfaces of the isolation material108outside of the horizontal boundaries of the openings112(FIGS.4A and4B), and may partially remove portions of the spacer material114at lower vertical boundaries of the openings112. The spacer structures116, if any, may comprise remaining (e.g., unremoved) portions of the spacer material114on side surfaces of the isolation material108at horizontal boundaries of the openings112. In additional embodiments wherein the spacer material114is not formed, the spacer structures116are omitted (e.g., absent) from the microelectronic device structure100.

Still referring toFIG.5A, the material removal process may remove portions of the insulative line structures104within horizontal boundaries (e.g., in the X-direction and the Y-direction) of the openings112(FIGS.4A and4B) to form the extended openings118. The extended openings118may include upper portions118A comprising remaining (e.g., unfilled) portions of the openings112(FIGS.4A and4B), and lower portions118B vertically underlying and continuous with the upper portions118A. As shown inFIG.5A, the lower portions118B of the extended openings118may be horizontally narrower in the X-direction than the upper portions118A of the extended openings118. In some embodiments, inner side surfaces of the spacer structures116define horizontal boundaries of the upper portions118A of the extended openings118, and inner side surfaces of the isolation material108vertically underlying the spacer structures116define horizontal boundaries of the lower portions118B of the extended openings118. The extended openings118may vertically extend (e.g., in the Z-direction) from an upper vertical boundary (e.g., an upper surface) of the isolation material108to upper vertical boundaries (e.g., upper surfaces) of the conductive line structures102.

The spacer structures116(if any) and the extended openings118may be formed using conventional processes (e.g., conventional anisotropic etching processes) and conventional processing equipment, which are not described in detail herein. In some embodiments, a first anisotropic dry etching process is employed to remove the portions of the spacer material114(FIGS.4A and4B) and form the spacer structures116, and then a second anisotropic dry etching process is used to selectively remove newly exposed (e.g., uncovered) portions of the insulative line structures104and form the extended openings118. The first anisotropic dry etching process may employ a first dry etchant having a higher etch selectivity toward the spacer material114(FIGS.4A and4B) than the insulative line structures104; and the second anisotropic dry etching process may employ a second dry etchant having a higher etch selectivity toward the insulative line structures104than the spacer material114(FIGS.4A and4B).

Referring next toFIG.6A, conductive contact structures120may be formed within the extended openings118(FIGS.5A and5B), and conductive pad structures124may be formed on or over the conductive contact structures120. The conductive contact structures120may be substantially confined within boundaries (e.g., horizontal boundaries, vertical boundaries) of the extended openings118(FIGS.5A and5B), and the conductive pad structures124may be at least partially positioned outside of the boundaries of the extended openings118(FIGS.5A and5B). In addition, an additional isolation material122may be formed on or over the isolation material108, and may horizontally neighbor the conductive pad structures124.FIG.6Bis a simplified plan view of the microelectronic device structure100at the process stage depicted inFIG.6A. For clarity and ease of understanding the drawings and associated description, the additional isolation material122is omitted inFIG.6B.

As shown inFIG.6A, the conductive contact structures120may substantially fill the extended openings118(FIGS.5A and5B), and may exhibit substantially planar upper surfaces substantially coplanar with an upper surfaces of the isolation material108and the spacer structures116(if any). The conductive contact structures120may vertically extend (e.g., in the Z-direction) from upper boundaries (e.g., upper surfaces) of the isolation material108and the spacer structures116(if any) to upper boundaries (e.g., upper surfaces) of the conductive line structures102. In some embodiments, the dimensions, shapes, and the spacing of the conductive contact structures120are respectively substantially the same as the dimensions, shapes, and the spacing of the extended openings118(FIGS.5A and5B). The conductive contact structures120may be coupled to the conductive line structures102. In some embodiments, the conductive contact structures120are employed as digit line contact structures (e.g., data line contact structures, bit line contact structures) for a memory device, as described in further detail below.

The conductive contact structures120may each individually be formed of and include conductive material. By way of non-limiting example, the conductive contact structures120may be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, the conductive contact structures120are formed of and include Cu. In additional embodiments, the conductive contact structures120are formed of and include W.

The conductive contact structures120may be formed using conventional processes and conventional processing equipment, which are not described in detail herein. By way of non-limiting example, conductive material may be formed (e.g., non-conformably deposited) inside and outside of the extended openings118(FIGS.5A and5B), and then portions of the conductive material outside the boundaries (e.g., horizontal boundaries, vertical boundaries) of the extended openings118(FIGS.5A and5B) may be removed (e.g., through at least one material removal process, such as at least one CMP process) to form the conductive contact structures120.

With continued reference toFIG.6A, the additional isolation material122may be formed on or over an upper surface of the isolation material108. The additional isolation material122may be formed of and include at least one insulative material. By way of non-limiting example, the additional isolation material122may be formed of and include one or more of at least one dielectric oxide material (e.g., one or more of SiOx, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlOx, HfOx, NbOx, and TiOx), at least one dielectric nitride material (e.g., SiNy), at least one dielectric oxynitride material (e.g., SiOxNy), at least one dielectric carboxynitride material (e.g., SiOxCzNy), and amorphous carbon. A material composition of the additional isolation material122may be substantially the same as a material composition of the isolation material108, or the material composition of the additional isolation material122may be different than the material composition of the isolation material108. In some embodiments, the additional isolation material122is formed of and includes SiOx(e.g., SiO2).

The conductive pad structures124may be formed on or over surfaces of the conductive contact structures120, the spacer structures116(if any), and the isolation material108. The conductive pad structures124may be formed within and may substantially fill apertures formed within the additional isolation material122. As shown inFIGS.6A and6B, the conductive pad structures124may be formed to horizontally extend over multiple insulative line structures104(and, hence, over multiple conductive line structures102) and air gaps110. Individual conductive pad structures124may be coupled to individual conductive contact structures120. The conductive pad structures124may be employed as bond pads to couple the conductive contact structures120to additional conductive pad structures and additional conductive contact structures, as described in further detail below.

The conductive pad structures124may each individually be formed of and include conductive material. By way of non-limiting example, the conductive pad structures124may be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). A material composition of the conductive pad structures124may be substantially the same as a material composition of the conductive contact structures120, or the material composition of the conductive pad structures124may be different than the material composition of the conductive contact structures120. In some embodiments, the conductive pad structures124are formed of and include Cu.

The additional isolation material122and the conductive pad structures124may be formed using conventional processes and conventional processing equipment, which are not described in detail herein. As a non-limiting example, the additional isolation material122may be formed (e.g., through at least one material deposition process, such as one or more of an ALD process, a CVD process, a PECVD process, a PVD process, and a spin-coating process) on or over exposed surfaces of the conductive contact structures120, the spacer structures116(if any), and the isolation material108; apertures may be formed (e.g., etched) within the additional isolation material122; and then the conductive pad structures124may be formed within the apertures through a damascene process. The damascene process may include filling the apertures with conductive material (e.g., through at least one additional material deposition process, such as one or more of an ALD process, a CVD process, a PECVD process, a PVD process, and a spin-coating process), and then removing portions of the conductive material outside boundaries (e.g., horizontal boundaries, vertical boundaries) of the apertures using at least one planarization process (e.g., at least one CMP process). As another non-limiting example, conductive material may be formed (e.g., through at least one material deposition process, such as one or more of an ALD process, a CVD process, a PECVD process, a PVD process, and a spin-coating process) on or over exposed surfaces of the conductive contact structures120, the spacer structures116(if any), and the isolation material108; portions of the conductive material may be removed (e.g., etched) to form the conductive pad structures124through a subtractive process; and then the additional isolation material122may be formed (e.g., using at least one material deposition process and at least one planarization process) around the conductive pad structures124.

The methods of the disclosure described above with reference toFIGS.1A through6Bmay facilitate the self-alignment of the conductive pad structures124with the conductive line structures102, and may avoid or relax overlay constraints as compared to conventional methods of forming conductive bond pad structures over similar conductive line structures. The methods of the disclosure may reduce the number of processing acts (e.g., alignment and masking acts), materials, and structures required to form desirable microelectronic device structures as compared to conventional methods of forming desirable microelectronic device structures.

Thus, in accordance with embodiments of the disclosure, a method of forming a microelectronic device comprises forming line structures comprising conductive material and insulative material overlying the conductive material, the line structures separated from one another by trenches. An isolation material is formed on surfaces of the line structures inside and outside of the trenches, the isolation material only partially filling the trenches to form air gaps interposed between the line structures. Openings are formed to extend through the isolation material and expose portions of the insulative material of the line structures. The exposed portions of the insulative material of the line structures are removed to form extended openings extending to the conductive material of the line structures. Conductive contact structures are formed within the extended openings. Conductive pad structures are formed on the conductive contact structures. Additional methods, microelectronic devices, memory devices, and electronic systems are also described.

Microelectronic device structures (e.g., the microelectronic device structure100following the process stage described above with reference toFIGS.6A and6B) in accordance with embodiments of the disclosure may be employed in microelectronic devices (e.g., a memory device, such as a 3D NAND Flash memory device) of the disclosure. By way of non-limiting example,FIG.7is a simplified, partial cross-sectional view of a microelectronic device200(e.g., a memory device, such as a 3D NAND Flash memory device), in accordance with embodiments of the disclosure. As shown inFIG.7and described in further detail below, the microelectronic device200may include the microelectronic device structure100resulting from the completion of the process stage previously described with reference toFIGS.6A and6B. With the description provided below, it will be readily apparent to one of ordinary skill in the art that microelectronic devices described herein may be included in various relatively larger devices and various electronic systems.

As shown inFIG.7, the microelectronic device200may include a control logic region202, a memory array region204, a first interconnect region206, and a second interconnect region208. As shown inFIG.7, the first interconnect region206may vertically overlie (e.g., in the Z-direction) and be in electrical communication with the control logic region202, and the memory array region204may vertically overlie and be in electrical communication with the first interconnect region206. The first interconnect region206may be vertically interposed between and in electrical communication with the control logic region202and the memory array region204. In addition, the second interconnect region208may vertically overlie and be in electrical communication with the memory array region204. The memory array region204may be vertically interposed between and in electrical communication with the first interconnect region206and the second interconnect region208. The microelectronic device structure100previously described with reference toFIGS.6A and6Bmay form portions of the memory array region204and the first interconnect region206of the microelectronic device200.

The control logic region202of the microelectronic device200may include a semiconductive base structure210, gate structures212, first routing structures214, and first contact structures216. Portions of the semiconductive base structure210, the gate structures212, the first routing structures214, and the first contact structures216form various control logic devices215of the control logic region202, as described in further detail below.

The semiconductive base structure210(e.g., semiconductive wafer) of the control logic region202comprises a base material or construction upon which additional features (e.g., materials, structures, devices) of the microelectronic device200are formed. The semiconductive base structure210may comprise a semiconductive structure (e.g., a semiconductive wafer), or a base semiconductive material on a supporting structure. For example, the semiconductive base structure210may comprise a conventional silicon substrate (e.g., a conventional silicon wafer), or another bulk substrate comprising a semiconductive material. In some embodiments, the semiconductive base structure210comprises a silicon wafer. In addition, the semiconductive base structure210may include one or more layers, structures, and/or regions formed therein and/or thereon. For example, the semiconductive base structure210may include conductively doped regions and undoped regions. The conductively doped regions may, for example, be employed as source regions and drain regions for transistors of the control logic devices215of the control logic region202; and the undoped regions may, for example, be employed as channel regions for the transistors of the control logic devices215.

As shown inFIG.7, the gate structures212of the control logic region202of the microelectronic device200may vertically overlie (e.g., in the Z-direction) portions of the semiconductive base structure210. The gate structures212may individually horizontally extend between and be employed by transistors of the control logic devices215within the control logic region202of the microelectronic device200. The gate structures212may be formed of and include conductive material. A gate dielectric material (e.g., a dielectric oxide) may vertically intervene (e.g., in the Z-direction) between the gate structures212and channel regions (e.g., within the semiconductive base structure210) of the transistors.

The first routing structures214may vertically overlie (e.g., in the Z-direction) the semiconductive base structure210, and may be electrically connected to the semiconductive base structure210by way of the first contact structures216. The first routing structures214may serve as local routing structures for the microelectronic device200. A first group216A of the first contact structures216may vertically extend between and couple regions (e.g., conductively doped regions, such as source regions and drain regions) of the semiconductive base structure210to one or more of the first routing structures214. In addition, a second group216B of the first contact structures216may vertically extend between and couple some of the first routing structures214to one another.

The first routing structures214may each individually be formed of and include conductive material. By way of non-limiting example, the first routing structures214may be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, the first routing structures214are formed of and include Cu. In additional embodiments, the first routing structures214are formed of and include W.

The first contact structures216(including the first group216A and the second group216B thereof) may each individually be formed of and include conductive material. By way of non-limiting example, the first routing structures214may be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, the first contact structures216are formed of and include Cu. In additional embodiments, the first contact structures216are formed of and include W. In further embodiments, the first contact structures216of the first group216A of the first contact structures216are formed of and include first conductive material (e.g., W); and the first contact structures216of the second group216B of the first contact structures216are formed of and include a second, different conductive material (e.g., Cu).

As previously mentioned, portions of the semiconductive base structure210(e.g., conductively doped regions serving as source regions and drain regions, undoped regions serving as channel regions), the gate structures212, the first routing structures214, and the first contact structures216form various control logic devices215of the control logic region202. In some embodiments, the control logic devices215comprise complementary metal oxide semiconductor (CMOS) circuitry. The control logic devices215may be configured to control various operations of other components (e.g., memory cells within the memory array region204) of the microelectronic device200. As a non-limiting example, the control logic devices215may include one or more (e.g., each) of charge pumps (e.g., VCCPcharge pumps, VNEGWLcharge pumps, DVC2 charge pumps), delay-locked loop (DLL) circuitry (e.g., ring oscillators), Vddregulators, string drivers, page buffers, and various chip/deck control circuitry. As another non-limiting example, the control logic devices215may include devices configured to control column operations for arrays (e.g., memory element array(s), access device array(s)) within the memory array region204of the microelectronic device200, such as one or more (e.g., each) of decoders (e.g., local deck decoders, column decoders), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSAs), PMOS sense amplifiers (PSAs)), repair circuitry (e.g., column repair circuitry), I/O devices (e.g., local I/O devices), memory test devices, array multiplexers (MUX), and error checking and correction (ECC) devices. As a further non-limiting example, the control logic devices215may include devices configured to control row operations for arrays (e.g., memory element array(s), access device array(s)) within the memory array region204of the microelectronic device200, such as one or more (e.g., each) of decoders (e.g., local deck decoders, row decoders), drivers (e.g., WL drivers), repair circuitry (e.g., row repair circuitry), memory test devices, MUX, ECC devices, and self-refresh/wear leveling devices.

Still referring toFIG.7, the memory array region204of the microelectronic device200may include a stack structure218; portions of the microelectronic device structure100, including the conductive line structures102, the insulative line structures104, the isolation material108, and the air gaps110; and a source tier237including one or more source structure(s)238and one or more contact pad(s)240. The stack structure218may correspond to the base structure101, previously described with reference toFIGS.1A and1B, of the microelectronic device structure100. In addition, the conductive line structures102may serve as digit line structures (e.g., data line structures, bit line structures) of the microelectronic device200, and the insulative line structures104may serve as digit line cap structures (e.g., data line cap structures, bit line cap structures) of the microelectronic device200. The stack structure218may be vertically interposed between the conductive line structures102and the source tier237. The conductive line structures102may vertically underlie (e.g., in the Z-direction) the stack structure218, and may be electrically connected to features (e.g., pillar structures, filled vias) within the stack structure218. The source tier237may vertically overlie (e.g., in the Z-direction) the stack structure218. The source structure(s)238and the contact pad(s)240of the source tier237may be coupled (e.g., electrically connected) to features (e.g., pillar structures, filled vias) within the stack structure218and additional features (e.g., interconnect structures) within the second interconnect region208of the microelectronic device200. As shown inFIG.7, portions of the conductive contact structures120of the microelectronic device structure100may also be located within the memory array region204of the microelectronic device200. Additional portions of the conductive contact structures120may be located within the first interconnect region206of the microelectronic device200.

The stack structure218of the memory array region204includes a vertically alternating (e.g., in the Z-direction) sequence of conductive structures220and insulative structures222arranged in tiers224. Each of the tiers224of the stack structure218may include at least one of the conductive structures220vertically neighboring at least one of the insulative structures222. In some embodiments, the conductive structures220are formed of and include tungsten (W) and the insulative structures222are formed of and include silicon dioxide (SiO2) The conductive structures220and insulative structures222of the tiers224of the stack structure218may each individually be substantially planar, and may each individually exhibit a desired thickness.

As shown inFIG.7, one or more deep contact structure(s)226may vertically extend through the stack structure218. The deep contact structure(s)226may be configured and positioned to electrically connect one or more components of the microelectronic device200vertically overlying the stack structure218with one or more other components of the microelectronic device200vertically underlying the stack structure218. The deep contact structure(s)226may be formed of and include conductive material. In some embodiments, the deep contact structure(s) are formed of and include W.

As shown inFIG.7, the memory array region204further includes cell pillar structures228vertically extending through the stack structure218. The cell pillar structures228may each individually include a semiconductive pillar (e.g., a polycrystalline silicon pillar, a silicon-germanium pillar) at least partially surrounded by one or more charge storage structures (e.g., a charge trapping structure, such as a charge trapping structure comprising an oxide-nitride-oxide (“ONO”) material; floating gate structures). Intersections of the cell pillar structures228and the conductive structures220of the tiers224of the stack structure218may define vertically extending strings of memory cells230coupled in series with one another within the memory array region204of the microelectronic device200. In some embodiments, the memory cells230formed at the intersections of the conductive structures220and the cell pillar structures228within the tiers224of the stack structure218comprise so-called “MONOS” (metal-oxide-nitride-oxide-semiconductor) memory cells. In additional embodiments, the memory cells230comprise so-called “TANOS” (tantalum nitride-aluminum oxide-nitride-oxide-semiconductor) memory cells, or so-called “BETANOS” (band/barrier engineered TANOS) memory cells, each of which are subsets of MONOS memory cells. In further embodiments, the memory cells comprise so-called “floating gate” memory cells including floating gates (e.g., metallic floating gates) as charge storage structures. The floating gates may horizontally intervene between central structures of the cell pillar structures228and the conductive structures220of the different tiers224of the stack structure218.

As shown inFIG.7, the conductive line structures102may be vertically interposed between the stack structure218and the first interconnect region206underlying the stack structure218. Individual conductive line structures102may be coupled to individual vertically extending strings of memory cells230. In some embodiments, the conductive line structures102directly physically contact the cell pillar structures228. In additional embodiments, contact structures may vertically intervene between the conductive line structures102and the cell pillar structures228, and may couple the conductive line structures102to the vertically extending strings of memory cells230.

With continued reference toFIG.7, the source tier237may be vertically interposed between the stack structure218and the second interconnect region208overlying the stack structure218. Within the source tier237, the source structure(s)238and the contact pad(s)240may horizontally neighbor one another (e.g., in the X-direction, in the Y-direction). The source structure(s)238may be electrically isolated from the contact pad(s)240, and may be positioned at substantially the same vertical position (e.g., in the Z-direction) as the contact pad(s)240. At least one insulative material may be horizontally interposed between the source structure(s)238and the contact pad(s)240, as described in further detail below.

The source structure(s)238of the source tier237may be coupled to the vertically extending strings of memory cells230. In some embodiments, the source structure(s)238directly physically contact the cell pillar structures228. In additional embodiments, contact structures may vertically intervene between the source structure(s)238and the cell pillar structures228, and may couple the source structure(s)238to the vertically extending strings of memory cells230. In addition, the source structure(s)238may be coupled to additional structures (e.g., contact structures, routing structures, pad structures) within the second interconnect region208, as described in further detail below.

The contact pad(s)240of the source tier237may be coupled to the additional conductive features (e.g., conductive contact structures, conductive pillars, conductively filled vias) within the stack structure218. For example, as shown inFIG.7, the contact pad(s)240may be coupled to the deep contact structure(s)226vertically extending through the stack structure218. In some embodiments, the contact pad(s)240directly physically contact the deep contact structure(s)226. In additional embodiments, additional contact structures may vertically intervene between the contact pad(s)240and the deep contact structure(s)226, and may couple the contact pad(s)240to the deep contact structure(s)226. In addition, the contact pad(s)240may be coupled to additional structures (e.g., interconnect structures, routing structures, pad structures) within the second interconnect region208, as described in further detail below.

The source structure(s)238and the contact pad(s)240may each be formed of and include conductive material. A material composition of the source structure(s)238may be substantially the same as a material composition of the contact pad(s)240. In some embodiments, the source structure(s)238and the contact pad(s)240are formed of and include conductively doped semiconductive material, such as a conductively doped form of one or more of a silicon material, such as monocrystalline silicon or polycrystalline silicon; a silicon-germanium material; a germanium material; a gallium arsenide material; a gallium nitride material; and an indium phosphide material. As a non-limiting example, the source structure(s)238and the contact pad(s)240may be formed of and include epitaxial silicon (e.g., monocrystalline silicon formed through epitaxial growth) doped with at least one dopant (e.g., one or more of at least one n-type dopant, at least one p-type dopant, and at least another dopant). As another non-limiting example, the source structure(s)238and the contact pad(s)240may be formed of and include polycrystalline silicon doped with at least one dopant (e.g., one or more of at least one n-type dopant, at least one p-type dopant, and at least another dopant).

As shown inFIG.7, optionally, strapping structures241may be located on or over the source structure(s)238and the contact pad(s)240. The strapping structures241may be vertically interposed between the source structure(s)238and the contact pad(s)240and additional features (e.g., additional structures, additional materials) within the second interconnect region208. If present, the strapping structures241may be formed of and include conductive material. A material composition of the strapping structures241may be selected to lower contact resistance (relative to configurations wherein the strapping structures241are absent) between conductive structures within the second interconnect region208and each of source structure(s)238and the contact pad(s)240of the source tier237. By way of non-limiting example, the strapping structures241(if any) may be formed of and include a metallic material comprising one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, the strapping structures241are formed of and include tungsten silicide (WSix). In additional embodiments, the strapping structures241are formed of and include one or more of (e.g., a stack of) W and tungsten nitride (WNx).

With continued reference toFIG.7, the first interconnect region206of the microelectronic device200may be vertically interposed between the control logic region202and the memory array region204of the microelectronic device200. The first interconnect region206may couple features of the control logic region202with features of the memory array region204. As shown inFIG.7, the first interconnect region206may include second contact structures242coupled to the first routing structures214of the control logic region202; portions of the conductive contact structures120of the microelectronic device structure100coupled to the conductive line structures102of the memory array region204; and connected bond pads246extending between and coupling the second contact structures242and the conductive contact structures120. The connected bond pads246may include first bond pads248on (e.g., vertically overlying and directly adjacent) the second contact structures242, and the conductive pad structures124(serving as second bond pads) of the microelectronic device structure100. The first bond pads248and the conductive pad structures124may be physically connected to one another to form the connected bond pads246.

The second contact structures242of the first interconnect region206may vertically extend from and between the first bond pads248and some of the first routing structures214of the control logic region202. In some embodiments, the second contact structures242comprise conductively filled vias vertically extending through dielectric material interposed between the first bond pads248and the first routing structures214. The second contact structures242may be formed of and include conductive material. By way of non-limiting example, the second contact structures242may be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, each of the second contact structures242is formed of and includes Cu.

The connected bond pads246of the first interconnect region206may vertically extend from and between the second contact structures242and the conductive contact structures120of the microelectronic device structure100. The first bond pads248of the connected bond pads246may vertically extend from and between the second contact structures142and the conductive pad structures124of the connected bond pads246; and the conductive pad structures124of the connected bond pads246may vertically extend from and between the conductive contact structures120and the first bond pads248of the connected bond pads246. While inFIG.1, the first bond pad248and the conductive pad structure124of each connected bond pad246are distinguished from one another by way of a dashed line, the first bond pad248and the conductive pad structure124may be integral and continuous with one another. Put another way, each connected bond pad246may be a substantially monolithic structure including the first bond pad248as a first region thereof, and the conductive pad structure124as a second region thereof. For each connected bond pad246, the first bond pad248thereof may be attached to the conductive pad structure124thereof without a bond line.

The connected bond pads246(including the first bond pads248and the conductive pad structures124thereof) may be formed of and include conductive material. By way of non-limiting example, the connected bond pads246may be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, each of the connected bond pads246(including the first bond pads248and the conductive pad structures124thereof) is formed of and includes Cu.

Still referring toFIG.7, at least one insulative material232may cover and surround the second contact structures242and the first bond pads248of the connected bond pads246. The insulative material232may be attached to the additional isolation material122of the microelectronic device structure100. A material composition of the insulative material232may be substantially the same as a material composition of the additional isolation material122, or the material composition of the insulative material232may be different than the material composition of the additional isolation material122. In some embodiments, the insulative material232is formed of and includes at least one dielectric oxide material, such as SiOx(e.g., SiO2). In additional embodiments, the insulative material232is formed of and includes at least one low-k dielectric material, such as one or more of SiOxCy, SiOxNy, SiCxOyHz, and SiOxCzNy. The insulative material232may be substantially homogeneous, or the insulative material232may be heterogeneous. In some embodiments, the insulative material232is substantially homogeneous. In additional embodiments, the insulative material232is heterogeneous. The insulative material232may, for example, be formed of and include a stack of at least two different dielectric materials.

With continued reference toFIG.7, the second interconnect region208of the microelectronic device200may vertically overlie the memory array region204of the microelectronic device200. The second interconnect region208may include second routing structures252and conductive pads256. The second routing structures252may vertically overlie the source tier237(including the source structure(s)238and the contact pad(s)240thereof) of the memory array region204, and may be coupled to the source structure(s)238and the contact pad(s)240by way of third contact structures254. The third contact structures254may extend between the second routing structures252and the source structure(s)238and the contact pad(s)240of the source tier237. If present, the strapping structures241may vertically intervene between the third contact structures254and the source structure(s)238and the contact pad(s)240. The conductive pads256may vertically overlie the second routing structures252, and may be coupled to the second routing structures252by way of fourth contact structures258. The fourth contact structures258may extend from and between the second routing structures252and the conductive pads256.

The second routing structures252and the conductive pads256may serve as global routing structures for the microelectronic device200. The second routing structures252and the conductive pads256may, for example, be configured to receive global signals from an external bus, and to relay the global signals to other components (e.g., structures, devices) of the microelectronic device200.

The second routing structures252, the third contact structures254, the conductive pads256, and the fourth contact structures258may each be formed of and include conductive material. By way of non-limiting example, the second routing structures252, the third contact structures254, the conductive pads256, and the fourth contact structures258may each individually be formed of and include one or more of at least one metal, at least one alloy, and at least one conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide). In some embodiments, the second routing structures252and the third contact structures254are each formed of and include Cu, the conductive pads256are formed of and include Al, and the fourth contact structures258are formed of and include W. In additional embodiments, the second routing structures252are formed of and include Cu, the conductive pads256are formed of and include Al, and the third contact structures254and the fourth contact structures258are each formed of and include W.

Still referring toFIG.7, at least one additional insulative material260may cover and surround the second routing structures252, the third contact structures254, the conductive pads256, and the fourth contact structures258. The at least one additional insulative material260may also cover and surround portions of the source structure(s)238and the contact pad(s)240. A material composition of the additional insulative material260may be substantially the same as or may be different than a material composition of the insulative material132. In some embodiments, the additional insulative material260is formed of and includes at least one dielectric oxide material, such as SiOx(e.g., SiO2). In additional embodiments, the additional insulative material260is formed of and includes at least one low-k dielectric material, such as one or more of SiOxCy, SiOxNy, SiCxOyHz, and SiOxCzNy. The additional insulative material260may be substantially homogeneous, or the additional insulative material260may be heterogeneous. If the additional insulative material260is heterogeneous, amounts of one or more elements included in the additional insulative material260may vary stepwise (e.g., change abruptly), or may vary continuously (e.g., change progressively, such as linearly, parabolically) throughout different portions of the additional insulative material260. In some embodiments, the additional insulative material260is substantially homogeneous. In additional embodiments, the additional insulative material260is heterogeneous. The additional insulative material260, for example, be formed of and include a stack of at least two different dielectric materials.

Thus, a microelectronic device in accordance with embodiments of the disclosure comprises conductive line structures, insulative line structures, partially filled trenches, conductive contact structures, and conductive pad structures. The conductive line structures extend in a first horizontal direction. The insulative line structures are on the conductive line structures and extend in the first horizontal direction. The partially filled trenches intervene between the conductive line structures in a second horizontal direction orthogonal to the first horizontal direction. The partially filled trenches comprise an isolation material on side surfaces of the conductive line structures and the insulative line structures, and air gaps surrounded by the isolation material. The conductive contact structures vertically extend through portions of the insulative line structures and contact the conductive line structures. The conductive pad structures are on the conductive contact structures.

Furthermore, a memory device in accordance with embodiments of the disclosure comprises a memory array region, a control logic region vertically underlying the memory array region, and an interconnect region vertically interposed between the memory array region and the control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures; vertically extending strings of memory cells within the stack structure; a source structure vertically overlying the stack structure and coupled to the vertically extending strings of memory cells; digit line structures vertically underlying the stack structure and coupled to the vertically extending strings of memory cells; dielectric cap structures vertically underlying the digit line structures; an isolation material horizontally interposed between the digit line structures and horizontally interposed between the dielectric cap structures; and air gaps surrounded by the isolation material and horizontally alternating with the digit line structures. The control logic region comprises control logic devices configured to effectuate a portion of control operations for the vertically extending strings of memory cells. The interconnect region comprises structures coupling the digit line structures of the memory array region to the control logic devices of the control logic region.

FIGS.8A through8Dare simplified, partial cross-sectional views illustrating embodiments of a method of forming the microelectronic device200described above with reference toFIG.7. With the description provided below, it will be readily apparent to one of ordinary skill in the art that the methods and structures described herein may be used to form various devices and electronic systems.

Referring toFIG.8A, a first microelectronic device construction201may be formed to include the control logic region202of the microelectronic device200(FIG.7), including the semiconductive base structure210, the gate structures212, the first routing structures214, and the first contact structures216thereof. The first microelectronic device construction201may also be formed to include the second contact structures242, the first bond pads248, and the insulative material232. The first microelectronic device construction201may be formed using conventional processes (e.g., conventional material deposition processes, conventional material removal processes) and conventional processing equipment, which are not described in detail herein.

Referring next toFIG.8B, a second microelectronic device construction203may be formed to include a carrier structure233(e.g., a carrier wafer); a doped semiconductive material235(e.g., conductively doped silicon, such as one or more conductively doped monocrystalline silicon and conductively doped polycrystalline silicon) on or over the carrier structure233; the stack structure218; the deep contact structure(s)226; the cell pillar structures228; and the microelectronic device structure100, including the conductive line structures102, the insulative line structures104, the isolation material108, the air gaps110, the conductive contact structures120, the additional isolation material122, and the conductive pad structures124thereof. The second microelectronic device construction203may be formed separate from the first microelectronic device construction201(FIG.8A).

The carrier structure233of the second microelectronic device construction203comprises a base material or construction upon which additional features (e.g., materials, structures, devices) of the second microelectronic device construction203are formed. The carrier structure233may, for example, be formed of and include one or more of semiconductive material (e.g., one or more of a silicon material, such monocrystalline silicon or polycrystalline silicon (also referred to herein as “polysilicon”); silicon-germanium; germanium; gallium arsenide; a gallium nitride; gallium phosphide; indium phosphide; indium gallium nitride; and aluminum gallium nitride), a base semiconductive material on a supporting structure, glass material (e.g., one or more of borosilicate glass (BSP), phosphosilicate glass (PSG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), aluminosilicate glass, an alkaline earth boro-aluminosilicate glass, quartz, titania silicate glass, and soda-lime glass), and ceramic material (e.g., one or more of poly-aluminum nitride (p-AlN), silicon on poly-aluminum nitride (SOPAN), aluminum nitride (AlN), aluminum oxide (e.g., sapphire; α-Al2O3), and silicon carbide). The carrier structure233may be configured to facilitate safe handling of the second microelectronic device construction203for subsequent attachment to the first microelectronic device construction201, as described in further detail below.

In some embodiments, the doped semiconductive material235is formed on or over the carrier structure233, and then the stack structure218(including the tiers224of the conductive structures220and the insulative structures222there) is formed on or over the doped semiconductive material235. The deep contact structure(s)226, the cell pillar structures228, and additional features (e.g., filled trenches, contact regions, additional contact structures) may then be formed within the stack structure218. Thereafter, the microelectronic device structure100(including the conductive line structures102, the insulative line structures104, the isolation material108, the air gaps110, the conductive contact structures120, the additional isolation material122, and the conductive pad structures124thereof) may be formed on or over the stack structure218through the process previously described herein with reference toFIGS.1A through6B(wherein the stack structure218corresponds to the base structure101inFIGS.1A through6B).

Referring to next toFIG.8C, following the formation of the first microelectronic device construction201and the separate formation of the second microelectronic device construction203, the second microelectronic device construction203may be vertically inverted (e.g., flipped upside down in the Z-direction) and attached (e.g., bonded) to the first microelectronic device construction201to form a microelectronic device structure assembly205. Alternatively, the first microelectronic device construction201may be vertically inverted (e.g., flipped upside down in the Z-direction) and attached to the second microelectronic device construction203to form the microelectronic device structure assembly205. The attachment of the second microelectronic device construction203to the first microelectronic device construction201may attach the conductive pad structures124of the second microelectronic device construction203to the first bond pads248of the first microelectronic device construction201to form the connected bond pads246. In addition, the attachment of the second microelectronic device construction203to the first microelectronic device construction201may also attach the additional isolation material122of the second microelectronic device construction203to the insulative material232of the first microelectronic device construction201. InFIG.8C, vertical boundaries of the first microelectronic device construction201relative to the second microelectronic device construction203prior to the attachment of the first microelectronic device construction201to the second microelectronic device construction203to form the microelectronic device structure assembly205are depicted by the dashed line A-A. The first microelectronic device construction201may be attached to the second microelectronic device construction203without a bond line.

Referring next toFIG.8D, after attaching the second microelectronic device construction203(FIG.8C) to the first microelectronic device construction201(FIG.8C), the carrier structure233(FIG.8C) may be removed (e.g., through conventional detachment processes and/or conventional grinding processes) from the microelectronic device structure assembly205to expose (e.g., uncover) the doped semiconductive material235. Optionally, an additional amount (e.g., additional volume) of doped semiconductive material (e.g., doped polycrystalline silicon) may be formed on doped semiconductive material235following the removal of the carrier structure233(FIG.2A). If formed, the additional amount of doped semiconductive material may have substantially the same material composition as that of the doped semiconductive material235, or may have a different material composition than that of the doped semiconductive material235. In addition, optionally, a strapping material239may formed on or over the doped semiconductive material235. The strapping material239(if any) may comprise one or more of the conductive materials previously described in relation to the strapping structures241(FIG.7). The doped semiconductive material235(and the additional amount of doped semiconductive material, if any) may, optionally, be annealed (e.g., thermally annealed) before and/or after the formation of the strapping material239(if any). Annealing the doped semiconductive material235may, for example, facilitate or enhance dopant activation within the doped semiconductive material235.

Referring collectively toFIGS.7and8D, following the removal of the carrier structure233(FIG.8C), portions of the doped semiconductive material235(and the additional amount of doped semiconductive material, if any) and the strapping material239(FIG.8D) (if any) may be removed (e.g., etched) to respectively form the source structure(s)238(FIG.7), the contact pad(s)240(FIG.7), and the strapping structures241(FIG.7) (if any). Thereafter, the third contact structures254(FIG.7) may be formed on or over the source structure(s)238and the contact pad(s)240, and the second routing structures252(FIG.7) may then be formed on or over the third contact structures254. The fourth contact structures258(FIG.7) may then be formed on or over the second routing structures252, and the conductive pads256(FIG.7) may be formed on or over the fourth contact structures258to effectuate the formation of the microelectronic device200(FIG.7).

Thus, in accordance with embodiments of the disclosure, a method of forming a memory device comprises forming a first microelectronic device construction comprising control logic devices. A second microelectronic device construction is formed to comprise a carrier structure; a stack structure overlying the carrier structure and comprising vertically alternating conductive structures and insulating structures; vertically extending strings of memory cells within the stack structure; digit line structures vertically overlying the stack structure; dielectric cap structures vertically overlying the digit line structures; a dielectric material horizontally intervening between the digit line structures and horizontally intervening between the dielectric cap structures; and air gaps surrounded by the dielectric material and horizontally intervening between the digit line structures. The second microelectronic device construction is attached to the first microelectronic device construction to form a microelectronic device structure assembly, the digit line structures vertically interposed between the stack structure and the control logic devices within the microelectronic device structure assembly. The carrier structure is removed from the microelectronic device structure assembly. At least one source structure is formed over the stack structure of the microelectronic device structure assembly.

Microelectronic device structures (e.g., the microelectronic device structure100(FIGS.6A and6B)) and microelectronic devices (e.g., the microelectronic device200(FIG.7)) in accordance with embodiments of the disclosure may be used in embodiments of electronic systems of the disclosure. For example,FIG.9is a block diagram of an illustrative electronic system300according to embodiments of disclosure. The electronic system300may comprise, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular telephone, a digital camera, a personal digital assistant (PDA), portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet such as, for example, an iPad® or SURFACE® tablet, an electronic book, a navigation device, etc. The electronic system300includes at least one memory device302. The memory device302may comprise, for example, one or more of a microelectronic device structure (e.g., the microelectronic device structure100(FIGS.6A and6B)) and a microelectronic device (e.g., the microelectronic device200(FIG.7)) previously described herein. The electronic system300may further include at least one electronic signal processor device304(often referred to as a “microprocessor”). The electronic signal processor device304may, optionally, include one or more of a microelectronic device structure (e.g., the microelectronic device structure100(FIGS.6A and6B)) and a microelectronic device (e.g., the microelectronic device200(FIG.7)) previously described herein. While the memory device302and the electronic signal processor device304are depicted as two (2) separate devices inFIG.7, in additional embodiments, a single (e.g., only one) memory/processor device having the functionalities of the memory device302and the electronic signal processor device304is included in the electronic system300. In such embodiments, the memory/processor device may include one or more of a microelectronic device structure (e.g., the microelectronic device structure100(FIGS.6A and6B)) and a microelectronic device (e.g., the microelectronic device200(FIG.7)) previously described herein. The electronic system300may further include one or more input devices306for inputting information into the electronic system300by a user, such as, for example, a mouse or other pointing device, a keyboard, a touchpad, a button, or a control panel. The electronic system300may further include one or more output devices308for outputting information (e.g., visual or audio output) to a user such as, for example, a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device306and the output device308may comprise a single touchscreen device that can be used both to input information to the electronic system300and to output visual information to a user. The input device306and the output device308may communicate electrically with one or more of the memory device302and the electronic signal processor device304.

Thus, an electronic system according to embodiments of the disclosure comprises an input device, an output device, a processor device operably coupled to the input device and the output device, and a memory device operably coupled to the processor device. The memory device comprises a stack structure, a source structure, digit lines, strings of memory cells, dielectric nitride structures, insulative material, air gaps within the insulative material, conductive contacts, conductive pads, and control logic circuitry. The stack structure comprises tiers each comprising a conductive structure and an insulative structure vertically neighboring the conductive structure. The source structure overlies the stack structure. The digit lines underlie the stack structure. The strings of memory cells extend through stack structure and are coupled to the source structure and the digit lines. The dielectric nitride structures underlie the digit lines. The insulative material is interposed between the digit lines and is interposed between the dielectric nitride structures. The air gaps within the insulative material are interposed between the digit lines. The conductive contacts extend through the dielectric nitride structures and are coupled to the digit lines. The conductive pads underlie and are coupled to the conductive contacts. The control logic circuitry underlies and is coupled to the conductive pads.

The structures, devices, and methods of the disclosure advantageously facilitate one or more of improved microelectronic device performance, reduced costs (e.g., manufacturing costs, material costs), increased miniaturization of components, and greater packaging density as compared to conventional structures, conventional devices, and conventional methods. The structures, devices, and methods of the disclosure may also improve scalability, efficiency, and simplicity as compared to conventional structures, conventional devices, and conventional methods.

While the disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, the disclosure is not limited to the particular forms disclosed. Rather, the disclosure is to cover all modifications, equivalents, and alternatives falling within the scope of the following appended claims and their legal equivalent. For example, elements and features disclosed in relation to one embodiment may be combined with elements and features disclosed in relation to other embodiments of the disclosure.