Patent ID: 12245361

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

FIG.1is a perspective view of an interconnect structure1with a differential pair design according to some embodiments of the present disclosure.FIG.2is a cross sectional view of the interconnect structure1ofFIG.1taken along line2according to some embodiments of the present disclosure. As shown inFIGS.1-2, in some embodiments of the present disclosure, the interconnect structure1includes a substrate10, a dielectric block12, two conductors14, and two conductive lines18. The substrate10has an opening100therein. The dielectric block12is present in the opening100of the substrate10. The dielectric block12has two vias120therein, in which the dielectric block12has a dielectric constant smaller than a dielectric constant of the substrate10. The conductors14are respectively present in the vias120of the dielectric block12. In some embodiments of the present disclosure, at least one of the conductors14is at least partially present on a sidewall of the corresponding via120. The conductive lines18are present on a surface of the substrate10and are respectively connected to the conductors14.

In some embodiments of the present disclosure, the dielectric block12can be made of a low-k dielectric material. For example, the dielectric constant of the dielectric block12can be in a range from about 1 to about 4 at about 1 GHz, but various embodiments of the present disclosure are not limited in this regard.

In some embodiments of the present disclosure, the dielectric block12is made of a material including, for example, polyimide (PI), aromatic polymers, parylene, parylene-F, amorphous carbon, polytetrafluoroethylene (PTFE), air, or combinations thereof, but various embodiments of the present disclosure are not limited in this regard. The dielectric constant of PI is in a range from about 3 to about 4. The dielectric constant of aromatic polymers is in a range from about 2.6 to about 3.2. The dielectric constant of parylene is about 2.7. The dielectric constant of parylene-F is about 2.3. The dielectric constant of amorphous carbon is in a range from about 2.3 to about 2.8. The dielectric constant of PTFE is in a range from about 1.9 to about 2.1. The dielectric constant of air is about 1. In some embodiments of the present disclosure, the dielectric block12may further include resin, ink, epoxy, or combinations thereof, but various embodiments of the present disclosure are not limited in this regard.

In some embodiments of the present disclosure, the interconnect structure1further includes plugs16respectively plugged in the remaining vias120to prevent solder from wicking through the vias120during the assembly process and damaging (short-circuitry adjacent paths) the finished product. In some embodiments of the present disclosure, the plugs16may be made of solder mask ink, such as epoxy resin, liquid photoimageable solder mask (LPSM) ink, or combinations thereof. In some other embodiments of the present disclosure, the plugs16may be electrically conductive. For example, the plugs16may be made of epoxy resin mixed with conductive particles, such as copper particles, silver particles, or combinations thereof, but various embodiments of the present disclosure are not limited in this regard. The plugs16may also be thermally conductive when the plugs16have thermally conductive matter, such as copper particles, silver particles, or combinations thereof, therein. The thermally conductive plugs16in the vias120can improve removing heat from heat sensitive components during soldering operations. In yet some other embodiments, the plugs16may be non-conductive of electricity. For example, the plugs16may be made of epoxy resin mixed with non-conductive inorganic matter, such as ceramic, but various embodiments of the present disclosure are not limited in this regard. In some other embodiments of the present disclosure, the plugs16may be absent from the vias120. In yet some other embodiments of the present disclosure, the vias120may be filled with the conductors14.

Reference is made toFIG.3.FIG.3is a flowchart of a method for manufacturing the interconnect structure1ofFIG.1according to some embodiments of the present disclosure. The method begins with operation S101in which an opening is formed in a substrate. The method continues with operation S102in which a dielectric block is formed in the opening, and the dielectric block has a dielectric constant smaller than a dielectric constant of the substrate. The method continues with operation S103in which two vias are formed in the dielectric block. The method continues with operation S104in which two conductors are formed in the vias respectively. The method continues with operation S105in which plugs are formed in the remaining vias respectively.

FIGS.4A-4Eare cross-sectional views taken along line2ofFIG.1to sequentially illustrate steps for manufacturing the interconnect structure1according to some embodiments of the present disclosure. As shown inFIG.4A, an opening100is formed in a substrate10. In some embodiments of the present disclosure, the substrate10is an integrated circuit (IC) substrate. In some other embodiments of the present disclosure, the substrate10is a printed circuit board (PCB). For example, the substrate10can be made of FR-4 glass-reinforced epoxy. In yet some other embodiments of the present disclosure, the substrate10is a dielectric layer. The dielectric layer may be made of a polymer dielectric material, such as polyimide, benzocyclobutene (BCB), a photosensitive dielectric material, or combinations thereof. The dielectric layer is formed by, for example, spin coating.

In some embodiments of the present disclosure, the opening100is formed by mechanical drilling, mechanical routing, or combinations thereof when the substrate10is an integrated circuit (IC) substrate or a printed circuit board (PCB). In some other embodiments of the present disclosure, the opening100is formed by laser drilling when the substrate10is an IC substrate, a PCB, or a dielectric layer. The mechanical drilling is used to realize the opening100when the opening100has wide tolerance, and/or the substrate10has a sufficient thickness. On the other hand, the laser drilling is used to realize the opening100when the opening100has narrow tolerance, and/or the substrate10has a thin thickness. Although the opening100shown inFIG.4Ais a through hole, but various embodiments of the present disclosure are not limited in this regard. In some other embodiments of the present disclosure, the opening100may be a blind hole as well. The term “through hole” refers to a hole that is reamed, drilled, milled etc., through the workpiece. The term “blind hole” refers to a hole that is reamed, drilled, milled etc., to a depth without breaking through to the other side of the workpiece. In yet some other embodiments of the present disclosure, the substrate10may be made of a photosensitive dielectric material. The opening100may be formed by a photolithography process when the substrate10is made of a photosensitive dielectric material. Specifically, the substrate10is exposed to a pattern of intense light. The exposure to light causes a chemical change that allows some of the substrate10soluble in a photographic developer. Then, the photographic developer is applied onto the substrate10to remove the some of the substrate10soluble in the photographic developer to form the opening100in the substrate10.

As shown inFIG.4B, a dielectric block12is formed in the opening100of the substrate10by, for example, plugging the dielectric block12into the opening100of the substrate10. In some embodiments of the present disclosure, after the dielectric block12is formed in the opening100, the excess dielectric block12out of the opening100is removed by, for example, a grinding process. Therefore, after the dielectric block12is ground, the dielectric block12is substantially level with a top surface of the substrate10.

As shown inFIG.4C, vias120are formed in the dielectric block12. In some embodiments of the present disclosure, the vias120are formed by mechanical drilling, mechanical routing, or combinations thereof, but various embodiments of the present disclosure are not limited in this regard. For example, in some other embodiments of the present disclosure, the vias120can be formed by laser drilling. In yet some other embodiments of the present disclosure, the dielectric block12may be made of a photosensitive low-k material. The vias120may be formed by a photolithography process when the dielectric block12is made of a photosensitive low-k material. Specifically, the dielectric block12is exposed to a pattern of intense light. The exposure to light causes a chemical change that allows some of the dielectric block12soluble in a photographic developer. Then, the photographic developer is applied onto the dielectric block12to remove the some of the dielectric block12soluble in the photographic developer to form the vias120in the dielectric block12.

As shown inFIG.4D, conductors14are formed in the vias120respectively. The conductors14may be formed by, for example, plating conductive metal at least on sidewalls of the vias120. In some embodiments of the present disclosure, the conductors14are made of copper, gold, aluminum, or combinations thereof, but various embodiments of the present disclosure are not limited in this regard. The plating of the conductive metal may be performed by an electroplating process, where an electric current is used to transfer metal in an aqueous solution to a surface of the interconnect structure1including the sidewalls of the vias120. In order to facilitate the electroplating of the conductive metal, a seed layer (not shown) may be deposited prior to the electroplating of the conductive metal. The seed layer provides nucleation sites where the electroplated metal is initially formed. The electroplated metal is deposited more uniformly on the seed layer than on a bare dielectric. Then, the conductive metal is patterned to form the conductors14. Specifically, the conductive metal may be patterned by, for example, a photolithography and etching process.

In some embodiments of the present disclosure, as shown inFIGS.1and4D, two conductive lines18can be formed on the substrate10with the conductors14. The conductive lines18are present on the substrate10and are respectively electrically connected to the conductors14in the vias120. In practical applications, the conductive lines18can transmit high frequency signals. That is, the conductive lines18can be high frequency differential pairs transmission lines meeting high frequency (greater than about 20 GHz) transmission line requirements.

In some embodiments of the present disclosure, the conductive lines18are redistribution layers (RDL). A RDL is an extra conductive layer on an integrated circuit (IC) chip that makes input/output (I/O) pads of the IC chip available in other locations. When an IC chip is manufactured, the IC chip has a set of I/O pads that are wire-bonded to the pins of the package. A RDL is an extra layer of wiring on the IC chip that enables to be bonded out from different locations on the IC chip.

As shown inFIG.4E, plugs16are formed in the remaining vias120respectively. The plugs16may be formed in the remaining vias120by, for example, screen printing or roller printing. In some other embodiments of the present disclosure, the plugs16may be made from a photosensitive material. The photosensitive material is filled into the vias120and then is exposed to intense light, such as ultraviolet (UV) light, to solidify the photosensitive material. Then, the excess photosensitive material out of the vias120may be removed by, for example, a grinding process.

The low-k dielectric block12separating the conductors14reduces parasitic capacitance between the conductors14, enabling faster switching speeds and lower electronic crosstalk. That is, the low-k dielectric block12can enhance signal isolation between the conductors14. Therefore, multiple concurrent channels are available in one trace. Furthermore, the method for manufacturing the interconnect structure1shown inFIGS.4A-4Eis cost effective since the manufacturing method is doable by existing tools. Moreover, the interconnect structure1shown inFIG.1does not change integrated circuit (IC) substrates and/or printed circuit board design rules, and the thicknesses and structures of the integrated circuit (IC) substrate and/or the printed circuit board will not be changed by applying the interconnect structure1ofFIG.1.

In addition, for a lossless transmission line, the expression for the intrinsic impedance of the transmission line is:

ZC=LlCl(1)in which ZCis the intrinsic impedance of the transmission line, Llis the linear inductance per unit length, and Clis the linear capacitance per unit length.

The low-k dielectric block12can lower the capacitance of the conductive lines18. According to the above equation (1), the lower capacitance of the conductive lines18results in higher intrinsic impedance, which benefits to provide matching impedance when a spacing between the conductive lines18is narrow.

Reference is made toFIGS.5and6.FIG.5is a perspective view of an interconnect structure2with a differential pair design according to some other embodiments of the present disclosure.FIG.6is a cross-sectional view of the interconnect structure2ofFIG.5taken along line6according to some embodiments of the present disclosure. As shown inFIGS.5-6, the interconnect structure2includes a substrate10, a dielectric block12, two conductors14, two plugs16, a shielding element20, pads22, a dielectric layer24, two conductors26, and two conductive lines28. The substrate10has an opening100therein. The shielding element20is present on a sidewall of the opening100. The dielectric block12is then present in the opening100of the substrate10. That is, the shielding element20is present between the dielectric block12and the sidewall of the opening100. The dielectric block12has two vias120therein, in which the dielectric block12has a dielectric constant smaller than a dielectric constant of the substrate10. The conductors14are respectively present in the vias120of the dielectric block12. The plugs16are respectively plugged in the remaining vias120. The pads22are present on the conductors14respectively. The dielectric layer24is present on the substrate10. The dielectric layer24has two vias240therein to expose the pads22respectively. The conductors26are present in the vias240and electrically connected to the conductors14through the pads22, respectively. The conductive lines28are present on a surface of the dielectric layer24and electrically connected to the conductors26, respectively.

Reference is made toFIG.7.FIG.7is a flowchart of a method for manufacturing the interconnect structure ofFIG.5according to some embodiments of the present disclosure. The method begins with operation S201in which an opening is formed in a substrate. The method continues with operation S202in which a shielding element is formed on a sidewall of the opening. The method continues with operation S203in which a dielectric block is formed in the opening, and the dielectric block has a dielectric constant smaller than a dielectric constant of the substrate. The method continues with operation S204in which two first vias are formed in the dielectric block. The method continues with operation S205in which two first conductors are formed in the first vias respectively, and the shielding element is present around the first conductors and separated from the first conductors by the dielectric block. The method continues with operation S206in which plugs are formed in the remaining first vias respectively. The method continues with operation S207in which pads are formed on the first conductors respectively. The method continues with operation S208in which a dielectric layer is formed on the substrate. The method continues with operation S209in which two second vias are formed in the dielectric layer to expose the pads respectively. The method continues with operation S210in which two second conductors are formed in the second vias respectively, and the second conductors are electrically connected to the first conductors through the pads respectively.

FIGS.8A-8Iare cross-sectional views taken along line6ofFIG.5to sequentially illustrate steps for manufacturing the interconnect structure2according to some embodiments of the present disclosure.

Reference is made toFIG.8A. Similar toFIG.4A, an opening100is formed in a substrate10. In some embodiments of the present disclosure, the opening100is formed by mechanical drilling, mechanical routing, or combinations thereof when the substrate10is an integrated circuit (IC) substrate or a printed circuit board (PCB). In some other embodiments, the opening100is formed by laser drilling when the substrate10is an IC substrate, a PCB, or a dielectric layer. Although the opening100shown inFIG.8Ais a through hole, but various embodiments of the present disclosure are not limited in this regard. In some other embodiments, the opening100may be a blind hole as well. In yet some other embodiments of the present disclosure, the substrate10may be made of a photosensitive dielectric material. The opening100may be formed by a photolithography process when the substrate10is made of a photosensitive dielectric material.

Reference is made toFIG.8B. As shown inFIG.8B, a shielding element20is formed on a sidewall of the opening100. In some embodiments, the shielding element20may be formed by, for example, plating a conductive metal in the opening100. The shielding element20may be made of copper, gold, aluminum, or combinations thereof, but various embodiments of the present disclosure are not limited in this regard.

Reference is made toFIG.8C. Similar toFIG.4B, a dielectric block12is formed in the opening100of the substrate10by, for example, plugging the dielectric block12into the opening100of the substrate10. In some embodiments of the present disclosure, after the dielectric block12is formed in the opening100, the excess dielectric block12out of the opening100is removed by, for example, a grinding process. Therefore, after the dielectric block12is ground, the dielectric block12is substantially level with a top surface of the substrate10.

Reference is made toFIG.8D. Similar toFIG.4C, vias120are formed in the dielectric block12. In some embodiments of the present disclosure, the vias120are formed by mechanical drilling, mechanical routing, or combinations thereof, but various embodiments of the present disclosure are not limited in this regard. For example, in some other embodiments of the present disclosure, the vias120can be formed by laser drilling. In yet some other embodiments of the present disclosure, the dielectric block12may be made of a photosensitive low-k material. The vias120may be formed by a photolithography process when the dielectric block12is made of a photosensitive low-k material.

Reference is made toFIG.8E. Similar toFIG.4D, conductors14are formed in the vias120respectively. The conductors14may be formed by, for example, plating conductive metal at least on sidewalls of the vias120. The plating of the conductive metal may be performed by an electroplating process. In order to facilitate the electroplating of the conductive metal, a seed layer (not shown) may be deposited prior to the electroplating of the conductive metal. Then, the conductive metal is patterned to form the conductors14. Specifically, the conductive metal may be patterned by, for example, a photolithography and etching process.

Reference is made toFIG.8F. Similar toFIG.4E, plugs16are formed in the remaining vias120respectively. The plugs16may be formed in the remaining vias120by, for example, screen printing or roller printing. In some other embodiments of the present disclosure, the plugs16may be made from a photosensitive material. The photosensitive material is filled into the vias120and then is exposed to intense light, such as ultraviolet (UV) light, to solidify the photosensitive material. Then, the excess photosensitive material out of the vias120may be removed by, for example, a grinding process.

Reference is made toFIG.8G. As shown inFIG.8G, pads20are formed on the conductors14respectively. In some embodiments, the pads22are made of a metal (e.g., Cu). In some embodiments, the pads22may be formed by, for example, depositing, but various embodiments of the present disclosure are not limited in this regard. In some other embodiments, the pads22are made of graphite powder.

Reference is made toFIG.8H. As shown inFIG.8H, a dielectric layer24is formed on the substrate10, and vias240are formed in the dielectric layer24. In some embodiments, the dielectric layer24is formed on the substrate10by, for example, laminating. In some embodiments, the dielectric layer24is made of FR-4 glass-reinforced epoxy, polyimide, benzocyclobutene (BCB), a photosensitive dielectric material, or combinations thereof. The dielectric layer24is formed by, for example, spin coating. In some embodiments, the vias240of the dielectric layer24are formed by mechanical drilling, mechanical routing, laser drilling, or combinations thereof, but various embodiments of the present disclosure are not limited in this regard. In yet some other embodiments of the present disclosure, the dielectric layer24may be made of a photosensitive material. The vias240may be formed by a photolithography process when the dielectric layer24is made of a photosensitive material.

Reference is made toFIG.8I. As shown inFIG.8I, conductors26are formed in the vias240and electrically connected to the conductors14through the pads22respectively. In some embodiments, the conductors26may be formed by, for example, plating a conductive metal in the vias240. The conductors26are made of copper, gold, aluminum, or combinations thereof, but various embodiments of the present disclosure are not limited in this regard. In some embodiments, the vias240may be filled with the conductors26. In some other embodiments, the conductors26may be conformally formed on sidewalls of the vias240respectively.

In some embodiments, as shown inFIG.5, two conductive lines28can be formed on the dielectric layer24with the conductor26. The conductive lines28are present on the dielectric layer24and are respectively electrically connected to the conductor26in the vias240. In practical applications, the conductive lines28can transmit high frequency signals. That is, the conductive lines28can be high frequency differential pairs transmission lines meeting high frequency (greater than about 20 GHz) transmission line requirements. It is noted that since the dielectric block12and the conductors14therein are surrounded by the shielding element20, isolation between the conductors14and/or between the conductors14and other interconnections, e.g. other conductive vias in the substrate10, can be enhanced, and therefore electromagnetic interference therebetween can be diminished.

Reference is made toFIGS.9and10.FIG.9is a perspective view of an interconnect structure3with a single end design according to some embodiments of the present disclosure.FIG.10is a cross-sectional view of the interconnect structure3ofFIG.9taken along line10according to some embodiments of the present disclosure. It should be pointed out that single-ended signaling is the opposite technique of differential signaling. In single-ended signaling, the transmitter generates a single voltage that the receiver compares with a fixed reference voltage, both relative to a common ground connection shared by both ends.

As shown inFIGS.9-10, in some embodiments of the disclosure, the interconnect structure3is provided. The interconnect structure3includes a substrate30, a dielectric block32, a conductor34, and a conductive line38. The substrate30has an opening300therein. The material(s) of the substrate30may be similar to that of the substrate10ofFIG.1and therefore are not repeated here to avoid duplicity. The dielectric block32is present in the opening300of the substrate30. The dielectric block32has one via320therein, in which the dielectric block32has a dielectric constant smaller than a dielectric constant of the substrate30. The material(s) of the dielectric block32may be similar to that of the dielectric block12ofFIG.1and therefore are not repeated here to avoid duplicity. The conductor34is present in the via320of the dielectric block32. Specifically, the conductor34is present on a sidewall of the via320. The conductive line38is present on a surface of the substrate30and is connected to the conductor34. The material(s) of the conductor34may be similar to that of the conductors14ofFIG.2and therefore are not repeated here to avoid duplicity.

In some embodiments of the disclosure, the interconnect structure3further includes a plug36plugged in the remaining via320to prevent solder from wicking through the via320during the assembly process and damaging (short-circuitry adjacent paths) the finished product. In some other embodiments of the present disclosure, the plug36may be absent from the via320. In yet some other embodiments of the present disclosure, the via320may be filled with the conductor34. The material(s) of the plug36may be similar to that of the plugs16ofFIG.1and therefore are not repeated here to avoid duplicity.

Reference is made toFIG.11.FIG.11is a flowchart of a method for manufacturing the interconnect structure ofFIG.9according to some embodiments of the present disclosure. The method begins with operation S301in which an opening is formed in a substrate. The method continues with operation S302in which a dielectric block is formed in the opening, and the dielectric block has a dielectric constant smaller than a dielectric constant of the substrate. The method continues with operation S303in which a via is formed in the dielectric block. The method continues with operation S304in which a conductor is formed in the via. The method continues with operation S305in which a plug is formed in the remaining via.

Reference is made toFIGS.12A-12E.FIGS.12A-12Eare cross-sectional views taken along line10ofFIG.9to sequentially illustrate steps for manufacturing the interconnect structure3according to some embodiments of the present disclosure. As shown inFIG.12A, an opening300is formed in the substrate30. In some embodiments of the disclosure, the opening300is formed by mechanical drilling, mechanical routing, or combinations thereof when the substrate30is an integrated circuit (IC) substrate or a printed circuit board (PCB). In some other embodiments of the present disclosure, the opening300is formed by laser drilling when the substrate30is an IC substrate, a PCB, or a dielectric layer. Although the opening300shown inFIG.12Ais a through hole, but various embodiments of the present disclosure are not limited in this regard. In some other embodiments of the present disclosure, the opening300may be a blind hole as well.

As shown inFIG.12B, a dielectric block32is formed in the opening300of the substrate30by, for example, plugging the dielectric block32into the opening300of the substrate30. In some embodiments of the present disclosure, after the dielectric block32is formed in the opening300, the excess dielectric block32out of the opening300is removed by, for example, a grinding process. Therefore, after the dielectric block32is ground, the dielectric block32is substantially level with a top surface of the substrate30.

As shown inFIG.12C, the via320is formed in the dielectric block32. In some embodiments of the disclosure, the via320is formed by mechanical drilling, mechanical routing, laser drilling, or combinations thereof, but various embodiments of the present disclosure are not limited in this regard. For example, in some other embodiments of the present disclosure, the via320can be formed by laser drilling. In yet some other embodiments of the present disclosure, the dielectric block32may be made of a photosensitive low-k material. The via320may be formed by a photolithography process when the dielectric block32is made of a photosensitive low-k material. Specifically, the dielectric block32is exposed to a pattern of intense light. The exposure to light causes a chemical change that allows some of the dielectric block32soluble in a photographic developer. Then, the photographic developer is applied onto the dielectric block32to remove the some of the dielectric block32soluble in the photographic developer to form the via320in the dielectric block32.

As shown inFIG.12D, conductor34is formed in the via320. The conductor34may be formed by, for example, plating a conductive metal at least on a sidewall of the via320. In some embodiments of the present disclosure, the conductor34is made of copper, gold, aluminum, or combinations thereof, but various embodiments of the present disclosure are not limited in this regard. The plating of the conductive metal may be performed by an electroplating process, where an electric current is used to transfer metal in an aqueous solution to a surface of the interconnect structure3including the sidewall of the via320. In order to facilitate the electroplating of the conductive metal, a seed layer (not shown) may be deposited prior to the electroplating of the conductive metal. The seed layer provides nucleation sites where the electroplated metal is initially formed. The electroplated metal deposits more uniformly on the seed layer than on a bare dielectric. Then, the conductive metal is patterned to form the conductor34. Specifically, the conductive metal may be patterned by, for example, a photolithography and etching process.

In some embodiments of the present disclosure, as shown inFIGS.9and12D, the conductive line38can be formed on the substrate30with the conductor34. The conductive line38is present on the substrate30and is respectively electrically connected to the conductor34in the via320. In practical applications, the conductive line38can transmit high frequency signals. That is, the conductive line38can be high frequency differential pairs transmission lines meeting high frequency (greater than about 20 GHz) transmission line requirements.

As shown inFIG.12E, a plug36is formed in the remaining via320. The plug36may be formed in the remaining via320by, for example, screen printing or roller printing. In some other embodiments of the present disclosure, the plug36may be made from a photosensitive material. The photosensitive material is filled into the via320and then is exposed to intense light, such as ultraviolet (UV) light, to solidify the photosensitive material. Then, the excess photosensitive material out the via320may be removed by, for example, a grinding process.

In some embodiments of the present disclosure, in operation S304inFIG.11, a conductive line38can be simultaneously formed on the substrate30with the conductor34. As shown inFIGS.9-10, in some embodiments of the present disclosure, the interconnect structure3further includes a conductive line38. The conductive line38is present on the substrate30and electrically connected to the conductor34in the via320.

The low-k dielectric block32separating the conductor34and other interconnections (e.g., other conductive vias in the substrate30) reduces parasitic capacitance between the conductor34and the interconnections, enabling faster switching speeds and lower electronic crosstalk. The method for manufacturing the interconnect structure3shown inFIGS.12A-12Eis cost effective since the manufacturing method is doable by existing tools. The interconnect structure3shown inFIG.9does not change integrated circuit (IC) substrate and/or printed circuit board design rules and the thicknesses and structures of the integrated circuit (IC) substrate and/or the printed circuit board will not be changed by applying the interconnect structure3ofFIG.9.

Reference is made toFIGS.13-14.FIG.13is a perspective view of an interconnect structure4with a single end design according to some other embodiments of the present disclosure.FIG.14is a cross-sectional view of the interconnect structure4ofFIG.13taken along line14according to some embodiments of the present disclosure. As shown inFIGS.13-14, the interconnect structure3includes a substrate30, a dielectric block32, a conductor34, a plug36, a shielding element40, a pad42, a dielectric layer44, a conductor46, and a conductive line48. The substrate30has an opening300therein. The shielding element40is present on a sidewall of the opening300. The dielectric block32is present in the opening300of the substrate30. That is, shielding element40is present between the dielectric block32and the sidewall of the opening300. The dielectric block32has one via320therein, in which the dielectric block32has a dielectric constant smaller than a dielectric constant of the substrate30. The conductor34is present in the via320of the dielectric block32. The plug36is plugged in the remaining via320. The pad44is present on the conductor36. The dielectric layer44is present on the substrate30. The dielectric layer44has a via440therein to expose the pad42. The conductor46is present in the via440and electrically connected to the conductor34through the pad42. The conductive line48is present on a surface of the dielectric layer44and electrically connected to the conductor46.

Reference is made toFIG.15.FIG.15is a flowchart of a method for manufacturing the interconnect structure ofFIG.13according to some embodiments of the present disclosure. The method begins with operation S401in which an opening is formed in a substrate. The method continues with operation S402in which a shielding element is formed on a sidewall of the opening. The method continues with operation S403in which a dielectric block is formed in the opening, and the dielectric block has a dielectric constant smaller than a dielectric constant of the substrate. The method continues with operation S404in which a first via is formed in the dielectric block. The method continues with operation S405in which a first conductor is formed in the first via, and the shielding element is present around the conductor and separated from the conductor by the dielectric block. The method continues with operation S406in which a plug is formed in the remaining first via. The method continues with operation S407in which a pad is formed on the first conductor. The method continues with operation S408in which a dielectric layer is formed on the substrate. The method continues with operation S409in which a second via is formed in the dielectric layer to expose the pad. The method continues with operation S410in which a second conductor is formed in the second via and electrically connected to the first conductor through the pad.

FIGS.16A-16Iare cross-sectional views taken along line14ofFIG.13to sequentially illustrate steps for manufacturing the interconnect structure4according to some embodiments of the present disclosure.

Reference is made toFIG.16A. Similar toFIG.12A, an opening300is formed in a substrate30. In some embodiments of the present disclosure, the opening300is formed by mechanical drilling, mechanical routing, or combinations thereof when the substrate30is an integrated circuit (IC) substrate or a printed circuit board (PCB). In some other embodiments, the opening300is formed by laser drilling when the substrate30is an IC substrate, a PCB, or a dielectric layer. Although the opening300shown inFIG.16Ais a through hole, but various embodiments of the present disclosure are not limited in this regard. In some other embodiments, the opening300may be a blind hole as well. In yet some other embodiments of the present disclosure, the substrate30may be made of a photosensitive dielectric material. The opening300may be formed by a photolithography process when the substrate30is made of a photosensitive dielectric material.

Reference is made toFIG.16B. As shown inFIG.16B, a shielding element40is formed on a sidewall of the opening300. In some embodiments, the shielding element40may be formed by, for example, plating a conductive metal in the opening300. The shielding element40may be made of copper, gold, aluminum, or combinations thereof, but various embodiments of the present disclosure are not limited in this regard.

Reference is made toFIG.16C. Similar toFIG.12B, a dielectric block32is formed in the opening300of the substrate30by, for example, plugging the dielectric block32into the opening300of the substrate30. In some embodiments of the present disclosure, after the dielectric block32is formed in the opening300, the excess dielectric block32out of the opening300is removed by, for example, a grinding process. Therefore, after the dielectric block32is ground, the dielectric block32is substantially level with a top surface of the substrate30.

Reference is made toFIG.16D. As shown inFIG.16D, a via320is formed in the dielectric block32. Similar toFIG.12C, a via320is formed in the dielectric block32. In some embodiments of the present disclosure, the via320is formed by mechanical drilling, mechanical routing, or combinations thereof, but various embodiments of the present disclosure are not limited in this regard. For example, in some other embodiments of the present disclosure, the via320can be formed by laser drilling. In yet some other embodiments of the present disclosure, the dielectric block32may be made of a photosensitive low-k material. The via320may be formed by a photolithography process when the dielectric block32is made of a photosensitive low-k material.

Reference is made toFIG.16E. Similar toFIG.12D, a conductor34is formed in the via320. The conductor34may be formed by, for example, plating conductive metal at least on a sidewall of the via320. The plating of the conductive metal may be performed by an electroplating process. In order to facilitate the electroplating of the conductive metal, a seed layer (not shown) may be deposited prior to the electroplating of the conductive metal. Then, the conductive metal is patterned to form the conductor34. Specifically, the conductive metal may be patterned by, for example, a photolithography and etching process.

Reference is made toFIG.16F. Similar toFIG.12E, a plug36is formed in the remaining via320. The plug36may be formed in the remaining via320by, for example, screen printing or roller printing. In some other embodiments of the present disclosure, the plug36may be made from a photosensitive material. The photosensitive material is filled into the via320and then is exposed to intense light, such as ultraviolet (UV) light, to solidify the photosensitive material. Then, the excess photosensitive material out of the via320may be removed by, for example, a grinding process.

Reference is made toFIG.16G. As shown inFIG.16G, a pad42is formed on the conductor34. In some embodiments, the pad42is made of a metal (e.g., Cu). In some embodiments, the pad42may be formed by, for example, depositing, but various embodiments of the present disclosure are not limited in this regard. In some other embodiments, the pad42is made of graphite powder.

Reference is made toFIG.16H. As shown inFIG.16H, a dielectric layer44is formed on the substrate30, and a via440is formed in the dielectric layer44. In some embodiments, the dielectric layer44is formed on the substrate30by, for example, laminating. In some embodiments, the dielectric layer44is formed by, for example, spin coating. In some embodiments, the via440of the dielectric layer44is formed by mechanical drilling, mechanical routing, laser drilling, or combinations thereof, but various embodiments of the present disclosure are not limited in this regard. In yet some other embodiments of the present disclosure, the dielectric layer44may be made of a photosensitive material. The via440may be formed by a photolithography process when the dielectric layer44is made of a photosensitive material.

Reference is made toFIG.16I. As shown inFIG.16I, a conductor46is formed in the via440to contact the pad42. In some embodiments, the conductor46may be formed by, for example, plating a conductive metal in the via440. In some embodiments, the via440may be filled with the conductor46. In some other embodiments, the conductor46may be conformally formed on sidewalls of the via440respectively.

In some embodiments, as shown inFIG.13, a conductive line48can be formed on the dielectric layer44with the conductor46. The conductive line48is present on the dielectric layer44and is electrically connected to the conductor46in the vias440. In practical applications, the conductive lines48can transmit high frequency signals. That is, the conductive lines48can be high frequency differential pairs transmission lines meeting high frequency (greater than about 20 GHz) transmission line requirements. It is noted that since the dielectric block32and the conductor34therein are surrounded by the shielding element40, isolation between the conductor34and other interconnections, e.g. other conductive vias in the substrate30, can be enhanced, and therefore electromagnetic interference therebetween can be diminished.

According to some embodiments, a method includes forming an opening through a substrate. A low-k dielectric block is formed in the opening. At least one first via is formed through the low-k dielectric block. A first conductor is formed in the first via.

According to some embodiments, a method includes forming an opening in a substrate. A dielectric block is formed in the opening. At least one first via is formed in the dielectric block. A first conductor is formed in the first via. A dielectric layer is formed over the substrate and the first conductor. At least one second via is formed in the dielectric layer. A second conductor is formed in the second via, such that the second conductor is electrically connected to the first conductor.

According to some embodiments, a method includes forming an opening in a substrate. A shielding element is formed on a sidewall of the opening. A dielectric block is formed in the opening, such that the dielectric block is surrounded by the shielding element. The dielectric block has a lower dielectric constant than the substrate. At least one first via is formed in the dielectric block. A first conductor is formed in the first via.

Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.