Patent ID: 12218014

DETAILED DESCRIPTION

The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

A method for forming magnetoresistive random-access memory (MRAM) may comprise: depositing a multilayer film over a wafer; forming hard masks over the multilayer film; and performing a dry etch into the multilayer film to form an array of magnetic tunnel junction (MTJs). A challenge with the method is that the dry etch employs ion bombardment for etching and, as a result, is somewhat uncontrollable. Etched material may redeposit on sidewalls of the MTJs and may lead to high leakage between fixed and free elements of the MTJs. Because of the high leakage, the redeposited material has the potential to significantly degrade yields.

To mitigate degradation in yields from sidewall redeposition, quantitative inspection may be performed to determine the amount of redeposition and to determine whether to rework a wafer. According to a first inspection method, an individual manually inspects one or a few MTJs top down using a scanning electron microscope (SEM). However, redeposited material occupies a small area when viewed top down and contrast between redeposited material and neighboring material may be low. As a result, it may be difficult for an individual to reliably assess sidewall redeposition and the sensitivity of the first inspection process may be low. Further, because inspection is performed manually, throughput may be low and the number of MTJs assessed may be low. According to a second inspection method, an individual manually prepares and inspects a cross section of one or a few MTJs using a transmission electron microscope (TEM). However, preparing the cross section is destructive and hence leads to waste of a costly wafer. Further, because preparation and inspection are performed manually, throughput may be low and the number of MTJs assessed may be low. Further yet, because of the preparation, inspection is performed ex situ and adds complexity to workflows.

Various embodiments of the present disclosure are directed towards a method for non-destructive inspection of cell etch redeposition. In some embodiments of the method, a grayscale image of a plurality of cells on a wafer is captured. The grayscale image provides a top down view of the cells and, in some embodiments, is captured in situ after etching to form the cells. In some embodiments, the grayscale image is captured using a SEM and/or the cells are MTJs. The cells are identified in the grayscale image to determine non-region of interest (non-ROI) pixels corresponding to the cells. The non-ROI pixels are subtracted from the grayscale image by an image processing device to determine ROI pixels. The ROI pixels are remaining pixels and correspond to material on sidewalls of, and in recesses between, the cells. An amount of etch redeposition on the sidewalls and in the recesses is then scored by the image processing device based on gray levels of the ROI pixels. Further, the wafer is processed based on the score. For example, if the score indicates a threshold amount of etch redeposition, the cells may be reworked (e.g., removed and reformed). Otherwise, the wafer may proceed to a next processing step for forming an integrated circuit (IC) comprising the cells.

Because the image is captured in situ, the method may be performed with little to no impact on existing workflows and with little to no preparation. Because the image is captured top down (e.g., using a SEM), the image may capture a large area and a large number of cells. Further, the method may be performed non-destructively. Because much of the method is performed by the image processing device, etch redeposition on the large number of cells may be quickly and reliability assessed. Because the method looks at gray levels of individual pixels, the method may achieve high sensitivity. Because the method simplifies the amount of etch redeposition to a score, a problematic amount of etch redeposition may be readily identified.

For some embodiments, the cells may be in a periodic pattern. For example, the cells may be in a periodic pattern when the cells are MTJs in an array. In embodiments in which the cells are in a periodic pattern, positioning within the grayscale image may be readily achieved. After locating a single cell in the grayscale image, locations for a remainder of the cells may be calculated using the location of the single cell and the periodic pattern.

With reference toFIG.1, a schematic flow diagram100of some embodiments of a method for non-destructive inspection of cell etch redeposition is provided. The method is performed after an etch forming a plurality of cells102(represented by black circles) on a wafer104. The etch may, for example, be performed by dry etching using ion bombardment, such that the etch has a high propensity for material to redeposit on sidewalls of the cells102. The cells102are spread across a plurality of IC dies106of the wafer104and may, for example, be or comprise MTJs, gate stacks of logic devices, or some other suitable cell structure.

At108, a grayscale image110(only partially shown) of the cells102at a portion of the wafer104is captured. Note that different hashes are employed to represent different gray levels. The grayscale image110provides a top down view of the cells102and may, for example, be captured by a SEM, a review SEM (RSEM), or some other suitable imaging device. Because the grayscale image110provides a top down view of the cells102, the grayscale image110may be captured non-destructively and with little to no preparation of the wafer104. This, in turn, may reduce manufacturing costs and/or increase throughput. Further, because the grayscale image110is captured top down, the grayscale image110may capture a large area and a large number of cells.

In some embodiments, the grayscale image110is captured in situ within a process chamber employed for the etch to form the cells102. For example, the etch and the image capture may be performed within a common process chamber and the wafer104may remain in the common process chamber from a beginning of the etch to an end of the image capture. In at least embodiments in which the grayscale image110is captured in situ, the method may be performed with little to no impact on existing workflows and with little to no preparation. As a result, throughput may be high. In alternative embodiments, the grayscale image110is captured ex situ and is hence captured outside the process chamber employed for the etch.

After capturing the grayscale image110, image processing is performed on the grayscale image110at112so as to assess the quantity of etch redeposition on sidewalls of the cells102. Depending upon materials etched, the etch redeposition may be conductive and may include, for example, titanium, ruthenium, tantalum, some other suitable material(s), or any combination of the foregoing. Because the etch redeposition may be conductive, the etch redeposition may increase leakage current. For example, where the cells102are MTJs, etch redeposition may increase leakage current from fixed layers to free layers. The increased leakage current may, in turn, degrade yields. In some embodiments, the image processing is wholly automated and performed by an image processing device.

At114, a non-ROI116is identified and subtracted from the grayscale image110to identify a ROI118. For clarity, this is schematically illustrated by a mask image120. The non-ROI116(illustrated by black in the mask image120) includes regions of the grayscale image110corresponding to the cells102and further includes a peripheral region of the grayscale image110. The peripheral region extends in a closed path along a periphery of the grayscale image110and may, for example, have a square ring shape or some other suitable shape. In alternative embodiments, the non-ROI116is limited to regions of the grayscale image corresponding to the cells and hence does not include the peripheral region. The ROI118(illustrated by white in the mask image120) corresponds a remainder of the grayscale image110after subtracting the non-ROI116from the grayscale image110. In other words, the ROI118corresponds to regions of the grayscale image110between the cells102.

Identification of the non-ROI116comprises identification of the cells102in the grayscale image110. In some embodiments, the cells102are randomly or pseudo randomly arranged. In at least some embodiments in which the cells102are randomly or pseudo randomly arranged, each of the cells102is individually identified manually or automatically. As to manual identification, an individual may, for example, draw a circle or some other closed shape around the cells102using a human interface device (HID) (e.g., a mouse) and a graphical user interface (GUI) displayed on display device. As to automatic identification, the image processing device may, for example, automatically identify the cells102by computer vision. In other embodiments, the cells102are arranged in a periodic pattern. For example, the cells102may be in a plurality of rows and a plurality of columns to define an array. In at least some of such embodiments, a single one, or more than one, of the cells102, but fewer than all of the cells102, is/are identified manually or automatically by computer vision and a remainder of the cells102are identified by calculating locations of the remaining cells from the location of the single cell and from the periodic pattern. When more than one of the cells102are identified manually, or automatically by computer vision, the locations of the remaining cells may be calculated more accurately.

At122, a gray level distribution124is determined for pixels of the grayscale image110in the ROI118. Such pixels may also be known as ROI pixels. In some embodiments, the ROI pixels are 8-bit pixels, such that the gray levels vary from 0-255. In other embodiments, the ROI pixels have some other suitable number of bits. The gray level distribution124includes a pixel count for each gray level or quantile of gray levels. In some embodiments, the gray level distribution124is determined automatically by the image processing device.

At126, the ROI pixels are categorized by gray level into a severe category, a slight category, and a normal category. In alternative embodiments, more or less categories are amenable. The severe category is defined by ROI pixels having a high likelihood of corresponding to etch redeposition and is illustrated by a severe ROI image128. The severe ROI image128is black and white. Further, severe ROI pixels are illustrated in white and a remainder of pixels in the grayscale image110are illustrated in black. The slight category is defined by ROI pixels having a medium likelihood of corresponding to etch redeposition and is illustrated by a slight ROI image130. The slight ROI image130is black and white. Further, slight ROI pixels are illustrated in white and a remainder of pixels in the grayscale image110are illustrated in black. The normal category is defined by a remainder of the ROI pixels, which have a low likelihood of corresponding to etch redeposition. In some embodiments, the categorization is performed automatically by the image processing device.

It has been appreciated that the likelihood of a pixel corresponding to etch redeposition is proportional to gray level. As such, ROI pixels with gray levels less than a first threshold are assigned to the normal category, and ROI pixels with gray levels greater than a second threshold greater than the first threshold are assigned to the severe category. Further, ROI pixels between the first and second thresholds are assigned to the slight category.

While the method focuses on a single grayscale image, the method will practically be repeated for a plurality of grayscale images. For example, one or more grayscale images may be captured per IC die106. Further, while image capture conditions are ideally the same while capturing the plurality of grayscale image, this may not always be the case. As such, normalization is performed while categorizing the ROI pixels using an average gray level of the ROI pixels. Particularly, the first and second thresholds are summations of the average gray level with respective offsets. For example, the first threshold may be a summation of the average gray level with a first offset, and the second threshold may be a summation of the average gray level with a second offset greater than the first offset.

Defining the first and second thresholds as above has the effect of using relative brightness differences of the ROI pixels for categorizing the ROI pixels without having to directly calculate the relative brightness differences for the ROI pixels. Particularly, relative brightness difference for a given ROI pixel is a difference between the average gray level and a gray level of the given ROI pixel. Because categorization is performed by mathematical comparisons of the gray levels of the ROI pixels to the first and second thresholds, and because the first and second thresholds are summations of the average gray level and the respective offsets, the average gray level may be subtracted from each side of the mathematical comparisons without changing the effect of the mathematical comparisons. Further, the mathematical comparisons may be rewritten as mathematical comparisons of the offsets to the relative brightness differences. Therefore, the offsets may be regarded as thresholds for categorization of the ROI pixels in the relative-brightness-difference domain.

At132, a score134is determined based on the numbers of ROI pixels in the different categories. The greater a ratio of the severe ROI pixels to a total number of ROI pixels, the higher the score. Further, in some embodiments, the greater a ratio of the slight ROI pixels to a total number of ROI pixels, the higher the score. The higher the score, the more etch redeposition on sidewalls of the cells102. In some embodiments, the scoring is performed automatically by the image processing device. In some embodiments, the score134is a percentage of ROI pixels that are severe. In other embodiments, the score134is a percentage of ROI pixels that are severe and slight.

At136, the wafer104undergoes processing based on the score134. For example, prior to the method, the wafer104may be proceeding through a series of processing steps to form an IC at each of the IC dies106. Based on the score134, the wafer104may proceed to a next processing step in the series or may otherwise undergo rework. The rework may, for example, include removing and reforming cells. The reforming may, for example, include repeating processing steps in the series.

The processing at136comprises assessing the score134to determine whether the wafer104should undergo rework. Note that the score134may be one of many other parameters assessed. To the extent that rework is deemed appropriate, the wafer104may wholly undergo rework. For example, all cells102on the wafer104may be reworked. Alternatively, only one or more select portions of the wafer104(e.g., a portion of the wafer104corresponding to the grayscale image110) may be reworked. To the extent that rework is deemed inappropriate, the wafer104may proceed to a next processing step. In some embodiments, if the score134is greater than a threshold (e.g., the amount of etch redeposition is high), the portion of wafer104corresponding to the grayscale image108is reworked.

The processing at136may be performed manually or automatically. For example, the score134may be displayed on a display device. An individual may then assess the score134and adjust processing of the wafer104as appropriated based on the score134. As another example, a process control system may automatically compare to the score134to a threshold and may automatically route the wafer104using a transport system.

With reference toFIGS.2A and2B, schematic flow diagrams200A,200B of some alternative embodiments of the method ofFIG.1are provided.

InFIG.2A, the wafer104undergoes processing at202that runs in parallel with the image processing at112. For example, a cap layer may be deposited over the cells102. In contrast withFIG.1, processing of the wafer104is in series with the image processing and is hence suspended until the imaging processing is completed. The processing at202may proceed according to a series of processing steps that is independent of the method and that is employed to form an IC at each of the IC dies106. Further, once the image processing at112is complete, the cells102may be reworked if deemed appropriate based on the score134. Otherwise, the wafer104may continue with the series of processing steps.

InFIG.2B, a plurality of grayscale images110is captured of the cells102respectively at a plurality of different portions of the wafer104. Further, the grayscale images110each individually undergoes the image processing at112. In some embodiments, a plurality of grayscale images of cells is captured per IC die106. By performing the image processing individually on the grayscale images110, a plurality of scores134individual to the grayscale images110are generated and used for processing the wafer104at136.

At136, the scores134are assessed to select which, if any portions, the wafer104should undergo rework. In some embodiments, the scores134are individually assessed and, for each score134exceeding the threshold, the corresponding portion of the wafer104is selected for rework. In alternative embodiments, the scores134are grouped and the groups are individually assessed. For example, the scores134may be grouped by IC die106or by pairs or sets of neighboring IC dies106. For each group, a composite score is calculated and, if the composite score exceeds a threshold, the corresponding portion of the wafer104is selected for rework. The composite score for a group may, for example, be an average, a median, a maximum, a minimum, or a standard deviation for the scores of the group. To the extent that rework is deemed inappropriate, the wafer104may proceed according to a series of processing steps that is independent of the method and that is employed to form an IC at each of the IC dies106. To the extent that rework is deemed appropriate, the wafer104may be wholly reworked. Alternatively, only the one or more select portions of the wafer104are reworked.

In some embodiments, a plurality of grayscale images of cells is captured per IC die106, such that each IC die106has a plurality of scores. For each IC die106, the scores of the IC die are combined into a composite score and the composite score is compared to a threshold. For example, the composite score of an IC die may be an average, a median, a maximum, a minimum, or a standard deviation for the scores of the IC die. If any of the IC dies106, or a threshold number of the IC dies106, have composite scores in excess of the threshold, the wafer104may undergo rework in which cells are removed and recreated. For example, all of the IC dies106may undergo rework. As another example, only those IC dies106having composite scores in excess of threshold may undergo rework.

While the schematic flow diagram200B ofFIG.2Bis illustrated without the processing at202ofFIG.2A, alternative embodiments of the schematic flow diagram200B may include the processing at202ofFIG.2A. As such, the wafer104may undergo processing at202that runs in parallel with the image processing at112in alternative embodiment ofFIG.2B.

With reference toFIGS.3,4,5A,5B,6-8,9A-9C,10, and11, some embodiments of the method ofFIG.1are illustrated in more detail.

As illustrated by a diagram300ofFIG.3, a wafer104is provided upon completion of etching to form cells (not shown) on the wafer104. The wafer104has a plurality of IC dies106sharing a common layout and having individual cell regions302. The cell regions302accommodate the cells and are divided into cell subregions304(demarcated by the dashed lines). The cell subregions304may, for example, have a same size as a field of view of a SEM or some other suitable imaging device used hereafter to capture gray scale images.

As illustrated byFIG.4, a grayscale image110of a plurality of cells102at a cell subregion304ofFIG.3is captured. Note that different hashes are employed to represent different gray levels. The grayscale image110provides a top down view of the cells102and may, for example, be captured by a SEM, a RSEM, or some other suitable imaging device.

As illustratedFIGS.5A and5B, a non-ROI116is identified and subtracted from the grayscale image110to identify a ROI118. InFIG.5A, this is illustrated by a mask image120in which the non-ROI116is illustrated by black and in which the ROI118is illustrated by white. InFIG.5B, this is illustrated by overlaying the black region of the mask image120(which corresponds to the non-ROI116) on the grayscale image110. The non-ROI116includes regions of the grayscale image110corresponding to the cells102and further includes a peripheral region of the grayscale image110. The ROI118corresponds a remainder of the grayscale image110after subtracting the non-ROI116and hence corresponds to regions of the grayscale image110between the cells102.

As illustrated byFIG.6, a gray level distribution124is determined for pixels of the grayscale image110in the ROI118(e.g., ROI pixels). The ROI pixels correspond to pixels that remain in the grayscale image110after subtracting pixels of the non-ROI116(e.g., non-ROI pixels). The non-ROI pixels correspond to the black region that is in the mask image120ofFIG.5Aand that is overlaid on the grayscale image110inFIG.5B. The gray level distribution124includes a pixel count for each gray level or quantile of gray levels.

As illustrated byFIG.7, an average gray level Gavgis determined from the ROI pixels. As discussed in greater detail hereafter, the average gray level Gavgis employed as a reference for normalization across multiple grayscale image.

As illustrated byFIG.8, the ROI pixels are categorized by gray level into a normal category, a severe category, and a slight category. In alternative embodiments, more or less categories are amenable. The normal category is defined by ROI pixels having a low likelihood of corresponding to etch redeposition. Such ROI pixels are identified as pixels with gray levels less than a first threshold T1. The severe category is defined by ROI pixels having a high likelihood of corresponding to etch redeposition. Such ROI pixels are identified as ROI pixels having gray levels greater than a second threshold T2. The slight category is defined by ROI pixels having a medium likelihood of corresponding to etch redeposition. Such ROI pixels are identified as ROI pixels having gray levels between the first and second thresholds T1, T2.

The first and second thresholds T1, T2are functions of the average gray level Gavgand corresponding offsets O1, O2to allow for normalization. For example, the first threshold T1may be a summation of the average gray level Gavgwith a first offset O1, and the second threshold T2may be a summation of the average gray level Gave with a second offset O2greater than the first offset O1. Defining the first and second thresholds T1, T2as above has the effect of using relative brightness differences of the ROI pixels for categorizing the ROI pixels without having to directly calculate the relative brightness differences for the ROI pixels.

Relative brightness difference for a given ROI pixel is a difference between the average gray level Gavgand a gray level of the given ROI pixel. Because categorization is performed by mathematical comparisons of the gray levels of the ROI pixels to the first and second thresholds T1, T2, and because the first and second thresholds T1, T2are summations of the average gray level Gavgand the respective offsets O1, O2, the average gray level Gavgmay be subtracted from each side of the mathematical comparisons without changing the effect of the mathematical comparisons. Further, the mathematical comparisons may be rewritten as mathematical comparisons of the offsets O1, O2to the relative brightness differences. Therefore, the offsets O1, O2may be regarded as relative-brightness-difference thresholds for categorization of the ROI pixels, whereas the first and second thresholds T1, T2may be regarded as gray-level thresholds for categorization of the ROI pixels.

As illustrated byFIGS.9A-9C, severe and slight ROI pixels are respectively illustrated in white. InFIG.9A, a slight ROI image130illustrates ROI pixels categorized as slight in white while a remainder of pixels in the grayscale image110(see, e.g.,FIG.4) are black. InFIG.9B, a severe ROI image128illustrates ROI pixels categorized as severe in white while a remainder of pixels in the grayscale image110are black. InFIG.9C, a slight/severe ROI image902illustrates ROI pixels categorized as slight and severe in white while a remainder of pixels in the grayscale image110are black.

As illustrated by a diagram1000ofFIG.10, a score134is determined for the cell subregion304to which the grayscale image110(see, e.g.,FIG.4) corresponds. The score134is determined based on the numbers of ROI pixels in the different categories. The greater a ratio of the severe ROI pixels to a total number of ROI pixels, the higher the score. Further, in some embodiments, the greater a ratio of the slight ROI pixels to a total number of ROI pixels, the higher the score. In some embodiments, the score134is the percentage of ROI pixels that are severe (e.g., the number of severe ROI pixels divided by the total number of ROI pixels times100). In other embodiments, the score134is the percentage of ROI pixels that are severe and slight. In some embodiments, the score134takes into account the number of severe and slight ROI pixels, but severe ROI pixels have a greater weight than slight ROI pixels. For example, severe ROI pixels may have 1.5-10 times the weight of slight ROI pixels in the score134. In some of these embodiments, the score134may be equal to a ratio of the severe ROI pixels to a total number of ROI pixels times a weighting factor (e.g., 1.5-10) plus a ratio of the slight ROI pixels to a total number of ROI pixels plus.

As illustrated by a diagram1100ofFIG.11, the wafer104undergoes processing based on the score134. Particularly, a determination1102is made as to whether to rework the wafer104based on the score134. The determination1102may also be based on other suitable parameters. In some embodiments, rework is deemed appropriate if the score134exceeds a threshold. To the extent that rework is deemed appropriate, the wafer104may undergo rework1104. Otherwise, the wafer104may continue proceeding through a series of processing steps begun before the method to form the IC dies106. In other words, a next process step1106in the series of processing steps may be performed.

WhileFIGS.3,4,5A,5B,6-8,9A-9C,10, and11are described with reference to a method, it will be appreciated that the structures shown inFIGS.3,4,5A,5B,6-8,9A-9C,10, and11are not limited to the method but rather may stand alone separate of the method. WhileFIGS.3,4,5A,5B.6-8,9A-9C,10, and11are described as a series of acts, it will be appreciated that the order of the acts may be altered in other embodiments. WhileFIGS.3,4,5A,5B,6-8,9A-9C,10, and11illustrate and describe as a specific set of acts, some acts that are illustrated and/or described may be omitted in other embodiments. Further, acts that are not illustrated and/or described may be included in other embodiments.

Additionally, it is to be appreciated thatFIGS.5A,5B,6-8,9A-9C, and10may be automatically or semi automatically performed by an electronic processing device. As to semi-automatic embodiments, human input may be provided while carrying out the acts atFIGS.5A,5B,6-8,9A-9C, and10. For example, human input may be provided to identify the cells102in the grayscale image110, as described with regard toFIGS.5A and5B, whereas a remainder of the image processing described with regard toFIGS.6-8,9A-9C, and10may be fully automated. As to automatic embodiments, no human input may be provided while carrying out the acts atFIGS.5A,5B,6-8,9A-9C, and10. This may, for example, allow for high throughput.

With reference toFIG.12, a block diagram1200of some embodiments of the method ofFIGS.3,4,5A,5B,6-8,9A-9C,10, and11is provided. In some embodiments, the method is performed using artificial intelligence (AI) for optimization and enhanced performance.

At1202, a grayscale image of a plurality of cells at a portion of a wafer is captured, wherein the grayscale image provides a top down view and is captured upon completion of etching to form the cells. Sec, for example,FIGS.3and4.

At1204, a non-ROI is identified in the grayscale image, wherein the non-ROI includes regions of the grayscale image corresponding to the cells. See, for example,FIGS.5A and5B.

At1206, the non-ROI is subtracted from the grayscale image to determine a ROI, wherein the ROI corresponds to a remainder of the grayscale image. See, for example,FIGS.5A and5B.

At1208, a gray level distribution for pixels of the gray scale image in the ROI is determined. See, for example,FIG.6.

At1210, an average gray level is determined for the ROI pixels. See, for example,FIG.7.

At1212, the ROI pixels are categorized by relative brightness difference into a severe category, a slight category, and a normal category, wherein a relative brightness difference for a given ROI pixel is a gray level of the given ROI pixel minus the average gray level. See, for example,FIGS.8and9A-9C.

At1214, a score is determined based on a number of severe ROI pixels, wherein the score is proportional to a ratio of severe ROI pixels to a total number of ROI pixels. See, for example,FIG.10.

At1216, the wafer is processed based on the score. See, for example,FIG.11.

While the block diagram1200ofFIG.12is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

With reference toFIGS.13,14, and15A-15C, some alternative embodiments of the images described above are provided. InFIG.13, some alternative embodiments of the grayscale image110ofFIG.4are provided in which the ellipses are removed and more detail is shown. InFIG.14, some alternative embodiments of the mask image120ofFIG.5Aare provided in which the ellipses are removed. InFIGS.15A-15C, some alternative embodiments of the slight ROI image130, the severe ROI image128, and the slight/severe ROI image902respectively inFIGS.9A-9Care provided in which the ellipses are removed.

With reference toFIG.16, some alternative embodiments of the diagram1000ofFIG.10are provided in which each of the cell subregions304has an individual score134. Note that the individual scores134of the cell subregions304are only shown for one of the IC dies106due to space constraints. The scores134are individually determined for the cell subregions304by performing the acts described with regard toFIGS.4,5A,5B,6-8,9A-9C,10, and/or acts1202-1214inFIG.12, for each of the cell subregions304.

The scores134are combined by IC die106into die scores134die. For example, the die score for a given IC die may be an average, a median, a minimum, a maximum, or a standard deviation of scores134of corresponding cell subregions304. The die scores134diemay then be employed to determine whether to rework the wafer104. For example, if a threshold number of the die scores134dieexceed a threshold, the wafer104may be wholly reworked. As another example, if any of the die scores134dieexceed a threshold, only the corresponding IC dies may be reworked. If the foregoing rework criteria are unmet, the wafer104may proceed according to a series of processing steps to form an IC at each of the IC dies106.

With reference toFIGS.17A and17B,18,19,20A,20B, and21-28, some embodiments of a method for forming an IC with non-destructive inspection of cell etch redeposition is provided. The non-destructive inspection may, for example, be performed according to the method in any ofFIGS.1,2A,2B, and12.

As illustrated by the diagrams1700A,1700B ofFIGS.17A and17B, a plurality of IC dies106is partially formed on a wafer104.FIG.17Aprovides a top layout diagram1700A, whereasFIG.17Bprovides a cross-sectional diagram1700B along a portion of line A inFIG.17A. The IC dies106have individual cell regions302. At the cell regions302, a plurality of bottom electrode vias (BEVAs)1702boverlie the wafer104at a top of an interconnect structure1704. The BEVAs1702bare conductive and include corresponding plugs1706and corresponding liners1708cupping undersides of the plugs1706. The liners1708are configured to block outward diffusion of material from the plugs1706.

The interconnect structure1704comprises a plurality of wires1710and a plurality vias1702. The vias1702include the BEVAs1702band are alternatingly stacked with the wires1710to define conductive paths from the BEVAs1702bto access transistors1712(only partially shown) underlying the interconnect structure1704on the wafer104. The wires1710and the vias1702are in an interlayer dielectric (ILD) layer1714, intermetal dielectric (IMD) layers1716, and etch stop layers (ESLs)1718that are stacked over the wafer104.

The access transistors1712are defined in part by the wafer104and comprise corresponding source/drain regions1720in the wafer104. Further, although not visible, the access transistors1712comprise corresponding gate stacks bordering the source/drain regions1720. The access transistors1712may, for example, be metal-oxide-semiconductor field-effect transistors (MOSFETs) or some other suitable type of transistor. The wafer104may, for example, be or comprise a bulk wafer of monocrystalline silicon, a silicon-on-insulator (SOI) wafer, or some other suitable type of semiconductor wafer.

In some embodiments, the access transistors1712are separated from each other by a trench isolation structure1722. The trench isolation structure1722comprises a dielectric material and may, for example, be a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, or some other suitable trench isolation structure.

As illustrated by a cross-sectional diagram1800ofFIG.18, a bottom electrode layer1802, an MTJ film1804, and a top electrode layer1806are deposited stacked over the interconnect structure1704. Note that only an upper portion of the interconnect structure1704is hereafter shown for drawing compactness. A remainder of the interconnect structure1704and other structure underlying the interconnect structure1704is as inFIG.17B. The MTJ film1804comprises a fixed layer1808, a barrier layer1810overlying the fixed layer1808, and a free layer1812overlying the barrier layer1810. The fixed layer1808and the free layer1812are ferromagnetic. Further, the fixed layer1808has a fixed magnetization, whereas the free layer1812has a magnetization that is free to change.

As illustrated by a cross-sectional diagram1900ofFIG.19, hard masks1902are formed over the top electrode layer1806respectively at locations to hereafter form MTJ cells. The hard masks1902may, for example, be or comprise silicon nitride and/or some other suitable dielectrics.

As illustrated by diagrams2000A,2000B ofFIGS.20A and20B, an etch is performed into the bottom and top electrode layers1802,1806(see, e.g.,FIG.19) and the MTJ film1804(see, e.g.,FIG.19) to form a plurality of cells102individual to and respectively on the BEVAs1702b.FIG.20Aillustrates a cross-sectional diagram2000A of the cells102, andFIG.20Billustrates a diagram2000B of an etch process tool performing the etch.

Focusing onFIG.20A, the cells102comprise individual bottom electrodes2002, individual MTJs2004respectively overlying the bottom electrodes2002, and individual top electrodes2006respectively overlying the MTJs2004. The MTJs2004comprise individual fixed elements2008, individual barrier elements2010respectively overlying the fixed elements2008, and individual free elements2012respectively overlying the barrier elements2010.

During operation of any one of the cells102, a corresponding barrier element2010selectively allows quantum mechanical tunneling of electrons through the barrier element2010. When the magnetizations of corresponding fixed and free elements2008,2012are antiparallel, quantum mechanical tunneling may be blocked. As such, the cell may have a high resistance and may be in the first data state. When the magnetizations of the fixed and free elements2008,2012are parallel, quantum mechanical tunneling may be allowed. As such, the cell may have a low resistance and may be in the second data state.

The etch is performed by ion beam etching (IBE). However, the etch may alternatively be performed by some other suitable type of dry etching using ion bombardment or some other suitable type of etching. IBE depends upon ion bombardment for etching. Particularly, kinetic energy is transferred from ions to the layer being etched to break off material of the layer. Because of the transfer of kinetic energy, etched material has a propensity to “fly” off and redeposit elsewhere in a somewhat uncontrollable manner. Depending upon the density of this etch redeposition2014, the etch redeposition2014may increase leakage current and degrade yields. For example, when the etch redeposition2014is on sidewalls of the cells102, the etch redeposition2014may create a conductive bridge that increases leakage current from the fixed elements2008to the free elements2012. The etch redeposition may, for example, be or comprise tantalum, ruthenium, some other suitable conductive material(s), or any combination of the foregoing.

Focusing onFIG.20B, a wafer table2016is in a process chamber2018and supports the wafer104(see, e.g.,FIGS.17A and17B) and hence the structure ofFIG.19. Further, the wafer table2016is configured to rotate the wafer104about an axis extending into and out of the page. An exhaust pump2020is along a bottom of the process chamber2018at an exhaust port2022of the process chamber2018. An ion beam source2024is along a top of the process chamber2018and generates an ion beam2026using process gases from a gas delivery system2028. An imaging device2030is further in the process chamber2018. The imaging device2030may, for example, be a SEM, a RSEM, or some other suitable type of imaging device. In alternative embodiments, the imaging device2030is external to the process chamber2018.

As illustrated by the diagram2100ofFIG.21, multiple grayscale images110of the cells102(see, e.g.,FIG.20A) are captured by the imaging device2030. The capture is performed in situ within the process chamber2018. By in situ, it is meant that the wafer104remains in the process chamber2018from a beginning of the etch described with regard toFIGS.20A and20Bto an end of the image capture. In alternative embodiments, the capture is performed outside the process chamber2018. The grayscale images110correspond to cells102at different portions of the wafer104. For example, as described with regard toFIGS.2B and16, each IC die106may have a plurality of grayscale images and the grayscale images of each IC die106may correspond to different portions (e.g., cell regions and/or subregions) of the IC die. In some embodiments, a tilt of the wafer104is changed in advance of the capture to better focus the field of view of the imaging device2030on the cells102.

As illustrated by the diagram2200ofFIG.22, the grayscale images110undergo processing to determine individual die scores134diefor the IC dies106. The die scores134dieare proportional to etch residue and, hence, higher scores lead to higher leakage current and lower yields. To determine the die scores134die, the grayscale images110are individually processed according to the image processing at112ofFIG.1and/or according to acts1204-1214ofFIG.12to determine individual scores (e.g.,134inFIG.1). To the extent that an IC die is associated with a single grayscale image, the score of the single grayscale image is the die score of the IC die. To the extent that an IC die is associated with a plurality of grayscale images, the scores of the grayscale images are combined into the die score of the IC die. The scores may be combined by using an average function, a median function, a minimum function, a maximum function, a standard deviation function, or some other suitable function.

Also illustrated by the diagram2200ofFIG.22, the die scores134dieof the IC dies106are assessed to determine which, if any, of the IC dies106to rework. Particularly, the die scores134dieof the IC dies106are compared to a threshold and any IC dies with score in excess of the threshold are flagged for rework. For example, the threshold may be 10, such that two of the IC dies106are flagged for rework. Note that the flagged IC dies are highlighted by boxes having thick lines. In alternative embodiments, another suitable process is performed to flag which, if any, of the IC dies106to rework. To the extent that one or more IC dies106are flagged for rework, only the one or more IC dies106flagged for rework are reworked. In alternative embodiments, the wafer104may be wholly reworked.

As illustrated by the cross-sectional diagrams2300-2500ofFIGS.23-25, the IC dies106flagged for rework atFIG.22undergo rework and, in some embodiments, the whole wafer104undergoes rework. InFIG.23, the cells102and the BEVAs1702bare removed. The removal may, for example, be performed by a chemical mechanical polish (CMP), etching, some other suitable removal process, or any combination of the foregoing. InFIG.24, the BEVAs1702bare reformed. Further, the bottom electrode layer1802, the MTJ film1804, the top electrode layer1806, and the hard masks1902are reformed as described with regard toFIGS.18and19. InFIG.25, an etch is performed into the bottom and top electrode layers1802,1806(see, e.g.,FIG.24) and the MTJ film1804(see, e.g.,FIG.24) to form the cells102.

As illustrated by the diagram2600ofFIG.26, the acts described with regard toFIGS.21and22are repeated to determine which, if any, of the IC dies106to rework. Particularly, multiple grayscale images110of the cells102are captured by the imaging device2030as described with regard toFIG.21. The grayscale images110then undergo processing to determine individual die scores134diefor the IC dies106as described with regard toFIG.22. Further, the die scores134dieare assessed to determine which, if any, of the IC dies106to rework as described with regard toFIG.22. To the extent that rework is appropriate, the acts described with regard toFIGS.23-26are repeated. To the extent that rework is inappropriate, the IC proceeds to completion. For example, the interconnect structure1704may be extended over the cells102.

As illustrated by the cross-sectional diagram2700ofFIG.27, a cap layer2702is deposited over the cells102. In some embodiments, the cap layer2702is deposited while the grayscale images110ofFIG.21undergo processing atFIG.22, such that the rework described with regard toFIGS.23-25includes removal of the cap layer2702and redeposition of the cap layer2702. In alternative embodiments, the cap layer2702is deposited only after rework of the wafer104is completed. The cap layer2702may, for example, be or comprise silicon nitride and/or some other suitable dielectric(s).

As illustrated by the cross-sectional diagram2800ofFIG.28, the interconnect structure1704is completed over the cells102. This includes forming additional wires1710and additional vias1702stacked over and electrically coupled to the cells102in an additional IMD layer1716.

WhileFIGS.17A and17B,18,19,20A,20B, and21-28are described with reference to a method, it will be appreciated that the structures shown inFIGS.17A and17B,18,19,20A,20B, and21-28are not limited to the method but rather may stand alone separate of the method. WhileFIGS.17A and17B,18,19,20A,20B, and21-28are described as a series of acts, it will be appreciated that the order of the acts may be altered in other embodiments. WhileFIGS.17A and17B,18,19,20A,20B, and21-28illustrate and describe as a specific set of acts, some acts that are illustrated and/or described may be omitted in other embodiments. Further, acts that are not illustrated and/or described may be included in other embodiments.

With reference toFIG.29, a block diagram2900of some embodiments of the method ofFIGS.17A and17B,18,19,20A,20B, and21-28is provided.

At2902, an etch on a wafer having a plurality of integrated circuit (IC) dies that are partially formed, wherein the etch forms individual regions of cells at the IC dies. See, for example,FIGS.17A,17B,18,19,20A, and20B.

At2904, grayscale images of the wafer are captured, wherein the grayscale images provide top down views of different portions of the wafer. See, for example,FIG.21.

At2906, the grayscale images are processed to determine individual die scores for the IC dies, wherein a die score of an IC die is proportional to a ratio of region-of-interest (ROI) pixels with a slight and/or severe gray level to a total number of ROI pixels, and wherein the ROI pixels are pixels localized to the region(s) of the IC die and correspond to pixels separating the cells. See, for example,FIGS.22and26.

At2908, a determination is made as to whether to rework the wafer based on the scores. See, for example,FIGS.22and26.

At2910, the wafer is reworked in response to the scores meeting rework criteria. See, for example,FIGS.23-25.

At2912, processing of the wafer continues according to a series of processing steps to form an IC at each of the IC dies in response to the scores failing rework criteria. For example, a next processing step in a series of processing steps to form an MRAM device on the wafer104may be performed. See, for example,FIGS.27and28.

While the block diagram2900ofFIG.29is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

With reference toFIG.30, a block diagram3000of some alternative embodiments of the method ofFIG.29is provided in which the method employs parallel processing of the wafer and the grayscale images. Particularly, processing of the wafer continues at2912′ while the grayscale images are processed at2906. Further, the processing of the wafer continues according to a series of processing steps to form an IC at each of the IC dies. In response to rework criteria being met, the processing according to the series of processing steps is stopped and rework is performed at2910′.

While the block diagram3000ofFIG.30is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

With reference toFIG.31, a schematic diagram3100of some embodiments of a system for forming an IC with non-destructive inspection of cell etch redeposition is provided. The system may, for example, be configured to perform any of the above described methods, including (but not limited) to the methods inFIGS.1,2A,2B,12,29, and30.

An etch process tool3102is configured to perform an etch on a wafer104to form a plurality of cells (not individually shown) spread across a plurality of IC dies106of the wafer104. The cells may, for example, be MTJ cells, logic cells, or some other suitable type of cells.FIG.20Aprovides a non-limiting example of the cells, andFIG.20Bprovides a non-limiting example of the etch process tool3102. Further,FIGS.19,20A, and20Bprovide a non-limiting example of a process for performing the etch.

An imaging device2030is associated with the etch process tool3102and is configured to capture grayscale images110of the cells while the wafer104is still in a process chamber of the etch process tool3102upon completion of the etch.FIG.21provides non-limiting examples respectively of the imaging device2030and the etch process tool3102and further provides a non-limiting example of capture of the grayscale images110. The grayscale images110provide top down views of the cells at different portions of the wafer. The imaging device2030may, for example, be a SEM or some other suitable imaging device.

An image processing device3106is configured to individually process the grayscale images110automatically or semi-automatically to determine scores134individually for the grayscale images110. The processing may, for example, be performed as described with regard to any ofFIGS.1,2A,2B, and12and/or according to acts1204-1214ofFIG.12. In some embodiments, the processing for each of the grayscale images110is performed according to the imaging processing at112ofFIG.1. A non-limiting example of the processing for a single grayscale image is as illustrated and described with regard toFIGS.3,4,5A,5B,6-8,9A-9C, and10. The image processing device3106is electronic and may, for example, be a computer, an application-specific integrated circuit (ASIC), a microcontroller, or some other suitable type of electronic device.

In some embodiments, the image processing device3106comprises an electronic processor3108and an electronic memory3110. The electronic processor3108retrieves processor executable instructions for performing the processing of the grayscale images110from the electronic memory3110. Further, the electronic processor3108executes the retrieved processor executable instructions to perform the processing of the grayscale images110. In some embodiments, the image processing device3106further comprises or is associated with a display device3112and HID3114. The display device3112may, for example, be configured to display the scores134and/or may, for example, be configured to display a GUI for interacting with the processing of the grayscale images110. The HID3114may, for example, be configured to allow an individual to interact with the processing of the grayscale images110via the GUI. For example, the HID3114may be employed by an individual to identify cells within a grayscale image while performing the acts at114ofFIG.1.

A process controller3116is configured to assess the scores134to determine how to process the wafer104. Particularly, the process controller3116is configured to determine whether to rework the wafer104or whether the wafer104should continue processing according to a series of processing steps to form an IC at each of the IC dies106. The determination may, for example, be made by grouping and/or comparing the scores134to one or more thresholds. In some embodiments, if a threshold number of the scores134exceeds a threshold, rework may be in order. Otherwise, the wafer104may proceed without rework. The assessing may, for example, be performed as described with regard to act136at any ofFIGS.1,2A, and2B, as described with regard to any ofFIGS.11,17,22, and26, as described with regard to act1216ofFIG.12, or according to any other suitable process. To the extent that the rework is in order, the process controller3116is configured to control a transport system3118to transport the wafer104to one or more rework process tool(s)3120for rework. Otherwise, the process controller3116is configured to control the transport system3118to transport the wafer104to a deposition process tool3122or some other suitable process tool for continuing processing of the wafer according to a series of processing steps to form an IC at each of the IC dies106.

In view of the foregoing, some embodiments of the present disclosure provide a method including: capturing a grayscale image of a plurality of cells on a wafer, wherein the grayscale image provides a top down view and is captured upon completion of etching to form the cells; identifying the cells in the grayscale image; subtracting a region of the grayscale image corresponding to the identified cells from the grayscale image; scoring an amount of etch residue on sidewalls of, and in recesses between, the cells based on gray levels of remaining pixels at a remainder of the grayscale image; and processing the wafer based on a score from the scoring. In some embodiments, the cells are MTJs. In some embodiments, the cells are gate stacks of logic devices. In some embodiments, the method further includes, before the scoring, subtracting a peripheral region of the grayscale image that extends in a closed path along a periphery of the grayscale image. In some embodiments, the method further includes: determining an average gray level for the remaining pixels; and determining the score as a percentage of remaining pixels with a gray level exceeding a threshold, wherein the threshold is the average gray level plus a non-zero offset. In some embodiments, the method further includes performing the etching within a process chamber, wherein the capturing is performed within the process chamber, and wherein the wafer is within the process chamber continuously from a beginning of the etching to an end of the capturing. In some embodiments, the capturing is performed by a SEM. In some embodiments, the processing includes reforming the plurality of cells in response to the score exceeding a threshold. In some embodiments, the processing includes depositing a cap layer covering the cells in response a threshold exceeding the score.

In some embodiments, the present disclosure provides another method including: capturing a grayscale image of a plurality of cells on a wafer, wherein the grayscale image provides a top down view and is captured after etching to form the cells; performing image processing on the grayscale image, the image processing including: identifying the cells in the grayscale image; determining ROI pixels based on the identifying, wherein the ROI pixels includes pixels between the identified cells but not at the identified cells; determining an average gray level amongst the ROI pixels; determining a ratio of ROI pixels with gray levels exceeding a threshold to a total number of ROI pixels, wherein the threshold is greater than the average gray level; and processing the wafer based on the ratio. In some embodiments, the method further includes forming an IC on the wafer according to a series of processing steps, wherein the series includes the etching, and wherein a next processing step in the series is performed in parallel with the image processing. In some embodiments, the method further includes forming an IC on the wafer according to a series of processing steps, wherein the series includes the etching, and wherein a next processing step in the series is performed in series with the image processing. In some embodiments, the cells are arranged in an array including a plurality of rows and a plurality of columns. In some embodiments, the cells have a periodic pattern. In some embodiments, the method further includes: providing the wafer, wherein the wafer includes a plurality of IC dies blanketed by a multilayer stack; and performing the etching into the multilayer stack to form the plurality of cells, wherein the cells are at each of the IC dies. In some embodiments, the method further includes capturing a plurality of grayscale images corresponding to different subsets of the cells, wherein the plurality of grayscale images includes the grayscale image and is captured after the etching, and wherein the image processing is performed individually on each of the grayscale images.

In some embodiments, the present disclosure further provides a system including: an etch process tool configured to etch a multilayer film atop a wafer to form a plurality of cells from the multilayer film; an imaging device configured capture a grayscale image of the cells, wherein the grayscale image provides a top down view of the cells; and an image processing device configured to: identify the cells in the grayscale image; subtract non-ROI pixels from the grayscale image, wherein the non-ROI pixels include pixels at the identified cells; and generate a score for an amount of etch residue on sidewalls of, and in recesses between, the cells based on gray levels of remaining pixels of the grayscale image; and a process controller configured to process the wafer based on the score. In some embodiments, the etch process tool includes a process chamber, wherein the imaging device is configured to capture the grayscale image while the wafer is in the process chamber. In some embodiments, the imaging device is a SEM. In some embodiments, the cells are MJTs.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.