Patent ID: 12231793

This specification includes references to “one embodiment” or “an embodiment.” The appearances of the phrases “in one embodiment” or “in an embodiment” do not necessarily refer to the same embodiment. Particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.

“Comprising.” This term is open-ended. As used in the appended claims, this term does not foreclose additional structure or steps. Consider a claim that recites: “An apparatus comprising one or more processor units . . . .” Such a claim does not foreclose the apparatus from including additional components (e.g., a network interface unit, graphics circuitry, etc.).

“Configured To.” Various units, circuits, or other components may be described or claimed as “configured to” perform a task or tasks. In such contexts, “configured to” is used to connote structure by indicating that the units/circuits/components include structure (e.g., circuitry) that performs those task or tasks during operation. As such, the unit/circuit/component can be said to be configured to perform the task even when the specified unit/circuit/component is not currently operational (e.g., is not on). The units/circuits/components used with the “configured to” language include hardware—for example, circuits, memory storing program instructions executable to implement the operation, etc. Reciting that a unit/circuit/component is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112(f) for that unit/circuit/component. Additionally, “configured to” can include generic structure (e.g., generic circuitry) that is manipulated by software and/or firmware (e.g., an FPGA or a general-purpose processor executing software) to operate in manner that is capable of performing the task(s) at issue. “Configure to” may also include adapting a manufacturing process (e.g., a semiconductor fabrication facility) to fabricate devices (e.g., integrated circuits) that are adapted to implement or perform one or more tasks.

“First,” “Second,” etc. As used herein, these terms are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). For example, a buffer circuit may be described herein as performing write operations for “first” and “second” values. The terms “first” and “second” do not necessarily imply that the first value must be written before the second value.

“Based On.” As used herein, this term is used to describe one or more factors that affect a determination. This term does not foreclose additional factors that may affect a determination. That is, a determination may be solely based on those factors or based, at least in part, on those factors. Consider the phrase “determine A based on B.” While in this case, B is a factor that affects the determination of A, such a phrase does not foreclose the determination of A from also being based on C. In other instances, A may be determined based solely on B.

It will also be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first contact could be termed a second contact, and, similarly, a second contact could be termed a first contact, without departing from the intended scope. The first contact and the second contact are both contacts, but they are not the same contact.

The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description and the appended claims, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms “includes,” “including,” “comprises,” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

As used herein, the term “if” may be construed to mean “when” or “upon” or “in response to determining” or “in response to detecting,” depending on the context. Similarly, the phrase “if it is determined” or “if [a stated condition or event] is detected” may be construed to mean “upon determining” or “in response to determining” or “upon detecting [the stated condition or event]” or “in response to detecting [the stated condition or event],” depending on the context.

DETAILED DESCRIPTION

Various embodiments described herein relate to a ramp generator circuit of an image capturing device, e.g., a camera. In some embodiments, the image capturing device may include one or more lenses and an image sensor that includes a plurality of light-gathering pixels. In some embodiments, the pixels may be organized in a pixel array having one or more rows and/or one or more columns. Light captured by the image capturing device may pass through the lenses to reach the pixels of the image sensor. When exposed to light, the pixels may accumulate electrical charge, which may be read out to generate image signals. In some embodiments, the image signals read out of the pixels originally may be analog signals, e.g., analog voltages. In some embodiments, the image capturing device may perform analog-to-digital (A-to-D) conversion to convert the image signals from analog signals to digital signals, and the digital image signals may be further processed, e.g., by an image signal processor (ISP), to generate one or more images. In some embodiments, the image capturing device may be part of an electronic device, such as a mobile device (e.g., a smart phone, tablet, laptops, etc.), robotic equipment, or security monitoring device, among others.

In some embodiments, the image capturing device may use a ramp generator circuit in performance of A-to-D conversion of image signals. For example, the ramp generator circuit may generate a linear rising (or falling) analog signal (e.g., voltage or vramp). Given a pixel, the analog image signal (e.g., an analog voltage or vreadout) read out of the pixel may be compared against the signal (e.g., vramp) from the ramp generator circuit, e.g., using a comparator circuit. The time it takes for vrampto become equal with vreadout(e.g., the time it takes for the ramp generator circuit to trip the comparator), may be measured or calculated, based on which a digital value of the analog image signal may be determined. In some embodiments, the ramp generator circuit may use a reference voltage (e.g., vref) and an integration current (e.g., iint) as input to generate the rising or falling signal (e.g., vramp) as output. Further, in some embodiments, a bias voltage (e.g., vbias) may be used in generation of the integration current (e.g., iint) Sometimes, values of the reference voltage (e.g., vref), bias voltage (e.g., vbias), and/or integration current (e.g., iint) may fluctuate due to noises, e.g., temperature variation and/or other system noises. The fluctuation may propagate and become a major contribution to noises in A-to-D conversion of image signals.

Thus, to reduce impact of the noises, in some embodiments, the ramp generator circuit may include special designs to stabilize the reference voltage, bias voltage, and/or integration current. For example, in some embodiments, the ramp generator circuit may obtain the reference voltage (e.g., vref) from a voltage supply. Fluctuation of the reference voltage (e.g., vref) obtained by the ramp generator circuit may be caused by fluctuation of the output voltage of the voltage supply. Thus, in some embodiments, the ramp generator circuit may include a switch coupled between the output voltage of the power supply and the reference voltage (e.g., vref) obtained by the ramp generator circuit. The ramp generator circuit may selectively turn off the switch to decouple the reference voltage (e.g., vref) obtained by the ramp generator circuit from the noisy output voltage of the power supply. As a result, the ramp generator circuit may substantially reduce fluctuation of the reference voltage (e.g., vref) to hold and stabilize the reference voltage.

In some embodiments, the ramp generator circuit may obtain the integration current (e.g., iint) from a current supply. In some embodiments, the current supply may be part of the ramp generator. Alternatively, in some embodiments, the current supply may be implemented on a separate device external to the ramp generator circuit. In some embodiments, the current supply may include a current mirror circuit to generate the integration current (e.g., iint). The current mirror circuit may include two semiconductor devices coupled with each other through which the first device may receive the bias voltage (e.g., vbias) from the second device, where the first device generates the integration current (e.g., iint) for the ramp generator circuit. Thus, fluctuation of the bias voltage (e.g., vbias) received by the first device may cause fluctuation of the integration current (e.g., iint) obtained by the ramp generator circuit. To reduce the fluctuation, in some embodiments, the current mirror circuit may include a switch coupled between the first and second devices of the current mirror circuit. The switch in-between may be selectively turned off to decouple the bias voltage (e.g., vbias) received by the first device from the second device. As a result, the bias voltage (e.g., vbias) may be substantially held to be stabilized. This may also lead to substantial reduction of fluctuation and thus stabilization of the integration current (e.g., iint).

In some embodiments, turning off of the above described switches may be coordinated with readout and A-to-D conversion of pixel image signals. For example, in some embodiments, the switches may be turned off before A-to-D conversion of analog image signals, such that the reference voltage (e.g., vref), bias voltage (e.g., vbias), and/or integration current (e.g., iint) may be able to stay substantially stable during the A-to-D conversion. Once the A-to-D conversion is complete, these switches may be selectively turned back on.

FIG.1is a schematic diagram of an example ramp generator circuit, according to some embodiments. InFIG.1, ramp generator circuit100may obtain reference voltage102(e.g., vref) and integration current104(e.g., iint) to generate output voltage106(e.g., vramp). In some embodiments, output voltage106(e.g., vramp) may include one or more rising or falling portions. For purposes of illustration, in this example, ramp generator circuit100is shown as a single slope ramp generator circuit where output voltage106includes only linear rising portions. In some embodiments, ramp generator circuit100may be a single slope ramp generator circuit, a dual slope generator circuit, with rising and/or falling output voltages, and the like.

InFIG.1, in some embodiments, ramp generator circuit100may include integrator circuit110having operational amplifier (op-amp)112and capacitor114. Op-amp112may include one or more input and/or output terminals. Op-amp112may receive reference voltage102(e.g., vref) and integration current104(e.g., iint) as input and generate voltage106(e.g., vramp) as output. When integration current104(e.g., iint) is zero, output voltage106(e.g., vramp) may equal to reference voltage102(e.g., vref) (e.g., vramp=vref). When integration current104(e.g., iint) is a non-zero current, the current may flow through and be integrated by capacitor114. Given the direction of integration current104(e.g., iint) is to flow out of op-amp112, this may cause a rising output voltage (e.g., vramp) from vref. If lint is a constant current, vrampmay be a linear rising voltage. Thus, by controlling iint, the rising slope, linearity, and/or value of vrampmay be adjusted. As shown inFIG.1, in some embodiments, integrator circuit110may include reset switch116coupled between the output terminal of vrampand input terminal of iint. In some embodiments, integrator circuit110may selectively turn on switch116to reset vrampto vref. As a result, vrampmay have a waveform shown inFIG.1, as an example, according to some embodiments.

As shown inFIG.1, in some embodiments, ramp generator circuit100may obtain vreffrom a voltage supply. The output voltage v1from the voltage supply may fluctuate due to noises. In some embodiments, ramp generator circuit100may have a capacitor C1 at the input terminal of integrator circuit110to stabilize vref. However, due to practical design limits, the size of C1 may not be large enough to sufficiently hold vref. Thus, in some embodiments, ramp generator circuit100may include switch120coupled between ramp generator circuit100and the output voltage v1of the voltage supply. In some embodiments, ramp generator circuit100may selectively turn off switch120to decouple vref(obtained by ramp generator100) from v1(provided by the voltage supply) to thus hold vrefstable. For purposes of illustration, in the disclosure switch120is also called a “sample-and-hold” switch. As shown at bottom ofFIG.1, for example, during “sampling” time duration132, control signal130may turn on switch120such that vrefequals v1and thus also includes noises like v1. By comparison, during “holding” time duration134, control signal130may turn off switch120such that vrefmay be held at a substantially stable value.

As shown inFIG.1, in some embodiments, a bias voltage108(e.g., vbias) may be used for generating integration current iint. In some embodiments, vbiasmay be provided from voltage v2which may have noises. Thus, to stabilize vbias, in some embodiments, sample-and-hold switch122may be coupled between vbiasand v2. In some embodiments, switch122may be selectively turned off to decouple vbiasfrom v2to thus substantially reduce fluctuation of vbiasand hold its value stable. In some embodiments, the stabilization of vbiasmay also lead to stabilization of iint. As a result, stabilization of vref, vbias, and/or iintmay also reduce noises of vramp. As vrampis used in performance of A-to-D conversion of image signals, this may thus reduce noises and improve quality of the A-to-D conversion. In some embodiments, operations of reset switch116may cause noises. Thus, as shown inFIG.1, in some embodiments, ramp generator circuit100may include capacitor C3124coupled to the input terminal of integrator circuit110to reduce impact of the noises and stabilize iint. In some embodiments, capacitors C1 and/or C2 may be implemented using off-chip capacitors residing outside ramp generator circuit100in order to use large size capacitors. In some embodiments, the switches described above inFIG.1may be implemented using any appropriate types of semiconductor switching devices, e.g., MOSFETs, BJTs, and the like.

FIGS.2A-2Bare schematic diagrams of example current supplies for generating integration currents, according to some embodiments. As described above, in some embodiments, ramp generator circuit100may obtain the integration current (e.g., iint) from a current supply. The current supply may be part of the ramp generator circuit, or a separate device external to the ramp generator circuit. Either way, the techniques disclosed herein may apply to reduce fluctuation and stabilize vbias, and/or iint. InFIG.2A, in some embodiments, current supply202may include current mirror circuit202. Current mirror circuit202may act like a current-to-current convert, which may receive input current208(e.g., iref), such as a constant or controllable current, and generate corresponding output current104based on input current208(e.g., iref). When current mirror circuit202is coupled with integrator circuit110, as shown inFIG.1, output current104then becomes the integration current (e.g., iint) obtained by the integrator circuit. In some embodiments, current mirror circuit202may include at least two semiconductor devices204and206, such as field effect transistor, bipolar junction transistors, etc. InFIG.2A, devices204and206coupled back-to-back via their control terminals, and through the connection device206may receive a bias voltage (e.g., vbias) from output voltage v2of device204. In some embodiments, the two switches may be matched having substantially the same device properties. As a result, the value of input current208(e.g., iref) may be copied to output current104(e.g., iint), and thus result in a gain of 1 between output and input. As described above, voltage v2may include noises which may propagate to vbias. Thus, in some embodiments, current mirror circuit202may include sample-and-hold switch122. In some embodiments, sample-and-hold switch122may be selectively turned off to decouple vbiasfrom v2to thus hold vbiasat a substantially stable value. As a result, the stabilization of vbiasmay also lead to stabilization of output current iint. As shown inFIG.2A, in some embodiments, current mirror circuit202may further include capacitor C2 coupled to device206to stabilize vbias. In some embodiments, the gain of current mirror circuit202may be other numbers rather than 1, e.g., by changing the number of device204(at input) and/or device206(at output). For example, in some embodiments, current mirror circuit202may have m×devices204at input and n×devices206at output, and the gain may become n/m.

FIG.2Bshows another example current supply that may be used to generate the integration current (e.g., iint) for ramp generator circuit100, according to some embodiments. As shown inFIG.2B, current supply210may include cascode current mirror circuit212. Like current mirror circuit202inFIG.2A, cascode current mirror circuit212may also include at least two semiconductor devices214and216(e.g., similar to devices204and206) at input and output, where the switches are matched having substantially the same device properties. However, unlike current mirror circuit202, cascode current mirror circuit212may further include at least one semiconductor device224and at least one semiconductor device226at input and output, respectively such as field effect transistor, bipolar junction transistors, etc. As shown inFIG.2B, device224may be coupled in series with device214to form a cascode amplifier. Compared to current mirror circuit202, the cascode amplifier formed by addition of device224may help to stabilize voltage v3by reducing the voltage's headroom and fluctuation (more than voltage v2). Similarly, device226coupled in series with device216at output may form a cascode amplifier and reduce headroom and fluctuation of voltage vcas. As a result, this may help to stabilize the output current iintgenerated by cascode current mirror circuit212. In some embodiments, device226may match device224to have substantially the same device property. Further, in some embodiments, cascode current mirror circuit212may include sample-and-hold switch222between devices214and216(e.g., similar to sample-and-hold switch122inFIG.2A), and sample-and-hold switch232between devices224and226. Switch222may be selectively turned off to decouple vbiasfrom v2(that is generated from device214) to thus hold and stabilize vbias, whereas switch232may be selectively turned off to decouple vcasfrom v3(that is generated from device224) to thus hold and stabilize vcas. In some embodiments, the two sample-and-hold switches may be turned off and on synchronously at or around the same time. Note that for purposes of illustration, the switches inFIGS.2A-2Bare shown as MOSFET devices as an example. In some embodiments, the switches may be implemented using any appropriate types of semiconductor switching devices, e.g., MOSFETs, BJTs, and the like.

As described above, in some embodiments, the sample-and-hold switches described above (e.g.,120,122,222, and/or232) may be selectively turned off to hold the reference voltage (e.g., vref), bias voltage (e.g., vbias), and/or integration current (e.g., iint) during A-to-D conversion of image signals. Thus, operations of these switches may need to be coordinated with readout and A-to-D conversion of the image signals. For example, in some embodiments, operations of these switches may be coordinated with operations of the A-to-D conversion circuit(s).FIG.3is an example timing diagram showing coordination between operations of sample-and-hold switches and A-to-D conversion of an image signal, according to some embodiments. InFIG.3, from top to bottom, the first waveform represents an amplified version of an analog image signal vreadout302read out of a pixel, the second waveform represents an output voltage vramp306generated by a ramp generator circuit (e.g., ramp generator circuit100), the third waveform represents control signal316of a reset switch (e.g., reset switch116) of the ramp generator circuit, the fourth waveform represents control signal330of the sample-and-hold switch (e.g., switch120) for reference voltage (e.g., vref) of the ramp generator circuit, and the last waveform represents control signal340of the sample-and-hold switch (e.g., switch122) for bias voltage (e.g., vbias) of the current mirror circuit. In some embodiments, the amplified pixel image signal vreadout320may be generated using an amplifier, e.g., a programmable gain amplifier (PGA). The PGA may receive the original pixel image signal (e.g., a raw voltage signal), invert the phase of the original image signal, and amplify it with a gain. The amplified image signal from the PGA may then be sampled and converted to a digital image signal, as described below. Thus, for purposes of illustration, the waveform of the amplified pixel image signal is provided inFIG.3in this example to illustrate the coordination between operations of sample-and-hold switches and A-to-D conversion of the image signal.

For purposes of illustration, in this example, A-to-D conversion of the pixel's image signal is implemented using a correlated double sampling (CDS), e.g., by an A-to-D conversion circuit, where the analog image signal may be sampled twice, the first before transfer of electrical charge out of the photodiode of the pixel and the second after transfer of the electrical charge. Thus, as shown inFIG.3, before transfer of the electrical charge, vreadout302may first be at a reset voltage. At time t5, the electrical charge starts to be transferred out of the photodiode. For purposes of illustration, in this example, vreadout302may start to rise, and at time t6, settle at a settled voltage. As described above, the A-to-D conversion of vreadout302may be performed by comparing vreadout302against output voltage vramp306of the ramp generator circuit. The time it takes for vramp306to become equal with vreadout302may be measured or calculated, based on which the digital value of vreadout302may be determined. Thus, inFIG.3, for the first sampling of CDS, the first time duration Δt1 (e.g., between t3 and t4) may be measured or calculated based on which the digital value of the first sample of vreadout302may be determined. Similarly, for the second sample of CDS, the second time duration Δt2 (e.g., between t6 and t7) may be measured or calculated based on which the digital value of the second sample of vreadout302may be determined. A difference between the two digital values may be determined, e.g., to cancel out impact of the reset voltage, and used as the final digital value of the image signal. Once the CDS is complete, the output voltage vramp306may be reset to vrefat t8.

As shown inFIG.3, in some embodiments, the ramp generator circuit may use signal316(and the reset switch, e.g.,116) to selectively reset vrampto vref, e.g., by asserting signal316for the time duration between t4 and t6 to turn on the reset switch such that the ramp generator circuit may not generate the increasing voltage. As described above, in some embodiments, the ramp generator circuit may include a sample-and-hold switch (e.g.,120) to hold and stabilize the reference voltage (e.g., vref) obtained by the ramp generator circuit, and/or a sample-and-hold switch (e.g.,122or222) to hold and stabilize the bias voltage (e.g., vbias) that is used for generating the integration current (e.g., iint) obtained by the ramp generator circuit. As shown inFIG.3, operations of the sample-and-hold switches may be controlled by the ramp generator circuit and/or the current mirror circuit using signals330and340respectively. Take the sample-and-hold switch (e.g.,120) for vrefas an example. During sampling time duration332, the switch may be selectively turned on, such that vrefmay be coupled with an output voltage provided by a voltage supply and thus may similarly include noises. In contrast, during holding time duration334, the switch may be selectively turned off, such that such that vrefmay be decoupled with the output voltage and thus held substantially stable. As shown inFIG.3, holding time duration334may start before the above described A-to-D conversion of vreadout302. For example, inFIG.3, holding time duration334may start no later than t2, when vrampstarts to rise (or in other words, when integrator circuit starts to integrate the integration current iint), or even earlier at time t1 to provide an extra interval (between t1 and t2) for vrefto fully stabilize before vrampstarts to rise. In some embodiments, holding time duration334may end after the A-to-D conversion of vreadout302. For example, inFIG.3, holding time duration334may last until time t8 when the CDS and A-to-D conversion of vreadout302is complete. Referring back toFIG.1, in some embodiments, the ramp generator circuit may include capacitor C1 coupled to the input terminal of vref. During holding time duration334, holding of vrefmay rely on capacitor C1. Thus, in some embodiments, capacitor C1 may be sized appropriately to ensure vrefmay be held substantially stable by the capacitor for at least holding time duration334.

Operation of the sample-and-hold switch (e.g.,122or222) for vbiasmay be substantially similar to the above described sample-and-hold switch (e.g.,120) for vref. For example, in some embodiments, the sample-and-hold switch (e.g.,122or222) for vbiasmay be selectively turned off before (e.g., no later than t2 or even at t1) the A-to-D conversion of vreadout302, and last until at least the A-to-D conversion is complete (e.g., until at least t8). Optionally, the sample-and-hold switch may be selectively turned on between the two samples of CDS in order to recharge capacitor C2 that is coupled to the terminal of vbias. In some embodiments, the two sample-and-hold switches for vrefand vbiasmay be controlled synchronously, e.g., turned on and off at or around the same time, as shown inFIG.3. Alternatively, in some embodiments, the two sample-and-hold switches may be operated asynchronously. In addition, as described above inFIG.2B, in some embodiments, the ramp generator circuit and/or the current supply may include one or more additional sample-and-hold switches (e.g.,232for vcas). Those switches may be operated similarly to the sample-and-hold switches for vrefand vbiasas described above. In some embodiments, all these sample-and-hold switches may be controlled synchronously to be turned on and off at or around the same time.

FIG.4is a schematic diagram of another example ramp generator circuit, according to some embodiments. As shown inFIG.4, in some embodiments, ramp generator circuit400may be similar to ramp generator circuit100inFIG.1. However, inFIG.4, the integration current (e.g., iint)404flows into, rather than out of, the integrator circuit of ramp generator circuit400. As a result, output voltage406(e.g., vramp) of ramp generator circuit400may include one or more falling portions, as shown inFIG.4, rather than the rising portions like output voltage106inFIG.1. Similarly, in some embodiments, ramp generator circuit400may include sample-and-hold switch420for reference voltage (e.g., vref) and/or sample-and-hold switch422for reference voltage (e.g., vbias). Accordingly, in some embodiments, ramp generator circuit400may selectively turn off switch420and/or422to hold vref, vbias, and/or thus iintduring A-to-D conversion of image signals.

FIGS.5A-5Bare schematic diagrams of other example current supplies for generating integration currents, according to some embodiments. As shown inFIG.5A, current mirror circuit502may be similar to current mirror circuit302inFIG.3A. However, inFIG.5A, current mirror circuit502may implement a current source, rather than a current sink like current mirror circuit302. As a result, current mirror circuit502may be able to generate the integration current (e.g., iint) to flow into, rather than out of, the integrator circuit of ramp generator circuit400as described above. Similarly, cascode current mirror circuit512inFIG.5Bmay be similar to cascode current mirror circuit312inFIG.3B, except that cascode current mirror circuit512may implement a current source instead of a current sink. As shown inFIGS.5A-5B, in some embodiments, current mirror circuit502and cascode current mirror circuit512may include sample-and-hold switches522and532that may be selectively turned off to hold voltages vbiasand vcas.

FIG.6is a block diagram showing an example image capturing device having a ramp generator circuit, according to some embodiments. As shown inFIG.6, image capturing device600, such as a camera, may include one or more lenses602, image sensor604, one or more readout circuits606, one or more A-to-D conversion circuits608, and ramp generator circuit610. In some embodiments, image capturing device600may capture light from an environment. The light may pass through lenses602to reach image sensor604. In some embodiments, image sensor104may have a plurality of light-gathering pixels. For example, image sensor604may be a CMOS image sensor, a CCD image sensor, and the like. The pixels of image sensor604may accumulate electrical charge when exposed to the light. At read out, readout circuits606may transfer the electrical charge out of photodiodes of the pixels to generate analog image signals, such as analog voltages. A-to-D conversion circuits608may convert the analog image signals to digital image signals, using the output voltage (e.g., vramp) from ramp generator circuit610, as described above. The digital image signals may be provided, e.g., to an image signal processor (ISP), to be further processed to produce corresponding one or more images. As described above, in some embodiments, ramp generator circuit610(e.g., similar to the ramp generator circuits described above) may include one or more sample-and-hold switches (e.g., similar to the sample-and-hold switches described above) that may be selected turned off to hold the reference voltage (e.g., vref), bias voltage (e.g., vbias), and/or integration current (e.g., iint) during the A-to-D conversion of the pixel image signals.

FIG.7is a block diagram of an example architecture for performing readout and A-to-D conversion of image signals of an image sensor, according to some embodiments. As shown inFIG.7, in some embodiments, an image sensor may include a plurality of light-gathering pixels704, which may be organized into a pixel array. For example, inFIG.7, pixels704may be organized into a (m×n) pixel array having (m×rows) and (n×columns), where m and n are both integers. The first column may include pixels704(1,1),704(2,1), . . . ,704(m,1), the second column may include pixels704(1,2),704(2,2), . . . ,704(m,2), and the last column may include pixels704(1,n),704(2,n) and704(m, n). Further, in some embodiments, pixels on the same column may share the same readout circuit and A-to-D conversion circuit. For example, inFIG.7, pixels704(1,1),704(2,1), . . . ,704(m,1) of the first column may share readout circuit706(1) and A-to-D conversion circuit708(1),704(1,2),704(2,2), . . . ,704(m,2) of the second column may share readout circuit706(2) and A-to-D conversion circuit708(2), and pixels704(1,n),704(2,n) and704(m, n) of the last column may share circuit706(n) and A-to-D conversion circuit708(n). Each readout circuit706and A-to-D conversion circuit708may operate similarly to the readout circuits (e.g.,606) and A-to-D conversion circuits (e.g.,608) described above. Further, as shown inFIG.7, in some embodiments, all the pixels may share the same ramp generator circuit710, which may operate similarly to the ramp generator circuits described above.

In some embodiments, image signals of pixels704of the same column may be read out and A-to-D converted sequentially, whereas image signals of pixels704of the same row may be read out and A-to-D converted synchronously at or around the same time. Take the first column as an example. From top to bottom, pixel704(1,1) may be the first to be read out by readout circuit706(1) and converted by A-to-D conversion circuit708(1), pixel704(2,1) may be the second to be read out by readout circuit706(1) and converted by A-to-D conversion circuit708(1), and so on, until pixel704(m,1) may be the last to be read out and A-to-D converted. In addition, take the first row as an example. From left to right, pixels704(1,1),704(1,2), . . . ,704(1,n) may be read out by their respective readout circuits706(1)-706(n) and converted by their respective A-to-D conversion circuit708(1)-708(n) synchronously at or around the same time.

Since image signals pixels on the same column are converted not at or around the same time, their A-to-D conversion may be subject to noises caused by fluctuation of the reference voltage (e.g., vref), bias voltage (e.g., vbias), and/or integration current (e.g., iint) of ramp generator circuit710, as described above. Thus, in some embodiments, ramp generator circuit710may use one or more sample-and-hold switches, as described above, to hold and stabilize these electrical variables to reduce the row-to-row noises. In some embodiments, operations of ramp generator circuit710may need to be coordinated with readout and A-to-D conversion of image signals, as described above, e.g., inFIG.3. Since ramp generator circuit710is shared by all the pixels704of the image arrange, operations of ramp generator circuit710may have to be coordinated with readout and A-to-D conversion of each of the pixels. In this example, pixels704of the same column may be read out and then A-to-D converted sequentially, whereas pixels704of the same row may be read out and A-to-D converted synchronously at or around the same time. Thus, in some embodiments, operations of ramp generator circuit710may be determined based on the sequential A-to-D conversion of pixels in one column. For example, ramp generator circuit710may selectively turn off the one or more sample-and-hold switches to enter (m×sampling time durations) sequentially, one before the A-to-D conversion of each of pixels704(1,1),704(2,1), . . . ,704(m,1) of the first column. As the A-to-D conversion of other columns are synchronized with the first column, the reference voltage (e.g., vref), bias voltage (e.g., vbias), and/or integration current (e.g., iint) held during the sampling time durations may be applied to pixels of the first columns, but also pixels of the other columns. Note that the above is provided only as an example for purposes of illustration. In some embodiments, the readout sequence between the row and column may be exchanged, such that pixels on the same columns may be read out at or around the same time, whereas pixels on the same row may be read out sequentially. In that case, the techniques disclosed herein may be still applied to reduce noises on column-to-column pixels.

FIG.8is a flowchart showing an example method for reducing noises of a ramp generator circuit, according to some embodiments. As shown inFIG.8, in some embodiments, a reference voltage (e.g., vref) may be obtained by a ramp generator circuit, e.g., from a voltage supply, as described above, as shown by block802. In addition, in some embodiments, an integration current (e.g., iint) may be obtained by the ramp generator circuit, e.g., from a current supply, as described above, as shown by block804. To reduce the noises, in some embodiments, the ramp generator circuit may use one or more sample-and-hold switches to hold the reference voltage (e.g., vref) and/or a bias voltage (e.g., vbias) that is used for generating the integration current (e.g., iint). For example, in some embodiments, a first sample-and-hold switch may be selectively turned off to decouple vreffrom an output voltage (e.g., v1) provided by the voltage supply to thus hold vrefobtained by the ramp generator circuit, as described above, as shown by block806. In addition, in some embodiments, a second sample-and-hold switch may be selectively turned off to hold vbiasso that iintgenerated using vbiasmay also be stabilized, as described above, as shown by block808. In some embodiments, the ramp generator circuit may use the held and stabilized vrefand iintto generate a voltage (e.g., vramp) having one or more rising and/or falling portions, as shown by block810. In some embodiments, the voltage (e.g., vramp) of the ramp generator circuit may be provided to one or more A-to-D conversion circuits to perform A-to-D conversion of image signals from pixels of an image sensor, as described above, as shown by block812.

FIG.9illustrates a schematic representation of an example device900that may include an image capturing device (e.g., a camera) having a ramp generator circuit as described above, according to some embodiments. In some embodiments, the device900may be a mobile device and/or a multifunction device. In various embodiments, the device900may be any of various types of devices, including, but not limited to, a personal computer system, desktop computer, laptop, notebook, tablet, slate, pad, or netbook computer, mainframe computer system, handheld computer, workstation, network computer, a camera, a set top box, a mobile device, an augmented reality (AR) and/or virtual reality (VR) headset, a consumer device, video game console, handheld video game device, application server, storage device, a television, a video recording device, a peripheral device such as a switch, modem, router, or in general any type of computing or electronic device.

In some embodiments, the device900may include a display system902(e.g., comprising a display and/or a touch-sensitive surface) and/or one or more cameras904. In some non-limiting embodiments, the display system902and/or one or more front-facing cameras904amay be provided at a front side of the device900, e.g., as indicated inFIG.9. Additionally, or alternatively, one or more rear-facing cameras904bmay be provided at a rear side of the device900. In some embodiments comprising multiple cameras904, some or all of the cameras may be the same as, or similar to, each other. Additionally, or alternatively, some or all of the cameras may be different from each other. In various embodiments, the location(s) and/or arrangement(s) of the camera(s)904may be different than those indicated inFIG.9.

Among other things, the device900may include memory906(e.g., comprising an operating system908and/or application(s)/program instructions910), one or more processors and/or controllers912(e.g., comprising CPU(s), memory controller(s), display controller(s), and/or camera controller(s), etc.), and/or one or more sensors916(e.g., orientation sensor(s), proximity sensor(s), and/or position sensor(s), etc.). In some embodiments, the device900may communicate with one or more other devices and/or services, such as computing device(s)918, cloud service(s)920, etc., via one or more networks922. For example, the device900may include a network interface (e.g., network interface1010) that enables the device900to transmit data to, and receive data from, the network(s)922. Additionally, or alternatively, the device900may be capable of communicating with other devices via wireless communication using any of a variety of communications standards, protocols, and/or technologies.

FIG.10illustrates a schematic block diagram of an example computing device, referred to as computer system1000, that may include or host embodiments of an image capturing device (e.g., a camera) having a ramp generator circuit, e.g., as described above, according to some embodiments. In addition, computer system1000may implement methods for controlling operations of the camera and/or for performing image processing images captured with the camera. In some embodiments, the device900(described herein with reference toFIG.9) may additionally, or alternatively, include some or all of the functional components of the computer system1000described herein.

The computer system1000may be configured to execute any or all of the embodiments described above. In different embodiments, computer system1000may be any of various types of devices, including, but not limited to, a personal computer system, desktop computer, laptop, notebook, tablet, slate, pad, or netbook computer, mainframe computer system, handheld computer, workstation, network computer, a camera, a set top box, a mobile device, an augmented reality (AR) and/or virtual reality (VR) headset, a consumer device, video game console, handheld video game device, application server, storage device, a television, a video recording device, a peripheral device such as a switch, modem, router, or in general any type of computing or electronic device.

In the illustrated embodiment, computer system1000includes one or more processors1002coupled to a system memory1004via an input/output (I/O) interface1006. Computer system1000further includes one or more cameras1008coupled to the I/O interface1006. Computer system1000further includes a network interface1010coupled to I/O interface1006, and one or more input/output devices1012, such as cursor control device1014, keyboard1016, and display(s)1018. In some cases, it is contemplated that embodiments may be implemented using a single instance of computer system1000, while in other embodiments multiple such systems, or multiple nodes making up computer system1000, may be configured to host different portions or instances of embodiments. For example, in one embodiment some elements may be implemented via one or more nodes of computer system1000that are distinct from those nodes implementing other elements.

In various embodiments, computer system1000may be a uniprocessor system including one processor1002, or a multiprocessor system including several processors1002(e.g., two, four, eight, or another suitable number). Processors1002may be any suitable processor capable of executing instructions. For example, in various embodiments processors1002may be general-purpose or embedded processors implementing any of a variety of instruction set architectures (ISAs), such as the x86, PowerPC, SPARC, or MIPS ISAs, or any other suitable ISA. Also, in some embodiments, one or more of processors1002may include additional types of processors, such as graphics processing units (GPUs), application specific integrated circuits (ASICs), etc. In multiprocessor systems, each of processors1002may commonly, but not necessarily, implement the same ISA. In some embodiments, computer system1000may be implemented as a system on a chip (SoC). For example, in some embodiments, processors1002, memory1004, I/O interface1006(e.g. a fabric), etc. may be implemented in a single SoC comprising multiple components integrated into a single chip. For example, an SoC may include multiple CPU cores, a multi-core GPU, a multi-core neural engine, cache, one or more memories, etc. integrated into a single chip. In some embodiments, an SoC embodiment may implement a reduced instruction set computing (RISC) architecture, or any other suitable architecture.

System memory1004may be configured to store program instructions1020accessible by processor1002. In various embodiments, system memory1004may be implemented using any suitable memory technology, such as static random access memory (SRAM), synchronous dynamic RAM (SDRAM), nonvolatile/Flash-type memory, or any other type of memory. Additionally, existing camera control data1022of memory1004may include any of the information or data structures used for implementing features associated with the ramp generator circuit described above. In some embodiments, program instructions1020and/or data1022may be received, sent or stored upon different types of computer-accessible media or on similar media separate from system memory1004or computer system1000. In various embodiments, some or all of the functionality described herein may be implemented via such a computer system1000.

In one embodiment, I/O interface1006may be configured to coordinate I/O traffic between processor1002, system memory1004, and any peripheral devices in the device, including network interface1010or other peripheral interfaces, such as input/output devices1012. In some embodiments, I/O interface1006may perform any necessary protocol, timing or other data transformations to convert data signals from one component (e.g., system memory1004) into a format suitable for use by another component (e.g., processor1002). In some embodiments, I/O interface1006may include support for devices attached through various types of peripheral buses, such as a variant of the Peripheral Component Interconnect (PCI) bus standard or the Universal Serial Bus (USB) standard, for example. In some embodiments, the function of I/O interface1006may be split into two or more separate components, such as a north bridge and a south bridge, for example. Also, in some embodiments some or all of the functionality of I/O interface1006, such as an interface to system memory1004, may be incorporated directly into processor1002.

Network interface1010may be configured to allow data to be exchanged between computer system1000and other devices attached to a network1024(e.g., carrier or agent devices) or between nodes of computer system1000. Network1024may in various embodiments include one or more networks including but not limited to Local Area Networks (LANs) (e.g., an Ethernet or corporate network), Wide Area Networks (WANs) (e.g., the Internet), wireless data networks, some other electronic data network, or some combination thereof. In various embodiments, network interface1010may support communication via wired or wireless general data networks, such as any suitable type of Ethernet network, for example; via telecommunications/telephony networks such as analog voice networks or digital fiber communications networks; via storage area networks such as Fibre Channel SANs, or via any other suitable type of network and/or protocol.

Input/output devices1012may, in some embodiments, include one or more display terminals, keyboards, keypads, touchpads, scanning devices, voice or optical recognition devices, or any other devices suitable for entering or accessing data by one or more computer systems1000. Multiple input/output devices1012may be present in computer system1000or may be distributed on various nodes of computer system1000. In some embodiments, similar input/output devices may be separate from computer system1000and may interact with one or more nodes of computer system1000through a wired or wireless connection, such as over network interface1010.

Those skilled in the art will appreciate that computer system1000is merely illustrative and is not intended to limit the scope of embodiments. In particular, the computer system and devices may include any combination of hardware or software that can perform the indicated functions, including computers, network devices, Internet appliances, PDAs, wireless phones, pagers, etc. Computer system1000may also be connected to other devices that are not illustrated, or instead may operate as a stand-alone system. In addition, the functionality provided by the illustrated components may in some embodiments be combined in fewer components or distributed in additional components. Similarly, in some embodiments, the functionality of some of the illustrated components may not be provided and/or other additional functionality may be available.

Those skilled in the art will also appreciate that, while various items are illustrated as being stored in memory or on storage while being used, these items or portions of them may be transferred between memory and other storage devices for purposes of memory management and data integrity. Alternatively, in other embodiments some or all of the software components may execute in memory on another device and communicate with the illustrated computer system via inter-computer communication. Some or all of the system components or data structures may also be stored (e.g., as instructions or structured data) on a computer-accessible medium or a portable article to be read by an appropriate drive, various examples of which are described above. In some embodiments, instructions stored on a computer-accessible medium separate from computer system1000may be transmitted to computer system1000via transmission media or signals such as electrical, electromagnetic, or digital signals, conveyed via a communication medium such as a network and/or a wireless link. Various embodiments may further include receiving, sending or storing instructions and/or data implemented in accordance with the foregoing description upon a computer-accessible medium. Generally speaking, a computer-accessible medium may include a non-transitory, computer-readable storage medium or memory medium such as magnetic or optical media, e.g., disk or DVD/CD-ROM, volatile or non-volatile media such as RAM (e.g. SDRAM, DDR, RDRAM, SRAM, etc.), ROM, etc. In some embodiments, a computer-accessible medium may include transmission media or signals such as electrical, electromagnetic, or digital signals, conveyed via a communication medium such as network and/or a wireless link.

The methods described herein may be implemented in software, hardware, or a combination thereof, in different embodiments. In addition, the order of the blocks of the methods may be changed, and various elements may be added, reordered, combined, omitted, modified, etc. Various modifications and changes may be made as would be obvious to a person skilled in the art having the benefit of this disclosure. The various embodiments described herein are meant to be illustrative and not limiting. Many variations, modifications, additions, and improvements are possible. Accordingly, plural instances may be provided for components described herein as a single instance. Boundaries between various components, operations and data stores are somewhat arbitrary, and particular operations are illustrated in the context of specific illustrative configurations. Other allocations of functionality are envisioned and may fall within the scope of claims that follow. Finally, structures and functionality presented as discrete components in the example configurations may be implemented as a combined structure or component. These and other variations, modifications, additions, and improvements may fall within the scope of embodiments as defined in the claims that follow.