Patent ID: 12199518

DETAILED DESCRIPTION

Some preferred embodiments of the present invention will now be described in greater detail. However, it should be recognized that the preferred embodiments of the present invention are provided for illustration rather than limiting the present invention. In addition, the present invention can be practiced in a wide range of other embodiments besides those explicitly described, and the scope of the present invention is not expressly limited except as specified in the accompanying claims.

The present invention aims to propose a flyback converter with improved over voltage protection, which improves the problem that the voltage protection point is fixed in conventional flyback converters.

Please refer toFIG.1, an application circuitry of a flyback converter with improved over-voltage protection (OVP) functionality proposed according to a preferred embodiment of the present invention, the input voltage Vin came from the utility power supply, after being filtered by the bridge rectifier101and the input capacitor C1, is rectified into a DC voltage and then output to input of the transformer103. The application circuitry includes a primary side regulating (PSR) controller105, a primary side main switch Q3, a transformer103, an auxiliary power rectifier diode D1, an auxiliary power rectifier filter capacitor C2, a start-up resistor R_ON, two demagnetization (or quasi-resonant) detection voltage divider resistors R1and R2, a RCD clamping component104including a RSN resistor, a CSN capacitor and a diode D2, a rectifier diode DO, and an output filter capacitor CO. The PSR controller105is first charged to the auxiliary power rectifier filter capacitor C2through the starting resistor R_ON, when the voltage been charged reaches the starting gate voltage of the PSR controller105, its output terminal DRV starts to output a turn-on signal to control the primary side main switch Q3to turn on. When Q3on the primary side is turned on, its on-state is subject to the built-in current limit and the slow start control voltage levels of the PSR controller105, Q3will be turned off until the turn-on signal of the next cycle is received and the ON/OFF action is repeated. AC voltage of the output winding (secondary winding) Ns of the transformer103gradually increases due to the conduction of Q3(Q3is ON) on the secondary side, then the AC voltage is filtered by the output diode DO and the output filter capacitor CO to generate an output DC voltage Vo. AC voltage of the auxiliary winding Na coupled to the primary side transformer gradually increases, and the AC voltage is filtered to generate a DC output through the auxiliary power rectifier diode D1and filter capacitor C2, which provides the power required by the PSR controller105and replaces the power supply functionality of the starting resistor R_ON.

In a preferred embodiment, the PSR controller105is an integrated circuit controller (controller IC).

In a preferred embodiment, the main switch Q3(switching device) is a metal oxide semiconductor field effect transistor (MOSFET).

When the flyback converter energizes the transformer103during turn-on (t_on) period, the input voltage Vin of the flyback converter can be detected by the primary to auxiliary winding turns ratio Np/Na of the transformer103and the voltage Vaux measured on the auxiliary winding Na.

Auxiliary winding Na combined with voltage divider resistors R1and R2(voltage divider circuit) is connected to the FB pin as an external detection circuit109for quasi-resonant (QR) mode and OVP detections.

The current detection circuit107is electrically connected to the drain of the MOSFET transistor (main switch Q3) and the CS pin of the PSR controller105for detecting the current signal of the MOSFET transistor.

Referring toFIG.2, it shows the charging and discharging waveforms in sequence (from top to bottom) detected by DRV(OUT), FB, and CS pins of the PSR controller105in the flyback converter.FIG.2shows that when the flyback converter is in t_on period, the voltage detected by the FB pin is −(Na/Np)×VDC_BNI(because the auxiliary winding Na is out of phase with the primary winding Np), which is a fixed negative value.

Referring toFIG.1andFIG.2, if a feedback circuit is used to lock the voltage value VFBof the FB pin to zero volt (will be discussed inFIG.4) when designing the detection circuit for OVP of the flyback converter, which can result the following outcomes. During the t_on period of the flyback converter, the external detection circuit109for OVP will generate a current IFBflowing through the FB pin, one of the voltage divider resistor R1and the auxiliary winding Na, and the value of IFBis (1/R1)×(Na/Np)×Vpri; when the flyback converter is in the t_off, i.e. in turn-off, period, the external detection circuit109for OVP does not generate current.

Referring toFIG.3, it shows the detection circuit for OVP of the flyback converter, during the t_on period of the flyback converter, the external detection circuit109will generate a current IFBflowing through the FB pin, the voltage divider resistor R1and the auxiliary winding Na, where the current IFBis represented by a dashed arrow.

Please refer toFIG.4, which is a circuit diagram of the detection circuit for OVP inside the PSR controller105according to the present invention, as shown inFIG.4, the circuit includes an operational amplifier (OPA)211, a transistor Q4(a first transistor), and a current mirror consisting of a plurality of transistors Q1(a second transistor) and Q2(a third transistor). The positive input terminal (+) of the OPA211is grounded. The negative input terminal (−) of the OPA211is coupled to the source of the transistor Q4and the FB pin of the PSR controller105, where the FB pin is coupled to the external detection circuit109(FIG.1). Therefore, the voltage value at the FB pin has been locked to zero volt. The gate of the transistor Q4is coupled to the output terminal of the OPA211. The current IFBis generated from the drain of the transistor Q4, and the level (value) of the current IFBis

(N⁢a/N⁢p)×VpriR⁢1,
where Na/Np is the ratio of the auxiliary winding to the primary winding, Vpri is the voltage of the primary winding, and R1is one of the voltage divider resistors (refer toFIG.1,FIG.3).

The drain of the transistor Q1is coupled to the drain of the transistor Q4to receive the current IFB. The gates of the transistors Q1and Q2are coupled to each other and to the drains of the transistors Q1and Q4, and the sources of the transistors Q1and Q2are coupled to the supply voltage Vcc.

In a preferred embodiment, the first transistor is a N-type metal oxide semiconductor field effect transistor (NMOSFET).

In a preferred embodiment, the second transistor is a P-type metal oxide semiconductor field effect transistor (PMOSFET).

In a preferred embodiment, the third transistor is a P-type metal oxide semiconductor field effect transistor (PMOSFET).

The current IMis generated at the drain of the transistor Q2according to the current IFB, which means that the current mirror receives the current IFBand mirrors the current IFBto generate the current IM. Therefore, IMdepends on the relevant parameters of the transistors Q1and Q2, and there is a proportional relationship between IMand IFB. If the transistors Q1and Q2are identical, IMis equal to IFB.

A current source213generate a current has a predetermined current value IVINOVP_TH, one end is coupled to the drain of the transistor Q2and the other end is grounded.

A buffer215has an input terminal coupled to the current source213and the drain of the transistor Q2, and an output terminal coupled to the input terminal of the OVP circuit of the flyback converter for enabling or disabling the OVP circuit. The buffer215can output a digital signal 0 or 1 according to the comparison between IMgenerated by the current mirror and a preset current value IVINOVP_TH. When the input voltage Vin undergoes large transient changes, the output voltage Vpri exceeds the rated value, which will be reflected on IFBand IM, the level of current IFBis

(N⁢a/N⁢p)×VpriR⁢1.
Therefore, when the current IMis greater than the preset current value IVINOVP_TH, the buffer215outputs digital signal 1, OVP circuit of the flyback converter is then triggered to protect the PSR controller105, otherwise the buffer215outputs digital signal 0, OVP circuit of the flyback converter will be in sleep state.

While various embodiments of the present invention have been described above, it should be understood that they have been presented by a way of example and not limitation. Numerous modifications and variations within the scope of the invention are possible. The present invention should only be defined in accordance with the following claims and their equivalents.