Patent ID: 12255248

DETAILED DESCRIPTION

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure. It will be understood, however, by those skilled in the art that the disclosed aspects may be practiced without these specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail to not obscure the subject matter disclosed herein.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment disclosed herein. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” or “according to one embodiment” (or other phrases having similar import) in various places throughout this specification may not necessarily all be referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In this regard, as used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not to be construed as necessarily preferred or advantageous over other embodiments. Additionally, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Also, depending on the context of discussion herein, a singular term may include the corresponding plural forms and a plural term may include the corresponding singular form. Similarly, a hyphenated term (e.g., “two-dimensional,” “pre-determined, etc.) may be occasionally interchangeably used with a corresponding non-hyphenated version (e.g., “two dimensional,” “predetermined,” etc.), and a capitalized entry may be interchangeably used with a corresponding non-capitalized version. Such occasional interchangeable uses shall not be considered inconsistent with each other.

Also, depending on the context of discussion herein, a singular term may include the corresponding plural forms and a plural term may include the corresponding singular form. It is further noted that various figures (including component diagrams) shown and discussed herein are for illustrative purpose only, and are not drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, if considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and/or analogous elements.

The terminology used herein is for the purpose of describing some example embodiments only and is not intended to be limiting of the claimed subject matter. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be understood that when an element or layer is referred to as being on, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numerals refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

The terms “first,” “second,” etc., as used herein, are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless explicitly defined as such. Furthermore, the same reference numerals may be used across two or more figures to refer to parts, components, blocks, circuits, units, or modules having the same or similar functionality. Such usage is, however, for simplicity of illustration and case of discussion only; it does not imply that the construction or architectural details of such components or units are the same across all embodiments or such commonly-referenced parts/modules are the only way to implement some of the example embodiments disclosed herein.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As used herein, the term “module” refers to any combination of software, firmware and/or hardware configured to provide the functionality described herein in connection with a module. For example, software may be embodied as a software package, code and/or instruction set or instructions, and the term “hardware,” as used in any implementation described herein, may include, for example, singly or in any combination, an assembly, hardwired circuitry, programmable circuitry, state machine circuitry, and/or firmware that stores instructions executed by programmable circuitry. The modules may, collectively or individually, be embodied as circuitry that forms part of a larger system, for example, but not limited to, an integrated circuit (IC), system on-a-chip (SoC), an assembly, and so forth.

The electronic or electric devices and/or any other relevant devices or components according to embodiments of the present disclosure described herein may be implemented utilizing any suitable hardware, firmware (e.g. an application-specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices may be formed on one integrated circuit (IC) chip or on separate IC chips. Further, the various components of these devices may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), formed on one substrate or other appropriate architectures. Further, the various components of these devices may be a process or thread, running on one or more processors, in one or more computing devices, executing computer program instructions and interacting with other system components for performing the various functionalities described herein. The computer program instructions are stored in a memory which may be implemented in a computing device using a standard memory device, such as, for example, a random-access memory (RAM). The computer program instructions may also be stored in other non-transitory computer readable media such as, for example, a CD-ROM, flash drive, or the like. Also, a person of skill in the art should recognize that the functionality of various computing devices may be combined or integrated into a single computing device, or the functionality of a particular computing device may be distributed across one or more other computing devices without departing from the spirit and scope of the exemplary embodiments of the present disclosure.

Referring toFIGS.1A-1C, a conventional structure for the backside contact area to a semiconductor device is depicted, according to an example embodiment of the present disclosure. Backside contact area and backside contact structure are used interchangeably herein. The semiconductor device structure100is depicted with front-side and backside contacts, the details of which will be provided. The semiconductor device structure100may have a suitable thickness.

Before delving into the specifics of the semiconductor device structure100, it is important to note that the backside contact area110shown inFIGS.1B and1Chas a negative slope. In some embodiments, negative slope is when the diameter of a backside contact area (BSCA)110nearest the transistor101(e.g., first diameter d00) is wider than the diameter of the BSCA110furthest from the transistor structure (e.g., second diameter d01). When the backside contact area has a negative slope, issues such as bad metal filling properties and metal over-filling are prevalent. A negative slope could also make a void inside during metal filling, which could lead to a disconnect between the contact metal to source/drain116b, as we have explored in U.S. patent application Ser. No. 18/197,381. As such, U.S. patent application Ser. No. 18/197,381 is incorporated by reference herein in its entirety. However, when a BSCA (e.g., BSCA210shown inFIG.2) has a positive slope (e.g., a positive slope value), the limitations associated with a negative slope, as described herein, can be avoided. As used herein, “positive slope value” or “positive slope” (described in more detail below, in reference to the description forFIG.2) is when the diameter of the BSCA (e.g., backside contact area210shown inFIG.2) nearest the transistor structure201is smaller than the diameter of the BSCA210furthest from the transistor structure201.

Referring now toFIG.1in greater detail, a semiconductor device structure100having front-side and back-side contacts is shown. The semiconductor device structure100includes a substrate layer126, which may comprise a low-K dielectric ILD material such as SiO2. In other embodiments, the substrate layer126may be made of any material distinct from SiO2. The substrate layer126may have any suitable thickness. For example, the substrate layer may have a thickness in the range from 1000 Angstroms to 2000 Angstroms.

Semiconductor device101is disposed on the substrate layer126, with a first semiconductor side adjacent to substrate layer126and a second semiconductor side adjacent to a middle-of-line (MOL) layer112. The semiconductor device101may include any active or passive devices, such as FET transistors, BJTs, diodes, resistors, etc. In the embodiment shown inFIG.1, semiconductor device101is a FET transistor, comprising a first source-drain116a, a second source-drain116bseparated from the first source-drain116ain the X direction (perpendicular to the Y direction).

The semiconductor device101also includes a channel120connecting the first and second source-drains116a-bin the X direction and a gate structure118adjacent to, and at least partially enveloping or surrounding the channel structure120.

The source-drains may be terminals for the semiconductor device101and may be on opposing sides of the channel structure120. Thus, the illustrated semiconductor device101may be a nanosheet FET transistor. In other embodiments, the semiconductor device101may be a finFET transistor, nanowire transistor, planar transistor, or any other form of transistor having one or more terminals. Alternatively, semiconductor device101may comprise various passive devices such as diodes, resistors, etc. having one or more terminals.

Upon the semiconductor device101and opposite the substrate126may be a middle-of-line (MOL) layer112. The MOL layer112may comprise a bulk low-K dielectric ILD material such as SiO2. Within the MOL layer112may be formed one or more contact plugs114that contact a source-drain116aof semiconductor device101from above, as well as one or more contact vias107, contacting the contact plug114from above, and contacting a metal line108of the back-end-of-line (BEOL) layers106from below, as will be discussed further below. The contact plug114may include cobalt, tungsten, molibdenium, ruthenium, a transition metal with barrier metal, or barrier-less metal, among other similar possibilities. In alternative embodiments, contact plug114(and associated via107) may instead provide contact between a metal line108of the BEOL layers106and the gate118, providing for signal routing. In this example, the metal line108may be a signal routing metal line.

Upon the MOL layer112(that is, stacked in the Y direction), and opposite the semiconductor device101, may be a group of layers collectively called the back-end-of-line (BEOL) layers106. BEOL layers106may comprise a bulk low-K dielectric ILD material such as SiO2. Within the BEOL layers106are a series of stacks of metal lines108within a series of metal layers (one shown for convenience), the metal lines108running parallel to the major surfaces of the substrate and the BEOL layers106. The metal lines108may be adjacent to and contact vias such as via107to provide power or signals to semiconductor device101. The metal lines108within BEOL106may be connected by vias in a similar manner, but are not shown here for brevity reasons. One of ordinary skill in the art would recognize the connections within BEOL layers106.

Upon the BEOL layers106there may be a bonding oxide104which may be a silicon oxide of 3000-5000 Angstroms in thickness. In other embodiments, the thickness of bonding oxide104may be outside the range of 3000-5000 Angstroms.

Upon the bonding oxide104may be a carrier wafer102which may be a bulk silicon wafer.

Importantly, the substrate126also comprises at least one metal line that may serve as a backside power rail (BPR) which is not shown. To connect the backside power rail to the source-drain116bof the semiconductor device101, a backside contact area110is formed, thus allowing power to flow from power rail (not shown) to source-drain116b.

However, some methods of forming the backside contact110, can cause significant issues with the metal filling within backside contact area110. For example, contact plug110may include cobolt, tungsten, molybdenum, ruthenium, a transition metal with barrier metal, or barrier-less metal. A negative slope from the frontside could cause a number of issues, including a high risk for the backside contact area110to be overfilled. As illustrated inFIG.1C, the shape of backside contact area110, (e.g., the negative slope of BSCA110, in which the diameter of the BSCA110nearest the transistor101is wider than the diameter of the BSCA110furthest from the transistor structure101), may lead to overfilling of the metal in the BSCA110, potentially damaging the functionality of any circuit including semiconductor device101.

FIG.2depicts a profile improvement of a backside contact area to a semiconductor device, according to an example embodiment of the present disclosure.

Semiconductor device structure200may be similar in some ways to semiconductor device structure100. For example, semiconductor device101may have similar properties to semiconductor device201, carrier wafer102may have similar properties to carrier wafer203, bonding oxide104may have similar properties to bonding oxide205, BEOL layers106may have similar properties to BEOL layers206, metal lines108may have similar properties to metal lines208, MOL112may have similar properties to MOL212, contact plug114may have similar properties to contact plug214, source drain116a-bmay have similar properties to source drain216a-b, channel120may have similar properties to channel220, interlayer122may have similar properties to interlayer222, BDI structure124may have similar properties to BDI structure224, substrate126may have similar properties to substrate226. BDI124may have a composition that prevents silicide formation. For example, BDI124may be one composed entirely or partially of one of the following: SiBCN, SiO2, SiN, SiCO. In some embodiments, semiconductor device structure200has elements and properties that are significantly different from semiconductor device structure100, including but not limited to backside contact area210. Other similarities to semiconductor device structure100may exist that are not explicitly recited herein.

As used herein, profile improvement of the BSCA210may refer to an improvement in the overall structure or geometry of the BSCA210, allowing for improved metal filling properties. As will be described with reference toFIGS.3A-3I, it is important to note, among other aspects, that the backside contact structure210is shown with a pattern of layers (which may be repeating) including at least one truncated-cone shaped portion202(also referred to herein as first portion202) and one cylindrical-shaped portion204(also referred to herein as second portion204). In some embodiments the method for forming the backside contact area210(as described inFIGS.3A-3I) having at least one truncated-cone shaped portion202and one cylindrical shaped portion204is, among other features, a significant difference leading to the profile improvement of backside contact structure210inFIG.2. In some embodiments, as will be described in greater detail, the backside contact area210includes at least first portion202and second portion204. The method used to form BSCA210is described in greater detail in the description forFIGS.3A-3I. The improved profile of backside contact area210results in an average “positive” slope, which in turn reduces the likelihood of metal overfilling when depositing the metal of backside contact area210.

The semiconductor device structure200includes a substrate layer226, which may comprise a low-K dielectric ILD material such as SiO2. In other embodiments, the substrate layer226may be made of any material distinct from SiO2. The substrate layer226may have any suitable thickness. For example, the substrate layer may have a thickness in the range from 1000 Angstroms to 2000 Angstroms.

Semiconductor device201is disposed on the substrate layer226, with a first semiconductor side adjacent to substrate layer226and a second semiconductor side adjacent to a middle-of-line (MOL) layer212. The semiconductor device201may be formed in the Y direction, and may include any active or passive devices, such as FET transistors, BJTs, diodes, resistors, etc. In the embodiment shown inFIG.2, semiconductor device201is a FET transistor, comprising a first source-drain216a, a second source-drain216bseparated from the first source-drain216ain the X direction (perpendicular to the Y direction).

The semiconductor device201also includes a channel220connecting the first and second source-drains116a-bin the X direction and a gate structure218adjacent to, and at least partially enveloping or surrounding the channel structure220. The source-drains may be terminals for the semiconductor device201and may be on opposing sides of the channel structure220. Thus, the illustrated semiconductor device201may be a nanosheet transistor. In other embodiments, the semiconductor device201may be a FinFET transistor, nanowire transistor, planar transistor, or any other form of transistor having one or more terminals. Alternatively, semiconductor device201may comprise various passive devices such as diodes, resistors, etc. having one or more terminals.

Upon the semiconductor device201and opposite the substrate226may be a middle-of-line (MOL) layer212. The MOL layer212may comprise a bulk low-K dielectric ILD material such as SiO2. Within the MOL layer212may be formed one or more contact plugs214that contact a source-drain216aof semiconductor device201from above, as well as one or more contact vias207, contacting the contact plug214from above, and contacting a metal line208of the back-end-of-line (BEOL) layers206from below, as will be discussed further below. The contact plug214may include cobolt, tungsten, molibdenium, ruthenium, a transition metal with barrier metal, or barrier-less metal.

Upon the MOL layer212(that is, stacked in the Y direction), and opposite the semiconductor device201, may be a group of layers collectively called the back-end-of-line (BEOL) layers206. BEOL layers206may comprise a bulk low-K dielectric ILD material such as SiO2. Within the BEOL layers206are a series of stacks of metal lines208within a series of metal layers (one shown for convenience), the metal lines208running parallel to the major surfaces of the substrate and the BEOL layers206. The metal lines208may be adjacent to and contact vias such as via207to provide power or signals to semiconductor device201. The metal lines208within BEOL206may be connected by vias in a similar manner, but are not shown here for brevity reasons. One of ordinary skill in the art would recognize the connections within BEOL layers206.

Upon the BEOL layers206there may be a bonding oxide205which may be a silicon oxide of 3000-5000 Angstroms in thickness.

Upon the bonding oxide205may be a carrier wafer215which may be a bulk silicon wafer.

Importantly, the substrate226also comprises at least one metal line that may serve as a backside power rail (BPR). To connect the backside power rail (not shown) to the source-drain216bof the semiconductor device201, a backside contact area210(also referred to herein as backside contact structure210) is formed, thus allowing power to flow from power rail to source-drain216b.

The backside contact structure210may at least include, a first portion202and a second portion204, as shown inFIG.3. The first portion202may be partially within source-drain216b. The two side-walls202a-bof the first portion202are adjacent to and contact the source-drain region216b, BDI224and substrate226. The first portion202may have a positive slope. The first portion202has a first diameter, d1and a second diameter d2. The first diameter d1may be equal to the diameter of top-most portion of BSCA210within source/drain region216b. The backside contact structure210has a positive slope when the diameter, d1of first portion202, adjacent or nearest to semiconductor device201is small and a second diameter, d2distal from the semiconductor device201is larger than diameter d1. With this wide to narrow conical geometry, a positive slope is formed in first portion202when the second diameter d2is wider than first diameter d1. The ratio of wide to narrow proportion or ratio may depend on the diameter of the source/drain216b. Second diameter d2of first portion202may depend on the diameter d1of first portion202.

The backside contact structure210may also include a second portion204adjacent to, directly contacting and beneath the first portion202. The second portion204may have a cylindrical shape having a substantially constant third diameter, d3throughout the entire second portion204and having an infinite slope. The “infinite slope” is defined as the third diameter, d3being substantially constant and equal to the diameter of the portion(s) directly interfacing with it (in this example, second diameter, d2of first portion202). The second portion204extends from the first portion202to a distance further away from the source/drain216b. In certain embodiments, the overall BSCA210may have a profile composed of any number greater than or equal to 1 of a continuous infinite slope (e.g., second portion204and other portions identical to second portion204) and positive slope segments (e.g., first portion202).

Importantly, the first portion202and second portion204may be covered in a liner and the liner may sequentially include a first region272, a second region273and a third region274. The first portion202may include the first region272of the liner, the second region273of the liner, and the third region274of the liner.

The first region272of the liner may be within the source drain, the first region272may comprise either a Ta silicide liner or a Ti silicide liner. In some embodiments, an alternative material may be used that achieves similar properties as the Ti silicide or Ta silicide liner. The second region273may be between the first region272and the third region274, and coplanar with the BDI. The second region273and may be comprised of a Ti/TiN liner. In some embodiments, second region273may be comprised of a Ta/TaN liner. The third region274may be below the second region273and the third region274and may be comprised of a Ti silicide liner or a Ta silicide liner. In some embodiments, the liner may be entirely comprised of a Ti silicide liner. In other embodiments, the liner may be comprised of a Ti silicide liner with the exception of the second region273. In some embodiments, the entirety of the liner (including the first region272, second region273, third region274) may have a thickness between 1-8 nm. If PVD Ti is used, the thickness of the liner may be between 6-8 nm. If CVD Ti is used, the thickness of the liner may be between 2-5 nm.

FIG.3A-3Idepict forming an improved backside contact area210(shown inFIG.2) of a semiconductor device structure200, according to an example embodiment of the present disclosure. In some embodiments, the profile improvement to backside contact area210is an improvement over the backside contact area110discussed inFIG.1.

FIG.3Adepicts providing a contact a placeholder hole, according to some embodiments. Placeholder hole280may connect the backside power rail to the first source/drain structure216b, the contact placeholder hole having: a first portion contacting the first source/drain structure, having a positive slope, a second portion adjacent to the first portion having an infinite slope and extending from the first portion to a distance further distal from the first source/drain216b.

FIG.3Bdepicts providing placeholder252in the placeholder hole, according to some embodiments. It is important to note that althoughFIG.3Bshows placeholder252, the placeholder may be provided by a user or external entity. In some embodiments, providing the placeholder252includes providing a contact placeholder connecting the backside power rail (not shown) to the first source/drain structure216b, the placeholder having: a first portion contacting the first source/drain structure216b, having a positive slope value, a second portion adjacent to the first portion having an infinite slope and extending from the first portion to a distance further distal from the first source/drain. A thin Si capping layer211may be used to prevent source/drain216bepi damage during the placeholder removal process from the backside.

FIG.3Cdepicts removal of the SiGe layer250from semiconductor device structure200. In some embodiments, a wet recess process is used before SiGe250removal. As such, the placeholder252recess may be avoided during Si removal. Further, the top opening254of a BSCA209bcan be increased due to backside Si recess, as shown inFIG.3C.

Next, as shown inFIG.3C, the placeholder252is removed, forming BSCA209bwith a “wide” opening portion254. In some embodiments, first diameter255aand second diameter255bof BSCA209bmay be substantially similar in length.

In some embodiments, when the placeholder252is removed by ammonia based wet chemical, it also recesses the BSCA209c. Since the top portion of the BSCA209c(e.g., the portion within source/drain216b) is exposed first, the top of the BSCA209cis removed more than bottom, causing a wide top opening as shown inFIG.3C.

Next, as shown in FIG. the Si capping layer211may be removed completely (e.g., through a Si dry etching process). The Si dry etching process creates a, resulting BSCA209cthat exhibits a first portion (e.g., first portion202shown inFIG.2) that has a first truncated-cone shaped structure, the first portion202having a positive slope and a second portion204(e.g., second portion204shown inFIG.2) that has a conical shaped structure, the second portion204having an infinite slope. In other words, first portion202included first diameter d1within source/drain region216band a second diameter d2further from the first/source drain region216b, the first diameter d1being smaller than the second diameter d2. The second portion204includes third diameter d3, where the third diameter d3is substantially constant and equal to the second diameter d2. The epitaxy recess depth may be from10˜30 nm. In other embodiments, the depth may be outside this range. A deep epitaxy recess may also help to decrease interface resistance due to increased contact area. In some embodiments, etching into the source/drain216bmay also be also evident inFIG.3D. The profile improvement in BSCA209cwhen compared to BSCA209binFIG.3Bis noticeable when comparing the overall profile of BSCA209band BSCA209c.

Next, as shown inFIG.3Eshow the process which makes amorphous epi and recrystallization epi using ion implantation or laser anneal in the BSCA209d.

In order to achieve low contact resistance, ion implantation and a doping process is used. Also, for doping activation, laser anneal may be needed especially for nFET. So,FIG.3Emeans doping activated and crystalized epi process to make good silicide atFIGS.3F and3G. Next, as shown inFIG.3F, Ti/TiN may be deposited over the BSCA209eand further on a portion of substrate226. In some embodiments, Ta/TaN may be used instead of Ti/TiN. PVD, ALD and CVD processes are used for Ti/TiN layer. During the Ti/TiN deposition, Silicide can be formed at the interface between Si and Ti.

Turning toFIG.3G, semiconductor device300undergoes a laser annealing step, forming a silicide liner over the BSCA209f. Ti silicide may surround the BSCA209fbecause Ti/TiN barrier metal is deposited before Si removal.

In some embodiments, the laser annealing step is optional and may also be substituted with another step that results in similar physical and chemical properties. The liner includes a first region272, a second region273and a third region274, as previously described in the description forFIG.2. An outer portion260of substrate226also forms a silicide liner. The smooth texture provided through laser annealing and the chemical composition as a silicide may provide improved connectivity. Importantly, as discussed inFIG.2, Ti/TiN (or alternatively Ta/TaN) remains present at second region273and does not form a silicide layer, since it is in contact with the BDI224.

Turning toFIG.3H, the deposition of a metal layer and chemical mechanical polishing (CMP) step is depicted. This creates the finalized BSCA210, and which may further polish the substrate226to a fine plane, removing any silicide liner from outer portion260(outer portion260is shown inFIG.3F).

Turning toFIG.3I, Si layer226(also referred to herein as substrate226) is removed. Although it is not depicted in the figures, a first interlayer dielectric (ILD) structure may be formed on the source/drain region structures216a-216b. In some embodiments, a low k-based ILD substrate is deposited on BDI structure224and around the BSCA210. The low k-based ILD substrate may be a Si-based substrate.

FIGS.4A-4Care flowcharts for a process (depicted inFIGS.3A-3I) for forming a backside contact structure illustrated inFIG.2, according to an example embodiment of the present disclosure.

The method4000which further includes forming operation4001is illustrated visually in at leastFIGS.3A-3I. More specifically, forming a bottleneck-shaped backside contact structure in semiconductor device200is shown inFIGS.2and3I, where the semiconductor device200has two sides in a substrate226and partially within the first source/drain structure216a-b of the semiconductor device, wherein the semiconductor device has one or more source/drain structures216a-b, one or more channel structures and wherein the substrate is on a first side of the semiconductor device.

As shown inFIG.2, the bottleneck-shaped backside contact structure210has a first side partially within the first source/drain structure216b, a second side contacting a backside power rail (not shown), and a liner extending from the first side to the backside power rail. The liner includes a first region272of either a Ta silicide liner or a Ti silicide liner, a second region273comprised of a Ti/TiN liner, and a third region274comprised of either a Ta silicide liner or a Ti silicide liner.

The backside contact structure210includes a first portion202having a positive slope value and a second portion204, adjacent to the first portion, wherein the second portion has a slope that is greater than the positive slope. For example, the slope of the second portion can be any value that is greater than the value of the positive slope (e.g., the slope of the first portion). Forming the bottleneck-shaped backside contact structure210includes: removing a backside Si layer250; removing a placeholder252and performing dry etching on the substrate.

The method4000which further includes forming operation4004is illustrated visually in at leastFIG.3A-3C. More specifically, forming the bottleneck-shaped backside contact structure210includes: removing a backside Si layer250shown in3A and3B where SiGe layer250is removed. Further, the method2004of removing a placeholder252is shown inFIGS.3B and3Cwhere placeholder252is removed. The method4004of performing dry etching on the substrate is shown in 3D where dry etching of backside contact structure209cforms a unique backside contact profile.

The method4000which further includes performing operation4005is illustrated visually in at leastFIG.3E. Specifically, performing a Ti/TiN deposition282in a backside contact void209eis depicted. In some embodiments, Ta/TaN may be used instead of Ti/TiN.

The method4000which further includes performing operation4006is illustrated visually in at leastFIG.3F. Specifically, performing a laser anneal step over the Ti/TiN deposition282is depicted, forming a liner comprised of a first region272, a second region273and a third region274.

The method4000which further includes forming operation4007is illustrated visually in at leastFIG.3H. Specifically, forming a metallization in the backside contact.

The method4000which further includes performing operation4008is illustrated visually in at leastFIG.3H. Specifically, performing chemical mechanical polish after forming the metallization, forming: the first portion of the bottleneck-shaped backside contact structure partially within the first source/drain structure, having a first slope that is a positive slope value, the second portion of the bottleneck-shaped backside contact structure adjacent to the first portion having a second slope value that is greater than the first slope value and extending from the first portion to a distance further distal from the first source/drain.

The method4000which further includes forming operation4009, illustrated visually in at leastFIG.3I. More specifically, forming4009a bottleneck-shaped backside contact structure210in the backside contact void is shown throughoutFIGS.3A-3I, the resulting backside contact structure depicted inFIG.3I.

FIG.5depicts a semiconductor package2102according to an example embodiment of the present disclosure. The semiconductor package2102may include a processor2200and semiconductor units2300that are mounted on a substrate2100. The processor2200and/or the semiconductor units2300may include one or more of the semiconductor devices200ofFIG.2described above.

FIG.6depicts a schematic block diagram of an electronic system according to an example embodiment.

Referring toFIG.6, an electronic system3000in accordance with an embodiment may include a microprocessor3100, a memory3200, and a user interface3300that perform data communication using a bus3400. The microprocessor3100may include a central processing unit (CPU) or an application processor (AP). The electronic system3000may further include a random-access memory (RAM)3500in direct communication with the microprocessor3100.

The microprocessor3100and/or the RAM3500may be implemented in a single module or package. The user interface3300may be used to input data to the electronic system3000, or output data from the electronic system3000. For example, the user interface3300may include a keyboard, a touch pad, a touch screen, a mouse, a scanner, a voice detector, a liquid crystal display (LCD), a micro light-emitting device (LED), an organic light-emitting diode (OLED) device, an active-matrix light-emitting diode (AMOLED) device, a printer, a lighting, or various other input/output devices without limitation. The memory3200may store operational codes of the microprocessor3100, data processed by the microprocessor3100, or data received from an external device. The memory3200may include a memory controller, a hard disk, or a solid-state drive (SSD).

At least the microprocessor3100, the memory3200and/or the RAM3500in the electronic system3000may be the semiconductor devices201ofFIG.2.

Embodiments of the subject matter and the operations described in this specification may be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Embodiments of the subject matter described in this specification may be implemented as one or more computer programs, i.e., one or more modules of computer-program instructions, encoded on computer-storage medium for execution by, or to control the operation of data-processing apparatus. Alternatively, or additionally, the program instructions can be encoded on an artificially-generated propagated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, which is generated to encode information for transmission to suitable receiver apparatus for execution by a data processing apparatus. A computer-storage medium can be, or be included in, a computer-readable storage device, a computer-readable storage substrate, a random or serial-access memory array or device, or a combination thereof. Moreover, while a computer-storage medium is not a propagated signal, a computer-storage medium may be a source or destination of computer-program instructions encoded in an artificially-generated propagated signal. The computer-storage medium can also be, or be included in, one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices). Additionally, the operations described in this specification may be implemented as operations performed by a data-processing apparatus on data stored on one or more computer-readable storage devices or received from other sources.

While this specification may contain many specific implementation details, the implementation details should not be construed as limitations on the scope of any claimed subject matter, but rather be construed as descriptions of features specific to particular embodiments. Certain features that are described in this specification in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination may in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

Thus, particular embodiments of the subject matter have been described herein. Other embodiments are within the scope of the following claims. In some cases, the actions set forth in the claims may be performed in a different order and still achieve desirable results. Additionally, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.

As will be recognized by those skilled in the art, the innovative concepts described herein may be modified and varied over a wide range of applications. Accordingly, the scope of claimed subject matter should not be limited to any of the specific exemplary teachings discussed above, but is instead defined by the following claims.

The abstract is provided to comply with 37 C.F.R. Section 1.72 (b) requiring an abstract that will allow the reader to ascertain the nature and gist of the technical disclosure. It is submitted with the understanding that it will not be used to limit or interpret the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.