Patent ID: 12218143

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The description of the embodiments refers to the attached drawings to illustrate specific embodiments in which the present invention can be implemented. The directional terms mentioned in the present invention, such as “above”, “below”, “front”, “back”, “left”, “right”, “inside”, “outside”, “side”, etc., are only directions for referring to the attached drawings. Therefore, the directional terms are used to describe and understand the present invention, rather than to limit the present invention. In the figure, units with similar structures are indicated by the same reference numerals.

In the description of this application, the terms “first” and “second” are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present application, “plurality” means two or more than two, unless otherwise specifically defined.

In the description of the present application, it should be noted that the terms “installation”, “connected to”, or “connection” should be understood in a broad sense, unless otherwise specified and limited. For example, it can be a fixed connection, a detachable connection, or an integral connection. It can be mechanically connected, electrically connected, or can be communicated with each other. It can be directly connected or indirectly connected through an intermediary. It can be a communication between two elements or an interaction relationship between two elements. For one of ordinary skill in the art, the specific meanings of the above terms in the application can be understood according to specific circumstances.

The technical solution of the present application will be described with reference to the following specific embodiments.

The present application provides an array substrate, as shown inFIG.1andFIG.7. The array substrate includes a substrate100, an active layer200disposed on the substrate100, a first insulating layer300disposed on the substrate100and the active layer200, a first metal layer400disposed on the first insulating layer300, a second insulating layer500disposed on the substrate100, the active layer200, the first insulating layer300, and the first metal layer400and covering the first insulating layer300and the first metal layer400, and a second metal layer600disposed on the second insulating layer500.

The array substrate includes a TFT area. The first metal layer400includes a gate sub-layer located in the TFT area. The second metal layer600includes a source-drain metal sub-layer located in the TFT area, and the TFT area includes an active layer exposed area2located between the gate sub-layer and the source-drain metal sub-layer. The array substrate includes a barrier layer700located above the active layer200, wherein an orthographic projection of the barrier layer700on the active layer200at least partially covers an orthographic projection of the active layer exposed area2on the active layer200.

It is understandable that the present current-driven display devices such as organic light-emitting diode displays, mini light-emitting diodes, and micro light-emitting diodes require thin film transistors with larger current passing capacity and better device stability. Therefore, top-gate self-aligned oxide semiconductor thin film transistors with higher carrier mobility, less parasitic capacitance, and low leakage current are generally used. However, because thin film transistors with top gate structures have no film barrier in the area between the gate and the source and drain, an active layer is easily permeated by water and oxygen or directly irradiated by light, which affects the performance of TFT devices, and reduces weather resistance of the TFT devices. In this embodiment, a barrier layer700is provided at the active layer exposed area2between the gate sub-layer and the source-drain metal sub-layers, so that the orthographic projection of the barrier layer700on the active layer200at least partially covers the orthographic projection of the active layer exposed area2on the active layer200. The barrier layer700not only plays a role in blocking water and oxygen, but also blocks direct irradiation of light to the active layer200at the active layer exposed area2. This prevents the structure of the thin film transistor from being permeated by water and oxygen or directly irradiated by light to affect the performance of thin film transistor devices, thereby improving the weather resistance of the thin film transistor devices.

It should be noted that, as shown inFIG.2, it is a structural schematic diagram of a pixel driving circuit, wherein the pixel driving circuit is used to drive a light-emitting element. Wherein, the pixel driving circuit includes at least a switch thin film transistor T2, a reset detection thin film transistor T3, a storage capacitor Cst, and a driving thin film transistor T1for generating a driving current. In this embodiment, the thin film transistors are arranged in the TFT area. Specifically, the switch thin film transistor T2and the driving thin film transistor T1can be arranged in the TFT area. Furthermore, the first metal layer400may not only include the gate sub-layer, but also may include structures such as gate traces. In addition to the source-drain metal sub-layer, the second metal layer600may also include trace structures such as data lines and storage capacitor lines, which are not limited herein.

In one embodiment, the barrier layer700is disposed on the second insulating layer500, and the barrier layer700and the second metal layer600are formed in the same process. It is understandable that the barrier layer700can be made of the same material as the second metal layer600. Furthermore, the barrier layer700and the second metal layer600can be formed on the second insulating layer500by the same process. Specifically, the material of the barrier layer700and the second metal layer600can be a metal material or a metal oxide material.

In one embodiment, as shown inFIG.1andFIG.7, the TFT area includes a driving TFT sub-area10, and the gate sub-layer includes a first gate410located in the driving TFT sub-area10. The source-drain metal sub-layer includes a first source610and a first drain620located in the driving TFT sub-area10. The active layer exposed area2includes a first exposed sub-area21located between the first source610and the first gate410and a second exposed sub-area22located between the first drain620and the first gate410. The barrier layer700includes a first barrier sub-layer710, and the active layer200includes a first active sub-layer210located in the driving TFT sub-area10.

The orthographic projection of the first barrier sub-layer710on the first active sub-layer210at least partially covers the orthographic projection of the first exposed sub-area21on the first active sub-layer210, and/or the orthographic projection of the first barrier sub-layer710on the first active sub-layer210at least partially covers the orthographic projection of the second exposed sub-area22on the first active sub-layer210.

It can be understood that the first source610, the first drain620, and the first barrier sub-layer710are arranged in the same layer. The first source610, the first drain620, and the first barrier sub-layer710can be formed by the same process and have an integrally formed structure. The driving thin film transistor T1can be provided in the driving TFT sub-area10. In this embodiment, the driving thin film transistor T1may include the first gate410, the first source610, and the first drain620. The first source610is connected to a mini light-emitting diode800. The orthographic projection of the first barrier sub-layer710on the first active sub-layer210at least partially covers the orthographic projection of the first exposed sub-area21on the first active sub-layer210, and/or the orthographic projection of the first barrier sub-layer710on the first active sub-layer210at least partially covers the orthographic projection of the second exposed sub-area22on the first active sub-layer210so that the first barrier sub-layer710at least partially covers the portion of the first active sub-layer210located in the first exposed sub-area21and/or the second exposed sub-area22. It has the effect of blocking water and oxygen and preventing direct light to a certain extent.

In one embodiment, as shown inFIG.1toFIG.2, the orthographic projection of the first barrier sub-layer710on the first active sub-layer210at least partially covers the orthographic projection of the first gate410on the first active sub-layer210. It is understandable that when the orthographic projection of the first barrier sub-layer710on the first active sub-layer210at least partially covers the orthographic projection of the first gate410on the first active sub-layer210, the first barrier sub-layer710can form a capacitor with the first gate410. Specifically, as shown inFIG.2, in the driving thin film transistor T1, when the first gate410receives a data voltage signal Vdatato turn on the first drain620and the first drain620to drive the display, the capacitance formed by the first barrier sub-layer710and the first gate410can improve the electrical characteristics such as voltage retention of the driving thin film transistor T1.

In one embodiment, as shown inFIG.1, the first barrier sub-layer710includes a barrier body711disposed above the first gate410, a first branch712extending from one end of the barrier body711to the first exposed sub-area21, and a second branch713extending from another end of the barrier body711to the second exposed sub-area22. An orthographic projection of the barrier body711on the first active sub-layer210covers an orthographic projection of the first gate410on the first active sub-layer210. An end of the first branch712away from the barrier body711is connected to the first source610, or an end of the second branch713away from the barrier body711is connected to the first drain620.

It is understandable that the first barrier sub-layer710includes a barrier body711disposed above the first gate410and a first branch712and a second branch713respectively extending from both ends of the barrier body711to the first exposed sub-area21and the second exposed sub-area22. In this case, the first barrier sub-layer710may completely cover the first gate410. Compared with the first barrier sub-layer710partially covering the first gate410, the capacitance formed by the first barrier sub-layer710and the first gate410is increased, and the voltage retention and other electrical characteristics of the driving thin film transistor T1are maximized. In addition, by adopting a structure in which an end of the first branch712away from the barrier body711is connected to the first source610or an end of the second branch713away from the barrier body711is connected to the first drain620, the first barrier sub-layer710can at least completely cover the orthographic projection of the first exposed sub-area21or the second exposed sub-area22on the first active sub-layer210. Specifically, when the end of the first branch712away from the barrier body711is connected to the first source610, the first branch712in the first barrier sub-layer710completely covers the orthographic projection of the first exposed sub-area21on the first active sub-layer210, and when the end of the second branch713away from the barrier body711is connected to the first drain620, the second branch713in the first barrier sub-layer710completely covers the orthographic projection of the second exposed sub-area22on the first active sub-layer210. On the basis of maximizing the improvement of the voltage retention and other electrical characteristics of the driving thin film transistor T1, it also maximizes the shielding area of the first barrier sub-layer710to the first active sub-layer210. This ensures that the first barrier sub-layer710has certain water and oxygen barrier and light-shielding effects on the first active sub-layer210.

It should be noted that the first branch712, the second branch713, and the barrier body711can be configured in other forms. One of the first branch712or the second branch713is connected to the barrier body711, and the other one is spaced apart from the barrier body711. It may also be that the first branch712, the second branch713, and the barrier body711are arranged at intervals. In addition, based on the above structure, the orthographic projection of the barrier body711on the first active sub-layer210can be set to partially cover the orthographic projection of the first gate410on the first active sub-layer. In this situation, the orthographic projection of the first branch712on the first active sub-layer210can be set to completely cover the orthographic projection of the first exposed sub-area21on the first active sub-layer210. In addition, the orthographic projection of the second branch713on the first active sub-layer210is set to completely cover the orthographic projection of the second exposed sub-area22on the first active sub-layer210, which is not limited herein.

In one embodiment, as shown inFIG.1, the TFT area includes a switch TFT sub-area20. The gate sub-layer includes a second gate420located in the switch TFT sub-area20. The source-drain metal sub-layer includes a second source630and a second drain640located in the switch TFT sub-area20. The active layer exposed area2includes a third exposed sub-area23located between the second source630and the second gate420and a fourth exposed sub-area24located between the second drain640and the second gate420. The barrier layer700includes a second barrier sub-layer720, and the active layer200includes a second active sub-layer220located in the switch TFT sub-area20. The orthographic projection of the second barrier sub-layer720on the second active sub-layer220at least partially covers the orthographic projection of the third exposed sub-area23on the second active sub-layer220, and/or the orthographic projection of the second barrier sub-layer720on the second active sub-layer220at least partially covers the orthographic projection of the fourth exposed sub-area24on the second active sub-layer220.

It can be understood that the second source630, the second drain640, and the second barrier sub-layer720are arranged in the same layer. The second source630, the second drain640, and the second barrier sub-layer720can be formed by the same process and have an integrally formed structure. A data switch thin film transistor T2can be arranged in the switch TFT sub-area20. In this embodiment, the data switch thin film transistor T2may include the second gate420, the second source630, and the second drain640. The orthographic projection of the second barrier sub-layer720on the second active sub-layer220at least partially covers the orthographic projection of the third exposed sub-area23on the second active sub-layer220, and/or the orthographic projection of the second barrier sub-layer720on the second active sub-layer220at least partially covers the orthographic projection of the fourth exposed sub-area24on the second active sub-layer220so that the second barrier sub-layer720at least partially covers a part of the second active sub-layer220located in the third exposed sub-area23and/or the fourth exposed sub-area24. It has the effect of blocking water and oxygen and preventing direct light to a certain extent.

In one embodiment, as shown inFIG.1, the second barrier sub-layer720includes first sub-segments721or second sub-segments722arranged at intervals. An orthographic projection of the first sub-segment721on the second active sub-layer220covers an orthographic projection of the third exposed sub-area23on the second active sub-layer220, and an orthographic projection of the second sub-segment722on the second active sub-layer220covers an orthographic projection of the fourth exposed sub-area24on the second active sub-layer220.

It can be understood that the orthographic projection of the first sub-segment721on the second active sub-layer220is set to completely cover the orthographic projection of the third exposed sub-area23on the second active sub-layer220, and the orthographic projection of the second sub-segment722on the second active sub-layer220is set to completely cover the orthographic projection of the fourth exposed sub-area24on the second active sub-layer220. In this way, the second barrier sub-layer720can completely cover the part of the second active sub-layer220located in the third exposed sub-area23and the fourth exposed sub-area24. This exerts good water and oxygen barrier properties and prevents light from directly irradiating the third exposed sub-area23and fourth exposed sub-area24.

In one embodiment, as shown inFIG.1, the first sub-segment721is connected to the second source630, and the second sub-segment722is connected to the second drain640. An end of the first sub-segment721away from the second source630extends above the second gate420, and/or an end of the second sub-segment722away from the second drain640extends above the second gate420.

It is understandable that a data switch thin film transistor T2can be provided in the switch TFT sub-area20. In this embodiment, the data switch thin film transistor T2includes the second gate420, the second source630, and the second drain640. Specifically, the data switch thin film transistor T2needs to function as a data switch in the pixel circuit, that is, to charge and discharge. In this embodiment, an end of the first sub-segment721away from the second source630extends above the second gate420, and/or an end of the second sub-segment722away from the second drain640extends above the second gate420. That is, the orthographic projection of the first sub-segment721and/or the second sub-segment722on the second active sub-layer220partially covers the orthographic projection of the second gate420on the second active sub-layer220. In addition, the first sub-segment721and the second sub-segment722are arranged at intervals, so as to ensure that the second barrier sub-layer720does not completely cover the second gate420and to prevent the formation of a capacitance between the second barrier sub-layer720and the second gate420which causes a decrease in the charge and discharge sensitivity of the data switch thin film transistor T2. This ensures the charge and discharge sensitivity of the data switch thin film transistor T2. Specifically, the distance between the first sub-segment721and the second sub-segment722is greater than 2 um.

It should be noted that an end of the first sub-segment721away from the second source630extends above the second gate420, and/or an end of the second sub-segment722away from the second drain640extends above the second gate420. It is possible to increase the water and oxygen barrier capacity and the area that blocks direct light rays of the first sub-segment721and/or the second sub-segment722. On the basis of maximizing the prevention of the formation of capacitance with the second gate420to reduce the charge and discharge sensitivity of the data switch thin film transistor T2, the water and oxygen blocking capacity and the function of blocking light irradiation of the first sub-segment721and the second sub-segment722are maximized.

In one embodiment, as shown inFIG.1, the array substrate further includes a storage capacitor area30. The first metal layer400includes a first electrode plate430located in the storage capacitor area30. The second metal layer600includes a second electrode plate650located in the storage capacitor area30. An end of the second electrode plate650is connected to the second source630or the second drain640. In this embodiment, an end of the second electrode plate650is connected to the second source630.

The orthographic projection of the second electrode plate650on the substrate100at least partially covers the orthographic projection of the first electrode plate430on the substrate100.

It can be understood that, as shown inFIG.1toFIG.2, the storage capacitor area30can be used to set a storage capacitor Cst. In this embodiment, the first metal layer400includes a first electrode plate430located in the storage capacitor area30, and the second metal layer600includes a second electrode plate650located in the storage capacitor area30. The orthographic projection of the second electrode plate650on the substrate100at least partially covers the orthographic projection of the first electrode plate430on the substrate100. The storage capacitor Cstmay include the first electrode plate430and the second electrode plate650. Certainly, the orthographic projection of the second electrode plate650on the substrate100can completely cover the orthographic projection of the first electrode plate430on the substrate100, thereby increasing the facing area of the first electrode plate430and the second electrode plate650. Specifically, the size of the facing area of the first electrode plate430and the second electrode plate650can be adjusted according to the requirements for the size of the storage capacitor Cst. In addition, the second electrode plate650can also be connected to the second source630or the second drain640, and the second electrode plate650, the second source630, and the second drain640can be manufactured by the same process and are integrally formed.

The present application further provides a manufacturing method of an array substrate, as shown inFIG.3, including following steps:

S10: As shown inFIG.4, providing a substrate100and forming an active layer200on the substrate100, wherein the array substrate includes a TFT area. Specifically, the active layer200can be formed by coating and patterning on the substrate100. The material of the active layer200may be an oxide semiconductor material such as indium gallium zinc oxide (IGZO).

S20: As shown inFIG.5, forming a first insulating layer300on the substrate100and the active layer200, and forming a first metal layer400on the first insulating layer300, wherein the first metal layer400includes a gate sub-layer formed in the TFT area. Specifically, the first insulating layer300is a gate insulating layer. The first metal layer400includes a first gate410and a second gate420located in the TFT area. The first insulating layer300may be formed by patterning using the first gate410and the second gate420as a mask.

S30: As shown inFIG.6, forming a second insulating layer500on the substrate100, the active layer200, the first insulating layer300, and the first metal layer400to cover the first insulating layer300and the first metal layer400.

S40: Forming a second metal layer600on the second insulating layer500, wherein the second metal layer600includes a source-drain metal sub-layer formed in the TFT area.

S50: Forming a barrier layer700above the active layer200, wherein the TFT area includes an active layer exposed area2located between the gate sub-layer and the source-drain metal sublayer, and an orthographic projection of the barrier layer700on the active layer200at least partially covers an orthographic projection of the active layer exposed area2on the active layer200.

It is understandable that, as shown inFIG.7, the material of the source-drain metal sub-layers may be the same as the material of the barrier layer700. In addition, the source-drain metal sub-layers and the barrier layer700are manufactured by the same process, so that the source-drain metal sub-layers and the barrier layer700are integrally formed. It prevents the structure of the thin film transistor from affecting the performance of the device due to the penetration of water and oxygen or the direct irradiation of light. On the basis of improving the weather resistance of the thin film transistor device, it also prevents the increase of the production cost caused by the additional processes. In addition, it should be noted that in step S20: After forming the first insulating layer300and the first metal layer400, it may further include a step of metalizing the connecting portions of the active layer200and the first source610, the first drain620, the second source630, and the second drain640.

As described above, in this application, a barrier layer700is provided at the active layer exposed area2between the gate sub-layer and the source-drain metal sub-layers, so that the orthographic projection of the barrier layer700on the active layer200at least partially covers the orthographic projection of the active layer exposed area2on the active layer200. The barrier layer700not only plays a role in blocking water and oxygen, but also blocks direct irradiation of light to the active layer200at the active layer exposed area. This prevents the structure of the thin film transistor from being permeated by water and oxygen or directly irradiated by light to affect the performance of thin film transistor devices, thereby improving the weather resistance of the thin film transistor devices.

As mentioned above, although the present invention has been disclosed in preferred embodiments, the preferred embodiments are not intended to limit the present invention. One of ordinary skill in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention is subject to the scope defined by the claims.