Patent ID: 12237315

DETAILED DESCRIPTION

In general, according to one embodiment, there is provided a semiconductor device including a support, multiple first chips, a first sealing portion, a second chip, multiple first terminals and a second terminal. The multiple first chips are stacked on the support. The first sealing portion seals multiple first chips and has a recessed portion including a bottom surface separated from multiple first chips on a surface opposite to the support. The second chip is disposed in the recessed portion and has a function different from a function of the first chips. The multiple first terminals correspond to multiple first chips, each of multiple first terminals extending in a stacking direction from a surface of the first chip opposite to the support and penetrating the first sealing portion. The second terminal is disposed on a surface of the second chip opposite to the support.

Exemplary embodiments of a semiconductor device will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments.

First Embodiment

The semiconductor device according to the first embodiment is configured such that a plurality of chips is stacked and a terminal (vertical wire) extends from each chip in the stacking direction. A semiconductor device1configured as illustrated, for example, inFIG.1.FIG.1is a cross-sectional view illustrating a configuration of the semiconductor device1. Hereinafter, a direction perpendicular to the main surface of a support2is referred to as a Z direction, and two directions straight to each other in a plane perpendicular to the Z direction are respectively referred to as an X direction and a Y direction.

The semiconductor device1includes the support2, a plurality of chips3-1to3-8, a sealing portion4, a chip5, a plurality of terminals6-1to6-8, a plurality of terminals7-1to7-4, a sealing portion22, external electrodes23, a substrate10, and a sealing portion21.

The support2is a plate-shaped member extending in the XY direction. The support2has a rectangular shape in XY plan view. The support2has rigidity suitable for supporting multiple chips3-1to3-8. The support2can be formed of a material suitable for having predetermined rigidity (for example, glass, glass cloth, and silicon).

Multiple chips3-1to3-8are disposed on an −Z side of the support2, and can be stacked stepwise half by half. Multiple chips3-1to3-4are stacked stepwise on a −Y side of multiple chips3-5to3-8. Multiple chips3-5to3-8are stacked stepwise on a +Y side of multiple chips3-5to3-8. Each of the chips3-1to3-8has a function different from that of the chip5, and is, for example, a memory chip capable of data storage.

The sealing portion4seals multiple chips3-1to3-8. The sealing portion4can be formed of a first insulator having thermoplasticity such as mold resin. The sealing portion4has a front surface4aand a back surface4b. The back surface4bis in contact with the support2. The front surface4ais a main surface opposite to the support2. The sealing portion4has a recessed portion4a1on the front surface4a. The recessed portion4a1is a space recessed from the front surface4aof the sealing portion4to a side. The recessed portion4a1can take any shape as long as the chip5can be accommodated. The recessed portion4a1is disposed at a position where the chip5can be accommodated, and may be disposed, for example, in the vicinity of the center of the front surface4ain XY plan view (seeFIG.3).

The depth of the recessed portion4a1is smaller than a Z-direction depth of the chips3-4and3-8with respect to the front surface4a. The Z position of the hack surface4bis on the −Z side relative to the Z position of the front surfaces (−Z-side surfaces) of the chips3-4and3-8.

The recessed portion4a1has a bottom surface4a11and a side surface4a12. The bottom surface4a11extends in the XY direction. The bottom surface4a11is separated from multiple chips3-1to3-8in the Z direction. The bottom surface4a11is separated in the Z direction from the chip3-4on the most −Z side among multiple chips3-1to3-4and is separated in the Z direction from the chip3-8on the most −Z side among multiple chips3-5to3-8. The bottom surface4a11may be substantially parallel to a front surface3aof the chip3-4and may be substantially parallel to a front surface3aof the chip3-8. The recessed portion4a1may be, for example, a substantially rectangular parallelepiped hole, or may have a substantially rectangular shape in XY plan view. The area of the open end of the recessed portion4a1is larger than the area of the bottom surface4a11. An X-direction width of the open end of the recessed portion4a1is larger than an X-direction width of the bottom surface4a11. A Y-direction width of the open end of the recessed portion4a1is larger than a Y-direction width of the bottom surface4a11.

The area of the open end of the recessed portion4a1is larger than the area of the chip5. The X-direction width of the open end of the recessed portion4a1is larger than an X-direction width of the chip5. The Y-direction width of the open end of the recessed portion4a1is larger than a Y-direction width of the chip5.

The area of the bottom surface4a11is larger than the area of the chip5. The X-direction width of the bottom surface4a11is larger than the X-direction width of the chip5. The Y-direction width of the bottom surface4a11is larger than the Y-direction width of the chip5.

Multiple terminals6-1to6-8correspond to multiple chips3-1to3-8. Each of the terminals6-1to6-8extends in the −Z direction from a surface (−Z-side surface)3aof a corresponding chip3opposite to the support2, penetrates the sealing portion4, and reaches the front surface4a. Each of the terminals6-1to6-8may be connected to the corresponding chip3in plural per a chip. Each of the terminals6-1to6-8may linearly extend in the direction. Each of the terminals6-1to6-8is an upright terminal, and may have rigidity capable of maintaining a linear shape.

For example, each of the terminals6-1to6-8may have a diameter larger than that of a wire used for wire bonding type mounting. Each of the terminals6-1to6-8is a vertically extending wire, and is also referred to as a vertical wire. When each of the terminals6-1to6-8is configured as an upright type, the arrangement pitch between the terminals6-1to6-8can be easily a narrow pitch.

In a case where multiple chips3-1to3-8are stacked stepwise half by half, multiple terminals6-1to6-8may have different lengths stepwise half by half. The +Z-side end portions of multiple terminals6-1to6-4have the Z positions that are lowered stepwise on the −Y side of multiple terminals6-5to6-8. The +Z-side end portions of multiple terminals6-5to6-8have the Z positions that are lowered stepwise on the +Y side of multiple terminals6-5to6-8. The −Z-side end portions of multiple terminals6-1to6-8may have substantially equal Z positions. The −Z-side end portion of each of the terminals6-1to6-8is connected to an electrode pattern11of the substrate10via an electrode8and a ball bump9. Each of the terminals6-1to6-8can be formed of a conductive material containing metal (for example, gold) as a main component.

The chip5is disposed on the −Z side of the support2and is disposed on the −Z side of multiple chips3-1to3-8. The chip5has a function different from that of the chips3, and is, for example, a controller chip capable of controlling multiple chips3-1to3-8. The chip5is electrically connected to multiple chips3-1to3-8. The chip5is desirably disposed in the vicinity of the center of the semiconductor device1in XY plan view in order to make the wiring lengths to the chips3-1to3-8uniform. Therefore, the chip5is disposed in the recessed portion4a1.

A back surface (+Z-side surface)5bof the chip5may be slightly separated from the bottom surface4a11of the recessed portion4a1in the −Z direction. Thus, the chip5is separated in the −Z direction from the chips3-4and3-8on the most −Z side among multiple chips3-1to3-8.

Multiple terminals7-1to7-4are disposed on a front surface (−Z-side surface)5aof the chip5. Each of the terminals7-1to7-4may extend in a columnar shape in the −Z direction. The maximum width of each of the terminals7-1to7-4in the XY direction is larger than the maximum width of each of the terminals6-1to6-8in the XY direction. Each of the terminals7-1to7-4can be formed of a stack of a plurality of layers. Each of multiple layers can be formed of a conductive material containing an alloy as a main component, such as a solder alloy layer or a copper alloy layer. Multiple layers may include layers having different compositions, or layers having different compositions and layers having the same composition may be mixed.

The +Z-side end portions of multiple terminals7-1to7-4are coupled to the front surface5aof the chip5. The −Z-side end portions of multiple terminals7-1to7-4may have substantially equal Z positions. The Z-direction height of the −Z-side end portions of multiple terminals7-1to7-4from the support2may be substantially equal to the Z-direction height of the −Z-side end portions of multiple terminals6-1to6-8from the support2. The −Z-side end portion of each of the terminals7-1to7-4is connected to an electrode pattern11of the substrate10via an electrode8and a ball bump9. Each of the terminals7-1to7-4is a columnar bump and is also called a pillar bump. When each of the terminals7-1to7-4is configured in a columnar shape, the arrangement pitch between the terminals7-1to7-4can be easily a narrow pitch.

The sealing portion22fills the recessed portion4a1and seals the chip5. The sealing portion22fills a gap between the sealing portion4and the substrate10, and seals the electrodes8, the ball bumps9, and the electrode patterns11. The sealing portion22covers a −Z-side surface of the sealing portion4and covers a front surface10aof the substrate10. The sealing portion22can be formed of a second insulator having thermoplasticity such as mold resin. The second insulator is different in composition from the first insulator.

The sealing portion21covers and seals the support2, the sealing portion4, and the sealing portion22from the outside. The sealing portion21may reach the front surface10aof the substrate10. The sealing portion21can be formed of a third insulator having thermoplasticity such as mold resin. The third insulator is different in composition from the first insulator and is different in composition from the second insulator.

The sealing portion4, the sealing portion21, and the sealing portion22may contain an inorganic filler in an insulating resin. At this time, the content of the filler in the sealing portion4and the sealing portion21may be larger than the content of the filler in the sealing portion22.

The thermal expansion coefficients of the sealing portion4and the sealing portion21may be smaller than the thermal expansion coefficient of the sealing portion22.

The Young's moduli of the sealing portion4and the sealing portion21may be larger than the Young's modulus of the sealing portion22.

The substrate10includes multiple electrode patterns11, a plurality of through-hole electrodes12, a conductive layer13, a plurality of through-hole electrodes14, a prepreg layer15, and a core layer16. Each of multiple electrode patterns11is exposed on the front surface10aof the substrate10, and each of multiple through-hole electrodes14is exposed on a back surface10bof the substrate10. Each of the electrode patterns11, each of the through-hole electrodes12, the conductive layer13, and each of the through-hole electrodes14can be formed of a material containing a conductive material (for example, copper) as a main component. Each of the prepreg layer15and the core layer16can be formed of a material containing an insulator (for example, an organic substance such as plastic) as a main component.

Note that, inFIG.1, for the sake of simplicity, the conductive layer13is illustrated in a form of being connected to multiple electrode patterns11, multiple through-hole electrodes12, and multiple through-hole electrodes14, but in practice, predetermined wiring formed, and a predetermined electrode pattern11, a predetermined through-hole electrode12, and a predetermined through-hole electrode14may be selectively connected.

Multiple external electrodes23are disposed on the back surface10bof the substrate10, and are each joined to the through-hole electrodes14. The arrangement pitch of multiple external electrodes23in the X direction is larger than the arrangement pitch of multiple terminals6-1to6-8in the X direction. The arrangement pitch of multiple external electrodes23in the X direction is larger than the arrangement pitch of multiple terminals7-1to7-4in the X direction. Similarly, the arrangement pitch of multiple external electrodes23in the Y direction is larger than the arrangement pitch of multiple terminals6-1to6-8in the Y direction. The arrangement pitch of multiple external electrodes23in the Y direction is larger than the arrangement pitch of multiple terminals7-1to7-4in the Y direction. Thus, the semiconductor device1can be easily connected to wide-pitch external terminals (for example, terminals on a motherboard) while narrowing the arrangement pitch between the terminals6-1to6-8and the arrangement pitch between the terminals7-1to7-4.

Next, a method of manufacturing the semiconductor device1will be described with reference toFIGS.1to5C.FIG.1is a cross-sectional view illustrating a configuration of the semiconductor device1, but is used as a cross-sectional view illustrating a method of manufacturing the semiconductor device1.FIGS.2A to2D,4A to4C, and5A to5Care cross-sectional views illustrating a method of manufacturing the semiconductor device1.FIG.3is a plan view illustrating a method of manufacturing the semiconductor device1.

In the process illustrated inFIG.2A, the support2is prepared. The support2is a plate-shaped member extending in the XY direction. The support2can be formed of a material suitable for having predetermined rigidity (for example, glass, glass cloth, and silicon). Multiple chips3-1to3-8are stacked stepwise on a −Z-side surface2aof the support2.

For example, the chip3-1can be bonded to a −Y side region of the −Z-side surface2aof the support2via an adhesive, an adhesive film, or the like. The chip3-2can be bonded to the −Z side of the chip3-1in a state where the XY plane position is shifted to, for example, the +Y side. The chip3-3can be bonded to the −Z side of the chip3-2via an adhesive or an adhesive film in a state where the XY plane position is shifted to, for example, the +Y side. The chip3-4can be bonded to the −Z side of the chip3-3in a state where the XY plane position is shifted to, for example, the +Y side.

Thus, multiple chips3-1to3-4are stacked stepwise in the −Y side region of the surface2aof the support2while the Y position is sequentially shifted to the +Y side. Each of the chips3-1to3-4is face-up mounted with the front surfaces3aon the −Z side. The front surfaces3aof multiple chips3-1to3-4are sequentially increased in Z-direction height from the support2. Similarly, multiple chips3-5to3-8are stacked stepwise in the +Y side region of the surface2aof the support2while the Y position is sequentially shifted to the −Y side. Each of the chips3-5to3-8is face-up mounted with the front surfaces3aon the −Z side. The front surfaces3aof multiple chips3-5to3-8are sequentially increased in Z-direction height from the support2.

In the process illustrated inFIG.2B, multiple terminals6-1to6-8are coupled to multiple chips3-1to3-8. Multiple terminals6-1to6-8correspond to multiple chips3-1to3-8. The lengths of multiple terminals6-1to6-8can be different from each other corresponding to the Z-direction heights of multiple chips3-1to3-8from the support2(for example, to accommodate the difference in Z-direction height). Each of the terminals6-1to6-8can be coupled to an electrode pad on the front surface3aof the corresponding chip3at its +Z-side end portion in an upright position in the Z direction. Note that a plurality of terminals6may extend from each chip3(seeFIG.3).

For example, the lengths of multiple terminals6-1to6-4are sequentially shortened in accordance with a sequential increase in Z-direction height of the front surfaces3aof multiple chips3-1to3-4from the support2. Thus, in a state where multiple terminals6-1to6-4is coupled to multiple chips3-1to3-4, the Z positions of the −Z-side end portions thereof are close to each other. Similarly, the lengths of multiple terminals6-5to6-8are sequentially shortened in accordance with a sequential increase in Z-direction height of the front surfaces3aof multiple chips3-5to3-8from the support2. Thus, in a state where multiple terminals6-5to6-8is coupled to multiple chips3-5to3-8, the Z positions of the −Z-side end portions thereof are close to each other.

In the process illustrated inFIG.2C, a sealing portion4iis formed on the −Z side of the support2. That is, the front surfaces and side surfaces of multiple chips3-1to3-8are covered with the first insulator and the side surfaces and end surfaces of multiple terminals6-1to6-8are covered with the first insulator to form the sealing portion4i. The sealing portion4ican be formed of the first insulator having thermoplasticity such as mold resin. The Z-direction height of the sealing portion4ifrom the support2is higher than the Z-direction height of the chips3-4and3-8on the most −Z side and higher than the Z-direction height of each of the terminals6-1to6-8.

In the process illustrated inFIG.2D, a recessed portion4a1iis formed on a −Z-side surface4aiof the sealing portion4i. The recessed portion4a1iis formed to have a depth with respect to the sum of a predetermined depth and a polishing thickness in a later process. The predetermined depth is formed to be smaller than the Z-direction depth of the chips3-4and3-8with respect to the surface4a1. The predetermined depth may be equal to or more than the Z-direction height of the chip5from the substrate10in a state where the chip5is mounted on the substrate10in a later process. The recessed portion4a1imay be formed in a tapered shape in which the side surface4a12is inclined such that the opening width becomes smaller toward the bottom surface4a11in each of XZ cross-sectional view and YZ cross-sectional view. For example, the recessed portion4a1imay be formed by molding. By preparing a mold including a flat portion having a pedestal portion in the vicinity of the center in the XY direction, heating and melting the first insulator, pouring the first insulator into the mold, cooling the first insulator, and removing the mold, it is possible to form the sealing portion4ihaving the recessed portion4a1iin the vicinity of the center of the front surface in the XY direction. At this time, it is possible to easily remove the mold by forming the pedestal portion into a tapered shape, and it is possible to improve the throughput of the processing of forming the sealing portion4i. Alternatively, the recessed portion4a1imay be formed by laser processing. After the sealing portion4ihaving a flat surface is formed, the sealing portion4ihaving the recessed portion4a1iin the vicinity of the center of the surface can be formed by irradiating the surface with laser light while controlling the irradiation position in a rectangular shape by NC control or the like. At this time, the recessed portion4a1ican be formed in a tapered shape due to the characteristics of laser processing.

As illustrated inFIG.3, the recessed portion4a1iis formed in the vicinity of the center of the surface4aiin XY plan view.FIG.3exemplifies a configuration in which the recessed portion4a1iis formed as a substantially rectangular parallelepiped hole (having a substantially rectangular shape in XY plan view). The recessed portion4a1iis formed such that the X-direction width thereof is larger than the X-direction width of the chip5. The recessed portion4a1iis formed such that the Y-direction width thereof is larger than the Y-direction width of the chip5. With such a configuration of the recessed portion4a1i, the chip5can be accommodated in the recessed portion4a1iin a later process.

In the process illustrated inFIG.4A, the surface4aiof the sealing portion4iis polished. For example, a grinder of a polishing apparatus is pressed against the surface4aiof the sealing portion4i, and the grinder rotates about an axis perpendicular to the contact surface, and the rotation of the grinder is continued until the −Z-side end portion of each of the terminals6-1to6-8is exposed to the front surface4aof the sealing portion4. The Z-direction thickness of the sealing portion4is thinner than that of the sealing portion4iby an amount corresponding to the polishing thickness. The depth of the recessed portion4a1is smaller than that of the recessed portion4a1iby an amount corresponding to the polishing thickness.

In the process illustrated inFIG.4B, multiple electrodes8are formed on the front surface4aof the sealing portion4. Multiple electrodes8correspond to multiple terminals6-1to6-8. Each of the electrodes8is electrically connected to the −Z-side end portion of the corresponding terminal6. Each of the electrodes8is formed of a conductive material such as metal (for example, copper). Thus, an upper structure20in which multiple chips3-1to3-8are face-up mounted and sealed while being stacked stepwise is obtained.

In the process illustrated inFIG.4C, the substrate10is prepared. The ball bump9is coupled to each of multiple electrode patterns11exposed on the front surface10aof the substrate10. The electrode8is coupled to each of multiple ball bumps9in the vicinity of the center of the substrate10in XY plan view.

On the other hand, the chip5is prepared. Multiple electrode pads are disposed on the front surface5aof the chip5. Multiple terminals7-1to7-4corresponding to multiple electrode pads are prepared. One end of each of multiple terminals7-1to7-4is coupled to a corresponding electrode pad on the front surface5aof the chip5. Multiple terminals7-1to7-4also correspond to multiple electrodes8in the vicinity of the center of the substrate10in XY plan view. The other end of each of multiple terminals7-1to7-4is coupled to the electrode8. That is, the chip5is face-down mounted on the substrate10with the front surface5aon the −Z side. Thus, a lower structure30in which the chip5is face-down mounted on the substrate10is obtained.

The upper structure20and the lower structure30are arranged to face each other such that the front surface4aand the front surface10aface each other. When viewed from the Z direction, the relative positions of the upper structure20and the lower structure30are aligned such that the electrodes8of the upper structure20and the ball bumps9of the lower structure30overlap each other. At this time, the chip5is included inside the recessed portion4a1when viewed from the Z direction (seeFIG.3).

In the process illustrated inFIG.5A, the upper structure20and the lower structure30are relatively brought close to each other in the Z direction. The electrodes8of the upper structure20and the ball bumps9of the lower structure30are coupled to each other. The chip5is accommodated in the recessed portion4a1of the sealing portion4.

In the process illustrated inFIG.5B, the gap between the upper structure20and the lower structure30is sealed by the sealing portion22. The sealing portion22is loaded to fill the recessed portion4a1and fill the gap between the sealing portion4and the substrate10. The sealing portion22can be formed of a second insulator having thermoplasticity such as mold resin. Thus, the chip5is sealed by the sealing portion22, and the electrodes8and the ball bumps9are sealed by the sealing portion22.

In the process illustrated inFIG.5C, the outside of the upper structure20is sealed by the sealing portion21. The sealing portion21is formed to cover the support2, the sealing portion4, and the sealing portion22from the outside. The sealing portion21may be formed so as to reach the front surface10aof the substrate10. The sealing portion21can be formed of a third insulator having thermoplasticity such as mold resin. The third insulator is different in composition from the first insulator and is different in composition from the second insulator.

In the process illustrated inFIG.1, multiple external electrodes23are mounted on the back surface10bof the substrate10. The external electrodes23can be joined to the through-hole electrodes14exposed on the back surface10bof the substrate10. Then, the semiconductor device1is obtained through singulation by cutting.

As described above, in the first embodiment, in the semiconductor device1, the recessed portion4a1is provided in the vicinity of the center of the front surface4aof the sealing portion4in XY plan view that seals multiple stacked chips3-1to3-8. The chip5is accommodated in the recessed portion4a1. Thus, since it is easy to wire the chip5to multiple chips3-1to3-8at substantially equal distances, it is possible to provide the semiconductor device1having a structure suitable for appropriately arranging each of multiple chips3-1to3-8and the chip5.

Here, a case where multiple chips3-1to3-8are stacked stepwise on the support2and the chip5is bonded onto the uppermost (the most −Z-side) chips3-4and3-8at the time of manufacturing the semiconductor device1is considered. In this case, there is a possibility that the chips3-4and3-8are bent due to stress at the time of bonding or the like and the chip5is inclined from an appropriate planar direction.

On the other hand, in the first embodiment, in the semiconductor device1, the bottom surface4a11of the recessed portion4a1in which the chip5is accommodated is separated in the Z direction from the front surfaces3aof the uppermost (the most −Z-side) chips3-4and3-8among multiple chips3-1to3-8sealed by the sealing portion4. Thus, it is possible to provide the semiconductor device1having a structure suitable for manufacturing by mounting the chip5without inclination from an appropriate planar direction.

Here, a case where both the upright terminals6-1to6-8connected to the chips3-1to3-8and the terminals7-1to7-4having a columnar shape mounted on the chip5are sealed by the sealing portion4at the time of manufacturing the semiconductor device1will be considered. In this case, the height of the end varies between the terminals6-1to6-8and the terminals7-1to7-4. In order to accommodate this variation, the terminals6-1to6-8and the terminals7-1to7-4are formed to be high, and the heights are made uniform by polishing. That is, since the terminals7-1to7-4having a complicated structure (structure of a stack of a plurality of films) as compared with the terminals6-1to6-8are made high, there is a possibility that the cost of the semiconductor device1increases.

On the other hand, in the first embodiment, in the semiconductor device1, the upright terminals6-1to6-8are sealed together with the chips3-1to3-8to which the terminals6-1to6-8are connected by the sealing portion4, and the −Z-side end portions are exposed to the front surface4aof the sealing portion4. The terminals7-1to7-4having a columnar shape are mounted on the chip5accommodated in the recessed portion4a1of the sealing portion4. Thus, it is possible to suppress the influence of the variation between the terminals6-1to6-8and the terminals7-1to7-4with respect to the sealing by the sealing portion4, and it is possible to suppress the terminals7-1to7-4to be low. That is, it is possible to provide the semiconductor device1suitable for reducing the manufacturing cost.

Note that, as illustrated inFIG.6C, a buffer member40may be interposed between the chip5and the bottom surface4a11of the recessed portion4a1.FIGS.6A to6Care respectively cross-sectional views illustrating a method of manufacturing the semiconductor device according to a first modification of the first embodiment.

For example, in the method of manufacturing the semiconductor device1, after the processes illustrated inFIGS.2A to2Dare performed, the process illustrated inFIG.6Amay be performed. In the process illustrated inFIG.6A, the buffer member40is disposed on the bottom surface4a11of the recessed portion4a1. The buffer member40is a plate-shaped member extending in the XY direction. The buffer member40may be formed of an insulating material having flexibility and elasticity such as a resin-based adhesive. The buffer member40is disposed so as to cover the main part of the bottom surface4a11.

As indicated by the two-dot chain lines inFIG.3, the buffer member40is disposed so as to be included inside the bottom surface4a11and to include the chip5inside in XY plan view. The XY area of the buffer member40is smaller than the XY area of the bottom surface4a11and larger than the XY area of the chip5. The X-direction width of the buffer member40is smaller than the X-direction width of the bottom surface4a11and larger than the X-direction width of the chip5. The Y-direction width of the buffer member40is smaller than the Y-direction width of the bottom surface4a11and larger than the Y-direction width of the chip5.

After the processes illustrated inFIGS.4A to4Care performed, the process illustrated inFIG.6Bis performed instead of the process illustrated inFIG.5A. In the process illustrated inFIG.6B, the upper structure20and the lower structure30are relatively brought close to each other in the Z direction. As in the first embodiment, the electrodes8of the upper structure20and the ball bumps9of the lower structure30are coupled to each other. The chip5is accommodated in the recessed portion4a1of the sealing portion4while the back surface of the chip5is in contact with the buffer member40. At this time, the chip5is pressed against the buffer member40to some extent, but since the buffer member40has elasticity, stress on the chip5is suppressed.

The process illustrated inFIG.6Cis performed instead of the process illustrated inFIG.5B. In the process illustrated inFIG.6C, when the gap between the upper structure20and the lower structure30is sealed by the sealing portion22, the recessed portion4a1is filled while the exposed surfaces of the buffer member40and the chip5are covered. At this time, since the main part of the bottom surface4a11of the recessed portion4a1is covered with the buffer member40, generation of voids in the sealing portion22is suppressed, and the mounting quality can be improved.

Thereafter, as in the first embodiment, the process illustrated inFIG.5Cand the process illustrated inFIG.1are performed to manufacture the semiconductor device1.

As described above, in the semiconductor device according to the first modification of the first embodiment, the buffer member40is interposed between the chip5and the bottom surface4a11of the recessed portion4a1. Thus, it is possible to provide the semiconductor device1having a structure suitable for improving the mounting quality.

In addition, the recessed portion4a1imay have any shape as long as the chip5can be accommodated and may, for example, be formed as a groove having a lateral I-shape as illustrated inFIG.7(having a substantially lateral I-shape in XY plan view).FIG.7is a plan view illustrating a method of manufacturing the semiconductor device1according to a second modification of the first embodiment.FIG.7exemplifies a configuration in which the recessed portion4a1iis formed as a lateral I-shaped groove. In this case, unlike the first embodiment, the Y-direction width of the open end of the recessed portion4a1is substantially equal to the Y-direction width of the bottom surface4a11. Note that, as in the first embodiment, the area of the open end of the recessed portion4a1iis larger than the area of the bottom surface4a11, and the X-direction width of the open end of the recessed portion4a1iis larger than the X-direction width of the bottom surface4a11.

The terminals6-1to6-8are exposed on the bottom surface of the recessed portion4a1i. The height of the exposed surfaces of the terminals is low. Therefore, electrodes may be formed separately so as to compensate for the height of the terminals. Alternatively, the electrodes8and the ball bumps9may be formed high.

The recessed portion4a1imay be formed in a tapered shape in which the side surface4a12is inclined such that the opening width becomes smaller toward the bottom surface4a11in XZ cross-sectional view. For example, the recessed portion4a1imay be formed by dicing processing. After the sealing portion4ihaving a flat surface is formed, the sealing portion4ihaving the recessed portion4a1ihaving a groove shape in the vicinity of the center of the surface in the X direction can be formed by bringing a dicing blade into contact with the surface in the X direction and rotating the dicing blade while controlling the contact position by NC control or the like. At this time, the recessed portion4a1ican be formed in a tapered shape in XZ cross-sectional view due to the characteristics of dicing processing. Alternatively, the recessed portion4a1imay be formed by molding. By preparing a mold including a flat portion having a pedestal portion having a lateral I-shape in the vicinity of the center in the X direction, heating and melting the first insulator, pouring the first insulator into the mold, cooling the first insulator, and removing the mold, it is possible to form the sealing portion4ihaving the recessed portion4a1iin the vicinity of the center of the front surface in the X direction. At this time, it is possible to easily remove the mold by forming the pedestal portion into a tapered shape, and it is possible to improve the throughput of the processing of forming the sealing portion4i. Alternatively, the recessed portion4a1imay be formed by laser processing. After the sealing portion4ihaving a flat surface is formed, the sealing portion4ihaving the recessed portion4a1iin the vicinity of the center of the surface in the X direction can be formed by irradiating the surface with laser light while controlling the irradiation position in a lateral stripe shape by NC control or the like. At this time, the recessed portion4a1ican be formed in a tapered shape due to the characteristics of laser processing.

In addition, the recessed portion4a1imay be formed as a groove having a vertical I-shape as illustrated inFIG.8(having a substantially vertical I-shape in XY plan view).FIG.8is a plan view illustrating a method of manufacturing the semiconductor device1according to a third modification of the first embodiment.FIG.8exemplifies a configuration in which the recessed portion4a1iis formed as a vertical I-shaped groove. In this case, unlike the first embodiment, the X-direction width of the open end of the recessed portion4a1is substantially equal to the X-direction width of the bottom surface4a11. Note that, as in the first embodiment, the area of the open end of the recessed portion4a1iis larger than the area of the bottom surface4a11, and the Y-direction width of the open end of the recessed portion4a1iis larger than the Y-direction width of the bottom surface4a11.

The recessed portion4a1imay be formed in a tapered shape in which the side surface4a12is inclined such that the opening width becomes smaller toward the bottom surface4a11in YZ cross-sectional view. For example, the recessed portion4a1imay be formed by dicing processing. After the sealing portion4ihaving a flat surface is formed, the sealing portion4ihaving the recessed portion4a1ihaving a groove shape in the vicinity of the center of the surface in the Y direction can be formed by bringing a dicing blade into contact with the surface in the Y direction and rotating the dicing blade while controlling the contact position by NC control or the like. At this time, the recessed portion4a1ican be formed in a tapered shape in YZ cross-sectional view due to the characteristics of dicing processing. Alternatively, the recessed portion4a1imay be formed by molding. By preparing a mold including a flat portion having a pedestal portion having a vertical I-shape in the vicinity of the center in the Y direction, heating and melting the first insulator, pouring the first insulator into the mold, cooling the first insulator, and removing the mold, it is possible to form the sealing portion4ihaving the recessed portion4a1iin the vicinity of the center of the front surface in the Y direction. At this time, it is possible to easily remove the mold by forming the pedestal portion into a tapered shape, and it is possible to improve the throughput of the processing of forming the sealing portion4i. Alternatively, the recessed portion4a1imay be formed by laser processing. After the sealing portion4ihaving a flat surface is formed, the sealing portion4ihaving the recessed portion4a1iin the vicinity of the center of the surface in the Y direction can be formed by irradiating the surface with laser light while controlling the irradiation position in a vertical stripe shape by NC control or the like. At this time, the recessed portion4a1ican be formed in a tapered shape due to the characteristics of laser processing.

In addition, the recessed portion4a1imay be formed as a groove having a cross shape as illustrated inFIG.9(having a substantially cross shape in XY plan view).FIG.9is a plan view illustrating a method of manufacturing the semiconductor device1according to a fourth modification of the first embodiment.FIG.9exemplifies a configuration in which the recessed portion4a1iis formed as a cross-shaped groove. In this case, unlike the first embodiment, the X-direction width of the open end of the recessed portion4a1is substantially equal to the X-direction width of the bottom surface4a11in the vicinity of the center in the Y direction and is larger than the X-direction width of the bottom surface4a11in the vicinity of both ends in the Y direction, and the Y-direction width of the open end of the recessed portion4a1is substantially equal to the Y-direction width of the bottom surface4a11in the vicinity of the center in the X direction and is larger than the Y-direction width of the bottom surface4a11in the vicinity of both ends in the X direction. Note that, as in the first embodiment, the area of the open end of the recessed portion4a1iis larger than the area of the bottom surface4a11.

The terminals6-1to6-8are exposed on the bottom surface of the recessed portion4a1i. The height of the exposed surfaces of the terminals is low. Therefore, electrodes may be formed separately so as to compensate for the height of the terminals. Alternatively, the electrodes8and the ball bumps9may be formed high.

The portion in the vicinity of both ends of the recessed portion4a1iin the X direction may be formed in a tapered shape in which the side surface4a12is inclined such that the opening width becomes smaller toward the bottom surface4a11in YZ cross-sectional view. The portion in the vicinity of both ends of the recessed portion4a1iin the Y direction may be formed in a tapered shape in which the side surface4a12is inclined such that the opening width becomes smaller toward the bottom surface4a11in XZ cross-sectional view. For example, the recessed portion4a1imay be formed by dicing processing. After the sealing portion4ihaving a flat surface is formed, the sealing portion4ihaving the recessed portion4a1ihaving a cross groove shape on the surface can be formed by bringing a dicing blade into contact with the surface in the X direction and rotating the dicing blade and bringing the dicing blade into contact with the surface in the Y direction and rotating the dicing blade while controlling the contact position by NC control or the like. At this time, due to the characteristics of dicing processing, the portion in the vicinity of both ends of the recessed portion4a1iin the X direction can be formed in a tapered shape in YZ cross-sectional view, and the portion in the vicinity of both ends in the Y direction can be formed in a tapered shape in XZ cross-sectional view. Alternatively, the recessed portion4a11may be formed by molding. By preparing a mold including a flat portion having a pedestal portion having a cross shape, heating and melting the first insulator, pouring the first insulator into the mold, cooling the first insulator, and removing the mold, it is possible to form the sealing portion4ihaving the recessed portion4a1ihaving a cross shape on the surface. At this time, it is possible to easily remove the mold by forming the pedestal portion into a tapered shape, and it is possible to improve the throughput of the processing of forming the sealing portion4i. Alternatively, the recessed portion4a1imay be formed by laser processing. After the sealing portion4ihaving a flat surface is formed, the sealing portion4ihaving the recessed portion4a1ihaving a cross shape on the surface can be formed by irradiating the surface with laser light while controlling the irradiation position in a cross shape by NC control or the like. At this time, due to the characteristics of laser processing, the portion in the vicinity of both ends of the recessed portion4a1iin the X direction can be formed in a tapered shape in YZ cross-sectional view, and the portion in the vicinity of both ends in the Y direction can be formed in a tapered shape in XZ cross-sectional view.

Second Embodiment

Next, a semiconductor device according to the second embodiment will be described. Hereinafter, portions different from those of the first embodiment will be mainly described.

In the first embodiment, the semiconductor device1having a structure in which the back surface of the chip5is separated from the bottom surface4a11of the recessed portion4a1is exemplified, but in the second embodiment, a semiconductor device101having a structure in which the back surface of a chip5is in contact with a bottom surface4a11of a recessed portion4a1is exemplified.

Specifically, in the semiconductor device101, as illustrated inFIG.10, a back surface5bof the chip5comes into contact with the bottom surface4a11of the recessed portion4a1.FIG.10is a cross-sectional view illustrating a configuration of the semiconductor device101according to the second embodiment. As compared with the first embodiment, since a Z-direction distance between the chip5and uppermost chips3-4and3-8among a plurality of chips3-1to3-8is smaller, the height of the semiconductor device101can be reduced.

Note that a sealing portion4is interposed between the chip5and the chips3-4and3-8. Thus, as in the first embodiment, the chip5can be mounted in the vicinity of the center of the sealing portion4in XY plan view along the XY direction.

The semiconductor device101includes a plurality of terminals107-1to107-4and a sealing portion122, instead of multiple terminals7-1to7-4and the sealing portion22(seeFIG.1), and further includes a sealing portion123. The −Z-side end portions of multiple terminals107-1to107-4have the Z positions that are substantially the same as the −Z-side end portions of a plurality of terminals6-1to6-8. The sealing portion123fills the recessed portion4a1and seals the chip5. A −Z-side surface123aof the sealing portion123and a −Z-side surface4aof the sealing portion4form a continuous surface and have substantially the same Z position. The sealing portion123can be formed of a fourth insulator having thermoplasticity such as mold resin. The fourth insulator is different in composition from the first insulator. The fourth insulator may be different in composition from the second insulator and may be different in composition from the third insulator.

The sealing portion122and the sealing portion123may contain an inorganic filler in an insulating resin. At this time, the content of the filler in the sealing portion4, the sealing portion21, and the sealing portion122may be larger than the content of the filler in the sealing portion123. The content of the filler in the sealing portion4and the sealing portion21may be larger than the content of the filler in the sealing portion122.

The thermal expansion coefficients of the sealing portion4, the sealing portion21, and the sealing portion122may be smaller than the thermal expansion coefficient of the sealing portion123. The thermal expansion coefficients of the sealing portion4and the sealing portion21may be smaller than the thermal expansion coefficient of the sealing portion122.

The Young's moduli of the sealing portion4, the sealing portion21, and the sealing portion122may be larger than the Young's modulus of the sealing portion123. The Young's moduli of the sealing portion4and the sealing portion21may be larger than the Young's modulus of the sealing portion122.

Note that, as in the first embodiment, the −Z-side end portion of each of the terminals6-1to6-8is connected to an electrode pattern11of a substrate10via an electrode8and a ball bump9, and the −Z-side end portion of each of the terminals7-1to7-4is connected to an electrode pattern11of the substrate10via an electrode8and a ball bump9.

In addition, as illustrated inFIGS.11A to13C, a method of manufacturing the semiconductor device101is different from that of the first embodiment on the point described below.FIGS.11A to11B,12A to12C, and13A to13Care cross-sectional views illustrating a method of manufacturing the semiconductor device101.

For example, in the method of manufacturing the semiconductor device101, after the processes illustrated inFIGS.2A to2Dare performed, the process illustrated inFIG.11Amay be performed. In the process illustrated inFIG.11A, the chip5and multiple terminals107-1to107-4are prepared. One end of each of multiple terminals107-1to107-4is coupled to a corresponding electrode pad on the front surface of the chip5. The chip5to which multiple terminals107-1to107-4are coupled is disposed on the bottom surface4a11of the recessed portion4a1. As indicated by the one-dot chain lines inFIG.3, the chip5is disposed so as to be included inside the bottom surface4a11in XY plan view. The back surface5bof the chip5may be bonded to the bottom surface4a11via an adhesive, an adhesive film, or the like.

At this time, in a state where the chip5is disposed in the recessed portion4a1, the −Z-side end portion of each of the terminals6-1to6-8and the −Z-side end portion of each of the terminals107-1to107-8may be different from each other within a range in which the positions can be made uniform by polishing.

In the process illustrated inFIG.11B, the fourth insulating material is loaded into a recessed portion4ai. That is, the front surface and side surfaces of the chip5are covered with the fourth insulator and the side surfaces and end surfaces of multiple terminals107-1to107-8are covered with the fourth insulator to form a sealing portion123i. Thus, a sealing portion123ithat fills the recessed portion4aiis formed. The fourth insulating material is different in composition from the first insulator. The fourth insulator may be different in composition from the second insulator and may be different in composition from the third insulator.

At this time, a surface4aiof the sealing portion4and a surface123aiof the sealing portion123may be different from each other within a range in which the Z positions can be made uniform by polishing.

In the process illustrated inFIG.12A, the surface4aiof the sealing portion4iand the surface123aiof the sealing portion123iare polished. For example, a grinder of a polishing apparatus is pressed against the surface4aiof the sealing portion4iand the surface123aiof the sealing portion123i, and the grinder rotates about an axis perpendicular to the contact surface, and the rotation of the grinder is continued until the −Z-side end portion of each of the terminals6-1to6-8is exposed to the front surface4aof the sealing portion4and the −Z-side end portion of each of the terminals107-1to107-8is exposed to the surface123of the sealing portion123. The depth of the recessed portion4a1is smaller than that of the recessed portion4a1i(seeFIG.2D) by an amount corresponding to the polishing thickness. The Z-direction thickness of the sealing portion4is thinner than that of the sealing portion4iby an amount corresponding to the polishing thickness. The depth of the recessed portion4a1is smaller than that of the recessed portion4a1iby an amount corresponding to the polishing thickness. The Z-direction thickness of the sealing portion123is thinner than that of the sealing portion123iby an amount corresponding to the polishing thickness.

At this time, the −Z-side end portion of each of the terminals6-1to6-8and the −Z-side end portion of each of the terminals107-1to107-8have substantial the same Z position.

In the process illustrated inFIG.12B, a plurality of electrodes8is formed on the front surface4aof the sealing portion4, and a plurality of electrodes8is formed on the front surface123aof the sealing portion123. Multiple electrodes8formed on the front surface4aof the sealing portion4are the same as that in the first embodiment. Multiple electrodes8formed on the front surface123aof the sealing portion123correspond to multiple terminals107-1to107-4. Each of the electrodes8formed on the front surface123ais electrically connected to the −Z-side end portion of the corresponding terminal107. Thus, an upper structure120in which multiple chips3-1to3-8are face-up mounted and sealed while being stacked stepwise and the chip5is sealed in a state of being able to be face-down mounted is obtained.

In the process illustrated inFIG.12C, the substrate10is prepared. The ball bump9is coupled to each of multiple electrode patterns11exposed on the front surface10aof the substrate10. Thus, a lower structure130in which the chip5is configured in a state of being able to be face-down mounted is obtained.

The upper structure120and the lower structure130are arranged to face each other such that the front surfaces4aand123aand the front surface10aface each other. When viewed from the Z direction, the relative positions of the upper structure120and the lower structure130are aligned such that the electrodes8of the upper structure120and the ball bumps9of the lower structure130overlap each other.

In the process illustrated inFIG.13A, the upper structure120and the lower structure130are relatively brought close to each other in the Z direction. The electrodes8of the upper structure120and the ball bumps9of the lower structure130are coupled to each other.

In the process illustrated inFIG.13B, the gap between the upper structure120and the lower structure130is sealed by the sealing portion122. The sealing portion122is loaded to fill the gap between the sealing portions4and123and the substrate10. The sealing portion122can be formed of the second insulator having thermoplasticity such as mold resin. Thus, the electrodes8and the ball bumps9are sealed by the sealing portion122.

In the process illustrated inFIG.13C, the outside of the upper structure120is sealed by the sealing portion21. The sealing portion21is formed to cover a support2, the sealing portion4, and the sealing portion122from the outside. The sealing portion21may be formed so as to reach the front surface10aof the substrate10. The sealing portion21can be formed of a third insulator having thermoplasticity such as mold resin. The third insulator is different in composition from the first insulator and different in composition from the second insulator.

In the process illustrated inFIG.10, multiple external electrodes23are mounted on the back surface10bof the substrate10. The external electrodes23can be joined to the through-hole electrodes14exposed on the back surface10bof the substrate10. Then, the semiconductor device101is obtained through singulation by cutting.

As described above, in the second embodiment, in the semiconductor device101, the recessed portion4a1is provided in the vicinity of the center of the front surface4aof the sealing portion4in XY plan view that seals multiple stacked chips3-1to3-8. The chip5is accommodated in the recessed portion4a1. Thus, since it is easy to wire the chip5to multiple chips3-1to3-8at substantially equal distances, it is possible to provide the semiconductor device101having a structure suitable for appropriately arranging each of multiple chips3-1to3-8and the chip5.

Third Embodiment

Next, a semiconductor device according to the third embodiment will be described. Hereinafter, portions different from those of the first embodiment and the second embodiment will be mainly described.

In the second embodiment, the semiconductor device101having a structure in which the terminals6-1to6-8and107-1to107-4are connected to the external electrodes23via the substrate10is exemplified, but in the third embodiment, a semiconductor device201having a structure in which terminals6-1to6-8and107-1to107-4are connected to external electrodes23via a rewiring layer240is exemplified.

Specifically, in the semiconductor device201, as illustrated inFIG.14, the electrodes8, the ball bumps9, and the sealing portion21(seeFIG.10) are omitted, and the rewiring layer240is disposed instead of the substrate10.FIG.14is a cross-sectional view illustrating a configuration of the semiconductor device201according to the third embodiment. As compared with the second embodiment, the Z-direction distance between the terminals6-1to6-8and107-1to107-4and the external electrodes23is further reduced, and the Z height is reduced by the thickness of the sealing portion21, so that the height of the semiconductor device201can be further reduced.

Note that a sealing portion4is interposed between the chip5and the chips3-4and3-8. Thus, as in the first embodiment and the second embodiment, the chip5can be mounted in the vicinity of the center of the sealing portion4in XY plan view along the XY direction.

In the semiconductor device201, the rewiring layer240includes a plurality of layers of wiring for connecting the terminals6-1to6-8and107-1to107-4and the external electrodes23. The rewiring layer240includes, for example, three wiring layers, and includes a wiring layer241, a plug layer242, a wiring layer243, a plug layer244, a wiring layer245, and an interlayer insulating film246.

The −Z-side end portions of multiple terminals6-1to6-8are each connected to electrode patterns of the wiring layer241. The −Z-side end portions of multiple terminals107-1to107-4are each connected to electrode patterns of the wiring layer241.

Multiple external electrodes23are each connected to electrode patterns of the wiring layer245.

The electrode patterns of the wiring layer241and the electrode patterns of the wiring layer245can be connected via plugs of the plug layer242, line patterns of the wiring layer243, plugs of the plug layer244, or the like. Thus, the terminals6-1to6-8and107-1to107-4are connected to the external electrodes23via the rewiring layer240.

In addition, as illustrated inFIG.14, a method of manufacturing the semiconductor device201is different from that of the second embodiment on the point described below.FIG.14is a cross-sectional view illustrating a configuration of the semiconductor device201, but is used as a cross-sectional view illustrating a method of manufacturing the semiconductor device201.

For example, in the method for manufacturing the semiconductor device201, the process illustrated inFIG.14may be performed after the processes illustrated in the drawings up toFIG.12Aare performed as in the second embodiment. In the process illustrated inFIG.14, a conductive layer241iis deposited on a front surface4aof the sealing body4and a front surface123aof a sealing portion123by a vapor deposition method, a plating method, or the like. A resist pattern RP1that selectively covers the −Z-side end portions of multiple terminals6-1to6-8and the −Z-side end portions of multiple terminals107-1to107-4are formed thereon. The conductive layer241iis etched using the resist pattern RP1as a mask. Thus, the wiring layer241including electrode patterns that selectively cover the −Z-side end portions of multiple terminals6-1to6-8and the −Z-side end portions of multiple terminals107-1to107-4are formed.

Next, an insulating film246icovering the wiring layer241is deposited. A resist pattern RP2having openings at the positions of the electrode patterns of the wiring layer241is formed thereon. The insulating film246iis etched using the resist pattern RP2as a mask. Holes for selectively exposing the electrode patterns of the wiring layer241are formed. A conductive material such as tungsten is embedded in the holes. Thus, the plugs of the plug layer242connected to the electrode patterns of the wiring layer241are formed.

Similarly, the wiring layer243, the plug layer244, and the wiring layer245are formed.

Then, multiple external electrodes23are mounted on the −Z-side surface of the rewiring layer240. The external electrodes23are coupled to the electrode patterns of the wiring layer245. Then, the semiconductor device201is obtained through singulation by cutting.

As described above, in the third embodiment, in the semiconductor device201, a recessed portion4a1is provided in the vicinity of the center of the front surface4aof the sealing portion4in XY plan view that seals multiple stacked chips3-1to3-3. The chip5is accommodated in the recessed portion4a1. Thus, since it is easy to wire the chip5to multiple chips3-1to3-8at substantially equal distances, it is possible to provide the semiconductor device201having a structure suitable for appropriately arranging each of multiple chips3-1to3-8and the chip5.

Other Embodiments

(a) In the first embodiment and the second embodiment, the sealing portion4may be provided instead of the sealing portion22and the sealing portion122. For example, inFIG.5B, the sealing portion22is not provided, and sealing is directly performed by the sealing portion4. Similarly in the second embodiment, the process of providing the sealing portion122inFIG.13Bcan be deleted. Thus, the manufacturing cost can be reduced. At this time, the sealing portion21is provided between the sealing portion4and the substrate10.

(b) In the first embodiment, the terminals of the chip5are connected to the terminals provided on the substrate10by flip chip bonding with the chip5being in a face-down state. At this time, the circuit surface of the chip5is formed to face the substrate10side. Alternatively, the terminals of the chip5may be connected to the terminals provided on the substrate10by wire bonding. At this time, the circuit surface of the chip5is formed on a surface opposite to the substrate10. Connection by wire bonding enables formation at low cost.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.