Patent ID: 12198932

DETAILED DESCRIPTION

The technical solutions in the embodiments of the present disclosure are described below clearly and completely with reference to the drawings in the embodiments of the present disclosure. Apparently, the described embodiments are merely part rather than all of the embodiments of the present disclosure. All other embodiments obtained by a person skilled in the art based on the embodiments of the present application without creative efforts should fall within the protection scope of the present application. It should be noted that without conflict, the embodiments in the present application and features in the embodiments may be combined with each other.

In a capacitor process, multiple pattern structures arranged at intervals are formed, with a gap between two adjacent pattern structures. As shown inFIG.1, the pattern structures are formed on a dielectric layer900. Each pattern structure includes a mandrel layer901and sidewalls905located on both sides of the mandrel layer901. A gap is provided between two adjacent patterned structures, and the gap exposes the dielectric layer900.

An etching process is performed on the pattern structure. Because the dielectric layer under the gap is exposed without protection, in the etching process, the dielectric layer under the gap is more affected by etching than the mandrel layer. The dielectric layer under the gap will also be partially etched. Therefore, the dielectric layer exposed after the pattern structure is etched has a height difference with the dielectric layer under the gap, thus forming a recess.FIG.2is a schematic diagram of the recess between the dielectric layer under the pattern structure and the dielectric layer under the gap after the etching process. As shown inFIG.2, there is a drop h between the dielectric layer900exposed after the mandrel layer in the pattern structure is etched and the dielectric layer900under the gap. The drop h causes a recess in the gap, which will lead to a height difference between adjacent patterns. As a result, the pattern structures are not effectively transferred to a target layer during the subsequent pattern transfer, resulting in ineffective bridging or non-open defects of the pattern formed on a target structure.FIG.3is a schematic diagram of a defect caused by an etch loading effect. As shown inFIG.3, the etch loading effect may cause the bottom surface of the semiconductor structure to have a narrow open or even non-open defect. For example, the left side is a normal open size W1, and the right side is a narrow open size W2, where W2is significantly narrower than W1.

A method of manufacturing a semiconductor structure and a semiconductor structure manufactured by the method are disclosed, which can eliminate the pattern transfer defects (such as bridging or non-open defects) caused by the height difference between adjacent patterns due to the etch loading effect between the pattern structure and the gap, thereby improving the stability of the subsequent process and the performance of the product.

FIG.4is a schematic flowchart of an embodiment of a method of manufacturing a semiconductor structure according to the present disclosure. As shown inFIG.4, the method of manufacturing a semiconductor structure includes the following steps:

Step S101: Provide a substrate, and form a first sacrificial layer on the substrate, the first sacrificial layer including a first sacrificial dielectric layer and a second sacrificial dielectric layer that are stacked.

Step S103: Pattern the first sacrificial layer, and form first intermediate pattern structures that are arranged at intervals, a first gap being provided between two adjacent first intermediate pattern structures.

Step S105: Form a first spacer pad layer in the first gap, the first spacer pad layer covering sidewalls of each of the two adjacent first intermediate pattern structures and the bottom of the first gap.

Step S107: Remove the first spacer pad layer at the bottom of the first gap, and the second sacrificial dielectric layer.

Step S109: Remove the first sacrificial dielectric layer, to form first pattern structures.

The method of manufacturing a semiconductor structure is described in detail below with reference to the accompanying drawings.

Step S101is performed to provide a substrate, and form a first sacrificial layer on the substrate, the first sacrificial layer including a first sacrificial dielectric layer and a second sacrificial dielectric layer that are stacked.

In an embodiment of the present disclosure, the semiconductor structure is manufactured using a double patterning process, which may be, for example, a self-aligned double patterning (SADP) process.

In the SADP process, for example, the substrate has a stack of known patterned layers with self-aligned double patterning. The substrate may include monocrystalline silicon, an oxide layer, a polysilicon layer, silicon germanide, silicon on insulator, etc., and the substrate may also include a stack combination structure of multiple materials, such as a combination of silicon nitride, silicon oxide, silicon carbon nitride, and silicon oxynitride, etc.

In an embodiment of the present disclosure, in step S101, a substrate is provided, and a first sacrificial layer is formed on the substrate, the first sacrificial layer including a first sacrificial dielectric layer and a second sacrificial dielectric layer that are stacked, thus obtaining the structure shown inFIG.5.

In the structure shown inFIG.5, as a schematic illustration, only a base layer101of the substrate is shown. The base layer101may be a single-layer structure or a multilayer structure, and may be formed by a spin-on hardmask (SOH) layer. The SOH layer may be formed through a spin coating process. The SOH layer may be an insulating layer of a carbon-hydrogen (CxHy) system, which may include a silicon hard mask material, a carbon hard mask material, and an organic hard mask material, etc.

In some examples, a support layer103may be formed on the base layer101. A material of the support layer103may include, but is not limited to, silicon oxynitride (SiON), a nitrogen-doped silicon carbide layer, or a silicon carbide layer, etc. The support layer103may be formed by a chemical vapor deposition (CVD) or spin-on dielectrics (SOD) process.

In step S101, a first sacrificial layer is formed on the substrate, where the first sacrificial layer includes a first sacrificial dielectric layer and a second sacrificial dielectric layer that are stacked. As shown inFIG.5, a first sacrificial dielectric layer105and a second sacrificial dielectric layer107are formed on the support layer103in order. The first sacrificial dielectric layer105may be formed by a spin-on hardmask (SOH) layer. The SOH layer may be formed through a spin coating process. The SOH layer may be an insulating layer of a carbon-hydrogen (CxHy) system, which may include a silicon hard mask material, a carbon hard mask material, or an organic hard mask material, etc., such as a silicon oxynitride layer. A material of the second sacrificial dielectric layer107may include, but is not limited to, silicon oxynitride (SiON), polysilicon (Poly), an amorphous carbon layer (ACL), and oxide, etc. In this embodiment, the material of the second sacrificial dielectric layer107is the same as that of the support layer103. The second sacrificial dielectric layer107may be formed by a chemical vapor deposition (CVD) or spin-on dielectrics (SOD) process.

The structure shown inFIG.5is obtained through the foregoing step S101.

Step S103is performed, to pattern the first sacrificial layer and form the first intermediate pattern structures that are arranged at intervals along a first direction, the first gap being provided between two adjacent first intermediate pattern structures.

In an embodiment of the present disclosure, in step S103, a mask layer109is first formed on the second sacrificial dielectric layer107to obtain the structure shown inFIG.6.

The mask layer109is formed on the second sacrificial dielectric layer107; the mask layer109is formed on the surface of the second sacrificial dielectric layer107by a chemical vapor deposition process. A material of the mask layer109may include, but is not limited to, silicon oxynitride (SiON), polysilicon (Poly), an amorphous carbon layer (ACL), or oxide, etc.

The mask layer109is patterned to form mask patterns110. The mask patterns110include multiple line openings spaced apart, which are arranged along the first direction, and the line openings expose part of the second sacrificial dielectric layer107, thus obtaining the structure shown inFIG.7.

A patterned photoresist layer is formed on the surface of the mask layer109. Photoresist is spin-coated on the mask layer109and is patterned with a mask plate to form the patterned photoresist layer. The mask layer109is etched by using the patterned photoresist layer to form multiple mask patterns110on the second sacrificial dielectric layer107, a line opening along the first direction being provided between two adjacent mask patterns110. The line openings expose part of the second sacrificial dielectric layer107. The process for forming the mask patterns110is not limited thereto. In other examples, the mask patterns110can also be formed on the surface of the second sacrificial dielectric layer107by the SADP process.

The process is continued. The second sacrificial dielectric layer107and the first sacrificial dielectric layer105are etched along the mask patterns110to form the first intermediate pattern structures, a first gap112being provided between two adjacent first intermediate pattern structures, thus obtaining the structure shown inFIG.8. As shown inFIG.8, the etched second sacrificial dielectric layer107and first sacrificial dielectric layer105form the first intermediate pattern structures.

Step S105is performed to form the first spacer pad layer in the first gap, the first spacer pad layer covering sidewalls of each of the two adjacent first intermediate pattern structures and the bottom of the first gap.

In an embodiment of the present disclosure, in step S105, a first pad layer111is formed, and the first pad layer111covers each first intermediate pattern structure and each first gap, to obtain the structure shown inFIG.9.

The first pad layer111may be formed by an oxide layer, and the first pad layer111may be formed through a spin coating process. The first pad layer111covers sidewalls of each first intermediate pattern structure and the bottom of each first gap112. The first pad layer111completely covers the first intermediate pattern structures and the first gaps112, and has a thickness ranging from 50 nm to 150 nm, such as 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, or any value from 50 nm to 150 nm. The thickness of the first pad layer111is not limited thereto, but can vary depending on the size of the first intermediate pattern structure or the first gap, as long as it can completely cover the first intermediate pattern structures and the first gaps112. The first pad layer111can also be formed, for example, by photoresist or amorphous silicon.

The first pad layer111covering the top of the first intermediate pattern structure is removed to expose the second sacrificial dielectric layer107, and the first pad layer111on the sidewalls of the first intermediate pattern structure and at the bottom of the first gap112is retained to form the first spacer pad layer111A.

The step of removing the first pad layer covering the top of the first intermediate pattern structure to expose the second sacrificial dielectric layer, and retaining the first pad layer on the sidewalls of the first intermediate pattern structure and at the bottom of the first gap to form the first spacer pad layer further includes:

forming a first filling layer113covering the first pad layer111to obtain the structure shown inFIG.10.

The first filling layer113may be formed by a spin-on hardmask (SOH) layer. The SOH layer may be formed through a spin coating process. The SOH layer may be an insulating layer of a carbon-hydrogen (CxHy) system, which may include a silicon hard mask material, a carbon hard mask material, and an organic hard mask material, etc. In an embodiment, a material of the first filling layer113may be the same as that of the first sacrificial dielectric layer105. The first filling layer113may be, for example, a silicon oxynitride layer.

The first filling layer113completely covers the first pad layer111. The first filling layer113may also be formed, for example, by photoresist or amorphous silicon.

The first filling layer113above the second sacrificial dielectric layer107, and the first pad layer111above the second sacrificial dielectric layer107are removed, by using the second sacrificial dielectric layer107as a stop layer, to obtain the structure shown inFIG.11.

The first filling layer113between parts of the first pad layer111is removed to form the first spacer pad layer111A, thus obtaining the structure shown inFIG.12.

Step S107is performed to remove the first spacer pad layer at the bottom of the first gap, and the second sacrificial dielectric layer.

In an embodiment of the present disclosure, in step S107, the first spacer pad layer111A at the bottom of the first gap112, and the second sacrificial dielectric layer107are removed, to obtain the structure shown inFIG.13. The first spacer pad layer111A at the bottom of the first gap112, and the second sacrificial dielectric layer107can be removed simultaneously.

Step S109is performed to remove the first sacrificial dielectric layer, thus forming the first pattern structures.

In an embodiment of the present disclosure, in step S109, the first sacrificial dielectric layer105is removed to form the first pattern structures111B, thus obtaining the structure shown inFIG.14.

In an embodiment, the first spacer pad layer has a first line width and the first gap has a second line width, where the second line width is at least three times the first line width, i.e., the second line width is three times or more than the first line width.

In an embodiment, the line width of the first spacer pad layer may be equal to the first line width. In an embodiment of the present disclosure, the line width of the first spacer pad layer can be made smaller due to the presence of the second sacrificial dielectric layer, such that the target pattern can be made larger in the same area.

As shown inFIG.14, the support layer under the first pattern structure111B formed after step S109has substantially the same thickness as the support layer under the first gap, with no or negligible difference, which effectively overcomes the etch loading effect. The semiconductor structure can be effectively patterned to ensure the performance of the semiconductor structure.

FIG.15is a schematic flowchart of an embodiment of a method of manufacturing a semiconductor structure according to the present disclosure.

In an embodiment of the present disclosure, after obtaining the first pattern structures111B are obtained, step S111is performed to form a transition layer covering the first pattern structures.

In an embodiment of the present disclosure, in step S111, a transition layer114is formed on the first pattern structures111B, and the transition layer114completely covers the first pattern structures111B, thus obtaining the structure shown inFIG.16.

The transition layer114may be formed by a chemical vapor deposition (CVD) or spin-on dielectrics (SOD) process. A material of the transition layer114may include, but is not limited to, silicon oxynitride (SiON), a nitrogen-doped silicon carbide layer, or a silicon carbide layer, etc.

In an embodiment of the present disclosure, as shown inFIG.16, the transition layer114includes a first transition dielectric layer114A and a second transition dielectric layer114B stacked in order, where the first transition dielectric layer114A completely covers the first pattern structures111B. The second transition dielectric layer114B is formed on the first transition dielectric layer114A. A material of the first transition dielectric layer114A may be SOH; a material of the second transition dielectric layer114B may be silicon oxynitride. The materials of the first transition dielectric layer114A and the second transition dielectric layer114B are not limited thereto, and can be selected according to the etching conditions.

Step S113is performed to form a second sacrificial layer on the transition layer, the second sacrificial layer including a third sacrificial dielectric layer and a fourth sacrificial dielectric layer that are stacked.

In an embodiment of the present disclosure, in step S111, a third sacrificial dielectric layer115and a fourth sacrificial dielectric layer116are formed on the transition layer114in order. The third sacrificial dielectric layer115and the fourth sacrificial dielectric layer116form the second sacrificial layer, thus obtaining the structure shown inFIG.17.

The third sacrificial dielectric layer115may be formed by a spin-on hardmask (SOH) layer. The SOH layer may be formed through a spin coating process. The SOH layer may be an insulating layer of a carbon-hydrogen (CxHy) system, which can include a silicon hard mask material, a carbon hard mask material, and an organic hard mask material, etc., such as a silicon oxynitride layer. A material of the fourth sacrificial dielectric layer116may include, but is not limited to, silicon oxynitride (SiON), polysilicon (Poly), an amorphous carbon layer (ACL), oxide, etc. In this embodiment, the material of the third sacrificial dielectric layer115is the same as that of the first transition dielectric layer114A, and the material of the fourth sacrificial dielectric layer116is the same as that of the second transition dielectric layer114B. The fourth sacrificial dielectric layer116may be formed by a chemical vapor deposition (CVD) or spin-on dielectrics (SOD) process.

Step S115is performed to pattern the second sacrificial layer, and form second intermediate pattern structures that are arranged at intervals along a second direction, a second gap being provided between two adjacent second intermediate pattern structures. The second direction is different from the first direction; the first direction and the second direction may intersect vertically or at an angle.

In an embodiment of the present disclosure, in step S115, the second sacrificial layer is patterned to form the second intermediate pattern structures that are arranged at intervals along the second direction, a second gap117being provided between two adjacent second intermediate pattern structures, thus obtaining the structure shown inFIG.18.

With respect to step S115, in an embodiment of the present disclosure, in step S115, a mask layer is first formed on the fourth sacrificial dielectric layer116. A mask layer is formed on the surface of the fourth sacrificial dielectric layer116by using a chemical vapor deposition process. A material of the mask layer may include, but is not limited to, silicon oxynitride (SiON), polysilicon (Poly), an amorphous carbon layer (ACL), oxide, etc.

The mask layer is patterned to form mask patterns. The mask patterns include multiple line openings spaced apart, which are arranged along the second direction, and the line openings expose part of the fourth sacrificial dielectric layer116.

A patterned photoresist layer is formed on the surface of the mask layer. Photoresist is spin-coated on the mask layer and is patterned with a mask plate to form the patterned photoresist layer. The mask layer is etched by using the patterned photoresist layer to form multiple mask patterns on the fourth sacrificial dielectric layer116, a line opening along the second direction being provided between two adjacent mask patterns. The line openings expose part of the fourth sacrificial dielectric layer116. The second direction intersects the first direction. The second direction and the first direction may intersect vertically or at an angle. In other embodiments, mask patterns can be formed on the surface of the fourth sacrificial dielectric layer116by the SADP process.

The fourth sacrificial dielectric layer116and the third sacrificial dielectric layer115are etched along the mask patterns, to form the second intermediate pattern structures, a second gap117being provided between two adjacent second intermediate pattern structures, thus obtaining the structure shown inFIG.18. As shown inFIG.18, the etched fourth sacrificial dielectric layer116and third sacrificial dielectric layer115form the second intermediate pattern structures.

Step S117is performed to form a second spacer pad layer in the second gap, the second spacer pad layer covering sidewalls of each of the two adjacent second intermediate pattern structures and the bottom of the second gap.

In an embodiment of the present disclosure, in step S117, a second pad layer118is formed, and the second pad layer118covers each second intermediate pattern structure and each second gap117, as shown inFIG.19.

The second pad layer118may be formed by an oxide layer, and the second pad layer118may be formed through a spin coating process. The second pad layer118completely covers the second intermediate pattern structures and the second gaps117, and has a thickness ranging from 50 nm to 150 nm, such as 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, or any value from 50 nm to 150 nm. The thickness of the second pad layer118is not limited thereto, but can vary depending on the size of the second intermediate pattern structure or the second gap117, as long as it can completely cover the second intermediate pattern structures and the second gaps117. The second pad layer118can also be formed, for example, by photoresist or amorphous silicon.

The second pad layer118covering the top of each second intermediate pattern structure is removed to expose the fourth sacrificial dielectric layer116, and the second pad layer118on the sidewalls of the second intermediate pattern structure and at the bottom of the second gap117is retained, to form the second spacer pad layer118A (as shown inFIG.21).

The step of removing the second pad layer covering the top of each second intermediate pattern structure to expose the fourth sacrificial dielectric layer, and retaining the second pad layer on the sidewalls of the second intermediate pattern structure and at the bottom of the second gap to form the second spacer pad layer further includes:

forming a second filling layer119covering the second pad layer118, to obtain the structure shown inFIG.20.

The second filling layer119may be formed by a spin-on hardmask (SOH) layer. The SOH layer may be formed through a spin coating process. The SOH layer may be an insulating layer of a carbon-hydrogen (CxHy) system, which may include a silicon hard mask material, a carbon hard mask material, and an organic hard mask material, etc. In an embodiment, a material of the second filling layer119may be the same as that of the third sacrificial dielectric layer115. The second filling layer119may be a silicon oxynitride layer.

The second filling layer119completely covers the second pad layer118. The second filling layer119may also be formed, for example, by photoresist or amorphous silicon.

The second filling layer119above the fourth sacrificial dielectric layer116, and the second pad layer118above the fourth sacrificial dielectric layer116are removed, by using the fourth sacrificial dielectric layer116as the stop layer, to obtain the structure shown inFIG.21.

The second filling layer119between the second pad layer118is removed to form the second spacer pad layer118A, thus obtaining the structure shown inFIG.22.

Step S119is performed to remove the second spacer pad layer at the bottom of the second gap, and the fourth sacrificial dielectric layer.

In an embodiment of the present disclosure, in step S119, the second spacer pad layer118A at the bottom of the second gap117, and the fourth sacrificial dielectric layer116are removed to obtain the structure shown inFIG.23. The second spacer pad layer118A at the bottom of the second gap117, and the fourth sacrificial dielectric layer116can be removed simultaneously to obtain the structure shown inFIG.23.

Step S121is performed to remove the third sacrificial dielectric layer to form second pattern structures.

In an embodiment of the present disclosure, in step S121, the third sacrificial dielectric layer115is removed to form the second pattern structures118B, thus obtaining the structure shown inFIG.24.

In an embodiment, the second spacer pad layer has a third line width and the second gap has a fourth line width, where the fourth line width is at least three times the third line width, i.e., the fourth line width is three times or more than the third line width.

In an embodiment of the present disclosure, the second line width is equal to the fourth line width, and the first line width is equal to the third line width.

In an embodiment of the present disclosure, the line width of the second spacer pad layer may be equal to the third line width.

In an embodiment of the present disclosure, the line width of the second spacer pad layer can be made smaller due to the presence of the fourth sacrificial dielectric layer116, and the target pattern can be made larger in the same area.

In an embodiment of the present disclosure, a target layer121is further formed on the substrate. The target layer121is formed on top of the substrate and under the support layer103. After the first pattern structures111B and the second pattern structures118B are formed, the first pattern structures111B and the second pattern structures118B are transferred to the target layer121as a combined pattern, to obtain the target pattern.

In an embodiment of the present disclosure, the target pattern may be a pattern of capacitive holes arranged at intervals, as shown inFIG.25.

The present disclosure further provides a semiconductor structure, which can be made by using the foregoing method of manufacturing a semiconductor structure.

Each embodiment or implementation in the specification of the present disclosure is described in a progressive manner. Each embodiment focuses on the difference from other embodiments, and the same and similar parts between the embodiments may refer to each other.

In the description of the specification, the description with reference to terms such as “an embodiment”, “an illustrative embodiment”, “some implementations”, “an illustrative implementation” and “an example” means that the specific feature, structure, material or feature described in combination with the implementation(s) or example(s) is included in at least one implementation or example of the present disclosure.

In this specification, the schematic expression of the above terms does not necessarily refer to the same implementation or example. Moreover, the described specific feature, structure, material or characteristic may be combined in an appropriate manner in any one or more implementations or examples.

It should be noted that in the description of the present disclosure, the terms such as “center”, “top”, “bottom”, “left”, “right”, “vertical”, “horizontal”, “inner” and “outer” indicate the orientation or position relationships based on the drawings. These terms are merely intended to facilitate description of the present disclosure and simplify the description, rather than to indicate or imply that the mentioned device or element must have a specific orientation and must be constructed and operated in a specific orientation. Therefore, these terms should not be construed as a limitation to the present disclosure.

It can be understood that the terms such as “first” and “second” used in the present disclosure can be used to describe various structures, but these structures are not limited by these terms. Instead, these terms are merely intended to distinguish one element from another.

The same elements in one or more drawings are denoted by similar reference numerals. For the sake of clarity, various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of brevity, the structure obtained by implementing multiple steps may be shown in one figure. In order to make the understanding of the present disclosure more clearly, many specific details of the present disclosure, such as the structure, material, size, processing process and technology of the device, are described below. However, as those skilled in the art can understand, the present disclosure may not be implemented according to these specific details.

Finally, it should be noted that the above embodiments are merely used to explain the technical solutions of the present disclosure, but are not intended to limit the present disclosure. Although the present disclosure is described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions on some or all technical features therein. These modifications or substitutions do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

INDUSTRIAL APPLICABILITY

The embodiments of the present disclosure provide a method of manufacturing a semiconductor structure and a semiconductor structure, which can eliminate the pattern transfer defect caused by a height difference between adjacent patterns due to an etch loading effect between the pattern structure and the gap.