Patent ID: 12191242

DESCRIPTION OF THE EMBODIMENTS

With reference toFIG.1andFIG.2, a chip package50acting as a memory driving device includes a chip52and a package substrate54. The chip52is installed to the package substrate54. By installing or assembling the chip package50to a motherboard60of a computer (or a similar device), a plurality of memory modules70on the motherboard60may be driven. The memory modules70may be compatible with a plurality of different specifications, including a DDR4 UDIMM mode, a DDR4 RDIMM mode, a DDR5 mode, or an LPDDR5 mode, which should however not be construed as a limitation in the disclosure. A printed circuit board (PCB) of the motherboard60and a PCB of the package substrate54may be considered as a wiring board, respectively. In this embodiment, an electronic assembly A may include the chip package50and the motherboard60, and may also include the memory modules70. On the other hand, the chip package50may be considered as an electronic assembly constituted by the chip52and the package substrate54.

In an embodiment of the disclosure, a contact arrangement100is provided as shown inFIG.3. The contact arrangement100may be applied as a pad arrangement at the chip package50or a pad arrangement at the motherboard60inFIG.1, and the contact arrangement100may also be applied as a conductive medium arrangement between the chip package50and the motherboard60. The arrangement of the conductive medium M is, for instance, an arrangement of conductive pads, an arrangement of conductive balls, an arrangement of conductive pins, an arrangement of conductive elastic terminals, and so forth, which should however not be construed as a limitation in the disclosure. In addition, the contact arrangement at the package substrate54of the chip package50and the contact arrangement at the motherboard60have a mirror image relationship, so as to achieve electrical connection. With reference toFIG.3andFIG.4, in this embodiment, the contact arrangement100may be constituted by exposed portions of wiring layers L of the wiring board (e.g., the wiring layers L of the motherboard60inFIG.1or the wiring layers L of the package substrate54inFIG.2). In addition to the contact arrangement100depicted inFIG.3, inFIG.4, plural traces T formed by the wiring layers L are further represented by dashed lines.

As shown inFIG.4, the contact arrangement100is composed of a plurality of contacts C and includes a plurality of contact groups110. At least one of the contact groups110includes a plurality of shared contacts112, a plurality of dedicated contacts114, and a plurality of ground contacts116. The shared contacts112in a first mode or a second mode may transmit signals corresponding to the first mode or the second mode. The first mode is, for instance, one of a DDR4 UDIMM mode, a DDR4 RDIMM mode, a DDR5 mode, and an LPDDR5 mode of the memory modules70, and the second mode is, for instance, another of the DDR4 UDIMM mode, the DDR4 RDIMM mode, the DDR5 mode, and the LPDDR5 mode of the memory modules70. That is, the first mode and the second mode are two different modes of the memory modules70. The dedicated contacts114(non-shared contacts) may transmit the signals corresponding to the first mode and do not transmit the signals corresponding to the second mode. It means the dedicated contacts114are dummy signal contacts in the second mode. Alternatively, the dedicated contacts114(the non-shared contacts) may transmit the signals corresponding to the second mode and do not transmit the signals corresponding to the first mode. It means the dedicated contacts114are dummy signal contacts in the first mode. The ground contacts116surround the shared contacts112and the dedicated contacts114.

The contact arrangement100provided in one or more embodiments of the disclosure may support the DDR4 UDIMM mode (specification), the DDR4 RDIMM mode, the DDR5 mode, or the LPDDR5 mode of the memory modules70at the same time, and the signals corresponding to these modes (specifications) may be divided into three types, including clock (CLK/Clock) signals, data (Data/Strobe) signals, and control (Control/CMD) signals, which belong to three contact groups110marked in a box depicted inFIG.4. The descriptions of the contact groups110are respectively provided below.

With reference toFIG.5AandFIG.5B, in the same contact group110, the shared contacts112are configured to transmit data signals (Data/Strobe) corresponding to the DDR4 UDIMM mode, the DDR4 RDIMM mode, the DDR5 mode, or the LPDDR5 mode. Two of the shared contacts112constitute a shared contact differential pair112a(e.g., as shown by pin positions A1and A2inFIG.5A), which is configured to transmit data signals corresponding to the DDR4 UDIMM mode, the DDR4 RDIMM mode, the DDR5 mode, or the LPDDR5 mode. In addition, two of the dedicated contacts114constitute a dedicated contact differential pair114a. The dedicated contact differential pair114amerely transmits data signals corresponding to the DDR4 RDIMM mode or the LPDDR5 mode. When the memory module is in the DDR4 UDIMM mode or the DDR5 mode, the dedicated contact differential pair114ais in a normally closed (NC) state (e.g., as shown by pin positions A3and A4inFIG.5A). It means the dedicated contact differential pair114ais a dummy contact differential pair in the DDR4 UDIMM mode or the DDR5 mode. In addition, two of the shared contacts112(i.e., the shared contacts112g) of the same contact group110are in a ground state to serve as the reference loop of the signals. In this embodiment, the ground contacts116are substantially located on the peripheries of one contact group110and surround the shared contact differential pair112aand the dedicated contact differential pair114a. The ground contacts116may be connected to each other through the traces T and may be connected to the shared contacts112g(configured to be grounded) through the traces T.

As shown inFIG.5B, in this embodiment, a sum of the shared contacts112and the dedicated contacts114of the same contact group110is at least 12. As shown inFIG.5C, in another embodiment, a sum of the shared contacts112and the dedicated contacts114of the same contact group110is 14. In the embodiment depicted inFIG.5BandFIG.5C, the contact group110includes one shared contact differential pair112aand two dedicated contact differential pairs114aand114b. The two dedicated contact differential pairs114aand114bin the DDR4 RDIMM mode or the LPDDR5 mode transmit the corresponding data signals, while the two dedicated contact differential pairs114aand114bin the DDR4 UDIMM mode or the DDR5 mode are in an NC state. It means the two dedicated contact differential pairs114aand114bare dummy contact differential pairs in the DDR4 UDIMM mode or the DDR5 mode.

With reference toFIG.6, in the same contact group110, the shared contacts112in the DDR4 mode (the DDR4 UDIMM mode or the DDR4 RDIMM mode) or the DDR5 mode (or the LPDDR5 mode) transmit corresponding control signals (Control/CMD). In an embodiment, at least one of the dedicated contacts114of the same contact group110is a dedicated contact114cof the DDR5 mode (or the LPDDR5 mode). In the DDR5 mode (or the LPDDR5 mode), the dedicated contact114cmerely transmits the control signals corresponding to the DDR5 mode (or the LPDDR5 mode). In other words, in the DDR4 mode (the DDR4 UDIMM mode or the DDR4 RDIMM mode), the dedicated contact114cis in an NC state. It means the dedicated contact114cis a dummy contact in the DDR4 mode. In another embodiment, at least one of the dedicated contacts114of the same contact group110is a dedicated contact114dof the DDR4 mode (the DDR4 UDIMM mode or the DDR4 RDIMM mode). In the DDR4 mode (the DDR4 UDIMM mode or the DDR4 RDIMM mode), the dedicated contact114dmerely transmits the control signals corresponding to the DDR4 mode (the DDR4 UDIMM mode or the DDR4 RDIMM mode). In other words, in the DDR5 mode (or the LPDDR5 mode), the dedicated contact114dis in an NC state. It means the dedicated contact114dis a dummy contact in the DDR5 mode. In another embodiment, at least two dedicated contacts114cand114dof the dedicated contacts114respectively in the DDR4 UDIMM mode, the DDR4 RDIMM mode, the DDR5 mode, or the LPDDR5 mode transmit the corresponding control signals. In addition, two of the shared contacts112(i.e., shared contacts112p) are in a power state and may serve as a reference loop of signals. In this embodiment, the ground contacts116are substantially located on the peripheries of one contact group110and surround the shared contacts112, the dedicated contacts114c,114d, and the shared contacts112pconfigured for the power source. The ground contacts116may be connected to each other through the traces T.

With reference toFIG.7AandFIG.7B, in the same contact group110, the shared contacts112in the DDR4 mode (the DDR4 UDIMM mode or the DDR4 RDIMM mode) or the DDR5 mode (or the LPDDR5 mode) transmit corresponding clock signals (CLK/Clock). In the same contact group110, two of the shared contacts112may constitute a shared contact differential pair112b(e.g., as shown by pin positions B1and B2inFIG.7A) and may be configured to transmit the clock signals corresponding to the DDR4 mode (the DDR4 UDIMM mode or the DDR4 RDIMM mode) or the DDR5 mode (or the LPDDR5 mode). Two of the shared contacts112(e.g., the shared contacts112p) may be in a power state, so that the two shared contacts and the ground contacts116may collectively isolate the clock signals. Two of the dedicated contacts114may constitute a dedicated contact differential pair114e(e.g., as shown by pin positions B3and B4inFIG.7A). The dedicated contact differential pair114emerely transmits the clock signals corresponding to the DDR5 mode (or the LPDDR5 mode). When the memory module is in the DDR4 mode (the DDR4 UDIMM mode or the DDR4 RDIMM mode), the dedicated contact differential pair114eis in an NC state. It means the dedicated contact differential pair114eis a dummy contact differential pair in the DDR4 mode. In this embodiment, the ground contacts116are substantially located on the peripheries of one contact group110and surround the shared contact differential pair112cor the dedicated contact differential pair114e, and the ground contacts116may connected to each other through the traces T. In this embodiment, the ground contacts116are substantially located on the peripheries of one contact group110and surround the dedicated contact differential pair114eand the shared power contacts112p. In this embodiment, these ground contacts116are substantially located on the peripheries of one contact group110and surround the shared contact differential pair112cand the shared contacts112pconfigured for the power source.

With reference toFIG.7B, in this embodiment, the contact groups110include a contact group110having a dedicated contact differential pair114eand a contact group110having a shared contact differential pair112b, and the contact group110having the shared contact differential pair112bis farther away from a shape center of the contact groups110than the contact group110having the dedicated contact differential pair114e. In other words, the contact group110having the shared contact differential pair112bis located in a relatively peripheral region. In addition, in another embodiment not shown in the drawings, the contact group110may include a shared contact differential pair112band a dedicated contact differential pair114eat the same time, and the shared contact differential pair112bis farther away from a shape center of the contact groups110than the dedicated contact differential pair114e.

With reference toFIG.1,FIG.2,FIG.8A, andFIG.8B, the wiring board (e.g., the package substrate54or the motherboard60) includes a plurality of wiring layers L and a plurality of conductive vias V. The conductive vias V are connected to at least two of the wiring layers L. Excluding the wiring layer closest to a surface of the wiring board, each of the remaining wiring layers L has only one single trace T between two adjacent conductive vias of the conductive vias V.

To sum up, according to one or more embodiments of the disclosure, under the specification that supports a plurality of different memory modules at the same time, signals corresponding to different modes (specifications) are transmitted through the shared contacts, signals corresponding to a certain mode (specification) are transmitted through one or more of the dedicated contacts, and the ground contacts surround the shared contacts and the dedicated contacts to ensure the quality of signal transmission.

It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided they fall within the scope of the following claims and their equivalents.