Patent ID: 12250026

Like reference numerals are used throughout the Figures to denote similar elements and features. While aspects of the invention will be described in conjunction with the illustrated embodiments, it will be understood that it is not intended to limit the invention to such embodiments.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Although some examples of the present disclosure are described in the context of photonics quantum signal detection and processing, the teachings of the present disclosure may be implemented in other forms of photonics systems including, for example, fibre optics, spectroscopy, LiDAR-based systems, and radiology in medical imaging.

FIG.1is a block diagram illustrating certain components of an example photon detection system100including a PNR detector102in accordance with an embodiment of the present disclosure. The photon detection system100is configured to measure the photon number of an incoming light signal generated by a light source104, which may include suitable optical components (not shown). Although shown as a component of photon detection system100, it is understood that light source104may be located outside and separate of system100as an independent component or a subcomponent of another system. The light source104may, for example, be a pulsed photon source that is capable of generating faint laser pulse, or a resonator capable of generating squeezed light pulses or single-photon generating sources.

Upon absorption of the incident photons generated by the light source104, the PNR detector102is configured to output an electrical pulse. The PNR detector102may be any photon detector that is capable of operating within a linear response region of the detector such as, for example, a transition-edge sensor (TES) based PNR detector, or any other appropriate detector. The detector102may be cooled to a superconducting state (i.e. in the order of tens or hundreds of milli-Kelvin) such that it has zero electrical resistances and hence zero voltage drop. The absorption of one or more photons causes a temperature change in the absorber of the detector102, thereby increasing the resistivity of the detector leading to a voltage drop across the detector. The voltage drop may be proportional to the number of photons absorbed by the PNR detector102.

The electrical signal outputted from the PNR detector102is then detected and recorded by a data acquisition system (DAQ)106. The DAQ106may, for example, include a computing system (as described in more detail below) equipped with appropriate hardware circuit and software. In some embodiments, the DAQ106may include one or more amplifiers (not shown) to amplify the output electrical signals (i.e. voltage drop) of the PNR detector102. In some embodiments, the electrical signal, with or without amplification, may be digitized through an analog-digital-converter (ADC) (not shown) such that the electrical signal readings are quantized into discrete digital quantities.

The recorded data from the DAQ106is then received by the signal processor108, which is a software agent (e.g. a computer program) that comprises instructions that are executed by one or more computing systems. The signal processor108may include any number of independent or interconnected sub-modules. As used here, a “module” can refer to a combination of a hardware processing circuit and machine-readable instructions (software and/or hardware) executable on the hardware processing circuit. A hardware processing circuit can include any or some combination of a microprocessor, a core of a multi-core microprocessor, a microcontroller, a programmable integrated circuit, a programmable gate array, a digital signal processor, or another hardware processing circuit. The signal processor108is configured to carry out the PNR signal processing method in accordance with embodiments of the present disclosure as described in more detail below.

FIG.2illustrates a simplified block diagram of an exemplary embodiment of computing system200, which may be used to implement the signal processor108. Other computing systems suitable for implementing the methods and systems described in the present disclosure may be used, which may include components different from those discussed below. In some example embodiments, the computing system108may be implemented across more than one physical hardware unit, such as in a parallel computing, distributed computing, virtual server, or cloud computing configuration. AlthoughFIG.2shows a single instance of each component, there may be multiple instances of each component in the classical computing system200.

The computing system200may include one or more processing unit(s)202, such as a central processing unit (CPU) with a hardware accelerator, a graphics processing unit (GPU), a tensor processing unit (TPU), a neural processing unit (NPU), a microprocessor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a dedicated logic circuitry, a dedicated artificial intelligence processor unit, or combinations thereof.

The computing system200may also include one or more input/output (I/O) interfaces204, which may enable interfacing with one or more appropriate input devices206and/or output devices208. In the example shown, the input device(s)206(e.g., a keyboard, a mouse, a microphone, a touchscreen, and/or a keypad) and output device(s)208(e.g., a display, a speaker and/or a printer) are shown as optional and external to the computing system200. In other examples, one or more of the input device(s)206and/or the output device(s)208may be included as a component of the computing system200. In other examples, there may not be any input device(s)206and output device(s)208, in which case the I/O interface(s)204may not be needed.

The computing system200may include one or more network interfaces210for wired or wireless communication with a network. In example embodiments, network interfaces210include one or more wireless interfaces such as transmitters212that enable communications in a network. The network interface(s)210may include interfaces for wired links (e.g., Ethernet cable) and/or wireless links (e.g., one or more radio frequency links) for intra-network and/or inter-network communications. The network interface(s)210may provide wireless communication via one or more transmitters212or transmitting antennas, one or more receivers214or receiving antennas, and various signal processing hardware and software. In this regard, some network interface(s)210may include respective processing systems that are similar to computing system200. In this example, a single antenna216is shown, which may serve as both transmitting and receiving antenna. However, in other examples there may be separate antennas for transmitting and receiving.

The computing system200may also include one or more storage devices such as storage units218, which may include a non-transitory storage unit such as a solid state drive, a hard disk drive, a magnetic disk drive and/or an optical disk drive. The storage devices of computing system200may include one or more memories220, which may include a volatile or non-volatile memory (e.g., a flash memory, a random access memory (RAM), and/or a read-only memory (ROM)). The storage devices (e.g., storage units218and/or non-transitory memory(ies)220) may store instructions for execution by the processing units(s)202, such as to carry out the PNR signal processing methods of the present disclosure. The memory(ies)220may include other software instructions, such as for implementing an operating system or a quantum simulation system as disclosed herein and other applications/functions.

In some examples, one or more data sets and/or module(s) may be provided by an external memory (e.g., an external drive in wired or wireless communication with the computing system200) or may be provided by a transitory or non-transitory computer-readable medium. Examples of non-transitory computer readable media include a RAM, a ROM, an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a CD-ROM, or other portable memory storage.

There may be a bus222providing communication among components of the computing system200, including the processing units(s)202, I/O interface(s)204, network interface(s)210, storage unit(s)218, memory(ies)220. The bus222may be any suitable bus architecture including, for example, a memory bus, a peripheral bus or a video bus.

FIG.3is a flowchart diagram illustrating an example method300for processing the PNR signal performed by the signal processor108. At operation302, the system100calibrates the PNR detector102to generate characteristic pulse plots for each unique photon number. The light source104generates a plurality of light pulses directed at the PNR detector102. In example embodiments, the calibration is performed using a sufficiently high number (i.e. in sufficient number to contain pulses of each photon number in the order of 100's) of well separated pulses at a low repetition rate (i.e. in the range of 10 kHz to 100 kHz) so that the unique shape of all relevant photon numbers may be generated as characteristic plots and averaged in sufficient numbers to minimize noise impact. The calibration pulses are used to generate electrical output waveforms from the PNR detector102for each unique photon number. The photon number is identified in all the arriving pulses. The output waveforms for each photon number are then averaged. The average plot for each photon number is stored, such as in storage unit218or memories220, as the characteristic waveform for a given photon number. In some embodiments, the average plot includes a plurality of discrete voltage values. The characteristic plots represent the unique response of the particular PNR detector102photon absorption.

Additionally, a generic tail portion of the characteristic plots are obtained. In some embodiments, the generic tail portion can be generated as the second half of a 2-photon number characteristic plot. It is understood that other methods of setting the tail portion may be suitable, including using the second half of other photon number plots as appropriate. An offset, defined as the difference between an average or mean value of the measured signal and the 0-photon number characteristic plot (i.e. the average or mean voltage value of the 0-phone number plot shown as702inFIG.7), is subtracted from the generic tail portion values for scaling of the tail portion values.

At304, light source104generates light pulses which are received by the PNR detector102, which in turn outputs a corresponding electrical signal plot. The light pulses, including at least a first pulse and a second pulse, form a pulse train where the first pulse partially overlaps with the second pulse. An example pulse train detected by a PNR detector102is shown inFIG.4, which includes 1000 digitized voltage signals outputted from a PNR detector102with an average of 0.3 photons per pulse. The X-axis denotes time in units of the 1/sampling rate, which is 15 MHz in this example. The Y-axis denotes the voltage value in units of milli-volts (mV)/2{circumflex over ( )}15? Generally, the Y-axis is scaled proportional to the PNR signal. As shown inFIG.4, a tail portion of the first pulse402overlaps with a rising edge portion of the second pulse404at406. The overlap between two successive pulses may cause miscounts of the photon number for the later pulse. It is understood that the difference Δt between two consecutive pulses, (i.e. first pulse402and second pulse404), must be such that Δt is equal to or greater than the time required for the PNR detector102to provide sufficient signal to noise ratio for the photon number in the first pulse402to be determined and recover into its linear response region. The Δt is characteristic of the individual PNR detector and the photon pulse.

Referring back toFIG.3, optionally at306, stray tail subtraction may be performed to minimize interference on the first pulse photon number determination that stems from unintended lighting sources, such as environmental or natural light. In cases where interference from unintended light sources is negligible, the stray tail subtraction may not be applied.FIG.5shows a flowchart diagram illustrating an example method500of stray tail subtraction in accordance with the present disclosure.

At502, the standard deviation of the 0-photon number voltage signal is determined as the standard deviation of the signal at408. The determination of the standard deviation σ may be made at any point in time where the photon number is 0 prior to or after the signal pulses, or from a pre-calibrated value. In some exemplary embodiments, the 0-photon number standard deviation may be calculated as:

σ2=1N-1⁢∑i=0N-1⁢(xi-μ)2,
where N is the pulse iteration variable, and μ is the mean value of the 0-photon number voltage. N should be high (in one example, 100k), to avoid statistical noise.

At504, the system identifies whether a signal is a stray event by determining whether the signal value exceeds a threshold value. In some embodiments, the threshold value is four (4) standard deviations of the 0-photon number threshold in the region408for the first pulse402as shown inFIG.4, and region802for the second pulse and best shown inFIG.8.

At506, for each identified stray event, the height of the generic tail portion determined during the calibration phase at302is normalized to the individual voltage signal. In the exemplary embodiment shown inFIG.4, the mean value of the detected voltage value is approximately −100 and begins at time=0, which is 400 units (in this case mV*2{circumflex over ( )}15) above the mean value of the 0-photon number characteristic plot at −500. Accordingly, the generic tail portions values are then vertically scaled up by an offset value of 400 mv/2{circumflex over ( )}15 and subtracted point by point from the detected signal. The process is also referred to as “stray tail subtraction”.FIG.6illustrates the result of stray tail subtraction being applied before the first pulse402shown in FIG.4. As may be noted, the amount of stray signal is reduced near area602just prior to the arrival of the first pulse402. In some embodiments, the height of the stray signal is determined within a time window prior to the arrival of the signal pulse. For example, the time window may be 10% of Δt. In the illustrated example shown inFIG.6, with a sampling frequency of 15 MHz, the windows used to determine signal height for the stray tail subtraction may be approximately 5 nanoseconds (ns) before the arrival of the first pulse402.

Referring back toFIG.3, at308, the signal processor108determines a photon number of the first pulse402. The photon number of the first pulse may be determined via any suitable method including, for example, by the area method where the area under the signal plot is mapped to the area of the characteristic plot, principal component analysis (PCA), and by the dot product method where a dot product of the signal trace and a normalized unique shape is used to estimate the photon number. It is understood that any other suitable method for estimating photon number based on TES detector output may be applied.

At310, the characteristic plot that corresponds to the first photon number is subtracted from the first pulse of the received electrical signal plot. In some embodiments, the characteristic plot is overlayed over the first pulse402as best shown inFIG.7, which shows the characteristic plot of the PNR detector generated during the calibration phase overlayed on top of the plot inFIG.6. InFIG.7, the characteristic plots are shown in darker solid lines. The bottom characteristic plot line702denotes the 0-photon number state, and each of the successive characteristic plot lines denotes states with increasing photon numbers. The values of the overlaid plot may be subtracted, for example point by point, from the first pulse values of the received electrical signal plot. By way of a non-limiting example, if step308determines a first photon number of 2 in the first pulse, then the characteristic plot for 2-photons is subtracted from the received signal plot.FIG.8shows the plot ofFIG.7after the characteristic plot values are subtracted from the first pulse402. Each detected photon number plot line subtracts the values of the closest characteristic plot. The subtraction effectively removes the first pulse402so that its impact, particularly any overlapping with the second pulse404may be minimized.

Optionally, at312, stray tail subtraction may be performed to minimize interference on the second pulse that stems from unintended lighting sources, such as environmental or natural lighting sources. Operation312may be carried out by performing method500similar to operation306.FIG.9illustrates a plot of the second pulse fromFIG.8after stray tail subtraction. As may be discerned through a comparison withFIG.8, the stray signal interference just prior to the arrival of the second pulse404near area902, is minimized.

At314, the digital processor108determines a photon number of the second pulse404. The photon number of the second pulse404may be determined with minimized signal overlap with the first pulse402, thus minimizing the likelihood of miscount. Operation314may be performed via any suitable method including, for example, by matching area under the signal trace, principal component analysis (PCA), or by using a dot product of the signal trace and a normalized unique shape to estimate the photon number. It is understood that any other suitable method for estimating photon number based on TES detector output may be applied. In some embodiments, the method of photon number determination for the first pulse and second pulse are similar and may be implemented by the same software sub-module in digital processor108.

At316, after the photon number of the second pulse404is determined, the first and second photon numbers may be stored in storage units218or memory220. The stored photon numbers may be displayed to the user via output device208, such as a monitor display, or used for other modules or elements of another system.

Although the present disclosure describes the photon number resolving method and system with respect to a two-pulse pulse train, it is understood that the disclosure may be extended to pulse trains with three or more pulses.

Although the present disclosure may describe methods and processes with steps in a certain order, one or more steps of the methods and processes may be omitted or altered as appropriate. One or more steps may take place in an order other than that in which they are described, as appropriate.

Although the present disclosure may be described, at least in part, in terms of methods, a person of ordinary skill in the art will understand that the present disclosure is also directed to the various components for performing at least some of the aspects and features of the described methods, be it by way of hardware components, software or any combination of the two. Accordingly, the technical solution of the present disclosure may be embodied in the form of a software product. A suitable software product may be stored in a pre-recorded storage device or other similar non-volatile or non-transitory computer readable medium, including DVDs, CD-ROMs, USB flash disk, a removable hard disk, or other storage media, for example. The software product includes instructions tangibly stored thereon that enable a processing device (e.g., a personal computer, a server, or a network device) to execute examples of the methods disclosed herein.

The present disclosure may be embodied in other specific forms without departing from the subject matter of the claims. The described example embodiments are to be considered in all respects as being only illustrative and not restrictive. Selected features from one or more of the above-described embodiments may be combined to create alternative embodiments not explicitly described, features suitable for such combinations being understood within the scope of this disclosure.

All values and sub-ranges within disclosed ranges are also disclosed. Also, although the systems, devices and processes disclosed and shown herein may comprise a specific number of elements/components, the systems, devices and assemblies could be modified to include additional or fewer of such elements/components. For example, although any of the elements/components disclosed may be referenced as being singular, the embodiments disclosed herein could be modified to include a plurality of such elements/components. The subject matter described herein intends to cover and embrace all suitable changes in technology.