Patent ID: 12223907

DETAILED DESCRIPTION

The technical solutions in the embodiments of the present disclosure will be described hereinafter clearly and completely with reference to the drawings of the embodiments of the present disclosure. Apparently, the following embodiments merely relate to a part of, rather than all of, the embodiments of the present disclosure, and based on these embodiments, a person of ordinary skill in the art may, without any creative effort, obtain other embodiments, which also fall within the scope of the present disclosure.

In the embodiments of the present disclosure, each transistor may be a triode, a thin film transistor (TFT), a field effect transistor (FET), or any other element having a same characteristic. In order to differentiate two electrodes of the transistor, apart from a control electrode, from each other, one of the two electrodes may be called as a first electrode, and the other may be called as a second electrode.

In actual use, when the transistor is a TFT or FET, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.

As shown inFIG.1, a pixel circuit according to one embodiment of the present disclosure includes a light-emitting element10, a driving circuit11, a first light-emission control circuit12, a first initialization circuit13, an energy storage circuit14, a compensation control circuit15and a data written-in circuit16.

The first light-emission control circuit12is electrically connected to a light-emission control line E1, a first terminal of the driving circuit11and the light-emitting element10, and configured to control the first terminal of the driving circuit11to be electrically connected to the light-emitting element10under control of a light-emission control signal from the light-emission control line E1.

The first initialization circuit13is electrically connected to a reset control line R1, a first initial voltage terminal I1and a control terminal of the driving circuit11, and configured to write a first initial voltage Vint1from the first initial voltage terminal I1into the control terminal of the driving circuit11under control of a reset control signal RS from the reset control line R1.

A first terminal of the energy storage circuit14is electrically connected to the control terminal of the driving circuit11, a second terminal of the energy storage circuit14is electrically connected to a first electrode of the light-emitting element10, and the energy storage circuit14is configured to store electric energy.

The data written-in circuit16is electrically connected to a written-in control line X1, a data line D1and the first terminal of the driving circuit11, and configured to write a data voltage Vdata from the data line D1into the first terminal of the driving circuit11under control of a written-in control signal from the written-in control line X1.

The compensation control circuit15is electrically connected to a compensation control line B1, the control terminal of the driving circuit11and a second terminal of the driving circuit11, and configured to control the control terminal of the driving circuit11to be electrically connected to the second terminal of the driving circuit11under control of a compensation control signal from the compensation control line B1.

In at least one embodiment of the present disclosure, when the pixel circuit operates in a high-frequency driving mode, the compensation control line B1and the written-in control line X1may receive a same control signal, and the compensation control line B1and the written-in control line X1may be a same control line, or, the compensation control line B1and the written-in control line X1may receive different control signals, and the compensation control line B1and the written-in control line X1may be different control lines.

When the pixel circuit operates in a low-frequency driving mode, the compensation control line B1and the written-in control line X1may receive different control signals, and the compensation control line B1and the written-in control line X1may be different control lines.

In at least one embodiment of the present disclosure, that the pixel circuit operates in the high-frequency driving mode refers to that a refresh frequency of the pixel circuit is relatively high. For example, the refresh frequency may be greater than a predetermined frequency, the predetermined frequency may be, but not limited to, greater than or equal to 30 Hz and smaller than or equal to 50 Hz:

That the pixel circuit operates in the low-frequency driving mode refers to that the refresh frequency of the pixel circuit is relatively low. For example, the refresh frequency may be smaller than the predetermined frequency.

The pixel circuit in the embodiments of the present disclosure differs from the related pixel circuit in structure, is capable of performing a threshold voltage compensation and is able to be applied to low-frequency driving.

During the operation of the pixel circuit in the embodiments of the present disclosure, a display frame may include a first initialization stage and a compensation stage arranged one after another.

Within the first initialization stage, the first initialization circuit13writes the first initial voltage Vint1from the first initial voltage terminal I1into the control terminal of the driving circuit11under control of the reset control signal RS;

Within a data written-in time period, the data written-in circuit16writes the data voltage Vdata from the data line D1into the first terminal of the driving circuit11under control of the written-in control signal.

Within the compensation stage, the compensation control circuit15controls the control terminal of the driving circuit11to be electrically connected to the second terminal of the driving circuit11under control of the compensation control signal.

At the beginning of the data written-in time period, the driving circuit11controls the first terminal of the driving circuit11to be electrically connected to the second terminal of the driving circuit11under control of a potential at the control terminal of the driving circuit, and charges the energy storage circuit14via the data voltage to change the potential at the control terminal of the driving circuit11until the first terminal of the driving circuit11is electrically disconnected from the second terminal of the driving circuit11, so as to realize the threshold voltage compensation.

The data written-in time period is the same as the compensation stage, or the data written-in time period is included in the compensation stage.

During the implementation, when the pixel circuit operates in the low-frequency driving mode, the display frame may be a refresh frame included in the display period. When the pixel circuit operates in the high-frequency driving mode, the display frame may be the display period.

As shown inFIG.2, on the basis of the pixel circuit inFIG.1, the pixel circuit may further include a second light-emission control circuit21.

The second light-emission control circuit21is electrically connected to the light-emission control line E1, a first voltage terminal V1and the second terminal of the driving circuit11, and configured to control the first voltage terminal V1to be electrically connected to the second terminal of the driving circuit11under control of the light-emission control signal.

The first light-emission control circuit12is electrically connected to the first electrode of the light-emitting element10, and a second electrode of the light-emitting element10is electrically connected to a second voltage terminal V2.

In a possible embodiment of the present disclosure, the first voltage terminal V1may be, but not limited to, a high voltage terminal VDD, and the second voltage terminal V2may be, but not limited to, a low voltage terminal VSS.

During the operation of the pixel circuit inFIG.2, the display period may further include a first light-emission stage arranged after the compensation stage:

Within the first light-emission stage, the first light-emission control circuit12controls the first terminal of the driving circuit11to be electrically connected to the light-emitting element10under control of the light-emission control signal, the second light-emission control circuit21controls the first voltage terminal V1to be electrically connected to the second terminal of the driving circuit11under control of the light-emission control signal, and the driving circuit11drives the light-emitting element10to emit light.

As shown inFIG.3, on the basis of the pixel circuit inFIG.2, the pixel circuit further includes a second initialization circuit31.

The second initialization circuit31is electrically connected to an initial control line R2, a second initial voltage terminal12and the first electrode of the light-emitting element10, and configured to write a second initial voltage Vint2from the second initial voltage terminal12into the first electrode of the light-emitting element10under control of an initial control signal from the initial control line R2, so as to control the light-emitting element10not to emit light, reset a potential at the first electrode of the light-emitting element10, and release residual charges at the first electrode of the light-emitting element10.

During the operation of the pixel circuit inFIG.3, within the compensation stage, the second initialization circuit31writes the second initial voltage Vint2from the second initial voltage terminal12into the first electrode of the light-emitting element10under control of the initial control signal, to control the light-emitting element10not to emit light, and release residual charges at the first electrode of the light-emitting element10.

When the pixel circuit inFIG.3operates in the high-frequency driving mode, the initial control line R2may receive, but not limited to, a same control signal as the compensation control line B1, and the initial control line R2and the compensation control line B1may be, but not limited to, a same control line.

When the pixel circuit inFIG.3operates in the low-frequency driving mode, the initial control line R2and the compensation control line B1may receive different control signals, and the initial control line R2and the compensating control line B1may be different control lines.

In at least one embodiment of the present disclosure, when the pixel circuit operates in the low-frequency driving mode, the display frame may be the refresh frame, and the display period may further include a maintaining frame, the maintaining frame may include a second initialization stage and a second light-emission stage arranged one after another.

Within the second initialization stage, the second initialization circuit31writes the second initial voltage Vint2from the second initial voltage terminal12into the first electrode of the light-emitting element10under control of the reset control signal RS, to control the light-emitting element10not to emit light, and release residual charges at the first electrode of the light-emitting element10.

Within the second light-emission stage, the first light-emission control circuit12controls the first terminal of the driving circuit11to be electrically connected to the light-emitting element10under control of the light-emission control signal, and the second light-emission control circuit21controls the first voltage terminal V1to be electrically connected to the second terminal of the driving circuit11under control of the light-emission control signal, and the driving circuit11drives the light-emitting element to emit light.

In a possible embodiment of the present disclosure, the data written-in circuit includes a first transistor, the compensation control circuit includes a second transistor, the energy storage circuit includes a storage capacitor, and the driving circuit includes a driving transistor.

A control electrode of the first transistor is electrically connected to the written-in control line, a first electrode of the first transistor is electrically connected to the data line, and a second electrode of the first transistor is electrically connected to the first terminal of the driving circuit.

A control electrode of the second transistor is electrically connected to the compensation control line, a first electrode of the second transistor is electrically connected to the control terminal of the driving circuit, and a second electrode of the second transistor is electrically connected to the second terminal of the driving circuit.

A first terminal of the storage capacitor is electrically connected to the control terminal of the driving circuit, and a second terminal of the storage capacitor is electrically connected to the first electrode of the light-emitting element.

A control electrode of the driving transistor is the control terminal of the driving circuit, a first electrode of the driving transistor is the first terminal of the driving circuit, and a second electrode of the driving transistor is the second terminal of the driving circuit.

In a possible embodiment of the present disclosure, the second light-emission control circuit includes a third transistor, and the first light-emission control circuit includes a fourth transistor.

A control electrode of the third transistor is electrically connected to the light-emission control line, a first electrode of the third transistor is electrically connected to the first voltage terminal, and a second electrode of the third transistor is electrically connected to the second terminal of the driving circuit.

A control electrode of the fourth transistor is electrically connected to the light-emission control line, a first electrode of the fourth transistor is electrically connected to the first terminal of the driving circuit, and a second electrode of the fourth transistor is electrically connected to the first electrode of the light-emitting element.

In a possible embodiment of the present disclosure, the first initialization circuit includes a fifth transistor. A control electrode of the fifth transistor is electrically connected to the reset control line, a first electrode of the fifth transistor is electrically connected to the first initial voltage terminal, and a second electrode of the fifth transistor is electrically connected to the control terminal of the driving circuit.

In a possible embodiment of the present disclosure, the second initialization circuit includes a sixth transistor. A control electrode of the sixth transistor is electrically connected to the initial control line, a first electrode of the sixth transistor is electrically connected to the second initial voltage terminal, and a second electrode of the sixth transistor is electrically connected to the first electrode of the light-emitting element.

As shown inFIG.4, on the basis of the pixel circuit inFIG.3, the data written-in circuit16includes a first transistor T1, the compensation control circuit15includes a second transistor T2, the energy storage circuit14includes a storage capacitor C1, the driving circuit11includes a driving transistor T0, and the light-emitting element is an organic light-emitting diode O1.

A gate electrode of the first transistor T1is electrically connected to a first scanning control line G1, a drain electrode of the first transistor T1is electrically connected to the data line D1, and a source electrode of the first transistor T1is electrically connected to a source electrode of the driving transistor T0.

A gate electrode of the second transistor T2is electrically connected to the first scanning control line G1, a drain electrode of the second transistor T2is electrically connected to a gate electrode of the driving transistor T0, and a source electrode of the second transistor T2is electrically connected to a drain electrode of the driving transistor T0.

A first terminal of the storage capacitor C1is electrically connected to the gate electrode of the drive transistor T0, and a second terminal of the storage capacitor C1is electrically connected to an anode of the organic light-emitting diode O1.

The second light-emission control circuit21includes a third transistor T3, and the first light-emission control circuit12includes a fourth transistor T4.

A gate electrode of the third transistor T3is electrically connected to the light-emission control line E1, a drain electrode of the third transistor T3is electrically connected to the high voltage terminal VDD, and a source electrode of the third transistor T3is electrically connected to a drain electrode of the driving transistor T0.

A gate electrode of the fourth transistor T4is electrically connected to the light-emission control line E1, a drain electrode of the fourth transistor T4is electrically connected to the source electrode of the driving transistor T0, and a source electrode of the fourth transistor T4is electrically connected to the anode of the organic light-emitting diode O1.

The first initialization circuit13includes a fifth transistor T5, a gate electrode of the fifth transistor T5is electrically connected to the reset control line R1, a drain electrode of the fifth transistor T5is electrically connected to the first initial voltage terminal I1, and a source electrode of the fifth transistor T5is electrically connected to the gate electrode of the driving transistor T0.

The second initialization circuit32includes a sixth transistor T6, a gate electrode of the sixth transistor T6is electrically connected to the first scanning control line G1, a drain electrode of the sixth transistor T6is electrically connected to the second initial voltage terminal12, and a source electrode of the sixth transistor T6is electrically connected to the anode of the organic light-emitting diode O1.

A cathode of the organic light-emitting diode O1is electrically connected to the low voltage terminal VSS.

The pixel circuit inFIG.4is a brand new 7T1C pixel circuit which is capable of efficiently supporting the characteristic of full oxide devices.

In the pixel circuit inFIG.4, T1, T2, T3, T4, T5, T6and T0are each, but not limited to, an oxide transistor, and T1, T2, T3, T4, T5, T6and T0are each, but not limited to, an NMOS (N-type metal-oxide-semiconductor) transistor.

In the pixel circuit inFIG.4, the compensation control line, the written-in control line and the initial control line are a same control line, i.e., the first scanning control line G1, and the pixel circuit inFIG.4is able to operate in the high-frequency driving mode.

InFIG.4, N1denotes a first node, and the first node N1is electrically connected to the gate electrode of T0. N2denotes a second node, and the second node N2is electrically connected to the drain electrode of T0. N3denotes a third node, and the third node N3is electrically connected to the source electrode of T0. N4denotes a fourth node, and the fourth node N4is electrically connected to the anode of O1.

As shown inFIG.5, when the pixel circuit inFIG.4operates in the high-frequency driving mode, the display frame may include a first initialization stage S11, a compensation stage S12and a first light-emission stage S13arranged one after another.

Within the first initialization phase S11, a low voltage signal is applied to E1, a high voltage signal is applied to R1, a low voltage signal is applied to G1, T5is turned on, a first initial voltage Vint1is applied to I1and written into the first node N1, so that T0is turned on at the beginning of the compensation stage S12.

Within the compensation stage S12, a low voltage signal is applied to E1, a low voltage signal is applied to R1, a high voltage signal is applied to G1, T1, T2and T6are all turned on, and T5is turned off. The data voltage Vdata is applied to the data line D1, and a second initial voltage Vint2is applied to I2. The data voltage Vdata is written into the third node N3, and the first node N1is controlled to be electrically connected to the second node N2. Vint2is written into the fourth node N4to enable O1not to emit light, and release residual charges at the anode of O1.

At the beginning of the compensation phase S12, T0is turned on, C1is charged via the data voltage Vdata, so as to change a potential at the first node N1until T0is turned off. At this time, a potential at the third node N3is Vdata, and the potential at the first node N1and a potential at the second node N2are each Vdata+Vth. A potential at the fourth node N4is VINT2, and Vth is a threshold voltage of T0.

Within the first light-emission stage S13, a high voltage signal is applied to E1, a low voltage signal is applied to R1and G1, T3and T4are turned on, and T0drives O1to emit light.

Within the first light-emission stage S13, the potential at the fourth node N4is Vo+Vs: the potential at the first node N1becomes Vdata+Vth+Vo+Vs−Vint2, and Vgs is equal to Vdata+Vth−Vint2, where Vo is a turning-on voltage of O1, and Vs is a voltage value of a low voltage signal from the low voltage terminal VSS.

Within the first light-emission stage S13, a driving current Io that T0drives O1to emit light is equal to 0.5K (Vdata−Vint2)2, where K is a current coefficient of T0. Based on the formula of Io, Io is independent of the threshold voltage Vth of T0, so as to realize the threshold voltage compensation.

InFIG.5, VN1is the potential at the first node N1, VN2is the potential at the second node N2, VN3is the potential at the third node N3, and VN4is the potential at the fourth node N4.

In at least one embodiment of the present disclosure, Vint1may be greater than or equal to 0V and smaller than or equal to 10V. For example, Vint1may be, but limited to, 0V, 2V, 4V, 5V, 6V, 8V or 10V.

Vint2may be greater than or equal to −10V and smaller than or equal to 0V. For example, Vint2may be, but limited to, −10V, −8V, −7V, −6V, −4V, −2V or 0V.

In a possible embodiment of the present disclosure, Vint2may be, but limited to, the same with voltage value of the low voltage signal from the low voltage terminal VSS.

As shown inFIG.6, on the basis of the pixel circuit inFIG.3, the data written-in circuit16includes a first transistor T1, the compensation control circuit15includes a second transistor T2, the energy storage circuit14includes a storage capacitor C1, the driving circuit11includes a driving transistor T0, and the light-emitting element is an organic light-emitting diode O1.

A gate electrode of the first transistor T1is electrically connected to a second scanning control line G2, a drain electrode of the first transistor T1is electrically connected to the data line D1, and a source electrode of the first transistor T1is electrically connected to a source electrode of the driving transistor T0.

A gate electrode of the second transistor T2is electrically connected to the first scanning control line G1, a drain electrode of the second transistor T2is electrically connected to a gate electrode of the driving transistor T0, and a source electrode of the second transistor T2is electrically connected to a drain electrode of the driving transistor T0.

A first terminal of the storage capacitor C1is electrically connected to the gate electrode of the drive transistor T0, and a second terminal of the storage capacitor C1is electrically connected to an anode of the organic light-emitting diode O1.

The second light-emission control circuit21includes a third transistor T3, and the first light-emission control circuit12includes a fourth transistor T4.

A gate electrode of the third transistor T3is electrically connected to the light-emission control line E1, a drain electrode of the third transistor T3is electrically connected to the high voltage terminal VDD, and a source electrode of the third transistor T3is electrically connected to a drain electrode of the driving transistor T0.

A gate electrode of the fourth transistor T4is electrically connected to the light-emission control line E1, a drain electrode of the fourth transistor T4is electrically connected to the source electrode of the driving transistor T0, and a source electrode of the fourth transistor T4is electrically connected to the anode of the organic light-emitting diode O1.

The first initialization circuit13includes a fifth transistor T5, a gate electrode of the fifth transistor T5is electrically connected to the reset control line R1, a drain electrode of the fifth transistor T5is electrically connected to the first initial voltage terminal I1, and a source electrode of the fifth transistor T5is electrically connected to the gate electrode of the driving transistor T0.

The second initialization circuit32includes a sixth transistor T6, a gate electrode of the sixth transistor T6is electrically connected to the first scanning control line G1, a drain electrode of the sixth transistor T6is electrically connected to the second initial voltage terminal12, and a source electrode of the sixth transistor T6is electrically connected to the anode of the organic light-emitting diode O1.

A cathode of the organic light-emitting diode O1is electrically connected to the low voltage terminal VSS.

The pixel circuit inFIG.6is a brand new 7T1C pixel circuit which is capable of efficiently supporting the characteristic of full oxide devices.

In the pixel circuit inFIG.6, T1, T2, T3, T4, T5, T6and T0are each, but not limited to, an oxide transistor, and T1, T2, T3, T4, T5, T6and T0are each, but not limited to, an NMOS (N-type metal-oxide-semiconductor) transistor.

In the pixel circuit inFIG.6, the compensation control line and the initial control line are a same control line, i.e., being the first scanning control line G1and the writing control line is the second scanning control line G2, and the pixel circuit inFIG.6is able to operate in the high-frequency driving mode and the low-frequency driving mode.

InFIG.6, N1denotes a first node, and the first node N1is electrically connected to the gate electrode of T0. N2denotes a second node, and the second node N2is electrically connected to the drain electrode of T0. N3denotes a third node, and the third node N3is electrically connected to the source electrode of T0. N4denotes a fourth node, and the fourth node N4is electrically connected to the anode of O1.

In the pixel circuit inFIG.6, the fifth transistor T5operates under the control of the reset control signal RS from the reset control line R1, so as to freely adjust a time period for resetting the potential at the gate electrode of the driving transistor T0via the first initial voltage Vint1from the first initial voltage terminal I1. The sixth transistor T6operates under the control of a first scanning control signal from the first scanning control line G1and is capable of operating in the low-frequency driving mode, so as to reset the anode of O1. The first transistor T1operates under the control of a second scanning control signal from the second scanning control line G2for data voltage written-in, and the first transistor T1and the sixth transistor T6operate under the control of different control signals, so as to, when operating in the low-frequency driving mode, maintain the first transistor T1to be in an off state during the maintaining frame and control the sixth transistor T6to be turned on during the second initialization stage in the maintaining frame.

As shown inFIG.7, when the pixel circuit inFIG.6operates in the high-frequency driving mode, the display frame may include a first initialization stage S11, a compensation stage S12and a first light-emission stage S13arranged one after another, and the compensation stage S12includes a data written-in time period S0.

Within the first initialization phase S11, a low voltage signal is applied to E1, a high voltage signal is applied to R1, a low voltage signal is applied to G1, a low voltage signal is applied to G2, T5is turned on, a first initial voltage Vint1is applied to I1and written into the first node N1, so that T0is turned on at the beginning of the data written-in time period S0.

Within the compensation stage S12, a low voltage signal is applied to E1, a low voltage signal is applied to R1, a high voltage signal is applied to G1, T2and T6are all turned on, and T5is turned off. A second initial voltage Vint2is applied to I2. The first node N1is electrically connected to the second node N2. Vint2is written into the fourth node N4to enable O1not to emit light, and release residual charges at the anode of O1.

Within the data written-in time period S0, a high voltage signal is applied to G2, a low voltage signal is applied to R1and E1, and the data voltage Vdata is applied to the data line D1, so as to write the data voltage Vdata into the third node N3.

At the beginning of the data written-in time period S0, T0is turned on, C1is charged via the data voltage Vdata, so as to change a potential at the first node N1until T0is turned off. At this time, a potential at the third node N3is Vdata, and the potential at the first node N1and a potential at the second node N2are each Vdata+Vth. A potential at the fourth node N4is VINT2, and Vth is a threshold voltage of T0.

Within the first light-emission stage S13, a high voltage signal is applied to E1, a low voltage signal is applied to R1, G1and G2, T3and T4are turned on, and T0drives O1to emit light.

Within the first light-emission stage S13, the potential at the fourth node N4is Vo+Vs, the potential at the first node N1becomes Vdata+Vth+Vo+Vs−Vint2, and Vgs is equal to Vdata+Vth−Vint2, where Vo is a turning-on voltage of O1, and Vs is a voltage value of a low voltage signal from the low voltage terminal VSS.

Within the first light-emission stage S13, a driving current Io that T0drives O1to emit light is equal to 0.5K (Vdata−Vint2)2, where K is a current coefficient of T0. Based on the formula of Io, Io is independent of the threshold voltage Vth of T0, so as to realize the threshold voltage compensation.

As shown inFIG.8, when the pixel circuit inFIG.6operates in the low-frequency driving mode, the display period may include a refresh frame F1and at least one maintaining frame F2, the refresh frame F1may include a first initialization stage S11, a compensation stage S12and a first light-emission stage S13arranged one after another, the compensation stage S12includes a data written-in time period S0, and the maintaining frame F2includes a second initialization stage S21and a second light-emission stage S22.

Within the first initialization phase S11, a low voltage signal is applied to E1, a high voltage signal is applied to R1, a low voltage signal is applied to G1, a low voltage signal is applied to G2, T5is turned on, a first initial voltage Vint1is applied to I1and written into the first node N1, so that T0is turned on at the beginning of the data written-in time period S0.

Within the compensation stage S12, a low voltage signal is applied to E1, a low voltage signal is applied to R1, a high voltage signal is applied to G1, T2and T6are all turned on, and T5is turned off. A second initial voltage Vint2is applied to I2. The first node N1is electrically connected to the second node N2. Vint2is written into the fourth node N4to enable O1not to emit light, and release residual charges at the anode of O1.

Within the data written-in time period S0, a high voltage signal is applied to G2, a low voltage signal is applied to R1and E1, and the data voltage Vdata is applied to the data line D1, so as to write the data voltage Vdata into the third node N3.

At the beginning of the data written-in time period S0, T0is turned on, C1is charged via the data voltage Vdata, so as to change a potential at the first node N1until T0is turned off. At this time, a potential at the third node N3is Vdata, and the potential at the first node N1and a potential at the second node N2are each Vdata+Vth. A potential at the fourth node N4is VINT2, and Vth is a threshold voltage of T0.

Within the first light-emission stage S13, a high voltage signal is applied to E1, a low voltage signal is applied to R1, G1and G2, T3and T4are turned on, and T0drives O1to emit light.

Within the first light-emission stage S13, the potential at the fourth node N4is Vo+Vs, the potential at the first node N1becomes Vdata+Vth+Vo+Vs−Vint2, and Vgs is equal to Vdata+Vth−Vint2, where Vo is a turning-on voltage of O1, and Vs is a voltage value of a low voltage signal from the low voltage terminal VSS.

Within the first light-emission stage S13, a driving current Io that T0drives O1to emit light is equal to 0.5K (Vdata−Vint2)2, where K is a current coefficient of T0. Based on the formula of Io, Io is independent of the threshold voltage Vth of T0, so as to realize the threshold voltage compensation.

Within the second initialization stage S21, a low voltage signal is applied to E1, a low voltage signal is applied to R1and G2, a high voltage signal is applied to G1, T6and T2are turned on. The second initial voltage Vint2is applied to I2and written into the anode of O1, so as to control O1not to emit light, reset the potential at the anode of O1, and release residual charges at the anode of O1. Since T3and T4are each in an off-state at this time, the display is not adversely affected when T2is turned on.

Within the second light-emission stage S22, a high voltage signal is applied to E1, a low voltage signal is applied to R1, G1, G2and G3, T3and T4are turned on, and T0drives O1to emit light.

Within the maintaining frame F2, a low voltage signal is applied to G2, so as to turn off T1and stop the data voltage written-in, thereby maintaining the display at the brightness of the refresh frame.

When the pixel circuit inFIG.6operates in the low-frequency driving mode, prior to the second light-emission stage in the maintaining frame F1, within the second initialization stage in the maintaining frame F1, T6is turned on to reset the potential at the anode of O1, so that the potential at the anode of O1is maintained as the same before T0drives O1to emit light in each maintaining frame, thereby avoiding the flicker phenomenon in the low-frequency display.

As shown inFIG.9, on the basis of the pixel circuit inFIG.3, the data written-in circuit16includes a first transistor T1, the compensation control circuit15includes a second transistor T2, the energy storage circuit14includes a storage capacitor C1, the driving circuit11includes a driving transistor T0, and the light-emitting element is an organic light-emitting diode O1.

A gate electrode of the first transistor T1is electrically connected to a second scanning control line G2, a drain electrode of the first transistor T1is electrically connected to the data line D1, and a source electrode of the first transistor T1is electrically connected to a source electrode of the driving transistor T0.

A gate electrode of the second transistor T2is electrically connected to the first scanning control line G1, a drain electrode of the second transistor T2is electrically connected to a gate electrode of the driving transistor T0, and a source electrode of the second transistor T2is electrically connected to a drain electrode of the driving transistor T0.

A first terminal of the storage capacitor C1is electrically connected to the gate electrode of the drive transistor T0, and a second terminal of the storage capacitor C1is electrically connected to an anode of the organic light-emitting diode O1.

The second light-emission control circuit21includes a third transistor T3, and the first light-emission control circuit12includes a fourth transistor T4.

A gate electrode of the third transistor T3is electrically connected to the light-emission control line E1, a drain electrode of the third transistor T3is electrically connected to the high voltage terminal VDD, and a source electrode of the third transistor T3is electrically connected to a drain electrode of the driving transistor T0.

A gate electrode of the fourth transistor T4is electrically connected to the light-emission control line E1, a drain electrode of the fourth transistor T4is electrically connected to the source electrode of the driving transistor T0, and a source electrode of the fourth transistor T4is electrically connected to the anode of the organic light-emitting diode O1.

The first initialization circuit13includes a fifth transistor T5, a gate electrode of the fifth transistor T5is electrically connected to the reset control line R1, a drain electrode of the fifth transistor T5is electrically connected to the first initial voltage terminal I1, and a source electrode of the fifth transistor T5is electrically connected to the gate electrode of the driving transistor T0.

The second initialization circuit32includes a sixth transistor T6, a gate electrode of the sixth transistor T6is electrically connected to the third scanning control line G3, a drain electrode of the sixth transistor T6is electrically connected to the second initial voltage terminal12, and a source electrode of the sixth transistor T6is electrically connected to the anode of the organic light-emitting diode O1.

A cathode of the organic light-emitting diode O1is electrically connected to the low voltage terminal VSS.

The pixel circuit inFIG.9is a brand new 7T1C pixel circuit which is capable of efficiently supporting the characteristic of full oxide devices.

In the pixel circuit inFIG.9, T1, T2, T3, T4, T5, T6and T0are each, but not limited to, an oxide transistor, and T1, T2, T3, T4, T5, T6and T0are each, but not limited to, an NMOS (N-type metal-oxide-semiconductor) transistor.

InFIG.9, N1denotes a first node, and the first node N1is electrically connected to the gate electrode of T0. N2denotes a second node, and the second node N2is electrically connected to the drain electrode of T0. N3denotes a third node, and the third node N3is electrically connected to the source electrode of T0. N4denotes a fourth node, and the fourth node N4is electrically connected to the anode of O1.

In the pixel circuit inFIG.9, the compensation control line, the written-in control line and the initial control line are different control lines. The compensation control line is the first scanning control line G1, the written-in control line is the second scanning control line G2, and the initial control line is the third scanning control line G3. The pixel circuit inFIG.9is able to operate in both the high-frequency and low-frequency driving modes.

In the pixel circuit inFIG.9, the fifth transistor T5operates under the control of the reset control signal RS from the reset control line R1, so as to freely adjust a time period for resetting the potential at the gate electrode of the driving transistor T0via the first initial voltage Vint1from the first initial voltage terminal I1. The sixth transistor T6operates under the control of a third scanning control signal from the third scanning control line G3and is capable of operating in the low-frequency driving mode, so as to reset the anode of O1. The first transistor T1operates under the control of the second scanning control signal from the second scanning control line G2for data voltage written-in, and the first transistor T1and the sixth transistor T6operate under the control of different control signals so as to, when operating in the low-frequency driving mode, maintain the first transistor T1to be in an off state during the maintaining frame and control the sixth transistor T6to be turned on during the second initialization stage in the maintaining frame.

As shown inFIG.10, when the pixel circuit inFIG.9operates in the high-frequency driving mode, the display frame may include a first initialization stage S11, a compensation stage S12and a first light-emission stage S13arranged one after another, and the compensation stage S12includes a data written-in time period S0.

Within the first initialization phase S11, a low voltage signal is applied to E1, a high voltage signal is applied to R1, a low voltage signal is applied to G1, G2and G3, T5is turned on, a first initial voltage Vint1is applied to I1and written into the first node N1, so that T0is turned on at the beginning of the data written-in time period S0.

Within the compensation stage S12, a low voltage signal is applied to E1, a low voltage signal is applied to R1, a high voltage signal is applied to G1, a high voltage signal is applied to G3, T2and T6are turned on, and T5is turned off. A second initial voltage Vint2is applied to I2. The first node N1is electrically connected to the second node N2. Vint2is written into the fourth node N4to enable O1not to emit light, reset the potential at the anode of O1, and release residual charges at the anode of O1.

Within the data written-in time period S0, a high voltage signal is applied to G2, a low voltage signal is applied to R1and E1, and the data voltage Vdata is applied to the data line D1, so as to write the data voltage Vdata into the third node N3.

At the beginning of the data written-in time period S0, T0is turned on, C1is charged via the data voltage Vdata, so as to change a potential at the first node N1until T0is turned off. At this time, a potential at the third node N3is Vdata, and the potential at the first node N1and a potential at the second node N2are each Vdata+Vth. A potential at the fourth node N4is VINT2, and Vth is a threshold voltage of T0.

Within the first light-emission stage S13, a high voltage signal is applied to E1, a low voltage signal is applied to R1, G1and G2, T3and T4are turned on, and T0drives O1to emit light.

Within the first light-emission stage S13, the potential at the fourth node N4is Vo+Vs, the potential at the first node N0becomes Vdata+Vth+Vo+Vs−Vint2, and Vgs is equal to Vdata+Vth-Vint2, where Vo is a turning-on voltage of O1, and Vs is a voltage value of a low voltage signal from the low voltage terminal VSS.

Within the first light-emission stage S13, a driving current Io that T0drives O1to emit light is equal to 0.5K (Vdata−Vint2)2, where K is a current coefficient of T0. Based on the formula of Io, Io is independent of the threshold voltage Vth of T0, so as to realize the threshold voltage compensation.

As shown inFIG.11, when the pixel circuit inFIG.9operates in the low-frequency driving mode, the display period may include a refresh frame F1and at least one maintaining frame F2, the refresh frame F1may include a first initialization stage S11, a compensation stage S12and a first light-emission stage S13arranged one after another, the compensation stage S12includes a data written-in time period S0, and the maintaining frame F2includes a second initialization stage S21and a second light-emission stage S22.

Within the first initialization phase S11, a low voltage signal is applied to E1, a high voltage signal is applied to R1, a low voltage signal is applied to G1, G2and G3, T5is turned on, a first initial voltage Vint1is applied to I1and written into the first node N1, so that T0is turned on at the beginning of the data written-in time period S0.

Within the compensation stage S12, a low voltage signal is applied to E1, a low voltage signal is applied to R1, a high voltage signal is applied to G1, a high voltage signal is applied to G3, T2and T6are turned on, and T5is turned off. A second initial voltage Vint2is applied to I2. The first node N1is electrically connected to the second node N2. Vint2is written into the fourth node N4to enable O1not to emit light, reset the potential at the anode of O1, and release residual charges at the anode of O1.

Within the data written-in time period S0, a high voltage signal is applied to G2, a low voltage signal is applied to R1and E1, and the data voltage Vdata is applied to the data line D1, so as to write the data voltage Vdata into the third node N3.

At the beginning of the data written-in time period S0, T0is turned on, C1is charged via the data voltage Vdata, so as to change a potential at the first node N1until T0is turned off. At this time, a potential at the third node N3is Vdata, and the potential at the first node N1and a potential at the second node N2are each Vdata+Vth. A potential at the fourth node N4is VINT2, and Vth is a threshold voltage of T0.

Within the first light-emission stage S13, a high voltage signal is applied to E1, a low voltage signal is applied to R1, G1and G2, T3and T4are turned on, and T0drives O1to emit light.

Within the first light-emission stage S13, the potential at the fourth node N4is Vo+Vs, the potential at the first node N1becomes Vdata+Vth+Vo+Vs−Vint2, and Vgs is equal to Vdata+Vth−Vint2, where Vo is a turning-on voltage of O1, and Vs is a voltage value of a low voltage signal from the low voltage terminal VSS.

Within the first light-emission stage S13, a driving current Io that T0drives O1to emit light is equal to 0.5K (Vdata−Vint2)2, where K is a current coefficient of T0. Based on the formula of Io, Io is independent of the threshold voltage Vth of T0, so as to realize the threshold voltage compensation.

Within the second initialization stage S21, a low voltage signal is applied to E1, a high voltage signal is applied to G3, a low voltage signal is applied to R1, G1and G2, T6is turned on. The second initial voltage Vint2is applied to I2and written into the anode of O1, so as to control O1not to emit light, reset the potential at the anode of O1, and release residual charges at the anode of O1.

Within the second light-emission stage S22, a high voltage signal is applied to E1, a low voltage signal is applied to R1, G1, G2and G3, T3and T4are turned on, and T0drives O1to emit light.

When the pixel circuit inFIG.9operates in the low-frequency driving mode, prior to the second light-emission stage in the maintaining frame F1, within the second initialization stage in the maintaining frame F1, T6is turned on to reset the potential at the anode of O1, so that the potential at the anode of O1is maintained as the same before T0drives O1to emit light in each maintaining frame, thereby avoiding the flicker phenomenon in the low-frequency display.

Optionally, in at least one embodiment of the present disclosure, the pixel circuit may further include a third initialization circuit, the third initialization circuit is electrically connected to the reset control line and a third initial voltage terminal, the third initialization circuit is electrically connected to the first terminal of the driving circuit or the second terminal of the driving circuit, and the third initialization circuit is configured to write a third initial voltage from the third initial voltage terminal into the first terminal of the driving circuit or the second terminal of the driving circuit under control of the reset control signal RS from the reset control line.

In at least one embodiment of the present disclosure, the pixel circuit may further include the third initialization circuit, and the third initialization circuit may write the third initial voltage to the first terminal of the driving circuit or the second terminal of the driving circuit when the first initialization circuit resets the potential at the control terminal of the driving circuit, so as to increase a bias voltage of the driving transistor of the driving circuit, thereby to mitigate the hysteresis phenomenon of the driving transistor.

In at least one embodiment of the present disclosure, when the first initial voltage Vint1is of a positive value, the third initial voltage Vint3may be of a negative value, so that when the first initialization circuit controls to write the first initial voltage Vint1into the gate electrode of the driving transistor, and the third initialization circuit controls to write the third initial voltage Vint3into the first electrode of the driving transistor or the second electrode of the driving transistor, a gate-source voltage of the driving transistor is much greater than the threshold voltage Vth of the driving transistor, thereby increasing the bias voltage of the driving transistor.

In a possible embodiment of the present disclosure, the third initialization circuit includes a seventh transistor, a control electrode of the seventh transistor is electrically connected to the reset control line, a first electrode of the seventh transistor is electrically connected to the third initial voltage terminal, and a second electrode of the seventh transistor is electrically connected to the first terminal of the driving circuit or the second terminal of the driving circuit.

As shown inFIG.12, on the basis of the pixel circuit inFIG.3, the pixel circuit may further include a third initialization circuit110.

The third initialization circuit110is electrically connected to the reset control line R1and a third initial voltage terminal I3, the third initialization circuit110is electrically connected to the second terminal of the driving circuit11, and the third initialization circuit110is configured to write a third initial voltage Vint3from the third initial voltage terminal I3into the second terminal of the driving circuit11under control of the reset control signal RS from the reset control line R1.

During the operation of the pixel circuit inFIG.12, within the first initialization stage, the third initialization circuit110writes the third initial voltage Vi3from the third initial voltage terminal I3into the second terminal of the driving circuit11under the control of the reset control signal RS.

As shown inFIG.13, on the basis of the pixel circuit inFIG.9, the pixel circuit further includes a third initialization circuit110

The third initialization circuit110includes a seventh transistor T7, a gate electrode of the seventh transistor T7is electrically connected to the reset control line R1, a drain electrode of the seventh transistor T7is electrically connected to the third initial voltage terminal I3, and a source electrode of the seventh transistor T7is electrically connected to the second node N2.

In the pixel circuit inFIG.13, all transistors are each an oxide transistor, and all transistors are each an NMOS transistor.

During the operation of the pixel circuit inFIG.13, within the first initialization stage, a high voltage signal is applied to R1, T7is turned on, the third initial voltage Vint3is applied to the third initial voltage terminal I3and written into the second node N2, T5is turned on, and the first initial voltage Vint1is applied to the first initial voltage terminal I1and written into the gate electrode of T0, so as to increase the bias voltage of the driving transistor T0, thereby to mitigate the hysteresis phenomenon of the driving transistor T0.

In at least one embodiment of the present disclosure, a transistor in the light-emission control circuit, a transistor in the data written-in circuit, a transistor in the compensation control circuit, a transistor in the driving circuit, a transistor in the first initialization circuit, a transistor in the second initialization circuit, and a transistor in the third initialization circuit are each an oxide thin film transistor.

The present disclosure provides in some embodiments a display device including the above-mentioned pixel circuit.

The display device may be any product or member having a display function, e.g., a mobile phone, a flat-panel computer, a television, a display, a laptop computer, a digital photo frame or a navigator.

The above embodiments are for illustrative purposes only, but the present disclosure is not limited thereto. Obviously, a person skilled in the art may make further modifications and improvements without departing from the spirit of the present disclosure, and these modifications and improvements shall also fall within the scope of the present disclosure.