Patent ID: 12231106

DETAILED DESCRIPTION

Certain details are set forth below to provide a sufficient understanding of embodiments of the invention. However, it will be clear to one skilled in the art that embodiments of the invention may be practiced without these particular details. Moreover, the particular embodiments of the present invention described herein are provided by way of example and should not be used to limit the scope of the invention to these particular embodiments. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the invention.

FIG.1is a block diagram of a semiconductor device10according to an embodiment of the disclosure. The semiconductor device10may be a DDR5 SDRAM integrated into a single semiconductor chip, for example. The semiconductor device10may be mounted on an external substrate2that is a memory module substrate, a mother board or the like. The external substrate2employs an external resistance RZQ that is coupled to a calibration terminal ZQ27of the semiconductor device10. The external resistance RZQ is a reference impedance used by impedance (ZQ) calibration circuit38. In the present embodiment, the external resistance RZQ, which may also be referred to as an external ZQ resistor, is coupled to a power supply voltage. In some embodiments, the impedance of the external resistance RZQ is 240 ohms. In some embodiments of the disclosure the power supply voltage to which the external resistance RZQ is coupled may be a power supply voltage Vdd2H, as will be described in more detail below. However, the scope of the disclosure is not limited to the external resistance RZQ being coupled to the power supply voltage Vdd2H, and the external resistance RZQ may be coupled to another power supply in another embodiment of the disclosure. For example, in other embodiments of the disclosure the external resistance RZQ may be connected to a power supply voltage VDDQ, or to another power supply voltage.

As shown inFIG.1, the semiconductor device10includes a memory cell array11. The memory cell array11includes a plurality of banks, cach bank including a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. The selection of the word line WL is performed by a row decoder12and the selection of the bit line BL is performed by a column decoder13. Sense amplifiers18are coupled to corresponding bit lines BL and coupled to local I/O line pairs LIOT/B. Local IO line pairs LIOT/B are coupled to main IO line pairs MIOT/B via transfer gates TG19which function as switches.

Turning to the explanation of a plurality of external terminals included in the semiconductor device10, the plurality of external terminals includes address terminals21, command terminals22, clock terminals23, data terminals24, power supply terminals25and26, and the calibration terminal ZQ27. An input signal block41may include the address terminals21, the command terminals22and the clock terminals23. A data interface block42includes the data terminals24. The data terminals24may be coupled to output buffers for read operations of memories. Alternatively, the data terminals24may be coupled to input buffers for read/write access of the memories that will be later described.FIG.1shows an example of dynamic random access memory (DRAM), however, any device having external terminals for signal input/output may be included as the external terminals of embodiments of the disclosure.

The address terminals21are supplied with an address signal ADD and a bank address signal BADD. The address signal ADD and the bank address signal BADD supplied to the address terminals21are transferred via an address input circuit31to an address decoder32. The address decoder32receives the address signal ADD and supplies a decoded row address signal XADD to the row decoder12, and a decoded column address signal YADD to the column decoder13. The address decoder32also receives the bank address signal BADD and supplies the bank address signal BADD to the row decoder12and the column decoder13.

The command terminals22are supplied with a command signal COM. The command signal COM may include one or more separate signals. The command signal COM input to the command terminals21is input to a command decoder34via the command input circuit33. The command decoder34decodes the command signal COM to generate various internal command signals. For example, the internal commands may include a row command signal to select a word line and a column command signal, such as a read command or a write command, to select a bit line, and a calibration signal ZQ_COM provided to the calibration circuit38.

Accordingly, when a read command is issued and a row address and a column address are timely supplied with the read command, read data is read from a memory cell MC in the memory cell array11designated by these row address and column address. The read data DQ is output externally from the data terminals24via a read/write amplifier15and an input/output circuit17. Similarly, when the write command is issued and a row address and a column address are timely supplied with the write command, and then write data DQ is supplied to the data terminals24, the write data DQ is supplied via the input/output circuit17and the read/write amplifier15to the memory cell array11and written in the memory cell MC designated by the row address and the column address. The input/output circuit17may include input buffers and output buffers, according to one embodiment. The input/output circuit17may include programmable termination components30. The programmable termination components30of the input/output circuit17may be set to provide impedances of the input buffer and output buffer of the input/output circuit17. As previously described, the impedance of the programmable termination components may be used to reduce impedance mismatch.

The clock terminals23are supplied with external clock signals CK and /CK, respectively. These external clock signals CK and /CK are complementary to each other and are supplied to a clock input circuit35. The clock input circuit35receives the external clock signals CK and /CK and generates an internal clock signal ICLK. The internal clock signal ICLK is supplied to an internal clock generator36and thus a phase controlled internal clock signal LCLK is generated based on the received internal clock signal ICLK and a clock enable signal CKE from the command input circuit33. Although not limited thereto, a DLL circuit can be used as the internal clock generator36. The phase controlled internal clock signal LCLK is supplied to the input/output circuit17and is used as a timing signal for determining an output timing of the read data DQ. The internal clock signal ICLK is also supplied to a timing generator37and thus various internal clock signals can be generated.

A temperature sensor44senses a temperature of the semiconductor device10and provides a TEMP signal, which is indicative of a temperature of the semiconductor device10. In some embodiments, the TEMP signal may be a digital signal having a value indicative of a temperature of the semiconductor device. In some embodiments, the TEMP signal may have a voltage level indicative of a temperature of the semiconductor device. For example, a value of the VTEMP signal may increase if the temperature of the semiconductor device increases.

A mode register46is used to define various modes of programmable operations and configurations of the semiconductor device10. The mode register retains the stored information until it is reprogrammed, reset, or the semiconductor device10loses power. The mode register46is programmed via a mode register write command. The mode register46may include one or more registers for storing information related to the different operations and configurations. For example, the mode register may be used to set burst length, burst type, CAS latency, frequency set point, enable programmable termination components, as well as others. The mode register46may also be programmed with information that can be read to provide status information about the semiconductor device10. For example, the mode register may be used to provide a ready status, calibration status, as well as other status information. The information that is read may be programmed by circuits of the semiconductor device10. The mode register46may be read via a mode register read command. Reading the mode register46allows information about the status of operations and configurations to be provided by the semiconductor device10.

The power supply terminals25are supplied with power supply voltages VDD and VSS. These power supply voltages VDD and VSS are supplied to an internal power supply circuit39. The internal power supply circuit39generates various internal voltages VPP, VOD, VARY, VPERI, Vdd2H and a reference voltage ZQVREF. The Vdd2H voltage may be an internal voltage used as an output voltage to drive output signals. The internal voltage VPP is mainly used in the row decoder12, the internal voltages VOD and VARY are mainly used in the sense amplifiers18included in the memory cell array11, and the internal voltage VPERI is used in many other circuit blocks. The reference voltage ZQVREF is used by the calibration circuit38. In some embodiments, the ZQVREF is based on the Vdd2H voltage.

The power supply terminals26are supplied with power supply voltages VDDQ and VSSQ. These power supply voltages VDDQ and VSSQ are supplied to the input/output circuit17. The power supply voltages VDDQ and VSSQ may be the same voltages as the power supply voltages VDD and VSS that are supplied to the power supply terminals25, respectively. However, the dedicated power supply voltages VDDQ and VSSQ may be used for the input/output circuit17so that power supply noise generated by the input/output circuit17does not propagate to the other circuit blocks.

The power supply voltage VDDQ may change during operation. For example, the power supply voltage VDDQ may change from a relatively low voltage (e.g., 0.3 volts) to a relatively high voltage (e.g., 0.5 volts), and vice versa. The power supply voltage VDDQ may be changed when a frequency set point of the semiconductor device10is changed. Changing frequency set point for the semiconductor device10changes the frequency of operation, for example, the operating speed of the input/output circuits17. Lower frequencies of operation may operate without the use of on-die terminations, while higher frequencies of operation may require using on-die terminations to mitigate impedance mismatch. Lower voltages may be used for lower frequencies of operation due to reduced voltage swing from being unterminated, whereas higher voltages are used for higher frequencies of operation. For example, when switching from a relatively low frequency set point to a higher frequency set point the power supply voltage VDDQ may change from relatively low voltage to a higher power supply voltage VDDQ. Conversely, when switching from a relatively high frequency set point to a lower frequency set point the power supply voltage VDDQ may change from relatively high voltage to a lower power supply voltage VDDQ. In some examples, external resistance RZQ is connected to the power supply voltage VDDQ.

The calibration circuit38include circuits to perform calibration operations when activated by the calibration signal ZQ_COM. The calibration operations may be performed with reference to an impedance of an external resistance RZQ and the reference voltage ZQVREF. The calibration circuit38is coupled to the calibration terminal ZQ27. In embodiments where a plurality of semiconductor devices10have respective calibration terminals ZQ27coupled to an external resistance RZQ, the calibration circuit38arbitrates amongst the plurality of semiconductor devices10for use of the external resistance RZQ during calibrations operations. During a calibration operation, the calibration circuit38calibrate impedances of programmable termination components to the external resistance RZQ by determining appropriate calibration parameters that are used to set the programmable termination component impedance. The calibration parameters determined by the calibration circuit38during the calibration operation may be stored by the calibration circuit38. The stored calibration parameters may be retrieved and applied to the programmable termination components. An impedance code ZQCODE representing calibration parameters is supplied to the input/output circuit17to set the programmable termination components to the desired impedance for the buffers of the input/output circuit17.

The calibration circuit38programs calibration information ZQRDY into the mode register46. The calibration information ZQRDY reflects an aspect of the calibration operation. For example, in some embodiments the value of the calibration information ZQRDY programmed in the mode register46represents whether the calibration operation is completed. In some embodiments the value of the calibration information ZQRDY represents whether any new calibration parameters have been determined by a calibration circuit38. The mode registers125may be queried, for example, by a memory controller, to retrieve the calibration information reflecting an aspect of the calibration operation, for example, completion of the calibration operations and/or new calibration parameters have been determined.

Providing the calibration information to be queried allows for a memory controller to be informed as to an aspect of the calibration operation. In some embodiments, the calibration information may be used by the memory controller to determine when to issue a command to apply the calibration parameters, rather than issuing the command at the end of a time period under the assumption that all devices have completed calibration operations. As previously described, as systems include more and more devices, completing calibration operations for the multiple device system within the time period becomes very challenging. By programming calibration information into the mode registers, a memory controller can determine when to issue the command to apply the calibration parameters by periodically reading the mode register rather than idling until the calibration operations are completed.

In some embodiments, following completion of the calibration operation for a power up sequence, the calibration parameters may be applied by the semiconductor device without relying on any commands from a memory controller. For example, the semiconductor device applies the calibration parameters automatically after determining the calibration operation is completed without waiting for a command from the memory controller. In this manner, the memory controller does not need to be involved with the calibration of impedances during a power up sequence. The memory controller, however, may check the status of the calibration operation by checking the calibration information in the mode register.

Programming calibration information into the mode registers also allows the total time for the calibration operations to exceed the time period without negatively impacting power up time due to the memory controller idling until the calibration operations for all of the devices are completed. Additionally, in some embodiments, the calibration parameters are applied to set impedances without the need to receive a command to do so. The calibration parameters may be applied automatically after completing the calibration operations. More generally, completion of calibration operations for the devices is not rushed, and the memory controller may perform other start up related operations during the time for the calibration operations.

FIG.2Ais a block diagram of a semiconductor memory200according to an embodiment of the disclosure. The semiconductor memory200may be a volatile memory such as a SRAM or DRAM, or a non-volatile memory such as a FLASH memory or a ferroelectric memory. In one embodiment, the Double Data Rate (DDR) memory, such as a Low Power Double Data Rate 5 (LPDDR5) memory. In accordance with various embodiments, the semiconductor memory200may include a plurality of individual semiconductor devices204that may be arranged on one or more different semiconductor dies. In some embodiments, the semiconductor device10ofFIG.1may be used as the individual semiconductor devices204of the semiconductor memory200.

The semiconductor memory200may include a package that contains and interconnects the various individual semiconductor devices204. The package may provide a plurality of external pins that couple to contact pads arranged on the interior of the package. The pins and pads may provide electrical connections such as between the semiconductor devices204and the larger system to which the semiconductor memory200is coupled. As shown inFIG.2A, the semiconductor memory200may include an internal pad, which may be referred to as the ZQ pad112. An external resistance RZQ may couple to the ZQ pad112.

One or more of the individual semiconductor devices204are coupled to the ZQ pad112to share the external resistance RZQ for impedance calibration. Each of the semiconductor devices204may be coupled to the ZQ pad112at a respective calibration terminal ZQ27. As previously described, where several semiconductor devices204have respective calibration terminals ZQ27sharing an external resistance RZQ, the semiconductor devices204need to arbitrate for use of the external resistance RZQ during calibrations operations and obtain control over the external resistance RZQ before initiating calibration operations.

The semiconductor memory200may be associated with one or more memory controllers240that are configured to provide data communication to and from the semiconductor memory200. Each memory controller240may communicate across a separate memory bus252that couples the memory controller240to one or more individual semiconductor devices204of the semiconductor memory200. Each memory bus252associated with a given memory controller240may include address, data, and control lines that are connected in common between the various semiconductor devices204with which the respective memory controller240communicates. Each memory bus252may additionally include individual chip select lines256that may be selectively asserted to enable one of the semiconductor devices204to send or receive data across the common address, data, and control lines. Through the combination of individual chip select lines256and common address, data, and control lines, a memory bus252associated with a given memory controller240provides separate communication pathways between the memory controller and each of the various semiconductor devices204with which the memory controller240communicates.

As will be described in more detail below, the calibration circuit38is configured to arbitrate and perform ZQ calibration operations and maintain calibration parameters in the background. That is, the calibration circuit38may perform ZQ calibration operations and maintain calibration parameters without receiving a calibration command, for example, from a memory controller. In this manner, calibration operations can be performed and the calibration parameters maintained by the semiconductor device10without waiting for a calibration command.

Calibration operations may be performed as part of a power-on sequence that occurs when power is first provided to the semiconductor device10. Calibration operations may also be performed by the calibration circuit38when there is a change in operating condition for the semiconductor device10. For example, calibration operations may be performed by the calibration circuit38based on the operating temperature of the semiconductor device10, such as a change in the operating temperature may cause calibration operations to be performed, or the operating temperature exceeds or falls below a temperature limit. Calibration operations may also be performed based on time. For example, the calibration circuit38may perform calibration operations after a time period has elapsed. The calibration circuit38may perform calibration operations periodically as another example.

The calibration circuit38may provide an indication of completing calibration operations or determining new calibration parameters by updating information in the mode registers125. For example, in some embodiments, the calibration circuit38updates a bit stored in the mode registers125. The mode registers125may be queried, for example, by a memory controller, to retrieve the updated bit reflecting the completion of the calibration operations. The calibration circuit38may additionally or alternatively update information in the mode registers125to provide indication of updated calibration parameters. The calibration parameters may be changed (e.g., updated) following a calibration operation triggered by the calibration circuit38, such as previously discussed.

In operation, with reference toFIG.2B, a memory controller240may issue a mode register read command at step260to a semiconductor device204to which the memory controller is coupled to read calibration information from the mode register. At step263, if the read calibration information is set to indicate that the calibration operation is completed and/or new calibration parameters have been determined, at step265the memory controller240may issue a command to apply the calibration parameters to set impedances of the programmable termination components for that semiconductor device. Where calibration parameters are applied without the need to receive a command, the memory controller240does not issue a specific command, step265may be omitted. If the calibration information is not set to indicate such, the memory controller240may check the calibration information at a later time, as represented by step270. Until that later time, the memory controller240may perform other operations, for example, other operations related to power up and initialization.

The operation of checking the calibration information of the semiconductor devices204may be repeated by the memory controllers240until the semiconductor devices204are all calibrated. After all of the semiconductor devices204have calibration information indicating that the calibration operation is completed, and the calibration parameters have been applied, calibration operations for the semiconductor memory200is complete.

FIG.3is a block diagram of an impedance ZQ calibration circuit300according to an embodiment of the disclosure. The calibration circuit300may be used as the ZQ calibration circuit38(FIG.1) in some embodiments. The ZQ calibration circuit300may perform calibration operations without receiving a calibration command, for example, from a memory controller. The calibrations operations occur in the background, and completion or updating with new calibration parameters is indicated by calibration information programmed in a mode register.

The calibration circuit300is coupled to the calibration terminal ZQ27. An external resistance RZQ is coupled between the calibration terminal ZQ27and a power supply. The power supply may provide a voltage, for example, that is equal to the internal voltage Vdd2H. In some embodiments, the internal voltage Vdd2H is a constant voltage, and does not vary based on variations in an externally provided voltage, for example, the externally provided data output voltage VDDQ or the power supply voltage VDD. However, as previously described, in some embodiments of the disclosure, the power supply may provide a voltage that is equal to the VDDQ voltage, or another voltage.

The calibration circuit300includes a ZQ arbitration engine310coupled to the calibration terminal ZQ27and receives a calibration activation signal ZQCAL. As previously discussed, the calibration circuit300performs calibration operations when activated by the calibration signal ZQ_COM. The ZQ arbitration engine310is configured to arbitrate for control over the external resistance RZQ amongst multiple semiconductor devices that are coupled to the same external resistance RZQ. In response to the calibration activation signal ZQCAL, the ZQ arbitration engine310provides a calibration start signal ZQCALSTART to initiate calibration operations when control over the external resistance RZQ is obtained.

In some embodiments, the ZQ arbitration engine310may apply a protocol priority arbitration scheme with other semiconductor devices coupled to a shared external resistance RZQ. In determining whether other semiconductor devices are performing calibration operations using the external resistance RZQ, the ZQ arbitration engine310may monitor a voltage of the calibration terminal ZQ27and compare the voltage to an expected threshold voltage. The arbitration engine310may monitor the voltage of the calibration terminal ZQ27over a time interval associated with the semiconductor device to avoid contention over use of the external resistance RZQ. Each of the semiconductor devices coupled to the external resistance RZQ may have a different time interval.

While examples of arbitration protocols have been described, they are not intended to limit the disclosure to only these examples arbitration protocols. Other arbitration protocols may be used as well without departing from the scope of the present disclosure.

The ZQ calibration engine320is coupled to the arbitration engine310and the calibration terminal ZQ27. The ZQ calibration engine320is configured to perform the calibration operation and provide calibration parameters for setting impedances of programmable termination components. The ZQ calibration engine320performs calibration operations when activated by the calibration start signal ZQCALSTART. The ZQ calibration engine320uses a voltage of the calibration terminal ZQ27for determining the calibration parameters. The calibration parameters may be stored, and the ZQ calibration engine320may apply the calibration parameters to set impedances of the programmable termination components responsive to the ZQLAT signal. The ZQLAT signal is based on a ZQ Latch command received by the semiconductor device. The calibration parameters are provided in the form of an impedance code ZQCODE. The impedance code ZQCODE is provided to the input/output circuit17and applied to set the impedances of programmable termination components included in the input/output circuit17.

The calibration circuit further includes a ZQ calibration controller330. The ZQ calibration controller330receives the calibration signal ZQ_COM and is coupled to the ZQ arbitration engine310. The calibration controller330provides the calibration activation signal ZQCAL to the ZQ arbitration engine310to initiate calibration operations when control over the external resistance RZQ is obtained.

The ZQ calibration controller330may further receive temperature information provided by the temperature sensor44. The temperature information may be represented by the TEMP signal. As will be described in more detail below, the calibration controller330may provide a calibration activation signal ZQCAL to initiate calibration operations based on the temperature information. For example, in some embodiments, the calibration controller330may initiate a calibration operation responsive to a change in temperature exceeding a temperature range. In this manner, accurate calibration parameters may be maintained over changing operating temperature.

The ZQ calibration controller330may initiate calibration operations based on time. The ZQ calibration controller330may receive a clock signal, for example, the internal clock signal LCLK provided by the internal clock generator36ofFIG.1. The ZQ calibration controller330may use the clock signal to time when a calibration activation signal ZQCAL is provided to initiate the calibration operations. For example, the ZQ calibration controller330may provide the calibration activation signal ZQCAL to periodically perform the calibration operations. A time period may be measured according to the clock signal, and the calibration activation signal ZQCAL provided when the time period elapses. In this manner, accurate calibration parameters may be maintained over time.

FIG.4is a flow diagram400of an operation of the calibration circuit300according to an embodiment of the disclosure. A calibration operation is performed at step410to determine the calibration parameters for the programmable termination components30of the I/O circuit17. In the event that the calibration parameters are updated with new calibration parameters (e.g., to change the settings of the programmable termination components30) at step420, information is programmed in the mode register at step430to indicate that the calibration parameters have been updated (e.g., program “1” in the mode register). However, in the event that the calibration parameters are not updated with new calibration parameters (e.g., maintain current settings of the programmable termination components30) at step420, the information in the mode register providing notification/indication of the calibration operation is maintained at step440(e.g., maintain “0” in the mode register).

FIG.5is a flow diagram of a calibration operation500according to an embodiment of the disclosure. The calibration operation500may be performed by a calibration circuit, for example, the calibration circuit38ofFIG.1, the calibration circuit300ofFIG.3, or another calibration circuit in accordance with an embodiment of the disclosure.

In some embodiments, the calibration operation500may be initiated by a calibration circuit as part of a power up operation. In some embodiments, the calibration operation500may be initiated responsive to a calibration command. A calibration command may be provided, for example, by a memory controller to a semiconductor device including a calibration circuit. In some embodiments, the calibration operation500may be initiated by a calibration circuit based on temperature, such as temperature measured by a temperature sensor44ofFIG.1. For example, the calibration circuit may initiate the calibration operation500when the measured temperature exceeds a temperature limit. In another example, the calibration circuit may initiate the calibration operation500when a temperature difference between a current temperature and a previous temperature exceeds a temperature range. In some embodiments, the calibration operation500may be initiated by a calibration circuit based on time. For example, the calibration circuit may initiate the calibration operation500periodically, or after a time period has elapsed. The time period may be measured based on a clock signal.

A calibration circuit may perform step510when a plurality of semiconductor devices are coupled to the same external resistance RZQ. One semiconductor device may use the external resistance RZQ at a time for calibration operations. To avoid more than one semiconductor device using the external resistance RZQ at a time, a ZQ arbitration engine of the calibration circuit may arbitrate usage of the external resistance RZQ by the semiconductor device to avoid conflicts with other semiconductor devices using the external resistance RZQ at the same time.

At step520a decision is made by the calibration circuit whether the semiconductor device has control over the external resistance RZQ to use for the calibration operation. The calibration circuit remains at step520until the semiconductor device has obtained control over the external resistance RZQ to perform the calibration operation. When the semiconductor device has control over the external resistance RZQ, the calibration circuit performs the calibration operation at step530. The steps510and520may be excluded from the calibration operation500in some embodiments. For example, where concurrent usage of the external resistance RZQ by multiple semiconductor devices is avoided by some other technique, the steps510and520may be excluded.

At step530the calibration parameters may be determined by the calibration circuit based on the external resistance RZQ. The calibration parameters may be determined by the ZQ calibration engine. In some embodiments, the ZQ calibration engine determines the calibration parameters by an operation that includes comparing the voltage at the calibration terminal ZQ27to a reference voltage and adjusting programmable termination components until the voltage at the calibration terminal ZQ is equal to the reference voltage ZQVREF. The calibration parameters are then stored by the calibration circuit at step540and an indication of completing the calibration operation is provided by programming information to a mode register at step550. The mode register may be queried through a mode register read operation, for example, by a memory controller. In some embodiments, a calibration latch command may be received by the semiconductor device10to apply any new calibration parameters. In some embodiments, the new calibration parameters may be applied without a calibration latch command. For example, after a change in the frequency set point any new calibration parameters may be applied without receiving a calibration latch command from a memory controller.

FIG.6is a flow diagram of calibration initiation operation600for initiating a calibration operation based on temperature according to an embodiment of the disclosure. The calibration initiation operation600may be performed by a calibration circuit, for example, the calibration circuit38ofFIG.1, the calibration circuit300ofFIG.3, or another calibration circuit in accordance with an embodiment of the disclosure.

At step610, temperature information representing a current temperature may be latched by the calibration circuit. Temperature information may be provided to the calibration circuit by a temperature sensor, for example, temperature sensor44ofFIG.1. As previously described, the temperature sensor senses a temperature of the semiconductor device and provides temperature information. The temperature information may be represented by a signal that is indicative of a temperature of the semiconductor device. For example, in some embodiments the signal represents digital data that may be latched by the calibration circuit. In some embodiments a voltage level of the signal may become higher if the temperature of the semiconductor device becomes higher, and conversely, may become lower if the temperature of the semiconductor device becomes lower. The voltage of the signal may be converted into a digital value that may then be latched by the calibration circuit.

At step620, the current temperature is compared to a previous temperature by the calibration circuit to determine a change in temperature. When the change in temperature exceeds a temperature range, a calibration operation may be initiated. At step630the decision is made whether the change in temperature exceeds the temperature range. If the change in temperature does not exceed the temperature range, new temperature information is latched for comparison at step610. In this way, the change in temperature as measured by the temperature sensor may be monitored by the calibration circuit until the change in temperature exceeds the temperature range. If the change in temperature does exceed the temperature range, a calibration operation is initiated by the calibration circuit at step640. The calibration operation500ofFIG.5may be used by the calibration operation at step640in some embodiments.

The temperature range against which the temperature change is evaluated may be programmable by programming information in a mode register in some embodiments. For example, programming first information to the mode register may program a first temperature range to evaluate the temperature change, whereas programming second information to the mode register may program a second temperature range to evaluate the temperature change.

FIG.7is a block diagram of an impedance ZQ calibration controller700according to an embodiment of the disclosure. The ZQ calibration controller700may be used for the ZQ calibration controller330. The ZQ calibration controller700includes ZQ calibration control logic710that receives the calibration signal ZQ_COM. As previously described, the calibration signal ZQ_COM is used to activate the calibration circuit to perform calibration operations. The ZQ calibration control logic710provides the calibration activation signal ZQCAL to initiate a calibration operation. The calibration activation signal ZQCAL may be provided, for example, to a ZQ arbitration engine to begin arbitration for control of an external resistance RZQ before performing the calibration operation.

The ZQ calibration controller700may further include a temperature comparator720. The temperature comparator720may receive temperature information TEMP and may be compared by the temperature comparator720to determine whether the ZQ calibration control logic710should initiate a calibration operation by providing the calibration activation signal ZQCAL. For example, the temperature information TEMP may be latched and compared by the temperature comparator720to temperature information for a previous temperature to determine whether a change in temperature exceeds a temperature range. Where the change in temperature exceeds the temperature range, the ZQ calibration control logic710provides a calibration activation signal ZQCAL to initiate a calibration operation. In some embodiments, the temperature comparator720compares the temperature information TEMP to temperature limits, and when the temperature limits are exceeded, the ZQ calibration control logic710initiates a calibration operation.

The ZQ calibration controller700may include a timer730. The timer730receives an internal clock signal LCLK. The timer730may be used to cause the ZQ calibration control logic710to provide the calibration activation signal ZQCAL to initiate a calibration operation based on time. The timer730may use the internal clock signal LCLK to time when to initiate calibration operations. For example, the timer730may be used to cause the ZQ calibration control logic710to periodically initiate calibration operations. The timer730may measure a time period according to the internal clock signal LCLK so that the ZQ calibration control logic710provides the calibration activation signal ZQCAL when the time period elapses.

The ZQ calibration controller700may also include a ZQ calibration flag circuit740. The ZQ calibration flag circuit740is configured to program information into a mode register (e.g., mode register125ofFIG.1) to provide an indication related to the calibration operation. In the embodiment ofFIG.7, the calibration information programmed in the mode register is represented by calibration information ZQRDY. The calibration information may be represented by a single bit of data programmed in the mode register. The ZQ calibration flag circuit740is configured to program the calibration information ZQRDY in the mode register having a value that reflects an aspect of the calibration operation. For example, in some embodiments the value of the calibration information ZQRDY programmed in the mode register represents whether the calibration operation is completed. A “0” value may indicate that the calibration operation has not completed and a “1” value may indicate that the calibration operation has completed. In some embodiments the value of the calibration information ZQRDY represents whether any new calibration parameters have been determined by a ZQ calibration engine. A “0” value indicates that a calibration operation did not result in new calibration parameters, and a “1” value may indicate that there are new calibration parameters.

The calibration information programmed in the mode register has been described as a bit of data, that is, calibration information ZQRDY represented by one bit of data. However, in some embodiments, additional bits may be included as part of the information programmed in the mode register. For example, two or more bits may be programmed in the mode register, with each bit providing indication of different aspects of the calibration operation.

The mode register may be read by a mode register read command received by the semiconductor device10. The calibration information ZQRDY will be provided in response to the mode register read, thereby providing the indication of the calibration operation. The mode register read command may be used by a memory controller to query the semiconductor device10regarding the status of a calibration operation. In response to the mode register read command, information programmed in the mode register, including the calibration information ZQRDY, is provided by the semiconductor device10to the memory controller. Upon determining that the calibration information ZQRDY is set (e.g., to indicate that the calibration operation is complete, to indicate new calibration parameters, etc.), the memory controller may provide a ZQ latch command to the semiconductor device to apply the calibration parameters to set impedances of the programmable termination components in some embodiments. The semiconductor device10applies the calibration parameters to set the impedances in response to the ZQ latch command. In some embodiments, the calibration parameters may be applied to set the impedances without receiving a command, for example, the calibration parameters are automatically applied by the semiconductor device following completion of the calibration operations.

The ZQ calibration controller700is illustrated inFIG.7as including the ZQ calibration control logic710, the temperature comparator720, timer730, and ZQ calibration flag circuit740. However, the embodiment illustrated inFIG.7is not intended to limit the configuration of the ZQ calibration controller700. In other embodiments of the invention, one or more of the ZQ calibration control logic710, the temperature comparator720, timer730, and ZQ calibration flag circuit740may be located elsewhere in the semiconductor device and/or implemented using other circuits included in the semiconductor device.

FIG.8is a block diagram of an impedance ZQ calibration engine800according to an embodiment of the disclosure. The ZQ calibration engine800includes calibration engine control logic822that receives a calibration start signal ZQCALSTART to activate the ZQ calibration engine800to perform calibration operations. A comparator824included in the ZQ calibration engine800is coupled to the calibration terminal ZQ27and is further provided the reference voltage ZQVREF. The comparator824compares the voltage at the calibration terminal ZQ27with the reference voltage ZQVREF. The reference voltage ZQVREF may be based on another voltage. For example, in some embodiments, the reference voltage ZQVREF may be based on an externally provided data output voltage VDDQ. In some embodiments, the reference voltage ZQVREF may be based on an internal voltage. For example, the reference voltage ZQVREF may be based on Vdd2H, which as previously described, may be a constant voltage and does not vary based on variations in an externally provided voltage, for example, the externally provided data output voltage VDDQ. Vdd2H may be 1.05 volts in some embodiments. In some embodiments, however, Vdd2H may be 1.1 volts. The reference voltage ZQVREF may be a fraction of Vdd2H. In some embodiments, the reference voltage ZQVREF may be one-fourth of Vdd2H. In some embodiments, the reference voltage ZQVREF may be one-half of Vdd2H. The specific examples for the reference voltage ZQVREF described are not intended to limit the reference voltage ZQVREF to those examples. Other values for the reference voltage ZQVREF may be used as well.

The comparator824provides a signal to a calibration parameter circuit826. The calibration parameter circuit826determines calibration parameters that are used to adjust the impedance of programmable termination components. The calibration parameter circuit826determines the calibration parameters by changing the calibration parameters until comparator824indicates that the voltage at the calibration terminal ZQ27is equal to the reference voltage ZQVREF. When the comparator824indicates the voltages are equal, the calibration parameters are provided to a calibration parameter latch828. The calibration parameter latch828latches the calibration parameters, and the calibration parameters are applied to set impedances of programmable termination components in response to the ZQ latch signal ZQLAT.

The ZQ calibration engine800further includes a calibration parameter storage circuit830. The calibration parameter storage circuit830is configured to store calibration parameters. Calibration parameters for various operating conditions may be stored by the calibration storage circuit830. For example, calibration parameters for multiple frequency set points may be stored after the calibration parameters are determined by the calibration parameter circuit826. The calibration parameters may be kept current by background calibration operations. The current calibration parameters may be stored to update previous calibration parameters. Storing calibration parameters in the calibration storage circuit830may avoid performing a calibration operation when changing operating conditions, for example, changing frequency set points.

FIG.9is a block diagram of programmable termination components900according to an embodiment of the disclosure. The programmable termination components900may be used setting pull-up and pull-down impedances for the programmable termination components30of the I/O circuits17. In some embodiments, the programmable termination components900is a replica of programmable termination components that are used for on-die termination and output buffer impedance. In such embodiments where the programmable termination components900is a replica, the programmable termination components900are used to determine an impedance code ZQCODE, which is then used to set the impedances of the actual programmable termination components used for on-die termination and output buffer impedance.

The programmable termination components900include adjustable pull-up termination components910and adjustable pull-down termination components920. The adjustable pull-up termination components910and adjustable pull-down termination components920are coupled to a node930. The node930may be coupled to the calibration terminal27through switch940. A pull-up impedance of the pull-up termination components910may be adjusted according to pull-up calibration parameters ZQPUP and a pull-down impedance of the pull-down termination components920may be adjusted according to pull-down calibration parameters ZQPDN. The pull-up and pull-down calibration parameters ZQPUP and ZQPDN may be included in the calibration parameters ZQCODE provided by the ZQ calibration engine320.

In some embodiments, the adjustable pull-up termination components910may include a plurality of similar pull-up termination circuits coupled in parallel between the node930and a power supply. Each of the pull-up termination circuits includes a resistor and P-channel devices coupled in parallel with the resistor to reduce the impedance of the pull-up termination circuit to tune the impedance of the resistor. The pull-up calibration code ZQPUP may be provided to the control terminals of the P-channel devices to adjust the impedance of the pull-up termination circuits. The adjustable pull-down termination components920is similar to the adjustable pull-up termination components910. Each of the pull-down termination circuits of the adjustable pull-down termination components920includes multiple N-channel devices coupled in parallel with a resistor, and the impedance of the pull-down termination circuits are adjustable by the pull-down calibration parameters ZQPDN. Other configurations of adjustable pull-up and pull-down termination components may be used in other embodiments of the disclosure, and the example provided is not intended to limit the scope of the disclosure to any particular configuration of adjustable pull-up and pull-down termination components

The pull-up termination components910may be coupled to a power supply (e.g., Vdd2H) through a switch915. The switch915may be used to activate the pull-up termination components910. The pull-down termination components920may be coupled to ground through a switch925. The switch925may be used to activate the pull-down termination components920. The switches915and925may be controlled by the calibration engine control logic822during calibration operations.

A calibration operation according to an embodiment of the disclosure will described below. The calibration operation maybe performed by the ZQ calibration circuit. The calibration operation will be described with reference toFIGS.1-9. It will be appreciated that the following calibration operation is provided by way of example and is not intended to limit the disclosure to the specific calibration operation described. The ZQ calibration engine control logic822is activated by the calibration start signal ZQCALSTART to perform the calibration operation. The calibration operation may include determining calibration parameters to set a pull-down impedance of the programmable termination components and also determining calibration parameters to set a pull-up impedance of the programmable termination components.

When the calibration engine control logic822is activated by the calibration start signal ZQCALSTART, the comparator824compares a voltage at the calibration terminal ZQ27with the reference voltage ZQVREF to determine the calibration parameters to set a pull-down impedance. The voltage at the calibration terminal ZQ27is based on an impedance of programmable termination components set by current calibration parameters and the external resistance RZQ. As previously described, the calibration terminal ZQ27is coupled to an external resistance RZQ. The external resistance RZQ forms a voltage divider circuit with the pull-down impedance of the programmable termination components, and thus, the voltage of the calibration terminal ZQ27is a fraction of the Vdd2H voltage based on the ratio of the impedances of the external resistance RZQ and the pull-down impedance of the programmable termination components. As the pull-down impedance of the programmable termination components increases, the voltage of the calibration terminal ZQ27increases. Conversely, as the pull-down impedance of the programmable termination components decreases the voltage of the calibration terminal ZQ27decreases.

The pull-down impedance of the programmable termination components is adjusted by the calibration parameter circuit826by changing the calibration parameters setting the pull-down impedance until the comparator824indicates that the voltage of the calibration terminal ZQ27is equal to the reference voltage ZQVREF. When the voltage of the calibration terminal ZQ27is equal to the reference voltage ZQVREF, the pull-down impedance of the programmable termination components has been set to the correct pull-down impedance. The calibration parameters provided by the calibration parameter circuit826that set the correct impedance or the pull-down impedance of the programmable termination components are latched by the calibration parameter latch828.

With the correct pull-down impedance of the adjustable pull-down termination components set, the calibration parameters to set the pull-up impedance of the adjustable pull-up termination components may be determined. Instead of the external resistance RZQ being used for the calibration, the calibration terminal ZQ27is coupled through the adjustable pull-down termination components to ground (set with the correct pull-down impedance) and further coupled through the adjustable pull-up termination components to the power supply providing the voltage Vdd2H.

The pull-up impedance of the adjustable pull-up termination components is adjusted by the calibration parameter circuit826by changing the calibration parameters setting the pull-up impedance until the comparator824provides a signal to the calibration parameter circuit826that indicates the voltage of the calibration terminal ZQ27is equal to the reference voltage ZQVREF. When the voltage of a shared node between the pull-up and pull-down termination components (e.g., node930ofFIG.9) is equal to the reference voltage ZQVREF, the pull-up impedance of the adjustable pull-up termination components has been set to the correct pull-up impedance. The calibration parameters provided by the calibration parameter circuit826that set the correct pull-up impedance of the adjustable pull-up termination components are latched by the calibration parameter latch828.

Following the calibration operation, the calibration parameters for the pull-down and pull-up impedances have been determined and the calibration parameters for setting the pull-down and pull-up impedances are applied in response to the ZQ latch signal ZQLAT.

As previously described, the reference voltage ZQVREF may be based on an internal voltage, for example, Vdd2H, or an external voltage, such as VDDQ. The internal voltage Vdd2H may be a constant voltage that does not vary based on variations in the externally provided data output voltage VDDQ. Thus, a calibration operation may not need to be performed if the data output voltage VDDQ is changed, for example, when changing a frequency set point for operation.

In some embodiments, calibration operations for determining the calibration parameters for the pull-up impedance for the programmable termination components may be command based. For example, a command may be received by the semiconductor device for performing calibration operations for the pull-up impedance of the programmable termination components, without performing calibration operations for the pull-down impedance. Calibration operations for the pull-impedance do not require the use of the external resistance RZQ, and consequently, arbitration to obtain control over the external resistance RZQ is not necessary. In this manner, the pull-up impedance of the programmable termination components may be updated when changing a frequency set point for operation, which may involve changing the data output voltage VDDQ. Changing the data output voltage VDDQ may involve changing the pull-up impedance without changing the pull-down impedance.

FIG.10is a timing diagram of a Voh calibration according to an embodiment of the disclosure. Voh represents the voltage of a logical high value for output data signals. The timing diagram ofFIG.10illustrates various signals for changing a frequency set point associated with changing to a higher data output voltage VDDQ.FIG.10illustrates a true clock signal CK_t and a complementary clock signal CK_c, along with command-address signals CA and the command represented by the command-address signals CA.FIG.10further illustrates the data output voltage VDDQ, true and complementary data strobe signals DQS_t and DQS_c, and the data signals DQ[15:0]. In the embodiment ofFIG.10, the data signals DQ[15:0] include 16 signals. However, the data signals for other embodiments may include greater or fewer signals.

Over times T0and T1, a write command is received by the semiconductor device10. Write data is received as data signals DQS[15:0] by the semiconductor device10between times T2and Tb0in response to the data strobe signals DQS_t and DQS_c. Between times T2and Tb0, the semiconductor device is deselected, as indicated by DES for the representation of the command. A data strobe to data time tDQS2DQ is illustrated, as is a write strobe pause time tWPST.

At around time T1, the data output voltage VDDQ begins to increase from a first voltage (e.g., 0.3 volts). Although the data output voltage VDDQ begins to change the write operation of the earlier write command may continue. A change in data output voltage VDDQ indicates that a frequency set point for the semiconductor device will be changed. Typically, the data output voltage VDDQ increases for a change to a higher frequency set point, and conversely, the data output voltage VDDQ decreases for a change to a lower frequency set point. By time Tb0the data output voltage VDDQ has reached a second voltage (e.g., 0.5 volts) that is greater than the first voltage. A calibration command is received at time Tb0to perform a calibration operation, as represented by the MPC train/cal command. A calibration operation may be needed due to the change in data output voltage VDDQ from the first voltage to the higher second voltage. A ZQ calibration time tZQCAL is measured relative to the calibration command. During the ZQ calibration time tZQCAL the calibration process is performed.

Another write command is received by the semiconductor device over times Tc0and Tc1, with write data received between times Td1and Te1responsive to the data strobe signals DQS_t and DQS_c. A write data preamble time tWPRE and data strobe setup time tDQSS are also illustrated. As illustrated byFIG.10, a memory operation, for example, a write operation, may be performed during the ZQ calibration time tZQCAL.

Over times Te2and Te3, mode register write commands are received to cause the frequency set point to change following the end of the ZQ calibration time tZQCAL. In response, the frequency set point for the semiconductor device changes over the frequency change time tFC, and the semiconductor device may be operated according to the new frequency set point following time Tf0. During the frequency change time tFC, the reference voltage Vref may be updated for the new data output voltage VDDQ. In some embodiments, a calibration latch command is needed to be received by the semiconductor device to apply any new calibration parameters to adjust the impedances of the programmable termination components in the input/output circuits17. In other embodiments, any changes to the calibration parameters are applied without receiving a calibration latch command, for example, responsive to frequency set point change, which eliminates the need for the semiconductor device to receive a calibration latch command to apply the calibration parameters.

FIG.11is a timing diagram of a Voh calibration according to an embodiment of the disclosure. The timing diagram ofFIG.11illustrates various signals for changing a frequency set point associated with changing to a lower data output voltage VDDQ.FIG.11illustrates a true clock signal CK_t and a complementary clock signal CK_c, along with command-address signals CA and the command represented by the command-address signals CA.FIG.11further illustrates the data output voltage VDDQ, true and complementary data strobe signals DQS_t and DQS_c, and the data signals DQ[15:0]. In the embodiment ofFIG.11, the data signals DQ[ 15:0] include 16 signals. However, the data signals for other embodiments may include greater or fewer signals.

Over times T0and T1, a write command is received by the semiconductor device10. Write data is received as data signals DQS[15:0] by the semiconductor device10between times T2and Tb0in response to the data strobe signals DQS_t and DQS_c. Between times T2and Tb0, the semiconductor device is deselected, as indicated by DES for the representation of the command. A data strobe to data time tDQS2DQ is illustrated, as is a write strobe pause time tWPST.

Over times Tb0and Tb1, mode register write commands are received to cause the frequency set point to change. In response, the frequency set point for the semiconductor device changes over the frequency change time tFC. During the frequency change time tFC, the reference voltage Vref may be updated for the new data output voltage VDDQ. The semiconductor device may be operated according to the new frequency set point following time Tc0.

At around time Tc0, the data output voltage VDDQ begins to decrease from the first voltage. As previously discussed, a change in data output voltage VDDQ indicates that a frequency set point for the semiconductor device will be changed. Decreasing the data output voltage VDDQ typically signals a change to a lower frequency set point. By time Td0the data output voltage VDDQ has reached the lower second voltage.

A calibration command is received at time Td1to perform a calibration operation, as represented by the MPC train/cal command. A calibration operation may be needed due to the change in data output voltage VDDQ from a first voltage (e.g., 0.5 volts) to a lower voltage (e.g., 0.3 volts). A ZQ calibration time tZQCAL is measured relative to the calibration command. During the ZQ calibration time tZQCAL the calibration process is performed.

At time Tc1a ZQ calibration latch command is received by the semiconductor device to apply any new calibration parameters to adjust the impedances of the programmable termination components in the input/output circuits17. In other embodiments, any changes to the calibration parameters are applied responsive to frequency set point change, which eliminates the need for the semiconductor device to receive a calibration latch command to apply the calibration parameters.

From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.