Patent ID: 12189991

DETAILED DESCRIPTION

The invention aims at providing a technical solution and a storage device controller capable of arranging or rearranging a host device's write command signals that are out of sequence (not in order) to meet the requirement of the NVMe (NVM Express) zoned namespaces (ZNS) interface wherein NVM stands for Non-Volatile Memory. A namespace is a collection of logical block addresses (LBAs) accessible to the software of the host device. An NVMe namespace is divided into a plurality of zones which may be required to be sequentially written, and the logical block addresses of the same zone may be also required to be sequentially written. The provided storage device controller is to be coupled between the host device and one or more storage devices such as flash memory-based SSDs (solid-state drives/disks), and it can arrange or rearrange the host device's write command signals that are out of sequence to meet the sequential write requirements of the zoned namespace(s).

FIG.1is a block diagram of a storage device controller100according to an embodiment of the invention. The storage device controller100is a multi-core flash memory processor (but not limited) which at least comprises multiple processor cores C0, C1, CN-1, and CN, and a specific interface circuit105such as an NVM Express (NVMe) hardware circuit, wherein the NVMe hardware circuit105supports NVMe protocol communication between a host device101and the storage device controller100; the number N is not intended to be a limitation. The storage device controller100is externally coupled to the host device101such as a personal computer device or a server device and externally coupled to one or more storage devices such as flash memory-based SSDs (not shown inFIG.1).

A processor core such as CNamong the multiple cores C0, C1, CN-1, and CNis dedicated and selected as an administrator core (or referred to as a manager core for all storage zones (which can be called as zones or open zones)) which has a manager thread such as a host-based flash translation layer (abbreviated as HBFTL in the following paragraphs) thread and is arranged to execute such HBFTL thread wherein a thread is an execution thread which can be executed by a processor or a processor core to perform a specific operation/function. The other processor cores C0, and CN-1are regarded as worker cores, and each worker core has a first thread such as a fetch command thread TF and a second thread such as a data move thread TD.

The host device101may comprise a host driver1010which may have multiple I/O queues Q0, Q1. . . and QMwhich are respectively coupled to the NVMe hardware circuit105through the NVMe interface protocol. The number M can be identical to or different from the number N. Each of the I/O queues Q0, Q1, . . . , and QMcan be used to store information of a single write command signal which may carry the write command, one set of corresponding write address information, and corresponding data unit(s) to be written, wherein the corresponding write address information may comprise a start logical block address (abbreviated as SLBA) and a data length of the corresponding data unit(s) such as a number of logical block address(es) (abbreviated as NLBA). Further, the queue depth of each I/O queues Q0, Q1, . . . , and QMmay be equal to one (but not limited); that is, each I/O queue can merely store one single set of write address information. In this embodiment, the queue depth of each I/O queues Q0, Q1, and QMcan be configured to be larger than one since the storage device controller100can allow the out-of-sequence write command signals.

When the host device101issues multiple write command signals to write different data units into consecutive storage spaces of the same open zone or different open zones, the storage device controller100can allow that the write address information of the write command signals are out of order (or out of sequence). The host device101for example may issue and transmit the different write command signals into at least one portion of the different I/O queues Q0, Q1, . . . , and QM, and the I/O queues Q0, Q1, . . . , and QMmay sequentially or randomly output the different write address information of the write command signals into the NVMe hardware circuit105; in the embodiments, for example (but not limited), the SLBA information of the write command signals received by the storage device controller100may be out of sequence, and the storage device controller100can still correctly service the write command signals to meet the sequential write requirements of the zoned namespace(s).

The different corresponding write address information of the different write command signals, stored in the I/O queues, are respectively transmitted from the I/O queues to the NVMe hardware circuit105, and the transmissions may be sequential or may be out of order. That is, the NVMe hardware circuit105may simultaneously buffer one or more sets of write address information of write command signals.

When a worker core such as C0is idle, the worker core C0is arranged to execute its first thread, i.e. the fetch command thread TF, to fetch one set of write command information of one write command signal from the NVMe hardware circuit105, and then is arranged to transmit the set of write command information to the manager core CN. Similarly, when multiple or all worker cores C0, C1, . . . , CN-1are idle, a portion of worker cores C0, C1, . . . , CN-1respectively execute their fetch command threads TF to respectively fetch different sets of write address information of write command signals from the NVMe hardware circuit105. Then, the worker cores respectively transmit their fetched different write address information to the manager core CN.

The manager core CNis used to arrange or rearrange the order of write command signals if the different write address information of the received write command signals are out of order; the manager core CNdoes not rearrange the order of the write command signals if the different write address information of the write command signals are not out of order. Then, the manager core CNis used to sequentially transmit the rearranged different write address information respectively to the idle worker cores.

For example, for a worker core such as C0, the worker core C0is arranged to execute its second thread, i.e. a data move thread TD, to move and write corresponding data based on a rearranged write address information into a storage space specified by the rearranged write address information. That is, for the worker core C0, the write address information fetched by its first thread may be different from that assigned by the manager core CNand received by its second thread. Alternatively, in one example, for another different worker core such as C1, the write address information fetched by its first thread may be identical to that received by its second thread and assigned by the manager core CN.

FIG.2is a block diagram of the storage device controller100according to another embodiment of the invention. In this embodiment, the storage device controller100can support a different example of the host device101which may comprise a single I/O queue1011which can store multiple sets of different write address information. The operations and functions of the storage device controller100are identical to those of the storage device controller100inFIG.1and are not detailed for brevity.

FIG.3is a diagram showing an example of the operations of the storage device controller100inFIG.1according to an embodiment of the invention. InFIG.3, for example (but not limited), four consecutive write command signals may be sequentially transmitted from the host device101into the NVMe hardware circuit105inFIG.1, and the different write address information, received by the storage device controller100, may be not out of order. A hardware memory1051within the NVMe hardware circuit105may store the four write command signals W1, W2, W3, and W4which carry four sets of different write address information, e.g. SLBA and NLBA information, which may be not out of order.

For example (but not limited), the worker core C0executes its fetch command thread TF to fetch the write address information (e.g. SLBA=A and NLBA=K) of the write command signal W1from the NVMe hardware circuit105, wherein SLBA=A means that the start logical block address is equal to A and NLBA=K means that the number of logical block addresses is equal to K; that is, the end logical block address of the write command signal W1is equal to or calculated as (A+K). Then, the worker core C0executes its fetch command thread TF to transfer the write address information (e.g. SLBA=A and NLBA=K) of the write command signal W1into the HBFTL thread of the manager core CN. It should be noted that, in one example, during a data write operation/procedure associated with multiple write command signals, if an operation of a write command signal has been completed or finished, then the HBFTL thread of the manager core CNmay record an end logical block address of the write command signal at its zone write pointer. In addition, the write command signal W1is a first command signal received by the HBFTL thread of the manager core CN, and the HBFTL thread is arranged to establish a link list and record the write address information (e.g. SLBA=A and NLBA=K) of write command signal W1at a first node of the link list.

Then, similarly, the worker core C1may execute its fetch command thread TF to fetch the write address information (e.g. SLBA=A+K+M and NLBA=N) of the write command signal W2from the NVMe hardware circuit105, wherein SLBA=A+K+M means that the start logical block address is equal to (A+K+M) and NLBA=N means that the number of logical block addresses is equal to N; that is, the end logical block address of the write command signal W2is equal to or calculated as (A+K+M+N). Also, the worker core C1executes its fetch command thread TF to transfer the write address information (e.g. SLBA=A+K+M and NLBA=N) of the write command signal W2into the HBFTL thread of the manager core CN.

After receiving the write address information (e.g. SLBA=A+K+M and NLBA=N) of the write command signal W2, the HBFTL thread of the manager core CNis arranged to compare the SLBA of the last node of the link list, i.e. the SLBA (i.e. A) of first write command signal W1, with the SLBA (i.e. A+K+M) of write command signal W2to determine how to update the link list. In this example, the SLBA (i.e. A+K+M) of write command signal W2is larger than the SLBA (i.e. A) of write command signal W1, and the HBFTL thread is arranged to record the information of the second write command W2at a second node of the link list, wherein the second node is a next node following the first node. Similarly, during the data write operation/procedure associated with multiple write command signals, if an operation of the write command signal W1has been completed or finished, then the HBFTL thread of the manager core CNmay record an end logical block address A of the write command signal W1at its zone write pointer. In this situation, the HBFTL thread of the manager core CNmay compare the information of the zone write pointer with the SLBA of second write command signal W2to determine whether to load data from the host device101to the storage device controller100by using a direct memory access (DMA) operation. For example (but not limited), when the information of the zone write pointer is equal to the SLBA of one write command, the DMA operation may be executed to load data. In this example, since the information of the zone write pointer is not equal to the SLBA (i.e. A+K+M) of the write command signal W2, the DMA operation is not performed.

Then, similarly, the worker core CN-1may execute its fetch command thread TF to fetch the write address information (e.g. SLBA=A+K+M+N and NLBA=L) of the write command signal W3from the NVMe hardware circuit105, wherein SLBA=A+K+M+N means that the start logical block address is equal to (A+K+M+N) and NLBA=L means that the number of logical block addresses is equal to L; that is, the end logical block address of the write command signal W3is equal to or calculated as (A+K+M+N+L). Also, the worker core CN-1executes its fetch command thread TF to transfer the write address information (e.g. SLBA=A+K+M+N and NLBA=L) of the write command signal W3into the HBFTL thread of the manager core CN.

After receiving the write address information (e.g. SLBA=A+K+M+N and NLBA=L), the HBFTL thread of the manager core CNis arranged to compare the SLBA of the last node of the link list, i.e. the SLBA (A+K+M) of the second write command signal W2with the SLBA (i.e. A+K+M+N) of write command signal W3to determine how to generate or update the link list. In this example, the SLBA (i.e. A+K+M+N) of write command signal W3is larger than the SLBA (i.e. A+K+M) of write command signal W2, and the HBFTL thread is arranged to record the information of the third write command signal W3at the link list's third node which follows the information of the second write command W2at the second node of the link list, wherein the third node is now the last node in the link list.

Similarly, during the data write operation/procedure associated with multiple write command signals, if an operation of the write command signal W2has been completed or finished, then the HBFTL thread of the manager core CNmay record an end logical block address (A+K+M+N) of the write command signal W2at its zone write pointer. In this situation, the HBFTL thread may compare the information of the zone write pointer with the SLBA of third write command signal W3to determine whether to load data from the host device101to the storage device controller100by using the DMA operation. For example (but not limited), if the information of the zone write pointer is equal to the SLBA of the third write command signal W3, the DMA operation can be executed to load data. If the information of the zone write pointer is not equal to the SLBA of the write command signal W3, the DMA operation is not performed.

Then, similarly, the worker core C1(but not limited) may execute its fetch command thread TF to fetch the write address information (e.g. SLBA=A+K and NLBA=M) of the write command signal W4from the NVMe hardware circuit105, wherein SLBA=A+K means that the start logical block address is equal to (A+K) and NLBA=M means that the number of logical block addresses is equal to M; that is, the end logical block address of the write command signal W4is equal to or calculated as (A+K+M). Also, the worker core C1executes its fetch command thread TF to transfer the write address information (e.g. SLBA=A+K and NLBA=M) of the write command signal W4into the HBFTL thread of the manager core CN.

After receiving the write address information (e.g. SLBA=A+K and NLBA=M), the HBFTL thread of the manager core CNis arranged to compare the SLBA of the last node of the link list, i.e. the SLBA (A+K+M+N) of the third write command signal W3, with the SLBA (i.e. A+K) of write command signal W4to determine how to update the link list. In this example, the SLBA (i.e. A+K) of write command signal W4is smaller than the SLBA (i.e. A+K+M+N) of the last node of the link list, and the HBFTL thread is arranged to insert a new node between two nodes of the link list. For example (but not limited), the HBFTL thread inserts a new node between the node of write command signal W1and the node of write command signal W2to rearrange the order of the link list, wherein the new node records the write address information of write command signal W4, i.e. the information of SLBA=A+K and NLBA=M. Thus, the updated link list comprises four nodes in which a first node recording the address information of write command signal W1is followed by a second node recording the address information of write command signal W4which is followed by a third node recording the address information of write command W2which is followed by a fourth node (i.e. the last node) recording the address information of write command W3.

Further, similarly, during the data write operation/procedure associated with multiple write command signals, if an operation of one write command signal has been completed or finished, then the HBFTL thread of the manager core CNmay record an end logical block address of the write command signal at its zone write pointer. In this situation, the HBFTL thread may compare the information of the zone write pointer with the SLBA of third write command signal W4to determine whether to load data from the host device101to the storage device controller100by using the DMA operation. For example (but not limited), if the information of the zone write pointer is equal to the SLBA of the third write command signal W4, the DMA operation can be executed to load data. If the information of the zone write pointer is not equal to the SLBA of the write command signal W4, the DMA operation is not performed.

Then, the manager core CNexecute its HBFTL thread to sequentially assign and transmit the write address information recorded at the different nodes of the link list to idle worker core (s) of the different worker cores in order. For example, the executed HBFTL thread is arranged for assigning and transmitting the information of SLBA and NLBA of the write command signal W1at the first node of the link list to the data move thread TD of the worker core C0, and the worker core C0executes its data move thread TD to move and write the data units to be written by the write command signal W1from the host device101into the storage block (s) of one or more SSDs, specified by the SLBA and NLBA of the write command signal W1. In this example, the fetch command thread TF and data move thread TD of the worker core C0process or service the same write command signal W1.

When the operation of write command signal W1is finished or is ready to be finished, the HBFTL thread of manager core CNis arranged for assigning and transmitting the information of SLBA and NLBA of the write command signal W4at the second node of the link list to the data move thread TD of the worker core C1, and the worker core C1executes its data move thread TD to move and write the data units to be written by the write command signal W4from the host device101into the different storage block(s) of one or more SSDs, specified by the SLBA and NLBA of the write command signal W4. In this example, the fetch command thread TF of the worker core C1services the write command signal W2, and the data move thread TD of the worker core C1services the write command signal W4different from the write command signal W2.

Then, when the operation of write command signal W4is or is to be finished, the HBFTL thread of manager core CNis arranged for assigning and transmitting the information of SLBA and NLBA of the write command signal W2at the third node of the link list to the data move thread TD of the worker core CN-1, and the worker core CN-1executes its data move thread TD to move and write the data units to be written by the write command signal W2from the host device101into the different storage block (s) of one or more SSDs, specified by the SLBA and NLBA of the write command signal W2. In this example, the fetch command thread TF of the worker core CN-1services the write command signal W3, and the data move thread TD of the worker core CN-1services the write command signal W2different from the write command signal W3.

Then, when the operation of write command signal W2is finished, the HBFTL thread of manager core CNis arranged for assigning and transmitting the information of SLBA and NLBA of the write command signal W3at the last node of the link list to the data move thread TD of an idle worker core such as C0, C1, or CN-1, and for example the worker core C1(but not limited) is idle while the worker core C0and CN-1are busy, and the worker core C1may execute its data move thread TD to move and write the data units to be written by the write command signal W3from the host device101into the different storage block(s) of one or more SSDs, specified by the SLBA and NLBA of the write command signal W3.

It should be noted that, in one embodiment, based on the generated link list, the HBFTL thread of the manager core CNcan correspondingly and sequentially assign and transmit the address information recorded at the different nodes of the link list to a single one idle worker core, multiple different idle worker cores, or different idle worker core(s) which are different from the worker cores C0, C1, and CN-1. Further, in one embodiment, the idle worker cores, selected by the manager core CN, may be out of order while the operation of sequentially assign and transmit the information recorded at the different nodes of the link list is in order. Further, a worker core after executing the fetch command thread TF to service a write command signal may be arranged to execute other threads to service other operations or requests and thus become busy, and a different idle worker core is assigned by the manager core CNto execute the data move thread TD to service such write command signal. By doing so, even the address information of the sequentially received write command signals are out of sequence, the storage device controller100can still meet the sequential write requirements of the zoned namespace(s).

FIG.4is a diagram showing a flow of the operations of the manager core CNexecuting its HBFTL thread inFIG.1according to an embodiment of the invention. Provided that substantially the same result is achieved, the steps of the flowchart shown inFIG.4need not be in the exact order shown and need not be contiguous, that is, other steps can be intermediate. Steps are detailed in the following:

Step S400: Start;

Step S405: HBFTL thread receives the information of SLBA and NLBA of a write command signal;

Step S410: HBFTL thread compares the information of the SLBA and NLBA of the write command signal with the information of a zone write pointer to determine whether to execute a DMA operation; if the information is matched or equal, the flow proceeds Step S415, otherwise, the flow proceeds Step S420;

Step S415: a direct memory access (DMA) operation is triggered and executed to load data;

Step S420: HBFTL thread compares the SLBA of the write command signal with the SLBA information at the last node of the link list; if the SLBA of the write command signal is larger than the SLBA information at the last node of the link list, the flow proceeds Step S425, otherwise, the flow proceeds Step S430;

Step S425: HBFTL thread adds a new node as a last node of the link list to record the address information of the received write command signal at the new node (i.e. the last node of the updated link list);

Step S430: HBFTL thread inserts a new node between two nodes of the link list to update the link list to record the address information of the received write command signal at the inserted node (i.e. it is not the last node of the updated link list); and

Step S435: End.

Further, in another embodiment, in addition to the operations in the embodiments ofFIG.1orFIG.2, the HBFTL thread of the manager core CNmay further assign or configure different worker cores as manager cores respectively dedicated for different open zones, and the loading of the processor core CNcan be shared by the other processor cores which are originally used as worker cores. That is, the capability of the manager core CNcan be shared into the different worker cores. The write operations in the different open zones can be isolated and individual, and the response time can be shorter.

FIG.5is a block diagram of a storage device controller500according to another embodiment of the invention. The storage device controller500is a multi-core flash memory processor (but not limited) which at least comprises multiple processor cores C0, C1, . . . , CN-1, and CN, and a specific interface circuit105such as an NVM Express (NVMe) hardware circuit wherein the NVMe hardware circuit105supports NVMe protocol communication between the host device101(not shown inFIG.5) and the storage device controller500; the number N is not intended to be a limitation. The storage device controller500is externally coupled to the host device101such as a personal computer device or a server device and externally coupled to one or more storage devices such as flash memory-based SSDs (not shown inFIG.1). A processor core such as CNamong the multiple cores C0, C1, . . . , CN-1, and CNis selected as an administrator core (or referred to as a manager core) which has a manager thread TM such as a first host-based flash translation layer (abbreviated as HBFTL) thread and is arranged to execute the first HBFTL thread. The other processor cores C0, C1, . . . f CN-1are regarded as worker cores, and each worker core has a first thread such as a fetch command thread TF and a second thread such as a data move thread TD. If a worker core is configured as a manager core for a specific open zone, the worker core further includes a second HBFTL thread which can be partially or fully copied and transmitted from the manager core CNinto such worker core. The second HBFTL thread is assigned by the first HBFTL thread of the manager core CNto service or process data/operations of the specific open zone. Then, the first HBFTL thread running on the manager core CNis arranged to notify all the other worker cores of such worker core has been configured as a manager core of the specific open zone.

For example (but not limited), inFIG.5, the manager core CNmay assign the worker core C0as a manager core of the open zone X and transmit a copy of the first HBFTL thread to the worker core C0as the second HBFTL thread for the open zone X, assign the worker core C1as a manager core of the open zone Y and transmit a copy of the first HBFTL thread to the worker core C1as the second HBFTL thread for the open zone Y, and assign the worker core CN-1as a manager core of the open zone Z and transmit a copy of the first HBFTL thread to the worker core CN-1as the second HBFTL thread for the open zone Z; the other different worker cores may not be assigned as manager cores, and a copy of the first HBFTL thread are not transmitted to the other different worker cores. The manager core CNis arranged to notify all processor cores of the information which worker core(s) is/are assigned as manager core(s) dedicated for the open zone(s).

In this example inFIG.5(but not limited), initially the processor core C0is an idle worker core and is not yet configured used as the manager core of the open zone X. The worker core C0may executes its fetch command thread TF to fetch the write address information of one write command signal from the NVMe hardware circuit105wherein the write address information indicates SLBA information in the open zone Y, and then it transmits the write address information to the manager thread TM (i.e. the first HBFTL thread) of the manager core CN. The manager core CNaccordingly determines or configures the processor core C0as the manager core dedicated for the open zone X, and then a copy of the first HBFTL thread is transmitted from the manager core CNto the processor core C0and is used as the second HBFTL thread of the processor core C0. Similarly, based on the same operations, the manager core CNcan respectively determine or configure the processor core C1as the manager core dedicated for the open zone Y and the processor core CN-1as the manager core dedicated for the open zone Z. A copy of the first HBFTL thread is respectively transmitted from the manager core CNto the processor core C1and to the processor core CN-1.

FIG.6is a diagram of a scenario example of the operations of the processor cores in the embodiment ofFIG.5according to an embodiment of the invention. InFIG.6, the processor core C0has been configured as the manager core of the open zone X, and a copy of the manger thread in the manager core CNis transmitted to and stored in the processor core C0. The processor core C1has been configured as the manager core of the open zone Y, and a copy of the manger thread in the manager core CNis transmitted to and stored in the processor core C1. The processor core CN-1has been configured as the manager core of the open zone Z, and a copy of the manger thread in the manager core CNis transmitted to and stored in the processor core CN-1.

In this example, for example (but not limited), the processor core C0executes its fetch command thread TF to fetch the SLBA and NLBA information of a write command signal associated with the open zone Y, and it is arranged to transmit the SLBA and NLBA information of the write command signal into the HBFTL thread of the processor core C1without transmit the SLBA and NLBA information to the manager core CN. Then the processor core C1, which is used as the manager core of the open zone Y, is arranged to generate or update a corresponding link list of the open zone Y, and then it transmits the SLBA and NLBA information of the write command signal for the open zone Y back to the data move thread TD of the processor core C0, which is arranged to execute its data move thread TD to perform a data writing operation to load and write data of the write command signal for the open zone Y into a corresponding storage space belonging to the open zone Y.

Alternatively, the processor core C1executes its fetch command thread TF to fetch the SLBA and NLBA information of another write command signal associated with the open zone Z, and it is arranged to transmit the SLBA and NLBA information of the write command signal into the HBFTL thread of the processor core CN-1without transmit the SLBA and NLBA information to the manager core CN. Then the processor core CN-1, which is used as the manager core dedicated for the open zone Z, is arranged to generate or update a corresponding link list of the open zone Z, and then it transmits the SLBA and NLBA information of the write command signal to the data move thread TD of the processor core C1, which executes its data move thread TD to load and write data of the write command into a corresponding storage space belonging to the open zone Z.

By doing so, in this example, the manager thread TM in the manager core CNis not triggered and executed to update link lists of open zones Y and Z. The loading of processor core CNcan be alleviated.

FIG.7is a flowchart diagram of the operations of the storage device controller500executing the HBFTL thread of the manager core CNaccording to another embodiment of the invention. Provided that substantially the same result is achieved, the steps of the flowchart shown inFIG.7need not be in the exact order shown and need not be contiguous, that is, other steps can be intermediate. Steps are detailed in the following:Step S700: Start;Step S705: HBFTL thread of the manager core CNreceives the information of SLBA and NLBA of a write command signal associated with a specific open zone;Step S710: HBFTL thread of the manager core CNdetermines whether a specific processor core among the other processor core(s) C0-CN-1has already handled a command of the specific open zone; if a processor has already handled the specific open zone, the flow proceeds Step S715, otherwise, the flow proceeds Step S720A;Step S715: HBFTL thread of the manager core CNassigns or configures the specific processor core as a manager core dedicated for the specific open zone, creates and transmits a copy of the HBFTL thread of the manager core CNinto the specific processor core, and notifies all the other different processor cores of the specific processor core being set as the manager core of the specific open zone;Step S716: HBFTL thread of the specific processor core, different from the manager core CN, receives the information of SLBA and NLBA of the write command signal associated with the specific open zone;Step S720A: HBFTL thread of the manager core CNcompares the information of the SLBA and NLBA of the write command signal with the information of a zone write pointer of the specific open zone to determine whether to execute a DMA operation; if the information is matched or equal, the flow proceeds Step S725A, otherwise, the flow proceeds Step S730A;

Step S725A: a direct memory access (DMA) operation is triggered and executed to load data;Step S730A: HBFTL thread of the manager core CNcompares the SLBA of the write command signal with the SLBA information at the last node of the link list; if the SLBA of the write command signal is larger than the SLBA information at the last node of the link list, the flow proceeds Step S735A, otherwise, the flow proceeds Step S740A;Step S735A: HBFTL thread of the manager core CNadds a new node as a last node of the link list to record the address information of the received write command signal at the new node (i.e. the last node of the updated link list);Step S740A: HBFTL thread of the manager core CNinserts a new node between two nodes of the link list to update the link list to record the address information of the received write command signal at the inserted node (i.e. it is not the last node of the updated link list);Step S720B: HBFTL thread of the specific processor core compares the information of the SLBA and NLBA of the write command signal with the information of a zone write pointer of the specific open zone to determine whether to execute a DMA operation; if the information is matched or equal, the flow proceeds Step S725B, otherwise, the flow proceeds Step S730B;

Step S725B: a direct memory access (DMA) operation is triggered and executed to load data;Step S730B: HBFTL thread of the specific processor core compares the SLBA of the write command signal with the SLBA information at the last node of the link list; if the SLBA of the write command signal is larger than the SLBA information at the last node of the link list, the flow proceeds Step S735B, otherwise, the flow proceeds Step S740B;Step S735B: HBFTL thread of the specific processor core adds a new node as a last node of the link list to record the address information of the received write command signal at the new node (i.e. the last node of the updated link list);Step S740B: HBFTL thread of the specific processor core inserts a new node between two nodes of the link list to update the link list to record the address information of the received write command signal at the inserted node (i.e. it is not the last node of the updated link list); andStep S745: End.

FIG.8is a flowchart diagram of the operations of the specific processor core in the embodiment ofFIG.7according to another different embodiment of the invention. Provided that substantially the same result is achieved, the steps of the flowchart shown inFIG.8need not be in the exact order shown and need not be contiguous, that is, other steps can be intermediate. Steps are detailed in the following:Step S800: Start;Step S805: HBFTL thread of the specific processor core, which has been configured as a manager core dedicated for a specific open zone, receives the information of SLBA and NLBA of a write command signal;Step S810: HBFTL thread of the specific processor core determines whether the SLBA of the write command signal is in the specific open zone; if the SLBA of the write command signal is in the specific open zone, the flow proceeds Step S820A, otherwise, the flow proceeds Step S815;Step S815: HBFTL thread of the specific processor core transmits the SLBA and NLBA information of the write command signal into another processor core which is assigned as a manager core of an open zone in which the SLBA of the write command signal is located;Step S816: HBFTL thread of the another processor core, different from the specific processor core and manager core CN, receives the information of SLBA and NLBA of the write command signal;Step S820A: HBFTL thread of the specific processor core compares the information of the SLBA and NLBA of the write command signal with the information of a zone write pointer of the specific open zone to determine whether to execute a DMA operation; if the information is matched or equal, the flow proceeds Step S825A, otherwise, the flow proceeds Step S830A;

Step S825A: a direct memory access (DMA) operation is triggered and executed to load data;Step S830A: HBFTL thread of the specific processor core compares the SLBA of the write command signal with the SLBA information at the last node of the link list; if the SLBA of the write command signal is larger than the SLBA information at the last node of the link list, the flow proceeds Step S835A, otherwise, the flow proceeds Step S840A;Step S835A: HBFTL thread of the specific processor core adds a new node as a last node of the link list to record the address information of the received write command signal at the new node (i.e. the last node of the updated link list);Step S840A: HBFTL thread of the specific processor core inserts a new node between two nodes of the link list to update the link list to record the address information of the received write command signal at the inserted node (i.e. it is not the last node of the updated link list);Step S820B: HBFTL thread of the another processor core compares the information of the SLBA and NLBA of the write command signal with the information of a zone write pointer of another open zone to determine whether to execute a DMA operation; if the information is matched or equal, the flow proceeds Step S825B, otherwise, the flow proceeds Step S830B;

Step S825B: a direct memory access (DMA) operation is triggered and executed to load data;Step S830B: HBFTL thread of the another processor core compares the SLBA of the write command signal with the SLBA information at the last node of the link list; if the SLBA of the write command signal is larger than the SLBA information at the last node of the link list, the flow proceeds Step S835B, otherwise, the flow proceeds Step S840B;Step S835B: HBFTL thread of the another processor core adds a new node as a last node of the link list to record the address information of the received write command signal at the new node (i.e. the last node of the updated link list);Step S840B: HBFTL thread of the another processor core inserts a new node between two nodes of the link list to update the link list to record the address information of the received write command signal at the inserted node (i.e. it is not the last node of the updated link list); andStep S845: End.

In other embodiments, for the different open zones, multiple idle processor cores may simultaneously execute their data move thread to load and move data units into different storage spaces specified by different write command signals respectively belonging to the different open zones.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.