Patent ID: 12218121

DETAILED DESCRIPTION OF THE EMBODIMENTS

Although terms such as first and second are used herein to describe various elements or components, it goes without saying that these elements or components are not limited to such terms. These terms are used to merely distinguish a single element or component from other elements or components. Therefore, it goes without saying that the first element or component described below may be a second element or component within the technical idea of the present inventive concept.

Hereinafter, a semiconductor device according to some embodiments will be described referring toFIGS.1to23.FIG.1is a layout diagram for explaining the semiconductor device according to some embodiments. Referring toFIG.1, the semiconductor device according to some embodiments includes a first cell region CR1.

A standard cell provided by a cell library may be provided inside the first cell region CR1. InFIG.1, the standard cell provided in the first cell region CR1is a 2-input AND (AND2) cell, which may be configured from six (6) transistors (3 NMOS, 3 PMOS). However, this is only an example, and it goes without saying that the standard cell provided in the first cell region CR1may be diverse, for example, a NAND cell, a NOR cell, and an XOR cells.

In some embodiments, the first cell region CR1may be defined by a first cell separation pattern I1aand a second cell separation pattern I1bspaced apart along a first direction X. For example, the first cell separation pattern I1aand the second cell separation pattern I1bmay extend side by side (and lengthwise) in a second direction Y which intersects the first direction X. The first cell region CR1may be defined between the first cell separation pattern I1aand the second cell separation pattern I1b.

The semiconductor device according to some embodiments provided in the first cell region CR1may include a first active region AR1, a second active region AR2, first to third gate electrodes G1to G3, a plurality of source/drain contacts CA11to CA17, a plurality of first contact vias VA11to VA17, a plurality of gate contacts CB11to CB13, a first power supply wiring VDD, a second power supply wiring VSS, a plurality of first routing wirings IW11, IW12, CW11, CW12, and OW1, and a second routing wiring DW1.

The first active region AR1and the second active region AR2may be spaced apart from each other and extend side by side. For example, the first active region AR1and the second active region AR2may each extend lengthwise in the first direction X. The second active region AR2may be spaced apart from the first active region AR1in the second direction Y.

In some embodiments, semiconductor elements of different conductivity types (e.g., transistors) may be formed on the first active region AR1and the second active region AR2. Hereinafter, it will be described that the first active region AR1is a PFET region and the second active region AR2is an NFET region. However, this is only an example, and it goes without saying that the first active region AR1may be the NFET region and the second active region AR2may be the PFET region.

The first to third gate electrodes G1to G3may be interposed between the first cell separation pattern I1aand the second cell separation pattern I1b. The first to third gate electrodes G1to G3may each intersect (i.e., extend over) the first active region AR1and the second active region AR2. For example, the first to third gate electrodes G1to G3may be spaced apart from each other in the first direction X and extend lengthwise in the second direction Y, as shown.

The first to third gate electrodes G1to G3may be adjacent to each other and arranged sequentially along the first direction X. That is, no other gate electrode or other cell separation pattern may be placed between the first to third gate electrodes G1to G3. As used herein, adjacent gate electrodes may be referred to as being spaced apart from each other by one gate pitch GP. As an example, as shown, the single gate pitch GP may be defined as a spaced distance between one side of the first gate electrode G1and one side of the second gate electrode G2, or possibly as a center-to-center “integrate” spacing for side-by-side gate electrodes having the same width. The one gate pitch GP may be, but is not limited to, for example, 30 nm to 60 nm. As an example, the one gate pitch GP may be 50 nm to 60 nm. As another example, the one gate pitch GP may be 40 nm to 50 nm. As another example, the one gate pitch GP may be 30 nm to 40 nm.

In some embodiments, each of the first cell separation pattern I1aand the second cell separation pattern I1bmay be spaced apart from adjacent gate electrodes by one gate pitch GP. As an example, the first gate electrode G1and the first cell separation pattern I1amay be spaced apart from each other by the one gate pitch GP, and the third gate electrode G3and the second cell separation patterns I1bmay be spaced apart from each other by one gate pitch GP.

A plurality of source/drain contacts CA11to CA17may be placed on both sides of the first to third gate electrodes G1to G3. The plurality of source/drain contacts CA11to CA17may be connected to source/drain regions of the first active region AR1or the second active region AR2. For example, a first source/drain contact CA11may be formed on the first active region AR1between the first gate electrode G1and the first cell separation pattern I1a. A second source/drain contact CA12may be formed on the first active region AR1between the first gate electrode G1and the second gate electrode G2. A third source/drain contact CA13may be formed on the first active region AR1between the second gate electrode G2and the third gate electrode G3. A fourth source/drain contact CA14may be formed on the first active region AR1and the second active region AR2between the third gate electrode G3and the second cell separation pattern I1b. A fifth source/drain contact CA15may be formed on the second active region AR2between the first gate electrode G1and the first cell separation pattern I1a. A sixth source/drain contact CA16may be formed on the second active region AR2between the first gate electrode G1and the second gate electrode G2. A seventh source/drain contact CA17may be formed on the second active region AR2between the second gate electrode G2and the third gate electrode G3.

The plurality of first contact vias VA11to VA17may be placed to overlap corresponding ones of the plurality of source/drain contacts CA11to CA17. Here, the term “overlap” means an overlap in a third direction Z that intersects the first direction X and the second direction Y. The first contact vias VA11to VA17may be connected to the source/drain contacts CA11to CA17, respectively.

The plurality of gate contacts CB11to CB13may be placed to overlap the first gate electrode G1, the second gate electrode G2, and the third gate electrode G3, respectively. Here, the term “overlap” means an overlap in the third direction Z. As shown, the first gate contact CB11may be connected to the first gate electrode G1, the second gate contact CB12may be connected to the second gate electrode G2, and the third gate contact CB13may be connected to the third gate electrode G3.

The first power supply wiring VDDand the second power supply wiring VSSmay be spaced apart from each other in the second direction Y. For example, the first power supply wiring VDDand the second power supply wiring VSSmay each extend lengthwise in the first direction X, and second power supply wiring VSSmay be spaced apart from the first power supply wiring VDDin the second direction Y.

The first power supply wiring VDDand the second power supply wiring VSSmay provide a power supply voltage to the first cell region CR1. In some embodiments, a drain voltage may be applied to the first power supply wiring VDD, and a source voltage may be applied to the second power supply wiring VSS. For example, a positive (+) voltage may be applied to the first power supply wiring VDD, and a ground GND voltage or a negative (−) voltage may be applied to the second power supply wiring VSS, but the embodiment is not limited thereto.

The first power supply wiring VDDand the second power supply wiring VSSmay be formed in a BEOL (back end-of-line) process step. In some embodiments, the first power supply wiring VDDand the second power supply wiring VSSmay be formed at the same routing level as first routing wirings IW11, IW12, CW11, CW12, and OW1to be explained below. For example, the first power supply wiring VDDand the second power supply wiring VSSmay be placed at the first routing level M1, as explained more fully hereinbelow.

The first power supply wiring VDDmay be connected to some of the source/drain contacts CA11to CA17. For example, the first power supply wiring VDDmay be connected to the first via pattern VA11and the third via pattern VA13. Accordingly, the first source/drain contact CA11and the third source/drain contact CA13may be connected to the first power supply wiring VDD. In contrast, the second power supply wiring VSSmay be connected to some other parts of the source/drain contacts CA11to CA17. For example, the second power supply wiring VSSmay be connected to the seventh via pattern VA17. Accordingly, the seventh source/drain contact CA17may be connected to the second power wiring VSS.

Each of the plurality of first routing wirings IW11, IW12, CW11, CW12, and OW1may extend in the first direction X. The first routing wirings IW11, IW12, CW11, CW12, and OW1may be formed at the BEOL process step. The first routing wirings IW11, IW12, CW11, CW12, and OW1may be formed at the same routing level as each other. For example, the first routing wirings IW11, IW12, CW11, CW12, and OW1may be placed at the first routing level M1. In some embodiments, the first routing level M1may be a routing level placed at the lowermost part among the wirings formed at the BEOL process step.

In some embodiments, the first routing wirings IW11, IW12, CW11, CW12, and OW1may be interposed between the first power supply wiring VDDand the second power supply wiring VSS. For example, a routing region RA may be defined between the first power supply wiring VDDand the second power supply wiring VSS. The routing region RA may include first to third routing tracks I to III arranged sequentially along the second direction Y, as an example. Each of the first routing wirings IW11, IW12, CW11, CW12, and OW1may be placed in one of the first to third routing tracks I to III. In some embodiments, the routing region RA may include three or less routing tracks.

The first routing wirings IW11, IW12, CW11, CW12, and OW1may be connected to some of the source/drain contacts CA11to CA17or some of the gate contacts CB11to CB13. As an example, the first routing wirings IW11, IW12, CW11, CW12, and OW1may include first to fifth wiring patterns IW11, IW12, CW11, CW12, and OW1.

The first wiring pattern IW11is placed in the second routing track II, and may be connected to the first gate contact CB11. As a result, the first gate electrode G1may be connected to the first wiring pattern IW11. The first wiring pattern IW11may function as a first input wiring that provides a first input signal to the first cell region CR1. In contrast, the second wiring pattern IW12is placed inside the third routing track III, and may be connected to the second gate contact CB12. As a result, the second gate electrode G2may be connected to the second wiring pattern IW12. The second wiring pattern IW12may function as a second input wiring that provides a second input signal to the first cell region CR1. Next, the third wiring pattern CW11is placed inside the third routing track III, and may be connected to a fifth via pattern VA15. As a result, the fifth source/drain contact CA15may be connected to the third wiring pattern CW11. The third wiring pattern CW11may function as a connection wiring that connects signals in the first cell region CR1.

A fourth wiring pattern CW12is placed in the first routing track I, and may be connected to the second via pattern VA12and the third gate contact CB13. As a result, the second source/drain contact CA12and the third gate electrode G3may be connected to the fourth wiring pattern CW12. The fourth wiring pattern CW12may function as a connection wiring that connects signals in the first cell region CR1. A fifth wiring pattern OW1is placed in the second routing track II, and may be connected to the fourth via pattern VA14. As a result, the fourth source/drain contact CA14may be connected to the fifth wiring pattern OW1. The fifth wiring pattern OW1may function as a first output wiring that provides the first output signal from the first cell region CR1.

In some embodiments, the first routing wirings IW11, IW12, CW11, CW12, and OW1placed inside the same routing track may be spaced apart from each other by a predetermined distance. This may be due to a width of a mask pattern that separates the first routing wirings IW11, IW12, CW11, CW12, and OW1. For example, a spaced distance between the first wiring pattern IW11and the fifth wiring pattern OW1in the second routing track II may be the same as a spaced distance between the third wiring pattern CW11and the second wiring pattern IW12in the third routing track III. As used herein, the meaning of the term “same” includes not only exactly the same thing, but also minute differences that may occur due to process margins and the like.

The predetermined distance at which the first routing wirings IW11, IW12, CW11, CW12, and OW1placed inside the same routing track are spaced apart may be, but is not limited to, for example, 10 nm to 40 nm. As an example, the spaced distance between the first wiring pattern IW11and the fifth wiring pattern OW1, and the spaced distance between the third wiring pattern CW11and the second wiring pattern IW12may each be 25 nm to 35 nm.

The second routing wiring DW1(M2) may extend in the second direction Y. The second routing wiring DW1may be formed at the BEOL process step. The second routing wiring DW1may be formed at a level (e.g., M2) that is higher than the first routing wirings IW11, IW12, CW11, CW12, and OW1formed at a lower level. For example, the second routing wiring DW1may be placed at a second routing level M2that is higher than the first routing level M1.

The second routing wiring DW1may be connected to some of the first routing wirings IW11, IW12, CW11, CW12, and OW1. As an example, the second routing wiring DW1extends in the second direction Y, and may connect the first wiring pattern IW11and the fourth wiring pattern CW12. As an example, a first routing via V1athat connects the first wiring pattern IW11and the second routing wiring DW1may be formed, and a second routing via V1b, which electrically connects the fourth routing pattern CW12and the second routing wiring DW1, may be formed. Therefore, the first wiring pattern IW11may be electrically connected to the fourth wiring pattern CW12. Thus, the “upper level” second routing wiring DW1may function as a connection wiring that connects signals in the first cell region CR1. And, as illustrated, a 2-input AND (AND2) cell (3 NMOS, 3 PMOS) may be provided in the first cell region CR1through the first routing wirings IW11, IW12, CW11, CW12, and OW1and the second routing wiring DW1, as described herein.

In some embodiments, at least some of the first routing wirings IW11, IW12, CW11, CW12, and OW1may protrude from the boundary of the first cell region CR1. For example,FIG.1schematically shows that the third wiring pattern CW11, at M1(first direction X), protrudes from the boundary of the first cell region CR1. Specifically, the third wiring pattern CW11extends in the first direction X, and may protrude from the boundary of the first cell region CR1extending in the second direction Y. In some embodiments, a part of the third wiring pattern CW11may overlap the first cell separation pattern I1a.

In some embodiments, the third wiring pattern CW11protruding from the boundary of the first cell region CR1may be close to a minimum wiring length according to defined design “ground” rules (e.g., as specified by a design rule checking (DRC) tool algorithm). Here, the minimum wiring length means a minimum length at which the routing wirings (for example, the first routing wirings IW11, IW12, CW11, CW12, and OW1) placed at the first routing level M1may extend in the first direction X according to the defined design rules. As an example, a length Lm of the third wiring pattern CW11extending in the first direction X may be 2 gate pitches GP or less. Alternatively, as an example, the length Lm of the third wiring pattern CW11extending in the first direction X may be 1.5 gate pitches GP or less. As a further example, the length Lm of the third wiring pattern CW11extending in the first direction X may be 0.5 gate pitch GP or more and 1.5 gate pitches GP or less (i.e., 0.5 GP≤Lm≤1.5 GP).

A length D11of the third wiring pattern CW11protruding from the boundary of the first cell region CR1may vary, depending on the placement of the third wiring pattern CW11. As an example, the length D11of the third wiring pattern CW11protruding from the boundary of the first cell region CR1may be 0.5 gate pitch GP or less. Alternatively, as an example, the length D11of the third wiring pattern CW11protruding from the boundary of the first cell region CR1may be one gate pitch GP or less or 1.5 gate pitches GP or less.

As semiconductor devices become more highly integrated, securement of PnR (Placement and Routing) resources of the semiconductor devices becomes an increasingly important issue. For example, while the number of routing tracks placed in the cell region may gradually decrease, the routing wirings still need to satisfy the minimum wiring length according to the defined design rules. Thus, securing efficient PnR resources may be increasingly required.

The semiconductor device according to some embodiments may efficiently secure the PnR resources even in small areas, using the first routing wirings IW11, IW12, CW11, CW12, and OW1that at least partially protrude from the first cell region CR1in order to meet corresponding minimum length design rules associated with the routing wirings. For example, as described above, the third wiring pattern CW11is placed to protrude from the boundary of the first cell region CR1, and therefore, may provide the PnR resources for other routing wirings (e.g., IW11, IW12, CW12, OW1, and DW1). If the third wiring pattern CW11is designed by only being placed inside the boundary of the first cell region CR1, the third wiring pattern CW11may violate the minimum wiring length according to the defined design rules, and therefore may require a larger area of the first cell region CR1, or make it difficult to place other routing wirings (e.g., IW11, IW12, CW12, OW1, and DW1). Therefore, it is possible to provide a semiconductor device capable of securing efficient PnR (Placement and Routing) resources by having at least one “internal” cell wiring protrude outside the first cell region CR1in order to meet the minimum length design rule requirement.

FIG.2is a plan view for explaining a semiconductor device according to some embodiments.FIG.3is a cross-sectional view taken along A-A ofFIG.2.FIG.4is a cross-sectional view taken along B-B ofFIG.2.FIG.5is a cross-sectional view taken along C-C ofFIG.2. The semiconductor device shown inFIGS.2to5may be an example of the semiconductor device that is implemented using the layout diagram ofFIG.1. For convenience of explanation, repeated parts of contents explained above usingFIG.1will be only briefly explained (or omitted).

AlthoughFIGS.2to5show a fin-type transistor FinFET including a channel region of a fin-type pattern as semiconductor device according to some embodiments, this is only an example. The semiconductor device according to some embodiments may, of course, include a tunneling transistor, a transistor including nanowire, a transistor including nanosheet, a VFET (Vertical FET), a CFET (Complementary FET) or a three-dimensional (3D) transistor. Further, the semiconductor device according to some embodiments of the present inventive concept may also include a bipolar junction transistor, a laterally diffused metal oxide semiconductor (LDMOS) transistor, and the like.

Referring toFIGS.2to5, the semiconductor device according to some embodiment is formed on the substrate100. The substrate100may be bulk silicon or SOI (silicon-on-insulator). In contrast, the substrate100may be a silicon substrate, or may include other materials, but are not limited to, for example, silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead tellurium compounds, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide.

The substrate100may include a first active region AR1and a second active region AR2. In some embodiments, the first active region AR1and the second active region AR2may be separated by an element separation film I2. For example, as shown inFIGS.4and5, the element separation film I2may extend in the first direction X to separate the first active region AR1and the second active region AR2.

A plurality of active patterns F1and F2may be formed on the substrate100. For example, a first active pattern F1may be formed on the first active region AR1, and a second active pattern F2may be formed on the second active region AR2. In some embodiments, the first and second active patterns F1and F2may each include a fin-type pattern protruding from the upper surface of the substrate100.

The first and second active patterns F1and F2may be spaced part from each other and extend side by side. For example, the first and second active patterns F1and F2may each extend in the first direction X. In addition, the first and second active patterns F1and F2may be arranged side by side along the second direction Y.

The first and second cell separation patterns I1aand I1bmay cross the first and second active patterns F1and F2. The first and second cell separation patterns I1aand I1bmay define a first cell region CR1across the first and second active patterns F1and F2.

A field insulating film105may be formed on the substrate100. In some embodiments, the field insulating film105may surround at least a part of the side surfaces of the first and second active patterns F1and F2. For example, as shown inFIGS.4and5, a part of the first and second active patterns F1and F2may protrude upward from the field insulating film105. This field insulating film105may include, but is not limited to, for example, at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN) or a combination thereof.

The first to third gate electrodes G1to G3may intersect the first and second active patterns F1and F2, respectively. The first to third gate electrodes G1to G3may each include a gate conductive film130. The gate conductive film130may include, but is not limited to, for example, at least one of Ti, Ta, W, Al, Co and a combination thereof. The gate conductive film130may also include, for example, silicon or silicon germanium (SiGe) besides metal.

The gate conductive film130is shown as a single film, but the technical idea of the present inventive concept is not limited thereto. Unlike that shown, the gate conductive film130may also be formed by stacking a plurality of conductive materials. For example, the gate conductive film130may include a work function adjusting film that adjusts the work function, and a filling conductive film that fills a space formed by the work function adjusting film. The work function adjusting film may include, for example, at least one of TiN, TaN, TiC, TaC, TiAlC and a combination thereof. The filling conductive film may include, for example, W or Al. Such a gate conductive film130may be formed through a replacement process, for example; however, other processes may also be used.

A gate dielectric film120may be interposed between the first and second active patterns F1and F2and the gate conductive film130. For example, the gate dielectric film120may extend along the side walls and a bottom surface of the gate conductive film130. However, the technical idea of the present inventive concept is not limited thereto, and the gate dielectric film120may extend only along the bottom surface of the gate conductive film130. In some embodiments, a part of the gate dielectric film120may be interposed between the field insulating film105and the gate conductive film130. For example, as shown inFIG.4, the gate dielectric film120may further extend along the upper surface of the field insulating film105.

The gate dielectric film120may include, for example, at least one of silicon oxide, silicon oxynitride, silicon nitride, and high dielectric constant (high-k) material having a higher dielectric constant than silicon oxide. The high dielectric constant material may include, but is not limited to, for example, hafnium oxide.

The gate spacer140may be formed on the substrate100and the field insulating film105. The gate spacer140may extend along both sides of the gate conductive film130. For example, the gate spacer140may extend in the second direction Y and intersect the first and second active patterns F1and F2. The gate spacer140may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, for example.

A gate capping pattern150may extend along the upper surface of the gate conductive film130. For example, the gate capping pattern150may extend in the second direction Y to cover the upper surface of the gate conductive film130.

A first source/drain region160may be formed on the first active region AR1. For example, the first source/drain region160may be formed inside the first active pattern F1on both sides of the gate conductive film130. The first source/drain region160may be spaced apart from the gate conductive film130by the gate spacer140. A second source/drain region260may be formed on the second active region AR2. For example, the second source/drain region260may be formed inside the second active pattern F2on both sides of the gate conductive film130. The second source/drain region260may be spaced apart from the gate conductive film130by the gate spacer140. In some embodiments, each of the first source/drain region160and the second source/drain region260may include an epitaxial layer formed inside the first and second active patterns F1and F2.

When the semiconductor device formed in the first active region AR1is a PFET, the first source/drain region160may include p-type impurities or impurities for preventing diffusion of p-type impurities. For example, the first source/drain region160may include at least one of B, C, In, Ga, and Al or a combination thereof. In contrast, when the semiconductor device formed in the second active region AR2is an NFET, the second source/drain region260may include n-type impurities or impurities for preventing the diffusion of n-type impurities. For example, the second source/drain region260may include at least one of P, Sb, As, or a combination thereof.

The first source/drain region160and the second source/drain region260are each shown as a single film, but the technical idea of the present inventive concept is not limited thereto. For example, the first source/drain region160and the second source/drain region260may be formed of multi-layered films, with each including impurities having different concentrations from each other.

A plurality of interlayer insulating films110,210,410,510,610, and710may be formed on the substrate100. The interlayer insulating films110,210,410,510,610, and710may include, but are not limited to, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride and a low dielectric constant (low-k) material having a lower dielectric constant than silicon oxide.

The first interlayer insulating film110and the second interlayer insulating film210may be formed to cover the field insulating film105, the first source/drain region160, the second source/drain region260, the gate spacer140, and the gate capping pattern150. For example, the first interlayer insulating film110may cover the upper surface of the field insulating film105, the upper surface of the first source/drain region160, the upper surface of the second source/drain region260, and the side surfaces of the gate spacer140. The second interlayer insulating film210may cover the upper surface of the gate capping pattern150and the upper surface of the first interlayer insulating film110.

The source/drain contacts CA11to CA17may penetrate the first interlayer insulating film110and the second interlayer insulating film210, and be connected to the first source/drain region160or the second source/drain region260. For example, the first to fourth source/drain contacts CA11to CA14may be connected to the first source/drain region160, and the fourth to seventh source/drain contacts CA14to CA17may be connected to the second source/drain region260.

The gate contacts CB11to CB13may penetrate the first interlayer insulating film110, the second interlayer insulating film210, and the fourth interlayer insulating film410, and be connected to the gate conductive film130. For example, the first gate contact CB11may be connected to the gate conductive film130of the first gate electrode G1, the second gate contact CB12may be connected to the gate conductive film130of the second gate electrode G2, and the third gate contact CB13may be connected to the gate conductive film130of the third gate electrode G3.

The first contact vias VA11to VA17may penetrate the fourth interlayer insulating film410and be connected to the source/drain contacts CA11to CA17to correspond to them. In some embodiments, the upper surfaces of the first contact vias VA11to VA17and the upper surfaces of the gate contacts CB11to CB13may be placed on the same plane. For example, as shown inFIG.3, the upper surface of the second via pattern VA12and the upper surface of the third gate contact CB13may be placed on the same plane as the upper surface of the fourth interlayer insulating film410.

The first routing wirings IW11, IW12, CW11, CW12, and OW1may each extend in the first direction X. In some embodiments, the first routing wirings IW11, IW12, CW11, CW12, and OW1may be placed at a level (i.e., a first routing level M1) that is higher than those of the source/drain contacts CA11to CA17, the first contact vias VA11to VA17, and the gate contacts CB11to CB13. For example, the first routing wirings IW11, IW12, CW11, CW12, and OW1may be placed inside the fifth interlayer insulating film510.

In some embodiments, the first routing wirings IW11, IW12, CW11, CW12, and OW1may each be connected to some of the first contact vias VA11to VA17or some of the gate contacts CB11to CB13. For example, the first wiring pattern IW11may be connected to the upper surface of the first gate contact CB11, the second wiring pattern IW12may be connected to the upper surface of the second gate contact CB12, the third wiring pattern CW11may be connected to the upper surface of the fifth via pattern VA15, the fourth wiring pattern CW12may be connected to the upper surface of the second via pattern VA12and the upper surface of the third gate contact CB13, and the fifth wiring pattern OW1may be connected to the upper surface of the fourth via pattern VA14.

The first power supply wiring VDDand the second power supply wiring VSSmay each extend in the first direction X. In some embodiments, the first power supply wiring VDDand the second power supply wiring VSSmay be placed at a level (i.e., the first routing level M1) that is higher than those of the source/drain contacts CA11to CA17, the first contact vias VA11to VA17, and the gate contacts CB11to CB13. For example, the first power supply wiring VDDand the second power supply wiring VSSmay be placed inside the fifth interlayer insulating film510.

In some embodiments, the first power supply wiring VDDand the second power supply wiring VSSmay each be connected to some of the first contact vias VA11to VA17. For example, the first power supply wiring VDDmay be connected to the upper surface of the third via pattern VA13, and the second power supply wiring VSSmay be connected to the upper surface of the seventh via pattern VA17.

The first routing via V1aand the second routing via V1beach penetrate the sixth interlayer insulating film610, and may be connected to the first routing wirings IW11, IW12, CW11, CW12, and OW1. For example, the first routing via V1amay be connected to the upper surface of the third wiring pattern CW11, and the second routing via V1bmay be connected to the upper surface of the fourth routing pattern CW12.

The second routing wiring DW1may extend in the second direction Y. In some embodiments, the second routing wiring DW1is placed at a level (i.e., a second routing level M2) that is higher than those of the first routing wirings IW11, IW12, CW11, CW12, and OW1. For example, the second routing wiring DW1may be placed inside the seventh interlayer insulating film710. And, the second routing wiring DW1may be connected to the first routing via V1aand the second routing via V1b. For example, the second routing wiring DW1may be connected to the upper surface of the first routing via V1aand the upper surface of the second routing via V1b.

In some embodiments, the source/drain contacts CA11to CA17, the first contact vias VA11to VA17, the gate contacts CB11to CB13, the first power supply wiring VDD, the second power supply wiring VSS, the first routing wirings IW11, IW12, CW11, CW12, and OW1, the routing vias V1aand V1b, and the second routing wiring DW1may each include barrier films220,230,520, and720, and filling films222,232,522, and722. The barrier films220,230,520, and720may extend along the surfaces of the interlayer insulating films110,210,410,510,610, and710. The filling films222,232,522, and722may fill a space formed by the barrier films220,230,520, and720.

The barrier films220,230,520, and720may include a metal or metal nitride for preventing diffusion of the filling films222,232,522, and722. For example, the barrier films220,230,520, and720may include, but are not limited to, at least one of titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), platinum (Pt), alloys thereof, and nitrides thereof.

The filling films222,232,522, and722may include, but are not limited to, at least one of aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co) and alloys thereof.

Although the first contact vias VA11to VA17, the first power supply wiring VDD, the second power supply wiring VSS, the first routing wirings IW11, IW12, CW11, CW12, and OW1, the routing vias V1aand V1b, and the second routing wiring DW1are shown as only being formed by the dual damascene process, this is only an example, and they may of course be formed by a single damascene process or other wiring process.

FIGS.6to8are various other cross-sectional views taken along A-A ofFIG.2. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to5will be briefly explained or omitted. Referring toFIG.6, the semiconductor device according to some embodiments further includes a second contact via VB13. The second contact via VB13may penetrate the fourth interlayer insulating film410and be connected to the gate contacts CB11to CB13to correspond to them. The second contact via VB13may connect the gate contacts CB11to CB13and the first routing wirings IW11, IW12, CW11, CW12, and OW1. As an example, as shown, the second contact via VB13may connect the third gate contact CB13and the fourth wiring pattern CW12.

In some embodiments, the upper surfaces of the source/drain contacts CA11to CA17and the upper surfaces of the gate contacts CB11to CB13may be placed on the same plane. As an example, as shown, the upper surface of the second source/drain contact CA12and the upper surface of the third gate contact CB13may be placed on the same plane as the upper surface of the second interlayer insulating film210. In some embodiments, the upper surfaces of the first contact vias VA11to VA17and the upper surface of the second contact via VB13may be placed on the same plane. As an example, as shown, the upper surface of the second via pattern VA12and the upper surface of the second contact via VB13may be placed on the same plane as the upper surface of the fourth interlayer insulating film410.

Referring toFIG.7, the semiconductor device according to some embodiments further includes connecting contacts CM11to CM15. Each of these connecting contacts CM11to CM15may be connected to some of the source/drain contacts CA11to CA17or some of the gate contacts CB11to CB13. For example, a third interlayer insulating film314that covers the second interlayer insulating film210may be formed. Each of the connecting contacts CM11to CM15penetrates the third interlayer insulating film314, and may be connected to some of the source/drain contacts CA11to CA17or some of the gate contacts CB11to CB13.

The connecting contacts CM11to CM15may connect the source/drain contacts CA11to CA17and the first contact vias VA11to VA17, or may connect the gate contacts CB11to CB13and the second contact via VB13. As an example, as shown, the second connecting contact CM12may connect the second source/drain contact CA12and the second via pattern VA12, and may the fifth connecting contact CM15may connect the third gate contact CB13and the second contact via VB13.

In some embodiments, a liner film312may be further formed between the second interlayer insulating film210and the third interlayer insulating film314. The liner film312may prevent the second interlayer insulating film210from being damaged in the process of forming the connecting contacts CM11to CM15. The liner film312may include, but is not limited to, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonitride, aluminum nitride (AlN), or a combination thereof. The liner film312is shown as a single film, but the technical idea of the present inventive concept is not limited thereto. Unlike that shown, the liner film312may also be formed by stacking a plurality of insulating materials.

In some embodiments, the connecting contacts CM11to CM15may include a barrier film320and a filling film322. The barrier film320may include a metal or metal nitride for preventing diffusion of the filling film322.

Referring toFIG.8, in the semiconductor device according to some embodiments, the source/drain contacts CA11to CA17are directly connected to the first routing wirings IW11, IW12, CW11, CW12, and OW1. For example, the source/drain contacts CA11to CA17penetrate the first interlayer insulating film110, the second interlayer insulating film210, and the fourth interlayer insulating film410, and may be connected to the first source/drain region160or the second source/drain region260. As an example, as shown, the second source/drain contact CA12may be directly connected to the fourth wiring pattern CW12.

FIG.9is another cross-sectional view taken along C-C ofFIG.2. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to5will be briefly explained or omitted. Referring toFIG.9, at least a part of the first power supply wiring VDDand at least a part of the second power supply wiring VSSare buried in the substrate100.

For example, the substrate100may include trenches that are spaced apart from each other and extend in the first direction X side by side. The first power supply wiring VDDand the second power supply wiring VSSmay be buried in the trenches. In some embodiments, the first via pattern VA11and the third via pattern VA13may penetrate the first interlayer insulating film110and the field insulating film105. As a result, the first power supply wiring VDDburied in the substrate100may be connected to the first source/drain contact CA11and the third source/drain contact CA13.

In some embodiments, the seventh via pattern VA17may penetrate the first interlayer insulating film110and the field insulating film105. As a result, the second power supply wiring VSSburied in the substrate100may be connected to the seventh source/drain contact CA17.

In some embodiments, a substrate insulating film102may be interposed between the first power supply wiring VDDand the substrate100, and between the second power supply wiring VSSand the substrate100. The substrate insulating film102may electrically separate the first power supply wiring VDDand the second power supply wiring VSSfrom the substrate100. The substrate insulating film102may include, but is not limited to, for example, at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or a combination thereof.

FIGS.10and11are cross-sectional views for explaining a semiconductor device according to some embodiments. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to5will be briefly explained or omitted. Referring toFIGS.10and11, in the semiconductor device according to some embodiments, each of the first and second active patterns F1and F2may include a plurality of wire patterns114,116, and118. For example, each of the first and second active patterns F1and F2may include first, second and third wire patterns114,116, and118that are stacked on the substrate100sequentially, and spaced apart from each other. For example, the first wire pattern114may be spaced apart from the substrate100in the third direction Z, the second wire pattern116may be spaced apart from the first wire pattern114in the third direction Z, and the third wire pattern118may be spaced apart from the second wire pattern116in the third direction Z.

Each of the first to third wire patterns114,116, and118may extend in the first direction X. Further, each of the first to third wire patterns114,116, and118may penetrate the first to third gate electrodes G1to G3. As a result, as shown inFIG.11, the first to third gate electrodes G1to G3may surround the outer peripheral surfaces of the first to third wire patterns114,116, and118. As shown byFIG.11, although the cross sections of the first to third wire patterns114,116, and118are each shown as a rectangular shape, this is only an example. For example, each of the cross sections of the first to third wire patterns114,116, and118may be other polygons or circles, for example. In some embodiments, the first and second active patterns F1and F2may each have a fin-type pattern112that protrudes from the upper surface of the substrate100and extends in the first direction X. The first wire pattern114may be spaced apart from, for example, the fin-type pattern112in the third direction Z.

FIGS.12and13are layout diagrams for showing a semiconductor device according to some embodiments. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to5will be briefly explained or omitted. Referring toFIGS.12and13, the semiconductor device according to some embodiments further includes a second cell region CR2.

A standard cell provided by the cell library may be provided inside the second cell region CR2. InFIGS.12and13, the standard cell provided in the second cell region CR2is a 2-input AND (AND2) cell. As an example, the semiconductor device provided in the second cell region CR2may include the first and second active regions AR1and AR2, the first to third gate electrodes G1to G3, the source/drain contacts CA11to CA17, the first contact vias VA11to VA17, the gate contacts CB11to CB13, the first and second power supply wirings VDDand VSS, the first routing wirings IW11, IW12, CW11, CW12, and OW1, and the second routing wiring DW1that are described above.

The first cell region CR1and the second cell region CR2may be arranged along the first direction X. The second cell region CR2may be adjacent to the first cell region CR1. In some embodiments, the second cell region CR2may be defined by a first cell separation pattern I1aand a third cell separation pattern I1carranged along the first direction X.

In some embodiments, at least some of the first routing wirings IW11, IW12, CW11, CW12, and OW1of the second cell region CR2may retract from the boundary of the second cell region CR2.FIGS.12and13show, as an example, that the second wiring pattern IW12retracts from the boundary of the second cell region CR2. Specifically, the second wiring pattern IW12may retract from the boundary of the second cell region CR2extending in the second direction Y. In some embodiments, the second wiring pattern IW12may not overlap the fourth source/drain contact CA14.

The first routing wirings IW11, IW12, CW11, CW12, and OW1of the second cell region CR2may provide a space for the first routing wirings IW11, IW12, CW11, CW12, and OW1of the first cell region CR1. For example, the second wiring pattern IW12of the second cell region CR2that retracts from the boundary of the second cell region CR2may provide a space for the third wiring pattern CW11of the first cell region CR1that protrudes from the boundary of the first cell region CR1. More specifically, the third wiring pattern CW11of the first cell region CR1may extend in the first direction X over the first cell region CR1and the second cell region CR2. According, it is possible to provide a semiconductor device capable of securing efficient PnR resources with small unit cell size, and capable of meeting fabrication/process requirements associated with appropriate design rules checking (DRC) design tools.

In some embodiments, the second wiring pattern IW12retracting from the boundary of the first cell region CR1may be close to the minimum wiring length according to the defined design rules. As an example, a length Lm of the second wiring pattern IW12extending in the first direction X may be 2 gate pitches GP or less.

A length D21of the second wiring pattern IW12retracting from the boundary of the first cell region CR1may vary, depending on the placement of the second wiring pattern IW12. As an example, the length D21of the second wiring pattern IW12retracting from the boundary of the first cell region CR1may be 0.5 gate pitch GP or more. Alternatively, as an example, the length D21of the second wiring pattern IW12retracting from the boundary of the first cell region CR1may be one gate pitch GP or more or 1.5 gate pitches GP or more.

In some embodiments, at least some of the first routing wirings IW11, IW12, CW11, CW12, and OW1of the first cell region CR1may retract from the boundary of the first cell region CR1. As an example, the second wiring pattern IW12of the first cell region CR1may retract by D22from the boundary of the first cell region CR1. Although D22is shown as only being the same as D21, this is only an example, and D22may of course be smaller or greater than D21.

In some embodiments, at least some of the first routing wirings IW11, IW12, CW11, CW12, and OW1of the second cell region CR2may protrude from the boundary of the second cell region CR2. As an example, the third wiring pattern CW11of the second cell region CR2may protrude by D12from the boundary of the second cell region CR2. Although D12is shown as only being the same as D11, this is only an example, and D12may of course be smaller or greater than D11.

Accordingly, as described hereinabove and illustrated by the side-by-side two-input AND cells CR1, CR2withinFIG.13, for example, a first logic gate (e.g., AND2 within CR1) is defined within a first unit cell footprint on a semiconductor substrate. This first unit cell footprint is illustrated as the width of CR1in the X-direction. A first wiring pattern (e.g., CW11(M1)) is provided, which extends in a first direction (e.g., X-direction) across a portion of the first unit cell footprint (e.g., across the first cell separation pattern I1a), by an amount equal to D11. The first wiring pattern is electrically connected to at least one of a gate electrode and a source/drain region within the first logic gate, and has: (i) a first terminal end within a perimeter of the first unit cell footprint (e.g., within CR1), and (ii) a second terminal end, which extends outside the perimeter of the first unit cell footprint (i.e., into CR2). This second terminal end is patterned so that it is not electrically connected to any current carrying region of any semiconductor device that is located outside the perimeter of the first unit cell footprint (i.e., any device within CR2). Nonetheless, and advantageously, a length of the first wiring pattern CW11(M1) is equivalent to a minimum allowable length thereof, as defined by a corresponding layout design rule associated with the first logic device (and verified by a design rule checking (DRC) algorithm associated with a corresponding method of fabrication).

FIGS.14and15are layout diagrams for showing a semiconductor device according to some embodiments. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to5will be briefly explained or omitted. Referring toFIGS.14and15, the semiconductor device according to some embodiments further includes a third cell region CR3.

A standard cell provided by the cell library may be provided inside the third cell region CR3. InFIGS.14and15, the standard cell provided in the third cell region CR3is a 2-input NAND (NAND2) cell. As an example, the semiconductor devices provided in the third cell region CR3may include fourth and fifth gate electrodes G4and G5, source/drain contacts CA21to CA25, first contact vias VA21to VA25, gate contacts CB21and CB22, and first routing wiring IW21, IW22, and OW2. Since the connection between the fourth and fifth gate electrodes G4and G5, the source/drain contacts CA21to CA25, the first contact vias VA21to VA25, the gate contacts CB21and CB22, and the first routing wirings IW21, IW22, and OW2is similar to that explained above usingFIG.1, detailed description thereof will not be provided below.

The first cell region CR1and the third cell region CR3may be arranged along the first direction X. The third cell region CR3may be adjacent to the first cell region CR1. In some embodiments, the third cell region CR3may be defined by a first cell separation pattern I1aand a fourth cell separation pattern I1darranged along the first direction X.

A sixth wiring pattern IW21may function as a third input wiring that provides a third input signal to the third cell region CR3. A seventh wiring pattern IW22may function as a fourth input wiring that provides a fourth input signal to the third cell region CR3. An eighth wiring pattern OW2may function as a second output wiring that provides a second output signal from the third cell region CR3.

In some embodiments, at least some of the first routing wirings IW21, IW22, and OW2of the third cell region CR3may retract from the boundary of the third cell region CR3.FIGS.14and15show, as an example, that the sixth wiring pattern IW21retracts from the boundary of the third cell region CR3.

The first routing wirings IW21, IW22, and OW2of the third cell region CR3may provide a space for the first routing wirings IW11, IW12, CW11, CW12, and OW1of the first cell region CR1. For example, the sixth wiring pattern IW21retracting from the boundary of the third cell region CR3may provide a space for the third wiring pattern CW11protruding from the boundary of the first cell region CR1. More specifically, the third wiring pattern CW11may extend in the first direction X over the first cell region CR1and the third cell region CR3. Accordingly, it is possible to provide a semiconductor device capable of securing efficient PnR resources.

A length D23of the sixth wiring pattern IW21retracting from the boundary of the third cell region CR3may vary, depending on the placement of the sixth wiring pattern IW21. As an example, the length D23of the sixth wiring pattern IW21retracting from the boundary of the third cell region CR3may be 0.5 gate pitch GP or more. Alternatively, as an example, the length D23of the sixth wiring pattern IW21retracting from the boundary of the third cell region CR3may be one gate pitch GP or more, or 1.5 gate pitches GP or more.

FIGS.16and17are various layout diagrams for showing a semiconductor device according to some embodiments. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to15will be briefly explained or omitted. Referring toFIG.16, in the semiconductor device according to some embodiments, at least some of the first routing wirings IW21, IW22, and OW2of the third cell region CR3retract from both sides of the boundary of the third cell region CR3.

FIG.16schematically shows that the sixth wiring pattern IW21and the seventh wiring pattern IW22each retract from both sides of the boundary of the third cell region CR3. Lengths D23and D24of the sixth wiring pattern IW21and the seventh wiring pattern IW22retracting from both sides of the boundary of the third cell region CR3may vary, depending on the placement of the sixth wiring pattern IW21and the seventh the wiring pattern IW22. Accordingly, it is possible to provide a semiconductor device capable of securing more efficient PnR resources.

In some embodiments, the sixth wiring pattern IW21and the seventh wiring pattern IW22may each be close to the minimum wiring length according to the defined design rules. As an example, a length Lm of the sixth wiring pattern IW21and the seventh wiring pattern IW22extending in the first direction X may each be 2 gate pitches GP or less.

Referring toFIG.17, in the semiconductor device according to some embodiments, the sixth wiring pattern IW21and the seventh wiring pattern IW22are arranged to intersect (e.g., in a zigzag pattern) in the second direction Y.

As an example, the sixth wiring pattern IW21may retract by D25from one side of the boundary of the third cell region CR3. The seventh wiring pattern IW22may be spaced apart by D23from one side of the boundary of the third cell region CR3, and may be spaced apart by D24from the other side of the boundary of the third cell region CR3. In such a case, it is easy to provide PnR resources for high level wiring (for example, a routing wiring placed at the second routing level M2), and a semiconductor device capable of securing more efficient PnR resources may be provided.

FIG.18is a layout diagram for explaining a semiconductor device according to some embodiments. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to17will be briefly described or omitted. Referring toFIG.18, the semiconductor device according to some embodiments further includes a filler cell region FR.

The first cell region CR1and the filler cell region FR may be arranged along the first direction X. The filler cell region FR may be adjacent to the first cell region CR1. In some embodiments, the filler cell region FR may be defined by a first cell separation pattern I1aand a fifth cell separation pattern I1earranged along the first direction X.

A filler cell (or a dummy cell), which fills an empty space between the cell regions in which a standard cell is provided, may be provided inside the filler cell region FR. As an example, source/drain contacts or gate electrodes may not be placed between the first cell separation pattern I1aand the fifth cell separation pattern I1e.

The filler cell region FR may provide a space for the first routing wirings IW11, IW12, CW11, CW12, and OW1of the first cell region CR1. For example, the filler cell region FR may provide a space for a third wiring pattern CW11that protrudes from the boundary of the first cell region CR1. More specifically, the third wiring pattern CW11may extend in the first direction X over the first cell region CR1and the filler cell region FR. Accordingly, it is possible to provide a semiconductor device capable of securing efficient PnR resources.

FIGS.19to21are various layout diagrams for showing a semiconductor device according to some embodiments. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to17will be briefly described or omitted. Referring toFIG.19, in the semiconductor device according to some embodiments, the routing region RA of the third cell region CR3may include two or less routing tracks.

As an example, the routing region RA may include first and second routing tracks I and II that are sequentially arranged along the second direction Y. The first routing wirings IW21, IW22, and OW2of the third cell region CR3may each be placed on one of the first and second routing tracks I and II.

As an example, the sixth wiring pattern IW21may be placed in the second routing track II and connected to the fourth gate electrode G4. The seventh wiring pattern IW22may be placed in the second routing track I and connected to the fifth gate electrode G5.

In some embodiments, at least some of the first routing wirings IW21, IW22, and OW2of the third cell region CR3may protrude from the boundary of the third cell region CR3.FIG.19schematically shows that the sixth wiring pattern IW21and the seventh wiring pattern IW22each protrude from the boundary of the third cell region CR3. Specifically, the seventh wiring pattern IW22may protrude from one side of the third cell region CR3, and the sixth wiring pattern IW21may protrude from the other side of the third cell region CR3.

The lengths D13and D14of each of the sixth wiring pattern IW21and the seventh wiring pattern IW22protruding from the boundary of the third cell region CR3may vary, depending on the placement of the sixth wiring pattern IW21and the seventh wiring pattern IW22. As an example, the lengths D13and D14of each of the sixth wiring pattern IW21and the seventh wiring pattern IW22protruding from the boundary of the third cell region CR3may be 0.5 gate pitch GP or less.

Referring toFIG.20, the semiconductor device according to some embodiments includes a fourth cell region CR4. The standard cell provided by the cell library may be provided inside the fourth cell region CR4. InFIG.20, the standard cell provided in the fourth cell region CR4is a 2-input NAND (NAND2) cell, which may be configured from four (4) transistors (2 NMOS, 2 PMOS). As an example, the semiconductor devices provided in the fourth cell region CR4may include first to third active regions AR1to AR3, sixth and seventh gate electrodes G6and G7, source/drain contacts CA31to CA36, first contact vias VA31to VA36, gate contacts CB31and CB32, first and second power supply wirings VDDand VSS, first routing wirings IW31, IW32, CW31, and CW32, and a second routing wiring OW3. Since the connection between the first to third active regions AR1to AR3, the sixth and seventh gate electrodes G6and G7, the source/drain contacts CA31to CA36, the first contact vias VA31to VA36, the gate contacts CB31and CB32, the first and second power supply wirings VDDand VSS, the first routing wirings IW31, IW32, CW31, and CW32, and the second routing wiring OW3is similar to that explained above usingFIG.1, detailed description thereof will not be provided below.

In some embodiments, the fourth cell region CR4may be defined by a sixth cell separation pattern I1fand a seventh cell separation pattern I1garranged along the first direction X.

In some embodiments, a multi-row (height) standard cell may be provided inside the fourth cell region CR4. As an example, the second power supply wiring VSSin the fourth cell region CR4may be interposed between the two first power supply wirings VDD. The routing region RA may include, for example, first and second routing tracks I and II defined between one first power supply wiring VDDand the second power supply wiring VSS, and fourth and fifth routing tracks IV and V defined between the other first power supply wiring VDDand the second power supply wiring VSS. Each of the first routing wirings IW31, IW32, CW31, and CW32of the fourth cell region CR4may be placed in one of the first, second, fourth and fifth routing tracks I, II, IV, and V.

A ninth wiring pattern IW31may function as a third input wiring that provides the third input signal to the fourth cell region CR4. A tenth wiring pattern IW32may function as a fourth input wiring that provides the fourth input signal to the fourth cell region CR4. Eleventh and twelfth wiring patterns CW31and CW32may each function as connection wirings that connect signals in the fourth cell region CR4. The second routing wiring OW3may function as a second output wiring that provides the second output signal from the fourth cell region CR4.

In some embodiments, at least some of the first routing wirings IW31, IW32, CW31, and CW32of the fourth cell region CR4may protrude from the boundary of the fourth cell region CR4.FIG.20schematically shows that the eleventh wiring pattern CW31protrudes from the boundary of the fourth cell region CR4. A length D15of the eleventh wiring pattern CW31protruding from the boundary of the fourth cell region CR4may vary, depending on the placement of the eleventh wiring pattern CW31. As an example, the length D15of the eleventh wiring pattern CW31protruding from the boundary of the fourth cell region CR4may be 0.5 gate pitch GP or less.

In some embodiments, the eleventh routing pattern CW31protruding from the boundary of the fourth cell region CR4may be close to the minimum wiring length according to the defined design rules. As an example, the length Lm of the eleventh wiring pattern CW31extending in the first direction X may be 2 gate pitches GP or less.

Referring toFIG.21, the semiconductor device according to some embodiments includes a fifth cell region CR5. The standard cell provided by the cell library may be provided inside the fifth cell region CR5. InFIG.21, the standard cell provided in the fifth cell region CR5is a 2-input NAND (NAND2) cell. As an example, the semiconductor device provided in the fifth cell region CR5may include the first to third active regions AR1to AR3, the sixth and seventh gate electrodes G6and G7, the source/drain contacts CA41to CA45, the first contact vias VA41to VA45, the gate contacts CB41and CB42, the first and second power supply wirings VDDand VSS, the first routing wirings IW41, IW42, CW41, CW42, and OW4, and the second routing wiring DW2. Since the connection between the first to third active regions AR1to AR3, the sixth and seventh gate electrodes G6and G7, the source/drain contacts CA41to CA45, the first contact vias VA41to VA45, the gate contacts CB41to CB42, the first and second power supply wirings VDDand VSS, the first routing wirings IW41, IW42, CW41, CW42and OW4, and the second routing wiring DW2is similar to that explained above usingFIG.1, detailed description thereof will not be provided below.

In some embodiments, the fifth cell region CR5may be defined by a sixth cell separation pattern I1fand a seventh cell separation pattern I1garranged along the first direction X. In some embodiments, a multi-column standard cell may be provided inside the fifth cell region CR5. As an example, the first power supply wiring VDDin the fifth cell region CR5may be interposed between the two second power supply wirings VSS. The routing region RA may include, for example, first and second routing tracks I and II defined between one second power supply wiring VSSand the first power supply wiring VDD, and fourth and fifth routing tracks IV and V defined between the other second power supply wiring VSSand the first power supply wiring VDD. Each of the first routing wirings IW41, IW42, CW41, CW42, and OW4of the fifth cell region CR5may be placed in one of the first, second, fourth and fifth routing tracks I, II, IV, and V.

A thirteenth wiring pattern IW41may function as a third input wiring that provides the third input signal to the fifth cell region CR5. A fourteenth wiring pattern IW42may function as a fourth input wiring that provides the fourth input signal to the fifth cell region CR5. Each of fifteenth and sixteenth wiring patterns CW41and CW42may function as connection wirings that connect signals in the fifth cell region CR5. A seventeenth wiring pattern OW4may function as a second output wiring that provides the second output signal to the fifth cell region CR5.

In some embodiments, at least some of the first routing wirings IW31, IW32, CW31, and CW32of the fifth cell region CR5may protrude from the boundary of the fifth cell region CR5.FIG.21shows an example in which the fifteenth wiring pattern CW41and the seventeenth wiring pattern OW4protrude from the boundary of the fifth cell region CR5. Lengths D16and D17of each of the fifteenth wiring pattern CW41and the seventeenth wiring pattern OW4protruding from the boundary of the fifth cell region CR5may vary, depending on the placement of the fifteenth wiring pattern CW41and the seventeenth wiring pattern OW4. As an example, the lengths D16and D17of each of the fifteenth wiring pattern CW41and the seventeenth wiring pattern OW4protruding from the boundary of the fifth cell region CR5may be one gate pitch GP or less.

In some embodiments, the fifteenth wiring pattern CW41and the seventeenth wiring pattern OW4protruding from the boundary of the fifth cell region CR5may be close to the minimum wiring length according to the defined design rule. As an example, a length Lm of each of the fifteenth wiring pattern CW41and the seventeenth wiring pattern OW4extending in the first direction X may be 2 gate pitches GP or less.

FIGS.22and23are various layout diagrams for explaining a semiconductor device according to some embodiments. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to21will be briefly described or omitted. Referring toFIG.22, the semiconductor device according to some embodiments includes a sixth cell region CR6.

The standard cell provided by the cell library may be provided inside the sixth cell region CR6. Routing wirings of various routing levels may be provided inside the sixth cell region CR6. As an example, the semiconductor device provided in the sixth cell region CR6may include first routing wirings placed at the first routing level M1, second routing wirings placed at the second routing level M2higher than the first routing level M1, and third routing wirings placed at a third routing level M3higher than the second routing level M2.

In some embodiments, at least some of various routing wirings provided inside the sixth cell region CR6may protrude from the boundary of the sixth cell region CR6.FIG.22shows an example in which a part of the first routing wirings of the first routing level M1and a part of the second routing wirings of the second routing level M2protrude from the boundary of the sixth cell region CR6. Specifically, a part of the first routing wirings of the first routing level M1extends in the first direction X, and may protrude from the boundary of the sixth cell region CR6extending in the second direction Y. A part of the second routing wirings of the second routing level M2extends in the second direction Y, and may protrude from the boundary of the sixth cell region CR6extending in the first direction X.

A length D31of the first routing wiring of the first routing level M1protruding from the sixth cell region CR6may vary, depending on the placement of the sixth cell region CR6or the first routing wiring of the cell region adjacent to the sixth cell region CR6. As an example, the length D31of the first routing wiring of the first routing level M1protruding from the sixth cell region CR6may be 0.5 gate pitch GP or less, one gate pitch GP or less, or 1.5 gate pitches GP or less. Similarly, a length D32of the second routing wiring of the second routing level M2protruding from the sixth cell region CR6may also vary, depending on the placement of the sixth cell region CR6or the second routing wiring adjacent to the sixth cell region CR6.

Referring toFIG.23, the semiconductor device according to some embodiments includes a seventh cell region CR7. A standard cell provided by the cell library may be provided inside the seventh cell region CR7. Routing wirings of various routing levels may be provided inside the seventh cell region CR7. As an example, the semiconductor device provided in the seventh cell region CR7may include second routing wirings placed at the second routing level M2, and third routing wirings placed at the third routing level M3higher than the second routing level M2.

In some embodiments, at least some of the various routing wirings provided inside the seventh cell region CR7may protrude from the boundary of the seventh cell region CR7.FIG.23shows an example in which a part of the third routing wirings of the third routing level M3protrudes from the boundary of the seventh cell region CR7. Specifically, a part of the third routing wirings of the third routing level M3extends in the first direction X, and may protrude from the boundary of the seventh cell region CR7extending in the second direction Y.

A length D33of the third routing wiring of the third routing level M3protruding from the seventh cell region CR7may vary, depending on the placement of the seventh cell region CR7or the first routing wiring adjacent to the seventh cell region CR7.

Hereinafter, the layout design method and the method for fabricating the semiconductor device according to some embodiments will be described referring toFIGS.24to30B.

FIG.24is a block diagram of a computer system for performing the layout design of the semiconductor device according to some embodiments. Referring toFIG.24, the computer system may include a CPU10, a working memory30, an I/O device50, an auxiliary storage device70, and a system interconnector90. Here, the computer system may be provided as a dedicated device for a layout design of the semiconductor device according to some embodiments. In some embodiments, the computer system may also include various design and verification simulation programs.

The CPU10may execute software (application programs, operating systems, and device drivers) that runs on the computer system. The CPU10may execute the operating system loaded into the working memory30. The CPU10may execute various applications to be driven on the basis of the operating system. For example, the CPU10may execute a layout design tool32, a placement and routing tool34and/or an OPC tool36loaded into the working memory30.

The operating system or the application programs may be loaded into the working memory30. An operating system image (not shown) stored in the auxiliary storage device70may be loaded into the working memory30on the basis of the booting sequence, when booting up the computer system. The operating system may support various I/O operations of the computer system.

A layout design tool32for the layout design of the semiconductor device according to some embodiments may be loaded from the auxiliary storage device70into the working memory30. Subsequently, the placement and routing tool34, which places the designed standard cells, rearranges the internal wiring pattern in the placed standard cell, and routes the placed standard cells, may be loaded from the auxiliary storage device70into the working memory30. Subsequently, an OPC tool36that performs optical proximity correction (OPC) of the designed layout data may be loaded from the auxiliary storage device70into the working memory30.

The I/O device50may control the user input and output from the user interface devices. For example, the I/O device50includes a keyboard and a monitor, and may receive input of information from the user. The user may receive input of information about semiconductor regions and data paths that require adjusted operating characteristics, using the I/O device50. Also, the processing procedure and the processing results of the OPC tool36may be displayed through the I/O device50.

The auxiliary storage device70may be provided as a storage medium of the computer system. The auxiliary storage device70may store application programs, an operating system image, and various data.

The system interconnector90may be a system bus for providing a network inside the computer system. The CPU10, the working memory30, the I/O device50, and the auxiliary storage device70may be electrically connected and data may be exchanged through the system interconnector90.

FIG.25is a flowchart for explaining a layout design method and a method for fabricating the semiconductor device according to some embodiments. Referring toFIG.25, a high level design of the semiconductor integrated circuit may be performed, using the computer system explained above usingFIG.22(S10). The high level design may mean description of the integrated circuit to be designed in the parent language of the computer language. For example, a parent language such as C language may be used for the high level design. Circuits designed by high level design may be expressed more specifically by register transfer level (RTL) coding and simulation. Subsequently, the code generated by the register transfer level coding is converted into a netlist and may be synthesized by the entire semiconductor elements. A synthesized schematic circuit is verified by the simulation tool, and the adjustment process may be accompanied according to the verification result.

Subsequently, a layout design for implementing the logically completed semiconductor integrated circuit on a silicon substrate may be performed (S20). For example, the layout design may be performed by referring to the schematic circuit synthesized by the high level design or the netlist corresponding thereto. The layout design may include a routing procedure of placing and connecting various standard cells provided by the cell library according to the defined design rules.

The layout may be a procedure of defining the shape or size of a pattern for forming a transistor and metal wirings to be actually formed on a silicon substrate. For example, in order to actually form the inverter circuit on the silicon substrate, layout patterns such as PFET, NFET, P-WELL, N-WELL, the gate electrode, and the wiring patterns placed on them may be appropriately placed.

Next, routing on the selected and placed standard cells may be performed. Specifically, the upper wirings (routing patterns) may be placed on the placed standard cell. By performing the routing, the placed standard cells may be interconnected in accordance with the design. After routing, the layout may be verified whether there are any parts that violate the design rules. Items to be verified may include a DRC (Design Rule Check), an ERC (Electronical Rule Check), a LVS (Layout vs Schematic comparison tool) and the like.

Subsequently, an optical proximity correction (OPC) procedure may be performed (S30). The layout patterns provided through the layout design may be implemented on a silicon substrate, using a photolithography process. At this time, the optical proximity correction may be a technique for correcting a distortion phenomenon that may occur in the photolithography process.

Subsequently, a photomask may be produced on the basis of the layout changed by the optical proximity correction (S40). The photomask may be produced, for example, in a manner of drawing layout patterns, using a chrome film coated on a glass substrate. Subsequently, a semiconductor element may be fabricated, using the generated photomask (S50). In the process of fabricating the semiconductor element using a photomask, various types of exposure and etching processes may be repeated. Through these processes, the shape of the patterns formed at the time of layout design may be sequentially formed on the silicon substrate.

FIGS.26to28are layout diagrams for explaining the layout design method for the semiconductor device according to some embodiments. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to25will be briefly explained or omitted.

Referring toFIG.26, a first cell region CR1is provided. The standard cell provided by the cell library may be provided inside the first cell region CR1. In some embodiments, a relatively complex standard cell may be provided inside the first cell region CR1. For example, the standard cell provided in the first cell region CR1may be, but is not limited to, a 2-input AND (AND2) cell, a 2-2-input AND-OR-INVERTER (AOI22) cell, a flip-flop (FF) cell, a multiplexer (MUX) cell, or the like. InFIG.26, the standard cell provided in the first cell region CR1is a 2-input AND (AND2) cell. As an example, the first cell region CR1may include first routing wirings IW11, IW12, CW11, CW12, and OW1, and a second routing wiring DW1.

At least some of the first routing wirings IW11, IW12, CW11, CW12, and OW1may be designed to protrude from the boundary of the first cell region CR1. In some embodiments, among the first routing wirings IW11, IW12, CW11, CW12, and OW1, the wiring pattern protruding from the boundary of the first cell region CR1may be selected within a predetermined routing track.FIG.26schematically shows that the third wiring pattern CW11in the third routing track III protrudes from the boundary of the first cell region CR1. As an example, when the third wiring pattern CW11is placed inside the boundary of the first cell region CR1that implements a relatively complicated 2-input AND (AND2) cell, the third wiring pattern CW11may be smaller than the minimum wiring length according to the defined design rules. Therefore, the third wiring pattern CW11may be designed to protrude by D11from the boundary of the first cell region CR1.

Designing of the third wiring pattern CW11to protrude from the boundary of the first cell region CR1may be, but it is not limited to, for example, various operations such as placement of a mask pattern that defines the third wiring pattern CW11to protrude from the boundary of the first cell region CR1, addition of a mask layer that protects the mask pattern that defines the third wiring pattern CW11, or addition of a mask layer that protrudes from the boundary of the first cell region CR1.

As an example, cutting mask patterns XC may be provided. The cutting mask patterns XC may define the first routing wirings IW11, IW12, CW11, CW12, and OW1. Specifically, routing wirings extending in the first direction X and placed at the first routing level (M1ofFIG.1) may be provided inside each of the first to third routing tracks I to III. Next, the cutting mask patterns XC that are placed to overlap a part of the routing wirings may be provided. The region of the routing wirings that overlap the cutting mask patterns XC may be cut. Accordingly, the first routing wirings IW11, IW12, CW11, CW12, and OW1that are spaced apart from each other may be provided.

A spaced distance between the first routing wirings IW11, IW12, CW11, CW12, and OW1in the first direction X may be determined by a width XW of each cutting mask pattern XC in the first direction X. The width XW of each cutting mask pattern XC may be, but is not limited thereto, for example, 10 nm to 40 nm. As an example, the width XW of each cutting mask pattern XC may be 25 nm to 35 nm.

The cutting mask patterns XC may be provided at the step of performing the layout design (S20ofFIG.25). For example, the cutting mask patterns XC may be provided in the routing procedure for placing and connecting the standard cells. In some embodiments, the cutting mask patterns XC may be placed so that at least some of the first routing wirings IW11, IW12, CW11, CW12, and OW1protrude from the boundary of the first cell region CR1. As an example, the cutting mask patterns XC may include a first cutting mask XC11and a second cutting mask XC12that define a third wiring pattern CW11. At this time, as shown, the first cutting mask XC11may be shifted in a direction toward the outside of the first cell region CR1(for example, −X direction). Therefore, the third wiring pattern CW11may be designed to protrude from the boundary of the first cell region CR1.

The spaced distance between the cutting mask patterns XC in the first direction X may be close to the minimum wiring length according to the defined design rules. As an example, a spaced distance XL between the first cutting mask XC11and the second cutting mask XC12may be 2 gate pitches (GP ofFIG.1) or less. Alternatively, as an example, the spaced distance XL between the first cutting mask XC11and the second cutting mask XC12may be 1.5 gate pitches (GP) or less. As an example, the spaced distance XL between the first cutting mask XC11and the second cutting mask XC12may be 0.5 gate pitch GP or more and 1.5 gate pitches GP or less.

Referring toFIG.27, the third cell region CR3is provided. The standard cell provided by the cell library may be provided inside the third cell region CR3. In some embodiments, a relatively simple standard cell may be provided inside the third cell region CR3. For example, the standard cell provided in the third cell region CR3may be, but is not limited to, an inverter (INV) cell, a buffer (BUF) cell, a NAND cell, a NOR cell, or the like. InFIG.27, the standard cell provided in the third cell region CR3is a 2-input NAND (NAND2) cell. As an example, the third cell region CR3may include first routing wirings IW21, IW22, and OW2.

At least some of the first routing wirings IW21, IW22, and OW2may be designed to retract from the boundary of the third cell region CR3. In some embodiments, among the first routing wirings IW21, IW22, and OW2, the routing pattern retracting from the boundary of the third cell region CR3may be selected within a predetermined routing track.FIG.27schematically shows that the sixth wiring pattern IW21in the third routing track III retracts from the boundary of the third cell region CR3. As an example, the length of the sixth wiring pattern IW21may be shortened in the third cell region CR3, which implements a relatively simple 2-input NAND (NAND2) cell. Therefore, the sixth wiring pattern IW21may be designed to retract by D23from the boundary of the third cell region CR3.

Designing of the sixth wiring pattern IW21to retract from the boundary of the third cell region CR3may be, but is not limited to, for example, various operations such as placement of a mask pattern defining the sixth wiring pattern IW21to retract from the boundary of the third cell region CR3, addition of a mask layer that protects the mask pattern that defines the sixth wiring pattern IW21, or addition of a mask layer that protrudes from the boundary of the third cell region CR3.

As an example, cutting mask patterns XC may be provided. Since the cutting mask patterns XC are similar to those described above in the description ofFIG.26, detailed description thereof will not be provided below.

In some embodiments, the cutting mask patterns XC may be placed such that at least some of the first routing wiring IW21, IW22, and OW2retract from the boundary of the third cell region CR3. As an example, the cutting mask patterns XC may include a third cutting mask XC21and a fourth cutting mask XC22that define a sixth wiring pattern IW21. At this time, as shown, the third cutting mask XC21may be shifted in a direction toward the inside of the third cell region CR3(for example, −X direction). Therefore, the sixth wiring pattern IW21may be designed to retract from the boundary of the third cell region CR3.

Referring toFIG.28, the first cell region CR1and the third cell region CR3are placed to be adjacent to each other. The first cell region CR1and the third cell region CR3may be arranged along the first direction X and adjacent to each other. As an example, the first cell separation pattern I1amay separate the first cell region CR1and the third cell region CR3.

The first routing wirings IW21, IW22, and OW2of the third cell region CR3may provide a space for the first routing wirings IW11, IW12, CW11, CW12, and OW1of the first cell region CR1. For example, the sixth wiring pattern IW21retracting from the boundary of the third cell region CR3may provide a space for the third wiring pattern CW11protruding from the boundary of the first cell region CR1. More specifically, the third wiring pattern CW11may extend in the first direction X over the first cell region CR1and the third cell region CR3. Accordingly, it is possible to provide a layout design method for the semiconductor device capable of ensuring efficient PnR resources.

FIGS.29A to29Care various layout diagrams for explaining the layout design method for the semiconductor device according to some embodiments. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to28will be briefly described or omitted. Referring toFIGS.29A to29C, in the layout design method for the semiconductor device according to some embodiments, the cutting mask patterns XC may be designed so that at least some of the first routing wirings IW11, IW12, CW11, CW12, and OW1protrude or retract from the boundary of the first cell region CR1.

As an example, referring toFIGS.29A and29B, the cutting mask patterns XC may include a fifth cutting mask XC13, a sixth cutting mask XC14, and a seventh cutting mask XC15. The fifth cutting mask XC13may define one end of the second wiring pattern IW12, the sixth cutting mask XC14may define one end of the fifth wiring pattern OW1, and the seventh cutting mask XC13may define one end of the fourth wiring pattern CW12.

As an example, as shown inFIG.29A, each of the fifth cutting mask XC13, the sixth cutting mask XC14, and the seventh cutting mask XC15may be shifted in a direction toward the outside of the first cell region CR1(e.g., +X direction). In some embodiments, the fifth cutting mask XC13, the sixth cutting mask XC14, and the seventh cutting mask XC15may be arranged in a row along the second direction Y outside the first cell region CR1.

As another example, as shown inFIG.29B, the fifth cutting mask XC13may be shifted in a direction toward the inside of the first cell region CR1(e.g., −X direction), and the sixth cutting mask XC14may be shifted in the direction toward the outside of the first cell region CR1(e.g., +X direction). The seventh cutting mask XC15may not be shifted.

Also, as an example, referring toFIG.29C, the cutting mask patterns XC may include an eighth cutting mask XC16. The eighth cutting mask XC16extends in the second direction Y, and may define one end of the second wiring pattern IW12, one end of the fifth wiring pattern OW1, and one end of the fourth wiring pattern CW12.

As an example, the eighth cutting mask XC16may be placed outside the first cell region CR1. Therefore, the second wiring pattern IW12, the fifth wiring pattern OW1, and the fourth wiring pattern CW12may be designed to protrude from the boundary of the first cell region CR1.

FIGS.30A and30Bare various layout diagrams for explaining the layout design method for the semiconductor device according to some embodiments. For convenience of explanation, repeated parts of contents explained above usingFIGS.1to28will be briefly described or omitted. Referring toFIG.30A, the layout design method for the semiconductor device according to some embodiments may include provision of a first protective mask layer PM1.

The first protective mask layer PM1may define at least some of the first routing wirings IW11, IW12, CW11, CW12, and OW1. Specifically, the first protective mask layer PM1may be provided to cover at least some of the first routing wirings IW11, IW12, CW11, CW12, and OW1. The regions of the first routing wirings IW11, IW12, CW11, CW12, and OW1that overlap the first protective mask layer PM1may be protected. For example, the first protective mask layer PM1may protect the routing wiring from being cut by the cutting mask patterns (XC ofFIG.26).

In some embodiments, the first protective mask layer PM1may be placed so that at least some of the first routing wirings IW11, IW12, CW11, CW12, and OW1protrude or retract from the boundary of the first cell region CR1. As an example, the first protective mask layer PM1may overlap the third wiring pattern CW11. Therefore, the third wiring pattern CW11may be designed to protrude from the boundary of the first cell region CR1.

Referring toFIG.30B, the layout design method for the semiconductor device according to some embodiments may include provision of a second protective mask layer PM2. The second protective mask layer PM2may be provided to cover the first cell region CR1. In addition, the regions of the first routing wirings IW11, IW12, CW11, CW12, and OW1that overlap the second protective mask layer PM2may be protected. For example, the second protective mask layer PM2may protect the routing wirings from being cut by the cutting mask patterns (XC ofFIG.26).

In some embodiments, the boundary of the second protective mask layer PM2may be placed to protrude or retract from the boundary of the first cell region CR1. As an example, one side of the second protective mask layer PM2may be shifted in the direction toward the outside of the first cell region CR1(e.g., −X direction). Therefore, the third wiring pattern CW11may be designed to protrude from the boundary of the first cell region CR1.

While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present inventive concept as defined by the following claims. It is therefore desired that the present embodiments be considered in all respects as illustrative and not restrictive, reference being made to the appended claims rather than the foregoing description to indicate the scope of the invention.