Patent ID: 12189243

DETAILED DESCRIPTION

Technical solutions in some embodiments of the present disclosure will be described clearly and completely with reference to the accompanying drawings below. Obviously, the described embodiments are merely some but not all embodiments of the present disclosure. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present disclosure shall be included in the protection scope of the present disclosure.

Unless the context requires otherwise, throughout the description and the claims, the term “comprise” and other forms thereof such as the third-person singular form “comprises” and the present participle form “comprising” are construed as open and inclusive, i.e., “including, but not limited to”. In the description of the specification, the terms such as “one embodiment”, “some embodiments”, “exemplary embodiments”, “example”, “specific example” and “some examples” are intended to indicate that specific features, structures or characteristics related to the embodiment(s) or example(s) are included in at least one embodiment or example of the present disclosure. Schematic representations of the above terms do not necessarily refer to the same embodiment(s) or example(s). In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any suitable manner.

Hereinafter, the terms such as “first” and “second” are used for descriptive purposes only, and are not to be construed as indicating or implying the relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined with the term such as “first” or “second” may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the term “a plurality of/the plurality of” means two or more unless otherwise specified.

In the description of some embodiments, terms such as “coupled” and “connected” and their extensions may be used. For example, the term “connected” may be used in the description of some embodiments to indicate that two or more components are in direct physical or electrical contact with each other. As another example, the term “coupled” may be used in the description of some embodiments to indicate that two or more components are in direct physical or electrical contact. The term “coupled” or “communicatively coupled”, however, may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

As used herein, a term such as “about”, “substantially” or “approximately” includes a stated value and an average value within an acceptable range of deviation of a particular value. The acceptable range of deviation is determined by a person of ordinary skill in the art in view of the measurement in question and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system).

Exemplary embodiments are described herein with reference to sectional views and/or plan views as idealized exemplary drawings. In the drawings, thicknesses of layers and sizes of regions are enlarged for clarity. Thus, variations in shape relative to the accompanying drawings due to, for example, manufacturing technologies and/or tolerances may be envisaged. Therefore, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but including shape deviations due to, for example, manufacturing. For example, an etched region shown in a rectangular shape generally has a curved feature. Therefore, the regions shown in the accompanying drawings are schematic in nature, and their shapes are not intended to show actual shapes of regions in a device, and are not intended to limit the scope of the exemplary embodiments.

A pogo test is performed on a display panel, that is, fix the display panel is fixed on a platform for the pogo test, and the display panel is pressed (e.g., a pressure is 50 kgf) by a pressure head of a pogo test device, after keeping for a period of time, the pressure head is removed and the display panel is lightened to confirm a pressing phenomenon. A supporting area of spacers is insufficient due to a low resolution (i.e., a low Pixels Per Inch (PPI)) of some display panels, and thus an anti-pressure ability of the display panel is relatively weak. As a result, after the pogo test, a black spot will appear at a pressuring position of the display panel, and does not disappear for a long time or disappears slowly, so that a quality of the display panel may be affected seriously.

Embodiments of the present disclosure provide a display apparatus200, as shown inFIG.9, the display apparatus200includes a display panel100.

As shown inFIGS.1and2, the display panel100includes an array substrate10and an opposite substrate20. The array substrate10and the opposite substrate20are arranged opposite to each other.

The display panel100further includes a liquid crystal layer30disposed between the array substrate10and the opposite substrate20.

The array substrate10includes a first substrate101and a plurality of sub-pixels P disposed on the first substrate101. The plurality of sub-pixels P are arranged in an array.

For example, as shown inFIG.1, sub-pixels P arranged in a line in a horizontal direction X are referred to as a row of sub-pixels, and sub-pixels P arranged in a line in a vertical direction Y are referred to as a column of sub-pixels.

The opposite substrate20includes a second substrate201and a plurality of first spacers210disposed on the second substrate201.

An orthographic projection of a first spacer210on the array substrate10is located in a region R where a region between two adjacent rows of sub-pixels intersects with a region between two adjacent columns of sub-pixels.

In this case, in a process of pressing the display panel100, the first spacers210may support the display panel100, which may improve the anti-pressure ability of the display panel100compared to a case where there is no spacer in the region where the region between two adjacent rows of sub-pixels intersects with the region between two adjacent columns of sub-pixels.

Therefore, in the display panel100in the embodiments of the present disclosure, an orthographic projection of a first spacer210of the plurality of first spacers210in the opposite substrate20on the array substrate10is located in a region where a region between two adjacent rows of sub-pixels intersects with a region between two adjacent columns of sub-pixels, the first spacer210may support the display panel100when the display panel100is pressed. Compared to the case where there is no spacer in the region where the region between two adjacent rows of sub-pixels intersects with the region between two adjacent columns of sub-pixels, the supporting area of the spacers in the embodiments of the present disclosure to the display panel100is increased, a supporting strength of the spacers to the display panel100is improved, and the anti-pressure ability of the display panel100is improved, thereby preventing the display panel100from being pressed poorly, and improving the anti-pressure ability of the display apparatus200.

In some embodiments, as shown inFIGS.1and2, the opposite substrate20further includes a plurality of second spacers220.

Orthographic projections of the second spacers220on the second substrate201are non-overlapping with orthographic projections of the first spacers210on the second substrate201.

The plurality of second spacers220are arranged in a plurality of columns, and second spacers in each column are arranged in a column direction (i.e., the vertical direction Y) in which the plurality of sub-pixels P are arranged. Orthographic projections of the second spacers220in each column on the array substrate10are located in a column region where a column of sub-pixels are located.

It will be noted that a column region where a column of sub-pixels are located includes a region where each sub-pixel in the column of sub-pixels is located and a region between every two adjacent sub-pixels in the column of sub-pixels, and reference can be made to the M region inFIG.1.

For example, an orthographic projection of the second spacer220on the first substrate101is located between orthographic projections of two adjacent sub-pixels in the same column on the first substrate101.

In this case, when the display panel100is pressed, the first spacers210and the second spacers220may support the display panel100together, and thus a supporting area of the first spacers210and the second spacers220to the display panel100is increased, the supporting strength of the first spacers210and the second spacers220to the display panel100is improved, and the anti-pressure ability of the display panel100is improved, thereby preventing the display panel100from being pressed poorly.

The first spacers210and the second spacers220are all auxiliary spacers. For example, a distribution density of the auxiliary spacers (including the first spacers210and the second spacers220) in the embodiments of the present disclosure is increased by 50% compared to a distribution density of original auxiliary spacers (only including the second spacers, and not including the first spacers). In a case where a supporting area of the first spacers210and a supporting area of the second spacers220are equal, a supporting area of the auxiliary spacers (including the first spacers210and the second spacers220) is increased by 50% compared to a supporting area of the original auxiliary spacers (only including the second spacers, and not including the first spacers).

It will be noted that, in a direction parallel to a plane where the second substrate201is located, a distance between edges proximate to each other of the first spacer210and the second spacer220adjacent to the first spacer210is greater than a deviation of process capability in an actual production process. In this way, it is possible to avoid affecting film-forming effects of the first spacers210and the second spacers220due to actual process errors, thereby avoiding affecting supporting capacities of the first spacers210and the second spacers220, and avoiding affecting the anti-pressure ability of the display panel100.

In some embodiments, the plurality of second spacers220and the plurality of first spacers210are disposed in the same layer.

A material of the plurality of second spacers220is the same as a material of the plurality of first spacers210.

In this case, the second spacers220and the first spacers210are formed synchronously, thereby saving processes.

In some embodiments, as shown inFIGS.1to4, a dimension of the first spacer210and a dimension of the second spacer220are equal or approximately equal in a direction perpendicular to the plane PL where the second substrate201is located.

It will be understood that a distance between a surface of the first spacer210proximate to the array substrate10and a surface of the first spacer210proximate to the second substrate201is equal or approximately equal to a distance between a surface of the second spacer220proximate to the array substrate10and a surface of the second spacer220proximate to the second substrate201.

In some embodiments, in a unit area of 1 mm2of the array substrate10, a sum of an area of surfaces of the first spacers210away from the second substrate201and an area of surfaces of the second spacers220away from the second substrate201is greater than 10000 μm2. In this way, the supporting strength of the display panel100may be improved, thereby avoiding the black spot or a defect of Mura of the display panel100.

It will be noted that a shape of the orthographic projection of the first spacer210on the array substrate10and a shape of the orthographic projection of the second spacer220on the array substrate10may be the same or different, for example, both of them may be circular or hexagonal.

An area of the orthographic projection of the first spacer210on the array substrate10and an area of the orthographic projection of the second spacer220on the array substrate10may be equal or not equal.

In some embodiments, as shown inFIGS.3and4, the opposite substrate20further includes a plurality of filter patterns202disposed on a side of the first spacers210proximate to the second substrate201.

For example, the plurality of filter patterns202include red filter patterns, blue filter patterns and green filter patterns. Light emitted from the red filter patterns is red light, light emitted from the blue filter patterns is blue light, and light emitted from the green filter patterns is green light.

Orthographic projections of a column of sub-pixels on the first substrate101are within an orthographic projection of a filter pattern202on the first substrate101.

An orthographic projection of the first spacer210on the second substrate201is located within an orthographic projection of a filter pattern202on the second substrate201.

In a direction perpendicular to an extension direction of the filter pattern202(i.e., the horizontal direction X inFIG.3), the filter pattern202has a protruding portion T1at a position corresponding to the first spacer210. The orthographic projection of the first spacer210on the second substrate201overlaps with an orthographic projection of the protruding portion T1of the filter pattern202on the second substrate201.

In a case where the opposite substrate20includes the second spacers220, the orthographic projection of the protruding portion T1on the second substrate201is non-overlapping with orthographic projections of the second spacers220on the second substrate201.

In this case, a bottom of the first spacer210is located on the same filter pattern202without stretching across two adjacent filter patterns202. A film thickness uniformity of the same filter pattern202is better than a film thickness uniformity of different filter patterns202, that is, a thickness uniformity of the protruding portion T1of the filter pattern202where the first spacer210is located is relatively good. Therefore, a surface of the first spacer210proximate to the second substrate201is flat, and the first spacer is uniformly stressed in the process of pressing the display panel100, thereby preventing the first spacer210from being damaged (e.g., from cracking).

It will be noted that, in the direction parallel to the plane where the second substrate201is located, a distance between edges proximate to each other of the first spacer210and the protruding portion T1of the filter pattern202corresponding to the first spacer210and a distance between edges proximate to each other of the protruding portion T1and the second spacer220adjacent to the protruding portion T1, are both greater than a deviation of process capability in the actual production process. In this way, it is possible to avoid a problem caused by process errors that the orthographic projection of the first spacer210on the second substrate201is beyond the edge of the orthographic projection of the protruding portion T1of the filter pattern202on the second substrate201to affect flatness of the surface of the first spacer210proximate to the second substrate201, thereby avoiding affecting the supporting capacity of the first spacers210and the anti-pressure ability of the display panel100.

In some embodiments, as shown inFIG.3, a filter pattern202adjacent to the filter pattern202having the protruding portion T1in the plurality of filter patterns202has a recessed portion T2. The protruding portion T1extends into the recessed portion T2.

It will be noted that the protruding portion T1may be in contact with an edge of the recessed portion T2proximate to the protruding portion T1without a gap therebetween. In the actual production process, the protruding portion T1may be lapped on the edge of the recessed portion T2proximate to the protruding portion T1, or there is a small gap or approximately no gap between the protruding portion T1and the edge of the recessed portion T2proximate to the protruding portion T1.

In a case where the protruding portion T1is lapped on the edge of the recessed portion T2proximate to the protruding portion T1, an orthographic projection of the first spacer210on the first substrate101is non-overlapping with a lapped region. In a case where there is a gap between the protruding portion T1and the edge of the recessed portion T2proximate to the protruding portion T1, the orthographic projection of the first spacer210on the first substrate101is non-overlapping with an orthographic projection of the gap on the first substrate101. It will be understood that an edge of an orthographic projection of the protruding portion T1on the array substrate10proximate to the recessed portion T2coincides with an edge of an orthographic projection of the recessed portion T2on the array substrate10proximate to the protruding portion T1.

In this case, an orthographic projection of a protruding portion T1of a filter pattern202on the second substrate201is non-overlapping with orthographic projections of other filter patterns202on the second substrate201. An orthographic projection of a recessed portion T2of a filter pattern202on the second substrate201is non-overlapping with orthographic projections of other filter patterns202on the second substrate201.

Thus, at a position of the protruding portion T1of the filter pattern202, an adjacent filter pattern202has the recessed portion T2, which does not cover the protruding portion T1and does not affect film uniformity of the protruding portion T1, so that thicknesses of all positions of the protruding portion T1are uniform. In this case, the surface of the first spacer210proximate to the second substrate201is flat, and the first spacer is uniformly stressed in the process of pressing the display panel100, thereby preventing the first spacer210from being damaged.

In some embodiments, as shown inFIGS.1and2, the array substrate10further includes a plurality of gate lines GL disposed on the first substrate101. At least one gate line GL is located between two adjacent rows of sub-pixels.

The orthographic projection of the first spacer210on the first substrate101overlaps with an orthographic projection of the gate line GL on the first substrate101.

In a case where the opposite substrate20includes the plurality of second spacers220, the orthographic projection of the second spacer220on the first substrate101overlaps with the orthographic projection of the gate line GL on the first substrate101.

For example, a material of the gate line GL is a metal material.

In this case, in the process of pressing the display panel100, the first spacer210and the second spacer220are supported by the gate line GL on a side proximate to the array substrate10, thereby improving supporting effects of the first spacer210and the second spacer220.

It will be noted that a position of the second spacer220may be designed by those skilled in the art according to a size of a space between the gate line GL and adjacent sub-pixels on a condition that normal display of the display panel100is ensured. For example, as shown inFIG.1, in an extension direction of the gate line GL, two adjacent second spacers220are arranged in a staggered manner.

In some embodiments, as shown inFIG.1, the gate line GL has protruding portions T3in a column direction in which the sub-pixels are arranged (i.e., the vertical direction Y inFIG.1).

In the case where the opposite substrate20includes the plurality of second spacers220, the orthographic projection of the second spacer220on the array substrate10is located in a region where the protruding portion of the gate line GL is located.

In this case, in the process of pressing the display panel100, the second spacer220may be supported by the protruding portion of the gate line GL, so that a contact surface between the second spacer220and the array substrate10is uniformly stressed, thereby preventing the second spacer220from being damaged.

It will be noted that a protruding direction of the protruding portion of the gate line GL may be designed by those skilled in the art according to a space size of a region where the gate line GL is located.

In some embodiments, as shown inFIG.1, in the column direction in which the sub-pixels are arranged, the protruding portion of the gate line GL protrudes towards a side away from a row of sub-pixels coupled to the gate line GL. In this way, it is possible to avoid that a distance between the gate line GL and the sub-pixel P is so small that a size of a light-emitting region of the sub-pixel is affected, thereby avoiding affecting an aperture ratio of the display panel100.

In some embodiments, as shown inFIGS.1,3, and6to9, two gate lines GL are disposed between two adjacent rows of sub-pixels.

In two adjacent sub-pixels in a row of sub-pixels, a gate line GL to which one sub-pixel is coupled is located on one side of two opposite sides of the row of sub-pixels in the column direction, and a gate line GL to which the other sub-pixel is coupled is located on the other side of the two opposite sides of the row of sub-pixels in the column direction.

It will be understood that a row of sub-pixels are coupled to two gate lines GL. For example, in a row of sub-pixels, sub-pixels in odd columns are coupled to one gate line GL, and sub-pixels in even columns are coupled to the other gate line GL.

In some embodiments, as shown inFIG.1, in the case where the opposite substrate20includes the plurality of second spacers220, in the region between two adjacent rows of sub-pixels, an orthographic projection of one second spacer220in two adjacent second spacers220on the first substrate101overlaps with an orthographic projection of one gate line GL in the two gate lines GL on the first substrate101, and an orthographic projection of the other second spacer220in the two adjacent second spacers220on the first substrate101overlaps with an orthographic projection of the other gate line GL in the two gate lines GL on the first substrate101.

It will be understood that the two gate lines GL in the region between two adjacent rows of sub-pixels are respectively coupled to the two adjacent rows of sub-pixels.

It will be noted that the positions of the second spacers220may be designed by those skilled in the art according to actual situations and a size of a space where the gate line GL is located.

For example, in the region between two adjacent rows of sub-pixels, the orthographic projections of the two adjacent second spacers220on the first substrate101may overlap with the orthographic projection of one gate line GL in the two gate lines GL on the first substrate101, but may be non-overlapping with the orthographic projection of the other gate line GL in the two gate lines GL on the first substrate101.

In some embodiments, as shown inFIGS.1,3, and6to9, the array substrate10further includes a plurality of data lines DL disposed on the first substrate101. Two adjacent columns of sub-pixels are coupled to a data line DL.

For example, two adjacent columns of sub-pixels are grouped into a group, and a data line DL is disposed between two adjacent groups of sub-pixels.

In some embodiments, as shown inFIGS.1,3, and6to9, the array substrate10further includes a plurality of common signal lines CL disposed on the first substrate101. The plurality of common signal lines CL and the plurality of data lines DL have the same extension direction. A common signal line CL is located between two adjacent columns of sub-pixels. The common signal line CL is configured to transmit a common voltage signal to sub-pixels.

In a row direction in which the sub-pixels P are arranged, a common signal line CL is located between two adjacent data lines DL.

As shown inFIGS.1and2, the orthographic projection of the first spacer210on the first substrate101overlaps with an orthographic projection of the common signal line CL on the first substrate101.

For example, two adjacent columns of sub-pixels are grouped into a group, a data line DL is disposed between two adjacent groups of sub-pixels, and a common signal line CL is disposed between two columns of sub-pixels in each group of sub-pixels.

The orthographic projection of the first spacer210on the first substrate101overlaps with an orthographic projection of an intersection region of the common signal line CL and the gate line GL on the first substrate101.

In some embodiments, as shown inFIGS.1,3, and6to9, the array substrate10further includes a thin film transistors (TFT) disposed in the sub-pixel P.

TFTs in the two adjacent sub-pixels in the row of sub-pixels are respectively located on two opposite sides of the row of sub-pixels in the column direction.

For the two opposite sides of the row of sub-pixels P in the column direction, a TFT on one side is coupled to a gate line GL disposed on the same side as the TFT on the one side, and a TFT on the other side is coupled to a gate line GL disposed on the same side as the TFT on the other side.

For example, in the case where the opposite substrate20includes the plurality of second spacers220, as shown inFIGS.1,3and9, the orthographic projection of the second spacer220on the first substrate101is non-overlapping with an orthographic projection of the TFT on the first substrate101; or as shown inFIG.6, the orthographic projection of the second spacer220on the first substrate101overlaps with an orthographic projection of a TFT on the first substrate101.

It will be noted that the positions of the second spacers220may be designed by those skilled in the art according to actual situations. For example, in a case where the opposite substrate20further includes main spacers, the positions of the second spacers220may be designed according to a height difference between a main spacer and the second spacer220(i.e., the auxiliary spacer) and a position of the main spacer, which is not limited here.

In some embodiments, as shown inFIGS.1,3and6to9, the array substrate10further includes a plurality of first electrodes110disposed on the first substrate101. A first electrode110is located in a sub-pixel P. The first electrode110is coupled to the TFT.

The first electrode110is a pixel electrode.

As shown inFIG.5, the opposite substrate20further includes a second electrode120disposed on the second substrate201. The second electrode120is located on the side of the first spacer210proximate to the second substrate201.

The second electrode120is a common electrode.

It will be understood that in a case where the opposite substrate20includes the plurality of filter patterns202, the second electrode120is located on a side of the filter pattern202away from the second substrate201.

In a case where the array substrate10includes the plurality of common signal lines CL, the second electrode120is coupled to the common signal lines CL (not shown in the figures).

In some embodiments, as shown inFIG.7, the array substrate10further includes the first electrodes110and the second electrodes120disposed on the first substrate101and located in the sub-pixels P.

The first electrode110is a planar electrode, and the second electrode120is a slit electrode.

The first electrode110is closer to the first substrate101than the second electrode120.

One of the first electrode110and the second electrode120is coupled to the TFT. For example, the first electrode110is coupled to the TFT, and in this case, the first electrode110is a pixel electrode; alternatively, the second electrode120is coupled to the TFT, and in this case, the second electrode120is a common electrode.

It will be understood that in the case where the array substrate10includes the plurality of common signal lines CL, if the first electrode110is coupled to the TFT, the second electrode120is coupled to the common signal line CL; alternatively, if the second electrode120is coupled to the TFT, the first electrode110is coupled to the common signal line CL.

In some embodiments, as shown inFIG.8, the array substrate10further includes a plurality of common signal lines CL disposed on the first substrate101.

The plurality of common signal lines CL and the plurality of gate lines GL are disposed in the same layer and are made of the same material.

A common signal line CL is located in a region where a row of sub-pixels is located. An orthographic projection of the common signal line CL on the first substrate101is non-overlapping with the orthographic projection of the TFT on the first substrate101.

As shown inFIG.8, the common signal line CL has a plurality of bending segments CL2, and any two adjacent bending segments CL2are coupled by a conductive pattern CL1at edges thereof proximate to each other. The conductive pattern CL1and the common signal line CL are in the same layer, and an orthographic projection of the conductive pattern on the first substrate101overlaps with orthographic projection of the data line DL on the first substrate101. A bending segment is located in a region where two adjacent sub-pixels in a row of sub-pixels are located, and a bending segment includes five sub-segments coupled in sequence. In an orthographic projection of the middlemost sub-segment on the first substrate101, edges of the orthographic projection on opposite sides in the extension direction of the gate line GL are located in different sub-pixels of two adjacent sub-pixels, and a middle portion of the orthographic projection is located in a gap region between the two sub-pixels.

In addition, in some embodiments, the opposite substrate20further includes third spacers disposed on the second substrate201.

The third spacers serve as main spacers to support the display panel100in the process of pressing the display panel100. A supporting area of the third spacers to the display panel100is smaller than a supporting area of the first spacers210and the second spacers220as a whole to the display panel100.

Orthographic projections of the third spacers on the array substrate10are non-overlapping with the orthographic projections of the first spacers210on the array substrate10and the orthographic projections of the second spacers220on the array substrate10.

In a thickness direction of the second substrate201, a height of the third spacer is greater than or approximately equal to a height of the second spacer220.

For example, the orthographic projection of the first spacer210on the array substrate10is located between the orthographic projection of the second spacer220on the array substrate10and the orthographic projection of the third spacer on the array substrate10.

An orthographic projection of the third spacer on the first substrate101overlaps with the orthographic projection of the TFT on the first substrate101; alternatively, the orthographic projection of the third spacer on the first substrate101is located between two sub-pixels in two adjacent rows and overlaps with the orthographic projection of the gate line GL on the first substrate101. Moreover, orthographic projections of the third spacers on the array substrate10are uniformly distributed.

It will be noted that a distribution density and an arrangement position of the third spacers may be designed by those skilled in the art according to actual requirements. For example, the array substrate10includes a plurality of sub-pixel groups, each sub-pixel group includes sub-pixels P, and the number of the sub-pixels P that each sub-pixel group includes is the same. An orthographic projection of a third spacer on the first substrate101is located in an orthographic projection of a sub-pixel group on the first substrate101.

For example, in the case where the opposite substrate20includes the plurality of second spacers220, the orthographic projection of the second spacer220on the first substrate101is non-overlapping with the orthographic projection of the TFT on the first substrate101; and in a case where the opposite substrate20further includes the third spacers (i.e., the main spacers) and a height difference between the third spacer and the second spacer220(i.e., the auxiliary spacer) is relatively small (for example, the height difference is approximately 0.1 μm), the orthographic projection of the third spacer on the first substrate101overlaps with the orthographic projection of the TFT on the first substrate101. In this way, it is possible to avoid a problem that in a case where the height difference between the third spacer (i.e., the main spacer) and the second spacer220(i.e., the auxiliary spacer) is relatively small and the orthographic projection of the third spacer on the first substrate101overlaps with the orthographic projection of the TFT on the first substrate101, if the orthographic projection of the second spacer220on the first substrate101overlaps with the orthographic projection of the TFT on the first substrate101, a support of the second spacer220is excessive in the process of pressing the display panel100, resulting in a poor display (e.g., an uneven display brightness) of the display panel100.

For example, in the case where the opposite substrate20includes the plurality of second spacers220, the orthographic projection of the second spacer220on the first substrate101overlaps with the orthographic projection of the TFT on the first substrate101; and in a case where the opposite substrate20includes the third spacers (i.e., the main spacers) and the height difference between the third spacer and the second spacer220(i.e., the auxiliary spacer) is relatively great (for example, the height difference is greater than 0.5 μm), the orthographic projection of the third spacer on the first substrate101overlaps with the orthographic projection of the TFT on the first substrate101. In this way, it is possible to avoid a problem that in the case where the opposite substrate20includes the third spacers (i.e., the main spacers) and the height difference between the third spacer and the second spacer220(i.e., the auxiliary spacer) is relatively great (for example, the height difference is greater than 0.5 μm), if the orthographic projection of the third spacer on the first substrate101overlaps with the orthographic projection of the gate line GL on the first substrate101, a supporting capacity of the third spacer is insufficient in the process of pressing the display panel100, resulting that the anti-pressure ability of the display panel100is reduced.

In addition, as shown inFIG.9, the display apparatus200further includes a driver integrated circuit (IC). The driver IC is bonded to the array substrate10in the display panel100, and is coupled to the data lines DL.

The driver IC is configured to transmit data signals to the data lines DL.

For example, the display apparatus200may be any apparatus that displays an image whether in motion (e.g., a video) or stationary (e.g., a still image), and whether textual or graphical. More specifically, it is anticipated that the embodiments may be implemented in a variety of electronic apparatuses or associated with a variety of electronic apparatuses. The variety of electronic apparatuses include, but are not limited to mobile phones, wireless apparatuses, personal data assistants (PDAs), hand-held or portable computers, GPS receivers/navigators, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automobile displays (e.g., odometer displays, etc.), navigators, cockpit controllers and/or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photos, electronic billboards or signs, projectors, building structures, packaging and aesthetic structures (e.g., displays for displaying an image of a piece of jewelry), etc.

The foregoing descriptions are merely specific implementations of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Changes or replacements that any person skilled in the art could conceive of within the technical scope of the present disclosure shall be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.