Patent ID: 12243937

DETAILED DESCRIPTION

FIG.1shows a HEMT transistor10. This HEMT transistor10is provided with a stack13which comprises, from a front side11to a back side12, an insulator layer14, a barrier layer15, and a channel layer16capable of forming a conduction layer16ain the form of a two-dimensional electron gas layer. In some implementations, conduction layer16aextends in channel layer16from an interface15a, formed between barrier layer15and said channel layer16.

The III-V semiconductor materials selected to form barrier layer15and/or channel layer16may comprise gallium nitride (GaN), aluminum nitride (AlN), AlxGa1-xNxternary alloys, gallium arsenide (GaAs), AlGaAs or InGaAs ternary alloys. For example, barrier layer15and channel layer16may respectively comprise an AlGaN compound and GaN. Insulator layer14may comprise a dielectric material, and in some implementations silicon dioxide (SiO2) or silicon nitride (Si3N4).

HEMT transistor10also comprises a source electrode17and a drain electrode18in electric contact with conduction layer16a. In some implementations, source electrode17and drain electrode18emerge through front side11, and cross barrier layer15to reach interface15aand electrically contact conduction layer16a. Source electrode17and drain electrode18may partially or integrally cross conduction layer16a. Source electrode17and drain electrode18may comprise a metal species, for example, aluminum, filling trenches formed in stack13.

HEMT transistor10also comprises a gate electrode19intended to be imposed a voltage Vg enabling to control the state of conduction layer16a. In some implementations, when the electric potential difference between gate electrode19and source electrode17, noted Vg-Vs, is greater than a threshold voltage Vth characteristic of HEMT transistor10, said transistor is in the conductive state. Conversely, when Vg-Vs is smaller than Vth, HEMT transistor10is in the non-conductive state, and thus behaves as an off switch.

Thus, depending on the value of threshold voltage Vth, and in some implementations on its sign, a HEMT transistor may be in depletion (normally-on) mode if its threshold voltage Vth is negative, or in enhancement (normally-off) mode if its threshold voltage Vth is positive.

Such a high electron mobility transistor however has an on-state resistivity Ron (Ron being the on-state drain/source resistance) which limits the intensity of the current likely to flow through the conduction layer.

In this regard, the main parameters influencing resistivity Ron are:the surface resistance of the channel layer;the resistance of the contacts between the conduction layer and the source and drain electrodes;the electric resistivities of the routing metals of the chips;the electric resistances induced in the final assembly having the high electron mobility transistor integrated therein.

There further exist situations, in some implementations in the field of power conversion and/or storage, for which a bidirectionality of the HEMT transistors may be required. However, such bidirectional transistors, unless occupying a relatively large surface area, have too high an on-state resistivity Ron.

An aim of the present disclosure thus is to provide a more compact bidirectional electronic device provided with high electron mobility transistors and having a reasonable on-state resistivity as compared with known devices of the state of the art.

Another aim of the present disclosure is to provide a bidirectional electronic device likely to operate at high electric voltages, in some implementations higher than 600 V.

It should be understood that the different drawings shown in relation with the present description are given as an illustration only and by no way limit the disclosure. It should be clear that the relative scales or dimensions may not be respected.

All throughout the description, it is admitted that a layer or an interface is generally planar and extends along a plane parallel to the (0, x, y) plane of the (0, x, y, z) orthonormal reference frame. Further, when reference is made to a representation along a cross-section plane, the latter is perpendicular to all the planes formed by the layers, and in some implementations perpendicular to the (0, x, y) plane. It should also be understood that, when reference is made to a stack of layers, the latter are stacked along the z direction of the (0, x, y, z) orthonormal reference frame.

The disclosure concerns a device formed by two (or more) high electron mobility transistors, (hereafter, “HEMT transistors”) respectively referred to as first transistor and second transistor stacked together. The HEMT transistors each comprise a stack of semiconductor layers respectively referred to as first stack and second stack. In some implementations, the first stack and the second stack are separated by an insulating layer and each extends from said insulating layer to, respectively, a first surface and a second surface of the device. In some implementations, each stack comprises, from the insulating layer, a barrier layer and a channel layer.

The first stack and the second stack also each comprise a set of electrodes respectively referred to as first set and second set. Each set of electrodes is in some implementations provided with a source electrode, a drain electrode, and a gate electrode which are arranged so that the first transistor and the second transistor are connected head-to-tail.

The device may also comprise two terminals respectively referred to as first terminal and second terminal (the latter form connection points) and between which a current is likely to flow either in the first transistor or in the second transistor.

In some implementations, the two terminals are respectively connected to a drain electrode of one of the first or the second HEMT transistor, and connected to a source electrode of another one of the first or the second HEMT transistor. For example, the first terminal may be in electric contact with one of the drain electrode of the first set or of the source electrode of the second set, while the second terminal may be in electric contact with one of the drain electrode of the second set or of the source electrode of the first set.

Such an arrangement forms a device which is both compact and bidirectional.

“Connected head-to-tail” is used to refer to two HEMT transistors connected according to opposite biasings. In some implementations, according to the terms of the present disclosure, two HEMT transistors are assembled head-to-tail when the source electrode of one of the transistors is electrically connected to the drain electrode of the other one of the transistors. In other words, the source electrode of the first transistor is connected to the drain electrode of the second transistor while the drain electrode of the first transistor is connected to the source electrode of the second transistor.

“Bidirectional device” is used to refer to a device arranged to conduct the current between two of its terminals in two opposite directions. In some implementations, according to the terms of the present disclosure, the first transistor, when it is in a conductive state, enables the flowing of a current in its channel layer from the first terminal to the second terminal (in a first direction). Equivalently, the second transistor, when it is in a conductive state, enables the flowing of a current in its channel layer from the second terminal to the first terminal (in a second direction opposite to the first direction).

Further, for a given HEMT transistor, the switching from one or the other of the conductive state and of the non-conductive state to the other one of these two states is controlled by the gate electrode of the concerned transistor. In some implementations, this control is executed by imposing a voltage Vg to the gate electrode. In some implementations, when the potential difference Vg-Vs between the gate electrode and the source electrode of the HEMT transistor is greater than its threshold voltage Vth, said transistor is in the conductive state and behaves as a conductive wire. On the contrary, when the potential difference Vg-Vs is smaller than the threshold voltage, the HEMT transistor is in a non-conductive state and behaves as an off switch.

FIG.2is a simplified representation of a device100according to an embodiment of the present disclosure.

The following description (relative to the first embodiment) will be limited to a first terminal in electric contact with the drain electrode of the first set and to a second terminal in electric contact with the drain electrode of the second set. Those skilled in the art, based on their general knowledge and on the present disclosure, may generalize the described concepts and thus consider other relative arrangements relative to the first terminal and to the second terminal.

Device100in some implementations comprises two high electron mobility transistors (HEMT) respectively referred to as first transistor200and second transistor300. In some implementations, device100comprises, from a first surface100ato a second surface100b, first transistor200, an insulating layer400, and second transistor300.

Insulating layer400may comprise a dielectric material, in some implementations, silicon dioxide or silicon nitride.

First transistor200and second transistor300each comprise a stack of semiconductor layers respectively referred to as first stack and second stack.

Each stack of semiconductor layers may in some implementations comprise group-III-V semiconductor materials, and in some implementations group-III-N semiconductor materials. The group-III-V semiconductor materials may in some implementations be selected from among gallium nitride (GaN), aluminum nitride (AlN), and their AlxGa1-xN ternary alloys, or from among gallium arsenide (GaAs) and its compounds (AlGaAs, InGaAs).

Each stack of semiconductor layers comprises, from the insulating layer, a barrier layer and a channel layer.

In some implementations, the first stack comprises, from insulating layer400to first surface100a, a first barrier layer201and a first channel layer202.

The second stack comprises, from insulating layer400to second surface100b, a second barrier layer301and a second channel layer302.

As an example and according to the present disclosure, a barrier layer may comprise an AlxGa1-xN ternary alloy while a channel layer may comprise GaN.

Further, a barrier layer may have a thickness in the range from 1 nm to 100 nm.

A channel layer may have a thickness in the range from 10 nm to 2 μm.

The first and the second stack may mirror one another, e.g., may be essentially identical in material and structural configurations.

A stack of semiconductor layers, according to the terms of the present disclosure, is capable of forming a two-dimensional electron gas (2DEG) which forms a conduction layer or region.

The conduction layer, within a stack, extends in the channel layer, from the interface formed between the barrier layer and the channel layer of the considered stack. The conduction layer is in some implementations likely to be formed within a HEMT transistor when the latter is in a conductive state.

Thus, when first transistor200is in the conductive state, first channel layer202is capable of forming a first conduction layer203, which extends in said first channel layer202, from a first interface formed between first barrier layer201and first channel layer202.

When second transistor300is in the conductive state, second channel layer302is capable of forming a second conduction layer303, which extends in said second channel layer302, from a second interface formed between second barrier layer301and second channel layer302.

Each HEMT transistor comprises a set of electrodes including a source electrode, a drain electrode, and a gate electrode.

In some implementations, first transistor200comprises one of the two sets of electrodes referred to as first set. The first set includes a first source electrode204, with a first drain electrode205, and with a first gate electrode206.

The second transistor300comprises the other one of the two sets of electrodes, referred to as second set. The second set includes a second source electrode304, with a second drain electrode305, and with a second gate electrode306.

First source electrode204and first drain electrode205extend from insulating layer400to the first stack. In some implementations, first drain electrode205and first source electrode204partly cross the first stack and partly cross first channel layer202. Thus, one and the other of the first drain electrode205and of the first source electrode204electrically contact first channel layer202and contact in some implementations first conduction layer203in the first channel layer202.

In some implementations, first drain electrode205emerges at the level of first surface100a. In this respect, the device may comprise a pad, referred to as first drain pad207, resting on the first surface and in contact with the first drain electrode. This first drain pad207forms a first terminal of device100. The first drain pad in some implementations comprises a doped semiconductor material, for example, doped silicon.

Second source electrode304and second drain electrode305extend from insulating layer400to the second stack. In some implementations, second drain electrode305and second source electrode304partly cross the second stack and in some implementations partly cross the second channel layer302. Thus, one and the other of second drain electrode305and of second source electrode304electrically contact second channel layer302and in some implementations contacts second conduction layer303.

In some implementations, second drain electrode305emerges at the level of second surface100a. In this respect, the device may comprise another pad, referred to as second drain pad307, resting on the second surface and in contact with the second drain electrode. This second drain pad307forms a second terminal of the device. The second drain pad in some implementations comprises a doped semiconductor material, for example, doped silicon.

According to the present disclosure, first transistor200and second transistor300are connected head-to-tail. In some implementations, first drain electrode205electrically contacts second source electrode304, while first source electrode204electrically contacts second drain electrode305.

According to an embodiment of the present disclosure, the electric contact between a source electrode and a drain electrode is direct. “Direct contact” is used to refer to that two electrodes are at the same electric potential. In some implementations, the source electrode of the first set is one and the same as the drain electrode of the second set, and the drain electrode of the first set is one and the same as the source electrode of the second set.

First gate electrode206and second gate electrode306each extend along a direction perpendicular to the first surface and in insulating layer400. In some implementations, first gate electrode206on the one hand and second gate electrode306on the other hand remain distant at the level of an active area ZA (FIG.3andFIG.4) of the device, respectively, of the first stack and of the second stack.

First gate electrode206and second gate electrode306enable to control the conductive or non-conductive state, respectively, of the first transistor and of the second transistor.

In some implementations, this control is executed by imposing an electric potential Vg to the gate electrode, and in some implementations an electric potential difference DDP, noted Vg-Vs between the gate electrode and the source electrode of the considered HEMT transistor.

Thus, when Vg-Vs is greater than a threshold voltage Vth characteristic of each of the HEMT transistors, the latter is in the conductive state. Conversely, when Vg-Vs is smaller than Vth, the HEMT transistor is in the non-conductive state, and thus behaves as an off switch.

Thus, depending on the value of threshold voltage Vth, and in some implementations on its sign, an HEMT transistor may be in depletion (normally-on) mode if its threshold voltage Vth is negative, or in enhancement (normally-off) mode if its threshold voltage Vth is positive.

Thus, the HEMT transistors likely to be considered in the present disclosure may be either of normally-on or depletion type (depletion mode high electron mobility transistor) or of normally-off or enhancement type (enhancement mode high electron mobility transistor).

Device100also comprises a first gate pad208and a second gate pad308arranged, respectively, on first surface100aand on second surface100b. First gate pad208is configured to electrically contact first gate electrode206. The electric contact is however offset from active area ZA (such as shown inFIG.3and inFIG.4). Second gate pad308is configured to electrically contact second gate electrode306. The electric contact is also offset from active area ZA.

“Offset” is used to designate a gate pad, which is arranged outside of an active area ZA of one and the other of the first and of the second transistor. In this respect,FIG.4is a representation of device100according to a view from the first surface (along a plan parallel to the (0, x, y) plane). The dotted lines delimit active area ZA within which any contact between a gate electrode and one and the other of the barrier and channel layers is avoided.

Thus, it is possible to independently control the state of one and the other of the two HEMT transistors.

In some implementations, the control of first transistor200may be executed by applying a gate potential to first gate pad208to impose a conductive state or a non-conductive state to said first transistor200.

The control of second transistor300may be executed by applying a gate potential to second gate pad308to impose a conductive state or a non-conductive state to said second transistor300.

Thus, when the first transistor is in the conductive state and the second transistor is in the non-conductive state, only the first transistor is likely to conduct a current. This current in some implementations flows, in a first direction (symbolized by the arrowed line inFIG.5), from first drain electrode205to second drain electrode305via first conduction layer203.

When the second transistor is in the conductive state and the first transistor is in the non-conductive state, only the second transistor is likely to conduct a current. This current in some implementations flows, in a second direction opposite to the first direction (symbolized by the arrowed line inFIG.6), from second drain electrode305to first drain electrode205via second conduction layer303.

The device100according to this embodiment due to the considered stacks and to the arrangement of the first and second sets remains relatively compact. Further, the head-to-tail connection of the first transistor to the second transistor enables to form a bidirectional device.

According to an embodiment, the first drain electrode and the second drain electrode form the terminals of device100. However, and according to another embodiment, it could have been considered to form these terminals with the first source electrode and the second source electrode, which would respectively emerge onto the first surface and the second surface.

Still in the context of this embodiment, instead of forming drain pads, it could have been considered to form source pads, and in some implementations a first source pad on the first surface and a second source pad on the second surface.

According to this configuration, the first source pad and the second source pad would be in contact, respectively, with the first source electrode and the second source electrode.

According to an embodiment, it could have been considered to form a first terminal with the source electrode of one of the two HEMT transistors and a second terminal with the source electrode of the other one of the two HEMT transistors.

The disclosure also concerns an embodiment which mostly uses all the terms of the other embodiments described herein.

According to the embodiment illustrated inFIG.7, the device comprises two diodes respectively referred to as first diode D1and second diode D2.

First diode D1is interposed between the source electrode204of the first set and the drain electrode305of the second set, while the second diode is interposed between the drain electrode of the first set and the source electrode of the second set.

Further, first diode D1is arranged (or biased) to allow the flowing of a current in the first transistor from the first terminal to the second terminal. Equivalently, second diode D2is arranged (or biased) to allow the flowing of a current in the second transistor from the second terminal to the first terminal.

The implementation of the first and of the second diode in some implementations enables to protect one and the other of the two source electrodes when the device is implemented for high-voltage applications, and in some implementations exceeding 600 V.

Diodes D1and D2in some implementations enable to prevent the biasing of one and the other of the two source electrodes when the device is submitted to a high voltage.

Diodes D1and D2in some implementations each comprise a Schottky diode.

As shown inFIG.8, the anode, referred to as first anode A1, and the cathode, referred to as first cathode C1, of first diode D1, are connected, respectively, to the source electrode of the first set and to the drain electrode of the second set.

The anode, referred to as second anode A2, and the cathode, referred to as second cathode C2, of second diode D2, are respectively connected to the source electrode of the second set and to the drain electrode of the first set.

In some implementations, first diode D1and second diode D2are respectively formed in the first stack and the second stack (FIG.8).

In some implementations, the cathode C2of the second diode extends in insulating layer400and in the second stack. Further, cathode C2electrically contacts the first drain electrode in the insulating layer. Cathode C2and the first drain electrode are in some implementations one and the same.

The cathode C1of the first diode extends in insulating layer400and in the first stack. Further, cathode C1electrically contacts the second drain electrode in the insulating layer. Cathode C1and the second drain electrode are in some implementations one and the same.

The anode A1of the first diode, arranged in the vicinity of cathode C1, extends in the insulating layer and in the first stack. A first interconnection I1, arranged in the insulating layer, enables to connect anode A1to the first source electrode.

The anode A2of the second diode, arranged in the vicinity of cathode C2, extends in the insulating layer and in the second stack. A second interconnection I2, arranged in the insulating layer, enables to connect anode A2to the second source electrode.

This architecture enables to obtain a compact device100and capable of “withstanding” high voltages and in some implementations greater than 600 Volts.

The device100according to the present disclosure may in some implementations be implemented in voltage converters, and in some implementations high-voltage converters.

Of course, the disclosure is not limited to the described embodiments and alternative embodiments may be brought thereto without departing from the framework of the disclosure such as defined by the claims.

Device (100) may be summarized as including a stack of two high electron mobility transistors, referred to as first (200) and second (300) transistor, separated by an insulating layer (400) and each provided with a stack of semiconductor layers respectively referred to as first stack and second stack, the first and the second stack each including, from the insulating layer (400) to, respectively, a first (100a) and a second surface (100b), a barrier layer (201,301) and a channel layer (202,302), the first (200) and the second (300) transistor respectively including a first set of electrodes and a second set of electrodes, the first and the second set of electrodes each including a source electrode (204,304), a drain electrode (205,305), and a gate electrode (206,306) which are arranged so that the first (200) and the second (300) transistor are electrically connected head-to-tail.

Said device (100) may include two terminals respectively referred to as first terminal and second terminal, the first terminal being in electric contact with one of the drain electrode (205) of the first set and of the source electrode (304) of the second set, and the second terminal being in electric contact with one of the drain electrode (305) of the second set and of the source electrode (204) of the first set.

The first terminal may include a first pad resting on one or the other of the first surface (100a) and of the second surface (100b), and the second terminal may include a second pad resting on one or the other of the first and of the second surface.

The gate electrode (206) of the first set and the gate electrode (306) of the second set may be arranged to control the switching, respectively of the first transistor (200) and of the second transistor (300), from one of a conductive state and of a non-conductive state to the other one of these two states.

The channel layer (202) of the first transistor (200), when the latter is in a conductive state, may be capable of forming a conduction layer, referred to as first conduction layer (203), and wherein a current is likely to flow from the first terminal to the second terminal, and the channel layer (302) of the second transistor, when the latter is in a conductive state, may be capable of forming a conduction layer, referred to as second conduction layer (303), and where a current is likely to flow from the second terminal to the first terminal.

The head-to-tail electric connection of the first and of the second transistor may include a connection of the drain electrode (205) of the first set to the source electrode (304) of the second set and of the source electrode (204) of the first set to the drain electrode (305) of the second set.

The connection between the drain electrode (205) of the first set and the source electrode (304) of the second set may be direct so that each of these two electrodes is at the same electric potential, and the connection between the source electrode (204) of the first set and the drain electrode (305) of the second set may be direct so that each of these two electrodes is at the same electric potential.

The source electrode (204) of the first set may be one and the same as the drain electrode (305) of the second set, and the drain electrode (205) of the first set may be one and the same as the source electrode (304) of the second set.

A diode, referred to as first diode (D1), may be interposed between the source electrode (204) of the first set and the drain electrode (305) of the second set, said first diode (D1) being arranged to allow the flowing of a current from the first terminal to the second terminal, and another diode, referred to as second diode (D2), may be interposed between the drain electrode (205) of the first set and the source electrode (304) of the second set, said second diode (D2) being arranged to allow the flowing of a current from the second terminal to the first terminal.

The first diode (D1) and the second diode (D2) may be formed, respectively, in the first stack and the second stack.

The insulating layer (400) may include a dielectric material, in some implementations silicon dioxide or silicon nitride.

Said device (100) may include two pads, referred to as first gate pad (208) and second gate pad (308), respectively arranged on the first surface (100a) and the second surface (100b), the first gate pad (208) electrically contacting the gate electrode (206) of the first set and the second gate pad (308) electrically contacting the gate electrode (306) of the second set.

The first and the second stack may be essentially identical.

The first (200) and the second (300) transistor may have an identical threshold voltage.

The two channel layers (202,302) may include GaN and the barrier layers may include an AlGaN ternary alloy.

The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various embodiments to provide yet further embodiments.

These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.