Patent ID: 12193152

BEST MODE

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

However, spirit and scope of the present invention is not limited to a part of the embodiments described, and may be implemented in various other forms, and within the spirit and scope of the present invention, one or more of the elements of the embodiments may be selectively combined and substituted for use.

In addition, unless expressly otherwise defined and described, the terms used in the embodiments of the present invention (including technical and scientific terms may be construed the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, and the terms such as those defined in commonly used dictionaries may be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art. Further, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention.

In this specification, the singular forms may also include the plural forms unless specifically stated in the phrase, and may include at least one of all combinations that may be combined in A, B, and C when described in “at least one (or more) of A (and), B, and C”. Further, in describing the elements of the embodiments of the present invention, the terms such as first, second, A, B, (a), and (b) may be used.

These terms are only used to distinguish the elements from other elements, and the terms are not limited to the essence, order, or order of the elements. In addition, when an element is described as being “connected”, “coupled”, or “contacted” to another element, it may include not only when the element is directly “connected” to, “coupled” to, or “contacted” to other elements, but also when the element is “connected”, “coupled”, or “contacted” by another element between the element and other elements.

In addition, when described as being formed or disposed “on (over)” or “under (below)” of each element, the “on (over)” or “under (below)” may include not only when two elements are directly connected to each other, but also when one or more other elements are formed or disposed between two elements. Further, when expressed as “on (over)” or “under (below)”, it may include not only the upper direction but also the lower direction based on one element.

FIG.1is a view showing a circuit board according to an embodiment.

Before describing of the present invention, recently, 5G technology has been developed, and accordingly, interest in circuit boards that can reflect it is increasing. At this time, the circuit board must have a high multi-layer structure in order to apply the 5G technology, and accordingly the circuit pattern must be miniaturized. However, although a comparative example makes it possible to form a fine pattern, there is a problem in that it cannot be stably protected. For example, a circuit pattern applied to a circuit board for 5G has a narrow line width, and accordingly, an interval between the patterns is narrowed. However, although the prior art can form a fine pattern, it cannot be suppressed when migration of a metal material constituting the fine pattern occurs, and thus there is a reliability problem. Accordingly, the embodiment provides a circuit board having a new structure that can solve the reliability problem.

Specifically, referring toFIG.1, the circuit board includes an insulating layer140, a first circuit pattern130, a first barrier layer120and130, a second circuit pattern160, and a second barrier layer150and170, a first protective layer180, and a second protective layer185.

Before describing ofFIG.1, a circuit board according to an embodiment may have a multilayer structure based on an insulating layer. That is, although the circuit board inFIG.1is illustrated as including a single insulating layer, the embodiment is not limited thereto. For example, the circuit board in the embodiment may include a plurality of insulating layers. For example, the insulating layer140ofFIG.1may represent a first outermost insulating layer among a plurality of insulating layers, and the first circuit pattern130may represent a first outer layer circuit pattern protruding on the first outermost insulating layer. For example, the insulating layer140ofFIG.1may represent a second outermost insulating layer among a plurality of insulating layers, and the second circuit pattern160may represent a second outer layer circuit pattern buried in the second outermost insulating layer.

The insulating layer140may represent any one specific layer in a plurality of stacked structures. The insulating layer140is a substrate on which an electric circuit capable of changing wiring is formed, and may include a printed circuit board, a wiring board, and an insulating substrate made of an insulating material capable of forming circuit patterns on a surface.

For example, the insulating layer140may be rigid or flexible. For example, the insulating layer140may include glass or plastic. Specifically, the insulating layer140may include a chemically tempered/semi-tempered glass, such as soda lime glass, aluminosilicate glass, etc., a tempered or flexible plastic such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), etc., or sapphire.

In addition, the insulating layer140may include an optically isotropic film. As an example, the insulating layer140may include cyclic olefin copolymer (COC), cyclic olefin polymer (COP), optically isotropic PC, optically isotropic polymethylmethacrylate (PMMA), or the like.

In addition, the insulating layer140may be partially bent while having a curved surface. That is, the insulating layer140may partially have a plane and may partially be bent while having a curved surface. Specifically, an end portion of the insulating layer140may be bent while having a curved surface, or bent or crooked while having a surface with a random curvature. Accordingly, the circuit board in the embodiment is applicable to electronic devices having various shapes.

In addition, the insulating layer140may be a flexible substrate having flexibility. Further, the insulating layer140may be a curved or bent substrate. At this point, the insulating layer140123may form a wiring layout for electrical wirings which connect circuit components based on a circuit design, and electrical conductors may be disposed on an insulating material. Further, electrical components may be mounted on the insulating layer140may form wirings configured to connect the electrical components to make a circuit, and may mechanically fix the components besides functioning to electrically connect the components.

A circuit pattern may be disposed on a surface of the insulating layer140.

For example, a first circuit pattern130may be disposed under a lower surface of the insulating layer140.

In addition, a second circuit pattern160may be disposed on an upper surface of the insulating layer140.

The first circuit pattern130may be formed by being buried in a lower portion of the insulating layer140. A side surface of the first circuit pattern130may be surrounded by the insulating layer140. However, the side surface of the first circuit pattern130may not contact the insulating layer140. That is, a first-second portion120of a first barrier layer may be positioned between the side surface of the first circuit pattern130and the insulating layer140. Accordingly, the side surface of the first circuit pattern130may be spaced apart from the insulating layer140by a thickness of the first-second portion120of the first barrier layer.

In addition, an upper surface of the first circuit pattern130may be portioned in the insulating layer140. Specifically, the upper surface of the first circuit pattern130may be positioned higher than a lower surface of the insulating layer140. Meanwhile, the upper surface of the first circuit pattern130may not contact the insulating layer140. That is, a first-second portion120of the first barrier layer may be positioned between the upper surface of the first circuit pattern130and the insulating layer140. Accordingly, the upper surface of the first circuit pattern130may be spaced apart from the insulating layer140by a thickness of the first-second portion120of the first barrier layer.

A lower surface of the first circuit pattern130may be positioned on the same plane as a lower surface of the insulating layer140.

As described above, upper, lower and side surfaces of the first circuit pattern130do not contact the insulating layer140. Accordingly, the embodiment can solve the problem that the metal material constituting the first circuit pattern130migrates to the insulating layer140.

That is, although the first circuit pattern130is buried in a lower portion of the insulating layer140, it may not be in direct contact with the insulating layer140by the first-second portion120of the first barrier layer. That is, the first-second portion120of the first barrier layer may be positioned between the side and upper surfaces of the first circuit pattern130and the insulating layer140. Accordingly, the side surface and the upper surface of the first circuit pattern130may be spaced apart from the insulating layer140by a thickness of the first-second portion120of the first barrier layer.

The second circuit pattern160is disposed to protrude on an upper surface of the insulating layer140. In this case, the second circuit pattern160may not contact the insulating layer140. That is, a lower surface of the second circuit pattern160may be spaced apart from the upper surface of the insulating layer140by a predetermined interval. That is, a lower surface of the second circuit pattern160may be positioned higher than the upper surface of the insulating layer140. Specifically, a second-first portion150of the second barrier layer may be positioned between a lower surface of the first circuit pattern130and an upper surface of the insulating layer140. Accordingly, the lower surface of the second circuit pattern160may be spaced apart from the insulating layer140by a thickness of the second-first portion150of the second barrier layer.

That is, although the second circuit pattern160is disposed on the upper surface of the insulating layer140, it may not directly contact the insulating layer140by the second-first portion150of the second barrier layer. That is, the second-first portion150of the second barrier layer may be positioned between the lower surface of the second circuit pattern160and the upper surface of the insulating layer140. Accordingly, the lower surface of the second circuit pattern160may be spaced apart from the insulating layer140by a thickness of the first portion of the second barrier layer.

The first circuit pattern130and the second circuit pattern160as described above are wires for transmitting electrical signals, and may be formed of a metal material having high electrical conductivity. Preferably, the first circuit pattern130and the second circuit pattern160may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

In addition, migration in which copper ions penetrate into the insulating layer140may occur by forming the first circuit pattern130and the second circuit pattern160of copper. In this case, a first barrier layer is disposed between the first circuit pattern130and the insulating layer140in the embodiment. In addition, a second barrier layer is disposed between the second circuit pattern160and the insulating layer140in the embodiment. Accordingly, the embodiment can prevent migration of the copper ions from penetrating into the insulating layer140, thereby improving the reliability of the fine pattern.

Meanwhile, a first protective layer180is disposed under a lower surface of the insulating layer140. In addition, a second protective layer185is disposed on an upper surface of the insulating layer140.

The first protective layer180and the second protective layer182may be formed of at least one layer using any one or more of Solder Resist (SR), oxide, and Au. Preferably, the first protective layer180and the second protective layer185may be solder resist.

The first protective layer180may be disposed under a lower surface of the insulating layer140to protect the first circuit pattern130.

For example, the first protective layer180may protect a lower surface of the first circuit pattern130. In this case, the first protective layer180may not directly contact the first circuit pattern130.

The second protective layer185may be disposed to cover the second circuit pattern160. That is, a side surface of the second circuit pattern160may be surrounded by the second protective layer185. However, the side surface of the second circuit pattern160may not contact the second protective layer185. That is, a second-second portion170of the second barrier layer may be positioned between the side surface of the second circuit pattern160and the second protective layer185. Accordingly, the side surface of the second circuit pattern160may be spaced apart from the second protective layer185by a thickness of the second-second portion170of the second barrier layer.

In addition, at least a portion of an upper side of the second circuit pattern160may be covered by the second protective layer185. That is, an upper surface of the second circuit pattern160may be positioned lower than an upper surface of the second protective layer185. In this case, the upper surface of the second circuit pattern160may not contact the second protective layer185. That is, a second-second portion170of the second barrier layer may be positioned between the upper surface of the second circuit pattern160and the second protective layer185. Accordingly, the upper surface of the second circuit pattern160may be spaced apart from the second protective layer185by a thickness of the second-second second portion170of the second barrier layer.

A lower surface of the second circuit pattern160may be positioned higher than the upper surface of the insulating layer140and higher than a lower surface of the second protective layer185.

As described above, upper, lower and side surfaces of the second circuit pattern160do not contact the insulating layer140and the second protective layer185. Accordingly, the embodiment may solve the problem that copper ions constituting the second circuit pattern160migrate to the second protective layer185.

That is, the second circuit pattern160protrudes on the upper surface of the insulating layer140and is covered by the second protective layer185. However, the second circuit pattern160may not directly contact the second protective layer185by the second-second portion170of the second barrier layer. That is, the second-second portion170of the second barrier layer may be positioned between the side and upper surfaces of the second circuit pattern160and the second passivation layer185. Accordingly, the side surface and the upper surface of the second circuit pattern160may be spaced apart from the second protective layer185by a thickness of the second-second portion170of the second barrier layer.

Hereinafter, the first barrier layer and the second barrier layer will be described.

The first barrier layer may be disposed between the first circuit pattern130and the insulating layer140. Also, the first barrier layer may be disposed between the first circuit pattern130and the first protective layer180.

Specifically, the first barrier layer includes a first-first portion110disposed between the first circuit pattern130and the first protective layer180. In addition, the first barrier layer includes a first-second portion120disposed between the first circuit pattern130and the insulating layer140.

Each of the first-first portion110and the first-second portion120of the first barrier layer may include a plurality of layers.

That is, the first-first portion110of the first barrier layer includes a first-first metal layer111. The first-first metal layer111may be formed of a metal material including palladium (Pd). The first-first metal layer111may function to prevent copper ions constituting the first circuit pattern130from migrating to the first protective layer180.

In addition, the first-first portion110of the first barrier layer includes a first-second metal layer112disposed between a lower surface of the first circuit pattern130and the first-first metal layer111. The first-second metal layer112may be a seed layer of the first-first metal layer111. In addition, the first-second metal layer112may function to primarily block the migration of copper ions constituting the first circuit pattern130. Accordingly, the first-second metal layer112in the embodiment is formed between the first circuit pattern130and the first-first metal layer111using gold (Au) having a relatively large grain size. In this case, the first-first metal layer111may be referred to as a first-first palladium layer. Also, the first-second metal layer112may be referred to as a first-first gold layer.

The first-second metal layer112may be disposed under a lower surface of the first circuit pattern130to have a first width. In this case, the first width of the first-second metal layer112may be greater than a second width of a lower surface of the first circuit pattern130. Accordingly, the first circuit pattern130may not contact the first protective layer180.

The first-first metal layer111may be disposed under the lower surface of the first-second metal layer112to have the same first width as the first-second metal layer112.

That is, the first-second portion120of the first barrier layer includes the second-first metal layer121. The second-first metal layer121may be formed of a metal material including palladium (Pd). The second-first metal layer111may function to prevent copper ions constituting the first circuit pattern130from migrating to the insulating layer140.

In addition, the first-second portion120of the first barrier layer includes a second-second metal layer122disposed between side and upper surfaces of the first circuit pattern130and the second-first metal layer121. The second-second metal layer122may be a seed layer of the second-first metal layer121.

Accordingly, the second-second metal layer122in the embodiment made of a metal including gold (Au) having a relatively large grain size is formed on the side surface and the upper surface of the first circuit pattern130. The second-first metal layer121may be formed by plating the second-second metal layer122as a seed layer. In this case, the second-first metal layer121may be referred to as a first-second palladium layer. In addition, the second-second metal layer122may be referred to as a first-second gold layer.

The second-second metal layer122may be disposed to surround side surfaces and upper surfaces of the first circuit pattern130. Also, the second-first metal layer121may be disposed to surround the second-second metal layer122.

Meanwhile, an upper surface of the first-second metal layer112may include a first region in contact with a lower surface of the first circuit pattern130. In addition, an upper surface of the first-second metal layer112may include a second region in contact with the second-first metal layer121. In addition, an upper surface of the first-second metal layer112may include a third region in contact with the second-second metal layer122. Accordingly, the first-first metal layer111of the embodiment may not contact the first circuit pattern130, the second-first metal layer121, and the second-second metal layer122.

A second barrier layer may be disposed between the second circuit pattern160and the insulating layer140. Also, the second barrier layer may be disposed between the second circuit pattern160and the second protective layer185.

Specifically, the second barrier layer includes a second-first portion150disposed between the second circuit pattern160and the insulating layer140. In addition, the second barrier layer includes a second-second portion170disposed between the second circuit pattern160and the second protective layer185.

Each of the second-first portion150and the second-second portion170of the second barrier layer may include a plurality of layers.

That is, the second-first portion150of the second barrier layer includes a third-first metal layer151. The third-first metal layer151may be formed of a metal material including palladium (Pd). The third-first metal layer151may function to prevent copper ions constituting the second circuit pattern160from migrating to the insulating layer140.

In addition, the second-first portion150of the second barrier layer includes a third-second metal layer152disposed between a lower surface of the second circuit pattern160and the third-first metal layer151. The third-second metal layer152may be a seed layer of the third-first metal layer151. Accordingly, the third-second metal layer152of the embodiment includes gold (Au) having a relatively large grain size and is formed on the lower surface of the second circuit pattern160. In addition, the third-first metal layer151may be formed by plating the third-second metal layer152as a seed layer. In this case, the third-first metal layer151may be referred to as a second-first palladium layer. In addition, the third-second metal layer152may be referred to as a second-first gold layer.

The third-second metal layer152may be disposed under a lower surface of the second circuit pattern160to have a first width. In this case, the first width of the third-second metal layer152may be greater than a second width of a lower surface of the second circuit pattern160. Accordingly, the second circuit pattern160may not contact the insulating layer140.

The third-first metal layer151may be disposed under the lower surface of the third-second metal layer152to have the same first width as the third-second metal layer152.

That is, the second-second portion170of the second barrier layer includes a fourth-first metal layer171. The fourth-first metal layer171may be formed of a metal material including palladium (Pd). The second-first metal layer111may function to prevent copper ions constituting the second circuit pattern160from migrating to the second protective layer185.

In addition, the second-second portion170of the second barrier layer includes a fourth-second metal layer172disposed between side and upper surfaces of the second circuit pattern160and the fourth-first metal layer171. The fourth-second metal layer172may be a seed layer of the fourth-first metal layer171. In the embodiment, a fourth-second metal layer172of the embodiment includes gold (Au) having a relatively large grain size and is formed on side and upper surfaces of the second circuit pattern160. In addition, fourth-first metal layer171may be formed by plating the fourth-second metal layer172as a seed layer. In this case, the fourth-first metal layer171may be referred to as a second-second palladium layer. In addition, the fourth-second metal layer172may be referred to as a second-second gold layer.

The fourth-second metal layer172may be disposed to surround side and upper surfaces of the second circuit pattern160. Also, the fourth-first metal layer171may be disposed to surround the fourth-second metal layer172.

Meanwhile, an upper surface of the third-second metal layer152may include a first region in contact with a lower surface of the second circuit pattern160. In addition, an upper surface of the third-second metal layer152may include a second region in contact with the fourth-first metal layer171. In addition, the upper surface of the third-second metal layer152may include a third region in contact with the fourth-second metal layer172. Accordingly, the third-first metal layer151of the embodiment may not contact the second circuit pattern160, the fourth-first metal layer171, and the fourth-second metal layer172.

The embodiment such as the above provides a circuit board including an insulating layer and a circuit pattern. In this case, the circuit pattern is formed of a metal material including copper. In this case, the circuit pattern formed of the metal material including copper does not directly contact the insulating layer. To this end, a barrier layer is disposed around the circuit pattern. For example, the embodiment includes a gold metal layer disposed around the circuit pattern and containing gold (Au), and a palladium metal layer disposed around the gold metal layer and including palladium (Pd). The palladium metal layer may prevent copper constituting the circuit pattern from penetrating toward the insulating layer, and accordingly, it is possible to improve reliability by suppressing the occurrence of copper migration. In addition, the gold metal layer is disposed between the palladium metal layer and the circuit pattern to form the palladium metal layer. In this case, the gold metal layer includes gold (Au) having a larger grain size than other layers, and thus the palladium metal layer can be stably formed.

In addition, the barrier layer in the embodiment is also formed on a circuit pattern disposed on an outermost layer among the circuit patterns. This may prevent migration of copper constituting the circuit pattern of the outermost layer to a solder resist.

In addition, a portion of the barrier layer is disposed on a surface of a buried pattern in the ETS (Embedded Trace Substrate) structure of the embodiment. In this case, the barrier layer is disposed to protrude on the surface of the buried pattern, and this may function as a mounting pad on which a solder layer for mounting a device is disposed. That is, a buried pattern of a conventional ETS structure is formed in a fine pattern, as a result, it was not possible to function as a mounting pad only with a simple pattern, and accordingly, a separate mounting pad having a structure that is buried in the insulating layer or protrudes above the surface of the insulating layer has to be formed. At this time, when the mounting pad is buried in the insulating layer, an interval between the fine patterns is widened by a width of the mounting pad, and thus there is a problem in circuit integration. In addition, when a structure in which the mounting pad protrudes on the insulating layer is applied, it was necessary to proceed with a separate process to form it. On the other hand, when forming the barrier layer on the buried pattern, the embodiment allows a portion of the barrier layer to have a structure protruding on a surface of the insulating layer, and accordingly, the barrier layer can be used as a mounting pad, thereby simplifying the manufacturing process.

FIG.2is a view showing a circuit board including a via according to an exemplary embodiment.

Meanwhile, although only the circuit pattern has been described inFIG.1, a circuit board100A according to the embodiment may include a via190disposed in the insulating layer140.

Referring toFIG.2, a via190may be formed to pass through the insulating layer140. Specifically, the via190may electrically connect between the first circuit pattern130and the second circuit pattern160. In this case, the via190may be formed of a metal material including copper. Accordingly, copper ions constituting the via190may migrate to the insulating layer140. Accordingly, the via190in the embodiment may have a three-layer structure in a horizontal direction. That is, the via190may be formed by plating a metal material in a via hole (not shown) passing through the insulating layer140.

At this time, when the via hole is formed, a fifth-first metal layer191of the embodiment is preferentially formed on an inner wall of the via hole. The fifth-first metal layer191may be formed of a metal including palladium.

In addition, the via190may include a fifth-second metal layer192formed on an inner surface of the fifth-first metal layer191. The fifth-second metal layer192may include gold.

Also, the via190may include a fifth-third metal layer193. The fifth-third metal layer193may include copper. The fifth-third metal layer193may be formed to fill an inside of the via hole. That is, the via hole of the embodiment are not all filled by the fifth-third metal layer193, the fifth-third metal layer193is formed after the fifth-first metal layer191and the fifth-second metal layer192are formed. Accordingly, it is possible to prevent migration of copper ions constituting the fifth-third metal layer193to the insulating layer140.

Hereinafter, a method of manufacturing a circuit board according to an embodiment will be described.FIGS.3to15are views showing the manufacturing method of the circuit board shown inFIG.1in order of process.

Referring toFIG.3, a carrier board210serving as a basic material is prepared for manufacturing a circuit board. The carrier board210may include an insulating member211and a metal layer212disposed on the insulating member211.

In this case, although it is illustrated that the metal layer212is disposed only on one surface of the insulating member211in the drawing, the embodiment is not limited thereto. That is, the metal layer212may be disposed on both sides of the insulating member211, and accordingly, a plurality of circuit boards may be simultaneously manufactured on both sides of the insulating member211.

Next, referring toFIG.4, a first-first portion110constituting a first barrier layer is formed on the carrier board210.

That is, the first-first portion110of the first barrier layer may include a first-first metal layer111disposed on the carrier board210and a first-second metal layer112disposed on the first-first metal layer111.

The first-first metal layer111may include palladium. In addition, the first-second metal layer112may include gold. The first-first metal layer111and the first-second metal layer112may be formed through a chemical copper plating process.

Next, referring toFIG.5, a first mask M1of the embodiment is formed on the first-first portion110of the first barrier layer. The first mask M1may include an opening (not shown) exposing a region where the first circuit pattern130is to be formed.

In addition, a first circuit pattern130filling an opening of the first mask M1of the embodiment is formed by plating a first portion of the first barrier layer as a seed layer.

Next, referring toFIG.6, the first mask M1is removed, and a second mask M2is formed on the first-first portion110of the first barrier layer. The second mask M2may include an opening (not shown) exposing a region in which the second-second metal layer122is to be formed among the first-second portion120of the first barrier layer.

Then, a second-second metal layer122filling the opening of the second mask M2of the embodiment is formed by plating the first-first portion110of the first barrier layer as a seed layer.

Next, referring toFIG.7, the second mask M2is removed, and a third mask M3is formed on the first-first portion110of the first barrier layer. The third mask M3may include an opening (not shown) exposing a region in which the second-first metal layer121is to be formed among the first-second portion120of the first barrier layer.

Then, a second-first metal layer121filling the opening of the third mask M3of the embodiment is formed by plating the first-first portion110of the first barrier layer as a seed layer.

Next, referring toFIG.8, an insulating layer140covering the first circuit pattern130is formed on the first barrier layer.

Next, referring toFIG.9, a second-first portion150constituting a second barrier layer is formed on the insulating layer140.

That is, the second-first portion150of the second barrier layer includes a third-first metal layer151disposed on the insulating layer140and a third-second metal layer152disposed on the third-first metal layer151.

The third-first metal layer151may include palladium. Also, the third-second metal layer152may include gold. The third-first metal layer151and the third-second metal layer152may be formed through a chemical copper plating process.

Next, referring toFIG.10, a second circuit pattern160is formed on the second-first portion150of the second barrier layer, and a second-second portion170of the second barrier layer is formed on the second circuit pattern160by sequentially re-performing the processes ofFIGS.5to7. A second-second portion170of the second barrier layer includes a fourth-first metal layer171and a four-second metal layer172.

Next, referring toFIG.11, a process of removing a part of the second-first portion150of the second barrier layer may be performed.

Next, referring toFIG.12, a process of removing the carrier board210may be performed.

Next, referring toFIG.13, a process of removing a part of the first-first portion110of the first barrier layer may be performed.

Next, referring toFIG.14, a process of forming the first protective layer180on the lower surface of the insulating layer140and forming the second protective layer185on the upper surface of the insulating layer140may be performed.

That is, the first protective layer180is disposed under the lower surface of the insulating layer140. In addition, the second protective layer185is disposed on the upper surface of the insulating layer140.

The first protective layer180and the second protective layer182may be formed of at least one layer using any one or more of Solder Resist (SR), oxide, and Au. Preferably, the first protective layer180and the second protective layer185may be solder resist.

Meanwhile, referring toFIG.15, the first protective layer180A according to another embodiment may include an opening (not shown) exposing a part of the first-first portion110of the first barrier layer.

Also, the second protective layer185A according to another exemplary embodiment may include an opening exposing a part of the second-second portion170of the second barrier layer.

Accordingly, a first barrier layer surrounding the first circuit pattern130and a second barrier layer surrounding the second circuit pattern160in the embodiment may be formed.

Features, structures, effects, etc. described in the above embodiments are included in at least one embodiment, and it is not necessarily limited to only one embodiment. Furthermore, features, structures, effects, etc. illustrated in each embodiment can be combined or modified for other embodiments by those of ordinary skill in the art to which the embodiments belong. Accordingly, the contents related to such combinations and variations should be interpreted as being included in the scope of the embodiments.

In the above, the embodiment has been mainly described, but this is only an example and does not limit the embodiment, and those of ordinary skill in the art to which the embodiment pertains will appreciate that various modifications and applications not illustrated above are possible without departing from the essential characteristics of the present embodiment. For example, each component specifically shown in the embodiment can be implemented by modification. And the differences related to these modifications and applications should be interpreted as being included in the scope of the embodiments set forth in the appended claims.