Patent ID: 12261117

DESCRIPTION OF THE EMBODIMENTS

With reference to the Drawings, first and second embodiments of the present invention will be described below. In the Drawings, the same or similar elements are indicated by the same or similar reference numerals. The Drawings are schematic, and it should be noted that the relationship between thickness and planer dimensions, the thickness proportion of each layer, and the like are different from real ones. Accordingly, specific thicknesses or dimensions should be determined with reference to the following description. Moreover, in some drawings, portions are illustrated with different dimensional relationships and proportions. The embodiments described below merely illustrate schematically devices and methods for specifying and giving shapes to the technical idea of the present invention, and the span of the technical idea is not limited to materials, shapes, structures, and relative positions of elements described herein.

Further, definitions of directions such as an up-and-down direction in the following description are merely definitions for convenience of understanding, and are not intended to limit the technical ideas of the present invention. For example, as a matter of course, when the subject is observed while being rotated by 90°, the subject is understood by converting the up-and-down direction into the right-and-left direction. When the subject is observed while being rotated by 180°, the subject is understood by inverting the up-and-down direction.

First Embodiment

<Configuration of Semiconductor Device>

A semiconductor device according to a first embodiment of the present invention is illustrated below with a high voltage integrated circuit (referred to below as a “HVIC”) that drives power switching elements implementing a bridge circuit for power conversion and the like. The semiconductor device50according to the first embodiment of the present invention drives a power converter60for one phase of the bridge circuit for power conversion, for example, as illustrated inFIG.1. The power converter60includes a high-voltage-side switching element S1and a low-voltage-side switching element S2connected in series to implement an output circuit.

WhileFIG.1illustrates a case in which the high-voltage-side switching element S1and the low-voltage-side switching element S2are each an IGBT, the high-voltage-side switching element S1and the low-voltage-side switching element S2are not limited to the IGBT, and may be any other power switching elements such as a MOSFET. The high-voltage-side switching element Si is connected antiparallel to a freewheeling diode FWD1, and the low-voltage-side switching element S2is connected antiparallel to a freewheeling diode FWD2. The present embodiment may also be applied to a case of a reverse-conducting IGBT in which the high-voltage-side switching element S1and the freewheeling diode FWD1are integrated in one chip, and the low-voltage-side switching element S2and the freewheeling diode FWD2are integrated in another chip.

The high-voltage-side switching element Si and the low-voltage-side switching element S2are connected between a high-voltage main power supply VDC on the positive electrode side and a ground potential (a GND potential) on the negative electrode side with respect to the main power supply VDC so as to implement a half bridge circuit. A high-level electrode terminal (a collector terminal) of the high-voltage-side switching element S1is connected to the main power supply VDC, and a low-level electrode terminal (an emitter terminal) of the low-voltage-side switching element S2is connected to the GND potential. A connection point61between a low-level electrode terminal (an emitter terminal) of the high-voltage-side switching element S1and a high-level electrode terminal (a collector terminal) of the low-voltage-side switching element S2is an output point of the power converter60for one phase of the bridge circuit for power conversion. The connection point61is connected to a load67such as a motor, and a VS potential at a reference voltage terminal VS is supplied to the load67.

The semiconductor device50according to the first embodiment of the present invention outputs, from an output terminal OUT, a drive signal for turning on/off a gate of the high-voltage-side switching element S1so as to drive in accordance with an input signal input from an input terminal IN. The semiconductor device50according to the first embodiment of the present invention includes at least a low-potential-side circuit (a low-side circuit)41, a level shift circuit42, and a high-potential-side circuit (a high-side circuit)43as a part of the entire circuit. The low-side circuit41, the level shift circuit42, and the high-side circuit43may be monolithically integrated in a single semiconductor chip (a semiconductor substrate), for example. Alternatively, elements implementing the low-side circuit41, the level shift circuit42, and the high-side circuit43may be separately integrated in two or more semiconductor chips.

The low-side circuit41operates with the GND potential used as a reference potential applied to a ground terminal GND and with a VCC potential used as a power supply potential applied to a low-level-side power supply terminal VCC. The low-side circuit41generates an ON/OFF signal at a low-side level to output the signal to the level shift circuit42in accordance with the input signal input from the input terminal IN. The low-side circuit41may include a complementary MOS (CMOS) circuit (not illustrated) including an nMOS transistor and a pMOS transistor, for example.

The level shift circuit42operates with the GND potential used as a reference potential applied to the ground terminal GND. The level shift circuit42converts the ON/OFF signal at the low-side level output from the low-side circuit41to an ON/OFF signal at a high-side level used on the high side. The level shift circuit42may include an nMOS transistor to serve as a level shifter, a level shift resistor, and a protection diode (not illustrated).

The high-side circuit43operates with the VS potential used as a reference potential applied to the reference voltage terminal VS and with a VB potential used as a power supply potential that is a first potential applied to a high-level-side power supply terminal VB. The high-side circuit43outputs the drive signal through the output terminal OUT in accordance with the ON/OFF signal output from the level shift circuit42so as to drive a gate of the high-voltage-side switching element S1. The high-side circuit43includes a CMOS circuit at the output stage including an nMOS transistor46as an active element and a pMOS transistor45as an active element. A source terminal of the pMOS transistor45is connected to the high-level-side power supply terminal VB. A source terminal of the nMOS transistor46is connected to the reference voltage terminal VS. The output terminal OUT is connected between a drain terminal of the pMOS transistor45and a drain terminal of the nMOS transistor46.

The semiconductor device50according to the first embodiment of the present invention is illustrated with a bootstrap circuit type. The configuration illustrated inFIG.1includes a bootstrap diode65which is an external element connected between the low-level-side power supply terminal VCC and the high-level-side power supply terminal VB. A bootstrap capacitor66which is an external element is connected between the high-level-side power supply terminal VB and the reference voltage terminal VS. The bootstrap diode65and the bootstrap capacitor66implement a part of the circuit of the drive power supply of the high-voltage-side switching element S1.

The VB potential is the highest potential applied to the semiconductor device50, and is kept at a level higher than the VS potential as a second potential by about 5 to 15 volts due to the bootstrap capacitor66in a normal state of not being affected by noise. The VS potential is repeatedly raised and dropped between the high-potential-side potential of the main power supply VDC (for example, about 400 volts or greater and 2000 volts or lower) and the low-potential-side potential (the GND potential) by complementarily turning on/off the high-voltage-side switching element S1and the low-voltage-side switching element S2, and varies from zero to several hundreds of volts. The VS potential can be a negative potential. The potential of the low-level-side power supply terminal VCC is about 5 to 15 volts.

FIG.2is a view illustrating a schematic planar layout of the semiconductor device50illustrated inFIG.1. The semiconductor device50according to the first embodiment of the present invention includes a high-potential-side circuit area (a high-side circuit area)51and a low-potential-side circuit area (a low-side circuit area)53integrated in a single chip. A structure of high voltage junction termination (HVJT)52is arranged at the circumference of the high-side circuit area51.

The high-side circuit area51illustrated inFIG.2includes elements such as a semiconductor element and a passive element (not illustrated). The type, the number, and the positional relationship of the elements included in the high-side circuit area51can be determined as appropriate. The high-side circuit area51includes a plurality of pads (high-potential-side pads)11a,12a, and13athat can be connected to a bonding wire. The respective high-potential-side pads11a,12a, and13aare implemented by a part of high-potential-side wiring layers11,12, and13exposed on openings11b,12b, and13bin a surface passivation film (31,32). The high-side circuit area51corresponds to the high-side circuit43illustrated inFIG.1, and the respective high-potential-side pads11a,12a, and13acorrespond to the high-level-side power supply terminal VB, the output terminal OUT, and the reference voltage terminal VS illustrated inFIG.1, for example.

The HVJT52electrically separates the high-side circuit area51from the low-side circuit area53. The HVJT52can include a breakdown voltage structure of the level shift elements implementing the level shift circuit42illustrated inFIG.1.

The low-side circuit area53illustrated inFIG.2includes elements such as a semiconductor element and a passive element (not illustrated). The type, the number, and the positional relationship of the elements included in the low-side circuit area53can be determined as appropriate. The low-side circuit area53includes a plurality of pads (low-potential-side pads)14a,15a, and16athat can be connected to the bonding wire. The respective low-potential-side pads14a,15a, and16aare implemented by a part of low-potential-side wiring layers14,15, and16exposed on openings14b,15b, and16bin the surface passivation film (31,32). The low-side circuit area53corresponds to the low-side circuit41illustrated inFIG.1, and the respective low-potential-side pads14a,15a, and16acorrespond to the low-level-side power supply terminal VCC, the input terminal IN, and the ground terminal GND illustrated inFIG.1, for example.

In the present specification, the plural high-potential-side wiring layers11,12, and13and the plural low-potential-side wiring layers14,15, and16are each collectively referred to as a “wiring layer” when the spatial positions or the shapes of the wiring layers are not distinguished from each other. Similarly, in the present specification, the plural high-potential-side pads11a,12a, and13aand the plural low-potential-side pads14a,15a, and16aare each collectively referred to as a “pad” when the spatial positions or the like are not distinguished from each other.

FIG.3is an upper cross-sectional view as viewed from A-A direction inFIG.2particularly illustrating the circumference of the high-potential-side pad11aamong the plural high-potential-side pads11a,12a, and13aincluded in the high-side circuit area51.

The semiconductor device50according to the first embodiment of the present invention includes the high-potential-side wiring layer11serving as the high-potential-side pad11a, as illustrated inFIG.3. The high-potential-side wiring layer11is one of the high-potential-side wiring layers11,12, and13located at the uppermost layer of the multi-layer wiring structure on the semiconductor substrate. The high-potential-side wiring layer11has a thickness of about 600 nanometers or greater and 2000 nanometers or less, for example. The high-potential-side wiring layer11may be made of a metallic material such as aluminum (Al) or an Al alloy mainly including Al. An example of the Al alloy is Al-silicon (Si) or Al—Si-copper (Cu).

A three-layer structure including a titanium nitride (TiN) layer21, a titanium oxynitride (TiON) layer22, and a titanium oxide (TiO) layer23deposited on the TiON layer22is provided on the top surface of the high-potential-side wiring layer11. The TiN layer21has a thickness of about 30 nanometers or greater and 40 nanometers or less, for example. The TiON layer22has a thickness of about 30 nanometers or greater and 40 nanometers or less, for example. The TiO layer23has a thickness of about 30 nanometers or greater and 40 nanometers or less, for example.

The TiN layer21serves as an anti-reflection film for preventing reflection (halation) of light from the metal film as a base of the high-potential-side wiring layer11during the formation of a resist pattern for delineating the metal film. The TiON layer22is formed such that oxygen (O) and nitrogen (N) are diffused into a Ti layer provided on the TiN layer21to serve as an anti-reflection film together with the TiN layer21. The TiO layer23is formed by the oxidation of the top surface of the Ti layer provided on the TiN layer21to serve as the anti-reflection film together with the TiN layer21.

The surface passivation film (31,32) is deposited on the top surface of the TiO layer23. The surface passivation film (31,32) includes a first insulating film31deposited on the TiO layer23, and a second insulating film32deposited on the first insulating film31. The first insulating film31is a silicon oxide film (a SiO2film) having a thickness of about 200 nanometers, for example. The first insulating film31may be an insulating film (a TEOS film) deposited by chemical vapor deposition (CVD) using tetraethoxysilane (TEOS) gas of an organic silicon compound. The second insulating film32is a silicon nitride film (a Si3N4film) having a thickness of about 500 nanometers or greater and 1000 nanometers or less, for example.

The number and the material of the layers included in the surface passivation film (31,32) can be determined as appropriate. For example, the surface passivation film (31,32) may be a single film, or may include three or more layers laminated together. The surface passivation film (31,32) may have a structure including at least one of a polyimide film, a silicon oxide film (a SiO2film) without containing phosphorus (P) or boron (B) which is referred to as a non-doped silicate glass (NSG) film, a phosphosilicate glass (PSG) film, a borosilicate glass (BSG) film, and a borophosphosilicate glass (BPSG) film.

The opening11bis provided to penetrate the TiN layer21, the TiON layer22, the TiO layer23, and the surface passivation film (31,32). A part of the high-potential-side wiring layer11exposed on the opening11bserves as the high-potential-side pad11a.

The opening11bis formed such that the TiN layer21, the TiON layer22, the TiO layer23, and the surface passivation film (31,32) are partly removed by use of a common etching mask. The edge of the second insulating film32is defined by side etching to be retreated from the respective edges of the TiN layer21, the TiON layer22, the TiO layer23, and the first insulating film31. The respective edges of the TiN layer21, the TiON layer22, the TiO layer23, and the surface passivation film (31,32) are exposed on the side wall of the opening11b.

<Method of Manufacturing Semiconductor Device>

An example of a method of manufacturing the semiconductor device according to the first embodiment of the present invention is described below with reference toFIG.4A to5Cwhile focusing on the cross section illustrated inFIG.3. It should be understood that the method of manufacturing the semiconductor device described below is an example, and the semiconductor device can be manufactured by various methods other than the method described below including modified examples within the scope of the appended claims.

First, a semiconductor substrate such as a Si substrate is prepared. Several kinds of elements such as a semiconductor element and a passive element are formed on the semiconductor substrate by use of photolithography, ion implantation, dry etching, CVD, and the like, and the multi-layer wiring structure is further provided on the semiconductor substrate.

Next, a metal film for wiring formation10made of metallic material such as Al or an Al alloy is deposited by sputtering or the like on the uppermost layer of the multi-layer wiring structure. As illustrated inFIG.4A, the TiN layer21is then deposited on the metal film for wiring formation10by sputtering or the like so as to have a thickness of about 30 nanometers or greater and 40 nanometers or less. As illustrated inFIG.4B, the Ti layer24is then deposited on the TiN layer21by sputtering or the like so as to have a thickness of about 30 nanometers or greater and 40 nanometers or less. The TiN layer21and the Ti layer24each have lower reflectance than the metal film for wiring formation10made of Al or an Al alloy, so as to serve as an anti-reflection film. The thickness of the Ti layer24may be 40 nanometers or greater.

The sequential deposition of the metal film for wiring formation10, the TiN layer21, and the Ti layer24is preferably executed through an integrated process. In particular, a wafer transfer between the respective chambers is preferably executed in a vacuum by use of a common sputtering apparatus so as to continuously deposit the metal film for wiring formation10, the TiN layer21, and the Ti layer24without returning to the atmosphere during the process. The use of the metal film for wiring formation10made of Al or an Al alloy leads the interface between the metal film for wiring formation10and the TiN layer21and the interface between the TiN layer21and the Ti layer24to be in a closely joined state, so as to prevent separation between the layers during the manufacturing process. Instead of the deposition through the integrated process, the metal film for wiring formation10, the TiN layer21, and the Ti layer24may be sequentially deposited by use of an independent sputtering apparatus.

If the Ti layer24is deposited with a thickness of less than 30 nanometers, oxygen and nitrogen may be diffused and collide with each other in the Ti layer24during ozone oxidation for passivating the high-potential-side wiring layer11or during heat treatment such as plasma CVD for forming the surface passivation film (31,32) as described below, which results in the fragile TiON layer22having less film hardness to cause the separation of the TiON layer22due to a shear stress during the heat treatment accordingly. The Ti layer24is thus preferably deposited to have a thickness of 30 nanometers or greater.

Next, as illustrated inFIG.4C, a photoresist film71is applied on the Ti layer24. The photoresist film71is then delineated by photolithography. The TiN layer21and the Ti layer24, which serve as the anti-reflection films, can prevent reflection (halation) of light from the metal film for wiring formation10. Using the delineated photoresist film71as an etching mask, the metal film for wiring formation10, the TiN layer21, and the Ti layer24are selectively removed by dry etching such as reactive ion etching (RIE). The selective removal by dry etching delineates the metal film for wiring formation10, the TiN layer21, and the Ti layer24so as to form a wiring pattern of the high-potential-side wiring layer11. Although not illustrated, the other wiring patterns of the high-potential-side wiring layers12and13and the low-potential-side wiring layers14,15, and16illustrated inFIG.2are simultaneously formed by the selective etching removal of the metal film for wiring formation10.

WhileFIG.4Cillustrates the cross section of the wiring pattern focusing on the high-potential-side wiring layer11at a position in which the metal film for wiring formation10, the TiN layer21, and the Ti layer24remain without being removed, the same is also applied to the other wiring patterns. Namely, the TiN layer21and the Ti layer24are delineated to form the multi-layer structure also on the respective high-potential-side wiring layers12and13and the respective low-potential-side wiring layers14,15, and16. An interlayer insulating film is exposed on the part in which the wiring patterns of the high-potential-side wiring layers12and13and the low-potential-side wiring layers14,15, and16are not present.

After the photoresist film71is removed and the surface of the Ti layer24is cleaned, the passivating treatment for oxidizing the Ti layer24is executed by ozone oxidation or the like at a temperature of about 300° C. In this treatment, ozone is diffused from the top surface of the Ti layer24, and a titanium oxide (TiO2) layer24xof anatase type having an amorphous structure is formed with a thickness of about 5 nanometers or greater and 10 nanometers or less, as illustrated inFIG.5A. Since both ozone from above and nitrogen from below are diffused into the Ti layer24, the TiON layer22is formed between the TiN layer21and the TiO2layer24x.

Next, the first insulating film31such as a silicon oxide film is deposited on the TiO2layer24xby a method such as plasma CVD at a temperature of about 380° C. or higher and 405° C. or lower at a normal pressure. The first insulating film31is also deposited on the multi-layer wiring structure exposed on the part in which the wiring patterns of the high-potential-side wiring layers11,12and13and the low-potential-side wiring layers14,15, and16are not present. The interposition of the TiON layer22between the TiN layer21and the TiO2layer24xduring the deposition of the first insulating film31promotes the downward diffusion of oxygen contained in the TiO2layer24xto decrease the oxygen concentration in the TiO2layer24x, so as to form the hydrophilic TiO layer23, as illustrated inFIG.5B. A spin-on-glass (SOG) film may be applied on the first insulating film31after the deposition of the first insulating film31, and then cured at a temperature of about 400° C. or higher and 450° C. or lower.

Next, hydrogen annealing is executed at a temperature of about 400° C. for about 30 minutes. The second insulating film32such as a silicon nitride film is then deposited on the first insulating film31by a method such as plasma CVD at a temperature of about 400° C. with about −390 MPa, as illustrated inFIG.5C. The second insulating film32is also deposited on the first insulating film31deposited on the part in which the wiring patterns of the high-potential-side wiring layers11,12and13and the low-potential-side wiring layers14,15, and16are not present.

Next, a mask film (not illustrated) such as a silicon nitride film is deposited on the second insulating film32by a method such as plasma CVD, and the mask film is delineated by photolithography and etching. Using the delineated mask film as an etching mask for pad opening, the second insulating film32, the first insulating film31, the TiO layer23, the TiON layer22, and the TiN layer21are sequentially selectively removed by dry etching such as RIE. The opening11bis thus formed to expose a part of the high-potential-side wiring layer11so as to use the part exposed on the opening11bto serve as the high-potential-side pad11a, as illustrated inFIG.3. The respective edges of the second insulating film32, the first insulating film31, the TiO layer23, the TiON layer22, and the TiN layer21are exposed on the side wall of the opening11b. The execution of the dry etching also causes the other high-potential-side wiring layers12and13and the low-potential-side wiring layers14,15, and16to be partly exposed, so as to provide the respective high-potential-side pads12aand13aand the respective low-potential-side pads14a,15a, and16aat the exposed parts.

Comparative Example

A semiconductor device of a comparative example is described below. The semiconductor device of the comparative example differs from the semiconductor device according to the first embodiment of the present invention in having a two-layer structure including the TiN layer21and a high-concentration TiO layer25on the high-potential-side wiring layer11, as partly illustrated inFIG.6, while the semiconductor device according to the first embodiment has the three-layer structure including the TiN layer21, the TiON layer22, and the TiO layer23on the high-potential-side wiring layer11, as partly illustrated inFIG.3.

In particular, as partly illustrated inFIG.4B, the manufacturing process for the semiconductor device according to the first embodiment of the present invention provides the two-layer structure including the TiN layer21and the Ti layer24each serving as an anti-reflection film on the high-potential-side wiring layer11to obtain the three-layer structure including the TiN layer21, the TiON layer22, and the TiO layer23accordingly, as illustrated inFIG.3. The manufacturing process for the semiconductor device of the comparative example provides the single TiN layer21serving as an anti-reflection film without forming the Ti layer24to obtain the two-layer structure including the TiN layer21and the high-concentration TiO layer25, as illustrated inFIG.6.

In the semiconductor device of the comparative example illustrated inFIG.6, the edge of the high-concentration TiO layer25is exposed on the side wall of the opening11b. The high-concentration TiO layer25has oxygen concentration and superhydrophilicity higher than those of the TiO layer23. This leads moisture or OH−to easily enter the interface between the TiN layer21and the high-concentration TiO layer25under the temperature-humidity-bias (THB) environment, and tends to cause separation between the TiN layer21and the high-concentration TiO layer25due to a decomposition reaction. In addition, the reaction between TiN and moisture produces TiO to lead to volume expansion to cause cracks or voids in the surface passivation film (31,32), resulting in a decomposition reaction at the circumference of the high-potential-side pad11aor faults such as corrosion of the wiring layer.

If the semiconductor device of the comparative example is used for a HVIC, the separation tends to be caused at the circumference of the respective high-potential-side pads11a,12a, and13adue to an anodic oxidation reaction (a decomposition reaction), as illustrated inFIG.7.FIG.7schematically illustrates areas A1, A2, and A3in which the separation is caused between the TiN layer21and the high-concentration TiO layer25. When a temperature-humidity-bias (THB) test is executed for the semiconductor chip such as the HVIC in which a high voltage of several hundreds of volts is applied to the respective high-potential-side pads11a,12a, and13a, a large amount of impurity ions or OH−contained in molded resin is accumulated toward the high-potential-side pads11a,12a, and13a. Further, since the high-concentration TiO layer25has superhydrophilicity, TiO reacts with moisture or OH−accumulated around the high-potential-side pads11a,12a, and13aunder the THB environment, and nitrogen is released as ammonium ions (NH4+) from the TiN layer21having hydrophobicity. The inventors found out that a precipitate such as Ti(OH)4is deposited at the released part, and the volume expansion of TiO promotes at the interface with the TiN layer21, causing voids at the interface or cracks in the surface passivation film to result in faults in shape of the pads.

In the semiconductor device according to the first embodiment of the present invention, while the respective edges of the TiN layer21, the TiON layer22, the TiO layer23, and the surface passivation film (31,32) are exposed on the side wall of the opening11bas illustrated inFIG.3, the TiON layer22interposed as a buffer layer between the hydrophobic TiN layer21and the hydrophilic TiO layer23promotes the downward diffusion of oxygen. This decreases the oxygen concentration in the TiO layer23to shift from superhydrophilicity to hydrophilicity, so as to avoid rapid introduction of moisture or OH−from the side wall of the opening11bto prevent the reaction of moisture or OH−with TiN (the anodic oxidation reaction). In addition, the bond of hydrogen between the TiO layer23and the TiON layer22can prevent the entrance of moisture. The prevention of the entrance of moisture can reduce the volume expansion of TiO or the releasing phenomenon of NH4+from TiN accordingly.

FIG.8,FIG.9, andFIG.10show, on an upper side, line profiles by a STEM in a case in which the Ti layer deposited on the TiN layer in the manufacturing process has a thickness of each of 35, 15, and 5 nanometers.FIG.8,FIG.9, andFIG.10shows, on a lower side, micrographs by the STEM corresponding to the upper side ofFIG.8,FIG.9, andFIG.10. The line profiles and the micrographs by the STEM are obtained from samples after the completion of the entire manufacturing process including the passivation film step.

In the line profiles ofFIG.8,FIG.9, andFIG.10, the detection amount of the respective elements is treated such that the0element in the TEOS (P-TEOS) layer formed by plasma CVD and the Ti element and the N element in the TiN layer have peak detection intensity substantially equal to each other. The boundary between the TiO layer21and the TiON layer22and the boundary between the TiON layer22and the TiO layer23can be generally defined as follows.

As illustrated in the line profile ofFIG.8, the boundary between the TiO layer21and the TiON layer22is defined along a position “a” in which the respective concentration inclinations of oxygen and nitrogen are shifted from a steep state to a gentle state in the depth direction from the surface passivation film31. The boundary between the TiON layer22and the TiO layer23is defined along a position “b” in which the respective concentration inclinations of oxygen and nitrogen are shifted to the steep state in the depth direction from the position “a”. The nitrogen concentration in the TiON layer22at a position “c” at which the oxygen concentration and the nitrogen concentration intersect with each other is preferably half or lower of the concentration at a position “d” at which the TiN layer21has the highest nitrogen concentration.

As shown in the upper side ofFIG.8, when the thickness of the Ti layer deposited on the TiN layer is 30 nanometers or greater, the regions in which the respective concentration inclinations of oxygen and nitrogen in the Ti layer are steep do not intersect with each other, so as to avoid the separation at the film interface during the manufacturing process. The separation at the respective interfaces between the TiN, TiON, and TiO is thus not observed in the micrograph ofFIG.8. In contrast, when the thickness of the Ti layer deposited on the TiN layer is less than 30 nanometers, as shown in the micrographs ofFIG.9andFIG.10, the regions in which the respective concentration inclinations of oxygen and nitrogen diffused into the Ti layer are steep intersect with each other, as indicated in the region surrounded by the broken line. This provides the fragile TiON layer, which may induce film separation due to a shear stress during high-temperature treatment. The separation is observed in each of the micrographs ofFIG.9andFIG.10as indicated by the white part in the region surrounded by the broken line.

The Ti layer24is thus preferably deposited to have a thickness of 30 nanometers or greater as an anti-reflection film on the TiN layer21in the manufacturing process for the semiconductor device. The end product of the semiconductor device preferably has 30 nanometers or greater of the total thickness of the TiON layer22and the TiO layer23corresponding to the thickness of the Ti layer24. Setting the thickness of the Ti layer24to 30 nanometers or greater can lead the nitrogen concentration in the TiON layer22at the part at which the oxygen concentration and the nitrogen concentration intersect with each other to be half or lower of the concentration at the part at which the TiN layer21has the highest nitrogen concentration.

As described above, the manufacturing process for the semiconductor device according to the first embodiment of the present invention provides the two-layer structure including the TiN layer21as a lower layer and the Ti layer24as an upper layer to serve as the anti-reflection films on the metal film for wiring formation10, so as to reduce the reflection (halation) of light from the metal film for wiring formation10when forming the photoresist pattern for delineating the respective high-potential-side wiring layers11,12, and13.

The end product of the semiconductor device has the three-layer structure including the TiN layer21, the TiON layer22, and the TiO layer23on the respective high-potential-side wiring layers11,12, and13. The TiON layer22prevents the reaction with moisture or OH−or the release of NH4+under the temperature-humidity-bias environment, so as to avoid volume expansion of the TiO layer23. This eliminates the execution of separated operations for the etching step of etching the TiN layer21, the TiON layer22, and the TiO layer23serving as the anti-reflection films and the etching step of etching the surface passivation film32to cover the edge of the TiN layer21with the surface passivation film, so as to avoid an increase in the number of the steps of the process.

As illustrated inFIG.11, the surface passivation film32may be formed to cover the opening11bof the TiN layer21, the TiON layer22, and the TiO layer23. While the number of the steps of the process increases in this case, the effect of preventing the volume expansion of the TiO layer23can be improved.

Second Embodiment

<Configuration of Semiconductor Device>

A semiconductor device according to a second embodiment of the present invention is illustrated below with a HVIC, as in the case of the semiconductor device according to the first embodiment of the present invention. The semiconductor device according to the second embodiment of the present invention includes wiring layers (high-potential-side wiring layers)81,82, and83at the uppermost layer of the multi-layer wiring structure on the semiconductor substrate, as illustrated inFIG.12. The high-potential-side wiring layers81and82partly serve as pads (high-potential-side pads)81aand82a. The high-potential-side pads81aand82aare defined by openings81band82bof a surface passivation film (not illustrated).FIG.12illustrates the openings81band82bof the surface passivation film as indicated by the dash-dotted lines. The high-potential-side wiring layer83has a meandering wiring pattern.

FIG.13is a view, separately indicated on the right and left sides, illustrating a cross section at the circumferential area of the high-potential-side pad81aas viewed in direction A-A inFIG.12and a cross section adjacent to the edge of the high-potential-side wiring layer81as viewed in direction B-B distant from the circumferential area of the high-potential-side pad81a. As illustrated inFIG.13, if the three-layer structure including the TiN layer21, the TiON layer22, and the TiO layer23on the high-potential-side wiring layer81is provided entirely in the semiconductor device, separation may be caused at the interface between the TiON layer22and the TiO layer23due to curing of the SOG film or heat treatment such as hydrogen annealing, since the adhesion at the interface between the TiON layer22and the TiO layer23is low. As shown on the right side inFIG.13, a tensile stress F of the surface passivation film (31,32) after the deposition of the second insulating film32may promote the separation at the interface between the TiON layer22and the TiO layer23to result in degradation of external appearance. The interface separation occurs particularly when the thickness of the Ti layer24on the TiN layer is 30 nanometers or less during the manufacturing process.

The separation at the interface between the TiON layer22and the TiO layer23tends to promote particularly in an area A21in the wiring pattern of the high-potential-side wiring layer83and in areas A22, A23, and A24adjacent to the edges (the corners) of the high-potential-side wiring layers81and82serving as the high-potential-side pads81aand82, due to a film stress at the respective edges of the high-potential-side wiring layers81,82, and83, as illustrated inFIG.12.

To deal with this problem, as illustrated inFIG.14, the semiconductor device according to the second embodiment of the present invention uses the anti-reflection film having a structure that differs between circumferential areas (pad circumferential areas) A31and A32of the high-potential-side pads81aand82aand an area (a pad separation area) A33separated further from the high-potential-side pads81aand82athan the pad circumferential areas A31and A32.FIG.14illustrates the pad circumferential areas A31and A32each indicated by the gray hatch and the pad separation area A33with no hatch. The pad separation area A33is the other area excluding the pad circumferential areas A31and A32, and includes the edges of the high-potential-side wiring layers81and82serving as the high-potential-side pads81aand82aand the high-potential-side wiring layer83having the wiring pattern.

The pad circumferential areas A31and A32each have a frame-shaped planar pattern surrounding the high-potential-side pads81aand82a. The respective pad circumferential areas A31and A32are defined in an area with a predetermined distance D1from the respective openings81band82b. The respective pad circumferential areas A31and A32are also defined to be distant from the edges of the respective high-potential-side wiring layers81and82by a predetermined distance D2. In other words, the pad separation area A33is defined to include the predetermined distance D2from the edges of the respective high-potential-side wiring layers81and82. The distance D1is about one micrometer or greater, and preferably five micrometers or greater, for example. The distance D2is about 10 micrometers or greater, for example.

FIG.15is a view, separately indicated on the right and left sides, illustrating a cross section of the pad circumferential area A31as viewed in direction A-A inFIG.14and a cross section of the pad separation area A33as viewed in direction B-B inFIG.14. The pad circumferential area A31indicated on the left side inFIG.15selectively (locally) has a three-layer structure of the TiN layer21, the TiON layer22, and the TiO layer23on the high-potential-side wiring layer81. The TiON layer22promotes the downward diffusion of oxygen, so as to decrease the oxygen concentration in the TiO layer23and lead the TiO layer23to have hydrophilicity. This can avoid a rapid moisture absorption action to prevent the entrance of moisture or OH−in the pad circumferential area A31, and can prevent a decomposition reaction at the circumference of the high-potential-side pad81aupon high-voltage application or corrosion of the wiring layer. The pad circumferential area A32illustrated inFIG.14has the same structure as the pad circumferential area A31. The three-layer structure is preferably provided adjacent to the opening11b.

The pad separation area A33indicated on the right side inFIG.15has a two-layer structure of the TiN layer21and the high-concentration TiO layer25on the high-potential-side wiring layer81. The TiON layer is not interposed between the TiN layer21and the high-concentration TiO layer25so as eliminate the interface between the TiO and TiON that has low adhesion and is easy to separate. This structure can avoid the separation and the degradation of external appearance. In addition, since the pad separation area A33is distant from the high-potential-side pads81aand82a, the entrance of moisture or OH−from the side walls of the high-potential-side pads81aand82adoes not occur. Although not illustrated, the TiN layer21and the high-concentration TiO layer25are provided on the multi-layer wiring structure under the high-potential-side wiring layers81,82, and83at the part of the pad separation area A33illustrated inFIG.14in which the high-potential-side wiring layers81,82, and83are not provided.

<Method of Manufacturing Semiconductor Device>

An example of a method of manufacturing the semiconductor device according to the second embodiment of the present invention is described below while focusing on the cross section corresponding to the case inFIG.15. As illustrated inFIG.16A, the TiN layer21and the Ti layer24are sequentially deposited on a metal film for wiring formation80, as in the case of the process in the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

Next, as illustrated inFIG.16B, a photoresist film71is applied on the Ti layer24. The photoresist film71is then delineated by photolithography. The TiN layer21and the Ti layer24, which serve as the anti-reflection films, can prevent reflection (halation) of light from the metal film for wiring formation80. Using the delineated photoresist film71as an etching mask, the metal film for wiring formation80, the TiN layer21, and the Ti layer24are selectively removed by dry etching such as reactive ion etching (RIE) so as to delineate the metal film for wiring formation80, the TiN layer21, and the Ti layer24.FIG.16Billustrates the part in which the metal film for wiring formation80, the TiN layer21, and the Ti layer24remain without being removed.

Next, a photoresist film72is applied on the Ti layer24. The photoresist film72is then delineated by photolithography. Using the delineated photoresist film72as an etching mask, the Ti layer24in the pad separation area A33is selectively removed by dry etching such as RIE so as to leave the Ti layer24only in the pad circumferential area A31, as illustrated inFIG.16C. The other subsequent steps in the method of manufacturing the semiconductor device according to the second embodiment of the present invention are the same as those in the method of manufacturing the semiconductor device according to the first embodiment of the present invention, and overlapping explanations are not repeated below.

FIG.17andFIG.18are views showing line profiles by a STEM in a case in which the TiN layer and the Ti layer are stacked as an anti-reflection film in the pad separation area A33(comparative example), and a case in which only the TiN layer is stacked as an anti-reflection film in the pad separation area A33(example). In the comparative example shown inFIG.17, separation was observed at a position P1indicated by the broken line around the boundary between TiO and TiON. In the example shown inFIG.18, a steep change in the concentration inclination around the boundary between TiO and TiON was not confirmed, or a separation was not observed.

As described above, the manufacturing process for the semiconductor device according to the second embodiment of the present invention provides the two-layer structure of the TiN layer21as a lower layer and the Ti layer24as an upper layer to serve as the anti-reflection films on the metal film for wiring formation80, as in the case of the first embodiment of the present invention, so as to reduce the reflection (halation) of light from the metal film for wiring formation80when forming the photoresist pattern for delineating the respective high-potential-side wiring layers81and82.

According to the second embodiment of the present invention, the three-layer structure of the TiN layer21, the TiON layer22, and the TiO layer23is selectively (locally) provided on the high-potential-side wiring layer81in the respective pad circumferential areas A31and A32, so as to prevent a decomposition reaction at the circumference of the high-potential-side pads81aand82aor corrosion of the wiring layer. In addition, the two-layer structure of the TiN layer21and the high-concentration TiO layer25is selectively provided on the high-potential-side wiring layer81in the pad separation area A33, so as to avoid the separation during the manufacturing process and the degradation of external appearance. The thickness of the Ti layer24is preferably 10 nanometers or greater in view of suppression of the decomposition reaction in the high-potential-side pads.

Other Embodiments

As described above, the invention has been described according to the first and second embodiments, but it should not be understood that the description and drawings implementing a portion of this disclosure limit the invention. Various alternative embodiments of the present invention, examples, and operational techniques will be apparent to those skilled in the art from this disclosure.

For example, the first and second embodiments of the present invention illustrated above are not limited to the case of the semiconductor device using the Si substrate as the semiconductor substrate. The technical idea described in the first and second embodiments of the present invention may be applied to a semiconductor device using a semiconductor of a compound such as arsenic gallium (GaAs). The technical idea described in the first and second embodiments of the present invention may also be applied to a semiconductor device using a wide-bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), or diamond. The technical idea described in the first and second embodiments of the present invention may also be applied to a semiconductor device using a narrow-bandgap semiconductor such as indium antimonide (InSb) or semimetal.

The semiconductor device according to the first and second embodiments of the present invention illustrated above are not limited to the case of HVIC. For example, the technical idea described in the first and second embodiments of the present invention is particularly effective for a semiconductor device to which a high voltage of several tens of volts or more is applied.