Patent ID: 12200927

DETAILED DESCRIPTION

Embodiments of the invention will now be described with reference to the drawings.

The drawings described below are schematic, and are exaggerated or simplified as appropriate for easier viewing of the drawings. For example, there are cases where only major components are shown, and the other components are not illustrated. The configurations and dimensional ratios do not always match between the drawings, even for identical components.

First Embodiment

FIG.1is a perspective view showing a memory device according to the first embodiment of the present invention.

In the memory device1according to the embodiment as shown inFIG.1, a semiconductor substrate100is provided, and multiple tiles101are arranged in a plane on the semiconductor substrate100. The semiconductor substrate100is, for example, a p-type silicon substrate.

In the specification hereinbelow, an XYZ orthogonal coordinate system is employed for convenience of description. Two mutually-orthogonal directions parallel to the upper surface of the semiconductor substrate100are taken as an “X-direction” and a “Y-direction”. For example, the multiple tiles101are arranged in a matrix configuration along the X-direction and the Y-direction. A direction perpendicular to the upper surface of the semiconductor substrate100is taken as a “Z-direction”. Although a direction that is in the Z-direction from the semiconductor substrate100toward the tiles101also is called “up” and the reverse direction also is called “down”, these expressions are for convenience and are independent of the direction of gravity.

A general configuration of the tile101will now be described.

FIG.2is a cross-sectional view showing one tile of the memory device according to the first embodiment.

In the tile101as shown inFIG.2, an inter-layer insulating film111and a passivation film112are stacked in this order upward from the substrate100below. The inter-layer insulating film111contacts the upper surface of the semiconductor substrate100. For example, the inter-layer insulating film111is formed of silicon oxide (SiOx). For example, the passivation film112is formed of polyimide.

Many p-type or n-type impurity diffusion layers121, and other structures, such as STI (Shallow Trench Isolation structures)(not shown), are formed in the upper portion of the semiconductor substrate100. Gate electrodes122and contacts123are provided in the lower portion of the inter-layer insulating film111. The gate electrodes122are insulated from the semiconductor substrate by a gate oxide film. Circuit elements such as MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), etc., are formed in the semiconductor substrate100by the impurity diffusion layers121, the gate oxide film and the gate electrodes122, etc. The circuit elements are formed in a circuit element formation layer131which includes the upper portion of the semiconductor substrate100and the lower portion of the inter-layer insulating film111.

Multiple layers of interconnects124and vias125are formed on the circuit element formation layer131in the inter-layer insulating film111. A lower layer interconnect layer132includes the interconnects124and the vias125. The peripheral circuit of the memory device1is formed in the circuit element formation layer131and the lower layer interconnect layer132.

A portion of the inter-layer insulating film111positioned above the lower layer interconnect layer132is a memory array portion133. The configuration of the memory array portion133is described below.

The portion of the inter-layer insulating film111positioned above the memory array portion133and the portion in which the passivation film112is located are included in an upper layer interconnect layer134. In the upper layer interconnect layer134, interconnects126and vias127are provided in the inter-layer insulating film111, and a pad128is provided on the inter-layer insulating film111. The central portion of the pad128is exposed from under the passivation film112.

Although a configuration is described as an example in the present embodiment in which the peripheral circuit is formed under the memory array portion133, the invention is not limited thereto. For example, both the memory array portion and the peripheral circuit may be directly formed on the semiconductor substrate. In such a case, for example, the peripheral circuit is located at the periphery of the memory array portion. Alternately, the peripheral circuit may be formed on another semiconductor substrate. In such a case, for example, the semiconductor substrate in which the memory array portion is formed and the semiconductor substrate in which the peripheral circuit is formed are bonded together after formation.

The configuration of the memory array portion133will now be described.

FIGS.3A and3Bare perspective views showing the memory array portion of the memory device according to the first embodiment.

FIG.4is a plan view showing the memory array portion of the memory device according to the first embodiment.

FIG.5is a cross-sectional view along line A-A′ shown inFIG.4.

FIG.6is a cross-sectional view along line B-B′ shown inFIG.4.

FIG.7is a cross-sectional view along line C-C′ shown inFIG.4.

In the memory array portion133of the memory device1as shown inFIGS.3A,3B,4,5,6, and7, multiple source-drain structure bodies10and multiple gate structure bodies20are alternately arranged one at a time along the X-direction on an inter-layer insulating film111a. The inter-layer insulating film111ais part of the lower portion of the inter-layer insulating film111. The source-drain structure bodies10and the gate structure bodies20each have a plate shape spreading along the YZ plane. A memory structure body30includes the multiple source-drain structure bodies10and the multiple gate structure bodies20.

The source-drain structure bodies10each include multiple unit stacked bodies11and multiple insulating bodies12alternately arranged one on top of another along the Z-direction. The insulating body12is in the form of a horizontal strip extending in the Y-direction. The insulating body12is made of an insulating material, e.g., silicon oxycarbide (SiOC).

A source line13, a source layer14, an insulating layer15, a drain layer16, and a bit line (a drain line)17are stacked in this order upward from below in each unit stacked body11. The source line13, the source layer14, the insulating layer15, the drain layer16, and the bit line17each have a form of a horizontal strip extending in the Y-direction. Accordingly, the multiple bit lines17are arranged along the X-direction and the Z-direction in the entire memory structure body30to form a three-dimensional memory array structure. This is similar for the source line13, the source layer14, the insulating layer15, and the drain layer16as well.

The source line13and the bit line17are made of metals. For example, the source line13and the bit line17are formed using a refractory metal layer with a metal liner formed thereon. The refractory metal layer may include a layer of tungsten (W), tungsten nitride (WN), molybdenum (Mo), or titanium tungsten alloy (TiW). The metal liner layer may include a layer of titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN). The source layer14and the drain layer16are semiconductor layers and are made of, for example, n+-type amorphous silicon (aSi). The source layer14contacts the source line13, and the drain layer16contacts the bit line17. The insulating layer15is formed of an insulating material, e.g., silicon oxide. The insulating layer15contacts the source layer14and the drain layer16.

Referring toFIG.4, channel layers18are provided on the two side surfaces of the stacked body made of the source line13, the source layer14, the insulating layer15, the drain layer16, and the bit line17facing the two X-direction sides. The channel layer18is a semiconductor layer and is made of, for example, p+-type amorphous silicon. The channel layer18contacts the source line13, the source layer14, the insulating layer15, the drain layer16, and the bit line17.

The gate structure bodies20each include multiple local word lines21and multiple insulating members22alternately arranged along the Y-direction. The local word line21and the insulating member22have columnar configurations extending in the Z-direction. The insulating member22is made of an insulating material, e.g., silicon oxide.

The local word lines21in two adjacent gate structure bodies20of a source-drain structure body10are positioned staggered from each other in the Y-direction. In other words, when viewed from the Z-direction, the local word lines21in the multiple gate structure bodies20are arranged in a staggered configuration. When viewed from the X-direction, the local word lines21that belong to one gate structure body20and the local word lines21that belong to an adjacent gate structure body20may have an overlap in the Y-direction or the local word lines21may be spaced apart in the Y-direction without any overlap. A charge storage film23is formed on each local word line21. In particular, the charge storage film23is formed between a respective local word line21and a respective channel layer. Chargers are stored or removed from the charge storage film to realize the memory function of the memory array.

The local word line21is made of a metal. For example, the local word line21is formed using a refractory metal layer with a metal liner formed thereon. The refractory metal layer may include a layer of tungsten (W), tungsten nitride (WN), molybdenum (Mo), titanium tungsten alloy (TiW) or copper (Cu). The metal liner layer may include a layer of titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN). The charge storage film23may include a tunneling layer, a charge storage layer and a blocking layer. The tunneling layer may include one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (AlOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), hafnium silicon oxide (HfSixOy), hafnium zirconium oxide (HfZrO), or combination. The charge storage layer may include silicon nitride (SiN), hafnium oxide (HfOx), or hafnium silicon oxynitride (HfSiON). The blocking layer may include silicon oxide, aluminum oxide, or both.

For example, the channel layer18of the source-drain structure body10contacts the insulating member22and the charge storage film23of the gate structure body20. In other words, for example, the source-drain structure body10contacts the gate structure body20.

Thereby, a memory cell40that has a MOSFET structure is configured at each most proximate portion between the unit stacked bodies11extending in the Y-direction and the local word lines21extending in the Z-direction. The memory cell40has different thresholds according to whether or not a charge is stored in the charge storage layer in the charge storage film23. Therefore, information can be stored by the charge entering and exiting the charge storage layer. In one example embodiment, the charge storage layer of the charge storage film23in which the charge is stored is a silicon nitride layer, but the present invention is not limited thereto. For example, the charge storage layer may be formed of a material such as hafnium silicon oxide (HfSiO), zirconium oxide (ZrO), hafnium aluminum oxide (HfAlO), silicon oxynitride (SiON), silicon nitride (SiN), hafnium oxide (HfOx), hafnium silicon oxynitride (HfSiON), etc.

Returning toFIG.2, the two Y-direction end portions of the memory structure body30include staircase structures, and the upper surface of each step includes the bit line17. Each bit line17is connected to a contact at the upper surface of the step. It is sufficient for the memory structure body30to have a configuration in which each bit line17can be connected to the peripheral circuit, and it is not always necessary for the end portions to have staircase structures.

Multiple global word lines31are provided on the memory structure body30. The multiple global word lines31are arranged along the Y-direction, and each global word line31extends in the X-direction. In the present embodiment, the global word line31has a shape that corresponds to the position of a reference bit line17r, as will be described in more details below.

First, the general configuration of the global word line31will be described.

Referring toFIG.4, the width, i.e., the length in the Y-direction, of each global word line31is about equal to or less than the length in the Y-direction of the local word line21. Each global word line31passes through the region directly above the local word lines21belonging to every other gate structure body20and is connected to these local word lines21via plugs29(FIG.5). In other words, a first global word line31is connected to the local word lines21belonging to the odd-numbered gate structure bodies20counting from one X-direction end portion of the memory structure body30, and the global word line31next to the first global word line31is connected to the local word lines21belonging to the even-numbered gate structure bodies20.

The relationship between the reference bit line and the global word line will now be described.

FIG.8is a plan view showing the memory structure body and the global word lines of the first embodiment.

Four global word lines31are marked with the numerals “1” to “4” inFIG.8to assist understanding. Also, eight local word lines21are marked, two each, with the numerals “1” to “4”. As described below, the global word line31and the local word lines21that are marked with the same numeral are connected to each other. The charge storage film23is not shown inFIG.8to simplify the discussion.

As shown inFIG.8, the multiple bit lines17include three types of bit lines: “reference bit line17r”, “dummy bit line17d”, and “active bit line17a.”

Bit lines17that are associated with at least one source-drain structure body10of the multiple source-drain structure bodies10provided in the memory structure body30are used as the reference bit lines17r. In the present embodiment, the reference bit lines17rare located at the vicinities of the two X-direction end portions of the memory structure body30. The unit stacked body11that includes the reference bit line17rdoes not function as a memory cell. Hereinbelow, the unit stacked body11that includes the reference bit line17ris called a “dummy memory cell40d”. The reference bit line17rprovides a reference potential when reading data from the memory cell40connected to the active bit line17a.

The bit lines17that are located at the periphery of the reference bit line17rare used as the dummy bit lines17d. The unit stacked body11that includes the dummy bit line17ddoes not function as a memory cell. The dummy bit line17dmay not be provided, or the dummy bit line17dmay be at a position other than the periphery of the reference bit line17r.

The bit lines17other than the reference bit line17rand the dummy bit line17dare used as the active bit lines17a. In the present embodiment, the active bit lines17aare located at portions other than the two X-direction end portions of the memory structure body30. The unit stacked body11that includes the active bit line17afunctions as memory cells.

Each respective source-drain structure body10is associated with a given type of bit lines17. In other words, all of the multiple bit lines17arranged in the Z-direction that are associated with one source-drain structure body10are of the same type, being one of the reference bit lines17r, the dummy bit lines17d, or the active bit lines17a.

Each global word line31is formed as a continuous body including a basic portion31a, a wide portion31b, and a pad portion31c. The basic portion31ahas the general configuration of the global word line31described above. In other words, the width of the basic portion31ais about equal to or less than the length in the Y-direction of the local word line21. The basic portion31aof each global word line31is located in the regions directly above the local word lines21adjacent or interposed between the active bit lines17a. The basic portion31ais connected to the multiple local word lines21that are arranged in one column along the X-direction and belong to every other gate structure body20.

The wide portion31bof each global word line31is located in a region directly above the reference bit line17rand the two local word lines21having the reference bit line17rinterposed therebetween. The width, i.e., the length in the Y-direction, of the wide portion31bis greater than the width of the basic portion31a. Thereby, the wide portion31bis connected to the two local word lines21that are arranged in a direction oblique to the X-direction with the reference bit line17rinterposed therebetween. In other words, the wide portion31bis connected to two staggered local word lines21formed across the reference bit line17rinterposed therebetween.

By such a configuration as shown inFIG.8, the wide portion31bof one global word line31marked with the numeral “1” is connected to two local word lines21marked with the numeral “1”. The two local word lines21have the reference bit line17rinterposed. This is similar for the global word lines31and the local word lines21marked with the numerals “2” to “4” as well.

The pad portion31cof each global word line31is located at the end portion of the global word line31and is located at the outer X-direction side of the memory structure body30when viewed from the Z-direction. In one embodiment, the width of the pad portion31cis greater than the width of the wide portion31b. In other embodiments, the width of the pad portion31cmay not be greater than the width of the wide portion31band may be, for example, equal to the width of the wide portion31b. A contact28is connected to the pad portion31c, and the pad portion31cis connected to the peripheral circuit via the contact28.

As described above, the basic portion31aof the global word line31is located at the vicinities of the regions directly above the active bit lines17a, and the active bit lines17aare located at the X-direction central portion of the memory structure body30. The wide portion31bis located at the vicinity of the region directly above the reference bit line17r, and the reference bit line17ris located at the X-direction end portion of the memory structure body30. The pad portion31cis located at the outer X-direction side of the region directly above the memory structure body30. Therefore, in each global word line31, the wide portion31bis located between the basic portion31aand the pad portion31c.

In the first and fourth global word lines31counting from one Y-direction end, the wide portion31band the pad portion31care located at one X-direction end (the left side ofFIG.8); and in the second and third global word lines31, the wide portion31band the pad portion31care located at the other X-direction end (the right side ofFIG.8). Combinations of the four global word lines31and allocation of the wide portion31band the pad portion31c(the left side or the right side ofFIG.8) may have other arrangement. In the present embodiment, the four global word lines31that are consecutively arranged are included in one basic unit, and the basic unit may be repeatedly arranged along the Y-direction across the memory structure body.

Because the width of the wide portion31bis greater than the width of the basic portion31a, the number of the global word lines31arrangeable in the Y-direction in the region where the wide portion31bis located is about half of that in the region where the basic portion31ais located. For example, as shown inFIG.8, the global word line31marked with the numeral “2” and the global word line31marked with the numeral “3” cannot be disposed between the wide portion31bof the global word line31marked with the numeral “1” and the wide portion31bof the global word line31marked with the numeral “4”. The basic portion31aof the global word line31marked with the numeral “2” is terminated before reaching the wide portion31bof the global word line31marked with the numeral “1”; and the basic portion31aof the global word line31marked with the numeral “3” is terminated before reaching the wide portion31bof the global word line31marked with the numeral “4”.

Similarly, other global word lines31cannot be disposed between the wide portion31bof the global word line31marked with the numeral “2” and the wide portion31bof the global word line31marked with the numeral “3”. Therefore, the basic portion31aof the global word line31marked with the numeral “1” is terminated before reaching the wide portion31bof the global word line31marked with the numeral “2”; and the basic portion31aof the global word line31marked with the numeral “4” is terminated before reaching the wide portion31bof the global word line31marked with the numeral “3”. Thus, the basic portion31aof each global word line31must be terminated before reaching the wide portion31bof the global word line31next to that global word line31. Accordingly, if the basic portions31aof all of the global word lines31are located over the regions directly above all of the active bit lines17a, the wide portions31bcan be located only at the two X-direction end portions of the memory structure body30.

The local word lines21which belong two gate structure bodies20having the reference bit line17rlocated at left side ofFIG.8interposed are connected to the wide portions31bof the global word lines31marked with the numerals “1” and “4”, but not connected to the global word lines31marked with the numerals “2” and “3”. On the other hand, the local word lines21which belong two gate structure bodies20having the reference bit line17rlocated at right side ofFIG.8interposed are connected to the wide portions31bof the global word lines31marked with the numerals “2” and “3”, but not connected to the global word lines31marked with the numerals “1” and “4”.

In this way, each global word line31is connected to all of the local word lines21that are formed in a respective column in the X-direction and one additional local word line21that is formed in an adjacent column. In particular, each global word line31is connected at the wide portion31bto a local word line21belonging to one column and also to a local word line belonging to an adjacent column. The two local word lines connected by the wide portion31bare formed on the two sides of the referenced bit line17rand are staggered in the Y-direction.

The relationship between the bit lines and the sense amplifiers will now be described.

FIG.9shows the bit lines and the sense amplifiers of the first embodiment.

FIG.10is a circuit diagram showing the local word lines, the memory cells, the bit lines, and the sense amplifiers of the first embodiment.

In the example shown inFIG.8, one reference bit line17ris provided on each of the left and right sides. In the example shown inFIG.9, three reference bit lines17rare provided on each of the left and right sides. Thereby, in the example shown inFIG.9, the wide portion31bof the global word line31is located at region directly above three source-drain structure bodies10and four gate structure bodies20. The three reference bit lines17rbelong to the three source-drain structure bodies10. The four gate structure bodies20are located on both side of each of the three source-drain structure bodies10. The wide portion31bof the global word line31is connected to the local word lines21which belong to the four gate structure bodies20. InFIG.9, the bit lines17are shown with a dotted pattern for convenience of illustration.

As shown inFIGS.9and10, the bit lines17extend out at the staircase structures in the Y-direction end portions of the memory structure body30and are connected to sense amplifiers41. A sense amplifier41is provided for the multiple bit lines17; and each bit line17is switchably connected to a respective sense amplifier41(the switching element is not illustrated inFIGS.9and10for simplicity). In other embodiments, the sense amplifiers41may be provided respectively for each of the bit lines17. InFIGS.9and10, only two sense amplifiers41are shown for convenience of illustration.

A bit line driver42and a transistor43are provided between the bit line17and the sense amplifier41. The bit line driver42is a switching element such as a MOSFET, etc. The transistor43is, for example, a PMOS (p-type Metal-Oxide-Semiconductor) transistor. The bit line driver42is connected between the bit line17and the gate of the transistor43. The drain of the transistor43is connected to the input terminal of the sense amplifier41. The output terminal of the sense amplifier41is connected to a comparison circuit44. For example, the sense amplifier41, the bit line driver42, the transistor43, and the comparison circuit44are located in the peripheral circuit formed in the circuit element formation layer131and the lower layer interconnect layer132(referring toFIG.2).

An operation of the memory device1according to the present embodiment will now be described.

As shown inFIGS.9and10, one memory cell40of which the value is to be read is selected from the multiple memory cells40. The selected memory cell40is taken as a “memory cell40s”.

First, all of the source lines13are set to an electrically floating state after applying a constant potential. Then, a read potential Vread is applied to the global word line31that is connected to the memory cell40s. Thereby, the read potential Vread is applied to the local word line21connected to the memory cell40svia the basic portion31aof the global word line31. In description below, memory cell40sis connected to the global word line31marked with the numeral “1”. Thus, the read potential Vread is applied to the global word line31marked with the numeral “1”. On the other hand, an off-potential Voff is applied to the global word lines31other than the global word line31connected to the memory cell40s. Namely, the off-potential Voff is applied to the global word lines31marked with the numerals “2” to “4”. Therefore, the off-potential Voff is applied to the local word lines21marked with the numerals “2” to “4” via the wide portion31bof the global word lines31marked with the numerals “2” to “4”.

A bit line potential Vbit is applied to the active bit line17aconnected to the memory cell40s. The bit line potential Vbit is applied to the reference bit line17ras well. A potential is not applied to the other active bit lines17aand dummy bit lines17d.

The read potential Vread is a potential such that the conducting state of the memory cell40is different according to the value stored in the memory cell40. The bit line potential Vbit is a potential such that a current flows between the bit line17and the source line13when the memory cell40is in the on-state. The off-potential Voff is a potential such that the memory cell40is set to the off-state regardless of the value of the memory cell40. As an example in the present embodiment, the read potential Vread is taken to be 2 V, the bit line potential Vbit is taken to be 0.5 V, and the off-potential Voff is taken to be 0 V.

Thereby, when the memory cell40sis in the off-state, a current does not flow between the source line13and the active bit line17aconnected to the memory cell40s. On the other hand, when the memory cell40sis in the on-state, a current flows between the source line13and the active bit line17aconnected to the memory cell40s, and the gate potential that is applied to the transistor43decreases. Thereby, a read current Iread flows into the sense amplifier41. In this way, when the memory cell40sis in the on-state, electrical charge from the active bit line17aconnected to the memory cell40sflows into the source line13via the memory cell40sto change the potential of the active bit line17a. A state of the memory cell40sis estimated by detecting the change of the potential of the active bit line17a.

Other than the current that flows in the active bit line17avia the memory cell40sthat is in the on-state, a leakage current flows in the local word lines21via the charge storage films23of all of the memory cells40connected to the active bit line17a. The leakage current is called a “gate leakage current”.

As described above, the memory cell40sis connected to the global word lines31marked with the numeral “1”. The local word lines21which belong to the gate structure bodies20associated with the reference bit line17rlocated at right side ofFIGS.8and9are not connected to the global word lines31marked with the numeral “1”. That is, the reference bit line17rat right-hand-side is not connected to the global word line31associated with the memory cell40s.

The bit line potential Vbit is applied to reference bit lines17rat right-hand-side, on the other hand, the off-potential Voff is applied to the local word lines21having the reference bit line17rinterposed. Thus, the dummy memory cells40ddo not conduct. Accordingly, only the gate leakage current flows in the reference bit line17rat right-hand-side. Therefore, the gate voltage of the transistor43connected to the reference bit line17ris a voltage potential determined by the leak amount via the dummy memory cells40d. As a result, a reference current Iref flows into the sense amplifier41connected to the reference bit line17r.

Then, the comparison circuit44determines the value of the memory cell40sby comparing an output SENVread of the sense amplifier41connected to the selected memory cell40sand an output SENVref of the sense amplifier41connected to the dummy memory cells40d.

At this time, the off-potential Voff is applied to the local word lines21having the reference bit line17rat right-hand-side interposed because the local word lines21are connected to the wide portions31bof global word lines31marked with the numerals “2” to “3”, but not connected to the global word line31marked with the numeral “1”. Thereby, the two dummy memory cells40dthat are connected to the reference bit line17rcan be reliably set to the off-state, and the flow of a current from the reference bit line17rto the source line13can be effectively suppressed. Thereby, the potential of the reference bit line17ris stabilized, and the accuracy of the read operation of the selected memory cell40sis increased.

When the value is read from the memory cell40connected to the global word lines31marked with the numeral “4”, the reference bit line17rthat is not interposed between the local word lines21connected to the global word lines31marked with the numeral “4”, that is, the reference bit line17rat right-hand-side is used. On the other hand, when the value is read from the memory cell40connected to the global word lines31marked with the numeral “2” or “3”, the reference bit line17rat left-hand-side is used.

A method for manufacturing the memory device according to the present embodiment will now be described.

Although several methods may be considered for the method for manufacturing the memory device described above, a method for making the global word lines by a sidewall double patterning process will be described in the present embodiment, in order to increase memory density of the memory devices. On the other hand, a method for making the global word lines by using single patterning as shown inFIG.8may be considered.

FIGS.11to14are plan views showing the method for manufacturing the memory device according to the first embodiment.

FIGS.15A to17Care cross-sectional views showing the method for manufacturing the memory device according to the first embodiment.

Because the global word lines31are not yet formed inFIGS.11to14, the numerals “1” to “4” that mark the global word lines31inFIG.8are placed on the contacts28that are connected to these global word lines31.

FIGS.15A to17Cillustrate the region where the basic portions31aof the global word lines31are formed and the region where the pad portion31cis formed next to each other;FIGS.15A to17Care illustrative only and do not correspond exactly to the plan views shown inFIGS.11to14.

First, the semiconductor substrate100is prepared as shown inFIG.2. Then, the circuit element formation layer131is formed in the semiconductor substrate100and above the semiconductor substrate100, and the lower layer interconnect layer132is formed on the circuit element formation layer131.

Then, the memory structure body30is made as shown inFIGS.3A and3B. The inter-layer insulating film111is formed at the periphery of the memory structure body30.

Continuing as shown inFIG.15A, a silicon nitride layer51, a silicon oxide layer52, an amorphous silicon layer53, and a silicon oxide layer54are formed in this order on the memory structure body30and on the inter-layer insulating film111.

Then, as shown inFIGS.11and15A, a pattern55is formed by performing a first lithography step. The pattern55may be, for example, a resist pattern or may be a pattern formed by transferring a resist pattern onto another material.

The pattern55covers the region where every other global word line31is formed in a subsequent process. In the example shown inFIG.11, the pattern55includes the region where the odd-numbered global word lines31are formed but does not include the region where the even-numbered global word lines31are formed. The local word lines21that are connected to the same global word line31in the memory device1after completion are either covered with the same pattern55or are not covered with any pattern55.

A first portion55a, a second portion55b, and a third portion55care continuous in the pattern55. The width, i.e., the length in the Y-direction, of the first portion55ais set to 2×, where × is the half pitch of the final global word lines (a width of the global word line31aalong the Y-direction inFIG.8); and the distance between the first portions55aadjacent to each other in the Y-direction also is set to 2×. Accordingly, the arrangement interval of the first portion55ais 4×. The width of the second portion55bis set to 4×; and the distance between the second portions55badjacent to each other in the Y-direction also is set to 4×. Accordingly, the arrangement interval of the second portion55bis 8×.

The width of the third portion55cis set to 6×; and the distance between the third portions55cadjacent to each other in the Y-direction is set to 2×. Accordingly, the arrangement interval of the third portion55cis 8×. In some embodiments, the width of the pad portion31cis set to be equal to the width of the wide portion31bin the global word line31after formation, the width of the third portion55cis set to 4×; and the distance between the third portions55cadjacent to each other in the Y-direction also is set to 4×. That is, the width of the third portion55cis, for example, adjustable from 4× to 6×. The case where the width of the third portion55cis set to 6× will now be described.

Then, as shown inFIG.15B, anisotropic etching such as RIE (Reactive Ion Etching), etc., of the silicon oxide layer54is performed using the pattern55as a mask and the amorphous silicon layer53as a stopper. The silicon oxide layer54is selectively removed thereby; the first portion55aof the pattern55is transferred onto a first portion54aof the silicon oxide layer54; the second portion55bof the pattern55is transferred onto a second portion54bof the silicon oxide layer54; and the third portion55cof the pattern55is transferred onto a third portion54cof the silicon oxide layer54. The patterned silicon oxide layer54is used as the mandrel members of the sidewall process described below.

Then, the silicon oxide layer54is slimmed as shown inFIGS.12and15C. For example, the slimming is performed by wet etching using DHF (Diluted Hydrofluoric Acid). The slimming amount is set to 0.5× per side surface. Thereby, the width of the first portion54aof the silicon oxide layer54is reduced from 2× to 1×; and the distance between the first portions54ais increased from 2× to 3×. The width of the second portion54bof the silicon oxide layer54is reduced from 4× to 3×; and the distance between the second portions54bis increased from 4× to 5×. The width of the third portion54cof the silicon oxide layer54is reduced from 6× to 5×; and the distance between the third portions54cis increased from 2× to 3×.

Continuing, a silicon nitride layer56is deposited as shown inFIG.15D. The thickness of the silicon nitride layer56is about 1×. The shape of the silicon nitride layer56reflects the pattern of the silicon oxide layer54. The silicon nitride layer56does not completely fill the gap between the pattern of the silicon oxide layer54.

Then, as shown inFIGS.13and16A, anisotropic etching such as RIE, etc., of the silicon nitride layer56is performed. The etching amount is slightly greater than about 1×. The portions of the silicon nitride layer56other than the portion located on the sidewall surface of the silicon oxide layer54are removed thereby. As a result, the silicon nitride layer56remains in a frame shape along the periphery of the silicon oxide layer54and becomes a sidewall structure. The width of each sidewall portion of the silicon nitride layer56is about 1×.

Continuing as shown inFIG.16B, the silicon oxide layer54that is used as the mandrel member is removed. For example, the removal is performed by wet etching using DHF. At this time, the silicon nitride layer56that is the sidewall is not removed and remains in a frame shape. In the present description, the frame shape of the silicon nitride layer56refers to the silicon nitride layer forming a closed loop frame around the silicon oxide layer54. In the cross-sectional view inFIG.16b, two pairs of sidewall structures are shown and each pair of sidewall structures of the silicon nitride layer56form one closed loop frame shaped structure.

Then, as shown inFIG.16C, anisotropic etching such as RIE, etc., of the amorphous silicon layer53is performed using the silicon nitride layer56as a mask and the silicon oxide layer52as a stopper. Thereby, the pattern of the silicon nitride layer56is transferred onto the amorphous silicon layer53. The amorphous silicon layer53has the same closed loop frame structure as the silicon nitride layer56.

Continuing as shown inFIGS.14and16D, patterns57aand57bare formed by performing a second lithography step. The pattern57ais formed at two adjacent closed loop frame shaped structures of the amorphous silicon layer53surrounding the contact28marked with the numeral “1” or the numeral “3” and the region between the two adjacent frame shaped structures of the amorphous silicon layers53. The pattern57ais located at the boundary between the regions where the global word lines31marked with the numeral “2” and the numeral “4” are to be formed. The pattern57amay be formed to cover or overlap at least partially the two adjacent structures of the amorphous silicon layers53for robustness of the patterning. However, the pattern57ashould not cover the region surround by each of the closed loop frame shaped structure of the amorphous silicon layers53. That is, the pattern57ais positioned in an open region outside the frame-shaped structures of the amorphous silicon layer53and between two frame-shaped structures of the amorphous silicon layer53. But the pattern57adoes not cover the region surrounded by each of the frame-shaped structure of the amorphous silicon layer53. Thus, the pattern57adoes not affect the function of the two global word lines31marked with the numeral “1” and the numeral “3”. The pattern57bis formed to surround the contact28located outside the frame-shaped amorphous silicon layer53.

In the example shown inFIG.14, the regions where the odd-numbered global word lines31are to be formed in a subsequent process are surrounded with the frame-shaped structure of the amorphous silicon layer53. On the other hand, the regions where the even-numbered global word lines31are to be formed are located outside the frame-shaped structures of the amorphous silicon layer53and are formed between the frame-shaped structures of the amorphous silicon layers53. The pattern57acovers the region between the two adjacent closed loop fame-shaped structures of the amorphous silicon layer53in the X-Y plane. In the present embodiment, the length in the Y-direction of the pattern57ais set to 3×. The position of the pattern57ahas a margin of ±1× in the Y-direction, which corresponds to the width of the amorphous silicon layer53.

On the other hand, the pattern57bis formed in the region surrounding the region where the pad portions31cof the even-numbered global word lines31are formed. Thereby, the region where the global word lines31are formed is defined by the amorphous silicon layers53, the pattern57a, and the pattern57b.

Then, as shown inFIG.17A, anisotropic etching such as RIE, etc., of the silicon oxide layer52is performed using the amorphous silicon layers53and the patterns57aand57bas a mask and the silicon nitride layer51as a stopper. Then, anisotropic etching such as RIE, etc., of the silicon nitride layer51is performed. Thereby, openings58are formed in the regions of the silicon oxide layer52and the silicon nitride layer51where the global word lines31are to be formed. Then, the patterns57aand57band the amorphous silicon layers53are removed.

Continuing as shown inFIG.17B, a metal film59is formed by depositing a metal, e.g., copper. The metal film59is formed inside the openings58and on the upper surface of the silicon oxide layer52.

Then, as shown inFIGS.8and17C, the silicon oxide layer52is exposed by performing planarization such as CMP (Chemical Mechanical Polishing), etc., of the metal film59. The portion of the metal film59that is located on the upper surface of the silicon oxide layer52is removed thereby. The portions of the metal film59that remain inside the opening58become the global word lines31. Thus, the multiple global word lines31are formed, and the memory array portion133is formed.

Continuing, the upper layer interconnect layer134is formed as shown inFIG.2. Then, a lattice-like trench is formed in the passivation film112and the inter-layer insulating film111. The portions that are defined by the trench become the tiles101. Thereby, as shown inFIG.1, the multiple tiles101are made on the semiconductor substrate100. Thus, the memory device1according to the present embodiment is manufactured.

Effects of the present embodiment will now be described.

In the memory device1according to the first embodiment, when the value is read from the selected memory cell40sas shown inFIG.10, the potential change of the active bit line17aconnected to the memory cell40sis detected; the potential change of at least one of the reference bit line17ris detected; and the two are compared. Thereby, the effects of the gate leakage current are somewhat canceled, and the value that is stored in the memory cell40scan be read with high accuracy and in a short time.

According to the embodiment as shown inFIG.8, the local word lines21at positions having the reference bit line17rinterposed are not connected to the global word line31that is connected to the memory cell40s. Thereby, the read potential Vread is not applied to the local word lines21having the reference bit line17rinterposed, and the off-potential Voff is applied to them. Therefore, the dummy memory cells40dthat are connected to the reference bit line17rcan be reliably set to the off-state; therefore, the potential of the reference bit line17ris stabilized. The accuracy of the read operation is further increased thereby.

According to the embodiment as shown inFIG.11, the pattern55is formed as a mandrel member by the first lithography. At this time, the local word lines21that are connected to the same global word line31in the memory device1after completion are either covered with the same pattern55or not covered with any pattern55. Then, the mandrel member is slimmed as shown inFIG.12, the amorphous silicon layer53is formed as a sidewall at the periphery of the mandrel member as shown inFIG.13, and the mandrel member is removed. At this stage, the region where some (e.g., the odd-numbered) global word lines31are formed is enclosed by the amorphous silicon layers53, and the region where the remaining (e.g., the even-numbered) global word lines31are formed is not enclosed and is positioned outside the closed loop frame shaped structures of the amorphous silicon layer53. Then, as shown inFIG.14, the patterns57aand57bare formed by the second lithography step. The pattern57asubdivides, into two regions along the X-direction, the open region between the two adjacent frame-shaped structures of the amorphous silicon layer53in the Y-direction; and the pattern57bsurrounds the X-direction end portion of the subdivided region. As a result, the region where the remaining (e.g., the even-numbered) global word lines31are to be formed is now appropriately defined by the pattern57aand the pattern57b.

Thus, the basic portion31athat has a width and a spacing of 1× each is formed by a sidewall process, and the global word line31that also includes the wide portion31bhaving a width of3xand the pad portion31chaving a width of 5× can be formed by the second lithography step. Accordingly, the global word lines31can make be made with smaller dimensions using the sidewall double patterning process. And, the reference bit lines17rwhich is not applied the read potential Vread can be fabricated by avoiding periodical patterning's limitation caused by the sidewall double patterning process itself.

It also may be considered to form a global word line having the desired shape by forming a mandrel member in a first lithography step, forming a closed loop frame-shaped pattern having a width and a spacing of 1× each by a sidewall process, by cutting the frame-shaped pattern by a second lithography step, and by forming an additional pattern by a third lithography step. However, in such a case, a total of three lithography steps are necessary, and the process cost increases. Also, because the width and the spacing of the frame-shaped pattern formed by the sidewall process are 1×, the margin of the second lithography becomes ±0.5× in the Y-direction, and the difficulty of the process increases. Conversely, according to the present embodiment, the global word line that has the desired shape can be formed by two lithography steps while maintaining a lithography margin of ±1× in the Y-direction.

Second Embodiment

The following description describes mainly the differences between the first and the second embodiments, and a description of the portions that are similar or the same as the first embodiment is omitted.

FIG.18is a plan view showing the memory structure body and the global word lines of the second embodiment.

As shown inFIG.18, the shape of the global word line31of a memory device2according to the second embodiment is different from that of the memory device1according to the first embodiment (as shown inFIG.8). Specifically, the wide portion31bof the first embodiment is not provided in the global word line31of the second embodiment. Instead, a diagonal portion31dis provided in the global word line31of the present embodiment and is provided between the basic portion31aand the pad portion31c. Similar to the first embodiment, the basic portion31aextends in the X-direction. The diagonal portion31dextends in a direction that is oblique to the X-direction and the Y-direction. The width of the diagonal portion31dis substantially equal to the width of the basic portion31a.

The diagonal portion31dis located in the region directly above the reference bit line17rand the gate structure bodies20at the two sides of the reference bit line17r. Thereby, the two local word lines21that have the reference bit line17rinterposed are connected to the diagonal portion31dof the same global word line31. In particular, the two local word lines21connected to the diagonal portion31dof the same global word line31are staggered in the Y-direction. Thus, the local word lines21associated with the reference bit line17rlocated at one side of the memory structure body are connected to one set of the global word lines31only, for example, the odd global word lines. Meanwhile, the local word lines21associated with the reference bit line17rlocated at the other side of the memory structure body are connected to another set of the global word lines31only, for example, the even global word lines. For example, the local word lines21associated with the reference bit line17rlocated at left-hand-side inFIG.18are connected to the global word lines31marked with the numeral “1” and “3”, and are not connected to the global word lines31marked with the numeral “2” and “4”. On the other hand, the local word lines21located associated with the reference bit line17rlocated at right-hand-side inFIG.18are connected to the global word lines31marked with the numeral “2” and “4”, and not connected to the global word lines31marked with the numeral “1” and “3”.

On the other hand, the basic portion31ais located in the region directly above the active bit lines17a, the dummy bit line17d, the gate structure body20between the active bit lines17a, and the gate structure body20between the active bit line17aand the dummy bit line17d. Thereby, the local word lines21that are connected to the memory cells40are connected to the basic portion31aof the global word line31.

According to the second embodiment, even when the wide portion31bis not provided in the global word line31, the local word lines21associated with the reference bit line17ris prevented from connecting to the global word line31connected to the selected memory cell40sto be read.

Because the width of the diagonal portion31dis substantially equal to the width of the basic portion31a, the arrangement interval of the diagonal portion31dcan be equal to the arrangement interval of the basic portion31ain the Y-direction. Therefore, the diagonal portion31dcan be located at any position in the X-direction in the region directly above the memory structure body30. Therefore, the arrangement position of the reference bit line17ris not limited to the two X-direction end portions of the memory structure body30and can be placed in any position within the memory structure body30, such as in the middle of the memory structure body.

Furthermore, as shown by region D inFIG.18, at the diagonal portion31d, the spacing between two adjacent global word lines31can be small.

Otherwise, the configuration, the operations, and the effects of the second embodiment are similar to those of the first embodiment described above.

Third Embodiment

FIG.19is a plan view showing the memory structure body and the global word lines of the third embodiment.

As shown inFIG.19, the shape of the global word line31of a memory device3according to the third embodiment also is different from that of the memory device according to the first embodiment (FIG.8). Specifically, in the global word line31of the third embodiment, the wide portion31bof the first embodiment (FIG.8) is not provided, and the diagonal portion31dof the second embodiment (FIG.18) is also not provided. In the global word line31of the third embodiment, the basic portion31ais directly linked to the pad portion31c.

In the memory device3according to the third embodiment, the local word lines21that are associated a reference bit line17r(that is, the local word lines21that are formed on the two sides of a reference bit line17r) are not staggered but are positioned in substantially the same location in the Y-direction. Meanwhile, the local word lines21associated with a first reference bit line17r(e.g. the reference bit line17ron the right) and the local word lines21associated with a second reference bit line17r(e.g. the reference bit line17ron the left) are positioned staggered from each other. Thereby, a pair of local word lines21formed on two sides of a given reference bit line17rare connected to the basic portion31aof the same global word line31. Furthermore, the local word lines21that are associated with different reference bit lines17rare connected to the basic portion31aof different global word lines31.

As a result, the local word lines21located at two sides of a first reference bit line17rare connected to one set of the global word lines31only, for example, the odd global word lines. Meanwhile, the local word lines21located at two sides of a second reference bit line17rare connected to another set of the global word lines31only, for example, the even global word lines. For example, the local word lines21located at two sides of the reference bit line17rlocated at left-hand-side inFIG.19are connected to the global word lines31marked with the numeral “2” and “4”, and not connected to the global word lines31marked with the numeral “1” and “3”. On the other hand, the local word lines21located at two sides of the reference bit line17rlocated at right-hand-side inFIG.19are connected to the global word lines31marked with the numeral “1” and “3”, and not connected to the global word lines31marked with the numeral “2” and “4”.

A method for manufacturing the memory device according to the third embodiment will now be described.

FIGS.20A and20Bare plan views showing the method for manufacturing the memory device according to the third embodiment.

As shown inFIG.20A, an intermediate structure body60is made in which the multiple source-drain structure bodies10and the plate-shaped insulating members22are alternately arranged along the X-direction. In the intermediate structure body60, a sacrificial member that is made of, for example, silicon nitride may be formed instead of the source line13and the bit line17.

Then, as shown inFIG.20B, a mask pattern61is formed on the intermediate structure body60. Openings62aand62bare formed in the mask pattern61. When viewed from the Z-direction, the openings62aand62bare, for example, substantially elliptical. The length in the Y-direction of the opening62bis substantially equal to the length in the Y-direction of the opening62a. The length in the X-direction of the opening62bis greater than the length in the X-direction of the opening62a. As thus configured, one insulating member22is exposed inside the opening62awhile two adjacent insulating members22and one source-drain structure body10between the two adjacent insulating members22are exposed inside the opening62b.

Continuing, anisotropic etching such as RIE, etc., of the insulating members22is performed using the mask pattern61as a mask. Thereby, holes63aand63bare formed in the insulating members22. The hole63ais formed in a part of a region directly below the opening62a, and the hole63bis formed in a part of a region directly below the opening62b. The source-drain structure body10is exposed at the side surfaces of the holes63aand63bfacing the X-direction. At this time, the source-drain structure body10is substantially not etched because the etching is impeded by the insulating body12made of silicon oxycarbide (SiOC) or an etching stop layer provided above the insulating body12. Therefore, when viewed from the Z-direction, the portion of the reference bit line17rthat overlaps the hole63bis not etched. When sacrificial members are formed instead of the source line13and the bit line17in the intermediate structure body60, the sacrificial members may be replaced with metal members via the holes63aand63b.

Then, the mask pattern61is removed. Then, sacrifice members64are filled in the holes63aand63b. And then, portions of the insulation members22located between holes63aand between holes63bare removed. Thereby, holes65aand65bare formed between the sacrifice members64. The arrangement pattern of the holes65aand65bis a pattern in which the arrangement pattern of the holes63aand63bis inverted in the insulation members22. Then, the charge storage films23are formed on the inner surfaces of the holes65aand65b. Then, the local word lines21are formed by filling a metal material into the holes65aand65b. Local word lines21aof the local word lines21formed in the holes65aare located between two of the holes63afilled by the sacrifice member64. On the other hand, local word lines21bof the local word lines21formed in the holes65bare located between two of the holes63bfilled by the sacrifice member64. Then, the sacrifice members64are removed from the holes63aand63b. Then, insulating material such as silicon oxide is backfilled in the holes63aand63bto form a part of the insulating member22. Thus, the memory structure body30is manufactured.

The local word lines21bthat are located at the two sides of the reference bit line17rare formed in the holes65band therefore have different shapes when viewed from the Z-direction from the local word lines21aformed in the holes65a.

In the third embodiment shown inFIG.19, it is unnecessary to provide the wide portion31bin the global word line31; therefore, the reference bit line17rcan be located at any position in the X-direction of the memory structure body30. Also, it is unnecessary to provide the diagonal portion31din the global word line31; therefore, the portion where the short spacing as shown by region D ofFIG.18does not occur.

Otherwise, the configuration, the operations, and the effects of the third embodiment are similar to those of the first embodiment described above. Although an example is shown in the third embodiment in which the opening62bof the mask pattern61has a size that extends over two insulating members22, the size is not limited thereto; the size may extend over three or more insulating members22.

Fourth Embodiment

FIG.21is a plan view showing the memory structure body and the global word lines of the fourth embodiment.

As shown inFIG.21, the configuration of the global word line31of a memory device4according to the fourth embodiment is similar to that of the third embodiment. Namely, in the global word line31, the basic portion31aand the pad portion31care provided, but the wide portion31bFIG.8) and the diagonal portion31d(18) are not provided.

In the memory device4, two adjacent bit lines17of the multiple bit lines17are used as the reference bit lines17r. The two adjacent reference bit lines17rare connected to each other in a region, e.g., the upper layer interconnect layer134or the lower layer interconnect layer132, other than the region between these two reference bit lines17r. Therefore, the same potential is constantly applied to the two adjacent reference bit lines17r.

Between the two adjacent reference bit lines17r, one plate-shaped insulating member22may be provided, or multiple columnar insulating members22and conductive bodies similar to the local word lines21may be alternately arranged along the Y-direction. However, the reference bit line17rdoes not function as a bit line driving the memory cells; therefore, the conductive bodies that are located between a pair of reference bit line17rdo not function as the local word lines21.

According to the fourth embodiment, it is unnecessary to provide the wide portion31bin the global word line31; therefore, the reference bit line17rcan be located at any position in the X-direction of the memory structure body30. Also, it is unnecessary to provide the diagonal portion31din the global word line31; therefore, the portion where the short spacing as shown by region D ofFIG.18does not easily occur. When viewed from the Z-direction, the shapes of the local word lines21located at the two sides of the two adjacent reference bit lines17rcan be the same as the shapes of the other local word lines21.

As a result, the local word lines21located at two sides of a first pair of adjacent reference bit lines17r(e.g. the reference bit line pair on the left hand side) are connected to one set of the global word lines31. Meanwhile, the local word lines21located at two sides of a second pair of adjacent reference bit lines17r(e.g. the reference bit line pair on the right hand side) are connected to another set of the global word lines31. For example, the local word lines21located at two sides of the two reference bit lines17rlocated at left-hand-side inFIG.21are connected to the global word lines31marked with the numeral “1” and “3”, and not connected to the global word lines31marked with the numeral “2” and “4”. On the other hand, the local word lines21located at two sides of the two adjacent reference bit lines17rlocated at right-hand-side inFIG.21are connected to the global word lines31marked with the numeral “2” and “4”, and not connected to the global word lines31marked with the numeral “1” and “3”.

Otherwise, the configuration, the operations, and the effects of the fourth embodiment are similar to those of the first embodiment described above.

Fifth Embodiment

FIG.22is a plan view showing the memory structure body and the global word lines of the fifth embodiment.

In a memory device5according to the fifth embodiment as shown inFIG.22, two adjacent bit lines17of the multiple bit lines17are used as the reference bit lines17r. The two adjacent reference bit lines17ris connected to each other via a connection portion17cextending in the X-direction. Therefore, the same potential is constantly applied to the two adjacent reference bit lines17r. The connection portion17cis provided inside the memory structure body30in each layer including the bit line17.

Otherwise, the configuration, the operations, and the effects of the fifth embodiment are similar to those of the fourth embodiment described above.

The embodiments described above are examples embodying the invention; and the invention is not limited to these embodiments. For example, additions, deletions, or modifications of some of the components or processes of the embodiments described above also are included in the invention. The embodiments described above can be implemented in combination with each other.