Patent ID: 12260933

DETAILED DESCRIPTION

The technical solutions in the embodiments of the present disclosure are described below clearly and completely with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are merely some rather than all of the embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative efforts should fall within the protection scope of the present disclosure. It should be noted that the embodiments in the present disclosure and features in the embodiments may be combined with each other in a non-conflicting manner.

It can be known from the background that the adjustment capability of the equalization circuit to the signals needs to be improved.

The embodiments of the present disclosure provide a data receiving circuit, a data receiving system, and a memory device. In the data receiving circuit, the decision feedback equalization module is integrated in the data receiving circuit, and is configured to adjust the first output signal and the second output signal to reduce intersymbol interference between signals outputted by the data receiving circuit. Moreover, the embodiments of the present disclosure are beneficial to adjust the signals outputted by the data receiving circuit using a smaller circuit layout area and lower power consumption, and reduce, by flexibly controlling the adjustment capability of the decision feedback equalization module to the first output signal and the second output signal, the influence of the intersymbol interference of the data received by the data receiving circuit on the data receiving circuit, thereby improving the receiving performance of the data receiving circuit, and reducing the influence of the intersymbol interference of the data on the accuracy of the signal outputted by the data receiving circuit.

One embodiment of the present disclosure provides a data receiving circuit. The data receiving circuit provided by one embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.FIG.1is a functional block diagram of a data receiving circuit according to one embodiment of the present disclosure;FIG.3andFIG.4are another two functional block diagrams of a data receiving circuit according to one embodiment of the present disclosure;FIG.5is a schematic diagram of a circuit structure of a data receiving circuit according to one embodiment of the present disclosure;FIG.6andFIG.7are schematic diagrams of two circuit structures of a first decision feedback unit in a data receiving circuit according to one embodiment of the present disclosure; andFIG.8andFIG.9are schematic diagrams of another two circuit structures of a data receiving circuit according to one embodiment of the present disclosure.

Referring toFIG.1, the data receiving circuit110includes: a receiving module100configured to receive a data signal DQ and a reference signal Vref, compare the data signal DQ and the reference signal Vref in response to a sampling clock signal CLK1, and output a first output signal Vout and a second output signal VoutN; and a decision feedback equalization module103connected to a feedback node of the receiving module100, and configured to perform decision feedback equalization on the receiving module100on the basis of a feedback signal to adjust the first output signal Vout and the second output signal VoutN, where the feedback signal is obtained on the basis of data received previously, and an adjustment capability of the decision feedback equalization module103to the first output signal Vout and the second output signal VoutN is adjustable.

The decision feedback equalization module103is integrated in the data receiving circuit, which is beneficial to adjust the signals outputted by the data receiving circuit using a smaller circuit layout area and lower power consumption. Moreover, the adjustment capability of the decision feedback equalization module103provided in the embodiments of the present disclosure to the first output signal Vout and the second output signal VoutN is adjustable. It can be understood that, when the data signal DQ and/or the reference signal Vref received by the receiving module100change, the adjustment capability of the decision feedback equalization module103to the first output signal Vout and the second output signal VoutN may be flexibly controlled, to reduce the influence of the intersymbol interference of the data received by the data receiving circuit on the data receiving circuit, improve the receiving performance of the data receiving circuit, and reduce the influence of the intersymbol interference of the data on the accuracy of the signals outputted by the data receiving circuit.

It should be noted that, the connection between the decision feedback equalization module103and the feedback node of the receiving module100includes at least the following two examples.

In some embodiments, referring toFIG.3, the receiving module100(referring toFIG.1) may include: a first amplification module101configured to receive the data signal DQ and the reference signal Vref, compare the data signal DQ and the reference signal Vref in response to the sampling clock signal CLK1, output a first voltage signal through a first node n_stg1, and output a second voltage signal through a second node p_stg1; and a second amplification module102connected to the first node n_stg1and the second node p_stg1, and configured to amplify a voltage difference between the first voltage signal and the second voltage signal, output the first output signal Vout through a third node net3(referring toFIG.5), and output the second output signal VoutN through a fourth node net4(referring toFIG.5); where, the feedback node includes a first feedback node and a second feedback node, the first node n_stg1serves as the first feedback node, the second node p_stg1serves as the second feedback node, and the decision feedback equalization module103is configured to perform the decision feedback equalization on the first node n_stg1and the second node p_stg1on the basis of the feedback signal to adjust the first voltage signal and the second voltage signal.

It should be noted that, the second amplification module102receives the first voltage signal and the second voltage signal, and amplify the voltage difference between the first voltage signal and the second voltage signal to output the first output signal Vout and the second output signal VoutN. That is, the first output signal Vout and the second output signal VoutN are affected by the first voltage signal and the second voltage signal, and the decision feedback equalization module103adjusts the first voltage signal and the second voltage signal on the basis of the feedback signal, which may also further adjust the first output signal Vout and the second output signal VoutN. Moreover, the adjustment of the first voltage signal and the second voltage signal by the decision feedback equalization module103is described in detail later with reference to specific circuit diagrams.

In some embodiments, still referring toFIG.3, the data receiving circuit may further include: an offset compensation module104connected to the second amplification module102and configured to compensate for an offset voltage of the second amplification module102. It should be noted that, the specific connection relationship between the offset compensation module104and the second amplification module102is described in detail later with reference to specific circuit diagrams.

In some other embodiments, referring toFIG.9, the receiving module100(referring toFIG.1) may include: a first amplification module101configured to receive the data signal DQ and the reference signal Vref, compare the data signal DQ and the reference signal Vref in response to the sampling clock signal CLK1, output a first voltage signal through a first node n_stg1, and output a second voltage signal through a second node p_stg1; and a second amplification module102connected to the first node n_stg1and the second node p_stg1, configured to amplify a voltage difference between the first voltage signal and the second voltage signal, output the first output signal Vout through a third node net3and output the second output signal VoutN through a fourth node net4, and provided with a first internal node n_stg2and a second internal node p_stg2, the first output signal Vout and the second output signal VoutN being obtained on the basis of a signal of the first internal node n_stg2and a signal of the second internal node p_stg2; where, the feedback node includes a first feedback node and a second feedback node, the first internal node n_stg2serves as the first feedback node, the second internal node p_stg2serves as the second feedback node, and the decision feedback equalization module103is configured to perform the decision feedback equalization on the first internal node n_stg2and the second internal node p_stg2on the basis of the feedback signal.

It should be noted that, the voltage signal at the first internal node n_stg2is a third voltage signal, and the voltage signal at the second internal node p_stg2is a fourth voltage signal. The decision feedback equalization module103is configured to perform the decision feedback equalization on the first internal node n_stg2and the second internal node p_stg2on the basis of the feedback signal. That is, the decision feedback equalization module103adjusts the third voltage signal and the fourth voltage signal. The first output signal Vout and the second output signal VoutN are based on the third voltage signal and the fourth voltage signal, and the decision feedback equalization module103adjusts the third voltage signal and the fourth voltage signal on the basis of the feedback signal, which may also further adjust the first output signal Vout and the second output signal VoutN. Moreover, the adjustment of the third voltage signal and the fourth voltage signal by the decision feedback equalization module103is described in detail later with reference to specific circuit diagrams.

In some embodiments, the data receiving circuit may further include: an offset compensation module connected to the first amplification module and configured to compensate for an offset voltage of the first amplification module. It should be noted that, the specific connection relationship between the offset compensation module and the first amplification module is described in detail later.

In the above two examples, the data receiving circuit employs two stages of amplification modules, namely the first amplification module101and the second amplification module102for processing the data signal DQ and the reference signal Vref, which is conducive to enhancing the amplification capability of the data receiving circuit, increasing the voltage amplitudes of the first output signal Vout and the second output signal VoutN, and facilitating subsequent circuit processing. In addition, the decision feedback equalization module103is configured to reduce the intersymbol interference by equivalently adjusting the data signal DQ.

The specific structure of the data receiving circuit according to one embodiment of the present disclosure is described in detail below with reference toFIG.4toFIG.9. It should be noted that, the following specific description of each module is applicable to the foregoing two examples.

In some embodiments, referring toFIG.4, the first amplification module101may include: a current source111connected between a power supply node Vcc (referring toFIG.5) and a fifth node net5and configured to provide a current to the fifth node net5in response to the sampling clock signal CLK1; and a comparison unit121connected to the fifth node net5, the first node n_stg1, and the second node p_stg1, and configured to receive the data signal DQ and the reference signal Vref, compare the data signal DQ and the reference signal Vref when the current source111provides the current to the fifth node net5in response to the sampling clock signal CLK1, output the first voltage signal through the first node n_stg1, and output the second voltage signal through the second node p_stg1.

It can be understood that, the comparison unit121may control a difference between the current provided to the first node n_stg1and the current provided to the second node p_stg1on the basis of a difference between the data signal DQ and the reference signal Vref, to output the first voltage signal and the second voltage signal.

The first amplification module101is described in detail below with reference toFIG.5,FIG.8, andFIG.9.

In some embodiments, referring toFIG.5,FIG.8, andFIG.9, the current source111may include: a first P-channel metal oxide semiconductor (PMOS) transistor MP1connected between the power supply node Vcc and the fifth node net5and provided with a gate for receiving the sampling clock signal CLK1. When the sampling clock signal CLK1is at a low level, the gate of the first PMOS transistor MP1receives the sampling clock signal CLK1to be turned on, and provides the current to the fifth node net5, such that the comparison unit121is in an operating state to compare the received data signals DQ and the reference signal Vref.

In some embodiments, still referring toFIG.8, on the basis that the current source111includes the first PMOS transistor MP1, the current source111may further include: a second PMOS transistor MP2connected between the power supply node Vcc and the first PMOS transistor MP1and provided with a gate for receiving an enable signal SampEnN. When the sampling clock signal CLK1is at a low level, and the enable signal SampEnN is also at a low level, the first PMOS transistor MP1and the second PMOS transistor MP2are both turned on to provide the current to the fifth node net5, such that the comparison unit121is in the operating state to compare the received data signals DQ and the reference signal Vref.

In addition, setting the second PMOS transistor MP2in an on or off state based on the enable signal SampEnN is beneficial to control the second PMOS transistor MP2to turn off based on the enable signal SampEnN when a device including the data receiving circuit is in a low-power-consumption mode, to turn off the data receiving circuit corresponding to the second PMOS transistor MP2, thereby reducing the overall power consumption of the device including the data receiving circuit.

In some embodiments, referring toFIG.5,FIG.8, andFIG.9, the comparison unit121may include: a third PMOS transistor MP3connected between the fifth node net5and the first node n_stg1and provided with a gate for receiving the data signal DQ; and a fourth PMOS transistor MP4connected between the fifth node net5and the second node p_stg1and provided with a gate for receiving the reference signal Vref.

It should be noted that, the level of the data signal DQ and the level of the reference signal Vref are changed asynchronously, such that the turn-on moment of the third PMOS transistor MP3for receiving the data signal DQ is different from the turn-on moment of the fourth PMOS transistor MP4for receiving the reference signal Vref; and at the same moment, the turn-on degree of the third PMOS transistor MP3is different from the turn-on degree of the fourth PMOS transistor MP4. It can be understood that, since the turn-on degree of the third PMOS transistor MP3is different from the turn-on degree of the fourth PMOS transistor MP4, and the shunt capability of the third PMOS transistor MP3to the current at the fifth node net5is also different from the shunt capability of the fourth PMOS transistor MP4to the current at the fifth node net5, the voltage at the first node n_stg1is different from the voltage at the second node p_stg1.

In one example, when the level of the data signal DQ is lower than the level of the reference signal Vref, the turn-on degree of the third PMOS transistor MP3is greater than the turn-on degree of the fourth PMOS transistor MP4, such that the current at the fifth node net5flows more into a path where the third PMOS transistor MP3is located, and the current at the first node n_stg1is greater than the current at the second node p_stg1, and furthermore, the level of the first voltage signal outputted by the first node n_stg1is high, and the level of the second voltage signal outputted by the second node p_stg1is low.

In some embodiments, referring toFIG.4, the first amplification module101may further include: a first reset unit131connected to the first node n_stg1and the second node p_stg1and configured to reset the first node n_stg1and the second node p_stg1. Thus, after the data receiving circuit completes reception of the data signal DQ and the reference signal Vref and the output of the first output signal Vout and the second output signal VoutN once, the first reset unit131may reset the level at the first node n_stg1and the level at the second node p_stg1to an original value, such that the data receiving circuit subsequently performs next data reception and processing.

In some embodiments, still referring toFIG.5,FIG.8, andFIG.9, the first reset unit131may include: a first N-channel metal oxide semiconductor (NMOS) transistor MN1connected between the first node n_stg1and a ground terminal and provided with a gate for receiving the sampling clock signal CLK1; and a second NMOS transistor MN2connected between the second node p_stg1and the ground terminal and provided with a gate for receiving the sampling clock signal CLK1.

In one example, when the sampling clock signal CLK1and the enable signal SampEnN are both at a low level, the first PMOS transistor MP1and the second PMOS transistor MP2are both turned on, and at this time, the first NMOS transistor MN1and the second NMOS transistor MN2are both turned off, to ensure normal operation of the data receiving circuit. Moreover, the first NMOS transistor MN1and the second NMOS transistor MN2may serve as a load of the first amplification module101to increase an amplification gain of the first amplification module101. When the sampling clock signal CLK1is at a high level, the first PMOS transistor MP1is turned off, and at this time, the first NMOS transistor MN1and the second NMOS transistor MN2are both turned on, to pull down the voltage at the first node n_stg1and the voltage at the second node p_stg1to reset the first node n_stg1and the second node p_stg1.

The decision feedback equalization module103is described in detail below through two examples. In one example, the decision feedback equalization module103is connected to the first node n_stg1and the second node p_stg1in the first amplification module101, to adjust the first voltage signal and the second voltage signal outputted by the first amplification module101. In the other example, the decision feedback equalization module103is connected to the first internal node n_stg2and the second internal node p_stg2in the second amplification module102, to adjust the voltage at the first internal node n_stg2and the voltage at the second internal node p_stg2.

In some embodiments, referring toFIG.5andFIG.8, the first node n_stg1may serve as the first feedback node, the second node p_stg1serves as the second feedback node, and the feedback signal includes a first feedback signal fbn and a second feedback signal fbp. The decision feedback equalization module103may include: a first decision feedback unit113connected to the first node n_stg1and the fifth node net5, and configured to perform the decision feedback equalization on the first node n_stg1on the basis of the first feedback signal fbn to adjust the first voltage signal; and a second decision feedback unit123connected to the second node p_stg1and the fifth node net5, and configured to perform the decision feedback equalization on the second node p_stg1on the basis of the second feedback signal fbp to adjust the second voltage signal.

The first decision feedback unit113is configured to adjust the current in the third PMOS transistor MP3to adjust the voltage at the first node n_stg1, which is equivalent to adjust the data signal DQ. The second decision feedback unit123is configured to adjust the current in the fourth PMOS transistor MP4to adjust the voltage at the second node p_stg1, which is equivalent to adjust the reference signal Vref.

In some embodiments, referring toFIG.6andFIG.7, any one of the first decision feedback unit113and the second decision feedback unit123includes: a switch unit1131configured to turn on the fifth node net5and a sixth node net6in response to the feedback signal; and an adjustment unit1132connected between the sixth node net6and an output node as one of the first node n_stg1and the second node p_stg1, and configured to adjust an equivalent resistance between the sixth node net6and the output node in response to control signals. In the first decision feedback unit113, the feedback signal is the first feedback signal fbn, the output node is the first node n_stg1, and the switch unit1131responds to the first feedback signal fbn; and in the second decision feedback unit123, the feedback signal is the second feedback signal fbp, the output node is the second node p_stg1, and the switch unit1131responds to the second feedback signal fbp.

The switch unit1131in the first decision feedback unit113is turned on or off on the basis of the first feedback signal fbn, and the switch unit1131in the second decision feedback unit123is turned on or off on the basis of the second feedback signal fbp. Regardless of whether it is the first decision feedback unit113or the second decision feedback unit123, when the switch unit1131is turned on, the adjustment unit1132is in the operating state to adjust the voltage at the first node n_stg1or the second node p_stg1.

In some embodiments, still referring toFIG.6andFIG.7, the switch unit1131may include: a fifth PMOS transistor MP5connected between the fifth node net5and the sixth node net6and provided with a gate for receiving the feedback signal.

It should be noted that, inFIG.6andFIG.7, only an example where the gate of the fifth PMOS transistor MP5receives the first feedback signal fbn and the output node is the first node n_stg1is given, and the specific structure of the first decision feedback unit113is shown. In practical applications, the specific structure of the second decision feedback unit123is similar to that of the first decision feedback unit113, the differences are that the gate of the fifth PMOS transistor MP5in the second decision feedback unit123receives the second feedback signal fbp and the output node is the second node p_stg1, and other places are the same.

In one example, the first feedback signal fbn received by the switch unit1131in the first decision feedback unit113is at a low level, the fifth PMOS transistor MP5is turned on, and at this time, the adjustment unit1132adjusts the voltage at the first node n_stg1on the basis of the control signal. In another example, the second feedback signal fbp received by the switch unit1131in the second decision feedback unit123is at a low level, the fifth PMOS transistor MP5is turned on, and at this time, the adjustment unit1132adjusts the voltage at the second node p_stg1on the basis of the control signal.

In some embodiments, still referring toFIG.6andFIG.7, the adjustment unit1132may include: a plurality of transistor groups connected in parallel between the sixth node net6and the output node, where control terminals of the different transistor groups receive different control signals, and the different transistor groups have different equivalent resistances. It can be understood that, the difference in equivalent resistances of the different transistor groups makes the overall equivalent resistance of the adjustment unit1132flexible and controllable. If the control signals received by the control terminals of the different transistor groups are different, the number of transistor groups in a turn-on state may be selected through the control signals to adjust the overall equivalent resistance of the adjustment unit1132, thereby flexibly controlling the voltage at the first node n_stg1.

In one example, referring toFIG.6, the adjustment unit1132may include three single MOS transistors connected in parallel between the sixth node net6and the first node n_stg1, namely a first MOS transistor M01, a second MOS transistor M02, and a third MOS transistor M03in sequence. A gate of the first MOS transistor M01receives a first control signal DfeTrim<2>, a gate of the second MOS transistor M02receives a second control signal DfeTrim<1>, and a gate of the third MOS transistor M03receives a third control signal DfeTrim<0>.

In some embodiments, referring toFIG.7, the different transistor groups may include: at least one of the transistor groups including a single MOS transistor; and at least one of the transistor groups including at least two MOS transistors connected in series. In this way, one transistor group may be formed by using several single MOS transistors connected in series having the same channel aspect ratio to adjust the equivalent channel aspect ratio of the transistor group, thereby realizing various designs of the adjustment unit1132. It can be understood that, the difference in the equivalent channel aspect ratios of the transistor groups may cause the equivalent resistances of the transistor groups to be different.

In one example, the adjustment unit may include a first transistor group, a second transistor group, and a third transistor group connected in parallel between the sixth node and the first node. The first transistor group includes the first MOS transistor, and the gate of the first MOS transistor receives the first control signal. The second transistor group includes the second MOS transistor, and the gate of the second MOS transistor receives the second control signal. The third transistor group includes the third MOS transistor and a fourth MOS transistor connected in series, the fourth MOS transistor is provided with a first terminal connected to the sixth node and a second terminal connected to a first terminal of the third MOS transistor, a second terminal of the third MOS transistor is connected to the first node, and a gate of the third MOS transistor and a gate of the fourth MOS transistor both receive the third control signal.

In another example, referring toFIG.7, in addition to the first transistor group13, the second transistor group23, and the third transistor group33included in the above example, the adjustment unit1132may further include a fourth transistor group43and a fifth transistor group53connected in parallel between the sixth node net6and the first node n_stg1. The first transistor group13includes the first MOS transistor M01, and the gate of the first MOS transistor M01receives the first control signal DfeTrim<2>. The second transistor group23includes the second MOS transistor M02, and the gate of the second MOS transistor M02receives the second control signal DfeTrim<1>. The third transistor group33includes the third MOS transistor M03and the fourth MOS transistor M04connected in series, the fourth MOS transistor M04is provided with a first terminal connected to the sixth node net6and a second terminal connected to a first terminal of the third MOS transistor M03, a second terminal of the third MOS transistor M03is connected to the first node n_stg1, and a gate of the third MOS transistor M03and a gate of the fourth MOS transistor M04both receive the third control signal DfeTrim<0>. The fourth transistor group43includes a fifth MOS transistor M05, and a gate of the fifth MOS transistor M05receives a fourth control signal DfePerPin<1>. The fifth transistor group53includes a sixth MOS transistor M06and a seventh MOS transistor M07connected in series, the seventh MOS transistor M07is provided with a first terminal connected to the sixth node net6and a second terminal connected to a first terminal of the sixth MOS transistor M06, a second terminal of the sixth MOS transistor M06is connected to the first node n_stg1, and a gate of the sixth MOS transistor M06and a gate of the seventh MOS transistor M07both receive a fifth control signal DfePerPin<0>.

It should be noted that, in the above three examples, the first control signal DfeTrim<2>, the second control signal DfeTrim<1>, and the third control signal DfeTrim<0> may be common to all data receiving circuits. That is, for different data receiving circuits connected to different DQ ports, the first control signal DfeTrim<2>, the second control signal DfeTrim<1>, and the third control signal DfeTrim<0> provided to the different data receiving circuits are the same. In addition, in the example shown inFIG.7, the fourth control signal DfePerPin<1> and the fifth control signal DfePerPin<0> are individually designed according to each DQ port. It can be understood that, for different data receiving circuits of each DQ port, for example, a first data receiving circuit is connected to a port DQ1, and a second data receiving circuit is connected to a port DQ2, the fourth control signal DfePerPin<1> and the fifth control signal DfePerPin<0> in the first data receiving circuit are designed based on the port DQ1, and the fourth control signal DfePerPin<1> and the fifth control signal DfePerPin<0> in the second data receiving circuit are designed based on the port DQ2. Since the data received by different DQ ports suffers from different intersymbol interference, and the interference received by each data signal DQ in the transmission path is also different, different fourth control signals DfePerPin<1> and fifth control signals DfePerPin<0> are separately designed for the data signal DQ received by each DQ port, which is conducive to the targeted adjustment of each DQ port by the adjustment unit1132, thereby further improving the receiving performance of the data receiving circuit. The DQ port is a port used by the data receiving circuit to receive the data signal DQ.

In the above embodiments, referring toFIG.6andFIG.7, the different transistor groups may include: a first transistor group13, a second transistor group23, and a third transistor group33connected in parallel, where an equivalent channel aspect ratio of the first transistor group13is twice an equivalent channel aspect ratio of the second transistor group23, and the equivalent channel aspect ratio of the second transistor group23is twice an equivalent channel aspect ratio of the third transistor group33. In this way, the ratio of the equivalent resistance of the first transistor group13, the equivalent resistance of the second transistor group23, and the equivalent resistance of the third transistor group33is 1:2:4, such that the total equivalent resistance of the adjustment unit1132may be linearly adjustment, thereby linearly adjusting the voltage at the first node n_stg1and the voltage at the second node p_stg1.

It should be noted that, the above description is only exemplified with the ratio of the equivalent channel aspect ratio of the first transistor group13to the equivalent channel aspect ratio of the second transistor group23being 2, and the ratio of the equivalent channel aspect ratio of the second transistor group23to the equivalent channel aspect ratio of the third transistor group33being 2. In practical applications, the ratio of the equivalent channel aspect ratio of the first transistor group13to the equivalent channel aspect ratio of the second transistor group23, or the ratio of the equivalent channel aspect ratio of the second transistor group23to the equivalent channel aspect ratio of the third transistor group33may also be other number, such as 3 or 4.

It should be noted that, inFIG.6, by controlling the channel aspect ratio of the first MOS transistor M01to be twice the channel aspect ratio of the second MOS transistor M02, the equivalent channel aspect ratio of the first transistor group13is twice the equivalent channel aspect ratio of the second transistor group23; and by controlling the channel aspect ratio of the second MOS transistor M02to be twice the channel aspect ratio of the third MOS transistor M03, the equivalent channel aspect ratio of the second transistor group23is twice the equivalent channel aspect ratio of the third transistor group33. InFIG.7, by controlling the channel aspect ratio of the first MOS transistor M01to be twice the channel aspect ratio of the second MOS transistor M02, the equivalent channel aspect ratio of the first transistor group13is twice the equivalent channel aspect ratio of the second transistor group23; and by controlling the channel aspect ratio of the second MOS transistor M02, the channel aspect ratio of the third MOS transistor M03, and the channel aspect ratio of the fourth MOS transistor M04to be the same, the channel aspect ratio of the second MOS transistor M02is twice the equivalent channel aspect ratio of the third transistor group33, that is, the equivalent channel aspect ratio of the second transistor group23is twice the equivalent channel aspect ratio of the third transistor group33.

In addition, inFIG.7, by controlling the channel aspect ratio of the fifth MOS transistor M05, the channel aspect ratio of the sixth MOS transistor M06, and the channel aspect ratio of the seventh MOS transistor M07to be the same, the channel aspect ratio of the fifth MOS transistor M05is twice the equivalent channel aspect ratio of the fifth transistor group53, that is, the equivalent channel aspect ratio of the fourth transistor group43is twice the equivalent channel aspect ratio of the fifth transistor group53. In some embodiments, the channel aspect ratio of the fifth MOS transistor M05may also be equal to the channel aspect ratio of the second MOS transistor M02.

In one example, referring toFIG.5, the channel length of the first MOS transistor M01, the channel length of the second MOS transistor M02, and the channel length of the third MOS transistor M03may be equal; and the channel width of the first MOS transistor M01may be twice the channel width of the second MOS transistor M02, and the channel width of the second MOS transistor M02may be twice the channel width of the third MOS transistor M03. It should be noted that, in practical applications, when the width of the first MOS transistor M01, the width of the second MOS transistor M02, and the width of the third MOS transistor M03are kept equal, by adjusting the ratio relationship of the channel length of the first MOS transistor M01, the channel length of the second MOS transistor M02, and the channel length of the third MOS transistor M03, or by adjusting the ratio relationship of the channel width of the first MOS transistor M01, the channel width of the second MOS transistor M02, and the channel width of the third MOS transistor M03, and adjusting the ratio relationship of the channel length of the first MOS transistor M01, the channel length of the second MOS transistor M02, and the channel length of the third MOS transistor M03, the ratio relationship of the equivalent channel aspect ratio of the first transistor group13, the equivalent channel aspect ratio of the second transistor group23, and the equivalent channel aspect ratio of the third transistor group33is implemented.

It should be noted that, the first MOS transistor M01, the second MOS transistor M02, the third MOS transistor M03, the fourth MOS transistor M04, the fifth MOS transistor M05, the sixth MOS transistor M06, and the seventh MOS transistor M07may all be PMOS transistors or NMOS transistors. When any one of the first MOS transistor M01, the second MOS transistor M02, the third MOS transistor M03, the fourth MOS transistor M04, the fifth MOS transistor M05, the sixth MOS transistor M06, and the seventh MOS transistor M07is a PMOS transistor, the phase of the control signal when the PMOS transistor is controlled to be in a turn-on state is a first phase. When the MOS transistor is an NMOS transistor, the phase of the control signal when the NMOS transistor is controlled to be in a turn-on state is a second phase. The first phase is opposite to the second phase.

In some other embodiments, referring toFIG.9, the first internal node n_stg2serves as the first feedback node, the second internal node p_stg2serves as the second feedback node, and the feedback signal includes a first feedback signal fbn and a second feedback signal fbp. The decision feedback equalization module103may include: a first decision feedback unit113connected to the first internal node n_stg2and the ground terminal, and configured to perform the decision feedback equalization on the first internal node n_stg2on the basis of the first feedback signal fbn; and a second decision feedback unit123connected to the second internal node p_stg2and the ground terminal, and configured to perform the decision feedback equalization on the second internal node p_stg2on the basis of the second feedback signal fbp.

The first decision feedback unit113is configured to adjust the current in the third NMOS transistor MN3to adjust the voltage at the first internal node n_stg2. The second decision feedback unit123is configured to adjust the current in the fourth NMOS transistor MN4to adjust the voltage at the second internal node p_stg2.

It should be noted that, when the decision feedback equalization module103is connected to the first internal node n_stg2and the second internal node p_stg2in the second amplification module102, the specific structure of the first decision feedback unit113and the specific structure of the second decision feedback unit123are similar to those shown inFIG.6andFIG.7, except that the types of MOS transistors in the switch unit1131are different. For example, when the decision feedback equalization module103is connected to the first node n_stg1and the second node p_stg1in the first amplification module101, the MOS transistors in the switch unit1131are PMOS transistors. When the decision feedback equalization module103is connected to the first internal node n_stg2and the second internal node p_stg2in the second amplification module102, the MOS transistors in the switch unit1131are NMOS transistors. The places that are the same as or corresponding to the foregoing descriptions are not repeated herein. The difference between when the decision feedback equalization module103is connected to the second amplification module102and when the decision feedback equalization module103is connected to the first amplification module101is described in detail below.

Referring toFIG.9, any one of the first decision feedback unit113and the second decision feedback unit123includes: a switch unit1131configured to turn on the first internal node n_stg2and the sixth node net6, or the second internal node p_stg2and the sixth node net6in response to the feedback signal; and an adjustment unit1132connected between the sixth node net6and the ground terminal, and configured to adjust an equivalent resistance between the sixth node net6and the ground terminal in response to the control signal. In the first decision feedback unit113, the feedback signal is the first feedback signal fbn, and the switch unit1131turns on the first internal node n_stg2and the sixth node net6in response to the first feedback signal fbn; and in the second decision feedback unit123, the feedback signal is the second feedback signal fbp, and the switch unit1131turns on the second internal node p_stg2and the sixth node net6in response to the second feedback signal fbp.

Still referring toFIG.9, the switch unit1131may include: an eleventh NMOS transistor MN11connected between the first internal node n_stg2and the sixth node net6and provided with a gate for receiving the first feedback signal fbn, or connected between the second internal node p_stg2and the sixth node net6and provided with a gate for receiving the second feedback signal fbp. It can be understood that, the eleventh NMOS transistor MN11is equivalent to the fifth PMOS transistor MP5inFIG.6andFIG.7.

In one example, the first feedback signal fbn received by the switch unit1131in the first decision feedback unit113is at a low level, the eleventh NMOS transistor MN11is turned on, and at this time, the adjustment unit1132adjusts the voltage at the first internal node n_stg2on the basis of the control signal. The second feedback signal fbp received by the switch unit1131in the second decision feedback unit123is at a low level, the eleventh NMOS transistor MN11is turned on, and at this time, the adjustment unit1132adjusts the voltage at the second internal node p_stg2on the basis of the control signal.

It should be noted that, inFIG.9, an example where the MOS transistors included in the adjustment unit1132are NMOS transistors is given. In practical applications, the specific structure of the adjustment unit1132is similar to that in the foregoing embodiments, and details are not repeated herein.

In some embodiments, referring toFIG.4toFIG.9, the second amplification module102may include: an input unit112connected to the first node n_stg1and the second node p_stg1, and configured to compare the first voltage signal and the second voltage signal, provide a third voltage signal to a seventh node n_stg2, and provide a fourth voltage signal to an eighth node p_stg2, where, the second amplification module102is provided with a first internal node n_stg2and a second internal node p_stg2, the seventh node n_stg2serves as the first internal node n_stg2, and the eighth node p_stg2serves as the second internal node p_stg2; and a latch unit122configured to amplify and latch the third voltage signal and the fourth voltage signal, output the first output signal Vout to the third node net3, and output the second output signal VoutN to the fourth node net4.

The input unit112is configured to compare the first voltage signal and the second voltage signal to output the third voltage signal and the fourth voltage signal. The latch unit122is configured to output, according to the third voltage signal and the fourth voltage signal, a high-level signal to the third node net3and a low-level signal to the fourth node net4, or output a low-level signal to the third node net3and a high-level signal to the fourth node net4.

In some embodiments, referring toFIG.5,FIG.8, andFIG.9, the input unit112may include: a third NMOS transistor MN3connected between the seventh node n_stg2and the ground terminal and provided with a gate for receiving the first voltage signal; and a fourth NMOS transistor MN4connected between the eighth node p_stg2and the ground terminal and provided with a gate for receiving the second voltage signal.

In one example, when the level of the first voltage signal outputted by the first node n_stg1is higher than the level of the second voltage signal outputted by the second node p_stg1, the turn-on degree of the third NMOS transistor MN3is greater than the turn-on degree of the fourth NMOS transistor MN4, such that when the voltage at the seventh node n_stg2is less than the voltage at the eighth node p_stg2, the turn-on degree of the fifth NMOS transistor MN5is greater than the turn-on degree of the sixth NMOS transistor MN6, and when the voltage at the third node net3is less than the voltage at the fourth node net4, the turn-on degree of the seventh PMOS transistor MP7is greater than the turn-on degree of the sixth PMOS transistor MP6. The latch unit122forms positive feedback amplification, further making the first output signal Vout outputted by the third node net3at a low level, and making the second output signal VoutN outputted by the fourth node net4at a high level.

In some embodiments, still referring toFIG.5,FIG.8, andFIG.9, the latch unit122may include: a fifth NMOS transistor MN5connected between the seventh node n_stg2and the third node net3and provided with a gate for receiving the second output signal VoutN; a sixth NMOS transistor MN6connected between the eighth node p_stg2and the fourth node net4and provided with a gate for receiving the first output signal Vout; a sixth PMOS transistor MP6connected between the power supply node Vcc and the third node net3and provided with a gate for receiving the second output signal VoutN; and a seventh PMOS transistor MP7connected between the power supply node Vcc and the fourth node net4and provided with a gate for receiving the first output signal Vout.

In some embodiments, referring toFIG.4, the second amplification module102may further include: a second reset unit142connected to the latch unit122and configured to reset the latch unit122. Thus, after the data receiving circuit completes reception of the data signal DQ and the reference signal Vref and the output of the first output signal Vout and the second output signal VoutN once, the second reset unit142may reset the level at the third node net3and the level at the fourth node net4to an original value, such that the data receiving circuit subsequently performs next data reception and processing.

In some embodiments, still referring toFIG.5,FIG.8, andFIG.9, the second reset unit142may include: an eighth PMOS transistor MP8connected between the power supply node Vcc and the third node net3; and a ninth PMOS transistor MP9connected between the power supply node Vcc and the fourth node net4, a gate of the eighth PMOS transistor MP8and a gate of the ninth PMOS transistor MP9both responding to an inverted signal CLK2of the sampling clock signal CLK1.

In one example, when the sampling clock signal CLK1and the enable signal SampEnN are at a low level, the first PMOS transistor MP1and the second PMOS transistor MP2are both turned on, and at this time, the first NMOS transistor MN1and the second NMOS transistor MN2are both turned off. When the inverted signal CLK2of the sampling clock signal CLK1is at a high level, the eighth PMOS transistor MP8and the ninth PMOS transistor MP9are both turned off, to ensure normal operation of the data receiving circuit. When the sampling clock signal CLK1is at a high level, the first PMOS transistor MP1is turned off, and this time, the first NMOS transistor MN1and the second NMOS transistor MN2are both turned on. When the inverted signal CLK2of the sampling clock signal CLK1is at a low level, the eighth PMOS transistor MP8and the ninth PMOS transistor MP9are both turned on, to pull up the voltage at the third node net3and the voltage at the fourth node net4to reset the third node net3and the fourth node net4.

In some embodiments, referring toFIG.8, on the basis that the second reset unit142includes the eighth PMOS transistor MP8and the ninth PMOS transistor MP9, the second reset unit142may further include: a tenth PMOS transistor MP10connected between the power supply node Vcc and the seventh node n_stg2; and an eleventh PMOS transistor MP11connected between the power supply node Vcc and the eighth node p_stg2, a gate of the tenth PMOS transistor MP10and a gate of the eleventh PMOS transistor MP11both responding to the inverted signal CLK2of the sampling clock signal CLK1. In this way, when the data receiving circuit does not need to receive the data signal DQ and the reference signal Vref, it is beneficial to further ensure that the voltage at the third node net3and the voltage at the fourth node net4are pulled up, to reset the third node net3and the fourth node net4.

The specific connection relationship between the offset compensation module104and the second amplification module102is described in detail below.

In some embodiments, referring toFIG.5, the first node n_stg1serves as the first feedback node, and the second node p_stg1serves as the second feedback node; and the data receiving circuit may further include: an offset compensation module104connected to the seventh node n_stg2and the eighth node p_stg2and configured to compensate for an offset voltage of the input unit112.

In some embodiments, referring toFIG.5, the offset compensation module104may include: a first offset compensation unit114connected between the seventh node n_stg2and the ground terminal; and a second offset compensation unit124connected between the eighth node p_stg2and the ground terminal. The first offset compensation unit114is configured to compensate for parameters of the third NMOS transistor MN3. The second offset compensation unit124is configured to compensate for parameters of the fourth NMOS transistor MN4. The first offset compensation unit114and the second offset compensation unit124may adjust the offset voltage of the data receiving circuit by compensating for the parameters of the third NMOS transistor MN3and the parameters of the fourth NMOS transistor MN4.

In some embodiments, referring toFIG.5, the first offset compensation unit114may include at least two transistor groups connected in parallel, where each of the transistor groups includes: a seventh NMOS transistor MN7provided with a first terminal connected to the seventh node n_stg2and a gate connected to the first node n_stg1; and a seventh MOS transistor M7arranged in one-to-one correspondence with the seventh NMOS transistor MN7, connected between a second terminal of the seventh NMOS transistor MN7and the ground terminal, and provided with a gate for receiving a first offset adjustment signal Offset_1. It should be noted that, for the simplicity of illustration,FIG.5only illustrates one transistor group in the first offset compensation unit114.

In this way, the turn-on degree of the seventh NMOS transistor MN7may be controlled by the first offset adjustment signal Offset_1to adjust the overall equivalent resistance of the first offset compensation unit114to further adjust the voltage at the seventh node n_stg2.

In some embodiments, the first offset compensation unit114includes two transistor groups connected in parallel, where one transistor group includes a seventh-first NMOS transistor (not shown in the figure) and a seventh-first MOS transistor (not shown in the figure), and the other transistor group includes a seventh-second NMOS transistor (not shown in the figure) and a seventh-second MOS transistor (not shown in the figure). The first offset adjustment signal Offset_1includes a third offset adjustment signal (not shown in the figure) and a fourth offset adjustment signal (not shown in the figure). A gate of the seventh-first NMOS transistor and a gate of the seventh-second NMOS transistor are connected to the first node n_stg1, a gate of the seventh-first MOS transistor receives the third offset adjustment signal, and a gate of the seventh-second MOS transistor receives the fourth offset adjustment signal.

The third offset adjustment signal and the fourth offset adjustment signal may be different. In this way, the turn-on degree of the seventh-first NMOS transistor and/or the turn-on degree of the seventh-second MOS transistor may be controlled on the basis of the third offset adjustment signal and the fourth offset adjustment signal to flexibly adjust the overall equivalent resistance of the first offset compensation unit114, to further improve the adjustment effect on the voltage at the seventh node n_stg2.

In some embodiments, referring toFIG.5, the second offset compensation unit124may include at least two transistor groups connected in parallel, where each of the transistor groups includes: an eighth NMOS transistor MN8provided with a first terminal connected to the eighth node p_stg2and a gate connected to the second node p_stg1; and an eighth MOS transistor M8arranged in one-to-one correspondence with the eighth NMOS transistor MN8, connected between a second terminal of the eighth NMOS transistor MN8and the ground terminal, and provided with a gate for receiving a second offset adjustment signal Offset_2. It should be noted that, for the simplicity of illustration,FIG.5only illustrates one transistor group in the second offset compensation unit124.

In this way, the turn-on degree of the eighth NMOS transistor MN8may be controlled by the second offset adjustment signal Offset_2to adjust the overall equivalent resistance of the second offset compensation unit124to further adjust the voltage at the eighth node p_stg2.

In some embodiments, the second offset compensation unit124includes two transistor groups connected in parallel, where one transistor group includes an eighth-first NMOS transistor (not shown in the figure) and an eighth-first MOS transistor (not shown in the figure), and the other transistor group includes an eighth-second NMOS transistor (not shown in the figure) and an eighth-second MOS transistor (not shown in the figure). The second offset adjustment signal Offset_2includes a fifth offset adjustment signal (not shown in the figure) and a sixth offset adjustment signal (not shown in the figure). A gate of the eighth-first NMOS transistor and a gate of the eighth-second NMOS transistor are connected to the first node n_stg1, a gate of the eighth-first MOS transistor receives the fifth offset adjustment signal, and a gate of the eighth-second MOS transistor receives the sixth offset adjustment signal.

The fifth offset adjustment signal and the sixth offset adjustment signal may be different. In this way, the turn-on degree of the eighth-first NMOS transistor and/or the turn-on degree of the eighth-second MOS transistor may be controlled on the basis of the fifth offset adjustment signal and the sixth offset adjustment signal to flexibly adjust the overall equivalent resistance of the second offset compensation unit124, to further improve the adjustment effect on the voltage at the eighth node p_stg2.

It should be noted that, the seventh MOS transistor M7, the seventh-first MOS transistor, the seventh-second MOS transistor, the eighth MOS transistor M8, the eighth-first MOS transistor, and the eighth-second MOS transistor may all be PMOS transistors or NMOS transistors. When any of the MOS transistors is a PMOS transistor, and the PMOS transistor is turned on, the phase of the first offset adjustment signal Offset_1is a third phase; and when the MOS transistors is an NMOS transistor, and the NMOS transistor is turned on, the phase of the second offset adjustment signal Offset_2is a fourth phase. The third phase is opposite to the fourth phase.

The specific connection relationship between the offset compensation module104and the first amplification module101is described in detail below.

In some embodiments, the seventh node n_stg2serves as the first feedback node, and the eighth node p_stg2serves as the second feedback node. The data receiving circuit may further include: an offset compensation module104connected to the first node n_stg1and the second node p_stg1and configured to compensate for an offset voltage of the comparison unit121.

The offset compensation module104may include: a first offset compensation unit114connected between the fifth node net5and the first node n_stg1; and a second offset compensation unit124connected between the fifth node net5and the second node p_stg1. The first offset compensation unit114is configured to compensate for parameters of the third PMOS transistor MP3. The second offset compensation unit124is configured to compensate for parameters of the fourth PMOS transistor MP4. The first offset compensation unit114and the second offset compensation unit124may adjust the offset voltage of the data receiving circuit by compensating for the parameters of the third PMOS transistor MP3and the parameters of the fourth PMOS transistor MP4.

In some embodiments, referring toFIG.8, the data receiving circuit may further include: a thirteen MOS transistor M1provided with a gate for receiving the sampling clock signal CLK1, a drain connected to the fifth node net5, and a source connected to the ground terminal.

In conclusion, the decision feedback equalization module103is integrated in the data receiving circuit, which is beneficial to adjust the signals outputted by the data receiving circuit using a smaller circuit layout area and lower power consumption. Moreover, the adjustment capability of the decision feedback equalization module103provided in the embodiments of the present disclosure to the first output signal Vout and the second output signal VoutN is adjustable. It can be understood that, when the data signal DQ and/or the reference signal Vref received by the receiving module100change, the adjustment capability of the decision feedback equalization module103to the first output signal Vout and the second output signal VoutN may be flexibly controlled, to reduce the intersymbol interference in the data receiving circuit, thereby improving the receiving performance of the data receiving circuit.

Another embodiment of the present disclosure provides a data receiving system. The data receiving system provided by another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.FIG.1is a functional block diagram of a data receiving system according to another embodiment of the present disclosure.

Referring toFIG.2, the data receiving system includes: a plurality of cascaded data transmission circuits130, where each of the data transmission circuits130includes the data receiving circuit110according to one embodiment of the present disclosure and a latch circuit120connected to the data receiving circuit110, and the data receiving circuit110is connected to a data port for receiving the data signal DQ; a previous-stage data transmission circuit130is connected to the decision feedback equalization module DFE of a next-stage data transmission circuit130, and output of the previous-stage data transmission circuit130serves as the feedback signal of the decision feedback equalization module DFE of the next-stage data transmission circuit130; and a last-stage data transmission circuit130is connected to the decision feedback equalization module DFE of a first-stage data transmission circuit130, and output of the last-stage data transmission circuit130serves as the feedback signal of the decision feedback equalization module DFE of the first-stage data transmission circuit130.

The latch circuits120and the data receiving circuits110are arranged in one-to-one correspondence, and the latch circuits120are configured to latch and output signals outputted by the data receiving circuits110corresponding to the latch circuits120.

It should be noted that, the output of any data transmission circuit130may include the following two situations: in some embodiments, the output of the data transmission circuit130refers to the output of the data receiving circuit110. It can be understood that, the output of the previous-stage data receiving circuit110serves as the feedback signal of the decision feedback equalization module DFE of the next-stage data receiving system, and the output of the last-stage data receiving circuit110serves as the feedback signal of the decision feedback equalization module DFE of the first-stage data receiving system. In this way, the output of the data receiving circuit110is directly transmitted to the decision feedback equalization module DFE, without passing through the latch circuit120, which is beneficial to reduce the transmission delay of data. In some other embodiments, the output of the data transmission circuit130refers to the output of the latch circuit120. It can be understood that, the output of the previous-stage data receiving circuit110is latched by the latch circuit120corresponding to this-stage data receiving circuit110, and then is connected to the decision feedback equalization module DFE of the next-stage data receiving system through the output terminal of the latch circuit120. That is, the output of the previous-stage latch circuit120serves as the feedback signal of the decision feedback equalization module DFE of the next-stage data receiving system, and the output of the last-stage latch circuit120serves as the feedback signal of the decision feedback equalization module DFE of the first-stage data receiving system.

It should be noted that, inFIG.1, taking an example where the data receiving system includes four cascaded data receiving circuits110, and the sampling clock signals of adjacent stages of the data receiving circuits110have a phase difference of 90 degrees, in practical applications, the number of the cascaded data receiving circuits110included in the data receiving system is not limited, and the phase difference of the sampling clock signals of adjacent stages of data receiving circuits110may be reasonably set on the basis of the number of the cascaded data receiving circuits110.

In some embodiments, the sampling clock signals of two adjacent stages of the data receiving circuits110have a phase difference of 90 degrees, and the cycle of the sampling clock signal is twice the cycle of the data signal DQ received by the data port, thus facilitating clock routing and saving power consumption.

In conclusion, in the data receiving system according to another embodiment of the present disclosure, the adjustment capability to the first output signal Vout and the second output signal VoutN may be flexibly controlled, to reduce the influence of the intersymbol interference of the data received by the data receiving circuit110on the data receiving circuit110, improve the receiving performance of the data receiving circuit110, and reduce the influence of the intersymbol interference of the data on the accuracy of the signals outputted by the data receiving circuit110, thereby improving the receiving performance of the data receiving system.

Another embodiment of the present disclosure further provides a memory device, including: a plurality of data ports; and a plurality of the data receiving systems according to another embodiment of the present disclosure, where each of the data receiving systems corresponds to one of the data ports. Thus, each of the data ports in the memory device may flexibly adjust the received data signal DQ through the data receiving system, to improve the adjustment capability to the first output signal Vout and the second output signal VoutN, thereby improving the receiving performance of the memory device.

In some embodiments, the memory device may be a DDR memory, such as a DDR4 memory, a DDR5 memory, a DDR6 memory, a LPDDR4 memory, a LPDDR5 memory, or a LPDDR6 memory.

The embodiments or implementations of this specification are described in a progressive manner, and each embodiment focuses on differences from other embodiments. The same or similar parts between the embodiments may refer to each other.

In the description of this specification, the description with reference to terms such as “an embodiment”, “an exemplary embodiment”, “some implementations”, “a schematic implementation”, and “an example” means that the specific feature, structure, material, or characteristic described in combination with the implementation(s) or example(s) is included in at least one implementation or example of the present disclosure.

In this specification, the schematic expression of the above terms does not necessarily refer to the same implementation or example. Moreover, the described specific feature, structure, material or characteristic may be combined in an appropriate manner in any one or more implementations or examples.

It should be noted that in the description of the present disclosure, the terms such as “center”, “top”, “bottom”, “left”, “right”, “vertical”, “horizontal”, “inner” and “outer” indicate the orientation or position relationships based on the accompanying drawings. These terms are merely intended to facilitate description of the present disclosure and simplify the description, rather than to indicate or imply that the mentioned apparatus or element must have a specific orientation and must be constructed and operated in a specific orientation. Therefore, these terms should not be construed as a limitation to the present disclosure.

It can be understood that the terms such as “first” and “second” used in the present disclosure can be used to describe various structures, but these structures are not limited by these terms. Instead, these terms are merely intended to distinguish one structure from another.

The same elements in one or more accompanying drawings are denoted by similar reference numerals. For the sake of clarity, various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of brevity, a structure obtained by implementing a plurality of steps may be shown in one figure. In order to understand the present disclosure more clearly, many specific details of the present disclosure, such as the structure, material, size, processing process, and technology of the device, are described below. However, as those skilled in the art can understand, the present disclosure may not be implemented according to these specific details.

Finally, it should be noted that the above embodiments are merely intended to explain the technical solutions of the present disclosure, rather than to limit the present disclosure. Although the present disclosure is described in detail with reference to the above embodiments, those skilled in the art should understand that they may still modify the technical solutions described in the above embodiments, or make equivalent substitutions of some or all of the technical features recorded therein, without deviating the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.

INDUSTRIAL APPLICABILITY

According to the data receiving circuit, the data receiving system, and the memory device provided in the embodiments of the present disclosure, the decision feedback equalization module is integrated in the data receiving circuit, and is configured to adjust the first output signal and the second output signal to reduce the influence of the intersymbol interference on the data reception. The embodiments of the present disclosure are beneficial to adjust the signals outputted by the data receiving circuit using a smaller circuit layout area and lower power consumption, and reduce, by flexibly controlling the adjustment capability of the decision feedback equalization module to the first output signal and the second output signal, the influence of the intersymbol interference of the data received by the data receiving circuit on the data receiving circuit, thereby improving the receiving performance of the data receiving circuit, and reducing the influence of the intersymbol interference of the data on the accuracy of the signals outputted by the data receiving circuit.