Patent ID: 12199542

DETAILED DESCRIPTION

Hereinafter, example embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

FIG.1is a diagram schematically illustrating a configuration of a vehicle1according to the present example embodiment. For example, the vehicle1is an electric car that travels on four wheels including two driving wheels2and two steering wheels (not illustrated). The vehicle1in the present example embodiment includes a vehicle speed sensor3, an accelerator position sensor (APS)4, an electronic control unit (ECU)5, a motor assembly6, a high-voltage battery7, and a low-voltage battery8.

The vehicle speed sensor3detects the speed of the vehicle1and outputs a result of the detection to the electronic control device5as vehicle speed data. The accelerator position sensor4detects a depression amount of an accelerator pedal, and outputs a result of the detection to the electronic control device5as accelerator position data.

The electronic control unit5controls a driving force transmitted to the driving wheels2by the motor assembly6described later based on the vehicle speed data input from the vehicle speed sensor3and the accelerator position data input from the accelerator position sensor4. Specifically, the electronic control unit5determines, based on the vehicle speed data and the accelerator position data, a torque command value Tm* at which a driving force requested by the driver is transmitted to the driving wheel2, and outputs a motor control signal CS indicating the torque command value Tm* to the motor assembly6.

The motor assembly6drives the driving wheel2based on the motor control signal CS input from the electronic control unit5. Specifically, the motor assembly6transmits the driving force requested by the driver to the driving wheel2by controlling the torque of a motor10based on the torque command value Tm* indicated by the motor control signal CS. The motor assembly6includes the motor10, a reduction gear20, a differential gear30, and a motor control device40.

The motor10is a high-output motor used as a drive source of the vehicle1. For example, the motor10is an inner rotor type three-phase synchronous motor. The motor10includes a rotor shaft11, a U-phase terminal12u, a V-phase terminal12v, a W-phase terminal12w, a U-phase coil13u, a V-phase coil13v, and a W-phase coil13w.

Further, although not illustrated inFIG.1, the motor10includes a motor housing, and a rotor and a stator housed in the motor housing. The rotor is a rotating body rotatably supported by a bearing component inside the motor housing. The stator is fixed inside the motor housing in a state of surrounding an outer peripheral surface of the rotor, and generates an electromagnetic force necessary for rotating the rotor.

The rotor shaft11is a shaft body coaxially joined to the rotor. The U-phase terminal12u, the V-phase terminal12v, and the W-phase terminal12ware metal terminals exposed from a surface of the motor housing. The U-phase terminal12u, the V-phase terminal12v, and the W-phase terminal12ware electrically connected to the motor control device40. The U-phase coil13u, the V-phase coil13v, and the W-phase coil13ware excitation coils provided in the stator. The U-phase coil13u, the V-phase coil13v, and the W-phase coil13ware star-connected inside the motor10.

The U-phase coil13uis electrically connected between the U-phase terminal12uand a neutral point N. The V-phase coil13vis electrically connected between the V-phase terminal12vand the neutral point N. The W-phase coil13wis electrically connected between the W-phase terminal12wand the neutral point N. Three-phase current flowing through the U-phase coil13u, the V-phase coil13v, and the W-phase coil13wis controlled by the motor control device40, so that an electromagnetic force necessary for rotating the rotor is generated. When the rotor rotates, the rotor shaft11also rotates in synchronization with the rotor. A rotational force of the rotor shaft11is transmitted to the driving wheel2via a power transmission mechanism including the reduction gear20and the differential gear30.

The motor control device40controls the motor10based on the motor control signal CS input from the electronic control device5. Specifically, the motor control device40controls the three-phase current flowing through the U-phase coil13u, the V-phase coil13v, and the W-phase coil13wbased on the torque command value Tm* indicated by the motor control signal CS, so as to control the torque of the motor10to a value corresponding to the torque command value Tm*.

The motor control device40includes a high-voltage positive electrode terminal41, a high-voltage negative electrode terminal42, a low-voltage positive electrode terminal43, and a low-voltage negative electrode terminal44as power supply terminals. The high-voltage positive electrode terminal41is electrically connected to a positive electrode terminal of the high-voltage battery7. The high-voltage negative electrode terminal42is electrically connected to a negative electrode terminal of the high-voltage battery7. The low-voltage positive electrode terminal43is electrically connected to a positive electrode terminal of the low-voltage battery8. The low-voltage negative electrode terminal44is electrically connected to a negative electrode terminal of the low-voltage battery8.

The high-voltage battery7and the low-voltage battery8are, for example, secondary batteries such as a lithium ion battery or a nickel hydrogen battery. The high-voltage battery7outputs, for example, a high-DC voltage HV of 470 V. The low-voltage battery8outputs, for example, a low-DC voltage LV of 12 V. Although details will be described later, an internal circuit of the motor control device40is divided into a high-voltage system circuit and a low-voltage system circuit. The high-DC voltage HV output from the high-voltage battery7to the motor control device40is used as power supply voltage for operating the high-voltage system circuit, and the low-DC voltage LV output from the low-voltage battery8to the motor control device40is used as power supply voltage for operating the low-voltage system circuit.

The motor control device40includes a U-phase output terminal45u, a V-phase output terminal45v, and a W-phase output terminal45was output terminals. The U-phase output terminal45uis electrically connected to the U-phase terminal12uof the motor10. The V-phase output terminal45vis electrically connected to the V-phase terminal12vof the motor10. The W-phase output terminal45wis electrically connected to the W-phase terminal12wof the motor10. When the three-phase current is supplied from the motor control device40to the motor10via the U-phase output terminal45u, the V-phase output terminal45v, and the W-phase output terminal45w, the motor10rotates with the torque determined by the torque command value Tm*.

FIG.2is a diagram schematically illustrating a configuration of the internal circuit of the motor control device40. As illustrated inFIG.2, the motor control device40includes a motor drive circuit100, a first separation circuit210, a second separation circuit220, an MCU300, a power management integrated circuit (PMIC)400, an alternative circuit500, a first overvoltage detection circuit610, a second overvoltage detection circuit620, an OR circuit700, and a multiplexer800.

The motor drive circuit100is a three-phase inverter that converts DC power supplied from the high-voltage battery7into three-phase power and outputs the three-phase power to the motor10. The motor drive circuit100has an upper arm110including three upper switching elements and a lower arm120including three lower switching elements. The upper arm110includes a U-phase upper switching element QUH, a V-phase upper switching element QVH, and a W-phase upper switching element QWH. The lower arm120includes a U-phase lower switching element QUL, a V-phase lower switching element QVL, and a W-phase lower switching element QWL. In the present example embodiment, each of the switching elements is, for example, an N-channel IGBT. Further, each of the switching elements includes freewheel diodes in antiparallel.

The collector terminal of the U-phase upper switching element QUH, the collector terminal of the V-phase upper switching element QVH, and the collector terminal of the W-phase upper switching element QWHare electrically connected to the high-voltage positive electrode terminal41. The emitter terminal of the U-phase lower switching element QUL, the emitter terminal of the V-phase lower switching element QVL, and the emitter terminal of the W-phase lower switching element QWLare electrically connected to the high-voltage negative electrode terminal42. Note that, as described above, the high-voltage positive electrode terminal41is electrically connected to the positive electrode terminal of the high-voltage battery7, and the high-voltage negative electrode terminal42is electrically connected to the negative electrode terminal of the high-voltage battery7.

The emitter terminal of the U-phase upper switching element QUHis electrically connected to each of the U-phase output terminal45uand a collector terminal of the U-phase lower switching element QUL. That is, the emitter terminal of the U-phase upper switching element QUHis electrically connected to the U-phase terminal12uof the motor10via the U-phase output terminal45u.

The emitter terminal of the V-phase upper switching element QVHis electrically connected to each of the V-phase output terminal45vand a collector terminal of the V-phase lower switching element QVL. That is, the emitter terminal of the V-phase upper switching element QVHis electrically connected to the V-phase terminal12vof the motor10via the V-phase output terminal45v.

The emitter terminal of the W-phase upper switching element QWHis electrically connected to each of the W-phase output terminal45wand a collector terminal of the W-phase lower switching element QWL. That is, the emitter terminal of the W-phase upper switching element QWHis electrically connected to the W-phase terminal12wof the motor10via the W-phase output terminal45w.

The motor drive circuit100includes a U-phase upper gate driver111, a V-phase upper gate driver112, a W-phase upper gate driver113, a U-phase lower gate driver121, a V-phase lower gate driver122, and a W-phase lower gate driver123as gate drivers for driving the switching elements.

The U-phase upper gate driver111is electrically connected to the gate terminal, the collector terminal, and the emitter terminal of the U-phase upper switching element QUH. The U-phase upper gate driver111changes gate voltage of the U-phase upper switching element QUHbased on a U-phase upper gate control signal UHG output from the multiplexer800. The gate voltage is voltage between the gate terminal and the emitter terminal. Specifically, for example, when the U-phase upper gate control signal UHG is at a high level, the U-phase upper gate driver111changes the gate voltage to a value at which the U-phase upper switching element QUHis in an on state. In contrast, when the U-phase upper gate control signal UHG is at a low level, the U-phase upper gate driver111changes the gate voltage to a value at which the U-phase upper switching element QUHis in an off state.

Further, the U-phase upper gate driver111outputs a fault signal FLT1which is an abnormality detection signal to the MCU300and the alternative circuit500. The U-phase upper gate driver111outputs the fault signal FLT1at a high level when the U-phase upper switching element QUHis in a normal state. In contrast, the U-phase upper gate driver111outputs the fault signal FLT1at a low level when the U-phase upper switching element QUHis in an abnormal state. For example, when excessive collector current flows through the U-phase upper switching element QUH, the collector-emitter voltage exceeds a saturation voltage. In this case, the U-phase upper switching element QUHis determined to be in an abnormal state. For example, the U-phase upper gate driver111monitors the collector-emitter voltage of the U-phase upper switching element QUH, and outputs the fault signal FLT1at a low level when the collector-emitter voltage exceeds a saturation voltage.

Note that an event in which the U-phase upper switching element QUHis determined to be in an abnormal state is not limited to the event in which excessive collector current flows through the U-phase upper switching element QUH. For example, an event in which a temperature of the U-phase upper switching element QUHgreatly increases is also an event in which the U-phase upper switching element QUHis determined to be in an abnormal state. For this reason, for example, the U-phase upper gate driver111may monitor a temperature of the U-phase upper switching element QUHwith a thermistor or the like, and output the fault signal FLT1at a low level when the temperature exceeds a threshold. Further, the U-phase upper gate driver111may output the fault signal FLT1at a low level even in a case where the U-phase upper gate driver111does not operate due to, for example, no input of power supply voltage of the U-phase upper gate driver111.

The V-phase upper gate driver112is electrically connected to the gate terminal, the collector terminal, and the emitter terminal of the V-phase upper switching element QVHSimilarly to the U-phase upper gate driver111, the V-phase upper gate driver112changes the gate voltage of the V-phase upper switching element QVHbased on a V-phase upper gate control signal VHG output from the multiplexer800.

Further, similarly to the U-phase upper gate driver111, the V-phase upper gate driver112outputs a fault signal FLT2which is an abnormality detection signal to the MCU300and the alternative circuit500. That is, the V-phase upper gate driver112outputs the fault signal FLT2at a high level when the V-phase upper switching element QVHis in a normal state. In contrast, the V-phase upper gate driver112outputs the fault signal FLT2at a low level when the V-phase upper switching element QVHis in an abnormal state.

The W-phase upper gate driver113is electrically connected to the gate terminal, the collector terminal, and the emitter terminal of the W-phase upper switching element QWHSimilarly to the U-phase upper gate driver111, the W-phase upper gate driver113changes the gate voltage of the W-phase upper switching element QWHbased on a W-phase upper gate control signal WHG output from the multiplexer800.

Further, similarly to the U-phase upper gate driver111, the W-phase upper gate driver113outputs a fault signal FLT3which is an abnormality detection signal to the MCU300and the alternative circuit500. That is, the W-phase upper gate driver113outputs the fault signal FLT3at a high level when the W-phase upper switching element QWHis in a normal state. In contrast, the W-phase upper gate driver113outputs the fault signal FLT3at a low level when the W-phase upper switching element QWHis in an abnormal state.

The U-phase lower gate driver121is electrically connected to the gate terminal, the collector terminal, and the emitter terminal of the U-phase lower switching element QUL. Similarly to the U-phase upper gate driver111, the U-phase lower gate driver121changes the gate voltage of the U-phase lower switching element QULbased on a U-phase lower gate control signal ULG output from the multiplexer800.

Further, similarly to the U-phase upper gate driver111, the U-phase lower gate driver121outputs a fault signal FLT4which is an abnormality detection signal to the MCU300and the alternative circuit500. That is, the U-phase lower gate driver121outputs the fault signal FLT4at a high level when the U-phase lower switching element QULis in a normal state. In contrast, the U-phase lower gate driver121outputs the fault signal FLT4at a low level when the U-phase lower switching element QULis in an abnormal state.

The V-phase lower gate driver122is electrically connected to the gate terminal, the collector terminal, and the emitter terminal of the V-phase lower switching element QVL. Similarly to the U-phase upper gate driver111, the V-phase lower gate driver122changes the gate voltage of the V-phase lower switching element QVLbased on a V-phase lower gate control signal VLG output from the multiplexer800.

Further, similarly to the U-phase upper gate driver111, the V-phase lower gate driver122outputs a fault signal FLT5which is an abnormality detection signal to the MCU300and the alternative circuit500. That is, the V-phase lower gate driver122outputs the fault signal FLT5at a high level when the V-phase lower switching element QVLis in a normal state. In contrast, the V-phase lower gate driver122outputs the fault signal FLT5at a low level when the V-phase lower switching element QVLis in an abnormal state.

The W-phase lower gate driver123is electrically connected to the gate terminal, the collector terminal, and the emitter terminal of the W-phase lower switching element QWL. Similarly to the U-phase upper gate driver111, the W-phase lower gate driver123changes the gate voltage of the W-phase lower switching element QWLbased on a W-phase lower gate control signal WLG output from the multiplexer800.

Further, similarly to the U-phase upper gate driver111, the W-phase lower gate driver123outputs a fault signal FLT6which is an abnormality detection signal to the MCU300and the alternative circuit500. That is, the W-phase lower gate driver123outputs the fault signal FLT6at a high level when the W-phase lower switching element QWLis in a normal state. In contrast, the W-phase lower gate driver123outputs the fault signal FLT6at a low level when the W-phase lower switching element QWLis in an abnormal state.

The first separation circuit210and the second separation circuit220are circuits that separate the internal circuit of the motor control device40into the high-voltage system circuit and the low-voltage system circuit. The high-voltage system circuit includes the motor drive circuit100described above. The low-voltage system circuit includes the MCU300, the PMIC400, the alternative circuit500, the first overvoltage detection circuit610, the second overvoltage detection circuit620, the OR circuit700, and the multiplexer800.

An input terminal of the first separation circuit210is electrically connected to the high-voltage positive electrode terminal41. An output terminal of the first separation circuit210is electrically connected to an input terminal of the first overvoltage detection circuit610and an overvoltage detection port310of the MCU300. The first separation circuit210electrically separates the high-voltage system circuit and the low-voltage system circuit from each other, and converts the high-DC voltage HV input from the high-voltage battery7into a low voltage that can be input to the first overvoltage detection circuit610to output the voltage.

An input terminal of the second separation circuit220is electrically connected to the high-voltage positive electrode terminal41. An output terminal of the second separation circuit220is electrically connected to an input terminal of the second overvoltage detection circuit620. The second separation circuit220electrically separates the high-voltage system circuit and the low-voltage system circuit from each other, and converts the high-DC voltage HV input from the high-voltage battery7into a low voltage that can be input to the second overvoltage detection circuit620to output the voltage. The first separation circuit210and the second separation circuit220include a circuit including, for example, an isolator and a resistance voltage dividing circuit.

An output voltage of the first separation circuit210is equal to an output voltage of the second separation circuit220. The output voltages of the first separation circuit210and the second separation circuit220are proportional to the high-DC voltage HV input from the high voltage battery7, that is, an input voltage of the motor drive circuit100. In other words, the output voltages of the first separation circuit210and the second separation circuit220represent the input voltage of the motor drive circuit100. For this reason, hereinafter, the output voltages of the first separation circuit210and the second separation circuit220are referred to as an inverter input voltage VINV.

The MCU300is an arithmetic processing device that controls the motor drive circuit100. The MCU300is, for example, a dual-core type MCU equipped with two processor cores. In addition to the two processor cores, the MCU300includes a physical non-transitory memory such as a flash memory that stores a program and the like executed by the processor core, a volatile memory such as a random access memory (RAM), an input/output port, a communication port, an internal bus that interconnects these, and the like.

The MCU300includes, as a communication port, a controller area network (CAN) communication port for performing CAN communication with the electronic control unit5, and a serial peripheral interface (SPI) communication port for performing SPI communication with the PMIC400. The CAN communication port of the MCU300is electrically connected to the electronic control unit5via a CAN communication cable (not illustrated). The motor control signal CS output from the electronic control unit5is input to the MCU300via the CAN communication cable and the CAN communication port. The SPI communication port of the MCU300is electrically connected to the PMIC400via an SPI communication bus320of a four-wire type.

The MCU300performs switching control of each switching element included in the motor drive circuit100on the basis of the motor control signal CS input from the electronic control unit5. Specifically, the MCU300generates a timing signal indicating a switching timing of each switching element based on the torque command value Tm* indicated by the motor control signal CS, and outputs the timing signal from an output port to the multiplexer800. The switching timing is a timing at which the state of each switching element is switched from an off state to an on state and a timing at which the state is switched from the on state to the off state. The timing signal is, for example, a pulse-width modulated rectangular wave signal.

Specifically, the MCU300outputs a U-phase upper timing signal HPU representing a switching timing of the U-phase upper switching element QUHto the multiplexer800, and outputs a U-phase lower timing signal LPU representing a switching timing of the U-phase lower switching element QULto the multiplexer800.

Further, the MCU300outputs a V-phase upper timing signal HPV representing a switching timing of the V-phase upper switching element QVHto the multiplexer800, and outputs a V-phase lower timing signal LPV representing a switching timing of the V-phase lower switching element QVLto the multiplexer800.

Further, the MCU300outputs a W-phase upper timing signal HSW representing a switching timing of the W-phase upper switching element QWHto the multiplexer800, and outputs a W-phase lower timing signal LPW representing a switching timing of the W-phase lower switching element QWLto the multiplexer800.

The MCU300includes, as an input port, the overvoltage detection port310electrically connected to an output terminal of the first separation circuit210. Although details will be described later, the MCU300compares the inverter input voltage VINVinput from the first separation circuit210via the overvoltage detection port310with a first threshold VTH1, and executes the fail-safe control when the inverter input voltage VINVexceeds the first threshold VTH1. The fail-safe control means control in which all the switching elements included in one of the upper arm110and the lower arm120are set to be in an on state and all the switching elements included in the other are set to be in an off state (ASC control), or control in which all the switching elements included in both the upper arm110and the lower arm120are set to be in an off state (SD control). Note that the first threshold VTH1is digital data stored in advance in a physical non-transitory memory of the MCU300. Further, the inverter input voltage VINVinput via the overvoltage detection port310is converted into digital data by an AD converter incorporated in the MCU300.

The MCU300outputs a first error signal ER1and a second error signal ER2to the PMIC400as signals for notifying abnormality of the two processor cores. Specifically, when the two processor cores are in a normal state, the MCU300sets both the first error signal ER1and the second error signal ER2to a high level. In contrast, when at least one of the two processor cores is in an abnormal state, the MCU300sets at least one of the first error signal ER1and the second error signal ER2to a low level.

The PMIC400performs power management of the MCU300and functions as a monitor that monitors the state of the MCU300. The PMIC400is provided separately from the MCU300. The PMIC400is communicably connected to the MCU300via the SPI communication bus320. The PMIC400communicates with the MCU300via the SPI communication bus320in order to perform processing necessary for power management of the MCU300.

The PMIC400is electrically connected to the low-voltage battery8via the low-voltage positive electrode terminal43and the low-voltage negative electrode terminal44. The PMIC400generates power supply voltage necessary for operation of the low-voltage system circuit based on the low-DC voltage LV output from the low-voltage battery8, and supplies the generated power supply voltage to the MCU300, the alternative circuit500, the first overvoltage detection circuit610, the second overvoltage detection circuit620, the OR circuit700, the multiplexer800, and the like.

The PMIC400outputs a restart signal RST, a first abnormality detection signal FOT, and a second abnormality detection signal IOT to the OR circuit700as signals for notifying abnormality of the MCU300. Specifically, when the MCU300is in a normal state, the PMIC400sets all of the restart signal RST, the first abnormality detection signal FOT, and the second abnormality detection signal IOT to a high level.

When the MCU300is in an abnormal state, the PMIC400sets at least one of the restart signal RST, the first abnormality detection signal FOT, and the second abnormality detection signal IOT to a low level. For example, when at least one of the first error signal ER1and the second error signal ER2input from the MCU300is at a low level, the PMIC400sets the first abnormality detection signal FOT to a low level. Further, when an abnormality that requires restart of the MCU300occurs, the PMIC400sets the restart signal RST to a low level. Further, when another abnormality occurs in the MCU300, the PMIC400sets the second abnormality detection signal IOT to a low level.

The alternative circuit500is a circuit that substitutes for the MCU300. The alternative circuit500includes a first OR circuit510, a second OR circuit520, a matrix circuit530, a first switch540, and a second switch550.

The first OR circuit510receives input of the fault signal FLT1output from the U-phase upper gate driver111, the fault signal FLT2output from the V-phase upper gate driver112, and the fault signal FLT3output from the W-phase upper gate driver113. The first OR circuit510calculates the OR of the fault signals FLT1, FLT2, and FLT3, and outputs an upper arm fault signal FLTH indicating a result of the calculation to the matrix circuit530.

The first OR circuit510is an OR circuit of the negative logic. Therefore, when at least one of the fault signals FLT1, FLT2, and FLT3is at a low level, the upper arm fault signal FLTH at a low level is output from the first OR circuit510. When all of the fault signals FLT1, FLT2, and FLT3are at a high level, the upper arm fault signal FLTH at a high level is output from the first OR circuit510. In other words, when at least one of the U-phase upper switching element QUH, the V-phase upper switching element QVH, and the W-phase upper switching element QWHincluded in the upper arm110is in an abnormal state, the upper arm fault signal FLTH at a low level is output from the first OR circuit510. When all of the U-phase upper switching element QUH, the V-phase upper switching element QVH, and the W-phase upper switching element QWHincluded in the upper arm110are in a normal state, the upper arm fault signal FLTH at a high level is output from the first OR circuit510.

Hereinafter, that at least one of the U-phase upper switching element QUH, the V-phase upper switching element QVH, and the W-phase upper switching element QWHincluded in the upper arm110is in an abnormal state will be described as “the upper arm110is in an abnormal state”. Further, that all of the U-phase upper switching element QUH, the V-phase upper switching element QVH, and the W-phase upper switching element QWHincluded in the upper arm110are in a normal state will be described as “the upper arm110is in a normal state”. That is, when the upper arm110is in an abnormal state, the upper arm fault signal FLTH at a low level is output from the first OR circuit510. Further, when the upper arm110is in a normal state, the upper arm fault signal FLTH at a high level is output from the first OR circuit510.

The second OR circuit520receives input of the fault signal FLT4output from the U-phase lower gate driver121, the fault signal FLT5output from the V-phase lower gate driver122, and the fault signal FLT6output from the W-phase lower gate driver123. The second OR circuit520calculates the OR of the fault signals FLT4, FLT5, and FLT6, and outputs a lower arm fault signal FLTL indicating a result of the calculation to the matrix circuit530.

The second OR circuit520is an OR circuit of the negative logic. Therefore, when at least one of the fault signals FLT4, FLT5, and FLT6is at a low level, the lower arm fault signal FLTL at a low level is output from the second OR circuit520. When all of the fault signals FLT4, FLT5, and FLT6are at a high level, the lower arm fault signal FLTL at a high level is output from the second OR circuit520. In other words, when at least one of the U-phase lower switching element QUL, the V-phase lower switching element QVL, and the W-phase lower switching element QWLincluded in the lower arm120is in an abnormal state, the lower arm fault signal FLTL at a low level is output from the second OR circuit520. When all of the U-phase lower switching element QUL, the V-phase lower switching element QVL, and the W-phase lower switching element QWLincluded in the lower arm120are in a normal state, the lower arm fault signal FLTL at a high level is output from the second OR circuit520.

Hereinafter, that at least one of the U-phase lower switching element QUL, the V-phase lower switching element QVL, and the W-phase lower switching element QWLincluded in the lower arm120is in an abnormal state will be described as “the lower arm120is in an abnormal state”. Further, that all of the U-phase lower switching element QUL, the V-phase lower switching element QVL, and the W-phase lower switching element QWLincluded in the lower arm120are in a normal state is described as “the lower arm120is in a normal state”. That is, when the lower arm120is in an abnormal state, the lower arm fault signal FLTL at a low level is output from the second OR circuit520. Further, when the lower arm120is in a normal state, the lower arm fault signal FLTL at a high level is output from the second OR circuit520.

The matrix circuit530outputs a first output signal OUT1to the first switch540and outputs a second output signal OUT2to the second switch550based on the upper arm fault signal FLTH input from the first OR circuit510and the lower arm fault signal FLTL input from the second OR circuit520.

When both the upper arm fault signal FLTH and the lower arm fault signal FLTL are at a high level, the matrix circuit530outputs the first output signal OUT1at a low level to the first switch540and outputs the second output signal OUT2at a high level to the second switch550. In other words, when both the upper arm110and the lower arm120are in a normal state, the matrix circuit530outputs the first output signal OUT1at a low level to the first switch540and outputs the second output signal OUT2at a high level to the second switch550.

When the upper arm fault signal FLTH is at a low level and the lower arm fault signal FLTL is at a high level, the matrix circuit530outputs the first output signal OUT1at a low level to the first switch540and outputs the second output signal OUT2at a high level to the second switch550. In other words, when the upper arm110between the upper arm110and the lower arm120is in an abnormal state, the matrix circuit530outputs the first output signal OUT1at a low level to the first switch540and outputs the second output signal OUT2at a high level to the second switch550.

When the upper arm fault signal FLTH is at a high level and the lower arm fault signal FLTL is at a low level, the matrix circuit530outputs the first output signal OUT1at a high level to the first switch540and outputs the second output signal OUT2at a low level to the second switch550. In other words, when the lower arm120between the upper arm110and the lower arm120is in an abnormal state, the matrix circuit530outputs the first output signal OUT1at a high level to the first switch540and outputs the second output signal OUT2at a low level to the second switch550.

When both the upper arm fault signal FLTH and the lower arm fault signal FLTL are at a low level, the matrix circuit530outputs the first output signal OUT1at a low level to the first switch540and outputs the second output signal OUT2at a low level to the second switch550. In other words, when both the upper arm110and the lower arm120are in an abnormal state, the matrix circuit530outputs the first output signal OUT1at a low level to the first switch540and outputs the second output signal OUT2at a low level to the second switch550.

The first switch540has three contacts541,542, and543. The contact541is electrically connected to a high-level voltage line561. High-level voltage VHi is supplied from the PMIC400to the high-level voltage line561. The contact542is electrically connected to a low-level voltage line562. Low-level voltage VLo is supplied from the PMIC400to the low-level voltage line562. In other words, the low-level voltage line562is electrically connected to the low-voltage negative electrode terminal44, which is a ground terminal of the low-voltage system circuit.

The contact543is electrically connected to the multiplexer800. Hereinafter, a signal output from the contact543to the multiplexer800is referred to as an upper arm control signal HG. When the first output signal OUT1input from the matrix circuit530to the first switch540is at a low level, the contact542and the contact543are electrically connected, so that the upper arm control signal HG having the low-level voltage VLo is output from the contact543to the multiplexer800. Further, when the first output signal OUT1input from the matrix circuit530to the first switch540is at a high level, the contact541and the contact543are electrically connected, so that the upper arm control signal HG having the high-level voltage VHi is output from the contact543to the multiplexer800.

The second switch550has three contacts551,552, and553. The contact551is electrically connected to the high-level voltage line561. The contact552is electrically connected to the low-level voltage line562. The contact553is electrically connected to the multiplexer800. Hereinafter, a signal output from the contact553to the multiplexer800is referred to as a lower arm control signal LG.

When the second output signal OUT2input from the matrix circuit530to the second switch550is at a low level, the contact552and the contact553are electrically connected, so that the lower arm control signal LG having the low-level voltage VLo is output from the contact553to the multiplexer800. When the second output signal OUT2input from the matrix circuit530to the second switch550is at a high level, the contact551and the contact553are electrically connected, so that the lower arm control signal LG having the high-level voltage VHi is output from the contact553to the multiplexer800.

As described above, when both the upper arm110and the lower arm120are in a normal state, the alternative circuit500outputs the upper arm control signal HG having the low-level voltage VLo to the multiplexer800and outputs the lower arm control signal LG having the high-level voltage VHi to the multiplexer800.

Further, when the upper arm110between the upper arm110and the lower arm120is in an abnormal state, the alternative circuit500outputs the upper arm control signal HG having the low-level voltage VLo to the multiplexer800and outputs the lower arm control signal LG having the high-level voltage VHi to the multiplexer800.

Further, when the lower arm120between the upper arm110and the lower arm120is in an abnormal state, the alternative circuit500outputs the upper arm control signal HG having the high-level voltage VHi to the multiplexer800and outputs the lower arm control signal LG having the low-level voltage VLo to the multiplexer800.

Furthermore, when both the upper arm110and the lower arm120are in an abnormal state, the alternative circuit500outputs the upper arm control signal HG having the low-level voltage VLo to the multiplexer800and outputs the lower arm control signal LG having the low-level voltage VLo to the multiplexer800.

The first overvoltage detection circuit610outputs, to the OR circuit700, a first overvoltage detection signal DV1whose state changes depending on the magnitude of the inverter input voltage VINVwhich is an input voltage of the motor drive circuit100. Specifically, the first overvoltage detection circuit610compares the inverter input voltage VINVinput from the first separation circuit210with a second threshold VTH2higher than the first threshold VTH1, and changes the state of the first overvoltage detection signal DV1from a first state to a second state when the inverter input voltage VINVexceeds the second threshold VTH2. In the present example embodiment, the first state is a high level, and the second state is a low level.

The second overvoltage detection circuit620outputs, to the OR circuit700, a second overvoltage detection signal DV2whose state changes depending on the magnitude of the inverter input voltage VINVwhich is an input voltage of the motor drive circuit100. Specifically, the second overvoltage detection circuit620compares the inverter input voltage VINVinput from the second separation circuit220with a third threshold VTH3higher than the second threshold VTH2, and changes the state of the second overvoltage detection signal DV2from the first state to the second state when the inverter input voltage VINVexceeds the third threshold VTH3.

Each of the first overvoltage detection circuit610and the second overvoltage detection circuit620includes an analog comparison circuit including a comparator. That is, the second threshold VTH2and the third threshold VTH3are not digital data stored in a physical non-transitory memory like the first threshold VTH1, but are analog voltages generated by, for example, a resistance voltage dividing circuit. In the first overvoltage detection circuit610, the inverter input voltage VINVthat is an analog voltage and the second threshold VTH2that is an analog voltage are input to a comparator, and an output signal of the comparator is output to the OR circuit700as the first overvoltage detection signal DV1. Similarly, in the second overvoltage detection circuit620, the inverter input voltage VINVthat is an analog voltage and the third threshold VTH3that is an analog voltage are input to a comparator, and an output signal of the comparator is output to the OR circuit700as the second overvoltage detection signal DV2.

The first threshold VTH1, the second threshold VTH2, and the third threshold VTH3are determined in a range from 470 V, which is a rated voltage of the high-voltage battery7, to 700 V, which is a withstand voltage of the motor drive circuit100. The first threshold VTH1is a voltage value higher than 470 V and lower than the second threshold VTH2. The second threshold VTH2is a voltage value higher than the first threshold VTH1and lower than the third threshold VTH3. The third threshold VTH3is a voltage value higher than the second threshold VTH2and lower than 700 V.

The OR circuit700is an OR circuit of the negative logic. The restart signal RST, the first abnormality detection signal FOT, and the second abnormality detection signal IOT output from the PMIC400, the first overvoltage detection signal DV1output from the first overvoltage detection circuit610, and the second overvoltage detection signal DV2output from the second overvoltage detection circuit620are input to the OR circuit700. The OR circuit700calculates the OR of the restart signal RST, the first abnormality detection signal FOT, the second abnormality detection signal IOT, the first overvoltage detection signal DV1, and the second overvoltage detection signal DV2, and outputs a signal indicating a result of the calculation to the multiplexer800as a mode switching signal MS.

When at least one of the restart signal RST, the first abnormality detection signal FOT, the second abnormality detection signal IOT, the first overvoltage detection signal DV1, and the second overvoltage detection signal DV2is at a low level, the mode switching signal MS at a low level is output from the OR circuit700. Further, when all of the restart signal RST, the first abnormality detection signal FOT, the second abnormality detection signal IOT, the first overvoltage detection signal DV1, and the second overvoltage detection signal DV2are at a high level, the mode switching signal MS at a high level is output from the OR circuit700.

That is, when all of Conditions 1 to 3 described below are satisfied, the mode switching signal MS at a high level is output from the OR circuit700.

(Condition 1) The PMIC400detects that the MCU300is in a normal state.

(Condition 2) The first overvoltage detection circuit610detects that the inverter input voltage VINVis equal to or less than the second threshold VTH2.

(Condition 3) The second overvoltage detection circuit620detects that the inverter input voltage VINVis equal to or less than the third threshold VTH3.

Further, when at least one of Conditions 4 to 6 described below is satisfied, the mode switching signal MS at a low level is output from the OR circuit700.

(Condition 4) The PMIC400detects that the MCU300is in an abnormal state.

(Condition 5) The first overvoltage detection circuit610detects that the inverter input voltage VINVexceeds the second threshold VTH2.

(Condition 6) The second overvoltage detection circuit620detects that the inverter input voltage VINVexceeds the third threshold VTH3.

The mode switching signal MS output from the OR circuit700, each timing signal output from the MCU300, and the upper arm control signal HG and the lower arm control signal LG output from the alternative circuit500are input to the multiplexer800. As described above, the timing signal output from the MCU300includes the U-phase upper timing signal HPU, the U-phase lower timing signal LPU, the V-phase upper timing signal HPV, the V-phase lower timing signal LPV, the W-phase upper timing signal HPW, and the W-phase lower timing signal LPW.

When the mode switching signal MS is at a high level, the multiplexer800outputs the U-phase upper timing signal HPU to the U-phase upper gate driver111as the U-phase upper gate control signal UHG, outputs the V-phase upper timing signal HPV to the V-phase upper gate driver112as the V-phase upper gate control signal VHG, and outputs the W-phase upper timing signal HPW to the W-phase upper gate driver113as the W-phase upper gate control signal WHG.

Further, when the mode switching signal MS is at a high level, the multiplexer800outputs the U-phase lower timing signal LPU to the U-phase lower gate driver121as the U-phase lower gate control signal ULG, outputs the V-phase lower timing signal LPV to the V-phase lower gate driver122as the V-phase lower gate control signal VLG, and outputs the W-phase lower timing signal LPW to the W-phase lower gate driver123as the W-phase lower gate control signal WLG.

When the mode switching signal MS is at a low level, the multiplexer800outputs the upper arm control signal HG to the U-phase upper gate driver111as the U-phase upper gate control signal UHG, outputs the upper arm control signal HG to the V-phase upper gate driver112as the V-phase upper gate control signal VHG, and outputs the upper arm control signal HG to the W-phase upper gate driver113as the W-phase upper gate control signal WHG.

Further, when the mode switching signal MS is at a low level, the multiplexer800outputs the lower arm control signal LG to the U-phase lower gate driver121as the U-phase lower gate control signal ULG, outputs the lower arm control signal LG to the V-phase lower gate driver122as the V-phase lower gate control signal VLG, and outputs the lower arm control signal LG to the W-phase lower gate driver123as the W-phase lower gate control signal WLG.

As described above, when the mode switching signal MS is at a high level, the motor drive circuit100is controlled by each timing signal output from the MCU300. Hereinafter, the state in which the MCU300controls the motor drive circuit100as described above is referred to as a first control mode. Further, when the mode switching signal MS is at a low level, the motor drive circuit100is controlled by the upper arm control signal HG and the lower arm control signal LG output from the alternative circuit500. Hereinafter, the state in which the alternative circuit500controls the motor drive circuit100as described above is referred to as a second control mode.

That is, the multiplexer800functions as a mode switching assembly that switches the control mode between the first control mode in which the MCU300controls the motor drive circuit100and the second control mode in which the alternative circuit500controls the motor drive circuit100on the basis of the state of the MCU300, in other words, the state of the mode switching signal MS. The multiplexer800switches the control mode from the first control mode to the second control mode when the mode switching signal MS changes from a high level to a low level. Although details will be described later, in the second control mode, the alternative circuit500controls switching of the switching elements included in the upper arm110and the lower arm120on the basis of the state of the upper arm110and the lower arm120. Specifically, the alternative circuit500performs, on the basis of the state of the upper arm110and the lower arm120, either control in which all the switching elements included in one of the upper arm110and the lower arm120are set to be in an on state and all the switching elements included in the other are set to be in an off state (ASC control), or control in which all the switching elements included in both the upper arm110and the lower arm120are set to be in an off state (SD control).

Next, operation of the motor control device40configured as described above will be described.

First, the operation of the motor control device40at a normal time will be described. The normal time is when all of Conditions 1 to 3 described below are satisfied.

(Condition 1) The PMIC400detects that the MCU300is in a normal state.

(Condition 2) The first overvoltage detection circuit610detects that the inverter input voltage VINVis equal to or less than the second threshold VTH2.

(Condition 3) The second overvoltage detection circuit620detects that the inverter input voltage VINVis equal to or less than the third threshold VTH3.

When Condition 1 is satisfied, all of the restart signal RST, the first abnormality detection signal FOT, and the second abnormality detection signal IOT output from the PMIC400to the OR circuit700are at a high level. When Condition 2 is satisfied, the first overvoltage detection signal DV1output from the first overvoltage detection circuit610to the OR circuit700is at a high level. When Condition 3 is satisfied, the second overvoltage detection signal DV2output from the second overvoltage detection circuit620to the OR circuit700is at a high level. Therefore, when all of Conditions 1 to 3 are satisfied, the mode switching signal MS at a high level is output from the OR circuit700to the multiplexer800. When the mode switching signal MS is at a high level, the control mode of the motor control device40is the first control mode in which the MCU300controls the motor drive circuit100.

FIG.3is a flowchart showing motor control processing executed by the MCU300according to a program stored in a physical non-transitory memory at the normal time. Note that the MCU300repeatedly executes the motor control process illustrated inFIG.3in a predetermined control cycle.

As illustrated inFIG.3, first, the MCU300compares the inverter input voltage VINVinput from the first separation circuit210via the overvoltage detection port310with the first threshold VTH1, and determines whether or not the inverter input voltage VINVexceeds the first threshold VTH1(Step S1). Specifically, in Step S1, the MCU300determines whether or not the inverter input voltage VINVexceeds the first threshold VTH1by comparing the inverter input voltage VINVconverted into digital data by the AD converter with the first threshold VTH1read from a physical non-transitory memory. Note that, as previously described, the first threshold VTH1is higher than 470 V that is the rated voltage of the high-voltage battery7and lower than the second threshold VTH2.

When “No” in Step S1, that is, when the inverter input voltage VINVis equal to or less than the first threshold VTH1, the MCU300performs normal motor control based on the motor control signal CS input from the electronic control device5(Step S2). In the present example embodiment, as the normal motor control, the MCU300performs vector control of three-phase current supplied from the motor drive circuit100to the motor10on the basis of the torque command value Tm* indicated by the motor control signal CS input from the electronic control device5, thereby rotating the motor10with the torque determined by the torque command value Tm*. Since the vector control is generally known as a control system of the motor10which is a three-phase synchronous motor, in the present example embodiment, the vector control will be briefly described with reference toFIG.4.

FIG.4is a flowchart showing the vector control executed as the normal motor control by the MCU300in Step S2. As illustrated inFIG.4, the MCU300acquires a detection value of three-phase current including U-phase current Iu, V-phase current Iv, and W-phase current Iw from a current sensor (not illustrated) such as a shunt resistor provided in the motor drive circuit100(Step S21).

Subsequently, the MCU300calculates two-phase currents Iα and Iβ in a fixed coordinate system by performing Clarke transformation on the detection values of the U-phase current Iu, the V-phase current Iv, and the W-phase current Iw (Step S22).

Subsequently, the MCU300converts the two-phase currents Iα and Iβ in the fixed coordinate system into a d-axis current Id and a q-axis current Iq in a rotating coordinate system by Park transformation based on Equations (1) and (2) (Step S23). Note that the MCU300acquires a detection value of the rotation angle θRof the motor10from a position detection device (not illustrated) such as a resolver attached to the motor10as “θR” in Equations (1) and (2).
Id=Iα·cos θR+Iβ·sin θR(1)
Iq=−Iα·sin θR+Iβ·cos θR(2)

Subsequently, the MCU300determines a target d-axis current IdREFand a target q-axis current IqREFon the basis of the torque command value Tm* (Step S24). In the physical non-transitory memory of the MCU300, table data indicating the target d-axis current IdREFand the target q-axis current IqREFcorresponding to the torque command value Tm* is stored in advance. In Step S24, the MCU300reads the target d-axis current IdREFand the target q-axis current IqREFcorresponding to the torque command value Tm* indicated by the motor control signal CS from the table data stored in the physical non-transitory memory, so as to determine the target d-axis current IdREFand the target q-axis current IqREF.

Subsequently, the MCU300calculates a d-axis voltage Vd at which the deviation between the d-axis current Id and the target d-axis current IdREFbecomes zero by PI computation, and calculates a q-axis voltage Vq at which the deviation between the q-axis current Iq and the target q-axis current IqREFbecomes zero by PI computation (Step S25).

Subsequently, the MCU300inversely converts the d-axis voltage Vd and the q-axis voltage Vq in the rotating coordinate system into two-phase voltages Vα and Vβ in the fixed coordinate system by inverse-Park transformation based on Equations (3) and (4) (Step S26). As “θR” in Equations (3) and (4), a detection value of the rotation angle θRobtained from a position detection device (not illustrated) such as a resolver is used.
Vα=Vd·cos θR−Vq·sin θR(3)
Vβ=Vd·sin θR+Vq·cos θR(4)

Subsequently, the MCU300inversely converts the two-phase voltage values Vα and Vβ into three-phase voltages by space vector transformation (Step S27). The three-phase voltages include a U-phase voltage Vu, a V-phase voltage Vv, and a W-phase voltage Vw. Finally, the MCU300generates the U-phase upper timing signal HPU, the V-phase upper timing signal HPV, the W-phase upper timing signal HPW, the U-phase lower timing signal LPU, the V-phase lower timing signal LPV, and the W-phase lower timing signal LPW at which the three-phase voltages obtained by the space vector transformation described above are applied to the motor10, and outputs the generated signals to the multiplexer800(Step S28).

When the mode switching signal MS is at a high level, the multiplexer800outputs the U-phase upper timing signal HPU input from the MCU300to the U-phase upper gate driver111as the U-phase upper gate control signal UHG, outputs the V-phase upper timing signal HPV input from the MCU300to the V-phase upper gate driver112as the V-phase upper gate control signal VHG, and outputs the W-phase upper timing signal HPW input from the MCU300to the W-phase upper gate driver113as the W-phase upper gate control signal WHG.

Further, when the mode switching signal MS is at a high level, the multiplexer800outputs the U-phase lower timing signal LPU input from the MCU300to the U-phase lower gate driver121as the U-phase lower gate control signal ULG, outputs the V-phase lower timing signal LPV input from the MCU300to the V-phase lower gate driver122as the V-phase lower gate control signal VLG, and outputs the W-phase lower timing signal LPW input from the MCU300to the W-phase lower gate driver123as the W-phase lower gate control signal WLG.

As described above, in a case where the inverter input voltage VINVis equal to or less than the first threshold VTH1, the MCU300executes vector control as normal motor control on the basis of the motor control signal CS input from the electronic control device5, so that each switching element included in the motor drive circuit100is subjected to switching control at an appropriate timing. As a result, the U-phase current Iu, the V-phase current Iv, and the W-phase current Iw supplied from the motor drive circuit100to the motor10are appropriately controlled, so that the motor10rotates with the torque determined by the torque command value Tm*, and a driving force requested by the driver is transmitted from the motor assembly6to the driving wheel2.

Hereinafter, the description will be continued returning toFIG.3. In a case of “Yes” in Step S1ofFIG.3, that is, in a case where the inverter input voltage VINVexceeds the first threshold VTH1, there is a high possibility that abnormality has occurred in the motor drive circuit100, and a further increase in the inverter input voltage VINVleads to a failure of the switching element and the like. For this reason, the MCU300performs the fail-safe control based on the states of the upper arm110and the lower arm120(Step S3).

First, in Step S3, the MCU300determines whether the upper arm110and the lower arm120are in a normal state or an abnormal state. Specifically, when all of the fault signal FLT1input from the U-phase upper gate driver111, the fault signal FLT2input from the V-phase upper gate driver112, and the fault signal FLT3input from the W-phase upper gate driver113are at a high level, the MCU300determines that the upper arm110is in a normal state. Further, in a case where at least one of the fault signals FLT1, FLT2, and FLT3is at a low level, the MCU300determines that the upper arm110is in an abnormal state.

Further, in a case where all of the fault signal FLT4input from the U-phase lower gate driver121, the fault signal FLT5input from the V-phase lower gate driver122, and the fault signal FLT6input from the W-phase lower gate driver123are at a high level, the MCU300determines that the lower arm120is in a normal state. Further, in a case where at least one of the fault signals FLT4, FLT5, and FLT6is at a low level, the MCU300determines that the lower arm120is in an abnormal state.

Then, when determining that both the upper arm110and the lower arm120are in a normal state, the MCU300sets all of the U-phase upper timing signal HPU, the V-phase upper timing signal HPV, and the W-phase upper timing signal HSW to a low level and outputs the signals to the multiplexer800. In this manner, all of the U-phase upper gate control signal UHG, the V-phase upper gate control signal VHG, and the W-phase upper gate control signal WHG output from the multiplexer800to the motor drive circuit100are at a low level.

Further, when determining that both the upper arm110and the lower arm120are in a normal state, the MCU300sets all of the U-phase lower timing signal LPU, the V-phase lower timing signal LPV, and the W-phase lower timing signal LPW to a high level and outputs the signals to the multiplexer800. In this manner, all of the U-phase lower gate control signal ULG, the V-phase lower gate control signal VLG, and the W-phase lower gate control signal WLG output from the multiplexer800to the motor drive circuit100are at a high level.

As a result, in a case where both the upper arm110and the lower arm120are in a normal state, all the switching elements included in the upper arm110are controlled to an off state, and all the switching elements included in the lower arm120are controlled to an on state. In other words, when determining that both the upper arm110and the lower arm120are in a normal state, the MCU300executes the ASC control for controlling all the switching elements included in the upper arm110to an off state and controlling all the switching elements included in the lower arm120to an on state. In this manner, current passing through all the switching elements included in the upper arm110is cut off, and a counter electromotive force generated by the motor10flows back in a closed circuit including the lower arm120. In this manner, a further increase in the inverter input voltage VINVand further acceleration of the motor10can be prevented, and damage to the switching element and the high-voltage battery7can be prevented.

When determining that the upper arm110between the upper arm110and the lower arm120is in an abnormal state, the MCU300sets all of the U-phase upper timing signal HPU, the V-phase upper timing signal HPV, and the W-phase upper timing signal HSW to a low level and outputs the signals to the multiplexer800. In this manner, all of the U-phase upper gate control signal UHG, the V-phase upper gate control signal VHG, and the W-phase upper gate control signal WHG output from the multiplexer800to the motor drive circuit100are at a low level.

Further, when determining that the upper arm110between the upper arm110and the lower arm120is in an abnormal state, the MCU300sets all of the U-phase lower timing signal LPU, the V-phase lower timing signal LPV, and the W-phase lower timing signal LPW to a high level and outputs the signals to the multiplexer800. In this manner, all of the U-phase lower gate control signal ULG, the V-phase lower gate control signal VLG, and the W-phase lower gate control signal WLG output from the multiplexer800to the motor drive circuit100are at a high level.

As a result, in a case where the upper arm110between the upper arm110and the lower arm120is in an abnormal state, all the switching elements included in the upper arm110are controlled to an off state, and all the switching elements included in the lower arm120are controlled to an on state. In other words, when determining that the upper arm110between the upper arm110and the lower arm120is in an abnormal state, the MCU300executes the ASC control to control all the switching elements included in the upper arm110to an off state and control all the switching elements included in the lower arm120to an on state. In this manner, current passing through all the switching elements included in the upper arm110is cut off, and a counter electromotive force generated by the motor10flows back in a closed circuit including the lower arm120. In this manner, a further increase in the inverter input voltage VINVand further acceleration of the motor10can be prevented, and damage to the switching element and the high-voltage battery7can be prevented.

When determining that the lower arm120between the upper arm110and the lower arm120is in an abnormal state, the MCU300sets all of the U-phase upper timing signal HPU, the V-phase upper timing signal HPV, and the W-phase upper timing signal HSW to a high level and outputs the signals to the multiplexer800. In this manner, all of the U-phase upper gate control signal UHG, the V-phase upper gate control signal VHG, and the W-phase upper gate control signal WHG output from the multiplexer800to the motor drive circuit100are at a high level.

Further, when determining that the lower arm120between the upper arm110and the lower arm120is in an abnormal state, the MCU300sets all of the U-phase lower timing signal LPU, the V-phase lower timing signal LPV, and the W-phase lower timing signal LPW to a low level and outputs the signals to the multiplexer800. In this manner, all of the U-phase lower gate control signal ULG, the V-phase lower gate control signal VLG, and the W-phase lower gate control signal WLG output from the multiplexer800to the motor drive circuit100are at a low level.

As a result, in a case where the lower arm120between the upper arm110and the lower arm120is in an abnormal state, all the switching elements included in the upper arm110are controlled to an on state, and all the switching elements included in the lower arm120are controlled to an off state. In other words, when determining that the lower arm120between the upper arm110and the lower arm120is in an abnormal state, the MCU300executes the ASC control to control all the switching elements included in the upper arm110to an on state and control all the switching elements included in the lower arm120to an off state. In this manner, current passing through all the switching elements included in the lower arm120is cut off, and a counter electromotive force generated by the motor10flows back in a closed circuit including the upper arm110. In this manner, a further increase in the inverter input voltage VINVand further acceleration of the motor10can be prevented, and damage to the switching element and the high-voltage battery7can be prevented.

When determining that both the upper arm110and the lower arm120are in an abnormal state, the MCU300sets all of the U-phase upper timing signal HPU, the V-phase upper timing signal HPV, and the W-phase upper timing signal HSW to a low level and outputs the signals to the multiplexer800. In this manner, all of the U-phase upper gate control signal UHG, the V-phase upper gate control signal VHG, and the W-phase upper gate control signal WHG output from the multiplexer800to the motor drive circuit100are at a low level.

Further, when determining that both the upper arm110and the lower arm120are in an abnormal state, the MCU300sets all of the U-phase lower timing signal LPU, the V-phase lower timing signal LPV, and the W-phase lower timing signal LPW to a low level and outputs the signals to the multiplexer800. In this manner, all of the U-phase lower gate control signal ULG, the V-phase lower gate control signal VLG, and the W-phase lower gate control signal WLG output from the multiplexer800to the motor drive circuit100are at a low level.

As a result, in a case where both the upper arm110and the lower arm120are in an abnormal state, all the switching elements included in the upper arm110are controlled to an off state, and all the switching elements included in the lower arm120are controlled to an off state. In other words, when determining that both the upper arm110and the lower arm120are in an abnormal state, the MCU300executes the SD control for controlling all the switching elements included in the upper arm110to an off state and controlling all the switching elements included in the lower arm120to an off state. In this manner, since the counter electromotive force generated by the rotation of the motor10flows to the high-voltage battery7via the freewheel diode of each switching element, the switching element can be protected.

The operation of the motor control device40at the normal time is described above. Next, the operation of the motor control device40at the time of abnormality will be described. The time of abnormality means that at least one of Conditions 4 to 6 described below is satisfied.

(Condition 4) The PMIC400detects that the MCU300is in an abnormal state.

(Condition 5) The first overvoltage detection circuit610detects that the inverter input voltage VINVexceeds the second threshold VTH2.

(Condition 6) The second overvoltage detection circuit620detects that the inverter input voltage VINVexceeds the third threshold VTH3.

When Condition 4 is satisfied, at least one of the restart signal RST, the first abnormality detection signal FOT, and the second abnormality detection signal IOT output from the PMIC400to the OR circuit700is at a low level. When Condition 5 is satisfied, the first overvoltage detection signal DV1output from the first overvoltage detection circuit610to the OR circuit700is at a low level. When Condition 6 is satisfied, the second overvoltage detection signal DV2output from the second overvoltage detection circuit620to the OR circuit700is at a low level. Therefore, when at least one of Conditions 4 to 6 is satisfied, the mode switching signal MS at a low level is output from the OR circuit700to the multiplexer800. When the mode switching signal MS is at a low level, the control mode of the motor control device40is the second control mode in which the alternative circuit500controls the motor drive circuit100.

In the second control mode, the alternative circuit500executes the fail-safe control based on the states of the upper arm110and the lower arm120. As previously described, when both the upper arm110and the lower arm120are in a normal state, the alternative circuit500outputs the upper arm control signal HG having the low-level voltage VLo to the multiplexer800and outputs the lower arm control signal LG having the high-level voltage VHi to the multiplexer800.

When the mode switching signal MS is at a low level, the multiplexer800outputs the upper arm control signal HG to the U-phase upper gate driver111as the U-phase upper gate control signal UHG, outputs the upper arm control signal HG to the V-phase upper gate driver112as the V-phase upper gate control signal VHG, and outputs the upper arm control signal HG to the W-phase upper gate driver113as the W-phase upper gate control signal WHG.

Further, when the mode switching signal MS is at a low level, the multiplexer800outputs the lower arm control signal LG to the U-phase lower gate driver121as the U-phase lower gate control signal ULG, outputs the lower arm control signal LG to the V-phase lower gate driver122as the V-phase lower gate control signal VLG, and outputs the lower arm control signal LG to the W-phase lower gate driver123as the W-phase lower gate control signal WLG.

Therefore, when both the upper arm110and the lower arm120are in a normal state, all of the U-phase upper gate control signal UHG, the V-phase upper gate control signal VHG, and the W-phase upper gate control signal WHG output from the multiplexer800to the motor drive circuit100are at a low level, and all of the U-phase lower gate control signal ULG, the V-phase lower gate control signal VLG, and the W-phase lower gate control signal WLG output from the multiplexer800to the motor drive circuit100are at a high level.

As a result, in a case where both the upper arm110and the lower arm120are in a normal state, all the switching elements included in the upper arm110are controlled to an off state, and all the switching elements included in the lower arm120are controlled to an on state. In other words, when both the upper arm110and the lower arm120are in a normal state, the alternative circuit500executes the ASC control for controlling all the switching elements included in the upper arm110to an off state and controlling all the switching elements included in the lower arm120to an on state. In this manner, current passing through all the switching elements included in the upper arm110is cut off, and a counter electromotive force generated by the motor10flows back in a closed circuit including the lower arm120. In this manner, a further increase in the inverter input voltage VINVand further acceleration of the motor10can be prevented, and damage to the switching element and the high-voltage battery7can be prevented.

When the upper arm110between the upper arm110and the lower arm120is in an abnormal state, the alternative circuit500outputs the upper arm control signal HG having the low-level voltage VLo to the multiplexer800and outputs the lower arm control signal LG having the high-level voltage VHi to the multiplexer800. In this manner, all of the U-phase upper gate control signal UHG, the V-phase upper gate control signal VHG, and the W-phase upper gate control signal WHG output from the multiplexer800to the motor drive circuit100are at a low level, and all of the U-phase lower gate control signal ULG, the V-phase lower gate control signal VLG, and the W-phase lower gate control signal WLG output from the multiplexer800to the motor drive circuit100are at a high level.

As a result, in a case where the upper arm110between the upper arm110and the lower arm120is in an abnormal state, all the switching elements included in the upper arm110are controlled to an off state, and all the switching elements included in the lower arm120are controlled to an on state. In other words, when the upper arm110between the upper arm110and the lower arm120is in an abnormal state, the alternative circuit500executes the ASC control to control all the switching elements included in the upper arm110to an off state and control all the switching elements included in the lower arm120to an on state. In this manner, current passing through all the switching elements included in the upper arm110is cut off, and a counter electromotive force generated by the motor10flows back in a closed circuit including the lower arm120. In this manner, a further increase in the inverter input voltage VINVand further acceleration of the motor10can be prevented, and damage to the switching element and the high-voltage battery7can be prevented.

When the lower arm120between the upper arm110and the lower arm120is in an abnormal state, the alternative circuit500outputs the upper arm control signal HG having the high-level voltage VHi to the multiplexer800and outputs the lower arm control signal LG having the low-level voltage VLo to the multiplexer800. In this manner, all of the U-phase upper gate control signal UHG, the V-phase upper gate control signal VHG, and the W-phase upper gate control signal WHG output from the multiplexer800to the motor drive circuit100are at a high level, and all of the U-phase lower gate control signal ULG, the V-phase lower gate control signal VLG, and the W-phase lower gate control signal WLG output from the multiplexer800to the motor drive circuit100are at a low level.

As a result, in a case where the lower arm120between the upper arm110and the lower arm120is in an abnormal state, all the switching elements included in the upper arm110are controlled to an on state, and all the switching elements included in the lower arm120are controlled to an off state. In other words, when the lower arm120between the upper arm110and the lower arm120is in an abnormal state, the alternative circuit500executes the ASC control to control all the switching elements included in the upper arm110to an on state and control all the switching elements included in the lower arm120to an off state. In this manner, current passing through all the switching elements included in the lower arm120is cut off, and a counter electromotive force generated by the motor10flows back in a closed circuit including the upper arm110. In this manner, a further increase in the inverter input voltage VINVand further acceleration of the motor10can be prevented, and damage to the switching element and the high-voltage battery7can be prevented.

When both the upper arm110and the lower arm120are in an abnormal state, the alternative circuit500outputs the upper arm control signal HG having the low-level voltage VLo to the multiplexer800and outputs the lower arm control signal LG having the low-level voltage VLo to the multiplexer800. In this manner, all of the U-phase upper gate control signal UHG, the V-phase upper gate control signal VHG, and the W-phase upper gate control signal WHG output from the multiplexer800to the motor drive circuit100are at a low level, and all of the U-phase lower gate control signal ULG, the V-phase lower gate control signal VLG, and the W-phase lower gate control signal WLG output from the multiplexer800to the motor drive circuit100are at a low level.

As a result, in a case where both the upper arm110and the lower arm120are in an abnormal state, all the switching elements included in the upper arm110are controlled to an off state, and all the switching elements included in the lower arm120are controlled to an off state. In other words, when both the upper arm110and the lower arm120are in an abnormal state, the alternative circuit500executes the SD control for controlling all the switching elements included in the upper arm110to an off state and controlling all the switching elements included in the lower arm120to an off state. In this manner, since the counter electromotive force generated by the rotation of the motor10flows to the high-voltage battery7via the freewheel diode of each switching element, the switching element can be protected.

As described above, the motor control device40according to the present example embodiment includes the motor drive circuit100having the upper arm110and the lower arm120, the MCU300that controls the motor drive circuit100, the alternative circuit500that substitutes for the MCU300, and the multiplexer800that switches the control mode between the first control mode and the second control mode on the basis of the state of the MCU300. The multiplexer800switches the control mode from the first control mode to the second control mode when the state of the MCU300changes from a normal state to an abnormal state. In the second control mode, the alternative circuit500performs the fail-safe control based on the states of the upper arm110and the lower arm120.

According to the present example embodiment, it is possible to execute the fail-safe control by the substitute circuit500when an abnormality occurs in the MCU300. Further, it is possible to execute appropriate fail-safe control based on the states of the upper arm110and the lower arm120.

The motor control device40in the present example embodiment further includes the monitor (PMIC400) that monitors the state of the MCU300. The multiplexer800switches the control mode from the first control mode to the second control mode when the monitor detects that the state of the MCU300changes from a normal state to an abnormal state.

In a control device using an arithmetic processing device such as the MCU300, it is common to provide a monitoring circuit that monitors a state of the arithmetic processing device. Therefore, if an existing monitoring circuit is used as the monitor of the present disclosure, it is not necessary to add a new component for the monitor, and the present disclosure can be realized at low cost.

In the present example embodiment, the monitor (PMIC400) is provided separately from the MCU300. In this manner, even if an abnormality occurs in the MCU300, which is an arithmetic processing device, the monitor can be prevented from being affected by the abnormality.

In the present example embodiment, the monitor is the PMIC400that performs power management of the MCU300.

By using the PMIC400which is a power management IC of the MCU300as the monitor, it is possible to realize the present disclosure at low cost without newly providing a circuit corresponding to the monitor.

The motor control device40in the present example embodiment further includes the first overvoltage detection circuit610that outputs the first overvoltage detection signal DV1whose state changes depending on the magnitude of the input voltage (inverter input voltage VINV) of the motor drive circuit100. The MCU300compares the inverter input voltage VINVwith the first threshold VTH1, and performs the fail-safe control when the inverter input voltage VINVexceeds the first threshold VTH1. The first overvoltage detection circuit610compares the inverter input voltage VINVwith the second threshold VTH2higher than the first threshold VTH1, and changes the state of the first overvoltage detection signal DV1from a high level to a low level when the inverter input voltage VINVexceeds the second threshold VTH2. The multiplexer800switches the control mode from the first control mode to the second control mode also when the state of the first overvoltage detection signal DV1changes from a high level to a low level.

As usual, when the MCU300performs the fail-safe control at a time point at which an overvoltage exceeding the first threshold is generated to suppress an increase in the inverter input voltage. However, in a case where a large overvoltage exceeding the second threshold is generated, there is a high possibility that the fail-safe control by the MCU300is not functioning correctly. In such a case, switching is made to the second control mode and the fail-safe control by the alternative circuit500is performed, so that the fail-safe control can be continued regardless of the state of the MCU300. Further even in a case where the alternative circuit500is used, appropriate fail-safe control based on the states of the upper arm110and the lower arm120can be executed.

The motor control device40in the present example embodiment further includes the second overvoltage detection circuit620that outputs the second overvoltage detection signal DV2whose state changes depending on the magnitude of the input voltage (inverter input voltage VINV) of the motor drive circuit100. The second overvoltage detection circuit620compares the inverter input voltage VINVwith the third threshold VTH3higher than the second threshold VTH2, and changes the state of the second overvoltage detection signal DV2from a high level to a low level when the inverter input voltage VINVexceeds the third threshold VTH3. The multiplexer800switches the control mode from the first control mode to the second control mode when at least one of the first overvoltage detection signal DV1and the second overvoltage detection signal DV2changes from a high level to a low level. Normally, at a time point at which the first threshold or the second threshold is detected, increase in the inverter input voltage is suppressed by the fail-safe control by the MCU300or the first overvoltage detection circuit610. However, in a case where a large overvoltage exceeding the third threshold is generated, there is a high possibility that the fail-safe control by the MCU300or the first overvoltage detection circuit610is not functioning correctly. In such a case, switching is made to the second control mode and the fail-safe control by the alternative circuit500is performed, so that the fail-safe control can be continued regardless of the state of the MCU300or the first overvoltage detection circuit610. That is, as compared with a case where only the first overvoltage detection circuit610is provided, the possibility that the fail-safe control can be executed is increased when the second overvoltage detection circuit620is further provided, and the safety is improved. Further even in a case where the alternative circuit500is used, appropriate fail-safe control based on the states of the upper arm110and the lower arm120can be executed.

In the present example embodiment, in a case where both the upper arm110and the lower arm120are in a normal state, the alternative circuit500controls all the switching elements included in the upper arm110to an off state and controls all the switching elements included in the lower arm120to an on state.

In this manner, in a case where both the upper arm110and the lower arm120are in a normal state, appropriate fail-safe control can be performed by the alternative circuit500.

In the present example embodiment, in a case where the upper arm110, between the upper arm110and the lower arm120, is in an abnormal state, the alternative circuit500controls all the switching elements included in the upper arm110to an off state and controls all the switching elements included in the lower arm120to an on state.

In this manner, in a case where the upper arm110between the upper arm110and the lower arm120is in an abnormal state, appropriate fail-safe control can be performed by the alternative circuit500.

In the present example embodiment, in a case where the lower arm120, between the upper arm110and the lower arm120, is in an abnormal state, the alternative circuit500controls all the switching elements included in the upper arm110to an on state and controls all the switching elements included in the lower arm120to an off state.

In this manner, in a case where the lower arm120between the upper arm110and the lower arm120is in an abnormal state, appropriate fail-safe control can be performed by the alternative circuit500.

In the present example embodiment, in a case where both the upper arm110and the lower arm120are in an abnormal state, the alternative circuit500controls all the switching elements included in the upper arm110to an off state and controls all the switching elements included in the lower arm120to an off state.

In this manner, in a case where both the upper arm110and the lower arm120are in an abnormal state, appropriate fail-safe control can be performed by the alternative circuit500.

In the present example embodiment, the alternative circuit500determines whether the upper arm110and the lower arm120are in a normal state or an abnormal state on the basis of an abnormality detection signal (fault signal) output from each gate driver of the motor drive circuit100.

In this manner, it is possible to determine whether the upper arm110and the lower arm120are in a normal state or an abnormal state more accurately than a case where the fault signal of the gate driver is not used.

The present disclosure is not limited to the above example embodiment, and the configurations described in the present specification can be appropriately combined within a range not contradictory to each other.

For example, in the above example embodiment, the PMIC400serving as the monitor is provided separately from the MCU300serving as the arithmetic processing device. However, the present disclosure is not limited to this, and the monitor may be provided in the arithmetic processing device, or both the arithmetic processing device including the monitor and the monitor provided separately from the arithmetic processing device may be included.

Further, in a case where the monitor is arranged inside the arithmetic processing device, the control mode may be switched by operation of the mode switching assembly (multiplexer800) using a signal for notifying abnormality output from the arithmetic processing device as a trigger.

Further, in the above example embodiment, the PMIC400is exemplified as the monitor provided separately from the arithmetic processing device. However, the present disclosure is not limited to this, and an electronic device having a function of monitoring a state of the arithmetic processing device may be used as the monitor.

In the above example embodiment, as the motor assembly including the motor control device40, the motor assembly6that applies a driving force to the driving wheel2of the vehicle1that is an electric car is exemplified. However, the present disclosure is not limited to this, and the motor control device of the present disclosure may be included in another motor assembly.

Further, in the above example embodiment, the case where the motor assembly6including the motor control device40is mounted on the vehicle1that is an electric car is exemplified. However, the motor assembly of the present disclosure can be applied to a vehicle other than an electric car, a device that requires a rotational force of a motor, or the like.

In the above example embodiment, the motor assembly6includes one of the motor10and the motor drive circuit100, and the motor drive circuit100includes six switching elements in the upper arm and the lower arm combined. However, the present disclosure is not limited to this. The configuration may be such that the motor assembly6includes a generator motor separately from the motor10, and the motor drive circuit100includes six switching elements for driving the generator motor in addition to the six switching elements for driving the motor10. Further, the configuration may be such that the fail-safe control of the present disclosure can be executed on the switching element that drives the generator motor.

In the above example embodiment, regarding the operation of the motor control device40when the MCU300is in a normal state, the fail-safe control is started when overvoltage of the inverter input voltage is detected. However, the present disclosure is not limited to this. The configuration may be such that a rotation speed detection unit that detects a rotation speed of the motor10is provided, and the fail-safe control is started when the rotation speed detection unit detects a rotation speed exceeding an optional threshold.

In the above example embodiment, regarding the operation of the motor control device40at the time of abnormality of the MCU300, the configuration in which the control mode is switched from the first control mode to the second control mode by output of the mode switching signal MS at a low level to the multiplexer800when overvoltage of the inverter input voltage or abnormality of the MCU300is detected so that the fail-safe control is performed is exemplified. However, the present disclosure is not limited to this. The configuration may be such that a rotation speed detection unit that detects a rotation speed of the motor10is provided, and the control mode is switched from the first control mode to the second control mode by output of the mode switching signal MS at a low level to the multiplexer800when the rotation speed detection unit detects a rotation speed exceeding an optional threshold, so that the fail-safe control is performed.

In the above example embodiment, the configuration in which the motor assembly6inputs power to the motor drive circuit100without increasing or decreasing the voltage of the high-voltage battery7is exemplified. However, the present disclosure is not limited to this. The motor assembly6may include a DC-DC converter that increases or decreases voltage of the high-voltage battery7.

In the above example embodiment, the configuration may be such that the inverter input voltage, a rotation speed of the motor10, a state of the MCU300, and the like after the fail-safe control is executed are detected. The configuration may be such that, for example, after the fail-safe control, in a case where the inverter device changes from a low safety state to a high safety state, such as when it is detected that the inverter input voltage or the motor rotational speed returns to a predetermined threshold or less, or when it is detected that the MCU300returns from an abnormal state to a normal state, the fail-safe control is finished even if the rotation of the motor10is not stopped, and the switching control returns to that at the normal time.

In the above example embodiment, the configuration may be such that the gate control signal output from the multiplexer800is monitored so that a short-circuit state of the motor drive circuit100is prevented. For example, in a case where both the U-phase upper gate control signal UHG and the U-phase lower gate control signal ULG are at a high level, both the U-phase upper switching element QUHand the U-phase lower switching element QUHare in an on state, and the motor drive circuit100is short-circuited. The configuration may be such that, when it is detected that the gate control signals are output at a high level in both the upper and lower arms in the same phase as described above, the supply of the gate control signal to the motor drive circuit100is stopped, or all the switching elements are set to off.

In the above example embodiment, all of the OR circuit700, the first OR circuit510, and the second OR circuit520are OR circuits of the negative logic. However, these circuits may be OR circuits of the positive logic. Furthermore, the logic of each signal may be reversed, and, for example, operation described below may be executed. In a case where at least one high-level signal is input to the OR circuit700of the positive logic, the control mode is switched from the first control mode to the second control mode by output of the mode switching signal MS at a high level to the multiplexer800. When the switching element included in the upper arm110is abnormal, at least one of three upper gate drivers outputs an FLT signal at a high level to the first OR circuit510of the positive logic. The first logic circuit510of the positive logic outputs the upper arm fault signal FLTH at a high level to the matrix circuit530. The matrix circuit530outputs the first output signal OUT1at a high level to the first switch540. In the first switch540, the contact541and the contact543are electrically connected, so that the upper arm control signal HG having the high-level voltage VHi is output from the contact543to the multiplexer800. The multiplexer800outputs the U-phase upper gate control signal UHG, the V-phase upper gate control signal VHG, and the W-phase upper gate control signal WHG, all of which are set at a high level, to three upper gate drivers.

Features of the above-described preferred example embodiments and the modifications thereof may be combined appropriately as long as no conflict arises.

While example embodiments of the present disclosure have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the present disclosure. The scope of the present disclosure, therefore, is to be determined solely by the following claims.