Patent ID: 12213248

DETAILED DESCRIPTION OF THE EMBODIMENTS

Embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals designate corresponding or identical elements throughout the various drawings.

EMBODIMENT

A printed wiring board1of an embodiment is formed by alternately laminating multiple resin insulating layers and multiple conductor layers.FIG.1is a cross-sectional view illustrating a part of the printed wiring board1of the embodiment. As illustrated inFIG.1, the printed wiring board1includes a second conductor layer50, a first resin insulating layer30, a first conductor layer10, a second resin insulating layer40, and a third conductor layer60. The second conductor layer50, the first resin insulating layer30, the first conductor layer10, the second resin insulating layer40, and the third conductor layer60are laminated in this order and form a stripline structure. The second conductor layer50, the first resin insulating layer30, the first conductor layer10, the second resin insulating layer40, and the third conductor layer60can form a part of a build-up layer formed on a core substrate. The printed wiring board1may have a resin insulating layer and a conductor layer other than the second conductor layer50, the first resin insulating layer30, the first conductor layer10, the second resin insulating layer40, and the third conductor layer60.

The second conductor layer50is formed of copper. The second conductor layer50is formed of a seed layer52and an electrolytic plating film54on the seed layer52. The second conductor layer50is entirely or partially a solid layer. The second conductor layer50is a power line or a ground line.

The first resin insulating layer30is formed on the second conductor layer50. The first resin insulating layer30is formed using a thermosetting resin. The first resin insulating layer30may contain inorganic particles such as silica particles. The first resin insulating layer30may contain a reinforcing material such as a glass cloth. A dielectric loss tangent (Df) of the first resin insulating layer30is 0.02 or less.

The first conductor layer10is formed on the first resin insulating layer30. The first conductor layer10is formed of copper. The first conductor layer10includes wirings (12,14) and solid layers (16,18). The wirings (12,14) are signal lines. The solid layers (16,18) are each a power line or a ground line. The wirings (12,14) and the solid layers (16,18) are each formed of a seed layer22and an electrolytic plating film24on the seed layer22. When the above first resin insulating layer30contains a reinforcing material such as glass cloth, a copper foil may be provided between the first resin insulating layer30and the seed layer22.

The second resin insulating layer40is formed on the first resin insulating layer30and the first conductor layer10. The second resin insulating layer40is formed using a thermosetting resin. The second resin insulating layer40may contain inorganic particles such as silica particles. The second resin insulating layer40may contain a reinforcing material such as a glass cloth. A dielectric loss tangent (Df) of the second resin insulating layer40is 0.02 or less. In the printed wiring board1of the embodiment, the dielectric loss tangent (Df) of the first resin insulating layer30and the dielectric loss tangent (Df) of the second resin insulating layer40are both 0.02 or less. Therefore, transmission losses of the wirings (12,14) are small.

The third conductor layer60is formed on the second resin insulating layer40. The third conductor layer60is formed of copper. The third conductor layer60is formed of a seed layer62and an electrolytic plating film64on the seed layer62. The third conductor layer60is entirely or partially a solid layer. The third conductor layer60is a power line or a ground line. When the above second resin insulating layer40contains a reinforcing material such as glass cloth, a copper foil may be provided between the second resin insulating layer40and the seed layer62.

As described above, in the embodiment, a stripline structure is formed in which the wirings (12,14) embedded in the first resin insulating layer30and the second resin insulating layer40are sandwiched between the second conductor layer50and the third conductor layer60.

Surfaces of Wirings

In the following, a surface of the wiring12is described with reference toFIGS.2,3,4A, and4B. InFIGS.2,3,4A, and4B, the wiring12is described as an example. However, the same description also applies to the wiring14.FIG.2is an enlarged cross-sectional view of the wiring12.FIG.2is obtained by cutting the wiring12in a plane perpendicular to the first resin insulating layer30. A length of an entire outer circumference of the cross section of the wiring12ofFIG.2is about 50 μm. As illustrated inFIG.2, a large number of recesses (grooves) are formed on the outer circumference of the cross section of the wiring12. Shapes and depths of the large number of recesses are irregular.

FIG.3is an enlarged cross-sectional view of a part of an upper side of the cross section of the wiring12ofFIG.2(portion (III) ofFIG.2). A length of the outer circumference contained in the portion (III) is about 15 μm. As illustrated inFIG.3, among multiple recesses (G1-G13) formed in the portion (III), there are three recesses (G9, G10, G11) that are relatively deep having a depth of 2.0 μm or more and of which a diameter of a bottom part is larger than a diameter of an opening part. In the embodiment, the number of recesses that are formed on the surface of the wiring12and are relatively deep having a depth of 2.0 μm or more and of which a diameter of a bottom part is larger than a diameter of an opening part is small. A recess that has a depth of 2.0 μm or more and of which a diameter of a bottom part is larger than a diameter of an opening part may be referred to as a “crevasse-like recess.” InFIG.3, for the recess (G3), a diameter of a bottom part is larger than a diameter of an opening part, but a depth is less than 2.0 μm, and thus, the recess (G3) is not a crevasse-like recess. For the recess (G12), a depth is 2.0 μm, but a diameter of an opening part is larger than a diameter of a bottom part, and thus, the recess (G12) is not a crevasse-like recess. The length of the entire outer circumference of the cross section of the wiring12inFIG.2is about 50 μm. However, the number of the above-described crevasse-like recesses (recesses that have a depth of 2.0 μm or more and of which a diameter of a bottom part is larger than a diameter of an opening part) is 5 or less on the entire circumference. That is, in the embodiment, the number of crevasse-like recesses is 10 or less per 100 μm length of the outer circumference of the cross section of the wiring12(seeFIG.2).

FIGS.4A and4Bare each a cross-sectional view for describing a “depth of a recess” in the embodiment. The depths of the recesses are measured by analyzing an image of the cross section of the wiring12.FIGS.4A and4Brespectively illustrate two examples. The example ofFIG.4Aillustrates the recess (G21). The recess (G21) has a shape in which a diameter of a bottom part (B21) is larger than a diameter of an opening part (A21). A depth (D21) of the recess (G21) is a linear distance from the opening part (A21) to the bottom part (B21). The example ofFIG.4Billustrates the recess (G22). The recess (G22) has a shape of which an inner part bends on one side. A depth (D22) of the recess (G22) is a linear distance from an opening part (A22) to a bottom part (B22). In this way, a depth of a recess is a linear distance from an opening part to a bottom part regardless of a shape of the recess. In practice, the depths of the recesses are measured by analyzing an image of the cross section of the wiring12.

For recesses (crevasse-like recesses) that are among the recesses formed on the surface of the wiring12and are relatively deep having a depth of 2.0 μm or more and of which a diameter of a bottom part is larger than a diameter of an opening part, accurate roughness measurement using a common roughness measurement device is difficult and the transmission loss of the wiring12is highly likely to be increased. Therefore, when the number of crevasse-like recesses is large, the transmission loss of the wiring12increases. When the number of the crevasse-like recesses per 100 μm length of the outer circumference of the cross section of the wiring12is 10 or less as in the embodiment, the transmission loss of the wiring12is relatively small. Therefore, according to the embodiment, the printed wiring board1having the wirings (12,14) with low transmission losses is provided. The wirings (12,14) of the present embodiment are each an example of a “conductor circuit.”

In a formation process of the wirings (12,14), surfaces of the wirings (12,14) are roughened by performing etching (for example, a CZ roughening treatment) for rough surface formation. The etching (CZ roughening treatment) for rough surface formation is a treatment performed after a quick etching treatment for seed layer removal. Hereinafter, the etching for rough surface formation may be simply referred to as “etching.” By roughening the surfaces of the wirings (12,14) by etching, adhesion to the first resin insulating layer40is improved. When the surfaces of the wirings (12,14) are etched, an etching amount is, for example, 1.0 μm in a depth direction from a surface of a wiring. In another example, an etching amount may be 0.5 μm in a depth direction from a surface of a wiring. On the other hand, it is also possible that the surfaces of the wirings (12,14) are not etched (not roughened). Here, the “etching amount” is a depth amount by which the surface of the wiring is etched in a depth direction by the etching (CZ roughening treatment) for rough surface formation described above.

In the embodiment, a root mean square height (Rq) of the surfaces of the wirings (12,14) is 1.00 μm or less. A ten-point average roughness (Rz) of each of the surfaces of the wirings (12,14) is 2.00 μm or less. The above numerical values (Rq, Rz) are calculated based on actual measurement values measured using a 3D microscope (for example, a shape analysis laser microscope “VK-X1000”).

In the printed wiring board1of the embodiment, on the surface of the second conductor layer50, the surfaces of the solid layers (16,18), and the surface of the third conductor layer60, the number of crevasse-like recesses per 100 μm length of an outer circumference of a cross section may be more than 10. When a large number of crevasse-like recesses are formed on the surface of the second conductor layer50, the surfaces of the solid layers (16,18), and the surface of the third conductor layer60, a high anchor effect is realized. Further, the second conductor layer50, the solid layers (16,18), and the third conductor layer60are all each a power line or a ground line, and thus, the transmission loss does not cause a problem.

Method for Manufacturing Printed Wiring Board

FIGS.5A-5Gillustrate a method for manufacturing the printed wiring board1of the embodiment.FIG.5Aillustrates the second conductor layer50formed of the seed layer52and the electrolytic plating film54on the seed layer52. The upper surface of the second conductor layer50is roughened by etching. As illustrated inFIG.5B, the first resin insulating layer30is formed on the second conductor layer50. The upper surface of the first resin insulating layer30is roughened by a permanganate treatment. As illustrated inFIG.5C, the seed layer22is formed on the first resin insulating layer30. As illustrated inFIG.5D, a plating resist80is formed on the seed layer22. The plated resist80has openings for forming the wirings (12,14) and the solid layers (16,18) (FIG.1).

As illustrated inFIG.5E, the electrolytic plating film24is formed on the seed layer22exposed from the plating resist80. The electrolytic plating film24fills the openings. The wirings (12,14) and the solid layers (16,18) are formed of the seed layer22and the electrolytic plating film24formed on the seed layer22. As a result, the first conductor layer10is formed.

As illustrated inFIG.5F, the plating resist80is removed. As illustrated inFIG.5G, the seed layer22exposed from the electrolytic plating film24is removed by a quick etching treatment.

After that, in a state in which the wirings (12,14) are masked, the surfaces of the solid layer (16,18) are roughened by etching (a CZ roughening treatment). The surfaces of the wirings (12,14) after the mask is removed are subjected to 1.0 μm etching. It is also possible that the surfaces of the wirings (12,14) are subjected to 0.5 μm etching. It is also possible that the surfaces of the wirings (12,14) are not subjected to etching. The surfaces of the wirings (12,14) may be treated such that the number of recesses (crevasse-like recesses) that have a depth of 0.2 μm or more and of which a diameter of a bottom part is larger than a diameter of an opening part is 10 or less per 100 μm length of an outer circumference of a cross section of each of the wirings (12,14).

After that, the second resin insulating layer40is formed on the first resin insulating layer30and the first conductor layer10. The upper surface of the first resin insulating layer30is roughened by a permanganate treatment. The third conductor layer60formed of the seed layer62and the electrolytic plating film64on the seed layer62is formed on the second resin insulating layer40. The stripline structure is formed. As a result, the printed wiring board1(FIG.1) of the embodiment is obtained.

First Modified Embodiment

An example of a difference of a printed wiring board1of a first modified embodiment from that of the embodiment is described below. In the first modified embodiment, further, the number of recesses (crevasse-like recesses) that have a depth of 0.2 μm or more and of which a diameter of a bottom part is larger than a diameter of an opening part is 10 or less per 100 μm length of an outer circumference of a cross section of each of the solid layers (16,18). That is, in the first modified embodiment, the number of crevasse-like recesses is 10 or less per 100 μm length of an outer circumference of a cross section of each of the wirings (12,14) and the solid layers (16,18) of the first conductor layer10. In the first modified embodiment, the wirings (12,14) and the solid layers (16,18) are each an example of a “conductor circuit.”

Second Modified Embodiment

In a second modified embodiment, the number of crevasse-like recesses is 10 or less per 100 μm length of an outer circumference of a cross section of at least one of the second conductor layer50and the third conductor layer60. That is, in the second modified embodiment, the number of crevasse-like recesses is 10 or less per 100 μm length of an outer circumference of a cross section of each of the wirings (12,14) of the first conductor layer10and at least one of the second conductor layer50and the third conductor layer60. In the second modified embodiment, the wirings (12,14) and at least one of the second conductor layer50and the third conductor layer60are each an example of a “conductor circuit.”

Third Modified Embodiment

In a third modified embodiment, the number of crevasse-like recesses is 10 or less per 100 μm length of an outer circumference of a cross section of each of the wirings (12,14) and the solid layers (16,18) of the first conductor layer10and all the second conductor layer50and the third conductor layer60. In the third modified embodiment, the wirings (12,14), the solid layers (16,18), the second conductor layer50, and the third conductor layer60are each an example of a “conductor circuit.”

Fourth Modified Embodiment

In a fourth modified embodiment, a printed wiring board1does not have a stripline structure. The printed wiring board1of the fourth modified embodiment includes multiple resin insulating layers and multiple conductor layers alternately laminated with the multiple resin insulating layers, and may have any structure as long as the number of crevasse-like recesses is 10 or less per 100 μm length of an outer circumference of a cross section of a conductor circuit included in the multiple conductor layers.

Fifth Modified Embodiment

In a fifth modified embodiment, the root mean square height (Rq) of the surfaces of the wirings (12,14) are larger than 1.0 μm. The ten-point average roughness (Rz) of each of the surfaces of the wirings (12,14) is larger than 2.00 μm.

Six Modified Embodiment

In a sixth modified embodiment, the dielectric loss tangent (Df) of each of the first resin insulating layer30and the second resin insulating layer40is larger than 0.02.

It is thought that it may be possible that a numerical value representing a surface roughness, such as a ten-point average roughness (Rz), an arithmetic mean roughness (Ra), or a root mean square height (Rq), is not proportional to an actual transmission loss of a wiring.

A printed wiring board according to an embodiment of the present invention includes: multiple resin insulating layers; and multiple conductor layers that are alternately laminated with the multiple resin insulating layers. The multiple conductor layers include a conductor circuit. The number of recesses that have a depth of 2.0 μm or more and of which a diameter of a bottom is larger than a diameter of an opening part is 10 or less per 100 μm length of an outer circumference of a cross section of the conductor circuit.

Among recesses formed on a surface of a conductor circuit, recesses that are relatively deep having a depth of 2.0 μm or more and of which a diameter of a bottom part is larger than a diameter of an opening part are highly likely to increase a transmission loss of the conductor circuit. In a printed wiring board according to an embodiment of the present invention, the number of recesses that have a depth of 2.0 μm or more and of which a diameter of a bottom part is larger than a diameter of an opening part is 10 or less per 100 μm length of an outer circumference of a cross section of a conductor circuit. Therefore, according to an embodiment of the present invention, since the number of the recesses that have a depth of 2.0 μm or more and of which a diameter of a bottom part is larger than a diameter of an opening part is relatively small, a printed wiring board having a conductor circuit with a low transmission loss is provided.

Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.