Patent ID: 12230553

DETAILED DESCRIPTION

In order to facilitate the understanding of the present disclosure, the present disclosure is described more comprehensively below with reference to the drawings. The embodiments of the present disclosure are shown in the drawings. However, the present disclosure may be embodied in various forms without being limited to the embodiments described herein. These embodiments are provided in order to make the present disclosure more thorough and comprehensive.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field of the present disclosure. The terms mentioned herein are merely for the purpose of describing specific embodiments, rather than to limit the present disclosure.

It should be understood that when an element or layer is “on”, “adjacent to”, “connected to” or “coupled to” other element or layer, it may be on, adjacent to, connected to or coupled to other element or layer directly or indirectly via an intermediate element or layer. When an element is “directly on”, “directly adjacent to”, “directly connected to” or “directly coupled to” other element or layer, there is no intermediate element or layer. It should be understood that although the terms such as “first”, “second” and “third” may be used to describe various elements, components, regions, layers, doping types and/or portions, these elements, components, regions, layers, doping types and/or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Therefore, a first element, component, region, layer, doping type or portion described may be expressed as a second element, component, region, layer or portion without departing from the concept of the present disclosure.

Terms such as “under”, “below”, “underneath”, “beneath”, “above” and “on” are intended to describe the spatial relationship between one element or feature and other element or feature shown in the drawings. It should be understood that these terms are also intended to indicate different orientations of devices in use and operation in addition to the orientations shown in the drawings. For example, if the device in the drawing is flipped, an element or feature described as “under”, “underneath” or “below” other element will be oriented “on” the other element or feature. Therefore, the exemplary terms “under” and “below” may include the orientations of “above” and “below”. In addition, the device may also include other orientations (for example, 90° rotation or other orientations), and the terms used herein should be explained accordingly.

In this specification, the singular forms of “a”, “an” and “the/this” may also include plural forms, unless clearly indicated otherwise. It should also be understood that the terms such as “including/comprising” and “having” indicate the existence of the stated features, wholes, steps, operations, components, parts or combinations thereof. However, these terms do not exclude the possibility of the existence of one or more other features, wholes, steps, operations, components, parts or combinations thereof. Meanwhile, in this specification, the term “and/or” includes any and all combinations of related listed items.

The embodiments of the present disclosure are described herein with reference to schematic diagrams or cross-sectional views of ideal embodiments (and intermediate structures) of the present disclosure, in anticipation of changes in the illustrated shape due to, for example, manufacturing technology and/or tolerances. Therefore, the embodiments of the present disclosure should not be limited to the specific shape shown here, but include shape deviations due to, for example, manufacturing technology.

Referring toFIG.1, an embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure includes a base100, an insulating layer200and a conductive structure320.

The base100includes a substrate110and a dielectric layer120. The substrate110includes a front surface110aand a back surface110bthat are opposite to each other. The dielectric layer120is formed on the front surface110a. The base100is provided with a via hole100a. The via hole100apenetrates the substrate110from the back surface110bof the substrate100and extends to the dielectric layer120. The insulating layer200is located on an inner wall surface of the via hole100a. The conductive structure320includes a first conductive layer321and a second conductive layer322connected to each other. The first conductive layer321is close to a bottom of the via hole100a, and the second conductive layer322is close to a top of the via hole100a. A diameter of the first conductive layer321is less than that of the second conductive layer322.

In this embodiment, the diameter of the first conductive layer321corresponding to a semiconductor device formed between the substrate110and the dielectric layer120is small. Therefore, the expansion stress of the first conductive layer321on the substrate110and the dielectric layer120in this corresponding part is small, thereby reducing the thermal stress of the conductive structure320on the surrounding device.

In an embodiment, the semiconductor structure further includes a barrier layer310. The barrier layer310is located on a surface of the insulating layer200, and there is a gap100bbetween the barrier layer310and the first conductive layer321. The gap100bmay be filled with air or other heat insulating medium. The barrier layer310is a film layer that effectively inhibits the thermal expansion stress of the conductive structure320. The barrier layer310may be made of tantalum (Ta), tantalum nitride (TaN), etc., and may have a thickness of 0.05-0.1 μm. The barrier layer310can effectively reduce the thermal expansion coefficient of the conductive structure320when the conductive structure320is thermally expanded.

Since the air in the gap100bhas poor thermal conductivity, the heat generated by the conductive structure320can be further prevented from spreading to the surrounding device. Meanwhile, the gap100bisolates the first conductive layer321from the barrier layer310, thereby effectively blocking the thermal expansion stress of the first conductive layer, so as to better protect the surrounding device.

In an embodiment, the first conductive layer321and the barrier layer310are spaced apart, and the second conductive layer322is connected to the barrier layer310. The first conductive layer321may be made of a metal conductive material such as copper (Cu). Specifically, the first conductive layer may include a first seed layer and a first conductive portion. The first seed layer is formed on a surface of the barrier layer310, and the first conductive portion is formed on a surface of the first seed layer.

In an embodiment, the semiconductor structure further includes an isolation layer330. The isolation layer330is located at the bottom of the via hole100aand between the barrier layer310and the first conductive layer321. The barrier layer310, the isolation layer330, the first conductive layer321and the second conductive layer322together enclose the gap100bfilled with air.

In an embodiment, the second conductive layer322includes a second seed layer3221and a second conductive portion3222. The second seed layer3221surrounds the second conductive portion3222. A sidewall of the second seed layer3221is in contact with the barrier layer310, and the bottom of the second seed layer3221is in contact with the first conductive layer321.

An embodiment further provides a stacked structure. The stacked structure is formed by processing the above-mentioned semiconductor structure.

Specifically, when the stacked structure is formed, the above-mentioned semiconductor structure is processed through a process such as etching or planarization, such that the conductive structure320in the dielectric layer120is exposed (not shown). In this way, when this semiconductor structure is stacked with an adjacent semiconductor structure, the conductive structure320in the via hole100acan be conductively connected to achieve signal transmission.

Referring toFIG.2, an embodiment provides a manufacturing method of a semiconductor structure. The manufacturing method includes:

Step S1: Provide a base, where the base includes a substrate and a dielectric layer;

the substrate includes a front surface and a back surface that are opposite to each other;

the dielectric layer is formed on the front surface; the base is provided with a via hole;

and the via hole penetrates the substrate from the back surface of the substrate and extends to the dielectric layer.

Step S2: Form an insulating layer on an inner wall surface of the via hole.

Step S3: Form a conductive structure on a surface of the insulating layer, where the conductive structure includes a first conductive layer and a second conductive layer connected to each other; the first conductive layer is close to a bottom of the via hole, and the second conductive layer is close to a top of the via hole; and a diameter of the first conductive layer is less than that of the second conductive layer.

The manufacturing method of a semiconductor structure is described in detail below with references toFIGS.1and3to11.

Step S100: Provide a base100.

As shown inFIG.3, the base100includes a substrate110and a dielectric layer120. The substrate110has a front surface110aand a back surface110bthat are opposite to each other. The dielectric layer120is formed on the front surface110a.

In Step S100, the substrate110may include, but is not limited to, a silicon substrate. A shallow trench isolation structure400may be formed on a side of the substrate110close to the dielectric layer120. The shallow trench isolation structure400isolates the substrate110into multiple active regions. The active regions are used to form various semiconductor devices.

The dielectric layer120may include, but is not limited to, a dielectric layer made of an oxide (such as silicon dioxide). A via structure and a metal layer electrically connecting the active regions may be formed in the dielectric layer120, so as to draw out signals of the semiconductor devices to the outside or provide an external signal for the semiconductor devices.

Step S200: Form a via hole100ain the base100.

Referring toFIG.4, specifically, the base100shown inFIG.3may be etched from the back surface110bof the substrate110by dry etching, thereby forming the base100with the via hole100a. The via hole100apenetrates the substrate110from the back surface110bof the substrate110and extends to the dielectric layer120. The depth of the via hole100amay be 20-150 μm, and the depth that the via hole extends into the dielectric layer120may be 0.5-1 μm. The diameter of the via hole100amay be 3-50 μm. The depth-to-width ratio (that is, the ratio of the depth to the diameter) of the via hole100amay be 0.4-50.

The via hole100ais used to form a conductive structure therein. When chips formed by multiple semiconductor structures are stacked, the corresponding via holes100aof the chips are aligned, such that the conductive structures in the via holes100aare electrically connected, thereby realizing interconnection between the chips.

The back surface110bof the substrate110is far away from the semiconductor devices formed in the active regions and circuit structures connecting the semiconductor devices. Therefore, in this embodiment, when the via hole100ais formed, damage to the semiconductor devices formed in the active regions and the related circuit structures is effectively prevented.

Step S300: Form an insulating layer200on an inner wall surface of the via hole100a.

Referring toFIG.5, the insulating layer200is used to achieve electrical isolation between the conductive structure and the substrate110. The insulating layer200may be made of silicon dioxide, etc. The materials of the insulating layer200and the dielectric layer120may be the same or different.

When the insulating layer200is made of silicon dioxide, specifically, a silicon dioxide film layer may be deposited as the insulating layer200on an inner wall of the via hole100athrough chemical vapor deposition (CVD) based on silane (SiH4) or tetraethyl orthosilicate (TEOS). The thickness of the silicon dioxide film layer may be 0.2-2 μm.

Step S400: Form a barrier layer310on a surface of the insulating layer200.

Referring toFIG.6, the barrier layer310may be made of tantalum (Ta), tantalum nitride (TaN), etc., and may have a thickness of 0.05-0.1 μm.

Step S500: Form a primary isolation layer331on a surface of the barrier layer310, where the primary isolation layer331includes a sidewall portion3311.

Referring toFIG.7, the primary isolation layer331is made of an insulating material. As an example, the primary isolation layer331may be made of silicon dioxide. Specifically, a 0.2-2 μm thick silicon dioxide film layer may be deposited as the primary isolation layer331on the inner wall of the via hole100athrough CVD based on silane (SiH4) or tetraethyl orthosilicate (TEOS).

Step S600: Form a primary conductive layer3211on a surface of the primary isolation layer331.

Referring toFIG.8, specifically, a first primary seed layer may be formed on the surface of the barrier layer310, and then a first primary conductive layer may be formed on a surface of the first primary seed layer. The first primary conductive layer and the first primary seed layer define the primary conductive layer3211.

As an example, the primary conductive layer3211may be made of copper (Cu). In this case, a copper seed layer may be formed on the surface of the barrier layer310as the first primary seed layer through physical vapor deposition (PVD). Then, copper (Cu) is electroplated on a surface of the first primary seed layer to form the first primary conductive layer.

Since a part of the primary conductive layer3211is to be removed in a subsequent step S700to form a gap100bfilled with air, the primary conductive layer3211grown on the surface of the barrier layer310may not fill the via hole100a. As an example, the filling thickness of a central part of the primary conductive layer3211may be 20-70% of the depth of the via hole100a.

Step S700: Remove a part of the primary conductive layer3211to expose a part of the sidewall portion3311, such that the remaining primary conductive layer3211defines a first conductive layer321.

Referring toFIG.9, a part of the primary conductive layer3211covering the sidewall portion3311may be removed by a mixed acid solution (for example, a mixed solution of H2SO4/H2O2), so as to expose a part of the sidewall portion3311of the primary isolation layer331and form the first conductive layer321.

Specifically, in this case, the first primary seed layer forms a first seed layer, and the first primary conductive layer forms a first conductive portion. The first seed layer and the first conductive portion define the first conductive layer321.

Step S800: Remove a part of the sidewall portion3311to form the gap100bbetween the barrier layer310and the first conductive layer321, where the remaining primary isolation layer331defines an isolation layer330.

Referring toFIG.10, specifically, the sidewall portion3311of the primary isolation layer331(such as a silicon dioxide film layer) may be etched by hydrofluoric acid or dry etching to form the gap100bbetween the barrier layer310and the first conductive layer321.

After a part of the primary isolation layer331is removed, a distance H1between a surface of the isolation layer330formed by the remaining primary isolation layer331and an opening of the via hole100ais greater than a distance H2between a surface of the first conductive layer321and the opening of the via hole100a. That is, after this part of the primary isolation layer331is removed, an upper surface of the isolation layer330formed by the remaining primary isolation layer331is lower than that of the first conductive layer321.

In this embodiment, by forming the isolation layer330, the first conductive layer321and the barrier layer310are spaced apart easily and effectively. Of course, in other embodiments, the isolation layer330may not be formed. Instead, the first conductive layer321and the barrier layer310may be spaced apart by other means, which is not limited herein.

Step S900: Form a second seed layer3221on the surface of the barrier layer310and the surface of the first conductive layer321, where the second seed layer3221closes the gap100b, thereby forming the gap100bon two sides of the first conductive layer321.

Referring toFIG.11, specifically, the second seed layer3221may be formed through PVD, etc. In this embodiment, the second seed layer3221facilitates the subsequent formation of a second conductive portion3222and closes the gap100b.

Step S1000: Form the second conductive portion3222on a surface of the second seed layer3221, where the second conductive portion3222and the second seed layer3221define a second conductive layer322.

Referring toFIG.1, specifically, the second conductive portion3222may be formed through electroplating, etc. In other embodiments, the first conductive layer321and the second conductive layer322of the conductive structure320may also be formed simultaneously through a single process. The materials of the first conductive layer321and the second conductive layer322are the same. For example, they are both made of copper (Cu). In this way, the first conductive layer321is in good contact with the second conductive layer322, thereby reducing the contact resistance of the conductive layers and effectively reducing the impedance of the conductive structure320. Of course, in other embodiments, the materials of the first conductive layer321and the second conductive layer322may also be different.

Of course, it is understandable that in the present disclosure, the semiconductor structure is not limited to being formed by the manufacturing method in the above embodiments.

In the specification, the description of terms such as “an embodiment” and “an ideal embodiment” means that the specific feature, structure, material or characteristic described in combination with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

The technical characteristics of the above examples can be employed in arbitrary combinations. In an effort to provide a concise description of these examples, all possible combinations of all technical characteristics of the examples may not be described; however, these combinations of technical characteristics should be construed as disclosed in the description as long as no contradiction occurs.

Only several implementations of the present disclosure are described in detail above, but they should not therefore be construed as limiting the scope of the present disclosure. It should be noted that those of ordinary skill in the art can further make variations and improvements without departing from the concept of the present disclosure. These variations and improvements all fall within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope defined by the claims.