Patent ID: 12256542

DETAILED DESCRIPTION

As discussed above, the embodiments of the present disclosure are directed to a bonded three-dimensional memory device employing a pillar contact between vertical semiconductor channels and a source layer and methods of making the same, the various aspects of which are described below. The embodiments of the present disclosure can be used to form various structures including a multilevel memory structure, non-limiting examples of which include semiconductor devices such as three-dimensional memory array devices comprising a plurality of NAND memory strings. The embodiments of the present disclosure can be used to form a bonded assembly of multiple semiconductor dies including a memory die. Support circuitry (also referred to as peripheral or driver circuitry) used to perform write, read, and erase operations of the memory cells in the vertical NAND strings may be implemented in CMOS devices formed on a same substrate as the three-dimensional memory device. In such devices, design and manufacturing consideration is that degradation of CMOS devices due to collateral thermal cycling and hydrogen diffusion during manufacture of the three-dimensional memory device places severe constraints on performance of the support circuitry. Various embodiments include methods that provide high-performance support circuitry for three-dimensional memory device. Various embodiments include methods that provide a source layer in three-dimensional memory devices that is easier to implement than conventional methods.

The drawings are not drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are used merely to identify similar elements, and different ordinals may be used across the specification and the claims of the instant disclosure. The same reference numerals refer to the same element or similar element. Unless otherwise indicated, elements having the same reference numerals are presumed to have the same composition. Unless otherwise indicated, a “contact” between elements refers to a direct contact between elements that provides an edge or a surface shared by the elements. As used herein, a first element located “on” a second element can be located on the exterior side of a surface of the second element or on the interior side of the second element. As used herein, a first element is located “directly on” a second element if there exist a physical contact between a surface of the first element and a surface of the second element. As used herein, a “prototype” structure or an “in-process” structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component therein. As used herein, a first electrical component is electrically connected to a second electrical component if there exists an electrically conductive path between the first electrical component and the second electrical component.

As used herein, a “layer” refers to a material portion including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer may be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer may extend horizontally, vertically, and/or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layer thereupon, thereabove, and/or therebelow.

A monolithic three-dimensional memory array is one in which multiple memory levels are formed above a single substrate, such as a semiconductor wafer, with no intervening substrates. The term “monolithic” means that layers of each level of the array are directly deposited on the layers of each underlying level of the array. In contrast, two dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device. For example, non-monolithic stacked memories have been constructed by forming memory levels on separate substrates and vertically stacking the memory levels, as described in U.S. Pat. No. 5,915,167 titled “Three-dimensional Structure Memory.” The substrates may be thinned or removed from the memory levels before bonding, but as the memory levels are initially formed over separate substrates, such memories are not true monolithic three-dimensional memory arrays.

Generally, a semiconductor package (or a “package”) refers to a unit semiconductor device that can be attached to a circuit board through a set of pins or solder balls. A semiconductor package may include a semiconductor chip (or a “chip”) or a plurality of semiconductor chips that are bonded thereamongst, for example, by flip-chip bonding or another chip-to-chip bonding. A package or a chip may include a single semiconductor die (or a “die”) or a plurality of semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or a chip with multiple dies is capable of simultaneously executing as many external commands as the total number of dies therein. Each die includes one or more planes. Identical concurrent operations can be executed in each plane within a same die, although there may be some restrictions. In case a die is a memory die, i.e., a die including memory elements, concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within a same memory die. Each plane contains a number of memory blocks (or “blocks”), which are the smallest unit that can be erased by in a single erase operation. Each memory block contains a number of pages, which are the smallest units that can be selected for programming.

Referring toFIG.1, a first exemplary structure according to an embodiment of the present disclosure is illustrated, which can be used, for example, to fabricate a device structure containing vertical NAND memory devices. The first exemplary structure includes a carrier substrate9, a dielectric spacer layer12, a semiconductor material layer14, and an alternating stack of first material layers32and second material layers42located over the semiconductor material layer14. In one embodiment, the carrier substrate9may comprise a semiconductor substrate, an insulating substrate, or a conductive substrate. The carrier substrate9has a thickness that is sufficient to provide structural support to the dielectric spacer layer12, the semiconductor material layer14, and the alternating stack that are formed thereabove. In one embodiment, the carrier substrate9may comprise a commercially-available silicon wafer.

The dielectric spacer layer12comprises a dielectric material such as undoped silicate glass (i.e., silicon oxide) or a doped silicate glass. The dielectric spacer layer12may be formed by deposition of a dielectric material. Alternatively, in case the carrier substrate9comprises a semiconductor material, such as a single crystalline silicon or polysilicon, the dielectric spacer layer12may be formed by oxidation of a surface portion of the carrier substrate9. The thickness of the dielectric spacer layer12may be in a range from 10 nm to 200 nm, such as from 20 nm to 100 nm, although lesser and greater thicknesses may also be employed.

The semiconductor material layer14includes a semiconductor material such as amorphous silicon, polysilicon, or silicon-germanium alloy. The semiconductor material layer14may be formed by a chemical vapor deposition (CVD) process (e.g., low pressure CVD, plasma enhanced CVD, etc.) or by a physical vapor deposition (PVD) process. The thickness of the semiconductor material layer14may be in a range from 50 nm to 300 nm, such as from 100 nm to 250 nm, although lesser and greater thicknesses may also be employed. The semiconductor material layer14may comprise a heavily doped (e.g., p-type or n-type doped) amorphous silicon or polysilicon layer which may function as a source side select gate electrode of a NAND device.

The alternating stack of the first material layers and the second material layers can be formed over the semiconductor material layer14. Each first material layer includes a first material, and each second material layer includes a second material that is different from the first material. In one embodiment, each first material layer can be an insulating layer32, and each second material layer can be a sacrificial material layer42.

The first material of the insulating layers32can be at least one insulating material. As such, each insulating layer32can be an insulating material layer. Insulating materials that can be used for the insulating layers32include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides that are commonly known as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the insulating layers32can be silicon oxide.

The second material of the sacrificial material layers42is a sacrificial material that can be removed selective to the first material of the insulating layers32. As used herein, a removal of a first material is “selective to” a second material if the removal process removes the first material at a rate that is at least twice the rate of removal of the second material. The ratio of the rate of removal of the first material to the rate of removal of the second material is herein referred to as a “selectivity” of the removal process for the first material with respect to the second material. The sacrificial material layers42may comprise an insulating material, a semiconductor material, or a conductive material. The second material of the sacrificial material layers42can be subsequently replaced with electrically conductive electrodes which can function, for example, as control gate electrodes of a vertical NAND device. Non-limiting examples of the second material include silicon nitride, an amorphous semiconductor material (such as amorphous silicon), and a polycrystalline semiconductor material (such as polysilicon). In one embodiment, the sacrificial material layers42can be spacer material layers that comprise silicon nitride or a semiconductor material including at least one of silicon and germanium.

In one embodiment, the insulating layers32can include silicon oxide, and sacrificial material layers can include silicon nitride. The thicknesses of the insulating layers32and the sacrificial material layers42can be in a range from 20 nm to 50 nm, although lesser and greater thicknesses can be used for each insulating layer32and for each sacrificial material layer42. The number of repetitions of the pairs of an insulating layer32and a sacrificial material layer (e.g., a control gate electrode or a sacrificial material layer)42can be in a range from 2 to 1,024, and typically from 8 to 256, although a greater number of repetitions can also be used. The top and bottom gate electrodes in the stack may function as the select gate electrodes. In one embodiment, each sacrificial material layer42in the alternating stack (32,42) can have a uniform thickness that is substantially invariant within each respective sacrificial material layer42.

While the present disclosure is described using an embodiment in which the spacer material layers are sacrificial material layers42that are subsequently replaced with electrically conductive layers, in other embodiments the sacrificial material layers are formed as electrically conductive layers. In such embodiments, steps for replacing the spacer material layers with electrically conductive layers can be omitted.

Optionally, an insulating cap layer70can be formed over the alternating stack (32,42). The insulating cap layer70includes a dielectric material that is different from the material of the sacrificial material layers42. In one embodiment, the insulating cap layer70can include a dielectric material that can be used for the insulating layers32as described above. The insulating cap layer70can have a greater thickness than each of the insulating layers32. The insulating cap layer70can be deposited, for example, by chemical vapor deposition. In one embodiment, the insulating cap layer70can be a silicon oxide layer.

The first exemplary structure can include at least one memory array region100in which a three-dimensional array of memory elements is to be subsequently formed, at least one staircase region300in which stepped surfaces of the alternating stack (32,42) are to be subsequently formed, and an interconnection region200in which interconnection via structures extending through the levels of the alternating stack (32,42) are to be subsequently formed.

Referring toFIG.2, stepped surfaces are formed in the staircase region300, which is also referred to as a terrace region. As used herein, “stepped surfaces” refer to a set of surfaces that include at least two horizontal surfaces and at least two vertical surfaces such that each horizontal surface is adjoined to a first vertical surface that extends upward from a first edge of the horizontal surface, and is adjoined to a second vertical surface that extends downward from a second edge of the horizontal surface. A stepped cavity is formed within the volume from which portions of the alternating stack (32,42) are removed through formation of the stepped surfaces. A “stepped cavity” refers to a cavity having stepped surfaces.

The terrace region is formed in the staircase region300, which is located between the memory array region100and the interconnection region200containing the at least one semiconductor device for the peripheral circuitry. The stepped cavity can have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity changes in steps as a function of the vertical distance from the top surface of the semiconductor material layer10. In one embodiment, the stepped cavity can be formed by repetitively performing a set of processing steps. The set of processing steps can include, for example, an etch process of a first type that vertically increases the depth of a cavity by one or more levels, and an etch process of a second type that laterally expands the area to be vertically etched in a subsequent etch process of the first type. As used herein, a “level” of a structure including alternating plurality is defined as the relative position of a pair of a first material layer and a second material layer within the structure.

Each sacrificial material layer42other than a topmost sacrificial material layer42within the alternating stack (32,42) laterally extends farther than any overlying sacrificial material layer42within the alternating stack (32,42) in the terrace region. The terrace region includes stepped surfaces of the alternating stack (32,42) that continuously extend from a bottommost layer within the alternating stack (32,42) to a topmost layer within the alternating stack (32,42).

A stepped dielectric material portion65(i.e., an insulating fill material portion) can be formed in the stepped cavity by deposition of a dielectric material therein. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. Excess portions of the deposited dielectric material can be removed from above the top surface of the insulating cap layer70, for example, by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the stepped dielectric material portion65. As used herein, a “stepped” element refers to an element that has stepped surfaces and a horizontal cross-sectional area that increases monotonically as a function of a vertical distance from a top surface of a substrate on which the element is present. If silicon oxide is used for the stepped dielectric material portion65, the silicon oxide of the stepped dielectric material portion65may, or may not, be doped with dopants such as B, P, and/or F. In one embodiment, the stepped dielectric material portion65has a stepwise-increasing lateral extent that increases with a vertical distance from the carrier substrate9.

Optionally, drain select level isolation structures72can be formed through the insulating cap layer70and a subset of the sacrificial material layers42located at drain select levels. The drain select level isolation structures72can be formed, for example, by forming drain select level isolation trenches and filling the drain select level isolation trenches with a dielectric material such as silicon oxide. Excess portions of the dielectric material can be removed from above the top surface of the insulating cap layer70.

Referring toFIGS.3A and3B, a lithographic material stack (not shown) including at least a photoresist layer can be formed over the insulating cap layer70and the stepped dielectric material portion65, and can be lithographically patterned to form openings therein. The openings include a first set of openings formed over the memory array region100and a second set of openings formed over the staircase region300. The pattern in the lithographic material stack can be transferred through the insulating cap layer70or the stepped dielectric material portion65, and through the alternating stack (32,42) by performing an anisotropic etch process that uses the patterned lithographic material stack as an etch mask. Portions of the alternating stack (32,42) underlying the openings in the patterned lithographic material stack are etched to form memory openings49and support openings19. As used herein, a “memory opening” refers to a structure in which memory elements, such as a memory stack structure, is subsequently formed. As used herein, a “support opening” refers to a structure in which a support structure (such as a support pillar structure) that mechanically supports other elements is subsequently formed. The memory openings49are formed through the insulating cap layer70and the entirety of the alternating stack (32,42) in the memory array region100. The support openings19are formed through the stepped dielectric material portion65and the portion of the alternating stack (32,42) that underlie the stepped surfaces in the staircase region300.

The anisotropic etch process can include a series of anisotropic etch steps that sequentially etch the materials of the stepped dielectric material portion65and the alternating stack (32,42), the semiconductor material of the semiconductor material layer14, and the dielectric material of the dielectric spacer layer12. The anisotropic etch process forms memory openings49in the memory array region100, and forms support openings19in the staircase region300.

In one embodiment, the anisotropic etch process may comprise a first anisotropic etch step that etches the materials of the stepped dielectric material portion65and the alternating stack (32,42), a second anisotropic etch step that etches the semiconductor material of the semiconductor material layer14, and a third anisotropic etch step that etches the dielectric material of the dielectric spacer layer12. In one embodiment, the first anisotropic etch process may indiscriminately etch the materials of the stepped dielectric material portion65, the insulating layers32, and the sacrificial material layers42. A terminal portion of the first anisotropic etch process may be selective to the semiconductor material of the semiconductor material layer14.

According to an aspect of the present disclosure, the second anisotropic etch step that etches the semiconductor material of the semiconductor material layer14may have an etch chemistry that etches the semiconductor material with the taper angle. In other words, the second anisotropic etch step forms sloped sidewalls of the memory openings49and the support openings49while etching through the semiconductor material layer14. The taper angle of the sloped sidewalls of the semiconductor material layer14around the memory openings49and the support openings19may be in a range from 3 degrees to 25 degrees, such as from 5 degrees to 15 degrees, although lesser and greater taper angles may also be employed. The taper angles are measures with respect to the vertical direction. Generally, the taper angle of the sloped sidewalls of the semiconductor material layer14around the memory openings49and the support openings19and the thickness of the semiconductor material layer14may be selected such that the diameter or the minor axis of a horizontal cross-sectional shape of each memory opening49in a horizontal plane including an interface between the dielectric spacer layer12and the semiconductor material layer14is not greater than twice the sum of the thickness of a memory film to be formed and the thickness of a vertical semiconductor channel material to be subsequently formed within each memory opening49. For example, the diameter or the minor axis of a horizontal cross-sectional shape of each memory opening49in the horizontal plane including the interface between the dielectric spacer layer12and the semiconductor material layer14may be in a range from 30 nm to 120 nm, such as from 40 nm to 80 nm, although lesser and greater dimensions may also be employed.

The third to anisotropic etch step that extends the memory openings49and the support openings19through the dielectric spacer layer12may have an etch chemistry that etches the dielectric material of the dielectric spacer layer12while forming a vertical or substantially vertical sidewall around each portion of the memory openings49and the support openings19that extends through the dielectric spacer layer12. The patterned lithographic material stack can be subsequently removed, for example, by ashing.

The memory openings49and the support openings19can extend from the top surface of the alternating stack (32,42) to at least the horizontal plane including the topmost surface of the carrier substrate9. In one embodiment, physically exposed to portions of the carrier substrate9may be vertically recessed from the un-recessed top surface of the carrier substrate9by a recess depth. The recess depth can be, for example, in a range from 1 nm to 50 nm, although lesser and greater recess depths can also be used. A two-dimensional array of memory openings49can be formed in the memory array region100. A two-dimensional array of support openings19can be formed in the staircase region300. Optionally, an isotropic wet etch may be conducted to widen the diameter of the support openings19and the memory openings49after the anisotropic etches.

Referring toFIG.4, a memory film50and a semiconductor channel material layer60L can be sequentially deposited in the memory openings49and the support openings19. In one embodiment, the memory film50comprises a stack of layers including a blocking dielectric layer52, a charge storage layer54, a tunneling dielectric layer56.

The blocking dielectric layer52can include a single dielectric material layer or a stack of a plurality of dielectric material layers. In one embodiment, the blocking dielectric layer can include a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. Alternatively or additionally, the blocking dielectric layer52can include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the blocking dielectric layer52can include silicon oxide. The thickness of the blocking dielectric layer52can be in a range from 3 nm to 20 nm, although lesser and greater thicknesses can also be used. Alternatively, the blocking dielectric layer52can be omitted, and a backside blocking dielectric layer can be formed after formation of backside recesses on surfaces of memory films to be subsequently formed.

Subsequently, the charge storage layer54can be formed. In one embodiment, the charge storage layer54can be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material, which can be, for example, silicon nitride. Alternatively, the charge storage layer54can include a continuous layer or patterned discrete portions of a conductive material such as doped polysilicon or a metallic material that is patterned into multiple electrically isolated portions (e.g., floating gates), for example, by being formed within lateral recesses into sacrificial material layers42. In one embodiment, the charge storage layer54includes a silicon nitride layer. In one embodiment, the sacrificial material layers42and the insulating layers32can have vertically coincident sidewalls, and the charge storage layer54can be formed as a single continuous layer. The charge storage layer54can be formed as a single charge storage layer of homogeneous composition, or can include a stack of multiple charge storage layers. The thickness of the charge storage layer54can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be used.

The tunneling dielectric layer56includes a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. The charge tunneling may be performed through hot-carrier injection or by Fowler-Nordheim tunneling induced charge transfer depending on the mode of operation of the monolithic three-dimensional NAND string memory device to be formed. The tunneling dielectric layer56can include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicates, alloys thereof, and/or combinations thereof. In one embodiment, the tunneling dielectric layer56can include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is commonly known as an ONO stack. In one embodiment, the tunneling dielectric layer56can include a silicon oxide layer that is substantially free of carbon or a silicon oxynitride layer that is substantially free of carbon. The thickness of the tunneling dielectric layer56can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be used.

According to an aspect of the present disclosure, the thickness of the memory film50and the lateral dimensions of the memory openings49at the level of the dielectric spacer layer12can be selected such that a vertically-extending continuous cavity is present within each memory opening49between the horizontal plane including the bottom surface of the dielectric spacer layer12and the horizontal plane including the top surface of the dielectric spacer layer12. In other words, each of the memory openings49comprises an empty cylindrical volume at the level of the dielectric spacer layer12.

The semiconductor channel material layer60L includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. The semiconductor material of the semiconductor channel material layer60L may be intrinsic (i.e., not intentionally doped) or may be doped with a doping of a first-conductivity-type, which may be p-type or n-type. The atomic concentration of dopants of the first conductivity in the semiconductor channel material layer60L may be in a range from 1.0×1014/cm3to 1.0×1018/cm3, although lesser and greater atomic concentrations may also be employed. In one embodiment, the semiconductor channel material layer60L includes amorphous silicon or polysilicon. The semiconductor channel material layer60L can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer60L can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be used. A memory cavity49′ is formed in the volume of each memory opening49that is not filled with the deposited material layers (52,54,56,60L).

According to an aspect of the present disclosure, each empty cylindrical volume of the memory openings49located at the level of the dielectric spacer layer12and laterally surrounded by a respective tubular portion of the memory film50is filled with the semiconductor channel material layer60L. Within each memory opening49, an elongated empty volume laterally bounded by an inner sidewall of the semiconductor channel material layer60L is provided. Each such elongated empty volume comprises a tapered bottom region having an inverted conical shape. Tapered surface segments of an inner sidewall of the semiconductor channel material layer60L merge at an apex of the inverted conical shape. According to an aspect of the present disclosure, the apexes of the inverted conical shapes of the tapered bottom regions of the elongated empty volumes within the memory openings49are located above the horizontal plane including the bottom surface of the semiconductor material layer14and below the horizontal plane including the top surface of the semiconductor material layer14.

A dielectric core layer62L can be deposited in the elongated empty volumes within the memory openings49and the support openings19. The dielectric core layer62L includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer62L can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), or by a self-planarizing deposition process such as spin coating.

Referring toFIG.5, the dielectric core layer62L can be recessed selective to the material of the semiconductor channel material layer60L, for example, by a recess etch. The material of the dielectric core layer62L is vertically recessed below the horizontal plane core layer62L constitutes a dielectric core62.

Referring toFIG.6, a semiconductor material having a doping of a second conductivity type can be deposited in the recess regions that overlie the dielectric cores62. The second conductivity type that is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The atomic concentration of dopants of the second conductivity type in the deposited semiconductor material can be in a range from 5.0×1018/cm3to 2.0×1021/cm3, although lesser and greater atomic concentrations can also be used. The doped semiconductor material can be, for example, doped poly silicon.

Portions of the deposited semiconductor material, the semiconductor channel material layer60L, and the memory film50that are located above the horizontal plane including the top surface of the insulating cap layer70can be removed by a planarization process. For example, a chemical mechanical polishing (CMP) process or a recess etch process may be employed to remove material portions that overlie the horizontal plane including the top surface of the insulating cap layer70. Each remaining portion of the doped semiconductor material having a doping of the second conductivity type constitutes a drain region63. Each remaining portion of the semiconductor channel material layer60L that remains in a respective memory opening49or in a respective support opening19constitutes a vertical semiconductor channel60. The memory film50is divided into a plurality of memory films50located within a respective one of the memory openings49and the support openings19.

Electrical current can flow through each vertical semiconductor channel60when a vertical NAND device including the vertical semiconductor channel60is turned on. Within each memory opening49, a tunneling dielectric layer56is surrounded by a charge storage layer54, and laterally surrounds a vertical semiconductor channel60. Each adjoining set of a blocking dielectric layer52, a charge storage layer54, and a tunneling dielectric layer56collectively constitute a memory film50, which can store electrical charges with a macroscopic retention time. In some embodiments, a blocking dielectric layer52may not be present in the memory film50at this step, and a blocking dielectric layer may be subsequently formed after formation of backside recesses. As used herein, a macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device such as a retention time in excess of 24 hours. Each combination of a memory film50and a vertical semiconductor channel60constitutes a memory stack structure55.

Each memory stack structure55is a combination of a semiconductor channel, a tunneling dielectric layer, a plurality of memory elements comprising portions of the charge storage layer54, and an optional blocking dielectric layer52. Each combination of a memory stack structure55, a dielectric core62, and a drain region63within a memory opening49is herein referred to as a memory opening fill structure58. Each combination of a memory film50, a vertical semiconductor channel60, a dielectric core62, and a drain region63within each support opening19constitutes a support pillar structure20.

An instance of a memory opening fill structure58can be formed within each memory opening49. An instance of the support pillar structure20can be formed within each support opening19. The support pillar structures20are formed through a region of the alternating stack (32,42) that underlie the stepped surfaces and a region of the stepped dielectric material portion65that overlie the stepped surfaces. Each of the support pillar structures20comprises a semiconductor material portion (i.e., a vertical semiconductor channel60of the support pillar structure20) having a same composition as the vertical semiconductor channels60of the memory opening fill structures58, and a dielectric layer stack (i.e., a memory film50of a support pillar structure20) containing a same set of dielectric material layers as each of the memory films50of the memory opening fill structures58. While the present disclosure is described using the illustrated configuration for the memory stack structure, the methods of the present disclosure can be applied to alternative memory stack structures including different layer stacks or structures for the memory film50and/or for the vertical semiconductor channel60.

Generally, memory opening fill structures58are formed in the memory openings49. Each of the memory stack structures58comprises a respective memory film50and a respective vertical semiconductor channel60. According to an aspect of the present disclosure, each vertical semiconductor channel60includes a solid semiconductor (e.g., silicon) pillar portion60P that vertically extends through the dielectric spacer layer12and has no hollow space inside. In one embodiment, each of the memory opening fill structures58comprises a respective dielectric core62that is laterally surrounded by the respective vertical semiconductor channel60. The dielectric core62does not extend inside the pillar portion60P, and the pillar portion60P does not surround the dielectric core62. Each vertical semiconductor channel60also includes a hollow portion60H which surrounds the dielectric core62.

In one embodiment, each of the memory openings49has a tapered-segment-containing vertical cross-sectional profile such that each of the memory openings49has a lesser lateral dimension at an interface between the semiconductor material layer14and the dielectric spacer layer12than at an interface between the semiconductor material layer14and the alternating stack (32,42). As used herein, a “tapered-segment-containing vertical cross-sectional profile” refers to a vertical cross-sectional profile that includes at least one tapered segment within the vertical cross-sectional profile. In the exemplary structure, a vertical cross-sectional profile of a memory opening49has a tapered sidewall of the semiconductor material14as a tapered segment of the vertical cross-sectional profile.

In one embodiment, each of the dielectric cores62has a respective conical portion embedded within the semiconductor material layer14. The conical portion may be located between the horizontal plane including the interface between the semiconductor material layer14and the dielectric spacer layer12and the horizontal plane including the interface between the semiconductor material layer14and the alternating stack (32,42). In one embodiment, the respective conical portion has a respective apex that is more proximal to the vertical plane including the topmost surface of the alternating stack (32,42) than the dielectric spacer layer12is to the vertical plane including the topmost surface of the alternating stack (32,42).

In one embodiment, each of the memory openings49has a sidewall including a sidewall segment of the semiconductor material layer14and a sidewall segment of the dielectric spacer layer12. In one embodiment, the sidewall segment of the semiconductor material layer14has a greater taper angle relative to a vertical direction than the sidewall segment of the dielectric spacer layer12has a taper angle relative to the vertical direction. In one embodiment, the taper angle of the sidewall segment of the semiconductor material layer14may be in a range from 3 degrees to 25 degrees, such as from 5 degrees to 15 degrees. The taper angle of the sidewall segment of the dielectric spacer layer12may be in a range from 0 degrees to 5 degrees, such as from 0.2 degree to 3 degrees, and is less than the taper angle of the sidewall segment of the semiconductor material layer14by at least 3 degrees, such as at least 5 degrees.

Referring toFIGS.7A and7B, a contact level dielectric layer73can be formed over the alternating stack (32,42) of insulating layer32and sacrificial material layers42, and over the memory stack structures55and the support pillar structures20. The contact level dielectric layer73includes a dielectric material that is different from the dielectric material of the sacrificial material layers42. For example, the contact level dielectric layer73can include silicon oxide. The contact level dielectric layer73can have a thickness in a range from 50 nm to 500 nm, although lesser and greater thicknesses can also be used.

A photoresist layer (not shown) can be applied over the contact level dielectric layer73, and is lithographically patterned to form openings in areas between clusters of memory stack structures55. The pattern in the photoresist layer can be transferred through the contact level dielectric layer73, the alternating stack (32,42) and the stepped dielectric material portion65, the semiconductor material layer14, and the dielectric spacer layer12, and into an upper portion of the carrier substrate9by performing an anisotropic etch process. The anisotropic etch process forms backside trenches79, which vertically extend from the top surface of the contact level dielectric layer73at least to the top surface of the carrier substrate9, and laterally extend through the memory array region100and the staircase region300.

In one embodiment, the backside trenches79can laterally extend along a first horizontal direction hd1 and can be laterally spaced apart one from another along a second horizontal direction hd2 that is perpendicular to the first horizontal direction hd1. The memory stack structures55can be arranged in rows that extend along the first horizontal direction hd1. The drain select level isolation structures72can laterally extend along the first horizontal direction hd1. Each backside trench79can have a uniform width that is invariant along the lengthwise direction (i.e., along the first horizontal direction hd1). Each drain select level isolation structure72can have a uniform vertical cross-sectional profile along vertical planes that are perpendicular to the first horizontal direction hd1 that is invariant with translation along the first horizontal direction hd1. Multiple rows of memory stack structures55can be located between a neighboring pair of a backside trench79and a drain select level isolation structure72, or between a neighboring pair of drain select level isolation structures72. In one embodiment, the backside trenches79can include a source contact opening in which a source contact via structure can be subsequently formed. The photoresist layer can be removed, for example, by ashing.

Referring toFIG.8, an etchant that selectively etches the second material of the sacrificial material layers42with respect to the first material of the insulating layers32can be introduced into the backside trenches79, for example, using an etch process. Backside recesses43are formed in volumes from which the sacrificial material layers42are removed. The removal of the second material of the sacrificial material layers42can be selective to the first material of the insulating layers32, the material of the stepped dielectric material portion65, the semiconductor material of the semiconductor material layer14, the material of the dielectric spacer layer12, and the material of the outermost layer of the memory films50. In one embodiment, the sacrificial material layers42can include silicon nitride, and the materials of the insulating layers32and the stepped dielectric material portion65can be selected from silicon oxide and dielectric metal oxides.

The etch process that removes the second material selective to the first material and the outermost layer of the memory films50can be a wet etch process using a wet etch solution, or can be a gas phase (dry) etch process in which the etchant is introduced in a vapor phase into the backside trenches79. For example, if the sacrificial material layers42include silicon nitride, the etch process can be a wet etch process in which the first exemplary structure is immersed within a wet etch tank including phosphoric acid, which etches silicon nitride selective to silicon oxide, silicon, and various other materials used in the art. The support pillar structure20, the stepped dielectric material portion65, and the memory stack structures55provide structural support while the backside recesses43are present within volumes previously occupied by the sacrificial material layers42.

Each backside recess43can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each backside recess43can be greater than the height of the backside recess43. A plurality of backside recesses43can be formed in the volumes from which the second material of the sacrificial material layers42is removed. The memory openings in which the memory stack structures55are formed are herein referred to as front side openings or front side cavities in contrast with the backside recesses43. In one embodiment, the memory array region100comprises an array of monolithic three-dimensional NAND strings having a plurality of device levels disposed above the substrate semiconductor material layer14. In this case, each backside recess43can define a space for receiving a respective word line of the array of monolithic three-dimensional NAND strings.

Each of the plurality of backside recesses43can extend substantially parallel to the top surface of the substrate semiconductor material layer14. A backside recess43can be vertically bounded by a top surface of an underlying insulating layer32and a bottom surface of an overlying insulating layer32. In one embodiment, each backside recess43can have a uniform height throughout

Referring toFIG.9, a backside blocking dielectric layer (not shown) can be optionally formed by a conformal deposition process on physically exposed surfaces around the backside recesses43and at peripheral regions of the backside trenches79. The backside blocking dielectric layer comprises a dielectric material such as a dielectric metal oxide. The thickness of the backside blocking dielectric layer (not shown) can be in a range from 1 nm to 15 nm, such as 2 to 6 nm, although lesser and greater thicknesses can also be used.

At least one metallic material is deposited in the plurality of backside recesses43, on the sidewalls of the at least one the backside trench79, and over the top surface of the contact level dielectric layer73. The at least one metallic material can include a conductive metal nitride material (such as TiN, TaN, or WN) and a metallic fill material (such as W, Co, Ru, Ti, and/or Ta). Each metallic material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof.

A plurality of electrically conductive layers46can be formed in the plurality of backside recesses43, and a continuous metallic material layer (not shown) can be formed on the sidewalls of each backside trench79and over the contact level dielectric layer73. Each electrically conductive layer46includes a portion of the metallic barrier liner and a portion of the metallic fill material layer that are located between a vertically neighboring pair of dielectric material layers such as a pair of insulating layers32. The continuous metallic material layer (not shown) includes a continuous portion of the metallic barrier liner and a continuous portion of the metallic fill material layer that are located in the backside trenches79or above the contact level dielectric layer73. Each sacrificial material layer42can be replaced with an electrically conductive layer46. A backside cavity is present in the portion of each backside trench79that is not filled with the optional backside blocking dielectric layer and the continuous metallic material layer.

The deposited metallic material of the continuous electrically conductive material layer is etched back from the sidewalls of each backside trench79and from above the contact level dielectric layer73, for example, by an isotropic wet etch, an anisotropic dry etch, or a combination thereof. Each remaining portion of the deposited metallic material in the backside recesses43constitutes an electrically conductive layer46. Each electrically conductive layer46can be a conductive line structure. Thus, the sacrificial material layers42are replaced with the electrically conductive layers46.

Each electrically conductive layer46can function as a combination of a plurality of control gate electrodes located at a same level and a word line electrically interconnecting, i.e., electrically connecting, the plurality of control gate electrodes located at the same level. The plurality of control gate electrodes within each electrically conductive layer46are the control gate electrodes for the vertical memory devices including the memory stack structures55. In other words, each electrically conductive layer46can be a word line that functions as a common control gate electrode for the plurality of vertical memory devices. The word lines comprise a metallic (e.g., metal or metal alloy) material. One or more topmost electrically conductive layers46may comprise drain side select gate electrodes of the NAND strings. The semiconductor material layer14may comprise the bottommost source side select gate electrode of the NAND strings. Optionally, one or more bottommost electrically conductive layers46may comprise additional source side select gate electrodes of the NAND strings.

Referring toFIG.10, an insulating material such as silicon oxide can be conformally deposited at peripheral regions of the backside trenches79. An optional conductive fill material, such as a metallic material, can be deposited in remaining volumes of the backside trenches79by a conformal deposition process. Portions of the insulating material and the conductive fill material that are deposited outside the backside trenches79can be removed by a planarization process, which may employ a chemical mechanical polishing process and/or a recess etch process. Each remaining portion of the insulating material that remains in the backside trenches79constitute a backside insulating spacer74. Each remaining portion of the conductive fill material that remains in the backside trenches79constitutes a backside trench via structure76.

Referring toFIGS.11A and11B, contact via structures (88,86,84) can be formed through the contact level dielectric layer73, and optionally through the stepped dielectric material portion65. For example, drain contact via structures88can be formed through the contact level dielectric layer73on each drain region63. Word line contact via structures86can be formed on the electrically conductive layers46through the contact level dielectric layer73, and through the stepped dielectric material portion65. Pass-through via structures84can be formed through the stepped dielectric material portion65and on the semiconductor material layer14.

Referring toFIG.12, a first line level dielectric layer90is deposited over the via level dielectric layer80. Various metal line structures (98,96,94) are formed in the first line level dielectric layer90. The metal line structures (98,96,94) are herein referred to as first line level metal interconnect structures. The various metal line structure (98,96,94) include bit lines98that are electrically connected to a respective plurality of the drain contact via structures88, word-line-connection metal interconnect lines96that are electrically connected to a respective one of the word line contact via structures86, and peripheral metal interconnect lines94that are electrically connected to a respective one of the pass-through via structures84. The bit lines98are electrically connected to upper ends of a respective subset of the vertical semiconductor channels60in the memory stack structures55in the memory array region100via a respective subset of the drain regions63. The drain regions63are located at end portions of the vertical semiconductor channels60that are distal from the semiconductor material layer14and the dielectric spacer layer12. In one embodiment, the memory stack structures55are arranged in rows that extend along the first horizontal direction (e.g., word line direction) hd1, and the bit lines98laterally extend along the second horizontal direction (e.g., bit line direction) hd2.

A first semiconductor die (e.g., memory die)1000is provided by performing additional processing steps on the exemplary structure. Specifically, additional metal interconnect structures168included in additional interconnect level dielectric layers160are formed. In an illustrative example, the additional interconnect level dielectric layers160can include a via level dielectric layer, a second line level dielectric layer, a second via level dielectric layer, and a metallic pad structure level dielectric layer140. The metal interconnect structures168can include first metal via structures included in the first via level dielectric layer, second metal line structures included within the second line level dielectric layer, second metal via structures included in the second via level dielectric layer, and first bonding structures178(such as metallic pad structures) included in the metallic pad structure level dielectric layer140. While the present disclosure is described using an example in which the additional interconnect level dielectric layers160include the first via level dielectric layer, the second line level dielectric layer, the second via level dielectric layer, and the metallic pad structure level dielectric layer, embodiments are expressly contemplated herein in which the additional interconnect level dielectric layers160include a different number and/or different combinations of dielectric material layers. The first semiconductor die1000may be a memory die that includes a three-dimensional array of memory elements. Electrical connection paths can be provided by each combination of a first bonding structure178and a respective set of metal interconnect structures.

Referring toFIG.13, a second semiconductor die700can be provided, which can be a logic die including various semiconductor devices710. In one embodiment, the second semiconductor die700comprises a peripheral (e.g., driver) circuitry containing peripheral devices configured to control operation of the three-dimensional array of memory elements in the first semiconductor die1000. The peripheral circuitry can include a word line driver that drives the electrically conductive layers (e.g., word lines)46within the first semiconductor die1000, a bit line driver that drives the bit lines98in the first semiconductor die1000, a word line decoder circuitry that decodes the addresses for the electrically conductive layers46, a bit line decoder circuitry that decodes the addresses for the bit lines98, a sense amplifier circuitry that senses the states of memory elements within the memory stack structures55in the first semiconductor die1000, a power supply/distribution circuitry that provides power to the first semiconductor die1000, a data buffer and/or latch, and/or any other semiconductor circuitry that can be used to operate the array of memory stack structures58in the first semiconductor die1000.

The second semiconductor die700can include a logic-die substrate708, which can be a semiconductor substrate. The logic-die substrate can include a substrate semiconductor layer709. The substrate semiconductor layer709may be a semiconductor wafer or a semiconductor material layer, and can include at least one elemental semiconductor material (e.g., single crystal silicon wafer or layer), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, combinations of a through-substrate insulating liner711and a through-substrate connection via structure712may be formed in an upper portion of the substrate semiconductor layer709.

Shallow trench isolation structures720can be formed in an upper portion of the substrate semiconductor layer709to provide electrical isolation for semiconductor devices of the sense amplifier circuitry. The various semiconductor devices710can include field effect transistors, which include respective transistor active regions742(i.e., source regions and drain regions), a channel746, and a gate structure750. The field effect transistors may be arranged in a CMOS configuration. Each gate structure750can include, for example, a gate dielectric752, a gate electrode754, a dielectric gate spacer756and a gate cap dielectric758. For example, the semiconductor devices710can include word line drivers for electrically biasing word lines of the first semiconductor die1000comprising the electrically conductive layers46.

Dielectric material layers are formed over the semiconductor devices710, which are herein referred to as logic-side dielectric layers760. Optionally, a dielectric liner762(such as a silicon nitride liner) can be formed to apply mechanical stress to the various field effect transistors and/or to prevent diffusion of hydrogen or impurities from the logic-side dielectric layers760into the semiconductor devices710. Logic-side metal interconnect structures780are included within the logic-side dielectric layers760. The logic-side metal interconnect structures780can include various device contact via structures782(e.g., source and drain electrodes which contact the respective source and drain nodes of the device or gate electrode contacts), interconnect-level metal line structures784, interconnect-level metal via structures786, and second bonding structures788(such as metallic pad structures) that may be configured to function as bonding pads. Generally, the second semiconductor die700comprises second bonding structures788that overlie, and are electrically connected to, the semiconductor devices710.

Referring toFIGS.14A and14B, the first semiconductor die1000and the second semiconductor die700are positioned such that the second bonding structures788of the second semiconductor die700face the first bonding structures178of the first semiconductor die1000. In one embodiment, the first semiconductor die1000and the second semiconductor die700can be designed such that the pattern of the second bonding structures788of the second semiconductor die700is the mirror pattern of the pattern of the first bonding structures178of the first semiconductor die1000. The first semiconductor die1000and the second semiconductor die700can be bonded to each other by metal-to-metal bonding. Alternatively, an array of solder material portions may be used to bond the first semiconductor die1000and the second semiconductor die700through the array of solder material portions (such as solder balls).

In the case of metal-to-metal bonding, facing pairs of a first bonding structure178of the first semiconductor die1000and a second bonding structure788of the second semiconductor die700can brought to direct contact with each other, and can be subjected to an elevated temperature to induce material diffusion across the interfaces between adjoined pairs of metallic pad structures (178,788). The interdiffusion of the metallic material can induce bonding between each adjoined pairs of metallic pad structures (178,788). In addition, the logic-side dielectric layers760and the interconnect level dielectric layers160can include a dielectric material (such as a silicate glass material) that can be bonded to each other. In this case, physically exposed surfaces of the logic-side dielectric layers760and the interconnect level dielectric layers160can be brought to direct contact with each other and can be subjected to thermal annealing to provide additional bonding.

In case an array of solder material portions is used to provide bonding between the first semiconductor die1000and the second semiconductor die700, a solder material portion (such as a solder ball) can be applied to each of the first bonding structures178of the first semiconductor die1000, and/or to each of the second bonding structures788of the second semiconductor die700. The first semiconductor die1000and the second semiconductor die700can be bonded to each other through an array of solder material portions by reflowing the solder material portions while each solder material portion is contacted by a respective pair of a first bonding structure178of the first semiconductor die1000and a second bonding structure788of the second semiconductor die700.

Generally, a second semiconductor die700can be bonded to a first semiconductor die1000. The first semiconductor die1000comprises an array of memory stack structures55, and the logic die1000comprises a complementary metal oxide semiconductor (CMOS) circuit that includes a peripheral circuitry electrically coupled to nodes of the array of memory stack structures55through a subset of metal interconnect structures168included within the first semiconductor die1000. The first semiconductor die1000includes the semiconductor material layer14, and is attached to the carrier substrate9.

Optionally, the substrate semiconductor layer (e.g., the silicon wafer)709of the second semiconductor die700can be thinned from the backside. For example, a combination of grinding, polishing, and/or chemical etching may be employed to remove portions of the substrate semiconductor layer709that are distal from the interface between the first semiconductor die1000and the second semiconductor die700. Surfaces of the through-substrate contact via structures712can be physically exposed after thinning the substrate semiconductor layer709. A backside insulating layer714can be formed on the backside surface of the logic die substrate708(as thinned after the thinning process). Laterally-insulated through-substrate via structures (711,712) can vertically extend through the logic die substrate708to provide electrical contact to various input nodes and output nodes of the periphery circuitry in the second semiconductor die700. Each laterally-insulated through-substrate via structure (711,712) includes a through-substrate connection via structure712and a through-substrate insulating liner711that laterally surrounds the through-substrate conductive via structure712. Logic-side bonding pads716(which is also referred to as front bonding pads) can be formed on surface portions of the laterally-insulated through-substrate via structures (711,712). Generally, a semiconductor die is provided, which includes semiconductor devices710located on a semiconductor substrate (such as the substrate semiconductor layer709). The second bonding structures788overlie, and are electrically connected to, the semiconductor devices710, and laterally-insulated through-substrate via structures (711,712) can extend through the logic-side substrate708. Alternatively, the substrate semiconductor layer (e.g., the silicon wafer)709of the second semiconductor die700may be retained in the device and the logic-side bonding pads716and the laterally-insulated through-substrate via structures (711,712) are omitted.

The first exemplary bonded assembly of the first semiconductor die1000and the second semiconductor die700may comprise a first exemplary bonded assembly of a memory die and a logic die. Within the first exemplary bonded assembly, the semiconductor material layer14is located on a distal surface32D of the alternating stack of the insulating layers32and the electrically conductive layers46, as shown inFIG.14B. As used herein, a distal surface of an element within a first exemplary bonded assembly of two semiconductor dies refers to a surface of the element that is distal from the interface between the two semiconductor dies such as the interface between the first semiconductor die1000and the second semiconductor die700. The semiconductor material layer14is more distal from the second semiconductor die700(i.e., the logic die) than the alternating stack (32,46) is from the second semiconductor die700. The dielectric spacer layer12located on a distal surface14D of the semiconductor material layer14. The carrier substrate9is located on a distal surface12D of the dielectric spacer layer12. Memory openings49(filled with the memory opening fill structures58) vertically extend through the alternating stack (32,46), through the semiconductor material layer14, and through the dielectric spacer layer12, and may extend into a proximal portion of the carrier substrate9. Memory opening fill structures58are located in the memory openings49, and comprise a respective vertical semiconductor channel60and a respective memory film50.

Referring toFIG.15, the carrier substrate9may be removed while retaining the dielectric spacer layer12, the memory opening fill structures58, and the backside insulating spacers74. For example, if the carrier substrate9comprises a semiconductor substrate (such as a commercially available silicon wafer), a grinding process may be performed to remove a predominant portion of the carrier substrate9from the backside, a polishing process may be performed to remove a proximal portion of the carrier substrate9that is proximal to the interface between the first semiconductor die1000and the second semiconductor die700, and an isotropic wet etch process employing an etchant that etches the semiconductor material of the carrier substrate9selective to the dielectric material of the dielectric spacer layer12to remove remaining portions of the semiconductor material of the carrier substrate9. In an illustrative example, the wet etch process may employ KOH as an etchant. Portions of the memory opening fill structures58may protrude from the exposed distal surface12D of the dielectric spacer layer12.

Referring toFIG.16, an optional planarization dielectric layer11may be formed on the physically exposed distal surface12D of the dielectric spacer layer12. The dielectric layer11comprises a self-planarizing dielectric material such as a flowable oxide (FOX) (e.g., spin-on-glass), spin-on-carbon or photoresist. Alternatively, a non-self planarizing material, such as a silicon oxide deposited from an organic source (e.g., TEOS) by CVD (e.g., low pressure CVD, atmospheric pressure CVD or plasma enhanced CVD) may be used. Thus, the physically exposed top surface of the dielectric layer11may be planar. The thickness of the dielectric layer11may be in a range from 50 nm to 300 nm, although lesser and greater thicknesses may also be employed.

Referring toFIG.17, a non-selective planarization process may be performed to remove material portions that overlie the horizontal plane including the distal surface12D of the dielectric spacer layer12. The non-selective planarization process may employ a chemical mechanical polishing process, or a non-selective recess etch process that indiscriminately etches materials of the dielectric layer11, the protruding portions of the memory opening fill structures58(e.g., the memory films50and the vertical semiconductor channels60), the backside insulating spacers74, and the backside trench via structures76. The dielectric layer11may be entirely removed. Portions of the memory films50, the vertical semiconductor channels60, the backside insulating spacers74, and the backside trench via structures76that overlie the horizontal plane including the distal surface12D of the dielectric spacer layer12can be removed in by the non-selective planarization process. A distal end surface of each of the vertical semiconductor channels60can be physically exposed. Specifically, the solid semiconductor (e.g., silicon) pillar portion60P of the vertical semiconductor channels60is exposed in the distal surface12D of the dielectric spacer layer12.

Referring toFIG.18, a photoresist layer (not shown) can be applied over the dielectric spacer layer12, and can be lithographically patterned to form openings in areas that overlie the pass-through via structures84. An etch process, such as an anisotropic etch process, can be performed to etch through unmasked portions of the dielectric spacer layer12and the semiconductor material layer14. A contact recess region103vertically extending through the dielectric spacer layer12and the semiconductor material layer14can be formed over each pass-through via structure84. A and a surface of the at least one pass-through via structure84can be physically exposed at the bottom of each contact recess region103. The photoresists layer can be subsequently removed, for example, by ashing.

Referring toFIG.19A, portions of the vertical semiconductor channels60and the memory films50that are embedded within the dielectric spacer layer12may be removed. For example, a recess etch process may be performed.

A sequence of isotropic recess etch processes may be performed to remove portions of the memory films50that are located around the pillar cavities107. In other words, distal portions of the memory films50, which are more distal from the second semiconductor die700than the recessed end surfaces of the pillar portions60P of the vertical semiconductor channels60are from the second semiconductor die700, are removed by the sequence of isotropic etch processes. The sequence of isotropic etch processes may comprise a first isotropic etch process that etches the material of the tunneling dielectric layers56, a second isotropic etch process that etches the material of the charge storage layers54, and the third isotropic etch process that etches the material of the blocking dielectric layers52. A cylindrical surface segment of the dielectric spacer layer12can be physically exposed around each pillar cavity107.

The semiconductor recess etch process may have an etch chemistry that etches the semiconductor material of the vertical semiconductor channels60selective to the material of the dielectric spacer layer12. The semiconductor recess etch process may comprise an isotropic etch process such as a wet etch process, or may comprise an anisotropic etch process. For example, the semiconductor recess etch process may comprise a wet etch process using hot trimethyl-2 hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH). End surfaces of the pillar portions60P of the vertical semiconductor channels60can be vertically recessed by the recess etch process. The recessed end surfaces of the pillar portions60P of the vertical semiconductor channels60can be formed between the horizontal plane including the distal surface12D of the dielectric spacer layer12and the horizontal plane including the proximal surface of the dielectric spacer layer12which contacts a distal surface14D of the semiconductor material layer14. Pillar cavities107can be formed in each volume from which the material of the pillar portions60P of the vertical semiconductor channels60are removed. The surfaces of the solid semiconductor pillar portion60P is exposed in the via cavities107.

In an alternative embodiment shown inFIG.19B, the semiconductor recess etch process is extended such that the recessed end surfaces of the pillar portions60P of the vertical semiconductor channels60can be formed between the horizontal plane including the distal surface14D of the semiconductor material layer14and the horizontal plane including the opposing proximal surface14P of the semiconductor material layer14. In this alternative embodiment, each pillar cavity107extends into the semiconductor material layer14.

Referring toFIG.20, at least one electrically conductive material layer can be deposited in the pillar cavities107, in the contact recess regions103, and over the distal surface12D of the dielectric spacer layer12. The at least one conductive material layer may comprise at least one metallic material layer (121L,123L). In one embodiment, the at least one metallic material layer (121L,123L) may comprise a metallic diffusion barrier liner121L and a metallic fill material layer123L. The metallic diffusion barrier liner121L may comprise a metallic diffusion barrier material such as WN, TiN, TaN, MoN, TiC, TaC, WC, or a combination thereof. The thickness of a horizontally-extending portion of the metallic diffusion barrier liner121L may be in a range from 1 nm to 10 nm, although lesser and greater thicknesses may also be employed. The metallic diffusion barrier liner121L may be deposited by a conformal deposition process or a non-conformal deposition process. The metallic fill material layer123L comprises at least one high-conductivity metal such as W, Ti, Ta, Mo, Ru, Co, Nb, Cu, Al, etc. The metallic fill material layer123L may be deposited by physical vapor deposition, chemical vapor deposition, electroplating, electroless plating, etc. In one embodiment, voids129that are not filled with any of the at least one metallic material layer (121L,123L) may be present within volumes of the pillar cavities107. In this case, each void129may be encapsulated by a portion of the metallic diffusion barrier liner121L, and may be located entirely between a horizontal plane including the distal surface12of the dielectric spacer layer12and a horizontal plane including end surfaces of the pillar portions60P of the vertical semiconductor channels60. The at least one metallic material layer (121L,123L) can contact each end surface of the pillar portions60P of the vertical semiconductor channels60and each end surface of the pass-through via structures84. Alternatively, a heavily doped semiconductor material, such as heavily doped polysilicon may be used instead of or in addition to the at least one metallic material layer (121L,123L).

Referring toFIG.21, a photoresist layer (not shown) may be applied over the top surface of the at least one metallic material layer (121L,123L), and may be lithographically patterned to form discrete areas. An etch process, such as an anisotropic etch process, can be performed to transfer the pattern in the photoresist layer through the at least one metallic material layer (121L,123L), the dielectric spacer layer12, and the semiconductor material layer14. The at least one metallic material layer (121L,123L), the dielectric spacer layer12, and the semiconductor material layer14can be divided into multiple discrete portions that are laterally spaced apart among one another by backside isolation trenches139.

Patterned portions of the at least one metallic material layer (121L,123L) comprise a source layer122that contacts end surfaces of the pillar portions60P of the vertical semiconductor channels60. Alternatively, the source layer112may comprise a heavily doped semiconductor material, such as heavily doped polysilicon, instead of or in addition to the at least one metallic material layer (121L,123L). Generally, the source layer122comprises at least one electrically conductive material that is in direct contact with the distal surface12D of the dielectric spacer layer12and in direct contact with distal end surfaces of the solid semiconductor pillar portions60P of the vertical semiconductor channels60. The source layer122may comprise a source metallic barrier liner122A that is a patterned portion of the metallic diffusion barrier liner121L, and a source metal layer122B that is a patterned portion of the metallic fill material layer123L.

Thus, by forming the tapered memory opening49at the step ofFIGS.3A and3B, permits the solid semiconductor pillar portions60P of the vertical semiconductor channels60to be formed. The source layer122physically contacts the solid semiconductor pillar portions60P, which provides a good electrical contact. If the solid semiconductor pillar portions60P were omitted, then the source layer122would have to contact only the cylindrical edge and/or inner surface of the vertical semiconductor channel60which surrounds the dielectric core62, which degrades the quality of the electrical contact between the source and the channel. The embodiments of the present disclosure provide an improved electrical contact between vertical semiconductor channels60and the source layer122by ensuring at least a minimum contact area between them.

Further, patterned portions of the at least one metallic material layer (121L,123L) comprise a metallic contact plate124that contacts end surfaces of a respective one of the pass-through via structures84. The metallic contact plate124may comprise a contact metallic barrier liner124A that is a patterned portion of the metallic diffusion barrier liner121L, and a contact metal layer124B that is a patterned portion of the metallic fill material layer123L. Optionally, patterned portions of the at least one metallic material layer (121L,123L) may comprise dummy metallic plates126that contact end surfaces of a respective one of the support pillar structures20. The dummy metal plates126may comprise a dummy metallic barrier liner126A that is a patterned portion of the metallic diffusion barrier liner121L, and a dummy metal layer126B that is a patterned portion of the metallic fill material layer123L. The dummy metal plates126may be laterally spaced from each other to minimize the effect of leakage currents. The dummy metal plates126are electrically inactive components which are not connected to an external voltage source, and are electrically floating.

In one embodiment, the dielectric spacer layer12is more distal from the second semiconductor die700than any portion of the dielectric cores62of the memory opening fill structures58is from the second semiconductor die700, i.e., more distal from the second semiconductor die700than the most distal portions of the dielectric cores62of the memory opening fill structures58. In one embodiment, each of the dielectric cores62has a respective conical portion embedded within the semiconductor material layer14, and the respective conical portion has a respective apex that is more proximal to the second semiconductor die700than the dielectric spacer layer12is to the second semiconductor die700. In other words, tips of the conical portions of the dielectric cores62are located between the horizontal plane including the distal surface14D of the semiconductor material layer14and the horizontal plane including the proximal surface of the semiconductor material layer14that contacts the alternating stack (32,46).

In one embodiment, each of the memory openings49has a sidewall including a sidewall segment of the semiconductor material layer14and a sidewall segment of the dielectric spacer layer12. The sidewall segment of the semiconductor material layer14has a greater taper angle relative to a vertical direction than the sidewall segment of the dielectric spacer layer12. Each of the memory opening fill structures58can have a tapered-segment-containing vertical cross-sectional profile such that each of the memory opening fill structures58has a lesser lateral dimension within a horizontal plane including an interface between the semiconductor material layer14and the dielectric spacer layer12than within a horizontal plane including an interface between the semiconductor material layer14and the alternating stack (32,46).

In one embodiment, each of the vertical semiconductor channels60comprises a pillar portion60P having a respective end surface located between a horizontal plane including the distal surface14D of the semiconductor material layer14and a horizontal plane including the distal surface12D of the dielectric spacer layer12. In one embodiment, the source layer122comprises vertically-protruding source portions122P vertically extending into the pillar cavities107in the dielectric spacer layer12and having contact surfaces contacting the end surfaces of the pillar portions60P of the vertical semiconductor channels60. In one embodiment, each of the contact surfaces of the vertically-protruding source portions122P has a respective periphery that coincides with a periphery of a respective one of the end surfaces of the pillar portions60P of the vertical semiconductor channels60, and contacting a cylindrical surface of a respective pillar cavity107through the dielectric material layer12. In one embodiment, each of the vertically-protruding source portions122P comprises a respective cylindrical sidewall having a proximal periphery (i.e., a periphery that is proximal to the interface between the first semiconductor die1000and the second semiconductor die700) that coincides with a distal periphery of a sidewall of a respective one of the pillar portions60P of the vertical semiconductor channels60.

In one embodiment, the alternating stack (32,46) comprises a staircase region in which lateral extents of the alternating stack (32,46) decrease with a vertical distance from the dielectric spacer layer12and in which stepped surfaces of the alternating stack (32,46) are present. The memory die1000comprises a stepped dielectric material portion65contacting the stepped surfaces. In one embodiment, the memory die comprises support pillar structures20that vertically extend through the stepped dielectric material portion65, a respective portion of the alternating stack (32,46), and the semiconductor material layer14, and at least partly through the dielectric spacer layer12.

Referring toFIG.22A, backside dielectric material layers (132,134,136) can be formed over the source layer122and the metallic contact plates124. The backside dielectric material layers (132,134,136) may comprise, for example, a backside dielectric fill material layer132including a dielectric fill material, such as a silicon oxide, a backside dielectric passivation layer134that comprises a diffusion blocking dielectric material, such as a silicon nitride or silicon carbide nitride, and a polymer material layer136that includes a photosensitive polymer material such as polyimide. The polymer material layer136may be patterned with the discrete openings, for example, by lithographic exposure and development, and an etch process such as an anisotropic etch process can be performed to transfer the pattern of the openings in the polymer material layer136through the backside dielectric passivation layer134and the backside dielectric fill material layer132.

At least one metallic material including on under bump metallurgy (UBM) material stack may be deposited in the openings through the backside dielectric material layers (132,134,136) directly on physically exposed surfaces of the source layer122and the metallic contact plates124. The at least one metallic material can be subsequently patterned to form bonding pads (142,144), which may comprise at least one source-side a bonding pad142and contact-connection bonding pads144.

Generally, at least one backside dielectric material layer (132,134,136) can be formed in on the source layer122, and a bonding pad (such as a source-side bonding pad142) vertically extends through the at least one backside dielectric material layer (132,134,136) and contacts the source layer122. A pass-through via structure84may vertically extend through the stepped dielectric material portion65to the peripheral devices710of the logic die700, and an additional bonding pad vertically extending through the at least one backside dielectric material layer (132,134,136) and electrically connected to the pass-through via structure84.

Referring toFIG.22B, in a modified first configuration of the exemplary structure, after the step ofFIG.19Bis performed to extend the pillar cavities107into the semiconductor material layer, the steps ofFIGS.20,21and22Aare performed to deposit the source layer122into the pillar cavities107. In the alternative embodiment ofFIG.22B, the junction between the solid semiconductor pillar portions60P of the vertical semiconductor channels60and the source layer122is shifted down into a horizontal plane which extends through the semiconductor material layer14. Thus, the source layer122comprises vertically-protruding source portions vertically extending into the semiconductor material layer14and having contact surfaces contacting the end surfaces of the pillar portions60P of the vertical semiconductor channels60.

Referring toFIG.23, a first alternative configuration of the first exemplary structure according to an embodiment of the present disclosure is illustrated at the processing steps ofFIGS.14A and14B. The first alternative configuration of the first exemplary structure may be derived from the first exemplary structure described above by forming a dielectric backside trench fill structure176comprising a dielectric material in lieu of each combination of a backside insulating spacer74and a backside trench via structure76at the processing steps ofFIG.10.

Referring toFIG.24A, the processing steps ofFIGS.15-22may be subsequently performed to provide the first alternative configuration of the exemplary structure.

Referring toFIG.24B, in a modified first alternative configuration, the steps ofFIGS.19B,20,21and22Bare performed to shift the junction between the solid semiconductor pillar portions60P of the vertical semiconductor channels60and the source layer122into a horizontal plane which extends through the semiconductor material layer14, according to the alternative embodiment. Thus, the source layer122comprises vertically-protruding source portions vertically extending into the semiconductor material layer14and having contact surfaces contacting the end surfaces of the pillar portions60P of the vertical semiconductor channels60.

Referring toFIG.25, a second alternative configuration of the first exemplary structure according to an embodiment of the present disclosure is illustrated at the processing steps ofFIG.6. The second alternative configuration of the first exemplary structure can be derived from the first exemplary structure illustrated inFIG.2by forming the support openings19prior to, or after, formation of the memory openings49and the memory opening fill structures58. In this case, the support openings19are filled with at least dielectric fill material such as silicon oxide to form support pillar structures20′ consisting essentially of the at least one dielectric fill material. In other words, formation of the memory openings49and the memory opening fill structures58can be effected by employing a separate set of processing steps than the set of processing steps and are employed to form the support openings19and the support pillar structures20′. Alternatively, the memory openings49and the support openings19may be formed at a same processing step employing an anisotropic etch process, and sacrificial fill material portions may be formed and is subsequently selectively removed to enables sequential formation of the memory opening fill structures58and the support pillar structures20′ in a forward order or in a reverse order.

Referring toFIG.26, the processing steps ofFIGS.7A-20can be subsequently performed to form the at least one metallic material layer (121L,123L) on the distal surface12D of the dielectric spacer layer12.

Referring toFIG.27, the processing steps ofFIGS.21and22may be subsequently performed to provide the second alternative configuration of the exemplary structure.

Referring toFIG.28, a third alternative configuration of the first exemplary structure according to an embodiment of the present disclosure can be derived from the second alternative configuration of the first exemplary structure forming a dielectric backside trench fill structure176comprising a dielectric material in lieu of each combination of a backside insulating spacer74and a backside trench via structure76at the processing steps ofFIG.10.

Referring toFIG.29, a fourth alternative configuration of the first exemplary structure according to an embodiment of the present disclosure may be derived from the first exemplary structure illustrated inFIG.15by performing a sequence of isotropic etch processes to remove portions of the memory films50that protrude above the horizontal plane including the distal surface12D of the dielectric spacer layer12. In other words, distal portions of the memory films50, which are more distal from the alternating stack (32,46) than the distal surface12D of the dielectric spacer layer12is from the alternating stack (32,46), are removed by the sequence of isotropic etch processes. The sequence of isotropic etch processes may comprise a first isotropic etch process that etches the material of the blocking dielectric layers52, a second isotropic etch process that etches the material of the charge storage layers54, and the third isotropic etch process that etches the material of the tunneling dielectric layers56. A cylindrical surface segment of each pillar portion60P of the vertical semiconductor channels60can be physically exposed after the sequence of isotropic etch processes. Physically exposed end surfaces of the vertical semiconductor channels60, i.e., physically exposed top surfaces of the pillar portions60P of the vertical semiconductor channels60, protrude out from the horizontal plane including the distal surface12D of the dielectric spacer layer12.

An optional ion implantation process may be used to doped the exposed pillar portions60P with first or second conductivity type dopants. In this embodiment, the pillar portions60P may have a higher doping concentration than the remaining hollow portions60H of the vertical semiconductor channels60.

An optional recrystallization process may be used to recrystallize the exposed pillar portions60P. For example, the exposed pillar portions60P may be irradiated with a laser, such as an excimer laser, to recrystallize the pillar portions60. If the pillar portions60P comprise amorphous silicon, then they may be recrystallized into polysilicon. If the pillar portions60P comprise polysilicon, then they may be recrystallized into larger grain polysilicon. In this embodiment, the pillar portions60P may comprise polysilicon having a larger average grain side than the remaining polysilicon hollow portions60H of the vertical semiconductor channels60. In one embodiment, both the ion implantation and recrystallization steps may be performed on the pillar portions60. Alternatively, one or both of these steps may be omitted.

Referring toFIG.30, the processing steps ofFIG.18can be performed to form contact recess regions103. Subsequently, the processing steps ofFIG.20can be performed to deposit at least one metallic material layer (121L,123L) directly on physically exposed end surfaces and cylindrical surface segments of the protruding regions of the pillar portions60P of the vertical semiconductor channels60.

Referring toFIG.31, the processing steps ofFIGS.21and22can be performed to provide the fourth alternative configuration of the exemplary structure. Interfaces between the source layer122and the vertical semiconductor channels60comprise portions that are more distal from the alternating stack (32,46) than the distal surface12D of the dielectric spacer layer12is from the alternating stack (32,46). In one embodiment, each of the vertical semiconductor channels60has a respective end surface contacting the source layer122and is more distal from the alternating stack (32,46) than the distal surface12D of the dielectric spacer layer12is form the alternating stack (32,46). Further, each of the vertical semiconductor channels60may have a respective cylindrical surface that contacts cylindrical surface segments of the source layer122and is more distal from the alternating stack (32,46) than the distal surface12D of the dielectric spacer layer12is form the alternating stack (32,46).

Referring toFIG.32, a fifth alternative configuration of the exemplary according to an embodiment of the present disclosure can be derived from the fourth alternative configuration of the first exemplary structure by forming a dielectric backside trench fill structure176comprising a dielectric material in lieu of each combination of a backside insulating spacer74and a backside trench via structure76at the processing steps ofFIG.10.

Referring toFIG.33, a sixth alternative configuration of the first exemplary structure according to an embodiment of the present disclosure can be derived from the fourth alternative configuration of the first exemplary structure by forming dielectric support pillar structures20′ employing the methods described with reference to the second alternative configuration of the first exemplary structure in lieu of the support pillar structures20described with reference to the exemplary structure.

Referring toFIG.34, a seventh alternative configuration of the first exemplary structure according to an embodiment of the present disclosure can be derived from the sixth alternative configuration of the first exemplary structure by forming a dielectric backside trench fill structure176comprising a dielectric material in lieu of each combination of a backside insulating spacer74and a backside trench via structure76at the processing steps ofFIG.10.

Referring toFIG.35, an eighth alternative configuration of the first exemplary structure according to an embodiment of the present disclosure may be the same as the first exemplary structure illustrated inFIG.17. The carrier substrate9and end portions of the memory films50and the vertical semiconductor channels60are removed such that physically exposed end surfaces of the vertical semiconductor channels60are flush with a distal surface12D of the dielectric spacer layer12. In one embodiment, physically exposed end surfaces of the memory films50may be flush with (i.e., in the same horizontal plane as) the distal surface12D of the dielectric spacer layer12.

Optionally, a sacrificial dielectric layer (e.g., silicon oxide layer) may be formed over the distal surface12D of the dielectric spacer layer12and the exposed pillar portions60P. Subsequently, the above described ion implantation and/or recrystallization processes may optionally be performed on the pillar portions through the sacrificial dielectric layer. The sacrificial dielectric layer is then removed by selective etching or non-selective etch back.

Referring toFIG.36, the processing steps ofFIG.18can be performed to form contact recess regions103. Subsequently, the processing steps ofFIG.20can be performed to deposit at least one metallic material layer (121L,123L) directly on physically exposed end surfaces and cylindrical surface segments of the protruding regions of the pillar portions60P of the vertical semiconductor channels60.

Referring toFIG.37, the processing steps ofFIGS.21and22can be performed to provide the eighth alternative configuration of the exemplary structure. Interfaces between the source layer122and the vertical semiconductor channels60may be flush (i.e., the same horizontal plane) with the distal surface12D of the dielectric spacer layer12. In one embodiment, each of the vertical semiconductor channels60has a respective end surface contacting the source layer122and is located within the same horizontal plane as the distal surface12D of the dielectric spacer layer12. In one embodiment, interfaces between the source layer122and the vertical semiconductor channels60are located entirely within the horizontal plane including the distal surface12D of the dielectric spacer layer12.

Referring toFIG.38, a ninth alternative configuration of the exemplary according to an embodiment of the present disclosure can be derived from the eighth alternative configuration of the first exemplary structure by forming a dielectric backside trench fill structure176comprising a dielectric material in lieu of each combination of a backside insulating spacer74and a backside trench via structure76at the processing steps ofFIG.10.

Referring toFIG.39, a tenth alternative configuration of the first exemplary structure according to an embodiment of the present disclosure can be derived if from the eighth alternative configuration of the first exemplary structure by forming the dielectric support pillar structures20′ employing the methods described with reference to the second alternative configuration of the first exemplary structure in lieu of the support pillar structures20described with reference to the exemplary structure.

Referring toFIG.40, an eleventh alternative configuration of the first exemplary structure according to an embodiment of the present disclosure can be derived from the tenth alternative configuration of the first exemplary structure by forming a dielectric backside trench fill structure176comprising a dielectric material in lieu of each combination of a backside insulating spacer74and a backside trench via structure76at the processing steps ofFIG.10.

Referring to all drawings and according to various embodiments of the present disclosure, a semiconductor structure comprises: a memory die (such as a first semiconductor die1000) bonded to a logic die (such as a second semiconductor die700), the memory die comprising: an alternating stack of insulating layers32and electrically conductive layers46; a semiconductor material layer14located over a distal surface32D of the alternating stack (32,46), wherein the semiconductor material layer14is more distal from the logic die than the alternating stack (32,46) is from the logic die; a dielectric spacer layer12located over a distal surface14D of the semiconductor material layer14; memory openings49vertically extending through the alternating stack (32,46), through the semiconductor material layer14, and at least partly through the dielectric spacer layer12; memory opening fill structures58located in the memory openings49wherein each of the memory opening fill structures58comprises a dielectric core62, a vertical semiconductor channel60having a hollow portion60H which surrounds the dielectric core62and a pillar portion62P which does not surround the dielectric core62, and a memory film50; and a source layer122located over a distal surface12D of the dielectric spacer layer12and contacting the pillar portions60P of the vertical semiconductor channels60.

In one embodiment, the pillar portion60P has a higher dopant concentration than the hollow portion60H. In another embodiment, the pillar portion60P has a larger grain size than the hollow portion60H.

In one embodiment, each of the memory openings49has a tapered-segment-containing vertical cross-sectional profile such that each of the memory openings49has a lesser lateral dimension within a horizontal plane including an interface between the semiconductor material layer14and the dielectric spacer layer12than within a horizontal plane including an interface between the semiconductor material layer14and the alternating stack (32,46).

In one embodiment, the dielectric spacer layer12is more distal from the logic die than any portion of the dielectric cores62of the memory opening fill structures58is from the logic die. In one embodiment, each of the dielectric cores62has a respective conical portion embedded within the semiconductor material layer14; and the respective conical portion has a respective apex that is more proximal to the logic die than the dielectric spacer layer12is to the logic die.

In one embodiment, each of the memory openings49has a sidewall including a sidewall segment of the semiconductor material layer14and a sidewall segment of the dielectric spacer layer12; and the sidewall segment of the semiconductor material layer14has a greater taper angle relative to a vertical direction than the sidewall segment of the dielectric spacer layer12.

In one embodiment shown inFIGS.22A and24A, the pillar portions60P of the vertical semiconductor channels60have a respective end surface located between a horizontal plane including the distal surface14D of the semiconductor material layer14and a horizontal plane including the distal surface12D of the dielectric spacer layer12; and the source layer122comprises vertically-protruding source portions vertically extending into the dielectric spacer layer12and having contact surfaces contacting the end surfaces of the pillar portions60P of the vertical semiconductor channels60. In one embodiment, each of the contact surfaces of the vertically-protruding source portions has a respective periphery that coincides with a periphery of a respective one of the end surfaces of the pillar portions60P of the vertical semiconductor channels60. In one embodiment, each of the vertically-protruding source portions comprises a respective cylindrical sidewall having a proximal periphery that coincides with a distal periphery of a sidewall of a respective one of the pillar portions60P of the vertical semiconductor channels60.

In the alternative embodiment shown inFIGS.22B and24B, the pillar portions60P of the vertical semiconductor channels60have a respective end surface located between a horizontal plane including the distal surface14D of the semiconductor material layer14and a horizontal plane including an opposing proximal surface14P of the semiconductor material layer14; and the source layer122comprises vertically-protruding source portions vertically extending into the semiconductor material layer14and having contact surfaces contacting the end surfaces of the pillar portions60P of the vertical semiconductor channels60.

In the second embodiment, each of the pillar portions60P of the vertical semiconductor channels60has a respective end surface contacting the source layer122and located within a horizontal plane that includes the distal surface of the dielectric spacer layer12(or is more distal from the alternating stack (32,46) than the distal surface of the dielectric spacer layer12is form the alternating stack (32,46)).

In one embodiment, the logic die700contains peripheral semiconductor devices710configured to control operation of a three-dimensional array of memory elements (e.g., portions of the memory films50in the NAND strings) located in the memory die1000.

In one embodiment, the alternating stack (32,46) comprises a staircase region in which lateral extents of the alternating stack (32,46) decrease with a vertical distance from the dielectric spacer layer12and in which stepped surfaces of the alternating stack (32,46) are present; the memory die comprises a stepped dielectric material portion65contacting the stepped surfaces; and the memory die comprises support pillar structures (20,20′) that vertically extend through the stepped dielectric material portion65, a respective portion of the alternating stack (32,46), and the semiconductor material layer14, and at least partly through the dielectric spacer layer12.

In one embodiment, the semiconductor structure comprises: at least one backside dielectric material layer (132,134,136) located on the source layer122; a bonding pad142vertically extending through the at least one backside dielectric material layer (132,134,136) and contacting the source layer122; a pass-through via structure84that vertically extends through the stepped dielectric material portion65; and an additional bonding pad144vertically extending through the at least one backside dielectric material layer (132,134,136) and electrically connected to the pass-through via structure84.

Referring toFIG.41, a second exemplary structure according to an embodiment of the present disclosure may be derived from the first exemplary structure illustrated inFIG.2by forming memory openings49and support openings through the insulating cap layer70, the alternating stack (32,42), the dielectric material portion65, and the semiconductor material layer14. The layout of the memory openings49and the support openings19in a plan view may be the same as in the first exemplary structure illustrated inFIGS.3A and3B. A patterned photoresist layer (not shown) may be employed as an etch mask. The anisotropic etch process employed to form the memory openings49and the support openings19ofFIG.41may comprise a first anisotropic etch step that etches materials of the insulating cap layer70, the alternating stack (32,42), and the stepped dielectric material portion65selective to the semiconductor material of the semiconductor material layer14, and a second anisotropic etch step that etches the material of the semiconductor material layer14selective to the material of the dielectric spacer layer12. According to an aspect of the present disclosure, each of the memory openings49and the support openings19may have a respective straight sidewall that vertically extends from a horizontal plane including the top surface of the insulating cap layer70to a top surface of the dielectric spacer layer12. An etch mask layer (such as the patterned photoresists layer) that is employed as an etch mask for the anisotropic etch process can be subsequently removed, for example, by ashing.

Referring toFIG.42and according to an aspect of the present disclosure, a selective growth process can be performed to grow a semiconductor material or an electrically conductive material (such as a metal material) from physically exposed surfaces of the semiconductor material layer14. The selective growth process may comprise a selective atomic layer deposition (ALD) process or a selective chemical vapor deposition (CVD) process in which a reactant gas and an etchant gas are concurrently or alternately flowed into a processing chamber. Generally, the nucleation rate of the decomposition products of the reactant gas on a physically exposed surface depends on the characteristics of the physically exposed surface.

Semiconductor surfaces such as physically exposed cylindrical surfaces of the semiconductor material layer14around the memory openings49and the support openings19provide a higher nucleation rate than dielectric surfaces such as surfaces of the alternating stack (32,42), the insulating cap layer70, and the stepped dielectric material portion65. During the selective CVD growth process, the flow rate of the etchant gas is selected such that the etch rate for the decomposition products of the reactant gas is greater than that nucleation rate of the decomposition products on dielectric surfaces, and is less than the new creation rate of the decomposition products on semiconductor surfaces. In this case, the decomposition products of the reactant gas accumulates only on semiconductor surfaces, and does not accumulate on dielectric surfaces.

The semiconductor material or the conductive material that grows from the physically exposed semiconductor surfaces of the semiconductor material layer14constitutes tubular spacers116having a respective tubular configuration. The duration of the selective growth process can be selected such that the lateral thickness, i.e., the lateral distance between an inner cylindrical sidewall and an outer cylindrical sidewall, of each tubular spacer116is less than the radius (in case of opening having a circular horizontal cross-sectional shapes) or the minor axis (in case of openings having an elliptical horizontal cross-sectional shapes) of each memory opening49and each support opening19. In other words, the duration of the tubular spacer116growth process is less than the time it takes the tubular spacers116to completely fill the entire width of the memory openings49, and there is a cavity49C remaining between the inner sidewall(s)116A of the tubular spacers116in each memory opening49. The cavity49C has a narrower width than the width of the memory opening49.

In one embodiment, each tubular spacer116comprises a cylindrical outer sidewall116B, the cylindrical inner sidewall116A that is laterally offset inward from the cylindrical outer sidewall116B by a uniform lateral offset distance (i.e., the lateral thickness), a planar annular surface116C contacting the dielectric spacer layer12and connecting a bottom periphery of the cylindrical inner sidewall116A to a bottom periphery of the cylindrical outer sidewall116B, and a convex annular surface116D connecting a top periphery of the cylindrical inner sidewall116A to a top periphery of the cylindrical outer sidewall116B. Alternatively, the convex annular surface116D may be replaced by at least one faceted surface segment in case faceting occurs growth of the semiconductor material or the conductive material of the tubular spacers116.

The lateral thickness of the tubular spacers116, as measured between an inner cylindrical sidewall116A and an outer cylindrical sidewall116B, may be in a range from 20% to 90%, such as from 30% to 80%, and/or from 40% to 70%, of the radius or the minor axis of the bottom region of the memory openings49and the support openings19. In an illustrative example, the radius or the minor axis of the horizontal cross-sectional shape at a bottom region of each of the memory openings49and the support openings19may be in a range from 15 nm to 100 nm, such as from 20 nm to 80 nm, and the lateral thickness of the tubular spacers116may be in a range from 5 nm to 80 nm, such as from 10 nm to 40 nm, although lesser and greater lateral thicknesses may also be employed.

In case the tubular spacers116comprise a semiconductor material, then the tubular spacers116may comprise, and/or may consist essentially of, amorphous silicon, polysilicon, a silicon germanium alloy, or a compound semiconductor material. The semiconductor material of the tubular spacers116may or may not be doped. For example, if the semiconductor material layer14comprises a doped silicon layer of a second conductivity type (e.g., n-type), then the tubular spacers116may also comprise doped silicon of the second conductivity type. In case the tubular spacers116comprise a conductive material, then tubular spacers116may comprise, and/or may consist essentially of an elemental metal (such as W, Ti, Ta, Mo, Ru, Co), or a metal-semiconductor alloy (such as a metal silicide) that is formed by selective growth of a metal and subsequent anneal to cause reaction between the metal and the semiconductor material in the semiconductor material layer14. In case the selectively deposited material of the tubular spacers116does not react with the semiconductor material in the semiconductor material layer14, then the cylindrical outer surfaces116B of the tubular spacers116may be vertically coincident with an overlying cylindrical sidewall of a respective memory opening49or a respective support opening19. A surface segment of the dielectric spacer layer12is a physically exposed underneath each cavity49C (e.g., a cylindrical cavity which is a portion of a respective memory opening49or a support opening19) that is laterally surrounded by a respective tubular spacer116.

Referring toFIG.43, an extension etch process can be performed to etch the material of the dielectric spacer layer12selective to the material of the tubular spacers116. The extension etch process may comprise an anisotropic etch process. Each of the memory openings49and the support openings19may be vertically extended through the dielectric spacer layer12underneath a respective cavity49C that is laterally surrounded by a respective tubular spacer116. In one embodiment, top portions of the carrier substrate9may be collaterally etched during a terminal portion of the extension etch process. Generally, the extension etch process may anisotropically etch portions of the dielectric spacer layer12that are not masked by the tubular spacers116, the alternating stack (32,42), or the stepped dielectric material portion65after formation of the tubular spacer116. A bottom end portion of each of the memory openings49and the support openings19is vertically extended through the dielectric spacer layer12. Each of the memory openings49and the support openings19may have a respective upper portion (49U,19U) located over the horizontal plane including a top surface of the semiconductor material layer14, and the respective lower portion (49L,19L) located under the horizontal plane including the top surface of the semiconductor material layer14. The lower portion has a smaller area and a smaller width (e.g., diameter) than the upper portion. The lower portion may comprise a cylindrical cavity having a uniform horizontal cross-sectional shape and vertically-extending from a top edge of an inner cylindrical sidewall116A of a tubular spacer116to a periphery of a bottommost surface of a respective memory opening49or a respective support opening19.

Referring toFIG.44, a memory film50is conformally deposited directly on a physically exposed surfaces of the carrier substrate9, physically exposed cylindrical sidewalls of the dielectric spacer layer12, physically exposed inner sidewalls of the tubular spacers116, physically exposed sidewalls of the insulating layers32and the spacer material layers42, and a physically exposed as surfaces of the insulating cap layer70and the stepped dielectric material portion65. Thus, memory film50is deposited into the memory openings49and the support openings19as described above with reference toFIG.4. The memory film50can be deposited in an outer portion of each cylindrical cavity49C that is laterally surrounded by a respective tubular spacer116. In one embodiment, the memory film50comprises a stack of layers including the blocking dielectric layer52, the charge storage layer54, the tunneling dielectric layer56. In one embodiment, each component layer within the memory film50may have the same material composition and the same thickness range as in the first exemplary structure described with reference toFIG.4.

In one embodiment, each tubular spacer116may have the outer sidewall116B that is vertically coincident with and is adjoined to an outer sidewall of a memory film50located in a same memory opening49or located in a same support opening19. The cylindrical inner sidewall116A contacts the outer sidewall of the memory film50.

Referring toFIG.45, a semiconductor channel material layer60L can be formed on the memory film50. In one embodiment, the semiconductor channel material layer60L may have the same material composition and the same thickness range as in the first exemplary structure described with reference toFIG.4. Each portion of the semiconductor channel material layer60L that is deposited in a memory opening49or in a support opening19comprises a respective pillar portion60P that is formed in a lower portion of the memory opening49or the support openings19, and a respective hollow portion60H that is formed in an upper portion of the memory opening49or the support opening19. The semiconductor channel material layer60L is formed in, and fills, an inner portion of each cylindrical cavity that is laterally surrounded by a respective tubular spacer116. Each pillar portion60P vertically extends through an opening (e.g., the cavity49C) in a respective tubular spacer116. In one embodiment, each pillar portion60P comprises a straight cylindrical surface segment60S and an annular concave surface segment60C connecting an edge of the straight cylindrical surface segment and a bottom edge of an outer sidewall of an overlying hollow portion60H of the semiconductor channel material layer60L. In one embodiment, the straight cylindrical surface segment vertically extends through the semiconductor material layer14and through the dielectric spacer layer12.

Referring toFIG.46, a dielectric core layer62L can be deposited in the elongated empty volumes within the memory openings49and the support openings19. The dielectric core layer62L includes a dielectric material, such as silicon oxide or organosilicate glass. The dielectric core layer62L can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD), atomic layer deposition (ALD), or by a self-planarizing deposition process, such as spin coating.

Referring toFIG.47, the dielectric core layer62L can be recessed selective to the material of the semiconductor channel material layer60L, for example, by a recess etch. The material of the dielectric core layer62L is vertically recessed below the horizontal plane core layer62L constitutes a dielectric core62.

Referring toFIG.48, a semiconductor material having a doping of a second conductivity type can be deposited in the recess regions that overlie the dielectric cores62. The second conductivity type that is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The atomic concentration of dopants of the second conductivity type in the deposited semiconductor material can be in a range from 5.0×1018/cm3to 2.0×1021/cm3, although lesser and greater atomic concentrations can also be used. The doped semiconductor material can be, for example, doped poly silicon.

Portions of the deposited semiconductor material, the semiconductor channel material layer60L, and the memory film50that are located above the horizontal plane including the top surface of the insulating cap layer70can be removed by a planarization process. For example, a chemical mechanical polishing (CMP) process or a recess etch process may be employed to remove material portions that overlie the horizontal plane including the top surface of the insulating cap layer70. Each remaining portion of the doped semiconductor material having a doping of the second conductivity type constitutes a drain region63. Each drain region63can be formed at a distal end, i.e., a top end, of a vertical semiconductor channel60that is distal from the semiconductor material layer14and the dielectric spacer layer12. Each remaining portion of the semiconductor channel material layer60L that remains in a respective memory opening49or in a respective support opening19constitutes a vertical semiconductor channel60. The memory film50is divided into a plurality of memory films50located within a respective one of the memory openings49and the support openings19.

Electrical current can flow through each vertical semiconductor channel60when a vertical NAND string including the vertical semiconductor channel60is turned on. Within each memory opening49, a tunneling dielectric layer56is surrounded by a charge storage layer54, and laterally surrounds a vertical semiconductor channel60. Each adjoining set of a blocking dielectric layer52, a charge storage layer54, and a tunneling dielectric layer56collectively constitutes a memory film50, which can store electrical charges with a macroscopic retention time. In some embodiments, a blocking dielectric layer52may not be present in the memory film50at this step, and a blocking dielectric layer may be subsequently formed after formation of backside recesses. Each combination of a memory film50and a vertical semiconductor channel60constitutes a memory stack structure55.

Each memory stack structure55is a combination of a semiconductor channel60, a tunneling dielectric layer56, a plurality of memory elements comprising portions of the charge storage layer54, and an optional blocking dielectric layer52. Each combination of a tubular spacer116, a memory stack structure55, a dielectric core62, and a drain region63within a memory opening49is herein referred to as a memory opening fill structure58. Each combination of a tubular spacer116, a memory film50, a vertical semiconductor channel60, a dielectric core62, and a drain region63within each support opening19constitutes a support pillar structure20.

An instance of a memory opening fill structure58can be formed within each memory opening49. An instance of the support pillar structure20can be formed within each support opening19. The support pillar structures20are formed through a region of the alternating stack (32,42) that underlie the stepped surfaces and a region of the stepped dielectric material portion65that overlie the stepped surfaces. Each of the support pillar structures20comprises a semiconductor material portion (i.e., a vertical semiconductor channel60of the support pillar structure20) having a same composition as the vertical semiconductor channels60of the memory opening fill structures58, and a dielectric layer stack (i.e., a memory film50of a support pillar structure20) containing a same set of dielectric material layers as each of the memory films50of the memory opening fill structures58. While the above embodiment is described using the configuration ofFIG.48for the memory stack structure, the methods of the present disclosure can be applied to alternative memory stack structures including different layer stacks or structures for the memory film50and/or for the vertical semiconductor channel60.

Generally, memory opening fill structures58are formed in the memory openings49. Each of the memory stack structures58comprises a respective tubular spacer116, a respective memory film50and a respective vertical semiconductor channel60. According to an aspect of the present disclosure, each vertical semiconductor channel60includes a pillar portion60P that vertically extends through the dielectric spacer layer12and has no hollow space inside. In one embodiment, each of the memory opening fill structures58comprises a respective dielectric core62that is laterally surrounded by the respective vertical semiconductor channel60. The dielectric core62does not extend inside the pillar portion60P, and the pillar portion60P does not surround the dielectric core62. Each vertical semiconductor channel60also includes a hollow portion60H which surrounds the dielectric core62.

In one embodiment, each vertical semiconductor channel60comprises a hollow portion60H which laterally surrounds the dielectric core62and vertically extends through the alternating stack (32,42), and a pillar portion60P which vertically extends through the semiconductor material layer14and the dielectric spacer12and does not surround the dielectric core62. Each vertical semiconductor channel60is formed in and fills an inner portion of a respective cavity49C that is laterally surrounded by a respective tubular spacer116. Each memory opening fill structure58is located in a respective memory opening49. In one embodiment, each memory opening fill structure58comprises a tubular spacer116that is formed by selective deposition of a material on physically exposed surfaces of the semiconductor material layer14while suppressing growth of the material from physically exposed surfaces of the alternating stack (32,42), a memory film50that is deposited on the tubular spacer116and on sidewalls of the alternating stack (32,42), a vertical semiconductor channel60that is formed on the memory film50, and a dielectric core62that is formed on the vertical semiconductor channel60. The vertical semiconductor channel60has a hollow portion60H which surrounds the dielectric core62and a pillar portion60P which does not surround the dielectric core62. The tubular spacer116laterally surrounds the pillar portion60P, is laterally spaced from the pillar portion60P by a cylindrical portion of the memory film50, and contacts a cylindrical sidewall of the semiconductor material layer14.

Referring toFIGS.49A and49B, a contact-level dielectric layer73and backside trenches79may be formed by performing the processing steps described with reference toFIGS.7A and7B.

Referring toFIGS.50A and50B, the processing steps described with reference toFIG.8may be performed to form backside recesses43through removal of the sacrificial material layers42selective to the insulating layers32. The processing steps described with reference toFIG.9may be performed to form electrically conductive layers46in the backside recesses43. The processing steps described with reference toFIG.10may be performed to form backside insulating spacers74and backside trench fill structures76. The processing steps described with reference toFIGS.11A and11Bmay be performed to form various contact via structures (88,86,84).

Referring toFIGS.51A and51B, the processing steps ofFIG.12may be performed to form a first line level dielectric layer90, various metal line structures (98,96,94) including bit lines98, additional metal interconnect structures168embedded within additional interconnect level dielectric layers160, and first bonding structures178. The bit lines98are electrically connected to the drain regions63. The first bonding structures178can be formed over the bit line98, and a subset of the first bonding structures178may be electrically connected to a respective one of the bit lines98. These steps form the first semiconductor die1000, which may be a memory die.

A second semiconductor die700can be subsequently provided, which may be a logic die including various semiconductor devices710. For example, the second semiconductor die700may be the same as the second semiconductor die700described with reference toFIG.13. In one embodiment, the logic die700comprises semiconductor devices710located on a semiconductor substrate (such as a logic-die substrate708) and second bonding structures788that overlie, and are electrically connected to, the semiconductor devices710. In one embodiment, the logic die700comprises peripheral devices configured to control operation of the electrically conductive layers46and the bit lines98.

The first semiconductor die1000and the second semiconductor die700can be bonded to each other employing metal-to-metal bonding or hybrid bonding. For example, the first bonding structures178of the first semiconductor die1000may be bonded to the second bonding structures788of the second semiconductor die700. The processing steps described with reference toFIGS.14A and14Bmay be employed to bond the first semiconductor die1000to the second semiconductor die700. A bonded assembly of the memory die1000and the logic die700is formed.

Optionally, the substrate semiconductor layer (e.g., the silicon wafer)709of the second semiconductor die700can be thinned from the backside. For example, a combination of grinding, polishing, and/or chemical etching may be employed to remove portions of the substrate semiconductor layer709that are distal from the interface between the first semiconductor die1000and the second semiconductor die700. Surfaces of the through-substrate contact via structures712can be physically exposed after thinning the substrate semiconductor layer709. A backside insulating layer714can be formed on the backside surface of the logic die substrate708(as thinned after the thinning process). Laterally-insulated through-substrate via structures (711,712) can vertically extend through the logic die substrate708to provide electrical contact to various input nodes and output nodes of the periphery circuitry in the second semiconductor die700. Each laterally-insulated through-substrate via structure (711,712) includes a through-substrate connection via structure712and a through-substrate insulating liner711that laterally surrounds the through-substrate conductive via structure712. Logic-side bonding pads716(which is also referred to as front bonding pads) can be formed on surface portions of the laterally-insulated through-substrate via structures (711,712). Generally, a semiconductor die is provided, which includes semiconductor devices710located on a semiconductor substrate (such as the substrate semiconductor layer709). The second bonding structures788overlie and are electrically connected to the semiconductor devices710, and laterally-insulated through-substrate via structures (711,712) can extend through the logic-side substrate708. Alternatively, the substrate semiconductor layer (e.g., the silicon wafer)709of the second semiconductor die700may be retained in the device and the logic-side bonding pads716and the laterally-insulated through-substrate via structures (711,712) are omitted.

In the bonded assembly, the alternating stack (32,46) may be more proximal to the logic die700than the semiconductor material layer14is to the logic die700. In one embodiment, the logic die700contains peripheral semiconductor devices configured to control operation of the electrically conductive layers46and the vertical semiconductor channels60. In one embodiment, the alternating stack (32,46) comprises a staircase region in which lateral extents of the alternating stack (32,46) decrease with a vertical distance from the dielectric spacer layer12and in which stepped surfaces of the alternating stack (32,46) are present. The memory die1000comprises a stepped dielectric material portion65contacting the stepped surfaces. In one embodiment, the memory die1000comprises support pillar structures20that vertically extend through the stepped dielectric material portion65, a respective portion of the alternating stack (32,46), and the semiconductor material layer14, and through the dielectric spacer layer12.

Referring toFIG.52, the carrier substrate9may be removed while retaining the dielectric spacer layer12, the memory opening fill structures58, and the backside insulating spacers74. For example, if the carrier substrate9comprises a semiconductor substrate (such as a commercially available silicon wafer), a grinding process may be performed to remove a predominant portion of the carrier substrate9from the backside, a polishing process may be performed to remove a proximal portion of the carrier substrate9that is proximal to the interface between the first semiconductor die1000and the second semiconductor die700, and an isotropic wet etch process employing an etchant that etches the semiconductor material of the carrier substrate9selective to the dielectric material of the dielectric spacer layer12to remove remaining portions of the semiconductor material of the carrier substrate9. In an illustrative example, the wet etch process may employ KOH as an etchant. Portions of the memory opening fill structures58may protrude from the exposed distal surface12D of the dielectric spacer layer12. A distal surface14D of the semiconductor material layer14contacts a proximal surface of the dielectric spacer layer12. A distal surface32D of the alternating stack (32,46) contacts a proximal surface of the semiconductor material layer14. In the bonded assembly, the interface between the memory die1000and the logic die700is employed as a reference plane for determining distality or proximity of surfaces within the bonded assembly.

Referring toFIG.53, a non-selective planarization process may be performed to remove material portions that overlie the horizontal plane including the distal surface12D of the dielectric spacer layer12. The non-selective planarization process may employ a chemical mechanical polishing process. Portions of the memory films50, the vertical semiconductor channels60, the backside insulating spacers74, and the backside trench via structures76that overlie the horizontal plane including the distal surface12D of the dielectric spacer layer12can be removed in by the non-selective planarization process. A distal end surface of each of the vertical semiconductor channels60can be physically exposed. Specifically, planar end surfaces of the pillar portions60P of the vertical semiconductor channels60can be physically exposed, which can be located within the horizontal plane including the top surface of the distal surface12D of the dielectric spacer layer12.

Referring toFIG.54, dopants of the first conductivity type may be implanted into the pillar portions60P of the vertical semiconductor channels60. The dose of the ion implantation process may be selected such that the pillar portions60P include dopants of the first conductivity type at an atomic concentration in a range from 1.0×1016/cm3to 1.0×1019/cm3, such as from 1.0×1017/cm3to 1.0×1018/cm3. In this case, the pillar portions60P may have a higher dopant concentration than the hollow portions60H.

A photoresist layer (not shown) can be applied over the dielectric spacer layer12, and can be lithographically patterned to form openings in areas that overlie the pass-through via structures84. An etch process, such as an anisotropic etch process, can be performed to etch through unmasked portions of the dielectric spacer layer12and the semiconductor material layer14. A contact recess region vertically extending through the dielectric spacer layer12and the semiconductor material layer14can be formed over each pass-through via structure84. A and a surface of the at least one pass-through via structure84can be physically exposed at the bottom of each contact recess region103. The photoresists layer can be subsequently removed, for example, by ashing.

At least one electrically conductive material layer can be deposited on and over the distal surface12D of the dielectric spacer layer12. The at least one conductive material layer may comprise at least one metallic material layer (121L,123L). In one embodiment, the at least one metallic material layer (121L,123L) may comprise a metallic diffusion barrier liner121L and a metallic fill material layer123L. The metallic diffusion barrier liner121L may comprise a metallic diffusion barrier material such as Ti, Ta, WN, TiN, TaN, MoN, TiC, TaC, WC, or a combination thereof. The thickness of a horizontally-extending portion of the metallic diffusion barrier liner121L may be in a range from 1 nm to 10 nm, although lesser and greater thicknesses may also be employed. The metallic diffusion barrier liner121L may be deposited by a conformal deposition process or a non-conformal deposition process. The metallic fill material layer123L comprises at least one high-conductivity metal such as W, Ti, Ta, Mo, Ru, Co, Nb, Cu, Al, etc. The metallic fill material layer123L may be deposited by physical vapor deposition, chemical vapor deposition, electroplating, electroless plating, etc. The at least one metallic material layer (121L,123L) can contact each end surface of the pillar portions60P of the vertical semiconductor channels60and each end surface of the pass-through via structures84. Alternatively, a heavily doped semiconductor material, such as heavily doped polysilicon may be used instead of or in addition to the at least one metallic material layer (121L,123L).

Referring toFIG.55, a photoresist layer (not shown) may be applied over the top surface of the at least one metallic material layer (121L,123L), and may be lithographically patterned to form discrete areas. An etch process, such as an anisotropic etch process, can be performed to transfer the pattern in the photoresist layer through the at least one metallic material layer (121L,123L), the dielectric spacer layer12, and the semiconductor material layer14. The at least one metallic material layer (121L,123L), the dielectric spacer layer12, and the semiconductor material layer14can be divided into multiple discrete portions that are laterally spaced apart from each other by backside isolation trenches.

Patterned portions of the at least one metallic material layer (121L,123L) comprise a source layer122that contacts end surfaces of the pillar portions60P of the vertical semiconductor channels60. Alternatively, the source layer122may comprise a heavily doped semiconductor material, such as heavily doped polysilicon, instead of or in addition to the at least one metallic material layer (121L,123L). Generally, the source layer122comprises at least one electrically conductive material that is in direct contact with the distal surface12D of the dielectric spacer layer12and in direct contact with distal end surfaces of the solid semiconductor pillar portions60P of the vertical semiconductor channels60. The source layer122may comprise a source metallic barrier liner122A that is a patterned portion of the metallic diffusion barrier liner121L, and a source metal layer122B that is a patterned portion of the metallic fill material layer123L.

Thus, the source layer122is formed over the dielectric spacer layer12, and directly on the pillar portions60P of the vertical semiconductor channels60. The pillar portions60P of the vertical semiconductor channels60have end surfaces contacting the source layer122within a horizontal plane that includes an interface between the source layer122and the dielectric spacer layer12. In one embodiment, the straight cylindrical surface segments of the pillar portions60P of the vertical semiconductor channels60vertically extend through the semiconductor material layer14and through the dielectric spacer layer12, and are adjoined to the source layer122.

Further, patterned portions of the at least one metallic material layer (121L,123L) comprise a metallic contact plate124that contacts end surfaces of a respective one of the pass-through via structures84. The metallic contact plate124may comprise a contact metallic barrier liner124A that is a patterned portion of the metallic diffusion barrier liner121L, and a contact metal layer124B that is a patterned portion of the metallic fill material layer123L. Optionally, patterned portions of the at least one metallic material layer (121L,123L) may comprise dummy metallic plates126that contact end surfaces of a respective one of the support pillar structures20. The dummy metal plates126may comprise a dummy metallic barrier liner126A that is a patterned portion of the metallic diffusion barrier liner121L, and a dummy metal layer126B that is a patterned portion of the metallic fill material layer123L. The dummy metal plates126may be laterally spaced from each other to minimize the effect of leakage currents. The dummy metal plates126are electrically inactive components which are not connected to an external voltage source, and are electrically floating.

In one embodiment, the dielectric spacer layer12is more distal from the second semiconductor die700than any portion of the dielectric cores62of the memory opening fill structures58is from the second semiconductor die700, i.e., more distal from the second semiconductor die700than the most distal portions of the dielectric cores62of the memory opening fill structures58.

In one embodiment, each of the memory openings49has a sidewall including the cylindrical inner sidewall116A of the tubular spacer116and a sidewall segment of the dielectric spacer layer12. In one embodiment, each of the vertical semiconductor channels60comprises a pillar portion60P having a respective end surface located between a horizontal plane including the distal surface14D of the semiconductor material layer14and a horizontal plane including the distal surface12D of the dielectric spacer layer12.

In one embodiment, the alternating stack (32,46) comprises a staircase region in which lateral extents of the alternating stack (32,46) decrease with a vertical distance from the dielectric spacer layer12and in which stepped surfaces of the alternating stack (32,46) are present. The memory die1000comprises a stepped dielectric material portion65contacting the stepped surfaces. In one embodiment, the memory die comprises support pillar structures20that vertically extend through the stepped dielectric material portion65, a respective portion of the alternating stack (32,46), and the semiconductor material layer14, and at least partly through the dielectric spacer layer12.

Backside dielectric material layers (132,134,136) can be formed over the source layer122and the metallic contact plates124. The backside dielectric material layers (132,134,136) may comprise, for example, a backside dielectric fill material layer132including a dielectric fill material, such as a silicon oxide, a backside dielectric passivation layer134that comprises a diffusion blocking dielectric material, such as a silicon nitride or silicon carbide nitride, and a polymer material layer136that includes a photosensitive polymer material such as polyimide. The polymer material layer136may be patterned with the discrete openings, for example, by lithographic exposure and development, and an etch process such as an anisotropic etch process can be performed to transfer the pattern of the openings in the polymer material layer136through the backside dielectric passivation layer134and the backside dielectric fill material layer132.

At least one metallic material including on under bump metallurgy (UBM) material stack may be deposited in the openings through the backside dielectric material layers (132,134,136) directly on physically exposed surfaces of the source layer122and the metallic contact plates124. The at least one metallic material can be subsequently patterned to form bonding pads (142,144), which may comprise at least one source-side a bonding pad142and contact-connection bonding pads144.

Generally, at least one backside dielectric material layer (132,134,136) can be formed in on the source layer122, and a bonding pad (such as a source-side bonding pad142) vertically extends through the at least one backside dielectric material layer (132,134,136) and contacts the source layer122. A pass-through via structure84may vertically extend through the stepped dielectric material portion65to the peripheral devices710of the logic die700, and an additional bonding pad vertically extending through the at least one backside dielectric material layer (132,134,136) and electrically connected to the pass-through via structure84.

Referring toFIG.56, a first alternative configuration of the second exemplary bonded assembly may be derived from the second exemplary bonded assembly illustrated inFIG.55by forming a dielectric backside trench fill structure176comprising a dielectric material in lieu of each combination of a backside insulating spacer74and a backside trench via structure76.

Referring toFIG.57, an alternative configuration of the second exemplary structure can be derived from the second exemplary structure illustrated inFIG.48by forming support pillar structures20′ prior to, or after, formation of the memory opening fill structures58. In this case, the support openings19are filled with at least dielectric fill material such as silicon oxide to form support pillar structures20′ consisting essentially of the at least one dielectric fill material. In other words, the memory openings49and the memory opening fill structures58can formed using a separate set of processing steps than the set of processing steps and are employed to form the support openings19and the support pillar structures20′. Alternatively, the memory openings49and the support openings19may be formed at a same processing step employing an anisotropic etch process, and sacrificial fill material portions may be formed and are subsequently selectively removed to enables sequential formation of the memory opening fill structures58before or after the support pillar structures20′.

Referring toFIG.58, subsequent processing steps described above may be performed to provide a second alternative configuration of the second exemplary bonded assembly according to an embodiment of the present disclosure.

Referring toFIG.59, a vertical cross-sectional view of a third alternative configuration of the second exemplary bonded assembly is illustrated. The features and the processing steps of the first alternative configuration and the second alternative configuration of the second exemplary bonded assembly may be employed to provide the third alternative configuration of the second exemplary bonded assembly.

Referring toFIG.60, a fourth alternative configuration of the second exemplary bonded assembly according to an embodiment of the present disclosure may be derived from any of the above-described configurations of the second exemplary bonded assembly by vertically recessing the pillar portions60P of the vertical semiconductor channels60prior to deposition of the at least one metallic material layer (121L,123L) that is subsequently employed to form the source layer122, as described with reference toFIG.20above.

Referring to various embodiments and drawings that are related to the second exemplary bonded assembly and/or the second exemplary structure, a semiconductor structure that comprises a memory die1000is provided. The memory die1000comprises: an alternating stack (32,46) of insulating layers32and electrically conductive layers46; a semiconductor material layer14located over the alternating stack (32,46); a dielectric spacer layer12located over the semiconductor material layer14, and spaced from the alternating stack (32,46) by the semiconductor material layer14; a memory opening49vertically extending through the alternating stack (32,46), through the semiconductor material layer14, and at least partly through the dielectric spacer layer12; a memory opening fill structure58located in the memory opening49and comprising a dielectric core62, a vertical semiconductor channel60having a hollow portion60H which surrounds the dielectric core62and a pillar portion60P which does not surround the dielectric core62, a memory film50; and a source layer122located over the dielectric spacer layer12and contacting the pillar portion60P of the vertical semiconductor channel60.

In one embodiment, the memory die also includes a tubular spacer116that laterally surrounds the pillar portion60P, is laterally spaced from the pillar portion60P by a cylindrical portion of the memory film50, and contacts a cylindrical sidewall of the semiconductor material layer14.

In one embodiment, the pillar portion60P vertically extends through an opening in the tubular spacer116. In one embodiment, the pillar portion60P comprises a straight cylindrical surface segment and an annular concave surface segment connecting an edge of the straight cylindrical surface segment and an edge of an outer sidewall of the hollow portion60H of the vertical semiconductor channel60. In one embodiment, the straight cylindrical surface segment vertically extends through the semiconductor material layer14and through the dielectric spacer layer12, and is adjoined to the source layer122.

In one embodiment, the tubular spacer116comprises a semiconductor material or a conductive material. In one embodiment, the tubular spacer116has an outer sidewall that is vertically coincident with, and is adjoined to, an outer sidewall of the memory film50. In one embodiment, the tubular spacer116comprises a cylindrical outer sidewall, a cylindrical inner sidewall that is laterally offset inward from the cylindrical outer sidewall by a uniform lateral offset distance, a planar annular surface contacting the dielectric spacer layer12, and a convex annular surface contacting the memory film50.

In one embodiment, the pillar portion60P has a higher dopant concentration than the hollow portion60H. In one embodiment, the pillar portion60P of the vertical semiconductor channel60has an end surface contacting the source layer122within a horizontal plane that includes an interface between the source layer122and the dielectric spacer layer12.

In one embodiment, the semiconductor structure comprises a logic die700that is bonded to the memory die1000, wherein the alternating stack (32,46) is more proximal to the logic die700than the semiconductor material layer14is to the logic die700. In one embodiment, the logic die700contains peripheral semiconductor devices configured to control operation of the electrically conductive layers46and the vertical semiconductor channel60.

In one embodiment, the alternating stack (32,46) comprises a staircase region in which lateral extents of the alternating stack (32,46) decrease with a vertical distance from the dielectric spacer layer12and in which stepped surfaces of the alternating stack (32,46) are present; the memory die1000further comprises a stepped dielectric material portion65contacting the stepped surfaces; and the memory die1000further comprises support pillar structures20that vertically extend through the stepped dielectric material portion65, a respective portion of the alternating stack (32,46), and the semiconductor material layer14, and at least partly through the dielectric spacer layer12.

In one embodiment, the semiconductor structure comprises: at least one backside dielectric material layer (132,134,136) located on the source layer122; a bonding pad142vertically extending through the at least one backside dielectric material layer (132,134,136) and contacting the source layer122; a pass-through via structure84that vertically extends through the stepped dielectric material portion65; and an additional bonding pad144vertically extending through the at least one backside dielectric material layer (132,134,136) and electrically connected to the pass-through via structure84.

The various embodiments of the present disclosure may be employed to provide reliable physical and electrical contact between end portions of the vertical semiconductor channels60in a three-dimensional memory device to a source layer112, which may be formed on a backside of a bonded assembly after removal of a carrier substrate.

In the second embodiment, by using the tubular spacers116to narrow the bottom of the memory openings49, the bottom position of the dielectric core62is set in a more precise location. Therefore, the length of the pillar portion60P of the semiconductor channel60is more precisely controlled, leading to a more stable device. Furthermore, the thickness of the semiconductor material layer14may be reduced, which reduces the process cost. Finally, by adding the tubular spacers116, a taper etch of the semiconductor material layer14is not required during formation of the memory opening49, which simplifies the device fabrication process.

Although the foregoing refers to particular preferred embodiments, it will be understood that the claims are not so limited. It will occur to those of ordinary skill in the art that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the claims. Compatibility is presumed among all embodiments that are not alternatives of one another. The word “comprise” or “include” contemplates all embodiments in which the word “consist essentially of” or the word “consists of” replaces the word “comprise” or “include,” unless explicitly stated otherwise. Where an embodiment using a particular structure and/or configuration is illustrated in the present disclosure, it is understood that the claims may be practiced with any other compatible structures and/or configurations that are functionally equivalent provided that such substitutions are not explicitly forbidden or otherwise known to be impossible to one of ordinary skill in the art. All of the publications, patent applications and patents cited herein are incorporated herein by reference in their entirety.