Patent ID: 12200921

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.

The present disclosure will be described with respect to embodiments, a static random-access memory (SRAM) formed of fin field effect transistors (FinFETs). The embodiments of the disclosure may also be applied, however, to a variety of integrated circuits. Various embodiments will be explained in detail with reference to the accompanying drawings.

Static random-access memory (SRAM) is a type of volatile semiconductor memory that uses bistable latching circuitry to store each bit. Each bit in an SRAM is stored on four transistors (PU-1, PU-2, PD-1, and PD-2) that form two cross-coupled inverters. This SRAM cell has two stable states which are used to denote 0 and 1. Two additional access transistors (PG-1 and PG-2) serve to control the access to a storage cell during read and write operations.

FIG.1is a circuit diagram of a six transistor (6T) SRAM cell. The SRAM cell10includes a first inverter102formed by a pull-up transistor PU-1 and a pull-down transistor PD-1. The SRAM cell10further includes a second inverter104formed by a pull-up transistor PU-2 and a pull-down transistor PD-2. Furthermore, both the first inverter102and second inverter104are coupled between a voltage bus Vdd and a ground potential Vss. In some embodiments, the pull-up transistor PU-1 and PU-2 can be p-type metal oxide semiconductor (PMOS) transistors while the pull-down transistors PD-1 and PD-2 can be n-type metal oxide semiconductor (NMOS) transistors, and the claimed scope of the present disclosure is not limited in this respect.

InFIG.1, the first inverter102and the second inverter104are cross-coupled. That is, the first inverter102has an input connected to the output of the second inverter104. Likewise, the second inverter104has an input connected to the output of the first inverter102. The output of the first inverter102is referred to as a storage node103. Likewise, the output of the second inverter104is referred to as a storage node105. In a normal operating mode, the storage node103is in the opposite logic state as the storage node105. By employing the two cross-coupled inverters, the SRAM cell10can hold the data using a latched structure so that the stored data will not be lost without applying a refresh cycle as long as power is supplied through Vdd.

In an SRAM device using the 6T SRAM cells, the cells are arranged in rows and columns. The columns of the SRAM array are formed by a bit line pairs, namely a first bit line BL and a second bit line BLB. The cells of the SRAM device are disposed between the respective bit line pairs. As shown inFIG.1, the SRAM cell10is placed between the bit line BL and the bit line BLB.

InFIG.1, the SRAM cell10further includes a first pass-gate transistor PG-1 connected between the bit line BL and the output103of the first inverter102. The SRAM cell10further includes a second pass-gate transistor PG-2 connected between the bit line BLB and the output105of the second inverter104. The gates of the first pass-gate transistor PG-1 and the second pass-gate transistor PG-2 are connected to a word line WL, which connects SRAM cells in a row of the SRAM array.

In operation, if the pass-gate transistors PG-1 and PG-2 are inactive, the SRAM cell10will maintain the complementary values at storage nodes103and105indefinitely as long as power is provided through Vdd. This is so because each inverter of the pair of cross coupled inverters drives the input of the other, thereby maintaining the voltages at the storage nodes. This situation will remain stable until the power is removed from the SRAM, or, a write cycle is performed changing the stored data at the storage nodes.

In the circuit diagram ofFIG.1, the pull-up transistors PU-1, PU-2 are p-type transistors. The pull-down transistors PD-1, PD-2, and the pass-gate transistors PG-1, PG-2 are n-type transistors. According to various embodiments, the pull-up transistors PU-1, PU-2, the pull-down transistors PD-1, PD-2, and the pass-gate transistors PG-1, PG-2 can be implemented by FinFETs.

The structure of the SRAM cell10inFIG.1is described in the context of the 6T-SRAM. One of ordinary skill in the art, however, should understand that features of the various embodiments described herein may be used for forming other types of devices, such as an8T-SRAM memory device, or memory devices other than SRAMs. Furthermore, embodiments of the present disclosure may be used as stand-alone memory devices, memory devices integrated with other integrated circuitry, or the like. Accordingly, the embodiments discussed herein are illustrative of ways to make and use the disclosure, and do not limit the scope of the disclosure.

Reference is made toFIGS.2A to2D.FIG.2Ais a top view of a memory device in accordance with some embodiments of the present disclosure.FIG.2Bis a cross-sectional view along line B-B ofFIG.2A.FIG.2Cis a cross-sectional view along line C-C ofFIG.2A.FIG.2Dis an enlarged view ofFIG.2A. InFIG.2A, the integrated circuit is an SRAM device100including four memory cells200a,200b,200c, and200d. In some other embodiments, however, the number of the memory cells200a,200b,200c, and200din the SRAM device100is not limited in this respect.

In some embodiments, the SRAM device100includes a substrate210. The substrate210may be a semiconductor material and may include known structures including a graded layer or a buried oxide, for example. In some embodiments, the substrate210includes bulk silicon that may be undoped or doped (e.g., p-type, n-type, or a combination thereof). Other materials that are suitable for semiconductor device formation may be used. Other materials, such as germanium, quartz, sapphire, and glass could alternatively be used for the substrate210. Alternatively, the silicon substrate210may be an active layer of a semiconductor-on-insulator (SOI) substrate or a multi-layered structure such as a silicon-germanium layer formed on a bulk silicon layer.

In some embodiments, the substrate210includes a plurality of P-well regions212,214and a plurality of N-well regions216. As an example of memory cell200a, each cell includes an N-well region216and two P-well regions212,214on opposite sides of the N-well region216. That is, the N-well region216is between two P-well regions212,214. In some embodiments, NMOS devices will be formed on the P-well regions212,214, and PMOS devices will be formed on N-well regions216, which will be discussed later. In some embodiments, the P-well regions212,214are implanted with P-type dopant material, such as boron ions, and the N-well regions216are implanted with N-type dopant material such as arsenic ions. During the implantation of the P-well regions212,214, the N-well regions216are covered with masks (such as photoresist), and during implantation of the N-well regions216, the P-well regions212,214are covered with masks (such as photoresist).

In some embodiments, the SRAM device100includes a plurality of semiconductor fins220a,220b,220c,220d,220e, and220f. For example, semiconductor fins220a,220bare disposed within the P-well regions212of the substrate210, semiconductor fins220b,220care disposed within the N-well regions216of the substrate210, and semiconductor fins220e,220fare disposed within the N-well regions214of the substrate210, respectively. In some embodiments, the semiconductor fins220a,220b,220c,220d,220e, and220fmay be or include, for example, silicon.

In some embodiments, the semiconductor fins220a,220b,220c,220d,220e, and220fmay be formed, for example, by patterning and etching the substrate210using photolithography techniques. In some embodiments, a layer of photoresist material (not shown) is deposited over the substrate210. The layer of photoresist material is irradiated (exposed) in accordance with a desired pattern (semiconductor fins220a,220b,220c,220d,220e, and220fin this case) and developed to remove a portion of the photoresist material. The substrate210is then etched using the remaining photoresist material as an etching mask, so as to form the semiconductor fins220a,2206,220c,220d,220e, and220f.

In some embodiments, a plurality of isolation regions (not shown) may be formed on the substrate210and in the spaces between the semiconductor fins220a,220b,220c,220d,220e, and220f. The isolation structures, which act as a shallow trench isolation (STI) around the semiconductor fins220a,220b,220c,220d,220e, and220f, may be formed by chemical vapor deposition (CVD) techniques using tetra-ethyl-ortho-silicate (TEOS) and oxygen as a precursor.

In some embodiments, the SRAM device100includes gate structures230a,230b,230c,230d,230e, and230f. As an example in the memory cell200a, the gate structures230a,230bare disposed in the P-well region212of the substrate210and cross the semiconductor fins220a,220b, the gate structures230c,230dare disposed in the N-well region216of the substrate210and cross the semiconductor fins220c,220d, and the gate structures230e,230fare disposed in the P-well region214of the substrate210and cross the semiconductor fins220e,220f. In some embodiments, the gate structures230a,230cextend continuously from to each other, and thus the gate structures230a,230ccan also be regarded as first and second portions of a single gate structure. On the other hand, the gate structures230d,230fextend continuously from each other, and thus the gate structures230d,230fcan also be regarded as first and second portions of a single gate structure.

In the P-well region212of the memory cell200a, the gate structure230aand the semiconductor fins220a,220bform a pull-down transistor PD-2. The gate structure230band the semiconductor fins220a,220bform a pass-gate transistor PG-2. The pull-down transistor PD-2 and the pass-gate transistor PG-2 are NMOS devices. On the other hand, In the N-well region216of the memory cell200a, the gate structure230cand the semiconductor fin220cform a pull-up transistor PU-2. The gate structure230dand the semiconductor fin220dform a pull-up transistor PU-1. The pull-up transistor PU-1 and the pull-up transistor PU-2 are PMOS devices. In the P-well region214of the memory cell200a, the gate structure230eand semiconductor fins220e,220fform a pass-gate transistor PG-1. The gate structure230fand semiconductor fins220;220fform a pull-down transistor PD-1. The pass-gate transistor PG-1 and the pull-down transistor PD-1 are NMOS devices. Accordingly, the memory cell200aof the SRAM device100is a six-transistor (6T) SRAM. One of ordinary skill in the art, however, should understand that features of the various embodiments described herein may be used for forming other types of devices, such as an8T-SRAM memory device or other integrated circuit.

As shown inFIG.2A, when the memory cells200a˜200dare arranged together to form an array (the SRAM device100herein), the cell layouts may be flipped or rotated to enable higher packing densities. Often by flipping the cell over a cell boundary or axis and placing the flipped cell adjacent the original cell, common nodes and connections can be combined to increase packing density. For example, the memory cells200a˜200dare mirror images and in rotated images of each other. Specifically, the memory cells200aand200bare mirror images across a Y-axis, as is the memory cells200cand200d. The memory cells200aand200care mirror images across an X-axis, as is the memory cells200band200d. Further, the diagonal memory cells (the memory cells200aand200d; the memory cells200band200c) are rotated images of each other at 180 degrees.

The SRAM device100includes a plurality of gate spacers240a,240b,240c,240d,240e, and240f. For example, a pair of gate spacers240aare disposed on opposite sides of the gate structure230a, a pair of gate spacers240bare disposed on opposite sides of the gate structure230b, a pair of gate spacers240care disposed on opposite sides of the gate structure230c, a pair of gate spacers240dare disposed on opposite sides of the gate structure230d, a pair of gate spacers240eare disposed on opposite sides of the gate structure230e, and a pair of gate spacers240fare disposed on opposite sides of the gate structure230f. In some embodiments, the gate spacers240a,240cextend continuously from each other and are made of continuous material, and thus the gate spacers240a,240ccan also be regarded as first and second portions of a single gate spacer. On the other hand, the gate spacers240d,240fextend continuously from each other and are made of continuous material, and thus the gate spacers240d,240fcan also be regarded as first and second portions of a single gate spacer.1nsome embodiments, the gate spacers240a,240b,240c,240d,240e, and240fmay include SiO2, Si3N4, SiOxNy, SiC, SiCN films, SiOC, SiOCN films, and/or combinations thereof.

The SRAM device100includes a plurality of isolation structures250. In some embodiments, the isolation structures250separate parts of the gate structures230a-230f. For example, in memory cell200a, an isolation structure is disposed between the gate structures230cand230e, another isolation structure250is disposed between the gate structures230band230d. In some embodiments, the isolation structures250include silicon oxide, silicon nitride or a suitable insulating material.

Reference is made toFIGS.2A,2B and2C, in whichFIG.2Bis a cross-sectional view along line B-B ofFIG.2A, andFIG.2Cis a cross-sectional view along line C-C ofFIG.2A. In greater detail,FIG.2Bis a cross-sectional view along a lengthwise direction of the semiconductor fin220band taken along the gate structure230a, andFIG.2Cis a cross-sectional view along a lengthwise direction of the semiconductor fin220cand taken along the gate structure230c. It is noted thatFIGS.2B and2Chave the same scale, and thus the dimensions ofFIGS.2B and2Care substantially the same.

InFIG.2B, the semiconductor fin220bis over the substrate210, the gate structure230ais over the semiconductor fin220b, and the gate spacers240aare disposed on opposite sidewalls of the gate structure230a. In some embodiments, the gate structure230aincludes a gate dielectric layer GD, a work function metal layer WFM1, a work function metal layer WFM2, and a gate metal GM. A plurality of source/drain structures260N are disposed in the semiconductor fin220band on opposite sides of the gate structure230a, respectively. A contact etch stop layer (CESL)265is disposed over the source/drain structures260N, and along the sidewalls of the gate spacers240a. An interlayer dielectric (ILD) layer270is disposed over the CESL265.

InFIG.2C, the semiconductor fin220cis over the substrate210, the gate structure230cis over the semiconductor fin220c, and the gate spacers240care disposed on opposite sidewalls of the gate structure230c. In some embodiments, the gate structure230cincludes a gate dielectric layer GD, a work function metal layer WFM1, and a gate metal GM. A plurality of source/drain structures260P are disposed in the semiconductor fin220cand on opposite sides of the gate structure230c. CESL265is disposed over the source/drain structures260P and along the sidewalls of the gate spacers240c. ILD layer270is disposed over the CESL265.

Reference is made toFIGS.2B and2C. In some embodiments, the gate structure230ais wider than the gate structure230c. For example, a width W1 of the gate structure230ais greater than a width W2 of the gate structure230c. That is, a distance between gate spacers240ais greater than a distance between the gate spacers240c. On the other hand, each gate spacer240ais narrower than each gate spacer240c. For example, a width W3 of each gate spacer240ais lower than a width W4 of each gate spacer240c. Moreover, a total width W5 of the gate structure230aand the gate spacers240aon opposite sides of the gate structure230ais substantially equal to the total width W6 of the gate structure230cand the gate spacers240con opposite sides of the gate structure230c. Stated another way, the width W1 of the gate structure230a, the width W2 of the gate structure230c, the width W3 of the gate spacers240a, and the width W4 of the gate spacers240csubstantially satisfy (W1+2*W3)=(W2+2*W4), in which W1+2*W3=W5 and W2+2*W4=W6. From another view point, a distance between two source/drain structures260N on opposite sides of the gate structure230a(i.e., substantially equal to width W5) is substantially equal to a distance between two source/drain structures260P on opposite sides of the gate structure230c(i.e., substantially equal to width W6).

In some embodiments, the gate dielectric layers GD of the gate structures230a,230care made of high-k dielectric materials, such as metal oxides, transition metal-oxides, or the like. Examples of the high-k dielectric material include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium tantalum oxide (HITaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, or other applicable dielectric materials. In some embodiments, the gate dielectric layers GD are oxide layers. The gate dielectric layers GD may be formed by a deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma enhanced CVD (PECVD) or other suitable techniques.

In some embodiments, the work function metal layers WFM1 of the gate structures230a,230cmay include tantalum nitride (TaN). In some embodiments, the work function metal layer WFM2 of the gate structure230amay include a titanium-containing material, such as, for example, titanium nitride (TiN). In some embodiments, tantalum is absent in the work function metal layer WFM2. The work function metal layers WFM1 and/or WFM2 can provide a suitable work function value for a gate structure of a semiconductor device, so as to benefit tuning the threshold voltage of the semiconductor device. The work function metal layers WFM1 and WFM2 can be formed by suitable process, such as ALD, CVD, PVD, remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), metal organic CVD (MOCVD), sputtering, plating, other suitable processes, or combinations thereof. In some embodiments, the work function metal layer WFM2 is absent in the gate structure230cofFIG.2C. Accordingly, the gate structure230ahas more work function metal layers than the gate structure230c.

In some embodiments, the gate metals GM of the gate structures230a,230cmay include tungsten (W). In some other embodiments, the gate metals GM include aluminum (Al), copper (Cu) or other suitable conductive material.

In some embodiments, the source/drain structures260N,260P may be may be formed by performing an epitaxial growth process that provides an epitaxy material over the substrate210, and thus the source/drain structures260N,260P can also be interchangeably referred to as epitaxy structures260N,260P in this context. In various embodiments, the source/drain structures260N,260P may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SIP, or other suitable material. In some embodiments, the source/drain structures260N may include N-type impurities, while the source/drain structures260P may include P-type impurities.

In some embodiments, the CESL265includes silicon nitride, silicon oxynitride or other suitable materials. The CESL265can be formed using, for example, plasma enhanced CVD, low pressure CVD, ALD or other suitable techniques. The ILD layer270may include a material different from the CESL265. In some embodiments, the ILD layer270may include silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. The ILD layer270may be formed using, for example, CVD, ALD, spin-on-glass (SOG) or other suitable techniques.

Reference is made toFIGS.2A to2D, in whichFIG.2Dis an enlarged view of memory cell200aofFIG.2A. In some embodiments, the gate structure230band the gate spacers240b, the gate structure230eand the gate spacers240e, and the gate structure230fand the gate spacers240fhave similar or the same structure as gate structure230aand gate spacers240adescribed inFIG.2B, respectively. On the other hand, the gate structure230dand the gate spacers240dhave similar or the same structure as gate structure230cand gate spacers240cdescribed inFIG.2C, respectively. For example, each of the gate structures230b,230e, and230fincludes a gate dielectric layer GD, a work function metal layer WFM1, a work function metal layer WFM2, and a gate metal GM, and the gate structure230dincludes a gate dielectric layer GD, a work function metal layer WFM1, and a gate metal GM.

With respect to the gate structures230aand230c, the gate structure230aextends continuously from the gate structures230c. In greater detail, the gate dielectric layer GD of the gate structure230aand the gate dielectric layer GD of the gate structure230care continuous material, the work function metal layer WFM1 of the gate structure230aand the work function metal layer WFM1 are continuous material, and the gate metal GM of the gate structure230aand the gate metal GM of the gate structure230care continuous material. This is because such elements of gate structures230a,230care formed at the same time, which will be discussed later. Accordingly, the combination of the gate structures230a,230ccan also be regarded as a single gate structure, in which the gate structures230a,230ccan be referred to as first and second portions of the single gate structure. In some embodiments, the gate structures230a,230cin combination form a stepped sidewall profile.

Further, the gate spacers240aand the gate spacers240care continuous material, as they are formed at the same time. That is, there is no interface between each gate spacer240aand its adjacent gate spacer240c. Accordingly, the combination of each gate spacer240aand its adjacent gate spacer240ccan also be regarded as a single gate spacer, in which the gate spacers240a,240ccan be referred to as first and second portions of the single gate spacer. In some embodiments, in a top view ofFIG.2D, the outer sidewall of the gate spacer240a(i.e., sidewall farthest from the gate structure230a) is aligned (coterminous) with and contacts the outer sidewall of the gate spacer240c(i.e., sidewall farthest from to the gate structure230c). On the other hand, in a top view ofFIG.2D, the inner sidewall of the gate spacer240a(i.e., sidewall closest to the gate structure230a) is misaligned with the inner sidewall of the gate spacer240c(i.e., sidewall closest to the gate structure230c). This is also in consistent with that the gate spacers240aand240chave different widths, as described inFIGS.2B and2C. In some embodiments, the gate spacers240a,240cin combination form a stepped sidewall profile.

As the inner sidewall of the gate spacer240ais misaligned with the inner sidewall of the gate spacer240c, although the gate dielectric layer GD of the gate structure230aand the gate dielectric layer GD of the gate structure230care continuous material, the gate dielectric layer GD of the gate structure230ais misaligned with the gate dielectric layer GD of the gate structure230c, as well as the work function metal layers WFM1 of the gate structures230a,230c. In some embodiments, in the top view ofFIG.2D, the gate metal GM of the gate structure230ahas a first portion GM-1 and a second portion GM-2, in which the second portion GM-2 is narrow than the first portion GM-1 along the lengthwise direction of the semiconductor fin220bas well as the direction perpendicular to the lengthwise direction of the semiconductor fin220b. On the other hand, along the lengthwise direction of the semiconductor fin220b, the gate metal GM of the gate structure230cis wider than the second portion GM-2 of the gate metal GM of the gate structure230aand is narrower than the first portion GM-1 of the gate metal GM of the gate structure230a. In some embodiments, the second portion GM-2 of the gate metal GM of the gate structure230acontacts the gate metal GM of the gate structure230c. In some embodiments, the gate dielectric layer GD of the gate structure230acontacts a longitudinal end of the gate structure230c.

In some embodiments, the above discussed relationships between gate structures230aand230cand between gate spacers240aand240ccan also be found at gate structures230fand230d, and gate spacers240fand240d, which will not be repeated for brevity.

With respect to the gate structures230band230d, there is an isolation structure250between and contacts the gate structures230band230d. The isolation structure250substantially extends along a border between the P-well region212and the N-well region216. In the top view ofFIG.2Dand along the lengthwise direction of the semiconductor fin220b, the interface between the gate structure230band the isolation structure250is longer than the interface between the gate structure230dand the isolation structure250, while the interface between the gate spacer240band the isolation structure250is shorter than the interface between the gate spacer240dand the isolation structure250. However, the total thickness of the gate structure230band the gate spacers240bon opposite sides of the gate structure230bis substantially equal to the total thickness of the gate structure230dand the gate spacers240don opposite sides of the gate structure230d. Although the gate structures230band230dare separated by the isolation structure250, the outer sidewall of the gate spacer240bis substantially aligned with the outer sidewall of the gate spacer240d, and the inner sidewall of the gate spacer240bis misaligned with the inner sidewall of the gate spacer240d.

In some embodiments, the above discussed relationships between gate structures230band230dand between gate spacers240band240dcan also be found at gate structures230eand230c, and gate spacers240eand240c, which will not be repeated for brevity.

FIGS.3to21Billustrate a method in various stages of fabricating a memory device in accordance with some embodiments of the present disclosure.

Reference is made toFIG.3. A plurality of semiconductor fins220a,220b,220c,220d,220e, and220fare formed over a substrate210. The semiconductor fins220a-220fmay be formed, for example, by patterning and etching the substrate210using photolithography techniques. In some embodiments, the substrate210includes a plurality of P-well regions212,214and a plurality of N-well regions216. In some embodiments, the P-well regions212,214are implanted with P-type dopant material, such as boron ions, and the N-well regions216are implanted with N-type dopant material such as arsenic ions. During the implantation of the P-well regions212,214, the N-well regions216are covered with masks (such as photoresist), and during implantation of the N-well regions216, the P-well regions212,214are covered with masks (such as photoresist).

Reference is made toFIGS.4A to4C, in whichFIG.4Bis a cross-sectional view along line B-B ofFIG.4A, andFIG.4Cis a cross-sectional view along line C-C ofFIG.4A. Portions of the semiconductor fins220cand220dare removed. For example, a photomask (not shown) is formed over the substrate210and exposes portions of the semiconductor fins220cand220d, followed by an etching process to remove the exposed portions of the semiconductor220cand220d. The resulting structure is shown inFIG.4A. After the etching process, the photomask may be removed. The etching process at this step can be interchangeably referred to as a fin cut process.

Reference is made toFIGS.5A to5C, in whichFIG.5Bis a cross-sectional view along line B-B ofFIG.5A, andFIG.5Cis a cross-sectional view along line C-C ofFIG.5A. It is noted that some elements inFIGS.5B and5Care not illustrated inFIG.5Afor simplicity. A plurality of gate dielectric layers232and a plurality of dummy gate layers234are formed over the substrate210and cross the semiconductor fins220a-220f. In some embodiments the gate dielectric layers232and the dummy gate layers234can be collectively referred to as dummy gate structure.

The gate dielectric layers232may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. The gate dielectric layers232may be formed by suitable process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any suitable process. The dummy gate layers234may be deposited over the gate dielectric layers232and then planarized, such as by a CMP. The dummy gate layers234may include polycrystalline-silicon (poly-Si) or poly-crystalline silicon-germanium (poly-SiGe). Further, the dummy gate layers234may be doped poly-silicon with uniform or non-uniform doping. The dummy gate layers234may be formed by suitable process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any suitable process.

Reference is made toFIGS.6A to6C, in whichFIG.6Bis a cross-sectional view along line B-B ofFIG.6A, andFIG.6Cis a cross-sectional view along line C-C ofFIG.6A. A plurality of gate spacers240are formed on opposite sidewalls of the dummy gate layers234. The gate spacers240may be formed by, for example, depositing a spacer layer blanket over the dummy gate layers234, followed by an anisotropic etching process to remove horizontal portions of the spacer layer, such that vertical portions of the spacer layer remain on sidewalls of the dummy gate layers234. In some embodiments, the gate spacers240may be formed by CVD, SACVD, flowable CVD, ALD, PVD, or other suitable process. In some embodiments, the thickness T1 of the gate spacers240is in a range of about 1.5 nm to about 4 nm.

Reference is made toFIGS.7A and7B, in whichFIGS.7A and7Bfollow the cross-section ofFIGS.6B and6C. A plurality of source/drain structures260N,260P are formed over the semiconductor fins220band220cof the substrate210, respectively. For example, the exposed portions of the semiconductor fins220band220cexposed by the dummy gate layers234and the gate spacers240are recessed by suitable process, such as etching. Afterwards, the source/drain structures260are formed respectively over the exposed surfaces of the remaining semiconductor fins2206and220c. The source/drain structures260N,260P may be formed by performing an epitaxial growth process that provides an epitaxy material over the semiconductor fins220band220c. In some embodiments, the source/drain structures260N may include N-type impurities, while the source/drain structures260P may include N-type impurities. It is understood that, although not shown inFIGS.7A and7B, the source/drain structures260N are also formed in the semiconductor fins220a,220e, and220f, and the source/drain structures260P are also formed in the semiconductor fins220das shown inFIG.6A.

Reference is made toFIGS.8A and8B, in whichFIGS.8A and8Bfollow the cross-section ofFIGS.7A and7B. A contact etch stop layer (CESL)265and an interlayer dielectric (ILD) layer270are formed over the substrate210and over the source/drain structures260. For example, a CESL material and a ILD material may be deposited sequentially over the substrate210, followed by a CMP process to remove excessive CESL material and ILD material until the top surfaces of the dummy gate layers234are exposed. The CESL265can be formed using, for example, plasma enhanced CVD, low pressure CVD, ALD or other suitable techniques. The ILD layer270may be formed using, for example, CVD, ALD, spin-on-glass (SOG) or other suitable techniques.

Reference is made toFIGS.9A to9C, in whichFIG.9Bis a cross-sectional view along line B-B ofFIG.9A, andFIG.9Cis a cross-sectional view along line C-C ofFIG.9A. The dummy gate layers234are removed. In some embodiments, the dummy gate layers234may be removed by suitable process, such as etching. After the dummy gate layers234are removed, a gate trench G1 is formed between the gate spacers240over the semiconductor fin220b, and a gate trench G2 is formed between the gate spacers240over the semiconductor fin220c. In some embodiments, the gate dielectric layers232remain after removing the dummy gate layers234, such that the gate dielectric layers232are exposed by the trenches G1 and G2.

Reference is made toFIGS.10A to10C, in whichFIG.10Bis a cross-sectional view along line B-B ofFIG.10A, andFIG.10Cis a cross-sectional view along line C-C ofFIG.10A. A mask layer M1 is formed over the substrate210, in which the mask layer M1 exposes the P-well regions212,214of the substrate210and covers the N-well regions216of the of the substrate210. In greater detail, the mask layer M1 covers the semiconductor fins220c,220d, while exposes the semiconductor fins220a,220b,220e,220f. As shown inFIGS.9B and9C, the trench G2 over the semiconductor fin220cis filled with the mask layer M1, and thus the gate dielectric layer232within the trench T2 over the semiconductor fin220cis covered by the mask layer M1. In some embodiments, the mask layer M1 may be photoresist, and may be formed by suitable photolithography process.

Reference is made toFIGS.11A to11C, in whichFIG.11Bis a cross-sectional view along line B-B ofFIG.11A, andFIG.11Cis a cross-sectional view along line C-C ofFIG.11A. The gate dielectric layer232exposed by the gate trench GL over the semiconductor fin220bis removed, and the gate spacers240over the semiconductor fin220bare thinned. In greater detail, the gate dielectric layer232over the semiconductor fins220a,220b,220e,220fwithin the P-well regions212,214are removed, and the gate spacers240over the semiconductor fins220a,220b,220e,220fwithin the P-well regions212,214are thinned (seeFIG.11A). On the other hand, the gate dielectric layers232and gate spacers240over the semiconductor fins220c,220dwithin the N-well regions216are protected by the mask layer M1. In some embodiments, the gate dielectric layer232can be removed by suitable process, such as etching. For example, the etchant for etching the gate dielectric layer232may be HF.

InFIG.11B, during etching the gate dielectric layer232, the gate spacers240may also be etched by some amounts using the same etchant. For example, the gate spacers240may have original thickness T1 (seeFIG.10B), and the etched gate spacers240may have thickness T2. In some embodiments, the thickness T2 is lower than the thickness T1. The difference between thicknesses T1 and T2 is the thickness loss during the etching process described inFIGS.11A to11C. In some embodiments, the thickness loss (e.g., T1-T2) is in a range from about 0.5 nm to about 3 nm. As the gate spacers240over the semiconductor fin220bare etched, the etched gate spacers240over the semiconductor fin220bare thinner than the gate spacers240over the semiconductor fin220cthat is protected by the mask layer M1 (seeFIG.11C), in which gate spacers240over the semiconductor fin220cremain their original thickness T1.

Reference is made toFIGS.12A to12C, in whichFIG.12Bis a cross-sectional view along line B-B ofFIG.12A, andFIG.12Cis a cross-sectional view along line C-C ofFIG.12A. The mask layer M1 is removed. In some embodiments, the mask layer M1 can be removed by suitable process, such as stripping. As a result, the gate dielectric layer232over the semiconductor fin220cis exposed by the gate trench G2. It is noted that in this stage, the top surface of the semiconductor fin220bis free of coverage of the gate dielectric layer232, because the gate dielectric layer232on the top surface of the semiconductor fin220bhas been removed.

Reference is made toFIGS.13A to13C, in whichFIG.13Bis a cross-sectional view along line B-B ofFIG.13A, andFIG.13Cis a cross-sectional view along line C-C ofFIG.13A. The gate dielectric layer232exposed by the gate trench G2 over the semiconductor fin220bis removed, and the gate spacers240over the semiconductor fins220band220care thinned. In greater detail, the gate dielectric layer232over the semiconductor fins220cand220dwithin the N-well regions216are removed. On the other hand, the gate spacers240over the semiconductor fins220a-220fwithin either the P-well regions212,214or the N-well region216are thinned in this step. In some embodiments, the gate dielectric layer232can be removed by suitable process, such as etching. For example, the etchant for etching the gate dielectric layer232may be HF In some embodiments, the etchant used in the process ofFIGS.13A to13Cis similar or the same as the etchant used in the process ofFIGS.11A to11C.

The resulting structures of the etching process are shown inFIGS.13A to13C. InFIG.13A, the etched gate spacers240over the semiconductor fins220a,220b,220c,220d,220e,220fare referred to as gate spacers240a,240b,240c,240d,240e,240f, as labeled inFIGS.2A to2D.

InFIG.11B, during etching the gate dielectric layer232over the semiconductor tin220c(seeFIG.12C), the gate spacers240bmay also be etched by some amounts using the same etchant, because the gate spacers240bare exposed to the etchant of the etching process. For example, the gate spacers240binFIG.12Bmay have thickness T2, and the etched gate spacers240binFIG.13Bmay have thickness T3. In some embodiments, the thickness T3 is lower than the thickness T2. The difference between thicknesses T3 and T2 is the thickness loss during the etching process described inFIGS.13A to13C. In some embodiments, the thickness loss (e.g., T2-T3) is in a range from about 0.5 nm to about 3 nm. In some embodiments, the thickness loss of the gate spacer240bduring the etching process ofFIGS.11A to11Chas a first value (e.g., T1-T2), and the thickness loss of the gate spacer240bduring the etching process ofFIGS.13A to13Chas a second value, in which the first value is greater than the second value. For example, the ratio of the first value to the second value is in a range from about 2:1 to about 4:1. That is, gate spacers240bare etched by more amounts in the etching process ofFIGS.11A to11Cthan in the etching process ofFIGS.13A to13C. This is because the etching process ofFIGS.11A to11Cis used to generate thickness difference between the gate spacers240band240c. In some embodiments, the duration of the etching process of the etching process ofFIGS.11A to11Cmay be longer than the duration of the etching process of the etching process ofFIGS.13A to13C, so as to etch more amounts of the gate spacers240bin the etching process ofFIGS.11A to11C.

InFIG.11C, during etching the gate dielectric layer232, the gate spacers240cmay also be etched by some amounts using the same etchant. For example, the gate spacers240cmay have original thickness T1 (seeFIG.12C), and the etched gate spacers240cmay have thickness T4. In some embodiments, the thickness T4 is lower than the thickness T1. The difference between thicknesses T1 and T4 is the thickness loss during the etching process described inFIGS.13A to13C. In some embodiments, the thickness loss (e.g., T1-T4) is in a range from about 0.5 nm to about 3 nm.

In some embodiments, the thickness T3 of the gate spacers240bis in a range from about 0.5 nm to about 3 nm. If the thickness13is too low (e.g., much lower than 0.5 nm), the gate spacers240bcannot provide sufficient isolation to the gate structure formed in later steps (e.g., the gate structure230bofFIGS.16A to16C). In some embodiments, the ratio of thickness T4 to thickness is in a range from about 1 to about 4. If the ratio is too high, it indicate the gate spacers2406may be too thin and cannot provide sufficient isolation. If the ratio is too low, it indicate the gate spacers240bmay be too thick and cannot provide sufficient difference from the gate spacers240c.

Reference is made toFIGS.14A and14B, in whichFIGS.14A and14Bfollow the cross-sections ofFIGS.13B and13C. A gate dielectric layer GD, a work function metal layer WFM1, a work function metal layer WFM2 are formed over the substrate210and fill the gate trenches G2 and G1. The gate dielectric layers GD may be formed by a deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma enhanced CVD (PECVD) or other suitable techniques. The work function metal layers WFM1 and WFM2 can be formed by suitable process, such as ALD, CVD, PVD, remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), metal organic CVD (MOCVD), sputtering, plating, other suitable processes, or combinations thereof.

Reference is made toFIGS.15A and15B, in whichFIGS.15A and15Bfollow the cross-sections ofFIGS.14A and14B. A mask layer M2 is formed over the substrate210, in which the mask layer M2 covers the semiconductor fin220b(e.g., P-well regions212), and does not cover the semiconductor fin220c(e.g., N-well regions216) Then, the work function metal layer WFM2 over the semiconductor fin220c(seeFIG.14B) is removed. The work function metal layer WFM2 over the semiconductor fin220ccan be removed by suitable etching process, such as dry etching or wet etching.

Reference is made toFIGS.16A to16C, in whichFIG.16Bis a cross-sectional view along line B-B ofFIG.16A, andFIG.16Cis a cross-sectional view along line C-C ofFIG.16A. The mask layer M2 is removed. A gate metal GM is formed over the substrate210, followed by a CMP process to remove excessive gate metal GM, work function metal layer WFM2, work function metal layer WFM1, and the gate dielectric layer GD until top surfaces of the ILD layer270are exposed. The resulting structures are shown inFIGS.16A to16C, in which a plurality of gate structures230a,230b,230c,230d,230e,230fare formed. In greater detail, the gate structures230a,230b,230c,230d,230e,230fare respectively between the corresponding gate spacers240a,240b,240c,240d,240e,240f, as shown inFIG.16A. It is noted that the gate structures230b,230e,230fand the gate spacers240b,240e,240fhave similar or the same structures as the gate structure230aand the gate spacers240adescribed inFIG.16B, and the gate structures230dand the gate spacers240dhave similar or the same structures as the gate structure230cand the gate spacers240cdescribed inFIG.16B.

Reference is made toFIG.17. A plurality of isolation structures250are formed over the substrate210. In greater detail, in memory cell200a, an isolation structure250is formed between and contacts the gate structures230cand230e, so as to electrically isolate the gate structures230cand230e. On the other hand, an isolation structure250is formed between and contacts the gate structures230band230d, so as to electrically isolate the gate structures230band230d. Generally, the isolation structures250are formed along a border of the P-well regions212,214and the N-well region216. The isolation structures250may be formed by, for example, forming a photoresist layer over the substrate210, patterning the photoresist layer to form openings that expose portions of the gate structures230a-230f, etching the exposed portions of the gate structures230a-230fto form recesses, removing the photoresist layer, depositing a dielectric material over the substrate210and filling the recesses, followed by a CMP process until the top surfaces of the ILD layer270are exposed. In some embodiments, the isolation structures250are flowable dielectric material that can be deposited using a flowable CVD (FCVD). In some embodiments, the flowable isolation structures250may include a flowable oxide such as a flowable silicon oxide. The flowable isolation structures250is formed by using a spin on dielectric (SOD) such as a silicate, a siloxane, a methyl SilsesQuioxane (MSQ), a hydrogen SisesQuioxane (HSQ), an MSQ/HSQ, a perhydrosilazane (TCPS) or a perhydro-polysilazane (PSZ). Alternatively, the flowable isolation structures250can be formed by using a low temperature plasma chemical vapor deposition.

Due to the scaling down of transistors, device variations and leakage are increasing sharply. As the need for low power systems grows, the supply voltage (VDD) has been scaled down to reduce both dynamic and leakage power. The operation of the SRAM at lower supply voltage becomes very challenging. The minimum operating voltage, Vmin, needs to be satisfied otherwise will cause write failure, red disturb failure, access failure or retention failure. In the present disclosure, an etching process is performed to reduce thicknesses of gate spacers of an NMOS device over a P-well region, and therefore creates a wider deposition window for metal gate structure, which in turn will increase the volume of metal gate structure and will also lower the Vminof the NMOS device. Accordingly, the device performance can be improved. However, if the gate structures the N-well regions and P-well regions have the same thickness, the Vminof the NMOS device in the P-well region may be about 73% of the desired value. That is, the present disclosure can improve the Vminof the NMOS device by more than 25%.

FIGS.18A to19Billustrate a method in various stages of fabricating a memory device in accordance with some embodiments of the present disclosure.

Reference is made toFIGS.18A and18B, in whichFIGS.18A and18Bare similar toFIGS.5B and5C, where a plurality of dielectric layers332and dummy gate layers334are formed respectively over the semiconductor fins220a,220cof the substrate210. The material of the dielectric layers332and dummy gate layers334are similar or the same as the material of the dielectric layers232and dummy gate layers234described inFIGS.5B and5C. Different from the dielectric layers232and dummy gate layers234described inFIGS.5B and5C, the dielectric layers332and dummy gate layers334have tapered profile. For example, the dummy gate layers334have a width decreases when a distance from the substrate210increases. This is because when the etching process for etching the dummy gate layers334is a wet etching, etchant does not sufficiently etch the bottom of the dummy gate layers334, which results in the tapered profile (or trapezoid profile) of the dummy gate layers334.

Reference is made toFIGS.19A and19B, in whichFIGS.19A and19Bare the resulting structures when the structures ofFIGS.18A and18Bundergo the processes described inFIGS.6A to17. The resulting structures ofFIGS.19A and19Brespectively include gate structures330a,330c, and gate spacers340a,340c. The gate structures330a,330chave similar or the same structures as the gate structures230a,230cinFIGS.16B and16C, and the gate spacers340a,340chave similar or the same structures as the gate spacers340a,340cinFIGS.16B and16C, and the relationships between the gate structures330aand the gate spacers340aand between the gate structures230cand the gate spacers240care substantially the same.

As described inFIGS.18A and18B, the dummy gate layers334have tapered profile (or trapezoid profile), and this results in that the gate structures330a,330chave tapered profile, as the gate structures330a,330csubstantially inherit the profile of the dummy gate layers334. For example, the gate structures330a,330chave widths decreases when a distance from the substrate210increases. Stated another way, the gate structures330a,330chave tapered profile (or trapezoid profile).

FIGS.20A to21Billustrate a method in various stages of fabricating a memory device in accordance with some embodiments of the present disclosure.

Reference is made toFIGS.20A and20B, in whichFIGS.20A and20Bare similar toFIGS.138and13C, where the gate dielectric layer232over the semiconductor fin220cis removed, and the gate spacers240a,240care thinned. InFIG.13B, because the gate dielectric layer232over the semiconductor fin220bhas been removed inFIG.11B, and thus the top surface of the semiconductor fin220bis exposed to the etching process ofFIGS.13B and13C, and thus the semiconductor fin220bmay be etched by some amounts during the etching process ofFIGS.13B and13C. The resulting structures are shown inFIGS.20A and20B, in which a gate trench G3 is formed between the gate spacers240a, while the gate trench G3 is slightly into the semiconductor fin220b. Stated another way, the exposed surface of the semiconductor fin220bis lower than the bottommost surface of the gate spacers240a. On the other hand, a gate trench G4 is formed between the gate spacers240cinFIG.20B. In some embodiments, the gate trench G3 inFIG.20Ais deeper than the gate trench G4 inFIG.20B. This is because the etchant of the etching process would start from etching the gate dielectric layer232over the semiconductor fin220b(seeFIG.12C), and the gate dielectric layer232can protect the semiconductor fin220bfrom being etched.

Reference is made toFIGS.21A and21B, in whichFIGS.21A and21Bare the resulting structures when the structures ofFIGS.20A and20Bundergo the processes described inFIGS.14A to17. The resulting structures ofFIGS.21A and21Brespectively include gate structures430a,430c. The gate structures430a,430chave similar or the same structures as the gate structures230a,230cinFIGS.16B and16C. In some embodiments, the bottom surface of the gate structure430is lower than the bottom surface of the gate spacers240a. Moreover, the bottom surface of the gate structure430ainFIG.21Ais lower than the bottom surface of the gate structure430cinFIG.21B. In some embodiments, a bottom portion of the gate structure430ais embedded in the semiconductor fin2206, while the gate structure430cis not embedded in the semiconductor fin220c.

FIGS.22A to22Billustrate a method1000of manufacturing in accordance with some embodiments of the present disclosure. Although the method1000is illustrated and/or described as a series of acts or events, it will be appreciated that the method is not limited to the illustrated ordering or acts. Thus, in some embodiments, the acts may be carried out in different orders than illustrated, and/or may be carried out concurrently. Further, in some embodiments, the illustrated acts or events may be subdivided into multiple acts or events, which may be carried out at separate times or concurrently with other acts or sub-acts. In some embodiments, some illustrated acts or events may be omitted, and other un-illustrated acts or events may be included.

At block S101, forming plurality of semiconductor fins over a substrate.FIG.3illustrates a schematic view of some embodiments corresponding to act in block S101.

At block S102, portions of the semiconductor fins are removed.FIGS.4A to4Cillustrate schematic views of some embodiments corresponding to act in block S102.

At block S103, gate dielectric layers and dummy gate layers are formed over the substrate and crossing the semiconductor fins.FIGS.5A to5Cillustrate schematic views of some embodiments corresponding to act in block S103.

At block S104, gate spacers are formed on opposite sidewalls of the dummy gate layers.FIGS.6A to6Cillustrate schematic views of some embodiments corresponding to act in block S104.

At block S105, source/drain structures are formed over the semiconductor fins.FIGS.7A to7Billustrate schematic views of some embodiments corresponding to act in block S105.

At block S106, source/drain structures are formed over the semiconductor fins.FIGS.7A to7Billustrate schematic views of some embodiments corresponding to act in block S106.

At block S107, a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer are formed over the substrate and over the source/drain structures.FIGS.8A to8Billustrate schematic views of some embodiments corresponding to act in block S107.

At block S108, the dummy gate layers are removed.FIGS.9A to9Cillustrate schematic views of some embodiments corresponding to act in block S108.

At block S109, a first mask layer is formed over the substrate, in which the mask layer exposes P-well regions of the substrate and covers N-well regions of the substrate.FIGS.10A to10Cillustrate schematic views of some embodiments corresponding to act in block S109.

At block S110, the gate dielectric layers in the P-well regions are removed, and the gate spacers in the P-well regions are thinned.FIGS.11A to11Cillustrate schematic views of some embodiments corresponding to act in block Si10.

At block S111, the first mask layer is removed.FIGS.12A to12Cillustrate schematic views of some embodiments corresponding to act in block S111.

At block S112, the gate dielectric layers in the N-well regions are removed, and the gate spacers in the P-well regions and the N-well regions are thinned.FIGS.13A to13Cillustrate schematic views of some embodiments corresponding to act in block S112.

At block S113, a gate dielectric layer, a first work function metal layer, a second work function metal layer are formed over the substrate.FIGS.14A to14Billustrate schematic views of some embodiments corresponding to act in block S113.

At block S114, a second mask layer is formed over the substrate, in which the mask layer covers the P-well regions of the substrate, and does not cover the N-well regions of the substrate, and a portion the work function metal layer within the N-well regions of the substrate is removed.FIGS.15A to15Billustrate schematic views of some embodiments corresponding to act in block S114.

At block S115, the second mask layer is removed, and gate metal is formed over the substrate, followed by a CMP process to form metal gate structures.FIGS.16A to16Cillustrate schematic views of some embodiments corresponding to act in block S115.

At block S116, isolation structures are formed over the substrate.FIG.17illustrates a schematic view of some embodiments corresponding to act in block S115.

FIG.23illustrates simulation results of memory devices in accordance with some embodiments of the present disclosure. Conditions CN1 and CN2 illustrate simulation results of different memory devices. The difference between Conditions CN1 and CN2 is that Condition CN1 is a simulation result of a memory device having gate structures (within different regions) having the same width, while Condition CN2 is a simulation result of a memory device having gate structures (within different regions) having different width (such as the memory device discussed inFIGS.1to17). The height of the bar indicates how Vmin is close to a desired Vmin, in which the topmost point of the vertical axis indicates the desired Vmin. Comparing Condition CN1 with Condition CN2, it is clear that Condition CN2 is close to the desired Vmin.

Based on the above discussion, it can be seen that the present disclosure offers advantages. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantages is required for all embodiments. Due to the scaling down of transistors, device variations and leakage are increasing sharply. As the need for low power systems grows, the supply voltage (VDD) has been scaled down to reduce both dynamic and leakage power. The operation of the SRAM at lower supply voltage becomes very challenging. The minimum operating voltage, Vmin, needs to be satisfied otherwise will cause write failure, red disturb failure, access failure or retention failure. In the present disclosure, an etching process is performed to reduce thicknesses of gate spacers of an NMOS device over a P-well region, and therefore creates a wider deposition window for metal gate structure, which in turn will increase the volume of metal gate structure and will also lower the Vmin of the NMOS device. Accordingly, the device performance can be improved. However, if the gate structures the N-well regions and P-well regions have the same thickness, the Vmin of the NMOS device in the P-well region may be about 73% of the desired value. That is, the present disclosure can improve the Vmin of the NMOS device by more than 25%.

In some embodiments of the present disclosure, a memory device includes a substrate, first semiconductor fin, second semiconductor fin, first gate structure, second gate structure, first gate spacer, and a second gate spacer. The substrate has a P-well region and an N-well region. The first semiconductor fin is over the P-well region of the substrate. The second semiconductor fin is over the N-well region of the substrate. The first gate structure is over the P-well region of the substrate and crosses the first semiconductor fin. The second gate structure is over the N-well region of the substrate and crosses the second semiconductor fin, the first gate structure extends continuously from the second gate structure, in which in a top view of the memory device, a width of the first gate structure is greater than a width of the second gate structure. The first gate spacer is on a sidewall of the first gate structure. The second gate spacer extends continuously from the first gate spacer and on a sidewall of the second gate structure, in which in the top view of the memory device, a width of the first gate spacer is less than a width of the second gate spacer.

In some embodiments of the present disclosure, a memory device includes a substrate, an isolation structure, a first gate structure, and a second gate structure. The substrate has a P-well region and an N-well region. The isolation structure extends along a border between the P-well region and the N-well region. The first gate structure extends from a first side of the isolation structure within the P-well region. The second gate structure extends from a second side of the isolation structure within the N-well region, wherein when viewed from above, an interface between the first gate structure and the isolation structure is larger than an interface between the second gate structure and the isolation structure.

In some embodiments of the present disclosure, a memory device includes a substrate, a first semiconductor fin over the substrate, a second semiconductor fin over the substrate, a first gate structure over the substrate and crossing the first semiconductor fin, a second gate structure over the substrate and crossing the second semiconductor fin, a first gate spacer on a sidewall of the first gate structure, and a second gate spacer on a sidewall of the second gate structure. In a top view of the memory device, an outer sidewall of the first gate spacer farthest from the first gate structure is coterminous with an outer sidewall of the second gate spacer farthest from the second gate structure, and an inner sidewall of the first gate spacer closest to the first gate structure is misaligned with an inner sidewall of the second gate spacer closest to the second gate structure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.