Patent ID: 12261197

DETAILED DESCRIPTION

The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

MIM (metal-insulator-metal) capacitors may be implemented into the back-end-of-the-line (BEOL) metal interconnect layers of integrated chips. MIM capacitors typically have a top electrode and a bottom electrode separated by a capacitor dielectric layer. During formation of a MIM capacitor, a capacitor dielectric layer is formed over a bottom electrode. A top electrode film is deposited over the capacitor dielectric layer. A masking layer is formed over the top electrode film, and the top electrode film is patterned according to the masking layer, thereby forming a top electrode. A masking layer removal process is performed to remove the masking layer and a cleaning process is performed to remove by-products from the top electrode film deposition and/or the patterning process. The removal and/or cleaning processes utilize one or more chemicals from a diffusive species (e.g., oxygen (O2), hydrogen peroxide (H2O2), hydrofluoric acid (HF), dihydrofolic acid (DHF), etc.).

A challenge with the above MIM capacitor pertains to a structure of the top electrode. The top electrode film may be formed by a physical vapor deposition (PVD) process with a large thickness (e.g., 400 Angstroms), such that the top electrode has large columnar grains. The large thickness increases a structural integrity of the MIM capacitor but does so at the expense of large grain sizes. Due to the columnar grains, the diffusive species from the removal and/or cleaning processes diffuses through the top electrode (e.g., along the grain boundaries between adjacent columnar grains) to the capacitor dielectric layer. The diffusive species reacts or otherwise interacts with the capacitor dielectric layer, thereby forming voids in the capacitor dielectric layer. These voids may result in electrical breakdown of the capacitor dielectric layer, and may hence result in the top electrode electrically shorting to the bottom electrode at high operating voltages (e.g., within a range of 2.3 to 3.5 volts (V)). Such electrical shorting, in turn, leads to failure of the MIM capacitor.

Various embodiments of the present application are directed to a top electrode having a diffusion barrier layer that blocks and/or prevents the diffusion of the diffusive species. In some embodiments, a first top electrode layer is formed over the capacitor dielectric layer by a PVD process, such that the first top electrode layer comprises a first material (e.g., titanium nitride (TiN)) that has columnar grains and a first thickness (e.g., 200 Angstroms). A diffusion barrier layer is formed over the first top electrode layer by an atomic layer deposition (ALD) process, and an annealing process with a treatment species (e.g., nitrogen (N2), hydrogen (H2), a combination of the foregoing, etc.) is performed on the diffusion barrier layer. The diffusion barrier layer comprises the first material with a second thickness (e.g., 10 to 15 Angstroms). By virtue of performing the annealing process with the treatment species, the diffusion barrier layer is nitrogen rich (e.g., N-rich) and has a higher ratio of nitrogen atoms to titanium atoms than the first top electrode layer. This results in the diffusion barrier layer being at least partially crystalline with grain sizes smaller than the columnar grains of the first top electrode layer. A second top electrode layer is formed over the diffusion barrier layer by a PVD process, such that the second top electrode layer comprises the first material with columnar grains and has about the first thickness (e.g., 200 Angstroms). The aforementioned layers are patterned according to a masking layer, thereby defining the top electrode. The partially crystalline structure and small grain sizes of the diffusion barrier layer blocks diffusion of the diffusive species to the capacitor dielectric layer during subsequent removal and/or cleaning processes. Thus, the diffusion barrier layer prevents the formation of voids in the capacitor dielectric layer, thereby preventing the breakdown in the MIM capacitor at high operating volts. This, in part, increases an operating voltage, an endurance, and a reliability of the MIM capacitor.

Referring toFIG.1A, a cross-sectional view of some embodiments of a metal-insulator-metal (MIM) capacitor100ahaving a diffusion barrier layer112is provided.

The MIM capacitor100aincludes a top electrode108, a bottom electrode104, and a capacitor dielectric layer106disposed between the top and bottom electrodes108,104. The bottom electrode104overlies a substrate102. The top electrode108overlies the bottom electrode104, and has a first width W1that is smaller than a second width W2of the bottom electrode104. The top electrode108includes a first top electrode layer110a, a second top electrode layer110b, and a diffusion barrier layer112disposed between the first and second top electrode layers110a-b.

In some embodiments, the top electrode108and the bottom electrode104may be or comprise a metal nitride, such as, for example, titanium nitride, tantalum nitride, tungsten nitride, or the like. The first and second top electrode layers110a-bcomprise the metal nitride with a first ratio of nitrogen atoms to metal atoms (e.g., titanium atoms), such that the aforementioned layers have grains (e.g., columnar grains) with a first grain size. The diffusion barrier layer112comprises a metal nitride with a second ratio of nitrogen atoms to metal atoms (e.g., titanium atoms), such that the diffusion barrier layer has diffusion barrier grains (e.g., non-columnar grains) with a second grain size smaller than the first grain size. In some embodiments, the first ratio of nitrogen atoms to metal atoms is 1:1 and the second ratio of nitrogen atoms to metal atoms is 1.0x:1 (where x is within a range of about 2-5). For example, for every 100 metal atoms the first and/or second top electrode layers110a-bmay comprise 100 nitrogen atoms, whereas for every 100 metal atoms the diffusion barrier layer112may comprise 102 to 105 nitrogen atoms. Therefore, the diffusion barrier layer112is nitrogen rich (N-rich) (i.e., a greater number of nitrogen atoms than metal atoms). By virtue of the nitrogen atoms having a smaller atomic radius than the metal atoms, a distance between atoms in the diffusion barrier layer112is less than a distance between atoms in the first and/or second top electrode layers110a-b. Thus, the atoms in the diffusion barrier layer112are more densely packed together than the atoms in the first and/or second top electrode layers110a-b, leading to the diffusion barrier layer112having smaller grain sizes. In some embodiments, the atoms in the diffusion barrier layer112are so densely packed together that a diffusive species (e.g., oxygen (O2), hydrogen peroxide (H2O2), hydrofluoric acid (HF), dihydrofolic acid (DHF), etc.) is unable to travel between adjacent atoms in the diffusion barrier layer112. Therefore, the diffusion barrier layer112has more densely packed atoms, non-columnar grains, and/or an at least partially crystalline structure that contributes to an ability to block and/or mitigate diffusion of the diffusive species. This prevents the diffusive species from adversely affecting a structural integrity of the capacitor dielectric layer106, thereby mitigating degradation of the MIM capacitor100a. In some embodiments, the bottom electrode104comprises a metal nitride with the first ratio of nitrogen atoms to metal atoms, wherein the bottom electrode104has columnar grains.

For example, during a formation of the MIM capacitor100a, the first top electrode layer110ais formed over the capacitor dielectric layer106by a first deposition process (e.g., a physical vapor deposition (PVD) process). By virtue of the first deposition, the first top electrode layer110ahas first grain sizes (e.g., columnar grains). The diffusion barrier layer112is formed over the first top electrode layer110aby a second deposition process (e.g., an atomic layer deposition (ALD) process) with a second thickness (e.g., about 10-15 Angstroms). After performing the second deposition process, an annealing process with a treatment species (e.g., nitrogen (N2), hydrogen (H2), a combination of the foregoing, etc.) is performed on the diffusion barrier layer112, such that the diffusion barrier layer is rich in the treatment species (e.g., N-rich). In some embodiments, the annealing process is performed with a first treatment species (e.g., nitrogen (N2)) and a second treatment species (e.g., hydrogen (H2)), where the second treatment species facilitates implanting the first treatment species into the diffusion barrier layer. In such embodiments, the second treatment species may facilitate dissociating a molecule of the first treatment species into first treatment species atoms, such that the first treatment species atoms may be more easily implanted into the diffusion barrier layer112. This ensures the diffusion barrier layer112has second grain sizes (e.g., equiaxed gains) smaller than the first grain sizes. Further, the second top electrode layer110bis formed over the diffusion barrier layer112by the first deposition process, such that the second top electrode layer110bhas the first grain sizes. After forming the aforementioned layers, a patterning process is performed, thereby defining the top electrode108with the first width W1. Subsequently, a removal process may be performed to remove a mask (e.g., a photoresist mask) and/or a cleaning process may be performed to remove by-products from the aforementioned deposition processes and/or the patterning process.

The removal and/or cleaning processes utilize one or more chemicals from the diffusive species (e.g., oxygen (O2), hydrogen peroxide (H2O2), hydrofluoric acid (HF), etc.). In some embodiments, if the diffusive species reaches the capacitor dielectric layer106it may react or otherwise interact with the capacitor dielectric layer106, thereby forming voids in the capacitor dielectric layer106. During the removal and/or cleaning processes, the diffusive species may travel along grain boundaries of the grains in the second top electrode layer110bto the diffusion barrier layer112. However, the second grain sizes of the diffusion barrier layer112mitigate and/or block the diffusive species from reaching the capacitor dielectric layer106. Thus, the second grain sizes of the diffusion barrier layer112prevent the formation of voids in the capacitor dielectric layer106. By preventing the formation of voids in the capacitor dielectric layer106, breakdown of the capacitor dielectric layer106may not occur under high operating voltages (e.g., within a range of 2.3 to 3.5 V). Therefore, the diffusion barrier layer112increases an operating voltage (e.g., up to about 4.8 V), an endurance, and a reliability of the MIM capacitor100a.

Referring toFIG.1B, a cross-sectional view of a MIM capacitor100baccording to some alternative embodiments of the MIM capacitor100aofFIG.1Ais provided. In some embodiments, the cross-sectional view of the MIM capacitor100binFIG.1Bis an enlarged view, such that the grain sizes of the different layers are visible.

The capacitor dielectric layer106has a thickness tcrdefined in a center region of the capacitor dielectric layer106. The top electrode108overlies the center region of the capacitor dielectric layer106, such that the capacitor dielectric layer106has the thickness tcrbetween a top surface of the bottom electrode104and a bottom surface of the first top electrode layer110a. The capacitor dielectric layer106has a thickness tprdefined in a peripheral region of the capacitor dielectric layer106, such that the peripheral region surrounds the center region and is laterally offset from the top electrode108. In some embodiments, the thickness tpris less than the thickness tcr. Thus, the capacitor dielectric layer106has two discrete thicknesses. In some embodiments, the capacitor dielectric layer106may, for example, be or comprise a high κ dielectric material, such as aluminum oxide (AlxOy), zirconium oxide (ZrOx), or the like. As used herein, a high κ dielectric material is a dielectric material with a dielectric constant greater than 3.9. In yet further embodiments, the capacitor dielectric layer106comprises a plurality of dielectric materials and/or a plurality of dielectric layers. For example, the capacitor dielectric layer106may comprise a first zirconium oxide layer (e.g., ZrO2), a second zirconium oxide layer (e.g., ZrO2), and an aluminum oxide layer (e.g., Al2O3) disposed between the first and second zirconium oxide layers (not shown).

The first top electrode layer110acomprises a plurality of grains114. For ease of illustration, only some of the grains114are labeled114. The grains114define grain boundaries that may extend from an upper surface of the capacitor dielectric layer106to a lower surface of the diffusion barrier layer112. In some embodiments, the grains114are columnar grains, and a first grain may have a different area and/or width than a second grain. For example, a first grain114amay have a greater width and/or area than a second grain114b. In some embodiments, the first top electrode layer110amay, for example, be or comprise a first material, such as titanium nitride, tantalum nitride, tungsten nitride, or the like and/or may have a maximum thickness taof about 100 Angstroms, 200 Angstroms, or within a range of about 100 to 200 Angstroms.

The second top electrode layer110bcomprises a plurality of grains116. For ease of illustration, only some of the grains116are labeled116. The grains116define grain boundaries that may extend from an upper surface of the diffusion barrier layer112to a point above the upper surface of the diffusion barrier layer112. In some embodiments, the grains116are columnar grains, and a first grain may have a different area and/or width than a second grain. For example, a first grain116amay have a greater width and/or area than a second grain116b. In some embodiments, a grain boundary of the first grain116aof the second top electrode layer110bis laterally offset from a grain boundary of the first grain114aof the first top electrode layer110aby a distance d1. In some embodiments, the distance d1is non-zero. Thus, the grains116of the second top electrode layer110band the grains114of the first top electrode layer110amay both be columnar grains with different layouts and/or different grain boundary locations. In such embodiments, the distance d1being non-zero increases an ability for the top electrode108to prevent diffusion of the diffusive species to the capacitor dielectric layer106. The distance d1may act as another barrier in place of the diffusive species. For example, in some embodiments, the diffusive species may vertically diffuse through the first top electrode layer110aand the diffusion barrier layer112. In such embodiments, the shifted grain boundaries (e.g., due to the distance d1) between the first and second top electrode layers110a-bmay require the diffusive species to laterally diffuse before it could vertically diffuse through the second top electrode layer110b. Thus, the shifted grain boundaries between the first and second electrode layers110a-bincrease an ability to mitigate and/or block diffusion of the diffusive species.

In some embodiments the second top electrode layer110bcomprises the first material, such that the first and second top electrode layers110a-bcomprise a same material. In some embodiments, the second top electrode layer110bmay, for example, be or comprise titanium nitride, tantalum nitride, tungsten nitride, or the like and/or may have a maximum thickness tbof about 100 Angstroms, 200 Angstroms, or within a range of about 100 to 200 Angstroms. In some embodiments, the maximum thickness taof the first top electrode layer110ais equal to the maximum thickness tbof the second top electrode layer110b.

The diffusion barrier layer112is between the first and second top electrode layers110a-band has diffusion barrier grains118. Box A illustrates an enlarged view of the diffusion barrier layer112, such that the diffusion barrier grains118may be more easily illustrated. In some embodiments, an entirety of the diffusion barrier layer112comprises the diffusion barrier grains118. For ease of illustration, only some of the diffusion barrier grains118are labeled118. In some embodiments, the diffusion barrier grains118are smaller than the grains114of the first top electrode layer110aand/or the grains116of the second top electrode layer110b. The diffusion barrier grains118may, for example, be equiaxed grains and/or non-columnar grains. In further embodiments, the diffusion barrier layer112may have a partially crystalline structure. In the aforementioned embodiments, the diffusion barrier grains118have a grain size smaller than the grains114of the first top electrode layer110aand/or the grains116of the second top electrode layer110b.

The smaller grain sizes of the diffusion barrier grains118(in relation to the grains116) allow the diffusion barrier grains118to be more densely packed together, hence the diffusion barrier grains118have smaller grain boundaries than the grains116. In some embodiments, the grain sizes are small enough to block and/or mitigate diffusion of the diffusive species. Therefore, the diffusion barrier layer112is configured to block and/or mitigate diffusion of a diffusive species to the capacitor dielectric layer106. The diffusive species may, for example, be or comprise oxygen (O2), hydrogen peroxide (H2O2), hydrofluoric acid (HF), dihydrofolic acid (DHF), a combination of the aforementioned, or the like. In some embodiments, the diffusive species may travel along the grain boundaries of the grains116of the second top electrode layer110bto the diffusion barrier layer112. However, the diffusive species may be unable to enter the diffusion barrier layer112and/or travel along grain boundaries of the diffusion barrier grains118. Thus, the diffusion barrier layer112blocks the diffusive species from reaching the capacitor dielectric layer106. In further embodiments, the diffusion barrier layer112comprises titanium nitride with a higher concentration of nitrogen than titanium.

The diffusion barrier layer112has a thickness tdbthat is smaller than the maximum thickness taof the first top electrode layer110aand/or the maximum thickness tbof the second top electrode layer110b. For example, the thickness tbdis within a range of about 10 to 15 Angstroms. In some embodiments, if the thickness tbdis less than 10 Angstroms, then the diffusion barrier layer112may be unable to block diffusion of the diffusive species, thereby resulting in breakdown of the capacitor dielectric layer106under high operating voltages (e.g., within a range of 2.3 to 3.5 V). In yet another embodiment, if the thickness tbdis greater than 15 Angstroms, then time and costs associated with forming the diffusion barrier layer112may be increased. The first top electrode layer110a, the second top electrode layer110b, and the diffusion barrier layer112may comprise a same material (e.g., TiN). In some embodiments, the diffusion barrier layer112may, for example, be or comprise titanium nitride, tantalum nitride, tungsten nitride, tungsten, nickel, titanium, tantalum, zirconium, nickel chromium, palladium, or the like. In some embodiments, a maximum thickness of the diffusion barrier layer112is about 20, 15, 13, or within a range of 10-20 times less than a maximum thickness taof the first top electrode layer110aand/or a maximum thickness tbof the second top electrode layer110b.

In some embodiments, the diffusion barrier grains118are small grains with approximately equal dimensions. In some embodiments, a diffusion barrier grain118has approximately equal dimensions if all dimensions of the diffusion barrier grains118(e.g., height H, width W, and depth D) are within about 30, 20, or 10 percent of the average of the dimensions (e.g., (H+W+D)/3). In some embodiments, one, some, or all of the dimensions of the diffusion barrier grains118is/are between about 1-4.5 nanometers, about 2.5-4.5 nanometers, or about 0.5-2.5 nanometers. For example, a maximum dimension of the diffusion barrier grains118may be between one of these ranges. Further, in some embodiments, one (e.g., a maximum dimension), some, or all of the dimensions of the diffusion barrier grains118is/are less than about 4 or 4.5 nanometers. For example, a maximum dimension of the diffusion barrier grains118may be less than one or more of these thresholds.

Referring toFIG.1C, a cross-sectional view of a MIM capacitor100caccording to some alternative embodiments of the MIM capacitor100bofFIG.1Bis provided. The diffusion barrier layer112has a rough bottom surface that conforms to a rough upper surface of the first top electrode layer110a. In some embodiments, the upper surface of the first top electrode layer110acomprises a plurality of protrusions and the bottom surface of the diffusion barrier layer112comprises a plurality of recesses that adjoin the protrusions of the first top electrode layer110a. Further, a sidewall of the second top electrode layer110bis laterally offset from a sidewall of the diffusion barrier layer112by a distance d2. In some embodiments, the distance d2is non-zero.

Referring toFIG.2A, a cross-sectional view of some embodiments of a metal-insulator-metal-insulator-metal (MIMIM) capacitor200aincluding a top electrode108with a diffusion barrier layer112and a middle electrode202comprising a middle electrode diffusion barrier layer206is provided.

A bottom electrode104overlies a substrate102. A capacitor dielectric layer106overlies the substrate102and the bottom electrode104. The capacitor dielectric layer106continuously extends over a sidewall and an upper surface of the bottom electrode104. A middle electrode202extends over an upper surface of the capacitor dielectric layer106and overlies a portion of the bottom electrode104. The middle electrode202is separated from the bottom electrode104by the capacitor dielectric layer106.

The middle electrode202comprises a first middle electrode layer204a, a second middle electrode layer204b, and a middle electrode diffusion barrier layer206disposed between the first and second middle electrode layers204a-b. In some embodiments, the middle electrode202is configured as the top electrode108ofFIGS.1A-1C, such that the middle electrode diffusion barrier layer206is configured to block and/or mitigate diffusion of a diffusive species (e.g., oxygen (O2), hydrogen peroxide (H2O2), hydrofluoric acid (HF), etc.) to the capacitor dielectric layer106. Further, the first and second middle electrode layers204a-bmay each have columnar grains and the middle electrode diffusion barrier layer206has grains smaller than the columnar grains. In further embodiments, the middle electrode diffusion barrier layer206comprises titanium nitride with a high concentration of nitrogen, such that the middle electrode diffusion barrier layer206is at least partially crystalline. In the aforementioned embodiment, the at least partially crystalline structure of the middle electrode diffusion barrier layer206blocks and/or mitigates diffusion of the diffusive species. In yet further embodiments, the middle electrode diffusion barrier layer206comprises equiaxed grains.

An upper capacitor dielectric layer208overlies an upper surface of the middle electrode202. In some embodiments, the upper capacitor dielectric layer208comprises a same material as the capacitor dielectric layer106. In some embodiments, the upper capacitor dielectric layer208may, for example, be or comprise a high κ dielectric material, such as aluminum oxide (AlxOy), zirconium oxide (ZrOx), or the like. In yet further embodiments, the upper capacitor dielectric layer208comprises a plurality of dielectric materials and/or a plurality of dielectric layers. For example, the upper capacitor dielectric layer208may comprise a first zirconium oxide layer (e.g., ZrO2), a second zirconium oxide layer (e.g., ZrO2), and an aluminum oxide layer (e.g., Al2O3) disposed between the first and second zirconium oxide layers (not shown).

The top electrode108overlies the upper capacitor dielectric layer208and the capacitor dielectric layer106. The top electrode108is configured as the top electrode108ofFIGS.1A-1C, such that the diffusion barrier layer112is disposed between the first and second top electrode layers110a-b. The diffusion barrier layer112is configured to block and/or mitigate diffusion of the diffusive species to the upper capacitor dielectric layer208and/or the capacitor dielectric layer106. In some embodiments, the top electrode108is separated from the middle electrode202by the upper capacitor dielectric layer208, and the top electrode108is separated from the middle electrode by the capacitor dielectric layer106.

Referring toFIG.2B, a cross-sectional view200bof a portion of the MIMIM capacitor200aofFIG.2Aas indicated by the dashed box inFIG.2Ais provided.

The first middle electrode layer204acomprises a plurality of grains204agthat may, for example, be columnar grains that create grain boundaries extending from the capacitor dielectric layer106to the middle electrode diffusion barrier layer206. The second middle electrode layer204bcomprises a plurality of grains204bgthat may, for example, be columnar grains that create grain boundaries extending from the middle electrode diffusion barrier layer206to the upper capacitor dielectric layer208. The middle electrode diffusion barrier layer206may, for example, comprises diffusion barrier grains (not shown) that are smaller than the grains204agand/or the grains204bg. In some embodiments, the diffusion barrier grains of the middle electrode diffusion barrier layer206may be configured as the diffusion barrier grains118ofFIG.1B. The top electrode108overlies the upper capacitor dielectric layer208and is configured as the top electrode108ofFIGS.1A-C.

Referring toFIG.2C, a cross-sectional view200cof an alternative embodiment ofFIG.2Bis provided, in which the first middle electrode layer204acomprises a plurality of protrusions that adjoin a plurality of recesses of the middle electrode diffusion barrier layer206. The second middle electrode layer204bcomprises a plurality of protrusions that adjoin a plurality of recesses of the upper capacitor dielectric layer208. Further, the first top electrode layer110acomprises a plurality of protrusions that adjoin a plurality of recesses of the diffusion barrier layer112.

Referring toFIG.2D, a cross-sectional view200dof a portion of the MIMIM capacitor200aofFIG.2Aas indicated by the dashed box inFIG.2Ais provided, in which the capacitor dielectric layer106comprises a lower dielectric layer210, a middle dielectric layer212, and an upper dielectric layer214. The middle dielectric layer212is disposed between the upper and lower dielectric layers214,210. In some embodiments, the upper and lower dielectric layers214,210may respectively comprise zirconium oxide and the middle dielectric layer212may comprise aluminum oxide. In further embodiments, the upper capacitor dielectric layer208is configured as the capacitor dielectric layer106inFIG.2D(not shown).

Referring toFIG.3, a cross-sectional view of some embodiments of an integrated circuit (IC)300including a metal-insulator-metal (MIM) capacitor100ais provided. The MIM capacitor100ais disposed in an interconnect structure303configured for a one-transistor one-capacitor (1T1C) setup.

The IC300includes the interconnect structure303overlying a substrate102. The substrate102may, for example, be or comprise a bulk substrate (e.g., a bulk silicon substrate) or a silicon-on-insulator (SOI) substrate. An access metal-oxide-semiconductor field-effect transistor (MOSFET)308is disposed on the substrate102. The access MOSFET308includes a pair of source/drain regions302disposed in the substrate102and laterally spaced apart. A gate dielectric304overlies the substrate102between the individual source/drain regions302, and a gate electrode306overlies the gate dielectric304. In some embodiments, the gate electrode306may, for example, be or comprise polysilicon, or another suitable conductive material. The substrate102comprises a first doping type (e.g., p-type) and the source/drain regions302comprise a second doping type (e.g., n-type) opposite the first doping type. In some embodiments, the source/drain regions302comprise a doping concentration greater than a doping concentration of the substrate102. A well region305is disposed between the source/drain regions302and comprises the first doping type with a higher doping concentration than the substrate102.

The interconnect structure303comprises a plurality of inter-level dielectric (ILD) layers314overlying the substrate102and the access MOSFET308. The ILD layers314may comprise one or more ILD materials. In some embodiments, the one or more ILD materials may, for example be a low κ dielectric material, an oxide (e.g., silicon dioxide), a combination of the aforementioned, or another suitable dielectric material. As used herein, a low κ dielectric material is a dielectric material with a dielectric constant less than 3.9. A plurality of conductive wires312and conductive vias310are stacked within the ILD layers314and are configured to provide electrical connections between various devices (e.g., the access MOSFET308and/or the MIM capacitor100a) disposed throughout the IC300. In some embodiments, the conductive wires312and/or the conductive vias310may, for example, be or comprise copper, aluminum, or some other conductive material.

The MIM capacitor100ais disposed in an upper ILD layer314u. The MIM capacitor100aincludes a top electrode108, a bottom electrode104, and a capacitor dielectric layer106disposed between the top and bottom electrodes108,104. A plurality of upper vias316a-celectrically couple the MIM capacitor100ato the underlying conductive wires312. The plurality of upper vias316a-care electrically coupled to upper wires318a-c. In some embodiments, a first upper wire318ais electrically coupled to a second upper wire318bby way of a connector320(which is schematically illustrated for each of illustration). In some embodiments, the connector320comprises wires and/or vias overlying the MIM capacitor100a. A bottom electrode via316bextends from the second upper wire318bto a bottom electrode104of the MIM capacitor100aand a top electrode via316cextends from a third upper wire318cto the top electrode108of the MIM capacitor100a. In some embodiments, the MIM capacitor100ais configured as the MIM capacitor100aofFIGS.1A-C.

In some embodiments, the gate electrode306is electrically coupled to a word line (WL), such that an appropriate WL voltage can be applied to the gate electrode306to electrically couple the MIM capacitor100ato a bit line (BL) and source line (SL). The SL is electrically coupled to a source/drain region302and the BL is electrically coupled to another source/drain region302by way of the interconnect structure303and the MIM capacitor100a. Thus, in some embodiments, an output of the BL and/or the MIM capacitor100amay be accessed at the SL upon application of the appropriate WL voltage. In further embodiments, a voltage may be applied at a transistor body node301that is electrically coupled to the well region305(i.e., a body of the access MOSFET308) disposed under the gate electrode306. The voltage applied at the transistor body node301may be configured to assist in controlling a conductive channel formed in the well region305.

Referring toFIG.4, a circuit diagram400of some embodiments of the IC300ofFIG.3is provided.

As illustrated inFIG.4, the SL is electrically coupled to a first source/drain region of the access MOSFET308. A WL is electrically coupled to a gate electrode of the access MOSFET308, and a second source/drain region of the access MOSFET308is electrically coupled to the MIM capacitor100a. The bottom electrode104is configured as a first plate100p1of the MIM capacitor100a, and the top electrode108is configured as a second plate100p2of the MIM capacitor100a, such that the first plate100p1is parallel to the second plate100p2. In some embodiments, the capacitor dielectric layer (106ofFIG.3) is disposed between the first and second plates100p1,100p2. In some embodiments, the first plate100p1is electrically coupled to the second source/drain region of the access MOSFET308, and the second plate100p2is electrically coupled to a BL.

Referring toFIG.5, a cross-sectional view of an IC500according to some alternative embodiments of the IC300ofFIG.3is provided, in which a bonding structure505overlies the interconnect structure303.

The access MOSFET308includes source/drain regions302, a gate electrode306, and a gate dielectric304. The source/drain regions302are disposed between an isolation structure502that extends from an upper surface of the substrate102to a point below the upper surface of the substrate102. In some embodiments, the isolation structure502is configured as a shallow trench isolation (STI) structure and comprises one or more dielectric materials (e.g., silicon dioxide). The access MOSFET308further includes a sidewall spacer structure504surrounding the gate electrode306and the gate dielectric304. At least a portion of the sidewall spacer structure504overlies the source/drain regions302.

The bonding structure505overlies the interconnect structure303and the MIM capacitor100a. The bonding structure505includes a first passivation layer510, a second passivation layer512, a top dielectric structure514, a bump structure515, a redistribution layer508, and a redistribution via506. The redistribution layer508is disposed within the second passivation layer512. The redistribution via506is disposed within the first passivation layer510and extends from the redistribution layer508to a first upper wire318a. Thus, the redistribution layer508is electrically coupled to the MIM capacitor100a. The bump structure515extends through the top dielectric structure514and contacts the redistribution layer508. The bump structure515includes a bond pad516, a bond bump518, and a solder ball520. The bump structure515is electrically coupled to the interconnect structure303by way of the redistribution layer508. In some embodiments, the bump structure515is configured to electrically couple the IC500to another IC (not shown).

Referring toFIG.6, a cross-sectional view600of some alternative embodiments of a portion of the IC500ofFIG.5, as indicated by the dashed box inFIG.5is provided.

As illustrated inFIG.6, the MIM capacitor100ais disposed within an ILD layer314and overlies conductive wires312. The conductive wires312each comprise a conductive body312asurrounded by a conductive liner312b. A first upper wire318aoverlies the top electrode108and comprises one or more protrusions that directly contact the top electrode108. A second upper wire318boverlies the bottom electrode104, and comprises a protrusion that extends through the capacitor dielectric layer106and directly contacts the bottom electrode104. In some embodiments, the first and second upper wires318a-brespectively comprise the conductive body312asurrounded by the conductive liner312b. In some embodiments, the conductive body312amay, for example, be or comprise aluminum, copper, an alloy of the aforementioned, or the like. In further embodiments, the conductive liner312bmay, for example, be or comprise tungsten, or the like.

Referring toFIG.7, a cross-sectional view of an integrated circuit (IC)700corresponding to some alternative embodiments of the IC300ofFIG.3is provided. The IC700includes a metal-insulator-metal-insulator-metal (MIMIM) capacitor200adisposed in a first passivation layer510and configured for a one-transistor two-capacitor (1T2C) setup.

The access MOSFET308is configured and/or illustrated as the access MOSFET308ofFIG.3. A bonding structure505overlies the interconnect structure303and the access MOSFET308. The bonding structure505includes the first passivation layer510, a second passivation layer512, a redistribution layer508, and first and second redistribution vias506a-b. The MIMIM capacitor200ais disposed within the first passivation layer510. The MIMIM capacitor200aincludes a bottom electrode104, a capacitor dielectric layer106, an upper capacitor dielectric layer208, a top electrode108, and a middle electrode202disposed between the top and bottom electrodes108,104.

The first redistribution via506aextends from the redistribution layer508to a topmost layer of the conductive wires312in the interconnect structure303. The first redistribution via506aextends through the top electrode108, the capacitor dielectric layer106, and the bottom electrode104, such that the top electrode108is electrically coupled to the bottom electrode104. The second redistribution via506bextends from the redistribution layer508to the topmost layer of the conductive wires312and is electrically coupled to a source/drain region302of the access MOSFET308. The second redistribution via506bextends through the upper capacitor dielectric layer208, the middle electrode202, and the capacitor dielectric layer106. Thus, the middle electrode202is electrically coupled to the source/drain region302of the access MOSFET308. In some embodiments, the redistribution layer508is electrically coupled to the BL.

Referring toFIG.8, a circuit diagram800of some embodiments of the IC700ofFIG.7is provided.

As illustrated inFIG.8, the SL is electrically coupled to a first source/drain region of the access MOSFET308. The WL is electrically coupled to a gate electrode of the access MOSFET308, and a second source/drain region of the access MOSFET308is electrically coupled to the MIMIM capacitor200a. The second source/drain region of the access MOSFET308is electrically coupled to the BL by way of the MIMIM capacitor200a.

In some embodiments, the MIMIM capacitor200aincludes a first capacitor802electrically coupled to a second capacitor804in parallel with one another. The first capacitor802includes a first plate802p1and a second plate802p2, such that the first plate802p1is parallel to the second plate802p2. The second capacitor804includes a first plate804p1and a second plate804p2, such that the first plate804p1is parallel to the second plate804p2. In some embodiments, the middle electrode202is configured as the first plate802p1of the first capacitor802and the first plate804p1of the second capacitor804. In further embodiments, the bottom electrode104is configured as the second plate802p2of the first capacitor802, and the top electrode108is configured as the second plate804p2of the second capacitor804. The second plate802p2of the first capacitor802and the second plate804p2of the second capacitor804are electrically coupled to the BL.

Referring toFIG.9, a cross-sectional view of an IC900according to some alternative embodiments of the IC700ofFIG.7is provided, in which a bonding structure505having a bump structure515overlies the interconnect structure303.

The access MOSFET308includes source/drain regions302, a gate electrode306, and a gate dielectric304. The source/drain regions302are disposed between an isolation structure502that extends from an upper surface of the substrate102to a point below the upper surface of the substrate102. In some embodiments, the isolation structure502is configured as a shallow trench isolation (STI) structure and comprises one or more dielectric materials (e.g., silicon dioxide). The access MOSFET308further includes a sidewall spacer structure504surrounding the gate electrode306and the gate dielectric304. At least a portion of the sidewall spacer structure504overlies the source/drain regions302.

The bonding structure505overlies the interconnect structure303and the access MOSFET308. The bonding structure505includes a first passivation layer510, a second passivation layer512, a top dielectric structure514, the bump structure515, a redistribution layer508, and first and second redistribution vias506a,506b. The redistribution layer508is disposed within the second passivation layer512. The first and second redistribution vias506a-bare disposed within the first passivation layer510and extend from the redistribution layer508to the conductive wires312. In some embodiments, the redistribution layer508is electrically coupled to the MIMIM capacitor200a. The bump structure515extends through the top dielectric structure514and contacts the redistribution layer508. The bump structure515includes a bond pad516, a bond bump518, and a solder ball520. The bump structure515is electrically coupled to the interconnect structure303by way of the redistribution layer508. In some embodiments, the bump structure515is configured to electrically couple the IC900to another IC (not shown).

Referring toFIG.10, a cross-sectional view1000of some alternative embodiments of a portion of the IC900ofFIG.9, as indicated by the dashed box inFIG.9is provided.

As illustrated inFIG.10, the MIMIM capacitor200ais disposed within the first passivation layer510and directly underlies the redistribution layer508. The redistribution layer508includes a conductive body508asurrounded by a conductive liner508b. In some embodiments, the redistribution layer508has a protrusion that extends through the first passivation layer510to a conductive wire312in an ILD layer314. In some embodiments, the conductive body508amay, for example, be or comprise aluminum, copper, an alloy of the aforementioned, or the like. In further embodiments, the conductive liner508bmay, for example, be or comprise tungsten, or the like.

FIGS.11-16illustrate cross-sectional views1100-1600of some embodiments of a method of forming a metal-insulator-metal (MIM) capacitor having a diffusion barrier layer according to aspects of the present disclosure. Although the cross-sectional views1100-1600shown inFIGS.11-16are described with reference to a method, it will be appreciated that the structures shown inFIGS.11-16are not limited to the method but rather may stand alone separate of the method. Furthermore, althoughFIGS.11-16are described as a series of acts, it will be appreciated that these acts are not limiting in that the order of the acts can be altered in other embodiments, some acts that are illustrated and/or described may be omitted in whole or in part. In some embodiments,FIGS.11-16may, for example, be employed to form some embodiments of the MIM capacitor100bofFIG.1B.

As shown in cross-sectional view1100ofFIG.11, a bottom electrode104is formed over a substrate102. In some embodiments, the bottom electrode104may, for example, be or comprise titanium nitride, tantalum nitride, titanium, tantalum, tungsten, or the like. A capacitor dielectric layer106is formed over the bottom electrode104. A first deposition process is performed to form a first top electrode layer110aover the capacitor dielectric layer106. In some embodiments, the first top electrode layer110amay be a first material (e.g., titanium nitride (TiN)) and/or may have a thickness tawithin a range of about 100 to 200 Angstroms. In some embodiments, the first deposition process includes performing a physical vapor deposition (PVD), such that the first top electrode layer110ahas a plurality of grains114(as illustrated and described inFIG.1B). Other deposition processes are, however, amenable. For example, in some embodiments, the first top electrode layer110amay be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or some other suitable deposition process. The grains114may, for example, be columnar grains with grain boundaries that extend from a top surface of the capacitor dielectric layer106to a point above the top surface of the capacitor dielectric layer106. In some embodiments, the thickness tais a maximum thickness of the first top electrode layer110a. In some embodiments, the bottom electrode104and/or the capacitor dielectric layer106may be deposited by thermal oxidation, CVD, PVD, ALD, some other deposition process, or any combination of the foregoing.

As shown in cross-sectional view1200ofFIG.12, a diffusion barrier layer112is formed over the first top electrode layer110a. In some embodiments, the diffusion barrier layer112may, for example, be or comprise the first material (e.g., TiN) and/or may have a thickness tdbwithin a range of about 10 to 15 Angstroms. In some embodiments, the thickness tdbis a maximum thickness of the diffusion barrier layer112. In some embodiments, a process for forming the diffusion barrier layer112includes: 1) performing a second deposition process to deposit the diffusion barrier layer112; and 2) performing an annealing process on the diffusion barrier layer112. In some embodiments, the annealing process may increase from a minimum annealing temperature (e.g. about 250 degrees Celsius) to a maximum annealing temperature (e.g., about 400 degrees Celsius). In some embodiments, the second deposition process includes performing an ALD process, such that that the thickness tdbmay be formed within the range of about 10 to 15 Angstroms. Other deposition processes are, however, amenable. In some embodiments, the diffusion barrier layer112and the first top electrode layer110aare deposited by different deposition processes. For example, in such embodiments, the diffusion barrier layer112is deposited by ALD and the first told electrode layer110ais deposited by PVD. In further embodiments, the diffusion barrier layer112may be formed by CVD, PVD, or some other suitable deposition process.

In some embodiments, while performing the annealing process, the structure ofFIG.12is exposed to a treatment species (e.g., nitrogen (N2), hydrogen (H2), a combination of the foregoing, etc.), wherein the diffusion barrier layer112is rich in the treatment species (e.g., N-rich) after performing the annealing process. In some embodiments, during the annealing process the treatment species may be implanted and/or absorbed into the diffusion barrier layer112, wherein the diffusion barrier layer112is rich in the treatment species (e.g., N-rich). In some embodiments, the diffusion barrier layer112comprises a ratio of titanium to nitrogen of about 1:1.02, 1:1.03, 1:1.04, or 1:1.05. For example, for every 100 titanium atoms, the diffusion barrier layer112may comprise 102 to 105 nitrogen atoms. Further, nitrogen atoms have a smaller atomic radius than titanium atoms, wherein a layer with a greater number of nitrogen atoms than titanium atoms will have a shorter distance between adjacent atoms (i.e., smaller grain sizes). Because the diffusion barrier layer112is N-rich (i.e., a greater number of nitrogen atoms than titanium atoms) a distance between atoms in the diffusion barrier layer112is less than a distance between atoms in the first top electrode layer110a. Therefore, the atoms in the diffusion barrier layer112are more densely packed together than the atoms in the first top electrode layer110a, leading to the diffusion barrier layer112having smaller grain sizes. In further embodiments, the atoms in the diffusion barrier layer112are so densely packed together that a diffusive species is unable to travel between adjacent atoms in the diffusion barrier layer112.

In further embodiments, the diffusion barrier layer112may be N-rich in an upper region112a, where the upper region112ais defined from the dotted line inFIG.12to a top surface112tsof the diffusion barrier layer112. In some embodiments, after performing the annealing process and exposing the diffusion barrier layer112to the treatment species, the diffusion barrier layer112has at least a partially crystalline structure that is different from that of the first top electrode layer110a. For example, the diffusion barrier layer112has a plurality of grains that are non-columnar and smaller than the grains114of the first top electrode layer110a. In some embodiments, the grains of the diffusion barrier layer112may be equiaxed as described and/or illustrated inFIG.1B. In further embodiments, the annealing process with the treatment species facilitates the partially crystalline structure of the diffusion barrier layer112, such that the diffusion barrier layer112has grains with grain sizes less than about 3 Angstroms. The partially crystalline structure, non-columnar grain sizes, and/or N-rich properties of the diffusion barrier layer112block and/or mitigate diffusion of a diffusive species through the diffusion barrier layer112during subsequent processing steps (e.g., the patterning, removal, and/or cleaning processes ofFIGS.15and16). This, in part, may be because the nitrogen atoms disposed in the diffusion barrier layer112during the annealing process reduce a distance between adjacent titanium and nitrogen atoms. Thus, the diffusive species is unable to travel between adjacent titanium and nitrogen atoms in the diffusion barrier layer112. The diffusive species may, for example, be or comprise oxygen (O2), hydrogen peroxide (H2O2), hydrofluoric acid (HF), dihydrofolic acid (DHF), or a combination of the aforementioned.

As shown in cross-sectional view1300ofFIG.13, a second top electrode layer110bis formed over the diffusion barrier layer112. In some embodiments, the second top electrode layer110bis formed by a third deposition process (e.g., a PVD process), such that the second top electrode layer110bcomprises the first material (e.g., TiN) and/or has a thickness tbwithin a range of about 100 to 200 Angstroms. The second top electrode layer110bhas a plurality of grains116that may, for example, be columnar grains (as illustrated and described inFIG.1B). In some embodiments, the third deposition process is the same as the first deposition process (e.g., PVD process) and different from the second deposition process (e.g., ALD process). In further embodiments, the first, second, and third deposition processes each comprise a PVD process. Other deposition processes are, however, amenable for the first, second, and third deposition processes.

As shown in cross-sectional view1400ofFIG.14, a masking layer1402is formed over the second top electrode layer110b. In some embodiments, the masking layer1402may, for example, be or comprise a photoresist, a hard mask, or the like.

As shown in cross-sectional view1500ofFIG.15, a patterning process is performed on the first and second top electrode layers110a-b, the diffusion barrier layer112, and the capacitor dielectric layer106, thereby defining the top electrode108and the metal-insulator-metal (MIM) capacitor100a. The top electrode108includes the first and second top electrode layers110a-band the diffusion barrier layer112. The MIM capacitor100aincludes the top electrode108, the bottom electrode104, and a capacitor dielectric layer106. In some embodiments, the patterning process may include performing a wet etch on the first and second top electrode layers110a-b, the diffusion barrier layer112, and the capacitor dielectric layer106. The aforementioned layers may be exposed to one or more etchants according to the masking layer1402. In some embodiments, the one or more etchants may, for example, be or comprise at least one of the diffusive species (e.g., hydrogen peroxide (H2O2)).

In further embodiments, after performing the patterning process, the capacitor dielectric layer106has a thickness tcrdefined in a center region106crof the capacitor dielectric layer106and a thickness tprdefined in a peripheral region106prof the capacitor dielectric layer106. The top electrode108overlies the center region106crof the capacitor dielectric layer106, such that the capacitor dielectric layer106has the thickness tc, between a top surface of the bottom electrode104and a bottom surface of the first top electrode layer110a. The peripheral region106prsurrounds the center region106crand is laterally offset from the top electrode108. In some embodiments, the thickness tpris less than the thickness tcr. Thus, the capacitor dielectric layer106has two discrete thicknesses.

As shown in cross-sectional view1600ofFIG.16, a removal process is performed on the structure ofFIG.15to remove the masking layer (1402ofFIG.15). In some embodiments, the removal process includes performing a wet etch and/or a dry etch, such as a wet ash and/or a dry ash. The removal process may, for example, include exposing the top electrode108, masking layer (1402ofFIG.15), and or the capacitor dielectric layer to at least one of the diffusive species.

In some embodiments, after performing the removal process, a cleaning process may be performed on the top electrode108and the capacitor dielectric layer106to, for example, remove by-products from the patterning process and/or the removal process. The cleaning process may include exposing the top electrode108and the capacitor dielectric layer106to at least one of the diffusive species (e.g., H2O2and/or dihydrofolic acid (DHF)). The diffusion barrier layer112is configured to block diffusion of the diffusive species to the center region106crof the capacitor dielectric layer106during and/or after the patterning, cleaning, and/or removal process(es), thereby preventing and/or mitigating a formation of voids in at least the center region106crof the capacitor dielectric layer106. This, in part, prevents the breakdown of the MIM capacitor100aat high operating volts, thereby increasing an operating voltage, an endurance, and a reliability of the MIM capacitor100a.

FIG.17illustrates a method1700of forming a MIM capacitor having a diffusion barrier layer according to the present disclosure. Although the method1700is illustrated and/or described as a series of acts or events, it will be appreciated that the method is not limited to the illustrated ordering or acts. Thus, in some embodiments, the acts may be carried out in different orders than illustrated, and/or may be carried out concurrently. Further, in some embodiments, the illustrated acts or events may be subdivided into multiple acts or events, which may be carried out at separate times or concurrently with other acts or sub-acts. In some embodiments, some illustrated acts or events may be omitted, and other un-illustrated acts or events may be included.

At act1702, a bottom electrode is formed over a substrate, and a capacitor dielectric layer is formed over the bottom electrode.FIG.11illustrates a cross-sectional view1100corresponding to some embodiments of act1702.

At act1704, a first deposition process is performed to deposit a first top electrode layer over the capacitor dielectric layer.FIG.11illustrates a cross-sectional view1100corresponding to some embodiments of act1704.

At act1706, a second deposition process is performed to deposit a diffusion barrier layer over the first top electrode layer. In some embodiments, the first deposition process (e.g., a PVD process) is different from the second deposition process (e.g., an ALD process).FIG.12illustrates a cross-sectional view1200corresponding to some embodiments of act1706.

At act1708, an annealing process is performed on the diffusion barrier layer. The diffusion barrier layer is exposed to a treatment species (e.g., nitrogen (N2), hydrogen (H2), a combination of the foregoing, etc.) during the annealing process.FIG.12illustrates a cross-sectional view1200corresponding to some embodiments of act1708.

At act1710, a third deposition process is performed to deposit a second top electrode layer over the diffusion barrier layer.FIG.13illustrates a cross-sectional view1300corresponding to some embodiments of act1710.

At act1712, a masking layer is formed over the second top electrode layer.FIG.14illustrates a cross-sectional view1400corresponding to some embodiments of act1712.

At act1714, a patterning process is performed on the first and second top electrode layers, the diffusion barrier layer, and the capacitor dielectric layer, thereby defining a top electrode.FIG.15illustrates a cross-sectional view1500corresponding to some embodiments of act1714.

At act1716, a removal process is performed to remove the masking layer.FIG.16illustrates a cross-sectional view1600corresponding to some embodiments of act1716.

At act1718, a cleaning process is performed on the top electrode and the capacitor dielectric layer.FIG.16illustrates a cross-sectional view1600corresponding to some embodiments of act1718.

Accordingly, in some embodiments, the present disclosure relates to a MIM capacitor that has a top electrode, a bottom electrode, and a capacitor dielectric layer disposed between the top and bottom electrodes. The top electrode has a first top electrode layer, a second top electrode layer, and a diffusion barrier layer disposed between the first and second top electrode layers.

In some embodiments, the present application provides a metal-insulator-metal (MIM) capacitor, including a bottom electrode overlying a substrate; a capacitor dielectric layer overlying the bottom electrode; and a top electrode overlying the capacitor dielectric layer, wherein the top electrode includes a first top electrode layer, a second top electrode layer, and a diffusion barrier layer disposed between the first and second top electrode layers.

In some embodiments, the present application provides an integrated chip, including an interconnect structure overlying a substrate, wherein the interconnect structure includes an alternating stack of conductive vias and wires; a bottom electrode overlying at least one of the conductive wires; a capacitor dielectric layer overlying the bottom electrode; a top electrode overlying the capacitor dielectric layer, wherein the top electrode includes a first top electrode layer; and a second top electrode layer overlying the first top electrode layer, wherein the first and second top electrode layers respectively have a first columnar grain and a second columnar grain, wherein the second columnar grain overlies the first columnar grain and has sidewalls laterally offset from sidewalls of the first columnar grain.

In some embodiments, the present application provides a method for forming a metal-insulator-metal (MIM) capacitor, the method includes forming a bottom electrode over a substrate; forming a capacitor dielectric layer over the bottom electrode; depositing a first top electrode layer over the capacitor dielectric layer; depositing a diffusion barrier layer over the first top electrode layer; performing an annealing process on the diffusion barrier layer, wherein after the annealing process the diffusion barrier layer is rich in a treatment species; and depositing a second top electrode layer over the diffusion barrier layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.