Patent ID: 12237387

The features and advantages of embodiments of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings. In the drawings, like reference numbers generally indicate identical or similar elements, unless otherwise mentioned. Additionally, generally, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears.

DETAILED DESCRIPTION OF THE INVENTION

This specification discloses one or more embodiments that incorporate features of this invention. The disclosed embodiment(s) merely exemplify the present invention. The scope of the present invention is not limited to the disclosed embodiment(s).

The embodiment(s) described, and references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment(s) described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is understood that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not expressly described.

Before describing the various embodiments in detail, further explanation shall be given regarding certain terms that are used throughout the descriptions.

The terms “etch” or “etching” or “etch-back process” are used herein to generally describe a fabrication process of patterning a material such that at least a portion of the material remains after etching is completed. It shall be construed that etching a semiconductor material, for example, involves the steps of patterning a mask layer disposed over the semiconductor material (e.g., a photoresist layer or a hard mask), subsequently removing areas of the semiconductor material that are no longer protected by the mask layer, and optionally removing remaining portions of the mask layer. It shall also be construed that such removing step is conducted using an “etchant” and that such an etchant has a “selectivity” that is higher to the semiconductor material than to the mask layer. Further, it shall be understood that etching may be used in general terms without a mask layer, yet still yielding removed parts and remaining parts of the etched material.

The term “selectivity” between two materials is described herein as the ratio between the etch rates of the two materials under the same etching conditions. For example, an etchant with a selectivity of 3:1 to the semiconductor over the mask layer means that the etchant removes the semiconductor material at a rate three times faster than that at which it removes the mask layer.

The term “substrate” is used herein to generally describe a material onto which subsequent material layers are added. In this disclosure, the substrate itself may be patterned and materials added on top of it may also be patterned or remain without patterning. Furthermore, although throughout the following descriptions, the substrate is most commonly thought to be silicon, the substrate may also be any of a wide variety of materials, including commonly used semiconductor materials.

Further, it shall be understood that devices fabricated in and/or on the substrate may be in several regions of the substrate and furthermore that these regions may not be mutually exclusive. That is, in some embodiments, portions of one or more regions may overlap.

Further, the terms “deposit” or “dispose” are used herein to describe the act of applying a layer of material to the substrate or to layers already applied to the substrate, whether these layers are patterned or not. Further, it shall be understood that the deposited layer of material is conformal, unless otherwise mentioned. The term “conformal” is used herein to describe a film that at least partially covers one or more sidewalls of features patterned on a substrate.

The term “substantially perpendicular,” in reference to a topographical feature's sidewall, is used herein to generally describe a sidewall disposed at an angle ranging between about 85 degrees and 90 degrees with respect to the substrate. The term “substantially shorter,” in reference to the length of a first feature relative to that of a second feature, is used herein to generally imply that the length of the first feature is at most one half the length of the second feature. Lastly, the term “substantially longer” is used herein, in reference to the length of a first feature relative to that of a second feature, to generally imply that the length of the first feature is a least twice the length of the second feature.

Turning now to the drawings,FIG.1illustrates an example of a non-volatile memory cell100having a split-gate transistor architecture. Memory cell100is formed on substrate102. For ease of description, substrate102is assumed to be silicon. Other substrate materials may be used. Further, substrate102may be p-type silicon or a p-type well formed in an n-type silicon substrate or well. Memory cell100includes a first n-type doped region104and a second n-type doped region106. The first doped region104may be used as a source/drain region, and similarly, the second doped region106may also be used as a source/drain region. While regions104and106are n-type in this example, they may also be p-type regions when substrate102is n-type silicon or an n-type well formed in a p-type silicon substrate. Further, regions104and106may be formed, for example, using ion implantation. For convenience, region104is referred herein as the drain of memory cell100, and region106is referred to as a the source of memory cell100, irrespective of biases applied thereto. The terms drain and source are used by convention, not as limitations.

Memory cell100includes two gates, a select gate114and a memory gate110. Each gate may be a poly-Si layer. As shall be described below, select gate114is a spacer. Select gate114is disposed over dielectric layer112, whereas memory gate110is disposed over a charge-trapping dielectric108. The charge-trapping dielectric108may include, for example, a charge-trapping silicon nitride layer sandwiched between two silicon dioxide layers; this three-layer arrangement is referred to as an “oxide, nitride, oxide (ONO) stack,” or simply as “ONO layers.” Alternatively, charge-trapping dielectric108may include a silicon-rich nitride film, or any film that includes, but is not limited to, silicon, oxygen, and nitrogen, in various stoichiometries.

Dielectric112electrically isolates select gate114from memory gate110. Dielectric112comprises a first portion that is disposed vertically, i.e., substantially perpendicular to substrate102, and a second portion disposed horizontally beneath select gate114. The first portion and the second portion are connected to one another, e.g., dielectric112may be deposited in a single step to form its horizontal and vertical portions. In some examples, dielectric112and charge trapping dielectric108may have the same architecture, e.g., they may both be ONO stacks, while in other examples they may be physically distinguishable. For example, dielectric112is assumed to be a single-layer silicon dioxide film whereas dielectric108is an ONO stack.

To better understand how offsets in select gate114affect performance of memory cell100, example write, erase, and read operations, as they relate to memory cell100, shall now be described. In order to “write” a digital bit in memory cell100, a positive voltage on the order of 5 volts, for example, is applied to region106while region104and substrate102are grounded. A low positive voltage on the order of 1.5 volts, for example, is applied to select gate114while a higher positive voltage on the order of 8 volts, for example, is applied to memory gate110. As electrons are accelerated within a channel region between source and drain, some acquire sufficient energy to transport upwards and become trapped within charge-trapping dielectric108. This phenomenon is known as hot electron injection, and it is an example mechanism for storing charge within charge-trapping dielectric108. As such, charges trapped within charge-trapping dielectric108correspond to the “high” bit state of memory cell100. The trapped charge is retained even after the various voltage supplies are removed, hence the term “non-volatile” attributed to memory cell100in the preceding paragraphs.

To “erase” memory cell100(i.e., in order to remove charges trapped in charge-trapping dielectric108due to hot electron injection) a positive voltage on the order of 5 volts, for example, is applied to region106while region104is held at a fixed bias or simply left floating, and select gate108and substrate102are grounded. A high-magnitude negative voltage, −8 volts for example, is applied to memory gate110. Under these bias conditions, channel holes gain sufficient kinetic energy to overcome the oxide barrier and are injected into the charge-trapping layer. This added positive charge compensates the trapped negative charged electrons, thereby effectively erasing memory cell100to put it in the “low” bit state.

To “read” the state of memory cell100, a low voltage applied is to memory gate110and to select gate114. The low voltage is chosen so that it lies substantially equidistant between the threshold voltage necessary to turn on the split-gate transistor when storing a “high” bit and the threshold voltage necessary to turn on the split-gate transistor when storing a “low” bit. As such, if the application of the low voltage during the “read” operation caused substantial current flow between regions104and106, then the memory cell holds a “low” bit. Conversely, if the application of the low voltage during the “read” operation caused no current follow between regions104and106, then the memory cell holds a “high” bit.

Since the current during the “read” operation is directly proportional to the width of the memory gate110and to the width116of select gate114, the width of each gate is a critical dimension. In other words, the width of memory gate110and the width of select gate114must be fabricated within tight process tolerances in order to yield a gate width substantially equal to a nominal width set forth during the design of memory cell100. Otherwise, if the gate widths are either too short or too long as compared to the nominal width, incorrect operation of memory cell100will occur. Further, in an array comprising a plurality of memory cells such as memory cell100, each cell would have different characteristics due to mismatches in select gate length. This mismatch leads to poor memory array performance. As shall be seen below, while it may be possible to accurately control the width of memory gate110during fabrication, controlling the width116of select gate114is more complicated.

FIGS.2A-2Eillustrate cross-sectional views of an example fabrication process for the memory cell100shownFIG.1. It is to be understood that this description is meant to provide a general overview of the major steps involved in fabricating a split-gate transistor and that, in actual practice, many more features and/or fabrication steps may be provided to form memory cell100.

FIG.2Ashows a semiconductor substrate202(for example silicon) having disposed thereon a dielectric208and a transistor gate layer210. Substrate202may be p-type or n-type silicon as described previously. Further, substrate202may be a specific region of a larger semiconductor substrate (not shown). Dielectric208may comprise a stack of multiple dielectrics such as an ONO stack. Transistor gate layer210may be a poly-Si film, a metal alloy, or any other material that may serve as a transistor gate. For ease of description, it is assumed that dielectric208and transistor gate layer210are an ONO stack and a polycrystalline film, respectively.

Dielectric208and transistor gate layer210may be deposited on substrate202by conventional deposition methods. For example, the nitride layer of the ONO stack comprised in dielectric208may be deposited using low pressure chemical vapor deposition (LPCVD), whereas the oxide layer disposed under the nitride film of the ONO stack may be grown directly from substrate202using thermal oxidation; further, the oxide layer disposed over the silicon nitride film in the ONO stack may also be deposited using plasma-enhanced chemical vapor deposition (PECVD). Similarly, transistor gate layer210may be deposited via PECVD or any other methods typically used to deposit polycrystalline silicon. It shall be understood that different deposition (or growth) methods may impart varying electrical characteristic to memory cell100due to varying film qualities.

FIG.2Bshows semiconductor device200having two transistor gates, and a gate dielectric disposed thereunder. While only two transistor gates are shown inFIG.2B, it shall be understood that more than two gates may be formed. The two transistor gates are formed by patterning transistor gate layer210. The patterning of transistor gate layer210may be achieved by defining an etch mask (not shown) using photolithography and subsequently etching exposed regions of transistor gate layer210with an etchant that has higher selectivity to transistor gate layer210than to the etch mask. While this patterning step is defined in general terms, one of skill in the art would readily understand that transistor gate layer210may be patterned with more advanced lithography techniques, such as for example a double patterning step. Following the pattering of transistor gate layer210, exposed regions of dielectric208are removed. Transistor gate layer210thereby serves as a hard mask for the removal of the exposed regions of dielectric208.

FIG.2Cshows the formation of a conformal dielectric212layer on and around both gates. Dielectric212may be deposited utilizing a deposition process which enables step coverage. Such deposition processes may be, for example, PECVD. While dielectric212may be any of a wide variety of commonly used dielectrics, it is assumed, for ease of description, to be silicon dioxide. Dielectric212may be of equal thickness or thicker than dielectric208. Dielectric212further extends over the region between the formed transistor gates.

FIG.2Dshows the disposition of a spacer layer214on the semiconductor device200ofFIG.2C. Spacer layer214is disposed on dielectric212utilizing a conformal deposition process. Again, PECVD may be used to deposit spacer layer214. For ease of description, spacer layer214may be for example a poly-Si film. The deposited thickness of spacer layer214may be, for example, less than the thickness of transistor gate layer210.

Following the deposition of spacer layer214, an etch mask is disposed on spacer layer214and patterned (step not shown). The pattern defined in the etch mask are for forming two spacers on either side of each gate. As shown inFIG.2E, following the etch-back process, spacers214aand214bare formed on either side of transistor gate layer210aand210b. As shown inFIG.2E, the formed spacers214aand214bhave a cross-sectional view that comprises a perimeter having a curved portion. In some instances, the spacer's sidewall may be sloped.

This sidewall shape results from increased corner erosion during the etch-back process and from the anisotropy of the dry etchants typically used to conduct poly-Si etching (e.g., reactive ion etching (RIE) in chloro-fluorine plasmas). Specifically, since spacer layer214has a step due to the elevation of transistor gate layer210, spacer layer214must be over-etched in order to completely remove the portion of spacer layer214located directly on top of the gate. Further, since the region of spacer layer214that is on the sidewall of transistor gate layer210is conformal, the spacer resulting from the etch-back process has an outward curved sidewall since the etchant is anisotropic.

In addition to a curved sidewall profile, the aforementioned process conditions introduce offsets in the final width of spacer214. For example, variation in the duration of the etch-back process is directly related to how much corner erosion occurs. As such, spacer214may have a width216that is shorter than the targeted nominal width.

FIG.3illustrates an example non-volatile memory cell300, according to an embodiment of the present invention. Memory cell300is formed on substrate302. Substrate302is silicon and may be a p-type silicon bulk or a p-type region in an n-type bulk or well. Memory cell300includes a first n-type region304and a second n-type region306. The first doped region304may be used as a source/drain region, and similarly the second doped region306may be used as a source/drain region. While region304and region306are n-type in this example embodiment. they may also be v-type regions in another embodiment, when substrate302is an n-type bulk or an n-type well.

Memory cell300further includes two gates, a select gate314, which is a spacer, and a memory gate310. Gate310may be a poly-Si layer disposed and patterned using conventional techniques. However, select gate314is a spacer formed according to an example fabrication process, according to an embodiment of the present invention described below with reference toFIGS.4A-4D.

Memory cell300includes at least two dielectrics. The first dielectric312is a silicon dioxide layer. Dielectric312comprises a horizontal portion disposed beneath select gate314and a vertical portion sandwiched between memory gate310and select gate314. While in this embodiment the horizontal portion and the vertical portion of dielectric312are assumed to be of the same material, in alternate embodiments, the two portions may be two distinct dielectric materials.

The second dielectric308is disposed directly beneath memory gate310, and it is a charge trapping dielectric. Charge trapping dielectric308may include for example a silicon nitride layer sandwiched between two silicon dioxide layers, thus forming an ONO stack similar to the one previously described in memory cell100. Alternatively, dielectric308may include a silicon-rich nitride film, or any film that includes, but is not limited to, silicon, oxygen, or nitrogen, in various stoichiometries.

Memory cell300has similar operation to memory cell100. However, memory cell300differs structurally from memory cell100since in memory cell300, select gate314includes cross-section having a perimeter comprising a vertical sidewall320, substantially perpendicular to substrate302, in the portion farthest away from the edge of memory gate310. Moreover, spacer314includes a top curved portion318shorter in length than vertical sidewall320so as to provide a relatively flat surface (when compared with spacer214) on top of spacer314for subsequent metallization steps. Furthermore, the top curved portion318and the vertical sidewall320are joined at a discontinuity322. The discontinuity322is substantially shorter in length than both the top curved portion318and the vertical sidewall320. The structural features of spacer314result from improved process control of critical dimension316, which is the width of spacer314, and from minimized corner erosion during fabrication, according to an embodiment of the present invention as shall be described below.

FIGS.4A-4Dillustrate various cross-sectional views of non-volatile memory cells400, during their fabrication on substrate402, according to an embodiment. Substrate402is silicon and may be p-type or n-type silicon. For example, substrate402may be a p-type bulk region of a silicon wafer or a p-well in an n-type region of the wafer. Similarly, substrate402may be an n-type bulk or an n-type well in a p-type bulk region. While the substrate is silicon in this example embodiment, alternative embodiments may use other semiconductor substrates commonly used in semiconductor technology. Further, whileFIGS.4A-4Ddepict only two memory cells400, the many fabrication steps disclosed herein apply to the fabrication of more than two memory cells400. Furthermore, while a plurality of steps are described, steps generally undertaken in the fabrication of semiconductor devices are omitted for the sake of conciseness.

FIG.4Adepicts two gate structures, each gate structure comprising a transistor gate410, a charge trapping dielectric408, and an additional dielectric412that is conformal to gate410. The gate410is a poly-Si layer disposed and patterned with conventional deposition and patterning techniques, for example. While in this embodiment gate410is poly-Si, in alternative embodiments gate410may be made using other types of material that may serve as a transistor gate. Further, in this embodiment of the present invention, dielectric408may comprise a stack of multiple dielectrics such as an ONO stack, as previously described. Dielectric412may be silicon dioxide for example, and as in the case of dielectric312, it comprises a horizontal portion and a vertical portion. The horizontal portion and the vertical portion of dielectric412are the same material in this embodiment. In alternate embodiments the horizontal portion and the vertical portion of dielectric412may be distinct materials or distinct material stacks.

There is disposed, conformal to the gate structures, a spacer layer414. Spacer layer414is poly-Si, and it may be disposed using conventional poly-Si deposition techniques, such as the ones mentioned above. Further, there is disposed on spacer layer414a thin film dielectric424. Thin film424is conformal to spacer layer414. Further, thin film dielectric424is substantially thinner than spacer layer414. Thin film424is used as a sacrificial layer. Specifically, as will become apparent below, thin film424is used to form sacrificial spacers on the sidewalls of spacer layer414. In this example embodiment, thin film424is silicon nitride. However, thin film424may be any film that has etch chemistry that is substantially different than the etch chemistry of spacer layer414. In other words, an etchant of thin film424must have very low selectivity to spacer layer414. Conversely, an etchant of spacer layer414must have very low selectivity to thin film424. In summary, spacer layer414and thin film424form a multi-stack structure wherein the materials in the structure are etched at much different etch rates when subjected to an etchant that has high selectivity to only one material within the structure.

FIG.4Billustrates memory cells400following an etch-back process for fabricating sacrificial spacers424aand424bon the sidewalls of spacer layer414. A mask layer is disposed on thin film424(not shown) and patterned. Following the patterning of the mask layer, exposed regions of thin film424are etched, for example, in a CF4or CH2F2plasma etchant. These etchants have high selectivity to silicon nitride, e.g., they are highly selective to thin film424. Also, these etchants have very low selectivity to spacer layer414. Therefore, spacer layer414remains substantially unaltered even when it becomes in contact with the etchants.

FIG.4Cshows memory cells400following the sacrificial etch-back process that produced sacrificial spacers424aand424b. A subsequent etch-back process is conducted, but with an etchant having high selectivity to poly-Si, namely to the exposed regions of spacer layer414. Such etchants may be for example, chlorine and/or fluorine based plasma etchants. These etchants have relatively low selectivity to sacrificial spacers424aand424b. Therefore, spacers424aand424bact as masks for the sidewalls of spacer layer414during the etch back process. Accordingly, there is virtually no corner erosion during the etch-back process for spacer layer414, and the etch-back process yields a vertical sidewall profile. In addition, the etch-back process provides improved control over critical dimension416since spacer width416is insensitive to over-etching as a result of the sidewalls of spacer layer414being protected during the process.

FIG.4Dillustrates memory cells400following additional steps undertaken to remove exposed regions of dielectric412and to remove sacrificial spacers424aand424b. These procedures yield spacers414aand414b. Spacers414aand414bhave a vertical sidewall420, which is substantially perpendicular to substrate402, and a top curved portion418. The top curved portion418and the vertical sidewall420are joined by a discontinuity422that corresponds to the width of sacrificial spacers424aand424b. The width of discontinuity422is substantially shorter than the length of vertical sidewall420and substantially shorter than the length of the top curved portion418. The width of discontinuity422may be minimized by keeping thin film424as thin as possible. Lastly, spacers414band the portion of dielectric412directly beneath them may be subsequently removed and source/drain regions may be implanted in order to yield the structure shown in the embodiment depicted inFIG.3.

It is to be appreciated that the Detailed Description section, and not the Summary and Abstract sections (if any), is intended to be used to interpret the claims. The Summary and Abstract sections (if any) may set forth one or more but not all exemplary embodiments of the invention as contemplated by the inventor(s), and thus, are not intended to limit the invention or the appended claims in any way.

While the invention has been described herein with reference to exemplary embodiments for exemplary fields and applications, it should be understood that the invention is not limited thereto. Other embodiments and modifications thereto are possible, and are within the scope and spirit of the invention. For example, the methods disclosed herein may be used in applications where spacers are not limited to memory-cell fabrication. Such applications may include, for example, fabrication processes that use spacers as hard masks. Furthermore, the present invention is not limited multi-stack material comprising silicon nitride and poly-Si. Other multi-stack materials are contemplated and are within the scope of the present invention. For example, the multi-stack may be a silicon nitride/silicon dioxide stack, a silicon dioxide/poly-Si stack, and stacks of other materials typically used in semiconductor device fabrication.

The breadth and scope of the invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.