Patent ID: 12211753

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Gate-all-around (GAA) transistor structures may be patterned using any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.

FIGS.1-16illustrate a method of forming a semiconductor device in accordance with some embodiments of the present disclosure. Reference is made toFIG.1. An epitaxial stack104is formed over the substrate102. In some embodiments, the substrate102may be a semiconductor substrate such as a silicon substrate. In some embodiments, the substrate102may include various layers, including conductive or insulating layers formed on a semiconductor substrate. In some embodiments, different doping profiles (e.g., n wells, p wells) may be formed on the substrate102in device regions102aand102bdesigned for different device types (e.g., n-type field effect transistors (NFET), p-type field effect transistors (PFET)). The doping may include ion implantation of dopants and/or diffusion processes. In some embodiments, the substrate102may also include other semiconductors such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. In some embodiments, the substrate102may include a compound semiconductor and/or an alloy semiconductor. In some embodiments, the substrate102may optionally include an epitaxial layer (epi-layer), may be strained for performance enhancement, may include a silicon-on-insulator (SOI) structure, and/or have other suitable enhancement features.

The epitaxial stack104includes first epitaxial layers106of a first composition interposed by second epitaxial layers108of a second composition. The first and second composition can be different. In some embodiments, the first epitaxial layers106are SiGe and the second epitaxial layers108are silicon (Si). In some embodiments, the first epitaxial layers106and the second epitaxial layers108have different oxidation rates and/or etch selectivity. In some embodiments, the first epitaxial layers106include SiGe and the second epitaxial layers108include Si, and the Si oxidation rate of the second epitaxial layers108is less than the SiGe oxidation rate of the first epitaxial layers106.

The second epitaxial layers108or portions thereof may form a channel region of a semiconductor device. In some embodiments, the second epitaxial layers108may be referred to as “nanowires” used to form a channel region of a semiconductor device such as a gate-all-around (GAA) transistor. These “nanowires” are also used to form portions of the source/drain features of the GAA transistor. As the term is used herein, “nanowires” refers to semiconductor layers that are cylindrical in shape as well as other configurations such as, bar-shaped. The use of the second epitaxial layers108to define a channel or channels of the semiconductor device is further provided below.

It should be noted that four layers of each of the first epitaxial layers106and the second epitaxial layers108are illustrated inFIG.1, and this is for illustrative purpose and not intended to be limiting beyond what is specifically recited in the claims. It should be appreciated that any number of epitaxial layers can be formed in the epitaxial stack104; the number of layers depending on the desired number of channels regions for the GAA transistor. In some embodiments, the number of second epitaxial layers108is between two and ten.

In some embodiments, the first epitaxial layers106are substantially uniform in thickness. In some embodiments, the second epitaxial layers108are substantially uniform in thickness. As described in more detail below, the second epitaxial layers108may serve as channel region(s) for a subsequently-formed GAA transistor and its thickness chosen based on device performance considerations. The first epitaxial layers106may serve to define at least one gap distance between adjacent channel region(s) for a subsequently-formed GAA device and its thickness chosen based on device performance considerations.

In some embodiments, epitaxial growth of the layers of the epitaxial stack104may be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and/or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layers (e.g., the first epitaxial layers106and the second epitaxial layers108) include the same material as the substrate102. In some embodiments, the epitaxially grown layers (e.g., the first epitaxial layers106and the second epitaxial layers108) include a different material than the substrate102. As stated above, in at least some examples, the first epitaxial layers106include at least one epitaxially grown silicon germanium (SiGe) layer and the second epitaxial layers108include at least one epitaxially grown silicon (Si) layer. In some embodiments, either of the first epitaxial layers106and the second epitaxial layers108may include other materials such as germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or a combination thereof. As discussed, the materials of the first epitaxial layers106and the second epitaxial layers108may be chosen based on providing differing oxidation and/or different etch selectivity properties. In some embodiments, the first epitaxial layers106and the second epitaxial layers108are substantially dopant-free where for example, no intentional doping is performed during the epitaxial growth process.

Reference is made toFIGS.2A,2B, and2C, whereinFIGS.2B and2Care cross-sectional views taken along lines2B and2C inFIG.2A. Fin elements112extending from the substrate102are formed. In some embodiments, each of the fin elements112includes a substrate portion formed from the substrate102, and portions of each of the epitaxial layers of the epitaxial stack104including the first epitaxial layers106and the second epitaxial layers108.

In some embodiments, the fin elements112may be fabricated using any suitable process, including photolithography and etch processes. The photolithography process may include forming a photoresist layer over the substrate102(e.g., over the epitaxial stack104), exposing the resist to a pattern, performing post-exposure bake processes, and developing the resist to form a masking element including the resist. In some embodiments, pattering the resist to form the masking element may be performed using an electron beam (e-beam) lithography process. The masking element may then be used to protect regions of the epitaxial stack104, while an etch process forms trenches114in unprotected regions through the masking element, thereby leaving the plurality of extending fin elements112. In some embodiments, the trenches114may be etched using a dry etch (e.g., reactive ion etching), a wet etch, and/or other suitable processes.

Reference is made toFIGS.3A,3B, and3C, whereinFIGS.3B and3Care cross-sectional views taken along lines3B and3C inFIG.3A. The trenches114are filled with dielectric material to form isolation features116. The isolation features116can be referred to as shallow trench isolation (STI) features interposing the fin elements112. In some embodiments, the isolation features116may include SiO2, Si3N4, SiOxNy, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and/or other suitable materials. In some embodiments, the isolation features116may be deposited by a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, and/or other suitable process. In some embodiments, after deposition of the isolation features116, an annealing process can be performed, for example, to improve the quality of the isolation features116. In some embodiments, the isolation features116may include a multi-layer structure, for example, having one or more liner layers.

In some embodiments in which forming the STI features, after deposition of the isolation features116, the deposited dielectric material is thinned and planarized by a chemical mechanical polishing (CMP) process. The CMP process may planarize top surfaces of the isolation features116. In some embodiments, the STI features interposing the fin elements112are recessed, such that the fin elements112extend above the isolation features116. In some embodiments, the recessing may include a dry etching process, a wet etching process, and/or a combination thereof. In some embodiments, a recessing depth is controlled (e.g., by controlling an etching time) so as to result in a desired height of the exposed upper portion of the fin elements112, and the height exposes each of the layers of the epitaxial stack104.

Numerous other embodiments of methods to form fin elements112on the substrate102may also be used including, for example, defining the fin region (e.g., by mask or isolation regions) and epitaxially growing the epitaxial stack104in the form of the fin elements112. In some embodiments, forming the fin elements112may include a trim process to decrease the width of the fins, and the trim process may include wet or dry etching processes.

Reference is made toFIGS.4A,4B,4C, and4D, whereinFIGS.4B,4C, and4Dare cross-sectional views taken along lines4B,4C, and4D inFIG.4A. A gate stack118is formed. In some embodiments, the gate stack118is a dummy gate stack. That is, in some embodiments using a gate-last process, the gate stack118is a dummy gate stack and will be replaced by the final gate stack at a subsequent step. In some embodiments, the gate stack118may be replaced at a later step by a high-k dielectric layer and a metal gate electrode. In some embodiments, the gate stack118is formed over the substrate102and is at least partially disposed over the fin elements112. Portions of the fin elements112underlying the gate stack118may be referred to as the channel regions or channels of GAA transistors. The gate stack118may also define source/drain regions of GAA transistors. In some embodiments, regions of the epitaxial stack104which are adjacent to the channel region and on opposite sides of the channel region may be referred to as the source/drain regions.

In some embodiments, the gate stack118includes one or more hard mask layers (e.g., oxide, nitride). In some embodiments, the gate stack118is formed by various process steps such as layer deposition, patterning, etching, as well as other suitable processing steps. Exemplary layer deposition processes includes CVD (including both low-pressure CVD and plasma-enhanced CVD), PVD, ALD, thermal oxidation, e-beam evaporation, or other suitable deposition techniques, or a combination thereof. In some embodiments, the patterning process for forming the gate stack118includes a lithography process (e.g., photolithography or e-beam lithography) which may further include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), other suitable lithography techniques, and/or a combination thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and/or other etching methods.

As indicated above, the gate stack118may include an additional gate dielectric layer. In some embodiments, the gate stack118may include silicon oxide. In some embodiments, the additional gate dielectric layer of the gate stack118may include silicon nitride, a high-k dielectric material or other suitable material. In some embodiments, an electrode layer of the gate stack118may include polycrystalline silicon (polysilicon). In some embodiments, hard mask layers such as SiO2, Si3N4, SiOxNy, alternatively include SiC, and/or other suitable compositions may also be included.

Reference is made toFIGS.5A,5B,5C, and5D, whereinFIGS.5B,5C, and5Dare cross-sectional views taken along lines5B,5C, and5D inFIG.5A. A spacer layer120is blanket formed over the substrate102. The spacer layer120may include a dielectric material such as SiO2, Si3N4, SiOxNy, SiC, SiCN films, SiOc, SiOCN films, and/or a combination thereof. In some embodiments, the spacer layer120includes multiple layers, such as main spacer walls, liner layers, and the like. In some embodiments, the spacer layer120may be formed by depositing a dielectric material over the gate stack118using processes such as, CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process.

Reference is made toFIGS.6A,6B,6C, and6D, whereinFIGS.6B,6C, and6Dare cross-sectional views taken along lines6B,6C, and6D inFIG.6A. An etching-back process is performed to remove horizontal portions of the spacer layer120, while remaining vertical portions of the spacer layer120on sidewalls of the gate stack118to act as spacers125. That is, after the formation of the spacer layer120, the spacer layer120may be etched-back to expose portions of the fin elements112adjacent to and not covered by the gate stack118(e.g., source/drain regions), and spacers125remain on the opposite sidewalls of the gate stack118. In some embodiments, the etching-back process of the spacer layer120may include a wet etch process, a dry etch process, a multiple-step etch process, and/or a combination thereof. The spacer layer120may be removed from the top surface of the exposed epitaxial stack104and lateral surfaces of the exposed epitaxial stack104, and the spacer layer120may be removed from the top surface of the gate stack118. In some embodiments, the first epitaxial layers106and the second epitaxial layers108abut the sidewalls of the gate stack118.

Reference is made toFIGS.7A,7B,7C, and7D, whereinFIGS.7B,7C, and7Dare cross-sectional views taken along lines7B,7C, and7D inFIG.7A. An oxidation process is performed. The oxidation process may be referred to as a selective oxidation as due to the varying oxidation rates of the layers of the epitaxial stack104, and thus certain layers are oxidized. In some embodiments, the oxidation process may be performed by exposing the semiconductor device to a wet oxidation process, a dry oxidation process, or a combination thereof. In some embodiments, the epitaxial stack104exposed to a wet oxidation process using water vapor or steam as the oxidant, at a pressure of about 1 ATM, within a temperature range of about 400-600° C., and for a time from about 0.5-2 hours. It should be noted that the oxidation process conditions provided herein are merely exemplary, and are not meant to be limiting. In some embodiments, this oxidation process may extend such that the oxidized portion of the epitaxial layer(s) of the epitaxial stack104abuts the sidewall of the gate stack118.

During the oxidation process, the first epitaxial layers106of the fin elements112are fully oxidized, and thus the first epitaxial layers106transform into an oxidized layers122. The oxidized layers122extend to the gate stack118, including, under the spacers125. In some embodiments, the oxidized layers122extend to abut the sidewalls of the gate stack118. In some embodiments, the oxidized layers122may include an oxide of silicon germanium (SiGeOx).

By way of example, in some embodiments where the first epitaxial layers106include SiGe, and where the second epitaxial layers108includes Si, the faster SiGe oxidation rate (i.e., as compared to Si) ensures that the SiGe of the first epitaxial layers106become fully oxidized while minimizing or eliminating the oxidization of the second epitaxial layers108. It will be understood that any of the plurality of materials discussed above may be selected for each of the epitaxial layers that provide different suitable oxidation rates.

Reference is made toFIGS.8A,8B,8C, and8D, whereinFIGS.8B,8C, and8Dare cross-sectional views taken along lines8B,8C, and8D inFIG.8A. A selective etching process is performed. In some embodiments, the selective etching may etch the oxidized layers122(seeFIG.7A). In some embodiments, the oxidized layers122are removed from the source/drain regions (e.g., the regions of the fin elements112adjacent the channel regions underlying the gate stack118). Portions of the oxidized layer122directly underlying the spacers125adjacent the gate stack118remain on the substrate102(e.g., during the etching process the spacers125act as masking elements). Removal of the oxidized layers122create gaps124in the places of removed portions of the oxidized layers122, while portions122A of the oxidized layer122(e.g., SiGeO) remain on the substrate102. The gaps124may be filled with the ambient environment (e.g., air, N2). In some embodiments, portions of the oxidized layers122are removed by a selective wet etching process.

Reference is made toFIGS.9A,9B,9C, and9D, whereinFIGS.9B,9C, and9Dare cross-sectional views taken along lines9B,9C, and9D inFIG.9A. First epitaxial source/drain features126and second epitaxial source/drain features128are grown from the source/drain regions which are adjacent to the channel regions and on opposite sides of the channel regions. In some embodiments, growths of the first epitaxial source/drain features126and the second epitaxial source/drain features128includes growing one or more epitaxial materials. That is, the epitaxial material of the first epitaxial source/drain features126is grown on the second epitaxial layers108over the region102a, and the epitaxial material is also grown within the gaps124over the102a. Similarly, the epitaxial material of the second epitaxial source/drain features128is grown on the second epitaxial layers108over the region102b, and the epitaxial material is also grown within the gaps124over the region102b. The first epitaxial source/drain features126and the second epitaxial source/drain features128abut the oxidize portions122A and/or the spacers125. Thus, the oxidized portions122A are interposed between the first epitaxial source/drain features126(or the second epitaxial source/drain features128) and the gate stack118.

In some embodiments, the growth of the first epitaxial source/drain features126and the growth of the second epitaxial source/drain features128are performed in different steps. For example, the first epitaxial source/drain features126can be grown prior to the growth of the second epitaxial source/drain features128, and during the growth of the first epitaxial source/drain features126, the epitaxy layers108over the region102bcan be protected using a suitable mask (not shown). The first and second epitaxial source/drain features126and128may be in-situ doped. The doping species include P-type dopants, such as boron or BF2; N-type dopants, such as phosphorus or arsenic; and/or other suitable dopants including combinations thereof. If the epitaxial source/drain features are not in-situ doped, a second implantation process (i.e., a junction implant process) is performed to dope the epitaxial source/drain features. One or more annealing processes may be performed to activate the epitaxial source/drain features. The annealing processes include rapid thermal annealing (RTA) and/or laser annealing processes.

In some embodiments, the first epitaxial source/drain features126include a first semiconductor material, and the second epitaxial source/drain features128include a second semiconductor different than the first semiconductor material. If an n-type GAA transistor is to be formed on the region102a, the first epitaxial source/drain features126may be formed using one or more epitaxy processes, such that Si features, silicon phosphate (SiP) features, silicon carbide (SiC) features, and/or other suitable features suitable for serving as source/drain regions of the n-type device can be formed in a crystalline state from the epitaxial layers108over the region102a. In some embodiments, the lattice constants of the first epitaxial source/drain features126are different from the lattice constant of the fin elements112, so that the channel regions of the fin elements112can be strained or stressed by the first epitaxial source/drain features126to improve carrier mobility of the semiconductor device and enhance the device performance. The epitaxy processes include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and/or other suitable processes. The epitaxy process may use gaseous and/or liquid precursors, which interact with the composition of the second epitaxial layers108over the region102a. During this epitaxy process, a patterned mask (not shown) can be formed on the region102bof the substrate102in some embodiments.

If a p-type GAA transistor is to be formed on the region102b, the second epitaxial source/drain features128may be formed using one or more epitaxy processes, such that Si features, SiGe features, and/or other suitable features suitable for serving as source/drain regions of the p-type device can be formed in a crystalline state from the epitaxial layers108over the region102b. In some embodiments, the lattice constants of the second epitaxial source/drain features128are different from the lattice constant of the fin elements112, so that the channel regions of the fin elements112can be strained or stressed by the second epitaxial source/drain features128to improve carrier mobility of the semiconductor device and enhance the device performance. The epitaxy processes include suitable deposition techniques as stated above. The epitaxy process may use gaseous and/or liquid precursors, which interact with the composition of the second epitaxial layers108over the region102b. During this epitaxy process, a patterned mask (not shown) can be formed on the region102aof the substrate102in some embodiments.

Reference is made toFIGS.10A,10B,10C, and10D, whereinFIGS.10B,10C, and10D are cross-sectional views taken along lines10B,10C, and10D inFIG.10A. An inter-layer dielectric (ILD) layer130is formed. In some embodiments, a contact etch stop layer (CESL) is also formed over the substrate102prior to forming the ILD layer130. In some embodiments, the CESL includes a silicon nitride layer, silicon oxide layer, a silicon oxynitride layer, and/or other materials. The CESL may be formed by plasma-enhanced chemical vapor deposition (PECVD) process and/or other suitable deposition or oxidation processes. In some embodiments, the ILD layer130includes materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. The ILD layer130may be deposited by a PECVD process or other suitable deposition technique. In some embodiments, after depositing the ILD layer130(and/or CESL or other dielectric layers), a planarization process may be performed to expose the top surface of the gate stack118. For example, a planarization process includes a chemical mechanical polishing (CMP) process which removes portions of the ILD layer130(and CESL layer, if present) overlying the gate stack118.

Reference is made toFIGS.11A,11B,11C, and11D, whereinFIGS.11B,11C, and11D are cross-sectional views taken along lines11B,11C, and11D inFIG.11A. The gate stack118(seeFIG.10A) is removed by a suitable etching process to form a gate trench132therein. The first epitaxial layers106(seeFIG.10C) in the channel region of the semiconductor device are selectively removed. In some embodiments, the first epitaxial layers106are removed by a selective wet etching process. In some embodiments, the selective wet etching includes HF. In some embodiments, the first epitaxial layers106are SiGe and the second epitaxial layers108are silicon allowing for the selective removal of the SiGe of the first epitaxial layers106. It should be noted that during the removal of the first epitaxial layers106, gaps are provided between the adjacent nanowires in the channel region (e.g., gaps between second epitaxial layers108). The gaps may be filled with the ambient environment conditions (e.g., air, nitrogen, etc.).

After the removal of the first epitaxial layers106, the second epitaxial layers108in the gate trench132are referred to as a plurality of nanowires in the channel region. In some embodiments, the second epitaxial layers108in the gate trench132and over the region102acan be referred to as first nanowires108A used for the n-type GAA transistor, and the second epitaxial layers108in the gate trench132and over the region102bcan be referred to as second nanowires108B used for the p-type GAA transistor.

FIGS.12-14Aillustrate exemplary steps of forming a gate stack in the gate trench132. As shown inFIG.12, a high-k dielectric layer220and a first high-k dielectric sheath layer230are in sequence formed in the gate trench132using one or more deposition processes. Thereafter, a mask240is formed over the first high-k dielectric sheath layer230and patterned such that the device region102ais masked while the device region102bis exposed, as shown inFIG.13. Afterwards, an exposed portion of the first high-k dielectric sheath layer230over the device region102bis removed using an etching process, while a masked portion of the first high-k dielectric sheath layer230over the device region102aremains. Next, a second high-k dielectric sheath layer250is formed over the device region102busing a suitable deposition process, and the patterned mask240over the device region102ais then removed. Thereafter, a metal layer260is formed using a suitable deposition process to fill the gate trench132, and a planarization process, such as CMP, is performed to remove excess materials outside the gate trench132, and the resulting structure is shown inFIGS.14A and14B, whereinFIG.14Bis a cross-sectional view taken along lines14B inFIG.14A.

In some embodiments, the high-k dielectric layer220includes HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, Y2O3, the like, or a combination thereof. In some embodiments, the first high-k dielectric sheath layer230includes Y2O3, Lu2O3, La2O3, SrO, the like, or a combination thereof. In some embodiments, the second high-k dielectric sheath layer250includes Al2O3, TiO2, ZrO2, MgO, the like, or a combination thereof. The formation methods of these dielectric layers may include, for example, molecular beam deposition (MBD), ALD, PECVD, and the like.

In some embodiments, the metal layer260includes tungsten (W), cobalt (Co), ruthenium (Ru), aluminum (Al), the like, or a combination thereof. Formation of the metal layer260may include, for example, MBD, ALD, PECVD, and the like. In some embodiments, first interfacial layers210amay respectively be formed around the first nanowires108A before formation of the high-k dielectric layer220, and second interfacial layers210bmay respectively be formed around the second nanowires108B before formation of the high-k dielectric layer220. The first and second interfacial layers210aand210bmay include SiO2, SiON, Y-doped SiO2, SixGeyOz, GeO2, SiHfO, SiHfON, the like, or a combination thereof. Additional layers, such as, an additional interfacial dielectric cap layer, may also be deposited (e.g., between the interfacial layer210a(or210b) and the high-k dielectric layer220).

As illustrated inFIGS.14A and14B, portions of the high-k dielectric layer220respectively surround the first interfacial layers210aand can be referred to as first high-k dielectric linings220a, and other portions of the high-k dielectric layer220respectively surround the second interfacial layers210band can be referred to as second high-k dielectric linings220b. Portions of the first high-k dielectric sheath layers230respectively surround the first high-k dielectric linings220aand can be referred to as first high-k dielectric sheaths230a, and portions of the second high-k dielectric sheath layers250respectively surround the second high-k dielectric linings220band can be referred to as second high-k dielectric sheaths250b. A portion of the metal layer260surrounds the first high-k dielectric sheaths230aand can be referred to as a first metal gate electrode260a, and a portion of the metal layer260surrounds the second high-k dielectric sheaths250band can be referred to as a second metal gate electrode260b.

The first interfacial layers210a, first high-k dielectric linings220a, first high-k dielectric sheaths230a, and first metal gate electrode260acan be in combination serve as a first gate stack GS1for the first nanowires108A. The second interfacial layers210b, second high-k dielectric linings220b, second high-k dielectric sheaths250b, and second metal gate electrode260bcan be in combination serve as a second gate stack GS2for the second nanowires108B.

In some embodiments, the first and second high-k dielectric sheaths230aand250binclude different materials used to adjust the work function of first and second gate stacks GS1and GS2to a desired value based on device design. For example, if the first gate stack GS1, the first epitaxial source/drain features126and the first nanowires108A form an n-type GAA transistor T1, the first high-k dielectric sheaths230acan include a material used to adjust the work function of the first gate stack GS1suitable for the n-type device. The material of the first high-k dielectric sheaths230asuitable for the n-type device may be, for example, Y2O3, Lu2O3, La2O3, SrO, Er, Sc, or a combination thereof. On the contrary, if the second gate stack GS2, the second epitaxial source/drain features128and the second nanowires108B form a p-type GAA transistor T2, the second high-k dielectric sheaths250bcan include a material used to adjust the work function of the second gate stack GS2suitable for the p-type device. The material of the second high-k dielectric sheaths250bsuitable for the p-type device may be, for example, Al2O3, TiO2, ZrO2, MgO, or a combination thereof. In some embodiments, the first high-k dielectric sheaths230aare made of La2O3, and the second high-k dielectric sheaths250bis made of Al2O3.

Because different work functions of the n-type and p-type GAA transistors T1and T2can be achieved by different materials of the first and second high-k dielectric sheaths230aand250b, the first and second metal gate electrodes260aand260bcan be made of the same material in some embodiments. For example, the metal layer260may be a single metal layer having a single metal material, and the first and second metal gate electrodes260aand260bare made of the single metal material. In other words, a space between the first and second high-k dielectric sheaths230aand250bare filled with a single metal, such as tungsten (W), cobalt (Co), ruthenium (Ru), aluminum (Al) or the like. As a result, the metal layer260is a single-layered structure rather than a multi-layered structure, and hence deposition of the metal layer260can be eased.

In some embodiments, outer surfaces of the first and second high-k dielectric sheaths230aand250bare respectively in contact with the first and second metal gate electrodes260aand260b, the first and second high-k dielectric linings220aand220bare in contact with inner surfaces of corresponding first and second high-k dielectric sheaths230aand250b. In some embodiments, the first high-k dielectric sheaths230asurrounding different nanowires108A are merged, and the second high-k dielectric sheaths250bare merged, as illustrated inFIG.14C. The merged first high-k dielectric sheaths230aand the merged second high-k dielectric sheaths250bcan prevent metal from interposing neighboring nanowires, and parasitic capacitance can thus be reduced.

In some embodiments, the first and second interfacial layers210aand210bare made of the same material if they are formed in the same processing step. For example, the first and second interfacial layers210aand210bmay be made of SiO2, SiON, Y-doped SiO2, SixGeyOz, GeO2, SiHfO, SiHfON, the like, or a combination thereof. In some other embodiments, the first and second interfacial layers210aand210bare made of different materials. For example, the first interfacial layer210amay initially be formed, and a portion of the first interfacial layer210aover the device region102bis then removed using a suitable patterning process (e.g., a combination of photolithography and etching), and the second interfacial layer210bmade of a different material than the first interfacial layer210ais then formed over the device region102b.

In some embodiments, the first and second high-k dielectric linings220aand220bare made of the same material because they are formed from the same high-k dielectric layer220. For example, the first and second high-k dielectric linings220aand220binclude HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, Y2O3, the like, or a combination thereof. In some other embodiments, the first and second high-k dielectric linings220aand220bare made of different materials. The first and second high-k dielectric linings220aand220bhaving different materials can be formed using any suitable deposition and patterning process, as discussed above.

In some embodiments, after formation of the first and second high-k dielectric sheath layers230and250and before formation of the metal layer260, a thermal treatment, such as annealing, can be performed to the first and second high-k dielectric sheath layers230and250. The thermal treatment can drive materials of the first and second high-k dielectric sheath layers230and250to diffuse into corresponding portions of the high-k dielectric layer220, and hence the first and second high-k dielectric sheath layers230and250can then be removed to enlarge the process window for depositing the metal layer260.

Reference is made toFIG.15. The ILD layer130(seeFIG.14A) is removed and silicide features150are formed. In some embodiments, the ILD layer130is removed by using an etching process, such as a wet etching process, a dry etching process, or a combination thereof. After the removal of the ILD layer130, the first epitaxial source/drain features126and the second epitaxial source/drain features128are exposed, and the silicide features150are formed from the exposed first epitaxial source/drain features126and the exposed second epitaxial source/drain features128. In some embodiments, formation of the silicide features150includes using a metal to form self-aligned silicide materials to the exposed first epitaxial source/drain features126and the exposed second epitaxial source/drain features128. The metal includes Ti, Co, Ta, Nb, or a combination thereof. In some embodiments, the formation of the silicide features150involves using an anneal to form the silicide features150and then removing the unreacted metal.

Thereafter, another ILD layer152is formed over the substrate102, contact holes are formed in the ILD layer152to expose the silicide features150, and source/drain contacts156are formed in the contact holes to contact with the silicide features150. The resulting structure is shown inFIG.16. In some embodiments, the ILD layer152includes materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. The ILD layer152may be deposited by a PECVD process or other suitable deposition technique. In some embodiments, a contact etch stop layer (CESL) is also formed over the substrate102prior to forming the ILD layer152. In some embodiments, the CESL includes a silicon nitride layer, silicon oxide layer, a silicon oxynitride layer, and/or other materials. The CESL may be formed by plasma-enhanced chemical vapor deposition (PECVD) process and/or other suitable deposition or oxidation processes. In some embodiments, after depositing the ILD layer152(and/or CESL or other dielectric layers), a planarization process may be performed to expose the top surface of the first and second gate stacks GS1and GS2. For example, a planarization process (e.g. CMP) can be performed to remove portions of the ILD layer152(and CESL layer, if present) overlying the gate stacks GS1and GS2.

FIGS.17-22illustrate a method of forming a semiconductor device in accordance with some embodiments of the present disclosure. As shown inFIG.17, first and second bottom source/drain regions304aand304bare formed over a substrate302with an isolation feature308(e.g. STI feature) separating the first and second bottom source/drain regions304aand304b. In some embodiments, the substrate302is a bulk silicon substrate, such as a silicon wafer. In some embodiments, the substrate302includes an elementary semiconductor, such as silicon or germanium in a crystalline structure; a compound semiconductor, such as silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; or a combination thereof. In some embodiments, the substrate302includes a silicon-on-insulator (SOI) substrate. The SOI substrate is fabricated using separation by implantation of oxygen (SIMOX), wafer bonding, and/or other suitable methods.

First nanowires310A are formed over the first bottom source/drain region304a, and the second nanowires310B are formed over the second bottom source/drain region306b. Exemplary formation of the first and second nanowires310A and310B and the first and second bottom source/drain regions304aand304bincludes forming a bottom semiconductor layer having the first and second bottom source/drain regions304aand304bdisposed over device regions302aand302b, forming a middle semiconductor layer having channel regions312band312bdisposed over first and second bottom source/drain regions304aand304b, forming a top semiconductor layer having first and second top source/drain regions314aand314bdisposed over channel regions312band312b, and patterning the stack of bottom, middle and top semiconductor layers to form the first and second nanowires310A and320B.

In some embodiments, the patterning of stack of bottom, middle and top semiconductor layers may be done using a combination of photolithography and etching. For example, a hard mask and/or photoresist (not illustrated) may be disposed over the stack. The hard mask may comprise one or more oxide (e.g., silicon oxide) and/or nitride (e.g., silicon nitride) layers to prevent damage to the underlying semiconductor layers during patterning, and the hard mask may be formed using any suitable deposition process, such as, atomic layer deposition (ALD), CVD, high density plasma CVD (HDP-CVD), physical vapor deposition (PVD), and the like. The photoresist may comprise any suitable photosensitive material blanket deposited using a suitable process, such as, spin on coating, and the like. In some embodiments, the bottom, middle and top semiconductor layers may be formed using metal-organic (MO) chemical vapor deposition (CVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), combinations thereof, and the like.

The first bottom and top source/drain regions304aand314ain the device region302amay be doped with a n-type dopant (e.g., P, As, Si, Ge, C, O, S, Se, Te, Sb, combinations thereof, and the like) at a suitable concentration (e.g., about 1×1018atoms cm−3to about 1×1022atoms cm−3). Suitable materials for the first bottom and top source/drain regions304aand314a(e.g., n-type epitaxy materials) may include Si, SiP, SiPC, Ge, GeP, a III-V material (e.g., InP, GaAs, AlAs, InAs, InAlAs, InGaAs, and the like), combinations thereof, and the like. In other embodiments, the first bottom and top source/drain regions304aand314amay comprise a different material, different dopants, and/or a different doping concentration depending on device design.

The second bottom and top channel regions304band314bin the device region302bmay be doped with a p-type dopant (e.g., B, BF2, Si, Ge, C, Zn, Cd, Be, Mg, In, combinations thereof, and the like) at a suitable concentration (e.g., about 1×1018atoms/cm2to about 1×1022atoms/cm2). Suitable epitaxy materials for the second bottom and top channel regions304band314b(e.g., p-type epitaxy materials) may include Si, SiGe, SiGeB, Ge, GeB, a III-V material (e.g., InSb, GaSb, InGaSb, and the like), combinations thereof, and the like. In other embodiments, the second bottom and top channel regions304band314bmay comprise a different material, different dopants, and/or a different doping concentration depending on device design.

The channel region312ain device region302aand the channel region312bin device region302bmay be doped with either n-type or p-type dopants depending on device design. For example, for accumulation mode devices, the channel region312amay be doped with n-type dopants (e.g., P, As, Si, Ge, C, O, S, Se, Te, Sb, combinations thereof, and the like) while the channel region312bmay be doped with p-type dopants (e.g., B, BF2, Si, Ge, C, Zn, Cd, Be, Mg, In, combinations thereof, and the like). As another example, for inversion mode devices, the channel region312amay be doped with p-type dopants (e.g., B, BF2, Si, Ge, C, Zn, Cd, Be, Mg, In, combinations thereof, and the like) while the channel region312bmay be doped with n-type dopants (e.g., P, As, Si, Ge, C, O, S, Se, Te, Sb, combinations thereof, and the like). In some embodiments, a dopant concentration of channel regions312aand312bmay be about 1×1012atoms cm−3to about 1×1018atoms cm−3, for example. Suitable materials for channel regions312aand312bmay include Si, SiP, SiPC, SiGe, SiGeB, Ge, GeB, GeP, a III-V material (e.g., InP, GaAs, AlAs, InAs, InAlAs, InGaAs, InSb, GaSb, InGaSb, and the like), combinations thereof, and the like. The material of channel region312aand/or the channel region312bmay depend on the desired type of the respective region. In other embodiments, channel regions312aand312bmay comprise a different material, different dopants, and/or a different doping concentration depending on device design.

After formation the nanowires, a contact etch stop layer (CESL)320is blanket formed over the substrate302. Next, a dielectric layer330is formed over the CESL320. Thereafter, upper portions of the CESL320, and upper portions of the dielectric layer330are removed using wet and/or dry etching processes to expose sidewalls of the first and second channel regions312aand314a.

In some embodiments, the CESL320comprises a material that can be selectively etched from a material of the dielectric layer330. For example, in some embodiments where the dielectric layer330comprises an oxide, the CESL320may comprise SiN, SiC, SiCN, or the like. The CESL320may be deposited using a conformal process, such as CVD, plasma enhanced CVD, PECVD, PVD, or the like.

The dielectric layer330may comprise a low-k dielectric having a k-value less than about 3.9, such as about 2.8 or even less. In some embodiments, the dielectric layer330comprises a flowable oxide formed using, for example, flowable chemical vapor deposition (FCVD). The dielectric layer330may fill the space between adjacent nanowires (e.g., nanowires310A and310B inFIG.17).

Reference is made toFIG.18. A high-k gate dielectric layer350and a first-high-k dielectric sheath layer360are in sequence formed over the substrate302. In some embodiments, the high-k dielectric layer350includes HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, Y2O3, the like, or a combination thereof. In some embodiments, the first high-k dielectric sheath layer360includes Y2O3, Lu2O3, La2O3, SrO, the like, or a combination thereof. The formation methods of high-k dielectric layer350and the first-high-k dielectric sheath layer360may include, for example, molecular beam deposition (MBD), ALD, PECVD, and the like.

In some embodiments, before formation of the high-k layers, first interfacial layers340aare respectively formed around the first nanowires310A using any suitable technique, such as thermal oxidation. Similarly, before formation of the high-k layers, second interfacial layers340bare respectively formed around the second nanowires320A using any suitable technique, such as thermal oxidation.

Thereafter, a portion of the first high-k dielectric sheath layer360over the device region302bis removed using a suitable patterning process (e.g., a combination of photolithography and etching), and a second high-k dielectric sheath layer370is then formed over the device region302b. The resulting structure is shown inFIG.19. In some embodiments, the second high-k dielectric sheath layer370includes Al2O3, TiO2, ZrO2, MgO, the like, or a combination thereof. The formation method of the second high-k dielectric sheath layer370may include, for example, molecular beam deposition (MBD), ALD, PECVD, and the like.

Next, as shown inFIG.20, a metal layer380is formed over the substrate302to surround the first and second nanowires310A and310B. In some embodiments, the metal layer380includes tungsten (W), cobalt (Co), ruthenium (Ru), aluminum (Al), the like, or a combination thereof. Formation of the metal layer380may include, for example, MBD, ALD, PECVD, and the like. Thereafter, the metal layer380is etched back to expose the first and second top source/drain regions314aand314b, and the resulting structure is shown inFIG.21. In the resulting structure, the metal layer380may not share any interface with the top and bottom source/drain regions304a/304b/314a/314b(e.g., top and bottom source/drain regions). After the etching back, an ILD layer (not shown) can be formed to cover the exposed top source/drain regions314aand314b.

FIG.22is an enlarged view ofFIG.21. As illustrated, portions of the high-k dielectric layer350respectively surround the first interfacial layers340aand can be referred to as first high-k dielectric linings350a, and other portions of the high-k dielectric layer350respectively surround the second interfacial layers340band can be referred to as second high-k dielectric linings350b. Portions of the first high-k dielectric sheath layers360respectively surround the first high-k dielectric linings350aand can be referred to as first high-k dielectric sheaths360a, and portions of the second high-k dielectric sheath layers370respectively surround the second high-k dielectric linings350band can be referred to as second high-k dielectric sheaths370b. A portion of the metal layer380surrounds the first high-k dielectric sheaths360aand can be referred to as a first metal gate electrode380a, and a portion of the metal layer380surrounds the second high-k dielectric sheaths370band can be referred to as a second metal gate electrode380b.

The first interfacial layers340a, first high-k dielectric linings350a, first high-k dielectric sheaths360a, and first metal gate electrode380acan be in combination serve as a first gate stack GS3for the channel regions312aof the first nanowires310A. The second interfacial layers340b, second high-k dielectric linings350b, second high-k dielectric sheaths370b, and second metal gate electrode380bcan be in combination serve as a second gate stack GS4for the channel regions312bof the second nanowires310B.

In some embodiments, the first and second high-k dielectric sheaths360aand370binclude different materials used to adjust the work function of first and second gate stacks GS3and GS4to a desired value based on device design. For example, if the first gate stack GS3, the first nanowires310A and the first bottom source/drain region304aform an n-type GAA transistor T3, the first high-k dielectric sheaths360acan include a material used to adjust the work function of the first gate stack GS3suitable for the n-type device. The material of the first high-k dielectric sheaths360asuitable for the n-type device may be, for example, Y2O3, Lu2O3, La2O3, SrO, Er, Sc, or a combination thereof. On the contrary, if the second gate stack GS4, the second nanowires310B and the second bottom source/drain region304bform a p-type GAA transistor T4, the second high-k dielectric sheaths370can include a material used to adjust the work function of the second gate stack GS4suitable for the p-type device. The material of the second high-k dielectric sheaths370bsuitable for the p-type device may be, for example, Al2O3, TiO2, ZrO2, MgO, or a combination thereof. In some embodiments, the first high-k dielectric sheaths360aare made of La2O3, and the second high-k dielectric sheaths370bis made of Al2O3.

Based on the above discussions, it can be seen that the present disclosure offers advantages. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that a single metal layer can be used as a gate electrode of a GAA transistor, and hence deposition of the gate electrode can be eased compared to multi-layered gate electrode. Another advantage is that different high-k dielectric sheaths are respectively used for n-type and p-type GAA transistors, and different work functions of gate stacks of the n-type and p-type GAA transistors can be achieved. Yet another advantage is that the high-k dielectric sheaths around the neighboring nanowires can be merged, and hence no metal interposes neighboring nanowires. This may be beneficial for reducing parasitic capacitance.

FIG.23illustrates a flow chart outlining a method1000for forming a semiconductor device in accordance with some embodiments of the present disclosure. The method1000is used to form the semiconductor device as described previously with respect toFIGS.1-16, in accordance with some embodiments.

In operation1002, an epitaxial stack104including first epitaxial layers106and second epitaxial layers108are formed over a substrate102, as shown inFIG.1, in accordance with some embodiments. In operation1004, fin elements112are formed by patterning the epitaxial stack104, as shown inFIGS.2A-2C, in accordance with some embodiments. In operation1006, isolation features116are formed, as shown inFIGS.3A-3C, in accordance with some embodiments.

In operation1008, a dummy gate stack118is formed across the fin elements112, as shown inFIGS.4A-4D, in accordance with some embodiments. In operation1010, spacers125are formed along the dummy gate stack118, as shown inFIGS.5A-6D, in accordance with some embodiments.

In operation1012, the first epitaxial layers106are oxidized to form oxidized layers122, as shown inFIGS.7A-7D, in accordance with some embodiments. In operation1014, portions of the oxidized layers122are removed from source/drain regions and portions122A of the oxidized layers122remain under the spacers125, as shown inFIGS.8A-8D, in accordance with some embodiments.

In operation1016, source/drain features126and128are formed in a region102aand a region102brespectively, as shown inFIGS.9A-9D, in accordance with some embodiments. In operation1018, an inter-layer dielectric layer130is formed over the source/drain features126and128, as shown inFIGS.10A-10D, in accordance with some embodiments.

In operation1020, the dummy gate stack118is removed, as shown inFIGS.11A-11D, in accordance with some embodiments. In operation1022, the first epitaxial layers106are removed from a channel region to expose the second epitaxial layers108, as shown inFIGS.11A-11D, in accordance with some embodiments.

In operation1024, interfacial layers210are formed around the exposed second epitaxial layers108and high-k dielectric layers220are formed around the interfacial layers210, as shown inFIG.12, in accordance with some embodiments. In operation1026, first high-k dielectric sheath layers230are formed around the high-k dielectric layers220in the first region102a, as shown inFIGS.12-13, in accordance with some embodiments. In operation1028, second high-k dielectric sheath layers250are formed around the high-k dielectric layers220in the second region102b, as shown inFIGS.14A-14C, in accordance with some embodiments. In operation1030, a metal layer260is formed around the first high-k dielectric sheath layers230and the second high-k dielectric sheath layers250, as shown inFIGS.14A-14C, in accordance with some embodiments.

In operation1032, the inter-layer dielectric layer130is removed; silicide features150are formed on the source/drain features126and128; an inter-layer dielectric layer152is formed over the source/drain features126and128; and source/drain contacts1032are formed to the silicide features150, as shown inFIGS.15-16, in accordance with some embodiments.

Embodiments of a semiconductor device may be provided below. The semiconductor device includes a set of nanostructures with middle portions thinner than end portions, a plurality of semiconductor capping layers formed around the thinner middle portions of the nanostructures, and a gate structure formed around the semiconductor capping layers. Since the middle portion is thinner than the end portions, the space between the middle portions of neighboring nanostructures may be filled with more work function adjustment layers. Therefore, various transistors having different threshold voltages in a semiconductor substrate may be achieved.

FIG.24illustrates a flow chart outlining a method2000for forming a semiconductor device in accordance with some embodiments of the present disclosure. The method2000differs from the method1000in that the method2000further includes, after operation1022and before operation1024, operation2002and operation2004, in accordance with some embodiments. Since operations1002to1032of the method2000are similar to operations1002to1032of method1000described previously with respect toFIGS.1-16, a detailed description thereof is omitted herein for the sake of brevity.

FIGS.25A-1to25D-3illustrate one or more steps of forming a semiconductor device during the method2000in accordance with some embodiments of the present disclosure.

FIG.25A-1illustrates a perspective view of a semiconductor structure after operation1022of the method2000in which the first epitaxial layers106are removed from the channel region to expose the second epitaxial layers108, in accordance with some embodiments. For a better understanding of the semiconductor structure, an X-Y-Z coordinate reference is provided inFIG.25A-1. The X-axis and Y-axis are generally orientated along the lateral directions that are parallel to the main surface of the substrate102. The Y-axis is transverse (e.g., substantially perpendicular) to the X-axis. The Z-axis is generally oriented along the vertical direction that is perpendicular to the main surface of the substrate102(or the X-Y plane).

FIG.25A-1further illustrates reference cross-sections that are used in later figures. Cross-sections I-I and II-II are in planes along the longitudinal axes of the second epitaxial layers108in the region102aand the region102b, respectively, in accordance with some embodiments. Cross-section III-III is in a plane across the channel region of the second epitaxial layers108and is along the longitudinal axis of a gate structure, in accordance with some embodiments.

FIG.25A-2is a cross-sectional view corresponding to cross-section I-I or II-II ofFIG.25A-1, andFIG.25A-3is a cross-sectional view corresponding to cross-section III-III ofFIG.25A-1. For the sake of simplicity and clarity,FIGS.25A-2and25A-3only illustrate the uppermost two of the second epitaxial layers108and neighboring features.

The first epitaxial layers106are removed from the channel region thereby exposing the four main surfaces of the second epitaxial layers108and forming gaps133, as shown inFIGS.25A-1to25A-3, in accordance with some embodiments. The gaps133are formed between two neighboring second epitaxial layers108, in accordance with some embodiments. The exposed second epitaxial layers108form nanostructures that function as channel layers of the resulting semiconductor devices (e.g., GAA transistors), in accordance with some embodiments. As the term is used herein, “nanostructures” refers to semiconductor layers that have cylindrical shape, bar shaped and/or sheet shape. Portions of nanostructures108surrounded by the source/drain features126and128are also used to form the source/drain terminals of the resulting semiconductor devices, in accordance with some embodiments. In some embodiments, the second epitaxial layers108have a thickness D1along Z direction in a range of about 2 nm to about 20 nm.

FIGS.25B-1and25B-2illustrate cross-sectional views of a semiconductor structure after operation2002of the method2000in which the exposed second epitaxial layers108are recessed, in accordance with some embodiments.FIG.25B-1corresponds to cross-section I-I or II-II ofFIG.25A-1, andFIG.25B-2corresponds to cross-section III-III ofFIG.25A-1.

An etching process is performed on the semiconductor structure ofFIGS.25A-1to25A-3, in accordance with some embodiments. Middle portions of the second epitaxial layers108at the channel region are recessed to form recessed middle portions108M, as shown inFIGS.25B-1and25B-2, in accordance with some embodiments. Because covered by the gate spacers125and the source/drain features126or128, end portions108E of the second epitaxial layers108on the opposite sides of the middle portions108M of the second epitaxial layers108are not recessed during the etching process, in accordance with some embodiments.FIG.25B-2illustrates the end portions108E of the second epitaxial layers108with dashed lines because the end portions108E of the second epitaxial layers108are located outside the cross-sectional view ofFIG.25B-2.

In some embodiments, the etching process is an isotropic etching process that thins down the middle portions of the second epitaxial layers108from the four main surfaces of the second epitaxial layers108toward the interior of the second epitaxial layers108. The isotropic etching process may be wet etching, dry chemical etching, or another suitable etching technique. In some embodiments, the middle portions of the second epitaxial layers108are recessed to an etching depth D2that is in a range of about 0.5 nm to about 3 nm. In some embodiments, the ratio of the etching depth D2to the thickness D1of the second epitaxial layers108is in a range of about 0.1 to about 0.16. That is, the total etching amount (twice the etching depth D2) is from about 0.2 to about 0.33 of the thickness D1. In some embodiments, the recessed middle portions108M of the second epitaxial layers108have a thickness D3in a range of about 1.5 nm to about 17 nm, as shown inFIGS.25B-1and25B-2. In some embodiments, the ratio of thickness D3to thickness D1is in a range of about 0.67 to about 0.8. If the ratio of thickness D3to thickness D1is too low, the current flowing through the channel layer, which is formed from the middle portions108M of the second epitaxial layers108, may decrease, which may affect device performance (e.g., speed). If the ratio of thickness D3to thickness D1is too high, the gap133may not provide enough space to accommodate more work function adjustment layers.

After the etching process, a distance between the recessed middle portions108M of neighboring two second epitaxial layers108is greater than a distance between the end portions108E of neighboring two second epitaxial layers108, in accordance with some embodiments. That is, the etching process enlarges the gaps133, in accordance with some embodiments.

The etching process creates inner side surfaces108S1and108S2of the end portions108E facing the channel regions, as shown inFIG.25B-1, in accordance with some embodiments. The inner side surfaces108S1and108S2face one another, in accordance with some embodiments. In some embodiments, the inner side surfaces108S1and108S2are aligned below the inner sidewalls of the gate spacers125facing the channel region.

FIGS.25C-1and25C-2illustrate cross-sectional views of a semiconductor structure after operation2004of the method2000in which the semiconductor capping layers404are formed around the middle portions108M of the second epitaxial layers108, in accordance with some embodiments.FIG.25C-1corresponds to cross-section I-I or II-II ofFIG.25A-1, andFIG.25C-2corresponds to cross-section III-III ofFIG.25A-1.

Semiconductor capping layers404are formed on the recessed middle portions108M of the second epitaxial layers108using an epitaxial growth process, as shown inFIGS.25C-1and25C-2, in accordance with some embodiments. In some embodiments, the semiconductor capping layers404are made of silicon germanium. Portions of the semiconductor capping layers404formed in the region102aare denoted as404awhile portions of the semiconductor capping layers404formed in the region102bare dented as404b, in accordance with some embodiments.

The semiconductor capping layers404are epitaxially grown from the semiconductor surface of the second epitaxial layers108and substantially not grown from dielectrics, e.g., the spacers125, the oxidized layers122A, and/or the inter-layer dielectric layer130, in accordance with some embodiments. The semiconductor capping layer404extends along the middle portion108M of the second epitaxial layer108from the inner side surface108S1to the inner side surface108S2, in accordance with some embodiments. In some embodiments, the semiconductor capping layer404interfaces the second epitaxial layer108at the outer surface of the middle portion108M and the inner side surfaces108S1and108S2of the end portions108E.

The semiconductor capping layers404are configured as work function adjustment layers to adjust the effective work functions of the gate structures for transistors, which may allow for various transistors over a substrate to have different threshold voltages, in accordance with some embodiments. The gaps133are enlarged by recessing the middle portions of the second epitaxial layers108, and therefore provide more space to accommodate more work function adjustment layers, such as the semiconductor capping layers404and materials subsequently formed over the semiconductor capping layers404(such as the high-k dielectric layer, high-k sheath layer, and/or the metal layer). As a result, the embodiments of the present disclosure may provide greater processing flexibility to achieve various transistors having different threshold voltages in a semiconductor substrate.

In addition, the semiconductor capping layers404also serve as portions of the channel layers of transistors, and therefore the loss of current flowing through the channels layers of the transistors due to recessing the middle portions of the second epitaxial layers108may be compensated.

In some embodiments, the semiconductor capping layers404are formed to have a thickness D4in a range of about 0.5 nm to about 3 nm, as shown inFIGS.25C-1and25C-2. In some embodiments, the thickness D4is substantially equal to the etching depth D2. In some embodiments, the germanium concentration of the semiconductor capping layers404is in a range of about 10 atomic % to about 60 atomic %. In some embodiments, the semiconductor capping layers404may be formed separately for N-type FETs and P-type FETs such that the semiconductor capping layers404aand the semiconductor capping layers404bmay have different thicknesses and germanium concentrations. For example, the semiconductor capping layers404ain the region102a(such as NMOS region) may be thinner than the semiconductor capping layers404bin the region102b(such as PMOS region). The germanium concentration of semiconductor capping layer404ain the region102a(such as NMOS region) may be less than the concentration of the semiconductor capping layer404bin the region102b(such as PMOS region).

After the semiconductor capping layers404are formed, operations1024-1030of the method2000, which are described previously with respect toFIGS.12-14C, may be performed on the semiconductor structure ofFIGS.25C-1and25C-2.FIGS.25D-1to25D-3illustrate cross-sectional views of a semiconductor structure after operations1030of the method2000in which gate structures GS1and GS2are formed, in accordance with some embodiments.FIG.25D-1corresponds to cross-section I-I ofFIG.25A-1,FIG.25D-2corresponds to cross-section II-II ofFIG.25A-1, andFIG.25D-3corresponds to cross-section III-III ofFIG.25A-1.

A gate structure GS1is formed to fill the gate trench132and the gaps133in the region102a, and it is thereby wrapped around the nanostructures of the second epitaxial layers108A, as shown inFIGS.25D-1and25D-3, in accordance with some embodiments. A gate structure GS2is formed to fill the gate trench132and the gaps133in the region102b, and it is thereby wrapped around the nanostructures of the second epitaxial layers108B, as shown inFIGS.25D-2and25D-3, in accordance with some embodiments. The gate structure GS1includes interfacial layers210adisposed around the semiconductor capping layers404a, high-k dielectric layer220adisposed around the interfacial layers210a, high-k dielectric sheath layers230adisposed around the high-k dielectric layer220a, and metal electrodes260adisposed around the high-k dielectric sheath layers230a, in accordance with some embodiments. The gate structure GS2includes interfacial layers210bformed around the semiconductor capping layers404b, high-k dielectric layers220bformed around the interfacial layers210b, high-k dielectric sheath layers250bformed around the high-k dielectric layer220b, and metal electrodes260bformed around the high-k dielectric sheath layers230b, in accordance with some embodiments. The metal layer260, used to form metal gate electrodes260aand260bof the gate structure GS1and GS2, continuously extends across the semiconductor capping layers404aand the semiconductor capping layers404b, in accordance with some embodiments. The gate structure GS1, interposing the source/drain features126, combines with the source/drain features126to form a FET, e.g., n-type GAA FET/nanostructure transistor, in accordance with some embodiments. The gate structure GS2, interposing the source/drain features128, combines with the source/drain features128to form a FET, e.g., p-type GAA FET/nanostructure transistor, in accordance with some embodiments.

The gate structure GS1and GS2shown inFIGS.25D-1to25D-3are similar to those shown inFIGS.14A-14C, except from the interfacial layers210, in accordance with some embodiments. The interfacial layers210(including210ain the region102aand210bin the region102b) of the gate structures GS1and GS2are formed around the semiconductor capping layers404, as shown inFIGS.25D-1to25D-3, in accordance with some embodiments. The interfacial layers210are formed by oxidizing the outer portions of the semiconductor capping layers404such that the interfacial layers210wrap around unoxidized portions of the semiconductor capping layers404, in accordance with some embodiments. In some embodiments, the interfacial layers210is germanium oxide, silicon oxide and/or silicon germanium oxide. The interfacial layers210extend along the semiconductor capping layers404between the end portions108E of the second epitaxial layers108, in accordance with some embodiments. After the gate structure GS1and GS2are formed, operation1032is performed on the semiconductor structure ofFIGS.25D-1to25D-3, to form source/drain contacts, in accordance with some embodiments.

FIGS.26A-1to26B-3illustrate one or more steps of forming a semiconductor device during the method2000in accordance with some embodiments of the present disclosure. The structures shown inFIGS.26A-1to26B-3are similar to those shown inFIGS.25C-1to25D-3except for the thickness of the semiconductor capping layers404, in accordance with some embodiments.

FIGS.26A-1and26A-2illustrate cross-sectional views of a semiconductor structure after operation2004of the method2000in which semiconductor capping layers404are formed on the middle portions108M of the second epitaxial layers108, in accordance with some embodiments.FIG.26A-1corresponds to cross-section I-I or II-II ofFIG.25A-1, andFIG.26A-2corresponds to cross-section III-III ofFIG.25A-1.

Semiconductor capping layers404are formed around the recessed middle portions108M of the second epitaxial layers108at the channel region, as shown inFIGS.26A-1and26A-2, in accordance with some embodiments. In some embodiments, the semiconductor capping layers404are formed to have a thickness D5in a range of about 0.5 nm to about 3 nm, as shown inFIGS.26A-1and26A-2. In some embodiments, the thickness D5is less than the etching depth D2(FIG.25B-1).

The semiconductor capping layers404are formed to conform to the profile of the second epitaxial layers108, in accordance with some embodiments. The semiconductor capping layer404includes extending portions404E along the inner side surfaces108S1and108S2of the end portions108E of the second epitaxial layers108and a flat portion404F located laterally between the extending portions404E, in accordance with some embodiments. A dimension of the extending portion404E along Z direction is greater than a dimension of the flat portion404F along Z direction, in accordance with some embodiments. That is, a portion of the semiconductor capping layer404at its edge is thicker than a portion of the semiconductor capping layer404at its center, such that the semiconductor capping layer404has a concave outer surface, in accordance with some embodiments.

After the semiconductor capping layers404are formed, operations1024-1030of the method2000may be performed on the semiconductor structure ofFIGS.25A-1and26A-2.FIGS.26B-1to26B-3illustrate cross-sectional views of a semiconductor structure after operations1030of the method2000in which gate structures GS1and GS2are formed, in accordance with some embodiments.FIG.26B-1corresponds to cross-section I-I ofFIG.25A-1,FIG.26B-2corresponds to cross-section II-II ofFIG.25A-1, andFIG.26B-3corresponds to cross-section III-III ofFIG.25A-1.

A gate structure GS1is formed to fill the gate trench132and the gaps133in the region102a, and it thereby wraps around the nanostructures of the second epitaxial layers108A, as shown inFIGS.26B-1and26B-3, in accordance with some embodiments. A gate structure GS2is formed to fill the gate trench132and the gaps133in the region102b, and it thereby wraps around the nanostructures of the second epitaxial layers108B, as shown inFIGS.26B-2and26B-3, in accordance with some embodiments.

The interfacial layers210of the gate structures GS1and GS2are formed to conform to the profile of the semiconductor capping layers404, in accordance with some embodiments. The interfacial layers210include extending portions210E along the inner side surfaces108S1and108S2of the end portions108E of the second epitaxial layer108and a flat portion210F located laterally between the extending portions210E, in accordance with some embodiments.

FIGS.27A-1to27B-3illustrate one or more steps of forming a semiconductor device during the method2000in accordance with some embodiments of the present disclosure. The structures shown inFIGS.27A-1to27B-3are similar to those shown inFIGS.25C-1to25D-3except for the thickness of the semiconductor capping layers404, in accordance with some embodiments.

FIGS.27A-1and27A-2illustrate cross-sectional views of a semiconductor structure after operation2004of the method2000in which semiconductor capping layers404are formed on the middle portions108M of the second epitaxial layers108, in accordance with some embodiments.FIG.27A-1corresponds to cross-section I-I or II-II ofFIG.25A-1, andFIG.27A-2corresponds to cross-section III-III ofFIG.25A-1.

Semiconductor capping layers404are formed around the recessed middle portions108M of the second epitaxial layers108at channel region, as shown inFIGS.27A-1and27A-2, in accordance with some embodiments. In some embodiments, the semiconductor capping layers404are formed to have a thickness D6in a range of about 0.5 nm to about 3 nm, as shown inFIGS.27A-1and27A-2. In some embodiments, the thickness D6is greater than the etching depth D2(FIG.25B-1).

A portion of the semiconductor capping layer404at its edge is thinner than a portion of the semiconductor capping layer404at its center, such that the semiconductor capping layer404has a convex outer surface, in accordance with some embodiments.

FIGS.27B-1to27B-3illustrate cross-sectional views of a semiconductor structure after operations1030of the method2000in which gate structures GS1and GS2are formed, in accordance with some embodiments.FIG.27B-1corresponds to cross-section I-I ofFIG.25A-1,FIG.27B-2corresponds to cross-section II-II ofFIG.25A-1, andFIG.27B-3corresponds to cross-section III-III ofFIG.25A-1.

A gate structure GS1is formed to fill the gate trench132and the gaps133in the region102a, and it thereby wraps around the nanostructures of the second epitaxial layers108A, as shown inFIGS.27B-1and27B-3, in accordance with some embodiments. A gate structure GS2is formed to fill the gate trench132and the gaps133in the region102b, and it thereby wraps around the nanostructures of the second epitaxial layers108B, as shown inFIGS.27B-2and27B-3, in accordance with some embodiments.

In some embodiments, portions of the high-k dielectric sheath layers230a(or the dielectric sheath layers250b) formed around neighboring second epitaxial layers108and are in contact with and merged with each other, as shown inFIGS.27B-1to27B-3, in accordance with some embodiments. Therefore, the metal layer260partially surrounds the second epitaxial layers108aand108band the gaps133are free of the metal layer260, in accordance with some embodiments.

FIGS.28A-1to28A-3illustrate one or more steps of forming a semiconductor device during the method2000in accordance with some embodiments of the present disclosure. The structures shown inFIGS.28A-1to28A-3are similar to those shown inFIGS.27B-1to27B-3except for the semiconductor capping layers404ahaving a thinner thickness than the semiconductor capping layers404b, in accordance with some embodiments.

The semiconductor capping layers404ain the region102a(such as NMOS region) and the semiconductor capping layers404bin the region102b(such as PMOS region) are formed separately to adjust the effective work functions of the gate structures GS1and GS2for N-type FET and P-type FET, in accordance with some embodiments. The semiconductor capping layers404aare formed to be thinner (e.g., thickness D5shown inFIG.26A-1), and the semiconductor capping layers404bare formed to be thicker (e.g., thickness D6shown inFIG.27A-1), in accordance with some embodiments. In some embodiments, the germanium concentration of semiconductor capping layer404ais less than the concentration of the semiconductor capping layer404b.

FIGS.29-1and29-2,FIGS.30-1and30-2,FIGS.31-1to31-2, andFIGS.32-1and32-2are cross-sectional views of modifications of the semiconductor devices ofFIGS.25D-1and25D-2,FIGS.26B-1and26B-2,FIGS.27B-1to27B-2, andFIGS.28-1to28-2, respectively, where the source/drain features126(or128) shown inFIG.29-1through32-2are formed adjoining to but not surrounding the nanostructures108A (or108B). The formation of the source/drain features126and128includes recessing the fin elements112including the epitaxial layers106and108(FIG.6A) to form source/drain recesses (not shown) at the source/drain regions, in accordance with some embodiments. The dummy gate stack118and the spacers125may be used as etching mask. Afterward, one or more semiconductor material for the source/drain features126and128are grown on the fin elements112from the source/drain recesses using epitaxial growth processes, in accordance with some embodiments. The source/drain features126adjoin the end portions108E of the nanostructures108A, in accordance with some embodiments. The source/drain features128adjoin the end portions108E of the nanostructures108B, in accordance with some embodiments.

FIGS.29-1and29-2,FIGS.30-1and30-2,FIGS.31-1to31-2, andFIGS.32-1and32-2are cross-sectional views of modifications of the semiconductor devices ofFIGS.25D-1and25D-2,FIGS.26B-1and26B-2,FIGS.27B-1to27B-2, andFIGS.28-1to28-2, respectively, where the source/drain features126(or128) shown inFIG.29-1through32-2are formed adjoining to but not surrounding the nanostructures108A (or108B). The formation of the source/drain features126and128includes recessing the fin elements112including the epitaxial layers106and108(FIG.6A) to form source/drain recesses (not shown) at the source/drain regions, in accordance with some embodiments. The dummy gate stack118and the spacers125may be used as etching mask. Afterward, one or more semiconductor material for the source/drain features126and128are grown on the fin elements112from the source/drain recesses using epitaxial growth processes, in accordance with some embodiments. Because the portions of the fin elements112uncovered by the dummy gate stack118and the spacers125are removed, the end portion108E of the nanostructures108are formed below the spacers125. The source/drain features126adjoin the end portions108E of the nanostructures108A, in accordance with some embodiments. The source/drain features128adjoin the end portions108E of the nanostructures108B, in accordance with some embodiments.

As described above, the semiconductor device includes a set of nanostructures108A, and each of the set of nanostructures108includes end portions108E and a middle portion108M between the end portions108E. The end portions108E are thicker than the middle portion108M. The semiconductor device also includes a plurality of semiconductor capping layers404formed around the middle portions108M of the set of nanostructures108A, and a gate structure GS1or GS2formed around the plurality of semiconductor capping layers404a. Because the middle portion108M is thinner than the end portions108E, the space between the middle portions108M of neighboring nanostructures (i.e., the enlarged gap133) may be filled with more work function adjustment layers, e.g., the semiconductor capping layers404, the dielectric sheath layers230or250, and/or metal layer260. Therefore, the embodiments of the present disclosure may provide greater processing flexibility to achieve various transistors having different threshold voltages in a semiconductor substrate.

Embodiments of a semiconductor device may be provided. The semiconductor device includes a set of nanostructures with middle portions thinner than end portions, a plurality of semiconductor capping layers formed around the thinner middle portions of the nanostructures, and a gate structure formed around the semiconductor capping layers. Since the middle portion is thinner than the end portions, the space between the middle portions of neighboring nanostructures may be filled with more work function adjustment layers. Therefore, various transistors having different threshold voltages in a semiconductor substrate may be achieved.

According to various embodiments of the present disclosure, a semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures comprises a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.

According to various embodiments of the present disclosure, a semiconductor device includes nanostructures stacked over a substrate in a vertical direction. The nanostructures comprise a first nanostructure, and the first nanostructure comprises a first end portion having a first inner side surface, a second end portion having a second inner side surface facing the first inner side surface, and a middle portion laterally between the first end portion and the second end portion. The semiconductor device also includes a first gate spacer and a second gate spacer covering the first end portion and the second end portion of the first nanostructure respectively, and a silicon germanium layer extending from the first inner side surface of the first end portion of the first nanostructure to the second inner side surface of the second end portion of the first nanostructure.

According to various embodiments of the present disclosure, a semiconductor device includes an n-type nanostructure transistor in a first region of a substrate and a p-type nanostructure transistor in a second region of the substrate. The n-type nanostructure transistor includes a first nanostructure, a first SiGe layer wrapping around the first nanostructure, and a first gate dielectric layer wrapping around the first SiGe layer. The p-type nanostructure transistor includes a second nanostructure, a second SiGe layer wrapping around the second nanostructure, and a second gate dielectric wrapping around the second SiGe layer. A germanium concentration of the first SiGe layer is less than a germanium concentration of the second SiGe layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.