Patent ID: 12237834

The contents shown inFIGS.1-5are provided only for helpfully illustrating the embodiments of the present disclosure, instead of limiting the scope of the present disclosure.

DETAILED DESCRIPTION OF THE INVENTION

FIG.1depicts a schematic view of an electronic device for overcurrent detection according to one or more embodiments of the present disclosure. Referring toFIG.1, an electronic device1for overcurrent detection (“electronic device1” for short) of the present disclosure may be coupled with a power stage2and a driver3of the power stage2. The electronic device1may generally be configured to monitor a current C01flowing through an upper-bridge power component21of the power stage2to a load L1and/or a current C02flowing from the load L1(as shown inFIG.4) to a lower-bridge power component22of the power stage2, and respectively perform high-side and low-side overcurrent detections therefor. Correspondingly, the electronic device1may comprise a high-side overcurrent detection circuit11and a low-side overcurrent detection circuit12. When a high-side overcurrent event occurs, the high-side overcurrent detection circuit11, in general, may detect the high-side overcurrent event and provide a high-side OCP signal HS1for the driver3to take necessary actions. Similarly, when a low-side overcurrent event occurs, the low-side overcurrent detection circuit12, in general, may detect the low-side overcurrent event and provide a low-side OCP signal LS1for the driver3to take necessary actions.

The power stage2may be implemented based on wide bandgap semiconductors such as GaN, Silicon Carbide (SiC), Vertical Double-Diffused Metal-Oxide-Semiconductor (VDMOS), Lateral Double-Diffused Metal-Oxide-Semiconductor (LDMOS), or the like. The wide bandgap characteristic allows the power stage2to operate at middle or high voltage domains (e.g., from a few hundred volts to even over 1,000 volts.)

The upper-bridge power component21may be coupled with a DC power supply PS1and the load L1and may be turned on/off by applying an upper-bridge control signal UG to the upper-bridge control signal terminal of the upper-bridge power component21. The lower-bridge power component22may be coupled with the load L1and a ground level and may be turned on/off by applying a lower-bridge control signal LG to the lower-bridge control signal terminal of the lower-bridge power component22. When the upper-bridge power component21is turned on, current flows from the positive terminal of the power supply PS1, through the load L1, and then back to the negative terminal of the power supply PS1. When the upper-bridge power component21is turned off, the lower-bridge power component22is turned on and allows current to flow in the opposite direction as shown inFIG.4.

The load L1may be one or more electronic devices that accept the power supplied from the power stage2and may be, for example, any components used in an audio system.

The driver3may generally be configured to provide the required electrical signals to control and/or drive the power stage2efficiently. A fast-charging device such as a GaN-based charger typically has high gate capacitance and requires precise voltage and current waveforms to switch on and off rapidly. The driver3ensures that the gate voltage and current are properly controlled, allowing the charging device to operate optimally.

The high-side overcurrent detection of electronic device1mainly focuses on the upper-bridge power component21, whereas the low-side current protection mainly focuses on the lower-bridge power component22. Once a high-side overcurrent event occurs, the electronic device1may detect the event and thus provide the high-side OCP signal HS1with logic high for the driver3to turn off the upper-bridge power component21. Similarly, when a low-side overcurrent event occurs, the electronic device1may the event and thus provide the low-side OCP signal LS1with logic high for the driver3to turn off the lower-bridge power component22.

FIG.2depicts a schematic view of a feasible structure of the high-side overcurrent detection circuit11of the electronic device1inFIG.1. Referring to bothFIG.1andFIG.2, the high-side overcurrent detection circuit11may basically comprise a high-side V2I converter111, voltage offsetting component112, a first high-side comparator113, and a high-side OCP signal generator114. The voltage offsetting component112may be coupled with the high-side V2I converter111. The first high-side comparator113may be coupled with the voltage offsetting component112, the high-side V2I converter111, and the high-side OCP signal generator114.

To monitor the current flowing through the upper-bridge power component21after the upper-bridge power component21is turned on, the high-side V2I converter111may be coupled with an input terminal (i.e., the node N1shown inFIG.2) and an output terminal (i.e., the node N2shown inFIG.2) of the upper-bridge power component21. The input terminal of the upper-bridge power component21may refer to the terminal where the current from the power supply PS1enters the upper-bridge power component21, and the output terminal may refer to the terminal where the current from the power supply PS1exits the upper-bridge power component21.

The voltage offsetting component112may be configured to cause a high-side offsetting voltage drop VOS1, and the high-side V2I converter111may be configured to convert a voltage difference between a first voltage V1 watched at the node N1and a sum of the high-side offsetting voltage drop VOS1and a first balancing voltage drop caused by the high-side OCP signal generator114into a first current C1. On the other hand, the high-side V2I converter111may also be configured to convert a voltage difference between a second voltage V2 watched at the node N2and a second balancing voltage drop caused by the first high-side comparator113into a second current C2.

The high-side V2I converter111may comprise a first resistor R1coupled with the node N1and a second resistor R2coupled with the node N2as shown inFIG.2. Each of the first resistor R1and the second resistor R2may be a single resistor, or a combination of multiple resistors coupled in series, depending on different situations.

The voltage offsetting component112may comprise one or more transistors coupled in series, depending on different situations. In some embodiments, each transistor of the voltage offsetting component112may be a diode-connected metal oxide semiconductor field effect transistor (MOSFET), i.e., a MOSFET whose gate electrode is connected to the drain electrode or a diode-connected bipolar junction transistor (BJT), i.e., a BJT whose base is connected to the collector.) A transistor with a diode-connected structure may conduct current in both directions, just like a diode. Moreover, a transistor with a diode-connected structure will cause a voltage drop when there is a current flowing therethrough, i.e., the gate-source voltage of the diode connected transistor, just like a diode.

The first high-side comparator113may be implemented as a current mirror that includes two transistors T1and T2as the master and slave transistors, respectively. The transistor T1may be coupled with the second resistor R2. The transistor T1may also be a diode-connected MOSFET or a diode-connected BJT, and thus will inevitably introduce a voltage drop (i.e., the gate-source voltage of the diode connected transistor T1) to the formation of the second current C2, which is previously referred to as the “second balancing voltage drop.” In response, the same amount of voltage drop may be introduced to the formation of the first current C1in addition to the high-side offsetting voltage drop VOS1, such that the “competition” between the first current C1and the second current C2remains fair, and this is where the high-side OCP signal generator114comes into play.

The high-side OCP signal generator114may comprise an AND gate114G, a first inverter114V and a second high-side comparator114M coupled with the first high-side comparator113and the first inverter114V, in which the second high-side comparator114M may be implemented as another current mirror that comprises two transistors T3and T4as the master and slave transistors, respectively. The transistor T3may be identical to the transistor T1, which means it may also be diode-connected and may cause the same amount of voltage drop. Therefore, a voltage drop may be caused by the transistor T3to the formation of the first current C1, thereby balancing the voltage drop caused by the diode-connected transistor T1. The voltage drop caused by the transistor T3is previously referred to as the “first balancing voltage drop” and is of the same amount as the voltage drop caused by the transistor T1.

The formations of the currents C1and C2are described with further details as follows. Still referring toFIG.1andFIG.2, the first voltage V1 is at nearly the same voltage level with the power supply PS1, e.g., around 100 volts. The high-side voltage offsetting component112may be used to form or cause the high-side offsetting voltage drop VOS1to serve as a voltage drop offset by the first voltage V1. The first resistor R1with certain resistance (e.g., 500,000 ohms) may be used to convert the voltage difference between the first voltage V1 and the sum of the high-side offsetting voltage drop VOS1and the first balancing voltage drop into an current form, i.e., the first current C1. On the other hand, the second resistor R2with certain resistance may be used to convert the second voltage V2 into the second current C2. The second resistor R2may include same amount of resistance as the first resistor R1, e.g., 500,000 ohms.

Accordingly, the current magnitudes of the first current C1and the second current C2may be formulated by the following equation:

IC⁢1=VN⁢1-VOS⁢1-VtRR⁢1(Equation⁢1)IC⁢2=VN⁢2-VtRR⁢2=VN⁢1-VDS-VtRR⁢2(Equation⁢2)wherein:IC1represents the current magnitude (current value) of the first current C1;IC2represents the current magnitude (current value) of the second current C2;VN1represents the voltage level watched at the node N1, which is almost the same as the voltage provided by the power supply PS1in the case shown inFIG.2;VN2represents the voltage level watched at the node N2, and equals “VN1minus the voltage drop VDSthat is caused by the upper-bridge power component21”;VOS1represents the voltage across the high-side voltage offsetting component112;Vtrepresents the first balancing voltage drop as well as the second balancing voltage drop for Ic1and Ic2respectively;RR1represents the resistance of the first resistor R1; andRR2represents the resistance of the second resistor R2.

Note that the first and second voltages V1 and V2 indicate high voltage due to the high-voltage power supply PS1(e.g., around 100 volts), so they cannot be measured and compared directly by regular low-voltage controllers that allows, e.g., only around 5-10 volts, let alone triggering a high-side OCP. To overcome this problem, the first resistor R1(in cooperation with the high-side voltage offsetting component112) and the second resistor R2of the high-side V2I converter111may be used to serve as a clamping mechanism to ensure that the rest components of the high-side overcurrent detection circuit11may work well in the low-voltage domain.

The high-side offsetting voltage drop VOS1may generally be regarded as a threshold for evaluating the voltage drop caused by the upper-bridge power component21(i.e., the “VDS” shown in Equation 2.) That is, a high-side overcurrent event (e.g., when the current C01is around 100 amp) may be detected when the voltage drop caused by the upper-bridge power component21is greater than the voltage drop caused by the high-side voltage offsetting component112, which means at that time the current flows to the load L1is abnormally large.

The first high-side comparator113may be configured to compare the first current C1and the second current C2and generate/output an output CS11accordingly. Specifically, the transistor T1may be coupled with the second resistor R2in series to receive the second current C2, and the transistor T2may be coupled with the high-side voltage offsetting component112in series to receive the first current C1. With the function of the current mirror, the second current C2may be replicated from the current input terminal of the current mirror to the current output terminal of the current mirror. Thus, the first current C1and the sensed/replicated second current C2meet and “compete” at a node N3between the high-side voltage offsetting component112and the transistor T2and jointly form the output CS11of the first high-side comparator113at the node N3. In other words, the output CS11of the first high-side comparator113equals “the first current C1minus the second current C2”.

In some embodiments, there may be another transistor T0whose gate is controlled by the upper-bridge control signal UG coupled between the second resistor R2and the transistor T1. As the lower-bridge power component22is turned on (i.e., the upper-bridge power component21is turned off), the upper-bridge control signal UG will make the transistor T0turned off either. Thus, the transistor T0may prevent current C02from flowing to the high-side overcurrent detection circuit11during the lower-bridge power component22being turned on.

As shown inFIG.2, when the first current C1is stronger than the second current C2, there will be a current flowing from the node N3to the high-side OCP signal generator114of the electronic device1, and thus, the output CS11of the first high-side comparator113presents logic high. In contrast, when the first current C1is weaker than the second current C2, there will be a current flowing from the high-side OCP signal generator114to the node N3, and thus, the output CS11of the first high-side comparator113presents logic low.

The output CS11of the first high-side comparator113may, to a certain level, indicate whether a high-side overcurrent event has been detected. More specifically, based on Equations 1 and 2, the comparison of the first C1and the second current C2may be further formulated by the following equation:

IC⁢1-IC⁢2={VN⁢1-VOS⁢1-VtRR⁢1-VN⁢1-VDS-VtRR⁢2VDS-VOS⁢1RR⁢1=VDS-VOS⁢1RR⁢2,if⁢RR⁢1=RR⁢2(Equation⁢3)
When RR1equals to RR2, it may further be concluded that the difference between IC1and IC2becomes positively correlated with the difference between VDS(i.e., the voltage drop caused by the upper-bridge power component21) and VOS1, (i.e., the voltage drop caused by the high-side voltage offsetting component112.) Under this circumstance, IC1being greater than IC2means that VDSis greater than VOS1, which further means that the voltage drop caused by the upper-bridge power component21is greater than the predetermined threshold of voltage drop represented by the high-side offsetting voltage drop VOS1. This indicates that too much current has flowed through the upper-bridge power component21and then been supplied to the load L1.

Note that the difference between IC1and IC2is still capable of indicating the relationship between VOS1and VDSto some level even when RR1does not equal to RR2, and a person having ordinary skill in the art may realize how to make certain adjustments based on Equation 3 and related descriptions mentioned above.

The second high-side comparator114M may be configured to compare the output CS11of the first high-side comparator113with a first reference current of a first reference current source RC1and provide an output CS12for an input of the first inverter114V. To do so, the transistor T3may provide a current input terminal of the current mirror, and the current input terminal is coupled with the node N3to receive the output CS11of the first high-side comparator113. With the function of the current mirror, the output CS11of the first high-side comparator113may be replicated from the current input terminal of the current mirror to the current output terminal of the current mirror provided by the transistor T4. In addition, the transistor T4may be coupled with first reference current source RC1in series to receive the first reference current. Thus, the output CS11of the first high-side comparator113and the first reference current meet and “compete” at a node N4and jointly form the output CS12of the second high-side comparator114M for the input of the first inverter114V. In other words, the output CS12of the second high-side comparator114M equals the first reference current minus the output CS11of the first high-side comparator113.

As shown inFIG.2, the output CS12of the second high-side comparator114M will present logic high when the first reference current is stronger than the output CS11of the first high-side comparator113and will present logic low when the first reference current is weaker than the output CS11of the first high-side comparator113. The output of the first inverter114V, accordingly, presents logic high when the output CS12of the second high-side comparator114M presents logic low, namely when the output CS11of the first high-side comparator113is stronger than the first reference current.

The output signal of the first invertor114V may be provided to the AND gate114G as one of the inputs of the AND gate114G, and the upper-bridge control signal UG may be provided as the other input of the AND gate114G. The high-side OCP signal HS1will present logic high when both of the output signal of the first invertor114V and the upper-bridge control signal UG are logic high and will trigger the driver3to turn off the upper-bridge power component21for overcurrent protection accordingly.

In some embodiments, the upper-bridge control signal UG may be debounced for a certain period, e.g., 100 ns, to avoid misjudgment of an overcurrent event at the initial phases of the upper bridge. More specifically, for high-side over current detection, the debouncing of the upper-bridge control signal UG needs to cover the setting of the voltage between the drain and source of the transistor. For example, in the system ofFIG.2, the first voltage V1 provided by the power supply PS1is around 100 volts, and the second voltage V2 would rise from 0 volt towards 100 volts. The debouncing time should be able to cover the slew rate of the second voltage V2 from 0 volt to at least the difference between 100 volts and “I*RDS,” which may be over or around 100 ns, depending on the system configuration. The debouncing time may be fine-tuned according to different types of application.

The first reference current provided by the first reference current source RC1as described above may serve as additional threshold for determining whether a high-side overcurrent event occurs. In this case, the high-side overcurrent event will be detected when not only is the first current C1stronger than the second current C2, but also is the output CS11of the first high-side comparator113, a.k.a. the difference between the first current C1and the second signal C2, stronger than the first reference current (e.g., 1 uA when the resistance of the first resistor R1is 500,000 ohms.) This means that the threshold for evaluating/estimating the voltage drop caused by upper-bridge power component21is adjusted from “the high-side offsetting voltage drop VOS1only” to “the voltage drop caused by the first reference current (in cooperation with the first resistor R1) plus the high-side offsetting voltage drop VOS1”, which can be formulated by the following equation:
VDSI1=VOS1+IRE1×RR1=VOS1+VADJ1(Equation 4)wherein:VDSI1represents the threshold of the voltage drop of the upper-bridge power component21;VOS1represents the voltage drop caused by the high-side voltage offsetting component112;IRE1represents the current magnitude (current value) of the first reference current;RR1represents the resistance of the first resistor R1; andVADJ1represents the voltage drop caused by IRE1and RR1.

As can be seen from Equation 4, with the threshold being raised up by the first reference current, the voltage drop caused by the upper-bridge power component21(i.e., VDSin Equations 2 and 3) needs to be greater than it used to be when without the threshold adjusting mechanism, unless the first reference current is set to only slightly over 0 amp. In some embodiments, the voltage drop caused by the first reference current and the first resistor R1(i.e., “VADJ1” in Equation 3) may normally be set to, for example but not limited to, 2 volts, whereas in some other embodiments, the voltage drop caused by the first reference current and the first resistor R1may be set to a bare minimum (i.e., only slightly over 0 volt) such that there is barely a further adjustment performed to the threshold of voltage drop.

As previously described, the voltage offsetting component112, in some embodiments, may comprise one or more transistors coupled in series, depending on different situations. However, in some other embodiments, the voltage offsetting component112may alternatively comprise an offsetting resistor, as shown inFIG.3. The offsetting resistor may be a single resistor, or a combination of multiple resistors coupled in series, depending on different situations.

FIG.3depicts a schematic view of an alternative of the high-side overcurrent detection circuit11of the electronic device inFIG.2. Referring toFIG.3, the high-side offsetting voltage drop VOS1may be provided by the offsetting resistor and an additional offsetting current C10flowing through the offsetting resistor, since the voltage across a circuit is equal to the product of the current flowing through the circuit and the resistance of the circuit. The resistance of the offsetting resistor may be determined based on the estimated voltage drop caused by the upper-bridge power component21, considering the offsetting current C10.

With the addition of the offsetting current C10, the current magnitude of the first current C1may thus be adjusted according to the following equation:

IC⁢1=VN⁢1-VOS⁢1-VtRR⁢1+IOS(Equation⁢5)whereinIC1represents the current magnitude (current value) of the first current C1;VN1represents the voltage level watched at the node N1, which is almost the same as the voltage provided by the power supply PS1in the case shown inFIG.2;VOS1represents the voltage drop caused by the voltage offsetting component112;Vtrepresents the first balancing voltage drop;RR1represents the resistance of the first resistor R1; andIOSrepresents the magnitude (current value) of the offsetting current C10.

In response to adding the offsetting current C10to the first current C1, an equal amount of current is also added to the second current C2described in Equation 2. This ensures that the comparison between the first current C1and the second current C2remains balanced. Thus, the current magnitude of the second current C2may also be adjusted according to the following equation:

IC⁢2=VN⁢1-VDS-VtRR⁢2+IOS(Equation⁢6)wherein:IC2represents the current magnitude (current value) of the second current C2;VN2represents the voltage level watched at the node N2, and equals VN1minus the voltage drop VDSthat is caused by the upper-bridge power component21;Vtrepresents the second balancing voltage drop;RR2represents the resistance of the second resistor R2; andIOSrepresents the current magnitude (current value) of the offsetting current C10.

FIG.4depicts a schematic view of a feasible structure of the low-side overcurrent detection circuit12of the electronic device inFIG.1. Referring to bothFIG.1andFIG.4, the low-side overcurrent detection circuit12may be coupled with the lower-bridge power component22of the power stage2to monitor the current C02flowing therethrough during the lower-bridge power component22being turned on (i.e., the upper-bridge power component UG is turned off) such that the lower-bridge power component22may be timely turned off after a low-side overcurrent event occurs.

The low-side overcurrent detection circuit12may comprise a low-side V2I converter121coupled with the lower-bridge power component22, a low-side voltage offsetting component122coupled with the low-side V2I converter121, a low-side comparator123coupled with low-side voltage offsetting component122, and a low-side OCP signal generator124coupled with an output of the low-side comparator123(i.e., a node N6shown inFIG.4.)

The low-side voltage offsetting component122may be configured to cause a low-side offsetting voltage drop VOS2, and the low-side V2I converter121may be configured to convert a voltage difference between a third voltage V3 watched at an input terminal (i.e., at a node N5shown inFIG.4) of the lower-bridge power component22and the low-side offsetting voltage drop VOS2into a third current C3. The low-side V2I converter121may comprise a third resistor R3coupled with the low-side voltage offsetting component122. The third resistor R3may be a single resistor, or a combination of multiple resistors coupled in series, depending on different situations. The low-side offsetting voltage drop VOS2may be caused/formed based on the low-side voltage offsetting component122, and the third resistor R3with certain resistance (e.g., 1,000 ohm) may be used to convert the voltage difference between the low-side offsetting voltage drop VOS2and the third voltage V3 into the third current C3.

The current magnitude of the third current C3may be formulated by the following equation:

IC⁢3=VN⁢5-VOS⁢2RR⁢3(Equation⁢7)wherein:IC3represents the current magnitude (current value) of the third current C3;VN5represents the voltage level watched at the node N5(i.e., the third voltage V3);VOS2represents the voltage drop caused by the low-side voltage offsetting component122; andRR3represents the resistance of the third resistor R3.

In some embodiments, the low-side voltage offsetting component122may comprise one or more transistors coupled in series, just like the high-side voltage offsetting component112does. In some embodiments, the low-side voltage offsetting component122and the low-side comparator123may share the transistor T5inFIG.4, and the gate-source voltage of the transistor T5(e.g., around 0.7 volts) may be included in the voltage “VOS2” in Equation 7 when the transistor T5is shared by the low-side voltage offsetting component122and the low-side comparator123. Each transistor of the low-side voltage offsetting component122and the transistor T5may be a diode-connected MOSFET or a diode-connected BJT.

In some embodiments, the low-side V2I converter121may adopt the second resistor R2of the high-side V2I converter111to serve as the third resistor R3, since the two circuits function alternately in a time-wise manner. Note that the resistance “RR3” in Equation 7 is equal to “RR2” in Equations 2, 3, and 6 when the second resistor R2is shared by the high-side V2I converter111and the low-side V2I converter121.

The low-side comparator123, in general, may be configured to compare the third current C3with a second reference current provided by a second reference current source RC2. In some embodiments, like the first and second high-side comparators112and114M, the low-side comparator123may also be implemented as a current mirror that includes two transistors T5and T6as a master and a slave, respectively. The transistor T5may be coupled with the low-side voltage offsetting component122in series to receive the third current C3. With the function of the current mirror, the third current C3may be replicated from the current input terminal of the current mirror (provided by the transistor T5) to the current output terminal of the current mirror (provided by the transistor T6.) In addition, the transistor T6may be coupled with second reference current source RC2in series to receive the second reference current. Thus, the third current C3and the second reference current meet and “compete” at the node N6and jointly form an output CS2of the low-side comparator123at the node N6. In other words, the output CS2of the low-side comparator123equals the second reference current minus the third current C3.

The low-side comparator123may provide the output CS2of the low-side comparator123according to the result of “competition” at the node N6. Specifically, the output CS2of the low-side comparator123will present logic high when the second reference current is stronger than the third current C3at the node N6. The output CS2of the low-side comparator123will present logic low when the third current C3is stronger than the second reference current at the node N6.

The low-side OCP signal generator124may comprise a second inverter124V and a second AND gate124G. The second inverter124V may be coupled with the low-side comparator123at the node N6, while the second AND gate124G may be coupled with an output of the second inverter124V and the lower-bridge control signal terminal of the lower-bridge power component22. The second AND gate124G may output the low-side OCP signal LS1with logic high for the driver3to turn off the lower-bridge power component22when a low-side overcurrent event is detected.

As shown inFIG.4, the low-side OCP signal LS1will present logic high when the lower-bridge control signal LG present logic high and the output CS2of the low-side comparator123present logic low. In some embodiments, the lower-bridge control signal LG may be debounced for a certain period, e.g., 100 ns, to avoid misjudgment of a low-side overcurrent event at the initial phases of the lower bridge.

The output CS2of the low-side comparator123being logic low means not only that the third voltage V3 is stronger than the low-side offsetting voltage drop VOS2, but also that the third current C3is stronger than the second reference current of the second reference current source RC2. This brings two thresholds for determining whether a low-side overcurrent event occurs, i.e., the low-side offsetting voltage drop VOS2and the second reference current.

When a low-side overcurrent (or short circuit) event has been detected, the voltage level watched at the input terminal (i.e., at the node N5shown inFIG.4) of the lower-bridge power component22, which should have been kept low to near the ground level, would be pulled up to an undesired high level, e.g., near the voltage level of the power supply PS1. Therefore, an undesired current output to the load L1is likely to exist even during the upper-bridge power component21being turned off. The low-side offsetting voltage drop VOS2(e.g., 1.4 volts, which equals twice the gate-source voltage) may serve as a threshold for estimating the voltage level watched at the node N5.

As to the second reference current, in some embodiments, it may be set to a bare minimum (e.g., only slightly over 0 amp) for triggering the function of the low-side comparator123, such that the determination of a low-side overcurrent event is based on the third current C3only. However, in some other embodiments, like the first reference current source RC1, the second reference current may serve as an adjusting mechanism of the threshold for determining whether a low-side overcurrent event occurs. In this case, the low-side overcurrent event will be detected when the third current C3is stronger than second reference current (e.g., 1 uA when the resistance of the second resistor R2or the third resistor R3is 500,000 ohms.) This means that the threshold for evaluating/estimating the voltage level at the lower-bridge power component22is adjusted from “the low-side offsetting voltage drop VOS2only” to “the low-side offsetting voltage drop VOS2plus the voltage drop caused by the second reference current (in cooperation with the third resistor R3)”, which can be formulated by the following equation:
VDSI2=VOS2+IRE2×RR3=VOS2+VADJ2(Equation 8)wherein:VDSI2represents the threshold of the voltage level watched at the node N5;VOS2represents the voltage drop caused by the low-side voltage offsetting component122;IRE2represents the current of the second reference current;RR3represents the resistance of the third resistor R3; andVADJ2represents the voltage drop caused by IRE2and RR3.

Note that in the embodiments where the second resistor R2is shared by the high-side V2I converter111and the low-side V2I converter121, the resistance “RR3” in Equation 8 is also equal to “RR2” in Equations 2, 3, and 6.

In some embodiments, the electronic device1, the power stage2, and the driver3may be implemented in the same package. The package may be implemented based on technologies such as Wafer Level Fan-Out (WLFO) packaging, low thermal resistance heat conduction lead frame, extra substrate, etc.

Based on the above descriptions, the electronic device1of the present disclosure provides a good way of performing high-side overcurrent detection and protection as well as low-side overcurrent detection and protection, and both of which can be achieved by the level-shifting and V2I mechanisms in the low-voltage hardware.

As disclosed, the resistors are adopted to endure and cope with the high voltage levels, such that the high-side overcurrent detection circuit11and the low-side overcurrent detection circuit12of the electronic device1of the present disclosure can smoothly shift the high-voltage levels applied to the upper-bridge power component21to a low-voltage domain. Thus, the voltage applied to the electronic device1may be clamped with a low voltage level such that the components of the electronic device1can work well in the low-voltage domain.

As disclosed, the V2I mechanisms are adopted to convert the concerned voltages for determining whether an overcurrent event occurs into currents (i.e., the first current C1, the second current C2, and the third current C3), and thus, the overcurrent detection and protection can be achieved in a current form instead of a voltages form. The proposed method well outperforms the conventional way of using partial voltages signals for overcurrent detection and protection, because it can keep the target voltage difference from being “diluted” to a partial voltage that is too subtle to implement when attempting to shift the high voltage signals (e.g., 100 volts) to low-voltage voltage signals (5 volts) and when the voltage difference of the high voltage signals is subtle (e.g., 2 millivolt from 100 volts and 98 volts.) The conversion and comparison of currents performed in the present disclosure jointly “reflects” the condition (i.e., whether it is) of the voltage drop caused by the upper-bridge power component21(as shown in the Equation 5 above), while the offsetting mechanism performed in the present disclosure ensures the comparison between the voltage drop caused by the upper-bridge power component21and the threshold, thus achieving the effect of OCP that is based on the comparison of currents.

FIG.5depicts a method for overcurrent detection according to one or more embodiments of the present disclosure. Referring toFIG.5, a method5for overcurrent detection (“method5” for short) may comprise steps as follows:causing, by a high-side voltage offsetting component, a high-side offsetting voltage drop (labeled as step501);converting, by a high-side voltage-to-current (V2I) converter, a voltage difference between a sum of a first balancing voltage drop caused by a high-side OCP signal generator and the high-side offsetting voltage drop and a first voltage at an input terminal of an upper-bridge power component of a power stage into a first current (labeled as step502);converting, by the high-side V2I converter, a voltage difference between a second voltage of an output terminal of the upper-bridge power component and a second balancing voltage drop caused by a first high-side comparator coupled with the high-side V2I converter into a second current (labeled as step503);comparing, by the first high-side comparator, the first current and the second current (labeled as step504); andgenerating, by the high-side OCP signal generator, a high-side OCP signal with logic high for a driver of the power stage when the first current is stronger than the second current, such that the driver turns off the upper-bridge power component accordingly (labeled as step505).

In some embodiments, regarding the method5, the voltage difference between the first voltage and the sum of the high-side offsetting voltage drop and the first balancing voltage drop may be converted into the first current via a first resistor of the high-side V2I converter, the first resistor being coupled with the high-side voltage offsetting component. Moreover, the second voltage is converted into the second current via a second resistor of the high-side V2I converter, the second resistor being coupled with the output terminal of the upper-bridge power component and the first high-side comparator. In some embodiments, the first high-side comparator may further be a first current mirror, and the first current mirror may further include a first transistor coupled with the second resistor and a second transistor coupled with the high-side voltage offsetting component, and the second balancing voltage drop may be caused by the first transistor.

In some embodiments, regarding the method5, the voltage difference between the first voltage and the sum of the high-side offsetting voltage drop and the first balancing voltage drop may be converted into the first current via a first resistor of the high-side V2I converter, the first resistor being coupled with the high-side voltage offsetting component. Moreover, the second voltage is converted into the second current via a second resistor of the high-side V2I converter, the second resistor being coupled with the output terminal of the upper-bridge power component and the first high-side comparator. Moreover, in some embodiments, the high-side voltage offsetting component may further comprise at least one diode-connected metal oxide semiconductor field effect transistor or at least one diode-connected bipolar junction transistor to cause the high-side offsetting voltage drop.

In some embodiments, regarding the method5, the voltage difference between the first voltage and the sum of the high-side offsetting voltage drop and the first balancing voltage drop may be converted into the first current via a first resistor of the high-side V2I converter, the first resistor being coupled with the high-side voltage offsetting component. Moreover, the second voltage is converted into the second current via a second resistor of the high-side V2I converter, the second resistor being coupled with the output terminal of the upper-bridge power component and the first high-side comparator. In addition, in some embodiments, the high-side voltage offsetting component may further comprise an offsetting resistor flowed through by an offsetting current to cause the high-side offsetting voltage drop, and each of the first current and the second current may include the offsetting current.

In some embodiments, regarding the method5, the voltage difference between the first voltage and the sum of the high-side offsetting voltage drop and the first balancing voltage drop may be converted into the first current via a first resistor of the high-side V2I converter, the first resistor being coupled with the high-side voltage offsetting component. Moreover, the second voltage is converted into the second current via a second resistor of the high-side V2I converter, the second resistor being coupled with the output terminal of the upper-bridge power component and the first high-side comparator. In some embodiments, the method5may further comprise the steps of: “comparing, by a second high-side comparator of a high-side OCP signal generator, an output of the first high-side comparator with a first reference current of a first reference current source,” “providing, by the second high-side comparator, an output of the second high-side comparator for an input of a first inverter high-side OCP signal generator, wherein the first inverter is coupled with the second high-side comparator, and the output of the second high-side comparator is logic low when the output of the first high-side comparator is stronger than the first reference current,” and “outputting, by a first AND gate of the high-side OCP signal generator, the high-side OCP signal with logic high for the driver to turn off the upper-bridge power component, wherein the first AND gate is coupled with an output of the first inverter and an upper-bridge control signal terminal of the upper-bridge power component.” Additionally, in some embodiments, the second high-side comparator may be a second current mirror, and the second current mirror may include a third transistor coupled with a second transistor of a first current mirror and a fourth transistor coupled with the first reference current source, such that the output of the first high-side comparator and the first reference current jointly form the output of the second high-side comparator.

In some embodiment, the method5may further comprise the steps of: “causing, by a low-side voltage offsetting component coupled with the low-side comparator, a low-side offsetting voltage drop,” “converting, by a low-side V2I converter coupled with the low-side voltage offsetting component and a lower-bridge power component of the power stage, a voltage difference between the low-side offsetting voltage drop and a third voltage at an input terminal of the lower-bridge power component into a third current,” and “comparing, by a low-side comparator coupled with the low-side V2I converter, the third current with a second reference current and generating an output that indicates a low-side overcurrent event has been detected when the third current is stronger than the second reference current, such that the lower-bridge power component is turned off by the driver.” Moreover, in some further embodiments, the method5may further comprise a step of “outputting, by a second AND gate of a low-side OCP signal generator, a low-side OCP signal with logic high for the driver to turn off the lower-bridge power component accordingly.” In these further embodiments, the second AND gate may be coupled with an output of a second inverter of the low-side OCP signal generator and a lower-bridge control signal terminal of the lower-bridge power component, and the second inverter may be coupled with the low-side comparator to receive the output of the low-side comparator, wherein the output of the low-side comparator is logic low when the third current is stronger than the second reference current.

Each embodiment of the method5basically corresponds to a certain embodiment of the electronic device1. Therefore, those of ordinary skill in the art may fully understand and implement all the corresponding embodiments of the method5simply by referring to the above descriptions of the electronic device1, even though not all the embodiments of the method5are described in detail above.

The above disclosure is related to the detailed technical contents and inventive features thereof. People of ordinary skill in the art may proceed with a variety of modifications and replacements based on the disclosures and suggestions of the invention as described without departing from the characteristics thereof. Nevertheless, although such modifications and replacements are not fully disclosed in the above descriptions, they have substantially been covered in the following claims as appended.