Patent ID: 12218114

DETAILED DESCRIPTION OF THE DRAWINGS

The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.

Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, and resistors, create a relationship between voltage and current necessary to perform electrical circuit functions.

Back-end manufacturing refers to cutting or singulating the finished wafer into the individual semiconductor die and packaging the semiconductor die for structural support, electrical interconnect, and environmental isolation. To singulate the semiconductor die, the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections can be made with conductive layers, bumps, stud bumps, conductive paste, bond wires, or other suitable interconnect structure. An encapsulant or other molding compound is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.

FIG.1ashows a semiconductor wafer100with a base substrate material102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk semiconductor material. A plurality of semiconductor die or components104is formed on wafer100separated by a non-active, inter-die wafer area or saw street106as described above. Saw street106provides cutting areas to singulate semiconductor wafer100into individual semiconductor die104. In one embodiment, semiconductor wafer100has a width or diameter of 100-450 millimeters (mm).

FIG.1bshows a cross-sectional view of a portion of semiconductor wafer100. Each semiconductor die104has a back or non-active surface108and an active surface110containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within or over the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface110to implement analog circuits or digital circuits, such as digital signal processor (DSP), ASIC, MEMS, memory, or other signal processing circuit. Semiconductor die104may also contain integrated passive devices (IPDs), such as inductors, capacitors, and resistors, for RF signal processing. Back surface108of semiconductor wafer100may undergo an optional backgrinding operation with a mechanical grinding or etching process to remove a portion of base material102and reduce the thickness of semiconductor wafer100and semiconductor die104.

An electrically conductive layer112is formed over active surface110using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layers112include one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive material. Conductive layer112operates as contact pads electrically connected to the circuits on active surface110.

Conductive layer112can be formed as contact pads disposed side-by-side a first distance from the edge of semiconductor die104, as shown inFIG.1b. Alternatively, conductive layer112can be formed as contact pads that are offset in multiple rows such that a first row of contact pads is disposed a first distance from the edge of the die, and a second row of contact pads alternating with the first row disposed a second distance from the edge of the die. Conductive layer112represents the last conductive layer formed over semiconductor die104with contact pads for subsequent electrical interconnect to a larger system. However, there may be one or more intermediate conductive and insulating layers formed between the actual semiconductor devices on active surface110and contact pads112for signal routing.

An electrically conductive bump material is deposited over conductive layer112using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer112using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form conductive balls or bumps114. In one embodiment, conductive bumps114are formed over an under bump metallization (UBM) having a wetting layer, barrier layer, and adhesion layer. Conductive bumps114can also be compression bonded or thermocompression bonded to conductive layer112. Conductive bumps114represent one type of interconnect structure that can be formed over conductive layer112for electrical connection to a substrate. The interconnect structure can also use bond wires, conductive paste, stud bump, micro bump, conductive pillars, or other electrical interconnect.

InFIG.1c, semiconductor wafer100is singulated through saw street106using a saw blade or laser cutting tool118into individual semiconductor die104. The individual semiconductor die104can be inspected and electrically tested for identification of KGD post-singulation.

FIGS.2a-2jillustrate forming photonic semiconductor packages150with semiconductor die104.FIG.2ais a partial cross-sectional view of a substrate or interposer152. While only a single interposer152is shown, hundreds or thousands of interposers are commonly processed on a common carrier, using the same steps described herein for a single unit but performed en masse.

Interposer152includes one or more insulating layers154interleaved with one or more conductive layers156. Insulating layer154is a core insulating board in one embodiment, with conductive layers156patterned over the top and bottom surfaces, e.g., a copper-clad laminate substrate. Conductive layers156also include conductive vias electrically coupled through insulating layers154. Interposer152can include any number of conductive and insulating layers interleaved over each other. A solder mask or passivation layer can be formed over either side of interposer152. Any suitable type of interposer, substrate, or leadframe is used for interposer152in other embodiments.

Any components desired to implement the intended functionality of packages150are mounted to or disposed over interposer152and electrically connected to conductive layers156. Interposer152has two major surfaces: top surface157and bottom surface159. Components can be mounted onto top surface157and bottom surface159in any suitable order and configuration.

InFIG.2b, manufacturing of package150commences with surface mounting of semiconductor die104a, discrete component164, and e-bar or PCB unit166on bottom surface159. Bottom components are mounted first, but manufacturing could also proceed with components disposed on top surface157first. PCB unit166is a printed circuit board with a structure similar to interposer152or another type of interposer or substrate. Conductive layers167provide electrical paths through and across the surfaces of PCB unit166. Solder bumps168are reflowed between conductive layers167and interposer152to mechanically and electrically connect PCB units166to interposer152. Solder bumps168are formed similarly to bumps114above, and can be substituted with other types of interconnect structure as indicated above for bumps114. In one embodiment, bumps168are formed by printing solder paste on interposer157or PCB unit166prior to disposing them together.

Semiconductor die104ais structured and formed similarly to semiconductor die104above, but includes conductive pillars170as the interconnect structure instead of solder bumps114. Conductive pillars170are formed by depositing a photolithography mask layer over wafer100and then forming openings in the mask wherever pillars170are desired. The openings are filled with copper or another suitable conductive material to form pillars170, and then the mask is removed. A solder cap172is formed on each conductive pillar170using the same mask or by printing or dipping after removing the mask. Solder caps172are reflowed between conductive pillars170and conductive layer156to mechanically and electrically connect semiconductor die104ato interposer152. Solder bumps or other types of interconnect structures are used instead of conductive pillars170in other embodiments. Conductive pillars170do not collapse when solder caps172are reflowed like solder bumps114will, which provides a more consistent standoff between semiconductor die104aand interposer152.

Another specific detail regarding semiconductor die104athat wasn't necessarily true of semiconductor die104is that semiconductor die104ais a photonic integrated circuit (PIC). That is, semiconductor die104ahas the capability to transmit and/or receive light signals. At a later stage, a fiber optic or similar connector will be attached to photonic region176of semiconductor die104afor connection of fiber optic cables to carry light signals to and from semiconductor die104a. Semiconductor die104ais cantilevered over the edge of interposer152, i.e., photonic portion176of the semiconductor die extends outside of a footprint of the interposer. Thus, photonic region176remains available for later attachment of fiber optic hardware.

One or more discrete components164, e.g., resistors, capacitors, inductors, transistors, or diodes, are mounted on bottom surface159using solder paste or another suitable attachment and connection mechanism. Solder paste is reflowed between terminals of discrete components164and contact pads of conductive layers156on bottom surface159.

InFIG.2c, a mold underfill (MUF)180is deposited between semiconductor die104aand interposer152, around conductive pillars170. MUF180fills in gaps to structurally support the physical connection provided by solder caps172. MUF180is deposited using capillary action in one embodiment. MUF180is cured after being deposited.

FIG.2dshows interposer152with semiconductor die104a, discrete components164, and PCB unit166being flipped and then disposed over and mounted to a package substrate190. Bumps192are added to PCB unit166prior to flipping and mounting interposer152, or solder paste is printed onto the PCB unit or substrate190. Bumps192are reflowed between PCB unit166and substrate190to physically and electrically connect the PCB unit to the substrate as shown inFIG.2e. Substrate190is structured similarly to interposer152and PCB unit166with insulating layer194interleaved with conductive layers196, but could also be any other type of package substrate or leadframe. Substrate190is electrically connected to discrete components164and semiconductor die104athrough PCB unit166and interposer152. Additional electrical or semiconductor components can be mounted onto substrate190prior to attaching the interposer152assembly.

InFIG.2f, an encapsulant or molding compound200is deposited between interposer152and substrate190, covering top and bottom surfaces of PCB unit166and semiconductor die104aexcept for photonic region176that remains exposed. Encapsulant200is an electrically insulating material deposited using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable application process. Encapsulant200can be polymer composite material, such as an epoxy resin, epoxy acrylate, or polymer with or without a filler. Encapsulant200is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.

InFIG.2g, any additional desired components, e.g., additional discrete components164and semiconductor die104b, are mounted onto top surface157of interposer152. Any desired combination of electrical components can be disposed on bottom surface159and top surface157. Additional encapsulant can be deposited over top surface157to protect semiconductor die104bif desired. In other embodiments, no electrical components are disposed on top surface157. InFIG.2h, MUF204is deposited under semiconductor die104bas with MUF180under semiconductor die104a.

Package150is completed inFIG.2iby applying solder bumps206to substrate190in any suitable method, similar to the application of bumps114inFIG.1b. Bumps190are subsequently used to install package150into a larger electrical system. Other types of interconnect structure are used in other embodiments. Additional electrical or semiconductor components can be disposed on the bottom of substrate190between bumps206if desired. In some embodiments, a plurality of packages150is formed as a panel and then singulated from each other after completion.

FIG.2jshows a plan view of package150. Photonic region176of semiconductor die104aextends out from the footprint of interposer152to allow connection of fiber optic hardware. PCB units166are disposed around the other three sides of semiconductor die104awhere interposer152overlaps semiconductor die104a. The layout of PCB units166can be different, e.g., only a single PCB unit on one side of semiconductor die104aor an ‘L’-shaped PCB unit that extends around multiple sides of semiconductor die104a. Substrate190extends for the entire footprint of package150, including under photonic region176.

Package150is an advanced photonic system-in-package with multiple semiconductor die and discrete components. Photonic region176will have one or more fiber optic connectors attached using optical grade epoxy, or otherwise have hardware configure to send and receive optical signals. Photonic region176of semiconductor die104ahas a photodiode formed in its surface to receive an optical signal, a light emitting diode formed in its surface to emit an optical signal, or both. The fiber optic hardware attached to photonic region176will include a waveguide to guide light between fiber optic cables and semiconductor die104a. The optical transmissions have improved characteristics relative to electrical transmissions as discussed above. The structure and method of making package150improves the capabilities available on a photonic package and make manufacturing easier and cheaper.

FIGS.3aand3billustrate a package210formed similarly to package150, except that semiconductor die104aincludes notches212formed within photonic region176. Notches212operate as a physical guide for placement of optical ferrules during subsequent manufacturing. Ferrules are placed with tabs within notches212to ensure proper placement and alignment. A suitable optical epoxy is used to physically and optically connect the ferrules. The plan view inFIG.3bshows two notches212aand212bare formed. Notch212ais for an optical receiver and notch212bis for an optical transmitter in one embodiment. Notches212are formed using a deep reactive-ion etching (DRIE), chemical etching, mechanical grinding, or another suitable process, either before or after assembly of package210.

FIGS.4aand4billustrate a package220with PCB unit166replaced by copper-core solder balls (CCSB)222-224. CCSB include a copper core222surrounded by a solder coating224. Copper core222can consist of any material with a higher reflow temperature than solder coating224so that the core physically supports interposer152over substrate190when the solder coating is reflowed. Core222provides a standoff height between the interposer and substrate. Using CCSB222-224instead of PCB unit166reduces processing steps because the PCB unit requires a step of printing solder onto both sides of the PCB unit or onto substrate190and interposer152, which is not required with the CCSB due to being completely covered with solder to begin with. CCSB222-224electrically and physically connects interposer152to substrate190.

FIGS.5aand5billustrate a package230that uses copper balls222as electrical interconnects and physical standoff without a solder coating. Solder paste232is printed onto interposer152and substrate190prior to assembly, and then reflowed onto copper balls222.

FIGS.6aand6billustrate incorporating the above-described photonic semiconductor packages, e.g., package230, into an electronic device300.FIG.6aillustrates a partial cross-section of package230mounted onto a printed circuit board (PCB) or other substrate302as part of electronic device300. Bumps206are reflowed onto conductive layer304of PCB302to physically attach and electrically connect package230to the PCB. In other embodiments, thermocompression or other suitable attachment and connection methods are used. In some embodiments, an adhesive or underfill layer is used between package230and PCB302. Semiconductor die104are electrically coupled to conductive layer304through interposer152, copper balls222, and substrate190. One or more optical ferrules310or other optical hardware is mounted onto photonic region176of semiconductor die104as shown inFIG.6b. Optical cables312are attached to ferrules310to transmit and receive optical signals.

FIG.6billustrates electronic device300including PCB302with a plurality of semiconductor packages mounted on a surface of the PCB, including package230. Electronic device300can have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. Electronic device300can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device300can be a subcomponent of a larger system. For example, electronic device300can be part of a tablet computer, cellular phone, digital camera, communication system, or other electronic device. Electronic device300can also be a graphics card, network interface card, or another signal processing card that is inserted into a computer. The semiconductor packages can include microprocessors, memories, ASICs, logic circuits, analog circuits, RF circuits, discrete active or passive devices, or other semiconductor die or electrical components.

InFIG.6b, PCB302provides a general substrate for structural support and electrical interconnection of the semiconductor packages mounted on the PCB. Conductive signal traces304are formed over a surface or within layers of PCB302using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces304provide for electrical communication between the semiconductor packages, mounted components, and other external systems or components. Traces304also provide power and ground connections to the semiconductor packages as needed.

In some embodiments, a semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. Second level packaging involves mechanically and electrically attaching the intermediate substrate to PCB302. In other embodiments, a semiconductor device may only have the first level packaging where the die is mechanically and electrically mounted directly to PCB302.

For the purpose of illustration, several types of first level packaging, including bond wire package346and flipchip348, are shown on PCB302. Additionally, several types of second level packaging, including ball grid array (BGA)350, bump chip carrier (BCC)352, land grid array (LGA)356, multi-chip module (MCM)358, quad flat non-leaded package (QFN)360, quad flat package362, and embedded wafer level ball grid array (eWLB)364are shown mounted on PCB302along with package230. Conductive traces304electrically couple the various packages and components disposed on PCB302to package230, giving use of the components within package230to other components on the PCB.

Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB302. In some embodiments, electronic device300includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using less expensive components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.

While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.