Patent ID: 12199108

DESCRIPTION OF REFERENCE SIGNS

100′, display panel;103′, bonding area;104′, fan-out area;105′, driving chip;106′, output terminal;107′, fan-out wire;

100, display panel;101, display area;102, non-display area;103, bonding area;104, fan-out area;105, driving chip;1051, first side;1052, second side;1053, third side;106, output terminal;107, fan-out wire;1071, first fan-out section;1072, second fan-out section;108, input terminal;1091, first section;1092, second section;110, flexible circuit board;111, first signal wire;112, second signal wire;113, test pad connection wire;

10, first output terminal group;11, first fan-out wire group;12, second output terminal group;13, second fan-out wire group;

1, substrate;2, first metal layer;21, gate;3, gate insulating layer;31, insulating layer;32, connecting hole;4, semiconductor layer;5, second metal layer;51, source;52, drain.

DETAILED DESCRIPTION OF EMBODIMENTS

Technical solutions in embodiments of the present disclosure will be clearly and completely described below in conjunction with drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present disclosure. In addition, it should be understood that the specific implementations described here are only used to illustrate and explain the present disclosure, and are not used to limit the present disclosure. In the present disclosure, unless otherwise stated, directional words used such as “upper” and “lower” generally refer to upper and lower directions of a device in actual use or working state, and specifically refer to the drawing directions in the drawings; and “inner” and “outer” refer to an outline of the device.

Please refer toFIGS.2and3.FIG.2is a schematic diagram of a simplified planar structure of a display panel provided by an embodiment of the present disclosure, andFIG.3is a schematic diagram of a planar structure of the display panel provided by the embodiment of the present disclosure.

An embodiment of the present disclosure provides a display panel100. The display panel100comprises a substrate1. The substrate1comprises a display area101and a non-display area102surrounding the display area101, and the non-display area102comprises a bonding area103and a fan-out area104connecting to the bonding area103and the display area101, and the fan-out area104is located between the display area101and the bonding area103.

The bonding area103is provided with a driving chip105, the driving chip105comprises a first side1051close to the display area101and two second sides1052connected to the first side1051, and the two second sides1052are arranged oppositely. The driving chip105comprises a plurality of output terminals106, and the plurality of output terminals106constitute a first output terminal group10.

The fan-out area104is provided with a plurality of fan-out wires107, and the plurality of the fan-out wires107comprise at least a first fan-out wire group11, and each fan-out wire107in the first fan-out wire group11extends from the fan-out area104to the bonding area103, and is electrically connected to a corresponding output terminal106in the first output terminal group10through an adjacent second side1052.

Alternatively, a shape of the driving chip105is a rectangle, the first side1051and the second sides1052are perpendicular to each other, and the two second sides1052are parallel to each other.

On the one hand, in order to prevent a short circuit between the plurality of fan-out wires107in the first fan-out wire group11, there is no contact between each fan-out wire107in the first fan-out wire group11. On the other hand, it is also necessary to prevent poor display caused by disordered signal transmission between the output terminals106and the fan-out wires107in the first fan-out wire group11. Each fan-out wire107in each fan-out wire group11needs to be electrically connected to the corresponding output terminal106in the first output terminal group10, so that the fan-out wires107on the outer side need to be electrically connected to the output terminals106located on the outer side, and the fan-out wires107located on the inner side are electrically connected with the output terminals106located on the inner side. Further, the fan-out wires107in the first fan-out wire group11located on the outer side need to be electrically connected to the output terminals106in the first output terminal group10located on the outer side, and the fan-out wires107in the first fan-out wire group11on the inner side are electrically connected to the output terminals106in the first output terminal group10located on the inner side.

In view of this, the embodiment of the present disclosure achieves the above-mentioned purpose by adopting a wire-changing jumper for the plurality of the fan-out wires107in the first fan-out wire group11, and specific solutions are described as follows.

Each fan-out wire107in the first fan-out wire group11comprises a first fan-out section1071and a second fan-out section1072that are connected to each other and located in different layers to ensure that even if there is no contact between the first fan-out section1071and the second fan-out section1072, the first fan-out section1071and the second fan-out section1072overlap in a plane direction perpendicular to the display panel, so as to prevent the short circuit between the plurality of fan-out wires107in the first fan-out wire group11.

Each first fan-out section1071is electrically connected to the display area101, and each second fan-out section1072is electrically connected to a corresponding output terminal106in the first output terminal group10. That is to say, the display area101is electrically connected to the first fan-out section1071first, and then is electrically connected to the output terminal106in the first output terminal group10through the second fan-out section1072.

It is understandable that, compared to the prior art in which every part of each fan-out wire107in the first fan-out wire group11is located in a same film layer, each fan-out wire107in the present disclosure can be electrically connected to the corresponding output terminal106, so that the poor display caused by signal transmission disorder due to the inconsistency of an order of the two can be prevent.

In order to more clearly illustrate a structure of the fan-out wires107in the first fan-out wire group11, a structure of the display panel100in the embodiment of the present disclosure will be described below with reference toFIG.4, which is a schematic diagram of a cross-sectional structure of the display area101of the display panel100provided by the embodiment of the present disclosure.

It should be noted that the display panel100in the embodiment of the present disclosure may be a bottom-gate display panel or a top-gate display panel, and the present disclosure is not limited to this. In order to clearly describe the technical solutions in the present disclosure, the embodiment of the present disclosure takes the display panel100as the bottom-gate display panel as an example for illustration.

Specifically, the display panel100comprises the substrate1and a thin film transistor array layer, the thin film transistor array layer is disposed on the substrate1and comprises a plurality of thin film transistors distributed in an array and a plurality of signal wires. The substrate1can be made of any suitable insulating material with flexibility, and can be transparent, translucent, or opaque.

The thin film transistor array layer comprises a first metal layer2, a gate insulating layer3, a semiconductor layer4, and a second metal layer5. Specifically, the first metal layer2is located on the substrate1and comprises a gate21and scan signal wires (not shown in the figures) and the like. The gate insulating layer3is located on the first metal layer2, and covers the substrate1and the gate21. The semiconductor layer4is located on the gate insulating layer3, and a material of the semiconductor layer4may be low-temperature polysilicon or amorphous silicon. The second metal layer5is located on the semiconductor layer4and covers the gate insulating layer3and the semiconductor layer4, and the second metal layer5comprises a source51, a drain52, and data signal wires (not shown in the figures).

Specifically, materials of the first metal layer2and the second metal layer5may be same or different. The materials of the first metal layer2may comprise a single layer or multiple layers of gold (Au), silver (Ag), copper (Cu), nickel (5i), platinum (Pt), palladium (Pd), aluminum (Al), molybdenum (Mo), or a chromium (Cr), or an alloy such as aluminum (Al): neodymium (5d) alloy, molybdenum (Mo): tungsten (W) alloy; and the materials of the second metal layer5may comprise a single layer or multiple layers of gold (Au), silver (Ag), copper (Cu), nickel (5i), platinum (Pt), palladium (Pd), aluminum (Al), molybdenum (Mo) or chromium (Cr), or an alloy such as aluminum (Al): neodymium (5d) alloy, molybdenum (Mo): tungsten (W) alloy.

As an embodiment, please refer toFIG.5.FIG.5is a schematic diagram of a cross-sectional structure of the non-display area of the display panel inFIG.3.

Specifically, the first fan-out sections1071are located on the substrate1, and the second fan-out sections1072are located on a side of the first fan-out sections1071away from the substrate1, that is, the first fan-out sections1071are disposed in a same layer as the first metal layer2, and the second fan-out sections1072are disposed in a same layer as the second metal layer5. Alternatively, in other embodiments, the second fan-out sections1072are located on the substrate1, and the first fan-out sections1071are located on a side of the second fan-out sections1072away from the substrate1, that is, the first fan-out sections1071are disposed in a same layer with the second metal layer5, and the second fan-out sections1072are disposed in a same layer as the first metal layer2.

Further, an insulating layer31is also provided between the first fan-out sections1071and the second fan-out sections1072to prevent a short circuit between the first fan-out sections1071and the second fan-out sections1072. The first fan-out sections1071and the second fan-out sections1072are electrically connected through connecting holes32opened in the insulating layer31. The insulating layer31and the gate insulating layer3are disposed in a same layer and are prepared through a same process.

Please refer toFIG.6toFIG.13.FIG.6toFIG.13are schematic diagrams of various partial structures of the non-display area of the display panel provided by embodiments of the present disclosure.

Specifically, the first fan-out wire group11inFIGS.6to13comprises the plurality of fan-out wires107, and the first output terminal group10comprises the plurality of output terminals106. It should be noted that, for the convenience of description, the embodiment of the present disclosure assumes that the first fan-out wire group11comprises five fan-out wires107, and the first output terminal group10comprises five output terminals106as an example for description, but the present disclosure should not be limited by this.

Various embodiments provided inFIGS.6to13will be described one by one below.

As an embodiment, please refer toFIG.6.FIG.6is a schematic diagram of a first partial structure of the non-display area of the display panel provided by an embodiment of the present disclosure.

Specifically, the plurality of second fan-out sections1072are electrically connected to corresponding output terminals106in the first output terminal group10through an adjacent second side1052. The plurality of first fan-out sections1071are arranged along a preset direction, and ends of the plurality of second fan-out sections1072that are not connected to the first fan-out sections1071are arranged along the preset direction. In the preset direction, an arrangement sequence of each of the first fan-out sections1071is same as an arrangement sequence of ends of correspondingly connected second fan-out sections1072that are not connected to the first fan-out sections1071.

Specifically, the preset direction is perpendicular to a direction in which the display area101points to the fan-out area104, the preset direction may refer to a first direction inFIG.6, and the direction in which the display area101points to the fan-out area may refer to a second direction inFIG.6. The first direction and the second direction inFIGS.7to13are the same, and the description will not be repeated below.

Generally, an extension direction of the first side1051is perpendicular to the direction in which the display area101points to the fan-out area104, therefore the preset direction may be parallel to the extension direction of the first side1051.

Specifically, the first fan-out section1071of the first fan-out wire, the first fan-out section1071of the second fan-out wire . . . the first fan-out section1071of the fifth fan-out wire are arranged in the preset direction in sequence. An end of the second fan-out section1072of the first fan-out wire that is not connected to the first fan-out section1071, and an end of the second fan-out section1072of the second fan-out wire that is not connected to the first fan-out section1071. . . an end of the second fan-out section1072of the fifth fan-out wire that is not connected to the first fan-out section1071are arranged in sequence along the preset direction. A first output terminal, a second output terminal . . . and a fifth output terminal of the first output terminal group10are arranged in order along the extension direction of the first side1051. The first fan-out section of the first fan-out wire is electrically connected to the first output terminal through the second fan-out section1072of the first fan-out wire, the first fan-out section1071of the second fan-out wire is electrically connected to the second output terminal through the second fan-out section1072of the second fan-out wire . . . the first fan-out section1071of the fifth fan-out wire is electrically connected to the fifth output terminal through the second fan-out section1072of the fifth fan-out wire.

It is understandable that the embodiment of the present disclosure adopts the wire-changing jumper design, so that on the premise of preventing a short circuit between the fan-out wires107, each fan-out wire107of the first fan-out wire group11can be connected to the corresponding output terminal106in the first output terminal group10, and therefore each fan-out wire107can be electrically connected to the corresponding output terminal106, thereby preventing poor display caused by disordered signal transmission due to the inconsistency of the order of the two.

As an embodiment, please refer toFIG.7.FIG.7is a schematic diagram of a second partial structure of the non-display area of the display panel provided by an embodiment of the present disclosure.

Specifically, the plurality of first fan-out sections1071are connected to corresponding second fan-out sections1072through an adjacent second side edge1052, and the plurality of second fan-out sections1072are electrically connected to corresponding output terminals106in the first output terminal group10. The ends of the plurality of first fan-out sections1071that are not connected to the second fan-out sections1072are arranged along the preset direction, and the plurality of second fan-out sections1072are arranged along the preset direction. In the preset direction, a sequence of the ends of the first fan-out section1071that are not connected to the second fan-out sections1072is same as a sequence of the correspondingly connected second fan-out sections1072.

Specifically, the end of the first fan-out section1071of the first fan-out wire that is not connected to the second fan-out section1072, and the end of the first fan-out section1071of the second fan-out wire that is not connected to the second fan-out section1072. . . the end of the first fan-out section1071of the fifth fan-out wire that is not connected to the second fan-out section1072are arranged in sequence along the preset direction. The second fan-out section1072of the first fan-out wire, the second fan-out section1072of the second fan-out wire . . . the second fan-out section1072of the fifth fan-out wire are arranged in sequence along the preset direction. The first output terminal, the second output terminal . . . and the fifth output terminal of the first output terminal group10are arranged in sequence along the extension direction of the first side1051. Wherein, the first fan-out section1071of the first fan-out wire is electrically connected to the first output terminal through the second fan-out section1072of the first fan-out wire, the first fan-out section of the second fan-out wire1071is electrically connected to the second output terminal through the second fan-out section1072of the second fan-out wire . . . the first fan-out section of the fifth fan-out wire1071is electrically connected to the fifth output terminal through the second fan-out section1072of the fifth fan-out wire.

It is understandable that the embodiment of the present disclosure adopts the wire-changing jumper design, so that on the premise of preventing the short circuit between the fan-out wires107, each fan-out wire107of the first fan-out wire group11can be connected to the corresponding output terminal106in the first output terminal group10, and therefore each fan-out wire107can be electrically connected to the corresponding output terminal106, thereby preventing poor display caused by disordered signal transmission due to the inconsistency of the order of the two.

Further, the first fan-out wire located on the outermost side is electrically connected to the first output terminal closest to the second side1052, and the fifth fan-out wire located on the innermost side is electrically connected to the fifth output terminal the furthest away from the second side1052, so that a length of the first fan-out wire on the outermost side can be reduced. Since an impedance of the fan-out wire is positively related to the length, the design of the present disclosure can reduce the impedance of the first fan-out wire on the outermost side.

In the same way, lengths of the 2/3/4 fan-out wires located between the first fan-out wire and the fifth fan-out wire are close to the lengths of the first fan-out wire and the fifth fan-out wire, and impedances also approach. Therefore, compared with the prior art that the fan-out wires107in the first fan-out wire group11are located in the same film layer, the impedances of the plurality of fan-out wires107in the first fan-out wire group11in the present disclosure are approximately equal, so that uniformity of impedance can be achieved, which is beneficial to improve uniformity of signal transmission.

Please continue to refer toFIGS.6and7, the plurality of output terminals106further comprise a second output terminal group12, and the plurality of fan-out wires107further comprise a second fan-out wire group13, and each fan-out wire107of the second fan-out wire group13is electrically connected to a corresponding output terminal106in the second output terminal group12. The plurality of fan-out wires107of the second fan-out wire group13are consistent with the design of the fan-out wires in the prior art and are arranged in a single layer.

Specifically, the plurality of output terminals106of the first output terminal group10and the plurality of output terminals106of the second output terminal group12are arranged along the extension direction of the first side1051, so that the second output terminal group12is arranged on a side of the first output terminal group10away from the second side1052. Compared with existing conventional driving chips, an arrangement sequence of the plurality of output terminals106of the driving chip105in the present disclosure is fixed without any change. An arrangement sequence of the fan-out wires107is same as an arrangement sequence of the output terminals106, so that each fan-out wire107can be electrically connected to the corresponding output terminal106, which prevents poor display caused by disordered signal transmission due to the inconsistency of the order of the two. Therefore, the display panel100of the present disclosure can directly emulate the existing conventional driving chips, and there is no need to design the arrangement sequence of the output terminals of the driving chips separately, which saves costs and facilitates mass production of products.

Further, for the display panel100adopting a newly designed driving chip105, the technical solution provided in the present disclosure is also applicable. The following will illustrate structures of the display panel100that may be involved in the embodiments of the present disclosure. Regarding the structure of the fan-out wires107of the first fan-out wire group11and the connection relationship with the output terminals106of the first output terminal group10, please refer to the foregoing discussion content, which will not be repeated here.

As an embodiment, please refer toFIG.8.FIG.8is a schematic diagram of a third partial structure of the non-display area of the display panel provided by an embodiment of the present disclosure.

Specifically, the plurality of output terminals106of the first output terminal group10and the plurality of output terminals106of the second output terminal group12are arranged along the extension direction of the first side1051, at least a part of the output terminals106of the second output terminal group12are arranged on a side of the first output terminal group10close to the adjacent second side1052.

It can be understood that since the output terminals106of the second output terminal group12are located in a middle area of the driving chip105, the output terminals106of the first output terminal group10are located on left and right sides of the driving chip105, the fan-out wires107in the second fan-out wire group13to which the output terminals106of the second output terminal group12are connected still have space for compression, and the fan-out wires107in the first fan-out wire group11connected to the output terminals106of the first output terminal group10cannot be further compressed. Therefore, in the embodiment of the present disclosure, at least a part of the output terminals106of the second output terminal group12are arranged on a side of the first output terminal group10close to the second side1052, so that the bonding area103is further moved upward as a whole, which can reduce a lower frame of the display panel100.

As an embodiment, referring toFIG.9, which is a schematic diagram of a fourth partial structure of the non-display area of the display panel provided by an embodiment of the present disclosure.

Specifically, the plurality of output terminals106of the first output terminal group10are arranged along the extension direction of an adjacent second side1052, and the plurality of output terminals106of the second output terminal group12are arranged along the extension direction of the first side1051.

Specifically, the first output terminal, the second output terminal . . . the fifth output terminal of the first output terminal group10are arranged in sequence along the preset direction (the second direction), and the first fan-out section of the first fan-out wire is electrically connected to the first output terminal through the second fan-out section1072of the first fan-out wire, the first fan-out section1071of the second fan-out wire is electrically connected to the second output terminal through the second fan-out section107of the second fan-out wire . . . the first fan-out section1071of the fifth fan-out wire is electrically connected to the fifth output terminal through the second fan-out section1072of the fifth fan-out wire.

As an embodiment, please refer toFIG.10, which is a schematic diagram of a fifth partial structure of the non-display area of the display panel provided by an embodiment of the present disclosure.

Specifically, the output terminals106of the second output terminal group12are arranged along the extension direction of the first side1051, and the output terminals106of the first output terminal group10are located on a side of the output terminals106of the second output terminal group12away from the display area101.

That is to say, the output terminals106of the first output terminal group10and the output terminals106of the second output terminal group12are arranged side by side. In the extension direction of the first side1051(the first direction), an arrangement sequence of the output terminals106of the first output terminal group10and an arrangement sequence of the output terminals106of the second output terminal group12are reversed.

Specifically, the first output terminal, the second output terminal . . . and the fifth output terminal of the first output terminal group10are arranged in sequence in an opposite direction of the first direction, and the first fan-out section1071of the first fan-out wire is electrically connected to the first output terminal through the second fan-out section1072of the first fan-out wire, the first fan-out section1071of the second fan-out wire is electrically connected to the second output terminal through the second fan-out section1072of the second fan-out wire . . . the first fan-out section1071of the fifth fan-out wire is electrically connected to the fifth output terminal through the second fan-out section1072of the fifth fan-out wire.

Further, referring toFIGS.2to12, the driving chip105further comprises a third side1053away from the display area101, and the third side1053is disposed opposite to the first side1051, so the third side1053is connected to the two second sides1052. The driving chip105further comprises a plurality of input terminals108for transmitting external signals to the output terminals106, and the plurality of input terminals108are arranged along an extension direction of the third side1053.

As an embodiment, please refer toFIG.11.FIG.11is a schematic diagram of a sixth partial structure of the non-display area of the display panel provided by an embodiment of the present disclosure.

Specifically, the output terminals106of the second output terminal group12are arranged along the extension direction of the first side1051, and the output terminals106of the first output terminal group10are arranged along the extension direction of the third side1053, and the second output terminal group12is located on a side of the input terminals108close to the second side1052.

As an embodiment, please refer toFIG.12.FIG.12is a schematic diagram of a seventh partial structure of the non-display area of the display panel provided by an embodiment of the present disclosure.

Specifically, the output terminals106of the second output terminal group12are arranged along the extension direction of the first side1051, and the output terminals106of the first output terminal group10are arranged along the extension direction of the third side1053, and at least a part of the output terminals106of the second output terminal group12are arranged between the plurality of input terminals108.

Further, referring toFIG.3,FIG.6andFIG.12, the display panel100further comprises a test pad provided on the substrate1for image detection of the display panel.

Specifically, before an integrated circuit chip is bound to the display panel100, data signals and clock signals may be sent to the display area101of the display panel100through the test pad to realize image detection of the display panel100. Through the image detection, it can be determined whether the display panel100has a display abnormality. If there is a display abnormality, cause of the display abnormality can be found in time and the abnormality can be processed before binding, and the binding can be performed after the display is normal, so as to ensure that display function of the display panel100after the binding is normal, which is beneficial to improve production yield of the display panel100. If the detection is performed after the binding, workload of rework process which will be performed when the display is abnormal is relatively large, and the production yield of the display panel100will be greatly reduced.

In order to adapt to the wire-changing jumper design adopted by the fan-out wires107in the embodiment of the present disclosure, the test pad in the embodiment of the present disclosure also adopts a sectioned design.

Specifically, the test pad comprises a first section1091and a second section1092, the first section1091is located in the fan-out area104, and the second section1092is located in the bonding area103. Compared with the prior art, in the present disclosure, a part of the test pad is disposed outside the bonding area103, so that an area of the substrate corresponding to the driving chip105leaves more space to layout the fan-out wires107, which can further reduce the lower frame of the display panel100.

It is understandable that since the first fan-out sections1071are vertical wires, which will not restrict the setting of the test pad, the first section1091corresponds to the first fan-out sections1071, and an orthographic projection of the first section1091on the substrate1overlaps an orthographic projection of the first fan-out sections1071on the substrate1. The fan-out wires107in the first fan-out wire group11is electrically connected to the first section1091first, and then is electrically connected to the output terminals106of the first output terminal group10. Before binding the driving chip105, the first section1091is configured to provide test signals to the fan-out wires107in the first fan-out wire group11to detect images.

In contrast, the second fan-out sections1072are horizontally routed, which will limit the setting of the test pad, so an orthographic projection of the second section1092on the substrate1and an orthographic projection of the output terminals106and the input terminals108on the substrate1do not overlap, and the orthographic projection of the second section1092on the substrate1is located at a side of an orthographic projection of the second output terminal group12on the substrate1away from the display area101. The fan-out wires107in the second fan-out wire group13is first electrically connected to the plurality of output terminals106of the second output terminal group12, and then electrically connected to the second section1092. The second section1092is configured to provide test signals to the fan-out wires107in the second fan-out wire group13to detect image before the integrated circuit chip is bound.

Further, please refer toFIG.13.FIG.13is a schematic diagram of an eighth partial structure of the non-display area of the display panel provided by an embodiment of the present disclosure.FIG.13is an improvement based onFIG.6, apparently, this improvement can be applied to other embodiments.

The display panel100further comprises a plurality of test pad connection wires113configured to connect the first section1091and the second section1092. There is a gap between two adjacent output terminals106of the first output terminal group10, and at least a part of the test pad connection wires113are connected to the second section1092through the gap from a side of the first side1051close to the display area101.

It can be understood that the test pad connection wires113are routed on a side of the first side1051close to the display area101, which is beneficial to save space under the first output terminal group10, thereby increasing a wire space for the fan-out wires107in the first fan-out wire group11, so that a number of the fan-out wires107in the second fan-out wire group13is reduced, which can further reduce the lower frame of the display panel100.

Please refer toFIG.14, which is a schematic diagram of another planar structure of the display panel provided by an embodiment of the present disclosure.

Further, the display panel100further comprises a flexible circuit board110disposed on a side of the driving chip105away from the display area101, and the flexible circuit board110is electrically connected to the input terminals108. Signals transmitted to the display area101are usually first transmitted to the input terminals108through the flexible circuit board110, and then transmitted to the output terminals106through the input terminals108and wires inside the driving chip105, and transmitted to the display area101through the output terminals106and the fan-out wires107.

Further, please continue to refer toFIG.3andFIG.14, the display panel100further comprises a plurality of signal wires disposed in the display area101, and each of the signal wires is electrically connected to a corresponding fan-out wire107.

In terms of location, the plurality of signal wires comprise first signal wires111and second signal wires112, and the first signal wires111are electrically connected to the output terminals106of the first output terminal group10through the fan-out wires107of the first fan-out wire group11, and the second signal wires112are electrically connected to the output terminals of the second output terminal group12through the fan-out wires107of the second fan-out wire group13.

From a functional point of view, the plurality of signal wires may comprise a plurality of data signal wires and a plurality of touch signal wires, and an arrangement of the data signal wires is the same as that of the touch signal wires, and the data signal wires are insulated from the touch signal wires. The flexible circuit board110in the present disclosure sends touch signals to the touch signal wires through the driving chip105, and the driving chip105sends data signals to the data signal wires.

The embodiment of the present disclosure also provides a display device, the display device comprises the above-mentioned display panel, and the display device can be any products or elements having display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

Beneficial effects are: in the display panel and the display device provided by the embodiments of the present disclosure, the plurality of fan-out wires are disposed in the fan-out area of the display panel, and the plurality of fan-out wires comprise at least the first fan-out wire group. Each fan-out wire in the first fan-out group extends from the fan-out area to the bonding area, and is electrically connected to the corresponding output terminal in the first output terminal group through the adjacent second side. Each fan-out wire in the first fan-out wire group of the present disclosure adopts the wire-changing jumper design, and each fan-out wire in the first fan-out wire group comprises the first fan-out section and the second fan-out section that are connected and located on different layers, each first fan-out section is electrically connected to the display area, and each second fan-out section is electrically connected to the corresponding output terminal in the first output terminal group. Under the premise of realizing the narrow frame, the fan-out wires are electrically connected to the corresponding output terminals, which prevents the short circuit between the plurality of fan-out wires, and prevents poor display caused by signal disorder due to inconsistent orders of the output terminals and the fan-out wires.

In summary, although preferred embodiments have been described above in the present disclosure, the above-mentioned preferred embodiments are not intended to limit the present disclosure. Those of ordinary skilled in the art can make various modifications and changes without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure is subject to the scope defined by the claims.