Patent ID: 12213343

It should be understood that the dimensions of various parts shown in the accompanying drawings are not necessarily drawn according to actual proportional relations. In addition, the same or similar components are denoted by the same or similar reference signs.

DETAILED DESCRIPTION

Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The following description of the exemplary embodiments is merely illustrative and is in no way intended as a limitation to the present disclosure, its application or use. The present disclosure may be implemented in many different forms, which are not limited to the embodiments described herein. These embodiments are provided to make the present disclosure thorough and complete, and fully convey the scope of the present disclosure to those skilled in the art. It should be noticed that: relative arrangement of components and steps, material composition, numerical expressions, and numerical values set forth in these embodiments, unless specifically stated otherwise, should be explained as merely illustrative, and not as a limitation.

The use of the terms “first”, “second” and similar words in the present disclosure do not denote any order, quantity or importance, but are merely used to distinguish between different parts. A word such as “comprise”, “have” or variants thereof means that the element before the word covers the element(s) listed after the word without excluding the possibility of also covering other elements. The terms “up”, “down”, or the like are used only to represent a relative positional relationship, and the relative positional relationship may be changed correspondingly if the absolute position of the described object changes.

In the present disclosure, when it is described that a specific component is disposed between a first component and a second component, there may be an intervening component between the specific component and the first component or between the specific component and the second component. When it is described that a specific part is connected to other parts, the specific part may be directly connected to the other parts without an intervening part, or not directly connected to the other parts with an intervening part.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as the meanings commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms as defined in general dictionaries, unless explicitly defined herein, should be interpreted as having meanings that are consistent with their meanings in the context of the relevant art, and not to be interpreted in an idealized or extremely formalized sense.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, these techniques, methods, and apparatuses should be considered as part of this specification.

FIG.1is a schematic structure view showing a display panel according to an embodiment of the present disclosure.

As shown inFIG.1, the display panel comprises a base substrate11and a plurality of sub-pixels12.

The base substrate11comprises a display area111and a peripheral area112surrounding the display area. In some embodiments, the base substrate11comprises a first base substrate layer, a second base substrate layer, a first barrier layer, and a second barrier layer. The first barrier layer is located between the first base substrate layer and the second base substrate layer, and the second base substrate layer is located between the first barrier layer and the second barrier layer. For example, the material of at least one of the first base substrate layer or the second base substrate layer may comprise a flexible material such as polyimide (PI). For example, the material of at least one of the first barrier layer or the second barrier layer may comprise an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

The plurality of sub-pixels12is located at the display area111. For example, the plurality of sub-pixels12may comprise a red sub-pixel, a green sub-pixel, or a blue sub-pixel. Each sub-pixel12comprises a pixel circuit. For example, the pixel circuit may comprise six transistors and one capacitor (6T1C). For another example, the pixel circuit may comprise seven transistors and one capacitor (7T1C).

In some embodiments, referring toFIG.1, the display panel further comprises a plurality of data lines DL. The plurality of data lines DL is located at the display area111and electrically connected to the plurality of sub-pixels12located at the display area111. The plurality of data lines DL is configured to provide a data signal to the plurality of sub-pixels12. For example, each data line DL is electrically connected to a column of sub-pixels12.

In some embodiments, referring toFIG.1, the display panel further comprises a plurality of gate lines GL. The plurality of gate lines GL is located at the display area111and electrically connected to the plurality of sub-pixels12. The plurality of gate lines GL is configured to provide a gate signal to the plurality of sub-pixels12. For example, each gate line GL is electrically connected to a row of sub-pixels12.

In some embodiments, referring toFIG.1, the display panel further comprises a plurality of light emitting control lines GCL. The plurality of light emitting control lines GCL is located at the display area111and electrically connected to the plurality of sub-pixels12. The plurality of light emitting control lines GCL is configured to provide a light emitting control signal to the plurality of sub-pixels12. For example, each light emitting control line GCL is electrically connected to a row of sub-pixels12.

In some embodiments, referring toFIG.1, the display panel further comprises a plurality of power lines PL. The plurality of power lines PL is located at the display area111and electrically connected to the plurality of sub-pixels12. The plurality of power lines16is configured to provide a power signal to the plurality of sub-pixels12.

In some embodiments, referring toFIG.1, the display panel further comprises a plurality of initialization lines IL. The plurality of initialization lines IL is located at the display area111and electrically connected to the plurality of sub-pixels12. The plurality of initialization lines IL is configured to provide an initialization signal to the plurality of sub-pixels12.

FIG.2Ais a schematic cross-sectional view showing a sub-pixel in a display panel according to an embodiment of the present disclosure.FIG.2Bis a schematic cross-sectional view showing a display panel according to an embodiment of the present disclosure. The structure of the display panel according to some embodiments of the present disclosure will be introduced below in conjunction withFIGS.2A and2B.

As shown inFIG.2A, the sub-pixel12comprises a driving transistor121. Here, the driving transistor121comprises a plurality of conductive layers. As some implementations, the driving transistor121may be a top gate transistor. As other implementations, the driving transistor121may be a bottom gate transistor.FIG.2Ashows the driving transistor121as a top gate transistor.

As shown inFIG.2B, other than the base substrate11and the plurality of sub-pixels12, the display panel further comprises a first dam13, a second dam14, an encapsulation layer15and at least one pressure sensor16. For example, the pressure sensor16can serve as a volume button or a power-on button.

The first dam13and the second dam14both surround the display area111and are located at the peripheral area112. The second dam14is located on one side of the first dam13away from the display area111. Here, the first dam13and the second dam14can block water and oxygen from entering the sub-pixel12.

The encapsulation layer15is located on one side of the plurality of sub-pixels12, the first dam13and the second dam14away from the base substrate11. Here, the orthographic projections of the plurality of sub-pixels12, the first dam13and the second dam14on the base substrate11are located within the orthographic projection of the encapsulation layer15on the base substrate11. For example, the encapsulation layer15may comprise a thin film encapsulation layer. In some embodiments, the encapsulation layer15may comprise a first inorganic layer151, a second inorganic layer152, and an organic layer153located between the first inorganic layer151and the second inorganic layer152. In some embodiments, the display panel may further comprise a third dam22located between the second dam14and the display area111. The third dam22is used for blocking the flow of the organic layer153.

At least one pressure sensor16is located on at least one of a first side of the second dam14proximate to the first dam13and a second side of the second dam14away from the first dam13. For example, the at least one pressure sensor16is located on the first side of the second dam14proximate to the first dam13. For another example, the at least one pressure sensor16is located on the second side of the second dam14away from the first dam13For still another example, one or more pressure sensors16of the at least one pressure sensor16are located on the first side of the second dam14proximate to the first dam13, and one or more sensors16of the at least one pressure sensor16are located on the second side of the second dam14away from the first dam13.

At least one resistor R in each pressure sensor16is located in a same layer as one of the plurality of conductive layers in the driving transistor121. For example, at least one resistor R of the pressure sensor16comprises four resistors.

It should be noted that, in the embodiments of the present disclosure, a plurality of components is located in a same layer means that the plurality of components is formed by performing a patterning process on a same material layer. Therefore, the plurality of components has a same material, and has substantially a same thickness.

In the above embodiments, at least one pressure sensor16is located on at least one of the first side of the second dam14proximate to the first dam13or the second side of the second dam14away from the first dam13, and at least one resistor R of each pressure sensor16is located in a same layer as one of the plurality of conductive layers in the driving transistor121. With such a structure, the pressure sensor16can be formed in the process of forming the sub-pixel12without additional providing an interaction button, thereby facilitating reducing the thickness of the display panel.

In addition, the pressure sensor16can make full use of the space of the peripheral area112without additionally increasing the size of the peripheral area112. Therefore, in some embodiments of the present disclosure, the thickness of the display panel can be reduced in a case where a narrow bezel is realized.

Some specific implementations of the driving transistor121will be described below in conjunction withFIG.2A.

Referring toFIG.2A, the driving transistor121comprises an active layer1211, a gate electrode1212, a first insulating layer1213, a second insulating layer1214, a third insulating layer1215, a first electrode1216, and a second electrode1217. The plurality of conductive layers in the driving transistor121comprises a gate1212, a first electrode1216, and a second electrode1217.

The active layer1211and the gate1212are located on one side of the base substrate11. For example, the gate1212is located on one side of the active layer1211away from the base substrate11. For example, the material of the active layer1211may comprise polysilicon. For example, the material of the gate electrode1212may comprise Mo.

The first insulating layer1213is located between the active layer1211and the gate1212. The second insulating layer1214is located on one side of the active layer1211, the gate electrode1212and the first insulating layer1213away from the base substrate11. The third insulating layer1215is located on one side of the second insulating layer1214away from the base substrate11. For example, the material of at least one of the first insulating layer1213, the second insulating layer1214, or the third insulating layer1215may comprise an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

The first electrode1216and the second electrode1217are located on one side of the third insulating layer1215away from the base substrate11and electrically connected to the active layer1211. In some embodiments, the first electrode1216is a drain, and the second electrode1217is a source. For example, the first electrode1216and the second electrode1217are electrically connected to the active layer1211through a via hole penetrating through the third insulating layer1215, the second insulating layer1214, and the first insulating layer1213, respectively. For example, the first electrode1216and the second electrode1217may comprise a stacked layer of Ti/Al/Ti.

As some implementations, at least one resistor R of the pressure sensor16is located in a same layer as the gate1212.

As other implementations, at least one resistor R of the pressure sensor16, the first electrode1216and the second electrode1217are located in a same layer. For example, the resistor R comprises a stacked layer of Ti/Al/Ti. In this manner, the pressure sensor16is more sensitive to variation in resistance after an external pressure is applied.

In some embodiments, the pixel circuit in the sub-pixel12comprises seven transistors and one capacitor. For example, other than the driving transistor121, the sub-pixel12further comprises a first switching transistor, a second switching transistor, and a third switching transistor. The first electrode of the first switching transistor is electrically connected to one of the plurality of data lines DL, the second electrode of the first switching transistor is electrically connected to the second electrode1217(for example, a source) of the driving transistor121, and the gate of the first switching transistor is electrically connected to one of the plurality of gate lines GL. The first electrode of the second switching transistor is electrically connected to one of the plurality of power lines PL, the second electrode of the second switching transistor is electrically connected to the second electrode1217(for example, a source) of the driving transistor122, and the gate of the second switching transistor is electrically connected to one of the plurality of light emitting control lines GCL. The first electrode of the third switching transistor is electrically connected to the first electrode1216(for example, a drain) of the driving transistor121, the second electrode of the third switching transistor is electrically connected to the anode124, and the gate of the third switching transistor is electrically connected to one of the plurality of light emitting control lines GCL.

In some embodiments, referring toFIG.2A, the sub-pixel12further comprises a planarization layer123, an anode124, a pixel defining layer125, a functional layer126and a cathode127.

The planarization layer123is located on one side of the first electrode1216, the second electrode1217, and the third insulating layer1215away from the base substrate11. For example, the material of the planarization layer123may comprise an organic insulating material such as PI or resin material.

The anode124is located on one side of the planarization layer123away from the base substrate11and electrically connected to one of the first electrode1216and the second electrode1217. For example, the anode124is electrically connected to the first electrode1216through a via hole penetrating through the planarization layer123. For example, the material of the anode124may comprise indium tin oxide (ITO) or the like.

The pixel defining layer125is located on one side of the anode124and the planarization layer123away from the base substrate11. The pixel defining layer125has a first opening V1. Here, the orthographic projection of the first opening V1 on the base substrate11at least partially overlaps with the orthographic projection of the anode124on the base substrate11. In other words, the first opening V1 exposes at least a portion of the anode124. For example, the material of the pixel defining layer125may comprise an organic insulating material such as PI or resin material.

The functional layer126is at least partially located in the first opening V1 and located on one side of the anode124away from the base substrate11. Here, the functional layer126comprises at least a light emitting layer, for example, an organic light emitting layer. In some embodiments, the functional layer126may further comprise one or more of an electron transport layer, an electron injection layer, a hole transport layer, and a hole injection layer.

The cathode127is at least partially located in the first opening V1 and located on one side of the functional layer126away from the base substrate11. For example, the cathode127may extend from the display area111to the peripheral area112.

In some embodiments, referring toFIG.2B, the display panel further comprises a power bus18electrically connected to the cathode127. Here, the power bus18is located at the peripheral area112and located in a same layer as the first electrode1216and the second electrode1217. For example, a power signal can be applied to the cathode via the power bus18.

The electrical connection of the cathode127and the power bus18according to some implementations of the present disclosure will be introduced below.

Referring toFIG.2B, the planarization layer123has a second opening V2, and the pixel defining layer125further has a third opening V3. Here, the orthographic projections of the second opening V2 and the third opening V3 on the base substrate11are located at the peripheral area112. For example, the second opening V2 and the third opening V3 may be holes or slots. In some embodiments, the second opening V2 and the third opening V3 may be slots arranged around the display area111.

The display panel further comprises an electrical connection portion19. The electrical connection portion19is at least partially located in the second opening V2, and in contact with the power bus18. The cathode127is partially located in the third opening V3, and in contact with the electrical connection portion19. In addition, the electrical connection portion19is located in a same layer as the anode124.

In this manner, the cathode127is electrically connected to the power bus18via the electrical connection portion19located in a same layer as the anode124.

In some embodiments, the display panel further comprises an initialization bus21located at the peripheral area112and electrically connected to the plurality of initialization lines IL located at the display area111. An initialization signal can be provided to the plurality of initialization lines IL via the initialization bus21. The initialization bus line21is located between the planarization layer123and the base substrate11and located in a same layer as the first electrode1216and the second electrode1217. For example, the initialization bus21is located between the power line13and the display area111.

In some embodiments, the display panel further comprises a driving circuit20. The driving circuit20is located between the power bus18and the initialization bus21and located between the planarization layer123and the base substrate11. In some embodiments, the driving circuit22may comprise a gate driving circuit and alight emitting control driving circuit. The gate driving circuit comprises a plurality of gate driving units electrically connected to the plurality of gate lines GL, for example, a plurality of cascaded first shift registers. The light emitting control driving circuit comprises a plurality of light emitting control driving units electrically connected to the plurality of light emitting control lines GCL, for example, a plurality of cascaded second shift registers.

Some specific implementations of the first dam13and the second dam14will be described below.

In some implementations, referring toFIG.2B, the first dam13comprises a first layer131and a second layer132located on one side of the first layer away from the base substrate11. The first layer131and the planarization layer123are located in a same layer, and the second layer132and the pixel defining layer125are located in a same layer. For example, the orthographic projection of the first dam13on the base substrate11partially overlaps with the orthographic projection of the power bus18on the base substrate11.

In some implementations, referring toFIG.2B, the second dam14comprises a third layer141, a fourth layer142located on one side of the third layer141away from the base substrate11, and a fifth layer143located on one side of the fourth layer142away from the base substrate11. The third layer141and the planarization layer123are located in a same layer, the fourth layer142and the pixel defining layer125are located in a same layer, and the fifth layer143and the support layer24(seeFIG.2A) located at the display area111are located in a same layer. Here, the support layer24is located on one side of the pixel defining layer125away from the base substrate11. For example, the material of the support layer24may comprise an organic insulating material such as PI or resin material.

In some embodiments, referring toFIG.2B, the display panel further comprises a crack stop member17for preventing a crack during the process of cutting the display panel from expanding to the display area111. Here, the crack stop member17is located on one side of the encapsulation layer15away from the display area111, and the pressure sensor16in the display panel is located on one side of the crack stop member17proximate to the display area111.

In some embodiments, the distance between the boundary of the orthographic projection of the first dam13on the base substrate11proximate to the second dam14and the boundary of the orthographic projection of the second dam14on the base substrate11proximate to the first dam13is a first distance, the distance between the boundary of the orthographic projection of the second dam14on the base substrate11away from the first dam13and the boundary of the orthographic projection of the encapsulation layer15on the base substrate11is a second distance, and the distance between the boundary of the orthographic projection of the encapsulation layer15on the base substrate11and the boundary of the orthographic projection of the crack stop member17on the base substrate11proximate to the display area111is a third distance. Here, the first distance and the second distance are greater than the third distance. For example, the first distance and the second distance are greater than 50 micrometers, and may be, for example, 80 micrometers, 90 micrometers, 100 micrometers, 110 micrometers, 130 micrometers, or 150 micrometers. For example, the third distance is 30 micrometers to 70 micrometers, for example 40 micrometers, 50 micrometers, 60 micrometers, etc. It should be understood that, the first distance, the second distance, and the third distance can be adjusted by those skilled in the art according to the size of the bezel of the display panel. In addition, it should also be understood that, the distance between two boundaries can be understood as a minimum distance from various points on one boundary to various points on the other boundary.

In some embodiments, referring toFIGS.2A and2B, the display panel further comprises a buffer layer23located between the base substrate11and the first insulating layer1213. For example, the material of the buffer layer23may comprise an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. Here, the first insulating layer1213, the second insulating layer1214, and the third insulating layer1215extend from the display area111to the peripheral area112, and the crack stop member17penetrates through the third insulating layer1215, the second insulating layer1214, the first insulating layer1213and the buffer layer18.

For example, the display panel has one or more grooves penetrating through the third insulating layer1215, the second insulating layer1214, the first insulating layer1213, and the buffer layer18. By filling a material such as an organic material in the one or more grooves, one or more crack stop members17can be formed. In some embodiments, the crack stop member17comprises a plurality of material layers, which may be located in a same layer as one or more of the planarization layer123, the pixel defining layer125and the support layer24. For example, the crack stop member17comprises two material layers, one of which is located in a same layer as the planarization layer123and the other of which is located in a same layer as the pixel defining layer125.

Some implementations of the position of the pressure sensor16in the display panel will be introduced below.

In some embodiments, referring toFIG.2B, at least one pressure sensor161of the display panel comprises a first pressure sensor161. Here, the first pressure sensor161is located between the second dam14and the first dam13, and the orthographic projection of the first pressure sensor16on the base substrate11is located within the orthographic projection of the encapsulation layer15on the base substrate11. In this manner, on one hand, the first pressure sensor161is covered by the encapsulation layer15; on the other hand, the second dam14can prevent an adverse effect of water and oxygen on the first pressure sensor161. Therefore, the reliability of the first pressure sensor161is improved.

In other embodiments, referring toFIG.2B, at least one pressure sensor16of the display panel comprises a second pressure sensor162. Here, the second pressure sensor162is located between the second dam14and the crack stop member17, and the orthographic projection of the second pressure sensor162on the base substrate11is located within the orthographic projection of the encapsulation layer15on the base substrate11. In this manner, the second pressure sensor162is covered by the encapsulation layer15, an adverse effect of water and oxygen on the second pressure sensor162is reduced.

In still other embodiments, referring toFIG.2B, at least one pressure sensor16of the display panel comprises a third pressure sensor163located between the encapsulation layer15and the crack stop member17.

FIG.3is a schematic circuit view showing a pressure sensor according to an embodiment of the present disclosure.

As shown inFIG.3, the at least one resistor R of the display panel comprises a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4.

The first resistor R1 is electrically connected between the first input terminal IN1 and the first output terminal OUT1, the second resistor R2 is electrically connected between the first output terminal OUT1 and the second input terminal IN2, the third resistor R3 is electrically connected between the second input terminal IN2 and the second output terminal OUT2, and the fourth resistor R4 is electrically connected between the second output terminal OUT2 and the first input terminal IN1. Here, the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 have a same resistance value in a case where no pressure is applied to the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4. It should be understood that, “the same” here means “the same” within a tolerance range of the process of a semiconductor.

The operation principle of the pressure sensor16will be explained by taking that an external pressure is applied to the first resistor R1 and no external pressure is applied to the other three resistors as an example.

An input voltage Vin is applied between the first input terminal IN1 and the second input terminal IN2. In a case where no external pressure is applied, the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 have a same resistance value, and the output voltage between the first output terminal OUT1 and the second output terminal OUT2 Vout is 0; in a case where an external pressure is applied to the first resistor R1 and no external pressure is applied to the other three resistors, the resistance value of the first resistor R1 changes, and the resistance values of the other three resistors do not change. Therefore, Vout it not 0. Therefore, whether an external pressure is applied to the first resistor R1 of the pressure sensor16can be recognized according to the value of Vout.

For the signal input and signal output of the pressure sensor16, the following wiring is also provided in the embodiments of the present disclosure.

FIG.4Ais a schematic cross-sectional view showing the wiring of a pressure sensor according to an embodiment of the present disclosure.

As shown inFIG.4A, the display panel further comprises a first signal output line SG1 electrically connected to the first output terminal OUT1 and a second signal output line SG2 electrically connected to the second output terminal OUT2. It should be noted that, the manner of electrical connection of the first output terminal OUT1 and the first signal output line SG1 is similar to the manner of electrical connection of the second output terminal OUT2 and the second signal output line SG2. In a case where the output terminal shown inFIG.4Ais the first output terminal OUT1, the signal line shown inFIG.4Ais the first signal output line SG1; in a case where the output terminal shown inFIG.4Ais the second output terminal OUT2, the signal line shown inFIG.4Ais the second signal output line SG2.

The first signal output line SG1 and the second signal output line SG2 may be located in a same layer as a certain layer in the sub-pixel12, which will be described below in conjunction withFIGS.2A and4A.

Referring toFIG.2A, the sub-pixel12further comprises a storage capacitor122. The storage capacitor122comprises a first electrode plate1221located in a same layer as the gate1212, and a second electrode plate1222located between the second insulating layer1214and the third insulating layer1215. It should be understood that, the storage capacitor122further comprises the second insulating layer1214located between the first electrode plate1221and the second electrode plate1222.

In some embodiments, the first signal output line SG1 and the second signal output line SG2 are located in a same layer as one of the first electrode plate1221and the second electrode plate1222.

For example, the first signal output line SG1 and the second signal output line SG2 are located in a same layer as the first electrode plate1221. In this case, the first output terminal OUT1 may be electrically connected to the first signal output line SG1 through one or more via holes penetrating through the third insulating layer1215and the second insulating layer1214, and the second output terminal OUT2 may be electrically connected to the second signal output line SG2 through one or more via holes penetrating through the third insulating layer1215and the second insulating layer1214.

For another example, referring toFIG.4A, the first signal output line SG1 and the second signal output line SG2 are located in a same layer as the second electrode plate1222. In this case, the first output terminal OUT1 may be electrically connected to the first signal output line SG1 through one or more via holes penetrating through the third insulating layer1215, and the second output terminal OUT2 may be electrically connected to the second signal output line SG2 through one or more via holes penetrating through the third insulating layer1215.

FIG.4Bis a schematic cross-sectional view showing the wiring of a pressure sensor according to another embodiment of the present disclosure.

As shown inFIG.4B, the display panel further comprises a first signal input line SI1 electrically connected to the first input terminal IN1, and a second signal input line SI2 electrically connected to the second input terminal IN2. It should be noted that, the manner of electrical connection of the first input terminal IN1 and the first signal input line SI1 is similar to the manner of electrical connection of the second input terminal IN2 and the second signal input line SI2. In a case where the input terminal shown inFIG.4Bis the first input terminal IN1, the signal line shown inFIG.4Bis the first signal input line SI1; in a case where the input terminal shown inFIG.4Bis the second input terminal IN2, the signal line shown inFIG.4Bis the second signal input line SI2.

In the case where the first signal output line SG1 and the second signal output line SG2 are located in a same layer as one of the first electrode plate1221and the second electrode plate1222, the first signal input line SI1 and the second signal input line SI2 are located in a same layer as the other of the first electrode plate1221and the second electrode plate1222. In other words, the two signal output lines SG1 and SG2 are located in different layers from the two signal input lines SI1 and SI2.

For example, referring toFIG.4B, the first signal input line SI1 and the second signal input line SI2 are located in a same layer as the first electrode plate1221. For example, the first input terminal IN1 may be electrically connected to the first signal input line SI1 through one or more via holes penetrating through the third insulating layer1215and the second insulating layer1214, and the second input terminal IN2 may be electrically connected to the second signal input line IG2 through one or more via holes penetrating through the third insulating layer1215and the second insulating layer1214.

In this way, the signal interference between the two signal output lines SG1 and SG2 and the two signal input lines SI1 and SI2 can be reduced.

FIGS.5A and5Bare schematic views showing the layout of a pressure sensor according to some embodiments of the present disclosure.

InFIGS.5A and5B, the first resistor R1 and the third resistor R3 are arranged symmetrically with respect to the first line L1, and the second resistor R2 and the fourth resistor R4 are arranged symmetrically with respect to the second line L2. For example, the first line L1 is perpendicular to the second line L2.

In some embodiments, referring toFIG.5B, the first resistor R1 is located on one side of the first line L1, and the second resistor R2, the third resistor R3, and the fourth resistor R4 are located on the other side of the first line L1. In this way, it is more easily to arrange the four resistors so that the first resistor R1 is subjected to an external pressure, while the other three resistors are not subjected to an external pressure.

In addition,FIGS.5A and5Bschematically show the positions of the first input terminal IN1, the second input terminal IN2, the first output terminal OUT1, and the second output terminal OUT2.

FIG.6is a schematic flowchart showing a manufacturing method of a display panel according to an embodiment of the present disclosure.

At step602, a base substrate is provided. The base substrate comprises a display area and a peripheral area surrounding the display area.

At step604, a plurality of sub-pixels, a first dam, a second dam, and at least one pressure sensor are formed. For example, during the process of forming a sub-pixel, the first dam, the second dam, and the pressure sensor may be formed at the same time.

The plurality of sub-pixels is located at the display area. At least one of the plurality of sub-pixels comprises a driving transistor comprising a plurality of conductive layers.

The first dam and the second dam are located at the peripheral area and surround the display area, and the second dam is located on one side of the first dam away from the display area.

At least one pressure sensor is located on at least one of the first side of the second dam proximate to the first dam and the second side of the second dam away from the first dam. At least one resistor in each of the at least one pressure sensor is located in a same layer as one of the plurality of conductive layers.

At step606, an encapsulation layer located on one side of the plurality of sub-pixels, the first dam and the second dam away from the base substrate is formed.

Here, the orthographic projections of the plurality of sub-pixels, the first dam and the second dam on the base substrate are located within the orthographic projection of the encapsulation layer on the base substrate.

In the above embodiments, at least one pressure sensor is located on at least one of the first side of the second dam proximate to the first dam and the second side of the second dam away from the first dam, and at least one resistance R in each pressure sensor is located in a same layer as one of the plurality of conductive layers in the driving transistor. With such a structure, the pressure sensor can be formed during the process of forming a sub-pixel without additionally providing an interaction button, thereby facilitating reducing the thickness of the display panel.

The present disclosure also provides a display device, which may comprise the display panel according to any one of the above embodiments. In some embodiments, the display device may be, for example, any product or component with a display function, such as a mobile terminal, a television, a monitor, a notebook computer, a digital photo edge, a navigator, or an electronic paper.

For example, the display device is a mobile terminal. In some embodiments, the bezel on one side of the mobile terminal is designed so that an external pressure can be applied to the first resistor R1 in the pressure sensor16of the display panel, while an external pressure cannot be applied to the other three resistors, thus making the output voltage Vout of the pressure sensor16change.

Hereto, various embodiments of the present disclosure have been described in detail. Some details well known in the art are not described to avoid obscuring the concept of the present disclosure. According to the above description, those skilled in the art would fully know how to implement the technical solutions disclosed herein.

Although some specific embodiments of the present disclosure have been described in detail by way of examples, those skilled in the art should understand that the above examples are only for the purpose of illustration and are not intended to limit the scope of the present disclosure. It should be understood by those skilled in the art that modifications to the above embodiments and equivalently substitution of part of the technical features can be made without departing from the scope and spirit of the present disclosure. The scope of the disclosure is defined by the following claims.