Patent ID: 12236141

DETAILED DESCRIPTION

Embodiments of the present disclosure will now be described in detail in conjunction with the accompanying drawings. However, those of ordinary skill in the art will appreciate that, in various embodiments of the present disclosure, many technical details have been proposed to better enable the reader to understand the present disclosure. However, the technical solution claimed in the present disclosure can be implemented without these technical details and various changes and modifications based on the following embodiments.

FIG.1toFIG.4are schematic structural diagrams of memory circuits according to embodiments of the present disclosure.

Referring toFIG.1toFIG.2, the memory circuit includes multiple memory banks10, where each of the memory banks10includes a first memory sub-bank11, a second memory sub-bank12and a third memory sub-bank13sequentially arranged. The second memory sub-bank12includes a first memory section121and a second memory section122. The first memory sub-bank11and the second memory section122are configured to store upper bytes, and the first memory section121and the third memory sub-bank13are configured to store lower bytes.

Embodiments of the present disclosure will be described in more detail below in conjunction with the accompanying drawings.

Referring toFIG.1, the memory circuit may include multiple memory banks10. As the capacity of the memory circuit changes, the capacities, number, and arrangement of the memory banks10will change accordingly. Taking the capacity of the memory circuit being 16 G and the capacity of each memory bank being 1 G as an example, the memory circuit includes sixteen memory banks10(BK0˜BK15), and the arrangement of the memory banks10is 4×4. Furthermore, each memory bank has a corresponding row decoder (not shown) configured to receive a row address signal to activate a corresponding word line, and a column decoder YDEC configured to obtain a readout signal of a bit line of a specific column address. The readout signal is amplified by a sense amplifier and then input into local I/O lines.

It should be noted that the structure of the memory circuit provided in the embodiment of the present disclosure is applicable not only to the capacity of 16 G or less, but also to the capacity of 16 G or more. The adjacent memory banks10share the same peripheral circuit region14including a decoding circuit connected to a word line driver configured to drive the word lines in the memory banks10. In a case of an arrangement of 4×4, two peripheral circuit regions14are provided in each row. Furthermore, the peripheral circuit area14and the column decoder YEDC are located on different sides of the memory bank10.

In addition, the memory circuit further includes a cross-point region circuit XP disposed between four memory banks10(for example, BK0, BK1, BK4, and BK5) adjacent to each other. Structures such as a pull-up drive circuit, a local equalization circuit, an I/O equalization circuit, a precharge circuit, and an equalization drive circuit may be provided in the cross-point region circuit XP. The pull-up drive circuit is configured to supply an operation voltage to a first electrode line to activate the sense amplifier. The local equalization circuit is connected between the first electrode line and the second electrode line in series and configured to connect or disconnect a first electrode line and a second electrode line, and if the first electrode line is connected with the second electrode line, the sense amplifier cannot be activated; the I/O equalization circuit and the precharge circuit are connected in series between a pair of bit lines, the precharge circuit is configured to pull up the voltage of the pair of the bit lines to a half the operation voltage, the I/O equalization circuit is configured to share the charges in the pair of the bit lines, and the equalization drive circuit is configured to activate the I/O equalization circuit and the precharge circuit.

In some embodiments, a number of memory segments in the first memory sub-bank11is identical to a number of memory segments in the third memory sub-bank13, and a number of memory segments in the first memory section121is identical to a number of memory segments in the second memory section122. In this way, it is advantageous to make the number of memory segments storing upper bytes be equal to the number of memory segments storing lower bytes, and ensure that memory banks can effectively store upper bytes and lower bytes having the identical number of bits, thereby avoiding redundancy of memory segments storing upper bytes or lower bytes, and improving utilization of memory banks.

Taking the embodiment shown inFIG.2as an example, the first memory sub-bank1includes thirty-two memory segments (SEG0U˜SEG31U corresponding to1U˜32U), where “U” indicates that the memory segment stores the upper bytes, the third memory sub-bank13also includes thirty-two memory segments (SEG16L˜SEG47L corresponding to17L˜48L), where “L” indicates that the memory segment stores the lower bytes. Accordingly, the first memory section121includes sixteen memory segments (SEG0L˜SEG15L corresponding to1L˜16L), and the second memory section122also includes sixteen memory segments (SEG32U˜SEG47U corresponding to33U˜48U), where “U” indicates that the memory segment stores the upper bytes. It should be noted that as the capacities of the memory circuit and the memory banks change, the number of memory segments included in each memory sub-bank also changes. For example, if the capacity of each memory bank is doubled, the number of memory segments included in each memory sub-bank is doubled.

Furthermore, in a case where the number of the memory segments storing the upper bytes is identical to the number of the memory segments storing the lower bytes, if each of the memory segments includes an identical number of word lines, the number of word lines included in the memory segments storing the upper bytes is identical to the number of word lines included in the memory segments storing the lower bytes. It should be noted that, in different memories, the number of memory cells included in a memory segment may be different from each other. In some embodiments, a sum of the number of memory segments in the first memory section121and the number of memory segments in the second memory section122is equal to the number of memory segments in the first memory sub-bank, that is to say, the number of memory segments in the first memory sub-bank11is identical to the number of memory segments in the the second memory sub-bank12, and to the number of memory segments in the third memory sub-bank13.

As shown inFIG.2, the first memory sub-bank11, the second memory sub-bank12and the third memory sub-bank13each include thirty-two memory segments. In other embodiments, a sum of the number of memory segments in the first memory section121and the number of memory segments in the second memory section122may also be smaller than the number of memory segments in the first memory sub-bank11. In this way, all memory segments in the second memory sub-bank12may also share the row decoder with the memory segments in the first memory sub-bank11or the memory segments in the third memory sub-bank13.

In some embodiments, the logical start address of the memory segments in the first memory sub-bank11, the logical start address of the memory segments in the second memory sub-bank12, and the logical start address of the memory segments in the third memory sub-bank13are sequentially extended. The logical start address of the memory segments in the second memory section122is behind the logical start address of the memory segments in the first memory section121. Since the physical address of the memory cell in each memory segment is equal to the start address of the segment to which the memory cell belongs plus a offset within the segment, the physical address of the memory cell in the second memory section122is behind the physical address of the memory cell in the first memory section121. The physical addresses of the memory cells in the first memory section sub-bank11are not continuous with the physical addresses of the memory cells in the second memory section122. Accordingly, the physical addresses of the memory cells in the first memory section121are not continuous with the physical addresses of the memory cells in the third memory section sub-bank13.

In some embodiments, the first memory sub-bank11includes a third memory section111and a fourth memory section112, and the third memory sub-bank13includes a fifth memory section131and a sixth memory section132. The third memory section111, the first memory section121and the fifth memory section131are arranged side by side, and the fourth memory section112, the second memory section122, and the sixth memory section132are arranged side by side. The first memory section includes a number of word lines identical to a number of word lines included in the third memory section, and the second memory section includes a number of word lines identical to a number of word lines included in the sixth memory section. In this way, it is beneficial to make the first memory section121and the second memory section122share the same row decoder with the memory sections in the memory sub-banks respectively adjacent to the sub-banks where the first memory section121and the second memory section122disposed.

Furthermore, the number of word lines in the first memory section121is identical to the number of word lines in the second memory section122. The number of word lines in the first memory section121is identical to the number of word lines in the third memory section111and to the number of word lines in the fifth memory section131. The number of word lines in the second memory section122is identical to the number of word lines in the fourth memory section112and to the number of word lines in the sixth memory section132.

In some embodiments, referring toFIG.3, the memory circuit includes a first row decoder21disposed between the third memory section111and the first memory section121, and a second row decoder22disposed between the fourth memory section112and the second memory section122. The first row decoder21is configured to activate word lines in the third memory section111and the first memory section121, and the second row decoder22is configured to activate word lines in the fourth memory section112. It is possible to save the circuit area and simplify the memory circuit by using the same row decoder to activate word lines in different memories sub-bank. In addition, the shared row decoder is disposed between the corresponding two memory sections, so that it is advantageous to shorten the connection distance of the circuit, thereby avoiding a long RC delay due to a large resistance of the wires, and improving the readout speed of the memory circuit. Furthermore, the two memory sections sharing the row decoder are configured to store the upper bytes and the lower bytes, respectively, so that it is advantageous to prevent the row decoder from activating an erroneous word line after receiving the row address.

It should be noted that the logical address of the memory segment includes the most significant bit (MSB) and the block selection address, the most significant bit is located in the leftmost bit RA<n> of the row address, and the block selection address is the other bits RA<n−1:0> of the row address. Referring toFIG.2, the most significant bit of the memory segment storing the upper bytes is 0, the most significant bit of the memory segment storing the lower bytes is 1, the block selection addresses of different memory banks storing the same type of bytes (the upper bytes or the lower bytes) are different, for example, SEG0˜SEG47, and the block selection addresses of different memory banks storing the different types of bytes may be the same, for example, all are SEG0˜SEG47.

In some embodiments, the memory circuit further includes a first switch circuit31configured to connect the first row decoder21and the third memory section111, a second switch circuit32configured to connect the second row decoder22and the fourth memory section112, and a third switch circuit33configured to connect the first row decoder21and the first memory section121. The first switch circuit31and the second switch circuit32are configured to receive a first flag signal41and be turned on, and the third switch circuit is configured to receive a second flag signal42and be turned on. The first flag signal41is indicative of reading the upper bytes and the second flag signal42is indicative of reading the lower bytes. The switch circuit is connected between the line decoder and the memory section in series to turn on the line decoder and the memory section storing the byte when the corresponding byte is read, so that it is advantageous to prevent the line decoder from activating erroneous word lines, and improve the accuracy of data read by the memory circuit.

In some embodiments, the memory circuit further includes a third row decoder23disposed between the fifth memory section131and the first memory section121, a fourth row decoder24disposed between the sixth memory section132and the second memory section122. The third row decoder23is configured to activate word lines in the fifth memory section131, and the fourth row decoder24is configured to activate word lines in the second memory section122and the sixth memory section132. The switch circuit connected between the third row decoder23and the fifth memory section131in series is turned on when receiving the second flag signal42, the switch circuit connected between the fourth row decoder24and the sixth memory section132in series is turned on when receiving the second flag signal42, and the switch circuit connected between the fourth row decoder24and the second memory section122in series is turned on when receiving the first flag signal41. Similar to the first row decoder21and the corresponding switch circuit, the arrangement of the fourth row decoder24facilitates to simplify the circuit and improve the readout rate of the memory circuit. In addition, the first row decoder21and the fourth row decoder24with the similar connection and function are provided simultaneously.

Accordingly, the memory circuit further includes: a first sense amplifier141configured to amplify a readout signal of a bit line in the first memory section121, a second sense amplifier142configured to amplify a readout signal of a bit line in the second memory section122, a third sense amplifier43configured to amplify a readout signal of a bit line in the third memory section111, and a fourth sense amplifier44configured to amplify a readout signal of a bit line in the fourth memory section112; and a first control unit51disposed between the first sense amplifier141and the third sense amplifier43, and a second control unit52disposed between the second sense amplifier142and the fourth sense amplifier44. The first control unit51is configured to control the first sense amplifier141and the third sense amplifier, and the second control unit52is configured to control the fourth sense amplifier44. Similarly to the setting of the first row decoder21, a first control unit is provided to connect two adjacent sense amplifiers and control the two adjacent sense amplifiers, so that it is facilitate to simplify the circuit and shorten the RC delay; and simultaneously, it is possible to make the connection between the first control unit51and components adjacent to the first control unit51is similar to the connection between the first row decoder21and components adjacent to the first row decoder21, so that it is facilitate to simplify the layout design of the memory circuit.

Each of the first row decoder21and the first control unit51is disposed between the first memory section121and the third memory section111, and also disposed between the sense amplifier corresponding to the first memory section121and the sense amplifier corresponding to the third memory section111. The first control unit51and the second control unit52are both disposed between the first memory sub-bank11and the second memory sub-bank12.

In some embodiments, the memory circuit further includes a fourth switch circuit34configured to connect the first control unit51and the first sense amplifier141, a fifth switch circuit35configured to connect the first control unit51and the third sense amplifier43, and a sixth switch circuit36configured to connect the second control unit52and the fourth sense amplifier44. The fifth switch circuit35and the sixth switch circuit36are configured to receive the first flag signal41and be turned on, the fourth switch circuit34is configured to receive the second flag signal42and be turned on. The first flag signal41is indicative of reading the upper bytes, and the second flag signal is indicative of reading the lower bytes. Similarly to the setting of the switch circuit described above, the first control unit51is connected to the corresponding sense amplifier at the corresponding timing by setting the switch circuit, so that it is advantageous to ensure that the first control unit51is ready to control the corresponding sense amplifier, thus accurately amplify the minute readout signal on the corresponding bit line, and ensure the accuracy of data readout of the memory circuit.

In some embodiments, the memory circuit further includes a third row decoder23disposed between the first memory section121and the fifth memory section131, a fourth row decoder24disposed between the second memory section122and the sixth memory section132. The third row decoder23is configured to activate word lines in the fifth memory section131, and the fourth row decoder24is configured to activate word lines in the second memory section122and the sixth memory section132.

Accordingly, the memory circuit further includes a fifth sense amplifier45configured to amplify the readout signal of a bit line in the fifth memory section131and a sixth sense amplifier46configured to amplify the readout signal of a bit line in the sixth memory section132. Furthermore, the memory circuit includes a third control unit53and a fourth control unit54. The third control unit53is connected to the fifth sense amplifier45through a corresponding switch circuit to adjust the fifth sense amplifier45when the memory circuit reads the lower bytes, and the fourth control unit54is respectively connected to the second sense amplifier142and the sixth sense amplifier46through different switch circuits, to adjust the second sense amplifier142when the upper bytes are read and adjust the sixth sense amplifier46when the lower bytes are read.

In some embodiments, referring toFIG.4, the memory circuit further includes local input/output (I/O) lines LIO, primary amplifiers60and a global I/O line GIO, where each I/O line LIO is configured to transmit a readout signal amplified by a respective sense amplifier; and each primary amplifier60is configured to receive the readout signal output by the local I/O line LIO and amplify the readout signal, and transmit the readout signal amplified again to the global I/O line GIO.

It can be understood that each local I/O line LIO corresponds to one bit line. The number of bit lines in each memory bank10is identical to the number of columns of the memory array in the memory bank10. That is to say, the more the number of columns of the memory array is, the more the number of bit lines in the memory bank is. Similarly, the number of bit lines in each memory sub-bank is identical to the number of columns of the memory array in the memory sub-bank. In addition, each local I/O line LIO corresponds to a primary amplifier60; the primary amplifier60is configured to receive the readout signal output by the corresponding local I/O line LIO and amplify the readout signal, and the primary amplifier60is connected to the corresponding global I/O line GIO according to the type of the bytes stored in the memory sub-bank.

Among the multi-byte data, the byte is divided into upper bytes and lower bytes. To ensure the accuracy of data readout, the upper bytes are generally transmitted by the upper global I/O line UGIO, and the lower bytes are transmitted by the lower global I/O line LGIO. In some embodiments, the first memory sub-bank11, the second memory sub-bank12, and the third memory sub-bank13each includes 128 bit lines. The global I/O line GIO is configured to transmit sixteen bytes of data, where the first eight bytes are upper bytes and the last eight bytes are lower bytes. Since each byte includes eight bits, the global I/O line GIO is configured to transmit 128 bits of data.

The local I/O line LIO includes a first local I/O line LIO1connected to the first memory sub-bank11and a third local I/O line LIO3connected to the third memory sub-bank13. The global I/O lines include an upper global I/O line UGIO and a lower global I/O line LGIO. The memory circuit further includes: a seventh switch circuit37configured to connect the first local I/O line LIO1and the upper global I/O line UGIO, and receive the first flag signal41and be turned on; and an eighth switch circuit38configured to connect the third local I/O line LIO3and the lower global I/O line LGIO, and receive the second flag signal42and be turned on.

In addition, the local I/O lines further include a second local I/O line LIO2connected to the second memory sub-bank12. The memory circuit further includes: a selector39having one end connected to the second local I/O line LIO2and configured to receive the first flag signal41or the second flag signal42, in response to receiving the first flag signal41, the selector is configured to connect the second local I/O line LIO2and the upper global I/O line UGIO, and in response to receiving the second flag signal42, the selector is configured to connect the second local I/O line LIO2and the lower global I/O line LGIO.

In some embodiments, the primary I/O line and the cross-point region circuit XP are connected in series between the local I/O line LIO and the primary amplifier60, after the readout signal is amplified by the sense amplifier and amplified readout signal is activated by the column selection signal, the activated amplified readout signal is then sequentially transmitted to the local I/O line LIO, the cross-point region circuit, the primary I/O line and the primary amplifier60. After the primary amplifier60amplifies the readout signal again, the amplified readout signal is transmitted to data terminal sequentially through the receiving amplifier, the multiplexer and the output buffer. The receiving amplifier is activated by a corresponding start signal to amplify the minute signal generated on the global I/O line. The multiplexer is a parallel-to-serial conversion circuit that transmits multiple pieces of stored information simultaneously read out from the memory array to the output buffer in time sequence, and the output sequence is controlled by the corresponding data output start signal.

Accordingly, in the write operation, a data signal to be stored is input from the data terminal and transmitted to the input buffer together with the data input start signal, and the data input into the input buffer is transmitted to the word line driver via the de-multiplexer, the global write driver, and the global I/O line GIO. Correspondingly, the de-multiplexer is a circuit that performs serial-to-parallel conversion on the data information continuously input in time sequence. The correspondences between the input data signals and the global I/O line GIO are controlled by the data input start signal, so as to be consistent with the output sequence in the read operation.

Specifically, the selector39may include a first switch391and a second switch392. One end of each of the first switch391and the second switch392is connected to the primary amplifier60to receive the readout signal amplified again, the other end of the first switch391is connected to the upper global I/O line UGIO and configured to receive the first flag signal41and be turned on, and the other end of the second switch392is connected to the lower I/O line LGIO and configured to receive the second flag signal42and be turned on.

In the embodiment of the present disclosure, three memory sub-banks are arranged side by side, the memory sub-bank in the middle position can share the same row decoder with the adjacent memory sub-banks, and it is not necessary to introduce additional row decoders, so that it is advantageous to increase the capacity of the memory bank with a smaller circuit area without increasing the number of memory segments in the memory sub-bank. In addition, the second memory sub-bank in the middle position is configured to store the upper bytes and the lower bytes, and the memory sub-bank on both sides is configured to store the upper bytes or the lower bytes. In this way, it is impossible to make the memory segment storing the upper bytes to share the same row decoder with the memory segment storing the lower bytes, thereby avoiding the shared row decoder from activating the erroneous word line, and improving the readout accuracy of the memory circuit.

Embodiments of the present disclosure further provide a memory including the above-described memory circuit. The memory including the above-described memory circuit may have a small volume and a large capacity to ensure the efficient operation of the package test.

Those of ordinary skill in the art can understand that each embodiment is a specific embodiment implementing the disclosure, and in practical applications, various variations about the form and details can be made thereto without departing from the spirit and scope of the disclosure. Those skilled in the art may make respective alterations and modifications without departing from the spirit and scope of the present disclosure, so the protection scope of the disclosure is subject to the protection scope in claims.

INDUSTRIAL PRACTICABILITY

Embodiments of the present disclosure relate to the semiconductor field, and a memory circuit and a memory are provided. The memory circuit may at least include a plurality of memory banks, each of the memory banks includes a first memory sub-bank, a second memory sub-bank and a third memory sub-bank sequentially arranged, the second memory sub-bank including a first memory section and a second memory section, the first memory sub-bank and the second memory section being configured to store upper bytes, and the first memory section and the third memory sub-bank being configured to store lower bytes. Embodiments of the present disclosure are advantageous to improve integration and capacity of the memory circuit without changing an external size of the circuit.