Patent ID: 12225785

DETAILED DESCRIPTION

In order to make objects, technical details and advantages of embodiments of the present disclosure clear, the technical solutions of the embodiments will be described in a clearly and fully understandable way in connection with the related drawings. It is apparent that the described embodiments are just a part but not all of the embodiments of the present disclosure. Based on the described embodiments herein, those skilled in the art can obtain, without any inventive work, other embodiment(s) which should be within the scope of the present disclosure.

Unless otherwise defined, all the technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms “first,” “second,” etc., which are used in the description and claims of the present disclosure, are not intended to indicate any sequence, amount or importance, but distinguish various components. The terms “comprises,” “comprising,” “includes,” “including,” etc., are intended to specify that the elements or the objects stated before these terms encompass the elements or the objects listed after these terms as well as equivalents thereof, but do not exclude other elements or objects. The phrases “connect”, “connected”, etc., are not intended to define a physical connection or a mechanical connection, but may comprise an electrical connection which is direct or indirect. The terms “on,” “under,” “right,” “left” and the like are only used to indicate relative position relationship, and in a case that the position of an object is described as being changed, the relative position relationship may be changed accordingly.

In the field of OLED (Organic Light-Emitting Diode) display, with the rapid development of high-resolution products, higher requirements are put forward for a structural design of a display substrate, such as an arrangement of pixels and signal lines. For example, compared to an OLED display device with a resolution of 4K, the number of sub-pixel units that need to be arranged in a large-size 8K resolution OLED display device is doubled, and a pixel density is doubled accordingly; on one hand, a line width of the signal line is correspondingly smaller, which leads to an increase of a self-resistance of the signal line; on the other hand, more overlapping regions exist between signal lines, which leads to an increase of parasitic capacitance of the signal lines, thus leading to an increase of resistance capacitance load of the signal lines. Correspondingly, signal delay (RC delay), voltage drop (IR drop), voltage rise (IR rise) and other phenomena caused by the resistance capacitance load of the signal lines also become serious. These phenomena seriously affect a display quality of a display product.

A micro OLED display usually has a size of less than 100 microns, such as a size less than 50 microns, and involves a combination of organic light-emitting diode (OLED) technology and CMOS technology, which manufactures an OLED array on a silicon-based substrate including CMOS circuits.

Micro OLEDs are widely used in fields of AR and VR. With the continuous development of technology, higher resolutions are required for the Micro OLEDs. Therefore, higher requirements are put forward for the structural design of the display substrate, such as the arrangement of the pixels and the signal lines.

A display substrate provided by at least one embodiment of the present disclosure can achieve a sub-pixel area of 5.45 um×13.6 um by an optimized layout and wiring design processing in the design, which realizes a pixel circuit array with a high resolution (PPI) and an optimized arrangement, and achieves a better display effect.

FIG.1Ais a block diagram of a display substrate provided by at least one embodiment of the present disclosure. As shown inFIG.1A, the display substrate10includes a plurality of sub-pixels100arranged in an array, a plurality of scan lines11, and a plurality of data lines12. Each of the plurality of sub-pixels100includes a light-emitting element and a pixel circuit that drives the light-emitting element. The plurality of scan lines11and the plurality of data lines12cross each other to define a plurality of pixel regions distributed in an array in a display region, and a pixel circuit of a sub-pixel100is provided in each of the plurality of pixel regions. The pixel circuit is, for example, a conventional pixel circuit, such as a 2T1C (that is, two transistors and a capacitor) pixel circuit, a 4T2C pixel circuit, a 5T1C pixel circuit, a 7T1C pixel circuit and other nTmC (n, m are positive integers) pixel circuits, and in different embodiments, the pixel circuit may further include a compensation sub-circuit, the compensation sub-circuit includes an internal compensation sub-circuit or an external compensation sub-circuit, and the compensation sub-circuit may include a transistor and a capacitor and so on. For example, according to needs, the pixel circuit may further include a reset circuit, a light-emitting control sub-circuit, and a detection circuit. For example, the display substrate may further include a gate driving sub-circuit13and a data driving sub-circuit14located in a non-display region. The gate driving sub-circuit13is connected with the pixel circuit through the scan lines11to provide various scanning signals, and the data driving sub-circuit14is connected with the pixel circuit through the data lines12to provide data signals. Positional relationships between the gate driving sub-circuit13and the data driving sub-circuit14, and between the scan lines11and the data lines12shown inFIG.1Aare only exemplary, and actual arrangement and positions can be designed as required.

For example, the display substrate10may further include a control circuit (not shown). For example, the control circuit is configured to control the data driving sub-circuit14to apply the data signals and to control the gate driving sub-circuit to apply the scanning signals. An example of the control circuit is a timing control circuit (T-con). The control circuit can be in various forms, for example, including a processor and a memory, the memory includes an executable code, and the processor runs the executable code to execute the above detection method.

For example, the processor may be a central processing unit (CPU) or other form of processing device with data processing capability and/or instruction execution capability, for example, may include a microprocessor, a programmable logic controller (PLC), and so on.

For example, the storage device may include one or more computer program products, the computer program products may include various forms of computer-readable storage media, such as a volatile memory and/or a non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and/or a cache memory. The non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, and so on. One or more computer program instructions can be stored on a computer-readable storage medium, and the processor can execute functions expected by the program instructions. Various application programs and various data can also be stored in the computer-readable storage medium.

The pixel circuit may include a driving sub-circuit, a data writing sub-circuit, a compensation sub-circuit and a storage sub-circuit as required, and may further include a light-emitting control sub-circuit, and a reset circuit as required.

FIG.1Bshows a schematic diagram of a pixel circuit. As shown inFIG.1B, the pixel circuit includes a data writing sub-circuit111, a driving sub-circuit112, and a storage sub-circuit113.

The data writing sub-circuit111is electrically connected with a first terminal of the storage sub-circuit113, and is configured to transmit a data signal Vd to the first terminal of the storage sub-circuit113in response to a control signal (a first control signal SEL). A second terminal of the storage sub-circuit113is, for example, configured to receive a second power voltage VSS.

The driving sub-circuit112includes a control electrode150, a first electrode151and a second electrode152, The control electrode (control terminal)150of the driving sub-circuit is electrically connected with the first terminal of the storage sub-circuit, the first electrode (first terminal)151of the driving sub-circuit112is configured to receive a first power voltage VDD, the second electrode (second terminal)152of the driving sub-circuit112is electrically connected with a first node S, and is connected with a first electrode121of a light-emitting element120. The driving sub-circuit112is configured to drive the light-emitting element120to emit light in response to a voltage at the first terminal of the storage sub-circuit. A second electrode122of the light-emitting element120is, for example, configured to receive a first common voltage Vcom1.

In at least some embodiments of the present disclosure, as shown inFIG.1B, the pixel circuit further includes a bias sub-circuit114. The bias sub-circuit114includes a control terminal, a first terminal and a second terminal, the control terminal of the bias sub-circuit114is configured to receive a bias signal; the first terminal of the bias sub-circuit114is configured to, for example, receive the second power voltage VSS, the second terminal of the bias sub-circuit114is electrically connected with the first node S. For example, the bias signal is a second common voltage Vcom2. For example, the bias signal Vcom2is a constant voltage signal, for example, ranging from 0.8V to 1V; the bias sub-circuit114is normally open under the action of the bias signal, and is configured to provide a constant current, so that the voltage applied to the light-emitting element120has a linear relationship with the data signal, which helps to achieve a fine control of a gray scale, thereby improving a display effect. This will be further explained in the following text in conjunction with specific circuits.

For example, in the case that the data signal (voltage) Vd changes from high to low, a gray-scale voltage written in the first electrode121of the light-emitting element120needs to change rapidly, and the bias sub-circuit114can also allow the first electrode121of the light-emitting element120to release charges quickly, thereby achieving better dynamic contrast.

The transistors used in the embodiments of the present disclosure may all be thin film transistors or field effect transistors or other switching devices with the same characteristics, in the embodiments of the present disclosure, metal-oxide semiconductor field effect transistors are taken as examples for description. A source electrode and a drain electrode of a transistor used herein can be symmetrical in structure, so that there is no difference between the source electrode and the drain electrode of the transistor in structure. In the embodiments of the present disclosure, in order to distinguish the two electrodes of the transistor other than a gate electrode, one electrode is directly described as a first electrode, and the other electrode is a second electrode. In addition, transistors can be divided into an N-type transistor and a P-type transistor according to their characteristics. In a case that the transistor is the P-type transistor, a turn-on voltage is a low-level voltage (for example, 0V, −5V, −10V or other suitable voltages), and an off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltage); in a case that the transistor is the N-type transistor, the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltage), and the off voltage is a low-level voltage (for example, 0V, −5V, −10V or other suitable voltages).

The display substrate provided by the embodiments of the present disclosure may adopt a rigid substrate, such as a glass substrate, a silicon substrate, etc., and can also be formed of flexible materials with excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyaryl compounds, polyetherimide, polyethersulfone, polyethylene glycol terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), triacetyl cellulose (TAC), cyclic olefin polymer (COP) and cyclic olefin copolymer (COC), etc. The embodiments of the present disclosure are described by taking a silicon substrate as an example, that is, the pixel structure is manufactured on the silicon substrate, however, the embodiment of the present disclosure are not limited thereto.

For example, the pixel circuit includes a complementary metal oxide semiconductor circuit (CMOS circuit), that is, the pixel circuit is manufactured on a monocrystal silicon substrate. Relying on mature CMOS integrated circuit technology, silicon-based technology can achieve higher accuracy (for example, the PPI can reach 6,500 or even more than 10,000).

For example, in the case that a short circuit occurs between the first electrode121and the second electrode122of the light-emitting element120in the sub-pixel due to process fluctuations of the display substrate, the voltage of the first electrode121of the light-emitting element120is too high (for example, the first common voltage Vcom1is at a high potential) or too low (for example, the first common voltage Vcom1is at a low potential), causing a PN junction between the second electrode of the driving circuit and the base substrate to turn on, and causing failure of the CMOS circuit, and resulting in defects such as dark lines in the display substrate.

In some examples, for example, the data writing sub-circuit includes a first data writing transistor P1, and the driving sub-circuit includes a driving transistor N2; for example, the first data writing transistor is a P-type metal-oxide semiconductor field effect transistor (PMOS), the driving transistor N2is an N-type metal-oxide semiconductor field effect transistor (NMOS), a gate electrode, a first electrode, and a second electrode of the driving transistor N2serve as the control electrode150, the first electrode151and the second electrode152of the driving sub-circuit112, respectively. In this case, for example, in a case that the first common voltage Vcom1supplied to the second electrode122of the light-emitting element120is at a low potential, and the first electrode121and the second electrode122of the light-emitting element120are short circuited, the potential of the second electrode of the driving transistor directly connected with the first electrode121is caused to be too low.

FIG.1Cshows a schematic diagram of the failure of the transistors in the pixel circuit. An N-type active region (such as the second electrode) of the driving transistor N2, a P-type silicon-based substrate, an N-type well region where the first data writing transistor P1is located, and a P-type active region (such as the first electrode) of the first data writing transistor P1form two parasitic transistors Q1and Q2that are connected with each other, which forms an N-P-N-P structure. In the case that the potential of the second electrode (that is, the first node S) of the driving transistor N2is too low, causing a PN junction (a transmitting junction) between the second electrode (a heavily-doped N-type region) of the driving transistor N2and the P-type substrate to be positively biased and Q1to be turned on, which provides a current large enough to turn on the parasitic transistor Q2; in turn, the parasitic transistor Q2feeds back a current to the parasitic transistor Q1, to form a vicious circle, finally most of the current flows directly from VDD to VSS through the parasitic transistors without being controlled by the gate voltage of the transistor, which causes the CMOS pixel circuit to fail; in addition, the failure of the circuit will cause the parasitic transistor Q2to continuously draw a current from a emitter, i.e., the data line, thereby causing a column of sub-pixels connected with the data line to fail, and causing defects such as a dark line on the display substrate, which greatly affects the display effect.

In at least some embodiments of the present disclosure, at least one sub-pixel further includes a resistance device, the resistance device is connected between the second electrode152of the driving sub-circuit112and the first electrode121of the light-emitting element120, and the resistance device can increase or decrease the potential of the first node S, so that the latch-up effect can be relieved or avoided, the reliability of the circuit can be improved, and the display effect can be improved.

FIG.2Ais a schematic diagram of a pixel circuit provided by at least one embodiment of the present disclosure. As shown inFIG.2A, the pixel circuit further includes the resistance device130, the first terminal131of the resistance device130is electrically connected with the second electrode152of the driving sub-circuit112, and the second terminal132is electrically connected with the first electrode121of the light-emitting element120, that is, the second electrode152of the driving sub-circuit112is electrically connected with the first electrode121of the light-emitting element120through the resistance device130.

For example, the resistance device130is a constant resistor or a variable resistor, and may also be an equivalent resistor formed by other devices (such as a transistor).

For example, the resistance device130and the control electrode150of the driving sub-circuit112are arranged in a same layer and insulated from each other, and a resistivity of the resistance device is higher than a resistivity of the control electrode of the driving sub-circuit; that is, a conductivity of the control electrode of the driving sub-circuit is higher than a conductivity of the resistance device. For example, the resistivity of the resistance device is more than ten times of the resistivity of the control electrode.

It should be noted that the “in a same layer” mentioned in the present disclosure refers to forming two (or more than two) structures through a same deposition process and patterning them through a same patterning process, and the materials of the structures can be the same or different. For example, the materials for forming precursors of the structures arranged in the same layer are the same, and the finally formed materials may be the same or different. The “an integrated structure” in the present disclosure refers to an interconnected structure formed by forming two (or more than two) structures through a same deposition process and patterning them through a same patterning process, and the materials of the structures can be the same or different.

Through this arrangement, the control electrode of the driving sub-circuit and the resistance device can be formed in the same patterning process, thereby saving process.

For example, both a material of the resistance device and a material the control electrode of the driving sub-circuit are polysilicon materials, and a doping concentration of the resistance device is lower than a doping concentration of the control electrode, thus the resistance device has a higher resistivity than the control electrode. For example, the resistance device may be intrinsic polysilicon or lightly doped polysilicon, and the control electrode may be heavily doped polysilicon.

In other examples, the material of the control electrode is different from the material of the resistance device. For example, the material of the control electrode may include a metal and the material of the resistance device may comprise a metal oxide corresponding to the metal. For example, the metal may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloy materials composed of the above metals.

In at least one embodiment of the present disclosure, the data writing sub-circuit111may include a transmission gate circuit composed of two complementary transistors in parallel connection with each other; the control signal includes two inverted control signals. The data writing sub-circuit111adopts a circuit in a transmission gate structure, which can help to transmit the data signal to the first terminal of the storage sub-circuit113with no loss.

For example, the data writing sub-circuit includes a first control electrode, a second control electrode, a first terminal and a second terminal, the first control electrode and the second control electrode of the data writing sub-circuit are respectively configured to receive a first control signal and a second control signal, the first terminal of the data writing sub-circuit is configured to receive a data signal, and the second terminal of the data writing sub-circuit is electrically connected to the first terminal of the storage sub-circuit, and is configured to transmit the data signal to the first terminal of the storage sub-circuit in response to the first control signal and the second control signal.

It should be noted that in the description of the embodiments of the present disclosure, the first node S does not necessarily represent an actual component, but represents a junction for connecting related circuits in a circuit diagram.

It should be noted that in the description of the embodiments of the present disclosure, the symbol Vd can represent both the data signal terminal and a level of the data signal, similarly, the symbol SEL can represent both a control signal and a control signal terminal, the symbols Vcom1and Vcom2can represent a first common voltage and a second common voltage, and can also represent a first common voltage terminal and a second common voltage terminal; the symbol VDD can represent both a first voltage terminal and a first power voltage, and the symbol VSS can represent both a second voltage terminal and a second power voltage. The case is the same in the following embodiments and is not repeated.

FIG.2Bshows a circuit diagram of a specific implementation example of the pixel circuit shown inFIG.2A. As shown inFIG.2B, the data writing sub-circuit111includes a first data writing transistor P1and a second data writing transistor N1that are connected in parallel with each other. The first data writing transistor P1and the second data writing transistor N1are a P-type metal-oxide semiconductor field effect transistor (PMOS) and an N-type metal-oxide semiconductor field effect transistor (NMOS), respectively. The control signal includes a first control signal SEL and a second control signal SEL_B that are inverted to each other, a gate electrode of the first data writing transistor P1serves as the first control electrode of the data writing sub-circuit, and is configured to receive the first control signal SEL, a gate electrode of the second data writing transistor N1serves as the second control electrode of the data writing sub-circuit, and is configured to receive the second control signal SEL_B. The first electrode of the second data writing transistor N1and the first electrode of the first data writing transistor P1are electrically connected and serve as the first terminal of the data writing sub-circuit, and are configured to receive a data signal Vd; the second electrode of the second data writing transistor N1and the second electrode of the first data writing transistor P1are electrically connected and serve as the second terminal of the data writing sub-circuit, and is electrically connected with the control electrode150of the driving sub-circuit112.

For example, the first data writing transistor P1and the second data writing transistor N1have a same size and a same channel width to length ratio.

The data writing sub-circuit111take advantages of the complementary electrical characteristics of the transistors and has a low on-state resistance regardless of whether transmitting a high level or a low level, so that the data writing sub-circuit111has an advantage of electrical signal integrity in the transmission, and can transmit the data signal Vd to the first terminal of the storage sub-circuit113without loss.

For example, as shown inFIG.2B, the driving sub-circuit112includes a driving transistor N2, for example, the driving transistor N2is NMOS. The gate electrode, the first electrode and the second electrode of the driving transistor N2serve as the control electrode, the first electrode and the second electrode of the driving sub-circuit112, respectively.

For example, the storage sub-circuit113includes a storage capacitor Cst, the storage capacitor Cst includes a first capacitor electrode141and a second capacitor electrode142, and the first capacitor electrode141and the second capacitor electrode142serve as the first terminal and the second terminal of the storage sub-circuit113, respectively.

For example, the resistance device130includes a resistor R. For example, a PN junction is formed between the second electrode152of the driving sub-circuit112and the base substrate, a resistance value of the resistance device130is configured that in a case that the driving transistor N2is operating in a saturation region, that is, in a case that the pixel circuit operates to drive the light-emitting element120to emit light, the PN junction is turned off. In this situation, even if a short circuit occurs between the two electrodes of the light-emitting element120, because a voltage drop is occurred on the resistance device130, the potential of the second electrode152can be protected, so that the occurrence of the failure of the circuit is avoided.

For example, the resistance value R of the resistance device130meets:

R>❘"\[LeftBracketingBar]"Vs-Von-Vcom⁢1❘"\[RightBracketingBar]"Is,
where Vs is a bias voltage of the base substrate, Vcom1is the first common voltage provided for the second electrode of the light-emitting element, Von is the turn-on voltage of the PN junction, and Is is a saturation current of the driving transistor N2working in the saturation region, that is ½μnCoxW/L(Vgs−Vth)2, where μnis a carrier mobility of the driving transistor, Coxis a capacitance per unit area of the gate insulating layer, W/L is a width to length ratio of the channel region, Vgs is a voltage difference between the gate electrode and the source electrode of the driving transistor, and Vth is a threshold voltage of the driving transistor. For example, the turn-on voltage Von ranges from 0.6 V to 0.7V. Through the above arrangement, it can be ensured that the PN junction formed between the second electrode152of the driving sub-circuit112and the base substrate is turned off in a case that the driving transistor N2is working in the saturation region.

For example, the light-emitting element120is specifically implemented as an organic light-emitting diode (OLED). For example, the light-emitting element120may be an OLED with a top emitting structure, which may emit red light, green light, blue light, or white light. For example, the light-emitting element120is a micro OLED. The embodiments of the present disclosure do not limit the specific structure of the light-emitting element. For example, the first electrode121of the light-emitting element120is an anode of the OLED, the second electrode122is a cathode of the OLED, that is, the pixel circuit has a common cathode structure. However, the embodiments of the present disclosure are not limited thereto; the pixel circuit may also be in a common anode structure according to the change of the circuit structure.

For example, the bias sub-circuit114includes a bias transistor N3, and the gate electrode, the first electrode and the second electrode of the bias transistor N3serve as the control terminal, the first terminal and the second terminal of the bias sub-circuit114, respectively.

FIG.2Cshows a signal timing diagram of the pixel circuit shown inFIG.2B, the working principle of the pixel circuit shown inFIG.2Cis described below in conjunction with the signal timing diagram shown inFIG.2B. For example, the second data writing transistor, the driving transistor, and the bias transistor are all N-type transistors, and the first data writing transistor is a P-type transistor, however, the embodiments of the present disclosure are not limited thereto.

FIG.2Cshows waveform diagrams of each signal in two consecutive display periods T1and T2, for example, the data signal Vd is a high gray-scale voltage during the display period T1, and the data signal Vd is a low gray-scale voltage during the display period T2.

For example, as shown inFIG.2C, a display process of each frame of image includes a data writing stage1and a light-emitting stage2. A working process of the pixel circuit includes: in the data writing stage1, both the first control signal SEL and the second control signal SEL_B are turn-on signals, the first data writing transistor P1and the second data writing transistor N1are turned on, the data signal Vd is transmitted to the gate electrode of the driving transistor N2through the first data writing transistor P1and the second data writing transistor N1; in the light-emitting stage2, both the first control signal SEL and the second control signal SEL_B are off signals, due to a bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains unchanged, the driving transistor N2works in a saturated state and has an unchanged current, and drives the light-emitting element120to emit light. In a case that the pixel circuit enters the display period T2from the display period T1, the data signal Vd changes from a high gray-scale voltage to a low gray-scale voltage, the bias transistor N3under the control of the second common voltage Vcom2generates a stable drain current which can quickly discharge the charge stored in the anode of the OLED in a case that the display gray scale of the OLED needs to change rapidly. For example, the discharge process occurs during data writing stage1in the display period T2, and thus in the light-emitting stage2of the display period T2, the voltage of the anode of the OLED can be rapidly reduced, so that a better dynamic contrast is achieved, and the display effect is improved.

Referring toFIG.2B, for example, in the light-emitting stage, a light-emitting current of the light-emitting element OLED is on the order of nanoamperes (for example, a few nanoamperes) in a case that the light-emitting element OLED is written in a gray-scale data, while the bias transistor N3generates a current generated on the order of microamperes (for example, 1 microampere) while working in the saturation region under the control of the bias signal, i.e. the second common voltage Vcom2, and thus almost all the current flowing through the driving transistor N2flows into the bias transistor N3, the current of the driving transistor N2and the current of the bias transistor N3can be regarded as the same, that is ½μnCoxW/L(Vgs1−Vth1)2=½μnCoxW/L(Vgs2−Vth2)2, here it is assumed that the driving transistor N2and the bias transistor N3have a same transistor conductivity μnCoxW/L, then it is obtained that Vgs1−Vth1=Vgs2−Vth2, in which Vgs1and Vth1are the voltage difference Vgs1between the gate electrode and the source electrode of the driving transistor N2and the threshold voltage of the driving transistor N2, respectively; Vgs2and Vth2are the voltage difference between the gate electrode and the source electrode of the bias transistor N3and the threshold voltage of the bias transistor N3, respectively; and because Vgs2−Vth2=Vcom2−VSS−Vth2, which is a fixed value, denoted as K0, that is, Vgs1−Vth1=K0, that is, Vd−V0−Vth1=K0, in which Vd is the data signal held at the gate electrode of the driving transistor N2during the light-emitting stage, V0is the voltage at the first node S. In this way, it can be concluded that the voltage V0at the first node S has a linear relationship with the data signal (data voltage) Vd.

For example, the bias transistor N3works in a saturation region under the control of the bias signal Vcom2, and a difference between a voltage of the gate electrode and a voltage of the source electrode of the bias transistor is Vcom2−VSS and is a fixed value; according to the above formula of a current of the transistor in a saturation region, the current flowing through the bias transistor N3in this situation is a constant current, so the bias transistor N3can be regarded as a current source.

For example, in the case that the first node S is directly electrically connected with the light-emitting element120, the voltage V0is directly applied to the first electrode121of the light-emitting element120, and is an anode voltage of the OLED for example; in a case that the first node S is electrically connected with the light-emitting element120through the resistance device130, because the current flowing through the light-emitting element120is extremely small, a voltage of the first node S can be approximately equal to a voltage of the first electrode121of the light-emitting element120; that is, the voltage of the first electrode121of the light-emitting element120is in a linear relationship with the data signal (data voltage) Vd, so that a fine control of the gray scale can be realized, and the display effect can be improved.

For example, the first control signal SEL and the second control signal SEL_B are differential complementary signals with a same amplitude but opposite phases, which helps to improve an anti-interference performance of the circuit. For example, the first control signal SEL and the second control signal SEL_B can be output by a same gate driving circuit unit (such as a GOA unit), thereby simplifying the circuit.

For example, as shown inFIG.1A, the display substrate10may further include a data driving circuit13and a scan driving circuit14. The data driving circuit13is configured to send out a data signal, such as the above-mentioned data signal Vd, as required (for example, inputting an image signal to the display device). The scan driving circuit14is configured to output various scanning signals, for example, including the above-mentioned first control signal SEL and second control signal SEL_B, for example, the scan driving circuit14is an integrated circuit chip (IC) or a gate driving circuit (GOA) directly manufactured on the display substrate.

For example, the display substrate uses a silicon substrate as the base substrate101, the pixel circuit, the data driving circuit13and the scan driving circuit14can all be integrated on the silicon substrate. In this case, since the silicon-based circuit can achieve a higher accuracy, the data driving circuit13and the scan driving circuit14may also be formed, for example, in a region corresponding to the display region of the display substrate, and are not necessarily located in the non-display region.

For example, the display substrate10further includes a control circuit (not shown). For example, the control circuit is configured to control the data driving circuit13to apply the data signal Vd, and to control the gate driving circuit13to apply various scanning signals. An example of the control circuit is a timing control circuit (T-con). The control circuit can be in various forms, for example, including a processor and a memory, the memory includes executable code, and the processor runs the executable code to execute the above detection method.

For example, the processor may be a central processing unit (CPU) or another form of processing device with data processing capability and/or instruction execution capability, for example, may include a microprocessor, a programmable logic controller (PLC), and so on.

For example, the storage device may include one or more computer program products, the computer program product may include various forms of computer-readable storage media, such as a volatile memory and/or a non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and/or a cache memory. The non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, and so on. One or more computer program instructions can be stored on a computer-readable storage medium, and the processor121can execute functions expected by the program instructions. Various application programs and various data can also be stored in the computer-readable storage medium, for example, the electrical characteristic parameters obtained in the above detection method.

The following uses the pixel circuit shown inFIG.2Bas an example to illustrate the display substrate provided by at least one embodiment of the present disclosure, but the embodiments of the present disclosure are not limited thereto.

FIG.3Ais a schematic diagram of a display substrate10provided by at least one embodiment of the present disclosure. For example, as shown inFIG.3A, the display substrate10includes a base substrate101, and a plurality of sub-pixels100are located on the base substrate101. The plurality of sub-pixels100are arranged as a sub-pixel array, a row direction of the sub-pixel array is a first direction D1, a column direction of the sub-pixel array is a second direction D2, and the first direction D1intersects the second direction D2, for example, the first direction D1is orthogonal to the second direction D2.FIG.3Aexemplarily shows two rows and six columns of sub-pixels, that is, two pixel rows20and six pixel columns30, and uses dashed-line frames to respectively show the regions of three pixel columns spaced apart from each other.

For example, the base substrate101may be a rigid substrate, such as a glass substrate, a silicon substrate, etc., and can also be formed of flexible materials with excellent heat resistance and durability, such as polyimide (PI), polycarbonate (PC), polyethylene terephthalate (PET), polyethylene, polyacrylate, polyaryl compounds, polyetherimide, polyether Sulfone, polyethylene glycol terephthalate (PET), polyethylene (PE), polypropylene (PP), polysulfone (PSF), polymethyl methacrylate (PMMA), triacetyl cellulose (TAC), cyclic olefin polymer (COP) and cyclic olefin copolymer (COC), etc. The embodiments of the present disclosure are described by always taking the base substrate101as a silicon substrate as an example, however, the embodiment of the present disclosure does not limit to this.

For example, the base substrate101includes monocrystal silicon or high-purity silicon. The pixel circuit is formed on the base substrate10through a CMOS semiconductor process, for example, an active region of the transistor (including the channel region, the first electrode and the second electrode of the transistor) is formed in the base substrate101through a doping process, each insulating layer is formed by a silicon oxidation process or a chemical vapor deposition process (CVD), and a plurality of conductive layers are formed by a sputtering process to form wiring structures. The active region of each of the transistors is located inside the base substrate101.

FIG.3Bshows a cross-sectional schematic diagram ofFIG.3Aalong a section line I-I′. For clarity, some traces or electrode structures that are not directly connected are omitted inFIG.3B.

For example, as shown inFIG.3B, the display substrate10includes a base substrate101, a first insulating layer201, a polysilicon layer102, a second insulating layer202, a first conductive layer301, a third insulating layer203, a second conductive layer302, a fourth insulating layer204, a third conductive layer303, a fifth insulating layer205and a fourth conductive layer304that are sequentially located on the base substrate101. In the following, the structure of the display substrate10will be described hierarchically, andFIG.3Bwill be used as a reference and will be described together.

For clarity and convenience of description,FIG.4Ashows a portion of the display substrate10located below the first conductive layer301, that is, the base substrate101and the first insulating layer201and the polysilicon layer102on the base substrate101, including each of the transistors (P1, N1-N3), a storage capacitor Cst, and a resistance device130;FIG.4Bshows an enlarged schematic diagram of a sub-pixel100inFIG.4A; for clarity, the section line I-I′ inFIG.3Ais also correspondingly shown inFIG.4A,FIGS.5A to5Eshow a formation process of the substrate structure shown inFIG.4A.

As shown inFIG.4B, for example, in a direction parallel to a plate surface of the base substrate101, the first data writing transistor P1and the driving transistor N2are on opposite sides of the storage capacitor Cst, for example, are on opposite sides of the storage capacitor Cst in the second direction D2.

With reference toFIG.1C, this arrangement helps to increase a distance between the first data writing transistor P1and the driving transistor N2, so that the resistance of the parasitic circuit is increased, and the risk of the failure of the CMOS circuit is further reduced.

For example, a material of the second capacitor electrode142of the storage capacitor140is a conductor or a semiconductor. For example, as shown inFIG.3BandFIG.4B, the second capacitor electrode142of the storage capacitor140is a first region401of the base substrate101; for example, the base substrate101is a P-type silicon-based substrate, and the material of the second capacitor electrode142is P-type monocrystal silicon. In a case that a voltage is applied to the first capacitor electrode141, the semiconductive first region401located under the first capacitor electrode141in the base substrate101forms an inversion region and becomes a conductor, so that the first region401is electrically connected with the contact hole regions (the contact hole regions145aand145bas shown inFIG.4B) on both sides of the first region401. In this case, no additional doping process is performed on the first region401.

In another example, the first region401is, for example, a conductive region in the base substrate101, such as a heavily doped region, so that the second capacitor electrode142can obtain a stable and higher conductivity.

For example, the base substrate101further includes a second region402, and the second region402is an N-type well region in the base substrate101. As shown inFIG.4B, for example, the first data writing transistor P1and the resistance device130are arranged side by side in the second direction D2in the second region402. Arranging the resistance device130made of polysilicon material in the N-type substrate helps to reduce parasitic effects, and improve the circuit characteristics.

For example, in a direction parallel to the plate surface of the base substrate101, the resistance device (R)130and the first data writing transistor P1are located on a same side of the second capacitor electrode142. For example, in a direction parallel to the surface of the base substrate101, the driving transistor N2and the bias transistor N3are located on a same side of the second capacitor electrode142.

For example, as shown inFIG.4B, the first data writing transistor P1and the second data writing transistor P1are arranged side by side in the first direction D1, and are symmetrical about a symmetry axis along the second direction D2. For example, the gate electrode160of the first data writing transistor P1and the gate electrode170of the second data writing transistor N1are arranged side by side in the first direction D1, and are symmetrical about the symmetry axis along the second direction D2.

For example, the resistance device130is a U-shaped structure, such as an asymmetrical U-shaped structure, for example, lengths of two branches of the U-shaped structure are not equal. For example, as shown inFIG.4B, the second terminal132of the resistance device130is closer to the driving transistor N2.

The resistance device130arranged as a U-shaped structure helps to save a layout area occupied by the resistance device, so that the space utilization of the layout is improved, which helps to improve a resolution of the display substrate. For example, in a same space, the resistance device with the U-shaped structure can increase the length of the resistance device, so that a desired resistance value is obtained.

In addition, a design of the resistance device130as an asymmetric structure is also to make a reasonable use of the layout space. For example, as shown inFIG.4B, a contact hole region411ais designed above a shorter branch of the U-shaped resistor. The contact hole region411ais side by side with the second terminal132of the resistance device130in the first direction D1. For example, the contact hole region411ais an N-type heavily doped region (N+). For example, the contact hole region411is used to bias the well region401where the first data writing transistor P1is located, so that a threshold voltage change caused by parasitic effects such as a substrate bias effect is avoided, and the stability of the circuit is improved. For example, referring toFIG.3B, by applying a low-voltage bias to the P-type substrate101and a high-voltage bias to the N-type well region402, the parasitic PN junction between the P-type substrate101and the N-type well region402can be reversely biased, so that electrical isolate between devices is realized, the parasitic effect between the devices is reduced, and the stability of the circuit is improved.

For example, an opening of the U-shaped structure faces the first capacitor electrode141, the first terminal131and the second terminal132of the resistance device130are respectively located at two ends of the U-shaped structure. As shown in the figure, the first terminal131of the resistance device130is provided with a contact hole region133for electrically connecting with the gate electrode150of the driving transistor N2; the second terminal132of the resistance device130is provided with a contact hole region134for electrical connection with the first electrode121of the light-emitting element120.

For example, the material of the resistance device130includes polysilicon material, the contact hole regions133and134are doped regions for reducing contact resistance; a body region of the resistance device130other than the contact hole region is, for example, an intrinsic region or a low-doped region, so that a desired resistance value is obtained.

For example, the first capacitor electrode141of the storage capacitor140and the resistance device130are arranged in a same layer and insulated from each other, and both include a polysilicon material; and a doping concentration of the first capacitor electrode141of the storage capacitor140is higher than a doping concentration of the body region of the resistance device130. For example, the body region of the resistance device130is an intrinsic polysilicon material.

For example, the gate electrodes160,170,150, and180of the transistors P1, N1to N3and the first capacitor electrode141of the storage capacitor140are arranged in a same layer, and all include a polysilicon material. For example, as shown inFIG.4B, the gate electrode150of the driving transistor N2and the first capacitor electrode141are connected with each other as an integral structure.

FIG.4Balso shows active regions P1a, N1a, N2a, and N3aof the transistors P1, N1to N3, respectively, and shows a first electrode161and a second electrode162of the first data writing transistor P1, a first electrode171and a second electrode172of the second data writing transistor N1, a first electrode151and a second electrode of the driving transistor N2, a first electrode181and a second electrode182of the bias transistor N3.

FIG.4Balso shows a gate contact region165, a first contact region163, and a second electrode contact region164of the first data writing transistor P1, a gate contact region175, a first contact region173, and a second electrode contact region174of the second data writing transistor N1, a gate contact region155, a first contact region153and a second electrode contact region154of the driving transistor N2, and a gate contact region185, a first contact region183, and a second electrode contact region184of the bias transistor N3. For example, each of the first electrode contact regions is a region where the corresponding first electrode is used to form electrical contacts, each of the second electrode contact regions is a region where the corresponding second electrode contact region is used to form electrical contacts, and each of the gate contact region is an area where the corresponding gate electrode is used to form electrical contacts.

For example, the active region P1aof the first data writing transistor P1and the active region N1aof the second data writing transistor N1are arranged side by side in the first direction D1, and are symmetrical about a symmetry axis along the second direction D2.

As shown inFIG.4B, an area of the active region N2aof the driving transistor N2is larger than an area of other transistors, so that a greater width to length ratio can be obtained, which helps to improve the driving capability of the driving transistor N2and improve the display effect.

As shown inFIG.4B, for the transistor with a larger active region, such as the drive transistor N2and the bias transistor N3, since the space is enough, at least two contact hole regions can be respectively provided on the first electrode and the second electrode of the drive transistor N2and the bias transistor N3, So that the drive transistor N2and the bias transistor N3can get sufficient contact with the structure to be connected and form a parallel structure, thereby reducing the contact resistance.

FIG.4Balso shows a contact hole region144on the first capacitor electrode141and contact hole regions145aand145bthat are configured to be electrically connected with the second capacitor electrode142. As shown inFIG.4B, the first capacitor electrode141and the second capacitor electrode142are respectively arranged with at least two contact hole regions to reduce the contact resistance.

With reference toFIG.4A, the transistors (including the shape and size of each transistor, etc.), the storage capacitors, and the resistance devices in two sub-pixels100adjacent in the first direction D1are symmetrical about a symmetry axis along the second direction D2respectively, that is, the corresponding structures in the two sub-pixels are respectively symmetrical about the symmetry axis along the second direction D2. The transistors in two sub-pixels100adjacent in the second direction D2is axially symmetrical with respect to a symmetry axis along the first direction.

The symmetrical arrangement can maximize a uniformity of process errors, so that a uniformity of the display substrate is improved. In addition, the symmetrical arrangement allows some structures in the substrate that are arranged in a same layer and are connected with each other to be integrally formed, compared with separate arrangements, the symmetrical arrangement can make the pixel layout more compact, and improves the space utilization, so that the resolution of the display substrate is improved.

For example, as shown inFIG.4A, second regions402of two sub-pixels100adjacent in the first direction D1are in an integral structure, second regions402of two sub-pixels100adjacent in the second direction D2are in an integral structure, that is, the first data writing transistor N1and the resistance device130in the four adjacent sub-pixels100are located in a same well region. Compared with separate well regions, this arrangement can make the arrangement of pixels more compact under the premise of meeting the design rules, which helps to improve the resolution of the display substrate.

For example, as shown inFIG.4A, the active regions P1aof the first data writing transistors P1of two sub-pixels adjacent in the second direction D2are connected with each other as an integral structure, that is, the active regions P1aof the two first data writing transistors P1are located in a same doped region A1(P well) of the same second region402, and the first electrodes of the two first data transistors P1are connected with each other as an integral structure, to receive the same data signal Vd.

For example, as shown inFIG.4A, the active regions N1aof the second data writing transistors N1of two sub-pixels adjacent in the second direction D2are connected with each other as an integral structure, that is, the active regions N1aof the two second data writing transistors N1are located in a same doped region A2(N-well) of the base substrate101, and the first electrodes of the two second data writing transistors N1are connected with each other as an integral structure, to receive the same data signal Vd.

For example, as shown inFIG.4A, the gate electrodes of the first data writing transistor P1or the gate electrodes of the second data writing transistor N2of two sub-pixels100adjacent in the first direction D1are connected with each other to form an integral structure.

Since for each row of pixels, the gate electrodes of the first data writing transistor P1are all configured to receive the same first control signal SEL, and the gate electrodes of the second data writing transistor N1are all configured to receive the same second control signal SEL_B; additionally, since the transistors of the two sub-pixels adjacent in the first direction D1are mirror-symmetrical, and the case where the first data writing transistor P1of two sub-pixels are adjacent and the case where the second data writing transistors N1of two sub-pixels are adjacent happen alternately in the first direction D1; therefore, the gate electrodes of two adjacent first data writing transistors P1can be directly connected as an integral structure to form a first control electrode group191, and the gate electrodes of the adjacent second data writing transistors N1can be directly connected as an integral structure to form a second control electrode group192. This arrangement can make the arrangement of the pixels more compact on the premise of meeting the design rules, which helps to improve the resolution of the display substrate.

As shown inFIG.4A, for two sub-pixels100adjacent in the first direction D1, in a case that their driving transistors N2are adjacent to each other, the active regions N2aof the two driving transistors N2are connected with each other as an integral structure, that is, the active regions N2aof the two driving transistors N2are located in a same doped region B (N well) of the base substrate101, and the first electrodes of the two driving transistors N2are connected with each other as an integral structure to form a third control electrode group193, to receive the same first power supply voltage VDD; in a case that their bias transistors N3are adjacent to each other, the gate electrodes of the two bias transistors N3are connected to each other as an integral structure, to receive the same second common voltage Vcom2; the active regions N3aof the two bias transistors N3are connected with each other as an integral structure, that is, the active regions N3aof the two bias transistors N3are located in a same doped region C (N well) of the base substrate101, and the first electrodes of the two bias transistors N3are connected with each other to form an integral structure, to receive the same second power voltage VSS.

This arrangement can make the arrangement of the pixels more compact on the premise of meeting the design rules, which helps to improve the resolution of the display substrate.

FIGS.5A to5Dshow the formation process of the substrate structure shown inFIG.4A, for clarity, only two rows and two columns of sub-pixels are shown in the figure, that is, four adjacent sub-pixels100are shown, and the four sub-pixels100form a pixel unit group420.FIG.4Aillustrates the pixel unit group420with a dotted box. For example, the display substrate comprises a plurality of pixel unit groups arranged along the first direction and the second direction.

In the following, a forming process of the display substrate provided by the embodiment of the present disclosure will be exemplarily described with reference toFIGS.5A to5D, but this is not a limitation of the present disclosure.

For example, a silicon-based substrate is provided, for example, a material of the silicon-based substrate is P-type monocrystalline silicon. N-type transistors (such as driving transistors) can be directly manufactured on the P-type silicon substrate, that is, the P-type substrate serves as the channel region of the N-type transistors, which is conducive to taking advantage of a high speed of NMOS devices, and improves the circuit performance.

As shown inFIG.5A, for example, N-type doping is performed on a P-type silicon substrate, to form an N-type well region, that is, the second region402, which serves as a substrate for the first data writing transistor P1and the resistance device130.

For example, the second regions402of two sub-pixels adjacent in the first direction D1may be connected with each other, and the second regions402of two sub-pixels adjacent in the second direction D2may be connected with each other. For example, the region which is not to be doped in the base substrate101is shielded while performing the N-type doping treatment.

As shown inFIG.4BandFIG.5B, for example, a first insulating layer201is formed on the base substrate101, then a polysilicon layer102is formed on the first insulating layer201.

The first insulating layer201includes the gate insulating layer of each of the transistors, and further includes a dielectric layer104of the storage capacitor Cst. The polysilicon layer102includes a first capacitor electrode141, a resistance device130, and gate electrodes150,160,170, and180of each of the transistors (P1, N1to N3).

The gate electrode of the first data writing transistor P1is located in the second region402, and the N-type well region serves as the channel region of the P-type transistor. The resistance device130is also located in the second region402, that is, an orthographic projection of the resistance device130on the base substrate is in the second region4. Forming the resistance device130made of polysilicon material in the N-type substrate helps to reduce parasitic effects and improve the circuit characteristics. Each of the N-type transistors is directly formed on the P-type substrate outside the N-type well region.

For example, as shown inFIG.5B, the orthographic projections of the first capacitor electrodes141of the four sub-pixels in each pixel unit group on the base substrate is outside the second region402, and surrounds the second region402. For example, the second region402is rectangular, the orthographic projection of the first capacitor electrode141of each sub-pixel on the base substrate is around a corner of the rectangle; for example, each first capacitor electrode141comprises a concave structure, and an outline of the concave structure is L-shaped, the corner of the rectangle stretches into the orthographic projection of the concave structure and matches the L-shaped outline.

As shown inFIG.5B, patterns of the polysilicon layers in the two sub-pixels adjacent in the first direction D1are symmetrical about a symmetry axis along the second direction D2; and patterns of the polysilicon layers in the two sub-pixels adjacent in the second direction D2are symmetrical about a symmetry axis along the first direction D1; that is, the pattern of the polysilicon layer is a symmetrical pattern. For example, as shown in FIG.5B, the resistance devices of sub-pixels adjacent in the first direction are symmetrical about a symmetry axis along the second direction, and the resistance devices of sub-pixels adjacent in the second direction are symmetrical about a symmetry axis along the first direction. For example, the first capacitor electrodes of sub-pixels adjacent in the first direction are symmetrical about a symmetry axis along the second direction, and the first capacitor electrodes of sub-pixels adjacent in the second direction are symmetrical about a symmetry axis along the first direction.

For example, the gate electrodes of the first data writing transistor P1of two sub-pixels adjacent in the first direction D1are symmetrical about a symmetry axis along the second direction, and the gate electrodes of the second data writing transistor N1of the two sub-pixels adjacent in the first direction D1are symmetrical about a symmetry axis along the second direction. For example, the gate electrodes of the first data writing transistor P1of two sub-pixels adjacent in the first direction D1are integrally formed, and the gate electrodes of the second data writing transistor N1of the two sub-pixels adjacent in the first direction D1are integrally formed.

For example, the gate electrodes of the first data writing transistor P1of two sub-pixels adjacent in the second direction D2are symmetrical about a symmetry axis along the first direction, and the gate electrodes of the second data writing transistor N1of the two sub-pixels adjacent in the second direction D2are symmetrical about a symmetry axis along the first direction.

For example, the first insulating layer is formed on the base substrate by a thermal oxidation method. For example, a material of the first insulating layer is silicon nitride, oxide or oxynitride.

For example, a polysilicon material layer is formed on the first insulating layer by a chemical vapor deposition process (PVD), then a photolithography process is performed on the polysilicon material layer to form the polysilicon layer102.

FIG.5Cshows a doping window region103of the base substrate (left picture), and also shows the doping window region on the substrate structure as shown inFIG.5B(right picture). For example, the doping is heavy doping, to form contact hole regions for electrical connection in the base substrate. For example, the doping window region includes the source region and the drain region of each of the transistors. For example, the doping window region also includes the contact hole regions of the substrate and the contact hole regions of the resistance device130, for example, including the contact hole regions400a,400b,411a,411b,145a,145b,133,134shown inFIG.4B. For example, since the gate electrode of the transistor is formed of polysilicon material, the polysilicon gate electrode also needs to be doped. In a case that the doping is performed, a barrier layer needs to be formed to cover the non-doped region, and only the corresponding doping window region and amorphous silicon areas are exposed.

It should be noted thatFIG.5Conly illustrates each doping window region, in a case that an actual doping process is performed, a corresponding barrier layer/mask layer can be arranged to expose both the corresponding doping window region and the polysilicon region for doping. For example, a material of the barrier layer/mask layer may be photoresist or an oxide material.

As shown inFIG.5D, a barrier layer135is formed corresponding to the resistance device130. In order to protect a resistance of the resistance device130, the resistance device130needs to be shielded during the doping process to prevent the resistance device130from being damaged due to the doping. The barrier layer135covers the main body of the resistance device130and only exposes the contact hole regions133and134at both ends of the resistance device130.

For example, the barrier layer135may be made of silicon nitride, oxide or oxynitride, or a photoresist material. After finishing the doping process, the barrier layer135may remain in the display substrate, or may be removed.

In other examples, the barrier layer135of the resistance device130can also be formed together with barrier layers/mask layers in other regions during doping, which are not limited in the embodiments of the present disclosure.

For example, during the doping process, the N-type doping and the P-type doping need to be performed separately, for example, to form both the source region and the drain region of the N-type transistor and both the source region and the drain region of the P-type transistor. In a case that the N-type doping process is performed, the barrier layer needs to be formed to shield the region where the N-type doping is not to be performed; in a case that the P-type doping process is performed, a barrier layer needs to be formed to shield the region where the P-type doping is not to be performed.

FIG.5Eshows the N-type doped region SN and the P-type doped region SP with different shading patterns (left picture), and also shows the N-type doped region SN and the P-type doped region SP on the substrate shown inFIG.5D(right picture). The N-type doped region SN and the P-type doped region SP are also shown inFIG.4B, and can be referred to together.

For example, performing an N-type doping process includes forming a barrier layer to cover the P-type doped region SP, and to cover the region of the N-type doped region SN except for the doping window region and the polysilicon region, and only the doping window region and the polysilicon region in the N-type doped region SN are retained, that is, the SN region overlaps with the doping window region103and the polysilicon region shown inFIG.5C; then an N-type doping process is performed. Referring toFIG.4B, the gate electrodes, the first electrodes and the second electrodes of the transistors N1to N3, and the contact hole regions411a,411b,145a,145bcan be formed through the N-type doping process. The N-type doping process may be, for example, an ion implantation process, and the doping element may be, for example, boron element.

For example, performing a P-type doping process includes forming a barrier layer to cover the N-type doped region SN, and to cover the P-type doped region SP except for the doping window region and the polysilicon region, and only the doping window region and the polysilicon region in the P-type doped region SP are retained, that is, the SP region overlaps with the doping window region103and the polysilicon region shown inFIG.5C; then the P-type doping process is performed. Referring to4B, the gate electrode, the first electrode and the second electrode of the transistor P1, and the contact holes400a,400b,133, and134can be formed through the P-type doping process. The P-type doping process may be, for example, an ion implantation process, and the doping element may be, for example, phosphorus element.

In the doping process, for example, an ion implantation process is applied, and the polysilicon pattern can serve as a mask, so that an implantation of ions into the silicon-based substrate happens on both sides of the polysilicon, thereby forming the first electrode and the second electrode of each of the transistors, and realizing a self-alignment. In addition, a resistivity of the polysilicon with original high resistance is reduced through the doping process, the gate electrode of each transistor and the first capacitor electrode can be formed. Therefore, using the polysilicon material the material of the resistance device and the gate electrode has multiple beneficial effects, and the process cost is reduced.

In this way, the structure of the display substrate shown inFIG.4Ais formed, which includes each of the transistors P1, N1to N3, the resistance device130and the storage capacitor Cst.

For example, corresponding transistors, the resistance devices, and the storage capacitors Cst in two sub-pixels adjacent in the first direction D1are respectively symmetrical about a symmetry axis along the second direction D2; corresponding transistors, resistance devices, and storage capacitors Cst in two sub-pixels in adjacent the second direction D2are respectively symmetrical about a symmetry axis along the first direction D1.

It should be noted that, in the embodiment, the storage capacitor Cst is a capacitor formed by a field effect, after a voltage is applied to the first capacitor electrode141, inversion charges are generated in a region of the base substrate101under the first capacitor electrode141, rendering a bottom electrode plate of the storage capacitor Cst, i. e. the second capacitor electrode142conductive.

In other embodiments, a conducting treatment (for example, a doping treatment) may be performed in advance on the region of the base substrate101located below the first capacitor electrode141to form the second capacitor electrode142. The embodiments of the present disclosure are not limited thereto.

The second insulating layer202, the first conductive layer301, the third insulating layer203, the second conductive layer302, the fourth insulating layer204, the third conductive layer303, the fifth insulating layer205, and the fourth conductive layer304are sequentially formed on the substrate shown inFIG.4A, and the display substrate shown inFIG.3Ais formed.

FIGS.6A and6Brespectively show a pattern of the first conductive layer301and a situation where the first conductive layer301is arranged on the substrate structure shown inFIG.4A,FIG.6Cshows a cross-sectional schematic diagram ofFIG.6Balong a section line IV-IV′;FIG.6Balso shows via holes in the second insulating layer202, and the via holes correspond to the contact regions inFIG.4Bin a one-to-one correspondence and are used to electrically connect each of the contact hole regions with the pattern in the first conductive layer301. For clarity, only two rows and six columns of sub-pixels are shown in the figure, and a dotted frame is used to show a region of one sub-pixel100; in addition,FIG.6Balso correspondingly shows a position of the section line I-I′ inFIG.3A.

As shown inFIG.6A, patterns of the first conductive layers in two sub-pixels adjacent in the first direction D1are symmetrical about a symmetry axis along the second direction D2; patterns of the first conductive layers in two sub-pixels adjacent in the second direction D2are symmetrical about a symmetry axis along the first direction D1. The pattern of the first conductive layer will be exemplarily described below by taking one sub-pixel as an example.

As shown inFIG.6A, the first conductive layer301includes a connection electrode313(an example of the first connection electrode of the present disclosure), and the connection electrode313is used to electrically connect the first terminal131of the resistance device130with the second electrode152of the driving sub-circuit112.

For example, with reference toFIG.6B, a first end of the connection electrode313is electrically connected with the first terminal131of the resistance device130through a via hole225(an example of the first via hole of the present disclosure) in the second insulating layer202; a second end of the connection electrode313includes a first branch331and a second branch332, combining withFIG.3B, the first branch331is electrically connected with the first electrode151of the driving transistor N2through the via hole226a(an example of the second via hole of the present disclosure) in the second insulating layer202, and the second branch332is electrically connected with the first electrode181of the bias transistor N3through a via hole226bin the second insulating layer202.

For example, as shown inFIG.6B, in the second direction D2, the via hole225and the via hole226aare respectively located on opposite sides of the first capacitor electrode141; that is, an orthographic projection of the connection electrode313on the base substrate101crosses over an orthographic projection of the first capacitor electrode141on the base substrate101in the second direction D2.

For example, a number of both the via hole226aand the via hole226bmay be at least two, to reduce the contact resistance.

For example, with referring toFIGS.6A and6B, the first conductive layer301further includes a connection electrode314, the connection electrode314is electrically connected with the second terminal132of the resistance device130through the via hole229in the second insulating layer202, and the connection electrode314is configured to be electrically connected with the first electrode121of the light-emitting element120.

For example, the connection electrode314is L-shaped, one branch of the connection electrode314is electrically connected with the second terminal132of the resistance device130, and the other branch is configured to be electrically connected with the first electrode121of the light-emitting element120.

For example, as shown inFIG.6BandFIG.6C, the first conductive layer301also includes a third capacitor electrode315, the third capacitor electrode315overlaps with the first capacitor electrode141in a direction perpendicular to the base substrate. The third capacitor electrode315is on a side of the first capacitor electrode141away from the second capacitor electrode142, and is configured to be electrically connected with the second capacitor electrode142; that is, in the direction perpendicular to the base substrate, the second capacitor electrode142and the third capacitor electrode315are located on two sides of the first capacitor electrode141respectively, and are electrically connected with each other, so that a structure of parallel capacitors is formed, and the capacitance value of the storage capacitor Cst is increased.

For example, as shown inFIG.6BandFIG.6C, the third capacitor electrode315comprises a first portion315aand a second portion315b, and the first portion315aand the second portion315bare spaced apart from each other in the first direction D1. For example, the first portion315ais electrically connected with the contact hole region145bthrough a via hole228in the second insulating layer202, so as to be electrically connected with the second capacitor electrode142; the second portion315bis electrically connected with the contact hole region145athrough a via hole227in the second insulating layer202, so as to be electrically connected with the second capacitor electrode142.

For example, the first portion315aand the second portion315bof the third capacitor electrode315are located on two sides of the connection electrode313in the first direction D1, and are respectively spaced apart from the connection electrode313.

For example, the third capacitor electrodes of two sub-pixels adjacent in the first direction D1are about a symmetry axis along the second direction D2; and the third capacitor electrodes of two sub-pixels adjacent in the second direction D1are about a symmetry axis along the first direction D1.

For example, as shown inFIG.6B, the first portions315aor the second portions315bof the third capacitor electrodes of two sub-pixels adjacent in the first direction D1are in an integral structure.

For example, as shown inFIG.6B, for each pixel unit group420, the first portions315aof the third capacitor electrodes of two sub-pixels adjacent in the first direction D1are connected with each other as an integral structure.

For example, as shown inFIG.6B, the second portion315bof the third capacitor electrode315of a sub-pixel in each pixel unit group420and the second portion315bof the third capacitor electrode315of a sub-pixel, which is adjacent to the sub-pixel, in a pixel unit group adjacent to the each pixel unit group420are connected as an integral structure.

For example, as shown inFIG.6A, adjacent third capacitor electrodes315in two sub-pixels adjacent in the first direction D1may be integrally formed to receive the same second power voltage VSS, and adjacent third capacitor electrodes315in two sub-pixels adjacent in the first direction D1may be integrally formed to receive the same second power voltage VSS.

For example, at least two via holes227and228may be arranged respectively to reduce the contact resistance; for example, the at least two via holes227are arranged along the second direction D2, and the at least two via holes228are arranged along the second direction D2.

For example, the first conductive layer301further includes a connection electrode317(an example of the second connection electrode of the present disclosure), and the connection electrode317is used to electrically connect the second terminal of the data writing sub-circuit with the first terminal of the storage sub-circuit, that is, electrically connecting the second electrode161of the first data writing transistor P1, the second electrode171of the second data writing transistor N1, and the first capacitor electrode141.

With referring toFIG.6AandFIG.6B, the connection electrode317includes three ends, for example, a T-shaped structure. With referring toFIG.3B, the first end of the connection electrode317is electrically connected with the second electrode of the first data writing transistor P1through a via hole261ain the second insulating layer202, the second end of the connection electrode317is electrically connected with the second electrode of the second data writing transistor N1through a via hole261bin the second insulating layer202, and the third end of the connection electrode317is electrically connected with the first capacitor electrode141through a via hole261cin the second insulating layer202.

For example, as shown inFIG.6B, in the second direction D2, the third end of the connection electrode314at least partially overlaps with the connection electrode317. This arrangement makes the pixel layout more compact, so that the space utilization rate of the display substrate is improved, and the resolution of the display substrate is improved.

With referring toFIG.6AandFIG.6B, the first conductive layer301further includes a first scan line connection portion311and a second scan line connection portion312, and the first scan line connection portion311is configured to be electrically connected with the first scan line so that the gate electrode of the first data writing transistor P1receives the first control signal SEL. The second scan line connection portion312is configured to be electrically connected with the second scan line so that the gate electrode of the second data writing transistor N1receives the first control signal SEL_B.

For example, the first scan line connection portion311is electrically connected with the gate electrode of the first data writing transistor P1through a via hole221in the second insulating layer202, and the second scan line connection portion312is electrically connected with the gate electrode of the second data writing transistor N1through a via hole222in the second insulating layer202.

For example, as shown inFIG.6A, sub-pixels adjacent in the first direction D1share a first scan line connection portion311or a second scan line connection portion312.

For the specific description of the first scan line connection portion and the second scan line connection portion, the description ofFIGS.10A to10Bbelow can be referred to.

As shown inFIG.6A, the first conductive layer301further includes a data line connection portion245, and the data line connection portion245is configured to be electrically connected with the data line, so that the first electrode of the first data writing transistor P1and the first electrode of the second data writing transistor N1receive the data signal Vd transmitted by the data line.

As shown inFIG.6B, the data line connection portion245is electrically connected with the first electrode161of the first data writing transistor P1through a via hole223in the second insulating layer202, and the data line connection portion245is electrically connected with the first electrode171of the second data writing transistor N1through a via hole224in the second insulating layer202.

For example, as shown inFIG.6A, a plurality of data line connection portions245are arranged at intervals in the first direction D1, for example, located at a boundary of two sub-pixel rows. For example, two sub-pixels adjacent in the second direction D2share one data line connection portion245.

For the specific description of the data line connection portion, the description of the second data line connection portion inFIGS.8A to8Dbelow can be referred to.

Referring toFIGS.6A and6B, the first conductive layer301further includes a connection electrode318, and the connection electrode318is electrically connected with the first electrode of the driving transistor N2through a via hole230in the second insulating layer202.

Referring toFIGS.4A and6B, the first conductive layer301further includes connection electrodes319a,319b,319c, these connection electrodes are all arranged for biasing the substrates of the transistors, for example, used for connecting the N-type substrate to a first power voltage terminal to receive the first power voltage VDD (high voltage), or used for connecting the P-type substrate to a second power voltage terminal to receive the second power supply voltage VSS (low voltage), as a result, parasitic effects such as the substrate bias effect can be avoided, and the stability of the circuit can be improved.

With referring toFIG.4B, the connection electrodes319aand319bare respectively electrically connected with the contact hole regions411aand411bin the second region (N-well region)402of the base substrate101through via holes262aand262bin the second insulating layer202, the connection electrodes319aand319bare configured to be electrically connected with the first voltage terminal VDD to bias the N-type substrate of the first data writing transistor P1. The connection electrode319cis electrically connected with the contact hole region400ain the base substrate101through a via hole262cin the second insulating layer202, and the connection electrode319cis configured to be electrically connected with the second voltage terminal VSS to bias the P-type substrate where the second data writing transistor N1is located.

With referring toFIGS.6A to6B, the first conductive layer301further includes a bias voltage line250, the bias voltage line250is extended along the first direction D1, and is electrically connected with the gate electrode of the bias transistor N3through a via hole263in the second insulating layer202, to provide the second common voltage Vcom2.

With reference toFIGS.4B and6A to6B, the first conductive layer301further includes a power line260, the power line260is extended along the first direction D1and is used for transmitting the second power voltage VSS. The power line260is electrically connected with the first electrode of the bias transistor N3through a via hole264ain the second insulating layer202to provide the second power voltage VSS, and is electrically connected with a contact hole region400bin the base substrate101through a via hole264bin the second insulating layer202to bias the P-type substrate where the second data writing transistor N1is located.

FIG.7Ashows a schematic diagram of the second conductive layer302,FIG.7Bshows the second conductive layer302on the basis of the first conductive layer301,FIG.7Bfurther shows the via hole in the third insulating layer203, and the via hole in the third insulating layer203is used to connect the pattern in the first conductive layer301and the pattern in the second conductive layer302. For clarity, only four rows and six columns of sub-pixels are shown in the figure, a dividing line of two sub-pixel rows is further shown by a dotted line; in addition,FIG.7Balso correspondingly shows a position of the section line I-I′ inFIG.3A.

As shown inFIG.7A, patterns of second conductive layers in two sub-pixels adjacent in the first direction D1are symmetrical about a symmetry axis along the second direction D2; and patterns of second conductive layers in two sub-pixels adjacent in the second direction D2are symmetrical about a symmetry axis along the first direction D1. The patterns of the second conductive layers will be exemplarily described below by taking one sub-pixel as an example.

As shown inFIG.7A, the second conductive layer302includes power lines270a,270b,280a, and280bextended along the first direction D1, the power lines270aand270bare used to transmit the second power voltage VSS, and the power lines280aand280bare used to transmit the first power voltage VDD. The power lines270a,280a,270b, and280bare alternately arranged one by one in the second direction D2.

With reference toFIGS.3B,7A, and7B, the power line270ais electrically connected with the power line260in the first conductive layer301through a plurality of via holes235in the third insulating layer203, so that a parallel structure is formed, the resistance of the wiring is effectively reduced; the plurality of via holes235are arranged along the first direction D1. For example, the power line270bis electrically connected with the third capacitor electrode315through via holes236in the third insulating layer203to provide the second power voltage VSS; for example, the plurality of via holes236are arranged along the second direction D2. For example, the power line270bis also electrically connected with the third capacitor electrode315(315b) through via holes267in the third insulating layer203to provide the second power voltage VSS; for example, the plurality of via holes267are arranged along the second direction D2.

For example, in the second direction D2, a width of the power line270bis greater than a width of the power line270a, this is because the first portion and the second portion of the third capacitor electrode315that is electrically connected with the power line270bboth have a larger area, setting the power line270bto have a larger width can facilitate the formation of a plurality of connection holes236and267with the third capacitor electrode315, so that the contact resistance is effectively reduced.

With reference toFIGS.7A and7B, the power line280ais electrically connected with the connection electrode318in the first conductive layer301through a via hole237in the third insulating layer203, so that the power line280ais connected with the first electrode of the driving transistor N2to provide the first power supply voltage VDD. The power line280bis electrically connected with the connection electrode319ain the first conductive layer301through a via hole238in the third insulating layer203, so that the second region (N-well region)402in the base substrate101is biased with a high voltage; for example, the plurality of via holes238are arranged along the second direction D2.

For example, in the second direction D2, a width of the power line280bis greater than a width of the power line280a, this is because the connection electrode319aelectrically connected to the power line280bhas a larger size in the second direction D2, setting the power line280bto have a larger width can facilitate the formation of a plurality of connection holes238between the power line280band the connection electrode319a, so that the contact region with the connection electrode319ais increased, and the contact resistance is effectively reduced.

For example, the second conductive layer302further includes a plurality of first scan lines210and a plurality of second scan lines220extended along the first direction D1. For example, the scan line11shown inFIG.1Amay be the first scan line210or the second scan line220.

With reference toFIG.6AandFIG.6B, the first scan line210is electrically connected with the first scan line connection portion311through a via hole231in the third insulating layer203, and the second scan line220is electrically connected with the second scan line connection portion312through a via hole232in the third insulating layer203.

For the specific description of the first scan line and the second scan line, the description ofFIGS.10A-10Bbelow may be referred to.

For example, with referring toFIG.3B,FIG.7AandFIG.7B, the second conductive layer302further includes a connection electrode323, and the connection electrode323is electrically connected with the connection electrode314in the first conductive layer301through a via hole239in the third insulating layer203, so that the connection electrode323is connected to the second terminal132of the resistance device130. The connection electrode323is configured to be electrically connected with the first electrode121of the light-emitting element120. For example, the number of the via hole239is at least two.

For example, with referring toFIG.7AandFIG.7B, the second conductive layer302further includes a connection electrode324, and the connection electrode324is electrically connected with the connection electrode319bin the first conductive layer301through a via hole265in the third insulating layer203, so that the connection electrode324is electrically connected with the contact hole region411bin the second region (N-well region)402in the base substrate101.

For example, with referring toFIG.7AandFIG.7B, the second conductive layer302further includes a connection electrode325, the connection electrode325is electrically connected with the connection electrode319cin the first conductive layer301through a via hole266in the third insulating layer203, so that the connection electrode325is electrically connected with the contact hole region400ain the base substrate101.

For example, the connection electrode325is in a cross-shaped structure. For example, the connection electrodes324and the connection electrodes325are alternately distributed in the first direction D1, and are located at a boundary of two sub-pixel rows.

For example, as shown inFIG.7A, the second conductive layer302further includes a data line connection portion244. With referring toFIG.7B, the data line connection portion244is electrically connected with the data line connection portion245in the first conductive layer301through a via hole233.

For example, as shown inFIG.7A, a plurality of data line connection portions244are arranged at intervals in the first direction D1, and a connection electrode324or a connection electrode325is provided between every two adjacent data line connection portions244.

For example, the data line connection portion244is located at a boundary between two sub-pixel rows. For example, two sub-pixels adjacent in the second direction D2share one data line connection portion244.

For example, with referring toFIGS.7A and7B, in the second direction D2, the data line connection portions244located in each column of sub-pixels are alternately located on two sides of the data line connection portions245, and are electrically connected with the first end and the second end of the data line connection portions245through via holes233and234, respectively, which is to connect the data line connection portions245to different data lines.

For a specific description of the data line connection portion, the description of the first data line connection portion inFIGS.11A to11Dbelow may be referred to.

FIG.8Ashows a schematic diagram of the third conductive layer303,FIG.8Bshows the third conductive layer303on the basis of the second conductive layer302,FIG.8Balso shows the via holes in the fourth insulating layer204, and the via holes in the fourth insulating layer204is used to connect the pattern in the second conductive layer302with the pattern in the third conductive layer303. For clarity, the figures only show the conductive patterns corresponding to the sub-pixels in four rows and six columns, and a dividing line of two rows of sub-pixels is shown inFIG.8Awith a dashed line; in addition,FIG.8Balso correspondingly shows the position of the section line I-I′ inFIG.3A.

For example, the third conductive layer303includes a plurality of data lines extended along the second direction D2, and the data line is configured to be connected with the first terminal of the data writing sub-circuit in the sub-pixel to provide the data signal Vd. For example, as shown inFIG.8A, the plurality of data lines include a plurality of first data lines241and a plurality of second data lines242, the first data lines241and the second data lines242are alternately arranged one by one along the first direction D1. For example, the data line12shown inFIG.1Amay be the first data line241or the second data line242.

For example, the data line is divided into a plurality of data line groups, each of the data line groups includes a first data line241and a second data line242. For example, each sub-pixel column is correspondingly connected with a data line group, that is, with a first data line241and a second data line242; that is, one column of sub-pixels is driven by two data lines. This helps to reduce the load on each data line, so that the driving ability of the data line is improved, the signal delay is reduced, and the display effect is improved.

Referring toFIG.8B, the first data line241is electrically connected with the data line connection portion244which is between the first row of sub-pixels and the second row of sub-pixels and in the second conductive layer302shown inFIG.7Bthrough a via hole403in the fourth insulating layer204, so as to provide the data signal to the first and second rows of sub-pixels; the second data line242is electrically connected with the data line connection portion244which is between the third row of sub-pixels and the fourth row of sub-pixels and in the second conductive layer302shown inFIG.7Bthrough a via hole404in the fourth insulating layer204, so as to provide the data signal to the third and fourth rows of sub-pixels.

For the specific description of the first data line and the second data line, the descriptions inFIGS.11A-11Dbelow may be referred to. For the convenience of comparison,FIG.8Bshows the positions corresponding to the section lines II-II′ and III-III′ inFIG.11B.

For example, the third conductive layer303includes power lines330and340extended along the second direction D2. The power line330is configured to transmit the first power voltage VDD, and the power line340is configured to transmit the second power voltage VSS. As shown inFIG.8A, the power line330and the power line340are alternately arranged one by one in the first direction D1.

Referring toFIG.8B, the power line330is electrically connected with the power lines280aand280bin the second conductive layer302through via holes405and406in the fourth insulating layer204, respectively, so that a meshed power line structure for transmitting the first power voltage is formed. This structure helps to reduce the resistance on the power line, so that the voltage drop on the power line is reduced, which helps to evenly deliver the first power voltage VDD to each of the sub-pixels of the display substrate. The power line330is also electrically connected with the connection electrode324(referring toFIG.7A) in the second conductive layer302through a via hole407in the fourth insulating layer, so that the power line330is electrically connected with the contact hole region411bin the second region402(N-well region) in the base substrate101, to bias the N-type substrate where the first data writing transistor P1and the resistance device130are located.

Referring toFIG.8B, the power line340is electrically connected with the power lines270aand270bin the second conductive layer302through a via hole408and a via hole409in the fourth insulating layer204, respectively, so that a meshed power line structure for transmitting the second power supply voltage is formed. The meshed power line structure helps to reduce the resistance on the power line, so that the voltage rise on the power line is reduced, which helps to evenly deliver the second power voltage VSS to each of the sub-pixels of the display substrate. The power line340is also electrically connected with the connection electrode325(referring toFIGS.3B and6A) in the second conductive layer302through a via hole412in the fourth insulating layer, so that the power line340is electrically connected with the contact hole region400ain the base substrate101, to bias the P-type substrate where the transistors N1-N3are located.

As shown inFIG.8A, the third conductive layer303further includes a connection electrode333, the connection electrode333is located between the first data line241and the second data line242in a data line group. As shown in conjunction withFIG.7B, the connection electrode333is electrically connected with the power line270bin the second conductive layer through a via hole413in the fourth insulating layer, for example, the number of the via413is at least two, so that the connection electrode333can fully contact with the power line270bto reduce the contact resistance. The parallel connection electrode333arranged on the power line270bcan help to reduce the resistance on the power line270b, so that the voltage rise on the power line is reduced, which helps to evenly deliver the second power voltage VSS to each of the sub-pixels of the display substrate.

As shown inFIG.3B,FIG.8AandFIG.8B, the third conductive layer303further includes a connection electrode334, the connection electrode334is electrically connected with the connection electrode323in the second conductive layer302through a via hole414in the fourth insulating layer, so that the connection electrode334is connected with a second terminal132of the resistance device130. The connection electrode334is configured to be electrically connected with the first electrode121of the light-emitting element120. For example, the number of the via holes414is at least two.

As shown in conjunction withFIG.8AandFIG.8B, the third conductive layer303further includes a shielding electrode341, for example, the shielding electrode341is extended along the second direction D2, the shielding electrode341is located between a first data line241and a second data line242of a data line group, for example, the first data line241and the second data line242are symmetrically arranged on both sides of the shielding electrode341. The shielding electrode341is arranged between the two data lines to play a role of shielding and prevent signals in the two data lines from interfering with each other. For example, the shielding electrode341is configured to receive a constant voltage to improve the shielding ability. In this embodiment, the shielding electrode341is configured to receive the second power voltage VSS.

For example, the display substrate comprises a plurality of shielding electrodes341, the plurality of shielding electrodes341are arranged in a one-to-one correspondence with the plurality of data line groups, and each shielding electrode is between the first data line and the second data line of the corresponding data line group.

As shown inFIG.8A, the connection electrode333, the connection electrode334, and the shielding electrode341are arranged in the second direction D2, and are located between the first data line241and the second data line242; the connection electrode333, the connection electrode334, and the shielding electrode341constitute a shielding wall, which plays a role of shielding in an entire extension range of the first data line241and the second data line242, to prevent the signals in the two data lines from interfering with each other.

For example, as shown inFIG.8A, the connection electrode333and the shielding electrode341are located on two sides of the connection electrode334respectively, and are spaced apart from the connection electrode334. The connection electrode333is provided with a protruding portion333aat one end close to the connection electrode334, the protruding portion333ais in an L shape, a first branch of the protruding portion333ais extended along the first direction D1, and is connected with the main body of the connection electrode333, a second branch of the protruding portion333ais extended along the second direction D2and the direction approaching the connection electrode334, the second branch is overlapped with a gap between the connection electrode333and the connection electrode334in the first direction D1, so that the shielding effect is improved, and the signal crosstalk between the two data lines is further avoided.

Similarly, the shielding electrode341is provided with an L-shaped protruding portion341aat one end close to the connection electrode334, and the L-shaped protruding portion341ais used for further shielding the gap between the shielding electrode341and the connection electrode334, to improve the shielding effect.

In this way, the shielding wall achieves complete shielding in the second direction D2, and the first data line241and the second data line242have no area directly facing each other in the first direction D1, so that a better signal shielding effect is achieved, a better stability of the display data is provided, and the display effect is improved.

FIG.9Ashows a schematic diagram of the fourth conductive layer304, FIG.9B shows the fourth conductive layer304on the basis of the third conductive layer303, andFIG.9Balso shows via holes in the fifth insulating layer205, the via holes in the fifth insulating layer205are used to connect patterns in the third conductive layer303with patterns in the fourth conductive layer304. For clarity, only four rows and six columns of sub-pixels are shown in the figure, a dividing line of two rows of sub-pixels is shown by a dotted line; in addition,FIG.9Balso correspondingly shows the position of the section line I-I′ inFIG.3A.

For example, the fourth conductive layer304includes power lines350and360extended along the second direction D2. The first power line350is used to transmit the first power voltage VDD, and the power line360is used to transmit the second power voltage VSS. As shown inFIG.9A, the power lines350and the power lines360are alternately arranged one by one in the first direction D1.

For example, the plurality of power lines350and the plurality of power lines330are arranged in one-to-one correspondence, and the plurality of power lines360and the plurality of power lines340are arranged in one-to-one correspondence; in a direction perpendicular to the base substrate101, each power line350and the corresponding power line330overlap with each other and are electrically connected with each other (for example, in parallel), each power line360and the corresponding power line340are overlapped and are electrically connected with each other (for example, in parallel). As a result, the resistance on the power line is reduced, and the display uniformity is improved.

Referring toFIG.9B, the power line350is electrically connected with the corresponding power line330through a via hole251in the fifth insulating layer205, and the power line360is electrically connected with the corresponding power line340through a via hole252in the fifth insulating layer. For example, the numbers of the via holes251and252are at least two respectively.

With reference toFIGS.9A and9B, the fourth conductive layer304further includes a connection electrode342, the connection electrode342is electrically connected with the connection electrode333in the third conductive layer303through a via hole253in the fifth insulating layer, for example, the number of via holes253is at least two, so that the connection electrode342can fully contact the connection electrode333to reduce the contact resistance. Providing the connection electrode342helps to further reduce the resistance on the power line270b, so that the voltage rise on the power line is reduced, which helps to evenly deliver the second power supply voltage VSS to each of the sub-pixels of the display substrate.

CombiningFIG.3B,FIG.9AwithFIG.9B, the fourth conductive layer304further includes a connection electrode343, the connection electrode343is electrically connected with the connection electrode334in the third conductive layer303through a via hole254in the fifth insulating layer, so that the connection electrode343is connected to a second terminal132of the resistance device130. The connection electrode343is used for electrical connection with a first electrode121of the light-emitting element120. For example, the number of the via holes254is at least two.

CombiningFIG.9AwithFIG.9B, the fourth conductive layer304further includes a connection electrode344, and the connection electrode344is electrically connected with the shielding electrode341in the third conductive layer303through a via hole255in the fifth insulating layer. As shown inFIG.9A, the fourth conductive layer304further includes a connection portion345, which connects the connection electrode344to the power line360directly adjacent to the connection electrode344.

For example, as shown inFIG.9A, the connection electrodes344located on two sides of the power line360are symmetrically arranged about the power line360, the power line360, the connection electrodes344on two sides of the power line360, and the corresponding connection portions345of the connection electrodes are connected with each other as an integral structure. In this way, the power line360can provide the second power voltage VSS to the shielding electrode341, to improve the shielding ability of the shielding electrode.

For example, each via hole may be additionally filled with a conductive material (such as tungsten) to conduct electricity.

FIG.9Balso shows a contact hole region256of the connection electrode343, and the contact hole region256is used to electrically connect with the first electrode121of the light-emitting element120.

It should be noted that along the section line I-I′, a part of the connection electrode343in the contact hole region256and a part of the connection electrode343corresponding to the via hole254are not continuous (as shown in the region F inFIG.9B); however, for the convenience of description, the contact hole region256and the via hole254are shown on the continuous connection electrode343in the cross-sectional schematic diagram shown inFIG.3B, which is consistent with the actual situation. For example, as shown inFIG.3B, the display substrate10further includes a sixth insulating layer206, and a via hole257is formed in the sixth insulating layer206corresponding to a contact hole region256of the connection electrode343, the via hole257is filled with a conductive material (such as tungsten), then a polishing process (such as chemical mechanical polishing) is performed to form a flat surface, which is used to form the light-emitting element120.

For example, the number of the via hole257is at least two.

For example, as shown inFIG.3B, the numbers of the contact hole regions for electrical connection on the connection electrodes314,323,334, and343connected with the first electrode121of the light-emitting element120are at least two, respectively, the contact resistance between the connection electrodes is reduced, in turn, the connection resistance between the resistance device130and the first electrode121of the light-emitting element120is reduced, so that the voltage drop on a transmission path of the data signal from the resistance device130to the first electrode121is reduced, the problems such as color shift and display unevenness caused by the loss of anode potential due to the voltage drop are alleviated, and the display effect is improved.

For example, as shown inFIG.3B, in the direction perpendicular to the base substrate101, the via holes257,254, and414corresponding to the first electrode121of the light-emitting element120do not overlap with each other. In the direction perpendicular to the substrate, stacking of the via holes leads to poor connection, disconnection or unevenness at the positions of the via holes, and this arrangement improves the electrical connection quality of the first electrode121of the light-emitting element120, and improves the display effect.

As shown inFIG.3B, the light-emitting element120includes a first electrode121, a light-emitting layer123, and a second electrode122sequentially disposed on the sixth insulating layer206. For example, the first electrode121and the second electrode122are the anode and the cathode of the OLED, respectively. For example, a plurality of first electrodes121are arranged at intervals in a same layer, and correspond to the plurality of sub-pixels in a one-to-one correspondence. For example, the second electrode122is a common electrode, and is provided in an entire surface of the display substrate10.

For example, as shown inFIG.3B, the display substrate further includes a first encapsulation layer124, a color filter layer125, and a cover plate126on a side of the light-emitting element120away from the base substrate101.

For example, the first encapsulation layer124is configured to seal the light-emitting element to prevent external moisture and oxygen from penetrating into the light-emitting element and the pixel circuit and from causing damage to the device. For example, the encapsulation layer124includes an organic thin film or a structure in which an organic thin film and an inorganic thin film are alternately stacked. For example, a water-absorbing layer may be arranged between the encapsulation layer124and the light-emitting element, and is configured to absorb residual water vapor or sol in the pre-production process of the light-emitting element. The cover plate126is, for example, a glass cover plate.

For example, as shown inFIG.3B, the display substrate may further include a second encapsulation layer127located between the color filter layer125and the cover plate126, and the second encapsulation layer127can protect the color filter layer125.

For example, the light-emitting element120is configured to emit white light, and combines the color filter layer125to realize a full-color display.

In other examples, the light-emitting element120is configured to emit light of three primary colors, in this situation, the color filter layer125is not necessary. The embodiment of the present disclosure does not limit the manner in which the display substrate10realizes full-color display.

The following Table A exemplarily shows thickness ranges and example values of the first insulating layer to the sixth insulating layer, Table B exemplarily shows thickness ranges and example values of the first conductive layer to the fourth conductive layer, Table C exemplarily shows sizes and example values of the via hole VIA2 in the second insulating layer, the via hole VIA3 in the third insulating layer, the via hole VIA4 in the fourth insulating layer, the via hole VIA5 in the fifth insulating layer, and the via hole VIA6 in the sixth insulating layer, and Table D exemplarily shows example values of the channel width, length, and respective width-to-length ratio of each transistor (N1to N4, and P1); however, this is not a limitation to the present disclosure.

TABLE ANumericalExemplaryFilm LayerRange (Å)Value (Å)The first insulating layer 20130~3432The second insulating layer 20210000~1400012000The third insulating layer 2036500~75007000The fourth insulating layer 2046500~75007000The fifth insulating layer 2056500~75007000The sixth insulating layer 2066500~75007000

TABLE BNumericalExemplaryFilm LayerRange (Å)Value (Å)The first conductive layer 2014500~55005000The second conductive layer 2024500~55005000The third conductive layer 2034500~55005000The fourth conductive layer 2044500~55005000

TABLE CVia HoleNumerical Range (um)Exemplary Value (um)VIA20.2-0.30.22VIA30.2-0.30.26VIA40.2-0.30.26VIA50.2-0.30.26VIA60.3-0.40.36

TABLE DTransistorW(um)/L(um)P10.6/0.6N10.6/0.6N21.5/0.6N31.02/0.76

For example, as shown in Table A, among the first insulating layer to the sixth insulating layer, a thickness of the first insulating layer201is the smallest, and the thickness of the second insulating layer202is the greatest. This is because the first insulating layer201includes the gate insulating layer of each transistor, and further includes the dielectric layer104of the storage capacitor Cst, providing the thickness of the first insulating layer201to be smaller can help to improve the gate control ability of the transistor to obtain a larger storage capacitor. In addition, the second insulating layer202serves as a field oxide layer, setting the second insulating layer202thicker helps an electrical isolation between the transistors. For example, the thicknesses of the third insulating layer203, the fourth insulating layer204, the fifth insulating layer205, and the sixth insulating layer206are the same or similar; for example, the thickness of the second insulating layer202is 1.5 to 2 times of the thickness of the third insulating layer203/the fourth insulating layer204/the fifth insulating layer205/the sixth insulating layer206.

For example, a planar shape of each of the via holes can be a rectangular (such as square) or a circular, the size in Table C represents an average side length or an aperture of the rectangle. For example, as shown in Table C, the plurality of via holes in each of the insulating layers are provided with a same size. For example, among the second insulating layer to the sixth insulating layer, the size of the via hole in the sixth insulating layer206is the largest. This is because the sixth insulating layer206is closest to the light-emitting element, during the driving process of the light-emitting element, the current gathers up from the transistor in the bottom layer to the light-emitting element, so that the size of the via hole in the sixth insulating layer206is the largest, so as to transmit a larger convergent current.

For example, a distance between the first data writing transistor P1and the second data writing transistor N1ranges from 0.4 to 0.45 microns, for example, 0.42 microns, which helps to increase the pixel density. As shown inFIG.4B, the distance D0is a distance between the sides of the gate electrode160of the first data writing transistor P1and the gate electrode170of the second data writing transistor N1that are closest to each other.

For example, as shown inFIG.4B, an equivalent length of the resistance device130is 4.4 microns, and an average width of the resistance device130is 0.42 microns.

For example, as shown inFIG.4B, an effective capacitance area of the storage capacitor Cst is 20 square microns, that is, an effective area of the polysilicon layer102for forming the storage capacitor Cst is 20 square microns. For example, an area ratio of the storage capacitor Cst in each sub-pixel is 20%-35%, for example, 27%. The display substrate provided by the embodiments of the present disclosure can effectively increase the area ratio of the storage capacitor through reasonable layout, so that the capacitance value is increased.

For example, a thickness of the polysilicon layer102is 200 nanometers.

At least one embodiment of the present disclosure further provides a pixel structure, and the pixel structure includes a base substrate, a pixel row located on the base substrate, and a first scan line and a second scan line. The pixel row includes a plurality of sub-pixels located on the base substrate and the plurality of sub-pixels are arranged along a first direction; the first scan line and the second scan line extend along the first direction, and each of the sub-pixels includes a pixel circuit, the pixel circuit includes a data writing sub-circuit, a storage sub-circuit, and a driving sub-circuit. The data writing sub-circuit includes a first control electrode, a second control electrode, a first terminal and a second terminal, the first control electrode and the second control electrode of the data writing sub-circuit are respectively configured to receive the first control signal and the second control signal, the first terminal of the data writing sub-circuit is configured to receive a data signal, the second terminal of the data writing circuit is electrically connected with the first terminal of the storage sub-circuit, and is configured to transmit the data signal to the first terminal of the storage sub-circuit in response to the first control signal and the second control signal, the driving sub-circuit includes a control terminal, a first terminal and a second terminal, the control terminal of the driving sub-circuit is electrically connected with the first terminal of the storage sub-circuit, the first terminal of the driving sub-circuit is configured to receive the first power voltage, the second terminal of the driving sub-circuit is used to connect with the light-emitting element, the driving sub-circuit is configured to drive the light-emitting element to emit light in response to the voltage at the first terminal of the storage sub-circuit; the first scan line is electrically connected with the first control electrode of the data writing circuit of the plurality of sub-pixels to provide the first control signal; the second scan line is electrically connected with the second control electrode of the data writing circuit of the plurality of sub-pixels to provide the second control signal; the first scan line and the second scan line are provided with a same resistance, and an area of an orthographic projection of the first scan line on the base substrate is the same as an area of an orthographic projection of the second scan line on the base substrate.

In some examples, for example, the first scan line and the second scan line refer to a portion, which is in the display region, of a wiring that transmits the corresponding control signal from the scan driving circuit to each of the sub-pixels, so that in a case of comparing the resistances and the areas, the portion of the wiring outside the display region can be ignored.

In other examples, for example, the first scan line and the second scan line may also represent all portions of the wiring that transmits the corresponding control signal from the scan driving circuit to each of the sub-pixels and include the portions of the wiring located in the display region and the non-display region, for example, the portion S shown inFIG.1A. For example, the first control signal SEL and the second control signal SEL_B can be output by a same gate driving circuit unit (such as a GOA unit).

With this arrangement, it can be ensured that a resistance-capacitance (RC) load on the first scan line is the same as a resistance-capacitance (RC) load on the second scan line. Referring to1A, in a case that the control signal is transmitted from the scan driving circuit14to each of the sub-pixels, a proportion of the portion of the scan line11(for example, the first scan line and the second scan line) outside the display region (shown by the dashed frame) is relatively small, so that the RC loads of the portions of the scan lines11in the display region are provided to be the same can improve the synchronization of the first control signal SEL and the second control signal SEL_B; with reference toFIG.2C, for example, in a case of entering from the data writing stage1to the light-emitting stage2, the above setting can make a rising edge of the first control signal SEL and a falling edge of the second control signal SEL_B occur at the same time. Therefore, the anti-interference performance of the pixel circuit is improved.

The present disclosure further provides a display substrate including a plurality of pixel structures, the plurality of pixel rows in the plurality of pixel structures are arranged in the second direction, and the first direction intersects the second direction, so that the plurality of sub-pixels of the plurality of pixel rows are a plurality of pixel columns.

It should be noted that the pixel structure provided by the embodiment of the present disclosure can be applied to the display substrate10provided by any one of the foregoing embodiments. However, the pixel structures provided by the embodiments of the present disclosure are not limited to a silicon-based display substrate, for example, may also be applied to a glass substrate or a flexible substrate, in this case, the light-emitting element may also be, for example, in a bottom emission structure or a double-side emission structure.

FIG.10Ashows a schematic diagram of a display substrate provided by at least one embodiment of the present disclosure. For clarity, the figure shows two rows and six columns of sub-pixels, namely only two above pixel structures. Compared with the display substrate illustrated inFIG.3A, the display substrate omits the third conductive layer and the fourth conductive layer. In the following, the arrangement of the first scan line and the second scan line in the display substrate and the pixel structure provided by the embodiment of the present disclosure will be exemplarily described with reference toFIG.10A, but the embodiments of the present disclosure are not limited thereto.

For example, as shown inFIG.10A, each sub-pixel row is respectively correspondingly connected with a first scan line210and a second scan line220, but the present disclosure is not limited thereto.

For example, the display substrate10further includes a plurality of first scan line connection portions311electrically connected with the first scan line210and a plurality of second scan line connection portions312electrically connected with the second scan line220; the first scan line210is electrically connected with the first control electrode (that is, the gate electrode of the first data writing transistor) of the data writing circuit of a row of sub-pixels through the plurality of first scan line connection portions311, and the second scan line220is electrically connected with the second control electrode (that is, the gate electrode of the second data writing transistor) of the data writing circuit of the row of sub-pixels through the plurality of second scan line connection portions312.

For example, the first scan line210and the second scan line220are arranged in a same layer and insulated from each other and are made of a same material.

For example, the plurality of first scan line connection portions311and the plurality of second scan line connection portions312are arranged at intervals in a same layer and are made of a same material, and are located in a different conductive layer from the first scan line210and the second scan line220.

FIG.10Bshows an enlarged schematic diagram of the region E in the dashed frame region inFIG.10A, for clarity, the figure only shows the gate electrodes of the first data writing transistor P1and the second data writing transistor N1, the first scan lines210, and the second scan lines220, and the first scan line connection portions311and the second scan line connection portions312. For the convenience of comparison, the position of the E region is also correspondingly shown inFIG.7B.FIG.10Cshows a cross-sectional schematic diagram ofFIG.10Balong a section line V-V′.

For example, the lengths and the line widths of the first scan line210and the second scan line220are respectively the same.

For example, the first scan line connection portion311and the second scan line connection portion312are alternately arranged in the first direction D1, and the extension direction of the first scan line connection portion311and the extension direction of the second scan line connection portions312are different from the first direction D1. The orthographic projection of the first scan line connection portions311on the base substrate intersects with both the orthographic projections of the first scan line210and the second scan line220on the base substrate. The orthographic projection of the second scan line connection portions312on the base substrate intersect with both the orthographic projections of the first scan line210and the second scan line220on the base substrate. For example, both the first scan line connection portion311and the second scan line connection portion312are linear structures, and extend along the second direction D2.

For example, a sum of areas of orthographic projections of the plurality of first scan line connection portions311on the base substrate is the same as a sum of areas of orthographic projections of the plurality of second scan line connection portions312on the base substrate. Therefore, the parasitic capacitances on the plurality of first scan line connection portions311and the parasitic capacitances on the plurality of second scan line connection portions312are the same.

This setting makes the loads caused by the parasitic capacitances of the wirings (including the corresponding scan lines and connection portions) are the same while the first control signal and the second control signal respectively transmitting from the first scan line and the second scan line to the data writing sub-circuit, and the synchronization of the first control signal and the second control signal is further improved.

For example, a size of the first data writing transistor P1electrically connected with the first scan line and a size of the second data writing circuit N1electrically connected with the second scan line are the same, thus the loads generated on respective scan lines are also the same, and the synchronization of the first control signal and the second control signal is further improved, so that the anti-interference performance of the circuit is improved.

For example, each of the plurality of first scan line connection portions311has a same length along the second direction D2, and each of the plurality of first scan line connection portions311has a same line width. Each of the plurality of second scan line connection portions312has a same length in the second direction D2, and each of the plurality of second scan line connection portions312has a same line width.

For example, the first scan line210is electrically connected with the first scan line connection portion311through the via holes231, the second scan line220is electrically connected with the second scan line connection portions312through the via holes232, and the via hole231and the via hole232are both located in the third insulating layer203.

For example, as shown inFIG.10B, the first control electrode group191formed by the first control electrodes of two sub-pixels adjacent in the first direction D1and the second control electrode group192formed by the second control electrodes of the two sub-pixels adjacent in the first direction D1are alternately arranged one by one in the first direction D1.

For example, as shown inFIG.10B, the first scan line connection portion311is electrically connected with the first control electrode group191or the first control electrode through the via hole221, the second scan line connection portion312is electrically connected with the second control electrode group192or the second control electrode through the via hole222. For example, the plurality of first scan line connection portions311are electrically connected with the plurality of first control electrode groups191in a one-to-one correspondence, and the plurality of second scan line connection portions312are electrically connected with the plurality of second control electrode groups192in a one-to-one correspondence.

For example, the first scan lines210and the second scan lines220are located on a same side of the plurality of first control electrode groups191and the plurality of second control electrode groups192, and the first scan lines210are closer to the plurality of first control electrode groups191and the second control electrode groups192.

For example, as shown inFIG.10B, in a direction perpendicular to the base substrate, the first scan lines210intersect with both the first scan line connection portion311and the second scan line connection portion312, and the second scan lines220intersect with both the first scan line connection portion311and the second scan line connection portion312. The via hole231is located at the intersection of the first scan line210and the first scan line connection portion311, and the via hole232is located at the intersection of the second scan line220and the second scan line connection portion312.

For example, as shown inFIG.10B, the via hole231and the via hole232are alternately arranged in the first direction D1and are staggered in the second direction, and the via hole231is closer to the plurality of the first control electrode groups191and the plurality of the second control electrode groups192than the via hole232.

As shown inFIG.10B, one end of the second scan line connection portion312is electrically connected with the corresponding second scan line220through the via hole232, and the other end of the second scan line connection portion312is electrically connected with the second control electrode or the second control electrode group to be connected through the via hole222. The first scan line210passes between the via hole232and the via hole222.

For example, as shown inFIG.10B, the first scan line connection portion311includes a main body portion321and an extension portion322, the extension portion322is a portion extended from the main body portion321and away from the first scan line20along the second direction. The main body portion321is used to electrically connect the first scan line connection portion311and the first control electrode or the first control electrode group, and the main body portion321is located between the first scan line210and the connected first control electrode or first control electrode group in the second direction D2; the extension portion322is located at a side of the first scan lines210away from the first control electrode or first control electrode group connected with the extension portion322in the second direction D2.

Here, the extension portion322serves as a dummy structure, and does not actually play a role of electrical connection, the extension portion322is arranged to make the length and the area of the first scan line connection portion311respectively the same as the length and the area of the second scan line connection portion312, thereby forming the same capacitive load on the first scan line connection portion311and on the second scan line connection portion312.

For example, as shown inFIG.10B, the via hole221is located in the middle of the first control electrode group191, and the via hole222is located in the middle of the second control electrode group192. The two first control electrodes in the first control electrode group191are axisymmetric with respect to the first scan line connection portion311correspondingly connected with the first control electrode group191to the first control electrode group and an extension line of the first scan line connection portion311; and the two second control electrodes in the second control electrode group192are axisymmetric with respect to the second scan line connection portion312correspondingly connected to the second control electrode group and an extension line of the second scan line connection portion312.

Referring toFIG.10A, the first scan lines210correspondingly connected with two adjacent pixel rows are symmetrical about a symmetry axis along the first direction D1, and the second scan lines220corresponding to two adjacent pixel rows are symmetrical about a symmetry axis along the first direction D1.

The display substrate10includes a plurality of data lines extended along the second direction D2, and the data line is used to connect with the first terminal of the data writing sub-circuit in the sub-pixel to provide the data signal Vd.

FIG.11Ashows a schematic diagram of a display substrate provided by other embodiments of the present disclosure, the figure shows a schematic diagram of a data line of a display substrate provided by at least one embodiment of the present disclosure, but the embodiments of the present disclosure are not limited to this case.

With reference toFIG.8A, the data lines are divided into a plurality of data line groups, each of the plurality of data line groups includes a first data line241and a second data line242. The plurality of data line groups are electrically connected with the plurality of pixel columns in a one-to-one correspondence to provide the data signal Vd. Each of the sub-pixel columns is electrically connected with a first data line241and a second data line242respectively; that is, one column of sub-pixels is driven by two data lines.

For example, as shown inFIG.11A, each sub-pixel column is correspondingly connected with two data lines, that is, a first data line241and a second data line242. For each column of sub-pixels, two sub-pixels in an n-th pixel row and in an (n+1)-th pixel row in the plurality of pixel rows constitute a pixel group240, and share one data line, where n is an odd number or an even number greater than 0. For each column of sub-pixels, in the second direction D2, the N-th pixel group240is connected with the first data line241, and the (N+1)-th pixel group240is connected with the second data line242, where N is a natural number, that is, in the second direction D2, the pixel group240is alternately connected with the first data line241and the second data line242, the odd-numbered pixel groups share one data line, and the even-numbered pixel groups share another data line.

By setting two data lines to drive a sub-pixel column, the load on each data line can be reduced, so that the driving ability of the data line is improved, the signal delay is reduced, and the display effect is improved.

Since the display substrate provided by the embodiment of the present disclosure is symmetry in structure, the layout of the signal line can be matched with the driving mode of the above-mentioned data line, to achieve the effect of optimized design.

For example, with reference toFIG.4A, the first electrodes of two first data writing transistors P1in a pixel group240are connected with each other as an integral structure (see region A1), and the first electrodes of two second data writing transistors N1are connected with each other as an integral structure (see region A2), thus in accordance with the above-mentioned driving method of the data line, a connecting via hole can be provided for the first electrodes of the integrated structure to be connected with the data line in a limited contact region, so that the data line is electrically connected with the two first data writing transistors P1or the two second data writing transistors N2in the pixel group240, instead of being connected with the two transistors through a via hole separately. This not only saves the process, but also makes the layout design more compact under the restriction of the design rules, and the resolution of the display substrate is improved.

FIG.11Bshows the connection structure of the data lines in two adjacent pixel groups240, for clarity, only partial diagrams of the sub-pixels in each of the pixel groups connected with the first data line and the second data line are selectively shown, and the partial diagrams corresponding to the two pixel groups are put together, to show the continuous relationship of signal lines, where the dotted line shows a dividing line of the two pixel groups.

As shown inFIG.11B, in a direction perpendicular to the base substrate, the first data line241overlaps with the first data writing transistor P1, and is electrically connected with the first electrodes of two adjacent first data writing transistors P1in one pixel row240; and the second data line242overlaps with the second data writing transistor N1, and is electrically connected with the first electrodes of two adjacent second data writing transistors N1in one pixel group240.

For example, as shown inFIG.11B, in the direction perpendicular to the base substrate, the first data line241overlaps with the gate electrode160of the first data writing transistor P1, the second data line242overlaps with the gate electrode170of the second data writing transistor N1; that is, both the first data line241and the second data line242pass through the pixel region, and no additional pixel space is occupied, to improve the space utilization.

FIG.11CandFIG.11Drespectively show a cross-sectional schematic diagram ofFIG.11Balong the section lines II-II′ and III-III′, and the section lines are, for example, along the first direction D1. For clarity, the figures only show the structure that is electrically connected with the data line, and other structures are omitted. As shown inFIGS.11C and11D, the first data line241and the second data line242are located in the third conductive layer303, and are electrically connected with the corresponding first data line connection portions244in the second conductive layer302through the via holes403and404in the fourth insulating layer204, respectively. In the direction perpendicular to the base substrate, the first data line connection portion244overlaps with the corresponding first data line241or the second data line242respectively. The first data line connection portion244is electrically connected with the second data line connection portion245in the first conductive layer301through the via holes233and234in the third insulating layer203, the second data line connection portion245is electrically connected with the first electrode161of the first data writing transistor P1and the first electrode171of the second data writing transistor N1through the via holes223and224in the second insulating layer202, respectively, so that the data signal is transmitted to the transistors.

Since the first electrodes of the two adjacent first data writing transistors P1and the first electrodes of the two adjacent second data writing transistors N1in one pixel row are respectively connected as an integral structure, and the second data line connection portion245electrically connects the first electrode of the first data writing transistor P1with the first electrode of the second data writing transistor N1in one sub-pixel, thus, the second data line connection portion245electrically connects the first electrodes161of the two first data writing transistors P1and the first electrodes171of the two second data writing transistors N1of two sub-pixels adjacent in the second direction D2in one sub-pixel group, and the second data line connection portion245is connected to the corresponding first data line241or the corresponding second data line242through the corresponding first data line connection portion244. It can be seen that the first electrodes of the four transistors only need to be provided with one via hole in both the third insulating layer and the fourth insulating layer to realize electrical connection with the data line, the layout space is greatly saved, and the space utilization is improved.

As shown inFIGS.11B to11D, for example, the first data line241and the second data line242are symmetrically arranged on two sides of the second data line connection portion245.

For example, as shown inFIGS.11C and11D, the third conductive layer further includes a shielding electrode341, the shielding electrode341is located between the first data line241and the second data line242, for example, the first data line241and the second data line242are symmetrically arranged on two sides of the shielding electrode341. The shielding electrode341is arranged between the two data lines to play a role of shielding, so as to prevent signals in the two data lines from interfering with each other. For example, the shielding electrode341is configured to receive a constant voltage to improve the shielding ability; for example, the shielding electrode341is configured to receive the second power voltage.

For example, as shown inFIG.4A, the first electrodes161of the first data writing transistors P1of two sub-pixels100adjacent in the second direction D2are connected with each other as an integral structure, and the first electrodes171of the second data writing transistors N1of two sub-pixels100adjacent in the second direction D2are connected with each other as an integral structure.

For example, the materials of the above-mentioned first to fourth conductive layers are metal materials, such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W), and alloy materials of the above metals. For example, the materials of the first to fourth conductive layers may also be conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc aluminum oxide (AZO), and so on.

For example, the material of the first insulating layer to the sixth insulating layer is, for example, an inorganic insulating layer, such as silicon oxide, silicon nitride, silicon oxynitride, or other silicon oxide, silicon nitride or silicon oxynitride, or metal oxynitride insulating materials, for example, aluminum oxide, and titanium nitride.

For example, the light-emitting element120is a top emitting structure, the first electrode121is reflective, and the second electrode122is transmissive or semi-transmissive. For example, the first electrode121is made of a material with a high work function to act as an anode, such as an ITO/Ag/ITO laminated structure; the second electrode122is made of a material with a low work function to act as a cathode, for example, is a semi-transmissive metal or metal alloy material, such as an Ag/Mg alloy material.

At least one embodiment of the present disclosure further provides a display panel, which includes any one of the above display substrates10. It should be noted that the above-mentioned display substrate10provided by at least one embodiment of the present disclosure may include a light-emitting element120, and may also not include the light-emitting element120, that is, the light emitting element120can be formed in a panel factory after the display substrate10is completed. In the case that the display substrate10itself does not include the light-emitting element120, the display panel provided by the embodiment of the present disclosure further includes the light-emitting element120in addition to the display substrate10.

At least one embodiment of the present disclosure further provides a display device40, as shown inFIG.12, the display device40includes any one of the above-mentioned display substrates10or display panels, and the display device in this embodiment may be any product or component that has a display function, such as a display, an OLED panel, an OLED TV, an electronic paper, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, and a navigator.

What are described above is related to only the illustrative embodiments of the present disclosure and not limitative to the protection scope of the present application. Therefore, the protection scope of the present application shall be defined by the accompanying claims.