Patent ID: 12211850

The same reference number is used in the drawings for the same or similar (either by function and/or structure) features.

DETAILED DESCRIPTION

As explained above, each digital library has logic cells of a given height and corresponding performance. The applicable unit dimension of cell height may be referred to as “track” (T), “pitch,” “grid,” and the like. Cell height of a given library is referred to as multiples of T. The height of cells in one library, for example, may be 7T (seven times the track, T, dimension). Cell libraries thus may include nT cells, where “n” is greater than or equal to 1 (e.g., 5T cells, 6T cells, 7T cells, 8T cells, 9T cells, etc.). In some cases, n is an integer, but can be other than an integer in other cases (e.g., 6.5T, 7.5T, etc.) A 9T cell may have transistors with a larger channel width (W) than an 8T cell, and an 8T cell may have transistors with a larger W than a 7T cell. Accordingly, a 9T cell is typically a higher performance cell than an 8T cell, and an 8T cell is typically a higher performance cell than a 7T cell. A higher performance cell, however, occupies a larger area than does a lower performance cell.

Any given design generally includes multiple logic cells, including multiple instances of logic cells that implement a same logic function, and instances of logic cells that implement different logic functions. Due to timing constraints, some logic cells may need to be of a higher performance (e.g., lower propagation delay) than other logic cells. For example, 20% of the cells of a design may need to be 9T cells, while the remaining 80% of the cells need not be implemented as 9T cells and can be implemented as 7T cells. However, some place and route software tools only use cells of a same height to implement a circuit. Accordingly, the digital library to source the cells for the design may be the library comprising the highest needed performance cells of the design. In the example above, all of the cells may be implemented using the 9T cell library although only 20% of the cells actually need the performance capability afforded by the 9T cells. The cells that do not need 9T performance are nevertheless implemented using 9T cells, which also means those cells have an area that is larger than necessary (compared to what would have been the case if 7T cells could have been used). Area is thus wasted on higher performance cells when such performance is not needed for many of the cells in the design.

The embodiments described herein are directed to an integrated circuit that includes multiple logic cells arranged in rows on a substrate. A first row includes a first logic cell. A second row includes an extension logic cell. One or more transistors in the first logic cell may have a drive strength that is smaller than the minimum drive strength of the one or more transistors in the extension logic cell. At least a portion of a semiconductor structure forming the extension logic cell extends into an unused area of the first logic cell in the adjacent row, and one or more transistors in the extension logic cell may have a drive strength that is greater than a maximum drive strength of the one or more transistors in the first logic cell. The first logic cell has a low enough drive strength that its semiconductor structure is small enough to result in an unused area within the first logic cell into which the semiconductor structure of the adjacent extension logic cell can extend.

FIG.1is a plan view of an example logic cell100of an integrated circuit (100). The example logic cell100has two transistors. The logic cell100has a width W1and a height H1. The width W1may vary from logic cell to logic cell within a given logic cell library. A “unit width” (UW) defines a standard width measurement of, for example, 0.5 micrometers (microns). The unit width may be a width of a line pitch value at an interconnect metal level, e.g. metal2. In the example ofFIG.1, the width W1of logic cell100is double the unit width (2×UW) and accordingly W1is 1.0 microns (in the example in which UW is 0.5 microns). The height H1is a fixed value for the logic cells of a given library. For example, the cells of one particular library may have H1that is 7T. For the cells of another library, however, H1may be 8T. In general, the height of the cells of a library is nT, where n is an integer greater than or equal to 1. For example, 5T, 6T, 7T, 8T, and 9T cell libraries are available. In one example, “T” is 0.5 microns, which may also be a line pitch value of an interconnect metal level. The cells of a given library all have the same height, but the width of the cells of a given library may vary from cell to cell.

The transistors of the example logic cell100ofFIG.1are configured as an inverter, which is shown schematically inFIG.2, at least some components of which are also identified inFIG.1. The inverter200includes a P-type metal-oxide semiconductor field effect transistor (PMOS transistor) Q1and an N-type metal-oxide semiconductor field effect transistor (NMOS transistor) Q2as well as interconnections (e.g., metal connections between components). Transistor Q1has a source126and a drain128. Transistor Q2has a source136and a drain138. The source126of transistor Q1is coupled to a first power rail (e.g., a non-zero supply voltage, VDD) by a trace115, and the source136of transistor Q2is coupled a second power rail (e.g., ground (VSS)) by a trace120. While shown in a polysilicon level, the traces115,120may be in any interconnect level. While not explicitly shown, the power rails115,120may be located in a metal layer above the low-drive logic cell100such that the side117is at about parallel to and at a midpoint of the power rail115and the side122is at about parallel to and at a midpoint of the power rail120. The drains128and138of transistors Q1and Q2are coupled together at an output node Y (labeled135). A polysilicon (or other suitable material) trace130acts as the gate of the transistors Q1and Q2and a local interconnect between the gates, and is an input node A of the logic cell100. The signal on the output node Y is the logical inverse of the signal on the input node A, Y=Ā. For example, the signal on the output node Y is a logic high responsive to the signal on the input node A being logic low, and vice versa. While the logic cell examples provided in this discussion refer to the function as inversion, the function provided by the logic cells is no limited to any particular functions, which may include, e.g. NOR or NAND gates, or more complex functions such as flip-flops.

Referring again toFIG.1, the logic cell100includes the power rails115and120along the logic cell's opposing sides117and122, respectively, spaced apart along the longitudinal axis by the height H1. Power rail115(configured to receive VDD) is alongside117, and power rail120(configured to receive VSS) is along the opposing side122. The low-drive logic cell100includes a first transistor source-drain region125, and a second transistor source-drain region127. Source-drain region125includes the source126and the drain128of PMOS transistor Q1. Similarly, source-drain region127includes the source136and the drain138of NMOS transistor Q2. The gates of transistors Q1and Q2are coupled together by a trace that which may comprise a polysilicon or other suitable material and provides the node A.

FIGS.3-5are plan views of a 7T digital cell300, an 8T digital cell400, and a 9T digital cell500, respectively. Digital cells300,400, and500generally have the same configuration as that of digital cell100ofFIG.1(two transistors which form an inverter). Some of the components of cell architecture shown inFIG.1are omitted fromFIGS.3-5for simplicity. Digital cell300has source-drain regions325and327and a gate330. Overlying VDD and ground power rails for logic cell300are identified by reference numerals315and320, respectively. Reference numeral350defines the distance between the source-drain regions325,327and the power rails315and320as shown. Digital cell400has source-drain regions425and427and a gate430. The VDD and ground power rails for logic cell400are identified by reference numerals415and420, respectively. Digital cell500has source-drain regions525and527and a gate530. The VDD and ground power rails for logic cell500are identified by reference numerals515and520, respectively, and reference numeral550defines the distance between the source-drain regions525,527and the power rails515and520.

The width of source-drain regions325and327of logic cell300is identified by reference numeral321. In some embodiments, the width of the source-drain region325is the same as for source-drain region327, but in other embodiments the widths can be different. The width of source-drain regions425and427of logic cell400is identified by reference numeral421. The width of source-drain regions525and527of logic cell500is identified by reference numeral521. The width521of source-drain regions525and527of logic cell500is larger than the width421of source-drain regions425and427of logic cell400. The width421of source-drain regions425and427of logic cell400is larger than the width321of source-drain regions325and327of logic cell300. Accordingly, during saturation and for similar gate-to-source voltages, the drain current capacity of logic cell500is larger than that of logic cells300or400, and the drain current capacity of logic cell400is larger than that of logic cell300. In turn, this means that the performance of logic cell500is greater than that of logic cell400, and the performance of logic cell400is greater than that of logic cell300. Logic cell500has a higher performance than logic cells300and400, but logic cell500occupies more area than logic cells300or400. Logic cell300has the lowest performance from among cells300,400, and500but also occupies the smallest area. A trade-off thus exists between size and performance—smaller size results in lower performance but smaller die size, and higher performance but higher die size.

As described above, if at least some of the cells of a given design require the performance of the larger, higher performance logic cells (e.g., 9T cells versus smaller 8T or 7T cells), then all cells in the design are typically implemented with the same size, higher performance cells, resulting in a larger area of the design than would otherwise be needed if smaller, lower drive logic cells were used.FIG.6shows an embodiment in which three logic cells610,400, and660are provided on a semiconductor die640. In general, the die640can include any number of logic cells other than three (two or four or more). Logic cells610,400, and660have the same height (8T in this example).

In this embodiment, logic cell400is as described above. Logic cell400is an 8T logic cell whose transistor channel widths are the same as shown inFIG.4(reference numerals421illustrate the channel widths). Logic cell400has the performance of an 8T logic cell as a result of, at least in part, channel widths421.

Logic cell610implements a same or different logic function than logic cell400and has at least two transistors, at least some of which have channel widths321that are the same as the channel widths of the 7T logic cell300ofFIG.3. Further, for logic cell610, the spacing650between the source-drain regions325,327and the respective power rails315and320is larger than the spacing350of the 7T logic cell300ofFIG.3. Functionally, logic cell610has the performance of a 7T logic cell, but with an 8T height. The larger 8T height results from the larger spacing between the power rails and the source-drain regions, which results in “empty areas”645. Accordingly, logic cell610may be referred to as a “7T equivalent” (7TE) logic cell meaning that it has the performance equivalent of a 7T cell but with a larger height than a conventional 7T logic cell300.

Logic cell660also has at least two transistors, at least some of which have channel widths521that are consistent with the 9T logic cell500ofFIG.5. Functionally, logic cell660has the performance of a 9T logic cell, but with a smaller, 8T height. Accordingly, logic cell610may be referred to as a 9T equivalent (9TE) logic cell. The 8T height of the 9T-performance logic cell660is smaller than a conventional 9T logic cell500(FIG.5). The smaller 8T height is achieved by repositioning the power rails515and520to at least partially overlay the source-drain regions525and527to thereby align with the corresponding power rails of logic cells610and400. As a result, at least a portion of the source-drain regions525and527extend beyond the 8T height dimension.

FIG.7shows a layout of logic cells on a die740. The die740includes at least two rows (ROW1and ROW2) of logic cells. More than two rows are possible in other embodiments. ROW1includes logic cells400and610. ROW2includes logic cells400and660. While two logic cells per row are shown in the embodiment ofFIG.7, any number of logic cells can be included in each row in other embodiments. Furthermore, each of the logic cells may have a same logic function or different logic function from others of the logic cells. A VDD power rail includes power rails315,415and515, a first ground power rail includes power rails320and420at the top of the figure, and a second ground power rail includes power rails320and520at the bottom of the figure. A centerline of the VDD power rail is spaced apart by 8T from each of the first and second ground power rails.

The part of 9TE logic cell660that extends outside the boundaries of the 8T logic cell height extends into the adjacent, lower empty space645of 7TE logic cell610. Because the 7TE logic cell610has empty spaces645, then wherever a 9TE logic cell660is to be included in a layout, a 7TE logic cell610may be included above and/or below the 9TE logic cell. The 8T logic cell400is not located above or below a 9TE logic cell660because logic cell400does not have sufficient empty space into which the upper or lower extension portions of the 9TE logic cell660can be extended. In some embodiments, a 6TE logic cell can be located above and/or below a 9TE (or 10TE) logic cell660. A 6TE logic call has transistors with even narrower width channels (in an 8T height) and thus empty spaces that are even larger than empty spaces645of the 7TE logic cells. In some embodiments, for any mTE logic cell that extends over the cell boundary (e.g., a 9TE logic cell660in the example ofFIG.7), any nTE logic cell can be located above or below it as long as the following relationship between n and m is true:
n≤m−2  (1)
In the example of a 9TE logic cell660extending over the cell boundary, the upper or lower abutting cell could be any of a 7TE, 6TE, 5TE, etc. logic cell.

FIG.8is an example method800for forming an integrated circuit in accordance with the disclosed embodiments. At801, the method includes forming first, second and third power rails over a semiconductor substrate. As explained above, the first power rail is configured to have a first polarity (e.g., VDD) and the second and third power rails are configured to have a different second polarity (e.g., ground, VSS).

At802, the method further includes forming a plurality of first logic cells over the semiconductor substrate in first and second rows. The first row is separated from the second row by the first power rail. Each of the plurality of first logic cells includes a first height and a first semiconductor structure. The first semiconductor structure includes at least one transistor and interconnections to implement a logic function. Further, for each first logic cell in the first row, the first semiconductor structure is located entirely between the first and second power rails. For each at least two adjacent first logic cell in the second row, the first semiconductor structure is located entirely between the first and third power rails.

At803, the method also includes forming an extension logic cell over the semiconductor substrate in the first row. The extension logic cell includes a second height that is greater than the first height. The extension logic cell also includes a second semiconductor structure having at least one transistor and interconnections. The second semiconductor structure is configured to implement at least a second logic function. Further, at least a portion of the second semiconductor structure extends into the second row.

In the embodiment ofFIG.7, the 7TE and 9TE logic cells610and660align horizontally and the empty pace645of the logic cell610is arranged laterally along the entire power rail315of the cell.FIG.9shows an embodiment in which the 7TE and 9TE cells are offset laterally. The semiconductor structure of the 7TE logic cell is identified at910and is L-shaped which provides a laterally smaller (but possibly vertically larger) empty space945into which the semiconductor structure920of the 9TE logic cell can extend.

In this description, the term “couple” may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by direct connection; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, for example, by an end-user and/or a third-party.

While the use of particular transistors is described herein, other transistors (or equivalent devices) may be used instead. For example, a p-type metal-oxide-silicon field effect transistor (“MOSFET”) may be used in place of an n-type MOSFET with little or no changes to the circuit. Furthermore, other types of transistors may be used (such as bipolar junction transistors (BJTs)).

Uses of the phrase “ground” in the foregoing description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value means +/−10 percent of the stated value. Modifications are possible in the described examples, and other examples are possible within the scope of the claims.

Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.