Patent ID: 12206330

TABLE 1 shows the logic states for the set/reset logic component ofFIG.2.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made to the drawings wherein like reference numerals identify similar structural features or aspects of the subject disclosure. For purposes of explanation and illustration, and not limitation, a partial view of an embodiment of a system in accordance with the disclosure is shown inFIG.1and is designated generally by reference character100. Other embodiments of systems in accordance with the disclosure, or aspects thereof, are provided inFIG.2and TABLE 1, as will be described. The systems and methods described herein can be used to overcome traditional problems with high forward control gain in synchronous/standard buck power converters with wide input voltage ranges, e.g. where the input voltage ranges from 90 VDC to 600 VDC.

The DC-DC conversion system100includes a buck converter102configured to receive a DC link voltage as input and to output a DC output voltage that is lower than the DC link voltage. A controller104is operatively connected to the buck converter102to control the buck converter102. The controller104includes logic configured to control the buck converter102in a normal switching mode in response to the DC link voltage being below a predetermined high threshold. The controller104also includes logic configured to control the buck converter102in a rate limited switching mode in response to the DC link voltage being at or above the predetermined high threshold.

The buck converter102includes a positive DC link voltage node106and a negative DC link voltage node108. A switching component110connects the positive and negative DC link voltage nodes106,108. The controller104is operatively connected to control switching of the switching component110. The switching component110includes a pair of switches Q1and Q2connected in series across the positive and negative DC link voltage nodes106,108. The switching components Q1and Q2can be any suitable type of switches, such as solid state switches where the gates are connected to the controller104so the controller104can control the switching of the switching components to produce the output voltage at the DC output nodes114,108.

The buck converter102includes a main inductor LBconnecting a node112between the two switches Q1and Q2to a positive DC output node114. A first reluctance indicated with a dashed box inFIG.1includes the main inductor LB, wherein RBis the winding resistance of the main inductor LB. A second reluctance (the capacitor CO and its associated internal resistance, RCoesras indicated by a dashed line box around them inFIG.1) is connected across the positive DC output node114and the negative DC link voltage node108, which is configured to serve as a negative DC output node. The second reluctance is connected in parallel with the load (represented inFIG.1by RL). Those skilled in the art will readily appreciate that the load is not necessarily part of the buck converter102, and can be any suitable load to be powered by the output voltage and current of the cuck converter102. An input capacitor Cinconnects between the positive and negative DC link voltage nodes106,108in parallel with the switching component110.

With continued reference toFIG.1, the controller104is described now in additional detail. A first current sensor CT1is operatively connected to provide input indicative of current through the positive DC link voltage node106to the current control logic component116of the controller102. The current control logic component116is operatively connected to control switching of the switching component110, e.g. the component116connects to the gates of the switches Q1and Q2. A first voltage sensor VOUTis operatively connected to provide input indicative of voltage across the positive DC output node114and the negative DC link voltage node108to the controller102. A second voltage sensor118is operatively connected to provide input indicative of voltage (VDC_LINK) across the positive and negative DC link voltage nodes106,108to the controller102.

A differential logic component120is operatively connected to output a differential signal indicative of difference between the output from the first voltage sensor VOUTand a commanded voltage (VCMD) to a voltage control logic component122that is configured to output a voltage control signal based on the differential signal. The control algorithm inside block122can be a standard control algorithm, i.e. a proportional plus integral, although any other suitable type of control algorithm can be used. A rate limiter124, e.g. a logic component for limiting current rate through the main inductor LB, is operatively connected to output a rate limiting signal based on the voltage control signal from the voltage control logic component122. A switch logic component126is operatively connected to receive input from a rate limiter logic component128and from the voltage control logic component122. The switch logic component126is configured to switch between sending output from the rate limiter124or from the voltage control logic component122to the current control logic component116. The rate limiter logic component128is operatively connected to receive input (VDC_LINK) from the second voltage sensor118, and to control the switch logic component126between the rate limiting switching mode and the normal switching mode, which are further discussed below.

A method of DC-DC power conversion includes converting a DC link voltage to a DC output voltage for a load, e.g. RL, that is lower than the DC link voltage using a buck converter, e.g. buck converter102. The method includes controlling the buck converter in a normal switching mode in response to the DC link voltage being below a predetermined high threshold. The method also includes controlling the buck converter in a rate limited switching mode in response to the DC link voltage being at or above the predetermined high threshold.

With reference toFIG.2, the logic of the switch logic component126is now described with reference to the methods of operating the system100ofFIG.1. Controlling the buck converter in the rate limited switching mode includes latching the rate limited switching mode in an enabled state, e.g. RL_EN=1 inFIG.2, upon occurrence of the DC link voltage being at or above the predetermined high threshold (DC LINK Voltage>=I_PK_CMD_UP_LIMIT=1 inFIG.2), to keep the rate limited switching mode enabled even if the DC link voltage drops below the predetermined high threshold after latching. This is represented inFIG.2, and TABLE 1, with the state of the S input to the set/reset logic component130being having a value of 1, and the R input of the set/reset logic component130having a value of 0, which gives the output (RL_EN) from the set/reset logic component130a value of 1. This puts the switching logic component126ofFIG.1in the rate limiting switching mode for the switches Q1and Q2. Those skilled in the art will readily appreciate that any suitable method can be used to regulate the peak inductor current for block116ofFIG.1.

The method includes resetting the enabled state of the rate limiting switching mode upon detection of occurrence of the DC link voltage being at or below a predetermined low threshold (DC LINK Voltage<=I_PK_CMD_LO_LIMIT=1 inFIG.2). This is represented inFIG.2, and TABLE 1, with the state of the S input of the set/reset logic component130having a value of either 0 or 1, and with the state of the R input having a value of 1, which gives the output (RL_EN) from the set/reset logic component130a value of 0. This puts the switching logic component126ofFIG.1in the normal switching mode for the switches Q1and Q2. I_PK_CMD_LO_LIMIT and I_PK_CMD_UP_LIMIT are designed values for a given application.

The method includes disabling the rate limited switching mode (RL_EN=0 inFIG.2) upon occurrence of the DC link voltage being at or above the predetermined high threshold and a delayed occurrence of the DC link voltage being at or below the predetermined low threshold. The purpose of the delay box in the logic diagram ofFIG.2is to prevent toggling modes after rapid DC link oscillations outside the high and low thresholds, i.e. to filter out noise. As shown in TABLE 1, if the R and S inputs to the set/reset logic component130are both 0, then there is no change to the output of the set/reset logic component130. In this state, the switching logic component126ofFIG.1will maintain whichever of the switching modes it is already in for the switches Q1and Q2.

With reference again toFIG.1, controlling the buck converter102in the normal switching mode includes controlling current to the load based on measured current supplied to the buck converter at the DC Link Voltage, as an input from the current sensor CT1to the current logic control component116, and based on a commanded inductor current, e.g. the output from the voltage control logic component122, for controlling current in a main inductor, e.g. LB, of the buck converter. The commanded inductor current for controlling the current in the main inductor is derived from a voltage control signal that is based on a differential of commanded output voltage and measured output voltage to the load, e.g. using the differential logic component120.

With continued reference toFIG.1, controlling the buck converter in the rate limiting mode includes controlling current to the load based on measured current supplied to the buck converter at the DC Link Voltage, e.g. as an input from the current sensor CT1to the current logic control component116, and based on a commanded inductor current for controlling current in a main inductor of the buck converter. In this rate limiting mode, the commanded inductor current for controlling the current in the main inductor is derived from a peak inductor current limiting function, e.g. in the rate limiter124, that outputs the commanded inductor current on a rate limited basis relative to the normal switching mode. The output of the rate limiter124is based on a differential of commanded output voltage and measured output voltage to the load, e.g. the output of the differential logic component120.

Systems and method as disclosed herein have the potential to improve the high forward gain control for buck converters relative to more traditional techniques. This in turn can help make power converters more stable and less susceptible to load disturbances, e.g. load transients.

As will be appreciated by those skilled in the art, aspects of the present embodiments may be embodied as a system, method or computer program product. Accordingly, aspects of the present embodiments may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module,” “component” or “system.” Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.

Any combination of one or more computer readable medium(s) may be utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Computer program code for carrying out operations for aspects of the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, Smalltalk, C++ or the like and conventional procedural programming languages, such as the “C” programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).

Aspects of the present disclosure are described above with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the embodiments. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in a flowchart and/or block diagram block or blocks.

The methods and systems of the present disclosure, as described above and shown in the drawings, provide for overcoming traditional problems with high forward control gain in synchronous/standard buck power converters with wide input voltage ranges, e.g. where the input voltage ranges from 90 VDC to 600 VDC. While the apparatus and methods of the subject disclosure have been shown and described with reference to preferred embodiments, those skilled in the art will readily appreciate that changes and/or modifications may be made thereto without departing from the scope of the subject disclosure.