Patent ID: 12235771

DETAILED DESCRIPTION

Various embodiments will be described hereinafter with reference to the accompanying drawings.

In general, according to one embodiment, a memory system is connectable to a host. The memory system comprises a nonvolatile memory, and a controller electrically connected to the nonvolatile memory and configured to control the nonvolatile memory. In response to receiving, from the host, a first read command that requests reading first data and specifies a first virtual address in a virtual address space of the host, the controller executes a command process of reading the first data from the nonvolatile memory. The controller executes an address translation process of translating the first virtual address to a first physical address for accessing a memory of the host. In the address translation process, the controller transmits an address translation request to the host, the address translation request being a request for obtaining first address translation information for translating the first virtual address to the first physical address. In response to receiving, from the host, a response indicating that obtainment of the first address translation information fails, the controller suspends the command process until the first address translation information is obtained, and, after the first address translation information is obtained, resumes the command process.

It is assumed that a memory system according to an embodiment is implemented as an SSD.FIG.1is a block diagram illustrating an example of a configuration of an information processing system1that includes the memory system according to the embodiment. The information processing system1includes a host (host device)2and an SSD3. The host2and the SSD3can be connected via a bus7.

The host2is an information processing apparatus. The host2is, for example, a personal computer, a server computer, or a mobile device. The host2accesses the SSD3. Specifically, the host2transmits, to the SSD3, a write command that is a command to write data. The host2also transmits, to the SSD3, a read command that is a command to read data.

The host2includes a processor21, a memory22, a root complex (RC)23, and an input/output memory management unit (IOMMU)213. The processor21, the memory22, the root complex23, and the IOMMU213are interconnected via an internal bus20.

The SSD3is a storage device that is connectable to the host2. The SSD3includes a nonvolatile memory. The SSD3writes data to the nonvolatile memory. The SSD3also reads data from the nonvolatile memory.

Communication between the SSD3and the host2is executed via the bus7. The bus7is a communication path that connects the host2and the SSD3. The bus7is, for example, a PCI Express™ (PCIe™) bus. The PCIe bus is a full-duplex communication path. The full-duplex communication path includes both a transmission path that transmits data and an input/output (I/O) command from the host2to the SSD3, and a transmission path that transmits data and a response from the SSD3to the host2. The I/O command is a command for writing or reading data to or from the nonvolatile memory. The I/O command is, for example, a write command or a read command.

As a standard of a logical interface for connecting the host2and the SSD3, a standard of NVM Express™ (NVMe™) may be used. In the interface of the NVMe standard, communication between the host2and the SSD3is performed using a pair of queues that include at least one submission queue (SQ) and a completion queue (CQ) associated with the at least one submission queue (SQ). The pair of queues is referred to as a submission queue/completion queue pair (SQ/CQ pair).

The submission queue (SQ) is a queue used to issue a command to the SSD3. The submission queue (SQ) contains a plurality slots. Each of the plurality slots is capable of storing a command. The host2creates the submission queue (SQ) in the memory22of the host2. The host2also issues a submission queue (SQ) create command to the SSD3. The submission queue (SQ) create command notifies the SSD3of an address indicating a memory location in the memory22where the submission queue (SQ) has been created, the size of the submission queue (SQ), a completion queue (CQ) identifier associated with the submission queue (SQ), and so on.

The completion queue (CQ) is a queue used to receive, from the SSD3, a completion response indicating completion of a command. The completion response contains information indicating a status of the completed command. The completion response is also referred to as a command completion or a command completion notification. The completion queue (CQ) contains a plurality of slots. Each of the plurality of slots is capable of storing a completion response. The host2creates the completion queue (CQ) in the memory22of the host2. The host2also issues a completion queue (CQ) create command to the SSD3. The completion queue (CQ) create command notifies the SSD3of an address indicating a memory location in the memory22where the completion queue (CQ) has been created, the size of the completion queue (CQ), and so on.

Next, a configuration of the host2will be described.

The processor21is, for example, a central processing unit (CPU). The processor21executes software (host software) loaded into the memory22from the SSD3or another storage device connected to the host2. The host software includes, for example, a virtual machine monitor, a guest operating system (guest OS) that is an operating system executed on the virtual machine monitor, and application programs.

The memory22is, for example, a volatile memory. The memory22is also referred to as a main memory, a system memory, or a host memory. The memory22is, for example, a dynamic random access memory (DRAM). A part of a memory region of the memory22is used to store the SQ/CQ pair.

In the communication between the host2and the SSD3, a command is issued from the host2to the SSD3and a completion response is transmitted from the SSD3to the host2, using the SQ/CQ pair. The transfer of command, data, and completion response between the host2and the SSD3is executed via the bus7.

The root complex23is a circuit that connects I/O devices (here, the SSD3) connected to the bus7, to each of the processor21and the memory22. The root complex23is connected to each of the processor21and the memory22. The root complex23may be connected to each of the processor21and the memory22via, for example, the internal bus20. The root complex23also executes communications with the SSD3via the bus7.

The IOMMU213is a circuit that translates addresses included in various requests received from the SSD3. The IOMMU213translates an address used by the SSD3into an address used internally by the host2.

Next, an internal configuration of the SSD3will be described. The SSD3includes a controller4and a nonvolatile memory5. The nonvolatile memory5is, for example, a NAND flash memory. The NAND flash memory is also referred to as a NAND memory. In the following, the nonvolatile memory5is referred to as a NAND memory5. The SSD3may also include a random access memory, for example, a dynamic random access memory (DRAM)6.

The controller4is a memory controller. The controller4is, for example, a circuit such as a system-on-a-chip (SoC). The controller4is electrically connected to the NAND memory5. The controller4executes a data write operation of writing data to the NAND memory5and a data read operation of reading data from the NAND memory5. The controller4also executes communication with the host2via the bus7. As a physical interface connecting the controller4and the NAND memory5, for example, a Toggle NAND flash interface, or an open NAND flash interface (ONFI) is used. The functions of each part of the controller4may be implemented by dedicated hardware, a processor that executes a program, or a combination of the dedicated hardware and the processor.

The NAND memory5is a nonvolatile memory. The NAND memory5includes a memory cell array51and a page buffer52. The memory cell array51includes a plurality of memory cells arranged in a matrix. The NAND memory5may be a flash memory of a two-dimensional structure or a flash memory of a three-dimensional structure.

The memory cell array51of the NAND memory5includes a plurality of blocks BLK0 to BLKx−1. Each of the blocks BLK0 to BLKx−1 includes a plurality of pages (here, pages P0 to Py−1). Each page includes, for example, a plurality of memory cells connected to the same word line. Each of the blocks BLK0 to BLKx−1 is a unit for a data erase operation for erasing data. Each of the pages P0 to Py−1 is a unit for a program operation and a sense operation, each of the program operation and the sense operation being described later.

The page buffer52is configured with, for example, a static RAM (SRAM). The page buffer52temporarily stores data to be transferred between the controller4and the NAND memory5.

In performing a data write operation, data received from the controller4is temporarily stored in the page buffer52, and then the data temporarily stored in the page buffer52is programmed into the memory cell array51. The operation of temporarily storing the data received from the controller4in the page buffer52is referred to as a data-in operation. The operation of programming (writing) the data temporarily stored in the page buffer52into the memory cell array51is referred to as a program operation.

In performing a data read operation, data read from the memory cell array51is temporarily stored in the page buffer52, and then the data temporarily stored in the page buffer52is output to the controller4. The operation of temporarily storing the data read from the memory cell array51in the page buffer52is referred to as a sense operation. The operation of outputting the data temporarily stored in the page buffer52to the controller4is referred to as a data-out operation.

Each of the data-in operation and the data-out operation is an operation of transferring data between the controller4and the NAND memory5. Each of the program operation and the sense operation is an operation with data transfer within the NAND memory5without data transfer between the controller4and the NAND memory5. Therefore, each I/O operation executed on the NAND memory5(i.e., a data write operation or a data read operation) includes at least (i) an operation of transferring data between the controller4and the NAND memory5, and (ii) an operation with data transfer within the NAND memory5without data transfer between the controller4and the NAND memory5.

A DRAM6is a volatile memory. A part of the memory region of the DRAM6is used, for example, for storing a logical-to-physical translation table (L2P table)61. The L2P table61stores mapping information. The mapping information is information that indicates mapping between each of logical addresses and each of physical addresses of the NAND memory5. In addition, a part of the memory region of the DRAM6is also used as an internal buffer62. The internal buffer62temporarily stores, for example, write data received from the host2or read data read from the NAND memory5.

Next, an internal configuration of the controller4will be described. The controller4includes a host interface (host I/F)41, a central processing unit (CPU)42, a direct memory access controller (DMAC)43, a static RAM (SRAM)44, a NAND interface (NAND I/F)45, an error correction code (ECC) encoding/decoding unit46, and a DRAM interface (DRAM I/F)47. The host interface41, the CPU42, the DMAC43, the SRAM44, the NAND interface45, the ECC encoding/decoding unit46, and the DRAM interface47are interconnected via a bus40.

Among the components of the controller4, one or more components that control communication with the host2is referred to as a front end (FE). The front end (FE) includes the host interface41.

Among the components of the controller4, one or more components that control communication with the NAND memory5is referred to as a back end (BE). The back end (BE) includes the NAND interface45and the ECC encoding/decoding unit46.

The host interface41is a communication interface circuit. The host interface41executes communication with the host2. The host interface41is, for example, a PCIe controller.

The host interface41includes an arbitration mechanism. This arbitration mechanism is a mechanism of selecting, from a plurality of submission queues of the host2, a submission queue from which a command is to be fetched. The arbitration mechanism is, for example, a round robin arbitration mechanism or a weighted round robin arbitration mechanism.

The host interface41manages, for each of submission queues (SQs), a submission queue tail pointer (SQTP) and a submission queue head pointer (SQHP). In addition, the host interface41manages, for each of completion queues (CQs), a completion queue tail pointer (CQTP) and a completion queue head pointer (CQHP).

The CPU42is a processor. The CPU42controls the host interface41, the DMAC43, the SRAM44, the NAND interface45, the ECC encoding/decoding unit46, and the DRAM interface47. The CPU42loads a control program (firmware) stored in the NAND memory5or a ROM (not shown) into the SRAM44and performs various processes by executing the firmware. The firmware may be loaded into the DRAM6.

The CPU42performs management of data stored in the NAND memory5and management of blocks included in the NAND memory5, as a flash translation layer (FTL). The management of the data stored in the NAND memory5includes, for example, management of mapping information which is information indicating the correspondence between each of logical addresses and each of physical addresses of the NAND memory5. A logical address is an address used by the host2to access the NAND memory5. The logical address is, for example, a logical block address (LBA). The physical address of the NAND memory5is an address indicating a physical storage location among a plurality of physical storage locations included in the NAND memory5. The CPU42manages the mapping between each of the logical addresses and each of the physical addresses using the L2P table61. In addition, the management of blocks included in the NAND memory5includes management of defective blocks (bad blocks) included in the NAND memory5, wear leveling, and garbage collection.

The DMAC43is a circuit that executes direct memory access (DMA). The DMAC43executes data transfer between the memory22of the host2and the SRAM44or the DRAM6. When data is to be transferred from the controller4to the memory22of the host2, the DMAC43transmits a memory write request to the root complex23of the host2and thereby writing the data to the memory22. The memory write request includes information specifying a memory address that indicates a memory location in the memory22to which data is to be transferred. When data is to be transferred from the memory22of the host2to the controller4, the DMAC43transmits a memory read request to the root complex23and thereby obtaining the data from the memory22. The memory read request includes information specifying a memory address that indicates a memory location in the memory22where the data is stored.

The SRAM44is a volatile memory. A part of the memory region of the SRAM44is used by the CPU42as an address translation cache (ATC)441. The ATC441is a cache that stores address translation information. The address translation information is information for translating a virtual address in a virtual address space of the host2to a physical address for accessing the memory22of the host2. The virtual address space of the host2is an address space allocated to a virtual machine executed in the host2. The virtual address in the virtual address space is, for example, a guest physical address (GPA). The guest physical address (GPA) is an address used by the guest OS to access the memory22.

The NAND interface45is a circuit that controls the NAND memory5. When the NAND memory5includes a plurality of NAND flash memory dies, the NAND interface45may be connected to these NAND flash memory dies via a plurality of channels.

The ECC encoding/decoding unit46is a circuit that executes an encoding process of encoding data and a decoding process of decoding data. When data is to be written to the NAND memory5, the ECC encoding/decoding unit46executes the encoding process. In the encoding process, the ECC encoding/decoding unit46adds an error correction code (ECC) as a redundancy code to the data to be written to the NAND memory5. When data is read from the NAND flash memory5, the ECC encoding/decoding unit46executes the decoding process. In the decoding process, the ECC encoding/decoding unit46perform an error correction process for the data read from the NAND memory5, using the ECC added to the data.

The DRAM interface47is a circuit that controls the DRAM6. The DRAM interface47stores data in the DRAM6and reads data stored in the DRAM6.

Next, a functional configuration of the CPU42will be described. The CPU42includes a command fetch unit421, a command processing unit422, and a virtual address translation control unit423. A part or all of each of the command fetch unit421, the command processing unit422, and the virtual address translation control unit423may be implemented by dedicated hardware in the controller4. For example, the command fetch unit421may be implemented in the host interface41.

The command fetch unit421fetches I/O commands from a submission queue (SQ) of the host2via the host interface41. Thus, the controller4is capable of receiving a plurality of I/O commands from the host2.

The command processing unit422interprets an I/O command that is fetched from the submission queue (SQ) and executes a command process corresponding to the I/O command. The command process corresponding to the I/O commands is, for example, a process of writing data to the NAND memory5or a process of reading data from the NAND memory5. Specifically, the command processing unit422instructs the NAND memory5to execute a data write operation or a data read operation corresponding to the I/O command. An instruction of the data write operation or the data read operation is transmitted to the NAND memory5via the NAND interface45.

For example, when the I/O command received (fetched) from the host2is a read command, the command processing unit422executes a command process of reading read target data specified by the I/O command from the NAND memory5. The read target data read from the NAND memory5is temporarily stored in the internal buffer62. Then, the command processing unit422transfers the read target data stored in the internal buffer62to the memory22of the host2.

The command processing unit422transmits a completion response indicative of completion of the I/O command, to the host2via the host interface41. In this case, the command processing unit422stores the completion response in a completion queue (CQ) associated with the submission queue (SQ) from which this I/O command has been fetched.

Further, the command processing unit422transmits an interrupt message to the host2. The interrupt message is a message for notifying the host2that a new completion response has been stored in the completion queue (CQ).

The virtual address translation control unit423executes an address translation process necessary to access the memory22of the host2. The address translation process is a process that translates a virtual address notified to the controller4by a command received from the host2, to a physical address for accessing the memory22of the host2. The virtual address notified to the controller4by the command received from the host2is, for example, (1) a virtual address corresponding to a memory location in the memory22where write data to be written to the NAND memory5is stored, (2) a virtual address corresponding to a memory location in the memory22where a list including a plurality of virtual addresses is stored, the plurality of virtual addresses respectively corresponding to a plurality of memory locations in the memory22where write data to be written to the NAND memory5is stored, (3) a virtual address corresponding to a memory location in the memory22to which read data read from the NAND memory5is to be transferred, (4) a virtual address corresponding to a memory location in the memory22where a list including a plurality of virtual addresses is stored, the plurality of virtual addresses respectively corresponding to a plurality of memory locations in the memory22to which read data read from the NAND memory5is to be transferred, (5) a virtual address corresponding to a memory location in the memory22where a submission queue (SQ) exists, (6) a virtual address corresponding to a memory location in the memory22where a completion queue (CQ) exists, or (7) a virtual address corresponding to a memory location in the memory22to which an interrupt message is to be transferred. The virtual address translation control unit423executes, for example, an ATC search process, an address translation request issuing process, or a page request issuing process.

In the ATC search process, the virtual address translation control unit423determines whether or not address translation information corresponding to a target virtual address to be translated is stored in the ATC441. When the address translation information is stored in the ATC441, the virtual address translation control unit423translates the target virtual address to a physical address of the memory22using the address translation information stored in the ATC441. When the address translation information is not stored in the ATC441, the address translation process performed using the ATC441fails. In this case, the virtual address translation control unit423executes the address translation request issuing process.

In the address translation request issuing process, the virtual address translation control unit423transmits an address translation request to the host2. The address translation request is a request for obtaining an address translation information for translating the target virtual address to a physical address of the memory22. Upon receiving the address translation request, the host2executes a process of obtaining the address translation information corresponding to the virtual address specified by the address translation request. When the address translation information can be obtained, the host2transmits the address translation information to the virtual address translation control unit423of the SSD3. Upon receiving the address translation information, the virtual address translation control unit423translates the virtual address to a physical address of the memory22using the received address translation information. When the address translation information cannot be obtained, the host2transmits a response indicating that obtainment of the address translation information fails, to the virtual address translation control unit423of the SSD3. When receiving, from the host2, the response indicating that the obtainment of the address translation information fails, the virtual address translation control unit423executes the page request issuing process.

In the page request issuing process, the virtual address translation control unit423transmits a page request to the host2. The page request is a message for requesting preparation of address translation information necessary for the address translation process. The host2, which has received the page request, executes a process of preparing the address translation information necessary to translate the virtual address to a physical address of the memory22. When the preparation of the address translation information is completed, the host2transmits a response indicating that the preparation of the address translation information is completed, to the virtual address translation control unit423of the SSD3. The virtual address translation control unit423, which has received the response indicating that the preparation of the address translation information is completed, transmits an address translation request to the host2again. The host2, which has received the address translation request, transmits a response to the address translation request, to the virtual address translation control unit423of the SSD3. The response to the address translation request includes the prepared address translation information. Upon receiving the response, the virtual address translation control unit423translates the virtual address to a physical address of the memory22using the address translation information included in the received response.

The virtual address translation control unit423also notifies the command processing unit422or the command fetch unit421of information about a status of the address translation process, such as (1) information indicating success (cache hit) or failure (cache miss) of the ATC search process, (2) information indicating success or failure of obtainment of the address translation information executed in the host2in response to the address translation request, or (3) information indicating the completion of the process of preparing the address translation information executed in the host2in response to the page request.

Time required to obtain a physical address of the memory22depends on the status of the address translation process. For example, in a case where a cache miss occurs in the ATC441, the time required to obtain a physical address of the memory22becomes longer than in a case where a cache hit occurs in the ATC441. In a case where a response indicating that the obtainment of the address translation information is failed is received from the host2, the time required to obtain a physical address of the memory2will become much longer. Until a physical address of the memory22is obtained, the controller4cannot transmit information such as read data, a completion response, and an interrupt message, to the host2. Therefore, if a command process corresponding to the I/O command is executed without considering the status of the address translation process, the information that cannot be transmitted to the host2may stay in the internal buffer62of the controller4, and thereby the internal buffer62may be occupied with the information that cannot be transmitted to the host2. In this case, not only is the command process of this I/O command delayed, but it is also impossible to fetch other I/O commands. This may cause a degradation in the performance of the I/O process in the SSD3.

Therefore, the controller4adaptively controls the processing of the I/O command based on the status of the address translation process.

For example, when receiving a read command specifying a virtual address in the virtual address space of the host2, the controller4starts a command process of reading read target data, which is specified by the read command, from the NAND memory5.

The controller4also executes an address translation process of translating the virtual address specified by the read command to a physical address for accessing the memory22of the host2.

When the address translation process succeeds, the controller4identifies a memory location in the memory22, based on the physical address obtained in the address translation process. When the virtual address specified by the read command is a virtual address corresponding to a memory location in the memory22to which the read target data is to be transferred, the controller4identifies the memory location indicated by the obtained physical address as a memory location in the memory22to which the read target data is to be transferred. Note that when the size of the read target data specified by the read command is relatively large, the specified virtual address may be a virtual address corresponding to a memory location in the memory22where a list including a plurality of virtual addresses is stored. In this case, the controller4executes both a first address translation process and a second address translation process in order to identify memory locations in the memory22to which the read target data is to be transferred. The first address translation process is a process of translating the specified virtual address to a first physical address that indicates a memory location in the memory22where the list including the plurality of virtual addresses is stored. The second address translation process is a process of translating the plurality of virtual addresses included in the list to a plurality of second physical addresses of the memory22, respectively. The controller4identifies a plurality of memory locations in the memory22indicated by the plurality of second physical addresses as memory locations in the memory22to which the read target data is to be transferred.

The controller4then transfers the data read from the NAND memory5to the identified one or more memory locations in the memory22. In a case where a plurality of memory locations are identified, a plurality of data portions included in the data read from the NAND memory5are transferred to the plurality of memory locations, respectively.

On the other hand, when the address translation process fails, the controller4suspends the command process of reading the read target data from the NAND memory5until the address translation information required for the address translation process becomes obtainable. Then, when the address translation information becomes obtainable, the controller4resumes the command process.

For example, the controller4may suspend the command process when the controller4detects that a cache miss occurs. Alternatively, the controller4may suspend the command process when the controller4receives, from the host2, a response indicating that the obtainment of the address translation information is failed, rather than when a cache miss occurs.

To suspend the command process, the controller4may stop a process of transmitting to the NAND memory5one or more instructions that have not yet been transmitted to the NAND memory5among a plurality of instructions necessary for reading the read target data specified by the read command. Assume, as an example, that it is necessary to transmit ten sense instructions to the NAND memory5to cause the NAND memory5to execute ten sense operations in order to read the read target data specified by one read command. For example, in a case where four sense instructions have already been transmitted to the NAND memory5and the remaining six sense instructions have not yet been transmitted to the NAND memory5, the controller4does not transmit the remaining six sense instructions to the NAND memory5. Data based on the four sense instructions that have already been transmitted to the NAND memory5are transferred from the NAND memory5to the controller4. The controller4maintains this data in the internal buffer62and does not transmit this data to the host2. When the command process is resumed, the controller4transmits the remaining six sense instructions to the NAND memory5and reads the remaining data among the read target data from the NAND memory5. The controller4then transmits the data maintained in the internal buffer62and the remaining data read from the NAND memory5to the host2.

By suspending the command process in this manner, it is possible to prevent the internal buffer62from being occupied for a long period of time by read data that cannot be transmitted to the host2. Also, by suspending the command process, it is possible to prevent read data that cannot be transmitted to the host2from being transferred from the NAND memory5to the controller4. This allows a peak value of the data traffic between the NAND memory5and the controller4to be lowered. Therefore, a peak value of power consumption of each of the NAND memory5and the controller4can also be lowered.

The controller4also executes an address translation process when transmitting to the host2first information (e.g., completion response or interrupt message). The first information is information for notifying the host2of completion of an I/O command. In this address translation process, a virtual address corresponding to a memory location in the memory22of the host2to which the first information is to be transferred is translated to a physical address for accessing the memory22.

When this address translation process succeeds, the controller4transfers the first information to the memory22using the physical address obtained in the address translation process.

On the other hand, when the address translation process fails, the controller4suspends a first process of fetching another I/O command from a submission queue associated with a completion queue in which the completion response of this completed I/O command is to be stored until the address translation information necessary for the address translation process becomes obtainable, and resumes the first process after the address translation information becomes obtainable. As a result, it is possible to prevent a resource (e.g., SRAM44) in the controller4from being occupied by the completion responses or the interrupt messages that cannot be transmitted to the host2.

Next, a procedure of a series of processes for processing I/O commands will be described.FIG.2is a diagram illustrating a procedure of a series of processes for processing an I/O command, which is executed in the memory system according to the embodiment.FIG.2illustrates the procedure from when the host issues an I/O command to when the host2processes a completion response corresponding to this I/O command.

Step1: The host2stores one or more new I/O commands to be transmitted to the SSD3, in one or more free SQ slots in the submission queue (SQ). These one or more new I/O commands are stored in the one or more free SQ slots beginning with a slot indicated by a current value of a submission queue tail pointer (SQTP). The new I/O commands stored in the submission queue (SQ) may be write commands, read commands, or other I/O commands. InFIG.2, each I/O command stored in the submission queue (SQ) is denoted as “CMD”.

Step2: To notify the controller4of the SSD3that one or more new I/O commands have been stored in the submission queue (SQ), the host2performs write access to a submission queue tail doorbell register in the SSD3, the register corresponding to the submission queue (SQ), and updates a value of the submission queue tail pointer (SQTP) corresponding to the submission queue (SQ). The value of the submission queue tail pointer (SQTP) is incremented by the number of new I/O commands stored in the submission queue (SQ). Such updating of the submission queue tail pointer (SQTP) serves as a trigger that causes the controller4to start processing each of the I/O commands stored in the submission queue (SQ)

Step3: The controller4can recognize the number of new I/O commands stored in the submission queue (SQ) from the difference between the new value of the submission queue tail pointer (SQTP) and the value of the submission queue head pointer (SQHP). The controller4fetches any given number of I/O commands, the any given number being one or more, from the submission queue (SQ). Each of the fetched I/O commands is temporarily stored in the SRAM44of the controller4.

Step4: The controller4updates the value of the submission queue head pointer (SQHP) corresponding to the submission queue (SQ) such that the value of the submission queue head pointer (SQHP) is incremented by the number of the I/O commands fetched at step3.

Step5: The controller4executes each of the fetched I/O commands. That is, the controller4executes a command process corresponding to each of the fetched I/O commands. An order in which command processes corresponding to these I/O commands are executed is not limited to a specific order, and these I/O commands may be processed in an order different from an order in which these I/O commands are fetched. In the command process corresponding to each of the I/O commands, the controller4executes data transfer from the memory22to the internal buffer62or data transfer from the internal buffer62to the memory22, as needed.

Step6: When a command process corresponding to a certain I/O command is completed, the controller4first updates the completion queue tail pointer (CQTP) corresponding to the completion queue (CQ) associated with the submission queue (SQ) from which this completed I/O command is fetched, and increments the value of the completion queue tail pointer (CQTP) by one.

Step7: The controller4stores a new completion response indicating the status of this completed I/O command, in a next free CQ slot in this completion queue (CQ). InFIG.2, each of the completion responses stored in the completion queue (CQ) is denoted as “CPL”.

Step8: The controller4transmits an interrupt message associated with the completion queue (CQ) in which the completion response is stored at step7, to the host2, thereby notifying the host2that a new completion response has been stored in this completion queue (CQ). In this case, the controller4transfers the interrupt message to the host2by transmitting to the host2a memory write request specifying a predetermined memory address of the memory22. A memory location in the memory22to which the interrupt message is to be transferred may, for example, be pre-specified for each completion queue (CQ) by the host2.

Step9: The host2obtains one or more completion responses from a CQ slot in this completion queue (CQ), the CQ slot being indicated by the current value of the completion queue head pointer (CQHP), and processes the obtained one or more completion responses.

Step10: The host2performs write accesses to a completion queue head doorbell register in the SSD3, the register corresponding to this completion queue (CQ), and updates the value of the completion queue head pointer (CQHP). The value of the completion queue head pointer (CQHP) is incremented by the number of completion responses processed at step9.

Next, an operation of accessing the memory22of the host2will be described.FIG.3is a diagram illustrating an operation of accessing a memory of a host which is executed in the memory system according to the embodiment, and an operation of accessing the memory of the host which is executed in a virtual machine of the host.

In the host2, a virtual machine monitor (VMM)211is executed. The VMM211is software that creates one or more virtual machines on a computer that functions as the host2. The VMM211operates each of the created virtual machines. InFIG.3, the VMM211creates a virtual machine VM0 and a virtual machine VM1, and the virtual machine VM0 and the virtual machine VM1 are executed on the VMM211. The operation of the virtual machine VM0 is controlled by a guest OS #0, which is an operating system executed on the VMM211. The operation of the virtual machine VM1 is controlled by a guest OS #1, which is another operating system executed on the VMM211.

The guest OS #0 of the virtual machine VM0 accesses the memory22using a guest physical address (GPA) in a guest physical address space (GPA space) allocated to the virtual machine VM0 by the VMM211. The GPA space allocated to the virtual machine VM0 is a virtual address space used by the guest OS #0 to access the memory22.

The guest OS #1 of the virtual machine VM1 accesses the memory22using a guest physical address (GPA) in a guest physical address space (GPA space) allocated to the virtual machine VM1 by the VMM211. The GPA space allocated to the virtual machine VM1 is a virtual address space used by the guest OS #1 to access the memory22.

In addition to the IOMMU213, the host2includes a memory management unit (MMU)212.

The MMU212translates a GPA included in a memory access request issued by the processor21(i.e., each of the guest OS #0 and the guest OS #1 inFIG.3), to a host physical address (HPA). The HPA is a physical address for accessing the memory22. The MMU212accesses the memory22using the HPA.

The IOMMU213translates a memory address included in a memory access request issued by the SSD3, to an HPA. In other words, the memory address issued by the SSD3to access the memory22is a GPA in a GPA space used by a guest OS. Therefore, the IOMMU213translates the GPA included in the memory access request issued by the SSD3to an HPA. For example, in a case where the SSD3is associated with the virtual machine VM0 as an I/O device for the virtual machine VM0, the IOMMU213translates, based on the correspondence between the GPA space of the guest OS #0 and the HPA space of the memory22, the GPA included in the memory access request issued by the SSD3, to an HPA.

Here, a case in which a read command is issued from the guest OS #0 to the SSD3is described. The read command specifies a data pointer in addition to a start logical block address corresponding to read target data and a length of the read target data (the number of logical block addresses). The data pointer is information about a memory location in the memory22to which the read target data is to be transferred.

The memory22is logically divided into a plurality of memory locations referred to as memory pages. The size of each of the memory pages is set by the host2. A minimum size of the memory page that can be set is, for example, 4 KiB.

The read command can specify one or more memory locations (memory pages) in the memory22to which the read target data is to be transferred by using a physical region page (PRP) entry, a PRP list, or a scatter gather list (SGL). Here, a case in which the read command uses the PRP entry is assumed. The read command includes a first PRP entry field (PRP1) and a second PRP entry field (PRP2). Each of the PRP1 and the PRP2 specifies a memory page using a PRP entry. The PRP entry is a pointer to the memory page. The PRP entry includes a page base address of the memory page and an offset within this memory page. The page base address is an address that identifies one memory page.

Since the guest OS #0 recognizes only the GPA space of the guest OS #0, each of the PRP1 and the PRP2 included in the read command issued by the guest OS #0 specifies a page base address of a memory page using a GPA in the GPA space of the guest OS #0.

The SSD3that has received the read command executes a command process corresponding to the received read command. Based on the received read command, the SSD3starts the command process of reading the read target data from the NAND memory5. Then, with reference to the PRP1 and the PRP2 included in the received read command, the SSD3obtains one or two GPAs respectively corresponding to one or two memory pages to which the read target data is to be transferred. Note that, in a case where the size of the read target data is small, the read command may specify only one GPA corresponding to one memory page using only the PRP1.

To transfer the read target data read from the NAND memory5to the memory22, the SSD3transmits a memory write request to the host2, the memory write request specifying the obtained GPA. The memory write request is received by the IOMMU213. In a case where the SSD3is an I/O device associated with the virtual machine VM0, the IOMMU213translates the GPA included in the memory write request to an HPA, based on the correspondence between the HPA space and the GPA space of the virtual machine VM0. The IOMMU213then writes the read target data to the memory22using the HPA. As a result, the read target data is stored in a memory location (memory page) in the memory22, which is indicated by the HPA.

Next, the relationship between the GPA space and the HPA space will be described.FIG.4is a diagram illustrating the relationship between the GPA space and the HPA space used by the host. Here, similarly to a case illustrated inFIG.3, a case in which two virtual machines (virtual machines VM0 and VM1) are executed in the host2is assumed.

For the virtual machine VM0, a GPA space #0 with a range of 0x000000 to 0x0FFFFF is allocated. Similarly, for the virtual machine VM1, a GPA space #1 with a range of 0x000000 to 0x0FFFFF is allocated. Here, 0x represents hexadecimal notation.

Each of these GPA spaces is a subset of the HPA space and is mapped to a specific range within the HPA space. In the example inFIG.4, the GPA space #0 is, for example, mapped in a range 0x200000 to 0x2FFFFF in the HPA space. In this case, for example, 0x050000 in the GPA space #0 is translated to 0x250000 in the HPA space by the MMU212or the IOMMU213. The GPA space #1 is mapped to, for example, a range 0x100000 to 0x1FFFFF in the HPA space. In this case, for example, 0x050000 in the GPA space #1 is translated to 0x150000 in the HPA space by the MMU212or the IOMMU213.

Next, a PRP list specified in a read command will be described.FIG.5is a diagram illustrating a PRP entry and a PRP list which are specified by a read command issued to the memory system according to the embodiment.

In a case where the size of read target data is larger than the total size that can be described by using two PRP entry fields (PRP1 and PRP2) of the read command, i.e., larger than the size corresponding to two memory pages, at least one of the two PRP entry fields of the read command is used to specify a PRP list, which is a set of a plurality of PRP entries. The PRP list including the plurality of PRP entries is stored in one memory page. The PRP entry field specifying the PRP list indicates a page base address of a memory page where the PRP list is stored.

FIG.5exemplifies a case where the read command uses the PRP1 and the PRP2 to specify four memory pages in the memory22to which the read target data is to be transferred. InFIG.5, the PRP1 included in the read command specifies one memory page. The PRP2 included in the read command specifies one memory page that stores the PRP list to specify three memory pages.

The PRP1 indicates a page base address of one memory page. Here, the PRP1 indicates the page base address of a memory page of page #0, for example.

The PRP2 indicates a page base address of another memory page that stores the PRP list. The memory page indicated by the PRP2 includes a plurality of PRP entries. Here, the memory page indicated by the PRP2 stores, for example, three PRP entries, i.e., PRP entries #0 to #2. The PRP entries #0 to #2 indicate, for example, page base addresses of three memory pages of pages #1 to #3, respectively.

Here, a case in which the read command specifies a start LBA as LBA #0 and data length as four LBAs is assumed. In a case where the data size corresponding to one LBA is 4KiB and the memory page size is 4KiB, four pieces of data corresponding to LBAs #0 to #3, each having a size of 4KiB, are to be transferred respectively to four memory pages corresponding to pages #0 to #3.

Note that, in the case where this read command is issued to the SSD3by the guest OS #0 or the guest OS #1, each of the PRP1 and the PRP2 uses a GPA to specify a certain memory page. That is, the address stored in the PRP1 of the read command indicates a GPA corresponding to the memory page of page #0. The address stored in the PRP2 of the read command indicates a GPA corresponding to the memory page that stores the PRP list.

Each of the plurality of PRP entries included in the PRP list also uses a GPA to indicate a certain memory page. For example, the address stored in the PRP entry #0 included in the PRP list indicates a GPA corresponding to the memory page of page #1. The address stored in the PRP entry #1 included in the PRP list indicates a GPA corresponding to the memory page of page #2. The address stored in the PRP entry #2 included in the PRP list indicates a GPA corresponding to the memory page of page #3.

Therefore, in order to access the three memory pages (pages #1 to #3), it is necessary to execute: (1) a process of translating the GPA indicated by the PRP2 to a HPA in the memory22and obtaining the PRP list from the memory22; (2) a process of translating the GPA indicated by the PRP entry #0 included in the obtained PRP list to a HPA in the memory22; (3) a process of translating the GPA indicated by the PRP entry #1 included in the obtained PRP list to a HPA in the memory22; and (4) a process of translating the GPA indicated by the PRP entry #2 included in the obtained PRP list to a HPA in the memory22.

Note that, similarly to the PRP entry fields (PRP1, PRP2) included in the read command, the PRP entry fields (PRP1, PRP2) included in a write command can also specify a memory page where a PRP list is stored.

Furthermore, for both read and write commands, the SGL can be used instead of the PRP list. The SGL also uses the same mechanism as the PRP list to allow more memory pages to be used for data transfer than the number of memory pages which can be described in a command alone.

Next, the address translation process will be described.FIG.6is a diagram illustrating an address translation process executed in the memory system according to the embodiment. The IOMMU213includes a translation agent (TA)214and an address translation protection table (ATPT)215. The function of each part of the IOMMU213can be implemented by dedicated hardware, a processor that executes a program, or a combination of the dedicated hardware and the processor.

In a standard of PCIe, a function related to the IOMMU213is defined as an address translation service (ATS). The ATS is a protocol for performing communication related to address translation between the host2and the SSD3. In the following, the address translation request described with reference toFIG.1is referred to as an ATS translation request. The ATS translation request is an address translation request to translate a virtual address to a physical address for accessing the memory22.

In response to receiving the ATS translation request from the SSD3via the RC23, the translation agent214executes an ATS translation process. The ATS translation process is a process that obtains the address translation information corresponding to the virtual address specified by the received ATS translation request, from the address translation protection table215. In the ATS, the virtual address is defined as an untranslated address, and the physical address of the memory22is defined as a translated address. The virtual address is, for example, a GPA. The physical address is, for example, an HPA. Then, the translation agent214transmits an ATS completion response that includes the address translation information obtained from the address translation protection table215, to the SSD3via the RC23.

The address translation protection table215is a table that stores the address translation information.

When a virtual address specified by the host2(e.g., guest OS) is to be translated to a physical address of the memory22, first, the virtual address translation control unit423searches the ATC441to determine whether or not address translation information corresponding to the virtual address is stored in the ATC441. When the address translation information is not stored in the ATC441, the virtual address translation control unit423transmits an ATS translation request specifying the virtual address, to the RC23of the host2. When receiving the ATS translation request from the SSD3, the RC23transmits the received ATS translation request to the translation agent214.

The translation agent214, which has received the ATS translation request, searches the address translation protection table215and determines whether or not address translation information corresponding to the virtual address specified by the ATS translation request is stored in the address translation protection table215. When the address translation information is stored in the address translation protection table215, the translation agent214obtains the address translation information from the address translation protection table215. The address translation information obtained from the address translation protection table215includes a physical address corresponding to the virtual address specified by the ATS translation request, or both this physical address and the virtual address specified by the ATS translation request. The translation agent214transmits an ATS completion response that includes the obtained address translation information, to the virtual address translation control unit423via the RC23. When the address translation information is not stored in the address translation protection table215or other errors have occurred, the translation agent214transmits an ATS completion response indicating that the ATS translation process fails, i.e., that obtainment of address translation information fails, to the virtual address translation control unit423via the RC23.

When receiving the ATS completion response including the address translation information, the virtual address translation control unit423stores the physical address included in the address translation information of the received ATS completion response, or both the virtual address and the physical address included in the address translation information of the received ATS completion response, in the ATC441.

When receiving, from the translation agent214, the ATS completion response indicating that the obtainment of the address translation information failed, the virtual address translation control unit423transmits a page request to the RC23of the host2. The page request is a message requesting preparation of the address translation information. When receiving the page request, the RC23notifies the received page request to, for example, the processor21or the VMM211. This allows the host2(the processor21or the VMM211) to start a process of preparing the address translation information in the address translation protection table215. When the address translation information is prepared, the host2transmits a response to the virtual address translation control unit423via the RC23. The response is a response to the page request and indicates that the preparation of the address translation information is completed. The virtual address translation control unit423, which has received the response to the page request, transmits the ATS translation request to the translation agent214again.

Furthermore, when the address translation information in the address translation protection table215is changed by, for example, updating the correspondence between the GPA space and the HPA space, the translation agent214transmits an invalidation request to the virtual address translation control unit423via the RC23. The invalidation request is a request for invalidating old address translation information stored in the ATC441. The invalidation request specifies a specific range of the virtual address. The virtual address translation control unit423, which has received the invalidation request, invalidates each entry in the ATC441where address translation information corresponding to each of the virtual addresses belonging to the specified range is stored.

Next, a procedure of the address translation process will be described.FIG.7is a flowchart illustrating a procedure of the address translation process executed in the memory system according to the embodiment. When a memory read request or a memory write request is to be transmitted to the host2, the virtual address translation control unit423of the controller4starts the address translation process.

The virtual address translation control unit423searches the ATC441for address translation information necessary to translate a target GPA to a physical address (HPA) of the memory22, then determines whether or not the address translation information corresponding to the target GPA exists in the ATC441(step S101).

When the address translation information corresponding to the target GPA exists in the ATC441, that is, when a cache hit occurs in the ATC441(Yes at step S101), the virtual address translation control unit423obtains the address translation information from the ATC441. The virtual address translation control unit423translates the target GPA to the HPA using the address translation information obtained from the ATC441(step S102).

When the address translation information corresponding to the target GPA does not exist in the ATC441, that is, when a cache miss occurs in the ATC441(No at step S101), the virtual address translation control unit423transmits, to the host2, an ATS translation request specifying the target GPA (step S103). The host2, which has received the ATS translation request, executes the ATS translation process of obtaining, from the address translation protection table215, address translation information corresponding to the specified GPA. When the ATS translation process is completed, the host2transmits an ATS completion response to the virtual address translation control unit423. When obtainment of the address translation information succeeds, the host2transmits, to the virtual address translation control unit423, an ATS completion response including the address translation information and a status indicating success of the obtainment of the address translation information, i.e., success of the ATS translation process. On the other hand, when the obtainment of the address translation information fails, the host2transmits, to the virtual address translation control unit423, an ATS completion response including a status indicating failure of the obtainment of the address translation information, i.e., failure of the ATS translation process.

The virtual address translation control unit423receives the ATS completion response from the host2(step S104).

The virtual address translation control unit423determines whether or not the received ATS completion response includes a status indicating success (step S105).

When the received ATS completion response includes a status indicating success (Yes at step S105), the virtual address translation control unit423stores the address translation information included in the received ATS completion response in the ATC441(step S106).

The virtual address translation control unit423translates the target GPA to the HPA using the address translation information received at step S104(step S102).

When the received ATS completion response includes a status indicating failure (No at step S105), the virtual address translation control unit423transmits a page request to the host2(step S107). The host2, which has received the page request, starts a process of preparing address translation information corresponding to the GPA specified by the page request. In the process of preparing the address translation information, the host2prepares the address translation information corresponding to the GPA specified by the page request in the address translation protection table215. When the process of preparing the address translation information is completed, the host2transmits a response to the page request, to the virtual address translation control unit423.

The virtual address translation control unit423receives the response to the page request from the host2(step S108).

The virtual address translation control unit423transmits the ATS translation request specifying the target GPA to the host2again (step S109). The host2, which has received the ATS translation request, executes the ATS translation process of obtaining the address translation information corresponding to the specified GPA from the address translation protection table215. The address translation information corresponding to the specified GPA has already been prepared in the address translation protection table215. Therefore, the ATS translation process is assumed to be successful. When the ATS translation process is completed, the host2transmits, to the virtual address translation control unit423, an ATS completion response including the address translation information and a status indicating success.

The virtual address translation control unit423receives the ATS completion response from the host2(step S110).

The virtual address translation control unit423determines whether or not the received ATS completion response includes a status indicating success (step S111).

When the received ATS completion response includes the status indicating success (Yes at step S111), the virtual address translation control unit423stores the address translation information included in the received ATS completion response in the ATC441(step S112).

The virtual address translation control unit423translates the target GPA to the HPA using the address translation information included in the received ATS completion response (step S102).

If the received ATS completion response includes a status indicating failure (No at step S111) for some reason, the virtual address translation control unit423transmits the page request to the host2again (step S107).

Thus, in performing the address translation process, time required for the address translation process differs among (A) a case where the address translation information can be obtained from the ATC441, (B) a case where the address translation information can be obtained by transmitting an ATS translation request, and (C) a case where the address translation information can be obtained by transmitting the ATS translation request again after transmitting a page request. Accordingly, in the SSD3according to the embodiment, the command process is controlled according to the status of the address translation process.

First, the control of a command process for a read command will described.FIG.8is a sequence diagram illustrating a first example of a procedure of a command process for a read command, which is executed in the memory system according to the embodiment. InFIG.8, a case in which a PRP list is specified by a PRP entry field included in the read command, i.e., the PRP entry field indicates a GPA corresponding to a memory location (memory page) where the PRP list is stored, is assumed. Furthermore, inFIG.8, a case in which a cache hit occurs in all address translation processes, is assumed.

In a command fetch process, the front end (FE) of the controller4issues an I/O command fetch request using a GPA (step S201). This GPA is a virtual address corresponding to an SQ slot of a submission queue (SQ) from which an I/O command is to be fetched. The FE of the controller4passes the issued fetch request to the virtual address translation control unit423.

The virtual address translation control unit423searches the ATC441for address translation information corresponding to the GPA included in the fetch request received from the FE (step S202). When the address translation information corresponding to this GPA is stored in the ATC441(cache hit), the virtual address translation control unit423obtains the address translation information from the ATC441and translates the GPA to an HPA using the obtained address translation information (step S203).

The command fetch unit421issues a memory read request of fetching the I/O command from the memory22, using the HPA translated by the virtual address translation control unit423(step S204). In the following, the memory read request is referred to as a DMA read request. At step S204, the command fetch unit421transmits, to the RC23of the host2, the DMA read request that includes the translated HPA. On the basis of the HPA included in the DMA read request received from the controller4, the RC23reads the I/O command (in this case, a read command) from the SQ slot of the memory22and transmits the read command, which is read from the SQ slot, to the controller4as a response to the DMA read request. In this manner, the FE receives the read command from the host2(step S205). The received read command is passed from the FE to the BE. The BE starts a command process for reading read target data specified by the read command, from the NAND memory5. Then, the FE moves to a data transfer process.

In the data transfer process, the FE issues a fetch request for the PRP list, using the GPA included in the PRP entry field of the received read command (step S206). The FE passes the issued fetch request to the virtual address translation control unit423.

The virtual address translation control unit423searches the ATC441for address translation information corresponding to the GPA included in the fetch request received from the FE (step S207). When the address translation information corresponding to this GPA is stored in the ATC441(cache hit), the virtual address translation control unit423obtains the address translation information from the ATC441and translates this GPA to an HPA using the obtained address translation information (step S208).

The command fetch unit421issues a DMA read request for fetching the PRP list from the memory22, using the HPA translated by the virtual address translation control unit423(step S209). At step S209, the command fetch unit421transmits, to the RC23of the host2, the DMA read request that includes the translated HPA. On the basis of the HPA included in the DMA read request received from the controller4, the RC23reads the PRP list from the memory22and transmits the read PRP list to the controller4as a response corresponding to the DMA read request. In this manner, the FE of the controller4receives the PRP list from the host2(step S210).

The PRP list includes a plurality of GPAs, the plurality of GPAs respectively corresponding to a plurality of memory locations in the memory22to which read data is to be transferred. The FE executes, for each of the GPAs included in the PRP list, the following process.

The FE selects one GPA from the plurality of GPAs included in the PRP list. The FE issues a transfer request for transferring read data to the memory22using the selected GPA (step S211). The FE passes the issued transfer request to the virtual address translation control unit423.

The virtual address translation control unit423searches the ATC441for address translation information corresponding to the GPA included in the transfer request received from the FE (step S212). When a cache hit occurs, the virtual address translation control unit423translates the GPA to an HPA using the address translation information in the ATC441(step S213).

The DMAC43issues a memory write request for transferring the read data to the memory22, using the HPA translated by the virtual address translation control unit423(step S214). In the following, the memory write request is referred to as a DMA write request. At step S214, the DMAC43transmits, to the RC23of the host2, a DMA write request that includes the translated HPA and the read data. When receiving the DMA write request from the controller4, the RC23stores the read data included in the received DMA write request in a memory location in the memory22. The memory location is indicated by the HPA included in the received DMA write request. To execute the transfer process for all the read data, the controller4executes the processes from step S211to step S214as many times as the number of GPAs included in the PRP list. When the transfer processes for all the read data are completed, the FE moves to a completion response transfer process.

In the completion response transfer process, the FE issues a transfer request for transferring a completion response to the memory22, using a GPA (step S215). This GPA is a GPA corresponding to a memory location in the memory22to which this completion response is to be transferred, i.e., a GPA corresponding to a next free CQ slot of a completion queue (CQ) associated with the SQ from which the completed read command has been fetched. The FE passes the issued transfer request to the virtual address translation control unit423.

The virtual address translation control unit423searches the ATC441for address translation information corresponding to the GPA included in the transfer request received from the FE (step S216). When a cache hit occurs, the virtual address translation control unit423translates the GPA to an HPA using the address translation information in the ATC441(step S217).

The DMAC43issues a DMA write request for transferring the completion response to the memory22, using the HPA translated by the virtual address translation control unit423(step S218). At step S218, the DMAC43transmits, to the RC23of the host2, the DMA write request. The DMA write request includes the translated HPA and the completion response. When receiving the DMA write request from the controller4, the RC23stores the completion response included in the received DMA write request in a memory location in the memory22. The memory location is indicated by the HPA included in the received DMA write request. The FE then moves to an interrupt transmission process.

In the interrupt transmission process, the FE issues a transmission request for transmitting an interrupt message to the memory22, using a GPA (step S219). This GPA is a GPA corresponding to a memory location in the memory22where the interrupt message is to be transmitted. The interrupt message includes an interrupt vector associated with a completion queue (CQ) where the completion response was stored at step S218. The FE passes the issued transmission request to the virtual address translation control unit423.

The virtual address translation control unit423searches the ATC441for address translation information corresponding to the GPA included in the transmission request received from the FE (step S220). When a cache hit occurs, the virtual address translation control unit423translates the GPA to an HPA using the address translation information in the ATC441(step S221).

The DMAC43issues a DMA write request for transmitting the interrupt message to the memory22, using the HPA translated by the virtual address translation control unit423(step S222). At step S222, the DMAC43transmits, to the RC23of the host2, the DMA write request. The DMA write request includes the translated HPA and the interrupt message. When receiving the DMA write request from the controller4, the RC23stores the interrupt message included in the received DMA write request in a memory location in the memory22. The memory location is indicated by the HPA included in the received DMA write request. Then, the series of processing for the read command is ended.

Next, a case in which a cache miss occurs in the ATC441will be described.FIG.9is a sequence diagram illustrating a second example of a procedure of a command process for a read command, which is executed in the memory system according to the embodiment.

In a command fetch process, the controller4executes processes from step S301to step S302. The processes from step S301to step S302are the same as the processes from step S201to step S202described inFIG.8. When a cache miss occurs in the ATC441at step S302, the virtual address translation control unit423transmits, to the host2, an ATS translation request specifying the GPA included in the fetch request received from the FE (step S303). The host2searches the address translation protection table215for address translation information corresponding to the GPA which is an untranslated address specified by the ATS translation request received from the controller4. When the address translation information can be obtained from the address translation protection table215, the host2transmits, to the controller4, an ATS completion response including the obtained address translation information and a status indicating the success of the ATS translation process.

The virtual address translation control unit423receives the ATS completion response from the host2(step S304).

Since the ATS translation process has succeeded, the virtual address translation control unit423stores the address translation information included in the received ATS completion response in the ATC441(step S305).

The virtual address translation control unit423translates the GPA to an HPA using this address translation information (step S306). Processes from step S302to step S306are collectively referred to as an ATS process.

The virtual address translation control unit423executes processes from step S307to step S308. The processes from step S307to step S308are the same as the processes from step S204to step S205described inFIG.8. The FE then moves to a data transfer process.

In the data transfer process, the FE issues a fetch request for the PRP list using a GPA included in the PRP entry field of the obtained read command (step S309). The FE passes the issued fetch request to the virtual address translation control unit423.

Then, when a cache miss occurs in the ATC441, the virtual address translation control unit423executes an ATS process (or an ATS+page request interface (PRI) process described later) (step S310). The ATS process executed at step S310is the same as the ATS process described at steps S302to step S306. The ATS+PRI process executed at step S310is a process executed in the case where the ATS translation process in the ATS process has failed.

When an HPA corresponding to a memory location where the PRP list is stored is obtained in the ATS process (or the ATS+PRI process), the controller4executes the processes from step S311to step S313. The processes from step S311to step S313are the same as the processes from step S209to step S211described inFIG.8.

When a cache miss occurs in the ATC441in the ATC search process that searches for address translation information corresponding to a GPA selected from the PRP list, the virtual address translation control unit423executes the ATS process (or the ATS+PRI process) (step S314).

The DMAC43executes a process of step S315using the HPA obtained in the ATS process (or the ATS+PRI process) executed at step S314. The process executed at step S315is the same as the process executed at step S214described inFIG.8. When the transfer processes of all the read data are completed, the FE moves to a completion response transfer process.

In the completion response transfer process, the FE issues a transfer request for transferring a completion response to the memory22, using a GPA corresponding to a next free CQ slot in the completion queue (CQ) (step S316).

When a cache miss occurs in the ATC441in the ATC search process that searches for address translation information corresponding to the GPA included in this transfer request, the virtual address translation control unit423executes the ATS process (or the ATS+PRI process) (step S317).

The DMAC43executes a process of step S318using an HPA obtained in the ATS process (or the ATS+PRI process) executed at step S317. The process executed at step S318is the same as the process executed at step S218described inFIG.8. The FE then moves to an interrupt transmission process.

In the interrupt transmission process, the FE issues a transmission request for transmitting an interrupt message to the memory22, using a GPA corresponding to a memory location where the interrupt message is to be transmitted (step S319).

When a cache miss occurs in the ATC441in the ATC search process that searches for address translation information corresponding to the GPA included in this transmission request, the virtual address translation control unit423executes the ATS process (or the ATS+PRI process) (step S320).

The DMAC43executes a process of step S321using an HPA obtained in the ATS process (or the ATS+PRI process) executed at step S320. The process executed at step S321is the same as the process executed at step S222described inFIG.8.

Next, a command process for a read command in a case where the ATS translation process fails will be described.FIG.10is a sequence diagram illustrating a third example of a procedure of a command process for a read command, which is executed in the memory system according to the embodiment.

In a command fetch process, the controller4executes processes from step S401to step S402. The processes from step S401to step S402are the same as the processes from step S201to S202described inFIG.8. When a cache miss occurs in the ATC441at step S402, the virtual address translation control unit423executes a process of step S403. The process executed at step S403is the same as the process executed at step S303described inFIG.9.

When receiving an ATS translation request from the controller4, the host2searches the address translation protection table215for address translation information corresponding to the GPA specified by the ATS translation request. Here, a case in which the host2is unable to obtain the address translation information corresponding to the specified GPA is assumed. In this case, the host2transmits, to the controller4, an ATS completion response including a status indicating failure of the ATS translation process. Therefore, the virtual address translation control unit423receives, from the host2, the ATS completion response including the status indicating the failure of the ATS translation process (step S404).

The virtual address translation control unit423transmits, to the host2, a page request for requesting preparation of the address translation information (step S405). The host2, which has received the page request, starts the process of preparing the address translation information corresponding to the GPA specified in the page request, in the address translation protection table215. When the process of preparing the address translation information in the address translation protection table215is completed, the host2transmits, to the virtual address translation control unit423, a page request group response, which is a response indicating that the preparation of the address translation information is completed.

The virtual address translation control unit423receives the page request group response (step S406).

When receiving the page request group response, the virtual address translation control unit423transmits the ATS translation request to the host2again (step S407). The ATS translation request transmitted at step S407specifies the same GPA as that specified by the ATS translation request transmitted at step S403. The host2, which has received the ATS translation request, searches the address translation protection table215and obtains the address translation information corresponding to the specified GPA. The host2transmits, to the virtual address translation control unit423of the controller4, an ATS completion response that includes the obtained address translation information and the status indicating the success of the ATS translation process.

The virtual address translation control unit423receives the ATS completion response from the host2(step S408).

Since the ATS translation process has succeeded, the virtual address translation control unit423stores the address translation information included in the received ATS completion response, in the ATC441(step S409).

The virtual address translation control unit423translates the GPA to an HPA using this address translation information (step S410). The processes from step S402to step S410are collectively referred to as an ATS+PRI process.

Thus, in the ATS+PRI process, in addition to the ATS process, a process of transmitting a page request to the host2and a process of transmitting the ATS translation request again to the host2after a page request group response is received from the host2are executed.

After the ATS+PRI process is completed, the controller4executes processes from step S411to step S412. The processes from step S411to step S412are the same as the processes from step S307to S308described inFIG.9.

The subsequent processes from step S413to step S425are the same as the processes from step S309to step S321described inFIG.9. In each of step S414, step S418, step S421, and step S424, if the ATS translation process fails, then the ATS+PRI process is executed.

Next, a process of notifying the FE and the BE of a status of the address translation process from the virtual address translation control unit423will be described.FIG.11is a sequence diagram illustrating a procedure of an address translation process executed in the memory system according to the embodiment. InFIG.11, a case in which the ATS+PRI process is executed in the address translation process is assumed.

In each of the command fetch process, the data transfer process, the completion response transfer process, and the interrupt transmission process, the controller4executes the following processes.

The FE of the controller4issues each of various requests (e.g., command fetch requests, PRP list fetch requests, data transfer requests, completion response transfer requests, and interrupt message transmission requests) using a GPA (step S501).

The virtual address translation control unit423searches the ATC441for address translation information corresponding to the GPA included in each of the various requests received from the FE (step S502). When a cache miss occurs in the ATC441, the virtual address translation control unit423transmits, to the host2, an ATS translation request specifying the GPA (step S503).

After transmitting the ATS translation request, the virtual address translation control unit423notifies at least one of the FE and the BE of the controller4that a cache miss has occurred in the ATC441, as a result of the ATC search (step S504).

Then, when receiving an ATS completion response including a status indicating failure from the host2(step S505), the virtual address translation control unit423notifies at least one of the FE and the BE that the ATS translation process has failed, as a result of the ATS translation request (step S506).

After receiving, from the host2, the ATS completion response including the status indicating failure, the virtual address translation control unit423transmits a page request to the host2(step S507).

When receiving a page request group response from the host2(step S508), the virtual address translation control unit423notifies at least one of the FE and the BE of the controller4that the preparation of the address translation information has been completed, as a result of the page request (step S509).

Then, the virtual address translation control unit423transmits the ATS translation request to the host2again (step S510). The host2, which has received the ATS translation request, obtains, from the address translation protection table215, the address translation information corresponding to the specified GPA. The host2transmits, to the virtual address translation control unit423, an ATS completion response including the obtained address translation information and a status indicating success.

When receiving the ATS completion response from the host2(step S511), the virtual address translation control unit423notifies at least one of the FE and the BE of the controller4that the ATS translation process has succeeded, as a result of the ATS translation request (step S512).

The virtual address translation control unit423stores the address translation information included in the received ATS completion response, in the ATC441(step S513) and translates the GPA to an HPA using this address translation information (step S514).

Then, the command fetch unit421or the DMAC43transmits a memory access request (DMA read/write request) to the host2, using the HPA translated by the virtual address translation control unit423(step S515).

Thus, by using a mechanism of notifying at least one of the FE and the BE, of the status of the address translation process from the virtual address translation control unit423, the controller4can recognize the status of the address translation process.

Note that, inFIG.11, at step S503and step S504, a case in which the virtual address translation control unit423notifies the ATC search result after issuing the ATS translation request is described. However, the virtual address translation control unit423may notify the ATC search result at the same time or before issuing the ATS translation request. Also, at step S506and step S507, a case in which a page request is transmitted after notifying the result of the ATS translation request is described. However, the virtual address translation control unit423may issue the page request at the same time or before notifying the result of the ATS translation request. Also, at step S509and step S510, a case in which the virtual address translation control unit423transmits the ATS translation request again after notifying the result of the page request is described. However, the virtual address translation control unit423may notify the result of the page request at the same time or after the ATS translation request is transmitted again.

Next, an operation of suspending a command process corresponding to a read command on the basis of the status of the address translation process in the data transfer process will be described.FIG.12is a sequence diagram illustrating an example of a procedure of an operation of suspending a command process of reading data from the nonvolatile memory, the operation of suspending being executed in the memory system according to the embodiment.FIG.12illustrates a case in which failure of the ATS translation process in the data transfer process is used as a trigger to suspend the command process.

The FE obtains a read command from the host2by executing the command fetch process described inFIG.8,FIG.9, orFIG.10(step S601).

The FE requests the BE to execute a data read operation for reading read target data from the NAND memory5(step S602). The read target data is data specified by the obtained read command.

The BE starts the data read operation to execute a command process corresponding to the obtained read command (step S603). In the data read operation, the BE first transmits, to the NAND memory5, a sense instruction for causing the NAND memory5to execute a sense operation of transferring at least part of the read target data from the memory cell array51to the page buffer52. The BE waits until the sense operation in the NAND memory5is completed. When the sense operation in the NAND memory5is completed, the BE transmits, to the NAND memory5, one or more data-out instructions for causing the NAND memory5to execute one or more data-out operations. When all the data stored in the page buffer52has been transferred to the controller4by the one or more data-out operations, the BE transmits, to the NAND memory5, another sense instruction for causing the NAND memory5to execute another sense operation of transferring at least part of remaining data of the read target data from the memory cell array51to the page buffer52. Thus, in the data read operation, the BE transmits, to the NAND memory5, a plurality of instructions necessary for reading the read target data (i.e., a plurality of sense instructions and a plurality of data-out instructions).

After requesting the BE to execute the data read operation, the FE issues a fetch request for a PRP list, using a GPA included in the PRP entry field of the obtained read command (step S604). The FE passes the issued fetch request to the virtual address translation control unit423.

The virtual address translation control unit423searches the ATC441for address translation information corresponding to the GPA included in the fetch request received from the FE (step S605).

When a cache miss occurs in the ATC441, the virtual address translation control unit423transmits, to the host2, an ATS translation request specifying the GPA included in the fetch request (step S606).

When receiving an ATS completion response including a status indicating failure from the host2(step S607), the virtual address translation control unit423notifies the BE that the ATS translation process has failed, as a result of the ATS translation request (step S608).

When notified that the ATS translation process has failed, the BE suspends the command process corresponding to the read command by temporarily stopping the data read operation in progress (step S609). At step S609, for example, the BE temporarily stops a process of transmitting each of instructions to the NAND memory5, the instructions being one or more instructions that have not yet been transmitted to the NAND memory5among the plurality of instructions necessary for reading the read target data specified by the obtained read command.

At this time, when there is another read command received from the host2, the BE may switch an operation to be executed to a data read operation corresponding to said another read command (step S610), and may execute the data read operation corresponding to said another read command (step S611). This allows the BE to execute the data read operation corresponding to said another read command in preference to the read command for which the ATS translation process has failed.

Then, after notifying the BE of the result of the ATS translation request at step S608, the virtual address translation control unit423transmits, to the host2, a page request for requesting the preparation of address translation information (step S612). The host2, which has received the page request, starts the process of preparing the address translation information. When the process of preparing the address translation information is completed, the host2transmits, to the virtual address translation control unit423, a page request group response, which is a response indicating that the preparation of the address translation information is completed.

When receiving the page request group response from the host2(step S613), the virtual address translation control unit423transmits the ATS translation request to the host2again (step S614). This ATS translation request specifies the same GPA as the GPA specified in the ATS translation request transmitted at step S606. The host2, which has received the ATS translation request, searches the address translation protection table215to obtain the address translation information corresponding to the specified GPA. The host2transmits, to the virtual address translation control unit423of the controller4, an ATS completion response including the obtained address translation information and a status indicating success.

When receiving the ATS completion response including the address translation information and the status indicating success from the host2(step S615), the virtual address translation control unit423notifies the BE that the ATS translation process has succeeded, as a result of the ATS translation request (step S616).

The BE, which has received the notification, resumes the suspended command process by resuming the data read operation that was temporarily stopped at step S609(step S617). At step S617, the BE starts a process of transmitting, to the NAND memory5, the one or more instructions that have not yet been transmitted to the NAND memory5among the plurality of instructions necessary for reading the read target data corresponding to the suspended read command from the NAND memory5.

The virtual address translation control unit423stores the address translation information included in the ATS completion response received at step S615in the ATC441(step S618).

The virtual address translation control unit423translates the GPA to an HPA using this address translation information (step S619).

The command fetch unit421fetches the PRP list from the memory22using the HPA translated by the virtual address translation control unit423(step S620). At step S620, the command fetch unit421transmits, to the RC23of the host2, a DMA read request that includes the HPA translated by the virtual address translation control unit423. On the basis of the HPA included in the DMA read request received from the controller4, the RC23reads the PRP list from the memory22, and transmits the read PRP list to the controller4. The FE thus receives the PRP list from the host2(step S621).

In the data transfer process, in a case where the ATS translation process fails, it takes a longer time to obtain the address translation information than in a case where the ATS translation process succeeds. Therefore, by suspending the command process in response to the failure of the ATS translation process, it is possible to minimize a memory region in the internal buffer62that is occupied by read data that cannot be transmitted to the host2. As a result, it is capable of mitigating a degradation in the performance of the I/O process of the SSD3. In addition, by suspending the command process, a peak value of the data traffic between the controller4and the NAND memory5can be lowered. Therefore, a peak value of the power consumption of each of the NAND memory5and the controller4can also be lowered.

Here, a case in which the BE temporarily stops the command process according to the result indicated by the ATS completion response received at step S607is described. However, instead of the ATS completion response, the occurrence of cache miss at step S605may also be used as a trigger to temporarily stop the command process.

In a case where a cache miss has occurred in the ATC441in the data transfer process, it takes a longer time to obtain the address translation information than in a case where a cache hit occurs in the ATC441. Therefore, by suspending the command process in response to the occurrence of the cache miss, a memory region in the internal buffer62that is occupied by read data that cannot be transmitted to the host2can be minimized.

Also, here, a case in which the BE resumes the command process in response to receiving the ATS completion response at step S615is described. However, instead of the ATS completion response, the reception of the page request group response at step S613may also be used as a trigger to resume the command process.

Also, here, a case in which the failure of the ATS translation process to translate the GPA corresponding to the memory location where the PRP list is stored is used as a trigger to suspend the command process is described. However, even after the PRP list has been obtained, the address translation process is performed in order to translate each of the GPAs included in the PRP list to an HPA. Even in a case where the ATS translation process fails in this address translation process, the command process may also be suspended.

In this manner, the command process may be suspended when the obtainment of the address translation information fails in either the ATS translation process of translating a GPA corresponding to a memory location where a PRP list is stored to an HPA or the ATS translation process of translating each of the GPAs included in the PRP list to an HPA.

Furthermore, in some cases, the PRP entry field included in the read command does not indicate a PRP list, however, indicates a GPA corresponding to a memory location to which the read data is to be transferred. In this case, the controller4may execute the address translation process that translates the GPA corresponding to the memory location to which the read data is to be transferred to an HPA, in parallel with the command process corresponding to the read command. In this case, when the ATS translation process fails in this address translation process, the controller4suspends the command process. Then, in response to receiving a page request group response from the host2or an ATS completion response indicating success from the host2, the controller4resumes the command process.

Next, an operation of controlling a command fetch operation on the basis of the status of the address translation process in the completion response transfer process will be described.FIG.13is a sequence diagram illustrating a first example of a procedure of controlling a command fetch operation, the procedure being executed in the memory system according to the embodiment. InFIG.13, a case in which the command fetch operation is suspended in response to the failure of the ATS translation process in the completion response transfer process is assumed. This completion response transfer process may be a process of transmitting a completion response indicating completion of a read command or a process of transmitting a completion response indicating completion of a write command.

First, the FE issues a transfer request for transferring a completion response of a completed I/O command to the memory22, using a GPA corresponding to a next free completion queue (CQ) slot in a CQ where the completion response of the completed I/O command is to be stored (step S701). The FE passes the issued transfer request to the virtual address translation control unit423.

The virtual address translation control unit423searches the ATC441for address translation information corresponding to the GPA included in the transfer request (step S702).

When a cache miss has occurs in the ATC441, the virtual address translation control unit423transmits, to the host2, an ATS translation request specifying the GPA (step S703).

When receiving, from the host2, an ATS completion response including a status indicating failure (step S704), the virtual address translation control unit423notifies the FE that the ATS translation process has failed, as a result of the ATS translation request (step S705).

When notified that the ATS translation process has failed, the FE suspends fetching an I/O command from each of all submission queues (SQ) associated with the completion queue (CQ) in which the completion response of the completed I/O command is to be stored (step S706). This is because a completion response corresponding to each of the I/O commands stored in these submission queues is to be transferred to the completion queue (CQ) to which the completion response included in the transfer request issued at step S701is to be transferred. Therefore, until the address translation information that includes the HPA of a memory page where this completion queue (CQ) exists is prepared in the address translation protection table215, the HPA of none of the slots of this completion queue (CQ) can be obtained. Thus, if an I/O command is fetched from each of these submission queues (SQs), a large number of completion responses that cannot be transmitted to the host2may occupy resources in the controller4. By executing the control illustrated inFIG.13, the resources in the controller4occupied by the completion responses that cannot be transmitted to the host2can be minimized.

Note that the FE may continue executing a process of fetching I/O commands from submission queues (SQ) associated with a completion queue (CQ) other than the completion queues (CQs) to which the completion responses of the completed I/O command is to be transferred.

After notifying the BE of the result of the ATS translation request at step S705, the virtual address translation control unit423transmits, to the host2, a page request for requesting preparation of the address translation information (step S707). The host2, which has received the page request, starts the process of preparing the address translation information. When the process of preparing the address translation information is completed, the host2transmits, to the virtual address translation control unit423, a page request group response, which is a response indicating that the preparation of the address translation information is completed.

When receiving the page request group response from the host2(step S708), the virtual address translation control unit423transmits the ATS translation request to the host2again (step S709). This ATS translation request specifies the same GPA as the GPA specified in the ATS translation request transmitted at step S703. The host2, which has received the ATS translation request, searches the address translation protection table215to obtain the address translation information corresponding to the specified GPA. The host2transmits, to the virtual address translation control unit423of the controller4, an ATS completion response including the acquired address translation information and a status indicating success.

When receiving the ATS completion response including the address translation information and the status indicating success is received from the host2(step S710), the virtual address translation control unit423notifies the FE that the ATS translation process has succeeded, as a result of the ATS translation request (step S711).

The FE, which has received the notification, resumes fetching an I/O command from each of all submission queues (SQ) associated with the CQs in which the completion response to the completed I/O command is to be stored (step S712).

The virtual address translation control unit423stores the address translation information included in the ATS completion response received at step S710in the ATC441(step S713).

The virtual address translation control unit423translates the GPA to an HPA using this address translation information (step S714).

The DMAC43transfers the completion response to the completion queue (CQ) in the memory22using the HPA translated by the virtual address translation control unit423(step S715).

Here, a case in which the FE suspends the command fetch operation according to the result indicated by the ATS completion response received at step S704is described. However, instead of the ATS completion response, the occurrence of cache miss at step S702may also be used as a trigger to suspend the command fetch operation.

Also, here, a case in which the FE resumes the command fetch operation in response to receiving the ATS completion response at step S710is described. However, instead of the ATS completion response, the reception of the page request group response at step S708may also be used as a trigger to resume the command fetch operation.

Next, a procedure of controlling the command fetch operation on the basis of the status of the address translation process in the interrupt transmission process is described.FIG.14is a sequence diagram illustrating a second example of a procedure of controlling the command fetch operation, the procedure being executed in the memory system according to the embodiment. InFIG.14, a case in which the command fetch operation is suspended in response to the failure of the ATS translation process in the interrupt transmission process is assumed. This interrupt transmission process may be a process of transmitting either an interrupt message for notifying the host2that a command completion response for a read command has been stored in a completion queue (CQ), or an interrupt message for notifying the host2that a completion response for a write command has been stored in the completion queue (CQ).

First, the FE issues a transmission request of an interrupt message corresponding to a completion queue (CQ) where a completion response of a completed I/O command is stored, using a GPA corresponding to a memory location in the memory22to which the interrupt message is to be transmitted (step S801). The FE passes the issued transmission request to the virtual address translation control unit423.

The virtual address translation control unit423searches the ATC441for address translation information corresponding to the GPA included in the transmission request (step S802).

When a cache miss occurs in the ATC441, the virtual address translation control unit423transmits, to the host2, an ATS translation request specifying the GPA (step S803).

When receiving an ATS completion response including a status indicating failure from the host2(step S804), the virtual address translation control unit423notifies the FE that the ATS translation process has failed, as a result of the ATS translation request (step S805).

When notified that the ATS translation process has failed, the FE suspends fetching an I/O command from each of all submission queues (SQ) associated with all completion queues (CQ) corresponding to this interrupt message (step S806). This is because an interrupt message corresponding to each of the I/O commands stored in these submission queues is to be transmitted to the memory location in the memory22to which the interrupt message included in the transmission request issued at step S801is to be transmitted. Therefore, if an I/O command is fetched from each of these submission queues (SQ), a large number of interrupt messages that cannot be transmitted to the host2may occupy resources in the controller4. By executing the control illustrated inFIG.14, the resources in the controller4that are occupied by the interrupt messages that cannot be transmitted to the host2can be minimized.

Note that the FE may continue executing a process of fetching I/O commands from submission queues (SQ) associated with a completion queues (CQ) other than the completion queues (CQs) corresponding to this interrupt messages to be transmitted.

After notifying the FE of the result of the ATS translation request at step S805, the virtual address translation control unit423transmits, to the host2, a page request for requesting the preparation of address translation information (step S807). The host2, which has received the page request, starts the process of preparing the address translation information. When the process of preparing the address translation information is completed, the host2transmits, to the virtual address translation control unit423, a page request group response, which is a response indicating that the preparation of the address translation information is completed.

When receiving the page request group response from the host2(step S808), the virtual address translation control unit423transmits the ATS translation request to the host2again (step S809). The ATS translation request specifies the same GPA as the GPA specified in the ATS translation request transmitted at step S803. The host2, which has received the ATS translation request, searches the address translation protection table215and obtains the address translation information corresponding to the specified GPA. The host2transmits, to the virtual address translation control unit423of the controller4, an ATS completion response including the obtained address translation information and a status indicating success.

When receiving the ATS completion response including the address translation information and the status indicating success from the host2(step S810), the virtual address translation control unit423notifies the FE that the ATS translation process has succeeded, as a result of the ATS translation request (step S811).

The FE, which has received the notification, resumes fetching an I/O command from each of all submission queues (SQ) associated with all completion queues (CQ) corresponding to this interrupt message (step S812).

The virtual address translation control unit423stores the address translation information included in the ATS completion response received at step S810in the ATC441(step S813).

The virtual address translation control unit423translates the GPA to an HPA using this address translation information (step S814).

The DMAC43transfers the interrupt message to the memory22using the HPA translated by the virtual address translation control unit423(step S815).

Here, a case in which the FE suspends the command fetch operation according to the result of the ATS completion response received at step S804is described. However, instead of the ATS completion response, the occurrence of the cache miss at step S802may also be used as a trigger to suspend the command fetch operation.

Also, here, a case in which the FE resumes the command fetch operation in response to receiving the ATS completion response at step S810is described. However, instead of the ATS completion response, the reception of the page request group response at step S808may also be used as a trigger to resume the command fetch operation.

Next, a procedure of controlling the command fetch operation in response to receiving an invalidating command is described.FIG.15is a sequence diagram illustrating a procedure of an invalidating process executed in the memory system according to the embodiment.

First, in a case where the address translation information in the address translation protection table215has been changed, the host2transmits, to the controller4, an ATS invalidation request for invalidating old address translation information. This ATS invalidation request specifies a GPA corresponding to address translation information to be invalidated.

When receiving the ATS invalidation request from the host2(step S901), the virtual address translation control unit423identifies an entry in the ATC441corresponding to the GPA specified by the received invalidation request and invalidates the address translation information stored in this entry (step S902).

The virtual address translation control unit423transmits, to the host2, a completion response for the received ATS invalidation request (step S903).

The virtual address translation control unit423notifies the FE of the GPA corresponding to the address translation information invalidated at step S902(step S904).

The FE determines whether or not the notified GPA is a GPA corresponding to a completion queue (CQ). In a case where the notified GPA is a GPA corresponding to any one of the completion queues (CQ), the FE suspends fetching I/O commands from all submission queues (SQ) associated with this completion queue (CQ) until the FE obtains, from the host2, new address translation information for translating the GPA corresponding to this completion queue (CQ) to an HPA (step S905).

Also, in this case, resources in the controller4can be prevented from being occupied by a large number of completion responses that cannot be transmitted to the host2.

As explained above, according to the present embodiment, in response to receiving a read command from the host2, the read command specifying a virtual address in the virtual address space of the host2, the controller4starts a command process of reading, from the NAND memory5, read target data specified by the read command. In addition, the controller4executes an address translation process of translating a GPA, which is the virtual address specified by the read command, to an HPA, which is a physical address for accessing the memory22of the host2. When the address translation process fails, the controller4suspends the command process of reading the read target data from the NAND memory5until the address translation information necessary for the address translation process can be obtained. Then, when the address translation information becomes obtainable, the controller4resumes the command process. By suspending the command process in this manner, it is possible to prevent the internal buffer62from being occupied for a long period of time by read data that cannot be transmitted to the host2. Also, by suspending the command process, it is possible to prevent read data that cannot be transmitted to the host2from being transferred from the NAND memory5to the controller4. This allows a peak value of the data traffic between the NAND memory5and the controller4to be lowered. Therefore, a peak value of power consumption of each of the NAND memory5and the controller4can also be lowered.

Also, in transmitting, to the host2, information (completion response or interrupt message) for notifying the host2of completion of an I/O command, the controller4executes the address translation process. In this address translation process, a process of translating a GPA, which is a virtual address corresponding to a memory location in the memory22of the host2to which the completion response or the interrupt message is to be transferred, to an HPA, which is a physical address for accessing the memory22, is executed.

When this address translation process fails, the controller4suspends the process of fetching an I/O command from each of submission queues associated with a completion queue in which the completion response for this completed I/O command is to be stored until the address translation information necessary for the address translation process becomes obtainable, then, after the address translation information becomes obtainable, resumes the process of fetching the I/O command from each of the submission queues associated with this completion queue. As a result, resources in the controller4can be prevented from being occupied by the completion responses or the interrupt messages that cannot be transmitted to the host2.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel devices and methods described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modification as would fall within the scope and spirit of the inventions.