Patent ID: 12218231

DETAILED DESCRIPTION

FIG.3shows a HEMT transistor50according to an embodiment.

The HEMT transistor50has a general structure similar to the HEMT transistor30ofFIG.2, thus briefly described herein below; the regions thereof have been identified by numbers incremented by50.

The HEMT transistor50comprises a semiconductor body52, here formed by a lower layer54, for example, of gallium nitride (GaN), and an upper layer56, for example, of aluminum gallium nitride (AlGaN). The upper layer56forms a surface52A of the semiconductor body52. In a not shown manner, the semiconductor body52may further comprise a silicon substrate and/or the upper layer56may be a multilayer, including layers of AlGaN with different percentage of aluminum (for example one AlGaN layer with 20% of aluminum and another AlGaN layer with 40%).

A source metallization70and a drain metallization72extend, at a mutual distance, above the body52. Also here, the source70and drain metallizations72comprise lower portions70A,72A and upper portions70B,72B, and are, for example, of aluminum. The source70and drain metallizations72form source and drain electrodes and are electrically coupled to respective source and drain terminals S, D.

A first insulating layer58, for example of silicon nitride, extends above the upper layer56and part of the lower portions70A,72A of the source70and drain metallizations72.

A gate region60, of conductive material, extends above the semiconductor body52and comprises a lower gate portion60A (extending into an opening, called first opening61, of the first insulating layer58, and in direct contact with the upper layer56of the semiconductor body52), an upper gate portion60B, a first intermediate gate portion60C and a second intermediate gate portion60D, arranged between the lower gate portion60A and the upper gate portion60B. Here again, the gate region60may be formed by a stack of materials, for example nickel (Ni), aluminum Al and tungsten nitride (WN) or tantalum nitride (TaN).

The gate region60is electrically coupled to a gate terminal G.

A dielectric layer82, for example of silicon nitride, extends above the first insulating layer58and, partly, within the gate region60. Therefore the dielectric layer82has an opening (also called second opening83) wherein the second intermediate portion60D of the gate region60extends.

A second insulating layer62, for example of silicon nitride, extends above the dielectric layer82and surrounds the upper gate portion60A on the top and laterally. In practice, the second insulating layer62forms, with the first insulating layer58and the dielectric layer82, an insulation structure63sealing the gate region60.

A passivation layer66, for example of silicon oxide, surrounds the upper portions70B,72B of the source and drain metallizations70,72and covers the whole structure.

The transistor50ofFIG.3has a first and a second field plate region84,85, of conductive material such as a metal, for example of aluminum.

The first field plate region84extends above the dielectric layer82, between the gate region60and the drain metallization72, and is covered by the second insulating layer62. In the embodiment shown, the first field plate region84is arranged closer to the gate region60than to the drain metallization72. For example, in the direction in which the source metallization70, the gate region60, the first field plate region84and the drain metallization72are adjacent (direction parallel to a first Cartesian axis X inFIG.3), the first field plate region84may have a width L1depending on the breakdown voltage, for example comprised between 0.1 and 3 μm, for example of 1 μm, and may be arranged at a distance d of 0.1 to 3 μm, for example of 1 μm from the gate region60(the distance d being calculated, approximately, from the edge of the upper gate portion60B facing the first field plate region84).

The first field plate region84may be of a same conductive material, in particular of the same metal layer, and manufactured in the same manufacturing step as the upper gate portion60B, as discussed in detail below with reference toFIGS.6A-6D.

The second field plate region85extends above the second insulating layer62, vertically overlying (with respect to a second Cartesian axis Z) the first field plate region84, and is covered by the passivation layer66. The second field plate region85has a width L2at least equal to, but generally greater than, the width L1of the first field plate region84. For example, the width L2of the second field plate region85may be comprised between 0.1 and 5 μm.

The field plate regions84,85are electrically coupled to the source metallization70, as shown by lines75. In particular, the second field plate region85may be formed together with and using the same metal layer as the upper portions70B and72B of the source and drain regions70,72.

The field plate regions84,85have the effect of modifying the existing electric field and in particular making it more uniform during the operation of the HEMT transistor50. Furthermore, the presence of the first field plate region84allows the gain of the HEMT transistor50to be considerably increased. In fact, in case of an increase in the drain voltage, the first field plate region84, acting as a shield between the gate region60and the drain metallization72, has the effect of decreasing the gate-drain capacity to which the gain is inversely related, as discussed below with reference toFIG.8.

FIG.4shows a different embodiment of a HEMT transistor, here indicated with100.

The HEMT transistor100has a general structure similar to the HEMT transistor50ofFIG.3. The common parts have thus been provided with the same reference numbers and will not be further described.

In the HEMT transistor100, the first field plate region, here indicated with84′, comprises a lower plate portion84A′ and an upper plate portion84B′.

The upper plate portion84B′ of the first field plate region84′ roughly corresponds to the first field plate region84ofFIG.3, and thus extends above the second insulating layer62, laterally to the gate region60, between the same and the drain metallization72. The lower plate portion84A′ of the first field plate region84′ extends continuously from the upper plate portion84B′ towards the surface52A of the semiconductor body52through an opening (called third opening86) of the dielectric layer, here indicated with82′, and, partially, through the first insulating layer, here indicated with58′, in a cavity87thereof. The lower plate portion84A′, however, does not completely extend through the first insulating layer58′ and a thinner portion thereof, below referred to as thinned portion58A′, extends between the surface52A of the semiconductor body52and the first field plate region84′, electrically separating the latter from the semiconductor body52.

This embodiment is characterized by a marked increase in gain and a particularly uniform electric field, as discussed below with reference toFIG.8.

FIG.5shows another embodiment of a HEMT transistor, here indicated with150.

The HEMT transistor150has a general structure similar to the HEMT transistor50ofFIG.3, except for the shape of the gate region (similar to the HEMT transistor1ofFIG.1). The parts in common with the HEMT transistor50ofFIG.3have thus been provided with the same reference numbers and will not be further described.

In detail, the HEMT transistor150comprises a gate region60″ having a lower gate portion60A″ and an upper gate portion60B″. Furthermore, the HEMT transistor150comprises a first insulating layer, indicated with58″ and having an opening61″ accommodating the lower gate portion60A″, and a first field plate region84″. The first field plate region84″ extends above the insulating layer58″ and is coated, laterally and on the top, by the second insulating layer62.

In this embodiment, the lower gate portion60A″ and the upper gate portion60B″ may be formed by a single deposited (for example “sputtered”) metal layer or a single evaporated layer or by a stack of layers deposited separately. In the latter case, the first field plate region84″ may be formed with one of the layers of the gate region60″.

Here again, the second field plate region85extends vertically (in direction of the second Cartesian axis Z) above the first field plate region84″.

This embodiment allows a simplification of the manufacturing process, due to the simple shape of the gate region60″.

The manufacturing process of the HEMT transistors50and100ofFIGS.3and4will now be described, with reference toFIGS.6A-6Dand, respectively,7A-7D.FIG.6Ashows a cross-section similar toFIG.3in an intermediate manufacturing step of the HEMT transistor50.

In particular,FIG.6Ashows an intermediate structure, wherein, above the semiconductor body52, the lower portion70A of the source metallization70, the lower portion72A of the drain metallization72, and the first insulating layer58have already been formed in a per se known manner; furthermore, the first insulating layer58has been etched to form the first opening61; the lower gate portion60A in the first opening61and the first intermediate gate portion60C above the lower gate portion60A have been formed (for example, the lower gate portion60A and the first intermediate gate portion60C may be formed simultaneously, by physical vapor deposition (PVD) of a nickel layer within a cavity formed in a temporary structure and having a small-sized opening, related to the area of the first intermediate gate portion60C) and, after removing the temporary structure, the dielectric layer82has been deposited, for example by PECVD deposition.

Next,FIG.6B, a portion of the dielectric layer82is removed, for example by dry etching, above the first intermediate gate portion60C, forming the second opening83.

Then,FIG.6C, two sputtering processes are carried out in succession; in particular a first sputtering process, of tungsten nitride (WN) or tantalum nitride (TaN), forms a first metal layer, which is thinner, fills the second opening83and is intended to subsequently form the second intermediate gate portion60D, and a second sputtering process, for example of aluminum, forms a second metal layer which is thicker. The layer formed of the first and second metal layers is indicated with200inFIG.6C. Alternatively, a sequence of sputtered metal layers, including tungsten nitride/aluminium/titanium nitride WN/Al/TiN may be used.

Next,FIG.6D, for example using a resist mask not shown, portions of the metal layer200(also called gate metal layer) are selectively removed, forming the second intermediate gate portion60D and the upper portion60B of the gate region60, as well as the first field plate region84.

Known steps follow, including deposition of the second insulating layer62, deposition of a third metal layer, for example aluminum based (such as an Al, AlSiCu or AlCu bi-layer and a Ti, TiN metal layer) by sputtering and subsequent selective removal to form the upper portions70B and72B of the source and drain metallizations70,72and the second field plate region85. Finally the deposition of the passivation layer66follows.

In this way, the first field plate region84may be formed without adding process steps with respect to the manufacturing process of the HEMT transistor30ofFIG.2, only through an etching mask modification of the gate metal layer200, and thus without additional costs.

FIG.7Ashows a cross-section similar toFIG.4in an intermediate manufacturing step of the HEMT transistor100.

In particular,FIG.7Ashows an intermediate structure wherein, above the semiconductor body52, the lower portion70A of the source metallization70, the lower portion72A of the drain metallization72and the first insulating layer58′ have already been formed, in a per se known manner; furthermore, the first insulating layer58′ has already been etched to form the first opening61, the lower gate portion60A in the first opening61and the first intermediate gate portion60C above the lower gate portion60A have already been formed (for example, the lower gate portion60A and the first intermediate gate portion60C may be formed as described above for the HEMT transistor50) and the dielectric layer82′ has been deposited, for example by PECVD deposition. The intermediate structure ofFIG.7Ais thus identical to that ofFIG.6A.

Next,FIG.7B, a portion of the dielectric layer82′ is removed above the first intermediate gate portion60C, forming the second opening83. Furthermore, a portion of the dielectric layer82′ and the underlying portion of the first insulating layer58′ are selectively removed, laterally to the second opening83, where it is desired to form the first field plate region84′, forming the third opening86.

Then,FIG.7C, a gate metal layer200′ is deposited, for example in the manner described above with reference toFIG.6C, carrying out in succession a first sputtering process, of tungsten nitride (WN) or tantalum nitride (TaN), to form a first metal layer (which is thinner and intended to subsequently form the second intermediate gate portion60D and the lower portion84A of the first field plate region84) and a second sputtering process, for example of aluminum, to form a second metal layer, which is thicker.

Next,FIG.7D, for example using a resist mask not shown, portions of the gate metal layer200′ are selectively removed, completing the gate region60′ and the first field plate region84′.

Known steps follow, including deposition of the second insulating layer62, deposition of a third metal layer, for example aluminium-based (as indicated above) by sputtering and subsequent selective removal to form the upper portions70B and72B of the source and drain metallizations70,72and the second field plate region85. Finally, the deposition of the passivation layer66follows.

Also in this case, the first field plate region84may be formed without adding process steps with respect to the manufacturing process of the HEMT transistor30ofFIG.2, through an etching mask modification of the gate metal layer200′, and thus without additional costs.

Similarly, the manufacturing process of the HEMT transistor150does not require additional steps with respect to those foreseen for forming the HEMT transistor1ofFIG.1, and in some embodiments, only some modifications of the mask may be used to define the gate region60″ in order to form the first field plate region84″. The HEMT device shown inFIGS.3-5has many advantages. As indicated, due to the presence of an additional shielding region (first field plate region84,84′,84″), the HEMT device described has a high gain, as shown inFIG.8.

In particular,FIG.8shows the result of simulations carried out by the Applicant relative to the plot of the gain G obtainable with the HEMT transistor as a function of the frequency fin the range 2-10 GHz, for the HEMT transistor1ofFIG.1(curve A), the HEMT transistor30ofFIG.2(curve B), the HEMT transistor50ofFIG.3(curve C) and the HEMT transistor100ofFIG.4(curve D), respectively. As visible, the HEMT transistors50and100have a considerably greater gain with respect to the similar structures lacking the first field plate region84,84′.

In a not shown manner, the HEMT device shown inFIGS.3-5allows a not negligible improvement to be obtained also as regards electric field uniformity and thus its robustness at high voltages.

Finally, it is clear that modifications and variations may be made to the HEMT transistor and the manufacturing process thereof described and illustrated herein without thereby departing from the scope of the present disclosure. For example, the different embodiments described may be combined so as to provide further solutions.

For example, the second field plate85and the first field plate84,84′,84″ may be connected in various ways to the source metallization70; the first field plate84″ and the gate region60″ inFIG.5may be positioned in different ways with respect to the insulating layer58″; and the gate region60″ inFIG.5may be defined in different ways, as discussed in detail hereinafter.

Connection of the Second Field Plate85:

The second field plate85may be connected to the source metallization70through connecting regions extending either over an active area (where the 2-dimensional electron gas—2 deg— forms a channel region of the HEMT transistor and conducts current) or an inactive area surrounding the active area, as explained below.

For example,FIG.9shows an embodiment where the HEMT transistor150ofFIG.5has the second field plate85connected to the source metallization70through a connecting portion formed in the third metal layer which also forms the upper portion70B of the source metallization70, the upper portion72B of the drain metallization72and the second field plate region85, and thus defined in the same etching step.

In particular, inFIG.9, a biasing metal portion88of the third metal layer extends on the second insulating layer62between the upper portion70B of the source metallization70and the second field plate region85and forms a single region with them.

According to a different embodiment, the second field plate85is connected to the source metallization70through a connecting region extending over the inactive area of the HEMT transistor150, as described hereinbelow with reference toFIG.10, which shows the structure of an elementary cell of the HEMT transistor150ofFIG.5in a plan view.

It is intended that the HEMT transistor150may comprise a plurality of elementary cells, each having at least one source metallization70, at least one drain metallization72, at least one first field plate84, and at least one second field plate85, extending as fingers along a direction (vertical direction ofFIG.10).

FIG.10shows a portion of an intermediate structure of the HEMT transistor150after depositing and defining the second insulating layer62(not visible inFIG.10) and depositing and defining a third metal layer, indicated by98, to form the upper portions70B and72B of the source and drain metallizations70,72and the second field plate region85. In particular,FIG.10shows the active area90(which accommodates high mobility conduction electrons of the 2-deg), surrounded by the inactive area91, not participating to the conduction action. The inactive area91is generally doped, to avoid passage of current when the HEMT transistor150is switched off.

InFIG.10, line93indicates the boundary of the active area90.

Here, the third metal layer98is also defined to form a second field plate connecting region97extending over the inactive area91between the upper portion70B of the source metallization70and the second field plate region85, thereby connecting them electrically.

According to a different embodiment,FIG.11, the second field plate85is connected to the source metallization70through a plurality of clips or bridge portions105extending at a distance to each other over the active area90and formed by the second metal layer200″. In this case, in a cross-section, the clips105are not visible (as inFIG.5) or have a shape similar to the biasing metal portion88ofFIG.9, depending on whether the cross section through the HEMT transistor150is drawn in an area between two adjacent clips105or crosses one of the clips105.

According to still another embodiment, the second field plate85is connected to the source metallization70by both the second field plate connecting region ofFIG.10and the clips105ofFIG.11.

Connection of the First Field Plate84,84′,84″:

The first field plate84,84′,84″_may be connected to the source metallization70through connecting regions extending over the inactive area91or through the second field plate85, as explained below.

For example, the first field plate84,84′,84″ may be connected to the source metallization70as shown inFIGS.12A-12C, which show the structure of an elementary cell of the HEMT transistor150ofFIG.5in three intermediate manufacturing steps (connection over the inactive area91).

Also here, the HEMT transistor150may comprise a plurality of elementary cells, each having at least one source metallization70, at least one drain metallization72, at least one first field plate84, and at least one second field plate85, extending as fingers along a direction (vertical direction ofFIGS.12A-12C).

FIG.12Ashows a portion of the intermediate structure of the HEMT transistor150after forming the lower portions70A,72A of the source and drain metallizations70,72, and after forming and defining the insulating layer58″ (FIG.5).

InFIG.12A, the lower portions70A,72A of the source70and drain metallizations72extend mainly on the active area90and have ends portions70A1,72A1extending on the inactive area91. Line93indicates the boundary of the active area90; line94indicates the boundary of insulating layer58″ (not visible) and line95indicates the first opening (61″ inFIG.5).

FIG.12Bshows the same portion of the intermediate structure of the HEMT transistor150after depositing and defining a metal layer (similar to gate metal layer200′ ofFIG.7C), so as to form the gate region60″, the first field plate84″ and a first connecting region96. The first connecting region96is integral with and in prosecution of the first field plate84″, extends from and end of the first field plate84″ onto the inactive area91and ends with an enlarged portion96A.

FIG.12Cshows the same portion ofFIGS.12A and12Bafter depositing and defining the second insulating layer62(not visible inFIG.12C) and depositing and defining the third metal layer, indicated again by98, to form the upper portions70B and72B of the source and drain metallizations70,72and the second field plate region85.

InFIG.12C, the second insulating layer62(FIG.5) has been defined to form a through opening99over the enlarged portion96A of the first connecting region96.

Here, the third metal layer98also extends over the inactive region91and in particular over the enlarged portion96A and fills the through opening99to form a connection via (indicated by the same number99since it has the same shape as the through opening). The connection via99electrically connects the upper portion70B of the source metallization70to the enlarged portion96A of the first connecting region96(at a lower level) and thus to the first field plate84″.

Here, in addition, the third metal layer98is also defined to form the second field plate connecting region97extending over the inactive area91between the upper portion70B of the source metallization70and the second field plate region85.

Therefore, the first connecting region96, the connection via99and the second connecting region97form line75ofFIG.3, directly connecting the source metallization70, the first field plate84″ and the second field plate region85.

According to a different embodiment, the first field plate84,84′,84″ may be connected to the source metallization70through the second field plate85, as shown inFIG.13.

In detail, inFIG.13, the second insulating layer62has a through opening, called field plate connection opening89, extending over the first field plate84″. Thereby, during deposition of the third metal layer98, the metal enters and fills the field plate connection opening89, forming a field plate via also indicated by89(since it has the same shape and is defined by the field plate connection opening89). The field plate connection via89electrically connects the first field plate84″ to the second field plate region85and thus, through one of the solutions discussed above in section Connection of the second field plate85, to the source metallization70.

According to another embodiment, the first field plate84,84′,84″ may be connected to the source metallization70both over the inactive area91(through the first connecting region96, the enlarged portion96A, and the connection via99,FIGS.12A-12C) and over the active area90(through the field plate connection via89,FIG.13), combining the solutions ofFIGS.12A-12CandFIG.13.

Arrangement of the First Field Plate84″:

The first field plate84″ may be arranged in different ways with respect to the insulating layer58″.

In particular, as an alternative to the arrangement shown inFIG.5, where the first field plate84″ is formed completely over the insulating layer58″, the first field plate84″ may be formed with its lower portion inside the insulating layer58″, as shown inFIG.14.

In this case, process steps similar to those described with reference toFIGS.7B-7Dare performed. In particular, after depositing the insulating layer58″, the first opening61and, in a separate etching step, a cavity87′ (corresponding to the third opening86and the cavity87ofFIG.4) are formed. Then, the gate metal layer (analogous to gate metal layer200″ ofFIG.7C) is deposited and defined to form the gate region60″ and the first field plate region84″. Thereafter, the second insulating layer62and the third metal layer are deposited and defined and covered by the passivation layer66.

According to a different embodiment, the first field plate84″ may be formed to contact the semiconductor body52. In this case, the insulating layer58″ may be removed only partially, as shown inFIG.15.

In detail, inFIG.15, the third opening in the insulating layer58″ (here, indicated by86′) is a through opening, so that the bottom portion of the first field region4″ directly contacts the semiconductor body52.

Arrangement of the Gate Region60″:

The gate region60″ may extend directly on and physical in contact with the semiconductor body52, as shown inFIGS.9,12,13-15or may enter a recess in the semiconductor body52, as shown inFIG.16.

InFIG.16, a lower gate portion60A″ of the gate60″ extends through part of the upper layer56of the semiconductor body52in a recess79.

This solution may be used when the first field plate84″ is in direct contact with the semiconductor body52.

Definition of Gate Region60″ and First Field Plate84″:

The gate region60″ and the first field plate84″ may be defined through known masking and etching steps, in which case the insulating layer58″ is slightly recessed as a consequence of the etching process, as shown inFIGS.9,13-17or using a lift-off process. In this case, as shown inFIG.17, the insulating layer58″ has a planar upper surface, not recessed.

The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.