Patent ID: 12261132

DETAILED DESCRIPTION

Embodiments describe chip sealing structures and methods of manufacture. In an embodiment, a chip structure includes a main body area formed of a substrate (e.g. semiconductor substrate) such as silicon, and a back-end-of-the-line (BEOL) build-up structure spanning over the substrate. Chip edge sidewalls extend from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surround the substrate and the BEOL build-up structure. In accordance with embodiments, a conformal sealing layer covers at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure to form a lip around the top surface of the BEOL build-up structure.

In one aspect, embodiments describe conformal sealing layers that can be used in combination with or replace traditional seal ring structures. The conformal sealing layers in accordance with embodiments may also provide a clamping force on the multi-layer stack, which can facilitate adhesion and sealing properties of the conformal sealing layer. The conformal sealing layers may additionally create an impermeable membrane.

In another aspect, the conformal sealing layers can improve chip area utilization compared to traditional seal ring structures since area commonly reserved for seal ring physical space is removed. For example, traditional seal ring structures consume a significant die area and overall wafer utilization, particularly for smaller dies. In accordance with embodiment, a sidewall sealing layer allows the reduction of area allocated to the traditional seal ring, thereby increasing the total number of chips that can be harvested per wafer. Additionally, the buffer distance from the chip edge sidewalls can be reduced by replacing high stress-generating mechanical dicing processes such as blade sawing with lower stress processes. In this aspect, embodiments describe programmable dicing techniques. For example, this may include laser assisted chemical etch dicing flows to carve out specific die-set areas, which can also be irregularly shaped. Chemical etching may be wet etch or plasma etch, particularly if the substrate, such as a semiconductor wafer (silicon), is deep (e.g. more than 50 μm). An exemplary plasma dicing process may be, or include, a deep reactive-ion etching (DRIE) process. Such programmable dicing techniques can facilitate harvesting of arrayed structures. Furthermore, such programmable dicing techniques can facilitate dicing through non-conventional FEOL die areas. Furthermore, such dicing techniques can be used to dice BEOL structures with very fragile materials (e.g. dielectrics with low dielectric constants, low-k materials) which could otherwise be damaged by high stress processes. Additionally, the sealing layers described herein can provide added protection against processing stresses as well as sealing in the case the fragile layers are compromised.

In various embodiments, description is made with reference to figures. However, certain embodiments may be practiced without one or more of these specific details, or in combination with other known methods and configurations. In the following description, numerous specific details are set forth, such as specific configurations, dimensions and processes, etc., in order to provide a thorough understanding of the embodiments. In other instances, well-known semiconductor processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the embodiments. Reference throughout this specification to “one embodiment” means that a particular feature, structure, configuration, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments.

The terms “above”, “over”, “to”, “between”, “spanning” and “on” as used herein may refer to a relative position of one layer with respect to other layers. One layer “above”, “over”, “spanning” or “on” another layer or in “contact” with another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers.

Referring now toFIG.1a cross-sectional side view illustration is provided of a chip structure100in accordance with an embodiment. As shown, the chip structure100can include a main body area105formed of a multi-layered stack including a substrate101, a first front-end-of-the line (FEOL) die area104of a first die106patterned into the substrate101, a back-end-of-the-line (BEOL) build-up structure110spanning over the first FEOL die area104, and chip edge sidewalls115extending from a back surface102of the substrate101to a top surface116of the BEOL build-up structure110and laterally surrounding the first FEOL die area104and the BEOL build-up structure110. In accordance with embodiments, a conformal sealing layer130covers at least a first chip edge sidewall of the chip edge sidewalls115and a portion of the top surface116of the BEOL build-up structure110such that the conformal sealing layer130forms a lip134around the top surface116of the BEOL build-up structure110.

In accordance with some embodiments, the conformal sealing layer130material(s) may be selected to form a compressive stress to the main body area105. This can be vertical stress and/or horizontal stress. The compressive stress can help clamp the conformal sealing layer130onto the main body area and promote adhesion. Compressive stress may provide additional protection from mechanical stressors such as cracks. The conformal sealing layer130may have a sufficiently high Young's modulus, yield stress, and fracture toughness to protect against mechanical stressors. In an embodiment, the substrate101is a silicon substrate or silicon on insulator (SOI) substrate. The conformal sealing layer130may possess strong adhesion to silicon, and not diffuse substantially into silicon to adversely affect device performance. In an embodiment, the conformal sealing layer130has a Young's Modulus greater than silicon such as greater than 170 GPa, or more specifically 300-550 GPa, such as 300-400 GPa, and a coefficient of thermal expansion (CTE) greater than the substrate (e.g. silicon), such as greater than 4 ppm/° C. Compressive stress can also be tailored by deposition parameters. For example, this may be facilitated by a high temperature deposition process in which the deposited material contracts upon cooling, providing compressive stress. In some embodiments, the conformal sealing layer130may be slightly tensile, and still function as an impermeable barrier.

The FEOL die areas104in accordance with embodiments can include the active and passive devices of the dies106. The BEOL build-up structure110is then formed over the substrate101to provide electrical interconnections. The BEOL build-up structure110may conventionally fulfill the connectivity requirements of the die106. The BEOL build-up structure110may be fabricated using conventional materials including metallic wiring layers114and vias113(e.g. copper, aluminum, etc.) and insulating interlayer dielectrics (ILD)111,112such as oxides (e.g. silicon oxide, carbon doped oxides, etc.), nitrides (e.g. silicon nitride), low-k, materials, etc. The BEOL build-up structure110wiring layers114can be formed in lower metal layers M_low, upper metal layers M_high, and midlevel metal layers M_mid. The upper metal layers M_high may have coarser line widths and line spacing, with the midlevel metal layers M_mid having intermediate line widths and spacing, and the lower metal layers M_low having finer line widths and spacing. Additionally, the interlayer dielectrics (ILDs)111for the lower metal and midlevel metal layers may be formed of low_k materials, which can allow quicker moisture transport. Thus, when using the finer wiring layers, additional precautions can be taken in accordance with embodiments, such as passivation of diced chip edge sidewalls115with conformal sealing layer130. The top surface of the BEOL build-up structure110can include exposed contact pads120, such as underbump metallurgy (UBM) pads, and may be connected to the FEOL die areas104.

Up until this point, the description related toFIG.1has focused on a chip structure100including a single FEOL die area104of a single die106. However, embodiments are not so limited and may include multiple dies106and corresponding FEOL die areas104, which can be connected with die-to-die routing within the BEOL build-up structure110. Additionally, other structures such as metallic sealing structures (e.g. full or partial seal rings) can optionally be included within the BEOL build-up structure110. Furthermore, the conformal sealing layer130may be formed on any number of chip edge sidewalls115ranging from selective deposition onto a single chip edge sidewall115or all chip edge sidewalls115. Deposition onto multiple chip edge sidewalls115may further facilitate clamping in the x-y plane (e.g. lateral, horizontal), with the lip134further facilitating clamping in the z-direction (e.g. vertical, along dicing direction).

Referring now toFIGS.2A-2Badditional illustrations are provided of chip structures100with additional features. While illustrated and described separately, the additional features are not necessarily intended to be exclusive of one another, and instead are intended to illustrate flexibility for application of the conformal sealing layer130in accordance with embodiments.

FIG.2Ais a schematic cross-sectional side view illustration of a chip structure100including a conformal sealing layer130along chip edge sidewalls115similar to that illustrated and described with regard toFIG.1with the additional feature of diced die-to-die routing140in accordance with an embodiment. As shown a terminal end141of the die-to-die routing140may be exposed along the chip edge sidewall115, with the conformal sealing layer130being deposited directly on the terminal end141. In the embodiment illustrated, the upper metal layers M_high may be primarily used for die-to-die routing140for lower resistance wiring, and possibly greater flexibility to form chip structures100including custom die sets with dynamic die-to-die routing140after testing. While the chip structure100ofFIG.2Aincludes a single FEOL die area104, with scribed die-to-die routing140, the chip structures100in accordance with embodiments may include a plurality of FEOL die areas104corresponding to separate dies106connected with die-to-die routing140. Thus, illustration and description ofFIG.2Ais not intended to be limited to the specific structure illustrated, and instead is intended to illustrate a chip structure100including a conformal sealing layer130deposited along a diced chip edge sidewall115including a diced die-to-die routing140.

Referring now toFIG.2B, a schematic cross-sectional side view illustration is provided of a chip structure100including a metallic sealing structure and conformal sealing layer130along a chip edge sidewall115including diced die-to-die routing140in accordance with an embodiment. Specifically,FIG.2Billustrates a combination of a partial metallic sealing structure152adjacent a first chip edge sidewall115and a full metallic sealing structure150adjacent a second chip edge sidewall115. Full metallic sealing structures150may extend substantially through the BEOL build-up structure from underlying silicon substrate101to upper metal layers M_high and in contact with the top passivation layer to provide an impermeable seal. Partial metallic sealing structures150may include one or more openings within the dielectric layers111,112of the BEOL build-up structure110.

In the illustrated embodiments, the die-to-die routing140extends through an opening155vertically oriented with the partial metallic sealing structure152. Specifically, the opening155is illustrated as being above with partial metallic sealing structure152, though the opening155could also be under, or within the partial metallic sealing structure152. In accordance with embodiments, the die-to-die routing140can extend through multiple openings155within the metallic sealing structure152.

Still referring toFIG.2B, some additional optional features are illustrated to show flexibility of the sealing structure designs in accordance with embodiments. For example, where a full sealing structure150is provided adjacent a chip edge sidewall115, the conformal sealing layer130is optionally not deposited. In the illustrated embodiment, the conformal sealing layer130is selectively deposited along the compromised chip edge sidewall115including the partial metallic sealing structure152. It is to be appreciated that such an embodiment is exemplary, and embodiments are not so limited.

Up until this point, the description and illustrations with regard toFIGS.1-2Bhas been primarily directed to chip structures100including one or more dies106. For example, each die106may include a die area104formed within the substrate101, and overlying BEOL build-up structure. The die area104may include one or more active devices (e.g. transistors for logic function) or passive devices (e.g. capacitors, inductors, resistors, etc.). Accordingly, the term “die” or “die area” as used herein can be inclusive of both active devices and passive devices. Exemplary dies106can include logic, memory, and may combine multiple intellectual property (IP) cores, or single IP cores. For example, the dies106can be system on chip (SOC) dies including multiple IP cores, or smaller chiplets of including one or more partitioned IP cores. In an embodiment, the dies106include arrays of passive devices, such as capacitor arrays, for connection with other electronic components. In an embodiment, the chip structures100described herein do not include a die, and instead can provide discrete routing and/or devices. For example, the chip structures100can be an interfacing bar, or bridge for connecting multiple components.

Referring now toFIG.3Aa schematic cross-sectional side view illustration is provided of a chip structure100including a BEOL build-up structure110spanning over a single FEOL die area104in accordance with an embodiment. The single FEOL die area104may include multiple devices108, such as active device or passive devices. In an embodiment, a plurality of solder bumps109can be provided on the BEOL build-up structure110, for example onto contact pads120, for flip chip connection. However, this is exemplary and embodiments are not so limited.

FIG.3Bis similar to the chip structure100ofFIG.3A, with the inclusion of multiple die areas104, which can be connected by die-to-die routing140in the BEOL build-up structure110. Referring now toFIG.3C, a variation ofFIGS.3A-3Bis illustrated in which the BEOL build-up structure110spans over a plurality of devices108formed in the substrate101.FIG.3Cis merely an alternate illustration of eitherFIG.3AorFIG.3B, where the plurality of devices108can be considered to be in the same die area104, or different die areas104. Thus,FIG.3Cillustrates an exemplary embodiment such as an integrated passive device, where a plurality of devices108such as trench capacitors can be provided in a chiplet structure to be connected with another component. Referring now toFIG.3Dan alternative embodiment is illustrated where the devices108are optionally formed within the BEOL build-up structure110rather than in the underlying substrate101. In such an embodiment, the chip structure100may be an interfacing bar, or bridge, including wiring layers114, and optionally one or more devices108. In an embodiment, the chip structure100does not include a die area104. It is to be appreciated that the chip structures100illustrated inFIGS.3A-3Dcan be combined. For example, devices108can be formed in both the substrate101and BEOL build-up structure100, that may span over one or more die areas.

Turning now toFIG.4andFIGS.5A-5Ga flow chart and schematic cross-sectional side view illustrations are provided for a process of forming a plurality of chip structures including a conformal sealing layer in accordance with an embodiment. In interest of clarity and conciseness, the flow chart provide inFIG.4is described concurrently with the illustrations inFIGS.5A-5G. Furthermore, while the exemplary process flow illustrates the formation of a plurality of chip structures100, each including a single FEOL die area104, that the embodiments are not so limited and may include multi-die set chip structures100with multiple FEOL die areas104, or any of the alternative chip structures described herein.

In accordance with embodiments, the combination of laser dicing and chemical etch dicing, such as plasma dicing, can be used to provide custom harvesting of various arrayed. Such programmable dicing techniques can also be employed to provide additional flexibility into selection of dicing areas, and to support fine dicing with reduced street width or loss of material. In operation, an arrayed wafer including FEOL die areas104and BEOL build-up structure110with complete die-to-die routing can be received and tested for good and bad FOEL die areas104. This information is then used to create a map identifying valid die106sets for chip structures100.

At operation4010a patterning layer, such as a lift-off photoresist or other masking material, is formed over the BEOL build-up structure of a fully built wafer as shown inFIG.5Ausing a suitable method such as spin coating. A dicing tool then retrieves the map and can perform programmable dicing. At operation4020the dicing tool may first form an array of dicing lane grooves162through the patterning layer160and the BEOL build-up structure110as shown inFIG.5B. The dicing lane grooves162may be formed partially or completely through the BEOL build-up structure110to expose the substrate101. Thus, this laser dicing operation may also cut through any die-to-die routing140that may be present in the dicing lanes. Laser cutting through the patterning layer160and BEOL build-up structure110may avoid an additional lithography operation, and can be well defined (e.g. <1 μm edge). At operation4030dicing is then performed through the array of dicing lane openings to form an array of kerfs164partially through the underlying substrate101as shown inFIG.5C. In accordance with embodiments, this operation may be a chemical etch dicing operation such as plasma dicing or wet chemical dicing, using the patterning layer160as an etch mask. The chemical etch dicing operation may additionally define a plurality of main body areas105in the multi-layer stack-up, including what will become the chip edge sidewalls115. Such programmable dicing techniques as described with operations4020-4030can be used to achieve fine dicing, with mitigated material loss. This facilitates integration of dense arrayed structures. Additionally, the programmable dicing techniques are very flexible for shape, size or layout constraints. This allows the freedom to dice chip structures with die sets of any shape. This ability thus allows additional reliability margin improvements to the diced die sets to be realized with programmable dicing in accordance with embodiments.

Referring now toFIG.5Dopenings166in the patterning layer160that overlie the array kerfs164are widened. For example, the openings previously corresponding to formation of the dicing lane grooves162and subsequent kerfs164are further widened within the patterning layer160. This may correspond to a resist pull-back operation in which lithography is used to pattern the opening166. This is followed with operation4040in which a conformal sealing layer130is deposited over the patterning layer160, within the array of kerfs164, and partially along the top surface116of the BEOL build-up structure110to form lips134. As shown, the conformal sealing layer130is deposited along the chip edge sidewalls115and bottom surface165of the kerfs164within the substrate101. In accordance with embodiments, the conformal sealing layer130may be a single layer or include multiple layers.

The conformal sealing layer130may be formed of a variety of materials, or layer stacks of different materials, including semiconductors, metals, semi-metals, dielectrics, ceramics, and polymers. Selection of material may be based on at least barrier properties, clamping action, and diffusivity into the substrate, with higher Young's Modulus and CTE tending to provide higher clamping action. A listing of exemplary materials is provided in Table 1.

TABLE 1Listing of conformal sealing layer exemplary materialsYoung'sDiffusivityMaterialModulusCTEBarrierClampingrisk inClassMaterial(GPa)(ppm/° C.)propertiesactionsiliconCommentSemiconductorsSi1703Metals/TiN5009GoodGoodLowFilm may applySemi-bidirectionalmetalscompressive stressTi1209Good, alsoGoodHighSilicide formationa getter forwith Si may helpoxidationadhesionandmoistureCu13017GoodGoodHighDielectricsSiO2800.5ModerateModerateLowSiO2 is weaker(Glass)and may be undertensile stressSi—O—C—N~100~3Moderate+ModerateLowBetter than SiO2alloys+CeramicsSiN3501GoodModerateLow+Al2O34504.5GoodGoodLowPolymersPolyimide2.550ModerateModerateLow

In accordance with embodiments, the conformal sealing layer130may exert a compressive stress on the main body areas105. This can be vertical stress and/or horizontal stress in the vicinity of the sealing layer. The compressive stress can help clamp the conformal sealing layer130onto the main body area and promote adhesion. The vertical stress can also help hold the stack together. For example, this may be facilitated by a high temperature deposition process in which the deposited material contracts upon cooling, providing compressive stress. The conformal sealing layer130may be formed of suitable materials, including oxides (e.g. alumina), nitrides (e.g. silicon nitride, titanium nitride, titanium carbonitride, chromium nitride, aluminum titanium nitride, aluminum titanium chromium nitride, zirconium nitride), metals, and metal oxides. Suitable deposition methods include, but are not limited to, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), and physical vapor deposition (PVD). In an embodiment, the conformal sealing layer130has a Young's Modulus greater than silicon such as greater than 170 GPa, or more specifically 300-400 GPa, and a coefficient of thermal expansion (CTE) greater than silicon, such as greater than 4 ppm/° C.

Following deposition of the conformal sealing layer130, the patterning layer160may then be removed along with a portion of the conformal sealing layer130on top of the patterning layer160at operation4050, and as shown inFIG.5F. The multi-layer stack may then be flipped over, and a thickness of the substrate101is reduced to open up the array of kerfs164at operation4060, which also has the effect of singulating the plurality of chip structures100as shown inFIG.5G. The reduction in thickness can be performed chemically, or through a backgrinding operation such as chemical mechanical polishing (CMP) where the depth of the back surface102is reduced past the bottom surfaces165of the kerfs164. As a result, the back surfaces102of the substrate101may form a planar surface with back surfaces137of the conformal sealing layer130.

Referring now toFIG.6, a schematic top view illustration is provided of a wafer (substrate101) including a plurality of various FEOL die areas104arranged in die106sets of different sizes in accordance with an embodiment. Specifically,FIG.6illustrates an exemplary stage in processing similar toFIG.5F, after deposition of a conformal sealing layer130and prior to backgrinding to singulate each chip structure100. It is to be appreciated that the illustration provided inFIG.6however shows conformal sealing layer130outlines, generally as they may appear after singulation in order to show dicing lanes between chip structures100.

As shown, adjacent FEOL die areas104can be interconnected with die-to-die routing140to form chip structures100with any number of die sets. Specifically illustrated are die sets of ,2X,4X,8X. Each FEOL die area104may have a distinct circuit block separate from adjacent die areas104. Each FEOL die area104may represent a complete system, or sub-system. Adjacent FEOL die areas104may perform the same or different function. In an embodiment, an FEOL die area104interconnected with die-to-die routing can include a digital die area tied to an FEOL die area104with another function, such as analog, wireless (e.g. radio frequency, RF) or wireless input/output, by way of non-limiting examples. The tied FEOL die areas104may be formed using the same processing nodes, whether or not having the same or different functions. Whether each FEOL die area104includes a complete system, or are tied subsystems, the die-to-die routing140may be inter-die routing (different systems) or intra-die routing (different, or same subsystems within the same system). For example, intra die-to-die routing may connect different subsystems within a system on chip (SOC) where inter die-to-die routing can connect different SOCs, though this is illustrative and embodiments are not limited to SOCs.

In accordance with embodiments, any or all FEOL die area104edges can be configured to include die-to-die routing140. As shown inFIG.6, dicing or scribe lanes can be located anywhere to accommodate yield (e.g. bad dies) or demand (e.g. need for larger die sets. Dicing can be performed through die-to-die routing140between FEOL die areas104, or not. For example, the top five rows on substrate101are illustrated as having selective conformal sealing layers130deposited around pre-determined chip structure100die sets. The specific die106sets could have been determined after initial die area testing prior to completing the die-to-die routing140, or after completion of the BEOL build-up structures including die-to-die routing140. A defective FEOL die area, marked with an “X,” may cause dicing to be performed through die-to-die routing140which would have otherwise connected adjacent die areas104within a chip structure110. The bottom two rows show a slightly different configuration, where die-to-die routing140connects all FEOL die areas104in the bottom two rows, and die set determination is made after formation of the die-to-die routing. In this configuration, dicing lanes will go through die-to-die routing140. The harvesting and chip sealing techniques in accordance with embodiments can facilitate improved wafer utilization and harvesting of more dies or components. For example, this may be accomplished by being able to harvest die sets of different or irregular shapes, as well as utilizing programmable dicing methods.

In order to illustrate flexibility of the conformal sealing layer130and programmable dicing methods, various exemplary implementations are described and illustrated with regard toFIGS.7-18. It is to be appreciated that the following examples are illustrative of different features, and are not necessarily restrictive of one another, and may be combined in various single and multiple die set arrangements. Similar toFIG.6,FIGS.7-18illustrate exemplary embodiments after deposition of a conformal sealing layer130, and prior to backgrinding.

Referring toFIGS.7-8,FIG.7is a schematic cross-sectional side view illustration of a conformal sealing layer130formed around individual dies106in accordance with an embodiment.FIG.8is a schematic top view illustration of a conformal sealing layer formed around an individual die106in accordance with an embodiment. Thus, the embodiments illustrated inFIGS.7-8may correspond to sealing of a chip structure100including a1X die set ofFIG.6. More specifically, the cross-sectional side view illustration ofFIG.7illustrates various wiring layers M_low, M_mid, M_high, optionally a multiple layer conformal sealing layer130including a first seal layer131formed along chip edge sidewalls115and top surface116of the BEOL build-up structure110, and second seal layer132formed on the first seal layer131. In the exemplary top view illustration ofFIG.8, the chip structure100includes a FEOL die area104that includes both a device area170and input output/region(s)172. In an exemplary implementation, die routing174within the BEOL build-up structure110may be connected to the input/output region(s)172for potential connection to die-to-die routing. For example, the die routing174may be included within one of the upper metal layers, M_high, and connected to the FEOL die area104with various wiring layers114and vias113(seeFIG.1). In the exemplary embodiment illustrated, the chip structure100does not include die-to-die routing.

Referring toFIGS.9-10,FIG.9is a schematic cross-sectional side view illustration of a conformal sealing layer130formed around a die106set in accordance with an embodiment.FIG.10is a schematic top view illustration of a conformal sealing layer formed around a die set in accordance with an embodiment. As shown, the chip structures100can include internal die-to-die routing140connecting the adjacent dies106. Thus, the embodiments illustrated inFIGS.9-10may correspond to sealing of a chip structure100including a2X die set similar to that illustrated inFIG.6.

Referring toFIGS.11-12,FIG.11is a schematic top view illustration of a conformal sealing layer130formed around individual dies106with diced die-to-die routing140in accordance with an embodiment.FIG.12is a schematic top view illustration of a conformal sealing layer formed around a die106with diced die-to-die routing140in accordance with an embodiment. The embodiments illustrated inFIGS.11-12may correspond to sealing of a chip structure100including a ′ die set similar to that illustrated inFIG.6.

Referring toFIGS.13-14,FIG.13is a schematic top view illustration of a conformal sealing layer130formed around a die106set with diced die-to-die routing140in accordance with an embodiment.FIG.14is a schematic top view illustration of a conformal sealing layer formed around a die set with diced die-to-die routing in accordance with an embodiment. The embodiments illustrated inFIGS.13-14may correspond to sealing of a chip structure100including a2X′ die set similar to that illustrated inFIG.6.

Referring toFIGS.15-16,FIG.15is a schematic top view illustration of a conformal sealing layer130formed around individual dies106with partial metallic sealing structures152and diced die-to-die routing140in accordance with an embodiment.FIG.16is a schematic top view illustration of a conformal sealing layer formed around a die with partial metallic sealing structures152diced die-to-die routing140in accordance with an embodiment. In particular,FIGS.15-16illustrate the compatibility of the conformal sealing layer130with compromised, or partial metallic sealing structures152in accordance with embodiments. Full metallic sealing structures150can also be included. As shown, partial metallic sealing structures152can be formed partially or fully around the dies106, with die-to-die routing140completed for desired die sets. Partial metallic sealing structures152can be incorporated to provide design flexibility for harvesting interconnected die sets, while full metallic sealing structure150can be incorporated to provide more robust physical and/or electrical protection to the die within a chip structure100. The conformal sealing layer130can fully seal the chip edges sidewalls115adjacent the partial metallic sealing structures152.

Referring toFIGS.17-18,FIG.17is a schematic top view illustration of a conformal sealing layer130formed around a die106set with partial metallic sealing structure152in accordance with an embodiment.FIG.18is a schematic top view illustration of a conformal sealing layer formed around a die set with partial metallic sealing structure152in accordance with an embodiment.FIGS.17-18are substantially similar to those illustrated inFIGS.15-16, with a difference being that dicing is not performed through the die-to-die routing140. Similarly, the conformal sealing layer130can fully seal the chip edges sidewalls115adjacent the partial metallic sealing structures152.

While not separately illustrated, it is to be appreciated that the conformal sealing layer130ofFIGS.17-18can be formed along a single, multiple, or all chip edge sidewalls115. For example, where an internal full metallic seal structure150is located adjacent a chip edge sidewall115, the conformal sealing layer130is optional.

In utilizing the various aspects of the embodiments, it would become apparent to one skilled in the art that combinations or variations of the above embodiments are possible for forming sealed chip structure. Although the embodiments have been described in language specific to structural features and/or methodological acts, it is to be understood that the appended claims are not necessarily limited to the specific features or acts described. The specific features and acts disclosed are instead to be understood as embodiments of the claims useful for illustration.