Patent ID: 12224482

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

An IC layout is generated after numerous steps of an IC design, also called a “data preparation stage,” and a series of checks in a process, called “physical verification,” at the end. Examples of common checks in this verification process are design rule checking (DRC), layout versus schematic (LVS), parasitic extraction, antenna rule checking which will be discussed in detail below, and electrical rule checking (ERC). When all verification is complete, the data in the IC layout is translated into an industry standard format, typically a vector-based format, such as GDSII or OASIS, and sent to a semiconductor foundry, called a fab house. The foundry then converts, via mask data preparation (MDP) procedure, the data into a set of instructions by which a photomask writer can generate a physical mask (a photomask) to be used in a photolithographic process of semiconductor device fabrication. More recent MDP procedures require the additional steps associated with design for manufacturability such as, resolution enhancement technologies (RET) and optical proximity correction (OPC). By using a series of photomasks, in addition to other processes, a wafer having one or more die (chips) is fabricated.

The antenna effect, more formally plasma induced gate oxide damage, is an effect that can potentially cause yield and reliability problems during the manufacture of integrated circuits. In the manufacturing of an integrated circuit (IC) using Metal-Oxide-Semiconductor (MOS) technology, processes involving charged ions are typically employed, such as a plasma etching process and an ion implantation process. As an example, during a plasma etching process used in forming gate polysilicon (poly) patterns or interconnect metal line patterns, electrostatic charges may accumulate on a floating gate poly electrode. The resulting voltage on the gate poly electrode may become so large that charges may flow into the gate oxide, become trapped in the gate oxide or flow through the gate oxide. These charges may significantly degrade the gate oxide strength and cause MOS device reliability failures.

Each poly gate region collects an electrostatic charge proportional to its own area. A small gate oxide region connected to a large poly geometry or a large interconnect metal geometry through poly contacts can accumulate a disproportionate amount of charges (positive plasma ions in the case of a grounded or a negative biased wafer) and may suffer serious damage. This mechanism is commonly known as the antenna effect because the large poly or interconnect metal area act as an antenna to collect the electrostatic charges that flow through the vulnerable gate oxide. The strength of the antenna effect is proportional to the ratio between the exposed conductor area and the gate oxide area.

Foundries normally supply antenna rules, which are rules that are provided to avoid the antenna effect. A violation of the antenna rules is called an antenna violation. When there is any antenna rule violation, IC designers take measures to fix the antenna rule violation.

Additionally, on-chip electrostatic discharge (ESD) is typically provided. On-chip ESD protection mechanisms generally work in two ways. First, by dissipating the ESD current transient safely using a low-impedance discharging channel that prevents thermal damages in the structures of the IC. Secondly, by clamping any ESD induced voltage to a safe level to avoid dielectric degradation or rupture. Ideally the complete ESD protection solution may be realized on the IC creating an effective discharging channel from any pin to every other pin on the IC.

A three-dimensional integrated circuit (3D IC) is an IC manufactured by stacking silicon wafers or dies and interconnecting them vertically using, for instance, through-substrate vias (TSVs), hybrid boding (HB), or Cu—Cu connections, so that they behave as a single device to achieve performance improvements at reduced power and smaller footprint than conventional two dimensional processes. The 3D IC is one of several 3D integration schemes that exploit the vertical direction (i.e., a Z-direction) to achieve electrical performance benefits, in microelectronics and nanoelectronics. In a 3D IC chip, the antenna effect is specifically referred to the package antenna effect. The package antenna effect is caused by ploy gate breakage due to charges generated during etching of a TSV and a HB structure.

In accordance with embodiments of the disclosure, as a 3D IC may generally have TSVs and HB structures, and an antenna diode is placed in the TSV cell (i.e., within a “keep-out” zone where no active semiconductor devices are placed as discussed further below) or a HB region, rather than being associated with any specific functional cell. The centralized approach (i.e., one antenna diode in the TSV cell or the HB region that protects many transistors in neighboring functional cells) is more effective in terms of chip area, IC speed, and power consumption. Placing the antenna diode inside the TSV cell takes advantage of the chip area inside the TSV cell, which otherwise cannot be utilized for placing any active semiconductor devices. In addition to adding an antenna diode in the TSV cell or the HB region, the gate structure of a transistor in the neighboring function cells may have an enlarged poly area to provide further antenna effect protection for this specific transistor. These technologies are applicable to ESD protection as well.

FIG.1is a schematic diagram illustrating a 3D IC package100in accordance with some embodiments. In the example shown inFIG.1, the 3D IC package100includes three stacked IC dies102,104, and106, though any desired number (e.g., four, six, nine, and so on) of stacked IC dies are within the scope of the disclosure. A variety of IC die types may be included, depending intended functions performed by the 3D IC package100. For example, the 3D IC package100may be the main processor of a laptop computer, a tablet computer, a smart phone, an audio/video player, a cellular phone, a video game console, a television, a radio, or other electronic device. In some embodiments, two of the IC dies (e.g., the IC dies102and104) are similarly configured, so that one of the two IC dies (e.g., the IC die102) can be substituted for the other (e.g., the IC die104) in the event of a failure, and the failed IC die (e.g., the IC die104) can be bypassed.

In some embodiments, the 3D IC package100is a complete system in package (SiP), in which the IC die102is a general purpose processor, and the IC dies104and106may be any combination of dynamic random access memory (DRAM), a graphics processor, an audio/video processor, a digital radio receiver, a flash memory (or other solid state memory), a communications processor (which may include a WiFi (802.11) interface, a global positioning satellite (GPS) receiver, a Bluetooth interface, a second processor, a power management unit or other communications interface used by the 3D IC package100. These IC die types are only listed as examples and are not exclusive of other types of IC dies.

In some embodiments, the 3D IC package100may be optionally mounted to a semiconductor interposer (e.g., a silicon interposer) not shown, in a 2.5D IC configuration. The interposer has one or more additional IC dies mounted horizontally from the 3D IC package100. In one non-limiting example, one of the additional IC dies is the main system processor, another one of the additional IC dies is a system bus, and the IC dies102,104, and106are three DRAM dies.

Each of the three stacked IC dies102,104, and106has a front side (F) and a back side (B). In the example shown inFIG.1, the back side of the IC die102is facing the front side of the IC die104; the back side of the IC die104is facing the front side of the front side of the IC die106. The IC dies102,104, and106are connected to each other by interconnect structures110, such as through substrate vias (TSVs) (also referred to as through-silicon vias in the case where the IC dies are fabricated on a silicon substrate), metal patterns, conductive vias, redistribution layer, hybrid bonding (HB) structures or the like. The discussion herein applies to IC dies fabricated on any type of semiconductor substrate such as silicon substrates and silicon on insulator (SOI) substrates. AlthoughFIG.1only shows five interconnect structures110between the IC dies102and104as well as between the IC dies104and106, this is just for illustrative purpose. Any desired number of interconnect structures110may be provided.

FIG.2is a cross-sectional diagram of an example 3D IC package100ofFIG.1in accordance with some embodiments. In the example shown inFIG.2, each of the IC dies102,104, and106has a substrate122, front-end-of-line (FEOL) structures such as transistors not shown, and back-end-of-line (BEOL) structures including a multi-layer interconnect (MLI) structure124. The MLI structure124includes, among other things, multiple metal layers and vias connecting those multiple metal layers. In one non-limiting example, the MLI structure124includes the first metal (M1) layer, the second metal (M2) layer, the third metal (M3) layer, the fourth metal (M4) layer, the fifth metal (M5) layer all the way up to the twelfth metal (M12) layer. Complicated routing of the IC die104may be achieved by the MLI structure124. Solder bumps126at the front side of the IC die102can be used to bond the 3D IC package100with other structures such as a semiconductor interposer as mentioned above. Since the IC die104is interfacing, at both the front side and the back side, with the IC die102and the IC die106, respectively, only the IC die104is discussed in detail below for simplicity.

In the example shown inFIG.2, there are two categories of the interconnect structures110, namely the interconnect structures110aand the interconnect structures110b. The interconnect structure110aincludes a TSV112and an HB structure114. The TSV112is through the substrate122and connected between the MLI structure124and the HB structure114. The HB structure114includes two layers: a hybrid bonding contact structure and a hybrid bonding metal layer, which will be described below in detail with reference toFIG.8. The HB structure114is also used for, together with other HB structures114, bonding of the IC dies104and106. Specifically, the HB structure114interfaces with another HB structure114on the other side (i.e., protruding from the IC die106) to form an HB structure pair, and the hybrid bonding metal layers of this HB structure pair are bonded together. As such, the IC dies104and106are bonded and electrically connected through the TSV112and the HB structure114, at the back side of the IC die104. Details of the interconnect structure110awill be discussed in detail below with reference toFIGS.3-6.

On the other hand, at the front side of the IC die104, the interconnect structure110bincludes another HB structure114(e.g., the leftmost between the IC dies104and102, shown inFIG.2). The HB structure114is similarly used for, together with other HB structures114, bonding of the IC dies104and102. Specifically, the HB structure114interfaces with another HB structure114on the other side (i.e., protruding from the IC die102) to form an HB structure pair, and the hybrid bonding metal layers of this HB structure pair are bonded together. As such, the IC dies104and102are bonded. Details of the interconnect structure110bwill be discussed in detail below with reference toFIGS.8-9.

FIG.3is a cross-sectional diagram of a TSV cell132at the back side of the IC die104ofFIG.2in accordance with some embodiments.FIG.4is a diagram illustrating the TSV cell132ofFIG.3in accordance with some embodiments.FIG.5is a diagram illustrating a layout of the TSV cell132ofFIG.3in accordance with some embodiments. In general, an antenna diode136is placed in the TSV cell132for antenna effect protection of the IC die104. Unlike in some 2D ICs, the antenna diode136is not placed in any functional cell and is not associated with any specific transistors in the IC die104. Instead, the antenna diode136is placed in the TSV cell132. It should be noted that the antenna diode136is one non-limiting example of an antenna protection module. Other suitable antenna protection modules are within the scope of the disclosure.

In the example shown inFIG.3, the interconnect structure110aincludes, among other things, a (backside) TSV112at the back side of the IC die104. The TSV112is located in a TSV cell132. A functional cell134is next to the TSV cell132. The functional cell134may be a standard cell chosen from a cell library in the IC design stage. In the non-limiting example shown inFIG.3, a transistor138is located in the functional cell134, though other components not shown may also be located in the functional cell134. One end of the TSV112is connected to a metal pattern140in the zero metal (M0) layer. It should be noted that this is just one example, and the TSV112may be connected to other metal patterns in other layers (e.g., a metal pattern in the M1 layer). In one non-limiting example, the TSV112includes a liner not shown, a diffusion barrier layer not shown, and a conductive material not shown, subsequently from outside to inside. In one embodiment, the TSV structure112is formed by the following operations. Firstly, a TSV opening is formed extending to the metal pattern140in the M0 layer by one or more etching processes. After the TSV opening is formed, the liner is formed on sidewalls of the TSV opening to act as an isolation layer, such that the conductive material of the TSV structure112and the substrate122do not directly contact with each other. Afterwards, the diffusion barrier layer is conformally formed on the liner and on the bottom of the TSV opening. The diffusion barrier layer is used to prevent the conductive material, which will be formed later, from migrating to undesired regions. After the diffusion barrier layer is formed, the conductive material is used to fill into the TSV opening. Afterwards, excess liner, diffusion barrier layer, and conductive material, which are on the outside of the TSV opening, are removed by a planarization process, such as a chemical mechanical polishing (CMP) process, although any suitable removal process may be used.

However, during the fabrication of the TSV112, charges are generated in etch processes. Those charges (schematically shown as “e−” inFIG.3) may flow to and accumulate on the gate139of the transistor138in the functional cell134. Specifically, in this example, the electrical path through which the charges flow is from the TSV112, via the metal pattern140and a schematic electrical path142, to the gate structure139of the transistor138. The schematic electrical path142represents an electrical path in other metal layers such as the M1 layer and the M2 layer. As a result, the voltage on the poly electrode of the gate structure139may become so large that charges may flow into the gate oxide of the gate structure139, become trapped in the gate oxide or flow through the gate oxide. These charges may significantly degrade the gate oxide strength and cause MOS device reliability failures, as mentioned above.

In a 2D IC package, an antenna diode may be placed in the specific functional cell (e.g., the functional cell134) where an antenna effect exists or an antenna rule is violated. The antenna diode creates another electrical path to discharge the charges. However, placing an antenna diode in the specific functional cell is remedial (i.e., only after identifying the antenna effect), and sometimes there is not enough chip area in the specific functional cell to accommodate the antenna diode. Alternatively, it is possible to place an antenna diode in every functional cell to solve the problem in advance. However, the extra capacitance of the antenna diodes may make the 2D IC slower and more power hungry. It should be noted that an antenna capacitor may function in the same manner as the antenna diode in terms of antenna effect protection.

In contrast, in the 3D IC (e.g., the 3D IC package100shown inFIG.1andFIG.2), TSVs (e.g., the TSV112) are generally used. The antenna diode136is not associated with any specific functional cell (e.g., the functional cell134). Instead, the antenna diode136is placed in the TSV cell132. The centralized approach (i.e., one antenna diode in the TSV cell that protects many transistors in neighboring functional cells) is more effective in terms of chip area, IC speed, and power consumption. Specifically, in the example ofFIG.3, an antenna diode136is placed in the TSV cell132. The antenna diode136is connected with the TSV112through a via137and the metal pattern140in the M0 layer, though other connection means (e.g. through metal patterns in other metal layers) are also within the scope of the disclosure.

In one embodiment, in addition to adding the antenna diode136in the TSV cell132, the gate structure139of the transistor138has an enlarged poly area. This can be achieved by for example connecting multiple transistors in parallel. When the transistor138is a FinFET, this can also be achieved by for example using multiple fin (e.g., two-fin, three-fin, five-fin, and so on) structures for one FinFET. The enlarged poly area can provide further antenna effect protection to a specific transistor in a specific functional cell.

Referring toFIG.4, the TSV cell132has a TSV cell boundary144. The TSV112is located in the middle of the TSV cell132. The TSV cell132is also referred to as a keep-out zone (KOZ)132, because no active semiconductor devices (i.e., transistors that are used to transmit/process signals) are allowed to be placed in the keep-out zone132, to avoid interference (e.g., TSV-induced stress) between the TSV112and the active semiconductor devices inside the keep-out zone132. In other words, if any active semiconductor device is placed inside the keep-out zone132, the behavior of the active semiconductor device may be negatively impacted, and electrical damages may occur. Keep-out zone132is a conservative way to prevent any active semiconductor devices from being impacted by the interference. It should be noted that the TSV cell132and the keep-out zone132are used interchangeably in the disclosure.

However, as the antenna diode136is a passive semiconductor device (i.e., a transistor not used to transmit/process signals), the antenna diode136is allowed to be placed in the keep-out zone132(i.e., inside the TSV cell boundary144).

On the other hand, placing the antenna diode too close to the TSV112is avoided, because process variations may result a closer distance between the TSV112and the antenna diode136than expected. The closer distance may lead to physical damages. Therefore, the antenna diode136should be placed outside a TSV buffer zone146having a TSV buffer zone boundary147.

In summary, the antenna diode136, or generally an antenna protection module, is placed in the TSV cell132, and more specifically inside the TSV cell boundary144while outside the TSV buffer zone146. The size of the TSV cell132is generally larger than the size of the functional cell134. Placing the antenna diode136inside the TSV cell132(i.e., the keep-out zone132) takes advantage of the chip area inside the TSV cell132, which otherwise cannot be utilized for placing any active semiconductor devices.

As shown inFIG.4, the distance between the TSV112and the TSV cell boundary144is D1, whereas the distance between the TSV112and the TSV buffer zone boundary147is D2. In one non-limiting example, D1 is 5 μm, whereas D2 is 3 μm. In another non-limiting example, D1 is 3 μm, whereas D2 is 1 μm. It should be noted that the shapes and the dimensional sizes shown inFIG.4are only for illustration. Other shapes and dimensional sizes are within the scope of the disclosure.

The TSV cell132can be divided into multiple rows for layout design purposes. In one embodiment, the antenna diode136is placed “on row,” meaning that the antenna diode136is placed on one row148as shown inFIG.4. Placing the antenna diode136on row may be compatible with certain layout rules.

FIG.5is a diagram illustrating another TSV cell132′ in accordance with some embodiments. As mentioned above, on-chip ESD protection is provided in disclosed embodiments to protect the IC device. On-chip ESD protection mechanisms generally work in two ways. In general, by placing an ESD protection module136′ inside the TSV cell132′, the ESD current is dissipated safely through a low-impedance discharging channel that prevents thermal damages in the structures of the IC.

FIG.5is similar toFIG.4, except that the ESD protection module136′ is different from the antenna diode136ofFIG.4. Devices that may be used as the ESD protection module136′ include diodes, bipolar transistors, MOSFETs and silicon-controlled rectifiers (SCRs), among others. The ESD protection module136′ is generally larger than the antenna diode136ofFIG.4, as the ESD current is generally larger than that of an antenna effect. In the non-limiting example shown inFIG.5, the ESD protection module136′ includes multiple diodes connected in parallel to handle the relatively large ESD current.

Again, the ESD protection module136′ is placed inside the keep-out zone132′ (i.e., the TSV cell132′, used interchangeably in this disclosure) while outside the TSV buffer zone146, in the same manner as inFIG.4. The ESD protection module136′ can be placed inside the keep-out zone132′ because it is not an active semiconductor device. Other details are not repeated for simplicity asFIG.5is similar toFIG.4.

It should be noted that the antenna protection module (e.g., the antenna diode136) and the ESD protection module136′ can generally be referred to as a protection module.

FIG.6is a cross-sectional diagram illustrating the TSV cell132ofFIG.3with backside routing150in accordance with some embodiments.FIG.7is a flowchart illustrating a method700of antenna rule checking in accordance with some embodiments. The portion above the dash line X-X′ is the same as that inFIG.3, whereas the portion below the dash line X-X′ is the backside routing150. In the non-limiting example shown inFIG.6, the backside routing150includes, among other things, two metal patterns in two metal layers152, a via154connected therebetween, and a solder bump126. Charges generated during the fabrication of the backside routing150may flow to and accumulate at the gate structure139of the transistor138as well. Therefore, the antenna rule checking method700is needed to address the IC die104having the TSV112.

As shown inFIG.7, the method700generally includes two steps. At step702, a first antenna rule checking is run for the IC die104with a (backside) TSV112. The TSV112has the antenna diode136placed inside the keep-out zone132(i.e., the TSV cell132) of the TSV112. In one embodiment, poly area parameters and junction area parameters may be generated for a specific port step702, which may be utilized later. At step704, a second antenna rule checking is run for the backside routing150shown inFIG.6. In one embodiment, the poly area parameters and the junction area parameters generated earlier may be used for the second antenna rule checking. As such, the antenna rule checking method700can address potential antenna rule violation on both sides (i.e., above and below the line X-X′ shown inFIG.6).

FIG.8is a cross-sectional diagram of a HB region133at the front side of the IC die104ofFIG.2in accordance with some embodiments.FIG.9is a diagram illustrating the HB region133ofFIG.8in accordance with some embodiments. In general, an antenna diode136is placed in the HB region133(i.e., a region surrounding the HB structure114) for antenna effect protection of the IC die104. Unlike in 2D IC, the antenna diode136is not placed in any functional cell and is not associated with any specific transistors in the IC die104. Instead, the antenna diode136is placed in the HB region133.

Hybrid bonding (HB) is a technology that may be used for wafer-to-wafer, die-to-wafer, and die-to-die interconnection. In hybrid bonding, two structures are bonded together using different materials with a wafer bonder. Specifically, two dies/wafers are bonded together using a combination of two technologies, namely a dielectric-to-dielectric bond and a metal-to-metal bond, often at room temperature. In one embodiment, the dielectric-to-dielectric bond is followed by the metal-to-metal bond. In one embodiment, the metal-to-metal bond is a copper-to-copper bond. Hybrid bonding enables 250,000 to 1 million interconnect structures per square millimeter, much more than other technologies such as micro-bumps do.

In the example shown inFIG.8, the interconnect structure110bincludes, among other things, a HB structure114at the front side of the IC die104. The HB structure114is located in a HB region (i.e., a HB cell, used interchangeably in this disclosure)133. A functional cell134is next to the HB region133. The functional cell134may be a standard cell chosen from a cell library in the IC design stage. In the non-limiting example shown inFIG.8, a transistor138is located in the functional cell134, though other components not shown may also be located in the functional cell134.

The HB structure114includes, among other things, a hybrid bonding metal layer116and a hybrid bonding contact structure118below the hybrid bonding metal layer116. The hybrid bonding contact structure188is a via in one embodiment. The hybrid bonding contact structure188is connected to a metal pattern162in the top metal layer of an MLI structure not shown. In a non-limiting example shown inFIG.8, the top metal layer is the twelfth metal (M12) layer.

However, during the fabrication of the HB structure114, charges are generated in etch processes. Those charges (schematically shown as “c” inFIG.8) may flow to and accumulate on the gate structure139of the transistor138in the functional cell134. Specifically, in this example, the electrical path through which the charges flow is from the HB structure114, via the metal pattern162and a schematic electrical path142, to the gate structure139of the transistor138. The schematic electrical path142represents an electrical path in other metal layers such as all metal layers between the M1 layer to the M12 layer. As a result, the voltage on the poly electrode of the gate structure139may become so large that charges may flow into the gate oxide of the gate structure139, become trapped in the gate oxide or flow through the gate oxide. These charges may significantly degrade the gate oxide strength and cause MOS device reliability failures, as mentioned above.

Again, unlike in 2D IC where an antenna diode may be placed in the specific functional cell (e.g., the functional cell134) where an antenna effect exists or an antenna rule is violated, in the 3D IC (e.g., the 3D IC package100shown inFIG.1andFIG.2), the antenna diode136is not associated with any specific functional cell (e.g., the functional cell134). Instead, the antenna diode136is placed in the HB region133. The centralized approach (i.e., one antenna diode in the HB region that protects many transistors in neighboring functional cells) is more effective in terms of chip area, IC speed, and power consumption. Specifically, in the example ofFIG.8, an antenna diode136is placed in the HB region133. The antenna diode136is connected with the HB structure114through a schematic electrical path143similar to the schematic electrical path142.

In one embodiment, in addition to adding the antenna diode136in the HB region133, the gate structure139of the transistor138has an enlarged poly area. This can be achieved by for example connecting multiple transistors in parallel. When the transistor138is a FinFET, this can also be achieved by for example using multiple fin (e.g., two-fin, three-fin, five-fin, and so on) structures for one FinFET. The enlarged poly area can provide further antenna effect protection to a specific transistor in a specific functional cell.

Referring toFIG.9, the HB region133has a HB region boundary160. The HB structure114is located in the middle of the HB region133. Unlike the TSV cell132as shown inFIG.4, the HB region does not have a keep-out zone (KOZ) and does not have a buffer zone, because the HB structure114is on the top of the front side of the IC die104. The antenna diode136is allowed to be placed anywhere in the HB region133. In some embodiments, the antenna diode136does not overlap with the HB structure114. In other embodiments, the antenna diode136may overlap with the HB structure114. In a non-limiting example, the distance D3 between the HB structure114and the antenna diode136is three contacted poly pitches (CPP). In another non-limiting example, the distance D3 between the HB structure114and the antenna diode136is two contacted poly pitches (CPP). In yet another non-limiting example, the distance D3 between the HB structure114and the antenna diode136is one contacted poly pitch (CPP). It should be noted that the shapes and the dimensional sizes shown inFIG.9are only for illustration. Other shapes and dimensional sizes are within the scope of the disclosure.

Similarly, the HB region133can be divided into multiple rows for layout design purposes. In one embodiment, the antenna diode136is placed “on row,” meaning that the antenna diode136is placed on one row not shown. Placing the antenna diode136on row may be compatible with certain layout rules.

Similarly, an ESD protection module may be placed in the HB region133in the same manner shown inFIG.5. For simplicity, details of placing an ESD protection module in the HB region133are not discussed in detail.

FIG.10is a flowchart illustration a method1000for fabricating a 3D IC package in accordance with some embodiments. As shown inFIG.10, the method1000starts at step1002. At step1002, a first IC die (e.g., the IC die104shown inFIG.2) is provided. The first IC die has a first substrate (i.e., the substrate122shown inFIG.2) at a back side of the first IC die. At step1004, a TSV (e.g., the TSV112shown inFIG.3) is fabricated through the first substrate. The TSV has a TSV cell (e.g., the TSV cell132shown inFIG.3). In one embodiment, the TSV structure s formed by the following operations. Firstly, a TSV opening is formed extending to the metal pattern in the M0 layer by one or more etching processes. After the TSV opening is formed, the liner is formed on sidewalls of the TSV opening to act as an isolation layer, such that the conductive material of the TSV and the substrate do not directly contact with each other. Afterwards, the diffusion barrier layer is conformally formed on the liner and on the bottom of the TSV opening. The diffusion barrier layer is used to prevent the conductive material, which will be formed later, from migrating to undesired regions. After the diffusion barrier layer is formed, the conductive material is used to fill into the TSV opening. Afterwards, excess liner, diffusion barrier layer, and conductive material, which are on the outside of the TSV opening, are removed by a planarization process, such as a chemical mechanical polishing (CMP) process, although any suitable removal process may be used.

At step1006, a protection module (e.g., the antenna diode136shown inFIG.4, the ESD protection module136′ shown inFIG.5) is fabricated in the first substrate. The protection module is electrically connected to the TSV, and the protection module is within the TSV cell. At step1008, a second IC die (e.g., the IC die106shown inFIG.2) is provided at the back side of the first IC die and facing the first substrate. At step1010, the second IC die is bonded to the back side of the first IC die. The first IC die and the second IC die are electrically connected through the TSV. In one embodiment, the second IC die is bonded to the back side of the first IC die using hybrid bonding (i.e., by utilizing a HB structure), and the TSV is electrically connected to the HB structure.

In accordance with some disclosed embodiments, a 3D IC package is provided. The 3D IC package includes: a first IC die comprising a first substrate at a back side of the first IC die; a second IC die stacked at the back side of the first IC die and facing the first substrate; a TSV through the first substrate and electrically connecting the first IC die and the second IC die, the TSV having a TSV cell including a TSV cell boundary surrounding the TSV; and a protection module fabricated in the first substrate, wherein the protection module is electrically connected to the TSV, and the protection module is within the TSV cell.

In accordance with some disclosed embodiments, another 3D IC package is provided. The 3D IC package includes: a first IC die comprising a first substrate at a back side of the first IC die; a second IC die stacked at a front side of the first IC die; a HB structure bonding the first IC die and the second IC die, the HB structure having a HB region surrounding the HB structure; and a protection module fabricated in the first substrate, wherein the protection module is electrically connected to the HB structure, and the protection module is within the HB region.

In accordance with further disclosed embodiments, a method is provided. The method includes: providing a first IC die comprising a first substrate at a back side of the first IC die; fabricating a through-substrate via (TSV) through the first substrate, the TSV having a TSV cell; fabricating a protection module in the first substrate, wherein the protection module is electrically connected to the TSV, and the protection module is within the TSV cell; providing a second IC die at the back side of the first IC die and facing the first substrate; and connecting the second IC die to the back side of the first IC die using the TSV.

This disclosure outlines various embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.