Patent ID: 12201840

DETAILED DESCRIPTION

The following description is of the best-contemplated mode of carrying out the disclosure. This description is made for the purpose of illustrating the general principles of the disclosure and should not be taken in a limiting sense. The scope of the disclosure is best determined by reference to the appended claims.

FIG.1is a block diagram of an electrical stimulation device100according to an embodiment of the disclosure. As shown inFIG.1, the electrical stimulation device100may comprise a boost circuit110, a voltage selecting circuit120, control circuit130, a first switch circuit140, a second switch circuit150and an adjustable current source160. It should be noted thatFIG.1presents a simplified block diagram in which only the elements relevant to the disclosure are shown. However, the disclosure should not be limited to what is shown inFIG.1. The electrical stimulation device100may also comprise other elements and devices.

According to embodiments of the disclosure, the boost circuit110may be configured to generates a plurality of voltages V1˜V6to provide the voltage selecting circuit120with selecting. The structure of the boost circuit110is illustrated based onFIGS.2A-2Bbelow.

According to embodiments of the disclosure, according to a reference voltage, the voltage selecting circuit120may select a suitable voltage from the voltages generated by the boost circuit110, and the selected voltage will be taken as an output voltage V+. The structure of the voltage selecting circuit120is illustrated based onFIG.3below.

According to embodiments of the disclosure, the control circuit130may control the boost circuit110, the first switch circuit140, the second switch circuit150and the adjustable current source160according to commands from an external device (not shown in figures). The control circuit130may control enabling or disabling of the first switch circuit140and the second switch circuit150to control the transformation between the positive voltage and the negative voltage. In addition, when the electrical stimulation is performed, the control circuit130may transmit a control signal Vc to enable the boost circuit110. The structure of the control circuit130is illustrated based onFIGS.2A-2BandFIG.3below.

According to embodiments of the disclosure, the first switch circuit140may be coupled to a first electrode input end E1and a second electrode input end E2, and the second switch circuit150may be coupled to the first electrode input end E1and the second electrode input end E2. When the first switch circuit140is enabled, the first switch circuit140may obtain the reference voltage Vrefin on the tissue impedance R (e.g. the independence of the human body or biological tissue) from the first electrode input end E1and the second electrode input end E2. When the second switch circuit150is enabled, the second switch circuit150may obtain the reference voltage Vrefin on the tissue impedance R from the first electrode input end E1and the second electrode input end E2.

FIG.2Ais a circuit diagram of a boost circuit110according to an embodiment of the disclosure. As shown inFIG.2A, the boost circuit110may comprise a plurality of stages of the charge pump circuits111-1˜111-5and a plurality of capacitors Cs1˜Cs5. Each charge pump circuit may be corresponded to a capacitor, and each capacitor may store may store different voltage. InFIG.2A, the V5vpin of each charge pump circuit is used to receive the 5V (the disclosure should not be limited thereto) voltage from the battery (not shown in figures) of the electrical stimulation device100. The Vih pin of each charge pump circuit is used to receive the output of the Voh pin of the prior stage of charge pump circuit, wherein the Vih pin of the first stage of charge pump circuit111-1receives the source voltage Vdd. The Vil pin of each charge pump circuit is used to receive the output of the Vol pin of the prior stage of charge pump circuit, wherein the Vil pin of the first stage of charge pump circuit111-1receive the ground voltage gnd. In addition, the Vin pin of the first stage of charge pump circuit111-1is used to receive the control signal Vc from the control circuit130(i.e. when the electrical stimulation is performed, the control circuit130may transmit the control signal Vc to the boost circuit110), and the Vin pins of other charge pump circuits111-2˜111-5may receive the signal received by the Vih pin of prior stage of charge pump circuit. As shown inFIG.1, in the embodiment, the boost circuit110may generate the voltage V1with 5V voltage value (i.e. the 5V voltage (not boosted) of the V5vpin=V1), the voltage V2with 10V voltage value (i.e. the voltage of output node Vout1=V2), the voltage V3with 15V voltage value (i.e. the voltage of output node Vout2=V3), the voltage V4with 20V voltage value (i.e. the voltage of output node Vout3=V4), the voltage V5with 25V voltage value (i.e. the voltage of output node Vout4=V5) and the voltage V6with 30V voltage value (i.e. the voltage of output node Vout5=V6), but the disclosure should not be limited thereto. The voltage V1may be outputted to the voltage selecting circuit120through the V5vpin of charge pump circuit. The voltages V2˜V6which are boosted may be stored in the capacitors Cs1˜Cs5respectively. The voltages V2˜V6which are boosted by the boost circuit110may be outputted to the voltage selecting circuit120through output nodes Vout1˜Vout5respectively. The operations of each charge pump circuit shown inFIG.2Aare illustrated based onFIG.2B. It should be noted thatFIG.2Ashows five stages of the charge pump circuits, but the disclosure should not be limited thereto. In other embodiments, the boost circuit110may also adopt different stages of the charge pump circuits. In addition, it should be noted that the boost circuit110shown inFIG.2Ais only an embodiment of the disclosure, but the disclosure should not be limited thereto. In other embodiments, other boost circuits also can be adopted as the boost circuit110.

FIG.2Bis a circuit diagram of a charge pump circuit200according to an embodiment of the disclosure. The charge pump circuit200shown inFIG.2Bcan be applied to the charge pump circuits111-1˜111-5shown inFIG.2A. As shown inFIG.2B, the charge pump circuit200may comprise invertors210˜230, a diode240and a Zener diode250. The charge pump circuit200may be coupled to a capacitor Cs and connected to the Zener diode250in parallel. In the embodiment, it is assumed that the V5vpin of the charge pump circuit200receives 5V voltage from the battery (not shown in figures) of the electrical stimulation device100, the Vih pin of the charge pump circuit200receives 5V voltage, and the Vil pin of the charge pump circuit200receives 0V voltage. Therefore, when the control signal Vc received by the Vin pin of the charge pump circuit200is at high level (5V), the Voh pin of the charge pump circuit200may output 5V voltage and the Vol pin of the charge pump circuit200may output 0V voltage; and when the control signal Vc received by the Vin pin of the charge pump circuit200is at low level (0V), the Voh pin of the charge pump circuit200may output 10V voltage and the Vol pin of the charge pump circuit200may output 5V voltage. That is to say, when the control signal Vc received by the Vin pin of the charge pump circuit200is at low level (0V), the output voltage of the Voh pin of the charge pump circuit200will be twice as the voltage (i.e. 5V voltage) of the Vih pin of the charge pump circuit200(i.e. the voltage boost is performed), and the capacitor Cs may store the 10V of output voltage of the Voh pin of the charge pump circuit200. On the contrary, when the control signal Vc received by the Vin pin of the charge pump circuit200is at high level (5V), the output voltage of the Voh pin of the charge pump circuit200will maintain 5V voltage (i.e. the voltage boost is not performed). In addition, in the embodiment, the Zener diode250is used to limit the cross-voltage between the two ends of the capacitor Cs to below 5V in order to protect the inputs (i.e. Vih pin and Vil pin) of the next stage of charge pump. It should be noted that inFIG.2B, the charge pump circuit200comprises three inverters, but the disclosure should not be limited thereto. In other embodiments, the charge pump circuit200may comprise different number of inverters.

FIG.3is a circuit diagram of a voltage selecting circuit120, a control circuit130, a first switch circuit140, a second switch circuit150and an adjustable current source160according to an embodiment of the disclosure. As shown inFIG.3, the voltage selecting circuit120may be coupled to a current source300and the voltage selecting circuit120may comprise a first selecting circuit121, a second selecting circuit122, a third selecting circuit123, a fourth selecting circuit124, a fifth selecting circuit125and a sixth selecting circuit126. The first selecting circuit121, the second selecting circuit122, the third selecting circuit123, the fourth selecting circuit124, the fifth selecting circuit125and the sixth selecting circuit126are respectively corresponded to the voltages V1˜V6generated by the boost circuit110. The first selecting circuit121may comprise a first diode D1, a first resistor R1, a second resistor R2, a first Zener diode ZD1and a first transistor M1. One end of the first resistor R1is coupled to the diode Da and the diode Db, and the other end of the first resistor R1is coupled to the current source300. One end of the resistor R2is coupled to the current source300, and the other end of the resistor R2is coupled to the cathode of the first Zener diode ZD1and the gate of the first transistor M1.

The second selecting circuit122may comprise a second diode D2, a third resistor R3, a fourth resistor R4, a second Zener diode ZD2, a third Zener diode ZD3, a second transistor M2and a third transistor M3. One end of the third resistor R3is coupled to the drain of the first transistor M1and the cathode of the first diode D1and the other end of the third resistor R3is coupled to the cathode of the third Zener diode ZD3and the gate of the third transistor M3. One end of the fourth resistor R4is coupled to the current source300, and the other end of the fourth resistor R4is coupled to the drain of the third transistor M3, the gate of the second transistor M2, and the cathode of the second Zener diode ZD2. The gate of the second transistor M2and the drain of the third transistor M3are coupled to the cathode of the second Zener diode ZD2, and the sources of the second transistor M2and the third transistor M3are coupled to the anode of the second Zener diode ZD2, the anode of the third Zener diode ZD3and the output voltage V+.

The third selecting circuit123may comprise a third diode D3, a fifth resistor R5, a sixth resistor R6, a fourth Zener diode ZD4, a fifth Zener diode ZD5, a fourth transistor M4and a fifth transistor M5. One end of the fifth resistor R5is coupled to the drain of the second transistor M2and the cathode of the second diode D2, and the other end of the fifth resistor R5is coupled to the cathode of the fifth Zener diode ZD5and the gate of the fifth transistor M5. One end of the sixth resistor R6is coupled to the current source300, and the other end of the sixth resistor R6is coupled to the drain of the fifth transistor M5, the gate of the fourth transistor M4, and the cathode of the fourth Zener diode ZD4. The gate of the fourth transistor M4and the drain of the fifth transistor M5are coupled to the cathode of the fourth Zener diode ZD4, and the sources of the fourth transistor M4and the fifth transistor M5are coupled to the anode of the fourth Zener diode ZD4, the anode of the fifth Zener diode ZD5and the output voltage V+.

The fourth selecting circuit124may comprise a fourth diode D4, a seventh resistor R7, an eighth resistor R8, a sixth Zener diode ZD6, a seventh Zener diode ZD7, a sixth transistor M6and a seventh transistor M7. One end of the seventh resistor R7is coupled to the drain of the fourth transistor M4and the cathode of the third diode D3, and the other end of the seventh resistor R7is coupled to the cathode of the seventh Zener diode ZD7and the gate of the seventh transistor M7. One end of the eighth resistor R8is coupled to the current source300, and the other end of the eighth resistor R8is coupled to the drain of the seventh transistor M7, the gate of the sixth transistor M6, and the cathode of the sixth Zener diode ZD6. The gate of the sixth transistor M6and the drain of the seventh transistor M7are coupled to the cathode of the sixth Zener diode ZD6, and the sources of the sixth transistor M6and the seventh transistor M7are coupled to the anode of the sixth Zener diode ZD6, the anode of the seventh Zener diode ZD7and the output voltage V+.

The fifth selecting circuit125may comprise a fifth diode D5, a ninth resistor R9, a tenth resistor R10, an eighth Zener diode ZD8, a ninth Zener diode ZD9, an eighth transistor M8and a ninth transistor M9. One end of the ninth resistor R9is coupled to the drain of the sixth transistor M6and the cathode of the fourth diode D4, and the other end of the ninth resistor R9is coupled to the cathode of the ninth Zener diode ZD9and the gate of the ninth transistor M9. One end of the tenth resistor R10is coupled to the current source300, and the other end of the tenth resistor R10is coupled to the drain of the ninth transistor M9, the gate of the eighth transistor M8, and the cathode of the eighth Zener diode ZD8. The gate of the eighth transistor M8and the drain of the ninth transistor M9are coupled to the cathode of the eighth Zener diode ZD8, and the sources of the eighth transistor M8and the ninth transistor M9are coupled to the anode of the eighth Zener diode ZD8, the anode of the ninth Zener diode ZD9and the output voltage V+.

The sixth selecting circuit126may comprise a sixth diode D6, an eleventh resistor R11, a twelfth resistor R12, a tenth Zener diode ZD10, a eleventh Zener diode ZD11, a tenth transistor M10and a eleventh transistor M11. One end of the eleventh resistor R11is coupled to the drain of the eighth transistor M8and the cathode of the fifth diode D5, and the other end of the eleventh resistor R11is coupled to the cathode of the eleventh Zener diode ZD11and the gate of the eleventh transistor M11. One end of the twelfth resistor R12is coupled to the current source300, and the other end of the twelfth resistor R12is coupled to the drain of the eleventh transistor M11, the gate of the tenth transistor M10, and the cathode of the tenth Zener diode ZD10. The gate of the tenth transistor M10and the drain of the eleventh transistor M11are coupled to the cathode of the tenth Zener diode ZD10, and the sources of the tenth transistor M10and the eleventh transistor M11are coupled to the anode of the tenth Zener diode ZD10, the anode of the eleventh Zener diode ZD11and the output voltage V+.

The diodes D1˜D6may be coupled to the drains of the first transistor M1, the second transistor M2, the fourth transistor M4, the sixth transistor M6, the eighth transistor M8and the tenth transistor M10respectively (e.g. the first diode D1is coupled to the drain of the first transistor M1). The Zener diodes ZD1˜ZD11may be coupled to the gates and sources of the transistors M1˜M11(e.g. one end of the first Zener diode ZD1is coupled to the gate of the first transistor M1and the other end of the first Zener diode ZD1is coupled to the source of the first transistor M1) to limit the gate-source voltages VGSof the transistors M1˜M11to protect the transistors M1˜M11. According to an embodiment of the disclosure, the transistors M1˜M11may be the Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) or Bipolar Junction Transistors (BJTs), but the disclosure should not be limited thereto. It should be noted that the voltage selecting circuit120comprises six stages of the selecting circuits, but the disclosure should not be limited thereto. The number of the selecting circuit can be adjusted based on the number of voltages generated by the boost circuit110.

In addition, as shown inFIG.3, the first switch circuit140may comprise a first switch S1and a second switch S2, and the first switch circuit140is coupled to the adjustable current source160; and the second switch circuit150may comprise a third switch S3and a fourth switch S4, and the second switch circuit150is coupled to the adjustable current source160. One end of the first switch S1may be coupled to the diode Da, and the other end of the first switch S1may be coupled to the first electrode input end E1. One end of the second switch S2may be coupled to the second electrode input end E2, and the other end of the second switch S2may be coupled to the ground. One end of the third switch S3may be coupled to the diode Db, and the other end of the third switch S3may be coupled to the second electrode input end E2. One end of the fourth switch S4may be coupled to the first electrode input end E1, and the other end of the fourth switch S4may be coupled to the ground. One end of the diode Da may be coupled to the first switch S1and the other end of the diode Da may be coupled to the voltage selecting circuit120. One end of the diode Db may be coupled to the third switch S3and the other end of the diode Db may be coupled to the voltage selecting circuit120. The control circuit130may be configured to control enabling or disabling of the first switch circuit140and the second switch circuit150to control the transformation between the positive voltage and the negative voltage. When the current flowing through the tissue impedance R is positive current (e.g. the current I1as shown inFIG.3), the control circuit130may enable the first switch circuit140(i.e. enable the first switch S1and the second switch S2) and disable the second switch circuit150(i.e. disable the third switch S3and the fourth switch S4), and the reference voltage Vrefin generated on the tissue impedance R may be transmitted from the diode Da to the voltage selecting circuit120. When the current flowing through the tissue impedance R is negative current (e.g. the current I2as shown inFIG.3), the control circuit130may enable the second switch circuit150(i.e. enable the third switch S3and the fourth switch S4) and disable the first switch circuit140(i.e. disable the first switch S1and the second switch S2), and the reference voltage Vrefin generated on the tissue impedance R may be transmitted from the diode Db to the voltage selecting circuit120. In addition, the control circuit130may control the current generated by the adjustable current source160. In the embodiment of the disclosure, the first switch circuit140and the second switch circuit150may be an H-bridge structure. Therefore, the currents of two directions (i.e. positive current and the negative current) can be generated to make the alternating current (AC) voltage can be used for the electrical stimulation. It should be noted that in the embodiment, the first switch circuit140and the second switch circuit150are an H-bridge structure, but the disclosure should not be limited thereto. In other embodiments, other switch circuit structures which can achieve equivalent effect also can be applied to the first switch circuit140and the second switch circuit150.

In addition, as shown inFIG.3, the voltage selecting circuit120may detect (or obtain) the reference voltage Vrefin generated on the tissue impedance R from the diode Da or the diode Db (i.e. the reference voltage Vrefin may be fed back to the voltage selecting circuit120from the tissue impedance R). The voltage selecting circuit120may select one of the voltages V1˜V6to be the output voltage V+ in order to adjust the power voltage immediately. The operation of the voltage selecting circuit120is illustrated based onFIGS.4A-4Dbelow.

FIG.4Ais a schematic diagram of the voltage selecting circuit120generating the output voltage V+ based on the reference voltage Vrefin according to an embodiment of the disclosure. In the embodiment, it is assumed that the reference voltage Vrefin the voltage selecting circuit120detecting (or obtaining) from the diode Da or the diode Db is 1V, and the reference voltage Vrefin is changed to 4V reference voltage Vref after the reference voltage Vrefin passes through the first register R1and the current source300. When the reference voltage Vref is 4V, the first diode D1is forward biased and the first transistor M1is enabled (i.e. the first transistor M1is “ON”). Therefore, the voltage V1(5V) is transmitted by the first diode D1, and after the voltage V1(5V) passes through the first transistor M1(the gate voltage is 4V and the drain voltage is 5V), the first transistor M1may output 3V of output voltage V+. That is to say, in the embodiment, the output voltage V+ is outputted by the first selecting circuit121. In addition, when the reference voltage Vref is 4V, the second diode D2, the third diode D3and the fourth diode D4are forward biased, the third transistor M3(the gate voltage is 5V), the fifth transistor M5(the gate voltage is 8V and the drain voltage is 3V) and the seventh transistor M7(the gate voltage is 8V and the drain voltage is 3V) are enabled/turned on (i.e. the third transistor M3, the fifth transistor M5, and the seventh transistor M7are “ON”), and the second transistor M2(the gate voltage is 3V and drain voltage is 10V), the fourth transistor M4(the gate voltage is 3V and the drain voltage is 15V) and the sixth transistor M6(the gate voltage is 3V and the drain voltage is 20V) are disabled (i.e. the second transistor M2, the fourth transistor M4and the sixth transistor M6are “OFF”). Therefore, voltages V2(10V), V3(15V) and V4(20V) may not be outputted by the second transistor M2, the fourth transistor M4and the sixth transistor M6respectively.

FIG.4Bis a schematic diagram of the voltage selecting circuit120generating the output voltage V+ based on the reference voltage Vrefin according to another embodiment of the disclosure. In the embodiment, it is assumed that the reference voltage Vrefin the voltage selecting circuit120detecting (or obtaining) from the diode Da or the diode Db is 6V, and the reference voltage Vrefin is changed to 9V reference voltage Vref after the reference voltage Vrefin passes through the first register R1and the current source300. When the reference voltage Vref is 9V, the first diode D1is reverse biased and the second diode D2is forward biased. Therefore, the voltage V1(5V) is not transmitted by the first diode D1and the voltage V2(10V) is transmitted by the second diode D2. In addition, when the reference voltage Vref is 9V, the first transistor M1(the gate voltage is 9V and drain voltage is 8V) and the second transistor M2(the gate voltage is 9V and drain voltage is 10V) are enabled (i.e. the first transistor M1and the second transistor M2are “ON”), and the third transistor M3(the gate voltage is 8V and the drain voltage is 9V) is disabled/turned off (i.e. the third transistor M3is “OFF”). Therefore, after the voltage V2(10V) passes through the second transistor M2, the second transistor M2may output 8V output voltage V+. That is to say, in the embodiment, the output voltage V+ is outputted by the second selecting circuit122. In addition, when the reference voltage Vref is 9V, the third diode D3and the fourth diode D4are forward biased, the fifth transistor M5(the gate voltage is 10V and the drain voltage is 8V) and the seventh transistor M7(the gate voltage is 13V and the drain voltage is 8V) are enabled (i.e. the fifth transistor M5and the seventh transistor M7are “ON”), and the fourth transistor M4(the gate voltage is 8V and the drain voltage is 15V) and the sixth transistor M6(the gate voltage is 8V and the drain voltage is 20V) are disabled (i.e. the fourth transistor M4and the sixth transistor M6are “OFF”). Therefore, voltages V3(15V) and V4(20V) may not be outputted by the fourth transistor M4and the sixth transistor M6respectively.

FIG.4Cis a schematic diagram of the voltage selecting circuit120generating the output voltage V+ based on the reference voltage Vrefin according to another embodiment of the disclosure. In the embodiment, it is assumed that the reference voltage Vrefin the voltage selecting circuit120detecting (or obtaining) from the diode Da or the diode Db is 11V, and the reference voltage Vrefin is changed to 14V reference voltage Vref after the reference voltage Vrefin passes through the first register R1and the current source300. When the reference voltage Vref is 14V, the first diode D1and second diode D2are reverse biased and the third diode D3is forward biased. Therefore, the voltage V1(5V) and the voltage V2(10V) are not transmitted by the first diode D1and the second diode D2and the voltage V3(15V) is transmitted by the third diode D3. In addition, when the reference voltage Vref is 14V, the first transistor M1(the gate voltage is 14V and drain voltage is 13V), the second transistor M2(the gate voltage is 14V and drain voltage is 13V) and the fourth transistor M4(the gate voltage is 14V and the drain voltage 15V) are enabled (i.e. the first transistor M1, the second transistor M2and the fourth transistor M4are “ON”), and the third transistor M3(the gate voltage is 13V and the drain voltage is 14V) and the fifth transistor M5(the gate voltage is 13V and the drain voltage is 14V) are disabled (i.e. the third transistor M3and the fifth transistor M5are “OFF”). Therefore, after the voltage V3(15V) passes through the fourth transistor M4, the fourth transistor M4may output 13V output voltage V+. That is to say, in the embodiment, the output voltage V+ is outputted by the third selecting circuit123. In addition, when the reference voltage Vref is 14V, the fourth diode D4is forward biased, the seventh transistor M7(the gate voltage is 15V and the drain voltage is 13V) is enabled (i.e. the seventh transistor M7is “ON”), and the sixth transistor M6(the gate voltage is 13V and the drain voltage is 20V) is disabled (i.e. the sixth transistor M6is “OFF”). Therefore, V4(20V) may not be outputted by the sixth transistor M6.

FIG.4Dis a schematic diagram of the voltage selecting circuit120generating the output voltage V+ based on the reference voltage Vrefin according to another embodiment of the disclosure. In the embodiment, it is assumed that the reference voltage Vrefin the voltage selecting circuit120detecting (or obtaining) from the diode Da or the diode Db is 16V, and the reference voltage Vrefin is changed to 19V reference voltage Vref after the reference voltage Vrefin passes through the first register R1and the current source300. When the reference voltage Vref is 19V, the first diode D1, second diode D2and the third diode D3are reverse biased and the fourth diode D4is forward biased. Therefore, the voltage V1(5V), voltage V2(10V) and the voltage V3(15V) are not transmitted by the first diode D1, the second diode D2and the third diode D3and the voltage V4(20V) is transmitted by the fourth diode D4. In addition, when the reference voltage Vref is 19V, the first transistor M1(the gate voltage is 19V and drain voltage is 18V), the second transistor M2(gate voltage is 19V and drain voltage is 18V), the fourth transistor M4(the gate voltage is 19V and the drain voltage 18V) and the sixth transistor M6(the gate voltage is 19V and the drain voltage is 20V) are enabled (i.e. the first transistor M1, the second transistor M2, the fourth transistor M4and the sixth transistor M6are “ON”), and the third transistor M3(the gate voltage is 18V and the drain voltage is 19V), the fifth transistor M5(the gate voltage is 18V and the drain voltage is 19V), and the seventh transistor M7(the gate voltage is 18V and the drain voltage is 19V) are disabled (i.e. the third transistor M3, the fifth transistor M5and the seventh transistor M7are “OFF”). Therefore, after the voltage V4(20V) passes through the sixth transistor M6, the sixth transistor M4may output 18V output voltage V+. That is to say, in the embodiment, the output voltage V+ is outputted by the fourth selecting circuit124.

Accordingly, the voltage selecting circuit120may select the output voltage V+ from the voltages V1˜V6based on the reference voltage Vrefin, and the output voltage V+ may be provided to the first switch circuit140, a second switch circuit150and the adjustable current source160to provide the electrical stimulation to the tissue impedance R. When the tissue impedance R is changed, the changed reference voltage Vrefin will be fed back to the voltage selecting circuit120to select the suitable output voltage V+.

It should be noted that,FIGS.4A-4Bare only used to illustrate the embodiments of the disclosure, but the disclosure should not be limited thereto.

FIG.5is a flow chart illustrating an electrical stimulation method according to an embodiment of the disclosure. The electrical stimulation method can be applied to the electrical stimulation device100. As shown inFIG.5, in step S510, in response to electrical stimulation, a control circuit130of the electrical stimulation device100may transmit a control signal to enable a boost circuit110of the electrical stimulation device100.

In step S520, the boost circuit110of the electrical stimulation device100generates a plurality of voltages V1˜V6, wherein each of the voltages V1˜V6has a different voltage value.

In step S530, a voltage selecting circuit120of the electrical stimulation device100may select one of the voltages V1˜V6based on a reference voltage Vrefin generated on a tissue impedance R to generate an output voltage V+.

According to an embodiment of the disclosure, in the electrical stimulation method, the voltage selecting circuit may comprise a plurality of stages of the selecting circuits, wherein the selecting circuits correspond to the voltages generated by the boost circuit respectively. In some embodiments, each stage of the selecting circuit may comprise at least a diode, a first Zener diode and a first transistor. The diode may be coupled to the boost circuit. The first drain of the first transistor may be coupled to the diode, the first source of the first transistor may be coupled to one end of the first Zener diode, and the first gate of the first transistor may be coupled to the other end of the first Zener diode. In some embodiments, except for the first stage, each stage of the selecting circuits may further comprise a second Zener diode and a second transistor. The second source of the second transistor may be coupled to one end of the second Zener diode, and the second gate of the second transistor may be coupled to the other end of the second Zener diode. According to an embodiment of the disclosure, the electrical stimulation method may further comprises that when the diode of a selecting circuit is forward biased, the first transistor is enabled and the second transistor is disabled, the selecting circuit may output the output voltage based on its corresponding voltage.

According to the electrical stimulation device and method of the disclosure, the voltage selecting circuit of the electrical stimulation device can be used to automatically select one voltage from a plurality of voltages based on a reference voltage on the tissue impedance to generate the output voltage. Therefore, in the electrical stimulation device and method of the disclosure, the output voltage can be adjusted immediately to reduce the power consumption of the electrical stimulation device and extend the service life of the electrical stimulation device. In addition, in the electrical stimulation device and method of the disclosure, the structure of the voltage selecting circuit of the electrical stimulation device may not occupy too much space of the electrical stimulation device. Therefore, the volume of the electrical stimulation can be reduced.

Use of ordinal terms such as “first”, “second”, “third”, etc., in the disclosure and claims is for description. It does not by itself connote any order or relationship.

The steps of the method described in connection with the aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module (e.g., including executable instructions and related data) and other data may reside in a data memory such as RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable storage medium known in the art. A sample storage medium may be coupled to a machine such as, for example, a computer/processor (which may be referred to herein, for convenience, as a “processor”) such that the processor can read information (e.g., code) from and write information to the storage medium. A sample storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in user equipment. Alternatively, the processor and the storage medium may reside as discrete components in user equipment. Moreover, in some aspects any suitable computer-program product may comprise a computer-readable medium comprising codes relating to one or more of the aspects of the disclosure. In some aspects a computer program product may comprise packaging materials.

The above paragraphs describe many aspects. Obviously, the teaching of the disclosure can be accomplished by many methods, and any specific configurations or functions in the disclosed embodiments only present a representative condition. Those who are skilled in this technology will understand that all of the disclosed aspects in the disclosure can be applied independently or be incorporated.

While the disclosure has been described by way of example and in terms of preferred embodiment, it should be understood that the disclosure is not limited thereto. Those who are skilled in this technology can still make various alterations and modifications without departing from the scope and spirit of this disclosure. Therefore, the scope of the present disclosure shall be defined and protected by the following claims and their equivalents.