Patent ID: 12224761

The same reference numbers or other reference designators are used in the drawings to illustrate the same or similar (in function and/or structure) features.

DETAILED DESCRIPTION OF THE INVENTION

The one or more embodiments described in this specification are implemented into an analog-to-digital converter (ADC) circuit module utilizing band-limited dither, as it is contemplated that such implementation is particularly advantageous in that context. However, it is also contemplated that aspects of these embodiments may be beneficially applied to ADCs of other architectures, as well as in other applications involving the quantization of analog signal levels. Accordingly, it is to be understood that the following description is provided by way of example only and is not intended to limit the true scope of this invention as claimed.

FIG.1illustrates an ADC circuit module in which example embodiments may be implemented. The ADC circuit module ofFIG.1may be implemented as a system, subsystem, or functional block or module in a large scale integrated circuit, such as a microcontroller, semi-custom or application-specific integrated circuit, or the like; alternatively, the ADC circuit module may itself be realized as a separate ADC integrated circuit. Other implementations of the ADC circuit module are contemplated and will be apparent to those skilled in the art. In the example ofFIG.1, the ADC circuit module includes an ADC100in a generalized form as including a sample-and-hold amplifier (SHA) circuit102followed by a quantizer104. SHA102receives an input analog time-varying signal x(t), and samples that signal x(t) at a sampling frequency fsto create sample sequence xs[n], where n is the index of a given value in the sequence. Quantizer104operates to generate an output sequence y[n] of digital codes, each code word having k bits and representative of the analog value of each sample in sequence xs[n]. The number k of bits in each code word of output sequence y[n] may range from 1 bit to as many as sixteen bits in modern ADCs.

According to these example embodiments, the analog signal x(t) input to SHA102is generated by adder112, which adds a dither signal d(t) generated by dither generation circuit110to the actual input signal i(t). Adder112may be implemented, for example, as an operational amplifier (op amp) circuit with inputs receiving the input signal i(t) and the dither signal d(t), and configured to produce analog signal x(t) based on a sum of signals i(t) and d(t) at its output. As discussed above, the addition of dither signal d(t) to the input signal i(t) improves the linearity of ADC100, specifically by reducing quantization error that is deterministically linked to the input signal x(t).

According to these example embodiments, the application of dither signal d(t) is non-subtractive, in that the dither applied at the input is not then subtracted from the values of output sequence y[n]. To avoid degradation of the signal-to-noise ratio (SNR) from this non-subtractive dither, dither generation circuit110includes a filter to band-limit the dither signal d(t) to frequencies that are not of interest in the system in which ADC100is implemented. For the example of analog-to-digital conversion of a radio frequency (RF) signal having a carrier frequency fcof on the order of 1 GHz, dither generation circuit110may include a low-pass filter with a cutoff frequency of on the order of 100 MHz, such that the spectrum of dither signal d(t) is generally limited to frequencies below 100 MHz. In many applications, including RF applications, the amplitude of dither signal d(t) can be significant, for example on the order of 10% of the full scale (FS) range of ADC100.

It has been observed, however, that spurious frequency components can be produced by the addition of large-signal (e.g., >10% of FS) dither, even if band-limited by a low-pass filter.FIG.2illustrates an example of a frequency spectrum, obtained by Fast Fourier Transform (FFT), of an example output sequence y[n] generated from an RF input signal i(t) with a carrier frequency fcof about 900 MHz into which a dither signal d(t) bandlimited to 100 MHz is applied. In the spectrum ofFIG.2, spike200illustrates the amplitude of the fundamental frequency (e.g., carrier frequency fc) of input signal i(t) at about 900 MHz. The spectrum of band-limited dither signal d(t) is shown inFIG.2by region210, with significant amplitudes at frequencies between 0 and about 100 MHz. However, as evident from region220of the spectrum ofFIG.2, phase noise is present in the output stream y[n] at frequencies “close-in” to the fundamental, or carrier, frequency. The second harmonic distortion (HD2) of ADC100is believed to cause intermodulation of the dither signal d(t) with the input signal i(t) that, along with the leakage of dither signal d(t) into common mode due to imbalance between positive and negative amplitudes (P/M imbalance) at the input circuit, can modulate the sampling instant of ADC100. The resulting multiplicative noise (e.g., “beating”) of the dither signal with the input signal frequency appears as phase noise, evident in region220ofFIG.2.

According to these example embodiments, noise “shaping” is applied in the generation of the dither signal d(t) in order to avoid this close-in phase noise at frequencies near the fundamental frequency of the signal being converted. In some embodiments, this noise shaping is implemented in the form of a high pass filter, with characteristics selected so that the resulting filtered dither attains a desired histogram distribution following quantization in the ADC. In other embodiments, a digital dither with the desired noise characteristics and distribution is generated and applied.

FIG.3AandFIG.3Billustrate example architectures of an analog-to-digital converter circuit module for converting an input analog signal i(t) to a sequence y(n) of digital code words. In each of these examples, the analog-to-digital conversion is performed by ADC100, which in this example may be constructed according to any one of a number of architectures, including, for example, pipelined A/D converters, successive approximation register A/D converters, sigma-delta ADCs (also referred to as delta-sigma ADCs), all-digital converters, scan conversion-based transient digitizers, and the like. Regardless of the type and construction of ADC100, dither is applied to the analog signal being converted by adder112, which receives input signal i(t) at one input and a time-varying dither signal d(t) at another input.

In the example architecture ofFIG.3A, the dither signal d(t) is generated by an analog dither generation circuit310. Dither generation circuit310includes dither generator312, which generates an analog dither signal at its output with the desired amplitude and frequency characteristics. Examples of an analog dither generator312suitable for use in this implementation include circuits based on noise diodes, amplifier circuits arranged to amplify the input voltage noise of a wideband bipolar op amp, and the like. In each case, the analog signal generated at the output of dither generator312is a wideband time-varying signal. According to this example embodiment, the output of dither generator is coupled to an input of analog noise shaping filter314, which is constructed to filter the wideband signal from dither generator312according to a frequency characteristic selected to reduce the close-in phase noise of the added dither signal d(t) relative to the fundamental tone (e.g., carrier signal) of input signal i(t). For example, noise-shaping filter314may be a second-order high pass analog filter, with a cutoff frequency selected to remove the primary components of the close-in phase noise around the fundamental tone of input analog signal i(t). For the example described above relative toFIG.2in which the fundamental tone of input signal i(t) is about 900 MHz and is affected by close-in phase noise at frequencies within about 1 MHz of that fundamental frequency, the cutoff frequency of noise-shaping filter314may be selected to be at about 1 MHz.

The filtered output from noise-shaping filter314is applied to an input of low pass analog filter316, which removes dither frequency components above a frequency of interest in the end system application (e.g., above at least the frequency of the fundamental tone). The filtered output d2(t) from low pass filter316is amplified to the desired amplitude by amplifier318, and applied as dither signal d(t) to adder112.

In the alternative to the arrangement shown inFIG.3A, noise-shaping filter314and low-pass filter316may be reversed in order, such that the wideband output from dither generator312is first filtered by low-pass filter316and then filtered by noise-shaping filter314. Other variations to the particular implementation shown inFIG.3Awill be apparent to those skilled in the art having reference to this specification.

According to another example embodiment, as shown inFIG.3B, the ADC circuit module includes digital dither generation circuit320. In this example, pseudorandom binary sequence (PRBS) generator322is constructed and operates to generate a digital PRBS Din[k] at a desired sample rate, from which dither signal d(t) is generated. PRBS generator322may be constructed as dedicated custom or semi-custom circuitry for generating the digital sequence, or alternatively may be implemented in programmable circuitry executing program instructions for generating the desired random sequence. The generated PRBS Din[k] is then applied to digital noise-shaping filter324, which in this example is implemented as a digital filter configured to attain the desired frequency characteristic. For example, and as will be described in further detail below, the filter characteristic of digital noise-shaping filter324may be that of a second-order high-pass filter, with a cutoff frequency selected to remove the primary components of the close-in phase noise around the fundamental tone of input analog signal i(t). Digital noise-shaping filter324accordingly produces noise-shaped sequence Df[k] at its output, which is coupled to an input of digital-to-analog converter (DAC)325. DAC325is constructed and operates to convert the noise-shaped digital sequence Df[k] to an analog signal da(t) at its output, which is coupled to the input of analog low pass filter326. As in the analog example ofFIG.3A, low pass filter326is configured to remove frequency components above a frequency of interest in the end system application (e.g., above at least the frequency of the fundamental tone), producing filtered analog dither signal df(t) at its output, which is coupled to an input of amplifier328. Amplifier328amplifies signal df(t) at its input to produce dither signal d(t) at an amplitude reasonably matching the full-scale range of ADC100. Dither signal d(t) is applied to an input of adder112for combining with input signal i(t) to produce the dithered input signal x(t) that is converted to digital by ADC100as described above.

As noted above, digital noise-shaping filter324is arranged to apply the desired noise shaping (e.g., high-pass filter characteristics) to reduce intermodulation of the dither signal d(t) with harmonics of the fundamental tone, and thus reduce close-in phase noise at frequencies near the fundamental tone.FIG.4Aillustrates a frequency spectrum402of dither signal d(t) as generated from simulation of an example implementation of the architecture ofFIG.3Bin an end application in which the carrier frequency of input signal i(t) is around 1 GHz, and in which the ADC circuit module is sensitive to phase noise within 1 MHz of that carrier frequency. In this example, digital noise-shaping filter324applies a second order high-pass digital filter characteristic (1−z−1)2to a dither sequence Din[k] generated by PRBS generator322of a one-bit PRBS sequence {−1, +1}. As shown inFIG.4A, the noise-shaping provided by filter324in this example results in a dither spectrum402in which the power at and below 1 MHz is on the order of 30 dB lower than at higher frequencies (e.g., 5 MHz and higher). For comparison, a dither signal d(t) generated from a 2-bit PRBS sequence but not filtered by a noise-shaping filter exhibits a relatively flat average power spectrum422over frequency, including at frequencies 1 MHz and below. Application of a dither signal d(t) with the relatively flat spectrum plot422ofFIG.4Acan result in close-in phase noise at frequencies near the fundamental or carrier tone, such as shown by noise region220ofFIG.2discussed above.

For example,FIG.4Billustrates the power spectrum432of a digital output sequence y[n] generated by ADC100in simulation of the architecture ofFIG.3Bfor the case of a 1-bit PRBS dither sequence noise-shaped by digital filter324to produce dither signal d(t) with spectrum402shown inFIG.4A. As evident fromFIG.4B, spectrum432includes a peak at a fundamental frequency of 1 GHz and reduced amplitudes at frequencies within a band of interest BOI of ±1 MHz on either side of that fundamental tone. In contrast,FIG.4Billustrates power spectrum442for the digital sequence y[n] produced by ADC100for the case of a digital dither signal d(t) of a 2-bit PRBS without noise-shaping (spectrum422ofFIG.4A). As evident fromFIG.4B, this power spectrum442exhibits significant noise amplitude within the band of interest BOI.

An important measure of signal quality for ADC circuit modules is the spurious-free dynamic range (SFDR), which can be defined as a ratio of the strength of the fundamental tone to that of the strongest spurious signal within the frequency band of interest. More specifically, the SFDR of an ADC corresponds to the ratio of the RMS signal amplitude (e.g., at the fundamental tone) to the RMS value of the peak spurious spectral component at the ADC output. It has been observed through simulation that a noise-shaping digital filter324with a second order high-pass digital filter characteristic (1−z−1)2, applied to a one-bit PRBS sequence {−1, +1} generated by PRBS generator322, produces a dither signal d(t) with the spectrum402ofFIG.4Athat, added to the analog input signal, can improve the SFDR for the ADC circuit module by on the order of 30 dB, while limiting phase noise at frequencies close-in to the fundamental signal tone.

FIG.4Cillustrates digital filter characteristic (1−z−1)2as a z-transform representation of a noise-shaping digital filter324configured as a second-order high-pass filter. As noted above, this high-pass filter characteristic has been observed to reduce multiplicative close-in noise in the band of interest close-in to the fundamental tone of the input signal, and as a result provide good SFDR without compromising on close-in phase noise.

FIG.4Dillustrates a normalized histogram470of a digital dither sequence generated from a 2-bit PRBS, without filtering by a noise-shaping digital filter, scaled over the full-scale range of ADC100(e.g., the quantization levels spaced apart by k code values over full-scale). As evident fromFIG.4D, histogram470exhibits four quantization levels: {−3, −1, +1, +3} with uniform distribution of values over those four quantization levels. In contrast, the quantization pattern produced from digital filter324ofFIG.4C, applying a second-order high pass filter characteristic (1−z−1)2to a one-bit PRBS sequence {−1, +1}, produces an output sequence Df[k] having five output quantization levels: {−4, −2, 0, +2, +4} with a non-uniform distribution.FIG.4Dillustrates normalized histogram460of this output sequence Df[k] from digital filter324over these five quantization levels, scaled over the full-scale range of ADC100. As shown inFIG.4D, the number of values at the −2 k and +2 k quantization levels in normalized histogram460is one-half that of the number of values at the −1 k, 0 k, and +1 k quantization levels. This five-level and non-uniform characteristic of histogram460, resulting from noise-shaping filter324in this example embodiment, has an effect of reducing the maximum input signal amplitude that can be supported by ADC100, as compared with the maximum input signal amplitude that could be supported for the case of a dither sequence exhibiting a uniform four-level characteristic. This reduction in the maximum supported input signal amplitude can limit the achievable SFDR performance of the ADC circuit module.

According to an alternative example embodiment, the SFDR and SNR performance of an ADC circuit module can be further optimized by frequency shaping a digital dither sequence that, when converted to analog, produces a uniform distribution of values over the available quantization levels. According to one alternative example embodiment, this combination can be attained by the use of one or more sigma-delta modulators to generate the digital dither sequence. More specifically, each sigma-delta modulator generates one bit of each value in a digital dither sequence that, upon conversion to analog by a DAC, produces a frequency-shaped dither signal that is both noise-shaped and exhibits a uniform histogram over its quantization levels.

Referring toFIG.5A, the construction and operation of an ADC circuit module including dither generation circuit500according to an example of this alternative embodiment is described. In this example, dither generation circuit500includes two 1-bit sigma-delta modulators502[1],502[0]. In this example, sigma-delta modulators502[1],502[0] each generate one bit D1[k], D0[k], respectively, of a digital word produced in each sampling period k (e.g., with D1[k] and D0[k] as the MSB and LSB, respectively). The digital sequence D[k] is converted to an analog signal da(t) by DAC512. The converted analog signal da(t) is low-pass filtered by analog low-pass filter514in this example, and the resulting filtered signal df(t) is amplified by amplifier516to produce the dither signal d(t). As shown in the architecture ofFIG.5A, this dither signal is added by adder112to the input signal i(t) to produce combined analog signal x(t), which in turn is applied to an input of ADC100for conversion to digital output sequence y[n].

Each of sigma-delta modulators502[1],502[0] includes an adder504with a positive input receiving an input level (e.g., at 0 V) and a negative input receiving feedback from the modulator output. Referring to modulator502[1] by example, adder504has an output coupled to an input of an integrator506, which applies a selected transfer function including an integration to the signal from adder504. For example, the transfer function applied by integrator506may be of a low pass type. The output of integrator506is coupled to an input of adder508. To attain the desired noise-shaping, modulator5021includes a 1-bit PRBS generator507, which generates an unshaped pseudo-random noise sequence en[k] within the sigma-delta loop, applied in this example to another input of adder508. The summed signal at the output of adder508is applied to the input of 1-bit quantizer510at each sampling period. Quantizer510quantizes the summed output from adder508, to produce a sequence of bits D1 [k] at its output at a binary level (e.g., either −1 or +1) from the signal at its input at the sampling rate of the modulator. The output D1[k] is applied as feedback to the negative input of adder504, such that the difference signal applied by adder to integrator506represents a difference between the previous output value (e.g., D1 [k−1]) and the 0 level at the input. Accordingly, each of modulators502[0],502[1] operates to generate a random sequence of −1 and +1 values at its sampling rate.

According to this example embodiment, output sequence D[k] generated by the combination of sigma-delta modulators502[0],502[1] will exhibit a high-pass characteristic, with the particular cutoff frequency and other characteristics determined by the modulator sampling frequency and loop transfer function. More specifically, modulators502[1],502[0] will generate a random sequence of −1 and +1 values with a power spectrum dominated by higher frequencies, as determined by the sampling frequency and by the transfer function of integrators506. In other words, the digital sequence D[k] generated by the modulators502[1],502[0] in this example ofFIG.5Awill produce a noise-shaped digital dither sequence D[k] from which the eventual dither signal d(t) is produced by DAC512, low-pass filter514and amplifier516. This noise-shaping provided by dither generation circuit500can limit the close-in phase noise relative to the fundamental tone in its ADC circuit module in similar manner as the high-pass filtered implementations described above relative toFIG.4AandFIG.4B.

FIG.5Billustrates a frequency spectrum520of dither signal d(t) as generated from an example implementation of the architecture ofFIG.5Ain an end application in which the carrier frequency of input signal i(t) is around 1 GHz, and in which the ADC circuit module is sensitive to phase noise within 1 MHz of that carrier frequency. In this example, as described above, sigma-delta modulators502[1],502[0] produce random bit sequences D1 [k], D0[k], respectively, and thus together produce a sequence D[k] of 2-bit digital words that has a high-pass frequency spectrum. Accordingly, the dither signal d(t) produced by DAC512, low-pass filter514and amplifier516exhibits a noise-shaped power spectrum520that, when applied to analog input signal i(t) and quantized by ADC100, can reduce the phase noise at frequencies close-in (within 1 MHz) of a fundamental tone in input signal i(t). As shown inFIG.5B, power spectrum520is similar in shape to dither spectrum402(fromFIG.4A), which corresponds to a second order high-pass digital filter characteristic (1−z−1)2applied to a one-bit PRBS sequence {−1, +1}. According to this implementation ofFIG.5A, dither spectrum520exhibits power levels for frequencies at and below 1 MHz on the order of 30 dB lower than at higher frequencies (e.g., 5 MHz and higher), and on the order of 30 dB lower than spectrum422for a dither signal d(t) generated from a 2-bit PRBS sequence but not filtered by a noise-shaping filter.

Additionally, dither generation circuit500constructed as shown inFIG.5Aaccording to this example embodiment provides a dither signal d(t) that, when quantized by a downstream ADC, is uniformly distributed over its possible values.FIG.5Cillustrates a normalized histogram of the distribution of quantized values based on a dither sequence D[k] generated by the two sigma-delta modulators502[1],502[0] of dither generation circuit500in the example implementation ofFIG.5A. According to this implementation, each modulator502[1],502[0] generates “1” and “0” data states with equal probability, resulting in the 2-bit digital dither sequence D[k] having four possible data states {00, 01, 10, 11} with uniform probabilities. This uniform distribution of dither sequence D[k] values as generated by sigma-delta modulators502[1],502[0] of dither generation circuit500maintains the maximum input signal amplitude that can be supported by ADC100. In addition, the noise-shaping provided by those modulators results in a dither signal d(t) that reduces multiplicative phase noise from the analog-to-digital conversion of an analog input signal at frequencies close-in to the fundamental tone of the input signal. This noise-shaping attribute along with the maximum input signal amplitude maintained by the uniform histogram can thus attain good SFDR performance and good close-in phase noise in the ADC circuit module.

It is further contemplated that more than two 1-bit sigma-delta modulators may be implemented in a dither generation circuit generating a digital dither sequence. For example, three 1-bit sigma-delta modulators arranged in the manner ofFIG.5Awill generate a digital sequence D[k] of 3-bit data words. Such alternative implementations are contemplated to also provide noise-shaping in the form of a high-pass spectrum in the analog dither signal, from a digital sequence D[k] with a uniform probability distribution over the available quantization levels (e.g., eight quantization levels for a 3-bit sequence).

Alternatively, the dither generation circuit may utilize a single 2-bit sigma-delta modulator to generate a digital dither sequence D[k] of 2-bit digital words, in place of the pair of 1-bit modulators502[1],502[0] as described above relative toFIG.5A. The resulting analog dither signal d(t) generated from this 2-bit sigma-delta modulator will exhibit a high-pass frequency spectrum in the same manner as described above relative toFIG.5AandFIG.5Band can thus reduce close-in phase noise for the analog-to-digital conversion of an analog input signal. It has been observed, however, that the digital sequence generated by a single 2-bit sigma-delta modulator will not be uniformly distributed over its four possible data states {00, 01, 10, 11}. As such, generation of a digital dither sequence using multiple 1-bit sigma-delta modulators will be advantageous over a single 2-bit (or other multiple-bit) modulator architecture from the standpoint of SFDR performance.

According to these example embodiments, an ADC circuit module is provided in which band-limited dither for addition to an analog input signal can be generated to reduce multiplicative noise in the power spectrum of the output digital sequence, specifically to reduce phase noise at frequencies close-in to a fundamental or carrier tone in the input signal. These example embodiments can also provide improvement in both measures of spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNR) of these ADC circuit modules.

As used herein, the terms “terminal”, “node”, “interconnection” and “pin” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection between or a terminus of a device element, a circuit element, an integrated circuit, a device, or other electronics or semiconductor component.

Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value means +/−10 percent of the stated value or, if the value is zero, a reasonable range of values around zero. Modifications are possible in the described examples, and other examples are possible within the scope of the claims.

A device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or re-configurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof.

A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, for example, by an end-user and/or a third-party. While, in some example embodiments, certain elements are included in an integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit and/or some features illustrated as being internal to the integrated circuit may be incorporated outside of the integrated. As used herein, the term “integrated circuit” means one or more circuits that are: (i) incorporated in/over a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and/or (iv) incorporated in/on the same printed circuit board.

Circuits described herein are reconfigurable to include the replaced components to provide functionality at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor.

Uses of the phrase “ground” in the foregoing description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description.

While one or more embodiments have been described in this specification, it is of course contemplated that modifications of, and alternatives to, these embodiments, such modifications and alternatives capable of obtaining one or more of the technical effects of these embodiments, will be apparent to those of ordinary skill in the art having reference to this specification and its drawings. It is contemplated that such modifications and alternatives are within the scope of the claims presented herein.