Patent ID: 12250813

DETAILED DESCRIPTION

Embodiments of the present invention have been achieved in view of circumstances described above and are to provide a semiconductor device and a manufacturing method of a semiconductor device that can suppress characteristic deterioration due to influences of oxidation treatment.

A semiconductor device according to the present embodiment includes a semiconductor substrate, a memory transistor, and a MOS transistor. The memory transistor includes at least a first silicon dioxide film and a first gate electrode positioned on the semiconductor substrate in order. The MOS transistor includes a second silicon dioxide film and a second gate electrode positioned on the semiconductor substrate in order. Any bird's beak is not generated in at least either the first silicon dioxide film or the first gate electrode of the memory transistor.

The embodiments of the present invention will now be explained below with reference to the drawings. In the embodiments described below, characteristic configurations and operations of a semiconductor device and a manufacturing method of a semiconductor device are mainly explained. However, the semiconductor device and the manufacturing method of a semiconductor device can include characteristic configurations and operations that are omitted in the following descriptions.

First Embodiment

FIG.1is a plan view illustrating a configuration example of a semiconductor device1. The semiconductor device1includes, for example, a memory cell region100and a control region200. The memory cell region100and the control region200are both formed on an upper surface of a same semiconductor substrate. The memory cell region100according to the present embodiment corresponds to a first region and the control region200according to the present embodiment corresponds to a second region.

The memory cell region100is, for example, a region where a non-volatile memory is formed. For example, any of a charge trap memory and a floating gate memory is formed as a non-volatile memory in the memory cell region100. A charge trap memory and a floating gate memory are also referred to as a “charge trap memory transistor” and a “floating gate memory transistor”, respectively.

In the charge trap memory, a gate dielectric film of a memory transistor has a stacked structure (an ONO structure) including a silicon dioxide film (an interlayer dielectric film), a silicon nitride film, a silicon dioxide film (a tunnel dielectric film). Charges are accumulated in discrete traps in the silicon nitride film near an interface with the silicon dioxide film (the tunnel dielectric film) on the side of the silicon substrate. This changes the threshold voltage of the memory transistor and therefore enables data to be stored therein. Such a memory transistor is referred to as a MONOS (Metal Oxide Nitride Oxide Semiconductor) or a SONOS (Silicon Oxide Nitride Oxide Semiconductor). The charge trap memory according to the present embodiment may be a charge trap memory having a so-called SONONOS structure or a so-called MONONOS structure where the silicon nitride film is replaced with another ONO structure.

In the floating gate memory, a floating gate electrode is provided between two layers of gate dielectric films of a memory transistor and data is stored therein by accumulating charges in the floating gate electrode. The floating gate memory according to the present embodiment may be a floating gate memory in which a gate dielectric film (an interlay dielectric film) on the side of a control gate is replaced with an ONO structure.

The control region200includes, for example, peripheral circuits other than the non-volatile memory. The control region200includes, for example, a control circuit, a sense amplifier, a column decoder, a row decoder, an input/output circuit, a power supply circuit, a processor such as a CPU (Central Processing Unit), various analog circuits, an external input/output circuit, and the like. The control region200is, for example, a region where a MOS (Metal-Oxide-Semiconductor) field-effect transistor (hereinafter, also a MOSFET or a MOS transistor) is formed. A MOSFET is formed as follows. An n-type MOS (NMOS) is generally formed by forming a silicon oxide film and a gate region thereon in a gate region on a p-type silicon substrate, and implanting a high concentration of impurity ions into drain and source regions to obtain an n-type (n+-type) semiconductor. A p-type MOS (PMOS) is formed by creating a region of an n layer by ion implantation into a p-type silicon substrate, forming a silicon oxide film and a gate region thereon in a gate region of the n-type implanted region, and implanting a high concentration of impurity ions into drain and source regions to obtain a p-type (p+-type) semiconductor. The MOS transistor according to the present embodiment can be either an n-type MOS (NMOS) or a p-type MOS (PMOS).

FIG.2is a sectional view illustrating a configuration example of the semiconductor device1according to the present embodiment. As illustrated inFIG.2, the semiconductor device1includes a semiconductor substrate10, and a charge trap memory transistor2and a MOS transistor3formed on the semiconductor substrate10. Hereinafter, the charge trap memory transistor2is also referred to as “memory transistor2” or “transistor2” and the MOS transistor3is also referred to as “transistor3”.

For example, a silicon (Si) wafer including P-type or N-type impurities is used as the semiconductor substrate10. N-type or P-type well regions11are formed in predetermined regions of the semiconductor substrate10. For example, boron (B) is used as the P-type impurities and phosphorus (P) or antimony (Sb) is used as the N-type impurities.

The memory transistor2includes a first silicon dioxide film (SiO2) (a tunnel dielectric film)31, a first silicon nitride film (Si3N4)32, a second silicon dioxide film (an interlayer dielectric film)33, and a first gate electrode41positioned in order on the semiconductor substrate10. The first silicon dioxide film (SiO2)31, the first silicon nitride film (Si3N4)32, and the second silicon dioxide film33constitute an ONO structure of gate dielectric films between the semiconductor substrate and the first gate electrode41. The first gate electrode41is, for example, constituted of polysilicon (polycrystalline silicon: PolySi) including doped impurities and having a conductivity. The memory transistor2is one example of a charge trap memory transistor and is not limited to this configuration.

A third silicon dioxide film (SiO2)35is formed on side surfaces of the first gate electrode41, the first silicon nitride film32, the second silicon dioxide film33. Sidewalls71,72, and73are formed of a silicon dioxide film (SiO2)71, a silicon nitride film (Si3N4)72, and a silicon dioxide film (SiO2)73, respectively, in order from the side of the first gate electrode41. An interlayer dielectric film80is further provided. The interlayer dielectric film80has openings at predetermined locations and wires91of aluminum (Al) or the like arranged on the interlayer dielectric film80are respectively connected to the gate electrode of the memory transistor2via plugs92of tungsten (W) or the like arranged in the openings of the interlayer dielectric film80.

The N-type or P-type well regions11are formed in the predetermined regions in the semiconductor substrate10. On the semiconductor substrate10, element isolation regions20are formed in trenches shallowly dug in the semiconductor substrate10. The element isolation regions20are, for example, STIs (Shallow Trench Isolations) and are obtained by embedding an insulating film such as a silicon dioxide film (SiO2) in the trenches shallowly dug in the semiconductor substrate10. In this way, the memory transistor2is formed in the element isolation regions20, and an element region surrounded by the element isolation regions20.

Extension regions61and62, a source region63, and a drain region64are formed below the sidewalls71,72, and73. The extension regions61and62are also referred to as “LDDs (lightly doped drains)”.

The MOS transistor3includes a fourth silicon dioxide film (SiO2)36and a second gate electrode51positioned in order on the semiconductor substrate10. The fourth silicon dioxide film36constitutes a gate dielectric film of the MOS transistor3. The second gate electrode51is, for example, constituted of polysilicon (PolySi) including doped impurities and having a conductivity. The rest of the configuration can be formed, for example, to have a same configuration as that of the memory transistor2. A metal silicide layer such as a cobalt silicide (CoSi) or a titanium silicide (TiSi) may be formed on the source region63and the drain region64of the transistors2and3. The MOS transistor3is an example of the MOS transistor and is not limited to this configuration.

A manufacturing method of the semiconductor device1according to the present embodiment is explained below.FIG.3is a flowchart illustrating a flow of the manufacturing method of the semiconductor device1according to the present embodiment. As illustrated inFIG.3, the element isolation regions20are formed in the semiconductor substrate10(Step S100), and the first gate electrode41and the ONO structure of the gate dielectric films31,32, and33of the memory transistor2are constituted (Step S102). Subsequently, a generation process of a gate oxide film (Step S104) is performed to constitute the fourth silicon dioxide film36and the second gate electrode51.

In this way, the fourth silicon dioxide film36and the second gate electrode51of the transistor3are constituted after the first gate electrode41and the ONO structure of the gate dielectric films31,32, and33of the memory transistor2are constituted. In this case, influences of the manufacturing process of the memory transistor2on the well region11, the fourth silicon dioxide film36, and the second gate electrode51can be suppressed. For example, in the control region200of the semiconductor device1, it is preferable to suppress influences on the control region200in a case of constituting the memory cell region100that is currently manufactured by the existing process and is designed later, and the like. Meanwhile, there is a risk that the oxidation treatment process (Step S104) at the time of formation of an oxide film in the transistor3of the control region200, and the like affects the memory transistor2. Therefore, the manufacturing method of the semiconductor device1according to the present embodiment has a process of forming a sacrificial polysilicon film on at least a part of the surface region of the first gate electrode41and the ONO structure of the gate dielectric films31,32, and33to prevent the oxidation treatment process at the time of formation of a gate oxide film in the transistor3from affecting the memory transistor2, which will be described in detail later.

FIGS.4to11and14to18are sectional views of the semiconductor device1according to the present embodiment in first to thirteenth processes.FIG.12is a diagram illustrating film formation characteristics of a silicon dioxide film.FIG.13are diagrams illustrating a comparison of bird's beaks.

FIG.4illustrates parts of a sectional view of the semiconductor substrate10in the first process of the semiconductor device1according to the present embodiment. As illustrated inFIG.4, the first process is a process of forming the element isolation regions20. In the first process, an insulating film such as a silicon dioxide film is embedded in trenches obtained by shallowly digging the semiconductor substrate10to form the element isolation regions20. The element isolation regions20are formed in the semiconductor substrate10, for example, by an STI (shallow trench isolation) method.

FIG.5illustrates parts of a sectional view of the semiconductor substrate10in the second process of the semiconductor device1according to the present embodiment. As illustrated inFIG.5, the second process is a process of forming the well region11of the memory transistor2.

FIG.6illustrates parts of a sectional view of the semiconductor substrate10in the third process of the semiconductor device1according to the present embodiment. As illustrated inFIG.6, the third process is a process of constituting the ONO structure of the gate dielectric films31,32, and33. The first silicon dioxide film31, the first silicon nitride film32, and the second silicon dioxide film33are formed in order on the semiconductor substrate10.

In the third process, the first silicon dioxide film31serving as a tunnel film is first formed. For example, the first silicon dioxide film31is formed by thermally oxidizing the surface of the semiconductor substrate10. The thermal oxidation treatment is performed, for example, by steam oxidation treatment using steam (H2O) and oxygen or nitrogen (N2). A temperature range in the thermal oxidation treatment is, for example, 650° C. to 900° C. Subsequently, the first silicon nitride film32serving as a charge accumulating layer is formed on the first silicon dioxide film31. The first silicon nitride film32is formed, for example, by a CVD (chemical vapor deposition) method using ammonia (NH3) and dichlorosilane (DCS, SiH2Cl2) as reactant gases. Next, the second silicon dioxide film33serving as a block film is formed on the first silicon nitride film32. The second silicon dioxide film33is formed, for example, by the CVD method using dichlorosilane and nitric oxide (NO) as reactant gases.

FIG.7illustrates parts of a sectional view of the semiconductor substrate10in the fourth process of the semiconductor device1according to the present embodiment. As illustrated inFIG.7, the fourth process is a process of generating a silicon dioxide film33aon a surrounding part of the first gate electrode41after the first gate electrode41and the ONO structure of the gate dielectric films31,32, and33are constituted. The first gate electrode41is formed on the second silicon dioxide film33by patterning a conductive film. For example, a resist is applied onto the conductive film, and exposure and development are performed by a photolithography method using a photomask to form the resist. The conductive film is dry-etched using the resist as a mask to form the first gate electrode41. Subsequently, the first silicon nitride film32and the second silicon dioxide film33in a region other than the first gate electrode41are removed, for example, by wet etching processing using a hot phosphoric acid and hydrofluoric acid. At this time, the silicon dioxide film33ais formed on the upper wall and side walls of the first gate electrode41in some cases to protect the conductive film. The silicon dioxide film33ais formed by thermally oxidizing the surface of the first gate electrode41. The thermal oxidation treatment is performed, for example, by steam oxidation treatment using steam (H2O) and oxygen or nitrogen (N2). In the following explanations, the silicon dioxide film33aformed to be integral with the second silicon dioxide film33is referred to as “second silicon dioxide film33”.

FIG.8illustrates parts of a sectional view of the semiconductor substrate10in the fifth process and a top view of the memory transistor2in the semiconductor device1according to the present embodiment. That is, the sectional view of the memory transistor2is a sectional view along a line A-A in the top view. As illustrated inFIG.8, the fifth process is a process of forming a sacrificial polysilicon film34. The sacrificial polysilicon film (polycrystalline silicon: PolySi)34is formed, for example, by a CVD method. The sacrificial polysilicon film34at this time is characterized in a thickness t34and is formed according to a thickness t36of the fourth silicon dioxide film36(seeFIGS.11and12described later).

FIG.9illustrates parts of a sectional view of the semiconductor substrate10in the sixth process of the semiconductor device1according to the present embodiment. As illustrated inFIG.9, the sixth process is a process of etching the sacrificial polysilicon film34. The sacrificial polysilicon film34on the semiconductor substrate10is removed by a predetermined thickness from the upper side of the semiconductor substrate10, for example, by dry etching. That is, the predetermined thickness of the sacrificial polysilicon film34is removed from the surface of the semiconductor substrate10in a direction indicated by an arrow Y. Accordingly, the sacrificial polysilicon film34is maintained in a state of being formed at least on a part of the surface region of the first gate electrode41and the ONO structure of the gate dielectric films31,32, and33.

FIG.10illustrates parts of a sectional view of the semiconductor substrate10in the seventh process of the semiconductor device1according to the present embodiment. As illustrated inFIG.10, the seventh process is a process of forming the well region11of the transistor3.

FIG.11illustrates parts of a sectional view of the semiconductor substrate10in the eighth process of the semiconductor device1according to the present embodiment. As illustrated inFIG.11, the eighth process is a process of generating the fourth silicon dioxide film36. First, the first silicon dioxide film31of the transistor2is peeled off, for example, by wet etching processing (for example, hydrofluoric acid treatment). The fourth silicon dioxide film36is formed by thermally oxidizing the surface of the semiconductor substrate10of the transistor2. The thermal oxidation treatment is performed, for example, by steam oxidation treatment using steam (H2O) and oxygen or nitrogen (N2). A temperature range in the thermal oxidation treatment is, for example, 650° C. to 900° C. The third silicon dioxide film35is an oxide film obtained by oxidizing the sacrificial polysilicon film34and having a thickness t35. The thickness t35of the third silicon dioxide film35generated by the film formation in the eighth process is increased due to the oxidation to be larger than the thickness of the sacrificial polysilicon film34. The thickness t35of the third silicon dioxide film35is, for example, set to be the thickness t36of the fourth silicon dioxide film36.

As illustrated inFIG.12, when silicon is oxidized, 45 percent of the oxidized region is formed in the silicon and 55 percent thereof is generated to have a thickness increased from the original silicon surface. More specifically, when the surface of the semiconductor substrate10is oxidized to form silicon dioxide (SiO2), the volume of the region where the oxidized silicon region (silicon dioxide (SiO2)) is formed increases. In this case, 55 percent of the formed silicon dioxide (SiO2) film is formed on the surface of the semiconductor substrate10. The remaining 45 percent of the silicon dioxide (SiO2) film is formed in the semiconductor substrate10.

Referring back toFIGS.8and11, the thickness t34of the sacrificial polysilicon film34is set to enable the third silicon dioxide film35to have a similar thickness to the thickness t36of the silicon dioxide film generated in the eighth process. With this setting of the thickness t34of the sacrificial polysilicon film34, the whole sacrificial polysilicon film34is oxidized when the fourth silicon dioxide film36has the target thickness t36. In other words, when the thickness t34of the sacrificial polysilicon film34is set to t36×0.45, the thickness t35of the third silicon dioxide film35becomes a similar thickness to the thickness t36of the silicon dioxide film generated in the eighth process. As is understood from this, when the thickness t34of the sacrificial polysilicon film34is set to t36×0.45, generation of the fourth silicon dioxide film36having the target thickness and oxidation of the entire region of the sacrificial polysilicon film34end almost simultaneously. Accordingly, oxidation in a region covered with the sacrificial polysilicon film34is suppressed.

On the other hand, a region remaining in the sacrificial polysilicon film34without being oxidized becomes a factor that causes reduction of the breakdown voltage, or the like. Therefore, setting the thickness t34of the sacrificial polysilicon film34to be larger than t36×0.45 is impermissible. The sacrificial polysilicon film34does not have an impact on the performance of the memory transistor2even when remaining. For example, the silicon dioxide film36can also be used as an offset spacer at the time of LDD implantation. Accordingly, it is desirable that the film thickness t34of the sacrificial polysilicon film34is equal to or lower than 45 percent of the total film thickness t36of the fourth silicon dioxide film36generated in the eighth process.

However, there is a risk that the oxidation gradually progresses in the silicon materials of the first gate electrode41and the ONO structure of the gate dielectric films31,32, and33if the sacrificial polysilicon film34is thinned to be thinner than t36×0.45. Therefore, the film thickness t34of the sacrificial polysilicon film34according to the present embodiment is set to, for example, not more than 45 percent of the total film thickness t36generated in the eighth process and not less than 35 percent thereof as a selective configuration example. This enables progress of the oxidation in the region of the first gate electrode41and the ONO structure of the gate dielectric films31,32, and33covered with the sacrificial polysilicon film34to be suppressed and can suppress occurrence of a bird's beak. The value of 35 percent according to the present embodiment is an example and the film thickness t34of the sacrificial polysilicon film34is not limited to not less than 35 percent of the total film thickness t36generated in the eighth process. For example, it suffices that the film thickness t34of the sacrificial polysilicon film34is larger than zero percent of the total film thickness t36generated in the eighth process. Accordingly, gradual progress of the oxidation in the silicon materials of the first gate electrode41and the ONO structure of the gate dielectric films31,32, and33is suppressed by the sacrificial polysilicon film34without the sacrificial polysilicon film34remaining unoxidized.

The left drawing inFIG.13is a sectional view of the gate dielectric films31,32, and33in a case in which the thickness of the sacrificial polysilicon film34is 45 percent and the right drawing is a sectional view of the gate dielectric films31,32, and33in a case in which the sacrificial polysilicon film34is not provided. In the left drawing inFIG.13, all film thicknesses of the gate dielectric films31,32, and33are uniform and are ideal in terms of the performance. On the other hand, in the right drawing inFIG.13, the oxidation gradually progresses in the first gate electrode41and the gate dielectric films31,32, and33, so that, for example, silicon dioxide (SiO2) is formed, the first gate electrode41deforms, and the thickness of at least any of the gate dielectric films31,32, and33increases. In this way, a region where the volume is increased is produced due to bird's beaks. A bird's beak according to the present embodiment means gradual progress (sneaking) of the oxidation. Particularly, a bird's beak is likely to be generated in edge regions. If such a bird's beak is generated, the performance of the memory transistor2degrades.

Return to the rest of the explanations of the manufacturing process of the semiconductor device1.FIG.14illustrates parts of a sectional view of the semiconductor substrate10in the ninth process of the semiconductor device1according to the present embodiment. As illustrated inFIG.14, the ninth process is a process of forming the second gate electrode51of the transistor3. The second gate electrode51is formed on the fourth silicon dioxide film36by patterning a conductive film. For example, a resist is applied onto the conductive film, and exposure and development are performed by a photolithography method using a photomask to form the resist. The second gate electrode51is formed by dry-etching the conductive film using the resist as a mask.

FIG.15illustrates parts of a sectional view of the semiconductor substrate10in the tenth process of the semiconductor device1according to the present embodiment. As illustrated inFIG.15, the tenth process is a process of forming the extension regions61and62of the transistor2. For example, a dopant (for example, ions of impurities such as arsenic or phosphorus) required to form the extension regions61and62is implanted into the semiconductor substrate10of the transistor2.

FIG.16illustrates parts of a sectional view of the semiconductor substrate10in the eleventh process of the semiconductor device1according to the present embodiment. As illustrated inFIG.16, the eleventh process is a process of forming the extension regions61and62of the transistor3. For example, a dopant (for example, ions of impurities such as arsenic or phosphorus) required to form the extension regions61and62is implanted into the semiconductor substrate10of the transistor3.

FIG.17illustrates parts of a sectional view of the semiconductor substrate10in the twelfth process of the semiconductor device1according to the present embodiment. As illustrated inFIG.17, the twelfth process is a process of forming the sidewalls71,72, and73of the transistors2and3.

FIG.18illustrates parts of a sectional view of the semiconductor substrate10in the thirteenth process of the semiconductor device1according to the present embodiment. As illustrated inFIG.18, the thirteenth process is a process of forming the sources63and the drains64of the transistors2and3. The interlayer dielectric film80is formed after the thirteenth process, and openings are formed by processing the interlayer dielectric film80. Subsequently, as illustrated inFIG.2, the wires91such as aluminum (Al) arranged on the interlayer dielectric film are connected to the gate electrodes of the transistors2and3via the plugs92such as tungsten (W) arranged in the openings of the interlayer dielectric film80, respectively.

As described above, after at least the first silicon dioxide film (SiO2) (the tunnel dielectric film)31and the first gate electrode41are formed in the memory cell region100of the semiconductor substrate the sacrificial polysilicon film34is formed in the surface region for the purpose of protecting the semiconductor substrate10, and the fourth silicon dioxide film (SiO2)36(the gate dielectric film) is formed in the control region200. Accordingly, even when oxidation treatment is performed to form the fourth silicon dioxide film (SiO2)36, gradual progress of the oxidation in the first silicon dioxide film (SiO2) (the tunnel dielectric film)31and the first gate electrode41in the region covered with the sacrificial polysilicon film34can be suppressed. The thickness t34of the sacrificial polysilicon film34is set to a thickness according to the total film thickness t36of the fourth silicon dioxide film36generated by subsequent oxidation treatment (the eighth process). This enables the timing when generation of the fourth silicon dioxide film36having a target thickness ends and the timing when oxidation in the entire region of the sacrificial polysilicon film34ends to be matched. Therefore, progress of the oxidation into the region where the surface is covered with the sacrificial polysilicon film34can be suppressed with no unoxidized region remaining in the sacrificial polysilicon film34. By thus setting the thickness t34of the sacrificial polysilicon film34to a thickness according to the total film thickness t36of the fourth silicon dioxide film36generated by the subsequent oxidation treatment (the eighth process), generation of a bird's beak in a predetermined region can be suppressed even when the oxidation treatment is performed.

First Modification of First Embodiment

A manufacturing method of the semiconductor device1according to a first modification is different from the manufacturing method of the semiconductor device1according to the first embodiment in further forming a resist82in the memory transistor2in the process of forming the sacrificial polysilicon film34in the fifth process (FIG.8). Differences between the manufacturing method of the semiconductor device1according to the first embodiment and the manufacturing method of the semiconductor device1according to the first modification are described below.

FIG.19is a sectional view of the semiconductor substrate10in a fifth process of an embodiment according to the first modification of the first embodiment. As illustrated inFIG.19, the resist82is stacked on the memory transistor2.

FIG.20is a sectional view of the semiconductor substrate10in a sixth process according to the first modification of the first embodiment. As illustrated inFIG.20, the sixth process according to the first modification of the first embodiment is a process of etching the sacrificial polysilicon film34. The sacrificial polysilicon film34on the transistor3is removed, for example, by dry etching. In this case, the sixth process is different from that in the manufacturing method of the semiconductor device1according to the first embodiment in that the resist82prevents the whole film of the sacrificial polysilicon film34on the transistor3from being removed by the etching.

FIG.21illustrates parts of a sectional view of the semiconductor substrate10in an eighth process according to the first modification of the first embodiment. As illustrated inFIG.21, an oxide film35acovering the upper surface of the transistor2is formed in the eighth process according to the first modification of the first embodiment.

In this way, in the manufacturing method of the semiconductor device1according to the first modification of the first embodiment, the whole of the sacrificial polysilicon film34on the transistor2is maintained when the sacrificial polysilicon film34on the transistor3is removed by etching. Therefore, gradual progress of the oxidation in the upper surface of the transistor2can be suppressed in the process of generating the fourth silicon dioxide film36.

Second Modification of First Embodiment

A second modification of the first embodiment is different from the first embodiment in that the memory transistor2is a floating gate memory transistor4. Differences between the semiconductor device1according to the first embodiment or the first modification and the semiconductor device1according to the second modification are described below.

FIG.22is a sectional view illustrating a configuration example of the semiconductor device1according to the second modification of the first embodiment. As illustrated inFIG.22, the semiconductor device1includes the semiconductor substrate10, the floating gate memory transistor4formed on the semiconductor substrate10, and the MOS transistor3. The memory transistor4is one example of the floating gate memory transistor and the memory transistor4is not limited to this configuration.

The memory transistor4is different from the charge trap memory transistor2in including the silicon dioxide film31, a third gate electrode94made of polysilicon, a silicon dioxide film (an interlayer dielectric film)95, and a floating gate electrode96.

FIG.23illustrates parts of a sectional view of the semiconductor substrate10in a fourth process of the semiconductor device1according to the second modification of the first embodiment. As illustrated inFIG.23, the fourth process according to the second modification of the first embodiment is a process of forming the third gate electrode94, the silicon dioxide film (the interlayer dielectric film)95, and the floating gate electrode96, and subsequently generating a silicon dioxide film on the periphery of the third gate electrode94and the floating gate electrode96. The rest of the manufacturing procedure is similar to that of the semiconductor device1according to the first embodiment, or the first modification of the first embodiment. Therefore, explanations thereof are omitted. Since the sacrificial polysilicon film34is thus formed after the third gate electrode94, the silicon dioxide film (the interlayer dielectric film)95, and the floating gate electrode96are formed, generation of a bird's beak can be suppressed even when the fourth silicon dioxide film36is formed.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms and various omissions, substitutions, and changes may be made without departing from the spirit of the inventions. The embodiments and their modifications are intended to be included in the scope and the spirit of the invention and also in the scope of the invention and their equivalents described in the claims.