Patent ID: 12230324

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present specification discloses a pre-charge circuit and a masking circuit that are capable of determining whether to mask a comparison result of a basic element of a content addressable memory (CAM) and thereby fulfill the purpose of reducing the complexity of CAM circuit design. The pre-charge circuit and the masking circuit of the present disclosure are applicable to a CAM having an NOR type match line architecture; for instance, the pre-charge circuit of the present disclosure can replace each of the pre-charge circuits220ofFIG.2, and can receive a word line (WL) signal and a write enablement (WE) signal to operate accordingly in comparison with the pre-charge circuit220. In addition, the pre-charge circuit of the present disclosure can receive a system clock generated by a timing controller and operate accordingly. The generation and control of the WL signal, the WE signal, and the system clock can be realized with known/self-developed techniques which fall without the scope of the present disclosure, and their details are omitted here.

FIG.3shows an embodiment of the pre-charge circuit of the present disclosure. The pre-charge circuit300ofFIG.3includes a masking control circuit310, a charge control circuit320, and a discharge control circuit330. These circuits are described in the following paragraphs respectively.

Please refer toFIG.3. The masking control circuit310is configured to generate a masking signal MS according to a WL signal and a WE signal. When both the WL signal and the WE signal are at a first level (e.g., a logical high level such as a level having a logical value “1”), the masking signal MS is a first masking signal. When the WL signal and the WE signal are at different levels respectively, the masking signal MS is a second masking signal that is different from the first masking signal. For instance, when both the WL signal and the WE signal are at a second level (e.g., a logical low level such as a level having a logical value “0”), the masking signal MS is the second masking signal. It is noted that in this specification the description “a signal at a level” can be interpreted as “the level of a signal falling within a predetermined range”.

Please refer toFIG.3. The charge control circuit320is configured to generate a charge control signal (e.g., the charge control signal CG ofFIG.4) according to a match line pre-charge signal MLPR and the masking signal MS and thereby determine whether to charge a match line of a CAM. When the masking signal MS is the first masking signal, the masking signal MS masks the variation of the match line pre-charge signal MLPR to allow the charge control signal to be free from the variation of the match line pre-charge signal MLPR; in other words, the charge control signal cannot perceive the variation of the match line pre-charge signal MLPR. When the masking signal MS is the second masking signal, the masking signal MS does not mask the variation of the match line pre-charge signal MLPR to let the charge control signal vary with the variation of the match line pre-charge signal MLPR.

Please refer toFIG.3. The discharge control circuit330is configured to generate a discharge control signal (e.g., the discharge control signal DCG ofFIG.4) and thereby determine whether to discharge the charges of the match line of the CAM. When the masking signal MS masks the variation of the match line pre-charge signal MLPR, the discharge control signal is used for discharging the charges of the match line.

FIG.4shows an embodiment of the masking control circuit310, the charge control circuit320, and the discharge control circuit330. The masking control circuit310includes a first NAND gate312that is configured to generate the masking signal MS according to the WL signal and the WE signal. The charge control circuit320includes a second NAND gate322that is configured to generate a charge control signal CG according to the match line pre-charge signal MLPR and the masking signal MS. The charge control circuit320further includes a first switch324(e.g., a PMOS transistor) that is configured to couple a charge terminal (e.g., a power supply terminal VDD) with the match line or decouple the charge terminal from the match line according to the charge control signal CG. The discharge control circuit330includes an inverter322that is configured to generate a discharge control signal DCG according to the masking signal MS. The discharge control circuit330further includes a second switch334(e.g., an NMOS transistor) that is configured to couple the match line with a discharge terminal (e.g., a grounding terminal GND) or decouple the match line from the discharge terminal according to the discharge control signal DCG.

It is noted that the combination of the first NAND gate312, the second NAND gate322, and the inverter332ofFIG.4can be replaced with another combination of logic gates, which means that the present invention is not limited to the embodiment ofFIG.4. Since people having ordinary skill in the art can appreciate how to fulfill the above-mentioned replacement in accordance with the present disclosure and the common knowledge of this technical field, redundant description is omitted here.

It is also noted that the charge control circuit320ofFIG.3can optionally be omitted according to the demand for implementation. Providing the charge control circuit320is omitted, the circuit ofFIG.3functions as a masking circuit including the masking control circuit310and the discharge control circuit330; in this case, the masking circuit can disregard whether the aforementioned match line is charged. More specifically, when the masking circuit discharges the charges of the match line, even though the match line is charged according to the aforementioned match line pre-charge signal MLPR at the same time, the discharge path between the charge terminal and the discharge terminal will not substantially influence the operation of the masking circuit. In order to prevent the masking circuit from being influenced by the discharge path, people having ordinary skill in the art can use any known/self-developed manner to prevent the match line from being pre-charged and discharged concurrently. For example, a timing control manner can be exerted on the WE signal and/or the match line pre-charge signal MLPR to achieve the following effects: during the phase of writing data into the CAM, when the masking signal MS is the first masking signal (i.e., the WE signal is at the first level) to discharge the charges of the match line, the match line pre-charge signal MLPR is at the second level so that the match line won't be pre-charged. The WL signal and the WE signal can be replaced with other kinds of signals as long as such replacement is practicable; the discharge control circuit330can be replaced with a level control circuit (e.g., a circuit equivalent to the discharge control circuit330) while the discharge terminal can be replaced with a predetermined-level terminal whose voltage level is predetermined.

FIG.5shows another embodiment of the pre-charge circuit of the present disclosure. The pre-charge circuit500ofFIG.5includes a masking control circuit510, a charge control circuit520, and a discharge control circuit530. These circuits are described in the following paragraphs respectively.

Please refer toFIG.5. The masking control circuit510is configured to couple a charge terminal (e.g., a power supply terminal VDD) with the charge control circuit520or decouple the charge terminal from the charge control circuit520according to a WL signal and a WE signal. When any of the WL signal and the WE signal is at a first level (e.g., a logical low level such as a level having a logical value “0”), the masking control circuit510couples the charge terminal with the charge control circuit520. When both the WL signal and the WE signal are not at the first level, the masking control circuit510decouples the charge terminal from the charge control circuit520. For example, when both the WL signal and the WE signal are at a second level (e.g., a logical high level such as a level having a logical value “1”), the masking control circuit510decouples the charge terminal from the charge control circuit520.

Please refer toFIG.5. The charge control circuit520is configured to determine whether to charge a match line (ML) of a CAM according to a match line pre-charge signal MLPR. When the match line pre-charge signal MLPR is at the second level (e.g., a logical high level), the charge control circuit520determines to charge the match line. When the match line pre-charge signal MLPR is at the first level (e.g., a logical low level), the charge control circuit520determines not to charge the math line.

Please refer toFIG.5. The discharge control circuit530is configured to determine whether to discharge the charges of the match line to a discharge terminal (e.g., a grounding terminal GND) according to the WL signal and the WE signal. When both the WL signal and the WE signal are at the second level (e.g., a logical high level), the discharge control circuit530determines to discharge the charges of the match line. When any of the WL signal and the WE signal is not at the second level (e.g., when at least one of the WL signal and the WE signal is not at a logical high level), the discharge control circuit530determines not to discharge the charges of the match line. For example, when any of the WL signal and the WE signal is at the first level (e.g., a logical low level), the discharge control circuit530determines not to discharge the charges of the match line.

FIG.6shows an embodiment of the masking control circuit510, the charge control circuit520, and the discharge control circuit530ofFIG.5. The masking control circuit510includes a first switch (e.g., a PMOS transistor) and a second switch514(e.g., a PMOS transistor). The first switch is coupled between a charge terminal VDD and the charge control circuit520, and configured to couple the charge terminal VDD with the charge control circuit520or decouple the charge terminal VDD from the charge control circuit520according to the WE signal. The second switch is coupled between the charge terminal VDD and the charge control circuit520, and configured to couple the charge terminal VDD with the charge control circuit520or decouple the charge terminal VDD from the charge control circuit520according to the WL signal.

Please refer toFIG.6. The charge control circuit520includes an inverter522and a third switch524(e.g., a PMOS transistor). The inverter522is configured to generate an inverted match line pre-charge signal according to the match line pre-charge signal MLPR and thereby determine whether to charge the match line. The combination of the inverter522and the third switch524can be replaced with a single switch (e.g., an NMOS transistor), and the logic to control the single switch is opposite to the logic to control the third switch524. The third switch524is configured to couple the masking control circuit510with the match line or decouple the masking control circuit510from the match line according to the inverted match line pre-charge signal.

Please refer toFIG.6. The discharge control circuit530includes a fourth switch532(e.g., an NMOS transistor) and a fifth switch534(e.g., an NMOS transistor). The fourth switch532is coupled between the match line and the fifth switch534, and configured to couple the match line with the fifth switch534or decouple the match line from the fifth switch534according to the WL signal. The fifth switch534is coupled between the fourth switch532and a discharge terminal GND, and configured to couple the fourth switch542with the discharge terminal GND or decouple the fourth switch542from the discharge terminal GND according to the WE signal. In an alternative embodiment, the fourth switch532is turned on/off according to the WE signal while the fifth switch534is turned on/off according to the WL signal.

It is noted that each of the aforementioned match lines of a CAM can be coupled to a back-end circuit (not shown) of the CAM through a sense amplifier (not shown). The sense amplifier is configured to sample the signal of the match line during a latch active period and thereby output a sample signal level as a match output to the back-end circuit. Since the setting and operation of the sense amplifier and back-end circuit can be realized with known/self-developed techniques which fall beyond the scope of the present disclosure, their details are omitted here.

FIG.7shows a signal relation diagram in regard to the period of a writing operation of a CAM array. The signals shown inFIG.7include a system clock SCLK for the CAM array, a match line pre-charge signal MLPR, a WL signal, a WE signal, a match line (ML) signal (i.e., the signal of a match line), a sense amplifier latch active (SA Latch Active) signal (i.e., the latch active signal of a sense amplifier), and a match output MO. As shown inFIG.7, in each cycle of the system clock SCLK, the match line pre-charge signal MLPR enters an evaluation phase for comparison first, and then enters a pre-charge phase. When both the WL signal and the WE signal are at a high level, the aforementioned discharge control circuit330/530, for example, discharges the charges of the match line to lower the level of the ML signal as illustrated with the marked region “discharging charges of match line” of the ML signal inFIG.7, and thereby makes the level of the match output MO have a logical value “0” as illustrated with the marked region “logical value “0”” of the match output MO inFIG.7.FIG.8shows another signal relation diagram in regard to the period of a writing operation of a CAM array. In comparison withFIG.7, the match line pre-charge signal MLPR enters a pre-charge phase first and then enters an evaluation phase for comparison in each cycle of the system clock SCLK ofFIG.8.

It is noted that each row of the CAM cells210ofFIG.2can be integrated into a known hierarchical architecture. This hierarchical architecture shares a global match line, and the pre-charge circuit300/500which can take the place of the pre-charge circuit220ofFIG.2can optionally mask the variation of the match line pre-charge signal MLPR as mentioned in the preceding paragraphs and thereby control the signal level of the global match line. In brief, the pre-charge circuit300/500ofFIG.3/5is applicable to multiple kinds of CAMs, especially to CAMs having different kinds of NOR type match line architectures.

It is noted that people of ordinary skill in the art can selectively use some or all of the features of any embodiment in this specification or selectively use some or all of the features of multiple embodiments in this specification to implement the present invention as long as such implementation is practicable; in other words, the present invention can be carried out flexibly in accordance with the present disclosure.

To sum up, the masking circuit and pre-charge circuit of the present disclosure can determine whether to mask the comparison result of a basic element of a CAM, and this is helpful to reduce the circuit design complexity of the CAM and can reduce the design and manufacturing cost of the CAM.

The aforementioned descriptions represent merely the preferred embodiments of the present invention, without any intention to limit the scope of the present invention thereto. Various equivalent changes, alterations, or modifications based on the claims of the present invention are all consequently viewed as being embraced by the scope of the present invention.