Patent ID: 12256552

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Throughout the description herein, unless other specified, the same reference numeral in different figures refers to the same or similar component formed by a same or similar method using a same or similar material(s).

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In some embodiments, a ferroelectric film with random polarization directions is formed, which has a plurality of (e.g., three or more) effective coercive fields. Ferroelectric field-effect transistors (FeFET) built using the disclosed ferroelectric film are disclosed. Each of the disclosed FeFETs has a plurality of (e.g., three or more) programmable threshold voltage values that are set by a programming voltage. Ferroelectric tunnel junctions (FTJs) built using the disclosed ferroelectric film are disclosed. Each of the disclosed FTJs has a plurality of (e.g., three or more) programmable electrical resistance values that are set by a programming voltage. The disclosed FeFETs and FTJs are used to form memory cells with a 1T1FeFET or 1T1FTJ structure. The memory cells are used to form a memory array that is used in analog computing for AI/ML applications.

FIG.1illustrates a cross-sectional view of a ferroelectric film250with random polarization directions, in an embodiment. The ferroelectric (FE) film250has a plurality of grains (e.g., particles), such as grains201A,201B, and201C, which grains are formed in one or more layers of grains of the FE film250. The grains (e.g.,201A,201B, and201C) may be collectively referred to as grains201for ease of description herein.

As illustrated inFIG.1, each of the grains201has a random polarization direction (illustrated as an arrow within each grain) such that the grains in the FE film250have many different polarization directions. The grains of the FE film250may also have different sizes (referred to as grain sizes). The FE film250(which has non-uniform polarization directions) differs from an FE film having a uniform polarization direction, where the polarization directions of all the grains in the FE film are along a same or similar direction. For ease of discussion, the FE film having a uniform polarization direction may be referred to as a uniform FE film hereinafter.

For a uniform FE film with the same polarization direction and coercive field (Ec) for all of the grains, each of the grains has two possible polarization directions that are opposite to each other, and the polarization directions of all the grains are aligned (e.g., parallel to each other). When an electrical field applied to this uniform FE film has an effective field along the polarization direction higher than the Ecof the uniform FE film, the polarization directions of all the grains in this uniform FE film are switched to a first direction. Similarly, when the electrical field applied to this uniform FE film has an effective field along the polarization direction smaller than, e.g., −Ec, the polarization directions of all the grains in the uniform FE film switch to a second direction opposite the first direction. The polarization switching characteristic of the uniform FE film has a hysteresis loop and may have a shape similar to one of the Q-V curves inFIG.2B(see description below). Since this uniform FE film only has two different (e.g., opposite) possible polarization directions, devices built using the uniform FE film may only have two different states. For example, a ferroelectric field-effect transistor (FeFET) built using the uniform FE film may only has two different threshold voltage values, each corresponding to a polarization state. As another example, a ferroelectric tunnel junction (FTJ) built using the uniform FE film may only has two different tunneling electroresistance (TER) values, each corresponding to a polarization state of the uniform FE film.

For the FE film250ofFIG.1, each of the grains of the FE film250has two possible polarization directions that are opposite to each other, and the polarization direction of each grain may be random (e.g., uncorrelated with the polarization direction of another grain). When an electric field is applied, e.g., along the thickness T direction, the effective electric field along a direction parallel to each grain's polarization direction is different. For ease of discussion, the effective electric field along a direction parallel to a grain's polarization direction is simply referred to as the effective electric field of the grain. One skilled in the art will readily appreciate that the effective electric field of each grain may be calculated by performing a vector decomposition of the electric field applied.

Due to the random polarization directions of the grains of the FE film250, as the electric field applied along the thickness T direction gradually increases over time, the effective electrical fields of each of the grains may exceed its respective coercive fields at different time, and as a result, the polarization direction of each of the grains may switch to its respective first direction at a different time. Similarly, when the electric field decrease gradually over time, the polarization direction of each of the grains may switch to its respective second direction at a different time. Therefore, when viewed as a whole, the FE film250has a plurality of different states (e.g., more than two different states) that corresponds to the plurality of polarization direction switching in the FE film250. In other words, the FE film250has a plurality of different states that can be set (e.g., programmed) using a gradually (e.g., continuously) increasing and/or a gradually (e.g., continuously) decreasing electric field (or electric voltage). The plurality of different states of the FE film250may be advantageously used to form analog NVM synapse suitable for analogy computing for AI/ML applications, as discussed in more details below.

FIGS.2A,2B, and2Cillustrate the polarization switching characteristics of the ferroelectric film250ofFIG.1, in an embodiment. InFIG.2A, the FE film250is illustrated as having five grains labeled with numerals 1, 2, 3, 4, and 5. The number of grains illustrated inFIG.2Ais merely an example, and the FE film250may have any suitable number of grains. The five subplots (each in a different row) inFIG.2Ashow the same FE film250, but in each subplot, a different grain is labeled with a different numeral. The five subplots (each in a different row) inFIG.2Billustrate five Q-V curves for the five different grains of the FE film250, where each Q-V curve corresponds to a respective labeled grain in a same row inFIG.2A.FIG.2Cshows a combined Q-V curve for the FE film250when contributions from all the grains (e.g., 1, 2, 3, 4, and 5) are considered. One skilled in the art will readily appreciate that for each Q-V curve inFIG.2B, the X-axis shows the electric field applied to the FE film250along the thickness (see TinFIG.1) direction of the FE film250, and the Y-axis shows the direction and the strength of the remnant polarization of the grain along the thickness direction. Note that each of the Q-V curves has a hysteresis loop around the origin (e.g., (0,0) location) of its respective X-Y coordinate.

The effective coercive field of each of the grains of the FE film250may be determined by the grain size and/or each grain's polarization direction. Here the effective coercive field of a grain refers to a value of the electric field along the thickness T direction that causes the polarization direction of the grain to switch. As illustrated inFIG.2B, the Q-V curves of the grains have similar shapes, but the effective coercive fields (e.g., Ec1, Ec2, Ec3, Ec4, and Ec5) for different grains are different. Therefore, each grain switches its polarization direction (also referred to as polarization orientation) when the electric field (which may be proportional to the voltage applied) along the thickness T direction crosses its corresponding effective coercive field. For example, looking at the first Q-V curve ofFIG.2B, when the electric field applied increases above Ec1, the first grain switches from a second polarization direction to a first polarization direction; when the electric field applied decrease below, e.g., −Ec1, the first grain switches from the first polarization direction back to the second polarization direction. Note that inFIG.2B, for each grain, the strength (e.g., magnitude) of the remnant polarization along the thickness T direction may be different, due to the different polarization direction of each grain.

FIG.2Cshows the Q-V curve of the FE film250, when the Q-V curves of all the grains are combined together. The shape of the combined Q-V curve has many stairs (e.g., step changes), where the locations of the stairs along the X-axis correspond to the effective coercive fields of the different grains. For example, as the electric field applied to the FE film250gradually increases past the effective coercive fields Ec1, Ec2, Ec3, Ec4, and Ec5, the grains 1, 2, 3, 4, and 5 sequentially switch their polarization directions to their respective first directions (which may be uncorrelated with each other), and as a result, the overall remnant polarization of the FE film250(with contributions from all the grains) shows step increases at the effective coercive fields Ec1, Ec2, Ec3, Ec4, and Ec5. In other words, the combined Q-V curve has multiple (e.g., >2) polarization switching points along the X-axis, and therefore, the polarization strength (e.g., magnitude) has multiple values which are beneficial for use as analog NVM synapse. In the example ofFIG.2C, the FE film250has 10 different states, each corresponding to a polarization direction switching point (or an effective coercive field).

The curves260inFIG.2Cshow an approximation of the combined Q-V responses of all the grains. One skilled in the art will readily appreciate that as the number of grains in the FE film250increases, the number of polarization direction switching points (e.g., number of different effective coercive fields) increases, and the curve260more closely approximates the combined Q-V curves. In other words, by having larger numbers of grains with random polarization directions, the FE film250may have a smooth, continuous Q-V response that is beneficial for use as non-volatile memory synapse.

FIG.3illustrates a cross-sectional view of a ferroelectric field-effect transistor (FeFET)200, in an embodiment. The FeFET200includes a substrate231, which may be a semiconductor substrate, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used.

Source region207and drain region205(may be collectively referred to as the source/drain regions) are formed in the substrate231on opposing sides of a gate structure, which gate structure includes a gate dielectric layer211, an internal metal layer213, the ferroelectric film250, and a gate electrode217formed successively over the substrate231. The FeFET200may be referred to as an MFMIS FET, wherein MFMIS represents the materials of the different layers of the FeFET200. For example, the first M stands for the metal material of the gate electrode217, F stands for the ferroelectric material of the ferroelectric film250, the second M stands for the metal material of the internal metal layer213, I stands for the dielectric material of the gate dielectric layer211, and S stands for the substrate material of the substrate231.

The source region207and the drain region205may be formed by doping areas of the substrate231with an N-type dopant, such as arsenic or phosphorus, for an N-type device, or by doping areas of the substrate231with a P-type dopant, such as boron, for a P-type device. The gate dielectric layer211may be formed of a suitable dielectric material, such as silicon oxide, silicon nitride (SiN), a high-K dielectric material with a dielectric constant (K value) larger than 3.9 (e.g., between about 3.9 and about 25), or the like, and may be formed by a suitable formation method such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), combinations thereof, or the like.

The internal metal layer213is formed of a metal or a metal-containing material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), or copper (Cu), using a suitable formation method such as CVD, PVD, or ALD. In some embodiments, the ferroelectric film250is a doped hafnium oxide (HfO2) film, such as HfO2film doped with silicon (Si), aluminum (Al), zirconium (Zr), gadolinium (Gd), or yttrium (Yt). For example, the doped hafnium oxide may be a hafnium oxide doped with zirconium, where the atomic percentage ratio between Hf, Zr, and O is about 1:1:4. As another example, the doped hafnium oxide may be a hafnium oxide doped with aluminum, where the atomic percentage (at %) of aluminum is about 10 at % or less, such as about 10%.

In some embodiments, the FE film250is formed using atomic layer deposition (ALD) at a temperature of about 250° C. In some embodiments, a doped HfO2film is formed using ALD, with the dopant (e.g., Si, Al, Zr, Gd, or Yt) formed in some cycles of the ALD process over a monolayer of oxygen (O) formed in a previous ALD cycle. In an ALD process for forming an un-doped HfO2film, monolayers of Hf and monolayers of O are formed alternately in alternating deposition cycles (also referred to cycles) of the ALD process. To form the doped HfO2film, some deposition cycles for forming Hf monolayers in the un-doped ALD process are replaced with deposition cycles for forming the dopant (e.g., of Si, Al, Zr, Gd, or Yt) monolayers. For example, some monolayers of Hf are replaced by monolayers of a dopant Zr, and therefore, the doped HfO2film (e.g., doped by Zr) may comprise repetitions of the following monolayer structure: a first O monolayer, an Hf monolayer over (e.g., in direct contact with) the first O monolayer, a second O monolayer over (e.g., in direct contact with) the Hf monolayer, and a Zr monolayer over (e.g., in direct contact with) the second O monolayer.

A thickness T (seeFIG.1) of the ferroelectric film250is between about 5 nm and about 20 nm, in some embodiments. If the thickness Tis smaller than about 5 nm, the grains of the doped HfO2film formed tend to have a uniform polarization direction instead of random polarization directions, and therefore, do not provide the multiple-step Q-V response illustrated inFIG.2C. On the other hand, if the thickness T is larger than 20 nm, the FE film250may be too thick for advanced process technologies suitable for AI/ML hardware implementation.

In some embodiments, each grain of the FE film250comprises doped HfO2. After the FE film250is formed, the gate electrode217is formed over the FE film250, and a thermal anneal process is performed at a temperature between about 500° C. and about 600° C. The gate electrode217may comprise a metal or a metal-containing material, such as TiN, TaN, W, Cu, or the like, and may be formed using a suitable formation method, such as CVD, PVD, or ALD. The gate electrode217is formed of a same material as the internal metal layer213, in some embodiments. In other embodiments, the gate electrode217is formed of a different material than the internal metal layer213. In some embodiments, the as-deposited FE film250after the ALD process is amorphous, and after the anneal process discussed above, the FE film250is crystalized to form a poly-crystal FE film250. Without being limited to a particular theory, it is believed that the dopant in the doped HfO2film helps to form the poly-crystal FE film250with random polarization directions.

FIG.3further illustrates a programming voltage221(which may comprise a plurality of voltage pulses with gradually increasing or gradually decreasing voltages) for the FeFET200. During programming, the source region207and the drain region205are coupled to electrical ground (e.g., grounded), and the programming voltage221applies a voltage (e.g., a sequence of voltage pulses) to the gate electrode217, in some embodiments. Recall that inFIG.2C, the Q-V curve has multiple polarization direction switching points corresponding to different effective coercive fields (which are proportional to the programming voltage221applied). Therefore, depending on the voltage Vg of the programming voltage221, the direction and strength of the remnant polarization of the FE film250may have different values. Consider an example where the FeFET200is an NMOS FET, and the programming voltage221is a sequence of voltage pulses with a gradually increasing positive voltage. As the voltage Vg increases, the strength of the remnant polarization of the FE film250increases, which attracts more electrons to the channel region of the FeFET200, thereby causing a drop in the threshold voltage Vt of the FeFET200. By changing the programming voltage221, the threshold voltage Vt of the FeFET200is set (e.g., programmed) to different values, in some embodiments. Due to the plurality of effective coercive fields (see, e.g.,FIG.2C) of the FE film250, the FeFET200has a plurality of (e.g., more than two) different programmable threshold voltage values.

After the threshold voltage Vt of the FeFET200is set (e.g., programmed), when a voltage V (e.g., a read voltage in a memory device) is applied to the gate electrode217of the FeFET200, the current flowing between the source region207and the drain region205(referred to as source drain current) of the FeFET200is proportional to V-Vt, in some embodiments. In other words, the conductance (e.g., inverse of electrical resistance) between the source region207and the drain region205of the FeFET200may be adjusted by adjusting the threshold voltage Vt, which is programmed by the programming voltage221. Therefore, the FeFET200may be functionally considered as a three-terminal adjustable resistor, where electrical current flows between the source region207and the drain region205, and the gate electrode217is used to adjust the electrical resistance (or the conductance) of the resistor. For ease of discussion herein, the conductance between the source region207and the drain region205of the FeFET200may also be referred to as the effective conductance of the FeFET200, or simply the conductance of the FeFET200. Due to the plurality of effective coercive fields (see, e.g.,FIG.2C) of the FE film250, the FeFET200has a plurality of (e.g., more than two) different programmable effective conductance values.

FIG.4illustrates the change of the threshold voltage Vt (labeled ΔVt) versus the programming voltage Vg for the FeFET200ofFIG.3, in an embodiment.FIG.4illustrates an example where the FeFET200is an N-type device. As illustrated in theFIG.4, as Vg increases gradually from zero and passes a minimum value VA(which may correspond to a lowest positive effective coercive field similar to the first effective coercive field Ec1inFIG.2C), the threshold voltage Vt starts to decrease from an initial value over a range of Vg values (e.g., a range between VAand VB). When Vg reaches the voltage VB(which may correspond to a highest positive effective coercive field of the FE film250), the threshold voltage Vt reaches a minimum value and stops decreasing. Similarly, by applying a decreasing negative programming voltage Vg, the threshold voltage Vt increases over a range of Vg values (e.g., the range between −VAand −VB). The gradual, continuous, and substantially linear change in the threshold voltage Vt illustrated inFIG.4is especially beneficial for forming analog NVM synapse. In contrast, a uniform FE film may only have one positive coercive field Ec1, and therefore, the change of threshold voltage Vt versus Vg curve may exhibit one abrupt step change for positive Vg values. For this reason, non-volatile memory devices formed using the FeFET200may be referred to as analog non-volatile memory devices, due to the analog-like Q-V response (seeFIG.2C) and/or ΔVt versus Vg relation.

FIG.5illustrates a schematic view of a memory array400built using the FeFET200, in an embodiment. The memory array400ofFIG.5is a 4×4 array formed with sixteen 1T1FeFET analog non-volatile memory cells, where T stands for transistor, and FeFET stands for ferroelectric field-effect transistor. The size (e.g., 4×4) of the memory array400shown inFIG.5is a non-limiting example. One skilled in the art will readily appreciate that the memory array may have any other dimensions.

InFIG.5, each FeFET200is connected to a respective transistor411(also referred to as a switching transistor, or a switching FET) to form a memory cell. For example, the dashed circle inFIG.5illustrates a memory cell420. For each memory cell420, a source of the switching transistor411is connected to a gate of the FeFET200.FIG.5further illustrates bit lines BL1, BL2, BL3, and BL4, and word lines WL1, WL2, WL3, and WL4. Each of the bit lines is connected to the drains of respective FeFETs200. For example, the bit line BL1is connected to the drains of four FeFETs200disposed in the top row of the memory array inFIG.5. Each of the word lines is connected to the gates of respective switching transistors411. For example, the word line WL1is connected to the gates of four switching transistors411disposed in the top row of the memory array inFIG.5. In addition,FIG.5illustrates programming lines PRL1, PRL2, PRL3, and PRL4, and output lines SL1, SL2, SL3, and SL4. Each of the programming lines is connected to the drains of respective switching transistors411, and each of the output lines is connected to the sources of respective FeFET200. For example, the programming line PRL1is connected to the drains of four switching transistor411disposed in a same column (e.g., the leftmost column) of the memory array ofFIG.5, and the output line SL1is connected to the sources of the four FeFET200disposed in a same column (e.g., the leftmost column) of the memory array ofFIG.5.

As discussed above, the conductance of the FeFET200in each memory cell can be programmed to a different value through the programming voltage. The conductance of the FeFET200in each memory cell ofFIG.5may serve as an element (e.g., a coefficient) in a 4×4 matrix that is used to implement the Multiply-Accumulate (MAC) operations in analog computing. An example is discussed below to demonstrate how the FeFET200is used as analog NMV synapse in analog computing.

Consider an example where the conductance of each FeFET200is programmed to a different value Gi,j, wherein i and j denotes the row number and the column number in the memory array at which the FeFET200is located. For example, the four FeFETs200at the first row of the memory array400have conductances G1,1, G1,2, G1,3, and G1,4. A weight update operation may be performed to program the conductances of the FeFETs200. In the weight update operation, to program the conductance Gi,jof the FeFET200located on the i-th row and j-th column, a high voltage is applied at the word lines WLi to turn on the switching transistors411in the i-th row, and a programming voltage (e.g., a sequence of gradually increasing or gradually decreasing voltage pulses) is applied at the programming line PRLj to set (e.g., program) the conductance Gi,jof the FeFET200on the i-th row and j-th column. Note that the example here assumes that the switching transistor411is an N-type device, thus a high voltage (e.g., +3V, +5V) is used to turn on the switching transistor411.

After the conductances of all the FeFETs200in the memory array400are programmed, the analog computing is performed by an inference operation. In the inference operation, a high voltage is applied to all of the word lines WL1, WL2, WL3, and WL4to turn on all of the switching transistors411. Next, a read voltage, which may be a fixed voltage (e.g., +0.2V, +0.3V) that is slightly higher than, e.g., the largest threshold voltage of the FeFETs200, is applied to all the program lines PRL1, PRL2, PRL3, and PRL4, such that the read voltage is applied to the gates of all the FeFET200. Input voltages VI,1, VI,2, VI,3, and VI,4are applied to the bit lines BL1, BL2, BL3, and BL4, respectively. The current measured at the lower ends (see the ends with labels Io,1, Io,2, Io,3, and Io,4) of the output lines SL1, SL2, SL3, and SL4is given by

Io,j=∑k=14Gj,k⁢VI,k(1)
where j=1, 2, 3, or 4. Note that the output currents measured at the lower ends of the each output line (e.g., SL1, SL2, SL3, or SL4) automatically achieves the multiply-and-accumulate operations in Equation (1). In particular, by functioning as a programmable resistor, each FeFET200converts a respective input voltage (e.g., VI,1, VI,2, VI,3, or VI,4) into a respective output current, thereby achieving the multiply operations in Equation (1) without using digital multipliers. In addition, the source drain currents of all the FeFET200disposed on a same column of the memory array are naturally added together, as dictated by the Kirchhoff's Current Law, thereby achieving the accumulate operations without using digital adders. Therefore, the MAC operations in Equation (1) are achieved by using the analog properties of the devices (e.g., as dictated by physics laws) in the memory array.

Additional embodiments of analog NVM synapse formed using the FE film250are disclosed hereinafter. In particular, ferroelectric tunnel junctions (FTJs) built using the FE film250and non-volatile memory devices built using such FTJs are disclosed.

FTJ is a two-terminal device and may be formed by sandwiching a ferroelectric film between two electrically conductive layers (e.g., a top electrode and a bottom electrode), where the two electrically conductive layers function as the two terminals of the FTJ device. The electrical polarization direction of the ferroelectric film can be switched by an electric field applied to the ferroelectric film. The electrical resistance of the FTJ, also referred to as the tunneling electroresistance (TER) of the FTJ, is determined by the orientation of the electric polarization of the ferroelectric film. For example, for a conventional FTJ having a ferroelectric film with a uniform polarization direction, by changing the electrostatic potential (e.g., voltage) profile across the ferroelectric film, the FTJ may change from a high-resistance state (HRS) to a low-resistance state (LRS), or vice versa. Since the ferroelectric film250of the present disclosure has many different polarization direction switching points (see, e.g.,FIG.2C), the TER of the FTJ formed using the ferroelectric film250in the present disclosure has many different values that are programmable by applying different programming voltages. For example, the TER may be set (e.g., programmed) by a programming voltage with a gradually increasing or gradually decreasing voltage.

FIGS.6A and6Billustrate cross-sectional views of a device100comprising a ferroelectric tunnel junction (FTJ)102, in an embodiment.FIG.6Billustrates the cross-sectional view of the device100along cross-section B-B inFIG.6A, andFIG.6Aillustrates the cross-sectional view of the device100along cross-section A-A inFIG.6B. Note that for clarity, not all features of the device100are illustrated inFIGS.6A and6B, andFIGS.6A and6Bmay illustrate only a portion of the device formed. In addition, to illustrate the relationship (e.g., locations, sizes) between different features of the device100, some features (e.g.,105,103) that are not visible along the cross-section B-B are also illustrated inFIG.6Bin dashed lines.

Referring toFIG.6A, the device100includes a substrate131, a dielectric layer135over the substrate131, an FTJ102over the dielectric layer135, dielectric layers117and119over the dielectric layer135, vias111/113, and conductive lines115A/115B. The FTJ102includes a bottom electrode101(may also be referred to as a bottom metal layer), a dielectric layer103, an internal metal layer105(also referred to as an internal gate), the ferroelectric film250(also referred to as a ferroelectric layer), and a top electrode109(also referred to as a top metal layer).

FIG.6Afurther illustrates a conductive feature133formed in or on the substrate131. In the illustrated embodiment, the conductive feature133is a transistor that is electrically coupled to the bottom electrode101of the FTJ102by a via137. In the example ofFIG.6A, the via137extends through the dielectric layer135and electrically couples the bottom electrode101to a drain of the transistor133. The device100may therefore be a memory cell of a memory device (e.g., a non-volatile memory device) with a 1T1FTJ structure, where T stands for transistor, and FTJ stands for ferroelectric tunnel junction. Details of the device100and method of forming the device100are discussed hereinafter.

The substrate131may be a semiconductor substrate, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. Devices, such as transistors133, diodes, capacitors, resistors, etc., may be formed in and/or on the substrate131and may be interconnected by interconnect structures formed by, for example, metallization patterns in one or more dielectric layers over the substrate131.FIG.6Amay only illustrate a portion of the device that includes the FTJ102and the transistor133.

The dielectric layer135, which may be an interlayer dielectric (ILD) layer, is formed over the substrate131. The dielectric layer135may be a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; or a combination thereof, and may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. Next, the via137is formed in the dielectric layer135to electrically couple to, e.g., a drain of the transistor133. The via137may be formed by forming an opening in the dielectric layer135and filling the opening with an electrically conductive material (e.g., copper, tungsten, or the like).

Next, the bottom electrode101is formed over the dielectric layer135. The bottom electrode101is formed of an electrically conductive material. In the example ofFIG.6A, the bottom electrode101is formed of a metal or a metal-containing material, such as copper (Cu), tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), or the like. A thickness of the bottom electrode101may be between about 5 nm and about 30 nm, as an example. A suitable formation method, such as atomic layer deposition (ALD), may be used to form the bottom electrode101.

Next, the dielectric layer103and the internal metal layer105are formed over the bottom electrode101successively. The dielectric layer103is a silicon oxide layer, in some embodiments. In some embodiments, the dielectric layer103is formed of a high-K dielectric material having a dielectric constant (K) value larger than 3.9, such as between about 3.9 and about 25. Examples of the high-K dielectric material include hafnium oxide (e.g., HfO2), zirconium oxide (e.g., ZrO2), silicon nitride (e.g., SiN), and lanthanum oxide (e.g., La2O3). A thickness of the dielectric layer103is less than about 2 nm, such as about 1 nm, in some embodiments. A suitable deposition method, such as ALD, may be used to form the dielectric layer103.

The internal metal layer105is formed of an electrically conductive material (e.g., Cu, W, TiN, TaN), and may be formed of a same material or a different material as the bottom electrode101. A suitable deposition method, such as ALD, may be used to form the internal metal layer105. A thickness of the internal metal layer105is between about 5 nm and about 30 nm, in some embodiments.

Next, the dielectric layer103and the internal metal layer105are patterned using, e.g., a same patterning mask. In other words, a single patterning process is used to pattern both the dielectric layer103and the internal metal layer105, in some embodiments. An anisotropic etching process, such as a plasma etching process, may be used to pattern the dielectric layer103and the internal metal layer105. The patterning process removes portions of the dielectric layer103and portions of the internal metal layer105, and exposes portions of the bottom electrode101. After the patterning process, remaining portions of the dielectric layer103and remaining portions of the internal metal layer105have a same size (e.g., same length, width, and surface area), as illustrated inFIGS.6A and6B. For example, as shown inFIG.6B, the internal metal layer105and the dielectric layer103have a same surface area in a top view, thus their boundaries (e.g., sidewalls) overlap completely.

Referring back toFIG.6A, after the dielectric layer103and the internal metal layer105are patterned, the ferroelectric layer250and the top electrode109are formed successively over the internal metal layer105. The material and the formation method of the ferroelectric layer250of the device100is the same as or similar to the ferroelectric film250of the FeFET200discussed above, thus details may not be repeated. For example, the ferroelectric layer250is formed of a suitable ferroelectric material, such as doped hafnium oxide. The doped hafnium oxide may be a hafnium oxide doped by Si, Al, Zr, Gd, or Yt. As an example, the doped hafnium oxide may be a hafnium oxide doped with zirconium, where the atomic percentage ratio between Hf, Zr, and O is about 1:1:4. As another example, the doped hafnium oxide may be a hafnium oxide doped with aluminum, where the atomic percentage (at %) of aluminum is less than about 10 at %, such as about 10 at %. The ferroelectric layer250may have a thickness between about 5 nm to about 20 nm.

The top electrode109is formed of an electrically conductive material, such as Cu, W, TiN, TaN, or the like, and may be formed of a same material as the bottom electrode101. In some embodiments, the top electrode109is formed of a different material than the bottom electrode101. A thickness of the top electrode109is between about 10 nm and about 30 nm, in some embodiments. A suitable deposition method, such as ALD, may be used to form the top electrode109.

After the top electrode109and the ferroelectric layer250are formed, the top electrode109and the ferroelectric layer250are patterned using, e.g., a same patterning mask. In other words, a single patterning process is used to pattern both the top electrode109and the ferroelectric layer250, in some embodiments. An anisotropic etching process, such as a plasma etching process, may be used to pattern the top electrode109and the ferroelectric layer250. The patterning process removes portions of the top electrode109and portions of the ferroelectric layer250, and exposes portions of the internal metal layer105. After the patterning processing, remaining portions of the top electrode109and remaining portions of the ferroelectric layer250have a same size (e.g., same length, width, and surface area), as illustrated inFIGS.6A and6B. For example, as shown inFIG.6B, the top electrode109and the ferroelectric layer250have a same surface area in the top view, thus their boundaries (e.g., sidewalls) overlap completely.

As illustrated inFIG.6B, an area A1of the top electrode109is smaller than an area A2of the internal metal layer105. In some embodiments, a ratio between the area A1of the top electrode109and the area A2of the internal metal layer105is between about 1/100 and about ⅕, such as about 1/30. In the discussion herein, the top electrode109, the ferroelectric layer250and the internal metal layer105may be referred to as a first capacitor, where the top electrode109and the internal metal layer105are considered as the plates (e.g., top plate and bottom plate, respectively) of the first capacitor, and the ferroelectric layer250is considered as the dielectric layer between the plates of the first capacitor. The area (e.g., plate area) of the first capacitor is determined by the area of the top electrode109, and therefore, is A1. The top electrode109, the ferroelectric layer250, and the internal metal layer105may be collectively referred to as an MFM structure or an MFM capacitor, where M stands for the metal material (e.g., of layer109or layer105), and F stands for the ferroelectric material (e.g., of layer250).

Similarly, the internal metal layer105, the dielectric layer103, and the bottom electrode101may be referred to as a second capacitor, and the area (e.g., plate area) of the second capacitor is determined by the area of the internal metal layer105, and therefore, is A2. The internal metal layer105, the dielectric layer103, and the bottom electrode101may be collectively referred to as an MIM structure or an MIM capacitor, where M stands for metal material (e.g., of layer105or layer101), and I stands for dielectric material (e.g., of layer103). The FTJ102ofFIG.6A, therefore, may be referred to as an MFMIM FTJ or an MFMIM structure. The FTJ102is a two-terminal device, with the bottom electrode101and the top electrode109functioning as the two terminals of the FTJ102.

Still referring toFIG.6A, next, a dielectric layer117, such as SiO2, SiN, a low-K dielectric material, or the like, is formed over the bottom electrode101and over the FTJ102. A suitable deposition method, such as CVD, PVD, or the like, may be used to form the dielectric layer117. A via111is formed to extend from an upper surface of the dielectric layer117into the dielectric layer117, and to electrically couple to the top electrode109. Another via113is formed to extend from the upper surface of the dielectric layer117into the dielectric layer117, and to electrically couple to the bottom electrode101.

Next, a dielectric layer119is formed over the dielectric layer117, and conductive lines115A and115B (e.g., copper lines) are formed in the dielectric layer119. The dielectric layer119may comprise a same or similar material as the dielectric layer117, and may be formed using a same or similar formation method, thus details are not repeated. The conductive lines115A and115B may be formed using any suitable method, such as a damascene process. In some embodiments, the conductive lines115A/115B and the vias111/113are formed together in a dual-damascene process, in which case the dielectric layers117and119may be formed together as one layer. In the example ofFIG.6A, the conductive lines115A and115B are electrically coupled to the vias11and113, respectively. The conductive lines115A and115B provide electrical connection to the two terminals (e.g., top electrode109and bottom electrode101) of the FTJ102. In some embodiments, since the bottom electrode101of the FTJ102is electrically coupled to, e.g., the drain of the transistor133through the via137, and therefore, the via113and the conductive line115B may be omitted.

Additional processing, such as formation of additional dielectric layers and conductive features (e.g., vias, conductive lines) may be performed to finish fabrication of the device100, as one skilled in the art readily appreciates, thus details are not discussed herein. In addition, for clarity, not all features of the device100are illustrated inFIGS.6A and6B. For example, electrical connections to the gate and the source of the transistor133, as well as other components (e.g., other transistors, resistors, diodes, capacitors, inductors, or the like) of the device100and their electrical connections, are not illustrated inFIGS.6A and6B.

The rectangular shapes of the various layers (e.g.,109,250,105,103) of the FTJ102illustrated inFIG.6Bare non-limiting examples. Other shapes, such as square, circle, polygon, or the like, are also possible and are full intended to be included within the scope of the present disclosure.

The disclosed structure of the FTJ102(and other FTJs disclosed hereinafter) has many advantages. To appreciate the advantages, consider a reference FTJ which is similar to the FTJ102inFIG.6A, but without the internal metal layer105. In addition, the reference FTJ has a same size (e.g., same surface area in top view) for the top electrode109, the ferroelectric layers250, and the dielectric layer103. Since a typical electric displacement field (D field) for switching the polarization direction of a ferroelectric layer is about 30 μC/cm2, and since the structure of the reference FTJ results in a similar D field in the dielectric layer (e.g.,103), such a D field may cause breakdown of the dielectric layer, which typically has a breakdown D field of about 1 μC/cm2. The breakdown of the dielectric layer in the FTJ may contribute to the poor endurance of certain FTJs.

In the disclosed embodiments, by having the internal metal layer105, and by designing the area A1of the top electrode109to be smaller than the area A2of the internal metal layer105, the breakdown of the dielectric layer103is alleviated or avoided (see discussion below), thus the endurance of the FTJ is improved.

With the internal metal layer105inserted between the top electrode109and the bottom electrode101, the FTJ102may be considered as two capacitors coupled in series, where the two capacitors are: a first capacitor (e.g., an MFM capacitor) comprising the top electrode109, the ferroelectric layer250, and the internal metal layer105, and a second capacitor (e.g., an MIM capacitor) comprising the internal metal layer105, the dielectric layer103, and the bottom electrode101. The smaller area A1of the top electrode109may result in the capacitance of the first capacitor being smaller than the capacitance of the second capacitor. Since the first capacitor and the second capacitor are coupled in series, one skilled in the art will readily appreciate that for a given voltage V applied between the top electrode109and the bottom electrode101, the first capacitor (with smaller capacitance) experiences (e.g., shoulders) a larger voltage drop than the second capacitor. In other words, the first capacitor shoulders a larger percentage of the voltage V than the second capacitor, and as a result, the voltage drop across the second capacitor (e.g., between the internal metal layer105and the bottom electrode101) is reduced. The reduced voltage drop in the second capacitor results in a reduced D field in the dielectric layer103, which in turn reduces or prevents the breakdown of the dielectric layer103.

In addition, since the ferroelectric layer250has pre-determined programming voltages (e.g., voltages to set or change the TER of the FTJ102), and since the first capacitor shoulders a larger percentage of the voltage V (due to the smaller capacitance), a smaller voltage V applied across the FTJ102may be sufficient to provide the pre-determined programming voltages for the ferroelectric layer250, e.g., compared with a reference design where the first capacitor and the second capacitor each share 50% of the voltage V. In other words, the disclosed embodiments allow for lower programming voltages V for the FTJ102. The lower programming voltage V may advantageously reduce the power consumption of the FTJ102and/or the memory device formed using the FTJ102.

The use of high-K dielectric material as the dielectric layer103further improves the performance of the FTJ102. This is because for the same D field, the electrical field (E-field) in the dielectric layer103is inversely proportional to the K value of the dielectric layer103. Therefore, a higher K value (due to the use of high-K dielectric material) results in a reduced E-field in the dielectric layer103, which helps to prevent or reduce the breakdown of the dielectric layer103. Note that a higher K value may result in a lower breakdown E-field for the dielectric layer103. However, as long as the reduction in the E-field due to the use of high-K dielectric material is larger than the reduction in the breakdown E-field, using high-K dielectric material for the dielectric layer103provides performance gain (e.g., reduces breakdown of the dielectric layer103).

FIG.7illustrates a cross-sectional view of a device100A (e.g., a memory device) comprising an FTJ102A, in an embodiment. For simplicity, not all features of the device100A are illustrated. The FTJ102A inFIG.7is similar to the FTJ102inFIG.6A, but the bottom electrode of the FTJ102A is a heavily doped substrate121instead of the metal or metal-containing material inFIG.6A. In some embodiments, the heavily doped substrate121is a semiconductor substrate (e.g., silicon, silicon-germanium, germanium, or the like) doped by a dopant (e.g., boron, phosphorous, or arsenic). A concentration of the dopant may be between about 1019cm−3and about 1021cm−3, as an example. Due to the dopant in the heavily doped substrate121, the heavily doped substrate121is electrically conductive, in the illustrated embodiment. For example, an electrical resistivity of the heavily doped substrate121is between 0.1 mΩ-cm and about 10 mΩ-cm. A thickness of the heavily doped substrate121is between about 100 nm and about 100 m. In some embodiments, the heavily doped substrate121is a doped semiconductor layer over another substrate, or a doped top portion of a substrate.

FIG.7further illustrates an isolation region127, such as a shallow trench isolation (STI) region, which separates the bottom electrode121from an active region122of the substrate. In addition,FIG.7illustrates a transistor133formed in the active region122. The vias113and the conductive line115B electrically couple the bottom electrode121of the FTJ102A with the transistor133. For example, the via113over the transistor133is electrically coupled to a drain of the transistor133. Therefore,FIG.7illustrates portions of memory device (e.g., a memory cell) with a 1T1FTJ structure. The electrical connection between the transistor133and the FTJ102A shown inFIG.7is merely an example, other electrical connections are also possible and are fully intended to be included within the scope of the present disclosure.

InFIG.7, the top electrode109, the ferroelectric layer250and the internal metal layer105form an MFM structure. The internal metal layer105, the dielectric layer103, and the heavily doped substrate121form an MIS structure, where M stands for metal, I stands for dielectric material, and S stands for substrate. The FTJ102A may also be referred to as an MFMIS structure or an MFMIS FTJ.

Similar to the FTJ102, the area A1of the top electrode109of the FTJ102A is smaller than the area A2of the internal metal layer105of the FTJ102A. In some embodiments, a ratio between the area A1and the area A2is between about 1/100 and about ⅕, such as about 1/30. Dimensions of other layers of the FTJ102A are the same as or similar to those of the FTJ102. For example, a thickness of the dielectric layer103inFIG.7is less than about 2 nm, such as 1 nm. A thickness of the ferroelectric layer250inFIG.7is between about 5 nm and about 20 nm.

FIG.8illustrates a cross-sectional view of a device100B (e.g., a memory device) with an FTJ102B, in an embodiment. The FTJ102B is similar to the FTJ102, but the second capacitor has a three-dimensional (3D) MIM structure. In particular, the bottom electrode101is formed as a metal fin protruding above the dielectric layer135. In some embodiment, the bottom electrode101is formed by depositing a layer of metal or metal-containing material (e.g., Cu, W, TiN, TaN, or the like) over the dielectric layer135, then patterning the deposited layer to form the metal fin, using, e.g., an anisotropic etching process. In the example ofFIG.8, the metal fin structure of the bottom electrode101has a width W between about 5 nm and about 15 nm, and a height H between about 10 nm and about 50 nm.

Once the metal fin structure is formed, the dielectric layer103is formed conformally over sidewalls and over an upper surface of the bottom electrode101(e.g., a metal fin), using a suitable deposition method such as ALD. A thickness of the dielectric layer103(e.g., SiO2) is less than about 2 nm, such as about 1 nm. Next, the internal metal layer105is formed conformally over the dielectric layer103and extends along sidewalls and along an upper surface of the bottom electrode101.

Note that due to the structure of the 3D MIM structure, the area A2of the internal metal layer105(or the area of the dielectric layer103) includes areas along the sidewalls and along the upper surface of the bottom electrode101. As a result, compared with the planar MIM structure of the second capacitor in the FTJ102ofFIG.6A, the FTJ102B ofFIG.8can achieve the same area A2for the internal metal layer105with a smaller footprint over the substrate131. This allows a higher integration density for the device100B.

After the internal metal layer105is formed, the dielectric layer117is formed over the dielectric layer135and around the second capacitor (e.g.,101,103, and105). A planarization process, such as chemical mechanical planarization (CMP), may be performed to achieve a planar upper surface for the dielectric layer117and to expose the upper surface of the internal metal layer105.

Next, the ferroelectric layer250and the top electrode109are formed successively over the internal metal layer105, and a patterning process is performed to remove portions of the ferroelectric layer250and portions of the top electrode109, similar to the processing for the device100ofFIG.6A. Next, a dielectric layer118, which may be the same material as the dielectric layer117, is formed over the dielectric layer117. Depending on the materials of the dielectric layer118and/or the formation method, there may or may not be an interface117F between the dielectric layers118and117. Next, vias111and conductive lines115are formed to electrically couple to the top electrode109of the FTJ102B. Note that in the example ofFIG.8, the bottom electrode101of the FTJ102B is electrically coupled to, e.g., a drain of the transistor133by the via137. The electrical connection between the transistor133and the FTJ102B shown inFIG.8is merely an example, other electrical connections are also possible and are fully intended to be included within the scope of the present disclosure.

In the example ofFIG.8, the first capacitor of the FTJ102B has a planar MFM structure, which includes the top electrode109, the ferroelectric layer250, and the horizontal portion of the internal metal layer105(e.g., the portion along the upper surface of the dielectric layer103). The second capacitor of the FJT102B has a three-dimensional MIM structure, which includes the internal metal layer105, the dielectric layer103, and the bottom electrode101(e.g., a metal fin). The FTJ102B may be referred to as having a 3D MFMIM structure or as a 3D MFMIM FTJ.

Similar to the FTJ102, the area A1of the top electrode109of the FTJ102B is smaller than the area A2of the internal metal layer105of the FTJ102B. In some embodiments, a ratio between the area A1of the top electrode109and the area A2of the internal metal layer105is between about 1/100 and about ⅕, such as about 1/30. Dimensions of other layers of the FTJ102B are the same as or similar to those of the FTJ102. For example, a thickness of the dielectric layer103inFIG.8is less than about 2 nm, such as 1 nm. A thickness of the ferroelectric layer250inFIG.8is between about 5 nm and about 20 nm.

FIG.9illustrates a cross-sectional view of a device100C (e.g., a memory device) with an FTJ102C, in an embodiment. The FTJ102C is similar to the FTJ102B, but the bottom electrode121of the FTJ102C is a heavily doped substrate instead of a metal or a metal-containing material, which bottom electrode121has a fin structure protruding above a substrate125. In the illustrated embodiment, the bottom electrode121is connected to the substrate125, which is also a heavily doped substrate. In other words, the bottom electrode121and the substrate125inFIG.9are formed of a same heavily doped semiconductor material. In some embodiments, the fin structure of the bottom electrode121is formed by patterning the heavily doped semiconductor material using, e.g., an anisotropic etching process. The composition of the heavily doped semiconductor material (e.g.,121and125) is the same as or similar to that of the heavily doped substrate121ofFIG.7, thus details are not repeated here. A width W of the fin structure of the bottom electrode121is between about 5 nm and about 15 nm, and a height H of the fin structure of the bottom electrode121is between about 10 nm and about 50 nm, in some embodiments.

Referring toFIG.9, after the bottom electrode121is formed, a dielectric layer123is formed over the substrate125and around the bottom electrode121. The material and the formation method of the dielectric layer123may be the same as or similar to that of the dielectric layer117, thus details are not repeated. In some embodiments, the dielectric layer123is omitted. Subsequent processing to form other layers of the FTJ102C, the vias111/113, the conductive lines115A/115B, and the dielectric layers117/118/119are the same as or similar to those described above, thus details are not repeated here. The electrical connection between the transistor133and the FTJ102C shown inFIG.9is merely an example, other electrical connections are also possible and are fully intended to be included within the scope of the present disclosure.

Note that the second capacitor of the FTJ102C inFIG.9, which includes the bottom electrode121, the dielectric layer103, and the internal metal layer105, has a 3D MIS structure. The first capacitor of the FTJ102C, which includes (the horizontal portion of) the internal metal layer105, the ferroelectric layer250, and the top electrode109, has a planar MFM structure. The FTJ102C may be referred to as having a 3D MFMIS structure or as a 3D MFMIS FTJ. Similar to the discussion above for the FTJ102B, the 3D MIS structure of the second capacitor of the FTJ102C allows for a large area A2(e.g., areas along sidewalls and a top surface of the bottom electrode121) for the internal metal layer105with a small footprint over the substrate125, which allows for higher integration density for the memory array400.

Similar to the FTJ102B, the area A1of the top electrode109of the FTJ102C is smaller than the area A2of the internal metal layer105of the FTJ102C. In some embodiments, a ratio between the area A1of the top electrode109and the area A2of the internal metal layer105is between about 1/100 and about ⅕, such as about 1/30. Dimensions of other layers of the FTJ102C are the same as or similar to those of the FTJ102. For example, a thickness of the dielectric layer103inFIG.9is less than about 2 nm, such as 1 nm. A thickness of the ferroelectric layer250inFIG.9is between about 5 nm and about 20 nm.

FIG.10illustrates a schematic view of a memory array500formed using the FTJs, in an embodiment. The memory array500ofFIG.10is a 4×4 array formed with sixteen 1T1FTJ analog non-volatile memory cells, where T stands for transistor, and FTJ stands for ferroelectric tunnel junction. The size (e.g., 4×4) of the memory array500shown inFIG.10is a non-limiting example. One skilled in the art will readily appreciate that the memory array may have any other dimensions.

InFIG.10, each memory cell520includes a transistor511(also referred to as a switching transistor, or a switching FET) connected to a respective FTJ. The FTJ can be any suitable FTJ formed using the ferroelectric film250, such that the TER of the FTJ has a plurality (e.g., more than 2) of different values that are programmable by a programming voltage. For example, the FTJ102,102A,102B, or102C may be used to form the memory cell520. For ease of discussion, the FTJ in the memory array500will be referred to FTJ102, with the understanding that any suitable FTJ may be used.

For each memory cell520, a drain of the switching transistor511is connected to a first terminal of the FTJ102.FIG.10further illustrates bit lines BL1, BL2, BL3, and BL4, and word lines WL1, WL2, WL3, and WL4. The second terminal of each FTJ102is connected to a bit line, and the second terminals of FTJs102disposed along a same row inFIG.10are connected to a same bit line. Each of the word lines is connected to the gates of respective switching transistors511disposed along a same row. For example, the word line WL1is connected to the gates of four switching transistors511disposed in the top row of the memory array inFIG.10. In addition,FIG.10illustrates output lines SL1, SL2, SL3, and SL4, and each of the output lines is connected to the sources of respective switching transistors511disposed along a same column. For example, the output line SL1is connected to the sources of the four switching transistors511disposed in the leftmost column of the memory array ofFIG.10.

As discussed above, the conductance (e.g., inverse of the TER) of the FTJ102in each memory cell can be programmed to different values through the programming voltage. The conductance of the FTJ102in each memory cell ofFIG.10may serve as an element (e.g., a coefficient) in a 4×4 matrix that is used to implement the Multiply-Accumulate (MAC) operations in analog computing. An example is discussed below to demonstrate how the FTJ102is used as analog NMV synapse in analog computing.

Consider an example where the conductance of each FTJ102is programmed to a different value Gi,j, wherein i and j denotes the row number and the column number in the memory array at which the FTJ102is located. For example, the FTJs102at the first row of the memory array500have conductances G1,1, G1,2, G1,3, and G1,4. A weight update operation may be performed to program the conductances of the FTJs102. In the weight update operation, to program the conductance Gi,jof the FTJ102located on the i-th row and j-th column, a high voltage is applied at the word lines WLi to turn on the switching transistors511in the i-th row, and a programming voltage (e.g., a sequence of gradually increasing or gradually decreasing voltage pulses) is applied at the output line SLj to set (e.g., program) the conductance Gi,jof the FTJ102on the i-th row and j-th column. Note that the example here assumes that the switching transistor511is an N-type device, thus a high voltage (e.g., +3V, +5V) is used to turn on the switching transistor511.

After the conductances of all the FTJ102in the memory array500are programmed, the analog computing is performed by an inference operation. In the inference operation, a high voltage is applied to all of the word lines WL1, WL2, WL3, and WL4to turn on all of the switching transistors511. Input voltages VI,1, VI,2, VI,3, and VI,4are applied to the bit lines BL1, BL2, BL3, and BL4, respectively. The current measured at the lower ends (see the ends with labels Io,1, Io,2, Io,3, and Io,4) of the output lines SL1, SL2, SL3, and SL4is given by

Io,j=∑k=14Gj,k⁢VI,k(2)
where j=1, 2, 3, or 4. Note that the output currents measured at the lower ends of each output line (e.g., SL1, SL2, SL3, or SL4) automatically achieves the MAC operations in Equation (2). In particular, by functioning as a programmable resistor, each FTJ102converts a respective input voltage (e.g., VI,1, VI,2, VI,3, or VI,4) into a respective output current, thereby achieving the multiply operations in Equation (2) without using digital multipliers. In addition, the output currents of all the FTJs102disposed on a same column of the memory array are naturally added together, as dictated by the Kirchhoff's Current Law, thereby achieving the accumulate operations without using digital adders.

Variations to the disclosed embodiments are possible and are fully intended to be included within the scope of the present disclosure. For example, the internal metal layer213of the FeFET200(seeFIG.3) may be omitted to form an FeFET with a MFIS structure, and the MFIS FeFET may replace the FeFET200, e.g., inFIG.5to form the memory device. As another example, the ferroelectric film250may be formed between, and in physical contact with, a bottom electrode (e.g., a metal or a metal-containing layer) and a top electrode (e.g., a metal or a metal-containing layer) to form an FTJ with an MFM structure. As yet another example, the ferroelectric film250may be formed between, and in physical contact with, a bottom electrode (e.g., a heavily doped substrate) and a top electrode (e.g., a metal or a metal-containing layer) to form an FTJ with an MFS structure. The MFM FTJ or the MFS FTJ may replace the FTJs used inFIG.10to form the memory device. While the disclosed ferroelectric film250achieves multiple polarization switching point (see, e.g.,FIG.2C) by forming grains with random polarizations, the current disclosure also contemplates varying the sizes of the grains of the ferroelectric film250(e.g., grains with random sizes) as an additional tuning nob to achieve the target characteristics for the ferroelectric film250.

Disclosed embodiments achieve advantages. For example, by forming the ferroelectric film250with random polarization directions, the FeFET formed using the ferroelectric film250has a plurality (e.g., three or more) of programmable threshold voltages and may function as a programmable resistor. Similarly, FTJ formed using the ferroelectric film250has a plurality (e.g., three or more) of programmable resistance values (or conductance values). The disclosed FeFET and FTJ may be used to form analog NVM synapse used in analog computing, thereby avoiding the complex and computational intensive operations involved with matrix multiplication. In addition, by having the internal metal layer105in the FTJ, and by designing the area A1of the top electrode109to be smaller than the area A2of the internal metal layer105, only a small percentage of the voltage V applied at the two terminals of the FTJ is applied across the dielectric layer103, which reduces the E-field in the dielectric layer103and reduces or avoids breakdown of the dielectric layer103, thus improving the endurance of the FTJ. In addition, using high-K dielectric material for the dielectric layer103further reduces the E-field of the dielectric layer103, and may further improve the endurance of the device formed. The disclosed 3D MFMIM FTJ or 3D MFMIS FTJ allows for higher integration density than the planar FTJs.

FIG.11illustrates a flow chart of a method of fabricating a device, in accordance with some embodiments. It should be understood that the embodiment method shown inFIG.11is merely an example of many possible embodiment methods. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various steps as illustrated inFIG.11may be added, removed, replaced, rearranged or repeated.

Referring toFIG.11, at step1010, a gate dielectric layer is formed over a substrate. At step1020, an internal metal layer is formed over the gate dielectric layer. At step1030, a ferroelectric layer is formed over the internal metal layer. At step1040, a gate electrode is formed over the ferroelectric layer.

In accordance with an embodiment, a semiconductor device includes: a ferroelectric field-effect transistor (FeFET) including: a substrate; a source region in the substrate; a drain region in the substrate; and a gate structure over the substrate and between the source region and the drain region, wherein the gate structure includes: a gate dielectric layer over the substrate; a ferroelectric film over the gate dielectric layer; and a gate electrode over the ferroelectric film. In an embodiment, the gate structure further includes an internal metal layer between the gate dielectric layer and the ferroelectric film. In an embodiment, the ferroelectric film comprises a plurality of grains that have random polarization directions. In an embodiment, a threshold voltage of the FeFET is adjustable and has more than two different threshold voltage values. In an embodiment, the threshold voltage of the FeFET is configured to be adjusted by applying a sequence of voltage pulses with gradually increasing or gradually decreasing voltages to the gate electrode of the FeFET. In an embodiment, the ferroelectric film comprises doped hafnium oxide. In an embodiment, the doped hafnium oxide is a hafnium oxide doped by silicon, aluminum, zirconium, gadolinium, or yttrium. In an embodiment, a thickness of the ferroelectric film is between about 5 nm and about 20 nm. In an embodiment, a conductance of the FeFET measured between the source region and the drain region of the FeFET is adjustable and has more than two different conductance values, wherein the conductance of the FeFET is configured to be adjusted by applying a sequence of programming voltages with gradually increasing or gradually decreasing voltage values to the gate electrode of the FeFET. In an embodiment, the semiconductor device further includes: a switching transistor, wherein a source region of the switching transistor is coupled to the gate electrode of the FeFET; a word line coupled to a gate of the switching transistor; a programming line coupled to a drain region of the switching transistor; a bit line connected to the drain region of the FeFET; and an output line connected to the source region of the FeFET.

In accordance with an embodiment, a semiconductor device includes a substrate; and a ferroelectric tunnel junction (FTJ) over the substrate, the FTJ comprising: a bottom electrode over the substrate; a dielectric layer over the bottom electrode; an internal metal layer over the dielectric layer; a ferroelectric layer over the internal metal layer; and a top electrode over the ferroelectric layer, wherein a tunneling electroresistance (TER) of the FTJ is adjustable and have more than two different values. In an embodiment, the TER of the FTJ is configured to be adjusted by applying a sequence of voltage pulses with increasing or decreasing voltages between the top electrode and the bottom electrode. In an embodiment, the top electrode and the ferroelectric layer have a same first surface area, wherein the internal metal layer and the dielectric layer have a same second surface area, the second surface area being larger than the first surface area. In an embodiment, the ferroelectric layer is a doped hafnium oxide, and wherein a thickness of the ferroelectric layer is between about 5 nm and about 20 nm. In an embodiment, the ferroelectric layer comprises a plurality of grains that have random polarization directions. In an embodiment, the bottom electrode is a fin protruding above the substrate, wherein the dielectric layer and the internal metal layer extend conformally along sidewalls and a top surface of the fin.

In accordance with an embodiment, a method of forming a device that comprises a ferroelectric field-effect transistor (FeFET) includes: forming a gate dielectric layer over a substrate; forming an internal metal layer over the gate dielectric layer; forming a ferroelectric layer over the internal metal layer; and forming a gate electrode over the ferroelectric layer. In an embodiment, the ferroelectric layer is formed of a doped hafnium oxide with a thickness between about 5 nm and about 20 nm. In an embodiment, the doped hafnium oxide is a hafnium oxide doped by silicon, aluminum, zirconium, gadolinium, or yttrium. In an embodiment, the method further includes, after forming the gate electrode, performing an anneal process at a temperature between about 500° C. and about 600° C.

While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.