Patent ID: 12243777

DETAILED DESCRIPTION

FIG.1illustrates a plan view showing a semiconductor device according to some example embodiments.FIGS.2A and2Billustrate cross-sectional views respectively taken along lines I-I′ and II-II′ ofFIG.1.

Referring toFIGS.1,2A, and2B, a substrate100may include an active region AR. The active region AR may be defined by a second trench TR2formed on an upper portion of the substrate100. The substrate100may be a compound semiconductor substrate or a semiconductor substrate including, e.g., silicon, germanium, silicon-germanium, or the like. For example, the substrate100may be a silicon substrate.

The active region AR may be a logic cell area provided with logic transistors constituting a logic circuit of a semiconductor device. Alternatively, the active region AR may be a memory cell area to store data.

As illustrated inFIG.2A, the active region AR may be provided thereon with a plurality of active patterns AP extending in a second direction D2, and spaced apart from each other in a first direction D1. The active patterns AP may be vertically protruding portions of the substrate100. A first trench TR1may be defined between neighboring active patterns AP.

A device isolation layer ST may fill the first and second trenches TR1and TR2. The device isolation layer ST may include a dielectric material, e.g., a silicon oxide layer. The active patterns AP may have their upper portions that vertically protrude beyond, e.g., above, the device isolation layer ST. Each of the upper portions of the active patterns AP may have a fin shape. The device isolation layer ST may not cover the upper portions of the active patterns AP. The device isolation layer ST may cover lower sidewalls of the active patterns AP.

Source/drain patterns SD may be provided on the upper portions of the active patterns AP. The source/drain patterns SD may be impurity regions having a first conductive type (e.g., p type) or a second conductive type (e.g., n type). As illustrated inFIG.2B, a channel region CH may be interposed between a pair of the source/drain patterns SD within a same active pattern AP.

The source/drain patterns SD may be epitaxial patterns formed by a selective epitaxial growth process. The source/drain patterns SD may have their top surfaces at a higher level than that of top surfaces of the channel regions CH, e.g., along a third direction D3. For example, the source/drain patterns SD may include a semiconductor element (e.g., SiGe) whose lattice constant is greater than that of a semiconductor element of the substrate100. In another example, the source/drain patterns SD may include the same semiconductor element (e.g., Si) as that of the substrate100.

Gate electrodes GE may be provided to extend in the first direction D1, while running across the active patterns AP. The gate electrodes GE may be spaced apart from each other in the second direction D2. The gate electrodes GE may vertically overlap the channel regions CH. The gate electrodes GE may include, for example, one or more of conductive metal nitride (e.g., titanium nitride or tantalum nitride) and metal (e.g., titanium, tantalum, tungsten, copper, or aluminum).

A pair of gate spacers GS may be on opposite sidewalls of each of the gate electrodes GE. The gate spacers GS may extend in the first direction D1along the gate electrodes GE. The gate spacers GS may include one or more of, e.g., SiCN, SiCON, and SiN.

Gate dielectric patterns GI may be interposed between corresponding gate electrodes GE and corresponding channel regions CH. The gate dielectric patterns GI may include a high-k dielectric material. Gate capping patterns GP may be provided on corresponding gate electrodes GE. For example, the gate capping patterns GP may include one or more of SiON, SiCN, SiCON, and SiN.

A first interlayer dielectric layer110may be provided on the substrate100. The first interlayer dielectric layer110may cover the source/drain patterns SD, the gate spacers GS, and the gate capping patterns GP. The first interlayer dielectric layer110may include, e.g., a silicon oxide layer.

An active contact AC may penetrate the first interlayer dielectric layer110and to have electrical connection with the source/drain patterns SD. The active contact AC may be between a pair of the gate electrodes GE.

Second, third, and fourth interlayer dielectric layers120,130, and140may be sequentially stacked on the first interlayer dielectric layer110along the third direction D3. The second, third, and fourth interlayer dielectric layers120,130, and140may include, e.g., a silicon oxide layer.

A via VI may be provided in the second interlayer dielectric layer120, e.g., a thickness of the via VI in the third direction D3may equal that of the second interlayer dielectric layer120. The via VI may penetrate the second interlayer dielectric layer120and have connection with the active contact AC, e.g., the via VI may have a polyhedral island shape extending through an entire depth of the second interlayer dielectric layer120to contact the top of the active contact AC. The via VI may include a barrier pattern BM and a conductive pattern FM. The barrier pattern BM may cover a bottom surface and a sidewall of the conductive pattern FM. The barrier pattern BM may not cover a top surface of the conductive pattern FM. The barrier pattern BM of the via VI may be interposed between the conductive pattern FM and the active contact AC.

The barrier pattern BM may include a metal nitride layer, e.g., one or more of a titanium nitride layer, a tungsten nitride layer, and a tantalum nitride layer. The conductive pattern FM may include a metallic material, e.g., one or more of aluminum, copper, tungsten, molybdenum, and cobalt.

Lower connection lines M1may be provided in the third interlayer dielectric layer130. Each of the lower connection lines M1may have a linear shape extending in the second direction D2. The lower connection lines M1may be arranged spaced apart from each other along the first direction D1. Each of the lower connection lines M1may include a barrier pattern BM and a conductive pattern FM. A detailed description of the barrier pattern BM and the conductive pattern FM may be the same as that of the barrier pattern BM and the conductive pattern FM of the via VI discussed above.

For example, as illustrated inFIGS.1and2A, the lower connection lines M1may include a first lower connection line M11, a second lower connection line M12, and a third lower connection line M13that are adjacent to each other along the first direction D1. Portions of the third interlayer dielectric layer130may separate between the lower connection lines M1. The second lower connection line M12may be provided on and connected to the via VI, e.g., the second lower connection line M12may overlap the, e.g., entire, top of the via VI in the first and second directions D1and D2. The second lower connection line M12may be electrically connected through the via VI to the active contact AC.

The third interlayer dielectric layer130may include recesses RS on an upper portion thereof, e.g., each of the recesses RS may extend from a top surface of the third interlayer dielectric layer130to a predetermined depth along the third direction D3. The recesses RS may be formed on corresponding lower connection lines M1. Each of the recesses RS may vertically overlap the conductive pattern FM of a corresponding lower connection line M1. When viewed in a plan view, each recess RS may extend in the second direction D2along the, e.g., entire, lower connection line M1thereunder.

The recess RS may expose a top surface FMt of the conductive pattern FM of the lower connection line M1. The recess RS may not expose a top surface BMt of the barrier pattern BM of the lower connection line M1. For example, the third interlayer dielectric layer130may cover the top surface BMt of the barrier pattern BM of the lower connection line M1.

The third interlayer dielectric layer130may have a top surface130tat a level higher than that of the top surface FMt of the conductive pattern FM of the lower connection line M1, e.g., along the third direction D3. The level of the top surface130tof the third interlayer dielectric layer130may be higher than that of a bottom of the recess RS.

For example, the third interlayer dielectric layer130may include a part130pthat vertically protrudes between a pair of neighboring lower connection lines M1, e.g., each part130pmay vertically protrude between adjacent recesses RS. The part130pof the third interlayer dielectric layer130may be on the top surface BMt of the barrier pattern BM of the lower connection line M1. For example, the part130pof the third interlayer dielectric layer130may cover the top surface BMt of the barrier pattern BM of the lower connection line M1, e.g., the part130pof the third interlayer dielectric layer130may extend continuously to cover the top surfaces BMt of facing barrier patterns BM of adjacent lower connection lines M1. The part130pof the third interlayer dielectric layer130may be positioned higher than the top surface FMt of the conductive pattern FM of the lower connection line M1.

An etch stop layer EST may be interposed between the third interlayer dielectric layer130and the fourth interlayer dielectric layer140. The etch stop layer EST may cover the top surface130tof the third interlayer dielectric layer130. The etch stop layer EST may partially fill the recess RS. The etch stop layer EST may cover the top surface FMt of the conductive pattern FM of the lower connection line M1, which top surface FMt is exposed to the recess RS. A step difference between the recess RS and the top surface130tof the third interlayer dielectric layer130may allow the etch stop layer EST to have a stepwise structure on the recess RS. The etch stop layer EST may include, e.g., one or more of SiN, SiON, SiCN, and SiCON.

Upper connection lines M2may be provided in the fourth interlayer dielectric layer140. Each of the upper connection lines M2may have a linear shape extending in the first direction D1. The upper connection lines M2may be arranged spaced apart from each other along the second direction D2. Each of the upper connection lines M2may include a barrier pattern BM and a conductive pattern FM. A detailed description of the barrier pattern BM and the conductive pattern FM may be the same as that of the barrier pattern BM and the conductive pattern FM of the via VI discussed above.

For example, as illustrated inFIGS.1and2B, the upper connection lines M2may include a first upper connection line M21, a second upper connection line M22, and a third upper connection line M23that are adjacent to each other along the second direction D2. Portions of the fourth interlayer dielectric layer140may separate between the upper connection lines M2. The second upper connection line M22may be provided on and connected to the second lower connection line M12.

For example, the second upper connection line M22may include a vertical extension part VP that vertically extends, e.g., along the third direction D3, toward the substrate100. The vertical extension part VP may penetrate the fourth interlayer dielectric layer140and the etch stop layer EST to have a connection with the second lower connection line M12. For example, the second upper connection line M22may be electrically connected through the vertical extension part VP to the second lower connection line M12.

The vertical extension part VP may be a portion of the second upper connection line M22. The upper connection lines M2may be formed by a dual damascene process. In contrast, the via VI and the lower connection lines M1may each be formed by a single damascene process. The barrier pattern BM of the second lower connection line M12may be interposed between the via VI and the conductive pattern FM of the second lower connection line M12.

The vertical extension part VP may fill at least a portion of the recess RS above the second lower connection line M12. The vertical extension part VP may include a first segment P1in contact through the recess RS with the conductive pattern FM of the lower connection line M1, and also may include a second segment P2covering, e.g., a portion of, the top surface130tof the third interlayer dielectric layer130. The second segment P2of the vertical extension part VP may not fill the recess RS. The first segment P1may protrude more than the second segment P2toward the substrate100. For example, the first segment P1may have a bottom surface lower than that of the second segment P2. The etch stop layer EST may cover a lower sidewall of the second segment P2. For example, as illustrated inFIGS.2A-2B, only the second lower connection line M12and the second upper connection line M22among the lower and upper connection lines M1and M2may contact each other above the via VI, while a bottom of the fourth interlayer dielectric layer140may separate the other lower and upper connection lines M1and M2from each other.

For example, as illustrated inFIG.1, additional vias may be formed on the substrate100(dashed rectangles inFIG.1), so additional connections among different ones of the lower and upper connection lines M1and M2may be provided accordingly. For example, additional connection lines may be provided on the upper connection lines M2. For example, a plurality of metal layers may be provided on the upper connection lines M2.

FIGS.3A,4A,5A,6A,7A, and8Aillustrate cross-sectional views taken along line I-I′ ofFIG.1, showing a method of manufacturing a semiconductor device according to some example embodiments.FIGS.3B,4B,5B,6B,7B, and8Billustrate cross-sectional views taken along line II-II′ ofFIG.1, showing a method of manufacturing a semiconductor device according to some example embodiments.

Referring toFIGS.1,3A, and3B, transistors may be formed on the active region AR of the substrate100. The transistors may include the active patterns AP having the source/drain patterns SD and may also include the gate electrodes GE running across the active patterns AP.

The first interlayer dielectric layer110may be formed to cover the transistors. The active contact AC may be formed to penetrate the first interlayer dielectric layer110and to have connection with the source/drain patterns SD.

The second interlayer dielectric layer120may be formed on the first interlayer dielectric layer110. The via VI may be formed in the second interlayer dielectric layer120. The via VI may be formed by a single damascene process. For example, the formation of the via VI may include forming a hole by patterning the second interlayer dielectric layer120, and forming the barrier pattern BM and the conductive pattern FM that fill the hole.

A sacrificial layer SL may be formed on the second interlayer dielectric layer120. The sacrificial layer SL may include, e.g., a silicon oxide layer or a carbon-containing silicon oxide layer. Lower connection lines M1may be formed in the sacrificial layer SL. The lower connection lines M1may include first, second, and third lower connection lines M11, M12, and M13that are adjacent to each other. The lower connection lines M1may be formed by a single damascene process. For example, the formation of the lower connection lines M1may include forming holes by patterning the sacrificial layer SL, and forming the barrier pattern BM and the conductive pattern FM that fill each of the holes.

Referring toFIGS.1,4A, and4B, capping patterns CP may be formed on corresponding lower connection lines M1. The capping pattern CP may be formed to cover the top surface FMt of the conductive pattern FM of the lower connection line M1. The capping pattern CP may not cover the top surface BMt of the barrier pattern BM of the lower connection line M1.

The formation of the capping patterns CP may use spin coating, ALD, CVD, or PVD. The capping patterns CP may be formed using metal, e.g., Ti, Mo, Ta, Mn, Al, Co, Ru, or a combination thereof.

The capping pattern CP may be selectively formed on the conductive pattern FM of the lower connection line M1. For example, the capping pattern CP may be formed using metal exhibiting affinity to that of the conductive pattern FM, so the capping pattern CP may be self-alignedly formed on the conductive pattern FM, e.g., without being formed on the barrier pattern BM.

Referring toFIGS.1,5A, and5B, the sacrificial layer SL may be selectively removed. The removal of the sacrificial layer SL may include performing a wet etching process, an ashing process, a dry etching process, or a combination thereof. For example, when the sacrificial layer SL contains carbon, an ashing process may be performed to damage the sacrificial layer SL, and then a wet etching process or a dry etching process may be performed to selectively remove the damaged sacrificial layer SL. The second interlayer dielectric layer120may be kept when the sacrificial layer SL is removed. The removal of the sacrificial layer SL may expose sidewalls of the capping patterns CP and sidewalls of the lower connection lines M1.

Referring toFIGS.1,6A, and6B, the third interlayer dielectric layer130may be formed to cover the exposed capping patterns CP and lower connection lines M1. The third interlayer dielectric layer130may cover top surfaces of the capping patterns CP. The third interlayer dielectric layer130may have a top surface higher than those of the capping patterns CP. The third interlayer dielectric layer130may be formed by an ALD process or a flowable chemical vapor deposition (FCVD) process exhibiting superior gap-fill characteristics. The third interlayer dielectric layer130may include a silicon oxide layer whose dielectric constant is low.

Referring toFIGS.1,7A, and7B, the third interlayer dielectric layer130may undergo a planarization process, which is performed until the top surfaces of the capping patterns CP are exposed. As a result, the third interlayer dielectric layer130may have a planarized top surface130t, which is coplanar with the top surfaces of the capping patterns CP. The top surfaces of the capping patterns CP may be exposed.

The exposed capping patterns CP may be selectively removed. The capping patterns CP may be removed by a selective wet etching process. The removal of the capping patterns CP may define the recesses RS on an upper portion of the third interlayer dielectric layer130. Each of the recesses RS may expose the top surface FMt of the conductive pattern FM of the lower connection line M1. For example, the top surface FMt of the conductive pattern FM may define a bottom of the recess RS. The recess RS may extend in the second direction D2along the lower connection line M1thereunder. The top surface130tof the third interlayer dielectric layer130may be located at a level higher than that of the top surface FMt of the conductive pattern FM of the lower connection line M1.

Referring toFIGS.1,8A, and8B, an etch stop layer EST may be formed on the third interlayer dielectric layer130. The etch stop layer EST may be conformally formed to partially fill the recess RS. The etch stop layer EST may include, e.g., one or more of SiN, SiON, SiCN, and SiCON.

The fourth interlayer dielectric layer140may be formed on the etch stop layer EST. The fourth interlayer dielectric layer140may be patterned to form connection line holes HO. For example, a patterning process may be performed twice to cause at least one connection line hole HO to include a vertical extension hole VHO. The vertical extension hole VHO may penetrate the etch stop layer EST and expose the top surface FMt of the conductive pattern FM of the second lower connection line M12.

The vertical extension hole VHO may be formed in a self-aligned manner caused by the recess RS. The vertical extension hole VHO may not expose the top surface BMt of the barrier pattern BM of the second lower connection line M12. The recess RS may allow the vertical extension hole VHO to selectively expose the top surface FMt of the conductive pattern FM of the second lower connection line M12.

Referring back toFIGS.1,2A, and2B, the upper connection lines M2may be formed to fill the connection line holes HO. The upper connection lines M2may include first, second, and third upper connection lines M21, M22, and M23that are adjacent to each other. The upper connection lines M2may be formed by a dual damascene process. The formation of the upper connection lines M2may include forming the barrier pattern BM and the conductive pattern FM that fill each of the connection line holes HO.

The sacrificial layer SL may be damaged during the formation of the lower connection lines M1. According to some example embodiments, the damaged sacrificial layer SL may be replaced with the third interlayer dielectric layer130. Because the lower connection lines M1are provided therebetween with a damage-free dielectric layer whose dielectric constant is low, it may be possible to reduce a parasitic capacitance and to improve electrical characteristics of semiconductor devices.

In addition, the vertical extension part VP of the second upper connection line M22may be formed in a self-aligned manner caused by the recess RS on the upper portion of the third interlayer dielectric layer130. As a result, an electrical short may be avoided between the vertical extension part VP of the second upper connection line M22and one of the first lower connection line M11and the third lower connection line M13.

FIGS.9A and9Billustrate cross-sectional views respectively taken along lines I-I′ and II-II′ ofFIG.1, showing a semiconductor device according to some example embodiments. In the embodiment that follows, a detailed description of technical features repetitive to those of the semiconductor device discussed above with reference toFIGS.1,2A, and2Bwill be omitted, and a difference thereof will be discussed in detail.

Referring toFIGS.1,9A, and9B, the lower connection lines M1may be formed by a dual damascene process. For example, the second lower connection line M12may include a vertical extension part VP that vertically extends toward the substrate100. The vertical extension part VP may penetrate the second interlayer dielectric layer120and have connection with the active contact AC. For example, the second lower connection line M12may be electrically connected through the vertical extension part VP to the active contact AC.

The second interlayer dielectric layer120may cover a sidewall of the vertical extension part VP of the second lower connection line M12. Because the third interlayer dielectric layer130is provided on the second interlayer dielectric layer120, the third interlayer dielectric layer130may be located higher than the vertical extension part VP of the second lower connection line M12.

FIGS.10A and11Aillustrate cross-sectional views taken along line I-I′ ofFIG.1, showing a method of manufacturing a semiconductor device according to some example embodiments.FIGS.10B and11Billustrate cross-sectional views taken along line II-II′ ofFIG.1, showing a method of manufacturing a semiconductor device according to some example embodiments. In the embodiment that follows, a detailed description of technical features repetitive to those of the manufacturing method discussed above with reference toFIGS.1to8Bwill be omitted, and a difference thereof will be discussed in detail.

Referring toFIGS.1,10A, and10B, the lower connection lines M1may be formed in the second interlayer dielectric layer120. The lower connection lines M1may be formed by a dual damascene process. For example, the formation of the lower connection lines M1may be substantially the same as that of the upper connection lines M2discussed above with reference toFIGS.8A and8B. The capping patterns CP may be formed on corresponding lower connection lines M1.

Referring toFIGS.1,11A, and11B, the second interlayer dielectric layer120may be recessed. During the recess of the second interlayer dielectric layer120, an upper portion of the second interlayer dielectric layer120may be removed, and a lower portion of the second interlayer dielectric layer120may remain. The remaining second interlayer dielectric layer120may cover the vertical extension part VP of the second lower connection line M12.

In case that the second interlayer dielectric layer120is completely removed, the lower connection lines M1may collapse. In the present embodiment, because the upper portion of the second interlayer dielectric layer120is removed and the lower portion of the second interlayer dielectric layer120remains, the lower connection lines M1may be stably supported by the lower portion of the second interlayer dielectric layer120.

Subsequent processes may be the same as those discussed above with reference toFIGS.6A to8B.

FIG.12illustrates a cross-sectional view taken along line I-I′ ofFIG.1, showing a semiconductor device according to some example embodiments. In the embodiment that follows, a detailed description of technical features repetitive to those of the semiconductor device discussed above with reference toFIGS.1,2A, and2Bwill be omitted, and a difference thereof will be discussed in detail.

Referring toFIGS.1,2B, and12, one or more liners LIN may be interposed between the third interlayer dielectric layer130and the lower connection lines M1. The liner LIN may include a first segment that extends horizontally and covers a top surface of the second interlayer dielectric layer120, and may also include a second segment that extends vertically and covers the sidewall of the lower connection line M1. For example, the liner LIN may include a silicon oxide layer or a silicon nitride layer.

The liner LIN adjacent to the recess RS may cover the top surface BMt of the barrier pattern BM of the lower connection line M1. The liner LIN adjacent to the recess RS may define a side of the recess RS. The liner LIN adjacent to the recess RS may be interposed between the etch stop layer EST and the third interlayer dielectric layer130. The liner LIN adjacent to the recess RS may have a top surface LINt coplanar with the top surface130tof the third interlayer dielectric layer130. The top surface LINt of the liner LIN may be located at a level higher than that of the top surface FMt of the conductive pattern FM of the lower connection line M1.

FIGS.13and14illustrate cross-sectional views taken along line I-I′ ofFIG.1, showing a method of manufacturing a semiconductor device according to some example embodiments. In the embodiment that follows, a detailed description of technical features repetitive to those of the manufacturing method discussed above with reference toFIGS.1to8Bwill be omitted, and a difference thereof will be discussed in detail.

Referring toFIGS.1and13, the liner LIN may be conformally formed on a resultant structure ofFIGS.5A and5B. The liner LIN may cover surfaces of the exposed lower connection lines M1and surfaces of the exposed capping patterns CP. The liner LIN may protect the exposed lower connection lines M1.

Referring toFIGS.1and14, the third interlayer dielectric layer130may be formed on the liner LIN. The third interlayer dielectric layer130may undergo a planarization process, which is performed until the top surfaces of the capping patterns CP are exposed. The exposed capping patterns CP may be selectively removed. The removal of the capping patterns CP may define the recesses RS on the upper portion of the third interlayer dielectric layer130. An upper portion of the liner LIN may define a side of the recess RS.

Subsequent processes may be the same as those discussed above with reference toFIGS.8A and8B.

FIG.15illustrates a cross-sectional view taken along line I-I′ ofFIG.1, showing a semiconductor device according to some example embodiments. In the embodiment that follows, a detailed description of technical features repetitive to those of the semiconductor device discussed above with reference toFIGS.1,2B, and12will be omitted, and a difference thereof will be discussed in detail.

Referring toFIGS.1,2B, and15, air gaps AG may be defined in the third interlayer dielectric layer130. The air gaps AG may be defined between the first and second lower connection lines M11and M12and between the second and third lower connection lines M12and M13. Each of the air gaps AG may extend in the second direction D2between a pair of neighboring lower connection lines M1.

A width in the first direction D1of the air gap AG may decrease with increasing distance from the substrate100. The air gap AG may be surrounded by the third interlayer dielectric layer130and the etch stop layer EST. The air gap AG may reduce a parasitic capacitance between neighboring lower connection lines M1.

FIG.16illustrates a cross-sectional view taken along line I-I′ ofFIG.1, showing a method of manufacturing a semiconductor device according to some example embodiments. In the embodiment that follows, a detailed description of technical features repetitive to those of the manufacturing method discussed above with reference toFIGS.1to8BandFIGS.13and14will be omitted, and a difference thereof will be discussed in detail.

Referring toFIGS.1and16, the third interlayer dielectric layer130may be formed on a resultant structure ofFIG.13. During the formation of the third interlayer dielectric layer130, an air gap AG may be formed between a pair of neighboring lower connection lines M1.

Subsequent processes may be the same as those discussed above with reference toFIGS.7A to8B.

FIG.17illustrates a cross-sectional view taken along line I-I′ ofFIG.1, showing a semiconductor device according to some example embodiments. In the embodiment that follows, a detailed description of technical features repetitive to those of the semiconductor device discussed above with reference toFIGS.1,2A, and2Bwill be omitted, and a difference thereof will be discussed in detail.

Referring toFIGS.1,2B, and17, the vertical extension part VP of the second upper connection line M22may be offset in the first direction D1more than the vertical extension part VP ofFIG.2A. For example, the vertical extension part VP may not be aligned with a center of the second lower connection line M12.

The second segment P2of the vertical extension part VP may be adjacent to the first lower connection line M11. The second segment P2of the vertical extension part VP may have a bottom surface higher than the top surface FMt of the conductive pattern FM of the first lower connection line M1, with the result that an electrical short may be avoided between the vertical extension part VP and the first lower connection line M11.

In the present embodiment, even when the vertical extension part VP of the second upper connection line M22is misaligned with the center of the second lower connection line M12, the recess RS of the third interlayer dielectric layer130may prevent process defects such as an electrical short.

By way of summation and review, example embodiments provide a semiconductor device with improved electrical characteristics. Example embodiments also provide a method of manufacturing a semiconductor device, in which method process defects are avoided.

That is, according to example embodiments, the lower connection lines are provided therebetween with a damage-free dielectric layer whose dielectric constant is low, thereby reducing parasitic capacitance between the lower connection lines and improving electrical characteristics of the semiconductor device. Further, a vertical extension part of the second upper connection line may be formed in a self-aligned manner caused by the recess on the upper portion of the third interlayer dielectric layer, thereby preventing or substantially minimizing an electrical short between the vertical extension part and the first lower connection lines.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.