Patent ID: 12199118

DETAILED DESCRIPTION OF THE EMBODIMENTS

It will be understood that when an element or layer is referred to as being “over,” “above,” “on,” “below,” “under,” “beneath,” “connected to” or “coupled to” another element or layer, it can be directly over, above, on, below, under, beneath, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly over,” “directly above,” “directly on,” “directly below,” “directly under,” “directly beneath,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. Like numerals refer to like elements throughout.

Spatially relative terms, such as “over,” “above,” “on,” “upper,” “below,” “under,” “beneath,” “lower,” and the like, may be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

For the sake of brevity, conventional elements to semiconductor devices may or may not be described in detail herein for brevity purposes.

Although the terms first, second, etc. may be used herein to describe various elements or components, these elements or components should not be limited by these terms. These terms are used to distinguish one element or component from another element or component. Thus, a first element or component discussed below could be termed a second element or component without departing from the teachings of the disclosure.

Hereinafter, image sensors according to example embodiments will be described with reference toFIGS.1to23.

FIG.1is an example block diagram illustrating an image sensor according to some embodiments.FIG.2is an example circuit diagram explaining a unit pixel of an image sensor according to some embodiments.

Referring toFIG.1, the image sensor according to some embodiments may include an active pixel sensor array (APS)10, a row decoder20, a row driver30, a column decoder40, a timing generator50, a correlated double sampler (CDS)60, an analog-to-digital converter (ADC)70, and an input/output (I/O) buffer80.

The APS10may include a plurality of unit pixels arranged two-dimensionally and may convert an optical signal into an electrical signal. The APS10may be driven by driving signals such as a pixel selection signal, a reset signal, and a charge transfer signal received from the row driver30. Further, the electrical signal converted by the APS10may be provided to the CDS60.

The row driver30may provide the APS10with a plurality of driving signals to drive a plurality of unit pixels according to the decoding result of the row decoder20. When the unit pixels are arranged in a matrix, driving signals may be provided for each row.

The timing generator50may provide a timing signal and a control signal to the row decoder20and the column decoder40.

The CDS60may receive the electrical signal generated by the APS10, and may hold and sample the received signal. The CDS60may double-sample a certain noise level and a signal level according to the electrical signal, and may output a difference level corresponding to a difference between the noise level and the signal level.

The ADC70may convert an analog signal corresponding to the difference level outputted from the CDS60into a digital signal, and may output the digital signal.

The I/O buffer80may latch digital signals, and the latched signals may be sequentially outputted as the digital signals to an image signal processor according to the decoding result of the column decoder40.

Referring toFIG.2, each of the unit pixels may include a photoelectric conversion element PD, a transfer transistor TG, a floating diffusion region FD, a reset transistor RG, a source follower transistor SF, and a select transistor SEL.

The photoelectric conversion element PD may generate electric charges in proportion to an amount of light incident from the outside. The photoelectric conversion element PD may be coupled with the transfer transistor TG that transfers the generated and accumulated charges to the floating diffusion region FD. The floating diffusion region FD converts the charges into a voltage, and has a parasitic capacitance so that the charges can be stored cumulatively.

One end of the transfer transistor TG may be connected to the photoelectric conversion element PD, and the other end of the transfer transistor TG may be connected to the floating diffusion region FD. The transfer transistor TG may be formed of a transistor driven by a predetermined bias (e.g., a transfer signal TX). That is, the transfer transistor TG may transfer the charges generated from the photoelectric conversion element PD to the floating diffusion region FD in response to the transfer signal TX.

The source follower transistor SF may amplify a change in the electrical potential of the floating diffusion region FD that has received the charges from the photoelectric conversion element PD and output the amplified change to an output line VOUT. When the source follower transistor SF is turned on, a predetermined electrical potential, e.g., a power voltage VDD, provided to the drain of the source follower transistor SF, may be transferred to the drain region of the select transistor SEL.

The select transistor SEL may select a unit pixel to be read on a row basis. The select transistor SEL may be formed of a transistor driven by a select line through which a predetermined bias (e.g., a row select signal SX) is applied.

The reset transistor RG may periodically reset the floating diffusion region FD. The reset transistor RG may be formed of a transistor driven by a reset line through which a predetermined bias (e.g., a reset signal RX) is applied. When the reset transistor RG is turned on by the reset signal RX, a predetermined electrical potential, e.g., the power voltage VDD, provided to the drain of the reset transistor RG may be transferred to the floating diffusion region FD.

FIG.3is a schematic layout diagram of a light receiving region in an image sensor according to some embodiments.FIG.4is an example partial layout diagram illustrating a first region and a second region ofFIG.3.FIG.5is a cross-sectional view taken along lines A-A and B-B ofFIG.4.FIG.6is an enlarged view illustrating area E ofFIG.5.

Referring toFIG.3, the image sensor according to some embodiments includes a light receiving region APS.

A plurality of unit pixels UP that receive light and generate electrical signals may be disposed in the light receiving region APS. The unit pixels UP may be arranged two-dimensionally (e.g., in a matrix form) in a plane including a first direction X and a second direction Y. The active pixel sensor array10ofFIG.1may include a region corresponding to the light receiving region APS.

The light receiving region APS may include a first region I to a fourth region IV. The first region I may include the unit pixels UP adjacent to a center CP of the light receiving region APS. The second region II may include the unit pixels UP that are farther than the first region I from the center CP of the light receiving region APS. For example, the second region II may be spaced apart from the first region I in the first direction X. The third region III may include the unit pixels UP that are spaced apart from the first region I in a diagonal direction. For example, the second region II may be spaced apart from the third region III in the second direction Y. The fourth region IV may include the unit pixels UP that are farther than the second region II from the center CP of the light receiving region APS. For example, the fourth region W may be spaced apart from the second region II in the first direction X.

Each of the unit pixels UP may generate an electrical signal by sensing a predetermined color. For example, each of the unit pixels UP may receive light passing through one of a first color filter RP, a second color filter GP, and a third color filter BP to generate an electrical signal.

The first color filter RP, the second color filter GP, and the third color filter BP may include a red color filter, a green color filter, and a blue color filter, respectively. However, this is merely example, and the first color filter RP, the second color filter GP, and the third color filter BP may include a yellow filter, a magenta filter, and a cyan filter, respectively, or may further include a white filter.

The first color filter RP, the second color filter GP, and the third color filter BP may filter different colors. As an example, the first color filter RP may be a red color filter, the second color filter GP may be a green color filter, and the third color filter BP may be a blue color filter.

In some embodiments, the first color filter RP, the second color filter GP, and the third color filter BP may be arranged in a Bayer pattern. For example, two second color filters GP may be arranged along a diagonal direction other than the first direction X and the second direction Y. The first color filter RP may be arranged along the first direction X together with one second color filter GP, and may be arranged along the second direction Y together with the other second color filter GP. In addition, the third color filter BP may be arranged along the second direction Y together with one second color filter GP, and may be arranged along the first direction X together with the other second color filter GP. The first color filter RP and the third color filter BP may be arranged along a diagonal direction other than the first direction X and the second direction Y.

In some embodiments, at least some adjacent unit pixels UP may form a merged pixel that shares one color filter. For example, four unit pixels UP arranged in a 2×2 array may share one of the first color filter RP, the second color filter GP, and the third color filter BP.

Referring toFIGS.3to6, the image sensor according to some embodiments includes a first substrate110, a photoelectric conversion layer112, a pixel isolation pattern120, a first electronic element TR1, a first wiring structure IS1, a surface insulating layer140, a color filter170, a grid pattern150, and a microlens180.

The first substrate110may be a semiconductor substrate. For example, the first substrate110may be a bulk silicon or silicon-on-insulator (SOI) substrate. The first substrate110may be a silicon substrate, or may include other materials such as silicon germanium, indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the first substrate110may have an epitaxial layer formed on a base substrate.

The first substrate110may include a first surface110aand a second surface110bopposite to each other. In embodiments to be described later, the first surface110amay be referred to as a back surface of the first substrate110, and the second surface110bmay be referred to as a front surface of the first substrate110. In some embodiments, the first surface110aof the first substrate110may be a light receiving surface on which light is incident. That is, the image sensor according to some embodiments may be a backside illuminated (BSI) image sensor.

The photoelectric conversion layer112may be formed in the first substrate110. The plurality of photoelectric conversion layers112may be arranged to correspond to the plurality of unit pixels UP such that each photoelectric conversion layer112corresponds to a respective unit pixel UP. For example, the photoelectric conversion layers112may be arranged two-dimensionally (e.g., in a matrix form) in a plane including the first direction X and the second direction Y and may be disposed in the unit pixels UP. The photoelectric conversion layer112may generate electric charges in proportion to an amount of light incident from the outside.

The photoelectric conversion layer112may be formed by doping impurities into the first substrate110. For example, the photoelectric conversion layer112may be formed by ion-implanting n-type impurities into the first substrate110which is of a p-type. In some embodiments, the photoelectric conversion layer112may have a potential slope in a third direction Z crossing the surface (e.g., the first surface110aor the second surface110b) of the first substrate110. For example, the impurity concentration of the photoelectric conversion layer112may decrease from the second surface110btoward the first surface110a.

The photoelectric conversion layer112may include, for example, at least one of a photodiode, a phototransistor, a photogate, a pinned photodiode, an organic photodiode, quantum dots, or a combination thereof, but is not limited thereto.

The pixel isolation pattern120may be formed in the first substrate110. The pixel isolation pattern120may define the plurality of unit pixels UP in the first substrate110. For example, the pixel isolation pattern120may be formed in a grid shape in plan view, and may surround each of the unit pixels UP arranged in a matrix form.

In some embodiments, the pixel isolation pattern120may penetrate the first substrate110. For example, the pixel isolation pattern120may continuously extend from the second surface110bof the first substrate110to the first surface110aof the first substrate110.

In some embodiments, the pixel isolation pattern120may have a width that decreases as it moves away from the second surface110bof the first substrate110. Here, the width means a width in a direction parallel to the surface (e.g., the first surface110aor the second surface110b) of the first substrate110. This may be due to the characteristics of an etching process for forming the pixel isolation pattern120. For example, a process of etching the first substrate110to form the pixel isolation pattern120may be performed on the second surface110bof the first substrate110.

In some embodiments, the pixel isolation pattern120may include a conductive filling pattern122and an insulating spacer layer124. For example, an isolation trench defining the plurality of unit pixels UP may be formed in the first substrate110. The insulating spacer layer124may extend along the side surface of the isolation trench. The conductive filling pattern122may be formed on the insulating spacer layer124to fill the remaining region of the isolation trench. The insulating spacer layer124may electrically insulate the conductive filling pattern122from the first substrate110.

The conductive filling pattern122may include, for example, polysilicon (poly Si), but is not limited thereto. In some embodiments, a ground voltage or a negative voltage may be applied to the conductive filling pattern122. In this case, an electrostatic discharge (ESD) bruise defect of the image sensor may be effectively prevented. Here, the ESD bruise defect refers to a phenomenon in which electric charges generated by ESD or the like are accumulated in the first substrate110, causing spots such as bruises in a generated image.

The insulating spacer layer124may include, for example, at least one of silicon oxide, aluminum oxide, tantalum oxide, or a combination thereof, but is not limited thereto. In some embodiments, the insulating spacer layer124may include a low refractive index material having a lower refractive index than that of the first substrate110. In this case, the insulating spacer layer124may refract or reflect light incident obliquely on the photoelectric conversion layer112to improve light collection efficiency, thereby improving the quality of the image sensor. Further, the insulating spacer layer124may prevent photocharges generated in a specific unit pixel UP by incident light from moving to adjacent unit pixels UP by random drift.

The first electronic element TR1may be formed on the second surface110bof the first substrate110. The first electronic element TR1may include various transistors for processing the electrical signals generated from the unit pixels UP. For example, the first electronic element TR1may include transistors such as the transfer transistor TG, the reset transistor RG, the source follower transistor SF, or the select transistor SEL described above with reference toFIG.2.

In some embodiments, the first electronic element TR1may include a vertical transfer transistor. For example, the first electronic element TR1including the above-described transfer transistor TG may partially extend into the first substrate110. The transfer transistor TG may reduce the area of the unit pixel UP, thereby enabling high integration of the image sensor.

The first wiring structure IS1may be formed on the second surface110bof the first substrate110. The first wiring structure IS1may include one or a plurality of wires. For example, the first wiring structure IS1may include a first inter-wire insulating layer130and a plurality of first wires132in the first inter-wire insulating layer130. InFIG.5, the arrangement and the number of layers of wires constituting the first wiring structure IS1are merely examples, and the technical spirit of the disclosure is not limited thereto.

In some embodiments, the first wires132may be electrically connected to the unit pixels UP. For example, the first wire132may be connected to the first electronic element TR1.

The surface insulating layer140may be formed on the first surface110aof the first substrate110. The surface insulating layer140may extend along the first surface11aof the first substrate110. The surface insulating layer140may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, or a combination thereof, but is not limited thereto.

In some embodiments, the surface insulating layer140may be formed of multiple films. For example, the surface insulating layer140may include an aluminum oxide film, a hafnium oxide film, a silicon oxide film, a silicon nitride film, and a hafnium oxide film that are sequentially stacked on the first surface110aof the first substrate110.

The surface insulating layer140may function as an antireflection layer to prevent reflection of light incident on the first substrate110. Accordingly, the light receiving rate of the photoelectric conversion layer112may be improved. In addition, the surface insulating layer140may function as a planarization layer to allow the color filters170and the microlenses180, which will be described later, to be formed with a uniform height.

The color filter170may be formed on the first surface110aof the first substrate110. For example, the color filter170may be formed on the surface insulating layer140. The plurality of color filters170may be arranged two-dimensionally (e.g., in a matrix form) in a plane including the first direction X and the second direction Y. For example, the color filter170may include the first color filter RP, the second color filter GP, and the third color filter BP described above with reference toFIG.3.

Each of the first region I and the second region II may include a merged pixel that shares one of the plurality of color filters170. As an example, the first region I may include a first merged pixel P11to P14(i.e., a first group of unit pixels) sharing the first color filter RP, and the second region II may include a second merged pixel P21to P24sharing the first color filter RP. However, this is merely an example, and each of the first merged pixel P11to P14and the second merged pixel P21to P24may share a different color filter. For example, the first merged pixel P11to P14may share the first color filter RP, and the second merged pixel P21to P24may share the second color filter GP or the third color filter BP other than the first color filter RP.

The grid pattern150may be formed on the first surface110aof the first substrate110. For example, the grid pattern150may be formed on the surface insulating layer140. The grid pattern150may be formed in a grid shape in plan view and surround each of the unit pixels UP arranged in a matrix form. For example, the grid pattern150may be formed to overlap the pixel isolation pattern120in the third direction Z.

The grid pattern150may cross the color filter170from an edge to an opposite edge. For example, the grid pattern150may be formed in a grid shape in plan view and surround each of the color filters170arranged in a matrix form. In addition, as described above, since one color filter170may be shared by a plurality of unit pixels UP, the grid pattern150may cross the inside of one color filter170.

The grid pattern150may define a light receiving area of each of the unit pixels UP. Herein, the light receiving area may mean an area in which light incident toward the first surface110aof the first substrate110can pass through the grid pattern150in plan view. For example, as shown inFIG.4, the grid pattern150may define light receiving areas S11to S14of the first merged pixel P11to P14and light receiving areas S21to S24of the second merged pixel P21to P24. As the width of the grid pattern150increases, the light receiving areas S11to S14of the first merged pixel P11to P14and the light receiving areas S21to S24of the second merged pixel P21to P24may decrease.

The light receiving areas of the unit pixels UP included in the merged pixel may vary depending on positions where the unit pixels UP are disposed.

In some embodiments, the light receiving areas of at least some of the unit pixels UP may decrease as the unit pixels are farther away from the center CP of the light receiving region APS. For example, the light receiving areas S21and S23of the pixels P21and P23may be smaller than the light receiving areas S11and S13of the pixels P11and P13. As an example, a width W21of the grid pattern150defining the light receiving areas S21and S23on the left surfaces of the pixels P21and P23(i.e., a second portion of the grid pattern150) may be greater than a width W11of the grid pattern150defining the light receiving areas S11and S13on the left surfaces of the pixels P11and P13(i.e., a first portion of the grid pattern150). A width W23of the grid pattern150defining the light receiving areas S21and S22on the top surfaces of the pixels P21and P22may be the same as a width W13of the grid pattern150defining the light receiving areas S11and S12on the top surfaces of the pixels P11and P12. A width W24of the grid pattern150defining the light receiving areas S23and S24on the top surfaces of the pixels P23and P24may be the same as a width W14of the grid pattern150defining the light receiving areas S13and S14on the top surfaces of the pixels P13and P14. The term “same” as used herein not only means being completely identical but also includes a minute difference that may occur due to a process margin and the like.

In some embodiments, the light receiving areas of at least some of the unit pixels UP included in the second merged pixel P21to P24may decrease as the unit pixels are closer to the center CP of the light receiving region APS. For example, the light receiving areas S21and S23of the pixels P21and P23may be smaller than the light receiving areas S22and S24of the pixels P22and P24. For example, the width W21of the grid pattern150defining the light receiving areas S21and S23on the left surfaces of the pixels P21and P23may be greater than a width W22of the grid pattern150defining the light receiving areas S22and S24on the left surfaces of the pixels P22and P24.

In some embodiments, the light receiving areas of the unit pixels UP included in the first merged pixel P11to P14may be the same. For example, the light receiving area S11of the pixel P11, the light receiving area S12of the pixel P12, the light receiving area S13of the pixel P13, and the light receiving area S14of the pixel P14may be the same. As an example, the width W11of the grid pattern150defining the light receiving areas S11and S13on the left surfaces of the pixels P11and P13may be the same as a width W12of the grid pattern150defining the light receiving areas S12and S14on the left surfaces of the pixels P12and P14. The width W13of the grid pattern150defining the light receiving areas S11and S12on the top surfaces of the pixels P11and P12may be the same as the width W14of the grid pattern150defining the light receiving area S13and S14on the top surfaces of the pixels P13and P14.

In some embodiments, the grid pattern150may include a first material pattern152and a second material pattern154as shown, e.g., inFIG.5. The first material pattern152and the second material pattern154may be sequentially stacked on the surface insulating layer140. The first material pattern152and the second material pattern154may include different materials. As an example, the first material pattern152may be a metal pattern, and the second material pattern154may be an oxide pattern. As another example, the first material pattern152may be a first metal pattern, and the second material pattern154may be a second metal pattern different from the first metal pattern.

The metal pattern may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al), copper (Cu) or a combination thereof, but is not limited thereto. In some embodiments, the first material pattern152including the metal pattern may prevent the electric charges generated by ESD or the like from being accumulated on the surface (e.g., the first surface110a) of the first substrate110, thereby effectively preventing the ESD bruise defect.

The oxide pattern may include, for example, at least one of metal oxide such as titanium oxide, tantalum oxide, tungsten oxide, aluminum oxide, copper oxide, silicon oxide, or a combination thereof, but is not limited thereto. In some embodiments, the second material pattern154may include a low refractive index material having a lower refractive index than that of silicon (Si). In this case, the second material pattern154may refract or reflect light incident obliquely on the photoelectric conversion layer112to improve light collection efficiency, thereby improving the quality of the image sensor.

In some embodiments, the height of the grid pattern150may be lower than the height of the color filter170. For example, as shown inFIGS.5and6, with respect to the top surface of the surface insulating layer140, a height H1of the top surface of the grid pattern150may be lower than a height H2of the top surface of the color filter170. For example, with respect to the top surface of the surface insulating layer140, the height H1of the top surface of the grid pattern150may be about 3000 Å to about 5000 Å, and the height H2of the top surface of the color filter170may be about 5000 Å to about 10000 Å. In this case, the grid pattern150may not completely separate the color filters170. For example, as illustrated, the first color filter RP and the second color filter GP may be in contact with each other on the top surface of the grid pattern150.

In some embodiments, the height of the color filter170may decrease toward the edge of the color filter170. For example, as shown inFIGS.5and6, with respect to the top surface of the surface insulating layer140, the height H2of the top surface of the first color filter RP may decrease toward the second color filter GP. This may be due to the characteristics of a process for forming the color filter170on the grid pattern150. In some embodiments, the edge of the color filter170may include a convex curved surface170c. The height of the convex curved surface170cof the first color filter RP may decrease toward the second color filter GP.

In some embodiments, a first passivation layer160may be further formed on the surface insulating layer140and the grid pattern150. The first passivation layer160may conformally extend along the profiles of the top surface of the surface insulating layer140and the side and top surfaces of the grid pattern150. The first passivation layer160may be interposed between the surface insulating layer140and the color filter170and between the grid pattern150and the color filter170.

The first passivation layer160may prevent damage to the surface insulating layer140and the grid pattern150. The first passivation layer160may include, for example, aluminum oxide, but is not limited thereto.

The microlens180may be formed above the first surface110aof the first substrate110. For example, the microlens180may be formed on the color filter170. The plurality of microlenses180may be arranged to correspond to the plurality of unit pixels UP such that each microlens180corresponds to a respective unit pixel UP. For example, the plurality of microlenses180may be arranged two-dimensionally (e.g., in a matrix form) in a plane including the first direction X and the second direction Y.

The microlens180may have a convex shape and may have a predetermined radius of curvature. Accordingly, the microlens180may condense light incident on the photoelectric conversion layer112. The microlens180may include, for example, a light transmitting resin, but is not limited thereto.

In some embodiments, a second passivation layer185may be formed on the microlens180. The second passivation layer185may extend along the surface of the microlens180. The second passivation layer185may include inorganic oxide. For example, the second passivation layer185may include at least one of silicon oxide, titanium oxide, zirconium oxide, hafnium oxide, or a combination thereof, but is not limited thereto. As an example, the second passivation layer185may include low temperature oxide (LTO).

The second passivation layer185may protect the microlens180from the outside. For example, the second passivation layer185including inorganic oxide may cover and protect the microlens180including an organic material such as a light transmitting resin. In addition, the second passivation layer185may improve the quality of the image sensor by improving light collection efficiency of the microlens180. For example, the second passivation layer185may fill a space between the microlenses180, thereby reducing reflection, refraction, scattering, and the like of incident light reaching the space between the microlenses180.

In order to improve the performance of the image sensor, a merged pixel in which a plurality of adjacent unit pixels share one color filter is used. For example, the merged pixel has an advantage of being able to provide a bright image by operating as one pixel in a dark place of the image sensor, and provide a detailed image by being rearranged (re-mosaic) in a bright place of the image sensor.

Meanwhile, as the image sensor becomes increasingly highly integrated, there is a problem in that the sensitivity of each of the unit pixels constituting one merged pixel varies depending on its position. For example, in an electronic device including the image sensor, light incident from the outside may pass through a module lens and reach a light receiving region of the image sensor. In this case, the amount of light passing through the center portion of the module lens may be greater than the amount of light passing through the edge portion of the module lens. Accordingly, the sensitivities of the unit pixels adjacent to the center of the light receiving region among the unit pixels constituting one merged pixel may be greater than the sensitivities of the unit pixels away from the center of the light receiving region among the unit pixels constituting the one merged pixel. This difference in sensitivity causes a deterioration in the quality of an image generated when the merged pixel is rearranged (re-mosaic).

However, the image sensor according to some embodiments may improve the quality of a generated image by varying the light receiving areas depending on the positions of the unit pixels UP constituting the merged pixel. For example, as described above, in the second merged pixel P21to P24, the light receiving areas S21and S23of the pixels P21and P23closer to the center CP of the light receiving region APS may be smaller than the light receiving areas S22and S24of the pixels P22and P24farther away from the center CP of the light receiving region APS. Accordingly, a difference in sensitivity between the pixels P21and P23and the pixels P22and P24may be reduced, thereby providing the image sensor with improved quality.

In addition, the above sensitivity difference between the unit pixels constituting one merged pixel may increase as the unit pixels are farther away from the center of the light receiving region. However, the image sensor according to some embodiments may improve the quality of a generated image by varying the light receiving areas depending on the positions of the merged pixels. For example, as described above, the light receiving areas S21and S23of the pixels P21and P23in the second merged pixel P21to P24, which is away from the center CP of the light receiving region APS, may be smaller than the light receiving areas S11and S13of the pixels P11and P13in the first merged pixel P11to P14, which is adjacent to the center CP of the light receiving region APS. Accordingly, the image sensor with improved quality may be provided.

FIGS.7and8are various example partial layout diagrams illustrating first to third regions ofFIG.3. For simplicity of description, redundant parts of the description made with reference toFIGS.1to6may be recapitulated or omitted.

Referring toFIGS.3,7and8, in the image sensor according to some embodiments, the third region III spaced apart diagonally from the first region I may include a third merged pixel P31to P34that shares one of the plurality of color filters170.

For example, the third region III may include the third merged pixel P31to P34sharing the first color filter RP. However, this is merely an example, and the third merged pixel P31to P34may share the second color filter GP or the third color filter BP. The grid pattern150may define light receiving areas S31to S34of the third merged pixel P31to P34.

In some embodiments, the light receiving areas of at least some of the unit pixels UP may decrease as the unit pixels are farther away from the center CP of the light receiving region APS. For example, the light receiving areas S31, S32, and S33of the pixels P31, P32, and P33may be smaller than the light receiving areas S11, S12, and S13of the pixels P11, P12, and P13.

InFIG.7, as an example, widths W31and W33of the grid pattern150defining the light receiving areas S31, S32, and S33of the pixels P31, P32, and P33may be greater than the widths W11and W13of the grid pattern150defining the light receiving areas S11, S12, and S13of the pixels P11, P12, and P13. A width W34of the grid pattern150defining the light receiving areas S33and S34on the top surfaces of the pixels P33and P34may be the same as the width W14of the grid pattern150defining the light receiving areas S13and S14on the top surfaces of the pixels P13and P14.

In some embodiments, the light receiving areas of at least some of the unit pixels UP included in the third merged pixel P31to P34may decrease as the unit pixels are closer to the center CP of the light receiving region APS. For example, the light receiving area S31of the pixel P31may be smaller than the light receiving areas S32and S33of the pixels P32and P33.

InFIG.7, as an example, the width W31of the grid pattern150defining the light receiving areas S31and S33on the left surfaces of the pixels P31and P33may be greater than a width W32of the grid pattern150defining the light receiving areas S32and S34on the left surfaces of the pixels P32and P34. The width W33of the grid pattern150defining the light receiving areas S31and S32on the top surfaces of the pixels P31and P32may be greater than the width W34of the grid pattern150defining the light receiving areas S33and S34on the top surfaces of the pixels P33and P34.

InFIG.8, as another example, the width W22of the grid pattern150between the pixels P21and P23and the pixels P22and P24may be greater than the width W12of the grid pattern150between the pixels P11and P13and the pixels P12and P14. The width W24of the grid pattern150between the pixel P21and the pixel P23may be greater than a width W26of the grid pattern150between the pixel P22and the pixel P24.

InFIG.8, as another example, the width W32of the grid pattern150between the pixel P31and the pixel P32may be greater than the width W12of the grid pattern150between the pixel P11and the pixel P12. The width W32of the grid pattern150between the pixel P31and the pixel P32may be greater than a width W38of the grid pattern150between the pixel P33and the pixel P34. The width W34of the grid pattern150between the pixel P31and the pixel P33may be greater than a width W36of the grid pattern150between the pixel P32and the pixel P34.

FIG.9is an example partial layout diagram illustrating a first region, a second region, and a fourth region ofFIG.3. For simplicity of description, redundant parts of the description made with reference toFIGS.1to6may be recapitulated or omitted.

Referring toFIGS.3and9, in the image sensor according to some embodiments, the fourth region IV spaced apart from the second region II in the first direction X includes a fourth merged pixel P41to P44that shares one of the plurality of color filters170.

As an example, the fourth region IV may include the fourth merged pixel P41to P44that shares the first color filter RP. However, this is merely example, and the fourth merged pixel P41to P44may share the second color filter GP or the third color filter BP. The grid pattern150may define light receiving areas S41to S44of the fourth merged pixel P41to P44.

In some embodiments, the light receiving areas of at least some of the unit pixels UP may decrease as the unit pixels are farther away from the center CP of the light receiving region APS. For example, the light receiving areas S41and S43of the pixels P41and P43may be smaller than the light receiving areas S21and S23of the pixels P21and P23. As an example, a width W41of the grid pattern150defining the light receiving areas S41and S43on the left surfaces of the pixels P41and P43may be greater than the width W21of the grid pattern150defining the light receiving areas S21and S23on the left surfaces of the pixels P21and P23. A width W43of the grid pattern150defining the light receiving areas S41and S42on the top surfaces of the pixels P41and P42may be the same as the width W23of the grid pattern150defining the light receiving areas S21and S22on the top surfaces of the pixels P21and P22. A width W44of the grid pattern150defining the light receiving areas S43and S44on the top surfaces of the pixels P43and P44may be the same as the width W24of the grid pattern150defining the light receiving areas S23and S24on the top surfaces of the pixels P23and P24.

FIGS.10and11are various schematic layout diagrams of a light receiving region in an image sensor according to some embodiments. For simplicity of description, redundant parts of the description made with reference toFIGS.1to6may be recapitulated or omitted.

Referring toFIG.10, in the image sensor according to some embodiments, at least some of the unit pixels UP include a first focus pixel FP1.

The first focus pixel FP1may include a first sub-pixel LUP1and a second sub-pixel RUP1. The first sub-pixel LUP1and the second sub-pixel RUP1may be arranged along, for example, the first direction X.

Referring toFIG.11, in the image sensor according to some embodiments, at least some of the unit pixels UP further include a second focus pixel FP2.

The second focus pixel FP2may include a third sub-pixel LUP2and a fourth sub-pixel RUP2. The third sub-pixel LUP2and the fourth sub-pixel RUP2may be arranged along the second direction Y crossing the first direction X.

Each of the first focus pixel FP1and the second focus pixel FP2may perform an auto focus (AF) function. For example, since the first focus pixel FP1and the second focus pixel FP2may each include two sub-pixels (the first sub-pixel LUP1and the second sub-pixel RUP1, or the third sub-pixel LUP2and the fourth sub-pixel RUP2), it is possible to perform the auto focus function using a phase detection AF (PDAF).

FIG.12is a schematic layout diagram of a light receiving region in an image sensor according to some embodiments.FIG.13is an example partial layout diagram illustrating a first region ofFIG.12.FIG.14is a cross-sectional view taken along line C-C ofFIG.13.FIG.15is an example partial layout diagram illustrating a second region ofFIG.12.FIG.16is a cross-sectional view taken along line D-D ofFIG.15. For simplicity of description, redundant parts of the description made with reference toFIGS.1to6may be recapitulated or omitted.

Referring toFIG.12, in the image sensor according to some embodiments, nine unit pixels UP arranged in a 3×3 array may share one of the first color filter RP, the second color filter GP, and the third color filter BP.

Referring toFIGS.12to14, in the image sensor according to some embodiments, the first region I includes a first merged pixel P11to P19that shares one of the plurality of color filters170.

For example, the first region I may include the first merged pixel P11to P19that shares the first color filter RP. The grid pattern150may define light receiving areas S11to S19of the first merged pixel P11to P19.

In some embodiments, the light receiving areas of at least some of the unit pixels UP included in the first merged pixel P11to P19may decrease as the unit pixels are closer to the edge of the first color filter RP. For example, the first merged pixel P11to P19may include a first central pixel P15and a plurality of first peripheral pixels P11to P14and P16to P19. The first peripheral pixels P11to P14and P16to P19may surround the first central pixel P15in plan view as shown, e.g., inFIG.13. In this case, each of the light receiving areas S11to S14and S16to S19of the first peripheral pixels P11to P14and P16to P19may be smaller than the light receiving area S15of the first central pixel P15.

In some embodiments, the light receiving areas of at least some of the unit pixels UP included in the first peripheral pixels P11to P14and P16to P19may decrease as the unit pixels are closer to the vertex of the first color filter RP. For example, the pixels P11, P13, P17, and P19may be disposed adjacent to the vertex of the first color filter RP, and the pixels P12, P14, P16, and P18may be disposed away from the vertex of the first color filter RP. In this case, each of the light receiving areas S11, S13, S17, and S19of the pixels P11, P13, P17, and P19may be smaller than each of the light receiving areas S12, S14, S16, and S18of the pixels P12, P14, P16, and P18.

As an example, a width W11of the grid pattern150defining the light receiving area S11on the left surface of the pixel P11may be greater than widths W12and W13of the grid pattern150defining the light receiving area S12on the left and right surfaces of the pixel P12. The width W12of the grid pattern150between the pixel P11and the pixel P12may be greater than a width W14of the grid pattern150between the pixel P14and the pixel P15.

As an example, a width W15of the grid pattern150defining the light receiving area S13on the top surface of the pixel P13may be greater than widths W16and W17of the grid pattern150defining the light receiving area S16on the top and bottom surfaces of the pixel P16. The width W16of the grid pattern150between the pixel P13and the pixel P16may be greater than a width W18of the grid pattern150between the pixel P12and the pixel P15.

Referring toFIGS.12,15, and16, in the image sensor according to some embodiments, the second region II includes a second merged pixel P21to P29that shares one of the plurality of color filters170.

As an example, the second region II may include the second merged pixel P21to P29sharing the first color filter RP. The grid pattern150may define light receiving areas S21to S29of the second merged pixel P21to P29.

In some embodiments, the light receiving areas of at least some of the unit pixels UP included in the second merged pixel P21to P29may decrease as the unit pixels are closer to the edge of the first color filter RP. For example, the second merged pixel P21to P29may include a second central pixel P25and a plurality of second peripheral pixels P21to P24and P26to P29. The second peripheral pixels P21to P24and P26to P29may surround the second central pixel P25in plan view. In this case, each of the light receiving areas S21to S24and S26to S29of the second peripheral pixels P21to P24and P26to P29may be smaller than the light receiving area S25of the second central pixel P25.

In some embodiments, the light receiving areas of at least some of the unit pixels UP may decrease as the unit pixels are farther away from the center CP of the light receiving region APS. For example, the light receiving areas S21and S27of the pixels P21and P27may be smaller than the light receiving areas S11and S17of the pixels P11and P17. For example, a width W21of the grid pattern150defining the light receiving area S21on the left surface of the pixel P21may be greater than the width W11of the grid pattern150defining the light receiving area S11on the left surface of the pixel P11. For example, the light receiving areas S22and S28of the pixels P22and P28may be smaller than the light receiving areas S12and S18of the pixels P12and P18. As an example, a width W22of the grid pattern150defining the light receiving area S22on the left surface of the pixel P22may be greater than the width W12of the grid pattern150defining the light receiving area S12on the left surface of the pixel P12.

In some embodiments, the width W22of the grid pattern150defining the light receiving area S22on the left surface of the pixel P22may be smaller than the width W21of the grid pattern150defining the light receiving area S21on the left surface of the pixel P21, and may be greater than a width W23of the grid pattern150defining the light receiving area S23on the left surface of the pixel P23.

FIGS.17to19are various example partial layout diagrams illustrating the first to third regions ofFIG.12. For simplicity of description, redundant parts of the description made with reference toFIGS.1to16may be recapitulated or omitted.

Referring toFIGS.12and17to19, in the image sensor according to some embodiments, the third region III spaced apart diagonally from the first region I includes a third merged pixel P31to P39that shares one of the plurality of color filters170.

As an example, the third region III may include the third merged pixel P31to P39that shares the first color filter RP. The grid pattern150may define light receiving areas S31to S39of the third merged pixel P31to P39.

Referring toFIGS.12and17, in the image sensor according to some embodiments, the first merged pixel P11to P19, the second merged pixel P21to P29, and the third merged pixel P31to P39may be arranged in the same shape.

For example, the light receiving areas S31, S33, S37, and S39of the pixels P31, P33, P37, and P39may be the same as the light receiving areas S11and S21of the pixels P11and P21. The light receiving areas S32, S34, S36, and S38of the pixels P32, P34, P36, and P38may be the same as the light receiving areas S12and S22of the pixels P12and P22. The light receiving area S35of the pixel P35may be the same as the light receiving areas S15and S25of the pixels P15and P25.

Referring toFIGS.12and18, in the image sensor according to some embodiments, the light receiving areas of at least some of the unit pixels UP may decrease as the unit pixels are farther away from the center CP of the light receiving region APS.

For example, since both the second region II and the third region III may be spaced apart from the first region I in the first direction X, the light receiving areas S21, S27, S31, and S37of the pixels P21, P27, P31and P37may be smaller than the light receiving areas S11and S17of the pixels P11and P17. In addition, since the second region II may be spaced apart from the third region III in the second direction Y, the light receiving areas S31and S33of the pixels31and33may be smaller than the light receiving areas S21and S23of the pixels P21and P23.

Referring toFIGS.12and19, in the image sensor according to some embodiments, the light receiving areas of at least some of the peripheral pixels may increase as the peripheral pixels are farther away from the center CP of the light receiving region APS.

For example, the light receiving areas S22and S28of the pixels P22and P28may be greater than the light receiving areas S12and S18of the pixels P12and P18. Further, the light receiving areas S36and S38of the pixels P36and P38may be greater than the light receiving areas S16and S18of the pixels P16and P18.

FIG.20is a schematic layout diagram of a light receiving region in an image sensor according to some embodiments.FIG.21is an example partial layout diagram illustrating a first region and a second region ofFIG.20. For simplicity of description, redundant parts of the description made with reference toFIGS.1to19may be recapitulated or omitted.

Referring toFIG.20, in the image sensor according to some embodiments, sixteen unit pixels UP arranged in 4×4 array may share one of the first color filter RP, the second color filter GP, and the third color filter BP.

Referring toFIGS.20and21, in the image sensor according to some embodiments, the first region I includes a first merged pixel P11to P116that shares one of the plurality of color filters170, and the second region II includes a second merged pixel P21to P216that shares one of the plurality of color filters170.

As an example, the first region I may include the first merged pixel P11to P116sharing the first color filter RP, and the second region II may include the second merged pixel P21to P216sharing the first color filter RP. The grid pattern150may define light receiving areas S11to S116of the first merged pixel P11to P116and light receiving areas S21to S216of the second merged pixel P21to P216.

In some embodiments, the light receiving areas of at least some of the unit pixels UP may decrease as the unit pixels are farther away from the center CP of the light receiving region APS. In some embodiments, the light receiving areas of at least some of the unit pixels UP included in the second merged pixel P21to P216may decrease as the unit pixels are closer to the center CP of the light receiving region APS. For example, the light receiving areas S21, S25, S29, and S213of the pixels P21, P25, P29, and P213may be smaller than the light receiving areas S11, S15, S19, and S113of the pixels P11, P15, P19, and P113. As an example, a width W21of the grid pattern150defining the light receiving areas S21, S25, S29, and S213on the left surfaces of the pixels P21, P25, P29, and P213may be greater than a width W11of the grid pattern150defining the light receiving areas S11, S15, S19, S113on the left surfaces of the pixels P11, P15, P19, and P113.

FIG.22is a schematic layout diagram explaining an image sensor according to some embodiments.FIG.23is a schematic cross-sectional view illustrating an image sensor according to some embodiments. For simplicity of description, redundant parts of the description made with reference toFIGS.1to6may be recapitulated or omitted.

Referring toFIGS.22and23, the image sensor according to some embodiments may include a sensor array region SAR, a connection region CR, and a pad region PR.

The sensor array region SAR may include an area corresponding to the APS10shown inFIG.1. For example, in the sensor array region SAR, a plurality of unit pixels (e.g., UP inFIG.3) may be arranged two-dimensionally (e.g., in a matrix form).

The sensor array region SAR may include a light receiving region APS and a light blocking region OB. Active pixels that receive light to generate active signals may be arranged in the light receiving region APS. Optical black pixels that generate optical black signals by blocking light may be arranged in the light blocking region OB. The light blocking region OB may be formed, for example, along the periphery of the light receiving region APS, but this is merely an example.

In some embodiments, the photoelectric conversion layer112may not be formed in a part of the light blocking region OB. For example, the photoelectric conversion layer112may be formed in the first substrate110in the light blocking region OB adjacent to the light receiving region APS, but may not be formed in the first substrate110in the light blocking region OB spaced apart or farther way from the light receiving region APS. In some embodiments, dummy pixels may be formed in the light receiving region APS adjacent to the light blocking region OB.

The connection region CR may be formed around the sensor array region SAR. The connection region CR may be formed on one side of the sensor array region SAR, but this is merely example. Wires are formed in the connection region CR, and may be configured to transmit and receive electrical signals of the sensor array region SAR.

The pad region PR may be formed around the sensor array region SAR. The pad region PR may be formed adjacent to the edge of the image sensor according to some embodiments, but this is merely an example. The pad region PR may be connected to an external device or the like to allow the image sensor according to some embodiments to transmit and receive electrical signals to and from the external device.

The connection region CR is shown to be interposed between the sensor array region SAR and the pad region PR, but this is merely an example. The arrangement of the sensor array region SAR, the connection region CR, and the pad region PR may vary depending on the requirement.

In some embodiments, the first wiring structure IS1may include the first wire132in the sensor array region SAR and a second wire134in the connection region CR. The first wire132may be electrically connected to the unit pixels (e.g., UP ofFIG.3) of the sensor array region SAR. For example, the first wire132may be connected to the first electronic element TR1. At least a part of the second wire134may be electrically connected to at least a part of the first wire132. For example, at least a part of the second wire134may extend from the sensor array region SAR. Accordingly, the second wire134may be electrically connected to the unit pixels (e.g., UP ofFIG.3) of the sensor array region SAR.

The image sensor according to some embodiments may further include a second substrate210, a second wiring structure IS2, a first connection structure350, a second connection structure450, a third connection structure550, an element isolation pattern115, a light blocking filter270C, and a third passivation layer380.

The second substrate210may be a bulk silicon or silicon-on-insulator (SOI) substrate. The second substrate210may be a silicon substrate, or may include other materials such as silicon germanium, indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Alternatively, the second substrate210may have an epitaxial layer formed on a base substrate.

The second substrate210may include a third surface210aand a fourth surface210bopposite to each other. In some embodiments, the third surface210aof the second substrate210may face the second surface110bof the first substrate110.

In some embodiments, a second electronic element TR2may be formed on the third surface210aof the second substrate210. The second electronic element TR2may be electrically connected to the sensor array region SAR, and may transmit and receive an electrical signal to and from each of the unit pixels (e.g., UP ofFIG.3) of the sensor array region SAR. For example, the second electronic element TR2may include electronic elements constituting the row decoder20, the row driver30, the column decoder40, the timing generator50, the CDS60, the ADC70, or the input/output buffer80shown inFIG.1.

The second wiring structure IS2may be formed on the third surface210aof the second substrate210. The second wiring structure IS2may be attached to the first wiring structure IS1. For example, as shown inFIG.23, the top surface of the second wiring structure IS2may be attached to the bottom surface of the first wiring structure IS1.

The second wiring structure IS2may include one or a plurality of wires. For example, the second wiring structure IS2may include a second inter-wire insulating layer230and a plurality of wires232,234, and236in the second inter-wire insulating layer230. InFIG.23, the number of layers and arrangements of wires constituting the second wiring structure IS2are merely examples, and are not limited thereto.

At least some of the wires232,234, and236of the second wiring structure IS2may be connected to the second electronic element TR2. In some embodiments, the second wiring structure IS2may include a third wire232in the sensor array region SAR, a fourth wire234in the connection region CR, and a fifth wire236in the pad region PR. In some embodiments, the fourth wire234may be an uppermost wire among a plurality of wires in the connection region CR, and the fifth wire236may be an uppermost wire among a plurality of wires in the pad region PR.

The first connection structure350may be formed in the light blocking region OB. The first connection structure350may be formed on the surface insulating layer140of the light blocking region OB. In some embodiments, the first connection structure350may be in contact with the pixel isolation pattern120. For example, a first trench355texposing the pixel isolation pattern120may be formed in the first substrate110and the surface insulating layer140in the light blocking region OB. The first connection structure350may be formed in the first trench355tto be in contact with the pixel isolation pattern120in the light blocking region OB. In some embodiments, the first connection structure350may extend along the profiles of the side and bottom surfaces of the first trench355t.

In some embodiments, the first connection structure350may be electrically connected to the conductive filling pattern122to apply a ground voltage or a negative voltage to the conductive filling pattern122. Accordingly, the electric charges generated by ESD or the like may be discharged to the first connection structure350through the conductive filling pattern122, and the ESD bruise defect may be effectively prevented.

The second connection structure450may be formed in the connection region CR. The second connection structure450may be formed on the surface insulating layer140in the connection region CR. The second connection structure450may electrically connect the first substrate110to the second substrate210. For example, a second trench455texposing the second wire134and the fourth wire234may be formed in the first substrate110, the first wiring structure IS1, and the second wiring structure IS2in the connection region CR. The second connection structure450may be formed in the second trench455tto connect the second wire134to the fourth wire234. In some embodiments, the second connection structure450may extend along the profiles of the side and bottom surfaces of the second trench455t.

The third connection structure550may be formed in the pad region PR. The third connection structure550may be formed on the surface insulating layer140in the pad region PR. The third connection structure550may electrically connect the second substrate210to an external device or the like.

For example, a third trench550texposing the fifth wire236may be formed in the first substrate110, the first wiring structure IS1, and the second wiring structure IS2in the pad region PR. The third connection structure550may be formed in the third trench550tto be in contact with the fifth wire236. In addition, a fourth trench555tmay be formed in the first substrate110in the pad region PR. The third connection structure550may be formed in the fourth trench555tand be exposed. In some embodiments, the third connection structure550may extend along the profiles of the side and bottom surfaces of the third trench550tand the fourth trench555t.

Each of the first connection structure350, the second connection structure450, and the third connection structure550may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), aluminum (Al), copper (Cu), or a combination thereof, but is not limited thereto. In some embodiments, the first connection structure350, the second connection structure450, and the third connection structure550may be formed at the same level. The term “the same level” as used herein means being formed by the same manufacturing process.

In some embodiments, a first pad355filling the first trench355tmay be formed on the first connection structure350. In some embodiments, a second pad555filling the fourth trench555tmay be formed on the third connection structure550. Each of the first pad355and the second pad555may include, for example, at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), or an alloy thereof, but is not limited thereto. In some embodiments, the first pad355and the second pad555may be formed at the same level.

In some embodiments, a first filling insulating layer460filling the second trench455tmay be formed on the second connection structure450. In some embodiments, a second filling insulating layer560filling the third trench550tmay be formed on the third connection structure550. Each of the first filling insulating layer460and the second filling insulating layer560may include, for example, at least one of silicon oxide, aluminum oxide, tantalum oxide, or a combination thereof, but is not limited thereto. In some embodiments, the first filling insulating layer460and the second filling insulating layer560may be formed at the same level.

In some embodiments, the first passivation layer160may cover the first connection structure350, the first pad355, the second connection structure450, and the third connection structure550. For example, the first passivation layer160may extend conformally along the profiles of the first connection structure350, the first pad355, the second connection structure450, and the third connection structure550as shown, e.g., inFIG.23. In some embodiments, the first passivation layer160may expose the second pad555.

The element isolation pattern115may be formed in the first substrate110. For example, an element isolation trench115tmay be formed in the first substrate110. The element isolation pattern115may be formed in the element isolation trench115t. In some embodiments, the element isolation pattern115may extend from the first surface110aof the first substrate110into the first substrate110. In some embodiments, the element isolation pattern115may be spaced apart from the second surface110bof the first substrate110.

InFIG.23, it is shown that the element isolation pattern115is formed only around the second connection structure450in the connection region CR and around the third connection structure550in the pad region PR, but this is merely an example. For example, the element isolation pattern115may also be formed around the first connection structure350in the light blocking region OB.

The element isolation pattern115may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, or a combination thereof, but is not limited thereto. In some embodiments, the element isolation pattern115may be formed at the same level as the surface insulating layer140.

The light blocking filter270C may cover at least a part of the light blocking region OB. For example, the light blocking filter270C may be formed on the first connection structure350and the second connection structure450. The light blocking filter270C may include, for example, a blue filter, but is not limited thereto.

The third passivation layer380may be formed on the light blocking filter270C. For example, the third passivation layer380may be formed to cover a part of the first passivation layer160in the light blocking region OB, the connection region CR, and the pad region PR. In some embodiments, the second passivation layer185may extend along the surface of the third passivation layer380. The third passivation layer380may include, for example, a light transmitting resin, but is not limited thereto. In some embodiments, the third passivation layer380may include the same material as that of the microlens180.

In some embodiments, the second passivation layer185and the third passivation layer380may expose the second pad555. For example, an exposure opening ER that exposes the second pad555may be formed in the second passivation layer185and the third passivation layer380. Accordingly, the second pad555may be connected to the external device or the like to allow the image sensor according to some embodiments to transmit and receive electrical signals to and from the external device. That is, the second pad555may be an input/output pad of the image sensor according to some embodiments.

In concluding the detailed description, those skilled in the art will appreciate that many variations and modifications may be made to embodiments without substantially departing from the principles of the disclosure. Therefore, embodiments of the disclosure are used in a generic and descriptive sense only and not for purposes of limitation.