Patent ID: 12232263

DETAILED DESCRIPTION OF ILLUSTRATED EMBODIMENTS

The illustrations in the drawings are schematically presented. In different drawings, similar or identical elements are provided with the same reference signs.

Before, referring to the drawings, exemplary embodiments will be described in further detail, some basic considerations will be summarized based on which exemplary embodiments of the invention have been developed.

In conventional approaches of connecting two component carriers by an electrically conductive paste in a recess of a prepreg sheet, prepreg and paste are cured simultaneously. This however applies significant stress to the paste because of a pronounced shrinkage of the prepreg during curing. This high stress creates voids and defects in the paste and may result in product failure or breakage. Hence, the described conventional concept of creating a vertical interconnection may involve processability issues and alignment problems. In order to keep misalignment at an acceptable level, large pads need to be provided which contravenes to a desired miniaturization. A correspondingly manufactured electronic device may suffer from reliability limitations.

Thus, many conventional defects are related to the high resin amount flowing around the paste which may be a source of instability. More resin implies more shrinkage stress exerted to the metallic paste which may result in breakage, voids, and slipping. Furthermore, different scale values between the two component carriers may lead to high shear stress on the metallic paste interfaces, which may further increase the tendency of slipping and delamination. Such conventional approaches allow only a low miniaturization level as a corresponding manufacturing process setup cannot compensate the scaling mismatch between the component carriers to be connected. Thus, a big pad size of 500 μm and a minimum diameter of the metallic paste of 240 μm are consequences. The high amount of the metallic paste can also impact the electrical and thermal resistance compared to copper layers.

In view of the foregoing conventional shortcomings, it may be desired to improve metallic paste-based electronic devices for increasing reliability by eliminating slipping, delamination, metallic paste breakage and voids. Increasing the miniaturization level (in particular to achieve a smaller pad size and pitch) may be desired as well. Furthermore, it may be desired to decrease the yield loss due to scaling mismatch. Moreover, a reliability improvement may be desired. In particular, it may be desired to decrease the stress levels on the paste by lowering the amount of prepreg resin for obtaining a lower shrinkage and more stability. It may also be advantageous to add a stiffener in the bonding layer (for example fully cured FR4). Advantageously, the scaling mismatch between the component carriers to be connected may be at least partially compensated. It may be further desired to decrease the amount of the bonding paste used.

Miniaturization may be promoted by a decrease of the pad size by decreasing the metal paste via diameter from conventionally 200 μm to 70 μm to 100 μm. It may further be desired to compensate the scaling mismatch by an incremental approach (for instance implementing one or more intermediate layers).

According to an exemplary embodiment of the invention, a first component carrier and a second component carrier may be mechanically and electrically interconnected using an intermediate structure with a dielectric matrix and three or more stacked, staggered or laterally displaced vertical interconnect elements therein and/or thereon. Such a manufacturing architecture may reduce the amount of prepreg and thus the amount of stress acting on the electrically conductive vertical interconnect elements during curing of the prepreg. Less amount of prepreg means less stress and thus less artefacts and defects. In particular, the dielectric matrix of the intermediate structure may comprise a central stiffener (such as a fully cured core of FR4) which does not participate at curing and thereby does not experience shrinkage during establishing a connection between the component carriers. Apart from this, a core stiffener may increase the stability of the electronic device as a whole. Furthermore, the provision of three or more staggered vertical interconnect elements introduces additional degrees of freedom usable by a designer for reducing scaling mismatch and also reducing stress. The described manufacturing architecture also allows to reduce the amount of bonding paste needed and to increase the amount of dense copper, so that the electrical resistance of the vertical interconnect can be kept small. This results in a low loss of signal quality and electric energy during operation of the electronic device. Moreover, the diameter of an individual via may be reduced, for instance from conventionally 200 μm to a value in the range from 70 μm to 100 μm.

According to an exemplary embodiment of the invention, an electrically conductive vertical connection structure for electrically coupling two component carriers in a vertical direction may be provided which involves at least three staggered vertical interconnect elements in an intermediate structure between the component carriers. Such a manufacturing architecture increases the flexibility in terms of design, allows to obtain a high-frequency performance, supports a hybrid build-up and enables a high degree of miniaturization and modularization. At the same time, exemplary embodiments of the invention may overcome conventional limitations in terms of reliability issues resulting from a high amount of metal paste in a high amount of prepreg material causing excessive stress due to a pronounced curing shrinkage mismatch between prepreg (usually larger shrinkage) and metal paste (usually smaller shrinkage). In particular, exemplary embodiments of the invention provide a manufacturing concept which is executable on industrial scale, enables a high design flexibility, allows miniaturization and improved registration and involves only a small effort. By introducing an intermediate core between the component carriers, a decrease of the aspect ratio, a compensation of mismatching scale values and a reduction of the amount of electrically conductive paste and prepreg needed may be achieved. Such an intermediate core may provide additional stability and reliability to the build-up.

In particular, an exemplary embodiment of the invention may use two thin prepreg layers between a central cured core together with three (or more) staggered vertical interconnect elements rather than a single thick prepreg layer traversed by high amount of metallic paste. This reduces the manufacturing effort while compensating scaling mismatch between the component carriers to be assembled. More specifically, introducing a core stiffener between two thin prepreg sheets may allow to increase stability and stiffness, may reduce the amount of metallic paste needed, and may make it possible to expose both sides of the core with different scale values to compensate mismatch. For example, the scale values for each side can be loaded for exposing files of the individual component carriers. For example, the two sides of the core can be connected by laser vias or by plated through holes depending on a desired miniaturization level. Metallic paste for each component carrier can be directly aligned on the related component carrier through the respective prepreg sheet (which may be at least partially transparent). Using such a manufacturing concept, the pads may be smaller than in conventional approaches. For high flexibility, the laser connection can be smaller to ensure the scaling mismatch compensation. In an embodiment, it is also possible to use a photoimageable dielectric (PID) instead of a prepreg sheet.

In an embodiment (and also referring to the preceding paragraph), the method comprises, before the connecting, storing position and dimension information concerning a connection pad of the first component carrier and a connection pad of the second component carrier, wherein each of the connection pads is to be connected to a respective one of the at least three staggered electrically conductive vertical interconnect elements, and using the stored information for forming at least one of the at least three staggered electrically conductive vertical interconnect elements. More specifically, the described embodiment may allow for an individualized panel production and for process automation. For example, the surfaces of the two stacks to be connected may be structured before assembling (for instance before combining the two stacks with a stiffener). Thereby, the location and the dimensions of the connection pads may be saved in a log-file, which may be used during the next process stage(s), for example during structuring the stiffener. By using the log-file, the manufacturing machine knows exactly where the connecting pad(s) of the stiffener should appear, and which dimension the pad should have. For example, the machine can access the log-file using a barcode, which can be found on each stack, for instance having a construction manual included. Highly advantageously, this enables to execute an individualized panel production.

Exemplary applications of exemplary embodiments of the invention are component carrier-based electronic devices with high layer count, electronic devices with hybrid build-up, thick boards, high-frequency boards (for example for 5G applications), boards with one or more embedded components, boards for aerospace applications, etc.

An electronic device according to an exemplary embodiment of the invention may increases the reliability and the miniaturization level without any impact on the dielectric thickness or build-up design. Advantageously, the manufacturing architecture according to an exemplary embodiment of the invention may allow incremental processing with the possibility to compensate scaling mismatches. Furthermore, it may be possible to split and/or reduce the amount of metallic paste to achieve more stability, more stiffness, lower resistance and lower effort. It may also be possible to reduce the resin amount which may also contribute to more stability, more stiffness, and a stable process. Exemplary embodiments of the invention are also compatible with smaller pads compared to conventional approaches, so that the pad dimensions can be reduced for example from 500 μm to below 250 μm. Also, a pitch reduction by for instance 50% may become possible.

Descriptively speaking, an intermediate structure according to an exemplary embodiment of the invention may break the dielectric in three parts and does not add any additional complexity to the main build-up. The effort in terms of metallic paste may be reduced, since a lower amount may be sufficient, and a higher yield value may be achieved.

Advantageously, prepreg has to fill only less areas according to an exemplary embodiment of the invention, and copper on the core may be thinner. Apart from this, more stability may be obtained during final curing and a proper thickness control may be achieved. For high copper thicknesses, thicker prepregs can be used, if desired. It is also possible that prepregs are substituted by resin sheets. A laser may be perfectly aligned to each component carrier. By reducing the amount of metal paste, a lower resistance, less effort, high stability and a simplified manufacturing process may become possible. Furthermore, exemplary embodiments of the invention may offer the possibility for low aspect ratios (for instance by using alternative filling processes). Beyond this, there is the possibility to scale the two sides of the core with different scale values to compensate the scaling mismatches between the opposing component carriers. Beyond this, there may be a high miniaturization level on the component carriers, for instance from 500 μm pad size conventionally to 250 μm or less according to exemplary embodiments of the invention. For instance, a 250 μm pad and a 70 μm laser via can compensate a maximum shift between the component carriers of 540 μm. Advantageously, a shift compensation can be done automatically in order to manufacture the stiffener by using log-files, as explained above.

In an embodiment, it is also possible to use a copper pillar instead of conductive paste. This may offer more reliability and less electrical resistance. Using copper pillars and die bonding process may provide more reliable interfaces. In an embodiment, a photoimageable dielectric (PID) may be used to plate the copper pillars.

Furthermore, it may be possible to implement a compression bonding process to assemble or press the component carriers to be connected.

FIG.1illustrates a cross-sectional view of an electronic device100according to an exemplary embodiment of the invention.

The three main constituents of the electronic device100are a first component carrier102, a second component carrier110, and an intermediate structure118being mechanically and electrically connected in between.

As shown in a detail150inFIG.1, the first component carrier102comprises a first laminated layer stack104which comprises a plurality of first electrically conductive layer structures106and a plurality of first electrically insulating layer structures108. In the illustrated embodiment, the first component carrier102is embodied as laminate-type plate-shaped component carrier, in particular as printed circuit board (PCB).

Now referring to a detail152inFIG.1, the second component carrier110comprises a second laminated layer stack112which comprises a plurality of second electrically conductive layer structures114and a plurality of second electrically insulating layer structures116. In the shown embodiment, the second component carrier110is embodied as further laminate-type plate-shaped component carrier, in particular as printed circuit board (PCB).

As already mentioned, the laminated layer stacks104,112are composed of electrically conductive layer structures106,114and electrically insulating layer structures108,116. For example, the electrically conductive layer structures106,114may comprise patterned copper foils (and optionally one or more vertical through connections, for example copper filled laser vias). The electrically insulating layer structures108,116may comprise a resin (such as epoxy resin), optionally comprising reinforcing particles therein (for instance glass fibers or glass spheres). For instance, the electrically insulating layer structures108,116may be made of prepreg or FR4. The layer structures106,108may be connected by lamination, i.e., the application of pressure and/or heat. Correspondingly, the layer structures114,116may be connected by lamination, i.e., the application of pressure and/or heat.

As shown inFIG.1as well, sheet-shaped or plate-shaped intermediate structure118is connected between the first component carrier102and the second component carrier110. The intermediate structure118comprises an electrically conductive portion and an electrically insulating portion. The electrically conductive portion comprises three electrically conductive and mutually coupled vertically stacked and horizontally displaced or staggered vertical interconnect elements120,122,124. Thus, the (here exactly) three staggered vertical interconnect elements120,122,124are laterally displaced with respect to each other. In the illustrated embodiment, the vertical interconnect elements120,122,124are directly electrically conductively connected with each other. As shown, the lowermost vertical interconnect element120is electrically connected with an exposed connection pad138of the first component carrier102. Moreover, the uppermost vertical interconnect element124is electrically connected with an exposed connection pad140of the second component carrier110. The central vertical interconnect element122bridges the spatial displacement between the lowermost interconnect element120and the uppermost interconnect element124of the intermediate structure118. Thus, the staggered interconnect elements120,122,124are directly electrically connected between the connection pad138of the first component carrier102and the connection pad140of the second component carrier110for electrically coupling the first component carrier102with the second component carrier110. Consequently, an electric signal may propagate substantially vertically between the component carriers102,110through the staggered interconnect elements120,122,124.

For instance, one or more of the vertical interconnect elements120,122,124may comprise a cured metal paste, for instance a cured silver paste and/or a cured copper paste. However, at least one of the vertical interconnect elements120,124may also be embodied as inlay-type metal pillar or metal-plated via.

As shown as well inFIG.1, the three staggered vertical interconnect elements120,122,124are embedded in a dielectric sheet154of the intermediate structure118. For instance, dielectric sheet154may be laminated on its top side and on its bottom side to the respective component carrier102,110. Thus, the intermediate structure118not only electrically couples the component carriers102,110, but also connects them mechanically. The dielectric sheet154may be made of a single homogeneous electrically insulating material, or may be made preferably of different electrically insulating materials, sub-sheets or layers (for instance as shown inFIG.4).

Within the intermediate structure118, an electric signal may propagate substantially vertically and thus along a short path. This keeps signal losses and energy losses small. Since the intermediate structure118is free of a redistribution structure, i.e., provides no electric fan-out function, the intermediate structure118may be constructed in a simple way and does not lengthen the signal propagation path. More specifically, the signal path between the connection pads138,140does not extend along horizontal traces in the intermediate structure118. In fact, intermediate structure118may be free of such horizontal traces. The short electric path through the intermediate structure118is promoted by the fact that the three laterally displaced, stacked and staggered vertical interconnect elements120,122,124laterally overlap with each other in a common overlapping range164, in a viewing direction corresponding to the vertical direction according toFIG.1, as indicated by reference sign162.

Moreover, the staggering design of the interconnect elements120,122,124allows to compensate a lateral offset between the connection pads138,140of the component carriers102,110to be electrically coupled.

FIG.2illustrates a cross-sectional view of an electronic device100according to another exemplary embodiment of the invention.

The embodiment ofFIG.2differs from the embodiment ofFIG.1in that, in the embodiment according toFIG.2, the staggering direction of the interconnect elements120,122,124—from bottom to top—is from left to right rather than from right to left (as inFIG.1). This demonstrates that the manufacturing architecture of embodiments of the invention can highly flexibly compensate any kind of offsets and misalignments between connection pads138,140of the component carriers102,110, regardless of the direction of the offset or misalignment.

FIG.3illustrates a cross-sectional view of an electronic device100according to still another exemplary embodiment of the invention.

The embodiment ofFIG.3differs from the embodiment ofFIG.2in that, in the embodiment according toFIG.3, the amount of misalignment between the connection pads138,140of the component carriers102,110is smaller. This can be addressed by a horizontal positional adjustment of the interconnect elements120,122,124relatively to each other.

In each of the embodiments ofFIG.1toFIG.3, the central interconnect element122has a larger lateral (i.e., horizontal) extension than the lowermost interconnect element120and the uppermost interconnect element124. This enables an extension of the spatial range of compensable misalignments between the connection pads138,140of the component carriers102,110without compromising on the compactness of the electronic device100.

FIG.4shows a cross-sectional view of a structure obtained during carrying out a method of manufacturing an electronic device100according to an exemplary embodiment of the invention.FIG.5shows a cross-sectional view of an electronic device100according to an exemplary embodiment of the invention obtained by carrying out the method according toFIG.4.

For manufacturing the electronic device100, first component carrier102is provided, which can be embodied as described referring toFIG.1. Moreover, second component carrier110is provided, which can be embodied as well as described referring toFIG.1.

Furthermore, intermediate structure118having a central stiffener126is arranged vertically between the first component carrier102and the second component carrier110. A through hole is formed in central stiffener126and is filled with central vertical interconnect element122, such as a copper-plated or metal paste-filled laser via. A respective horizontally extending interconnect pad136is formed at each of the upper end and the lower end of central vertical interconnect element122.

According toFIG.4, a first connection layer128of the intermediate structure118is connected at a main surface of the first component carrier102at which connection pad138is located. The first connection layer128is patterned so as to have a through hole at which the connection pad138is exposed. In said through hole, lower vertical interconnect element120is accommodated so as to be electrically coupled to the connection pad138.

Correspondingly, a second connection layer130of the intermediate structure118is connected at a main surface of the second component carrier110at which connection pad140is located. The second connection layer130is patterned so as to have a through hole at which the connection pad140is exposed. In this through hole, upper vertical interconnect element124is accommodated so as to be electrically coupled to the connection pad140.

Thereafter, the central stiffener126of the intermediate structure118is connected with the first component carrier102(prepared as described) and the second component carrier110(prepared as described), for instance by thermal compression bonding. More specifically, this establishes a mechanical connection between the dielectric central stiffener126and the dielectric connection layers128,130. Simultaneously, this connection establishes an electrically conductive connection from the electrically conductive layer structures106of the first component carrier102, via connection pad138, via the lowermost vertical interconnect element120, via the lower interconnect pad136, via the central vertical interconnect element122, via the upper interconnect pad136, via the uppermost vertical interconnect element124, up to connection pad140, and from there to the electrically conductive layer structures114of the second component carrier110.

For example, the central vertical interconnect element122is a metal-filled via, which may for instance be filled with plated metal or with a metal paste. The upper and the lower vertical interconnect elements120,124may for instance be embodied as metal pillar.

As illustrated in a detail156ofFIG.4, the stiffener126may comprise a network of interconnected reinforcing particles132, here embodied as glass fibers132, in a matrix of resin158(for instance epoxy resin). For example, the stiffener126may be a fully cured core of FR4 material. However, the stiffener126may have a very low thickness d1of for instance 40 μm to 50 μm. This is enough to sufficiently stiffen the electronic device100in its central region and may simultaneously keep the electronic device100compact. Furthermore, stiffener126may be already fully cured before connection, i.e., in the state ofFIG.4, so that dielectric material of the stiffener126does not experience a curing-related shrinkage during connection, which would introduce stress in the electronic device100.

Each of the first connection layer128and the second connection layer130may be free of reinforcing glass particles and may for instance be a pure resin. Advantageously, each of the first connection layer128and the second connection layer130may have a very small thickness d2, d3, for instance in a range from 20 μm to 30 μm. The resin of the connection layers128,130may be still uncured prior to the connection, i.e., in the state according toFIG.4. Thus, the thermal compression bonding may trigger cross-linking or polymerization of the resin of the connection layers128,130so that an adhesive connection can be formed between the connection layers128,130and the material at both of their main surfaces. The resin of the connection layers128,130may be cured at least partially during the connection. Due to their very small thickness d2, d3, the resin of the connection layers128,130may experience curing-related shrinkage only to a small extent, so that the shrinkage-caused stress can remain acceptably small.

As in the previously described embodiments, the vertical interconnect elements120,122,124may compensate a lateral shift between the first connection pad138and the second connection pad140. Each of the interconnect pads136, the first connection pad138, and the second connection pad140may have a relatively small lateral extension L of less than 250 μm. This promotes miniaturization and ensures at the same time misalignment compensation over a sufficiently large spatial range.

The upper one and the lower one of the three staggered vertical interconnect elements120,122,124are laterally displaced by a lateral distance (see “B” inFIG.6) of preferably at least 200 μm. However, the three staggered vertical interconnect elements120,122,124may have a relatively small diameter D which is preferably in a range from 70 μm to 100 μm.

In the described embodiment, it may thus be possible to connect the flexible and curable resin or prepreg sheets in form of the connection layers128,130to the component carriers102,110prior to the interconnection (compareFIG.4). This may be particularly preferred, since this contributes to a flattening of the printed circuit boards. As an alternative to pure resin or prepreg, ABF material may be used as well. As a further alternative, the connection layers128,130may also be made of a photoimageable dielectric (PID).

The interconnect pads136,136may compensate a different scaling on the front side and the back side of the stiffener126. The connection layers128,130may have a very small thickness d2, d3of preferably 20 μm to 30 μm for miniaturization and to suppress stress-related defects. Also, the stiff core120may have a small thickness d1of for example 40 μm to 50 μm to keep the electronic device100compact. Holes in the connection layers128,130which serve for exposing the connection pads138,140may be formed by laser drilling, mechanically drilling or etching and may be filled with metallic paste or another electrically conductive element such as a copper pillar.

FIG.6shows details of an intermediate structure118of an electronic device100according to an exemplary embodiment of the invention. As can be taken fromFIG.6, each of the interconnect elements120,122,124has a respective central axis160which is laterally displaced with respect to each other central axis160of each of the respectively other two vertical interconnect elements120,122,124. By this configuration, even a large scaling mismatch can be compensated by the interconnect elements120,122,124.

FIG.7shows a cross-sectional view of a structure obtained during carrying out a method of manufacturing an electronic device100according to another exemplary embodiment of the invention.FIG.8shows a cross-sectional view of an electronic device100according to an exemplary embodiment of the invention obtained by carrying out the method according toFIG.7.

The method described referring toFIG.7differs from the method described referring toFIG.4in particular in that, according to the embodiment ofFIG.7, a separate (i.e., not yet attached) and recessed (see through hole166) first connection layer128is arranged between the first component carrier102(with upwardly protruding vertical interconnect element120on connection pad138) and a central stiffener126with central vertical interconnect element122and interconnect pads136,136. Furthermore, a separate (i.e., not yet attached) and recessed (see through hole168) second connection layer130is arranged between the second component carrier110(with downwardly protruding vertical interconnect element124on connection pad140) and the central stiffener126.

Thereafter, the intermediate structure118(in the shown embodiment composed of the three still separate constituents in form of the first connection layer128, the central stiffener126, and the second connection layer130) is connected with the first component carrier102on the bottom side, and with the second component carrier110on the top side.

FIG.9shows a cross-sectional view of a structure obtained during carrying out a method of manufacturing an electronic device100according to still another exemplary embodiment of the invention.FIG.10shows a cross-sectional view of an electronic device100according to an exemplary embodiment of the invention obtained by carrying out the method according toFIG.9.

The method described referring toFIG.9differs from the method described referring toFIG.4in particular in that, according to the embodiment ofFIG.9, the connection layers128,130are embodied as photoimageable dielectric (PID). Said photoimageable dielectric may be used to plate the copper pillars form the lowermost and uppermost vertical interconnect elements120,124according toFIG.9andFIG.10. Compression bonding may be used to assemble or press.

FIG.11shows a cross-sectional view of a structure obtained during carrying out a method of manufacturing an electronic device100according to yet another exemplary embodiment of the invention.

The method described referring toFIG.11differs from the method described referring toFIG.4in particular in that, according to the embodiment ofFIG.11, the still uncured connection layers128,130are attached to the central stiffener126(rather than to the component carriers102,110) prior to the connection of the constituents of the electronic device100. More specifically, the intermediate structure118according toFIG.11is formed with central stiffener126, first connection layer128connected on a first main surface of the stiffener126, and second connection layer130connected on a second main surface of the stiffener126between the still separate first component carrier102and the still separate second component carrier110. Thereafter, the pre-assembled intermediate structure118may be connected with the first component carrier102and the second component carrier110(not shown).

In the embodiment according toFIG.11, the prepreg sheets are thus connected to the core rather than to the component carriers102,110prior to the interconnection.

Vertical interconnect elements120,124may be embodied as copper pillars according toFIG.11. The use of copper pillars instead of electrically conductive paste may offer more reliability and lower electrical resistance. Furthermore, the use of copper pillars and a die bonding process provides more reliable interfaces.

It should be noted that the term “comprising” does not exclude other elements or steps and the article “a” or “an” does not exclude a plurality. Also, elements described in association with different embodiments may be combined.

Implementation of the invention is not limited to the preferred embodiments shown in the figures and described above. Instead, a multiplicity of variants is possible which use the solutions shown and the principle according to the invention even in the case of fundamentally different embodiments.