Patent ID: 12237854

DETAILED DESCRIPTION

The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Embodiments of the disclosure relate to circuit and method for inter-symbol and intra-symbol voltage modulation. Herein, a transceiver circuit is configured to determine a voltage target(s) and provide the voltage target(s) to a power management integrated circuit (PMIC) for generating a modulated voltage(s) to amplify a radio frequency (RF) signal modulated in multiple symbols. Specifically, the transceiver circuit will generate multiple voltage targets for any of the symbols to thereby enable intra-symbol voltage modulation when the respective symbol is modulated to carry a selected type of information (e.g., control information). In contrast, the transceiver circuit will generate a single voltage target for any of the symbols to thereby enable inter-symbol voltage modulation when the respective symbol is not modulated to carry the selected type of information. By dynamically performing inter-symbol and intra-symbol voltage modulation based on the type of information carried in a symbol(s), the modulated voltage can be timely adapted to closely track a time-variant power envelope of the RF signal to thereby avoid potential distortion (e.g., amplitude clipping) and protect critical information in the RF signal.

Before discussing inter-symbol and intra-symbol voltage modulation of the present disclosure, starting atFIG.2, an overview of orthogonal frequency division multiplexing (OFDM) symbols, which can be used to define durations of voltage modulation intervals, is first provided with reference toFIG.1.

FIG.1illustrates an exemplary time slot(s)10and a pair of mini time slots12(1)-12(2) as widely supported in a fifth generation (5G) and 5G new-generation (5G-NR) system. The time slot(s)10, which can represent any one or more of multiple continuous time slots, includes multiple symbols14(1)-14(N), such as OFDM symbols. The mini time slots12(1)-12(2) can each include at least two of the symbols14(1)-14(N). In the example shown inFIG.1, each of the mini time slots12(1)-12(2) includes four of the symbols14(1)-14(N). As previously shown in Table 1, each of the symbols14(1)-14(N) has a symbol duration that depends on the subcarrier spacing (SCS). Once the SCS is chosen, the duration and the CP of each of the symbols14(1)-14(N) are set accordingly.

The symbols14(1)-14(N) in the time slot(s)10can be modulated based on any type of modulation and coding scheme (MCS) to carry various types of information. For example, some of the symbols14(1)-14(N) can be modulated to carry downlink/uplink control information, some of the symbols14(1)-14(N) can be modulated to carry downlink/uplink data payload, and yet some of the symbols14(1)-14(N) can be empty (e.g., not bearing any information). Among the symbols14(1)-14(N), those symbols that are modulated to carry a selected type of information are of special importance in the context of the present disclosure.

Herein, the selected type of information may include information related to physical downlink control channel (PDCCH), physical uplink control channel (PUCCH), physical downlink shared channel (PDSCH), and/or physical uplink shared channel (PUSCH). In a non-limiting example, the selected type of information can be a sounding reference signal (SRS), a demodulation reference signal (DMRS), and so on. As described in detail below, whether the selected type of information is present or absent in any of the symbols14(1)-14(N) is a determining factor for intra-symbol or inter-symbol voltage modulation.

FIG.2is a schematic diagram of an exemplary transmission circuit16wherein a PMIC18and a transceiver circuit20are configured according to embodiments of the present disclosure to enable inter-symbol and intra-symbol voltage modulation. The transmission circuit16also includes a power amplifier circuit22. The power amplifier circuit22is configured to amplify an RF signal24based on a modulated voltage VCC, which can be an envelope tracking (ET) modulated voltage or an average power tracking (APT) modulated voltage. The PMIC18is configured to generate the modulated voltage VCCand the transceiver circuit20is configured to generate the RF signal24.

The transceiver circuit20is configured to modulate the RF signal24onto the symbols14(1)-14(N) inFIG.1. Herein, three consecutive symbols14(X−1),14(X),14(X+1) among the symbols14(1)-14(N) (X>1, N≥X+1) are illustrated as an example. As described above, some of the symbols14(X−1),14(X),14(X+1) may be modulated to carry the selected type of information, while some other ones of the symbols14(X−1),14(X),14(X+1) may not. As an example, it is assumed that the symbol14(X) is modulated to carry the selected type of information, and symbols14(X−1) and14(X+1) do not contain the selected type of information. In this regard, as further described below, the transmission circuit16will perform intra-symbol voltage modulation during the symbol14(X) and inter-symbol voltage modulation during the symbols14(X−1) and14(X+1).

Herein, intra-symbol voltage modulation means that the PMIC18can change the modulated voltage VCCmultiple times during the symbol14(X). In contrast, inter-symbol voltage modulation means that the PMIC18does not change the modulated voltage VCCduring any of the symbols14(X−1) and14(X+1). However, with inter-symbol voltage modulation, the PMIC18can still change the modulated voltage VCCbetween the symbols14(X−1) and14(X+1). In other words, the modulated voltage VCCin the symbol14(X−1) can be identical to or different from the modulated voltage VCCin the symbol14(X+1).

In an embodiment, the transceiver circuit20is configured to generate multiple target voltage indications VTGT(i) (i=X−1, X, X+1) in multiple voltage modulation intervals SX−1, SX, SX+1, respectively. Each of the voltage modulation intervals SX−1, SX, SX+1correspond to a respective one of the symbols14(X−1),14(X),14(X+1). In other words, there exists a one-to-one relationship between the voltage modulation intervals SX−1, SX, SX+1and the symbols14(X−1),14(X),14(X+1). Notably, the voltage modulation intervals SX−1, SX, SX+1represent three consecutive voltage modulation intervals among any number of voltage modulation intervals, so chosen for the sole purpose of illustration. Understandably, the voltage modulation interval SX−1is an immediately preceding voltage modulation interval of the voltage modulation interval SX, the voltage modulation interval SXis an immediately preceding voltage modulation interval of the voltage modulation interval SX+1, and so on.

According to an embodiment of the present disclosure, the PMIC18includes an inter-chip interface26, a memory circuit28, and a voltage generation circuit30. In a non-limiting example, the inter-chip interface26can be a multi-wire interface, such as an RF front-end (RFFE) interface, that is coupled to the transceiver circuit20. The transceiver circuit20is configured to provide a respective target voltage indication VTGT(i) (i=X−1, X, X+1, and so on) for each of the voltage modulation intervals SX−1, SX, SX+1.

Specifically, to enable to PMIC18to perform inter-symbol voltage modulation, the transceiver circuit20is configured to determine and provide a single voltage target VTGTto the PMIC18in the target voltage indications VTGT(i) (i=X−1, X+1). Accordingly, the PMIC18will generate the modulated voltage VCCduring the voltage modulation intervals SX−1, SX+1based on the respective voltage target VTGTreceived in the target voltage indications VTGT(i) (i=X−1, X+1).

Notably, the transceiver circuit20is configured to generate the RF signal24with a time-variant power envelope P(t) that can increase or decrease multiple times during each of the symbols14(X−1),14(X),14(X+1). In this regard, since the symbol14(X) includes the selected type of information, it is desirable that the PMIC18can generate multiple modulated voltages VCC1-VCCNduring the voltage modulation interval SXto better track (increase or decrease) the time-variant power envelope P(t) on an intra-symbol basis to help avoid potential distortion (e.g., amplitude clipping) to the RF signal24when the RF signal24is amplified by the power amplifier circuit22.

FIGS.3A and3Bare block diagrams providing exemplary illustrations of the target voltage indication VTGT(i) (i=X) generated by the transceiver circuit20inFIG.2to cause the PMIC18to perform the intra-symbol voltage modulation during the voltage modulation interval SX. Common elements betweenFIGS.2and3A-3Bare shown therein with common element numbers and will not be re-described herein.

In one embodiment, as illustrated inFIG.3A, the transceiver circuit20can divide the voltage modulation intervals SXequally such that each of the modulation subintervals T1-TNwill have an identical duration.

In another embodiment, as illustrated inFIG.3B, the transceiver circuit20can divide the voltage modulation interval SXunequally such that each of the modulation subintervals T1-TNwill have different durations. For example, the transceiver circuit20can make any of the modulation subintervals T1-TNlonger if a variation of the modulated voltage VCCexceeds a preset threshold between adjacent ones of the modulation subintervals T1-TN, or make any of the modulation subintervals T1-TNshorter if the modulated voltage VCCremains unchanged or the variation of the modulated voltage VCCis below the preset threshold in between the adjacent ones of the modulation subintervals T1-TN.

With reference back toFIG.2, the transceiver circuit20is also configured to set the voltage targets VTGT-1-VTGT-Nfor each of the modulation subintervals T1-TNbased on the time-variant power envelope P(t) of the RF signal24. In a non-limiting example, the transceiver circuit20can set a respective one of the voltage targets VTGT-1-VTGT-Nfor a respective one of the modulation subintervals T1-TNbased on a maximum of the time-variant power envelope P(t) during the respective one of the modulation subintervals T1-TN.

The transceiver circuit20is configured to write the voltage targets VTGT-1-VTGT-N, in association with the modulation subintervals T1-TN, into the memory circuit28via the inter-chip interface26. In one embodiment, the transceiver circuit20may write the voltage targets VTGT-1-VTGT-Nassociated with the voltage modulation interval SXprior to a start of the voltage modulation interval SX. Preferably, the transceiver circuit20will write the voltage targets VTGT-1-VTGT-Nassociated with the voltage modulation interval SXduring an immediately preceding one of the voltage modulation intervals SX−1, SX, SX+1. For example, the transceiver circuit20will write the voltage targets VTGT-1-VTGT-Nassociated with the voltage modulation interval SXduring the voltage modulation interval SX−1.

Prior to the voltage modulation interval SX, the voltage generation circuit30retrieves the voltage targets VTGT-1-VTGT-N, in association with the modulation subintervals T1-TN, from the memory circuit28. Accordingly, the voltage generation circuit30can generate the modulated voltages VCC-1-VCC-Nduring the modulation subintervals T1-TNbased on the voltage targets VTGT-1-VTGT-N, respectively.

FIG.4is a block diagram providing an exemplary illustration as to how the PMIC18inFIG.2can perform intra-symbol voltage modulation during the voltage modulation interval SX. Common elements betweenFIGS.2and4are shown therein with common element numbers and will not be re-described herein.

The voltage generation circuit30is configured to determine multiple starts TSTART-1-TSTART-Nof the modulation subintervals T1-TN, respectively. In a non-limiting example, the voltage generation circuit30can receive the start TSTART-1-TSTART-Nof the modulation subintervals T1-TNfrom the transceiver circuit20together with or separately from the voltage targets VTGT-1-VTGT-N. Accordingly, the voltage generation circuit30can generate each of the modulated voltages VCC-1-VCC-Nno later than a respective one of the determined start TSTART-1-TSTART-Nof the voltage modulation subintervals T1-TN.

According to an embodiment of the present disclosure, the voltage generation circuit30is configured to determine whether each of the modulated voltages VCC-1-VCC-Nis set to increase or decrease during a respective one of the modulation subintervals T1-TN. If any of the modulated voltages VCC-1-VCC-Nis set to increase during the respective one of the modulation subintervals T1-TN, the voltage generation circuit30may start transitioning to the respective one the modulated voltages VCC-1-VCC-Nprior to the respective start TSTART-1-TSTART-Nof the respective one of the modulation subintervals T1-TN. For example, the voltage generation circuit30determines that the modulated voltages VCC-1and VCC-3are set to increase during the modulation subintervals T1and T3, respectively. Accordingly, the voltage generation circuit30will start transitioning to the modulated voltages VCC-1and VCC-3with a timing advance Ta prior to the respective starts TSTART-1and TSTART-3of the modulation subintervals T1and T3. By starting the transition with the timing advance Ta, the voltage generation circuit30can ensure that the modulated voltages VCC-1and VCC-3can be ramped up to desired levels in time to help avoid amplitude clipping in the RF signal24.

In contrast, if any of the modulated voltages VCC-1-VCC-Nis set to increase, or remain unchanged, during the respective one of the modulation subintervals T1-TN, the voltage generation circuit30may start transitioning to the respective one the modulated voltages VCC-1-VCC-Nat the respective start TSTART-1-TSTART-Nof the respective one of the modulation subintervals T1-TN. For example, the voltage generation circuit30determines that the modulated voltages VCC-2and VCC-Nare set to decrease during the modulation subintervals T2and TN, respectively. Accordingly, the voltage generation circuit30will start transitioning to the modulated voltages VCC-2and VCC-Nright at the respective starts TSTART-2and TSTART-Nof the modulation subintervals T2and TN.

FIG.5is a schematic diagram of the voltage generation circuit30configured according to an embodiment of the present disclosure. Common elements betweenFIGS.2and5are shown therein with common element numbers and will not be re-described herein.

Herein, the voltage generation circuit30includes a current modulation circuit32, a voltage modulation circuit34, and a control circuit36. The current modulation circuit32includes a multi-level charge pump (MCP)38and a power inductor40. During the voltage modulation interval SX, the MCP38is configured to generate multiple low-frequency voltages VDC-1-VDCN, each as a function of a battery voltage VBAT, during the modulation subintervals T1-TN, respectively. Accordingly, in the voltage modulation interval SX, the power inductor40is configured to induce multiple low frequency currents IDC1-IDCNbased on the low-frequency voltages VDC-1-VDCN, respectively.

The voltage modulation circuit34includes a voltage amplifier42, an offset capacitor COFF, and a bypass switch SBYP. The voltage amplifier42is configured to generate multiple modulated initial voltages VAMP1-VAMPNbased on the voltage targets VTGT-1-VTGT-Nin the modulation subintervals T1-TN, respectively. The offset capacitor COFFis modulated by the low frequency currents IDC1-IDCNto multiple offset voltages VOFF1-VOFFNin the modulation subintervals T1-TN, respectively. Each of the offset voltages VOFF1-VOFFNwill raise a respective one of the modulated initial voltages VAMP1-VAMPNto a respective one of the modulated voltages VCC1-VCCN. For specific example as to how the offset voltages VOFF1-VOFFNcan be modulated by the low frequency currents IDC1-IDCNto raise the modulated initial voltages VAMP1-VAMPNto the modulated voltages VCC1-VCCN, please refer to U.S. patent application Ser. No. 17/946,224, entitled “MULTI-VOLTAGE GENERATION CIRCUIT.”

FIG.6is a schematic diagram illustrating the transceiver circuit20inFIG.2configured to enable inter-symbol and intra-symbol voltage modulation. Common elements betweenFIGS.2and6are shown therein with common element numbers and will not be re-described herein.

Herein, the transceiver circuit20includes a digital baseband circuit44, a signal processing circuit46, and a target voltage circuit48. The digital baseband circuit44is configured to generate an input vector {right arrow over (bMOD)} modulated in the symbols14(X−1),14(X),14(X+1). According to the example described above, the symbol14(X) is modulated to include the selected type of information, while the symbols14(X−1) and14(X+1) are not. In an embodiment, the digital baseband circuit44may determine which of the symbols14(X−1),14(X),14(X+1) will be modulated with the selected type of information based on system configuration. For example, in a 5G or 5G-NR system, the exact symbol location of the selected type of information can be predefined in a standard, such as a third-generation partnership project (3GPP) standard.

The signal processing circuit46, which may include digital-to-analog converter (DAC) and frequency converter (not shown), is configured to generate the RF signal24from the input vector {right arrow over (bMOD)} and provide the RF signal24to the power amplifier circuit22inFIG.2.

In an embodiment, the target voltage circuit48may include an internal memory and an internal processor, which are not shown herein for the sake of simplicity. The internal memory, which can be any type of memory, may store a target voltage lookup table (LUT) that correlates a time-variant amplitude of the input vector {right arrow over (bMOD)} with various levels of voltage targets. The internal memory may also store the exact symbol location of the selected type of information such that the internal processor (e.g., a digital signal processor) in the target voltage circuit48can determine whether the selected type of information is modulated in any of the symbols14(X−1),14(X),14(X+1). Alternatively, the digital baseband circuit44may provide an indication to the target voltage circuit48as to which of the symbols14(X−1),14(X),14(X+1) is modulated with the selected type of information.

The target voltage circuit48is configured to determine the voltage modulation intervals SX−1, SX, SX+1that correspond respectively to the symbols14(X−1),14(X),14(X+1). In one embodiment, the internal processor of the target voltage circuit48determines that the symbol14(X) is modulated to include the selected type of information. Accordingly, the internal processor in the target voltage circuit48divides the voltage modulation interval SXinto the voltage modulation subintervals T1-TNand uses the target voltage LUT to generate the voltage targets VTGT-1-VTGT-Nfor the voltage modulation subintervals T1-TN, respectively. In another embodiment, the internal processor in the target voltage circuit48determines that the symbols14(X−1) and14(X+1) are not modulated to include the selected type of information. Accordingly, the internal processor in the target voltage circuit48uses the target voltage LUT to generate the single voltage target VTGTfor the voltage modulation intervals SX−1and SX+1. Further, the internal processor in the target voltage circuit48generates the target voltage indications VTGT(i) (i=X−1, X, X+1) and provides the target voltage indications VTGT(i) to the PMIC18via the inter-chip interface26. In an embodiment, the target voltage LUT may store the various levels of voltage targets in digital formats. In this regard, the target voltage circuit48may also include an internal DAC (not shown) to convert the voltage targets VTGT-1-VTGT-Nor the single voltage target VTGTinto respective analog formats in the target voltage indications VTGT(i).

The transmission circuit16ofFIG.2can be configured to enable inter-symbol and intra-symbol voltage modulation based on a process. In this regard,FIG.7is a flowchart of an exemplary process200for enabling inter-symbol and intra-symbol voltage modulation according to embodiments of the present disclosure.

Herein, the digital baseband circuit44is configured to generate an input vector {right arrow over (bMOD)} modulated to include the selected type of information in one or more (e.g., symbol14(X)) of the symbols14(X−1),14(X),14(X+1) (step202). The target voltage circuit48is configured to determine the voltage modulation intervals SX−1, SX, SX+1corresponding to the symbols14(X−1),14(X),14(X+1) (step204). The target voltage circuit48then divides a respective one (e.g., voltage modulation interval SX) of the voltage modulation intervals SX−1, SX, SX+1into the voltage modulation subintervals T1-TN, each of the voltage modulation subintervals includes a respective one of the voltage targets VTGT-1-VTGT-Nwhen the target voltage circuit48determines that a corresponding one (e.g., symbol14(X)) of the symbols14(X−1),14(X),14(X+1) includes the selected type of information (step206). The target voltage circuit48then generates a respective one of the target voltage indications VTGT(i) (i=X−1, X, X+1) that includes the voltage targets VTGT-1-VTGT-N(step208). The voltage generation circuit30will then generate the modulated voltages VCC1-VCCNin the voltage modulation subintervals T1-TNbased on the voltage targets VTGT-1-VTGT-N, respectively (step210).

Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.