Patent ID: 12243492

DESCRIPTION OF EMBODIMENTS

Preferred embodiments according to the present disclosure will be described below with reference to the accompanying drawings. In addition, in the drawings, dimensions and scales of each part are appropriately made different from actual ones, and some parts are shown schematically to make them easier to understand. Also, the scope of the present disclosure is not limited to these forms unless the present disclosure is specifically described as being limited in the following description.

A. First Embodiment

1. Basic Configuration of Display Device1

FIG.1is a diagram showing a display device1according to a first embodiment. The display device1shown inFIG.1is, for example, a micro-display that displays images on a head-mounted display. Also, the display device1is, for example, an organic EL device including an OLED. OLED is an abbreviation for Organic Light emitting Diode. EL is an abbreviation of Electroluminescence. In this embodiment, the display device1can display full-color images. In addition, the images include those only displaying text information. Further, the display device1may be a device that can display only a single color.

The display device1includes a display panel10that displays images and is housed in a frame-shaped case71that opens at the display panel10. One end of an FPC board72is coupled to the display device1. FPC is an abbreviation for Flexible Printed Circuit. A plurality of terminals73for coupling a host device (not shown) are provided to the other end of the FPC board72. When the plurality of terminals73are coupled to the host device, various signals are supplied to the display device1from the host device via the FPC board72.

2. Configuration of Display Device1

FIG.2is a diagram schematically showing the display device1ofFIG.1. Also, the following description will be made using an X direction and a Y direction appropriately for convenience of explanation. An axis extending in the X direction and an axis extending in the Y direction are orthogonal to each other. The X direction is a “first direction” and a “row direction”, and the Y direction is a “second direction” and a “column direction”.

As shown inFIG.2, the display device1includes the display panel10, a control circuit130, a scanning line drive circuit110, and a data line drive circuit120. The display panel10, the control circuit130, the scanning line drive circuit110, and the data line drive circuit120are formed at a semiconductor substrate such as a silicon substrate, for example.

The display panel10is provided with m scanning lines11extending in the X direction and n data lines12extending in the Y direction. A plurality of display pixels P0are provided to correspond to intersections of a plurality of scanning lines11and a plurality of data lines12. Also, for example, a pixel P representing one dot of a color image is configured for every three display pixels P0arranged in the X direction. In this embodiment, an arrangement of pixels P is a so-called RGB stripe arrangement. In addition, each display pixel P0is provided with a pixel electrode151included in a light emitting element15, which will be described later.

The control circuit130controls image display. Digital video data Video output from a host device (not shown) is supplied to the control circuit130shown inFIG.2in synchronization with a synchronization signal Sync. The control circuit130controls each part of the display device1based on the video data Video and the synchronization signal Sync. The video data Video specifies a gradation level of the display pixel P0in an image to be displayed using, for example, 8 bits. Further, the synchronization signal Sync is a signal including a vertical synchronization signal that instructs to start vertical scanning of the video data Video, a horizontal synchronization signal that instructs to start horizontal scanning thereof, and a dot clock signal.

The control circuit130generates a control signal Ctr1based on the synchronization signal Sync and supplies the control signal Ctr1to the scanning line drive circuit110, and generates a control signal Ctr2based on the synchronization signal Sync and supplies the control signal Ctr2to the data line drive circuit120. Each of the control signals Ctr1and Ctr2includes a plurality of signals such as a pulse signal, a clock signal, and an enable signal.

Further, the control circuit130generates video data Vid based on the video data Video and supplies the video data Vid to the data line drive circuit120. Brightness characteristics may not match between a gradation level indicated by the video data Vid and the light emitting element15, which will be described later. Thus, in order to cause the light emitting element15to emit light at a brightness corresponding to the gradation level indicated by the video data Video, the control circuit130generates the video data Vid obtained by changing the 8 bits of the video data Video to 10 bits, for example.

In addition, the control circuit130is supplied with electric power from a power supply circuit (not shown) and supplies a power supply potential to the scanning line drive circuit110, the data line drive circuit120, and a plurality of transistor circuits20, which will be described later, included in the display panel10.

The scanning line drive circuit110generates a scanning signal Gwr based on the control signal Ctr1. The scanning signal Gwr is a signal for sequentially selecting and scanning m rows of the scanning lines11every predetermined number of rows in each frame period V. The scanning line drive circuit110sequentially and exclusively selects one or more scanning lines11from the m rows of the scanning lines11for each horizontal scanning period H included in each frame period V, and selects a display pixel P0to which a video signal Vd is written from among the plurality of display pixels P0. Further, inFIG.2, the scanning signals Gwr supplied to 1st, 2nd, 3rd, . . . , and m-th rows of the scanning lines11are expressed as Gwr_1, Gwr_2, Gwr_3, . . . , and Gwr_m.

Also, the above-described frame period V indicates a period required for the display device1to display one cut of images. A length of the frame period V is, for example, 1/60 second when a driving frame rate is 60 Hz. One frame period V includes the horizontal scanning period H and a light emission period corresponding to each row. The light emission period is a period during which the light emitting element15emits light. One horizontal scanning period H is a period required for horizontal scanning of one row. One horizontal scanning period H includes a writing period in which the video signal Vd is written to the display pixel P0. Further, the number of scanning lines11selected in one horizontal scanning period H is not limited to one row and may be two or more rows.

The data line drive circuit120supplies video signals Vd to the transistor circuits20, which will be described later, corresponding to the display pixels P0provided in the row selected by the scanning line drive circuit110. Also, inFIG.2, the video signals Vd supplied to the data lines12in the 1st, 2nd, 3rd, . . . , and n-th rows are expressed as Vd_1, Vd_2, Vd_3, . . . , and Vd_n.

3. Arrangement of Display Pixels P0

FIG.3is a diagram showing two arbitrary pixels P among the plurality of pixels P inFIG.1.FIG.3shows two arbitrary pixels P among the plurality of pixels P. One pixel P is defined as a first pixel P1and the other pixel P is defined as a second pixel P2. The second pixel P2is provided in the Y direction with respect to the first pixel P1.

Each of the first pixel P1and the second pixel P2has three display pixels P0. Specifically, the first pixel P1has a first display pixel Pa, a third display pixel Pc, and a fifth display pixel Pe. The first display pixel Pa, the third display pixel Pc, and the fifth display pixel Pe are arranged in the X direction. Also, the second pixel P2has a second display pixel Pb, a fourth display pixel Pd, and a sixth display pixel Pf. The second display pixel Pb, the fourth display pixel Pd, and the sixth display pixel Pf are arranged in the X direction. The first display pixel Pa and the second display pixel Pb emit light in a red wavelength band, for example. The third display pixel Pc and the fourth display pixel Pd emit light in a green wavelength band, for example. The fifth display pixel Pe and the sixth display pixel Pf emit light in a blue wavelength band, for example.

The pixel electrode151is provided in each display pixel P0. Similarly to the plurality of display pixels P0being disposed in a matrix, a plurality of pixel electrodes151are disposed in a matrix. Also, although not shown, each of the display pixels P0is provided with a light emitting region having substantially the same planar area and substantially the same planar shape as the pixel electrodes151. Light is emitted from the light emitting region.

The first display pixel Pa is provided with a first pixel electrode151a. The third display pixel Pc is provided with a third pixel electrode151c. The fifth display pixel Pe is provided with a fifth pixel electrode151e. In addition, the second display pixel Pb is provided with a second pixel electrode151b. The fourth display pixel Pd is provided with a fourth pixel electrode151d. The fifth display pixel Pe is provided with a fifth pixel electrode151e. The sixth display pixel Pf is provided with a sixth pixel electrode151f.

The third pixel electrode151cis provided in the X direction with respect to the first pixel electrode151a. The fifth pixel electrode151eis provided in the X direction with respect to the third pixel electrode151c. In addition, the second pixel electrode151bis provided in the Y direction with respect to the first pixel electrode151a. The fourth pixel electrode151dis provided in the Y direction with respect to the third pixel electrode151cand is provided in the X direction with respect to the second pixel electrode151b. The sixth pixel electrode151fis provided in the Y direction with respect to the fifth pixel electrode151eand is provided in the X direction with respect to the fourth pixel electrode151d.

4. Arrangement of Transistor Circuits20

FIG.4is a layout diagram of six transistor circuits20corresponding to six display pixels P0shown inFIG.3. InFIG.4, a first transistor circuit20a, a second transistor circuit20b, a third transistor circuit20c, a fourth transistor circuit20d, a fifth transistor circuit20e, and a sixth transistor circuit20fare shown as the six transistor circuits20.

The first transistor circuit20acorresponds to the first display pixel Pa. The second transistor circuit20bcorresponds to the second display pixel Pb. The third transistor circuit20ccorresponds to the third display pixel Pc. The fourth transistor circuit20dcorresponds to the fourth display pixel Pd. The fifth transistor circuit20ecorresponds to the fifth display pixel Pe. The sixth transistor circuit20fcorresponds to the sixth display pixel Pf.

The first transistor circuit20a, the second transistor circuit20b, the third transistor circuit20c, the fourth transistor circuit20d, the fifth transistor circuit20e, and the sixth transistor circuit20fare arranged in order in the X direction.

Although not shown in detail, the first transistor circuit20aand the second transistor circuit20boverlap the first display pixel Pa and the second display pixel Pb in a plan view. With such an arrangement, the problem of an electrical coupling path between the first transistor circuit20aand the first pixel electrode151abecoming excessively long and excessively complicated is inhibited. Also, the same applies to the second transistor circuit20b. In addition, the plan view indicates viewing in a direction orthogonal to both the X direction and the Y direction.

Similarly, although not shown in detail, the third transistor circuit20cand the fourth transistor circuit20doverlap the third display pixel Pc and the fourth display pixel Pd in a plan view. With such an arrangement, the problem of an electrical coupling path between the third transistor circuit20cand the third pixel electrode151cbecoming excessively long and excessively complicated is inhibited. Also, the same applies to the fourth transistor circuit20d. In addition, the fifth transistor circuit20eand the sixth transistor circuit20foverlap the fifth display pixel Pe and the sixth display pixel Pf in a plan view. With such an arrangement, the problem of an electrical coupling path between the fifth transistor circuit20eand the fifth pixel electrode151ebecoming excessively long and excessively complicated is inhibited. Also, the same applies to the sixth transistor circuit20f.

5. Configuration of Transistor Circuits20

FIG.5is a diagram showing the six transistor circuits20ofFIG.4. As shown inFIG.5, the first transistor circuit20aincludes a first light emitting element15a, a first drive transistor16a, a first selection transistor17a, and a first capacitive element18a.

The first light emitting element15aincludes the first pixel electrode151a, a common electrode152, and a light emitting layer153. Also, the common electrode152is common to first to sixth light emitting elements15ato15f. The light emitting layer153is common to the first to sixth light emitting elements15ato15f, but may be provided individually.

The first light emitting element15ais disposed on a path that couples a first constant potential wiring13pand a second constant potential wiring14p. A higher potential Vel is supplied to the first constant potential wiring13pfrom a power supply circuit (not shown). A lower potential Vct is supplied to the second constant potential wiring14pfrom the power supply circuit. Also, the first light emitting element15ais, for example, an OLED. The light emitting layer153includes a light emitting material and is interposed between the first pixel electrode151aand the common electrode152. The first pixel electrode151afunctions as an anode electrode, and the common electrode152functions as a cathode electrode. In such a first light emitting element15a, holes supplied from the first pixel electrode151aand electrons supplied from the common electrode152are recombined in the light emitting layer153. Due to the recombination, the light emitting layer153emits light.

The first drive transistor16asupplies the first pixel electrode151awith a first drive current Ida based on a potential corresponding to a first video signal Vda supplied from a first data line12aof the n data lines12. The first drive transistor16ais disposed in series with the first light emitting element15a. One of a source and a drain of the first drive transistor16ais electrically coupled to the first constant potential wiring13p, and the other is electrically coupled to the first pixel electrode151a.

The first selection transistor17aelectrically couples the first data line12ato the first drive transistor16a. Specifically, the first selection transistor17afunctions as a switch that controls conduction and non-conduction between the first data line12aand a gate of the first drive transistor16a. One of a source and a drain of the first selection transistor17ais electrically coupled to the first data line12a, and the other is electrically coupled to the gate of the first drive transistor16a. A gate of the first selection transistor17ais electrically coupled to one arbitrary scanning line11pamong the m scanning lines11.

In the following, the second to sixth transistor circuit20bto20fwill be described, but the description of items similar to those of the first transistor circuit20awill be appropriately omitted.

The second transistor circuit20bincludes a second light emitting element15b, a second drive transistor16b, a second selection transistor17b, and a second capacitive element18b. The second light emitting element15bincludes the second pixel electrode151b, the common electrode152, and the light emitting layer153. The second drive transistor16bsupplies the second pixel electrode151bwith a second drive current Idb based on a potential corresponding to a second video signal Vdb supplied from a second data line12b. The second selection transistor17belectrically couples the second data line12bamong the n data lines12to the second drive transistor16b. A gate of the second selection transistor17bis electrically coupled to the scanning line11p.

The third transistor circuit20cincludes a third light emitting element15c, a third drive transistor16c, a third selection transistor17c, and a third capacitive element18c. The third light emitting element15cincludes the third pixel electrode151c, the common electrode152, and the light emitting layer153. The third drive transistor16csupplies the third pixel electrode151cwith a third drive current Idc based on a potential corresponding to a third video signal Vdc supplied from a third data line12c. The third selection transistor17celectrically couples the third data line12camong the n data lines12to the third drive transistor16c. A gate of the third selection transistor17cis electrically coupled to the scanning line11p.

The fourth transistor circuit20dincludes a fourth light emitting element15d, a fourth drive transistor16d, a fourth selection transistor17d, and a fourth capacitive element18d. The fourth light emitting element15dincludes the fourth pixel electrode151d, the common electrode152, and the light emitting layer153. The fourth drive transistor16dsupplies the fourth pixel electrode151dwith a fourth drive current Idd based on a potential corresponding to a fourth video signal Vdd supplied from a fourth data line12d. The fourth selection transistor17delectrically couples the fourth data line12damong the n data lines12to the fourth drive transistor16d. A gate of the fourth selection transistor17dis electrically coupled to the scanning line11p.

The fifth transistor circuit20eincludes a fifth light emitting element15e, a fifth drive transistor16e, a fifth selection transistor17e, and a fifth capacitive element18e. The fifth light emitting element15eincludes the fifth pixel electrode151e, the common electrode152, and the light emitting layer153. The fifth drive transistor16esupplies the fifth pixel electrode151ewith a fifth drive current Ide based on a potential corresponding to a fifth video signal Vde supplied from a fifth data line12e. The fifth selection transistor17eelectrically couples the fifth data line12eamong the n data lines12to the fifth drive transistor16e. A gate of the fifth selection transistor17eis electrically coupled to the scanning line11p.

The sixth transistor circuit20fincludes a sixth light emitting element15f, a sixth drive transistor16f, a sixth selection transistor17f, and a sixth capacitive element18f. The sixth light emitting element15fincludes the sixth pixel electrode151f, the common electrode152, and the light emitting layer153. The sixth drive transistor16fsupplies the sixth pixel electrode151fwith a sixth drive current Idf based on a potential corresponding to a sixth video signal Vdf supplied from a sixth data line12f. The sixth selection transistor17felectrically couples the sixth data line12famong the n data lines12to the sixth drive transistor16f. A gate of the sixth selection transistor17fis electrically coupled to the scanning line11p.

Also, the configuration of the transistor circuits20shown inFIG.5is an example, and a configuration other than that shown inFIG.5may be used. For example, the first transistor circuit20amay further include another transistor that controls conduction between the first pixel electrode151aand the first drive transistor16a.

As described above, the first pixel electrode151aand the second pixel electrode151bshown inFIG.3are arranged in the Y direction. On the other hand, the first transistor circuit20aand the second transistor circuit20bshown inFIG.4are arranged in the X direction. Accordingly, the arrangement direction of the first transistor circuit20aand the second transistor circuit20bintersects the arrangement direction of the first pixel electrode151aand the second pixel electrode151b. In addition, the gate included in the first selection transistor17ashown inFIG.5and the gate included in the second selection transistor17bare electrically coupled to the same scanning line11p. Further, either the source or the drain of the first selection transistor17aand either a source or a drain of the second selection transistor17bare electrically coupled to different data lines12.

In known art, the transistor circuits20are disposed in a matrix, similarly to the arrangement of the pixel electrodes151. For this reason, in known art, when the first pixel electrode151aand the second pixel electrode151bare arranged in the Y direction, the first transistor circuit20aand the second transistor circuit20bare arranged in the Y direction. Thus, the first transistor circuit20aand the second transistor circuit20bare electrically coupled to different scanning lines11. Accordingly, in known art, two scanning lines11are required to control ON/OFF of the first selection transistor17aand the second selection transistor17b.

On the other hand, in this embodiment, the first pixel electrode151aand the second pixel electrode151bare arranged in the Y direction, whereas the first transistor circuit20aand the second transistor circuit20bare arranged in the X direction. For this reason, the gate of the first selection transistor17aand the gate of the second selection transistor17bare electrically coupled to the same scanning line11p. Accordingly, the scanning line11pfor controlling ON/OFF of the first selection transistor17band the second selection transistor17bis common. Thus, in known art, two scanning lines11are required, but in this embodiment, only one scanning line11pis required. That is, the number of scanning lines11can be reduced to ½ as compared with the known configuration. For this reason, it is possible to make one horizontal scanning period H twice longer than one horizontal scanning period H in known art. Thus, deterioration in display quality due to shortening of one horizontal scanning period H can be inhibited. In particular, even when progress to a higher driving frame rate is made, one horizontal scanning period H sufficient for maintaining the display quality can be secured.

Also, as shown inFIG.3, the third pixel electrode151cis provided in the X direction with respect to the first pixel electrode151a. The fourth pixel electrode151dis provided in the X direction with respect to the second pixel electrode151band is provided in the Y direction with respect to the third pixel electrode151c. The fifth pixel electrode151eis provided in the X direction with respect to the third pixel electrode151c. The sixth pixel electrode151fis provided in the X direction with respect to the fourth pixel electrode151dand is provided in the Y direction with respect to the fifth pixel electrode151e. Accordingly, the first to sixth pixel electrodes151ato151fare arranged in two rows and three columns.

Also, as shown inFIG.4, the third transistor circuit20c, the fourth transistor circuit20d, the fifth transistor circuit20e, and the sixth transistor circuit20fare arranged in the X direction, which is the same as the direction in which the scanning line11pextends. Accordingly, the first to sixth transistor circuits20ato20fare arranged in one row and six columns. In addition, the gate of the third selection transistor17c, the gate of the fourth selection transistor17d, the gate of the fifth selection transistor17e, and the gate of the sixth selection transistor17fare electrically coupled to the scanning line11p. Accordingly, each gate of the first to sixth selection transistors17ato17fis electrically coupled to the scanning line11p. Thus, the scanning line11pthat controls ON/OFF of the first to sixth selection transistors17ato17fof the first to sixth transistor circuits20ato20fis common. Also, either sources or drains of the first to sixth selection transistors17ato17fare electrically coupled to different data lines12.

According to this embodiment, while the six display pixels P0are arranged in two rows and three columns, the six transistor circuits20are arranged in one row and six columns. Accordingly, the number of transistor circuits20arranged in the column direction can be halved as compared to the number of pixel electrodes151arranged in the column direction. That is, the number of transistor circuits20arranged can be halved as compared to the number of display pixels P0arranged. Accordingly, as described above, one horizontal scanning period H can be secured to be twice longer than one horizontal scanning period H in known art. Thus, deterioration in display quality can be inhibited.

Also, the first pixel electrode151a, the third pixel electrode151c, and the fifth pixel electrode151eform the first pixel P1that forms one dot in color display. The second pixel electrode151b, the fourth pixel electrode151d, and the sixth pixel electrode151fform the second pixel P2that forms another dot in the color display. Thus, the transistor circuits20of the two pixels P arranged in the column direction are arranged in the row direction. In addition, the gates of the transistor circuits20included in the two pixels P arranged in the column direction are electrically coupled to the one scanning line11p. According to such a configuration, regardless of the arrangement direction of the pixels P, as described above, the number of transistor circuits20arranged in the column direction can be halved as compared to the number of pixel electrodes151arranged in the column direction. Accordingly, as described above, one horizontal scanning period H can be secured to be twice longer than one horizontal scanning period H in known art. Thus, deterioration in display quality can be inhibited.

B. Second Embodiment

A second Embodiment will be described. Also, in each of the following examples, the reference numerals used in the description of the first embodiment will be used for elements whose functions are similar to those in the first embodiment, and each detailed description thereof will be appropriately omitted.

This embodiment is different from the first embodiment in the combination of the display pixels P0included in one pixel P. The arrangement of the display pixels P0in this embodiment is a so-called Bayer array.

FIG.6is a diagram showing one pixel P in the second embodiment. Also,FIG.6shows one arbitrary pixel PA among the plurality of pixels P.

As shown inFIG.6, the pixel PA includes four display pixels P0. Specifically, the pixel PA includes a first display pixel PaA, a second display pixel PbA, a third display pixel PcA, and a fourth display pixel PdA. For example, the first display pixel PaA emits light in a red wavelength band. The second display pixel PbA emits light in a green wavelength band. The third display pixel PcA emits light in a green wavelength band. The fourth display pixel PdA emits light in a blue wavelength band.

The first pixel electrode151ais provided in the first display pixel PaA. The second pixel electrode151bis provided in the second display pixel PbA. The third pixel electrode151cis provided in the third display pixel PcA. The fourth pixel electrode151dis provided in the fourth display pixel PdA.

The second pixel electrode151bis provided in the Y direction with respect to the first pixel electrode151a. The third display pixel PcA is provided in the X direction with respect to the first pixel electrode151a. The fourth pixel electrode151dis provided in the Y direction with respect to the third display pixel PcA and is provided in the X direction with respect to the second pixel electrode151b.

FIG.7is a layout diagram of four transistor circuits20corresponding to the four display pixels P0shown inFIG.6. InFIG.7, the first transistor circuit20a, the second transistor circuit20b, the third transistor circuit20c, and the fourth transistor circuit20dare shown as the four transistor circuits20. The first transistor circuit20acorresponds to the first display pixel PaA. The second transistor circuit20bcorresponds to the second display pixel PbA. The third transistor circuit20ccorresponds to the third display pixel PcA. The fourth transistor circuit20dcorresponds to the fourth display pixel PdA.

The first transistor circuit20a, the second transistor circuit20b, the third transistor circuit20c, and the fourth transistor circuit20dare arranged in order in the X direction.

Although not shown in detail, the first transistor circuit20aand the second transistor circuit20boverlap the first display pixel PaA and the second display pixel PbA in a plan view. With such an arrangement, the problem of an electrical coupling path between the first transistor circuit20aand the first pixel electrode151abecoming excessively long and excessively complicated is inhibited. Also, the same applies to the second transistor circuit20b. In addition, although not shown in detail, the third transistor circuit20cand the fourth transistor circuit20doverlap the third display pixel PcA and the fourth display pixel PdA in a plan view. With such an arrangement, the problem of an electrical coupling path between the third transistor circuit20cand the third pixel electrode151cbecoming excessively long and excessively complicated is inhibited. Also, the same applies to the fourth transistor circuit20d.

In this embodiment, the four display pixels P0are arranged in two rows and two columns, whereas the four transistor circuits20are arranged in one row and four columns. Further, the gate of the first selection transistor17a, the gate of the second selection transistor17b, the gate of the third selection transistor17c, and the gate of the fourth selection transistor17dare electrically coupled to the same scanning line11p.

According to this embodiment, similarly to the first embodiment, the number of transistor circuits20arranged in the column direction can be halved as compared to the number of pixel electrodes151arranged in the column direction. That is, the number of transistor circuits20arranged can be halved as compared to the number of display pixels P0arranged. Specifically, the number of transistor circuits20arranged in the row direction is twice larger than the number of display pixels P0arranged. According to the configuration of this embodiment, one horizontal scanning period H can be secured to be twice longer than one horizontal scanning period H in known art. Thus, deterioration in display quality due to shortening of one horizontal scanning period H can be inhibited.

In addition, in this embodiment, the first pixel electrode151a, the second pixel electrode151b, the third pixel electrode151c, and the fourth pixel electrode151dform one pixel P that forms one dot in color display. Thus, the first to fourth transistor circuit20ato20dcorresponding to one pixel P are arranged in one row, and each gate of the first to fourth transistor circuit20ato20dis electrically coupled to the scanning line11p. Even when four display pixels P0of one pixel P are arranged in two rows and two columns as in this embodiment, the number of transistor circuits20arranged in the column direction can be halved as compared to the number of pixel electrodes151arranged in the column direction. Accordingly, as described above, one horizontal scanning period H can be secured to be twice longer than one horizontal scanning period H in known art. Thus, deterioration in display quality can be inhibited.

C: Third Embodiment

A third embodiment will be described. Also, in each of the following examples, the reference numerals used in the description of the first embodiment will be used for elements whose functions are similar to those in the first embodiment, and each detailed description thereof will be appropriately omitted.

This embodiment is different from the first embodiment in the combination of the display pixels P0included in one pixel P. In this embodiment, for example, monochrome display is performed.

FIG.8is a diagram showing one pixel P in the third embodiment. Also,FIG.8shows one arbitrary pixel PB among the plurality of pixels P. As shown inFIG.8, the pixel PB includes two display pixels P0. Specifically, the pixel PB includes a first display pixel PaB and a second display pixel PbB. For example, the first display pixel PaB and the second display pixel PbB emit light in a wavelength band of the same color.

The first pixel electrode151ais provided in the first display pixel PaB. The second pixel electrode151bis provided in the second display pixel PbB. The second pixel electrode151bis provided in the Y direction with respect to the first pixel electrode151a.

FIG.9is a layout diagram of two transistor circuits20corresponding to the two display pixels P0shown inFIG.8. InFIG.9, the first transistor circuit20aand the second transistor circuit20bare shown as the two transistor circuits20. The first transistor circuit20acorresponds to the first display pixel PaB. The second transistor circuit20bcorresponds to the second display pixel PbB.

The first transistor circuit20aand the second transistor circuit20bare arranged in order in the X direction. Although not shown in detail, the first transistor circuit20aand the second transistor circuit20boverlap the first display pixel PaB and the second display pixel PbB in a plan view. With such an arrangement, the problem of an electrical coupling path between the first transistor circuit20aand the first pixel electrode151abecoming excessively long and excessively complicated is inhibited. Similarly, the problem of an electrical coupling path between the second transistor circuit20band the second pixel electrode151bbecoming excessively long and excessively complicated is inhibited.

In this embodiment, similarly to the first embodiment, the arrangement direction of the first transistor circuit20aand the second transistor circuit20bintersects the arrangement direction of the first pixel electrode151aand the second pixel electrode151b. Further, in this embodiment, the two display pixels P0are arranged in two rows and one column, whereas the two transistor circuits20are arranged in one row and two columns. In addition, the gate included in the first selection transistor17aand the gate included in the second selection transistor17bare electrically coupled to the same scanning line11p.

According to this embodiment, similarly to the first embodiment, the number of transistor circuits20arranged in the column direction can be halved as compared to the number of pixel electrodes151arranged in the column direction. That is, the number of transistor circuits20arranged can be halved as compared to the number of display pixels P0arranged. According to the configuration of this embodiment, one horizontal scanning period H can be secured to be twice longer than one horizontal scanning period H in known art. Thus, deterioration in display quality due to shortening of one horizontal scanning period H can be inhibited.

In addition, in this embodiment, the first pixel electrode151aand the second pixel electrode151bform one pixel P that forms one dot in color display. Even when two display pixels P0included in one pixel P are arranged in two rows and one column, gates of the two transistor circuits20corresponding to the two display pixels P0are electrically coupled to one scanning line11p. According to such a configuration, as described above, the number arranged in the row direction can be halved. Accordingly, as described above, one horizontal scanning period H can be secured to be twice longer than one horizontal scanning period H in known art. Thus, deterioration in display quality can be inhibited.

D. Modified Examples

The embodiments exemplified above may be modified in various ways. Specific modified aspects that may be applied to the above-described embodiments will be exemplified below. Two or more aspects arbitrarily selected from the following examples may be combined as appropriate within a range in which they do not contradict each other.

The arrangements of the display pixels P0in the above-described embodiments are examples, and other arrangements may be used. For example, a so-called PenTile arrangement or the like may be used.

In the above-described embodiment, the two transistor circuits20overlap the two display pixels P0in a plan view. However, three or more transistor circuits20may overlap three or more display pixels P0in a plan view. In this case, three or more transistor circuits20corresponding to three or more display pixels P0arranged in the Y direction are arranged in the X direction. In addition, gates of the selection transistors17included in the three transistor circuits20are electrically coupled to the same scanning line11p. According to this configuration, the number of transistor circuits20arranged can be reduced to ⅓ or less of the number of display pixels P0arranged. According to such a configuration, one horizontal scanning period H can be secured to be three times or more of one horizontal scanning period H in known art.

However, a configuration in which two transistor circuits20overlap two display pixels P0in a plan view and gates of selection transistors17included in the two transistor circuits20corresponding to the two display pixels P0are electrically coupled to the same scanning line11pis optimal. The number of wirings of the data lines12does not become excessively dense, and deterioration in display quality due to shortening of one horizontal scanning period H can be inhibited.

In the above-described embodiments, the light emitting element15is an OLED. However, for example, the light emitting element15may be an LED, a mini LED, a micro LED, or the like. LED is an abbreviation for Light emitting Diode.

E. Electronic Devices

The display device1of each of the above-described embodiments or modified examples can be applied to various electronic devices. The display device1according to the above-described embodiments is particularly suitable for electronic devices that are required to display high-definition images of 2K2K or higher and are required to be compact.

FIG.10is a perspective view showing an outer shape of a head-mounted display300serving as an electronic device.FIG.11is a diagram of an optical configuration of the head-mounted display300shown inFIG.10. InFIG.11, the display device1for the left eye will be denoted as a display device1L, and the display device1for the right eye will be denoted as a display device1R.

As shown inFIG.10, the head-mounted display300includes temples310, a bridge320, a projection optical system301L, a projection optical system301R, and a control unit350. Also, as shown inFIG.11, the head-mounted display300includes the two display devices1. The control unit350includes, for example, a processor and a memory, and controls operations of the two display devices1.

Image light LL formed by the display device1L is radiated to the projection optical system301L. The projection optical system301L includes an optical lens302L and a half mirror303L. The image light LL is radiated toward the half mirror303L via the optical lens302L. Some of the image light LL is reflected by the half mirror303L and is projected to a pupil EY of a wearer of the head-mounted display300. Also, some of the image light LL is transmitted through the half mirror303L. Similarly, image light LR formed by the display device1R is radiated to the projection optical system301R. The projection optical system301R includes an optical lens302R and a half mirror303R. The image light LR is radiated toward the half mirror303L via the optical lens302R. Some of the image light LR is reflected by the half mirror303R and is projected to a pupil EY of the wearer of the head-mounted display300. Also, some of the image light LR is transmitted through the half mirror303R.

The wearer of the head-mounted display300can visually recognize an image formed by the image light LL and the image light LR while visually recognizing an external world image.

The head-mounted display300includes the above-described display devices1and the control unit350. According to the display devices1, deterioration in display quality can be inhibited. Accordingly, the head-mounted display300includes the display devices1, and thus deterioration in display quality of the head-mounted display300can be inhibited.

Also, examples of the electronic device to which the above-described display device is applied include, in addition to the head-mounted display300, an electronic device disposed close to the eyes, such as a digital scope, digital binoculars, a digital still camera, and a video camera. Further, it can be applied as a display unit provided in an electronic device such as a displayer or the like of a mobile phone, a smartphone, a smart watch, a personal digital assistant (PDA), a car navigation device, and an in-vehicle instrument panel. In addition, the display device1is applicable to a light bulb of a projection type projector.

Although the present disclosure has been described above based on the illustrated embodiments and modified examples, the present disclosure is not limited thereto. In addition, the configuration of each part of the present disclosure may be replaced with any configuration that exhibits the same function as in the embodiments described above, or any configuration can be added.