Patent ID: 12253778

DETAILED DESCRIPTION

In order to make objects, technical details and advantages of the embodiments of the present disclosure apparent, the technical solutions of the embodiments will be described in a clearly and fully understandable way in connection with the drawings related to the embodiments of the present disclosure. Apparently, the described embodiments are just a part but not all of the embodiments of the present disclosure. Based on the described embodiments herein, those skilled in the art can obtain other embodiment(s), without any inventive work, which should be within the scope of the disclosure.

Unless otherwise defined, all the technical and scientific terms used in the present disclosure have the same meanings as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms “first,” “second,” etc., which are used in the present disclosure, are not intended to indicate any sequence, amount or importance, but distinguish various components. The terms “comprise,” “comprising,” “include,” “including,” etc., are intended to specify that the elements or the objects stated before these terms encompass the elements or the objects and equivalents thereof listed after these terms, but do not preclude the other elements or objects.

Features such as “parallel”, “perpendicular” and “identical” used in the embodiments of the present disclosure include features such as “parallel”, “perpendicular” and “identical” in the strict sense, as well as “approximately parallel”, “approximately perpendicular” and “approximately identical” and other situations that contain certain errors. Considering the measurement and errors associated with a specific amount of measurement (for example, the limitation of the measurement system), the measurement is represented within an acceptable deviation range for specific values determined by those skilled in the art. For example, “approximately” can mean within one or more standard deviations, or within 10% or 5% of the value. In the case where the amount of a component is not specifically indicated below in the embodiments of the present disclosure, it means that the component may be one or more, or may be understood as at least one. “At least one” means one or more, and “plurality” means at least two. The feature “provided in the same layer” described in the present disclosure refers to two (or more than two) structures, which are provided in the same layer, are formed by the same deposition process and patterned by the same patterning process, and materials of the two structures are the same or different. The “integral structure” in the present disclosure refers to two (or more than two) structures, which are integrated, are formed by the same deposition process and patterned by the same patterning process and are connected to each other, and materials of the two structures are the same or different.

FIG.1is a schematic view of a partial planar structure of a display panel. As illustrated inFIG.1, the display panel includes a display region01and a peripheral region02located around the display region01. The display region01includes a plurality of sub-pixels011and data lines012and gate lines013electrically connected to the sub-pixels011. The peripheral region02includes a pad region021and a pad region022, and pads in the pad region021and pads in the pad region022are respectively electrically connected to different integrated circuits (IC). The pad region021includes pads023electrically connected to the data lines012and pads025electrically connected to synchronization signal lines028, and the pad region022includes pads024electrically connected to the data lines012and pads026electrically connected to the synchronization signal lines028. The data lines012are electrically connected to corresponding pads through connection lines027, and the connection lines027form a fanout region. The connection lines027electrically connected to the pads in the two pad regions021and022form two fanout regions. The pads025in the pad region021are electrically connected to the pads026in the pad region022through the synchronization signal lines028to achieve the synchronization of signals on integrated circuits electrically connected to the pads of the two pad regions021and022, respectively. The sub-pixel011includes a common electrode. In order to ensure the stability of the common electrode inside the display panel, the display panel is further provided with a common signal line029electrically connected to the common electrode and located in the peripheral region02. This common signal line029is electrically connected to a common electrode line surrounding the display region, and the common signal line029is electrically connected to a circuit board through a pad030, for example, the common signal line029is electrically connected to pins provided in a middle region of a flexible circuit board (FPC) through the pad030, and the common signal line029is located between the two fanout regions.

In research, the inventor(s) of the present application found that the common signal line029connecting the common electrode line and the flexible circuit board crosses the synchronization signal lines028connecting the two integrated circuits. For example, in a general display device, the synchronization signal lines connected between two integrated circuits are made of the same metal layer as the gate lines, and the total number of the synchronization signal lines is large, such as more than 10. The common signal line is made of the same metal layer as the data lines, and the common signal line needs to cross all the synchronization signal lines and be electrically connected to the corresponding pad of the flexible circuit board. In the manufacturing process of the display panel, because of the existence of static electricity, electrostatic discharge (ESD) breakdown is likely to occur at overlapping positions of the common signal line and the synchronization signal lines (such as long wires), thus causing a short circuit between the synchronization signal line and the common signal line, and causing the display panel to display abnormally.

The present disclosure provides a display panel, a circuit board and a display device. The display panel includes a base substrate including a display region and a peripheral region. The display panel further includes a first pad region, a second pad region, a third pad region, and a common signal line located in the peripheral region, and a plurality of sub-pixels located in the display region. The first pad region includes at least one first pad, and the at least one first pad is configured to be electrically connected to a first integrated circuit; the second pad region includes at least one second pad, and the at least one second pad is configured to be electrically connected to a second integrated circuit; the third pad region includes a plurality of third pads, the plurality of third pads are configured to be electrically connected to a circuit board, and the third pad region is located on a side of the first pad region and the second pad region away from the display region; at least part of the sub-pixels include a common electrode; the common signal line is electrically connected to the common electrode, the common signal line extends along a first direction, the first pad region and the second pad region are located on both sides of the common signal line in a second direction, and the first direction intersects with the second direction. The display panel further includes at least one first signal line and at least one second signal line, the at least one first pad is electrically connected to a first portion of the plurality of third pads through the at least one first signal line, the at least one second pad is electrically connected to a second portion of the plurality of third pads through the at least one second signal line, and the common signal line is electrically connected to an output terminal of the circuit board through a third portion of the plurality of third pads; the at least one first signal line and the at least one second signal line are configured to be electrically connected to each other through the circuit board and the third pads.

In the display panel provided by the present disclosure, the first signal line and the second signal line are electrically connected to each other through the third pad and the circuit board, thereby avoiding the electrostatic breakdown between the first signal line and the common signal line, and between the second signal line and the common signal line.

The display panel, circuit board and display device provided by the embodiments of the present disclosure will be described below with reference to the drawings.

FIG.2is a schematic view of a partial planar structure of a display panel according to an embodiment of the present disclosure.FIG.3andFIG.5are respectively enlarged views of different regions in a peripheral region illustrated inFIG.2.FIG.4is an enlarged view of a region A illustrated inFIG.3.FIG.6is an enlarged view of a region B illustrated inFIG.4.FIG.7is an enlarged view of a region C illustrated inFIG.5.FIG.8is a schematic view of a common signal line and surrounding structures.FIG.9andFIG.10are schematic enlarged views of two ends of the common signal line, respectively.

As illustrated inFIG.2, the display panel includes a base substrate10, and the base substrate10includes a display region11and a peripheral region12, that is, the display panel includes the display region11and the peripheral region12. For example, the display region11is a region for displaying images, and the peripheral region12is a region not for displaying images. For example, the peripheral region12is located on at least one side of the display region11; and for another example, the peripheral region12surrounds the display region11.

As illustrated inFIG.2, the display panel includes a first pad region100, a second pad region200, and a third pad region300located in the peripheral region12, a plurality of sub-pixels400located in the display region11, and a common signal line420located in the peripheral region12.

As illustrated inFIG.2,FIG.6andFIG.7, the first pad region100includes at least one first pad110, and the at least one first pad110is configured to be electrically connected to a first integrated circuit; and the second pad region200includes at least one second pad210, and the at least one second pad210is configured to be electrically connected to a second integrated circuit.

For example, the first integrated circuit and the second integrated circuit are two different integrated circuits (IC) provided outside the display panel, some pins in the first integrated circuit are configured to be electrically connected to first pads110, and some pins in the second integrated circuit are configured to be electrically connected to second pads210.

For example, the first pad region100includes a plurality of first pads110, and the second pad region200includes a plurality of second pads210. For example, the first pads110in the first pad region100are all electrically connected to the first integrated circuit, and the second pads210in the second pad region200are all electrically connected to the second integrated circuit. The electrical connection between the first pads and the first integrated circuit, and the electrical connection between the second pads and the second integrated circuit are achieved by anisotropic conductive adhesive or welding, which is not limited here. For example, the first integrated circuit and the second integrated circuit may be interchanged.

As illustrated inFIG.2-FIG.5, the third pad region300includes a plurality of third pads310, the plurality of third pads310are configured to be electrically connected to the circuit board, and the third pad region300is located on a side of the first pad region100and the second pad region200away from the display region11.

For example, the circuit board is a structure provided outside the display panel, and some pins of the circuit board are electrically connected to input pins of the first integrated circuit through the third pads310. For example, the circuit board is a flexible printed circuit board (FPC).

As illustrated inFIG.2, the plurality of sub-pixels400include a common electrode410. For example, the common electrode410is a common electrode shared by the plurality of sub-pixels400; for example, the common electrode410can be an entire surface electrode, or can be independent electrodes corresponding to pixel electrodes, and a plurality of independent electrodes are electrically connected together through a connection line; or the common electrode has a strip-shape, each row of sub-pixels corresponds to one common electrode, and the common electrodes corresponding to adjacent rows are electrically connected together through a connection line, etc. The specific shape of the common electrode is not limited.

As illustrated inFIG.2andFIG.3, the common signal line420is electrically connected to the common electrode410, the common signal line420is located in the peripheral region12and extends along a first direction, the first pad region100and the second pad region200are located on both sides of the common signal line420in a second direction, and the first direction intersects with the second direction.

For example, the figures schematically illustrate that the first direction is the Y direction, the second direction is the X direction, but they are not limited thereto, and the first direction and the second direction can be interchanged. For example, the first direction is perpendicular to the second direction, but not limited thereto, and an included angle between the first direction and the second direction is 60-120 degrees, such as 70-110 degrees, such as 80-100 degrees, such as 85-95 degrees.

As illustrated inFIG.2-FIG.5, the display panel further includes at least one first signal line510and at least one second signal line520, the at least one first pad110is electrically connected to a first portion311of the plurality of third pads310through the at least one first signal line510, the at least one second pad210is electrically connected to a second portion of the plurality of third pads310through the at least one second signal line520, and the common signal line420is electrically connected to an output terminal of the circuit board through a third portion313of the plurality of third pads310. For example, the first portion311and the second portion312of the third pads310are respectively located on both sides of the third portion313of the third pads310. For example, the total number of pads included in at least one of the first portion311, the second portion312and the third portion313of the third pads310is greater than 1. For example, the total number of pads included in the first portion311of the third pads310is equal to the total number of pads included in the second portion312of the third pads310, and the total number of pads included in the first portion311of the third pads310and the total number of pads included in the second portion312of the third pads310are both greater than the total number of pads included in the third portion313of the third pads310.

As illustrated inFIG.2, the at least one first signal line510and the at least one second signal line520are configured to be electrically connected to each other through the third pads310and the circuit board. For example, the third pads310are configured to be electrically connected to pins of the circuit board, thereby achieving that the first signal line is electrically connected to the second signal line through the third pads and the circuit board. For example, the first signal line510and the second signal line520are not directly connected to each other on the display panel.

In the display panel provided by the present disclosure, the first signal line and the second signal line are electrically connected to each other through the third pads and the circuit board, thereby avoiding the electrostatic breakdown between the first signal line and the common signal line, and between the second signal line and the common signal line.

For example, the total number of the first signal lines510is the same as the total number of the second signal lines520, and the plurality of first signal lines510and the plurality of second signal lines520achieve one-to-one electrical connection through the third pads310and the circuit board. For example, the total number of first signal lines510is greater than ten, and the total number of second signal lines520is greater than ten.

In some examples, as illustrated inFIG.2-FIG.9, in a direction perpendicular to the base substrate10, such as a direction perpendicular to the XY plane, both the at least one first signal line510and the at least one second signal line520do not overlap with the common signal line420. For example, each first signal line510does not overlap with the common signal line420, and each second signal line520does not overlap with the common signal line420.

In some examples, as illustrated inFIG.2, the signal configured to be transmitted on the first signal line510and the signal configured to be transmitted on a second signal line520corresponding to the first signal line510are the same signal, and the same signal includes at least one of a synchronization signal and a gamma signal. The above-mentioned “a second signal line520corresponding to the first signal line510” refers to a second signal line520electrically connected to the first signal line510through the third pads310and the circuit board.

For example, the first signal line510and the second signal line520may also be referred to as synchronization signal lines. For example, the synchronization signal transmitted by the first signal line510and the second signal line520is a SYNC (synchronized signals between master and slave) signal, the synchronization and consistency of two integrated circuits (IC) used to drive the display panel to display are achieved through the electrical connection between the first signal line510and the second signal line520, for example, enabling control signals, such as a data signal, output from timing controllers (TCON) integrated in the two ICs respectively, consistent, and thus achieving normal display of two partial regions of the display panel corresponding to the two ICs.

For example, the gamma signal transmitted by the first signal line510and the second signal line520can be GMHN, GMLN, GMHP (Gamma voltage link when use cascade function) or GMLP, where H represents high voltage, L represents low voltage, P represents positive voltage, and N represents negative voltage. Gamma voltage is used to compensate the non-linear perception of light by the human eye through the light and dark changes on the display panel, thereby forming a linear transformation in the brain; the conversion of the corresponding driving voltage according to the transmittance versus voltage (VT) curve of the display panel, which is usually the basis for the internal analog-to-digital conversion of the source driver; and the use of Gamma voltage is to first select a black point voltage or a white point voltage (configured to determine a liquid crystal deflection range) and the common electrode voltage (Vcom), and then adjust the voltage of middle gray scales. The Gamma signal is transmitted in the first signal line and the second signal line connected between the two ICs to achieve the consistency of the Gamma signal compensation in the two ICs, and then achieve the normal display of two partial regions of the display panel corresponding to the two ICs.

For example, the IC supports a single mode and a cascade mode to correspond to different resolutions of the display panel, and the above-mentioned two ICs are regarded as including a master IC and a slave IC. The two ICs are cascaded to each other by connecting synchronization signal lines between the master IC and the slave IC, so that the two ICs become equivalent to an extended IC, and the extended IC is configured to transmit signals to the above-mentioned two partial regions.

In a general display panel, a common signal line electrically connected to a circuit board overlaps with synchronization signal lines connecting two ICs in a direction perpendicular to the base substrate. Compared with such a display panel, in the display panel provided by the present disclosure, the first signal line and the second signal line are electrically connected to each other through the third pads and the circuit board, so that the common signal line, the first signal line and the second signal line do not overlap with each other in the direction perpendicular to the base substrate, thereby avoiding the common signal line from crossing the synchronization signal lines connecting different ICs without increasing the cost, thereby avoiding the problem of short circuit caused by static electricity in the process and improving the product quality and product yield.

In some examples, as illustrated inFIG.2andFIG.3, at least one kind of the at least one first signal line510and the at least one second signal line520is provided in the same layer as the common signal line and is insulated from the common signal line. For example, the first signal line510and the second signal line520are provided in the same layer, and the first signal line510, the second signal line520and the common signal line420are all provided in the same layer.

For example, as illustrated inFIG.2andFIG.10, gate lines550electrically connected to the sub-pixels400are also provided in the display region11, and the first signal line510, the second signal line520, and the common signal line420are structures provided in the same layer as the gate lines550.

For example, as illustrated inFIG.2-FIG.7, the first pad110and the first signal line510are structures provided in the same layer, and the second pad210and the second signal line520are structures provided in the same layer. For example, the first pad110and the first signal line510can be an integral structure, and the second pad210and the second signal line520can be an integral structure. For example, the third pad310and the first pad110are structures provided in different layers.

In some examples, as illustrated inFIG.4andFIG.5, at least one signal line of the at least one first signal line510and the at least one second signal line520includes a signal line portion501extending along the second direction and a signal line portion502extending along a third direction, the line width of the signal line portion501extending along the second direction is smaller than the line width of the signal line portion502extending along the third direction, and both the first direction and the second direction intersect with the third direction. For example, the line width of the signal line portion501of the first signal line510is smaller than the line width of the signal line portion502of the first signal line510. For example, the line width of the signal line portion501of the second signal line520is smaller than the line width of the signal line portion502of the second signal line520.

Compared with the case where a general synchronization signal line only extends along the second direction and have a small line width, in the display panel provided by the present disclosure, each first signal line and each second signal line includes not only a portion extending along the second direction but also a portion extending along the third direction, and by setting the line width of the portion extending along the third direction to be greater than the line width of the portion extending along the second direction, it is beneficial to reduce the resistance of each first signal line and the resistance of each second signal line to improve electrical characteristics of the first signal line and the second signal line.

For example, as illustrated inFIG.4-FIG.7, the plurality of first signal lines510includes signal lines with different line widths of signal line portions501, such as signal lines511and signal lines512; the plurality of second signal lines520include signal lines with different line widths of signal line portions501, such as signal lines521and signal lines522; and the signal line511is electrically connected to the signal line521, the signal line512is electrically connected to the signal line522, the signal line511and the signal line521are configured to transmit a SYNC signal, and the signal line512and the signal line522are configured to transmit a Gamma signal. For example, the total number of the signal lines511is 15, the total number of the signal lines512is 4, and along the direction indicated by the arrow in the Y direction, the signals transmitted by 4 signal lines512are GMLN, GMHN, GMHP and GMLP in sequence. For example, the signal lines512are located on a side of the signal lines511away from the display region.

For example, as illustrated inFIG.6, the total number of the first pads110is a plurality, and the plurality of first pads110is arranged in three rows to save space of the first pad region100in the second direction. For example, the signal lines511of the plurality of first signal lines510are electrically connected to three rows of first pads110, and the signal lines512are only electrically connected to one row of first pads110of the three rows of first pads110farthest from the display region.

For example, as illustrated inFIG.6, two adjacent rows of first pads110are shifted from each other to facilitate electrical connection between the first pads110in the middle row and the first signal lines510, for example, a first signal line510electrically connected to a first pad110located in the second row passes through a spacing between adjacent first pads110located in the first row.

The above-mentioned “two adjacent rows of first pads110are shifted from each other” means that at least part of at least one first pad in the second row is opposite to the spacing between adjacent first pads in the first row. For example, the distance staggered by two adjacent rows of first pads in the X direction is not greater than one first pad pitch.

For example, as illustrated inFIG.6andFIG.7, the distribution of the second pads210and the connection relationship between the second pads210and the second signal lines520can be the same as the distribution of the first pads110and the connection relationship between the first pads110and the first signal line510, and will not be repeated here.

For example, as illustrated inFIG.4, the ratio of line widths of the signal line portions502of different first signal lines510is 0.8-1.2, or 0.9-1.1, or 1. For example, the different first signal lines510further include signal line portions503extending along the first direction, and the ratio of line widths of the signal line portions503of the different first signal lines510is 0.8-1.2, or 0.9-1.1, or 1. In the display panel provided by the present disclosure, the difference of the line widths between the signal line portions, extending along the third direction, of the different first signal lines is set to be small, and the difference of the line widths between the signal line portions, extending along the first direction, of the different first signal lines is set to be small, which facilitates the corresponding electrical connection between different first signal lines and corresponding third pads.

For example, as illustrated inFIG.5, the ratio of line widths of the signal line portions502of different second signal lines520is 0.8-1.2, or 0.9-1.1, or 1. For example, the different second signal lines520further include signal line portions503extending along the first direction, and the ratio of line widths of the signal line portions503of the different second signal lines520is 0.8-1.2, or 0.9-1.1, or 1. In the display panel provided by the present disclosure, the difference of the line widths between the signal line portions, extending along the third direction, of the different second signal lines is set to be small, and the difference of the line widths between the signal line portions, extending along the first direction, of the different second signal lines is set to be small, which facilitates the corresponding electrical connection between different second signal lines and corresponding third pads.

In some examples, as illustrated inFIG.2andFIG.8, the common signal line420is electrically connected to at least one third pad310. As illustrated inFIG.4andFIG.5, each first signal line510is electrically connected to one third pad310, and each second signal line520is electrically connected to one third pad310.

For example, the first pad110, the second pad210and the third pad310all extend along the first direction, the length of the first pad110is the same as the length of the second pad210, and the length of the third pad310is greater than the length of the first pad110.

For example, as illustrated inFIG.4andFIG.5, the total number of the first portions311of the third pads310is the same as the total number of the first signal lines510, and the first portions311of the third pads310are electrically connected to the first signal lines510in a one-to-one correspondence. For example, the total number of the second portions312of the third pads310is the same as the total number of the second signal lines520, and the second portions312of the third pads310are electrically connected to the second signal lines520in a one-to-one correspondence. Of course, the embodiments of the present disclosure are not limited thereto, one first signal line may be connected to a plurality of third pads correspondingly, and one second signal line may be connected to a plurality of third pads correspondingly.

For example, the total number of the first portions311of the third pads310is the same as the total number of the second portions312of the third pads310. For example, the total number of the third portions313of the third pads310is less than the total number of the first portions311of the third pads310.

In some examples, as illustrated inFIG.2,FIG.3andFIG.9, a plurality of first dummy pads320is provided between the third pad310electrically connected to the common signal line420and the third pad310electrically connected to the first signal line510, and provided between the third pad310electrically connected to the common signal line420and the third pad310electrically connected to the second signal line520. The first dummy pad320is a pad that is not electrically connected to any structure on the display panel.

For example, as illustrated inFIG.2andFIG.3, the first dummy pads320are provided in the same layer as the third pads310. For example, the total number of the first dummy pads320is greater than the total number of the first portions311of the third pads310. For example, the total number of the first dummy pads320is greater than the total number of the third portions313of the third pads310. The etching uniformity of the third pads is improved by providing the first dummy pad between the first portion of the third pad and the third portion of the third pad, and between the second portion of the third pad and the third portion of the third pad.

In some examples, as illustrated inFIG.6andFIG.7, the first pad region100further includes at least one second dummy pad120, and the second pad region200further includes at least one third dummy pad220. For example, the first pad region100includes a first pad110electrically connected to the first signal line510and a second dummy pad120not electrically connected to the first signal line510; and the second pad region200includes a second pad210electrically connected to the second signal line520and a third dummy pad220not electrically connected to the second signal line520. The second dummy pad120is a pad that is not electrically connected to any structure on the display panel. For example, the total number of the second dummy pads120is a plurality, and the second dummy pad includes a portion between the first row of first pads110and a portion between the second row of first pads110. By providing the second dummy pads, it is possible to avoid the interference of adjacent first signal lines and improve the etching uniformity of the first pad region; similarly, the third dummy pad is a pad that is not electrically connected to any structure on the display panel, and providing a plurality of third dummy pads in the second pad region can avoid interference of adjacent second signal lines and improve the etching uniformity of the second pad region.

For example, the second dummy pad120is provided in the same layer as the first pad110, or in a different layer from the first pad110; and the third dummy pad220is provided in the same layer as the second pad210, or in a different layer from the second pad210.

In some examples, as illustrated inFIG.2,FIG.4toFIG.7, the at least one first signal line510and the at least one second signal line520are distributed symmetrically relative to a straight line located between the first pad region100and the second pad region200and extending along the first direction. For example, the first signal line510and the second signal line520electrically connected to each other are distributed symmetrically relative to a straight line located between the first pad region100and the second pad region200and extending along the first direction. For example, the first portion311of the third pad310and the second portion312of the third pad310are distributed symmetrically relative to the third portion313of the third pad310.

In some examples, as illustrated inFIG.2-FIG.5andFIG.8-FIG.9, a first dummy structure group810is provided between the common signal line420and at least one kind of the at least one first signal line510and the at least one second signal line520; and a straight line extending along the second direction passes through orthographic projections of at least one kind of the at least one first signal line510and the at least one second signal line520, the first dummy structure group810, and the common signal line420on the base substrate10. The first dummy structure group810is not electrically connected to any structure on the display panel. Providing the first dummy structure group can improve the distribution uniformity of the film layer on the display panel, and ensure the uniformity of pattern etching of the first signal line and the second signal line during the manufacturing process.

For example, the first dummy structure group810is provided between the first signal line510and the common signal line420and between the second signal line520and the common signal line420, and the straight line extending along the second direction passes through orthographic projections of the first dummy structure group810, the common signal line420, the first signal line510and the second signal line520on the base substrate10.

In some examples, as illustrated inFIG.2-FIG.5andFIG.8-FIG.9, in the direction perpendicular to the base substrate10, the first signal line510, the second signal line520and the common signal line420do not overlap with the first dummy structure group810.

In some examples, as illustrated inFIG.2-FIG.5andFIG.8-FIG.9, the first dummy structure group810includes a plurality of first dummy structure rows8100arranged along the first direction, and each first dummy structure row8100includes a plurality of first dummy structures811arranged along the second direction. For example, adjacent first dummy structure rows8100are aligned. Of course, the embodiments of the present disclosure are not limited thereto, and the first dummy structure group may also include a plurality of dummy structure lines arranged along the first direction.

For example, as illustrated inFIG.4, andFIG.8-FIG.9, each first dummy structure811is a strip-shaped structure extending along the first direction. For example, the length of the strip-shaped structure is relatively short, and for example, the length of the strip-shaped structure along the first direction is smaller than the line width of the signal line portion503, extending along the third direction, of the first signal line510; and for another example, the length of the strip-shaped structure along the first direction is smaller than the length of the first pad110, and the length of the strip-shaped structure along the first direction is smaller than the length of the third pad310.

For example, the plurality of first dummy structures811include some first dummy structures811in the same layer as the common signal line420and some first dummy structures811in a different layer from the common signal line420. For example, the first dummy structures811in the same layer as the common signal line420and the first dummy structures811in a different layer from the common signal line420are alternately arranged in the second direction.

The first dummy structure group provided in the present disclosure includes a plurality of first dummy structures, each of which is provided as a strip-shaped structure with a short length to avoid electrostatic discharge (ESD) caused by charge accumulation on the first dummy structures.

In some examples, as illustrated inFIG.2-FIG.3, the maximum length of a portion of at least one kind of the at least one first signal line510and the at least one second signal line520extending along the second direction is smaller than the maximum dimension of the first dummy structure group810in the second direction. For example, the maximum length of the portions of respective first signal lines510extending along the second direction and the maximum length of the portions of respective second signal lines520extending along the second direction are both smaller than the maximum dimension of one row of first dummy structure rows8100in the second direction.

In some examples, as illustrated inFIG.2-FIG.3,FIG.8andFIG.10, a second dummy structure group820is provided between the first dummy structure group810and the display region11; and a straight line extending along the second direction passes through orthographic projections of the second dummy structure group820and the common signal line420on the base substrate10, and the straight line does not pass through orthographic projections of the first signal line510and the second signal line520on the base substrate10.

For example, with a straight line where a signal line portion501, extending along the second direction, of the first signal lines510on the side closest to the display region10is located as a boundary, the dummy structures provided between the common signal line420and the first signal line510are divided into the first dummy structure group810and the second dummy structure group820. The orthographic projection of the first dummy structure811of the first dummy structure group810on a plane perpendicular to the X direction overlaps with the orthographic projection of the first signal line510on the plane perpendicular to the X direction, and the orthographic projection of the second dummy structure821of the second dummy structure group820on the plane perpendicular to the X direction does not overlap with the orthographic projection of the first signal line510on the plane perpendicular to the X direction.

In some examples, as illustrated inFIG.2-FIG.3,FIG.8andFIG.10, the second dummy structure group820includes a plurality of second dummy structure rows8200arranged along the first direction, and each second dummy structure row8200includes a plurality of second dummy structures821arranged along the second direction. For example, adjacent second dummy structure rows8200are aligned. Of course, the embodiments of the present disclosure are not limited thereto, and the first dummy structure group may also include a plurality of dummy structure lines arranged along the first direction.

For example, as illustrated inFIG.4,FIG.8andFIG.10, each second dummy structure821is a strip-shaped structure extending along the first direction. For example, the length of the strip-shaped structure is relatively short, for example, the length of the strip-shaped structure along the first direction is smaller than the length of the first pad110, and the length of the strip-shaped structure along the first direction is smaller than the length of the third pad310.

For example, the plurality of second dummy structures821include some second dummy structures821in the same layer as the common signal line420and some second dummy structures821in a different layer from the common signal line420. For example, the second dummy structures821in the same layer as the common signal line420and the second dummy structures821in a different layer from the common signal line420are alternately arranged in the second direction, for example, in the same layer as the source-drain metal layer.

The second dummy structure group provided in the present disclosure includes a plurality of second dummy structures, each of which is provided as a strip-shaped structure with a short length to avoid electrostatic discharge (ESD) caused by charge accumulation on the second dummy structures.

In some examples, as illustrated inFIG.8-FIG.10, the common signal line420includes a hollow portion421. For example, the hollow portion421includes a plurality of openings.

The display panel provided by the present disclosure may be a liquid crystal display panel, and the liquid crystal display panel includes a liquid crystal layer and a seal adhesive surrounding the liquid crystal layer. By providing a hollow portion in the seal adhesive covered by the common signal line, on the one hand, the light transmittance at the position of the common signal line can be increased to ensure the curing of the seal adhesive covered by the common signal line; on the other hand, electrostatic discharge (ESD) can be avoided in the process of manufacturing the display panel in the case where the common signal line is provided as a large piece of metal.

For example, as illustrated inFIG.8-FIG.10, the common signal line420further includes a first block structure422located on a side of the hollow portion421close to the third pad310, and the first block structure422is electrically connected to the third pad310.

For example, as illustrated inFIG.8-FIG.10, the first block structure422is provided as a bent structure to achieve that edges of both sides of the first block structure422extending along the first direction can be aligned with edges on both sides of the third pad310electrically connected to the first block structure422, thereby achieving a better electrical connection between the common signal line and the third pad, and also preventing the common signal line from interfering with the first dummy pad.

For example, as illustrated inFIG.2andFIG.10, the display panel further includes a circle of common electrode line430surrounding the display region11, and the common electrode line430is electrically connected to the third pad310. For example, the common electrode line430is electrically connected to a common electrode410, and the common signal line420is electrically connected to the common electrode410through the common electrode line430.

For example, as illustrated inFIG.2, the display panel further includes a circle of common compensation line (Vcom compensation)440surrounding the common electrode lines430, and a common feedback line (Vcom feedback)450located between the common compensation line440and the common electrode line430, and the common compensation line440is electrically connected to the common electrode line430. For example, both the common compensation line440and the common feedback line450are both electrically connected to the third pad310. For example, the common compensation line440is directly connected to the common electrode line430to improve the stability of the common voltage. For example, the common feedback line450is directly connected to the middle of the common electrode line430to compensate the common voltage of the upper half of the display panel.

For example, as illustrated inFIG.2,FIG.8andFIG.10, the common signal line420further includes a second block portion423located on a side of the hollow portion421close to the display region11, and the second block portion423is electrically connected to the common electrode line430. For example, the width (dimension along the second direction) of the second block portion423is smaller as it gets closer to the display region11to prevent the common signal line from interfering with the fanout regions on both sides (described later).

FIG.11is an enlarged view of a region D illustrated inFIG.10,FIG.12is an enlarged view of a partial region illustrated inFIG.4, andFIG.13is an enlarged view of a partial region illustrated inFIG.5.

In some examples, as illustrated inFIG.2,FIG.10andFIG.11, the display panel further includes a plurality of signal transmission lines530electrically connected to at least part of the plurality of sub-pixels400. For example, the signal transmission lines530include a data line.

In some examples, as illustrated inFIG.2,FIG.4-FIG.7andFIG.12-FIG.13, the display panel further includes a fourth pad region600and a fifth pad region700, the fourth pad region600is located on a side of the first pad region100away from the common signal line420, and the fifth pad region700is located on a side of the second pad region200away from the common signal line420. The fourth pad region600includes a plurality of fourth pads610, and the plurality of fourth pads610are configured to electrically connect an output terminal of the first integrated circuit to at least part of the plurality of signal transmission lines530. The fifth pad region700includes a plurality of fifth pads710, and the plurality of fifth pads710are configured to electrically connect an output terminal of the second integrated circuit to at least part of the plurality of signal transmission lines530. A fourth portion314of the plurality of third pads310is configured to electrically connect an input terminal of the first integrated circuit to the output terminal of the circuit board, and a fifth portion315of the plurality of third pads310is configured to electrically connect an input terminal of the second integrated circuit to the output terminal of the circuit board.

For example, as illustrated inFIG.2,FIG.4-FIG.7andFIG.12-FIG.13, the first pad110and the fourth pad610are electrically connected to the same integrated circuit, and the second pad210and the fifth pad710are electrically connected to the same integrated circuit. For example, the shape and dimension of the fourth pad610are the same as the shape and dimension of the first pad110. For example, the shape and dimension of the fifth pad710is the same as the shape and dimension of the second pad210. For example, at least part of the fourth pads610are provided in the same layer as at least part of the first pads110, and at least part of the fifth pads710are provided in the same layer as at least part of the second pads210.

For example, the output terminal of the first integrated circuit is electrically connected to the fourth pad610to transmit a data signal to the signal transmission line530in one region, and the output terminal of the second integrated circuit is electrically connected to the fifth pad710to transmit a data signal to the signal transmission line530in another region.

For example, as illustrated inFIG.12andFIG.13, a sixth pad620is further provided between the fourth pad610and the third pad310, and the input terminal of the first integrated circuit is electrically connected to the output terminal of the circuit board through the sixth pad620, a wire560connecting the sixth pad620and the fourth portion314of the third pads310, and the fourth portion314of the third pads310. For example, a seventh pad720is further provided between the fifth pad710and the third pad310, and the input terminal of the second integrated circuit is electrically connected to the output terminal of the circuit board through the seventh pad720, a wire560connecting the seventh pad720and the fifth portion315of the third pads310, and the fifth portion315of the third pads310.

For example, as illustrated inFIG.12, one end of each wire560is connected to at least one sixth pad620, and the other end of each wire560is connected to at least one third pad310. For example, one end of a first wire560closest to the first pad110is connected to three sixth pads620, and the other end of the first wire560is connected to two third pads310; one end of a second wire560is connected to ten sixth pads620, and the other end of the second wire560is connected to two third pads310; one end of a third wire560is connected to two sixth pads620, and the other end of the third wire560is connected to one third pad310; and one end of a fourth wire560is connected to one sixth pad620, and the other end of the fourth wire560is connected to one third pad310. The total number of connections between the wires and the sixth pads and the third pads is determined according to product requirements. Similarly, as illustrated inFIG.13, one end of each wire560is connected to at least one seventh pad720, and the other end of each wire560is connected to at least one third pad310.

For example, as illustrated inFIG.6-FIG.7andFIG.12-FIG.13, a third dummy structure group830is further provided between the fourth pad610and the sixth pad620and between the fifth pad710and the seventh pad720. For example, a straight line extending along the second direction passes through orthographic projections of the third dummy structure group830, the first signal line510and the second signal line520on the base substrate. The third dummy structure group is not electrically connected to any structure on the display panel, and the third dummy structure group is provided to improve the distribution uniformity of the film layer on the display panel, and ensure the uniformity of pattern etching of the first pad, the second pad, the fifth pad and the sixth pad during the manufacturing process.

For example, as illustrated inFIG.6-FIG.7andFIG.12-FIG.13, the third dummy structure group830includes a plurality of third dummy structure rows arranged along the first direction, and each third dummy structure row includes a plurality of third dummy structures831along the second direction. For example, adjacent third dummy structure rows are aligned.

For example, as illustrated inFIG.6-FIG.7andFIG.12-FIG.13, each third dummy structure831is a strip-shaped structure extending along the first direction. For example, the length of the strip-shaped structure is relatively short, for example, the length of the strip-shaped structure along the first direction is smaller than the length of any one of the first pad110, the second pad210, the third pad310, the fourth pad610and the fifth pad710.

The third dummy structure group provided in the present disclosure includes a plurality of third dummy structures, each of which is provided as a strip-shaped structure with a short length to avoid electrostatic discharge (ESD) caused by charge accumulation on the third dummy structures.

For example, as illustrated inFIG.4andFIG.5, dummy pads330are further provided between the fourth portion314of the third pads310and the first portion311of the third pads310, and between the fifth portion315of the third pads310and the second portion312of the third pads310. For example, the dummy pad330is not electrically connected to any structure of the display panel.

In some examples, as illustrated inFIG.2-FIG.8andFIG.10-FIG.13, the display panel further includes a plurality of connection lines540located in the peripheral region12and configured to electrically connect at least part of the signal transmission lines530to the plurality of fourth pads610, and electrically connect at least part of the signal transmission lines530to the plurality of fifth pads710. For example, some of the signal transmission lines530are electrically connected to the output terminals of the first integrated circuit through the connection lines540and the fourth pads610, and some other of the signal transmission lines530are electrically connected to the output terminals of the second integrated circuit through the connection lines540and the fifth pads710.

In some examples, as illustrated inFIG.2-FIG.8andFIG.10-FIG.13, a part of the plurality of connection lines540connected to the plurality of fourth pads610forms a first fanout region541, a part of the plurality of connection lines540connected to the plurality of fifth pads710forms a second fanout region542, and the common signal line420, the first signal line510and the second signal line520are all located between the first fanout region541and the second fanout region542.

For example, the common signal line420is located between two integrated circuits. For example, both the first pads110and the second pads210are located between the first fanout region541and the second fanout region542.

In some examples, as illustrated inFIG.10andFIG.11, the display panel further includes an electrostatic discharge structure8300electrically connected to the connection line540, and located between the signal transmission line530and the first pad region100and between the signal transmission line530and the second pad region200. For example, the electrostatic discharge structure8300is located between the signal transmission line530and the second dummy structure group820. For example, the electrostatic discharge structure8300is located between the signal transmission line530and the first fanout region541and between the signal transmission line530and the second fanout region542. Optionally, the electrostatic discharge structure includes a plurality of transistors, the plurality of transistors are electrically connected to each other, one end of the electrostatic discharge structure is electrically connected to the data line of the display panel, and the other end of the electrostatic discharge structure is connected to a common electrode line or an electrostatic discharge ring, which is not limited thereto.

In some examples, as illustrated inFIG.6andFIG.7, the plurality of fourth pads610and the plurality of fifth pads710both include a plurality of first signal output pads671and a plurality of second signal output pads672, and the plurality of first signal output pads671and the plurality of second signal output pads672are located in different layers; and the plurality of first signal output pads671and the plurality of second signal output pads672are arranged in a plurality of rows of output pad rows670, each row of output pad rows670includes the first signal output pads671and the second signal output pads672arranged alternately along the second direction, and adjacent rows of output pad rows670are offset with respect to each other in the second direction. For example, the ratio of the shifted dimension of the adjacent rows of output pad rows670in the second direction to the pitch of one pad is 0.5-1.5, or 0.6-1.4, or 0.7-1.3, or 0.8-1.2, or 0.9-1.1.

By providing the pads of the fourth pads and the fifth pads as output pads located in different layers, it is beneficial to improve the compactness of arrangement of pads and reduce the interference between pads provided in the same layer; and distributing the adjacent rows of output pad rows in a shifted manner in the second direction can facilitate providing of positions of connection lines connected to respective pads in the output pad row.

For example, as illustrated inFIG.6andFIG.7, a plurality of first signal output pads671and a plurality of second signal output pads672included in the fourth pads610are arranged into three output pad rows670; a connection line540electrically connected to a pad in the second output pad row670passes through an interval between the first signal output pad671and the second signal output pad672provided adjacent to each other in the first output pad row670; and a connection line540electrically connected to a pad in the third output pad row670passes through the interval between the first signal output pad671and the second signal output pad672provided adjacent to each other in the first output pad row670, and an interval between the first signal output pad671and the second signal output pad672provided adjacent to each other in the second output pad row670.

For example, one of the first signal output pad671and the second signal output pad672is provided in the same layer as the data line, and the other of the first signal output pad671and the second signal output pad672is provided in the same layer as the gate line.

In some examples, as illustrated inFIG.6andFIG.7, the plurality of connection lines540include a plurality of first connection lines543electrically connected to the plurality of first signal output pads671and a plurality of second connection lines544electrically connected to the plurality of second signal output pads672, the plurality of first connection lines543are provided in the same layer as the plurality of first signal output pads671, the plurality of second connection lines544are provided in the same layer as the plurality of second signal output pads672, and the plurality of first connection lines543and the plurality of second connection lines544are arranged alternately along the second direction.

For example, the first connection lines543provided in the same layer as the first signal output pads671are formed in the same patterning process as the first signal output pads671, and the second connection lines544provided in the same layer as the second signal output pads672are formed in the same patterning process as the second signal output pads672.

FIG.14is a schematic view of a partial structure of a circuit board according to another embodiment of the present disclosure. As illustrated inFIG.14, the circuit board includes a first pin region0100, a second pin region0200and a third pin region0300arranged along the first direction, and the second pin region0200and the third pin region0300are located on both sides of the first pin region0100; each pin region includes a plurality of pins; and the circuit board further includes at least one connection lead0400, and at least one pin0201in the second pin region0200is electrically connected to at least one pin0301in the third pin region0300through at least one connection lead0400. For example, N pins0201in the second pin region0200are electrically connected to N pins0301in the third pin region0300in a one-to-one correspondence through N connection leads0400.

The circuit board provided by the present disclosure can be cooperated with the above-mentioned display panel by electrically connecting at least one pin in the second pin region to at least one pin in the third pin region through at least one connection lead, so as to electrically connect the first signal line in the display panel to the second signal line, so that the display panel has a better display effect.

FIG.15is a schematic view of a partial structure of a display device according to yet another embodiment of the present disclosure. As illustrated inFIG.15, the display device includes the display panel illustrated in any one ofFIG.2-FIG.13and a circuit board1000, for example, the circuit board1000is the circuit board illustrated inFIG.14.

As illustrated inFIG.15, the circuit board1000includes at least one connection lead0400, and a first pin region0100, a second pin region0200and a third pin region0300arranged along the second direction, the second pin region0200and the third pin region0300are located on both sides of the first pin region0100, and each pin region includes a plurality of first pins0123; and at least one first pin0123in the second pin region0200is electrically connected to at least one first pin0123in the third pin region0300through the at least one connection lead0400. A first portion311of the third pad310is bound to the first pin0123of the first pin region0100, a second portion312of the third pad310is bound to the first pin0123of the second pin region0200, and a third portion313of the third pad310is bound to the first pin0123of the first pin region0100.

In the display device provided by the embodiments of the present disclosure, the first signal line and the second signal line in the display panel are electrically connected to each other through a circuit board, thereby avoiding electrostatic breakdown between the first signal line and the common signal line, and the second signal line and the common signal line without additionally increasing the manufacturing cost of the display panel.

For example, as illustrated inFIG.14, the first pin region0100, the second pin region0200and the third pin region0300are arranged along the U direction. For example, the U direction inFIG.14is the same as the second direction illustrated inFIG.2, but is not limited thereto.

For example, as illustrated inFIG.14, the first pin region0100includes a plurality of pins0101, the second pin region0200includes a plurality of pins0201, and the third pin region0300includes a plurality of pins0301.

For example, as illustrated inFIG.2-FIG.15, the pins0101in the first pin region0100are configured to be bound to the third portion313of the third pad310to achieve that the circuit board provides a common signal to the common signal line420.

In some examples, as illustrated inFIG.14, the connection lead0400is configured to transmit at least one of a synchronization signal and a gamma signal.

For example, as illustrated inFIG.2-FIG.15, the first signal line510is electrically connected to the second signal line520through the first portion311of the third pads310, the pin0201in the second pin region0200, the connection lead0400, the pin0301in the third pin region0300, and the second portion312of the third pads310.

In some examples, as illustrated inFIG.15, the display device further includes a first integrated circuit2000and a second integrated circuit3000, the first integrated circuit2000includes at least one second pin2001, and the second integrated circuit3000includes at least one third pin3001. At least one second pin2001is bound to at least one first pad110, and at least one third pin3001is bound to at least one second pad210.

For example, the first signal line510is electrically connected to the first integrated circuit2000through the third pad310, and the second signal line520is electrically connected to the second integrated circuit3000through the third pad310.

For example, as illustrated inFIG.2-FIG.15, the synchronization signal lines that need to be connected between the first integrated circuit2000and the second integrated circuit3000, that is, the first signal line510and the second signal line520are respectively connected to the circuit board (FPC) at the glass end from the left end and the right end of the common signal line420, and the synchronization signal lines on the display panel are not connected to each other, so that the common signal line can be avoided from crossing the synchronization signal lines; and in order to achieve the normal display of the display panel, it is still necessary to connect the synchronization signal lines of the first integrated circuit2000and the second integrated circuit3000, for example, the synchronization signal lines transmitting the same signal are electrically connected together through leads on a flexible printed circuit assembly (FPCA). For example, after respective integrated circuits are bound to the circuit board, the connection between the first signal line and the second signal line between the first integrated circuit and the second integrated circuit is achieved through the leads on the circuit board, so that the display panel can display normally.

For example, as illustrated inFIG.14, the total number of pins0101included in the first pin region0100is less than the total number of pins0201included in the second pin region0200, or the total number of pins0101included in the first pin region0100is less than the total number of pins0301included in the third pin region0300. For example, the total number of the pins0201is the same as the total number of the pins0301.

For example, as illustrated inFIG.14, the pins0101,0201, and0301have the same shape and dimension. For example, a plurality of pins0101, a plurality of pins0201and a plurality of pins0301are arranged at equal intervals in the U direction.

For example, the total number of pins0101is two, for example, two pins0101are bound to four third pads310on the display panel.

For example, as illustrated inFIG.2-FIG.14, the first pin region0100further includes dummy pins0102, and the dummy pins0102are bound to the first dummy pads320.

For example, as illustrated inFIG.14, the pin0101is located in the middle of the first pin region0100, and the dummy pins0102are located on both sides of the pin0101. For example, some of the dummy pins0102are located between the pin0101and the pin0201, and some other of the dummy pins0102are located between the pin0101and the pin0301.

In some examples, as illustrated inFIG.14, the connection leads0400are distributed symmetrically relative to the first lead region0100to prevent different connection leads from intersecting with each other.

For example, as illustrated inFIG.14, different connection leads0400are provided in the same layer. For example, the connection lead0400and the first pin0123are provided in the same layer. For example, the connection lead0400and the first pin0123connected thereto are formed as an integral structure.

For example,FIG.14schematically illustrates 10 connection leads0400, and these 10 connection leads are electrically connected to the signal lines511for transmitting the SYNC signal illustrated inFIG.6. For example, the connection lead0400further includes a partial lead electrically connected to the signal line512for transmitting the Gamma signal illustrated inFIG.6.

The following statements should be noted:

(1) In the accompanying drawings of the embodiments of the present disclosure, the drawings involve only the structure(s) in connection with the embodiment(s) of the present disclosure, and other structure(s) can be referred to common design(s).

(2) In case of no conflict, features in one embodiment or in different embodiments can be combined.

What have been described above are only specific implementations of the present disclosure, the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be based on the protection scope of the claims.