Patent ID: 12191419

MODE FOR CARRYING OUT THE INVENTION

Next, modes for carrying out the present disclosure (hereinafter, referred to as embodiments) will be described with reference to the drawings. In the following drawings, the same or similar parts are denoted by the same or similar reference signs. Furthermore, the embodiments will be described in the following order.1. First Embodiment2. Second Embodiment3. Third Embodiment4. Fourth Embodiment5. Fifth Embodiment6. Sixth Embodiment7. Seventh Embodiment8. Eighth Embodiment9. Ninth Embodiment

1. First Embodiment

[Configuration of Semiconductor Element]

FIG.1is a diagram illustrating a configuration example of a semiconductor device according to a first embodiment of the present disclosure.FIG.1is a diagram illustrating a configuration example of a semiconductor device1. The semiconductor device1inFIG.1includes a semiconductor element100and a control circuit2. Note thatFIG.1is a diagram for explaining an outline of configurations of the semiconductor device1and the semiconductor element100.

The semiconductor element100is a semiconductor element including a compound semiconductor layer. The semiconductor element100inFIG.1is formed as a two-terminal element, and one end is grounded and the other end is connected to the control circuit2via a signal line3. The control circuit2generates a control signal based on the ground potential and supplies the control signal to the semiconductor element100via the signal line3. Note that the configuration of the semiconductor device1inFIG.1is not limited to this example. For example, it is also possible to adopt a configuration in which one end of the semiconductor element100is set to a potential other than the ground potential.

The semiconductor element100inFIG.1includes a silicon substrate110, an electrode121, a first compound semiconductor layer140, a second compound semiconductor layer150, and a second electrode170. The electrode121and the compound semiconductor layer (the first compound semiconductor layer140and the second compound semiconductor layer150) are disposed on the silicon substrate110. The electrode121is disposed on a front surface of the silicon substrate110. The compound semiconductor layer is disposed on a back surface of the silicon substrate110that is a surface different from the front surface.

The silicon substrate110is a substrate constituted by Si. For the silicon substrate110, a single crystal Si wafer or the like can be used. Furthermore, the silicon substrate110can have an n-type conductivity type, for example.

The first compound semiconductor layer140is a compound semiconductor layer formed on the silicon substrate110. For the first compound semiconductor layer140, for example, a compound semiconductor containing gallium (Ga) and phosphorus (P) can be used. For example, gallium phosphide (GaP) can be used as the first compound semiconductor layer140. Hereinafter, the first compound semiconductor layer140is assumed to be a semiconductor constituted by GaP. The first compound semiconductor layer140containing GaP can be disposed as a buffer layer when the second compound semiconductor layer150described later is formed on the silicon substrate110. Furthermore, the first compound semiconductor layer140can have i-type and n-type conductivity types.

The second compound semiconductor layer150is a compound semiconductor layer stacked on the first compound semiconductor layer140. The second compound semiconductor layer150has a predetermined film thickness, for example, a film thickness of 1 μm or more, and is a semiconductor layer that generates an interaction with light, such as photoelectric conversion. For the second compound semiconductor layer150, for example, a compound semiconductor containing Ga, arsenic (As), P, and nitrogen (N) can be used. For example, a GaAsPN semiconductor can be used as the second compound semiconductor layer150. The GaAsPN semiconductor is a semiconductor having a small difference in lattice constant from Si constituting the silicon substrate110and capable of absorbing visible light. The second compound semiconductor layer150can have an i-type conductivity type. Furthermore, the second compound semiconductor layer150can have an n-type conductivity type. Note that the second compound semiconductor layer150preferably has a film thickness of 3 μm or more. This is because sufficient light absorption can be performed, and efficiency of photoelectric conversion is improved.

The electrode121is an electrode disposed on a surface of the silicon substrate110different from a surface on which the first compound semiconductor layer140is formed. The electrode121controls movement of charges between the silicon substrate110and the second compound semiconductor layer150via the first compound semiconductor layer140. The electrode121can be constituted by, for example, metal such as copper (Cu) or aluminum (Al), a semiconductor, or polycrystalline silicon.

The second electrode170is an electrode disposed adjacent to the second compound semiconductor layer150. The second electrode170is an electrode in which a voltage for controlling movement of charges of the first compound semiconductor layer140is applied between the electrode121and the second electrode170. The second electrode170can be constituted by a member similar to the electrode121. Furthermore, when the semiconductor element100is used as an optical semiconductor, the second electrode170can be constituted by a transparent electrode such as indium tin oxide (ITO).

As described above, the first compound semiconductor layer140containing GaP can be used as a buffer layer. This is because the first compound semiconductor layer140containing GaP has a small difference in lattice constant from Si constituting the silicon substrate110. Furthermore, the second compound semiconductor layer150can be formed on the silicon substrate110by epitaxial growth. However, during this epitaxial growth, N contained in the second compound semiconductor layer150reacts with the silicon substrate110to change properties of a surface of the silicon substrate110. By disposing the first compound semiconductor layer140, it is possible to prevent adhesion of N contained in the second compound semiconductor layer150to the surface of the silicon substrate110and to prevent change in the properties of the surface of the silicon substrate110. Furthermore, by disposing the first compound semiconductor layer140, the first compound semiconductor layer140absorbs a difference in thermal expansion coefficient between the silicon substrate110and the second compound semiconductor layer150, and stress at the time of forming the second compound semiconductor layer150can be reduced.

The first compound semiconductor layer140preferably has a film thickness not exceeding a critical film thickness of the silicon substrate110. Here, the critical film thickness is a film thickness at which the first compound semiconductor layer140can absorb a difference in lattice constant from Si as accumulation of internal stress of the first compound semiconductor layer140. When the first compound semiconductor layer140having a film thickness exceeding the critical film thickness is formed, the first compound semiconductor layer140cannot absorb a difference in lattice constant between the silicon substrate110and the first compound semiconductor layer140, and crystal defects (dislocations) due to misfit occur in the first compound semiconductor layer140. As the critical film thickness of the first compound semiconductor layer140, a film thickness of 20 nm can be applied.

When the semiconductor element100is applied to a light receiving element, light is made incident on the second compound semiconductor layer150via the second electrode170. The incident light generates charges due to a photoelectric effect in the second compound semiconductor layer150. In this case, the electrode121controls movement of the generated charges. Specifically, the control circuit2generates a control signal for moving the charges generated in the second compound semiconductor layer150to the silicon substrate110, and supplies the control signal to the electrode121. Therefore, a control signal is applied between the electrode121and the second electrode170. This control voltage is applied as a bias voltage to the first compound semiconductor layer140and the second compound semiconductor layer150. The charges generated in the second compound semiconductor layer150are moved by this control signal. For example, in a case where a positive control voltage with respect to the ground potential is applied to the electrode121, electrons out of charges generated by photoelectric conversion move to the silicon substrate110via the first compound semiconductor layer140. Meanwhile, holes out of the charges generated by photoelectric conversion move to the second electrode170.

In a case where the semiconductor element100is applied to a light emitting element, light generated when charges injected into the second compound semiconductor layer150disappear due to recombination is emitted to the outside via the second electrode170. A control signal for controlling movement of charges to be recombined for light emission in the second compound semiconductor layer150is supplied to the electrode121. Specifically, a drive voltage for injecting charges into the second compound semiconductor layer150is generated by the control circuit2and applied to the electrode121.

In any case, in the semiconductor element100, charges move via the first compound semiconductor layer140. A difference in bandgap between the first compound semiconductor layer140and each of the silicon substrate110and the second compound semiconductor layer150is a problem. This is because a barrier generated by the difference in band gap inhibits movement of charges.

[Band Structure of Semiconductor Element]

FIGS.2A and2Bare diagrams illustrating an example of a band structure of a semiconductor element according to an embodiment of the present disclosureFIGS.2A and2Bare diagrams illustrating an example of a band structure of the semiconductor element100. InFIGS.2A and2B, a region301represents a region of the second compound semiconductor layer150, a region302represents a region of the first compound semiconductor layer140, and a region303represents a region of the silicon substrate110.

FIG.2Ais a diagram illustrating a band structure in a case where no control voltage is applied. A band gap of the second compound semiconductor layer150in the region301is approximately 1.5 eV, and a band gap of the silicon substrate110in the region303is 1.1 eV. Meanwhile, a band gap of the first compound semiconductor layer140in the region302is 2.2 eV, which is wider than the band gaps of the second compound semiconductor layer150and the silicon substrate110. Therefore, this acts as a barrier when electrons in a conduction band move from the second compound semiconductor layer150(region301) to the silicon substrate110(region303), and inhibits the movement. Therefore, a moving speed also decreases.

FIG.2Bis a diagram illustrating an example in a case where a control voltage is applied. When a positive control voltage with respect to the second electrode170is applied to the electrode121and a bias voltage is supplied thereto, the potential changes and the region302becomes thin. When a photoelectric effect is generated by incident light304incident on the region301, electrons305out of generated charges pass through the region302by a tunneling effect and move to the silicon substrate110in the region303. This tunneling effect makes movement of the electrons305possible. Note that holes306out of the charges generated by the photoelectric effect move inside the region301and reach the second electrode170. Such a tunneling effect can be obtained by reducing the film thickness of the first compound semiconductor layer140in the region302. Specifically, by setting the film thickness of the first compound semiconductor layer140in the region302to 50 nm or less, a remarkable tunneling effect can be generated. Note that as a mechanism of the above-described tunneling effect, a mechanism such as direct tunneling or fowler-nordheim (FN) tunneling is considered and the mechanism is not limited to one tunneling. In any case, the thin film thickness of the first compound semiconductor layer140is a factor of the mechanism of the tunneling effect.

As described above, even in a case where the first compound semiconductor layer140containing GaP having a wide band gap is disposed, by reducing the film thickness of the first compound semiconductor layer140and applying a control voltage via the electrode121, an influence of an energy barrier generated by the difference in band gap can be reduced.

The semiconductor element100can be manufactured through the following steps. The silicon substrate110is formed into an n-type conductivity type, and a surface on which the first compound semiconductor layer140is to be disposed is subjected to surface treatment and thermal cleaning. Next, the first compound semiconductor layer140is formed on the silicon substrate110. The first compound semiconductor layer140can be formed by, for example, molecular beam epitaxy (MBE), atomic layer deposition (ALD), or metal organic chemical vapor deposition (MOCVD). The second compound semiconductor layer150is stacked on the first compound semiconductor layer140. The second compound semiconductor layer150can be formed by epitaxial growth. The second electrode170is stacked on the second compound semiconductor layer150. The second electrode170can be formed by, for example, sputtering. Next, the electrode121is formed on the silicon substrate119. The electrode121can be formed by, for example, sputtering. Through the above steps, the semiconductor element100can be manufactured.

As described above, in the semiconductor element100according to the first embodiment of the present disclosure, the first compound semiconductor layer140is disposed as a buffer layer, and the electrode121is disposed on the silicon substrate110. By applying, to the electrode121, a control voltage for controlling movement of charges from the second compound semiconductor layer150to the silicon substrate110, it is possible to reduce a barrier when charges are move from the second compound semiconductor layer150to the silicon substrate110. This makes it possible to improve movement of charges.

2. Second Embodiment

The semiconductor element100according to the above-described first embodiment includes a two-layered compound semiconductor. Meanwhile, a semiconductor element100according to a second embodiment of the present disclosure is different from that of the above-described first embodiment in including a three-layered compound semiconductor.

[Configuration of Semiconductor Element]

FIG.3is a diagram illustrating a configuration example of a semiconductor device according to the second embodiment of the present disclosure.FIG.3is a diagram illustrating a configuration example of a semiconductor device1and the semiconductor element100similarly toFIG.1. The semiconductor element100inFIG.3is different from the semiconductor element100inFIG.1in further including a p-type third compound semiconductor layer160.

The third compound semiconductor layer160is a compound semiconductor layer disposed between a second compound semiconductor layer150and a second electrode170. For the third compound semiconductor layer160, a compound semiconductor containing Ga, As, P, and N can be used similarly to the second compound semiconductor layer150. Furthermore, the third compound semiconductor layer160can have a conductivity type different from the second compound semiconductor layer150. For example, the third compound semiconductor layer160can have a p-type. By disposing the third compound semiconductor layer160adjacent to the i-type second compound semiconductor layer150, the pin-junction semiconductor element100can be formed. A depletion layer can be formed in a region of the second compound semiconductor layer150, and recombination of charges generated by a photoelectric effect can be suppressed.

Furthermore, in the semiconductor element100inFIG.3, the second compound semiconductor layer150can have an n-type conductivity type. In this case, the pn-junction semiconductor element100can be formed, and a depletion layer is formed at an interface between the second compound semiconductor layer150and the third compound semiconductor layer160.

Furthermore, as the third compound semiconductor layer160, a compound semiconductor layer whose band gap has become wider by changing a mixed crystal ratio of GaAsPN constituting the second compound semiconductor layer150can also be used. In this case, the semiconductor element100has a double hetero structure.

The third compound semiconductor layer160has a relatively thin film thickness. This is because the third compound semiconductor layer160needs to transmit incident light, and an influence of a contact interface with the electrode170is reduced. Specifically, the third compound semiconductor layer160can have a film thickness of about 100 nm or less.

Since the configuration of the semiconductor element100other than this is similar to the configuration of the semiconductor element100described in the first embodiment of the present disclosure, description thereof will be omitted.

As described above, the semiconductor element100according to the second embodiment of the present disclosure forms a depletion layer by disposing the third compound semiconductor layer160having a conductivity type different from the second compound semiconductor layer150. Therefore, recombination of charges generated by a photoelectric effect can be reduced, and conversion efficiency can be improved.

3. Third Embodiment

In the semiconductor element100according to the above-described second embodiment, the second electrode170is directly grounded. Meanwhile, a semiconductor element100according to a third embodiment of the present disclosure is different from that of the above-described second embodiment in being grounded via a second electrode170and an electrode penetrating a silicon substrate110.

[Configuration of Semiconductor Element]

FIG.4is a diagram illustrating a configuration example of a semiconductor device according to the third embodiment of the present disclosure.FIG.4is a diagram illustrating a configuration example of a semiconductor device1and the semiconductor element100similarly toFIG.3. The semiconductor element100inFIG.4is different from the semiconductor element100inFIG.3in that a through electrode122and an electrode123are further disposed.

The electrode123is an electrode disposed adjacent to a surface of the silicon substrate110. The electrode123is grounded on the surface of the silicon substrate110. The electrode123can be connected to the ground line in common with a control circuit2. Note that the configuration of the semiconductor device1inFIG.4is not limited to this example. For example, it is also possible to adopt a configuration in which the electrode123is set to a potential other than the ground potential.

The through electrode122is an electrode disposed so as to penetrate the silicon substrate110and a compound semiconductor layer, and is an electrode disposed between a second electrode170and the electrode123. The through electrode122can be formed by disposing an insulating film (not illustrated) on an inner wall of a through hole formed in the silicon substrate110and the compound semiconductor layer and embedding a conductive material such as metal therein. The through electrode122can be formed in the silicon substrate110and the compound semiconductor layer after the second electrode170is formed. Alternatively, the second electrode170can be formed after the through electrode122is formed in the silicon substrate110and the compound semiconductor layer.

Since the configuration of the semiconductor element100other than this is similar to the configuration of the semiconductor element100described in the third embodiment of the present disclosure, description thereof will be omitted.

As described above, the semiconductor element100according to the third embodiment of the present disclosure electrically connects the second electrode170via the through electrode122. The semiconductor element100according to the third embodiment can be connected to the ground line in common with the control circuit2to simplify wiring with the control circuit2.

4. Fourth Embodiment

The semiconductor element100according to the above-described first embodiment is formed as an optical semiconductor element. Meanwhile, in a fourth embodiment of the present disclosure, an example in which a semiconductor element100is applied to an imaging element will be described.

[Configuration of Imaging Element]

FIG.5is a diagram illustrating a configuration example of a semiconductor device according to the fourth embodiment of the present disclosure. A semiconductor device1inFIG.5constitutes an imaging device. The semiconductor device1includes a pixel array unit10, a vertical drive unit20, a column signal processing unit30, and a control unit40.

In the pixel array unit10, pixels200are arranged in a two-dimensional lattice shape. Here, the pixel200generates an image signal corresponding to emitted light. The pixel200includes a photoelectric conversion unit that generates charges corresponding to emitted light. Furthermore, the pixel200further includes an image signal generation circuit. The image signal generation circuit generates an image signal based on charges generated by the photoelectric conversion unit. The generation of an image signal is controlled by a control signal generated by the vertical drive unit20described later. In the pixel array unit10, signal lines11and12are arranged in an XY matrix shape. The signal line11is a signal line that transmits a control signal of the image signal generation circuit in the pixel200, is arranged for each row of the pixel array unit10, and is commonly wired to the pixels200arranged in each row. The signal line12is a signal line that transmits an image signal generated by the image signal generation circuit of the pixel200, is arranged for each column of the pixel array unit10, and is commonly wired to the pixels200arranged in each column.

The vertical drive unit20generates a control signal of the image signal generation circuit of the pixel200. The vertical drive unit20transmits the generated control signal to the pixel200via the signal line11inFIG.5. The column signal processing unit30processes the image signal generated by the pixel200. The column signal processing unit30processes the image signal transmitted from the pixel200via the signal line12inFIG.5. The processing in the column signal processing unit30corresponds to, for example, analog-to-digital conversion for converting an analog image signal generated in the pixel200into a digital image signal. The image signal processed by the column signal processing unit30is output as an image signal of the semiconductor device1. The control unit40controls the entire semiconductor device1. The control unit40controls the semiconductor device1by generating and outputting a control signal for controlling the vertical drive unit20and the column signal processing unit30. The control signal generated by the control unit40is transmitted to the vertical drive unit20and the column signal processing unit30by signal lines41and42, respectively.

The photoelectric conversion unit, the image signal generation circuit, the vertical drive unit20, and the like can be formed in a silicon substrate119described later. Furthermore, for the vertical drive unit20and the like, a circuit constituted by a complementary metal oxide semiconductor (CMOS) can be adopted.

[Circuit Configuration of Pixel]

FIG.6is a diagram illustrating an example of a circuit configuration of a pixel according to the fourth embodiment of the present disclosure.FIG.6is a circuit diagram illustrating a configuration of the pixel200. The pixel200inFIG.6includes a photoelectric conversion unit101, a first charge holding unit103, a second charge holding unit102, and MOS transistors104to109. Furthermore, the signal line11including signal lines OFG, TX, TR, RST, and SEL and the signal line12are wired to the pixel200. The signal lines OFG, TX, TR, RST, and SEL constituting the signal line11are signal lines for transmitting a control signal of the pixel200. These signal lines are connected to gates of the MOS transistors. By applying a voltage equal to or higher than a threshold between a gate and a source to a MOS transistor via these signal lines, the MOS transistor can be made conductive. Meanwhile, the signal line12transmits an image signal generated by the pixel200. Furthermore, a power supply line Vdd is wired to the pixel200, and power is supplied to the pixel200. Note that the first charge holding unit103, the second charge holding unit102, and the MOS transistors104to109constitute the image signal generation circuit described inFIG.5.

An anode of the photoelectric conversion unit101is grounded, and a cathode of the photoelectric conversion unit101is connected to each of sources of the MOS transistors104and105. A drain of the MOS transistor104is connected to the power supply line Vdd, and a gate of the MOS transistor104is connected to the signal line OFG. A drain of the MOS transistor105is connected to a source of the MOS transistor106and one end of the second charge holding unit102. The other end of the second charge holding unit102is grounded. A gate of the MOS transistor105is connected to the signal line TX, and a gate of the MOS transistor106is connected to the signal line TR. A drain of the MOS transistor106is connected to a source of the MOS transistor107, a gate of the MOS transistor108, and one end of the first charge holding unit103. The other end of the first charge holding unit103is grounded. A gate of the MOS transistor107is connected to the signal line RST. Drains of the MOS transistors107and108are commonly connected to the power supply line Vdd, and a source of the MOS transistor108is connected to a drain of the MOS transistor109. A source of the MOS transistor109is connected to the signal line12, and a gate of the MOS transistor109is connected to the signal line SEL.

The photoelectric conversion unit101generates and holds charges corresponding to emitted light as described above. As the photoelectric conversion unit101, a photodiode can be used.

The MOS transistor104is a transistor that resets the photoelectric conversion unit101. By applying a power supply voltage to the photoelectric conversion unit101, the MOS transistor104discharges charges held in the photoelectric conversion unit101to the power supply line Vdd and resets the photoelectric conversion unit101. The reset of the photoelectric conversion unit101by the MOS transistor104is controlled by a signal transmitted by the signal line OFG.

The MOS transistor105is a transistor that transfers charges generated by photoelectric conversion of the photoelectric conversion unit101to the second charge holding unit102. The charge transfer by the MOS transistor105is controlled by a signal transmitted by the signal line TX.

The second charge holding unit102is a capacitor that holds the charges transferred by the MOS transistor105.

The MOS transistor106is a transistor that transfers the charges held in the second charge holding unit102to the first charge holding unit103. The charge transfer by the MOS transistor106is controlled by a signal transmitted by the signal line TR.

The MOS transistor108is a transistor that generates a signal based on charges held in the first charge holding unit103. The MOS transistor109is a transistor that outputs the signal generated by the MOS transistor108as an image signal to the signal line12. The MOS transistor109is controlled by a signal transmitted by the signal line SEL.

The MOS transistor107is a transistor that resets the first charge holding unit103by discharging the charges held in the first charge holding unit103to the power supply line Vdd. The reset by the MOS transistor107is controlled by a signal transmitted by the signal line RST.

Generation of an image signal in the pixel200inFIG.6can be performed as follows. First, the MOS transistor104is made conductive to reset the photoelectric conversion unit101. Charges generated by photoelectric conversion after the reset are accumulated in the photoelectric conversion unit101. After a lapse of a predetermined time, the MOS transistors106and107are made conductive to reset the second charge holding unit102. Next, the MOS transistor105is made conductive. Therefore, charges generated in the photoelectric conversion unit101are transferred to and held in the second charge holding unit102.

The operation from the reset of the photoelectric conversion unit101to the charge transfer by the MOS transistor105is simultaneously performed in all the pixels200arranged in the pixel array unit10. That is, global reset, which is simultaneous reset in all the pixels200, and simultaneous charge transfer in all the pixels200are executed. Therefore, global shutter is implemented. Note that a period from the reset of the photoelectric conversion unit101to the charge transfer by the MOS transistor105corresponds to an exposure period.

Next, the MOS transistor107is made conductive again to reset the first charge holding unit103. Next, the MOS transistor106is made conductive, and charges held in the second charge holding unit102are transferred to and held in the first charge holding unit103. Therefore, the MOS transistor108generates an image signal corresponding to the charges held in the first charge holding unit103. Next, by making the MOS transistor109conductive, the image signal generated by the MOS transistor108is output to the signal line12. This operation from the reset of the first charge holding unit103to the output of the image signal is sequentially performed for each row of the pixel array unit10in which the pixels200are arranged. By outputting image signals in the pixels200in all the rows of the pixel array unit10, a frame that is an image signal for one screen is generated and output from the semiconductor device1.

By generating and outputting an image signal in the pixel200in parallel with the above-described exposure period, time required for imaging and transfer of the image signal can be shortened. Furthermore, by simultaneously performing exposure in all the pixels200in the pixel array unit10, it is possible to prevent occurrence of frame distortion and to improve image quality. As described above, the second charge holding unit102is used to temporarily hold charges generated by the photoelectric conversion unit101when global shutter is performed.

[Configuration of Pixel]

FIG.7is a diagram illustrating a configuration example of the pixel according to the fourth embodiment of the present disclosure.FIG.7is a diagram illustrating a configuration example of the pixel200. The pixel200inFIG.7includes a silicon substrate119, a wiring region120, a first compound semiconductor layer140, a second compound semiconductor layer150, a second electrode170, a color filter191, a planarizing film192, and an on-chip lens193.

The silicon substrate119is a substrate constituted by Si, and is a semiconductor substrate in which diffusion regions of semiconductor elements included in the image signal generation circuit of the pixel200, the vertical drive unit20, the column signal processing unit30, and the control unit40described inFIG.5are formed. The diffusion regions of the semiconductor elements such as the image signal generation circuit are disposed in a well region formed in the silicon substrate110. For convenience, the silicon substrate110inFIG.7is assumed to constitute a p-type well region. By forming an n-type semiconductor region in the p-type well region, the diffusion regions of the semiconductor elements such as the image signal generation circuit can be formed. InFIG.7, the vertical drive unit20described inFIG.5, and the photoelectric conversion unit101, the second charge holding unit102, and the MOS transistor105described inFIG.6are illustrated as examples of the semiconductor elements.

An n-type semiconductor region111of the silicon substrate119inFIG.7is a semiconductor region corresponding to the silicon substrate110described inFIG.1. Note that the semiconductor element including the n-type semiconductor region111, the first compound semiconductor layer140, the second compound semiconductor layer150, and the second electrode170inFIG.7constitutes the photoelectric conversion unit101, and corresponds to the semiconductor element100described inFIG.1.

An n-type semiconductor region112of the silicon substrate119inFIG.7constitutes the second charge holding unit102. Furthermore, the n-type semiconductor regions111and112and a gate electrode124described later constitute the MOS transistor105. That is, the n-type semiconductor regions111and112correspond to a source region and a drain region of the MOS transistor105, respectively, and the p-type well region between the n-type semiconductor regions111and112corresponds to a channel region. Furthermore, the signal line11inFIG.7corresponds to the signal line TX inFIG.6.

The wiring region120is a region where wiring for transmitting a signal to an element such as the MOS transistor105is formed. The wiring region120includes a wiring layer128and an insulating layer129. The wiring layer128transmits a signal to an element. The wiring layer128can be constituted by metal such as copper (Cu). The insulating layer129insulates the wiring layer128. The insulating layer129can be constituted by, for example, silicon oxide (SiO2). The wiring region120further includes the gate electrode124of the MOS transistor105. The insulating layer129between the gate electrode124and the silicon substrate119constitutes a gate insulating film. The gate electrode124inFIG.7is disposed adjacent to the silicon substrate119via the gate insulating film.

The color filter191is an optical filter that transmits an incident light beam having a predetermined wavelength among light beams incident on the pixel200. As the color filter191, one of three types of color filters191that transmit red light, green light, and blue light can be disposed in the pixel200.

The planarizing film192is a film that planarizes a surface. The planarizing film192inFIG.7is stacked on the color filter191and planarizes a surface on which the on-chip lens193described later is to be formed.

The on-chip lens193is a lens that condenses incident light. The on-chip lens193inFIG.7is formed in a hemispherical shape and condenses incident light on the photoelectric conversion unit101.

Configurations of the first compound semiconductor layer140, the second compound semiconductor layer150, and the second electrode170are similar to those of the semiconductor element100inFIG.1, and therefore description thereof will be omitted.

Incident light incident through the on-chip lens193, the color filter191, and the second electrode170causes photoelectric conversion in the second compound semiconductor layer150to generate charges. As described inFIG.6, when the second charge holding unit102is reset, a positive power supply voltage is applied to the second charge holding unit102. Therefore, the potential of the n-type semiconductor region112inFIG.7becomes positive by the reset. When a control signal for making the MOS transistor105conductive is applied to the gate electrode124via the signal line TX, the n-type semiconductor regions111and112are made conductive with each other, and the potential of the n-type semiconductor region111also becomes positive. Therefore, the n-type semiconductor region111is reset to a depletion state.

The positive voltage of the n-type semiconductor region111is applied to the second compound semiconductor layer150via the first compound semiconductor layer140. Charges (electrons) generated by photoelectric conversion in the second compound semiconductor layer150move to the n-type semiconductor region111via the first compound semiconductor layer140. When a control signal is applied to the gate electrode124, the voltage of the n-type semiconductor region111changes, and an electric field for moving charges of the compound semiconductor layer changes. That is, the electric field of the compound semiconductor layer or the like is indirectly controlled by the control signal applied to the gate electrode124, and movement of charges is controlled.

As described above, the gate electrode124controls movement of charges between the n-type semiconductor region111and the second compound semiconductor layer150via the first compound semiconductor layer140. Note that the gate electrode124is an example of an electrode described in claims. The n-type semiconductor region111is an example of a silicon substrate described in claims. The vertical drive unit20is an example of a control circuit described in claims.

Furthermore, the pixel200adopts a configuration in which the second compound semiconductor layer150performs photoelectric conversion of incident light, and a semiconductor element formed in the silicon substrate119holds charges generated by photoelectric conversion and transferred to the silicon substrate119and generates an image signal. Therefore, an existing processing circuit formed in the silicon substrate119and constituted by a CMOS or the like can be applied to the semiconductor device1. Furthermore, since the second compound semiconductor layer150performs photoelectric conversion of incident light, a photoelectric conversion unit does not need to be disposed in the silicon substrate119. Therefore, the size of the second charge holding unit102or the like disposed in the silicon substrate119can be increased, and charge accumulation capacity can be improved.

Note that the configuration of the pixel200is not limited to this example. For example, the pixel200can also adopt a configuration in which incident light having a wavelength that is not absorbed by the second compound semiconductor layer150, such as infrared light, is photoelectrically converted by a photoelectric conversion unit disposed in the silicon substrate110.

[Method for Manufacturing Semiconductor Device]

FIGS.8A,8B,80,9A,9B, and9Care diagrams illustrating an example of a method for manufacturing the semiconductor device according to the fourth embodiment of the present disclosure.FIGS.8A,8B,8C,9A,9B, and9Care diagrams illustrating an example of a process for manufacturing the semiconductor device1.

First, the first compound semiconductor layer140and the second compound semiconductor layer150are sequentially stacked on a back surface of the silicon substrate119. The first compound semiconductor layer140can be formed by MBE. Furthermore, the second compound semiconductor layer150can be formed by epitaxial growth (FIG.8A).

Next, the silicon substrate119is turned upside down (FIG.8B), a p-type well region is formed in the silicon substrate119, and the n-type semiconductor regions111and112are formed. This can be performed by ion implantation (FIG.8C).

Next, a gate insulating film is formed on a front surface of the silicon substrate119, and the gate electrode124is formed. Next, the insulating layer129and the wiring layer128(not illustrated) are disposed to form the wiring region120(FIG.9A).

Next, the silicon substrate119is turned upside down again, and the second electrode170is stacked on the second compound semiconductor layer150(FIG.9B).

Next, the color filter191and the planarizing film192are stacked on the second electrode170. Thereafter, the on-chip lens193is formed (FIG.9C). Through the above steps, the semiconductor device1can be manufactured.

Note that a low-temperature process can also be adopted for the step of epitaxial growth of the second compound semiconductor layer150. At this time, the following manufacturing process can also be adopted. A step of forming a diffusion region (FIG.8C) and a step of forming the wiring region120(FIG.9A) are performed on the silicon substrate119. Next, the silicon substrate119is turned upside down, and a step of forming the first compound semiconductor layer140and the second compound semiconductor layer150(FIG.8A) is performed.

As described above, in the semiconductor device1according to the fourth embodiment of the present disclosure, movement of charges generated in the second compound semiconductor layer150is controlled by a control signal applied to the gate electrode124of the MOS transistor105formed in the silicon substrate119. Transfer of charges generated by photoelectric conversion is performed via the first compound semiconductor layer140, and inhibition of movement of charges at the time of transfer can be reduced. High-speed imaging of the semiconductor device1formed as an imaging element is possible.

5. Fifth Embodiment

In the pixel200according to the above-described fourth embodiment, the p-type well region is disposed in the region of the silicon substrate119at a boundary between the pixels200. Meanwhile, a pixel200according to a fifth embodiment of the present disclosure is different from that of the above-described fourth embodiment in including a separation layer.

[Configuration of Imaging Element]

FIG.10is a diagram illustrating a configuration example of a pixel according to the fifth embodiment of the present disclosure. The pixel200inFIG.10is different from the pixel200inFIG.7in that a separation layer118is disposed in a silicon substrate119.

The separation layer118is disposed in the silicon substrate119at a boundary between the pixels200, and surrounds and separates a portion of the silicon substrate119of the pixel200. The separation layer118is constituted by, for example, an insulating substance such as SiO2and separates the adjacent pixels200from each other. By disposing the separation layer118, movement of charges between the adjacent pixels200can be prevented, and occurrence of crosstalk can be reduced. The separation layer118can be formed by embedding SiO2or the like in a groove (trench) formed in the silicon substrate119. Note that the separation layer118inFIG.10illustrates an example formed in a shape penetrating the silicon substrate119.

Note that the configuration of the pixel200is not limited to this example. For example, the pixel200can adopt a configuration including the separation layer118having a shape not penetrating the silicon substrate119.

Since the configuration of the semiconductor element100other than this is similar to the configuration of the semiconductor element100described in the fourth embodiment of the present disclosure, description thereof will be omitted.

As described above, in the semiconductor device1according to the fifth embodiment of the present disclosure, by disposing the separation layer118in the silicon substrate119of the pixel200, an influence of crosstalk from the adjacent pixel200can be reduced.

6. Sixth Embodiment

The pixel200according to the above-described fourth embodiment uses the MOS transistor105in which the gate electrode124is disposed on a surface of the silicon substrate119. Meanwhile, a pixel200according to a sixth embodiment of the present disclosure is different from that of the above-described fourth embodiment in including a MOS transistor105formed as a vertical transistor.

[Configuration of Imaging Element]

FIG.11is a diagram illustrating a configuration example of a pixel according to the sixth embodiment of the present disclosure. The pixel200inFIG.11is different from the pixel200inFIG.7in that the MOS transistor105formed as a vertical transistor is disposed and a gate electrode125is disposed instead of the gate electrode124.

The vertical transistor inFIG.11is a MOS transistor that transfers charges in a thickness direction of a silicon substrate119. The gate electrode125is formed so as to be embedded in a region from a surface of the silicon substrate119to an n-type semiconductor region111. Furthermore, the gate electrode125is disposed adjacent to an n-type semiconductor region112. Note that a gate insulating film is disposed between the gate electrode125and the silicon substrate119. When a control signal is applied to the gate electrode125, a channel is formed in a p-type well region adjacent to the gate electrode125between n-type semiconductor regions111and112, and charges are transferred. By disposing the MOS transistor105formed as a vertical transistor, charges can be easily transferred from the n-type semiconductor region111disposed on a back surface side of the silicon substrate119. As compared withFIG.7, the shape of the n-type semiconductor region111can be simplified.

Since the configuration of the semiconductor element100other than this is similar to the configuration of the semiconductor element100described in the fourth embodiment of the present disclosure, description thereof will be omitted.

As described above, in the semiconductor device1according to the sixth embodiment of the present disclosure, by disposing the MOS transistor105formed as a vertical transistor in the pixel200, the shape of the n-type semiconductor region111can be simplified.

7. Seventh Embodiment

In the pixel200according to the above-described fourth embodiment, the second electrode170is disposed. Meanwhile, a pixel200according to a seventh embodiment of the present disclosure is different from that of the above-described fourth embodiment in using a charge accumulation region of a second compound semiconductor layer150formed by disposing a fixed charge film as a second electrode.

[Configuration of Imaging Element]

FIG.12is a diagram illustrating a configuration example of a pixel according to the seventh embodiment of the present disclosure. The pixel200inFIG.12is different from the pixel200inFIG.7in that a fixed charge film180is disposed instead of the second electrode170.

The fixed charge film180is constituted by a dielectric having fixed charges. The fixed charge film180is disposed adjacent to a second compound semiconductor layer150, and forms a charge accumulation layer in the second compound semiconductor layer150by its own fixed charges. This charge accumulation layer can be used as a second electrode. Furthermore, since the charge accumulation layer is formed, a surface level of the second compound semiconductor layer150is pinned, and dark current can also be reduced. The fixed charge film180can be constituted by, for example, aluminum oxide (Al2O3).

Since the configuration of the semiconductor element100other than this is similar to the configuration of the semiconductor element100described in the fourth embodiment of the present disclosure, description thereof will be omitted.

As described above, in the semiconductor device1according to the seventh embodiment of the present disclosure, the fixed charge film180is disposed in the pixel200, and the charge accumulation layer formed in the second compound semiconductor layer150is used as a second electrode. Therefore, pinning of an interface level of the second compound semiconductor layer150is performed, and the second electrode170can be omitted.

8. Eighth Embodiment

In the pixel200according to the above-described seventh embodiment, the fixed charge film180is disposed. Meanwhile, a pixel200according to an eighth embodiment of the present disclosure is different from that of the above-described seventh embodiment in that a fixed charge film180is also used for separating a second compound semiconductor layer150.

[Configuration of Imaging Element]

FIG.13is a diagram illustrating a configuration example of a pixel according to the eighth embodiment of the present disclosure. The pixel200inFIG.13is different from the pixel200inFIG.12in that a separation unit181is disposed in the second compound semiconductor layer150.

The separation unit181surrounds and separates the second compound semiconductor layer150. The separation unit181is disposed in the second compound semiconductor layer150at a boundary between the pixels200to separate the adjacent pixels200from each other. The separation unit181inFIG.13represents an example of a separation unit constituted by a fixed charge film. The separation unit181can be formed by forming a trench in the second compound semiconductor layer150and embedding the fixed charge film180in the trench. By disposing the separation unit181, movement of charges from the second compound semiconductor layer150of the adjacent pixel200can be prevented, and crosstalk can be reduced.

Since the configuration of the semiconductor element100other than this is similar to the configuration of the semiconductor element100described in the seventh embodiment of the present disclosure, description thereof will be omitted.

As described above, in the semiconductor device1according to the eighth embodiment of the present disclosure, by disposing the separation unit181in the second compound semiconductor layer150, crosstalk from the adjacent pixel200can be reduced.

9. Ninth Embodiment

The pixel200according to the above-described eighth embodiment uses the separation unit181constituted by a fixed charge film. Meanwhile, a pixel200according to a ninth embodiment of the present disclosure is different from that of the above-described eighth embodiment in using a separation unit constituted by a third compound semiconductor layer160.

[Configuration of Imaging Element]

FIG.14is a diagram illustrating a configuration example of a pixel according to the ninth embodiment of the present disclosure. The pixel200inFIG.14is different from the pixel200inFIG.13in that the third compound semiconductor layer160and a separation unit161are disposed instead of the fixed charge film180and the separation unit181, and a second electrode170is disposed.

As described above inFIG.3, the third compound semiconductor layer160is a p-type compound semiconductor layer disposed between a second compound semiconductor layer150and the second electrode170. The separation unit161inFIG.14is a separation unit constituted by the third compound semiconductor layer160. By disposing a compound semiconductor layer having a conductivity type different from the second compound semiconductor layer150, the second compound semiconductor layer150can be separated. The separation unit161can be formed by forming a trench reaching a first compound semiconductor layer140in the second compound semiconductor layer150and epitaxially growing the third compound semiconductor layer160. By disposing the separation unit161, movement of charges from the second compound semiconductor layer150of the adjacent pixel200can be prevented, and crosstalk can be reduced.

Since the configuration of the semiconductor element100other than this is similar to the configuration of the semiconductor element100described in the eighth embodiment of the present disclosure, description thereof will be omitted.

As described above, in the semiconductor device1according to the eighth embodiment of the present disclosure, by disposing the separation unit161in the second compound semiconductor layer150, crosstalk from the adjacent pixel200can be reduced.

Note that the configuration of the semiconductor element100according to the second embodiment can be applied to other embodiments. Specifically, the third compound semiconductor layer160described inFIG.3may be combined with each of the semiconductor elements100inFIGS.7and10to13.

The configuration of the semiconductor element100according to the third embodiment can be applied to other embodiments. Specifically, the through electrode122described inFIG.4may be combined with each of the semiconductor elements100inFIGS.7and10to14.

The configuration of the semiconductor element100according to the fifth embodiment can be applied to other embodiments. Specifically, the separation layer118described inFIG.10may be combined with each of the semiconductor elements100inFIGS.11to14.

The configuration of the semiconductor element100according to the sixth embodiment can be applied to other embodiments. Specifically, the MOS transistor105described inFIG.11may be combined with each of the semiconductor elements100inFIGS.12and14.

The configuration of the semiconductor element100according to the seventh embodiment can be applied to other embodiments. Specifically, the fixed charge film180described inFIG.12may be combined with the semiconductor element100inFIG.14.

Finally, the description of each of the above-described embodiments is an example of the present disclosure, and the present disclosure is not limited to the above-described embodiments. For this reason, it is needless to say that various modifications can be made according to design and the like without departing from the technical idea according to the present disclosure even if the modifications are outside the above-described embodiments.

Furthermore, the effects described in the present specification are merely examples and are not limited. Furthermore, there may be other effects.

Furthermore, the drawings in the above-described embodiments are schematic, and a dimensional ratio or the like of each portion does not necessarily coincide with an actual one. Furthermore, it is needless to say that the drawings include portions having different dimensional relationships and ratios from each other.

Note that the present technology can adopt the following configurations.

(1) A semiconductor element including:a silicon substrate;a first compound semiconductor layer formed on the silicon substrate;a second compound semiconductor layer stacked on the first compound semiconductor layer; andan electrode that is disposed on the silicon substrate and controls movement of charges between the silicon substrate and the second compound semiconductor layer via the first compound semiconductor layer.

(2) The semiconductor element according to (1), in which the first compound semiconductor layer contains Ga and P.

(3) The semiconductor element according to (1) or (2), in which the second compound semiconductor layer contains Ga, As, P, and N.

(4) The semiconductor element according to any one of (1) to (3), in which the first compound semiconductor layer has a film thickness of 50 nm or less.

(5) The semiconductor element according to any one of (1) to (4), in which the second compound semiconductor layer has a film thickness of 3 μm or more.

(6) The semiconductor element according to any one of (1) to (5), in whichthe electrode is disposed on a front surface of the silicon substrate, andthe first compound semiconductor layer is formed on a back surface of the silicon substrate that is a surface different from the front surface.

(7) The semiconductor element according to any one of (1) to (6), further including a second electrode which is disposed adjacent to the second compound semiconductor layer and in which a voltage for controlling movement of the charges is applied between the electrode and the second electrode.

(8) The semiconductor element according to (7), in which the second electrode is constituted by a transparent electrode.

(9) The semiconductor element according to (7), further includinga fixed charge film disposed adjacent to the second compound semiconductor layer and constituted by a dielectric having fixed charges, in whichthe second electrode is constituted by a charge accumulation region formed in the second compound semiconductor layer on the basis of the fixed charges of the fixed charge film.

(10) The semiconductor element according to any one of (1) to (9), further including a third compound semiconductor layer stacked on the second compound semiconductor layer and having a conductivity type different from the second compound semiconductor layer.

(11) The semiconductor element according to any one of (1) to (10), further including a separation unit that surrounds and separates the second compound semiconductor layer.

(12) The semiconductor element according to (11), in which the separation unit is constituted by a dielectric having fixed charges.

(13) The semiconductor element according to (11), in which the separation unit is constituted by a compound semiconductor having a conductivity type different from the second compound semiconductor layer.

(14) The semiconductor element according to any one of (1) to (13), in which the electrode controls movement of the charges generated in the second compound semiconductor layer by photoelectric conversion.

(15) The semiconductor element according to (14), in which the electrode performs the control by application of a control signal for moving the charges to the silicon substrate.

(16) The semiconductor element according to (15), further including a charge holding unit that is disposed in the silicon substrate and holds the moved charges.

(17) The semiconductor element according to (16), further including an image signal generation circuit that generates an image signal on the basis of the held charges.

(18) The semiconductor element according to (14), further including a separation layer that surrounds and separates the silicon substrate.

(19) The semiconductor element according to any one of (1) to (10), in which the electrode controls movement of charges to be recombined for light emission in the second compound semiconductor layer.

(20) A semiconductor device including:a silicon substrate;a first compound semiconductor layer formed on the silicon substrate;a second compound semiconductor layer stacked on the first compound semiconductor layer;an electrode that is disposed on the silicon substrate and controls movement of charges between the silicon substrate and the second compound semiconductor layer via the first compound semiconductor layer; anda control circuit that supplies a control signal for the control to the electrode.

REFERENCE SIGNS LIST

1Semiconductor device2Control circuit10Pixel array unit20Vertical drive unit30Column signal processing unit100Semiconductor element101Photoelectric conversion unit102Second charge holding unit103First charge holding unit104to109MOS transistor110,119Silicon substrate111,112n-Type semiconductor region118Separation layer120Wiring region121,123Electrode122Through electrode124,125Gate electrode140First compound semiconductor layer150Second compound semiconductor layer160Third compound semiconductor layer161,181Separation unit170Second electrode180Fixed charge film200Pixel