Patent ID: 12205898

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90° or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Embodiments, or examples, illustrated in the drawings are disclosed as follows using specific language. It will nevertheless be understood that the embodiments and examples are not intended to be limiting. Any alterations or modifications in the disclosed embodiments, and any further applications of the principles disclosed in this document are contemplated as would normally occur to one of ordinary skill in the pertinent art.

Further, it is understood that several processing steps and/or features of a device may be only briefly described. Also, additional processing steps and/or features can be added, and certain of the following processing steps and/or features can be removed or changed while still implementing the claims. Thus, it is understood that the following descriptions represent examples only, and are not intended to suggest that one or more steps or features are required.

In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

In various embodiments, a metal-oxide-metal (MOM) capacitive device is based on a cell structure in which an electrode includes a first bus and fingers in a first metal layer and a second bus and fingers in a second metal layer perpendicular to and overlapping the first bus and fingers. The electrode includes vias that electrically connect the first bus to the second bus and fingers, and electrically connect the second bus to the first bus and fingers. The electrode structure thereby enables a multi-cell capacitive device to include cells that are directly abutted by sharing the first and/or second buses, e.g., through adjacent cells having a mirror symmetry. Compared to approaches that do not include the electrode, e.g., approaches in which adjacent cells are separated by spaces, the MOM device is capable of having an increased density, thereby improving performance for a given area.

In some embodiments, direct abutment of adjacent cells and increased density are enabled by cells configured to avoid violation of one or more design rules of a manufacturing process used to create the MOM capacitive device, e.g., by matching bus spacing to a pitch of a metal layer adjacent to the first or second metal layer to avoid a metal/via overlap violation.

As discussed below,FIGS.1A and1Bare directed to an applicable IC layout system and design flow,FIGS.2A-5Cdepict configurations corresponding to both layouts and structures of the various MOM embodiments,FIG.6is directed to an applicable layout generation method, andFIGS.7and8are directed to applicable manufacturing methods.

FIG.1Aillustrates a block diagram of a processing system in accordance with some embodiments.

Referring now toFIG.1A, a block diagram of a processing system100, such as an electronic design automation (EDA) processing system, is provided in accordance with an embodiment. The processing system100is a general purpose computer platform and may be used to implement any or all of the processes discussed herein or is a dedicated computer platform for performing electronic design. The processing system100may comprise a processing unit110, such as a desktop computer, a workstation, a laptop computer, or a dedicated unit customized for a particular application. The processing system100may be equipped with a display114and one or more input/output devices112, such as a mouse, a keyboard, or printer. The processing unit110may include a central processing unit (CPU)120, memory122, a mass storage device124, a video adapter126, and an I/O interface128connected to a bus130.

The bus130may be one or more of any type of several bus architectures including a memory bus or memory controller, a peripheral bus, or video bus. The CPU120may comprise any type of electronic data processor, such as a microprocessor, and the memory122may comprise any type of system memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), or read-only memory (ROM).

The mass storage device124may comprise any type of storage device configured to store data, programs, and other information and to make the data, programs, and other information accessible via the bus130. The mass storage device124may comprise, for example, one or more of a hard disk drive, a magnetic disk drive, an optical disk drive, or the like.

The video adapter126and the I/O interface128provide interfaces to couple external input and output devices to the processing unit110. As illustrated inFIG.1A, examples of input and output devices include the display114coupled to the video adapter126and the I/O device112, such as a mouse, keyboard, printer, and the like, coupled to the I/O interface128. Other devices may be coupled to the processing unit110, and additional or fewer interface cards may be utilized. For example, a serial interface card (not shown) may be used to provide a serial interface for a printer. The processing unit110also may include a network interface140that may be a wired link to a local area network (LAN) or a wide area network (WAN)116and/or a wireless link.

It can be contemplated that the processing system100may include additional components. For example, the processing system100may include power supplies, cables, a motherboard, removable storage media, cases, and the like. These other components, although not shown, are considered part of the processing system100.

In an embodiment, an EDA is program code that is executed by the CPU120to analyze a user file to obtain an integrated circuit layout (described further below with respect toFIG.1B). Further, during the execution of the EDA, the EDA may analyze functional components of the layout. The program code may be accessed by the CPU120via the bus130from the memory122, mass storage device124, or the like, or remotely through the network interface140.

FIG.1Billustrates one possible flow used by the EDA in an embodiment to automatically generate a physical layout from a user supplied behavioral/functional design201. The behavioral/functional design201specifies the desired behavior or function of the circuit based upon various signals or stimuli applied to the inputs of the overall design, and may be written in a suitable language, such as a hardware description language (HDL). The behavioral/functional design201may be uploaded into the processing unit110(seeFIG.1A) through the I/O interface128, such as by a user creating the file while the EDA is executing. Alternatively, the behavioral/functional design201may be uploaded and/or saved on the memory122or mass storage device124, or the behavioral/functional design201may be uploaded through the network interface140from a remote user (seeFIG.1A). In these instances, the CPU120will access the behavioral/functional design201during execution of the EDA.

Additionally, the user also provides a set of design constraints203in order to constrain the overall design of the physical layout of the behavioral/functional design201. The design constraints203may be input, for example, through the I/O interface128, downloading through the network interface140, or the like. The design constraints203may specify timing and other suitable constraints for the behavioral/functional design201, once physically formed into an integrated circuit, to comply.

The EDA uses the behavioral/functional design201and the design constraints203and performs a synthesis205to create a functionally equivalent logic gate-level circuit description, such as a netlist. The synthesis205forms the functionally equivalent logic gate-level circuit description by matching the behavior and/or functions desired from the behavioral/functional design201to standard cells from cell libraries206, which meet the design constraints203.

The cell libraries206may include one or more individual cell libraries. Each of the individual cell libraries contains a listing of pre-designed components, called cells, each of which may perform a discrete logic function on a small scale. The cell is stored in the individual cell libraries as information comprising internal circuit elements, the various connections to these circuit elements, a pre-designed physical layout pattern that includes the height of each cell along with the cells' designed power rails, dopant implants, wells, and the like. Additionally, the stored cell may also comprise a shape of the cell, terminal positions for external connections, delay characteristics, power consumption, and the like.

Once the synthesis205creates the functionally equivalent logic gate-level circuit description from the behavioral/functional design201and the design constraints203by using one or more of the cell libraries206, a place and route213is performed to create an actual physical design for the overall structure. The place and route213forms the physical design by taking the chosen cells from the cell libraries206and placing them into cell rows. The placement of each individual cell within the cell rows, and the placement of each cell row in relation to other cell rows, may be guided by cost functions in order to minimize wiring lengths and area desires of the resulting integrated circuit. This placement may be done either automatically by the place and route213, or else may alternatively be performed partly through a manual process, whereby a user may manually insert one or more cells into a row.

After the initial placement of the individual cells, a post layout treatment215is performed. In an embodiment the post layout treatment215is a treatment that occurs after the placement of the individual cells and is a treatment which analyzes the vias along the abutments between the individual cells and modifies these vias along the abutment in order to overcome restraints related to the physical limitations of lithography processes and which help generate a higher density cell.

Once a physical design layout has been generated by the place and route213and the post layout treatment215has occurred, the physical design may be sent to a manufacturing tool217to generate, e.g., photolithographic masks, that may be used in the physical manufacture of the desired design. The physical design layout may be sent to the manufacturing tool217through that LAN/WAN166or other suitable forms of transmission from the EDA to the manufacturing tool217.

FIG.2Aillustrates a single cell20in accordance with some embodiments that may be stored in the cell libraries206. The cell20is a MOM capacitor cell. The cell20is arranged within cell boundaries B1, B2, B3, and B4.

The cell20includes buses vb1, vb2, hb1, and hb2. The buses vb1and vb2can each be referred to as a vertical bus, and the buses hb1and hb2can each be referred to as a horizontal bus. The buses vb1and vb2can be substantially parallel. The buses hb1and hb2can be substantially parallel. The buses vb1and vb2can be substantially perpendicular to the buses hb1and hb2. The bus vb1is aligned with the boundary B1. The bus vb2is aligned with the boundary B2. The bus hb1is aligned with the boundary B3. The bus hb2is aligned with the boundary B4.

The buses hb1, hb2, vb1, and vb2can comprise conductive materials. In some embodiments, the buses hb1, hb2, vb1, and vb2can be made of conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other applicable materials. The buses hb1, hb2, vb1, and vb2are configured to receive reference voltages. For example, the buses hb1, hb2, vb1, and vb2can be configured to receive reference voltages VDD or VSS.

The cell20includes fingers hf1, hf2, hf3, hf4, hf5and hf6extending along a horizontal axis (e.g., the X axis). The cell20includes fingers vf1, vf2, vf3, vf4, vf5and vf6extending along a vertical axis (e.g., the Y axis). The fingers hf1, hf2, hf3, hf4, hf5and hf6are disposed at the same elevation as the buses hb1and hb2. The fingers vf1, vf2, vf3, vf4, vf5and vf6are disposed at the same elevation as the buses vb1and vb2. In the embodiment shown inFIG.2A, the fingers vf1, vf2, vf3, vf4, vf5and vf6and the buses vb1and vb2are disposed above the fingers hf1, hf2, hf3, hf4, hf5and hf6and the buses hb1and hb2. The fingers vf1, vf2, vf3, vf4, vf5and vf6and the buses vb1and vb2can be disposed on a layer adjacent to the layer at which the fingers hf1, hf2, hf3, hf4, hf5and hf6and the buses hb1and hb2are disposed.

The fingers hf1, hf2, hf3, hf4, hf5, hf6, vf1, vf2, vf3, vf4, vf5and vf6can comprise conductive materials. In some embodiments, the fingers hf1, hf2, hf3, hf4, hf5, hf6, vf1, vf2, vf3, vf4, vf5and vf6can be made of conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or other applicable materials. In some embodiments, the fingers hf1, hf2, hf3, hf4, hf5, hf6, vf1, vf2, vf3, vf4, vf5and vf6can be made of identical materials. In some embodiments, the fingers hf1, hf2, hf3, hf4, hf5and hf6can be made of materials different than those of the fingers vf1, vf2, vf3, vf4, vf5and vf6.

Fingers and buses on different elevations can be electrically connected through, for example, a conductive via. Buses on different elevations can be electrically connected through, for example, a conductive via. Referring toFIG.2A, the buses vb1and hb1are electrically connected through a conductive via v1. The fingers hf1, hf3, and hf5are each electrically connected to the bus vb1through a conductive via v1. The fingers hf2, hf4, and hf6are each electrically connected to the bus vb2through a conductive via v1. The fingers vf1, vf3, and vf5are each electrically connected to the bus hb2through a conductive via v1. The fingers vf2, vf4, and vf6are each electrically connected to the bus hb1through a conductive via v1.

The fingers hf1, hf2, hf3, hf4, hf5, and hf6can each include a width W1. The fingers vf1, vf2, vf3, vf4, vf5, and vf6can each include a width W2. In some embodiments, the width W1can be substantially identical to the width W2. In other embodiments, the width W1can be different from the width W2to suit needs.

The fingers hf1, hf2, hf3, hf4, hf5, and hf6can be spaced apart from each other by a constant distance (e.g., the distance Dv1). In other embodiments, the fingers hf1, hf2, hf3, hf4, hf5, and hf6can be spaced apart from each other by different distances to suit needs. The fingers vf1, vf2, vf3, vf4, vf5, and vf6can be spaced apart from each other by a constant distance (e.g., the distance Dh1). In other embodiments, the fingers vf1, vf2, vf3, vf4, vf5, and vf6can be spaced apart from each other by different distances to suit needs.

The minimum distance between a bus and its adjacent finger, for example, the distance Dh2between the finger vf6and the bus vb2, can equal or exceed the distance between fingers (e.g., the distance Dh1). Similarly, the distance Dv2between the finger hf1and the bus hb2, can equal or exceed the distance between fingers (e.g., the distance Dv1).

A “VIA to line” space is usually taken into consideration in the fabrication of a semiconductor device. The increased space between a bus and its adjacent finger (e.g., Dh2) can enhance back-end-of-line (BEOL) breakdown voltage. In other words, the increased space between a bus and its adjacent finger may improve BEOL reliability.

From a top view perspective, the fingers hf1-hf6each includes a first end overlapping with a portion of the bus vb1and a second end overlapping with a portion of the bus vb2. From a top view perspective, the fingers vf1-vf6each includes a first end overlapping with a portion of the bus hb1and a second end overlapping with a portion of the bus hb2. From a top view perspective, the buses hb1and hb2each includes a first end overlapping with a portion of the bus vb1and a second end overlapping with a portion of the bus vb2. From a top view perspective, the buses vb1and vb2each includes a first end overlapping with a portion of the bus hb1and a second end overlapping with a portion of the bus hb2.

FIG.2Billustrates an exemplary decomposition of a single cell, in accordance with some embodiments.FIG.2Bshows an exemplary decomposition of the cell20. The cell20can include the conductive structures20aand20b. In some embodiments, the conductive structures20aand20bcan each be referred to as an electrode or a plate. In some embodiments, the conductive structures20aand20bcan each be referred to as a mesh electrode or a mesh plate.

The conductive structure20aincludes fingers at different elevations. The conductive structure20aincludes buses at different elevations. The bus hb1and the fingers hf1, hf3, and hf5are located at the same elevation. The bus vb1and the fingers vf2, vf4, and vf6are located at the same elevation. The fingers vf2, vf4, and vf6and the bus vb1are disposed above the fingers hf1, hf3, and hf5and the bus hb1.

The bus vb1can be electrically connected to the fingers hf1, hf3, and hf5through conductive vias (e.g., v1). The bus vb1can be electrically connected to the bus hb1through a conductive via (e.g., v1). The bus hb1can be electrically connected to the fingers vf2, vf4, and vf6through conductive vias (e.g., v1). The bus hb1can be electrically connected to the bus vb1through a conductive via (e.g., v1). The bus vb1is aligned with the cell boundary B1. The bus hb1is aligned with the cell boundary B3.

The conductive structure20ais configured to receive a reference voltage. In some embodiments, the conductive structure20acan be configured to receive a reference voltage VDD. The reference voltage VDD can be applied to the conductive structure20athrough the bus vb1or the bus hb1. All the fingers of the conductive structure20awill be configured at a substantial identical electric potential.

The conductive structure20bincludes fingers at different elevations. The conductive structure20bincludes buses at different elevations. The bus hb2and the fingers hf2, hf4, and hf6are located at the same elevation. The bus vb2and the fingers vf1, vf3, and vf5are located at the same elevation. The fingers vf1, vf3, and vf5and the bus vb2are disposed above the fingers hf2, hf4, and hf6and the bus hb2.

The bus vb2can be electrically connected to the fingers hf2, hf4, and hf6through conductive vias (e.g., v1). The bus vb2can be electrically connected to the bus hb2through a conductive via (e.g., v1). The bus hb2can be electrically connected to the fingers vf1, vf3, and vf5through conductive vias (e.g., v1). The bus hb2can be electrically connected to the bus vb2through a conductive via (e.g., v1). The bus vb2is aligned with the cell boundary B2. The bus hb2is aligned with the cell boundary B4.

The conductive structure20bis configured to receive a reference voltage. In some embodiments, the conductive structure20bcan be configured to receive a reference voltage VSS. The reference voltage VSS can be applied to the conductive structure20bthrough the bus vb2or the bus hb2. All the fingers of the conductive structure20bwill be configured at a substantial identical electric potential.

FIG.2Cis a cross section along the cell boundary B1ofFIG.2A, in accordance with some embodiments.

Referring toFIG.2C, the bus vb1is disposed above the buses hb1and hb2and the fingers hf1-hf6. The bus vb1can be a conductive layer adjacent to a conductive layer at which the buses hb1and hb2and the fingers hf1-hf6are disposed. The bus vb1is electrically connected to the fingers hf1, hf3, and hf5and the bus hb1.

Dielectric materials can be disposed within the space between the bus vb1and the buses hb1and hb2. Dielectric materials can be disposed within the space between the bus vb1and the fingers hf1-hf6. The dielectric layer22surrounds the buses hb1and hb2and the fingers hf1-hf6. The dielectric layer22covers the buses hb1and hb2and the fingers hf1-hf6. The buses hb1and hb2and the fingers hf1-hf6are embedded within the dielectric layer22. The dielectric layer22can include, for example, silicon dioxide, glass, PTFE (Teflon), polyethylene (PE), polyimide, polypropylene, polystyrene, titanium dioxide, strontium titanate, barium strontium titanate, barium titanate, conjugated polymers, calcium copper titanate, or other applicable materials. In some embodiments, the dielectric layer22can be replaced by vacuum.

The buses vb1, hb1and hb2and the fingers hf1-hf6can be formed at two arbitrary adjacent conductive layers within a semiconductor device. In some embodiments, the buses vb1, hb1and hb2and the fingers hf1-hf6can be formed at metal layers M0and M1. In some embodiments, the buses vb1, hb1and hb2and the fingers hf1-hf6can be formed at metal layers M1and M2. In some embodiments, the buses vb1, hb1and hb2and the fingers hf1-hf6can be formed at metal layers M2and M3. In some embodiments, the buses vb1, hb1and hb2and the fingers hf1-hf6can be formed at metal layers M3and M4. In some embodiments, the buses vb1, hb1and hb2and the fingers hf1-hf6can be formed at two adjacent metal layers higher than the metal layer M4.

FIG.2Dis a cross section along the cell boundary B3ofFIG.2A, in accordance with some embodiments.

Referring toFIG.2D, the buses vb1and vb2and the fingers vf1-vf6are disposed above the bus hb1. The bus hb1can be a conductive layer adjacent to a conductive layer at which the buses vb1and vb2and the fingers vf1-vf6are disposed. The bus hb1is electrically connected to the fingers vf1, vf3, and vf5and the bus vb2.

Dielectric materials can be disposed within the space between the bus hb1and the buses vb1and vb2. Dielectric materials can be disposed within the space between the bus hb1and the fingers vf1-vf6. The dielectric layer22surrounds the buses vb1and vb2and the fingers vf1-vf6. The dielectric layer22covers the buses vb1and vb2and the fingers vf1-vf6. The buses vb1and vb2and the fingers vf1-vf6are embedded within the dielectric layer22. The dielectric layer22can include, for example, silicon dioxide, glass, PTFE (Teflon), polyethylene (PE), polyimide, polypropylene, polystyrene, titanium dioxide, strontium titanate, barium strontium titanate, barium titanate, conjugated polymers, calcium copper titanate, or other applicable materials. In some embodiments, the dielectric layer22can be replaced by vacuum.

The buses hb1, vb1and vb2and the fingers vf1-vf6can be formed at two arbitrary adjacent conductive layers within a semiconductor device. In some embodiments, the buses hb1, vb1and vb2and the fingers vf1-vf6can be formed at first and second metal layers, also referred to as metal layers M0and M1in some embodiments. In some embodiments, the buses hb1, vb1and vb2and the fingers vf1-vf6can be formed at second and third metal layers, also referred to as metal layers M1and M2in some embodiments. In some embodiments, the buses hb1, vb1and vb2and the fingers vf1-vf6can be formed at third and fourth metal layers, also referred to as metal layers M2and M3in some embodiments. In some embodiments, the buses hb1, vb1and vb2and the fingers vf1-vf6can be formed at fourth and fifth metal layers, also referred to as metal layers M3and M4in some embodiments. In some embodiments, the buses hb1, vb1and vb2and the fingers vf1-vf6can be formed at two adjacent metal layers higher than the fifth metal layer.

Cell20including electrodes20aand20bis thereby configured to enable a multi-cell capacitive device to include cells that are directly abutted by sharing first and/or second buses, e.g., through adjacent cells having a mirror symmetry. Compared to approaches that do not include an electrode, e.g., electrode20aor20b, configured to enable directly abutted cells, the capacitive device is capable of having an increased density, thereby improving performance for a given area.

In some embodiments, cell20(and/or a cell30,40, or50discussed below) includes buses hb1, hb2, vb1, and vb2, and fingers hf1-hf6and vf1-vf6having one or more of the dimensions discussed above configured to avoid violations of one or more design rules of a manufacturing process used to create cell20and is thereby capable of being directly abutted with additional instances of cell20as discussed below. For example, in some embodiments, the dimensions correspond to buses vb1and vb2having a spacing matched to a pitch of a metal layer below that of buses hb1and hb2such that a metal/via overlap violation is avoided.

FIG.2Eillustrates an exemplary arrangement of one cell abutting another cell, in accordance with some embodiments. Referring toFIG.2E, a cell array A1can be obtained by abutting the cell20and the cell24. The cells20and24are symmetrical with respect to the boundary B2or the bus vb2. In some embodiments, the cell24can be obtained by flipping the cell20along the boundary B2(or the bus vb2) by 180°. For the cell array A1, the bus vb2will be shared by both the cells20and24. That is, the bus vb2can be a part of the cell20and also a part of the cell24. The cell array A1will have a capacitance substantially equal to the sum of the capacitances of the cells20and24.

By aligning the buses of a MOM cell with the cell boundaries, as the cells20and24do, a cell array (e.g., the cell array A1) with a higher area efficiency is therefore made possible. By abutting a MOM cell with its mirror symmetric cell (e.g., cells20and24), a cell array (e.g., the cell array A1) with a higher area efficiency is therefore created. Specifically, a cell array with higher capacitance can be obtained by abutting several MOM cells, without space therebetween, while space between MOM cells is usually required in common technique.

FIG.2Fillustrates an exemplary arrangement of one cell abutting another cell, in accordance with some embodiments. Referring toFIG.2F, a cell array A2can be obtained by abutting the cell20and the cell26. The cells20and26are mirror symmetric with respect to the boundary B3or the bus hb1. In some embodiments, the cell26can be obtained by flipping the cell20along the boundary B3(or the bus hb1) by 180°. For the cell array A2, the bus hb1will be shared by both the cells20and26. That is, the bus hb1can be a part of the cell20and also a part of the cell26. The cell array A2will have a capacitance substantially equal to the sum of the capacitances of the cells20and26.

By aligning the buses of a MOM cell with the cell boundaries, as the cells20and26do, a cell array (e.g., the cell array A2) with a higher area efficiency is therefore made possible. By abutting a MOM cell with its mirror symmetric cell (e.g., cells20and26), a cell array (e.g., the cell array A2) with a higher area efficiency is therefore created. Specifically, a cell array with higher capacitance can be obtained by abutting several MOM cells, without space therebetween, while space between MOM cells is usually required in common technique.

FIG.2Gillustrates a cell array in accordance with some embodiments.FIG.2Gshows a cell array A3comprising cells C1, C2, C3, C4, C5, C6, C7, C8, and C9. For the cell array A3, buses are arranged along the cell boundaries B1, B2, B3, and B4, and the axes X1, X2, X3, and X4. The cell C1ofFIG.2Gcan be the cell20ofFIG.2A. In the cell array A3, one cell is mirror symmetric to its adjacent cell. For example, the cell C1is mirror symmetric to the cell C2with respect to the axis X1. Similarly, the cell C2is mirror symmetric to the cell C3with respect to the axis X2. The cell C4is mirror symmetric to the cell C5with respect to the axis X1, and the cell C5is mirror symmetric to the cell C6with respect to the axis X2. The cell C7is mirror symmetric to the cell C8with respect to the axis X1, and the cell C8is mirror symmetric to the cell C9with respect to the axis X2.

In addition, the cell C1is mirror symmetric to the cell C4with respect to the axis X4, and the cell C4is mirror symmetric to the cell C7with respect to the axis X3. The cell C2is mirror symmetric to the cell C5with respect to the axis X4, and the cell C5is mirror symmetric to the cell C8with respect to the axis X3. The cell C3is mirror symmetric to the cell C6with respect to the axis X4, and the cell C6is mirror symmetric to the cell C9with respect to the axis X3.

By abutting a MOM cell with its mirror symmetric cell, a cell array (e.g., the cell array A3) with a higher area efficiency is therefore created. The cell array A3will have a capacitance substantially equal to the sum of the capacitances of the cells C1-C9.

FIG.2Hillustrates a cell structure in accordance with some embodiments.FIG.2Hshows a cell structure A4comprising cells C1, C2, C3, C4, C5, and C6. As shown inFIG.2H, the cells C1, C2, C3, C4, C5, and C6of the cell structure A4are not arranged as a regular array. The irregular arrangement of the cells C1, C2, C3, C4, C5, and C6could achieve good area utilization for the cell structure A4to be applied as a decoupling capacitor (DECAP).

The cell C1ofFIG.2Hcan be the cell20ofFIG.2A. In the cell structure A4, one cell is mirror symmetric to its adjacent cell. The cell C1is mirror symmetric to the cell C2with respect to the axis X1, and the cell C2is mirror symmetric to the cell C3with respect to the axis X2. The cell C4is mirror symmetric to the cell C5with respect to the axis X2. The cell C6is mirror symmetric to the cell C5with respect to the axis X4, and the cell C5is mirror symmetric to the cell C3with respect to the axis X3. The cell C4is mirror symmetric to the cell C2with respect to the axis X3.

FIG.3Aillustrates a single cell in accordance with some embodiments.FIG.3Ashows a cell30that may be stored in the cell libraries206. The cell30is a MOM capacitor cell. The cell30is arranged within cell boundaries B1, B2, B3, and B4. The cell30is similar to the cell20ofFIG.2A, the difference therebetween is that in the cell30, the fingers are not identical in length to the buses. Referring toFIG.3A, the fingers hf1′, hf2′, hf3′, hf4′, hf5′, and hf6′ are shorter than the buses hb1and hb2. The fingers vf1′, vf2′, vf3′, vf4′, vf5′, and vf6′ are shorter than the buses vb1and vb2.

For the fingers of the cell30, one end thereof overlaps a portion of a bus from the top view perspective, and the other end thereof is spaced apart from another bus. For example, take the finger hf1′ as an example, one end of the finger hf1′ overlaps a portion of the bus vb1(see, for example, the dotted circle T1), while the other end of the finger hf1′ is spaced apart from the bus vb2(see, for example, the dotted circle T2). The space between a finger and a bus can prevent an undesired short circuit resulting from electromigration.

For example, as will be discussed in the subsequent paragraphs, the finger hf1′ is electrically connected to a reference voltage through the bus vb1, which receives a reference voltage, while the bus vb2is configured to receive a different reference voltage. The space between the finger hf1′ and the bus vb2can prevent an undesired short circuit therebetween. Also, the space between a finger and a bus can increase the breakdown voltage that can be sustained by the cell30, and thus improve the max voltage tolerance of a semiconductor device that including the cell30.

FIG.3Billustrates an exemplary decomposition of a single cell, in accordance with some embodiments.FIG.3Bshows an exemplary decomposition of the cell30. The cell30can include the conductive structures30aand30b. In some embodiments, the conductive structures30aand30bcan each be referred to as an electrode or a plate. In some embodiments, the conductive structures30aand30bcan each be referred to as a mesh electrode or a mesh plate.

The conductive structure30aincludes fingers at different elevations. The conductive structure30aincludes buses at different elevations. The bus hb1and the fingers hf1′, hf3′, and hf5′ are located at the same elevation. The bus vb1and the fingers vf2′, vf4′, and vf6′ are located at the same elevation. The fingers vf2′, vf4′, and vf6′ and the bus vb1are disposed above the fingers hf1′, hf3′, and hf5′ and the bus hb1.

The bus vb1can be electrically connected to the fingers hf1′, hf3′, and hf5′ through conductive vias (e.g., v1). The bus vb1can be electrically connected to the bus hb1through a conductive via (e.g., v1). The bus hb1can be electrically connected to the fingers vf2′, vf4′, and vf6′ through conductive vias (e.g., v1). The bus hb1can be electrically connected to the bus vb1through a conductive via (e.g., v1). The bus vb1is aligned with the cell boundary B1. The bus hb1is aligned with the cell boundary B3.

The conductive structure30ais configured to receive a reference voltage. In some embodiments, the conductive structure30acan be configured to receive a reference voltage VDD. The reference voltage VDD can be applied to the conductive structure30athrough the bus vb1or the bus hb1. All the fingers of the conductive structure30awill be configured at a substantial identical electric potential.

The conductive structure30bincludes fingers at different elevations. The conductive structure30bincludes buses at different elevations. The bus hb2and the fingers hf2′, hf4′, and hf6′ are located at the same elevation. The bus vb2and the fingers vf1′, vf3′, and vf5′ are located at the same elevation. The fingers vf1′, vf3′, and vf5′ and the bus vb2are disposed above the fingers hf2′, hf4′, and hf6′ and the bus hb2.

The bus vb2can be electrically connected to the fingers hf2′, hf4′, and hf6′ through conductive vias (e.g., v1). The bus vb2can be electrically connected to the bus hb2through a conductive via (e.g., v1). The bus hb2can be electrically connected to the fingers vf1′, vf3′, and vf5′ through conductive vias (e.g., v1). The bus hb2can be electrically connected to the bus vb2through a conductive via (e.g., v1). The bus vb2is aligned with the cell boundary B2. The bus hb2is aligned with the cell boundary B4.

The conductive structure30bis configured to receive a reference voltage. In some embodiments, the conductive structure30bcan be configured to receive a reference voltage VSS. The reference voltage VSS can be applied to the conductive structure30bthrough the bus vb2or the bus hb2. All the fingers of the conductive structure30bwill be configured at a substantially identical electric potential.

Cell30including electrodes30aand30bis thereby configured to enable a multi-cell capacitive device to include cells that are directly abutted by sharing first and/or second buses, whereby the benefits discussed above with respect to cell20are capable of being achieved.

FIG.3Cillustrates a cell array A5in accordance with some embodiments, comprising cells C1, C2, C3, and C4. For the cell array A5, buses are arranged along the cell boundaries B1, B2, B3, and B4, and the axes X1and X2. The cell C1ofFIG.3Ccan be the cell30ofFIG.3A. In the cell array A5, one cell is mirror symmetric to its adjacent cell. For example, the cell C1is mirror symmetric to the cell C2with respect to the axis X1. Similarly, the cell C2is mirror symmetric to the cell C4with respect to the axis X2. The cell C3is mirror symmetric to the cell C4with respect to the axis X1, and the cell C3is mirror symmetric to the cell C1with respect to the axis X2.

The bus vb2is shared by the cells C1and C2. That is, the bus vb2is a part of the cell C1and also a part of the cell C2. The bus vb2is shared by the cells C3and C4. That is, the bus vb2is a part of the cell C3and also a part of the cell C4. The bus hb1is shared by the cells C1and C3. That is, the bus hb1is a part of the cell C1and also a part of the cell C3. The bus hb1is shared by the cells C2and C4. That is, the bus hb1is a part of the cell C2and also a part of the cell C4.

By abutting a MOM cell with its mirror symmetric cell, a cell array (e.g., the cell array A5) with a higher area efficiency is therefore created. The cell array A5will have a capacitance substantially equal to the sum of the capacitances of the cells C1-C4.

FIG.4Aillustrates a single cell40in accordance with some embodiments that may be stored in the cell libraries206. The cell40is a MOM capacitor cell. The cell40is arranged within cell boundaries B1, B2, B3, and B4. The cell40is similar to the cell20ofFIG.2A, the difference therebetween is that in the cell40, the buses are not aligned with the cell boundaries. That is, the buses of the cell40are adjacent to the cell boundaries. The buses of the cell40are spaced apart from the cell boundaries. The buses of the cell40are disposed around the cell boundaries.

FIG.4Billustrates an exemplary decomposition of a single cell, in accordance with some embodiments.

FIG.4Bshows an exemplary decomposition of the cell40. The cell40can include the conductive structures40aand40b. In some embodiments, the conductive structures40aand40bcan each be referred to as an electrode or a plate. In some embodiments, the conductive structures40aand40bcan each be referred to as a mesh electrode or a mesh plate.

The conductive structure40ais similar to the conductive structure20aofFIG.2B, the difference therebetween is that in the conductive structure40a, the buses vb1and hb1are not aligned with the cell boundaries B1and B3. The conductive structure40bis similar to the conductive structure20bofFIG.2B, the difference therebetween is that in the conductive structure40b, the buses vb2and hb2are not aligned with the cell boundaries B2and B4.

Cell40including electrodes40aand40bis thereby configured to enable a multi-cell capacitive device to include cells that are closely abutted by having reduced spacing between electrode components compared to other approaches, whereby the benefits discussed above with respect to cell20are capable of being achieved.

In some embodiments, cell40includes buses vb1, vb2, hb1, and hb2, offset from corresponding boundaries B1-B4by one or more distances configured to avoid violations of one or more design rules of a manufacturing process used to create cell40and is thereby capable of being directly abutted with additional instances of cell40, e.g., by avoiding having abutted cells cause violations of one or more of a metal-to-metal, metal-to-via, or via-to-via spacing rule.

FIG.4Cillustrates a cell array in accordance with some embodiments.FIG.4Cshows a cell array A6comprising cells C1, C2, C3, and C4. The cell C1ofFIG.4Ccan be the cell40ofFIG.4A. In the cell array A6, one cell is mirror symmetric to its adjacent cell. For example, the cell C1is mirror symmetric to the cell C2with respect to the axis X1. Similarly, the cell C2is mirror symmetric to the cell C4with respect to the axis X2. The cell C3is mirror symmetric to the cell C4with respect to the axis X1, and the cell C3is mirror symmetric to the cell C1with respect to the axis X2. The buses vb2and vb3are disposed on opposite sides of the axis X1. The buses vb2and vb3sandwich the axis X1. The buses hb2and hb3are disposed on opposite sides of the axis X2. The buses hb2and hb3sandwich the axis X2.

By abutting a MOM cell with its mirror symmetric cell, a cell array (e.g., the cell array A6) with a higher area efficiency is therefore created. The cell array A6will have a capacitance substantially equal to the sum of the capacitances of the cells C1-C4.

FIG.5Aillustrates a single cell in accordance with some embodiments.FIG.5Ashows a cell50that may be stored in the cell libraries206. The cell50is a MOM capacitor cell. The cell50is arranged within cell boundaries B1, B2, B3, and B4. The cell50is similar to the cell20ofFIG.2A, the difference therebetween is that the cell50includes additional vertical buses (i.e., the buses vb3and vb4). In addition, the cell50includes additional conductive vias for connecting the additional vertical buses to their corresponding fingers. For example, the bus vb3is electrically connecting to its corresponding fingers through the conductive via v2. Although the cell50as shown includes only two horizontal buses (i.e., the buses hb1and hb2), it can be contemplated that the cell50may include additional horizontal buses to suit needs.

With additional buses, the overall resistance of the cell50can be reduced accordingly. The relatively lower resistance of a MOM capacitor can decrease the latency of a semiconductor. The relatively lower resistance of a MOM capacitor can increase the response speed of a semiconductor. The relatively lower resistance of a MOM capacitor can also increase the bandwidth of a semiconductor.

The width Wb of a bus can be different than the width Wf of a finger. In some embodiments, the width Wb of a bus can equal or exceed the width Wf of a finger. A bus of greater width can facilitate reducing overall bus metal resistance in the semiconductor device manufactured.

The distance Dbb between adjacent buses can be different than the distance Dff between adjacent fingers. In some embodiments, the distance Dbb between adjacent buses can equal or exceed the distance Dff between adjacent fingers. The “VIA to VIA” space (e.g., the space between vias v1and v2) is usually taken into consideration in fabrication of a semiconductor device. Neighboring vias may have a possibility of bridging. In the implementation, a greater space between adjacent buses is sometimes preferred in order to avoid any uncertainty in fabrication.

FIG.5Bshows an exemplary decomposition of the cell50. The cell50can include the conductive structures50aand50b. In some embodiments, the conductive structures50aand50bcan each be referred to as an electrode or a plate. In some embodiments, the conductive structures50aand50bcan each be referred to as a mesh electrode or a mesh plate.

The conductive structure50ais similar to the conductive structure20aofFIG.2B, the difference therebetween is that the conductive structure50aincludes an additional bus vb3. The bus vb3is electrically connected to the fingers hf1, hf3, and hf5through conductive vias v2. The bus vb3is electrically connected to the bus hb1through a conductive via v2. The conductive structure50ais configured to receive a reference voltage VDD.

The conductive structure50bis similar to the conductive structure20bofFIG.2B, the difference therebetween is that the conductive structure50bincludes an additional bus vb4. The bus vb4is electrically connected to the fingers hf2, hf4, and hf6through conductive vias v2. The bus vb4is electrically connected to the bus hb2through a conductive via v2. The conductive structure50bis configured to receive a reference voltage VSS.

Cell50including electrodes50aand50bis thereby configured to enable a multi-cell capacitive device to include cells that are directly abutted by sharing first and/or second buses, whereby the benefits discussed above with respect to cell20are capable of being achieved.

FIG.5Cillustrates a cell array in accordance with some embodiments.FIG.5Cshows a cell array A7comprising cells C1, C2, C3, and C4. The cell C1ofFIG.5Ccan be the cell50ofFIG.5A. In the cell array A7, one cell is mirror symmetric to its adjacent cell. For example, the cell C1is mirror symmetric to the cell C2with respect to the axis X1. Similarly, the cell C2is mirror symmetric to the cell C4with respect to the axis X2. The cell C3is mirror symmetric to the cell C4with respect to the axis X1, and the cell C3is mirror symmetric to the cell C1with respect to the axis X2. The bus vb2is aligned with the axis X1. The buses vb4and vb5are disposed on opposite sides of the axis X1. The buses vb4and vb5sandwich the axis X1.

The bus vb2is shared by the cells C1and C2. That is, the bus vb2is a part of the cell C1and also a part of the cell C2. The bus vb2is shared by the cells C3and C4. That is, the bus vb2is a part of the cell C3and also a part of the cell C4. The bus hb1is shared by the cells C1and C3. That is, the bus hb1is a part of the cell C1and also a part of the cell C3. The bus hb1is shared by the cells C2and C4. That is, the bus hb1is a part of the cell C2and also a part of the cell C4.

By abutting a MOM cell with its mirror symmetric cell, a cell array (e.g., the cell array A7) with a higher area efficiency is therefore created. The cell array A7will have a capacitance substantially equal to the sum of the capacitances of the cells C1-C4. With additional buses, the overall resistance of the cell array A7can be reduced accordingly. The relatively lower resistance of a capacitor cell array can decrease the latency of a semiconductor. The relatively lower resistance of a capacitor cell array can increase the response speed of a semiconductor. The relatively lower resistance of a capacitor cell array can also increase the bandwidth of a semiconductor.

FIG.6is a flowchart showing a method600of arranging metal-oxide-metal (MOM) cells within a semiconductor device layout, in accordance with some embodiments of the present disclosure.FIG.6is a flowchart of method600including operations602,604,606,608, and610, operable to generate a semiconductor device layout corresponding to one or more of cells20-50or arrays A1-A7discussed above with respect toFIGS.2A-5C.

In some embodiments, some or all of the operations of method600is executed by a processor of a computer, e.g., CPU120, discussed above with respect toFIG.1A.

Some or all of the operations of method600are capable of being performed as part of a design procedure performed in a design house, e.g., a design house820discussed below with respect toFIG.8.

In some embodiments, the operations of method600are performed in the order depicted inFIG.6. In some embodiments, the operations of method600are performed simultaneously and/or in an order other than the order depicted inFIG.6. In some embodiments, one or more operations are performed before, between, during, and/or after performing one or more operations of method600.

In the operation602, a first metal-oxide-metal (MOM) cell is placed within a layout of a semiconductor. The first MOM cell includes a first bus and a second bus extending along a first direction and a third bus and a fourth bus extending along a second direction. The first MOM cell can be, for example, the cells20,30,40, or50disclosed in the present disclosure. The operation602can be performed collaboratively, for example, by the synthesis205, the cell libraries206, and the place and route213ofFIG.1B.

In operation604, a second MOM cell is formed by flipping the first MOM cell along the second bus. For example, referring back toFIG.2E, the cell24can be formed by flipping the cell20along the bus vb2by 180°. In operation604, the second MOM cell formed is mirror symmetric to the first MOM cell with respect to the second bus. The operation604can be performed collaboratively, for example, by the synthesis205, the cell libraries206, and the place and route213ofFIG.1B.

In operation606, the second MOM cell is placed abutting to the first MOM cell. For example, referring back toFIG.2G,2H,3C,4C, or5C, the cell C2can be placed abutting the cell C1. The operation606can be performed collaboratively, for example, by the synthesis205, the cell libraries206, and the place and route213ofFIG.1B.

In operation608, a third MOM cell is formed by flipping the first MOM cell along the third bus. For example, referring back toFIG.2F, the cell26can be formed by flipping the cell20along the bus hb1by 180°. In operation608, the third MOM cell formed is mirror symmetric to the first MOM cell with respect to the third bus. The operation608can be performed collaboratively, for example, by the synthesis205, the cell libraries206, and the place and route213ofFIG.1B.

In operation610, the third MOM cell is placed abutting the first MOM cell. For example, referring back toFIG.3C,4C, or5C, the cell C3can be placed abutting the cell C1. The operation610can be performed collaboratively, for example, by the synthesis205, the cell libraries206, and the place and route213ofFIG.1B.

By executing some or all of the operations of method600, a semiconductor device layout diagram is generated corresponding to a semiconductor device that includes some or all of the features discussed above with respect to cells20-50and arrays A1-A7, thereby obtaining the benefits discussed above.

FIG.7is a flowchart of a method700of manufacturing a semiconductor device, in accordance with some embodiments. Method700is operable to form one or more of cells20-50or arrays A1-A7discussed above with respect toFIGS.2A-5C.

In some embodiments, the operations of method700are performed in the order depicted inFIG.7. In some embodiments, the operations of method700are performed in an order other than the order depicted inFIG.7and/or two or more operations of method700are performed simultaneously. In some embodiments, one or more additional operations are performed before, during, and/or after the operations of method700. In some embodiments, performing some or all of the operations of method700includes performing one or more operations as discussed below with respect to IC manufacturing system800ofFIG.8.

At operation710, in some embodiments, front-end-of-line (FEOL) devices are formed in a semiconductor substrate. In various embodiments, forming FEOL devices includes forming one or more transistors, e.g., included in one or more logical or functional circuits. In some embodiments, forming FEOL devices includes forming one or more active areas, source/drain (S/D) structures, isolation structures, gate structures, or the like.

In some embodiments, forming FEOL devices includes performing one or more implantation processes in areas of a semiconductor substrate corresponding to active areas, whereby predetermined doping concentrations and types are achieved for one or more given dopants. In some embodiments, forming FEOL devices includes performing one or more lithography, deposition, etching, planarizing, or other suitable processes.

At operation720, first and second buses and first and second groups of fingers extending in a first direction at a first elevation are constructed. Constructing the first and second buses and first and second groups of fingers includes constructing the first and second groups of fingers between the first and second buses at the first elevation, also referred to as a first metal layer in some embodiments.

In some embodiments, constructing the first and second groups of fingers includes alternating the fingers of the first group of fingers with the fingers of the second group of fingers.

In some embodiments, constructing the first and second buses and first and second groups of fingers includes constructing conductive segments corresponding to buses hb1and hb2, odd numbered instances of fingers hfx, and even numbered instances of fingers hfx, respectively, as discussed above with respect to cells20-50andFIGS.2A-5C.

In some embodiments, constructing the first and second buses and first and second groups of fingers includes constructing conductive segments corresponding to multiple cells of an array, e.g., one or more of arrays A1-A7discussed above with respect toFIGS.2A-5C.

In some embodiments, constructing conductive segments, e.g., one or more of a bus, group of fingers, via or other electrical connection discussed herein with respect to operations720-740, includes performing a plurality of manufacturing operations including depositing and patterning one or more photoresist layers, performing one or more etching processes, and performing one or more deposition processes whereby one or more conductive materials are configured to form a continuous, low resistance structure.

At operation730, third and fourth buses and third and fourth groups of fingers extending in a second direction at a second elevation are constructed. Constructing the third bus and third group of fingers includes constructing vias whereby the third bus and third group of fingers are electrically connected to the first bus and the first group of fingers, and the fourth bus and fourth group of fingers are electrically connected to the second bus and second group of fingers. Constructing the third and fourth buses and third and fourth groups of fingers includes constructing the third and fourth groups of fingers between the third and fourth buses at the second elevation, also referred to as a second metal layer in some embodiments.

In some embodiments, constructing the third and fourth groups of fingers includes alternating the fingers of the third group of fingers with the fingers of the fourth group of fingers.

In some embodiments, constructing the third and fourth buses and third and fourth groups of fingers includes constructing conductive segments corresponding to buses vb1and vb2, even numbered instances of fingers vfx, and odd numbered instances of fingers vfx, respectively, as discussed above with respect to cells20-50andFIGS.2A-5C.

In some embodiments, constructing the third and fourth buses and third and fourth groups of fingers includes constructing conductive segments corresponding to multiple cells of an array, e.g., one or more of arrays A1-A7discussed above with respect toFIGS.2A-5C.

At operation740, in some embodiments, a first electrical connection is constructed between a first reference voltage path and the first and third busses and first and third groups of fingers, and a second electrical connection is constructed between a second reference voltage path and the second and fourth busses and second and fourth groups of fingers.

In some embodiments, constructing the electrical connection includes constructing one or more conductive segments at one or more of the first, second, or another elevations and/or constructing one or more vias between various elevations.

In various embodiments, constructing the electrical connection includes constructing one or more electrical connections between one or more reference voltage paths configured to carry one or both of voltages VDD or VSS as discussed above with respect toFIGS.2A-5C.

By executing some or all of the operations of method700, a semiconductor device is built that includes some or all of the features discussed above with respect to cells20-50and arrays A1-A7, thereby obtaining the benefits discussed above.

FIG.8is a block diagram of IC manufacturing system800, and an IC manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, based on an IC layout diagram, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is fabricated using manufacturing system800.

InFIG.8, IC manufacturing system800includes entities, such as a design house820, a mask house830, and an IC manufacturer/fabricator (“fab”)850, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device860. The entities in system800are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house820, mask house830, and IC fab850is owned by a single larger company. In some embodiments, two or more of design house820, mask house830, and IC fab850coexist in a common facility and use common resources.

Design house (or design team)820generates an IC design layout diagram822. IC design layout diagram822includes various geometrical patterns, e.g., an IC layout diagram including the MOM cells discussed above. The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device860to be fabricated. The various layers combine to form various IC features. For example, a portion of IC design layout diagram822includes various IC features, such as an active region, gate electrode, source and drain, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house820implements a proper design procedure to form IC design layout diagram822. The design procedure includes one or more of logic design, physical design or place and route. IC design layout diagram822is presented in one or more data files having information of the geometrical patterns. For example, IC design layout diagram822can be expressed in a GDSII file format or DFII file format.

Mask house830includes data preparation832and mask fabrication844. Mask house830uses IC design layout diagram822to manufacture one or more masks845to be used for fabricating the various layers of IC device860according to IC design layout diagram822. Mask house830performs mask data preparation832, where IC design layout diagram822is translated into a representative data file (RDF). Mask data preparation832provides the RDF to mask fabrication844. Mask fabrication844includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as mask (reticle)845or a semiconductor wafer853. The design layout diagram822is manipulated by mask data preparation832to comply with particular characteristics of the mask writer and/or requirements of IC fab850. InFIG.8, mask data preparation832and mask fabrication844are illustrated as separate elements. In some embodiments, mask data preparation832and mask fabrication844can be collectively referred to as mask data preparation.

In some embodiments, mask data preparation832includes optical proximity correction (OPC) which uses lithography enhancement techniques to compensate for image errors, such as those that can arise from diffraction, interference, other process effects and the like. OPC adjusts IC design layout diagram822. In some embodiments, mask data preparation832includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

In some embodiments, mask data preparation832includes a mask rule checker (MRC) that checks the IC design layout diagram822that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram822to compensate for limitations during mask fabrication844, which may undo part of the modifications performed by OPC in order to meet mask creation rules.

In some embodiments, mask data preparation832includes lithography process checking (LPC) that simulates processing that will be implemented by IC fab850to fabricate IC device860. LPC simulates this processing based on IC design layout diagram822to create a simulated manufactured device, such as IC device860. The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine IC design layout diagram822.

It should be understood that the description of mask data preparation832has been simplified for the purposes of clarity. In some embodiments, data preparation832includes additional features such as a logic operation (LOP) to modify the IC design layout diagram822according to manufacturing rules. Additionally, the processes applied to IC design layout diagram822during data preparation832may be executed in a variety of different orders.

After mask data preparation832and during mask fabrication844, a mask845or a group of masks845are fabricated based on the modified IC design layout diagram822. In some embodiments, mask fabrication844includes performing one or more lithographic exposures based on IC design layout diagram822. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle)845based on the modified IC design layout diagram822. Mask845can be formed in various technologies. In some embodiments, mask845is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) or EUV beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask version of mask845includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask845is formed using a phase shift technology. In a phase shift mask (PSM) version of mask845, various features in the pattern formed on the phase shift mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication844is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in semiconductor wafer853, in an etching process to form various etching regions in semiconductor wafer853, and/or in other suitable processes.

IC fab850is an IC fabrication facility that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, IC Fab850is a semiconductor foundry. For example, there may be a manufacturing facility for the front-end fabrication of a plurality of IC products (front-end-of-line (FEOL) fabrication), while a second manufacturing facility may provide the back end fabrication for the interconnection and packaging of the IC products (back-end-of-line (BEOL) fabrication), and a third manufacturing facility may provide other services for the foundry.

IC fab850includes wafer fabrication tools852configured to execute various manufacturing operations on semiconductor wafer853such that IC device860is fabricated in accordance with the mask(s), e.g., mask845. In various embodiments, fabrication tools852include one or more of a wafer stepper, an ion implanter, a photoresist coater, a process chamber, e.g., a CVD chamber or LPCVD furnace, a CMP system, a plasma etch system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein.

IC fab850uses mask(s)845fabricated by mask house830to fabricate IC device860. Thus, IC fab850at least indirectly uses IC design layout diagram822to fabricate IC device860. In some embodiments, semiconductor wafer853is fabricated by IC fab850using mask(s)845to form IC device860. In some embodiments, the IC fabrication includes performing one or more lithographic exposures based at least indirectly on IC design layout diagram822. Semiconductor wafer853includes a silicon substrate or other proper substrate having material layers formed thereon. Semiconductor wafer853further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps).

According to some embodiments, a semiconductor device is provided. The semiconductor device includes a first metal-oxide-metal (MOM) cell. The first MOM cell comprises a first bus in a first elevation and extending along a first direction; and a second bus in a second elevation, extending along a second direction different than the first direction, and electrically connected to the first bus through a via. The first MOM cell further comprises a first group of fingers in the first elevation and extending along the first direction; and a second groups of fingers in the second elevation and extending along the second direction. Each finger of the first group of fingers is electrically connected to the second bus through a corresponding via, each finger of the second group of fingers is electrically connected to the first bus through a corresponding via, and each finger of the first group of fingers overlaps each finger of the second group of fingers.

According to other embodiments, a semiconductor device is provided. The semiconductor device includes a first metal-oxide-metal (MOM) cell. The first MOM cell comprises a first bus and a second bus at a first elevation and extending along a first direction, and a third bus and a fourth bus at a second elevation and extending along a second direction different from the first direction. The first MOM cell further comprises a first group of fingers alternating with a second group of fingers at the first elevation and extending along the first direction, all of which are disposed between the first bus and the second bus, and a third group of fingers alternating with a fourth group of fingers at the second elevation and extending along the second direction, all of which are disposed between the third bus and the fourth bus. The first bus and the third bus are electrically connected through a via, the second bus and the fourth bus are electrically connected through a via, each finger of the first group of fingers is electrically connected to the third bus through a corresponding via, each finger of the second group of fingers is electrically connected to the fourth bus through a corresponding via, each finger of the third group of fingers is electrically connected to the first bus through a corresponding via, and each finger of the fourth group of fingers is electrically connected to the second bus through a corresponding via.

According to other embodiments, a method of manufacturing a semiconductor device is provided. The method includes constructing first and second buses and first and second groups of fingers extending in a first direction at a first elevation, the first and second groups of fingers being between the first and second buses, and constructing third and fourth buses and third and fourth groups of fingers extending in a second direction at a second elevation, the third and fourth groups of fingers being between the third and fourth buses. The third bus and third group of fingers are electrically connected through vias to the first bus and first group of fingers, and the fourth bus and fourth group of fingers are electrically connected through vias to the second bus and second group of fingers.

The methods and features of the present disclosure have been sufficiently described in the above examples and descriptions. It should be understood that any modifications or changes without departing from the spirit of the present disclosure are intended to be covered in the protection scope of the present disclosure.

Moreover, the scope of the present application in not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As those skilled in the art will readily appreciate from the present disclosure, processes, machines, manufacture, composition of matter, means, methods or steps presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein, may be utilized according to the present disclosure.

Accordingly, the appended claims are intended to include within their scope: processes, machines, manufacture, compositions of matter, means, methods or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the present disclosure.