Patent ID: 12211852

DETAILED DESCRIPTION

Exemplary embodiments are described herein more fully with reference to accompanying drawings. However, the exemplary embodiments may be implemented in many forms and should not be construed as limited to examples set forth herein. On the contrary, by providing these embodiments, the present disclosure will be more thorough and complete, and concepts of the exemplary embodiments will be fully communicated to a person of ordinary skill in the art. In the drawings, the same reference numerals denote the same or similar structures, and therefore their detailed description are omitted.

Although relative terms, for example “upper” and “lower”, are used in the specification to describe a relative relationship between one component of an icon and another component, using these terms in the specification is merely for convenience. For example, according to exemplary directions described in the accompanying drawings, it can be understood that if an apparatus of the icon is turned upside down, a component described in “upper” will become a component described in “lower”. Other relative terms, for example “high”, “low”, “top”, “bottom”, “left” and “right”, etc., also have similar meanings. When some structure is “on” other structures, it may mean that some structure is integrally formed on other structures, or that some structure is “directly” arranged on other structures, or that some structure is “indirectly” arranged on other structures by another structure.

The terms “a”, “an” and “the” are used to indicate existence of one or more elements/components/etc. The terms “including” and “is/are provided with” are used to mean inclusive and mean that there may be other elements/components/etc. besides the listed elements/components/etc.

FIG.1is a structural schematic diagram of an exemplary embodiment of a semiconductor structure in related art. The semiconductor structure includes a semiconductor substrate00, a first isolation dam02and a plurality of switching transistors. The semiconductor substrate includes a trench05, an isolation region031formed by a region where the trench05is located, a plurality of active regions032defined by the isolation region031, and an electrical isolation layer01, the electrical isolation layer01being located on one side, away from an opening of the trench, of the trench05. The first isolation dam02fills the trench05. The switching transistor is embedded in the active region032of the semiconductor substrate00, and the switching transistor may include a channel portion041, a gate insulation layer042, a gate043, a first source/drain portion and a second source/drain portion. As shown inFIG.1, the first source/drain portion may include a first lightly doped portion0461and a first heavily doped portion0462, and the second source/drain portion may include a second lightly doped portion0451and a second heavily doped portion0452. The first isolation dam02may be made from an insulation material, for example silicon oxide, etc., and the first isolation dam02may be used to block electrical leakage, out of the active region032, of the switching transistor located in the active region032. However, as shown inFIG.1, the channel portion041of the switching transistor is relatively close to the electrical isolation layer01. When the switching transistor conducts electricity, a current flowing through the channel portion041of the switching transistor is prone to leakage from between the first isolation dam02and the electrical isolation layer01, and a direction of the leaked current may be shown by an arrow inFIG.1.

Based on this, this exemplary embodiment provides a semiconductor structure.FIG.2is a structural schematic diagram of an exemplary embodiment of the semiconductor structure of the present disclosure. The semiconductor structure may include: a semiconductor substrate1, a first isolation dam2, a plurality of switching transistors3and a second isolation dam4. The semiconductor substrate1may include a trench11, an isolation region5formed by a region where the trench11is located, a plurality of active regions6defined by the isolation region5, and an electrical isolation layer12, the electrical isolation layer12being located on one side, away from an opening of the trench, of the trench11, and a trench bottom of the trench11being spaced from the electrical isolation layer12by a preset distance. The first isolation dam2fills the trench11. The switching transistor3is at least partially embedded in the active region6of the semiconductor substrate, and the second isolation dam4is at least partially located between the first isolation dam2and the electrical isolation layer12.

In the semiconductor structure provided by this exemplary embodiment, since the trench bottom of the trench11is spaced from the electrical isolation layer12by the preset distance, a leaked current of the switching transistor is prone to leakage from between the first isolation dam02and the electrical isolation layer01. The second isolation dam4in this exemplary embodiment may be used to block the leaked current of the switching transistor3, thereby avoiding the leaked current of the switching transistor.

It should be noted that, in this exemplary embodiment, as shown inFIG.2, the isolation region5may indicate a spatial region which may penetrate the entire semiconductor substrate1in a layer direction. The active region6may also indicate a spatial region which may penetrate the entire semiconductor substrate1in a layer direction.

In this exemplary embodiment, as shown inFIG.2, the semiconductor substrate1may be made from semiconductor materials, for example silicon, a silicon-on-insulator (SOI), germanium, gallium arsenide, etc. The first isolation dam2may be made from an insulating material, for example silicon oxide. The electrical isolation layer12may be made from a doped semiconductor subjected to ion doping, and a doping type of the electrical isolation layer is different from that of a source/a drain of the switching transistor. For example, when the switching transistor is an N-type switching transistor, the electrical isolation layer12may be made from a semiconductor material subjected to P-type ion doping, and when the switching transistor is a P-type switching transistor, the electrical isolation layer12may be made from a semiconductor material subjected to N-type ion doping.

In this exemplary embodiment, the second isolation dam4is used to block the leaked current of the switching transistor. The second isolation dam4may be made from a semiconductor material subjected to ion doping, and the switching transistor may include a source/a drain. A doping type of the second isolation dam is different from that of the source/the drain of the switching transistor. For example, when the doping type of the source/the drain of the switching transistor is P-type doping, the second isolation dam4may be made from a semiconductor material subject to N-type ion doping. When the doping type of the source/the drain of the switching transistor is N-type doping, the second isolation dam4may be made from a semiconductor material subjected to P-type ion doping. Since the doping type of the second isolation dam is different from that of the source/the drain of the switching transistor, a carrier for transport between the source and the drain of the switching transistor is different from a type of a majority carrier of the second isolation dam4(one carrier is a hole and the other carrier is an electron). When the carrier for transport between the source and the drain of the switching transistor flows to the second isolation dam4, the carrier for transport between the source and the drain of the switching transistor combines with the majority carrier of the second isolation dam4, thus blocking the leaked current of the switching transistor.

It should be understood that in other exemplary embodiments, the second isolation dam4may also be made from other materials, for example, the second isolation dam4may be made from an insulation material.

FIG.3is a top view ofFIG.2. In this exemplary embodiment, the active regions6are isolated into mutually isolated sections by the isolation region5. The active region6may be rectangular, and correspondingly, the trench on the semiconductor substrate1may be formed by a plurality of intersecting strip-shaped sub-trenches. It should be understood that in other exemplary embodiments, the active region6may also in other shapes. For example,FIG.4is a top view of another exemplary embodiment of the semiconductor structure of the present disclosure, the active region6may also in a circular shape.

In this exemplary embodiment, as shown inFIG.2, the second isolation dam4may be connected between the first isolation dam2and the electrical isolation layer12in an abutting manner. That is, the second isolation dam4, the first isolation dam2and the electrical isolation layer12may be provided with a plurality of recess structures, and side walls of the recess structures are all sealed structures, which may completely block a current leakage path of the switching transistor. It should be understood that in other exemplary embodiments, the second isolation dam4may also be located between the first isolation dam2and the electrical isolation layer12, the second isolation dam4is not connected to the first isolation dam2in an abutting manner and/or the second isolation dam4is not connected to the electrical isolation layer12in an abutting manner, and the structure may still play a certain role in blocking the leaked current.

In this exemplary embodiment, as shown inFIG.2, an orthographic projection of a side surface, facing the electrical isolation layer12, of the first isolation dam2on the electrical isolation layer12is located on an orthographic projection of the second isolation dam4on the electrical isolation layer12. That is, a width of the second isolation dam4is greater than or equal to a width of a bottom of the first isolation dam2, and a direction of the width is perpendicular to a side wall of the trench. The second isolation dam4with a relatively great with may enhance the leaked current blocking effect of the second isolation dam4.

In this exemplary embodiment, as shown inFIG.2, the width L1of the second isolation dam may be 1.2-1.5 times of a width L2of an opening of a top of the trench, and a direction of the width is perpendicular to the side wall of the trench. A distance between a side surface, facing the electrical isolation layer12, of the first isolation dam2and a side surface, facing the electrical isolation layer, of the second isolation dam4is greater than or equal to 15 nm. That is, a distance between of a bottom of the first isolation dam2and a bottom of the second isolation dam4may be greater than or equal to 15 nm. The height of the first isolation dam2may be 4-5 times of the height of the second isolation dam4, a direction of the height is perpendicular to a plane where the electrical isolation layer is located. One end, facing the electrical isolation layer12, of the first isolation dam2may be embedded in the second isolation dam, which may wrap a portion of the second isolation dam4in a side surface of the bottom of the first isolation dam2, thus enhancing the leaked current blocking effect of the second isolation dam4.

In this exemplary embodiment,FIG.5is a structural schematic diagram of another exemplary embodiment of the semiconductor structure of the present disclosure. The active region6of the semiconductor substrate may be provided with a recess13, and the recess13and the trench11may be provided on the same side surface of the semiconductor substrate1. The switching transistor may include: a channel portion31, a gate insulation layer32, a gate33and a source/a drain, where the channel portion31is at least partially embedded at one side, away from an opening of the recess, of the recess13, the gate insulation layer32covers one side, away from the electrical isolation layer12, of the recess13according to a shape of the side of the recess, and the gate33may be arranged on one side, away from the electrical isolation layer12, of the gate insulation layer32and is located in the recess13. The source/the drain may include: a first source/a first drain and a second source/a second drain, and in the first source/the first drain and the second source/the second drain, one is a source of the switching transistor, and the other is a drain of the switching transistor. As shown inFIG.5, the first source/the first drain may include a first lightly doped source/a first lightly doped drain351and a first heavily doped source/a first heavily doped drain352, the first lightly doped source/the first lightly doped drain351is connected to a first side of the channel portion31, and the first heavily doped source/the first heavily doped drain352is connected to the first lightly doped source/the first lightly doped drain351. An ion doping concentration of the first heavily doped source/the first heavily doped drain352is greater than that of the first lightly doped source/the first lightly doped drain351, and a doping type of the first lightly doped source/the first lightly doped drain351and a doping type of the first heavily doped source/the first heavily doped drain352are the same. The second source/the second drain may include: a second lightly doped source/a second lightly doped drain341and a second heavily doped source/a second heavily doped drain342. The second lightly doped source/the second lightly doped drain341is connected to a second side of the channel portion31, and the first side and the second side of the channel portion are opposite each other, that is, an orthographic projection of the gate33on a plane where the channel portion31is located is located between the first side and the second side of the channel portion. The second heavily doped source/the second heavily doped drain342is connected to the second lightly doped source/the second lightly doped drain341. An ion doping concentration of the second heavily doped source/the second heavily doped drain342is greater than that of the second lightly doped source/the second lightly doped drain341, and a doping type of the second heavily doped source/the second heavily doped drain342and a doping type of the second lightly doped source/the second lightly doped drain341are the same. The first source/the first drain is set to include the first lightly doped source/the first lightly doped drain351and the first heavily doped source/the first heavily doped drain352, and the second source/the second drain is set to include the second lightly doped source/the second lightly doped drain341and the second heavily doped source/the second heavily doped drain342, which may prevent a hot electron degradation effect in the channel portion of the switching transistor.

As shown inFIGS.2and5, the semiconductor structure may further include an encapsulation layer7, the encapsulation layer7may cover one side, provided with the trench11, of the semiconductor substrate1, and the encapsulation layer7may be made from silicon nitride, which has relatively strong hardness and may protect the semiconductor structure.

This exemplary embodiment further provides a method of manufacturing a semiconductor structure.FIG.6is a flowchart of an exemplary embodiment of the method of manufacturing a semiconductor structure of the present disclosure. The method of manufacturing a semiconductor structure may include:S1: form a semiconductor substrate, where the semiconductor substrate includes a trench, an isolation region formed by a region where the trench is located, a plurality of active regions defined by the isolation region, and an electrical isolation layer, the electrical isolation layer being located on one side, away from an opening of the trench, of the trench, and a trench bottom of the trench being spaced from the electrical isolation layer by a preset distance;S2: fill the trench with an insulation material, so as to form a first isolation dam;S3: form a plurality of switching transistors in the active region of the semiconductor substrate, the switching transistor being at least partially embedded in the active region of the semiconductor substrate; andS4: form a second isolation dam at least partially located between the first isolation dam and the electrical isolation layer.

The following describes the steps above in detail:as shown inFIG.7, the forming a semiconductor substrate in S1may include: provide a semiconductor substrate; and perform ion implantation on the semiconductor substrate to form the electrical isolation layer12in the semiconductor substrate. The semiconductor substrate may be made from semiconductor materials, for example silicon, a silicon-on-insulator (SOI), germanium, gallium arsenide, etc. The performing ion implantation on the semiconductor substrate may include perform N-type ion implantation or P-type ion implantation on the semiconductor substrate. When the switching transistor is a P-type switching transistor, the performing ion implantation on the semiconductor substrate may include perform N-type ion implantation on the semiconductor substrate. When the switching transistor is an N-type switching transistor, the performing ion implantation on the semiconductor substrate may include perform P-type ion implantation on the semiconductor substrate. The electrical isolation layer12may be a lightly doped semiconductor.

As shown inFIG.8, the forming a semiconductor substrate in S1may further includes: form a trench11on one side of the semiconductor substrate, form an isolation region5by a region where the trench11is located, define a plurality of active regions6by the isolation region5, and space a trench bottom of the trench11from the electrical isolation layer12by a preset distance. As shown inFIG.8, before the forming the trench11, the method of manufacturing a semiconductor structure may further include: form a recess13on the active region6, the recess13and the trench11being provided on the same side surface of the semiconductor substrate1. The recess13and the trench11may be formed by photolithography, and an etching process may use dry etching, and etching gas may be C4F6. After the recess13is formed by photolithography, it is necessary to fill the recess13with photoresist to form a mask for etching the trench11. After the trench11is etched, it is also necessary to clean the photoresist filling the recess13. In view of the fact that the trench11is deeper than the recess13, in this exemplary embodiment, the recess13is firstly etched by photolithography, and then the trench11is etched by photolithography, which facilitates cleaning of the photoresist after the recess13and the trench11are etched. It should be noted that, in this exemplary embodiment, as shown inFIG.8, the isolation region5may indicate a spatial region which may penetrate the entire semiconductor substrate1in a layer direction. The active region6may also indicate a spatial region which may penetrate the entire semiconductor substrate1in a layer direction.

As shown inFIG.9, S2may include: fill the trench with an insulation material, so as to form a first isolation dam2. In this exemplary embodiment, as shown inFIG.9, before or after filling the trench with an insulation material, so as to form a first isolation dam2, an insulation material layer032may be deposited on one side, provided with the recess13, of the semiconductor substrate1according to a shape of the side of the recess. The insulation material layer032may be made from an insulating material, for example silicon oxide. The insulation material layer032may use deposition methods of chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.

As shown inFIG.10, the method of manufacturing a semiconductor structure may further include: form a gate material layer033on one side, away from the electrical isolation layer12, of the insulation material layer032. The gate material layer033may use deposition methods of chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The gate material layer033may be made from a doped polysilicon conductor.

As shown inFIG.11, the method of manufacturing a semiconductor structure may further include: perform etching back, chemical mechanical polishing (CMP), cleaning, etc. on the gate material layer033and the insulation material layer032, so as to form a portion of the insulation material layer032into gate insulation layers32of the plurality of switching transistors, and to form a portion of the gate material layer033into the gates33of the plurality of switching transistors, where the gate insulation layers32of each switching transistor are arranged independently of one another and the gates33of each switching transistor are arranged independently of one another.

As shown inFIG.12, the method of manufacturing a semiconductor structure may further include: arrange a mask on an upper surface of the semiconductor structure shown inFIG.12, and form a portion of the semiconductor substrate into a channel portion31of the switching transistor by an ion implantation technology. A doping type of the channel portion31may be the same as that of the electrical isolation layer12. Specifically, the ion implantation technology may provide initial energy for doped ions, and the doped ions may reach a preset depth of the semiconductor substrate under the action of the initial energy, such that a target depth of the semiconductor substrate may be subjected to ion doping. In addition, the mask may block entering of the ions into the semiconductor substrate, so a target position of the semiconductor substrate may be subjected to ion doping by combining an opening shape of the mask and the initial energy of the ions.

As shown inFIG.13, the method of manufacturing a semiconductor structure may further include: arrange the mask on the upper surface of the semiconductor structure shown inFIG.13, and form a portion of the semiconductor substrate into a second isolation dam4by an ion implantation manner. A doping type of the second isolation dam is different from that of the source/the drain of the switching transistor.

In this exemplary embodiment,FIG.14is a partial enlarged diagram ofFIG.13, andFIG.14shows a partial enlarged diagram of position A of an oval dashed box inFIG.13. The forming a portion of the semiconductor substrate into a second isolation dam4by an ion implantation manner may include: perform ion doping on a first structure portion41of the semiconductor substrate, so as to form the first structure portion41into at least a portion of the second isolation dam4, where the first structure portion41may be located between the first isolation dam and the electrical isolation layer, and the first structure portion41may be connected between the electrical isolation layer and the first isolation dam2in an abutting manner.

As shown inFIG.14, the forming a portion of the semiconductor substrate into a second isolation dam4by an ion implantation manner may further include: perform ion doping on a second structure portion42of the semiconductor substrate, so as to form the second structure portion42into at least a portion of the second isolation dam4, one end, facing the electrical isolation layer, of the first isolation dam2being embedded in the second structure portion42. The second isolation dam4may be composed of the first structure portion41subjected to ion doping and the second structure portion42subjected to ion doping.

It should be noted that after the first structure portion41of the semiconductor substrate is subjected to ion doping, so as to form the first structure portion41into a portion of the second isolation dam4, the ion implantation technology may be stopped, and doped ions implanted into the first structure portion41may move, by diffusion, to a position where the second structure portion42is located, thereby forming the second structure portion42into a portion of the second isolation dam4.

In this exemplary embodiment, as shown inFIG.13, a width L1of the second isolation dam may be greater than a width L2of an opening of a top of the trench. The width L1of the second isolation dam may be 1.2-1.5 times of a width L2of the opening of the top of the trench, and a direction of the width is perpendicular to the side wall of the trench. A distance between a side surface, facing the electrical isolation layer12, of the first isolation dam2and a side surface, facing the electrical isolation layer, of the second isolation dam4is greater than or equal to 15 nm. That is, a distance between of a bottom of the first isolation dam2and a bottom of the second isolation dam4is greater than or equal to 15 nm. The height of the first isolation dam2may be 4-5 times of the height of the second isolation dam4, a direction of the height is perpendicular to a plane where the electrical isolation layer is located. The width of the second isolation dam may be defined by the mask, that is, a width of an opening of the mask equals the width of the second isolation dam.

As shown inFIG.15, the method of manufacturing a semiconductor structure may further includes: form a portion of the semiconductor substrate into a first source/a first drain and a second source/a second drain of the switching transistor by an ion implantation technology, where the source and the drain are embedded in the active region and located on two opposite sides of the gate insulation layer, and the source/the drain are respectively connected to the channel portion. As shown inFIG.15, the first source/the first drain may include a first lightly doped source/a first lightly doped drain351and a first heavily doped source/a first heavily doped drain352, the first lightly doped source/the first lightly doped drain351is connected to a first side of the channel portion31, and the first heavily doped source/the first heavily doped drain352is connected to the first lightly doped source/the first lightly doped drain351. An ion doping concentration of the first heavily doped source/the first heavily doped drain352is greater than that of the first lightly doped source/the first lightly doped drain351, and a doping type of the first lightly doped source/the first lightly doped drain351and a doping type of the first heavily doped source/the first heavily doped drain352are the same. The second source/the second drain may include: a second lightly doped source/a second lightly doped drain341and a second heavily doped source/a second heavily doped drain342. The second lightly doped source/the second lightly doped drain341is connected to a second side of the channel portion31, and the first side and the second side of the channel portion are opposite each other, that is, an orthographic projection of the gate33on a plane where the channel portion31is located is located between the first side and the second side of the channel portion. The second heavily doped source/the second heavily doped drain342is connected to the second lightly doped source/the second lightly doped drain341. An ion doping concentration of the second heavily doped source/the second heavily doped drain342is greater than that of the second lightly doped source/the second lightly doped drain341, and a doping type of the second heavily doped source/the second heavily doped drain342and a doping type of the second lightly doped source/the second lightly doped drain341are the same.

As shown inFIG.15, the method of manufacturing a semiconductor structure may further include: covering one side, provided with the trench11, of the semiconductor substrate1with an encapsulation layer7, where the encapsulation layer7may be made from silicon nitride, which has relatively strong hardness and may protect the semiconductor structure.

It will become easy for a person of ordinary skill in the art to conceive of other embodiments of the present disclosure after considering the specification and implementing contents disclosed herein. The present disclosure is intended to cover any modification, use or adaptive change of the present disclosure, which follows general principles of the present disclosure and includes common knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and the embodiments are merely regarded as exemplary, with a true scope and spirit of the present disclosure being indicated by the claims.

It should be understood that the present disclosure is not limited to precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from the scope of the present disclosure. The scope of the present disclosure is merely limited by the appended claims.