Patent ID: 12232315

DETAILED DESCRIPTION

Certain example embodiments provide a semiconductor storage device that can be made smaller than those in the related art.

In general, according to an embodiment, a semiconductor storage device includes a plurality of conductor layers, a plurality of bit lines, a first row of pillars, a second row of pillars, and an insulator. The plurality of conductor layers is stacked in a first direction. The plurality of bit lines is spaced from each other in a second direction that intersects the first direction. Each of the bit lines extends in a third direction intersecting the first and second directions. The first row of pillars is along the second direction. Each of the pillars in the first row extends through the plurality of conductor layers in the first direction and includes a semiconductor layer electrically connected to one of the bit lines. The second row of pillars is along the second direction. Each of the pillars in the second row extends through the plurality of conductor layers in the first direction and includes a semiconductor layer electrically connected to one of the bit lines. The first and second rows of pillars are spaced from each other in the third direction. The insulator electrically separates at least some of the conductor layers into two regions adjacent to each other in the third direction. A first interval in the second direction between adjacent pillars in the first row is less than a second interval in the second direction between adjacent pillars in the second row.

Hereinafter, the certain example embodiments will be described with reference to the accompanying drawings. In order to facilitate understanding of the description, the same components are, in general, designated by the same reference numerals in the different drawings, and duplicate description of repeated aspects may be omitted.

A first embodiment will be described. The semiconductor storage device10according to the first embodiment is a nonvolatile storage device comprising a NAND flash memory.FIG.1is a block diagram illustrating a configuration example of a memory system including a semiconductor storage device10. This memory system includes a memory controller1and a semiconductor storage device10. Although a plurality of semiconductor storage devices10may be actually provided in the memory system ofFIG.1, only one is illustrated inFIG.1. The specific configuration of the semiconductor storage device10will be described below. This memory system may be connected to a host device (“host”) or the like. The host is, for example, an electronic device such as a personal computer or a mobile terminal such as smart phone or the like.

The memory controller1controls writing of data to the semiconductor storage device10in response to a write request from the host. The memory controller1also controls reading of data from the semiconductor storage device10in response to a read request from the host.

Between the memory controller1and the semiconductor storage device10, several signals such as a chip enable signal /CE, a ready/busy signal /RB, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal /WE, read enable signals RE and /RE, a write protect signal /WP, a data signal DQ <7:0>, data strobe signals DQS and /DQS are transmitted and/or received.

The chip enable signal /CE is a signal for enabling the semiconductor storage device10. The ready/busy signal /RB is a signal for indicating whether the semiconductor storage device10is in a ready state or a busy state. The “ready state” is a state in which an external command can be accepted. The “busy state” is a state in which an external command cannot be accepted. The command latch enable signal CLE is a signal indicating that the signal DQ <7:0> is a command. The address latch enable signal ALE is a signal indicating that the signal DQ <7:0> is an address. The write enable signal /WE is a signal for capturing a received signal into the semiconductor storage device10, and is asserted by the memory controller1each time a command, an address, and data are received. The memory controller1instructs the semiconductor storage device10to capture the signal DQ <7:0> while the signal /WE is at an “L (Low)” level.

The read enable signals RE and /RE are signals for the memory controller1to read data from the semiconductor storage device10. These signals are used, for example, to control the operation timing of the semiconductor storage device10when outputting the signal DQ <7:0>. The write protect signal /WP is a signal for instructing the semiconductor storage device10to prohibit data writing and erasing. The signal DQ <7:0> is data transmitted and received between the semiconductor storage device10and the memory controller1, and includes commands, addresses, and data. The data strobe signals DQS and /DQS are signals for controlling the input/output timing of the signal DQ <7:0>.

The memory controller1includes a RAM301, a processor302, a host interface303, an ECC circuit304, and a memory interface305. The RAM301, the processor302, the host interface303, the ECC circuit304, and the memory interface305are connected to each other by an internal bus306.

The host interface303outputs the request received from the host, user data (write data), and the like to the internal bus306. Further, the host interface303transmits the user data read from the semiconductor storage device10, the response from the processor302, and the like to the host.

The memory interface305controls a process of writing user data and the like to the semiconductor storage device and a process of reading the user data from the semiconductor storage device10based on the instruction of the processor302.

The processor302controls the memory controller1in an integrated manner. The processor302is, for example, a CPU, an MPU, or the like. When receiving a request from the host via the host interface303, the processor302controls in response to the request. For example, the processor302instructs the memory interface305to write user data and parity to the semiconductor storage device10in response to the request from the host. Further, the processor302instructs the memory interface305to read the user data and the parity from the semiconductor storage device10in response to the request from the host.

The processor302determines a storage region (memory region) on the semiconductor storage device10with respect to the user data stored in the RAM301. User data is stored in the RAM301via the internal bus306. The processor302determines the memory region for the page-based data (page data), which is a write unit. The user data stored on one page of the semiconductor storage device10is also referred to as “unit data” below. The unit data is generally encoded and stored in the semiconductor storage device10as a codeword. In the present embodiment, encoding is not essential. The memory controller1may store the unit data in the semiconductor storage device10without encoding, butFIG.1illustrates a configuration in which encoding is performed as an example of the configuration. If the memory controller1does not encode, the page data will match the unit data. Further, one codeword may be generated based on one unit data, or one codeword may be generated based on the divided data in which the unit data is divided. Moreover, one codeword may be generated by using a plurality of unit data.

The processor302determines the memory region of the semiconductor storage device10to be written for each unit data. A physical address is assigned to the memory region of the semiconductor storage device10. The processor302manages the memory region to which the unit data is written by using the physical address. The processor302specifies the determined memory region (physical address) and instructs the memory interface305to write user data to the semiconductor storage device10. The processor302manages the correspondence between the logical address (logical address managed by the host) of the user data and the physical address. When the processor302receives a read request including a logical address from the host, the processor302identifies the physical address corresponding to the logical address, specifies the physical address, and instructs the memory interface305to read the user data.

The ECC circuit304encodes the user data stored in the RAM301to generate a codeword. Further, the ECC circuit304decodes the codeword read from the semiconductor storage device10.

The RAM301temporarily stores the user data received from the host until the user data is stored in the semiconductor storage device10, or temporarily stores the data read from the semiconductor storage device10until the user data is transmitted to the host. The RAM301is, for example, a general-purpose memory such as SRAM or DRAM.

FIG.1illustrates a configuration example in which the memory controller1includes the ECC circuit304and the memory interface305, respectively. Alternatively, the ECC circuit304may be built in the memory interface305. Further, the ECC circuit304may be built in the semiconductor storage device10. The specific configuration and arrangement of each element illustrated inFIG.1are not particularly limited.

When a write request is received from the host, the memory system inFIG.1operates as follows. The processor302temporarily stores the data to be written in the RAM301. The processor302reads the data stored in the RAM301and inputs the data to the ECC circuit304. The ECC circuit304encodes the input data and inputs the codeword to the memory interface305. The memory interface305writes the input codeword to the semiconductor storage device10.

When a read request is received from the host, the memory system inFIG.1operates as follows. The memory interface305inputs the codeword read from the semiconductor storage device10to the ECC circuit304. The ECC circuit304decodes the input codeword and stores the decoded data in the RAM301. The processor302transmits the data stored in the RAM301to the host via the host interface303.

The configuration of the semiconductor storage device will be described. As illustrated inFIG.2, the semiconductor storage device10includes a memory cell array430, a sense amplifier440, a row decoder450, an input/output circuit401, a logic control circuit402, a sequencer421, a register422, a voltage generation circuit423, an input/output pad group411, a logic control pad group412, and a power supply input terminal group413.

The memory cell array430is a portion that stores data. The memory cell array430has a plurality of memory cell transistors MT associated with a plurality of bit lines BL and a plurality of word lines WL. The specific configuration of the memory cell array430will be described below with reference toFIGS.3to6.

The sense amplifier440is a circuit for adjusting the voltage applied to the bit line BL and reading the voltage of the bit line BL and converting the read voltage into data. At the time of reading the data, the sense amplifier440acquires the read data read from the memory cell transistor MT to the bit line BL and transfers the acquired read data to the input/output circuit401. When writing data, the sense amplifier440transfers the write data written via the bit line BL to the memory cell transistor MT. The operation of the sense amplifier440is controlled by the sequencer421.

The row decoder450is a circuit configured as a group of switches for applying a voltage to each of the word line WLs. The row decoder450receives a block address and a row address from the register422, selects the corresponding block based on the block address, and selects the corresponding word line WL based on the row address. The row decoder450switches the opening and closing of the above switch group so that the voltage from the voltage generation circuit423is applied to the selected word line WL. The operation of the row decoder450is controlled by the sequencer421.

The input/output circuit401transmits and receives the signal DQ <7:0>, and the data strobe signals DQS and /DQS to and from the memory controller1. The input/output circuit401transfers the command and address in the signal DQ <7:0> to the register422. Further, the input/output circuit401transmits and receives write data and read data to and from the sense amplifier440.

The logic control circuit402receives the chip enable signal /CE, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal /WE, the read enable signals RE and /RE, and the write protect signal /WP from the memory controller1. Further, the logic control circuit402transfers the ready/busy signal /RB to the memory controller1to notify the present state of the semiconductor storage device10to the outside.

The sequencer421controls the operation of each portion including the memory cell array430based on the control signals input from the memory controller1to the input/output circuit401and the logic control circuit402.

The register422is a portion that temporarily stores commands and addresses. The register422stores commands for instructing a write operation, a read operation, an erasing operation, and the like. The command is input from the memory controller1to the input/output circuit401, and then transferred from the input/output circuit401to the register422and stored.

The register422also stores the address corresponding to the above command. The address is input from the memory controller1to the input/output circuit401, and then transferred from the input/output circuit401to the register422and stored.

Further, the register422also stores the state information indicating the operation state of the semiconductor storage device10. The state information is updated by the sequencer421each time according to the operation state of the memory cell array430and the like. The state information is output from the input/output circuit401to the memory controller1as a state signal in response to the request from the memory controller1.

The voltage generation circuit423is a portion that generates the voltage required for each of the data write operation, read operation, and erasing operation in the memory cell array430. Such a voltage includes, for example, a voltage applied to each word line WL, a voltage applied to each bit line BL, and the like. The operation of the voltage generation circuit423is controlled by the sequencer421.

The input/output pad group411is a portion including a plurality of terminals (pads) for transmitting and receiving each signal between the memory controller1and the input/output circuit401. Each terminal is individually provided corresponding to the signal DQ <7:0> and the data strobe signals DQS and/DQS.

The logic control pad group412is a portion including a plurality of terminals (pads) for transmitting and receiving each signal between the memory controller1and the logic control circuit402. Each terminal is individually provided corresponding to the chip enable signal /CE, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal /WE, the read enable signal RE and /RE, the write protect signal /WP, and the ready/busy signal /RB.

The power supply input terminal group413is a portion including a plurality of terminals for receiving each voltage required for the operation of the semiconductor storage device10. The voltage applied to each terminal includes power supply voltages Vcc, VccQ, and Vpp, and a ground voltage Vss.

The power supply voltage Vcc is a circuit power supply voltage supplied from the outside as an operation power supply, and is, for example, a voltage of about 3.3 V. The power supply voltage VccQ is, for example, a voltage of 1.2 V. The power supply voltage VccQ is a voltage used when transmitting and receiving signals between the memory controller1and the semiconductor storage device10. The power supply voltage Vpp is a power supply voltage higher than the power supply voltage Vcc, for example, a voltage of 12 V.

A specific configuration of the memory cell array430will be described.FIG.3is an equivalent circuit diagram illustrating the configuration of the memory cell array430. As illustrated inFIG.3, the memory cell array430includes a plurality of string units SU0to SU3. Each string unit SU0to SU3includes a plurality of cell string SRs. Further, each cell string SR includes, for example, eight memory cell transistors MT0to MT7and two select transistors STD and STS. The number of memory cell transistors and select transistors in the cell string SR may be different from the example illustrated inFIG.1.

The plurality of string units SU0to SU3configure one block as a whole, and a plurality of such blocks are provided in the memory cell array430. InFIG.3, only a single block is illustrated, and the other blocks are omitted.

In the following description, each of the string units SU0to SU3may be referred to as “string unit SU” without distinction. Similarly, each of the memory cell transistors MT0to MT7may be referred to as “memory cell transistor MT” without distinction.

Each string unit SU includes the same number of cell string SRs as N bit lines BL0to BL (N-1) provided. N is a positive integer. The cell string SR is formed so that the memory cell transistors MT0to MT7and the select transistors STD and STS are arranged in series. As will be described below, the cell string SR is formed along a pillar50inside a memory hole MH inFIG.4. The pillar50is a columnar body having a substantially cylindrical shape, and is also referred to as “memory pillar”.

The memory cell transistors MT0to MT7in the cell string SR are disposed in series between the source of the select transistor STD and the drain of the select transistor STS. The drain of the select transistor STD is connected to one of the bit lines BL0and the like. The source of the select transistor STS is connected to the source line SL. In the following description, each of the bit lines BL1to BL(N-1) may be referred to as “bit line BL” without distinction.

As will be described below, each memory cell transistor MT is configured as a transistor having a charge storage layer at the gate portion. The amount of charge stored in the charge storage layer corresponds to the data stored in the memory cell transistor MT. The memory cell transistor MT may be a charge trap type using, for example, a silicon nitride film as the charge storage layer, or a floating gate type using, for example, a silicon film as the charge storage layer.

The gates of the plurality of select transistors STD in the string unit SU0are all connected to a select gate line SGD0. The select gate line SGD0is a line to which a voltage for switching the opening/closing of each select transistor STD is applied. Similarly, for the string units SU1to SU3, select gate lines SGD1to SGD3for applying a voltage to the select transistor STD are provided corresponding to each string unit SU.

The gates of the plurality of select transistors STS in the string unit SU0are all connected to a select gate line SGS0. The select gate line SGS0is a line to which a voltage for switching the opening/closing of each select transistor STS is applied. Similarly, for the string units SU1to SU3, select gate lines SGS1to SGS3for applying a voltage to the select transistor STS are provided corresponding to each string unit SU. The select gate line SGS may be shared between the string units SU0to SU3constituting one block, and the gates of all the select transistors STS in the string units SU0to SU3may be connected to the common select gate line SGS.

Each gate of the memory cell transistors MT0to MT7is connected to word lines WL0to WL7. Voltages are applied to the word lines WL0to WL7for the purpose of switching the opening and closing of the memory cell transistors MT0to MT7, changing the amount of charge accumulated in each charge storage layer of the memory cell transistors MT0to MT7, and the like.

The writing and reading of data in the semiconductor storage device10are collectively performed for each unit referred to as “page” in the plurality of memory cell transistors MT connected to any word line WL in any one of the string units SU. On the other hand, the erasing of data in the semiconductor storage device10is collectively performed for all the memory cell transistors MT in the block. As a specific method for such writing, reading, and erasing data, various known methods may be adopted, and detailed description thereof will be omitted.

FIG.4schematically illustrates a perspective view of the configuration of the memory cell array430and the portion in the vicinity thereof of the semiconductor storage device10. As illustrated inFIG.4, the semiconductor storage device10includes a substrate20, an insulator layer21, a semiconductor layer22, and a plurality of insulator layers30and a conductor layer40.

The substrate20is a plate-shaped member having a flat surface on the z-direction side ofFIG.4, and is, for example, a silicon wafer. The insulator layer21, the semiconductor layer22, the insulator layer30, the conductor layer40, and the like described below are a plurality of layers formed by, for example, CVD film formation on the upper surface side of the substrate20. For example, an element isolation area20iis provided on the surface of the substrate20. The element isolation area20iis, for example, an insulating region containing silicon oxide, and is a part of the insulating region that partitions the source and drain regions of a transistor Tr.

The insulator layer21is a layer formed of an insulating material such as silicon oxide. A peripheral circuit including the above-mentioned transistor Tr, wiring LIN, and the like are formed on the surface side of the substrate20. This peripheral circuit includes the sense amplifier440, the row decoder450, and the like illustrated inFIG.2. The insulator layer21covers the entire peripheral circuit.

The semiconductor layer22is a layer that functions as the source line SL inFIG.3. The semiconductor layer is formed of a silicon-containing material, such as impurity-doped polycrystalline silicon. The semiconductor layer22is embedded in the insulator layer21at a portion below the memory cell array430.

The semiconductor layer22may be entirely formed of a semiconductor material such as silicon, but may have a two-layer structure composed of a semiconductor layer22aand a conductive layer22bas illustrated in the example ofFIG.4. The semiconductor layer22ais a layer formed of a semiconductor material such as silicon, and the conductive layer22bis a layer formed of a metal material such as tungsten.

A plurality of the insulator layer30and the conductor layer40are formed above the semiconductor layer22and are alternately arranged in the z direction ofFIG.4.

The conductor layer40is a conductive layer formed of, for example, a material containing tungsten. The conductor layers40are used as the word lines WL0to WL7and the select gate lines SGS1, SGD1, and the like in FIG.3. The insulator layer30is disposed at a position between the conductor layers40adjacent to each other and electrically insulates between the two. The insulator layer30is formed of, for example, a material containing silicon oxide.

In the region where the plurality of insulator layers30and the conductor layers40are stacked in the z direction, a plurality of memory holes MH penetrate the plurality of insulator layers30and the conductor layers40in the z direction, and pillars50having a substantially cylindrical shape are formed inside the memory holes MH. Each pillar50is formed in a range from the insulator layer30on the most z-direction side to the semiconductor layer22.

FIG.5illustrates a cross section of the pillar50when cut along a plane (y-z plane) passing through the central axis along the longitudinal direction thereof. Further,FIG.6illustrates a cross section of the pillar50when cut along a plane (x-y plane) perpendicular to the central axis thereof and passing through the conductor layer40.

As illustrated inFIG.6, the pillar50has a circular or elliptical cross-sectional shape. The pillar50has a body51and a stacked film52.

The body51has a core portion51aand a semiconductor layer51b. The semiconductor layer51bis formed of, for example, a material made of amorphous silicon, and is a portion where a channel such as a memory cell transistor MT is formed. The core portion51ais formed of an insulating material such as silicon oxide, and is provided inside the semiconductor layer51b. The entire body51may be the semiconductor layer51b, and the inner core portion51amay not be provided.

The stacked film52is a multi-layer film covering the outer periphery of the body51. The stacked film52has, for example, a tunnel insulating film52aand a charge capture film52b. The tunnel insulating film52ais the innermost film formed. The tunnel insulating film52acontains, for example, silicon oxide or silicon oxide and silicon nitride. The tunnel insulating film52ais a potential barrier between the body51and the charge capture film52b. For example, when electrons are injected from the body51into the charge capture film52b(write operation) and when holes are injected from the body51into the charge capture film52b(erasing operation), electrons and holes pass (tunneling) through the potential barrier of the tunnel insulating film52a, respectively.

The charge capture film52bis a film covering the outside of the tunnel insulating film52a. The charge capture film52bcontains, for example, silicon nitride and has a trap site that traps charges in the film. The portion of the charge capture film52bsandwiched between the conductor layer40, which is the word line WL, and the body serves as the storage region of the memory cell transistor MT, namely, as the charge storage layer described above. The threshold voltage of the memory cell transistor MT changes depending on the presence or absence of charges on the charge capture film52bor the amount of the charges. As a result, the memory cell transistor MT stores the information.

As illustrated inFIG.5, the outer peripheral surface of the conductor layer40, which is the word line WL, is covered with a barrier film45and a block insulating film46. The barrier film45is a film for improving the adhesion between the conductor layer40and the block insulating film46. For the barrier film45, for example, when the conductor layer40is tungsten, a stacked structural film of titanium nitride and titanium is selected.

The block insulating film46is a film for preventing back tunneling of charges from the conductor layer40to the stacked film52side. The block insulating film46is, for example, a silicon oxide film or a metal oxide film. One example of a metal oxide is an aluminum oxide.

A cover insulating film31is provided between the insulator layer30and the charge capture film52b. The cover insulating film31contains, for example, silicon oxide. The cover insulating film31is a film for protecting the charge capture film52bfrom being etched in the replacement step of replacing a sacrifice layer with the conductor layer40. If the replacement step is not used to form the conductor layer40, the cover insulating film31may be omitted.

As described above, the inside of the portion of the pillar50to which each conductor layer40is connected functions as a transistor. That is, each pillar50is a portion of the cell string SR illustrated inFIG.3, and a plurality of transistors are connected in series along the longitudinal direction thereof. Each conductor layer40is connected to the gate of each transistor via the stacked film52. The semiconductor layer51binside the transistor functions as a channel of the transistor.

A part of each of the transistors arranged in series as described above along the longitudinal direction of the pillar50functions as a plurality of memory cell transistors MT inFIG.3. Further, the transistors formed on both sides of the plurality of memory cell transistors MT arranged in series function as the select transistors STD and STS inFIG.3.

Returning toFIG.4and the description is continued. As illustrated inFIG.4, the plurality of bit lines BL are provided above each pillar50. Each bit line BL is formed as a linear wiring extending in the x direction inFIG.4. The bit lines BL are arranged along the y direction inFIG.4. The upper end of the pillar50is connected to one of the bit lines BL via a contact Cb. As a result, the semiconductor layer51bof each pillar50is electrically connected to the bit line BL.

At the lower end of the pillar50, the stacked film52is removed, and the semiconductor layer51bis connected to the semiconductor layer22. As a result, the semiconductor layer22that functions as the source line SL and the channel of each transistor are electrically connected.

The stacked conductor layer40and the insulator layer30are divided into a plurality of regions by a slit ST. The slit ST is a linear groove extending in the y direction ofFIG.4, and is formed to a depth reaching, for example, the semiconductor layer22. In an example, an insulating spacer is formed on the inner surface of the slit ST, and a conductive material is then filled into the region inside the insulating spacer. The insulating spacer is, for example, silicon oxide. The conductive material is, for example, tungsten or polysilicon. With such a configuration, the slit ST can be used, for example, as a wiring for adjusting the potential of the semiconductor layer22. The insulating spacer formed on the inner surface of the slit ST is also referred to as “insulator91” below.

The upper portion of the stacked conductor layer40and the insulator layer30is separated by a slit SHE. The slit SHE is a shallow groove extending in the y direction inFIG.4. The slit SHE is formed to a depth that extends only into the conductor layer40provided as the select gate wire SGD among the plurality of conductor layers40. The inside of the slit SHE is filled with, for example, an insulating material. The insulating spacer filled inside the slit SHE is also referred to as “insulator92” below.

Hereinafter, the configuration of each portion will be described by using the x direction, y direction, and z direction illustrated inFIG.4. The z direction is a direction from the bottom to the top in the figure, and is the direction along which the plurality of conductor layers are stacked. The x direction is a direction that intersects the z direction, and is the direction in which each bit line BL extends. The y direction is a direction that intersects both the z direction and the x direction, and is the direction in which the plurality of bit lines BL are spaced from each other.

A specific arrangement of the pillars50and the like in the first embodiment will be described with reference toFIG.7. InFIG.7, the configuration of the portion of the memory cell array430between a pair of slits ST, that is, the configuration of the portion between a pair of insulators91is schematically illustrated in a top plan view.

As illustrated inFIG.7, the region where the plurality of pillars50are disposed in the top plan view is divided into a plurality of regions by the insulator91of the slit ST and the insulator92of the slit SHE. Each region divided in this way is also referred to as “cell region CAR” below. In addition, each cell region CAR may be distinguished from each other and may be referred to as “cell region CAR1” or “cell region CAR2”. In the example ofFIG.7, the portion between the slit ST on the x direction side and the slit SHE on the −x direction side is the cell region CAR1. Further, the portion between the slit ST on the −x direction side and the slit SHE on the x direction side is the cell region CAR2.

The slit ST and the slit SHE divide the region where the plurality of pillars50are disposed into a plurality of cell regions CAR arranged in the x direction by the insulators91and92provided inside the slits ST and the slit SHE, respectively. Each of the insulators91and92extends in the plurality of conductor layers40in the z direction and the y direction and divides the plurality of conductor layers40in the y direction.

As described above, each pillar50penetrates the plurality of conductor layers40in the z direction. A group of pillars50in one cell region CAR belong to a common string unit SU.

In each cell region CAR, each pillar50is connected to one of the bit lines BL via a contact Cb. In other words, each bit line BL is connected to one of the pillars50two-dimensionally disposed in a top view as illustrated inFIG.7.

In the first embodiment, a dummy pillar50D is formed in a part of the region between the pair of slits ST. The dummy pillar50D has the same configuration as the pillar50and penetrates the conductor layers40in the z direction like the pillars50. However, since the dummy pillar50D is not connected to a bit line BL via a contact Cb, the dummy pillar50D is not used for data storage. As illustrated inFIG.7, when viewed along the z direction, the slit SHE and the insulator92inside the slit SHT pass through a position overlapping each dummy pillar50D. InFIG.7, the dummy pillar50D is depicted with hatching so that the dummy pillar50D can be distinguished from the pillar50.

For convenience of description, the row formed by the pillars50arranged linearly in the y direction is also referred to as “row LN” below. In each cell region CAR, a plurality of rows LN are arranged in the x direction.

Among a plurality of rows LN, the one closest to the insulators91and92(slit ST and slit SHE) in the x direction is also referred to as “end row LNe” below. Further, among the plurality of rows LN, those located at different positions from the end row LNe in the x direction are also referred to as “inner row LNi” below. The inner row LNi may be referred to as a “first row” in the present embodiment. The plurality of pillars50constituting the inner row LNi may be referred to as to a “first pillar” for the first embodiment. The end row LNe may be referred to as a “second row” for the first embodiment. The plurality of pillars50constituting the end row LNe may be referred to as a “second pillar” for the first embodiment. In one cell region CAR, a plurality of inner rows LNi are provided, and a part of the plurality of inner rows LNi is adjacent to the end row LNe.

As illustrated inFIG.7, in the first embodiment, the plurality of inner rows LNi are arranged in the x direction. Among a pair of inner rows LNi adjacent to each other in the x direction, the pillars50in one inner row LNi are disposed at positions shifted in the y direction with respect to the pillars50in the other inner row LNi. Further, the pillars50in the end row LNe are disposed at positions shifted in the y direction with respect to the pillars50in the inner row LNi adjacent to the end row LNe.

As illustrated inFIG.7, the pillars50in the inner row LNi have a pitch of approximately equal intervals along the y direction. On the other hand, the arrangement pitch of each pillar50in the end row LNe on the insulator92(slit SHE) side (specifically, in the portion where the dummy pillar50D is disposed) is partially expanded (enlarged) to be more than the arrangement pitch of each pillar50in the inner row LNi. The “arrangement pitch” in this context is the distance between centers of the pillars50adjacent to each other in the y direction.

In order to explain the reason for such a configuration, the configuration according to comparative examples will be described with reference toFIGS.8and9.

In the comparative example ofFIG.8, the dummy pillars50D are linearly arranged along the y direction. Immediately above the dummy pillars50D, the slit SHE and the insulator92also extend linearly in the y direction. In this comparative example, the pillars50are arranged at a pitch of approximately equal intervals within all the rows LN including the end row LNe.

In the example ofFIG.8, four rows LN are provided along the x direction in one cell region CAR. That is, if the total number of rows LN in the cell region CAR is defined as a “consecutive number”, then consecutive number in the example ofFIG.8is 4.

As described above, each bit line BL needs to be connected to one of the pillars50disposed in the cell region CAR. Here, if one-half of the arrangement pitch of the bit lines BL is defined as “BLHP” (Bit Line Half Pitch), then BLHP is calculated by the following equation (1):
BLHP=(arrangement pitch of pillars50in the y direction)/the consecutive number/2

For example, when the arrangement pitch of the pillars50in the y direction is 152 nm and the consecutive number is 4 (as illustrated inFIG.8), the value of BLHP is 152/4/2=19 nm.

A range AR11(illustrated inFIG.8) is the distance in the y direction having the same dimension as the arrangement pitch of the pillars50. In a cell region CAR, inside this range AR11, four pillars50(that is, the consecutive number of pillars) are arranged in the x direction, and therefore it is necessary to have the same number of bit lines BL within the range AR11. This is the reason why BLHP is a function of the consecutive number in Equation (1).

In order to reduce the size of the semiconductor storage device10, it is necessary to reduce at least one of the arrangement pitch of the pillars50or BLHP. When the arrangement pitch of the pillars50is reduced, eventually a manufacturing process limit or the like approaches and it becomes increasingly difficult to make the arrangement pitch smaller via this route, thus increasing the consecutive number to make the BLHP smaller may be an alternative in some instances.

FIG.9illustrates an example in which the consecutive number is increased to 5 from 4 (the configuration ofFIG.8). A range AR12illustrated inFIG.9is the distance in the y direction having the same dimension as the arrangement pitch of the pillars50, similarly to the AR11as described above. In the example ofFIG.9, five bit lines BL are disposed in this range AR12, and as a result, the BLHP is reduced. The value of BLHP in the example ofFIG.8was 152 nm/4/2=19 nm, whereas the value of BLHP in the example ofFIG.9is 152 nm/5/2=15.2 nm.

In this way, if the consecutive number is increased by 1 for the purpose of reducing BLHP, the value of BLHP drops significantly from 19 nm to 15.2 nm. However, the difficulty of processing the bit lines BL may increase significantly, and therefore in reality it may be difficult to increase the consecutive number. As described above, in the configuration of the related art, since it is necessary to change the consecutive number one by one, it may be difficult to reduce the size of the semiconductor storage device10by reducing the BLHP.

However, as described with reference toFIG.7, in the first embodiment, the arrangement pitch of each pillar50in the end row LNe on the insulator92(slit SHE) side is partially enlarged. Ranges AR1and AR2illustrated inFIG.7both the match the dimension of one of the arrangement pitches inFIG.7of the pillars50in the y direction. The range AR1is the range corresponding to the portion where the arrangement pitch of pillars50in the end row LNe is enlarged. The range AR2is the range corresponding to the portion where the arrangement pitch in the end row LNe is not enlarged.

Therefore, in the cell region CAR1, the consecutive number is 4 inside the range AR1and 5 inside the range AR2. As described above, in the first embodiment, by enlarging the arrangement pitch of pillars50in the end row LNe, the consecutive number in the whole is set to be between 4 and 5. The region of the cell region CAR1in the range AR1corresponds to a “first region” in the present embodiment, and the region in the range AR2corresponds to a “second region” in the present embodiment. The number of rows LN in the first region (4 in the present embodiment) is one less than the number of rows LN in the second region (5 in the present embodiment). Such a first region and a second region can be similarly defined in the cell regions CAR other than the cell region CAR1.

In the first embodiment, the portion where the arrangement pitch of each pillar50in the end row LNe is enlarged and the portion where the arrangement pitch is not enlarged are substantially the same in the dimensions along the y direction. Therefore, since the overall consecutive number can be regarded as 4.5, the value of BLHP calculated by Equation (1) is 152 nm/4.5/2=16.88 nm.

The value of BLHP (16.88 nm) is thus smaller than 19 nm. which occurs when the consecutive number is 4, but larger than 15.2 nm, which occurs when the consecutive number is 5. That is, it is possible to reduce the BLHP and the size of the semiconductor storage device10within a range in which the difficulty of processing the bit line BL does not increase significantly.

In the first embodiment, the insulator92inside the slit SHE is not linear along the y direction, and has a convex portion921protruding in the x direction and a convex portion922protruding in the −x direction.

The convex portion921protrudes so as to enter the portion of the cell region CAR1on the x direction side toward the portion where the arrangement pitch of each pillar50in the end row LNe is enlarged. Further, the convex portion922protrudes so as to enter the portion of the cell region CAR2on the −x direction side toward the portion where the arrangement pitch of each pillar50in the end row LNe is enlarged.

In the first embodiment, a pair of cell region CAR1and cell region CAR2are adjacent to each other with the insulator92of the slit SHE interposed therebetween. A cell region CAR1corresponds to a “first cell region” in the first embodiment. A cell region CAR2corresponds to a “second cell region” in the first embodiment.

The convex portions921and922are formed in the insulator92(slit SHE) between the two as described above. The convex portion921is a portion that protrudes toward a portion where the arrangement pitch of the pillars50in the end row LNe of the cell region CAR1is enlarged, and corresponds to a “first convex portion” in the present embodiment. Further, the convex portion922is a portion that protrudes toward a portion where the arrangement pitch of the pillars50in the end row LNe of the cell region CAR2is enlarged, and corresponds to a “second convex portion” in the first embodiment.

The first convex portion and the second convex portion are disposed at different positions in the y direction. With such a configuration, the dimensions of the cell regions CAR1and CAR2along the x direction become smaller, and therefore the semiconductor storage device10can be further miniaturized.

The number of bit lines BL passing above each of the pillars50changes according to the total quantity number of the inner rows LNi and the end rows LNe in the cell region CAR, that is, the consecutive number. In the first embodiment, the total quantity number of the inner rows LNi and the end rows LNe in each of the cell regions CAR divided by the insulators91and92is 5. In such a configuration, the number of bit lines BL passing immediately above each of the pillars50is approximately 3. The number of bit lines BL passing immediately above the pillars50is approximately 3 when the consecutive number exceeds 4 but is 6 or less. Therefore, in the first embodiment, the plurality of pillars50include the pillars50above which three bit lines BL pass directly.

A second embodiment will be described. In the following, the points different from the above-described first embodiment will be mainly described, and the points common to the first embodiment will be omitted as appropriate.

FIG.10schematically illustrates an arrangement of the pillars50and the like according to the second embodiment in the same manner as inFIG.7. As illustrated inFIG.10, the insulator92(slit SHE) of the second embodiment also has the convex portion921and the convex portion922as in the first embodiment. However, in the second embodiment, the dummy pillar50D is not provided in the memory cell array430. The insulator92of the second embodiment passes between the pillar50in the end row LNe of the cell region CAR1and the pillar50in the end row LNe of the cell region CAR2.

Also in the present embodiment, in the end row LNe of the cell region CAR1, the arrangement pitch of the pillars is partially enlarged, and the first convex portion (convex portion921) enters toward the enlarged portion. Further, in the end row LNe of the cell region CAR2, the arrangement pitch of the pillars50is partially enlarged, and the second convex portion (convex portion922) enters toward the enlarged portion. In the present embodiment, since the dummy pillar50D is not provided, the distance between the end row LNe of the cell region CAR1and the end row LNe of the cell region CAR2along the x direction is shorter than that in the first embodiment. Even with such a configuration, the same effect as that described in the first embodiment is obtained.

A third embodiment will be described. In the following, the points different from the above-described second embodiment will be mainly described, and the points common to the second embodiment will be omitted as appropriate.

FIG.11schematically illustrates an arrangement of the pillars50and the like according to the third embodiment in the same manner as inFIG.10. As illustrated inFIG.11, in the third embodiment, each insulator92(slit SHE) extends linearly along the y direction. On the other hand, the insulator91(slit ST) has a first convex portion (convex portion911) and a second convex portion (convex portion912) as in the insulator92in the second embodiment (FIG.10).

In the present embodiment, each of a pair of cell regions CAR adjacent to each other with the insulator91interposed therebetween is the cell region CAR1(first cell region) and the cell region CAR2(second cell region). In each cell region CAR, the arrangement pitch of each pillar50in the end row LNe on the insulator91side is partially enlarged more than the arrangement pitch of each pillar50in the inner row LNi.

Even with such a configuration, the same effect as that described in the first embodiment is obtained.

A fourth embodiment will be described. In the following, the points different from the first embodiment will be mainly described, and the points common to the first embodiment will be omitted as appropriate.

FIG.12schematically illustrates an arrangement of the pillars50and the like according to the fourth embodiment in the same manner as inFIG.7. As illustrated inFIG.12, in the fourth embodiment, the region between the pair of insulators91(slits ST) is divided into three cell regions CAR1, CAR2, and CAR3by the two insulators92(slit SHE). In each cell region CAR, the arrangement pitch of each pillar50in the end row LNe on the insulator92side is partially enlarged more than the arrangement pitch of each pillar50in the inner row LNi.

In the end row LNe on the slit SHE side of the cell region CAR1, two pillars50and one dummy pillar50D are alternately arranged in the y direction. Therefore, the number of pillars50in the end row LNe is ⅔ of the number of pillars50in the inner row LNi.

In the end row LNe on the x direction side of the cell region CAR2, one pillar50and two dummy pillars50D are alternately arranged in the y direction. Therefore, the number of pillars50in the end row LNe is ⅓ of the number of pillars50in the inner row LNi.

Even in the end row LNe on the −x direction side of the cell region CAR2, one pillar50and two dummy pillars50D are alternately arranged in the y direction. Therefore, the number of pillars50in the end row LNe is also ⅓ of the number of pillars50in the inner row LNi.

Therefore, in the cell region CAR2, the total value of the number of pillars50in the end row LNe is ⅔ of the number of pillars50in the inner row LNi.

In the end row LNe on the slit SHE side of the cell region CAR3, two pillars50and one dummy pillar50D are alternately arranged in the y direction. Therefore, the number of pillars50in the end row LNe is ⅔ of the number of pillars50in the inner row LNi.

As described above, in any of the three cell regions CAR1, CAR2, and CAR3provided in the present embodiment, the total value of the number of pillars50in the end row LNe is ⅔ of the number of pillars50in one inner row LNi. Since the consecutive number of each cell region CAR in the present embodiment can be regarded as 4+⅔, that is, 4.66, the value of BLHP calculated by Equation (1) is 152/4.66/2=16.28 nm.

FIG.13schematically illustrates how the plurality of pillars50are distributed in the three cell regions CAR1, CAR2, and CAR3. InFIG.13, the reference numeral110indicates the pillar50disposed in a portion of the cell region CAR1excluding the end row LNe on the slit SHE side. Further, the reference numeral111indicates the pillar50disposed in the end row LNe on the slit SHE side of the cell region CAR1.

The reference numeral120indicates the pillar50disposed in the portion of the cell region CAR2(that is, each inner row LNi) excluding the two end rows LNe. Further, the reference numeral121indicates the pillar50disposed in the end row LNe on the −x direction side of the cell region CAR2. Further, the reference numeral122indicates the pillar50disposed in the end row LNe on the x direction side of the cell region CAR2.

The reference numeral130indicates the pillar50disposed in the portion of the cell region CAR3excluding the end row LNe on the slit SHE side. Further, the reference numeral132indicates the pillar50disposed in the end row LNe on the slit SHE side of the cell region CAR3.

As described above, the number of pillars50in the portion marked with the reference numeral111is ⅔ of the number of pillars50in the inner row LNi. Further, the number of pillars50in the portion marked with the reference numeral122is ⅓ of the number of pillars50in the inner row LNi. The portion marked with the reference numeral111and the portion marked with the reference numeral122are the portions in which the pillars50for one row of the inner row LNi are divided between the cell region CAR1and the cell region CAR2. Similarly, the portion marked with the reference numeral121and the portion with the reference numeral132are the portions in which the pillars50for one row of the inner row LNi is divided between the cell region CAR2and the cell region CAR3.

Assuming that the number of cell regions CAR arranged in the x direction, that is, the number of cell regions CAR divided by the insulators91and92is “n” (n=3 in the present embodiment), the arrangement pitch of the pillars50in the end row LNe may be adjusted so that the total value of the number of pillars50in the end row LNe of each cell region CAR is the number of the pillars50in one inner row LNi×(n−1)/n. The first embodiment ofFIG.7corresponds to the case where n=2 in the above. Even with the above configuration, the same effect as that described in the first embodiment is obtained.

A fifth embodiment will be described. In the following, the points different from the first embodiment will be mainly described, and the points common to the first embodiment will be omitted as appropriate.

FIG.14schematically illustrates an arrangement of the pillars50and the like according to the fifth embodiment in the same manner as inFIG.7. As illustrated inFIG.14, in the fifth embodiment, the region between the pair of insulators91(slits ST) is divided into four cell regions CAR1, CAR2, CAR3, and CAR4by the three insulators (slits SHE). In each cell region CAR, the arrangement pitch of each pillar50in the end row LNe on the slit SHE side is partially enlarged more than the arrangement pitch of each pillar50in the inner row LNi.

In the end row LNe on the slit SHE side of the cell region CAR1, three pillars50and one dummy pillar50D are alternately arranged in the y direction. Therefore, the number of pillars50in the end row LNe is ¾ of the number of pillars50in the inner row LNi.

In the end row LNe on the x direction side of the cell region CAR2, one pillar50and three dummy pillars50D are alternately arranged in the y direction. Therefore, the number of pillars50in the end row LNe is ¼ of the number of pillars50in the inner row LNi.

In the end row LNe on the −x direction side of the cell region CAR2, two pillars50and two dummy pillars50D are alternately arranged in the y direction. Therefore, the number of the pillars50in the end row LNe is 2/4 of the number of the pillars50in the inner row LNi.

Therefore, in the cell region CAR2, the total value of the number of the pillars50in the end row LNe is ¾ of the number of the pillars50in one inner row LNi.

In the end row LNe on the x direction side of the cell region CAR3, two pillars50and two dummy pillars50D are alternately arranged in the y direction. Therefore, the number of the pillars50in the end row LNe is 2/4 of the number of the pillars50in the inner row LNi.

In the end row LNe on the −x direction side of the cell region CAR3, one pillar50and three dummy pillars50D are alternately arranged in the y direction. Therefore, the number of pillars50in the end row LNe is ¼ of the number of pillars50in the inner row LNi.

Therefore, in the cell region CAR3, the total value of the number of the pillars50in the end row LNe is ¾ of the number of pillars50in one inner row LNi.

In the end row LNe on the slit SHE side of the cell region CAR4, three pillars50and one dummy pillar50D are alternately arranged in the y direction. Therefore, the number of pillars50in the end row LNe is ¾ of the number of pillars50in the inner row LNi.

As described above, in any of the four cell regions CAR1, CAR2, CAR3, and CAR4provided in the present embodiment, the total value of the number of the pillars50in the end row LNe is ¾ of the number of the pillars50in one inner row LNi. Since the consecutive number of each cell region CAR in the present embodiment can be regarded as 4+¾, that is, 4.75, the value of BLHP calculated by Equation (1) is 152/4.75/2=16 nm.

FIG.15schematically illustrates how the plurality of pillars50are distributed in the four cell regions CAR1, CAR2, CAR3, and CAR4in the same manner as inFIG.13. InFIG.15, the reference numeral110indicates the pillar50disposed in a portion of the cell region CAR1excluding the end row LNe on the slit SHE side. Further, the reference numeral111indicates the pillar50disposed in the end row LNe on the slit SHE side of the cell region CAR1.

The reference numeral120indicates the pillar50disposed in the portion of the cell region CAR2(that is, each inner row LNi) excluding the two end rows LNe. Further, the reference numeral121indicates the pillar50disposed in the end row LNe on the −x direction side of the cell region CAR2. Further, the reference numeral122indicates the pillar50disposed in the end row LNe on the x direction side of the cell region CAR2.

The reference numeral130indicates the pillar50disposed in the portion of the cell region CAR3(that is, each inner row LNi) excluding the two end rows LNe. Further, the reference numeral131indicates the pillar50disposed in the end row LNe on the −x direction side of the cell region CAR3. Further, the reference numeral132indicates the pillar50disposed in the end row LNe on the x direction side of the cell region CAR3.

The reference numeral140indicates the pillar50disposed in the portion of the cell region CAR4excluding the end row LNe on the slit SHE side. Further, the reference numeral142indicates the pillar50disposed in the end row LNe on the slit SHE side of the cell region CAR4.

As described above, the number of pillars50in the portion marked with the reference numeral111is ¾ of the number of pillars50in the inner row LNi. Further, the number of pillars50in the portion marked with reference numeral122is ¼ of the number of pillars50in the inner row LNi. The portion marked with the reference numeral111and the portion marked with the reference numeral122are the portions in which the pillars50for one row of the inner row LNi are divided between the cell region CAR1and the cell region CAR2. Similarly, the portion marked with the reference numeral121and the portion with the reference numeral132are the portions in which the pillars50for one row of the inner row LNi is divided between the cell region CAR2and the cell region CAR3. Further, the portion marked with the reference numeral131and the portion marked with the reference numeral142are the portions in which the pillars50for one row of the inner row LNi is divided between the cell region CAR3and the cell region CAR4.

As described in the fourth embodiment, assuming that the number of cell regions CAR arranged in the x direction, that is, the number of cell regions CAR divided by the insulators91and92is “n”, the arrangement pitch of the pillars50in the end row LNe may be adjusted so that the total value of the number of pillars50in the end row LNe of each cell region CAR is the number of the pillars50in one inner row LNi×(n−1)/n. The present embodiment corresponds to the case where n=4 in the above. Even with the above configuration, the same effect as that described in the first embodiment is obtained.

A sixth embodiment will be described. In the following, the points different from the first embodiment will be mainly described, and the points common to the first embodiment will be omitted as appropriate.

FIG.16schematically illustrates an arrangement of the pillars50and the like according to the sixth embodiment in the same manner as inFIG.7. As illustrated inFIG.16, in the sixth embodiment, the region between the pair of insulators91(slit ST) is divided into four cell regions CAR1, CAR2, CAR3, and CAR4by the three insulators92(slit SHE).

In the present embodiment, the central slit SHE in the x direction extends linearly along the y direction. Directly under the central slit SHE, the dummy pillars50D are arranged in a straight line in the y direction.

The shapes of the two slits SHE other than the above are the same as the shapes of the slits SHE in the first embodiment (FIG.7). Further, the arrangement of the dummy pillars50D directly under the slit SHE is also the same as that of the first embodiment.

Since the configuration of the cell regions CAR1and CAR2in the sixth embodiment is the same as the configuration of the first embodiment, the consecutive number can be regarded as 4.5. Since the configuration of the cell regions CAR3and CAR4is the same as the configuration of the first embodiment but inverted with respect to the y-z plane, the consecutive number can also be regarded as 4.5. Even with such a configuration, the same effect as that described in the first embodiment is obtained.

The shapes of the slit ST and the slit SHE (that is, the shapes of the insulators91and92) are not limited to the examples described in the above embodiments, and various shapes may be adopted.FIGS.17A and17Billustrate modification examples in which the shape of the slit SHE is changed. For example, as illustrated inFIG.17A, in the end row LNe, one pillar50and one dummy pillar50D may be alternately arranged in the y direction, and then the slit SHE may pass directly above each dummy pillar50D. As in this example, the arrangement pitch of the pillars50in the end row LNe may be enlarged more than the arrangement pitch of the pillars50in the inner row LNi at all intervals, not only a part.

Further, as illustrated inFIG.17B, in the end row LNe, the three pillars50and the three dummy pillars50D may be alternately arranged in the y direction, and then the slit SHE may pass directly above each dummy pillar50D.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.