Patent ID: 12218092

DETAILED DESCRIPTION

According to various example embodiments, a semiconductor chip may be mounted on a package substrate by connection pins that are inserted into insertion holes formed in the package substrate without using connection members such as bumps.

Thus, since the connection pins are inserted into the insertion holes, an overall package thickness may be reduced. Further, since chip pads of the semiconductor chip are directly connected to internal wirings of the package substrate by the connection pins, a routing space may be reduced and electrical characteristics may be improved.

FIGS.1to26represent non-limiting, example embodiments as described herein. Hereinafter, various example embodiments will be explained in detail with reference to the accompanying drawings.

FIG.1is a cross-sectional view illustrating a semiconductor package in accordance with example embodiments.FIG.2is an enlarged cross-sectional view illustrating a portion ‘A’ inFIG.1.FIG.3is a plan view illustrating the semiconductor package inFIG.1.FIG.1is a cross-sectional view taken along the line I-I inFIG.3.

Referring toFIGS.1to3, a semiconductor package10may include a package substrate100, a semiconductor chip200, a plurality of connection pins300and a molding member400. Additionally, in some example embodiments, the semiconductor package10may further include external connection members500.

In example embodiments, the package substrate100may be a multilayer circuit board having an upper surface102and a lower surface104facing each other. For example, the package substrate100may be a printed circuit board (PCB) including wirings respectively provided in a plurality of layers and vias connected to the wirings.

In particular, the package substrate100may include a plurality of stacked insulation layers110and wiring patterns120provided respectively in the insulation layers.

The package substrate100may include a first insulation layer110a, a second insulation layer110b, a third insulation layer110c, a fourth insulation layer110d, and a fifth insulation layer110esequentially stacked on one another. The first insulation layer110amay be an upper cover insulation layer, the second insulation layer110bmay be an upper insulation layer, the third insulation layer110cmay be a core layer, the fourth insulation layer110dmay be a lower insulation layer, and the fifth insulation layer110emay be a lower cover insulation layer.

For example, the insulation layer110may include an insulating material having a thermosetting resin such as epoxy resin or a thermoplastic resin such as polyimide. The insulation layer may include a resin impregnated in a core material such as organic fiber (glass fiber), for example, a prepreg, FR-4, BT (Bismaleimide Triazine), etc.

The wiring patterns120may include a first wiring pattern120a, a second wiring pattern120b, a third wiring pattern120c, and a fourth wiring pattern120d. The first wiring pattern120amay be formed on an upper surface of the second insulation layer110b, and the second wiring pattern120bmay be formed on an upper surface of the third insulation layer110c. The third wiring pattern120cmay be formed on a lower surface of the third insulation layer110c, and the fourth wiring pattern120dmay be formed on a lower surface of the fourth insulation layer110d. For example, the wiring pattern120may include a metal material such as copper, aluminum, etc. It will be understood that arrangements and numbers of the insulation layers and the wiring patterns are exemplary, and are not limited to the arrangement and numbers of insulation layers and wiring patterns illustrated and described.

The package substrate100may include a plurality of insertion holes112having different depths and extending from the upper surface102. For example, the insertion holes112may have a diameter within a range of about 15 μm to about 150 μm. The insertion holes112may extend from the upper surface102toward the lower surface104.

The plurality of insertion holes112may include a first insertion hole112a, a second insertion hole112b, a third insertion hole112c, and a fourth insertion hole112d. The first insertion hole112amay extend through the first insulation layer110afrom the upper surface102in a thickness direction to expose a portion of the first wiring pattern120a. The first insertion hole112amay have a first depth D1(see, e.g.,FIG.15) from the upper surface102to expose a portion of a first circuit layer. The portion of the first wiring pattern120aexposed by the first insertion hole112amay serve as a first connection pad to which a first connection pin300ais connected.

The second insertion hole112bmay be formed to extend through the first and second insulation layers110aand110bfrom the upper surface102in the thickness direction to expose a portion of the second wiring pattern120b. The second insertion hole112bmay have a second depth D2(see, e.g.,FIG.15) from the upper surface102greater than the first depth D1to expose a portion of a second circuit layer. The portion of the second wiring pattern120bexposed by the second insertion hole112bmay serve as a second connection pad to which a second connection pin300bis connected.

The third insertion hole112cmay be formed to extend through the first, second and third insulation layers110a,110band110cfrom the upper surface102in the thickness direction to expose a portion of the third wiring pattern120c. The third insertion hole112cmay have a third depth D3(see, e.g.,FIG.15) from the upper surface102greater than the second depth D2to expose a portion of a third circuit layer. The portion of the third wiring pattern120cexposed by the third insertion hole112cmay serve as a third connection pad to which a third connection pin300cis connected.

The fourth insertion hole112dmay be formed to extend through the first, second, third and fourth insulation layers110a,110b,110cand110dfrom the upper surface102in the thickness direction to expose a portion of the fourth wiring pattern120d. The fourth insertion hole112dmay have a fourth depth D4(see, e.g.,FIG.15) from the upper surface102greater than the third depth D3to expose a portion of a fourth circuit layer. The portion of the fourth wiring pattern120dexposed by the fourth insertion hole112dmay serve as a fourth connection pad to which the fourth connection pin300dis connected.

The semiconductor chip200may be disposed on the package substrate100. The semiconductor chip200may be mounted on the package substrate100through the connection pins300. A planar area of the semiconductor chip200may be smaller than a planar area of the package substrate100. When viewed from a plan view, the semiconductor chip200may be disposed within the planar area of the package substrate100.

The semiconductor chip200may include a plurality of chip pads230provided on a first surface212of the semiconductor chip200. The connection pins300having different heights may be provided on the plurality of chip pads230. Each of the connection pins300may have a diameter within a range of about 5 μm to about 95 μm.

A first connection pin300ahaving a first height H1may be formed on a first chip pad230aof the plurality of chip pads. A second connection pin300bhaving a second height H2may be formed on a second chip pad230b. The second height H2may be greater than the first height H1. A third connection pin300chaving a third height H3may be formed on a third chip pad230c. The third height H3may be greater than the second height H2. A fourth connection pin300dhaving a fourth height H4may be formed on a fourth chip pad230d. The fourth height H4may be greater than the third height H3. For example, the first to fourth heights may be within a range of about 15 μm to about 300 μm. A difference between the respective heights, for example, a difference between the second height and the first height may be within a range of about 15 μm to about 180 μm.

In example embodiments, the semiconductor chip200may be mounted on the package substrate100in a flip chip bonding manner. In this case, the semiconductor chip200may be mounted on the package substrate100such that an active surface on which the chip pads230are formed, that is, the first surface212faces the package substrate100. An underfill member350may be provided between the first surface212of the semiconductor chip200and the upper surface102of the package substrate100.

When the semiconductor chip200is disposed on the package substrate100, the connection pins300on the chip pads230may be inserted into the insertion holes formed in the package substrate100, and may be bonded to the portions of the wiring patterns exposed by the insertion holes by a thermo-compression process. The connection pins300may partially penetrate the insulating layers110of the package substrate100to serve as vias for electrically connecting the wiring patterns.

The first connection pin300amay be inserted into the first insertion hole112ato be electrically connected to the portion of the first wiring pattern120aexposed by the first insertion hole112a, that is, the first connection pad. The second connection pin300bmay be inserted into the second insertion hole112bto be electrically connected to the portion of the second wiring pattern120bexposed by the second insertion hole112b, that is, the second connection pad. The third connection pin300cmay be inserted into the third insertion hole112cto be electrically connected to the portion of the third wiring pattern120cexposed by the third insertion hole112c, that is, the third connection pad. The fourth connection pin300dmay be inserted into the fourth insertion hole112dto be electrically connected to the portion of the fourth wiring pattern120dexposed by the fourth insertion hole112d, that is, the fourth connection pad.

As illustrated inFIG.2, the second connection pin300bmay include a connection pillar30and a metal bonding layer32formed on a surface of the connection pillar30. The second connection pin300bmay be connected to the portion of the second wiring pattern120bexposed by the second insertion hole112bby a thermo-compression process. During the thermo-compression process, the metal bonding layer32may be melted at a high temperature while under compression to at least partially fill a space between a surface of the second connection pillar30and an inner surface of the second insertion hole112b. In this way, the second wiring pattern120bmay be electrically connected to the second wiring pattern120b. It is noted that the second connection pin300bis illustrated inFIG.2by way of example. A similar description applies for the remaining connection pins300but a repeated description thereof is omitted for conciseness.

As illustrated inFIG.3, the chip pads230of the semiconductor chip200may be arranged in an array form in a pad region R, and the connection pins300may be provided on the chip pads230, respectively, in the pad region R. In some example embodiments, dummy connection pillars may also be provided on the semiconductor chip200. For example, in some example embodiments, dummy connection pillars310may be provided in four corner regions of the semiconductor chip200respectively. The dummy connection pillars310may be provided respectively on dummy pads provided on the first surface212of the semiconductor chip200.

Each of the dummy connection pillars310may have a height less than the height H1of the first connection pin300a. Each of the dummy connection pillars300may have a diameter greater than the diameter of the connection pin300. The dummy connection pillars310may be disposed between the first surface212of the semiconductor chip200and the upper surface102of the package substrate100. When the semiconductor chip200is mounted via the connection pins300, the dummy connection pillars310may support the semiconductor chip200such that the semiconductor chip200is stably attached on the package substrate100.

In example embodiments, the molding member400may be formed on the package substrate100to protect the semiconductor chip200from the outside. The molding member may include an epoxy mold compound (EMC).

Outer connection pads for providing an electrical signal, that is, portions of the fourth wiring pattern120dexposed by the fifth insulating layer110e, may be provided on the lower surface104of the package substrate100. The external connection members500may be disposed on the outer connection pads of the package substrate100for electrical connection with an external device. For example, the external connection member500may be a solder ball. The semiconductor package10may be mounted on a module substrate (not illustrated) via the solder balls to constitute a memory module.

As mentioned above, the semiconductor package10may include the package substrate100having the insertion holes extending from the upper surface102in the thickness direction toward the lower surface104and exposing portions of the wiring patterns in different layers respectively; the semiconductor chip200arranged on the package substrate100such that the first surface212on which the chip pads230are formed faces the upper surface102of the package substrate100; and the plurality of connection pins300provided on the chip pads230and extending through the insertion holes112to be electrically connected to the exposed portions of the wiring patterns, respectively.

Accordingly, the semiconductor chip200may be mounted on the package substrate100by the connection pins300that are inserted into the insertion holes112formed in the package substrate100without using connection members such as bumps.

Thus, since the connection pins300are inserted into the insertion holes112, the overall package thickness may be reduced. Further, since the chip pads230of the semiconductor chip200are directly connected to the internal wirings of the package substrate100by the connection pins300, a routing space may be reduced and electrical characteristics may be improved.

Hereinafter, a method of manufacturing the semiconductor package inFIG.1will be explained.

FIGS.4to18are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with example embodiments.FIGS.5to10are enlarged cross-sectional views illustrating a portion ‘B’ inFIG.4.FIG.17is an enlarged cross-sectional view illustrating a portion ‘C’ inFIG.16.

Referring toFIGS.4to14, a plurality of connection pins300may be formed on chip pads230of a semiconductor chip, respectively.

First, the connection pins300may be formed on the chip pads230of a wafer W including the semiconductor chip in a wafer level.

In example embodiments, as illustrated inFIG.4, the wafer W may include a substrate210and the chip pads230provided in a first surface212of the substrate210. Although it is not illustrated in the figures, the wafer W may include an insulation interlayer on an active surface of the substrate210. For example, the chip pad230may be provided in an outermost insulation layer of the insulation interlayer. The substrate210may include a die region DA where circuit patterns and cells are formed and a scribe lane region SA surrounding the die region DA. As described later, the substrate210of the wafer W may be sawed along the scribe lane region SA dividing a plurality of the die regions DA.

For example, the substrate210may include may include silicon, germanium, silicon-germanium, or III-V compounds, e.g., GaP, GaAs, GaSb, etc. In some embodiments, the substrate210may be a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate.

Circuit patterns (not illustrated) may be provided in the active surface of the substrate210. The circuit patterns may include a transistor, a diode, etc. The circuit patterns may constitute circuit elements. The chip pad230may be electrically connected to the circuit elements by wirings in the insulation interlayer.

In example embodiments, first connection pins330amay be formed on first chip pads230aof the plurality of chip pads230.

First, as illustrated inFIG.5, an insulation layer pattern20may be formed on a front side212of the wafer W (hereinafter, referred to as the first surface of the substrate210for simplicity of explanation) to expose the plurality of chip pads, and then, a seed layer22may be formed on the chip pads.

For example, the insulation layer pattern20may include oxide, or nitride, etc., or a mixture thereof. The insulation layer pattern20may be formed by a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, an atomic layer deposition (ALD) process, a lower pressure chemical vapor deposition (LPCVD) process, a sputtering process, etc. Alternatively, the insulation layer pattern20may include a polymer layer formed by a spin coating process or a spray process. In case that a protective layer pattern for exposing the chip pads230is formed on the first surface212of the substrate210, the process of forming the insulation layer pattern may be omitted.

The seed layer22may include an alloy layer including titanium/copper (Ti/Cu), titanium/palladium (Ti/Pd), titanium/nickel (Ti/Ni), chrome/copper (Cr/Cu) or a combination thereof. The seed layer22may be formed by a sputtering process.

Then, as illustrated inFIG.6, a photoresist pattern24having a first opening26which exposes a portion of the seed layer22over the first chip pad230aof the plurality of chip pads may be formed on the first surface212of the substrate210.

After a photoresist layer is formed on the first surface of the substrate210to cover the chip pads, an exposure process may be performed on the photoresist layer to form the photoresist pattern24having the first opening26exposing the portion of the seed layer22on the first chip pad230aof the plurality of chip pads. A first height of a first connection pin to be formed in a later step may depend on a thickness of the photoresist pattern24. A diameter of the first connection pin may be determined by a diameter of the first opening26.

As illustrated inFIG.7, a conductive material may be formed to fill the first opening26of the photoresist pattern24to form a connection pillar30as the first connection pin. The conductive material may include nickel (Ni), copper (Cu), palladium (Pd), or platinum (Pt), etc.

As illustrated inFIGS.8and9, a metal bonding layer32may be formed on the connection pillar30. As shown inFIG.8, an exposure process may be performed on the photoresist pattern24to form a second opening28that exposes the connection pillar30. An outer surface of the connection pillar30may be completely exposed by the second opening28. Then, as shown inFIG.9, a plating process may be performed to form the metal bonding layer32on the surface of the connection pillar30and the surface of the seed layer22exposed by the second opening28. The metal bonding layer may include a metal material that has a lower melting point than the metal material of the connection pillar and is in a solid state at room temperature. For example, the metal bonding layer may include a solder material.

Alternatively, the metal bonding layer may be provided in the insertion holes112. That is, the process of forming the metal bonding layer on the connection pillar may be omitted. In this case, a process of forming a metal bonding layer to fill the insertion holes may be performed. For example, after a metal material of the metal bonding layer is formed to fill insertion holes formed in a package substrate, the connection pins may be inserted into the insertion holes and may be joined with the connection pins at a high temperature under compression such that the semiconductor chip is mounted on the package substrate.

As illustrated inFIG.10, after the photoresist pattern24is removed, the exposed portion of the seed layer22may be partially etched using the metal bonding layer32as a mask to form a seed layer pattern23. Thus, as shown inFIG.11, a first connection pin300ahaving a first height H1may be formed on the first chip pad230aof the plurality of chip pads. The first connection pin300amay include the connection pillar30formed on the first chip pad230aand the metal bonding layer32formed on the surface of the connection pillar30. The first connection pin300amay have a diameter within a range of about 5 μm to about 95 μm.

Referring toFIG.12, a second connection pin300bhaving a second height H2may be formed on a second chip pad230bof the plurality of chip pads230.

Processes the same as or similar to the processes described with reference toFIGS.5to10may be performed to form the second connection pin300bhaving the second height H2on the second chip pad230b. The second height H2may be greater than the first height H1.

Referring toFIG.13, a third connection pin300chaving a third height H3and a fourth connection pin300dhaving a fourth height H4may be formed on a third chip pad230cand a fourth chip pad230dof the plurality of chip pads230, respectively.

Processes the same as or similar to the processes described with reference toFIGS.5to10may be performed to from the third connection pin300chaving the third height H3on the third chip pad230c. The third height H3may be greater than the second height H2.

Processes the same as or similar to the processes described with reference toFIGS.5to10may be performed to from the fourth connection pin300dhaving the fourth height H4on the fourth chip pad230d. The fourth height H4may be greater than the third height H3.

For example, each of the first to fourth heights H1to H4may be within a range of about 15 μm to about 300 μm. A difference between the respective heights, for example, a difference between the second height and the first height may be within a range of about 15 μm to about 180 μm.

Accordingly, the connection pins300having different heights may be formed on the plurality of chip pads230, respectively. The first to fourth connection pins300a,300b,300dand300dhaving different heights H1, H2, H3, and H4may be formed on the first to fourth chip pads300a,300b,300cand300d, respectively. Each of the first to fourth connection pins300a,300b,300cand300dmay have a diameter within a range of about 5 μm to about 95 μm.

In example embodiments, before or after forming the first to fourth connection pins300a,300b,300cand300d, dummy connection pillars310(seeFIG.16) may be formed in four corner regions of the semiconductor chip200. Each of the dummy connection pillars may have a diameter greater than the diameter of the connection pin300. Each of the dummy connection pillars310may have a height less than the height H1of the first connection pin300a. The dummy connection pillars310may support the semiconductor chip200such that the semiconductor chip200is stably attached onto the package substrate100through the connection pins300in a subsequent mounting process.

Referring toFIG.14, the wafer W may be sawed along the scribe lane region SA to form an individual semiconductor chip200.

Before performing the sawing process, a second surface214of the substrate210may be grinded.

Referring toFIG.15, a package substrate100having insertion holes112a,112b,112cand112dwith different depths may be provided.

In example embodiments, the package substrate100may be a multilayer circuit board having an upper surface102and a lower surface104facing each other. For example, the package substrate100may be a printed circuit board (PCB) including wirings respectively provided in a plurality of layers and vias connected to the wirings.

As illustrated inFIG.15, the package substrate100may include a plurality of stacked insulation layers110and wiring patterns120a,120b,120c,120dand120dprovided respectively in the insulation layers.

In particular, first to fifth insulation layers110a,110b,110c,110dand110emay be sequentially stacked on one another. The first insulation layer110amay be an upper cover insulation layer, the second insulation layer110bmay be an upper insulation layer, the third insulation layer110cmay be a core layer, the fourth insulation layer110dmay be a lower insulation layer, and the fifth insulation layer110emay be a lower cover insulation layer.

For example, the insulation layer may include an insulating material having a thermosetting resin such as epoxy resin or a thermoplastic resin such as polyimide. The insulation layer may include a resin impregnated in a core material such as organic fiber (glass fiber), for example, a prepreg, FR-4, or BT (Bismaleimide Triazine), etc.

A first wiring pattern120amay be formed on an upper surface of the second insulation layer110b, and a second wiring pattern120bmay be formed on an upper surface of the third insulation layer110c. A third wiring pattern120cmay be formed on a lower surface of the third insulation layer110c, and a fourth wiring pattern120dmay be formed on a lower surface of the fourth insulation layer110d. For example, the wiring pattern may include a metal material such as copper, or aluminum, etc. It will be understood that arrangements and numbers of the insulation layers and the wiring patterns are exemplary, and are not limited thereto.

The plurality of insertion holes112a,112b,112cand112dhaving different depths and extending from the upper surface102may be formed in the insulating layer110of the package substrate100. The insertion holes may be formed by an etching process or a laser drilling process.

The first insertion hole112amay be formed to extend through the first insulation layer110afrom the upper surface102in a thickness direction. The first insertion hole112amay expose a portion of the first wiring pattern120a. The first insertion hole112amay have a first depth D1from the upper surface102to expose a portion of a first circuit layer. The portion of the first wiring pattern120aexposed by the first insertion hole112amay serve as a first connection pad to which the first connection pin300ais connected by a subsequent mounting process.

The second insertion hole112bmay be formed to extend through the first and second insulation layers110aand110bfrom the upper surface102in the thickness direction. The second insertion hole112bmay expose a portion of the second wiring pattern120b. The second insertion hole112bmay have a second depth D2from the upper surface102greater than the first depth D1to expose a portion of a second circuit layer. The portion of the second wiring pattern120bexposed by the second insertion hole112bmay serve as a second connection pad to which the second connection pin300bis connected by a subsequent mounting process.

The third insertion hole112cmay be formed to extend through the first, second and third insulation layers110a,110band110cfrom the upper surface102in the thickness direction. The third insertion hole112cmay expose a portion of the third wiring pattern120c. The third insertion hole112cmay have a third depth D3from the upper surface102greater than the second depth D2to expose a portion of a third circuit layer. The portion of the third wiring pattern120cexposed by the third insertion hole112cmay serve as a third connection pad to which the third connection pin300cis connected by a subsequent mounting process.

The fourth insertion hole112dmay be formed to extend through the first, second, third and fourth insulation layers110a,110b,110cand110dfrom the upper surface102in the thickness direction. The fourth insertion hole112dmay expose a portion of the fourth wiring pattern120d. The fourth insertion hole112dmay have a fourth depth D4from the upper surface102greater than the third depth D3to expose a portion of a fourth circuit layer. The portion of the fourth wiring pattern120dexposed by the fourth insertion hole112dmay serve as a fourth connection pad to which the fourth connection pin300dis connected by a subsequent mounting process.

Referring toFIGS.16and17, the semiconductor chip200may be mounted on the package substrate100.

In example embodiments, the semiconductor chip200may be mounted on the package substrate100in a flip chip bonding manner. In this case, the semiconductor chip200may be mounted on the package substrate100such that the active surface on which the chip pads230are formed, that is, the first surface212faces the package substrate100. In some example embodiments, an underfill member350may be provided between the first surface212of the semiconductor chip200and the upper surface102of the package substrate100.

When the semiconductor chip200is disposed on the package substrate100, the connection pins300on the chip pads230may be inserted into the insertion holes formed in the package substrate100, and may be bonded to the portions of the wiring patterns exposed by the insertion holes by a thermo-compression process.

The first connection pin300amay be inserted into the first insertion hole112ato be electrically connected to the portion of the first wiring pattern120aexposed by the first insertion hole112a, that is, the first connection pad. The first connection pin300amay physically contact the first connection pad. The second connection pin300bmay be inserted into the second insertion hole112bto be electrically connected to the portion of the second wiring pattern120bexposed by the second insertion hole112b, that is, the second connection pad. The second connection pin300bmay physically contact the second connection pad. The third connection pin300cmay be inserted into the third insertion hole112cto be electrically connected to the portion of the third wiring pattern120cexposed by the third insertion hole112c, that is, the third connection pad. The third connection pin300cmay physically contact the third connection pad. The fourth connection pin300dmay be inserted into the fourth insertion hole112dto be electrically connected to the portion of the fourth wiring pattern120dexposed by the fourth insertion hole112d, that is, the fourth connection pad. The fourth connection pin300dmay physically contact the fourth connection pad.

As illustrated inFIG.17, the second connection pin300bmay include the connection pillar30and the metal bonding layer32formed on a surface of the connection pillar30. The second connection pin300bmay be connected to the portion of the second wiring pattern120bexposed by the second insertion hole112bby a thermo-compression process. In the thermos-compression process, the metal bonding layer32may be melted at a high temperature to at least partially fill a space between a surface of the second connection pillar30and an inner surface of the second insertion hole112b.

Alternatively, the metal bonding layer32may be formed to fill in the insertion holes112. In this case, after a metal material of the metal bonding layer is filled in the insertion holes formed in the package substrate100, the connection pins300may be inserted into the insertion holes, and the connection pins300may be bonded to portions of the wiring patterns at a high temperature while under compression. Alternatively, the connection pins300may be directly bonded to the portions of the wiring patterns by, for example, Cu—Cu bonding.

Referring toFIG.18, a molding member400may be formed on the package substrate100to cover the semiconductor chip200. For example, the molding member400may include an insulating material such as an epoxy molding compound.

Then, in some example embodiments, external connection members such as solder balls may be disposed on outer connection pads on the lower surface104of the package substrate100, that is, portions of the fourth wiring pattern120dexposed by the fifth insulation layer110e, as illustrated inFIG.1.

FIG.19is a cross-sectional view illustrating a semiconductor package in accordance with example embodiments.FIG.20is an enlarged cross-sectional view illustrating a portion ‘D’ of the semiconductor package ofFIG.19. The semiconductor package may be substantially the same as or similar to the semiconductor package described with reference toFIGS.1to3except for an additional support structure and second semiconductor chips. Thus, same reference numerals will be used to refer to the same or like elements and any further repetitive explanation concerning the above elements will be omitted for conciseness.

Referring toFIGS.19and20, a semiconductor package11may include a package substrate100, a first semiconductor chip200, a plurality of connection pins300, a support structure600, a plurality of additional semiconductor chips700and a molding member800. Additionally, in some example embodiments, the semiconductor package11may further include conductive connection members730for electrically connecting the additional semiconductor chips700to the package substrate100. Further, in some example embodiments, the semiconductor package11may further include external connection members900.

In example embodiments, the package substrate100may be a multilayer circuit board having an upper surface102and a lower surface104facing each other. For example, the package substrate100may be a printed circuit board (PCB) including wirings respectively provided in a plurality of layers and vias connected to the wirings.

The package substrate100may include a first wiring pattern120a, a second wiring pattern120b, a third wiring pattern120c, and a fourth wiring pattern120dstacked sequentially on one another.

The package substrate100may include a plurality of insertion holes112having different depths and extending from the upper surface102. For example, the insertion holes112may have a diameter within a range of about 15 μm to about 150 μm. The insertion holes112may extend from the upper surface102toward the lower surface104.

The plurality of insertion holes112may include a first insertion hole112a, a second insertion hole112b, a third insertion hole112c, and a fourth insertion hole112d. The first insertion hole112amay extend through a first insulation layer110afrom the upper surface102in a thickness direction to a portion of the first wiring pattern120a. The first insertion hole112amay have a first depth D1from the upper surface102to expose a portion of a first circuit layer. The portion of the first wiring pattern120aexposed by the first insertion hole112amay serve as a first connection pad to which a first connection pin300ais connected.

The second insertion hole112bmay be formed to extend through the first and second insulation layers110aand110bfrom the upper surface102in the thickness direction to expose a portion of the second wiring pattern120b. The second insertion hole112bmay have a second depth D2from the upper surface102greater than the first depth D1to expose a portion of a second circuit layer. The portion of the second wiring pattern120bexposed by the second insertion hole112bmay serve as a second connection pad to which a second connection pin300bis connected.

The third insertion hole112cmay be formed to extend through the first, second and third insulation layers110a,110band110cfrom the upper surface102in the thickness direction to expose a portion of the third wiring pattern120c. The third insertion hole112cmay have a third depth D3from the upper surface102greater than the second depth D2to expose a portion of a third circuit layer. The portion of the third wiring pattern120cexposed by the third insertion hole112cmay serve as a third connection pad to which a third connection pin300cis connected.

The fourth insertion hole112dmay be formed to extend through the first, second, third and fourth insulation layers110a,110b,110cand110dfrom the upper surface102in the thickness direction to expose a portion of the fourth wiring pattern120d. The fourth insertion hole112dmay have a fourth depth D4from the upper surface102greater than the third depth D3to expose a portion of a fourth circuit layer. The portion of the fourth wiring pattern120dexposed by the fourth insertion hole112dmay serve as a fourth connection pad to which the fourth connection pin300dis connected.

The first semiconductor chip200may be disposed on the package substrate100. The first semiconductor chip200may be mounted on the package substrate100through the connection pins300. The first semiconductor chip200may be a logic chip including a logic circuit. The logic chip may be a controller that controls memory chips.

The first semiconductor chip200may include a plurality of chip pads230provided on a first surface212thereof. The connection pins300having different heights may be provided on the plurality of chip pads230.

A first connection pin300ahaving a first height H1may be formed on a first chip pad230aof the plurality of chip pads. A second connection pin300bhaving a second height H2may be formed on a second chip pad230b. The second height H2may be greater than the first height H1. A third connection pin300chaving a third height H3may be formed on a third chip pad230c. The third height H3may be greater than the second height H2. A fourth connection pin300dhaving a fourth height H4may be formed on a fourth chip pad230d. The fourth height H4may be greater than the third height H3.

In example embodiments, the first semiconductor chip200may be mounted on the package substrate100in a flip chip bonding manner. In this case, the first semiconductor chip200may be mounted on the package substrate100such that an active surface on which the chip pads230are formed, that is, the first surface212faces the package substrate100.

When the first semiconductor chip200is disposed on the package substrate100, the connection pins300on the chip pads230may be inserted into the insertion holes formed in the package substrate100, and may be bonded to the portions of the wiring patterns exposed by the insertion holes by a thermo-compression process. The connection pins300may partially penetrate the insulating layers110of the package substrate100to serve as vias for electrically connecting the wiring patterns.

The first connection pin300amay be inserted into the first insertion hole112ato be electrically connected to the portion of the first wiring pattern120aexposed by the first insertion hole112a, that is, the first connection pad. The first connection pin300amay physically contact the first connection pad. The second connection pin300bmay be inserted into the second insertion hole112bto be electrically connected to the portion of the second wiring pattern120bexposed by the second insertion hole112b, that is, the second connection pad. The second connection pin300bmay physically contact the second connection pad. The third connection pin300cmay be inserted into the third insertion hole112cto be electrically connected to the portion of the third wiring pattern120cexposed by the third insertion hole112c, that is, the third connection pad. The third connection pin300cmay physically contact the third connection pad. The fourth connection pin300dmay be inserted into the fourth insertion hole112dto be electrically connected to the portion of the fourth wiring pattern120dexposed by the fourth insertion hole112d, that is, the fourth connection pad. The fourth connection pin300dmay physically contact the fourth connection pad.

As illustrated inFIG.20, the second connection pin300bmay include a connection pillar30and a metal bonding layer32formed on a surface of the connection pillar30. The second connection pin300bmay be connected to the portion of the second wiring pattern120bexposed by the second insertion hole112bby a thermo-compression process. During the thermos-compression process, the metal bonding layer32may be melted at a high temperature while under compression to at least partially fill a space between a surface of the second connection pillar30and an inner surface of the second insertion hole112b.

Returning toFIG.19, in example embodiments, the support structure600may be disposed on the upper surface102of the package substrate100to be spaced apart from the first semiconductor chip200. The support structure600may be attached on the upper surface102of the package substrate100using an adhesive film610. The support structure600may be disposed between the package substrate100and other electronic components to support other electronic components.

The support structure600may include a support spacer605and an adhesive film610attached to a lower surface of the support spacer605. For example, the adhesive film610may include a die adhesive film (DAF). The support spacer605may be attached on the upper surface102of the package substrate100using the adhesive film610by a die attach process.

In some example embodiments, the support structure600may include a plurality of support structures. For example, two support structures600may be disposed on sides of the first semiconductor chip200. A height of the support structure600from the package substrate100may be substantially the same as a height of the first semiconductor chip200.

In example embodiments, a plurality of the additional semiconductor chips700may be stacked on the first semiconductor chip200and the support structure600. The plurality of additional semiconductor chips700may include a second semiconductor chip700aand a third semiconductor chip700b. The second and third semiconductor chips700aand700bmay be attached on the support structure600using adhesive members710. For example, the second semiconductor chip700amay be attached to the support structure600and the first semiconductor chip200using a first adhesive member710a, and the third semiconductor chip700bmay be attached to the second semiconductor chip700ausing a second adhesive member710b. For example, the adhesive member710may include a die adhesive film (DAF). In some example embodiments, a planar area of one or more of the plurality of additional semiconductor chips700may be greater than a planar area of the first semiconductor chip200. In some example embodiments, a planar area of one or more of the plurality of additional semiconductor chips700may be greater than a combined planar area of the first semiconductor chip200and the support structure600. Accordingly, the second and third semiconductor chips700aand700bmay be supported and mounted by the support structure600on the package substrate100.

The plurality of additional semiconductor chips700may be electrically connected to the package substrate100by the conductive connection members730. In particular, the conductive connection member730may connect chip pads of the additional semiconductor chips700to substrate pads of the package substrate100, that is, portions of the first wiring pattern120aexposed by the first insulating layer110a. For example, the conductive connection member730may include a bonding wire. Accordingly, the additional semiconductor chips700may be stacked on the support structure600and may be electrically connected to the package substrate100by a plurality of the conductive connection members730.

The additional semiconductor chips700may include a memory chip including a memory circuit. For example, the additional semiconductor chips700may include a nonvolatile memory device such as a NAND flash memory. It will be understood that the number, sizes, arrangement, etc. of the additional semiconductor chips700are provided by way of example, and are not limited thereto.

In example embodiments, the molding member800may be formed on the package substrate100to protect the first semiconductor chip200, the support structure600and the additional semiconductor chips700from the environment. The molding member may include an epoxy mold compound (EMC).

Outer connection pads for providing an electrical signal, that is, portions of the fourth wiring120dexposed by the fifth insulating layer110emay be provided on the lower surface104of the package substrate100. External connection members900for electrical connection with an external device may be disposed on the outer connection pads of the package substrate100. For example, the external connection member900may be a solder ball. The semiconductor package11may be mounted on a module substrate (not illustrated) via the solder balls to constitute a memory module.

As mentioned above, the semiconductor package11may include the package substrate100, the first semiconductor chip200and the support structure600mounted on the package substrate100, the plurality of additional semiconductor chips700supported on the first semiconductor chip200and the support structure600, and the molding member800on the package substrate100covering the first semiconductor chip200, the support structure600and the additional semiconductor chips700.

The first semiconductor chip200may be mounted on the package substrate100through the connection pins300. When the semiconductor chip200is mounted on the package substrate100, the connection pins300on the chip pads230may be inserted into the insertion holes formed in the package substrate100, and may be bonded to the portions of the wiring patterns exposed by the insertion holes by a thermo-compression process. Accordingly, the connection pins300may partially penetrate the insulating layers110of the package substrate100to serve as vias for electrically connecting the wiring patterns.

Accordingly, it may be possible to reduce the overall package thickness and improve structural stability. Thus, the molding member may be prevented from getting through a space between the first semiconductor chip200and the package substrate100, and may be prevented from getting through a space between the first semiconductor chip200and the additional semiconductor chips700due to tilting of the first semiconductor chip200mounted by the flip-chip bonding manner.

Hereinafter, a method of manufacturing the semiconductor package inFIG.19will be explained.

FIGS.21to26are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with example embodiments.

Referring toFIG.21, a plurality of connection pins300may be formed on chip pads230of a first semiconductor chip200, respectively.

Processes the same as or similar to the processes described with reference toFIGS.4to14may be performed to form the connection pins300having different heights on the chip pads230.

A first connection pin300ahaving a first height H1may be formed on a first chip pad230aof the plurality of chip pads. A second connection pin300bhaving a second height H2may be formed on a second chip pad230b. The second height H2may be greater than the first height H1. A third connection pin300chaving a third height H3may be formed on a third chip pad230c. The third height H3may be greater than the second height H2. A fourth connection pin300dhaving a fourth height H4may be formed on a fourth chip pad230d. The fourth height H4may be greater than the third height H3. For example, the first to fourth heights may be within a range of 15 nm to 300 nm. A difference between the respective heights, for example, a difference between the second height and the first height may be within a range of about 15 nm to about 180 nm.

Referring toFIG.22, insertion holes112a,112b,112cand112dhaving different depths may be formed in a package substrate100.

For example, the insertion holes may be formed by an etching process or a laser drilling process.

A first insertion hole112amay be formed to extend through a first insulation layer110afrom an upper surface102in a thickness direction. The first insertion hole112amay expose a portion of a first wiring pattern120a. The first insertion hole112amay have a first depth D1from the upper surface102to expose a portion of a first circuit layer. The portion of the first wiring pattern120aexposed by the first insertion hole112amay serve as a first connection pad to which the first connection pin300ais connected by a subsequent mounting process.

A second insertion hole112bmay be formed to extend through the first and second insulation layers110aand110bfrom the upper surface102in the thickness direction. The second insertion hole112bmay expose a portion of the second wiring pattern120b. The second insertion hole112bmay have a second depth D2from the upper surface102greater than the first depth D1to expose a portion of a second circuit layer. The portion of the second wiring pattern120bexposed by the second insertion hole112bmay serve as a second connection pad to which the second connection pin300bis connected by a subsequent mounting process.

A third insertion hole112cmay be formed to extend through the first, second and third insulation layers110a,110band110cfrom the upper surface102in the thickness direction. The third insertion hole112cmay expose a portion of the third wiring pattern120c. The third insertion hole112cmay have a third depth D3from the upper surface102greater than the second depth D2to expose a portion of a third circuit layer. The portion of the third wiring pattern120cexposed by the third insertion hole112cmay serve as a third connection pad to which the third connection pin300cis connected by a subsequent mounting process.

A fourth insertion hole112dmay be formed to extend through the first, second, third and fourth insulation layers110a,110b,110cand110dfrom the upper surface102in the thickness direction. The fourth insertion hole112dmay expose a portion of the fourth wiring pattern120d. The fourth insertion hole112dmay have a fourth depth D4from the upper surface102greater than the third depth D3to expose a portion of a fourth circuit layer. The portion of the fourth wiring pattern120dexposed by the fourth insertion hole112dmay serve as a fourth connection pad to which the fourth connection pin300dis connected by a subsequent mounting process.

Referring toFIG.23, the first semiconductor chip200may be mounted on the package substrate100.

In example embodiments, the first semiconductor chip200may be mounted on the package substrate100in a flip chip bonding manner. In this case, the first semiconductor chip200may be mounted on the package substrate100such that an active surface on which the chip pads230are formed, that is, a first surface212faces the package substrate100.

When the first semiconductor chip200is disposed on the package substrate100, the connection pins300on the chip pads230may be inserted into the insertion holes formed in the package substrate100, and may be bonded to the portions of the wiring patterns exposed by the insertion holes by a thermo-compression process.

The first connection pin300amay be inserted into the first insertion hole112ato be electrically connected to the portion of the first wiring pattern120aexposed by the first insertion hole112a, that is, the first connection pad. The first connection pin300amay physically contact the first connection pad. The second connection pin300bmay be inserted into the second insertion hole112bto be electrically connected to the portion of the second wiring pattern120bexposed by the second insertion hole112b, that is, the second connection pad. The second connection pin300bmay physically contact the second connection pad. The third connection pin300cmay be inserted into the third insertion hole112cto be electrically connected to the portion of the third wiring pattern120cexposed by the third insertion hole112c, that is, the third connection pad. The third connection pin300cmay physically contact the third connection pad. The fourth connection pin300dmay be inserted into the fourth insertion hole112dto be electrically connected to the portion of the fourth wiring pattern120dexposed by the fourth insertion hole112d, that is, the fourth connection pad. The fourth connection pin300dmay physically contact the fourth connection pad.

Referring toFIG.24, at least one support structure600may be stacked on the package substrate100.

In example embodiments, the support structure600may be attached on the upper surface102of the package substrate100using an adhesive film610to be spaced apart from the first semiconductor chip200. Two support structures600may be disposed in both sides of the first semiconductor chip200. For example, the adhesive film610may include a die adhesive film (DAF). The support structure600may be attached on the upper surface102of the package substrate100using the adhesive film610by a die attach process.

A height of the support structure600from the package substrate100may be substantially the same as a height of the first semiconductor chip200. In some example embodiments, the height of the support structure may be greater than the height of the first semiconductor chip200.

Referring toFIG.25, a plurality of additional semiconductor chips700may be stacked on the first semiconductor chip200and the support structure600.

In some example embodiments, the additional semiconductor chips700may include a second semiconductor chip700aand a third semiconductor chip700b. The second and third semiconductor chips700aand700bmay be attached on the support structure600using adhesive members710. For example, the second semiconductor chip700amay be attached to the support structure600and the first semiconductor chip200using a first adhesive member710a, and the third semiconductor chip700bmay be attached to the second semiconductor chip700ausing a second adhesive member710b. A planar area of one or more of the additional semiconductor chips700may be greater than a planar area of the first semiconductor chip200. In some example embodiments, a planar area of one or more of the additional semiconductor chips700may be greater than a combined planar area of the first semiconductor chip200and the support structure600. Accordingly, the second and third semiconductor chips700aand700bmay be supported and mounted by the support structure600on the package substrate100.

The additional semiconductor chips700may be offset-aligned sequentially or in a zigzag manner. For example, the second and third semiconductor chips700aand700bmay be stacked in a cascade structure. The second and third semiconductor chips700aand700bmay be sequentially offset-aligned in a first lateral direction (right direction) of the package substrate100. The second and third semiconductor chips700aand700bmay be attached on the first semiconductor chip200and the support structure300using an adhesive film710such as DAF.

Then, a wire bonding process may be performed to connect chip pads of the second and third semiconductor chips700aand700bto substrate pads on the upper surface102of the package substrate100, that is, portions of the first wiring pattern120aexposed by the first insulating layer110a. The chip pads of the second and third semiconductor chips700aand700bmay be connected to the substrate pads by conductive connecting members730, that is, bonding wires.

Referring toFIG.26, a molding member800may be formed on the upper surface102of the package substrate100to cover the first semiconductor chip200, the support structure600and the additional semiconductor chips700. The molding member may include an epoxy mold compound (EMC).

Then, external connection members such as solder balls may be formed on outer connection pads on a lower surface104of the package substrate100, that is, portions of the fourth wiring pattern120dexposed by the fifth insulating layer110eas illustrated inFIG.19.

The semiconductor package may include semiconductor devices such as logic devices or memory devices. The semiconductor package may include logic devices such as central processing units (CPUs), main processing units (MPUs), or application processors (APs), or the like, and volatile memory devices such as DRAM devices, HBM devices, or nonvolatile memory devices such as flash memory devices, PRAM devices, MRAM devices, ReRAM devices, or the like.

The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in example embodiments without materially departing from the novel teachings and advantages described above. Accordingly, all such modifications are intended to be included within the scope of example embodiments as defined in the claims.