Patent ID: 12218655

DETAILED DESCRIPTION

In some applications, a transistor should be turned on with a gate-to-source voltage (Vgs) of, for example, 7V or higher. Such applications include buck converters and motor controllers, both of which include a high side (HS) transistor coupled to a low side (LS) transistor at a switch node. The gate driver for each HS and LS transistor, therefore, should be able to produce a suitably sized output voltage (e.g., 7V or higher). However, many semiconductor processes produce transistors for use in gate drivers that have a maximum rating for their Vgs that is smaller than the voltage needed to be produced on the output of the gate driver. Such transistors have limited Vgs voltage ratings due to the thin gate oxide layers formed on the gates of the transistors. In one example, 5V (Vgs) rated transistors are used in a gate driver whose output voltage needs to be higher than 5V. In one gate driver circuit, sub-rails are generated to produce supply voltages between the gate driver's main supply voltage and ground to ensure that the 5V Vgs of the transistors are not exceeded. Such gate drivers unfortunately may include pass-transistors that produce the sub-rails that are large in order to provide a sufficiently large current when the main supply voltage to the gate driver is fairly low. Further, such gate drivers may not produce adequate output voltage and current at lower levels of supply voltage. However, the gate drivers described herein address these problems.

FIG.1shows an example of a HS transistor coupled to a LS transistor at a switch node (SW). A gate driver100ais coupled to and drives a voltage on the gate of the HS transistor with respect to the SW node, and thus also connects to the SW node. A gate driver100bis coupled to and drives a voltage on the gate of the LS transistor with respect to ground, and thus also connects to ground. HS_ON is an input control signal to gate drive100aand dictates whether the HS transistor is to be on or off. LS_ON is an input control signal to gate driver100band dictates whether the LS transistor is to be on or off. Each gate driver100aand100bgenerally has the same circuit architecture, an example of which is shown in the schematic ofFIG.2.

FIG.2is a circuit schematic of a gate driver200in accordance with an example embodiment. Gate driver200can be used to implement either or both of gate drivers100aand100bofFIG.1. Gate driver200includes voltage terminals201and203and a gate terminal202. Gate202couples to the gate of the respective HS or LS transistor. Voltage terminal203couples to the SW node in the case of the HS transistor or to ground in the case of the LS transistor. Voltage terminal201is the supply voltage rail for the gate driver200.

Gate driver200includes transistors M1-M18, resistors R1-R5, dual-knee clamps206,208, and230, control logic circuit210, control logic circuit220, and inverter228. M1and M2are coupled in series between voltage terminal201and voltage terminal203. In this example, M1is a P-type MOSFET (PMOS transistor), and M2is an N-type MOSFET (NMOS transistor). The source of M1is coupled to voltage terminal201, and the source of M2is coupled to voltage terminal203. The drains of M1and M2are coupled together to form the gate terminal202. The gate driver200receives an input control signal205labeled “DRV” inFIG.2. Control signal DRV represents HS_ON or LS_ON inFIG.1. Responsive to DRV being logic high (“1”), the gate driver200turns on M1and turns off M2. With M1being on, the voltage on the gate terminal202is forced high towards VCC. With M2being on, the voltage on the gate terminal202is forced low towards ground/SW.

Dual-knee clamp206is coupled between voltage terminal201and the gate of M1. Dual-knee clamp208is coupled between the gate of M2and the voltage terminal203. Accordingly, dual-knee clamp206is coupled across the gate and source of M1, and dual-knee clamp is coupled across the gate and source of M2. Dual-knee clamp206ensures that the Vgs of M1does not exceed a safe operating voltage. In one example, M1and M2are 5V (Vgs) transistors and thus dual-knee clamp206ensures that Vgs of M1does not exceed 5V and dual-knee clamp208ensues that Vgs of M2also does not exceed 5V. The drain-to-source voltage (Vds) of M1and M2, however, are rated for much higher voltages (e.g., 20V).

M3and M4are NMOS transistors. The drains of M3and M4are coupled to the gate of M1. M1is turned on in response to M3and M4being turned on. M3is sized (size being the ratio of the channel width (W) to the channel length (L)) larger than M1. Accordingly, the current through M3is larger than the current through M4. In one example, the current through M3is 30 milli-amperes (mA), while the current through M4is 15 micro-amperes. M3thus represents a larger current path than the current path through M4between the gate of M1and the voltage terminal203. Control logic210controls the on and off state of transistors M3and M4and thus the on and off states of the larger and smaller current paths between the gate of M1and the voltage terminal203. Control logic210includes an edge-triggered flip-flop212, an AND gate214, and a delay216. When M1is to be turned on (DRV asserted to logic high), the control logic circuit210turns on both M3and M4to discharge the gate of M1very quickly and thus turn on M1very quickly. Once M1is on, then control logic circuit210turns off M3(the larger current path) while maintaining M4on to keep M1in an on-state. In this example, each dual-knee clamp206/208generates an output control signal labeled CLAMP1_ON/CLAMP2_ON that indicates whether the respective dual-knee clamp has detected that the Vgs of the respective M1and M2transistor has exceeded the clamping voltage (e.g., 5V). This control signal is indicative of the respective M1and M2transistor being on. Control logic circuit210receives CLAMP1_ON from dual-knee clamp206, and control logic circuit220receives CLAMP2_ON from dual-knee clamp208. Control logic circuit210responds to assertion (e.g., logic high) of CLAMP1_ON by turning M3off.

With M2on and M1off, the gate driver200operates as follows to turn on M1. The DRV signal205transitions from low to high to command the gate driver200to turn on M1. In response to a logic high assertion of DRV signal205, M7turns on pulling the gate of M2towards ground thereby turning off M2(or otherwise ensuring that that M2remains off). A positive assertion of the DRV signal205also turns on M6and, through the set(S) input of flip-flop212, also turns on M5. With M5and M6both on, current flows from voltage terminal201through M8and through M5and M6to ground/SW terminal203. M8, M9and M10are configured as a current mirror. The current through M8is thus mirrored through M9thereby turning off M17. M17previously being on had turned on M2. Accordingly, with M17off (and M7on), M2is ensured to be off.

The control logic210includes a delay216and an AND gate214. The input of the delay216receives the DRV signal205. The output of the delay is coupled to an input of the AND gate and to the gate of M4. The output of AND gate214is coupled to the gate of M3. The positive assertion of the DRV signal204sets the flip-flop thereby driving its Q output high to turn on M5(as noted above) and to provide a logic high to one input of the AND gate214. Following expiration of the delay time period implemented by delay216, the other input of AND gate214is driven high, resulting in M3being turned on. The expiration of the delay time period also results in M4being turned on. The time delay from the positive assertion of the DRV signal205provides sufficient time to ensure that M2is turned off before the control logic210attempts to turn on M1.

With M3and M4both being on, the combined current through the larger current path (M3) and the smaller current path (M4) flows from the gate of M1to discharge M1's gate and rapidly turn on M1. With M1on, the voltage on the gate terminal202rises rapidly towards the voltage on the voltage terminal201. Further, the Vgs of M1increases as M1is turned on. Upon the Vgs of M1reaching the clamping voltage implemented within the dual-knee clamp206, the dual-knee clamp206activates preventing the Vgs of M1from exceeding the clamping voltage (e.g., 5V). At the time that the dual-knee clamp activates to clamp the Vgs of M1, the dual-knee clamp206asserts CLAMP1_ON to a logic high level. CLAMP1_ON is coupled to the reset (R) input of flip-flop212. Flip-flop212responds to the positive assertion of CLAMP1_ON by causing its Q output to become logic low. A logic low on the Q output of flip-flop212causes the output of AND gate214to become logic low thereby turning the larger current path (M3) off. The smaller current path (M4) remains on thereby maintaining M1in an on-state. By turning M3off, the average quiescent current of the gate driver200is reduced compared to what would have been the case if M3was maintained on.

The operation of the gate driver200to turn off M1and turn on M2is similar to that described above. The control logic220also includes a flip-flop222, AND gate224, and delay226. The gate driver200responds to a logic low assertion of the DRV signal by turning off M1and turning on M2. Through inverter228, the DRV signal205sets the flip-flop thereby forcing its Q output high. At this point, both M13and M14are on resulting in current flowing through resistor R5thereby forcing the gate of M16low enough to turn on M16and thus turn off M1. While M1is on and M2is off, M7is turned on preventing M2from turning on, as explained above. When the DRV signal205becomes logic low to turn on M2, the DRV signal205causes M7to turn off.

Following a delay (implemented by delay226) from the negative edge of the DRV signal205, both M11and M12are turned on thereby turning on a larger current path (M11) and a smaller current path (M12). The combined current flows through M15and is mirrored through M17thereby forcing the gate of M2to increase and turn on.

Dual-knee clamp208ensures that the Vgs of M2does not exceed the clamping voltage (e.g., 5V). Upon the Vgs of M2reaching the clamping voltage of the dual-knee clamp208, the dual-knee clamp208asserts to a logic high state CLAMP2_ON, which resets flip-flop222. In response to the Q output of flip-flop222becoming logic low, the larger current path implemented by M11is turned off thereby reducing the average quiescent current of the gate driver200.

The voltage on the voltage terminal201may be substantially higher than the maximum Vgs permitted for M1and M2(as well as the other transistors in the gate driver200). The dual-knee clamps206and208protect M1and M2from experiencing a voltage difference between their gates and sources that might damage the transistors. In one example, M1and M2may be drain-extended transistors safely operating with a Vgs up to 5V and a Vds up to 20V. Further, the only subrail voltage in driver200is created on subrail245by the subrail reference240and M18. The subrail245is used to power the digital electronics including the flip-flops212and222, the inverter228, the delays216and226, and the AND gates214and224, and not any transistors through which the full output current of the gate driver flows.

While AND gates214and224are shown in the example ofFIG.2, in other examples, different types of logic gates or combinations of logic gates can be used.

The additional dual-knee clamp230is included for much the same reason as for dual-knee clamps206and208. M16inFIG.2is turned on by pulling its gate to ground with a relatively high current, and then a small current is used to maintain the on-state of M16. Dual-knee clamp230is used to protect the gate of M16. In alternative embodiments, a Zener diode can be used as a clamp to protect the gate of M16because the high current for M16is not as high as for M1and M2.

It is possible that the voltage on the voltage terminal201is low enough with respect to ground/SW node terminal203that either or both of the dual-knee clamps206and208do not activate to clamp the Vgs of the respective M1and M2. That is, the Vgs may remain below the clamping voltage of the dual-knee clamps. This condition could occur for lower levels of supply voltage (VCC). If this condition occurs, the dual-knee clamps will not assert their output control signals CLAMP1_ON and CLAMP2_ON. Further, if neither CLAMP1_ON nor CLAMP2_ON assert high, then the respective flip-flops212and214will not receive a logic high on their reset inputs and, accordingly, the larger current paths (M3and M11) will remain on even after M1/M2turn on.

FIG.3is an example latch300usable to implement either or both of flip-flops212and222ofFIG.2. Latch300includes an RS flip-flop302, a delay304, and an OR gate306. The Q output of the flip-flop302is coupled to an input of delay304, and the delay's output is coupled to an input of OR gate306. The other input of OR gate306is coupled to the respective dual-knee clamp and thus receives that clamp's CLAMP1_ON or CLAMP2_ON (CLAMPx_ON) output control signal. Thus, the flip-flop302is reset (positive assertion on its R input) when either the CLAMPx_ON signal is asserted high by the clamp or a fixed time delay after the flip-flop's Q output becomes logic high. Accordingly, the larger current path controlled by the flip-flop is turned off in response to the clamp detecting a Vgs of the respective M1or M2that equals the clamping voltage of the clamp, but is turned off regardless after it has been on for a fixed period of time that ensures that the corresponding M1or M2is fully on.

FIG.4is an example circuit for implementing dual-knee clamp208.FIG.5is a graph illustrating the dual-knee relationship between the current through the clamp (Iclamp) and the voltage difference (Vclamp) between the gate of M2and voltage terminal203. The first knee is illustrated at501and the second knee is illustrated at502inFIG.5.

Dual-knee clamp208includes a current source11(“11” referring both to the current source and the magnitude of the current it produces), resistors RC1, RC2, and R41, transistors MC1and MC2, a current mirror402, and an inverter410. Resistor RC1is coupled in series with current source11to produce a reference voltage (VREF, e.g., 3V) on the gate of MC1. That voltage fixes the gate voltage for MC1. As a PMOS device, MC1will not turn on until its source voltage is more than the transistor's threshold voltage above its gate voltage. When M17is turned on, the gate voltage on M2increases. When the gate voltage of M2is more than a threshold voltage of MC1above MC1's gate voltage (VREF), MC1turns on and the source of MC1and gate of MC2will be a threshold voltage above VREF. This is the first “knee”501inFIG.5. In one example, the first knee is at a Vclamp voltage Vth1of 4V.

As the voltage on the gate of M1increases to the point where it is one threshold voltage above its gate voltage (e.g., 5V for a Vth1of 4V, assuming the Vt of MC2is 1V), MC2also turns on. At that point (the second knee502inFIG.5), both MC1and MC2are on. MC2is a larger transistor than MC1and thus more of the Iclamp current flows through MC2than MC1. The Vgs of M17is fixed by the gate voltage used to turn on M17and the drain voltage of M17which is the voltage of voltage terminal201. Thus, M17functions as a current source to produce a fixed current as Iclamp through the dual-knee clamp208. The majority (e.g., 90%) of Iclamp flow through MC2. The voltage on the gate of MC2is fixed and for the current to balance relative to the current source of M17then the voltage on the source of MC2is set to a level that that produces Iclamp current through MC2. Accordingly, the source voltage of MC2remains fixed regardless of any further attempted increase in the gate voltage of M2.

Upon MC2turning on, the current mirror402causes current to flow through resistor R41. Prior to MC2turning on, the input of inverter410is pulled high through resistor R41, and thus the inverter's output (CLAMP2_ON) is logic low. When MC2turns on (which occurs upon the voltage between the gate of M2and terminal203reaching the second knee502inFIG.5, the input to inverter410becomes logic low and CLAMP2_ON becomes logic high.

FIG.6is an example circuit for implementing dual-knee clamp206. The architecture of this circuit is much the same as that for dual-knee clamp208inFIG.4. PMOS devices MC1and MC2ofFIG.4are NMOS devices MC1A and MC2A inFIG.6. As the gate of M1decreases, MC1A first turns on at a first knee, and then at a second knee, MC2A turns on. An inverter is not included in this example, as the voltage across R61(CLAMP1_ON) is initially low before the clamp reaches the second knee. At that point, current flows through resistor R61and CLAMP1_ON becomes logic high.

FIG.7is a circuit schematic of a gate driver700in accordance with an example embodiment. Gate driver700can be used to implement either or both of gate drivers100aand100bofFIG.1. Gate driver700is largely similar to gate driver200ofFIG.2. A difference is as follows. As explained above, gate driver200includes feedback control signals CLAMP1_ON and CLAMP2_ON from the dual-knee clamps206and208indicating that the respective M1and M2have been turned on, and control logic circuits210and220respond to assertions of CLAMP1_ON and CLAMP2_ON by turning off the respective larger current paths (M3and M11). Gate driver700, however, has dual-knee clamps706and708that are similar to corresponding dual-knee clamps206and208but do not have the output circuit components to generate the feedback control signals CLAMP1_ON and CLAMP2_ON. For example, compared to clamp206ofFIG.6, clamp706ofFIG.7does not have current mirror602nor resistor R61to generate CLAMP1_ON. Similarly, compared to clamp208ofFIG.4, clamp708ofFIG.7does not have current mirror402, resistor R41nor inverter410to generate CLAMP2_ON. Clamp706is a dual-knee clamp for M1as well as a dual-knee clamp for M16. InFIG.2, two separate dual-knee clamps206and230were included for protecting M1and M16, respectively, but inFIG.7, a single dual-knee clamp provides the same functionality to protect M1and M16. MC4A is a voltage protection device for the current source below it (11). If current source11can handle the applicable voltages (e.g., 20V), MC4A may be omitted in other embodiments. MC3A and resistor RC3are coupled together and provide the clamp for M16.

InFIG.7, the control logic is identified as control logic circuits710and720. Another difference between the gate drive700ofFIG.7and gate driver200ofFIG.2is that the control logic circuits710and720ofFIG.7include one-shots712and712instead of flip-flops. These one-shots activate their respective larger current paths (M3) and (M11) for a defined period of time (the pulse width of the one-shot's output pulses) and thus the control logic circuits710and720do not rely on feedback control signals to specify when M1and M2have turned on. The width of the pulses from the one-shots is long enough to ensure that M1and M2have had sufficient time to turn on.

In this description, the term “couple” may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by direct connection; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

A device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or re-configurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof.

As used herein, the terms “terminal”, “node”, “interconnection”, “pin” and “lead” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection between or a terminus of a device element, a circuit element, an integrated circuit, a device or other electronics or semiconductor component.

A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, for example, by an end-user and/or a third-party.

While the use of particular transistors is described herein, other transistors (or equivalent devices) may be used instead. For example, a p-type metal-oxide-silicon field effect transistor (“MOSFET”) may be used in place of an n-type MOSFET with little or no changes to the circuit. Furthermore, other types of transistors may be used (such as bipolar junction transistors (BJTs)). References to a “control input” of a transistor is the gate of a MOSFET or the base of a BJT. References to a “current terminal” of a transistor is the drain or source of a MOSFET or the collector or emitter of a BJT.

Circuits described herein are reconfigurable to include additional or different components to provide functionality at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor.

Uses of the phrase “ground” in the foregoing description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value means +/−10 percent of the stated value. Modifications are possible in the described examples, and other examples are possible within the scope of the claims.

Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.