Patent ID: 12237816

DETAILED DESCRIPTION

In one embodiment of the disclosure, an on-chip transformer circuit is disclosed. The on-chip transformer circuit comprises a primary winding circuit comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding. In some embodiments, the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.

In one embodiment of the disclosure, a distributed active transformer (DAT) power combiner circuit is disclosed. The DAT power combiner circuit comprises a first DAT circuit comprising a first primary winding circuit comprising a first primary conductive loop comprising at least two input ports configured to receive at least two input signals, respectively associated therewith; and a first secondary winding circuit comprising a first secondary conductive loop comprising a first output port configured to provide a first output signal, based on the at least two input signals associated with the first primary winding circuit. The DAT power combiner circuit further comprises a second DAT circuit comprising a second primary winding circuit comprising a second primary conductive loop comprising at least two input ports configured to receive at least two input signals, respectively associated therewith; and a second secondary winding circuit comprising a second secondary conductive loop comprising a second output port configured to provide a second output signal, based on the at least two input signals associated with the second primary winding circuit, wherein the two input signals associated with the primary winding circuit and the two input signals associated with the secondary winding circuit are different. In some embodiments, the first DAT circuit and the second DAT circuit are physically arranged in a way that the first output port of the first DAT circuit and the second output port of the second DAT circuit face one another from opposite directions.

In one embodiment of the disclosure, a stacked differential amplifier circuit is disclosed. The stacked differential amplifier circuit comprises a differential amplifier circuit comprising a first differential output terminal and a second differential output terminal. In some embodiments, the stacked differential amplifier circuit further comprises a stacked amplifier circuit, comprising a first stacked transistor circuit comprising a first stacked terminal coupled to the first differential output terminal of the differential amplifier circuit; and a second stacked transistor circuit comprising a fourth stacked terminal coupled to the second differential output terminal of the differential amplifier circuit. In some embodiments, the differential amplifier circuit comprises a plurality of unit cell amplifier circuits in parallel, each unit cell amplifier circuit comprising a first unit cell transistor circuit comprising a first transistor terminal and a second transistor terminal; and a second unit cell transistor circuit comprising a fourth transistor terminal and a fifth transistor terminal. In some embodiments, the first transistor terminal of the first unit cell transistor circuit and the fourth transistor terminal of the second unit cell transistor circuit are coupled to one another to form a differential arrangement. In some embodiments, the second transistor terminal of the first unit cell transistor circuit associated with each of the unit cell amplifier circuits are coupled together to form the first differential output terminal; and the fifth transistor terminal of the second unit cell transistor circuit associated with each of the unit cell amplifier circuits are coupled together to form the second differential output terminal. In some embodiments, each of the unit cell amplifier circuits is configured to be selectively activated or deactivated, based on the output requirements of the stacked differential amplifier circuit.

The present disclosure will now be described with reference to the attached drawing figures, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures and devices are not necessarily drawn to scale. As utilized herein, terms “component,” “system,” “interface,” “circuit” and the like are intended to refer to a computer-related entity, hardware, software (e.g., in execution), and/or firmware. For example, a component can be a processor (e.g., a microprocessor, a controller, or other processing device), a process running on a processor, a controller, an object, an executable, a program, a storage device, a computer, a tablet PC and/or a user equipment (e.g., mobile phone, etc.) with a processing device. By way of illustration, an application running on a server and the server can also be a component. One or more components can reside within a process, and a component can be localized on one computer and/or distributed between two or more computers, A set of elements or a set of other components can be described herein, in which the term “set” can be interpreted as “one or more.”

Further, these components can execute from various computer readable storage media having various data structures stored thereon such as with a module, for example. The components can communicate via local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network, such as, the Internet, a local area network, a wide area network, or similar network with other systems via the signal).

As another example, a component can be an apparatus with certain functionality provided by mechanical parts operated by electric or electronic circuitry, in which the electric or electronic circuitry can be operated by a software application or a firmware application executed by one or more processors. The one or more processors can be internal or external to the apparatus and can execute at least a part of the software or firmware application. As yet another example, a component can be an apparatus that provides specific functionality through electronic components without mechanical parts; the electronic components can include one or more processors therein to execute software and/or firmware that confer(s), at least in part, the functionality of the electronic components.

Use of the word exemplary is intended to present concepts in a concrete fashion. As used in this application, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or”. That is, unless specified otherwise, or clear from conte8, “X employs A or B” is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then “X employs A or B” is satisfied under any of the foregoing instances. In addition, the articles “a” and “an” as used in this application and the appended claims should generally be construed to mean “one or more” unless specified otherwise or clear from conte8 to be directed to a singular form. Furthermore, to the event that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.”

The following detailed description refers to the accompanying drawings. The same reference numbers may be used in different drawings to identify the same or similar elements. In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular structures, architectures, interfaces, techniques, etc. in order to provide a thorough understanding of the various aspects of various embodiments. However, it will be apparent to those skilled in the art having the benefit of the present disclosure that the various aspects of the various embodiments may be practiced in other examples that depart from these specific details. In certain instances, descriptions of well-known devices, circuits, and methods are omitted so as not to obscure the description of the various embodiments with unnecessary detail.

As indicated above, increasing the power efficiency, and reducing the size and the cost of the transmitters, while keeping other specifications within the standard is a key factor to the evolution of overall performance of the wireless mobile products. Among the several building blocks associated with wireless transmitters, power amplifiers have been one of the most challenging. Designing a high efficiency power amplifier is a major challenge in transmitter design. Further, impedance transformation and power combining are major challenges in power amplifier design. In some embodiments, on-chip transformers are utilized in transmitters for impedance transformation associated with power amplifiers. Utilizing an efficient on-chip transformer for impedance transformation is essential for efficient operation of transmitters. Further, in some embodiments, power combiners are utilized in transmitters for combining power associated with one or more power amplifiers. Utilizing an efficient power combiner circuit for power combining is also essential for efficient operation of transmitters.

In current implementations of transmitters, various on-chip transformer designs are utilized. For example, in some embodiments, a coplanar interleaved transformer, which has the primary and secondary windings interleaved on the same integrated circuit layer is utilized. Due to the complexity of the windings and flux leakage, the coplanar interleaved transformer has low quality (Q) and low coupling coefficient (k). Further, in some embodiments, toroidal and concentric transformers are implemented in multi-layer metal windings. However, they suffer from weak coupling, asymmetrical center tap location. Furthermore, in some embodiments, overlay transformers that include primary windings on one layer and secondary windings on another layer are utilized. The primary side and secondary side windings are overlapped to achieve high coupling coefficient. However, the short distance between the upper metal layer windings and lower layer windings introduces high parasitic capacitance, which lowers the self-resonance frequency (SRF). Therefore, the overlay transformer design does not work well for mmWave applications. In order to overcome the above disadvantages, an on-chip transformer circuit comprising a primary winding circuit in a first dielectric layer and a secondary winding circuit in a second, different dielectric layer is proposed in this disclosure. In some embodiments, the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding. In some embodiments, the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding, further details of which are given in embodiments below.

Similarly, in current implementations of transmitters, various power combiner designs are utilized. For example, in one embodiment, a single distributed active transformer (DAT) that combines the power from 2 differential amplifiers is utilized as the power combiner. In some embodiments, the said DAT uses dummy metal to balance the capacitive coupling in single-ended operation of the DAT. However, a single DAT combines only two differential PAs. In another embodiment, a power combiner that use two DATs in parallel is utilized. In some embodiments, the said power combiner combines the power of four differential PAs and therefore, have more output power. However, they don't have methodology to balance the capacitive coupling in single-ended operation of the DATs. Therefore, port imbalance increases loss and consequently degrades the combining efficiency. More importantly, the two employed DATs are both placed on one side of an output RF pad. This physical placement requires extra leads from DATs to reach to the RF pad which increases the loss of the power combiner. Further, in another embodiment, a power combiner that use two parallel regular transformers and combine the power of two differential PAs is utilized. The said power combiner has less port imbalance compared to the single-ended DAT, but it is less efficient as it occupies larger area and also requires extra lead from transformers to the RF pad, as the two parallel transformers are placed on the same side of an output RF pad. In order to overcome the above disadvantages, a DAT power combiner circuit comprising a first DAT circuit that combines the power from a first set of 2 differential amplifiers and a second DAT circuit that combines the power from second, different, set of 2 differential amplifiers, thereby combining the power from 4 differential PAs is proposed in this disclosure. In particular, the first DAT circuit and the second DAT circuit are physically arranged in a way that output ports of the first DAT circuit and the second DAT circuit face one another from opposite directions. In some embodiments, such a physical arrangement enables the first DAT circuit and the second DAT circuit to couple to a radio frequency (RF) pad placed between the first DAT circuit and the second DAT circuit from a minimum distance.

Similarly, in current implementations of transmitters, various power amplifier (PA) designs are utilized. For example, in some embodiments, a power amplifier circuit design that involves stacking two or more transistors in Bulk CMOS or SOI CMOS is utilized. In some embodiments, the stacked transistors are arranged in a single-ended topology or a differential topology. In higher order modulation schemes or OFDM, the PA in the transmitter front-end usually operates at much lower output power than its saturated peak power which is called as back-off operation. Therefore, the energy efficiency in the lower output powers (i.e. back-off operation) is a key metric in PA design. In current implementations of PAs, while the efficiency is good when transmitting symbols at the peak output power, it gets degraded significantly at back-off operation, since the PA actives are always in ON mode and the DC power gets wasted. In order to overcome the above disadvantages, a digital capability which effectively enhances the back-off energy efficiency and provides re-configurability for applications such as VSWR tuning is preferred. Therefore, a stacked differential amplifier circuit that utilizes digital operation to selectively activate or deactivate select segments of the stacked differential amplifier circuit is proposed in this disclosure, further details of which are given in embodiments below.

FIG.1illustrates an exemplary simplified block diagram of an on-chip transformer circuit100, according to various embodiments described herein. The on-chip transformer circuit100comprises a primary winding circuit102and a secondary winding circuit104coupled to one another. In particular, in the embodiments described herein, the primary winding circuit102and the secondary winding circuit104are magnetically coupled to one another, and the term “coupled” is not to be construed to be limited to mean “directly coupled”. In some embodiments, the primary winding circuit102comprises a primary feeding port106comprising two primary signal terminals configured to receive a primary input signal. In some embodiments, the primary feeding port106comprise a differential port configured to receive a differential input signal. In such embodiments, the primary input signal may comprise a differential input signal. However, in other embodiments, the primary feeding port102can comprise a single-ended input port configured to receive a single ended signal. In some embodiments, the secondary winding circuit104comprises a secondary feeding port108comprising two secondary signal terminals configured to provide a secondary output signal. In some embodiments, the secondary feeding port108comprise a differential port configured to provide a differential input signal. In such embodiments, the secondary output signal may comprise a differential output signal. However, in other embodiments, the secondary feeding port108can comprise a single-ended output port configured to provide a single ended signal.

In some embodiments, the primary winding circuit102may comprise at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate. In some embodiments, the primary conductive winding comprises a primary metal winding. In some embodiments, the primary feeding port106associated with the primary conductive winding is arranged on any one side of the first N-sided polygon. In some embodiments, the primary winding circuit102further comprises a primary center-tap port comprising a conductive connection coupled to a center point of the primary conductive winding with respect to the two primary signal terminals. In some embodiments, the primary center tap port is located in a third dielectric layer of the substrate and is coupled to the center point of the primary conductive winding via a plurality of vias. In some embodiments, the secondary winding circuit104comprises at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate. In some embodiments, the secondary conductive winding comprises a secondary metal winding. In some embodiments, the secondary feeding port108associated with the secondary conductive winding is arranged on any one side of the second N-sided polygon.

In some embodiments, the secondary winding circuit104further comprises a secondary center-tap port comprising a conductive connection (e.g., a metal connection) coupled to a center point of the secondary conductive winding with respect to the two secondary signal terminals. In some embodiments, the secondary center tap port is located in a fourth dielectric layer of the substrate and is coupled to the center point of the secondary conductive winding via a plurality of vias. In some embodiments, the third dielectric layer and the fourth dielectric layer are the same. In some embodiments, the first N-sided polygon and the second N-sided polygon may be equal-sided polygons or non-equal-sided polygons. In some embodiments, N can be any number greater than or equal to 4 (i.e., N>=4). In some embodiments, the number of turns associated with the primary conductive winding and the secondary conductive windings may be the same. However, in other embodiments, the number of turns associated with the primary conductive winding and the secondary conductive windings may be different (e.g., step-up transformer, step-down transformer etc.).

In some embodiments, the primary winding circuit102and the secondary winding circuit104are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding. In some embodiments, the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding. In particular, in one embodiment, the primary winding circuit102and the secondary winding circuit104are configured to be identical to one another in shape and size, and the secondary winding circuit104is rotated with respect to the primary winding circuit102by a predefined rotation angle such that the primary winding circuit102and the secondary winding circuit104overlap at the predetermined locations along the primary conductive winding and the secondary conductive winding, further details of which are provided in an embodiment below. Further, in another embodiment, the secondary conductive winding associated with the secondary winding circuit104and the primary conductive winding associated with the primary winding circuit102are interleaved with respect to one another, at one or more respective sides, forming one or more interleaved sides, along the primary conductive winding and the secondary conductive winding such that the primary winding circuit and the secondary winding circuit overlap at the predetermined locations along the primary conductive winding and the secondary conductive winding, further details of which are given in an embodiment below.

FIG.2illustrates an example implementation of an on-chip transformer circuit200, according to one embodiment of the disclosure. In some embodiments, the on-chip transformer circuit200comprises one possible way of implementation of the on-chip transformer circuit100inFIG.1. The on-chip transformer circuit200comprises a primary winding circuit202comprising 3 turns of a primary conductive winding (e.g., a metal winding) arranged in an octagon shape having 8 sides on a first dielectric layer of a substrate. However, in other embodiments, the primary winding circuit202can have any number of turns (more or less than 3) and can be arranged to have more or less than 8 sides (e.g., N sides). In this embodiment, the orthogonal sides have different length from the diagonal sides for each turn. However, in other embodiments, the length of each side of the polygon can be defined differently (e.g., equal sides or non-equal sides). The on-chip transformer circuit200further comprises a secondary winding circuit204comprising 3 turns of a secondary conductive winding (e.g., a metal winding) arranged in an octagon shape having 8 sides on a second, different dielectric layer of the substrate.

In some embodiments, the secondary winding circuit204is configured to be identical or substantially identical in shape and size to the primary winding circuit202. However, in other embodiments, the secondary winding circuit204can have different dimensions, for example, length of each side can be different compared to the primary winding circuit202. In some embodiments, the primary winding circuit202and the secondary winding circuit204are symmetrically arranged with respect to a common center point210. In some embodiments, the secondary winding circuit204is rotated (clockwise or anti-clockwise) with respect to the primary winding circuit202by a predefined rotation angle θ such that the primary winding circuit202and the secondary winding circuit204overlap one another at predetermined locations (e.g.,215a,215betc.) along the primary conductive winding and the secondary conductive winding. In some embodiments, the predetermined locations comprises a number of locations that is less than all the available locations along the primary conductive winding and the secondary conductive winding. In some embodiments, the secondary winding circuit204is rotated with respect to the primary winding circuit202by the predefined rotation angle in reference to the common center point210.

In this embodiment, the secondary conductive winding is shown to include the same number of turns as the primary winding circuit202(i.e., 3 turns). However, in other embodiments, the number of turns in the secondary conductive windings can be different from the primary winding circuit202, In this embodiment, the predefined rotation angle comprises 45 degrees. However, in other embodiments, the rotation angle can be different. In some embodiments, the secondary winding circuit204is rotated with respect to the primary winding circuit202so as to optimize the coupling coefficient and the self-resonance frequency of the on-chip transformer circuit200. In some embodiments, the length of each side of the primary winding circuit202and the secondary winding circuit204are chosen in a way to get optimal coupling coefficient and self-resonance frequency in the rotated position.

In some embodiments, the primary winding circuit202comprises a primary feeding port206comprising a first primary signal terminal p1206aand a second primary signal terminal p2206b. In some embodiments, the primary winding circuit202further comprises a primary center-tap port CT1207comprising a conductive connection coupled to a center point of the primary conductive winding with respect to the two primary signal terminals206aand206b. In some embodiments, the primary center tap port CT1207is located in a third dielectric layer of the substrate and is coupled to the center point of the primary conductive winding via a plurality of vias, as shown inFIG.3b. In some embodiments, the secondary winding circuit204comprises a secondary feeding port208comprising a first secondary signal terminal s1208aand a second secondary signal terminal s2208b. In some embodiments, the secondary winding circuit204further comprises a secondary center-tap port CT2209comprising a conductive connection (e.g., a metal connection) coupled to a center point of the secondary conductive winding with respect to the two secondary signal terminals208aand208b. In some embodiments, the secondary center tap port CT1207is located in the third dielectric layer of the substrate and is coupled to the center point of the secondary conductive winding via a plurality of vias, as shown inFIG.3b.

In some embodiments, the secondary center tap port CT2209may be removed and one of the two secondary signal terminals, say S1208a, may be coupled to AC ground electrically, so as to configure the on-chip transformer circuit200as a balun (balance-unbalance). In the balun mode, the on-chip transformer circuit200may be configured to convert a differential signal at the primary side to a single-ended signal at the secondary side. Alternately, in the balun mode, the on-chip transformer circuit200may be configured to convert a single-ended signal at the secondary side to a differential signal at the primary side. In some embodiments, the primary winding circuit202is arranged to be symmetric with respect to a primary center line212(also referred to as primary side symmetric line in some embodiments) comprising a straight line between the two primary terminals p1and p2of the primary feeding port206associated with the primary winding circuit202and passing through the common center point210. Similarly, the secondary winding circuit204is arranged to be symmetric with respect to a secondary center line214(also referred to as secondary side symmetric line in some embodiments) comprising a straight line between the two secondary terminals s1and s2of the secondary feeding port208associated with the secondary winding circuit204and passing through the common center point210.

In this embodiment, the primary feeding port206and the secondary feeding port208are arranged in orthogonal directions with respect to one another. However, in other embodiments, the primary feeding port206and the secondary feeding port208may be arranged in different orientations with respect to one another. For example,FIG.3adepicts an on-chip transformer circuit300comprising a primary winding circuit302and a secondary winding circuit304having a primary feeding port306and a secondary feeding port308arranged in diagonal directions with respect to one another. Therefore, in this embodiment, the primary center line and the secondary center line overlap to form a symmetric line305. All the other features of the on-chip transformer circuit300are similar to the on-chip transformer circuit200inFIG.2and is therefore all the explanations above with respect toFIG.2is also applicable toFIG.3. Further, in other embodiments, the primary feeding port206and the secondary feeding port208of the on-chip transformer circuit200may be arranged in non-orthogonal or non-diagonal direction with respect to one another.

FIG.3billustrates a cross-section view of the on-chip transformer circuit300with respect to the symmetric line305. InFIG.3b, it can be seen that the primary conductive windings302are arranged in a dielectric layer352and the secondary conductive windings are arranged in a dielectric layer354. Further, the primary conductive winding is shifted with respect to the secondary conducting winding by a shifting distance362. Further, inFIG.3b, it can be seen that the primary center-tap port CT1is arranged in the dielectric layer356and coupled to center point of the primary conductive winding302using a plurality of vias358. Similarly, the secondary center-tap port CT2is arranged in the dielectric layer356and coupled to center point of the secondary conductive winding304using a plurality of vias360. Although, the various dielectric layers352,354and356are shown to be adjacent layers, in other embodiments, the dielectric layers352,354and356may not be adjacent to one another. Also, the order in which the various windings are arranged in the various dielectric layers352,354and356may be different. For example, in some embodiments, the primary winding circuit302may be arranged in the dielectric layer354and the secondary winding circuit304may be arranged in the dielectric layer352.

FIG.4illustrates another example implementation of an on-chip transformer circuit400, according to one embodiment of the disclosure. In some embodiments, the on-chip transformer circuit400depicts another possible way of implementation of the on-chip transformer circuit200inFIG.2. The on-chip transformer circuit400comprises a primary winding circuit402comprising a primary conductive winding having 2 turns arranged in the form of an octagon in a first dielectric layer of a substrate. The on-chip transformer circuit400further comprises a secondary winding circuit404comprising a secondary conductive winding having 2 turns arranged in the form of an octagon in a second, different, dielectric layer of a substrate. The primary winding circuit402comprises a primary feeding port406and the secondary winding circuit404comprises a secondary feeding port408arranged at 135 degrees with respect to one another. All the other features of the on-chip transformer circuit400are similar to the on-chip transformer circuit200inFIG.2and is therefore all the explanations above with respect toFIG.2is also applicable toFIG.4.

FIG.5illustrates another example implementation of an on-chip transformer circuit500, according to one embodiment of the disclosure. In some embodiments, the on-chip transformer circuit500depicts another possible way of implementation of the on-chip transformer circuit200inFIG.2. The on-chip transformer circuit500comprises a primary winding circuit502comprising a primary conductive winding having one single turn arranged in the form of a decagon (N=10) in a first dielectric layer of a substrate. The on-chip transformer circuit500further comprises a secondary winding circuit504comprising a secondary conductive winding having one single turn arranged in the form of a decagon in a second, different, dielectric layer of a substrate. The secondary winding circuit504is rotated with respect to the primary winding circuit502by 18 degrees. All the other features of the on-chip transformer circuit500are similar to the on-chip transformer circuit200inFIG.2and is therefore all the explanations above with respect toFIG.2is also applicable toFIG.5.

FIG.6illustrates an example implementation of an on-chip transformer circuit600, according to one embodiment of the disclosure. In some embodiments, the on-chip transformer circuit600comprises another possible way of implementation of the on-chip transformer circuit100inFIG.1. The on-chip transformer circuit600comprises a primary winding circuit602comprising one single turn of a primary conductive winding (e.g., a metal winding) arranged in an octagon shape having 8 sides on a first dielectric layer of a substrate. However, in other embodiments, the primary winding circuit602can have any number of turns and can be arranged to have more or less than 8 sides. In some embodiments, the primary winding circuit602comprises an equal-sides polygon, that is, all the sides of the polygon are equal in length (equal sided octagon, in this embodiment). However, in other embodiments, the length of each side of the polygon can be defined differently (e.g., equal sides or non-equal sides). The on-chip transformer circuit600further comprises a secondary winding circuit604comprising one single turn of a secondary conductive winding (e.g., a metal winding) arranged in an octagon shape having 8 sides on a second, different dielectric layer of the substrate. In this embodiment, the secondary conductive winding is shown to include the same number of turns as the primary winding circuit202(i.e., 1 turn). However, in other embodiments, the number of turns in the secondary conductive windings604can be different from the primary winding circuit602.

In some embodiments, the primary winding circuit602comprises a primary feeding port606comprising a first primary signal terminal p1606aand a second primary signal terminal p2606b. In some embodiments, the primary winding circuit602further comprises a primary center-tap port CT1607comprising a conductive connection coupled to a center point of the primary conductive winding with respect to the two primary signal terminals606aand606b. In some embodiments, the primary center tap port CT1607is located in a third dielectric layer of the substrate and is coupled to the center point of the primary conductive winding via a plurality of vias. In some embodiments, the secondary winding circuit604comprises a secondary feeding port608comprising a first secondary signal terminal s1608aand a second secondary signal terminal s2608b. In some embodiments, the secondary winding circuit604further comprises a secondary center-tap port CT2609comprising a conductive connection (e.g., a metal connection) coupled to a center point of the secondary conductive winding with respect to the two secondary signal terminals608aand608b. In some embodiments, the secondary center tap port CT2609is located in the third dielectric layer of the substrate and is coupled to the center point of the secondary conductive winding via a plurality of vias. In some embodiments, the secondary center tap port CT2609may be removed and one of the two secondary signal terminals, say S1608a, may be coupled to AC ground electrically, so as to configure the on-chip transformer circuit600as a balun (balance-unbalance). In the balun mode, the on-chip transformer circuit600may be configured to convert a differential signal at the primary side to a single-ended signal at the secondary side. Alternately, in the balun mode, the on-chip transformer circuit600may be configured to convert a single-ended signal at the secondary side to a differential signal at the primary side.

In some embodiments, the primary winding circuit602and the secondary winding circuit604are arranged to be symmetrical with respect to a center line605(also referred to as a symmetric line, in some embodiments). In some embodiments, the center line605passes through the middle of the two primary signal terminals p1and p2associated with the primary conductive winding, and the two secondary signal terminals s1and s2associated with the secondary conductive winding. In some embodiments, the two primary signal terminals and the two secondary terminals are arranged in opposite directions with respect to one another. In some embodiments, each side of the primary winding circuit602is symmetrically aligned with respect to a corresponding side of the secondary winding circuit604, thereby forming 8 aligned sides (e.g.,620a,620betc.) of the on-chip transformer circuit600. In other embodiments, wherein the primary winding circuit602and the secondary winding circuit604comprise N sides, N sides of the primary winding circuit602may be symmetrically aligned with respect to N corresponding sides of the secondary winding circuit604, thereby forming N aligned sides (e.g.,620a,620betc.) of the on-chip transformer circuit600. In some embodiments, the term symmetrically aligned can be construed to mean that there is a symmetry in terms of length of each side of the primary conductive winding to the length of a corresponding side of the secondary conductive winding, or there is a symmetry in terms of a distance between each side of the primary conductive winding to a corresponding side of the secondary conductive winding, or both.

In this embodiment, the secondary conductive winding associated with the secondary winding circuit604and the primary conductive winding associated with the primary winding circuit602are interleaved with respect to one another, at 2 aligned sides620aand620c, thereby forming 2 interleaved sides. However, in other embodiments, the secondary conductive winding associated with the secondary winding circuit604and the primary conductive winding associated with the primary winding circuit602are interleaved with respect to one another, at one or more respective sides, forming one or more interleaved sides, along the primary conductive winding and the secondary conductive winding, such that the primary winding circuit602and the secondary winding circuit604overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding. In some embodiments, the predetermined locations comprises a number of locations that is less than all the available locations along the primary conductive winding and the secondary conductive winding. In some embodiments, the usage that the primary conductive winding and the secondary conductive winding interleave with respect to one another may be construed to mean that the primary conductive winding and the secondary conductive winding cross over one another. In some embodiments, the one or more interleaved sides can comprise one or more of the aligned sides associated with the on-chip transformer circuit600, except the aligned sides comprising the primary feeding port606and the secondary feeding port608(i.e., up to N−2 interleaved sides, if there are N aligned sides in total). In some embodiments, the one or more interleaved sides comprises at least one side pair comprising two aligned sides that are mirrored about the center line, as is the case inFIG.6. Alternately, in some embodiments, the one or more interleaved sides comprises every aligned side except the aligned sides comprising the primary feeding port606and the secondary feeding port608.

FIG.7illustrates another example implementation of an on-chip transformer circuit700, according to one embodiment of the disclosure. In some embodiments, the on-chip transformer circuit700depicts another possible way of implementation of the on-chip transformer circuit600inFIG.6. The on-chip transformer circuit700comprises a primary winding circuit702comprising two turns of a primary conductive winding (e.g., a metal winding) arranged in an equal-sided octagon shape having 8 sides on a first dielectric layer of a substrate. The on-chip transformer circuit700further comprises a secondary winding circuit704comprising two turns of a secondary conductive winding (e.g., a metal winding) arranged in an equal-sided octagon shape having 8 sides on a second, different dielectric layer of the substrate. Each side of the primary winding circuit702is symmetrically aligned with respect to a corresponding side of the secondary winding circuit704to form a plurality of aligned sides, for example,720a,720cetc. In this embodiment, the secondary conductive winding associated with the secondary winding circuit704and the primary conductive winding associated with the primary winding circuit702are interleaved with respect to one another, at 2 aligned sides720aand720c, thereby forming 2 interleaved sides.

In embodiments where the primary winding circuit702or the secondary winding circuit704have multiple turns, each turn associated with the primary winding circuit702is interleaved (or overlapped) with each turn of the secondary winding circuit704at the interleaved sides. For example, on the interleaved side720a, each turn associated with the primary winding circuit702is interleaved (or overlapped) with each turn of the secondary winding circuit704at the interleaved sides. In some embodiments, the primary winding circuit702further comprises a metal bridge722configured to couple the two turns of the primary conductive winding in a series pattern, in order to have larger inductance. Similarly, the secondary winding circuit704further comprises a metal bridge724configured to couple the two turns of the secondary conductive winding in a series pattern, in order to have larger inductance. All the other features of the on-chip transformer circuit700are similar to the on-chip transformer circuit600inFIG.6and is therefore all the explanations above with respect toFIG.6is also applicable toFIG.7.

FIG.8illustrates another example implementation of an on-chip transformer circuit800, according to one embodiment of the disclosure. In some embodiments, the on-chip transformer circuit800depicts another possible way of implementation of the on-chip transformer circuit600inFIG.6. The on-chip transformer circuit800comprises a primary winding circuit802comprising one single turn of a primary conductive winding (e.g., a metal winding) arranged in an equal-sided octagon shape having 8 sides on a first dielectric layer of a substrate. The on-chip transformer circuit800further comprises a secondary winding circuit804comprising one single turn of a secondary conductive winding (e.g., a metal winding) arranged in an equal-sided octagon shape having 8 sides on a second, different dielectric layer of the substrate, Each side of the primary winding circuit802is symmetrically aligned with respect to a corresponding side of the secondary winding circuit804to form 8 aligned sides, for example,820a,820b,820cetc. In this embodiment, the secondary conductive winding associated with the secondary winding circuit804and the primary conductive winding associated with the primary winding circuit802are interleaved with respect to one another, at 6 aligned sides820a,820b,820cetc., thereby forming 6 interleaved sides (i.e., N−2). In some embodiments, the 6 interleaved sides comprise all the aligned sides of the on-chip transformer circuit800except the aligned sides comprising the primary feeding port and the secondary feeding port. All the other features of the on-chip transformer circuit800are similar to the on-chip transformer circuit600inFIG.6and is therefore all the explanations above with respect toFIG.6is also applicable toFIG.8.

FIG.9illustrates another example implementation of an on-chip transformer circuit900, according to one embodiment of the disclosure. In some embodiments, the on-chip transformer circuit900depicts another possible way of implementation of the on-chip transformer circuit600inFIG.6. The on-chip transformer circuit900comprises a primary winding circuit902comprising one single turn of a primary conductive winding (e.g., a metal winding) arranged in an equal-sided decagon shape having 10 sides on a first dielectric layer of a substrate. The on-chip transformer circuit900further comprises a secondary winding circuit904comprising one single turn of a secondary conductive winding (e.g., a metal winding) arranged in an equal-sided decagon shape having 10 sides on a second, different dielectric layer of the substrate. Each side of the primary winding circuit902is symmetrically aligned with respect to a corresponding side of the secondary winding circuit904to form 10 aligned sides, for example,920a,920betc. In this embodiment, the secondary conductive winding associated with the secondary winding circuit904and the primary conductive winding associated with the primary winding circuit902are interleaved with respect to one another, at 8 aligned sides, thereby forming 8 interleaved sides (i.e., N−2). In some embodiments, the 8 interleaved sides comprise all the aligned sides of the on-chip transformer circuit900except the aligned sides comprising the primary feeding port and the secondary feeding port. All the other features of the on-chip transformer circuit900are similar to the on-chip transformer circuit600inFIG.6and is therefore all the explanations above with respect toFIG.6is also applicable toFIG.9.

FIG.10illustrates a flow chart of a method1000for an on-chip transformer circuit, according to one embodiment of the disclosure. The method1000is explained herein with reference to the on-chip transformer circuit100inFIG.1and the on-chip transformer circuit200inFIG.2. At1002, a primary winding circuit (e.g., the primary winding circuit202inFIG.2) comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon is provided in a first dielectric layer of a substrate. At1004, a secondary winding circuit (e.g., the secondary winding circuit204inFIG.2) comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon is provided in a second, different, dielectric layer of the substrate. In some embodiments, the secondary winding circuit and the primary winding circuit are identical in shape and size. At1006, the primary winding circuit and the secondary winding circuit are arranged symmetrically with respect to a common center point (e.g., the common center point210inFIG.2).

In some embodiments, the primary winding circuit is arranged to be symmetric with respect to a primary center line (e.g., the primary center line212inFIG.2) comprising a straight line between the two primary terminals of a primary feeding port associated with the primary winding circuit and the secondary winding circuit is arranged to be symmetric with respect to a secondary center line (e.g., the secondary center line inFIG.2) comprising a straight line between the two secondary terminals of the secondary feeding port associated with the secondary winding circuit, wherein the primary center line and the secondary center line passes through the common center point. At1008, the secondary winding circuit is rotated with respect to the primary winding circuit by a predefined rotation angle (e.g., the predefined rotation angle θ inFIG.2) in reference to the common center point, such that the primary winding circuit and the secondary winding circuit overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding. At1010, a primary center tap port (e.g., the primary center tap port207inFIG.2) comprising a first conductive connection is provided in a third, different layer of the substrate and the first conductive connection is coupled to a center point of the primary conductive winding via a plurality of vias, and a secondary center tap port (e.g., the secondary center tap port209inFIG.2) comprising a second conductive connection is provided in the third layer of the substrate and the second conductive connection is coupled to a center point of the secondary conductive winding via a plurality of vias.

FIG.11illustrates a flow chart of a method1100for an on-chip transformer circuit, according to one embodiment of the disclosure. The method1100is explained herein with reference to the on-chip transformer circuit100inFIG.1and the on-chip transformer circuit600inFIG.6. At1102, a primary winding circuit (e.g., the primary winding circuit602inFIG.6) comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon is provided in a first dielectric layer of a substrate. At1104, a secondary winding circuit (e.g., the secondary winding circuit604inFIG.6) comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon is provided in a second, different, dielectric layer of the substrate is provided. At1106, the primary winding circuit and the secondary winding circuit are arranged to be symmetrical with respect to a center line (e.g., the center line605inFIG.6). In some embodiments, the center line comprises a straight line that passes through the middle of the two primary signal terminals (p1, p2inFIG.6) associated with the primary conductive winding and two secondary signal terminals (s1, s2inFIG.6) associated with the secondary conductive winding. In some embodiments, the two primary signal terminals and the two secondary terminals are arranged in opposite directions with respect to one another.

At1108, N sides of primary winding circuit aligned symmetrically with respect to corresponding N sides of the secondary winding circuit, forming N aligned sides (e.g., aligned sides620a,620betc. inFIG.6) of the on-chip transformer circuit. At1110, the secondary conductive winding associated with the secondary winding circuit and the primary conductive winding associated with the primary winding circuit are interleaved or overlapped with respect to one another, at one or more respective sides, forming one or more interleaved sides, along the primary conductive winding and the secondary conductive winding, such that the primary winding circuit and the secondary winding circuit overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding. In some embodiments, the one or more interleaved sides can comprise one or more of the aligned sides associated with the on-chip transformer circuit, except the aligned sides comprising the primary feeding port and the secondary feeding port (i.e., up to N−2 interleaved sides, if there are N aligned sides in total). In some embodiments, the one or more interleaved sides comprises at least one side pair comprising two aligned sides that are mirrored about the center line. Alternately, in some embodiments, the one or more interleaved sides comprises every aligned side except the aligned sides comprising the primary feeding port and the secondary feeding port. At1110, a primary center tap port (e.g., the primary center tap port607inFIG.6) comprising a first conductive connection is provided in a third, different layer of the substrate and the first conductive connection is coupled to a center point of the primary conductive winding via a plurality of vias, and a secondary center tap port (e.g., the secondary center tap port609inFIG.6) comprising a second conductive connection is provided in the third layer of the substrate and the second conductive connection is coupled to a center point of the secondary conductive winding via a plurality of vias.

FIG.12depicts a simplified block diagram of a distributed active transformer (DAT) power combiner circuit1200, according to one embodiment of the disclosure. In some embodiments, the DAT power combiner circuit1200is utilized to combine power associated with a plurality of input signals from a plurality of devices, for example, power amplifiers. The DAT power combiner circuit1200comprises a first DAT circuit1202and a second DAT circuit1204. In some embodiments, the first DAT circuit1202comprises a first input port1202aand a second input port1202bconfigured to receive a first input signal1203and a second input signal1205, respectively. In some embodiments, the first DAT circuit1202may comprise a first primary winding circuit (not shown) comprising the first input port1202aand the second input port1202b, further details of which are provided in an embodiment below. In some embodiments, the first DAT circuit1202further comprises a first output port1208configured to provide a first output signal1211. In some embodiments, the first DAT circuit1202may further comprise a first secondary winding circuit (not shown) comprising the first output port1208, further details of which are provided in an embodiment below. In some embodiments, the first output signal1211is generated based on the first input signal1203and the second input signal1205. In this embodiment, the first DAT circuit1202is depicted as a 2:1 power combiner configured to combine 2 input signals (i.e.,1203and1205in this case) and generate a first output signal (i.e.,1211) based thereon. However, in other embodiments, the first DAT circuit1202may be configured to combine more than 2 input signals. In such embodiments, the first DAT circuit1202may comprise more than 2 input ports. In other words, in some embodiments, the first DAT circuit1202may comprise at least two input ports configured to receive at least two input signals, respectively associated therewith.

In some embodiments, the first input port1202aand the second input port1202bcomprise differential input ports. In such embodiments, the first input signal1203and the second input signal1205comprise differential input signals. In some embodiments, the first output port1208comprises a differential output port. In such embodiments, the first output signal1211comprises a differential output signal.

In some embodiments, the second DAT circuit1204comprises a third input port1204aand a fourth input port1204bconfigured to receive a third input signal1207and a fourth input signal1209, respectively. In some embodiments, the second DAT circuit1204may comprise a second primary winding circuit (not shown) comprising the third input port1204aand the fourth input port1204b, further details of which are provided in an embodiment below. In some embodiments, the second DAT circuit1204further comprises a second output port1210configured to provide a second output signal1213. In some embodiments, the second DAT circuit1204may further comprise a second secondary winding circuit (not shown) comprising the second output port1210, further details of which are provided in an embodiment below. In some embodiments, the second output signal1213is generated based on the third input signal1207and the fourth input signal1209. In this embodiment, the second DAT circuit1204is depicted as a 2:1 power combiner configured to combine 2 input signals (i.e.,1207and1209in this case) and generate an output signal (i.e.,1213) based thereon. However, in other embodiments, the second DAT circuit1204may be configured to combine more than 2 input signals. In such embodiments, the second DAT circuit1204may comprise more than 2 input ports. In other words, in some embodiments, the second DAT circuit1204may comprise at least two input ports configured to receive at least two input signals, respectively associated therewith.

In some embodiments, the third input port1204aand the fourth input port1204bcomprise differential input ports. In such embodiments, the third input signal1207and the fourth input signal1209comprise differential input signals. In some embodiments, the second output port1210comprises a differential output port. In such embodiments, the second output signal1213comprises a differential output signal.

In some embodiments, the first output port1208of the first DAT circuit1202and the second output port1210of the second DAT circuit1204are electrically connected to one another. In some embodiments, the first output port1208of the first DAT circuit1202and the second output port1210of the second DAT circuit1204are electrically connected to one another at a coupling circuit1206(e.g., at a common node associated therewith). In some embodiments, the coupling circuit1206is implemented as a part of the DAT power combiner circuit1200. However, in other embodiments, the coupling circuit1206is implemented as a component external to the DAT power combiner circuit1200. In some embodiments, the coupling circuit1206comprises a radio frequency (RF) pad configured to be coupled to a load circuit. Alternately, in other embodiments, the coupling circuit1206comprises a load circuit. In some embodiments, the first output port1208of the first DAT circuit1202and the second output port1210of the second DAT circuit1204are configured to couple to the coupling circuit1206from opposite directions of the coupling circuit. In such embodiments, the coupling circuit1206is physically located between the first DAT circuit1202and the second DAT circuit1204. In some embodiments, the first DAT circuit1202and the second DAT circuit1204are physically arranged in a way that the first output port1208of the first DAT circuit1202and the second output port1210of the second DAT circuit1204face one another from opposite directions. In some embodiments, such an arrangement enables the first DAT circuit1202and the second DAT circuit1204to couple to the coupling circuit1206from a minimum distance from the opposite ends. In some embodiments, reducing the distance between the output ports (i.e.,1208,1210) and the coupling circuit1206, reduces the loss associated with the extra leads connecting the output ports to the coupling circuit1206, thereby further reducing the insertion loss of the DAT power combiner circuit1200.

In some embodiments, the first DAT circuit1202may be implemented as explained inFIGS.13a-13d, In some embodiments, the first DAT circuit1202comprises a primary winding circuit1301comprising a primary conductive loop (e.g., metal winding) comprising a first input port1301a(analogous to the first input port1202ainFIG.12) configured to receive a first input signal and a second input port1301b(analogous to the second input port1202binFIG.12) configured to receive a second input signal, as shown inFIG.13a. In some embodiments, the first input signal and the second input signal comprise differential signals. In this embodiment, the first input port1301ais shown to receive the first input signal from a first differential power amplifier and the second input port1301bis shown to receive the second input signal from a second differential amplifier. However, in other embodiments, the first input port1301amay be configured to receive the first input signal and the second input port1301bmay be configured to receive the second input signal from other differential devices that are different from differential amplifiers. In some embodiments, the primary conductive loop comprises a first segment1320acoupled between the first input port1301aand the second input port1301b, and a second segment1320bcoupled between the first input port1301aand the second input port1301b. In some embodiments, the primary winding circuit1301may comprise more than 2 input ports, as explained above with respect toFIG.12. Referring back toFIG.12, in some embodiments, the first DAT circuit1202further comprises a secondary winding circuit1303arranged next to the primary winding circuit1301. In some embodiments, the secondary winding circuit1303comprises a secondary conductive loop (e.g., metal winding) comprising a first output port1308(analogous to the first output port1208inFIG.12) configured to provide a first output signal, based on the first input signal and the second input signal, as shown inFIG.13b. In some embodiments, the first output port1308comprises a differential output port, as shown inFIG.13b. However, in other embodiments, the first output port1308comprises a single-ended output port (with one of the terminals grounded), as shown inFIG.13c. By making the secondary single-ended which is the most common real case, in some embodiments, a huge imbalance is created between the impedances seen from each of the first input port1301aand the second input port1301b.

In some embodiments, when the primary winding circuit1301comprises 2 input ports (as is the case here), the primary winding circuit1301further comprises a conductive line1315(e.g., a metal conductor or winding) having a first end and a second, different end. In some embodiments, the first end of the conductive line1315is coupled to the first segment1320a(e.g., a center point associated therewith) of the first primary conductive loop coupled between the first input port1301aand the second input port1301b, and the second end of the conductive line1315is coupled to a second, different, segment1320b(e.g., a center point associated therewith) of the first primary conductive loop coupled between the first input port1301aand the second input port1301b. In some embodiments, the conductive line1315forces the centers of the two segments1320aand1320bto have the same potential and thereby improve the imbalance due to an asymmetry on the capacitive coupling between the primary winding circuit1301and secondary winding circuit1303.

Referring back toFIG.12, in some embodiments, the first DAT circuit1202further comprises a dummy winding circuit1322comprising a dummy conductive loop (e.g., a metal loop) having a dummy port1324comprising a first dummy terminal that is grounded and a second, different, dummy terminal that is floating. In some embodiments, the dummy winding circuit1322is physically arranged next to the primary winding circuit1301in a way that the primary conductive loop is located between the first secondary conductive loop and the first dummy conductive loop. In some embodiments, the dummy winding circuit1322is also provided to compensate for the imbalance between the primary winding circuit1301and the secondary winding circuit1303indicated above. In some embodiments, the dummy winding circuit1322enables to replicate the voltage swing across the first output port1308and ground, along the length of the secondary conductive loop with decreasing the amplitude (in a reverse direction) and therefore, the electric coupling across the inter-winding capacitance is equalized. Therefore, in some embodiments, the dummy winding circuit1320minimizes the port imbalance and insertion loss of the first DAT circuit1202. In some embodiments, the second DAT circuit1204inFIG.12is also implemented in the same way as explained above with respect to the first DAT circuit1202inFIG.12.

FIG.14depicts an example implementation of a distributed active transformer (DAT) power combiner circuit1400, according to one embodiment of the disclosure. In some embodiments, the DAT power combiner circuit1400depicts one possible way of implementation of the DAT power combiner circuit1200inFIG.12. The DAT power combiner circuit1400comprises a first DAT circuit1402and a second DAT circuit1404. In some embodiments, the first DAT circuit1402comprises a first primary winding circuit1401comprising a first primary conductive loop (e.g., metal winding) comprising a first input port1401aconfigured to receive a first input signal1434and a second input port1401bconfigured to receive a second input signal1436. In some embodiments, the first input port1401aand the second input port1401bare located at diagonally opposite directions with respect to one another along the first primary conductive loop. Alternately, in other embodiments, the first input port1401aand the second input port1401bmay be arranged differently. In some embodiments, the first input signal1434and the second input signal1436comprise differential signals.

In this embodiment, the first input port1401ais shown to receive the first input signal1434from a first differential power amplifier circuit1426and the second input port1401bis shown to receive the second input signal1436from a second differential amplifier circuit1428. However, in other embodiments, the first input port1401amay be configured to receive the first input signal1434and the second input port1401bmay be configured to receive the second input signal1436from other differential devices that are different from differential amplifiers. The first DAT circuit1402further comprises a first secondary winding circuit1403arranged next to the first primary winding circuit1401and comprising a first secondary conductive loop (e.g., metal winding) comprising a first output port1408configured to provide a first output signal1442. In some embodiments, the first output signal1442is generated at the first secondary winding circuit1403based on the first input signal1434and the second input signal1436. In some embodiments, the first output port1408is arranged to be orthogonal with respect to the first input port1401aand the second input port1401b. However, in other embodiments, the first output port1408may be arranged differently. In this embodiment, the first output port1408comprises a single-ended output port with one of the terminals grounded. However, in other embodiments, the first output port1408may comprise a differential output port.

In some embodiments, the second DAT circuit1404comprises a second primary winding circuit1451comprising a second primary conductive loop (e.g., metal winding) comprising a third input port1451aconfigured to receive a third input signal1438and a fourth input port1451bconfigured to receive a fourth input signal1440. In some embodiments, the third input port1451aand the fourth input port1451bare located at diagonally opposite directions with respect to one another along the second primary conductive loop. Alternately, in other embodiments, the third input port1451aand the fourth input port1451bmay be arranged differently. In some embodiments, the third input signal1438and the fourth input signal1440comprise differential signals. In this embodiment, the third input port1451ais shown to receive the third input signal1438from a third differential power amplifier circuit1430and the fourth input port1451bis shown to receive the fourth input signal1440from a fourth differential amplifier circuit1432. However, in other embodiments, the third input port1451amay be configured to receive the third input signal1438and the fourth input port1451bmay be configured to receive the fourth input signal1440from other differential devices that are different from differential amplifiers.

The second DAT circuit1404further comprises a second secondary winding circuit1453arranged next to the second primary winding circuit1451. In some embodiments, the second secondary winding circuit1453comprises a second secondary conductive loop (e.g., metal winding) comprising a second output port1458configured to provide a second output signal1444, based on the third input signal1438and the fourth input signal1440. In some embodiments, the second output port1458is arranged to be orthogonal with respect to the third input port1451aand the fourth input port1451b. However, in other embodiments, the second output port1458may be arranged differently. In this embodiment, the second output port1458comprises a single-ended output port with one of the terminals grounded. However, in other embodiments, the second output port1458may comprise a differential output port. In this embodiment, the first DAT circuit1402and the second DAT circuit1404are depicted as 2:1 power combiner configured to combine 2 input signals and generate an output signal based thereon. However, in other embodiments, the first DAT circuit1402and the second DAT circuit1404may be configured to combine more than 2 input signals. In such embodiments, the first primary winding circuit1401of the first DAT circuit1402and the second primary winding circuit1451of the second DAT circuit1404may comprise more than 2 input ports.

In some embodiments, the first output port1408of the first DAT circuit1402and the second output port1458of the second DAT circuit1404are electrically connected to one another. In some embodiments, the first output port1408of the first DAT circuit1402and the second output port1458of the second DAT circuit1404are electrically connected to one another at a coupling circuit1406. In some embodiments, the coupling circuit1406is implemented as a part of the DAT power combiner circuit1400. However, in other embodiments, the coupling circuit1406is implemented as a component external to the DAT power combiner circuit1400. In this embodiment, the coupling circuit1406comprises a radio frequency (RF) pad configured to be coupled to a load circuit. In some embodiments, an RF pad comprises a signal pad and 2 ground pads. Alternately, in other embodiments, the coupling circuit1406may be implemented differently. In some embodiments, the coupling circuit1406is physically located between the first DAT circuit1402and the second DAT circuit1404. In some embodiments, the first DAT circuit1402and the second DAT circuit1404are physically arranged in a way that the first output port1408of the first DAT circuit1402and the second output port1458of the second DAT circuit1404face one another from opposite directions. In some embodiments, the first output port1408of the first DAT circuit1402and the second output port1458of the second DAT circuit1404are exactly aligned with respect to one another. However, in other, embodiments, the alignment may be different. In some embodiments, such an arrangement enables the first DAT circuit1402and the second DAT circuit1404to couple to the coupling circuit1406from a minimum distance from the opposite ends. In some embodiments, reducing the distance between the output ports (i.e.,1408,1458) and the coupling circuit1406, reduces the loss associated with the extra leads connecting the output ports to the coupling circuit1406, thereby further reducing the insertion loss of the DAT power combiner circuit1400.

By making the secondary single-ended in the first DAT circuit1402, in some embodiments, a port imbalance is created between the impedances seen from each of the first input port1401aand the second input port1401b. Therefore, in order to compensate for the port imbalance, a first conductive line1415(e.g., a metal conductor or winding) is included within the first primary winding circuit1401, wherein the first conductive line1415(e.g., a metal conductor or winding) comprises a first end and a second, different end. In some embodiments, the first end of the first conductive line1415is coupled to a first segment (not shown) of the first primary conductive loop coupled between the first input port1401aand the second input port1401b, and the second end of the first conductive line1415is coupled to a second, different, segment (not shown) of the first primary conductive loop coupled between the first input port1401aand the second input port1401b, as explained above with respect toFIG.13c.

In some embodiments, the first conductive line1415forces the centers of the two segments of the first primary conductive loop to have the same potential and thereby improve the imbalance due to an asymmetry on the capacitive coupling between the primary winding circuit1401and secondary winding circuit1403. In some embodiments, the first DAT circuit1402further comprises a first dummy winding circuit1422comprising a first dummy conductive loop (e.g., a metal loop) having a first dummy port1424comprising a first dummy terminal that is grounded and a second, different, dummy terminal that is floating, as explained above with respect toFIG.13d. In some embodiments, the first dummy winding circuit1422is physically arranged next to the first primary winding circuit1401in a way that the first primary conductive loop is located between the first secondary conductive loop and the first dummy conductive loop. In some embodiments, the first dummy port1424is arranged in a diagonally opposite direction with respect to the first output port1408. In some embodiments, the first dummy winding circuit1422is also provided to compensate for the imbalance between the first primary winding circuit1401and the first secondary winding circuit1403.

Similarly, by making the secondary single-ended in the second DAT circuit1404, in some embodiments, a port imbalance is created between the impedances seen from each of the third input port1451aand the fourth input port1451b. Therefore, in order to compensate for the port imbalance, a second conductive line1465(e.g., a metal conductor or winding) is included within the second primary winding circuit1465. In some embodiments, the second conductive line1465comprises a first end and a second, different end, wherein the first end is coupled to a first segment (not shown) of the second primary conductive loop coupled between the third input port1451aand the fourth input port1451b, and the second end is coupled to a second, different, segment (not shown) of the second primary conductive loop coupled between the third input port1451aand the fourth input port1451b, as explained above with respect toFIG.13c.

In some embodiments, the second conductive line1465forces the centers of the two segments of the second primary conductive loop to have the same potential and thereby improve the imbalance due to an asymmetry on the capacitive coupling between the second primary winding circuit1451and the second secondary winding circuit1453. In some embodiments, the second DAT circuit1404further comprises a second dummy winding circuit1472comprising a second dummy conductive loop (e.g., a metal loop) having a second dummy port1474comprising a first dummy terminal that is grounded and a second, different, dummy terminal that is floating, as explained above with respect toFIG.13d. In some embodiments, the second dummy winding circuit1472is physically arranged next to the second primary winding circuit1451in a way that the second primary conductive loop is located between the second secondary conductive loop and the second dummy conductive loop. In some embodiments, the second dummy port1474is arranged in a diagonally opposite direction with respect to the second output port1458. In some embodiments, the second dummy winding circuit1472is also provided to compensate for the imbalance between the second primary winding circuit1451and the second secondary winding circuit1453.

FIG.15aandFIG.15billustrates a flowchart of a method1500of a distributed active transformer (DAT) power combiner circuit, according to one embodiment of the disclosure. It is noted herein that the flowchart1500inFIG.15bis a continuation of the flowchart1500inFIG.15aand are not to be construed as separate methods/flowcharts. The method1500is explained herein with reference to the DAT power combiner circuit1400inFIG.14. At1502, a first DAT circuit (e.g., the first DAT circuit1402inFIG.14) comprising a first primary winding circuit (e.g., first primary winding circuit1401in FIG.14) and a first secondary winding circuit (e.g., the first secondary winding circuit1403inFIG.14) is provided. In some embodiments, the first primary winding circuit comprises a first primary conductive loop comprising at least two input ports (e.g., the first input port1401aand the second input port1401binFIG.14) configured to receive at least two input signals (e.g., the first input signal1434and the second input signal1436inFIG.14), respectively associated therewith; and the first secondary winding circuit comprises a first secondary conductive loop comprising a first output port (e.g., the first output port1408inFIG.14) configured to provide a first output signal (e.g., the first output signal1442inFIG.14), based on the at least two input signals associated with the first primary winding circuit.

At1504, a second DAT circuit (e.g., the second DAT circuit1404inFIG.14) comprising a second primary winding circuit (e.g., the second primary winding circuit1451inFIG.14) and a second secondary winding circuit (e.g., the second secondary winding circuit1453inFIG.14) is provided. In some embodiments, the second primary winding circuit comprises a second primary conductive loop comprising at least two input ports (e.g., the third input port1451aand the fourth input port1451binFIG.14) configured to receive at least two input signals (e.g., the third input signal1438and the fourth input signal1440inFIG.14), respectively associated therewith; and the second secondary winding circuit comprises a second secondary conductive loop comprising a second output port (e.g., the second output port1458inFIG.14) configured to provide a second output signal (e.g., the second output signal1444inFIG.14), based on the at least two input signals associated with the second DAT circuit. In some embodiments, the two input signals associated with the first primary winding circuit and the two input signals associated with the second primary winding circuit are different. At1506, the first output port of the first DAT circuit and the second output port of the second DAT circuit are arranged to face one another from opposite directions. At1508, the first output port and the second output are coupled to a coupling circuit (e.g., the coupling circuit1406inFIG.14) physically located between the first output port of the first DAT circuit and the second output port of the second DAT circuit.

At1510, a first conductive line (e.g., the first conductive line1415inFIG.14) is provided within the first primary winding circuit. In some embodiments, the first conductive line comprises a first end coupled to a first segment of the first primary conductive loop, and a second end coupled to a second, different, segment of the first primary conductive loop, as explained above with respect toFIG.14. In some embodiments, the first conductive line is provided when the first primary winding circuit comprises 2 input ports. In some embodiments, the first conductive line is provided to compensate for the port imbalance, as explained with respect toFIG.13candFIG.14above. At1512, a second conductive line (e.g., the second conductive line1465inFIG.14) is provided within the second primary winding circuit. In some embodiments, the second conductive line comprises a first end coupled to a first segment of the first primary conductive loop, and a second end coupled to a second, different, segment of the first primary conductive loop. In some embodiments, the second conductive line is provided when the second primary winding circuit comprises 2 input ports. In some embodiments, the second conductive line is provided to compensate for the port imbalance, as explained with respect toFIG.13candFIG.14above.

At1514, a first dummy winding circuit (e.g., the first dummy winding circuit1422inFIG.14) is provided within the first DAT circuit. In some embodiments, the first dummy winding circuit comprises a first dummy conductive loop having a first dummy port (e.g., the first dummy port1424inFIG.14) comprising a first dummy terminal that is grounded and a second, different, dummy terminal that is floating. In some embodiments, the first dummy conductive loop is physically arranged in a way that the first primary conductive loop is located between the first secondary conductive loop and the first dummy conductive loop. At1516, a second dummy winding circuit (e.g., the second dummy winding circuit1472inFIG.14) is provided within the second DAT circuit. In some embodiments, the second dummy winding circuit comprises a second dummy conductive loop having a second dummy port (e.g., the second dummy port1474inFIG.14) comprising a first dummy terminal that is grounded and a second, different, dummy terminal that is floating. In some embodiments, the second dummy conductive loop is physically arranged in a way that the second primary conductive loop is located between the second secondary conductive loop and the second dummy conductive loop.

FIG.16depicts a simplified block diagram of a stacked differential amplifier circuit1600, according to one embodiment of the disclosure. The stacked differential amplifier circuit1600comprises a differential amplifier circuit1602, a stacked amplifier circuit1604and a control circuit1606. In some embodiments, the differential amplifier circuit1602comprises a plurality of unit cell amplifier circuits coupled in parallel to one another. In some embodiments, each of the unit cell amplifier circuits associated with the differential amplifier circuit1602may be configured to receive a differential input signal1608. In some embodiments, each of the unit cell amplifier circuits may comprise a first unit cell transistor circuit and a second, different, unit cell transistor circuit coupled to one another in a differential arrangement, further details of which are given in an embodiment below. In some embodiments, the stacked amplifier circuit1604may comprise a first stacked transistor circuit and a second stacked transistor circuit and is configured to be coupled to the differential amplifier circuit1602, further details of which are given in an embodiment below. In particular, in some embodiments, the first unit cell transistor circuit associated with each of the unit cell amplifier circuits are configured to be coupled in series to the first stacked transistor circuit associated with the stacked amplifier circuit1604. Similarly, in some embodiments, the second unit cell transistor circuit associated with each of the unit cell amplifier circuits are configured to be coupled in series to the second stacked transistor circuit associated with the stacked amplifier circuit1604.

In some embodiments, each of the unit cell amplifier circuits associated with the differential amplifier circuit1602may comprise a respective tail current switch circuit coupled to the differential arrangement of the first unit cell transistor circuit and the second unit cell transistor circuit. In some embodiments, the tail current switch circuit is configured to selectively activate or deactivate a respective unit cell amplifier circuit. In some embodiments, the control circuit1606is coupled to the differential amplifier circuit1602and is configured to selectively turn on or turn off one or more the tail current switch circuits associated therewith, in order to selectively activate or deactivate one or more respective unit cell amplifier circuits. In some embodiments, selectively activating and deactivating one or more unit cell amplifier circuits enables to improve the efficiency of the stacked differential amplifier circuit1600during low power operations. In some embodiments, the control circuit1606comprises a digital control circuit configured to control the plurality of tail current switch circuits digitally. In some embodiments, when all the unit cell amplifier circuits are activated, the stacked differential amplifier circuit1600operates at its peak output power. In some embodiments, each of the unit cell amplifier circuits are identical to one another. However, in other embodiments, each of the unit cell amplifier circuits may be different. In some embodiments, in order to enable digital configurability, the configuration of each of the unit cell amplifier circuit is derived based on segmenting a differential amplifier circuit (or the transistors associated therewith) configured for peak power operation into the plurality of unit cell amplifier circuits in a binary fashion (e.g., if segmented into 7 bits, then 128 identical unit cell amplifier circuits may be derived).

FIG.17depicts a stacked differential amplifier circuit1700, according to one embodiment of the disclosure. In some embodiments, the stacked differential amplifier circuit1700depicts a detailed diagram of the stacked differential amplifier circuit1600inFIG.16. The stacked differential amplifier circuit1700comprises a differential amplifier circuit1702, a stacked amplifier circuit1704and a control circuit1706. In some embodiments, the differential amplifier circuit1702comprises a plurality of unit cell amplifier circuits1702a,1702b. . .1702K coupled in parallel to one another. In some embodiments, each of the unit cell amplifier circuits, for example, the unit cell amplifier circuit1702acomprises a first unit cell transistor circuit1708comprising a first transistor terminal1710, a second transistor terminal1712and a third transistor terminal1714. In some embodiments, the unit cell amplifier circuit1702afurther comprises a second unit cell transistor circuit1716comprising a fourth transistor terminal1720, a fifth transistor terminal1718and a sixth transistor terminal1722. All the explanation given here with respect to the unit cell amplifier circuit1702ais equally applicable to all the unit cell amplifier circuits1702a. . .1702K, and is not to be construed to be Ii d to the unit cell amplifier circuit1702a.

In some embodiments, the first unit cell transistor circuit1708and the second unit cell transistor circuit1716comprises metal-oxide semiconductor field effect transistors (MOSFETs). In some embodiments, first transistor terminal1710, the second transistor terminal1712and the third transistor terminal1714associated with the first unit cell transistor circuit1708comprises a source terminal, a drain terminal and a gate terminal, respectively. However, in other embodiments, the first transistor terminal1710, the second transistor terminal1712and the third transistor terminal1714associated with the first unit cell transistor circuit1708may be configured differently. Similarly, in some embodiments, the fourth transistor terminal1720, the fifth transistor terminal1718and the sixth transistor terminal1722associated with the second unit cell transistor circuit1716comprises a source terminal, a drain terminal and a gate terminal, respectively. However, in other embodiments the fourth transistor terminal1720, the fifth transistor terminal1718and the sixth transistor terminal1722associated with the second unit cell transistor circuit1716may be configured differently.

In some embodiments, the first transistor terminal1710of the first unit cell transistor circuit1708and the fourth transistor terminal1720of the second unit cell transistor circuit1716are coupled to one another to form a differential arrangement. In some embodiments, the second transistor terminal1712of the first unit cell transistor circuit1708associated with each of the unit cell amplifier circuits1702a,1702b. . .1702K are coupled together to form a first differential output terminal1728associated with the differential amplifier circuit1702. Similarly, the fifth transistor terminal1718of the second unit cell transistor circuit1716associated with each of the unit cell amplifier circuits1702a,1702b. . .1702K are coupled together to form a second differential output port1730associated with the differential amplifier circuit1702. In some embodiments, the third transistor terminal1714of the first unit cell transistor circuit1708and the sixth transistor terminal1722of the second unit cell transistor circuit1716associated with each of the unit cell amplifier circuits1702a,1702b. . .1702K may be coupled to a differential input circuit (not shown) configured to provide a differential input signal1760to the unit cell amplifier circuits1702a,1702b. . .1702K.

In some embodiments, the third transistor terminal1714of the first unit cell transistor circuit1708and the sixth transistor terminal1722of the second unit cell transistor circuit1716associated with each of the unit cell amplifier circuits1702a,1702b. . .1702K may be further coupled to an input bias circuit (not shown) configured to provide a bias voltage to the third transistor terminal1714of the first unit cell transistor circuit1708and the sixth transistor terminal1722of the second unit cell transistor circuit1716. In some embodiments, the unit cell amplifier circuit1702afurther comprises a tail current switch circuit1746comprising a transistor circuit configured to selectively activate or deactivate the unit cell amplifier circuit1702a. In some embodiments, when the tail current switch circuit1746is turned on, the respective unit cell amplifier circuit (e.g., the unit cell amplifier circuit1702a) is activated and when the tail current switch circuit1746is turned off, the respective unit cell amplifier circuit is deactivated. In some embodiments, the tail current switch circuit1746comprises a first tail terminal1748, a second tail terminal1750and a third tail terminal1752. In some embodiments, the first tail terminal1748, the second tail terminal1750and the third tail terminal1752comprises a drain terminal, a source terminal and a gate terminal, respectively. However, in other embodiments, the first tail terminal1748, the second tail terminal1750and the third tail terminal1752associated with the tail current switch circuit1746may be configured differently.

In some embodiments, the first tail terminal1748of the tail current switch circuit1746is coupled to a differential conductive line1762that couples the first transistor terminal1710of the first unit cell transistor circuit1708and the fourth transistor terminal1720of the second unit cell transistor circuit1716. In some embodiments, the differential conductive line1762refers to any conductive medium that electrically couples the first transistor terminal1710of the first unit cell transistor circuit1708and the fourth transistor terminal1720of the second unit cell transistor circuit1716. In some embodiments, the differential conductive line1762may be part of the first transistor terminal1710and the fourth transistor terminal1720itself. However, in other embodiments, the differential conductive line1762may not be a part of the first transistor terminal1710and the fourth transistor terminal1720itself, and may include a conductive trace etc. In some embodiments, the second tail terminal1750of the tail current switch circuit1746is coupled to a common ground.

Further, in some embodiments, the third tail terminal1752of the tail current switch circuit1746is coupled to the control circuit1706. In some embodiments, the control circuit1706is configured to turn on or turn off the tail current switch circuit1746, in order to selectively activate or deactivate the unit cell amplifier circuit1702a, based on the output requirements of the stacked differential amplifier circuit1700, In some embodiments, the control circuit1706is further configured to turn on or turn off one or more of the tail current switch circuits1746associated with the one or more of the unit cell amplifier circuits1702a,1702b. . .1702K, in order to selectively activate or deactivate the respective unit cell amplifier circuits. In some embodiments, selectively activating and deactivating one or more unit cell amplifier circuits1702a,1702b, . . .1702K enables to improve the efficiency of the stacked differential amplifier circuit1700during low power operations. In some embodiments, the control circuit1706comprises a digital control circuit configured to control the plurality of tail current switch circuits digitally. In some embodiments, when all the unit cell amplifier circuits1702a,1702b. . .1702K are activated, the stacked differential amplifier circuit1700operates at its peak output power. In some embodiments, configuration of each of the unit cell amplifier circuits1702a,1702b. . .1702K are identical to one another. However, in other embodiments, configuration of each of the unit cell amplifier circuits1702a,1702b. . .1702K may be different. In some embodiments, in order to enable digital configurability, the configuration of each of the unit cell amplifier circuits1702a,1702b. . .1702K is derived based on segmenting a differential amplifier circuit (or the transistors associated therewith) configured for peak power operation into the plurality of unit cell amplifier circuits in a binary fashion (e.g., if segmented into 7 bits, then 128 identical unit cell amplifier circuits may be derived).

In some embodiments, the stacked amplifier circuit1704comprises a first stacked transistor circuit1733comprising a first stacked terminal1734, a second stacked terminal1742and a third stacked terminal1738. In some embodiments, the stacked amplifier circuit1704further comprises a second stacked transistor circuit1735comprising a fourth stacked terminal1736, a fifth stacked terminal1744and a sixth stacked terminal1740. In some embodiments, the first stacked transistor circuit1733and the second stacked transistor circuit1735comprise MOSFETs. In some embodiments, the first stacked terminal1734, the second stacked terminal1742and the third stacked terminal1738associated with the first stacked transistor circuit1733comprises a source terminal, a drain terminal and a gate terminal, respectively. However, in other embodiments, the first stacked terminal1734, the second stacked terminal1742and the third stacked terminal1738associated with the first stacked transistor circuit1733may be configured differently. In some embodiments, the fourth stacked terminal1736, the fifth stacked terminal1744and the sixth stacked terminal1740associated with the second stacked transistor circuit1735comprises a source terminal, a drain terminal and a gate terminal, respectively. However, in other embodiments, the fourth stacked terminal1736, the fifth stacked terminal1744and the sixth stacked terminal1740associated with the second stacked transistor circuit1735may be configured differently.

In some embodiments, the first stacked terminal1734of the first stacked transistor circuit1733is coupled to the first differential output terminal1728of the differential amplifier circuit1702. Similarly, in some embodiments, the fourth stacked terminal1736of the second stacked transistor circuit1735is coupled to the second differential output terminal1730of the differential amplifier circuit1702. In some embodiments, the second stacked terminal1742of the first stacked transistor circuit1733and the fifth stacked terminal1744of the second stacked transistor circuit1735are configured to be coupled to a further circuit (not shown), for example, a load circuit. In some embodiments, the second stacked terminal1742of the first stacked transistor circuit1733and the fifth stacked terminal1744of the second stacked transistor circuit1735together comprises a differential output port associated with the stacked differential amplifier circuit1700and is configured to provide a differential output signal to the further circuit. In some embodiments, the further circuit may comprise another stacked amplifier circuit (not shown) to enable multiple levels of stacking, in order to increase the output power delivered by the stacked differential amplifier circuit1700. In some embodiments, the third stacked terminal1738of the first stacked transistor circuit1733may be coupled to a first stacked bias circuit (not shown) configured to bias the first stacked transistor circuit1733. Similarly, in some embodiments, the sixth stacked terminal1740of the second stacked transistor circuit1735may be coupled to a second stacked bias circuit (not shown) configured to bias the second stacked transistor circuit1735.

In some embodiments, the unit cell amplifier circuit1702afurther comprises a first neutralization capacitance1724coupled between the drain terminal1712of the first unit cell transistor circuit1708and the gate terminal1722of the second unit cell transistor circuit1716. In some embodiments, the first neutralization capacitance1724enables to neutralize the gate drain capacitance associated with the first unit cell transistor circuit1708. In some embodiments, the first neutralization capacitance1724for each of the unit cell amplifier circuits1702a,1702b. . .1702K are realized using overlapping metal capacitances, thereby enabling to realize a compact layout. In some embodiments, the unit cell amplifier circuit1702afurther comprises a second neutralization capacitance1726coupled between the drain terminal1718of the second unit cell transistor circuit1716and the gate terminal1714of the first unit cell transistor circuit1708. In some embodiments, the second neutralization capacitance1726enables to neutralize the gate drain capacitance associated with the second unit cell transistor circuit1716. In some embodiments, the second neutralization capacitance1726for each of the unit cell amplifier circuits1702a,1702b. . .1702K are realized using overlapping metal capacitances, thereby enabling to realize a compact layout.

In some embodiments, the stacked differential amplifier circuit1700further comprises a differential shunt stub circuit1732. In some embodiments, the differential shunt stub circuit1732is configured to provide a better match between the first unit cell transistor circuit1708associated with each of the unit cell amplifier circuits1702a,1702b. . .1702K and the first stacked amplifier circuit1733. In some embodiments, the differential shunt stub circuit1732is further configured to provide a better match between the second unit cell transistor circuit1716associated with each of the unit cell amplifier circuits1702a,1702b. . .1702K and the second stacked amplifier circuit1735. In some embodiments, the differential shunt stub circuit1732comprises a transmission line. However, in other embodiments, the differential shunt stub circuit1732may be implemented differently. In some embodiments, the differential shunt stub circuit1732comprises a first end and a second, different end. In some embodiments, the first end of the differential shunt stub circuit1732is coupled to a first conductive line1754that couples the first differential output terminal1728of the differential amplifier circuit1702to the first stacked terminal1734of the first stacked transistor circuit1733. In some embodiments, the second end of the differential shunt stub circuit1732is coupled to a second conductive line1756that couples the second differential output terminal1730of the differential amplifier circuit1702to the fourth stacked terminal1736of the second stacked transistor circuit1735. In some embodiments, the first conductive line1754refers to any conductive medium that electrically couples the first differential output terminal1728of the differential amplifier circuit1702to the first stacked terminal1734of the first stacked transistor circuit1733. In some embodiments, the first conductive line1754may be part of the first differential output terminal1728and the first stacked terminal1734itself. However, in other embodiments, the first conductive line1754may not be a part of the first differential output terminal1728and the first stacked terminal1734itself, and may include a conductive trace etc. Similarly, in some embodiments, the second conductive line1756refers to any conductive medium that electrically couples the second differential output terminal1730of the differential amplifier circuit1702to the fourth stacked terminal1736of the second stacked transistor circuit1735, In some embodiments, the second conductive line1756may be part of the second differential output terminal1730and the fourth stacked terminal1736itself. However, in other embodiments, the second conductive line1756may not be a part of the second differential output terminal1730and the fourth stacked terminal1736itself, and may include a conductive trace etc.

FIG.18aandFIG.18billustrates a flowchart of a method1800of a stacked differential amplifier circuit, according to one embodiment of the disclosure. It is noted herein that the flowchart1800inFIG.18bis a continuation of the flowchart1800inFIG.18aand are not to be construed as separate methods/flowcharts. The method1800is explained herein with reference to the stacked differential amplifier circuit1700inFIG.17. At1802, a differential amplifier circuit (e.g., the differential amplifier circuit1702inFIG.17) comprising a plurality of unit cell amplifier circuits (e.g., the plurality of unit cell amplifier circuits1702a,1702b. . .1702K) in parallel is provided. At1804, a first unit cell transistor circuit (e.g., the first unit cell transistor circuit1708inFIG.17) comprising a first transistor terminal (e.g., the first transistor terminal1710inFIG.17) and a second transistor terminal (e.g., the second transistor terminal1712inFIG.17); and a second unit cell transistor circuit (e.g., the second unit cell transistor circuit1716inFIG.17) comprising a fourth transistor terminal (e.g., the fourth transistor terminal1720inFIG.17) and a fifth transistor terminal (e.g., the fifth transistor terminal1718inFIG.17) are provided within each unit cell amplifier circuit. In some embodiments, the first transistor terminal of the first unit cell transistor circuit and the fourth transistor terminal of the second unit cell transistor circuit are coupled to one another to form a differential arrangement. At1806, the second transistor terminal of the first unit cell transistor circuit associated with each of the unit cell amplifier circuits is coupled to one another to form a first differential output terminal (e.g., the first differential output terminal1728inFIG.17) associated with the differential amplifier circuit; and the fifth transistor terminal of the second unit cell transistor circuit associated with each of the unit cell amplifier circuits are coupled to one another to form a second differential output terminal (e.g., the second differential output terminal1730inFIG.17) associated with the differential amplifier circuit.

At1808, a tail current switch circuit (e.g., the tail current switch circuit1746inFIG.17) is provided within each of the unit cell amplifier circuits. In some embodiments, the tail current switch circuit is configured to selectively activate or deactivate the respective unit cell amplifier circuit. At1810, a control circuit (e.g., the control circuit1706inFIG.17) configured to turn off or turn on the tail current switch circuits associated with the plurality of unit cell amplifier circuits is provided. In some embodiments, the control circuit comprises a digital control circuit configured to turn on or turn off the tail current switch circuit digitally. In some embodiments, turning on or turning off the tail current switch circuits enables to activate or deactivate the respective unit cell amplifier circuits. At1814, a first neutralization capacitance (e.g., the first neutralization capacitance1724inFIG.17) is provided within each unit cell amplifier circuit between the drain terminal (e.g., the drain terminal1712inFIG.17) of the first unit cell transistor circuit and the gate terminal (e.g., the gate terminal1722inFIG.17) of the second unit cell transistor circuit, and a second neutralization capacitance (e.g., the second neutralization capacitance1726inFIG.17) is provided within each unit cell amplifier circuit between the drain terminal (e.g., the drain terminal1718inFIG.17) of the second unit cell transistor circuit and the gate terminal (e.g., the gate terminal1714inFIG.17) of the first unit cell transistor circuit.

At1816, a stacked amplifier circuit (e.g., the stacked amplifier circuit1704inFIG.17) comprising a first stacked transistor circuit (e.g., the first stacked transistor circuit1733inFIG.17) having a first stacked terminal (e.g., the first stacked terminal1734) coupled to the first differential output terminal of the differential amplifier circuit; and a second stacked transistor circuit (e.g., the second stacked transistor circuit1735inFIG.17) having a fourth stacked terminal (e.g., the fourth stacked terminal1736inFIG.17) coupled to the second differential output terminal of the differential amplifier circuit is provided. At1818, a differential shunt stub circuit (e.g., the differential shunt stub circuit1732inFIG.17) having a first end and a second, different end is provided. In some embodiments, the first end of the differential shunt stub circuit is coupled to a first conductive line (e.g., the first conductive line1754inFIG.17) that couples the first differential output terminal of the differential amplifier circuit to the first stacked terminal of the first stacked transistor circuit and wherein the second end of the differential shunt stub circuit is coupled to a second conductive line (e.g., the second conductive line1756inFIG.17) that couples the second differential output terminal of the differential amplifier circuit to the fourth stacked terminal of the second stacked transistor circuit.

While the methods are illustrated and described above as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the disclosure herein. Also, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

While the apparatus has been illustrated and described with respect to one or more implementations, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention.

In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the disclosure. In addition, while a particular feature may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application.

While the invention has been illustrated, and described with respect to one or more implementations, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention.

Examples can include subject matter such as a method, means for performing acts or blocks of the method, at least one machine-readable medium including instructions that, when performed by a machine cause the machine to perform acts of the method or of an apparatus or system for concurrent communication using multiple communication technologies according to embodiments and examples described herein.

Example 1 is an on-chip transformer circuit, comprising a primary winding circuit comprising at least one turn of a primary conductive winding arranged as a first N-sided polygon in a first dielectric layer of a substrate; and a secondary winding circuit comprising at least one turn of a secondary conductive winding arranged as a second N-sided polygon in a second, different, dielectric layer of the substrate; and wherein the primary winding circuit and the secondary winding circuit are arranged to overlap one another at predetermined locations along the primary conductive winding and the secondary conductive winding, wherein the predetermined locations comprise a number of locations less than all locations along the primary conductive winding and the secondary conductive winding.

Example 2 is a transformer circuit, including the subject matter of example 1, wherein the primary winding circuit comprises a primary feeding port comprising two primary signal terminals associated with the primary conductive winding arranged on any one side of the first N-sided polygon and wherein the secondary winding circuit comprises a secondary feeding port comprising two secondary signal terminals associated with the secondary conductive winding arranged on any one side of the second N-sided polygon.

Example 3 is a transformer circuit, including the subject matter of examples 1-2, including or omitting elements, wherein the secondary winding circuit is rotated with respect to the primary winding circuit by a predefined rotation angle such that the primary winding circuit and the secondary winding circuit overlap one another at the predetermined locations along the primary conductive winding and the secondary conductive winding.

Example 4 is a transformer circuit, including the subject matter of examples 1-3, including or omitting elements, wherein the primary winding circuit and the secondary winding circuit are identical to one another in shape and size.

Example 5 is a transformer circuit, including the subject matter of examples 1-4, including or omitting elements, wherein the primary winding circuit and the secondary winding circuit are symmetrically arranged with respect to a common center point and wherein the secondary winding circuit is rotated with respect to the primary winding circuit by the predefined rotation angle in reference to the common center point.

Example 6 is a transformer circuit, including the subject matter of examples 1-5, including or omitting elements, wherein the primary winding circuit is arranged to be symmetric with respect to a primary center line comprising a straight line between the two primary terminals of the primary feeding port associated with the primary winding circuit and the secondary winding circuit is arranged to be symmetric with respect to a secondary center line comprising a straight line between the two secondary terminals of the secondary feeding port associated with the secondary winding circuit, wherein the primary center line and the secondary center line passes through the common center point.

Example 7 is a transformer circuit, including the subject matter of examples 1-6, including or omitting elements, wherein the N-sided polygon associated with the primary winding circuit and the secondary winding circuit comprises an octagon.

Example 8 is a transformer circuit, including the subject matter of examples 1-7, including or omitting elements, wherein the predefined rotation angle between the primary winding circuit and the secondary winding circuit comprises 45 degrees.

Example 9 is a transformer circuit, including the subject matter of examples 1-8, including or omitting elements, wherein the secondary conductive winding associated with the secondary winding circuit and the primary conductive winding associated with the primary winding circuit are interleaved with respect to one another, at one or more respective sides, forming one or more interleaved sides, along the primary conductive winding and the secondary conductive winding such that the primary winding circuit and the secondary winding circuit overlap one another at the predetermined locations along the primary conductive winding and the secondary conductive winding.

Example 10 is a transformer circuit, including the subject matter of examples 1-9, including or omitting elements, wherein the primary winding circuit and the secondary winding circuit are arranged to be symmetrical with respect to a center line, wherein the center line passes through the middle of the two primary signal terminals associated with the primary conductive winding and two secondary signal terminals associated with the secondary conductive winding, and wherein the two primary signal terminals and the two secondary terminals are arranged in opposite directions with respect to one another.

Example 11 is a transformer circuit, including the subject matter of examples 1-10, including or omitting elements, wherein the N sides of primary winding circuit are symmetrically aligned with respect to corresponding N sides of the secondary winding circuit, forming N aligned sides of the on-chip transformer circuit

Example 12 is a transformer circuit, including the subject matter of examples 1-11, including or omitting elements, wherein the one or more interleaved sides comprises at least one side pair, wherein the at least one side pair comprises two aligned sides that are mirrored about the center line.

Example 13 is a transformer circuit, including the subject matter of examples 1-12, including or omitting elements, wherein the one or more interleaved sides comprises every aligned side except the aligned sides comprising the primary feeding port and the secondary feeding port.

Example 14 is a transformer circuit, including the subject matter of examples 1-13, including or omitting elements, wherein the primary winding circuit comprises a primary center-tap port comprising a metal connection coupled to a center point of the primary conductive winding with respect to the two primary signal terminals, and wherein the secondary winding circuit comprises a secondary center-tap port comprising a metal connection coupled to a center point of the secondary conductive winding with respect to the two secondary signal terminals.

Example 15 is a transformer circuit, including the subject matter of examples 1-14, including or omitting elements, wherein the N sides of the first N-sided polygon and the second N-sided polygon comprises four or more sides.

Example 16 is a transformer circuit, including the subject matter of examples 1-15, including or omitting elements, wherein the first N-sided polygon and the second N-sided polygon comprise equal sided polygons or non-equal sided polygons.

Example 17 is a transformer circuit, including the subject matter of examples 1-16, including or omitting elements, wherein the first N-sided polygon and the second N-sided polygon comprise equal sided polygons.

Example 18 is a transformer circuit, including the subject matter of examples 1-17, including or omitting elements, further comprising a primary center tap port comprising a first conductive connection in a third, different layer of the substrate and coupled to a center point of the primary conductive winding via a plurality of vias, and a secondary center tap port comprising a second conductive connection in the third layer of the substrate and coupled to a center point of the secondary conductive winding via a plurality of vias.

Example 19 is a distributed active transformer (DAT) power combiner circuit, comprising a first DAT circuit comprising a first primary winding circuit comprising a first primary conductive loop comprising at least two input ports configured to receive at least two input signals, respectively associated therewith; and a first secondary winding circuit comprising a first secondary conductive loop comprising a first output port configured to provide a first output signal, based on the at least two input signals associated with the first primary winding circuit; and a second DAT circuit comprising a second primary winding circuit comprising a second primary conductive loop comprising at least two input ports configured to receive at least two input signals, respectively associated therewith; and a second secondary winding circuit comprising a second secondary conductive loop comprising a second output port configured to provide a second output signal, based on the at least two input signals associated with the second primary winding circuit, wherein the two input signals associated with the first primary winding circuit and the two input signals associated with the second primary winding circuit are different; and wherein the first DAT circuit and the second DAT circuit are physically arranged in a way that the first output port of the first DAT circuit and the second output port of the second DAT circuit face one another from opposite directions.

Example 20 is a DAT circuit, including the subject matter of example 19, wherein the first output port of the first DAT circuit and the second output port of the second DAT circuit are coupled to a coupling circuit physically located between the first output port of the first DAT circuit and the second output port of the second DAT circuit.

Example 21 is a DAT circuit, including the subject matter of examples 19-20, including or omitting elements, wherein the first output port and the second output port are electrically connected to one another at the coupling circuit.

Example 22 is a DAT circuit, including the subject matter of examples 19-21, including or omitting elements, wherein the coupling circuit comprises a radio frequency (RF) pad configured to be coupled to a load circuit.

Example 23 is a DAT circuit, including the subject matter of examples 19-22, including or omitting elements, wherein the coupling circuit comprises a load circuit.

Example 24 is a DAT circuit, including the subject matter of examples 19-23, including or omitting elements, wherein the at least two input ports associated with the first primary circuit and the second primary circuit comprise differential input ports, and wherein the first output port and the second output port comprise single-ended output ports.

Example 25 is a DAT circuit, including the subject matter of examples 19-24, including or omitting elements, wherein the at least two input ports associated with the first primary circuit comprises a first input port configured to receive a first input signal and a second, different, input port configured to receive a second input signal; and wherein the at least two input ports associated with the second primary winding circuit comprises a third input port configured to receive a third input signal and a fourth, different, input port configured to receive a fourth input signal.

Example 26 is a DAT circuit, including the subject matter of examples 19-25, including or omitting elements, wherein the first primary winding circuit associated with the first DAT circuit further comprises a first conductive line having a first end and a second, different end, wherein the first end is coupled to a first segment of the first primary conductive loop coupled between the first input port and the second input port, and the second end is coupled to a second, different, segment of the first primary conductive loop coupled between the first input port and the second input port.

Example 27 is a DAT circuit, including the subject matter of examples 19-26, including or omitting elements, wherein the second primary winding circuit associated with the second DAT circuit further comprises a second conductive line having a first end and a second, different end, wherein the first end is coupled to a first segment of the second primary conductive loop coupled between the third input port and the fourth input port, and the second end is coupled to a second, different, segment of the second primary conductive loop coupled between the third input port and the fourth input port.

Example 28 is a DAT circuit, including the subject matter of examples 19-27, including or omitting elements, wherein the first DAT circuit further comprises a first dummy winding circuit comprising a first dummy conductive loop having a first dummy port comprising a first dummy terminal that is grounded and a second, different, dummy terminal that is floating, wherein the first dummy conductive loop is physically arranged in a way that the first primary conductive loop is located between the first secondary conductive loop and the first dummy conductive loop.

Example 29 is a DAT circuit, including the subject matter of examples 19-28, including or omitting elements, wherein the second DAT circuit further comprises a second dummy winding circuit comprising a second dummy conductive loop having a second dummy port comprising a first dummy terminal that is grounded and a second, different, dummy terminal that is floating, wherein the second dummy conductive loop is physically arranged in a way that the second primary conductive loop is located between the second secondary conductive loop and the second dummy conductive loop.

Example 30 is a stacked differential amplifier circuit, comprising a differential amplifier circuit comprising a first differential output terminal and a second differential output terminal; and a stacked amplifier circuit, comprising a first stacked transistor circuit comprising a first stacked terminal coupled to the first differential output terminal of the differential amplifier circuit; and a second stacked transistor circuit comprising a fourth stacked terminal coupled to the second differential output terminal of the differential amplifier circuit; wherein the differential amplifier circuit comprises a plurality of unit cell amplifier circuits in parallel, each unit cell amplifier circuit comprising a first unit cell transistor circuit comprising a first transistor terminal and a second transistor terminal; and a second unit cell transistor circuit comprising a fourth transistor terminal and a fifth transistor terminal, wherein the first transistor terminal of the first unit cell transistor circuit and the fourth transistor terminal of the second unit cell transistor circuit are coupled to one another to form a differential arrangement; wherein the second transistor terminal of the first unit cell transistor circuit associated with each of the unit cell amplifier circuits are coupled together to form the first differential output terminal; wherein the fifth transistor terminal of the second unit cell transistor circuit associated with each of the unit cell amplifier circuits are coupled together to form the second differential output terminal; and wherein each of the unit cell amplifier circuits is configured to be selectively activated or deactivated, based on the output requirements of the stacked differential amplifier circuit.

Example 31 is a stacked differential amplifier circuit, including the subject matter of example 30, including or omitting elements, wherein each of the unit cell amplifier circuit further comprises a respective tail current switch circuit coupled to a differential conductive line that couples the first transistor terminal of the first unit cell transistor circuit and the fourth transistor terminal of the second unit cell transistor circuit, and wherein the tail current switch circuit is configured to selectively activate or deactivate the respective unit cell amplifier circuit.

Example 32 is a stacked differential amplifier circuit, including the subject matter of examples 30-31, including or omitting elements, further comprising a control circuit configured to turn on or turn off one or more of the tail current switch circuits digitally, in order to selectively activate or deactivate the respective unit cell amplifier circuits.

Example 33 is a slacked differential amplifier circuit, including the subject matter of examples 30-32, including or omitting elements, wherein the first transistor terminal and the second transistor terminal of first unit cell transistor circuit comprises a source terminal and a drain terminal respectively, and wherein the fourth transistor terminal and the fifth transistor terminal of second unit cell transistor circuit comprises a source terminal and a drain terminal respectively.

Example 34 is a stacked differential amplifier circuit, including the subject matter of examples 30-33, including or omitting elements, wherein each of the unit cell amplifier circuit further comprises a first neutralization capacitance between the drain terminal of the first unit cell transistor circuit and a gate terminal of the second unit cell transistor circuit, and a second neutralization capacitance between the drain terminal of the second unit cell transistor circuit and a gate terminal of the first unit cell transistor circuit.

Example 35 is a stacked differential amplifier circuit, including the subject matter of examples 30-34, including or omitting elements, further comprising a differential shunt stub circuit having a first end and a second, different end, wherein the first end is coupled to a first conductive line that couples the first differential output terminal of the differential amplifier circuit to the first stacked terminal of the first stacked transistor circuit and wherein the second end is coupled to a second conductive line that couples the second differential output terminal of the differential amplifier circuit to the fourth stacked terminal of the second stacked transistor circuit.

Various illustrative logics, logical blocks, modules, and circuits described in connection with aspects disclosed herein can be implemented or performed with a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform functions described herein. A general-purpose processor can be a microprocessor, but, in the alternative, processor can be any conventional processor, controller, microcontroller, or state machine.

The above description of illustrated embodiments of the subject disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosed embodiments to the precise forms disclosed. While specific embodiments and examples are described herein for illustrative purposes, various modifications are possible that are considered within the scope of such embodiments and examples, as those skilled in the relevant art can recognize.

In this regard, while the disclosed subject matter has been described in connection with various embodiments and corresponding Figures, where applicable, it is to be understood that other similar embodiments can be used or modifications and additions can be made to the described embodiments for performing the same, similar, alternative, or substitute function of the disclosed subject matter without deviating therefrom. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, but rather should be construed in breadth and scope in accordance with the appended claims below.

In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the disclosure. In addition, while a particular feature may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application.