Patent ID: 12232312

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.

In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

FIG.1is a schematic cross-sectional side view of a memory device100in accordance with some embodiments of the present disclosure.FIG.2is a schematic cross-sectional top view of the memory device100illustrated inFIG.1.FIG.1is the cross-sectional side view along a line AA inFIG.2. In some embodiments, the memory device100as shown inFIG.1can be a part of device. In some embodiments, the memory device100includes several unit cells arranged along rows and columns.

In some embodiments, the memory device100includes a semiconductor substrate101. In some embodiments, the semiconductor substrate101is semiconductive in nature. In some embodiments, the semiconductor substrate101is a semiconductor wafer (e.g., a silicon wafer) or a semiconductor-on-insulator (SOI) wafer (e.g., a silicon-on-insulator wafer). In some embodiments, the semiconductor substrate101is a silicon substrate.

In some embodiments, the semiconductor substrate101is defined with a peripheral region (not shown) and an array region101a. In some embodiments, the array region101ais at least partially surrounded by the peripheral region. In some embodiments, the peripheral region is adjacent to a periphery of the semiconductor substrate101, and the array region101ais adjacent to a central area of the semiconductor substrate101. In some embodiments, the array region101amay be used for fabricating electronic components such as capacitors, transistors or the like. In some embodiments, a boundary is disposed between the peripheral region and the array region101a.

In some embodiments, the semiconductor substrate101includes a recess101cextending into the semiconductor substrate and surrounding the active area101b. In some embodiments, the semiconductor substrate101includes an active area101bdisposed over or in the semiconductor substrate101. In some embodiments, the active area101bis a doped region in the semiconductor substrate101. In some embodiments, the active area101bextends horizontally over or under a top surface of the semiconductor substrate101. In some embodiments, a dimension of a top cross section of each active area101bcan be same as or different from each other.

In some embodiments, each of the active areas101bincludes a same type of dopant. In some embodiments, each of the active areas101bincludes a type of dopant that is different from the types of dopants included in other active areas101b. In some embodiments, each of the active areas101bhas a same conductive type. In some embodiments, the active area101bincludes N type dopants.

In some embodiments, a first dielectric layer102is disposed over the semiconductor substrate101. In some embodiments, the first dielectric layer102is disposed over the active area101bof the semiconductor substrate101. In some embodiments, the first dielectric layer102includes dielectric material such as oxide, silicon dioxide (SiO2) or the like. In some embodiments, the first dielectric layer102is an oxide film. In some embodiments, the first dielectric layer102may serve as a gate dielectric or a part of the gate dielectric subsequently formed over the active area101bof the semiconductor substrate101.

In some embodiments, a second dielectric layer103is disposed over the first dielectric layer102and the semiconductor substrate101. In some embodiments, the second dielectric layer103is disposed over the active area101bof the semiconductor substrate101. In some embodiments, the second dielectric layer103includes nitride, silicon nitride or the like. In some embodiments, the second dielectric layer103is a nitride film. In some embodiments, the second dielectric layer103may serve as a mask layer for protecting the semiconductor substrate101. In some embodiments as shown inFIG.2, the active area101bcovered by the first dielectric layer102and the second dielectric layer103is in a strip, elongated, rectangular or polygonal shape.

In some embodiments, the memory device100includes an isolation member104surrounding the active area101bof the semiconductor substrate101. In some embodiments, the active area101bis surrounded by the isolation member104, such that the active areas101bare separated and electrically isolated from each other by the isolation member104. In some embodiments, the active areas101bare arranged along a column or row direction. In some embodiments, the active area101bis entirely surrounded by the isolation member104.

In some embodiments, the isolation member104surrounds the first dielectric layer102and the second dielectric layer103disposed over the active area101bof the semiconductor substrate101. In some embodiments, the isolation member104is at least partially disposed within the recess101cof the semiconductor substrate101. In some embodiments, the isolation member104entirely surrounds the active area101bof the semiconductor substrate101.

In some embodiments, a top surface103aof the second dielectric layer103is substantially coplanar with a top surface104aof the isolation member104. In some embodiments, a top surface102aof the first dielectric layer102is substantially lower than the top surface104aof the isolation member104. In some embodiments, a depth of the isolation member104is substantially greater than or equal to a depth of the active area101b. In some embodiments, the isolation member104is a shallow trench isolation (STI) or is a part of the STI. In some embodiments, the isolation member104defines a boundary of the active area101b.

In some embodiments, the isolation member104is formed of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, the like or a combination thereof. In some embodiments, the first dielectric layer102and the isolation member104include a same material. In some embodiments, the first dielectric layer102is integral with the isolation member104.

FIG.3is a flow diagram illustrating a method S200of manufacturing a memory device100in accordance with some embodiments of the present disclosure, andFIGS.4to27are cross-sectional views of intermediate stages in formation of the memory device100in accordance with some embodiments of the present disclosure.

The stages shown inFIGS.4to27are also illustrated schematically in the flow diagram inFIG.3. In following discussion, the fabrication stages shown inFIGS.4to27are discussed in reference to process steps shown inFIG.3. The method S200includes a number of operations, and description and illustration are not deemed as a limitation to a sequence of the operations. The method S200includes a number of steps (S201, S202, S203, S204, S205, S206, S207, S208and S209).

Referring toFIGS.4to8, a semiconductor substrate101, a first dielectric layer102over the semiconductor substrate, a second dielectric layer103over the first dielectric layer, and a patterned photoresist layer105over the second dielectric layer are provided according to step S201inFIG.3.

In some embodiments as shown inFIG.4, the semiconductor substrate101including an active area101bdisposed over or in the semiconductor substrate101is provided. In some embodiments, the semiconductor substrate101includes semiconductive material. In some embodiments, the semiconductor substrate101is a silicon substrate. In some embodiments, the semiconductor substrate101is defined with a peripheral region (not shown) and an array region101aat least partially surrounded by the peripheral region. In some embodiments, the array region101ais adjacent to a central area of the semiconductor substrate101.

In some embodiments, the active area101bis a doped region in the semiconductor substrate101. In some embodiments, the active area101bextends horizontally over or under a top surface of the semiconductor substrate101. In some embodiments, each of the active areas101bincludes a same type of dopant. In some embodiments, each of the active areas101bincludes a type of dopant that is different from types of dopants included in other active areas101b. In some embodiments, each of the active areas101bhas a same conductive type. In some embodiments, the active area101bis formed by an ion implantation process or an ion doping process.

In some embodiments as shown inFIG.5, the first dielectric layer102is formed over the semiconductor substrate101. In some embodiments, the first dielectric layer102is formed over the active area101bof the semiconductor substrate101. In some embodiments, the first dielectric layer102is formed by oxidizing the semiconductor substrate101or a part of the semiconductor substrate101, deposition or any other suitable process. In some embodiments, the first dielectric layer102includes dielectric material such as oxide, silicon dioxide (SiO2) or the like. In some embodiments, the first dielectric layer102is an oxide film.

In some embodiments as shown inFIG.6, the second dielectric layer103is formed over the first dielectric layer102. In some embodiments, the second dielectric layer103is disposed over the active area101bof the semiconductor substrate101. In some embodiments, the second dielectric layer103includes nitride, silicon nitride or the like. In some embodiments, the second dielectric layer103is a nitride film. In some embodiments, the second dielectric layer103is formed by chemical vapor deposition (CVD), spin coating or any other suitable process.

In some embodiments as shown inFIGS.7and8, the patterned photoresist layer105is formed over the second dielectric layer103. In some embodiments, the patterned photoresist layer105is formed by disposing a photoresist material105aover the second dielectric layer103as shown inFIG.7, and patterning the photoresist material105aas shown inFIG.8. The patterning of the photoresist material105aincludes removing portions of the photoresist material105aby etching or any other suitable process. As shown inFIG.8, the second dielectric layer103is at least partially exposed through the patterned photoresist layer105.

Referring toFIGS.9and10, first portions of the semiconductor substrate101, the first dielectric layer102and the second dielectric layer103exposed through the patterned photoresist layer105are removed to form a trench106according to step S202inFIG.3.FIG.10is a top view ofFIG.9.FIG.9is the cross-sectional side view along a line BB inFIG.10. The trench106extends through the first dielectric layer102and the second dielectric layer103. In some embodiments, the first portions of the semiconductor substrate101, the first dielectric layer102and the second dielectric layer103exposed through the patterned photoresist layer105are removed by etching or any other suitable process. In some embodiments, a strip pattern as seen in a top view ofFIG.9is formed after the formation of the trench106as shown inFIG.10.

Referring toFIGS.11and12, the patterned photoresist layer105is removed according to step S203inFIG.3.FIG.12is a top view ofFIG.11.FIG.11is the cross-sectional side view along a line CC inFIG.12. In some embodiments, the patterned photoresist layer105is removed by etching, stripping or any other suitable process. As shown inFIG.12, the second dielectric layer103is exposed after the removal of the patterned photoresist layer105.

Referring toFIGS.13to15, an isolation member104is disposed within the trench106according to step S204inFIG.3.FIG.15is a top view ofFIG.14.FIG.14is the cross-sectional side view along a line DD inFIG.15. In some embodiments, the isolation member104is formed by disposing an isolation material107over the semiconductor substrate101and the second dielectric layer103as shown inFIG.13, and then removing portions of the isolation material107to form the isolation member104as shown inFIG.14. In some embodiments, the trench106is filled by the isolation material107. In some embodiments, the portions of the isolation material107are removed by planarization, etching or any other suitable process. In some embodiments, the isolation member104surrounds the first dielectric layer102and the second dielectric layer103disposed over the active area101bof the semiconductor substrate101. In some embodiments, the isolation member104includes oxide.

Referring toFIGS.16and17, a sacrificial pillar108is disposed over the second dielectric layer103according to step S205inFIG.3.FIG.17is a top view ofFIG.16.FIG.16is the cross-sectional side view along a line EE inFIG.17. The sacrificial pillar108is formed by deposition or any other suitable process. In some embodiments, the sacrificial pillar108is in contact with the isolation member104and the second dielectric layer103. In some embodiments, the sacrificial pillar108includes nitride. In some embodiments, a cross-section of the sacrificial pillar108is in a circular shape.

Referring toFIGS.18and19, a first spacer109surrounding the sacrificial pillar108is disposed according to step S206inFIG.3.FIG.19is a top view ofFIG.18.FIG.18is the cross-sectional side view along a line FF inFIG.19. The first spacer109is formed over the isolation member104and the second dielectric layer103. In some embodiments, the sacrificial pillar108is surrounded by the first spacer109. In some embodiments, the first spacer109is in contact with an entire outer surface of the sacrificial pillar108. In some embodiments, the first spacer109is hollow. In some embodiments, the sacrificial pillar108is formed over the second dielectric layer103prior to the formation of the first spacer109. In some embodiments, the first spacer109includes dielectric material such as oxide, nitride, oxynitride or the like.

Referring toFIGS.20and21, the sacrificial pillar108is removed according to step S207inFIG.3.FIG.21is a top view ofFIG.20.FIG.20is the cross-sectional side view along a line GG inFIG.21. In some embodiments, the sacrificial pillar108is removed by etching or any other suitable process. In some embodiments, the sacrificial pillar108is removed after the formation of the first spacer109.

Referring toFIGS.22and23, a second spacer110surrounding the first spacer109is disposed according to step S208inFIG.3.FIG.23is a top view ofFIG.22.FIG.22is the cross-sectional side view along a line HH inFIG.23. In some embodiments, the second spacer110is formed by deposition or any other suitable process. In some embodiments, the sacrificial pillar108is removed prior to the disposing of the second spacer110. In some embodiments, the first spacer109and the second spacer110include a same dielectric material. In some embodiments, the first spacer109and the second spacer110include dielectric material such as oxide, nitride, oxynitride or the like.

In some embodiments, the second spacer110is disposed by forming a first annular member110ain contact with an outer surface109aof the first spacer109and forming a second annular member110bin contact with an inner surface109bof the first spacer109. In some embodiments, the first annular member110ais a second hollow spacer, and the second annular member110bis a third hollow spacer. In some embodiments, the first annular member110asurrounds the first spacer109, and the second annular member110bis surrounded by the first spacer109. The first annular member110asurrounds the first spacer109and the second annular member110b. In some embodiments, the formation of the first annular member110aand the formation of the second annular member110bare performed separately or simultaneously.

In some embodiments, the disposing of the second spacer110includes forming an opening111surrounded by the first spacer109and the second spacer110. After the disposing of the second spacer110, at least a portion of the second dielectric layer103is exposed through the second spacer110and are disposed within the opening111from a top view as shown inFIG.23.

Referring toFIGS.24and25, second portions of the first dielectric layer102and the second dielectric layer103exposed through the second spacer110are removed according to step S209inFIG.3.FIG.24is a top view illustrating the removal of portions of the first dielectric layer102and the second dielectric layer103that are exposed through the second spacer110and surrounded by the second annular member110bfrom the top view, andFIG.25is a top view illustrating the removal of portions of the first dielectric layer102and the second dielectric layer103that are exposed through the second spacer110and outside the first annular member110afrom the top view.

In some embodiments, the removal of the second portions of the first dielectric layer102and the second dielectric layer103exposed through the second spacer110includes removing the portions of the first dielectric layer102and the second dielectric layer103that are within the second spacer110from the top view as shown inFIG.24, and removing the portions of the first dielectric layer102and the second dielectric layer103that are outside the second spacer110from the top view as shown inFIG.25.

In some embodiments, the removal of the portions of the first dielectric layer102and the second dielectric layer103that are within the second spacer110from the top view as shown inFIG.24is performed before or after the removal of the portions of the first dielectric layer102and the second dielectric layer103that are outside the second spacer from the top view as shown inFIG.25. In some embodiments, the removal of the portions of the first dielectric layer102and the second dielectric layer103that are within the second spacer110from the top view as shown inFIG.24is performed simultaneously with the removal of the portions of the first dielectric layer102and the second dielectric layer103that are outside the second spacer from the top view as shown inFIG.25.

In some embodiments, after the removal of the portions of the first dielectric layer102and the second dielectric layer103that are within the second spacer110from the top view as shown inFIG.24is performed before or after the removal of the portions of the first dielectric layer102and the second dielectric layer103that are outside the second spacer from the top view as shown inFIG.25, at least a portion of the semiconductor substrate101is exposed through the second dielectric layer103as shown inFIG.25.

In some embodiments, after the removal of the second portions of the first dielectric layer102and the second dielectric layer103exposed through the second spacer110, the first spacer109and the second spacer110are removed as shown inFIGS.26and27.FIG.27is a top view ofFIG.26. In some embodiments, the first spacer109and the second spacer110are removed by etching, stripping or any other suitable process. In some embodiments, the removal of the first spacer109and the removal of the second spacer110are performed separately or simultaneously. In some embodiments, the removal of the first spacer109is performed before or after the removal of the second spacer110.

In some embodiments, the portion of the semiconductor substrate101exposed through the second dielectric layer103as shown inFIG.25is removed, and then the isolation member104is also disposed in the hole112as shown inFIG.27. In some embodiments, the isolation member104fills the hole112. In some embodiments, the removal of the portion of the semiconductor substrate101exposed through the second dielectric layer103is performed before or after the removal of the first spacer109and the removal of the second spacer110. In some embodiments, a memory device100as shown inFIGS.1and2is formed as shown inFIGS.26and27.

In some embodiments, the second dielectric layer103is removed after the filling of the hole112by the isolation member104. In some embodiments, after the removal of the second dielectric layer103, the isolation member104and the first dielectric layer102are planarized. In some embodiments, after the planarization, implantation of dopants over the active area101bis performed.

In an aspect of the present disclosure, a method of manufacturing a memory device is provided. The method includes steps of providing a semiconductor substrate including an active area disposed over or in the semiconductor substrate, a first dielectric layer over the semiconductor substrate, a second dielectric layer over the first dielectric layer, and a patterned photoresist layer over the second dielectric layer; removing first portions of the semiconductor substrate, the first dielectric layer and the second dielectric layer exposed through the patterned photoresist layer to form a trench; removing the patterned photoresist layer; disposing an isolation member within the trench; disposing a sacrificial pillar over the second dielectric layer; disposing a first spacer surrounding the sacrificial pillar; removing the sacrificial pillar; disposing a second spacer surrounding the first spacer; and removing second portions of the first dielectric layer and the second dielectric layer exposed through the second spacer.

In another aspect of the present disclosure, a method of manufacturing a memory device is provided. The method includes steps of providing a semiconductor substrate including an active area disposed over or in the semiconductor substrate; forming an oxide film over the semiconductor substrate; forming a nitride film over the oxide film; form a trench extending through the oxide film and the nitride film; forming a first hollow spacer over the nitride film; forming a second hollow spacer surrounding the first hollow spacer; forming a third hollow spacer surrounded by the first hollow spacer; and removing portions of the oxide film and the nitride film exposed through the second hollow spacer and the third hollow spacer.

In another aspect of the present disclosure, a memory device is provided. The memory device includes a semiconductor substrate defined with an active area over or in the semiconductor substrate and including a recess surrounding the active area; a first dielectric layer disposed over the active area of the semiconductor substrate; a second dielectric layer disposed over the first dielectric layer; and an isolation member disposed within the recess and entirely surrounding the active area.

In conclusion, because the active area of the semiconductor substrate is defined by disposing several annular spacers over the semiconductor substrate and removing predetermined portions of the semiconductor substrate exposed through the annular spacers, a size of the active area can be maintained with minimal or no decrease during the removal. Therefore, a process window for subsequent processes over the active area is not further reduced. As a result, misalignment or leakage among the memory cells in the memory device can be prevented or minimized, and an overall performance the memory device can be improved.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein, may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods and steps.