Patent ID: 12199170

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Still further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within +/−10% of the number described, unless otherwise specified. For example, the term “about 5 nm” encompasses the dimension range from 4.5 nm to 5.5 nm.

The present disclosure is generally related to semiconductor devices and fabrication methods, and more particularly to fabricating gate-all-around field effect transistor (GAA FET) devices with a semiconductor seed layer deposited on an inner spacer layer, which facilitates later-on formations of source/drain (S/D) epitaxial features.

A GAA FET device is a type of multi-gate device. Multi-gate devices include those transistors whose gate structures are formed on at least two-sides of a channel region. These multi-gate devices may include a p-type metal-oxide-semiconductor device or an n-type metal-oxide-semiconductor device. Specific examples may be presented and referred to herein as FINFET, on account of their fin-like structure. As a type of multi-gate device, a GAA FET device includes any FET device that has its gate structure, or portion thereof, formed on 4-sides of a channel region (e.g., surrounding a portion of a channel region). Devices presented herein also include embodiments that have channel regions disposed in nanowire channel(s), bar-shaped channel(s), and/or other suitable channel configuration. Presented herein are embodiments of devices that may have one or more channel regions (e.g., nanowires) associated with a single, contiguous gate structure. However, one of ordinary skill would recognize that the teaching can apply to a single channel (e.g., single nanowire) or any number of channels. One of ordinary skill may recognize other examples of semiconductor devices that may benefit from aspects of the present disclosure.

Illustrated inFIGS.1A and1Bis a method100of semiconductor fabrication including fabrication of multi-gate devices. It is understood that additional operations can be provided before, during, and after processes shown byFIGS.1A and1B, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable. As used herein, the term “multi-gate device” is used to describe a device (e.g., a semiconductor transistor) that has at least some gate material disposed on multiple sides of at least one channel of the device. In some examples, the multi-gate device may be referred to as a GAA FET device or a nanosheet device having gate material disposed on at least four sides of at least one channel of the device. The channel region may be referred to as a “nanowire,” which as used herein includes channel regions of various geometries (e.g., cylindrical, bar-shaped) and various dimensions.

The method100is described below with references toFIGS.1A and1B, in conjunction withFIGS.2-22.FIGS.2,3,4,5,6,7,8,9,10A,19,20,21, and22are perspective views of an embodiment of a GAA FET device according to various stages of the method100ofFIGS.1A and1B.FIGS.10B,11,12,13,14,15,16,17, and18are corresponding cross-sectional views of an embodiment of the GAA FET device along a cut (e.g., cut X1-X1inFIG.10A), which is along a lengthwise direction of the channel and perpendicular to a top surface of the substrate.

Referring toFIGS.1A and2, the method100begins at operation102where a substrate10is provided. The substrate10may include various regions that have been suitably doped with impurities (e.g., p-type or n-type conductivity). In some embodiments, impurity ions (dopants)12are implanted into a silicon substrate to form a well region. The ion implantation is performed to prevent a punch-through effect. The dopants12are, for example boron (B) for an n-type FinFET or phosphorus (P) for a p-type FinFET.

In some embodiments, the substrate10includes a single crystalline semiconductor layer on at least its surface portion. The substrate10may comprise a single crystalline semiconductor material such as, but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb and InP. In the illustrated embodiment, the substrate10is made of Si.

The substrate10may include in its surface region, one or more buffer layers (not shown). The buffer layers can serve to gradually change the lattice constant from that of the substrate to that of the source/drain regions. The buffer layers may be formed from epitaxially grown single crystalline semiconductor materials such as, but not limited to Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In a particular embodiment, the substrate10comprises silicon germanium (SiGe) buffer layers epitaxially grown on bulk silicon. The germanium concentration of the SiGe buffer layers may increase from 30 atomic % germanium for the bottom-most buffer layer to 70 atomic % germanium for the topmost buffer layer.

Referring toFIGS.1A and3, the method100then proceeds to operation104where stacked semiconductor layers are formed over the substrate10. The stacked semiconductor layers include first semiconductor layers20and second semiconductor layers25. Further, a mask layer15is formed over the stacked layers. By way of example, the stacked semiconductor layers may be epitaxially grown by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and/or other suitable epitaxial growth processes.

The first semiconductor layers20and the second semiconductor layers25are made of materials having different lattice constants, and may include one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb or InP. In some embodiments, the first semiconductor layers20and the second semiconductor layers25are made of Si, a Si compound, SiGe, Ge or a Ge compound. However, other embodiments are possible including those that provide for a first composition and a second composition having different oxidation rates and/or etch selectivity. In at least some examples, the first semiconductor layers20include an epitaxially grown SiGe layer and the second semiconductor layers25include an epitaxially grown Si layer. The Si oxidation rate of the second semiconductor layers25is less than the SiGe oxidation rate of the first semiconductor layers20. In one example, the first semiconductor layers20are Si1-xGex, where x is less than about 0.3, such as in a range from about 0.15 to about 0.25. In some embodiments, the first semiconductor layers20and the second semiconductor layers25are substantially dopant-free (i.e., having an extrinsic dopant concentration from about 0 cm−3to about 1×1017cm−3), where for example, no intentional doping is performed during the epitaxial growth process.

The second semiconductor layers25or portions thereof may form nanosheet channel(s) of the GAA FET device. The term nanosheet is used herein to designate any material portion with nanoscale, or even microscale dimensions, and having an elongate shape, regardless of the cross-sectional shape of this portion. Thus, this term designates both circular and substantially circular cross-section elongate material portions, and beam or bar-shaped material portions including for example a cylindrical in shape or substantially rectangular cross-section. The use of the second semiconductor layers25to define a channel or channels of a device is further discussed below. Accordingly, the second semiconductor layers25are also referred to as the channel layers25, while the first semiconductor layers20are also referred to as the sacrificial layers20.

InFIG.3, three layers of the first semiconductor layer20and three layers of the second semiconductor layer25are disposed. However, the number of the layers are not limited to three, and may be as small as one (each layer) and in some embodiments, 2-10 layers of each of the first and second semiconductor layers are formed. By adjusting the numbers of the stacked layers, a driving current of the GAA FET device can be adjusted.

The first semiconductor layers20and the second semiconductor layers25are epitaxially formed over the substrate10. The thickness of the first semiconductor layers20may be equal to or greater than that of the second semiconductor layers25, such as in a range from about 3 nm to about 50 nm in some embodiments, or in a range from about 5 nm to about 15 nm in other embodiments. The thickness of the second semiconductor layers25is in a range from about 3 nm to about 30 nm in some embodiments, or in a range from about 5 nm to about 15 nm in other embodiments. The thickness of each of the first semiconductor layers20may be the same or may vary. In some embodiments, the bottommost semiconductor layer20(the closest layer to the substrate10) is thicker than the upper semiconductor layers. The thickness of the bottommost semiconductor layer is in a range from about 10 nm to about 50 nm in some embodiments, or in a range from 20 nm to 40 nm in other embodiments.

In some embodiments, the mask layer15includes a first mask layer15A and a second mask layer15B. The first mask layer15A is a pad oxide layer made of silicon oxide, which can be formed by a thermal oxidation process. The second mask layer15B is made of silicon nitride (SiN), which is formed by chemical vapor deposition (CVD), including low pressure CVD (LPCVD) and plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable process. The mask layer15is patterned into a mask pattern by using patterning operations including photo-lithography and etching.

Referring toFIGS.1A and4, the method100then proceeds to operation106where fin elements (also referred to as fins)30are formed by patterning the stacked semiconductor layers20and25by using the patterned mask layer15. With reference to the example ofFIG.4, in an embodiment of operation106, a plurality of fins30extending from the substrate10are formed extending in the X direction. In various embodiments, each of the fins30includes upper portions constituted by the stacked semiconductor layers20and25, and well portions11formed from the substrate10. The width W1of the upper portion of the fin structure along the Y direction is in a range from about 10 nm to about 40 nm in some embodiments, or in a range from about 20 nm to about 30 nm in other embodiments. The height H1along the Z direction of the fin structure is in a range from about 100 nm to about 200 nm in some embodiments.

The fins30may be fabricated using suitable processes including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the fins30by etching initial stacked semiconductor layers20and25. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and/or other suitable processes.

InFIG.4, two fins30are arranged in the Y direction. But the number of the fins30is not limited to and may be as small as one or three or more. In some embodiments, one or more dummy fin structures are formed on both sides of the fins30to improve pattern fidelity in the patterning operations.

Referring toFIGS.1A,5, and6, method100proceeds to operation108by forming a shallow trench isolation (STI) feature interposing the fins30. By way of example, an insulating material layer41including one or more layers of insulating material is formed over the substrate so that the fin structures are fully embedded in the insulating material layer41. The insulating material for the insulating material layer41may include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-K dielectric material, formed by LPCVD (low pressure chemical vapor deposition), plasma-CVD or flowable CVD. An anneal operation may be performed after the formation of the insulating material layer41. Then, a planarization operation, such as a chemical mechanical polishing (CMP) method and/or an etch-back method, is performed such that the upper surface of the topmost second semiconductor layer25is exposed from the insulating material layer41as shown inFIG.5.

In some embodiments, a liner layer35is formed over the structure ofFIG.4before forming the insulating material layer41, as shownFIG.5. In some embodiments, the liner layer35is made of SiN or a silicon nitride-based material (e.g., SiON, SiCN or SiOCN). Then, as shown inFIG.6, the insulating material layer41is recessed to form an isolation feature40so that the upper portions of the fins30are exposed. With this operation, the fins30are electrically separated from each other by the isolation feature40, which is also referred to as a shallow trench isolation (STI)40.

Referring toFIGS.1A,7, and8, method100proceeds to operation110where sacrificial layers/features are formed and in particular, a dummy gate structure. While the present discussion is directed to a replacement gate process whereby a dummy gate structure is formed and subsequently replaced, other configurations may be possible. With reference toFIG.7, after the STI40is formed, a sacrificial gate dielectric layer52is formed. The sacrificial gate dielectric layer52includes one or more layers of insulating material, such as a silicon oxide-based material. In one embodiment, silicon oxide formed by CVD is used. The thickness of the sacrificial gate dielectric layer52is in a range from about 1 nm to about 5 nm in some embodiments.

FIG.8illustrates a structure after a sacrificial gate structure50is formed over the exposed fins30. The sacrificial gate structure50includes the sacrificial gate dielectric layer52and a sacrificial gate electrode54. The sacrificial gate structure50is formed over a portion of the fins30which is to be a channel region. The sacrificial gate structure defines the channel region of the GAA FET device.

The sacrificial gate structure50is formed by first blanket depositing the sacrificial gate dielectric layer52over the fins30. A sacrificial gate electrode layer is then blanket deposited on the sacrificial gate dielectric layer52and over the fins30, such that the fins30are fully embedded in the sacrificial gate electrode layer. The sacrificial gate electrode layer includes silicon such as polycrystalline silicon or amorphous silicon. The thickness of the sacrificial gate electrode layer is in a range from about 100 nm to about 200 nm in some embodiments. In some embodiments, the sacrificial gate electrode layer is subjected to a planarization operation. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD, including LPCVD and PECVD, PVD, ALD, or other suitable process. Subsequently, a mask layer is formed over the sacrificial gate electrode layer. The mask layer includes a pad SiN layer56and a silicon oxide mask layer58.

Next, a patterning operation is performed on the mask layer and sacrificial gate electrode layer is patterned into the sacrificial gate structure50, as shown inFIG.8. The sacrificial gate structure includes the sacrificial gate dielectric layer52, the sacrificial gate electrode54(e.g., poly silicon), the pad SiN layer56and the silicon oxide mask layer58. By patterning the sacrificial gate structure, the stacked semiconductor layers20and25are partially exposed on opposite sides of the sacrificial gate structure50, thereby defining source/drain (S/D) regions. In this disclosure, a source and a drain are interchangeably used and the structures thereof are substantially the same. InFIG.8, one sacrificial gate structure50is formed, but the number of the sacrificial gate structures50is not limited to one, two, or more sacrificial gate structures, which are arranged in the X direction in some embodiments. In certain embodiments, one or more dummy sacrificial gate structures are formed on both sides of the sacrificial gate structures to improve pattern fidelity.

Referring toFIGS.1A and9, method100then proceeds to operation112where gate sidewall spacers are formed. After the sacrificial gate structure50is formed, a blanket layer53of an insulating material for forming gate sidewall spacers55(FIG.10A) is conformally deposited by using CVD or other suitable methods. The blanket layer53is deposited in a conformal manner so that it is formed to have substantially equal thicknesses on vertical surfaces, such as the sidewalls, horizontal surfaces, and the top of the sacrificial gate structure. In some embodiments, the blanket layer53is deposited to a thickness in a range from about 2 nm to about 8 nm. In one embodiment, the insulating material of the blanket layer53is a silicon nitride-based material, such as SiN, SiON, SiOCN or SiCN and combinations thereof.

After the blanket layer53is formed, anisotropic etching is performed on the blanket layer53using, for example, reactive ion etching (RIE). During the anisotropic etching process, most of the insulating material is removed from horizontal surfaces, leaving the gate sidewall spacers55on the vertical surfaces such as the sidewalls of the sacrificial gate structure50and the sidewalls of the exposed fins30, as shown inFIG.10A. The mask layer58may be exposed from the gate sidewall spacers55. In some embodiments, isotropic etching may be subsequently performed to remove the insulating material from the upper portions of the S/D region of the exposed fins30.

Still referring toFIG.10A, in conjunction withFIG.10B, which is the cross sectional view corresponding to area A1and line X1-X1ofFIG.10A, method100proceeds to operation114where the stacked structure of the first semiconductor layers20and the second semiconductor layers25is etched down at the S/D regions, by using one or more lithography and etching operations, thereby forming an S/D trench60. In some embodiments, fins30in S/D regions are recessed down below the upper surface of the STI40by using dry etching and/or wet etching. In the illustrated embodiment, the substrate10(or the bottom part11of the fin structure) is also partially etched. At this stage, end portions (also referred to as lateral ends) of the stacked layers of the first semiconductor layers20and the second semiconductor layers25are exposed in the S/D trench60.

Referring toFIGS.1A and11, method100proceeds to operation116where the first semiconductor layers20are laterally etched in the X direction within the S/D trench60, thereby forming cavities62. The width W2of the cavities62is in a range from about 3 nm to about 10 nm in some embodiments. When the first semiconductor layers20are Ge or SiGe and the second semiconductor layers25are Si, the first semiconductor layers20can be selectively etched by using a wet etchant such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solutions. In some embodiments, operation116also trims end portions of the second semiconductor layers25to reduce a thickness of the end portions of the second semiconductor layers25and expand a height H2of the cavities62. As will be discussed below, expanding the height H2of the cavities62provides extra space to accommodate a seed layer to be deposited therein. After the trimming, a ratio between the height H2of the cavities62and thickness H3of the first semiconductor layers20may range from about 1.1:1 to about 1.4:1. If the ratio is less than 1.1:1, the seed layer subsequently to be formed in the cavities62may not be able to provide sufficient surface area to facilitate epitaxial growth of S/D features. If the ratio is larger than 1.4:1, the end portions of the second semiconductor layers25may become too thin, which in turn weakens current driving performance of the GAA FET device. In some embodiments, H2is in a range from about 6 nm to about 15 nm.

Referring toFIGS.1A and12, method100proceeds to operation118where a first liner layer64is formed on the end portions of the first semiconductor layers20and the second semiconductor layers25. By forming the first liner layer64, the size of cavities62is reduced but not completed filled up, due to the cavity height expanding in previous operation116, which reserves space for the subsequent deposition of a seed layer. The first liner layer64also wraps over the end portions of the second semiconductor layers25. As will be shown in further details below, the first liner layer64is etched and formed into inner spacers. Therefore, the first liner layer64is also referred to as an inner spacer layer64. In some embodiments, the first liner layer64includes a dielectric material, such as SiN, SiOC, SiOCN, SiCN, SiO2, KN1, and/or other suitable material, such as a low-k dielectric material with a dielectric constant less than about 3.9. In some embodiments, the first liner layer64is a semiconductor layer, which may include SiGe or Ge. In various embodiments, an atomic % of Ge in the first liner layer64is larger than that in the first semiconductor layer20. For example, the first semiconductor layers20may include Si1-xGex, where x is less than about 0.3, such as in a range from about 0.15 to about 0.25; while the first liner layer64may include Si1-yGey, where y is larger than about 0.3, such as in a range from about 0.35 to about 0.4. The variation of the atomic % of Ge provides a different oxidation rates between the first liner layer64and the first semiconductor layer20, where the benefit will become evident in a later section of the present disclosure. In some embodiments, the first liner layer64is conformally epitaxially grown in the S/D trench60by ALD or any other suitable method. The first liner layer64may have a thickness in a range from about 0.5 nm to about 3.0 nm, such as from about 1.0 nm to about 2.0 nm in some examples.

Referring toFIGS.1B and13, method100proceeds to operation120where a second liner layer66is formed on the first liner layer64in the S/D trench60. The second liner layer66may fill up the cavities62. In various embodiments, the second liner layer66is a semiconductor layer. For example, the second liner layer66may be an undoped silicon layer. In some embodiments, the second liner layer66includes amorphous silicon. As will be shown in further details below, the second liner layer66is etched and formed into seeds to facilitate later-on S/D epitaxial growth. Therefore, the second liner layer66is also referred to as a seed layer66or a semiconductor seed layer66. In some embodiments, the second liner layer66is conformally epitaxially grown in the S/D trench60by ALD or any other suitable method. The second liner layer66may have a thickness in a range from about 0.5 nm to about 3.0 nm, such as from about 1.0 nm to about 2.0 nm in some examples.

Referring toFIGS.1B,14, and15, method100proceeds to operation122to partially remove the first liner layer64and the second liner layer66from the S/D trench60to expose end portions of the second semiconductor layers25. Operation122may include an etching process. By this etching, the first liner layer64and the second liner layer66remain substantially within the cavity62, because of a small volume of the cavity. Generally, plasma dry etching etches a layer in wide and flat areas faster than a layer in concave (e.g., holes, grooves and/or slits) portions. Thus, the first liner layer64and the second liner layer66can remain inside the cavities62. In some embodiments, since the first liner layer64and the second liner layer66are made of different materials, operation122may include more than one etching process with different etchants targeting at different materials. For example, operation122first partially removes the second liner layer66in a first etching process, while the first liner layer64substantially remains on the second semiconductor layers25, as shown inFIG.14. Subsequently, operation122partially removes the first liner layer64in a second etching process to expose lateral ends of the second semiconductor layers25, as shown inFIG.15.

Referring toFIGS.1B and16, if the first liner layer64is a semiconductor layer (e.g., SiGe or Ge), method100may optionally proceed to operation124to oxidize the first liner layer64into a dielectric oxide layer. In some embodiments, method100may proceed to operation124prior to operation122. In some embodiments, the first liner layer64is a SiGe or Ge layer with atomic % of Ge larger than that of the other semiconductor layers in the S/D trench60, such as the second liner layer66, the first semiconductor layers20, and the second semiconductor layers25. For example, the first semiconductor layers20may include Si1-xGex, where x is less than about 0.3, such as in a range from about 0.15 to about 0.25; while the first liner layer64may include Si1-yGey, where y is larger than about 0.3, such as in a range from about 0.35 to about 0.4, and the second liner layer66and the second semiconductor layer25may include Si. The higher atomic % of Ge provides a faster oxidation rates for the first liner layer64, such that under certain oxidation environment the first liner layer64is oxidized while other semiconductor layers in the S/D trench60remain substantially unchanged. In the illustrated embodiment, the first liner layer64is oxidized by O3clean and converted to a silicon germanium oxide (SiGeO) layer. Thereafter the second liner layer66may have a dielectric constant higher than that of the oxidized first liner layer64.

After operation124, the first liner layer64is denoted as inner spacer layer64and the second liner layer66is denoted as seed layer66for the sake of clarity and simplicity. As shown inFIG.16, the inner spacer layer64surrounds (or sandwiches) lateral ends of the second semiconductor layers25and surrounds (or sandwiches) the seed layer66. In other words, the seed layer66is embedded in the inner spacer layer64. In various embodiments, the inner spacer layer64may have a width W2ranging from about 3 nm to about 10 nm and a height H2ranging from about 6 nm to about 15 nm, the seed layer66may have a width W4ranging from about 1 nm to about 3 nm and a height H4ranging from about 3 nm to about 12 nm. In the illustrated embodiment, the bottom portion of the seed layer66(close to the substrate10) has a larger width than the top portion of the seed layer66. In the illustrated embodiment, end portions of the inner spacer layer64and the seed layer66are both under the gate sidewall spacers55and offset from sidewalls of the sacrificial gate structure50. However, depending on depth of the cavities62and thickness of the gate sidewall spacers55, in some embodiments end portions of the inner spacer layer64may extend under the sacrificial gate structure50(i.e., directly under the sacrificial gate electrode54) while end portions of the seed layer66are offset from sidewalls of the sacrificial gate structure50; in some alternative embodiments, end portions of the inner spacer layer64and the seed layer66may both extend under the sacrificial gate structure50(i.e., directly under the sacrificial gate electrode54).

Referring toFIGS.1B,17, and18, method100proceeds to operation126where an S/D epitaxial feature68is formed in the S/D trench60. In an embodiment, forming the S/D epitaxial feature68includes epitaxially growing one or more semiconductor layers (e.g., layers68aand68b) by an MBE process, a chemical vapor deposition process, and/or other suitable epitaxial growth processes. In a further embodiment, the S/D epitaxial feature68is in-situ or ex-situ doped with an n-type dopant or a p-type dopant. For example, in some embodiments, the S/D epitaxial feature68includes silicon-germanium (SiGe) doped with boron for forming S/D features for a p-type FET. In some embodiments, the S/D epitaxial feature68includes silicon doped with phosphorous for forming S/D features for an n-type FET. In the illustrated embodiment, operation126first deposits semiconductor layer68ain the S/D trench60and then deposits semiconductor layer68bon the semiconductor layer68a. In some embodiments, the semiconductor layers68aand68bdiffer in amount of dopant included therein. In some examples, the amount of dopant included in the semiconductor layer68ais less than that included in the semiconductor layer68bdue to the nature of the doping process. The semiconductor layer68ais selectively grown on different semiconductor surfaces exposed in the S/D trench60, such as the top surface of the substrate10, the lateral ends of the second semiconductor layers25, as well as sidewalls of the seed layer66. The seed layer66effectively increases available semiconductor surfaces in the S/D trench60for the epitaxial growth. Benefiting from a larger epitaxial growing area, the portions of the semiconductor layer68agrown directly from different semiconductor surfaces merge better and provide a less wavy surface for the subsequent epitaxial growth of the semiconductor layer68b, where the resultant semiconductor layer68bgrown directly from the semiconductor layer68ais substantially free of voids.

Referring toFIGS.1B and19, the method100then proceeds to operation128where an inter-layer dielectric (ILD) layer95is formed on the substrate. In some embodiments, a contact etch stop layer (CESL)90is also formed prior to forming the ILD layer95. In some examples, the CESL90includes a silicon nitride layer, silicon oxide layer, a silicon oxynitride layer, and/or other materials known in the art. The CESL90may be formed by plasma-enhanced chemical vapor deposition (PECVD) process and/or other suitable deposition or oxidation processes. In some embodiments, the ILD layer95includes materials such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. The ILD layer95may be deposited by a PECVD process or other suitable deposition technique. In some embodiments, after formation of the ILD layer95, the semiconductor device as shown inFIG.19may be subject to a high thermal budget process to anneal the ILD layer95. In some examples, after depositing the ILD layer95, a planarization process may be performed to remove excessive dielectric materials. For example, a planarization process includes a chemical mechanical planarization (CMP) process which removes portions of the ILD layer95(and CESL layer, if present) overlying the sacrificial gate structure50and exposes the sacrificial gate electrode54.

Referring toFIGS.1B and20, method100then proceeds to operation130by removing the sacrificial gate structure50to form a gate trench92in the channel region. A final gate structure (e.g., including a high-K dielectric layer and metal gate electrode) may be subsequently formed in the gate trench92, as will be described below. Operation130may include one or more etching processes that are selective to the material in the sacrificial gate structure50. For example, the removal of the sacrificial gate structure50may be performed using a selective etch process such as a selective wet etch, a selective dry etch, or a combination thereof. The stacked semiconductor layers20and25of the fin30are exposed in the gate trench92.

Referring toFIGS.1B and21, method100then proceeds to operation132by removing the first semiconductor layers20from the fins30in the gate trench92thereby forming nanowires of the second semiconductor layers25. In an embodiment, the first semiconductor layers20are removed by a selective wet etching process. In an embodiment, the first semiconductor layers20are SiGe and the second semiconductor layers25are silicon allowing for the selective removal of the first semiconductor layers20using a wet etchant such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution. In some embodiments, the selective wet etching includes an APM etch (e.g., ammonia hydroxide-hydrogen peroxide-water mixture). In the present embodiment, since the inner spacer layer64(e.g., SiGeO) is formed, the etching of the first semiconductor layers20(e.g., SiGe) stops at the inner spacer layer64. Since the etching of the first semiconductor layers20stop at the inner spacer layer64, it is possible to prevent the gate electrode and the S/D epitaxial features from contacting or bridging.

Referring toFIGS.1B and22, method100then proceeds to operation134where a gate structure93is formed. The gate structure93may be a high-K/metal gate (HK MG) stack, however other compositions are possible. In some embodiments, after the multi-channels provided by the plurality of nanowires (now having gaps therebetween due to the removing of the first semiconductor layers20) of the second semiconductor layers25are formed, a gate dielectric layer94is formed around each channel layers (nanowires of the second semiconductor layers25), and a gate electrode layer96is formed on the gate dielectric layer94.

In certain embodiments, the gate dielectric layer94includes one or more layers of a dielectric material, such as silicon oxide, silicon nitride, or high-k dielectric material, other suitable dielectric material, and/or combinations thereof. Examples of high-k dielectric material include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, other suitable high-k dielectric materials, and/or combinations thereof. In some embodiments, the gate dielectric layer94includes an interfacial layer formed between the channel layers and the dielectric material. The gate dielectric layer94may be formed by CVD, ALD or any suitable method. In one embodiment, the gate dielectric layer94is formed using a highly conformal deposition process such as ALD in order to ensure the formation of a gate dielectric layer having a uniform thickness around each channel layers. The thickness of the gate dielectric layer94is in a range from about 1 nm to about 6 nm in one embodiment.

The gate electrode96is formed on the gate dielectric layer94to surround each channel layers. The gate electrode96includes one or more layers of conductive material, such as poly silicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof. The gate electrode96may be formed by CVD, ALD, electro-plating, or other suitable method. The gate electrode96is also deposited over the upper surface of the ILD layer95. The gate dielectric layer and the gate electrode layer formed over the ILD layer95are then planarized by using, for example, CMP, until the top surface of the ILD layer95is revealed.

After the planarization operation, the gate electrode96is recessed and a cap insulating layer98is formed over the recessed gate electrode96. The cap insulating layer98includes one or more layers of a silicon nitride-based material, such as SiN. The cap insulating layer98can be formed by depositing an insulating material followed by a planarization operation.

In certain embodiments of the present disclosure, one or more work function adjustment layers (not shown) are interposed between the gate dielectric layer94and the gate electrode96. The work function adjustment layers are made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of these materials. For the n-channel FET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi and TaSi is used as the work function adjustment layer, and for the p-channel FET, one or more of TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC and Co is used as the work function adjustment layer. The work function adjustment layer may be formed by ALD, PVD, CVD, e-beam evaporation, or other suitable process. Further, the work function adjustment layer may be formed separately for the n-channel FET and the p-channel FET which may use different metal layers.

The semiconductor device as shown inFIG.22may undergo further processing to form various features and regions known in the art. For example, subsequent processing may form contact openings, contact metal, as well as various contacts/vias/lines and multilayers interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate, configured to connect the various features to form a functional circuit that may include one or more multi-gate devices. In furtherance of the example, a multilayer interconnection may include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may employ various conductive materials including copper, tungsten, and/or silicide. In one example, a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure. Moreover, additional process steps may be implemented before, during, and after the method100, and some process steps described above may be replaced or eliminated in accordance with various embodiments of the method100.

Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to a semiconductor device and the formation thereof. For example, embodiments of the present disclosure provide a seed layer embedded in an inner spacer layer so as to provide larger semiconductor surface area in a S/D trench to facilitate S/D epitaxial growth, which in turn improves qualities of the S/D epitaxial features. The inner spacer layer also provides isolation between S/D regions and the gate stack. Furthermore, the inner spacer layer and the seed layer formation method can be easily integrated into existing semiconductor fabrication processes.

In one exemplary aspect, the present disclosure is directed to a method of manufacturing a semiconductor device. The method includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked; forming a sacrificial gate structure over the fin structure; etching a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a source/drain trench; laterally etching the first semiconductor layers through the source/drain trench; forming an inner spacer layer, in the source/drain trench, at least on lateral ends of the etched first semiconductor layers; forming a seeding layer on the inner spacer layer; and growing a source/drain epitaxial layer in the source/drain trench, wherein the growing of the source/drain epitaxial layer includes growing the source/drain epitaxial layer from the seeding layer. In some embodiments, the seeding layer is partially embedded in the inner spacer layer. In some embodiments, the forming of the inner spacer layer includes depositing the inner spacer layer in the source/drain trench, thereby covering lateral ends of the second semiconductor layers; and partially removing the inner spacer layer to expose the lateral ends of the second semiconductor layers. In some embodiments, the forming of the seeding layer includes epitaxially growing the seeding layer on the inner spacer layer, wherein the seeding layer covers lateral ends of the second semiconductor layers; and partially removing the seeding layer from the lateral ends of the second semiconductor layers. In some embodiments, the method further includes after the forming of the seeding layer, oxidizing the inner spacer layer. In some embodiments, the growing of the source/drain epitaxial layer includes growing a first epitaxial layer directly from the seeding layer; and growing a second epitaxial layer directly from the first epitaxial layer, wherein the second epitaxial layer has a higher dopant concentration than that of the first epitaxial layer. In some embodiments, the inner spacer layer includes germanium. In some embodiments, the seeding layer includes undoped silicon. In some embodiments, the seeding layer includes amorphous silicon. In some embodiments, the method further includes removing the sacrificial gate structure, thereby forming a gate trench; removing the first semiconductor layers from the gate trench, thereby exposing the second semiconductor layers in the gate trench; and forming a metal gate structure engaging the exposed second semiconductor layers.

In another exemplary aspect, the present disclosure is directed to a method of manufacturing a semiconductor device. The method includes forming a fin extruding from a substrate, the fin having a plurality of sacrificial layers and a plurality of channel layers, wherein the sacrificial layers and the channel layers are alternately arranged; removing the sacrificial layers and the channel layers from a source/drain region of the fin, thereby forming a source/drain trench; depositing a first semiconductor layer in the source/drain trench; depositing a second semiconductor layer on the first semiconductor layer; partially removing the first semiconductor layer and the second semiconductor layer to expose the channel layers in the source/drain trench; oxidizing the first semiconductor layer; and epitaxially growing a source/drain feature from the second semiconductor layer. In some embodiments, the second semiconductor layer has a dielectric constant higher than that of the oxidized first semiconductor layer. In some embodiments, the first semiconductor layer includes silicon germanium and the second semiconductor layer includes silicon. In some embodiments, after the partially removing of the first semiconductor layer and the second semiconductor layer, remaining portions of the second semiconductor layer are surrounded by the first semiconductor layer. In some embodiments, the depositing of the first semiconductor layer and the depositing of the second semiconductor layer both include an epitaxial growing process. In some embodiments, the method further includes removing the sacrificial layers from a channel region of the fin, thereby forming a gate trench; and forming a gate structure engaging the channel layers in the gate trench.

In yet another exemplary aspect, the present disclosure is directed to a multi-gate semiconductor device. The multi-gate semiconductor device includes channel members disposed over a substrate; a gate structure engaging the channel members; a source/drain epitaxial feature adjacent the channel members; an inner spacer layer interposing the gate structure and the source/drain epitaxial feature; and a semiconductor layer interposing the inner spacer layer and the source/drain epitaxial feature. In some embodiments, the semiconductor layer is embedded in the inner spacer layer. In some embodiments, the semiconductor layer is in physical contact with the source/drain epitaxial feature. In some embodiments, the inner spacer layer surrounds lateral ends of the channel members, and wherein the lateral ends of the channel members have a thickness smaller than center portions of the channel members.

The foregoing outlines features of several embodiments so that those of ordinary skill in the art may better understand the aspects of the present disclosure. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.