Patent ID: 12210773

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG.1is a block diagram of a storage device100according to embodiments of the inventive concept.

Referring toFIG.1, the storage device10may include a memory device110and a memory controller120. Although in the present embodiment the storage device100is shown including a plurality of hardware components, the inventive concept is not limited thereto, and other components may be included. The memory controller120may control the memory device110to write data to the memory device110, in response to a write request from a host, or may control the memory device110to read data stored in the memory device110, in response to a read request from the host.

In some embodiments of the inventive concept, the storage device100may include an internal memory that is embedded in an electronic device. For example, the storage device100may include an embedded universal flash storage (UFS) memory device, an embedded multi-media card (eMMC), or a solid state drive (SSD). However, the inventive concept is not limited thereto, and the storage device100may include a non-volatile memory (e.g., a one-time programmable read-only memory (OTPROM), a programmable ROM (PROM), an erasable and programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a mask ROM, a flash ROM, or the like). In some embodiments of the inventive concept, the storage device100may include an external memory that is detachable from an electronic device. For example, the storage device100may include at least one of a UFS memory card, a compact flash (CF) card, a secure digital (SD) card, a micro-SD card, a mini-SD card, an extreme digital (xD) card, and a memory stick.

The storage device100may support a plurality of channels CH1to CHm, and the memory device110may be connected to the memory controller120through the plurality of channels CH1to CHm. The memory device110may include a plurality of non-volatile memory devices NVM11to NVMmn. Each of the non-volatile memory devices NVM11to NVMmn may be connected to one of the plurality of channels CH1to Chm through a corresponding way. For example, the non-volatile memory devices NVM11to NVM1nmay be respectively connected to a first channel CH1through ways W11to W1n, and the non-volatile memory devices NVM21to NVM2nmay be respectively connected to a second channel CH2through ways W21to W2n. In addition, the non-volatile memory devices NVMm1to NVMmn may be respectively connected to an mth channel CHm through ways Wm1to Wmn. In an embodiment of the inventive concept, each of the non-volatile memory devices NVM11to NVMmn may be implemented by any memory unit capable of operating according to an individual command from the memory controller120. For example, although each of the non-volatile memory devices NVM11to NVMmn may be implemented by a chip or a die, the inventive concept is not limited thereto.

The memory controller120may transmit signals to and receive signals from the memory device110through the plurality of channels CH1to CHm. For example, the memory controller120may transmit commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the memory device110through the channels CH1to CHm or may receive the data DATAa to DATAm from the memory device110.

The memory controller120may select, through each channel, one of the non-volatile memory devices connected to the corresponding channel and may transmit signals to and receive signals from the selected non-volatile memory device. For example, the memory controller120may select a non-volatile memory device NVM11from among the non-volatile memory devices NVM11to NVM1nconnected to the first channel CH1. The memory controller120may transmit the command CMDa, the address ADDRa, and the data DATAa to the selected non-volatile memory device NVM11or may receive the data DATAa from the selected non-volatile memory device NVM11, through the first channel CH1.

The memory controller120may transmit signals to and receive signals from the memory device110in parallel through different channels. For example, the memory controller120may transmit the command CMDb to the memory device110through the second channel CH2while transmitting the command CMDa to the memory device110through the first channel CH1. For example, the memory controller120may receive the data DATAb from the memory device110through the second channel CH2while receiving the data DATAa from the memory device110through the first channel CH1. In addition, the memory device110may receive the data DATAb from the memory controller120through the second channel CH2while receiving the data DATAa from the memory controller120through the first channel CH1.

The memory controller120may control overall operations of the memory device110. The memory controller120may control each of the non-volatile memory devices NVM11to NVMmn connected to the channels CH1to CHm by transmitting signals to the channels CH1to CHm. For example, the memory controller120may control one selected from among the non-volatile memory devices NVM11to NVM1nby transmitting the command CMDa and the address ADDRa to the first channel CH1.

Each of the non-volatile memory devices NVM11to NVMmn may be operated according to control by the memory controller120. For example, a first non-volatile memory device NVM11may program the data DATAa according to the command CMDa, the address ADDRa, and the data DATAa, which are provided to the first channel CH1. For example, a second non-volatile memory device NVM21may read the data DATAb according to the command CMDb and the address ADDRb, which are provided to the second channel CH2, and may transmit the read data DATAb to the memory controller120.

The memory controller120may transmit a command for a second non-volatile memory device NVM12to the second non-volatile memory device NVM12through a data signal line of the first channel CH1while receiving, through a data signal line in the first channel CH1, output data output from the first non-volatile memory device NVM11among the non-volatile memory devices NVM11to NVM1nconnected to a single channel, for example, the first channel CH1. The memory controller120may change a voltage level of a data signal line of the first channel CH1based on a command for the second non-volatile memory device NVM12. Accordingly, output data output from the first non-volatile memory device NVM11may be loaded on the data signal line of the first channel CH1having the changed voltage level, and the output data of the first non-volatile memory device NVM11and the command for the second non-volatile memory device NVM12may be transmitted in both directions of the data signal line of the first channel CH1. In other words, information may be simultaneously transmitted in both directions of a channel. For example, information may be simultaneously transmitted in first and second directions of a channel. The first and second directions may be opposite to each other.

AlthoughFIG.1illustrates that the memory device110communicates with the memory controller120through in channels and includes n non-volatile memory devices in correspondence with each channel, the number of channels and the number of non-volatile memory devices connected to a single channel may be variously changed.

FIG.2is a diagram illustrating a memory interface associated with the first channel CH1of the storage device100ofFIG.1.

Referring toFIGS.1and2, the memory controller120may select the first non-volatile memory device NVM11(hereinafter, referred to as a first NVM110a) from among the non-volatile memory devices NVM11to NVM1nconnected to the first channel CH1. The memory controller120is connected to the first NVM110athrough the first channel CH1. The first NVM110amay include first, second, third, fourth, fifth, sixth, seventh and eighth pins P11, P12, P13, P14, P15, P16, P17and P18, a memory interface circuit112, a control logic circuit114, and a memory cell array116.

The memory interface circuit112may receive a chip enable signal nCE from the memory controller120through the first pin P11. The memory interface circuit112may transmit signals to and receive signals from the memory controller120through the second to eighth pins P12to P18according to the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (for example, a low level), the memory interface circuit112may transmit signals to and receive signals from the memory controller120through the second to eighth pins P12to P18. When the chip enable signal nCE is in a not-enabled state, the memory interface circuit112may not transmit signals to and receive signals from the memory controller120.

The memory interface circuit112may receive a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE from the memory controller120through the second to fourth pins P12to P14. The memory interface circuit112may receive a data signal DQ from the memory controller120or may transmit the data signal DQ to the memory controller120, through the seventh pin P17. A command CMDa, an address ADDRa, and data DATAa may be transferred through the data signal DQ. For example, the data signal DQ may be transferred through a plurality of data signal lines. In this case, the seventh pin P17may include a plurality of pins corresponding to a plurality of data signals.

The memory interface circuit112may obtain the command CMDa from the data signal DQ received in an enabled period (for example, a high-level state) of the command latch enable signal CLE, based on toggle timings of the write enable signal nWE. The memory interface circuit112may obtain the address ADDRa from the data signal DQ received in an enabled period (for example, a high-level state) of the address latch enable signal ALE, based on the toggle timings of the write enable signal nWE.

In an embodiment of the inventive concept, the write enable signal nWE may be maintained in a static state (for example, a high level or a low level) and then may toggle between the high level and the low level. For example, the write enable signal nWE may toggle in a period in which the command CMDa or the address ADDRa is transmitted. Accordingly, the memory interface circuit112may obtain the command CMDa or the address ADDRa, based on the toggle timings of the write enable signal nWE.

The memory interface circuit112may receive a read enable signal nRE from the memory controller120through the fifth pin P15. The memory interface circuit112may receive a data strobe signal DQS from the memory controller120or transmit the data strobe signal DQS to the memory controller120, through the sixth pin P16.

In a data output operation of the first NVM110a, the memory interface circuit112may receive the read enable signal nRE that toggles, through the fifth pin P15, before the data DATAa is output. The memory interface circuit112may generate the data strobe signal DQS that toggles, based on the toggling of the read enable signal nRE. For example, the memory interface circuit112may generate the data strobe signal DQS that starts to toggle after a preset delay (for example, tDQSRE) from a toggling start time of the read enable signal nRE. The memory interface circuit112may transmit the data signal DQ including the data DATAa, based on a toggle timing of the data strobe signal DQS. Accordingly, the data DATAa may be transmitted to the memory controller120in alignment with the toggle timing of the data strobe signal DQS.

In a data input operation of the first NVM110a, when the data signal DQ including the data DATAa is received from the memory controller120, the memory interface circuit112may receive the data strobe signal DQS that toggles, together with the data DATAa, from the memory controller120. The memory interface circuit112may obtain the data DATAa from the data signal DQ, based on the toggle timing of the data strobe signal DQS. For example, the memory interface circuit112may obtain the data DATA by sampling the data signal DQ at a rising edge and a falling edge of the data strobe signal DQS.

The memory interface circuit112may transmit a ready/busy output signal R/nB through the eighth pin P18. The memory interface circuit112may transmit state information of the first NVM110ato the memory controller120through the ready/busy output signal R/nB. When the first NVM110ais in a busy state (in other words, when internal operations of the first NVM110aare being performed), the memory interface circuit112may transmit, to the memory controller120, the ready/busy output signal R/nB indicating the busy state. When the first NVM110ais in a ready state (in other words, when the internal operations of the first NVM110aare not being performed or are completed), the memory interface circuit112may transmit, to the memory controller120, the ready/busy output signal R/nB indicating the ready state. For example, while the first NVM110areads the data DATAa from the memory cell array116in response to a page read command, the memory interface circuit112may transmit, to the memory controller120, the ready/busy output signal R/nB indicating the busy state (for example, a low level). For example, while the first NVM110aprograms the data DATAa into the memory cell array116in response to a program command, the memory interface circuit112may transmit, to the memory controller120, the ready/busy output signal R/nB indicating the busy state (for example, a low level).

The control logic circuit114may take overall control of various operations of the first NVM110a. The control logic circuit114may receive a command/address CMDa/ADDRa obtained from the memory interface circuit112. The control logic circuit114may generate control signals for controlling the other components of the first NVM110a, according to the received command/address CMDa/ADDRa. For example, the control logic circuit114may generate various control signals for programming the data DATAa into the memory cell array116or reading the data DATAa from the memory cell array116.

The memory cell array116may store the data DATAa obtained from the memory interface circuit112, according to control by the control logic circuit114. The memory cell array116may output the stored data DATAa to the memory interface circuit112, according to control by the control logic circuit114.

The memory cell array116may include a plurality of memory cells. For example, the plurality of memory cells may include flash memory cells. However, the inventive concept is not limited thereto, and the memory cells may include resistive random access memory (RRAM) cells, ferroelectric RAM (FRAM) cells, phase-change RAM (PRAM) cells, thyristor RAM (TRAM) cells, or magnetoresistive RAM (MRAM) cells. According to an embodiment of the inventive concept, the memory cells may include static RAM (SRAM) cells or dynamic RAM (DRAM) cells. Hereinafter, embodiments of the inventive concept, in which the memory cells are NAND flash memory cells, will be mainly described.

The memory controller120may include first, second, third, fourth, fifth, sixth, seventh and eighth pins P21, P22, P23, P24, P25, P26, P27and P28, a controller interface circuit122, a command logic circuit123, an on-die termination (ODT) circuit124, a switch circuit125, and a data extraction circuit126. The first to eighth pins P21to P28may respectively correspond to the first to eighth pins P11to P18of the first NVM110a. In other words, the first pin P21may be connected to the first pin P11and the eighth pin P28may be connected to the eighth pin P18.

The controller interface circuit122may transmit the chip enable signal nCE to the first NVM110athrough the first pin P21. The controller interface circuit122may transmit signals to and receive signals from the first NVM110a, which is selected through the chip enable signal nCE, through the second to eighth pins P22to P28.

The controller interface circuit122may transmit the command enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the first NVM110athrough the second to fourth pins P22to P24. The controller interface circuit122may transmit the data signal DQ to the first NVM110aor receive the data signal DQ from the first NVM110a, through the seventh pin P27.

The controller interface circuit122may transmit the data signal DQ including the command CMDa or the address ADDRa, together with the write enable signal nWE that is toggling, to the first NVM110a. The controller interface circuit122may transmit the data signal DQ including the command CMDa when the command latch enable signal CLE having an enabled state is transmitted, and the controller interface circuit122may transmit the data signal DQ including the address ADDRa when the address latch enable signal ALE having an enabled state is transmitted.

The controller interface circuit122may transmit the read enable signal nRE to the first NVM110athrough the fifth pin P25. The controller interface circuit122may receive the data strobe signal DQS from the first NVM110aor transmit the data strobe signal DQS to the first NVM110a, through the sixth pin P26.

In a data output operation of the first NVM110a, the controller interface circuit122may generate the read enable signal nRE that toggles, and may transmit the read enable signal nRE to the first NVM110a. For example, the controller interface circuit122may generate the read enable signal nRE, which changes from a static state (for example, a high level or a low level) to a toggle state, before the data DATAa is output. Accordingly, in the first NVM110a, the data strobe signal DQS, which toggles based on the read enable signal nRE, may be generated. The controller interface circuit122may receive the data signal DQ including the data DATAa, together with the data strobe signal DQS that toggles, from the first NVM110a. The controller interface circuit122may obtain the data DATAa from the data signal DQ, based on the toggle timing of the data strobe signal DQS.

In a data input operation of the first NVM110a, the controller interface circuit122may generate the data strobe signal DQS that toggles. For example, the controller interface circuit122may generate the data strobe signal DQS, which changes from a static state (for example, a high level or a low level) to a toggle state, before the data DATAa is transmitted. The controller interface circuit122may transmit the data signal DQ including the data DATAa to the first NVM110a, based on toggle timings of the data strobe signal DQS.

The controller interface circuit122may receive the ready/busy output signal R/nB from the first NVM110athrough the eighth pin P28. The controller interface circuit122may determine the state information of the first NVM110a, based on the ready/busy output signal R/nB.

While the memory controller120receives, through the data signal DQ line and the seventh pin P27, output data output in a data output operation of the first NVM110a, the command logic circuit123may generate a command for another non-volatile memory device (e.g., the second non-volatile memory device NVM12) connected to the first channel CH1. The command logic circuit123may output control signals based on a command for the second non-volatile memory device NVM12.

The ODT circuit124may provide a termination resistance to the data signal DQ line through the seventh pin P27to adjust the swing widths and/or driving strengths of signals received through the data signal DQ line and increase signal integrity.

The switch circuit125may transmit a command for the second non-volatile memory device NVM12to the second non-volatile memory device NVM12through the seventh pin P27and the data signal DQ line in response to control signals of the command logic circuit123.

The data extraction circuit126may receive, through the data signal DQ line and the seventh pin P27, the output data output in a data output operation of the first NVM110a, and may obtain internal data corresponding to the output data of the first NVM110a.

FIG.3is a block diagram of the first NVM110aillustrated inFIG.2.

Referring toFIG.3, the first NVM110amay include a control logic circuit114, a memory cell array116, a page buffer unit118, a voltage generator119, and a row decoder394. The first NVM110amay further include a command decoder, an address decoder, an input/output (I/O) buffer, and the like.

The control logic circuit114may control various overall operations of the first NVM110a. The control logic circuit114may output various control signals in response to a command CMDa and/or an address ADDRa from the memory controller120. For example, the control logic circuit114may output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

The memory cell array116may include a plurality of memory blocks BLK1to BLKz, and each of the plurality of memory blocks BLK1to BLKz may include a plurality of memory cells. The memory cell array116may be connected to the page buffer unit118via bit lines BL, and may be connected to the row decoder394via word lines WL, string selection lines SSL, and ground selection lines GSL.

According to an embodiment of the inventive concept, the memory cell array116may include a 3D memory cell array, and the 3D memory cell array may include a plurality of memory NAND strings. Each memory NAND string may include memory cells respectively connected to word lines vertically stacked on a substrate. U.S. Pat. Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and U.S. Patent Application Publication No. 2011/0233648 are incorporated by reference herein in their entireties. According to an embodiment of the inventive concept, the memory cell array116may include a two-dimensional (2D) memory cell array, and the 2D memory cell array may include a plurality of memory NAND strings arranged in a column direction and a row direction.

The page buffer unit118may include a plurality of page buffers PB1to PBn (where n is an integer equal to or greater than 2), and the plurality of page buffers PB1to PBn may be connected to the memory cells via the plurality of bit lines BL, respectively. The page buffer unit118may select at least one bit line from the plurality of bit lines BL in response to the column address Y-ADDR. The page buffer circuit118may operate as a write driver or a sense amplifier according to operation modes. For example, during a program operation, the page buffer circuit118may apply a bit line voltage corresponding to data DATAa that is to be programmed to a selected bit line. During a read operation, the page buffer circuit118may sense a current or voltage of the selected bit line to sense the data DATAa stored in a memory cell.

The voltage generator119may generate various types of voltages for performing program, read, and erase operations, based on the voltage control signal CTRL_vol. For example, the voltage generator119may generate word line voltages VWL, for example, a program voltage, a read voltage, a program verify voltage, and an erase voltage.

The row decoder394may select one word line from the plurality of word lines WL in response to the row address X-ADDR, and may select one string selection line from the plurality of string selection lines SSL. For example, during a program operation, the row decoder394may apply a program voltage and a program verify voltage to the selected word line, and, during a read operation, the row decoder394may apply a read voltage to the selected word line.

FIGS.4to6are diagrams for explaining a 3D V-NAND structure applicable to the first NVM110aofFIG.3.FIG.4is an equivalent circuit of a memory block BLKi, andFIG.5is a perspective view of the memory block BLKi.FIG.6illustrates a first NVM110ahaving a chip-to-chip (C2C) structure.

Referring toFIG.4, the memory block BLKi may include a plurality of memory NAND strings NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32and NS33connected between bit lines BL1, BL2, and BL3and a common source line CSL. Each of the plurality of memory NAND strings NS11to NS33may include a string select transistor SST, a plurality of memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7and MC8, and a ground select transistor GST. For brevity of illustration, each of the plurality of memory NAND strings NS11to NS33includes eight memory cells MC1to MC8inFIG.4. However, the inventive concept is not limited thereto.

The string select transistor SST may be connected to a corresponding one of string selection lines SSL1, SSL2, and SSL3. The plurality of memory cells MC1to MC8may be connected to gate lines GTL1, GTL2, GTL3, GTL4, GTL5, GTL6, GTL7and GTL8, respectively. The gate lines GTL1to GTL8may respectively correspond to word lines, and some of the gate lines GTL1to GTL8may respectively correspond to dummy word lines. For example, dummy wordlines may be adjacent to the string selection lines SSL1, SSL2, and SSL3. The ground select transistor GST may be connected to a corresponding one of ground selection lines GSL1, GSL2, and GSL3. The dummy wordlines may also be adjacent to the ground selection lines GSL1, GSL2, and GSL3. The string select transistor SST may be connected to a corresponding one of the bit lines BL1, BL2, and BL3, and the ground select transistor GST may be connected to the common source line CSL.

Gate lines (for example, GTL1) on the same level may be commonly connected to one another, and the ground selection lines GSL1, GSL2, and GSL3and the string selection lines SSL1, SSL2, and SSL3may be separated from one another. Although the memory block BLKi is connected to the eight gate lines GTL1to GTL8and the three bit lines BL1, BL2, and BL3inFIG.4, the inventive concept is not limited thereto.

Referring toFIGS.5and6, the memory block BLKi is formed in a vertical direction with respect to a substrate SUB. Memory cells that constitute the memory NAND strings NS11to NS33are stacked on a plurality of semiconductor layers.

Common source lines CSL each extending in a first direction (Y direction) are provided on the substrate SUB. On a portion of the substrate SUB between two adjacent common source lines CSL, a plurality of insulation layers IL each extending in the first direction (Y direction) may be provided sequentially in a third direction (Z direction), and the plurality of insulation layers IL may be spaced apart from one another by a specific distance in the third direction (Z direction). A plurality of pillars P sequentially arranged in the first direction (Y direction) and penetrating through the plurality of insulation layers IL in the third direction (Z direction) are provided on the portion of the substrate SUB between two adjacent common source lines CSL. The plurality of pillars P may penetrate through the plurality of insulation layers IL and contact the substrate SUB. A surface layer S of each of the plurality of pillars P may include a silicon material doped with impurities of a first conductive type, and may function as a channel region. An internal layer I of each of the plurality of pillars P may include an insulating material such as silicon oxide, or an air gap. On the portion of the substrate SUB between two adjacent common source lines CSL, a charge storage layer CS is provided along the insulation layers IL, the pillars P, and an exposed surface of the substrate SUB. The charge storage layer CS may include a gate insulation layer (or a tunneling insulation layer), a charge trapping layer, and a blocking insulation layer. On the portion of the substrate SUB between two adjacent common source lines CSL, a gate electrode GE such as the string and ground selection lines SLL and GSL and word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7and WL8is provided on an exposed surface of the charge storage layer CS. Drains or drain contacts DR may be provided on the plurality of pillars P, respectively. The bit lines BL1to BL3each extending in the second direction (X direction) and spaced apart from one another by a specific distance in the first direction (Y direction) may be provided on the drain contacts DR.

As shown inFIG.5, each of the memory NAND strings NS11to NS33may be implemented as a structure in which a first memory stack ST1and a second memory stack ST2are stacked in a third direction (Z direction). The first memory stack ST1is connected to the common source line CSL, the second memory stack ST2is connected to the bit lines BL1to BL3, and the first memory stack ST1and the second memory stack ST2are stacked such that they may share different channel holes.

Referring toFIG.6, a first NVM110amay have a C2C structure. The C2C structure may refer to a structure formed by manufacturing an upper chip including a cell region CELL on a first wafer, manufacturing a lower chip including a peripheral circuit region PERI on a second wafer, separate from the first wafer, and then bonding the upper chip and the lower chip to each other. Here, the bonding process may include a method of electrically connecting a bonding metal formed on an uppermost metal layer of the upper chip and a bonding metal formed on an uppermost metal layer of the lower chip. For example, when the bonding metals may include copper (Cu), a Cu-to-Cu bonding technique may be employed. The present embodiment, however, may not be limited thereto. For example, the bonding metals may also be formed of aluminum (Al) or tungsten (W).

Each of the peripheral circuit region PERI and the cell region CELL of the first NVM110amay include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

The peripheral circuit region PERI may include a first substrate210, an interlayer insulating layer215, a plurality of circuit elements220a,220b, and220cformed on the first substrate210, first metal layers230a,230b, and230crespectively connected to the plurality of circuit elements220a,220b, and220c, and second metal layers240a,240b, and240cformed on the first metal layers230a,230b, and230c. In an embodiment of the inventive concept, the first metal layers230a,230b, and230cmay be formed of tungsten having relatively high electrical resistivity, and the second metal layers240a,240b, and240cmay be formed of copper having relatively low electrical resistivity.

In the embodiment illustrated inFIG.6, although only the first metal layers230a,230b, and230cand the second metal layers240a,240b, and240care shown and described, the inventive concept is not limited thereto, and one or more additional metal layers may be further formed on the second metal layers240a,240b, and240c. At least a portion of the one or more additional metal layers formed on the second metal layers240a,240b, and240cmay be formed of aluminum or the like having a lower electrical resistivity than those of copper forming the second metal layers240a,240b, and240c.

The interlayer insulating layer215may be disposed on the first substrate210and cover the plurality of circuit elements220a,220b, and220c, the first metal layers230a,230b, and230c, and the second metal layers240a,240b, and240c. The interlayer insulating layer215may include an insulating material such as silicon oxide, silicon nitride, or the like.

Lower bonding metals271band272bmay be formed on the second metal layer240bin the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals271band272bin the peripheral circuit region PERI may be electrically bonded to upper bonding metals371band372bof the cell region CELL. The lower bonding metals271band272band the upper bonding metals371band372bmay be formed of aluminum, copper, tungsten, or the like. Further, the upper bonding metals371band372bin the cell region CELL may be referred as first metal pads and the lower bonding metals271band272bin the peripheral circuit region PERI may be referred as second metal pads.

The cell region CELL may include at least one memory block. The cell region CELL may include a second substrate310and a common source line320. On the second substrate310, a plurality of word lines331,332,333,334,335,336,337and338(e.g.,330) may be stacked in a direction (a Z-axis direction), perpendicular to an upper surface of the second substrate310. At least one string select line and at least one ground select line may be arranged on and below the plurality of word lines330, respectively, and the plurality of word lines330may be disposed between the at least one string select line and the at least one ground select line.

In the bit line bonding area BLBA, a channel structure CH may extend in a direction (a Z-axis direction), perpendicular to the upper surface of the second substrate310, and pass through the plurality of word lines330, the at least one string select line, and the at least one ground select line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, and the like, and the channel layer may be electrically connected to a first metal layer350cand a second metal layer360c. For example, the first metal layer350cmay be a bit line contact, and the second metal layer360cmay be a bit line. In an embodiment of the inventive concept, the bit line360cmay extend in a first direction (a Y-axis direction), parallel to the upper surface of the second substrate310.

In the embodiment illustrated inFIG.6, an area in which the channel structure CH, the bit line360c, and the like are disposed may be the bit line bonding area BLBA. In the bit line bonding area BLBA, the bit line360cmay be electrically connected to the circuit elements220cproviding a page buffer393in the peripheral circuit region PERI. The bit line360cmay be connected to upper bonding metals371cand372cin the cell region CELL, and the upper bonding metals371cand372cmay be connected to lower bonding metals271cand272cconnected to the circuit elements220cof the page buffer393.

In the word line bonding area WLBA, the plurality of word lines330may extend in a second direction (an X-axis direction), parallel to the upper surface of the second substrate310and perpendicular to the first direction, and may be connected to a plurality of cell contact plugs341,342,343,344,345,346and347(e.g.,340). The plurality of word lines330and the plurality of cell contact plugs340may be connected to each other in pads provided by at least a portion of the plurality of word lines330extending in different lengths in the second direction. A first metal layer350band a second metal layer360bmay be connected to an upper portion of the plurality of cell contact plugs340connected to the plurality of word lines330, sequentially. The plurality of cell contact plugs340may be connected to the peripheral circuit region PERI by the upper bonding metals371band372bof the cell region CELL and the lower bonding metals271band272bof the peripheral circuit region PERI in the word line bonding area WLBA.

The plurality of cell contact plugs340may be electrically connected to the circuit elements220bforming a row decoder394in the peripheral circuit region PERI. In an embodiment of the inventive concept, operating voltages of the circuit elements220bof the row decoder394may be different than operating voltages of the circuit elements220cforming the page buffer393. For example, operating voltages of the circuit elements220cforming the page buffer393may be greater than operating voltages of the circuit elements220bforming the row decoder394.

A common source line contact plug380may be disposed in the external pad bonding area PA. The common source line contact plug380may be formed of a conductive material such as a metal, a metal compound, polysilicon, or the like, and may be electrically connected to the common source line320. A first metal layer350aand a second metal layer360amay be stacked on an upper portion of the common source line contact plug380, sequentially. For example, an area in which the common source line contact plug380, the first metal layer350a, and the second metal layer360aare disposed may be the external pad bonding area PA.

Input-output pads205and305may be disposed in the external pad bonding area PA. Referring toFIG.6, a lower insulating film201covering a lower surface of the first substrate210may be formed below the first substrate210, and a first input-output pad205may be formed on the lower insulating film201. The first input-output pad205may be connected to at least one of the plurality of circuit elements220a,220b, and220cdisposed in the peripheral circuit region PERI through a first input-output contact plug203, and may be separated from the first substrate210by the lower insulating film201. In addition, a side insulating film may be disposed between the first input-output contact plug203and the first substrate210to electrically separate the first input-output contact plug203and the first substrate210.

Referring toFIG.6, an upper insulating film301covering the upper surface of the second substrate310may be formed on the second substrate310, and a second input-output pad305may be disposed on the upper insulating layer301. The second input-output pad305may be connected to at least one of the plurality of circuit elements220a,220b, and220cdisposed in the peripheral circuit region PERI through a second input-output contact plug303. In the present embodiment, the second input-output pad305is electrically connected to the circuit element220a.

According to embodiments of the inventive concept, the second substrate310and the common source line320may not be disposed in an area in which the second input-output contact plug303is disposed. In addition, the second input-output pad305may not overlap the word lines330in the third direction (the Z-axis direction). Referring toFIG.6, the second input-output contact plug303may be separated from the second substrate310in a direction, parallel to the upper surface of the second substrate310, and may pass through the interlayer insulating layer315of the cell region CELL to be connected to the second input-output pad305.

According to embodiments of the inventive concept, the first input-output pad205and the second input-output pad305may be selectively formed. For example, the first NVM110amay include only the first input-output pad205disposed on the first substrate210or the second input-output pad305disposed on the second substrate310. Alternatively, the first NVM110amay include both the first input-output pad205and the second input-output pad305.

A metal pattern provided on an uppermost metal layer may be provided as a dummy pattern or the uppermost metal layer may be absent, in each of the external pad bonding area PA and the bit line bonding area BLBA, respectively included in the cell region CELL and the peripheral circuit region PERI.

In the external pad bonding area PA, the first NVM110amay include a lower metal pattern273a, corresponding to an upper metal pattern372aformed in an uppermost metal layer of the cell region CELL, and having the same cross-sectional shape as the upper metal pattern372aof the cell region CELL so as to be connected to each other, in an uppermost metal layer of the peripheral circuit region PERI. In the peripheral circuit region PER, the lower metal pattern273aformed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a contact. Similarly, in the external pad bonding area PA, the upper metal pattern372a, corresponding to the lower metal pattern273aformed in an uppermost metal layer of the peripheral circuit region PERI, and having the same shape as a lower metal pattern273aof the peripheral circuit region PERI, may be formed in an uppermost metal layer of the cell region CELL.

The lower bonding metals271band272bmay be formed on the second metal layer240bin the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals271band272bof the peripheral circuit region PERI may be electrically connected to the upper bonding metals371band372bof the cell region CELL by a Cu-to-Cu bonding.

Further, in the bit line bonding area BLBA, an upper metal pattern392, corresponding to a lower metal pattern252formed in the uppermost metal layer of the peripheral circuit region PERI, and having the same cross-sectional shape as the lower metal pattern252of the peripheral circuit region PERI, may be formed in an uppermost metal layer of the cell region CELL. A contact may not be formed on the upper metal pattern392formed in the uppermost metal layer of the cell region CELL.

In an embodiment of the inventive concept, corresponding to a metal pattern formed in an uppermost metal layer in one of the cell region CELL and the peripheral circuit region PERI, a reinforcement metal pattern having the same cross-sectional shape as the metal pattern may be formed in an uppermost metal layer in the other one of the cell region CELL and the peripheral circuit region PERI. A contact may not be formed on the reinforcement metal pattern.

FIG.7is a circuit diagram of a storage device100according to embodiments of the inventive concept. Hereinafter, subscripts (e.g., ‘a’ of110aand ‘b’ of110b) attached to reference numerals are used to distinguish a plurality of circuits having the same function. In the following embodiments, terms “data signal DQ and “DQ” may be used interchangeably for convenience.

Referring toFIGS.2and7, the memory controller120may be connected to first and second NVMs110aand110bthrough a first channel CH1. In the present embodiment, a data signal DQ line700(hereinafter, referred to as “DQ line700”) among a plurality of signal lines of the first channel CH1described with reference toFIG.2will be described. The DQ line700of the first channel CH1may be connected in common to a DQ pin P27of the memory controller120, a DQ pad P17aof the first NVM110a, and a DQ pad P17bof the second NVM110b.

The first NVM110amay include an output buffer712aand an input buffer714aeach connected to the DQ pad P17a, and the second NVM110bmay include an output buffer712band an input buffer714beach connected to the DQ pad P17b. The output buffers712aand712band the input buffers714aand714bmay be driven by a power voltage VCC and a ground voltage VSS.

Each of the first and second NVMs110aand110bmay output data DOUT, which is output according to a read operation, to the DQ pads P17aand P17bthrough the output buffers712aand712b. Among the first and second NVMs110aand110b, the first NVM110areceiving a read enable signal nRE from the memory controller120may output the output data DOUT to the DQ pad P17aand the DQ line700through the output buffer712a. The memory controller120may receive the output data DOUT of the first NVM110atransmitted to the DQ line700.

The first and second NVMs110aand110bmay receive a command CMD, which is provided from the memory controller120to the DQ line700, through the DQ pads P17aand P17band the input buffers714aand714b, respectively. The input buffers714aand714bmay include a comparator for comparing the level of a signal applied to the DQ pads P17aand P17bwith the level of a second reference voltage VREF2, and may obtain an internal command iCMD through the comparator. In other words, the comparator may output the internal command iCMD based on the comparison of the signal applied to the DQ pads P17aand P17bwith the second reference voltage VREF2. According to an embodiment of the inventive concept, the second reference voltage VREF2may be set to an intermediate voltage level between the power voltage VCC and the ground voltage VSS. Among the first and second NVMs110aand110b, the second NVM110breceiving a write enable signal nWE and a command latch enable signal CLE from the memory controller120may receive the command CMD of the memory controller120through the DQ pad P17band the input buffer714b. The second NVM110bmay obtain an internal command iCMD corresponding to the command CMD of the memory controller120.

The memory controller120may include a switch circuit125and a data extraction circuit126each connected to the DQ pin P27. The switch circuit125may be connected to the ODT circuit124in selective response to a pull-up signal PU and a pull-down signal PD each provided from the command logic circuit123. When the command logic circuit123generates a command CMD to be provided to the first and second NVMs110aand110b, the command logic circuit123may generate a pull-up signal PU, a pull-down signal PD, and a selection signal SEL according to a signal bit value (hereinafter, referred to as a CMD signal bit) of the command CMD. The pull-up signal PU, the pull-down signal PD, and the selection signal SEL provided from the command logic circuit123may be referred to as control signals. The command logic circuit123may generate the pull-up signal PU when the CMD signal bit is logic ‘1’, and generate the pull-down signal PD when the CMD signal bit is logic ‘0’. In addition, the command logic circuit123may generate the selection signal SEL at a logic high level when the CMD signal bit is logic ‘1’, generate the selection signal SEL at a logic low level when the CMD signal bit is logic ‘0’, and provide the selection signal SEL to the data extraction circuit126.

The ODT circuit124may be provided to increase signal integrity by adjusting the swing widths and/or driving strengths of signals received through the DQ line700. In general, as the swing widths of the signals decrease, an influence due to external noise increases, and signal reflection caused by impedance mismatch at interfaces worsens. To reduce the impedance mismatch, the memory controller120may perform an impedance adjustment operation of constantly adjusting a termination resistance by using the ODT circuit124. Likewise, in the first and second NVMs110aand110b, termination resistances may be provided using the output buffers712aand712b, respectively. According to an embodiment of the inventive concept, the termination resistances of the output buffers712aand712bmay be provided only to the power voltage VCC, thereby implementing a pseudo open drain (POD) level on the DQ line700to reduce the power consumption of the storage device100. The ODT circuit124may include a pull-up resistor portion RU connected to the power voltage VCC and a pull-down resistor portion RD connected to the ground voltage VSS.

The switch circuit125may include a first switch SW1and a second switch SW2, which are connected between the ODT circuit124and the DQ pin P27. The first switch SW1may be connected between the DQ pin P27and the pull-down resistor portion RD and may be turned on or off by the pull-down signal PD of the command logic circuit123. The second switch SW2may be connected between the pull-up resistor portion RU and the DQ pin P27and may be turned on or off by the pull-up signal PU of the command logic circuit123.

The data extraction circuit126may include a first comparator721, a second comparator722, and a selector723. The first comparator721may compare the level of a signal applied to the DQ pin P27with the level of a first reference voltage VREF1and provide a result of the comparison as a first input11of the selector723. The second comparator722may compare the level of the signal applied to the DQ pin P27with the level of a third reference voltage VREF3and provide a result of the comparison to a second input12of the selector723. The level of the first reference voltage VREF1may be set lower than the level of the second reference voltage VREF2, and the level of the third reference voltage VREF3may be set higher than the level of the second reference voltage VREF2.

When the selection signal SEL is at a logic low level, the selector723may select the output of the first comparator721input to the first input11and output the selected output of the first comparator721as an internal data signal iDQ. When the selection signal SEL is at a logic high level, the selector723may select the output of the second comparator722input to the second input12and output the selected output of the second comparator722as the internal data signal iDQ.

FIGS.8to10are diagrams illustrating a method of operating a storage device, according to embodiments of the inventive concept.FIG.8is a flowchart illustrating a read method of the memory controller120with respect to the first and second NVMs110aand110bsharing the DQ line700of the first channel CH1in the storage device100ofFIG.7.FIG.9is a diagram illustrating a read operation between the memory controller120and the first and second NVMs110aand110baccording to the read method ofFIG.8. InFIGS.8and9, the read operation by the memory controller120may include a page read operation according to a page read command, and a data output operation of transmitting data, which is page-read by a page read operation according to a random read command, as output data DOUT to the memory controller120.FIG.10is a chart showing a page read operation of the first and second NVMs110aand110b.

Referring toFIGS.7,8, and9, in operation S810, the memory controller120may transmit a first page read command to the first NVM110a. The memory controller120may transmit a first address to the first NVM110ain addition to the first page read command. The first NVM110amay perform a page read operation910on memory cells corresponding to the first address in the memory cell array116(seeFIG.3) in response to the first page read command.

One or more bits may be programmed to a memory cell in the memory cell array116of the first NVM110a. A memory cell may be a single level cell (SLC), a multi-level cell (MLC), a triple level cell (TLC), or a quad level cell (QLC) according to the number of bits stored in the memory cell. A memory cell may have a plurality of states according to the number of bits stored in the memory cell. Each of the plurality of states may be a range of a threshold voltage. For example, when each of the memory cells is a QLC, a state of each of the memory cells may correspond to one of the sixteen states S1to S16, as shown inFIG.10. Memory cells connected to one word line WL may include a least significant bit (LSB) page, a first central significant bit (CSB1) page, a second central significant bit (CSB2) page, and a most significant bit (MSB) page.

The page read operation910of the first NVM110amay include an operation of searching for valley locations VR1to VR15of the threshold voltages of memory cells, an operation of inferring optimal read voltages RD1to RD15, based on the valley locations VR1to VR15, and a page read operation with respect to each of the LSB page, the CSB1page, the CSB2page, and the MSB page by using the optimal read voltages RD1to RD15. The valley location VR1may be located between states S1and S2and the valley location VR15may be located between states S15and S16.

For example, in a read operation with respect to the LSB page, the memory device110may identify the eleventh and twelfth states S11and S12by applying the eleventh read voltage RD11to the selection word line WL, and then may identify the sixth and seventh states S6and S7, the fourth and fifth states S4and S5, and the first and second states S1and S2by sequentially applying the sixth read voltage RD6, the fourth read voltage RD4, and the first read voltage RD1to the selection word line WL. In a read operation with respect to the CSB1page, the memory device110may identify the thirteenth and fourteenth states S13and S14, the ninth and tenth states S9and S10, the seventh and eighth states S7and S8, and the third and fourth states S3and S4by sequentially applying the thirteenth read voltage RD13, the ninth read voltage RD9, the seventh read voltage RD7, and the third read voltage RD3to the selection word line WL. In a read operation with respect to the CSB2page, the memory device110may identify the fourteenth and fifteenth states S14and S15, the eighth and ninth states S8and S9, and the second and third states S2and S3by sequentially applying the fourteenth read voltage RD14, the eighth read voltage RD8, and the second read voltage RD2to the selection word line WL. In a read operation with respect to the MSB page, the memory device110may identify the fifteenth and sixteenth states S15and S16, the twelfth and thirteenth states S12and S13, the tenth and eleventh states S10and S11, and the fifth and sixth states S5and S6by applying the fifteenth read voltage RD15, the twelfth read voltage RD12, the tenth read voltage RD10, and the fifth read voltage RD5to the selection word line WL.

In operation S820, the memory controller120may transmit a second page read command to the second NVM110b. The memory controller120may transmit a second address to the second NVM110bin addition to the second page read command. The second NVM110bmay perform a page read operation920on memory cells corresponding to the second address in the memory cell array116in response to the second page read command. The page read operation920of the second NVM110b, as described with reference toFIG.10, may include an operation of searching for valley locations VR1to VR15of the threshold voltages of memory cells, an operation of inferring optimal read voltages RD1to RD15, based on the valley locations VR1to VR15, and a page read operation with respect to each of the LSB page, the CSB1page, the CSB2page, and the MSB page by using the optimal read voltages RD1to RD15.

In operation S830, the memory controller120may transmit a first random read command to the first NVM110a. The memory controller120may transmit a third address to the first NVM110ain addition to the first random read command. The third address may be set to address all or some of the memory cells corresponding to the first address of the first NVM110a. The first NVM110amay perform a data output operation912of selecting all or part of data, which is page-read according to the first page read command in response to the first random read command and the third address, and outputting the output data DOUT of the first NVM110a. According to the data output operation912, the output data DOUT of the first NVM110amay be transmitted to the DQ pad P17aand the DQ line700through the output buffer712a.

In operation S840, the memory controller120may receive, through the DQ line700, the output data DOUT output from the first NVM110aaccording to the first page read command and the first random read command.

In operation S842, the memory controller120may perform a data extraction operation on the output data DOUT of the first NVM110areceived through the DQ line700and the DQ pin P27. In the data extraction operation, an internal data signal iDQ corresponding to the output data DOUT of the first NVM110amay be obtained using the data extraction circuit126. The data extraction circuit126may obtain the internal data signal iDQ by selectively outputting the output of the first comparator721and the output of the second comparator722based on the selection signal SEL applied to the selector723. The first comparator721may obtain the output thereof by comparing the voltage level of the output data DOUT applied to the DQ pin P27with the level of the first reference voltage VREF1, and the second comparator722may obtain the output thereof by comparing the voltage level of the output data DOUT with the level of the third reference voltage VREF3.

While receiving the output data DOUT through the DQ line700in operation S840, the memory controller120may perform operation S850in which a second random read command for the second NVM110bis transmitted to the second NVM110bthrough the DQ line700.

In operation S850, the memory controller120may transmit the second random read command to the second NVM110b. The memory controller120may transmit a fourth address to the second NVM110bin addition to the second random read command. The fourth address may be set to address all or some of the memory cells corresponding to the second address of the second NVM110b. The second NVM110bmay perform a data output operation922of selecting all or part of data, which is page-read according to the second page read command in response to the second random read command and the fourth address, and outputting the output data DOUT of the first second NVM110b. According to the data output operation922, the output data DOUT of the second NVM110bmay be transmitted to the DQ pad P17band the DQ line700through the output buffer712b.

In operation S852, the memory controller120may receive, through the DQ line700, the output data DOUT output from the second NVM110baccording to the second page read command and the second random read command.

In operation S854, the memory controller120may perform a data extraction operation on the output data DOUT of the second NVM110breceived through the DQ line700and the DQ pin P27. In the data extraction operation, an internal data signal iDQ corresponding to the output data DOUT of the second NVM110bmay be obtained using the data extraction circuit126.

FIG.11is a timing diagram illustrating data and commands transmitted to the DQ line700of the first channel CH1in the storage device100ofFIG.7. It should be noted that in the timing diagram described below, the horizontal axis and the vertical axis represent time and a voltage level, respectively, and are not drawn to scale.

Referring toFIGS.2,7and11, to perform a read operation, the first NVM110amay receive a read enable signal nRE from the memory controller120through the first channel CH1at time T1. The first NVM110amay generate a data strobe signal DQS according to the read enable signal nRE. The first NVM110amay output data, which is page-read by a page read operation, as the output data DOUT. The output data DOUT may be transmitted to the memory controller120together with the data strobe signal DQS. The first NVM110amay transmit the output data DOUT output by the read operation to the DQ line700of the first channel CH1through the DQ pad P17a.

At time T1, the second NVM110bmay receive a write enable signal nWE through the first channel CH1to receive a command CMD from the memory controller120. The memory controller120may transmit a command CMD having a high voltage level VH to the DQ line700of the first channel CH1through the DQ pin P27by using the second switch SW2turned on by the pull-up signal PU of the command logic circuit123. The command of the high voltage level VH may be output at time T1. The high voltage level VH indicates that the CMD signal bit is logic “1”, and may be set higher than the level of the second reference voltage VREF2. Accordingly, the level of the DQ line700of the first channel CH1may be changed to the high voltage level VH of the command CMD.

Output data DOUT output by a read operation of the first NVM110amay be loaded on the DQ line700of the first channel CH1, and a command CMD transmitted to the second NVM110bmay be loaded on the DQ line700. In other words, both the output data DOUT and the command CMD are loaded on the first channel CH1at the same time. For example, the command CMD transmitted to the second NVM110bmay have a relatively lower transmission rate than the output data DOUT of the first NVM110a. For example, the transmission rate of the command CMD may be set to about ¼ of the transmission rate of the output data DOUT. Accordingly, a command CMD having a low frequency may be embedded in output data DOUT having a high frequency.

The memory controller120may receive, through the DQ pin P27, the output data DOUT of the first NVM110atransmitted to the DQ line700of the first channel CH1, and may obtain an internal data signal iDQ corresponding to the output data DOUT of the first NVM110aby using the data extraction circuit126.

From time T1to time T2, the output data DOUT of the first NVM110amay be loaded on the DQ line700of the first channel CH1at a high voltage level (VH) state of the command CMD. The memory controller120may select the output of the second comparator722based on a selection signal SEL having a logic high level, which is generated by the command logic circuit123, and obtain the selected output of the second comparator722as an internal data signal iDQ. In this case, the second comparator722compares the voltage level of the output data DOUT applied to the DQ pin P27with the level of the third reference voltage VREF3to produce the internal data signal iDQ. The internal data signal iDQ may correspond to the output data DOUT of the first NVM110a. The second NVM110bmay generate, as the internal command iCMD, an output of the input buffer714b, the output of the input buffer714bbeing obtained by comparing a command CMD applied to the DQ pad P17bwith the level of the second reference voltage VREF2. The internal command iCMD may correspond to a CMD signal logic ‘1’ bit of the memory controller120.

At time T2, the memory controller120may transmit a command CMD having a low voltage level VL to the DQ line700of the first channel CH1through the DQ pin P27by using the first switch SW1turned on by the pull-down signal PD of the command logic circuit123. The low voltage level VL indicates that the CMD signal bit is logic “0”, and may be set lower than the level of the second reference voltage VREF2. Accordingly, the level of the DQ line700of the first channel CH1may be changed to the low voltage level V L of the command CMD. In other words, from time T1to time T2, the level of the DQ line700of the first channel CH1may correspond to the high voltage level VM and from time T2to T3, the level of the DQ line700of the first channel CH1may correspond to the low voltage level VL.

From time T2to time T3, the output data DOUT of the first NVM110amay be loaded on the DQ line700of the first channel CH1in a low voltage level (VL) state of the command CMD. The memory controller120may select the output of the first comparator721based on a selection signal SEL having a logic low level, which is generated by the command logic circuit123, and obtain the selected output of the first comparator721as an internal data signal iDQ. In this case, the first comparator721compares the voltage level of the output data DOUT applied to the DQ pin P27with the level of the first reference voltage VREF1to produce the internal data signal iDQ. The internal data signal iDQ may correspond to the output data DOUT of the first NVM110a. The second NVM110bmay generate, as the internal command iCMD, an output of the input buffer714bby comparing the low voltage level VL of a command CMD applied to the DQ pad P17bwith the level of the second reference voltage VREF2. The internal command iCMD may correspond to a CMD signal logic ‘0’ bit of the memory controller120.

At time T3, when the CMD signal bit is logic ‘1’, the memory controller120may transmit a command CMD having the high voltage level VH by the command logic circuit123, the ODT circuit124, and the switch circuit125to the DQ line700of the first channel CH1through the DQ pin P27.

From time T3to time T4, the output data DOUT of the first NVM110amay be loaded on the DQ line700of the first channel CH1in a high voltage level (VH) state of the command CMD. The memory controller120may select the output of the second comparator722based on a selection signal SEL having a logic high level, which is generated by the command logic circuit123, and obtain the selected output of the second comparator722as an internal data signal iDQ. Here, the second comparator722compares the voltage level of the output data DOUT applied to the DQ pin P27with the level of the third reference voltage VREF3to obtain the internal data signal iDQ. The second NVM110bmay generate, as the internal command iCMD, an output of the input buffer714bby comparing a command CMD applied to the DQ pad P17bwith the level of the second reference voltage VREF2.

InFIGS.7to11, the output data DOUT output from the first NVM110aand the command CMD transmitted to the second NVM110bmay be transmitted in both directions of the DQ line700of the first channel CH1. In other words, the output data DOUT and the command CMD may be present on the DQ line700of the first channel CH1at the same time while being transmitted in different directions. More specifically, the voltage level of the DQ line700of the first channel CH1may be changed based on the command CMD for the second NVM110b, and the output data DOUT of the first NVM110amay be loaded on the DQ line700of the first channel CH1having the changed voltage level. According to another embodiment of the inventive concept, the address ADDR of the second NVM110bmay be transmitted to the DQ line700of the first channel CH1instead of the command CMD of the second NVM110b. Accordingly, the voltage level of the DQ line700of the first channel CH1may be changed based on an address ADDR of the second NVM110b, and the output data DOUT of the first NVM110amay be loaded on the DQ line700of the first channel CH1having the changed voltage level. In this case, the address ADDR of the second NVM110bmay have the high voltage level VH and the output data DOUT of the first NVM110amay be loaded on the DQ line700of the high voltage level changed by the address ADDR of the second NVM110b. The output data DOUT of the first NVM110aand the address ADDR of the second NVM110bmay be transmitted in both directions of the DQ line700of the first channel CH1.

FIG.12is a circuit diagram of a storage device100baccording to embodiments of the inventive concept. The storage device100bofFIG.12is different from the storage device100ofFIG.7in that a data extraction circuit126aof a memory controller120is configured as a high pass filter and input buffers714aand714bof first and second NVMs110aand110bare configured as low-pass filters. Hereinafter, descriptions of the storage device100bthat are redundant with those of the storage device100ofFIG.7may be omitted.

Referring toFIGS.11and12, the data extraction circuit126amay receive high frequency components of signals received through a DQ line700and a DQ pin P27and generate internal data iDQ. The data extraction circuit126amay obtain internal data iDQ by filtering, by using a high pass filter, high-frequency output data DOUT output from the first NVM110a. The input buffers714aand714bof the first and second NVMs110aand110bmay respectively receive low frequency components of signals received through the DQ line700and DQ pads P17aand P17band obtain an internal command iCMD. The input buffer714bof the second NVM110bmay obtain the internal command iCMD by filtering a low-frequency command CMD of the memory controller120by using a low pass filter.

FIG.13is a diagram illustrating a read operation of a storage device according to embodiments of the inventive concept.

Referring toFIGS.1and13, a read operation for the first channel CH1of the storage device100may be sequentially performed on the non-volatile memory devices NVM11to NVM1n. The memory controller120may transmit a page read command PAGE RD and a random read command RDM RD to each of the non-volatile memory devices NVM11to NVM1n. For example, the page read command PAGE RD and the random read command RDM RD may be transmitted to the non-volatile memory device NVM11and then to the non-volatile memory device NVM12. The random read command RDM RD may be transmitted after a time tR for which each of the non-volatile memory devices NVM11to NVM1nperforms a page read operation in response to the page read command PAGE RD. Each of the non-volatile memory devices NVM11to NVM1nmay perform a data output operation in response to the random read command RDM RD.

In a first read operation READ1, the random read command RDM RD may be transmitted to the non-volatile memory device NVM12after a time tDMA in which the non-volatile memory device NVM11performs a data output operation in response to the random read command RDM RD, and then, the non-volatile memory device NVM12may perform a data output operation in response to the random read command RDM RD. In the first read operation READ1, data output to the memory controller120takes a time tDOUT1, which corresponds to the sum of an application time tCMD of the random read command RDM RD for each of the non-volatile memory devices NVM11to NVM1nand the time tDMA for performing the data output operation. In the first read operation READ1, the data output operation of the non-volatile memory device NVM12occurs after the data output operation of the non-volatile memory device NVM11.

In comparison, a second read operation READ2in which a random read command for the non-volatile memory device NVM12is transmitted may be performed during the time tDMA for which the non-volatile memory device NVM11described with reference toFIGS.7to12performs a data output operation. In other words, the time in which the random read command for the non-volatile memory device NVM12is transmitted may overlap with the data output operation of the non-volatile memory device NVM11. In the second read operation READ2, data output to the memory controller120takes a time tDOUT2, which corresponds to the sum of an application time tCMD of one random read command RDM RD to the non-volatile memory device NVM11and a time tDMA for performing the data output operation of each of the non-volatile memory devices NVM11to NVM1n. The time tDOUT2is considerably shorter than the time tDOUT1. While in the second read operation READ2the memory controller120receives high-frequency output data of a selected non-volatile memory device among the non-volatile memory devices NVM11to NVM1n, the memory controller120may transmit a low frequency command to another non-volatile memory device among the non-volatile memory devices NVM11to NVM1n, and thus, data input/output efficiency and data transmission speed may be increased.

FIGS.14and15are diagrams illustrating a storage device100caccording to embodiments of the inventive concept. A circuit diagram of the storage device100cofFIG.14is different from that of the storage device100ofFIG.7in that a memory controller120includes a data logic circuit127instead of the command logic circuit123. A timing diagram ofFIG.15is different from that ofFIG.11in that write data DIN input according to a write operation for a second NVM110b, instead of the command CMD that is transmitted to the second NVM110binFIG.11, is loaded on a DQ line700of a first channel CH1. Hereinafter, descriptions of the storage device100athat are redundant with those of the storage device100ofFIG.7may be omitted.

Referring toFIG.14, the data logic circuit127may generate a pull-up signal PU, a pull-down signal PD, and a selection signal SEL according to a bit value (hereinafter, referred to as a DIN bit) of the write data DIN when providing the write data DIN to the second NVM110b. The data logic circuit127may generate the pull-up signal PU when the DIN bit is logic ‘1’, generate the pull-down signal PD when the DIN bit is logic ‘0’, and provide the pull-up signal PU and the pull-down signal PD to a switch circuit125. In addition, the data logic circuit127may generate a selection signal SEL at a logic high level when the DIN bit is logic ‘1’, generate the selection signal SEL at a logic low level when the DIN bit is logic ‘0’, and provide the selection signal SEL to a data extraction circuit126.

The second NVM110bmay receive, through a DQ pad P17band an input buffer714b, the write data DIN provided from the memory controller120to the DQ line700. The input buffer714bmay compare the write data DIN applied to the DQ pad P17bwith the level of a second reference voltage VREF2and obtain internal write data iDIN as a result of the comparison. The input buffer714amay function similarly to the input buffer714b. The second NVM110bmay obtain internal write data iDIN corresponding to the write data DIN of the memory controller120.

Referring toFIG.15, to perform a read operation, a first NVM110amay receive a read enable signal nRE from the memory controller120through the first channel CH1at time Ta, and may generate a data strobe signal DQS according to the read enable signal nRE. The data strobe signal DQS generated by the first NVM110amay be transmitted to a DQS line of the first channel CH1. The first NVM110amay transmit output data DOUT output by a read operation to the DQ line700of the first channel CH1through the DQ pad P17a. The memory controller120may transmit a data strobe signal DQS associated with write data DIN for the second NVM110bto the second NVM110bthrough the DQS line of the first channel CH1. A data strobe signal DQS generated by the first NVM110aand a data strobe signal DQS for the second NVM110bgenerated by the memory controller120may be transmitted through the DQS line of the first channel CH1. A data strobe signal DQS generated by the first NVM110amay be loaded on the DQS line of the first channel CH1at the level of a data strobe signal DQS transmitted to the second NVM110b. For example, from time ta to time tb, the data strobe signal DQS generated by the first NVM110amay be loaded on the DQS line of the first channel CH1at the first level and then the second level. The second NVM110bmay receive a data strobe signal DQS through the first channel CH1to receive the write data DIN from the memory controller120. The memory controller120may transmit write data DIN having a high voltage level VH to the DQ line700of the first channel CH1through the DQ pin P27by using a second switch SW2turned on by the pull-up signal PU of the data logic circuit127. The high voltage level VH indicates that the DIN bit is logic ‘1’, and may be set higher than the level of the second reference voltage VREF2. Accordingly, the level of the DQ line700of the first channel CH1may be changed to the high voltage level VH of the write data DIN.

Output data DOUT output by a read operation of the first NVM110amay be loaded on the DQ line700of the first channel CH1, and write data DIN transmitted to the second NVM110bmay be loaded on the DQ line700. For example, the write data DIN transmitted to the second NVM110bmay have a relatively lower transmission rate than the output data DOUT of the first NVM110a. For example, the transmission rate of the write data DIN may be set to about ¼ of the transmission rate of the output data DOUT. Accordingly, write data DIN having a low frequency may be embedded in output data DOUT having a high frequency.

From time Ta to time Tb, the output data DOUT of the first NVM110amay be loaded on the DQ line700of the first channel CH1in a high voltage level (VH) state of the write data DIN. The memory controller120may select the output of the second comparator722based on a selection signal SEL having a logic high level, which is generated by the data logic circuit127, and obtain the selected output of the second comparator722as an internal data signal iDQ. Here, the second comparator722compares the voltage level of the output data DOUT applied to the DQ pin P27with the level of the third reference voltage VREF3to output the internal data signal iDQ. The second NVM110bmay generate, as an internal data signal iDQ, an output of the input buffer714bby comparing write data DIN applied to the DQ pad P17bwith the level of the second reference voltage VREF2.

At time Tb, the memory controller120may transmit write data DIN having a low voltage level VL to the DQ line700of the first channel CH1through the DQ pin P27by using the first switch SW1turned on by the pull-down signal PD of the data logic circuit127. The low voltage level VL indicates that the DIN bit is logic “0”, and may be set lower than the level of the second reference voltage VREF2. Accordingly, the level of the DQ line700of the first channel CH1may be changed to the low voltage level VL of the write data DIN.

From time Tb to time Tc, the output data DOUT of the first NVM110amay be loaded on the DQ line700of the first channel CH1in a low voltage level (VL) state of the write data DIN. For example, the output data may not exceed the level of the second reference voltage VREF2. The memory controller120may select the output of the first comparator721based on a selection signal SEL having a logic low level, which is generated by the data logic circuit127, and obtain the selected output of the first comparator721as an internal data signal iDQ. Here, the first comparator721compares the voltage level of the output data DOUT applied to the DQ pin P27with the level of the first reference voltage VREF1to output the internal data signal iDQ. The second NVM110bmay generate, as internal write data iDIN, an output of the input buffer714bby comparing the low voltage level VL of write data DIN applied to the DQ pad P17bwith the level of the second reference voltage VREF2.

At time Tc, when the DIN bit is logic ‘1’, the memory controller120may transmit write data DIN having the high voltage level VH by the data logic circuit126, the ODT circuit124, and the switch circuit125to the DQ line700of the first channel CH1through the DQ pin P27.

From time Tc to time Td, the output data DOUT of the first NVM110amay be loaded on the DQ line700of the first channel CH1in a high voltage level (VH) state of the write data DIN. The memory controller120may select the output of the second comparator722based on a selection signal SEL having a logic high level, which is generated by the data logic circuit127, and obtain the selected output of the second comparator722as an internal data signal iDQ. Here, the second comparator722compares the voltage level of the output data DOUT applied to the DQ pin P27with the level of the third reference voltage VREF3to output the internal data signal iDQ. The second NVM110bmay obtain, as internal write data iDIN, an output of the input buffer714bby comparing the low voltage level VL of write data DIN applied to the DQ pad P17bwith the level of the second reference voltage VREF2.

According to an embodiment of the inventive concept, the memory controller120may obtain internal data IDQ by filtering, e.g., using a high pass filter, high-frequency output data DOUT output from the first NVM110a. The input buffer714bof the second NVM110bmay obtain an internal write command iDIN by filtering low-frequency write data DIN of the memory controller120by using a low pass filter.

InFIGS.14and15, while the memory controller120receives high-frequency output data DOUT of the first NVM110a, the memory controller120may transmit low-frequency write data DIN to the second NVM110b, and thus, data input/output efficiency and data transmission speed may be increased.

FIG.16is a diagram illustrating a system1000to which a storage device according to embodiments of the inventive concept is applied. The system1000ofFIG.16may include a mobile system such as a mobile phone, a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet-of-things (IoT) device. However, the system1000ofFIG.16is not limited to the mobile system and may also include a PC, a laptop computer, a server, a media player, or an automotive device such as a navigation device.

Referring toFIG.16, the system1000may include a main processor1100, memories1200aand1200b, and storage devices1300aand1300band may additionally include one or more of an image capturing device1410, a user input device1420, a sensor1430, a communication device1440, a display1450, a speaker1460, a power supplying device1470, and a connecting interface1480. Components of the system1000may be connected to each other via a bus.

The main processor1100may control overall operations of the system1000, and more particularly, may control operations of other components constituting the system1000. The main processor1100may be a general-purpose processor, a dedicated processor, an application processor, or the like.

The main processor1100may include one or more central processing unit (CPU) cores1110and may further include a controller1120for controlling the memories1200aand1200band/or the storage devices1300aand1300b. According to embodiments of the inventive concept, the main processor1100may further include an accelerator block1130, which is a dedicated circuit for high-speed data calculations such as artificial intelligence (AI) data calculations. The accelerator block1130may include a graphics processing unit (GPU), a neural processing unit (NPU), and/or a data processing unit (DPU), and may be implemented by a separate chip that is physically independent of the other components.

The memories1200aand1200bmay be used as a main memory device and may include volatile memory such as SRAM and/or DRAM or may include non-volatile memory such as PRAM and/or RRAM. The memories1200aand1200bmay also be implemented in the same package as the main processor1100.

The storage devices1300aand1300bmay function as non-volatile storage devices storing data regardless of the supply or not of power, and may have relatively larger storage capacities than the memories1200aand1200b. The storage devices1300aand1300bmay include storage controllers1310aand1310b, and non-volatile memory (NVM) storages1320aand1320bstoring data under the control of the storage controllers1310aand1310b, respectively. The NVM storages1320aand1320bmay include V-NAND flash memory having a 2-dimensional (2D) structure or a 3-dimensional (3D) structure or may include another type of non-volatile memory such as PRAM and/or RRAM.

The storage devices1300aand1300bmay be included in the system1000while physically separated from the main processor1100or may be implemented in the same package as the main processor1100. In addition, the storage devices1300aand1300bmay have a form such as a memory card and thus may be detachably coupled to the other components of the system1000through an interface such as the connecting interface1480described below. The storage devices1300aand1300bmay include, but are not limited to, devices to which standard specifications such as UFS are applied.

The image capturing device1410may capture still images or moving images and may include a camera, a camcorder, and/or a webcam.

The user input device1420may receive various types of data input by a user of the system1000and may include a touch pad, a keypad, a keyboard, a mouse, and/or a microphone.

The sensor1430may sense various physical quantities, which may be obtained from outside the system1000, and may convert the sensed physical quantities into electrical signals. The sensor1430may include a temperature sensor, a pressure sensor, a luminance sensor, a position sensor, an acceleration sensor, a biosensor, and/or a gyroscope.

The communication device1440may perform transmission and reception of signals between the system1000and other devices outside the system1000, according to various communication protocols. The communication device1440may include an antenna, a transceiver, and/or a modem.

The display1450and the speaker1460may function as output devices outputting visual information and auditory information to the user of the system1000, respectively.

The power supplying device1470may appropriately convert power supplied by a battery embedded in the system1000and/or by an external power supply and thus supply the converted power to each of the components of the system1000.

The connecting interface1480may provide a connection between the system1000and an external device that is connected to the system1000and capable of exchanging data with the system1000. The connecting interface1480may be implemented by various interfaces such as Advanced Technology Attachment (ATA), Serial ATA (SATA), external SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnection (PCI), PCI express (PCIe), NVM express (NVMe), IEEE 1394, universal serial bus (USB), a secure digital (SD) card interface, a multi-media card (MMC) interface, an eMMC interface, UFS, embedded Universal Flash Storage (eUFS), and a CF card interface.

FIG.17is a diagram illustrating a UFS system2000according to embodiments of the inventive concept. The UFS system2000, which is a system conforming to the UFS standard set forth by the Joint Electron Device Engineering Council (JEDEC), may include a UFS host2100, a UFS device2200, and a UFS interface2300. The above descriptions of the system1000ofFIG.16may also be applied to the UFS system2000ofFIG.17unless conflicting with the following descriptions regardingFIG.17.

Referring toFIG.17, the UFS host2100and the UFS device2200may be connected to each other through the UFS interface2300. When the main processor1100ofFIG.16is an application processor, the UFS host2100may be implemented as a portion of a corresponding application processor. A UFS host controller2110and a host memory2140may respectively correspond to the controller1120and the memories1200aand1200bofFIG.16. The UFS device2200may correspond to the storage devices1300aand1300bofFIG.16, and a UFS device controller2210and NVM storage2220may respectively correspond to the storage controllers1310aand1310band the NVM storages1320aand1320binFIG.16.

The UFS host2100may include the UFS host controller2110, an application2120, a UFS driver2130, the host memory2140, and a UFS interconnect (UIC) layer2150. The UFS device2200may include the UFS device controller2210, the NVM storage2220, a storage interface2230, a device memory2240, a UIC layer2250, and a regulator2260. The NVM storage2220may include a plurality of storage units2221, and each storage unit2221may include V-NAND flash memory having a 2D structure or a 3D structure or may include another type of non-volatile memory such as PRAM and/or RRAM. The UFS device controller2210and the NVM storage2220may be connected to each other through the storage interface2230. The storage interface2230may be implemented to conform to a standard specification such as Toggle or ONFI.

The application2120may refer to a program that intends to communicate with the UFS device2200to use a function of the UFS device2200. The application2120may transmit an input-output request to the UFS driver2130to perform input to and output from the UFS device2200. The input-output request may refer to, but is not limited to, a read request, a write request, and/or a discard request of data.

The UFS driver2130may manage the UFS host controller2110through a UFS-host controller interface (HCI). The UFS driver2130may convert the input-output request generated by the application2120into a UFS command defined by the UFS standard, and may transfer the converted UFS command to the UFS host controller2110. One input-output request may be converted into a plurality of UFS commands. Although a UFS command may be a command defined by the SCSI standard, the UFS command may also be a UFS standard-dedicated command.

The UFS host controller2110may transmit the UFS command converted by the UFS driver2130to the UIC layer2250of the UFS device2200through the UIC layer2150and the UFS interface2300. In this process, a UFS host register2111of the UFS host controller2110may perform a role as a command queue.

The UIC layer2150of the UFS host2100may include MIPI M-PHY2151and MIPI UniPro2152, and the UIC layer2250of the UFS device2200may also include MIPI M-PHY2251and MIPI UniPro2252.

The UFS interface2300may include a line for transmitting a reference clock signal REF_CLK, a line for transmitting a hardware reset signal RESET_n with respect to the UFS device2200, a pair of lines for transmitting a differential input signal pair DIN_T and DIN_C, and a pair of lines for transmitting a differential output signal pair DOUT_T and DOUT_C.

A frequency value of the reference clock signal REF_CLK provided from the UFS host2100to the UFS device2200may be, but is not limited to, one of 19.2 MHz, 26 MHz, 38.4 MHz, and 52 MHz. Even while the UFS host2100is being operated, in other words, even while data transmission and reception between the UFS host2100and the UFS device2200is being performed, the frequency value of the reference clock signal REF_CLK may be changed. The UFS device2200may generate clock signals having various frequencies from the reference clock signal REF_CLK received from the UFS host2100, by using a phase-locked loop (PLL) or the like. In addition, the UFS host2100may also set a value of a data rate between the UFS host2100and the UFS device2200, based on the frequency value of the reference clock signal REF_CLK. In other words, the value of the data rate may be determined according to the frequency value of the reference clock signal REF_CLK.

The UFS interface2300may support a plurality of lanes, and each lane may be implemented by a differential pair. For example, a UFS interface may include one or more reception lanes and one or more transmission lanes. InFIG.17, the pair of lines for transmitting the differential input signal pair DIN_T and DIN_C may constitute a reception lane, and the pair of lines for transmitting the differential output signal pair DOUT_T and DOUT_C may constitute a transmission lane. Although one transmission lane and one reception lane are illustrated inFIG.17, the respective numbers of transmission lanes and reception lanes may be changed.

The reception lane and the transmission lane may transfer data in a serial communication manner, and full-duplex type communication between the UFS host2100and the UFS device2200may be allowed due to a structure in which the reception lane is separated from the transmission lane. In other words, even while receiving data from the UFS host2100through the reception lane, the UFS device2200may transmit data to the UFS host2100through the transmission lane. In addition, control data such as a command from the UFS host2100to the UFS device2200, and user data, which the UFS host2100intends to store in the NVM storage2220of the UFS device2200or to read from the NVM storage2220, may be transferred through the same lane. Accordingly, there is no need to further arrange, between the UFS host2100and the UFS device2200, a separate lane for data transfer, in addition to a pair of reception lanes and a pair of transmission lanes.

The UFS device controller2210of the UFS device2200may take overall control of operations of the UFS device2200. The UFS device controller2210may manage the NVM storage2220through a logical unit (LU)2211, which is a logical data storage unit. The number of LUs2211may be, but is not limited to, 8. The UFS device controller2210may include a flash translation layer (FTL) and, by using address mapping information of the FTL, may convert a logical data address, for example, a logical block address (LBA), which is transferred from the UFS host2100, into a physical data address, for example, a physical block address (PBA). In the UFS system2000, a logical block for storing user data may have a size in a certain range. For example, a minimum size of the logical block may be set to be 4 Kbyte.

When a command from the UFS host2100is input to the UFS device2200through the UIC layer2250, the UFS device controller2210may perform an operation according to the input command, and when the operation is completed, the UFS device controller2210may transmit a completion response to the UFS host2100.

For example, when the UFS host2100intends to store user data in the UFS device2200, the UFS host2100may transmit a data storage command to the UFS device2200. When a response indicative of being ready to receive the user data is received from the UFS device2200, the UFS host2100may transmit the user data to the UFS device2200. The UFS device controller2210may temporarily store the received user data in the device memory2240and, based on the address mapping information of the FTL, may store the user data temporarily stored in the device memory2240in a selected location of the NVM storage2220.

As another example, when the UFS host2100intends to read the user data stored in the UFS device2200, the UFS host2100may transmit a data read command to the UFS device2200. The UFS device controller2210having received the data read command may read the user data from the NVM storage2220, based on the data read command, and may temporarily store the read user data in the device memory2240. In this data read process, the UFS device controller2210may detect and correct an error in the read user data, by using an embedded error correction code (ECC) circuit. In addition, the UFS device controller2210may transmit the user data temporarily stored in the device memory2240to the UFS host2100. Further, the UFS device controller2210may further include an advanced encryption standard (AES) circuit, and the AES circuit may encrypt or decrypt data, which is input to the UFS device controller2210, by using a symmetric-key algorithm.

The UFS host2100may store commands, which are to be transmitted to the UFS device2200, in the UFS host register2111capable of functioning as a command queue according to an order, and may transmit the commands to the UFS device2200in the order. Here, even when a previously transmitted command is still being processed by the UFS device2200, in other words, even before the UFS host2100receives a notification indicating that processing of the previously transmitted command is completed by the UFS device2200, the UFS host2100may transmit the next command on standby in the command queue to the UFS device2200, and thus, the UFS device2200may also receive the next command from the UFS host2100even while processing the previously transmitted command. The maximum number of commands capable of being stored in the command queue (in other words, a queue depth) may be, for example, 32. In addition, the command queue may be implemented by a circular queue type in which a start and an end of a command sequence stored in a queue are respectively indicated by a head pointer and a tail pointer.

Each of the plurality of storage units2221may include a memory cell array and a control circuit for controlling an operation of the memory cell array. The memory cell array may include a 2D memory cell array or a 3D memory cell array. The memory cell array may include a plurality of memory cells, and each memory cell may be a single level cell (SL) storing 1 bit of information or may be a cell storing 2 or more bits of information, such as a multi-level cell (MLC), a triple level cell (TLC), or a quadruple level cell (QLC). The 3D memory cell array may include a vertical NAND string vertically oriented such that at least one memory cell is located on another memory cell.

VCC, VCCQ1, VCCQ2, or the like may be input as a power supply voltage to the UFS device2200. VCC, which is a main power supply voltage for the UFS device2200, may have a value of about 2.4 V to about 3.6 V. VCCQ1, which is a power supply voltage for supplying a voltage in a low-voltage range, is mainly for the UFS device controller2210and may have a value of about 1.14 V to about 1.26 V. VCCQ2, which is a power supply voltage for supplying a voltage in a range higher than VCCQ1and lower than VCC, is mainly for an input-output interface such as the MIPI M-PHY2251and may have a value of about 1.7 V to about 1.95 V. The power supply voltages set forth above may be supplied for the respective components of the UFS device2200through the regulator2260. The regulator2260may be implemented by a set of unit regulators respectively connected to different ones of the power supply voltages set forth above.

In an embodiment of the inventive concept, when, for example, the memory controller transmits a read command to another non-volatile memory through the shared DQ line while receiving the output data of a selected non-volatile memory through the shared DQ line, simultaneously and in both directions of the channel, data input/output efficiency of the storage device may be increased to thereby improve data transmission performance.

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made thereto without departing from the spirit and scope of the inventive concept as set forth in the following claims.