Patent ID: 12230633

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The present disclosure is directed to, but not otherwise limited to, a fin-like field-effect transistor (FinFET) device. The FinFET device, for example, may be a complementary metal-oxide-semiconductor (CMOS) device including a P-type metal-oxide-semiconductor (PMOS) FinFET device and an N-type metal-oxide-semiconductor (NMOS) FinFET device. The following disclosure will continue with one or more FinFET examples to illustrate various embodiments of the present disclosure. It is understood, however, that the application should not be limited to a particular type of device, except as specifically claimed.

The use of FinFET devices has been gaining popularity in the semiconductor industry. Referring toFIG.1, which illustrates a perspective view of an example FinFET device50. The FinFET device50is a non-planar multi-gate transistor that is built over a substrate (such as a bulk substrate). A thin silicon-containing “fin-like” structure (hereinafter referred to as a “fin”) forms the body of the FinFET device50. The fin extends along an X-direction shown inFIG.1. The fin has a fin width Wfin, measured along a Y-direction that is orthogonal to the X-direction. In some embodiments, the fin width Wfin, of the fin may be defined as a width of the top surface of the fin measured along the Y-direction. A gate60of the FinFET device50wraps around this fin, for example around the top surface and the opposing sidewall surfaces of the fin. Thus, a portion of the gate60is located over the fin in a Z-direction that is orthogonal to both the X-direction and the Y-direction.

LGdenotes a length (or width, depending on the perspective) of the gate60measured in the X-direction. The gate60may include a gate electrode component60A and a gate dielectric component60B. The gate dielectric60B has a thickness toxmeasured in the Y-direction. A portion of the gate60is located over a dielectric isolation structure such as shallow trench isolation (STI). A source70and a drain80of the FinFET device50are formed in extensions of the fin on opposite sides of the gate60. A portion of the fin being wrapped around by the gate60serves as a channel of the FinFET device50. The effective channel length of the FinFET device50is determined by the dimensions of the fin.

FIG.2illustrates a diagrammatic cross-sectional side view of FinFET transistors in a CMOS configuration. The CMOS FinFET includes a substrate, for example a silicon substrate. An N-type well and a P-type well are formed in the substrate. A dielectric isolation structure such as a shallow trench isolation (STI) is formed over the N-type well and the P-type well. A P-type FinFET90is formed over the N-type well, and an N-type FinFET91is formed over the P-type well. The P-type FinFET90includes fins95that protrude upwardly out of the STI, and the N-type FinFET91includes fins96that protrude upwardly out of the STI. The fins95include the channel regions of the P-type FinFET90, and the fins96include the channel regions of the N-type FinFET91. In some embodiments, the fins95are comprised of silicon germanium, and the fins96are comprised of silicon. A gate dielectric is formed over the fins95-96and over the STI, and a gate electrode is formed over the gate dielectric. In some embodiments, the gate dielectric includes a high-k dielectric material, and the gate electrode includes a metal gate electrode, such as aluminum and/or other refractory metals. In some other embodiments, the gate dielectric may include SiON, and the gate electrode may include polysilicon. A gate contact is formed on the gate electrode to provide electrical connectivity to the gate.

FinFET devices offer several advantages over traditional Metal-Oxide Semiconductor Field Effect Transistor (MOSFET) devices (also referred to as planar transistor devices). These advantages may include better chip area efficiency, improved carrier mobility, and fabrication processing that is compatible with the fabrication processing of planar devices. Thus, it may be desirable to design an integrated circuit (IC) chip using FinFET devices for a portion of, or the entire IC chip.

As illustrated inFIG.3, which illustrates a top view of a layout100A corresponding to a semiconductor device100according to some embodiments of the present disclosure. The semiconductor device100includes a first circuit102and a second circuit104. As shown in layout100A, the first circuit102and the second circuit104are spaced from each other by a region106which includes, for example, an isolation structure. In some embodiments, the first circuit102may be used in an input/output (I/O) device of the semiconductor device100, and the second circuit104may be used in a core device of the semiconductor device100.

The first circuit102includes a plurality of a first active area region111with fins112,114,116,118, a second active area region121with fins122,124,126, and128, a plurality of gate electrodes130,132, a plurality of spacers134,136138,140, and a plurality of contact areas142,144,146,148.

The first and second active area regions111and121extend along a Y-direction of the layout100A. The Y-direction of the layout100A can be referred to as the X-direction ofFIG.1. In some embodiments, the first and second active area regions111and121are also referred to as oxide-definition (OD) regions. Example materials of the first and second active area regions111and121include, but are not limited to, semiconductor materials doped with various types of p-dopants and/or n-dopants. In some embodiments, the first and second active area regions111and121include dopants of the same type. In some embodiments, one of the first and second active area regions111and121includes dopants of a type different from a type of dopants of another one of the first and second active area regions111and121. The first and second active area regions111and121are isolated from each other by one or more isolation structures as described herein. The first and second active area regions111and121are within corresponding well regions. For example, the first active area region111is within a well region110which is an n-well region in one or more embodiments, and the second active area region121is within a well region120which is a p-well region in one or more embodiments. The described conductivity of the well regions110and120is an example. Other arrangements are within the scope of various embodiments.

The n-well region110and the p-well region120are on opposite sides of an imaginary line108A which divides the semiconductor device into separate regions for different types of devices or transistors. Examples of transistors include, but are not limited to, metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), FinFETs, planar MOS transistors with raised source/drains, or the like. In the example configuration inFIG.3, the n-well region110is a region for forming p-channel metal-oxide semiconductor (PMOS) transistors, and the p-well region120is a region for forming n-channel metal-oxide semiconductor (NMOS) transistors. Each of the first and second active area regions111and121includes one or more fins to form FinFETs as described inFIGS.1and2. For example, the first active area region111comprises the four fins112,114,116,118and the second active area region121comprises the four fins122,124,126,128. The fins112,114,116,118,122,124,126,128are isolated from each other by one or more isolation structures as described herein. Other numbers of fins in each of the first and second active area regions111and121are within the scope of various embodiments. The described FinFET configuration is an example. Other arrangements are within the scope of various embodiments. For example, in one or more embodiments, the first and second active area regions111and121may not include fins and are configured for forming planar MOSFET transistors.

The fins112,114,116,118,122,124,126,128are extend in an elongated manner in the Y-direction. In some embodiments, the fins112,114,116,118are parts of the PMOSFET, and the fins122,124,126,128are parts of the NMOSFET. The PMOSFET fins112,114,116,118are located over the n-well region110, whereas the NMOSFET fins122,124,126,128are located over the p-well region120. In some embodiments, the PMOSFET fins112,114,116,118comprise a silicon germanium (SiGe) material (for strain effect enhancement), but the NMOSFET fins122,124,126,128comprise a non-germanium-containing semiconductor material, for example Si.

In some embodiment, at least one of the fins112,114,116,118of the first active area region111and the fins122,124,126128of the second active area region121has a first width measured along the X-direction as described with respect to the fin width Wfin, inFIG.1. For example, the fin118of the first active area region111has the first width W1 measured along the X-direction. In some embodiments, a pair of the adjacent fins of the first and second active area regions111and121are spaced from each other by a first spacing measured along the X-direction. For example, the adjacent fins122and124are spaced from each other by the first spacing S1. The first spacing S1 can be referred to as a distance that is measured along the X-direction and between boundaries of the adjacent fins122and124. For example, a distance measured along the X-direction from one side (e.g., the right side inFIG.3) of the boundary of the fin122to the opposite side (e.g., the left side inFIG.3) of the boundary of the fin124is equal to the first spacing S1.

In some embodiments, the fins of the first and second active area regions111and121can be arranged along the X-direction by a first pitch, which can be defined by a sum of the first width and the first spacing. In some embodiments, the first pitch is equal to a sum of the first width W1 of the fin118and the first spacing between the boundaries of the adjacent fins116and118, and thus the first pitch is equal to a distance X1 measured along the X-direction from one side (e.g., the right side inFIG.3) of the boundary of the fin116to the same side (e.g., the right side inFIG.3) of the boundary of the fin118. In some embodiments, the first pitch is equal to a sum of the first width of the fin122and the first spacing between the boundaries of the adjacent fins122and124, and thus the first pitch is equal to a distance X1′ measured along the X-direction from one side (e.g., the left side inFIG.3) of the boundary of the fin122to the same side (e.g., the left side inFIG.3) of the boundary of the fin124. Accordingly, in some embodiments, either the distance X1 or the distance X1′ can be referred to as the first pitch, and the fins of the first and second active area regions111and121are arranged along the X-direction by the first pitch.

The gate electrodes130and132extend along an X-direction of the layout100. The X-direction of the layout100A can be referred to as the Y-direction ofFIG.1. The gate electrodes130and132are across first and second active area regions111and121. Example materials of the gate electrodes130and132include, but are not limited to, polysilicon and metal. Other materials are within the scope of various embodiments. The gate electrodes130and132and the corresponding first and second active area regions111and121form one or more transistors in the layout100A. In the example configuration inFIG.3, a transistor may be formed by the gate electrode132and the first active area region111. In some embodiments, such transistor having a gate, a drain, and a source is formed in the first circuit102. For example, the gate of the transistor is formed by the gate electrode132. One of the drain or the source (referred to herein as “source/drain” or “S/D”) of the transistor is defined by a region of the first active area region111on one side (e.g., the upper side inFIG.3) of the gate electrode132. The other source/drain of the transistor may be defined by another region of the first active area region111on the opposite side (e.g., the lower side inFIG.3) of the gate electrode132. For another example, a further transistor may be formed by the gate electrode132and the second active area region121. In at least one embodiment, such further transistors are formed by the gate electrode130and the corresponding first and second active area regions111and121. One or more of the gate electrodes130and132are coupled to other circuitry of the semiconductor device by corresponding gate contacts. For example, gate contacts may be formed on the corresponding gate electrodes130and132and configured to electrically couple to the corresponding gate electrodes130and132to other circuitry. Furthermore, at least one of the gate electrodes130and132has a first gate length L1 along a longitudinal direction of at least one of the first fins112-118,122-128(i.e., the Y-direction of the layout100A), as depicted inFIG.3.

The spacers134,136,138,140are arranged along sides of the corresponding gate electrodes130and132. For example, the spacers134and136are arranged along longitudinal sides of the gate electrode130in the X direction, and the spacers138and140are arranged along longitudinal sides of the gate electrode132. The spacers134,136,138,140include one or more dielectric materials for electrically isolating the corresponding gate electrodes from unintended electrical contact. Example dielectric materials of the spacers include, but are not limited to, silicon nitride, oxynitride and silicon carbide. In at least one embodiment, one or more of the spacers134,136,138,140may have a tapered profile as described herein.

The contact areas142,144,146,148overlap the corresponding first and second active area regions111and121. For example, the contact areas142,146overlap the first active area region111, and the contact areas144,148overlap the second active area region121. The contact areas142,144,146,148are configured to electrically couple the underlying source/drains of the corresponding transistors with each other or with other circuitry of the semiconductor device100.

In the example configuration inFIG.3, the boundaries of one or more of the contact areas142,144,146,148are spaced from boundaries of the spacers134,136,138,140. For example, an upper edge of the contact area142is spaced in the Y-direction from an adjacent lower edge of the spacer136, and a lower edge of the contact area142is spaced in the Y-direction from an adjacent upper edge of the spacer138. Other arrangements are within the scope of various embodiments. For example, in one or more embodiments, one or more of the contact areas are self-aligned contacts (SAC) having boundaries defined at least partially by the boundaries of the spacers134,136,138,140.

The second circuit104includes a plurality of a third active area region151with fins152,154,156,158, a fourth active area region161with fins162,164,166, and168, a plurality of gate electrodes170,172, a plurality of spacers174,176178,180, and a plurality of contact areas182,184,186,188,190,192.

The third and fourth active area regions151and161extend along the Y-direction of the layout100A. In some embodiments, the third and fourth active area regions151and161are also referred to as OD regions. Example materials of the third and fourth active area regions151and161include, but are not limited to, semiconductor materials doped with various types of p-dopants and/or n-dopants. In some embodiments, the third and fourth active area regions151and161include dopants of the same type. In some embodiments, one of the third and fourth active area regions151and161includes dopants of a type different from a type of dopants of another one of the third and fourth active area regions151and161. The third and fourth active area regions151and161are isolated from each other by one or more isolation structures as described herein. The third and fourth active area regions151and161are within corresponding well regions. For example, the third active area region151is within a well region150which is an n-well region in one or more embodiments, and the fourth active area region161is within a well region160which is a p-well region in one or more embodiments. The described conductivity of the well regions150and160is an example. Other arrangements are within the scope of various embodiments.

The n-well region150and the p-well region160are on opposite sides of an imaginary line108B which divides the semiconductor device into separate regions for different types of devices or transistors. Examples of transistors include, but are not limited to, MOSFET, CMOS transistors, BJT, high voltage transistors, high frequency transistors, PFETs and/or NFETs, FinFETs, planar MOS transistors with raised source/drains, or the like. In the example configuration inFIG.3, the n-well region150is a region for forming PMOS transistors, and the p-well region160is a region for forming NMOS transistors. Each of the third and fourth active area regions151and161includes one or more fins to form FinFETs as described inFIGS.1and2. For example, the third active area region151comprises the four fins152,154,156,158and the fourth active area region161comprises the four fins162,164,166,168. The fins152,154,156,158,162,164,166,168are isolated from each other by one or more isolation structures as described herein. Other numbers of fins in each of the third and fourth active area regions151and161are within the scope of various embodiments. The described FinFET configuration is an example. Other arrangements are within the scope of various embodiments. For example, in one or more embodiments, the third and fourth active area regions151and161may not include fins and are configured for forming planar MOSFET transistors.

The fins152,154,156,158,162,164,166,168are extend in an elongated manner in the Y-direction. In some embodiments, the fins152,154,156,158are parts of the PMOSFET, and the fins162,164,166,168are parts of the NMOSFET. The PMOSFET fins152,154,156,158are located over the n-well region150, whereas the NMOSFET fins162,164,166,168are located over the p-well region160. In some embodiments, the PMOSFET fins152,154,156,158comprise a silicon germanium (SiGe) material (for strain effect enhancement), but the NMOSFET fins162,164,166,168comprise a non-germanium-containing semiconductor material, for example Si.

In some embodiment, at least one of the fins152,154,156,158of the third active area region151and the fins162,164,166168of the fourth active area region161has a second width measured along the X-direction as described with respect to the fin width Wfin, inFIG.1. For example, the fin158of the third active area region151has the second width W2 measured along the X-direction. In some embodiments, a pair of the adjacent fins of the third and fourth active area regions151and161are spaced from each other by a second spacing measured along the X direction. For example, the adjacent fins162and164are spaced from each other by the second spacing S2. The second spacing S2 can be referred to as a distance that is measured along the X-direction and between boundaries of the adjacent fins162and164. For example, a distance measured along the X-direction from one side (e.g., the right side inFIG.3) of the boundary of the fin162to the opposite side (e.g., the left side inFIG.3) of the boundary of the fin164is equal to the second spacing S2.

In some embodiments, the fins of the third and fourth active area regions151and161can be arranged along the X-direction by a second pitch, which can be defined by a sum of the second width and the second spacing. In some embodiments, the second pitch is equal to a sum of the second width W2 of the fin158and the second spacing between the boundaries of the adjacent fins156and158, and thus the second pitch is equal to a distance X2 measured along the X-direction from one side (e.g., the right side inFIG.3) of the boundary of the fin156to the same side (e.g., the right side inFIG.3) of the boundary of the fin158. In some embodiments, the second pitch is equal to a sum of the second width of the fin162and the second spacing between the boundaries of the adjacent fins162and164, and thus the second pitch is equal to a distance X2′ measured along the X-direction from one side (e.g., the left side inFIG.3) of the boundary of the fin162to the same side (e.g., the left side inFIG.3) of the boundary of the fin164. Accordingly, in some embodiments, either the distance X2 or the distance X2′ can be referred to as the second pitch, and the fins of the third and fourth active area regions151and161are arranged along the X-direction by the second pitch.

The gate electrodes170and172extend along the X-direction of the layout100A and are across the third and fourth active area regions151and161. Example materials of the gate electrodes170and172include, but are not limited to, polysilicon and metal. Other materials are within the scope of various embodiments. The gate electrodes170and172and the corresponding third and fourth active area regions151and161form one or more transistors in the layout100A. In the example configuration inFIG.3, a transistor may be formed by the gate electrode172and the third active area region151. In some embodiments, such transistor having a gate, a drain, and a source is formed in the second circuit104. The gate of the transistor is formed by the gate electrode172. One of the drain or the source (referred to herein as “source/drain” or “S/D”) of the transistor is defined by a region of the third active area region151on one side (e.g., the upper side inFIG.3) of the gate electrode172. The other source/drain of the transistor is defined by another region of the third active area region151on the opposite side (e.g., the lower side inFIG.3) of the gate electrode172. For another example, a further transistor may be formed by the gate electrode172and the fourth active area region161. In at least one embodiment, further transistors are formed by the gate electrode170and the corresponding third and fourth active area regions151and161. One or more of the gate electrodes170and172are coupled to other circuitry of the semiconductor device by corresponding gate contacts. For example, gate contacts may be formed on the corresponding gate electrodes170and172and configured to electrically couple to the corresponding gate electrodes170and172to other circuitry. Furthermore, at least one of the gate electrodes170and172has a second gate length L2 along a longitudinal direction of at least one of the second fins152-158,162-168(i.e., the Y-direction of the layout100A), as depicted inFIG.3. In some embodiments, a ratio of the first gate length L1 to the second gate length L2 is greater than 2. In some embodiments, a ratio of the first gate length L1 to the second gate length L2 is in a range from 2 to 20. In some embodiments, a center-to-center distance or spacing in the Y-direction between the gate electrodes170and172is less than a center-to-center distance or spacing in the Y-direction between the gate electrodes130and132.

The spacers174,176,178,180are arranged along sides of the corresponding gate electrodes170and172. For example, the spacers174and176are arranged along longitudinal sides of the gate electrode170in the X direction, and the spacers178and180are arranged along longitudinal sides of the gate electrode172. The spacers174,176,178,180include one or more dielectric materials for electrically isolating the corresponding gate electrodes from unintended electrical contact. Example dielectric materials of the spacers include, but are not limited to, silicon nitride, oxynitride and silicon carbide. In at least one embodiment, one or more of the spacers174,176,178,180have a tapered profile as described herein.

The contact areas182,184,186,188,190,192overlap the corresponding third and fourth active area regions151and161. For example, the contact areas182,186,190overlap the third active area region151, and the contact areas184,188,192overlap the fourth active area region161. The contact areas182,184,186,188,190,192are configured to electrically couple the underlying source/drains of the corresponding transistors with each other or with other circuitry of the semiconductor device100.

In the example configuration inFIG.3, boundaries of one or more of the contact areas182,184,186,188,190,192are spaced from boundaries of the spacers174,176,178,180. For example, an upper edge of the contact area186is spaced in the Y direction from an adjacent lower edge of the spacer176, and a lower edge of the contact area186is spaced in the Y direction from an adjacent upper edge of the spacer178. Other arrangements are within the scope of various embodiments. For example, in one or more embodiments, one or more of the contact areas are SAC having boundaries defined at least partially by boundaries of the spacers174,176,178,180.

Reference is made toFIGS.4and5.FIG.4is a cross-section view taken along line4-4inFIG.3.FIG.5is a cross-section view taken along line5-5inFIG.3. The configuration of the semiconductor device is described herein with respect to bothFIGS.4and5. The structures shown inFIGS.4and5can be formed by modelling in a layout as depicted inFIG.3, and then physical elements or layers are formed by using the gate electrode and the gate contact as patterns.

As illustrated inFIGS.4and5, the semiconductor device100comprises a substrate202over which various elements of the semiconductor device100are formed. The elements of the semiconductor device100include active elements and/or passive elements. In at least one embodiment, active elements are arranged in a circuit region of the semiconductor device to provide one or more functions and/or operations intended to be performed by the semiconductor device. In at least one embodiment, the semiconductor device further comprises a non-circuit region, e.g., a sealing region that extends around and protects the circuit region. Examples of active elements include, but are not limited to, transistors and diodes. Examples of transistors are described herein with respect toFIG.3. Examples of passive elements include, but are not limited to, capacitors, inductors, fuses, and resistors. A plurality of metal layers and via layers are alternatingly formed over the substrate202to electrically couple the elements of the semiconductor device100with each other and/or with external devices. The substrate202comprises, in at least one embodiment, a silicon substrate. The substrate202comprises, in at least one embodiment, silicon germanium (SiGe), Gallium arsenic, P-type doped Si, N-type doped Si, or suitable semiconductor materials. For example, semiconductor materials including group III, group IV, and group V elements are within the scope of various embodiments. In some embodiments, the substrate202further includes one or more other features, such as various doped regions, a buried layer, and/or an epitaxy (epi) layer. In some embodiments, the substrate202comprises a semiconductor on insulator, such as silicon on insulator (SOI). In some embodiments, the substrate202includes a doped epi layer, a gradient semiconductor layer, and/or a semiconductor layer overlying another semiconductor layer of a different type such as a silicon layer on a silicon germanium layer.

The semiconductor device100further comprises one or more well regions over the substrate202. In the example configuration inFIG.4, the n-well region110and p-well region120are over the substrate202, as described with respect toFIG.3. In the example configuration inFIG.5, the n-well region150and p-well region160are over the substrate202, as described with respect toFIG.3.

The semiconductor device100further comprises one or more isolation structures over and around the well regions110,120,150,160. In the example configuration inFIGS.4and5, the isolation structure204A is over the well regions110,120, and the isolation structure204B is over the well regions150,160. The isolation structures204A and204B electrically isolate various elements of the semiconductor device100from each other. For example, as illustrated inFIG.4, the isolation structure204A electrically isolates the fins112,114,116,118in the first active area region111from the fins122,124,126,128in the second active area region121. Similarly, as illustrated inFIG.5, the isolation structure204B electrically isolates the fins152,154,156,158in the third active area region151from the fins162,164,166,168in the fourth active area region161. In some embodiments, in the cross-section inFIGS.4and5, at least one of the isolation structures204A,204B may have a thickness less than at least one of the fins112-118,122-128,152-158,162-168. In some embodiments, outside the cross-section shown inFIGS.4and5, at least one of the isolation structures204A,204B may include regions where the thickness thereof is higher than at least one of the corresponding fins112-118,122-128,152-158,162-168. In at least one embodiment, at least one of the isolation structures204A,204B comprises one or more shallow trench isolation (STI) regions. Example materials of the STI regions include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate, and/or any other low k dielectric materials. In some embodiments, the STI thickness is from 50 nm to 200 nm. In some embodiments, the isolation structures204A,204B may have the sane or different materials.

The semiconductor device100further comprises active area regions, gate electrodes, and corresponding spacers over the isolation structure. In the example configuration inFIGS.4and5, the semiconductor device100further comprises the first, second, third, fourth active area regions111,121,151,161, the gate electrodes132,172, and corresponding spacers206,208,210,212over the corresponding isolation structures204A and204B. Other arrangements are within the scope of various embodiments. For example, in one or more embodiments, the gate electrodes132,172, and/or one or more of the corresponding spacers206,208,210,212are partially embedded in the corresponding isolation structures204A and204B.

In some embodiments, the semiconductor device100further comprises an inter-layer dielectric (ILD) layer214over the isolation structures204A,204B. Example materials of the ILD layer214include, but are not limited to, SiNx, SiOx, SiON, SiC, SiBN, SiCBN, or combinations thereof. The ILD layer214embeds therein the gate electrodes132,172and/or the corresponding spacers206,208,210,212. The ILD layer214further embeds therein the fins112-118,122-128,152-158,162-168of the first, second, third, fourth active area regions111,121,151,161and the contact plugs in the corresponding contact areas142,144,146,148,182,184,186,188,190,192ofFIG.3.

In the example configuration inFIG.4, the gate electrode132wraps over the fins112-118and122-128of the first and second active area regions111,121in regions where the gate electrode132crosses over the fins112-118and122-128. The spacers206,208may adhere to opposite sidewalls of the gate electrode132. To electrically isolate the gate electrode132from the fins112-118and122-128, a first gate dielectric layer216is arranged under and around the gate electrode132, in which the fins112-118and122-128are covered by the gate dielectric layer216. The spacers138,140ofFIG.3may be over opposite sides of the first gate dielectric layer216. Example materials of the gate dielectric layer include, but are not limited to, a high-k dielectric layer, an interfacial layer, and/or combinations thereof. Example materials for the high-k dielectric layer include, but are not limited to, silicon nitride, silicon oxynitride, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, suitable high-k dielectric materials, and/or combinations thereof. In at least one embodiment, a gate dielectric layer includes multi-layer structure of, for example, SiO2with a high-k dielectric, or SiON with a high-k dielectric.

In the example configuration inFIG.4, the gate electrode132is wrapped over the fins112-118and122-128, and includes a first conductive gate material over the n-well region110and a second conductive gate material over the p-well region120. In at least one embodiment, the conductive gate materials include the same conductive material. In at least one embodiment, the conductive gate materials include different conductive materials. In at least one embodiment, the conductive material or materials of at least one of the conductive gate materials is/are selected in accordance with the type of device or transistor. For example, each of the first and second conductive gate materials includes a first conductive work function layer and a first contact layer over the first conductive work function layer.

In at least one embodiment, the first work function layer is configured to have a first work function in a range from 4 eV to 5 eV. In some embodiments, the first conductive gate material includes a p-type work function metal (p-metal) for forming a PMOS over the n-well region110. Example p-metals include, but are not limited to, TiN, TaN, a carbon-doped metal nitride such as TaCN. In some embodiments, the second conductive gate material includes an n-type work function metal (n-metal) for forming an NMOS over the p-well region120. Example n-metals include, but are not limited to, Ta, TiAl, and TiAlN. Other work function materials are within the scope of various embodiments. For example, in one or more embodiments, the first work function layer comprises doped conducting oxide materials, TaAl, TiSi, NiSi, PtSi, suitable Ti containing work function materials, suitable Ta containing work function materials, suitable Al containing work function materials, and suitable W containing work function materials.

In at least one embodiment, the first contact layer over the first conductive work function layer is configured to have a low contact resistance. Example materials of the first contact layer include, but are not limited to, polysilicon with silicide, refractory materials such as TiN, TaN, TiW, and TiAl, suitable Ti containing work function materials, suitable Ta containing work function materials, suitable Al containing work function materials, suitable W containing work function materials, suitable Cu containing work function materials, and suitable N containing work function materials.

The first conductive gate material and the second conductive gate material are isolated from the fins112-118and122-128by the first gate dielectric layer216over the n-well region110and the p-well region120. In at least one embodiment, the first gate dielectric layer216has a first portion over the n-well region110and a second portion over the p-well region120. In some embodiments, the first and second portions of the first gate dielectric layer216include the same dielectric material. In some embodiments, the first and second portions of the first gate dielectric layer216include different dielectric materials. In some embodiments, the gate electrode132extends continuously from the n-well region110into the p-well region120, and the first conductive gate material is in contact with the second conductive gate material. Other arrangements are within the scope of various embodiments. For example, in at least one embodiment, at least one of the first and second portions of the first gate dielectric layer216is interposed between and electrically isolates the first and second conductive gate materials. In at least one embodiment, at least one of the first and second portions of the first gate dielectric layer216includes one or more of HfO2, Ta2O5and Al2O3.

In at least one embodiment, the first work function layer, the first contact layer and the first gate dielectric layer configure a gate stack structure. Examples of gate stack structures include, but are not limited to, a metals/high-K dielectric structure, an Al/refractory metals/high-K dielectric structure, a W/refractory metals/high-K dielectric structure, a Cu/refractory metals/high-K dielectric structure, and a silicide/high-K dielectric structure. In at least one embodiment, the gate stack structure includes a Si3N4/metals/high-K dielectric structure in which the metals are selected from the group consisting of Al/refractory metals, W/refractory metals, Cu/refractory metals, silicide, and combinations thereof.

In the example configuration inFIG.5, the gate electrode172wraps over the fins152-158and160-168of the third and fourth active area regions150,160in regions where the gate electrode172crosses over the fins152-158and160-168. The spacers210,212may adhere to opposite sidewalls of the gate electrode172. To electrically isolate the gate electrode172from the fins152-158and160-168, a second gate dielectric layer218is arranged under and around the gate electrode172. The spacers178,180ofFIG.3may be over opposite sides of the second gate dielectric layer218. Example materials of the second gate dielectric layer218may be similar to those of the first gate dielectric layer216.

In the example configuration inFIG.5, the gate electrode172is wrapped over the fins152-158and160-168, and includes a first conductive gate material over the n-well region150and a second conductive gate material over the p-well region160, which are similar to those of the gate electrode132. Similarly, the conductive material or materials of at least one of the conductive gate materials of the gate electrode172is/are selected in accordance with the type of device or transistor. For example, each of the first and second conductive gate materials the gate electrode172includes a second conductive work function layer and a second contact layer over the second conductive work function layer. Properties and configurations of the second conductive work function layer and the second contact layer of the gate electrode172may be similar to those of the first conductive work function layer and the first contact layer of the gate electrode132.

The first conductive gate material and the second conductive gate material are isolated from the fins152-158and162-168by the second gate dielectric layer218over the n-well region150and the p-well region160. In at least one embodiment, the second gate dielectric layer218has a first portion over the n-well region150and a second portion over the p-well region160. In some embodiments, the first and second portions of the second gate dielectric layer218include the same dielectric material. In some embodiments, the first and second portions of the second gate dielectric layer218include different dielectric materials. In some embodiments, the gate electrode172extends continuously from the n-well region150into the p-well region160, and the first conductive gate material of the gate electrode172is in contact with the second conductive gate material of the gate electrode172. Other arrangements are within the scope of various embodiments. For example, in at least one embodiment, at least one of the first and second portions of the of the second gate dielectric layer218is interposed between and electrically isolates the first and second conductive gate materials of the gate electrode172. In at least one embodiment, at least one of the first and second portions of the of the second gate dielectric layer218includes one or more of HfO2, Ta2O5and Al2O3.

In at least one embodiment, the second work function layer, the second contact layer and the second gate dielectric layer configure a gate stack structure. Examples of gate stack structures include, but are not limited to, a metals/high-K dielectric structure, an Al/refractory metals/high-K dielectric structure, a W/refractory metals/high-K dielectric structure, a Cu/refractory metals/high-K dielectric structure, and a silicide/high-K dielectric structure. In at least one embodiment, the gate stack structure includes a Si3N4/metals/high-K dielectric structure in which the metals are selected from the group consisting of Al/refractory metals, W/refractory metals, Cu/refractory metals, silicide, and combinations thereof.

Reference is made toFIG.4. Each of the fins112-118and122-128of the first and second active area regions111,121has the first width as depicted inFIG.3. For example, the top surface of the fin118of the first active area region111has the first width W1 measured along an X-direction ofFIG.4(i.e., the X-direction ofFIG.3). Either a pair of the adjacent fins112-118of the first active area region111or a pair of the adjacent fins122-128of the second active area region121are spaced from each other by the first spacing in the X direction, as depicted inFIG.3. For example, the adjacent fins122and124are spaced from each other by the first spacing S1, in which the first spacing S1 can be referred to as a distance that is measured from one side (e.g., the right side inFIG.4) of the boundary of the top surface of the fin122and the opposite side (e.g., the left side inFIG.4) of the boundary of the top surface of the fin124. Similarly, in either of the first active area region111or the second active area region121, the fins can be arranged along the X-direction by the first pitch, as depicted inFIG.3. The first pitch can be defined by the sum of the first width and the first spacing. For example, the fins116,118of the first active area region111are arranged along the X-direction by the distance X1, and the fins122,124of the second active area region121are arranged along the X-direction by the distance X1′ which is equal to the distance X1. Furthermore, the first gate dielectric layer216covering the fins112-118and122-128has a first thickness T1. In some embodiments, the first thickness T1 of the first gate dielectric layer216can be referred to as a height thereof measured from the top surface of one of the fins112-118and122-128. For example, the first thickness T1 of the first gate dielectric layer216can be referred to as a distance from the top surface of the fin112to the top surface of the first gate dielectric layer216.

Reference is made toFIG.5. Each of the fins152-158and162-168of the third and fourth active area regions151,161has the second width as depicted inFIG.3. For example, the top surface of the fin158of the third active area region151has the second width W2 measured along an X-direction ofFIG.5(i.e., the X-direction ofFIG.3). Either a pair of the adjacent fins152-158of the third active area region151or a pair of the adjacent fins162-168of the fourth active area region161are spaced from each other by the second spacing in the X direction, as depicted inFIG.3. For example, the adjacent fins162and164are spaced from each other by the second spacing S2, in which the second spacing S2 can be referred to as a distance that is measured from one side (e.g., the right side inFIG.5) of the boundary of the top surface of the fin162and the opposite side (e.g., the left side inFIG.5) of the boundary of the top surface of the fin164. Similarly, in either of the third active area region151or the fourth active area region161, the fins can be arranged along the X-direction by the second pitch, as depicted inFIG.3. The second pitch can be defined by the sum of the second width and the second spacing. For example, the fins156,158of the third active area region151are arranged along the X-direction by the distance X2, and the fins162,164of the fourth active area region161are arranged along the X-direction by the distance X2′ which is equal to the distance X2. Furthermore, the second gate dielectric layer218covering the fins152-158and162-168has a second thickness T2. In some embodiments, the first thickness T2 of the second gate dielectric layer218can be referred to as a height thereof measured from the top surface of one of the fins152-158and162-168. For example, the second thickness T2 of the second gate dielectric layer218can be referred to as a distance from the top surface of the fin152to the top surface of the second gate dielectric layer218.

Reference is made toFIGS.4and5. The first thickness T1 of the first gate dielectric layer216is greater than the second thickness T2 of the second gate dielectric layer218. For example, a ratio of the first thickness T1 of the first gate dielectric layer216to the second thickness T2 of the second gate dielectric layer218is greater than 1.3. In some embodiments, a ratio of the first thickness T1 of the first gate dielectric layer216to the second thickness T2 of the second gate dielectric layer218is in a range from 1.3 to 2. Such thickness difference may be advantageous to provide various isolations suitable for different device that have different functions. For example, the first circuit102(seeFIG.3) used in the I/O device and the second circuit104(seeFIG.3) used in the core device may provide different functions and have different device characteristics, such as device dimensions, driving currents, threshold voltages, device densities, and so forth. The thickness difference between the first and second gate dielectric layers216,218is thus advantageous to provide suitable isolations for the I/O device and the core device. Stated differently, with the thickness difference between the first and second gate dielectric layers216,218, the I/O device can be operated at a voltage higher than that of the core device.

In some embodiments, the first width W1 of at least one of the fins112-118and122-128is less than the second width W2 of at least one of the fins152-158and162-168. In some embodiments, a ratio of the second width W2 of at least one of the fins152-158and162-168to the first width W1 of at least one of the fins112-118and122-128is equal to or greater than 1.05. In some embodiments, a ratio of the second width W2 of at least one of the fins152-158and162-168to the first width W1 of at least one of the fins112-118and122-128is equal to or greater than 1.1. In some embodiments, a ratio of the second width W2 of at least one of the fins152-158and162-168to the first width W1 of at least one of the fins112-118and122-128is in arrange from 1.05 to 1.3. In some embodiments, the first spacing S1 is greater than the second spacing S2. Accordingly, due to that the first width W1 is less than the second width W2 and the first spacing S1 is greater than the second spacing S2, the first pitch can be equal to the second pitch (i.e., the first pitch and the second pitch are substantially the same). For example, the first pitch and the second pitch may be less than about 32 nm. With such dimension configurations, although the first thickness T1 of the first gate dielectric layer216is greater than the second thickness T2 of the second gate dielectric layer218, the space between a pair of the adjacent fins112-118and122-128of the first and second active area regions111,121is sufficient to be filled with the gate electrode132, which may include the first work function layer and the first contact layer. As such, either shrinking the pattern layout dimension or being sufficient to fill the space the adjacent fins of the I/O device with the gate electrode132is achieved.

Reference is made toFIG.3. In the semiconductor device100, the contact plugs are arranged in the spaces between adjacent spacers. For the sake of simplicity, the contact plugs are designated by the same reference numerals of the corresponding contact areas. The contact plugs142,144,146,148,182,184,186,188,190, and192are shown inFIG.3. In the semiconductor device100, the contact plugs142,144,146,148,182,184,186,188,190, and192are in contact with corresponding source/drain (S/D) features. In the example configuration inFIG.3, at least one of the fins112-118,122-128,152-158and162-168includes S/D features which are in contact with at least one of the contact plugs142-148,182-192. In one or more embodiments, portions of at least one of the fins112-118,122-128,152-158and162-168between the adjacent spacers are recessed to form S/D cavities having bottom surfaces lower than the top surface of the corresponding fin. After the formation of the S/D cavities, S/D features are produced by epi-growing a strained material in the S/D cavities. In at least one embodiment, the lattice constant of the strained material is different from the lattice constant of the substrate202(seeFIGS.4and5). Thus, channel regions of the semiconductor device100are strained or stressed to enhance carrier mobility of the device. For example, for a PMOS device, the strained material is configured to apply a compressive stress to enhance hole mobility in the at least one source or drain region of the PMOS device. For an NMOS device, the strained material is configured to apply a tensile stress to enhance electron mobility in the at least one source or drain region of the PMOS device. Examples of the strained material include, but are not limited to, SiGe, SiGeC, SiC, GeSn, SiGeSn, SiP, SiCP and other suitable materials. In at least one embodiment, the strained material for a PMOS device comprises SiGe, SiGeC, Ge, Si, or a combination thereof. In at least one embodiment, the strained material for an NMOS device comprises SiC, SiP, SiCP, Si, or a combination thereof. In the example configuration inFIG.3, upper surfaces of the strained material in the S/D features extend upward above top surface of the corresponding fin. Other arrangements are within the scope of various embodiments. For example, in at least one embodiment, upper surfaces of the strained material in the S/D features are lower than the top surface of the corresponding fin.

In some embodiments, the layout100A is represented by a plurality of masks generated by one or more processors and/or stored in one or more non-transitory computer-readable media. Other formats for representing the layout100A are within the scope of various embodiments. Examples of a non-transitory computer readable recording medium include, but are not limited to, external/removable and/or internal/built-in storage or memory unit, e.g., one or more of an optical disk, such as a DVD, a magnetic disk, such as a hard disk, a semiconductor memory, such as a ROM, a RAM, a memory card, and the like. For example, the layout100A is presented by at least one first mask corresponding to the first, second, third, fourth active area regions111,121,151,161, at least one second mask corresponding to the gate electrodes130,132,170,172, and at least one third mask corresponding to the spacers134,136,138,140,174,176,178,180.

FIGS.6-11are plan views of formation of the fins depicted inFIG.3. As shown inFIG.6, an imaginary line302may divide a substrate300into separate regions for different types of devices or transistors. For example, a first region304for forming a I/O circuit and a second region306for forming a core circuit can be defined by the imaginary line302. In some embodiments, the first region304may abut against the second region306. In some embodiments, the first region304and the second region306may be spaced apart from each other. In some embodiments, the substrate300is a silicon substrate. In some embodiments, the substrate300is similar to the substrate202depicted inFIGS.4and5. A plurality of dummy patterns310are formed on the substrate300. The dummy patterns310may be formed by a series of operations including deposition, photolithography patterning, and etching processes. For example, a dielectric layer may be formed by a deposition process, and then the dielectric layer is etched to form the dummy patterns310. The photolithography patterning processes may include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), and/or other applicable processes. The etching processes may include dry etching, wet etching, and/or other etching methods (e.g., reactive ion etching). In some embodiments, the dielectric layer for forming the dummy patterns310has a thickness in a range from 1000 nm to 20000 nm.

Reference is made toFIG.7. A plurality of spacer lines312are formed on the substrate300, in which a pair of the spacer lines312are in contact with opposing sidewalls of the corresponding dummy pattern310. In some embodiments, a dielectric layer may be formed on the substrate300and the dummy patterns310by a deposition process, and then an etch back process is performed to form the spacer lines312. In some embodiments, the dielectric layer for forming the spacer lines312has a thickness in a range from 200 nm to 7000 nm.

Reference is made toFIG.8. The dummy patterns310are removed and the spacer lines312remain. In some embodiments, an etching process may be performed to remove the dummy patterns310, in which the etching process includes wet etching, dry etching, or combination thereof.

Reference is made toFIG.9. Some of the spacer lines312are removed by a series of operations including deposition, photolithography patterning, and etching processes. The photolithography patterning processes may include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), and/or other applicable processes. The etching processes may include dry etching, wet etching, and/or other etching methods (e.g., reactive ion etching). In this regard, a first group of the spacer lines312covered by the rectangle patterns314are removed, and a second group of the spacer lines312remain. The remained spacer lines312within the first region304may be employed for forming fins in the I/O circuit, and the remained spacer lines312within the second region306may be employed for forming fins in the core circuit.

Reference is made toFIG.10. A photolithography processes may be performed to trim down the width of the spacer lines312within the first region304. In some embodiments, the width of the spacer lines312within the first region304is trimmed down, and the width of the spacer lines312within the second region306remain. Accordingly, after the photolithography processes, the spacer lines312within the first region304are thinner than the spacer lines312within the second region306.

Reference is made toFIG.11. Photolithography and etching processes are performed by using the spacer lines312ofFIG.10as a hard mask layer, so as to remove some portions of the substrate300. Then, the spacer lines312ofFIG.10are removed. Within the first region304, the remained portions of the substrate300underlying the spacer lines312can serve as fin lines316A. Within the second region306, the remained portions of the substrate300underlying the spacer lines312can serve as fin lines316B. As depictedFIG.10, since the spacer lines312within the first region304are thinner than the spacer lines312within the second region306, the fin lines316A inheriting the profile of the spacer lines312within the first region304are thinner than the fin lines316B inheriting the profile of the spacer lines312within the second region306. After the formation of the fin lines316A and316B, photolithography and etching processes can be performed to removing some portions of the fin lines316A and316B, so as to cut the fin lines316A and316B. For example, the continuous fin lines316A and316B may become discontinuous, so as to define OD areas. After defining the OD areas, processes can be subsequently performed to form elements on the substrate300, such as a process for doping channel, a process for forming gate electrodes, a process for forming S/D features, a process for forming gate contacts, a process for forming gate contacts, formation of via openings or metal layers.

In some embodiments, the process for trimming down the width of the spacer lines312can be omitted. For example, after performing the processes as described inFIG.9, photolithography and etching processes can be performed by using the spacer lines312ofFIG.10as a hard mask layer, so as to remove some portions of the substrate300. Then, the spacer lines312ofFIG.10are removed, and remained portions of the substrate300underlying the spacer lines312can serve as fin lines. After the fin lines are formed, a photolithography patterning process is performed to removing some of the fin lines, and photolithography and etching processes then can be performed, so as to trim down the width of the remained fin lines.

As illustrated inFIG.12, which illustrates a top view of a layout400A corresponding to a semiconductor device400according to some embodiments of the present disclosure. The semiconductor device400includes a first core circuit402and a second core circuit404which abut each other, in which each of the first core circuit402and the second core circuit404may be used in a core device of the semiconductor device400. The semiconductor device400further includes a dummy gate406corresponding to a common edge of the first core circuit402and the second core circuit404which abut each other. Furthermore, the semiconductor device400may further include an I/O circuit. Many aspects of the I/O circuit are the same as or similar to those of the first circuit102as described inFIG.3, and thus the detailed explanation may be omitted.

Many aspects of the first core circuit402are the same as or similar to those of the second circuit104. For example, the first core circuit402includes a first active area region411with fins412,414, a second active area region415with fins416,418, a plurality of gate electrodes420,422,424, a plurality of spacers426,428,430,432,434,436, and a plurality of contact areas438,440,442,444,446,448. The first active area region411is within a well region408which is an n-well region in one or more embodiments, and the second active area region415is within a well region410which is a p-well region in one or more embodiments.

In some embodiments, a width of at least one of the fins412,414,416,418, a spacing between a pair of the fins in of the first active area region411or the second active area region415, and a pitch which is equal to a sum of the width and the spacing of the first core circuit402are the same as or similar to those of the second circuit104. These dimension parameters of the first core circuit402can be defined by the same definition as described inFIG.3. For the sake of simplicity, the these dimension parameters are designated by the same reference numerals of the corresponding dimension parameters asFIG.3.

In some embodiment, at least one of the fins412,414of the first active area region411and the fins416,418of the second active area region415has the second width W2 measured along the X-direction as described inFIG.3. For example, the fin416of the second active area region415has the second width W2 measured along the X-direction. In some embodiments, a pair of the adjacent fins of the first active area region411or the second active area region415are spaced from each other by the second spacing in the X direction. In some embodiments, the fins of the first active area region411or the second active area region415can be arranged along the X-direction by the second pitch, which can be defined by a sum of the second width and the second spacing. For example, the fins412,414of the second active area region415are arranged along the X-direction by the second pitch.

In some embodiments, the second pitch is equal to a distance X2 from one side (e.g., the left side inFIG.12) of the boundary of the fin416to the same side (e.g., the left side inFIG.12) of the boundary of the fin418. In some embodiments, the second pitch is equal to a distance X2′ from one side (e.g., the right side inFIG.12) of the boundary of the fin412to the same side (e.g., the right side inFIG.12) of the boundary of the fin414. Accordingly, in some embodiments, either the distance X2 or the distance X2′ can be referred to as the second pitch, and the fins of the first and second active area regions411and415are arranged along the X-direction by the second pitch.

Many aspects of the second core circuit404are the same as or similar to those of the first core circuit402. For example, the second core circuit404includes a third active area region451with a fin452, a fourth active area region453with a fins454, a plurality of gate electrodes456,458, a plurality of spacers460,462,464,466, and a plurality of contact areas468,470,472,474. The third active area region451is within the n-well region408, and the fourth active area region453is within the p-well410. Different from the first core circuit402, the second core circuit404is referred as a single fin device, and the first core circuit402is referred as a multiple fin device. For example, the first active area region411with the fins412,414and the third active area region451with the fin452are located within the same n-well region408, and the fin number of the first active area region411is greater than that of the third active area region451. With the difference between the fin numbers of the first core circuit402and the second core circuit404, the first core circuit402can be used for a high speed application, and the second core circuit404with short contact layer can result in capacitance reduction and power reduction.

In some embodiments, a width of at least one of the fins452and454can be defined by the similar definition as described inFIG.3. In some embodiment, at least one of the fin452of the third active area region451and the fin454of the fourth active area region453has a third width measured along the X-direction. For example, the fin454of the fourth active area region453has the second width W3 measured along the X-direction.

The dummy gate406extends along the X-direction of the layout400A and is across the well regions408,410. The dummy gate may be a dielectric dummy gate comprising one or more dielectric materials. Example dielectric materials of the dummy gate406include, but are not limited to, oxide-based dielectric materials, such as SiO2, SiON, Si3N4, SiOCN and combinations thereof. In at least one embodiment, the gate electrodes420,422,424include one or more metal materials, and the dummy gate406is free of the metal materials of the gate electrodes420,422,424. In some embodiments, the spacers are arranged along longitudinal sides of the dummy gate406in the X direction. The dummy gate406is configured to provide isolation between the first core circuit402and the second core circuit404. In some embodiments, a fin-cutting process may be performed to form a trench between the first core circuit402and the second core circuit404, and such trench is filled with at least one dielectric material, so as to from the dummy gate406. In some embodiments, the dummy gate406may include single or multi dielectric layers.

In some embodiments, at least one of the contact areas438,440,442,444,446,448of the first core circuit402is rectangular having a first side parallel to the X-direction, and the first side having a first length. For example, the first side of the contact area448has the first length labelled as a first dimension D1. In some embodiments, at least one of the contact areas468,470,472,474of the second core circuit404is rectangular having a second side parallel to the X-direction, and the second side having a first length different than the first length. For example, the second side of the contact area470has the second length labelled as a second dimension D2, and the first dimension D1 is greater than the second dimension D2. Accordingly, the second side of the contact area470is shorter than the first side of the contact area448. In some embodiments, a ratio of the first dimension D1 to the second dimension D2 is in a range from 1.1 to 3.

FIG.13is a cross-section view of the I/O circuit401of the semiconductor device400.FIG.14is a cross-section view of the first core circuit402of the semiconductor device400.FIG.15is a cross-section view of the third core circuit404of the semiconductor device400. TheFIGS.13,14, and15are respectively taken lines along gate electrodes thereof as depictedFIGS.4and5.

The semiconductor device400further comprises one or more isolation structures over and around the well regions4082and410. In the example configuration inFIGS.13,14, and15, the isolation structures474A,474B,474C are over the corresponding well regions408and410. The isolation structures474A,474B,474C electrically isolate various elements of the semiconductor device400from each other. For example, as illustrated inFIG.13, the isolation structure474A electrically isolates fins476and477from each other. Similarly, as illustrated inFIG.14, the isolation structure474B electrically isolates fins416and418from each other. In at least one embodiment, at least one of the isolation structures474A,474B,474C comprises one or more STI regions. Example materials of the STI regions include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate, and/or any other low k dielectric materials. In some embodiments, the STI thickness is from 50 nm to 200 nm.

In the example configuration inFIG.13, a gate electrode480wraps over the fins476,477. To electrically isolate the gate electrode480from the fins476,477, a first gate dielectric layer478is arranged under and around the gate electrode480, in which the fins476,477are covered by the first gate dielectric layer478. Each of the fins476,477has a first width as depicted inFIG.4. For example, the top surface of the fin476has the first width W1 measured along the X-direction. A pair of the fins476,477are spaced from each other by a first spacing, as depicted inFIG.4. The fins476,477can be arranged by the first pitch, as depicted inFIG.4. The first pitch can be defined by the sum of the first width and the first spacing. For example, the fins476,477are arranged by the distance X1 measured along the X-direction. Furthermore, the first gate dielectric layer478covering the fins476,477has a first thickness T1. The first thickness T1 of the first gate dielectric layer478can be referred to as a height thereof measured from the top surface of one of the fins476,477, as depicted inFIG.4.

In the example configuration inFIG.14, the gate electrode424wraps over the fins416,418. To electrically isolate the gate electrode424from the fins416,418, a second gate dielectric layer482is arranged under and around the gate electrode424, in which the fins416,418are covered by the second gate dielectric layer482. Each of the fins416,418has a second width as depicted inFIG.12. For example, the top surface of the fin418has the second width W2 measured along the X-direction. A pair of the fins416,418are spaced from each other by a second spacing, as depicted inFIG.12. The fins416,418can be arranged by the second pitch, as depicted inFIG.12. The second pitch can be defined by the sum of the second width and the second spacing. For example, the fins416,418are arranged by the distance X2 measured along the X-direction. Furthermore, the second gate dielectric layer482covering the fins416,418has a second thickness T2. The first thickness T2 of the second gate dielectric layer482can be referred to as a height thereof measured from the top surface of one of the fins416,418, as depicted inFIG.5.

In the example configuration inFIG.15, the gate electrode456wraps over the fin454. To electrically isolate the gate electrode456from the fin454, a third gate dielectric layer484is arranged under and around the gate electrode456, in which the fin454are covered by the third gate dielectric layer484. The top surface of the fins456has the third width W3 measured along the X-direction, as depicted inFIG.12. Furthermore, the third gate dielectric layer484covering the fin454has a third thickness T3. The third thickness T3 of the third gate dielectric layer484can be referred to as a height thereof measured from the top surface of the fin454.

Reference is made toFIGS.13,14, and15. The first thickness T1 of the first gate dielectric layer478is greater than either the second thickness T2 of the second gate dielectric layer482or the third thickness T3 of the third gate dielectric layer484. For example, a ratio of the first thickness T1 of the first gate dielectric layer478to the second thickness T2 of the second gate dielectric layer482is greater than 1.3. In some embodiments, a ratio of the first thickness T1 of the first gate dielectric layer478to the second thickness T2 of the second gate dielectric layer482is in a range from 1.3 to 2. In some embodiments, the second and third gate dielectric layers482and484have the same thickness. Such thickness difference may be advantageous to provide various isolations suitable for different device that have different functions. For example, the I/O circuit401used in the I/O device, the first core circuit402used in the core device, and the third core circuit404used in the other core device may provide different functions and have different device characteristics, such as device dimensions, driving currents, threshold voltages, device densities, and so forth. The thickness difference between the first gate dielectric layer478and either the second gate dielectric layer482or the third gate dielectric layer484is thus advantageous to provide suitable isolations for the I/O device and the core device. Stated differently, with the thickness difference between the first gate dielectric layer478and either the second gate dielectric layer482or the third gate dielectric layer484, the I/O device can be operated at a voltage higher than that of the core device.

In some embodiments, the first width W1 of at least one of the fin476,477is less than the second width W2 of at least one of the fins416,418. In some embodiments, the first width W1 of at least one of the fin476,477is less than the third width W3 of the fin454. In some embodiments, the third width W3 of the fin454is less than the second width W2 of at least one of the fins416,418. In some embodiments, a ratio of the second width W2 of at least one of the fins416,418to the first width W1 of at least one of the fin476,477is equal to or greater than 1.05. In some embodiments, a ratio of the second width W2 of at least one of the fins416,418to the first width W1 of at least one of the fin476,477is equal to or greater than 1.1. In some embodiments, a ratio of the second width W2 of at least one of the fins416,418to the first width W1 of at least one of the fin476,477is in a range from 1.05 to 1.3. In some embodiments, a ratio of the second width W2 of at least one of the fins416,418to the third width W3 of the fin454is equal to or greater than 1.05. In some embodiments, a ratio of the second width W2 of at least one of the fins416,418to the third width W3 of the fin454is equal to or greater than 1.1. In some embodiments, the first spacing is greater than the second spacing. Accordingly, due to that the first width is less than the second width and the first spacing is greater than the second spacing, the first pitch X1 can be equal to the second pitch X2 (i.e., the first pitch and the second pitch are substantially the same). For example, the first pitch X1 and the second pitch X2 may be less than about 32 nm. With such dimension configurations, although the first thickness T1 of the first gate dielectric layer478is greater than the second thickness T2 of the second gate dielectric layer482, the space between a pair of the fins476and477is sufficient to be filled with the gate electrode480, which may include a work function layer and a contact layer. As such, either shrinking the pattern layout dimension or being sufficient to fill the space the adjacent fins of the I/O device with the gate electrode480is achieved.

In some embodiments, the second core circuit404may serve as a single-port SRAM cell, and the layout of the second core circuit404can be designed as a single-port SRAM cell layout with the relationship among the above dimension configurations. For example,FIG.16illustrates a circuit schematic for a single-port SRAM cell500.FIG.17illustrates the corresponding layout in a top view of the single-port SRAM cell500according to some embodiments of the present disclosure, in which gates G, drains D, sources S corresponding to transistors are labelled inFIG.17.

The single-port SRAM cell500includes pull-up transistors PU-1, PU-2; pull-down transistors PD-1, PD-2; and pass-gate transistors PG-1, PG-2. As show in the circuit diagram, transistors PU-1 and PU-2 are p-type transistors, such as the p-type FinFETs discussed above, and transistors PG-1, PG-2, PD-1, and PD-2 are n-type FinFETs discussed above.

The drains of pull-up transistor PU-1 and pull-down transistor PD-1 are coupled together, and the drains of pull-up transistor PU-2 and pull-down transistor PD-2 are coupled together. Transistors PU-1 and PD-1 are cross-coupled with transistors PU-2 and PD-2 to form a first data latch. The gates of transistors PU-2 and PD-2 are coupled together and to the drains of transistors PU-1 and PD-1 to form a first storage node SN1, and the gates of transistors PU-1 and PD-1 are coupled together and to the drains of transistors PU-2 and PD-2 to form a complementary first storage node SNB1. Sources of the pull-up transistors PU-1 and PU-2 are coupled to power voltage CVdd, and the sources of the pull-down transistors PD-1 and PD-2 are coupled to a ground voltage CVss.

The first storage node SN1 of the first data latch is coupled to bit line BL through pass-gate transistor PG-1, and the complementary first storage node SNB1 is coupled to complementary bit line BLB through pass-gate transistor PG-2. The first storage node SN1 and the complementary first storage node SNB1 are complementary nodes that are often at opposite logic levels (logic high or logic low). Gates of pass-gate transistors PG-1 and PG-2 are coupled to a word line WL.

As shown in the top view layout ofFIG.17, the single-port SRAM cell500includes a plurality of fin lines510-513(also referred to as active region, or OD). The N-type fin lines510and513are comprised of a non-germanium-containing semiconductor material, for example silicon. The P-type fine lines511-512are comprised of silicon germanium for strain effect enhancement.

Similar to the SRAM cells discussed above, the fin lines510and513can be located over a P-type well region of the SRAM cell500extend continuously in the Y-direction, whereas the fin lines511and512located over an N-type well region of the SRAM cell500extend discontinuously in the Y-direction. In other words, the fin line511and the fin line512each extend partially into, but not completely through, the SRAM cell500. According to the embodiment shown inFIG.17, the fin line511extends into the SRAM cell500from the “bottom” of the SRAM cell500, and it terminates into the SRAM cell500on the drain side of the pull-up transistor PU-1. The fin line512extends into the SRAM cell500from the “top” of the SRAM cell500, and it terminates into the SRAM cell500on the drain side of the pull-up transistor PU-2. This type of configuration helps prevent the data node leakage between the drain nodes of adjacent pull-up transistors.

As described above, the semiconductor device has the first circuit configured to use in the I/O device and the second circuit configured to use in the core device. In the first circuit, at least one of the fins has the first width, and the first gate dielectric layer covering the fins has the first thickness. In the second circuit, at least one of the fins has the second width, and the second gate dielectric layer covering the fins has the second thickness. The first width is less than the second width, and the first thickness is greater than the second thickness. The thickness difference between the first and second gate dielectric layers is thus advantageous to provide suitable isolations for the I/O device and the core device. Stated differently, with the thickness difference between the first and second gate dielectric layers, the I/O device can be operated at a voltage higher than that of the core device. Furthermore, with the first width is less than the second width, although the first thickness is greater than the second thickness, the space between a pair of the adjacent fins used in the first circuit is sufficient to be filled with the gate electrode, which may include the first work function layer and the first contact layer. As such, either shrinking the pattern layout dimension or being sufficient to fill the space the adjacent fins of the I/O device with the gate electrode is achieved.

In some embodiments, a semiconductor device includes a dielectric dummy gate, a plurality of first semiconductor fins, and a plurality of second semiconductor fins. The dielectric dummy gate extends along a first direction. The first semiconductor fins extend along a second direction within a first core circuit region on a first side of the dielectric dummy gate, and the second direction is substantially perpendicular to the first direction. The second semiconductor fins extend along the second direction within a second core circuit region on a second side of the dielectric dummy gate opposite the first side of the dielectric dummy gate. A number of the second semiconductor fins within the second core circuit region is less than a number of the first semiconductor fins within the first core circuit region, and each of the second semiconductor fins has a width less than a width of each of the first semiconductor fins.

In some embodiments, a semiconductor device includes a first core circuit and a second core circuit electrically isolated from the first core circuit by a dielectric dummy gate. The first core circuit includes a plurality first semiconductor fins and a first source/drain contact extending a first length across the first semiconductor fins. The second core circuit includes a second semiconductor fin and a second source/drain contact extending a second length across the second semiconductor fin. The second length of the second source/drain contact is less than the first length of the first source/drain contact, and each of the first semiconductor fins has a width greater than a width of the second semiconductor fin.

In some embodiments, a semiconductor device includes an I/O circuit, a first core circuit, and a second core circuit. The I/O circuit includes a first semiconductor fin. The first core circuit includes a second semiconductor fin. The second core circuit includes a third semiconductor fin. A width of the third semiconductor fin is greater than a width of the first semiconductor fin of the I/O circuit and less than a width of the second semiconductor fin of the first core circuit.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.