Patent ID: 12213316

DETAILED DESCRIPTION

FIG.1is a circuit view illustrating a semiconductor device according to an example embodiment.

Referring toFIG.1, a semiconductor device100may include a bit line BL, a common source line CSL, word lines WL, upper gate lines UL1and UL2, lower gate lines LL1and LL2, and a cell string CSTR disposed between the bit line BL and the common source line CSL.

The cell string CSTR may include one or a plurality of lower transistors LT1and LT2adjacent to the common source line CSL, one or a plurality of upper transistors UT1and UT2adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between one or the plurality of lower transistors LT1and LT2and one or the plurality of upper transistors UT1and UT2.

One or the plurality of lower transistors LT1and LT2, the plurality of memory cell transistors MCT, and one or the plurality of upper transistors UT1and UT2may be connected in series.

In an example embodiment, the number of one or the plurality of upper transistors UT1and UT2may be two or more, and the plurality of upper transistors UT1and UT2may include a string select transistor UT2and an upper erase control transistor UT1connected to each other in series. The upper erase control transistor UT1may be disposed on the string select transistor UT2.

In an example embodiment, the number of one or the plurality of lower transistors LT1and LT2may be two or more, and the plurality of lower transistors LT1and LT2may include a ground select transistor LT2and a lower erase control transistor LT1connected to each other in series. The lower erase control transistor LT1may be disposed below the ground select transistor LT2.

The lower gate lines LL1and LL2may include a first lower gate line LL1and a second lower gate line LL2. The upper gate lines UL1and UL2may include a first upper gate line UL1and a second upper gate line UL2.

The first lower gate line LL1may be configured as a gate electrode of the lower erase transistor LT1. The second lower gate line LL2may be configured as a gate electrode of the ground select transistor LT2. The word lines WL may be configured as gate electrodes of the memory cell transistors MCT. The first upper gate line UL1may be configured as a gate electrode of the upper erase transistor UT1. The second upper gate line UL2may be configured as a gate electrode of the string select transistor UT2.

An erase operation for erasing data stored in the memory cell transistors MCT may use a gate induced drain leakage (GIDL) phenomenon occurring in the lower and upper erase transistors LT1and UT1. During the erase operation of the semiconductor device100in the example embodiment, an erase voltage may be applied to the bit line BL, and a voltage smaller than the erase voltage may be applied to an erase control gate electrode of the upper erase transistor UT1connected to the first upper gate line UL1. In this case, a depletion region may be formed in a portion in which the gate electrode of the upper erase transistor UT1overlaps a drain region, and electron-hole pairs may be formed in the depletion region. In the formed electron-hole pairs, electrons may move toward the drain region by band-to-band tunneling (BTBT), and holes may move to the channel region such that the channel voltage may increase, thereby enabling the erase operation. The GIDL current may be defined as a current generated in the process described above and enabling the erase operation. The semiconductor device100in an example embodiment may intentionally generate a GIDL current in the erase operation. Holes from the electron-hole pairs generated while the GIDL current is generated may be implanted into channels of the memory cell transistors MCT. Accordingly, electrons trapped in a data storage layer of each of the memory cell transistors MCT may move by the intentionally generated GIDL current, or holes of a channel may be trapped in the data storage layer, such that the operation of erasing the data stored in the memory cell transistors MCT may be performed.

FIG.2is a cross-sectional view illustrating a semiconductor device according to an example embodiment.FIG.3is an enlarged view illustrating a portion of a semiconductor device according to an example embodiment.

Referring toFIGS.2and3, the semiconductor device100may include a lower structure1, and an upper structure2on the lower structure1.

The lower structure1may include a semiconductor substrate6, circuit devices20disposed on the semiconductor substrate6, a lower interconnection structure30electrically connected to the circuit devices20, and a lower capping layer40. The circuit devices20may be provided for operating a cell array of a NAND flash memory device.

The upper structure2may include a pattern structure110on the lower structure1, a stack structure GS including interlayer insulating layers120and gate electrodes130alternately stacked on the pattern structure110, a channel structure CH penetrating the stack structure GS, and a separation structure SS penetrating the stack structure GS and extending in one direction. The upper structure2may further include an upper capping layer172, upper insulating layers174and176, contact plugs181and185connected to the channel structure CH, and a bit line190disposed on the contact plugs181and185. The upper structure2may include a region in which the cell array of the NAND flash memory device is disposed.

The semiconductor substrate6may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). The semiconductor substrate6may be configured as a single crystal silicon substrate. Device isolation layers10may be disposed in the semiconductor substrate6, and source/drain regions28including impurities may be disposed in a portion of the active region15defined between the device isolation layers10.

Each of the circuit devices20may include a transistor including a circuit gate dielectric layer22, a circuit gate electrode24, and source/drain regions28. The source/drain regions28may be disposed on both sides of the circuit gate electrode24in the active region15. The spacer layer26may be disposed on both sides of the circuit gate electrode24, and may insulate the circuit gate electrode24and the source/drain region28from each other. The circuit gate dielectric layer22may include silicon oxide, silicon nitride, silicon oxynitride, or a high-k material. The circuit gate electrode24may include at least one of titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN), tungsten (W), copper (Cu), aluminum (Al), molybdenum (Mo), and ruthenium (Ru). The circuit gate electrode24may include a semiconductor layer, such as, e.g., a doped polycrystalline silicon layer, and may include a material layer such as a metal-semiconductor compound. In an example embodiment, the circuit gate electrode24may include two or more layers.

The lower interconnection structure30may be electrically connected to the circuit gate electrodes24of the circuit devices20and the source/drain regions28. The lower interconnection structure30may include lower contact plugs35having a cylindrical shape or a truncated cone shape, and lower interconnection lines37having at least one region having a line shape. A portion of the lower contact plugs35may be connected to the source/drain regions28, and although not illustrated, the other portion of the lower contact plugs35may be connected to the circuit gate electrodes24. The lower contact plugs35may electrically connect the lower interconnection lines37disposed at different levels from an upper surface of the semiconductor substrate6to each other. The lower interconnection structure30may include a conductive material, and may include, e.g., tungsten (W), copper (Cu), aluminum (Al), and the like, and each component thereof may further include a diffusion barrier including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and tungsten nitride (WN). In example embodiments, the number of the lower contact plugs35and lower interconnection lines37included in the lower interconnection structure30and the arrangements thereof may be varied.

At least a portion of the lower interconnection lines37may include a pad layer to which a plurality of through contact plugs extending downwardly from the upper structure2are directly connected (not shown inFIGS.2and3). The plurality of through contact plugs may be disposed to penetrate a separate through region formed in the stack structure ST of the upper structure2. The plurality of through contact plugs may be electrically connected to the gate electrodes130or the channel structures CH of the upper structure2, respectively.

The lower capping layer40may be disposed to cover the semiconductor substrate6, the circuit devices20, and the lower interconnection structure30. The lower capping layer40may be formed of a material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. The lower capping layer40may include a plurality of insulating layers. The lower capping layer40may include an etch stop layer formed of silicon nitride.

The pattern structure110may include a lower pattern layer101, an intermediate pattern layer102on the lower pattern layer101, and an upper pattern layer103on the intermediate pattern layer102. At least a portion of the pattern structure110may correspond to the common source line CSL described with reference toFIG.1.

The lower pattern layer101may include a semiconductor material such as polysilicon. The lower pattern layer101may include doped polysilicon. For example, the lower pattern layer101may include polysilicon including impurities having N-type conductivity. The impurities having N-type conductivity may include, e.g., at least one of phosphorus (P), arsenic (As), and antimony (Sb), which may be N-type dopants.

The intermediate pattern layer102may extend along an upper surface of the lower pattern layer101. The intermediate pattern layer102and the upper pattern layer103may function as a portion of the common source line of the semiconductor device100, and may function as a common source line together with the lower pattern layer101, for example. The intermediate pattern layer102may penetrate the gate dielectric layer145, and may be in contact with the channel layer140. The intermediate pattern layer102and the upper pattern layer103may include a semiconductor material such as polysilicon. The intermediate pattern layer102may be a layer doped with impurities of the same conductivity as that of the lower pattern layer101, and the upper pattern layer103may be configured as a doped layer or may include impurities diffused from the intermediate pattern layer102. However, the material of the upper pattern layer103may be other than a semiconductor material, and may be formed of an insulating material.

The gate electrodes130may be stacked and spaced apart from each other in the vertical direction Z on the pattern structure110, and may form a stack structure GS together with the interlayer insulating layers120. The gate electrodes130may extend by different lengths on at least a region of the pattern structure110.

The gate electrodes130may include at least one lower gate electrode, e.g., lower gate electrode130L1and lower gate electrode130L2, at least one upper gate electrode, e.g., upper gate electrode130U1and upper gate electrode130U2, and intermediate gate electrodes130M disposed between the lower gate electrodes130L1and130L2and the upper gate electrodes130U1and130U2. Storage capacity of the semiconductor device100may be determined depending on the number of intermediate gate electrodes130M included in the memory cells.

Referring to the circuit view illustrating the semiconductor device100inFIG.1andFIGS.2and3together, the lower gate electrodes130L1and130L2may correspond to the lower gate lines LL1and LL2, the upper gate electrodes130U1and130U2may correspond to the upper gate lines UL1and UL2, and the intermediate gate electrodes130M may correspond to the word lines WL.

The lower gate electrodes130L1and130L2may be a first lower gate electrode130L1and a second lower gate electrode130L2. The first lower gate electrode130L1may be a gate electrode of the lower erase transistor LT1described with reference toFIG.1. The second lower gate electrode130L2may be a gate electrode of the ground select transistor LT2described with reference toFIG.1.

The upper gate electrodes130U1and130U2may be a first upper gate electrode130U1and a second upper gate electrode130U2. The first upper gate electrode130U1may be a gate electrode of the upper erase transistor UT1described with reference toFIG.1. The second upper gate electrode130U2may be a gate electrode of the string select transistor UT2described with reference toFIG.1.

The first lower gate electrode130L1may be referred to as a “lowest gate electrode” or a “lower erase control gate electrode.” The second lower gate electrode130L2may be referred to as a “second lower gate electrode” or a “ground select gate electrode.” The first upper gate electrode130U1may be referred to as an “uppermost gate electrode” or an “upper erase control gate electrode.” The second upper gate electrode130U2may be referred to as a “second upper gate electrode” or a “string select gate electrode.” A thickness of the upper erase gate electrode130U1in the vertical direction Z may be in a range of about 20 nm to about 30 nm.

Each of the gate electrodes130may include a first gate layer130aand a second gate layer130b. The first gate layer130amay include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof. The second gate layer130bmay include a metal material, such as, e.g., tungsten (W). However, the configuration of the gate electrodes130may include, e.g., three or more layers, and may include polycrystalline silicon or a metal silicide material. The gate electrode in an example embodiment may include the first gate layer130aand the second gate layer130b. For example, the corresponding gate electrode130included in the upper erase control gate electrode130U1may include the first gate layer130aand the second gate layer130bcorresponding thereto.

The interlayer insulating layers120may be disposed between the gate electrodes130. Similarly to the gate electrodes130, the interlayer insulating layers120may be stacked and spaced apart from each other in the vertical direction Z. The interlayer insulating layers120may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

Each of the channel structures CH may form a single memory cell string, and may extend in the vertical direction Z perpendicular to the upper surface of the lower pattern layer101. The channel structures CH may penetrate the stack structure GS in the vertical direction Z, and may be partially recessed into an upper portion of the lower pattern layer101from a lower end. The channel structures CH may be spaced apart from each other on the pattern structure110while forming rows and columns. For example, the channel structures CH may be disposed in a lattice pattern on a plane or in a zigzag pattern in one direction. Each of the channel structures CH may have a columnar shape having a side surface perpendicular to the upper surface of the lower pattern layer101or a side surface having a width decreasing toward the lower pattern layer101depending on an aspect ratio.

Each of the channel structures CH may include a channel layer140, a gate dielectric layer145, a core insulating layer147, and a channel pad150.

The gate dielectric layer145may include a tunneling layer141, a data storage layer142, and a blocking layer143stacked in order from the channel layer140.

The channel layer140may be formed to have an annular shape surrounding the inner core insulating layer147in the channel structure CH, and may be disposed on the side surface of the core insulating layer147. The channel layer140may cover a side surface and a bottom surface of the core insulating layer147. The channel layer140may be in contact with the intermediate pattern layer102through an external side surface in a lower portion. The channel layer140may extend to a region between the upper erase gate electrode130U1and the channel pad150. The channel layer140may include a semiconductor material such as polysilicon. For example, the channel layer140may include undoped polysilicon, and may be doped with impurities having P-type conductivity or impurities having N-type conductivity in example embodiments.

The gate dielectric layer145may be disposed between the gate electrodes130and the channel layer140. A gate dielectric layer145may extend to a region between the gate electrodes130and the channel layer140, may extend to a region above the upper erase control gate electrode130U1, and may extend to a region below the lower erase control gate electrode130L1. The tunneling layer141may tunnel charges into the data storage layer142. The tunneling layer141may include, e.g., silicon oxide (SiO), silicon oxynitride (SiON), or a combination thereof. The data storage layer142may be configured as a charge trap layer. The data storage layer142may include, e.g., silicon nitride (SiN). The blocking layer143may include silicon oxide (SiO), silicon oxynitride (SiON), a high-k dielectric material, or a combination thereof.

The core insulating layer147may have a cylindrical shape extending in the vertical direction Z. An upper surface of the core insulating layer147may be in contact with the channel pad150. The core insulating layer147may include silicon oxide or a low-k material.

The channel pad150may be disposed on the core insulating layer147in the channel structure CH. The channel pad150may be disposed on the internal side surface of the channel layer140and may be in contact with the channel layer140. At least a portion of the channel pad150may be surrounded by the upper erase control gate electrode130U1in a horizontal direction parallel to the upper surface of the lower pattern layer101. At least a portion of the channel pad150may overlap the upper erase control gate electrode130U1in the horizontal direction.

A level L of the bottom surface of the channel pad150may be lower than a level of the upper surface of the upper erase control gate electrode130U1, and may be substantially the same as or higher than a level of the lower surface of the upper erase control gate electrode130U1. The level L of the bottom surface of the channel pad150may be higher than a level of the upper surface of the string select gate electrode130U2. In an example embodiment, the level L of the bottom surface of the channel pad150may be between the level of the lower surface of the upper erase control gate electrode130U1and the level of the upper surface of the string select gate electrode130U2. The level L of the bottom surface of the channel pad150may be defined based on the surface of the lower pattern layer101facing the stack structure GS, such as, e.g., the upper surface of the lower pattern layer101. The bottom surface of the channel pad150may include a downwardly curved portion, for example.

In an example embodiment, the channel pad150may include a first pad layer151and a second pad layer152on the first pad layer151. The first pad layer151may cover side surfaces of the second pad layer152opposing each other. The first pad layer151may cover the lower surface of the second pad layer152, and may have a U-shape or a shape similar thereto.

The first pad layer151may be formed of undoped (intentionally not doped) polysilicon, and may work as a diffusion buffer layer between the second pad layer152and the channel layer140. For example, to form a depletion region D (described further below), the first pad layer151may intentionally diffuse impurities from the second pad layer152and may form a concentration gradient of impurities, thereby alleviating the diffusion of impurities. Thus, the first pad layer151may be provided to decrease the impurity concentration of a region adjacent to the channel layer140in the channel pad150to a predetermined value or less.

For example, referring to the inset inFIG.3, the first pad layer151may include a first region151aincluding a polysilicon region having a low concentration (formed by impurities diffused from the second pad layer152including impurities having a high concentration), and a second region151bhaving impurities having a concentration lower than that of the first region151a. At least a portion of the second region151bmay include an undoped polysilicon region. The first region151aand the second region151bmay be divided based on whether the concentration of the N-type impurities corresponds to a predetermined value, such as, e.g., 2×1019/cm3. In the drawings, the vicinity corresponding to the predetermined concentration value is indicated by a dashed line between the interfacial surfaces s1and s2. The concentration profile of impurities may be different from the illustrated example. The concentration distribution of impurities may be observed by X-ray fluorescence spectrometry (XRF) or secondary ion mass spectrometry (SIMS), for example.

In a region of the second region151bhorizontally overlapping the upper erase control gate electrode130U1, the depletion region D may be formed adjacent to the interfacial surface s1between the first pad layer151and the channel layer140.

During an erase operation of the semiconductor device100, electron-hole pairs may be formed in the depletion region D such that a gate induced drain leakage current may be induced.

In an example embodiment, the impurity concentration of the depletion region D may be, e.g., less than about 2×1019/cm3. However, the depletion region D may be defined upon a predetermined value different from this example.

The depletion region D may horizontally overlap the upper erase control gate electrode130U1. Thus, the area in which the GIDL current is generated during the erase operation in the semiconductor device100in an example embodiment may increase further than in a case in which the channel pad150does not overlap the upper erase control gate electrode130U1in the horizontal direction. Also, the area in which the GIDL current is generated during an erase operation in the semiconductor device100in an example embodiment may increase further than in a case in which the first pad layer151is not included.

In further detail, in a case in which the channel pad150does not overlap the upper erase control gate electrode130U1in the horizontal direction, a GIDL current in which the vertical BTBT is dominant may be generated in the channel layer140. In this case, since the area in which GIDL is generated may be locally formed in the channel layer140, GIDL generation efficiency may be reduced. Also, in a case in which the first pad layer151is not included, the second pad layer152having a high concentration may be in direct contact with the channel layer140, and accordingly, the area of the depletion region D in which the GIDL is generated may be relatively reduced, such that GIDL generation efficiency may be reduced. In the absence of the first pad layer151, which may be the diffusion buffer layer, the depletion region D for generating the GIDL current may not be formed by a difference in impurity concentration.

On the other hand, in the present example embodiment, the channel pad150may overlap the upper erase control gate electrode130U1in the horizontal direction, such that the depletion region D may overlap the upper erase control gate electrode130U1in the horizontal direction. In this case, since the GIDL current may be generated in which transverse BTBT in the horizontal direction dominates, the area in which GIDL is generated may be increased by the overlap area. Also, in the present example embodiment, the first pad layer151, as a diffusion buffer layer, is provided, and the area of the depletion region D may further increase. Accordingly, as the area of the depletion region D, the area in which GIDL is generated, increases, GIDL current generation efficiency may improve.

In general, to provide a PN junction between the channel pad150and the channel layer140, GIDL generation efficiency may improve by doping impurities having P-type conductivity. However, in this case, since a dopant having P-type conductivity may need to be implanted in a concentration higher than that of the channel pad including impurities having N-type conductivity using an ion implantation process, the process cost may increase and mass productivity may degrade. Also, when the impurities having P-type conductivity are doped, an etch rate of the layer doped with the impurities having P-type conductivity may change. Accordingly, the doped region may be removed in a subsequent etching process, and it may be difficult to maintain the PN junction. Also, process dispersion in each of the channel structures CH may significantly increase due to the subsequent etching process.

On the other hand, in the present example embodiment, GIDL generation efficiency may improve using the first pad layer151working as a diffusion buffer layer and by providing the depletion region D. Thus, the process cost may be reduced by omitting an ion implantation process, and the process dispersion may not increase.

The area of the depletion region D and GIDL current generation efficiency therefrom may vary depending on a thickness t1of the first pad layer151in the horizontal direction, which will be described in greater detail with reference toFIGS.4A to4D. Also, the area of the depletion region D and GIDL current generation efficiency therefrom may vary depending on the shape of the interfacial surface s2between the first pad layer151and the second pad layer152, which will be described in greater detail with reference toFIGS.6and7.

The interfacial surfaces s1and s2between the channel layer140, the first pad layer151, and the second pad layer152may be distinguished from each other using energy dispersive spectroscopy (EDS), atom probe tomography (APT), or high-angle annular dark-field imaging (HAADF). For example, even when the channel layer140, the first pad layer151, and the second pad layer152are formed of the same material, the impurities may be locally concentrated and distributed on the interfacial surfaces s1and s2during the process, and accordingly, each layer may be distinguished from each other through the analysis method described above.

The second pad layer152may be disposed on the first pad layer151. The second pad layer152may include doped polysilicon that is doped with impurities and having N-type conductivity. The concentration of impurities included in the second pad layer152may be, e.g., in a range of about 1×1020/cm3to about 1×1021/cm3. The second pad layer152may be formed by directly depositing a doped semiconductor material. However, this may be varied, and after depositing the semiconductor material, the doping may be performed at a desired concentration through an additional process.

Referring again toFIG.2, the separation structure SS may be disposed to penetrate the stack structure GS in the vertical direction Z, and may extend in the X direction. The separation structure SS may extend in the X direction and may separate the gate electrodes130of the stack structure GS from each other in the Y direction. A level of the upper surface of the separation structure SS may be higher than a level of the upper surface of the channel structure CH with respect to the upper surface of the lower pattern layer101. The separation structure SS may penetrate the entire stacked gate electrodes130, and may be in contact with the pattern structure110. The separation structure SS may have a shape of which a width may decrease toward the lower pattern layer101due to a high aspect ratio. The separation structure SS may include an insulating material such as silicon oxide or silicon nitride. In an example embodiment, the separation structure SS may include an insulating spacer and a conductive layer in contact with the lower pattern layer101.

The upper capping layer172may be disposed to cover upper portions of the stack structure GS and the channel structures CH. An upper surface of the upper capping layer172may be substantially coplanar with an upper surface of the channel structure CH. The upper capping layer172may be formed of a material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

The upper insulating layers174and176may be disposed on the upper capping layer172, and may include a first upper insulating layer174and a second upper insulating layer176. The first upper insulating layer174may be substantially coplanar with the upper surface of the separation structure SS. The second upper insulating layer176may be disposed on the first upper insulating layer174and the separation structure SS. The upper insulating layers174and176may be formed of a material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

The contact plugs181and185may be connected to the channel structures CH. The contact plugs181and185may include a first contact plug181and a second contact plug185. The first contact plug181may be in contact with the channel pad150. The contact plugs181and185may electrically connect the channel structure CH to the bit line190. Each of the contact plugs181and185may include barrier layers181aand185aand conductive layers181band185b. For example, the barrier layer181amay surround a lower surface and side surfaces of the conductive layer181b. The barrier layers181aand185amay include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), and tungsten carbon nitride (WCN), for example. The conductive layers181band185bmay include a conductive material, a metal material such as tungsten (W), copper (Cu), or aluminum (Al), for example.

The bit line190may extend in the Y direction on the stack structure GS and the channel structures CH. The bit line190may be electrically connected to the circuit devices20of the lower structure1by through contact plugs. The bit line190may be electrically connected to the channel layer140. The bit line190may include a barrier layer190aand a conductive layer190b. The barrier layer190amay include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), and tungsten carbon nitride (WCN), for example. The conductive layer190bmay include a conductive material, a metal material such as tungsten (W), copper (Cu), or aluminum (Al), for example. The bit line190illustrated inFIG.2may correspond to the bit line BL illustrated in the circuit view inFIG.1.

FIGS.4A to4Care views illustrating sizes of a depletion region, a GIDL generating region, in examples in which thicknesses of a first pad layer are different, and corresponding to region “B” inFIG.3.

Referring toFIGS.4A to4C, as the thicknesses t1a, t1b, and t1cof the first pad layer151increase, the areas of the depletion regions Da, Db, and Dc may respectively increase.

The depletion regions Da, Db, and Dc may be internal regions indicated by dashed-dotted lines in the drawing. The GIDL current may be proportional to the area of the depletion region formed in the region in which the gate electrode and the drain region overlap each other. Accordingly, as the thicknesses t1a, t1b, and t1cof the first pad layer151, which are diffusion buffer layers, increase, the corresponding areas Da, Db, and Dc may increase, such that the GIDL current may increase. However, the GIDL current may also be proportional to an electric field applied to the depletion region during the erase operation, and as the thicknesses t1a, t1b, and t1cincrease, the applied electric field may decrease. Accordingly, when the first pad layer151is formed to have an optimal thickness in consideration of the area of the depletion region and the electric field, the generation of the GIDL current may increase. Referring toFIG.4Dtogether, when the thickness of the first pad layer151is in the range of about 3 nm to about 10 nm, the amount of GIDL current generation may significantly increase as compared to the comparative examples. Specifically, when the thickness of the first pad layer151is in the range of about 5 nm to about 9 nm, e.g., the amount of generated GIDL current may increase by about 4 times or more as compared to the comparative examples.

FIG.4Dis a graph illustrating comparison of GIDL current values in comparative examples and example embodiments through simulation results.

FIG.4Dillustrates GIDL current values generated during an erase operation in each example.

Comparative example 1 inFIG.4Dis an example in which an overlap region is not present, and comparative example 2 is an example in which the first pad layer151is not included (t1=0).

Example embodiments E1, E2, E3, and E4inFIG.4Dindicate the GIDL current generated during the erase operation when the thickness t1of the first pad layer151is varied in the range of about 5 nm to about 13 nm. The displayed GIDL current values may represent a median of samples in each example.

Referring toFIG.4D, in the examples embodiments E1, E2, and E3, the amount of generated GIDL current increased by about 4 times or more relative to comparative examples 1 and 2. This may be because, as described above, by introducing the first pad layer151as a diffusion buffer layer, the depletion region D (in which a concentration of impurities is a predetermined concentration or less) was formed, and the area in which the GIDL was generated was increased by an area of overlap (where the depletion region D overlaps the erase control gate electrode130U1in the horizontal direction).

In comparative example 2, since the channel layer140has a small thickness of less than about 10 nm, specifically, about 5 nm, when the first pad layer151is not present, it may be difficult to form the depletion region for BTBT between the second pad layer152and the channel layer140.

FIGS.5to10are enlarged views illustrating a portion of a semiconductor device according to an example embodiment, illustrating region “A” inFIG.2.

Referring toFIG.5, in a semiconductor device100′, two upper erase transistors may be disposed above a single cell string. For example, a first erase control gate electrode130U1u(disposed on an uppermost end among the gate electrodes130) and a second erase control gate electrode130U1d(disposed below the first erase control gate electrode130U1d) may be included in a first upper erase transistor and a second upper erase transistor, respectively. To improve efficiency of GIDL current generation, a level L′ of a bottom surface of the channel pad150′ may be substantially equal to or higher than a level of a bottom surface of the second erase control gate electrode130U1d. Accordingly, regions of the channel pad150may overlap the erase control gate electrodes130U1uand130U1din the horizontal direction. Each of the first pad layer151′ and the second pad layer152′ may extend further downward than in the aforementioned example embodiment. However, in another example embodiment, a plurality of upper erase transistors may be disposed above a single cell string. For example, two or more upper erase control gate electrodes may be disposed and spaced apart from each other in the vertical direction Z on the string select gate electrode130U2. When the number of upper erase control transistors increases, the area of the overlap region in which the channel pad150′ horizontally overlaps the upper erase control gate electrodes may increase, such that efficiency of GIDL current generation may increase.

Referring toFIG.6, in the semiconductor device100A, a first pad layer151A may be formed using a deposition-etch-deposition (DED) process, and the shape thereof may be different from the aforementioned example embodiment. For example, during the etching process, the upper portion of the first pad layer151A may be removed relatively more than the other portions. The first pad layer151A may include a portion in which a thickness in a horizontal direction decreases toward an upper end in a region in contact with the internal side surface of the channel layer140. For example, the first pad layer151A may include a lower portion and an upper portion on the lower portion, in a region in contact with the channel layer140, and the lower portion may have a first thickness t1in a horizontal direction, and the upper portion may have a second thickness t2smaller than the first thickness t1in the horizontal direction.

The internal side surface s2′ of the first pad layer151A in contact with a second pad layer152A may be inclined with respect to the external side surface s1of the first pad layer151A in contact with the channel layer140. The internal side surface s2′ may be inclined less than the external side surface s1. The slope of the internal side surface s2′ may be different from the slope of the external side surface s1. As the internal side surface s2′ is inclined, the shape or area of the depletion region D may also vary. The area may increase in a lower portion of the depletion region D overlapping the upper erase gate electrode130U1in the horizontal direction, and an electric field applied during an erase operation may increase in an upper portion of the depletion region D. Thus, the shape of the depletion region D may be optimized such that generation of the GIDL current is maximized. Accordingly, efficiency of GIDL current generation may improve. A thickness in a region in which the first pad layer151A overlaps the erase gate electrode130U1in the horizontal direction may be maintained in a range of about 3 nm to about 10 nm.

To correspond to the shape of the first pad layer151A, the second pad layer152A may have an inclined side surface, of which the thickness in the horizontal direction may decrease downwardly. As the first pad layer151A has the inclined internal side surface s2′, gap-filling of the second pad layer152A filling the space therein may be easily performed in a subsequent process.

Referring toFIG.7, in a semiconductor device100B, similarly to the semiconductor device inFIG.6, the internal side surface s2′ of a first pad layer151B may be inclined with respect to the external side surface s1. The second pad layer152B may penetrate the first pad layer151A, and the bottom surface of the second pad layer152B may be in contact with the upper surface of the core insulating layer147. A lower portion of the first pad layer151B may be removed during an etching process.

Referring toFIG.8, in a semiconductor device100C, an upper portion of a first pad layer151C may be removed such that a second pad layer152C may be in contact with the first pad layer151C in a lower portion of a side surface, and may be in contact with the channel layer140in an upper portion of the side surface. For example, while the first pad layer151C is removed by an etchback process, upper portions of the channel layer140and the gate dielectric layer145may also be partially removed.

Referring toFIG.9, in a semiconductor device100D, a hemispherical grain (HSG) may be formed on the surface of a first pad layer151D. For example, a curved protrusion P may be formed on an internal side surface s2rof the first pad layer151D such that the first pad layer151D may have serrations to include a serration portion. Accordingly, the surface area of the interfacial surface s2rbetween the first pad layer151D and the second pad layer152D may increase. The shape or area of the depletion region Dh may also vary in response to the internal side surface s2rhaving serrations. The area may increase in a middle region of the depletion region Dh overlapping the upper erase gate electrode130U1in the horizontal direction, and an electric field applied during an erase operation may increase in the upper and lower regions. The shape of the depletion region Dh may be optimized to increase GIDL current generation. Accordingly, efficiency of GIDL current generation may increase.

Referring toFIG.10, in a semiconductor device100E, HSG may be formed on the surface of a first pad layer151E, and for example, a protrusion P′ formed on an internal side surface s2r′ of the first pad layer151E may have an inwardly pointed shape. Accordingly, the surface area of the interfacial surface s2r′ between the first pad layer151E and a second pad layer152E may increase. As described above, the shape of the depletion region Dh may be optimized to increase generation of the GIDL current. Accordingly, efficiency of GIDL current generation may improve.

FIGS.11and12are cross-sectional views illustrating a semiconductor device according to an example embodiment, illustrating regions corresponding toFIG.2.

Referring toFIG.11, in a semiconductor device100F, a stack structure GS of an upper structure2may include a lower stack structure and an upper stack structure on the lower stack structure, and each of a channel structures CHa may include a lower channel structure CH1penetrating the lower stack structure and an upper channel structure CH2penetrating the upper stack structure. The channel layer140of the first channel structure CH1may be connected to the channel layer140of the second channel structure CH2. In the connection region, the gate dielectric layer145and the channel layer140may be bent. For example, the side surface of the channel layer140may include a bent portion formed by a difference in width in the connection region, and a slope of the side surface may change. In the example embodiment, the stack structure may be configured as a double stacked structure, and the example embodiment may also include an example embodiment in which the stack structure is configured as a multi-stack structure.

Referring toFIG.12, in a semiconductor device100G, a lower structure1and an upper structure2may be bonded to each other through a bonding structure. The upper structure2of the semiconductor device100G may be obtained by disposing the upper structure2of the semiconductor device100inFIG.2upside down. The upper structure2may further include an upper bonding pad160and a lower bonding pad60. The upper structure2may further include a third upper insulating layer178. The upper bonding pad160may be electrically connected to the bit line190through a via, and the lower bonding pad60may be electrically connected to the circuit devices20through a via. The lower bonding pad60and the upper bonding pad160may include, e.g., tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof. The lower bonding pad60and the upper bonding pad160may function as a bonding layer for bonding the lower structure1to the upper structure2. Also, the lower bonding pad60and the upper bonding pad160may provide an electrical connection path between the lower structure1and the upper structure2. The lower bonding pad60and the upper bonding pad160may be bonded to each other by copper (Cu)-copper (Cu) bonding.

FIGS.13to18are views illustrating a method of manufacturing a semiconductor device according to an example embodiment, illustrating processes of a method of manufacturing a semiconductor device illustrated inFIG.2in order.

Referring toFIG.13, a lower structure1including circuit devices20, a lower interconnection structure30, and a lower capping layer40may be formed on a semiconductor substrate6. A lower pattern layer101, horizontal sacrificial layers107,108, and109, and an upper pattern layer103may be formed on the lower structure1. Interlayer insulating layers120and sacrificial layers128may be alternately stacked on the upper pattern layer103.

Device isolation layers10may be formed in the semiconductor substrate6. The circuit gate dielectric layer22and the circuit gate electrode24may be sequentially formed on the active region15. The device isolation layers10may be formed by, e.g., a shallow trench isolation (STI) process. The circuit gate dielectric layer22may be formed of silicon oxide, and the circuit gate electrode24may be formed of at least one of polycrystalline silicon or a metal silicide layer. Thereafter, a spacer layer26may be formed on both sidewalls of the circuit gate dielectric layer22and the circuit gate electrode24, and source/drain regions28may be formed in a portion of the active region15. In example embodiments, the spacer layer26may include a plurality of layers. The source/drain regions28may be formed by performing an ion implantation process.

The lower contact plugs35and the lower interconnection lines37of the lower interconnection structure30may be formed by forming a portion of the lower capping layer40, partially removing the lower capping layer40by etching, and filling a conductive material, or may be formed by depositing and patterning a conductive material, and filling the region removed by patterning with a portion of the lower capping layer40.

The lower capping layer40may be formed of a plurality of insulating layers. A portion of the lower capping layer40may be formed in each process of forming the lower interconnection structure30, and a portion of the lower capping layer40may be formed on the uppermost lower interconnection line37, such that the lower capping layer40may be formed to cover the circuit devices20and the lower interconnection structure30.

The lower pattern layer101may be formed on the lower structure1, and may include a semiconductor material, such as, e.g., polysilicon.

The horizontal sacrificial layers107,108, and109may be stacked in order on the lower pattern layer101. The horizontal sacrificial layers107,109, and109may include a first layer107, a second layer108, and a third layer109, and may be replaced with the intermediate pattern layer102inFIG.2formed in a subsequent process. The first and third layers107and109may be formed of the same material as that of the interlayer insulating layers120, and may be formed of, e.g., silicon oxide. The second layer108may be formed of the same material as that of the sacrificial layers128and may be formed of, e.g., silicon nitride.

The upper pattern layer103may be formed on the horizontal sacrificial layers107,108, and109. Although not illustrated, the upper pattern layer103may include a portion in which the horizontal sacrificial layers107,108, and109are bent along a side surface of the patterned region and is in contact with the lower pattern layer101. The upper pattern layer103may include a semiconductor material, such as, e.g., polysilicon.

The sacrificial layers128may be partially replaced with the gate electrodes130(seeFIG.2) in a subsequent process. The sacrificial layers128may be formed of a material different from that of the interlayer insulating layers120, and may be formed of a material etched with etch selectivity for the interlayer insulating layers120under predetermined etching conditions. For example, the interlayer insulating layer120may be formed of at least one of silicon oxide and silicon nitride, and the sacrificial layers128may be formed of a material different from that of the interlayer insulating layer120, selected from among silicon, silicon oxide, silicon carbide, and silicon nitride. In example embodiments, the thicknesses of the interlayer insulating layers120may not be the same. The thicknesses of the interlayer insulating layers120and the sacrificial layers128and the number of films included in the interlayer insulating layers120and the sacrificial layers128may be varied from the illustrated examples. An upper capping layer172and a stopper layer129may be formed on the uppermost sacrificial layer128. The stopper layer129may include silicon nitride.

Referring toFIG.14, a channel hole H penetrating the stack structure of the interlayer insulating layers120and the sacrificial layers128may be formed. The gate dielectric layer145, the channel layer140, and the core insulating layer147may be formed in the channel hole H. A recess portion RS may be formed by partially removing the core insulating layer147from an upper portion.

The channel hole H may be formed by anisotropically etching the stack structure of the interlayer insulating layers120and the sacrificial layers128in the vertical direction Z. The channel hole H may penetrate the upper capping layer172, the stopper layer129, the upper pattern layer103, and the horizontal sacrificial layers107,108, and109, and may be recessed into the lower pattern layer101.

The gate dielectric layer145may be conformally formed in the channel hole H. The forming the gate dielectric layer145may include forming a blocking layer143, a data storage layer142, and a tunneling layer141in order from a sidewall of the channel hole H. Thereafter, the channel layer140may be conformally formed on the gate dielectric layer145in the channel hole H, and the core insulating layer147may be formed to fill the other space of the channel hole H. The gate dielectric layer145and the channel layer140may be formed to extend to the stopper layer129and may be removed by a planarization process. The exposed core insulating layer147may be partially removed from the upper portion, thereby forming the recess portion RS. The depth of the recess portion RS may be determined in consideration of the level of the bottom surface of the channel pad150. For example, a lower end of the recess portion RS may be formed at a level that is lower than a level of the upper surface of the uppermost sacrificial layer128, and may be formed at substantially the same level as or higher than a level of the lower surface of the uppermost sacrificial layer128.

Referring toFIG.15, an undoped polysilicon layer151P may be formed.

The undoped polysilicon layer151P may be conformally formed to cover the internal side surface of the channel layer140exposed by removing the core insulating layer147and the bottom surface of the recess portion RS. The undoped polysilicon layer151P may extend to the stopper layer129. In a subsequent process, the undoped polysilicon layer151P may be partially removed by performing a DED process or an etchback process. For example, the undoped polysilicon layer151P may be partially removed using an anisotropic etching process. In this process, the undoped polysilicon layer151P may be partially removed and may remain only in the channel hole H to be included in the first pad layer151of the channel pad150inFIG.2, and the shape and the thickness thereof may be varied depending on an etching process and a deposition process.

Referring toFIG.16, the channel pad150may be formed by forming the second pad layer152on the first pad layer151. Channel structures CH may be formed by performing a planarization process.

The second pad layer152may be formed to cover the first pad layer151. The second pad layer152may be formed of polysilicon including impurities having N-type conductivity. In this process, an ion implantation process may not be performed when forming the channel pad. For example, to form PN bonding or to control the impurity concentration, a process of performing an ion implantation process on the channel pad may not be performed, and polysilicon doped with impurities having N-type conductivity may be directly deposited. In an example embodiment, since the first pad layer151may work as a diffusion buffer layer and impurities may be diffused from the second pad layer152such that a depletion region D may be formed, the impurity concentration of the depletion region D for generating the GIDL current may be controlled without the ion implantation process.

The planarization process may be performed until the upper surface of the upper capping layer172is exposed. While performing the planarization process, the stopper layer129may stop the planarization process. For example, while the stopper layer129is removed, when an interfacial surface between the different materials of the stopper layer129and the upper capping layer172is sensed, the planarization process may be stopped. Accordingly, the upper surface of the channel structure CH may be exposed, and the upper surface of the channel structure CH may be substantially coplanar with the upper surface of the upper capping layer172. The planarization process may be, e.g., a chemical mechanical polishing process.

Referring toFIG.17, an isolation trench T penetrating the stack structure of the upper pattern layer103, the horizontal sacrificial layers107,108, and109, the interlayer insulating layers120, and the sacrificial layers128and extending in the X direction may be formed, and the horizontal sacrificial layers107,108, and109may be replaced with an intermediate pattern layer102.

The isolation trench T may be formed by forming a mask layer using a photolithography process, and anisotropically etching the first upper insulating layer174, the sacrificial layers128, and the interlayer insulating layers120. The isolation trench T may be formed in the form of a trench extending in the X direction, and may expose the lower pattern layer101on a lower end.

Thereafter, while forming other sacrificial spacer layers in the trench T, the second layer108may be exposed by an etchback process. The second layer108may be selectively removed, and the first and third layers107and109disposed above and below the second layer108may be removed. The trench T may be partially recessed into the lower pattern layer101, and may penetrate the upper capping layer172and the first upper insulating layer174.

The horizontal sacrificial layers107,108, and109may be removed by an etching process. During the process of removing the horizontal sacrificial layers107,108, and109, a portion of the exposed gate dielectric layer145may also be removed from a side surface. The intermediate pattern layer102may be formed by depositing a conductive material in the region from which the horizontal sacrificial layers107,108, and109are removed, the sacrificial spacer layers may be removed from the trench T.

Referring toFIG.18, the sacrificial layers128may be removed through the trench T, thereby forming horizontal openings LT.

The sacrificial layers128may be selectively removed with respect to the interlayer insulating layers120, the upper capping layer172, and the first upper insulating layer174through the isolation trench T. Accordingly, a plurality of horizontal openings LT may be formed between the interlayer insulating layers120.

Referring again toFIG.2, the gate electrodes130may be formed by filling the horizontal openings LT with a conductive material. Accordingly, the stack structure ST in which the interlayer insulating layers120and the gate electrodes130are alternately stacked may be formed. The forming the gate electrodes130may include forming the first gate layer130aand the second gate layer130bin order. Thereafter, the separation structure SS may be formed by filling the isolation trench T with an insulating material, and the second upper insulating layer176, the contact plugs181and185, and the bit line190may be formed. Accordingly, the semiconductor device100inFIGS.2and3may be manufactured.

FIG.19is a view illustrating a data storage system including a semiconductor device according to an example embodiment.

Referring toFIG.19, a data storage system1000may include a semiconductor device1100and a controller1200electrically connected to the semiconductor device1100. The data storage system1000may be implemented as a storage device including one or a plurality of semiconductor devices1100or an electronic device including a storage device. For example, the data storage system1000may be implemented as a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device, including one or a plurality of semiconductor devices1100.

The semiconductor device1100may be implemented as a nonvolatile memory device, and may be implemented as the NAND flash memory device described with reference toFIGS.1to12, for example. The semiconductor device1100may include a first semiconductor structure1100F and a second semiconductor structure1100S on the first semiconductor structure1100F. In example embodiments, the first semiconductor structure1100F may be disposed on the side of the second semiconductor structure1100S. The first semiconductor structure1100F may be configured as a peripheral circuit structure including a decoder circuit1110, a page buffer1120, and a logic circuit1130. The second semiconductor structure1100S may be configured as a memory cell structure including a bit line BL, a common source line CSL, word lines WL, first and second gate upper lines UL1and UL2, first and second gate lower lines LL1and LL2, and memory cell strings CSTR between the bit line BL and the common source line CSL.

In the second semiconductor structure1100S, each of the memory cell strings CSTR may include lower transistors LT1and LT2adjacent to the common source line CSL, upper transistors UT1and UT2adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1and LT2and the upper transistors UT1and UT2. The number of the lower transistors LT1and LT2and the number of the upper transistors UT1and UT2may be varied in example embodiments.

In example embodiments, the upper transistors UT1and UT2may include a string select transistor, and the lower transistors LT1and LT2may include a ground select transistor. The gate lower lines LL1and LL2may be gate electrodes of the lower transistors LT1and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, and the gate upper lines UL1and UL2may be gate electrodes of the upper transistors UT1and UT2, respectively.

In example embodiments, the lower transistors LT1and LT2may include a lower erase control transistor LT1and a ground select transistor LT2connected to each other in series. The upper transistors UT1and UT2may include a string select transistor UT1and an upper erase control transistor UT2connected to each other in series. At least one of the lower erase control transistor LT1and the upper erase control transistor UT1may be used for an erase operation of erasing data stored in the memory cell transistors MCT using a GIDL phenomenon.

The common source line CSL, the first and second gate lower lines LL1and LL2, the word lines WL, and the first and second gate upper lines UL1and UL2may be electrically connected to the decoder circuit1110through first connection interconnections1115extending from the first semiconductor structure1100F to the second semiconductor structure1100S. The bit lines BL may be electrically connected to the page buffer1120through second connection interconnections1125extending from the first semiconductor structure1100F to the second semiconductor structure1100S.

In the first semiconductor structure1100F, the decoder circuit1110and the page buffer1120may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit1110and the page buffer1120may be controlled by the logic circuit1130. The semiconductor device1100may communicate with the controller1200through an input and output pad1101electrically connected to the logic circuit1130. The input and output pad1101may be electrically connected to the logic circuit1130through an input and output connection interconnection1135extending from the first semiconductor structure1100F to the second semiconductor structure1100S.

The controller1200may include a processor1210, a NAND controller1220, and a host interface1230. In example embodiments, the data storage system1000may include a plurality of semiconductor devices1100, and in this case, the controller1200may control the plurality of semiconductor devices1100.

The processor1210may control overall operation of the data storage system1000including the controller1200. The processor1210may operate according to a predetermined firmware, and may access the semiconductor device1100by controlling the NAND controller1220. The NAND controller1220may include a NAND interface1221for processing communication with the semiconductor device1100. Control commands for controlling the semiconductor device1100, data to be written in the memory cell transistors MCT of the semiconductor device1100, and data to be read from the memory cell transistors MCT of the semiconductor device1100may be transmitted through the NAND interface1221. The host interface1230may provide a communication function between the data storage system1000and an external host. When a control command is received from an external host through the host interface1230, the processor1210may control the semiconductor device1100in response to the control command.

FIG.20is a perspective view illustrating a data storage system including a semiconductor device according to an example embodiment.

Referring toFIG.20, a data storage system2000according to an example embodiment may include a main substrate2001, a controller2002mounted on the main substrate2001, one or more semiconductor packages2003, and a DRAM2004. The semiconductor package2003and the DRAM2004may be connected to the controller2002by interconnection patterns2005formed on the main substrate2001.

The main substrate2001may include a connector2006including a plurality of pins coupled to an external host. The number and the arrangement of the plurality of pins in the connector2006may be varied depending on a communication interface between the data storage system2000and the external host. In example embodiments, the data storage system2000may communication with the external host through one of a universal serial bus (USB), a peripheral component interconnect express (PCI-Express), a serial advanced technology attachment (SATA), and an M-phy for universal flash storage (UFS). In example embodiments, the data storage system2000may operate by power supplied from the external host through the connector2006. The data storage system2000may further include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the controller2002and the semiconductor package2003.

The controller2002may write data in the semiconductor package2003or may read data from the semiconductor package2003, and may improve an operating speed of the data storage system2000.

The DRAM2004may be configured as a buffer memory for mitigating a difference in speeds between the semiconductor package2003, a data storage space, and an external host. The DRAM2004included in the data storage system2000may also operate as a cache memory, and may provide a space for temporarily storing data in a control operation for the semiconductor package2003. When the DRAM2004is included in the data storage system2000, the controller2002further may include a DRAM controller for controlling the DRAM2004in addition to the NAND controller for controlling the semiconductor package2003.

The semiconductor package2003may include first and second semiconductor packages2003aand2003bspaced apart from each other. Each of the first and second semiconductor packages2003aand2003bmay be configured as a semiconductor package including a plurality of semiconductor chips2200. Each of the first and second semiconductor packages2003aand2003bmay include a package substrate2100, semiconductor chips2200on the package substrate2100, adhesive layers2300disposed on a lower surface of each of the semiconductor chips2200, a connection structure2400electrically connecting the semiconductor chips2200to the package substrate2100, and a molding layer2500covering the semiconductor chips2200and the connection structure2400on the package substrate2100.

The package substrate2100may be configured as a printed circuit board including package upper pads2130. Each of the semiconductor chips2200may include an input and output pad2210. The input and output pad2210may correspond to the input and output pad1101inFIG.21. Each of the semiconductor chips2200may include gate stack structures3210and channel structures3220. Each of the semiconductor chips2200may include the semiconductor device described with reference toFIGS.1to12.

In example embodiments, the connection structure2400may be a bonding wire electrically connecting the input and output pad2210to the package upper pads2130. Accordingly, in each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may be electrically connected to each other through a bonding wire method, and may be electrically connected to the package upper pads2130of the package substrate2100. In example embodiments, in each of the first and second semiconductor packages2003aand2003b, the semiconductor chips2200may be electrically connected to each other by a connection structure including a through silicon via (TSV), instead of the connection structure2400of a bonding wire method.

In example embodiments, the controller2002and the semiconductor chips2200may be included in a single package. For example, the controller2002and the semiconductor chips2200may be mounted on a separate interposer substrate different from the main substrate2001, and the controller2002may be connected to the semiconductor chips2200by interconnections formed on the interposer substrate.

FIG.21is a cross-sectional view illustrating a semiconductor device according to an example embodiment.FIG.21illustrates an example embodiment of the semiconductor package2003inFIG.20, and illustrates the semiconductor package2003inFIG.20taken along line I-I′.

Referring toFIG.21, in the semiconductor package2003, the package substrate2100may be configured as a printed circuit board. The package substrate2100may include a package substrate body portion2120, package upper pads2130(seeFIG.20) disposed on an upper surface of the package substrate body portion2120, lower pads2125disposed on a lower surface of the package substrate body portion2120or exposed through the lower surface, and internal interconnections2135electrically connecting the package upper pads2130to the lower pads2125in the package substrate body portion2120. The package upper pads2130may be electrically connected to the connection structures2400. The lower pads2125may be connected to the interconnection patterns2005of the main substrate2010of the data storage system2000through conductive connection portions2800as inFIG.20.

Each of the semiconductor chips2200may include a semiconductor substrate3010and a first structure3100and a second structure3200stacked in order on the semiconductor substrate3010. The first structure3100may include a peripheral circuit region including peripheral interconnections3110. The second structure3200may include a common source line3205, a gate stack structure3210on the common source line3205, channel structures3220and separation structures3230penetrating the gate stack structure3210, bit lines3240electrically connected to the channel structures3220, which may be memory channel structures, and gate contact plugs3235electrically connected to the word lines WL (seeFIG.19) of the gate stack structure3210. As described with reference toFIGS.1to12, each of the semiconductor chips2200may include the semiconductor substrate6, the circuit devices20, the pattern structure110, the stacked structure GS including the gate electrodes130, the channel structures CH, and the bit line190. Each of the channel structures CH may include a channel pad150, and the channel pad150may include a first pad layer151and a second pad layer152.

Each of the semiconductor chips2200may include a through interconnection3245electrically connected to the peripheral interconnections3110of the first structure3100and extending into the second structure3200. The through interconnection3245may be disposed on an external side of the gate stack structure3210, and may be further disposed to penetrate the gate stack structure3210. Each of the semiconductor chips2200may further include an input and output pad2210(seeFIG.19) electrically connected to the peripheral interconnections3110of the first structure3100.

According to the aforementioned example embodiments, a channel pad electrically connected to the bit line may include a first pad layer and a second pad layer in contact with the channel layer. The first pad layer may be formed of undoped polysilicon, and may include a region having a low impurity concentration due to impurities diffused from the second pad layer, and the second pad layer may include doped polysilicon having a high impurity concentration. Accordingly, a depletion region may be formed adjacent to the interfacial surface between the first pad layer and the channel layer, and the depletion region may overlap the erase control gate electrode in the horizontal direction. Accordingly, a GIDL current in which transverse BTBT dominates may be generated, and the GIDL generation area may increase by the area of the depletion region overlapping the erase control gate electrode, such that holes may be smoothly supplied into the channel layer during the erase operation. Accordingly, GIDL current generation efficiency may improve, such that a semiconductor device having improved electrical properties and a data storage system including the same may be provided.

Also, by optimizing the thickness and/or shape of the first pad layer, generation of GIDL current in the depletion region may increase during the erase operation, and an ion implantation process may be omitted, thereby reducing process costs. Accordingly, a semiconductor device having improved productivity and a data storage system including the same may be provided.

An example embodiment may provide a semiconductor device having improved electrical properties by improving efficiency of GIDL current generation and having improved productivity by lowering process costs.

An example embodiment may provide a data storage system including a semiconductor device having improved electrical properties by improving efficiency of GIDL current generation and having improved productivity by lowering process costs

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.