Patent ID: 12244314

DETAILED DESCRIPTION

Embodiments described herein provide for the integration of a current ramp to develop and drive a high peak current through an inductive load in a short period of time. An efficient implementation of this integrator is based primarily on three transistors and an integrator capacitor. The simplicity of the design permits faster integration than compared to previous solutions based on traditional operational amplifiers. Furthermore, good linearity is achieved during the integration by compensating for a drain current dependency of a transistor with respect to the transistor gate to source voltage. Specifically, the integrator is temporarily biased to a mid-supply operating point to determine an average drain current of an integrating transistor. The average drain current is determined by a gate to source voltage of a first stage transistor, which is sampled and held for further use. This sampled voltage is subsequently used to force the drain current of the integrator transistor to be constant during integration of a current ramp, thereby ensuring that substantially all of the current from the current ramp flows to the integrator capacitor. The first stage transistor drives a final stage transistor used to drive the inductive load, where a gate of the first stage transistor follows the source voltage of the integrator transistor. Accordingly, the integrator integrates a linear sloped current ramp (t) to provide a quadratic voltage signal (t**2) across the inductive load. The quadratic voltage results in a third order (t**3) current through the inductive load as determined by the equation V=L*di/dt, where V is the applied voltage across the load, L is the inductance of the load, and di/dt is a rate of current change through the load. In one embodiment, the applied voltage across the load ranges from 0-2.5V, over a 6 ns integration cycle resulting in a drive current of 150 mA into a 30 nH inductive load.

FIG.1is a schematic diagram of an integrator circuit100, in accordance with some embodiments. The integrator circuit100can be implemented in various electronic applications including, but by no means limited to, automotive, industrial, and consumer applications including signal processing or battery management systems. One application includes the implementation of a computer chip or related electronic integrator circuit for a communication bus. As shown inFIG.1, the integrator circuit100can drive an inductive load110, for example, a primary coil of a transformer.

As shown inFIG.1, the integrator circuit100may comprise a first transistor102(e.g., the first stage transistor), a second transistor104(e.g., the integrator transistor), a third transistor106(e.g., the final stage transistor), and the integrator capacitor108. In some embodiments, one or more of the first transistor102, second transistor104, and third transistor106may be a Metal—Oxide—Semiconductor Field-Effect Transistor (MOSFET). In other embodiments, one or more of the transistors102,104,106may be an Insulated-Gate Field Effect transistor (IGFET). The three transistors102,104,106may collectively drive a current, (e.g., 150 mA, in the coil in 6 ns), and produce negligible or no input current at the gate of the second transistor104, resulting in the integration of a linear input current with good linearity, high peak current and within the short period of time necessary for driving small inductive loads.

The first transistor102is coupled between a current source122and a ground terminal113. The current source122is coupled to a voltage supply V1112(e.g. 5V). The current source122may provide a source of current, (e.g., 2 mA), to the drain of the first transistor102. The third transistor106has a gate coupled to the drain of the first transistor102and to the current source122, so that the first transistor102may drive the third transistor106. The third transistor106may be configured to drive an inductive load110(e.g, a coil). The third transistor106may have a source coupled to both the integrator capacitor108and the inductive load110and a drain coupled to the voltage supply112.

The gate of the first transistor102may be coupled to a source of the second transistor104and to a current source121connected to the ground terminal113. The current source121, may provide a constant current as a function of a sampled gate to source voltage (not shown) of the first transistor102, determined prior to applying the current ramp to a gate of the second transistor104. As described below, the current source121may provide a constant current to the second transistor104for the duration of the integration of the linear current ramp. In one embodiment, the gate of the second transistor104may be temporarily connected by a switch152(e.g., a transistor) to a voltage supply V2/2103(e.g., 3.0V/2 or 1.5V), prior to integrating the current ramp generated by an input current source120. In another embodiment, the gate of the second transistor104may be temporarily connected to a mid-supply voltage, where the mid-supply voltage is substantially half of a maximum peak current that the integrator circuit100may provide on the output node114.

The input current source120may be coupled to the both the gate of the second transistor104and the integrator capacitor108. The second transistor104is configured so that a source of current from the input current source120flows via an input node (the gate of the second transistor104or “inc”) to the integrator capacitor108resulting in substantially no current flowing to the second transistor104. Specifically, the switch152temporarily biases the gate of the second transistor to a mid-supply, or average operating point of the integrator circuit100, so that the sampled gate to source voltage of the first transistor102, and thus the constant current provided by the current source121, represent an average operating point of the integrator itself.

The first transistor102and the second transistor104are cascaded, resulting in a gate-source voltage (Vg1) of the first transistor102being added to a gate-source voltage (Vg2) of the second transistor104to provide the voltage (Vinc) at the gate input of the second transistor104. The integrator capacitor108also provides feedback from the output node114to the gate of the second transistor104(e.g., the integrator input), similar to a negative feedback loop between an output and inverting input of a conventional operational amplifier. For example, when a voltage at the output node114increases, the gate voltage of104may increase due to capacitive coupling through the integrator capacitor108. This in turn increases the drive current of the second transistor104, which increases the drive current of the first transistor102and reduces the drive current of the third transistor106, thereby countering the increase in the output node114. This provides stability for the integrator circuit100due to transient voltages.

A constant current through the second transistor104is maintained during integration, regardless of a change in voltage Vg1 or voltage Vg2. For example, a decrease in voltage Vg1 at the first transistor102can be compensated for by an increase in voltage Vg2 at the second transistor104so that the combined voltage at the gate of the second transistor104remains unchanged.

FIG.2is a schematic representation of an integrator circuit200, in accordance with another embodiment. As shown, the integrator circuit200can be part of an isolated communication bus or the like, for example, a capacitive isolation line at a transmit side of a transformer of a bus. The integrator circuit200comprises a first transistor202, a second transistor204, a third transistor206, and an integrator capacitor208, which may be the same or similar to the transistors102-106and capacitor108described with reference toFIG.1, but may be configured and arranged in the circuit200in a different manner than the circuit100ofFIG.1. The third transistor206may sink up to 1 mA from the voltage supply112. During the rapid voltage increase required across the inductive load (e.g., coil)210, the gate of the third transistor206is charged through transistors212and214with up to 2 mA of current from the voltage supply112.

A transistor216sets a 1 mA Direct Current (DC) operating point to the third transistor206. The transistor216may be considered a “copy” of the third transistor206, in that the two transistors share similar electrical characteristics (e.g., same polarity and layout), with the exception of gain, determined by a transistor channel width. In an embodiment, the transistor216has 100 times less gain than the third transistor206(e.g., the gate and thus channel width of the transistor206is 100 times wider than the gate of the transistor216). The transistor216is forced to conduct 10 uA though a current source217, which results in a 1 mA bias to the third transistor206due to the 100 times gain difference between the transistor216and the third transistor206. A closed loop is formed with transistors212and214driving the shared gate connection to transistors216and206in response to the drain voltage of the transistor216.

A 2 mA DC operating point of transistors212and214and also transistor202is set in a different manner to the operating point of the third transistor206, by using a transistor203. Similar to the relationship between the transistor216and206, the transistor203is a “copy” of the first transistor202, in that these two transistors have similar electrical characteristics but transistor203is designed with 1/10 of the gain of the first transistor202and has a DC operating point of 200 uA. The transistor203sets the DC operating point of the first transistor202as a consequence of defining the drain to source current (IDS) of the second transistor204and ensuring that the IDS of the second transistor204remains constant during the integration of the input current ramp applied to the gate of the second transistor204. The transistor203is used to define a constant IDS current through the second transistor204with a sample and hold process defined below.

The transistor203has a DC operating point of 200 uA as a result of a current source205being mirrored with p-type transistors221and222, where a gain of transistor222is 10 times larger than a gain of the transistor221. The drain voltage of the p-type transistor221drives the gate of a transistor224. A resulting current though a branch formed by transistors224,226and228is mirrored with a current mirror formed by transistors228and229, thereby forcing a constant IDS current through the second transistor104defined by the gate voltage of transistor203.

An input current source209, similar to the current source120ofFIG.1is configured to source a linear sloped current ramp to the gate of the second transistor204during an integration phase, following a preset phase used to set an operating point of the integrator circuit200. An example of the input current source209is described below with reference toFIG.7. In one embodiment, the input current source209is activated by opening a switch S2252.

In one example, the transistors226and214are biased to 3V, thus providing sufficient “voltage headroom” for the current mirror formed by transistors221and222and thereby an effective output range of 3V for driving the inductive load210. During the preset phase, the gate input to the second transistor204is shorted to a mid-supply voltage level201(e.g., 1.5V) by the switch S2252and further stored across the integrator capacitor208to establish an average DC operating value for the integrator circuit200. The gate to source voltage (VGS) of transistor203and the capacitor207connected thereto is set to be the same as the VGS of the first transistor202by closing a switch S1formed by transistor251to connect the respective gates of transistors202and203. Subsequently, the switch S1251is opened to “sample” the VGS voltage of the first transistor202and “hold” it across the capacitor207. Accordingly, the VGS voltage of the transistor203, set by the stored voltage on the capacitor207establishes a fixed current through the second transistor204and transistor229representing an average DC bias of the integrator circuit100, which remains constant regardless of VGS voltage variations in the second transistor204during a subsequent integration phase.

The integration phase begins by opening the switch S2252and activating the input current source209. In one embodiment the input current source is activated by opening a similar S2switch within the input current source209. In the embodiment shown inFIG.2, the switch S1251is opened (e.g., turned off) by transitioning a gate voltage of the switch S1251from 1.5V (voltage201) to 0V (ground113). The switch S2252is opened (e.g., turned off) by transitioning a gate voltage of the switch252from 3.0V (voltage103) to 1.5V (voltage201).

During the integration phase the VGS of the first transistor202and the second transistor204will vary, however the IDS current through the second transistor204will remain constant due to the current mirror including transistor229forcing a constant current set by the sampled voltage on the capacitor207during the preset phase. Accordingly, the voltage sum (Vinc ofFIG.1) of the VGS of the transistors202and204will remain constant and thus substantially all of the current sourced by the input current source209will flow to the capacitor208to provide a quadratic voltage (t**2) across the inductive load210.

Specifically, as current is sourced from transistor214towards the gate of the third transistor206(e.g., from 0 mA up to 1.5 mA), a corresponding reduction in current flows through the first transistor202(e.g., from 2 mA down to 0.5 mA). This reduction in IDS current of the first transistor202will cause a reduction in VGS of the first transistor with a corresponding increase in VGS of the second transistor. Thus, the source voltage the second transistor204will ramp linearly in proportion to the input current ramp from the input current source209, as the current mirror including transistor229forces the constant IDS current through the second transistor204. In one embodiment, the integration current of up to 700 uA, integrated across the capacitor208(e.g., a 1 pF capacitor), provides the desired quadratic (t**2) voltage waveform up to 2.5V across a 30 nH inductive load210. The inductive load210thus sinks up to 150 mA with a third order current waveform (t**3).

With reference toFIGS.3A and3Band continued reference toFIG.2, the switch S1251is opened to sample and hold the VGS voltage of transistor202. Shortly thereafter, the switch S2252is opened to disconnect the 1.5V voltage bias from the second transistor204and start the integration phase. In one embodiment, the input current source209is activated with the same S2signal controlling the switch252. FIG.FIG.3Ashows the voltage across the inductive load210reaching a maximum approximately 6 ns after the switch S2252is opened. This maximum is shown at approximately 10 ns (tend). Once the voltage across the inductive load210has settled, the S1switch251is closed to start a new cycle including a new preset and integration phase.

FIG.4illustrates various voltage output waveforms that could be generated by an integrator circuit to drive an inductive load. Specifically, a square, linear and quadratic (t**2) voltage waveform is shown. The quadratic voltage waveform is used by embodiments of the present disclosure because this waveform affords a longer integration cycle (e.g., 6 ns) to reach the same peak voltage.FIG.5with continued reference toFIG.4, shows corresponding current waveforms flowing through the inductive load with a third order (t**3 or “t3”) being used by the present disclosure to extend the integration cycle to 6 ns. As discussed above a square voltage waveform across an inductive load results in a linear sloped ramp (t) current through the same load. A linear sloped voltage waveform (t) results in a quadratic current waveform (t**2). A quadratic voltage waveform (t**2) results in a third order current waveform (t**3).

FIG.6with reference toFIG.2shows various overlayed currents and voltages formed in the integrator circuit (e.g.,FIG.1orFIG.2) during the integration phase to further illustrate at least some of the advantages taught by the present disclosure. Waveform A shows one embodiment of a linear current ramp rising to 140 uA as sourced by the input current source209. The waveform A is provided for illustrative purposes. In other embodiments, the Waveform A may show a ramp up to 700 uA with an elapsed integration time of 6 ns, or total elapsed time of approximately 9 ns. Waveform B shows the gate input voltage of transistor204(Vinc) without the benefit of forcing a constant IDS current through transistor204during the integration phase. In contrast to Waveform B, Waveform C shows a near constant gate input voltage to the transistor204. Similarly, Waveforms D and E show the generated voltages across the inductive load210respectively with and without the constant IDS current forced through transistor204during the integration phase. Lastly, Waveform F shows an ideal voltage waveform across the inductive load210, showing a larger developed voltage and a quadratic shape more closely matching that of Waveform E than Waveform F. With respect to Waveform D, almost 0.7V of peak voltage amplitude is lost due to integration current flowing to the gate of transistor204.

FIG.7is a schematic representation of an input current source500for generating a linear current ramp, (e.g., the input current source209) in accordance with an embodiment of the present disclosure. Prior to activating the input current source500by opening the transistor (clamp)532, all the active transistor components are biased (e.g., transistors532,533,534,535,537and539), while the passive components are not. This is done, to allow quick activation of the input current source500. Specifically, the capacitor538is shorted, and the current sources530and531are chosen to source the same current to substantially eliminate current flow through the resistor540. When the transistor532is opened (e.g., shut off with signal A or in some embodiments signal S2ofFIG.2), the transistor535will force a linear ramp across the capacitor538, according to the equation I=C*dv/dt, where I is the current from the current source531, C is capacitance of capacitor538and dv/dt is the rate of voltage change across the capacitor538. The resistor540being electrically in parallel with the capacitor538will receive the same linear current ramp. The drain of transistor537provides a linear current ramp (mirrored from the current flowing through the resistor540and transistor539) and may be coupled to the gate of the second transistor204ofFIG.2.

FIG.8AandFIG.8Bshow respective current and voltage waveforms for the embodiment ofFIG.7. InFIG.8A, the current source531sources 25 uA to form a current ramp through the resistor540of up to 80 uA. The gain of the current mirror formed by transistors537and539thus provides a current output ramping to 200 uA. In other embodiments, the current of the current source531and/or the gain of the current mirror formed by transistors537and539may be adjusted to provide a current ramp of 700 uA or other suitable current maximum suited to the integrator circuit.FIG.8Bshows the ramped voltage at the source of the transistor535corresponding to the generated currents ofFIG.8A, starting at 1 ns and ending at 7 ns, for an elapsed time of 6 ns.

As will be appreciated, as least some of the embodiments as disclosed include at least the following embodiments. In one embodiment, an apparatus comprises a first transistor comprising a first gate, a first drain and a first source. A second transistor comprises a second gate, a second drain and a second source, the second gate coupled to a first current source configured to generate a linear current ramp, the second source coupled to the first gate and a second current source configured to generate a constant current through the second transistor determined by a sampled voltage between the first gate and the first source. A third transistor comprises a third gate, a third drain and a third source, the third gate coupled to the first drain, and the third source coupled to an inductive load, wherein the third transistor is configured to source a load current to the inductive load in response to an integration of the linear current ramp. A first capacitor is coupled between the third source and the second gate, the capacitor configured to integrate the linear current ramp.

Alternative embodiments of the apparatus include one of the following features, or any combination thereof. The second drain is coupled to a first voltage supply and the third drain is coupled to a second voltage supply, wherein the first voltage supply supplies a first voltage less than a second voltage of the second voltage supply. The first voltage is less than a peak value of the quadratic voltage. The second gate is preset to a voltage by a switch between the second gate and a voltage supply configured to supply the voltage, wherein the voltage is less than a peak value of the quadratic voltage. A replica transistor comprises a replica gate, a replica drain and replica source, the replica gate is switchably coupled to the first gate with a switch, the replica source is coupled to the first source and the replica drain coupled to a current mirror coupled to the second current source. A second capacitor is coupled to the replica gate, the second capacitor is configured to store the sampled voltage when the first switch is open. The first current source begins ramping the linear current ramp in response to an opening of a switch between the second gate and a voltage supply. The first current source comprises a plurality of transistors, a timing resistor and a timing capacitor, the first current source configured to bias each of the transistors, short the timing capacitor and minimize a current flow the timing resistor in response to a closing of a switch between the second gate a voltage supply. A replica transistor comprises a replica gate and a replica drain, the replica gate coupled to the third gate, the replica drain coupled to a current source and a feedback transistor coupled to the third gate, a first ratio of a constant third current supplied to the third drain divided by a current of the current source being defined by a second ratio of a first gain of the third transistor divided by a second gain of the replica transistor.

In another embodiment, an apparatus comprises a first transistor comprising a first gate, a first drain and a first source. A second transistor comprises a second gate and a second source, the second gate coupled to a first current source configured to generate a linear current ramp, the second source coupled to the first gate and a second current source configured to generate a constant current through the second transistor determined by a sampled voltage between the first gate and the first source. A third transistor comprises a third gate and a third source, the third gate coupled to the first drain, and the third source coupled to an inductive load, wherein the third transistor is configured to source a load current to the inductive load in response to an integration of the linear current ramp. A first capacitor is coupled between the third source and the second gate, wherein the sampled voltage is held on a second capacitor coupled to a replica gate of a replica transistor, the replica gate switchably connected to the second gate with a first switch, and a replica drain of the replica transistor coupled to a current mirror, the current mirror coupled to the second current source.

Alternative embodiments of the apparatus include one of the following features, or any combination thereof. The second gate is switchably coupled to a voltage supply with a second switch prior to the integration. The first switch is closed during a preset phase and the sampled voltage is sampled during the preset phase. The first switch is opened during the integration. The second switch is opened during the integration. The first current source begins ramping the linear current ramp in response to an opening of a second switch between the second gate and a voltage supply. A first switch is opened before opening a second switch coupled between the second gate and a voltage supply.

In another embodiment, an apparatus comprises a first transistor comprising a first gate, a first drain and a first source. A second transistor comprises a second gate and a second source, the second gate coupled to a first current source configured to generate a linear current ramp, the second source coupled to the first gate and a second current source configured to generate a constant current through the second transistor determined by a sampled voltage between the first gate and the first source. A third transistor comprises a third gate and a third source, the third gate coupled to the first drain, and the third source coupled to a load, wherein the third transistor is configured to source a load current to the load in response to an integration of the linear current ramp. A first capacitor is coupled between the third source and the second gate, wherein the sampled voltage is held on a second capacitor coupled to a replica gate of a replica transistor, the replica gate switchably connected to the second gate with a first switch, and a replica drain of the replica transistor coupled to a current mirror, the current mirror coupled to the second current source, and wherein the second gate is switchably coupled to a voltage supply with a second switch prior to the integration.

Alternative embodiments of the apparatus include one of the following features, or any combination thereof. The load is an inductive load. The load current from the third transistor generates a quadratic voltage across the load. An integrator input voltage on the second gate is constant during the integration.

Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.

Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.