Patent ID: 12199138

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

FIG.1Ais a cross-sectional view of a semiconductor device according to some example embodiments of the disclosure.FIG.1Bis an enlarged view of a portion E1ofFIG.1A.FIG.1Cis an enlarged view of a portion E2ofFIG.1A.FIG.1Dis an enlarged view of a portion E3ofFIG.1A.

Referring toFIG.1A, the semiconductor device may include a substrate100. In some embodiments, the substrate100may be a semiconductor substrate or a semiconductor-on-insulator substrate. For example, the substrate100may include silicon, germanium, silicon-germanium, GaP, or GaAs. In some embodiments, the substrate100may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. The substrate100may have the form of a plate extending along a plane defined by a first direction D1and a second direction D2. The first direction D1and the second direction D2may intersect each other. For example, the first direction D1and the second direction D2may be horizontal directions intersecting each other.

An interlayer insulating layer110covering the substrate100may be provided. In some embodiments, the interlayer insulating layer110may be a multilayer insulating layer including a plurality of insulating layers.

Capacitor contact structures120extending through the interlayer insulating layer110may be provided. The capacitor contact structures120may be connected to the substrate100. In some embodiments, the capacitor contact structure120may be connected to an impurity region formed in the substrate100. In some embodiments, each capacitor contact structure120may be a multilayer conductive layer including a plurality of conductive layers. The capacitor contact structures120may include, for example, tungsten.

A capacitor structure130may be provided on the interlayer insulating layer110. The capacitor structure130may be electrically connected to the capacitor contact structures120. The capacitor structure130may be electrically connected to the substrate100via the capacitor contact structures120. The capacitor structure130may include lower electrodes LE, interfacial layers IF, a capacitor insulating layer CI, supporters SU, and an upper electrode UE.

The lower electrodes LE may have the form of a pillar extending in a third direction D3. The lower electrode LE may be connected to the capacitor contact structure120. The supporters SU may support the lower electrodes LE. A sidewall of the supporter SU may contact a sidewall LE_S of the lower electrode LE and, as such, the supporter SU may support the sidewall LE_S of the lower electrode LE. A plurality of supporters SU may support one lower electrode LE. The plurality of supporters SU supporting one lower electrode LE may be disposed at different levels.

The interfacial layers IF may cover the lower electrodes LE. The interfacial layers IF may surround the lower electrodes LE, respectively. The interfacial layer IF may contact the side wall LE_S and a top surface LE_T of the lower electrode LE. The supporter SU may contact the side wall LE_S of the lower electrode LE while extending through the interfacial layer IF.

The capacitor insulating layer CI may cover the interfacial layers IF, the supporters SU, and the interlayer insulating layer110. The capacitor insulating layer CI may surround the lower electrodes LE, the interfacial layers IF, and the supporters SU. The capacitor insulating layer CI may contact a top surface IF_T and an outer sidewall IF_OS of the interfacial layer IF. The capacitor insulating layer CI may contact a top surface SU_T and a bottom surface SU_B of the support SU. The capacitor insulating layer CI may contact a top surface of the interlayer insulating layer110. The interfacial layer IF may be interposed between the lower electrode LE and the capacitor insulating layer CI. In some embodiments, the capacitor insulating layer CI may be a multilayer insulating layer. The capacitor insulating layer CI may include, for example, an oxide.

The upper electrode UE may cover the capacitor insulating layer CI. The upper electrode UE may surround the lower electrodes LE, the interfacial layers IF, and the supporters SU. Portions of the interfacial layer IF and the capacitor insulating layer CI may be interposed between the upper electrode UE and the lower electrode LE. The upper electrode UE may include, for example, TiN, TiNbN, or TiSiN.

The lower electrode LE may include a first surface SF1. The first surface SF1may be a surface of the lower electrode LE contacting the interfacial layer IF. The first surface SF1may include the top surface LE_T and the sidewall LE_S of the lower electrode LE.

The interfacial surface IF may include a second surface SF2. The second surface SF2may be a surface of the interfacial surface IF contacting the lower electrode LE. The second surface SF2may include an inner sidewall IF_IS and an inner connection surface IF_IC of the interfacial surface IF. The inner sidewall IF_IS of the interfacial layer IF may be a surface contacting the sidewall LE_S of the lower electrode LE. The inner connection surface IF_IC of the interfacial layer IF may be a surface contacting the top surface LE_T of the lower electrode LE. The inner connection surface IF_IC of the interfacial layer IF may be a surface connected to the inner sidewall IF_IS of the interfacial layer IF.

The interfacial layer IF may include a third surface SF3. The third surface SF3may be a surface of the interfacial surface IF contacting the capacitor insulating layer CI. The third surface SF3may include the top surface IF_T and the outer sidewall IF_OS of the interfacial layer IF.

Referring toFIG.1B, the interfacial layer IF may include first metal materials M1, first bonding materials BO1, and halogen materials HA. The first bonding material BO1and the halogen material HA may be bonded to the first metal material M1. In the interfacial layer IF, the number of the first bonding materials BO1may be greater than the number of the halogen materials HA.

The first metal materials M1may be identical metal elements. For example, the first metal materials M1may be one of Nb, Ti, Zr, Hf, In, Al, Sr, Ba, Y, La, or Gd.

The halogen materials HA of the interfacial layer IF may be identical halogen elements. For example, the halogen materials HA of the interfacial layer IF may be one of F, Cl, I, or Br.

The first bonding materials BO1may be nonmetal elements different from the halogen material HA. In some embodiments, the first bonding materials BO1may be identical nonmetal elements. For example, the first bonding materials BO1may be O. In some embodiments, the first bonding materials BO1may be different nonmetal elements. For example, a part of the first bonding materials BO1may be O, and the remaining part of the first bonding material BO1may be N.

The halogen materials HA of the interfacial layer IF may be disposed adjacent to the lower electrode LE. The halogen materials HA of the interfacial layer IF may be disposed nearer to the lower electrode LE than to the capacitor insulating layer CI. The halogen materials HA of the interfacial layer IF may be disposed adjacent to the second surface SF2of the interfacial layer IF. The halogen materials HA of the interfacial layer IF may be disposed nearer to the second surface SF2of the interfacial layer IF than to the third surface SF3of the interfacial layer IF. The halogen materials HA of the interfacial layer IF may define the second surface SF2of the interfacial layer IF. In other words, the halogen materials HA of the interfacial layer IF may be at least a part of materials constituting the second surface SF2of the interfacial layer IF. The halogen materials HA of the interfacial layer IF may be exposed to the second surface SF2of the interfacial layer IF. The interfacial layer IF may include halogen materials HA at the second surface SF2. The first bonding materials BO1may be disposed in the entirety of the interfacial layer IF.

In example embodiments of the disclosure, bonding relation and disposition of the first metal materials M1, the first bonding materials BO1and the halogen materials HA of the interfacial layer IF are not limited to those of the shown case. In some example embodiments of the disclosure, the numbers of first bonding materials BO1and halogen materials HA bonded to the first metal material M1are not limited to four.

The lower electrode LE may include second metal materials M2, second bonding materials BO2, and halogen materials HA. The second bonding material BO2and the halogen material HA may be bonded to the second metal materials M2. In the lower electrode LE, the number of the second bonding materials BO2may be greater than the number of the halogen materials HA. In example embodiments of the disclosure, materials included in the lower electrode LE are not limited to those of the shown case. In some embodiments, the lower electrode LE may not include halogen materials HA.

In some embodiments, the second metal materials M2may be identical metal elements. For example, the second metal materials M2may be Ti. In some embodiments, the second metal materials M2may be different metal elements. For example, a part of the second metal materials M2may be Ti, and the remaining part of the second metal materials M2may be Si. In another example, a part of the second metal materials M2may be Ti, and the remaining part of the second metal materials M2may be Nb.

The halogen materials HA of the lower electrode LE may be identical halogen elements. The halogen materials HA of the lower electrode LE may be halogen elements identical to the halogen materials HA of the interfacial layer IF.

The second bonding materials BO2may be nonmetal elements different from the halogen material HA. In some embodiments, the second bonding materials BO2may be identical elements. For example, the second bonding materials BO2may be N. In some embodiments, the second bonding materials BO2may different elements. For example, a part of the second bonding materials BO2may be N, and the remaining part of the second bonding materials BO2may be O.

In some embodiments, the second bonding materials BO2may be nonmetal elements different from the first bonding materials BO1. For example, the second bonding materials BO2may be N, and the first bonding materials BO1may be O.

The halogen materials HA of the lower electrode LE may be disposed adjacent to the interfacial layer IF. The halogen materials HA of the lower electrode LE may be disposed nearer to the interfacial layer IF than to a center LE_CT (seeFIG.1A) of the lower electrode LE. The halogen materials HA of the lower electrode LE may be disposed adjacent to the first surface SF1of the lower electrode LE. The halogen materials HA of the lower electrode LE may be nearer to the first surface SF1of the lower electrode LE than to the center LE_CT of the lower electrode LE. The halogen materials HA of the lower electrode LE may define the first surface SF1of the lower electrode LE. In other words, the halogen materials HA of the lower electrode LE may be at least a part of materials constituting the first surface SF1of the lower electrode LE. The halogen materials HA of the lower electrode LE may be exposed to the first surface SF1of the lower electrode LE. The lower electrode LE may include halogen materials HA at the first surface SF1. The second bonding materials BO2may be disposed in the entirety of the lower electrode LE.

In example embodiments of the disclosure, bonding relation and disposition of the second metal materials M2, the second bonding materials BO2and the halogen materials HA of the lower electrode LE are not limited to those of the shown case. In example embodiments of the disclosure, the numbers of second bonding materials BO2and halogen materials HA bonded to the second metal material M2are not limited to four.

In some embodiments, a halogen material HA bonded to both the first metal material M1and the second metal material M2may be provided.

Referring toFIG.1C, the supporter SU may include third metal materials M3, third bonding materials BO3, and halogen materials HA. The third bonding material BO3and the halogen material HA may be bonded to the third metal material M3. In the supporter SU, the number of the third bonding materials BO3may be greater than the number of the halogen materials HA. In example embodiments of the disclosure, materials included in the supporter SU are not limited to those of the shown case. In some embodiments, the supporter SU may not include halogen materials HA.

The third metal materials M3may be identical metal elements. For example, the third metal materials M3may be Si. The third metal materials M3may have higher electron affinity than the first and second metal materials M1and M2. For example, the third metal materials M3may be Si, and the first and second metal materials M1and M2may be Ti having lower electron affinity than Si. In some embodiments, the interlayer insulating layer110(seeFIG.1A) may include the same metal material as the third metal material M3.

The halogen materials HA of the supporter SU may be identical halogen elements. The halogen materials HA of the supporter SU may be halogen elements identical to the halogen materials HA of the interfacial layer IF and the lower electrode LE.

The third bonding materials BO3may be nonmetal elements different from the halogen material HA. In some embodiments, the third bonding materials BO3may be identical elements. For example, the third bonding materials BO3may be one of C, O or N. In some embodiments, the third bonding materials BO3may be different elements. For example, a part of the third bonding materials BO3may be N, and the remaining part of the third bonding materials BO3may be C.

The halogen materials HA of the supporter SU may be disposed adjacent to the top surface SU_T of the supporter SU. The halogen materials HA of the supporter SU may be disposed nearer to the top surface SU_T than to a center SU_CT (seeFIG.1A) of the supporter SU. Similarly, the halogen materials HA of the supporter SU may be disposed adjacent to the bottom surface SU_B (seeFIG.1A) of the supporter SU.

Referring toFIG.1D, the supporter SU may include connection surfaces SU_C. The connection surfaces SU_C may be a surface interconnecting the top surface SU_T and a side surface SU_S of the supporter SU or a surface interconnecting the bottom surface SU_B and the side surface SU_S of the supporter SU. The connection surfaces SU_C may be curved.

The connection surfaces SU_C may contact the interfacial surface IF. The interfacial surface IF may include interposition portions IN. Each of the interposition portions IN may be interposed between the connection surface SU_C and the sidewall LE_S of the lower electrode LE. The width in the first direction D1of each of the interposition portions IN may be gradually reduced as the interposition portion IN extends toward the side wall SU_S of the supporter SU.

In some embodiments, an empty space may be provided between the connection surface SU_C and the lower electrode LE. The empty space may be adjacent to the side wall SU_S of the supporter SU. When the size of a material for forming the interfacial layer IF is relatively great, the empty space may be formed.

The semiconductor device according to example embodiments may include the interfacial layer IF selectively covering the lower electrode LE and, as such, dielectric characteristics of the capacitor structure CT may be enhanced. As the interfacial layers IF respectively covering the lower electrodes LE are not interconnected, the lower electrodes LE may be completely electrically isolated from one another. Accordingly, a leakage phenomenon of the capacitor structure130may be limited and/or prevented.

FIG.2is a flowchart explaining a method for manufacturing a capacitor structure in accordance with some example embodiments of the disclosure.FIGS.3,4A,5A, and6are cross-sectional views explaining a method for manufacturing a capacitor structure in accordance with some example embodiments of the disclosure.FIG.4Bis an enlarged view of a portion E4ofFIG.4A.FIG.4Cis an enlarged view of a portion E5ofFIG.4A.FIG.5Bis an enlarged view of a portion E6ofFIG.5A.FIG.5Cis an enlarged view of a portion E7ofFIG.5A.

Referring toFIGS.2and3, a semiconductor device manufacturing method according to some example embodiments of the disclosure may include forming a substrate100, an interlayer insulating layer110, a capacitor contact structure120, and a capacitor structure130.

The interlayer insulating layer110may be formed on the substrate100, and the capacitor contact structure120, which extends through the interlayer insulating layer110, may be formed on the substrate100. The capacitor structure130may be formed on the capacitor contact structure120.

Forming the capacitor structure130may include forming a lower electrode and a supporter (S100), surface-processing the lower electrode and the supporter (S200), forming an interfacial layer (S300), forming a capacitor insulating layer (S400), and forming an upper electrode (S500).

Lower electrodes LE, which are connected to capacitor contact structures120, may be formed, and supporters SU supporting the lower electrodes LE may be formed (S100). The lower electrodes LE may include second metal materials M2(seeFIG.1B), and second bonding materials BO2(seeFIG.1B) bonded to the second metal materials M2. The supporters SU may include third metal materials M3(seeFIG.1C) and third bonding materials BO3(seeFIG.1C) bonded to the third metal materials M3.

Referring toFIGS.2,4A,4B, and4C, the lower electrodes LE and the supporters SU may be surface-processed (S200). The lower electrodes LE and the supporters SU may be surface-processed through supply of a first source501. The first source SO1may react with the lower electrodes LE and the supporters SU.

The first source SO1may include a halogen compound. For example, the first source SO1may be a gas or plasma including BF3, AlF3, GaF3, InF3, PF3, PF5, AsF3, SbF3, SbF5, SiF4, GeF4, TiF4, TaF5, WF6, WOF4, HfF4, CdF2, SeF6, SeF4, TeF4, TeF6, NF3, CF4, CHF3, CH3F, C2F6, C4F8, SF6, or a combination thereof, or may be a liquid including NH4F, HF, or a combination thereof. In another example, the first source SO1may include a chlorine compound, an iodine compound, or a bromine compound.

As the first source SO1reacts with the lower electrodes LE and the supporters SU, a halogen element included in the first source SO1may be bonded to the second metal material M2of the lower electrode LE or the third metal material M3of the supporter SU. As the halogen element is bonded to the second metal material M2of the lower electrode LE, a halogen material HA of the lower electrode LE may be formed. As the halogen element is bonded to the third metal material M3of the supporter SU, a halogen material HA of the supporter SU may be formed.

Halogen materials HA of the lower electrode LE may be adjacent to a first surface SF1of the lower electrode LE. Halogen materials HA of the supporter SU may be adjacent to a top surface SU_T and a bottom surface SU_B (seeFIG.1A) of the supporter SU.

In some embodiments, the halogen element may be bonded to a metal material of the interlayer insulating layer110, thereby forming a halogen material in the interlayer insulating layer110.

Referring toFIGS.2,5A,5B, and5C, an interfacial layer IF may be formed (S300). Forming the interfacial layer IF (S300) may include performing an atomic layer deposition (ALD) process for repeatedly executing an ALD cycle. The ALD cycle may include supplying a second source SO2, purging the second source SO2, supplying a reactive gas RG, and purging the reactive gas RG.

The second source SO2may include a metal compound including a metal element and ligands binding to the metal element. The metal element of the second source SO2may be, for example, one of Nb, Ti, Zr, Hf, In, Al, Sr, Ba, Y, La, or Gd. The ligands of the second source SO2may be, for example, an amine compound or a cyclopentadienyl(C5H5).

As the second source SO2is supplied, the supplied second source SO2may selectively react with the lower electrodes LE. As the second metal materials M2included in the lower electrode LE have lower electron affinity than the third metal materials M3included in the supporter SU, the metal element included in the second source SO2may be selectively bonded to the halogen material HA of the lower electrode LE, but may not be bonded to the halogen material HA of the supporter SU. As the metal element of the second source SO2is bonded to the halogen material HA of the lower electrode LE, a first metal material M1may be formed.

In some embodiments, a part of the halogen materials HA of the lower electrode LE may be bonded to the metal element of the second source SO2, and the remaining part of the halogen materials HA of the lower electrode LE may not be bonded to the metal element of the second source SO2. In some embodiments, all of the halogen materials HA of the lower electrode LE may be bonded to the metal element of the second source SO2.

The second source SO2may be purged, and the reactive gas RG may be supplied. The reactive gas RG may include a nonmetal element bondable to the first metal material M1. For example, the reactive gas RG may be O2, O3or H2O gas. In accordance with supply of the reactive gas RG, the nonmetal element of the reactive gas GR may be bonded to the first metal material M1, and ligands may be detached from the first metal material M1. As the nonmetal element of the reactive gas RG is bonded to the first metal material M1, a first bonding material BO1may be formed.

The reactive gas RG may be purged, and the ALD cycle may be repeated, thereby again supplying the second source SO2. The supplied second source SO2may selectively react with first bonding materials BO1. As first metal materials M1have lower electron affinity than the third metal materials M3included in the supporter SU, the metal element included in the second source SO2may be selectively bonded to the first bonding material BO1, but may not be bonded to the halogen material HA of the supporter SU. As the metal element of the second source SO2is bonded to the first bonding materials BO1, a first metal material M1may be formed.

As the ALD cycle of the ALD process is repeated, as described above, the interfacial layer IF, which includes first metal materials M1, first bonding materials BO1and a halogen material HA, may be selectively formed on the lower electrode LE, but may not be formed on the supporter SU. In some embodiments, no interfacial layer IF may be formed on the interlayer insulating layer110, similarly to the supporter SU.

Referring toFIGS.2and6, a capacitor insulating layer CI may be formed (S400). The capacitor insulating layer CI may be formed on interfacial layers IF and supporters SU. In some embodiments, a part of the halogen materials HA included in the supporters SU may be removed in a process of forming the capacitor insulating layer CI. In some embodiments, all of the halogen materials HA included in the supporters SU may be removed in the process of forming the capacitor insulating layer CI.

Referring toFIGS.2and1A, an upper electrode UE may be formed on the capacitor insulating layer CI (S500).

The method for manufacturing the capacitor structure130in accordance with example embodiments may include surface-processing the lower electrode LE and the supporter SU and, as such, may selectively form the interfacial layer IF on the lower electrode LE. Accordingly, interfacial layers IF respectively covering lower electrodes LE may be separated from one another without execution of a process of etching the interfacial layers IF and, as such, time and costs may be reduced.

FIG.7is a flowchart explaining an interfacial layer formation method according to some example embodiments of the disclosure.FIG.8is a cross-sectional view explaining the interfacial layer formation method according to example embodiments of the disclosure.

Referring toFIGS.7and8, in the interfacial layer formation method according to example embodiments of the disclosure, forming an interfacial layer (S200a) may include forming a preliminary interfacial layer covering a lower electrode and a supporter (S210a), and etching the preliminary interfacial layer, thereby forming the interfacial layer (S220a).

Similar to the case described with reference toFIG.3, a substrate100a, an interlayer insulating layer110a, a capacitor contact structure120a, lower electrodes LEa, and supporters SUa may be formed. Thereafter, the lower electrodes Lea and the supporters SUa may be surface-processed, similarly to the case described with reference toFIGS.4A,4B, and4C.

Subsequently, a preliminary interfacial layer pIF covering the lower electrodes LEa and the supporters SUa may be formed (S210a). The preliminary interfacial layer pIF may cover the lower electrodes LEa, the supporters SUa, and the interlayer insulating layer110a.

The preliminary interfacial layer pIF may include a first portion PO1covering the lower electrode LEa, a second portion PO2covering the supporter SUa, and a third portion PO3covering the interlayer insulating layer110a. The thickness of the first portion PO1may be greater than the thickness of the second portion PO2and the thickness of the third portion PO3.

When the number of repetition times of an ALD cycle in an ALD process for formation of the preliminary interfacial layer pIF is relatively great, the preliminary interfacial layer pIF may be formed to have a relatively small thickness on the supporter SUa and the interlayer insulating layer110a.

The preliminary interfacial layer pIF may be etched, thereby forming an interfacial layer (S220a). In accordance with etching of the preliminary interfacial layer pIF, the second and third portions PO2and PO3of the preliminary interfacial layer pIF may be removed and, as such, the preliminary interfacial layer pIF may be divided, thereby forming interfacial layers.

FIG.9Ais a plan view of a semiconductor device according to example embodiments of the disclosure.FIG.9Bis a cross-sectional view taken along line A1-A1′ inFIG.9A.FIG.9Cis a cross-sectional view taken along line B1-B1′ inFIG.9A.

Referring toFIGS.9A,9B, and9C, the semiconductor device may include a substrate100b.

The substrate100bmay include active patterns AP. Upper portions of the substrate100bprotruding in a third direction D3may be defined as the active patterns AP. The active patterns AP may be spaced apart from one another.

An element isolation layer STI may be provided in a space provided among the active patterns AP. The active patterns AP may be defined by the element isolation layer STI. Each of the active patterns AP may be surrounded by the element isolation layer STI. The element isolation layer STI may include an insulating material. For example, the element isolation layer STI may include an oxide.

Gate structures GT extending in a second direction D2may be provided. The gate structures GT may be spaced apart from one another in a first direction D1. The gate structure GT may be provided on the element isolation layer STI and the active patterns AP. The gate structure GT may be a buried gate structure buried in the active patterns AP and the element isolation layer STI. The active patterns AP may include impurity regions. A cell transistor including the gate structure GT and the impurity regions of the active pattern AP may be defined.

Each of the gate structures GT may include a gate insulating layer GI, a gate electrode GE, and a gate capping layer GP. The gate insulating layer GI may cover surfaces of the active patterns AP and the element isolation layer STI. The gate electrode GE and the gate capping layer GP may be provided inside the gate insulating layer GI. The gate electrode GE may be spaced apart from the active pattern AP by the gate insulating layer GI. The gate capping layer GP may cover a top surface of the gate electrode GE. The gate insulating layer GI and the gate capping layer GP may include an insulating material. The gate electrode GE may include a conductive material.

Bit line structures BT extending in the first direction D1may be provided. The bit line structures BT may be spaced apart from one another in the second direction D2. The bit line structure BT may be electrically connected to the active pattern AP.

Each of the bit line structures BT may include a bit line BL, a bit line capping layer BP, and bit line spacers BS. The bit line BL may be connected to the active pattern AP. The bit line BL may include a conductive material. The bit line capping layer BP may be provided on the bit line BL. The bit line capping layer BP may include an insulating material. The bit line spacers BS may be provided at opposite sides of the bit line BL and the bit line capping layer BP. The bit line spacers BS may include an insulating material.

An interlayer insulating layer110bcovering the substrate100b, the gate structures GT and the bit line structures BT may be provided. The interlayer insulating layer110bmay include first and second insulating patterns111and112, insulating fences113, a separation pattern114, and an etch stop layer115.

Capacitor contact structures120b, which are connected to the active patterns AP of the substrate100b, may be provided. Each of the capacitor contact structures120bmay include a buried contact BC and a landing pad LP.

First and second insulating patterns111and112may be provided on the substrate100b. The second insulating pattern112may be provided on the first insulating pattern111. The first and second insulating patterns111and112may include different insulating materials, respectively.

The insulating fences113may be provided on the gate capping layer GP of the gate structure GT. The insulating fence113may be provided between adjacent ones of the bit line structures BT. The insulating fence120may include an insulating material.

The buried contact BC may be connected to the active pattern AP. The buried contact BC may be provided between adjacent ones of the insulating fences113. The buried contact BC may include a conductive material.

The landing pad LP may be provided on the buried contact BC. The landing pad LP may be provided between adjacent ones of the insulating fences113. The landing pad LP may be electrically connected to the active pattern AP via the buried contact BC. The landing pad LP may include a conductive material. In some embodiments, the landing pad LP may include a diffusion barrier layer. In some embodiments, a metal silicide layer may be provided between the landing pad LP and the buried contact BC.

The separation pattern114may be provided on the bit line structures BT and the insulating fences113. The separation pattern114may space the landing pads LP apart from one another. The separation pattern114may include an insulating material.

The etch stop layer115may be provided on the separation pattern114. The etch stop layer115may include an insulating material.

A capacitor structure130bmay be provided on the etch stop layer115. The capacitor structure130bmay include lower electrodes LEb, a capacitor insulating layer CIb, supporters SUb, interfacial layers IFb, and an upper electrode UEb. The capacitor structure130bmay be connected to the landing pad LP. The capacitor structure130bmay be electrically connected to the active pattern AP via the landing pad LP and the buried contact BC.

The lower electrode LEb may be connected to the landing pad LP. The interfacial layers IFb may selectively cover the lower electrodes LEb, and may expose the supporters SUb and the etch stop layer115. The capacitor insulating layer CIb may cover the etch stop layer115, the interfacial layers IFb, and the supporters SUb.

FIG.10Ais a perspective view of a semiconductor device according to some example embodiments of the disclosure.FIG.10Bis a cross-sectional view taken along line A2-A2′ ofFIG.10A.FIG.10Cis a cross-sectional view taken along line B2-B2′ ofFIG.10A.

Referring toFIGS.10A,10B, and10C, a semiconductor device200may include a substrate210, a plurality of first conductive lines220, a channel layer230, a gate electrode240, a gate insulating layer250, and a capacitor structure280. The semiconductor device200may be a memory device including a vertical channel transistor (VCT). The vertical channel transistor may represent a structure in which a channel length of the channel layer230extends from the substrate210in a vertical direction.

A lower insulating layer212may be disposed on the substrate210, and the plurality of first conductive lines220may be disposed on the lower insulating layer212under a condition that the plurality of first conductive lines220is spaced apart from one another in a first direction D1while extending in a second direction D2. A plurality of first insulating structures222may be disposed on the lower insulating layer212, to fill a space among the plurality of first conductive lines220. The plurality of first insulating structures222may extend in the second direction D2, and a top surface of the plurality of first insulating structures222may be disposed at the same level as a top surface of the plurality of first conductive lines220. The plurality of first conductive lines220may function as a bit line of the semiconductor device200.

In some embodiments, the plurality of first conductive lines220may include doped polysilicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. For example, the plurality of first conductive lines220may be constituted by doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, without being limited thereto. The plurality of first conductive lines220may include a single layer or multiple layers of the above-described materials. In some embodiments, the plurality of first conductive lines220may include a two-dimensional semiconductor material and, for example, the two-dimensional semiconductor material may include graphene, a carbon nanotube, or a combination thereof.

Channel layers230may be arranged on the plurality of first conductive lines220in the form of a matrix in which the channel layers230are spaced apart from one another in the first direction D1and the second direction D2. The channel layer230may have a first width in the first direction D1and a first height in a third direction D3, and the first height may be greater than the first width. For example, the first height may be about 2 to 10 times the first width, without being limited thereto. A bottom portion of the channel layer230may function as a first source/drain region (not shown), an upper portion of the channel layer230may function as a second source/drain region (not shown), and a portion of the channel layer230between the first and second source/drain regions may function as a channel region (not shown).

In some embodiments, the channel layer230may include an oxide semiconductor and, for example, the oxide semiconductor may include InxGayZnzO, InxGaySizO, InxSnyZnzO, InxZnyO, ZnxO, ZnxSnyO, ZnxOyN, ZrxZnySnzO, SnxO, HfxInyZnzO, GaxZnySnzO, AlxZnySnzO, YbxGayZnzO, InxGayO, or a combination thereof. The channel layer230may include a single layer or multiple layers of the oxide semiconductor. In some embodiments, the channel layer230may have greater bandgap energy than silicon. For example, the channel layer230may have bandgap energy of about 1.5 to 5.6 eV. For example, the channel layer230may have optimum channel performance when the channel layer230has bandgap energy of about 2.0 to 4.0 eV. For example, the channel layer230may be polycrystalline or amorphous, without being limited thereto. In some embodiments, the channel layer230may include a two-dimensional semiconductor material and, for example, the two-dimensional semiconductor material may include graphene, a carbon nanotube, or a combination thereof.

The gate electrode240may extend in the first direction D1on opposite sidewalls of the channel layer230. The gate electrode240may include a first sub-gate electrode240P1facing a first sidewall of the channel layer230, and a second sub-gate electrode240P2facing a second sidewall of the channel layer230opposing the first sidewall. As one channel layer230is disposed between the first sub-gate electrode240P1and the second sub-gate electrode240P2, the semiconductor device200may have a dual gate transistor structure. However, example embodiments are not limited to the above-described case, and a single gate transistor structure may be embodied by omitting the second sub-gate electrode240P2, and forming only the first sub-gate electrode240P1facing the first sidewall of the channel layer230.

The gate electrode240may include doped polysilicon, a metal, a conductive metal nitride, a conductive metal silicide, a conductive metal oxide, or a combination thereof. The gate electrode240may be constituted by doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, without being limited thereto.

The gate insulating layer250may surround a sidewall of the channel layer230, and may be interposed between the channel layer230and the gate electrode240. For example, the entire sidewall of the channel layer230may be surrounded by the gate insulating layer250, and a portion of a sidewall of the gate electrode240may contact the gate insulating layer250. In some embodiments, the gate insulating layer250may extend in an extension direction of the gate electrode240, and only two sidewalls facing the gate electrode240from among sidewalls of the channel layer230may contact the gate insulating layer250.

In some embodiments, the gate insulating layer250may be constituted by a silicon oxide layer, a silicon oxynitride layer, a high-k dielectric layer having a higher dielectric constant than the silicon oxide layer, or a combination thereof. The high-k dielectric layer may be constituted by a metal oxide or a metal oxynitride. For example, the high-k dielectric layer, which is usable as the gate insulating layer250, may be constituted by HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, without being limited thereto.

A plurality of second insulating structures232may extend on the plurality of first insulating structures222in the second direction D2, and the channel layer230may be disposed between two adjacent second insulating structures232from among the plurality of second insulating structures232. In addition, between the two adjacent second insulating structures232, a first buried layer234and a second buried layer236may be disposed in a space between two adjacent channel layers230. The first buried layer234may be disposed at a bottom portion of the space between the two adjacent channel layers230, and the second buried layer236may be formed on the first buried layer234, to fill a remaining portion of the space between the two adjacent channel layers230. A top surface of the second buried layer236may be disposed at the same level as a top surface of the channel layer230, and the second buried layer236may cover a top surface of the gate electrode240. Otherwise, the plurality of second insulating structures232may be formed by a material layer in continuity with the plurality of first insulating structures222, or the second buried layer236may be formed by a material layer in continuity with the first buried layer234.

A capacitor contact structure260may be disposed on the channel layer230. The capacitor contact structure260may be disposed to vertically overlap with the channel layer230. Capacitor contact structures260may be arranged in the form of a matrix in which the capacitor contact structures260are spaced apart from one another in the first direction D1and the second direction D2. The capacitor contact structure260may be constituted by doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, without being limited thereto. The upper insulating layer262may surround a sidewall of the capacitor contact structure260on the plurality of second insulating structures232and the second buried layer236.

An etch stop layer270may be disposed on the upper insulating layer262, and a capacitor structure280may be disposed on the etch stop layer270. The capacitor structure280may include lower electrodes282, a capacitor insulating layer284, an upper electrode286, interfacial layers288, and supporters289.

The lower electrode282may be electrically connected to a top surface of the contact structure260while extending through the etch stop layer270. In some embodiments, the lower electrode282may be disposed to vertically overlap with the capacitor contact structure260. The lower electrodes282may be arranged in the form of a matrix in which the lower electrodes282are spaced apart from one another in the first direction D1and the second direction D2.

The interfacial layers288may be disposed between the lower electrodes282and the capacitor insulating layer284. The supporters289may support the lower electrodes282. The interfacial layers288may be selectively provided on the lower electrodes282, and may not be provided on the supporters289.

The semiconductor device according to example embodiments may include an interfacial layer selectively covering a lower electrode. According, lower electrodes may be completely electrically isolated from one another and, as such, a leakage phenomenon of a capacitor structure may be limited and/or prevented.

While some example embodiments of the disclosure have been described with reference to the accompanying drawings, it should be understood by those skilled in the art that various modifications may be made without departing from the spirit and scope of example embodiments of the disclosure. Therefore, the above-described embodiments should be considered in a descriptive sense only and not for purposes of limitation.