Patent ID: 12218132

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

The terms used in this specification generally have their ordinary meanings in the art and in the specific context where each term is used. The use of examples in this specification, including examples of any terms discussed herein, is illustrative only, and in no way limits the scope and meaning of the disclosure or of any exemplified term. Likewise, the present disclosure is not limited to various embodiments given in this specification.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

As used herein, “around”, “about”, “approximately” or “substantially” shall generally refer to any approximate value of a given value or range, in which it is varied depending on various arts in which it pertains, and the scope of which should be accorded with the broadest interpretation understood by the person skilled in the art to which it pertains, so as to encompass all such modifications and similar structures. In some embodiments, it shall generally mean within 20 percent, preferably within 10 percent, and more preferably within 5 percent of a given value or range. Numerical quantities given herein are approximate, meaning that the term “around”, “about”, “approximately” or “substantially” can be inferred if not expressly stated, or meaning other approximate values.

Reference is now made toFIG.1.FIG.1is a perspective diagram of part of an integrated circuit100, in accordance with various embodiments. For illustration, the integrated circuit100includes a transistor110, a transistor120, and an insulating layer130. As shown inFIG.1, the transistor120is disposed above the transistor110. The insulating layer130is disposed between the transistor110and the transistor120. Alternatively stated, the transistors110and120and the insulating layer130are stacked and arranged vertically. In some embodiments, the integrated circuit100is a complementary field-effect transistor (CFET). The above implementation of the integrated circuit100is given for illustrative purposes. Various implementations of the integrated circuit100are within the contemplated scope of the present disclosure. For example, in some embodiments, the integrated circuit100is a logic gate circuit including AND, OR, NAND, MUX, Flip-flop, Latch, BUFF, inverter, or any other types of logic circuit.

In some embodiments, the transistor110is a first conductivity type FET (e.g., N-type), and the transistor120is a second conductivity type FET (e.g., P-type) different from the first conductivity type. However, the scope of the disclosure is not intended to be limiting of the present disclosure. For example, in some embodiments, the transistor110is a P-type transistor, and the transistor120is an N-type transistor. In other embodiments, the transistors110and120have the same conductivity type.

For illustration, as shown inFIG.1, the transistor110includes active areas111-112, a gate113, and metal over diffusions (MD)114-115. The transistor120includes active areas121and122, a gate123, and metal over diffusions124-125. The active areas111-112and the metal over diffusions114-115are separate from the active areas121-122and the metal over diffusions124-125. The insulating layer130is disposed between the gate113and the gate123.

In some embodiments, the insulating layer130includes a bottom surface contacting the gate113and an upper surface contacting the gate123. For illustration, the insulating layer130is configured to electrically insulate the gate113from the gate123.

In some embodiments, the insulating layer130includes, for example, silicon dioxide, silicon nitride, silicon oxycarbide (SiOC) or silicon carbide (SiC) insulating structure. However, the scope of the disclosure is not intended to be limiting of the present disclosure. For example, in various embodiments, the insulating material for the insulating layer130includes, for example, SiOCN, SiCN, or any kinds of suitable materials.

In some embodiments, the gates113and123include a gate dielectric layer (not shown) and a gate electrode layer (not shown). In some embodiments, the gates113and123are formed around channel regions of the transistors110and120, in which the channel regions include, for example, structures of round/square wire, nanoslab, nano-sheet, multi-bridge channel, nano-ring or any other suitable kinds of the nano structures.

The configurations of the elements in the integrated circuit100discussed above are given for illustrative purposes and can be modified depending on the actual implementations. Various configurations of the elements in the integrated circuit100are within the contemplated scope of the present disclosure. For example, in some embodiments, the transistor110includes additional active areas disposed next to the active areas111and112, and the transistor120includes additional active areas disposed next to the active areas121and122.

Reference is now made toFIG.2.FIG.2is a cross-sectional view of part of the integrated circuit100along the cross line XX′ inFIG.1, in accordance with various embodiments. With respect to the embodiments ofFIG.1, like elements inFIG.2are designated with the same reference numbers for ease of understanding. The specific operations of similar elements, which are already discussed in detail in above paragraphs, are omitted herein for the sake of brevity, unless there is a need to introduce the co-operation relationship with the elements shown inFIG.2.

As illustrated inFIG.2, the integrated circuit100further includes vias141-142, metal-zero segments151-156, and cut poly layers161-162. For simplicity of illustration, the metal over diffusions114-115and124-125, and the active areas111-112and121-122are not shown inFIG.2.

For illustration, with continued reference toFIG.2, the via141passes through the cut poly layer161and is coupled between the gate113and the metal-zero segment151. The via142is coupled between the gate123and the metal-zero segment155. In some embodiments, the metal-zero segment151is coupled to a first control signal, and the metal-zero segment155is coupled to a second control signal different from the first control signal. In such embodiments, the gate113of the transistor110receives the first control signal, and the transistor110operates in response to the first control signal. Similarly, the gate123of the transistor120receives the second control signal, and the transistor120operates in response to the second control signal.

In some approaches, the gates of two transistors as discussed above are coupled together and implemented by a single one gate structure. Because the gates of the two transistors are coupled together and receive the same control signal, extra arrangements including, for example, dummy gates, active areas, metal over diffusions, and/or conductive segments, are required if the two transistors are designed to operate in response to two different control signals. Therefore, extra arrangements occupy a greater area in the integrated circuit, compared to the embodiments of the present disclosure.

Compared to the above approaches, with configurations of the insulating layer130to separate the gates113and123in the embodiments illustrated inFIGS.1and2, the transistors110and120are able to operate in response to two different control signals, respectively, without extra arrangements. Accordingly, with the configurations as illustrated inFIGS.1and2, the area of the integrated circuit100is reduced, compared with some approaches as discussed above.

The configuration of the elements in the integrated circuit100discussed above is given for illustrative purposes and can be modified depending on the actual implementations. Various configurations of the elements in the integrated circuit100are within the contemplated scope of the present disclosure. For example, in some embodiments, the first control signal received at the gate113of the transistor110is the same as the second control signal received at the gate123of the transistor120.

Reference is now made toFIG.3A.FIG.3Ais an equivalent circuit diagram of part of an integrated circuit300, in accordance with various embodiments. For illustration, the integrated circuit300includes transistors310,320,330,340,350,360. As shown inFIG.3A, gates of the transistors310,320, and340are configured to receive a first control signal S1, and gates of the transistors330,350, and360are configured to receive a second control signal S2. Sources of the transistors310and320are coupled to a voltage VSS. Drains of the transistors310and320are coupled to each other. A source of the transistor330is coupled to the drains of the transistors310and320. A drain of the transistor330is coupled to drains of the transistors340,350, and360at an output node ZN. Sources of the transistors340,350, and360are coupled to a voltage VDD.

In some embodiments, the transistors310,320, and330are N-type FETs, and the transistors340,350, and360are P-type FETs. However, the scope of the disclosure is not intended to be limiting of the present disclosure. For example, in some embodiments, the transistors310,320, and330are P-type transistors, and the transistors340,350, and360are N-type transistors.

Reference is now made toFIG.3B.FIG.3Bis a perspective diagram of part of a semiconductor structure corresponding to the integrated circuit300inFIG.3A, in accordance with various embodiments. For illustration, the integrated circuit300includes active areas311-312,321,331,341,351-352, and361, gates313,322,332, and353, metal over diffusions314-315,323,333,342,354-355, and362, an insulating layer370, vias381a-381d,382a-382c,383a-383d, and384, and metal-zero segments391-394. In some embodiments, the active areas311-312,321, and331, the gate313, and the metal over diffusions314-315,323, and333are disposed in a first layer. The active areas341,351-352, and361, the gate353, and the metal over diffusions342,354-355, and362are disposed in a second layer above the first layer. The gate322and the gate332extend along z direction from the first layer to the second layer. The metal-zero segments391-394are disposed in a third layer above the second layer.

With reference toFIGS.3A and3B, the gate313is configured as the gate of the transistor310. The metal over diffusion314corresponds to the drain of the transistor310that is coupled to the drain of the transistor320. The metal over diffusion315corresponds to the source of the transistor310that is coupled to the voltage VSS. The gate322is configured as the gate of the transistor320and the transistor340. The metal over diffusion323corresponds to the drain of the transistor320that is coupled to the drain of the transistor310. The gate332is configured as the gate of the transistor330and the gate of the transistor360. The metal over diffusion333corresponds to the drain of the transistor330that is coupled to the drain of the transistor360. The metal over diffusion342corresponds to the source of the transistor340that is coupled to the voltage VDD. The gate353is configured as the gate of the transistor350. The metal over diffusion354corresponds to the source of the transistor350that is coupled to the voltage VDD. The metal over diffusion355corresponds to the drain of the transistor350that is coupled to the output node ZN. The metal over diffusion362corresponds to the drain of the transistor360that is coupled to the output node ZN.

With continued reference toFIG.3B, for illustration, the active areas311-312,321,331,341,351-352, and361extend in x direction that is different from z direction. The active areas311-312,321, and331are separated from the active areas351-352,341, and361in z direction. In some embodiments, the active areas311-312,321and331overlap the active areas351-352,341, and361in a plan view or layout view. In some embodiments, the active area311and the active area312are configured with respect to, for example, the active area111and the active area112ofFIG.1, respectively. The active area351and the active area352are configured with respect to, for example, the active area121and the active area122ofFIG.1, respectively.

For illustration, the metal over diffusions314-315,323,333,342,354-355, and362extend in y direction that is different from x and z direction. In some embodiments, the metal over diffusions314and315are configured with respect to, for example, the metal over diffusions114and115ofFIG.1, respectively. The metal over diffusions354and355are configured with respect to, for example, the metal over diffusions124and125ofFIG.1, respectively. As shown inFIG.3B, the metal over diffusions314and315are coupled to the active areas311and312, respectively. The metal over diffusion323is coupled to the active area321. The metal over diffusion333is coupled to the active area331. The metal over diffusion342is coupled to the active area341. The metal over diffusions354and355are coupled to the active areas351and352, respectively. The metal over diffusion362is coupled to the active area361. In some embodiments, the metal over diffusions314-315,323,333,342,354-355, and362are penetrated by the corresponding active areas coupled thereto. In some embodiments, in a plan view, the metal over diffusion314partially overlaps the metal over diffusion354, the metal over diffusion315partially overlaps the metal over diffusion355, the metal over diffusion323partially overlaps the metal over diffusion342, and the metal over diffusion333partially overlaps the metal over diffusion362.

For illustration, the gate313and the gate353extend in y direction. As shown inFIG.3B, the gate313and the gate353are separated from each other in z direction by the insulating layer370therebetween. In some embodiments, the gate313and the gate353are configured with respect to, for example, the gate113and the gate123ofFIGS.1and2, respectively. In some embodiments, a width of the gate313is longer than a width of the gate353along y direction. To explain in a different way, the gate313and the gate353partially overlap with each other in a plan view. However, the scope of the disclosure is not intended to be limiting of the present disclosure. For example, in some embodiments, the gate353extends along y direction in a direction opposite to the direction in which the gate313extends, and has a width equal to the width of the gate313along y direction.

As illustrated inFIG.3B, the gate322and the gate332are disposed next to the gates313and353along x direction. The gates322and the gate332extend in z direction and are separated from each other in x direction.

For illustration, the insulating layer370extends in y direction. In some embodiments, the insulating layer370is configured with respect to, for example, the insulating layer130ofFIGS.1and2. In other embodiments, the insulating layer370overlaps the gate313with a greater area compared to the gate353. However, the scope of the disclosure is not intended to be limiting of the present disclosure. For example, in some embodiments, the insulating layer370overlaps the gate313and the gate353with the equal area while the gate353has a width equal to the width of the gate313along y direction.

The vias381a-381d,382a-382c,383a-383d, and384extend in z direction. The via381ais coupled between the metal over diffusion314and the metal-zero segment391. The via381bis coupled between the metal over diffusion323and the metal-zero segment391. Therefore, the active area311is coupled to the active area321through the metal over diffusion314, the via381a, the metal-zero segment391, the via381b, and the metal over diffusion323. The via381cand the via381dare coupled to the metal over diffusion355and the metal over diffusion362, respectively. The vias381cand381dare coupled to each other through being coupled to the metal-zero segment393.

The via382ais coupled to the metal over diffusion315and the voltage VSS. The via382bis coupled to the metal over diffusion342and the voltage VDD. The via382cis coupled to the metal over diffusion354and the voltage VDD.

The via383ais coupled between the gate313and the metal-zero segment394. The via383bis coupled between the gate322and the metal-zero segment394. The via383cis coupled between the gate332and the metal-zero segment392. The via383dis coupled between the gate353and the metal-zero segment392. As shown inFIG.3B, the via383aand the via383dare separated from each other along y direction. In some embodiments, the via383aand the via383dare configured with respect to, for example, the via141and the via142ofFIG.2, respectively.

The via384is coupled between the metal over diffusion333and the metal over diffusion362. Therefore, the active area331is coupled to the active area361through the metal over diffusion333, the via384, and the metal over diffusion362.

The metal-zero segments391-394extend in x direction and are separated from each other along y direction. In some embodiments, the metal-zero segment392is coupled to a signal output to transmit the second control signal S2to the corresponding gates332and353. The metal-zero segment394is coupled to another signal output to transmit the first control signal S1to the corresponding gates313and322. The metal-zero segment393is configured for the formation of the structure corresponding to the output node ZN ofFIG.3A.

Reference is now made toFIG.3C.FIG.3Cis a layout diagram in a plan view of part of the integrated circuit300, corresponding to the part300A ofFIG.3B, in accordance with various embodiments. With respect to the embodiments ofFIG.3B, like elements inFIG.3Care designated with the same reference numbers for ease of understanding. The specific operations of similar elements, which are already discussed in detail in above paragraphs, are omitted herein for the sake of brevity, unless there is a need to introduce the co-operation relationship with the elements shown inFIG.3C.

As shown inFIG.3C, the integrated circuit300includes the active areas341,351-352, and361, the metal over diffusions342,354-355, and362, the gates322,332, and353, the vias381a-381d,383b, and383c, and the metal-zero segments391-394. For illustration, the gate322crosses the active areas341and352, the gate332crosses the active areas341and361, and the gate353crosses the active areas351-352. The metal-zero segment391overlaps the vias381aand381b. The metal-zero segment392overlaps the vias383cand383d. The metal-zero segment393overlaps the vias381cand381d. The metal-zero segment394overlaps the vias383aand383b.

Reference is now made toFIG.3D.FIG.3Dis a layout diagram in a plan view of part of the integrated circuit300corresponding to the part300B ofFIG.3B, in accordance with various embodiments. With respect to the embodiments ofFIG.3B, like elements inFIG.3Dare designated with the same reference numbers for ease of understanding. The specific operations of similar elements, which are already discussed in detail in above paragraphs, are omitted herein for the sake of brevity, unless there is a need to introduce the co-operation relationship with the elements shown inFIG.3D.

As shown inFIG.3D, the integrated circuit300includes the active areas311-312,321, and331, the gates313,332, and332, the metal over diffusions314-315,323, and333, the insulating layer370, the vias381a-381b,382a-382c,383a, and384, and power rails395-396. For illustration, the gate313crosses the active areas311and312, the gate322crosses the active areas312and321, and the gate332crosses the active areas321and331. The via384overlaps the metal over diffusion333. The metal-zero segment391overlaps the vias381aand381b. The metal-zero segment392overlaps the vias383cand383d. The metal-zero segment393overlaps the vias381cand381d. The metal-zero segment394overlaps the vias383aand383b.

The power rails395-396extend in x direction and are separated from each other in y direction. The power rail395overlaps the vias381a-381band382a, and the power rail396overlaps the vias382b-382cin a plan view. In some embodiments, the power rails395-396are disposed below the active areas311-312,321, and331, the gates313,332, and332, the metal over diffusions314-315,323, and333, and the vias381a-381b,382a-382c. The power rail395is coupled to the via382ato receive the voltage VSS for the integrated circuit300, and the power rail396is coupled to the vias382b-382cto output the voltage VDD to the integrated circuit300.

In some approaches, at least four gates with corresponding elements, including, for example, active areas and metal over diffusions, are required to implement the equivalent circuit ofFIG.3A. Specifically, the at least four gates are separated from each other in x direction. Thus, the at least four gates with corresponding elements in those approaches occupy a greater area in a plan view, compared with the integrated circuit300of the present disclosure.

Compared to the above approaches, with configurations illustrated inFIGS.3A,3B,3C and3D, the gate313and the gate353are stacked vertically and overlap each other. Therefore, in a plan view, the required area for the gate313and the gate353of the integrated circuit300is reduced. Accordingly, the required area for the gate313and the gate353with corresponding elements, including the active areas and the metal over diffusions, as shown inFIGS.3B,3C, and3D, is reduced.

The configuration ofFIGS.3A,3B,3C, and3Dare given for illustrative purposes. Various configurations of the elements mentioned above inFIGS.3A,3B,3C, and3Dare within the contemplated scope of the present disclosure. For example, in various embodiments, the insulating layer370extends in x direction and overlaps the metal over diffusions315and355in a plan view.

Reference is now made toFIG.4A.FIG.4Ais an equivalent circuit diagram of part of an integrated circuit400, in accordance with various embodiments. For illustration, the integrated circuit400includes transistors410,420,430,440,450,460. As shown inFIG.4A, a gate of the transistor410is coupled to a gate of the transistor440, a first source/drain of the transistor410is coupled to a first source/drain of the transistor430, and a second source/drain of the transistor410is coupled a first source/drain of the transistor420, a second source/drain of the transistor430, and a first source/drain of the transistor440. A gate of the transistor420is coupled to a gate of the transistor430, and a second source/drain of the transistor420is coupled to a second source/drain of the transistor440, a first source/drain of the transistor450, and a first source/drain of the transistor460. A second source/drain of the transistor450is coupled to a ground, and a second source/drain of the transistor460is coupled to a voltage supply. In some embodiments, the integrated circuit400is a transmission gate. However, the scope of the disclosure is not intended to be limiting of the present disclosure.

In some embodiments, the transistors410,420, and450are N-type FETs, and the transistors430,440, and460are P-type FETs. However, the scope of the disclosure is not intended to be limiting of the present disclosure. For example, in some embodiments, the transistors410,420, and450are P-type transistors and the transistors430,440, and460are N-type transistors.

Reference is now made toFIG.4B.FIG.4Bis a perspective diagram of a part of a semiconductor structure corresponding to a part of the integrated circuit400circled by a dash line inFIG.4A, in accordance with various embodiments. For illustration, the integrated circuit400includes active areas411-412,421,431-432, and441, gates413,422,433, and442, metal over diffusions414-415,423,434-435, and443, insulating layers451-452, vias461a-461d,462a-462c, and463a-463d, metal-zero segments471a-471b, and472-474, and metal-one segments481-482. In some embodiments, the active areas411-412, and421, the gates413and422, and the metal over diffusions414-415, and423are disposed in a first layer. The active areas431-432, and441, the gates433and442, and the metal over diffusions434-435, and443are disposed in a second layer above the first layer. The metal-zero segments471a-471b, and472-474are disposed in a third layer above the second layer. The metal-one segments481-482are disposed in a fourth layer above the third layer.

With reference toFIGS.4A and4B, the metal over diffusion414corresponds to the first source/drain of the transistor410. The metal over diffusion415corresponds to the second source/drain of the transistor410and the first source/drain of the transistor420. The gate413is configured as the gate of the transistor410. The metal over diffusion423corresponds to the second source/drain of the transistor420. The gate422is configured as the gate of the transistor420. The metal over diffusion434corresponds to the first source/drain of the transistor430. The metal over diffusion435corresponds to the second source/drain of the transistor430and the first source/drain of the transistor440. The gate433is configured as the gate of the transistor430. The metal over diffusion443corresponds to the second source/drain of the transistor440. The gate442is configured as the gate of the transistor440.

With reference toFIGS.4A and4B, the gate413is configured as the gate of the transistor410. The metal over diffusion414corresponds to the first source/drain of the transistor410that is coupled to a terminal of the transistor430. The metal over diffusion415corresponds to the second source/drain of the transistor410that is coupled to a terminal of the transistor430.

With continued reference toFIG.4B, for illustration, the active areas411-412,421,431-432, and441extend in x direction. The active areas411-412and421are separated from the active areas431-432and441in Z direction. In some embodiments, the active areas411-412and421overlap the active areas431-432and441in a plan view or layout view. In some embodiments, the active area411and the active area412are configured with respect to, for example, the active area111and the active area112ofFIG.1, respectively. The active area431and the active area432are configured with respect to, for example, the active area121and the active area122ofFIG.1, respectively. Furthermore, in some embodiments, the active area412and the active area421are configured with respect to, for example, the active area111and the active area112ofFIG.1, respectively. The active area432and the active area441are configured with respect to, for example, the active area121and the active area122ofFIG.1, respectively.

For illustration, the metal over diffusions414-415,423,434-435, and443extend in y direction. In some embodiments, the metal over diffusions414and415are configured with respect to, for example, the metal over diffusions114,115ofFIG.1. The metal over diffusions434and435are configured with respect to, for example, the metal over diffusions124,125ofFIG.1. In some embodiments, the metal over diffusions415and423are configured with respect to, for example, the metal over diffusions114,115ofFIG.1. The metal over diffusions435and443are configured with respect to, for example, the metal over diffusions124,125ofFIG.1. As shown inFIG.4B, the metal over diffusions414and415are coupled to the active areas411and412respectively. The metal over diffusion423is coupled to the active area421. The metal over diffusions434and435are coupled to the active areas431and432respectively. The metal over diffusion443is coupled to the active area441. In some embodiments, the metal over diffusions414-415,423,434-435, and443are penetrated by the corresponding active areas coupled thereto. In some embodiments, in a plan view, the metal over diffusion414overlaps the metal over diffusion434, the metal over diffusion415overlaps the metal over diffusion435, and the metal over diffusion423overlaps the metal over diffusion443.

For illustration, the gates413,422,433and442extend in y direction. As shown inFIG.4B, the gate413and the gate433are separated from each other in z direction by the insulating layer451therebetween. The gate422and the gate442are separated from each other in z direction by the insulating layer452therebetween. In some embodiments, the gate413and the gate422are configured respectively with respect to, for example, the gate113ofFIGS.1and2. The gate433and the gate442are configured respectively with respect to, for example, the gate123ofFIGS.1and2. In some embodiments, in a plan view, the gate413and the gate433partially overlap with each other, and the gate422and the gate442partially overlap with each other. However, the scope of the disclosure is not intended to be limiting of the present disclosure. For example, in some embodiments, a width of the gates413and422is different from a width of the gates433and442along x direction.

The insulating layers451-452extend in y direction. In some embodiments, the insulating layers451-452are configured with respect to, for example, the insulating layer130ofFIGS.1and2. In some embodiments, the insulating layer451electrically insulates the gate413from the gate433, and the insulating layer452electrically insulates the gate422from the gate442.

The via461ais coupled between the gate413and the metal-zero segment471b. The via461bis coupled between the gate422and the metal-zero segment471b. The via461cis coupled between the gate442and the metal-zero segment473. The via461dis coupled between the gate433and the metal-zero segment474. As shown inFIG.4B, the via461aand the via461dare separated from each other along y direction, and the via461band the via461care separated from each other along y direction. In some embodiments, the via461aand the via461dare configured with respect to, for example, the via141and the via142ofFIG.2, respectively. The via461band the via461care configured with respect to, for example, the via141and the via142ofFIG.2, respectively.

The via462ais coupled between the metal over diffusion414and the metal over diffusion434. Therefore, the active area411is coupled to the active area431through the metal over diffusion414, the via462a, and the metal over diffusion434. The via462bis coupled between the metal over diffusion415and the metal over diffusion435. Therefore, the active area412is coupled to the active area432through the metal over diffusion415, the via462b, and the metal over diffusion435. The via462cis coupled between the metal over diffusion423and the metal over diffusion443. Therefore, the active area421is coupled to the active area441through the metal over diffusion423, the via462c, and the metal over diffusion443.

The metal-zero segments471a-471band472-474extend in x direction and are separated from each other along y direction. The metal-one segments481-482extend in y direction and are separated from each other along x direction.

The via463ais coupled between the metal-zero segment471aand the metal-one segment481. The via463bis coupled between the metal-zero segment473and the metal-one segment481. The via463cis coupled between the metal-zero segment471band the metal-one segment482. The via463dis coupled between the metal-zero segment474and the metal-one segment482.

As discussed above, accordingly, the gate413in the first layer is coupled to the gate442in the second layer through the via461a, the metal-zero segment471a, the via463a, the metal-one segment481, the via463b, the metal-zero segment473, and the via461c. The gate422in the first layer is coupled to the gate433in the second layer through the via461b, the metal-zero segment471b, the via463c, the metal-one segment482, the via463d, the metal-zero segment474, and the via461d.

Reference is now made toFIG.4C.FIG.4Cis a layout diagram in a plan view of part of the integrated circuit400corresponding to the part400A ofFIG.4B, in accordance with various embodiments. With respect to the embodiments ofFIG.4B, like elements inFIG.4Care designated with the same reference numbers for ease of understanding. The specific operations of similar elements, which are already discussed in detail in above paragraphs, are omitted herein for the sake of brevity, unless there is a need to introduce the co-operation relationship with the elements shown inFIG.4C.

As shown inFIG.4C, the integrated circuit400includes the active areas431-432and441, the metal over diffusions434-435and443, the gates433and442, the vias461a-461dand463a-463d, the metal-zero segments471a-471band472-474, and the metal-one segments481-482. For illustration, the gate433crosses the active areas431and432, and the gate442crosses the active areas432and441. The metal-zero segment471aoverlaps the vias461aand463a. The metal-zero segment471boverlaps the vias461band463c. The metal-zero segment473overlaps the vias463band461c. The metal-zero segment474overlaps the vias461dand463d.

Reference is now made toFIG.4D.FIG.4Dis a layout diagram in a plan view of part of the integrated circuit400corresponding to the part400B ofFIG.4B, in accordance with various embodiments. With respect to the embodiments ofFIG.4B, like elements inFIG.4Dare designated with the same reference numbers for ease of understanding. The specific operations of similar elements, which are already discussed in detail in above paragraphs, are omitted herein for the sake of brevity, unless there is a need to introduce the co-operation relationship with the elements shown inFIG.4D.

As shown inFIG.4D, the integrated circuit400includes the active areas411-412and421, the gates413and422, the metal over diffusions414-315and423, the insulating layers451-452, the vias462a-462c, and power rails491-492. For illustration, the gate413crosses the active areas411and412, and the gate422crosses the active areas412and421. The gate413overlaps the insulating layer451and the via461a, and the gate422overlaps the insulating layer452and the via461b. The via462aoverlaps the metal over diffusion414, the via462boverlaps the metal over diffusion415, and the via462coverlaps the metal over diffusion423.

The power rails491-492extend in x direction and are separated from each other in y direction. In some embodiments, the power rails491-492are disposed below the active areas411-412, and421, the gates413and422, the metal over diffusions414-415and423, and the vias461a-461band462a-462c. The power rail491is coupled to a via (not shown) to receive a voltage VSS for the integrated circuit400, and the power rail492is coupled to another via (not shown) to receive a voltage VDD for the integrated circuit400.

In some approaches, at least three gates with corresponding elements, including, for example, active areas and metal over diffusions, are required to implement the equivalent circuit ofFIG.4A. Specifically, the at least three gates are separated from each other in x direction. Thus, the at least three gates with corresponding elements in those approaches occupy a greater area in a plan view, compared with the integrated circuit400of the present disclosure.

Compared to the above approaches, with configurations illustrated inFIGS.4A,4B,4C and4D, the gate413and the gate433are stacked vertically and overlap each other, and the gate422and the gate442are stacked vertically and overlap each other. Therefore, in a plan view the required area for the gates413,422,433and442of the integrated circuit400is reduced. Accordingly, the required area for the gates413,422,433and442with corresponding elements, including the active areas and the metal over diffusions, as shown inFIGS.4B,4C, and4D, is reduced.

The configuration ofFIGS.4A,4B,4C, and4Dare given for illustrative purposes. Various configurations of the elements mentioned above inFIGS.4A,4B,4C, and4Dare within the contemplated scope of the present disclosure. For example, in various embodiments, the insulating layers451-452extends in x direction and y direction.

In some embodiments, the integrated circuit400with the configurations as illustrated above includes an area in a layout view about 16% smaller than an area occupied by an integrated circuit with the configurations of some approaches, for those approaches does not include an insulating layer between the gate.

Reference is now made toFIG.5andFIGS.6A to6S.FIG.5is a flow chart of a method500for manufacturing the integrated circuit100,300, or400, or an integrated circuit600shown inFIGS.6A to6S, in accordance with some embodiments of the present disclosure.FIGS.6A to6Sare schematic diagrams, in cross-sectional view of part of the integrated circuit600along x direction (i.e., the source/drain to drain/source direction), illustrating various processes of the method500ofFIG.5, in accordance with some embodiments of the present disclosure. It is understood that additional operations can be provided before, during, and after the processes shown byFIG.5andFIGS.6A to6S, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

In operation510ofFIG.5, a multilayer stack in the integrated circuit600, including first semiconductor layers and second semiconductor layers, is formed by the processes as illustrated inFIGS.6A to6D. In some embodiments, the multilayer stack includes, for example, the channel regions of the transistors110and120ofFIG.1as discussed above. The formation of the multilayer stack will be discussed in detail in the following paragraphs with reference toFIGS.6A to6D.

For illustration, as shown inFIG.6A, an insulation602is disposed above a substrate601. The first semiconductor layers603and the second semiconductor layers604are disposed on the insulation602and alternately stacked on each other along z direction. In some embodiments, the first semiconductor layers603and the second semiconductor layers604are epitaxially grown on the insulation602.

In some embodiments, the first semiconductor layers603and the second semiconductor layers604are made of materials having lattice constants different from each other. For example, in some embodiments, the first semiconductor layers603are made of silicon and the second semiconductor layers604are made of silicon germanium (SiGe). The above materials of the first semiconductor layers603and the second semiconductor layers604are given for illustrative purposes. Various materials of the first semiconductor layers603and the second semiconductor layers604are within the contemplated scope of the present disclosure. For example, in various embodiments, the materials for forming the first semiconductor layers603and the second semiconductor layers604include one or more layers of Ge, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb or InP.

As shown inFIG.6B, trenches are defined and formed adjacent to the first semiconductor layers603and the second semiconductor layers604, and shallow trench isolations (STI)605a-605bare disposed in the trenches. For illustration, the trenches are formed at opposite sides of the first semiconductor layers603and the second semiconductor layers604, such that the shallow trench isolations605a-605bare formed at the opposite sides of the first semiconductor layers603and the second semiconductor layers604.

Next, as shown inFIG.6C, a dummy gate pattern606is patterned and disposed on an uppermost first semiconductor layer603of the first semiconductor layers603. In some embodiments, the uppermost first semiconductor layers603inFIG.6Cis an exposed top layer. In some embodiments, the dummy gate pattern606is formed by depositing and patterning a gate mask layer formed over the uppermost first semiconductor layers603formed as the exposed top layer. In some embodiments, the dummy gate pattern606is made of a silicon nitride (SiN), which is formed by chemical vapor deposition (CVD), including, for example, low pressure CVD (LPCVD) and plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable process. The dummy gate pattern606is patterned into a mask pattern by using patterning operations including, for example, photo-lithography and etching.

As shown inFIG.6D, a multilayer stack607is formed. In some embodiments, the first semiconductor layers603and the second semiconductor layers604, exposed without the dummy gate pattern606disposed on above, are patterned by using patterned mask layers and then etched, such that the first semiconductor layers603and the second semiconductor layers604below the dummy gate pattern606are formed in the multilayer stack607.

Furthermore, inFIG.6E, an insulator608is formed on opposite sides of a first portion of the multilayer stack607along x direction. As shown inFIG.6E, for illustration, the first portion of the multilayer stack607includes a portion of the first semiconductor layers603and a portion of the second semiconductor layers604that are closer to the substrate601and the insulation602, compared with a second portion of the multilayer stack607that is close to the dummy gate pattern606. In some embodiments, as the two sides of the first portion of the multilayer stack607contact the insulator608, the first portion of the multilayer stack607are exposed in y direction.

In some embodiments, the insulating material for the insulator608includes, for example, silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or dielectric material.

In some embodiments, the formation of the insulator608includes, for example, deposition, chemical mechanical polish (CMP) and etches. In various embodiments, the insulator608is formed on opposite sides of both of the first portion and the second portion of the multilayer stack607. After forming the insulator608, the insulator608is recessed, for example, by a dry etching and/or wet etching or other suitable methods, until the bottommost first semiconductor layers603included in the second portion of the multilayer stack607is exposed.

The numbers of the first semiconductor layers603and the second semiconductor layers604corresponding to the first portion of the multilayer stack607, and the numbers of the first semiconductor layers603and the second semiconductor layers604corresponding to the second portion of the multilayer stack607, as discussed above with respect toFIG.6E, are given for illustrative purposes. Various numbers of the first semiconductor layers603and the second semiconductor layers604corresponding to different portions of the multilayer stack607are within the contemplated scope of the present disclosure. For example, in various embodiments, the first portion of the multilayer stack607(with the insulator608formed at the opposite sides) includes more than four layers of the first semiconductor layers603and more than three layers of the second semiconductor layers604.

As shown inFIG.6F, for illustration, an insulator609is formed above the dummy gate pattern606and the two opposite sides of the second portion of the multilayer stack607. In some embodiment, the insulator609contacts the insulator608. In various embodiments, the formation of the insulator609includes, for example, deposition and etches, such as CVD or other suitable methods. In some embodiments, the insulating material of the insulator609is silicon nitride-based material, such as SiN, SiON, SiOCN or SiCN and combinations thereof.

In various embodiments, the insulating materials of the insulators608and609are different from each other and are etched by different etchants. In alternative embodiments, the same etchant have different etch rates between the insulating materials of the insulators608and609. Alternatively stated, the etchant exhibits a high-etch selectivity between the insulators608and609.

InFIG.6G, for illustration, the insulator608is removed. As shown inFIG.6G, the first portion of the multilayer stack607is exposed. In some embodiments, the insulator608is removed selectively, for example, by dry etching and/or wet etching.

Next, as shown inFIG.6H, a side portion of the first semiconductor layers603that are included in the first portion of the multilayer stack607is formed along z direction and connects the first semiconductor layers603corresponding to the first portion of the multilayer stack607to each other, to form a first semiconductor structure603a. The first semiconductor structure603acontacts in x direction the second semiconductor layers604therein. Alternatively stated, the second semiconductor layers604are exposed along y direction. In some embodiments, the first semiconductor structure603ais epitaxial growth on the insulation602.

In operation520ofFIG.5, a first drain region610aand a first source region610bare formed on opposing sides of the first portion of the multilayer stack607, as shown inFIG.6I. In some embodiments, the first drain region610aand the first source region610bare disposed abutted to the first semiconductor structure603a. In some embodiments, the first drain region610aand the first source regions610bare configured with respect to, for example, the active areas111and112ofFIG.1as discussed above.

In various embodiments, the formation of the first drain region610aand the first source region610bincludes, for example, deposition and etches. The configurations of the first drain region610aand the first source region610bare given for illustrative purposes, but the present disclosure is not limited thereto. For example, in some embodiments, the first drain region610aand the first source region610bare disposed on alternate position with respect to the first drain region610aand the first source region610bofFIG.6I.

In some embodiments, each one of the first drain region610aand the first source region610bincludes one or more layers of Si, SiP, SiC and SiCP for an n-type FET or Si, SiGe, Ge for a p-type FET. The first drain region610aand the first source region610bare formed by an epitaxial growth method using CVD, ALD or molecular beam epitaxy (MBE), and etch. In some embodiments, the formation of the first drain region610aand the first source region610bincludes ion implantation in a vertical direction (indicated by arrays inFIG.6I) with ions composed of dopants of n and p types for the NMOS and PMOS respectively. In some embodiments, the first drain region610aand the first source region610bare included in the n-type FET with respect to, for example, the transistor110ofFIG.1.

In various embodiments, the first drain region610aand the first source region610bare formed on opposite sides of both of the first portion and the second portion of the multilayer stack607. After forming the first drain region610aand the first source region610b, the first drain region610aand the first source region610bare recessed, by a dry etching and/or wet etching or other suitable methods, until reaching a level of the interface of the first semiconductor structure603aand the insulator609.

Moreover, inFIG.6J, for illustration, the insulator609is removed. As shown inFIG.6J, the dummy gate pattern606and the second portion of the multilayer stack607are exposed. In some embodiments, the insulator609is removed, for example, by dry etching and/or wet etching.

InFIG.6K, for illustration, an insulator611is formed on the first drain region610aand the first source region610b. In some embodiments, the insulator611is arranged at two opposite sides of at least one layer of the second semiconductor layers604. In various embodiments, the formation of the insulator611includes, for example, the deposition and etches. In some embodiments, the insulator611is made of a silicon nitride (SiN), which is formed by CVD, including, for example, low pressure CVD (LPCVD) and plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable process.

Next, as shown inFIG.6L, a side portion of the first semiconductor layers603that are included in the second portion of the multilayer stack607is formed and connects each layer of the first semiconductor layers603to adjacent layer of the first semiconductor layers603to form a second semiconductor structure603b. The second semiconductor structure603bsurrounds the second semiconductor layers604therein. In some embodiments, the second semiconductor structure603bis epitaxial growth on the insulator611.

In operation530ofFIG.5, a second drain region612aand a second source region612bare formed on opposing sides of the second portion of the multilayer stack607, as shown inFIG.6M. In some embodiments, the second drain region612aand the second source region612bare disposed abutted to the second semiconductor structure603b. In some embodiments, the second drain region612aand the second source regions612bare configured with respect to, for example, the active areas121and122ofFIG.1as discussed above. In various embodiments, the formation of the second drain region612aand the second source region612bincludes, for example, deposition, ion implantation, chemical mechanical polish and etches, as illustrated with respect to the first drain region610aand the first source region610b.

Moreover, inFIG.6N, the dummy gate pattern606is removed and an insulator613is disposed on the shallow trench isolations605a-605b, the second drain region612a, the second source region612b, and the second semiconductor structure603b. In some embodiments, the dummy gate pattern606is removed, for example, by dry etching and/or wet etching. The insulator613is formed by, for example, CVD process, and patterned into a mask pattern by using patterning operations including photo-lithography and etching.

In operation540ofFIG.5, the second semiconductor layers604of the multilayer stack607are removed, such that spaces between two adjacent layers of the first semiconductor layers603are provided, as shown inFIG.6O. Specifically, before the operation540, the second semiconductor layers604of the multilayer stack607are exposed in y direction. Accordingly, in some embodiments, the second semiconductor layers604are removed or etched through, along y direction, using a wet etchant that can selectively etch the second semiconductor layers604against the first semiconductor layers603. The wet etchant is such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution. Alternatively stated, the etching of the second semiconductor layers604(e.g., SiGe) stops at the first semiconductor layers603.

With the configurations ofFIG.6O, in some embodiments, the first semiconductor structure603ais electrically insulated from the second semiconductor structure603bby the insulator611.

In some embodiments, the multilayer stack607is implemented by, for example, including structures of round/square wire, nanoslab, nano-sheet, multi-bridge channel, nano-ring or any other suitable kinds of the nano structures.

In operation550ofFIG.5, a first gate region614over the first portion of the multilayer stack607is formed, as shown inFIG.6P. As shown inFIG.6P, the first gate region614is filled in the first semiconductor structure603a. The first gate region614is configured with respect to, for example, the gate113ofFIG.1. In some embodiments, the first gate region614includes one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof. In some embodiments, the formation of the first gate region614includes, for example, CVD, ALD, electro-plating, or other suitable method.

In some embodiments, before the first gate region614is formed, a gate dielectric layer (not shown) is formed in the first semiconductor layers603and surrounding the inner part of the first semiconductor layer603. The first gate region614is further formed in the gate dielectric layer. In some embodiments, the gate dielectric layer includes one or more layers of a dielectric material, such as silicon oxide, silicon nitride, or high-k dielectric material, other suitable dielectric material, and/or combinations thereof. Examples of high-k dielectric material include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloy, other suitable high-k dielectric materials, and/or combinations thereof. In some embodiments, the gate dielectric layer102includes an interfacial layer formed between the channel layers and the dielectric material.

In various embodiments, the formation of the gate dielectric layer includes, for example, CVD, ALD or any suitable method. In one embodiment, the gate dielectric layer is formed using a highly conformal deposition process such as ALD in order to ensure the formation of a gate dielectric layer having a uniform thickness around each channel layers including the first semiconductor layer603. The thickness of the gate dielectric layer is in a range from about 1 nm to about 6 nm in one embodiment.

In operation560ofFIG.5, an insulating layer615is formed above the first gate region614, as shown inFIG.6Q. The insulating layer615is configured with respect, for example, the insulating layer130ofFIG.1. For illustration, the insulating layer615is surrounded by the insulator611. In some embodiments, the insulating layer615is formed by filling a space between first semiconductor structure603aand the second semiconductor structure603bwith an insulating material. In various embodiments, the formation of the insulating layer615includes, for example, deposition, chemical mechanical polish, and etches.

In operation570ofFIG.5, a second gate region616over the second portion of the multilayer stack607is formed, as shown inFIG.6R. As shown inFIG.6R, the second gate region616is filled in the second semiconductor structure603band disposed above the exposed top layer of the first semiconductor layers603. The second gate region616is configured with respect to, for example, the gate123ofFIG.1. In some embodiments, the second gate region616includes, for example, a gate dielectric layer contacting the first semiconductor layers603surrounding the second gate region616. In various embodiments, the formation of the second gate region616includes, for example, deposition, chemical mechanical polish, and etches.

In some embodiments, the first gate region614and the second gate region616are formed by the same gate material. However, the scope of the disclosure is not intended to be limiting of the present disclosure. For example, the first gate region614and the second gate region616are formed by different gate materials.

With the configurations ofFIG.6R, in some embodiments, the first gate region614is electrically insulated from the second gate region616by the insulating layer615.

Furthermore, for illustration, inFIG.6S, the insulator613is removed. As shown inFIG.6S, the shallow trench isolations605a-605b, the second drain region612a, the second source region612b, and the second semiconductor structure603bare exposed.

As described above, the integrated circuit in the present disclosure is provided with an insulating layer between at least two gates, in which the at least two gates are stacked vertically. The insulating layer insulates electrically one gate from another gate of the at least two gates, such that the routing arrangements between the at least two gates are simplified. Accordingly, the required area in a plan view for the integrated circuit is reduced.

FIG.7is a block diagram of an IC device design system700, in accordance with some embodiments of the present disclosure. One or more operations of the method as discussed above with respect toFIG.5are implementable using the IC device design system700, in accordance with some embodiments.

In some embodiments, IC device design system700is a computing device including a hardware processor702and a non-transitory computer-readable storage medium704. Non-transitory computer-readable storage medium704, amongst other things, is encoded with, i.e., stores, computer program codes, i.e., a set of executable instructions706. Execution of instructions706by the hardware processor702represents (at least in part) an IC device design system which implements a portion or all of, e.g., the method discussed above with respect toFIG.5. (hereinafter, the noted processes and/or methods).

Processor702is electrically coupled to non-transitory computer-readable storage medium704via a bus708. Processor702is also electrically coupled to an I/O interface710by bus708. A network interface712is also electrically connected to processor702via bus708. Network interface712is connected to a network714, so that processor702and non-transitory, computer-readable storage medium704are capable of being connected to external elements via network714. Processor702is configured to execute the instructions706encoded in non-transitory computer-readable storage medium704in order to cause IC device design system700to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, processor702is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit.

In one or more embodiments, non-transitory computer-readable storage medium704is an electronic, magnetic, optical, electromagnetic, infrared, and/or a semiconductor system (or apparatus or device). For example, non-transitory computer-readable storage medium704includes a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or an optical disk. In one or more embodiments using optical disks, non-transitory computer-readable storage medium704includes a compact disk-read only memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or a digital video disc (DVD).

In one or more embodiments, non-transitory computer-readable storage medium704stores the instructions706configured to cause IC device design system700to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, non-transitory computer-readable storage medium704also stores information which facilitates performing a portion or all of the noted processes and/or methods. In various embodiments, non-transitory computer-readable storage medium704stores one or a combination of at least one IC layout designs720or at least one design specification722, each discussed above with respect toFIGS.3A-4Dand the method inFIG.5.

IC device design system700includes I/O interface710. I/O interface710is coupled to external circuitry. In various embodiments, I/O interface710includes one or a combination of a keyboard, keypad, mouse, trackball, trackpad, display, touchscreen, and/or cursor direction keys for communicating information and commands to and/or from processor702.

IC device design system700also includes network interface712coupled to processor702. Network interface712allows IC device design system700to communicate with network714, to which one or more other computer systems are connected. Network interface712includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion or all of the noted processes and/or methods, is implemented in two or more systems700.

IC device design system700is configured to receive information through I/O interface710. The information received through I/O interface710includes one or a combination of at least one design rule instructions, at least one set of criteria, at least one design rule, at least one DRM, and/or other parameters for processing by processor702. The information is transferred to processor702via bus708. IC device design system700is configured to transmit and/or receive information related to a user interface through I/O interface710.

In some embodiments, a portion or all of the noted processes and/or methods is implemented as a standalone software application for execution by a processor. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is a part of an additional software application. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a plug-in to a software application. In some embodiments, at least one of the noted processes and/or methods is implemented as a software application that is a portion of an EDA tool. In some embodiments, an IC layout diagram is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generating tool.

In some embodiments, the processes are realized as functions of a program stored in a non-transitory computer-readable recording medium. Examples of a non-transitory computer-readable recording medium include, but are not limited to, external/removable and/or internal/built-in storage or memory unit, e.g., one or more of an optical disk, such as a DVD, a magnetic disk, such as a hard disk, a semiconductor memory, such as a ROM, a RAM, a memory card, and the like.

By being usable to implement one or more operations of the method inFIG.5, IC device design system700and a non-transitory computer-readable storage medium, e.g., non-transitory computer-readable storage medium704, enable the benefits discussed above with respect to the method inFIG.5.

FIG.8is a block diagram of IC manufacturing system800, and an IC manufacturing flow associated therewith, in accordance with some embodiments of the present disclosure. In some embodiments, based on a layout design, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is fabricated using the IC manufacturing system800.

InFIG.8, the IC manufacturing system800includes entities, such as a design house820, a mask house830, and an IC manufacturer/fabricator (“fab”)850, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device860. The entities in system800are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house820, mask house830, and IC fab850is owned by a single larger company. In some embodiments, two or more of design house820, mask house830, and IC fab850coexist in a common facility and use common resources.

Design house (or design team)820generates an IC design layout diagram (or design)822based on the method inFIG.5, discussed above with respect toFIGS.3A-4D. IC design layout diagram822includes various geometrical patterns that correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device860to be fabricated. The various layers combine to form various IC features. For example, a portion of IC design layout diagram822includes various IC features, such as an active region, gate electrode, source and drain, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house820implements a proper design procedure including the method inFIG.5, discussed above with respect toFIGS.3A-4D, to form IC design layout diagram822. The design procedure includes one or more of logic design, physical design or place and route. IC design layout diagram822is presented in one or more data files having information of the geometrical patterns. For example, IC design layout diagram822can be expressed in a GDSII file format or DFII file format.

Mask house830includes data preparation832and mask fabrication844. Mask house830uses IC design layout diagram822to manufacture one or more masks845to be used for fabricating the various layers of IC device860according to IC design layout diagram822. Mask house830performs mask data preparation832, where IC design layout diagram822is translated into a representative data file (“RDF”). Mask data preparation832provides the RDF to mask fabrication844. Mask fabrication844includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle)845or a semiconductor wafer853. The design layout diagram822is manipulated by mask data preparation832to comply with particular characteristics of the mask writer and/or requirements of IC fab850. InFIG.8, mask data preparation832and mask fabrication844are illustrated as separate elements. In some embodiments, mask data preparation832and mask fabrication844are collectively referred to as mask data preparation.

In some embodiments, mask data preparation832includes optical proximity correction (OPC) which uses lithography enhancement techniques to compensate for image errors, such as those that can arise from diffraction, interference, other process effects and the like. OPC adjusts IC design layout diagram822. In some embodiments, mask data preparation832includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

In some embodiments, mask data preparation832includes a mask rule checker (MRC) that checks the IC design layout diagram822that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram822to compensate for limitations during mask fabrication844, which may undo part of the modifications performed by OPC in order to meet mask creation rules.

In some embodiments, mask data preparation832includes lithography process checking (LPC) that simulates processing that will be implemented by IC fab850to fabricate IC device860. LPC simulates this processing based on IC design layout diagram822to create a simulated manufactured device, such as IC device860. The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine IC design layout diagram822.

It should be understood that the above description of mask data preparation832has been simplified for the purposes of clarity. In some embodiments, data preparation832includes additional features such as a logic operation (LOP) to modify the IC design layout diagram822according to manufacturing rules. Additionally, the processes applied to IC design layout diagram822during data preparation832may be executed in a variety of different orders.

After mask data preparation832and during mask fabrication844, a mask845or a group of masks845are fabricated based on the modified IC design layout diagram822. In some embodiments, mask fabrication844includes performing one or more lithographic exposures based on IC design layout diagram822. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle)845based on the modified IC design layout diagram822. Mask845can be formed in various technologies. In some embodiments, mask845is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask version of mask845includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask845is formed using a phase shift technology. In a phase shift mask (PSM) version of mask845, various features in the pattern formed on the phase shift mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication844is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in semiconductor wafer853, in an etching process to form various etching regions in semiconductor wafer853, and/or in other suitable processes.

IC fab850includes wafer fabrication852. IC fab850is an IC fabrication business that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, IC Fab850is a semiconductor foundry. For example, there may be a manufacturing facility for the front end fabrication of a plurality of IC products (front-end-of-line (FEOL) fabrication), while a second manufacturing facility may provide the back end fabrication for the interconnection and packaging of the IC products (back-end-of-line (BEOL) fabrication), and a third manufacturing facility may provide other services for the foundry business.

IC fab850uses mask(s)845fabricated by mask house830to fabricate IC device860. Thus, IC fab850at least indirectly uses IC design layout diagram822to fabricate IC device860. In some embodiments, semiconductor wafer853is fabricated by IC fab850using mask(s)845to form IC device860. In some embodiments, the IC fabrication includes performing one or more lithographic exposures based at least indirectly on IC design layout diagram822. Semiconductor wafer853includes a silicon substrate or other proper substrate having material layers formed thereon. Semiconductor wafer853further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps).

A method is provided and includes operations below: forming a multilayer stack, wherein the multilayer stack includes multiple first semiconductor layers and multiple second semiconductor layers that are alternately stacked; forming a first source region and a first drain region on opposing sides of a first portion of the multilayer stack and forming a second source region and a second drain region on opposing sides of a second portion of the multilayer stack; removing the second semiconductor layers in the multilayer stack; forming a first gate region, corresponding to a first transistor, over the first portion of the multilayer stack; forming a first insulating layer above the first gate region; and forming a second gate region, corresponding to a second transistor, above the first insulating layer and over the second portion of the multilayer stack.

Also disclosed is an integrated circuit that includes a first transistor comprising a first gate region, a first source region and a first drain region that are arranged on opposite sides of a first portion of a multilayer stack and the first gate region; a second transistor comprising a second gate region, a second source region and a second drain region that are arranged on opposite sides of a second portion, above the first portion, of the multilayer stack and the second gate region; and a first insulating layer interposed between the first to second portions of the multilayer stack. The first gate region overlaps the second gate region in a layout view, and the first and second transistor have a fin structure.

Also disclosed is an integrated circuit that includes a first gate region in a bottom portion of a fin structure and a second gate region in an upper portion of the fin structure; a first insulating layer interposed between the first gate region and the second gate region to electrically isolate the first gate region from the second gate region; and a first conductive segment that extends in a first layer above the fin structure and is coupled to the first gate region by a first via extending next to the upper portion of the fin structure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.