Patent ID: 12235553

DETAILED DESCRIPTION

In order to make the objectives, technical solutions, and advantages of the present disclosure more clear, embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments can be implemented in several different forms. Those ordinary skilled in the art can readily understand that the method and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily in the case that no conflict occurs.

In the drawings, the size of a component, the thickness of a layer or an area may be exaggerated for the sake of clarity. Therefore, the present disclosure is not necessarily limited to this size, and the shape of size of the component does not reflect a real ratio in the drawings. In addition, the drawings schematically show ideal examples, and an aspect of the present disclosure is not limited to the shape, numerical value, or the like shown in the drawings.

The reference numbers used in the drawings include:10: horizontal scanning line;11: vertical scanning line;12: data line;13: via hole structure;14: pixel electrode;15: common electrode;16: transistor;20: first base;200: sub-pixel area;201: first sub-wiring area;202: second sub-wiring area;203: third wiring area;204: second wiring area;21a: red sub-pixel electrode;21b: blue sub-pixel electrode;21c: green sub-pixel electrode;210: first electrode strip;211: first conductive connecting portion;22: common electrode;220: second electrode strip;221: second conductive connecting portion;23: first scanning line;230: hollowed-out hole;24: second scanning line;25: data line;26: first common line;27: second common line;28: transistor;280: gate;281: active layer;282: first electrode;283: second electrode;29a: gate insulation layer;29b: passivation layer;30: metal wire;31: storage capacitor;310: first electrode plate;311: second electrode plate;32: black matrix;33: first covering portion; and34: second covering portion.

In order to realize the full screen design, an embodiment of the present disclosure provides an array substrate which can be applied to a liquid crystal display panel. As shown inFIG.1, the array substrate may include a plurality of (rows of) horizontal scanning lines10, a plurality of (columns of) vertical scanning lines11, a plurality of columns of extending data lines12, and a plurality of sub-pixels arrayed in a row direction X and a column direction Y. The sub-pixels may include pixel electrodes14and common electrodes15opposite to each other in a thickness direction of the array substrate (a direction perpendicular to the row direction X and the column direction Y), and transistors16connecting the pixel electrodes14and the data lines12. The vertical scanning line11is led out from the middle of the sub-pixel, and the vertical scanning line11and the horizontal scanning line10may be connected through a via hole structure13. A scanning signal input terminal of the vertical scanning line11and a data signal input terminal of the data line12may be located on the same side of the array substrate, for example, a binding side of the array substrate. In this way, the other three non-display sides of the array substrate (except the binding side) can be fabricated very narrowly since there is no input terminal of the scanning line and the input terminal of the data line12. Thus, the screen ratio can be increased, that is, the area of the display area can be increased to achieve a full screen.

Since the vertical scanning line11is used to transmit scanning signals, the electric field at the vertical scanning line11is extremely strong, which will lead to a light leakage area within 20 μm near the vertical scanning line11. In order to solve the light leakage problem, it is necessary to cover the light leakage area with a black matrix (BM). Specifically, it is also necessary to consider the influence on the accuracy of opposite arrangement when designing the black matrix, which will greatly reduce the pixel aperture ratio.

In addition, the vertical scanning line11and the horizontal scanning line10need to be switched through the via hole structure13. At the switching point (i.e., the via hole structure13), due to the coupling capacitance between the vertical scanning line11and the pixel electrode14, when the vertical scanning line11is turned off, the capacitive coupling state of the pixel electrode near the switching point is inconsistent with that of other pixel electrodes (which can be defined as ordinary pixel electrodes). With reference toFIG.2, the horizontal scanning line10pulls the voltage Vpixelof the common pixel electrode by ΔVp, and the pixel electrode at the switching point is pulled by ΔVp′generated by a voltage Vgate of the vertical scanning line11in addition to the ΔVpgenerated by the horizontal scanning line10. Therefore, the pixel electrode at the switching point will be darker compared with that at other points, and a plurality of switching points are connected into a line, which will be displayed as a dark line Mura, and thus will affect the display.

In addition, as shown inFIG.1, the common electrode15and the pixel electrode14are oppositely arranged in the thickness direction of the array substrate. In this design, an overlapping area between the pixel electrode114and the common electrode15is larger, so that a parasitic capacitance generated between the pixel electrode114and the common electrode15becomes larger, and thus a charging rate and aperture ratio of the pixel is greatly affected, resulting in poor display effect.

In order to solve the above problems, an embodiment of the present disclosure also provides an array substrate. The array substrate may be used in the liquid crystal display, which is not limited thereto, and may also be used in the organic light-emitting display. The array substrate according to the embodiment of the present disclosure is used in the liquid crystal display as an example.

As shown inFIG.3, the array substrate may be divided into a display area A and a non-display area B surrounding the display area A. The non-display area B of the array substrate2may be provided with a sealing area B1surrounding the display area A, a source electrostatic discharge area B2located in the sealing area B1near the display area A, and a fan-out area B3located in the sealing area B1away from the display area A. The source electrostatic discharge area B2and the fan-out area B3are located in the non-display area B (i.e., the binding area) on the same side of the display area A.

In an embodiment of the present disclosure, the array substrate may include a first base20, and pixel unit(s), first and second scanning lines23and24, data line(s)25, and first and second common lines26and27disposed on the first base20. It should be noted that the pixel units, the first scanning line23, the second scanning line24, the data line25, the first common line26, and the second common line27are located on the display area A of the array substrate.

As shown inFIGS.4to7, the first base20may be in a single layer structure. For example, the first base20may be a glass substrate, which is not limited thereto, and it may also be a substrate made of other materials. In addition, the first base20may also be in a multilayer structure, depending on the specific situations.

In an embodiment of the present disclosure, as shown inFIGS.4to7, the first base20may have a plurality of pixel areas arrayed in the row direction X and the column direction Y, a plurality of (columns of) first wiring areas (in which “column of first wiring area” means that each of the first wiring areas extends in the column direction) arrayed in the row direction X and a plurality of (rows of) second wiring areas204(in which “row of second wiring area” means that each of the second wiring areas extends in the row direction) arrayed in the column direction Y. Each of the pixel areas includes at least two sub-pixel areas200arranged at intervals in the row direction X; and the first wiring areas and the pixel areas in the columns are alternately arranged in the row direction X, a part of the plurality of the first wiring areas is defined as a first sub-wiring area201, and the other part is defined as a second sub-wiring area202. The second wiring areas204and the pixel areas in the rows are alternately arranged in the column direction Y. It should be noted that a third wiring area203may also be arranged between two adjacent columns of sub-pixel areas200in each column of pixel areas. It should be understood that the first sub-wiring area201, the second sub-wiring area202and the third wiring area203integrally extend in the column direction Y, while the second wiring area204integrally extends in the row direction X. Therefore, it can be seen that there is an overlapping area between the first sub-wiring area201, the second sub-wiring area202, and the third wiring area203and the second wiring area204.

As shown inFIG.4, the pixel unit may be provided in plural, and a plurality of pixel units may be arrayed on the first base in the row direction X and the column direction Y. It should be noted that each pixel unit may include at least two sub-pixels arranged in the row direction X, the number of sub-pixels in each pixel unit is equal to the number of sub-pixel areas200, and the sub-pixels in each pixel unit corresponds to the sub-pixel areas200in each pixel area one by one. In addition, the number of columns of pixel units may be equal to the number of columns of the first wiring areas, and the number of rows of pixel units may be equal to the number of rows of the second wiring areas204.

For example, each pixel unit may include three sub-pixels including a red sub-pixel, a green sub-pixel and a blue sub-pixel respectively arranged in the row direction X. In two adjacent pixel units in the row direction X, the red sub-pixel of one of the two adjacent pixel units is adjacent to the blue sub-pixel of the other of the two adjacent pixel units.

It should be understood that the red sub-pixel mentioned in the embodiment of the present disclosure refers to a sub-pixel corresponding to the red filter unit, that is, this sub-pixel may be used to drive liquid crystal molecules corresponding to the red filter unit to deflect, so that the light emitted by a backlight may be emitted through the red filter unit. Similarly, the blue sub-pixel refers to a sub-pixel corresponding to the blue filter unit, that is, this sub-pixel may be used to drive liquid crystal molecules corresponding to the blue filter unit to deflect, so that the light emitted by the backlight may be emitted through the blue filter unit; and the green sub-pixel refers to a sub-pixel corresponding to the green filter unit, that is, this sub-pixel may be used to drive liquid crystal molecules corresponding to the green filter unit to deflect, so that the light emitted by the backlight may be emitted through the green filter unit.

That is, each pixel unit may include at least two sub-pixels arranged at intervals in the row direction X. Specifically, it may include three sub-pixels corresponding to the red, green and blue filter units, respectively. However, it should be noted that the pixel units in the embodiment of the present disclosure are not limited to the three sub-pixels mentioned above, and may also include more sub-pixels, such as four sub-pixels, etc. The color corresponding to the sub-pixel is not limited to red, green, or blue mentioned above, but may also include other colors, such as white, yellow, etc., depending on the specific situations.

In an embodiment of the present disclosure, each sub-pixel may include sub-pixel electrodes21a,21b,21c, a common electrode22, and a transistor28.

Each of the sub-pixel electrodes21a,21band21cmay have a plurality of first electrode strips210arranged at intervals in the row direction X, and the first electrode strips210may be arranged on the sub-pixel area200. It should be understood that each of the sub-pixel electrodes21a,21b,21cmay also include first conductive connecting portion(s)211located on the same side of the first electrode strips210and connected with the first electrode strips210, that is, the sub-pixel electrodes21a,21b,21cmay be integrally shaped like a comb, and the first conductive connecting portion211may be arranged at the second wiring area204.

As shown inFIGS.4,5and8, the first electrode strip210may be in a curved shape as a whole with a bending angle α1of 150°-170°. Specifically, the first electrode strip210may include a two-part structure with an included angle α1of 150°-160° between two parts. For example, the included angle may be 150°, 156°, 162°, 166°, 170°, etc. In other words, the included angles α2and α3between extending directions of these two parts and the column direction Y are 5° to 15°, such as 5°, 7°, 9°, 12°, 15°, etc.

It should be noted that the sub-pixel electrode in the red sub-pixel may be defined as a red sub-pixel electrode21a, the sub-pixel electrode in the blue sub-pixel may be defined as a blue sub-pixel electrode21b, and the sub-pixel electrode in the green sub-pixel may be defined as a green sub-pixel electrode21c. Each of the red sub-pixel electrode21a, the blue sub-pixel electrode21b, and the green sub-pixel electrode21chas a plurality of first electrode strips210arranged at intervals in the row direction X. It should be understood that, the red sub-pixel electrode21a, the blue sub-pixel electrode21b, and the green sub-pixel electrode21chave the same structure, for example, number, size, shape, gap, etc. of the first electrode strips210are the same. The shape and size of the first conductive connecting portion211and the relative position of the first conductive connecting portion with the first electrode strip210are the same.

As shown inFIGS.4and5, the common electrode22may be arranged in the same layer as the sub-pixel electrodes21a,21band21c. For example, the aforementioned common electrode22and the sub-pixel electrodes21a,21b,21cmay be transparent electrodes, and the common electrode22and the sub-pixel electrodes21a,21b,21cmay be made of ITO (indium tin oxide) material, but are not limited thereto, and may also be made of IZO (indium zinc oxide) and other materials. It should be understood that there is a gap between the common electrode22and the sub-pixel electrodes21a,21b,21c(i.e., there is no contact therebetween).

Specifically, the common electrode22may have a plurality of second electrode strips220, the second electrode strips may be located in the sub-pixel area200. The common electrode22may also have a second conductive connecting portion221to connect the second electrode strips220, and the second conductive connecting portion221may be located in the second wiring area204. The second electrode strips220of the common electrode22and the first electrode strips210are alternately arranged in the row direction X, i.e., the sub-pixel electrodes and the common electrode22may be inserted into each other. That is, the array substrate according to the embodiment of the present disclosure may be in IPS (In-Plane Switching) mode, so that the parasitic capacitance generated between the sub-pixel electrode and the common electrode can be reduced, thereby improving the pixel charging rate and aperture ratio. However, it is not limited to the above embodiments, the common electrode22and the sub-pixel electrode may also be located at different layers of the array substrate and arranged oppositely, and one of the common electrode22and the sub-pixel electrode may be a slit electrode with a slit, and the other is a plate electrode without a slit, that is, the array substrate of the embodiment of the present disclosure may also be in FFS (Fringe Field Switching) mode, depending on the specific situations.

It should be noted that the common electrodes22of the sub-pixels may be connected with each other to form a whole structure.

In an embodiment of the present disclosure, as shown inFIGS.4,5and9, the second electrode strip220may be in a curved shape with a bending angle β1of 150°-170°. Specifically, the second electrode strip220may include a two-part structure with an included angle β1of 150°-160° between two parts. For example, the included angle β1may be 150°, 156°, 162°, 166°, 170°, etc. In other words, the included angles β2and β3between extending directions of these two parts and the column direction Y are 5° to 15°, such as 5°, 7°, 9°, 12°, 15°, etc.

The second electrode strip220and the first electrode strip210may be substantially parallel to each other, that is, the bending angle β1of the second electrode strip220may be the same as the bending angle α1of the first electrode strip210.

Based on the above, each of the first electrode strip210of the sub-pixel electrode and the second electrode strip220of the common electrode22is arranged in a curved shape with a bending angle designed to be 150°-170°, which can reduce the color cast and improve the display effect.

It should be noted that the first electrode strips210and the second electrode strips220in each sub-pixel are not limited to the aforementioned alternating arrangement in the row direction X, but may also be alternately arranged in the column direction Y, depending on actual requirements.

In addition, it should be noted that when the first electrode strip210and the second electrode strip220are in the curved shape as mentioned above, the overall shape of the sub-pixel area200may be the same as that of the first electrode strip210, and the overall shapes of the first sub-wiring area201, the second sub-wiring area202and the third wiring area203may also be the same as that of the first electrode strip210, so that the sub-pixel electrodes in the array substrate can be arranged more densely. The overall shape of the second wiring area204may be adapted to the shape of the signal lines (e.g., the first scanning line23and the first common line26) on the second wiring area204.

According toFIGS.4,5and7, the transistor28of each sub-pixel may be located in the second wiring area204. It should be understood that the transistor28as a whole may be located at a side of the sub-pixel electrodes21a,21band21cand the common electrode22close to the first base20, that is, the transistor28may be fabricated on the first base20before the sub-pixel electrodes and the common electrode22. As shown inFIGS.4and5, each transistor28may be connected to one sub-pixel electrode, which is not limited thereto, and one transistor28may be connected to a plurality of sub-pixel electrodes, or one sub-pixel electrode may be connected to a plurality of transistors28, etc., depending on the specific situations.

Specifically, as shown inFIGS.4,5and7, the transistor28includes a gate280, an active layer281, and a first electrode282and a second electrode283arranged on the same layer. The first electrode282is connected to one end of the active layer281, the second electrode283is connected to the other end of the active layer281, and the second electrode283may be connected with the sub-pixel electrode through a fourth via hole structure K4, and specifically may be connected with the first conductive connecting portion211of the sub-pixel electrode through the fourth via hole structure K4. It should be understood that one of the first electrode282and the second electrode283may be a source and the other may be a drain; and the fourth via hole structure K4may be located in the second wiring area204.

In an embodiment of the present disclosure, the gate280, the first electrode282and the second electrode283mentioned above may be made of metal materials, for example, aluminum, molybdenum and other metal materials. The gate280, the first electrode282and the second electrode283may be in a composite layer structure or a single layer structure, depending on the specific situations.

As shown inFIG.7, the transistor28of the embodiment of the present disclosure may be of bottom gate type, that is, the active layer281is located at a side of the gate280away from the first base20. It should be understood that a gate insulating layer29amay be formed between the active layer281and the gate280. That is, in the process of manufacturing the array substrate, the gate280may be formed on the first base20firstly; and then, a gate insulating layer29acovering the gate280is formed. After that, an active layer281directly opposite to the gate280is formed on the gate insulating layer29a. It should be noted that the entire layer of the gate insulating layer29ais disposed on the first base20, that is, the gate insulating layer29anot only covers the gate280, but also covers other structures fabricated before the gate insulating layer29a. It should be understood that the gate insulating layer29amay be made of inorganic materials, such as silicon oxide, silicon oxynitride and other materials.

The aforementioned transistor28may be fabricated on the first base20before the sub-pixel electrode, that is, in the process of fabricating the array substrate, the transistor28may be formed on the first base20first; and a sub-pixel electrode and a common electrode22are then formed. It should be noted that after the first electrode282and the second electrode283of the transistor28are formed on the first base20, and before the sub-pixel electrode and the common electrode22are formed, a passivation layer29bmay also be formed. As shown inFIG.7, the passivation layer29bcovers the first electrode282and the second electrode283, and the first conductive connecting portion211of the sub-pixel electrode may be connected to the second electrode283via the fourth via hole structure K4penetrating through the passivation layer29b.

The entire layer of the passivation layer29bis disposed on the areas of the first base20, that is, the passivation layer29bnot only covers the first electrode282and the second electrode283, but also covers other structures fabricated on the first base20before the passivation layer29b. It should be understood that the passivation layer29bmay be made of inorganic materials, such as silicon oxide and silicon oxynitride.

An organic insulating layer (not shown) may also be formed between the passivation layer29band the sub-pixel electrode. That is, in the process of manufacturing the array substrate, the passivation layer29bmay be formed on the first base20firstly; and the organic insulating layer is then formed on the passivation layer29b. After that, a sub-pixel electrode is formed on the organic insulating layer. The first conductive connecting portion211of the sub-pixel electrode may be connected to the second electrode283via the fourth via hole structure K4penetrating through the organic insulating layer and the passivation layer29b.

In an embodiment of the present disclosure, the planarization is realized by providing the organic insulating layer, which is beneficial to the subsequent coating of the sub-pixel electrode material, and at the same time, may increase the distance between the sub-pixel electrode and the layer where the second electrode283is located, so that the signal line on the layer where the second electrode283is located can be prevented from interfering with the sub-pixel electrode.

It should be noted that the array substrate of the embodiment of the present disclosure may not be provided with an organic insulating layer.

A color filter layer (not shown) may also be formed between the passivation layer29band the organic insulating layer. That is, in the process of manufacturing the array substrate, the passivation layer29bmay be formed on the first base20firstly; and the color filter layer is then formed on the passivation layer29b. After that, the organic insulating layer is formed on the color filter layer. The first conductive connecting portion211of the sub-pixel electrode may be connected to the second electrode283through the fourth via hole structure K4penetrating through the organic insulating layer, the color filter layer and the passivation layer29b. For example, the color filter layer may include the aforementioned red, green, blue and other filter units.

It should be noted that the array substrate of the embodiment of the present disclosure may not be provided with a color filter layer, and the color filter layer may be provided in an opposite substrate.

In addition, the transistor28of the embodiment of the present disclosure is not limited to the bottom gate type, and it may also be of a top gate type, depending on the specific situations.

As shown inFIG.4, the first scanning line23may be arranged in plural, and a plurality of (rows of) the first scanning lines23are sequentially arranged on the first base20in the column direction Y. The first scanning line23may be located in the second wiring area204. The first scanning line23may be formed between the first base20and the common electrode22, that is, in the process of manufacturing the array substrate, the first scanning line23may be formed on the first base20firstly, and the common electrode22and the sub-pixel electrode are then formed. For example, the first scanning line23may be arranged in the same layer as and connected to the gate280of the transistor28. It should be understood that the gate280of the transistor28and the first scanning line23may have an integrated structure.

In an embodiment of the present disclosure, each (row of) second wiring area204may be provided with at least one first scanning line23(in which each of the at least one first scanning line extend in the row direction). In other words, at least one first scanning line23may be disposed at a side of each row of pixel units in the column direction Y. For example, each of the second wiring areas204may be provided with one first scanning line23, wherein the same (row of) first scanning line23is connected with gates of transistors of sub-pixels in the same row, that is, one first scanning line23may provide scanning signals for sub-pixels in one row of pixel units; however, it is not limited thereto, and two (rows of) first scanning lines23may also be arranged in every second wiring area204, depending on the specific situations.

As shown inFIG.4, the first common line26may be arranged in plural, and a plurality of (rows of) the first common lines are sequentially arranged on the first base in the column direction Y. The first common line26is connected to the sub-pixel for providing a common signal for the sub-pixel. The first common line26may be formed between the first base20and the common electrode22. That is, in the process of manufacturing the array substrate, the first common line26may be formed on the first base20firstly, and the common electrode22and the sub-pixel electrode may be then formed. For example, the first common line26may be arranged in the same layer as the first scanning line23, and the first common line26may be connected with the common electrode22through a second via hole structure K2to provide a common signal for the common electrode22. Specifically, the first common line26may be connected with the second conductive connecting portion221of the common electrode22through the second via hole structure K2. It should be noted that, the second via hole structure K2may be located in the second wiring area204.

In an embodiment of the present disclosure, each second wiring area204may be provided with at least one first common line26(in which each of the at least one first common line extends in the row direction) thereon. In other words, at least one first common line26may be disposed at a side of each row of pixel units in the column direction Y. For example, each of the second wiring areas204may be provided with one first common line26. One (row of) first common line26is connected with the common electrodes of the same color sub-pixels in the same row through the second via hole structures K2. For example, the first common lines26in one row are connected with the second conductive connecting portions221of the common electrodes22of the red sub-pixels in the same row through the second via hole structure K2.

When the first common line26is connected to the common electrode22through the second via hole structure K2, the second via hole structure K2as mentioned may at least penetrate through the aforementioned gate insulating layer29aand passivation layer29b. Optionally, when the array substrate includes the aforementioned organic insulating layer and color filter layer, the second via hole structure K2as mentioned may also penetrate through the organic insulating layer and the color filter layer.

Based on the above, each (row of) second wiring area204may be provided with one (row of) first scanning line23and one (row of) first common line26thereon. It should be understood that there is no connection between the first common line26and the first scanning line23.

As shown inFIG.4, the second common line27may be arranged in plural, and a plurality of (columns of) second common lines28are sequentially arranged on the first base20in the row direction X. The second common line27may be formed between the first base20and the common electrode22. That is, in the process of manufacturing the array substrate, the second common line27may be formed on the first base20firstly, and the common electrode22and the sub-pixel electrode are then formed. The passivation layer29bas mentioned above is formed between the second common line27and the common electrode22and the sub-pixel electrode.

For example, the second common line27may be arranged in the same layer as the first electrode282and the second electrode283of the transistor28, wherein the aforementioned first common line26may be arranged in the same layer as the first scanning line23, and the first scanning line23may be arranged in the same layer as the gate280of the transistor28. Therefore, it can be seen that the second common line27in this embodiment of the present disclosure is fabricated after the first common line26being fabricated. It should be noted that the aforementioned gate insulating layer29ais formed between the second common line27and the first common line26.

In an embodiment of the present disclosure, the second common line27may be connected with the common electrode22through a third via hole structure K3. Specifically, as shown inFIG.4, when the second common line27is connected with the common electrode22through the third via hole structure K3, the third via hole structure K3may at least penetrate through the passivation layer29bas mentioned above. Further, when the array substrate includes the organic insulation layer and the color filter layer as mentioned above, the third via hole structure K3may also penetrate through the organic insulation layer and the color filter layer. It should be noted that the third via hole structure K3may be located in the second wiring area204, and the second common line27may be connected with the second conductive connecting portion221of the common electrode22through the third via structure K3.

At least one of the first common line26and the second common line27has a common signal input terminal to provide a common signal for the common electrode22. Optionally, the second common line27has a common signal input terminal, and the second common line27may transmit a received common signal to the first common line26and the common electrode22, but is not limited thereto, or alternatively, both the first common line26and the second common line27may have a common signal input terminal.

In an embodiment of the present disclosure, each (column of) second sub-wiring area202may be provided with one second common line27(in which the second common line27extends in the column direction). For example, a shape of a part of the second common line27opposite to the first electrode strip210in the row direction X may match with a shape of the first electrode strip210, that is, when the first electrode strip210is in a curved shape, the part of the second common line27opposite to the first electrode strip210in the row direction X may also be in a curved shape and substantially parallel with the first electrode strip210.

It should be understood that only the first common line26or only the second common line27may be provided in the embodiment of the present disclosure, depending on the specific situations.

As shown inFIG.4, the second scanning line24may be arranged in plural, and a plurality of (columns of) second scanning lines are sequentially arranged on the first base20in the row direction X. For example, the second scanning line24may be formed between the first base20and the common electrode22. That is, in the process of manufacturing the array substrate, the second scanning line24may be formed on the first base20firstly, and then the common electrode22and the sub-pixel electrode are formed. For example, the second scanning line24may be arranged in the same layer as the first electrode282and the second electrode283of the transistor28. It should be understood that there is a gap between the second scanning line24and the first electrode282as well as the second electrode283of the transistor28(i.e., there is no contact therebetween).

As shown inFIG.4, each first wiring area is provided with at least one second scanning line24(in which each of the at least one second scanning line extends in the column direction). In other words, at least one second scanning line24is arranged at a side of each row of pixel units in the row direction X. It should be noted that the red sub-pixel in one of two adjacent pixel units in the row direction X is adjacent to the blue sub-pixel in the other thereof. Therefore, it can be seen that the second scanning line24in the embodiment of the present disclosure may be located between the red sub-pixel and the blue sub-pixel in two adjacent columns.

For example, the shape of a part of the second scanning line24opposite to the first electrode strip210in the row direction X may match with the shape of the first electrode strip210, that is, when the first electrode strip210is in a curved shape, the part of the second scanning line24opposite to the first electrode strip210in the row direction X may also be in a curved shape and parallel to the first electrode strip210.

In an embodiment of the present disclosure, the second scanning line24is connected with a (row of) first scanning line23through the first via hole structure K1. The second scanning line24has a scanning signal input terminal. The scanning signal received by the second scanning line24may be transmitted to the gate280of the corresponding transistor28through the first via hole structure K1and the first scanning line23so as to control turning-on and turning-off of the transistor28.

Optionally, the first via hole structure K1may include a first via hole portion K11and a connecting portion K12, wherein the connecting portion K12and the second scanning line24are located in different layers of the array substrate, and a part of the connecting portion K12is connected with the first scanning line23and a part of the connecting portion K12is connected with the second scanning line24through the first via hole portion K11.

Further, the connecting portion K12is arranged in the same layer as the common electrode22and the sub-pixel electrode, and there is a gap between the connecting portion K12and the common electrode22as well as the sub-pixel electrode (i.e., there is no contact therebetween). In this case, the first via hole structure K1may further include a second via hole portion K13, and the connecting portion K12may be connected with the first scanning line23through the second via hole portion K13. That is, a part of the connecting portion K12may be connected with the first scanning line23through the second via hole portion K13, and a part of the connecting portion K12is connected with the second scanning line24through the first via hole portion K11.

It should be noted that when the connecting portion K12is arranged in the same layer as the common electrode22and the sub-pixel electrode, the first via hole portion K11may at least penetrate through the passivation layer29b. Further, when the array substrate includes the aforementioned organic insulation layer and color filter layer, the first via hole portion K11may also penetrate through the organic insulation layer and the color filter layer. The second via hole portion K13may at least penetrate through the gate insulating layer29aand the passivation layer29b. Further, when the array substrate includes the aforementioned organic insulating layer and color filter layer, the second via hole portion K13may also penetrate through the organic insulating layer and the color filter layer.

In an embodiment of the present disclosure, the first scanning line23may be provided with a plurality of hollowed-out holes230. An orthographic projection of the second via hole portion K13on the first base20partly overlaps with an orthographic projection of the first scanning line23on the first base20, and the orthographic projection of the second via hole portion K13on the first base20partly overlaps with an orthographic projection of the hollowed-out holes230on the first base20. In this way, the parasitic capacitance generated between the connecting portion K12and the first scanning line23may be reduced.

It should be noted that the aforementioned first via hole structure K1may be located in the second wiring area204. The first common line26may be designed to avoid the first via hole structure K1, that is, an orthographic projection of the aforementioned first via hole structure K1on the first base20does not overlap with an orthographic projection of the first common line26on the first base20.

It should be understood that the connecting portion K12is not limited to being arranged in the same layer as the common electrode22. For example, the connecting portion K12may be arranged in the same layer as the first scanning line23and directly connected with the first scanning line23, that is, it is not necessary to provide the aforementioned second via hole portion K13. When the connecting portion K12may be arranged in the same layer as the first scanning line23, the connecting portion K12may entirely extend in the column direction, and may be located on the first wiring area between two adjacent pixel units in the row direction X.

Optionally, each (row of) first scanning line23may be connected with two (columns of) second scanning lines24. In other words, the two second scanning lines24are respectively connected with the same first scanning line23through a first via hole structure K1, that is, each row (of first scanning line) may be driven by two sets of scanning signals, enhancing the scanning signals and improving the display effect. However, it is not limited thereto, and each first scanning line23may also be connected with one second scanning line24or with three or more second scanning lines. It should be noted that, in order to ensure the display uniformity, the numbers of second scanning lines24connected to each of the first scanning lines23need to be consistent.

Based on the above, it can be seen that, compared with the solution in which the vertical scanning line11is led out from the middle of the sub-pixel as shown inFIG.1, the second scanning line24according to an embodiment of the present disclosure is arranged in the first wiring area, so that an overlapping area between the second scanning line24and the sub-pixel electrode may be reduced, and thus the coupling capacitance between the second scanning line24and the sub-pixel electrode may be reduced, so as to improve ΔVp generated by the scanning signal pulling the pixel electrode at the second scanning line24, thereby overcoming the Mura phenomenon and improving the product quality. It should be noted that the coupling capacitance generated between the second scanning line24and the sub-pixel electrode in the embodiment of the present disclosure is small and may be negligible.

In addition, since the number proportion of cone cells responsible for color (green, red, blue) perception is 40:20:1, the human eyes are most sensitive to green at present. That is, in the practical applications, red and blue have less influence on the transmittance of the liquid crystal display panel than green. Based on this, the present disclosure further designs the second scanning line24between adjacent red and blue sub-pixels. Even if the second scanning line24causes light leakage at the red and blue sub-pixels, it is difficult to be detected by human eyes and has relatively small impact. Therefore, the width of the black matrix can be reduced, or the black matrix can be omitted to improve the pixel aperture ratio.

In an embodiment of the present disclosure, since the scanning signal provided by the second scanning line24is strong, the second scanning line24is arranged on each of the first sub-wiring areas201as shown inFIG.4, so as to ensure the display uniformity. That is, the second scanning line24is arranged on both the first sub-wiring area201and the second sub-wiring area202. Specifically, one of the first sub-wiring area201and the second sub-wiring area202is provided with at least one second scanning line24, while the other is provided with one second scanning line24.

Optionally, two second scanning lines24are arranged on each of the first sub-wiring areas201, and one second scanning line24is arranged on each of the second sub-wiring areas202. The two second scanning lines24on the same first sub-wiring area201are respectively connected with different first scanning lines23through the first via hole structure K1, thus ensuring the display effect and reducing the processing difficulty.

It should be noted that, in order to further ensure the display uniformity, the number of signal lines on the first sub-wiring area201may be equal to the number of signal lines on the second sub-wiring area202. The aforementioned first sub-wiring area201is provided with two second scanning lines24, while the second sub-wiring area202is provided with one second scanning line24. In order to make the number of signal lines on the second sub-wiring area202consistent with the number of signal lines on the first sub-wiring area201, each second sub-wiring area202may be provided with one second common line27as mentioned above.

Taking a 4K resolution display panel as an example, there are 3840 columns and 2160 rows of pixel units in the 4K resolution display panel, wherein each pixel unit includes a red sub-pixel, a green sub-pixel and a blue sub-pixel arranged sequentially in the row direction. Therefore, there are 3840×3 columns and 2160 rows of sub-pixels in the 4K resolution display panel, that is, there are 3840 (columns of) first wiring areas and there are 2160 (rows of) second wiring areas204. Each (row of) the second wiring area204is provided with one (row of) first scanning line23, that is, there are 2160 (rows of) first scanning lines. The two second scanning lines24are connected with one first scanning line23, that is, there are 2160×2 (columns of) second scanning lines24. The number of (columns of) the first wiring areas and the number of (columns of) the second scanning lines24is 8:9. In other words, every 8 first wiring areas forms a group, and a total of 9 second scanning lines24are provided. That is, in each group of first wiring areas, one first wiring area forms a first sub-wiring area201having two second scanning lines24; while the remaining 7 first wiring areas form second sub-wiring areas202, and each of the second sub-wiring areas202has one second scanning line24and one second common line27.

In other words, in an embodiment of the present disclosure, a plurality of first wiring areas are divided into a plurality of (columns of) first wiring area groups, and each first wiring area group includes 8 first wiring areas arranged sequentially in the row direction X. That is, in each of the first wiring area groups, a 1stfirst wiring area, a 2ndfirst wiring area, . . . , a 8thfirst wiring area are arranged sequentially in the row direction X. It should be noted that, the first wiring areas in each of the first wiring area groups have the same arrangement direction. In each of the first wiring area groups, the nthfirst wiring area is formed into the first sub-wiring area201, and the remaining 7 first wiring areas are formed into the second sub-wiring areas202, where 1≤n≤8 and n is a positive integer. That is, the first wiring area201in each of the first wiring area groups is located in the same column.

It should be noted that the display panel of the embodiment of the present disclosure is not limited to the aforementioned 4K resolution, and other resolutions are also possible. Therefore, the total number of the first wiring areas, the proportion and positional relationship of the first sub-wiring areas201and the second sub-wiring areas202are not limited to those mentioned above, and may also be determined according to specific situations as long as the display uniformity of the entire panel can be ensured.

In addition, it should be noted that some of the second sub-wiring areas202in a plurality (columns of) the second sub-wiring areas202may not be provided with the second common line27, and the second sub-wiring area202without the second common line27may be uniformly arranged in the display panel, depending on actual requirements.

As shown inFIGS.4and5, the data line25may be arranged in plural, and a plurality of date lines are sequentially arranged on the first base20in the row direction X, and are connected with sub-pixels for providing data signals for the sub-pixels. For example, the data line25is formed between the first base20and the common electrode22. In other words, in the process of manufacturing the array substrate, the data line25may be formed on the first base20firstly, and then the common electrode22and the sub-pixel electrode are formed. The data line25has a data signal input terminal and is connected with the first electrode282of the transistor28, that is, the data line25may transmit a received data signal to the first electrode282of the transistor28. Optionally, the data line25may be arranged in the same layer as the first electrode282of the transistor28.

In an embodiment of the present disclosure, the first sub-wiring area201, the second sub-wiring area202, and the third wiring area203may each be provided with at least one data line25. In other words, the data line25is provided on at least one side of each column of sub-pixels in the row direction X.

In an optional embodiment, as shown inFIG.4, one (column of) data line25is arranged at a side of each column of sub-pixels in the row direction X, and the (columns of) data lines25and the columns of sub-pixels are alternately arranged in the row direction X. In other words, one data line25may be arranged on the first sub-wiring area201, the second sub-wiring area202and the third wiring area203, wherein each data line25is connected with the sub-pixels in one column that are adjacent to the data line.

In another optional embodiment, as shown inFIG.10, one data line25is arranged on each of opposite sides of each column of sub-pixels in the row direction X, that is, two data lines25are arranged on the first sub-wiring area201, the second sub-wiring area202and the third wiring area203between two adjacent columns of sub-pixels. The sub-pixels in the even row in each column of sub-pixels is connected with one data line25located at a side thereof and adjacent thereto, and the sub-pixels in the odd row is connected with another data line25located at the other side thereof and adjacent thereto, that is, each column of sub-pixels are matched and connected with two data lines25, and these two data lines25are located on opposite sides of each column of sub-pixels in the row direction X, respectively, thereby improving the charging time.

It should be understood that the distance between each of two data lines25on both sides of the sub-pixel and the sub-pixel may be equal, so that both sides of the sub-pixel are pulled by the data signal uniformly, there is substantially no pressure difference generated by the data signal on both sides of the sub-pixel when the brightness is LO, and then it is unnecessary to consider light leakage at the first sub-wiring area201, the second sub-wiring area202and the third wiring area203.

It should be noted that no matter whether one data line25or two data lines25are provided in the first sub-wiring area201and the second sub-wiring area202, the data line25is closer to a column of sub-pixels connected thereto than the second common line27and the second scanning line24.

In an embodiment of the present disclosure, a shape of a part of the data line25opposite to the second electrode strip220in the row direction X may match with a shape of the second electrode strip220, that is, when the second electrode strip220is in a curved shape, the part of the data line25opposite to the second electrode strip220in the row direction may also be in a curved shape and may be substantially parallel to the second electrode strip220.

In an embodiment of the present disclosure, a width of the second scanning line24in the row direction X may be larger than a width of the data line25in the row direction X. Optionally, a ratio of the width of the second scanning line24in the row direction X to the width of the data line25in the row direction X may be 1.1 to 2, such as 1.1, 1.3, 1.5, 1.7, 2, etc. For example, the width of the data line25in the row direction X may be about 6 μm, and the width of the second scanning line24in the row direction X may be about 10 μm; however, it is not limited thereto. The width may also be other values depending on the specific situations.

Optionally, the width of the second common line27in the row direction X may be equal to the width of the second scanning line24.

In an embodiment of the present disclosure, the width of the first sub-wiring area201in the row direction X may be W1, the width of the second sub-wiring area202in the row direction X may be W2, and the width of the sub-pixel area200in the row direction X may be W3, where 0≤(W1−W2)/(2×W3)≤−4%, and W1, W2 and W3 are positive numbers. This design can avoid the risk of vertical Mura at the second scanning line24.

Optionally, the width W1 of the first sub-wiring area201may be equal to the width W2 of the second sub-wiring area202, so as to reduce the design difficulty.

In an embodiment of the present disclosure, the array substrate may further include a first covering portion33. An orthographic projection of the first covering portion33on the first base20completely overlaps with the first wiring area located between two adjacent pixel areas, and the first covering portion33is arranged and connected with the common electrode22of the sub-pixels, that is, the first covering portion33may cover signal lines (e.g., the second scanning line24, the data line25and the second common line27) between adjacent pixel areas, so as to shield signals, thereby alleviating and eliminating the influence of the signals on the electric field at the sub-pixel area200here, improving or eliminating the problem of the light leakage between adjacent pixel areas, reducing the area of the black matrix BM or eliminating the need to design a black matrix, and improving the pixel aperture ratio.

It should be noted that the orthographic projection of the first covering portion33on the first base20does not overlap with the second wiring area204. Opposite sides of the first covering portion33in the column direction Y are respectively connected with the second conductive connecting portions221of the common electrodes22of adjacent two rows of sub-pixels.

In addition, the array substrate may further include a second covering portion34. An orthographic projection of the second covering portion34on the first base20completely overlaps with the third wiring area203located between two adjacent sub-pixel areas200in each pixel area, and the second covering portion34is arranged in the same layer and connected with the common electrode22of the sub-pixels, that is, the second covering portion34may cover signal lines (e.g., the data line25) between two adjacent sub-pixel areas200in each pixel area, so as to shield signals, thereby alleviating and eliminating the influence of the signals on the electric field at the sub-pixel area200, improving or eliminating the problem of the light leakage between two adjacent sub-pixel areas200in each pixel area, reducing the area of the black matrix BM here or eliminating the need to design a black matrix, and improving the pixel aperture ratio.

It should be noted that the orthographic projection of the second covering portion34on the first base20does not overlap with the second wiring area204. Opposite sides of the second covering portion34in the column direction Y are respectively connected with the second conductive connecting portions221of the common electrodes22of adjacent two rows of sub-pixels.

It should be understood that the second conductive connecting portions221of the common electrodes22of adjacent sub-pixels in the row direction X are connected. The second conductive connecting portion221may cover a part of the second wiring area204. Although the second conductive connecting portion221of the common electrode22covers a part of the second wiring area204and may shield the scanning signal on the first scanning line23, the coupling electric field existing between the sub-pixel electrode and the first scanning line23will lead to disorder of liquid crystal arrangement in the display process. Therefore, it is necessary to provide a black matrix32at the second wiring area204to perform shielding.

A metal line30may also be arranged on opposite sides of each sub-pixel in the row direction X, and the metal line30is arranged closer to the sub-pixel than the data line25. The metal line30according to the embodiment of the present disclosure may be arranged in the same layer as the first common line26and connected with the first common line26, and this metal line30may shield signals, so as to alleviate and eliminate the influence of the data signal and the scanning signal on the electric field at the sub-pixel area200and improve the display effect.

In an embodiment of the present disclosure, the scanning signal input terminal of the second scanning line24, the common signal input terminal of the second common line27and the data signal input terminal of the data line25as mentioned above may be located on the same side of the first base20. For example, the first base20has a first side and a second side which are oppositely arranged in the column direction Y. Each of the scanning signal input terminal of the second scanning line24, the common signal input terminal of the second common line27and the data signal input terminal of the data line25is close to the first side or close to the second side, so that there is neither scanning signal input terminal of the second scanning line24, common signal input terminal of the second common line27, nor data signal input terminal of the data line25on other sides of the first base20. Therefore, the other sides may be made to be narrower, so that a proportion of the display area A can be increased to realize a full-screen display.

It should be noted that, as shown inFIG.3, an area B4where a driving circuit of the gate280for providing the scanning signal for the second scanning line24is located may be located in the non-display area B, specifically, it may be located between a source electrostatic discharge area B2and the fan-out area B3and located inside the sealing area B1; however, it is not limited thereto, the driving circuit of the gate280for providing the scanning signal for the second scanning lines24may not be arranged on the first base20, and may be electrically connected with the second scanning line24on the first base20through a flexible printed circuit board.

In addition, it should be noted that each of the via hole structures or the via hole portions mentioned in the present disclosure may be a structure in which a conductive material is filled in a hole.

The array substrate according to the embodiment of the present disclosure may further include a storage capacitor31, and the storage capacitor31may include a first electrode plate310and a second electrode plate311opposite to each other in the thickness direction of the array substrate. The first electrode plate310may be arranged in the same layer and connected with the first common line26, and the second electrode plate311may be arranged in the same layer as the first electrode282and the second electrode283of the transistor28. The second electrode plate311may be connected with the second electrode283of the transistor28. It should be noted that the first conductive connecting portion211of the sub-pixel electrode may be connected with the second electrode plate311through the fourth via hole structure K4, so as to realize the connection between the first conductive connecting portion211of the sub-pixel electrode and the second electrode283of the transistor28.

Based on the foregoing contents, in the array substrate according to an embodiment of the present disclosure, the first sub-wiring area201is provided with two second scanning lines24and one data line25, and the second sub-wiring area202is provided with one second scanning line24, one second common line27and one data line25. The third wiring area203is provided with one data line25, and each first scanning line23is connected with two second scanning lines24through the first via hole structure K1. The array substrate may be used in a 4K 60 Hz display panel.

In the array substrate according to another embodiment of the present disclosure, the first sub-wiring area201is provided with two second scanning lines24and two data lines25, and the second sub-wiring area202is provided with one second scanning line24, one second common line27and two data lines25. The third wiring area203is provided with two data lines25, and each first scanning line23is connected with two second scanning lines24through the first via hole structure K1. The array substrate may be used in 4K 120 Hz or 8K 60 Hz display panel.

It should be noted that the aforementioned 4K and 8K refer to a resolution of the display panel, and the 60 Hz and 120 Hz refer to a refresh rate of the display panel.

An embodiment of the present disclosure also provides a display panel, which includes the array substrate described in any of the above embodiments. It should be understood that the display panel may be a liquid crystal panel, therefore, the display panel may also include an opposite substrate oppositely arranged to the array substrate, and liquid crystal molecules located between the opposite substrate and the array substrate.

When the array substrate has the aforementioned color filter layer, it is unnecessary to set the color filter layer in the opposite substrate. In this case, the opposite substrate may include a second base (not shown) and a black matrix32arranged at a side of the second base facing towards the array substrate, as shown inFIG.11.

It should be understood that, when the array substrate does not have the aforementioned color filter layer, the color filter layer may be provided in the opposite substrate.

An embodiment of the present disclosure also provides an electronic device including the display panel as described above.

In the embodiment of the present disclosure, the specific type of the electronic device is not particularly limited, and any type of electronic device commonly used in this field may be used, such as a liquid crystal display television, a mobile phone, a computer, a watch, etc., and those skilled in the art may make corresponding choices according to the specific use of the electronic device, which will not be repeated in detail.

It should be noted that, the electronic device also includes other necessary parts and components in addition to the display panel. For example, the display may include, for example, a housing, a circuit board, a power cord, etc., which may be supplemented according to the specific use requirements of the electronic device, and will not be repeated herein.

In the present disclosure, unless otherwise specified, the term “arranged in the same layer” means that two layers, components, members, elements or parts can be formed by one same patterning process, and the two layers, components, members, elements or parts are generally formed of the same material.

In the present disclosure, unless otherwise specified, the expression “patterning process” generally includes steps of photoresist coating, exposure, development, etching, photoresist stripping, etc. The expression “one patterning process” means a process of forming a patterned layer, a component, a member, etc. using a mask plate.

The ordinal numbers such as “first”, “second”, “third” and “fourth” in the present specification are provided to avoid the confusion of constituent elements, rather than to limit the quantity.

In this specification, unless otherwise specified and limited, the terms “installation”, “interconnection” and “connection” should be understood in a broad sense. For example, it may be a fixedly connection, a detachably connection or an integrally connection; or may be a mechanically connection or an electrically connection; or may be a directly connection, an indirectly connection through a middle member, or through a communication between inner portions of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to the specific situations.

Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed here. This application is intended to cover any variations, uses, or adaptations of the disclosure following the general principles thereof and including such departures from the present disclosure as come within known or customary practice in the art. It is intended that the specification and embodiments be considered as exemplary only, with a true scope and spirit of the present disclosure being indicated by the following claims.