Patent ID: 12245428

DESCRIPTION OF THE EMBODIMENTS

FIG.1Ashows a schematic view of two blocks BLOCK(i)and BLOCK(i+1)of a vertical AND memory array10arranged in rows and columns. The block BLOCK(i)includes a memory array A(i). A row (e.g., an (m+1)throw) of the memory array A(i)is a set of AND memory cells20having a common word line (e.g., WL(i)m+1). The AND memory cells20of the memory array A(i)in each row (e.g., the (m+1)throw) correspond to a common word line (e.g., WL(i)m+i) and are coupled to different source pillars (e.g., SP(i)and SP(i)n+1) and drain pillars (e.g., DP(i)nand DP(i)n+1), so that the AND memory cells20are logically arranged in a row along the common word line (e.g., WL(i)m+1).

A column (e.g., an nthcolumn) of the memory array A(i)is a set of AND memory cells20having a common source pillar (e.g., SP(i)n) and a common drain pillar (e.g., DP(i)n). The AND memory cells20of the memory array A(i)in each column (e.g., the nthcolumn) correspond to different word lines (e.g., WL(i)m+1and WL(i)n) and are coupled to a common source pillar (e.g., SP(i)n) and a common drain pillar (e.g., DP(i)n). Hence, the AND memory cells20of the memory array A(i)are logically arranged in a column along the common source pillar (e.g., SP(i)n) and the common drain pillar (e.g., DP(i)n). In the physical layout, according to the fabrication method as applied, the columns or rows may be twisted and arranged in a honeycomb pattern or other patterns for high density or other reasons.

InFIG.1A, in the block BLOCK(i), the AND memory cells20in the nthcolumn of the memory array A(i)share a common source pillar (e.g., SP(i)n) and a common drain pillar (e.g., DP(i)n). The AND memory cells20in an (n+1)thcolumn share a common source pillar (e.g., SP(i)n+1) and a common drain pillar (e.g., DP(i)n+1).

The common source pillar (e.g., SP(i)n) is coupled to a common source line (e.g., SLn) and the common drain pillar (e.g., DP(i)n) is coupled to a common bit line (e.g., BLn). The common source pillar (e.g., SP(i)n+1) is coupled to a common source line (e.g., SLn+1) and the common drain pillar (e.g., DP(i)n+1) is coupled to a common bit line (e.g., BLn+1).

Likewise, the block BLOCK(i+1)includes a memory array A(i+1), which is similar to the memory array A(i)in the block BLOCK(i). A row (e.g., an (m+1)throw) of the memory array A(i+1)is a set of AND memory cells20having a common word line (e.g., WL(i+1)m+1). The AND memory cells20of the memory array A(i+1)in each row (e.g., the (m+1)throw) correspond to a common word line (e.g., WL(i+1)m+1) and are coupled to different source pillars (e.g., SP(i+1)nand SP(i+1)n+1) and drain pillars (e.g., DP(i+1)nand DP(i+1)n+1). A column (e.g., an nthcolumn) of the memory array A(i+1)is a set of AND memory cells20having a common source pillar (e.g., SP(i+1)n) and a common drain pillar (e.g., DP(i+1)n). The AND memory cells20of the memory array A(i+1)in each column (e.g., the nthcolumn) correspond to different word lines (e.g., WL(i+1)m+1and WL(i+1)m) and are coupled to a common source pillar (e.g., SP(i+1)n) and a common drain pillar (e.g., DP(i+1)n). Hence, the AND memory cells20of the memory array A(i+1)are logically arranged in a column along the common source pillar (e.g., SP(i+1)n) and the common drain pillar (e.g., DP(i+1)n).

The block BLOCK(i+1)and the block BLOCK(i)share source lines (e.g., SL and SLn+1) and bit lines (e.g., BLnand BLn+1). Therefore, the source line SL and the bit line BL are coupled to the nthcolumn of AND memory cells20in the AND memory array A(i)of the block BLOCK(i), and are coupled to the nthcolumn of AND memory cells20in the AND memory array A(i+1)of the block BLOCK(i+1). Similarly, the source line SLn+1and the bit line BLn+1are coupled to the (n+1)thcolumn of AND memory cells20in the AND memory array A(i)of the block BLOCK(i), and are coupled to the (n+1)thcolumn of AND memory cells20in the AND memory array A(i+1)of the block BLOCK(i+1).

Referring toFIG.1B, the memory array10may be disposed over an interconnect structure of a semiconductor die, for example, being disposed on one or more active devices (e.g., transistors) formed on a semiconductor substrate. Therefore, a dielectric substrate50is, for example, a dielectric layer (e.g., a silicon oxide layer) over a metal interconnect structure formed on a silicon substrate. The memory array10may include a gate stack structure52, a plurality of channel pillars16, a plurality of first conductive pillars (also referred to as source pillars)32a, a plurality of second conductive pillars (also referred to as drain pillars)32b, and a plurality of charge storage structures40.

Referring toFIG.1B, the gate stack structure52is formed on the dielectric substrate50in an array region (not shown) and a staircase region (not shown). The gate stack structure52includes a plurality of gate layers (also referred to as word lines)38and a plurality of insulating layer54vertically stacked on a surface50sof the dielectric substrate50. In the Z direction, the gate layers38are electrically isolated from each other by the insulating layer54disposed therebetween. The gate layer38extends in a direction parallel to the surface of the dielectric substrate50. As shown inFIG.1B, the gate layers38in the staircase region may have a staircase structure (not shown). Therefore, a lower gate layer38is longer than an upper gate layer38, and the end of the lower gate layer38extends laterally beyond the end of the upper gate layer38. A contact (not shown) for connecting the gate layer38may land on the end of the gate layer38to connect the gate layers38respectively to conductive lines.

Referring toFIG.1BtoFIG.1G, the memory array10further includes a plurality of channel pillars16. The channel pillar16continuously extends through the gate stack structure52. The material of the channel pillar16may be semiconductor such as undoped polysilicon.

Referring toFIG.1BtoFIG.1G, the memory array10further includes an insulating pillar28, a plurality of first conductive pillars32a, and a plurality of second conductive pillars32b. In this example, the first conductive pillars32aserve as source pillars. The second conductive pillars32bserve as drain pillars. The first conductive pillar32a, the second conductive pillar32b, and the insulating pillar28each extend in a direction (i.e., the Z direction) perpendicular to the gate layer38. The first conductive pillar32aand the second conductive pillar32bare separated from each other by the insulating pillar28. The first conductive pillar32aand the second conductive pillar32bare electrically connected to the channel pillar16. The first conductive pillar32aand the second conductive pillar32binclude doped polysilicon or metal materials. The insulating pillar28is, for example, silicon nitride or silicon oxide.

Referring toFIG.1C,FIG.1E,FIG.1FandFIG.1G, the charge storage structure40encloses the channel pillar16, the first conductive pillar32a, the second conductive pillar32band the insulating pillar28. At least a portion of the charge storage structure40is disposed between the channel pillar16and the gate layers38. The charge storage structure40may include a tunneling layer (or referred to as a bandgap engineered tunneling oxide layer)14, a charge storage layer12, and a blocking layer36. The charge storage layer12is located between the tunneling layer14and the blocking layer36. In some embodiments, the tunneling layer14and the blocking layer36include silicon oxide. The charge storage layer12includes silicon nitride or other materials capable of trapping charges. In some embodiments, as shown inFIG.1F, the charge storage structure40(the tunneling layer14, the charge storage layer12, and the blocking layer36) surrounds the gate layer38. In other embodiments, as shown inFIG.1G, a portion (the tunneling layer14and the charge storage layer12) of the charge storage structure40continuously extends in a direction (i.e., the Z direction) perpendicular to the gate layer38, and the other portion (the blocking layer36) of the charge storage structure40surrounds the gate layer38.

Referring toFIG.1F, the charge storage structure40, the channel pillar16, the source pillar32a, and the drain pillar32bare surrounded by the gate layer38and a memory cell20is defined. According to different operation methods, a 1-bit operation or a 2-bit operation may be performed on the memory cell20. For example, when a voltage is applied to the source pillar32aand the drain pillar32b, since the source pillar32aand the drain pillar32bare connected to the channel pillar16, electrons may be transferred along the channel pillar16and stored in the entire charge storage structure40. Accordingly, a 1-bit operation may be performed on the memory cell20. In addition, for an operation involving Fowler-Nordheim tunneling, electrons or holes may be trapped in the charge storage structure40between the source pillar32aand the drain pillar32b. For an operation involving source side injection, channel-hot-electron injection, or band-to-band tunneling hot carrier injection, electrons or holes may be locally trapped in the charge storage structure40adjacent to one of the source pillar32aand the drain pillar32b. Accordingly, a single level cell (SLC, 1 bit) or multi-level cell (MLC, greater than or equal to 2 bits) operation may be performed on the memory cell20.

During operation, a voltage is applied to a selected word line (gate layer)38; for example, when a voltage higher than a corresponding threshold voltage (Vth) of the corresponding memory cell20is applied, a channel region of the channel pillar16intersecting the selected word line38is turned on to allow a current to enter the drain pillar32bfrom the bit line BLnor BLn+1(shown inFIG.1BandFIG.1D), flow to the source pillar32avia the turned-on channel region (e.g., in a direction indicated by arrow60), and finally flow to the source line SLnor SLn+1(shown inFIG.1BandFIG.1D).

However, if the channel pillar16has a circular ring shape, a large electric field will be generated due to an overly large curvature, which will cause memory read disturb. In the embodiment of the disclosure, in a top view, i.e., in a projection on the surface50sof the dielectric substrate50, the channel pillar16has an elongated profile such as a ring-shaped ellipse, and the charge storage structure40and the insulating pillar28may respectively be elliptical. The first conductive pillar32aand the second conductive pillar32b, which serves as the source pillar and drain pillar, are disposed on a long axis of the elliptical profile to increase the path therebetween, so that the effect of the electric field and memory read disturb can reduced.

Referring toFIG.1CandFIG.1E, the channel pillar16of the embodiment of the disclosure includes a first part P1and a second part P2. A projection of the first part P1and the second part P2are connected each other and a projection of a combination of the first part P1and the second part P2on the surface of the dielectric substrate50has an elliptical profile. The first part P1is located between the charge storage layer12and the insulating pillar28to serve as the channel region. A length L1of the first part P1is the length of the channel. A first region R1of the second part P2is in contact with and electrically connected to the first conductive pillar32a, and a second region R2of the second part P2is in contact with and electrically connected to the second conductive pillar32b. The curvature of the first part P1of channel pillar16is smaller than the curvature of the second part P2.

Referring toFIG.1C, in some embodiments, the first part P1and the second part P2of the channel pillar16are in contact with the inner sidewall of the charge storage structure40. The first part P1and the second part P2of the channel pillar16are both disposed between and in contact with the insulating pillar28and the charge storage structure40. The first conductive pillar32aand the second conductive pillar32bare located between the insulating pillar28and the second part P2of the channel pillar16and fill up the space between the insulating pillar28and the second part P2of the channel pillar16. The first conductive pillar32aand the second conductive pillar32brespectively have a recess shape with openings opposite to each other.

Referring toFIG.1DandFIG.1E, in other embodiments, an inner sidewall of the channel pillar16is conformal with the outer sidewall of the insulating pillar28. The first part P1of the channel pillar16is disposed between and in contact with the insulating pillar28and the charge storage structure40. The second part P2of the channel pillar16is disposed between and in contact with the first conductive pillar32aand the insulating pillar28, and is disposed between and in contact with the second conductive pillar32band the insulating pillar28. The first conductive pillar32aand the second conductive pillar32bare located between the second part P2of the channel pillar16and the charge storage structure40and fill up the space between the second part P2of the channel pillar16and the charge storage structure40. The first conductive pillar32aand the second conductive pillar32brespectively have a recess shape with openings opposite to each other.

Since the first part P1of the channel pillar16that serves as the channel region has a smaller curvature, it is possible to reduce the effect of the electric field and reduce the disturbance to the current in its traveling direction. Therefore, it is possible to improve the accuracy of memory reading.

FIG.2AtoFIG.2Iare schematic top views of a process of fabricating a 3D AND flash memory device according to an embodiment of the disclosure.FIG.3AtoFIG.3Iare schematic cross-sectional view taken along line IV-IV′ inFIG.2AtoFIG.2I.

Referring toFIG.2AandFIG.3A, a stack structure102is formed on a dielectric substrate100. The dielectric substrate100is, for example, a dielectric layer (e.g., a silicon oxide layer) over a metal interconnect structure formed on a silicon substrate. The stack structure102may be composed of sacrificial layers106and insulating layers104that are sequentially alternately stacked on the dielectric substrate100. The uppermost layer of the stack structure102may be the insulating layer104. The lowermost layer of the stack structure102may be the sacrificial layer106or the insulating layer104. The insulating layer104is, for example, a silicon oxide layer. The sacrificial layer106is, for example, a silicon nitride layer. In this embodiment, the stack structure102has five insulating layers104and four sacrificial layers106, but the disclosure is not limited thereto. In other embodiments, more insulating layers104and more sacrificial layers106may be formed according to the actual requirements.

Photolithography and etching processes are performed to form a plurality of openings108in the stack structure102. However, for simplicity, only one opening108is shown in figures. In this embodiment, the bottom surface of the opening108exposes the dielectric substrate100, but the disclosure is not limited thereto. In other embodiments, when the lowermost layer of the stack structure102is the insulating layer104, the bottom of the opening108may be located in the lowermost insulating layer104. Namely, the bottom surface of the opening108may expose the lowermost insulating layer104without exposing the dielectric substrate100. Alternatively, in other embodiments, the bottom of the opening108may further extend into the dielectric substrate100.

In this embodiment, in a top view, the opening108has an elongated profile. For example, the opening108has an elliptical profile with a long axis and a short axis, but the disclosure is not limited thereto. In other embodiments, the opening108may have a profile of other shapes such as a polygonal shape (not shown).

Referring toFIG.2BandFIG.3B, a thermal oxidation process is performed to oxidize the surface of the sidewall of the sacrificial layer106exposed by the opening108to form a protection layer110. Next, a channel material116′ is formed on the stack structure102and in the opening108. The material of the channel material116′ may be a semiconductor material such as undoped polysilicon.

Referring toFIG.2CandFIG.3C, next, the opening108is filled with a filling layer. In some embodiments, the filling layer is an insulating material (i.e., an insulating filling layer124). The insulating filling layer124is covered on the channel material116′. The material of the insulating filling layer124is, for example, silicon oxide.

Referring toFIG.2DandFIG.3D, an opening OP1′ is formed in the central region of the insulating filling layer124through photolithography and etching processes. The opening OP1′ has a circular shape, for example. The etching process is, for example, an anisotropic etching process such as a dry etching process.

Referring toFIG.2EandFIG.3E, a pull-back process is performed to remove a portion of the insulating filling layer124around the opening OP1′, so that the opening OP1′ is flared to form an opening OP1. The pull-back process may be an isotropic etching process such as a wet etching process. In an embodiment in which the insulating filling layer124is silicon oxide, the etching process may be a wet etching process using, for example, a hydrofluoric acid solution as the etchant. In contrast to the above dry etching process for forming the opening OP1′, a wet etching process is adopted for forming the opening OP1, so that a higher etch selectivity between the insulating filling layer124and the channel material116′ can be obtained. Therefore, during the pull-back process, in the short-axis direction of the opening108, the channel material116′ may serve as a stop layer; in the long-axis direction of the opening108, the insulating filling layer124may be continuously etched. Therefore, the opening OP1has an elongated profile. The opening OP1has, for example, an elliptical profile with a long axis and a short axis, but the disclosure is not limited thereto. In other embodiments, the opening OP1may have a profile of other shapes such as a polygonal shape (not shown). Afterwards, the channel material116′ below the opening OP1is removed. The sidewall of the opening OP1in the short-axis direction exposes the channel material116′; the sidewall of the opening OP1in the long-axis direction exposes the insulating filling layer124. With the high etch selectivity between the insulating filling layer124and the channel material116′, after the pull-back process, the channel material116′ (which will serve as the channel region) is hardly damaged.

Referring toFIG.2FandFIG.3F, next, an insulating material (e.g., silicon nitride) different from the material of the insulating filling layer124is filled in the opening OP1to completely seal the opening OP1. After the insulating material is etched back through a dry etching or wet etching process until the surface of the insulating filling layer124is exposed, the insulating material remaining in the opening OP1forms an insulating pillar128.

Referring toFIG.2GandFIG.3G, an etching process is performed to remove the insulating filling layer124and form holes130aand130bon two sides of the insulating pillar128. That is the opening OP1is divided into two compartments (i.e., holes130aand130b) by the insulating pillar128. In an embodiment in which the insulating filling layer124is silicon oxide, the etching process may be a wet etching process using, for example, a hydrofluoric acid solution as the etchant. The sidewalls of the holes130aand130bexpose the channel material116′ and the insulating pillar128. The bottoms of the holes130aand130bexpose the channel material116′. Since the etching rate of the insulating pillar128is lower than the etching rate of the insulating filling layer124, the insulating pillar128is hardly damaged by etching and remains.

Referring toFIG.2HandFIG.3H, a conductive layer is formed on the channel material116′ and the insulating pillar128and in the holes130aand130b. The conductive layer is, for example, doped polysilicon. The dopant in the doped polysilicon is, for example, N-type such as phosphorus or arsenic. The dopant in the doped polysilicon is, for example, P-type such as boron or boron trifluoride. Afterwards, the conductive layer and the channel material116′ are etched back through a dry etching or wet etching process until the surface of the stack structure102is exposed to form conductive pillars132aand132band a channel pillar116. The conductive pillars132aand132bmay respectively serve as a source pillar and a drain pillar. One sidewall SW1of the conductive pillars132aor132bis in contact with the insulating pillar128, and another sidewall SW2of the conductive pillars132aor132bis respectively electrically connected to the channel pillar116. The first conductive pillars132aand the second conductive pillars132boccupy the volume of the space between the insulating pillar128and the second portion P2of the channel pillar116. Therefore, the volumes of the first conductive pillar132aand the conductive pillar132bare substantially the same as the volumes of the spaces between the insulating pillar128and the second portion P2of the channel pillar116.

Afterwards, referring toFIG.2IandFIG.3I, a replacement process is performed. In some embodiment, the sacrificial layers106is replaced with a plurality of tunneling layers114, a plurality of charge storage layers112, and a plurality of gate layers138in the replacement process. First, a patterning process is performed on the stack structure102to form a plurality of slit trenches (not shown) therein, so that the stack structure102is divided into a plurality of blocks. Next, an etching process such as a wet etching process is performed by injecting an etching liquid into the slit trenches to sequentially remove the sacrificial layers106and form a plurality of horizontal openings134. Afterwards, a tunneling material, a storage material, and a gate material are sequentially formed in the slit trenches and the horizontal openings134. The material of the tunneling material is, for example, silicon oxide. The storage material is, for example, silicon nitride. The gate material is, for example, tungsten. Then, an etch-back process is performed to remove the tunneling material, the storage material, and the gate material in the slit trenches to form a plurality of tunneling layers114, a plurality of charge storage layers112, and a plurality of gate layers138in the horizontal openings134.

In other embodiments, in the slit trenches (not shown) and the horizontal openings134, in addition to the tunneling material, the storage material, and the gate material, a blocking material and a barrier material are further included between the storage material and the gate material. The material of the blocking material is, for example, a high dielectric constant material having a dielectric constant greater than or equal to 7, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (La2O5), transition metal oxide, lanthanide oxide, or combinations thereof. The material of the barrier material is, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. After an etch-back process is performed on the tunneling material, the storage material, the blocking material, the barrier material, and the gate material, a tunneling layer114, a charge storage layer112, a blocking layer136, a barrier layer137, and a gate layer138are formed in each of the horizontal openings134. The blocking layer136, the charge storage layer112, and the tunneling layer114are collectively referred to as a charge storage structure140. In a top view, an inner sidewall of tunneling layer114of the charge storage structure140is conformal with and in contact with the outer sidewall of the channel pillar116.

At this time, a gate stack structure150is formed. The gate stack structure150is disposed on the dielectric substrate100and includes a plurality of gate layers138and a plurality of insulating layers104stacked alternately with each other.

The protection layer110(shown inFIG.2HandFIG.3H) may be optionally removed or retained.FIG.2IandFIG.3Ishow that the protection layer110is removed before the tunneling material is formed. However, the disclosure is not limited thereto. In other embodiments, the protection layer110may be retained (not shown).

The insulating filling layer124and the insulating pillar128of the embodiment of the disclosure include different materials. In some embodiments, the insulating filling layer124is silicon oxide, and the insulating pillar128is silicon nitride, as shown inFIG.2AtoFIG.2IandFIG.3AtoFIG.3I. In other embodiments, the insulating filling layer124is silicon nitride, and the insulating pillar128is silicon oxide, as shown inFIG.4AtoFIG.4IandFIG.5AtoFIG.5I.FIG.4AtoFIG.4Iare schematic top views of a process of fabricating a 3D AND flash memory device according to an embodiment of the disclosure.FIG.4AtoFIG.4Iare schematic top view taken along line V-V′ inFIG.5AtoFIG.5I.

Referring toFIG.4AtoFIG.4DandFIG.5AtoFIG.5D, an insulating filling layer124and an insulating pillar128are formed according to the methods of the above embodiment, and the insulating filling layer124is silicon nitride, and the insulating pillar128is silicon oxide.

Referring toFIG.4EtoFIG.4GandFIG.5EtoFIG.5G, the pull-back process for forming the opening OP1and the etching process for removing the insulating filling layer124to form the holes130aand130bmay both be a wet etching process using, for example, a hot phosphoric acid as the etchant.

In the above embodiment, the opening108is first sequentially filled with the channel material116′ and the insulating filling layer124, and then the conductive layer serving as the source pillar and the drain pillar is formed. However, the disclosure is not limited thereto. In other embodiments, after the opening108is formed, the conductive layer serving as the source pillar and the drain pillar may be filled in the opening108first, and then the subsequent process is performed.

FIG.6AtoFIG.6Iare schematic top views of a process of fabricating a 3D AND flash memory device according to an embodiment of the disclosure.FIG.6AtoFIG.6Iare schematic top view taken along line VI-VI′ inFIG.7AtoFIG.7I.

Referring toFIG.6A,FIG.6B,FIG.7AandFIG.7B, a stack structure102and an opening108(as shown inFIG.6AandFIG.7A) are formed according to the methods of the above embodiment, and a protection layer110(as shown inFIG.6BandFIG.7B) is formed on the sidewall of the sacrificial layer106.

Referring toFIG.6CandFIG.7C, afterwards, the opening108is filled with a filling layer. In some embodiments, the filling layer is a conductive material (i.e., a conductive layer132). The conductive layer132is, for example, doped polysilicon. The dopant in the doped polysilicon is, for example, N-type such as phosphorus or arsenic. The dopant in the doped polysilicon is, for example, P-type such as boron or boron trifluoride.

Referring toFIG.6DandFIG.7D, an opening OP2′ is formed in the conductive layer132through photolithography and etching processes. The opening OP2′ is circular, for example. The etching process is, for example, an anisotropic etching process such as a dry etching process.

Referring toFIG.6EandFIG.7E, a pull-back process such as an etching process is performed to remove a portion of the conductive layer132around the opening OP2′, so that the opening OP2′ is flared to form an opening OP2. The pull-back process may be an isotropic etching process such as a wet etching process. In contrast to the above dry etching process for forming the opening OP2′, a wet etching process is adopted for forming the opening OP2, so that a higher etch selectivity between the protection layer110and the conductive layer132can be obtained. Therefore, during the pull-back process, in the short-axis direction of the opening108, the protection layer110may serve as a stop layer; in the long-axis direction of the opening108, the conductive layer132may be continuously etched. Therefore, the opening OP2has a long axis and a short axis. The opening OP2has an elliptical profile, for example, but the disclosure is not limited thereto. In other embodiments, the opening OP2may have a profile of other shapes such as a polygonal shape (not shown). The sidewall of the opening OP2in the short-axis direction exposes the protection layer110; the sidewall of the opening OP2in the long-axis direction exposes the conductive layer132; the bottom of the opening OP2exposes the dielectric substrate100. The conductive layer132will be used to form a source pillar and a drain pillar.

Since the channel material116′ (shown inFIG.6FandFIG.7F) is formed after the opening108(shown inFIG.6BandFIG.7B) is formed, and the channel material116′ does not have the issue of etching damage. In the process of forming the opening OP2, with the high etch selectivity between the conductive layer132and the protection layer110, after the pull-back process, even if the opening OP2exposes the protection layer110, the protection layer110is hardly damaged and has a smooth sidewall. The channel pillar116(FIG.6HandFIG.7H) subsequently formed on the sidewall of the protection layer110exposed by the opening OP2will serve as the channel region.

Referring toFIG.6F,FIG.6G,FIG.7FandFIG.7G, a channel material116′ is formed on the conductive layer132and in the opening OP2. Then, an insulating material such as silicon oxide is formed in the opening OP2to completely seal the opening OP2. The insulating material is etched back through a dry etching or wet etching process until the surface of the channel material116′ is exposed to form an insulating pillar128. Since the channel material116′ is formed on the smooth sidewall of the protection layer110, the portion (which will serve as the channel region) of the formed channel material116′ that is in contact with the protection layer110also has a smooth sidewall. The insulating pillar128separates the filling layer (the conductive layer132) into two sub-filling layers, and the two sub-filling layers form the conductive pillar132aand132bas shown inFIG.6HandFIG.7H.

Referring toFIG.6HandFIG.7H, the channel material116′ and the conductive layer132are etched back through a dry etching or wet etching process until the surface of the stack structure102is exposed to form a channel pillar116and conductive pillars132aand132b. The channel pillar116surrounds the sidewall of the insulating pillar128. The conductive pillars132aand132bmay respectively serve as a source pillar and a drain pillar. The conductive pillars132aand132bare separated by the insulating pillar128. Sidewalls of the conductive pillars132aand132bon one side are electrically connected to the channel pillar116, and sidewalls of the conductive pillars132aand132bon another side are in contact with the protection layer110.

Afterwards, referring toFIG.6IandFIG.7I, a replacement process is performed according to the above method. In some embodiments, the sacrificial layer106is replaced with a tunneling layer114, a charge storage layer112, and a gate layer138in the replacement process. In other embodiments, the sacrificial layer106is replaced with a tunneling layer114, a charge storage layer112, a blocking layer136, a barrier layer137, and a gate layer138in the replacement process. Likewise, the protection layer110may be optionally removed (as shown inFIG.6IandFIG.7I) or retained (not shown). One sidewall SW1of the conductive pillars132aor132bis respectively electrically connected to the channel layer116, and another sidewall SW2of the conductive pillars132aor132bis respectively in contact with the tunneling layer114. In some embodiments, a portion of the channel layer116that is in contact with the tunneling layer114serves as the channel region and has a smooth sidewall. The volumes of the first conductive pillar132aand the conductive pillar132bare substantially the same as the volumes of the spaces between the insulating pillar128and the charge storage structure140.

In the above embodiments, the charge storage layer112and the tunneling layer114are formed in the horizontal opening134. However, the disclosure is not limited thereto. In other embodiments, the charge storage layer112and the tunneling layer114may also be formed after the opening108is formed and before the channel material116′ is formed. The above embodiments have been described by taking a 3D AND flash memory device as an example. However, the embodiment of the disclosure is not limited thereto. The disclosure may also be applied to a 3D NOR flash memory.

The channel pillar of the flash memory device of the embodiment of the disclosure has an elongated profile in a top view. The first part of the channel pillar that serves as the channel region has a smaller curvature, which can reduce the effect of the electric field and reduce the disturbance to the current in its traveling direction. Therefore, it is possible to improve the accuracy of memory reading.

In the method of fabricating the flash memory device of the embodiment of the disclosure, the etching process for forming the source pillar and the drain pillar is performed before the channel pillar is formed. Therefore, the channel pillar is not damaged by etching during the formation of the source pillar and the drain pillar.