Patent ID: 12204794

After reading this Application, those skilled in the art would recognize that the figures are not necessarily drawn to scale for construction, nor do they necessarily specify any particular location or order of construction.

DETAILED DESCRIPTION

General Discussion

In one embodiment, a computing device can perform both read operations and write operations concurrently with one or more memory devices.

In one embodiment, one or more queues and/or buffers for read operations and/or write operations are maintained on the memory device, allowing the computing device to issue concurrent read commands and write commands, without requiring complex ordering or buffering circuitry on the computing device, or at least allowing the computing device to use only relatively simplified ordering or buffering.

In one embodiment, when a computing device issues a command for a read operation, the memory device receives the read command and buffers that command in a priority order assigned to that command, such as for relatively immediate processing, or otherwise as specified by a system designer or by the computing device. The memory device can perform the read command and respond with the requested response thereto on a communication link (or “bus”) directed from the memory device to the computing device, such as a data bus disposed to communicate read data. When the memory device performs the read command, it can respond with the read data on the communication link directed from the memory device to the computing device.

In one embodiment, when the computing device issues a command for a write operation, the memory device receives the write command and buffers that command for processing in a priority order for that command, such as for relatively immediate processing, or otherwise as specified by a system designer or by the computing device. The memory device can receive data associated with the write command on a separate communication link (or “bus”) directed from the computing device to the memory device. When the memory device performs the write command, it can respond with an acknowledgement on the communication link directed from the memory device to the computing device, or on a command/acknowledgement bus disposed to communicate acknowledgements.

Because the communication link (sometimes referred to herein as a “communication bus” or a “bus”) from the memory device to the computing device, disposed to communicate read data, is separate from the communication link from the computing device to the memory device, disposed to communicate write data, there is no particular requirement to allocate separate time slots on either communication link for read data and write data. This can have the effect that the computing device and the memory device can communicate read commands/responses and write commands/responses bidirectionally and without substantial delay.

Because the memory device can perform buffering and priority ordering of read operations and write operations without explicit instruction by the computing device, the computing device can operate without relatively complex circuitry to perform that buffering or priority ordering. For example, the computing device can make do with relatively simple buffering or priority ordering (such as in response to multiple requests for read/write operations from distinct subassemblies within the computing device), or in some cases, with almost no buffering or priority ordering circuitry. This can have the effect that the computing device can allocate space for circuitry, wiring, power; reduce the size, cost, or design complexity of the ASIC; or otherwise assign such circuitry, wiring, or power to functions preferred by a designer thereof.

Because the memory device can perform buffering and priority ordering of read operations and write operations without explicit instruction by the computing device, the memory device can operate without instruction by the computing device to optimize read operations and write operations with more than one memory bank. For example, the memory device can reorder or otherwise group read operations and write operations to provide that such operations can be directed to multiple memory banks in a manner that optimizes the number of operations performed by each memory bank, without the computing device having to be involved in any such optimization.

Because the computing device and the memory device can communicate bidirectionally without having to reserve time slots for delayed responses, the communication links between the two devices can operate more efficiently and without substantial wasted capacity. This can have the effects that fewer read/write operations are delayed, and that fewer read/write operations are buffered to wait while other operations are performed.

In one embodiment, the computing device can include an application-specific integrated circuit (ASIC), a processor, a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), a video processing unit (VPU), or another type of AI or ML device, a cryptography unit, a system-on-a-chip (SoC), a floating-point gate array (FPGA), another type of computing device that can interface with one or more memory devices, or a combination or conjunction of multiple ones or multiple types of such devices. In one embodiment, the memory device can include a dynamic RAM (DRAM), static RAM (SRAM), another type of memory such as a static RAM (SRAM), a synchronous DRAM (SDRAM), a double-data rate SDRAM (DDR), a low-power DDR (LPDDR), a high-bandwidth memory (HBM), a memory cache, a multi-level memory such as including one or more levels of cache and a memory device, a database, another type of memory device that can interface with one or more devices, or a combination or conjunction of multiple ones or multiple types of such devices.

Terms and Phrases

The following terms and phrases are exemplary only, and not limiting.

The phrases “this application”, “this description”, and variants thereof, generally refer to any material shown or suggested by any portions of this Application, individually or collectively, and including all inferences that might be drawn by anyone skilled in the art after reviewing this Application, even if that material would not have been apparent without reviewing this Application at the time it was filed.

The phrases “computing device”, and variants thereof, generally refer to any device (or portion thereof) that might be disposed to issue read and/or write commands to a “memory device”, such as described herein, or multiple ones or multiple types of such memory devices, whether in parallel or series, whether to one or more separate or banks thereof, whether to a distributed or singular such device, whether to a logically local or remote such device, or otherwise as described herein. For example, the computing device can include an application-specific integrated circuit (ASIC), a processor, a processor, a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), a video processing unit (VPU), or another type of AI or ML device, a cryptography unit, a system-on-a-chip (SoC), a floating-point gate array (FPGA), another type of computing device that can interface with one or more memory devices, a combination or conjunction of multiple ones or multiple types of such devices, or otherwise as described herein.

The phrases “memory device”, and variants thereof, generally refer to any device (or portion thereof) that might be disposed to receive read and/or write commands from a “computing device”, such as described herein, or multiple ones or multiple types of such computing devices, whether in parallel or series, whether to one or more separate or banks thereof, whether to a distributed or singular such device, whether from a logically local or remote such device, or otherwise as described herein. For example, the memory device can include a dynamic RAM (DRAM), static RAM (SRAM), another type of memory such as a static RAM (SRAM), a synchronous DRAM (SDRAM), a double-data rate SDRAM (DDR), a low-power DDR (LPDDR), a high-bandwidth memory (HBM), a memory cache, a multi-level memory such as including one or more levels of cache and a memory device, a database, another type of memory device that can interface with one or more devices, a combination or conjunction of multiple ones or multiple types of such devices, or otherwise as described herein.

The phrases “communication link”, “communication bus”, “bus”, and variants thereof, generally refer to any device (or portion thereof) that might be disposed to send information from a first device to a second device, whether or not that information is retained at the first device, whether or not that information is acknowledged or assured to be received by the second device, whether or not that information undergoes substantial delay or is transmitted by intermediate devices, or otherwise as described herein. For example, a communication link can include an electrical, optical, or electrooptical coupling between the first and second devices, a circuit-switched or packet-switched network including the first and second devices, a redundant modular or otherwise reliable distributed communication system, or otherwise as described herein.

After reviewing this Application, those skilled in the art would recognize that these terms and phrases should be interpreted in light of their context in the specification.

FIGURES AND TEXT

FIG.1—Interleaved Read and Write Transactions

FIG.1shows a conceptual drawing of a system including an interface between a computing device and a memory using interleaved read and write transactions.

In one embodiment, a system100can include one or more of: a computing device110, a memory device120, a command/address communication link130, and a data communication link140.

The computing device110can include an ASIC or another device disposed to issue read and/or write commands to the memory device120. The memory device120can include a DRAM or another device disposed to receive read commands and/or write commands from the computing device110. The communication links130and/or140are also sometimes referred to herein as a “bus” or “busses”130and/or140.

In one embodiment, the command/address bus130can include one or more time slots131, each disposed to communicate an address (such as a read address associated with a read command, or a write address associated with a write command). The command/address bus130can also include one or more typically much shorter time slots (not shown) associated with specific commands indicating whether the associated command is a read command or a write command and/or acknowledgements of those read commands or write commands.

Separate Read/Write Communication Links

In one embodiment, the data bus140can be disposed to logically include a read communication link141, such as controlled by the memory device120. The read communication link141can include a sequence of read-data time slots142each allocated solely to read data to be communicated from the memory device120to the computing device110. The data bus140can be disposed to logically include a write communication link143, controlled by the computing device110. The write communication link143can include a sequence of write-data time slots144each allocated solely to write data to be communicated from the computing device110to the memory device120.

As the read communication link141is separate from the write communication link143, read data can be communicated using the read-data time slots142on the read communication link141concurrently with write data being communicated using the write-data time slots144on the write communication link143. This can have the effect that both the read communication link141and the write communication link143can operate concurrently. Thus, the computing device110and the memory device120need not allocate extra read-data time slots142or write-data time slots144.

As described herein, the command/address bus130can include one or more (typically much shorter) time slots (not shown), each of which can indicate whether the associated command is a read command or a write command, and each of which can include an acknowledgement of a read command or a write command. In alternative embodiments, acknowledgements of read commands or write commands can be disposed on one or more (typically much shorter) time slots (not shown), on the read communication link141or write communication link143.

As described herein, the read communication link141and the write communication link143can include separate physical wires suitable for communicating electromagnetic signals (thus, in parallel and possibly concurrently), or can be combined into a single physical wire suitable for communicating multiple electromagnetic signals (thus, possibly concurrently). In the latter case, the single physical wire can be disposed to communicate the multiple electromagnetic signals concurrently or simultaneously, thus, with the effect that read operations and write operations can be performed at the same time.

Read/Write Communication Delays

As the read communication link141is separate from the write communication link143, a (read) delay between issue of a read command on the command/address bus130and an associated read-data time slot142on the read communication link141need not have any particular relationship to a (write) delay between issue of a write command on the command/address bus130and an associated write-data time slot144on the write communication link143. Similarly, a (read) delay between issue of a read command and an associated acknowledgement thereof, need not have any particular relationship to a (write) delay between issue of a write command and an associated acknowledgement thereof. However, in practice it is common for a (read) delay between issue of a read command and an associated acknowledgement thereof, and for a (write) delay between issue of a write command and an associated acknowledgement thereof, to each occur on a clock cycle associated with the interface between the computing device110and the memory device120.

While the figure shows a delay of about half of a read-data time slot142between issue of a read command from the computing device110and a response from the memory device120with associated read data, the actual delay would likely be driven by delay incurred by the memory device120itself. For example, when the memory device120includes a multi-level memory (or when the memory device120includes a relatively larger DRAM with a relatively larger number of memory banks or a relatively slower access time), the actual delay incurred by the memory device120might depend on whether the requested data was found in a memory cache (a “cache hit”) or whether the requested data had to be requested from a slower and relatively more voluminous non-cache memory device (a “cache miss”). There is no particular requirement that the actual delay is in fact about half of a read-data time slot142; it might be shorter or longer.

Similarly, while the figure also shows a delay of about half of a write-data time slot144between issue of a write command and issue of the associated write data, the actual data would likely be driven by delay incurred by the computing device110, and possibly also a timing protocol with respect to when the memory device120expects write data from the computing device110. For example, when the computing device110issues a write command from a register file, the actual delay incurred by the computing device110might depend on a read sensor associated with that register file; in contrast, when the computing device110issues a write command from an instruction pipeline, the actual delay incurred by the computing device110might depend on a branch prediction circuit or other circuit associated with decoding an instruction associated with that write command. There is no particular requirement that the actual delay is in fact about half of a write-data time slot144; it might be shorter or longer.

FIG.2—Read and Write Transaction Control

FIG.2(collectively includingFIGS.2A-2B) shows a conceptual drawing of a system including an interface between a computing device and a memory using read and write transaction control.

Computing Device Read/Write Commands

In one embodiment, the computing device110can include a set of computing circuits111, disposed to perform the functions of the computing device110, and a host fabric interface112, disposed to interface between the computing circuits111and a set of communication circuits113disposed to communicate with the memory device120. In one embodiment, the communication circuits113can include one or more of:A command queue113a, disposed to receive and process read/write commands114issued by the computing device110.A read queue113b, disposed to receive data responsive to read commands issued to the memory device120.A write queue113c, disposed to send data associated with write commands issued to the memory device120.An ordering/transaction optimization circuit113d, disposed to prioritize, select, and order commands to be issued to (and responses received from) the memory device120.

In one embodiment, when the computing circuits111issue a read/write command114to the memory device120, the host fabric interface112transmits that read/write command114to the communication circuits113. The communication circuits113can receive the read/write command114and maintain it in the command queue113auntil fully processed.When the read/write command114includes a read command, the communication circuits113can transfer the read command to the read queue113b, including a read address associated with the read command.When the read/write command114includes a write command, the communication circuits113can transfer the write command to the write queue113c, including a write address and write data associated with the write command.

In one embodiment, when the read/write command114arrives at the command queue113a, the ordering/transaction optimization circuit113dcan process those read/write commands114according to their nature.When the read/write command114includes a new read command, the ordering/transaction optimization circuit113dcan be disposed to order that the new read command according to a priority for that new read command, and for each one in order, to write a “read command” indicator to the command/address bus130and write an associated read address to the command/address bus130. For example, read commands can each be assigned a priority so as to provide that multiple read commands are directed to the same memory bank123at the memory device120when possible. The “read command” indicator and the associated read address are communicated to the command/address bus130to direct the memory device120to perform the read operation associated with the read command. When the memory device120completes the read operation, the memory device120can communicate the read data on the read communication link141in a read-data time slot142, and to raise an alert to inform the computing device110that the read operation has been performed. For example, as described herein, the alert informing the computing device110can be raised on the command/address bus130.For example, in current computing devices110, the ratio of read-operations to write-operations might not be excessively large, such as about a ratio of about 2:1, but it might occur that the computing device110operates more effectively when read operations have priority over write operations a very large fraction of the time, such as about 99% or more of the time. In such cases, it would be generally desirable for read operations to be given priority over write operations almost all of the time, and for write operations to be queued for later performance when read operations are not queued for current performance.When the read/write command114includes a new write command, the ordering/transaction optimization circuit113dcan be disposed to order that new write command according to a priority for that new write command, and, for each one in order, to write a “write command” indicator to the command/address bus130and write an associated write address to the command/address bus130. For example, write commands can each be assigned a priority so as to provide that each write command is performed before queued read commands. The “write command” indicator and the associated write address are communicated to the command/address bus130to direct the memory device120to perform the write operation associated with the write command. The associated write data is communicated on the write communication link143in a write-data time slot144, to be received and processed by the memory device120. When the memory device120completes the write operation, the memory device120can raise an alert to inform the computing device110that the write operation has been performed. For example, as described herein, the alert informing the computing device110can be raised on the command/address bus130.For example, in alternative computing devices110(not actually the preferred technique currently used in current computing devices110), it might occur that the computing device110operates more effectively when write operations have priority over read operations, so that when read operations are performed, those read operations cause data to be read from the memory device120that has been correctly written to the memory device120. In such cases, it would be generally desirable for write operations to be given priority over read operations, and for read operations to be queued for later performance when write operations have been completed.

As described herein, the computing circuits113, including the command queue113a, read queue113b, write queue113c, and ordering/transaction optimization circuit113dcan be substantially simplified with respect to a format that might been involved if priority ordering and allocation of read/write time slots were performed with respect to a single read/write communication link and were performed on the computing device110. Allocating the most difficult functions of the computing circuits113to the memory device120itself can have the effect that substantial complexity, space, and power requirements can be freed for other uses by the computing device110. Thus, performing priority ordering and allocation of read/write time slots on the memory device120can allow the computing circuits113on the computing device110to be relatively simpler and to occupy relatively less space and involve use of relatively less power.

For example, when the memory device120includes its own processing of read/write commands114and its own priority ordering thereof, this can have the effect that the computing device110can issue read/write commands114to the memory device120without substantial concern that those read/write commands114involve any particular ordering or any particular allocation of time slots on a single communication link for both read/write commands114. Read commands can be separately issued, in no particularly required sequence, using the read-data time slots142on the read communication link141, while write commands can be separately issued, in no particularly required sequence, using the write-data time slots144on the write communication link143.

Memory Device Read/Write Commands

In one embodiment, the memory device120can include a set of memory circuits121, disposed to perform the functions of the memory device120, and a memory command interface124, disposed to interface between the memory circuits121and a set of communication circuits122disposed to communicate with the computing device110.

In one embodiment, the memory device120can (optionally) include a set of multiple memory banks123, such as disposed to operate concurrently in response to read/write commands114from the memory circuits121. For example, when the memory device120includes 1 Gigabyte (GB) of memory elements (not shown), those memory elements can be disposed as 1,024 parallel memory banks123each being 1 Megabyte (MB) in size. For another example, the memory device120can include a different number of memory banks123having a different substantially uniform size. For another example, the memory device120can include a different number of memory banks123, not having a substantially uniform size, thus, at least some of which have a substantially different size.

In one embodiment, the memory device120can (optionally) include a multilevel memory structure, thus having at least some memory elements (not shown) which are relatively faster and likely relatively more expensive or less numerous, and at least some memory elements (not shown) which are relatively slower and likely relatively less expensive or more numerous. For example, the memory device120can include a set of cache elements (not shown) disposed to retain memory elements deemed likely to be more frequently accessed, at least in the near term, and a set of non-cache elements (not shown) disposed to retain memory elements deemed likely to be less frequently accessed, at least in the near term.

In one embodiment, the communication circuits122can include one or more of:A read queue122a, disposed to receive and process read/write commands114issued by the computing device110.A write queue122b, disposed to receive and process read/write commands114issued by the computing device110.An ordering/transaction optimization circuit122c, disposed to prioritize, select, and order read/write commands114to be performed by the memory device120, and responses issued to the computing device110.

In one embodiment, the memory device120is coupled to the command/address bus130and is coupled to the read communication link141and to the write communication link143.The read queue122acan be coupled to the read communication link141. When read commands are issued, in no particularly required sequence, using the read-data time slots142on the read communication link141, the memory device120is disposed to receive those read commands at the read queue122a.The write queue122bcan be coupled to the write communication link143. When write commands are issued, in no particularly required sequence, using the write-data time slots144on the write communication link143, the memory device120is disposed to receive those write commands at the write queue122b.

In one embodiment, when one or more read/write commands114are received at one or more of the read queue122aor the write queue122b, the ordering/transaction optimization circuit122ccan determine which one or more of those read/write commands114is to be given priority order. The ordering/transaction optimization circuit122ccouples the read/write command114that is given priority order to the memory circuits121to be performed.When a read command is given priority order, the ordering/transaction optimization circuit122ccouples that command to the memory circuit121to be performed. The memory circuit121performs the read command and communicates the read data to the read queue122a, which communicates the read data to the read communication link141, to be transmitted to the computing device110in a read time slot142in response to the associated read/write command114.When a write command is given priority order, the ordering/transaction optimization circuit122ccouples that command to the memory circuit121to be performed. The memory circuit121performs the write command and communicates successful performance to the write queue122b, which communicates successful performance to the write communication link143, to be transmitted to the computing device110as a raised alert on the command/address bus130in response to the associated read/write command114.

For example, when the one or more read/write commands114are directed to a set of distinct memory banks123associated with the memory device120, the memory device120can assign a priority order to those read/write commands114so as to provide that each set of read operations, or each set of write operations, directed to the same memory bank123, are performed concurrently. This can have the effect that the read/write commands114directed to the same memory bank123can be performed with relatively greater bandwidth, relatively lesser latency, and/or relatively less power involved in operating the memory bank123. For example, when a particular memory bank123is powered up for one or more read/write commands114, following accesses (within a selected time duration) to the same memory bank123can often involve substantially less power consumption and take substantially less time than if those following accesses were to occur later than that selected time duration.

In one embodiment, when one or more read/write commands114are received at one or more of the read queue122aor the write queue122b, it might occur that the ordering/transaction optimization circuit122cdetermines that both a read command and a write command can be performed concurrently. For example, the memory circuit121can perform a read command from a first bank of memory concurrently with performing a write command to a separate and non-overlapping second bank of memory.When both a read and a write command can be performed concurrently, the ordering/transaction optimization circuit122ccouples those commands to the memory circuit121to be performed concurrently. The memory circuit121performs both commands; it communicates a result of the read command to the read queue122aand communicates a result of the write command to the write queue122b.When the memory circuit121performs the read command, it communicates the read data to the read communication link141, to be transmitted to the computing device110in a read time slot142in response to the associated read/command114.When the memory circuit121performs the write command, it communicates successful performance to the write queue122b, which communicates successful performance to the write communication link143, to be transmitted to the computing device110as a raised alert on the command/address bus130in response to the associated read/write command114.

As described herein, when one or more queues and/or buffers for read/write commands114, including possibly read operations and/or write operations, are maintained on the memory device120, the computing device110can issue concurrent read/write commands114, including possibly read operations and/or write operations, without requiring complex ordering or buffering circuitry on the computing device, or at least allowing the computing device to use only relatively simplified ordering or buffering.

Giving Greater Priority Order to Write Commands than Read Commands

In one embodiment, the memory device120can give greater priority to read commands than to write commands, such as to provide speed to a computing device110that might otherwise wait for write operations to be completed before performing read operations. In such cases, the ordering/transaction optimization circuit122ccan give greater priority to read/write commands114received at the write queue122b(thus, write commands) than to read/write commands114received at the read queue122a(thus, read commands).

In such cases, the write queue122bshould be emptied by the memory device120at a relatively faster rate than the read queue122ais emptied. This can have the effect that the write queue122bcould be emptied substantially immediately upon receipt of write commands. Thus, all pending write commands would be completed before any pending read commands are performed.

With some computing devices110, instructions might be retrieved from the memory device120, such as from an instruction portion of program/data memory, and decoded and performed with as little latency as possible. Such computing devices110might reorder performance of those instructions so as to minimize latency, and might even perform instructions speculatively (thus, without knowing for sure whether results of those speculative instructions will actually be used). In such cases, when the results of a particular read operation are dependent upon the results of one or more write operations, the computing device110might have to wait for the write operation to be completed before performing the read operation. This can have the effect that pending write operations should be completed before performing pending read operations.

Giving Greater Priority Order to Read than Write Commands

In an alternative embodiment, the memory device120can give greater priority to read commands than to write commands, such as to provide speed to a computing device110that performs many more read operations than write operations. In such cases, the ordering/transaction optimization circuit112ccan give priority to read/write commands114received at the read queue122a(thus, read commands) over read/write commands114received at the write queue122b(thus, write commands).

In such cases, the read queue122ashould be emptied by the memory device120at a relatively faster rate than the write queue122bis emptied. In ordinary use of many computing devices110, this might be balanced by the read queue122aalso being filled by the computing device110at a similar relatively faster rate than the write queue122bis filled.It might occur that the computing device110does not fill the read queue122aas quickly as the memory device120empties the read queue122a. The ordering/transaction optimization circuit112cmight, given a choice between a relatively empty (or relatively rapidly emptying) read queue122aand a relatively full (or relatively rapidly filling) write queue122b, determine that the write queue122bshould be given priority order and can issue a read/write command114from the write queue122b.It might occur that the computing device110fills the read queue122amuch more quickly than the memory device120empties the read queue122a. The ordering/transaction optimization circuit112cmight determine that the write queue122bshould be given priority order and can issue a read/write command114from the write queue122b.Alternatively, the ordering/transaction optimization circuit122cmight decide to maintain excess read/write commands114from the write queue122bin alternative storage, such as a write command buffer. In such cases, the ordering/transaction optimization circuit He122ccan be disposed to determine which write commands are the least current priority and can be disposed to move those write commands to the write command buffer115.

As described herein, because the memory device120can perform buffering and priority ordering of read/write commands114without explicit instruction by the computing device110, the computing device110can operate without relatively complex circuitry to perform that buffering or priority ordering. For example, the computing device110can make do with relatively simple buffering or priority ordering (such as in response to multiple requests for read/write commands114from distinct subassemblies within the computing device), or in some cases, with almost no buffering or priority ordering circuitry. This can have the effect that the computing device110can allocate space for circuitry, wiring, power, or otherwise, to functions preferred by a designer thereof.

Because the computing device110and the memory device120can communicate bidirectionally without having to reserve either read time slots142or write time slots144for delayed responses, the read communication link141and the write communication link143between the two devices can operate more efficiently and without substantial wasted capacity. This can have the effects that fewer read/write commands114are delayed, and that fewer read/write commands114are buffered to wait while other operations are performed.

Alternative Embodiments

While this Application primarily describes a systems and techniques that primarily relate to communication between a computing device and a memory device, there is no particular requirement for any such limitation. After reading this Application, those skilled in the art will recognize that the techniques described herein are applicable to a wide variety of devices disposed to issue read and/or write commands, and to a wide variety of devices disposed to respond thereto. For example, the techniques described herein are applicable to a wide variety of different types of devices disposed to maintain information and to provide and/or revise that information upon request or command, such as caching systems and multi-level memory systems; file structures, hash tables, and/or graph structures; artificial intelligence or machine learning training systems; or otherwise as described herein.

Moreover, after reading this Application, those skilled in the art will recognize that the techniques described herein are applicable to a wide variety of different types of devices which can communicate using commands and/or data, and a wide variety of different types of data communication, whether communicated using read/write commands or otherwise. For example, the techniques described herein are applicable to a wide variety of different types of devices which can issue commands to request status of a device, such as possibly submitting a query to a database system or to a search engine, or possibly reading status of a hardware control system or a network monitoring system. For another example, the techniques described herein are applicable to a wide variety of different types of devices which can issue commands to command/respond to control status of a device, such as possibly writing to a database system or posting data to a network application, or such as altering status of a hardware control system or a circuit-switching or packet-switching communication network.

This Application describes a preferred embodiment with preferred process steps and, where applicable, preferred data structures. After reading this Application, those skilled in the art would recognize that, where any calculation or computation is appropriate, embodiments of the description can be implemented using general purpose computing devices or switching processors, special purpose computing devices or switching processors, other circuits adapted to particular process steps and data structures described herein, or combinations or conjunctions thereof, and that implementation of the process steps and data structures described herein would not require undue experimentation or further invention.

The claims are incorporated into the specification as if fully set forth herein.