Patent ID: 12206050

DESCRIPTION OF EMBODIMENTS

A mesa including, for example, a core layer of a multi quantum well structure (MQW) is disposed in a light emitting region and a modulator region. In a semi-insulating buried hetero (SIBH) structure, the mesa is embedded with a semi-insulating semiconductor layer. Since the use of the semi-insulating buried layer reduces a capacity of the modulator region, the SIBH structure is suitable for high speed modulation. On the other hand, in the semi-insulating buried layer, current confinement in the light emitting region is insufficient, and a current leaks into the buried layer. For this reason, it is difficult to increase an optical output, and in particular, it is difficult to operate at high output under high temperatures. It is therefore an object of the present invention to provide a semiconductor optical device and a method of manufacturing the semiconductor optical device, which are capable of performing high output and high speed modulation.

First, the contents of embodiments according to the present disclosure will be listed and described.

(1) An embodiment according to the present disclosure is a semiconductor optical device in which a light emitting region that emits light and a modulator region that modulates the light are integrated. The device includes a first mesa that is disposed in the light emitting region, extends in a light propagation direction in which the light propagates, protrudes in a direction intersecting the light propagation direction, and includes an active layer; a first buried layer and a second buried layer that are disposed on each of two sides of the first mesa in a direction intersecting the light propagation direction and are sequentially stacked in the direction in which the first mesa protrudes; a first semiconductor layer that is disposed on the first mesa and the second buried layer; a second mesa that is disposed in the modulator region, extends in the light propagation direction, protrudes in a direction intersecting the light propagation direction, and includes a light absorption layer; and a third buried layer that is disposed on each of two sides of the second mesa. The first semiconductor layer and the first buried layer each have a first conductivity type. The second buried layer has a second conductivity type different from the first conductivity type, and the third buried layer is a semi-insulating semiconductor layer. By stacking the first buried layer and the second buried layer in the light emitting region, strong current confinement can be achieved. Since a current is selectively injected into the active layer, high output can be achieved. By disposing the semi-insulating third buried layer in the modulator region, a parasitic capacitance can be reduced, and high speed modulation can be achieved.

(2) The first mesa may include a second semiconductor layer and the active layer that are sequentially stacked, the second mesa may include a third semiconductor layer, the light absorption layer, and a fourth semiconductor layer that are sequentially stacked. The second semiconductor layer and the third semiconductor layer each may have the second conductivity type, and the fourth semiconductor layer may have the first conductivity type. Since the first semiconductor layer having the first conductivity type is disposed on the active layer, and the second semiconductor layer having the second conductivity type is disposed under the active layer, the current can be injected into the active layer. The first semiconductor layer having the first conductivity type is disposed on the light absorption layer, and the third semiconductor layer having the second conductivity type is disposed under the light absorption layer, so that a voltage can be applied to the light absorption layer.

(3) The semiconductor optical device may include a resin layer that is disposed on each of two sides of the second mesa and outside of the third buried layer. Since the parasitic capacitance is further reduced, higher speed modulation can be achieved.

(4) The first semiconductor layer and the first buried layer each may include p-type indium phosphide, and the second buried layer may include n-type indium phosphide. By a pn buried structure in which the p-type first buried layer and the n-type second buried layer are disposed on each of two sides of the first mesa, the current confinement can be effectively performed and the output can be increased.

(5) The third buried layer may include semi-insulating indium phosphide. The high speed modulation can be performed by reducing the parasitic capacitance using semi-insulating indium phosphide.

(6) The second mesa may include a first tapered portion tapered from the modulator region toward the light emitting region in the light propagation direction and a second tapered portion tapered from the light emitting region toward the modulator region in the light propagation direction. The first tapered portion and the second tapered portion can strengthen an optical coupling between the first mesa and the second mesa and suppress return of light or the like between the light emitting region and the modulator region.

(7) The first mesa may include a diffraction grating extending in the light propagation direction. The light emitting region functions as a DFB laser.

(8) A method of manufacturing a semiconductor optical device is a method of manufacturing a semiconductor optical device in which a light emitting region that emits light and a modulator region that modulates the light are integrated. The method includes forming a first mesa including an active layer in the light emitting region; sequentially stacking, in a direction in which the first mesa protrudes, a first buried layer and a second buried layer on each of two sides of the first mesa in a direction intersecting a light propagation direction in which the light propagates; forming a first semiconductor layer on the first mesa and the second buried layer; forming a second mesa including a light absorption layer in the modulator region; and disposing a third buried layer on each of two sides of the second mesa. In the method, the first semiconductor layer and the first buried layer each have a first conductivity type, the second buried layer has a second conductivity type different from the first conductivity type, and the third buried layer is a semi-insulating semiconductor layer. By stacking the first buried layer and the second buried layer in the light emitting region, strong current confinement can be achieved. Since the current is selectively injected into the active layer, the high output can be achieved. By disposing a semi-insulating third buried layer in the modulator region, the parasitic capacitance can be reduced, and the high speed modulation can be achieved.

(9) the forming the second mesa may be forming the second mesa having a larger width than the first mesa. The stacking the first buried layer and the second buried layer may include stacking the first buried layer and the second buried layer on each of two sides of each of the first mesa and the second mesa. The method may include removing the first buried layer and the second buried layer on each of two sides of the second mesa and narrowing the second mesa. The disposing the third buried layer may be disposing the third buried layer on each of two sides of the second mesa after the narrowing the second mesa. Since the first buried layer and the second buried layer are removed from each of two sides of the second mesa to form the third buried layer, the parasitic capacitance can be effectively reduced.

DETAILS OF EMBODIMENTS OF THE PRESENT DISCLOSURE

Specific examples of the semiconductor optical device and the method of manufacturing the semiconductor optical device according to embodiments of the present disclosure will be described below with reference to the drawings. It should be noted that the present disclosure is not limited to these examples, and is defined by claims, and is intended to embrace all the modifications within the meaning and range of equivalency of the claims.

(Semiconductor Optical Device)

FIG.1Ais a perspective view illustrating a semiconductor optical device100according to an embodiment.FIG.1Bis a cross-sectional view in an XZ plane taken along line A-A inFIG.1A.FIG.2Ais a cross-sectional view taken along line B-B inFIG.1A.FIG.2Bis a cross-sectional view taken along line C-C inFIG.1A. An inclination that occurs in a buried layer or the like is omitted in the perspective view.FIG.3is a cross-sectional view in an XY plane taken along line A-A inFIG.1A. An X-axis direction is a light propagation direction. A Z-axis direction is a stacking direction of layers and is orthogonal to the X-axis direction. A Y-axis direction is orthogonal to the X-axis direction and the Z-axis direction.

As illustrated inFIGS.1A and1B, semiconductor optical device100has a butt-joint structure including a light emitting region10, a waveguide region52, and a modulator region50. Light emitting region10, waveguide region52, and modulator region50are disposed in this order in the X-axis direction. A length L1in the X-axis direction of light emitting region10illustrated inFIG.1Bis, for example, 300 μm or more and 600 μm or less. A length L2in the X-axis direction of modulator region50is, for example, 50 μm or more and 200 μm or less. A length L3in the X-axis direction of waveguide region52is, for example, 20 μm or more and 150 μm or less.

FIG.2Ais a cross-sectional view of light emitting region10. Light emitting region10functions as a distributed feed-back type (DFB) laser. In light emitting region10, a mesa13(a first mesa), buried layers24,26and32, and a cladding layer28are disposed on a substrate12. Mesa13is formed of a diffraction grating layer14, a cladding layer16(a second semiconductor layer), an active layer18, and a cladding layer20which are stacked in this order on an upper surface of substrate12. Mesa13is located near the center of substrate12in the Y-axis direction, and extends in light emitting region10in the X-axis direction. A width W1of mesa13is, for example, from 1 μm to 2 μm, inclusive.

A buried layer24(a first buried layer) is disposed on substrate12and on each of two sides of mesa13in the Y-axis direction. Two buried layers24sandwich mesa13. A buried layer26(a second buried layer) is disposed on each of buried layers24. Two buried layers26are spaced apart from each other and sandwich mesa13therebetween in the Y-axis direction. Cladding layer28is disposed on mesa13and buried layer26, and is in contact with cladding layer20between two buried layers26. A contact layer30is disposed on cladding layer20.

Two buried layers32(third buried layers) are disposed on substrate12and sandwich mesa13, buried layers24and26, and cladding layer28in the Y-axis direction. Insulating films34and35are sequentially disposed on contact layer30and buried layers32. An electrode38is disposed on insulating film35and is in contact with contact layer30through openings of insulating films34and35to be electrically connected to contact layer30. Electrode38is formed of a metal such as a stacked body of titanium, platinum, and gold (Ti/Pt/Au). An electrode36is disposed on a lower surface of substrate12and electrically connected to substrate12. Electrode36is formed of a metal such as an alloy of gold, germanium and nickel (AuGeNi).

Active layer18includes a plurality of well layers and barrier layers and has a multi quantum well structure (MQW). The well layers and the barrier layers are formed of, for example, undoped gallium indium arsenide phosphide (i-GaInAsP) or aluminum gallium indium arsenide (i-AlGaInAs). Diffraction grating layer14is formed of, for example, indium gallium arsenide phosphide (InGaAsP). Substrate12and cladding layer16are formed of, for example, n-type indium phosphide (n-InP) and function as n-type cladding layers. Buried layer26is formed of n-InP. An n-type dopant added to InP includes, for example, silicon (Si). Cladding layers20and28(corresponding to the first semiconductor layer), and buried layer24are formed of, for example, p-InP. A p-type dopant includes, for example, zinc (Zn). Buried layers32are formed of, for example, semi-insulating InP doped with iron (Fe). Contact layer30is formed of, for example, p++-type InGaAs. Insulating films34and35are formed of an insulator such as silicon oxide (SiO2).

N-type cladding layer16, active layer18of the MQW, p-type cladding layers20and28are stacked to form a p-i-n structure including mesa13in the Z-axis direction. P-type buried layer24, n-type buried layer26, and p-type cladding layer28are stacked on each of two sides of mesa13to form a pn buried structure.

FIG.2Bis a cross-sectional view of modulator region50. Modulator region50functions as an electroabsorption (EA)-type modulator. In modulator region50, a mesa43(a second mesa), buried layers32, and resin layers44are disposed on substrate12. Mesa43is located near the center of substrate12in the Y-axis direction, and extends in modulator region50and waveguide region52in the X-axis direction. In modulator region50, mesa43is formed of diffraction grating layer14, cladding layer16(a third semiconductor layer), a light absorption layer40, cladding layer20, cladding layer28(these two cladding layers correspond to a fourth semiconductor layer), and contact layer30, which are stacked in this order on substrate12. A width W2of mesa43is, for example, from 1 μm to 2 μm, inclusive. Buried layer32is disposed on substrate12and on each of two sides of mesa43. Two buried layers32sandwich mesa43. As illustrated inFIG.3, in waveguide region52, mesa43has a waveguide layer54instead of light absorption layer40.

Insulating film34covers a top surface of substrate12, sides and top surface of buried layer32. Resin layers44are disposed on insulating film34and outside buried layers32. Two resin layers44sandwich mesa43and buried layers32in the Y-axis direction. Insulating film35is disposed on resin layers44. An electrode48is disposed on insulating film35. Electrode48is in contact with contact layer30through an opening of insulating film35to be electrically connected to contact layer30.

Light absorption layer40includes, for example, a plurality of well layers and barrier layers, and has a multi quantum well structure (MQW). The well layers and the barrier layers are formed of, for example, undoped gallium indium arsenide phosphide (i-GaInAsP) or aluminum gallium indium arsenide (i-AlGaInAs). N-type cladding layer16, light absorption layer40of the MQW, and p-type cladding layer20are stacked to form a p-i-n structure including mesa43in the Z-axis direction. Resin layers44are formed of, for example, benzocyclobutene (BCB) or the like. Electrode48is formed of a metal such as a stacked body of Ti/Pt/Au.

As illustrated inFIG.1B, light absorption layer40in modulator region50, waveguide layer54in waveguide region52, and active layer18in light emitting region10are disposed in the X-axis direction. Waveguide layer54in waveguide region52is formed of, for example, InGaAsP, and is optically coupled to active layer18and light absorption layer40. Waveguide layer54is disposed between cladding layer16and cladding layer20in the Z-axis direction.

No contact layer30is disposed in waveguide region52. Contact layer30and electrode48in modulator region50are insulated from contact layer30and electrode38in light emitting region10by insulating films34and35. Electrode36is disposed in light emitting region10, waveguide region52, and modulator region50. Protrusions and recesses extending in the X-axis direction are periodically disposed in a portion of diffraction grating layer14within light emitting region10. The protrusions and recesses function as a diffraction grating15. The diffraction grating may be disposed in active layer18.

FIG.3illustrates a cross section including active layer18, light absorption layer40, and waveguide layer54. As illustrated inFIG.3, a portion of mesa43in waveguide region52has tapered portions43aand43b. Specifically, tapered portions43aand43bare formed in diffraction grating layer14, cladding layers16and20, and waveguide layer54. Tapered portion43aof the two tapered portions is located near light emitting region10and is tapered from modulator region50toward light emitting region10along the X-axis direction. Tapered portion43bis located near modulator region50and is tapered from light emitting region10toward modulator region50along the X-axis direction. An inclination angle of each of tapered portions43aand43bwith respect to the X-axis direction is, for example, 10° or less.

In the X-axis direction, resin layers44extend from an end portion of semiconductor optical device100to a vicinity of the center of tapered portion43b. A width W3of buried layer32between resin layer44and light absorption layer40is, for example, 0.3 μm.

By injecting a current into active layer18in light emitting region10using electrodes38and36, light is emitted in the X-axis direction. An oscillation wavelength is controlled to, for example, 1550 nm by diffraction grating15. Since a band gap of waveguide layer54is larger than the energy of the light, waveguide layer54hardly absorbs the light. By applying a voltage to light absorption layer40in modulator region50using electrodes48and36, an absorbance of light absorption layer40is changed to modulate the light. The modulated light is emitted from the end face of semiconductor optical device100. Since tapered portion43bis disposed, coupling between light emitting region10and modulator region50is strengthened, and loss of light is suppressed. Since tapered portion43ais disposed, return of light from modulator region50to light emitting region10is suppressed.

As illustrated inFIG.2A, in light emitting region10, since p-type buried layer24, n-type buried layer26, and p-type cladding layer28are stacked, the current is blocked by buried layer26and is less likely to flow in the Z-axis direction through buried layers26and24. On the other hand, p-type cladding layers20and28are stacked on active layer18, and n-type cladding layer16is disposed under active layer18. By performing effective current confinement using the pn buried structure and selectively injecting a current to active layer18through cladding layer28, the high output can be achieved.

FIG.4is a schematic diagram illustrating characteristics of semiconductor optical devices. The horizontal axis represents a current inputted to light emitting region10, and the vertical axis represents an optical output. A solid line represents the characteristics of the semiconductor optical device according to the embodiment. A broken line represents the characteristics of a semiconductor optical device according to a comparative example. In the comparative example, semi-insulating buried layer32is disposed in both light emitting region10and modulator region50, and buried layers24and26are not disposed in light emitting region10.

The optical output increases as the current increases. However, in the comparative example, the optical output does not linearly increase when the current becomes equal to or greater than I1, and the optical output decreases when the current further increases. Current confinement by semi-insulating buried layer32is insufficient, resulting in current leakage, and making an efficient current injection difficult. At temperatures higher than room temperature (about 25° C.), such as 75° C. for example, a decrease in optical output is likely to occur.

On the other hand, in the embodiment, the optical output increases linearly even when the current is at I1 or above. The pn buried structure formed by buried layers24and26enables stronger current confinement than buried layer32, thereby increasing the optical output. For example, it is possible to perform high output operation even at high temperatures and obtain high optical output.

As illustrated inFIG.2B, in modulator region50, semi-insulating buried layer32is disposed on each of two sides of mesa43. A parasitic capacitance of modulator region50is lower than that of light emitting region10having the pn buried structure, and the high speed modulation is possible.

(Manufacturing Method)

Referring toFIGS.5A to18C, a method of manufacturing semiconductor optical device100will be described.FIGS.5A,6,7A,8A,9A,10A,11A,12A and13Aare plan views illustrating the method of manufacturing semiconductor optical device100.FIGS.14A,15A,16A,17A and18Aare perspective views illustrating the method of manufacturing semiconductor optical device100.FIGS.5B,7B,8B,9B,10B,11B,12B and13Bare cross-sectional views taken along line D-D of the corresponding plan views.FIGS.7C,8C,9C,10C,11C,12C and13Care cross-sectional views taken along line E-E in the corresponding plan views.FIGS.14B,15B,16B,17C and18Care cross-sectional views taken along line C-C in the corresponding perspective views.FIGS.17B and18Bare cross-sectional views taken along line B-B in the corresponding perspective views. In the perspective views, inclination that may occur on surfaces of buried layers or the like is omitted, and the surfaces are illustrated as a plane.

As illustrated inFIGS.5A and5B, diffraction grating layer14, cladding layer16, and active layer18are sequentially epitaxially grown on substrate12by an organometallic vapor phase epitaxy method or the like.

As illustrated inFIG.6, mask60formed of, for example, silicon oxide (SiO2) is disposed on active layer18. A portion of active layer18to be mesa13in light emitting region10is covered with mask60. A portion of active layer18exposed from mask60is removed by etching, and light absorption layer40and waveguide layer54are epitaxially grown after the etching. Each thickness of light absorption layer40and waveguide layer54is equal to the thickness of active layer18. Thereafter, mask60is removed, and a p-InP cladding layer20(not illustrated inFIG.6) is grown.

As illustrated inFIGS.7A to7C, a mask62is disposed on cladding layer20. Mask62extends from one end to the other end of substrate12in the X-axis direction and covers the central portion of cladding layer20in the Y-axis direction. A width in the Y-axis direction of mask62in modulator region50is, for example, 10 and a width in the Y-axis direction of mask62in light emitting region10is, for example, from 1 μm to 2 μm, inclusive. The width of mask62gradually decreases from modulator region50toward light emitting region10. That is, mask62has a tapered portion62athat is tapered in the X-axis direction (e.g. +X direction). Portions of diffraction grating layer14, cladding layers16and20, active layer18and light absorption layer40which are exposed from mask62are removed by etching. The etching is, for example, dry etching such as a reactive ion etching (RIE), or wet etching. As illustrated inFIG.7B, mesa13is formed in light emitting region10. As illustrated inFIG.7C, mesa43is formed in modulator region50. Substrate12is exposed on both sides of each of mesa13and43. The width of mesa43is greater than the width of mesa13. Tapered portion62aof mask62is transferred to mesa43to form tapered portion43ainFIG.3.

As illustrated inFIGS.8A to8C, buried layers24and26are epitaxially grown in order on a surface of substrate12which is exposed from mask62by, for example, an OMVPE method. P—InP buried layer24is grown by introducing a p-type dopant into a growth apparatus together with source gases. The dopant is switched to an n-type dopant to grow n-InP buried layer26. After the growth, mask62is removed.

As illustrated inFIGS.9A to9C, cladding layer28and contact layer30are epitaxially grown in order on mesas13and43, and buried layer26by, for example, the OMVPE method.

As illustrated inFIGS.10A to10C, a mask64is disposed on contact layer30. As illustrated inFIG.10A, the width of mask64gradually decreases from light emitting region10toward modulator region50, and, for example, is 10 μm in light emitting region10, and 1 μm to 2 μm in modulator region50. That is, mask64has a tapered portion64athat is tapered in the X-axis direction (e.g. −X direction). As illustrated inFIG.10B, the width of mask64is greater than the width of mesa13. As illustrated inFIG.10C, the width of mask64is less than the width of mesa43.

As illustrated inFIGS.11A to11C, portions of buried layers24and26, cladding layer28, and contact layer30that are exposed from mask64are removed by etching. As illustrated inFIG.11B, since the width of mask64is greater than the width of mesa13, buried layers24and26remain on both sides of mesa13. Cladding layer28and contact layer30remain on mesa13and buried layer26. As illustrated inFIG.11C, mesa43is narrowed, and buried layers24and26, cladding layer28, and contact layer30are removed from both sides of mesa43. Cladding layer28and contact layer30remain on mesa43. Tapered portion64aof mask64is transferred to mesa43to form tapered portion43binFIG.3.

As illustrated inFIGS.12A to12C, semi-insulating buried layer32is epitaxially grown on a surface of substrate12which is exposed from mask64. As illustrated inFIG.12B, in the Y-axis direction, buried layer32is located on each of two sides of mesa13and outside buried layers24and26, cladding layer28, and contact layer30. As illustrated inFIG.12C, buried layer32is disposed on each of two sides of mesa43. After the formation of buried layer32, mask64is removed.

As illustrated inFIGS.13A to13C, mask66is disposed. As illustrated inFIG.13B, mask66covers the entire light emitting region10. As illustrated inFIG.13C, mask66covers the entire mesa43and a portion of buried layer32. An upper surface of buried layer32outside the covered portion in the Y-axis direction is exposed from mask66.

As illustrated inFIGS.14A and14B, etching is performed to remove a portion of buried layer32outside the portion covered with mask66in the Y-axis direction. The portion of the buried layer32covered with mask66remains. The upper surface of substrate12and the side surfaces of buried layer32are exposed by etching. After the etching, mask66is removed.

As illustrated inFIGS.15A and15B, insulating film34is disposed on the upper surface of contact layer30, the upper and side surfaces of buried layer32, and the upper surface of substrate12by a chemical vapor deposition (CVD) method, for example. Mask66may be used as a part of insulating film34without being removed.

As illustrated inFIGS.16A and16B, resin layer44is disposed on the upper and side surfaces of insulating film34. As illustrated inFIG.16B, both sides of mesa43and buried layers32are embedded with resin layer44.

As illustrated inFIG.17A, an upper portion of resin layer44is removed by, for example, polishing or the like so that the upper surface of resin layer44and the upper surface of insulating film34in light emitting region10have substantially the same height. Thereafter, a portion of contact layer30between light emitting region10and modulator region50is removed by etching or the like to insulate light emitting region10and modulator region50(seeFIG.1B). As illustrated inFIGS.17A to17C, insulating film35is disposed on the upper surfaces of resin layer44and insulating film34.

As illustrated inFIG.18A, electrodes36,38and48are disposed. As illustrated inFIGS.18B and18C, openings are provided in insulating films34and35by resist patterning and etching or the like. Electrodes38and48are disposed on insulating film35by vapor deposition or the like, and electrode36is disposed on a lower surface of substrate12. Through the above steps, semiconductor optical device100is formed.

According to the present embodiment, as illustrated inFIG.2A, mesa13including active layer18is disposed in light emitting region10. A current is injected into active layer18through p-type cladding layer28. By the pn buried structure in which p-type buried layer24and n-type buried layer26are stacked on each of two sides of mesa13, current leakage to the buried layer is suppressed and current confinement can be enhanced. The high optical output can be obtained by selectively injecting the current into active layer18of mesa13. In particular, as illustrated inFIG.4, good characteristics can be achieved even at high temperatures and at high output. For example, semiconductor optical device100can be used for optical communications in data centers or the like.

As illustrated inFIG.2B, semi-insulating buried layer32is disposed on each of two sides of mesa43including light absorption layer40in modulator region50. Since the parasitic capacitance of modulator region50is lower than that of light emitting region10, the high speed modulation is possible. According to the embodiment, both of the high output and the high speed modulation can be achieved.

As illustrated inFIGS.2A and2B, n-type cladding layer16is disposed under active layer18and light absorption layer40, and p-type cladding layer20and28are disposed on active layer18and light absorption layer40, respectively. The p-i-n structure including active layer18is formed in mesa13of light emitting region10. On the other hand, the pn buried structure in which p-type buried layer24and n-type buried layer26are stacked is disposed on each of two sides of mesa13. Therefore, the current can be intensively injected into active layer18. The p-i-n structure including light absorption layer40is formed in mesa43of modulator region50. Semi-insulating buried layer32is disposed on each of two sides of mesa43. The parasitic capacitance can be reduced and a voltage can be applied to light absorption layer40. Both of the high output and the high speed modulation can be achieved.

As illustrated inFIG.2B, resin layer44is disposed on each of two sides of mesa43. Since the parasitic capacitance can be further reduced by resin layer44, light modulation can be performed at a higher speed.

Buried layer24, cladding layers20and28are formed of p-InP. Substrate12, buried layer24, and cladding layer16are formed of n-InP. A pn buried structure can be formed of InP. Buried layer32is formed of semi-insulating InP doped with Fe, which can reduce the parasitic capacitance. Compound semiconductors other than InP may be used for these layers. A p-type layer and an n-type layer may be alternately stacked, and the stacking order may be reversed from that in the embodiment.

As illustrated inFIG.11C, after removing buried layers24and26on each of two sides of mesa43and narrowing mesa43, buried layer32is disposed on each of two sides of mesa43as illustrated inFIG.12C. Since buried layer32is formed without the pn buried structure remaining on each of two sides of mesa43, the parasitic capacitance can be effectively reduced.

In the step illustrated inFIGS.7B and7C, the width of mesa13is smaller than that of mesa43. In the step illustrated inFIG.11C, mesa43in modulator region50is processed to be as thin as mesa13. In this step, tapered portions43aand43billustrated inFIG.3are formed. A slight positional deviation of, for example, several μm or less may occur between mesa13and mesa43of modulator region50. Tapered portions43aand43bcan enhance optical coupling between light emitting region10and modulator region50, and suppress return of light from modulator region50to light emitting region10. The inclination angle of each of tapered portions43aand43bwith respect to the X-axis direction is, for example, 5° or more and 10° or less. Abnormal growth of the buried layers can be suppressed.

InFIG.3, one end of waveguide layer54in the X-axis direction is located at the distal end of tapered portion43b, and the other end of waveguide layer54protrudes toward light emitting region10from the distal end of tapered portion43aby about 5 μm, for example. One end of waveguide layer54may protrude from the distal end of tapered portion43btoward modulator region50or may be located on light emitting region10. The other end of waveguide layer54may be located at the same position as the distal end of tapered portion43aor may be located closer to modulator region50than the distal end of tapered portion43a.

Diffraction grating15is disposed in diffraction grating layer14of Mesa13. Light emitting region10functions as a DFB laser. Diffraction grating15may be disposed in a layer other than diffraction grating layer14. Light emitting region10may function as a laser other than the DFB laser. Modulator region50may function as a modulator other than the EA modulator.

Embodiments according to the present disclosure have been described above. However, the present invention is not limited to the embodiment described above, and various modifications and changes can be made to the present invention within the scope of the gist described in the claims.