Patent ID: 12199598

DESCRIPTION OF THE EMBODIMENTS

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In the various figures, the same elements are denoted by the same or similar reference numerals. For the sake of clarity, the various parts in the figures are not drawn to scale.

The specific implementation of the invention will be further described in detail in combination with drawings and the embodiment.

FIG.3illustrates a circuit diagram of a circuit for preventing latch-up according to a first embodiment of the present invention. As shown inFIG.3, the circuit for preventing latch-up comprises a first transistor Q1, a second transistor Q2, and a control circuit10.

The first transistor Q1has a control terminal, a first terminal, and a second terminal, wherein the control terminal of the first transistor Q1is configured to receive a first control voltage VN, and the first terminal of the first transistor Q1is configured to receive a first supply voltage VH.

The second transistor Q2is of a type opposite to that of the first transistor Q1, and has a control terminal, a first terminal, and a second terminal the control terminal of the second transistor Q2is configured to receive a second control voltage VPand is connected to the second terminal of the first transistor Q1, the second terminal of the second transistor Q2is connected to the control terminal of the first transistor Q1, the first terminal of the second transistor Q2is configured to receive a second supply voltage VL. In the present embodiment, the first transistor Q1and the second transistor Q2are opposite-type bipolar transistors, with the control terminals being bases, the first terminals being emitters, and the second terminals being collectors.

In a preferred embodiment, the first transistor Q1is a PNP type bipolar transistor, and the second transistor Q2is an NPN type bipolar transistor.

The control circuit10is disposed on a path formed by the first transistor Q1and the second transistor Q2between the first supply voltage VHand the second supply voltage VL, and is used for disconnecting the path when the first control voltage VNand/or the second control voltage VPis out of a predetermined range.

In a preferred embodiment, the first predetermined range is adjustable according to a value of the first control voltage of the first transistor in a working state, so that the circuit for preventing latch-up having better stability and compatibility. For example, if the value of the first control voltage of the first transistor in the working state is 3V, the first predetermined range may be over 2.5V, so that the first switch transistor M1being turned off when the first control voltage changed to below 2.5V; if the value of the first control voltage of the first transistor in the working state is 5V, the first predetermined range may be over 4.5V, so that the first switch transistor M1being turned off when the first control voltage changed to below 4.5V.

The control circuit10is coupled between the first supply voltage VHand the first transistor Q1, and includes a first comparison module101and a first switch module102.

Wherein, the first comparison module101is used to output a first switch signal for turning off the first switch module102when the first control voltage VNis out of a first predetermined range; the first switch module102is used to disconnect the first supply voltage VHfrom the first transistor Q1when receiving the first switch signal.

In the present embodiment, the first comparison module101is a first comparator U1, and the first switch module102is a first switch transistor M1. A first input terminal of the first comparator U1receives the first control voltage VN, a second input terminal of the first comparator U1receives a first reference voltage VRH, and the output terminal of the first comparator U1is connected to a control terminal of the first switch transistor M1;

a first terminal of the first switch transistor M1receives the first supply voltage VH, and a second terminal of the first switch transistor M1is connected to the first terminal of the first transistor Q1.

When the first control voltage VN<the first reference voltage VRH, the first switch signal outputted by the first comparator U1controls the first switch transistor M1to be turned off. Wherein, the first reference voltage VRHmay be equal to the first supply voltage VH.

In a preferred embodiment, the first switch transistor M1is a PMOS transistor; the control terminal of the first switch transistor M1is a gate, the first terminal of the first switch transistor M1is a source, and the second terminal of the first switch transistor M1is a drain. The first switch signal is at a high level.

In a preferred embodiment, the first switch transistor M1is a NMOS transistor; the control terminal of the first switch transistor M1is a gate, the first terminal of the first switch transistor M1is a drain, and the second terminal of the first switch transistor M1is a source. The first switch signal is at a low level.

When a voltage disorder occurs (for example, a voltage disorder caused by static electricity or a circuit operation error), the first control voltage VNor the second control voltage VPmay be changed. If the first control voltage VNis caused to drop first, the first transistor Q1is turned on, and the first supply voltage VHis supplied to the control terminal of the second transistor Q2when a voltage difference between the first terminal and the control terminal of the first transistor Q1is greater than a turn-on voltage of the first transistor Q1, leading to the rise of the voltage VPat the control terminal of the second transistor Q2; the second transistor Q2is turned on when a voltage difference between the control terminal and the first terminal of the second transistor Q2is greater than a turn-on voltage of the second transistor Q2, generating a latch path. If the second control voltage VPis caused to rise first, the second transistor Q2is turned on, and the second supply voltage VLis supplied to the control terminal of the first transistor Q1when a voltage difference between the first terminal and the control terminal of the second transistor Q2is greater than a turn-on voltage of the second transistor Q2, leading to the drop of the first control voltage VN; the first transistor Q1is turned on when a voltage difference between the control terminal and the first terminal of the first transistor Q1is greater than a turn-on voltage of the first transistor Q1, generating a latch path.

Therefore, in the case of the voltage disorder, the first control voltage VNis directly or indirectly caused to drop. Comparing the first control voltage VNwith the first reference voltage VRH, the first comparator U1outputs the first switch signal to control the first switch transistor M1to be turned off when the first control voltage VN<the first reference voltage VRH, so that the current path of the first supply voltage VHis closed and no latch-up effect occurs.

The circuit for preventing latch-up provided by the present invention, by introducing the control circuit on the path formed by the first transistor and the second transistor between the first supply voltage and the second supply voltage, can disconnect the first supply voltage from the first transistor when the control voltage of the first transistor is out of a first predetermined range, so that a latch-up effect is prevented from occurring during power-on phase.

FIG.4illustrates a circuit diagram of a circuit for preventing latch-up according to a second embodiment of the present invention. Compared with the first embodiment, the difference is that the control circuit20is coupled between the second supply voltage VLand the second transistor Q2, and comprises a second comparison module201and a second switch module202.

Wherein, the second comparison module201is used to output a second switch signal for turning off the second switch module202when the second control voltage VPis out of a second predetermined range; the second switch module202is used to disconnect the second supply voltage VLfrom the second transistor Q2when receiving the second switch signal.

In a preferred embodiment, the second predetermined range is adjustable according to a value of the second control voltage of the second transistor in a working state, so that the circuit for preventing latch-up having better stability and compatibility. For example, if the value of the second control voltage of the second transistor in the working state is 3V, the second predetermined range may be below 3.5V, so that the second switch transistor M2being turned off when the second control voltage changed to over 3.5V; if the value of the second control voltage of the second transistor in the working state is 5V, the second predetermined range may be below 5.5V, so that the second switch transistor M2being turned off when the second control voltage changed to over 5.5V.

In the present embodiment, the second comparison module201is a second comparator U2, and the second switch module202is a second switch transistor M2. A first input terminal of the second comparator U2receives the second control voltage VP, a second input terminal of the second comparator U2receives a second reference voltage VRL, and the output terminal of the second comparator U2is connected to a control terminal of the second switch transistor M2;

a first terminal of the second switch transistor M2receives the second supply voltage VL, and a second terminal of the second switch transistor M2is connected to the first terminal of the second transistor Q2.

When the second control voltage VP>the second reference voltage VRL, the second switch signal outputted by the second comparator U2controls the second switch transistor M2to be turned off. Wherein, the second reference voltage VRLmay be equal to the second supply voltage VL.

In a preferred embodiment, the second switch transistor M2is a PMOS transistor; the control terminal of the second switch transistor M2is a gate, the first terminal of the second switch transistor M2is a drain, and the second terminal of the second switch transistor M2is a source. The second switch signal is at a high level.

In a preferred embodiment, the second switch transistor M2is a NMOS transistor; the control terminal of the second switch transistor M2is a gate, the first terminal of the second switch transistor M2is a source, and the second terminal of the second switch transistor M2is a drain. The second switch signal is at a low level.

In the case of the voltage disorder, the second control voltage VPis directly or indirectly caused to rise. Comparing the second control voltage VPwith the second reference voltage VRL, the second comparator U2outputs a second switch signal to control the second switch transistor M2to be turned off when the second control voltage VP>the second reference voltage VRL, so that the current path of the second supply voltage VLis closed and no latch-up effect occurs.

The circuit for preventing latch-up provided by the present invention, by introducing the control circuit on the path formed by the first transistor and the second transistor between the first supply voltage and the second supply voltage, can disconnect the second supply voltage from the second transistor when the control voltage of the second transistor is out of a second predetermined range, so that a latch-up effect is prevented from occurring in power-on phase.

FIG.5illustrates a circuit diagram of a circuit for preventing latch-up according to a third embodiment of the present invention. Compared with the first embodiment, the difference is that the control circuit includes a first control circuit10and a second control circuit20, wherein the first control circuit10is coupled between the first supply voltage VHand the first transistor Q1, and includes the first comparison module101and the first switch module102. The second control circuit20is coupled between the second supply voltage VLand the second transistor Q2, and comprises a second comparison module201and a second switch module202.

Wherein, the first comparison module101is used to output a first switch signal for turning off the first switch module102when the first control voltage VNis out of a first predetermined range; the first switch module102is used to disconnect the first supply voltage VHfrom the first transistor Q1when receiving the first switch signal.

In the present embodiment, the first comparison module101is a first comparator U1, and the first switch module102is a first switch transistor M1. A first input terminal of the first comparator U1receives the first control voltage VN, a second input terminal of the first comparator U1receives a first reference voltage VRH, and the output terminal of the first comparator U1is connected to a control terminal of the first switch transistor M1;

a first terminal of the first switch transistor M1receives the first supply voltage VH, and a second terminal of the first switch transistor M1is connected to the first terminal of the first transistor Q1.

When the first control voltage VN<the first reference voltage VRH, the first switch signal outputted by the first comparator U1controls the first switch transistor M1to be turned off. Wherein, the first reference voltage VRHmay be equal to the first supply voltage VH.

In a preferred embodiment, the first switch transistor M1is a PMOS transistor; the control terminal of the first switch transistor M1is a gate, the first terminal of the first switch transistor M1is a source, and the second terminal of the first switch transistor M1is a drain. The first switch signal is at a high level.

In a preferred embodiment, the first switch transistor M1is a NMOS transistor; the control terminal of the first switch transistor M1is a gate, the first terminal of the first switch transistor M1is a drain, and the second terminal of the first switch transistor M1is a source. The first switch signal is at a low level.

The second comparison module201is used to output a second switch signal for turning off the second switch module202when the second control voltage VPis out of a second predetermined range; the second switch module202is used to disconnect the second supply voltage VLfrom the second transistor Q2when receiving the second switch signal.

In the present embodiment, the second comparison module201is a second comparator U2, and the second switch module202is a second switch transistor M2. A first input terminal of the second comparator U2receives the second control voltage VP, a second input terminal of the second comparator U2receives a second reference voltage VRL, and the output terminal of the second comparator U2is connected to a control terminal of the second switch transistor M2;

a first terminal of the second switch transistor M2receives the second supply voltage VL, and a second terminal of the second switch transistor M2is connected to the first terminal of the second transistor Q2.

When the second control voltage VP>the second reference voltage VRL, the second switch signal outputted by the second comparator U2controls the second switch transistor M2to be turned off. Wherein, the second reference voltage VRLmay be equal to the second supply voltage VL.

In a preferred embodiment, the second switch transistor M2is a PMOS transistor; the control terminal of the second switch transistor M2is a gate, the first terminal of the second switch transistor M2is a drain, and the second terminal of the second switch transistor M2is a source. The second switch signal is at a high level.

In a preferred embodiment, the second switch transistor M2is a NMOS transistor; the control terminal of the second switch transistor M2is a gate, the first terminal of the second switch transistor M2is a source, and the second terminal of the second switch transistor M2is a drain. The second switch signal is at a low level.

In the case of the voltage disorder, the first control voltage VNis directly or indirectly caused to drop and the second control voltage VPto rise. Comparing the first control voltage VNwith the first reference voltage VRHand the second control voltage VPwith the second reference voltage VRL, the first comparator U1outputs a first switch signal to control the first switch transistor M1to be turned off when the first control voltage VN<the first reference voltage VRH, and the second comparator U2outputs a second switch signal to control the second switch transistor M2to be turned off when the second control voltage VP>the second reference voltage VRL, so that the current paths of the first supply voltage VHand the second supply voltage VLare closed and no latch-up effect occurs.

FIG.6illustrates a circuit diagram of a circuit for preventing latch-up according to a forth embodiment of the present invention. Compared with the third embodiment, the difference is that the control circuit further includes a voltage divider circuit30and a multiplexer40, preferably, further includes a latch50.

The voltage divider circuit30is connected between a reference supply VREFand ground GND, and is for providing initial reference voltages. For example, the voltage divider circuit30comprises a plurality of resistors R1-RNin series, and series nodes between the plurality of resistors R1-RNprovide a plurality of initial reference voltages. The reference supply VREFis a power supply that is not affected by temperature, for example, the reference supply VREFis a bandgap reference supply, or other power circuits with a combination of positive temperature coefficient and negative temperature coefficient.

The multiplexer40is connected to the voltage divider circuit30, and is for selecting a first reference voltage according to the value of the first control voltage of the first transistor in the working state, and/or selecting a second reference voltage according to a value of the second control voltage of the second transistor in the working state. The first predetermined range is a voltage range greater than the first reference voltage, and the second predetermined range is a voltage range less than the second reference voltage.

For example, if the value of the first control voltage of the first transistor in the working state is 3V, the multiplexer40selects 2.5V serves as the first reference voltage, and the first predetermined range is over 2.5V, so that the first switch transistor M1being turned off when the first control voltage changed to below 2.5V; if the value of the first control voltage of the first transistor in the working state is 5V, the multiplexer40selects 4.5V serves as the first reference voltage, and the first predetermined range is over 4.5V, so that the first switch transistor M1being turned off when the first control voltage changed to below 4.5V.

For example, if the value of the second control voltage of the second transistor in the working state is 3V, the multiplexer40selects 3.5V serves as the first reference voltage, and the second predetermined range is below 3.5V, so that the second switch transistor M2being turned off when the second control voltage changed to over 3.5V; if the value of the second control voltage of the second transistor in the working state is 5V, the second predetermined range is below 5.5V, so that the second switch transistor M2being turned off when the second control voltage changed to over 5.5V.

In a preferred embodiment, a control terminal of the multiplexer40receives the first control voltage to selects the first reference voltage, and/or a control terminal of the multiplexer40receives the second control voltage to selects the second reference voltage. In this embodiment, the circuit for preventing latch-up further includes a latch50connected to the multiplexer40, the latch50is for latching the first reference voltage and/or the second reference voltage, and sending the first reference voltage and/or the second reference voltage to the control circuit10/20.

InFIG.6, two voltage divider circuits30, two multiplexers40and two latches50are shown to control the control circuit10and the control circuit20respectively, it should be understood that the control circuit10and the control circuit20may share one voltage divider circuit30, one multiplexer40and one latch50.

The circuit for preventing latch-up provided by the present invention, by introducing the control circuit on the path formed by the first transistor and the second transistor between the first supply voltage and the second supply voltage, can disconnect the first supply voltage from the first transistor when the first control voltage of the first transistor is out of a first predetermined range, and can disconnect the second supply voltage from the second transistor when the second control voltage of the second transistor is out of a second predetermined range, so that a latch-up effect is prevented from occurring during power-on phase.

The present invention further provides an integrated circuit comprising the circuit for preventing latch-up according to any one of above embodiments.

The embodiments in accordance with the present invention, as described above, are not described in detail, and are not intended to limit the present invention to be only the described particular embodiments. Obviously, many modifications and variations are possible in light of the above. These embodiments has been chosen and described in detail in the specification to explain the principles and practical applications of the present invention so that those skilled in the art can make good use of the present invention and the modified invention based on the present invention. The invention is to be limited only by the scope of the appended claims and the equivalents of the appended claims.