Patent ID: 12225104

DETAILED DESCRIPTION

The current state of the art for short-distance wired data communication, such as between integrated circuits on a printed circuit board, exceeds 10 Gbps per wire, for a multiple-wire parallel communications channel. These considerable data rates demand accurate timing control, especially for the timing of the receiver data sampling operation. [Tajalli I] and [Tajalli II] describe generation of such timing clocks using Phase-Locked Loop (PLL) or Delay-Locked Loop (DLL) systems incorporating “matrix” phase comparison operations, in which multiple comparison results between different reference and local clock phases are performed, with the summed result providing a more accurate or informative measure of clock error.

Numerous forms of phase detectors are known to the art. A simple XOR or XNOR gate may be used to compare, as a non-limiting example, two square wave signals. One familiar with the art will observe that such a digital XOR output will be a variable-duty-cycle waveform which, when low pass filtered into an analog error signal, results in a proportional error signal centered in its analog signal range when the two input signals have a 90-degree phase offset relationship. InFIG.1, multiple dynamically-weighted XOR phase comparisons are made between reference clock signal Ck_Ref and phases of a local oscillator signal including phases VCO_000, VCO_090, VCO_180, VCO_270, resulting in an aggregate control signal. As taught by [Tajalli I] and [Tajalli II], appropriate adjustment of the weights of the various phase error components may be used to adjust the resulting lock phase of the PLL incorporating the matrix phase comparator, introduce additional poles or zeroes into the closed-loop PLL response, etc.

[Tajalli I] and [Tajalli II] additionally disclose that a digital XOR or XNOR gate may be decomposed into a transistor-level gate including sub-elements representing component AND operations subsequently ORed together to implement the desired composite function. Embodiments are described herein in which each such sub-element may be separately weighted so as to produce a more finely adjustable phase-error signal, that may be further combined with phase-error signals from other dynamically-weighted XOR gates receiving different phases of the local oscillator signal to generate the aggregate control signal, thus providing an interpolation.FIG.3is one example of this technique, where XOR gate113has been decomposed into individual AND terms310,320,330,340, each including a resistive weighting element, and all of which are ORed together to produce an aggregate control signal Iout that may be used for controlling phase adjustments in a local oscillator. Following standard practice for CMOS logic, NMOS sub-elements320and340implement the active-low function componentsIout=(x·y)+(x·y) and PMOS sub-elements310and330implement the active-high function components Iout=(x·y)+(x·y). Thus, the resulting phase-error signal output from gate113is composed of both positive-weighted (active-high) and negative-weighted (active-low) segments, allowing both active sourcing and sinking of output current.

FIGS.4A and4Billustrate further embodiments, in which configuration of the weighting operations for a decomposed gate such as that ofFIG.3is performed by enabling input bits t0, t1, t2, t3, rather than by configurable analog resistances. Specifically, they illustrate two versions of330inFIG.3, with quadrants310,320,340being implemented in similar fashion. Enabling each of input bits t0, t1, t2, t3turns on an enabling transistor in one of multiple parallel branch segments or paths, each contributing a fixed amount of current to result K. Thus, the number of such branch segments being enabled controls the overall amplitude, that is, weighting, of the overall result Iout. In a practical embodiment, the amount of current in each path may be controlled by appropriate selection of transistor geometry, as is well known in the art. As two examples offered without implying limitation,FIG.4Ashows transistor geometry chosen such that each parallel path contributes an equal amount of current, whileFIG.4Bshows transistor geometry chosen such that current contributions double for consecutive parallel paths. Thus, the embodiment ofFIG.4Amight be combined with unary (i.e. counting number) selection of input bits t0, t1, t2, t3using e.g., a thermometer code, whileFIG.4Bmay be combined with a binary number representation of input bits t0, t1, t2, t3.

FIG.5illustrates the results of utilizing the circuit ofFIG.4Ain each quadrant ofFIG.3. Enabling one, two, three, or all of t0, t1, t2, t3in330permits weighting of signal amplitude of weighted segment510. Similar adjustment in340allows configuration as shown by weighted segment520, adjustment of310allows configuration as shown by weighted segment530, and adjustment in320allows configuration as shown by weighted segment540. In this example using four branch segments paths per branch, a total of sixteen possible signal amplitudes may be obtained for the combined output Iout. In some embodiments, additional constraints may be applied, for example to maintain signal symmetry by always enabling equal numbers of PMOS and NMOS (i.e. positive weighted and negative weighted) branch segments.

As a further example, intentional control of the number of signal paths being enabled provides the ability to adjust lock phase without introduction of a dedicated phase interpolation device. A matrix phase comparator configuration similar to that ofFIG.1is assumed, although for descriptive simplicity only two-phase comparison elements113will be considered. A simplified block diagram of the resulting PLL configuration is shown inFIG.2, with the two-phase comparator elements113in the first instance comparing phase VCO_000 of the local oscillator signal to Ck_Ref, and in the second instance comparing phase VCO_090 of the local oscillator signal to Ck_Ref. The branch segment weights of each phase comparator are adjusted207,208to produce weighted segments that are subsequently combined and low-pass filtered230to generate the aggregate control signal that may be used to control the Voltage-Controlled Oscillator (VCO)240producing the phases of the local oscillator signal VCO_000 and VCO_090 to induce a phase offset into the phases of the local oscillator signal.

A Phase Interpolation Control Signal Generator205accepts a Phase Value input and produces control signals207,208, which, by selectively enabling numbers of branch segments in the first dynamically-weighted XOR gate and in the second dynamically-weighted XOR gate, control the relative contribution of each phase comparator instance to the aggregate control signal that may be low-pass filtered230and provided to VCO240.

FIGS.6-10are timing diagrams that illustrate formation of aggregate control signals, in accordance with some embodiments. References toFIG.3are made in the following descriptions, however it should be noted that similar examples and concepts may be extended to other similar systems.FIG.6illustrates a timing diagram of an interpolation between phases VCO_000 and VCO_090 of the local oscillator signal. As shown,FIG.6is the state of the weighted segments of phase-error signals error_000 and error_090 immediately after turning branches330and340off in a circuit as shown inFIG.3that is receiving a reference clock signal and phase VCO_000 of the local oscillator signal, and turning branches330and340on in a circuit as shown inFIG.3that is receiving the reference clock signal and phase VCO_090 of the local oscillator signal. As shown, an aggregation of the shaded portions of weighted segments error_000 and error_090 is mostly negative, and thus the local oscillator is rotated to bring the aggregate control signal to an average of zero, indicating locked condition.

FIG.7illustrates the relationship of phases VCO_000 and VCO_090 of the local oscillator signal with respect to the reference clock signal upon reaching lock condition. As shown, phases VCO_000 and VCO_090 have undergone a −45 degree phase shift with respect to the reference clock signal, and a phase of 45 is now locked to the 90-degree lock point of the phase detector. One would expect such a shift, as half of the XOR detector receiving phase VCO_000 is turned on while half of the XOR detector receiving phase VCO_090 is also turned on, and thus both phases are making equal contributions to the aggregate control signal. As will be further noted, the aggregation of weighted segments of phase-error signals error_000 and error_090 thus as an average result of 0, and the VCO is thus in a lock condition in which phases VCO_000 and VCO_090 have undergone a −45 degree phase shift with respect to the 90-degree lock point described above.

FIG.8illustrates a similar scenario, however inFIG.8, branches330and340are turned off for phase VCO_000, while branches330and340are turned on in phase VCO_270. As expected, phases VCO_000 and VCO_270 undergo a +45 degree phase shift with respect to the previous lock point, and thus a phase of 315 degrees is now locked to the 90-degree lock point of the phase detector.

The above examples describe fully turning branches on/off for simplicity of discussion, however, as shown inFIG.3, a branch may include a plurality of branch segments that may be individually turned off/on in adjacent phases of the local oscillator signal so that such AND operations may partially contribute to more than one phase-error signal. For example, as shown inFIG.3, t0 and t1 may be turned off/on in the dynamically-weighted XOR gates receiving phases VCO_000/VCO_090, respectively, which only constitutes as one half of branch330. Such a scenario is illustrated inFIG.9. InFIG.9, only t0 and t1 are turned off in the dynamically-weighted XOR receiving phase VCO_000, and only t0 and t1 are turned on in the dynamically-weighted XOR receiving phase VCO_090. As shown, such a configuration introduces a proportionately smaller offset of approximately −11.25 degrees of phase VCO_000 of the local oscillator signal with respect to the 90-degree lock point to the reference clock signal. The weighted segments of phase-error signals error_000 and error_090 are illustrated inFIG.9. As shown, the weighted segment associated with branch330of phase-error signal error_000 has half the amplitude with respect to the rest of the branches, as only two branch segments are contributing to the weighted segment, while all four branch segments contribute to the rest of the weighted segments of phase-error signal error_000.

In yet another embodiment, simply turning one or more branch segments off in a branch of a dynamically-weighted XOR gate will induce a phase shift, even without turning the corresponding branch segments on in a dynamically-weighted XOR gate receiving an adjacent phase of the local oscillator signal. Such an embodiment is shown inFIG.10. InFIG.1, branch segments t0 and t1 are turned off in the dynamically-weighted XOR gate receiving phase VCO_000 of the local oscillator signal, while no branch segments are turned on in the dynamically-weighted XOR gate receiving phase VCO_090. Such an embodiment induces a phase offset into the phases of the local oscillator signal, as the positive and negative portions of the aggregate control signal adjust their widths, e.g., by rotating the phases of the local oscillator signal to change the duty cycle of the output of the XOR gate, to compensate for the sudden negative aggregate control signal until the total positive area and total negative area are equal, thus indicating locked condition. As one may notice, the phase shift induced by the embodiment shown inFIG.10will be larger than that ofFIG.9. InFIG.9, some of the positive portion of the aggregate control signal is added back in via the positively weighted segment of phase-error signal error_090, while inFIG.10, there is no contribution from error_090. Thus, a larger shift is induced into the phases of the local oscillator signal to compensate.

FIG.11illustrates a desired linear transfer function for the phase interpolation behavior, versus the inherent non-linear result if the two signals were simply mixed by enabling or disabling a fixed number of weighted segments per adjustment step. It may be observed that the non-linear curve produced by using a fixed increment is always “above” the desired linear response, thus linearization requires fewer segments to be enabled per step. In some embodiments, a predetermined sequence of steps may be determined to achieve a more linear phase interpolation relationship, if such a relationship is desired.

FIG.12Ais one such embodiment for closely approximating a linear interpolation operation, by selectively enabling 32 possible gating signals on a first of two phase-error signal outputs. Each instance of element1220represents one weighted segment in a circuit sub-element such as that ofFIG.4A, within a first dynamically-weighted XOR gate such as that ofFIG.3. Unary decoder1210enables a selected number of its outputs, as determined by input Step #. In such embodiments, each selected output may control a corresponding branch segment in a branch of the plurality of branches of a dynamically-weighted XOR gate. The linearization function is performed by selectively disconnecting certain instances of1220from the overall result Q (that is, not connecting that weighted segment to the corresponding branch segment.) Examples of disconnected branch segments include the instances of1220enabled by Unary16, Unary20, Unary22-23, Unary 25-27, and Unary 29-30.

In some embodiments, the number of branch segments enabled to control a first phase-error result and the number of branch segments enabled to control a second phase-error result are coordinated as illustrated by control signal generator205ofFIG.2. In at least one embodiment, the number of branch segments in the second phase-error signal are inversely-weighted with respect to branch segments in the first phase-error signal. A complementary embodiment controlling a second dynamically-weighted XOR gate receiving an adjacent phase is shown inFIG.12B. The outputs I and Q may correspond to phase-control signals207and208, respectively, or vice versa.

FIG.13is a flow chart of a method in accordance with some embodiments. As shown, method1300includes receiving1302a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches. A plurality of weighted segments of a phase error-signal are generated at1304, the plurality of weighted segments comprising (i) positive weighted segments generated by a first subset of the plurality of logic branches when the reference clock signal and the phase of the local oscillator signal have equal logic levels and (ii) negative weighted segments generated by a second subset of the plurality of logic branches when the reference clock signal and the phase of the local oscillator signal have different logic levels, each weighted segment of the phase-error signal having a respective weight applied by a corresponding logic branch of the plurality of logic branches. An aggregate control signal is generated1306based on an aggregation of the weighted segments of the phase-error signal, and the aggregate control signal is output1308as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.

In some embodiments, each logic branch comprises a plurality of branch segments connected in parallel. In such embodiments, the method further includes generating a phase-control signal comprising a plurality of bits. In some embodiments, each branch segment is enabled according to a respective bit of the plurality of bits of the phase-control signal. In some embodiments, each branch segment is enabled according to a corresponding enabling transistor receiving the respective bit as an input. In some embodiments, the respective weight for a given weighted segment is determined by a number of branch segments enabled in the logic branch.

In some embodiments, the respective weight for a given weighted segment is determined in part by transistor dimensions in the logic branch. In alternative embodiments, the respective weight for a given weighted segment is determined in part by a tunable impedance connected to the logic branch.

In some embodiments, the aggregate control signal is further generated based on weighted segments in a second phase-error signal generated using the reference clock signal and a second phase of the local oscillator signal that is adjacent to the phase of the local oscillator signal. In some such embodiments, weighted segments in the second phase-error signal are inversely-weighted with respect to weighted segments in the first phase-error signal. In some embodiments, the induced phase offset corresponds to a non-zero average of the aggregate control signal.

In some embodiments, a method includes receiving a reference clock signal, and first and second phases of a local oscillator signal. Corresponding sets of weighted segments of a first and a second phase-error signal are generated by comparing the reference clock signal to the first and the second phases of the local oscillator signal, respectively, each corresponding set of weighted segments generated by a plurality of logic branches of a respective dynamically-weighted XOR gate, wherein the weighted segments in each of the first and second phase-error signals comprise first and second sets of weights, respectively, the first and second sets of weights selected according to a predetermined phase-offset value. An aggregate control signal is generated based on a summation of the weighted segments of the first and second phase-error signals, and the aggregate control signal is output as a current-mode output for controlling a local oscillator generating the first and second adjacent phases of the local oscillator signal, the local oscillator configured to induce a phase offset into the first and second phases of the local oscillator signal in response to the aggregate control signal by an amount associated with the predetermined phase-offset value.

In some embodiments, the weighted segments in each of the first and second segmented phase-error signals include (i) positive weighted segments generated by a first subset of the plurality of logic branches when the reference clock signal and the corresponding phase of the local oscillator signal have equal logic levels and (ii) negative weighted segments generated by a second subset of the plurality of logic branches when the reference clock signal and the corresponding phase of the local oscillator signal have different logic levels.

In some embodiments, the first and second sets of weights correspond to a total number of logic branch segments enabled in the respective dynamically-weighted XOR gates.

In some embodiments, the first and second sets of weights are selected according to a phase-control signal representing the predetermined phase-offset value of the first and second phases of the local oscillator signal. In some such embodiments, the phase-control signal is generated by a phase-control signal generator. In some embodiments, the phase-control signal generator includes a lookup table and is configured to select a phase-control signal from the lookup table. In some such embodiments, the lookup table may include phase-control signal steps that implement a linear interpolation function. In some embodiments, the phase-control signal may be a thermometer code. In such embodiments, the dynamically-weighted XOR receiving the first phase of the local oscillator signal may receive a thermometer code that is an inverse of a thermometer code received by the dynamically-weighted XOR receiving the second phase of the local oscillator signal.

In some embodiments, the first and second phases of the local oscillator signal have phase differences of 45 degrees. In some embodiments, the first and second phases of the local oscillator signal may have phase differences of 90 degrees or 180 degrees. In some embodiments, the first and second phases of the local oscillator signal may be adjacent phases in that they are pulled from adjacent ring oscillator elements in a local oscillator.