Patent ID: 12189560

DETAILED DESCRIPTION OF THE EMBODIMENTS

As is traditional in the field of the inventive concepts, embodiments are described, and illustrated in the drawings, in terms of functional blocks, units and/or modules. Those skilled in the art will appreciate that these blocks, units and/or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, and the like, which may be formed using semiconductor-based fabrication techniques or other manufacturing technologies. In the case of the blocks, units and/or modules being implemented by microprocessors or similar, they may be programmed using software (e.g., microcode) to perform various functions discussed herein and may optionally be driven by firmware and/or software. Alternatively, each block, unit and/or module may be implemented by dedicated hardware, or as a combination of dedicated hardware to perform some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) to perform other functions. Also, each block, unit and/or module of the embodiments may be physically separated into two or more interacting and discrete blocks, units and/or modules without departing from the scope of the inventive concepts. Further, the blocks, units and/or modules of the embodiments may be physically combined into more complex blocks, units and/or modules without departing from the scope of the inventive concepts.

FIG.1is a block diagram of a system10according to at least one example embodiment of the inventive concepts. As illustrated inFIG.1, the system10may include a first device11and a second device12communicating with each other via a plurality of interconnections13.

The system10may be referred to as any system including the first device11and the second device12communicating with each other via the plurality of interconnections13. In some embodiments, the first device11and the second device12may include integrated circuits manufactured by a semiconductor process. For example, the first device11and the second device12may be included in the same die, and communicate with each other via the plurality of interconnections13formed in the die. For example, the first device11and the second device12may be respectively included in different dies, and communicate with each other via the plurality of interconnections13formed outside the dies. In some embodiments, the first device11and the second device12may be housed independently of each other, and may communicate with each other via the plurality of interconnections13exposed outside housings.

The first device11and the second device12may communicate with each other based on a physical interface known to each other. The physical interface may correspond to a physical layer among communication layers, and the first device11and the second device12may transceive signals via the plurality of interconnections13based on the physical interface. As used in the present specification, the terms “transceive” and “transceiving” refer to transmitting, receiving, or transmitting and receiving. According to at least some example embodiment of the inventive concepts, the plurality of interconnections13may be embodied by a medium that transmits signals between the first device11and the second device12. For example, the plurality of interconnections13may include conductive wires (for example, a through silicon via (TSV), a micro-bump (MB), etc. inFIG.15) for transmitting electrical signals, and may also include waveguides for transmitting optical signals. As illustrated inFIG.1, each of the plurality of interconnections13may be connected to a plurality of first pins P1of the first device11and a plurality of second pins P2of the second device12. One interconnection, and a first pin and a second pin connected thereto may be included in a signal path through which a signal travels, and one signal path may be referred to as a lane herein. In other words, one lane may include one interconnection (e.g., a connection between one of first pins P1and one of second pins P2), and the number of lanes may match the number of interconnections. According to at least some example embodiments of the inventive concepts, the physical interface between the first device11and the second device12includes the plurality of interconnections13, the plurality of first pins P1, and the plurality of second pins P2. According to at least some example embodiments of the inventive concepts, the physical interface between the first device11and the second device12further includes the first and second routing circuits11_2and12_2, and is controlled by one or both of the first controller11_1and the second controller12_1.

The first device11may include a first controller11_1, a first routing circuit11_2, and the plurality of first pins P1, and the second device12may include a second controller12_1, a second routing circuit12_2, and the plurality of second pins P2. As illustrated inFIG.1, the first controller11_1may provide a first control signal CTR1to the first routing circuit11_2, and the first routing circuit11_2may form a path through which a first signal SIG1passes based on the first control signal CTR1. Similarly, the second controller12_1may provide a second control signal CTR2to the second routing circuit12_2, and the second routing circuit12_2may provide a path through which a second signal SIG2passes based on the second control signal CTR2. Examples of the first routing circuit11_2and the second routing circuit12_2will be described later with reference toFIG.6.

In some embodiments, the number of lanes formed between the first device11and the second device12may be greater than the number of signal paths required for the physical interface, and the first device11and the second device12may communicate with each other via some of the plurality of lanes. The lanes used for communication between the first device11and the second device12may correspond to the paths formed by the first routing circuit11_2and the second routing circuit12_2, and may be determined by the first control signal CTR1and the second control signal CTR2. In other words, the first routing circuit11_2may select some of the plurality of first pins P1based on the first control signal CTR1, the second routing circuit12_2may select some of the plurality of the second pins based on the second control signal CTR2, and as a result, the lanes corresponding to the selected first and second pins P1and P2may be selected. One lane may include one interconnection and a pair of pins, and herein, selection and determination of the lanes may have the same meaning as selection and determination of the interconnections and/or the pins.

The first controller11_1and the second controller12_1may perform a training of a physical interface between the first device11and the second device12. Training of the physical interface may be referred to as an operation performed by a transmitting side and a receiving side for determining a timing of a signal transmitted by the transmitting side, so that the receiving side easily and effectively identifies the signal transmitted by the transmitting side. For example, a timing of the first signal SIG1provided to the first routing circuit11_2may be determined, so that information included in the first signal SIG1transmitted by the first device11via some of the plurality of interconnections13is identical to information identified from the second signal SIG2received by the second device12. In addition, the timing of the first signal SIG1provided to the first routing circuit11_2may be determined, so that the second device12more easily identifies information from the second signal SIG2. Similarly, a timing of the second signal SIG2transmitted by the second device12may be determined by using the training of the physical interface.

The first controller11_1and the second controller12_1may train the physical interface by using each of different candidate groups among the plurality of lanes, and may determine a lane group (or an interconnection group or a pin group) to be used for the physical interface based on the training results. To this end, the first controller11_1may select the candidate group among the plurality of lanes (or the plurality of interconnections13, or the plurality of first pins P1), and may generate the first control signal CTR1based on the selected candidate group. In addition, as illustrated by a dashed line inFIG.1, the first controller11_1and the second controller12_1may communicate with each other, the first controller11_1may provide information about the selected candidate group to the second controller12_1, and the second controller12_1may generate the second control signal CTR2based on information provided by the first controller11_1. In some embodiments, the first controller11_1and the second controller12_1may communicate with each other via at least some of the plurality of interconnections13, and may communicate with each other via a channel (for example, WS1through WSn inFIG.13) independent of the plurality of interconnections13.

The first controller11_1may identify the best training result among the training results respectively corresponding to the different candidate groups, and may determine a candidate group corresponding to the identified best training result as lanes (or interconnections or pins) for the physical interface. The first controller11_1may generate the first control signal CTR1based on the determined lanes, and may provide information about the determined lanes to the second controller12_1, and the second controller12_1may generate the second control signal CTR2based on information provided by the first controller11_1. Accordingly, interconnections that provide optimal performance (for example, margin) may be detected among the plurality of interconnections13, and as a result, the reliability of communication between the first device11and the second device12may be significantly improved. In addition, as the optimal margin corresponding to connection states of the first device11and the second device12is detected, defects due to the physical interface between the first device11and the second device12may be removed or reduced, and accordingly, the yield of the system10including the first device11and the second device12may be improved. The first controller11_1and/or the second controller12_1may have a structure that is designed and/or programmed for performing the above-described operations, and may include, for example, at least one core executing a series of instructions, a logic circuit designed by using logic synthesis, and a combination thereof. For example, one or both of the first controller11_1and the second controller12_1may be embodied by processing circuitry such as hardware including logic circuits; a hardware/software combination executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, one or more of a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

FIG.2is a flowchart of a method of training a physical interface, according to at least one example embodiment of the inventive concepts. As described above with reference toFIG.1, a first device21may be connected to a second device22inFIG.2via a plurality of interconnections, and a training of a physical interface may be performed.

Referring toFIG.2, the first device21and the second device22may verify lanes in operation S10. As described above with reference toFIG.1, the lane may correspond to one signal path through which a signal passes between the first device21and the second device22, and may include interconnection and a pair of pins connected thereto. Due to a defect of the first device21, a defect of the second device22, a defect of one or more interconnections between the first device21and the second device22, or the like, some of the plurality of lanes may be unavailable. Accordingly, the first device21and the second device22may verify the lanes, and detect valid lanes. When an invalid lane is detected, the first device21and the second device22may not use the interconnection and the pair of pins which are included in the invalid lane, and may communicate with each other via the interconnection and the pair of pins included in valid lanes. In this manner, an operation of detecting the invalid lane and replacing the invalid lane with the valid lane may be referred to as a lane repair, and for the lane repair, the first device21and the second device22may be interconnected to each other via a greater number of lanes than the number of signal paths required for the physical interface. Accordingly, even when some of the lanes are unavailable, the first device21and the second device22may communicate normally.

According to at least some example embodiments of the inventive concepts, the first device21and the second device22may detect valid (and/or invalid) lanes. In the present specification, detecting whether one or more lanes are valid (or invalid) may be referred to as verifying, or performing verification with respect to, the lane(s). According to at least some example embodiments, in order to verify a plurality of lanes, the first device21may transmit a known signal to the second device22via the plurality of lanes, the second device22may provide a signal as feedback received via the plurality of lanes to the first device21, and the first device21may detect the valid lane(s) from among the plurality of lanes based on the feedback of the second device22. In the present specification, verification of a lane may be referred to as verification of an interconnection and/or a pair of pins included in the lane; a lane, an interconnection, and a pin that have passed verification may be referred to as a valid (or verified) lane, a valid interconnection, and a valid pin, respectively; and a lane, an interconnection, and a pin that have failed verification may be referred to as an invalid lane, an invalid interconnection, and an invalid pin, respectively.

The first device21may select a first candidate group among the valid lanes in operation S20. The first candidate group may include the number of lanes required to communicate with the second device22based on the physical interface. In some embodiments, each of the first device21and the second device22may include pins pre-allocated for the physical interface and pins for the lane repair (which may be referred to as redundancy pins herein). The first device21may select the first candidate group, so that the pre-allocated pins are used for the physical interface in an initial training (e.g., a first training which will be described in greater detail below).

The first device21and the second device22may perform the first training of the physical interface in operation S30. For example, the first device21(or a routing circuit) may form internal paths including the pins corresponding to the first candidate group selected in operation S20, and may provide information about the first candidate group to the second device22, and the second device22may form the internal paths including the pins corresponding to the first candidate group based on the information provided by the first device21. The first device21and the second device22may perform the first training by using the first candidate group, and accordingly, a timing of a signal sent between the first device and the second device may be determined in the physical interface using the first candidate group. Examples of training of the physical interface will be described later with reference toFIGS.3A and3B, and an example of operation S30will be described in greater detail below with reference toFIG.7.

The first device21may select a second candidate group among the valid lanes in operation S40. The second candidate group may have the number of lanes required to communicate with the second device22based on the physical interface, and may be different from the first candidate group in operation S20. In some embodiments, the first device21may select the second candidate group based on a result of the first training in operation S30, and an example of operation S40will be described later with reference toFIG.7.

The first device21and the second device22may perform a second training of the physical interface in operation S50. For example, the first device21may form internal paths including the pins corresponding to the second candidate group selected in operation S40, may transmit information about the second candidate group to the second device22, and the second device22may form the internal paths including the pins corresponding to the second candidate group based on the information provided by the first device21. The first device21and the second device22may perform the second training by using the second candidate group, and accordingly, a timing of a signal sent between the first device and the second device may be determined in the physical interface using the second candidate group.

The first device21may determine a lane group including the lanes to be used for the physical interface in operation S70. For example, the first device21may determine the lane group based on the result of the first training performed in operation S30and the result of the second training performed in operation S50. An example of operation S50will be described in greater detail below with reference toFIG.8. In some embodiments, the first device21and the second device22may additionally perform at least one training prior to operation S70, and the lane group may be determined based on the results of the first training and the second training as well as the result of at least one training that has been additionally performed. For example, the first device21may select a third candidate group that is different from the first candidate group and the second candidate group among the valid lanes after operation S50, and the first device21and the second device22may perform the third training by using the third candidate group. According to at least some example embodiments, the first device21may identify a candidate group that provides desirable or, alternatively, optimal performance (or margin) among the candidate groups, and the identified candidate group may be lane group determined in operation S70. In some embodiments, the first device21may determine the lane group based on a valid window margin as the result of the training, and an example of operation S70will be described later with reference toFIG.8.

The first device21and the second device22may form the lane group in operation S80. For example, the first device21may form the internal paths including the pins corresponding to the lane group determined in operation S70, and may provide information about the lane group to the second device22, and the second device22may form the internal paths including the pins corresponding to the lane group based on the information provided by the first device21. Herein, that the first device21provides information about the lane group to the second device22may be referred to as configuring the second device22so that the lane group is used for the physical interface.

The first device21and the second device22may communicate with each other via the lane group in operation S90. Due to the lane group providing the optimal margin, the communication between the first device21and the second device22may be less sensitive to various factors, and may stably use a high bandwidth provided by the physical interface.

FIGS.3A and3Bare timing diagrams illustrating examples of training the physical interface, according to at least some example embodiments of the inventive concepts. The timing diagrams ofFIGS.3A and3Bmay represent examples of the training performed by a memory interface as an example of the physical interface. Training of a memory interface may include an address (or a command) training and a data training, the timing diagram ofFIG.3Amay represent an example of the address training, and the timing diagram ofFIG.3Bmay represent an example of the data training. In the descriptions with reference toFIGS.3A and3Bbelow, it is assumed that the second device12inFIG.1is a memory device, and the first device11is a device that communicates with the memory device and a host between the memory device and the host, and duplicate descriptions thereof will be omitted. The memory device may include a volatile memory such as static random access memory (RAM) (SRAM) or dynamic RAM (DRAM), and a non-volatile memory such as a flash memory and resistive RAM (RRAM).

Referring toFIG.3A, the first device11may provide a clock signal CK, an address signal ADDR, and a command signal CMD to the second device12. In some embodiments, the address signal ADDR and the command signal CMD may be provided by the first device11to the second device12via the same lanes. The memory interface may define that the address signal ADDR and the command signal CMD are latched at each of a rising edge and a falling edge of the clock signal CK, and accordingly, as illustrated inFIG.3A, the address signal ADDR and the command signal CMD may be required to be maintained constant before and after the rising edge and the falling edge of the clock signal CK. As illustrated inFIG.3A, an interval in which the address signal ADDR and the command signal CMD are maintained constant before and after the rising and falling edges of the clock signal CK may be referred to as the valid window margin VWM, and the valid window margin VWM may include a first interval VWML before an edge of the clock signal CK (may be referred to as a setup time) and a second interval VWMR after an edge of the clock signal CK (referred to as a hold interval). When the address signal ADDR and/or the command signal CMD are transmitted in parallel as a multi-bit signal via a plurality of lanes, the valid window margin VWM of the address signal ADDR and/or the command signal CMD may correspond to a minimum valid window margin among a plurality of valid window margins VWMs corresponding to the plurality of lanes.

The physical interface may require the valid window margin VWM (or the minimum first interval VWML and the minimum second interval VWMR) equal to or greater than a threshold value. In some embodiments, the first device11and the second device12may perform an address training, so that the edges of the clock signal CK are located at the centers of the valid window margin VWM. As the valid window margin VWM becomes larger, the second device12may more easily latch the address signal ADDR and the command signal CMD, and accordingly, an error that occurs when the address signal ADDR and the command signal CMD are received may be reduced.

Referring toFIG.3B, during a write operation, the first device11may provide a data strobe signal DQS, a data signal DQ, a data mask signal DM, and a data bus inversion signal DBI to the second device12. In addition, during a read operation, the second device12may provide the data strobe signal DQS, the data signal DQ, the data mask signal DM, and the data bus inversion signal DBI to the first device11. Accordingly, the data training may include a training for a write path and a training for a read path. In some embodiments, the pins of the first device11and the second device12connected to the interconnections, via which the data strobe signal DQS, the data signal DQ, the data mask signal DM, and the data bus inversion signal DBI pass, may be bi-directional pins.

The memory interface may define that the data signal DQ, the data mask signal DM, and the data bus inversion signal DBI are latched at each of the rising and falling edges of the data strobe signal DQS. Accordingly, as illustrated inFIG.3B, the data signal DQ, the data mask signal DM, and the data bus inversion signal DBI may be required to be maintained constant during the valid window margin VWM including the first interval VWML and the second interval VWMR. The physical interface may require the valid window margin VWM (or the minimum first interval VWML and the minimum second interval VWMR) equal to or greater than a threshold value. In some embodiments, the first device11and the second device12may perform the data training, so that the edge of the data strobe signal DQS is at the center of the valid window margin VWM. As the valid window margin VWM is increased, the first device11and the second device12may more easily latch the data signal DQ, the data mask signal DM, and the data bus inversion signal DBI, and errors that occurs when the data signal DQ, the data mask signal DM, and the data bus inversion signal DBI are received may be reduced.

As described below with reference to drawings, lanes providing the best valid window margin VWM may be determined by training a physical interface. Accordingly, a device-to-device physical interface that is less sensitive from various factors while providing a high bandwidth may be achieved.

FIGS.4A and4Bare block diagrams illustrating examples of training a physical interface, according to at least some example embodiments of the inventive concepts. Each of the block diagrams ofFIGS.4A and4Bmay represent a training performed on different candidate groups of the lanes.

Referring toFIG.4A, a first device41amay be connected to a second device42avia first through ninth interconnections INT1through INT9, and accordingly, nine lanes may be formed between the first device41aand the second device42a. The first device41aand the second device42amay mutually transceive the data signal DQ having 8 bits via eight lanes. The first device41amay include a first routing circuit41_2aand nine first pins P11through P19, and the second device42amay include a second routing circuit42_2aand nine second pins P21through P29. The nine first pins P11through P19may be connected to the first through ninth interconnections INT1through INT9, respectively, and the nine second pins P21through P29may be connected to the first through ninth interconnections INT1through INT9, respectively.

Eight lanes corresponding to the first through eighth interconnections INT1through INT8among the nine lanes may be selected as a candidate group (for example, a first candidate group). To this end, the first routing circuit41_2amay form internal paths, so that the data signal DQ is transmitted or received via the eight first pins P11through P18respectively connected to the first through eighth interconnections INT1through INT8. In addition, the second routing circuit42_2amay form internal paths, so that the data signal DQ is transmitted or received via the eight second pins P21through P28respectively connected to the first through eighth interconnections INT1through INT8.

As illustrated inFIG.4A, the first routing circuit41_2amay include eight first unit circuits U11through U18respectively corresponding to first through eighth data signals DQ1through DQ8of the data signal DQ. As illustrated by solid lines inFIG.4A, the eight first unit circuits U11through U18may output the data signal DQ to the first pins P11through P18, or may receive the data signal DQ from the first pins P11through P18. Similarly, the second routing circuit42_2amay include eight second unit circuits U21through U28respectively corresponding to the first through eighth data signals DQ1through DQ8of the data signal DQ, and the eight second unit circuits U21through U28may output the data signal DQ to the eight second pins P21through P28or receive the data signal DQ from the eight second pins P21through P28, respectively. Accordingly, the ninth interconnection ING9may not be used, and the first pin P19and the second pin P29connected to the ninth interconnection INT9may not be used.

Referring toFIG.4B, a first device41bmay be connected to a second device42bvia the first through ninth interconnections INT1through INT9, and accordingly, nine lanes may be formed between the first device41band the second device42b. The first device41band the second device42bmay mutually transceive the data signal DQ having 8 bits via eight lanes. The first device41bmay include a first routing circuit41_2band nine first pins P11through P19, and the second device42bmay include a second routing circuit42_2band nine second pins P21through P29. The nine first pins P11through P19may be connected to the first through ninth interconnections INT1through INT9, respectively, and the nine second pins P21through P29may be connected to the first through ninth interconnections INT1through INT9, respectively.

Eight lanes corresponding to the first through fourth interconnections INT1through INT4and the sixth through ninth interconnections INT6through INT9among the nine lanes may be selected as a candidate group (for example, a second candidate group). To this end, the first routing circuit41_2bmay form paths so that the data signal DQ is either transmitted or received via the eight first pins P11through P14and P16through P19respectively connected to the first through fourth interconnections INT1through INT4and the sixth through ninth interconnections INT6through INT9. In addition, the second routing circuit42_2bmay form paths so that the data signal DQ is transmitted or received via the eight second pins P21through P24and P26through P29respectively connected to the first through fourth interconnections INT1through INT4and the sixth through ninth interconnections INT6through INT9.

As illustrated inFIG.4B, the first routing circuit41_2bmay include eight first unit circuits U11through U18respectively corresponding to the first through eighth data signals DQ1through DQ8of the data signal DQ. As illustrated by solid lines inFIG.4B, the eight first unit circuits U11through U18may output the data signal DQ to the eight first pins P11through P14and P16through P19, or may receive the data signal DQ from the eight first pins P11through P14and P16through P19. Similarly, the second routing circuit42_2bmay include eight second unit circuits U21through U28respectively corresponding to the first through eighth data signals DQ1through DQ8of the data signal DQ, and the eight second unit circuits U21through U28may output the data signal DQ to the eight second pins P21through P24and P26through P29, respectively, or receive the first through eighth data signals DQ1through DQ8from the eight second pins P21through P24and P26through P29, respectively. Accordingly, the fifth interconnection INT5may not be used, and the first pin P15and the second pin P25connected to the fifth interconnection INT5may not be used.

FIG.5is a graph of a training result of a physical interface, according to at least one example embodiment of the inventive concepts. In the graph ofFIG.5, the dashed line may represent the training result ofFIG.4A, and the solid line may represent the training result ofFIG.4B. Hereinafter,FIG.5will be described with reference toFIGS.4A and4B.

As described above with reference toFIG.4A, the training may be performed by using the first through eighth interconnections INT1through INT8, and accordingly, as illustrated by the dashed line inFIG.5, eight valid window margins VWM respectively corresponding to the first through eighth data signals DQ1through DQ8. As illustrated inFIG.5, a first valid window margin VWM1of the fifth data signal DQ5among eight valid window margins may be identified as the minimum valid window margin, and the first valid window margin VWM1may be determined as the valid window margin of the physical interface using the first candidate group of the interconnections, that is, the first through eighth interconnections INT1through INT8.

In some embodiments, for a subsequent training, the candidate group may be selected among the interconnections except for the interconnections corresponding to the minimum valid window margin. For example, when a training result such as indicated by the dashed line inFIG.5occurs, the interconnections except for the interconnection corresponding to the fifth data signal DQ5, that is, the first through fourth interconnections INT1through INT4and the sixth through ninth interconnections INT6through INT9excluding the fifth interconnection INT5, may be selected as the second candidate group. Accordingly, as described above with reference toFIG.4B, a training may be performed by using the first through fourth interconnections INT1through INT4and the sixth through ninth interconnections INT6through INT9, and as illustrated by the dashed line inFIG.5, eight the valid window margins respectively corresponding to the eight of the first through eighth data signals DQ1through DQ8of data signal DQ may be obtained. As illustrated by arrows inFIG.5, the valid window margins corresponding to the fifth through seventh data signals DQ5through DQ7may correspond to the valid window margins corresponding to the sixth through eighth data signals DQ6through DQ8in the previous training. As illustrated inFIG.5, a second valid window margin VWM2of the sixth data signal DQ6among eight valid window margins may be identified as the minimum valid window margin, and the second valid window margin VWM2may be determined as the valid window margin of the physical interface using the second candidate group of the interconnections, that is, the first through fourth interconnections INT1through INT4and sixth through ninth interconnections INT6through INT9.

As illustrated inFIG.5, the second valid window margin VWM2may be greater than the first valid window margin VWM1, and accordingly, the second candidate group including the first through fourth interconnections INT1through INT4and the sixth through ninth interconnections INT6through INT9may be determined as the interconnection group for the physical interface.

FIG.6is a block diagram of an apparatus60according to at least one example embodiment of the inventive concepts. The block diagram ofFIG.6illustrates a portion for adjusting a path for transmission/reception of the third data signal DQ3in the apparatus60. As described above with reference toFIG.1, a routing circuit62may receive a control signal CTR, and form a path for transceiving the third data signal DQ3according to the control signal CTR. As illustrated inFIG.6, the apparatus60may include the routing circuit62, input/output (I/O) buffers63, and a third pin P3and a fourth pin P4, and the third data signal DQ3may include a third data output signal DQ3_OUT and a third data input signal DQ3_IN.

The routing circuit62may include a decoder62_4and a plurality of multiplexers. The decoder62_4may receive the control signal CTR, and may generate a plurality of select signals for controlling the plurality of multiplexers by decoding the control signal CTR. For example, as illustrated inFIG.6, the routing circuit62may include a first multiplexer62_1and a third multiplexer62_3for receiving the third data output signal DQ3_OUT, and may include a second multiplexer62_2outputting the third data input signal DQ3_IN. The first multiplexer62_1may provide one of a second data output signal DQ2_OUT and the third data output signal DQ3_OUT to a first output buffer63_1, based on a third select signal C3provided by the decoder62_4. The second multiplexer62_2may output a signal output from one of a first input buffer63_2and a second input buffer63_4as the third data input signal DQ3_IN, based on the third select signal C3from the decoder62_4. Accordingly, when the third select signal C3is deactivated (for example, has a low level), the third data output signal DQ3_OUT may be output by sequentially passing through the first multiplexer62_1, the first output buffer63_1, and the third pin P3, and a signal input via the third pin P3may be received as the third data input signal DQ3_IN via the first input buffer63_2and the second multiplexer62_2. On the other hand, when the third select signal C3is activated (for example, has a high level), the third data output signal DQ3_OUT may be output by sequentially passing through the third multiplexer62_3, a second output buffer63_3, and the fourth pin P4, and a signal input via the fourth pin P4may be received as the third data input signal DQ3_IN via the second input buffer63_4and the second multiplexer62_2. In addition, the third multiplexer62_3may provide one of the third data output signal DQ3_OUT and a fourth data output signal DQ4_OUT to the second output buffer63_3, based on a fourth select signal C4provided by the decoder62_4.

FIG.7is a flowchart of a method of training a physical interface, according to at least one example embodiment of the inventive concepts. The flowchart ofFIG.7illustrates examples of operations S30and S40inFIG.2. As described above with reference toFIG.2, the first training of the physical interface may be performed in operation S30′ ofFIG.7, and the second candidate group among the valid lanes may be selected in operation S40′ ofFIG.7. As illustrated inFIG.7, operation S30′ may include operation S35, and operation S40′ may include operation S41and operation S42. Hereinafter,FIG.7will be described with reference toFIG.2.

Referring toFIG.7, a plurality of first valid window margins may be detected in operation S35. For example, the first device21may detect the plurality of first valid window margins respectively corresponding to a plurality of lanes included in the first candidate group as the result of the first training. As described above with reference toFIG.5, the minimum first valid window margin VWM1among the plurality of first valid window margins may be determined as the valid window margin of the physical interface using the first candidate group.

A lane corresponding to the minimum first valid window margin VWM1may be identified in operation S41. For example, the first device21may identify the minimum first valid window margin VWM1among the plurality of first valid window margins detected in operation S35, and identify a lane corresponding to the minimum first valid window margin VWM1. Accordingly, as described above with reference toFIGS.4A and5, a lane including the fifth interconnection INT5may be identified.

The second candidate group may be selected from lanes except for the identified lane in operation S42. For example, the first device21may select the second candidate group among the valid lanes except for the lane identified in operation S41. Accordingly, as described above with reference toFIGS.4B and5, the lane including the fifth interconnection INT5may be excluded, and the second candidate group including the lanes respectively including the first through fourth interconnections INT1through INT4and the sixth through ninth interconnections INT6through INT9may be selected.

FIG.8is a flowchart of a method of training a physical interface, according to at least one example embodiment of the inventive concepts. The flowchart ofFIG.8may illustrate examples of operations S50and S70inFIG.2. As described above with reference toFIG.2, the second training of the physical interface may be performed in operation S50′ ofFIG.8, and the lane group including the lanes to be used at the physical interface may be determined in operation S70′ ofFIG.8. As illustrated inFIG.8, operation S50′ may include operation S55, and operation S70′ may include a plurality of operations S71through S74.

The plurality of second valid window margins may be detected in operation S55. For example, the first device21may detect a plurality of second valid window margins respectively corresponding to a plurality of lanes included in the second candidate group as the result of the second training. As described above with reference toFIG.5, a minimum second valid window margin VWM2among the plurality of second valid window margins may be determined as the valid window margin of the physical interface using the second candidate group.

A lane corresponding to the minimum second valid window margin VWM2may be identified in operation S71. For example, the first device21may identify the minimum second valid window margin VWM2among the plurality of second valid window margins detected in operation S55, and identify a lane corresponding to the minimum second valid window margin VWM2. Accordingly, as described above with reference toFIGS.4B and5, a lane including the sixth interconnection INT6may be identified.

The minimum first valid window margin VWM1may be compared to the minimum second valid window margin VWM2in operation S72. As illustrated inFIG.8, when the minimum first valid window margin VWM1is greater than the minimum second valid window margin VWM2, the first candidate group may be determined as the lane group in operation S73. On the other hand, when the minimum first valid window margin VWM1is not greater than the minimum second valid window margin VWM2, the second candidate group may be determined as the lane group in operation S74. As a result, the first device21may identify a higher valid window margin among the minimum first valid window margin VWM1and the minimum second valid window margin VWM2, and identify, as a lane group, a candidate group corresponding to the valid window margin that has been identified among the first candidate group and the second candidate group in operation S70′.

FIGS.9A and9Bare block diagrams of examples of apparatuses, according to at least some example embodiments of the inventive concepts. Compared to the devices ofFIGS.4A and4B, devices90aand90bofFIGS.9A and9B, respectively, may transceive the data signal DQ as well as additional signals. In some embodiments, the data signal DQ and other signals may be mapped to the plurality of pins differently from as illustrated inFIGS.9A and9B. The signals illustrated together with the data signal DQ inFIGS.9A and9Bare only examples, and unused pins corresponding to signals different from the signals illustrated inFIGS.9A and9Bmay be used for better valid window margins. Hereinafter, duplicate descriptions to be given with reference toFIGS.9A and9Bare omitted.

Referring toFIG.9A, the device90amay include a routing circuit92aand a plurality of pins P00through P10. The device90amay transceive the data signal DQ as well as the data mask signal DM and the data bus inversion signal DBI. The data mask signal DM may indicate whether at least a portion of the data signal DQ is masked. For example, when the activated data mask signal DM is received together with the data signal DQ, the device90amay ignore lower 4 bits, that is, the first through fourth digital signals DQ1through DQ4of the first through eighth data signals DQ1through DQ8of the data signal DQ. In this manner, masking at least a portion of the data signal DQ by using the data mask signal DM may be referred to as a data masking function, and the physical interface may support the data masking function.

The data bus inversion signal DBI may indicate whether the data signal DQ is inverted. For example, when an activated data bus inversion signal DBI is received together with the data signal DQ, the device90amay invert the data signal DQ, and extract information from the inverted data signal DQ. Due to the data bus inversion signal DBI, transitions of the signals at the interconnections may decrease or the number of signals having a high level may decrease, and accordingly, power consumed for communication may decrease. In this manner, selectively inverting the data signal DQ by using the data bus inversion signal DBI may be referred to as a data bus inversion function, and the physical interface may support the data bus inversion function.

The data masking function and/or the data bus inversion function may be disabled in the device90a. In some embodiments, the device90aand another device in communication with the device90amay be preset, so that the data masking function and/or data bus inversion function are not used. Accordingly, when the data masking function and/or the data bus inversion function are not used, the data mask signal DM and/or the data bus inversion signal DBI may also not be used, and the number of available lanes for transceiving the data signal DQ may increase.

As illustrated inFIG.9A, the routing circuit92amay include ten of unit circuits U01through U10respectively corresponding to the data mask signal DM, the data signal DQ having 8 bits, and the data bus inversion signal DBI, and may include eleven of pins P00through P10. In some embodiments, when the data masking function is deactivated, ten of pins P01through P10of the eleven of pins P00through P10may be used for the data signal DQ having 8 bits and the data bus inversion signal DBI, and accordingly, ten different candidate groups may be available and ten trainings respectively corresponding to the ten different candidate groups may be performed. Similarly, in some embodiments, when the data masking function is deactivated, ten of pins P00through P09of the eleven of pins P00through P10may be used for the data signal DQ having 8 bits and the data mask signal DM, and accordingly, ten different candidate groups may be available and ten trainings respectively corresponding to the ten different candidate groups may be performed. In addition, in some embodiments, when the data masking function and the data bus conversion function are all deactivated, nine of pins P01through P09of the eleven of pins P00through P11may be used for the data signal DQ having 8 bits, and accordingly, nine different candidate groups may be available and nine trainings respectively corresponding to the nine different candidate groups may be performed. In this manner, a candidate group including pins that are not used as a result of the function being in a deactivated state may be selected.

Referring toFIG.9B, the device90bmay include a routing circuit92band the plurality of pins P00through P10. The device90bmay transmit or receive the data signal DQ as well as the data bus inversion signal DBI, a severity signal SEV, and an error correction code signal ECC. In some embodiments, unlike as illustrated inFIG.9B, the severity signal SEV and the error correction code signal ECC may be arranged for each data signal having 16 bits.

The severity signal SEV and the error correction code signal ECC may be used for the error correction code (or on-die) of data transceived via the data signal DQ. The data bus inversion function as well as the error correction function may be at least partially disabled in the device90b. In some embodiments, the device90band another device in communication with the device90bmay be preset, so that at least a portion of the error correction function is not used. Accordingly, when at least a portion of the error correction function is not used, the severity signal SEV and/or the error correction code signal ECC may also not be used, and the number of available lanes for transmission and reception of the data signal DQ may increase.

As illustrated inFIG.9B, the routing circuit92bmay include eleven of unit circuits U01through U11respectively corresponding to the severity signal SEV, the error correction code signal ECC, the data signal DQ having 8 bits, and the data bus inversion signal DBI, and may include twelve of pins P00through P11. When at least one of functions respectively corresponding to the data bus inversion signal DBI, the severity signal SEV, and/or the error correction code signal ECC is deactivated, only some of the twelve of pins P00through P11may be required, and accordingly, different candidate groups may be available, and trainings corresponding to the related candidate groups may be performed. As described above with reference toFIG.9A, a candidate group including pins that are not used due to the deactivated function may be selected.

FIG.10is a flowchart of a method of training a physical interface, according to at least one example embodiment of the inventive concepts. The flowchart ofFIG.10may illustrate an example of operation S42inFIG.7. As described above with reference toFIG.7, after the first training is completed, the second candidate group may be selected in operation S42′ ofFIG.10. As illustrated inFIG.10, operation S42′ may include operations S42_1and S42_2, and hereinafter,FIG.10will be described with reference toFIGS.7and9A.

Referring toFIG.10, whether at least one function is deactivated may be determined in operation S42_1. For example, each of the first device11and the second device12inFIG.1may include a mode register that stores whether functions supported by the physical interface are activated. The first controller11_1may access the mode register, and may determine whether at least one function is deactivated based on a value stored in the mode register. As illustrated inFIG.10, when at least one function is deactivated, operation S42_2may be subsequently performed.

The second candidate group including unused pins may be selected in operation S42_2. For example, the first controller11_1inFIG.1may identify at least one deactivated function, and identify at least one pin corresponding to the at least one identified function, that is, at least one unused pin. The first controller11_1may select the second candidate group including at least one unused pin instead of at least one pin included in the first candidate group which is used in the previous training (that is, the first training).

FIG.11is a block diagram of a device110according to at least one example embodiment of the inventive concepts. The block diagram ofFIG.11illustrates an example of a device (for example, 12 inFIG.1) that sets the candidate group of the lanes, and communicates with a device (for example, 11 inFIG.1) that finally determines the lane group. As illustrated inFIG.11, the device110may include a controller111, a routing circuit112, a first register113, and a second register114. Hereinafter, it is assumed that the device110ofFIG.11communicates with the first device11inFIG.1.

As described above with reference to the drawings, the routing circuit112may form paths based on the control signal CTR. Accordingly, the routing circuit112may map logical paths LP to physical paths PP based on the control signal CTR. As illustrated inFIG.11, the control signal CTR may be provided by the second register114.

The controller111may receive an instruction INS from the first device11(or the first controller11_1), and may generate a hard control signal CTR_H or a soft control signal CTR_S based on the instruction INS. The instruction INS received from the first device11may include a soft mapping command for temporarily mapping the logical paths LP to the physical paths PP and a hard mapping command for permanently mapping the logical paths LP to the physical paths PP. The controller111may provide the hard control signal CTR_H to the first register113based on the hard mapping command, and the soft control signal CTR_S to the second register114based on the soft mapping command.

The first register113may, in a non-volatile manner, store a value corresponding to the hard control signal CTR_H provided by the controller111, and may provide the stored value corresponding to hard control signal CTR_H to the second register114. The second register114may store one of a value corresponding to the hard control signal CTR_H provided by the first register113and a value corresponding to the soft control signal CTR_S provided by the controller111, and may provide the stored control signal CTR corresponding to the store value to the routing circuit112. In some embodiments, the second register114may be referred to as a shadow register. An example of a method of setting the candidate group used for the training and a finally determined lane group, by using the first register113and the second register114will be described later with reference toFIG.12. In some embodiments, the first register113and the second register114may be used for the lane repair.

FIG.12is a flowchart of a method of training a physical interface, according to at least one example embodiment of the inventive concepts. The flowchart ofFIG.12illustrates examples of operations S30, S50, and S80inFIG.2. As described above with reference toFIG.2, the first training may be performed in operation S30″ ofFIG.12, the second training may be performed in operation S50″ ofFIG.12, and the lane group may be formed in operation S80″ ofFIG.12. As illustrated inFIG.12, operation S30″ may include operations S31and S32, operation S50″ may include operations S51and S51, and operation S80″ may include operations S81and S82. Hereinafter,FIG.12will be described with reference toFIG.11, and a second device122inFIG.12may include the controller111, the routing circuit112, the first register113, and the second register114.

Referring toFIG.12, a first device121may transmit a first soft mapping command to the second device122in operation S31. For example, the first device121may select the first candidate group for the first training, and may transmit the first soft mapping command to the second device122as information about the selected first candidate group.

The second device122may temporarily set the first candidate group in operation S32. For example, the controller111included in the second device122may provide the soft control signal CTR_S for setting the first candidate group to the second register114in response to the first soft mapping command, and the second register114may provide the control signal CTR corresponding to the soft control signal CTR_S to the routing circuit112. Accordingly, the first training using the first candidate group may be performed.

The first device121may transmit a second soft mapping command to the second device122in operation S51. For example, the first device121may select the second candidate group for the second training, and may transmit the second soft mapping command to the second device122as information about the selected second candidate group.

The second device122may temporarily set the second candidate group in operation S52. For example, the controller111included in the second device122may provide the soft control signal CTR_S for setting the second candidate group to the second register114in response to the second soft mapping command, and the second register114may provide the control signal CTR corresponding to the soft control signal CTR_S to the routing circuit112. Accordingly, the second training using the second candidate group may be performed.

The first device121may transmit the hard mapping command to the second device122in operation S81. For example, the first device121may finally determine the lane group based on the training results, and may transmit the hard mapping command to the second device122as information about the determined lane group.

The second device122may permanently set the lane group in operation S82. For example, the controller111included in the second device122may provide the hard control signal CTR_H for setting the lane group to the first register113in response to the hard mapping command, and the first register113may store the hard control signal CTR_H in a non-volatile manner. When the controller111does not provide the soft control signal CTR_S to the second register114, the second register114may provide the control signal CTR corresponding to the hard control signal CTR_H provided by the first register113to the routing circuit112. Accordingly, the first device121and the second device122may communicate with each other based on the physical interface by using the determined lane group.

FIG.13is a diagram of a system130according to at least one example embodiment of the inventive concepts. As illustrated inFIG.13, the system130may include a high bandwidth memory (HBM)132and an HBM physical layer (PHY) (HBM_PHY)131communicating with the HBM132, and may be referred to as a memory system, a memory module, or the like. The HBM_PHY131and the HBM132may communicate with each other based on an HBM interface as the physical interface, and may perform a training of the HBM interface as described above with reference to the drawings.

Referring toFIG.13, the HBM_PHY131may include an institute of electrical and electronics engineers (IEEE)1500controller131_0and first through nthchannels131_1through131_n(n is an integer greater than1). The first through nthchannels131_1through131_nmay communicate with the HBM132independently of each other, and to this end, the HBM132may also include first through nthchannels132_1through132_n. As illustrated inFIG.13, each of the first through nth channels131_1through131_nmay receive data from a host (or a memory controller) via an advanced peripheral bus (APB) or transmit data to the host. In addition, each of the first through nthchannels131_1through131_nmay communicate with a channel corresponding to the HBM132via a first sub-channel (AWORD) for transmission of commands and/or addresses, and a second sub-channel (DWORD) for transmission and reception of data. An example of the first through nthchannels131_1through131_nwill be described later with reference toFIG.14.

The IEEE1500controller131_0may provide a direct connection between the host and the HBM132. As illustrated inFIG.13, the IEEE1500controller131_0may receive data from or transmit data to the host via an advanced peripheral bus (APB), and the IEEE1500controller131_0may communicate with the HBM132via independent channels WS1through WSn. In some embodiments, the IEEE1500controller131_0may provide information to the HBM132for setting the HBM132when training the first sub-channel (AWORD) of the first through nthchannels131_1through131_nis performed, and may receive information about signals received via the first through nthchannels132_1through132_n, that is, a feedback of the training from the HBM132. For example, as described above with reference to the drawings, the IEEE1500controller131_0may control the training by using each of different candidate groups for the first sub-channel (AWORD), and may determine the lane group for the first sub-channel (AWORD) based on the training results.

The HBM132may include a plurality of memory dies that are stacked, and via the first through nth channels132_1through132_n, data may be written to the plurality of memory dies in parallel or data may be read from the plurality of memory dies in parallel. In some embodiments, the HBM132may include a plurality of DRAM dies, and may be referred to as HBM DRAM. An example of a structure of the HBM132will be described later with reference toFIG.15.

FIG.14is a block diagram of a channel140according to at least one example embodiment of the inventive concepts. As described above with reference toFIG.13, the HBM_PHY131may include a plurality of channels, and the plurality of channels may communicate with the HBM132independently of each other. As illustrated inFIG.14, a channel140may include an AWORD control logic141, a control slice142, a DWORD control logic143, a plurality of data slices144, and input/output (I/O) buffers145.

The AWORD control logic141may communicate with the host, and control the control slice142. For example, the AWORD control logic141may provide a command and/or an address to the control slice142in response to the command (for example, a write command and a read command) and/or the address, which are received from the host via the APB and/or the double data rate (DDR) physical interface (DFI). In addition, the AWORD control logic141may generate a test pattern when training the first sub-channel AWORD is performed, and may adjust the timing of signals output via the first sub-channel AWORD by controlling a plurality of delay locked loops (DLLs)142_1included in the control slice142inFIG.14.

The control slice142may include the plurality of DLLs142_1and an input/output (I/O) control block142_2. The plurality of DLLs142_1may provide signals delayed according to the control of the AWORD control logic141, such as a command signal and/or an address signal, to the I/O control block142_2. The I/O control block142_2may provide, to the I/O buffers145, the command signal and/or the address signal received from the plurality of DLLs142_1via paths formed according to the control of the AWORD control logic141(or131_0inFIG.13). In other words, the I/O control block142_2may perform the function of the routing circuits described above with reference to the drawings.

The DWORD control logic143may communicate with the host, and control the plurality of data slices144. For example, the DWORD control logic143may provide data to the plurality of data slices144in response to data received from the host via the APB and/or DFI. The DWORD control logic143may generate a test pattern when training a write path of the second sub-channel DWORD is performed, and may adjust timing of signals output via the second sub-channel DWORD by controlling a plurality of first DLLs144_1included in each of the data slices144inFIG.14. In addition, the DWORD control logic143may provide data received from the plurality of data slices144to the host via the APB and/or DFI. The DWORD control logic143may control the timing of signals received via the second sub-channel DWORD by controlling a plurality of second DLLs144_2when training the read path of the second sub-channel DWORD is performed.

Each of the plurality of data slices144may include the plurality of first DLLs144_1, the plurality of second DLLs144_2, and an input/output (I/O) control block144_3. The plurality of first DLLs144_1may provide signals delayed according to the control of the DWORD control logic143, for example, data signals, to the I/O control block144_3. The I/O control block144_3may provide a data signal received from the plurality of first DLLs144_1via paths formed according to the control of the DWORD control logic143, to the I/O buffer145. In addition, the plurality of second DLLs144_2may provide signals delayed according to the control of the DWORD control logic143, for example, data signals, to the DWORD control logic143. The I/O control block144_3may provide a data signal received from the input/output (I/O) buffers145via paths formed according to the control of the DWORD control logic143, to the plurality of second DLLs144_2. Accordingly, the I/O control block144_3may perform the function of the routing circuits described above with reference to the drawings.

FIG.15is a diagram of a cross-sectional view of a system150according to at least one example embodiment of the inventive concepts. As illustrated inFIG.15, the system150may include an HBM device151, a processing circuit152, an interposer153, and a printed circuit board (PCB)154.

The HBM device151may include first through fourth memory dies MD1through MD4and a base die BD, and may be referred to as an HBM system. As illustrated inFIG.15, the first through fourth memory dies MD1through MD4may be stacked on the base die BD, and micro-bumps MB may be arranged between the first through fourth memory dies MD1through MD4and the base die BD. The micro-bumps MB may be connected to through silicon vias TSV penetrating each of the first through fourth memory dies MD1through MD4. The base die BD may be arranged on the interposer153, and first bumps B1may be arranged between the base die BD and the interposer153. An address signal, a command signal, and a data signal for accessing the first through fourth memory dies MD1through MD4may pass through the first bumps B1. In some embodiments, the first through fourth memory dies MD1through MD4may be collectively referred to as the HBM, and the HBM_PHY described above with reference toFIGS.13and14may be included in the base die BD. The HBM_PHY and the first through fourth memory dies MD1through MD4may perform a training by using each of different candidate groups of lanes based on the HBM interface, and may determine the lane group. Accordingly, some of a plurality of through silicon vias TSV and some of the plurality of micro-bumps MB, which provide an optimum margin, may be used for the HBM interface.

The processing circuit152may be arranged on the interposer153, and second bumps B2may be arranged between the processing circuit152and the interposer153. The processing circuit152may communicate with the base die BD via some of the second bumps B2, patterns formed on the interposer153, and some of the first bumps B1, and may write data to the HBM device151or may read data from the HBM device151. For example, the processing circuit152may include a central processing unit (CPU), a graphic processing unit (GPU), a neural processing unit (NPU), or the like.

The interposer153may be arranged on the PCB154, and third bumps B3may be arranged between the interposer153and the PCB154. In some embodiments, the third bumps B3may include flip die bumps. The interposer153may include a plurality of patterns for interconnecting the HBM device151to the processing circuit152. Fourth bumps B4may be arranged on a lower surface of the PCB154, and the system150may communicate with the outside via the fourth bumps B4.

FIG.16is a diagram of a cross-sectional view of a system160according to at least one example embodiment of the inventive concepts. As illustrated inFIG.16, the system160may include a PCB161, a connector162, a discrete device163, a power management integrated circuit (PMIC)164, a control module165, and memory devices166. In some embodiments, the connector162is a part of the PCB161. In some embodiments, the connector162, the discrete device163, the PMIC164, the control module165, and the memory devices166may be mounted on the PCB161.

The connector162may be connected to a device outside the system160. For example, the system160may be a memory system which stores data in the memory devices166or provides the stored data to the outside of the system160via the connector162, in response to a signal provided via the connector162. In some embodiments, the system160may include a solid state drive (SSD), and the connector162may have, as a non-limiting example, a structure defined by M.2 SSD and mini seral advanced technology attachment (mSATA) SSD. The memory devices166may store data under the control of the control module165to be described later. For example, the memory devices166may include at least one non-volatile memory device such as a flash memory and RRAM.

The discrete device163may provide a function for electrical characteristics required by the system160. For example, the discrete device163may include a capacitor so that power provided via the connector162is stably provided to components included in the system160. In addition, in some embodiments, the discrete device163may include a resistor and/or an inductor. The PMIC165may manage power provided to components of the system160. For example, the PMIC165may receive a supply voltage via the connector162, generate at least one supply voltage from the received supply voltage, and provide the generated at least one supply voltage to the components of the system160.

The control module165may control the memory devices166in response to the signal received via the connector162or for itself. As illustrated inFIG.16, the control module165may include a first interposer165_1, a second interposer165_2, a controller165_3, and a buffer165_4. The controller165_3may read data from the memory devices166or write data to the memory devices166in response to a request received via the connector162. In some embodiments, the controller165_3may map logical addresses received via the connector162to physical addresses of the memory devices166.

The buffer165_4may be used by the controller165_3to control the memory devices166. For example, the buffer165_4may store data that is received via the connector162and will be written to the memory devices166, and may also store data that is read by the memory devices166and will be output via the connector162. In some embodiments, the buffer165_4may include a memory device (e.g., DRAM) having a faster operation speed than the memory devices166.

The controller165_3and the buffer165_4may be connected to patterns of the PCB161via the first interposer165_1. In addition, the controller165_3and the buffer165_4may be connected to each other via the second interposer165_2. In some embodiments, unlike as illustrated inFIG.16, the second interposer165_2may extend so that all of bottom surfaces of the controller165_3and the buffer165_4are disposed on the second interposer165_2. In some embodiments, the controller165_3may perform training by using each of different candidate groups of lanes between the controller165_3and the buffer165_4, and may determine a lane group. Thus, a portion of a plurality of lanes, which provide an optimum margin, may be used for an interface between the controller165_3and the buffer165_4.

Example embodiments of the inventive concepts having thus been described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the intended spirit and scope of example embodiments of the inventive concepts, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.