Patent ID: 12237042

DETAILED DESCRIPTION

It may be known from the Background that, the signal adjustment capability of an equalization circuit needs to be improved, and the power consumption of the equalization circuit needs to be reduced.

Embodiments of the disclosure provide a data receiving circuit, a data receiving system and a memory device. In the data receiving circuit, the second amplification circuit may be further controlled by means of an enable signal, so as to select whether to consider the impact of the intersymbol interference of data received by the data receiving circuit on the data receiving circuit. For example, when the impact of the intersymbol interference on the data receiving circuit is required to be reduced, the enable signal is set to be at a first level, the second amplification circuit selectively receives one of the first signal pair and the second signal pair that has a larger level difference based on the current enable signal and the feedback signal, so as to ensure that the second amplification circuit receives a pair of differential signals with a larger signal level difference. When the impact of the intersymbol interference on the data receiving circuit is not required to be considered, the enable signal is set to be at a second level, and the second amplification circuit keeps receiving the first signal pair based on the current enable signal, so as to achieve effects of reducing the power consumption of the data receiving circuit while improving the receiving performance of the data receiving circuit.

Embodiments of the disclosure are described in detail below with reference to the drawings. However, it is to be understood by those skilled in the art that, in each embodiment of the disclosure, many technical details are provided for readers to better understand the embodiments of the disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the disclosure may also be realized.

An embodiment of the disclosure provides a data receiving circuit. The data receiving circuit provided in this embodiment of the disclosure is described in detail below with reference to the drawings.FIG.1is a functional block diagram of a data receiving circuit according to an embodiment of the disclosure.FIG.3toFIG.4are another two functional block diagrams of a data receiving circuit according to an embodiment of the disclosure.FIG.5is a schematic diagram of a circuit structure of a first amplification circuit in a data receiving circuit according to an embodiment of the disclosure.FIG.6is a schematic diagram of a circuit structure of a second amplification circuit in a data receiving circuit according to an embodiment of the disclosure.

Referring toFIG.1andFIG.3, the data receiving circuit100includes: a first amplification circuit101and a second amplification circuit102. The first amplification circuit101is configured to receive a data signal DQ, a first reference signal VR+ and a second reference signal VR−, perform first comparison on the data signal DQ and the first reference signal VR+ in response to a sampling clock signal clkN, output a first signal pair as a result of the first comparison, perform second comparison on the data signal DQ and the second reference signal VR−, and output a second signal pair as a result of the second comparison, where a level of the first reference signal VR+ is different from a level of the second reference signal VR−, the first signal pair includes a first signal Sn+ and a second signal Sp+, and the second signal pair includes a third signal Sn− and a fourth signal Sp−. The second amplification circuit102is configured to receive an enable signal EnDfe and a feedback signal fb, selectively receive the first signal pair or the second signal pair as an input signal pair based on the feedback signal fb during a period in which the enable signal EnDfe is at the first level, receive the first signal pair as the input signal pair during a period in which the enable signal EnDfe is at the second level, amplify a voltage difference of the input signal pair, and output a first output signal Vout and a second output signal VoutN as an amplification result. The feedback signal fb is obtained based on previously received data.

It may be understood that, during a period in which the enable signal EnDfe is at the first level, based on different previously received feedback signals fb, the second amplification circuit102may selectively receive one of the first signal pair and the second signal pair that has a larger level difference based on the current feedback signal fb, to ensure that the second amplification circuit102receives a pair of differential signals with a larger signal level difference, so as to reduce the impact of intersymbol interference of the received data signal on the data receiving circuit100. It is to be noted that, the level of the first reference signal VR+ is different from the level of the second reference signal VR−. For data signals DQ with different levels, the data signal DQ may have a larger level difference from that of one of the first reference signal VR+ and the second reference signal VR−, so that the first amplification circuit101can amplify the level difference, resulting in that the signal level difference of at least one of the first signal pair and the second signal pair outputted by the first amplification circuit101is relatively large. Therefore, when there is an intersymbol interference phenomenon in the data signal DQ received by the data receiving circuit100, the second amplification circuit102may subsequently receive one of the first signal pair and the second signal pair, that has a larger level difference, based on the enable signal EnDfe and the feedback signal fb. It may be understood that, the data receiving circuit100may enhance the ability of the data receiving circuit100on adjusting the received data signal DQ by using the first reference signal VR+ and the second reference signal VR−. That is to say, when there is an intersymbol interference phenomenon in the data signal DQ received by the data receiving circuit100, the second amplification circuit102receives, based on the enable signal EnDfe and the feedback signal fb, a signal pair in the first amplification circuit101that better processes the data signal DQ. The signal pair that better processes the data signal DQ is one of the first signal pair and the second signal pair that has a larger level difference. Therefore, the purpose of reducing the impact of the intersymbol interference of the received data signal DQ on the data receiving circuit100can be realized.

In addition, the second amplification circuit102selectively receives the one of the first signal pair and the second signal pair that has a larger level difference based on the feedback signal fb, so as to guarantee that the second amplification circuit102receives a pair of differential signals with a larger signal level difference. Therefore, the accuracy of the first output signal Vout and the second output signal VoutN outputted by the second amplification circuit102can be enhanced. Therefore, through the cooperation of the first amplification circuit101and the second amplification circuit102, the receiving performance of the data receiving circuit100is improved.

In another aspect, during a period in which the enable signal EnDfe is at the second level, regardless of variance of the level of the previously received feedback signal fb, the second amplification circuit102keeps receiving the first signal pair based on the enable signal EnDfe. In this case, a circuit for outputting the second signal pair in the first amplification circuit101may be in a non-operating state, so that the power consumption of the data receiving circuit100can be reduced.

Based on the analysis, it may be learned that, the enable signal EnDfe may be used to determine whether to consider the impact of the intersymbol interference of data received by the data receiving circuit100on the data receiving circuit100, so as to implement further control of the second amplification circuit102, thereby achieving the effects of reducing the power consumption of the data receiving circuit100while improving the receiving performance of the data receiving circuit100. It is to be noted that, a situation in which the intersymbol interference needs to be considered generally refers to a situation in which the data signal DQ received by the data receiving circuit100is high-speed data, that is, a situation in which a data transfer rate is very fast. A situation in which the intersymbol interference does not need to be considered generally refers to a situation in which the data signal DQ received by the data receiving circuit100is low-speed data, that is, a situation in which the data transfer rate is relatively slow.

How the data receiving circuit100reduces the impact of the intersymbol interference of the received data signal DQ on the data receiving circuit100is described in detail below with reference to a specific example.

In some embodiments, the level of the first reference signal VR+ is higher than the level of the second reference signal VR−. If the data signal DQ is at a low level and there is an intersymbol interference phenomenon in the data signal DQ received by the data receiving circuit100, the enable signal EnDfe is set at the first level, and the second amplification circuit102receives the first signal pair based on the current enable signal EnDfe and the feedback signal fb. In this case, the level difference between the data signal DQ and the first reference signal VR+ is greater than the level difference between the data signal DQ and the second reference signal VR−, so that the level difference between the signals in the first signal pair outputted by the first amplification circuit101is greater than the level difference between the signals in the second signal pair. Therefore, the second amplification circuit102receives the first signal pair, which facilitates the outputting of the first output signal Vout and the second output signal VoutN that meet requirements, that is, the accuracy of the first output signal Vout and the second output signal VoutN is guaranteed. Therefore, the impact of the intersymbol interference of the received data signal DQ on the data receiving circuit100can be reduced.

In addition, if the data signal DQ is at a high level and there is an intersymbol interference phenomenon in the data signal DQ received by the data receiving circuit100, the enable signal EnDfe is set at the first level, the second amplification circuit102receives the second signal pair based on the current enable signal EnDfe and the feedback signal fb. In this case, the level difference between the data signal DQ and the first reference signal VR+ is less than the level difference between the data signal DQ and the second reference signal VR−, so that the level difference between the signals in the first signal pair outputted by the first amplification circuit101is less than the level difference between the signals in the second signal pair. Therefore, the second amplification circuit102receives the second signal pair, which facilitates the outputting of the first output signal Vout and the second output signal VoutN that meet requirements, that is, the accuracy of the first output signal Vout and the second output signal VoutN is guaranteed. Therefore, the impact of the intersymbol interference of the received data signal DQ on the data receiving circuit100can be reduced.

It may be understood that, during the period in which the enable signal EnDfe is at the first level, the second amplification circuit102selectively receives one of the first signal pair and the second signal pair that has a larger level difference based on the feedback signal fb with a varying level, to enhance the accuracy of the first output signal Vout and the second output signal VoutN outputted by the second amplification circuit102, so that the impact of the intersymbol interference of the received data signal DQ on the data receiving circuit100can be reduced.

In some embodiments, referring toFIG.3toFIG.5, the first amplification circuit101may further be configured to receive the enable signal EnDfe, perform the first comparison and the second comparison to respectively output the first signal pair and the second signal pair during a period in which the enable signal EnDfe is at the first level, and merely perform the first comparison to output the first signal pair during a period in which the enable signal EnDfe is at the second level. A level of the first reference signal VR+ is greater than a level of the second reference signal VR−.

It may be understood that, whether the second comparison is performed can be determined by using the enable signal EnDfe to further control the first amplification circuit101. For example, when the impact of the intersymbol interference on the data receiving circuit100is required to be reduced, the enable signal is set to be at the first level, and the first amplification circuit101performs the first comparison and the second comparison to output the first signal pair and the second signal pair respectively based on the current enable signal EnDfe. Then, the second amplification circuit102selectively receives one of the first signal pair and the second signal pair that has a larger level difference based on the enable signal EnDfe and the feedback signal fb, so as to ensure that the second amplification circuit receives a pair of differential signals with a larger signal level difference. When the impact of the intersymbol interference on the data receiving circuit100is not required to be considered, the enable signal EnDfe is set to be at the second level, and the first amplification circuit101only performs the first comparison based on the current enable signal EnDfe, to output the first signal pair having a difference in the level. Then, the second amplification circuit102keeps receiving the first signal pair based on the current enable signal EnDfe. In this case, the first amplification circuit101causes, based on the current enable signal EnDfe, the circuit for outputting the second signal pair to be in the non-operating state, so as to reduce the power consumption of the data receiving circuit100.

In addition, in other embodiments, the level of the first reference signal VR+ may also be less than the level of the second reference signal VR−.

In some embodiments, referring toFIG.3, the sampling clock signal clkN includes a first sampling clock signal clkN1and a second sampling clock signal clkN2. The first amplification circuit101may include: a first comparison circuit111, a clock generation circuit131, and a second comparison circuit121. The first comparison circuit111has a first node net1and a second node net2, and is configured to receive the data signal DQ and the first reference signal VR+, perform the first comparison in response to the first sampling clock signal clkN1, and output the first signal Sn+ and the second signal Sp+ through the first node net1and the second node net2respectively. The clock generation circuit131is configured to receive the enable signal EnDfe and an original sampling clock signal clk, and output the second sampling clock signal clkN2. A phase of the second sampling clock signal clkN2is opposite to a phase of the original sampling clock signal clk during a period in which the enable signal EnDfe is at the first level. The second sampling clock signal clkN2is a logic high-level signal during a period in which the enable signal EnDfe is at the second level. The second comparison circuit121has a third node net3and a fourth node net4, and is configured to receive the data signal DQ and the second reference signal VR−, perform the second comparison in response to the second sampling clock signal clkN2during a period in which the enable signal EnDfe is at the first level, output the third signal Sn− and the fourth signal Sp− through the third node net3and the fourth node net4respectively, turn on a connection path between the third node net3and ground during a period in which the enable signal EnDfe is at the second level, and turn on a connection path between the fourth node net4and ground.

It may be understood that, in some embodiments, regardless of whether the impact of the intersymbol interference on the data receiving circuit100is required to be considered, the first comparison circuit111may perform the first comparison in response to the first sampling clock signal clkN1, and output the first signal Sn+ and the second signal Sp+ through the first node net1and the second node net2respectively. However, for the second comparison circuit121, the second comparison circuit121determines, based on the received second sampling clock signal clkN2, whether to perform the second comparison. For example, when the impact of the intersymbol interference on the data receiving circuit100is required to be reduced, the enable signal EnDfe is set to be at the first level, the phase of the current second sampling clock signal clkN2is opposite to the phase of the original sampling clock signal clk, so that the second comparison circuit121may perform the second comparison in response to the second sampling clock signal clkN2. When the impact of the intersymbol interference on the data receiving circuit100is not required to be considered, the enable signal EnDfe is set to be at the second level, and the current second sampling clock signal clkN2is a logic high-level signal. The second comparison circuit121turns on the connection path between the third node net3and ground and turns on the connection path between the fourth node net4and ground by means of the logic high-level signal, so that the second comparison circuit121outputs the third signal Sn− and the fourth signal Sp− respectively through the third node net3and the fourth node net4respectively, both of which are logic low-level signals. There is no level variance between the third signal Sn− and the fourth signal Sp−. In addition, in this case, the current in the second comparison circuit121is almost 0, thus facilitating reducing the overall power consumption of the data receiving circuit100.

In some embodiments, referring toFIG.3toFIG.5, the first comparison circuit111may include: a first current source1111, a first comparator1112, and a first reset circuit1113. The first current source1111is connected between a power node Vcc and a fifth node net5, and configured to supply a current to the fifth node net5in response to the first sampling clock signal clkN1. The first comparator1112is connected to the first node net1, the second node net2and the fifth node net5, and configured to receive the data signal DQ and the first reference signal VR+, perform the first comparison when the first current source1111supplies the current to the fifth node net5, and output the first signal Sn+ and the second signal Sp+. The first reset circuit1113is connected to the first node net1and the second node net2, and configured to reset the first node net1and the second node net2in response to the first sampling clock signal clkN1.

The second comparison circuit121may include: a second current source1211, a second comparator1212, and a second reset circuit1213. The second current source1211is connected between the power node Vcc and a sixth node net6, and configured to supply a current to the sixth node net6in response to the second sampling clock signal clkN2. The second comparator1212is connected to the third node net3, the fourth node net4and the sixth node net6, and configured to receive the data signal DQ and the second reference signal VR−, perform the second comparison when the second current source1211supplies the current to the sixth node net6, and output the third signal Sn− and the fourth signal Sp−. The second reset circuit1213is connected between the third node net3and the fourth node net4, and configured to reset the third node net3and the fourth node net4in response to the second sampling clock signal clkN2.

It may be understood that, based on a voltage difference between the data signal DQ and the first reference signal VR+, the first comparator1112may control a difference between the current supplied to the first node net1and the current supplied to the second node net2, so as to output the first signal Sn+ and the second signal Sp+. The second comparator1212may control a difference between the current supplied to the third node net3and the current supplied to the fourth node net4, based on a voltage difference between the data signal DQ and the second reference signal VR−, so as to output the third signal Sn− and the fourth signal Sp−. In addition, after the data receiving circuit100completes one reception of the data signal DQ, the first reference signal VR+ and the second reference signal VR− and one output of the first output signal Vout and the second output signal VoutN, the levels at the first node net1and the second node net2may restore to their respective initial values through the first reset circuit1113, and the levels at the third node net3and the fourth node net4may restore to their respective initial values through the second reset circuit1213, so that the data receiving circuit100can perform next data receiving and processing subsequently.

In some embodiments, a circuit structure of the first current source1111is the same as a circuit structure of the second current source1211. A circuit structure of the first comparator1112is the same as a circuit structure of the second comparator1212. In this way, the difference between the first signal pair outputted by the first comparison circuit111and the second signal pair outputted by the second comparison circuit121is mainly affected by the first reference signal VR+ and the second reference signal VR−, so that the data receiving circuit100can further reduce the impact of the intersymbol interference of the received data signal DQ on the data receiving circuit100based on the first reference signal VR+ and the second reference signal VR−. Therefore, the accuracy of the first output signal Vout and the second output signal VoutN outputted by the second amplification circuit102can be further enhanced.

In some embodiments, referring toFIG.5, the first current source1111may include: a first PMOS transistor MP1, connected between the power node Vcc and the fifth node net5. A gate of the first PMOS transistor MP1is configured to receive the first sampling clock signal clkN1. The second current source1211may include a second PMOS transistor MP2, connected between the power node Vcc and the sixth node net6. A gate of the second PMOS transistor MP2is configured to receive the second sampling clock signal clkN2.

Therefore, when the first sampling clock signal clkN1is at a low level, the gate of the first PMOS transistor MP1is turned on by receiving the first sampling clock signal clkN1; the current is supplied to the fifth node net5to cause the first comparator1112to be in an operating state. That is to say, the first comparison is performed on the received data signal DQ and the first reference signal VR+. When the second sampling clock signal clkN2is at a low level, the gate of the second PMOS transistor MP2is turned on by receiving the second sampling clock signal clkN2; the current is supplied to the sixth node net6to cause the second comparator1212to be in an operating state; and then the second comparison is performed on the received data signal DQ and the second reference signal VR−.

In an example, the phase of the first sampling clock signal clkN1is opposite to the phase of the original sampling clock signal clk. When the impact of the intersymbol interference on the data receiving circuit is required to be reduced, the enable signal EnDfe is set at the first level, and the phase of the second sampling clock signal clkN2is also opposite to the phase of the original sampling clock signal clk, so that the phase of the first sampling clock signal clkN1and the phase of the second sampling clock signal clkN2are synchronous, and the first PMOS transistor MP1and the second PMOS transistor MP2are turned on at the same time, to cause the first comparator1112to perform the first comparison and cause the second comparator1212to perform the second comparison. Then, the first signal pair and the second signal pair outputted by the first amplification circuit101are both valid. That is to say, there is a level difference between the first signal pair and the second signal pair. Subsequently, the second amplification circuit102may selectively receive the first signal pair or the second signal pair based on the varying feedback signal fb, to reduce the impact of the intersymbol interference of the received data signal DQ on the data receiving circuit100. In addition, when the impact of the intersymbol interference on the data receiving circuit100is not required to be considered, the enable signal EnDfe is set to be at the second level, the second sampling clock signal clkN2is the logic high-level signal, and the second PMOS transistor MP2is always turned off, so that the current in the second comparator1212is almost 0, so as to reduce the power consumption of the data receiving circuit100. Furthermore, at this time, the current second comparator1212cannot perform the second comparison, so that the valid second signal pair cannot be outputted. At this time, the first sampling clock signal clkN1is a clock signal, and the first PMOS transistor MP1may start to be turned on based on a falling edge of the clock signal, so as to cause the first comparator1112to perform the first comparison to output the valid first signal pair. Therefore, the entire data receiving circuit100may normally operate.

In some embodiments, referring toFIG.5, the first comparator1112may include: a third PMOS transistor MP3and a fourth PMOS transistor MP4. The third PMOS transistor MP3is connected between the first node net1and the fifth node net5, where a gate of the third PMOS transistor MP3is configured to receive the data signal DQ. The fourth PMOS transistor MP4is connected between the second node net2and the fifth node net5, where a gate of the fourth PMOS transistor MP4is configured to receive the first reference signal VR+. The second comparator1212may include: a fifth PMOS transistor MP5and a sixth PMOS transistor MP6. The fifth PMOS transistor MP5is connected between the third node net3and the sixth node net6, where a gate of the fifth PMOS transistor MP5is configured to receive the data signal DQ. The sixth PMOS transistor MP6is connected between the fourth node net4and the sixth node net6, where a gate of the sixth PMOS transistor MP6is configured to receive the second reference signal VR.

It is to be noted that, for the first comparator1112, variance of the level of the data signal DQ and variance of the level of the first reference signal VR+ are asynchronous, so that a turning-on moment of the third PMOS transistor MP3receiving the data signal DQ is different from a turning-on moment of the fourth PMOS transistor MP4receiving the first reference signal VR+, and at the same moment, a turning-on degree of the third PMOS transistor MP3is different from a turning-on degree of the fourth PMOS transistor MP4. It may be understood that, since the turning-on degree of the third PMOS transistor MP3is different from the turning-on degree of the fourth PMOS transistor MP4, the abilities of the third PMOS transistor MP3and the fourth PMOS transistor MP4for shunting the current at the fifth node net5are also different, so that a voltage at the first node net1is different from a voltage at the second node net2, which facilitates output of the first signal Sn+ and the second signal Sp+ as the first signal pair with a larger level difference.

For the second comparator1212, variance of the level of the data signal DQ and variance of the level of the second reference signal VR− are asynchronous, so that a turning-on moment of the fifth PMOS transistor MP5receiving the data signal DQ is different from a turning-on moment of the sixth PMOS transistor MP6receiving the second reference signal VR−, and at the same moment, a turning-on degree of the fifth PMOS transistor MP5is different from a turning-on degree of the sixth PMOS transistor MP6. It may be understood that, since the turning-on degree of the fifth PMOS transistor MP5is different from the turning-on degree of the sixth PMOS transistor MP6, the abilities of the fifth PMOS transistor MP5and the sixth PMOS transistor MP6for shunting the current at the sixth node net6are also different, so that a voltage at the third node net3is different from a voltage at the fourth node net4, which facilitates the output of the third signal Sn− and the fourth signal Sp− as the second signal pair having a larger level difference.

In an example, when the level of the data signal DQ is lower than the level of the first reference signal VR+, the turning-on degree of the third PMOS transistor MP3is greater than the turning-on degree of the fourth PMOS transistor MP4, to cause more current at the fifth node net5to flow into a path where the third PMOS transistor MP3is located, so that the current at the first node net1is greater than the current at the second node net2, so as to further achieve a high level of the first signal Sn+ outputted by the first node net1and a low level of the second signal Sp+ outputted by the second node net2. When the level of the data signal DQ is lower than the level of the second reference signal VR−, the turning-on degree of the fifth PMOS transistor MP5is greater than the turning-on degree of the sixth PMOS transistor MP6, to cause more current at the sixth node net6to flow into a path where the fifth PMOS transistor MP5is located, so that the current at the third node net3is greater than the current at the fourth node net4, so as to further achieve a high level of the third signal Sn− outputted by the third node net3and a low level of the fourth signal Sp− outputted by the fourth node net4.

Likewise, when the level of the data signal DQ is higher than the level of the first reference signal VR+, the turning-on degree of the third PMOS transistor MP3is less than the turning-on degree of the fourth PMOS transistor MP4, so that the level of the first signal Sn+ outputted by the first node net1is low, and the level of the second signal Sp+ outputted by the second node net2is high. When the level of the data signal DQ is higher than the level of the second reference signal VR−, a turning-on degree of the fifth PMOS transistor MP5is less than a turning-on degree of the sixth PMOS transistor MP6, so that the level of the third signal Sn− outputted by the third node net3is low, and the level of the fourth signal Sp− outputted by the fourth node net4is high.

In some embodiments, referring toFIG.5, the first reset circuit1113may include a first NMOS transistor MN1and a second NMOS transistor MN2. The first NMOS transistor MN1is connected between the first node net1and ground, where a gate of the first NMOS transistor MN1is configured to receive the first sampling clock signal clkN1. The second NMOS transistor MN2is connected between the second node net2and ground, where a gate of the second NMOS transistor MN2is configured to receive the first sampling clock signal clkN1. The second reset circuit1213may include a third NMOS transistor MN3and a fourth NMOS transistor MN4. The third NMOS transistor MN3is connected between the third node net3and ground, where a gate of the third NMOS transistor MN3is configured to receive the second sampling clock signal clkN2. The fourth NMOS transistor MN4is connected between the fourth node net4and ground, where a gate of the fourth NMOS transistor MN4is configured to receive the second sampling clock signal clkN2.

In an example, the phase of the first sampling clock signal clkN1is opposite to the phase of the original sampling clock signal clk. When the impact of the intersymbol interference on the data receiving circuit is required to be reduced, the enable signal EnDfe is set to be at the first level, and the phase of the second sampling clock signal clkN2is also opposite to the phase of the original sampling clock signal clk. At this time, the phase of the first sampling clock signal clkN1and the phase of the second sampling clock signal clkN2are synchronous. If both the first sampling clock signal clkN1and the second sampling clock signal clkN2are at a low level, the first PMOS transistor MP1and the second PMOS transistor MP2are turned on. At this time, the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3and the fourth NMOS transistor MN4are all turned off, to guarantee that the first signal pair and the second signal pair outputted by the first amplification circuit101are valid. In addition, the first NMOS transistor MN1and the second NMOS transistor MN2may be used as loads of the first comparator1112, to increase the amplification gain of the first comparator1112. The third NMOS transistor MN3and the fourth NMOS transistor MN4may be used as loads of the second comparator1212, to increase the amplification gain of the second comparator1212. If both the first sampling clock signal clkN1and the second sampling clock signal clkN2are at a high level, the first PMOS transistor MP1and the second PMOS transistor MP2are turned off, so that there is no current passing through the first comparator1112and the second comparator1212. At this time, the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3and the fourth NMOS transistor MN4are all turned on, to pull down the voltage at the first node net1, the voltage at the second node net2, the voltage at the third node net3, and the voltage at the fourth node net4. Therefore, the first node net1, the second node net2, the third node net3, and the fourth node net4are reset. In this way, the data receiving circuit100can perform the next data receiving and processing subsequently.

In addition, when the impact of the intersymbol interference on the data receiving circuit100is not required to be considered, the enable signal EnDfe is set to be at the second level, the second sampling clock signal clkN2is the logic high-level signal, and the second PMOS transistor MP2is always turned off. At this time, the third NMOS transistor MN3and the fourth NMOS transistor MN4are both turned on, to pull down the connection path between the third node net3and ground, and the connection path between the fourth node net4and ground is turned on, so that the third node net3and the fourth node net4can be reset. At this time, the current in the second comparator1212is almost 0, so that the power consumption of the data receiving circuit100can be reduced. At this time, if the first sampling clock signal clkN1is at a low level, the first PMOS transistor MP1is turned on, and the first NMOS transistor MN1and the second NMOS transistor MN2are turned off, to guarantee the first comparison circuit111to perform the first comparison, so as to output the valid first signal pair, so that the second amplification circuit102may keep receiving the first signal pair subsequently. Alternatively, if the first sampling clock signal clkN1is at a high level, the first PMOS transistor MP1is turned off, and the first NMOS transistor MN1and the second NMOS transistor MN2are turned on to pull down a voltage at the first node net1and a voltage at the second node net2, the first node net1and the second node net2are reset. Therefore, the data receiving circuit100can perform the next data receiving and processing subsequently.

In some embodiments, continuously referring toFIG.5, the clock generation circuit131may include: a first NAND gate circuit1311. One input of the first NAND gate circuit1311is configured to receive the original sampling clock signal, the other input of the first NAND gate circuit1311is connected to the power node Vcc; and an output of the first NAND gate circuit1311is configured to output the first sampling clock signal clkN1.

It may be understood that, since one input of the first NAND gate circuit1311is connected to the power node Vcc, the input is configured to receive a high level. At this time, if the original sampling clock signal clk received by the other input of the first NAND gate circuit1311is at the high level, the first sampling clock signal clkN1is at the low level. If the original sampling clock signal clk received by the other input of the first NAND gate circuit1311is at the low level, the first sampling clock signal clkN1is at the high level. In this way, the phase of the first sampling clock signal clkN1is opposite to the phase of the original sampling clock signal clk. Therefore, when the impact of the intersymbol interference on the data receiving circuit is required to be reduced, the phase of the first sampling clock signal clkN1and the phase of the second sampling clock signal clkN2are synchronous, so that the first amplification circuit101may simultaneously perform the first comparison and the second comparison.

In some embodiments, continuously referring toFIG.5, the clock generation circuit131may include: a second NAND gate circuit1312. One input of the second NAND gate circuit1312is configured to receive the original sampling clock signal clk, and the other input of the second NAND gate circuit1312is configured to receive the enable signal EnDfe; and an output of the second NAND gate circuit1312is configured to output the second sampling clock signal clkN2.

It is to be noted that, in an example, the period in which the enable signal EnDfe is at the first level refers to a level range in which the second NAND gate circuit1312determines the enable signal EnDfe to be at a logic level 1, that is, the high level. The second level of the enable signal EnDfe refers to a level range in which the second NAND gate circuit1312determines the enable signal EnDfe to be at a logic level 0, that is, the low level.

It may be understood that, the phase of the first sampling clock signal clkN1is opposite to the phase of the original sampling clock signal clk; when the impact of the intersymbol interference on the data receiving circuit is required to be reduced, the enable signal EnDfe is set to be at the high level. If the original sampling clock signal clk is at the high level, the two inputs of the second NAND gate circuit1312are configured to receive the high level, so that the second sampling clock signal clkN2outputted by the output is at the low level. At this time, the first sampling clock signal clkN1is also at the low level, so that the first amplification circuit101may simultaneously perform the first comparison and the second comparison, and the second amplification circuit102may selectively receive the first signal pair or the second signal pair based on the varying feedback signal fb subsequently, so as to reduce the impact of the intersymbol interference of the received data signal DQ on the data receiving circuit100. If the original sampling clock signal clk is at the low level, the second sampling clock signal clkN2outputted by the second NAND gate circuit1312is at the high level. At this time, the first sampling clock signal clkN1is also at the high level, so that the first comparator1112and the second comparator1212are in a non-operating state. In this way, the levels at the first node net1and the second node net2may restore to their respective initial values through the first reset circuit1113, and the levels at the third node net3and the fourth node net4restore to their respective initial values through the second reset circuit1213, so that the data receiving circuit100can perform the next data receiving and processing subsequently.

When the impact of the intersymbol interference on the data receiving circuit100is not required to be considered, the enable signal EnDfe is set to be at the low level. At this time, regardless of the original sampling clock signal clk being at the high level or at the low level, the second sampling clock signal clkN2outputted by the second NAND gate circuit1312is at the high level. Therefore, regardless of the first sampling clock signal clkN1being at the high level or at the low level, that is, regardless of whether the first comparator1112performs the first comparison, in the second comparison circuit121, the connection path between the third node net3and ground and the connection path between the fourth node net4and ground are turned on, so that the third signal Sn− and the fourth signal Sp− outputted by the second comparison circuit121using the third node net3and the fourth node net4respectively are logic low-level signals. There is no level difference between the third signal Sn− and the fourth signal Sp−.

It is to be noted that, it is merely an example that both the first NAND gate circuit1311and the second NAND gate circuit1312only include one NAND gate inFIG.5. In the practical application, specific structures of the first NAND gate circuit1311and the second NAND gate circuit1312are not limited, so that circuits that can realize NAND logic may be the first NAND gate circuit1311and the second NAND gate circuit1312.

In some embodiments, referring toFIG.4, the second amplification circuit102may include: a decision equalization enable circuit152, a first input circuit112, a second input circuit122, and a latch132. The decision equalization enable circuit152is configured to receive the feedback signal fb (referring toFIG.1) and the enable signal EnDfe. The first input circuit112is connected to a seventh node net7and an eighth node net8, and configured to be connected to the decision equalization enable circuit152, be turned on under control of the decision equalization enable circuit152to receive the first signal pair for third comparison, and provide signals to the seventh node net7and the eighth node net8respectively as a result of the third comparison. The second input circuit122is connected to the seventh node net7and the eighth node net8, and configured to be connected to the decision equalization enable circuit152, be turned on under control of the decision equalization enable circuit152to receive the second signal pair for fourth comparison, and provide the signal to the seventh node net7and the eighth node net8respectively as a result of the fourth comparison, where the first input circuit112and the second input circuit122are alternatively turned on under control of the decision equalization enable circuit152. The latch132is connected to the seventh node net7and the eighth node net8, and configured to amplify and latch the signal of the seventh node net7and the signal of the eighth node net8, and output the first output signal Vout and the second output signal VoutN through first output node net9and a second output node net10respectively.

It may be understood that, when the impact of the intersymbol interference on the data receiving circuit is required to be reduced, the enable signal EnDfe is set to be at the first level, the first signal pair and the second signal pair outputted by the first amplification circuit101are valid, and the first input circuit112and the second input circuit122are controlled by the decision equalization enable circuit152. At this time, the input circuit that is turned on receives the signal pair having a larger signal level difference in the received signal pairs, so that the second amplification circuit102receives one of the first signal pair and the second signal pair that has a larger level difference, to enhance the accuracy of the first output signal Vout and the second output signal VoutN outputted by the second amplification circuit102. When the impact of the intersymbol interference on the data receiving circuit100is not required to be considered, the enable signal EnDfe is set to be at the second level, and the first input circuit112and the second input circuit122are not controlled by the decision equalization enable circuit152, so that the first input circuit112is turned on or off under control of the received first signal pair, and the second input circuit122is turned on or off under control of the received second signal pair.

In addition, the decision equalization enable circuit152is integrated in the second amplification circuit102, so that an overall layout area of the data receiving circuit100can be further reduced.

The latch132is configured to output a high level signal to the first output node net9and output a low level signal to the second output node net10according to the signal of the seventh node net7and the signal of the eighth node net8, or to output the low level signal to the first output node net9and output the high level signal to the second output node net10.

In some embodiments, continuously referring toFIG.4, the feedback signal fb (referring toFIG.1) may include a differential first feedback signal fbp and a second feedback signal fbn. The decision equalization enable circuit152may include a first enable circuit1521and a second enable circuit1522. The first enable circuit1521is connected between ground and the first input circuit112and between ground and the second input circuit122, and configured to receive the enable signal EnDfe, the first feedback signal fbp and the second feedback signal fbn, so as to control one of the first input circuit112and the second input circuit122to be connected to ground. The second enable circuit1522is connected between ground and the first input circuit112and between ground and the second input circuit122, and configured to receive a complementary enable signal EnDfeN, so as to control the first input circuit112to be connected to ground. A level of the complementary enable signal EnDfeN is opposite to a level of the enable signal EnDfe. The first enable circuit1521and the second enable circuit1522are alternatively selected to be turned on.

It is to be noted that, that the level of the complementary enable signal EnDfeN is opposite to the level of the enable signal EnDfe means that, when one of the complementary enable signal EnDfeN and the enable signal EnDfe is at the high level, the other one is at the low level.

It may be understood that, when the impact of the intersymbol interference on the data receiving circuit is required to be reduced, the enable signal EnDfe is set to be at the first level, and the complementary enable signal EnDfeN is set to be at the second level. At this time, the first enable circuit1521turns on the first input circuit112or the second input circuit122based on one of the first feedback signal fbp and the second feedback signal fbn, so that the second amplification circuit102receives one of the first signal pair and the second signal pair that has a larger level difference. At this time, the second enable circuit1522is turned off. When the impact of the intersymbol interference on the data receiving circuit100is not required to be considered, the enable signal EnDfe is set to be at the second level, the complementary enable signal EnDfeN is set to be at the first level, and the second enable circuit1522is turned on, so that the first input circuit112is turned on or off under control of the received first signal pair. At this time, the third signal Sn− and the fourth signal Sp− outputted by the second comparison circuit121are logic low-level signals, so that the second input circuit122receiving the third signal Sn− and the fourth signal Sp− is turned off, and at this time, the first enable circuit1521is also turned off, so as to further reduce the power consumption of the data receiving circuit100.

It is to be noted that, in an example, the period in which the complementary enable signal EnDfeN is at the first level refers to a level range in which the second enable circuit1522determines the complementary enable signal EnDfeN to be at the logic level 1, that is, the high level. The period in which the complementary enable signal EnDfeN is at the second level refers to a level range in which the second enable circuit1522determines the complementary enable signal EnDfeN to be at the logic level 0, that is, the low level. In addition, the decision equalization enable circuit152may provide the complementary enable signal EnDfeN to itself based on the received enable signal EnDfe. In the practical application, the complementary enable signal EnDfeN may also be provided to the decision equalization enable circuit152by other circuits.

In some embodiments, referring toFIG.6, the first input circuit112may include: a fifth NMOS transistor MN5and a sixth NMOS transistor MN6. A drain of the fifth NMOS transistor MN5is connected to the seventh node net7, a source of the fifth NMOS transistor MN5is connected to the first enable circuit1521and the second enable circuit1522, and a gate of the fifth NMOS transistor MN5is configured to receive the first signal Sn+. A drain of the sixth NMOS transistor MN6is connected to the eighth node net8; a source of the sixth NMOS transistor MN6is connected to the first enable circuit1521and the second enable circuit1522; and a gate of the sixth NMOS transistor MN6is configured to receive the second signal Sp+. The second input circuit122may include a seventh NMOS transistor MN7and an eighth NMOS transistor MN8. A drain of the seventh NMOS transistor MN7is connected to the seventh node net7, a source of the seventh NMOS transistor MN7is connected to the first enable circuit1521and the second enable circuit1522, and a gate of the seventh NMOS transistor MN7is configured to receive the third signal Sn−. A drain of the eighth NMOS transistor MN8is connected to the eighth node net8; a source of the eighth NMOS transistor MN8is connected to the first enable circuit1521and the second enable circuit1522; and a gate of the eighth NMOS transistor MN8is configured to receive the fourth signal Sp−.

In an example, when the first input circuit112is turned on under control of the decision equalization enable circuit152, and if the level of the data signal DQ is higher than the level of the first reference signal VR+, the level of the first signal Sn+ is low, and the level of the second signal Sp+ is high, the gate of the fifth NMOS transistor MN5receives the first signal Sn+, and the gate of the sixth NMOS transistor MN6receives the second signal Sp+, so that a turning-on degree of the sixth NMOS transistor MN6is greater than a turning-on degree of the fifth NMOS transistor MN5, and the voltage at the eighth node net8is less than the voltage at the seventh node net7. Likewise, if the level of the data signal DQ is lower than the level of the first reference signal VR+, the level of the first signal Sn+ is high, and the level of the second signal Sp+ is low, the turning-on degree of the fifth NMOS transistor MN5is greater than the turning-on degree of the sixth NMOS transistor MN6, and the voltage at the seventh node net7is less than the voltage at the eighth node net8.

In another example, when the second input circuit122is turned on under control of the decision equalization enable circuit152, and if the level of the data signal DQ is higher than the level of the second reference signal VR−, the level of the third signal Sn− is low, and the level of the fourth signal Sp− is high, the gate of the seventh NMOS transistor MN7receives the third signal Sn−, and the gate of the eighth NMOS transistor MN8receives the fourth signal Sp−, so that a turning-on degree of the eighth NMOS transistor MN8is greater than a turning-on degree of the seventh NMOS transistor MN7, and the voltage at the eighth node net8is less than the voltage at the seventh node net7. Likewise, if the level of the data signal DQ is lower than the level of the second reference signal VR−, the level of the third signal Sn− is high, and the level of the fourth signal Sp− is low, the turning-on degree of the seventh NMOS transistor MN7is greater than the turning-on degree of the eighth NMOS transistor MN8, and the voltage at the seventh node net7is less than the voltage at the eighth node net8.

In some embodiments, continuously referring toFIG.6, the first enable circuit1521may include a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11and a twelfth NMOS transistor MN12. A drain of the ninth NMOS transistor MN9is connected to the source of the fifth NMOS transistor MN5and the source of the sixth NMOS transistor MN6, a source of the ninth NMOS transistor MN9is connected to a drain of the tenth NMOS transistor MN10, a gate of the ninth NMOS transistor MN9is configured to receive the first feedback signal fbp, a gate of the tenth NMOS transistor MN10is configured to receive the enable signal EnDfe, and a source of the tenth NMOS transistor MN10is connected to ground. A drain of the eleventh NMOS transistor MN11is connected to the source of the seventh NMOS transistor MN7and the source of the eighth NMOS transistor MN8; a source of the eleventh NMOS transistor MN11is connected to a drain of the twelfth NMOS transistor MN12; a gate of the eleventh NMOS transistor MN11is configured to receive the second feedback signal fbn; a gate of the twelfth NMOS transistor MN12is configured to receive the enable signal EnDfe; and a source of the twelfth NMOS transistor MN12is connected to ground.

It is to be noted that, that the first enable circuit1521controlling the first input circuit112to be connected to ground means that, the first enable circuit1521controls the turning on of the ninth NMOS transistor MN9and the tenth NMOS transistor MN10based on the enable signal EnDfe and the first feedback signal fbp, so that the first input circuit112may be turned on upon receiving the first signal pair, so as to be connected to ground. That the first enable circuit1521controls the second input circuit122to be connected to ground means that, the first enable circuit1521controls the turning on of the eleventh NMOS transistor MN11and the twelfth NMOS transistor MN12based on the enable signal EnDfe and the second feedback signal fbn, so that the second input circuit122may be turned on upon receiving the second signal pair, so as to be connected to ground.

In some embodiments, continuously referring toFIG.6, the second enable circuit1522may include: a thirteenth NMOS transistor MN13and a fourteenth NMOS transistor MN14. A drain of the thirteenth NMOS transistor MN13is connected to the source of the fifth NMOS transistor MN5and the source of the sixth NMOS transistor MN6, a source of the thirteenth NMOS transistor MN13is connected ground, and a gate of the thirteenth NMOS transistor MN13is configured to receive the complementary enable signal EnDfeN. A drain of the fourteenth NMOS transistor MN14is connected to the source of the seventh NMOS transistor MN7and the source of the eighth NMOS transistor MN8; a source of the fourteenth NMOS transistor MN14is connected ground; and a gate of the fourteenth NMOS transistor MN14is configured to receive the complementary enable signal EnDfeN.

It is to be noted that, when a plurality of data receiving circuits100are cascaded, obtaining the feedback signal fb based on the previously received data means that, the first output signal Vout and the second output signal VoutN outputted by the data receiving circuit100at a previous stage are used as the feedback signals fb of the data receiving circuit100at a subsequent stage; and the first output signal Vout and the second output signal VoutN outputted by the data receiving circuit100at the last stage are used as the feedback signals fb of the data receiving circuit100at the first stage. Specifically, the first output signal Vout outputted by the first output node net9of the data receiving circuit100at the previous stage is used as the first feedback signal fbp of the data receiving circuit100at the subsequent stage. The second output signal VoutN outputted by the second output node net10of the data receiving circuit100at the previous stage is used as the second feedback signal fbn of the data receiving circuit100at the subsequent stage. The first output signal Vout outputted by the first output node net9of the data receiving circuit100at the last stage is used as the first feedback signal fbp of the data receiving circuit100at the first stage. The second output signal VoutN outputted by the second output node net10of the data receiving circuit100at the last stage is used as the second feedback signal fbn of the data receiving circuit100at the first stage.

It may be understood that, if the first output signal Vout outputted by the first output node net9of the data receiving circuit100at the previous stage is at the high level and the second output signal VoutN outputted by the second output node net10is at the low level, the first feedback signal fbp received by the data receiving circuit100at the subsequent stage is at the high level, and the second feedback signal fbn is at the low level. At this time, the ninth NMOS transistor MN9is turned on, and the eleventh NMOS transistor MN11is turned off. When the impact of the intersymbol interference on the data receiving circuit is required to be reduced, the enable signal EnDfe is set to be at the logic level 1, and the complementary enable signal EnDfeN is set to be at the logic level 0, then the tenth NMOS transistor MN10is turned on, so that the first input circuit112is connected to ground, to provide signals to the seventh node net7and the eighth node net8as a result of the third comparison. At this time, the thirteenth NMOS transistor MN13and the fourteenth NMOS transistor MN14are disconnected.

If in the data receiving circuit100at the previous stage, the first output signal Vout outputted by the first output node net9is at the low level and the second output signal VoutN outputted by the second output node net10is at the high level, the first feedback signal fbp received by the data receiving circuit100at the subsequent stage is at the low level, and the second feedback signal fbn received by the data receiving circuit100at the subsequent stage is at the high level. At this time, the ninth NMOS transistor MN9is turned off, and the eleventh NMOS transistor MN11is turned on. When the impact of the intersymbol interference on the data receiving circuit is required to be reduced, the enable signal EnDfe is set to be at the logic level 1, the complementary enable signal EnDfeN is set to be at the logic level 0, then the twelfth NMOS transistor MN12is turned on, so that the second input circuit122is connected to ground, to provide signals to the seventh node net7and the eighth node net8as a result of the fourth comparison. At this time, the thirteenth NMOS transistor MN13and the fourteenth NMOS transistor MN14are disconnected.

When the impact of the intersymbol interference on the data receiving circuit100is not required to be considered, the enable signal EnDfe is set to be at the logic level 0, and the complementary enable signal EnDfeN is set to be at the logic level 1, then the tenth NMOS transistor MN10and the twelfth NMOS transistor MN12are turned off, that is, the first enable circuit1521is turned off, and the thirteenth NMOS transistor MN13and the fourteenth NMOS transistor MN14are turned on, so that the first input circuit112is turned on or off under control of the received first signal Sn+ and the second signal Sp+. For example, when the first comparison circuit111performs the first comparison to output the first signal Sn+ and the second signal Sp+ that are the differential signals, the turning-on degrees of the fifth NMOS transistor MN5and the sixth NMOS transistor MN6are different due to different levels of the received signals, so as to guarantee the accuracy of the first output signal Vout and the second output signal VoutN. At this time, the third signal Sn− and the fourth signal Sp− outputted by the second comparison circuit121are the logic low-level signals, so that the seventh NMOS transistor MN7receiving the third signal Sn− and the eighth NMOS transistor MN8receiving the fourth signal Sp− are turned off, which facilitates reducing the power consumption of the data receiving circuit100.

In some embodiments, continuously referring toFIG.6, the latch132may include: a fifteenth NMOS transistor MN15, a seventh PMOS transistor MP7, a sixteenth NMOS transistor MN16and an eighth PMOS transistor MP8. A gate of the fifteenth NMOS transistor MN15and a gate of the seventh PMOS transistor MP7are connected to the second output node net10, a source of the fifteenth NMOS transistor MN15is connected to the seventh node net7, a drain of the fifteenth NMOS transistor MN15and a drain of the seventh PMOS transistor MP7are connected to the first output node net9, and a source of the seventh PMOS transistor MP7is connected to a power node Vcc. A gate of the sixteenth NMOS transistor MN16and a gate of the eighth PMOS transistor MP8are connected to the first output node net9; a source of the sixteenth NMOS transistor MN16is connected to the eighth node net8; a drain of the sixteenth NMOS transistor MN16and a drain of the eighth PMOS transistor MP8are connected to the second output node net10; and a source of the eighth PMOS transistor MP8is connected to the power node Vcc.

In an example, if the level of the data signal DQ is higher than the level of the first reference signal VR+, that is, the voltage at the eighth node net8is less than the voltage at the seventh node net7, the turning-on degree of the sixteenth NMOS transistor MN16is greater than a turning-on degree of the fifteenth NMOS transistor MN15. The voltage at the second output node net10is less than the voltage at the first output node net9, so that the turning-on degree of the eighth PMOS transistor MP8is less than the turning-on degree of the seventh PMOS transistor MP7. Therefore, the latch132forms a positive feedback amplification, to further cause the first output signal Vout outputted by the first output node net9to be at the high level and cause the second output signal VoutN outputted by the second output node net10to be at the low level. Likewise, if the level of the data signal DQ is lower than the level of the first reference signal VR+, that is, the voltage at the seventh node net7is less than the voltage at the eighth node net8, the first output signal Vout outputted by the first output node net9is at the low level, and the second output signal VoutN outputted by the second output node net10is at the high level. In some embodiments, continuously referring toFIG.6, the second amplification circuit102may further include: a third reset circuit142, connected between a power node Vcc and an output of the latch132, and configured to reset the output of the latch132. In this way, after the data receiving circuit100completes one receiving of the data signal DQ, the first reference signal VR+ and the second reference signal VR− and one output of the first output signal Vout and the second output signal VoutN, the levels at the first output node net9and the second output node net10may restore to their respective initial values through the third reset circuit142, so that the data receiving circuit100can perform the next data receiving and processing subsequently.

In some embodiments, continuously referring toFIG.6, the third reset circuit142may include: a ninth PMOS transistor MP9and a tenth PMOS transistor MP10. The ninth PMOS transistor MP9is connected between the first output node net9and a power node Vcc, where a gate of the ninth PMOS transistor MP9is configured to receive the original sampling clock signal clk. The tenth PMOS transistor MP10is connected between the second output node net10and the power node Vcc, where a gate of the tenth PMOS transistor MP10is configured to receive the original sampling clock signal clk.

In an example, the phase of the first sampling clock signal clkN1is opposite to the phase of the original sampling clock signal clk. Referring toFIG.5andFIG.6, when the impact of the intersymbol interference on the data receiving circuit100is required to be reduced, the enable signal EnDfe is set to be at the logic level 1, the complementary enable signal EnDfeN is set to be at the logic level 0, the phase of the second sampling clock signal clkN2is set to be opposite to the phase of the original sampling clock signal clk. When the original sampling clock signal clk is at the high level, the first sampling clock signal clkN1and the second sampling clock signal clkN2are at the low level, so that the first NMOS transistor MN1and the second NMOS transistor MN2are turned on, and the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the ninth PMOS transistor MP9, and the tenth PMOS transistor MP10are all turned off. When the original sampling clock signal clk is at the low level, the first sampling clock signal clkN1and the second sampling clock signal clkN2are at the high level, so that the first PMOS transistor MP1and the second PMOS transistor MP2are turned off. At this time, the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3and the fourth NMOS transistor MN4are all turned on, to pull down the voltage at the first node net1, the voltage at the second node net2, the voltage at the third node net3, and the voltage at the fourth node net4, and therefore, the first node net1, the second node net2, the third node net3, and the fourth node net4are reset; the ninth PMOS transistor MP9and the tenth PMOS transistor MP10are also turned on, to pull up the voltage at the first output node net9and the voltage at the second output node net10, so as to reset the first output node net9and the voltage at the second output node net10.

When the impact of the intersymbol interference on the data receiving circuit100is not required to be considered, the enable signal EnDfe is set to be at the logic level 0, and the complementary enable signal EnDfeN is set to be at the logic level 1. At this time, regardless of whether the original sampling clock signal clk is at the high level or at the low level, the second sampling clock signal clkN2is always at the high level, so that the second PMOS transistor MP2is always turned off, and the third NMOS transistor MN3and the fourth NMOS transistor MN4are turned on, so as to reduce the current in the second comparison circuit121, thereby reducing the power consumption of the data receiving circuit100.

A specific operating principle of the data receiving circuit100provided in an embodiment of the disclosure is described in detail below with reference toFIG.6and Table 1.

In an example, when the plurality of data receiving circuits100are cascaded, the first output signal Vout outputted by the first output node net9of the data receiving circuit100at the previous stage is used as the first feedback signal fbp of the data receiving circuit100at the subsequent stage. The second output signal VoutN outputted by the second output node net10of the data receiving circuit100at the previous stage is used as the second feedback signal fbn of the data receiving circuit100at the subsequent stage.

The level of the first reference signal VR+ being greater than the level of the second reference signal VR− is used as an example for description below. When the data signal DQ is at the logic level 1, it represents that the level of the data signal DQ is greater than the level of the first reference signal VR+. When the data signal DQ is at the logic level 0, it represents that the level of the data signal DQ is less than the level of the second reference signal VR−. It is to be noted that, in Table 1, 1 represents a high level, and 0 represents a low level.

When the impact of the intersymbol interference on the data receiving circuit100is required to be considered, the enable signal EnDfe is at the high level, and the complementary enable signal EnDfeN is at the low level. At this time, the tenth NMOS transistor MN10and the twelfth NMOS transistor MN12are turned on, and the thirteenth NMOS transistor MN13and the fourteenth NMOS transistor MN14are turned off.

Referring to Table 1, if the data signal DQ1received by the data receiving circuit100at the previous stage is at the logic level 1, the first output signal Vout outputted by the data receiving circuit100at the previous stage, that is, the first feedback signal fbp of the data receiving circuit100at the subsequent stage is at the high level, and the second output signal VoutN outputted by the data receiving circuit100at the previous stage, that is, the second feedback signal fbn of the data receiving circuit100at the subsequent stage is at the low level. At this time, the gate of the ninth NMOS transistor MN9is turned on upon receiving the first feedback signal fbp, and the gate of the eleventh NMOS transistor MN11is disconnected upon receiving the second feedback signal fbn. The first input circuit112is configured to perform the third comparison on the first signal Sn+ and the second signal Sp+ to provide signals to the seventh node net7and the eighth node net8. There is no current flowing through the second input circuit122.

When the data signal DQ1received by the data receiving circuit100at the previous stage is at the logic level 1, the data signal DQ2received by the data receiving circuit100at the subsequent stage is in the following two cases, respectively.

Case I: referring to Table 1, when the data signal DQ2received by the data receiving circuit100at the subsequent stage is at the logic level 0, the level difference between the data signal DQ2and the data signal DQ1received by the data receiving circuit100at the previous stage is relatively large, so that there is a large intersymbol interference. At this time, the first input circuit112in the data receiving circuit100at the subsequent stage is turned on. That is to say, the second amplification circuit102in the data receiving circuit100at the subsequent stage receives the first signal Sn+ and the second signal Sp+. The first signal pair outputted by the first comparison circuit111in the data receiving circuit100at the subsequent stage is received by the second amplification circuit102. At this time, in the data receiving circuit100at the subsequent stage, the data signal DQ2is at the logic level 0, a voltage difference between the data signal DQ2and the first reference signal VR+ is greater than a voltage difference between the data signal DQ2and the second reference signal VR−, so that the level difference between the signals in the first signal pair processed by the first comparison circuit111is larger. At this time, the output accuracy of the first output signal Vout and the second output signal VoutN can be higher when the second amplification circuit102receives the first signal pair, thereby achieving the purpose of reducing the impact of the intersymbol interference of the received data signal DQ on the data receiving circuit100.

Case II: referring to Table 1, when the data signal DQ2received by the data receiving circuit100at the subsequent stage is at the logic level 1, the level difference between the data signal DQ2and the data signal DQ1received by the data receiving circuit100at the previous stage is relatively small, so that there is small or no intersymbol interference. At this time, the first input circuit112in the data receiving circuit100at the subsequent stage is turned on, and the first signal pair outputted by the first comparison circuit111in the data receiving circuit100at the subsequent stage is received by the second amplification circuit102.

Referring to Table 1, if the data signal DQ1received by the data receiving circuit100at the previous stage is at the logic level 0, the first output signal Vout outputted by the data receiving circuit100at the previous stage, that is, the first feedback signal fbp of the data receiving circuit100at the subsequent stage is at the low level, and the second output signal VoutN outputted by the data receiving circuit100at the previous stage, that is, the second feedback signal fbn of the data receiving circuit100at the subsequent stage is at the high level. At this time, the gate of the ninth NMOS transistor MN9is disconnected upon receiving the first feedback signal fbp, and the gate of the eleventh NMOS transistor MN11is turned on upon receiving the second feedback signal fbn. The second input circuit122is configured to perform the fourth comparison on the third signal Sn− and the fourth signal Sp− to provide signals to the seventh node net7and the eighth node net8. There is no current flowing through the first input circuit112.

When the data signal DQ1received by the data receiving circuit100at the previous stage is at the logic level 0, the data signal DQ2received by the data receiving circuit100at the subsequent stage is in the following two cases, respectively.

Case III: referring to Table 1, when the data signal DQ2received by the data receiving circuit100at the subsequent stage is at the logic level 0, the level difference between the data signal DQ2and the data signal DQ1received by the data receiving circuit100at the previous stage is relatively small, so that there is small or no intersymbol interference. At this time, the second input circuit122in the data receiving circuit100at the subsequent stage is turned on, and the second signal pair outputted by the second comparison circuit121in the data receiving circuit100at the subsequent stage is received by the second amplification circuit102.

Case IV: referring to Table 1, when the data signal DQ2received by the data receiving circuit100at the subsequent stage is at the logic level 1, the level difference between the data signal DQ2and the data signal DQ1received by the data receiving circuit100at the previous stage is relatively large, so that there is large intersymbol interference. At this time, the second input circuit122in the data receiving circuit100at the subsequent stage is turned on. That is to say, the second amplification circuit102in the data receiving circuit100at the subsequent stage receives the third signal Sn− and the fourth signal Sp−. The second signal pair outputted by the second comparison circuit121in the data receiving circuit100at the subsequent stage is received by the second amplification circuit102. At this time, in the data receiving circuit100at the subsequent stage, the data signal DQ2is at the logic level 1, a voltage difference between the data signal DQ2and the second reference signal VR− is greater than a voltage difference between the data signal DQ2and the first reference signal VR+, so that the level difference between the signals in the second signal pair processed by the second comparison circuit121is larger. At this time, the output accuracy of the first output signal Vout and the second output signal VoutN can be higher when the second amplification circuit102receives the second signal pair, thereby achieving the purpose of reducing the impact of the intersymbol interference of the received data signal DQ on the data receiving circuit100.

TABLE 1FirstSecondSignal pairData signalData signalfeedbackfeedbackreceived byDQ1DQ2signal fbpsignal fbnsecondreceivedreceivedreceivedreceivedamplificationby databy databy databy datacircuit in datatransmissiontransmissiontransmissiontransmissiontransmissioncircuit atcircuit atcircuit atcircuit atcircuit atprevioussubsequentsubsequentsubsequentsubsequentstagestagestagestagestage1010Sn+, Sp+1110Sn+, Sp+0001Sn−, Sp−0101Sn−, Sp−

When the impact of the intersymbol interference on the data receiving circuit100is not required to be considered, the enable signal EnDfe is at the low level, and the complementary enable signal EnDfeN is at the high level. At this time, the tenth NMOS transistor MN10and the twelfth NMOS transistor MN12are turned on, and the thirteenth NMOS transistor MN13and the fourteenth NMOS transistor MN14are turned off, so that the first input circuit112is turned on or off under control of the received first signal pair. At this time, the third signal Sn− and the fourth signal Sp− outputted by the second comparison circuit121are logic low-level signals, so that the second input circuit122receiving the third signal Sn− and the fourth signal Sp− is turned off.

It is to be noted that, in the above description of the high level and the low level, the high level may be a level that is greater than or equal to a supply voltage, and the low level may be a level that is less than or equal to a grounding voltage. However, the high level and the low level are relative. Specifically, level ranges included in the high level and the low level may be determined according to specific devices. For example, for an NMOS transistor, the high level refers to the level range of a gate voltage that can turn on the NMOS transistor, and the low level refers to the level range of a gate voltage that can turn off the NMOS transistor. For a PMOS transistor, the low level refers to the level range of a gate voltage that can turn on the PMOS transistor, and the high level refers to the level range of a gate voltage that can turn off the PMOS transistor. In addition, the high level may be the logic level 1 in the foregoing description, and the low level may be the logic level 0 in the foregoing description.

To sum up, the second amplification circuit102may be further controlled by means of the enable signal EnDfe, so as to determine whether to consider the impact of the intersymbol interference of data received by the data receiving circuit100on the data receiving circuit100. For example, when the impact of the intersymbol interference on the data receiving circuit100is required to be reduced, the enable signal EnDfe is set to be at the first level, and the second amplification circuit102selectively receives one of the first signal pair and the second signal pair that has a larger level difference based on the current enable signal EnDfe and the feedback signal fb, so as to ensure that the second amplification circuit102receives a pair of differential signals with a larger signal level difference. When the impact of the intersymbol interference on the data receiving circuit100is not required to be considered, the enable signal EnDfe is set to be at the second level, and the second amplification circuit102keeps receiving the first signal pair based on the current enable signal EnDfe, so as to achieve an effect of reducing the power consumption of the data receiving circuit100while improving the receiving performance of the data receiving circuit100.

Another embodiment of the disclosure further provides a data receiving system. The data receiving system provided in another embodiment of the disclosure is described in detail below with reference to the drawings.FIG.2is a functional block diagram of a data receiving system according to another embodiment of the disclosure.

Referring toFIG.2, the data receiving system includes: a plurality of cascaded data transmission circuits120, each of which includes the data receiving circuit100provided in an embodiment of the disclosure and a latch circuit110connected to the data receiving circuit100. An output signal of the data transmission circuit120at the previous stage is used as a feedback signal fb of the data transmission circuit120at the next stage. An output signal of the data transmission circuit120at the last stage is used as a feedback signal fb of the first stage data transmission circuit120.

The latch circuit110is in one-to-one correspondence with the data receiving circuit100. The latch circuit110is configured to latch and output a signal outputted by the data receiving circuit100corresponding to the latch circuit110.

In some embodiments, the data receiving circuit100receives data in response to a sampling clock signal. The data receiving system includes 4 cascaded data transmission circuits100, and a phase difference between the sampling clock signals clkN of the adjacent stage data receiving circuits100is 90°. Therefore, a period of the sampling clock signal clkN is 2 times of the period of the data signal DQ received by a data port, which facilitates clock wiring and reduction of power consumption.

It is to be noted that, inFIG.2, for example, the data receiving system includes 4 cascaded data receiving circuits100, and the phase difference between the sampling clock signals of the adjacent stage data receiving circuits100is 90°. In the practical application, the number of the cascaded data receiving circuits100included in the data receiving system is not limited, and a phase difference between the sampling clock signals of the adjacent stage data receiving circuits100may be reasonably set based on the number of the cascaded data receiving circuits100.

In some embodiments, the first output signal Vout and the second output signal VoutN outputted by the second amplification circuit102of the data receiving circuit100at the previous stage are used as the feedback signals fb of the data receiving circuit100at the subsequent stage. Therefore, the output of the data receiving circuit100is directly transmitted to the data transmission circuit120at the next stage without passing through the latch circuit110, so that the transmission delay of data can be reduced. Alternatively, a signal outputted by the latch circuit110at the previous stage is used as the feedback signal fb of the data receiving circuit100at the subsequent stage.

To sum up, according to the data receiving system provided in another embodiment of the disclosure, the second amplification circuit102may be further controlled by means of the enable signal EnDfe, so as to determine whether to consider the impact of the intersymbol interference of data received by the data receiving circuit100on the data receiving circuit100. For example, when the impact of the intersymbol interference on the data receiving circuit100is required to be reduced, the enable signal EnDfe is set to be at the first level, and the second amplification circuit102selectively receives one of the first signal pair and the second signal pair that has a larger level difference based on the current enable signal EnDfe and the feedback signal fb, so as to ensure that the second amplification circuit102receives a pair of differential signals with a larger signal level difference. Therefore, the accuracy of the first output signal Vout and the second output signal VoutN outputted by the second amplification circuit102can be enhanced, thereby improving the receiving performance of the data receiving system. When the impact of the intersymbol interference on the data receiving circuit100is not required to be considered, the enable signal EnDfe is set to be at the second level, and the second amplification circuit102keeps receiving the first signal pair based on the current enable signal EnDfe, so as to reduce the power consumption of the data receiving system.

Still another embodiment of the disclosure further provides a memory device, including: a plurality of data ports; and a plurality of data receiving systems provided in the another embodiment of the disclosure, each of which corresponds to a respective data port. Therefore, when the impact of the intersymbol interference on the memory device is required to be reduced, each data port in the memory device may flexibly adjust the received data signal DQ by using the data receiving system, and improve the ability of adjusting the first output signal Vout and the second output signal VoutN, so that the receiving performance of the memory device can be improved. When the impact of the intersymbol interference on the memory device is not required to be considered, the enable signal EnDfe is set to be at the second level, and the second amplification circuit102keeps receiving the first signal pair based on the current enable signal EnDfe, so as to reduce the power consumption of the memory device.

Those of ordinary skill in the art may understand that the above implementations are specific examples for realizing the disclosure, and in practical application, various changes may be made in form and details without departing from the spirit and the scope of the embodiments of the disclosure. Any person skilled in the art may make respective changes and modifications without departing from the spirit and scope of the embodiments of the disclosure. Therefore, the protection scope of the embodiments of the disclosure should be subject to the scope defined by the claims.