Patent ID: 12198008

DETAILED DESCRIPTION

The following detailed description is merely illustrative and is not intended to limit embodiments and/or application or uses of embodiments. Furthermore, there is no intention to be bound by any expressed or implied information presented in the preceding Background or Summary sections, or in the Detailed Description section.

One or more embodiments are now described with reference to the drawings, wherein like referenced numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of the one or more embodiments. It is evident, however, in various cases, that the one or more embodiments can be practiced without these specific details.

With reference now to the drawings,FIG.1illustrates a block diagram of a system100that facilitates frequency allocation in multi-qubit circuits according to one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity. As shown inFIG.1, system100includes a yield determination component110that determines an estimated fabrication yield associated with respective qubit chip configurations by conducting simulations of the respective qubit chip configurations at respective frequency offsets. In an aspect, the yield determination component110can utilize one or more statistical models that take into account the likelihood of frequency collisions between respective qubits in a given circuit to optimize qubit frequencies, qubit couplings, and/or other circuit parameters.

An example of a qubit circuit that can be analyzed by system100is shown by diagram200inFIG.2. As shown by diagram200, the respective qubits can be joined by respective quantum buses, here quantum buses that can be utilized to link two qubits per bus. Other bus configurations are also possible, as will be described in further detail below. In an aspect, the quantum buses of the qubit circuit shown in diagram200can be utilized to implement respective quantum gates between their respectively connected qubits. A specific, non-limiting example of a quantum gate that can be employed in the circuit shown by diagram200is a cross-resonance (CR) gate as described in Chow et al., “MULTIPLE-QUBIT WAVE-ACTIVATED CONTROL GATE,” U.S. Pat. No. 8,872,360, the entirety of which is hereby incorporated by reference. Other quantum gates could also be used.

In an aspect, qubits in a multi-qubit circuit, such as those shown by diagram200, can operate at different frequencies such that respective qubits in the system can be addressed by a quantum computer via their frequencies. However, if the frequencies of two or more qubits that are near each other physically (e.g., connected via the same quantum bus, etc.) are such that their frequencies result in a collision, the ability of the quantum computer to address individual ones of the qubits can be adversely impacted, resulting in degraded performance of the system. To mitigate this impact to system performance, respective qubits in a circuit can be designed such that respective qubits connected via a quantum bus and/or other means each operate at non-colliding frequencies. However, as noted above, imperfections in the qubit fabrication process can in some cases result in one or more qubits operating at frequencies other than their respective intended frequencies, which can in turn potentially result in frequency collisions between respective qubits in spite of the intended system design.

In an aspect, the yield determination component110can utilize a statistical model that includes one or more empirical inputs and one or more design inputs to reduce the amount of frequency collisions within a given multi-qubit circuit. By way of non-limiting example, empirical inputs to a statistical model as used by the yield determination component110can include collision window definitions, which can be determined via quantum modeling, measurement, and/or other techniques. Respective collision window definitions that can be utilized are described in further detail below with respect toFIG.6. Also or alternatively, the empirical inputs can include a measured statistical distribution of qubit frequencies. Various examples of distributions that can be utilized in this manner are described in further detail below with respect toFIGS.7-8.

By way of further specific, non-limiting example, design inputs to the statistical model can include the number of qubits in the circuit, the geometric arrangement of qubits in the circuit, and/or the function of the various qubits in the circuit, e.g., their use as data or ancilla in quantum error correction algorithms. One example of these design parameters is illustrated by the circuit shown in diagram200, as described above. Further examples of these parameters are described in further detail below with respect toFIGS.4-5.

As a further example, the design inputs can include the type(s) of respective qubits in the circuit, e.g., transmon, phase qubit, flux qubit, and/or another type of superconducting qubit. An additional example design input can include qubit anharmonicity, which is the deviation in frequency (e.g., in GHz or MHz) of a qubit or system of qubits from harmonic oscillation. Further example design inputs can include number of qubits per bus, intended qubit frequencies (e.g., given in GHz), desired fidelities for CR gates and/or other quantum gates, etc. Respective ones of the above-noted design inputs are described in further detail below.

In an aspect, the yield determination component110can model a multi-qubit circuit based on one or more of the above inputs to analyze performance of the circuit under various qubit frequency offsets, e.g., deviation from respective qubit frequencies as caused by fabrication error and/or other causes. As further shown byFIG.1, system100further includes a selection component120that selects a qubit chip configuration from among the respective qubit chip configurations based on the estimated fabrication yield associated with the respective qubit chip configurations as determined by the yield determination component110, e.g., via the statistical model constructed by the yield determination component110.

In an aspect, system100can improve the resilience of a multi-qubit circuit to frequency variations introduced during the fabrication process. By implementing the frequency allocation scheme corresponding to system100, performance of multi-qubit circuits and their respectively corresponding quantum computers can be improved, the fabrication yield of manufactured circuits can be improved, efficiency of multi-qubit circuit fabrication can be improved (e.g., by reducing the time and/or cost of fabricating physical circuits via mitigating frequency collisions in modeling and/or simulation as opposed to physical fabrication itself), and/or other benefits or advantages can be realized.

With reference next toFIG.3, a block diagram of a system300that facilitates qubit configuration for a multi-qubit circuit according to one or more embodiments described herein is illustrated. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity. As shown inFIG.3, system300includes a configuration component310that generates the respective qubit chip configurations utilized by the yield determination component110as described with respect toFIG.1above such that the qubit chip configurations differ from each other with respect to at least one of geometric configuration or frequency configuration.

In an aspect, the geometric configuration of a multi-qubit circuit can be defined at least in part by the total number of qubits in the circuit, the functionality of the respective qubits in the circuit (e.g., data or ancilla), and/or the number of qubits per bus in the circuit. By way of non-limiting example, the circuit illustrated by diagram200as described above contains 7 qubits that are linked via respective two-qubit buses, resulting in 8 gate pairs and qubit pairs. In another non-limiting example illustrated by diagram400inFIG.4, the eight two-qubit buses shown by diagram200can be replaced by two four-qubit buses, resulting in a configuration that offers twelve bus-coupled qubit pairs. The circuit shown by diagram400can employ two-qubit gates on the same eight pairs available in the circuit shown by diagram200, while having an additional4pairs available for gates. However, even if no gates are performed on these additional pairs, the presence of these connections can in some cases degrade circuit performance through frequency collisions among them. In a further non-limiting example illustrated by diagram500inFIG.5, a multi-qubit circuit can contain 16 qubits linked via respective two-qubit buses, resulting in a configuration that includes 22 gate pairs and qubit pairs.

Other geometric qubit configurations are possible. For instance, a multi-cubit circuit could contain different numbers of qubits, types of qubits (e.g., data or ancilla; transmon, CSFQ and/or other qubits; etc.), number of qubits per bus, or the like. A given circuit could also include mixes of different configurations. For instance, a circuit could include some qubits linked via two-qubit buses as shown byFIGS.2and5as well as other qubits linked via four-qubit buses as shown byFIG.4. While not shown, other bus types, such as three-qubit buses or the like, could also be used in addition to, or in place of, the bus types described above. In still another non-limiting example, qubit configurations can vary in terms of physical qubit placement. For instance, in place of the configuration shown inFIG.5that includes 2 rows of 8 qubits, the qubits could instead be placed in a square configuration of 4 rows of 4 qubits and/or in any other suitable configuration. Other configurations to those described above could also be used. Any number of qubits in any geometric arrangement can be incorporated into the circuit configuration as desired for a given quantum computing application. For instance, a circuit containing 400 qubits could comprise 2 rows of 200 qubits, or 20 rows of 20 qubits, employing 2 qubits per bus or 4 qubits per bus or some combination of 2 and 4 qubits per bus in a specified geometric arrangement.

In another aspect, the frequency configuration of a multi-qubit circuit can be defined at least in part by operational frequency ranges for respective qubits in the circuit and/or anharmonicity parameters associated with respective qubits in the circuit. Diagram600inFIG.6illustrates specific non-limiting example frequency ranges that can be employed by two qubits Q1and Q2. As shown in diagram600, f01denotes the first excitation frequency of the corresponding qubit and f12denotes the second excitation frequency. Further, the parameter δ denotes the anharmonicity of qubit Q1, e.g., the difference in frequency between the excitation frequencies f01and f12of qubit Q1. By way of non-limiting example, the anharmonicity δ of qubit Q1can be between −300 to −350 MHz for a transmon qubit. Other anharmonicity parameters are also possible.

Based on the frequency configurations of qubits Q1and Q2as shown by diagram600, respective types of collision windows can occur based on the anharmonicity δ of qubit Q1as well as the frequency separation Δ between qubits Q1and Q2. For instance, a first frequency collision type can occur when qubits Q1and Q2are on the same bus and share a common excitation frequency, e.g., such that |Δ|=0+/−a, where a is a collision window size (e.g., a=δ/20). A second frequency collision type between two qubits on the same bus can occur when the excitation frequency of the first qubit falls in the center of the excitation frequencies of the second qubit, e.g., |Δ|=−δ/2+/−a (e.g., where a=δ/80). A third frequency collision type between two qubits on the same bus can occur where the second excitation frequency of the first qubit collides with the first excitation frequency of the second qubit, e.g., |Δ|=−δ+/−a (e.g., where a=δ/20). A further frequency collision type can occur in a cross-resonance gate between qubits Q1and Q2if the difference in their excitation frequencies is sufficiently large, e.g., |Δ|>−1.05*δ.

It should be appreciated that the above collision types are provided merely as specific, non-limiting examples of collision types that could occur and that other collision types are possible. In an aspect, respective collision types can be defined in terms of 1) the frequency separation Δ between two qubits Q1and Q2, 2) the coupling between respective qubits, 3) the function of respective qubits in the circuit, 4) a desired gate fidelity, which can relate to the collision window size a, 5) the presence of additional qubits Q3, Q4, etc., coupled to Q1and/or Q2, and/or 6) any other suitable parameters.

In an aspect, the yield determination component110can further consider precision associated with fabricated qubit frequencies as an input to the statistical model described above. By way of example, the yield determination component110can directly measure the frequencies associated with a sample set of qubits to determine a frequency precision parameter.

Diagram700inFIG.7illustrates a histogram of the frequencies of 40 transmon-type qubits which were designed to be identical and fabricated to be identical according to a particular fabrication process. As shown by diagram700, imperfections in the fabrication process cause the respective qubits to exhibit significant variations in operating frequency. Here the 40 qubits vary in frequency with a standard deviation of approximately 230 MHz. The variation in operating frequency exhibited by the qubits in diagram700demonstrates that even small variations in physical dimensions introduced during fabrication can have a nontrivial impact on operating frequency.

By way of an additional example, the yield determination component110can also consider empirical measurements of the variation in qubit components which can thereby vary qubit frequency. For instance, a Josephson tunnel junction can be implemented in a transmon qubit, and imprecision in fabricating this component will lead to imprecision in the qubit frequency. Diagram800inFIG.8illustrates a histogram of the resistances of a set of such tunnel junctions which were designed and fabricated by a particular fabrication process to have identical tunnel barrier resistances. As shown by diagram800, imperfections in the fabrication process cause a variation in their resistances. From this variation, a variation can be predicted in any qubits that would be fabricated using this particular junction fabrication process.

With reference next toFIG.9, a diagram of an iterative process900for generating a qubit chip configuration according to various embodiments described herein is illustrated. While not shown inFIG.9for simplicity of illustration, it should be appreciated that the respective stages in process900can be implemented via a device operatively coupled to a processor, e.g., a processor utilized to implement the yield determination component110, selection component120, and/or configuration component310, and/or another suitable computing device. In an aspect, the diagram shown byFIG.9can further incorporate elements of the configuration component310and/or yield determination component110as described above with respect toFIGS.1and3, and/or one or more components as will be discussed below with respect toFIGS.10-13. It should be appreciated that the diagram shown byFIG.9offers an alternate representation of the process flow between such components.

In an aspect, process900can begin at stage902by determining (e.g., via the configuration component310) a qubit geometric layout. As shown inFIG.9, the qubit geometric layout can include factors such as a total number of qubits, functionality of respective qubits (e.g., data or ancilla), a number of qubits per bus, and/or other suitable factors as described above. Respective qubit geometric layouts that can be determined at stage902can include geometric layouts that are similar to those described above with respect toFIGS.2,4and5, and/or other suitable layouts comprising as many qubits as desired in any geometric arrangement desired for a given quantum computing circuit and application.

Next, at stage904, a qubit frequency layout corresponding to the qubit geometric layout determined at stage902can be determined (e.g., by the configuration component310). In an aspect, the qubit frequency layout determined at stage904can take into account the frequency properties of the respective qubits utilized in the geometric layout, e.g., the frequency properties described above with respect toFIG.6and/or other suitable properties. In another aspect, the frequency layout determined at stage904can utilize one or more fixed-frequency qubits and/or one or more tunable-frequency qubits.

At stage906, random frequency offset(s) can be assigned (e.g., by the configuration component310) at the qubits corresponding to the geometric and frequency layouts determined at stages902and904, respectively. As shown byFIG.9, the random frequency offsets assigned at stage906can be derived, at least in part, via a random number generator that utilizes one or more algorithms for random and/or pseudorandom number generation as known in the art. Also or alternatively, the frequency offsets assigned at stage906can be at least partially based on empirically measured frequency imprecision from one or more other simulations and/or sample fabrication runs, such as, e.g., the measurement data illustrated byFIGS.7-8. In an aspect, the frequency offsets applied at stage906can be utilized to mimic the performance of a real qubit device in a simulated setting, thereby accommodating factors such as variations in physical dimensions and fabrication imprecision as generally described above.

At stage908, the performance of a simulated qubit circuit generated according to the layouts determined at stages902and904and the frequency offsets assigned at stage906can be analyzed (e.g., by the yield determination component110), and frequency collisions associated with the simulated circuit can be counted. In an aspect, collisions can be counted at stage908at least in part by defining frequency collision windows for respective qubits in the respective qubit configurations determined at stages902and904and counting the frequency collisions according to those frequency collision windows. Also or alternatively, parameters such as qubit anharmonicity, desired gate metrics, and/or other suitable metrics (e.g., other metrics as described above with respect toFIG.6) could be used in counting frequency collisions at908.

At stage910, stages902-908can be repeated (e.g., by the configuration component310and/or the yield determination component110) over a desired number N (e.g., where N≥104, etc.) of iterations. Based on these iterations, a statistical prediction of device yield (i.e., an estimated fabrication yield) can be determined (e.g., by the yield determination component110) based on the number of frequency collisions observed at stage908of the respective iterations. In an aspect, the predicted device yield can be based on a calculated probability of zero collisions for a parameter set corresponding to a given iteration of stages902-908, and/or other factors. Briefly returning toFIG.1, an embodiment of system100in which the yield determination component110determines estimated device yield in the manner described with respect to stage910of process900can have the advantage of facilitating adjustment of respective qubit chip configurations by the yield determination component110to account for the frequency collisions observed at stage908.

At the conclusion of the desired number of iterations at stage910, process900can proceed to stage912, in which stages902-910are repeated (e.g., by the configuration component310and/or the yield determination component110) with adjustments to geometric layout, number of qubits, number of qubits per bus, frequency layout, and/or other parameters described above. In this manner, qubit parameters can be refined and estimated yield can be improved via iteration at stage912until a specified number of iterations and/or a desired device yield is reached. At the conclusion of stage912, a set of qubit parameters that resulted in at least a threshold device yield, or a highest device yield, can be selected (e.g., by the selection component120) for fabrication and/or other purposes.

Turning toFIG.10, a block diagram of a system1000for fabricating a superconducting qubit chip1002according to various embodiments described herein is illustrated. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity. As shown inFIG.10, system1000includes a yield determination component110and a selection component120for simulating qubit chip configurations and selecting a desired configuration, respectively, as described in accordance with various aspects above, as well as in accordance with the process described inFIG.9.

In addition, system1000includes a fabrication component1010that fabricates a superconducting qubit chip1002according to a qubit chip configuration selected by the selection component120. The fabrication component1010can be associated with a same computing device or combination of computing devices as the yield determination component110and the selection component120and/or a separate device. For instance, the fabrication component1010can be associated with one or more dedicated fabrication devices that are operable to receive a selected configuration from a device associated with the selection component120and fabricate a corresponding qubit chip1002according to the selected configuration using one or more techniques for qubit chip fabrication as known in the art. In an aspect, by simulating respective qubit chip specifications and/or configurations and selecting a configuration based on the simulation, the qubit chip configuration selected by the selection component120can result in improved resilience of the superconducting qubit chip1002to imperfections in fabrication by the fabrication component1010.

With reference next toFIG.11, a block diagram of an alternative system1100that facilitates frequency allocation in multi-qubit circuits according to various embodiments described herein is illustrated. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity. In an aspect, system1100as shown inFIG.11provides an alternative representation of part of the process described inFIG.9for determining frequency allocation in multi-qubit circuits. As shown inFIG.11, system1100includes a performance analysis component1110that determines operation metrics for respective qubit chip features by analyzing simulated performance of the respective qubit chip features at respective frequency offsets. The qubit chip features utilized by the performance analysis component1110can include, but are not limited to, geometric features such as a total number of qubits, functionality of respective qubits (e.g., data or ancilla, etc.), a number of qubits per bus, or the like. Also or alternatively, the qubit chip features can include, but are not limited to, frequency features such as operational frequency ranges for respective qubits, anharmonicity parameters associated with respective qubits, whether respective qubits have a fixed frequency or a tunable frequency, etc.

In an aspect, the performance analysis component1110can analyze performance of a simulated qubit chip with a complete set of assigned parameters, e.g., in a similar manner to that described above with respect toFIG.9. Alternatively, the performance analysis component1110can analyze performance of one or more individual qubits with respect to a complete set of parameters or a partial set of parameters. For instance, the performance analysis component1110could in some cases analyze performance associated with respective geometric qubit layouts without respect to particular frequency layouts, or vice versa. The performance analysis component could also or alternatively analyze performance associated with one or more qubits that form a portion of a qubit circuit that includes additional, non-analyzed qubits. Other analysis techniques could also be used.

As further shown byFIG.11, system1100further includes a design generation component1120that generates a superconducting qubit chip design using one or more of the respective qubit chip features analyzed by the performance analysis component1110based on the corresponding operation metrics determined by the performance analysis component1110. In an aspect, the design generation component1120can select a qubit chip design based on respective designs analyzed by the performance analysis component1110. Alternatively, the performance analysis component1110can analyze performance of respective qubit circuit parameters (e.g., geometric configuration, frequency configuration, etc.), such that the design generation component1120can construct a qubit chip design based on the individual parameters utilized by the performance analysis component1110. In another example, the performance analysis component1110can analyze performance associated with one or more portions or sub-circuits of a given qubit circuit, and the design generation component1120can construct a qubit chip design based on one or more sub-circuits analyzed by the performance analysis component1110and/or predefined sub-circuits, e.g., known efficient sub-circuit designs stored by a memory or data store associated with a computing device that implements system1100. Other techniques are also possible.

Turning toFIG.12, a block diagram of a system1200that facilitates frequency allocation in multi-qubit circuits via simulated collision monitoring according to various embodiments described herein is illustrated. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity. In an aspect, system1200as shown inFIG.12provides an alternative representation portions of the collision monitoring and design procedures depicted inFIG.9. As shown inFIG.12, system1200includes a collision monitoring component1210associated with the performance analysis component1110that can identify and/or otherwise monitor frequency collisions associated with simulations and/or other operations carried out by the performance analysis component1110. In an aspect, the collision monitoring component1210can define frequency collision windows for respective qubits corresponding to the qubit chip features analyzed by the performance analysis component1110, e.g., such as one or more of the collision windows as described above with respect toFIG.6and/or other collision windows as appropriate. The collision monitoring component1210can then identify collisions between the respective qubits based on the defined frequency collision windows. The collision monitoring component can employ repeated trials introducing statistical variation of parameters into the model in order to derive a probability of collisions occurring and probability of device yield, as depicted alternatively inFIG.9.

With reference now toFIG.13, a block diagram of an alternative system1300for fabricating a superconducting qubit chip1002according to various embodiments described herein is illustrated. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity. As shown inFIG.13, system1300includes a performance analysis component1110and a design generation component1120that can generate a qubit chip design as described above with respect toFIGS.11-12and with respect to the alternative depiction of this process as shown inFIG.9. Additionally, system1300includes a fabrication component1310that can fabricate a superconducting qubit chip1002according to the superconducting qubit chip design generated by the design generation component1120. In an aspect, the fabrication component1310can operate similarly to the fabrication component1010shown in system1000and/or differently. For instance, the type or nature of information obtained by the fabrication component1310from the design generation component1120can be different than that of corresponding information received by the fabrication component1010of system1000from the selection component120, and the fabrication component1310can utilize various techniques to account for these differences. Similar to the fabrication component1010of system1000as described above, the fabrication component1310of system1300can be implemented via a same device as the performance analysis component1110and/or the design generation component1120and/or a different device.

In an aspect, a superconducting qubit chip1002resulting from operation of the fabrication component1310can be similar in functionality to that produced by the fabrication component1010of system1000. In another aspect, the fabrication component1310can produce superconducting qubit chip1002with improved resilience to imperfections in fabrication by the fabrication component1310by utilizing the qubit design generated by the design generation component1120.

Referring next toFIG.14, a processing component1400that can be utilized to implement one or more aspects described herein is illustrated in accordance with one or more embodiments. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

As shown inFIG.14, the processing component1400can be associated with at least one processor1410(e.g., a central processing unit, a graphical processing unit, etc.), which can be utilized to implement one or more of the yield determination component110and/or selection component120as described above. The processor(s)1410can be connected via a data bus1420to one or more additional sub-components of the processing component1400, such as a communication component1430and/or a memory1440. While the communication component1430is illustrated as implemented separately from the processor(s)1410, the processor(s)1410in some embodiments can additionally be used to implement the communication component1430. In still other embodiments, the communication component1430can be external to the processing component1400and communicate with the processing component1400via a separate communication link.

The memory1440can be utilized by the processing component1400to store data utilized by the processing component1400in accordance with one or more embodiments described herein. Additionally or alternatively, the memory1440can have stored thereon machine-readable instructions that, when executed by the processing component1400, cause the processing component (and/or one or more processors1410thereof) to implement the yield determination component110and/or selection component120as described above.

FIG.15illustrates another processing component1500that can be utilized to implement one or more aspects described herein in accordance with one or more embodiments. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

As shown inFIG.15, the processing component1500can be associated with at least one processor1510, which can be utilized to implement one or more of the performance analysis component1110and/or design generation component1120as described above. The processor(s)1510can be connected via a data bus1520to one or more additional sub-components of the processing component1500, such as a communication component1530and/or a memory1540. In an aspect, the communication component1530can be configured in a similar manner to the communication component1430described above with respect toFIG.14.

Similar to the memory1440described above with respect toFIG.14, the memory1540can be utilized by the processing component1500to store data utilized by the processing component1500in accordance with one or more embodiments described herein. Additionally or alternatively, the memory1540can have stored thereon machine-readable instructions that, when executed by the processing component1500, cause the processing component (and/or one or more processors1510thereof) to implement the performance analysis component1110and/or design generation component1120as described above.

In various embodiments, the processing components1400,1500shown inFIGS.14-15can be or include hardware, software (e.g., a set of threads, a set of processes, software in execution, etc.) or a combination of hardware and software that performs a computing task (e.g., a computing task associated with received data). For example, processing components1400,1500can perform simulations of large and/or complex multi-qubit circuits and/or perform other operations that cannot be performed by a human (e.g., are greater than the capability of a human mind). For example, the amount of data processed, the speed of processing of the data and/or the data types processed by processing components1400,1500over a certain period of time can be respectively greater, faster and different than the amount, speed and data type that can be processed by a single human mind over the same period of time. For example, data processed by processing components1400,1500can be raw data (e.g., raw textual data, raw numerical data, etc.) and/or compressed data (e.g., compressed textual data, compressed numerical data, etc.) associated with one or more computing devices. Moreover, processing components1400,1500can be fully operational towards performing one or more other functions (e.g., fully powered on, fully executed, etc.) while also processing the above-referenced data.

FIG.16illustrates a flow diagram of an example, non-limiting computer-implemented method1600that facilitates frequency allocation in multi-qubit circuits according to one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

At1602, a device operatively coupled to a processor (e.g., processor(s)1410of a processing component1400) can determine (e.g., by a yield determination component110) an estimated fabrication yield associated with respective qubit chip configurations by conducting simulations of the respective qubit chip configurations at respective frequency offsets.

At1604, the device can select (e.g., by a selection component120) a qubit chip configuration from among the respective qubit chip configurations utilized at1602based on the estimated fabrication yield associated with the respective qubit chip configurations as further determined at1602.

In an aspect, method1600can conclude upon selection of a qubit chip configuration at1604. In another aspect, method1600can optionally continue to1606, in which the device, or a second device operatively coupled to a processor, can fabricate (e.g., by a fabrication component1010) a superconducting qubit chip according to the qubit chip configuration selected at1604.

FIG.17illustrates a flow diagram of an alternative example, non-limiting computer-implemented method1700that facilitates frequency allocation in multi-qubit circuits according to one or more embodiments described herein. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

At1702, a device operatively coupled to a processor (e.g., processor(s)1510of a processing component1500) can determine (e.g., by a performance analysis component1110) operation metrics for respective qubit chip features by analyzing simulated performance of the respective qubit chip features at respective frequency offsets.

At1704, the device can generate (e.g., by a design generation component1120) a superconducting chip design using one or more of the respective qubit features based on their respectively corresponding operation metrics.

In an aspect, method1700can conclude upon generation of a qubit chip design at1704. In another aspect, method1700can optionally continue to1706, in which the device, or a second device operatively coupled to a processor, can fabricate (e.g., by a fabrication component1310) a superconducting qubit chip according to the qubit chip design generated at1704.

For simplicity of explanation, the computer-implemented methodologies are depicted and described as a series of acts. It is to be understood and appreciated that the subject innovation is not limited by the acts illustrated and/or by the order of acts, for example acts can occur in various orders and/or concurrently, and with other acts not presented and described herein. Furthermore, not all illustrated acts can be required to implement the computer-implemented methodologies in accordance with the disclosed subject matter. In addition, those skilled in the art will understand and appreciate that the computer-implemented methodologies can alternatively be represented as a series of interrelated states via a state diagram or events. Additionally, it should be further appreciated that the computer-implemented methodologies disclosed hereinafter and throughout this specification are capable of being stored on an article of manufacture to facilitate transporting and transferring such computer-implemented methodologies to computers. The term article of manufacture, as used herein, is intended to encompass a computer program accessible from any computer-readable device or storage media.

Moreover, because configuration of data packet(s) and/or communication between processing components is established from a combination of electrical and mechanical components and circuitry, a human is unable to replicate or perform the subject data packet configuration and/or the subject communication between processing components. For example, a human is unable to generate data for transmission over a wired network and/or a wireless network between processing components, etc. Moreover, a human is unable to packetize data that can include a sequence of bits corresponding to information generated during one or more processes as described above, transmit data that can include a sequence of bits corresponding to information generated during one or more processes as described above, etc.

In order to provide a context for the various aspects of the disclosed subject matter,FIG.18as well as the following discussion are intended to provide a general description of a suitable environment in which the various aspects of the disclosed subject matter can be implemented.FIG.18illustrates a block diagram of an example, non-limiting operating environment in which one or more embodiments described herein can be facilitated. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity. With reference toFIG.18, a suitable operating environment1800for implementing various aspects of this disclosure can also include a computer1812. The computer1812can also include a processing unit1814, a system memory1816, and a system bus1818. The system bus1818couples system components including, but not limited to, the system memory1816to the processing unit1814. The processing unit1814can be any of various available processors. Dual microprocessors and other multiprocessor architectures also can be employed as the processing unit1814. The system bus1818can be any of several types of bus structure(s) including the memory bus or memory controller, a peripheral bus or external bus, and/or a local bus using any variety of available bus architectures including, but not limited to, Industrial Standard Architecture (ISA), Micro-Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Firewire (IEEE 1394), and Small Computer Systems Interface (SCSI). The system memory1816can also include volatile memory1820and nonvolatile memory1822. The basic input/output system (BIOS), containing the basic routines to transfer information between elements within the computer1812, such as during start-up, is stored in nonvolatile memory1822. By way of illustration, and not limitation, nonvolatile memory1822can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, or nonvolatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM). Volatile memory1820can also include random access memory (RAM), which acts as external cache memory. By way of illustration and not limitation, RAM is available in many forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM.

Computer1812can also include removable/non-removable, volatile/non-volatile computer storage media.FIG.18illustrates, for example, a disk storage1824. Disk storage1824can also include, but is not limited to, devices like a magnetic disk drive, solid state drive, floppy disk drive, tape drive, Jaz drive, Zip drive, LS-100 drive, flash memory card, or memory stick. The disk storage1824also can include storage media separately or in combination with other storage media including, but not limited to, an optical disk drive such as a compact disk ROM device (CD-ROM), CD recordable drive (CD-R Drive), CD rewritable drive (CD-RW Drive), a digital versatile disk ROM drive (DVD-ROM), or a Blu-ray disc drive. To facilitate connection of the disk storage1824to the system bus1818, a removable or non-removable interface is typically used, such as interface1826.FIG.18also depicts software that acts as an intermediary between users and the basic computer resources described in the suitable operating environment1800. Such software can also include, for example, an operating system1828. Operating system1828, which can be stored on disk storage1824, acts to control and allocate resources of the computer1812. System applications1830take advantage of the management of resources by operating system1828through program modules1832and program data1834, e.g., stored either in system memory1816or on disk storage1824. It is to be appreciated that this disclosure can be implemented with various operating systems or combinations of operating systems. A user enters commands or information into the computer1812through input device(s)1836. Input devices1836include, but are not limited to, a pointing device such as a mouse, trackball, stylus, touch pad, keyboard, microphone, joystick, game pad, satellite dish, scanner, TV tuner card, digital camera, digital video camera, web camera, and the like. These and other input devices connect to the processing unit1814through the system bus1818via interface port(s)1838. Interface port(s)1838include, for example, a serial port, a parallel port, a game port, and a universal serial bus (USB). Output device(s)1840use some of the same type of ports as input device(s)1836. Thus, for example, a USB port can be used to provide input to computer1812, and to output information from computer1812to an output device1840. Output adapter1842is provided to illustrate that there are some output devices1840like monitors, speakers, and printers, among other output devices1840, which require special adapters. The output adapters1842include, by way of illustration and not limitation, video and sound cards that provide a means of connection between the output device1840and the system bus1818. It should be noted that other devices and/or systems of devices provide both input and output capabilities such as remote computer(s)1844.

Computer1812can operate in a networked environment using logical connections to one or more remote computers, such as remote computer(s)1844. The remote computer(s)1844can be a computer, a server, a router, a network PC, a workstation, a microprocessor based appliance, a peer device or other common network node and the like, and typically can also include many or all of the elements described relative to computer1812. For purposes of brevity, only a memory storage device1846is illustrated with remote computer(s)1844. Remote computer(s)1844is logically connected to computer1812through a network interface1848and then physically connected via communication connection1850. Network interface1848encompasses wire and/or wireless communication networks such as local-area networks (LAN), wide-area networks (WAN), cellular networks, etc. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring and the like. WAN technologies include, but are not limited to, point-to-point links, circuit switching networks like Integrated Services Digital Networks (ISDN) and variations thereon, packet switching networks, and Digital Subscriber Lines (DSL). Communication connection(s)1850refers to the hardware/software employed to connect the network interface1848to the system bus1818. While communication connection1850is shown for illustrative clarity inside computer1812, it can also be external to computer1812. The hardware/software for connection to the network interface1848can also include, for exemplary purposes only, internal and external technologies such as, modems including regular telephone grade modems, cable modems and DSL modems, ISDN adapters, and Ethernet cards.

Various embodiments of the present can be a system, a method, an apparatus and/or a computer program product at any possible technical detail level of integration. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out one or more aspects of the present invention. The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium can also include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device. Computer readable program instructions for carrying out operations of one or more embodiments of the present invention can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuitry, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++, or the like, and procedural programming languages, such as the “C” programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform one or more aspects of the present invention.

One or more aspects of the present invention are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to one or more embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions. These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks. The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational acts to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams can represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the Figures. For example, two blocks shown in succession can, in fact, be executed substantially concurrently, or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.

While portions of the subject matter have been described above in the general context of computer-executable instructions of a computer program product that runs on a computer and/or computers, those skilled in the art will recognize that this disclosure also can or can be implemented in combination with other program modules. Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks and/or implement particular abstract data types. Moreover, those skilled in the art will appreciate that the inventive computer-implemented methods can be practiced with other computer system configurations, including single-processor or multiprocessor computer systems, mini-computing devices, mainframe computers, as well as computers, hand-held computing devices (e.g., PDA, phone), microprocessor-based or programmable consumer or industrial electronics, and the like. The illustrated aspects can also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. However, some, if not all aspects of this disclosure can be practiced on stand-alone computers. In a distributed computing environment, program modules can be located in both local and remote memory storage devices.

As used in this application, the terms “component,” “system,” “platform,” “interface,” and the like, can refer to and/or can include a computer-related entity or an entity related to an operational machine with one or more specific functionalities. The entities disclosed herein can be either hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a server and the server can be a component. One or more components can reside within a process and/or thread of execution and a component can be localized on one computer and/or distributed between two or more computers. In another example, respective components can execute from various computer readable media having various data structures stored thereon. The components can communicate via local and/or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and/or across a network such as the Internet with other systems via the signal). As another example, a component can be an apparatus with specific functionality provided by mechanical parts operated by electric or electronic circuitry, which is operated by a software or firmware application executed by a processor. In such a case, the processor can be internal or external to the apparatus and can execute at least a part of the software or firmware application. As yet another example, a component can be an apparatus that provides specific functionality through electronic components without mechanical parts, wherein the electronic components can include a processor or other means to execute software or firmware that confers at least in part the functionality of the electronic components. In an aspect, a component can emulate an electronic component via a virtual machine, e.g., within a cloud computing system.

In addition, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless specified otherwise, or clear from context, “X employs A or B” is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then “X employs A or B” is satisfied under any of the foregoing instances. Moreover, articles “a” and “an” as used in the subject specification and annexed drawings should generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form. As used herein, the terms “example” and/or “exemplary” are utilized to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. In addition, any aspect or design described herein as an “example” and/or “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor is it meant to preclude equivalent exemplary structures and techniques known to those of ordinary skill in the art.

As it is employed in the subject specification, the term “processor” can refer to substantially any computing processing unit or device comprising, but not limited to, single-core processors; single-processors with software multithread execution capability; multi-core processors; multi-core processors with software multithread execution capability; multi-core processors with hardware multithread technology; parallel platforms; and parallel platforms with distributed shared memory. Additionally, a processor can refer to an integrated circuit, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), a discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Further, processors can exploit nano-scale architectures such as, but not limited to, molecular and quantum-dot based transistors, switches and gates, in order to optimize space usage or enhance performance of user equipment. A processor can also be implemented as a combination of computing processing units. In this disclosure, terms such as “store,” “storage,” “data store,” data storage,” “database,” and substantially any other information storage component relevant to operation and functionality of a component are utilized to refer to “memory components,” entities embodied in a “memory,” or components comprising a memory. It is to be appreciated that memory and/or memory components described herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of illustration, and not limitation, nonvolatile memory can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or nonvolatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM). Volatile memory can include RAM, which can act as external cache memory, for example. By way of illustration and not limitation, RAM is available in many forms such as synchronous RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), direct Rambus RAM (DRRAM), direct Rambus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM). Additionally, the disclosed memory components of systems or computer-implemented methods herein are intended to include, without being limited to including, these and any other suitable types of memory.

What has been described above include mere examples of systems and computer-implemented methods. It is, of course, not possible to describe every conceivable combination of components or computer-implemented methods for purposes of describing this disclosure, but one of ordinary skill in the art can recognize that many further combinations and permutations of this disclosure are possible. Furthermore, to the extent that the terms “includes,” “has,” “possesses,” and the like are used in the detailed description, claims, appendices and drawings such terms are intended to be inclusive in a manner similar to the term “comprising” as “comprising” is interpreted when employed as a transitional word in a claim. The descriptions of the various embodiments have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Various modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.