Patent ID: 12213323

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

An integrated circuit may comprise, in some embodiments, multiple transistor devices arranged over a same substrate. In some configurations, an interconnect structure may be arranged over the one or more transistor devices on a frontside of the same substrate. The interconnect structure may comprise a network of interconnect wires and interconnect vias embedded in an interconnect dielectric structure. The interconnect wires and interconnect vias may be electrically coupled to one or more of the multiple transistor devices.

In integrated circuits comprising memory devices, a memory structure (e.g., a magnetoresistive random-access memory cell, a metal-insulator-metal memory cell, a ferroelectric random-access memory cell, a phase-change random-access memory cell, resistive random access memory cell, etc.) may be arranged within the interconnect structure and coupled to at least one of the multiple transistor devices. However, due to physical and/or electrical limitations to prevent signal interference, for example, the memory structure may be conventionally arranged between interconnect wires5and6. Because so many interconnect wires and interconnect vias are arranged between the memory structure and the one or more multiple transistors, the height of the integrated circuit is increased which decreases device density and the distance for a signal to travel between the memory structure and the one or more multiple transistors may be inefficient.

Various embodiments of the present disclosure are directed towards an integrated chip comprising a first transistor and a second transistor spaced apart by a second source/drain region and arranged over a carrier substrate. In some embodiments, the first and second transistors may be nanosheet field effect transistors (NSFET), fin field effect transistors (finFET), or some other type of transistor. A first interconnect structure is arranged between the carrier substrate and the first and second transistors. A contact plug structure is arranged directly over and electrically coupled to the second source/drain region, and a memory structure is arranged directly over and electrically coupled to the contact plug structure. In some embodiments, a second interconnect structure may be arranged directly over and coupled to the memory structure.

Thus, in various embodiments of the present disclosure, a frontside and a backside of the first and second transistors are utilized to reduce the first and/or second interconnect structures dimensions in the vertical direction to increase device density. Further, the contact plug structure is arranged directly between the first and/or second transistors and the memory structure, thereby reducing the distance for a signal traveling between the first and/or second transistors and the memory structure to increase the reliability of the integrated chip.

FIG.1illustrates a cross-sectional view100of some embodiments of an integrated chip comprising a memory structure arranged above nanosheet field effect transistors (NSFETs) and a first interconnect structure arranged below the NSFETs.

The integrated chip of the cross-sectional view100includes a first interconnect structure107arranged over a carrier substrate102. In some embodiments, the first interconnect structure107is bonded to the carrier substrate102through a first bonding layer104and a second bonding layer106. The first interconnect structure107may comprise interconnect wires110and interconnect vias108arranged within interconnect dielectric layers112and interconnect etch stop layers114. In some embodiments, from the perspective of the cross-sectional view100ofFIG.1, wherein the first interconnect structure107is arranged above the carrier substrate102, the interconnect vias108of the first interconnect structure107may each have an upper surface that is narrower than its bottom surface.

In some embodiments, a first nanosheet field effect transistor (NSFET)118is arranged over the first interconnect structure107, and a second NSFET120is arranged over the first interconnect structure107and beside the first NSFET118. In some embodiments, the first and second NSFETs each comprise a channel structure121comprising nanosheet channel structures122, and a gate electrode124arranged between the nanosheet channel structures122. The gate electrode124comprises portions arranged directly between the nanosheet channel structures122and a portion arranged below a bottommost one of the nano sheet channel structures122and coupled to one of the interconnect vias108of the first interconnect structure107. In some embodiments, inner spacer structures128surround outer sidewalls of the portions of the gate electrode124arranged directly between the nanosheet channel structures122. Further, in some embodiments, a first gate sidewall structure132is arranged on outer sidewalls of the portion of the gate electrode124arranged directly between the bottommost one of the nanosheet channel structures122and the first interconnect structure107, and a second gate sidewall structure130is arranged directly on outer sidewalls of the first gate sidewall structure132. Further, in some embodiments, first and second gate sidewall structures132,130are arranged within and laterally surrounded by a gate dielectric layer116.

In some embodiments, the first NSFET118comprises a first source/drain region126aand a second source/drain region126b, wherein the nanosheet channel structures122of the first NSFET118extend between the first and second source/drain regions126a,126b. In some embodiments, the second NSFET120comprises the second source/drain region126band a third source/drain region126c, wherein the nanosheet channel structures122of the second NSFET120extend between the second and third source/drain regions126b,126c. Thus, in some embodiments, the first and second NSFETs118,120share the second source/drain region126b. Further, in some embodiments, the first, second, and third source/drain regions126a,126b,126care separated from the first interconnect structures107by the gate dielectric layer116.

In some embodiments, the first and second NSFETs118,120respectively comprise a protection layer134arranged over a topmost one of the nanosheet channel structures122. In such embodiments, the protection layer134may be centered over and comprise a substantially same width as the topmost one of the nanosheet channel structures122. In some embodiments, the protection layer134may comprise, for example, a dielectric material such as silicon nitride, silicon oxynitride, silicon carbide, silicon nitrogen carbide, or some other suitable dielectric material. Thus, in some embodiments, the topmost one of the nanosheet channel structures122has a bottom surface that directly contacts the gate electrode124and a top surface that directly contacts the protection layer134.

In some embodiments, the integrated chip ofFIG.1further comprises a contact dielectric layer140arranged over the first and second NSFETs118,120and a contact plug structure138that extends through the contact dielectric layer140and directly contacts the second source/drain region126b. Thus, in some embodiments, the contact plug structure138is electrically coupled to the first and second NSFETs118,120. Further, in some embodiments, the contact plug structure138directly overlies the protection layers134of the first and second NSFETs118,120and also extends below the protection layers134of the first and second NSFETs118,120. In some embodiments, the contact plug structure138is also arranged directly between topmost ones of the nanosheet channel structures122of the first and second NSFETs118,120. In some embodiments, a barrier structure136is arranged directly between the contact plug structure138and the topmost ones of the nanosheet channel structures122of the first and second NSFETs118,120to provide protection to the topmost ones of the nanosheet channel structures122of the first and second NSFETs118,120during formation of the contact plug structure138. Similarly, in some embodiments, the protection layers134provide protection to the nanosheet channel structures122during the formation of the contact plug structure138. In some embodiments, the contact plug structure138comprises a conductive material such as, for example, tungsten, ruthenium, cobalt, or some other conductive material with a low resistivity. In some embodiments, the contact plug structure138has a first height h1extending between the memory structure142and the second source/drain region126b. In some embodiments, the first height h1may be in a range of between, for example, approximately 10 nanometers and approximately 300 nanometers.

In some embodiments, a memory structure142is arranged directly over the contact plug structure138such that the contact plug structure138electrically couples the memory structure142to the first and second NSFETs118,120. In some embodiments, the memory structure142may comprise a bottom electrode144arranged over the contact plug structure138, a top electrode148arranged over the bottom electrode144, and a memory storage structure146arranged between the bottom and top electrodes144,148. In some embodiments, the memory structure142may comprise a magnetoresistive random-access memory cell, a metal-insulator-metal memory cell, a ferroelectric random-access memory cell, a phase-change random-access memory cell, a resistive random-access memory cell, or some other memory device. In some embodiments, the memory structure142is surrounded by a memory dielectric structure143arranged over the contact dielectric layer140.

In some embodiments, a second interconnect structure150may be arranged over and coupled to the memory structure142. In such embodiments, the second interconnect structure150may comprise interconnect wires110and interconnect vias108embedded in interconnect dielectric layers112and interconnect etch stop layers114. In some embodiments, from the perspective of the cross-sectional view100ofFIG.1, wherein the second interconnect structure150is arranged above the memory structure142and the carrier substrate102, the interconnect vias108of the second interconnect structure150may each have an upper surface that is wider than its bottom surface.

Thus, in some embodiments, the memory structure142is arranged above the first and second NSFETs118,120, and the first interconnect structure107is arranged below the first and second NSFETs118,120, such that both sides of the first and second NSFETs118,120are being utilized, thereby reducing the height of the overall integrated chip inFIG.1. Further, in some embodiments, the contact plug structure138is arranged directly between the memory structure142and the first and second NSFETs118,120to reduce the distance for signals (e.g., current, voltage) to travel between the first and/or second NSFETs118,120and the memory structure142, thereby increasing the signal traveling efficiency and overall reliability of the integrated chip.

FIG.2Aillustrates a cross-sectional view200A of some other embodiments of an integrated chip comprising a memory structure arranged above NSFETs and a first interconnect structure arranged below the NSFETs.

As shown in cross-sectional view200A ofFIG.2A, in some embodiments, the memory structure142ofFIG.1may correspond to a magnetoresistive random-access memory (MRAM) cell or device. In such embodiments, a magnetic tunnel junction (MTJ) stack202may be arranged between the top electrode148and the bottom electrode144. In some embodiments, the MTJ stack202may comprise a thin insulating layer208arranged between a bottom magnetic layer204and a top magnetic layer206. Data may be stored in the MTJ stack202using magnetic orientations of the MTJ stack202. In some embodiments, a first MRAM sidewall structure210may be arranged on outer sidewalls of the memory structure142, and a second MRAM sidewall structure212may be arranged on outer sidewalls of the first MRAM sidewall structure210and/or the outer sidewalls of the memory structure142.

In some embodiments, a silicide layer216is arranged directly between the contact plug structure138and the second source/drain region126b. In some embodiments, the silicide layer216may comprise, for example, cobalt silicide, titanium silicide, nickel silicide, or some other suitable metallic silicide material. In such embodiments, the silicide layer216may aid in coupling the second source/drain region126bto the contact plug structure138.

In some embodiments, the first bonding layer104and not the second bonding layer (106ofFIG.1) is arranged directly between the carrier substrate102and the first interconnect structure107. Further, in some embodiments, the first interconnect structure107may be electrically coupled to the second interconnect structure150. In such embodiments, an elongated via structure214may extend through the dielectric layers (e.g., interconnect dielectric layers112, gate dielectric layer116, contact dielectric layer140, memory dielectric structure143, etc.) to directly couple the first interconnect structure107to the second interconnect structure150. It will be appreciated that in other embodiments, multiple wires and vias and/or some other structure(s) may be used to directly couple the first and second interconnect structures107,150.

FIG.2Billustrates a cross-sectional view200B of some alternative embodiments of the cross-sectional view200A ofFIG.2A, wherein the integrated chip comprising fin field effect transistors (finFETs) instead of NSFETs.

As shown in the cross-sectional view200B ofFIG.2B, in some embodiments, the integrated chip comprises a first finFET218and a second finFET220arranged over the first interconnect structure107and below the memory structure142. In such embodiments, the first finFET218and the second finFET220may each comprise a fin channel structure224that continuously extends between the gate electrode124and the protection layer134. In some embodiments, the first and second finFETs218,220may be used instead of the first and second NSFETs (118,120ofFIG.1) to reduce manufacturing complexity; however, in some embodiments, the first and second NSFETs (118,120ofFIG.1) may provide certain advantages over the first and second finFETs218,220such as, for example, faster switching speeds.

FIGS.3-23illustrate cross-sectional views300-2300of some embodiments of a method of forming a first interconnect structure below nanosheet field effect transistors (NSFETs) and a memory structure above the NSFETs. AlthoughFIGS.3-23are described in relation to a method, it will be appreciated that the structures disclosed inFIGS.3-23are not limited to such a method, but instead may stand alone as structures independent of the method.

As shown in cross-sectional view300ofFIG.3, a first substrate302is provided. In some embodiments, the first substrate302may be a silicon-on-insulator (SOI) substrate. In such embodiments, the first substrate302may comprise a base layer304, an insulator layer306arranged over the base layer304, and an active layer308arranged over the insulator layer306. In some embodiments, the base layer304and the active layer308may comprise a semiconductor material such as, for example, silicon, germanium, or the like. In some other embodiments, the first substrate302may be a single semiconductor substrate or wafer.

As shown in cross-sectional view400ofFIG.4, a stack of semiconductor layers402may be formed over first substrate302. The stack of semiconductor layers402may comprise spacer layers406and semiconductor layers404arranged in an alternating order. In other words, each one of the semiconductor layers404may be arranged between a lower one of the spacer layers406and an upper one of the spacer layers406. In some embodiments, the spacer layers406comprise a first material, and the semiconductor layers404comprise a second material different than the first material. In some embodiments, for example, the first material of the spacer layers406comprises germanium silicon or germanium, whereas the second material of the semiconductor layers404comprises silicon. In some embodiments, a bottommost layer of the stack of semiconductor layers402is a bottommost spacer layer406b. In such embodiments, the bottommost spacer layer406bdirectly contacts the active layer308of the first substrate302. In some embodiments, the semiconductor layers404and the spacer layers406are formed by an epitaxy growth process.

As shown in cross-sectional view500ofFIG.5, in some embodiments, a first dummy gate structure502and a second dummy gate structure504are formed over the stack of semiconductor layers402. In some embodiments, the first dummy gate structure502and the second dummy gate structure504comprise a dummy interfacial layer506arranged over the stack of semiconductor layers402, a dummy gate electrode510arranged over the dummy interfacial layer506and a dummy masking structure508arranged over the dummy gate electrode510. In some embodiments, a conformal first gate layer512is formed continuously over the first dummy gate structure502, the second dummy gate structure504, and the stack of semiconductor layers402. In some embodiments, the first dummy gate structure502is spaced from the second dummy gate structure504by a first distance d1. In some embodiments, the first distance d1is in a range of between, for example, approximately 2.5 nanometers and approximately 100 nanometers.

In some embodiments, the dummy interfacial layer506of the first and second dummy gate structures502,504may comprise, for example, a dielectric material such as a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), or some other suitable material. In some embodiments, the dummy gate electrodes510may comprise, for example, polysilicon. In some embodiments, the dummy interfacial layers506and the dummy gate electrodes510may be formed by way of a thermal oxidation and/or deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced CVD (PE-CVD), atomic layer deposition (ALD), etc.) followed by a removal process according to the dummy masking structures508. In some embodiments, the dummy masking structures508may be formed using photolithography and removal (e.g., etching) processes. In some embodiments, the dummy masking structures508may comprise a photoresist or hard mask material. In some embodiments, the conformal first gate layer512is formed over the dummy masking structures508by way of a deposition process (e.g., PVD, CVD, PE-CVD, ALD, etc.). In some embodiments, the conformal first gate layer512may comprise an oxide (e.g., silicon dioxide), a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), or some other suitable dielectric material.

As shown in cross-sectional view600ofFIG.6, in some embodiments, a removal process according to the first and second dummy gate structures502,504may be performed to remove upper portions of the stack of semiconductor layers (402ofFIG.5) to form upper patterned stacks of semiconductor layers602arranged directly beneath the first and second dummy gate structures502,504. In such embodiments, the removal process ofFIG.6is controlled by, for example, time, such that the removal process ofFIG.6does not completely remove a bottommost semiconductor layer404b. Thus, after the removal process ofFIG.6, the bottommost spacer layer406bis not removed and is completely covered by the bottommost semiconductor layer404b.

In some embodiments, the removal process ofFIG.6may be or comprise an etching process, such as, for example, a dry etching process. The removal process ofFIG.6may also be performed substantially in the vertical direction. Further, in some embodiments, the removal process ofFIG.6may remove the portions of the conformal first gate layer (512ofFIG.5) to form a first gate sidewall structure132surrounding outermost sidewalls of the first and second dummy gate structures502,504. Further, the dummy masking structure508may be substantially resistant to removal by the removal process ofFIG.6, in some embodiments.

As shown in cross-sectional view700ofFIG.7, inner spacer structures128are formed on outermost sidewalls of the spacer layers406. In some embodiments, before forming the inner spacer structures128, a lateral removal process is performed to outer portions of the spacer layers406to reduce the width of the spacer layers406. In some embodiments, the lateral removal process may comprise an isotropic etching process. Further, in some embodiments, the semiconductor layers404are unaffected by the lateral removal process. Then, in some embodiments, an inner spacer material is formed over the bottommost semiconductor layer404band over and around the upper patterned stacks of semiconductor layers602. In some embodiments, a vertical etching process may then be performed to remove portions of the inner spacer material that are not arranged on the outer sidewalls of the spacer layers406, thereby forming the inner spacer structures128.

As shown in cross-sectional view800ofFIG.8, in some embodiments, a removal process is performed to remove portions of the bottommost semiconductor layer (404bofFIG.7) and of the bottommost spacer layer (406bofFIG.7) that do not directly underlie the first or second dummy gate structures502,504. In some embodiments, the removal process ofFIG.8comprises an etching process conducted substantially in the vertical direction. In some embodiments, the removal process ofFIG.8may also remove portions of the active layer308of the first substrate302.

After the removal process ofFIG.8, channel structures121are formed directly below the first and second dummy gate structures502,504. In some embodiments, the channel structures121may comprise nanosheet channel structures122formed from the semiconductor layers (404ofFIG.7). It will be appreciated that in some embodiments, the channel structures121may each comprise more or less than four nanosheet channel structures122. In some embodiments, a bottommost nanosheet channel structure122bmay be spaced apart from the first substrate302by the bottommost spacer layer406b. The bottommost spacer layer406bdoes not comprise inner spacer structures128.

As shown in cross-sectional view900ofFIG.9, in some embodiments, the bottommost spacer layer (406bofFIG.8) may be selectively removed by a removal process, and a protection layer134may be formed directly between the bottommost nanosheet channel structure122band the first substrate302. In some embodiments, the removal process ofFIG.9comprises an isotropic etching process (e.g., wet etch, dry etch) to completely remove the bottommost spacer layer (406bofFIG.8). Although the spacer layers406arranged above the bottommost nanosheet channel structure122bcomprise a same material as the bottommost spacer layer (406bofFIG.8), the inner spacer structures128protect the spacer layers406arranged above the bottommost nanosheet channel structure122bfrom removal by the removal process ofFIG.9.

After removal of the bottommost spacer layer (406bofFIG.8), the protection layer134may be formed by first forming a protection material over the first substrate302and directly between the active layer308of the first substrate302and the bottommost nanosheet channel structure122b. Then, in some embodiments, an etching process may be performed according to the first and second dummy gate structures502,504to remove portions of the protection material that do not directly underlie the first and second dummy gate structures502,504, thereby forming the protection layer134.

In some embodiments, the protection layer134may comprise a same material as the inner spacer structures128. In other embodiments, the protection layer134may comprise a different material than the inner spacer structures128. In some embodiments, the protection layer134may comprise, for example, a dielectric material such as silicon nitride, silicon oxynitride, silicon carbon nitride, or some other suitable dielectric material.

As shown in cross-sectional view1000ofFIG.10, in some embodiments, a first source/drain region126a, a second source/drain region126b, and a third source/drain region126care formed on exposed portions of the active layer308of the first substrate302. In some embodiments, the first, second, and third source/drain regions126a,126b,126cextend from the first substrate302to above a topmost one of the nanosheet channel structures122. Further, the first, second, and third source/drain regions126a,126b,126cdirectly contact the nanosheet channel structures122. In some embodiments, the first, second, and third source/drain regions126a,126b,126care formed by way of an epitaxy growth process and comprise a semiconductor material. For example, in some embodiments, the first, second, and third source/drain regions126a,126b,126ccomprise silicon, germanium, or silicon germanium.

As shown in cross-sectional view1100ofFIG.11, in some embodiments, a gate dielectric layer116is formed over the first, second, and third source/drain regions126a,126b,126c; and a removal process is conducted to remove the first and second dummy gate structures (502,504ofFIG.10) and the spacer layers (406ofFIG.10). In some embodiments, the gate dielectric layer116is formed by way of a deposition process (e.g., PVD, CVD, PE-CVD, ALD, etc.). Further in some embodiments, the gate dielectric layer116comprises, for example, a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), a low-k oxide (e.g., a carbon doped oxide, SiCOH), or some other suitable dielectric material.

In some embodiments, the removal process ofFIG.11comprises one or more etching processes. For example, in some embodiments, a first etchant may be used to remove the dummy masking structures (508ofFIG.10), and a second etchant may be used to remove the dummy gate electrodes (510ofFIG.10), the dummy interfacial layer (506ofFIG.10), and the spacer layers (406ofFIG.10). In some embodiments, the removal process ofFIG.11does not remove the first gate sidewall structure132.

As shown in cross-sectional view1200ofFIG.12, in some embodiments, gate electrodes124are formed over and between the nanosheet channel structures122, thereby forming a first nanosheet field effect transistor (NSFET)118and a second NSFET120arranged over the first substrate302. In such embodiments, the second source/drain region126bis arranged between and shared by the first and second NSFETs118,120.

It will be appreciated that in other embodiments, the steps of the method illustrated inFIGS.3-12may be modified to form some other transistor type than an NSFET, such as, for example, a fin field effect transistor.

In some embodiments, the gate electrodes124of the first and second NSFETs118,120are formed by depositing a gate electrode material over and between the nanosheet channel structures122. In some embodiments, the gate electrode material is formed by way of a deposition process (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.). Further, in some embodiments, a removal process (e.g., chemical mechanical planarization (CMP)) is performed to remove any excess gate electrode material arranged over the gate dielectric layer116to form the gate electrode124of the first NSFET118and the gate electrode124of the second NSFET120. In some embodiments, the gate electrodes124of the first and second NSFETs118,120comprise a conductive material, such as, for example, titanium, tantalum, aluminum, or some other suitable conductive material.

As shown in cross-sectional view1300ofFIG.13, a first interconnect structure107is formed over the gate electrodes124of the first and second NSFETs118,120and over the gate dielectric layer116. In some embodiments, the first interconnect structure107comprises interconnect vias108and interconnect wires110embedded in interconnect dielectric layers112and interconnect etch stop layers114. In some embodiments, the first interconnect structure107may be formed by way of deposition processes (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.), patterning processes (e.g., photolithography/etching), and removal processes (e.g., wet etching, dry etching, chemical mechanical planarization (CMP), etc.).

For example, in some embodiments a bottommost one of the interconnect etch stop layers114is deposited over the gate dielectric layer116, and a bottommost one of the interconnect dielectric layers112is deposited over the bottommost one of the interconnect etch stop layers114. Then, in some embodiments, photolithography is performed to form cavities in the bottommost ones of the interconnect dielectric layers112and the interconnect etch stop layers114to expose the gate electrodes124of the first and second NSFETs118,120. Then, in some embodiments, a conductive material may be deposited within the cavities, and a removal process is performed to remove excess conductive material arranged over the bottommost one of the interconnect dielectric layers112to form the interconnect vias108in the bottommost ones of the interconnect dielectric layers112and the interconnect etch stop layers114. In such embodiments, the interconnect vias108and/or the interconnect wires110may be formed by way of a damascene process or a dual-damascene process. In some other embodiments, it will be appreciated that more or less than the interconnect wires110and interconnect vias108may be present than what is illustrated in the cross-sectional view1300ofFIG.13.

In some embodiments, the interconnect dielectric layers112comprise, for example, a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), a low-k oxide (e.g., a carbon doped oxide, SiCOH), or some other suitable dielectric material. In some embodiments, the interconnect etch stop layers114also comprise a dielectric material, but comprise a different dielectric material than the interconnect dielectric layers112. In some embodiments, the interconnect wires110and the interconnect vias108comprise a conductive material such as, for example, tungsten, aluminum, copper, titanium, tantalum, or some other suitable conductive material.

As shown in cross-sectional view1400ofFIG.14, in some embodiments, a second bonding layer106is formed over the first interconnect structure107. In some embodiments, the second bonding layer106comprises, for example, an oxide such as silicon dioxide. It will be appreciated that other materials for the second bonding layer106are also within the scope of the disclosure. In some embodiments, the second bonding layer106is formed by way of a high density plasma deposition process. In other embodiments, the second bonding layer106may be formed by way of another deposition process (e.g., CVD, PVD, PE-CVD, ALD, etc.). In some embodiments, to ensure a smooth upper surface, for example, the second bonding layer106may undergo a CMP process after it is deposited over the first interconnect structure107.

As shown in cross-sectional view1500ofFIG.15, in some embodiments, a first bonding layer104arranged on a carrier substrate102is bonded to the second bonding layer106. In such embodiments, the bonding process to bond the first bonding layer104to the second bonding layer106may comprise a thermal bonding process, for example. It will be appreciated that other bonding processes are also within the scope of the disclosure. It some embodiments, the first bonding layer104may also comprise an oxide, such as, silicon dioxide, for example.

As shown in cross-sectional view1600ofFIG.16, in some embodiments, the structure in the cross-sectional view1500ofFIG.15is flipped such that a backside302bof the first substrate302is facing “up” to be patterned. It will be appreciated that inFIGS.3-15, the first and second NSFETs118,120were formed on a frontside302fof the first substrate302and that the frontside302fof the first substrate302is on an opposite side of the backside302bof the first substrate302. In embodiments wherein the first substrate302is an SOI substrate, the first substrate302is flipped such that the base layer304is exposed for patterning. In such embodiments, the carrier substrate102may protect the first interconnect structure107from damage during the flipping of the structure inFIG.16.

As shown in cross-sectional view1700ofFIG.17, in some embodiments, a removal process is performed to remove portions of the first substrate (302ofFIG.17). In some embodiments, the removal process may comprise a CMP process to thin down the first substrate (302ofFIG.17). The removal process ofFIG.17may be conducted to remove the base layer (304ofFIG.16) of the first substrate (302ofFIG.16) and the insulator layer (306ofFIG.16) of the first substrate (302ofFIG.16). In some embodiments, the removal process ofFIG.17is stopped before completely removing the active layer308. Thus, after the removal process ofFIG.17, in some embodiments, the active layer308may still completely cover the first, second, and third source/drain regions126a,126b,126c. In other embodiments, the removal process ofFIG.17may comprise an etching process.

As shown in cross-sectional view1800ofFIG.18, in some embodiments, a removal process is performed to completely remove the active layer (308ofFIG.17) and/or remaining portions of the first substrate (302ofFIG.16) from the first, second, and third source/drain regions126a,126b,126c. In some embodiments, the removal process ofFIG.18comprises an etching process (e.g., wet etching, dry etching). In some embodiments, the removal processes ofFIGS.17and18comprise a single etchant, whereas in other embodiments, the removal process ofFIG.17comprises a CMP process followed by an etching process inFIG.18. In some embodiments, the removal process ofFIG.18also removes upper portions of the first, second, and third source/drain regions126a,126b,126c. In some embodiments, a same etchant may be used to remove the first substrate (302ofFIG.16) and portions of the first, second, and third source/drain regions126a,126b,126c, whereas in other embodiments different etchants may be used to remove the first substrate (302ofFIG.16) and the portions of the first, second, and third source/drain regions126a,126b,126c.

Nevertheless, in such embodiments, after the removal process ofFIG.18, one or more of the nanosheet channel structures122may be exposed. In such embodiments, the protection layers134of the first and second NSFETs118,120provide protection to the nanosheet channel structures122during the removal of the first substrate (302ofFIG.16). Thus, in some embodiments, the removal process ofFIG.18comprises one or more etchants to remove the first substrate (302ofFIG.16) and portions of the first, second, and third source/drain regions126a,126b,126c, and the protection layers134comprise a material that is resistant to removal by the one or more etchants of the removal process ofFIG.18. Further, the one or more etchants of the removal process ofFIG.18may be performed in a substantially vertical direction to prevent removal or damage to the nanosheet channel structures122in the lateral direction.

As shown in cross-sectional view1900ofFIG.19, in some embodiments, a barrier layer1936may be formed continuously over the first and second NSFETs118,120, thereby covering outer sidewalls of the nanosheet channel structures122arranged over the first, second, and third source/drain regions126a,126b,126c. In some embodiments, the barrier layer1936is formed by way of a deposition process (e.g., PVD, CVD, PE-CVD, ALD, etc.) and comprises a carbide (e.g., silicon carbide), a nitride (e.g., silicon nitride, silicon carbon nitride), or some other suitable dielectric material.

Further, in some embodiments, a contact dielectric layer140is formed over the barrier layer1936. In some embodiments, the contact dielectric layer140is formed by way of a deposition process (e.g., PVD, CVD, PE-CVD, ALD, etc.) and/or a removal process (e.g., etching, CMP, etc.). In some embodiments, the contact dielectric layer140comprises, for example, a nitride (e.g., silicon nitride, silicon oxynitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon oxide), borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), a low-k oxide (e.g., a carbon doped oxide, SiCOH), or some other suitable dielectric material. In some embodiments, the contact dielectric layer140extends above the first and second NSFETs118,120.

As shown in cross-sectional view2000ofFIG.20, in some embodiments, a contact masking structure2002is formed over the contact dielectric layer140, and a removal process is performed according to the contact masking structure2002to form a contact cavity in the contact dielectric layer140. In some embodiments, the contact masking structure2002is formed by way of photolithography and removal (e.g., etching) processes to form an opening arranged over the second source/drain region126b. In such embodiments, the contact masking structure2002may comprise a photoresist or a hard mask material. In some embodiments, after the formation of the contact masking structure2002, the removal process ofFIG.20is performed to remove portions of the contact dielectric layer140directly underlying the opening in the contact masking structure2002to form the contact cavity2004. In some embodiments, the removal process ofFIG.20comprises an etching process (e.g., wet etching, dry etching). In some embodiments, the contact cavity2004exposes the entire upper surface of the second source/drain region126b. Further, in some embodiments, portions of the protection layers134are also exposed after the formation of the contact cavity2004. In such embodiments, the protection layers134may comprise a material that is substantially resistant to removal by the removal process ofFIG.20.

Further, in some embodiments, horizontal portions of the barrier layer (1936ofFIG.19) that are arranged directly below the opening in the contact masking structure2002may be removed by the removal process ofFIG.20. The remaining barrier layer (1936ofFIG.19) may form a barrier structure136arranged on outer sidewalls of the protection layers134and nanosheet channel structures122arranged above the first, second, and third source/drain regions126a,126b,126c. The barrier structure136may protect the nanosheet channel structures122from removal and/or damage by the removal process ofFIG.20.

As shown in cross-sectional view2100ofFIG.21, a silicide layer216may be formed over the second source/drain region126b, and a contact plug structure138may be formed over the silicide layer216and within the contact cavity (2004ofFIG.20). In some embodiments, the silicide layer216may be formed by depositing a transition metal layer covering the second source/drain region126band subsequently heating the transition metal layer so it reacts with the semiconductor material of the second source/drain region126b. Thus, in some embodiments, the silicide layer216may comprise nickel silicide, titanium silicide, cobalt silicide, platinum silicide, tungsten silicide, or some other metal-semiconductor material.

In some embodiments, after the formation of the silicide layer216, a contact conductive material is formed over the silicide layer216by way of a deposition process (e.g., CVD, PVD, PE-CVD, ALD, sputtering, etc.). In some embodiments, excess contact conductive material arranged over the contact dielectric layer140is then removed by way of a removal process (e.g., etching, CMP) to form the contact plug structure138embedded in the contact dielectric layer140. In some embodiments, the contact plug structure138may comprise, for example, tungsten, ruthenium, cobalt, or some other conductive material with a low resistivity. Further, in some embodiments, the contact plug structure138comprises a lower portion138L arranged directly between the protection layers134that has a width equal to the first distance d1and second height h2. In some embodiments, the first distance d1may be in a range of between, for example, approximately 2.5 nanometers and approximately 100 nanometers, and the second height h2may be in a range of between, for example, approximately 5 nanometers and approximately 150 nanometers. Further, in some embodiments, the contact plug structure138comprises an upper portion138U arranged over the protection layers134that has a width equal to a second distance d2and a third height h3. In some embodiments, the second distance d2and the third height h3may each be in a range of between, for example approximately 5 nanometers and approximately 150 nanometers.

As shown in cross-sectional view2200ofFIG.22, in some embodiments, a memory structure142is formed directly over the contact plug structure138. In some embodiments, the memory structure142is a magnetoresistive random-access memory (MRAM) cell, comprising a magnetic tunnel junction (MTJ) stack202arranged between a top electrode148and a bottom electrode144. The bottom electrode144is arranged directly over and is coupled to the contact plug structure138. In some embodiments, the MTJ stack202may comprise a thin insulating layer208arranged between a bottom magnetic layer204and a top magnetic layer206. Further in some embodiments, the MTJ stack202has outermost sidewalls surrounded by a first MRAM sidewall structure210and a second MRAM sidewall structure212. The memory structure142may be arranged within a memory dielectric structure143arranged over the contact dielectric layer140.

In some embodiments, the memory structure142is formed through various steps comprising deposition processes (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), PE-CVD, atomic layer deposition (ALD), sputtering, etc.), removal processes (e.g., wet etching, dry etching, chemical mechanical planarization (CMP), etc.), and/or patterning processes (e.g., photolithography/etching). In other embodiments, the memory structure142may instead be or comprise a metal-insulator-metal memory cell, a ferroelectric random-access memory cell, a phase-change random-access memory cell, a resistive random-access memory cell, or some other memory device. In some embodiments, an interconnect etch stop layer114is formed over the memory structure142for protection of the memory structure142and/or memory dielectric structure143in future processing steps.

As shown in cross-sectional view2300ofFIG.23, in some embodiments, a second interconnect structure150is arranged over and coupled to the memory structure142. In some embodiments, the second interconnect structure150is formed similarly to the first interconnect structure107as described inFIG.13. The second interconnect structure150may comprise interconnect vias108and interconnect wires110embedded in interconnect dielectric layers112and/or interconnect etch stop layers114. In some embodiments, from the perspective of the cross-sectional view2300, wherein the second interconnect structure150is arranged over the first and second NSFETs118,120, and the first interconnect structure107is arranged below the first and second NSFETs118,120, the interconnect vias108of the second interconnect structure150have upper surfaces wider than their lower surfaces, whereas the interconnect vias108of the first interconnect structure107have upper surfaces that are more narrow than their lower surfaces.

In the cross-sectional view2300ofFIG.23, the memory structure142is arranged over and coupled to the first and second NSFETs118,120through the contact plug structure138, and a first interconnect structure107is arranged below and coupled to the first and second NSFETs118,120. Because upper and lower sides of the first and second NSFETs118,120are utilized, the overall height of the integrated chip may be reduced to increase device density while also improving signal travel efficiency between the first and second NSFETs118,120and the memory structure142to increase device reliability.

FIG.24illustrates a flow diagram of some embodiments of a method2400corresponding to the method illustrated inFIGS.3-23.

While method2400is illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

At act2402, spacer layers arranged between semiconductor layers are formed over a frontside of a substrate.FIG.4illustrates a cross-sectional view400of some embodiments corresponding to act2402.

At act2404, a first dummy gate structure and a second dummy gate structure are formed over the spacer and semiconductor layers.FIG.5illustrates cross-sectional view500of some embodiments corresponding to act2404.

At act2406, portions of the spacer and semiconductor layers that do not directly underlie the first and second dummy gate structures are removed, wherein a bottommost spacer layer is not removed and remains completely covered by a bottommost semiconductor layer.FIG.6illustrates cross-sectional view600of some embodiments corresponding to act2406.

At act2408, outer portions of exposed spacer layers are removed, and inner spacer structures are formed on the exposed spacer layers.FIG.7illustrates cross-sectional view700of some embodiments corresponding to act2408.

At act2410, portions of the bottommost semiconductor layer and the bottommost spacer layer that do not directly underlie the first and second dummy gate structures are removed.FIG.8illustrates cross-sectional view800of some embodiments corresponding to act2410.

At act2412, the bottommost semiconductor layer is selectively removed, and a first protection layer and a second protection layer arranged directly below the first dummy gate structure and the second dummy gate structure, respectively, are formed.FIG.9illustrates cross-sectional view900of some embodiments corresponding to act2412.

At act2414, source/drain regions are formed over the frontside of the substrate and beside the semiconductor layers; and the first dummy gate structure, the second dummy gate structure, and the spacer layers are replaced with gate electrodes to form a first nanosheet field effect transistor (NSFET) and a second NSFET.FIGS.10,11, and12illustrate cross-sectional views1000,1100,1200, respectively, of some embodiments corresponding to act2414.

At act2416, a first interconnect (IC) structure that is coupled to the first and second NSFETs is formed.FIG.13illustrates cross-sectional view1300of some embodiments corresponding to act2416.

At act2418, the substrate is flipped over to expose a backside of the substrate.FIG.16illustrates cross-sectional view1600of some embodiments corresponding to act2418,

At act2420, the substrate is removed.FIGS.17and18respectively illustrate cross-sectional views1700and1800of some embodiments corresponding to act2420.

At act2422, a contact plug structure is formed between the first and second NSFETs and is coupled to the source/drain region arranged between the first and second NSFETs.FIG.21illustrates cross-sectional view2100of some embodiments corresponding to act2422.

At act2424, a memory structure is formed over and coupled to the contact plug structure, and a second IC structure is formed over and coupled to the memory structure.FIGS.22and23respectively illustrate cross-sectional views2200and2300of some embodiments corresponding to act2424.

Therefore, the present disclosure relates to a method of manufacturing a memory structure arranged over first and second transistors and a first interconnect structure arranged below the first and second transistors to reduce the height of the integrated chip to increase device density while also improving signal travel efficiency.

Accordingly, in some embodiments, the present disclosure relates to an integrated chip comprising: a first transistor arranged over a substrate and comprising: first channel structures extending between a first source/drain region and a second source/drain region, a first gate electrode arranged between the first channel structures, and a first protection layer arranged over a topmost one of the first channel structures; a second transistor arranged over the substrate, beside the first transistor, and comprising: second channel structures extending between the second source/drain region and a third source/drain region, a second gate electrode arranged between the second channel structures, and a second protection layer arranged over a topmost one of the second channel structures; a first interconnect structure coupled to the first and second gate electrodes and arranged between the substrate and the first and second channel structures; and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.

In other embodiments, the present disclosure relates to an integrated chip comprising: a first interconnect structure over a substrate; a first channel structure arranged over and coupled to the first interconnect structure; a second channel structure arranged over and coupled to the first interconnect structure; a source/drain region arranged between the first and second channel structures; a first protection layer and a second protection layer arranged over the first channel structure and the second channel structure, respectively; a contact plug structure arranged over and coupled to the source/drain region; and a memory structure arranged over and coupled to the contact plug structure.

In yet other embodiments, the present disclosure relates to a method comprising: forming a first protection layer over a first substrate and a second protection layer over the first substrate; forming a first nanosheet field effect transistor (NSFET) arranged over the first protection layer and comprising first nanosheet channel structures, a first source/drain region, a second source/drain region, and a first gate electrode; forming a second NSFET over the second protection layer and comprising second nanosheet channel structures, the second source/drain region, a third source/drain region, and a second gate electrode; forming a first interconnect structure over the first and second NSFETs, wherein the first interconnect structure comprises interconnect wires and interconnect vias embedded in an interconnect dielectric structure; forming a bonding layer over the first interconnect structure; bonding a carrier substrate to the bonding layer; flipping the first substrate over to pattern a backside of the first substrate; removing the first substrate completely to expose the first, second, and third source/drain regions and the first and second protection layers; forming a dielectric layer over the first, second, and third source/drain regions and the first and second protection layers; forming a contact plug structure extending through the dielectric layer and coupled to the second source/drain region that is arranged between the first and second NSFETs; forming a memory structure over and coupled to the contact plug structure; and forming a second interconnect structure over and coupled to the memory structure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.