Patent ID: 12191361

It is noted that the drawings of the disclosure are not necessarily to scale. The drawings are intended to depict only typical aspects of the disclosure, and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like numbering represents like elements between the drawings.

DETAILED DESCRIPTION

In the following description, reference is made to the accompanying drawings that form a part thereof, and in which is shown by way of illustration specific illustrative embodiments in which the present teachings may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it is to be understood that other embodiments may be used and that changes may be made without departing from the scope of the present teachings. The following description is, therefore, merely illustrative.

It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or “over” another element, it may be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there may be no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it may be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

Reference in the specification to “one embodiment” or “an embodiment” of the present disclosure, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the phrases “in one embodiment” or “in an embodiment,” as well as any other variations appearing in various places throughout the specification are not necessarily all referring to the same embodiment. It is to be appreciated that the use of any of the following “/,” “and/or,” and “at least one of,” for example, in the cases of “A/B,” “A and/or B” and “at least one of A and B,” is intended to encompass the selection of the first listed option (a) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C,” such phrasing is intended to encompass the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B), or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as readily apparent by one of ordinary skill in the art, for as many items listed.

An integrated circuit (IC) structure according to the disclosure may provide, e.g., a transistor structure including a field plate over a first dielectric layer. The field plate includes multiple layers, e.g., a first layer including a high dielectric constant metal gate (HKMG) stack, and a second layer over the first layer including polysilicon. A gate structure is over the first dielectric layer and laterally adjacent to the field plate. The gate structure includes a polysilicon layer, and a gate spacer is laterally between the polysilicon layer and the field plate.

Referring toFIG.1, a preliminary structure50to form an IC structure according to embodiments of the disclosure is shown. Preliminary structure50may be processed as described herein to yield an IC structure including an extended drain metal oxide semiconductor (EDMOS) transistor structure according to embodiments of the disclosure. However, it is understood that other techniques, ordering of processes, etc., alternatively may be implemented to yield an IC structure according to the disclosure.FIG.1shows a cross-sectional view of preliminary structure50with a substrate102, e.g., one or more semiconductor materials. Substrate102may include but is not limited to silicon, germanium, silicon germanium, silicon carbide, or any other common IC semiconductor substrates. A portion or entire semiconductor substrate102may be strained.

For purposes of reference, three doped well regions104,106,108for different types of structures are illustrated. Each region may be electrically isolated from another by respective trench isolations110. Each trench isolation110may include a trench etched into substrate102and filled with an insulating material such as oxide, insulative semiconductor, etc., to isolate one region of the substrate from an adjacent region of the substrate. One or more structures of a given polarity may be formed on or partially within each doped well region104,106,108and isolated from others by trench isolations110. Semiconductor substrate102may include a variety of doped wells therein for formation of different polarity transistors. Doped well region104includes, for example, a doped well112in substrate102for providing a complementary metal oxide semiconductor (CMOS) device214(FIGS.8-12). Doped well region106includes, for example, three doped wells114including a doped well114B laterally between a doped well114A and a doped well114C for providing a flash memory cell structure208(FIGS.8-12). Doped well region108includes, for example, a first doped well120adjacent a second doped well122at a well boundary124in substrate102for providing a transistor structure212(FIGS.8-12). First doped well120includes a first dopant type and second doped well122includes a second dopant type opposite the first dopant type. Each well may be formed using any appropriate n-type or p-type dopant and may be formed using any now known or later developed technique (e.g., in-situ doping or ion implantation). The opposite doping polarities in each well120,122may define a “P-N junction” across well boundary124. The term “P-N” refers to two adjacent materials having different types of conductivity (i.e., P-type and N-type), which may be induced through dopants within the adjacent material(s). In some embodiments, one or more of doped well regions104,106,108may be counter-doped.

Preliminary structure50may include a dielectric layer126over substrate102. Dielectric layer126may be formed, e.g., by depositing gate dielectric material such as silicon dioxide (SiO2). In the present embodiment, dielectric layer126includes silicon dioxide. In alternative embodiments, dielectric layer126may be formed, e.g., by depositing any now known or later developed high dielectric constant (high-K) material (K value of at least approximately 3.9). Dielectric layer126may include any material typically used for gate dielectrics such as but not limited to metal oxides such as: tantalum oxide (Ta2O5), barium titanium oxide (BaTiO3), hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), or metal silicates such as hafnium silicate oxide (HfA1SiA2OA3) or hafnium silicate oxynitride (HfA1SiA2OA3NA4), where A1, A2, A3, and A4 represent relative proportions, each greater than or equal to zero and A1+A2+A3+A4 (1 being the total relative mole quantity), or a combination of these materials.

As used herein, “depositing” may include any now known or later developed techniques appropriate for the material to be deposited including but are not limited to: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metalorganic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation. Dielectric layer126may be deposited, for example, using ALD.

Referring now toFIG.2, embodiments of the disclosure may include removing portions of dielectric layer126using, e.g., a mask (not shown) with an opening at a targeted position to expose dielectric layer126. This removal process may include, forming a mask patterned to expose selected portion(s) of dielectric layer126. The mask (not shown) may include any now known or later developed appropriate masking material, e.g., a nitride hard mask. Any appropriate etching process, e.g., a reactive ion etch (RIE), can remove selected portion(s) of dielectric layer126. As shown inFIG.2, continued processing may include removing portions of dielectric layer126to yield a first portion128of dielectric layer126adjacent to a second portion130of dielectric layer126. First portion128of dielectric layer126is over first doped well120, second doped well122, and well boundary124. First portion128, moreover, has a first height132above doped well region108. Second portion130of dielectric layer126is over second doped well122and has a second height134above doped well region108that is greater than first height132above doped well region108. Forming dielectric layer126may include forming a first mask patterned to recess dielectric layer126to second height134and forming a second mask (not shown) patterned to expose second portions128of dielectric layer126to reduce second portions128to first height132. Where portions128,130have a substantially uniform composition, they may be distinguished from one another based on their relative heights and horizontal positions. Thus, there may not be a visible physical boundary between portions128,130of dielectric layer126. First portion128may not necessarily include the same materials as second portion130. For example, first portion128may include a middle voltage gate oxide (MVGOX) and second portion130may include a high voltage gate oxide (HVGOX). In another example, second portion130may include multiple materials, e.g., it may include an upper portion that includes HVGOX and a lower portion that includes MVGOX. In yet another example, second portion130may include an upper portion that includes HVGOX and a lower portion that includes MVGOX.

As discussed herein, portions128,130of dielectric layer126may be formed in part by etching. Etching generally refers to the removal of material from a substrate (or structures formed on the substrate) and is often performed with a mask in place so that material may selectively be removed from certain areas of the substrate, while leaving the material unaffected, in other areas of the substrate. There are generally two categories of etching, (i) wet etch and (ii) dry etch. Wet etch is performed with a solvent (such as an acid) which may be chosen for its ability to selectively dissolve a given material (such as oxide), while leaving another material (such as polysilicon) relatively intact. This ability to selectively etch given materials is fundamental to many semiconductor fabrication processes. A wet etch will generally etch a homogeneous material (e.g., oxide) isotropically, but a wet etch may also etch single-crystal materials (e.g., silicon wafers) anisotropically. Dry etch may be performed using a plasma. Plasma systems can operate in several modes by adjusting the parameters of the plasma. Ordinary plasma etching produces energetic free radicals, neutrally charged, that react at the surface of the wafer. Since neutral particles attack the wafer from all angles, this process is isotropic. Ion milling, or sputter etching, bombards the wafer with energetic ions of noble gases, which approach the wafer approximately from one direction, and therefore this process is highly anisotropic. Reactive ion etching (RIE) operates under conditions intermediate between sputter and plasma etching and may be used to produce deep, narrow features, such as shallow trench isolation (STI) trenches. In one non-limiting example, a RIE may be used to etch dielectric layer126.

Referring now toFIG.3, embodiments of the disclosure may include depositing a plurality of material layers over exposed portions of preliminary structure50. The plurality of material layers may include a dielectric layer136over substrate102and dielectric layer126, a semiconductor material layer138over dielectric layer136, and an insulative stack140over semiconductor material layer138. Dielectric layer136may be formed, e.g., by depositing any now known or later developed high-K material typically used for gate dielectrics such as but not limited to metal oxides. Semiconductor material layer138may be formed, e.g., by depositing semiconductor material such as but not limited to polysilicon (poly-Si). Insulative stack140may be formed, e.g., by depositing two or more layers of insulative material such as but not limited to oxide and nitride. Insulative stack140may include, for example, an oxide-nitride-oxide (ONO) stack over semiconductor material layer138. Additional processing may include selectively removing portions of semiconductor material layer138and insulative stack140over dielectric layer136. For example, as shown inFIG.4, embodiments of the disclosure may include selectively removing portions of semiconductor material layer138and insulative stack140over doped well regions104,108. Remnants of semiconductor material layer138and insulative stack140remain over doped well region106and additional processing may be used, for example, to form a flash memory cell structure (FIGS.8-12) over doped well region106.

Referring now toFIG.5, embodiments of the disclosure may include depositing a semiconductor material142on any exposed materials to cover dielectric layer136and insulative stack140. Semiconductor material142may include semiconductor material such as, but not limited to polycrystalline silicon (poly-Si). As will be described, additional processing may include selectively removing portions of semiconductor material142over doped well114B in doped well region106. The structure so formed which will be used, for example, to form a flash memory cell structure (FIGS.8-12) over doped well region106.

Referring now toFIG.6, embodiments of the disclosure may include forming an erase gate structure202over doped well114B. The term “erase gate structure,” as used herein, refers to a structure electrically coupled to a line for transmitting an electrical signal to a memory cell to instruct the memory cell to erase stored data. Forming erase gate structure202may include selectively removing portions of semiconductor material142over doped well114B to expose an upper surface of insulative stack140and forming a pair of sidewall spacers144A,144B over insulative stack140. Forming pair of sidewall spacers144A,144B may include depositing a layer of spacer material (not shown) over exposed surfaces and selectively removing portions of deposited spacer material to form pair of sidewall spacers144A,144B. Pair of sidewall spacers144A,144B may structurally and electrically isolate erase gate structure202from adjacent components. Additional processing to form erase gate structure202may include, for example, selectively removing portions of insulative stack140, semiconductor material layer138, and dielectric layer136, e.g., by using a mask (not shown) to expose target portions of preliminary structure50over doped well114B and etching. Selectively removing portions of semiconductor material layer138yields a semiconductor material layer138A and a semiconductor material layer138B. Selectively removing portions of insulative stack140may yield multiple insulative stacks, e.g., an insulative stack140A and an insulative stack140B.

As further shown inFIG.6, embodiments of the disclosure may include additional processing to form erase gate structure202such as forming a highly doped region146within doped well114B and depositing a dielectric layer148over highly doped region146. The method may further include forming an insulative tunnel147over dielectric layer148and laterally abutting semiconductor material layers138A,138B to electrically isolate erase gate structure202from adjacent components. Insulative tunnel147may include insulative material such as but not limited to oxide. Additional processing may include depositing a semiconductor material149over doped well114B and horizontally between pair of sidewall spacers144A,144B. Semiconductor material149may include semiconductor material such as but not limited to poly-Si. Erase gate structure202may be useful, for example, to form a non-EDMOS transistor structure over doped well region106, such as a flash memory cell structure (FIGS.8-10).

Referring now toFIG.7, embodiments of the disclosure may include processing preliminary structure50to form a gate structure200over doped well region108and a pair of control gate structures204A,204B over doped well region106. Forming gate structure200and pair of control gate structures204A,204B may include forming a mask150over portions of preliminary structure50to protect underlying material from subsequent processing. The method may include selectively removing, e.g., etching, exposed target portions of semiconductor material142and dielectric layer136. In the illustrated example, the method includes selectively removing portions of semiconductor material142to yield a polysilicon layer142A, a polysilicon layer142B, and a polysilicon layer142C. The method further may include selectively removing portions of dielectric layer136to yield a dielectric layer136A, a dielectric layer136B, and a dielectric layer136C. In the present embodiment, dielectric layers136A,136B,136C each include a same gate oxide material and are simultaneously formed. Polysilicon layers142A,142B and dielectric layers136A,136B are used to form, for example, pair of control gate structures204A,204B over doped well region106. Polysilicon layer142C and dielectric layer136C may be used to form, for example, gate structure200over doped well region108.

As further shown byFIG.7, embodiments of the disclosure may include gate structure200having dielectric layer136C over dielectric layer126and polysilicon layer142C over dielectric layer136C. Dielectric layer136C may be on first portion128and second portion130of dielectric layer126, and vertically between polysilicon layer142C and dielectric layer126. Gate structure200may have a height158above substrate102. Forming gate structure200may include selectively removing portions of dielectric layer136(FIG.6) and semiconductor material142(FIG.6) to yield dielectric layer136C and polysilicon layer142C using, e.g., a mask150to expose target portions of semiconductor material142and dielectric layer136and etching. Additional processing may include forming a pair of gate spacers156A,156B to electrically isolate gate structure200from adjacent components. Forming pair of gate spacers156A,156B may include depositing a layer of spacer material (not shown) (e.g., nitride) over exposed surfaces and selectively removing portions of deposited spacer material to form pair of gate spacers156A,156B. As further shown byFIG.7, embodiments of the disclosure may include forming pair of control gate structures204A,204B over doped well114B. First control gate structure204A includes a stack of material layers positioned over doped well114B and doped well114C, the stack of material layers including dielectric layer136A, semiconductor material layer138A, insulative stack140A, and polysilicon layer142A. Second control gate structure204B includes a stack of material layers positioned over doped well114A and doped well114B, the stack of material layers including dielectric layer136B, semiconductor material layer138B, insulative stack140B, and polysilicon layer142B. Pair of control gate structures204A,204B may have height158above substrate102that is equal, or substantially similar to, height158of gate structure200. Additional processing may include forming a pair of gate spacers154A,154B to electrically isolate pair of control gate structures204A,204B from adjacent components. Forming pair of gate spacers154A,154B may include depositing a layer of spacer material (not shown) (e.g., nitride) over exposed surfaces and selectively removing portions of deposited spacer material to form pair of gate spacers154A,154B. Pair of gate spacers154A,154B and spacers156A,156B may include horizontally tapered ends. Pair of gate spacers154A,154B may be formed at the same time as spacers156A,156B. Alternatively, as shown inFIGS.8-12, pair of gate spacers154A,154B and spacers156A,156B may not include horizontally tapered ends. Pair of control gate structures204A,204B and pair of gate spacers154A,154B may be used, for example, to form a non-EDMOS transistor structure over doped well region106, such as a flash memory cell structure (FIGS.8-10).

Referring now toFIG.8, embodiments of the disclosure may include forming a transistor structure212over doped well region108. Transistor structure212may include gate structure200and a field plate210having a height171over substrate102. Field plate210is over second portion130of dielectric layer126and laterally adjacent to gate structure200. Field plate210may include a first layer162over second portion130of dielectric layer126, and a second layer164over first layer162. First layer162may include a high dielectric constant metal gate (HKMG) stack. Second layer164may include a semiconductor material such as but not limited to polysilicon or amorphous silicon. In some embodiments, as shown inFIG.8, field plate210may include a hard mask remnant160over second portion130of dielectric layer126. Hard mask remnant160may include masking material such as but not limited to silicon germanium (SiGe).

Forming first layer162may include forming an HKMG stack, e.g., by depositing a conformal layer of a high-K301dielectric material typically used for gate dielectric layers. Forming the HKMG stack may include depositing a work function metal (WFM) layer302over a high-K dielectric material301and using, e.g., a mask (not shown) to expose a target portion(s) of the WFM layer302to selectively remove (e.g., etching) exposed target portion(s) of the WFM layer302from high-K material layer301(not shown). Subsequent processing may include applying a heat treatment (e.g., annealing) to embed the WFM layer302within the high-K material layer301. The WFM layer302may include one of a p-type or n-type WFM. The method may further include depositing a metal layer303(not shown) such as, e.g., titanium nitride (TiN), over the high-K material layer301embedded with the WFM layer302. In the present embodiment, first layer162is an HKMG stack that includes a n-type WFM302embedded within a high-K dielectric material301over second portion130of dielectric layer126in doped well region108, and a metal layer303of TiN over the high-K dielectric material301. Subsequent processing may be useful to form, for example, an n-type or p-type EDMOS transistor (FIG.9).

Forming second layer164may include depositing a semiconductor material (not shown) on any exposed materials to cover first layer162. Semiconductor material may include any semiconductor material such as but not limited to poly-Si or amorphous silicon. Additional processing, e.g., etching, of semiconductor material may yield second layer164useful to form field plate210over substrate102. Second layer164may include a doped semiconductor material formed using any appropriate n-type or p-type dopant and may be formed using any now known or later developed technique (e.g., in-situ doping or ion implantation).

A “field plate,” as used herein, refers to a structure for reducing peak electric field and enhance breakdown voltage during operation of transistors. Field plate structures spread out an electric field and mitigate peaking of the electric field to achieve a desirable electrical field profile and increase breakdown voltage of a transistor.

As further shown inFIG.8, embodiments of the disclosure may include forming a flash memory cell structure208over doped well region106. Flash memory cell structure208may include erase gate structure202, pair of control gate structures204A,204B, and a pair of word line gate structures206A,206B over doped well region106. Pair of word line gate structures206A,206B includes a first word line gate structure206A and a second word line gate structure206B having a height170over substrate102. First word line gate structure206A is positioned over doped well114C and includes a first layer166A and a second layer168A. Second word line gate structure206B is positioned over doped well114A and includes a first layer166B and a second layer168B. First layers166A,166B each include a HKMG stack as described herein regarding first layer162of field plate210. Second layers168A,168B each include a semiconductor material such as but not limited to poly-Si. A “flash cell memory structure,” as used herein, refers to a split-gate flash memory cell configured to retain data stored in the memory cell. The split-gate flash memory cell includes, for example, an erase gate structure, a pair of control gate structures, and a pair of word line gate structures over a doped well region.

As further shown inFIG.8, embodiments of the disclosure may include forming a CMOS device214having height158over substrate102. CMOS device214is over doped well region104and laterally distal to gate structure200. CMOS device214may include a first layer172over doped well112, the former of which may include selective silicon germanium (cSiGe). A second layer174over first layer172may include a HKMG stack. A third layer176over second layer174may include a semiconductor material such as but not limited to poly-Si. First layer172, second layer174, and third layer176may collectively form a gate structure of CMOS device214. The method may include forming a gate structure of CMOS device214simultaneously with field plate210and pair of word line gate structures206A,206B.

Referring now toFIG.9, embodiments of the disclosure include forming electrically active source/drain (“S/D”) regions. S/D regions are electrically active regions in a semiconductor substrate that define opposite terminals for current flow through the transistor. When a voltage is applied to the gate of the transistor, a conductive channel enables current flow between source and drain. For example,FIG.9shows forming a source region186A and a drain region186B in doped well region108, a source region188A and a drain region188B in doped well region106, and a source region190A and a drain region190B in doped well region104of substrate102. As will be recognized, source/drain regions are doped with a dopant having a selected polarity for a respective transistor. An n-type transistor may include n-type dopants such as but not limited to: phosphorous (P), arsenic (As), antimony (Sb), and a p-type transistor may include p-type dopants such as but not limited to: boron (B), indium (In) and gallium (Ga). Similar dopants, typically with different concentrations, may be used for doped wells112,114,116,118,120,122. Any suitable thermal process may be carried out to drive in the dopants. It is understood that processing for S/D regions may be carried out before spacer formation. S/D regions186A/186B,188A/188B,190A/190B may be formed using any now known or later developed technique, e.g., in-situ doping, ion implantation, etc. Dopants used may be any dopant appropriate for the transistor to be formed. Any necessary anneal to drive in dopants may be performed.

As further shown byFIG.9, embodiments of the disclosure may include additional processing to form IC structure100. The method may include, for example, forming a sidewall spacer178to electrically isolate transistor structure212, flash memory cell structure208, and CMOS device214from adjacent components. Forming sidewall spacer178may include depositing a layer of spacer material (not shown) (e.g., nitride) over exposed surfaces and selectively removing portions of deposited spacer material.

As further shown inFIG.9, embodiments of the disclosure may include forming a silicide layer180on upper surfaces of gate structure200, field plate210, flash memory cell structure208, and S/D regions186A/186B,188A/188B,190A/190B. Silicide layer180may improve electrical coupling of gate structure to other electrical components (not shown). Silicide layer180formation may include forming a silicide block mask (not shown) to expose select portion(s) of preliminary structure50and depositing a layer of conductive metal(s) (not shown) over exposed portions of preliminary structure50. Silicide layer180formation may include depositing a layer of conductive metal(s), applying a heat treatment (e.g., rapid thermal annealing) such that the conductive metal(s) combine with underlying semiconductor material, and removing any excess metal to yield silicide layer180on the upper surface of gate structure200, field plate210, flash memory cell structure208, and S/D regions186A/186B,188A/188B,190A/190B. The method may include removing portions of the silicide blocking mask (not shown) and yielding, for example, self-aligned silicide (“silicide”) blocking (SAB) spacer184over second portion130of dielectric layer126.

As further shown byFIG.9, embodiments of the disclosure may include additional processing to form IC structure100. The method may include, for example, depositing a stress inducing liner (simply “stress liner” hereafter)184over exposed surfaces, forming an interlayer dielectric (not shown) over stress liner184, and forming one or more contacts192through the interlayer dielectric. Stress liner184may include one or more stress liners such as, but not limited to, one or more of the following: tensile stress liner for NMOS transistors, compressive stress liner for PMOS transistors, or neutral stress liners. Stress liner184may act as an etch stop layer when forming contacts192. Any appropriate middle-of-line and back-end-of-line processing may be carried out to form contacts192to gate structure200, erase gate structure202, pair of word line gate structures206A/206B, field plate210, CMOS device214, and S/D regions186A/186B,188A/188B,190A/190B. As the processes to form stress liners and contacts are well known, no further details will be provided. Any necessary etch stop layers, e.g., single, or dual contact etch stop layers, may be employed, and any silicidation can be carried out as known in the field as part of the processes.

FIG.9depicts one embodiment of IC structure100including transistor structure212, flash memory cell structure208, and CMOS device214. Transistor structure212is a high voltage EDMOS (HV EDMOS) transistor that includes gate structure200and field plate210over doped well region108. Flash memory cell structure208is a non-EDMOS transistor structure laterally distal to transistor structure212over doped well region106that includes erase gate structure202, pair of control gate structures204A/204B, pair of gate spacers154A/154B, and pair of word line gate structures206A/206B. CMOS device214is a logic transistor structure laterally distal to transistor structure212over doped well region104.

In an example, transistor structure212includes gate structure200laterally adjacent to field plate210over dielectric layer126. Gate structure200is on first and second portions128,130of dielectric layer126, and over first doped well120, second doped well122, and well boundary124. Gate structure200includes dielectric layer136C, polysilicon layer142C and pair of gate spacers156A,156B. Dielectric layer136C vertically separates polysilicon layer142C and dielectric layer126. Pair of gate spacers156A,156B electrically isolate gate structure200from adjacent components. For instance, gate spacer156A may be laterally between dielectric layer136C/polysilicon layer142C and field plate210to electrically isolate gate structure200from field plate210. Field plate210is on second portion130of dielectric layer126and over second doped well122. Field plate210includes first layer162and second layer164over first layer162. First layer162includes an HKMG stack and second layer164includes polysilicon. Field plate210may include hard mask remnant160vertically between first layer162and second portion130of dielectric layer126. Gate structure200and field plate210each include silicide layer180to electrically couple transistor structure212to other electrical components via contacts192.

As further shown inFIG.9, embodiments of the disclosure may include forming one or more devices configured for different voltage requirements (e.g., logic transistors) adjacent transistor structure212. For example, IC structure100includes CMOS device214in region104and a non-EDMOS structure, e.g., flash memory cell structure208, in doped well region106. Field plate210may be included within flash memory cell structure208. In the present embodiment, IC structure100includes flash memory cell structure208having pair of control gate structures204A,204B laterally between pair of word line gate structures206A,206B, and erase gate structure202laterally between pair of control gate structures204A,204B. Pair of control gate structures204A,204B have height158above substrate102. Pair of word line gate structures206A,206B have height170above substrate102greater than height158and less than height171of field plate210.

FIG.10depicts another embodiment of IC structure100having a source line contact194in flash memory cell structure208. IC structure100is substantially similar to the embodiment described inFIG.9but additional processing, e.g., etching, removes material from erase gate structure202before source line contact194formation.

FIG.11depicts another embodiment of IC structure100having transistor structure212that includes gate structure200and does not include field plate210. IC structure100is substantially similar to the embodiment described inFIG.10but transistor structure212does not include field plate210. Forming transistor structure212may include, for example, using a mask (not shown) to prevent second portion130of dielectric layer126from exposure to additional processing that would otherwise form field plate210(FIGS.9-10). For example, forming HKMG stacks (e.g., first layers166A/166B) may include using a mask (not shown) over doped well region108such that only portions of doped well region106and108are exposed to subsequent processing (e.g., forming HKMG stacks).

FIG.12depicts another embodiment of IC structure100having transistor structure212that includes gate structure200. IC structure100is substantially similar to the embodiment described inFIG.9, but transistor structure212is a high voltage metal oxide semiconductor (HV MOS) device over doped well region108. In the present embodiment, transistor structure212is an HV MOS device over doped well region108that includes doped well122positioned laterally between doped well120and a doped well123. Transistor structure212may include dielectric layer126having a substantially uniform height above substrate102. Transistor structure may include dielectric layer136C vertically between dielectric layer126and polysilicon layer142C. Transistor structure212may include pair of gate spacers156A/156B to electrically isolate transistor structure212from adjacent components. Alternatively, transistor structure212is a middle voltage metal oxide semiconductor (MV MOS) device.

Embodiments of the present invention provide technical and commercial advantages, and some examples of such advantages are described herein. Embodiments of the disclosure may improve operational performance for several types of transistors, such as HV EDMOS transistors. Field plate210may improve breakdown voltage, saturation-drain-current, and gate-drain capacitance in transistor structure212.

The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing structures as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input structure, and a central processor.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. “Optional” or “optionally” means that the subsequently described event or circumstance may or may not occur, and that the description includes instances where the event occurs and instances where it does not.

Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about”, “approximately” and “substantially”, are not to be limited to the precise value specified. In at least some instances, the approximating language may correspond to the precision of an instrument for measuring the value. Here and throughout the specification and claims, range limitations may be combined and/or interchanged, such ranges are identified and include all the sub-ranges contained therein unless context or language indicates otherwise. “Approximately” as applied to a particular value of a range applies to both values, and unless otherwise dependent on the precision of the instrument measuring the value, may indicate +/−10% of the stated value(s).

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiment was chosen and described in order to best explain the principles of the disclosure and the practical application, and to enable others of ordinary skill in the art to understand the disclosure for various embodiments with various modifications as are suited to the particular use contemplated.