Patent ID: 12261097

DETAILED DESCRIPTION

Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages. Making electronic devices smaller may involve bringing components closer together than they were in earlier devices. This may increase the likelihood of thermal cross talk, in which heat generated by components during operation is transferred to other components in the device. The performance of some components may be largely indifferent to this heat, while the performance of other components may be substantially degraded. For example, in radio frequency (RF) communication devices, shrinking the size of such a device may involve bringing the power amplifier (PA) dies closer to the acoustic wave resonator (AWR) dies. However, since the AWR dies may be very sensitive to temperature fluctuations, thermal cross talk between the PA dies and the AWR dies may result in temperature fluctuations for the AWR dies that are outside of an acceptable range for reliable performance. Conventional approaches to limiting this thermal cross talk typically include separately packaging the PA dies and AWR dies. These thermal issues are not limited to the RF setting; similar issues arise in other electronic devices as well, such as wearable devices, multi-chip server packages, optical devices, etc.

The structures and assemblies disclosed herein may enable closer integration of heat-generating and temperature-sensitive components than previously achievable. For example, the structures and assemblies disclosed herein may enable heat-generating components (like the PA dies discussed above) and temperature-sensitive components (like the AWR dies discussed above) to be included in a single package, without compromising the performance of the temperature-sensitive components. The structures and assemblies disclosed herein not only enable smaller form factors for existing electronic devices, but also enable the next generation of electronic devices. For example, next-generation 5G wireless communication devices may require additional hardware to accommodate an increasing number of filters and communication bands; the structures and assemblies disclosed herein may enable this hardware to be compactly integrated into desirably sized devices, accelerating adoption of this next-generation technology and facilitating its use in a broader array of devices.

In the following detailed description, reference is made to the accompanying drawings that form a part hereof wherein like numerals designate like parts throughout, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The drawings are not necessarily to scale. Although many of the drawings illustrate rectilinear structures with flat walls and right-angle corners, this is simply for ease of illustration, and actual devices made using these techniques will exhibit rounded corners, surface roughness, and other features.

The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. As used herein, a “package” and an “IC package” are synonymous. When used to describe a range of dimensions, the phrase “between X and Y” represents a range that includes X and Y.

A number of examples of thermal management arrangements in IC packages and IC assemblies are disclosed herein. Although these arrangements may be separately discussed for ease of illustration, any suitable ones of these arrangements may be combined in an IC package or IC assembly. For example, any of the arrangements ofFIGS.1-7may be used in combination with any of the embodiments including a cooling device (e.g., as illustrated inFIG.8-13,16-19,39-40, or42), or in combination with any of the other arrangements ofFIGS.1-7. This particular set of combinations is just an example, and any suitable combination of any of the embodiments disclosed herein are within the scope of this disclosure.

FIG.1is a side, cross-sectional view of an IC assembly150including an IC package100with an example thermal management arrangement, in accordance with various embodiments. The IC package100ofFIG.1includes a package substrate102to which a heat-generating (HG) component104and a temperature-sensitive (TS) component106are coupled. While all electrical components generate heat during operation, and all electrical components have some sensitivity to temperature, the terms “heat-generating” and “temperature-sensitive” are used herein to identify a relative relationship between the components104and106; namely, that the HG component104, during operation, may generate enough heat to negatively impact the performance of the TS component106unless the components104and106are part of a thermal management arrangement, such as the arrangements disclosed herein. In some embodiments, the TS component106may be associated with a maximum temperature, such that adequate performance of the TS component106may not be achieved if the temperature of the TS component106is above the maximum temperature. When the IC package100is a multi-chip server or field programmable gate array (FPGA) package, an example of such a TS component106may be a memory die or stack (e.g., memory devices having a specified maximum temperature of approximately 85 degrees Celsius), while a corresponding HG component104may be a logic component, such as a processor die. In some embodiments, the TS component106may be associated with a temperature range, such that adequate performance of the TS component106may not be achieved if the temperature of the TS component106is above or below the temperature range. When the IC package100is an RF package, an example of such a TS component106may include a component (e.g., a die) that includes resonators (e.g., AWRs), while a corresponding HG component104may include a component (e.g., a die) that includes PAs and/or switches. When the IC package100is an optical interconnect package, an example of such a TS component106may include a component (e.g., a die) that generates optical signals (e.g., vertical cavity surface emitting lasers), while a corresponding HG component104may include a logic component, such as a processor die. In some embodiments, the HG component104may be a high-power density (HPD) component and the TS component106may be a low-power density (LPD) component. As used herein, the term “high-power density” and “low-power density” are relative terms, and refer to the relative amount of power consumed/generated by the components during operation. In particular, an HPD component has a higher power density during operation than an LPD component.

AlthoughFIG.1and others of the accompanying figures depict only a single HG component104and a single TS component106, this is simply for ease of illustration, and any of the IC packages100or IC assemblies150disclosed herein may include any desired number of additional components (or fewer components, as appropriate). For example, any of the IC packages100disclosed herein may include passive components (e.g., resistors, inductors, capacitors, or combinations thereof) disposed at either face of a package substrate102, embedded in a package substrate102, or in any other suitable location. In another example, any of the IC packages100disclosed herein may include active components (e.g., transistors) disposed at either face of a package substrate102, embedded in a package substrate102, or in any other suitable location.

As noted above, the HG component104and the TS component106may be coupled to the package substrate102. In particular, the package substrate102may include a first face149and an opposing second face153, and the HG component104and the TS component106may be coupled to the second face153. The package substrate102may include a dielectric material (e.g., a ceramic, a buildup film, an epoxy film having filler particles therein, glass, an organic material, an inorganic material, combinations of organic and inorganic materials, embedded portions formed of different materials, etc.), and may have conductive pathways extending through the dielectric material between the top and bottom surfaces, or between different locations on the top surface, and/or between different locations on the bottom surface. These conductive pathways may take the form of any of the interconnect structures1628discussed below with reference toFIG.44(e.g., including lines and vias).FIG.1(and others of the accompanying drawings) illustrate conductive contacts142at the second face153electrically coupled to conductive contacts140of the TS component106by solder bumps144, but any suitable interconnects (e.g., first-level interconnects, pillars/posts, wirebonds, bumps, waveguides, etc.) may be used to couple the TS component106to the package substrate102in any of the embodiments disclosed herein. As used herein, a “conductive contact” may refer to a portion of conductive material (e.g., metal) serving as an interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket). Similarly,FIG.1(and others of the accompanying drawings) illustrate conductive contacts162at the second face153of the package substrate102electrically coupled to conductive contacts154of the HG component104by solder bumps148, but any suitable interconnects (e.g., first-level interconnects, posts/pillars, wirebonds, etc.) may be used to couple the HG component104to the package substrate102in any of the embodiments disclosed herein. An underfill material146may be disposed around the solder balls144coupling the TS component106to the package substrate102, and an underfill material152may be disposed around the solder bumps148coupling the HG component104to the package substrate102. An underfill material may provide mechanical support to these interconnects, helping mitigate the risk of cracking or delamination due to differential thermal expansion between the package substrate102and the HG component104/TS component106. In some embodiments, the underfill material146and the underfill material152may have a same material composition, while in other embodiments, the underfill materials146and152may have different material compositions.

As illustrated inFIG.1, and others of the accompanying drawings, conductive contacts156may be disposed at the first face149of the package substrate102, and solder balls158may be disposed thereon. Conductive pathways (not shown) in the package substrate102may electrically couple the conductive contacts162to the conductive contacts142, the conductive contacts162to the conductive contacts156, and/or the conductive contacts142to the conductive contacts156. These conductive pathways may also conductively couple any elements embedded in the package substrate102(not shown) to any of the conductive contacts. In the IC assembly150ofFIG.1, the IC package100is illustrated as coupled to a circuit board108(e.g., a motherboard); in particular, the conductive contacts156may be electrically coupled to conductive contacts160of the circuit board108by the solder balls158(e.g., for a ball grid array (BGA) package), but any suitable interconnects may be used (e.g., pins in a pin grid array (PGA) package or lands in a land grid array (LGA) package). In other IC assemblies, an IC package100(e.g., in accordance with any of the embodiments disclosed herein) may be coupled to another IC package, a package interposer, or any other suitable support that may take the place of the circuit board108. Further, although the IC package100ofFIG.1(and others of the accompanying drawings) includes the components104and106coupled directly to a package substrate102, in any of the embodiments disclosed herein, an intermediate component may be disposed between the components104/106and the package substrate102(e.g., an interposer, a silicon bridge, an organic bridge, etc.). In such embodiments the interposer, silicon bridge, organic bridge, etc., may serve as the package substrate102.

The IC package100may further include a mold compound112disposed around the HG component104and the TS component106, a heat spreader114above the HG component104and the TS component106, and a high thermal conductivity (HTC) material110between the HG component104and the heat spreader114. As shown inFIG.1, the mold compound112may be present between the HG component104and the TS component106, and also between the TS component106and the heat spreader114. The mold compound112may have a lower thermal conductivity than the heat spreader114, and a lower thermal conductivity than the HTC material110; the term “high thermal conductivity” is used to describe the material110to indicate that the material110has a relatively higher thermal conductivity than the mold compound112. In some embodiments, the mold compound112may include an epoxy matrix with one or more filler materials (e.g., silica). In some embodiments, the HTC material110may include a metal (e.g., copper or aluminum), silicon and carbon (e.g., in the form of silicon carbide), matrices of copper and silicon and carbon (e.g., in the form of silicon carbide), matrices of copper and diamond, or any of the thermal interface material (TIM) materials disclosed herein. The thermal conductivity of the HTC material110may be higher than, or lower than, the thermal conductivity of the heat spreader114. The heat spreader114may have high thermal conductivity, and may facilitate the spread of heat away from the HG component104(and toward the heat sink118, as discussed below).

In the IC package100ofFIG.1, the presence of the HTC material110creates a thermal pathway for heat to be transferred away from the HG component104to the heat spreader114, while the mold compound112provides a thermal barrier between the TS component106and the HG component104, between the TS component106and the HTC material110, and between the TS component106and the heat spreader114. Thus, the thermal arrangement ofFIG.1may help insulate the TS component106from heat generated by and conducted through other portions of the IC package100, allowing the thermal performance of the TS component106to stay within a desired range.

The heat spreader114illustrated inFIG.1(and others of the accompanying figures) is shown as substantially planar above the rest of the IC package100, but in any of the embodiments disclosed herein, the heat spreader114may include leg portions that extend toward the package substrate102and are secured to the package substrate102(e.g., as illustrated inFIG.21and discussed below) and/or pedestals, ribs, or other three-dimensional features (e.g., as illustrated inFIG.3and discussed below). In some embodiments, the heat spreader114may be formed in situ above the rest of the IC package100by plating, additive manufacturing, or another technique, while in other embodiments, the heat spreader114may be separately manufactured (e.g., by stamping) and then brought into thermal contact with the rest of the IC package100. In the latter embodiments, a TIM (not shown inFIG.1, but discussed below with reference toFIG.2, for example) may be present between the rest of the IC package100and at least a portion of the heat spreader114. In some embodiments, the heat spreader114may include copper, aluminum, or nickel. In some embodiments, the heat spreader114may include copper plated with nickel (e.g., a layer of nickel having a thickness between 5 microns and 10 microns). In some embodiments, the heat spreader114may include nickel-plated aluminum. In some embodiments, the heat spreader114may include ceramics with good thermal conductivity (e.g., ceramics including diamond, silicon carbide, or aluminum nitride), or any combination of the materials discussed herein.

The dimensions of the elements of the IC package100ofFIG.1(and others of the accompanying figures) may take any suitable values. For example, in some embodiments, a height135of the HG component104(e.g., a PA die) may be between 100 microns and 800 microns. In some embodiments, a width131of the HG component104may be between 0.5 millimeters and 10 millimeters (e.g., between 1 millimeter and 5 millimeters). In some embodiments, a height137of the TS component106(e.g., an AWR die) may be between 100 microns and 800 microns. In some embodiments, a width133of the TS component106may be between 0.5 millimeters and 10 millimeters (e.g., between 1 millimeter and 5 millimeters). In some embodiments, a distance143between the HG component104and the TS component106may be less than 5 millimeters (e.g., between 0.1 millimeter and 5 millimeters). In some embodiments, a thickness197of a heat spreader114may be between 50 microns and 3 millimeters (e.g., between 250 microns and 1 millimeter when the heat spreader114is formed in situ, or between 0.5 millimeters and 3 millimeters when the heat spreader114is separately manufactured). In some embodiments, a thickness141of the mold compound112between the TS component106and the heat spreader114may be greater than 10 microns (e.g., greater than 50 microns).

The IC assembly150ofFIG.1also includes a heat sink118and a TIM116between the heat sink118and the IC package100. The TIM116may aid in the transfer of heat from the IC package100(e.g., from the heat spreader114) to the heat sink118, and the heat sink118may be designed to readily dissipate heat into the surrounding environment, as known in the art (e.g., using fins, as shown). In some embodiments, the TIM116may be a polymer TIM or a solder TIM. Any of the IC packages100disclosed herein may be part of an IC assembly150including a heat sink118and a TIM116.

FIG.1illustrates an IC assembly150including an IC package100; any of the other IC packages100disclosed herein may be incorporated into an IC assembly like the IC assembly150. Further, the subsequent drawings may include a number of elements that are also included inFIG.1or other drawings; any of these elements may take any suitable ones of the forms of those elements discussed herein with reference to any other drawing, and vice versa, and a discussion of these elements may not be repeated.

FIG.2illustrates an IC package100that is similar to the IC package100ofFIG.1, but in which a TIM120is present between the HTC material110and the HG component104, as well as between the HTC material110and the heat spreader114. Such an embodiment may be appropriate when the HTC material110is separately manufactured or prepared, and then positioned above the HG component104(e.g., using a pick-and-place tool). In other embodiments in which the HTC material110is plated or additively manufactured directly on top of the HG component104(not shown inFIG.2), a TIM120may only be present between the HTC material110and the heat spreader114, not between the HTC material110and the HG component104. In some embodiments, the HTC material110may be a piece of foil (e.g., a metal foil), and may have a thickness between 50 microns and 300 microns. The TIM120ofFIG.2may include a polymer TIM, a solder TIM, or a combination thereof. A solder TIM120may include an indium-based solder, such as a pure indium solder or an indium alloy solder (e.g., an indium-tin solder, an indium-silver solder, an indium-gold solder, an indium-nickel solder, or an indium-aluminum solder). In embodiments in which the TIM120includes a solder TIM, the other elements of the IC package100that contact the TIM120(e.g., the HG component104, the HTC material110, and/or the heat spreader114) may have an adhesion material region (not shown) facing the TIM120. The adhesion material region may serve to wet the TIM120, and may include gold, silver, titanium, nickel, and/or indium.

FIG.3illustrates an IC package sharing many characteristics with the IC packages100ofFIGS.1and2, but in which the heat spreader114includes a pedestal168that extends down toward the HG component104. The pedestal168may be a feature that is stamped into the heat spreader114when the heat spreader114is manufactured, or the heat spreader114(including the pedestal168) may be additively manufactured or otherwise formed. A TIM120, which may take the form of any of the TIMs120disclosed herein, may be disposed between the pedestal168and the HG component104to facilitate heat transfer between the HG component104and the heat spreader114.

FIG.4illustrates an IC package100in which the HTC material110extends between the HG component104and the heat spreader114(as discussed above with reference toFIG.1) but also extends laterally around the HG component104(including into the volume between the HG component104and the TS component106). As shown inFIG.4, in some embodiments, the HTC material110may be conformal over the HG component104(and the underfill material152). In some embodiments, a TIM (not shown) may be present between the HG component104and the HTC material110and/or between the HTC material110and the heat spreader114(e.g., as shown inFIG.5). An embodiment like that ofFIG.4may be particularly advantageous when the width131of the HG component104is comparable to or less than the height135; placing the HTC material110around the side faces of such an HG component104may allow an ample amount of heat to be drawn away from the HG component104via the side faces. The HTC material110may be spaced away from the TS component106by intervening mold compound112to preserve some thermal isolation of the TS component106. In some embodiments, the distance109between the HTC material110and the TS component106may be between greater than 50 microns (e.g., greater than 100 microns). As noted above,FIG.5illustrates an IC package100like the IC package100ofFIG.4, but in which a TIM120is present between the HTC material110and the heat spreader114. Such an embodiment may be particularly advantageous when the heat spreader114is separately manufactured, as noted above.

FIG.6illustrates an IC package100similar to the IC package100ofFIG.1, but in which an electrically conductive coating111is in conductive contact with the heat spreader114and with an electrically conductive plane113in the package substrate102. In some embodiments, the plane113may be a ground plane. When the heat spreader114is electrically conductive, the heat spreader114, the coating111, and the plane113together may form an electromagnetic shield around the HG component104, the TS component106, and any other components therein. Such electromagnetic shielding may advantageously mitigate the effects of electromagnetic interference on the HG component104, the TS component106, and any other components therein. In some embodiments, the thickness139of the coating111may be less than 5 microns (e.g., less than 2 microns). The coating111may include any suitable metal (e.g., aluminum, copper, tin, or combinations thereof), and in some embodiments, may include an electrically conductive paste (e.g., a silver-filled epoxy). In some embodiments, the coating111may be sprayed or rolled onto the side faces of the rest of the IC package100, and may make contact with exposed side faces of the plane113at the sides of the package substrate102. Although the electromagnetic shield structure ofFIG.6is illustrated in conjunction with the thermal management arrangements ofFIG.1, the electromagnetic shield structure ofFIG.6may be used in conjunction with any of the thermal management arrangements in any of the IC packages100disclosed herein.

FIG.7illustrates an IC package100similar to the IC package100, but in which electrically conductive through-mold vias (TMVs)115are in conductive contact with the heat spreader114and with an electrically conductive plane113in the package substrate102by way of vias117in the package substrate. When the heat spreader114is electrically conductive, the heat spreader114, the TMVs115, the vias117, and the plane113together may form an electromagnetic shield around the HG component104, the TS component106, and any other components therein, like that illustrated inFIG.6. In some embodiments, the TMVs115may include a conductive material (e.g., a metal, such as copper) and may have a tapered shape, narrowing toward the package substrate102, as shown. The vias117may also include a conductive material (e.g., a metal, such as copper), and may have a tapered shape, narrowing toward the plane113. As shown, the vias117may be arranged in a stack, with intervening pads, as known in the art. Although the electromagnetic shield structure ofFIG.7is illustrated in conjunction with the thermal management arrangements ofFIG.1, the electromagnetic shield structure ofFIG.7may be used in conjunction with any of the thermal management arrangements in any of the IC packages100disclosed herein.

In some embodiments, an IC package100may include a cooling device. Such a cooling device may be active (in that power must be supplied to the cooling device for it to perform a cooling function) or passive (in that cooling may occur without the need for a power supply). An example of an active cooling device that may be included in an IC package100is a thermoelectric cooler (TEC), discussed further below with reference toFIG.26, and an example of a passive cooling device that may be included in an IC package100is a vapor chamber, discussed further below with reference toFIGS.27-42.

FIG.8illustrates an IC package100having a cooling device122between the TS component106and the heat spreader114; a layer of TIM120is disposed between the cooling device122/mold compound112and the heat spreader114. In some embodiments, the cooling device122may be an active device (e.g., a TEC), and power may be supplied to the cooling device122via wirebonds128from the cooling device122to conductive contacts119at the second face153of the package substrate102. In embodiments in which the cooling device122is a passive device (e.g., a vapor chamber), no wirebonds128or conductive contacts119may be present. During operation of the IC package100, the cooling device122may draw heat away from the face193(proximate to the TS component106) and emit that heat at the face195(proximate to the heat spreader114). When the cooling device122includes a TEC, the cooling device122may perform this heat transfer function when it is turned on, and when it is turned off, the cooling device122may have a high thermal resistance (e.g., may have an overall thermal conductivity lower than the TIM120, lower than the heat spreader114, and/or lower than the mold compound112). This high thermal resistance may provide thermal isolation of the TS component106, and thus a TEC cooling device122may provide thermal benefits in both the on- and off-state. If a TEC cooling device122were instead located between the HG component104and the heat spreader114, the low thermal conductivity of the TEC cooling device122in the off-state would block the heat pathway from the HG component104to the heat spreader114, causing excessive heating of the HG component104and increasing the risk of undesirably heating the TS component106.FIG.8does not depict a TIM between the TS component106and the cooling device122; in some such embodiments, the cooling device122may be fabricated directly on top of the TS component106, while in other embodiments, a TIM may be present to provide an interface between the TS component106and a separately fabricated cooling device122.

InFIG.8, the HG component104is shown as having a greater height than the TS component106so that the HG component104may contact the TIM120, but this is simply illustrative, and the HG component104and TS component106may have any relative heights, with any height differences accommodated by intervening TIM120, HTC material110, and/or pedestals168, as discussed above. For example,FIG.9illustrates an IC package100also having a cooling device122between the TS component106and the heat spreader114, and further including an HTC material110between the HG component104and the heat spreader114, as well as additional TIM120between the HG component104and the HTC material110.FIG.9also illustrates a TIM120between the TS component106and the cooling device122, but as discussed above with reference toFIG.8, such a TIM120may or may not be present in an IC package100.

FIG.10illustrates an IC package100like the IC package100ofFIG.9, but in which electrical connections between the cooling device122and the package substrate102(when present) are provided by TMVs123through the mold compound112between the cooling device122and conductive contacts121of the package substrate102, instead of through wirebonds128. In some embodiments, the TMVs123may have a diameter between 50 microns and 500 microns. Electrical connections between the cooling device122and the package substrate102ofFIG.8may also be made by TMVs123, instead of by wirebonds128.

FIG.11illustrates an IC package100like the IC package100ofFIGS.9and10, but in which electrical connections between the cooling device122and the package substrate102(when present) are provided by electrical pathways125through the TS component106. The electrical pathways125are shown inFIG.11as taking the form of vias, but this is simply for ease of illustration, and any suitable conductive structures may provide the electrical pathways125. Electrical connections between the cooling device122and the package substrate102ofFIG.8may also be made by electrical pathways125through the TS component106, instead of by wirebonds128.

FIG.12illustrates an IC package100having a cooling device122embedded in the package substrate102in the shadow of the TS component106. A layer of TIM120is disposed between the HG component104/TS component106and the heat spreader114. In some embodiments, the cooling device122may be an active device (e.g., a TEC), and power may be supplied to the cooling device122via conductive pathways (not shown) in the package substrate102. In embodiments in which the cooling device122is a passive device (e.g., a vapor chamber), no such conductive pathways may be present. Thermal vias127may be disposed between the cooling device122and the first face149of the package substrate102; these thermal vias127may include vias, pads, and/or lines in the package substrate102, and may serve as thermal pathways to dissipate heat (and may not, for example, be coupled to any signal or power/ground pathways). In particular, during operation of the IC package100, the cooling device122may draw heat away from the face193(proximate to the TS component106) and emit that heat at the face195(proximate to the thermal vias127). The thermal vias127may help transfer the heat to the first face149of the package substrate102, where it may dissipate. AlthoughFIG.12(and others of the accompanying drawings) illustrates the thermal vias127in contact with the face195of the cooling device122, this need not be the case, and the thermal vias127may be spaced apart from the face195(e.g., by one or more intervening layers of the package substrate102) while still performing their thermal function. In an embodiment in which heat transfer is desirable between the TS component106and the package substrate102(e.g., to the cooling device122in the package substrate102), the underfill material146may be selected to have a higher thermal conductivity than the mold compound112and/or the underfill material152(e.g., the underfill material146may be an epoxy material with fillers having a higher thermal conductivity than fillers included in the mold compound112and/or the underfill material152, such as aluminum oxide or boron nitride fillers). Further, thermal vias127(not shown) in the package substrate102may be located between the TS component106and the cooling device122, and may also be located between the TS component106and the first face149of the package substrate102without being in a shadow of the cooling device122(e.g., as discussed below with reference toFIG.16).

In the embodiment ofFIG.12, the cooling device122is spaced apart from the second face153of the package substrate102(e.g., by one or more intervening layers of the package substrate102). In other embodiments, the cooling device122may be located at the second face153of the package substrate102. For example,FIG.13illustrates an IC package100like the IC package100ofFIG.12, but in which the cooling device122(which may be an active or passive cooling device, as discussed above) has a top surface that is coplanar with the second face153of the package substrate102; in other embodiments, a top surface of the cooling device122may be above the second face153of the package substrate102. As discussed above with reference toFIG.12, the embodiment ofFIG.13may also include thermal vias127between the cooling device122and the first face149of the package substrate102.

In some embodiments of the IC packages100disclosed herein, a thermal arrangement in an IC package100may include thermal management structures proximate to top and bottom faces of the HG component104(e.g., in addition to or instead of the thermal management structures proximate to a TS component106, as described herein). For example,FIG.14illustrates an IC package100in which thermal vias127are disposed in the shadow of the HG component104, between the HG component104and the first face149of the package substrate102, to draw heat away from the bottom face of the HG component104. The thermal vias127may be spaced apart from the second face153of the package substrate102, as shown, or may begin at second face153of the package substrate102. Additionally, a heat spreader114is located proximate to the top face of the HG component104(e.g., in direct contact with the top face of the HG component104, as illustrated inFIG.14), to draw heat away from the top face of the HG component. In an embodiment in which heat transfer is desirable between the HG component104and the package substrate102(e.g., to thermal vias127in the package substrate102), the underfill material152may be selected to have a higher thermal conductivity than the mold compound112and/or the underfill material146(e.g., the underfill material152may be an epoxy material with fillers having a higher thermal conductivity than fillers included in the mold compound112and/or the underfill material146, such as aluminum oxide or boron nitride fillers).

FIG.15illustrates an IC package100like the IC package100ofFIG.14, but in which a layer of TIM120is disposed between the HG component104/TS component106and the heat spreader114. In some embodiments, the TIM120may be present between the HG component104and the heat spreader114(to facilitate heat transfer from the HG component104to the heat spreader114) but not between the TS component106and the heat spreader114(to help with thermal isolation of the TS component106from the heat spreader114).

FIG.16illustrates an IC package100having a cooling device122(e.g., an active or passive device) embedded in the package substrate102in the shadow of the HG component104. A layer of TIM120is disposed between the HG component104/TS component106and the heat spreader114. Thermal vias127may be disposed between the cooling device122and the first face149of the package substrate102, and additional thermal vias127may be disposed between the HG component104and the first face149of the package substrate102, but laterally offset from the cooling device122(as noted above with reference toFIG.12). As discussed above, the underfill material152may be selected to have a higher thermal conductivity than the mold compound112and/or the underfill material146, and the underfill material146may be selected to have a lower thermal conductivity than the mold compound112and/or the underfill material152.

FIG.17illustrates an IC package100that is similar to the IC package100ofFIG.16, but which further includes an HTC material110between the HG component104and the heat spreader114(with mold compound112between the TS component106and the heat spreader114), as discussed above with reference toFIG.1. Including the HTC material110may enhance heat transfer from the top surface of the HG component104to the heat spreader114(via the TIM120), and may make room for additional mold compound112between the TS component106and the heat spreader114(to provide further thermal isolation for the TS component106). In some embodiments, a layer of TIM120(not shown) may be present between the HG component104and the HTC material110. This is one example of a combination of the various embodiments illustrated herein; as noted above, any suitable ones of the embodiments disclosed herein may be combined to provide a thermal management arrangement within the scope of this disclosure.

FIG.18illustrates an IC package100that is similar to the IC package100ofFIG.17, but which further includes a cooling device122between the TS component106and the heat spreader114, as discussed above with reference toFIG.8. Including the additional cooling device122between the TS component106and the heat spreader114may enhance heat removal from the TS component106(and, when the additional cooling device122is a TEC, may enhance thermal isolation between the TS component106and the HG component104when the TEC is off). In some embodiments, a layer of TIM120(not shown) may be present between the TS component106and the additional cooling device122. This is another example of a combination of the various embodiments illustrated herein; as noted above, any suitable ones of the embodiments disclosed herein may be combined to provide a thermal management arrangement within the scope of this disclosure.

FIG.19illustrates an IC package100that is similar to the IC package100ofFIG.18, but in which electrical connections to the cooling device122above the TS component106are provided by TMVs123through the mold compound112between the cooling device122and conductive contacts121of the package substrate102(e.g., as discussed above with reference toFIG.10), instead of through wirebonds128.

FIG.20illustrates an IC package100in which the TS component106is disposed at the first face149of the package substrate102, and the HG component104is disposed at the second face153of the package substrate102.FIG.20illustrates the TS component106in the shadow of the HG component104(and vice versa), but this need not be the case; for example, the TS component106and the HG component104may be laterally offset with respect to each other. In the IC package100ofFIG.20, the package substrate102itself may provide some amount of thermal isolation between the TS component106and the HG component104. A heat spreader114may be conformally disposed over the HG component104(e.g., using any of the deposition or additive manufacturing techniques discussed herein) to draw heat away from the HG component104from the top and side faces, as well as from the package substrate102(to further reduce the thermal crosstalk between the HG component104and the TS component106). The underfill material146and/or the underfill material152may be selected to have a lower thermal conductivity than a dielectric of the package substrate102, in order to provide additional thermal isolation to the TS component106. The solder balls158(or other interconnects, as discussed above) may have a height161that is large enough so that the solder balls158may couple the IC package100to another component (e.g., a circuit board108, as discussed above with reference toFIG.1) while accommodating the TS component106. The IC package100ofFIG.20may have a greater z-height than IC packages100in which the HG component104and the TS component106are both coupled to the second face153of the package substrate, but may have a smaller x-y footprint.

FIG.21illustrates an IC package100like the IC package100ofFIG.20, but in which the heat spreader114is not conformal over the HG component104. Instead, the heat spreader114may be a separately manufactured element that is in thermal contact with the HG component104by way of an intervening layer of TIM120. The heat spreader114may have legs that are coupled to the second face153of the package substrate102by a sealant129. The sealant129may have gaps (not shown) around the perimeter of the heat spreader114, to allow any gas generated during solder reflow to escape.

FIG.22illustrates an IC package100like the IC package100ofFIG.20, but which further includes one or more cooling devices122in the package substrate102. The particular number and arrangement of cooling devices122in the package substrate102is simply illustrative, and any number and arrangement may be used. Thermal vias127may be disposed between the cooling devices122and the second face153of the package substrate102, drawing heat away from the faces195of the cooling devices122and directing this heat toward the conformal heat spreader114. Further, thermal vias127(not shown) in the package substrate102may be located between the TS component106and the cooling devices122.

A number of examples of TS components106are disclosed herein, including resonator components that may be used in RF devices.FIG.23is a side, cross-sectional view of an example resonator component191that may serve as the TS component106in any of the IC packages100herein. The resonator component191may include a lid126having a first face151to which one or more resonator units107are attached. A resonator unit107may include a base138, a resonator103(e.g., an AWR) coupled to the base, and side walls101that couple the base138to the lid126. The base138, side walls101, and lid126may define a hermetically sealed cavity105into which the resonator103extends. The cavity105may be under vacuum, or may include a gas (e.g., air). The resonator103may include a piezoelectric material, and thus mechanical deformation of the resonator103may be associated with the generation of electrical signals. A mold compound124may be disposed around the resonator units107. Conductive contacts140of the resonator component191(shown in dashed lines) may be arranged in any of a number of ways; the conductive contacts140may include conductive contacts140A at a second face189of the lid126and/or conductive contacts1408at a face of the base138or mold compound124. In some embodiments, the lid126may include portions that extend beyond the resonator units (as shown in dashed lines), and in some such embodiments, conductive contacts140C of the resonator component191may be disposed at the first face151of the lid126in these portions. Conductive pathways (not shown) may run through the lid126, the side walls101, the base138, and/or the mold compound124between the resonators103and the conductive contacts140.

The dimensions of the resonator component191may take any suitable values. In some embodiments, a height159(the sum of the heights of the base138and the cavity105) may be between 50 microns and 500 microns. In some embodiments, a height157of the lid126may be between 50 microns and 500 microns. In some embodiments, a height155of the resonator component191may be between 100 microns and 1 millimeter. In some embodiments, a height155of the resonator component191may be less than 300 microns. In an IC package100, the resonator component191may have its temperature monitored and its operation stabilized by temperature compensation circuits, which may calibrate the frequency of the resonator component191as a function of temperature within a narrow temperature range. These temperature compensation circuits may be part of a TS component106that includes the resonator component191. The thermal arrangements disclosed herein may decrease the risk that the temperature of a resonator component191exceeds the narrow range in which the temperature compensation circuits may successfully operate, improving the reliability and performance of the resonator component191(and, for example, any filters relying on the resonator component191, as discussed below with reference toFIG.47).

FIG.24illustrates an example IC package100including an IC assembly163coupled to a package substrate102. The IC assembly163includes the resonator component191ofFIG.23and an HG component104(e.g., a PA). In the IC assembly163, the lid126of the resonator component191includes conductive contacts140A at the second face189of the lid126, as well as conductive contacts140C at the first face151of the lid126. The HG component104is coupled to the conductive contacts140A by solder bumps166(or another interconnect), and an underfill material164is disposed between the HG component104and the lid126. The underfill material164may be selected to have a relatively low thermal conductivity to help thermally isolate the HG component104from the resonators103of the resonator component191. Further, the lid126may be formed from a low thermal conductivity material (e.g., a glass or low thermal conductivity ceramic) to provide further thermal isolation. The IC assembly163may be coupled to a package substrate102by solder balls144(or other interconnects) between the conductive contacts140C and the conductive contacts142; the height of the solder balls144may be selected to accommodate the portion of the resonator component191below the lid126. The IC assembly163may be manufactured, sold, or otherwise handled, and may later be packaged by securing the IC assembly163to the package substrate102; in other embodiments, the IC assembly163may not be secured to a package substrate102, but may instead be included in an electronic device in any other suitable manner. An embodiment like that ofFIG.24may be useful in settings in which decreasing the size of the IC package100is particularly important, and/or when functionality is improved and/or cost is decreased by having the resonator component191and the HG component104integrated into one IC assembly163, even at the expense of potentially greater thermal crosstalk.

FIG.25illustrates an IC package100like that ofFIG.24, but in which the package substrate102includes one or more cooling devices122(e.g., one cooling device122per resonator unit107) in the shadow of the resonator component191. A portion of TIM120is disposed between each resonator unit107and the package substrate102to facilitate thermal transfer between the resonator component191and the cooling devices122. Thermal vias127may be disposed between the cooling devices and the first face149of the package substrate102. In some embodiments, the TIM120between the resonator component191and the package substrate102may be a continuous layer, rather than separate portions under each resonator unit107. In some embodiments, the cooling devices122may not be disposed at the second face153of the package substrate102, but may be spaced apart from the second face153(as discussed above).FIG.25also illustrates underfill material170disposed around the solder balls144(or other interconnects. In other embodiments, the package substrate102may include additional thermal vias127(e.g., between the resonator component191and the cooling devices122, or lateral to the cooling devices122), or may include thermal vias127instead of cooling devices122. In the embodiment ofFIG.25, the IC assembly163may be the same as the IC assembly163ofFIG.24, but the IC assembly163is packaged differently (including a different package substrate102). In some embodiments, the base138of each resonator unit may be in direct contact with TIM120(i.e., there is no mold compound between the base138and the TIM120).

As noted above, in some embodiments, the cooling device122included in an IC package100may be a TEC.FIG.26is a side, cross-sectional view of an example TEC172that may be included in any of the thermal management arrangements disclosed herein (e.g., serving as the cooling device122). The TEC172ofFIG.26includes alternating portions of p-type thermoelectric material and n-type thermoelectric material, with electrodes174coupling adjacent portions. The thermoelectric materials may include bismuth telluride, bismuth selenide, or antimony telluride, for example. A thermal insulator182may be disposed around the p- and n-type thermoelectric material portions, as shown, and conductive contacts178may be present at either end of the p/n “chain.” These conductive contacts178may be used for wirebonding, solder attachment, or other electrical interconnects. In some embodiments, the TEC172may be fabricated directly on another component (e.g., with the surface176of the TEC172in contact with a TS component106, as illustrated inFIG.8), while in other embodiments, the TEC172may be fabricated separately and then later integrated into an IC package100(e.g., with a TIM120providing a thermal interface). In some embodiments, a height145of the TEC172may be less than 500 microns (e.g., less than 100 microns).

As noted above, in some embodiments, the cooling device122included in an IC package100may be a vapor chamber.FIG.27is a side, cross-sectional view of an example vapor chamber180that may be included in any of the thermal management arrangements disclosed herein (e.g., serving as the cooling device122). The vapor chamber180may include a condenser130, an evaporator132, and side walls186between the condenser130and the evaporator132, all defining a vapor space196. The side walls186may provide a good seal with the condenser130and the evaporator132; in some embodiments, the side walls186may include solder or an impermeable adhesive. The evaporator132may include a uniform wick region134extending into the vapor space196, and the side walls186may include wick regions184extending into the vapor space196; the wicks in the wick region134may have a uniform structure across the interior surface of the evaporator132. A fluid (e.g., water, not shown) may also be disposed in the vapor space196; when the evaporator132is heated (e.g., by a heat source located proximate to the evaporator132), the fluid proximate to the wick region134may evaporate and flow toward the condenser130. The fluid may condense on the “cooler” condenser130, and then may flow laterally along the condenser130and be wicked back down to the evaporator132via the wick regions184and the wick region134. In some embodiments, the vapor chamber180(or any of the vapor chambers disclosed herein) may have a height147between 200 microns and 3 millimeters.

FIG.28is a side, cross-sectional view of an example vapor chamber190, which may be included in any of the thermal management arrangements disclosed herein (e.g., serving as the cooling device122). Like the vapor chamber180ofFIG.27, the vapor chamber190may include a condenser130, an evaporator132, and side walls186between the condenser130and the evaporator132, all defining a vapor space196. The evaporator132may include a uniform wick region134extending into the vapor space196, but in contrast to the vapor chamber180ofFIG.27, the side walls186may not include wicks extending into the vapor space196. The wicks of the wick region134of the vapor chamber190may have a uniform structure across the interior surface of the evaporator132. Further, the vapor chamber190may include a superhydrophobic material188at the interior face of the condenser130, as well as a superhydrophilic material175at the interior face of the evaporator132(e.g., in the wick region134). A fluid (e.g., water, not shown) may also be disposed in the vapor space196; when the evaporator132is heated (e.g., by a heat source located proximate to the evaporator132), the fluid proximate to the wick region134may evaporate and flow toward the condenser130. The superhydrophobic material188of the condenser130may cause the condensed fluid to be quickly repelled from the condenser130when the condensed fluid droplets reach a certain size, so that the condensed fluid may be said to “jump” back to the evaporator132. The vapor chamber190may thus be referred to as a jumping drops vapor chamber.

FIG.29is a side, cross-sectional view of another example jumping drops vapor chamber192. Like the vapor chamber190ofFIG.28, the vapor chamber192may include a condenser130, an evaporator132, and side walls186between the condenser130and the evaporator132, all defining a vapor space196. The vapor chamber192may also include a superhydrophobic material188at the interior face of the condenser130, as well as a superhydrophilic material175at the interior face of the evaporator132. A fluid (e.g., water, not shown) may also be disposed in the vapor space196. In contrast to the vapor chamber190(and in contrast to the vapor chamber180), the evaporator132may include a non-uniform wick region136extending into the vapor space196. In particular, the non-uniform wick region136may include subregions whose wicks have different characteristics (e.g., height, width, spacing, volume fraction, etc., as discussed below) than the wicks in other subregions. The characteristics of the wicks in a particular subregion of the non-uniform wick region136may be selected based on, among other factors, the power density of the heat source that will be proximate to that subregion when the vapor chamber192is included in an IC package100(examples of which are discussed below). For example, the amount of fluid that the non-uniform wick region136can hold is proportional to the height of the wicks, and the holding of an adequate amount of fluid by the wicks is critical to thermal performance of the vapor chamber192. If an inadequate volume of water is held in the non-uniform wick region136, the wicks may be said to “dry out” and the vapor chamber192may be unable to adequate transfer heat from the evaporator132to the condenser130. However, the taller the wicks in the non-uniform wick region136, the greater the thermal resistance presented by the wicks themselves and by the excess fluid.

The non-uniform wick regions136disclosed herein may balance the demand for adequate fluid at the evaporator132with the demand for low thermal resistance at the evaporator132by having different subregions of the non-uniform wick region136have different properties. For example, a non-uniform wick region136may include one or more fine wick subregions136A and one or more coarse wick subregions136B. The terms “fine” and “coarse” are used here to refer to the critical dimensions (e.g., height, width, pitch, etc.) of wicks in the subregions; a fine wick subregion136A may have shorter, narrower, more closely spaced wicks than a coarse wick subregion136B. Different fine wick subregions136A included in an evaporator132may have different wick properties, and different coarse wick subregions136B may have different wick properties. A non-uniform wick region136may include a fine wick subregion136A where a HPD component (e.g., an HG component104, such as a PA) is in the shadow of the fine wick subregion136A in an IC package100(as illustrated inFIGS.39and40, and discussed further below), and may include a coarse wick subregion136B where a LPD component (e.g., a TS component106, such as a resonator) is in the shadow of the coarse wick subregion136B in an IC package100. The fine wick subregion136A “above” the HPD component may provide low thermal resistance (and thereby produce a lower temperature) proximate to the HPD component, while the coarse wick subregion136B “above” the LPD component may provide a greater fluid reservoir to help mitigate the risk of dry out of the fine wick subregion136A. Because the coarse wick subregion136B is “above” the LPD component, the greater thermal resistance of the coarse wick subregion136B may be an acceptable cost for the benefit of a greater fluid reservoir.FIGS.30-32illustrate some example arrangements of fine wick subregions136A and coarse wick subregions136B in a non-uniform wick region136of a vapor chamber192; these are simply illustrative, and any non-uniform wick region136may include any number and arrangement of subregions with different wick properties.

In some embodiments, a non-uniform wick region136may include one or more subregions in which the wicks are provided by pillars of a thermally conductive material (e.g., a metal, such as copper). The volume fraction of the wicks in such a subregion may be associated with the diameter, height, and pitch of the pillars.FIGS.33-35illustrate examples of vapor chambers192having pillar wicks in various arrangements of fine wick subregions136A and coarse wick subregions136B, corresponding to the vapor chambers192ofFIGS.30-32, respectively. In some embodiments, the diameter185of the pillars in a fine wick subregion136A may be between 1 micron and 100 microns. In some embodiments, the pitch171of the pillars in a fine wick subregion136A may be between 2 microns and 150 microns. In some embodiments, the height169of the pillars in a fine wick subregion136A may be between 1 micron and 50 microns. In some embodiments, the diameter165of the pillars in a coarse wick subregion136B may be between 10 microns and 500 microns. In some embodiments, the pitch173of the pillars in a coarse wick subregion1368may be between 15 microns and 1000 microns. In some embodiments, the height167of the pillars in a coarse wick subregion1368may be between 10 microns and 500 microns. In some embodiments, the height:diameter aspect ratio of pillar wicks may be between 10:1 and 1:10. In some embodiments, the volume fraction of pillar wicks may be between 25% and 75%.

In some embodiments, a non-uniform wick region136may include one or more subregions in which the wicks are provided by sintered particles of a thermally conductive material (e.g., a metal, such as copper). The fluid retention in the wicks in such a subregion may be associated with the size of the particles and the porosity of the sintered mass; smaller particles (and lower porosity) may cause the retention of less fluid, while larger particles (and higher porosity) may cause the retention of more fluid.FIGS.36-38illustrate examples of vapor chambers192having sintered particle wicks in various arrangements of fine wick subregions136A and coarse wick subregions1368, corresponding to the vapor chambers192ofFIGS.30-32, respectively. In some embodiments, the diameter of the particles in a fine wick subregion136A may be between 1 micron and 25 microns, while the diameter of the particles in a coarse wick subregion1368may be between 30 microns and 500 microns. In some embodiments, the total height of the sintered particles in a coarse wick subregion1368may be greater than the total height of the sintered particles in a fine wick subregion136A, as shown inFIGS.36-38. In some embodiments, the volume fraction of sintered particle wicks may be between 25% and 75%. In some embodiments, a non-uniform wick region136may include one or more subregions having pillar wicks, and one or more subregions having sintered particle wicks, in any desired arrangement.

As noted above, the vapor chambers disclosed herein (e.g., the vapor chambers192) may be included in an IC package100. For example,FIGS.39and40illustrate IC packages100having an HG component104between two TS components106. InFIG.39, a vapor chamber192may be fabricated directly above the HG component104/TS components106/mold compound112(e.g., using an additive manufacturing process), with the HG component104in the shadow of a fine wick subregion136A and the TS components106in the shadows of corresponding coarse wick subregions1368. The IC package100ofFIG.40is similar to the IC package100ofFIG.39, but includes a layer of TIM120between the HG component104/TS components106/mold compound112and the vapor chamber192; such an embodiment may be appropriate when the vapor chamber192is separately manufactured.

The elements ofFIGS.39and40may take any suitable form (e.g., any of the forms disclosed herein), and the IC packages100ofFIGS.39and40may further include any of the thermal arrangements disclosed herein. For example, the package substrate102of the IC packages100ofFIGS.39and40may include thermal vias127, cooling devices122, etc. The wick regions134of the vapor chambers180and190(as well as the vapor chamber187, discussed below) may take the form of any of the wick subregions discussed above with reference to the vapor chamber192. Further, the vapor chamber192, in some embodiments, may not include the superhydrophobic material188or the superhydrophilic material175, and/or may include wick regions184on the side walls186; in such embodiments, the vapor chamber192may no longer be considered a “jumping drops” vapor chamber, but may include the non-uniform wick region136.

FIG.41illustrates an example vapor chamber187that may be included in any of the IC packages100disclosed herein. Like the vapor chambers190and192ofFIGS.28and29, respectively, the vapor chamber187may include a condenser130, an evaporator132, and side walls186between the condenser130and the evaporator132, all defining a vapor space196. The vapor chamber187may also include a superhydrophobic material188at the interior face of the condenser130, as well as a superhydrophilic material175at the interior face of the evaporator132. A fluid (e.g., water, not shown) may also be disposed in the vapor space196. In contrast to the vapor chambers190and192, the evaporator132may include sloped surface portions194(formed of the same material as the rest of the evaporator132, e.g., copper), which provide a sloped surface (e.g., linear, as illustrated inFIG.41, curved, polygonal, or having another shape) between the side walls186and the wick region134of the evaporator132. The concave surface of the evaporator132(including the sloped surface portions194), in conjunction with gravity, may accelerate the return of the condensed fluid from outside the wick region134to the wick region134, improving thermal performance by increasing the rate of fluid replenishment in the wick region134. A vapor chamber187including sloped surface portions194may be particularly advantageous in devices that maintain a fixed orientation in space so that gravity may reliably act to pull the condensed fluid down the sloped surface portions194to the wick region134. Such devices may include server computing devices, base stations, or other devices that typically remain stationary and in a predictable orientation relative to the force of gravity. The wick region134may take the form of any of the wick regions disclosed herein; in some embodiments, the wick region134may be a non-uniform wick region136, as discussed above. Further, the vapor chamber187, in some embodiments, may not include the superhydrophobic material188or the superhydrophilic material175, and/or may include wick regions184on the side walls186; in such embodiments, the vapor chamber187may no longer be considered a “jumping drops” vapor chamber, but may include the sloped surface portions194.

When the vapor chamber187ofFIG.41is included in an IC package100, an HPD component may be advantageously located in the shadow of the wick region134, while LPD components may be located in the shadow of the sloped surface portions194. The wick region134“above” the HPD component may provide low thermal resistance (and thereby enable greater thermal transfer) proximate to the HPD component, while the sloped surface portions194“above” the LPD component may aid in the return of fluid to the wick region134. Because the sloped surface portions194are “above” the LPD components, the greater thermal resistance of the sloped surface portions194may be an acceptable cost for the benefit of mitigated dry out risk in the wick region134.

FIG.42illustrates an IC package100having an HG component104between two TS components106. InFIG.42, a vapor chamber187may be fabricated directly above the HG component104/TS components106/mold compound112(e.g., using an additive manufacturing process), with the HG component104in the shadow of the wick region134and the TS components106in the shadows of the sloped surface portions194. In other embodiments, a layer of TIM120may be present between the HG component104/TS components106/mold compound112and the vapor chamber187; such an embodiment may be appropriate when the vapor chamber187is separately manufactured. The elements ofFIG.42may take any suitable form (e.g., any of the forms disclosed herein), and the IC package100ofFIG.42may further include any of the thermal arrangements disclosed herein. For example, the package substrate102of the IC package100ofFIG.42may include thermal vias127, cooling devices122, etc. In some embodiments, an IC package100including any of the vapor chambers disclosed herein may not include a heat spreader114; the vapor chamber may take the place of a heat spreader114.

The IC packages100and vapor chambers disclosed herein may include, or may be included in, any suitable electronic component.FIGS.43-47illustrate various examples of apparatuses that may be included in any of the IC packages100disclosed herein, or may include any of the IC packages100or vapor chambers disclosed herein.

FIG.43is a top view of a wafer1500and dies1502that may be included in an IC package100, in accordance with various embodiments. For example, a die1502may be, or may be included in, an HG component104or a TS component106. The wafer1500may be composed of semiconductor material and may include one or more dies1502having IC structures formed on a surface of the wafer1500. Each of the dies1502may be a repeating unit of a semiconductor product that includes any suitable IC. After the fabrication of the semiconductor product is complete, the wafer1500may undergo a singulation process in which the dies1502are separated from one another to provide discrete “chips” of the semiconductor product. The die1502may include one or more transistors (e.g., some of the transistors1640ofFIG.44, discussed below) and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components. In some embodiments, the wafer1500or the die1502may include a PA, one or more resonators, one or more switches, one or more lasers (e.g., VCSELS), a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die1502. For example, a memory array formed by multiple memory devices may be formed on a same die1502as a processing device (e.g., the processing device1802ofFIG.46) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

FIG.44is a side, cross-sectional view of an IC device1600that may be included in an IC package100, in accordance with various embodiments. For example, the IC device1600may be included in a die1502. One or more of the IC devices1600may be included in one or more dies1502(FIG.43). The IC device1600may be formed on a substrate1602(e.g., the wafer1500ofFIG.43) and may be included in a die (e.g., the die1502ofFIG.43). The substrate1602may be a semiconductor substrate composed of semiconductor material systems including, for example, n-type or p-type materials systems (or a combination of both). The substrate1602may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the substrate1602may be formed using alternative materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II-VI, III-V, or IV may also be used to form the substrate1602. Although a few examples of materials from which the substrate1602may be formed are described here, any material that may serve as a foundation for an IC device1600may be used. The substrate1602may be part of a singulated die (e.g., the dies1502ofFIG.43) or a wafer (e.g., the wafer1500ofFIG.43).

The IC device1600may include one or more device layers1604disposed on the substrate1602. The device layer1604may include features of one or more transistors1640(e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate1602. The device layer1604may include, for example, one or more source and/or drain (S/D) regions1620, a gate1622to control current flow in the transistors1640between the S/D regions1620, and one or more S/D contacts1624to route electrical signals to/from the S/D regions1620. The transistors1640may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors1640are not limited to the type and configuration depicted inFIG.44and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Planar transistors may include bipolar junction transistors (BJT), heterojunction bipolar transistors (HBT), or high-electron-mobility transistors (HEMT). Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors.

Each transistor1640may include a gate1622formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.

The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor1640is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).

In some embodiments, when viewed as a cross-section of the transistor1640along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

The S/D regions1620may be formed within the substrate1602adjacent to the gate1622of each transistor1640. The S/D regions1620may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate1602to form the S/D regions1620. An annealing process that activates the dopants and causes them to diffuse farther into the substrate1602may follow the ion-implantation process. In the latter process, the substrate1602may first be etched to form recesses at the locations of the S/D regions1620. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions1620. In some implementations, the S/D regions1620may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions1620may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions1620.

Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., the transistors1640) of the device layer1604through one or more interconnect layers disposed on the device layer1604(illustrated inFIG.44as interconnect layers1606-1610). For example, electrically conductive features of the device layer1604(e.g., the gate1622and the S/D contacts1624) may be electrically coupled with the interconnect structures1628of the interconnect layers1606-1610. The one or more interconnect layers1606-1610may form a metallization stack (also referred to as an “ILD stack”)1619of the IC device1600.

The interconnect structures1628may be arranged within the interconnect layers1606-1610to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures1628depicted inFIG.44). Although a particular number of interconnect layers1606-1610is depicted inFIG.44, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

In some embodiments, the interconnect structures1628may include lines1628aand/or vias1628bfilled with an electrically conductive material such as a metal. The lines1628amay be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate1602upon which the device layer1604is formed. For example, the lines1628amay route electrical signals in a direction in and out of the page from the perspective ofFIG.44. The vias1628bmay be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate1602upon which the device layer1604is formed. In some embodiments, the vias1628bmay electrically couple lines1628aof different interconnect layers1606-1610together.

The interconnect layers1606-1610may include a dielectric material1626disposed between the interconnect structures1628, as shown inFIG.44. In some embodiments, the dielectric material1626disposed between the interconnect structures1628in different ones of the interconnect layers1606-1610may have different compositions; in other embodiments, the composition of the dielectric material1626between different interconnect layers1606-1610may be the same.

A first interconnect layer1606may be formed above the device layer1604. In some embodiments, the first interconnect layer1606may include lines1628aand/or vias1628b, as shown. The lines1628aof the first interconnect layer1606may be coupled with contacts (e.g., the S/D contacts1624) of the device layer1604.

A second interconnect layer1608may be formed above the first interconnect layer1606. In some embodiments, the second interconnect layer1608may include vias1628bto couple the lines1628aof the second interconnect layer1608with the lines1628aof the first interconnect layer1606. Although the lines1628aand the vias1628bare structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer1608) for the sake of clarity, the lines1628aand the vias1628bmay be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.

A third interconnect layer1610(and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer1608according to similar techniques and configurations described in connection with the second interconnect layer1608or the first interconnect layer1606. In some embodiments, the interconnect layers that are “higher up” in the metallization stack1619in the IC device1600(i.e., farther away from the device layer1604) may be thicker.

The IC device1600may include a solder resist material1634(e.g., polyimide or similar material) and one or more conductive contacts1636formed on the interconnect layers1606-1610. InFIG.44, the conductive contacts1636are illustrated as taking the form of bond pads. The conductive contacts1636may be electrically coupled with the interconnect structures1628and configured to route the electrical signals of the transistor(s)1640to other external devices. For example, solder bonds may be formed on the one or more conductive contacts1636to mechanically and/or electrically couple a chip including the IC device1600with another component (e.g., a circuit board). The IC device1600may include additional or alternate structures to route the electrical signals from the interconnect layers1606-1610; for example, the conductive contacts1636may include other analogous features (e.g., posts) that route the electrical signals to external components.

FIG.45is a side, cross-sectional view of an IC assembly1700that may include one or more IC packages100and/or vapor chambers, in accordance with various embodiments. For example, any of the IC packages included in the IC assembly1700may be an IC package100including any of the thermal arrangements (or combination of thermal arrangements) disclosed herein. The IC assembly1700includes a number of components disposed on a circuit board1702(which may be, e.g., a motherboard). The IC assembly1700includes components disposed on a first face1740of the circuit board1702and an opposing second face1742of the circuit board1702; generally, components may be disposed on one or both faces1740and1742.

In some embodiments, the circuit board1702may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board1702. In other embodiments, the circuit board1702may be a non-PCB substrate.

The IC assembly1700illustrated inFIG.45includes a package-on-interposer structure1736coupled to the first face1740of the circuit board1702by coupling components1716. The coupling components1716may electrically and mechanically couple the package-on-interposer structure1736to the circuit board1702, and may include solder balls (as shown inFIG.45), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure1736may include an IC package1720coupled to a package interposer1704by coupling components1718. The coupling components1718may take any suitable form for the application, such as the forms discussed above with reference to the coupling components1716. Although a single IC package1720is shown inFIG.45, multiple IC packages may be coupled to the package interposer1704; indeed, additional interposers may be coupled to the package interposer1704. The package interposer1704may provide an intervening substrate used to bridge the circuit board1702and the IC package1720. The IC package1720may be or include, for example, a die (the die1502ofFIG.43), an IC device (e.g., the IC device1600ofFIG.44), or any other suitable component. Generally, the package interposer1704may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the package interposer1704may couple the IC package1720(e.g., a die) to a set of BGA conductive contacts of the coupling components1716for coupling to the circuit board1702. In the embodiment illustrated inFIG.45, the IC package1720and the circuit board1702are attached to opposing sides of the package interposer1704; in other embodiments, the IC package1720and the circuit board1702may be attached to a same side of the package interposer1704. In some embodiments, three or more components may be interconnected by way of the package interposer1704.

In some embodiments, the package interposer1704may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the package interposer1704may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the package interposer1704may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The package interposer1704may include metal lines1710and vias1708, including but not limited to through-silicon vias (TSVs)1706. The package interposer1704may further include embedded devices1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as RF devices, PAs, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the package interposer1704. The package-on-interposer structure1736may take the form of any of the package-on-interposer structures known in the art.

The IC assembly1700may include an IC package1724coupled to the first face1740of the circuit board1702by coupling components1722. The coupling components1722may take the form of any of the embodiments discussed above with reference to the coupling components1716, and the IC package1724may take the form of any of the embodiments discussed above with reference to the IC package1720.

The IC assembly1700illustrated inFIG.45includes a package-on-package structure1734coupled to the second face1742of the circuit board1702by coupling components1728. The package-on-package structure1734may include an IC package1726and an IC package1732coupled together by coupling components1730such that the IC package1726is disposed between the circuit board1702and the IC package1732. The coupling components1728and1730may take the form of any of the embodiments of the coupling components1716discussed above, and the IC packages1726and1732may take the form of any of the embodiments of the IC package1720discussed above. The package-on-package structure1734may be configured in accordance with any of the package-on-package structures known in the art. Further, any of the vapor chambers disclosed herein (e.g., the vapor chambers192and187) may be included in any suitable location in an IC assembly1700.

FIG.46is a block diagram of an example electrical device1800that may include one or more IC packages100or vapor chambers, in accordance with various embodiments. For example, any suitable ones of the components of the electrical device1800may include one or more of the IC assemblies150/1700, IC packages100, vapor chambers192or187, IC devices1600, or dies1502disclosed herein. A number of components are illustrated inFIG.46as included in the electrical device1800, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the electrical device1800may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

Additionally, in various embodiments, the electrical device1800may not include one or more of the components illustrated inFIG.46, but the electrical device1800may include interface circuitry for coupling to the one or more components. For example, the electrical device1800may not include a display device1806, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device1806may be coupled. In another set of examples, the electrical device1800may not include an audio input device1824or an audio output device1808, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device1824or audio output device1808may be coupled.

The electrical device1800may include a processing device1802(e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device1802may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device1800may include a memory1804, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory1804may include memory that shares a die with the processing device1802. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

In some embodiments, the electrical device1800may include a communication component1812(e.g., one or more communication components). For example, the communication component1812may be configured for managing wireless communications for the transfer of data to and from the electrical device1800. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication component1812may include RF components (e.g., PAs and resonators) packaged in any of the IC packages100disclosed herein.

The communication component1812may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication component1812may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component1812may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component1812may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication component1812may operate in accordance with other wireless protocols in other embodiments. The electrical device1800may include an antenna1822to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

In some embodiments, the communication component1812may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication component1812may include multiple communication components. For instance, a first communication component1812may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication component1812may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication component1812may be dedicated to wireless communications, and a second communication component1812may be dedicated to wired communications.

The electrical device1800may include battery/power circuitry1814. The battery/power circuitry1814may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device1800to an energy source separate from the electrical device1800(e.g., AC line power).

The electrical device1800may include a display device1806(or corresponding interface circuitry, as discussed above). The display device1806may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

The electrical device1800may include an audio output device1808(or corresponding interface circuitry, as discussed above). The audio output device1808may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.

The electrical device1800may include an audio input device1824(or corresponding interface circuitry, as discussed above). The audio input device1824may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

The electrical device1800may include a GPS device1818(or corresponding interface circuitry, as discussed above). The GPS device1818may be in communication with a satellite-based system and may receive a location of the electrical device1800, as known in the art.

The electrical device1800may include an other output device1810(or corresponding interface circuitry, as discussed above). Examples of the other output device1810may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

The electrical device1800may include an other input device1820(or corresponding interface circuitry, as discussed above). Examples of the other input device1820may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

The electrical device1800may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop electrical device, a server device or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some embodiments, the electrical device1800may be any other electronic device that processes data.

FIG.47is a block diagram of an example RF device2500that may include one or more IC packages100and/or vapor chambers, in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the RF device2500may include, or may be included in, an IC package100in accordance with any of the embodiments disclosed herein. Any of the components of the RF device2500may include, or be included in, an IC assembly1700as described with reference toFIG.45. In some embodiments, the RF device2500may be included within any components of the computing device1800as described above with reference toFIG.46(e.g., the communication component1812), or may be coupled to any of the components of the electrical device1800(e.g., may be coupled to the memory1804and/or to the processing device1802of the electrical device1800).

In still other embodiments, the RF device2500may further include any of the components described above with reference toFIG.46, such as, but not limited to, the battery/power circuitry1814, the memory1804, and various input and output devices as discussed above with reference toFIG.46.

In general, the RF device2500may be any device or system that may support wireless transmission and/or reception of signals in the form of electromagnetic waves in the RF range of approximately 3 kiloHertz (kHz) to 300 gigaHertz (GHz). In some embodiments, the RF device2500may be used for wireless communications, e.g., in a base station (BS) or a user equipment (UE) device of any suitable cellular wireless communications technology, such as GSM, WCDMA, or LTE. In a further example, the RF device2500may be used as, or in, a BS or a UE device of a millimeter-wave wireless technology such as fifth generation (5G) wireless (e.g., high-frequency/short wavelength spectrum, with frequencies in the range between about 20 and 60 GHz, corresponding to wavelengths in the range between about 5 and 15 millimeters). In yet another example, the RF device2500may be used for wireless communications using Wi-Fi technology (e.g., a frequency band of 2.4 GHz, corresponding to a wavelength of about 12 cm, or a frequency band of 5.8 GHz, corresponding to a wavelength of about 5 cm). For example, the RF device2500may be included in a Wi-Fi-enabled device such as a desktop, a laptop, a video game console, a smart phone, a tablet, a smart TV, a digital audio player, a car, a printer, etc. In some implementations, a Wi-Fi-enabled device may be a node (e.g., a smart sensor) in a smart system configured to communicate data with other nodes. In another example, the RF device2500may be used for wireless communications using Bluetooth technology (e.g., a frequency band from about 2.4 to about 2.485 GHz, corresponding to a wavelength of about 12 cm). In other embodiments, the RF device2500may be used for transmitting and/or receiving RF signals for purposes other than communication (e.g., in an automotive radar system, or in medical applications such as magnetic resonance imaging (MRI)).

In various embodiments, the RF device2500may be included in frequency-division duplex (FDD) or time-domain duplex (TDD) variants of frequency allocations that may be used in a cellular network. In an FDD system, the uplink (i.e., RF signals transmitted from the UE devices to a BS) and the downlink (i.e., RF signals transmitted from the BS to the US devices) may use separate frequency bands at the same time. In a TDD system, the uplink and the downlink may use the same frequencies but at different times.

A number of components are illustrated inFIG.47as included in the RF device2500, but any one or more of these components may be omitted or duplicated, as suitable for the application. For example, in some embodiments, the RF device2500may be an RF device supporting both of wireless transmission and reception of RF signals (e.g., an RF transceiver), in which case it may include both the components of what is referred to herein as a transmit (TX) path and the components of what is referred to herein as a receive (RX) path. However, in other embodiments, the RF device2500may be an RF device supporting only wireless reception (e.g., an RF receiver), in which case it may include the components of the RX path, but not the components of the TX path; or the RF device2500may be an RF device supporting only wireless transmission (e.g., an RF transmitter), in which case it may include the components of the TX path, but not the components of the RX path.

In some embodiments, some or all of the components included in the RF device2500may be attached to one or more motherboards. In various embodiments, the RF device2500may not include one or more of the components illustrated inFIG.47, but the RF device2500may include interface circuitry for coupling to the one or more components. For example, the RF device2500may not include an antenna2502, but may include antenna interface circuitry (e.g., a matching circuitry, a connector and driver circuitry) to which an antenna2502may be coupled. In another set of examples, the RF device2500may not include a digital processing unit2508or a local oscillator2506, but may include device interface circuitry (e.g., connectors and supporting circuitry) to which a digital processing unit2508or a local oscillator2506may be coupled.

As shown inFIG.47, the RF device2500may include an antenna2502, a duplexer2504, a local oscillator2506, and a digital processing unit2508. As also shown inFIG.47, the RF device2500may include an RX path that may include an RX path amplifier2512(which may include any of the PAs disclosed herein, and may include or be included in an HG component104), an RX path pre-mix filter2514, a RX path mixer2516, an RX path post-mix filter2518, and an analog-to-digital converter (ADC)2520. As further shown inFIG.47, the RF device2500may include a TX path that may include a TX path amplifier2522(which may include any of the PAs disclosed herein, and may include or be included in an HG component104), a TX path post-mix filter2524, a TX path mixer2526, a TX path pre-mix filter2528, and a digital-to-analog converter (DAC)2530. Still further, the RF device2500may further include an impedance tuner2532, an RF switch2534(which may include, or be included in, an HG component104), and control logic2536. In various embodiments, the RF device2500may include multiple instances of any of the components shown inFIG.47. In some embodiments, the RX path amplifier2512, the TX path amplifier2522, the duplexer2504, and the RF switch2534may be considered to form, or be a part of, an RF front-end (FE) of the RF device2500. In some embodiments, the RX path amplifier2512, the TX path amplifier2522, the duplexer2504, and the RF switch2534may be considered to form, or be a part of, an RF FE of the RF device2500. In some embodiments, the RX path mixer2516and the TX path mixer2526(possibly with their associated pre-mix and post-mix filters shown inFIG.47) may be considered to form, or be a part of, an RF transceiver of the RF device2500(or of an RF receiver or an RF transmitter if only RX path or TX path components, respectively, are included in the RF device2500). In some embodiments, the RF device2500may further include one or more control logic elements/circuits, shown inFIG.47as control logic2536(providing, for example, an RF FE control interface). The control logic2536may be used to enhance control of complex RF system environment, support implementation of envelope tracking techniques, reduce dissipated power, etc.

The antenna2502may be configured to wirelessly transmit and/or receive RF signals in accordance with any wireless standards or protocols, e.g., Wi-Fi, LTE, or GSM, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. If the RF device2500is an FDD transceiver, the antenna2502may be configured for concurrent reception and transmission of communication signals in separate, e.g., non-overlapping and non-continuous, bands of frequencies, e.g., in bands having a separation of, e.g., 20 MHz from one another. If the RF device2500is a TDD transceiver, the antenna2502may be configured for sequential reception and transmission of communication signals in bands of frequencies that may be the same, or overlapping for TX and RX paths. In some embodiments, the RF device2500may be a multi-band RF device, in which case the antenna2502may be configured for concurrent reception of signals having multiple RF components in separate frequency bands and/or configured for concurrent transmission of signals having multiple RF components in separate frequency bands. In such embodiments, the antenna2502may be a single wide-band antenna or a plurality of band-specific antennas (e.g., a plurality of antennas each configured to receive and/or transmit signals in a specific band of frequencies). In various embodiments, the antenna2502may include a plurality of antenna elements, e.g., a plurality of antenna elements forming a phased antenna array (i.e., a communication system or an array of antennas that may use a plurality of antenna elements and phase shifting to transmit and receive RF signals). Compared to a single-antenna system, a phased antenna array may offer advantages such as increased gain, ability of directional steering, and simultaneous communication. In some embodiments, the RF device2500may include more than one antenna2502to implement antenna diversity. In some such embodiments, the RF switch2534may be deployed to switch between different antennas.

An output of the antenna2502may be coupled to the input of the duplexer2504. The duplexer2504may be any suitable component configured for filtering multiple signals to allow for bidirectional communication over a single path between the duplexer2504and the antenna2502. The duplexer2504may be configured for providing RX signals to the RX path of the RF device2500and for receiving TX signals from the TX path of the RF device2500.

The RF device2500may include one or more local oscillators2506, configured to provide local oscillator signals that may be used for downconversion of the RF signals received by the antenna2502and/or upconversion of the signals to be transmitted by the antenna2502.

The RF device2500may include the digital processing unit2508, which may include one or more processing devices. In some embodiments, the digital processing unit2508may be implemented as the processing device1802ofFIG.46, descriptions of which are provided above. The digital processing unit2508may be configured to perform various functions related to digital processing of the RX and/or TX signals. Examples of such functions include, but are not limited to, decimation/downsampling, error correction, digital downconversion or upconversion, DC offset cancellation, automatic gain control, etc. Although not shown inFIG.47, in some embodiments, the RF device2500may further include a memory device (e.g., the memory device1804described above with reference toFIG.46) configured to cooperate with the digital processing unit2508.

Turning to the details of the RX path that may be included in the RF device2500, the RX path amplifier2512may include a low noise amplifier (LNA). An input of the RX path amplifier2512may be coupled to an antenna port (not shown) of the antenna2502, e.g., via the duplexer2504. The RX path amplifier2512may amplify the RF signals received by the antenna2502.

An output of the RX path amplifier2512may be coupled to an input of the RX path pre-mix filter2514, which may be a harmonic or band-pass (e.g., low-pass) filter, configured to filter received RF signals that have been amplified by the RX path amplifier2512.

An output of the RX path pre-mix filter2514may be coupled to an input of the RX path mixer2516, also referred to as a downconverter. The RX path mixer2516may include two inputs and one output. A first input may be configured to receive the RX signals, which may be current signals, indicative of the signals received by the antenna2502(e.g., the first input may receive the output of the RX path pre-mix filter2514). A second input may be configured to receive local oscillator signals from one of the local oscillators2506. The RX path mixer2516may then mix the signals received at its two inputs to generate a downconverted RX signal, provided at an output of the RX path mixer2516. As used herein, downconversion refers to a process of mixing a received RF signal with a local oscillator signal to generate a signal of a lower frequency. In particular, the RX path mixer (e.g., downconverter)2516may be configured to generate the sum and/or the difference frequency at the output port when two input frequencies are provided at the two input ports. In some embodiments, the RF device2500may implement a direct-conversion receiver (DCR), also known as homodyne, synchrodyne, or zero-intermediate frequency (IF) receiver, in which case the RX path mixer2516may be configured to demodulate the incoming radio signals using local oscillator signals whose frequency is identical to, or very close to the carrier frequency of the radio signal. In other embodiments, the RF device2500may make use of downconversion to an IF. IFs may be used in superheterodyne radio receivers, in which a received RF signal is shifted to an IF, before the final detection of the information in the received signal is done. Conversion to an IF may be useful for several reasons. For example, when several stages of filters are used, they can all be set to a fixed frequency, which makes them easier to build and to tune. In some embodiments, the RX path mixer2516may include several such stages of IF conversion.

Although a single RX path mixer2516is shown in the RX path ofFIG.47, in some embodiments, the RX path mixer2516may be implemented as a quadrature downconverter, in which case it would include a first RX path mixer and a second RX path mixer. The first RX path mixer may be configured for performing downconversion to generate an in-phase (I) downconverted RX signal by mixing the RX signal received by the antenna2502and an in-phase component of the local oscillator signal provided by the local oscillator2506. The second RX path mixer may be configured for performing downconversion to generate a quadrature (Q) downconverted RX signal by mixing the RX signal received by the antenna2502and a quadrature component of the local oscillator signal provided by the local oscillator2506(the quadrature component is a component that is offset, in phase, from the in-phase component of the local oscillator signal by 90 degrees). The output of the first RX path mixer may be provided to a I-signal path, and the output of the second RX path mixer may be provided to a Q-signal path, which may be substantially 90 degrees out of phase with the I-signal path.

The output of the RX path mixer2516may, optionally, be coupled to the RX path post-mix filter2518, which may be low-pass filters. In case the RX path mixer2516is a quadrature mixer that implements the first and second mixers as described above, the in-phase and quadrature components provided at the outputs of the first and second mixers respectively may be coupled to respective individual first and second RX path post-mix filters included in the RX path post-mix filter2518.

The ADC2520may be configured to convert the mixed RX signals from the RX path mixer2516from the analog to the digital domain. The ADC2520may be a quadrature ADC that, similar to the RX path mixer2516, may include two ADCs, configured to digitize the downconverted RX path signals separated in in-phase and quadrature components. The output of the ADC2520may be provided to the digital processing unit2508, configured to perform various functions related to digital processing of the RX signals so that information encoded in the RX signals can be extracted.

Turning to the details of the TX path that may be included in the RF device2500, the digital signal to later be transmitted (TX signal) by the antenna2502may be provided, from the digital processing unit2508, to the DAC2530. Similar to the ADC2520, the DAC2530may include two DACs, configured to convert, respectively, digital I- and Q-path TX signal components to analog form.

Optionally, the output of the DAC2530may be coupled to the TX path pre-mix filter2528, which may be a band-pass (e.g., low-pass) filter (or a pair of band-pass, e.g., low-pass, filters, in case of quadrature processing) configured to filter out, from the analog TX signals output by the DAC2530, the signal components outside of the desired band. The digital TX signals may then be provided to the TX path mixer2526, which may also be referred to as an upconverter. Similar to the RX path mixer2516, the TX path mixer2526may include a pair of TX path mixers, for in-phase and quadrature component mixing. Similar to the first and second RX path mixers that may be included in the RX path, each of the TX path mixers of the TX path mixer2526may include two inputs and one output. A first input may receive the TX signal components, converted to the analog form by the respective DAC2530, which are to be upconverted to generate RF signals to be transmitted. The first TX path mixer may generate an in-phase (I) upconverted signal by mixing the TX signal component converted to analog form by the DAC2530with the in-phase component of the TX path local oscillator signal provided from the local oscillator2506(in various embodiments, the local oscillator2506may include a plurality of different local oscillators, or be configured to provide different local oscillator frequencies for the RX path mixer2516in the RX path and the TX path mixer2526in the TX path). The second TX path mixer may generate a quadrature phase (Q) upconverted signal by mixing the TX signal component converted to analog form by the DAC2530with the quadrature component of the TX path local oscillator signal. The output of the second TX path mixer may be added to the output of the first TX path mixer to create a real RF signal. A second input of each of the TX path mixers may be coupled the local oscillator2506.

Optionally, the RF device2500may include the TX path post-mix filter2524, configured to filter the output of the TX path mixer2526.

As noted above, the TX path amplifier2522may be a PA (e.g., included in an HG component104), configured to amplify the upconverted RF signal before providing it to the antenna2502for transmission

In various embodiments, any of the RX path pre-mix filter2514, the RX path post-mix filter2518, the TX path post-mix filter2524, and the TX path pre-mix filter2528may be implemented as RF filters. In some embodiments, each of such RF filters may include one or more resonators (e.g., AWRs, film bulk acoustic resonators (FBARs), Lamb wave resonators, and/or contour-wave resonators), arranged in any suitable manner (e.g., in a ladder configuration). Any of the RX path pre-mix filter2514, the RX path post-mix filter2518, the TX path post-mix filter2524, and the TX path pre-mix filter2528may include one or more resonator components191. As discussed above with reference to the resonator component191, an individual resonator (e.g., the resonator103) of an RF filter may include a layer of a piezoelectric material such as aluminum nitride, enclosed between two or more electrodes or sets of electrodes, with a cavity (e.g., the cavity105) provided around a portion of each electrode or set of electrodes in order to allow a portion of the piezoelectric material to vibrate during operation of the filter. Any such resonators may be included in an IC package100as a TS component106. In some embodiments, an RF filter may be implemented as a plurality of RF filters, or a filter bank. A filter bank may include a plurality of RF resonators that may be coupled to a switch (e. g., the RF switch2534) configured to selectively switch any one of the plurality of RF resonators on and off (e.g., activate any one of the plurality of RF resonators), in order to achieve desired filtering characteristics of the filter bank (e.g., in order to program the filter bank). For example, such a filter bank may be used to switch between different RF frequency ranges when the RF device2500is, or is included in, a BS or in a UE device. In another example, such a filter bank may be programmable to suppress TX leakage on the different duplex distances.

The impedance tuner2532may include any suitable circuitry, configured to match the input and output impedances of the different RF circuitries to minimize signal losses in the RF device2500. For example, the impedance tuner2532may include an antenna impedance tuner. Being able to tune the impedance of the antenna2502may be particularly advantageous because antenna's impedance is a function of the environment that the RF device2500is in, e.g., antenna's impedance changes depending on, e.g., if the antenna is held in a hand, placed on a car roof, etc.

As described above, the RF switch2534may be a device configured to route high-frequency signals through transmission paths in order to selectively switch between a plurality of instances of any one of the components shown inFIG.47(e.g., to achieve desired behavior and characteristics of the RF device2500). The RF switch2534may be part of an HG component104. In some embodiments, an RF switch2534may be used to switch between different antennas2502. In other embodiments, an RF switch may be used to switch between a plurality of RF resonators (e.g., by selectively switching RF resonators on and off) of any of the filters included in the RF device2500. Typically, an RF system may include a plurality of such RF switches.

The RF device2500provides a simplified version and, in further embodiments, other components not specifically shown inFIG.47may be included. For example, the RX path of the RF device2500may include a current-to-voltage amplifier between the RX path mixer2516and the ADC2520, which may be configured to amplify and convert the downconverted signals to voltage signals. In another example, the RX path of the RF device2500may include a balun transformer for generating balanced signals. In yet another example, the RF device2500may further include a clock generator, which may include a suitable phase-lock loop (PLL), configured to receive a reference clock signal and use it to generate a different clock signal that may then be used for timing the operation of the ADC2520, the DAC2530, and/or that may also be used by the local oscillator2506to generate the local oscillator signals to be used in the RX path or the TX path.

The following paragraphs provide various examples of the embodiments disclosed herein.

Example 1 is a radio frequency (RF) integrated circuit (10) package, including: a package substrate; a first component, wherein the first component is coupled to the package substrate, and the first component includes one or more resonators; a second component, wherein the second component is coupled to the package substrate, and the second component includes one or more power amplifiers; a heat spreader; a cooling device, wherein the cooling device is closer to the first component than to the second component; and a stack of thermal vias in the package substrate in a shadow of the second component.

Example 2 includes the subject matter of Example 1, and further specifies that the cooling device is in contact with the first component.

Example 3 includes the subject matter of Example 2, and further specifies that the cooling device includes a thermoelectric cooler.

Example 4 includes the subject matter of Example 3, and further specifies that the thermoelectric cooler has a height that is less than 500 microns.

Example 5 includes the subject matter of Example 3, and further specifies that the thermoelectric cooler has a height that is less than 100 microns.

Example 6 includes the subject matter of Example 1, and further includes: a thermal interface material (TIM) between the cooling device and the first component.

Example 7 includes the subject matter of Example 6, and further specifies that the TIM includes indium or tin.

Example 8 includes the subject matter of any of Examples 6-7, and further specifies that the TIM includes a polymer material.

Example 9 includes the subject matter of any of Examples 1-8, and further includes: a thermal interface material (TIM) between the cooling device and the heat spreader.

Example 10 includes the subject matter of Example 9, and further specifies that the TIM includes indium or tin.

Example 11 includes the subject matter of any of Examples 9-10, and further specifies that the TIM includes a polymer material.

Example 12 includes the subject matter of any of Examples 1-11, and further specifies that the cooling device includes a vapor chamber.

Example 13 includes the subject matter of any of Examples 1-12, and further specifies that the cooling device is electrically coupled to the package substrate.

Example 14 includes the subject matter of Example 13, and further specifies that the cooling device includes a thermoelectric cooler.

Example 15 includes the subject matter of any of Examples 13-14, and further specifies that the cooling device is electrically coupled to the package substrate by wirebonds.

Example 16 includes the subject matter of any of Examples 13-15, and further specifies that the cooling device is electrically coupled to the package substrate by through-mold vias.

Example 17 includes the subject matter of any of Examples 13-16, and further specifies that the cooling device is electrically coupled to the package substrate by electrical pathways in the first component.

Example 18 includes the subject matter of any of Examples 1-17, and further specifies that the cooling device is between the first component and the heat spreader.

Example 19 includes the subject matter of any of Examples 1-17, and further specifies that the cooling device is embedded in the package substrate.

Example 20 includes the subject matter of Example 19, and further includes: one or more stacks of thermal vias in the package substrate between a surface of the package substrate and the cooling device.

Example 21 includes the subject matter of any of Examples 19-20, and further specifies that the cooling device is in a shadow of the first component.

Example 22 includes the subject matter of any of Examples 19-21, and further specifies that the first component is coupled to the package substrate by electrical interconnects proximate to a perimeter of the first component.

Example 23 includes the subject matter of any of Examples 19-22, and further specifies that the cooling device is at a surface of the package substrate.

Example 24 includes the subject matter of any of Examples 19-22, and further specifies that the cooling device is spaced apart from a surface of the package substrate by one or more substrate layers.

Example 25 includes the subject matter of any of Examples 19-24, and further includes: an underfill material between the first component and the package substrate, wherein the underfill material includes aluminum oxide or boron nitride.

Example 26 includes the subject matter of any of Examples 1-25, and further specifies that the heat spreader includes a metal.

Example 27 includes the subject matter of any of Examples 1-26, and further includes: an adhesive between the heat spreader and the package substrate.

Example 28 includes the subject matter of any of Examples 1-27, and further specifies that the second component and the first component are coupled to a same face of the package substrate.

Example 29 includes the subject matter of any of Examples 1-28, and further specifies that the second component further includes switches.

Example 30 includes the subject matter of any of Examples 1-29, and further includes: a thermal interface material (TIM) between the second component and the heat spreader.

Example 31 includes the subject matter of Example 30, and further specifies that the second component is in contact with the TIM, and the heat spreader is in contact with the TIM.

Example 32 includes the subject matter of any of Examples 1-29, and further specifies that the heat spreader is in contact with the second component.

Example 33 includes the subject matter of any of Examples 1-32, and further specifies that the second component is coupled to a face of the package substrate, and the stack of thermal vias is spaced apart from the face of the package substrate.

Example 34 includes the subject matter of any of Examples 1-33, and further specifies that the cooling device is a first cooling device, and the RF IC package further includes: a second cooling device in the package substrate in a shadow of the second component.

Example 35 includes the subject matter of Example 34, and further specifies that the second cooling device includes a thermoelectric cooler.

Example 36 includes the subject matter of any of Examples 34-35, and further specifies that the second component is coupled to a face of the package substrate, and the second cooling device is spaced apart from the face of the package substrate.

Example 37 includes the subject matter of any of Examples 34-36, and further specifies that the second cooling device is between the stack of thermal vias and the second component.

Example 38 includes the subject matter of Example 37, and further specifies that the stack of thermal vias is a first stack of thermal vias, and the RF IC package further includes: a second stack of thermal vias, wherein the second stack of thermal vias is in the shadow of the second component and the second cooling device is not between the second stack of thermal vias and the second component.

Example 39 includes the subject matter of any of Examples 1-38, and further includes: a material between the first component and the heat spreader, wherein the material has a thermal conductivity that is less than a thermal conductivity of the heat spreader.

Example 40 includes the subject matter of Example 39, and further specifies that the material is a first material, and the RF IC package further includes: a second material between the second component and the heat spreader, wherein the second material has a thermal conductivity that is greater than the thermal conductivity of the first material.

Example 41 includes the subject matter of Example 40, and further specifies that the second material has a thermal conductivity that is greater than the thermal conductivity of the heat spreader.

Example 42 includes the subject matter of any of Examples 40-41, and further specifies that the second material includes a metal.

Example 43 includes the subject matter of any of Examples 40-42, and further specifies that the second material includes copper or aluminum.

Example 44 includes the subject matter of any of Examples 40-43, and further specifies that the second material includes a ceramic.

Example 45 includes the subject matter of Example 44, and further specifies that the second material includes diamond or silicon carbide.

Example 46 includes the subject matter of Example 44, and further specifies that the second material includes aluminum and nitrogen.

Example 47 includes the subject matter of any of Examples 40-46, and further specifies that a distance between the second component and the heat spreader is between 50 microns and 300 microns.

Example 48 includes the subject matter of any of Examples 40-47, and further specifies that the second material is in contact with the second component.

Example 49 includes the subject matter of any of Examples 40-47, and further includes: a thermal interface material (TIM) between the second component and the second material.

Example 50 includes the subject matter of Example 49, and further specifies that the TIM includes indium or tin.

Example 51 includes the subject matter of any of Examples 49-50, and further specifies that the TIM includes a polymer material.

Example 52 includes the subject matter of any of Examples 40-51, and further includes: a thermal interface material (TIM) between the second material and the heat spreader.

Example 53 includes the subject matter of Example 52, and further specifies that the TIM includes indium or tin.

Example 54 includes the subject matter of any of Examples 52-53, and further specifies that the TIM includes a polymer material.

Example 55 includes the subject matter of any of Examples 40-54, and further specifies that the second material is also between the first component and the second component.

Example 56 includes the subject matter of Example 55, and further specifies that a distance between the second material and the first component is greater than 100 microns.

Example 57 includes the subject matter of any of Examples 55-56, and further specifies that a width of the second component is less than or equal to a height of the second component.

Example 58 includes the subject matter of any of Examples 1-57, and further includes: an underfill material between the second component and the package substrate, wherein the underfill material includes aluminum oxide or boron nitride.

Example 59 includes the subject matter of any of Examples 1-58, and further specifies that a distance between the first component and the second component is between 0.1 millimeter and 5 millimeters.

Example 60 is an integrated circuit (IC) package, including: a package substrate; a first component coupled to the package substrate, wherein the first component includes one or more resonators; a second component coupled to the package substrate, wherein the second component includes one or more power amplifiers; a heat spreader; a material between the first component and the heat spreader, wherein the material has a thermal conductivity that is less than a thermal conductivity of the heat spreader; and a stack of thermal vias in the package substrate in a shadow of the second component.

Example 61 includes the subject matter of Example 60, and further specifies that the material is also between the first component and the second component.

Example 62 includes the subject matter of any of Examples 60-61, and further specifies that a distance between the heat spreader and the first component is greater than 10 microns.

Example 63 includes the subject matter of any of Examples 60-62, and further specifies that a distance between the heat spreader and the first component is greater than 50 microns.

Example 64 includes the subject matter of any of Examples 60-63, and further specifies that a distance between the first component and the second component is between 0.1 millimeter and 5 millimeters.

Example 65 includes the subject matter of any of Examples 60-64, and further specifies that the material is a mold compound.

Example 66 includes the subject matter of any of Examples 60-65, and further specifies that the material includes an epoxy.

Example 67 includes the subject matter of any of Examples 66, and further specifies that the material includes filler particles.

Example 68 includes the subject matter of any of Examples 66-67, and further specifies that the material includes silica.

Example 69 includes the subject matter of any of Examples 60-68, and further specifies that the heat spreader includes a pedestal, and the IC package further includes a thermal interface material (TIM) between the pedestal and the second component.

Example 70 includes the subject matter of Example 69, and further specifies that the TIM includes indium or tin.

Example 71 includes the subject matter of any of Examples 69-70, and further specifies that the TIM includes a polymer material.

Example 72 includes the subject matter of any of Examples 60-71, and further specifies that the material is a first material, and the IC package further includes: a second material between the second component and the heat spreader, wherein the second material has a thermal conductivity that is greater than the thermal conductivity of the first material.

Example 73 includes the subject matter of Example 72, and further specifies that the second material has a thermal conductivity that is greater than the thermal conductivity of the heat spreader.

Example 74 includes the subject matter of any of Examples 72-73, and further specifies that the second material includes a metal.

Example 75 includes the subject matter of any of Examples 72-74, and further specifies that the second material includes copper or aluminum.

Example 76 includes the subject matter of any of Examples 72-75, and further specifies that the second material includes a ceramic.

Example 77 includes the subject matter of Example 76, and further specifies that the second material includes diamond or silicon carbide.

Example 78 includes the subject matter of Example 76, and further specifies that the second material includes aluminum and nitrogen.

Example 79 includes the subject matter of any of Examples 72-78, and further specifies that a distance between the second component and the heat spreader is between 50 microns and 300 microns.

Example 80 includes the subject matter of any of Examples 72-79, and further specifies that the second material is in contact with the second component.

Example 81 includes the subject matter of any of Examples 72-79, and further includes: a thermal interface material (TIM) between the second component and the second material.

Example 82 includes the subject matter of any of Examples 81, and further specifies that the TIM includes indium or tin.

Example 83 includes the subject matter of any of Examples 81-82, and further specifies that the TIM includes a polymer material.

Example 84 includes the subject matter of any of Examples 72-83, and further includes: a thermal interface material (TIM) between the second material and the heat spreader.

Example 85 includes the subject matter of Example 84, and further specifies that the TIM includes indium or tin.

Example 86 includes the subject matter of any of Examples 84-85, and further specifies that the TIM includes a polymer material.

Example 87 includes the subject matter of any of Examples 72-86, and further specifies that the second material is also between the first component and the second component.

Example 88 includes the subject matter of Example 87, and further specifies that a distance between the second material and the first component is greater than 100 microns.

Example 89 includes the subject matter of any of Examples 87-88, and further specifies that a width of the second component is less than or equal to a height of the second component.

Example 90 includes the subject matter of any of Examples 72-89, and further specifies that the second material is electrically conductive.

Example 91 includes the subject matter of any of Examples 60-90, and further specifies that the heat spreader is electrically conductive.

Example 92 includes the subject matter of Example 91, and further includes: electrically conductive material proximate to side faces of the IC package; and an electrically conductive plane, wherein the second component and the first component are between the electrically conductive plane and the heat spreader, and the electrically conductive material is in conductive contact with the heat spreader and the electrically conductive plane.

Example 93 includes the subject matter of Example 92, and further specifies that the electrically conductive plane is a plane in a package substrate.

Example 94 includes the subject matter of any of Examples 92-93, and further specifies that the electrically conductive material includes a coating on side faces of the IC package.

Example 95 includes the subject matter of Example 94, and further specifies that the coating has a thickness that is less than 5 microns.

Example 96 includes the subject matter of any of Examples 92-93, and further specifies that the electrically conductive material includes through-mold vias (TMVs).

Example 97 includes the subject matter of Example 96, and further specifies that the electrically conductive material includes vias in a package substrate.

Example 98 includes the subject matter of any of Examples 92-97, and further specifies that the electrically conductive material includes aluminum, copper, or tin.

Example 99 includes the subject matter of any of Examples 92-98, and further specifies that the electrically conductive material includes an epoxy.

Example 100 includes the subject matter of Example 99, and further specifies that the electrically conductive material includes silver.

Example 101 includes the subject matter of any of Examples 60-100, and further specifies that the second component and the first component are coupled to a same face of the package substrate.

Example 102 includes the subject matter of any of Examples 60-101, and further includes: an underfill material between the second component and the package substrate, wherein the underfill material includes aluminum oxide or boron nitride.

Example 103 includes the subject matter of any of Examples 60-102, and further specifies that the second component is coupled to a face of the package substrate, and the stack of thermal vias is spaced apart from the face of the package substrate.

Example 104 includes the subject matter of any of Examples 60-103, and further includes: a cooling device in the package substrate in a shadow of the second component.

Example 105 includes the subject matter of Example 104, and further specifies that the cooling device includes a thermoelectric cooler.

Example 106 includes the subject matter of any of Examples 104-105, and further specifies that the second component is coupled to a face of the package substrate, and the cooling device is spaced apart from the face of the package substrate.

Example 107 includes the subject matter of any of Examples 104-106, and further specifies that the cooling device is between the stack of thermal vias and the second component.

Example 108 includes the subject matter of Example 107, and further specifies that the stack of thermal vias is a first stack of thermal vias, and the IC package further includes: a second stack of thermal vias, wherein the second stack of thermal vias is in the shadow of the second component and the cooling device is not between the second stack of thermal vias and the second component.

Example 109 is a radio frequency (RF) integrated circuit (IC) package, including: a package substrate; a first component, wherein the first component is coupled to the package substrate, and the first component includes one or more resonators; a second component, wherein the second component is coupled to the package substrate, and the second component includes one or more power amplifiers; a heat spreader; and a stack of thermal vias in the package substrate in a shadow of the second component.

Example 110 includes the subject matter of Example 109, and further specifies that the heat spreader includes a metal.

Example 111 includes the subject matter of any of Examples 109-110, and further includes: an adhesive between the heat spreader and the package substrate.

Example 112 includes the subject matter of any of Examples 109-111, and further specifies that the second component and the first component are coupled to a same face of the package substrate.

Example 113 includes the subject matter of any of Examples 109-112, and further specifies that the second component further includes switches.

Example 114 includes the subject matter of any of Examples 109-113, and further includes: a thermal interface material (TIM) between the second component and the heat spreader.

Example 115 includes the subject matter of Example 114, and further specifies that the second component is in contact with the TIM, and the heat spreader is in contact with the TIM.

Example 116 includes the subject matter of any of Examples 109-113, and further specifies that the heat spreader is in contact with the second component.

Example 117 includes the subject matter of any of Examples 109-116, and further specifies that the second component is coupled to a face of the package substrate, and the stack of thermal vias is spaced apart from the face of the package substrate.

Example 118 includes the subject matter of any of Examples 109-117, and further includes: a cooling device in the package substrate in a shadow of the second component.

Example 119 includes the subject matter of Example 118, and further specifies that the cooling device includes a thermoelectric cooler.

Example 120 includes the subject matter of any of Examples 118-119, and further specifies that the second component is coupled to a face of the package substrate, and the cooling device is spaced apart from the face of the package substrate.

Example 121 includes the subject matter of any of Examples 118-120, and further specifies that the cooling device is between the stack of thermal vias and the second component.

Example 122 includes the subject matter of Example 121, and further specifies that the stack of thermal vias is a first stack of thermal vias, and the RF IC package further includes: a second stack of thermal vias, wherein the second stack of thermal vias is in the shadow of the second component and the cooling device is not between the second stack of thermal vias and the second component.

Example 123 includes the subject matter of any of Examples 109-122, and further includes: a material between the first component and the heat spreader, wherein the material has a thermal conductivity that is less than a thermal conductivity of the heat spreader.

Example 124 includes the subject matter of Example 123, and further specifies that the material is a first material, and the RF IC package further includes: a second material between the second component and the heat spreader, wherein the second material has a thermal conductivity that is greater than the thermal conductivity of the first material.

Example 125 includes the subject matter of Example 124, and further specifies that the second material has a thermal conductivity that is greater than the thermal conductivity of the heat spreader.

Example 126 includes the subject matter of any of Examples 124-125, and further specifies that the second material includes a metal.

Example 127 includes the subject matter of any of Examples 124-126, and further specifies that the second material includes copper or aluminum.

Example 128 includes the subject matter of any of Examples 124-127, and further specifies that the second material includes a ceramic.

Example 129 includes the subject matter of Example 128, and further specifies that the second material includes diamond or silicon carbide.

Example 130 includes the subject matter of Example 128, and further specifies that the second material includes aluminum and nitrogen.

Example 131 includes the subject matter of any of Examples 124-130, and further specifies that a distance between the second component and the heat spreader is between 50 microns and 300 microns.

Example 132 includes the subject matter of any of Examples 124-131, and further specifies that the second material is in contact with the second component.

Example 133 includes the subject matter of any of Examples 124-131, and further includes: a thermal interface material (TIM) between the second component and the second material.

Example 134 includes the subject matter of Example 133, and further specifies that the TIM includes indium or tin.

Example 135 includes the subject matter of any of Examples 133-134, and further specifies that the TIM includes a polymer material.

Example 136 includes the subject matter of any of Examples 124-135, and further includes: a thermal interface material (TIM) between the second material and the heat spreader.

Example 137 includes the subject matter of Example 136, and further specifies that the TIM includes indium or tin.

Example 138 includes the subject matter of any of Examples 136-137, and further specifies that the TIM includes a polymer material.

Example 139 includes the subject matter of any of Examples 124-138, and further specifies that the second material is also between the first component and the second component.

Example 140 includes the subject matter of Example 139, and further specifies that a distance between the second material and the first component is greater than 100 microns.

Example 141 includes the subject matter of any of Examples 139-140, and further specifies that a width of the second component is less than or equal to a height of the second component.

Example 142 includes the subject matter of any of Examples 124-141, and further specifies that the second material is electrically conductive.

Example 143 includes the subject matter of any of Examples 109-142, and further specifies that a distance between the first component and the second component is between 0.1 millimeter and 5 millimeters.

Example 144 includes the subject matter of any of Examples 109-143, and further includes: an underfill material between the second component and the package substrate, wherein the underfill material includes aluminum oxide or boron nitride.

Example 145 is an integrated circuit (IC) assembly, including: the IC package of any of Examples 1-144; and a circuit board, wherein the IC package is electrically coupled to the circuit board.

Example 146 includes the subject matter of Example 145, and further includes: an interposer, wherein the interposer is between the IC package and the circuit board.

Example 147 includes the subject matter of any of Examples 145-146, and further includes: a heat sink, wherein the IC package is between the heat sink and the circuit board.

Example 148 includes the subject matter of Example 147, and further includes: a thermal interface material (TIM) between the IC package and the heat sink.

Example 149 includes the subject matter of any of Examples 145-148, and further includes: a housing around the IC package and the circuit board.

Example 150 includes the subject matter of any of Examples 145-149, and further includes: wireless communication circuitry communicatively coupled to the circuit board.

Example 151 includes the subject matter of any of Examples 145-149, and further includes: a display communicatively coupled to the circuit board.

Example 152 includes the subject matter of any of Examples 145-151, and further specifies that the IC assembly is a mobile computing device.

Example 153 includes the subject matter of any of Examples 145-151, and further specifies that the IC assembly is a server computing device.

Example 154 includes the subject matter of any of Examples 145-151, and further specifies that the IC assembly is a wearable computing device.