Patent ID: 12230575

DETAILED DESCRIPTION

FIG.1is a plan view of a carrier structure according to example embodiments.

Referring toFIG.1, a carrier structure1000may include carrier tape500including a plurality of pockets510and an electronic component520may be accommodated in each of the plurality of pockets510. In an implementation, as illustrated in the drawings, the electronic component520may be accommodated in one of the plurality of pockets510, or electronic components520may be accommodated in more than one, e.g., each, of the plurality of pockets510.

The carrier tape500may be used as a packaging member for protecting the electronic component520when the electronic component520is transported or stored. The carrier tape500may include the plurality of pockets510for accommodating electronic components520, and a transfer hole530to engage a sprocket and transfer the same.

Each of the plurality of pockets510may have a concave shape accommodating the electronic component520. Each of the plurality of pockets510may include a bottom surface511and sidewalls SW. The sidewalls SW may include first sidewalls512in four corner regions of each of the plurality of pockets510, and second sidewalls513between corner regions, adjacent to each other, among the corner regions. The first sidewalls512of one pocket510may not be connected to each other and may be spaced apart from each other. The first sidewalls512may include a first portion512aand a second portion512bhaving different inclinations (e.g., inclination angles) relative to each other. The second sidewalls513may extend from the bottom surface511and the first sidewalls512.

The bottom surface511of the pocket510may include a first portion511ain a center of the pocket510and having a first width W1(e.g., in a X direction or a Y direction), second portions511bat a position, symmetrical about the first portion511aand having a second width W2, smaller than the first width W1, and third portions511cat a position, symmetrical about the first portion511aand having a third width W3, smaller than the first width W1and the second width W2. The first to third portions511a,511b, and511cof the bottom surface511may be in a single plane connected to, e.g., continuous with, each other.

Vertices or edges of a lower surface of the electronic component520may contact the sidewalls of the pocket510. The vertices of the lower surface of the electronic component520may contact the first sidewalls512.

FIGS.2A and2Bare cross-sectional views of a carrier structure according to example embodiments.FIG.2Ais a cross-sectional view taken along line I-I′ ofFIG.1.FIG.2Bis a cross-sectional view taken along line II-II′ ofFIG.1.

As shown inFIG.2A, the first sidewall512of the pocket510may include a first portion512aand a second portion512b. The first portion512aof the first sidewall512may have a first inclination (e.g., inclination angle) θ1with respect to the bottom surface511(e.g., as measured from an outer surface relative to an extension of the bottom surface511). The first portion512aof the first sidewall512may extend from the bottom surface511inclined at a first inclination θ1. One pocket portion, defined by the first portions512aof the first sidewalls512, may have a greater or increasing width (e.g., in a horizontal direction) moving away from the bottom surface511in a Z direction (e.g., a first distance between the first portions512ain the horizontal direction at a position proximate to the bottom surface511may be less than a second distance between the first portions512ain the horizontal direction at a position distal to the bottom surface511). Another pocket portion, defined by the second portions512bof the first sidewalls512, may also have a greater or increasing width moving away from the bottom surface511in a Z direction. The second portion512bof the first sidewall512may (e.g., continuously) extend from the first portion512aof the first sidewall512. The second portion512bof the first sidewall512may have a second inclination (e.g., inclination angle) θ2, different from the first inclination θ1of the first portion512a. In an implementation, the inclination of the second portion512bof the first sidewall512(e.g., the second inclination θ2) may be greater than the first inclination θ1of the first portion512a.

The first portions512aof the first sidewalls512may be inclined from the bottom surface511so that vertices of a lower surface of a semiconductor chip stack structure CS may be in contact therewith, and may be inclined surfaces. The inclined surfaces may be inclined to such an extent so that a lowermost connection member30L of the semiconductor chip stack structure CS (to be described below) are not in contact with (e.g., spaced apart from) the bottom surface511of the pocket510. In an implementation, the first portion512aof the first sidewall512may be an inclined surface, inclined at about 5° to about 15° from the bottom surface511. In an implementation, the first inclination θ1may be an angle of about 5° to about 15°. Maintaining the first inclination θ1at about 5° or greater may help prevent the lowermost connection member30L from contacting the bottom surface511of the pocket510. Maintaining the first inclination θ1at about 15° or less may help prevent a decrease in accommodation stability of the semiconductor chip stack structure CS supported by the sidewalls SW (see,FIG.1) of each pocket510, e.g., which could otherwise occur due to an increased separation distance from the sidewalls SW (see,FIG.1) of the pocket510and a side surface of the semiconductor chip stack structure CS.

The second portion512bof the first sidewall512may be an inclined surface, inclined relatively close to vertical with respect to the bottom surface511. The second portion512bof the first sidewall512may be an inclined surface, inclined at about 80° to about 90° with respect to the bottom surface511. In an implementation, the second inclination θ2may be an angle of about 80° to about 90°.

A pocket portion, defined by the second portions512bof the first sidewalls512, may have a greater width moving away from the bottom surface511in the Z direction. The pocket portion, defined by the second portions512bof the first sidewalls512, may have a minimum width W4and a maximum width W5(e.g., in the X direction), and the minimum width W4of the pocket portion may be, e.g., about 0.9 or more times the maximum width W5of the pocket portion (e.g., about 0.9 times to less than 1 times, such that the minimum width W4is less than the maximum width W5). In an implementation, the minimum width W4of the pocket portion may be, e.g., about 0.95 or more times of the maximum width W5of the pocket portion.

A difference in height H2(e.g., in the Z direction) between a lower end of the second portion512bof the first sidewall512and an upper end of the second portion512bmay be greater than a difference in height H1between the bottom surface511and an upper end of the first portion512aof the first sidewall512. The difference in height H2between the lower end of the second portion512bof the first sidewall512and the upper end of the second portion512bmay be, e.g., 2 to 4 times the height difference H1between the bottom surface511and the upper end of the first portion512aof the first sidewall512. In an implementation, the difference in height H2between the lower end of the second portion512bof the first sidewall512and the upper end of the second portion512bthereof may be, e.g., about 2 to 3.5 times the height difference H1between the bottom surface511and the upper end of the first portion512aof the first sidewall512.

In an implementation, a maximum thickness T of the carrier tape500may be greater than the difference in height H1between the bottom surface511and the upper end of the first portion512aof the first sidewall512. In an implementation, the maximum thickness T of the carrier tape500may be substantially equal to the difference in height H1between the bottom surface511and the upper end of the first portion512aof the first sidewall512.

In an implementation, an electronic component520accommodated in each of the plurality of pockets510may be a semiconductor chip stack structure CS. At least a portion of the semiconductor chip stack structure CS may contact the first sidewalls512of the pocket510. In an implementation, one pocket510may include first sidewalls512respectively in four corner regions, four corners or vertices of a lower surface of the semiconductor chip stack structure CS may be accommodated in contact with the first sidewalls512of the pocket510. In an implementation, the four corners or vertices of the lower surface of the semiconductor chip stack structure CS may contact the first portion512aof the first sidewalls512. In an implementation, only the vertices of the semiconductor chip stack structure CS may be in contact with the carrier tape500, rather than a specific surface of the semiconductor chip stack structure CS, and a contact area between the semiconductor chip stack structure CS and the carrier tape500may be reduced. In an implementation, the contact area between the semiconductor chip stack structure CS and the carrier tape500may be reduced, and a degree of contamination (e.g., which could otherwise occur due to the contact of the semiconductor chip stack structure CS with the carrier tape500) may be reduced.

As shown inFIG.2B, the first portion511aof the bottom surface511may be directly connected to second sidewalls513. The second sidewalls513extending from the first portion511amay not contact the semiconductor chip stack structure CS. In an implementation, in a region other than a corner of the pocket510, the semiconductor chip stack structure CS may not contact the carrier tape500. The corner region of the pocket510may include the first portion512aof the first sidewall512, and the carrier tape500may not contact the semiconductor chip stack structure CS in a central region, excluding the corner region of the pocket510.

As shown inFIG.2B, the second sidewalls513may have a third inclination θ3greater than the first inclination θ1of the first portion512aof the first sidewalls512(seeFIG.2A). The third inclination θ3of the second sidewalls513may be substantially equal to the second inclination θ2of the first sidewalls512(seeFIG.2A).

The semiconductor chip stack structure CS may include a base chip10and a plurality of semiconductor chips100,200,300, and400stacked on the base chip10in a vertical direction (e.g., the Z direction). In an implementation, the semiconductor chip stack structure CS may further include a molding member20, a connection member30electrically connecting the base chip10to the plurality of semiconductor chips100,200,300, and400, or a non-conductive film40surrounding the connection member30between the base chip10and the plurality of semiconductor chips100,200,300, and400. The semiconductor chip stack structure CS may further include a first through-via14penetrating through at least a portion of the base chip10and second through-vias140,240, and340penetrating through at least portions of the plurality of semiconductor chips100,200,300, and400. The semiconductor chip stack structure CS may further include the lowermost connection member30L below the base chip10(e.g., between the base chip10and the carrier tape500).

In an implementation, four corners or vertices of a lower surface of the base chip10may contact sidewalls of the pocket510. Four corners or vertices of the base chip10may contact the first sidewalls512of the pocket510. The four corners or vertices of the base chip10may contact the first portion512aof the first sidewalls512of the pocket510.

A width of the base chip10in a horizontal direction (e.g., X direction) may be greater than a width of the plurality of semiconductor chips100,200,300, and400in the horizontal direction. This may be due to a process of sequentially stacking the plurality of semiconductor chips100,200,300, and400in a chip or die state on a base chip10in a wafer state, and cutting the base chip10into individual chips.

The base chip10may include a base substrate11, a circuit structure12on a lower surface of the base substrate11, a first through-via14penetrating through at least portions of the base substrate11and the circuit structure12, and a lower connection pad15and an upper connection pad16respectively on a lower surface and an upper surface of the base chip10. The base chip10may be a dummy semiconductor chip not including individual devices, unlike the plurality of semiconductor chips100,200,300, and400stacked thereon. The base chip10may be a buffer chip that may receive a control signal, a power signal, or a ground signal for an operation of the plurality of semiconductor chips100,200,300, and400from an outside through the first through-via14, or receive a data signal to be stored in the plurality of semiconductor chips100,200,300, and400from an outside, or that may provide the data stored in the plurality of semiconductor chips100,200,300, and400externally.

In an implementation, the vertices or edges of the lower surface of the base chip10may contact the first sidewalls512. In an implementation, the vertices of the lower surface of the base chip10may contact the first portion512aof the first sidewalls512.

The base substrate11may include, e.g., a semiconductor layer including silicon or the like, and a rear insulating film on the semiconductor layer. The rear insulating film may include a silicon oxide layer, a silicon nitride film, a polymer film, or the like. The circuit structure12may include a silicon oxide film, a silicon nitride film, or a combination thereof, an interlayer insulating film and a wiring structure in the interlayer insulating film. The first through-via14may extend from an upper surface to a lower surface of the base chip10penetrating through the base substrate11and the circuit structure12. In an implementation, the first through-via14may penetrate through the circuit structure12to be directly connected to the lower connection pad15as shown in the drawing. In an implementation, the first through-via14may penetrate through only the base substrate11and may be electrically connected to the lower connection pad15through a wiring structure of the circuit structure12. The connection pads15and16may include, e.g., aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), or gold (Au).

The molding member20may seal the plurality of semiconductor chips100,200,300, and400on the base chip10. The molding member20may respectively cover side surfaces of the plurality of semiconductor chips100,200,300, and400so that they are not exposed externally. In an implementation, as illustrated in the drawings, the molding member20may cover an upper surface of an uppermost semiconductor chip400, or the molding member20may expose the upper surface of the uppermost semiconductor chip400. The molding member20may include an insulating resin, e.g., EMC.

In an implementation, the vertices of the lower surface of the base chip10may be in contact with the first sidewall512of the pocket510, and the molding member20encapsulating the plurality of semiconductor chips100,200,300, and400on the base chip10may be spaced apart from the first sidewalls512and the second sidewalls513of the pocket510. In an implementation, the molding member20may not be in contact with sidewalls SW (seeFIG.1) of the pocket510.

The connection member30and the lowermost connection member30L may include, e.g., a conductive material. The connection member30and the lowermost connection member30L may have a land, ball, or pin structure. The connection member30and the lowermost connection member30L may have a multilayer structure including copper pillar and solder, or a single-layer structure including tin-silver solder or copper.

The lowermost connection member30L below the base chip10may be spaced apart from the bottom surface511, the first sidewalls512, and the second sidewalls513of the pocket510.

The non-conductive film40may include an adhesive resin and may adhere the plurality of semiconductor chips100,200,300, and400to each other. The adhesive resin may be a thermosetting resin, and may include, e.g., an epoxy resin.

The plurality of semiconductor chips100,200,300, and400may include first to fourth semiconductor chips100,200,300, and400stacked in the vertical direction (Z direction). Each of the plurality of semiconductor chips100,200,300,400may include a semiconductor substrate110, a circuit structure120, second through-vias140,240, and340, and front pads150,250,350, and450, and rear pads160,260and360.

The semiconductor substrate110may include, e.g., a semiconductor layer including silicon or the like, and a rear insulating film on the semiconductor layer. The rear insulating film may include a silicon oxide film, a silicon nitride film, a polymer film, or the like. The circuit structure120may include a silicon oxide film, a silicon nitride film, or a combination thereof, an interlayer insulating film and a wiring structure in the interlayer insulating film. The second through-vias140,240, and340may penetrate through semiconductor chips below at least the uppermost semiconductor chip400among the plurality of semiconductor chips100,200,300, and400, respectively. In an implementation, as shown in the drawings, the second through-vias140,240, and340may penetrate through the circuit structure120to be directly connected to the front pads150,250, and350. In an implementation, the second through-vias140,240, and340may penetrate through only the semiconductor substrate110, and may be electrically connected to the front pads150,250, and350through the wiring structure of the circuit structure120. The front pads150,250,350, and450and the rear pads160,260, and360may include, e.g., aluminum (Al), copper (Cu), nickel (Ni), tungsten (W), platinum (Pt), or gold (Au).

The first rear pad160on an upper surface of the first semiconductor chip100and the second front pad250on a lower surface of the second semiconductor chip200may be electrically connected through the connection member30. In an implementation, the base chip10and the first semiconductor chip100, the second semiconductor chip200and the third semiconductor chip300, and the third semiconductor chip300and the fourth semiconductor chip400may be physically and electrically connected. Each of the first to fourth semiconductor chips100,200,300, and400may be a memory chip or a logic chip. In an implementation, the plurality of semiconductor chips100,200,300, and400may include a volatile memory chip such as DRAM or SRAM or a non-volatile memory chip such as PRAM, MRAM, RRAM, and flash memory.

The plurality of semiconductor chips100,200,300, and400may be electrically connected to each other through second through-vias140,240,340and a connection member30. The second through vias140,240, and340may be connected to front pads150,250,350and rear pads160,260, and360.

Hereinafter, the descriptions described with reference toFIGS.1to2Bmay be applied to components indicated by the same reference numerals.

FIG.3is a cross-sectional view of a carrier structure according to example embodiments.FIG.3is a cross-sectional view of a region corresponding to a cross-section I-I′ ofFIG.1.

Referring toFIG.3, in a carrier structure1000a, four vertices of a lowermost surface of a semiconductor chip stack structure CS may be in contact with at least one of first portions512aand second portions512bof first sidewalls512of a pocket510of carrier tape500a. In an implementation, the four vertices of a lowermost surface of the semiconductor chip stack structure CS may contact a boundary point at which the first portion512aand the second portion512bof the first sidewalls512(having different inclination each other) meet. In an implementation, the vertices of the lower surface of the base chip10of the semiconductor chip stack structure CS may be in contact with the boundary point in which the first portion512aof the first sidewall512and the second portion512bof the first sidewall512meet.

FIG.4is a cross-sectional view illustrating a carrier structure according to example embodiments.FIG.4is a cross-sectional view illustrating a region corresponding to the cross-section I-I′ ofFIG.1.

Referring toFIG.4, in a carrier structure1000b, a pocket510of carrier tape500bmay include first sidewalls512having a first portion512aand a second portion512bhaving different inclinations from each other. The first sidewalls512may further include a support portion514connecting the first portion512ato the second portion512bbetween the first portion512aand the second portion512b.

The support portion514may be parallel to a bottom surface511. The first sidewalls512of the plurality of pockets510of the carrier tape500bmay have a stepped shape. In an implementation, as illustrated in the drawings, the pocket510of the carrier tape500bmay have a two-layer stepped shape while including one support portion514, disposed parallel to the bottom surface511, or may have a stepped shape of two or more floors or levels while including a plurality of support portions on different levels.

At least a portion of a lowermost surface of a semiconductor chip stack structure CS may contact the support portion514. Even in this case, a molding member20may be spaced apart from sidewalls SW (see,FIG.1) including the first sidewall512of the pocket510and may not be in contact with the sidewalls SW. In an implementation, a lowermost connection member30L may not be in contact with the bottom surface511of the pocket510.

A distance (in the Z direction) from the bottom surface511of the pocket510an upper end of the support portion514may be, e.g., about 1 mm to about 2 mm. In an implementation, the distance from the bottom surface511of the pocket510to the top of the support portion514may be, e.g., about 1 mm to about 1.5 mm. In an implementation, a height of a step portion may be, e.g., about 1 mm to about 2 mm.

In an implementation, inclinations of the first portion512aof the first sidewall512and the second portion512bof the first sidewall512may be different from each other. In an implementation, the inclinations θ1and θ2of the first portion512aof the first sidewall512and the second portion512bof the first sidewall512may be substantially the same.

In an implementation, the first portion512aand the second portion512bof the first sidewall512may be inclined with respect to the bottom surface511. In an implementation, the first portion512aand/or the second portion512bof the first sidewall512may be vertically disposed relative to the bottom surface511.

FIG.5is a plan view of a carrier structure according to example embodiments.

Referring toFIG.5, a carrier structure1000cmay include carrier tape500cincluding a plurality of pockets540and an electronic component550accommodated in each of the plurality of pockets540. In an implementation, as illustrated in the drawings, the electronic component550may be accommodated in one of the plurality of pockets540, or the electronic components550may be accommodated in each of the plurality of pockets540.

Each of the plurality of pockets540may include a bottom surface541, sidewalls542and543, and a support544.

The sidewalls542and543may include first sidewalls543facing each other and second sidewalls542facing each other.

The pocket540may be symmetrical with respect to a center line L along the X direction of the pocket540. The pocket540may have a smaller width (e.g., in the X direction) in a region, adjacent to the center line L than in a region, spaced away (e.g., in the Y direction) from the center line L. The first sidewalls543of the pocket540may include a concave portion543athat is concavely recessed and a protrusion543bthat is relatively protruding in a plan view, respectively.

The supports544may contact sidewalls of each of the plurality of pockets540. The supports544may be on the bottom surface541of the pocket540, and may contact the first sidewalls542of the pocket540. The supports544may contact the protrusions543bof the first sidewalls543. The supports544may be spaced apart from the second sidewalls542. In an implementation, the supports544may be be in contact with the first sidewalls543of the pocket540, only a part of the supports544may be in contact with an edge of a lower surface of the electronic component550to be accommodated, and a degree of contamination due to contact with the carrier tape500cmay be reduced.

The electronic component550may be inside each of the plurality of pockets540. The electronic component550may be on the supports544. At least a portion of the electronic component550may contact the supports544.

FIGS.6A and6Bare cross-sectional views of a carrier structure according to example embodiments.FIG.6Ais a cross-sectional view taken along line ofFIG.5.FIG.6Bis a cross-sectional view taken along line IV-IV′ ofFIG.5.

The pocket540may include the bottom surface541, and the first sidewalls543extending from a bottom surface541. A pocket portion, defined by the first sidewalls543, may have an increasing width (e.g., in the X direction) moving away from the bottom surface541(e.g., in the Z direction). The first sidewalls543may be inclined surfaces having an inclination of less than 90° with respect to the bottom surface541.

The supports544may be at an edge of the pocket540and may contact the first sidewalls543. The supports544, spaced apart in the X direction, may contact the first sidewalls543facing each other, respectively. Each of the supports544may have a width Ws (e.g., in the X direction), greater than a height Ts (e.g., in the Z direction) from the bottom surface541. The height Ts of the supports544may be, e.g., about 1 mm to about 2 mm. In an implementation, the height Ts of the supports544may be, e.g., about 1 mm to about 1.5 mm. The width Ws of each of the supports544may be, e.g., about 1.5 mm to about 2.3 mm. In an implementation, the width Ws of each of the supports544may be, e.g., about 1.5 mm to about 2 mm.

In an implementation, an electronic component550accommodated in each of the plurality of pockets540may be a semiconductor chip stack structure CS. The semiconductor chip stack structure CS may include the same technical features as those described with reference toFIGS.2A and2B.

An upper surface of each of the supports544may contact at least a portion of a lower surface of the semiconductor chip stack structure CS. The upper surface of each of the supports544may be in contact with at least a portion of a lower surface of the base chip10, and may be disposed in such a manner that lowermost connection members30L are not in contact with the bottom surface541of the pocket540.

As set forth above, according to example embodiments, a carrier structure for preventing damage to a semiconductor chip stack structure by accommodating the semiconductor chip stack structure in carrier tape having an inclined sidewall may be provided.

According to example embodiments, a carrier structure for preventing damage to a semiconductor chip stack structure by accommodating the semiconductor chip stack structure in carrier tape including a support may be provided.

Herein, a lower side, a lower portion, a lower surface, and the like, are used to refer to a direction toward a mounting surface of the fan-out semiconductor package in relation to cross sections of the drawings, while an upper side, an upper portion, an upper surface, and the like, are used to refer to an opposite direction to the direction. However, these directions are defined for convenience of explanation, and the claims are not particularly limited by the directions defined as described above.

The meaning of a “connection” of a component to another component in the description includes an indirect connection through an adhesive layer as well as a direct connection between two components. In addition, “electrically connected” conceptually includes a physical connection and a physical disconnection. It can be understood that when an element is referred to by terms such as “first” and “second”, the element is not limited thereby. They may be used only for a purpose of distinguishing the element from the other elements, and may not limit the sequence or importance of the elements. In some cases, a first element may be referred to as a second element without departing from the scope of the claims set forth herein. Similarly, a second element may also be referred to as a first element. As used herein, the term “or” is not an exclusive term, e.g., “A or B” would include A, B, or A and B.

The term “an example embodiment” used herein does not refer to the same example embodiment, and is provided to emphasize a particular feature or characteristic different from that of another example embodiment. However, example embodiments provided herein are considered to be able to be implemented by being combined in whole or in part one with one another. For example, one element described in a particular example embodiment, even if it is not described in another example embodiment, may be understood as a description related to another example embodiment, unless an opposite or contradictory description is provided therein. Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.