Patent ID: 12191199

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed that are between the first and second features, such that the first and second features are not in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for case of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of a device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The term “nominal” as used herein refers to a desired, or target, value of a characteristic or parameter for a component or a process operation, set during the design phase of a product or a process, together with a range of values above and/or below the desired value. The range of values is typically due to slight variations in manufacturing processes or tolerances.

The term “vertical,” as used herein, means nominally perpendicular to the surface of a substrate.

In chip fabrication, lower-level interconnects—also referred to as “metal contacts”—are formed to electrically connect terminals of one or more field effect transistors (FETs)—e.g., gate, source, and/or drain terminals—to higher-level interconnects. Metal contacts can be formed via etching an interlayer dielectric stack to form one or more contact openings on the transistor's gate and on epitaxial layers of the source/drain regions. Filling the contact openings with a metal completes the metal contact formation. Metal contact formation is also referred to herein as “contact metallization.”

Contact openings are progressively becoming more challenging to fill due to their demanding geometry. For example, a contact opening may have an aspect ratio (AR)—e.g., ratio that can be defined by the opening's height to the opening's width-between about 3 and about 10 (e.g., 6) with a top portion of the opening having a critical dimension (CD) smaller than about 17 nm and a bottom portion of the opening having a CD smaller than about 14 nm. At the same time, the height of the contact can be greater than about 60 nm. Consequently, a metal deposition may be unable to fill the contact opening without the formation of voids or seams. Voids in contacts are undesirable because they may increase the contact's resistance and adversely affect a chip's reliability. For example, voids-depending on their size and position in the contact—can be exposed during a subsequent chemical mechanical planarization (CMP) process. With the voids exposed, slurry from the CMP process can enter the voids and remove metal from the contacts.

Pinch-off is a failure mechanism during a metal fill process that can lead to void formation in a contact. Pinch-off can be initiated when the metal deposition rate is high and metal deposits do not have sufficient time to reach the bottom of the contact. As a result, metal deposits accumulate on a top opening of the contact and prevent incoming metal deposits from reaching the bottom of the contact. Another reason for pinch-off formation during the metal fill process can be related to the contact profile. For example, a contact profile that has a re-entrant top opening, where the top CD of the opening is smaller than its a middle or bottom CD. In this case, pinch-off can be triggered when the metal deposition rate is sufficiently low.

The embodiments described herein are directed to a method that describes a cobalt (Co) metallization process with improved gap fill. The embodiments can be used to metal fill contacts with, for example, an AR between about 3 to about 10 and a height greater than about 60 nm. By way of example and not limitation, this disclosure includes a co-deposition/reflow physical vapor deposition (PVD) process that utilizes a radio frequency (RF) power to independently control the deposition and reflow process of the deposited metal.

FIG.1is a flow diagram of an example metal deposition method100according to some embodiments. Metal deposition method100describes the formation of Co metal in contacts. The contacts can have an AR between, for example, about 3 to about 10 and a depth greater than about 60 nm. Other fabrication operations may be performed between the various operations of metal deposition method100and are not discussed herein merely for clarity. Metal deposition method100is not limited to the operations shown inFIG.1and other alternative methods can be possible. Furthermore, the figures provided to describe method100are for illustrative purposes only and are not to scale. Some structures, films, or geometries may have been deliberately augmented for illustrative purposes.

Method100begins with operation110, where a substrate200is provided with a dielectric210formed thereon as shown inFIG.2. In some embodiments, substrate200may also refer to a fin structure on a wafer. For example, substrate200can be a portion of a semiconductor fin on a wafer. In some embodiments, the fin and the wafer can be made of the same or different material. Further, substrate200can be a fin on a bulk semiconductor wafer or a fin on a silicon on insulator (SOI) wafer. Further, substrate200can be made of silicon or another elementary semiconductor such as, for example, (i) germanium (Ge); (ii) a compound semiconductor including silicon carbide (SIC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb); (iii) an alloy semiconductor including silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GalnAs), gallium indium phosphide (GalnP), and/or gallium indium arsenide phosphide (GalnAsP); or (iv) combinations thereof.

For example purposes, substrate200in method100will be described in the context of a silicon fin on a silicon wafer (e.g., single crystal). Based on the disclosure herein, other materials can be used, which are within the spirit and scope of this disclosure.

FIG.2includes additional elements such as gate electrodes220, high-k dielectrics230, spacers240, capping layers250, and S/D epitaxial layers260. In some embodiments, gate electrodes220, high-k dielectrics230, spacers240, and capping layer250form a gate structure of a FET. Further, a gate structure along with adjacent S/D epitaxial layers can form terminals of the FET. In some embodiments, fewer or additional gate structures and S/D epitaxial layers260can be formed on substrate200. Therefore, the number of gate structures or S/D epitaxial layers260depicted inFIG.2is not limiting. In some embodiments, S/D epitaxial layers260can be a p-type epitaxially grown SiGe stack or an n-type carbon-doped epitaxial silicon (Si:C) stack. In some embodiments, dielectric210can be an interlayer dielectric (ILD) made of silicon dioxide (SiO2), carbon-doped silicon oxide (SiOxC), silicon oxy-nitride (SiON), silicon-oxy-carbon nitride (SiOCN), silicon carbide (SiC), silicon carbon nitride (SiCN), or a combination thereof. In some embodiments, dielectric210can be a stack of two or more dielectric materials. Dielectric210can provide electrical isolation between gate electrodes220and the metal contacts that will be formed adjacent to gate electrodes220. Dielectric210can be deposited with a CVD process, a flowable CVD process, a PVD process, or a thermally-grown process.

According to some embodiments, high-k dielectric230can be deposited by atomic layer deposition (ALD) and its thickness can range from about 10 Å to about 20 Å. In some embodiments, high-k dielectric230can be hafnium oxide (HfO2), a hafnium silicate-based material, or another dielectric material with dielectric constant (k-value) greater than 3.9—which is the dielectric constant of SiO2and is used as an example reference.

Gate electrode220can be a multilayer metal stack which can include: (i) a capping layer for high-k dielectric230, (ii) one or more metallic layers, (iii) a work function metal (WFM) stack, and (iv) a metal fill layer. For simplicity, the capping layer, the one or more metallic layers, the WFM stack, and the metal fill layer are not individually depicted within gate electrode220ofFIG.2. In some embodiments, the capping layer for high-k dielectric230can be deposited with an ALD process. ALD is a deposition method that can provide controlled and conformal layer growth at, for example, an angstrom level. In some embodiments, the capping layer for high-k dielectric230can have a thickness that ranges from about 5 Å to about 15 Å. The capping layer for high-k dielectric230can be used to protect high-k dielectric230from subsequent processing operations—e.g., the formation of the one or more metallic layers of gate electrode220. In some embodiments, the capping layer for high-k dielectric230can be a titanium (Ti)-based material.

The number and type of metallic layers in gate electrode220may depend on the transistor's threshold voltage requirements. Exemplary metallic layers in gate electrode220may include a tantalum nitride (TaN) bottom layer and one or more titanium nitride (TiN) layers. In some embodiments, the TaN bottom layer can be deposited by CVD. By way of example and not limitation, the thickness of the TaN bottom layer can range from about 10 Å to about 15 Å. In some embodiments, the one or more TiN layers can be formed by an ALD or a diffusion process. The TIN layers deposited with the ALD process can have a thickness between, for example, about 8 Å and about 12 Å, while the TiN layers deposited with a diffusion process can be thicker, e.g., with a thickness ranging from about 12 Å to about 50 Å.

In some embodiments, the WFM stack can include titanium/aluminum (Ti/Al) bi-layers or a Ti—Al alloy, both of which can be deposited with an ALD process. By way of example and not limitation, the WFM stack can have a thickness range between about 20 Å and about 35 Å. The WFM stack can tune the work function of the metal gate electrode and influence the threshold voltage of the transistor. The thickness and the number of the one or more TiN layers, in combination with the WFM stack, can set the transistor's threshold voltage.

In some embodiments, a metal fill layer can include a TiN barrier layer and a tungsten (W) metal stack. The TiN barrier layer, which can be deposited with an ALD process, can protect the underlying WFM stack from a fluorine chemistry used during the deposition of the W metal stack. According to some embodiments, the thickness of the TiN barrier layer can be between about 40 Å and about 50 Å.

In some embodiments, capping layer250can be a nitride etch stop layer formed to protect gate electrode220during a subsequent formation of contacts. In some embodiments, capping layer250can be silicon nitride (SixNy)

In some embodiments, spacers240can be made of a dielectric material, such as SiO2, silicon oxynitride (SiON), carbon-doped silicon nitride (SiCN), silicon oxycarbide (SiOxCy), or SixNy. In some embodiments, the thickness of spacers240can range from about 2 nm to about 5 nm. Spacers240can be a stack of one or more layers made of the same or different materials. In some embodiments, spacers240can be used as alignment masks during the formation of a FET's S/D regions on top of which S/D epitaxial layers260are formed.

Method100continues with operation120and the formation of a contact opening in dielectric210. For example,FIG.3shows a contact opening300in dielectric210. Contact opening300can be formed via patterning dielectric210using photolithography and etch processes. For instance, a coat of photoresist can be applied on dielectric210. The photoresist can be developed according to a desired pattern; for example, a desired pattern could be openings in dielectric210to expose a portion of the S/D epitaxial layer260. The undeveloped areas of the photoresist can be stripped with a wet or dry etch process to leave the desired pattern of developed photoresist on dielectric210. A dry etch process can be used, for example, to remove exposed areas of dielectric210between the photoresist pattern. Areas of dielectric210covered by the developed photoresist can be protected from the etch chemistry of the dry etch process and therefore not etched. The etch process can be anisotropic so that the sidewalls of contact opening150can be substantially vertical (e.g., greater than 80°, such as 87°). By way of example and not limitation, a dry etch chemistry can include a mixture of carbon fluoride gases (CFx). Capping layer250can protect gate electrode220during the etch process and while dielectric210is being etched. The etch process may also etch part of spacer240. However, the etching selectivity towards dielectric210can be much higher (e.g., greater than 5:1) and therefore dielectric210will be etched faster than, for example, spacer240. The etch process may be end-pointed when S/D epitaxial layer260is exposed.

During the formation of contact opening300, the top surface of S/D epitaxial layer260may be partially etched according to some embodiments. In some embodiments, and while the top surface of the S/D epitaxial layer260is being etched, S/D material (e.g., SiGe) can be sputtered from the top surface of S/D region and get “re-deposited” to the sidewall surfaces at the bottom of contact opening300. The re-deposited SiGe layer is not shown inFIG.3for simplicity.

In some embodiments, contact opening300can be a “shared” opening between gate electrode220and one of the S/D epitaxial layers260. By way of example and not limitation, in the 3-dimensional space, contact opening300can be considered a trench in dielectric210along the y-axis. In some embodiments, a plurality of contact openings similar to contact opening300may be formed in dielectric210in other locations of dielectric210. In some embodiments, contact openings similar to opening300can be formed on gate electrodes220. According to some embodiments, contact opening300may have, for example, an AR between about 3 and about 10, a top CD below about 17 nm, a bottom CD below about 14 nm, and a height of about 60 nm.

In some embodiments, prior to any metal deposition, opening300is treated with a pre-clean process to remove any native oxide that may have formed on the top surface of S/D epitaxial layer260. A native oxide can be formed, for example, via exposure of a wafer to air between processes or as a “byproduct” during the formation of contact opening300. A native oxide can increase the metal contact resistance if not removed.

By way of example and not limitation, the pre-clean process can be a combination of a physical etch and a chemical etch. For example, the physical etch may include argon (Ar) sputtering. Ar sputtering can remove, for example, between about 30 Å to about 60 Å of native oxide from the top surface of S/D epitaxial layer260. However, due to the AR of contact opening300(e.g., between about 3 to about 10), Ar sputtering may not be sufficient to remove a native oxide from the bottom of contact opening300. The chemical etch may complement the Ar sputtering etch. By way of example and not limitation, the chemical etch may use a remote plasma from a mixture of ammonia (NH3), nitrogen trifluoride (NF3), and hydrogen (H2) gases. The plasma reacts with silicon containing oxides, such as the native oxide on S/D epitaxial layer260, to form a salt that can be sublimated at a temperature, for example, between about 100° C. to about 200° C.

Method100continues with operation130. In130, once the top surface of S/D epitaxial layer260has been cleaned, a subsequent in-situ metal deposition forms a metal400and a barrier layer410in contact opening300as shown inFIG.4. According to some embodiments, metal400can be titanium (Ti). By way of example and not limitation, Ti can be deposited via a PVD process that uses a radio frequency source (RF PVD). RF PVD can improve Ti bottom coverage and mitigate Ti overhang, or pinch-off, at the top corners of contact opening300. According to some embodiments, Ti may be deposited thicker at the bottom of contact opening300compared to the sidewalls of contact opening300. In some embodiments, the Ti thickness can range from about 100 Å to about 130 Å. In some embodiments, barrier layer410can be titanium nitride (TiN) deposited conformally with an ALD process at a deposition temperature between about 300° C. and 350° C. By way of example and not limitation, the thickness of TiN can range from about 15 Å to about 20 Å. TiN can prevent oxidation of the underlying Ti metal400and provide an adhesion surface for a Co layer. According to some embodiments, barrier layer410may not be limited to TiN and may include other materials such as tantalum nitride (TaN), indium oxide (In2O3), tungsten nitride (WN), tantalum (Ta), niobium (Nb), zirconium (Zr), vanadium (V), tungsten (W), and ruthenium (Ru).

In some embodiments, a rapid thermal anneal (RTA) process can be used to form titanium silicide (TiSi2) at the bottom of contact opening300. TiSi2is formed when metal400reacts with silicon in the top surface of S/D epitaxial layer260during the RTA process. In some embodiments, the RTA temperature can range from about 500° C. to about 600° C. The RTA process can last from about 30 s to about 200 s. According to some embodiments, heat lamps can be used in the RTA process. However, other annealing methods may be used; for example, a laser anneal may be used. In some embodiments, a single RTA operation can be sufficient to form TiSi2. However, more than one RTA operations are possible.FIG.5shows contact opening300after an RTA process, where a silicide layer500is formed on S/D epitaxial layer260. In some embodiments, the thickness of silicide layer500can range from about 5 nm to about 15 nm.

In areas where silicon is exposed, metal400can react with silicon to form a silicide. In other areas where no silicon is present (e.g., where silicon is covered with oxides, nitride layers, or metals), there is little or no silicide formation. Additional metals that may be used to form silicides with a stable, low-resistance phase (e.g., grain structure) include cobalt (Co), nickel (Ni), tungsten (W), tantalum (Ta), and molybdenum (Mo). The resulting silicides can include cobalt silicide (CoSi2), nickel silicide (NiSi), tungsten silicide (WSi2), tantalum silicide (TaSi2), and molybdenum silicide (MoSi2) respectively. The annealing conditions (e.g., annealing temperature, annealing time, and method of heating) can influence the silicide's thickness, composition, and phase (grain structure). Some silicides may require one or more annealing steps to achieve a low resistance phase.

Method100continues with operation140and the formation of a liner layer600on barrier layer410as shown inFIG.6. In some embodiments, liner layer600is a Co layer with a thickness between about 70 Å to about 110 Å (e.g., 90 Å). By way of example and not limitation, liner layer600can be deposited with an RF PVD process at room temperature (e.g., about 24° C.). In some embodiments, the deposition pressure during the liner layer formation can be between about 50 mTorr and about 150 mTorr (e.g., 100 mTorr). According to some embodiments, the RF PVD process may utilize a high frequency RF generator that can operate between about 40 MHz to about 45 MHz and have an output power between about 500 Watts to 3000 Watts. Further, during the liner layer deposition, the RF power is applied to the Co target. In some embodiments, liner layer600covers barrier layer410. Liner layer600does not fill contact opening300and its function is to provide a growth surface for a subsequent Co deposition, according to some embodiments.

Method100continues with operation150and the formation of a metal layer700deposited on liner layer600as shown inFIG.7. Metal layer700partially fills contact opening300(shown inFIG.6) and forms opening710, which is smaller than contact opening300. According to some embodiments, metal layer700is a Co layer that can be deposited with a CVD process at a deposition temperature between about 150° C. and about 200° C. and at a process pressure below 10 Torr—for example, between about 2 Torr and about 5 Torr. By way of example and not limitation, the thickness of the deposited Co layer can be about 180 Å. Co deposition via CVD can be accomplished by using, for example, an organometallic precursor.

Method100continues with operation160and the formation of a metal layer800on metal layer700to fill opening710(ofFIG.7) as shown inFIG.8. In some embodiments, metal layer800is deposited and reflowed concurrently (e.g., reflow and co-deposition). In some embodiments, the deposition and reflow of metal layer800can be performed in an exemplary PVD reactor900, a cross section of which is depicted inFIG.9. An external DC and RF power generators (not shown inFIG.9) can be connected to PVD reactor900through respective feed-through connections920and930located on a top surface910of PVD reactor900. A Co target940can be mounted on an inner surface915of PVD reactor900. In some embodiments, an Ar plasma can be used to sputter Co material from Co target940. Co target940can be separated by a spacing950from an electrostatic chuck970. During processing, a wafer960can be positioned on electrostatic chuck970. Wafer960can be secured in place on electrostatic chuck970with an electrostatic force. Additionally, electrostatic chuck970includes a heater (not shown inFIG.9) than can provide heat to wafer960. Electrostatic chuck970includes a feed-through connection980, which can be connected to another external RF generator (not shown inFIG.9). This external RF generator can provide an RF power to wafer960through feed-through connection980and electrostatic chuck970. A coil magnet990, located on inner sidewall surfaces of PVD chamber900, can be used to modulate the directionality of the ionic species in the plasma. Magnet915, located on top surface910, can confine argon ions (Ar+) closer to target940. In some embodiments, the spacing between magnet915and target940can range from about 0.8 mm to about 1.2 mm.

The locations of the aforementioned elements can be different depending on the design of exemplary PVD reactor900, therefore the depiction of exemplary PVD reactor900inFIG.9should not be limiting. For illustration purposes,FIG.9includes select portions of exemplary PVD reactor900and other portions (not shown) may be included. For example, gas lines, gas exhaust lines, electrical connections, heaters, valves, additional panels, external peripherals and equipment may be included.

In some embodiments, the deposition of metal layer800can concurrently occur with a “reflow” process. During the deposition process, argon ions (Ar+) from the plasma can sputter Co material from target940. During the reflow process, Ar+impinge (bombard) the surface of wafer960so that the sputtered Co material can be “repositioned,” or reflowed, through a re-sputtering process in opening710ofFIG.7. To assist with the reflow process, wafer960is heated via the heater in electrostatic chuck960to a temperature between about 300° C. and about 500° C. (e.g., 450° C.). According to some embodiments, the deposition and reflow process is balanced to achieve an optimal gap fill performance. For example, if the deposition rate is high and the reflow is weak, pinch-off at the entrance of opening710may occur and a void can be formed. Conversely, if the deposition rate is low and the reflow is strong, Co metal may not fill opening710by the end of the co-deposition/reflow process.

In some embodiments, the deposition and the reflow processes can be individually controlled via an independent top and bottom RF power. The independent top and bottom RF power can be applied respectively to target940and wafer960via corresponding feed-through connections930and980. The top and bottom RF power can be provided by corresponding external RF generators as discussed above. By way of example and not limitation, an external RF generator, with a power output between about 500 Watts to about 3000 Watts, can provide the top RF power with a frequency between about 40 MHz to about 45 MHz. Another RF generator, with a power output between about 20 Watts to about 100 Watts, can provide the bottom RF power with a frequency between about 10 MHz to about 15 MHz. According to some embodiments, the bottom to top RF power ratio can range from about 4% to about 10% for an optimal metal gap fill window. Depending on the contact opening, the bottom to top RF power ratio may be adjusted outside the provided window (e.g., from about 4% to about 10%). Therefore, the RF power ratio provided is exemplary and not limiting.

The top RF power may not be sufficient to sputter material from target940and therefore, a DC power from an external DC power generator can be applied to target940through feed-through connection920to attract Ar+and increase the sputter rate of Co material from target940. In some embodiments, the DC power can range from about 200 Watts to about 1000 Watts. In some embodiments, the deposition rate of the deposited Co metal depends on the DC to top RF power ratio, which can be greater than about 25% (e.g. about 65%). According to some embodiments, the top RF power can tune the Co deposition rate and improve deposition uniformity. In some embodiments, high DC to top RF power ratio can increase the deposition rate and cause pinch off. On the other hand, a low DC to top RF power ratio can weaken Co deposition and result in poor gap fill of opening710. In other words, the DC to top RF power ratio can influence the balance between deposition and reflow.

According to some embodiments, spacing950can range between about 70 mm to about 130 mm (e.g., 95 mm to 105 mm). In some embodiments, spacing950can serve as another factor to control the deposition and uniformity of metal layer800. Coil magnet990, fitted on the inner sidewall surfaces of PVD reactor900, can further assist with the metal deposition uniformity and influence the impingement angle of Art on the wafer's surface during the reflow process.

Referring to operation170of method100, a chemical mechanical planarization (CMP) process can be used to remove the metal layers deposited over dielectric210(e.g.,400,410,600,700, and800) as shown inFIG.10and to form metal contact1000over S/D epitaxial layer260. CMP is a polishing process, which utilizes a chemical slurry in conjunction with a polishing pad to remove conductive or dielectric materials from a top surface of the wafer. CMP may achieve a planar and smooth topography across a wafer upon which additional layers of integrated circuitry can be built. The CMP process can be either end-pointed or timed. In an end-pointed CMP process, polishing can be automatically terminated when a polish rate difference is detected; for example, when a polish rate difference is detected between the layer that is being polished and an underlying layer. In some embodiments, the CMP process can use different slurry chemistries and polishing pads to remove the metal layers deposited over dielectric210(e.g.,400,410,600,700, and800).

In a similar manner as described above with respect to S/D epitaxial layer260, metal contacts can be formed on metal gate electrodes, such as gate electrode220. Further, a “shared” metal contact can be formed between a gate electrode and an epitaxial layer, where the shared metal contact “touches” both the gate electrode and the S/D epitaxial layer. Shared metal contacts are within the spirit and scope of this disclosure and can be fabricated using some or all of the operations of method100described above.

The embodiments described herein are directed to a metallization process with improved gap fill properties. According to some embodiments, the metallization process can fill contact holes with an AR between about 3 to about 10 and a height greater than about 60 nm. By way of example and not limitation, the metallization process includes a co-deposition/reflow PVD process. According to some embodiments, the deposition and reflow process can be individually controlled via an independent top RF power and bottom RF power provided to the target and the wafer respectively. The metal deposition rate can further be modulated by a DC power which can be applied to the target. As a result, the DC to top RF power ratio can also be independently controlled, according to some embodiments.

In some embodiments, a method includes forming a contact opening in an oxide, depositing a barrier layer in the contact opening, depositing a liner layer on the barrier layer, depositing a first metal layer on the liner layer to partially fill the contact opening. The method further includes, depositing a second metal layer on the first metal layer to fill the contact opening, where depositing the second metal layer includes sputter depositing the second metal layer using a first RF power and a DC power, and reflowing the second metal layer using a second RF power.

In some embodiments, a method includes providing a substrate with a source/drain epitaxial layer thereon, depositing a dielectric layer over the substrate, etching a contact opening in the dielectric layer to expose the source/drain epitaxial layer. The method further includes, depositing a barrier layer in the contact opening; depositing a liner layer on the barrier layer; depositing a first metal layer on the liner layer to partially fill the contact opening; and depositing a second metal layer on the first metal layer to fill the contact opening, where depositing the second metal layer includes concurrently sputtering and reflowing the second metal layer with a first RF power applied to a target and a second RF power applied to the substrate.

In some embodiments, a method includes providing a substrate with a FET thereon, depositing an oxide over the substrate, etching a first contact opening and a second contact opening in the oxide to expose a gate of the FET and a source/drain epitaxial layer of the FET respectively, depositing a barrier layer in the first and the second openings, depositing a liner layer over the barrier layer, depositing a first metal layer over the liner layer to partially fill the first and the second contact openings. The method further includes, depositing a second metal layer over the first metal layer to fill the first and the second contact openings, where depositing the second metal layer includes sputter depositing and reflowing the second metal layer with each of a first RF power and a DC power applied to a target and a second RF power applied to an electrostatic chuck in contact with the substrate.

It is to be appreciated that the Detailed Description section, and not the Abstract of the Disclosure section, is intended to be used to interpret the claims. The Abstract of the Disclosure section may set forth one or more but not all possible embodiments of the present disclosure as contemplated by the inventor(s), and thus, are not intended to limit the subjoined claims in any way.

The foregoing disclosure outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.