Patent ID: 12235713

DETAILED DESCRIPTION

Hereinafter, example embodiments will be described with reference to the accompanying drawings.

FIG.1is a block diagram showing a memory system according to some example embodiments.

A memory system10may include a host device100and a storage device200. The storage device200may also include a storage controller210and a non-volatile memory (NVM)220. Also, in some example embodiments, the host device100may include a host controller110and a host memory120. The host memory120may function as a buffer memory for temporarily storing data to be transmitted to the storage device200or the data received from the storage device200.

The storage device200may be a storage medium for storing data according to a request from the host device100. For example, the storage device200may be at least one of a solid-state drive (SSD), an embedded memory, and a detachable external memory. If the storage device200is an SSD, the storage device200may be a device that complies with an non-volatile memory express (NVMe).

If the storage device200is an embedded memory or an external memory, the storage device200may be a device that complies with a universal flash storage (UFS) or an embedded multi-media card (eMMC) standard. The host device100and the storage device200may each generate and transmit packets complying with the adopted standard protocol.

When the non-volatile memory220of the storage device200includes a flash memory, the flash memory may include a2D NAND memory array or a3D (or vertical) NAND (VNAND) memory array. As another example, the storage device200may also include various other types of non-volatile memories. For example, a Magnetic RAM (MRAM), a spin-transfer torque MRAM, a conductive bridging RAM (CBRAM), a Ferroelectric RAM (FeRAM), a Phase RAM (PRAM), a resistive memory (Resistive RAM) and various other types of memories may be applied to the storage device200.

In some example embodiments, the host controller110and the host memory120may be implemented as different semiconductor chips. Alternatively, in some example embodiments, the host controller110and the host memory120may be integrated on the same semiconductor chip. As an example, the host controller110may be one of a plurality of modules provided in the application processor, and such an application processor may be implemented as a system on chip (SoC). Further, the host memory120may be an embedded memory provided in the application processor, or a non-volatile memory or a memory module placed outside the application processor.

The host controller110may manage an operation of storing data of a buffer region (for example, write data) in the non-volatile memory220or storing data of the non-volatile memory220(for example, read data) in the buffer region.

The storage controller210may include a host interface211, a memory interface212and a central processing unit (CPU)213. Also, the storage controller210may further include a flash translation layer (FTL)214, a packet manager215, a buffer memory216, an error correction code (ECC) engine217, and an advanced encryption standard (AES) engine218.

The storage controller210may further include a working memory into which the flash translation layer (FTL)214is loaded, and when the CPU213executes the flash translation layer214, the data write and read operations of the non-volatile memory may be controlled.

The host interface211may transmit and receive packets to and from the host device100. Packets transmitted from the host device100to the host interface211may include a command, data to be written in the non-volatile memory220, or the like. The packets transmitted from the host interface211to the host device100may include a response to a command, data read from the non-volatile memory220or the like.

The memory interface212may transmit the data to be written in the non-volatile memory220to the non-volatile memory220or receive the read data from the non-volatile memory220. The memory interface212may be implemented to comply with standard conventions such as Toggle or Open NAND Flash Interface (ONFI).

The flash translation layer214may perform various operations such as address mapping, wear-leveling, and garbage collection. The address mapping operation is an operation of changing a logical address received from a host into a physical address which is used for actually storing the data in the non-volatile memory220. The wear-leveling operation is a technique for ensuring that blocks in the non-volatile memory220are used uniformly to prevent an excessive degradation of a particular block, and may be implemented, for example, through a firmware technique of balancing the erasure counts of the physical blocks. The garbage collection operation is a technique for ensuring an available capacity in the non-volatile memory220through a method of copying the valid data of the block to a new block and then erasing the existing block.

The packet manager215may generate a packet according to the protocol of the interface with the host device100, or may parse various types of information from the packet received from the host device100. Further, the buffer memory216may temporarily store the data to be recorded in the non-volatile memory220or the data read from the non-volatile memory220. The buffer memory216may be provided inside the storage controller210, but example embodiments are not limited thereto and the buffer memory216may be placed outside the storage controller210.

The ECC engine217may perform error detection and correction functions of the data to be recorded in the non-volatile memory220or the read data that is read from the non-volatile memory220. More specifically, the ECC engine217may generate parity bits for the write data to be written on the non-volatile memory220, and the parity bits generated in this way may be stored in the non-volatile memory220together with the write data. When reading the data from the non-volatile memory220, the ECC engine217may correct an error of the read data and output the read data with a corrected error, using the parity bits read from the non-volatile memory220together with the read data.

The AES engine218may perform at least one of encryption and decryption operations of the data which is input to the storage controller210, using a symmetric-key algorithm.

A machine learning module219may perform a machine learning operation on the data generated from the storage device200.

In some example embodiments, the machine learning module219may include an input layer, a hidden layer, and an output layer.

The input layer may be provided with learning data for each time point from the past time point to the present time point. The learning data for each time point may include, for example, log data collected from various components (for example, various types of hardware and firmware including a non-volatile memory220, a buffer memory216, and a temperature sensor230) included in the storage device200.

Such an input layer may be provided to the hidden layer for learning. In some example embodiments, although a Recurrent Neural Network (RNN) model that may receive time-series features and make sophisticated predictions may be applied as the hidden layer, example embodiments are not limited thereto.

When such learning is completed, prediction information (for example, a failure possibility) at a future time point further than the present time point may be calculated in the output layer. In some example embodiments, although the output layer may use a Multi-Layer Perceptron (MLP), example embodiments are not limited thereto

In some example embodiments, the machine learning module219may be implemented as firmware or software and operated by the storage device200. In this case, the machine learning module219may control the operation of the storage controller210. Also, in some example embodiments, the machine learning module219may be implemented as hardware and operated by the storage device200. In this case, the machine learning module219may be implemented in the form of another machine learning processor included in the storage device200.

The temperature sensor230may sense temperature of the storage device200, and provide the sensed temperature information to the storage controller210. Specifically, the temperature sensor230may sense the operating temperature of the storage device200and/or the surrounding environment temperature of the storage device200and/or the temperature of the components included in the storage device200, and provide the sensed temperature information to the storage controller210.

FIG.2is a diagram in which the storage controller and the non-volatile memory of the storage device ofFIG.1are reconfigured.

Referring toFIG.2, the storage device200may include a non-volatile storage220and a storage controller210. The storage device200may support a plurality of channels CH1to CHm, and the non-volatile storage220and the storage controller210may be connected through the plurality of channels CH1to CHm. For example, the storage device200may be implemented as a storage device such as an SSD.

The non-volatile storage220may include a plurality of non-volatile memory devices NVM11to NVMmn. Each of the non-volatile memory devices NVM11to NVMmn may be connected to one of the plurality of channels CH1to CHm through a corresponding way. For example, the non-volatile memory devices NVM11to NVM1nare connected to a first channel CH1through the ways W11to W1n, and the non-volatile memory devices NVM21to NVM2nmay be connected to a second channel CH2through the ways W21to W2n. In an example embodiment, each of the non-volatile memory devices NVM11to NVMmn may be implemented in a memory unit that may operate according to individual instructions from the storage controller210. For example, although each of the non-volatile memory devices NVM11to NVMmn may be implemented as a chip or a die, example embodiments are not limited thereto.

The storage controller210may transmit and receive signals to and from the non-volatile storage220through the plurality of channels CH1to CHm. For example, the storage controller210may transmit commands CMDa to CMDM, addresses ADDRa to ADDRm, and data DATAa to DATAm to the non-volatile storage220through the channels CH1to CHm, or may receive the data DATAa to DATAm from the non-volatile storage220.

The storage controller210may select one of the non-volatile memory devices connected to the channel through each channel, and may transmit and receive signals to and from the selected non-volatile memory device. For example, the storage controller210may select the non-volatile memory device NVM11among the non-volatile memory devices NVM11to NVM1nconnected to the first channel CH1. The storage controller210may transmit command CMDa, address ADDRa, and data DATAa to the selected non-volatile memory device NVM11through the first channel CH1or may receive the data DATAa from the selected non-volatile memory device NVM11.

The storage controller210may transmit and receive signals in parallel to and from the non-volatile storage220through different channels from each other. For example, the storage controller210may transmit a command CMDb to the non-volatile storage220through the second channel CH2, while transmitting a command CMDa to the non-volatile storage220through the first channel CH1. For example, the storage controller210may receive the data DATAb from the non-volatile storage220through the second channel CH2, while receiving the data DATAa from the non-volatile storage220through the first channel CH1.

The storage controller210may control the overall operation of the non-volatile storage220. The storage controller210may transmit the signal to the channels CH1to CHm to control each of the non-volatile memory devices NVM11to NVMmn connected to the channels CH1to CHm. For example, the storage controller210may transmit the command CMDa and the address ADDRa to the first channel CH1to control selected one among the non-volatile memory devices NVM11to NVM1n.

Each of the non-volatile memory devices NVM11to NVMmn may operate according to the control of the storage controller210. For example, the non-volatile memory device NVM11may program the data DATAa in accordance with the command CMDa, the address ADDRa, and the data DATAa provided to the first channel CH1. For example, the non-volatile memory device NVM21may read the data DATAb in accordance with the command CMDb and the address ADDRb provided to the second channel CH2, and transmit the read data DATAb to the storage controller210.

AlthoughFIG.2shows that the non-volatile storage220communicates with the storage controller210through m channels, and the non-volatile storage220includes n non-volatile memory devices corresponding to each channel, the number of channels and the number of non-volatile memory devices connected to one channel may be variously changed.

FIG.3is a diagram of a storage controller, memory interface and non-volatile memory according to some example embodiments. For example, the storage controller, the memory interface, and the non-volatile memory ofFIG.1may be reconfigured. The memory interface212may include a controller interface circuit212a.

The non-volatile memory220may include first to eight pins P11to P18, a memory interface circuit212b, a control logic circuit510, and a memory cell array520.

The memory interface circuit212bmay receive a chip enable signal nCE from the storage controller210through the first pin P11. The memory interface circuit212bmay transmit and receive signals to and from the storage controller210through second to eighth pins P12to P18according to the chip enable signal nCE. For example, when the chip enable signal nCE is in an enable status (e.g., a low level), the memory interface circuit212bmay transmit and receive signals to and from the storage controller210through second to eighth pins P12to P18.

The memory interface circuit212bmay receive a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE from the storage controller210through second to fourth pins P12to P14. The memory interface circuit212bmay receive a data signal DQ from the storage controller210or transmit the data signal DQ to the storage controller210through a seventh pin P17. The command CMD, the address ADDR, and the data DATA may be transferred through the data signal DQ. For example, the data signal DQ may be transferred through a plurality of data signal lines. In this case, the seventh pin P17may include a plurality of pins corresponding to the plurality of data signals.

The memory interface circuit212bmay acquire the command CMD from the data signal DQ received in an enable section (e.g., a high level status) of the command latch enable signal CLE on the basis of the toggle timings of the write enable signal nWE. The memory interface circuit212bmay acquire the address ADDR from the data signal DQ received in the enable section (e.g., a high level status) of the address latch enable signal ALE on the basis of the toggle timings of the write enable signal nWE.

In some example embodiments, the write enable signal nWE holds a static status (e.g., a high level or a low level) and then may be toggled between the high level and the low level. For example, the write enable signal nWE may be toggled at the section in which the command CMD or the address ADDR is transmitted. Accordingly, the memory interface circuit212bmay acquire the command CMD or the address ADDR on the basis of the toggle timings of the write enable signal nWE.

The memory interface circuit212bmay receive a read enable signal nRE from the storage controller210through the fifth pin P15. The memory interface circuit212bmay receive the data strobe signal DQS from the storage controller210through a sixth pin P16, or may transmit the data strobe signal DQS to the storage controller210.

In the data DATA output operation of the non-volatile memory220, the memory interface circuit212bmay receive the read enable signal nRE toggled through fifth pin P15before outputting the data DATA. The memory interface circuit212bmay generate the data strobe signal DQS toggled on the basis of the toggling of the read enable signal nRE. For example, the memory interface circuit212bmay generate the data strobe signal DQS that starts toggle after a predetermined delay (e.g., tDQSRE) on the basis of the toggling start time of the read enable signal nRE. The memory interface circuit212bmay transmit a data signal DQ including the data DATA on the basis of the toggle timing of the data strobe signal DQS. As a result, the data DATA may be arranged at the toggle timing of the data strobe signal DQS and transmitted to the storage controller210.

In the data DATA input operation of the non-volatile memory220, when the data signal DQ including the data DATA is received from the storage controller210, the memory interface circuit212bmay receive the data strobe signal DQS toggled together with the data DATA from the storage controller210. The memory interface circuit212bmay acquire the data DATA from the data signal DQ on the basis of the toggle timing of the data strobe signal DQS. For example, the memory interface circuit212bmay acquire the data DATA by sampling the data signal DQ at a rising edge and a falling edge of the data strobe signal DQS.

The memory interface circuit212bmay transmit a ready/busy output signal nR/B to the storage controller210through an eighth pin P18. The memory interface circuit212bmay transmit status information about the non-volatile memory220to the storage controller210through the ready/busy output signal nR/B. When the non-volatile memory220is in the busy status (that is, when the internal operations of the non-volatile memory220are being performed), the memory interface circuit212bmay transmit the ready/busy output signal nR/B indicating the busy status to the storage controller210. When the non-volatile memory220is in the ready status (i.e., the internal operations of the non-volatile memory220are not performed or are completed), the memory interface circuit212bmay transmit the ready/busy output signal nR/B indicating the ready status to the storage controller210.

For example, while the non-volatile memory220reads the data DATA from the memory cell array520according to a page read command, the memory interface circuit212bmay transmit the ready/busy output signal nR/B indicating the busy status (e.g., a low level) to the storage controller210. For example, while the non-volatile memory220programs the data DATA into the memory cell array520according to the program instruction, the memory interface circuit212bmay transmit the ready/busy output signal nR/B indicating the busy status to the storage controller210.

The control logic circuit510may generally control various operations of the non-volatile memory220. The control logic circuit510may receive the command/address CMD/ADDR acquired from the memory interface circuit212b. The control logic circuit510may generate control signals for controlling other components of the non-volatile memory220according to the received command/address CMD/ADDR. For example, the control logic circuit510may generate various control signals for programing the data DATA in the memory cell array520or reading the data DATA from the memory cell array520

The memory cell array520may store the data DATA acquired from the memory interface circuit212baccording to the control of the control logic circuit510. The memory cell array520may output the stored data DATA to the memory interface circuit212baccording to the control of the control logic circuit510.

The memory cell array520may include a plurality of memory cells. For example, a plurality of memory cells may be flash memory cells. However, example embodiments are not limited thereto, and the memory cells may be a Resistive Random Access Memory (RRAM) cell, a Ferroelectric Random Access Memory (FRAM) cell, a Phase Change Random Access Memory (PRAM) cell, a Thyristor Random Access Memory (TRAM) cell, and a Magnetic Random Access Memory (MRAM) cell. Hereinafter, example embodiments of the present disclosure will be described with a focus on an example embodiment in which the memory cells are NAND flash memory cells.

The storage controller210may include first to eighth pins P21to P28, and a controller interface circuit212a. The first to eighth pins P21to P28may correspond to the first to eighth pins P11to P18of the non-volatile memory220.

The controller interface circuit212amay transmit a chip enable signal nCE to the non-volatile memory220through a first pin P21. The controller interface circuit212amay transmit and receive signals to and from the non-volatile memory220selected through the chip enable signal nCE through the second to eighth pins P22to P28.

The controller interface circuit212amay transmit the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the non-volatile memory220through the second to fourth pins P22to P24. The controller interface circuit212amay transmit the data signal DQ to the non-volatile memory220or receive the data signal DQ from the non-volatile memory220through a seventh pin P27.

The controller interface circuit212amay transmit the data signal DQ including the command CMD or the address ADDR to the non-volatile memory220along with a toggled enable signal nWE. The controller interface circuit212amay transmit the data signal DQ including the command CMD to the non-volatile memory220by transmitting the command latch enable signal CLE having the enable status, and may transmit the data signal DQ including the address ADDR to the non-volatile memory220by transmitting the address latch enable signal ALE having the enable status.

The controller interface circuit212amay transmit the read enable signal nRE to the non-volatile memory220through the fifth pin P25. The controller interface circuit212amay receive the data strobe signal DQS from the non-volatile memory220through the sixth pin P26, or may transmit the data strobe signal DQS to the non-volatile memory220.

In the data DATA output operation of the non-volatile memory220, the controller interface circuit212amay generate a toggling read enable signal nRE and transmit the read enable signal nRE to the non-volatile memory220. For example, the controller interface circuit212amay generate the read enable signal nRE that changes from the static status (e.g., a high level or a low level) to the toggle status before the data DATA is output. As a result, the data strobe signal DQS toggled on the basis of the read enable signal nRE may be generated in the non-volatile memory220. The controller interface circuit212amay receive the data signal DQ including the data DATA along with the toggled data strobe signal DQS from the non-volatile memory220. The controller interface circuit212amay acquire the data DATA from the data signal DQ on the basis of the toggle timing of the data strobe signal DQS.

In the data DATA input operation of the non-volatile memory220, the controller interface circuit212amay generate a toggled data strobe signal DQS. For example, the controller interface circuit212amay generate a data strobe signal DQS that changes from the static status (e.g., a high level or a low level) to the toggle status before transmitting the data DATA. The controller interface circuit212amay transmit the data signal DQ including the data DATA to the non-volatile memory220on the basis of the toggle timings of the data strobe signal DQS.

The controller interface circuit212amay receive a ready/busy output signal nR/B from the non-volatile memory220through the eighth pin P28. The controller interface circuit212amay identify the status information about the non-volatile memory220on the basis of the ready/busy output signal nR/B.

Hereinafter, the operation of the memory system according to some example embodiments will be described referring toFIGS.4to12.

FIG.4is a flowchart showing operation of a memory system according to some example embodiments.FIG.5is a flowchart for explaining a machine running operation performed in a storage device according to some example embodiments.FIGS.6to10are diagrams for explaining a machine running operation performed in a storage device according to some example embodiments.FIGS.11and12are diagrams for explaining the operation of the memory system according to some example embodiments.

First, referring toFIG.4, a machine running operation is performed on the storage device200(S100).

AlthoughFIG.4shows a sequence in which the machine learning operation (S100) is performed on the storage device200, and then, the command for requesting the failure possibility information about the storage device200is received from the host device100(S200), example embodiments are not limited to the shown operation sequence.

A time point of execution of the machine learning operation (S100) performed by the storage device200may be performed with various modifications, unlike the shown example. Also, in some example embodiments, the storage device200may perform the machine learning operation (S100) according to reception of a command for instructing the execution of the machine running operation from the host device100.

The machine learning operation performed in the storage device200may include, for example, log data collection operations (S110, S120) shown inFIG.5, and a machine learning performing operation (S130) using the log data.

Hereinafter, a more specific description will be given referring toFIGS.5-10.

Referring toFIG.5, log data is collected (S110).

Referring toFIG.6, a log monitor240of the storage device200is included in the storage device200and may collect the log data from various components216,220,233, and250constituting the storage device200.

FIG.6shows a buffer memory216including a DRAM216a, a non-volatile memory220including a NAND226and a PRAM227, various hardware233forming the storage device200such as a temperature sensor230, a capacitor231and a Cyclic Redundancy Code (CRC) module232, and a firmware250installed in the storage device200, as examples of the components included in the storage device200. However, example embodiments are not limited thereto.

In some example embodiments, the log monitor240may be implemented as a part of the machine learning module (219ofFIG.1). Also, in some other example embodiments, the log monitor240may be implemented as a separate module different from the machine learning module (219ofFIG.1).

In some example embodiments, the log monitor240may be implemented as software and operate on the storage device200, and the log monitor240may be implemented as hardware and operate on the storage device200.

The log monitor240may collect the log data from the operations of the buffer memory216, the non-volatile memory220, the hardware233and the firmware250included in the storage device200. Specifically, the log monitor240may collect the log data for predicting the failure possibility of the buffer memory216, the non-volatile memory220, the hardware233and the firmware250from the operations of the buffer memory216, the non-volatile memory220, the hardware233and the firmware250included in the storage device200.

An example of the log data is shown inFIG.7.

Referring toFIGS.6and7, the log monitor240may collect the log data for predicting the failure possibility of the NAND226from the operation of the NAND226.

The log data for predicting the failure possibility of the NAND226may include a reclaim count of the NAND226, a read latency histogram of the NAND226, a read retry count of the NAND226, the number of Run Time Bad Block (RTBB) per die of the NAND226, the number of available die of the NAND226, a Uncorrectable Error CorreCtion (UECC) count of the NAND226and the like.

The reclaim operation of the NAND226is an operation which successfully reads the data stored in the NAND226through the read retry operation, but finds many error bits included in the read data, and shifts the data stored in the read page to the new page of the NAND226.

A high occurrence count of the reclaim operation of the NAND226indicates the failure possibility of the NAND226rises, the log monitor240collects the reclaim count of the NAND226as log data for predicting the failure possibility of the NAND226.

An increase in the read latency of the NAND226may indicate that the read retry or the reclaim operation is performed in the NAND226, and the read latency increases. Thus, the increase in the read latency of the NAND226may indicate that the failure possibility of the NAND226rises. Accordingly, the log monitor240collects the Read Latency Histogram of the NAND226as log data for predicting the failure possibility of the NAND226.

The read retry operation of the NAND226is an operation in which an error occurs in the read process and the read operation is performed again to read the same data.

Because the high occurrence count of the read retry operation of the NAND226indicates that the failure possibility of the NAND226rises, the log monitor240collects the read retry count of the NAND226as log data for predicting the failure possibility of the NAND226.

The Run Time Bad Block (RTBB) of the NAND226indicates a block in which a failure occurs during operation of the NAND226.

An increase in the RTBB of the NAND226indicates that the failure possibility of the NAND226rises. Therefore, the log monitor240collects the number of RTBB per die of the NAND226as log data for predicting the failure possibility of the NAND226.

The number of available dies of the NAND226indicates the number of the NAND chips actually used in NAND226, and the number of available dies of the NAND226decreases as the number of defective NAND chips increases.

Because the decrease in the number of available dies of the NAND226indicates that the failure possibility of the NAND226rises, the log monitor240collects the number of available dies of the NAND226as log data for predicting the failure possibility of the NAND226.

The UECC count of the NAND226indicates the occurrence count of uncorrectable error that occurs in NAND226.

Because an increase in the UECC count of the NAND226indicates that the failure possibility of the NAND226rises, the log monitor240collects the UECC count of the NAND226as log data for predicting the failure possibility of the NAND226.

In addition, the log monitor240may collect log data for predicting the failure possibility of the DRAM216afrom the operation of the DRAM216a.

The log data for predicting the failure possibility of the DRAM216amay include a Correctable Error CorreCtion (CECC) count of the DRAM216a, the temperature history of the DRAM216a, and the like.

The CECC count of the DRAM216ais a count of occurrence of 1-bit flip during operation of the DRAM216a.

Because an increase in the CECC count of DRAM216aindicates that the failure possibility of the DRAM216aincreases, the log monitor240collects the CECC count of the DRAM216aas log data for predicting the failure possibility of the DRAM216a.

The temperature history of the DRAM216ais data indicating the operating temperature at which the DRAM216aoperates over time.

Because the operating temperature of the DRAM216amay affect the failure possibility of the DRAM216a, the log monitor240collects the temperature history of the DRAM216aas log data for predicting the failure possibility of the DRAM216a.

Further, the log monitor240may collect log data for predicting the failure possibility of the capacitor231from the operation of the capacitor231.

The log data for predicting the failure possibility of the capacitor231may include the status (Capacitor Health) of the capacitor231or the like.

The status (Capacitor Health) of the capacitor231is information which indicates the status of the capacitor231by numerically expressing the charging status of the capacitor231existing in the storage device200. For example, if the initial value of the capacitor231is 100 (i.e., when the capacitor231is new), the charging capacity decreases as the capacitor231is used. Thus, the value of the status (Capacitor Health) of the capacitor231gradually decreases.

Because the status (Capacitor Health) of the capacitor231may affect the failure possibility of the capacitor231, the log monitor240collects the status (Capacitor Health) of the capacitor231as log data for predicting the failure possibility of the capacitor231.

Further, the log monitor240may collect log data for predicting the failure possibility of the temperature sensor230from the operation of the temperature sensor230.

The log data for predicting the failure possibility of the temperature sensor230may include the retry count of the temperature sensor230or the like.

The retry count of the temperature sensor230indicates a count of retry attempts that occur when reading the value sensed from the temperature sensor230.

Because an increase in the retry count of the temperature sensor230indicates that the failure possibility of the temperature sensor230rises, the log monitor240collects the retry count of the temperature sensor230as log data for predicting the failure possibility of the temperature sensor230.

Further, the log monitor240may collect log data for predicting the failure possibility of the CRC module232, from the operation of the CRC module232.

The log data for predicting the failure possibility of the CRC module232may include the error history of the CRC module232or the like.

The error history of the CRC module232may indicate the signal integrity status of the internal data path of the storage device200.

Because a high CRC error count indicates that the operation count of the CRC module232increases and the signal integrity status of the internal data path of the storage device200is not good, the log monitor240collects the error history of the CRC module232as log data for predicting the failure possibility of the CRC module232or the storage device200.

Further, the log monitor240may collect log data for predicting the failure possibility of the firmware250, from the operation of the firmware250.

The log data for predicting the failure possibility of the firmware250may include an exception count and a reset count that occur in the firmware250or the like.

An increase in the exception count and the reset count of the firmware250may indicate that the firmware250needs to be changed due to frequent occurrence of bug or the control operation of the storage device200not being performed smoothly. Therefore, the log monitor240collects the exception count and the reset count of the firmware250as log data for predicting the failure possibility of the firmware250or the storage device200.

Referring toFIG.5again, a determination with respect to whether the number of collected log data is larger than the predetermined number is made (S120). If the number of collected log data is smaller than the predetermined number (S120—N), the collection of log data continues (S110).

In some example embodiments, the log data collection operation (S110) may be continued until the number of log data satisfying a time window to be described later is collected.

Referring toFIG.6, in some example embodiments, the log monitor240may store the collected log data in the non-volatile memory220in the form of a DB228. That is, any one of the plurality of the NAND chips included in the non-volatile memory220may store the log data collected by the log monitor240.

However, example embodiments are not limited thereto, and the log monitor240may also store the collected log data in a region other than the non-volatile memory220. For example, the log monitor240may also store the collected log data in another storage region connected to the storage device200through a network.

Referring toFIGS.6and8, for example, the number of log data required for the log monitor240to collect log data from the operation of the NAND226in units of 10 seconds and predict the failure possibility of the NAND226may be 5 (i.e., p=5 ofFIG.8). In this case, the log monitor240may collect the above-mentioned log data from the operation of the NAND226for at least 50 seconds. That is, the failure possibility prediction operation of the NAND226of the machine learning module219may be performed after at least 50 seconds has elapsed.

Referring toFIG.5again, when the number of collected log data is larger than the predetermined number (S120—Y), the machine learning operation is performed (S130).

Referring toFIGS.1and8, each component may include k (k is a natural number) log data that has been accumulated up to a current time point, and the machine learning module219may predict the failure possibility of each component, using p (p is a natural number smaller than k) log data included within a predetermined time window among the k log data for each component collected according to passage of time. As time passes, the amount of k log data may increase.

As shown inFIG.8, when the present time point is assumed to be t, the machine learning module219may predict failure possibility (FP(t+1), FP(t+2), and FP(t+n)) up to a future n (n is a natural number) time point of a first component (component1), using the p log data included in the time window, among k log data collected from the past to the present time point from the operation of the first component (component1).

Further, the machine learning module219may predict the failure possibility (FP(t+1), FP(t+2), and FP(t+n)) up to the future n time point of a second component (component2), using p log data included in the time window, among the k log data collected from the past to the present time point from the operation of the second component (component2).

Such an operation of the machine learning module219may be performed on m (m is a natural number) components included in the storage device200.

Next, referring toFIGS.1and9, the machine learning module219may predict failure possibility of the storage device200(SSD Status(t+1), SSD Status(t+2), and SSD Status(t+n)) at different time points up to the future n time point of the storage device200on the basis of the failure possibility (FP(t+1), FP(t+2), and FP(t+n)) for each component predicted up to the future n time point.

For example, referring toFIG.10, the machine learning module219may form a matrix on the basis of the failure possibility (FP(t+1), FP(t+2), and FP(t+n)) for each component predicted for different time points up to the future n time point, and multiply the formed matrix by a weighted vector for each component to predict the failure possibility of the storage device200(SSD Status(t+1), SSD Status(t+2), and SSD Status(t+n)) for different time points up to the future n time point.

Here, the weighted vector for each component may be determined by various methods. In some example embodiments, a past failure rate for each component may be considered as the weighted vector for each component. However, example embodiments are not limited thereto.

ReferencingFIG.4again, the host device100transmits a command for requesting the failure possibility information about the storage device200to the storage device200(S200).

In some example embodiments, the command for requesting the failure possibility information about the storage device200may include a Get Log Page command.

For example, a log identifier of the Get Log Page command may be any one of C0to FF (wherein C0and FF are base16) as shown inFIG.11. That is, when the host device100specifies the log identifier as one of C0to FF and transmits the Get Log Page command to the storage device200, the host device100may request the failure possibility information about the storage device200from the storage device200.

Referring toFIG.4, the storage device200that has received the Get Log Page command responds to the host device100with the failure possibility information about the storage device200(S300).

In some example embodiments, the response of the storage device200may include status information for multiple prediction time points, as shown inFIG.12.

Specifically, referring toFIG.12, the storage device200may respond to the host device100with a score obtained by scoring the failure possibility of the storage device200and status information (Status) obtained by expressing the failure possibility of the storage device200as a status, at each prediction time point.

In some example embodiments, the status information (Status) may include an urgent status that requires immediate measure, a low status which is a non-urgent status and has relatively low failure possibility, a medium status which is a non-urgent status and has failure possibility higher than the low status, and a high status which is a non-urgent status and has failure possibility higher than the medium status and lower than the urgent status. However, example embodiments are not limited thereto, and the status information may be classified and expressed in various different ways as needed.

In some other example embodiments, in addition to the Get Log Page command discussed above, the command in which the host device100requests the failure possibility information about the storage device200may include a command of an admin command set, such as Get Feature command included in the NVMe standard.

In this case, when the host device100requests data of specific feature ID of the storage device200through the Get Feature command, the storage device200may define failure possibility information in the feature identifier (FID), and provide the host device100with the failure possibility information based on the specific feature ID.

Further, in some other example embodiments, the command in which the host device100requests the failure possibility information about the storage device200may include the Security Send command included in the NVMe standard.

In this case, when the host device100requests the failure possibility information from the storage device200through the Security Send command, the storage device200encrypts the failure possibility information with the security protocol, and may provide the failure possibility information to the host device100based on the Security Receive command.

Referring toFIG.4, the host device100determines RAID rebuilding timing of the storage device200on the basis of failure possibility information received from the storage device200(S400).

For example, when the failure possibility of the storage device200at the near future time point corresponds to the urgent status, the host device100may immediately perform the RAID rebuilding of the storage device200. When the failure possibility of the storage device200at the near future time point corresponds to the low status, the host device100may perform the RAID rebuilding at a later time, after sufficiently performing the I/O operation with the storage device200.

In this way, the predicted failure possibility information about the storage device is provided to the host device, and the host device may take necessary measures in advance before the failure actually occurs in the storage device. Accordingly, the reliability of the memory system can be improved.

Hereinafter, the operation of the memory system according to some other example embodiments will be described referring toFIG.13.

FIG.13is a diagram for explaining the operation of the memory system according to some other example embodiments. Hereinafter, repeated explanation of the aforementioned example embodiments will not be provided, and only the differences will be explained.

Referring toFIG.13, in this example embodiment, the storage device200may respond to the host device100with the failure possibility information for each component included in the storage device200as well as the failure possibility information about the storage device200.

Specifically, referring toFIG.13, the storage device200may respond to the host device100with the status information (Status) expressing the failure possibility of the storage device200(i.e., SSD), and status information (Status) expressing the failure possibility of each component included in the storage device200(i.e., Component1and Component2), at each prediction time point (i.e., t+1, t+2, . . . t+n).

At this time, although the status information (Status) may use the same classification method as that of example embodiments described above, example embodiments are not limited thereto.

In the case of this example embodiment, because the host device100may receive failure possibility information for the storage device200as a whole and each component in the storage device200, the storage device200can be managed more precisely.

FIG.14is a diagram showing a data center to which the storage device according to some example embodiments is applied.

Referring toFIG.14, a data center3000is a facility that gathers various types of data and provides services, and may be called a data storage center. The data center3000may be a system for providing search engines and database operations, and may be a computing system used by businesses such as banks and government agencies. The data center3000may include application servers3100to3100nand storage servers3200to3200m. The number of application servers3100to3100nand the number of storage servers3200to3200mmay be variously selected, and the number of application servers3100to3100nand the number of storage servers3200to3200mmay be different from each other.

The application server3100or the storage server3200may include at least one of the processors3110and3210and the memories3120and3220. Taking the storage server3200as an example, the processor3210may control the overall operation of the storage server3200, access the memory3220, and execute commands and/or data loaded into the memory3220. The memory3220may be a Double Data Rate Synchronous DRAM) DDR SDRAM), a High Bandwidth Memory (HBM), a Hybrid Memory Cube (HMC), a Dual In-line Memory Module (DIMM), an Optane DIMM or a Non-Volatile DIMM (NVM DIMM). According to an example embodiment, the number of processors3210and the number of memories3220included in the storage server3200may be variously selected.

In an example embodiment, the processor3210and the memory3220may constitute a processor-memory pair. In an example embodiment, the number of processors3210and the number of memories3220may be different from each other. The processor3210may include a single core processor or a multi-core processor. The aforementioned explanation of the storage server3200may be similarly applied to the application server3100. According to example embodiments, the application server3100may not include a storage device3150. The storage server3200may include at least one or more storage devices3250. The number of storage devices3250included in the storage server3200may be variously selected depending on example embodiments.

The application servers3100to3100nand the storage servers3200to3200mmay communicate with each other through a network3300. The network3300may be implemented, using Fibre Channel (FC), Ethernet, or the like. At this time, FC is a medium used for a relatively high-speed data transfer, and an optical switch that provides high performance/high availability may be used. The storage servers3200to3200mmay be provided as a file storage, a block storage or an object storage, depending on an access way of the network3300.

In an example embodiment, the network3300may be a storage-only network such as a Storage Area Network (SAN). For example, the SAN may be an FC-SAN which uses an FC network and is implemented according to FC Protocol (FCP). In another example, the SAN may be an IP-SAN which uses a TCP/IP network and is implemented according to a SCSI over TCP/IP or Internet SCSI (iSCSI) protocol. In another example embodiment, the network1300may be a general network such as a TCP/IP network. For example, the network1300may be implemented according to protocols such as an FC over Ethernet (FCoE), a Network Attached Storage (NAS), and a NVMe over Fabrics (NVMe-oF).

Hereinafter, the application server3100and the storage server3200will be mainly described. The description of the application server3100may also be applied to another application server3100n, and the description of the storage server3200may also be applied to another storage server3200m.

The application server3100may store data requested by the user or client to store in one of the storage servers3200to3200mthrough the network3300. Further, the application server3100may acquire the data requested by the user or the client to read from one of the storage servers3200to3200mthrough the network3300. For example, the application server3100may be implemented by a Web server or a Database Management System (DBMS).

The application server3100may access the memory3120nor the storage device3150nincluded in another application server3100nthrough the network3300, or may access the memories3220to3220mor the storage devices3250to3250mincluded in the storage servers3200to3200mthrough the network3300. As a result, the application server3100may perform various operations on the data stored in the application servers3100to3100nand/or the storage servers3200to3200m. For example, the application server3100may execute commands for moving or copying the data between the application servers3100to3100nand/or the storage servers3200to3200m. At this time, the data may be moved from the storage devices3250to3250mof the storage servers3200to3200mvia the memories3220to3220mof the storage servers3200to3200mor directly to the memories3120to3120nof the application servers3100to3100n. Data moving through the network3300may be data encrypted for security and privacy.

Taking the storage server3200as an example, an interface3254may provide a physical connection between the processor3210and a controller3251, and a physical connection between the NIC3240and the controller3251. For example, the interface3254may be implemented by a Direct Attached Storage (DAS) way in which the storage device3250is directly connected with a dedicated cable. For example, the interface3254may be implemented by various interface ways, such as an Advanced Technology Attachment (ATA), a Serial ATA (SATA), an external SATA (e-SATA), a Small Computer Small Interface (SCSI), a Serial Attached SCSI (SAS), a Peripheral Component Interconnection (PCI), a PCI express (PCIe), a NVM express (NVMe), an IEEE 1394, a universal serial bus (USB), a secure digital (SD) card, a multi-media card (MMC), an embedded multi-media card (eMMC), a Universal Flash Storage (UFS), an embedded Universal Flash Storage (eUFS), and a compact flash (CF) card interface.

The storage server3200may further include a switch3230and a NIC3240. The switch3230may selectively connect the processor3210and the storage device3250or may selectively connect the NIC3240and the storage device3250, according to the control of the processor3210.

In an example embodiment, the NIC3240may include a network interface card, a network adapter, and the like. The NIC3240may be connected to the network3300by a wired interface, a wireless interface (i.e., a Bluetooth interface), an optical interface, or the like. The NIC3240may include an internal memory, a DSP, a host bus interface, or the like, and may be connected to the processor3210, and/or the switch3230, or the like through the host bus interface. The host bus interface may also be implemented as one of the examples of the interface3254described above. In an example embodiment, the NIC3240may also be integrated with at least one of the processor3210, the switch3230, and the storage device3250.

In the storage servers3200to3200mor the application servers3100to3100n, the processor transmits the commands to the storage devices3130to3130nand3250to3250mor the memories3120to3120nand3220to3220mto program or read the data. At this time, the data may be data in which an error is corrected through an ECC engine. The data is data subjected to data bus inversion (DBI) or data masking (DM) process, and may include CRC information. The data may be data that is encrypted for security and privacy.

The storage devices3150to3150mand3250to3250mmay transmit the control signal and command/address signal to the NAND flash memory devices3252to3252maccording to the read command received from the processor. As a result, when data is read from the NAND flash memory devices3252to3252m, the Read Enable (RE) signal is input as a data output control signal, and may serve to output the data to the DQ bus. Data Strobe (DQS) may be generated using the RE signal. Command and address signals may be latched to the page buffer, depending on a rising edge or a falling edge of a Write Enable (WE) signal.

The controller3251may generally control the operation of the storage device3250. In an example embodiment, the controller3251may include a Static Random Access Memory (SRAM). The controller3251may write data in the NAND flash3252according to a write command, or may read the data from the NAND flash3252according to a read command. For example, the write command and/or the read command may be provided from the processor3210in the storage server3200, the processor3210min another storage server3200m, or the processors3110and3110nin the application servers3100and3100n. A DRAM3253may temporarily store (buffer) the data to be written in the NAND flash3252or the data read from the NAND flash3252. Also, the DRAM3253may store metadata. Here, the metadata is data generated by the controller3251to manage the user data or the NAND flash3252. The storage device3250may include an Secure Element (SE) for security or privacy.

In some example embodiments, the storage devices3150and3250may perform the aforementioned operations. That is, the storage devices3150and3250collect log data for each component included in the storage devices3150and3250, and may predict the failure possibility for each component on the basis of the collected log data.

The log data collected by each of the storage devices3150and3250may be stored inside each of the storage devices3150and3250, and the log data may be stored in a single dedicated storage device connected through the network3300.

At least one of the controllers, interfaces, modules, managers, engines, control logics, monitors, processors, switches, or other element represented by a block as illustrated inFIGS.1-3,6and14may be embodied as various numbers of hardware, software and/or firmware structures that execute respective functions described above, according to example embodiments. For example, at least one of the controllers, interfaces, modules, managers, engines, control logics, monitors, processors, switches, or other element may use a direct circuit structure, such as a memory, a processor, a logic circuit, a look-up table, etc. that may execute the respective functions through controls of one or more microprocessors or other control apparatuses. Also, at least one of the controllers, interfaces, modules, managers, engines, control logics, monitors, processors, switches, or other element may be specifically embodied by a module, a program, or a part of code, which contains one or more executable instructions for performing specified logic functions, and executed by one or more microprocessors or other control apparatuses. Also, at least one of the controllers, interfaces, modules, managers, engines, control logics, monitors, processors, switches, or other element may further include or may be implemented by a processor such as a central processing unit (CPU) that performs the respective functions, a microprocessor, or the like. Two or more of the controllers, interfaces, modules, managers, engines, control logics, monitors, processors, switches, or other element may be combined into one single component, element, module or unit which performs all operations or functions of the combined two or more of controllers, interfaces, modules, managers, engines, control logics, monitors, processors, switches, or other element. Also, at least part of functions of at least one of the controllers, interfaces, modules, managers, engines, control logics, monitors, processors, switches, or other element may be performed by another of these components. Further, although a bus is not necessarily illustrated in each of the above block diagrams, communication between the components may be performed through the bus. Functional aspects of the above example embodiments may be implemented in algorithms that execute on one or more processors. Furthermore, the controllers, interfaces, modules, managers, engines, control logics, monitors, processors, switches, or other element represented by a block or processing steps may employ any number of related art techniques for electronics configuration, signal processing and/or control, data processing and the like.

While example embodiments have been described with reference to the accompanying drawings, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present disclosure.