Patent ID: 12224211

Throughout the drawings and the detailed description, the same reference numerals refer to the same elements. The drawings may not be to scale, and the relative size, proportions, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience.

DETAILED DESCRIPTION

The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and/or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatuses, and/or systems described herein will be apparent after an understanding of the disclosure of this application. For example, the sequences of operations described herein are merely examples, and are not limited to those set forth herein, but may be changed as will be apparent after an understanding of the disclosure of this application, with the exception of operations necessarily occurring in a certain order. Also, descriptions of features that are known after understanding of the disclosure of this application may be omitted for increased clarity and conciseness.

The features described herein may be embodied in different forms, and are not to be construed as being limited to the examples described herein. Rather, the examples described herein have been provided merely to illustrate some of the many possible ways of implementing the methods, apparatuses, and/or systems described herein that will be apparent after an understanding of the disclosure of this application.

Throughout the specification, when an element, such as a layer, region, or substrate, is described as being “on,” “connected to,” or “coupled to” another element, it may be directly “on,” “connected to,” or “coupled to” the other element, or there may be one or more other elements intervening therebetween. In contrast, when an element is described as being “directly on,” “directly connected to,” or “directly coupled to” another element, there can be no other elements intervening therebetween.

As used herein, the term “and/or” includes any one and any combination of any two or more of the associated listed items.

Although terms such as “first,” “second,” and “third” may be used herein to describe various members, components, regions, layers, or sections, these members, components, regions, layers, or sections are not to be limited by these terms. Rather, these terms are only used to distinguish one member, component, region, layer, or section from another member, component, region, layer, or section. Thus, a first member, component, region, layer, or section referred to in examples described herein may also be referred to as a second member, component, region, layer, or section without departing from the teachings of the examples.

Spatially relative terms such as “above,” “upper,” “below,” and “lower” may be used herein for ease of description to describe one element's relationship to another element as shown in the figures. Such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as being “above” or “upper” relative to another element will then be “below” or “lower” relative to the other element. Thus, the term “above” encompasses both the above and below orientations depending on the spatial orientation of the device. The device may also be oriented in other ways (for example, rotated 90 degrees or at other orientations), and the spatially relative terms used herein are to be interpreted accordingly.

The terminology used herein is for describing various examples only, and is not to be used to limit the disclosure. The articles “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms “comprises,” “includes,” and “has” specify the presence of stated features, numbers, operations, members, elements, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, members, elements, and/or combinations thereof.

Due to manufacturing techniques and/or tolerances, variations of the shapes shown in the drawings may occur. Thus, the examples described herein are not limited to the specific shapes shown in the drawings, but include changes in shape that occur during manufacturing.

The features of the examples described herein may be combined in various ways as will be apparent after an understanding of the disclosure of this application. Further, although the examples described herein have a variety of configurations, other configurations are possible as will be apparent after an understanding of the disclosure of this application.

The present disclosure is a method of manufacturing an HV device200in which a gate edge region is formed as a shallow junction. Hereinafter, the present disclosure will be described in more detail with reference to examples illustrated in the drawings.

The following description provides a method of manufacturing a semiconductor device of which the depth of the drift region formed under the edge region of the gate electrode is formed shallower than the depth of the source and drain regions.

The following description also provides a method of manufacturing a semiconductor device for forming a drift region after forming a gate electrode.

The following description may reduce the area of the HV device200by forming as a shallow junction.

FIGS.1A to1Hare cross-sectional views illustrating a manufacturing process of a semiconductor device according to an example. The example will be described with reference to a semiconductor device in which an LV device100, an HV device200, and an nEDMOS device300are formed together on the semiconductor substrate10.

As illustrated inFIG.1A, a first deep well region20and a second deep well region30are formed in a semiconductor substrate10. The first deep well region20is a region in which an LV device100is formed, and the second deep well region30is a region in which an HV device200and an nEDMOS device300are formed. That is, the second deep well region30may be referred to as a high voltage device region. For example, although nEDMOS is illustrated inFIG.1, an nLDMOS device may be formed. This is because all of them are high voltage devices as BCD devices. Therefore, inFIG.1A, a low voltage device and a high voltage device are formed side by side, and may be isolated through an isolation region.

The first deep well region20and the second deep well region30may be formed by doping impurities of the same conductivity type or different conductivity types. In an example, the first deep well region20is HNW formed of N-type doping material, and the second deep well region30is HPW formed of a P-type doping material. The HPW region is formed relatively wider.

The device isolation region40having a predetermined depth is formed in the first deep well region20and the second deep well region30. As illustrated in the drawing, the depths of the device isolation regions40are the same. The device isolation region40may use LOCOS, STI, MTI, DTI, and the like. In this example, STI is used as the device isolation region40. The device isolation region40functions to partition an active region, which is a region where unit devices such as LV device100, HV device200, and nEDMOS device300are formed.

Gate insulating films101,201,301, and gate electrodes102,202,303are formed on the first deep well region20and the second deep well region30by performing a gate patterning process as illustrated atFIG.1B. The thicknesses of the gate insulating films101,201, and301are formed to be different from those of the LV device100and the HV device, and the thickness of the first gate insulating film101of the LV device100is formed to be smaller than that of the second gate insulating film201of the HV device. That is, because the HV device200operates at a higher voltage than the LV device100, the thickness of the second gate insulating film201of the HV device200is greater than that of the first gate insulating film101of the LV device.

The gate insulating film301of the nEDMOS device300is formed of gate insulating films having different thicknesses. As the below process describes, a relatively thin gate insulating film (third gate insulating film301a) and a thick gate insulating film (fourth gate insulating film301b) are formed on the well region or the drift region. The reason why the thin gate insulating film (third gate insulating film301a) is required is to increase the drain current (Idsat) value of the nEDMOS device. More current may flow due to lowering a threshold voltage (Vt) by using the thin gate insulating film. The reason why the thick gate insulating film (fourth gate insulating film301b) is required is that the thick gate insulating film (fourth gate insulating film301b) is not broken by the high voltage applied to the drain region. Thus, insulating films having different thicknesses are formed in the nEDMOS device.

The thickness of the first gate insulating film101may be the same as the thickness of the third gate insulating film301a. And the thickness of the second gate insulating film201may be the same as the thickness of the fourth insulating film301b. In such a case, the complexity of the process is reduced, and there are effects mentioned above. The current is increased by the thin gate insulating film, and the device reliability is improved by the thick gate insulating film.

FIG.1Cis a process of forming P-type well (PW) regions110afor an LV device100and P-type body region110bfor an nEDMOS device300. The PW regions110aand P-type body region110bare simultaneously formed by ion implanting P-type dopants into the upper surface of the substrate10using patterned photoresist masks22,32, and42. In order to form the PW region110aand P-type body region110bin the LV device100and the nEDMOS device, the PR masks22,32, and42having a pattern, in which only portions where the PW region110aand P-type body region110bare to be formed are opened, are formed on the substrate. The dopant may be implanted into the substrate using the same ion implantation energy. In this way, the depths of the PW region110aand P-type body region110bformed in the LV device100and the nEDMOS device300are the same as each other. And during ion implantation, the gate electrodes102and302also serve as masks in addition to the PR masks22,32and42. Thus, as illustrated inFIG.10, PW regions having different depths are formed. That is, a first depth d1of the PW regions115aand115bunder the gate electrode120is smaller than a second depth d2of the regions110aand110bother than the gate electrodes. That is, because the gate electrodes102and302serve as masks during the ion implantation, the depth of the ion implantation may be reduced by the thickness of the gate electrodes102and302. The second depth d2between the gate electrodes102and302and the device isolation region40is different from the first depth d1under the gate electrodes102and302. The different thickness between the first depth d1and the second depth d2is caused by the gate insulating films101and301and the gate electrodes102and302.

The P-type body region110bof the nEDMOS device300serves as a body region. The P-type body region110bis a region where a channel region is formed. The P type may be referred to as a first conductivity type, and the N type may be referred to as a second conductivity type. In addition, the photoresist masks22,32, and42may be removed through a plasma ashing and cleaning process.

FIG.1Dillustrates that after removing the photoresist mask, an N-type LDD (Lightly Doped Drain) region120is formed in the P-type well region110aof the LV device. The LDD region120is formed to have a predetermined thickness between the gate electrode102and the device isolation region40, and serves to mitigate the electric field of the high concentration drain region. Therefore, it also reduces hot carrier injection (HCI) caused by a high electric field. The LDD region120is formed to a depth smaller than the thickness of the PW region110aunder the gate electrode102formed by the process ofFIG.10.

In order to form an N-type drift as illustrated inFIG.1E, mask patterns24,34, and44are formed on the upper surface of the substrate10to cover the LV device100, HV device200, and nEDMOS device300, respectively. The mask patterns24,34, and44are simultaneously formed on the substrate, and they are referred to as a drift mask pattern. The mask pattern24for LV device100covers the entire surface of the LV gate electrode102and the LV active regions110a(LDD) and120(PW) so as not to implant dopants into the LV device100. The mask pattern44for nEDMOS device300covers the P-type body region110band a first portion of the nEDMOS gate electrode302. The mask pattern44for nEDMOS device300opens a second portion of the nEDMOS gate electrode302and a right portion of the active region to simultaneously form a shallow drift region211a,211b,211cand a deep drift region210a,210b,210c.

As shown inFIG.1E, the mask pattern34is formed on the HV gate electrode202. It is noted that the length of the mask pattern34is smaller than the length of the gate electrode202. The mask pattern34for HV device200partially covers the HV gate electrode202, and it opens both edge portion of the HV gate electrode202, such that a center portion of the HV gate electrode202is blocked by the mask pattern34. In such a state, ion implantations are performed to simultaneously form first and second shallow drift regions211aand211bas well as first and second deep drift regions210aand210bin the HV device200. The shallow drift regions211a,21bare formed by the dopants penetrated through the HV gate electrode202. On the other hand, the deep drift regions210a,210bare formed by the dopants directly implanted into the second deep well region30. So the depths between the shallow drift region211a,211b, and the deep drift region210a,210bare different even though the same implantation energy is used.

Ion implantations inFIG.1Emay use the tilt and rotation implantation method, as well as the vertical implantation method, with respect to the top surface of the substrate to have more uniform dopants distribution in the shallow drift regions211a,211b,211c. Both the first shallow drift region211aand the first deep drift region210aare merged to form a first drift region50in the HV device. In the same manner, both the second shallow drift region211band the second deep drift region210bare merged to form a second drift region60in the HV device.

Further, a third shallow drift region211cand a third deep drift regions210care also simultaneously formed in the nEDMOS device300by performing the ion implantations to form a third drift region70. The first, second and third shallow drift regions211a,221b,211chave the same depth (d3) with each other because they are formed in the same implantation conditions such as the same implantation energy and the same dopants concentration.

Herein, the shallow drift region211a,211b,211c, also refers to a shallow portion or first portion of the drift region50. The deep drift region210a,210b,210c, also refers to a deep portion or second portion of the drift region50.

The third depth d3of the first, second, and third shallow drift regions211depends on the thickness of the HV and nEDMOS gate electrodes202and302because the HV and nEDMOS gate electrodes202and302serves as another mask pattern. The first, second and third drift regions210a,210b,210chave the same depth (d4) with each other because they are formed in the same implantation conditions.

Shallow depths of the first and second shallow drift regions211a,211bin the HV device200are caused by the HV gate electrodes202serving as a mask pattern. The first and second shallow drift regions211a,211bare formed to overlap with edges of the HV gate electrode202, respectively, in the HV device200. The third depth, d3in HV device200are as shallow as LDD region120in the LV device100. The first and second shallow drift regions211are shallow junctions. Due to these shallow junctions under the gate electrode, the punch-through characteristic of the HV device200is improved compared with the conventional drift region. Accordingly, the short channel effect of the device may be improved that the gate length may be further reduced. This may reduce the chip size of the device, enabling a shrink down of chip size.

As shown inFIG.1F, spacers103,203and303are formed on sidewalls of the gate electrodes102,202, and302, respectively, after the first, second, and third drift regions50,60and70are formed.

As illustrated inFIG.1G, heavily doped regions N+ region140and P+ region150are formed. More specifically, the N+ region140is formed deeper than the LDD region120in the LDD region120of the P-type well region110aof the LV device, and the N+ region140is disposed respectively between the gate electrodes102,202, and302and the device isolation region40. In the nEDMOS device, the P+ region150and the N+ region140are formed in the P-type body region110b. The N+ region140formed in the deep drift region210of the HV device200is in contact with the device isolation region40and is formed to be spaced apart from the gate electrodes202and302by a predetermined distance. As a distance between the N+ region140and the gate electrodes202and302increases, the breakdown voltage increases.

Silicide layers170and silicide blocking layers180are formed, as illustrated inFIG.1H. The silicide layers170are formed over the N+ source/drain regions140and the gate electrodes102,202,302, respectively. On the other hand, the first, second, and third silicide blocking layers180are formed over the first, second, and third drift regions50,60,70, respectively. Further, the fourth silicide blocking layer180is also formed over the P-type body region110bto reduce the leakage current between the gate electrode302and the source region140in the nEDMOS device. The silicide blocking layers180block the formation of the silicide layer on a top surface of the substrate. The silicide blocking layers180are used to reduce the overall leakage current of the device, to increase the source-drain resistance, or to increase the breakdown voltage. The silicide layers170are formed by one of the materials selected from TiSi or CoSi2 or NiSi, etc. In this way, a semiconductor device with three devices is formed. Under the edge portion of the gate electrode, a shallow drift region is formed in the present example, and thus the chip size may be reduced by approximately 30% when compared with the typical process of forming the drift region before forming the gate electrode. As the chip size is reduced, many dies or chips may be secured in one wafer.

FIGS.2A and2Bare cross-sectional views of high voltage device structures (HV MOSs) manufactured according to an example.

FIG.2Ais a cross-sectional view of a high voltage device manufactured by split1of the present disclosure. Split1refers to forming the drift region410before forming the gate electrode. Split2refers to forming a drift region (FIGS.2B and440) after the gate electrode. In other words, Split2refers to forming a gate-through implantation (GTI) method.

As illustrated inFIG.2A, in the device formed by Split1, a bottom surface of the drift region410is almost flat. Because ion implantation is performed to form the drift region410without the gate electrode420on the entire surface of the semiconductor substrate, the drift region410is formed to have the same constant bottom depth in the HPW region430. The drift region410is formed before patterning the poly-Si layer, such that one drift junction laterally extends toward the other drift region. Thus, the two drift regions410are close to each other. Therefore, a short channel effect is increased in the device, and then a chip size shrink is difficult. For this reason, reducing an area of the HV device200is difficult. The depth of the drift region410is formed less than the depth of the device isolation region402. The device isolation region402is formed to have a depth greater than that of the drift region410to be electrically isolated from another drift region (not illustrated) of a neighboring device.

After a gate electrode420is formed, a source region412and a drain region412are formed at a predetermined distance from the gate electrode420in order to increase the breakdown voltage.

On the other hand,FIG.2bis a cross-sectional view of the high voltage device manufactured by Split2of the present disclosure. After the gate electrode450is formed, the mask pattern460is formed on the HV gate electrode450. It is noted that the length of the mask pattern460is smaller than a length of the gate electrode450. Then, ion implantations470are performed while the drift mask pattern460covers a portion of the gate electrode450. The drift mask pattern460is a photoresist material and exposes both side portions of the gate electrode450. The drift mask pattern460blocks ion implantation470into a center portion of the gate electrode450. So dopants470are implanted into the exposed gate electrode450and the active region430to form a shallow drift region441and a deep drift region440in the substrate430. The shallow drift region441is formed by the dopants penetrated through the gate electrode450. On the other hand, the deep drift region440is formed by the dopants directly implanted into the substrate430. So the depths between the shallow drift region and the deep drift region are different even though the same implantation energy is used. Ion implantations in theFIG.2Bmay use the tilt and rotation implantation method as well as the vertical implantation method with respect to the top surface of the substrate to have more uniform dopants distribution in the shallow drift regions211a,211b,211c.

The deep drift region440and the shallow drift region441are merged to form a first drift region480aor a second drift region480b. The two drift regions480a,480bare symmetric structure with respect to an imaginary center line dividing the gate electrode450. Due to the drift mask pattern460, the drift region480a,480bis not formed below the center portion of the gate electrode450. A third depth d3of the shallow drift region441is shallower than a fourth depth d4of the deep drift region440because the gate electrode450plays a role of another implantation mask pattern. The depth difference between the d3and the d4depends on the thickness of the gate electrode450and the gate insulating layer452. The shallow drift region441is in direct contact with the gate insulating film. The shallow drift region441has a depth greater than a depth of the source and the drain regions442. Here, the source and the drain regions442are formed at a predetermined distance from the spacer454formed on sidewalls of the gate electrode, such that a high voltage device having an increased overall breakdown voltage is obtained. Although not illustrated, a silicide blocking insulating film (also referred to as a silicide blocking layer) may be formed between the source region442or the drain region442and the gate electrode450. This increases the resistance between the gate electrode and the drain region (or source region), resulting in reducing the leakage current between the gate electrode and the drain region (or source region). A device isolation region432has a depth greater than that of the deep drift region440to be electrically isolated from another drift region (not illustrated) of a neighboring device.

FIGS.3A and3Bare cross-sectional views of high voltage device structures (nEDMOS) manufactured by the present disclosure.

FIG.3Ais a cross-sectional view of the nEDMOS device300manufactured by split1of the present disclosure. According toFIG.3A, each bottom surface of the P-type well region510and the drift region520formed in the P-type HPW region500is almost flat. This structure may increase the short channel effect (SCE) of the device, making it difficult to shrink down.

In addition, a source region544and a drain region544are formed in the P-type well region510and the drift region520, respectively. Pickup region542is formed in P-type well region510. Thin and thick gate insulating films531and532are formed between the source region544and the drain region544. The gate insulating film comprising thin and thick gate insulating films531and532has a different thickness. The thin gate insulating film531is formed near the source region544, and the thick gate insulating film532is formed near the drain region544. The thin gate insulating film531has an effect of lowering the threshold voltage, thereby increasing the source-drain current. The thick gate insulating film532is designed to withstand a high drain voltage, thereby increasing the breakdown voltage. The gate insulating films (FIGS.3B,582, and583) illustrated inFIG.3B, which are described afterward, also have the same effect. A gate electrode530is formed on the thin and thick gate insulating films531,532. A spacer534is formed on the sidewalls of the gate electrode.

FIG.3Bis a cross-sectional view of an nEDMOS device300manufactured by split2of the present disclosure. As illustrated, the P-type body region560has a different bottom depth. The P-type body region560between the gate electrode580and the device isolation region552has a first depth (d1) shallower than a second depth (d2) of P-type body region560under the gate electrode580. The first depth, d1, is the depth of the shallow PW region56under the gate electrode580. This is because ion implantation is performed using the gate electrode580as a mask. The first depth, d1, is a depth of the shallow PW region561under the gate electrode580. The second depth, d2, is a depth of the P-type body region560outside the gate electrode580. The shallow PW region561has a doping concentration less than a doping concentration of the P-type body region560because the gate electrode partially blocks the ion implantation into the shallow PW region. The PW region comprises the shallow PW region561and the P-type body region560, wherein the shallow PW region561and the P-type body region560are simultaneously formed in one step at the same process condition.

An N-type drift region570also has a different bottom depth. The N-type drift region570between the gate electrode580and the device isolation region552has a third depth (d3) shallower than a fourth depth (d4) of N-type drift region560under the gate electrode580. This is because ion implantation is performed using the gate electrode580as a mask. The third depth, d3, is a depth of the shallow drift region571under the gate electrode580. The fourth depth, d4, is a depth of the deep drift region570outside the gate electrode580. The shallow drift region571has a doping concentration less than a doping concentration of the deep drift region570because the gate electrode partially blocks the ion implantation into the shallow drift region. The drift region comprises the shallow drift region571and the deep drift region570, wherein the shallow drift region571and the deep drift region570are simultaneously formed in one step at the same process condition.

As illustrated inFIG.3b, it is formed thick in the order of d3<d1<d4<d2. A depth of the P-type body region560is formed deeper than a depth of the deep drift region570, which is caused by a difference in ion implantation energy used for the PW region and the drift region. PW ion implantation energy for forming the PW region is greater than DRFIT ion implantation energy for forming the drift region. A channel region is formed. Here, even the shallow PW region561has a depth deeper than a depth of the source region564, the drain region564, or the body pickup region562. The source region564is spaced apart from a high voltage PW region (HPW)550by the shallow PW region561. So the source region564does not contact the high voltage PW region (HPW)550. A threshold voltage of the nEDMOS device300depends on a doping concentration of the shallow PW region561.

As illustrated inFIG.3B, the shallow PW region561and the N-type shallow drift region571are formed under the thin gate insulating film582and the thick gate insulating film583, respectively. The N-type shallow drift region571has a depth (d3) less than a depth (d1) of the shallow PW region561. a PN junction region is formed under the gate insulating films582and583by abutting the N-type shallow drift region571with the shallow PW region561. The N-type shallow drift region571serves to further extend or expand the drift region570to the channel region.

The deep drift region570and the N-type shallow drift region571have depths deeper than a depth of the drain region564, the source region564, or the body pickup region562. The deep drift region570has a depth shallower than a depth of the isolation region552, but the P-type body region560has a depth deeper than a depth of the isolation region552.

As illustrated inFIG.3B, the drain region564is formed spaced apart from the sidewall spacer584, so as to form a high voltage device. The breakdown voltage varies depending on the distance between the drain region564and the gate electrode580. On the other hand, the source region564is aligned with the spacer584formed on sidewalls of the gate electrode580.

FIGS.4(a) and4(b)illustrate device simulation results of the respective device for the HV NMOS device formed by split1and split2of the present disclosure. As described above, a bottom surface of the N-drift region440N and441N by the split2(GPI method) of the present disclosure has a different profile from that of the N-drift region410N by the split1of the present disclosure. Among them, the bottom surfaces under the gate electrode are very different from each other. As illustrated inFIG.4(b), a shallow drift region exists under the gate electrode, and a deep drift region exists outside the gate electrode. The shallow drift region and the deep drift region each have a different slope. There are two gentle curves. This profile of the drift region is caused by the gate-thorough implantation method. In contrast, inFIG.4(a), there is only one deep drift region. When formed as illustrated inFIG.4B, the gate length of the HV device200may be further reduced. This is because a shallow drift region having lower doping concentration than the deep drift region exists under the gate electrode. Punch-through may be improved.

FIGS.5(a) and5(b)illustrate device simulation results of the respective device for the HV PMOS device formed by split1and split2of the present disclosure. The doping profiles of the P-drift region410P by split1and the doping profiles of the P-drift region440P and441P by split2are different. Among them, the doping profiles under the gate electrode are very different from each other. The further description is omitted as it is already described in the description ofFIGS.4(a) and4(b).

FIG.6is an extrapolated Vt (VTE) roll-off graph of the HV NMOS device formed by split1and split2of the present disclosure.FIG.7is an extrapolated Vt (VTE) roll-off graph of the HV PMOS device formed by split1and split2of the present disclosure. The X-axis represents the gate electrode length or channel length. The Y-axis represents the threshold voltage value VTE. As illustrated, in the technique of the present disclosure (marked as SPLIT1), the threshold voltage remarkably decreases as the length of the gate electrode decreases. This phenomenon (short channel effect) occurs because the channel length decreases as the gate electrode length decreases. However, in the present disclosure (marked as Split2), as the gate electrode length or channel length becomes smaller, the threshold voltage (VTE) value decreases more slowly than the technology of the present disclosure (marked as Split1). It can be seen that the short channel effect (SCE) is improved in both HV NMOS and HV PMOS by split2of the present disclosure.

As in the present example, by forming the junction of the gate edge region to a small depth by a gate-through implantation (GTI) method, which is a process of ion implantation using a patterned gate electrode as a mask, it can be seen that the short channel effect (SCE) and punch-through characteristics are improved, compared to a technology of forming drift before forming a gate electrode, thereby enabling shrink down of the device

Next, each unit device structure of the semiconductor device illustrated inFIG.1is described.

FIG.8is a cross-sectional view of the HV EDMOS device manufactured according to an example. As illustrated, HWP region610is formed in the substrate, and two device isolation regions602are formed at a predetermined depth on the surface of the substrate.

The two N-type drift regions620are formed symmetrically in the HPW region610. Each N-type drift region620is formed to have different thicknesses, that is, the first portion under the gate electrode622becomes a shallow drift region622formed with a relatively small thickness, and the second portion between the gate electrode656and the device isolation region602is formed to be thicker. As described above, the first portion of the N-type drift region near the edge of the gate electrode helps to improve the short channel effect characteristic.

As illustrated inFIG.8, one drift region as a whole is divided into two regions620and622, and the side profile of the drift region is changed twice. Inflection points exist in the shallow and deep drift regions.

An N-type source region624and an N-type drain region626are formed in the pair of N-type drift620regions, respectively. The source region624and the drain region626are not aligned with the spacer654and are formed by ion implantation spaced apart to reduce leakage current from gate-source and gate-drain, respectively. The heavily doped source region624and the drain region626are formed in contact with the device isolation region602. Each of the source region624and the drain region626has a depth shallower than a depth of the shallow drift region622. In addition, silicide layers630and658are formed on the heavily doped regions624and626, and the gate electrode656. In addition, the source/drain contact plug642is formed by being connected to the source region624and the drain region626, respectively.

As illustrated inFIG.8, a gate insulating film652, a gate electrode656, and a spacer654are formed on the substrate. The spacer654insulating film is formed on the gate insulating film652as well as sidewalls of the gate electrode656. Silicide layers630and658and a silicide blocking insulation layer660are formed on the gate electrode and on a top surface of the substrate. The silicide blocking insulation layer660serves to prevent silicide formation. In the example, the silicide blocking insulation layer660uses a SiO2 insulating film, but an insulating film such as SiN, SiON, or etc., may be used.

The silicide blocking insulation layer660is formed on both edge portions of the gate electrode656. The silicide layer is formed on a center portion of the gate electrode656. Thus, the heights of both ends of the gate electrode656are formed higher than the center thereof.

As illustrated inFIG.8, a first insulating layer670for borderless contact (BLC) is formed with respect to the entire area of the substrate. The first insulating layer670is also formed on the gate electrode656, silicide layers630and658, the device isolation region602, and the silicide blocking insulation layer660. The first insulating layer670may be formed of silicon nitride film (SiN) or silicon oxynitride film (SiON). Second and third insulating layers680,682are sequentially formed on the first insulating layer670. The second insulating layer680comprises a borophosphosilicate glass (BPSG) or a phosphosilicate glass (PSG) material. The third insulating layer682comprises a silicon oxide formed by Tetraethyl orthosilicate (TEOS) material. A metal wiring layer690connected to the source/drain contact plug642is formed on the third insulating layer682.

FIG.9is a cross-sectional view of a medium voltage MOS (MV MOS) device manufactured according to an example.

FIG.9is almost similar to the cross-sectional view of the device ofFIG.8described above; however, there is a difference in the alignment of an N-type heavily doped source and drain regions with respect to the gate electrode. As illustrated, two device isolation regions602are formed in an HPW region610and the surface of the substrate at a predetermined depth. N-type drift regions620and622are formed symmetrically in the two HPW regions610, respectively. Each of N-type drift regions620and622has a shallow drift region622and a deep drift region620. As such, a short channel effect of a device may be improved by forming the shallow drift region622. A spacer654insulating film is also formed on the gate insulating film652. An N-type source region624and a drain region626are formed in the two N-type drift regions620, respectively, and may be formed to align with the spacer654. Silicide layers630are formed on the source region624and the drain region626. A gate silicide layer658is also formed on the entire surface of the gate electrode656. Thus, inFIG.9, the silicide blocking insulation layer is not required to be formed. In addition, contact plugs642, a first insulating layer670, a second insulating layer680, a third insulating layer682are formed.

FIG.10is a cross-sectional view of a low voltage device manufactured according to an example. As illustrated, an N-type HNW region710is formed on the substrate, and PW regions720and722are formed thereon. In addition, a device isolation region702is formed at a predetermined depth from the substrate surface. The device isolation region702is formed over the HNW region710and the PW regions720and722. One PW region720and722may be divided into a shallow depth PW region722and a deep depth PW region720, which is caused by ion implantation through the gate electrode756. After forming the PW regions, LDD regions730are formed in the PW regions720and722on both sides of the gate electrode756. The spacer insulating film754is also formed on the gate insulating film762. A high concentration source region742and a drain region744are formed in the PW regions720and722. Silicide layers750are formed on the source and drain regions. Gate silicide layer768is formed on the entire surface of the gate electrode756. Contact plugs752connected to the source region742and the drain region744are also formed. A first insulating layer770, a second insulating layer780, a third insulating layer782, and a metal wiring layer790are also formed.

FIGS.8,9, and10are cross-sectional views of the high voltage, medium voltage, and low voltage devices, respectively. Although the gate length is illustrated similarly, the gate length is actually smaller in order of high voltage, medium voltage, and low voltage devices.

FIG.11is a cross-sectional view of the nEDMOS device300manufactured according to an example. The pEDMOS device differs only in the conductivity type, and the structure thereof is the same, and thus details are omitted.

As illustrated inFIG.11, a P-type HPW region810and a device isolation region802are formed on a substrate. In addition, a P-type deep body region820and an N drift region830are formed in the HPW region810. As illustrated, the P-type deep body region820and the N drift region830are configured with a deep region and a shallow region. That is because the P-type deep body region820and the N drift region830are formed by ion implantation through the gate electrode856.

As illustrated inFIG.11, a deep body region820is formed deeper than the device isolation region802. The deep body region820and the shallow body region821form one P-type body region. In addition, a bottom profile of the PW region has an inflection point between the deep body region820and the shallow body region821.

A deep drift region830has a depth shallower than a depth of the device isolation region802. A shallow drift region831has a depth shallower than a depth of the shallow body region821. An inflection point also exists between the deep drift region830and the shallow drift region831.

The P+ body contact region822and the N+ source region824, which are heavily doped regions, are formed in the P-type deep body region820. The N+ drain region826is formed in the N-type deep drift region830. The N+ source region824is aligned with the spacer854. The silicide layers835are formed on the P+ body contact region822, the N+ source region824, and the N+ drain region826, respectively. The total length of the silicide layer835is less than a maximum horizontal length of the N+ source or drain regions824and826. This is to reduce the substrate leakage current. A leakage current occurs between the substrate and the silicide layer, and when the silicide layer835extends beyond the source region or the drain region toward the direction of the gate electrode, the leakage current tends to increase by that amount. In order to reduce this, the silicide layer is formed so as not to cover the entire source or drain regions. That is, the silicide layer is formed only in a portion of the source or drain region. A silicide layer is also formed on the gate electrode.

Gate insulating films851and852are formed on the substrate. The spacer854is formed on the gate insulating films851and852as well as on sidewalls of the gate electrode. A silicide blocking insulation layer is formed on the entire surface of the substrate. The silicide blocking insulation layer860serves to prevent silicide formation. Thus, if the silicide blocking insulation layer860is not formed, silicide layers835and858are formed. In the example, the silicide blocking insulation layer860comprises one or stacked materials selected from a SiO2, SiN, SiON, etc. A first insulating layer870for borderless contact is formed on the silicide layers835and858, the silicide blocking insulation layer860, and the device isolation region802. The first insulating layer870may be formed of silicon nitride film (SiN) or silicon oxynitride film (SiON). A second insulating layer880, a third insulating layer882, and a metal wiring layer890are also formed.

FIG.12is a device plan view of the HV device200according to an example of the present disclosure.

(a) ofFIG.12illustrates an active region900for forming an active region, two drift regions910, and a gate electrode920.

The two drift regions910are formed to overlap the active region900and the gate electrode920. The gate electrode920is partially overlapped with the two drift regions910. In order to reduce the unit device size, the vertical size of the gate electrode920does not exceed the size of the drift region910.

A source contact932is formed in the high concentration source region930, and a drain contact942is formed in the high concentration drain region940. Reference numeral950denotes a gate contact950connected to the gate electrode920. The gate contact950is formed outside the active region900.

(b) ofFIG.12is a cross-sectional view taken along line B-B′ of (a) ofFIG.12and illustrates a cross-sectional view of a device formed later through the device plan view, as illustrated in (a) ofFIG.12. The source region930and the drain region940are formed in the active region, and the remaining regions are surrounded by the device isolation region990. Because the drift region980is ion-implanted in a vertical direction deeper than the source and drain regions930and940, the drift region980is formed surrounding the source and drain regions930and940.

The ion implantation is performed in a state where a separate drift forming mask is positioned on the gate electrode in the state where the gate electrode960is patterned. Therefore, the shallow drift region981under the gate electrode is smaller than the depth of the drift region982formed outside the gate electrode. The shallow drift region981has a depth deeper than a depth of either a source region930or a drain region980. The depth of the remaining drift region982is formed deeper than the shallow drift region981.

FIG.13is a cross-sectional view of an LV device, an HV device, and an nEDMOS device300, according to an example.

As illustrated inFIG.13, the LV device100, the HV device200, and the nEDMOS device300are formed on one substrate10. The LV device100is formed in an N-type deep well region, HNW710. The HV device200and the nEDMOS device300are formed in the P-type deep well region, HPW610. The LV device100, the HV device200, and the nEDMOS device300may be regarded as first, second, and third transistors formed on a substrate, respectively. N+ heavily doped region711is formed in the HNW710to allow a ground voltage or other voltage to be applied to the HNW710. P+ heavily doped region811is formed in the HPW610region to allow a ground voltage or other voltage to be applied to the HPW610. An implant region (not illustrated) for preventing channel stop may be formed at a lower portion of the device isolation region602between the LV device100and the HV device.

As illustrated inFIG.13, the first transistor100includes a first P-type well region720formed in a substrate10; a first gate insulating film762formed on the first P-type well region; a first gate electrode756formed on the first gate insulating film762; a first spacer754respectively formed on sidewalls of the first gate electrode756; a first source region742and a first drain region744formed in the first P-type well region720; a well region722of which the first well region is formed under the first gate electrode756and having a first depth; and a first well region720having a second depth deeper than the first depth, and formed outside the first gate electrode756. The second depth is greater than the depth of the device isolation regions602,702, and802.

The second transistor HV200is formed on the substrate10and includes the first and second drift region620formed spaced apart from each other; a second gate insulating film652formed on the first and second drift regions; a second gate electrode656formed on the second gate insulating film; a second spacer654formed on the sidewall of the second gate electrode; and a second source region624and a drain region626respectively formed in the first and second drift regions. Each of the first and second drift regions620includes a shallow drift region622formed under the second gate electrode and having a third depth; and a deep drift region620having a fourth depth deeper than the third depth and formed outside the second gate electrode. The fourth depth is smaller than the depth of the device isolation regions602,702, and802. The depth of the shallow drift region622may be greater than that of the second source624and the drain region626. The second transistor has a symmetrical structure. That is, the source and drain regions may be interchangeable. The length of the gate electrode656of the HV device200is greater than the length of the gate electrode756of the LV device100because it operates at a high voltage. However, the thickness of the gate electrode656of the HV device200is formed to be similar to the thickness of the gate electrode756of the LV device100. The thickness of the gate insulating film652of the HV device200is greater than that of the gate insulating film762of the LV device100because it operates at a high voltage.

The third transistor nEDMOS300is formed on the substrate10, and includes a P-type deep body region820and N-type third drift regions830and831having different conductivity types; third and fourth gate insulating films301aand301bhaving different thicknesses from each other on the body region and the third drift region; a third gate electrode856on the third and fourth gate insulating films. The depth of the body region820or the P-type deep body region820is greater than that of the device isolation regions602,702, and802, and the depth of the third drift regions831,830is less than the depth of the device isolation region. And the third transistor nEDMOS300further includes third source and drain regions824and826respectively formed in the body region and the third drift region, a body contact region822formed in the body region820. An inflection point exists between the shallow drift region831and the deep drift region830described above.

More particularly, the nEDMOS device300ofFIG.13includes a substrate10including device isolation regions602,802, a first active region and a second active region, gate insulating films851and852including third and fourth gate insulating films851and852having different thicknesses on the substrate; a gate electrode856formed on the gate insulating films851and852; a first conductivity type body region820or P-type deep body region820formed in the first active region and under the gate electrode; drift regions830and831of a second conductivity type in the second active region and under the gate electrode; a spacer854formed on the sidewall of the gate electrode; a second conductivity type source region824formed in the first conductivity type body region; a drain region826of the second conductivity type formed in the drift region of the second conductivity type; a first conductivity type body contact region822formed in the first conductivity type body region; a non-sal region860formed in the first and second active regions; silicide layer835and858formed on the source, drain and body regions and the gate electrode. The depth of the first conductivity type body region820is greater than the depth of the device isolation region, and the depth of the second conductivity type drift region830is smaller than the depth of the device isolation regions602,702, and802.

The thickness of the gate electrode856of the nEDMOS device300is formed to be similar to the thickness of the gate electrode656of the HV device200and the gate electrode756of the LV device100. The thickness of the thin gate insulating film851of the nEDMOS device300is identical to the thickness of the gate insulating film762of the LV device100. The thickness of the thick gate insulating film852of the nEDMOS device300is the same as the thickness of the gate insulating film652of the HV device200.

In the nEDMOS device300, the first conductivity type (P-type) shallow body region821and the second conductivity type shallow drift region831are in contact with each other at a lower portion of the gate insulating film to form a PN junction region. The first conductivity type body region includes a shallow well region821formed under the first gate insulating film and having a first depth; and the first conductivity type body region further comprises a P-type deep body region820formed under the source region and having a second depth deeper than the first depth. The second conductivity type drift region includes a shallow drift region831formed under the second gate insulating film and having a third depth; and the second conductivity type drift region further includes a deep drift region830formed under the drain region and having a fourth depth deeper than the third depth. That is, the drift region of the second conductivity type includes a shallow drift region831and a deep drift region830, and an inflection point exists between the shallow drift region and the deep drift region. In the semiconductor device of the present disclosure, the length of the silicide layer835formed in the drain region826is formed smaller than the length of the drain region826.

And silicide blocking insulation layers660and860are formed on the substrate. All are deposited at the same thickness under the same condition at the same time with one film. First insulating layers670,770, and870are simultaneously formed on the silicide blocking insulation layers660and860with the same thickness under the same conditions. And interlayer insulating films880and882are formed. A plurality of contact plugs642,752, and840are formed, which are connected to the source, drain, body contact, and gate electrode. Metal wiring patterns690,790and890connected to the respective contact plug are formed.

According to the semiconductor device manufacturing method of the present disclosure, as described above, the process is improved to form a gate pattern on the semiconductor substrate first and then perform a drift process. This improved process allows the portion under the gate edge to be formed at a smaller depth than the drift region of the source and drain regions.

As such, the shallow junction of the gate edge portion may improve the short channel effect characteristic, thereby enabling shrink down of the semiconductor device.

As a result, it is possible to reduce the size of the high-voltage semiconductor device occupying most of the display drive IC such that it is possible to manufacture a smaller IC chip, which is expected to have a competitive advantage.

While this disclosure includes specific examples, it will be apparent after an understanding of the disclosure of this application that various changes in form and details may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in a descriptive sense only, and not for purposes of limitation. Descriptions of features or aspects in each example are to be considered as being applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and/or if components in a described system, architecture, device, or circuit are combined in a different manner, and/or replaced or supplemented by other components or their equivalents. Therefore, the scope of the disclosure is defined not by the detailed description, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents are to be construed as being included in the disclosure.