Patent ID: 12238361

DETAILED DESCRIPTION

FIG.2is a schematic block diagram of a wideband receiver system200according to an embodiment of the present invention. Wideband receiver system200includes a radio front end210and a digital front end230. Radio front end210may be a single very wide-band tuner receiver that captures the desired swath of channels located in non-contiguous portions of the spectrum having a frequency bandwidth BW1120. In this example, the number of available channels in BW1120is assumed to be 10 with each channel occupying an 8 MHz bandwidth for a total of 80 MHz. Radio front end210is shown as including a low noise amplifier LNA202having an input terminal configured to receive an RF input signal102. In the example shown, RF signal102includes four desired RF channels having the respective carrier frequency frf1frf2, frf3, and frf4that are located in non-contiguous portions of the wide frequency spectrum BW1. It is understood, however, that spectrum BW1120may have any other number of desired frequencies that are not contiguous. LNA202has a very low noise figure and very high linearity and a wide tuning range (i.e., very high IIP2 and IIP3 intercept points) to maximize a signal-to-noise-and distortion ratio (SNDR) at the amplifier output. LNA202may have a programmable gain to amplify RF signal102to adequate voltage levels for mixers M1211and M2221.

Mixers M1211and M2221may be conventional mixers formed using, for example, differential Gilbert cells. Each of the mixers211and221multiplies (mixes) an amplified RF signal203with a respective first oscillator frequency signal205and a second oscillator frequency signal207to generate an in-phase signal212and a quadrature signal222that have a phase shift of 90° degree between them. Mixers211and221are identical so that the amplitude of the in-phase signal212and quadrature signal222are the same. The first and second oscillator frequencies205and207are identical and have a 90° degree phase shift generated through a 90° degree phase shifter P1206. Synthesizer S1may be a single local oscillator operable to generate the oscillator frequency205for converting the receive RF signal102to a zero-IF or low-IF band. Synthesizer S1can be a coarse (large step) phase locked loop. Synthesizer S1can also be programmable to cover the wideband frequency of the analog and digital terrestrial broadcast and/or the cable television system. The RF signal102may have relatively uniform signal strength in a cable network. However, its signal strength may extend in several orders of magnitude in a terrestrial broadcast system, thus, LNA202and/or mixers M1211, M2221are required to have a relatively high dynamic range to handle the large variations in the signal strength.

In-phase signal212and quadrature signal222are further amplified and filtered by respective amplifiers V1213, V2223and filters F1215, F2225to generate a filtered in-phase signal216and a filtered quadrature signal226. Filters F1215and F2225may be passive or active low-pass filters to filter out any unwanted frequency components of the signals214and224before digitizing them for further processing in digital front end230. It is understood that the in-phase path216and the quadrature path226must have the same amplitude spectrum and maintain a fixed phase relationship, i.e., amplifiers V1213, V2223and filters F1215, F2225must be substantially identical. Because the two paths216and226are in quadrature, the spectral components from both positive and negative frequencies can be overlaid so that the bandwidth (cutoff frequency) of filters F1215and F2225can be one half of the BW1bandwidth120.

Analog-to-digital converters ADC1218and ADC2228are high-speed (i.e., high sampling rate) converters to maximize the dynamic range. In an exemplary application, radio front end210operates as a nominal zero-IF down-mixer so that signals216and226have a nominal bandwidth290equal to one half of the RF signal bandwidth BW1thanks to the complex down-mixer architecture. In other embodiment, radio front end210operates as a low-IF down-mixer so that the nominal bandwidth290of signals216and226is greater than one half of the bandwidth BW1. In practice, the sampling rate of ADC1218and ADC2228is chosen to be higher than the Nyquist sampling requirement, i.e., the filtered analog quadrature signals216and226may be over-sampled in order to reduce or avoid aliasing of undesired signals into the digitized I and Q signals.

ADC1218generates a digital signal I232that is a digital representation of the analog filtered signal216; ADC2228generates a digital signal Q242that is a digital representation of the analog filtered signal226. Digital signals I232and Q242are then applied to a bank of N complex mixers250, wherein N is an integer value corresponding to the number of desired RF channels located in the non-contiguous portions of the frequency spectrum BW1. It is understood that the number N can be any integer value. In one embodiment, N can be equal to the number of all available channels that exist in the licensed frequency spectrum to provide system flexibility. In other embodiments, N can be equal to the number of all receivable channels within a geographic area. In yet another embodiment, N can be an integer value less than the number of receivable channels with the geographic area to reduce system costs. In the exemplary embodiment shown inFIG.2, the number of desired channels is 4. That is, each of the 4 complex mixers250mixes in-phase and quadrature signals232and242with an associated frequency to generate a corresponding baseband, which is then individually filtered, decimated and provided to an associated demodulator.

Each of the N complex mixers250receives the digital signals I232and Q242from ADCs218and228to extract a different one of the desired channels and frequency-shifts the extracted signals to the baseband frequency. Each of the frequency shifted desired channels252is filtered by an associated filter module (identified as260ato260n). In an embodiment, each of the filtered signals260ato260nmay be sent directly to an associated demodulator (identified as270ato270n) for extracting the original information transmitted in the associated desired channel. In another embodiment, each of the filtered signals262ato262nis further decimated before providing to a demodulator. A path of digital front end230is described in more detail below.

FIG.3is a simplified circuit diagram of one of the signal paths272ato272nof digital front end230shown inFIG.2according to an embodiment of the present invention. In an embodiment, digital signal I232may be further filtered by a filter311to obtain a filtered signal312. Similarly, digital signal Q242may be further filtered by a filter321to obtain a filtered signal322. Thus, digital signals312and322only contain low-frequency components with undesired high-frequency components being eliminated by respective filters311and321. It is noted that filtered signals312and322are interposed between the respective ADCs218,228and the bank of N complex mixers250.

Mixer300, which represents one of the N complex mixers250, includes four multipliers313,315,323, and325. Multipliers313and315multiply the filtered signal312with respective cos(ωcit) and sin(ωcit) signals and generate respective products314and316. Similarly, multipliers323and325multiply the filtered Q signal322with respective cos(ωcit) and sin(ωcit) signals and generate respective products324and326. An adder317sums the products314and326to generate a frequency-shifted signal I318. An adder327sums the products324and316to generate a frequency-shifted signal Q328. Basically, complex mixer300causes a frequency shift of the filtered components312and322to respective baseband signals318and328in the digital domain according to the operation:
Y(t)=X(t)*e−jωct(1)
or taken the Fourier transform, we obtain:
Y(ω)=X(ω−ωc)  (2)

Multipliers313,315,323, and325are identical digital multipliers. In an embodiment, a numerically controlled oscillator with quadrature output generates the cos(ωcit) and sin(ωcit) signals. Numerically controlled oscillators (NCO) can be implemented using a phase accumulator and a look-up table. NCOs are known to those of skill in the art and will not be described herein. The frequency ωciis so chosen that each one of the desired channels embedded in the digital signals I232and Q242will be downshifted to the baseband. In the given example shown inFIG.2, the bank of N complex mixers will have four complex mixers, each one of the N (i.e., four) complex mixers is coupled to an individual NCO having a distinct frequency ωciso that when mixing the filtered digital I and Q signals312and322with that frequency, each one of the complex mixers will generate the signals I (318) and Q (328) of a corresponding one of the desired channels at the baseband.

In an embodiment, baseband signals318and328are further individually filtered by respective filters330and340that are identified as one of the filters260a-ninFIG.2. Filters330and340may be band-pass or low-pass filters having a narrow bandwidth equal to the bandwidth of a desired channel. In certain embodiments, filters330and340can be analog passive or active low-pass or complex band-pass filters such as polyphase filters. In another embodiment, filters330and340can be digital low-pass filters, such as finite impulse response (FIR) filters to eliminate high frequency components that may be aliased back to the baseband signals Ii (332) and Qi (342) when decimated by subsequent decimator350.

The reduced sampling rate of the N desired baseband channels will be sent as a serial or parallel digital data stream to a demodulator using a serial or parallel data interface according to commonly known methods, as shown inFIG.2. This approach provides several advantages over conventional tuner architectures. First, it eliminates the need of expensive data conversion, filtering and channel selection on the demodulator side. Second, it removes undesired channels from the signal path at an early stage, thus relieves the large dynamic range requirement in the demodulator.

FIG.4shows a simplified schematic block diagram of a wideband receiver system400according to another embodiment of the present invention. Wideband receiver system400includes a radio front end410, a digital front end430, a tiled up-conversion module450, and a summing digital-to-analog converter module DAC470. Radio front end410includes a low noise amplifier LNA1that receives an RF input signal102and provides an amplified RF signal403to mixers M1411and M2421. Mixer M1411is coupled to an oscillator frequency405of a synthesizer S1whereas mixer M2421is coupled with the oscillator frequency405via a phase shifter P1406that generates a 90° degree phase-shift to the oscillator frequency405. Mixers M1411and M2421generate respective in-phase signal412and quadrature signal422that are further amplified by respective amplifiers V1413and V2423. The amplified in-phase and quadrature signals414,424are then filtered by filters F1415and F2425to eliminate undesired frequency components that would be aliased back to the in-phase and quadrature signals when digitally sampled by subsequent analog-to-digital converters ADC1418and ADC2428. Digital signals I422and Q442at the input of digital front end430are digital representations of the filtered analog in-phase and quadrature signals416,426before the ADCs. Digital front end430include a bank of N complex mixers432comprising432ato432nidentical mixers, where N is an integer value corresponding to the number of the desired channels located in non-contiguous portions of the frequency spectrum. Each of the N complex mixers432ato432nfrequency down-converts signals I432and Q442to an associated baseband. Each of the frequency down-converted I and Q signals are coupled to respective low-pass, band-pass, or decimating filters434. In this regard, the radio front end410and the digital front end430are similar to respective radio front end210and digital front end230ofFIG.2that have been described in detail above.

In an alternative embodiment of the present invention, the N filtered and decimated channels438ato438n(where indices a to n correspond to the associated number of desired channels) are not provided to a demodulator for demodulation. Instead, the N filtered and decimated channels438ato438nare further frequency up-converted to an intermediate frequency (IF) spectrum. In order to achieve that, the N filtered and decimated channels are coupled to a tiled up-conversion module450that includes a bank of N complex up-mixers, where N is an integer value correspond to the number of desired received channels. The N complex up-mixers include identical digital mixers452ato452nthat will be described further in detail below with reference toFIG.5. The N up-shifted channels are then filtered by a subsequent bank of channel filters454that, in an embodiment, comprises N individual finite impulse response (FIR) filters. The N filtered channels are then digitally combined and converted to the analog domain by a summing digital-to-analog converter module DAC470. The N up-shifted channels are adjacent to each other and form a contiguous or substantially-contiguous set of channels475in the IF spectrum centered around fifas illustrated inFIG.4. In an embodiment, the spectra of the mixed products are spaced in such a way so as to avoid overlap with known frequency bands containing potential or actual interferers. In another embodiment, the spectra of the mixed products are spaced in such a way so as to avoid overlap with frequency bands that might introduce interference to other systems. In general, because the bandwidth BW2is substantially lower than BW1, the IF frequency fifcan be set proportionally lower, e.g., typically about 16 MHz to accommodate the spectrum of BW2of up to 32 MHz (corresponding to the total bandwidth of the four desired channels, each having a bandwidth of 8 MHz in this example).

The up-conversion approach ofFIG.4provides several advantages over conventional tuner architectures. First, it allows the demodulator to operate the data converter at a lower data rate and with lower resolution (fewer bits) due to the fact that the contiguous channels have a narrower bandwidth. Second, the up-conversion approach provides full compatibility with existing demodulators that require an analog IF signal. Third, it removes undesired channels from the signal path at an early stage, thus relieves the requirement of a high dynamic range requirement of the demodulator's analog-to-digital converter and the demodulator itself.

FIG.5shows a simplified exemplary circuit diagram of a complex up-mixer500according to an embodiment of the present invention. Up-mixer500is one of the N complex up-mixers452ato452nin tiled up-conversion module450shown inFIG.4. Up-mixer500includes filter510and520configured to eliminate unwanted frequency components present in respective input signals I501and Q502. Filtered signals512and522are provided to up-mixers UMI515and UMQ525that multiply the filtered signals512and522with respective cos(ωut) and sin(ωut). The products516and526are summed in an adder530to generate an IF signal532according to the following equation:
IF(t)=I(t)*cos(ωut)+Q(t)*sin(ωut)  (3)

Up-mixers UMI515and UMQ525are identical digital multipliers that multiply the respective filtered signal512and522with a cosine function505and a sine function506that can be generated from a NCO using a digital phase accumulator and a look-up table.

As described above, TV channels are grouped into multiple frequency bands in North America. For example, channels 2 through 6 are grouped in VHF-low band (aka band I in Europe), channels 7 through 13 in VHF-high band (band III), and channels 14 through 69 in UHF band (bands IV and V). In order to receive such a wide frequency spectrum, the low noise amplifier and mixer must have very low noise, wide tuning range and high linearity as described above in the wideband receiver systems200and400. However, a wideband receiver having a single tuner with high sensitivity may have a high power consumption. For certain applications, it may be advantageous to use multiple tuners that are optimized for a given frequency band, such as a dedicated tuner for the low VHF band, another dedicated tuner for the high VHF band and the UHF band, and yet other dedicated tuners for receiving the digital video broadcasting (DVB) via satellite (DVB-S), via cable (DVB-C), or terrestrial digital video broadcasting (DVB-T). The multi-tuner approach may also be advantageously applied to cable networks that carry TV programs on an 88 MHz to 860 MHz according to the Data Over Cable Service Interface Specification (DOCSIS) protocol.

FIG.6shows a simplified schematic block diagram of a wideband multi-tuner receiver system600according to an embodiment of the present invention. In an embodiment, multi-tuner system600includes low noise amplifier A1602for receiving an RF input signal601. Amplifier A1602is coupled to at least a tuner1610and a tuner2720. In another embodiment, multi-tuner system600may not include amplifier602so that RF input signal601can be received directly at each tuner610and720.

Tuner1610includes an amplifying filter AF1613that filters and amplifies a first portion BWtuner1604of a broad frequency spectrum608that contains a first plurality of RF channels606including desired channels607having respective channel frequencies frf1and frf2. The first portion of the broad frequency spectrum BWtuner1604is then frequency down-converted to a low-IF or zero-IF in-phase signal Il612and a quadrature signal Q1622through respective mixer M1611and M2621. Signals Il612and Q1622are further amplified and low-pass filtered before applying to respective analog-to-digital converters ADC1618and ADC2628that convert analog signals Ia1616and Qa1626to respective digital in-phase signal Id1631and digital quadrature signal Qd1641. Because tuner1610only covers a portion BWtuner1604of the entire frequency spectrum608having fewer channels, the ADC1618and ADC2628can be slower-speed analog-to-digital converters with a large number of bits, i.e., large dynamic range.

Digital signals Id1631and Qd1641are then provided to a digital front end DFE630that includes a first bank of N complex mixers632and channel and decimating filters634. The first bank of N complex filters632has N identical complex mixers, where N is an integer value equal to the number of desired channels located in the first portion BWtuner1604of the broad frequency spectrum608. In an embodiment, each one of the first bank of N complex mixers includes four digital mixers that multiply digital stream Id1631and Qd1641with respective digitized cosine function and sine function to generate the sum and difference frequency components, as shown inFIG.3. The digitized cosine and sine frequency, i.e., the mixer frequency is so chosen so that when mixing signals Id1631and Qd1641will move them to a baseband or a low-IF band. In an embodiment, channel and decimating filters have similar structures as filters330and340and demodulator350as shown inFIG.3. That is, channel and decimating filters include digital low-pass filters330and340that eliminates unwanted high frequency components of the baseband signals I and Q prior to applying them to a decimator350(FIG.3) that reduces the sample frequency without any loss of information since Id1631and Qd1641are sampled at a much higher frequency by the respective ADC1618and ADC2628.

The decimated desired channels are then provided to an up-converter module650that includes a bank of N up-mixers. The bank of N up-mixers includes N identical up-mixers whose structure is shown inFIG.5. In an embodiment, N is an integer value equal to the number of desired channels present in BWtuner1604. Each one of the up-mixer frequency-shifts the baseband signals I and Q of each one of the desired channels to an appropriate portion of the intermediate frequency band according to Equation (3). In other words, the bank of N up-mixers is “frequency multiplexing” the desired channels onto a first portion682of an IF band686.

Similarly, tuner2720includes an amplifying filter AF2713that is configured to receive a second portion BWtuner2704of the broad frequency spectrum608. The second portion704contains a second plurality of RF channels706including a second number of desired channels. In the exemplary illustration ofFIG.6, the second portion704has a frequency bandwidth of BWtuner2that contains desired channels707having respective channel frequencies frf3and frf4. Tuner2720includes elements such as mixers M3711, M4721, amplifiers V3714, V4724, filters F3715, F4725and analog-to-digital converters ADC3731and ADC4741that are substantially the same as the like-named elements of the signal path of tuner1610. Thus, redundant description is omitted herein.

Digital in-phase signal Id2731and digital quadrature signal Qd2741are then provided to digital front end740. Digital front end740includes a bank of L complex filters, where L is an integer value equal to the number of desired channels in the second portion BWtuner2704of the broad frequency spectrum608. Each one of the bank of L complex filters is a digital complex mixer configured to transform the signals Id2731and Qd2741to baseband signals that are further filtered by individual digital low-pass filters such as FIR filters before decimated by a subsequent decimator. The elements of digital front end740are substantially similar to those described in digital front end630. Thus, redundant description is omitted herein.

The decimated baseband I and Q channels are further provided to a subsequent up-conversion module760that performs a function substantially similar to that of the up-conversion module650already described above. The outputs of up-conversion module650and760can be tiled to generate a contiguous set of IF frequencies682,684centered at fif686. In an embodiment, the outputs of up-conversion module650and760are digitally summed and converted to an analog signal by summing DAC670. In another embodiment, the up-conversion modules650and760and the digital summing function672can be performed using an inverse discrete Fourier transform or an inverse Fast Fourier transform operation.

The multi-tuner architecture provides the flexibility that multiple commercially available tuners can be used without the need of designing a wideband tuner. For example, a tuner designed for a terrestrial broadcast digital TV can be used together with a tuner dedicated to receiving a cable signal and/or a tuner for receiving a satellite broadcast signal. The multi-tuner receiver system provides an additional advantage that other tuners can be added quickly to the system to accommodate any future applications. Additionally, the multi-tuner architecture allows the use of slower speed (i.e., lower cost) analog-to-digital converters with a larger number of bits for achieving large dynamic range.

FIG.7shows a block diagram of an exemplary digital front end of the invention in more detail. In an embodiment, in-phase signal Id2731and quadrature signal Qd2741at the output of respective ADC converters718and728are provided to each of the L complex mixers732comprising mixers732A to732L. A more detailed description of each of L complex mixers is shown inFIG.3. Mixer732A multiplies Id2731and Qd2741with a cosine signal and a sine signal that are generated from an NCO1and produces an I-732A signal and a Q-732A signal that are further individually filtered by an FIR filter before decimating. The bank of L complex mixers corresponds to the block732inFIG.6; and the set of FIR filters and decimator corresponds to the block734inFIG.6. Each decimated pair of I-732i/M in the baseband, where the index “i” is from A to L, is further provided to a subsequent up-mixer for frequency-shifting to an intermediate frequency as shown inFIG.8.

FIG.8shows an exemplary embodiment of a bank of L complex up-mixers according to the present invention. Each decimated pair of complex signals I-732i/M and Q-732i/M is provided to an associated complex up-mixer, whose frequency is so chosen that when mixing with the pair of complex signals I-732i/M and Q-732i/M will generate an associated channel at a predetermined sub-portion of the intermediate frequency band686(FIG.6). A more detailed schematic block of one of the L up-mixers is described above together withFIG.5.

FIG.9is a simplified block diagram of a wideband multi-tuner receiver system900according to an embodiment of the present invention. In an embodiment, system900includes a crossbar switch910having at least an input terminal912configured to receive signals from an analog-to-digital converter (ADC)912and an input terminal922configured to receive signals from an ADC922. Crossbar switch910also includes an output terminal924that is coupled to a digital front end930. In an embodiment, input terminals912and922of crossbar switch910have P inputs, where P is an integer value that is equal to the total number of desired channels received by tuner1610and tuner2720. Output terminal924of crossbar switch910have Q outputs, where Q is an integer value that is equal to the total number of desired channels received by tuner1610and tuner2720.

In an embodiment, digital front end930may include a bank of R complex mixers that frequency shifts the received channels to a baseband. Digital front end930may combine digital front end630and740shown inFIG.6. Similarly, a tiled up-conversion module950may include up-converter modules650and760ofFIG.6.

System900further includes a summing DAC that operates similarly as summing DAC470and670that have been described in detail in relation with respectiveFIG.4andFIG.6above. Thus, redundant description is omitted herein.

FIG.10is a simplified block diagram of a wideband multi-tuner receiver system1000according to another embodiment of the present invention. System1000includes at least tuner1610coupled with digital front end630through an analog-to-digital converter620and tuner2720coupled with digital front end740through an analog-to-digital converter730. System1000further includes a crossbar switch1010that is interposed between digital front ends630,740and up-conversion modules650,760. Crossbar switch1010includes an input terminal1012having S inputs coupled with DFE630and an input terminal1022having T inputs coupled with DFE740. In an embodiment, S is an integer value equal to the number of desired channels processed in DFE630and T is an integer value equal to the number of desired channels processed in DFE740. Crossbar switch1010further includes an output terminal1024having U outputs coupled with up-converter module650and an output terminal1024having V outputs coupled with up-converter module760. In an embodiment, the total number of the outputs U and V is equal to the sum of the inputs S and T. Thus, crossbar switch1010allows the routing of any channel from either DFE630or DFE740to up-converters650or760. It is understood that system1000is not as flexible as system900because DFE630and DFE740are already pre-assigned to respective tuner1(610) and tuner2(720). However, this pre-assigned arrangement allows a simpler implementation of crossbar switch1010that operates at lower speeds.

While several embodiments in accordance with the present invention have been described, it is to be understood that the above description is intended to be illustrative and not restrictive. Many embodiments will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the appended claims along with their full scope of equivalents.