Patent ID: 12218064

DETAILED DESCRIPTION

Disclosed embodiments include molded silicon-interconnect bridges (MSiBs) that interface between integrated-circuit package substrates and integrated-circuit dice. Passive devices such as decoupling capacitors are embedded in the MSiBs such that power delivery demand changes are faster by the proximate location of the passive devices. In an embodiment, the capacitor is a multi-layer ceramic capacitor. In an embodiment, the capacitor is a silicon capacitor.

Ball-grid array densities are improved for input-output (I/O) density changes where keep-out-zone issues are addressed. Location of the passive devices, closer to the integrated-circuit dice, relieves integrated-circuit package substrate real estate issues to increase interconnect densities.

Power integrity of electrical performance is achieved by reduced package inductance looping. Decoupling capacitors are directly coupled to power rails (Vcc) and to ground (Vss), which lowers power delivery network impedance (ZPDN) and jitter behaviors. Location of the MSiBs on a die side of an integrated-circuit package substrate, provides close CTE mismatch tolerances.

The molded silicon-interconnect bridge embodiments use the term “silicon” as a genus for semiconductive material such as silicon or III-V semiconductive material, with useful doping variations according to several embodiments. In an embodiment, the molded silicon-interconnect bridge embodiments use the term “silicon” as a genus for inorganic glass materials with useful doping variations to closely match coefficients of thermal expansions of integrated-circuit dice that use the MSiB embodiments, according to several embodiments.

FIG.1Ais a cross-section elevation of an integrated-circuit package apparatus100with a molded silicon interposer bridge according to an embodiment. A silicon interconnect bridge in a molding-mass frame110includes a die side111and a package side109. A silicon interconnect bridge112is in a molding-mass frame114and at least part of the silicon interconnect bridge112and the molding-mass frame114share the die side111. In an embodiment, the assembly may be referred to as a molded silicon-interconnect bridge (MSiB)110.

A passive device116is in the molding-mass frame114and the silicon interconnect bridge112and the passive device116, occupy at least some of the same vertical space encompassed by the molding-mass frame114. A redistribution layer (RDL)118is on the die side111and the redistribution layer118is coupled to the passive device116and to a through-silicon via120in the silicon interconnect bridge112. The through-silicon via120communicates to the package side109.

In an embodiment, the passive device116is both coupled to the die side111and to the package side109. At the package side109, the passive device116is coupled by an electrical interconnect122to an electrical bump in an array, one electrical bump of which is indicated by reference number124.

In an embodiment, the passive device116is a first passive device116and a subsequent passive device126is in the molding-mass frame114, such that the two passive devices116and126are on opposite sides of the silicon interconnect bridge112. As illustrated in an embodiment, the passive devices116and126are decoupling capacitors.

In an embodiment, a first integrated-circuit die10is on the redistribution layer118and a subsequent integrated-circuit die20is also on the redistribution layer118, where the two IC dice10and20are side-by-side.

Interconnection between the two IC dice10and20is through an inter-die trace128in the RDL118. In an embodiment, interconnection between the two IC dice10and20is by coupling through the through-silicon via120. In an embodiment, coupling between the two IC dice10and20is through an inter-die trace128in the RDL118. In an embodiment, interconnection between the two IC dice10and20is both by an inter-die trace128in the RDL118and by the TSV120.

An integrated-circuit (IC) package substrate130includes a bridge side131and a land side129. In an embodiment, the IC package substrate130includes interconnections on either side of and passing through a package core132. A bridge-side redistribution layer (RDL)134and a land-side RDL136, as well as through-core interconnects138provide electrical communication between the bridge side131and the land side129according to an embodiment. Within the IC package substrate130is a ground (Vss) plane140in the dielectric material of the IC package substrate130, as well as a power (Vcc) plane142in the dielectric material.

In an embodiment, the land side129faces a board144such as a motherboard in a computing system, and an electrical bump array146is seen being brought toward the board144. In an embodiment, the board144has an external shell148that provides at least one of physical and electrical insulative protection for components on the board144. For example, the external shell148may be part of a hand-held computing system such as a communication device. In an embodiment, the external shell148is part of the exterior of a mobile computing platform such as a drone.

FIG.1Bis a top plan of portions of the integrated-circuit package apparatus101depicted inFIG.1Aaccording to an embodiment. The integrated-circuit package apparatus102shows the first and subsequent IC dice10and20on the RDL118. The passive devices116and126are seen along a section line A-A′, and the passive devices116and126are depicted in ghosted lines below the RDL118. Further below the RDL118, six columns of the electrical bump124(in ghosted lines) are also depicted in an array on the bridge side131of the IC package substrate130. Two columns each of bumps124are below the passive devices116and126(seeFIG.1A) and they are not depicted inFIG.1B.

Further in ghosted lines, the material of the molding-mass frame114occupies approximately the same perimeter as the RDL118. Consequently, the silicon interconnect bridge112is framed by the material of the molding-mass frame114.

FIG.1Cis a bottom view of the molded silicon-interconnect bridge101depicted inFIG.1Aaccording to an embodiment. The package side109of the mold material that makes up the molding-mass frame114, exhibits the several capacitors116and126, which are depicted in ghosted lines as they may be embedded beyond the package side109of the mold material that makes up the molding-mass frame114. As illustrated inFIG.1A, 10 electrical bumps124are arrayed in columns that include seven rows. These electrical bumps124are on the package side109and are in solid lines as they are not behind the package side109of the MSiB110.

FIG.2Ais a top plan of portions of an integrated-circuit package apparatus201similar to that depicted inFIG.1Baccording to an embodiment. The integrated-circuit package apparatus201shows respective first and subsequent IC dice10and20on an RDL218(depicted as an upper surface218of the RDL218). Passive devices216and226are seen along a section line A-A′, that is a similar placeholder as section line A-A′ seen inFIG.1B, with differences as herein discussed.

Passive devices216,217,226and227are arrayed in two rows or respective opposite sides of the embedded silicon-interconnect bridge212where passive devices217and227are respectively stacked on passive devices216and226within the mold material of the molding-mass frame214and the passive devices216and217, and226and227are depicted in ghosted lines below the RDL218. Further below the RDL218, six columns of the electrical bump224(in ghosted lines) are also depicted in an array on the bridge side231of the IC package substrate230. At least one column each of bumps224are below the passive devices216and226(see similar bump array124inFIG.1A) and they are not depicted inFIG.2A.

By viewing the passive devices216and217in seriatim repetition on the first side of the MSiB212, one observes a first-side third capacitor, which is a capacitor216that contacts a first-side second capacitor217, which in turn contacts a first-side first capacitor; a different occurrence of216. Similarly by viewing the passive devices226and227in seriatim repetition on the subsequent side of the MSiB212, one observes a subsequent-side third capacitor, which is a capacitor226that contacts a subsequent-side second capacitor227, which in turn contacts a subsequent-side first capacitor; a different occurrence of226.

Further in ghosted lines, the material of the molding-mass frame214occupies approximately the same perimeter as the RDL218. Consequently, the silicon interconnect bridge212is framed by the material of the molding-mass frame214.

FIG.2Bis a perspective elevation of stacked passive devices according to an embodiment. Two bottom capacitor216are configured with a top capacitor217, where the darker-shaded electrodes represent power terminal, and the lighter-shaded electrodes represent ground or source terminal. Consequently, a power rail is depicted where respective power terminals of the bottom216and top capacitor217make contact. Similarly, a ground (Vss) rail is depicted where the respective ground terminals of the bottom216and top capacitor217make contact.

FIG.2Cis a cross-section elevation of an array of stacked passive devices in a molding mass material according to several embodiments. In a multi-die embodiment, different potentials are used for various dice, such as a V1for a first die, VNfor a subsequent die, and V3for a third die. In an embodiment, different voltages are used in different parts of a given die. In a non-limiting example embodiment, a stacked array of top217and bottom216capacitors are configured in a molding mass214where a first power rail240is associated with a voltage of 1.0 V, a subsequent power rail242is associated with a voltage of 1.5 V, and a third power rail244is associated with a voltage of 1.8 V. A metal build-up layer246is also configured, such that when assembled as an integral part of, e.g., the MSiB210of the integrated-circuit package apparatus201depicted inFIG.2A, several different voltages may be delivered to composite power rails by use of stacked embedded capacitors. In an embodiment, the metal build-up layer246is part of the redistribution layer218.

In an embodiment, a first power plane241is related to the first power rail240within the metal build-up layer246. In an embodiment, a subsequent power plane243is related to the subsequent power rail242within the metal build-up layer246. In an embodiment, a third power plane245is related to (but not connected in the drawing) the third power rail244within the metal build-up layer246. In an embodiment, a ground plane248, provides a ground voltage (Vss) reference access or current return path to several devices on the lee side of electrical-potential usage.

FIG.3is a top plan of portions of a molded silicon-interconnect bridge310according to several embodiments. The MSiB310includes stacked capacitors316and317, and326and327that are arrayed within molding-material314that makes up a molding-material frame for the MSiB310.

As illustrated and in similar stacking fashion depicted inFIGS.2A,2B and2C, power rails are formed as well as ground rails by contacting appropriate power terminals to power terminals, and ground terminals to ground terminals. Whereas the stacking fashion is in semi-circular, three-capacitor arrangements, the several configurations have different voltages for power rails according to an embodiment. For example in an embodiment, the two power rails (all capacitors316and317) that are seen on the left of the silicon-interconnect bridge312, have a voltage of 1V. The power rail (the capacitors326and327at the upper right-hand corner) has a voltage of 1.5 V. And the power rail (the capacitors326and327at the lower right-hand corner) has a voltage of 1.8 V.

In an embodiment, a different occurrence of top capacitors317′ and327′ are disposed on the bottom capacitors316and326opposite the top capacitors317and327to form a four-capacitor stacked arrangement in a circular configuration. Improved real-estate utilization can be achieved through both semi-circular and circular (or closed loop) stacked capacitor arrangements.

The molded silicon-interconnect bridge310shows the first and subsequent IC dice10and20on an RDL318(where the RDL318has substantially the same perimeter as the molding-material314). The reference number318is showing as an upper surface. The passive devices316and317, and326and327are depicted in ghosted lines below the RDL318. Further below the RDL318, six columns of the electrical bump324(in ghosted lines) are also depicted in an array on the package side309of the MSiB310. At least two columns each of electrical bumps324are below the passive devices316and326and they are not depicted inFIG.3.

Further in ghosted lines, the material of the molding-mass frame314occupies approximately the same perimeter as the RDL318. Consequently, the silicon interconnect bridge312is framed by the material of the molding-mass frame314.

FIG.4is a top plan of portions of a molded silicon-interconnect bridge410according to several embodiments. The MSiB410includes stacked capacitors416and417, and426and427that are arrayed within molding-material414that makes up a molding-material frame for the MSiB410.

As illustrated and in similar stacking fashion depicted inFIGS.2A,2B,2C and3, power rails are formed as well as ground rails by contacting appropriate power terminals to power terminals, and ground terminals to ground terminals. Whereas the stacking fashion is in semi-serpentine, seven-capacitor arrangements, the several configurations have different voltages for power rails according to an embodiment. For example, the four power rails (all capacitors416and417) that are seen on the top part of the drawing of the silicon-interconnect bridge412, have a voltage of 1V. The power rail (the capacitors426and427at the bottom left to an approximate midline480) have a voltage of 1.5 V. And the power rail (the capacitors426and427at the bottom right to the approximate midline480) has a voltage of 1.8 V.

The molded silicon-interconnect bridge410shows the first and subsequent IC dice10and20on an RDL418(where the RDL418is depicted as a top surface, which has substantially the same perimeter as the molding-material414). The passive devices416and417, and426and427are depicted in ghosted lines below the RDL418. Further below the RDL418, 26 columns of the electrical bump424(in ghosted lines) are also depicted in an array on the package side (not pictured) of the MSiB410. More electrical bumps424may be located below the passive devices416and417, and426and427and they are not depicted inFIG.4.

Further in ghosted lines, the material of the molding-mass frame414occupies approximately the same perimeter as the RDL418. Consequently, the silicon interconnect bridge412is framed by the material of the molding-mass frame414.

FIG.5Ais a cross-section elevation of an integrated-circuit package apparatus501with dual molded silicon interposer bridges and an interstitial array of passive devices according to an embodiment. At least two silicon interconnect bridges in a molding-mass frame510includes a die side511and a package side509. At least two silicon interconnect bridges512and512′ are in a molding-mass frame514and at least part of the silicon interconnect bridges512and512′ and the molding-mass frame514share the die side511. In an embodiment, the assembly may be referred to as a molded silicon-interconnect bridge (MSiB)510.

A first passive device516is in the molding-mass frame514and the first silicon interconnect bridge512and the first passive device516, occupy at least some of the same vertical space encompassed by the molding-mass frame514. A subsequent passive device526is in the molding-mass frame514and the subsequent silicon interconnect bridge512′ and the subsequent passive device526, occupy at least some of the same vertical space encompassed by the molding-mass frame514.

In an embodiment, an interstitial passive device576is located within the molding material of the molding-mass frame514, between the first silicon interconnect bridge512and the subsequent silicon interconnect bridge512′. Consequently, a multiple-bridge, molded silicon-interconnect bridge (MBMSiB)510is achieved with an interstitial passive device. The MBMSiB510creates useful decoupling-capacitor locations to support the first IC die10and the subsequent IC die20.

In an embodiment, any of the stacked passive device embodiments are located within the molding-mass frame514. In an embodiment, the C- or circular-stacked capacitors316and317inFIG.3are located at the Z-level of the X-Y location of the first passive device516. In an embodiment, all capacitors516and526are C- or circular-stacked capacitors. In an embodiment, the stacked-capacitor string216and217embodiments inFIG.2A, are located at the Z-level of the X-Y location of the interstitial capacitor576. In an embodiment, the semi-serpentine stacked capacitors416and417inFIG.4are located at the Z-level of the X-Y location of the subsequent passive device526. In an embodiment all capacitors516and526are semi-serpentine stacked capacitors. Similarly, at least three power rails such as a 1 V rail, a 1.5 V rail and a 1.8 V rail may be configured for each the capacitor locations516,576and526.

A redistribution layer518is on the die side511and the redistribution layer518is coupled to the first passive device516and to a first through-silicon via520in the first silicon interconnect bridge512. The first through-silicon via520communicates to the package side509. Similarly, the redistribution layer518is also coupled to the subsequent passive device526and to a subsequent through-silicon via521in the subsequent silicon interconnect bridge512.

In an embodiment, the first passive device516is both coupled to the die side511and to the package side509. Similarly in an embodiment, the subsequent passive device526is both coupled to the die side511and to the package side509. At the package side509, the first passive device516is coupled by an electrical interconnect522to an electrical bump in an array, one electrical bump of which is indicated by reference number524.

In an embodiment, the passive device516is a first passive device516and the subsequent passive device526is in the molding-mass frame514, such that the two passive devices516and526are on opposite sides of the respective first and subsequent silicon interconnect bridges512and512′. As illustrated in an embodiment, the passive devices516and526are decoupling capacitors.

In an embodiment, a first integrated-circuit die10is on the redistribution layer518and a subsequent integrated-circuit die20is also on the redistribution layer518, where the two IC dice10and20are side-by-side.

Interconnection between the two IC dice10and20is through an inter-die trace528in the RDL518. In an embodiment, interconnection between the two IC dice10and20is by coupling through at least one of the first through-silicon via520and the subsequent TSV521. In an embodiment, coupling between the two IC dice10and20is through the inter-die trace528in the RDL518. In an embodiment, interconnection between the two IC dice10and20is both by an inter-die trace528in the RDL518and by at least one of the TSVs520and521.

An integrated-circuit (IC) package substrate530includes a bridge side531and a land side529. In an embodiment, the IC package substrate530includes interconnections on either side of and passing through a package core532. A bridge-side redistribution layer (RDL)534and a land-side RDL536, as well as through-core interconnects538provide electrical communication between the bridge side531and the land side529according to an embodiment. Within the IC package substrate530is a ground (Vss) plane540in the dielectric material of the IC package substrate530, as well as a plurality of power (Vcc) planes542in the dielectric material.

In an embodiment, the land side529faces a hoard544such as a motherboard in a computing system, and an electrical bump array546is seen being brought toward the board544. In an embodiment, the board544has an external shell548that provides at least one of physical and electrical insulative protection for components on the board544. For example, the external shell548may be part of a hand-held computing system such as a communication device. In an embodiment, the external shell548is part of the exterior of a mobile computing platform such as a drone.

FIG.5Bis a top plan of portions of the integrated-circuit package apparatus501depicted inFIG.5Aincluding interstitial passive devices according to an embodiment. The integrated-circuit package apparatus502shows the first and subsequent IC dice10and20on the RDL518. The passive devices516,576and526are seen along a section line A-A′, and the passive devices516,576,577and526are depicted in ghosted lines below the RDL518. Further below the RDL518, five columns of the electrical bumps524(in ghosted lines) are also depicted in an array on the bridge side531of the IC package substrate530. One column of bumps524is below the interstitial passive device576(seeFIG.5Bbelow). Two columns each of bumps524are below the passive devices516and526(seeFIG.5A) and they are not depicted inFIG.5B.

Further in ghosted lines, the material of the molding-mass frame514occupies approximately the same perimeter as the RDL518and it houses the several passive devices516,576,577and526. Consequently, the respective first and subsequent silicon interconnect bridge at512and512′ are framed by the material of the molding-mass frame514.

FIG.5Cis a bottom view of the molded silicon-bridge interconnect depicted inFIG.5Aaccording to an embodiment. The package side509of the mold material that makes up the molding-mass frame514, exhibits the several capacitors524,576,577and526, which are depicted in ghosted lines as they may be embedded beyond the package side509of the mold material that makes up the molding-mass frame514. As illustrated inFIG.5A, 10 electrical bumps524are arrayed in columns that include seven rows. These electrical bumps524are on the package side509and are in solid lines as they are not behind the package side509of the MMMSiB510.

FIGS.6A through6Frepresent fabrication of molded silicon-bridge interconnects for assembly to at least two IC dice and to a package substrate according to several embodiments. Although only two IC die, e.g.10and20are shown, four dice in a chipset may also be seated above the die sides on the RDLs, e.g.,118,218,318,418and518. For example a chipset of a processor die10and a graphics die20, is complement with a third die such as a memory die that has memory-controller hub or a platform-controller hub, and a fourth die such as a baseband processor. These four or more IC dice may be assembled 2.5-D style upon a given RDL according to several embodiments.

AtFIG.6A, a cross-section elevation of a molded silicon-interconnect bridge during assembly601according to an embodiment. A first carrier666supports a first passive device616and a subsequent passive device626, and a silicon interconnect bridge612. The silicon interconnect bridge612includes at least one TSV620. The assembly of passive devices616and626and the silicon interconnect bridge612are overmolded by a molding mass material614such that a die side611and a package side609are formed for later assembly to IC dice and to a package. In an embodiment, a temporary bonding layer is disposed on the first carrier666to secure the first and subsequent passive devices616,626, and the silicon interconnect bridge612.

AtFIG.6B, the assembly602has been inverted and the first carrier666has been stripped from the die side611. A second carrier668is assembled to the package side609. A redistribution layer618has been fabricated on the die side611such that the passive devices616and626, and the silicon interconnect bridge612are directly coupled to the RDL618.

AtFIG.6C, the assembly603has been again inverted after removing the second carrier668from the package side609. Further, a third carrier670has been assembled to the RDL618and the package side609has been processed by back-grinding to expose the silicon interconnect bridge612and the at least one TSV620.

AtFIG.6D, the assembly604has been etched to open contact corridors to the several passive devices616and626, and an electroless plating process has formed a seed layer672that contacts the several termini of the several passive devices616and626, the silicon interconnect bridge612and the at least one TSV620.

At6E, the assembly605has been litho-patterned and electroplated to form a final package side609, and to leave filled vias674in the several contact corridors within the molding mass material614, which has now become the molding-mass frame, e.g., the molding-mass frame114depicted inFIG.1A. In an embodiment, at least one TSV contact pad676is patterned and formed on the at least one TSV620at the package side609.

At6F, the assembly606has been bumped with several electrical bumps624in an array, for coupling the MSiB610to an integrated-circuit package at the package side609, and after separation of the third carrier670, the MSiB610can be assembled at the die side611to at least two IC dice according to several disclosed embodiments.

FIG.7is included to show an example of a higher-level device application for the disclosed embodiments. The molded silicon-bridge interconnect embodiments may be found in several parts of a computing system. In an embodiment, the molded silicon-bridge interconnect embodiments can be part of a communications apparatus such as is affixed to a cellular communications tower. In an embodiment, a computing system700includes, but is not limited to, a desktop computer. In an embodiment, a computing system700includes, but is not limited to a laptop computer. In an embodiment, a computing system700includes, but is not limited to a tablet. In an embodiment, a computing system700includes, but is not limited to a notebook computer. In an embodiment, a computing system700includes, but is not limited to a personal digital assistant (PDA). In an embodiment, a computing system700includes, but is not limited to a server. In an embodiment, a computing system700includes, but is not limited to a workstation. In an embodiment, a computing system700includes, but is not limited to a cellular telephone. In an embodiment, a computing system700includes, but is not limited to a mobile computing device. In an embodiment, a computing system700includes, but is not limited to a smart phone. In an embodiment, a system700includes, but is not limited to an internet appliance. Other types of computing devices may be configured with the microelectronic device that includes molded silicon-bridge interconnect embodiments.

In an embodiment, the processor710has one or more processing cores712and712N, where712N represents the Nth processor core inside processor710where N is a positive integer. In an embodiment, the electronic device system700using a molded silicon-bridge interconnect embodiment that includes multiple processors including710and705, where the processor705has logic similar or identical to the logic of the processor710. In an embodiment, the processing core712includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. In an embodiment, the processor710has a cache memory716to cache at least one of instructions and data for the molded silicon-bridge interconnect element on an integrated-circuit package substrate in the system700. The cache memory716may be organized into a hierarchal structure including one or more levels of cache memory.

In an embodiment, the processor710includes a memory controller714, which is operable to perform functions that enable the processor710to access and communicate with memory730that includes at least one of a volatile memory732and a non-volatile memory734. In an embodiment, the processor710is coupled with memory730and chipset720. In an embodiment, the chipset720is part of a molded silicon-bridge interconnect embodiment depicted inFIG.1A. The processor710may also be coupled to a wireless antenna778to communicate with any device configured to at least one of transmit and receive wireless signals. In an embodiment, the wireless antenna interface778operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

In an embodiment, the volatile memory732includes, but is not limited to, Synchronous Dynamic Random-Access Memory (SDRAM), Dynamic Random-Access Memory (DRAM), RAMBUS Dynamic Random-Access Memory (RDRAM), and/or any other type of random access memory device. The non-volatile memory734includes, but is not limited to, flash memory, phase change memory (PCM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), or any other type of non-volatile memory device.

The memory730stores information and instructions to be executed by the processor710. In an embodiment, the memory730may also store temporary variables or other intermediate information while the processor710is executing instructions. In the illustrated embodiment, the chipset720connects with processor710via. Point-to-Point (PtP or P-P) interfaces717and722. Either of these PtP embodiments may be achieved using a molded silicon-bridge interconnect embodiment as set forth in this disclosure. The chipset720enables the processor710to connect to other elements in a molded silicon-bridge interconnect embodiment in a system700. In an embodiment, interfaces717and722operate in accordance with a PtP communication protocol such as the Intel® QuickPath Interconnect (QPI) or the like. In other embodiments, a different interconnect may be used.

In an embodiment, the chipset720is operable to communicate with the processor710,705N, the display device740, and other devices772,776,774,760,762,764,766,777, etc. The chipset720may also be coupled to a wireless antenna778to communicate with any device configured to at least do one of transmit and receive wireless signals.

The chipset720connects to the display device740via the interface726. The display740may be, for example, a liquid crystal display (LCD), a plasma display, cathode ray tube (CRT) display, or any other form of visual display device. In an embodiment, the processor710and the chipset720are merged into a molded silicon-bridge interconnect embodiment in a system. Additionally, the chipset720connects to one or more buses750and755that interconnect various elements774,760,762,764, and766. Buses750and755may be interconnected together via a bus bridge772such as at least one molded silicon-bridge interconnect embodiment. In an embodiment, the chipset720, via interface724, couples with a non-volatile memory760, a mass storage device(s)762, a keyboard/mouse764, a network interface766, smart TV776, and the consumer electronics777, etc.

In an embodiment, the mass storage device762includes, but is not limited to, a solid-state drive, a hard disk drive, a universal serial bus flash memory drive, or any other form of computer data storage medium. In one embodiment, the network interface766is implemented by any type of well-known network interface standard including, but not limited to, an Ethernet interface, a universal serial bus (USB) interface, a Peripheral Component Interconnect (PCI) Express interface, a wireless interface and/or any other suitable type of interface. In one embodiment, the wireless interface operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, Home Plug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMax, or any form of wireless communication protocol.

While the modules shown inFIG.7are depicted as separate blocks within the molded silicon-bridge interconnect embodiments in a computing system700, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits. For example, although cache memory716is depicted as a separate block within processor710, cache memory716(or selected aspects of716) can be incorporated into the processor core712.

To illustrate the molded silicon interconnect bridge package embodiments and hods disclosed herein, a non-limiting list of examples is provided herein:

Example 1 is an integrated-circuit package substrate, comprising: a silicon interconnect bridge in a molding-mass frame, wherein the molding-mass frame has a die side and a package side, and wherein the silicon interconnect bridge shares the die side; a passive device in the molding-mass frame, wherein the silicon interconnect bridge and the passive device, occupy at least some of the same vertical space encompassed by the molding-mass frame; and a redistribution layer on the die side, wherein the redistribution layer is coupled to the passive device and to a through-silicon via in the silicon interconnect bridge, and wherein the through-silicon via communicates to the, package side.

In Example 2, the subject matter of Example 1 optionally includes a package substrate including a bridge side and a land side, and a ground (Vss) plane in a dielectric material and a power (Vcc) plane in the dielectric material; and where the bridge side of the package substrate is coupled to the package side through an electrical bump.

In Example 3, the subject matter of any one or more of Examples 1-2 optionally include wherein the redistribution layer is coupled at the die side to a first integrated-circuit die by a first electrical bump and to a subsequent integrated-circuit die by a subsequent electrical bump, and wherein communication between the first integrated-circuit die and the subsequent integrated-circuit die is by a trace in the redistribution layer.

In Example 4, the subject matter of any one or more of Examples 1-3 optionally include wherein the redistribution layer is coupled at the die side to a first integrated-circuit die by a first electrical bump and to a subsequent integrated-circuit die by a subsequent electrical bump, and wherein communication between the first integrated-circuit die and the subsequent integrated-circuit die is by the through-silicon via in the silicon interconnect bridge.

In Example 5, the subject matter of any one or more of Examples 1-4 optionally include wherein the redistribution layer is coupled at the die side to a first integrated-circuit die by a first electrical bump and to a subsequent integrated-circuit die by a subsequent electrical bump, wherein communication between the first integrated-circuit die and the subsequent integrated-circuit die is by the through-silicon via in the silicon interconnect bridge, and also by a trace in the redistribution layer.

In Example 6, the subject matter of any one or more of Examples 1-5 optionally include wherein the passive device is both coupled to the die side and to the package side.

In Example 7, the subject matter of any one or more of Examples 1-6 optionally include wherein the passive device is both coupled to the die side and to the package side, wherein the passive device is a first passive device, further including a subsequent passive device in the molding-mass frame, wherein the first passive device and the subsequent passive device are on opposite sides of the silicon interconnect bridge.

In Example 8, the subject matter of any one or more of Examples 1-7 optionally include wherein the passive device is a first capacitor, further including a subsequent capacitor, and wherein the first and subsequent capacitor are contacted at respective power terminals, to form a power rail.

In Example 9, the subject matter of any one or more of Examples 1-8 optionally include wherein the passive device is a first capacitor, further including a subsequent capacitor, and wherein the first and subsequent capacitor are contacted at respective power terminals, to form a power rail, further including: a package substrate including a bridge side and a land side, and a ground (Vss) plane in a dielectric material and a power (Vcc) plane in the dielectric material; where the bridge side of the package substrate is coupled to the package side through an electrical bump; and wherein the Vcc plane is coupled to the power rail.

In Example 10, the subject matter of any one or more of Examples 1-9 optionally include wherein the passive device is a first capacitor, further including a subsequent capacitor, and wherein the first and subsequent capacitor are contacted at respective power terminals, to form a power rail, further including: a third capacitor, wherein the third capacitor contacts the subsequent capacitor to form a Vss rail, and wherein the subsequent capacitor is stacked on the first capacitor and the third capacitor.

In Example 11, the subject matter of any one or more of Examples 1-10 optionally include wherein the passive device is a first capacitor, further including a subsequent capacitor, and wherein the first and subsequent capacitor are contacted at respective power terminals, to form a power rail; a third capacitor, wherein the third capacitor contacts the subsequent capacitor to form a Vss rail, and wherein the subsequent capacitor is stacked on the first capacitor and the third capacitor; a package substrate including a bridge side and a land side, and a ground (Vss) plane in a dielectric material and a power (Vcc) plane in the dielectric material; where the bridge side of the package substrate is coupled to the package side through an electrical bump; wherein the Vcc plane is coupled to the power rail; and wherein the Vss plane is coupled to the Vss rail.

Example 12 is an integrated-circuit package substrate, comprising: a first silicon interconnect bridge in a molding-mass frame, wherein the molding-mass frame has a die side and a package side, and wherein the first silicon interconnect bridge shares the die side; a subsequent silicon interconnect bridge in the molding-mass frame, wherein some molding-mass material of the molding-mass frame, spaces apart the first silicon interconnect bridge from the subsequent silicon interconnect bridge, and wherein the subsequent silicon interconnect bridge also shares the die side; an interstitial passive device in the molding-mass material between the first silicon interconnect bridge and the subsequent silicon interconnect bridge, wherein the first and subsequent silicon interconnect bridges and the interstitial passive device, occupy at least some of the same vertical space encompassed by the molding-mass frame; a redistribution layer on the die side, wherein the redistribution layer is coupled to the passive device and to a first through-silicon via in the first silicon interconnect bridge, and wherein the first through-silicon via communicates to the package side; and wherein the redistribution layer is coupled to the passive device and to a subsequent through-silicon via in the subsequent silicon interconnect bridge, and wherein the subsequent through-silicon via communicates to the package side.

In Example 13, the subject matter of Example 12 optionally includes a first capacitor in the molding-mass material and adjacent the first silicon interconnect bridge and opposite the interstitial passive device; a subsequent capacitor in the molding-mass material and adjacent the subsequent silicon interconnect bridge and opposite the interstitial passive device.

In Example 14, the subject matter of any one or more of Examples 12-13 optionally include a package substrate including a bridge side and a land side, and a ground (Vss) plane in a dielectric material and a power (Vcc) plane in the dielectric material; where the bridge side of the package substrate is coupled to the package side through an electrical bump; wherein the redistribution layer is coupled at the die side to a first integrated-circuit die by a first electrical bump and to a subsequent integrated-circuit die by a subsequent electrical bump, and wherein communication between the first integrated-circuit die and the subsequent integrated-circuit die is by a trace in the redistribution layer.

In Example 15, the subject matter of any one or more of Examples 12-14 optionally include wherein the redistribution layer is coupled at the die side to a first integrated-circuit die by a first electrical bump and to a subsequent integrated-circuit die by a subsequent electrical bump, and wherein communication between the first integrated-circuit die and the subsequent integrated-circuit die is by a trace in the redistribution layer.

In Example 16, the subject matter of any one or more of Examples 12-15 optionally include wherein the passive device is a capacitor that is both coupled to the die side and to the package side.

In Example 17, the subject matter of any one or more of Examples 12-16 optionally include a first-side first capacitor and a first-side subsequent capacitor in the molding-mass material and adjacent the first silicon interconnect bridge and opposite the interstitial passive device, wherein the first-side first capacitor and a first-side subsequent capacitor are contacted at respective power terminals, to form a first power rail; a subsequent-side first capacitor and a subsequent-side subsequent capacitor in the molding-mass material and adjacent the subsequent silicon interconnect bridge and opposite the interstitial passive device, wherein the subsequent-side first capacitor and a subsequent-side subsequent capacitor are contacted at respective power terminals, to form a subsequent power rail.

In Example 18, the subject matter of Example 17 optionally includes a package substrate including a bridge side and a land side, and a ground (Vss) plane in a dielectric material and a power (Vcc) plane in the dielectric material; where the bridge side of the package substrate is coupled to the package side through an electrical bump; and wherein the Vcc plane is coupled to at least one of the first power rail and the subsequent power rail.

In Example 19, the subject matter of Example 18 optionally includes a first-side third capacitor, wherein the first-side third capacitor contacts the first-side subsequent capacitor to form a Vss rail, and wherein the first-side subsequent capacitor is stacked on the first-side first capacitor and the first-side third capacitor.

Example 20 is a computing system comprising: a silicon interconnect bridge in a molding-mass frame, wherein the molding-mass frame has a die side and a package side, and wherein the silicon interconnect bridge shares the die side; a first integrated-circuit die on the die side, wherein the first IC die is a logic processor; a subsequent integrated-circuit die on the die side and adjacent the first integrated-circuit die, wherein the subsequent IC die is a graphics processor; a passive device in the molding-mass frame, wherein the silicon interconnect bridge and the passive device, occupy at least some of the same vertical space encompassed by the molding-mass frame; a redistribution layer on the die side, wherein the redistribution layer is coupled to the passive device and to a through-silicon via in the silicon interconnect bridge, and wherein the through-silicon via communicates to the package side; a package substrate including a bridge side and a land side, and a voltage-reference (Vss) plane in a dielectric material and a power (Vcc) plane in the dielectric material; where the bridge side of the package substrate is coupled to the package side through an electrical bump; wherein the redistribution layer is coupled at the die side to the first IC die by a first electrical bump and to the subsequent IC die by a subsequent electrical bump, and wherein communication between the first integrated-circuit die and the subsequent integrated-circuit die is by a trace in the redistribution layer; and wherein the molded silicon-interconnect bridge is part of a chipset.

In Example 21, the subject matter of Example 20 optionally includes a third IC die on the redistribution layer, wherein the third IC die is a memory die; and a board coupled to the package substrate at the land side, by an electrical-bump array.

In Example 22, the subject matter of Example 21 optionally includes wherein the hoard includes an external shell that is a dielectric material, and wherein the external shell is at least part of the exterior of an apparatus selected from a mobile computing system and a drone.

The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as “examples.” Such examples can include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

In the event of inconsistent usages between this document and any documents so incorporated by reference, the usage in this document controls.

In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or ltd “one or more.” In this document, the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated. In this document, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.” Also, in the following claims, the terms “including” and “comprising” are open-ended, that is, a system, device, article, composition, formulation, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

Method examples described herein can be machine or computer-implemented at least in part. Some examples can include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electrical device to perform methods as described in the above examples. An implementation of such methods can include code, such as microcode, assembly language code, a higher-level language code, or the like. Such code can include computer readable instructions for performing various methods. The code may form portions of computer program products. Further, in an example, the code can be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media can include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memories (RAMS), read only memories (ROMs), and the like.

The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. § 1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description as examples or embodiments, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments can be combined with each other in various combinations or permutations. The scope of the disclosed embodiments should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.