Patent ID: 12219746

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numerals are used to designate like elements. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method.

Fin structures described below may be patterned by any suitable method. For example, the fins may be patterned using one or more lithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine lithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.

Embodiments of forming a semiconductor structure are provided. The aspect of the present disclosure is directed to forming p-channel devices in a logic area and a memory cell array area having respective enhancing performances. The logic devices may focus more on high on-current, while memory devices (e.g., SRAM) may focus more on improvement in short channel effect (SCE). In accordance with some embodiments, a top fin element of a first fin structure for logic devices is formed with a greater thickness than a top fin element of a second fin structure for memory devices. Therefore, the top fin element of the first fin structure may provide a relatively large area of the channel, which enhance the performance of the resulting logic device. Furthermore, the final gate stack can have better control over the top fin element of the second fin structure, which may enhance the performance of the resulting SRAM device. Therefore, the embodiments of the present disclosure may provide great flexibility in turning the respective performances of the logic p-channel device and SRAM p-channel device.

FIG.1is a perspective view of a semiconductor structure100, in accordance with some embodiments of the disclosure. The semiconductor structure100includes a substrate102, in accordance with some embodiments. The semiconductor structure100(or the substrate102) may include various device areas, e.g., a logic area, a memory cell array area, an analog region, a peripheral area (e.g., an input/output area), another suitable area, or a combination thereof.FIG.1illustrates a logic area50A and a memory cell array area50B of the semiconductor structure100(or the substrate102), in accordance with some embodiments. The logic area50A and the memory cell array area50B are part of an integrated circuit (IC) device, in accordance with some embodiments.

Logic devices are to be formed in the logic area50A, and the memory devices (e.g., SRAM (Static Random-Access Memory), DRAM (Dynamic Random Access Memory), or Flash memory) are to be formed in the memory cell array area50B, in accordance with some embodiments. The logic devices perform the designed functions of an integrated circuit (IC) device, and the memory devices are operable as data storage, in accordance with some embodiments. The logic devices may be operable to access and/or control (e.g., perform read/write/erase operation) the memory devices, in accordance with some embodiments. Although the logic area50A and the memory cell array area50B are shown as being immediately adjacent to one another inFIG.1, the logic area50A and the memory cell array area50B may be spaced apart from one another by another device area, in accordance with some embodiments.

For a better understanding of the semiconductor structure, an X-Y-Z coordinate reference is provided inFIG.1. The X-axis and Y-axis are generally orientated along the lateral (or horizontal) directions that are parallel to the main surface of the semiconductor structure. The Y-axis is transverse (e.g., perpendicular or substantially perpendicular) to the X-axis. The Z-axis is generally oriented along the vertical direction that is perpendicular to the main surface of a semiconductor structure (or the X-Y plane).

The semiconductor structure100includes fin structures120P and120N over the logic area50A of the substrate102, and fin structures122P and122N over the memory cell array area50B of the substrate102, as shown inFIG.1, in accordance with some embodiments. The fin structure120P and the fin structure120N are used to form p-channel FinFETs and n-channel FinFETs for logic devices, respectively, in accordance with some embodiments. The fin structure122P and the fin structure122N are used to form p-channel FinFETs and n-channel FinFETs for memory devices, respectively, in accordance with some embodiments.

The fin structures120P,120N,122P and122N extend in the X direction, in accordance with some embodiments. That is, the fin structures120P,120N,122P and122N have longitudinal axes parallel to the X direction, in accordance with some embodiments. The X direction may also be referred to as the channel-extending direction. The current of the resulting semiconductor devices (i.e., FinFETs) flows in the X direction through the channel.

Each of the fin structures120P,120N,122P and122N includes a channel region CH and source/drain regions SD, where the channel region CH is defined between the source/drain regions SD, in accordance with some embodiments, in this disclosure, a source/drain refers to a source and/or a drain. It should be noted that in the present disclosure, a source and a drain are used interchangeably and the structures thereof are substantially the same.FIG.1shows one channel region CH and two source/drain regions SD for illustrative purposes and is not intended to be limiting. The number of channel regions CH and source/drain regions SD may be dependent on the demands on the design of the semiconductor device and/or performance considerations.

A gate structure or gate stack (not shown) will be formed with a longitudinal axis parallel to the Y direction and extending across and/or surrounding the channel regions CH of the fin structures120P,120N,122P and122N. The Y direction may also be referred to as a gate-extending direction.

FIG.1further illustrates reference cross-sections that are used in later figures. Cross-section Y1-Y1is in a plane parallel to the longitudinal axis (Y direction) of a gate structure and across the channel regions CH of the fin structures120P and120N, in accordance with some embodiments. Cross-section Y2-Y2is in a plane parallel to the longitudinal axis (Y direction) of a gate structure and across channel regions CFI of the fin structure122P and122N, in accordance with some embodiments.

Cross-sections X1-X1, X2-X2, X3-X3and X4-X4are in planes parallel to the longitudinal axis (X direction) of the fin structures120P,120N,122P and122N and through the fin structures120P,120N,122P and122N respectively, in accordance with some embodiments.

FIGS.2A,2B,2C,2D,2E,2F,2G,2H-1,2H-2,2I-1,2I-2,2J-1,2J-2,2K-1,2K-2,2L-1, and2L-2are cross-sectional views illustrating the formation of a semiconductor structure at various intermediate stages, in accordance with some embodiments of the disclosure.FIGS.2A,213.2C,2D.2E,2F.2G,2H-1,2I-1,2I-1,2K-I and2L-1correspond to the cross-sections Y1-Y1and Y2-Y2of FIG. I.FIGS.2H-2,2I-2,2J-2,2K-2, and2L-2correspond to the cross-sections X1-X1, X2-X2, X3-X3and X4-X4ofFIG.1.

FIG.2Aillustrates a semiconductor structure after the formation of wells104N,104P,106N and106P, in accordance with some embodiments.

A substrate102is provided, as shown inFIG.2A, in accordance with some embodiments. The substrate102may be a portion of a semiconductor wafer, a semiconductor chip (or die), and the like. In some embodiments, the substrate102is a silicon substrate. In some embodiments, the substrate102includes an elementary semiconductor such as germanium; a compound semiconductor such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonids (InSb); an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP; or a combination thereof. Furthermore, the substrate102may optionally include an epitaxial layer (epi-layer), may be strained for performance enhancement, may include a silicon-on-insulator (SOI) structure, and/or have other suitable enhancement features.

Some areas of the substrate102are defined as a logic area50A for forming logic devices thereon and a memory cell array area50B for forming memory devices (e.g., SRAM) thereon, as shown inFIG.2A, in accordance with some embodiments.

An n-type well104N and a p-type well104P are formed in the logic area50A of the substrate102, and an n-type well106N and a p-type well106P are formed in the memory cell array area50B of the substrate102, as shown inFIG.2A, in accordance with some embodiments. In some embodiments, the wells104N,104P,106N and106P are formed by ion implantation processes.

For example, a patterned mask layer (such as a photoresist layer and/or a hard mask layer) is formed to cover regions of the substrate102where the p-type wells are predetermined to be formed, and then n-type dopants (such as phosphorus or arsenic) are implanted into the substrate102, thereby forming the n-type wells104N and106N, in accordance with some embodiments. Afterward, the patterned mask layer may be removed.

Similarly, a patterned mask layer (such as photoresist layer and/or hard mask layer) is formed to cover regions of the substrate102where the n-type wells are predetermined to be formed, and then p-type dopants (such as boron or BF2) are implanted into the substrate102, thereby forming the p-type wells104P and106P, in accordance with some embodiments, Afterward, the patterned mask layer may removed.

In some embodiments, the respective concentrations of the dopants in the wells104N,104P,106N and106P are in a range from about 1016/cm−3to about 1018/cm−3. In sonic embodiments, the ion implantation processes may be performed several times with different dosages and different energy intensities. In some embodiments, the ion implantation process may include anti-punch through (APT) implant.

The numbers of the n-type wells104N and the p-type wells104N in the logic area50A and/or the numbers of the n-type wells106N and the p-type wells106N in the memory cell array area50B may be dependent on the demands on the design of the semiconductor device and/or performance considerations. In some embodiments, in the logic area50A, the n-type wells104N and the p-type wells104N are alternately arranged in the Y direction. In some embodiments, in the memory cell array area50B, the n-type wells106N and the p-type wells106N are alternately arranged in the Y direction.

In some embodiments, the width (in the Y direction) of the n-type well104N is substantially the same as the width (in the Y direction) of the n-type well106N, while the width (in the Y direction) of the p-type well104P is substantially same as the width (in the Y direction) of the p-type well106P. In some embodiments, the pitch (in the Y direction) of the n-type well104N (or the p-type well104P) is substantially the same as the pitch (in the Y direction) of the n-type well106N (or the p-type well106P).

FIG.2Billustrates a semiconductor structure after the formation of a semiconductor material108, a dielectric layer110and a patterned mask layer112, in accordance with sonic embodiments.

A semiconductor material108is formed over the substrate102, as shown inFIG.28, in accordance with some embodiments. In some embodiments, the semiconductor material108is pure or substantially pure silicon. The concentrations of the impurity (or the dopant) in the semiconductor material108is less than the concentrations of the dopants in the wells104N,104P,106N and106P, in accordance with some embodiments. For example, the concentrations of the impurity (or the dopant) in the semiconductor material108is less than 1014/cm−3.

In some embodiments, the semiconductor material108is globally grown over the substrate102using an epitaxial growth process. The epitaxial growth process may be molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE), or another suitable technique. In some embodiments, the semiconductor material108has a thickness D1(in the Z direction) in a range from about 27.5 nm to about 200 nm.

A dielectric layer110is formed over the semiconductor material108, as shown inFIG.2B, in accordance with some embodiments. In some embodiments, the dielectric layer110is made of dielectric material, such as silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), oxygen-doped silicon carbonitride (Si(O)CN), another suitable dielectric material.

In some embodiments, the dielectric layer110is globally deposited over the semiconductor material108. The deposition process may be chemical vapor deposition (CVD) (such as low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), high density plasma CVD (HDP-CVD), high aspect ratio process (HARP), or flowable CVD (FCVD)), atomic layer deposition (ALD), another suitable technique, and/or a combination thereof.

A patterned mask layer112is formed over the dielectric layer110, as shown inFIG.2B, in accordance with some embodiments. The patterned mask layer112vertically covers and/or overlaps the p-type wells104P and106P, in accordance with some embodiments. In some embodiments, the patterned mask layer112has trench patterns exposing the dielectric layer110. In some embodiments, the patterned mask layer112is a patterned photoresist layer, a patterned hard mask layer, or a combination thereof.

For example, a bottom anti-reflective coating (BARC) material is formed over the dielectric layer110using a deposition process, and a photoresist may be formed on the BARC material, such as by using spin-on coating. The BARC material may contain silicon, nitrogen, carbon, oxygen, another suitable element, and/or a combination thereof. The photoresist is then patterned with trench patterns (e.g., aligned over to the n-type wells104N and106N) by exposing the photoresist to light using an appropriate photomask. Exposed or unexposed portions of the photo resist may be removed depending on whether a positive or negative resist is used. The trench patterns of the photoresist may then be transferred to the BARC material, such as by using an etching process, e.g., an anisotropic etching process such as dry plasma etching.

FIG.2Cillustrates a semiconductor structure after an etching process, in accordance with some embodiments.

An etching process is performed using the patterned mask layer112to etch away portions of the dielectric layer110and the semiconductor material108uncovered by the patterned mask layer112, as shown inFIG.2C, in accordance with some embodiments. The etching process may be an anisotropic etching process such as dry plasma etching, an isotropic etching process such as dry chemical etching, remote plasma etching, wet chemical etching, and/or a combination thereof. The patterned mask layer112is removed during the etching process or by an additional process (such as etching, wet strip and/or aching), in accordance with some embodiments.

The trench patterns of the patterned mask layer112are transferred to the semiconductor material108, thereby forming a trench114A in the logic area50A and a trench114B in the memory cell area50B, in accordance with some embodiments. The trench114A is aligned over the n-type well104N, and the trench114B is aligned over the n-type well106N, in accordance with some embodiments. In some embodiments, the trench114A and the trench114B have the same etching depth D2in a range from about 25 nm to about 150 nm.

In some embodiments, in the logic area50A, an unetched portion of the semiconductor material108, protected by the patterned mask layer112, is denoted as108A, and the portion108A is located directly above the p-type well104P. In some embodiments, in the logic area50A, a remaining portion of the semiconductor material108directly below the trench114A is denoted as108C, and the portion108C is located directly above the n-type well104N.

In some embodiments, in the memory cell array area50B, an unetched portion of the semiconductor material108, protected by the patterned mask layer112, is denoted as108B, and the portion108B is located directly above the p-type well106P. In some embodiments, in the memory cell array area50B, a remaining portion of the semiconductor material108directly below the trench114B is denoted as10813, and the portion108D is located directly above the n-type well106N.

FIG.2Dillustrates a semiconductor structure after the formation of a patterned mask layer116, in accordance with some embodiments.

A patterned mask layer116is formed over the semiconductor structure ofFIG.2C, as shown inFIG.2D, in accordance with some embodiments. The patterned mask layer116vertically covers and/or overlaps the p-type well104P in the logic area50A and the n-type well106N and the p-type well106P in the memory cell array area50B, in accordance with some embodiments. In some embodiments, the trench114B is overfilled by the patterned mask layer116, In some embodiments, the patterned mask layer116has a trench pattern exposing the portion108C of the semiconductor material108. In some embodiments, the patterned mask layer116is a patterned photoresist layer, a patterned hard mask layer, or a combination thereof.

For example, a BARC material is formed over the semiconductor structure ofFIG.2Cusing a deposition process, and a photoresist may be formed on the BARC material, such as by using spin-on coating. The BARC material may contain silicon, nitrogen, carbon, oxygen, another suitable element, and/or a combination thereof. The photoresist is then patterned with a trench pattern (e.g., aligned over to the n-type well104N) by exposing the photoresist to light using an appropriate photomask. Exposed or unexposed portions of the photo resist may be removed depending on whether a positive or negative resist is used. The trench pattern of the photoresist may then be transferred to the BARC material, such as by using an etching process, e.g., an anisotropic etching process such as dry plasma etching.

FIG.2Eillustrates a semiconductor structure after an etching process, in accordance with some embodiments.

An etching process is performed using the patterned mask layer116to recess the portion108C of the semiconductor material108that is uncovered by the patterned mask layer116, as shown inFIG.2E, in accordance with some embodiments. The etching process may be an anisotropic etching process such as dry plasma etching, an isotropic etching process such as dry chemical etching, remote plasma etching, wet chemical etching, and/or a combination thereof. The patterned mask layer116is removed during the etching process or by an additional process (such as etching, wet strip and/or ashing), in accordance with some embodiments.

As a result, the trench114A is enlarged and denoted as114X, in accordance with some embodiments. In some embodiments, the trench114A′ has an etching depth D3in a range from about 27.5 nm to about 165 nm. In some embodiments, the trench114A′ is deeper than the trench114B by a dimension D4. In some embodiments; the dimension D4is in a range from about 2.5 nm to about 15 nm.

In some embodiments, the recessed portion108C of the semiconductor material108has a thickness D5. In some embodiments, the thickness D5is in a range from about 1 nm to about 35 nm. In alternatively embodiments, the portion108C of the semiconductor material108may be entirely removed in the etching process (i.e., D5is zero). In sonic embodiments, the portion108D of the semiconductor material108is thicker than the portion108C of the semiconductor material108and has a thickness D6. In some embodiments, the thickness D6is in a range from about 2.5 nm to about 50 nm.

FIG.2Fillustrates a semiconductor structure after the formation of semiconductor materials118A and118B, in accordance with some embodiments.

A semiconductor material118(including118A and118B) is formed to fill the trenches114A′ and11413, as shown inFIG.2E, in accordance with some embodiments. The semiconductor material118A is formed in the trenches114K and covers the portion108C of the semiconductor material108, and the semiconductor material118E is formed in the trenches114B and covers the portion108D of the semiconductor material108in accordance with some embodiments.

In some embodiments, the semiconductor material118is silicon germanium (Sidey), where y is greater than about 20%, e.g., ranging from about 20% to about 45%. The concentrations of the impurity (or the dopant) in the semiconductor material118is less than the concentrations of the dopants in the wells104N,104P,106N and106P, in accordance with some embodiments. For example, the concentrations of the impurity (or the dopant) in the semiconductor material118is less than 1014/cm−3.

In some embodiments, the semiconductor material118is grown from the semiconductor surface provided from the semiconductor material108using an epitaxial growth process. The epitaxial growth process may be MBE, MOCVD, or VPE, or another suitable technique. The upper surface of the semiconductor material118A is located a position substantially level to or higher than the top surface of the portion108A of the semiconductor material108, in accordance with some embodiments. The upper surface of the semiconductor material118D is located a higher position than the top surface of the portion108B of the semiconductor material108and the upper surface of the semiconductor material118A, in accordance with some embodiments.

In sonic embodiments, the semiconductor material118is difficult to grow on the dielectric material. Therefore, after the epitaxial growth is completed, the semiconductor material118covers only edge portions of the top surface of the dielectric layer110, in accordance with some embodiments.

FIG.2Gillustrates a semiconductor structure after a planarization process, in accordance with some embodiments.

A planarization process may be performed on the semiconductor structure ofFIG.2Fto expose the portions108A and108B of the semiconductor materials108, as shown inFIG.2G, in accordance with some embodiments. The planarization process may be chemical mechanical polishing (CMP) or an etching-back process. In the planarization process, the dielectric layer110is entirely removed, in accordance with some embodiments. After the planarization process, the top surfaces of the semiconductor material108A and108B and the semiconductor material118A and118B are substantially coplanar, in accordance with some embodiments.

FIGS.2H-1and2H-2illustrate a semiconductor structure after the formation of fin structures120P,120N,122P and122N, in accordance with some embodiments.

The semiconductor structure ofFIG.2Gis patterned to form fin structures120P,120N,122P and122N, as shown inFIGS.2H-1and2H-2, in accordance with some embodiments. In the logic area50A, the fin structure120P is formed over the n-type well104N and the fin structure120N is formed over the p-type well104P, in accordance with some embodiments. In the memory cell array area50B, the fin structure122P is formed over the n-type well106N and the fin structure122N is formed over the p-type well106P, in accordance with some embodiments. AlthoughFIG.2H-1illustrates that a single fin structure is formed in a single well, more than one fin structure may be formed in a single well.

In some embodiments, the patterning process for forming the fin structures120P.120N,122P and122N includes forming a patterned mask layer (not shown) over the semiconductor structure ofFIG.2G. The patterned mask layer may be a patterned photoresist layer, a patterned hard mask layer, or a combination thereof.

The patterning process further includes performing an etching process to etch away portions of the semiconductor materials118A and118B and the semiconductor materials108A,108B,108C and108D, and wells104N,104P,106N and106P uncovered by the patterned hard mask layer, thereby forming trenches and the fin structures120P,120N.122P and122N protruding from between the trenches, in accordance with some embodiments. The etching process may be an anisotropic etching process, e.g., dry plasma etching. The patterned mask layer may be removed during the etching process or by an additional process (such as etching, wet strip and/or ashing), in accordance with sonic embodiments.

The fin structure120P includes, from bottom to top, a bottom fin element formed from the n-type well104N, a middle fin element formed from the semiconductor material108C, and a top fin element formed from the semiconductor material118A, in accordance with some embodiments. In alternative embodiments where the semiconductor material108C is entirely removed, the fin structure120P has no middle fin element.

The fin structure120N includes, from bottom to op, a bottom fin element formed from the p-type well104P and a top fin element formed from the semiconductor material108A, in accordance with some embodiments.

The fin structure122P includes, from bottom to top, a bottom fin element formed from the n-type well106N, a middle fin element formed from the semiconductor material108D, and a top fin element formed from the semiconductor material118B, in accordance with some embodiments.

The fin structure122N includes, from bottom to top, a bottom fin element formed from the p-type well106P and a top fin element formed from the semiconductor material108B, in accordance with some embodiments.

In some embodiments, the top fin element118A of the fin structure120P has a thickness D7in a range from about 27.5 nm to about 165 nm. In some embodiments, the top fin element118B of the fin structure122P has a thickness D8in a range from about 25 nm to about 150 nm. In some embodiments, the thickness D7is greater than the thickness D8by the dimension D4is in a range from about 2.5 nm to about 15 nm. In some embodiments, the bottom surface118A1of the top fin element118A is located at a lower position than the bottom surface118B1of the top fin element118B.

In some embodiments, the middle fin element108C of the fin structure120P has a thickness D5in a range from about 1 nm to about 35 nm. In sonic embodiments, the middle fin element108D of the fin structure122P has a thickness D6in a range from about 2.5 nm to about 50 nm. In some embodiments, the thickness D5is less than the thickness D6by the dimension D4.

In some embodiments, the top fin element108A (or108B) of the fin structure120N (or122N) has a thickness D9in a range from about 27.5 nm to about 200 nm. In some embodiments, the thickness D9of the top fin element108A (or108B) is greater than the thickness D7of the top fin element118A and the thickness D8of the top fin element118B.

In some embodiments, the fin structures120P,120N,122P and122P have rounded tops. In alternative embodiments, the fin structures120P,120N,122P and122P have pointed tops or substantially flat top surfaces. In some embodiments, the tops of the fin structures120P,120N,122P and122P are located in substantially the same position.

FIGS.2I-1and2I-2illustrate a semiconductor structure after the formation of a semiconductor capping layer124and an isolation structure126, in accordance with some embodiments.

A semiconductorcapping layer124is formed along the semiconductor structure ofFIGS.1H-1and1H-2, as shown inFIGS.2I-1and2I-2, in accordance with some embodiments. The semiconductor capping layer124covers and extends along sidewalls and the tops the fin structures120P,120N,122P and122P and the upper surfaces of the wells104N,104P,106N and106P, in accordance with some embodiments. In some embodiments, the semiconductor capping layer124is made of silicon. In some embodiments, the semiconductor capping layer124is deposited using CVD, ALD, another suitable deposition technique, and/or a combination thereof.

In some embodiments, the semiconductor capping layer124has a thickness in a range from about 2 nm to about 15 nm. The semiconductor capping layer124is configured to reduce the crystalline defects on the exposed etched surface of the top fin elements118A and118B of the fin structures120P and122P (eg., repairing the dangling bond), thereby improving the mobility of the carrier of the resulting semiconductor device, in accordance with some embodiments.

An isolation structure126is formed over the semiconductor capping layer124to partially surround the fin structures120P,120N,122P and122P, as shown inFIG.2I-1, in accordance with some embodiments. The isolation structure126may be also referred to as shallow trench isolation (STI) feature In some embodiments, the isolation structure126is made of dielectric material such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxvnitride (SiON), silicon carbide (SiC), oxygen-doped silicon carbide (SiC:O), oxygen-doped silicon carbonitride (Si(O)CN), or a combination thereof.

In some embodiments, the formation of the isolation structure126includes depositing a dielectric material for the isolation structure126to overfill the trenches. In some embodiments, the dielectric material is deposited using chemical vapor deposition (CVD) (such as FCVD, LPCVD, PECVD, HDP-CVD, or HARP), ALD, another suitable technique, and/or a combination thereof.

The dielectric material formed over the tops of the fin structures120P,120N,122P and122P is planarized to expose the tops of the fin structures120P,120N,122E and122P, for example, using CMP, etching back process, or a combination thereof, in accordance with some embodiments.

The dielectric material is further recessed to expose the sidewalls of the fin structures120P,120N,122P and122P, in accordance with some embodiments. The recessing process may be an anisotropic etching process such as dry plasma etching, an isotropic etching process such as dry chemical etching, remote plasma etching or wet chemical etching, and/or a combination thereof. A remainder of the dielectric material serves as the isolation structure126, in accordance with some embodiments.

In some embodiments, the top surface126T of the isolation structure126is substantially flat. In alternative embodiments, the top surface1261of the isolation structure126is curved (e.g., concave). In some embodiments, the top surface1261of the isolation structure126is located at a position that is higher than the bottom surface118A1of the top fin element1185of the fin structure120P and lower than the bottom surface118B1of the top fin element118B of the fin structure122P.

A distance D10between the top surface126T of the isolation structure126and the bottom surface118A1of the top fin element118A is in a range from about 1 nm to about 12 nm. A distance D11between the top surface126T of the isolation structure126and the bottom surface118B1of the top fin element118B is in a range from about 1 nm to about 12 nm. The distance D10may be greater than, equal to, or less than the distance D11. In some embodiments, the position of the top surface126T of the isolation structure126may be adjusted in accordance with the performance requirements of the p-channel transistors (formed on the fin structures120P and122P), e.g., On-current (Ion), drain current in linear region (Id), channel resistance (RCH), parasitic capacitance, short channel effect (SCE), drain-induced barrier lowering (DIBL), etc. This will be discussed in detail later.

FIGS.2J-1and2J-2illustrate a semiconductor structure after the formation of dummy gate structures128A and1288, gate spacer layers134, source/drain features136N and136P, contact etching stop layer (CESL)138, and interlayer dielectric (IMD) layer140, in accordance with some embodiments.

A dummy gate structure128(including128A and1288) is formed over the semiconductor structure ofFIGS.2I-1and2I-2, as shown inFIGS.2J-1and2J-2, in accordance with some embodiments. The dummy gate structure128A is formed in the logic area50A and extends across and surrounds the channel regions of the fin structures120P and120N, in accordance with sonic embodiments. The dummy gate structure1288is formed in the memory cell array area50B and extends across and surrounds the channel regions of the fin structures122P and122N, in accordance with some embodiments. The dummy gate structures128A and1288define the channel region and the source/drain regions of the fin structures, in accordance with some embodiments.

In some embodiments, the dummy gate structures128A and128B extend in the Y direction. That is, the dummy gate structures128A and128B have longitudinal axes parallel to the Y direction, in accordance with some embodiments. The dummy gate structures128A and128B may be a single, continuous gate structure, or may be spaced apart from one another. The dummy gate structure12$ is configured as a sacrificial structure and will be replaced with a final gate stack, in accordance with some embodiments.

The dummy gate structure128includes a dummy gate dielectric layer130and a dummy gate electrode layer132formed over the dummy gate dielectric layer130, as shown inFIGS.2J-1and2J-2, in accordance with some embodiments. In some embodiments, the dummy gate dielectric layer130is made of one or more dielectric materials, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), HfO2, HfZrO, HfSiO, HfTiO, HfAlO, and/or a combination thereof. In some embodiments, the dielectric material is formed using ALD, CVD, thermal oxidation, physical vapor deposition (PVD), another suitable technique, and/or a combination thereof.

In some embodiments, the dummy gate electrode layer132is made of semiconductor material such as poly-silicon, poly-silicon germanium. In some embodiments, the dummy gate electrode layer132is made of a conductive material such as metallic nitrides, metallic silicides, metals, and/or a combination thereof. In some embodiments, the material for the dummy gate electrode layer132is formed using CVD, another suitable technique, and/or a combination thereof.

In some embodiments, the formation of the dummy gate structure128includes globally and conformally depositing a dielectric material for the dummy gate dielectric layer130over the semiconductor structure, depositing a material for the dummy gate electrode layer132over the dielectric material, planarizing the material for the dummy gate electrode layer132, and patterning the dielectric material and the material for the dummy gate electrode layer132into the dummy gate structure128.

The patterning process includes forming a patterned hard mask layer (not shown) over the material for the dummy gate electrode layer132to vertically cover the channel regions of the fin structures120P,120N,122P and122N, in accordance with some embodiments. The material for the dummy gate electrode layer132and the dielectric material, uncovered by the patterned hard mask layer, is etched away until the source/drain regions of the fin structures120P,120N,122P and122N are exposed, in accordance with some embodiments.

The top fin element118A of the fin structure120P extends downward beyond the dummy gate structure128A, as shown inFIG.2J-1, in accordance with some embodiments. In specific, the dummy gate dielectric layer130has a vertical portion extending along the sidewall of the top fin element118A, and the bottom130A1of the vertical portion of the dummy gate dielectric layer130is located at a higher position than the bottom surface118A1of the top fin element118A, in accordance with some embodiments.

The top fin element118B of the fin structure122P is encapsulated in the dummy gate structure128B, as shown inFIG.2J-1, in accordance with some embodiments. In specific, the dummy gate dielectric layer130has a vertical portion extending along the sidewall of the top fin element118B, and the bottom130B1of the vertical portion of the dummy gate dielectric layer130is located at a lower position than the bottom surface118B1of the top fin element118B, in accordance with some embodiments.

Gate spacer layers134are formed along the sidewalls of the dummy gate structure128, as shown inFIG.2J-2, in accordance with some embodiments. The gate spacer layers134are used to offset the subsequently formed source/drain features and separate the source/drain features from the gate structure, in accordance with some embodiments. In some embodiments, the gate spacer layers134are made of dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarhonitride (SiOCN), and/or oxygen-doped silicon carbonitride (Si(O)CN).

In some embodiments, the formation of the gate spacer layer134includes globally and conformally depositing a dielectric material for the gate spacer layer134over the semiconductor structure, followed by an anisotropic etching process. In some embodiments, the etching process is performed without an additional photolithography process. Remaining portions of the dielectric material on the sidewalls of the dummy gate structure128serve as the gate spacer layers134, in accordance with some embodiments.

N-type source/drain features136N and p-type source/drain features136P are formed over the semiconductor structure, as shown inFIG.2J-2, in accordance with some embodiments. The p-type source/drain features I36P are formed in fin structures120P and122P at the source/drain regions, in accordance with some embodiments. The n-type source/drain features136N are formed in fin structures120N and122N at the source/drain regions, in accordance with some embodiments.

The formation of the source/drain features136N and136P includes recessing the fin structures120P,120N,122P and122N using the dummy gate structure128and gate spacer layers134as an etching mask to form source/drain recesses at the source/drain regions, in accordance with some embodiments. The bottom surfaces of the source/drain recesses may extend to a position lower than the top surface126T of the isolation structure126, For example, the bottom surfaces of the source/drain recesses are substantially level with the bottom surface118A1of the top fin element118A, in accordance with some embodiments.

Afterward, the source/drain features136N and136P are grown on the fin structures120P,1201,122P and122N in the source/drain recesses using epitaxial growth processes, in accordance with some embodiments. The epitaxial growth process may be MBE, MOCVD, or VPE, or another suitable technique. The source/drain features136P abut the top fin element118A of the fin structure120P and the top fin element118B of the fin structure122P, in accordance with sonic embodiments. The source/drain features136N abut the top fin element108A of the fin structure120N and the top fin element108B of the fin structure122N, in accordance with some embodiments.

In some embodiments, the n-type source/drain features136N and the p-type source/drain features136P are formed separately. For example, a patterned mask layer (such as a photoresist layer and/or hard mask layer) may be formed to cover the semiconductor structure over the n-type wells104N and106N, and then the n-type source/drain features136N are grown. Afterward, the patterned mask layer may be removed.

Similarly, in some embodiments, a patterned mask layer (such as a photoresist layer and/or hard mask layer) is formed to cover the semiconductor structure over the p-type wells104P and106P, and then the p-type source/drain features136P are grown. Afterward, the patterned mask layer may be removed.

In some embodiments, the source/drain features136N and136P are in-situ doped during the epitaxial processes. In some embodiments, the respective concentrations of the dopant in the source/drain features136N and136P are in a range from about 1×1018cm−3to about 1×1022cm−3.

In some embodiments, the n-type source/drain features136N are doped with the n-type dopant during the epitaxial growth process. For example, the n-type dopant may be phosphorous (P) or arsenic (As). For example, the n-type source/drain features136N may be the epitaxially grown Si doped with phosphorous to form silicon:phosphor (Si:P) source/drain features and/or arsenic to form silicon:arsenic (Si:As) source/drain feature.

In some embodiments, the p-type source/drain features136P are doped with the p-type dopant during the epitaxial growth process. For example, the p-type dopant may be boron (B) or BF2. For example, the p-type source/drain features136P may be the epitaxially grown SiGe doped with boron (B) to form silicon germanium:boron (SiGe:B) source/drain feature. In some embodiments, the n-type source/drain features136N and the p-type source/drain features136P are made of different epitaxial materials. For example, the n-type source/drain features136N are made of SiP, and the p-type source/drain features136P are made of SiGe.

A contact etching stop layer138is formed over the semiconductor structure to cover the source/drain features136N and136P, as shown inFIG.2J-2, in accordance with some embodiments. In some embodiments, the contact etching stop layer138is made of dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), oxygen-doped silicon carbide (SiC:O), oxygen-doped silicon carbonitride (Si(O)CN), or a combination thereof. In some embodiments, a dielectric material for the contact etching stop layer138is globally and conformally deposited using CVD (such as LPCVD, PECVD, HDP-CVD, or HARP). ALD, another suitable method, or a combination thereof.

An interlayer dielectric layer140over the contact etching stop layer138, as shown inFIG.23-2, in accordance with some embodiments. In some embodiments, the interlayer dielectric layer140is made of dielectric material, such as un-doped silicate glass (USG), or doped silicon oxide such as borophosphosilicate glass (BPSG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and/or another suitable dielectric material. In some embodiments, the interlayer dielectric layer140and the contact etching stop layer138are made of different materials and have a great difference in etching selectivity.

In some embodiments, the dielectric material for the interlayerdielectric layer140is deposited using such as CVD (such as HDP-CVD, PECVD, HARP or FCVD), another suitable technique, and/or a combination thereof. The dielectric materials for the contact etching stop layer138and the interlayer dielectric layer140above the upper surface of the dummy gate structures128A and128B are removed using such as CMP, in accordance with some embodiments.

FIGS.2K-Iand2K-2illustrate a semiconductor structure after the formation of gate trenches142A and142B, in accordance with some embodiments.

The dummy gate structures128A and128B are removed using one or more etching processes to form gate trenches142A and142B, as shown inFIGS.2K-1and2K-2, in accordance with some embodiments. The semiconductor capping layer124is exposed from the dummy gate structures128A and128B, in accordance with some embodiments. The dummy gate structures128A and128B also expose the top surface1261of the isolation structure126, in accordance with some embodiments. The dummy gate structures128A and128B also expose the sidewalls of the gate spacer layers134facing the channel regions, in accordance with some embodiments.

In some embodiments, the etching process includes one or more etching processes. For example, when the dummy gate electrode layer132is made of polysilicon, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution may be used to selectively remove the dummy gate electrode layer132. For example, the dummy gate dielectric layer132may be thereafter removed using a plasma dry etching, a dry chemical etching, and/or a wet etching.

FIGS.2L-1and2L-2illustrate a semiconductor structure after the formation of final gate stacks144A and144B, in accordance with some embodiments.

Final gate stacks144A and144B are formed in the gate trenches142A and142B, as shown in F1Gs.2L-1and2L-2, in accordance with some embodiments. The final gate stack144A is formed in the logic area50A and extends across and surrounds the channel regions of the fin structures120P and120N, in accordance with some embodiments. The final gate stack144B is formed in the memory cell array area50B and extends across and surrounds the channel regions of the fin structures122P and122N, in accordance with sonic embodiments.

In some embodiments, the final gate stacks144A and144B extend in the Y direction. That is, the final gate stacks144A and144B have longitudinal axes parallel to the Y direction, in accordance with some embodiments. The final gate stacks144A and144B may be a single, continuous gate stack; or may be spaced apart from one another by another isolation feature.

In some embodiments, each of the final gate stacks144A and144B includes a gate dielectric layer146and a gate electrode layer148formed over the gate dielectric layer146, as shown inFIGS.2L-1and2L-2, in accordance with some embodiments. The gate dielectric layer146is formed to partially fill the gate trenches142A and142B, in accordance with some embodiments. In some embodiments, the gate dielectric layer146may be an I/O (input/output) oxide which is made of silicon oxide.

In some embodiments, the gate dielectric layer146may include an interfacial layer and a high-k dielectric layer formed over the interfacial layer. The interfacial layer may be made of a chemically formed silicon oxide by one or more cleaning processes such as including ozone (O3), ammonia hydroxide-hydrogen peroxide-water mixture, and/or hydrochloric acid-hydrogen peroxide-water mixture.

In some embodiments, the high-k dielectric layer is made of dielectric material with high dielectric constant (k value), for example, greater than 3.9. In some embodiments, the high-k dielectric layer includes hafnium oxide (HfO2), TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Y2O3, SrTiO3(STO), BaTiO3(BTO), BaZrO, HfSiO, LaSiO, AlSiO, HfTaO, HMO, (Ba,Sr)TiO3(BST), Al2O3, oxynitrides (SiON), a combination thereof, or another suitable material. The high-k dielectric layer may be deposited using ALD, PVD, CVD, and/or another suitable technique.

The metal gate electrode layer148is formed to fill remainders of the gate trenches142A and142B, in accordance with some embodiments. In some embodiments, the metal gate electrode layer148is made of more than one conductive material, such as a metal, metal alloy, conductive metal oxide and/or metal nitride, another suitable conductive material, and/or a combination thereof. For example, the metal gate electrode layer148may be made of Ti, Ag, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, Cu, W, Re, Co. Ni, another suitable conductive material, or multilayers thereof.

The metal gate electrode layer148may be a multi-layer structure with various combinations of a diffusion barrier layer, work function layers with a selected work function to enhance the device performance (e.g., threshold voltage) for n-channel FETs or p-channel FETs, a capping layer to prevent oxidation of work function layers, a glue layer to adhere work function layers to a next layer, and a metal fill layer to reduce the total resistance of gate stacks, and/or another suitable layer. The metal gate electrode layer148may be formed using AID, PVD, CVD, e-beam evaporation, or another suitable technique. The metal gate electrode layer148may be formed separately for n-channel FinFETs and p-channel FinFETs, which may use different work function materials.

A planarization process such as CMP may be performed on the semiconductor structure to remove the materials of the gate dielectric layer146and the metal gate electrode layer148formed above the upper surface of the interlayer dielectric layer140, in accordance with some embodiments. After the planarization process, the top surfaces of the metal gate electrode layer148, the gate spacer layers134, the contact etching stop layer138and the interlayer dielectric layer140are substantially coplanar, in accordance with some embodiments.

The top fin element118A of the fin structure120P extends downward beyond the final gate stack144A, as shown inFIG.2L-1, in accordance with some embodiments. In specific, the gate dielectric layer146has a vertical portion extending along the sidewall of the top fin element118A, and the bottom146A1of the vertical portion of the gate dielectric layer146is located at a higher position than the bottom surface118A1of the top fin element118A, in accordance with some embodiments.

The top fin element118B of the fin structure122P is encapsulated in the final gate stack144B, as shown inFIG.2L-1, in accordance with some embodiments. In specific, the gate dielectric layer146has a vertical portion extending along the sidewall of the top fin element118B, and the bottom146B1of the vertical portion of the gate dielectric layer146is located at a lower position than the bottom surface118B1of the top fin element118B, in accordance with some embodiments.

In the logic area50A, a portion of the final gate stack144A surrounding the fin structure120P combines with the neighboring source/drain features136P to form a p-channel FinFET, in accordance with some embodiments. The top fin element118A of the fin structure120P serves as the channel (e.g., SiGe channel) of the p-channel FinFET, and the final gate stack144A engages the channel so that current can flow between the source/drain features136P during operation.

In the logic area50A, a portion of the final gate stack144A surrounding the fin structure120N combines with the neighboring source/drain features136N to form an n-channel FinFET, in accordance with sonic embodiments. The top fin element108A of the fin structure120N serves as the channel (e.g., Si channel) of the n-channel FinFET, and the final gate stack144A engages the channel so that current can flow between the source/drain features136N during operation.

In the memory cell array area50B, a portion of the final gate stack144B surrounding the fin structure122P combines with the neighboring source/drain features136P to form a p-channel FinFET, in accordance with some embodiments. The top fin element118B of the fin structure122P serves as the channel (e.g., SiGe channel) of the p-channel FinFET, and the final gate stack144B engages the channel so that current can flow between the source/drain features136P during operation. In some embodiments where SRAM cells are formed in the memory cell array area50B, the p-channel FinFET is used as a pull-up transistor of the SRAM cells.

In the memory cell array area50B, a portion of the final gate stack144B surrounding the fin structure122N combines with the neighboring source/drain features136N to form an n-channel FinFET, in accordance with some embodiments. The top fin element108B of the fin structure122N serves as the channel (e.g., Si channel) of the n-channel FinFET, and the final gate stack144B engages the channel so that current can flow between the source/drain features136N during operation. In some embodiments where SRAM cells are formed in the memory cell array area50B, the n-channel FinFET is used as a pull-down transistor and/or a pass-gate transistor of the SRAM cells.

In accordance with embodiments of the present disclosure, the top fin element118A of the fin structure120P, which serves as the channel of the p-type FinFET in the logic area50A, extends downward beyond the final gate stack144A, thereby providing a relatively large area of the channel, which may provide benefits, e.g., one or more of (1) greater On-current (Ion), (2) greater drain current in linear region (Id), (3) lower channel resistance (RCH), and (4) lower parasitic capacitance. Thus, the performance of the resulting logic device may be enhanced.

In addition, in accordance with embodiments of the present disclosure, because the top fin element118B of the fin structure122P, which serves as the channel of the p-type FinFET (e.g., pull-up transistor for an SRAM cell) in the memory cell array area50B, is encapsulated in the final gate stack144B, the final gate stack144E can have better control over the channel, especially for the bottom portion of the top fin element118B, which may provide benefits, e.g., improving in SCE and/or DIBL. Thus, the performance of the resulting SRAM device may be enhanced.

Furthermore, the respective performances of the resulting logic device and the resulting SRAM device may be fine-tuned by adjusting the position of the top surface126T of the isolation structure126. For example, when the performance of the logic device is more of a concern than the SRAM device, the top surface1261of the isolation structure126may be adjusted to a higher position (e.g., farther away from the bottom surface of the118A1), For example, when the performance of the SRAM device is more of a concern than the logic device, the top surface126T of the isolation structure126may be adjusted to a lower position (e.g., farther away from the bottom surface of the118B1), Therefore, the embodiments of the present disclosure may provide great flexibility in turning the respective performances of the logic p-channel device and SRAM p-channel device.

It should be understood that the semiconductor structure of EEGs.2L-1and2L-2may undergo further CMOS processes to form various features over the semiconductor structure, such as a multilayer interconnect structure (e.g., contact plugs to final gate stacks, contact plugs to source/drain features, conductive vias, metal lines, inter metal dielectric lavers, passivation layers, etc.). In some embodiments, the logic device formed in the logic area50A inay be electrically connected to the memory device formed in the memory cell array area50B through the conductive features of the multilayer interconnect structure.

FIG.3is a modification ofFIG.2L-1, in accordance with some embodiments of the disclosure. The semiconductor structure ofFIG.3is similar to the semiconductor structure ofFIG.2L-1, except that the fin structure120P shown inFIG.3has no middle fin elements.

In some embodiments, the portion108C (FIG.2E) of the semiconductor material108may be entirely removed in the etching process described above inFIG.2E(i.e., D5is zero). The fin structure120P includes the bottom fin element formed from the n-type well104, and the top fin element118A on and in contact with the bottom fin element, as shown inFIG.3, in accordance with some embodiments.

FIGS.4A and48are cross-sectional views illustrating the formation of a semiconductor structure at various intermediate stages, in accordance with some embodiments of the disclosure.FIGS.4A and4Bcorrespond to the cross-sections Y1-Y1and Y2-Y2of FIG. I. The embodiments ofFIGS.4A and48are similar to the embodiments ofFIGS.2A through2L-2, except that the top surface of the isolation structure126shown inFIGS.4A and4Bis curved.

Continuing fromFIGS.2I-1and2I-2, the dielectric material for the isolation structure126is recessed to expose the sidewalls of the fin structures120P,120N,122P and122P, in accordance with some embodiments. Due to the characteristic of the etching process, the top surface of the isolation structure126is curved, e.g., concave, as shown inFIG.4A, in accordance with some embodiments.

In some embodiments, the side surface of the isolation structure126facing the fin structure120P has a top126T1, and the top126T1of the isolation structure126is located at a higher position than the bottom surface118A1of the top fin element118A of the fin structure120P, as shown inFIG.4A. In some embodiments, the lowest point126L of the curved top surface of the isolation structure126may be located at a lower position than the bottom surface118A1of the top fin element118A of the fin structure120P.

In sonic embodiments, the side surface of the isolation structure126facing the fin structure122P has a top126T2, and the top126T2of the isolation structure126is located at a lower position than the bottom surface118B1of the top fin element118B of the fin structure122P, as shown inFIG.4A, in accordance with some embodiments.

In some embodiments, the top126T1is spaced apart from the bottom surface118A1by a distance D10in a range from about 1 nm to about 12 nm, and the top12672is spaced apart from the bottom surface118B1by a distance D11in a range from about nm to about 12 nm. The distance D10may be greater than, equal to, or less than the distance D11. In some embodiments, the position of the top12611and the position of126T2of the isolation structure126may be adjusted in accordance with the respective performances of the logic p-channel device and SRAM p-channel device.

The steps described above with respect toFIGS.2J.-1through2L-2are performed, thereby forming the gate spacer layers134, the source/drain features136N and136P, the contact etching stop layer138, the interlayer dielectric layer140, and the final gate stacks144A and144B, as shown inFIG.4B, in accordance with some embodiments.

The top fin element118A of the fin structure120P extends downward beyond the final gate stack144A, in accordance with some embodiments. The gate dielectric layer146has a vertical portion extending along the sidewall of the top fin element118A, and the bottom146A1of the vertical portion of the gate dielectric layer146is located at a higher position than the bottom surface118A1of the top fin element118A, in accordance with some embodiments. In some embodiments, the lowest point of the gate dielectric layer146may be located at a lower position than the bottom surface118A1of the top fin element118A of the fin structure120P.

The top fin element118B of the fin structure122P is encapsulated in the final gate stack144B, in accordance with some embodiments. In specific, the gate dielectric layer146has a vertical portion extending along the sidewall of the top fin element118B, and the bottom146131of the vertical portion of the gate dielectric layer146is located at a lower position than the bottom surface118B1of the top fin element118B, in accordance with some embodiments.

FIGS.5A,5B,5C,5D,5E, and5Fare cross-sectional views illustrating the formation of a semiconductor structure at various intermediate stages, in accordance with some embodiments of the disclosure.FIGS.5A-5Fcorrespond to the cross-sections Y1-Y1and Y2-Y2ofFIG.1. The embodiments ofFIGS.5A-5Fare similar to the embodiments ofFIGS.2A through2L-2, except the logic area50A is a pattern loose area and the memory cell array area50B is a pattern dense area.

Continuing fromFIG.2A, the n-type well104N and the p-type well104P are formed in the logic area50A, while the n-type well106N and the p-type well106P are formed in the memory cell array area50B, in accordance with some embodiments. In some embodiments, the logic area50A is a pattern loose area and the memory cell array area50B is a pattern dense area.

In some embodiments, the width W1(in the Y direction) of the n-type well104N is greater than the width W2(in the Y direction) of the n-type well106N, as shown inFIG.5A. In sonic embodiments, the width (in the Y direction) of the p-type well104P is greater than the width (in the Y direction) of the p-type well106P. In some embodiments, the pitch P1(in the Y direction) of the n-type well104N (or the p-type well104P) is greater than the pitch P2(in the Y direction) of the n-type well106N (or the p-type well106P).

The steps described above with respect toFIG.2Bare performed, thereby forming the semiconductor material108, the dielectric layer110and the patterned mask layer112, as shown inFIG.5B, in accordance with some embodiments. The patterned mask layer112vertically covers and/or overlaps the p-type wells104P and106P, in accordance with some embodiments. In some embodiments, the trench pattern of the patterned mask layer112in the memory cell array area50B has a great density than the trench pattern in the logic area50A.

The etching process described above inFIG.2Cis performed to etch away portions of the dielectric layer110and the semiconductor material108uncovered by the patterned mask layer112, as shown inFIG.5C, in accordance with some embodiments. The trench patterns of the patterned mask layer112are transferred to the semiconductor material108, thereby forming trenches114A′ in the logic area50A and trenches114B in the memory cell area50B, in accordance with some embodiments.

Due to the etching loading effect, the etching amount in the logic area50A which has a relatively low pattern density is greater than the etching amount in the memory cell array area50B which has a relatively high pattern density, in accordance with some embodiments. As a result, the trench114A′ is deeper than the trench114B, in accordance with some embodiments.

In some embodiments, the trench114A′ has an etching depth D3in a range from about 27.5 nm to about 165 nm. In some embodiments, the trench114A′ is deeper than the trench114B by the dimension D4. In some embodiments, the dimension D4is in a range from about 2.5 nm to about 15 nm.

In some embodiments, the portion108C of the semiconductor material108directly above the n-type well104N has a thickness D5. In some embodiments, the thickness D5is in a range from about 1 nm to about 35 nm. In some embodiments, the portion108D of the semiconductor material108directly above the n-type well106N is thicker than the portion108C of the semiconductor material108and has a thickness D6. In some embodiments, the thickness D6is in a range from about 2.5 nm to about 50 nm.

Therefore, by designing different areas of the substrate102with different pattern densities to adjust the etching depth, one photolithography process and one etching process for ecessing the portion108C of the semiconductor material108may be omitted, in accordance with some embodiments.

The steps described above with respect to FIGs. and2G are performed, thereby forming the semiconductor material118(including118A and118B) in the trenches114′ and trenches114B, as shown inFIG.6D, in accordance with some embodiments.

The steps described above with respect toFIGS.2H-1and2H-2are performed, thereby forming the fin structures120P,120N,122P and122N, as shown inFIG.5E, in accordance with some embodiments.

The steps described above with respect toFIGS.2I-1through2L-2are performed, thereby forming the isolation structure126, the gate spacer layers134, the source/drain features136N and136P, the contact etching stop layer138, the interlayer dielectric layer140, and the final gate stacks144A and144B, as shownFIG.5F, in accordance with some embodiments.

In accordance with embodiments of the present disclosure, the top fin element118A of the fin structure120P, which serves as the channel of the p-type FinFET in the logic area50A, extends downward beyond the final gate stack144A, thereby providing a relatively large area of the channel. Thus, the performance of the resulting logic device may be enhanced.

In addition, in accordance with embodiments of the present disclosure, because the top fin element118B of the fin structure122P, which serves as the channel of the p-type FinFET (e.g., pull-up transistor for an SRAM cell) in the memory cell array area50B, is encapsulated in the final gate stack144B, the final gate stack144B can have better control over the channel, especially for the bottom portion of the top fin element118B. Thus, the performance of the resulting SRAM device may be enhanced.

As described above, the aspect of the present disclosure is directed to forming p-channel devices in a logic area and a memory cell array area having respective enhancing performances. In some embodiments, logic devices may focus more on high on-current, while memory devices (e.g., SRAM) may focus more on improvement in SCE. The top fin element118A of the fin structure120P for logic devices is formed with a greater thickness than the top fin element118B of the fin structure122P for memory devices, in accordance with some embodiments. Therefore, the top fin element118A may provide a relatively large area of the channel, which enhance the performance of the resulting logic device. Furthermore, the final gate stack144B can have better control over the top fin element118B, which may enhance the performance of the resulting SRAM device.

Embodiments of a method for forming a semiconductor structure are provided. The method for forming the semiconductor structure may include recessing a first semiconductor material to form a first trench in a logic area and a second trench in a memory cell array area, forming a second semiconductor material in the first trench and the second trench, and patterning the second semiconductor material in the first trench to form first fin structure in the logic area and patterning the second semiconductor material in the second trench to form second fin structure in the memory cell array area. The first trench may be deeper than the second trench, and thus the second semiconductor material of the first fin structure is thicker than the second semiconductor material of the second fin structure. Therefore, the logic device formed on the first fin structure may have an enhanced performance (e.g., greater on-current), while the memory device formed on the second fin structure may have an enhanced performance (e.g., improvement in SCE).

In some embodiments, a method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming a first semiconductor material over a substrate, and forming a first trench and a second trench in the first semiconductor material. The first trench is deeper than the second trench. The method also includes forming a second semiconductor material in the first trench and the second trench, patterning a first portion of the second semiconductor material in the first trench and a first portion of the first semiconductor material below the first portion of the second semiconductor material into a first fin structure, and patterning a second portion of the second semiconductor material in the second trench and a second portion of the first semiconductor material below the second portion of the second semiconductor material into a second fin structure. The method also includes forming an isolation structure over the substrate to surround the first fin structure and the second fin structure.

In some embodiments, a method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming a first n-type well, a p-type well, and a second n-type well in a substrate, and forming a first semiconductor material over the substrate. A first portion of the first semiconductor material directly above the first n-type well is thinner than a second portion of the first semiconductor material directly above the second n-type well. The second portion of the first semiconductor material is thinner than a third portion of the first semiconductor material directly above the p-type well. The method also includes forming a second semiconductor material over the first portion and the second portion of the first semiconductor material, etching the second semiconductor material and the first semiconductor material to form a first fin structure over the first n-type well, a second fin structure over the p-type well, and a third fin structure over the second n-type well, and forming a dummy gate structure across the first fin structure, the second fin structure, and the third fin structure.

In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a first fin structure over a substrate, and the first fin structure includes a first middle fin element and a first top fin element over the first middle fin element and with a different composition than the first middle fin element. The semiconductor structure also includes a first gate dielectric layer surrounding the first fin structure. The semiconductor structure also includes a second fin structure over the substrate, and the second fin structure includes a second middle fin element and a second top fin element over the second middle fin element and with a different composition than the second middle fin element. The first top fin element is thicker than the second top fin element. The semiconductor structure also includes a second dielectric layer surrounding the second fin structure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various chanes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.