Patent ID: 12223886

DETAILED DESCRIPTION

Details of objects and technical configurations of the present disclosure, and functions and effects thereof will be clarified through the following detailed description given with reference to the accompanying drawings illustrating embodiments of the present disclosure. Here, embodiments of the present disclosure are provided so that the present disclosure may be sufficiently thorough and complete to assist those skilled in the art in fully understanding the scope of the present disclosure. Therefore, the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein.

Throughout the specification, elements designated by the same reference numerals represent the same constituent elements. In the drawings, the length and thickness of each layer or region may be exaggerated for convenience. In addition, it will be understood that the case in which a first element is referred to as being “on” a second constituent element includes not only the case in which the first constituent element is disposed on the second constituent element such that the first constituent element directly contacts the second constituent element, but also the case in which a third constituent element is interposed between the first constituent element and the second constituent element.

It will be understood that although the terms “first,” “second,” or the like are used herein to describe various constituent elements, these terms are only used to distinguish one constituent element from another constituent element. Of course, the first constituent element and the second constituent element may be optionally named in accordance with convenience of those skilled in the art.

The terminology used in the specification of the present disclosure is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. For example, a constituent element expressed in the singular form is intended to include a plurality of constituent elements, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising” or “having” when used in the specification of the present disclosure specify the presence of stated features, integers, steps, operations, elements, components or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Unless otherwise defined, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Embodiments

FIG.1is a diagram schematically showing a display apparatus according to an embodiment of the present disclosure.FIG.2is a circuit diagram showing a circuit in a unit pixel area in the display apparatus according to the embodiment of the present disclosure.

Referring toFIGS.1and2, the display apparatus according to the embodiment of the present disclosure may include a display panel DP. The display panel DP may produce an image to be provided to a user. For example, the display panel DP may include a plurality of pixel areas PA.

Various signals may be provided to each pixel area PA through signal lines GL1, GL2, DL, EM1, EM2, PL, and RL. For example, the signal lines GL1, GL2, DL, EM1, EM2, PL, and RL may include gate lines GL1and GL2each configured to apply a gate signal to each pixel area PA, data lines DL each configured to apply a data signal to each pixel area PA, emission control lines EM1and EM2each configured to apply an emission control signal to each pixel area PA, supply voltage supply lines PL each configured to supply a positive supply voltage VDD to each pixel area PA, and reference voltage supply lines RL each configured to supply a reference voltage to each pixel area PA. The gate lines GL1and GL2and the emission control lines EM1and EM2may be electrically connected to a gate driver GD. The data lines DL may be electrically connected to a data driver DD. The supply voltage supply lines PL and the reference voltage supply lines RL may be electrically connected to a power unit PU.

The gate driver GD and the data driver DD may be controlled by a timing controller TC. For example, the gate driver GD may receive clock signals, reset signals, and a start signal from the timing controller TC, and the data driver DD may receive digital video data and a source timing signal from the timing controller TC.

Each pixel area PA may render a particular color. For example, a light emitting device500and a pixel driving circuit DC electrically connected to the light emitting device500may be disposed in each pixel area PA. The pixel driving circuit DC of each pixel area PA may generate drive current corresponding to the data signal DL in accordance with the gate signals GL1and GL2. For example, the pixel driving circuit DC of each pixel area PA may include a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, and a storage capacitor Cst.

FIG.3is a view schematically showing a layout of the third thin film transistor T3disposed in each pixel area PA in the display apparatus according to the embodiment of the present disclosure.FIG.4is a view schematically showing a cross-section taken along line I-I′ inFIG.1and a cross-section of each pixel area PA.FIG.5is a view showing cross-sections taken along lines II-II′ and III-III′ inFIG.3.

Referring toFIGS.1to5, in each pixel driving circuit DC of the display apparatus according to the embodiment of the present disclosure, the first thin film transistor T1may be electrically connected between a data line DL and a third node N3. For example, the first thin film transistor T1may electrically connect the third node N3 to the data line DL in accordance with a second gate signal applied thereto through a second gate line GL2. The first thin film transistor T1is turned on by the second gate signal and, as such, may transmit, to the third node N3, a data signal applied thereto through the data line DL. For example, the first thin film transistor T1may be a switching thin film transistor.

The first thin film transistor T1may include a first semiconductor pattern211, a first gate electrode213, a first drain electrode215, and a first source electrode217. For example, the first gate electrode213of the first thin film transistor T1may be electrically connected to the second gate line GL2, the first drain electrode215of the first thin film transistor T1may be electrically connected to the data line DL, and the first source electrode217of the first thin film transistor T1may be electrically connected to the third node N3.

The first semiconductor pattern211may include a semiconductor material. For example, the first semiconductor pattern211may include an oxide semiconductor such as IGZO. The first semiconductor pattern211may include a first channel region, a first drain region, and a first source region. The first channel region may be disposed between the first drain region and the first source region. The resistance of the first drain region and the resistance of the first source region may be smaller than the resistance of the first channel region. For example, each of the first drain region and the first source region may include a region, treated to have conductivity, of an oxide semiconductor. The first channel region may be a region, not treated to have conductivity, of an oxide semiconductor.

The first gate electrode213may include a conductive material. For example, the first gate electrode213may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The first gate electrode213may be disposed on the first semiconductor pattern211. For example, the first gate electrode213may overlap with the first channel region of the first semiconductor pattern211. The first drain region and the first source region of the first semiconductor pattern211may be disposed outside the first gate electrode213. The first gate electrode213may be insulated from the first semiconductor pattern211. For example, the first source region may be electrically connected to the first drain region by a signal applied to the first gate electrode213.

The first drain electrode215may include a conductive material. For example, the first drain electrode215may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The first drain electrode215may include a material different from that of the first gate electrode213. The first drain electrode215may be disposed on a layer different from that of the first gate electrode213. For example, the first drain electrode215may be insulated from the first gate electrode213. The first drain electrode215may be electrically connected to the first drain region of the first semiconductor pattern211.

The first source electrode217may include a conductive material. For example, the first source electrode217may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The first source electrode217may include a material different from that of the first gate electrode213. The first source electrode217may be disposed on a layer different from that of the first gate electrode213. For example, the first source electrode217may be disposed on the same layer as the first drain electrode215. The first source electrode217may include the same material as that of the first drain electrode215. The first source electrode217may be insulated from the first gate electrode213. For example, the first source electrode217may be electrically connected to the first source region of the first semiconductor pattern211.

In each pixel driving circuit DC of the display apparatus according to the embodiment of the present disclosure, the second thin film transistor T2may be electrically connected between a second node N2 and the third node N3. The second thin film transistor T2may include a second semiconductor pattern221, a second gate electrode223, a second drain electrode225, and a second source electrode227. For example, the second gate electrode223may be electrically connected to a first node N1, the second drain electrode225may be electrically connected to the third node N3, and the second source electrode227may be electrically connected to the second node N2. The second thin film transistor T2may generate drive current corresponding to a data signal applied to the third node N3. For example, the second thin film transistor T2may be a driving thin film transistor.

The second semiconductor pattern221may include a semiconductor material. For example, the second semiconductor pattern221may include an oxide semiconductor such as IGZO. The second semiconductor pattern221may include a second channel region disposed between a second drain region and a second source region. The second channel region may have a greater resistance than those of the second drain region and the second source region. For example, each of the second drain region and the second source region may include a region, treated to have conductivity, of an oxide semiconductor, and the second channel region may be a region, not treated to have conductivity, of an oxide semiconductor.

The second semiconductor pattern221may be disposed on the same layer as the first semiconductor pattern211. The second semiconductor pattern221may include the same material as that of the first semiconductor pattern211. For example, the second semiconductor pattern221may be formed concurrently (or in some cases, simultaneously) with the first semiconductor pattern211. The second drain region and the second source region of the second semiconductor pattern221may have the same resistance as that of the first drain region and the first source region. For example, the resistance of the second channel region may be equal to the resistance of the first channel region.

The second gate electrode223may include a conductive material. For example, the second gate electrode223may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The second gate electrode223may include the same material as that of the first gate electrode213. The second gate electrode223may be disposed on the same layer as the first gate electrode213. For example, the second gate electrode223may be formed concurrently (or in some cases, simultaneously) with the first gate electrode213.

The second gate electrode223may be disposed on the second semiconductor pattern221. For example, the second gate electrode223may overlap with the second channel region of the second semiconductor pattern221. The second drain region and the second source region of the second semiconductor pattern221may be disposed outside the second gate electrode223. The second gate electrode223may be insulated from the second semiconductor pattern221. For example, the second channel region of the second semiconductor pattern221may have electrical conductivity corresponding to a voltage applied to the second gate electrode223.

The second drain electrode225may include a conductive material. For example, the second drain electrode225may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The second drain electrode225may include a material different from that of the second gate electrode223. The second drain electrode225may be disposed on a layer different from that of the second gate electrode223. For example, the second drain electrode225may be insulated from the second gate electrode223. The second drain electrode225may be electrically connected to the second drain region of the second semiconductor pattern221.

The second drain electrode225may be disposed on the same layer as the first drain electrode215. The second drain electrode225may include the same material as that of the first drain electrode215. For example, the second drain electrode225may be formed concurrently (or in some cases, simultaneously) with the first drain electrode215.

The second source electrode227may include a conductive material. For example, the second source electrode227may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The second source electrode227may include a material different from that of the second gate electrode223. The second source electrode227may be disposed on a layer different from that of the second gate electrode223. For example, the second source electrode227may be insulated from the second gate electrode223. The second source electrode227may be electrically connected to the second source region of the second semiconductor pattern221.

The second source electrode227may be disposed on the same layer as the first source electrode217. The second source electrode227may include the same material as that of the first source electrode217. For example, the second source electrode227may be formed concurrently (or in some cases, simultaneously) with the first source electrode217.

In each pixel driving circuit DC of the display apparatus according to the embodiment of the present disclosure, the third thin film transistor T3may be electrically connected between the first node N1 and the second node N2. For example, the third thin film transistor T3may electrically connect the second node N2 to the first node N1 in accordance with a first gate signal applied thereto through a first gate line GL1. The third thin film transistor T3may be a switching thin film transistor. The third thin film transistor T3may have the same structure as that of the first thin film transistor T1. For example, the third thin film transistor T3may include a third semiconductor pattern231, a third gate electrode233, a third drain electrode235, and a third source electrode237. The third gate electrode233may be electrically connected to the first gate line GL1, the third drain electrode235may be electrically connected to the first node N1, and the third source electrode237may be electrically connected to the second node N2.

The second thin film transistor T2may be switched to a diode connection state in accordance with turn-on of the third thin film transistor T3. For example, the third thin film transistor T3may be a sampling thin film transistor electrically connected between the second gate electrode223and the second source electrode227of the second thin film transistor T2which is a driving thin film transistor.

The third semiconductor pattern231may include a semiconductor material. For example, the third semiconductor pattern231may include an oxide semiconductor such as IGZO. The third semiconductor pattern231may include a third channel region, a third drain region, and a third source region. The third channel region may be disposed between the third drain region and the third source region. The resistance of the third drain region and the resistance of the third source region may be smaller than the resistance of the third channel region. For example, each of the third drain region and the third source region may include a region, treated to have conductivity, of an oxide semiconductor, and the third channel region may be a region, not treated to have conductivity, of an oxide semiconductor.

The third semiconductor pattern231may be disposed on the same layer as the first semiconductor pattern211. The third semiconductor pattern231may include the same material as that of the first semiconductor pattern211. For example, the third semiconductor pattern231may be formed concurrently (or in some cases, simultaneously) with the first semiconductor pattern211. The third drain region and the third source region of the third semiconductor pattern231may have the same resistance as that of the first drain region and the first source region of the first semiconductor pattern211. For example, the resistance of the third channel region may be equal to the resistance of the first channel region.

The third gate electrode233may include a conductive material. For example, the third gate electrode233may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The third gate electrode233may include the same material as that of the first gate electrode213. The third gate electrode233may be disposed on the same layer as the first gate electrode213. For example, the third gate electrode233may be formed concurrently (or in some cases, simultaneously) with the first gate electrode213.

The third gate electrode233may be disposed on the third semiconductor pattern231. For example, the third gate electrode233may overlap with the third channel region of the third semiconductor pattern231. The third drain region and the third source region of the third semiconductor pattern231may be disposed outside the third gate electrode233. The third gate electrode233may be insulated from the third semiconductor pattern231. For example, the third source region may be electrically connected to the third drain region in accordance with a signal applied to the third gate electrode233.

The third drain electrode235may include a conductive material. For example, the third drain electrode235may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The third drain electrode235may include a material different from that of the third gate electrode233. The third drain electrode235may be disposed on a layer different from that of the third gate electrode233. For example, the third drain electrode235may be insulated from the third gate electrode233. The third drain electrode235may be electrically connected to the third drain region of the third semiconductor pattern231.

The third drain electrode235may be disposed on the same layer as the first drain electrode215. The third drain electrode225may include the same material as that of the first drain electrode215. For example, the third drain electrode225may be formed concurrently (or in some cases, simultaneously) with the first drain electrode215.

The third source electrode237may include a conductive material. For example, the third source electrode237may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The third source electrode237may include a material different from that of the third gate electrode233. The third source electrode237may be disposed on a layer different from that of the third gate electrode233. For example, the third source electrode237may be disposed on the same layer as the third drain electrode235. The third source electrode237may include the same material as that of the third drain electrode235. The third source electrode237may be insulated from the third gate electrode233. For example, the third source electrode237may be electrically connected to the third source region of the third semiconductor pattern231.

The third source electrode237may be disposed on the same layer as the first source electrode217. The third source electrode237may include the same material as that of the first source electrode217. For example, the third source electrode237may be formed concurrently (or in some cases, simultaneously) with the first source electrode217.

In each pixel driving circuit DC of the display apparatus according to the embodiment of the present disclosure, the fourth thin film transistor T4may be electrically connected between a supply voltage supply line PL and the second node N2. For example, the fourth thin film transistor T4may electrically connect the supply voltage supply line PL to the second node N2 in accordance with a first emission signal applied thereto through a first emission control line EM1. The fourth thin film transistor T4may be turned on in accordance with the first emission signal, thereby supplying, to the second node N2, a positive supply voltage VDD applied thereto through the supply voltage supply line PL. For example, the fourth thin film transistor T4may be a switching thin film transistor.

The fourth thin film transistor T4may have the same structure as that of the first thin film transistor T1. For example, the fourth thin film transistor T4may include a fourth semiconductor pattern, a fourth gate electrode, a fourth drain electrode, and a fourth source electrode. The fourth gate electrode may be electrically connected to the first emission control line EM1, the fourth drain electrode may be electrically connected to the second node N2, and the fourth source electrode may be electrically connected to the supply voltage supply line PL.

The fourth thin film transistor T4may be formed concurrently (or in some cases, simultaneously) with the first thin film transistor T1. For example, the fourth semiconductor pattern may be disposed on the same layer as the first semiconductor pattern211, the fourth gate electrode may be disposed on the same layer as the first gate electrode213, and the fourth drain electrode and the fourth source electrode may be disposed on the same layer as the first drain electrode215and the first source electrode217. The fourth semiconductor pattern may include the same material as that of the first semiconductor pattern211, the fourth gate electrode may include the same material as that of the first gate electrode213, and the fourth drain electrode and the fourth source electrode may include the same material as that of the first drain electrode215and the first source electrode217.

In each pixel driving circuit DC of the display apparatus according to the embodiment of the present disclosure, the fifth thin film transistor T5may be electrically connected between the third node N3 and a fifth node N5. For example, the fifth thin film transistor T5may electrically connect the third node N3 to the fifth node N5 in accordance with a second emission signal applied thereto through a second emission control line EM2. The fifth thin film transistor T5may be turned on in accordance with the second emission signal, thereby supplying, to the fifth node N5, the drive current generated by the second thin film transistor T2. For example, the fifth thin film transistor T5may be a switching thin film transistor.

The fifth thin film transistor T5may have the same structure as that of the first thin film transistor T1. For example, the fifth thin film transistor T5may include a fifth semiconductor pattern, a fifth gate electrode, a fifth drain electrode, and a fifth source electrode. The fifth gate electrode may be electrically connected to the second emission control line EM2, the fifth drain electrode may be electrically connected to the fifth node N5, and the fifth source electrode may be electrically connected to the third node N3.

The fifth thin film transistor T5may be formed concurrently (or in some cases, simultaneously) with the first thin film transistor T1. For example, the fifth semiconductor pattern may be disposed on the same layer as the first semiconductor pattern211, the fifth gate electrode may be disposed on the same layer as the first gate electrode213, and the fifth drain electrode and the fifth source electrode may be disposed on the same layer as the first drain electrode215and the first source electrode217. The fifth semiconductor pattern may include the same material as that of the first semiconductor pattern211, the fifth gate electrode may include the same material as that of the first gate electrode213, and the fifth drain electrode and the fifth source electrode may include the same material as that of the first drain electrode215and the first source electrode217.

In each pixel driving circuit DC of the display apparatus according to the embodiment of the present disclosure, the sixth thin film transistor T6may be electrically connected between a reference voltage supply line RL and a fourth node N4. The sixth thin film transistor T6may have the same structure as that of the first thin film transistor T1. For example, the sixth thin film transistor T6may include a sixth semiconductor pattern, a sixth gate electrode, a sixth drain electrode, and a sixth source electrode. The sixth thin film transistor T6may be turned on/off concurrently (or in some cases, simultaneously) with the third thin film transistor T3. For example, the sixth gate electrode may be electrically connected to the first gate line GL1, the sixth drain electrode may be electrically connected to the fourth node N4, and the sixth source electrode may be electrically connected to the reference voltage supply line RL. The sixth thin film transistor T6may electrically connect the reference voltage supply line RL to the fourth node N4 in accordance with the first gate signal. For example, the sixth thin film transistor T6may be turned on by the first gate signal, thereby transmitting, to the fourth node N4, a reference voltage applied thereto through the reference voltage supply line RL. The sixth thin film transistor T6may be a switching thin film transistor.

The fourth thin film transistor T4may be turned on by a signal applied thereto through the first emission control line EM1, thereby supplying, to the second node N2, the positive supply voltage VDD applied thereto through the supply voltage supply line PL. The fifth thin film transistor T5may be turned on by a signal applied thereto through the second emission control line EM2, thereby supplying, to the fifth node N5, the drive current generated by the second thin film transistor T2. The sixth thin film transistor T6may be turned on by a signal applied thereto through the first gate line GL1, thereby supplying, to the fourth node N4, the reference voltage applied thereto through the reference voltage supply line RL. For example, the sixth thin film transistor T6may be turned on/off concurrently (or in some cases, simultaneously) with the third thin film transistor T3.

The sixth thin film transistor T6may be formed concurrently (or in some cases, simultaneously) with the first thin film transistor T1. For example, the sixth semiconductor pattern may be disposed on the same layer as the first semiconductor pattern211, the sixth gate electrode may be disposed on the same layer as the first gate electrode213, and the sixth drain electrode and the sixth source electrode may be disposed on the same layer as the first drain electrode215and the first source electrode217. The sixth semiconductor pattern may include the same material as that of the first semiconductor pattern211, the sixth gate electrode may include the same material as that of the first gate electrode213, and the sixth drain electrode and the sixth source electrode may include the same material as that of the first drain electrode215and the first source electrode217.

In each pixel driving circuit DC of the display apparatus according to the embodiment of the present disclosure, the storage capacitor Cst may be electrically connected between the first node N1 and the fourth node N4. For example, a signal applied to the second gate electrode223of the second thin film transistor T2may be maintained for one frame by the storage capacitor Cst. The fourth node N4 may be electrically connected to the fifth node N5. For example, the storage capacitor Cst may be electrically connected between the second gate electrode223of the second thin film transistor T2and the fifth drain electrode of the fifth thin film transistor T5.

The storage capacitor Cst may have a stack structure of capacitor electrodes. The storage capacitor Cst may be formed using formation processes for the thin film transistors T1, T2, T3, T4, T5, and T6. For example, the storage capacitor Cst may include a first capacitor electrode formed concurrently (or in some cases, simultaneously) with the second gate electrode223, and a second capacitor electrode formed concurrently (or in some cases, simultaneously) with the second drain electrode225. The first capacitor electrode may include the same material as that of the second gate electrode223. The first capacitor electrode may be disposed on the same layer as the second gate electrode223. The second capacitor electrode may include the same material as that of the second drain electrode225. The second capacitor electrode may be disposed on the same layer as the second drain electrode225.

In the display apparatus according to the embodiment of the present disclosure, one frame may include an initialization period, a sampling period, and an emission period. In the initialization period, only the third thin film transistor T3, the fourth thin film transistor T4, and the sixth thin film transistor T6may be turned on and, as such, the positive supply voltage VDD may be applied to the first node N1 and the second node N2, and the reference voltage may be applied to the fourth node N4. That is, in the display apparatus according to the embodiment of the present disclosure, the storage capacitor Cst may be initialized during the initialization period.

In the sampling period, only the first thin film transistor T1, the third thin film transistor T3, and the sixth thin film transistor T6may be turned on and, as such, the second thin film transistor T2may be switched to a diode connection state, and the data signal may be applied to the third node N3. The voltage of the data signal may be lower than a value obtained by deducting a threshold voltage Vth of the second thin film transistor T2from the positive supply voltage VDD. In the display apparatus according to the embodiment of the present disclosure, accordingly, the first node N1 may have a potential equal to a value obtained by summing the threshold voltage Vth of the second thin film transistor T2and the data signal during the sampling period. In the display apparatus according to the embodiment of the present disclosure, accordingly, during the sampling period, the second thin film transistor T2may be turned on and, as such, current may flow between the second drain electrode225and the second source electrode227of the second thin film transistor T2. That is, in the display apparatus according to the embodiment of the present disclosure, drive current corresponding to the data signal may be generated by the second thin film transistor T2during the sampling period. In addition, in the display apparatus according to the embodiment of the present disclosure, a voltage value corresponding to the data signal may be stored in the storage capacitor Cst during the sampling period.

In the emission period, only the fourth thin film transistor T4and the fifth thin film transistor T5are turned on and, as such, the positive supply voltage VDD may be applied to the second node N2, and the third node N3 may be electrically connected to the fifth node N5. In the display apparatus according to the embodiment of the present disclosure, accordingly, the drive current generated by the second thin film transistor T2may be supplied to the fifth node N5 during the emission period.

The pixel driving circuit DC of each pixel area PA may be disposed on a device substrate100. The device substrate100may include an insulating material. For example, the device substrate100may include glass or plastic.

The display panel DP may include an active area AA where the pixel areas PA are disposed, and a bezel area BZ disposed outside the active area AA. At least one of the gate driver GD, the data driver DD, the power unit PU or the timing controller TC may be disposed on the bezel area BZ. For example, the display apparatus according to the embodiment of the present disclosure may be a gate-in-panel type display apparatus in which the gate driver GD is formed on the bezel area BZ of the display panel DP. The gate driver GD may include at least one circuit thin film transistor290disposed on the bezel area BZ of the device substrate100.

The circuit thin film transistor290may selectively rapidly transmit a particular signal. For example, the circuit thin film transistor290may be a switching thin film transistor. The circuit thin film transistor290may have the same structure as that of the first thin film transistor T1. For example, the circuit thin film transistor290may include a circuit semiconductor pattern291, a circuit gate electrode293, a circuit drain electrode295, and a circuit source electrode297.

The circuit semiconductor pattern291may include a semiconductor material. The circuit semiconductor pattern291may include a material different from that of the first semiconductor pattern211of each pixel area PA. For example, the circuit semiconductor pattern291may include low-temperature poly-Si (LTPS). The circuit semiconductor pattern291may be disposed on a layer different from that of the first semiconductor pattern211. For example, the circuit semiconductor pattern291may have electrical characteristics different from those of the first semiconductor pattern211of each pixel area PA.

The circuit semiconductor pattern291may include a circuit channel region, a circuit drain region, and a circuit source region. The circuit channel region may be disposed between the circuit drain region and the circuit source region. The resistance of the circuit drain region and the resistance of the circuit source region may be smaller than the resistance of the circuit channel region. For example, the circuit drain region and the circuit source region may include a conductive impurity. The circuit channel region may be a region not doped with a conductive impurity.

The circuit gate electrode293may include a conductive material. For example, the circuit gate electrode293may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The circuit gate electrode293may be disposed on the circuit semiconductor pattern291. For example, the circuit gate electrode293may overlap with the circuit channel region of the circuit semiconductor pattern291. The circuit drain region and the circuit source region of the circuit semiconductor pattern291may be disposed outside the circuit gate electrode293. The circuit gate electrode293may be insulated from the circuit semiconductor pattern291. For example, the circuit source region may be electrically connected to the circuit drain region by a signal applied to the circuit gate electrode293.

The circuit gate electrode293may be disposed on a layer different from that of the first gate electrode213. For example, the circuit gate electrode293may include a material different from that of the first gate electrode213of each pixel area PA. The circuit gate electrode293may be formed by a process different from that of the first gate electrode213of each pixel area PA.

The circuit drain electrode295may include a conductive material. For example, the circuit drain electrode295may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The circuit drain electrode295may include a material different from that of the circuit gate electrode293. The circuit drain electrode295may be disposed on a layer different from that of the circuit gate electrode293. For example, the circuit drain electrode295may be insulated from the circuit gate electrode293. The circuit drain electrode295may be electrically connected to the circuit drain region of the circuit semiconductor pattern291.

The circuit drain electrode295may be disposed on the same layer as the first drain electrode215of each pixel area PA. The circuit drain electrode295may include the same material as that of the first drain electrode215of each pixel area PA. For example, the circuit drain electrode295may be formed concurrently (or in some cases, simultaneously) with the first drain electrode215of each pixel area PA.

The circuit source electrode297may include a conductive material. For example, the circuit source electrode297may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The circuit source electrode297may include a material different from that of the circuit gate electrode293. The circuit source electrode297may be disposed on a layer different from that of the circuit gate electrode293. For example, the circuit source electrode297may be disposed on the same layer as the circuit drain electrode295. The circuit source electrode297may include the same material as that of the circuit drain electrode295. The circuit source electrode297may be insulated from the circuit gate electrode293. For example, the circuit source electrode297may be electrically connected to the circuit source region of the circuit semiconductor pattern291.

The circuit source electrode297may be disposed on the same layer as the first source electrode217of each pixel area PA. The circuit source electrode297may include the same material as that of the first source electrode217. For example, the circuit source electrode297may be formed concurrently (or in some cases, simultaneously) with the first source electrode217of each pixel area PA.

A plurality of insulating layers110,120,130,140,150,160,170,180, and190configured to prevent unnecessary electrical connection in the display panel DP may be disposed on the device substrate100. For example, a lower buffer layer110, a lower gate insulating layer120, a lower interlayer insulating layer130, an upper buffer layer140, an upper gate insulating layer150, an upper interlayer insulating layer160, a first planarization layer170, a second planarization layer180, and a bank insulating layer190may be disposed on the device substrate100.

The lower buffer layer110may be disposed near the device substrate100. The lower buffer layer110may prevent contamination caused by the device substrate100in a process of forming the circuit thin film transistor290and the pixel driving circuit DC of each pixel area PA. For example, the lower buffer layer110may completely cover the active area AA and the bezel area BZ of the device substrate100. The circuit thin film transistor290and the pixel driving circuit DC of each pixel area PA may be disposed on the lower buffer layer110. The lower buffer layer110may include an insulating material. For example, the lower buffer layer110may include an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx). The lower buffer layer110may have a multilayer structure. For example, the lower buffer layer110may have a stack structure constituted by an inorganic insulating layer made of silicon oxide (SiOx) and an inorganic insulating layer made of silicon nitride (SiNx).

The lower gate insulating layer120may insulate the circuit semiconductor pattern291and the circuit gate electrode293of the circuit thin film transistor290from each other. For example, the circuit semiconductor pattern291may be disposed between the lower buffer layer110and the lower gate insulating layer120. The lower gate insulating layer120may cover the circuit semiconductor pattern291. The lower gate insulating layer120may extend onto the active area AA of the device substrate100. For example, the thin film transistors T1, T2, T3, T4, T5, and T6of each pixel area PA may be disposed on the lower gate insulating layer120. The lower gate insulating layer120may include an insulating material. For example, the lower gate insulating layer120may include an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).

The lower interlayer insulating layer130may insulate the circuit drain electrode295and the circuit source electrode297from the circuit gate electrode291. For example, the circuit gate electrode291may be disposed between the lower gate insulating layer120and the lower interlayer insulating layer130, and the circuit drain electrode295and the circuit source electrode297may be disposed on the lower interlayer insulating layer130. The lower interlayer insulating layer130may extend onto the active area AA of the device substrate100. For example, the thin film transistors T1, T2, T3, T4, T5, and T6of each pixel area PA may be disposed on the lower interlayer insulating layer130. The lower interlayer insulating layer130may include an insulating material. For example, the lower interlayer insulating layer130may include an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).

The upper buffer layer140may be disposed between the lower interlayer insulating layer130and the thin film transistors T1, T2, T3, T4, T5, and T6of each pixel area PA. For example, the semiconductor patterns211,221, and231of each pixel area PA may be disposed on the upper buffer layer140. In the display apparatus according to the embodiment of the present disclosure, accordingly, damage to the semiconductor patterns211,221,231disposed in each pixel area PA, which is caused by formation processes for the circuit semiconductor pattern291and the circuit gate electrode293, may be prevented. For example, the thickness of the upper buffer layer140may be greater than the thickness of the lower interlayer insulating layer130. The upper buffer layer140may include an insulating material. The upper buffer layer140may include a material having a relatively low hydrogen content. For example, the upper buffer layer140may be an inorganic insulating layer made of silicon oxide (SiOx). In the display apparatus according to the embodiment of the present disclosure, accordingly, a variation in characteristics of the semiconductor patterns211,221, and231disposed in each pixel area PA, which is caused by diffusion of hydrogen, may be prevented. That is, in the display apparatus according to the embodiment of the present disclosure, degradation of characteristics of each pixel driving circuit DC caused by hydrogen may be prevented.

The upper gate insulating layer150may insulate the semiconductor patterns211,221, and231and the gate electrodes213,223,233in each pixel area PA from each other. For example, the first semiconductor pattern211, the second semiconductor pattern221, the third semiconductor pattern231, the fourth semiconductor pattern, the fifth semiconductor pattern, and the sixth semiconductor pattern of each pixel area PA may be disposed between the upper buffer layer140and the upper gate insulating layer150. The upper gate insulating layer150may cover the first semiconductor pattern211, the second semiconductor pattern221, the third semiconductor pattern231, the fourth semiconductor pattern, the fifth semiconductor pattern, and the sixth semiconductor pattern of each pixel area PA. For example, the first gate electrode213, the second gate electrode223, the third gate electrode233, the fourth gate electrode, the fifth gate electrode, and the sixth gate electrode of each pixel area PA may be disposed on the upper gate insulating layer150. The upper gate insulating layer150may extend onto the bezel area BZ of the device substrate100. For example, the circuit drain electrode295and the circuit source electrode297may be disposed on the upper gate insulating layer150of the bezel area BZ. The upper gate insulating layer150may include an insulating material. For example, the upper gate insulating layer150may be an inorganic insulating layer made of silicon oxide (SiOx).

Distances between corresponding ones of the semiconductor patterns211,221, and231and the gate electrodes213,223, and233may be equal. For example, the upper gate insulating layer150may directly contact the semiconductor patterns211,221, and231and the gate electrodes213,223, and233of each pixel area PA. In the display apparatus according to the embodiment of the present disclosure, accordingly, the formation process for the pixel driving circuit DC disposed in each pixel area PA may be simplified.

The upper interlayer insulating layer160may insulate the drain electrodes215,225, and235and the source electrodes217,227, and237disposed in each pixel area PA from corresponding ones of the gate electrodes213,223, and233disposed in each pixel area PA. For example, the gate electrodes213,223, and233of each pixel area PA may be disposed between the upper gate insulating layer150and the upper interlayer insulating layer160, and the drain electrodes215,225, and235and the source electrodes217,227, and237of each pixel area PA may be disposed on the upper interlayer insulating layer160. The drain electrodes215,225, and235and the source electrodes217,227, and237of each pixel area PA may be electrically connected to corresponding ones of the semiconductor patterns211,221, and231, respectively, while extending through the upper gate insulating layer150and the upper interlayer insulating layer160. The upper interlayer insulating layer160may extend onto the bezel area BZ of the device substrate100. For example, the circuit drain electrode295and the circuit source electrode297may be disposed on the upper interlayer insulating layer160. The circuit drain electrode295and the circuit source electrode297may be electrically connected to the circuit semiconductor pattern291while extending through the lower gate insulating layer120, the lower interlayer insulating layer130, the upper buffer layer140, the upper gate insulating layer150, and the upper interlayer insulating layer160.

The upper interlayer insulating layer160may include an insulating material. The upper interlayer insulating layer160may include a material different from that of the lower interlayer insulating layer130. The upper interlayer insulating layer160may include a material having a relatively low hydrogen content. For example, the upper interlayer insulating layer160may be an inorganic insulating layer made of silicon oxide (SiOx). In the display apparatus according to the embodiment of the present disclosure, accordingly, a variation in characteristics of the thin film transistors T1, T2, T3, T4, T5, and T6disposed in each pixel area PA, which is caused by hydrogen, may be prevented.

The first planarization layer170may be disposed on the upper interlayer insulating layer160. For example, the drain electrodes215,225, and235and the source electrodes217,227, and237of each pixel area PA may be covered by the first planarization layer170. The circuit drain electrode295and the circuit drain electrode297may be disposed between the upper interlayer insulating layer160and the first planarization layer170. The second planarization layer180may be disposed on the first planarization layer170. The first planarization layer170and the second planarization layer180may remove a step formed by the circuit thin film transistor290and the pixel driving circuit DC of each pixel area PA. For example, an upper surface of the second planarization layer180opposite to the device substrate100may be a flat surface.

The first planarization layer170and the second planarization layer180may include an insulating material. The first planarization layer170and the second planarization layer180may include a material different from that of the upper interlayer insulating layer160. For example, each of the first planarization layer170and the second planarization layer180may be an organic insulating layer made of an organic insulating material. The second planarization layer180may include the same material as that of the first planarization layer170. The second planarization layer180may directly contact the first planarization layer170. For example, a boundary surface between the first planarization layer170and the second planarization layer180may not be recognized.

The light emitting device500of each pixel area PA may be disposed on the second planarization layer180. The light emitting device500of each pixel area PA may emit light representing a particular color. For example, the light emitting device500of each pixel area PA may include a first electrode510, an emission layer520, and a second electrode530sequentially stacked on the second planarization layer180of the pixel area PA.

The first electrode510may include a conductive material. The first electrode510may include a material having high reflectivity. For example, the first electrode510may include a metal such as aluminum (Al) or silver (Ag). The first electrode510may have a multilayer structure. For example, the first electrode510may have a structure in which a reflective electrode made of a metal is disposed between transparent electrodes made of a transparent conductive material such as ITO or IZO.

The emission layer520may generate light having a luminance corresponding to a voltage difference between the first electrode510and the second electrode530. For example, the emission layer520may include an emission material layer (EML) including an emission material. The emission material may include an organic material, an inorganic material, or a hybrid material. For example, the display apparatus according to the embodiment of the present disclosure may be an organic light emitting display apparatus including an organic emission material.

The emission layer520may have a multilayer structure. For example, the emission layer520may further include at least one of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), or an electron injection layer (EIL). In the display apparatus according to the embodiment of the present disclosure, accordingly, the emission efficiency of the emission layer520may be enhanced.

The second electrode530may include a conductive material. The second electrode530may include a material different from that of the first electrode510. The transmittance of the second electrode530may be greater than the transmittance of the first electrode510. For example, the second electrode530may be a transparent electrode made of a transparent conductive material such as ITO or IZO. In the display apparatus according to the embodiment of the present disclosure, accordingly, light generated by the emission layer520may be outwardly emitted through the second electrode530.

The first electrode510of each pixel area PA may directly contact the upper surface of the second planarization layer180. In the display apparatus according to the embodiment of the present disclosure, accordingly, luminance deviation according to different generation positions of light emitted from respective light emitting devices500may be avoided.

The first electrode510of each light emitting device500may be electrically connected to the pixel driving circuit DC of the pixel area PA corresponding thereto. For example, the first electrode500of each pixel area PA may be electrically connected to the fifth node N5 of the pixel driving circuit DC disposed in the pixel area PA. In the display apparatus according to the embodiment of the present disclosure, accordingly, the drive current generated by the pixel driving circuit DC of each pixel area PA may be supplied to the light emitting device500of the pixel area PA for one frame.

Intermediate electrodes400may be disposed between the first planarization layer170and the second planarization layer180. The intermediate electrodes140may include a conductive material. For example, the intermediate electrodes400may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The first electrode510of each pixel area PA may be electrically connected to the pixel driving circuit DC of the pixel area PA via one of the intermediate electrodes400. For example, each intermediate electrode400may be electrically connected to the fifth node N5 of one of the pixel areas PA while extending through the first planarization layer170, and the first electrode510of each pixel area PA may directly contact one of the intermediate electrodes400while extending through the second planarization layer180of the pixel area PA. In the display apparatus according to the embodiment of the present disclosure, accordingly, the process of interconnecting the pixel driving circuit DC and the light emitting device500disposed in each pixel area PA may be simplified.

The bank insulating layer190may be disposed on the second planarization layer180. The bank insulating layer190may insulate the first electrode510of each pixel area PA from the first electrode510of another pixel area PA adjacent to the former pixel area PA. For example, an edge of the first electrode510disposed in each pixel area PA may be covered by the bank insulating layer190. The emission layer520and the second electrode530of each pixel area PA may be sequentially stacked on a portion of the corresponding first electrode510exposed by the bank insulating layer190. For example, the bank insulating layer190may define an emission area in each pixel area PA. The bank insulating layer190may include an insulating material. For example, the bank insulating layer190may include an organic insulating material. The bank insulating layer190may include a material different from that of the second planarization layer180.

Light emitted from the light emitting device500of each pixel area PA may represent a color different from that of light emitted from the light emitting device500of another pixel area PA adjacent to the former pixel area PA. For example, the emission layer520of each pixel area PA may include a material different from that of the emission layer520of the adjacent pixel area PA. The emission layer520disposed in each pixel area PA may include an end disposed on the bank insulating layer190. The emission layer520of each pixel area PA may be individually formed. For example, the emission layer520of each pixel area PA may be formed using a fine metal mask (FMM). A spacer may be disposed on the bank insulating layer190. The spacer may prevent damage to the bank insulating layer190and the emission layer520caused by the fine metal mask. The spacer may include an insulating material. For example, the spacer may include an organic insulating material. The spacer may include the same material as that of the bank insulating layer190. For example, the bank insulating layer190and the spacer may be concurrently (or in some cases, simultaneously) formed by a patterning process using a halftone mask. The end of the emission layer520disposed in each pixel area PA may be spaced apart from the spacer.

A voltage applied to the second electrode530of each pixel area PA may be identical to a voltage applied to the second electrode530of the adjacent pixel area PA. For example, a negative supply voltage VSS may be applied to the second electrode530of each pixel area PA. The second electrode530of each pixel area PA may be electrically connected to the second electrode530of the adjacent pixel area PA. The second electrode530of each pixel area PA may include the same material as that of the second electrode530of the adjacent pixel area PA. For example, the second electrode530of each pixel area PA may be formed concurrently (or in some cases, simultaneously) with the second electrode530of the adjacent pixel area PA. The second electrode530of each pixel area PA may directly contact the second electrode530of the adjacent pixel area PA. The second electrode530of each pixel area PA may extend onto the bank insulating layer190. The bank insulating layer190may be covered by the second electrode530. In the display apparatus according to the embodiment of the present disclosure, accordingly, the process of forming the second electrode530disposed in each pixel area PA may be simplified. In addition, in the display apparatus according to the embodiment of the present disclosure, it may be possible to adjust the luminance of light emitted from the light emitting device500of each pixel area PA by the data signal applied to the pixel driving circuit DC of the pixel area PA.

An encapsulation unit600may be disposed on the light emitting device500of each pixel area PA. The encapsulation unit600may prevent damage to the light emitting devices500caused by ambient moisture and external impact. The encapsulation unit600may extend onto the bezel area BZ of the device substrate100. The encapsulation unit600may include a multilayer structure. For example, the encapsulation unit600may include a first encapsulation layer610, a second encapsulation layer620, and a third encapsulation layer630sequentially stacked on the device substrate100. The first encapsulation layer610, the second encapsulation layer620, and the third encapsulation layer630may include an insulating material. The second encapsulation layer620may include a material different from those of the first encapsulation layer610and the third encapsulation layer630. For example, each of the first encapsulation layer610and the third encapsulation layer630may be an inorganic insulating layer made of an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), whereas the second encapsulation layer620may be an organic insulating layer made of an organic insulating material. Steps formed by the light emitting devices500may be controlled by the second encapsulation layer620. In the display apparatus according to the embodiment of the present disclosure, accordingly, damage to the light emitting devices500caused by ambient moisture and external impact may be effectively prevented.

Light shielding patterns310,320, and330may be disposed on each pixel area PA of the device substrate100. Each of the light shielding patterns310,320, and330may shield light advancing toward the semiconductor pattern211,221, or231of one of the thin film transistors T1. T2, T3, T4, T5, and T6disposed in the pixel area PA corresponding to the light shielding pattern310,320, or330after passing through the device substrate100. For example, the light shielding patterns310,320, and330of each pixel area PA may include a first light shielding pattern310overlapping with the first semiconductor pattern211of the pixel area PA, a second light shielding pattern320overlapping with the second semiconductor pattern221of the pixel area PA, a third light shielding pattern330overlapping with the third semiconductor pattern231of the pixel area PA, a fourth light shielding pattern overlapping with the fourth semiconductor pattern of the pixel area PA, a fifth light shielding pattern overlapping with the fifth semiconductor pattern of the pixel area PA, and a sixth light shielding pattern overlapping with the sixth semiconductor pattern of the pixel area PA.

The first light shielding pattern310may be disposed between the device substrate100and the first semiconductor pattern211. The first light shielding pattern310may include a material capable of reflecting light. For example, the first light shielding pattern310may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The first light shielding pattern310may be electrically connected to the first gate electrode213. For example, the first light shielding pattern310may function as a dummy gate electrode of the first thin film transistor T1.

The first light shielding pattern310may be disposed on the same layer as the circuit gate electrode293. The first light shielding pattern310may include the same material as that of the circuit gate electrode293. The first light shielding pattern310may be formed concurrently (or in some cases, simultaneously) with the circuit gate electrode293. For example, the first light shielding pattern310may be disposed between the lower gate insulating layer120and the lower interlayer insulating layer130. In the display apparatus according to the embodiment of the present disclosure, accordingly, the process of forming the first light shielding pattern310may be simplified.

The second light shielding pattern320may be disposed between the device substrate100and the second semiconductor pattern221. The second light shielding pattern320may include a material capable of reflecting light. For example, the second light shielding pattern320may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). A specific voltage may be applied to the second light shielding pattern320. For example, the second light shielding pattern320may be electrically connected to the second source electrode227. In the display apparatus according to the embodiment of the present disclosure, accordingly, a variation in characteristics of the second thin film transistor T2caused by external light may be effectively prevented.

The second light shielding pattern320may include a material different from that of the first light shielding pattern310. The second light shielding pattern320may be disposed on a layer different from that of the first light shielding pattern310. The vertical distance between the second light shielding pattern320and the second semiconductor pattern221may be smaller than the vertical distance between the first light shielding pattern310and the first semiconductor pattern211. For example, the second light shielding pattern320may be disposed between the lower interlayer insulating layer130and the upper buffer layer140. The first light shielding pattern310may be disposed nearer to the device substrate100than the second light shielding pattern320. In the display apparatus according to the embodiment of the present disclosure, accordingly, a parasitic capacitor formed between the second light shielding pattern320and the second semiconductor pattern221of each pixel area PA may have a greater capacitance than that of a parasitic capacitor formed between the first light shielding pattern310and the first semiconductor pattern211.

Generally, a variation in an effective gate voltage of each thin film transistor may be determined by the following expression. In the following expression, ΔVeffmeans a variation in the effective gate voltage, ΔVGATmeans a variation in a voltage applied to a gate electrode of the thin film transistor, C1means a capacitance of a parasitic capacitor formed between a semiconductor pattern of the thin film transistor and a light shielding pattern disposed under the semiconductor pattern, C2means a capacitance of a parasitic capacitor formed between the semiconductor pattern and the gate electrode, and CACTmeans a capacitance of a parasitic capacitor formed by voltages applied to a source region and a drain region of the semiconductor pattern.

Δ⁢Veff=C⁢2C⁢2+CA⁢C⁢T+C⁢1×Δ⁢VG⁢A⁢T[Expression]

The capacitance of a capacitor is inversely proportional to the distance between conductors constituting the capacitor. That is, in the display apparatus according to the embodiment of the present disclosure, the variation in the effective gate voltage of the second thin film transistor T2may be lower than the variation in the effective gate voltage of the first thin film transistor T1. Generally, when the variation in the effective gate voltage of a thin film transistor decreases, an s-factor meaning an inverse ratio of a current variation according to a variation in a voltage applied to a gate electrode of the thin film transistor is increased. In the display apparatus according to the embodiment of the present disclosure, accordingly, the second thin film transistor T2may have a relatively great s-factor and, as such, a variation in the drive current generated by the second thin film transistor T2, which is caused by a voltage applied to the second gate electrode223, may be reduced. In the display apparatus according to the embodiment of the present disclosure, accordingly, generation of mura defect at low gray levels may be prevented.

The third light shielding pattern330may be disposed between the device substrate100and the third semiconductor pattern231. The third light shielding pattern330may include a material capable of reflecting light. For example, the third light shielding pattern330may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The third light shielding pattern330may be electrically connected to the third gate electrode233. For example, the third light shielding pattern330may function as a dummy gate electrode of the third thin film transistor T3.

The third light shielding pattern330may be formed concurrently (or in some cases, simultaneously) with the first light shielding pattern310. For example, the third light shielding pattern330may include the same material as that of the first light shielding pattern310. In the display apparatus according to the embodiment of the present disclosure, accordingly, an enhancement in process efficiency may be achieved.

The third semiconductor pattern231may include a region disposed between the third light shielding pattern330and the third gate electrode233. For example, the third gate electrode233may extend across the third channel region of the third semiconductor pattern231in a width direction of the third semiconductor pattern231, and the third light shielding pattern330may extend in parallel to the third gate electrode233. A cross-section of the third light shielding pattern330in the width direction of the third semiconductor pattern231may have a concave shape. For example, a lower hole LH may be disposed between the device substrate100and the third channel region of the third semiconductor pattern231, and a side wall and a bottom surface of the lower hole LH may be covered by the third light shielding pattern330. For example, the lower hole LH may extend through the lower buffer layer110and the lower gate insulating layer120. The third light shielding pattern330may extend along the side wall and the bottom surface of the lower hole LH. For example, the third light shielding pattern330may directly contact the device substrate100within the lower hole LH. An end of the third light shielding pattern330may be disposed between the lower gate insulating layer120and the lower interlayer insulating layer130.

The third channel region of the third semiconductor pattern231may overlap with a concave portion of the third light shielding pattern330. Due to a step formed by the lower hole LH, a portion of the third gate electrode233overlapping with the third channel region of the third semiconductor pattern231may be disposed relatively near the device substrate100. For example, a cross-section of the third gate electrode233in the width direction of the third semiconductor pattern231may have a concave shape. In the display apparatus according to the embodiment of the present disclosure, accordingly, light L1reflected from the end of the third light shielding pattern330may be reflected in an outward direction of the third semiconductor pattern231by the concave shape of the third gate electrode233. In the display apparatus according to the embodiment of the present disclosure, accordingly, the light L1, which is inwardly reflected, is prevented from being introduced into the third channel region of the third semiconductor pattern231. That is, in the display apparatus according to the embodiment of the present disclosure, accordingly, a variation in characteristics of the third thin film transistor T3caused by the inwardly-reflected light may be prevented.

The fourth light shielding pattern may be disposed between the device substrate100and the fourth semiconductor pattern. The fifth light shielding pattern may be disposed between the device substrate100and the fifth semiconductor pattern. The sixth light shielding pattern may be disposed between the device substrate100and the sixth semiconductor pattern. The fourth light shielding pattern, the fifth light shielding pattern, and the sixth light shielding pattern may include a material capable of reflecting light. For example, the fourth light shielding pattern, the fifth light shielding pattern, and the sixth light shielding pattern may include a metal such as aluminum (Al), chromium (Cr), copper (Cu), molybdenum (Mo), titanium (Ti), and tungsten (W). The fourth light shielding pattern, the fifth light shielding pattern, and the sixth light shielding pattern may be disposed on the same layer as the first light shielding pattern310. For example, the fourth light shielding pattern, the fifth light shielding pattern, and the sixth light shielding pattern may be disposed between the lower gate insulating layer120and the lower interlayer insulating layer130. The fourth light shielding pattern, the fifth light shielding pattern, and the sixth light shielding pattern may include the same material as that of the first light shielding pattern310. For example, the fourth light shielding pattern, the fifth light shielding pattern, and the sixth light shielding pattern may be formed concurrently (or in some cases, simultaneously) with the first light shielding pattern310. In the display apparatus according to the embodiment of the present disclosure, accordingly, an enhancement in process efficiency may be achieved.

The fourth light shielding pattern may be electrically connected to the fourth gate electrode. For example, the fourth light shielding pattern may function as a dummy gate electrode of the fourth thin film transistor T4. The fifth light shielding pattern may be electrically connected to the fifth gate electrode. For example, the fifth light shielding pattern may function as a dummy gate electrode of the fifth thin film transistor T5. The sixth light shielding pattern may be electrically connected to the sixth gate electrode. For example, the sixth light shielding pattern may function as a dummy gate electrode of the sixth thin film transistor T6. In the display apparatus according to the embodiment of the present disclosure, accordingly, the efficiency of the pixel driving circuit DC disposed in each pixel area PA may be enhanced.

As apparent from the above description, the display apparatus according to the embodiment of the present disclosure may include the light emitting device500and the pixel driving circuit DC disposed in each pixel area PA, wherein the pixel driving circuit DC may include the second thin film transistor T2, which is a driving thin film transistor, and the third thin film transistor T3, which is a sampling thin film transistor, wherein the third thin film transistor T3may include the third semiconductor pattern231disposed on the third light shielding pattern330, and the third gate electrode233disposed on the third semiconductor pattern231, and wherein cross-sections of the third light shielding pattern330and the third gate electrode233in the width direction of the third semiconductor pattern231may have a concave shape. In the display apparatus according to the embodiment of the present disclosure, accordingly, a variation in characteristics of the third thin film transistor T3disposed in each pixel area PA, which is caused by inwardly-reflected light, may be prevented. In the display apparatus according to the embodiment of the present disclosure, accordingly, degradation of image quality caused by deviations in characteristics of the second thin film transistor T2disposed in each pixel area PA may be prevented.

In the display apparatus according to the embodiment of the present disclosure, the pixel driving circuit DC of each pixel area PA has been described as including the six thin film transistors T1, T2, T3, T4, T5, and T6. In a display apparatus according to another embodiment of the present disclosure, however, the pixel driving circuit DC of each pixel area PA may include one driving thin film transistor and a plurality of switching thin film transistors, wherein one of the switching thin film transistors may be a sampling thin film transistor electrically connected between a driving gate electrode and a driving source electrode of the driving thin film transistor. In the display apparatus according to the other embodiment of the present disclosure, accordingly, freedom of the configuration of each pixel driving circuit DC may be enhanced.

In the display apparatus according to the embodiment of the present disclosure, the lower hole LH has been described as extending through the lower buffer layer110and the lower gate insulating layer120. In a display apparatus according to another embodiment of the present disclosure, however, the lower hole LH may extend through one of the lower buffer layer110and the lower gate insulating layer120. For example, in the display apparatus according to the other embodiment of the present disclosure, the lower hole LH may extend through the lower buffer layer110, and the lower gate insulating layer120may extend along the side wall and the bottom surface of the lower hole LH. In the display apparatus according to the other embodiment of the present disclosure, accordingly, freedom of the process of forming the lower hole LH may be enhanced.

In the display apparatus according to the embodiment of the present disclosure, the third light shielding pattern330and the third gate electrode233, which extend across the third channel region between the third drain region and the third source region, have been described as having cross-sections having a concave shape in a width direction of the third semiconductor pattern231. In a display apparatus according to another embodiment of the present disclosure, however, light advancing toward the third channel region of the third semiconductor pattern231may be shielded by the third gate electrode233, without formation of the lower hole LH. For example, as shown inFIGS.6and7, in the display apparatus according to the other embodiment of the present disclosure, a light shielding trench PT, which extends through the upper gate insulating layer150, may be disposed on a first side surface S1of the third semiconductor pattern231, and the third gate electrode233may include a central region233adisposed on the third channel region of the third semiconductor pattern231, and a first electrode region233bcovering a side wall and a bottom surface of the light shielding trench PT. The light shielding trench PT may extend in a longitudinal direction of the third semiconductor pattern231. For example, the light shielding trench PT may be disposed in parallel to the first side surface S1of the third channel region. The first electrode region233bmay extend onto the first side surface S1of the third channel region within the light shielding trench PT. In the display apparatus according to the other embodiment of the present disclosure, accordingly, light L2reflected from the end of the third light shielding pattern330may be reflected in the outward direction of the third semiconductor pattern231by the first electrode region233bof the third gate electrode233. In the display apparatus according to the other embodiment of the present disclosure, accordingly, a variation in characteristics of the third thin film transistor T3caused by the inwardly-reflected light may be prevented by the first electrode region233bof the third gate electrode233.

The minimum distance between the device substrate100and the first electrode region233bmay be smaller than the minimum distance between the device substrate100and the third semiconductor pattern231. For example, the light shielding trench PT may partially extend through the upper buffer layer140. The bottom surface of the light shielding trench PT may be disposed nearer to the device substrate100than an upper surface of the upper buffer layer140. In the display apparatus according to the other embodiment of the present disclosure, accordingly, light advancing toward the third channel region of the third semiconductor pattern231by inward reflection may be effectively shielded. The third gate electrode233may be electrically connected to the third light shielding pattern330on a second side surface S2opposite to the first side surface S1of the third semiconductor pattern231. For example, the cross-section of the third gate electrode233in the width direction of the third semiconductor pattern231may have a concave shape with reference to the third semiconductor pattern231. In the display apparatus according to the other embodiment of the present disclosure, accordingly, a variation in characteristics of the third thin film transistor T3caused by the inwardly-reflected light may be effectively prevented.

In a display apparatus according to another embodiment of the present disclosure, the first electrode region233bmay be electrically connected to the third light shielding pattern330. For example, as shown inFIG.8, in the display apparatus according to the other embodiment of the present disclosure, the light shielding trench PT may extend through the lower interlayer insulating layer130, the upper buffer layer140, and the upper gate insulating layer150, and the first electrode region233bmay directly contact the third light shielding pattern330within the light shielding trench PT. In the display apparatus according to the other embodiment of the present disclosure, accordingly, the third gate electrode233may be stably connected to the third light shielding pattern330. In addition, in the display apparatus according to the other embodiment of the present disclosure, introduction of light toward the third channel region of the third semiconductor pattern231may be effectively prevented. In the display apparatus according to the other embodiment of the present disclosure, accordingly, degradation of image quality caused by deviations in characteristics of the second thin film transistor T2disposed in each pixel area PA may be effectively prevented.

In a display apparatus according to another embodiment of the present disclosure, as shown inFIGS.9and10, a first light shielding trench PT1may be disposed on the first side surface S1of the third semiconductor pattern231, a second light shielding trench PT2may be disposed on the second side surface S2of the third semiconductor pattern231, and the third gate electrode233may include a first electrode region233bdisposed in the first light shielding trench PT1, and a second electrode region233cdisposed in the second light shielding trench PT2. For example, a portion of the third gate electrode233may have a cap-shaped (inverted U-shaped) cross-section in the width direction of the third semiconductor pattern231. The first light shielding trench PT1and the second light shielding trench PT2may be spaced apart from the third semiconductor pattern231. The first light shielding trench PT1and the second light shielding trench PT2may extend in the longitudinal direction of the third semiconductor pattern231. For example, the third channel region of the third semiconductor pattern231may be disposed between the first light shielding trench PT1and the second light shielding trench PT2. The length of the second light shielding trench PT2may be equal to the length of the first light shielding trench PT1. The second light shielding trench PT2may have the same width as that of the first light shielding trench PT1. For example, the shape of the second light shielding trench PT2may be identical to the shape of the first light shielding trench PT1.

The first electrode region233bmay cover a side wall and a bottom surface of the first light shielding trench PT1. A side wall and a bottom surface of the second light shielding trench PT2may be covered by the second electrode region233c. The third gate electrode233may be electrically connected to the third light shielding pattern330outside the second light shielding trench PT2. In the display apparatus according to the other embodiment of the present disclosure, accordingly, introduction of inwardly-reflected light into the channel region of the third semiconductor pattern231may be effectively prevented.

In a display apparatus according to another embodiment of the present disclosure, the third channel region of the third semiconductor pattern231may be surrounded by the third light shielding pattern330and the third gate electrode233. For example, as shown inFIG.11, in the display apparatus according to the other embodiment of the present disclosure, the first light shielding trench PT1and the second light shielding trench PT2may extend through the lower interlayer insulating layer130, the upper buffer layer140, and the upper gate insulating layer150, the first electrode region233bmay directly contact the third light shielding pattern330within the first light shielding trench PT1, and the second electrode region233cmay directly contact the third light shielding pattern330within the second light shielding trench PT2. In the display apparatus according to the other embodiment of the present disclosure, accordingly, light reflected toward the third channel region of the third semiconductor pattern231may be effectively shielded by the third gate electrode233. In addition, in the display apparatus according to the other embodiment of the present disclosure, the third gate electrode233may be electrically connected to the third light shielding pattern330via the first electrode region233band the second electrode region233c. That is, in the display apparatus according to the other embodiment of the present disclosure, a process of forming a contact hole for electrical connection of the third gate electrode233to the third light shielding pattern330may be omitted. In the display apparatus according to the other embodiment of the present disclosure, accordingly, an enhancement in process efficiency may be achieved.

In a display apparatus according to another embodiment of the present disclosure, the third thin film transistor T3and the sixth thin film transistor T6, which are concurrently (or in some cases, simultaneously) turned on/off by the first gate signal applied thereto through the first gate line GL1, may be disposed in parallel. For example, as shown inFIGS.12and13, in the display apparatus according to the other embodiment of the present disclosure, the third thin film transistor T3and the sixth thin film transistor T6may be disposed on the third light shielding pattern330, the third semiconductor pattern231of the third thin film transistor T3and a sixth semiconductor pattern261of the sixth thin film transistor T6may extend across the third light shielding pattern330, and the third gate electrode233of the third thin film transistor T3may directly contact a sixth gate electrode263of the sixth thin film transistor T6.

The third gate electrode233and the sixth gate electrode263may be electrically connected to the third light shielding pattern330between the third semiconductor pattern231and the sixth semiconductor pattern261. A third light shielding trench PT3may be disposed on a side surface231S of the third semiconductor pattern231opposite to the sixth semiconductor pattern261, and a fourth light shielding trench PT4may be disposed on a side surface261S of the sixth semiconductor pattern261opposite to the third semiconductor pattern231. The third gate electrode233may include an end233edisposed in the third light shielding trench PT3, and the sixth gate electrode263may include an end263edisposed in the fourth light shielding trench PT4. The end233cof the third gate electrode233and the end263eof the sixth gate electrode263may be disposed nearer to the device substrate100than the third semiconductor pattern231and the sixth semiconductor pattern261. For example, the third light shielding trench PT3and the fourth light shielding trench PT4may extend through the upper buffer layer140and the upper gate insulating layer150. The end233eof the third gate electrode233may contact the lower interlayer insulating layer130within the third light shielding trench PT3, and the end263eof the sixth gate electrode263may contact the lower interlayer insulating layer130within the fourth light shielding trench PT4. In the display apparatus according to the other embodiment of the present disclosure, accordingly, freedom of the configuration of each pixel driving circuit DC may be enhanced, and introduction of light into the third channel region of the third semiconductor pattern231may be effectively prevented.

In a display apparatus according to another embodiment of the present disclosure, as shown inFIGS.14and15, a lower hole LH may be disposed between the device substrate100and the third channel region of the third semiconductor pattern231, a light shielding trench PT may be disposed on the first side surface of the third semiconductor pattern231, and the first electrode region233bof the third gate electrode233may extend along a side wall and a bottom surface of the light shielding trench PT. The first electrode region233bmay directly contact an end of the third light shielding pattern330within the light shielding trench PT. In the display apparatus according to the other embodiment of the present disclosure, accordingly, light reflected toward the third channel region of the third semiconductor pattern231may be effectively shielded by the third light shielding pattern330and the third gate electrode233. In the display apparatus according to the other embodiment of the present disclosure, accordingly, a variation in characteristics of the third thin film transistor T3disposed in each pixel area PA, which is caused by inward reflection of light, may be prevented. That is, in the display apparatus according to the other embodiment of the present disclosure, deviations in characteristics of the driving thin film transistor disposed in each pixel area PA, which are caused by introduction of light, may be prevented.

As apparent from the above description, the display apparatus according to each of the embodiments of the present disclosure may include a light emitting device and a pixel driving circuit disposed in each pixel area, wherein the pixel driving circuit may include a driving thin film transistor and a sampling thin film transistor, wherein the sampling thin film transistor may be electrically connected between a driving gate electrode and a driving source electrode of the driving thin film transistor, and may include a sampling semiconductor pattern disposed between a sampling light shielding pattern and a sampling gate electrode of the sampling thin film transistor, and wherein a cross-section of at least one of the sampling light shielding pattern or the sampling gate electrode in a width direction of the sampling semiconductor pattern may have a concave shape with reference to the sampling semiconductor pattern. In the display apparatus according to each of the embodiments of the present disclosure, accordingly, introduction of light into the channel region of the sampling semiconductor pattern disposed in each pixel area may be prevented. In the display apparatus according to each of the embodiments of the present disclosure, accordingly, degradation of image quality caused by deviations in characteristics of the driving thin film transistor disposed in each pixel area may be prevented.

Although the foregoing description has been given mainly in conjunction with embodiments, these embodiments are only illustrative without limiting the disclosure. Those skilled in the art to which the present disclosure pertains can appreciate that various modifications and applications illustrated in the foregoing description may be possible without changing essential characteristics of the embodiments. Therefore, the above-described embodiments should be understood as exemplary rather than limiting in all aspects. In addition, the scope of the present disclosure should also be interpreted by the claims below rather than the above detailed description. All modifications or alterations as would be derived from the equivalent concept intended to be included within the scope of the present disclosure should also be interpreted as falling within the scope of the disclosure.

The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.

These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.