Patent ID: 12218207

DETAILED DESCRIPTION

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. Embodiments of the present disclosure will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “over,” “under,” and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component(s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

Further, it is noted that the actual shapes of the various structures depicted as approximately rectangular may, in actual device, be curved, have rounded edges, have somewhat uneven thicknesses, etc. due to device fabrication conditions. The straight lines and right angles are used solely for convenience of representation of layers and features.

In the following description, semiconductor devices/dies/packages, methods for manufacturing the same, and the likes are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions may be made without departing from the scope and spirit of the present disclosure. Specific details may be omitted so as not to obscure the present disclosure; however, the disclosure is written to enable one skilled in the art to practice the teachings herein without undue experimentation.

FIG.1Ais a layout of a semiconductor device100A according to some embodiments of the present disclosure. The layout shows a relationship among gate electrodes114, field plates122and124, and source/drain (S/D) electrodes126of the semiconductor device100A. These elements can constitute parts of transistors in the semiconductor device100A. The layout reflects a top view of the semiconductor device100A, which means the layout reflects the gate electrodes114, the field plates122and124, and the S/D electrodes126are formed as layers and viewed along a direction normal to these layers. More structural details of the semiconductor device100A are provided as follows.

To illustrate,FIGS.1B and1Care cross-sectional views across a line1B-1B′ and a line1C-1C′ of the semiconductor device100A inFIG.1A. The semiconductor device100A further includes a substrate102, nitride-based semiconductor layers104and106, gate structures110, passivation layers116,118,120,130,138, vias132,136, patterned conductive layers134,140, and a protection layer142.

The substrate102may be a semiconductor substrate. The exemplary materials of the substrate102can include, for example but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator, such as silicon on insulator (SOI), or other suitable semiconductor materials. In some embodiments, the substrate102can include, for example, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds). In other embodiments, the substrate102can include, for example but is not limited to, one or more other features, such as a doped region, a buried layer, an epitaxial (epi) layer, or combinations thereof.

The nitride-based semiconductor layer104is disposed over the substrate102. The exemplary materials of the nitride-based semiconductor layer104can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, InxAlyGa(i-x-y)N where x+y≤1, AlyGa(1-y)N where y≤1. The nitride-based semiconductor layer106is disposed on the nitride-based semiconductor layer104. The exemplary materials of the nitride-based semiconductor layer106can include, for example but are not limited to, nitrides or group III-V compounds, such as GaN, AlN, InN, InxAlyGa(1-x-y)N where x+y≤1, AlyGa(1-y)N where y≤1.

The exemplary materials of the nitride-based semiconductor layers104and106are selected such that the nitride-based semiconductor layer106has a bandgap (i.e., forbidden band width) greater than a bandgap of the nitride-based semiconductor layer104, which causes electron affinities thereof different from each other and forms a heterojunction therebetween. For example, when the nitride-based semiconductor layer104is an undoped GaN layer having a bandgap of approximately 3.4 eV, the nitride-based semiconductor layer106can be selected as an AlGaN layer having bandgap of approximately 4.0 eV. As such, the nitride-based semiconductor layers104and106can serve as a channel layer and a barrier layer, respectively. A triangular well potential is generated at a bonded interface between the channel and barrier layers, so that electrons accumulate in the triangular well potential, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Accordingly, the semiconductor device100A is available to include at least one GaN-based high-electron-mobility transistor (HEMT).

In some embodiments, the semiconductor device100A may further include a buffer layer, a nucleation layer, or a combination thereof (not illustrated). The buffer layer can be disposed between the substrate102and the nitride-based semiconductor layer104. The buffer layer can be configured to reduce lattice and thermal mismatches between the substrate102and the nitride-based semiconductor layer104, thereby curing defects due to the mismatches/difference. The buffer layer may include a III-V compound. The III-V compound can include, for example but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Accordingly, the exemplary materials of the buffer layer can further include, for example but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof. The nucleation layer may be formed between the substrate102and the buffer layer. The nucleation layer can be configured to provide a transition to accommodate a mismatch/difference between the substrate102and a III-nitride layer of the buffer layer. The exemplary material of the nucleation layer can include, for example but is not limited to AlN or any of its alloys.

The gate structures110are disposed on/over/above the nitride-based semiconductor layer106. Each of the gate structures110may include an optional p-type doped III-V compound semiconductor layer112and the gate electrode114which is mentioned inFIG.1A. The p-type doped III-V compound semiconductor layers112and the gate electrodes114are stacked on the nitride-based semiconductor layer106. The p-type doped III-V compound semiconductor layers112are between the nitride-based semiconductor layer106and the gate electrodes114. In some embodiments, each of the gate structures110may further include an optional dielectric layer (not illustrated) between the p-type doped III-V compound semiconductor layer112and the gate electrode114.

In the exemplary illustration ofFIGS.1B and1C, the semiconductor device100A is an enhancement mode device, which is in a normally-off state when the gate electrodes114are at approximately zero bias. Specifically, the p-type doped III-V compound semiconductor layers112may create at least one p-n junction with the nitride-based semiconductor layer106to deplete the 2DEG region, such that at least one zone of the 2DEG region corresponding to a position below the corresponding gate structure110has different characteristics (e.g., different electron concentrations) than the rest of the 2DEG region and thus is blocked. Due to such mechanism, the semiconductor device100A has a normally-off characteristic. In other words, when no voltage is applied to the gate electrodes114or a voltage applied to the gate electrodes114is less than a threshold voltage (i.e., a minimum voltage required to form an inversion layer below the gate structures110), the zone of the 2DEG region below the gate structures110is kept blocked, and thus no current flows therethrough. Moreover, by providing the p-type doped III-V compound semiconductor layers112, gate leakage current is reduced and an increase in the threshold voltage during the off-state is achieved.

In some embodiments, the p-type doped III-V compound semiconductor layers112can be omitted, such that the semiconductor device100A is a depletion-mode device, which means the semiconductor device100A in a normally-on state at zero gate-source voltage.

The exemplary materials of the p-type doped III-V compound semiconductor layers112can include, for example but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped materials are achieved by using a p-type impurity, such as Be, Mg, Zn, Cd, and Mg. In some embodiments, the nitride-based semiconductor layer104includes undoped GaN and the nitride-based semiconductor layer106includes AlGaN, and the p-type doped III-V compound semiconductor layers112are p-type GaN layers which can bend the underlying band structure upwards and to deplete the corresponding zone of the 2DEG region, so as to place the semiconductor device100A into an off-state condition. In some embodiments, the gate electrodes114may include metals or metal compounds. The gate electrodes114may be formed as a single layer, or plural layers of the same or different compositions. The exemplary materials of the metals or metal compounds can include, for example but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, Si, metal alloys or compounds thereof, or other metallic compounds. In some embodiments, the exemplary materials of the gate electrodes114may include, for example but are not limited to, nitrides, oxides, silicides, doped semiconductors, or combinations thereof. In some embodiments, the optional dielectric layer can be formed by a single layer or more layers of dielectric materials. The exemplary dielectric materials can include, for example but are not limited to, one or more oxide layers, a SiOxlayer, a SiNxlayer, a high-k dielectric material (e.g., HfO2, Al2O3, TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, etc), or combinations thereof.

The S/D electrodes126are disposed on the nitride-based semiconductor layer106. The “S/D” electrode means each of the S/D electrodes126can serve as a source electrode or a drain electrode, depending on the device design. The S/D electrodes126can be located at two opposite sides of the corresponding gate structure110although other configurations may be used, particularly when plural source, drain, or gate electrodes are employed in the device. Each of the gate structure110can be arranged such that each of the gate structure110is located between the at least two of the S/D electrodes126. The gate structures110and the S/D electrodes126can collectively act as at least one nitride-based/GaN-based HEMT with the 2DEG region, which can be called a nitride-based/GaN-based semiconductor device. In the exemplary illustration ofFIG.1C, the pair of the adjacent S/D electrodes126are symmetrical about the gate structure110therebetween. In some embodiments, the pair of the adjacent S/D electrodes126can be optionally asymmetrical about the gate structure110therebetween. That is, one of the S/D electrodes126may be closer to the gate structure110than another one of the S/D electrodes126.

In some embodiments, the S/D electrodes126can include, for example but are not limited to, metals, alloys, doped semiconductor materials (such as doped crystalline silicon), compounds such as silicides and nitrides, other conductor materials, or combinations thereof. The exemplary materials of the S/D electrodes126can include, for example but are not limited to, Ti, AlSi, TiN, or combinations thereof. The S/D electrodes126may be a single layer, or plural layers of the same or different composition. In some embodiments, the S/D electrodes126form ohmic contact with the nitride-based semiconductor layer106. The ohmic contact can be achieved by applying Ti, Al, or other suitable materials to the S/D electrodes126. In some embodiments, each of the S/D electrodes126is formed by at least one conformal layer and a conductive filling. The conformal layer can wrap the conductive filling. The exemplary materials of the conformal layer, for example but are not limited to, Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or combinations thereof. The exemplary materials of the conductive filling can include, for example but are not limited to, AlSi, AlCu, or combinations thereof.

The passivation layers116,118,120are disposed over the nitride-based semiconductor layer106. The passivation layers116,118,120are sequentially stacked on the nitride-based semiconductor layer106. The passivation layers116,118,120can be formed for a protection purpose or for enhancing the electrical properties of the device (e.g., by providing an electrically isolation effect between/among different layers/elements). The passivation layer116covers a top surface of the nitride-based semiconductor layer106. The passivation layer116may cover the gate structures110. The passivation layer116can at least cover opposite two sidewalls of the gate structures110. The S/D electrodes126can penetrate/pass through the passivation layers116,118,120to contact the nitride-based semiconductor layer106. The exemplary materials of the passivation layers116,118,120can include, for example but are not limited to, SiNx, SiOx, Si3N4, SiON, SiC, SiBN, SiCBN, oxides, nitrides, poly(2-ethyl-2-oxazoline) (PEOX), or combinations thereof. In some embodiments, at least one of the passivation layers116,118,120can be a multi-layered structure, such as a composite dielectric layer of Al2O3/SiN, Al2O3/SiO2, AlN/SiN, AlN/SiO2, or combinations thereof.

The field plates122and124are disposed over the gate structures110. The field plate122is located between the passivation layers116and118. The field plate124is located between the passivation layers118and120. That is, the passivation layer116, the field plate122, the passivation layer118, the field plate124, and the passivation layer120are sequentially stacked/formed on the nitride-based semiconductor layer106. Each of the field plates122and124is located between at least two of the S/D electrodes126. The exemplary materials of the field plates122and124can include, for example but are not limited to, conductive materials, such as Ti, Ta, TiN, TaN, or combinations thereof. In some embodiments, other conductive materials such as Al, Cu doped Si, and alloys including these materials may also be used.

The process for forming the field plate122can be different than that of the field plate124, which is advantageous to the improvement in the electrical character of the semiconductor device100A. One of the reasons is that such approach can avoid the semiconductor device100A having a configuration turning away from the design thereof.

For example, with respect to a semiconductor device including a stack structure that is formed by a bottom passivation layer, a bottom field plate, a top passivation layer, and a top field plate. The formation of the bottom field plate may include patterning a blanket conductive layer to form the bottom field plate. However, during the patterning, some portion of the bottom passivation layer would be removed (the portions near a top surface of the bottom passivation layer), resulting in a reduced thickness of the bottom passivation layer. Accordingly, the top passivation layer and the top field plate on the bottom passivation layer will be formed at a position lower than the design position due to the reduced thickness of the bottom passivation layer. As such, the stability of the semiconductor device is affected and the performance of semiconductor device have reduced.

Referring toFIG.2, which is an enlarged view of a zone2A inFIG.1C, the illustration shows the detailed structural features resulted from the different processes for forming the field plates122and124.

The passivation layer116is disposed on the nitride-based semiconductor layer106. The passivation layer116covers the gate electrode114. As such, the passivation layer116is conformal with the gate electrode114, so as to form a protruding portion above the nitride-based semiconductor layer106with the gate electrode114.

The field plate122is disposed on the gate electrode114and the passivation layer116. At least one portion of the passivation layer116is covered with the field plate122, and the rest of the passivation layer116is free from coverage of the field plate122(but still can be covered by other layers). To illustrate, the passivation layer116has a portion116A covered with the field plate122and a portion116B free from the coverage of the field plate122. Furthermore, the field plate122laterally spans the gate electrode114. More specifically, in the cross-sectional view asFIG.2, a vertical projection of the gate electrode114on the nitride-based semiconductor layer106is entirely within a vertical projection of the field plate122on the nitride-based semiconductor layer106. The reason for such configuration is that an electric field distribution in a lateral HEMT device may be not uniform at an operation condition. The electric field will reach maximum at a gate edge toward a drain, which leads to breakdown and current collapse. Accordingly, the field plate design is implemented to reduce the peak electric field at the gate edge, improving uniformity of electric field distribution and hence increasing breakdown voltage.

The passivation layer118is disposed on the passivation layer116and covers the field plate122. The passivation layer118covers the portion116B of the passivation layer116. More specifically, the passivation layer116can have two regions abutting against each other, one of the regions is covered with the field plate122and another one is free from the coverage of the field plate122but covered with the passivation layer118.

The second field plate124is disposed over the field plate122and the passivation layer118. At least one portion of the passivation layer118is covered with the field plate124, and the rest of the passivation layer118is free from coverage of the field plate124(but still can be covered by other layers). To illustrate, the passivation layer118has a portion118A covered with the field plate124and a portion118B free from the coverage of the field plate124. Furthermore, the field plate124laterally spans the gate electrode114. The field plate124further laterally spans the field plate122. That is, the field plate124can laterally span an interface between the portions116A and116B of the passivation layer116, and thus the field plate124is directly above the interface between the portions116A and116B. More specifically, in the cross-sectional view asFIG.2, the vertical projection of the gate electrode114on the nitride-based semiconductor layer106is entirely within a vertical projection of the field plate124on the nitride-based semiconductor layer106. In the cross-sectional view asFIG.2, the vertical projection of the field plate124on the nitride-based semiconductor layer106is entirely within a vertical projection of the field plate124on the nitride-based semiconductor layer106. That is, the field plate124further extends laterally than the field plate122to reduce the peak electric field at an edge of the field plate122. The reason is similar with the afore-mentioned one. Due to the further extending of the field plate124, the interface between the portions116A and116B of the passivation layer116is closer to the gate electrode114than the interface between the portions118A and118B of the passivation layer118, which will be advantageous to cure the peak electric field at an edge of the field plate122by the field plate124.

In some embodiments, the field plate122has approximately the same thickness as a thickness of the field plate124. In some embodiments, the field plate122has a thickness greater than a thickness of the field plate124. In some embodiments, the field plate122has a thickness less than a thickness of the field plate124. The thickness relationship between the field plates122and124may depend on the practical requirements, such as the design on the distribution of the electric field or the process conditions.

The passivation layer120is disposed on the passivation layer118and covers the field plate124. The passivation layer120covers the portion118B of the passivation layer118. More specifically, the passivation layer118can have two regions abutting against each other, one of the regions is covered with the field plate124and another one is free from the coverage of the field plate124but covered with the passivation layer120.

Regarding at least one difference between the processes for forming the field plates122and124, they are patterned by different approaches. The patterning of the field plate122can be achieved by using a wet etching process, and the patterning of the field plate124can be achieved by using a dry etching process. In this regard, a chemical process of the wet etching can provide a high etch selectivity. The high etch selectivity means that the etch rate is stronger with respect to the target material but weaker with respect to the non-target material. In contrast, dry etching has a drawback of low selectivity. One of the reasons for using dry etching for patterning the field plate124is that dry etching involves ion bombardment, such as reactive-ion etching (RIE), and features fast etching and is controllable with respect to the target material. Although dry etching has a low selectivity, the tradeoff between the low selectivity and above advantages can provide a positive effect for the second lowest field plate (i.e., the field plate124).

In this regard, during the patterning of field plate122, the passivation layer116(e.g., the portion116B thereof) can be free from etching and thus the morphological profile thereof would be retained. As such, after patterning the field plate122, the thickness of the portion116A of the passivation layer116can be kept the same or almost the same (i.e., the reduced quantity is negligible). On the other hand, during patterning of the field plate124, the passivation layer118(e.g., the portion118B thereof) is etched as it is exposed from the field plate124, which is called over-etching, which would change the morphological profile thereof. As such, after the patterning the field plate124, the thickness of the portion118B of the passivation layer118is significantly reduced. Although the over-etching occurs across the passivation layer118, the vertical locations of the field plates122and124have been constructed such that over-etching would not significantly affect the performance of the semiconductor device100A. However, since the dry etching for pattering the field plate124has the favorable controllability, the efficiency of the process for manufacturing the semiconductor device100A can be increased (e.g., speeding up the manufacturing process).

Regarding over-etching, the etched portion118B of the passivation layer118will have a side surface and a top surface. The side surface of the portion118B is located between the portion118A and the top surface of the portion118A. The side surface of the portion118B forms an obtuse angle with the top surface of the portion118B. The top surface of the portion118B is in a position lower than the side surface of the portion118B. The passivation layer120is formed to cover the side surface and the top surface of the portion118B, so as to form an interface/a contact area therebetween. The interface/contact area therebetween is in a position lower than the portion118A.

As such, after the formation of the field plate122, a thickness difference between the portions116A and116B of the passivation layer116is zero or approximate zero. After the formation of the field plate124, a thickness difference between the portions118A and118B of the passivation layer116is significantly greater than zero, which is labeled as a thickness difference TD inFIG.2. Accordingly, the thickness difference between the portions116A and116B of the passivation layer116is less than the thickness difference TD between the portions118A and118B of the passivation layer118. Since the thickness difference between the portions116A and116B of the passivation layer116is zero or approximate zero, the layers formed above the passivation layer116after the formation of the field plate122can be located at a position complying to the device design (e.g., the passivation layer118and the field plate124), thereby avoiding a deleterious impact on the performance of the semiconductor device100A.

In other words, with respect to the nitride-based semiconductor layer106, a region of the passivation layer116is covered by the edge of the field plate122at a height H1; a region of the passivation layer116that is free from the coverage of the field plate122has a height H2; a region of the passivation layer118covered by the edge of the field plate124has a height H3; a region of the passivation layer118free from the coverage of the field plate124has a height H4; and a difference between the heights H1and H2is less than a difference between the heights H3and H4.

Furthermore, the difference between wet and dry etching creates a different profile of the field plates122and124at their edges/sidewalls. The field plate122has a sidewall SW1extending upward from the passivation layer116. The sidewall SW1of the field plate122is recessed inward to receive the passivation layer118. The field plate124has an oblique sidewall SW2approximately ending at an interface between the portions118A and118B of the passivation layer118. The reason for such difference relates to isotropic etching and anisotropic etching, which results from wet etching and dry etching, respectively. For example, the field plates122and124can be formed by patterning two blanket conductive layers having the same conductive material, respectively, while the patterning process are performed by wet etching and dry etching. As a result, the field plates122and124can have the same conductive material, and the sidewall SW1of the field plate122has a profile different than that of the oblique sidewall SW2of the field plate124. Moreover, the field plates122and124may have different roughnesses. In some embodiments, a surface roughness of the oblique sidewall SW2is greater than a surface roughness of the sidewall SW1. Herein, the surface roughness refers to a component of surface texture (i.e., the dimension would be much smaller than the layer thickness thereof).

As the sidewall SW1of the field plate122is formed by the isotropic process of the wet etching, the sidewall SW1of the field plate122is curved. For example, from a top surface to a bottom surface of the field plate122, a distance between the sidewall SW1of field plate122and the protruding portion (i.e., formed by the gate electrode114and the passivation layer116) decreases and then increases, as shown by distances D1, D2, and D3inFIG.2. The relationship among the distances D1-D3is D1>D2and D3>D2.

As the sidewall SW2of the field plate124is formed by the anisotropic process of the dry etching, the sidewall SW2of the field plate124is flat and oblique. For example, the oblique sidewall SW2of the field plate124extends upward from the passivation layer118and is oblique with respect to a top surface of the passivation layer118(e.g., a top surface of the portion118A or the side surface of the portion118B of the passivation layer118). Furthermore, since over-etching occurs at the portion118B of the passivation layer118, the side surface and the top surface of the portion118B of the passivation layer118are lower than the oblique sidewall SW2of the field plate124. The side surface of the portion118B may have a flat and oblique profile. The side surface of the portion118B may extend obliquely from the oblique sidewall SW2to a position lower than the top surface of the portion118A. The degree of obliqueness in the oblique sidewall SW2and the side surface of the portion118B may be different, which results from the etching selectivity therebetween (i.e., the field plate124and the passivation layer118having different etching rates with respect to the same etchant).

Referring toFIGS.1B and1Cagain, the passivation layer130is disposed above the passivation layer120and the S/D electrodes126. The passivation layer130covers the passivation layer120and the S/D electrodes126. The passivation layer130can serve as a planarization layer which has a level top surface to support other layers/elements. In some embodiments, the passivation layer130can be formed as being thicker, and a planarization process, such as chemical mechanical polish (CMP) process, is performed on the passivation layer130to remove the excess portions, thereby forming a level top surface. The exemplary materials of the passivation layer130can include, for example but are not limited to, SiNx, SiOx, Si3N4, SiON, SiC, SiBN, SiCBN, oxides, PEOX, or combinations thereof. In some embodiments, the passivation layer130is a multi-layered structure, such as a composite dielectric layer of Al2O3/SiN, Al2O3/SiO2, AlN/SiN, AlN/SiO2, or combinations thereof.

The vias132are disposed within the passivation layer130. The vias132penetrate the passivation layer130. The vias132extend longitudinally to electrically couple with the gate structure110, the field plates122and124, and the S/D electrodes126, respectively. The upper surfaces of the vias132are free from coverage of the passivation layer130. The exemplary materials of the vias132can include, for example but are not limited to, conductive materials, such as metals or alloys.

A patterned conductive layer134is disposed on the passivation layer130and the vias132. The patterned conductive layer134is in contact with the vias132. The patterned conductive layer134may have metal lines, pads, traces, or combinations thereof, such that the patterned conductive layer134can form at least one circuit. The exemplary materials of the patterned conductive layer134can include, for example but are not limited to, conductive materials. The patterned conductive layer134may include a single film or multilayered film having Ag, Al, Cu, Mo, Ni, Ti, alloys thereof, oxides thereof, nitrides thereof, or combinations thereof.

The passivation layer138is disposed above the passivation layer130and the patterned conductive layer134. The passivation layer138covers the passivation layer130and the patterned conductive layer134. The passivation layer138can serve as a planarization layer which has a level top surface to support other layers/elements. In some embodiments, the passivation layer138can be formed as being thicker, and a planarization process, such as CMP process, is performed on the passivation layer138to remove the excess portions, thereby forming a level top surface. The exemplary materials of the passivation layer138can include, for example but are not limited to, SiNx, SiOx, Si3N4, SiON, SiC, SiBN, SiCBN, oxides, PEOX, or combinations thereof. In some embodiments, the passivation layer138is a multi-layered structure, such as a composite dielectric layer of Al2O3/SiN, Al2O3/SiO2, AlN/SiN, AlN/SiO2, or combinations thereof.

The vias136are disposed within the passivation layer138. The vias136penetrate the passivation layer138. The vias136extend longitudinally to electrically couple with the patterned conductive layer134. The upper surfaces of the vias136are free from coverage of the passivation layer136. The exemplary materials of the vias136can include, for example, but are not limited to, conductive materials, such as metals or alloys.

A patterned conductive layer140is disposed on the passivation layer138and the vias136. The patterned conductive layer140is in contact with the vias136. The patterned conductive layer140may have metal lines, pads, traces, or combinations thereof, such that the patterned conductive layer140can form at least one circuit. The exemplary materials of the patterned conductive layer140can include, for example but are not limited to, conductive materials. The patterned conductive layer140may include a single film or multilayered film having Ag, Al, Cu, Mo, Ni, Ti, alloys thereof, oxides thereof, nitrides thereof, or combinations thereof.

The circuit of the patterned conductive layer134or140can connect different layers/elements, making these layers or elements have the same electrical potential. For example, the vias132A,132B, and132C are disposed on and electrically coupled to the gate electrode114, the field plate122, and the field plate124, respectively. By such connection, the gate electrode114, the field plate122, and the field plate124can be electrically connected to each other via the circuit of the patterned conductive layer134to have the same electrical potential, and thus the field plates122and124can act as gate field plates.

The protection layer142is disposed above the passivation layer138and the patterned conductive layer140. The protection layer142covers the passivation layer138and the patterned conductive layer140. The protection layer142can prevent the patterned conductive layer140from oxidizing. Some portions of the patterned conductive layer140can be exposed through openings in the protection layer142, which are configured to electrically connect to external elements (e.g., an external circuit).

Different stages of a method for manufacturing the semiconductor device100A are shown inFIGS.3A-3M, described below. In the following, deposition techniques can include, for example but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic CVD (MOCVD), plasma enhanced CVD (PECVD), low-pressure CVD (LPCVD), plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.

Referring toFIG.3A, a substrate102is provided. Nitride-based semiconductor layers104and106can be formed over the substrate102in sequence by using the above-mentioned deposition techniques. A blanket p-type doped III-V compound semiconductor layer111and a blanket conductive layer113can be formed above the nitride-based semiconductor layer106in sequence by using the above-mentioned deposition techniques.

Referring toFIG.3B, the blanket p-type doped III-V compound semiconductor layer111and the blanket conductive layer113are patterned to form a plurality of gate structures110over the nitride-based semiconductor layer106. Each of the gate structures110includes a p-type doped III-V compound semiconductor layer112and agate electrode114. The patterning process can be performed by photolithography, exposure and development, etching, other suitable processes, or combinations thereof. A passivation layer116can be formed to cover the of the gate structures110by using the above-mentioned deposition techniques. By covering the gate structures110, the passivation layer116can form a plurality of protruding portions above the nitride-based semiconductor layer106with the gate electrode114.

Referring toFIG.3C, a blanket conductive layer121and a mask layer150can be formed above the passivation layer116in sequence by using the above-mentioned deposition techniques. The mask layer150can serve as a wet-etching mask for the blanket conductive layer121during patterning the same. In some embodiments, the blanket conductive layer121is made of TiN and the mask layer150is made of SiOx(e.g., SiO2).

Referring toFIG.3D, the mask layer150is patterned to form a mask layer152having openings. Some portions of the blanket conductive layer121are exposed from the openings of the mask layer152. The profile of the mask layer152can be transferred to the blanket conductive layer121by performing a patterning process.

Referring toFIG.3E, the blanket conductive layer121is patterned to form field plates122above the gate electrodes114. The field plates122have a profile similar to that of the mask layer150such that the field plates122can laterally span across the corresponding gate electrodes114. The patterning process can be performed by a wet etching process. During the wet etching process, the mask layer152can protect portions of the underlying blanket conductive layer121. Accordingly, the portions of the blanket conductive layer121exposed from the openings of the mask layer152are removed. As afore-mentioned, the wet etching process can provide a high selectivity, so no over-etching would occur at the passivation layer116and thus the thickness of the passivation layer116can be kept the same or almost the same. In some embodiments, the blanket conductive layer121is made of TiN and the passivation layer116is made of Si3N4, such that they can have a high selectivity with respect to the same etchant during a wet etching process.

Referring toFIG.3F, the mask layer152is removed. Then, a passivation layer118and a blanket conductive layer123can be formed over the passivation layer116and the field plates122in sequence by using the above-mentioned deposition techniques. The passivation layer118can be formed to cover the passivation layer116and the field plates122. The blanket conductive layer123can be formed to cover the passivation layer118.

Referring toFIG.3G, a mask layer154can be formed above/over/on the blanket conductive layer123by using the above-mentioned deposition techniques. The mask layer154can serve as a dry-etching mask for the blanket conductive layer123during patterning the same. In some embodiments, the blanket conductive layer121is made of TiN and the mask layer154is made of made of light-sensitive materials, such as a composition of a polymer, a sensitizer, and a solvent.

Referring toFIG.3H, the mask layer154is patterned to form a mask layer156having openings. Some portions of the blanket conductive layer123are exposed from the openings of the mask layer156. The profile of the mask layer156can be transferred to the blanket conductive layer123by performing a patterning process. In the exemplary illustration ofFIG.3H, the patterning process can be performed by using a dry etching process. For example, the dry etching process is a RIE process, which applies high-energy ions158from a plasma source to attack the exposed portions of the blanket conductive layer123and react with it for removing the same, so as to achieve patterning. After patterning, field plates124are formed from the blanket conductive layer123.

Referring toFIG.3I, after patterning, the mask layer156is removed. The field plates124are formed above the field plate122. The field plates laterally span across the field plate122. Then, a passivation layer120can be formed over the passivation layer118and the field plates124by using the above-mentioned deposition techniques. The passivation layer120can be formed to cover the passivation layer118and the field plates124.

Referring toFIG.3J, S/D regions160are formed by removing some portions of the passivation layers116,118,120. At least one portion of the nitride-based semiconductor layer106is exposed from the S/D regions160.

Referring toFIG.3K, a blanket conductive layer125is formed above the resulted structure ofFIG.3J. The blanket conductive layer125is conformal with the resultant structure ofFIG.3J. The blanket conductive layer125is formed to cover the nitride-based semiconductor layer106and the passivation layers116,118,120. The blanket conductive layer125is formed to fill the S/D regions160, thereby contacting with the nitride-based semiconductor layer106. The next stage is patterning the blanket conductive layer125. According to the desired requirements, the blanket conductive layer125can be patterned to have different profiles.

Referring toFIG.3L, which shows one of the patterning results for the blanket conductive layer125, S/D electrodes126are formed by patterning the blanket conductive layer125. Some portions of the blanket conductive layer125are removed, and rest of the blanket conductive layer125within the S/D regions160remains to serve as the S/D electrodes126. In some embodiments, an entirety of the S/D electrodes126(i.e., the remaining blanket conductive layer125) is lower than the passivation layer120. In some embodiments, the blanket conductive layer125can be formed to be thicker, such that the S/D electrodes126(i.e., the remaining blanket conductive layer125) is in a position higher than the passivation layer120.

Referring toFIG.3M, which shows another one of the patterning results for the blanket conductive layer125, S/D electrodes126are formed in the same manner as inFIG.3L. Another remaining portion127of the blanket conductive layer125is located on the passivation layer120and is separated from the S/D electrodes126. The portion127can serve as at least one gate field plate above the field plates122and124and further laterally spans the field plates122and124. That is, patterning the blanket conductive layer125not only can form the S/D electrodes126but also form the gate field plate. Therefore, the formation of the S/D electrodes126and the gate field plate can be integrated into one stage.

After the formation of the S/D electrodes126, the follow-up processes can be performed for forming passivation layers, vias, and patterned conductive layers over the resultant structure ofFIG.3L or3M, thereby obtaining the structure ofFIGS.1A-1C. The process for forming the passivation layer serving as a planarization layer includes a chemical mechanical polish (CMP) process. The process for forming the vias includes forming a conductive layer and removing the excess portions of the conductive layer. The process for forming the patterned conductive layers includes photolithography, exposure and development, etching, other suitable processes, or combinations thereof.

FIG.4is a cross-sectional view of a semiconductor device100B according to some embodiments of the present disclosure. In the present embodiment, as shown in the exemplary illustration ofFIG.4, two opposite sidewalls SW1A and SW1B of the field plate122are asymmetrical about the gate electrode114of the gate structure. In order not to make the drawing too complex, the sidewalls SW1A and SW1B of the field plate122are depicted as being flat. Practically, the sidewalls SW1A and SW1B of the field plate122extend upward from the passivation layer116and are recessed inward to receive the passivation layer118. Regarding the asymmetry, a distance D4from the sidewall SW1A to the gate electrode114is different than a distance D5from the sidewall SW1B to the gate electrode114. The distance D4is less than the distance D5. In the semiconductor device100C, the field plates122and124can be patterned by wet and dry etching processes, respectively, as well, and thus the field plate design of the present disclosure is flexible, being available to satisfy different device requirements.

FIG.5is a cross-sectional view of a semiconductor device100C according to some embodiments of the present disclosure. In the present embodiment, as shown in the exemplary illustration ofFIG.5, two opposite sidewalls SW2A and SW2B of the field plate124are asymmetrical about the gate electrode114of the gate structure. In order not to make the drawing too complex, the sidewalls SW2A and SW2B of the field plate124are depicted as being vertically flat. Practically, the sidewalls SW2A and SW2B of the field plate124extend upward from the passivation layer120and are oblique. Regarding the asymmetry, a distance D6from the sidewall SW2A to the gate electrode114is different than a distance D7from the sidewall SW2B to the gate electrode114. The distance D6is less than the distance D7. In the semiconductor device100C, the field plates122and124can be patterned by wet and dry etching processes, respectively, as well, and thus the field plate design of the present disclosure is flexible, being available to satisfy different device requirements.

The foregoing description of the present invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations will be apparent to the practitioner skilled in the art. Different embodiments can be combined. For example, althoughFIG.4only shows the field plate122asymmetrical about the gate electrode114andFIG.5only shows the field plate124asymmetrical about the gate electrode114, in some embodiments, both the field plates122and124can be asymmetrical about the gate electrode114. For example, althoughFIG.5only shows the sidewall SW1A of the field plate122is closer to the gate electrode114than the sidewall SW1B of the field plate122, in some embodiments, the sidewall SW1A of the field plate122can be farther from the gate electrode114than the sidewall SW1B of the field plate122.

The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms “substantially,” “substantial,” “approximately” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term “substantially coplanar” can refer to two surfaces within micrometers of lying along a same plane, such as within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 m of lying along the same plane.

As used herein, the singular terms “a,” “an,” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. Further, it is understood that actual devices and layers may deviate from the rectangular layer depictions of the FIGS. and may include angles surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.