Patent ID: 12249574

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Embodiments will be described with respect to a specific context, namely, an interconnect structure of a semiconductor device and a method of forming the same. Various embodiments allow for forming a barrier/adhesion layer comprising a single material, such that the barrier/adhesion layer has a layered structure and provides good barrier and adhesion properties. Various embodiments described herein allow for reducing a thickness of the barrier/adhesion layer and enlarging a conductive material volume of an interconnect (such as a conductive line and/or via), and suppressing scattering effects at an interface between the barrier/adhesion layer and the conductive material. Accordingly, a resistance of the interconnect is reduced.

FIGS.1-3and5-17illustrate cross-sectional views of various intermediate stages of fabrication of a semiconductor device100in accordance with some embodiments. Referring toFIG.1, the process for forming the semiconductor device100comprises providing a substrate101. The substrate101may comprise, for example, bulk silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of a semiconductor material, such as silicon, formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulator layer is provided on a substrate, such as a silicon or glass substrate. Alternatively, the substrate101may include another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used.

In some embodiments, one or more active and/or passive devices103(illustrated inFIG.1as a single transistor) are formed on the substrate101. The one or more active and/or passive devices103may include various N-type metal-oxide semiconductor (NMOS) and/or P-type metal-oxide semiconductor (PMOS) devices, such as transistors, capacitors, resistors, diodes, photo-diodes, fuses, and the like. One of ordinary skill in the art will appreciate that the above examples are provided for the purpose of illustration only and are not meant to limit the present disclosure in any manner. Other circuitry may be also used as appropriate for a given application.

In some embodiments, the transistor103includes a gate stack comprising a gate dielectric105and a gate electrode107, spacers109on opposite sidewalls of the gate stack, and source/drain regions111adjacent to the respective spacers109. For simplicity, components that are commonly formed in integrated circuits, such as gate silicides, source/drain silicides, contact etch stop layers, and the like, are not illustrated. In some embodiments, the transistor103may be formed using any acceptable methods. In some embodiments, the transistor103may be a planar MOSFET, a finFET, a nano-FET, a gate-all-around (GAA) transistor, or the like.

In some embodiments, one or more interlayer dielectric (ILD) layers113are formed over the substrate101and the one or more active and/or passive devices103. In some embodiments, the one or more ILD layers113may comprise a low-k material, such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like, and may be formed by any suitable method, such as spin-on coating, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), a combination thereof, or the like.

In some embodiments, source/drain contact plugs115and a gate contact plug117are formed in the one or more ILD layers113. The source/drain contact plugs115provide electrical contacts to the source/drain regions111. The gate contact plug117provides electrical contact to the gate electrode107. In some embodiments, the steps for forming the contact plugs115and117include forming openings in the one or more ILD layers113, depositing one or more barrier/adhesion layers (not explicitly shown) in the openings, depositing seed layers (not explicitly shown) over the one or more barrier/adhesion layers, and filling the openings with a conductive material (not explicitly shown). A chemical mechanical polishing (CMP) is then performed to remove excess materials of the one or more barrier/adhesion layers, the seed layers, and the conductive material overfilling the openings. In some embodiments, topmost surfaces of the contact plugs115and117are substantially coplanar or level with a topmost surface of the one or more ILD layers113within process variations of the CMP process.

In some embodiments, the one or more barrier/adhesion layers may comprise titanium, titanium nitride, tantalum, tantalum nitride, a combination thereof, a multilayer thereof, or the like, and may be formed using physical vapor deposition (PVD), CVD, ALD, a combination thereof, or the like. The one or more barrier/adhesion layers protect the one or more ILD layers113from diffusion and metallic poisoning. The seed layers may comprise copper, titanium, nickel, gold, manganese, a combination thereof, a multilayer thereof, or the like, and may be formed by ALD, CVD, PVD, sputtering, a combination thereof, or the like. The conductive material may comprise copper, aluminum, tungsten, cobalt, ruthenium, combinations thereof, alloys thereof, multilayers thereof, or the like, and may be formed using, for example, by plating, or other suitable methods.

FIGS.2,3, and5-17illustrate cross-sectional views of various intermediate stages of fabrication of an interconnect structure119over the structure ofFIG.1in accordance with some embodiments. Referring toFIG.2, in some embodiments, the steps for forming the interconnect structure119starts with forming a metallization layer1211over the one or more ILD layers113and the contact plugs115and117. In some embodiments, the formation of the metallization layer1211starts with forming an etch stop layer (ESL)1231over the one or more ILD layers113and the contact plugs115and117, and forming an inter-metal dielectric (IMD) layer1251over the ESL1231.

In some embodiments, a material for the ESL1231is chosen such that an etch rate of the ESL1231is less than an etch rate of the IMD layer1251. In some embodiments, the ESL1231may comprise one or more layers of dielectric materials. Suitable dielectric materials may include oxides (such as silicon oxide, aluminum oxide, or the like), nitrides (such as SiN, or the like), oxynitrides (such as SiON, or the like), oxycarbides (such as SiOC, or the like), carbonitrides (such as SiCN, or the like), carbides (such as SiC, or the like), combinations thereof, or the like, and may be formed using spin-on coating, CVD, PECVD, ALD, a combination thereof, or the like. In some embodiments, the IMD layer1251may be formed using similar materials and methods as the one or more ILD layers113and the description is not repeated herein. In some embodiments, the one or more ILD layers113and the IMD layer1251may comprise a same material. In other embodiments, the one or more ILD layers113and the IMD layer1251may comprise different materials.

Referring further toFIG.2, the IMD layer1251and the ESL1231are patterned to form openings127in the IMD layer1251and the ESL1231. In some embodiments, the openings127expose top surfaces of the respective source/drain contact plugs115. The openings127may also be referred to as via openings. In some embodiments, the openings127may be formed using suitable photolithography and etching processes. The etching process may include one or more dry etching processes. The etching process may be anisotropic. The openings127have a width W1at a top of the openings127. In some embodiments, a width of the openings127decreases as the openings127extend towards the substrate101. In some embodiments, the width W1is between about 2 nm and about 20 nm.

Referring toFIG.3, a barrier/adhesion layer129is formed over the IMD layer1251and along sidewalls and bottoms of the openings127. In some embodiments, barrier/adhesion layer129comprises a material (or a compound) having a chemical formula MXn, where M is a transition metal element, such as Ti, Zr, Hf, V, Nb, Ta, Mo, W, Tc, Re, Co, Rh, Ir, Ni, Pd, or Pt, where X is a chalcogen element, such as S, Se, or Te, and where n is between 0.5 and 2. In other embodiments, the barrier/adhesion layer129may comprise Ta2S5, Ta2O5, or the like. In some embodiments, the barrier/adhesion layer129has a thickness T1between about 1 nm and about 3 nm. The barrier/adhesion layer129reduces a volume available for a conductive material that is subsequently formed in the openings127. In particular, after forming the barrier/adhesion layer129, a remaining width of the openings127is reduced to the original width W1(seeFIG.2) of the openings127minus 2 times the thickness T1of the barrier/adhesion layer129. In some embodiments, a ratio of 2 times the thickness T1of the barrier/adhesion layer129to the original width W1(seeFIG.2) of the openings127is between about 0.05 and about 1. By forming the barrier/adhesion layer129from a single material as described above, the thickness T1of the barrier/adhesion layer129may be reduced compared to a dual-material barrier/adhesion layer. Accordingly, a volume available for a conductive material that is subsequently formed in the openings127is enlarged and a resistance of resulting interconnects is reduced.

FIG.4is a flow diagram illustrating a method160of forming the barrier/adhesion layer129(seeFIG.3) in accordance with some embodiments.FIGS.5and6illustrate cross-sectional views of various intermediate stages of fabrication of the barrier/adhesion layer129in accordance with the method160. Referring toFIGS.4and5, in step161, a metallic material133is deposited over the IMD layer1251and along sidewalls and bottoms of the openings127. In some embodiments, the metallic material133comprises a transition metal, such as Ti, Zr, Hf, V, Nb, Ta, Mo, W, Tc, Re, Co, Rh, Ir, Ni, Pd, or Pt, and may be formed by PVD or the like. In some embodiments when the barrier/adhesion layer129comprises TaS2, the metallic material133comprises Ta.

Referring toFIGS.4and6, in step163, a chalcogen treatment process135is performed on the metallic material133to form the barrier/adhesion layer129(seeFIG.3). In some embodiment, the chalcogen treatment process135comprises performing a PECVD process using a suitable chalcogen-containing precursor. In some embodiments when the barrier/adhesion layer129comprises TaS2, the chalcogen treatment process135is a sulfidation process. In such embodiments, the sulfidation process comprises performing a PECVD process using a process gas comprising a sulfur-containing precursor and a carrier gas. In some embodiments, the sulfur-containing precursor comprises dimethyl disulfide (DMDS), H2S, a combination thereof, or the like. In some embodiments, the carrier gas comprises an inert gas, such as Ar, He, N2, or the like. In some embodiments, a flow rate of the carrier gas is between about 35 sccm and about 65 sccm. In some embodiments, the PECVD process is performed at a temperature between about 400° C. and about 800° C., and with a plasma power between about 20 W and about 800 W.

Referring back toFIG.3, in alternative embodiments, the barrier/adhesion layer129is formed using a single-step process such as ALD, CVD, or the like. In such embodiments, ALD or CVD may be performed using a suitable metal-containing precursor and a suitable chalcogen-containing precursor. In some embodiments when the barrier/adhesion layer129comprises TaS2, the metal-containing precursor comprises tantalum-containing precursor such as pentakis(dimethylamino)tantalum(V) (PDMAT), tantalum ethoxide, tantalum chloride, or the like, and the chalcogen-containing precursor comprises sulfur-containing precursor such as DMDS, H2S, or the like.

FIG.7illustrates a magnified view of a region131of the structure shown inFIG.3. In some embodiments, the barrier/adhesion layer129has a layered structure and comprises a plurality of sub-layers137. In some embodiments, the number of the sub-layers137is between about 1 and about 5. In some embodiments, each of the sub-layers137has a thickness between about 0.5 nm and about 1 nm. In some embodiments, the barrier/adhesion layer129has a thickness between about 0.5 nm and about 3 nm. In some embodiments when the barrier/adhesion layer129is formed using the method160described above with reference toFIGS.4-6, the layer structure of the barrier/adhesion layer129disappears at process temperatures below about 400° C.

FIG.8illustrates a cross-sectional view of a portion of the barrier/adhesion layer129in accordance with some embodiments. In some embodiments, the portion of the barrier/adhesion layer129as illustrated inFIG.8may be located along a bottom of the opening127(seeFIG.7), sidewalls of the opening127, or a top surface of the IMD layer1251. In some embodiments, each of the sub-layers137of the barrier/adhesion layer129is substantially flat (within process variations). In some embodiments, such a flat barrier/adhesion layer129may be formed using the method160described above with reference toFIGS.4-6at a process temperature of about 600° C. By forming the substantially flat barrier/adhesion layer129, scattering effects at an interface between the barrier/adhesion layer129and a conductive material subsequently formed over the barrier/adhesion layer129is suppressed, which reduces a resistance of resulting interconnects.

FIG.9illustrates a cross-sectional view of a portion of the barrier/adhesion layer129in accordance with some embodiments. In some embodiments, the portion of the barrier/adhesion layer129as illustrated inFIG.9may be located along the bottom of the opening127(seeFIG.7), the sidewalls of the opening127, or the top surface of the IMD layer1251. In some embodiments, each of the sub-layers137of the barrier/adhesion layer129has a wavy structure. In some embodiments, such a wavy barrier/adhesion layer129may be formed using the method160described above with reference toFIGS.4-6at a process temperature of about 800° C. Even though the barrier/adhesion layer129has a wavy structure as illustrated inFIG.9, the barrier/adhesion layer129is smooth in the microscopic level. Accordingly, scattering effects at an interface between the barrier/adhesion layer129and a conductive material subsequently formed over the barrier/adhesion layer129is suppressed, which reduces a resistance of resulting interconnects.

Referring toFIG.10, a seed layer139is formed over the barrier/adhesion layer129in the openings127(seeFIG.3) and over the IMD layer1251. In some embodiments, the seed layer139may comprise copper, titanium, nickel, gold, manganese, a combination thereof, a multilayer thereof, or the like, and may be formed by ALD, CVD, PVD, sputtering, a combination thereof, or the like. In some embodiments, the seed layer139may be formed having a thickness such that the seed layer139fills the openings127(seeFIG.3). In some embodiments, after depositing the seed layer139, a reflow process may be performed on the seed layer139to aid in filling of the openings127.

Referring toFIG.11, portions of the barrier/adhesion layer129and the seed layer139overfilling the openings127(seeFIG.3) are removed to expose a top surface of the IMD layer1251. In some embodiments, the removal process may be a planarization process comprising a CMP process, a grinding process, an etching process, a combination thereof, or the like. Remaining portions of the barrier/adhesion layer129and the seed layer139filling the openings127(seeFIG.3) form conductive vias1411. In some embodiments, top surfaces of the conductive vias1411are substantially coplanar or level with the top surface of the IMD layer1251within process variations of the planarization process. In some embodiments, by forming the barrier/adhesion layer129as described above with reference toFIGS.4-6, a volume of the seed layer139is increased and scattering effects at an interface between the barrier/adhesion layer129and the seed layer139is reduced. Accordingly, a resistance of the conductive vias1411is reduced.

Referring toFIG.12, after forming the conductive vias1411, an ESL1411is formed over the IMD layer1251and the conductive vias1411, and an IMD layer1451is formed over the ESL1411. In some embodiments, a material for the ESL1411is chosen such that an etch rate of the ESL1411is less than an etch rate of the IMD layer1451. In some embodiments, the ESL1411may be formed using similar materials and methods as the ESL1231and the description is not repeated herein. In some embodiments, the IMD layer1451may be formed using similar materials and methods as the IMD layer1251and the description is not repeated herein.

Subsequently, the IMD layer1451and the ESL1411are patterned to form openings147in the IMD layer1451and the ESL1411. In some embodiments, the openings147expose top surfaces of the respective conductive vias1411. The openings147may also be referred to as line openings. In some embodiments, the openings147may be formed using suitable photolithography and etching processes. The etching process may include one or more dry etching processes. The etching process may be anisotropic. The openings147have a width W2at a top of the openings147. In some embodiments, the width W2is between about 5 nm and about 40 nm.

Referring toFIG.13, a barrier layer149is formed over the IMD layer1451and along sidewalls and bottoms of the openings147, and an adhesion layer151is formed over the barrier layer149. In some embodiments, the barrier layer149may comprise titanium, titanium nitride, tantalum, tantalum nitride, a combination thereof, a multilayer thereof, or the like, and the adhesion layer151may comprise titanium, tantalum, cobalt, ruthenium, an alloy thereof, a combination thereof, a multilayer thereof, or the like, and may be formed by ALD, CVD, PVD, sputtering, a combination thereof, or the like. In other embodiments, the barrier layer149may be formed using similar materials and method as the barrier/adhesion layer129, and the adhesion layer151may comprise titanium, tantalum, cobalt, ruthenium, an alloy thereof, a combination thereof, a multilayer thereof, or the like, and may be formed by ALD, CVD, PVD, sputtering, a combination thereof, or the like. In yet other embodiments, the barrier layer149may comprise titanium, titanium nitride, tantalum, tantalum nitride, a combination thereof, a multilayer thereof, or the like, and the adhesion layer151may be formed using similar materials and method as the barrier/adhesion layer129.

In some embodiments, the barrier layer149has a thickness T2between about 1 nm and about 5 nm. In some embodiments, the adhesion layer151has a thickness T3between about 1 nm and about 5 nm. The barrier layer149and the adhesion layer151reduce a volume available for a conductive material that is subsequently formed in the openings147. In particular, after forming the barrier layer149and the adhesion layer151, a remaining width of the openings147is reduced to the original width W2(seeFIG.12) of the openings147minus a sum of 2 times the thickness T2of the barrier layer149and 2 times the thickness T3of the adhesion layer151. In some embodiments, a ratio of the sum of 2 times the thickness T2of the barrier layer149and 2 times the thickness T3of the adhesion layer151to the original width W2(seeFIG.12) of the openings147is between about 0.05 and about 1.

Referring toFIG.14, a seed layer153is formed over the adhesion layer151in the openings147and over the IMD layer1451. In some embodiments, the seed layer153may be formed using similar materials and methods as the seed layer139and the description is not repeated herein. In the illustrated embodiment, the seed layer153is formed having a thickness such that the seed layer153partially fills the openings147. In some embodiments when the adhesion layer151is formed using similar materials and methods as the barrier/adhesion layer129, scattering effects at an interface between the adhesion layer151and the seed layer153is suppressed, which reduces a resistance of resulting interconnects.

Referring toFIG.15, a conductive fill layer155is formed in the openings147(seeFIG.14) and over the IMD layer1451. In some embodiments, the conductive fill layer155overfills the openings147. In some embodiments, the conductive fill layer155may comprise copper, aluminum, tungsten, ruthenium, cobalt, nickel, combinations thereof, alloys thereof, multilayers thereof, or the like, and may be formed using, for example, by plating (such as, for example, electrochemical plating, electroless plating, or the like), or other suitable deposition methods.

Referring toFIG.16, portions of the barrier layer149, the adhesion layer151, the seed layer153, and the conductive fill layer155overfilling the openings147(seeFIG.14) are removed to expose a top surface of the IMD layer1451. In some embodiments, the removal process may be a planarization process comprising a CMP process, a grinding process, an etching process, a combination thereof, or the like. Remaining portions of the barrier layer149, the adhesion layer151, the seed layer153, and the conductive fill layer155filling the openings147(seeFIG.14) form conductive lines1571. In some embodiments, top surfaces of the conductive lines1571are substantially coplanar or level with a top surface of the IMD layer1451within process variations of the planarization process.

Referring toFIG.17, one or more metallization layers similar to the metallization layer1211are formed over the metallization layer1211until a metallization layer121Mis formed. In some embodiments, the metallization layer121Mis the final metallization layer of the interconnect structure119. In some embodiments, M may be between 1 and 12. In some embodiments, the intermediate metallization layers between the metallization layer1211and the metallization layer121Mare formed in a similar manner as the metallization layer1211and the description is not repeated herein. In other embodiments, the metallization layer121Mis not the final metallization layer of the interconnect structure119and additional metallization layers are formed over the metallization layer121M.

In some embodiments, process steps for forming the metallization layer121Mstart with forming an ESL123Mover a previous metallization layer. In some embodiments, the ESL123Mis formed using similar materials and methods as the ESL1231and the description is not repeated herein. Subsequently, an IMD layer125Mis formed over the ESL123M. In some embodiments, the IMD layer125Mis formed using similar materials and methods as the IMD layer1251and the description is not repeated herein. Subsequently, conductive vias141Mare formed in the IMD layer125Mand the ESL123M. In some embodiments, features of the conductive vias141Mare similar to features of the conductive vias1411, with similar features being labeled by similar numerical references. In some embodiments, the conductive vias141Mmay be formed using process steps as described above with reference toFIGS.2-11, and the description is not repeated herein.

In some embodiments, after forming the conductive vias141M, an ESL143Mis formed over the conductive vias141Mand the IMD layer125M. In some embodiments, the ESL143Mis formed using similar materials and methods as the ESL1411and the description is not repeated herein. Subsequently, an IMD layer145Mis formed over the ESL143M. In some embodiments, the IMD layer145Mis formed using similar materials and methods as the IMD layer1451and the description is not repeated herein. Subsequently, conductive lines157Mare formed in the IMD layer145Mand the ESL143M. In some embodiments, features of the conductive lines157Mare similar to features of the conductive lines1571, with similar features being labeled by similar numerical references. In some embodiments, the conductive lines157Mmay be formed using process steps as described above with reference toFIGS.12-16, and the description is not repeated herein.

FIG.18illustrates a cross-sectional view of a semiconductor device200in accordance with some embodiments. The semiconductor device200is similar to the semiconductor device100(seeFIG.17), with similar features being labeled by similar numerical references. In some embodiments, the interconnect structure201(comprising the metallization layers2031to203M) of the semiconductor device200may be formed using process steps similar to the process steps for forming the interconnect structure119of the semiconductor device100described above with reference toFIGS.2-17, and the description is not repeated herein. In the illustrated embodiment, the formation of the ESLs1411to143M(seeFIG.17) is omitted, such that the IMD layers1451to145Mare formed directly over the IMD layers1251to125M, respectively.

FIGS.19-25illustrate cross-sectional views of various intermediate stages of fabrication of a semiconductor device300in accordance with some embodiments. In particular,FIGS.19-25illustrate cross-sectional views of various intermediate stages of fabrication of an interconnect structure301over the structure ofFIG.1in accordance with some embodiments.

Referring toFIG.19, in some embodiments, the steps for forming the interconnect structure301starts with forming a metallization layer3031over the one or more ILD layers113and the contact plugs115and117. In some embodiments, the formation of the metallization layer3031starts with forming an ESL1231over the one or more ILD layers113and the contact plugs115and117, and forming an IMD layer1251over the ESL1231as described above with reference toFIG.2and the description is not repeated herein.

In some embodiments, the IMD layer1251and the ESL1231are patterned to form openings127in the IMD layer1251and the ESL1231as described above with reference toFIG.2and the description is not repeated herein. In some embodiments, the openings127expose top surfaces of respective source/drain contact plugs115.

Referring toFIG.20, a barrier/adhesion layer129is formed over the IMD layer1251and along sidewalls and bottoms of the openings127as described above with reference toFIGS.3-6and description is not repeated herein.

Referring toFIG.21, a seed layer305is formed over the barrier/adhesion layer129in the openings127and over the IMD layer1251. In some embodiments, the seed layer305may be formed using similar materials and methods as the seed layer139described above with reference toFIG.10and the description is not repeated herein. In some embodiments, the seed layer305may be formed having a thickness such that the seed layer305partially fills the openings127.

Referring toFIG.22, a conductive fill layer307is formed in the openings127(seeFIG.21) and over the IMD layer1251. In some embodiments, the conductive fill layer307overfills the openings127. In some embodiments, the conductive fill layer307may be formed using similar materials and methods as the conductive fill layer155described above with reference toFIG.15and description is not repeated herein.

Referring toFIG.23, portions of the barrier/adhesion layer129, the seed layer305, and the conductive fill layer307overfilling the openings127(seeFIG.21) are removed to expose a top surface of the IMD layer1251. In some embodiments, the removal process may be a planarization process comprising a CMP process, a grinding process, an etching process, a combination thereof, or the like. Remaining portions of the barrier/adhesion layer129, the seed layer305, and the conductive fill layer307filling the openings127(seeFIG.21) form conductive vias3091. In some embodiments, top surfaces of the conductive vias3091are substantially coplanar or level with the top surface of the IMD layer1251within process variations of the planarization process. In some embodiments, by forming the barrier/adhesion layer129as described above with reference toFIGS.3-6, a volume of the conductive fill layer307is increased and scattering effects at an interface between the barrier/adhesion layer129and the seed layer305is reduced. Accordingly, a resistance of the conductive vias3091is reduced.

Referring toFIG.24, after forming the conductive vias3091, an ESL1411is formed over the IMD layer1251and the conductive vias3091, and an IMD layer1451is formed over the ESL1411as described above with reference toFIG.12and the description is not repeated herein. Subsequently, conductive lines1571are formed in the IMD layer1451and the ESL1411as described above with reference toFIGS.12-16and the description is not repeated herein. In some embodiments, the conductive lines1571are in physical contact with respective conductive vias3091.

Referring toFIG.25, one or more metallization layers similar to the metallization layer3031are formed over the metallization layer3031until a metallization layer303Mis formed. In some embodiments, the metallization layer303Mis the final metallization layer of the interconnect structure301. In some embodiments, M may be between 1 and 12. In some embodiments, the intermediate metallization layers between the metallization layer3031and the metallization layer303Mare formed in a similar manner as the metallization layer3031and the description is not repeated herein. In other embodiments, the metallization layer303Mis not the final metallization layer of the interconnect structure301and additional metallization layers are formed over the metallization layer303M.

In some embodiments, process steps for forming the metallization layer303Mstart with forming an ESL123Mover a previous metallization layer. In some embodiments, the ESL123Mis formed using similar materials and methods as the ESL1231and the description is not repeated herein. Subsequently, an IMD layer125Mis formed over the ESL123M. In some embodiments, the IMD layer125Mis formed using similar materials and methods as the IMD layer1251and the description is not repeated herein. Subsequently, conductive vias309Mare formed in the IMD layer125Mand the ESL123M. In some embodiments, features of the conductive vias309Mare similar to features of the conductive vias3091, with similar features being labeled by similar numerical references. In some embodiments, the conductive vias309Mmay be formed using process steps as described above with reference toFIGS.19-23, and the description is not repeated herein.

In some embodiments, after forming the conductive vias309M, an ESL143Mis formed over the conductive vias309Mand the IMD layer125M. In some embodiments, the ESL143Mis formed using similar materials and methods as the ESL1411and the description is not repeated herein. Subsequently, an IMD layer145Mis formed over the ESL143M. In some embodiments, the IMD layer145Mis formed using similar materials and methods as the IMD layer1451and the description is not repeated herein. Subsequently, conductive lines157Mare formed in the IMD layer145Mand the ESL143M. In some embodiments, features of the conductive lines157Mare similar to features of the conductive lines1571, with similar features being labeled by similar numerical references. In some embodiments, the conductive lines157Mmay be formed using process steps as described above with reference toFIGS.12-16, and the description is not repeated herein.

FIG.26illustrates a cross-sectional view of a semiconductor device400in accordance with some embodiments. The semiconductor device400is similar to the semiconductor device300(seeFIG.25), with similar features being labeled by similar numerical references. In some embodiments, the interconnect structure401(comprising the metallization layers4031to403M) of the semiconductor device400may be formed using process steps similar to the process steps for forming the interconnect structure301of the semiconductor device300described above with reference toFIGS.19-25, and the description is not repeated herein. In the illustrated embodiment, the formation of the ESLs1411to143M(seeFIG.25) is omitted, such that the IMD layers1451to145Mare formed directly over the IMD layers1251to125M, respectively.

FIGS.27-33illustrate cross-sectional views of various intermediate stages of fabrication of a semiconductor device500in accordance with some embodiments. In particular,FIGS.27-33illustrate cross-sectional views of various intermediate stages of fabrication of an interconnect structure501over the structure ofFIG.1in accordance with some embodiments.

Referring toFIG.27, in some embodiments, the steps for forming the interconnect structure501starts with forming a metallization layer5031over the one or more ILD layers113and the contact plugs115and117. In some embodiments, the formation of the metallization layer5031starts with forming an ESL1231over the one or more ILD layers113and the contact plugs115and117, and forming an IMD layer1251over the ESL1231as described above with reference toFIG.2and the description is not repeated herein. Subsequently, conductive vias1411are formed in the IMD layer1251and the ESL1231as described above with reference toFIGS.2-11and the description is not repeated herein. In some embodiments, the conductive vias1411are in physical contact with respective contact plugs115.

Referring toFIG.28, after forming the conductive vias1411, an ESL1411is formed over the IMD layer1251and the conductive vias1411, and an IMD layer1451is formed over the ESL1411as described above with reference toFIG.12and the description is not repeated herein.

In some embodiments, the IMD layer1451and the ESL1411are patterned to form openings147in the IMD layer1451and the ESL1411as described above with reference toFIG.12and the description is not repeated herein. In some embodiments, the openings147expose top surfaces of respective conductive vias1411.

Referring toFIG.29, a barrier/adhesion layer505is formed over the IMD layer1451and along sidewalls and bottoms of the openings147. In some embodiments, the barrier/adhesion layer505may be formed using similar materials and methods as the barrier/adhesion layer129described above with reference toFIGS.3-6and description is not repeated herein. In some embodiments, the barrier/adhesion layer505has a thickness T4between about 1 nm and about 3 nm. The barrier/adhesion layer505reduces a volume available for a conductive material that is subsequently formed in the openings147. In particular, after forming the barrier/adhesion layer505, a remaining width of the openings147is reduced to the original width W2(seeFIG.28) of the openings147minus 2 times the thickness T4of the barrier/adhesion layer505. In some embodiments, a ratio of 2 times the thickness T4of the barrier/adhesion layer505to the original width W2(seeFIG.28) of the openings147is between about 0.05 and about 1. By forming the barrier/adhesion layer505from a single material as described above with reference toFIGS.3-6, the thickness T4of the barrier/adhesion layer505may be reduced compared to a dual-material barrier/adhesion layer. Accordingly, a volume available for a conductive material that is subsequently formed in the openings147is enlarged and a resistance of resulting interconnects is reduced.

Referring toFIG.30, a seed layer153is formed over the barrier/adhesion layer505in the openings147and over the IMD layer1451as described above in reference toFIG.14and the description is not repeated herein. In the illustrated embodiment, the seed layer153is formed having a thickness such that the seed layer153partially fills the openings147.

Referring toFIG.31, a conductive fill layer155is formed in the openings147(seeFIG.30) and over the IMD layer1451as described above with reference toFIG.15and the description is not repeated herein.

Referring toFIG.32, portions of the barrier/adhesion layer505, the seed layer153, and the conductive fill layer155overfilling the openings147(seeFIG.30) are removed to expose a top surface of the IMD layer1451. In some embodiments, the removal process may be a planarization process comprising a CMP process, a grinding process, an etching process, a combination thereof, or the like. Remaining portions of the barrier/adhesion layer505, the seed layer153, and the conductive fill layer155filling the openings147(seeFIG.30) form conductive lines5071. In some embodiments, top surfaces of the conductive lines5071are substantially coplanar or level with the top surface of the IMD layer1451within process variations of the planarization process. By forming the barrier/adhesion layer505from a single material as described above with reference toFIGS.3-6, a volume of the conductive fill layer155is increased and scattering effects at an interface between the barrier/adhesion layer505and the seed layer153is suppressed. Accordingly, a resistance of the conductive lines5071is reduced.

Referring toFIG.33, one or more metallization layers similar to the metallization layer5031are formed over the metallization layer5031until a metallization layer503Mis formed. In some embodiments, the metallization layer503Mis the final metallization layer of the interconnect structure501. In some embodiments, M may be between 1 and 12. In some embodiments, the intermediate metallization layers between the metallization layer5031and the metallization layer503Mare formed in a similar manner as the metallization layer5031and the description is not repeated herein. In other embodiments, the metallization layer503Mis not the final metallization layer of the interconnect structure501and additional metallization layers are formed over the metallization layer503M.

In some embodiments, process steps for forming the metallization layer503Mstart with forming an ESL123Mover a previous metallization layer. In some embodiments, the ESL123Mis formed using similar materials and methods as the ESL1231and the description is not repeated herein. Subsequently, an IMD layer125Mis formed over the ESL123M. In some embodiments, the IMD layer125Mis formed using similar materials and methods as the IMD layer1251and the description is not repeated herein. Subsequently, conductive vias141Mare formed in the IMD layer125Mand the ESL123M. In some embodiments, features of the conductive vias141Mare similar to features of the conductive vias1411, with similar features being labeled by similar numerical references. In some embodiments, the conductive vias141Mmay be formed using process steps as described above with reference toFIG.27, and the description is not repeated herein.

In some embodiments, after forming the conductive vias141M, an ESL143Mis formed over the conductive vias141Mand the IMD layer125M. In some embodiments, the ESL143Mis formed using similar materials and methods as the ESL1411and the description is not repeated herein. Subsequently, an IMD layer145Mis formed over the ESL143M. In some embodiments, the IMD layer145Mis formed using similar materials and methods as the IMD layer1451and the description is not repeated herein. Subsequently, conductive lines507Mare formed in the IMD layer145Mand the ESL143M. In some embodiments, features of the conductive lines507Mare similar to features of the conductive lines5071, with similar features being labeled by similar numerical references. In some embodiments, the conductive lines507Mmay be formed using process steps as described above with reference toFIGS.28-32, and the description is not repeated herein.

FIG.34illustrates a cross-sectional view of a semiconductor device600in accordance with some embodiments. The semiconductor device600is similar to the semiconductor device500(seeFIG.33), with similar features being labeled by similar numerical references. In some embodiments, the interconnect structure601(comprising the metallization layers6031to603M) of the semiconductor device600may be formed using process steps similar to the process steps for forming the interconnect structure501of the semiconductor device500described above with reference toFIGS.27-33, and the description is not repeated herein. In the illustrated embodiment, the formation of the ESLs1411to143M(seeFIG.33) is omitted, such that the IMD layers1451to145Mare formed directly over the IMD layers1251to125M, respectively.

FIGS.35-37illustrate cross-sectional views of various intermediate stages of fabrication of a semiconductor device700in accordance with some embodiments. In particular,FIGS.35-37illustrate cross-sectional views of various intermediate stages of fabrication of an interconnect structure701over the structure ofFIG.1in accordance with some embodiments.

Referring toFIG.35, in some embodiments, the steps for forming the interconnect structure701starts with forming a metallization layer7031over the one or more ILD layers113and the contact plugs115and117. In some embodiments, the formation of the metallization layer7031starts with forming an ESL1231over the one or more ILD layers113and the contact plugs115and117, and forming an IMD layer1251over the ESL1231as described above with reference toFIG.2and the description is not repeated herein. Subsequently, conductive vias3091are formed in the IMD layer1251and the ESL1231as described above with reference toFIGS.19-23, and the description is not repeated herein. In some embodiments, the conductive vias3091are in physical contact with respective contact plugs115.

Referring toFIG.36, after forming the conductive vias3091, an ESL1411is formed over the IMD layer1251and the conductive vias3091, and an IMD layer1451is formed over the ESL1411as described above with reference toFIG.12and the description is not repeated herein. Subsequently, conductive lines5071are formed in the IMD layer1451and the ESL1411as described above with reference toFIGS.28-32, and the description is not repeated herein. In some embodiments, the conductive lines5071are in physical contact with respective conductive vias3091.

Referring toFIG.37, one or more metallization layers similar to the metallization layer7031are formed over the metallization layer7031until a metallization layer703Mis formed. In some embodiments, the metallization layer703Mis the final metallization layer of the interconnect structure701. In some embodiments, M may be between 1 and 12. In some embodiments, the intermediate metallization layers between the metallization layer7031and the metallization layer703Mare formed in a similar manner as the metallization layer7031and the description is not repeated herein. In other embodiments, the metallization layer703Mis not the final metallization layer of the interconnect structure701and additional metallization layers are formed over the metallization layer703M.

In some embodiments, process steps for forming the metallization layer703Mstart with forming an ESL123Mover a previous metallization layer. In some embodiments, the ESL123Mis formed using similar materials and methods as the ESL1231and the description is not repeated herein. Subsequently, an IMD layer125Mis formed over the ESL123M. In some embodiments, the IMD layer125Mis formed using similar materials and methods as the IMD layer1251and the description is not repeated herein. Subsequently, conductive vias309Mare formed in the IMD layer125Mand the ESL123M. In some embodiments, features of the conductive vias309Mare similar to features of the conductive vias3091, with similar features being labeled by similar numerical references. In some embodiments, the conductive vias309Mmay be formed using process steps as described above with reference toFIGS.19-23and the description is not repeated herein.

In some embodiments, after forming the conductive vias309M, an ESL143Mis formed over the conductive vias309Mand the IMD layer125M. In some embodiments, the ESL143Mis formed using similar materials and methods as the ESL1411and the description is not repeated herein. Subsequently, an IMD layer145Mis formed over the ESL143M. In some embodiments, the IMD layer145Mis formed using similar materials and methods as the IMD layer1451and the description is not repeated herein. Subsequently, conductive lines507Mare formed in the IMD layer145Mand the ESL143M. In some embodiments, features of the conductive lines507Mare similar to features of the conductive lines5071, with similar features being labeled by similar numerical references. In some embodiments, the conductive lines507Mmay be formed using process steps as described above with reference toFIGS.28-32and the description is not repeated herein.

FIG.38illustrates a cross-sectional view of a semiconductor device800in accordance with some embodiments. The semiconductor device800is similar to the semiconductor device700(seeFIG.37), with similar features being labeled by similar numerical references. In some embodiments, the interconnect structure801(comprising the metallization layers8031to803M) of the semiconductor device800may be formed using process steps similar to the process steps for forming the interconnect structure701of the semiconductor device700described above with reference toFIGS.35-37, and the description is not repeated herein. In the illustrated embodiment, the formation of the ESLs1411to143M(seeFIG.37) is omitted, such that the IMD layers1451to145Mare formed directly over the IMD layers1251to125M, respectively.

FIGS.39-44illustrate cross-sectional views of various intermediate stages of fabrication of a semiconductor device900in accordance with some embodiments. In particular,FIGS.39-44illustrate cross-sectional views of various intermediate stages of fabrication of an interconnect structure901over the structure ofFIG.1in accordance with some embodiments. Referring toFIG.39, in some embodiments, the steps for forming the interconnect structure901starts with forming a metallization layer9031over the one or more ILD layers113and the contact plugs115and117. In some embodiments, the formation of the metallization layer9011starts with forming an ESL9051over the one or more ILD layers113and the contact plugs115and117, and forming an IMD layer9071over the ESL9051.

In some embodiments, a material for the ESL9051is chosen such that an etch rate of the ESL9051is less than an etch rate of the IMD layer9071. In some embodiments, the ESL9051may be formed using similar materials and methods as the ESL1231described above with references toFIG.2and the description is not repeated herein. In some embodiments, the IMD layer9071may be formed using similar materials and methods as the IMD layer1251described above with references toFIG.2and the description is not repeated herein.

In some embodiments, a mask stack909is formed over the IMD layer9071. As described below in greater detail, the mask stack909is used to aid in patterning of the IMD layer9071. In some embodiments, the mask stack909comprises one or more mask layers. In the illustrated embodiment, the mask stack909comprises a first mask layer909A and a second mask layer909B over the first mask layer909A. In some embodiments, the first mask layer909A includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, a combination thereof, or the like, and may be formed using an oxidation process, ALD, CVD, PVD, a combination thereof, or the like. The first mask layer909A may be also referred to as a dielectric mask layer. In some embodiments, the second mask layer909B may comprise a metal nitride compound, such as titanium nitride (TiN), tantalum nitride (TaN), or the like, and may be formed using CVD, PECVD, ALD, a combination thereof, or the like. The second mask layer909B may be also referred to as a metal mask layer.

Referring further toFIG.39, the mask stack909, the IMD layer9071, and the ESL9051are patterned to form openings911. The openings911comprise lower portions911A, which may be also referred to as via openings911A, and upper portions911B, which may be also referred to as line openings911B. In some embodiments, the openings911may be formed by a “via first” process. In other embodiments, the openings911may be formed by a “trench first” process.

In some embodiments when the openings911are formed using a “via first” process, the via openings911A are formed before forming the line openings911B. In some embodiments, a first patterned mask (not shown) is formed on the second mask layer909B. A material of the first patterned mask is deposited on the second mask layer909B. The material of the first patterned mask is then irradiated (exposed), cured, and developed to remove a portion of the material of the first patterned mask, thereby forming the first patterned mask. In some embodiments, the first patterned mask may comprise a photoresist, or any suitable photo-patternable material.

In some embodiments, the first patterned mask is used to pattern the first mask layer909A, the second mask layer909B, and the IMD layer9071to form the via openings911A. Portions of the first mask layer909A, the second mask layer909B, and the IMD layer9071unprotected by the first patterned mask are etched using a first etch process. In some embodiments, the first etch process may comprise one or more suitable etch processes, such as, for example, an anisotropic dry etch process, or the like. In some embodiments, the entire first patterned mask may be fully consumed prior to completion of the first etch process. In such embodiments, the first mask layer909A and the second mask layer909B are used as an etch mask to complete the first etch process.

In some embodiments, the first etch process stops when the via openings911A reach the ESL9051, such that bottoms of the via openings911A expose portions of the ESL9051. In alternative embodiments, the first etch process stops before the via openings911A reach the ESL9051. In such embodiments, the bottoms of the via openings911A expose portions of the IMD layer9071. Subsequently, remaining portions of the first patterned mask, if any, are removed. In some embodiments when the first patterned mask is formed of a photoresist material, the remaining portions of the first patterned mask may be removed using, for example, an ashing process in combination with a wet clean process.

After forming the via openings911A, the line openings911B are formed in the IMD layer9071. In some embodiments, a second patterned mask (not shown) is formed on the second mask layer909B. A material of the second patterned mask is deposited on the second mask layer909B. The material of the second patterned mask is then irradiated (exposed), cured, and developed to remove a portion of the material of the second patterned mask, thereby forming the second patterned mask. In some embodiments, the second patterned mask may comprise a photoresist, or any suitable photo-patternable material.

In some embodiments, the second patterned mask is used to pattern the first mask layer909A, the second mask layer909B, and the IMD layer9071to form the line openings911B. Portions of the first mask layer909A, the second mask layer909B, and the IMD layer9071unprotected by the second patterned mask are etched using a second etch process. In some embodiments, the second etch process may comprise one or more suitable etch processes, such as, for example, an anisotropic dry etch process, or the like. In some embodiments, the second etch process may be different from the first etch process. In some embodiments, the entire second patterned mask may be fully consumed prior to completion of the second etch process. In such embodiments, the first mask layer909A and the second mask layer909B are used as an etch mask to complete the second etch process.

In some embodiments, the second etch process may further extend the via openings911A. In some embodiments when the ESL9051is not exposed after the first etch process, the second etch process further etches the IMD layer9071and the ESL9051, such that the via openings911A extend through the ESL9051and expose the respective source/drain contact plugs115.

In other embodiments when the ESL9051is exposed after the first etch process, the second etch process etches the ESL9051, such that the via openings911A extend through the ESL9051and expose the respective source/drain contact plugs115. Subsequently, remaining portions of the second patterned mask, if any, are removed. In some embodiments when the second patterned mask is formed of a photoresist material, the remaining portions of the second patterned mask may be removed using, for example, an ashing process in combination with a wet clean process.

Referring further toFIG.39, in alternative embodiments, the openings911are formed using a “trench first” process. In such embodiments, formation process of the openings911is similar to the “via first process” described above with a distinction that the line openings911B are formed before forming the via openings911A. In some embodiments, the via openings911A have a width W3at tops of the via openings911A and the line openings911B have a width W4at tops of the line openings911B. In some embodiments, the width W3is between about 2 nm and about 20 nm. In some embodiments, the width W4is between about 5 nm and about 40 nm.

Referring toFIG.40, a barrier/adhesion layer913is formed over the mask stack909, along sidewalls and bottoms of the via openings911A, and along sidewalls and bottoms of the line openings911B. In some embodiments, the barrier/adhesion layer913may be formed using similar materials and methods as the barrier/adhesion layer129described above with reference toFIGS.3-6and the description is not repeated herein. In some embodiments, the barrier/adhesion layer913has a thickness T5between about 1 nm and about 3 nm. The barrier/adhesion layer913reduces a volume available for a conductive material that is subsequently formed in the openings911. In particular, after forming the barrier/adhesion layer913, a remaining width of the via openings911A is reduced to the original width W3(seeFIG.39) of the via openings911A minus 2 times the thickness T5of the barrier/adhesion layer913, and a remaining width of the line openings911B is reduced to the original width W4(seeFIG.39) of the line openings911B minus 2 times the thickness T5of the barrier/adhesion layer913. In some embodiments, a ratio of 2 times the thickness T5of the barrier/adhesion layer913to the original width W3(seeFIG.39) of the via openings911A is between about 0.1 and about 1. In some embodiments, a ratio of 2 times the thickness T5of the barrier/adhesion layer913to the original width W4(seeFIG.39) of the line openings911B is between about 0.05 and about 1. By forming the barrier/adhesion layer913using similar materials and methods as the barrier/adhesion layer129described above with reference toFIGS.3-6, the thickness T5of the barrier/adhesion layer913may be reduced compared to a dual-material barrier/adhesion layer. Accordingly, a volume available for a conductive material that is subsequently formed in the openings911is enlarged and a resistance of resulting interconnects is reduced.

Referring toFIG.41, a seed layer915is formed over the barrier/adhesion layer913in the openings911and over the mask stack909. In some embodiments, the seed layer915may be formed using similar materials and methods as the seed layer139described above with reference toFIG.10and the description is not repeated herein. In some embodiments, the seed layer915may be formed having a thickness such that the seed layer915partially fills the via openings911A and the line opening911B.

Referring toFIG.42, a conductive fill layer917is formed in the openings911(seeFIG.41) and over the mask stack909. In some embodiments, the conductive fill layer917overfills the openings911. In some embodiments, the conductive fill layer917may be formed using similar materials and methods as the conductive fill layer155described above with reference toFIG.15and description is not repeated herein.

Referring toFIG.43, portions of the barrier/adhesion layer913, the seed layer915, and the conductive fill layer917overfilling the openings911(seeFIG.41) are removed to expose a top surface of the IMD layer9071. In some embodiments, the removal process further removes the mask stack909(seeFIG.42). In some embodiments, the removal process may be a planarization process comprising a CMP process, a grinding process, an etching process, a combination thereof, or the like. Remaining portions of the barrier/adhesion layer913, the seed layer915, and the conductive fill layer917filling the via openings911A (seeFIG.41) form conductive vias919A1. Remaining portions of the barrier/adhesion layer913, the seed layer915, and the conductive fill layer917filling the line openings911B (seeFIG.41) form conductive lines919B1. In some embodiments, top surfaces of the conductive lines919B1are substantially coplanar or level with the top surface of the IMD layer9071within process variations of the planarization process. In some embodiments, by forming the barrier/adhesion layer913using similar materials and methods as the barrier/adhesion layer129described above with reference toFIGS.3-6, a volume of the conductive fill layer917is increased and scattering effects at an interface between the barrier/adhesion layer913and the seed layer915is reduced. Accordingly, a resistance of the conductive vias919A1and a resistance of the conductive line919B1are reduced.

Referring toFIG.44, one or more metallization layers similar to the metallization layer9031are formed over the metallization layer9031until a metallization layer903Mis formed. In some embodiments, the metallization layer903Mis the final metallization layer of the interconnect structure901. In some embodiments, M may be between 1 and 12. In some embodiments, the intermediate metallization layers between the metallization layer9031and the metallization layer903Mare formed in a similar manner as the metallization layer9031and the description is not repeated herein. In other embodiments, the metallization layer903Mis not the final metallization layer of the interconnect structure901and additional metallization layers are formed over the metallization layer903M.

In some embodiments, process steps for forming the metallization layer903Mstart with forming an ESL905Mover a previous metallization layer. In some embodiments, the ESL905Mis formed using similar materials and methods as the ESL9051and the description is not repeated herein. Subsequently, an IMD layer907Mis formed over the ESL905M. In some embodiments, the IMD layer907Mis formed using similar materials and methods as the IMD layer9071and the description is not repeated herein.

Subsequently, conductive vias919AMand conductive lines919BMare formed in the IMD layer907Mand the ESL905M. In some embodiments, features of the conductive vias919AMand the conductive lines919BMare similar to features of the conductive vias919A1and the conductive lines919B1, respectively, with similar features being labeled by similar numerical references. In some embodiments, the conductive vias919AMand the conductive lines919BMmay be formed using process steps as described above with reference toFIGS.39-43, and the description is not repeated herein.

FIGS.45-52illustrate cross-sectional views of various intermediate stages of fabrication of a semiconductor device1000in accordance with some embodiments. In particular,FIGS.45-52illustrate cross-sectional views of various intermediate stages of fabrication of an interconnect structure1001(seeFIG.52) over the structure ofFIG.1in accordance with some embodiments.

Referring toFIG.45, in some embodiments, the steps for forming the interconnect structure1001starts with forming a metallization layer10031(seeFIG.51) over the one or more ILD layers113and the contact plugs115and117. In some embodiments, the formation of the metallization layer10031starts with forming a mask1005over the one or more ILD layers113and the contact plugs115and117. The mask1005may comprise a photoresist material, a polymer material, a dielectric material, or the like. After forming the mask1005, the mask1005is patterned to form openings1007in the mask1005. The openings1007expose respective contact plugs115. In some embodiments when the mask1005comprises a photoresist material, the patterning process comprises exposing the photoresist material to light followed by curing and developing processes. In some embodiments when the mask1005comprises a dielectric material, the patterning process comprises suitable photolithography and etch processes.

Referring toFIG.46, conductive columns1009are formed in the opening1007(seeFIG.45). In some embodiments, the conductive columns1009may comprise copper, aluminum, tungsten, ruthenium, cobalt, nickel, combinations thereof, alloys thereof, multilayers thereof, or the like, and may be formed using electroless plating, PVD, CVD, a combination thereof, or the like. The conductive columns1009are in physical contact with respective contact plugs115.

Referring toFIG.47, the mask1005(seeFIG.46) is removed to expose sidewalls of the conductive columns1009. In some embodiments when the mask1005comprises a photoresist material, the mask1005is removed by an ashing process followed by a wet clean process. In some embodiments when the mask1005comprises a dielectric material, the mask1005is removed by a suitable etch process that is selective to a material of the mask1005.

Referring toFIG.48, a barrier/adhesion layer1011is formed over the conductive columns1009and the one or more ILD layers113. The barrier/adhesion layer1011extends along a top surface and sidewalls of each of the conductive columns1009. In some embodiments, the barrier/adhesion layer1011may be formed using similar materials and methods as the barrier/adhesion layer129described above with reference toFIGS.3-6, and description is not repeated herein. In some embodiments, the barrier/adhesion layer1011has a thickness between about 0.5 nm and about 5 nm. In the illustrated embodiment, the barrier/adhesion layer1011is formed having a thickness such that the barrier/adhesion layer1011partially fills gaps between adjacent conductive columns1009.

Referring toFIG.49, a capping layer10131is formed over the barrier/adhesion layer1011. The capping layer10131may comprise silicon oxide, a metal oxide, silicon carbide, silicon nitride, a combination thereof, or the like, and may be formed using ALD, CVD, a combination thereof, or the like. In some embodiments, the capping layer10131has a thickness between about 1 nm and about 10 nm. In the illustrated embodiment, the capping layer10131is formed having a thickness such that the capping layer10131partially fills the gaps between adjacent conductive columns1009.

Subsequently, a dielectric layer10151is formed over the capping layer10131. The dielectric layer10151may be also referred to as an IMD layer10151. In some embodiments, the IMD layer10151may be formed using similar materials and methods as the one or more ILD layers113and the description is not repeated herein. In the illustrated embodiment, the IMD layer10151is formed having a thickness such that the IMD layer10151overfills the gaps between adjacent conductive columns1009.

Referring toFIG.50, portions of the barrier/adhesion layer1011, the capping layer10131, and the IMD layer10151extending above top surfaces of the conductive columns1009are removed to expose the top surfaces of the conductive columns1009. In some embodiments, the removal process may also remove portions of the conductive columns1009. The removal process may be a planarization process comprising a CMP process, a grinding process, an etching process, a combination thereof, or the like. The remaining portions of the conductive columns1009and portions of the barrier/adhesion layer1011extending along the sidewalls of the conductive columns1009form conductive vias10171. In some embodiments, after performing the planarization process, top surfaces of the conductive vias10171are substantially coplanar or level with a top surface of the capping layer10131and a top surface of the IMD layer10151within process variations of the planarization process.

Referring toFIG.51, after performing the planarization process, an ESL1411is formed over the IMD layer10151and the conductive vias10171, and an IMD layer1451is formed over the ESL1411as described above with reference toFIG.12and the description is not repeated herein. Subsequently, conductive lines1571are formed in the IMD layer1451and the ESL1411as described above with reference toFIGS.12-16and the description is not repeated herein. In some embodiments, the conductive lines1571are in physical contact with respective conductive vias10171.

Referring toFIG.52, one or more metallization layers similar to the metallization layer10031are formed over the metallization layer10031until a metallization layer1003Mis formed. In some embodiments, the metallization layer1003Mis the final metallization layer of the interconnect structure1001. In some embodiments, M may be between 1 and 12. In some embodiments, the intermediate metallization layers between the metallization layer10031and the metallization layer1003Mare formed in a similar manner as the metallization layer10031and the description is not repeated herein. In other embodiments, the metallization layer1003Mis not the final metallization layer of the interconnect structure1001and additional metallization layers are formed over the metallization layer1003M.

In some embodiments, process steps for forming the metallization layer1003Mstart with forming an IMD layer1015M, a capping layer1013M, and conductive vias1017Mover a previous metallization layer. In some embodiments, the IMD layer1015Mis formed using similar materials and methods as the IMD layer10151and the description is not repeated herein. In some embodiments, the capping layer1013Mis formed using similar materials and methods as the capping layer10131and the description is not repeated herein. In some embodiments, features of the conductive vias1017Mare similar to features of the conductive vias10171, with similar features being labeled by similar numerical references. In some embodiments, the conductive vias1017Mmay be formed using process steps as described above with reference toFIGS.45-50, and the description is not repeated herein.

In some embodiments, after forming the conductive vias1017M, an ESL143Mis formed over the conductive vias1017Mand the IMD layer1015M. In some embodiments, the ESL143Mis formed using similar materials and methods as the ESL1411and the description is not repeated herein. Subsequently, an IMD layer145Mis formed over the ESL143M. In some embodiments, the IMD layer145Mis formed using similar materials and methods as the IMD layer1451and the description is not repeated herein. Subsequently, conductive lines157Mare formed in the IMD layer145Mand the ESL143M. In some embodiments, features of the conductive lines157Mare similar to features of the conductive lines1571, with similar features being labeled by similar numerical references. In some embodiments, the conductive lines157Mmay be formed using process steps as described above with reference toFIGS.12-16, and the description is not repeated herein.

FIG.53illustrates a cross-sectional view of a semiconductor device1100in accordance with some embodiments. The semiconductor device1100is similar to the semiconductor device1000(seeFIG.52), with similar features being labeled by similar numerical references. In some embodiments, the interconnect structure1101(comprising the metallization layers11031to1103M) of the semiconductor device1100may be formed using process steps similar to the process steps for forming the interconnect structure1001of the semiconductor device1000described above with reference toFIGS.45-52, and the description is not repeated herein. In the illustrated embodiment, the formation of the capping layers10131to1013M(seeFIG.52) is omitted, such that the IMD layers10151to1015Mare formed directly over respective barrier/adhesion layers1011.

FIG.54illustrates a cross-sectional view of a semiconductor device1200in accordance with some embodiments. The semiconductor device1200is similar to the semiconductor device1000(seeFIG.52), with similar features being labeled by similar numerical references. In some embodiments, the interconnect structure1201(comprising the metallization layers12031to1203M) of the semiconductor device1200may be formed using process steps similar to the process steps for forming the interconnect structure1001of the semiconductor device1000described above with reference toFIGS.45-52, and the description is not repeated herein. In the illustrated embodiment, the formation of the ESLs1411to143M(seeFIG.52) is omitted, such that the IMD layers1451to145Mare formed directly over the IMD layers10151to1015M, respectively.

FIG.55illustrates a cross-sectional view of a semiconductor device1300in accordance with some embodiments. The semiconductor device1300is similar to the semiconductor device1200(seeFIG.54), with similar features being labeled by similar numerical references. In some embodiments, the interconnect structure1301(comprising the metallization layers13031to1303M) of the semiconductor device1300may be formed using process steps similar to the process steps for forming the interconnect structure1201of the semiconductor device1200described above with reference toFIG.54and the description is not repeated herein. In the illustrated embodiment, the formation of the capping layers10131to1013M(seeFIG.54) is omitted, such that the IMD layers10151to1015Mare formed directly over respective barrier/adhesion layers1011.

FIGS.56-58illustrate cross-sectional views of various intermediate stages of fabrication of a semiconductor device1400in accordance with some embodiments. In particular,FIGS.56-58illustrate cross-sectional views of various intermediate stages of fabrication of an interconnect structure1401(seeFIG.58) over the structure ofFIG.1in accordance with some embodiments.

Referring toFIG.56, in some embodiments, the steps for forming the interconnect structure1401starts with forming a metallization layer14031(seeFIG.57) over the one or more ILD layers113and the contact plugs115and117. Process steps for forming the metallization layer14031start with forming an IMD layer10151, a capping layer10131, and conductive vias10171over the one or more ILD layers113and the contact plugs115and117. In some embodiments, the IMD layer10151, the capping layer10131, and the conductive vias10171are formed using process steps described above with reference toFIGS.45-50, and the description is not repeated herein.

Referring toFIG.57, after forming the conductive vias10171, an ESL1411is formed over the IMD layer10151and the conductive vias10171, and an IMD layer1451is formed over the ESL1411as described above with reference toFIG.12and the description is not repeated herein. Subsequently, conductive lines5071are formed in the IMD layer1451and the ESL1411as described above with reference to FIGS.28-32, and the description is not repeated herein. In some embodiments, the conductive lines5071are in physical contact with respective conductive vias10171.

Referring toFIG.58, one or more metallization layers similar to the metallization layer14031are formed over the metallization layer14031until a metallization layer1403Mis formed. In some embodiments, the metallization layer1403Mis the final metallization layer of the interconnect structure1401. In some embodiments, M may be between 1 and 12. In some embodiments, the intermediate metallization layers between the metallization layer14031and the metallization layer1403Mare formed in a similar manner as the metallization layer14031and the description is not repeated herein. In other embodiments, the metallization layer1403Mis not the final metallization layer of the interconnect structure1401and additional metallization layers are formed over the metallization layer1403M.

In some embodiments, process steps for forming the metallization layer1403Mstart with forming an IMD layer1015M, a capping layer1013M, and conductive vias1017Mover a previous metallization layer. In some embodiments, the IMD layer1015Mis formed using similar materials and methods as the IMD layer10151and the description is not repeated herein. In some embodiments, the capping layer1013Mis formed using similar materials and methods as the capping layer10131and the description is not repeated herein. In some embodiments, features of the conductive vias1017Mare similar to features of the conductive vias10171, with similar features being labeled by similar numerical references. In some embodiments, the conductive vias1017Mmay be formed using process steps as described above with reference toFIGS.45-50, and the description is not repeated herein.

In some embodiments, after forming the conductive vias1017M, an ESL143Mis formed over the conductive vias1017Mand the IMD layer1015M. In some embodiments, the ESL143Mis formed using similar materials and methods as the ESL1411and the description is not repeated herein. Subsequently, an IMD layer145Mis formed over the ESL143M. In some embodiments, the IMD layer145Mis formed using similar materials and methods as the IMD layer1451and the description is not repeated herein. Subsequently, conductive lines507Mare formed in the IMD layer145Mand the ESL143M. In some embodiments, features of the conductive lines507Mare similar to features of the conductive lines5071, with similar features being labeled by similar numerical references. In some embodiments, the conductive lines507Mmay be formed using process steps as described above with reference toFIGS.28-32, and the description is not repeated herein.

FIG.59illustrates a cross-sectional view of a semiconductor device1500in accordance with some embodiments. The semiconductor device1500is similar to the semiconductor device1400(seeFIG.58), with similar features being labeled by similar numerical references. In some embodiments, the interconnect structure1501(comprising the metallization layers15031to1503M) of the semiconductor device1500may be formed using process steps similar to the process steps for forming the interconnect structure1401of the semiconductor device1400described above with reference toFIGS.56-58, and the description is not repeated herein. In the illustrated embodiment, the formation of the capping layers10131to1013M(seeFIG.58) is omitted, such that the IMD layers10151to1015Mare formed directly over respective barrier/adhesion layers1011.

FIG.60illustrates a cross-sectional view of a semiconductor device1600in accordance with some embodiments. The semiconductor device1600is similar to the semiconductor device1400(seeFIG.58), with similar features being labeled by similar numerical references. In some embodiments, the interconnect structure1601(comprising the metallization layers16031to1603M) of the semiconductor device1600may be formed using process steps similar to the process steps for forming the interconnect structure1401of the semiconductor device1400described above with reference toFIGS.56-58, and the description is not repeated herein. In the illustrated embodiment, the formation of the ESLs1411to143M(seeFIG.58) is omitted, such that the IMD layers1451to145Mare formed directly over the IMD layers10151to1015M, respectively.

FIG.61illustrates a cross-sectional view of a semiconductor device1700in accordance with some embodiments. The semiconductor device1700is similar to the semiconductor device1600(seeFIG.60), with similar features being labeled by similar numerical references. In some embodiments, the interconnect structure1701(comprising the metallization layers17031to1703M) of the semiconductor device1700may be formed using process steps similar to the process steps for forming the interconnect structure1601of the semiconductor device1600described above with reference toFIG.60and the description is not repeated herein. In the illustrated embodiment, the formation of the capping layers10131to1013M(seeFIG.60) is omitted, such that the IMD layers10151to1015Mare formed directly over respective barrier/adhesion layers1011.

FIGS.62,63,65-67, and69-75illustrate cross-sectional views of various intermediate stages of fabrication of a semiconductor device1800in accordance with some embodiments. In particular,FIGS.62,63,65-67, and69-75illustrate cross-sectional views of various intermediate stages of fabrication of an interconnect structure1801(seeFIG.75) over the structure ofFIG.1in accordance with some embodiments.

Referring toFIG.62, in some embodiments, the steps for forming the interconnect structure1801starts with forming a metallization layer18031(seeFIG.74) over the one or more ILD layers113and the contact plugs115and117. Process steps for forming the metallization layer18031start with forming conductive columns1009over respective contact plugs115as described above with reference toFIGS.45-47, and the description is not repeated herein.

Referring toFIG.63, a barrier/adhesion layer1805is formed along sidewalls and a top surface of each of the conductive columns1009. The barrier/adhesion layers1805may be formed using similar materials as the barrier/adhesion layer129described above with reference toFIGS.3-6, and the description is not repeated herein. In some embodiments, the barrier/adhesion layers1805have a thickness between about 0.5 nm and about 5 nm.

FIG.64is a flow diagram illustrating a method1900of forming the barrier/adhesion layers1805(seeFIG.63) in accordance with some embodiments.FIGS.65-67illustrate cross-sectional views of various intermediate stages of fabrication of the barrier/adhesion layers1805in accordance with the method1900. Referring toFIGS.64and65, in step1901, a metallic material1807is deposited over the one or more ILD layers113and along the sidewalls and top surfaces of the conductive columns1009. The metallic material1807may be formed using similar materials and methods as the metallic material133described above with reference toFIG.5and the description is not repeated herein.

Referring toFIGS.64and66, in step1903, the metallic material1807is patterned to remove portions of the metallic material1807that are in physical contact with the one or more ILD layers113and the contact plugs115and117, such that remaining portions of the metallic material1807extend along the sidewalls and top surfaces of the conductive columns1009. In some embodiments, the patterning process may comprise suitable photolithography and etch processes. The suitable etch process may comprise a dry etch process, a wet etch process, a combination thereof, or the like.

Referring toFIGS.64and67, in step1905, a chalcogen treatment process1809is performed on remaining portions of the metallic material1807to form the barrier/adhesion layers1805(seeFIG.63). In some embodiments, the chalcogen treatment process1809is similar to the chalcogen treatment process135described above with reference toFIG.6and the description is not repeated herein.

FIG.68is a flow diagram illustrating a method2000of forming the barrier/adhesion layers1805(seeFIG.63) in accordance with some embodiments.FIGS.69-71illustrate cross-sectional views of various intermediate stages of fabrication of the barrier/adhesion layers1805in accordance with the method2000. Referring toFIGS.68and69, in step2001, a metallic material1807is deposited over the one or more ILD layers113and along the sidewalls and top surfaces of the conductive columns1009. The metallic material1807may be formed using similar materials and methods as the metallic material133described above with reference toFIG.5and the description is not repeated herein.

Referring toFIGS.68and70, in step2003, a chalcogen treatment process1809is performed on remaining portions of the metallic material1807to form a treated metallic material1811. In some embodiments, the chalcogen treatment process1809is similar to the chalcogen treatment process135described above with reference to FIG.6and the description is not repeated herein. In alternative embodiments, the layer1811is formed using a single-step process such as ALD, CVD, or the like. In such embodiments, ALD or CVD may be performed using a suitable metal-containing precursor and a suitable chalcogen-containing precursor.

Referring toFIGS.68and71, in step2005, the treated metallic material1811is patterned to remove portions of the treated metallic material1811that are in physical contact with the one or more ILD layers113and the contact plugs115and117, such that remaining portions of the treated metallic material1811extend along the sidewalls and top surfaces of the conductive columns1009and form the barrier/adhesion layers1805. In some embodiments, the patterning process may comprise suitable photolithography and etch processes. The suitable etch process may comprise a dry etch process, a wet etch process, a combination thereof, or the like.

Referring toFIG.72, after forming the barrier/adhesion layers1805, a capping layer10131is formed over the barrier/adhesion layers1805and over the one or more ILD layers113and the contact plugs115and117as described above with reference toFIG.49and the description is not repeated herein. In the illustrated embodiment, the capping layer10131is formed having a thickness such that the capping layer10131partially fills gaps between adjacent conductive columns1009. Subsequently, an IMD layer10151is formed over the capping layer10131as described above with reference toFIG.49and the description is not repeated herein. In the illustrated embodiment, the IMD layer10151is formed having a thickness such that the IMD layer10151overfills the gaps between adjacent conductive columns1009.

Referring toFIG.73, portions of the barrier/adhesion layers1805, the capping layer10131, and the IMD layer10151extending above top surfaces of the conductive columns1009are removed to expose the top surfaces of the conductive columns1009. In some embodiments, the removal process may also remove portions of the conductive columns1009. The removal process may be a planarization process comprising a CMP process, a grinding process, an etching process, a combination thereof, or the like. The remaining portions of the conductive columns1009and respective barrier/adhesion layers1805form conductive vias18131. In some embodiments, after performing the planarization process, top surfaces of the conductive vias18131are substantially coplanar or level with a top surface of the capping layer10131and a top surface of the IMD layer10151within process variations of the planarization process.

Referring toFIG.74, after performing the planarization process, an ESL1411is formed over the IMD layer10151and the conductive vias18131, and an IMD layer1451is formed over the ESL1411as described above with reference toFIG.12and the description is not repeated herein. Subsequently, conductive lines1571are formed in the IMD layer1451and the ESL1411as described above with reference toFIGS.12-16and the description is not repeated herein. In some embodiments, the conductive lines1571are in physical contact with respective conductive vias18131.

Referring toFIG.75, one or more metallization layers similar to the metallization layer18031are formed over the metallization layer18031until a metallization layer1803Mis formed. In some embodiments, the metallization layer1803Mis the final metallization layer of the interconnect structure1801. In some embodiments, M may be between 1 and 12. In some embodiments, the intermediate metallization layers between the metallization layer18031and the metallization layer1803Mare formed in a similar manner as the metallization layer18031and the description is not repeated herein. In other embodiments, the metallization layer1803Mis not the final metallization layer of the interconnect structure1801and additional metallization layers are formed over the metallization layer1803M.

In some embodiments, process steps for forming the metallization layer1803Mstart with forming an IMD layer1015M, a capping layer1013M, and conductive vias1813Mover a previous metallization layer. In some embodiments, the IMD layer1015Mis formed using similar materials and methods as the IMD layer10151and the description is not repeated herein. In some embodiments, the capping layer1013Mis formed using similar materials and methods as the capping layer10131and the description is not repeated herein. In some embodiments, features of the conductive vias1813Mare similar to features of the conductive vias18131, with similar features being labeled by similar numerical references. In some embodiments, the conductive vias1813Mmay be formed using process steps as described above with reference toFIGS.62-73, and the description is not repeated herein.

In some embodiments, after forming the conductive vias1813M, an ESL143Mis formed over the conductive vias1813Mand the IMD layer1015M. In some embodiments, the ESL143Mis formed using similar materials and methods as the ESL1411and the description is not repeated herein. Subsequently, an IMD layer145Mis formed over the ESL143M. In some embodiments, the IMD layer145Mis formed using similar materials and methods as the IMD layer1451and the description is not repeated herein. Subsequently, conductive lines157Mare formed in the IMD layer145Mand the ESL143M. In some embodiments, features of the conductive lines157Mare similar to features of the conductive lines1571, with similar features being labeled by similar numerical references. In some embodiments, the conductive lines157Mmay be formed using process steps as described above with reference toFIGS.12-16, and the description is not repeated herein.

FIG.76illustrates a cross-sectional view of a semiconductor device2100in accordance with some embodiments. The semiconductor device2100is similar to the semiconductor device1800(seeFIG.75), with similar features being labeled by similar numerical references. In some embodiments, the interconnect structure2101(comprising the metallization layers21031to2103M) of the semiconductor device2100may be formed using process steps similar to the process steps for forming the interconnect structure1801of the semiconductor device1800described above with reference toFIGS.62-75, and the description is not repeated herein. In the illustrated embodiment, the formation of the capping layers10131to1013M(seeFIG.75) is omitted, such that the IMD layers10151to1015Mare formed directly over respective barrier/adhesion layers1805.

FIG.77illustrates a cross-sectional view of a semiconductor device2200in accordance with some embodiments. The semiconductor device2200is similar to the semiconductor device1800(seeFIG.75), with similar features being labeled by similar numerical references. In some embodiments, the interconnect structure2201(comprising the metallization layers22031to2203M) of the semiconductor device2200may be formed using process steps similar to the process steps for forming the interconnect structure1801of the semiconductor device1800described above with reference toFIGS.62-75, and the description is not repeated herein. In the illustrated embodiment, the formation of the ESLs1411to143M(seeFIG.75) is omitted, such that the IMD layers1451to145Mare formed directly over the IMD layers10151to1015M, respectively.

FIG.78illustrates a cross-sectional view of a semiconductor device2300in accordance with some embodiments. The semiconductor device2300is similar to the semiconductor device2200(seeFIG.77), with similar features being labeled by similar numerical references. In some embodiments, the interconnect structure2301(comprising the metallization layers23031to2303M) of the semiconductor device2300may be formed using process steps similar to the process steps for forming the interconnect structure2201of the semiconductor device2200described above with reference toFIG.77and the description is not repeated herein. In the illustrated embodiment, the formation of the capping layers10131to1013M(seeFIG.77) is omitted, such that the IMD layers10151to1015Mare formed directly over respective barrier/adhesion layers1805.

FIGS.79-81illustrate cross-sectional views of various intermediate stages of fabrication of a semiconductor device2400in accordance with some embodiments. In particular,FIGS.79-81illustrate cross-sectional views of various intermediate stages of fabrication of an interconnect structure2401(seeFIG.81) over the structure ofFIG.1in accordance with some embodiments.

Referring toFIG.79, in some embodiments, the steps for forming the interconnect structure2401starts with forming a metallization layer24031(seeFIG.80) over the one or more ILD layers113and the contact plugs115and117. Process steps for forming the metallization layer24031start with forming an IMD layer10151, a capping layer10131, and conductive vias18131over the one or more ILD layers113and the contact plugs115and117. In some embodiments, the IMD layer10151, the capping layer10131, and the conductive vias18131are formed using process steps described above with reference toFIGS.62-73, and the description is not repeated herein.

Referring toFIG.80, after forming the conductive vias18131, an ESL1411is formed over the IMD layer10151and the conductive vias18131, and an IMD layer1451is formed over the ESL1411as described above with reference toFIG.12and the description is not repeated herein. Subsequently, conductive lines5071are formed in the IMD layer1451and the ESL1411as described above with reference toFIGS.28-32, and the description is not repeated herein. In some embodiments, the conductive lines5071are in physical contact with respective conductive vias18131.

Referring toFIG.81, one or more metallization layers similar to the metallization layer24031are formed over the metallization layer24031until a metallization layer2403Mis formed. In some embodiments, the metallization layer2403Mis the final metallization layer of the interconnect structure2401. In some embodiments, M may be between 1 and 12. In some embodiments, the intermediate metallization layers between the metallization layer24031and the metallization layer2403Mare formed in a similar manner as the metallization layer24031and the description is not repeated herein. In other embodiments, the metallization layer2403Mis not the final metallization layer of the interconnect structure2401and additional metallization layers are formed over the metallization layer2403M.

In some embodiments, process steps for forming the metallization layer2403Mstart with forming an IMD layer1015M, a capping layer1013M, and conductive vias1813Mover a previous metallization layer. In some embodiments, the IMD layer1015Mis formed using similar materials and methods as the IMD layer10151and the description is not repeated herein. In some embodiments, the capping layer1013Mis formed using similar materials and methods as the capping layer10131and the description is not repeated herein. In some embodiments, features of the conductive vias1813Mare similar to features of the conductive vias18131, with similar features being labeled by similar numerical references. In some embodiments, the conductive vias1813Mmay be formed using process steps as described above with reference toFIGS.62-73, and the description is not repeated herein.

In some embodiments, after forming the conductive vias1813M, an ESL143Mis formed over the conductive vias1813Mand the IMD layer1015M. In some embodiments, the ESL143Mis formed using similar materials and methods as the ESL1411and the description is not repeated herein. Subsequently, an IMD layer145Mis formed over the ESL143M. In some embodiments, the IMD layer145Mis formed using similar materials and methods as the IMD layer1451and the description is not repeated herein. Subsequently, conductive lines507Mare formed in the IMD layer145Mand the ESL143M. In some embodiments, features of the conductive lines507Mare similar to features of the conductive lines5071, with similar features being labeled by similar numerical references. In some embodiments, the conductive lines507Mmay be formed using process steps as described above with reference toFIGS.28-32, and the description is not repeated herein.

FIG.82illustrates a cross-sectional view of a semiconductor device2500in accordance with some embodiments. The semiconductor device2500is similar to the semiconductor device2400(seeFIG.81), with similar features being labeled by similar numerical references. In some embodiments, the interconnect structure2501(comprising the metallization layers25031to2503M) of the semiconductor device2500may be formed using process steps similar to the process steps for forming the interconnect structure2401of the semiconductor device2400described above with reference toFIGS.79-81, and the description is not repeated herein. In the illustrated embodiment, the formation of the capping layers10131to1013M(seeFIG.81) is omitted, such that the IMD layers10151to1015Mare formed directly over respective barrier/adhesion layers1805.

FIG.83illustrates a cross-sectional view of a semiconductor device2600in accordance with some embodiments. The semiconductor device2600is similar to the semiconductor device2400(seeFIG.81), with similar features being labeled by similar numerical references. In some embodiments, the interconnect structure2601(comprising the metallization layers26031to2603M) of the semiconductor device2600may be formed using process steps similar to the process steps for forming the interconnect structure2401of the semiconductor device2400described above with reference toFIGS.79-81, and the description is not repeated herein. In the illustrated embodiment, the formation of the ESLs1411to143M(seeFIG.81) is omitted, such that the IMD layers1451to145Mare formed directly over the IMD layers10151to1015M, respectively.

FIG.84illustrates a cross-sectional view of a semiconductor device2700in accordance with some embodiments. The semiconductor device2700is similar to the semiconductor device2600(seeFIG.83), with similar features being labeled by similar numerical references. In some embodiments, the interconnect structure2701(comprising the metallization layers27031to2703M) of the semiconductor device2700may be formed using process steps similar to the process steps for forming the interconnect structure2601of the semiconductor device2600described above with reference toFIG.83and the description is not repeated herein. In the illustrated embodiment, the formation of the capping layers10131to1013M(seeFIG.83) is omitted, such that the IMD layers10151to1015Mare formed directly over respective barrier/adhesion layers1805.

FIG.85illustrates a cross-sectional view of a semiconductor device2800in accordance with some embodiments. In some embodiments, some features of the semiconductor device2800are similar to features of the semiconductor device100(seeFIG.17), with similar features being labeled by similar numerical references. In some embodiments, the semiconductor device2800further includes an interconnect structure2801formed over the one or more ILD layers113and the contact plugs115and117. In some embodiments, the interconnect structure2801comprises metallization layers28031to2803M. In some embodiments, M may be between 1 and 12. Each of the metallization layers28031to2803Mmay be similar to any of metallization layers1211,2031,3031,4031,5031,6031,7031,8031,9031,10031,11031,12031,13031,14031,15031,16031,17031,18031,21031,22031,23031,24031,25031,26031, and27031(seeFIGS.17,18,25,26,33,34,37,38,44,52-55,58-61,75-78, and81-84, respectively). In some embodiments, each or some of the metallization layers28031to2803Mmay have a similar structure.

FIG.86Aillustrates a cross-sectional view of a stacked semiconductor device2900in accordance with some embodiments. In some embodiments, the stacked semiconductor device2900comprises a first semiconductor device2901bonded to a second semiconductor device2903. In the illustrated embodiment, the first semiconductor device2901comprises an integrated circuit die or a package comprising one or more integrated circuit dies, and the second semiconductor device2903comprises an integrated fan-out (InFO) package. Accordingly, the stacked semiconductor device2900may also be referred to as a package-on-package (PoP) device.

In some embodiments, one or more integrated circuit dies of the first semiconductor device2901may be a logic die (e.g., central processing unit (CPU), graphics processing unit (GPU), neural processing unit (NPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die (comprising, for example, SRAM L1, SRAM L2 circuitry, the like, or a combination thereof), etc.), a power management die (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) dies), the like, or combinations thereof. In the illustrated embodiment, the one or more integrated circuit dies of the first semiconductor device2901are memory dies, such that the first semiconductor device2901is a memory device.

In some embodiments, the first semiconductor device2901further comprises connectors2905providing electrical connections for the one or more integrated circuit dies of the first semiconductor device2901. The connectors2905may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like.

In some embodiments, the second semiconductor device2903comprises an integrated circuit die2907encapsulated in an encapsulant2909. The integrated circuit die2907may be a logic die (e.g., central processing unit (CPU), graphics processing unit (GPU), neural processing unit (NPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die (comprising, for example, SRAM L1, SRAM L2 circuitry, the like, or a combination thereof), etc.), a power management die (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) dies), the like, or combinations thereof. In the illustrated embodiment, the integrated circuit die2907comprises a logic die, such that the second semiconductor device2903is logic device. The encapsulant2909may be a molding compound, a polymer, an epoxy, silicon oxide filler material, the like, or a combination thereof, and may be applied by compression molding, transfer molding, or the like. In other embodiments, the encapsulant2909may comprise a polymer material, a dielectric material, or the like.

In some embodiments, the second semiconductor device2903further includes conductive columns2911extending through the encapsulant2909. The conductive columns2911may be formed of a suitable conductive material such as, for example, copper.

In some embodiments, a redistribution structure2913is formed on an active side of the integrated circuit die2907and on the encapsulant2909. The redistribution structure2913may comprise one or more insulating layers2915and metallization patterns2917within the one or more insulating layers2915. The one or more insulating layers2915may comprise a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. The metallization patterns2917may comprise conductive traces and vias and may be made of a suitable conductive material such as for example, copper.

In some embodiments, under bump metallizations (UBMs)2919are formed on the redistribution structure2913and connectors2921are formed on the UBMs2919. In some embodiments, the UBMs2919include three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. Other arrangements of materials and layers, such as an arrangement of chrome/chrome-copper alloy/copper/gold, an arrangement of titanium/titanium tungsten/copper, or an arrangement of copper/nickel/gold, may be also utilized for the formation of the UBMs2919. The connectors2921may be BGA connectors, solder balls, metal pillars, C4 bumps, micro bumps, ENEPIG formed bumps, or the like.

In some embodiments, the connectors2905are reflowed to attach the first semiconductor device2901to the conductive columns2911of the second semiconductor device2903. The connectors2905electrically and/or physically couple the first semiconductor device2901to the second semiconductor device2903.

In some embodiments, an underfill (not shown) may be formed between the first semiconductor device2901and the second semiconductor device2903, and surrounding the connectors2905. The underfill may be formed by a capillary flow process after the first semiconductor device2901is attached to the second semiconductor device2903or may be formed by a suitable deposition method before the first semiconductor device2901is attached to the second semiconductor device2903.

FIG.86Billustrates a magnified cross-sectional view of the conductive columns2911of the first semiconductor device2901(seeFIG.86A) in accordance with some embodiments. In some embodiments, process steps for forming the conductive column2911include pattering the encapsulant2909to form an opening therein, forming a barrier/adhesion layer2923along a bottom and the sidewalls of the opening, forming a seed layer2925over the barrier/adhesion layer2923, filling the opening with the conductive fill layer2927, and performing a planarization process (such as, for example, a CMP process) to remove excess portions of the barrier/adhesion layer2923, the seed layer2925and the conductive fill layer2927.

In some embodiments, the barrier/adhesion layer2923may be formed using similar materials and methods as barrier/adhesion layer129described above with reference toFIGS.3-6and the description is not repeated herein. In some embodiments, the seed layer2925may be formed using similar materials and methods as the seed layer139described above with reference toFIG.10and the description is not repeated herein. In some embodiments, the conductive fill layer2927may be formed using similar materials and methods as the conductive fill layer155described above with reference toFIG.15and the description is not repeated herein.

Referring back toFIG.86A, in some embodiments, barrier/adhesion layers such as barrier/adhesion layer2923(seeFIG.86B) may be also used while forming the metallization patterns2917of the redistribution structure2913of the first semiconductor device2901.

FIG.87Aillustrates a cross-sectional view of a stacked semiconductor device3000in accordance with some embodiments. In some embodiments, the stacked semiconductor device3000includes a first semiconductor device3001bonded to a package substrate3003. In the illustrated embodiment, the first semiconductor device3001includes an InFO package.

In some embodiments, the first semiconductor device3001includes an integrated circuit dies3005A and3005B encapsulated in an encapsulant3007. Each of the integrated circuit dies3005A and3005B may be a logic die (e.g., central processing unit (CPU), graphics processing unit (GPU), neural processing unit (NPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die (comprising, for example, SRAM L1, SRAM L2 circuitry, the like, or a combination thereof), etc.), a power management die (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) dies), the like, or combinations thereof. In some embodiments, the integrated circuit die3005A and the integrated circuit die3005B comprise a same type of a die. In other embodiments, the integrated circuit die3005A and the integrated circuit die3005B comprise different types of dies.

The encapsulant3007may be formed using similar materials and methods as the encapsulant2909described above with reference toFIG.86Aand the description is not repeated herein. In some embodiments, the encapsulant3007extends along sidewalls of the integrated circuit dies3005A and3005B and fills a gap between the integrated circuit die3005A and the integrated circuit die3005B.

In some embodiments, a redistribution structure3009is formed on active sides of the integrated circuit die3005A and the integrated circuit die3005B, and on the encapsulant3007. The redistribution structure3009may comprise one or more insulating layers (not shown) and metallization patterns (not shown) within the one or more insulating layers. In some embodiments, the redistribution structure3009may be formed using similar materials and methods as the redistribution structure2913described above with reference toFIG.86Aand the description is not repeated herein.

In some embodiments, the first semiconductor device3001further comprises connectors3011bonded to the redistribution structure3009. The connectors3011may be BGA connectors, solder balls, metal pillars, C4 bumps, micro bumps, ENEPIG formed bumps, or the like.

In some embodiments, the package substrate3003includes a substrate core3015and bond pads3017over the substrate core3015. The substrate core3015may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may also be used. Additionally, the substrate core3015may be a SOI substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. The substrate core3015is, in one alternative embodiment, based on an insulating core such as a fiberglass reinforced resin core. One example core material is fiberglass resin such as FR4. Alternatives for the core material include bismaleimide-triazine BT resin, or alternatively, other PCB materials or films. Build up films such as ABF or other laminates may be used for substrate core3015.

In some embodiments, the substrate core3015may include active and passive devices (not shown). A wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the design for the stacked semiconductor device3000. The devices may be formed using any suitable methods.

The substrate core3015may also include metallization layers (not shown) and vias3019, with the bond pads3017being physically and/or electrically coupled to the metallization layers and vias3019. The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like). In other embodiments, the substrate core3015is substantially free of active and passive devices. The vias3019may be also referred to as through vias or through substrate vias.

The package substrate3003further includes connectors3021attached to substrate core3015. The connectors3021provide electrical connector to the package substrate3003and the semiconductor devices bonded to the package substrate3003. The connectors3021may be BGA connectors, solder balls, metal pillars, C4 bumps, micro bumps, ENEPIG formed bumps, or the like.

In some embodiments, the connectors3011are reflowed to attach the first semiconductor device3001to bond pads3017of the package substrate3003. The connectors3011electrically and/or physically couple the package substrate3003, including metallization layers and vias3019in the substrate core3015, to the first semiconductor device3001.

In some embodiments, an underfill3013may be formed between the first semiconductor device3001and the package substrate3003and surrounding the connectors3011. The underfill3013may be formed by a capillary flow process after the first semiconductor device3001is attached to the package substrate3003or may be formed by a suitable deposition method before the first semiconductor device3001is attached to the package substrate3003.

FIG.87Billustrates a magnified cross-sectional view of the through via3019of the package substrate3003(seeFIG.87A) in accordance with some embodiments. In some embodiments, process steps for forming the through via3019include pattering the substrate core3015to form an opening therein, forming an insulating liner3023along a bottom and the sidewalls of the opening, forming a barrier/adhesion layer3025over the insulating liner3023, forming a seed layer3027over the barrier/adhesion layer3025, filling the opening with the conductive fill layer3029, and performing a planarization process (such as, for example, a CMP process) to remove excess portions of the insulating liner3023, the barrier/adhesion layer3025, the seed layer3027and the conductive fill layer3029. In some embodiments when the substrate core3015is formed of an insulating material, the insulating liner3023may be omitted.

In some embodiments, the insulating liner3023comprises silicon oxide, silicon nitride, silicon oxynitride, a combination thereof, or the like, may be formed using CVD, ALD, a combination thereof, or the like. In some embodiments, the barrier/adhesion layer3025may be formed using similar materials and methods as barrier/adhesive layer129described above with reference toFIGS.3-6and the description is not repeated herein. In some embodiments, the seed layer3027may be formed using similar materials and methods as the seed layer139described above with reference toFIG.10and the description is not repeated herein. In some embodiments, the conductive fill layer3029may be formed using similar materials and methods as the conductive fill layer155described above with reference toFIG.15and the description is not repeated herein.

Referring back toFIG.87A, in some embodiments, barrier/adhesion layers such as the barrier/adhesion layer3025(seeFIG.87B) may be also used while forming the metallization patterns of the redistribution structure3009of the first semiconductor device3001or while forming an interconnect structure of the package substrate3003.

FIG.88Aillustrates a cross-sectional view of a semiconductor device3100in accordance with some embodiments. In some embodiments, the semiconductor device3100is an InFO package. In some embodiments, the semiconductor device3100may include an integrated circuit die3101encapsulated in an encapsulant3103.

The integrated circuit die3101may be a logic die (e.g., central processing unit (CPU), graphics processing unit (GPU), neural processing unit (NPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die (comprising, for example, SRAM L1, SRAM L2 circuitry, the like, or a combination thereof), etc.), a power management die (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) dies), the like, or combinations thereof. In the illustrated embodiment, the integrated circuit die3101is an RF die.

The encapsulant3103may be formed using similar materials and methods as the encapsulant2909described above with reference toFIG.86Aand the description is not repeated herein. The encapsulant3103extends along sidewalls of the integrated circuit die3101.

In some embodiments, the semiconductor device3100further includes conductive columns3105and antennas3107extending though the encapsulant3103. The conductive columns3105and antennas3107may be formed of a suitable conductive material such as, for example, copper.

In some embodiments, the semiconductor device3100further includes a first redistribution structure3109on a backside of the integrated circuit die3101. The first redistribution structure3109may be also referred to as a backside redistribution structure. In some embodiments, an adhesive3115is interposed between the first redistribution structures3109and the backside of the integrated circuit die3101. The adhesive3115may be any suitable adhesive, epoxy, die attach film (DAF), or the like. The first redistribution structure3109may comprise one or more insulating layers3111and metallization patterns3113within the one or more insulating layers3111. The one or more insulating layers3111may comprise a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. The metallization patterns3113comprise conductive traces and vias and may be made of a suitable conductive material such as for example, copper.

In some embodiments, a second redistribution structure3117is formed on a front side of the integrated circuit die3101. The second redistribution structure3117may be also referred to as a front-side redistribution structure. The second redistribution structure3117may comprise one or more insulating layers3119and metallization patterns3121within the one or more insulating layers3119. The one or more insulating layers3119may be formed using similar materials and methods as the one or more insulating layers3111and the description is not repeated herein. The metallization patterns3121comprise conductive traces and vias and may be made of a suitable conductive material such as for example, copper.

In some embodiments, UBMs3123are formed on the second redistribution structure3117and connectors3125are formed on the UBMs3123. In some embodiments, the UBMs3123may be formed using similar materials and methods as the UBMs2919described above with reference toFIG.86Aand the description is not repeated herein. The connectors3125may be BGA connectors, solder balls, metal pillars, C4 bumps, micro bumps, ENEPIG formed bumps, or the like.

In some embodiments, a dielectric layer3127is formed over the first redistribution structure3109and antennas3129are formed over the dielectric layer3127. In some embodiments, the antennas3129are electrically coupled to the integrated circuit die3101through the first redistribution structure3109. The dielectric layer3127may be formed of an oxide, a nitride, SiC, SiN, SiOC, a combination thereof, or the like. The antennas3129may be formed of a suitable conductive material such as, for example, copper.

FIG.88Billustrates a magnified cross-sectional view of the conductive column3105of the semiconductor device3100(seeFIG.88A) in accordance with some embodiments. In some embodiments, process steps for forming the conductive column3105include pattering the encapsulant3103to form an opening therein, forming a barrier/adhesion layer3131along a bottom and the sidewalls of the opening, forming a seed layer3133over the barrier/adhesion layer3131, filling the opening with the conductive fill layer3135, and performing a planarization process (such as, for example, a CMP process) to remove excess portions of the barrier/adhesion layer3131, the seed layer3133and the conductive fill layer3135.

In some embodiments, the barrier/adhesion layer3131may be formed using similar materials and methods as barrier/adhesion layer129described above with reference toFIGS.3-6and the description is not repeated herein. In some embodiments, the seed layer3133may be formed using similar materials and methods as the seed layer139described above with reference toFIG.10and the description is not repeated herein. In some embodiments, the conductive fill layer3135may be formed using similar materials and methods as the conductive fill layer155described above with reference toFIG.15and the description is not repeated herein.

Referring back toFIG.88A, in some embodiments, barrier/adhesion layers such as barrier/adhesion layer3131(seeFIG.88B) may be also used while forming the metallization patterns3113of the first redistribution structure3109and the metallization patterns3121of the second redistribution structure3117.

In accordance with an embodiment, a device includes a substrate, a dielectric layer over the substrate, and a conductive interconnect in the dielectric layer. The conductive interconnect includes a barrier/adhesion layer and a conductive layer over the barrier/adhesion layer. The barrier/adhesion layer includes a material having a chemical formula MXn, with M being a transition metal element, X being a chalcogen element, and n being between 0.5 and 2.

Embodiments may include one or more of the following features. The device where the conductive layer includes a seed layer over and in physical contact with the barrier/adhesion layer. The device where a top surface of the dielectric layer is level with a top surface of the seed layer. The device where the conductive layer further includes a conductive fill layer over the seed layer. The device where a top surface of the dielectric layer is level with a top surface of the conductive fill layer. The device where the barrier/adhesion layer has a layered structure. The device where the barrier/adhesion layer has a thickness between about 0.5 nm and about 3 nm.

In accordance with another embodiment, a device includes a substrate, a first dielectric layer over the substrate, and a conductive via in the first dielectric layer. The conductive via includes a first barrier/adhesion layer comprising a first material and a first conductive layer over the first barrier/adhesion layer. The first material has a chemical formula MXn, with M being a transition metal element, X being a chalcogen element, and n being between 0.5 and 2. The device further includes a second dielectric layer over the first dielectric layer and the conductive via and a conductive line in the second dielectric layer. The conductive line includes a second barrier/adhesion layer comprising the first material and a second conductive layer over the second barrier/adhesion layer.

Embodiments may include one or more of the following features. The device where the first barrier/adhesion layer has a layered structure. The device where the first conductive layer includes a first seed layer over the first barrier/adhesion layer, the first seed layer being an uppermost layer of the conductive via. The device where the first conductive layer includes a first seed layer over the first barrier/adhesion layer, and a first conductive fill layer over the first seed layer, a top surface of the first conductive fill layer being level with a top surface of the first dielectric layer. The device where the second conductive layer includes a second seed layer over the second barrier/adhesion layer, the second seed layer being an uppermost layer of the conductive line. The device where the second conductive layer includes a second seed layer over the second barrier/adhesion layer, and a second conductive fill layer over the second seed layer, a top surface of the second conductive fill layer being level with a top surface of the second dielectric layer. The device where the second barrier/adhesion layer is in physical contact with the first conductive layer.

In accordance with yet another embodiment, a method includes forming a dielectric layer over a substrate, patterning the dielectric layer to form an opening in the dielectric layer, forming a barrier/adhesion layer along a bottom and sidewalls of the opening, and depositing a conductive layer over the barrier/adhesion layer in the opening. A material of the barrier/adhesion layer has a chemical formula MXn, with M being a transition metal element, X being a chalcogen element, and n being between 0.5 and 2. Forming the barrier/adhesion layer includes depositing a layer of the transition metal element along the bottom and the sidewalls of the opening, and performing a chalcogen treatment on the layer of the transition metal element.

Embodiments may include one or more of the following features. The method where depositing the layer of the transition metal element comprises performing a physical vapor deposition (PVD) process. The method where performing the chalcogen treatment comprises performing a plasma enhanced chemical deposition (PECVD) process using a precursor comprising the chalcogen element. The method where depositing the conductive layer includes depositing a seed layer over the barrier/adhesion layer in the opening, the seed layer filling the opening. The method where depositing the conductive layer includes depositing a seed layer over the barrier/adhesion layer in the opening, and depositing a conductive fill material over the seed layer in the opening, the conductive fill material filling the opening. The method where the barrier/adhesion layer includes a plurality of sub-layers.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.