Patent ID: 12237304

DETAILED DESCRIPTION

FIG.1illustrates a perspective view of a semiconductor package according to some embodiments.FIGS.2and4illustrate plan views of a semiconductor package according to some embodiments.FIGS.3A and3Billustrate cross-sectional views taken along lines A-A′ and B-B′ ofFIG.2.

Referring toFIGS.1,2,3A, and3B, a semiconductor package may include a package substrate100, a first chip stack CS1on the package substrate100, a second chip stack CS2on the first chip stack CS1, first and second upper wires UW1and UW2, first and second lower wires LW1and LW2, first, second, and third connection wires CW1, CW2, and CW3, and a molding layer300. As used herein, the terms “first,” “second,” and the like are merely for identification and differentiation, and are not intended to imply or require sequential inclusion (e.g., a third element and a fourth element may be described without implying or requiring the presence of a first element or second element), nor are they intended to be fixed to a particular element.

A printed circuit board (PCB), a flexible substrate, a tape substrate, or another suitable kind of substrate may be used as the package substrate100. In an implementation, the package substrate100may be a printed circuit board in which internal lines are formed. The package substrate100may include bonding pads BP1to BP4on a top surface thereof and coupling pads103on a bottom surface thereof. The bonding pads BP1to BP4may be electrically connected through the internal lines to the coupling pads103. The bonding pads BP1to BP4may be electrically connected through metallic wires to chip pads of the first and second chip stacks CS1and CS2. The coupling pads103may be attached to connection terminals105such as solder balls or solder bumps.

In an implementation, the bonding pads BP1to BP4may include first and second bonding pads BP1and BP2that are alternately arranged along a first direction D1parallel to the top surface of the package substrate100, third bonding pads BP3that are spaced apart from the first bonding pads BP1in a second direction D2intersecting the first direction D1, and fourth bonding pads BP4that are spaced apart in the second direction D2from the second bonding pads BP2.

The first and second bonding pads BP1and BP2may be closer (e.g., in the second direction D2) to the first chip stack CS1than the third and fourth bonding pads BP3and BP4are to the first chip stack CS1. A distance (e.g., in the second direction D2) between the first bonding pads BP1and the third bonding pads BP3may be substantially the same as a distance between the second bonding pads BP2and the fourth bonding pads BP4.

The first and third bonding pads BP1and BP3may be connected to signal terminals, and the second and fourth bonding pads BP2and BP4may be connected to power/ground terminals. In an implementation, as illustrated in the drawings, the number of the first bonding pads BP1and of the third bonding pads BP3may be three, and the number of the second bonding pads BP2and of the fourth bonding pads BP4may be two.

The first chip stack CS1may include a plurality of first chips110that are stacked through one or more adhesion layers ADL on the package substrate100. The first chips110may be stacked (e.g., offset) along the second direction D2on the package substrate100, constituting a staircase or cascade structure.

Each of the first chips110may have a structure in which chip pads are arranged on an edge of the first chip110, and the first chips110may be stacked such that each of the first chips110may expose chip pads of its underlying first chip110.

Each of the first chips110may include first signal pads111through which signals are input and output, and may further include first power/ground pads113through which power or ground signals are input. The first signal pads111and the first power/ground pads113may be alternately arranged along the first direction D1.

The first chips110may be memory chips that store data. In an implementation, the first chips110may be dynamic random access memory (DRAM) chips, static random access memory (SRAM) chips, NAND Flash memory chips, phase change random access memory (PRAM) chips, resistive random access memory (RRAM) chips, ferromagnetic random access memory (FeRAM) chips, or magnetic random access memory (MRAM) chips.

The second chip stack CS2may include a plurality of second chips120that are stacked through one or more adhesion layers ADL on the first chip stack CS1. The second chips120may be stacked along the second direction D2on the first chip stack CS1, constituting a staircase or cascade structure. The second chips120may be attached to each other through the adhesion layer ADL. The second chips120may be memory chips that store data and may have the same properties as those of the first chips110.

Each of the second chips120may have a structure in which chip pads are arranged on an edge of the second chip120, and the second chips120may be stacked such that each of the second chips120may expose chip pads of its underlying second chip120.

Each of the second chips120may include second signal pads121through which signals are input and output, and may further include second power/ground pads123through which power or ground signals are input. The second signal pads121and the second power/ground pads123may be alternately arranged along the first direction D1.

Chip pads of each of the first and second chips110and120may be arranged along the first direction D1at a first pitch P1, and on the package substrate100, the first and second bonding pads BP1and BP2(or the third and fourth bonding pads BP3and BP4) may be arranged along the first direction D1at a second pitch P2. In an implementation, the second pitch P2may be substantially the same as the first pitch P1. In an implementation, the first pitch P1may range from about 50 μm to about 200 μm.

In an implementation, referring toFIG.4, on the package substrate100, the first and second bonding pads BP1and BP2(or the third and fourth bonding pads BP3and BP4) may be arranged along the first direction D1at a second pitch P2, and the second pitch P2may be greater than the first pitch P1of chip pads on each of the first and second chips110and120.

In an implementation, as illustrated in the drawings, the bonding pads BP1to BP4may each have a size greater than that of each of the chip pads111,113,121, and123of the first and second chips110and120, or the bonding pads may have a size substantially the same as that of chip pads.

In an implementation, input/output signals of the first chips110and input/output signals of the second chips120may be output through different channels from each other. The first signal pads111of the first chips110may be electrically separated from the second signal pads121of the second chips120. The first power/ground pads113of the first chips110may be electrically connected to the second power/ground pads123of the second chips120.

The first connection wires CW1may electrically connect chip pads of the first chips110to each other. In an implementation, the first signal pads111of the first chips110may be connected to each other through the first connection wires CW1, and the first power/ground pads113of the first chips110may be connected to each other through the first connection wires CW1.

The second connection wires CW2may electrically connect chip pads of the second chips120to each other. In an implementation, the second signal pads121of the second chips120may be connected to each other through the second connection wires CW2, and the second power/ground pads123of the second chips120may be connected to each other through the second connection wires CW2.

The third connection wires CW3may connect the first power/ground pads113of an uppermost first chip110to the second power/ground pads123of a lowermost second chip120.

The first lower wires LW1may connect the first signal pads111of a lowermost first chip110of the first chip stack CS1to the first bonding pads BP1of the package substrate100.

The second lower wires LW2may connect the first power/ground pads113of the lowermost first chip110to the second bonding pads BP2of the package substrate100.

The first upper wires UW1may connect the second signal pads121of the lowermost second chip120of the second chip stack CS2to the third bonding pads BP3of the package substrate100. The first upper wires UW1may pass over the first connection wires CW1and the first lower wires LW1, thereby being bonded to the third bonding pads BP3. The first upper wires UW1may be longer than the first lower wires LW1(e.g., in the second direction D2). The first upper wires UW1may have a length that is about 2 times to about 10 times that of the first lower wires LW1.

The second upper wires UW2may connect the second power/ground pads123of the lowermost second chip120to the fourth bonding pads BP4of the package substrate100. The second upper wires UW2may pass over the first connection wires CW1, the third connection wires CW3, and the second lower wires LW2, thereby being bonded to the fourth bonding pads BP4. The second upper wires UW2may be longer than the second lower wires LW2. The second upper wires UW2may have a length substantially the same as that of the first upper wires UW1. The second upper wires UW2may have a length that is about 2 times to about 10 times that of the second lower wires LW2.

Each of the second upper wires UW2may be between adjacent ones of the first upper wires UW1. In an implementation, when the second chips120are driven to operate, the second upper wires UW2may shield electrical interference or crosstalk between the first upper wires UW1. Accordingly, it is possible to help reduce or prevent a reduction in operating speed of the second chips120and to help improve signal integrity of the semiconductor package.

On the second chip stack CS2, two wires CW2and UW1may be bonded to each of the second signal pads121of the lowermost second chip120. In addition, the second chip stack CS2may be configured such that three wires CW2, CW3, and UW2may be bonded to each of the second power/ground pads123of the lowermost second chip120.

On the top surface of the package substrate100, the molding layer300may cover the first and second chip stacks CS1and CS2and the bonding wires LW1, LW2, UW1, UW2, CW1, CW2, and CW3. The molding layer300may have a thickness greater than a sum of thicknesses of the first and second chip stacks CS1and CS2(e.g., in a third direction D3). The molding layer300may include a dielectric polymer, e.g., an epoxy molding compound (EMC).

The following will discuss semiconductor packages according to various embodiments in conjunction with the accompanying drawings, and like numerals indicate like components. In addition, for brevity of description, omission may be made to avoid repetitive explanations of the same features as those of the embodiments mentioned above, and a difference thereof will be discussed.

FIG.5illustrates a plan view of a semiconductor package according to some embodiments.FIGS.6A and6Billustrate cross-sectional views taken along lines A-A′ and B-B′ ofFIG.5.

Referring toFIGS.5,6A, and6B, the first and second upper wires UW1and UW2may be electrically connected to an uppermost second chip120of the second chip stack CS2. In an implementation, the first upper wires UW1may connect the second signal pads121of the uppermost second chip120of the second chip stack CS2to the third bonding pads BP3of the package substrate100. The second upper wires UW2may connect the second power/ground pads123of the uppermost second chip120to the fourth bonding pads BP4of the package substrate100.

According to the present embodiment, two bonding wires may be bonded to each of chip pads included in the first and second chips110and120.

FIG.7illustrates a plan view of a semiconductor package according to some embodiments.FIGS.8A and8Billustrate cross-sectional views taken along lines A-A′ and B-B′ ofFIG.7.

Referring toFIGS.7,8A, and8B, the first upper wires UW1may connect the second signal pads121of the lowermost second chip120of the second chip stack CS2to the third bonding pads BP3of the package substrate100.

The second upper wires UW2may connect the first power/ground pads113of the lowermost first chip110of the first chip stack CS1to the fourth bonding pads BP4of the package substrate100. The second upper wires UW2may pass over the first lower wires LW1and may connect with the fourth bonding pads BP4. The second upper wires UW2may have a length different from that of the first upper wires UW1, e.g., the length of the second upper wires UW2may be less than that of the first upper wires UW1.

According to the present embodiment, the chip stack CS1may be configured such that three bonding wires may be bonded to each of the first power/ground pads113of the lowermost first chip110.

In an implementation, as illustrated in the drawings, the second upper wires UW2may be connected to the first power/ground pads113of the lowermost first chip110, or the second upper wires UW2may be connected to either one of the first chips110of the first chip stack CS1or one of the second chips120of the second chip stack CS2.

The first upper wires UW1may be connected to the lowermost second chip120, and the second upper wires UW2may be connected to the uppermost second chip120. In this case, the second upper wires UW2may be longer than the first upper wires UW1.

FIG.9illustrates a plan view of a semiconductor package according to some embodiments.FIGS.10A and10Billustrate cross-sectional views taken along lines A-A′ and B-B′ ofFIG.9.

Referring toFIGS.9,10A, and10B, the first chip stack CS1may include four first chips110that are stacked through one or more adhesion layers ADL on the package substrate100. The second chip stack CS2may include four second chips120that are stacked one or more adhesion layers ADL on the first chip stack CS1.

In an implementation, the number of stacked first chips110may be six, eight, sixteen, or the like. In an implementation, the number of stacked second chips120may be six, eight, sixteen, or the like. In an implementation, the number of stacked first chips110may be different from that of stacked second chips120.

As discussed above, the first connection wires CW1may connect the first chips110to each other, and the second connection wires CW2may connect the second chips120to each other.

The third connection wires CW3may connect the first power/ground pads113of the uppermost first chip110to the second power/ground pads123of the lowermost second chip120.

The first upper wires UW1may connect the second signal pads121of one of the second chips120to the third bonding pads BP3of the package substrate100. In an implementation, the first upper wires UW1may be connected to the second signal pads121of the lowermost second chip120.

The second upper wires UW2may connect the second power/ground pads123of one of the second chips120to the fourth bonding pads BP4of the package substrate100.

The second upper wires UW2may have a length substantially the same as that of the first upper wires UW1. In an implementation, the second upper wires UW2may have a length different from that of the first upper wires UW1. In an implementation, the first upper wires UW1may be connected to the lowermost second chip120, and the second upper wires UW2may be connected to another second chip120other than the lowermost second chip120.

FIGS.11A and11Billustrate plan views of a semiconductor package according to some embodiments.FIGS.12A and12Billustrate cross-sectional views taken along lines A-A′ and B-B′ ofFIG.11A.

Referring toFIGS.11A,12A, and12B, a semiconductor package according to the present embodiment may include a package substrate100, a first chip stack CS1, a second chip stack CS2on the first chip stack CS1, a controller chip200, first and second upper wires UW1and UW2, first and second lower wires LW1and LW2, first, second, and third connection wires CW1, CW2, and CW3, and a molding layer300.

The package substrate100, as discussed above, may include first and second bonding pads BP1and BP2that are alternately arranged along the first direction D1, third bonding pads BP3that are spaced apart in the second direction D2from the first bonding pads BP1, and fourth bonding pads BP4that are spaced apart in the second direction D2from the second bonding pads BP2. In this case, the first and second bonding pads BP1and BP2may be adjacent to the first chip stack CS1, and the third and fourth bonding pads BP3and BP4may be adjacent to the controller chip200.

The controller chip200may include chip pads that are arranged on or near an edge of the controller chip200. The chip pads of the controller chip200may be arranged along the first direction D1at a second pitch P2. The second pitch P2may be substantially the same as a first pitch P1of chip pads for each of the first and second chips110and120.

The chip pads of the controller chip200may include first and second chip pads CP1and CP2. The first and second chip pads CP1and CP2may be alternately arranged along the first direction D1. The first chip pads CP1of the controller chip200may input and output a plurality of control signals or data signals, and the second chip pads CP2may be provided with power or ground signals.

The controller chip200may include, e.g., a central processing unit (CPU), an internal memory, a buffer memory control unit, a host interface, and a flash interface.

In an implementation, a buffer memory chip may replace the controller chip200, and the buffer memory chip may be a volatile memory chip. In an implementation, the buffer memory chip may be a dynamic random access memory (DRAM) chip.

In an implementation, the first upper wires UW1may connect the second signal pads121of one of the second chips120to the first chip pads CP1of the controller chip200. The second upper wires UW2may connect the second power/ground pads123of one of the second chips120to the second chip pads CP2of the controller chip200.

The first lower wires LW1may connect the first signal pads111of one of the first chips110to the first bonding pads BP1of the package substrate100. The second lower wires LW2may connect the first power/ground pads113of one of the first chips110to the second bonding pads BP2of the package substrate100.

The first chip pads CP1of the controller chip200may be connected through first bonding wires W1to the third bonding pads BP3of the package substrate100. The second chip pads CP2of the controller chip200may be connected through second bonding wires W2to the fourth bonding pads BP4of the package substrate100.

According to the embodiment shown inFIG.11B, the controller chip200may be configured such that chip pads arranged along the first direction D1may constitute one column, and that chip pads may constitute three columns adjacent to an edge of the controller chip200.

In an implementation, the controller chip200may include first, second, and third columns that are sequentially disposed along the second direction D2, and chip pads that constitute the second column may include first and second chip pads CP1and CP2. The first and second chip pads CP1and CP2may be alternately arranged along the first direction D1. As discussed above, the first chip pads CP1may input and output a plurality of control signals or data signals, and the second chip pads CP2may be provided with power or ground signals.

In an implementation, the first upper wires UW1may connect the second signal pads121of one of the second chips120to the first chip pads CP1in the second column of the controller chip200. The second upper wires UW2may connect the second power/ground pads123of one of the second chips120to the second chip pads CP2in the second column of the controller chip200.

The first chip pads CP1in the second column of the controller chip200may be connected through the first bonding wires W1to the third bonding pads BP3of the package substrate100. The second chip pads CP2in the second column of the controller chip200may be connected through the second bonding wires W2to the fourth bonding pads BP4of the package substrate100.

FIG.13illustrates a plan view of a semiconductor package according to some embodiments.FIGS.14A and14Billustrate cross-sectional views taken along lines A-A′ and B-B′ ofFIG.13.

Different from the embodiment shown inFIGS.11A,12A, and12B, a semiconductor package according to the present embodiment shown inFIGS.13,14A, and14B may be configured such that the first chip stack CS1may include four first chips110that are stacked through one or more adhesion layers ADL on the package substrate100. The second chip stack CS2may include four second chips120that are stacked through one or more adhesion layers ADL on the first chip stack CS1.

In an implementation, the number of stacked first chips110may be six, eight, sixteen, or the like. In an implementation, the number of stacked second chips120may be six, eight, sixteen, or the like. In an implementation, the number of stacked first chips110may be different from that of stacked second chips120.

The first upper wires UW1may connect the second signal pads121of the lowermost second chip120to the first chip pads CP1of the controller chip200. The second upper wires UW2may connect the second power/ground pads123of the lowermost second chip120to the second chip pads CP2of the controller chip200.

The second upper wires UW2may have a length substantially the same as that of the first upper wires UW1. In an implementation, the second upper wires UW2may have a length different from that of the first upper wires UW1. In an implementation, the first upper wires UW1may be connected to the lowermost second chip120, and the second upper wires UW2may be connected to another second chip120other than the lowermost second chip120.

FIG.15illustrates a plan view of a semiconductor package according to some embodiments.FIGS.16A and16Billustrate cross-sectional views taken along lines A-A′ and B-B′ ofFIG.15.

Referring toFIGS.15,16A, and16B, a semiconductor package according to the present embodiment may include a package substrate100, a first chip stack CS1, a second chip stack CS2on the first chip stack CS1, a third chip stack CS3on the second chip stack CS2, first and second lower wires LW1and LW2, first to fourth upper wires UW1to UW4, first to fifth connection wires CW1to CW5, and a molding layer300.

The package substrate100may include first and second bonding pads BP1and BP2that are alternately arranged along the first direction D1, third bonding pads BP3spaced apart from the first bonding pads BP1in the second direction D2, fourth bonding pads BP4spaced apart in the second direction D2from the second bonding pads BP2, fifth bonding pads BP5spaced apart in the second direction D2from the third bonding pads BP3, and sixth bonding pads BP6spaced apart in the second direction D2from the fourth bonding pads BP4. The first and second bonding pads BP1and BP2may be closer to the first chip stack CS1than the third and fourth bonding pads BP3and BP4are to the first chip stack CS1. The third and fourth bonding pads BP3and BP4may be closer to the first chip stack CS1than the fifth and sixth bonding pads BP5and BP6are to the first chip stack CS1.

The first, third, and fifth bonding pads BP1, BP3, and BP5may have intervals in the second direction D2that are substantially the same as each other, and the second, fourth, and sixth bonding pads BP2, BP4, and BP6may have intervals in the second direction D2that are substantially the same as each other.

Each of the first, second, and third chips110,120, and130may have a structure in which chip pads are arranged on or near an edge thereof. The first, second, and third chips110,120, and130may be stacked along the second direction D2to constitute a staircase or cascade structure.

As discussed above, the first chips110of the first chip stack CS1may each include first signal pads111and first power/ground pads113. The second chips120of the second chip stack CS2may each include second signal pads121and second power/ground pads123.

The third chip stack CS3may include a plurality of third chips130that are stacked through one or more adhesion layers ADL on the second chip stack CS2. In an implementation, two third chips130may be stacked, or the number of stacked third chips130may be, e.g., four, six, eight, or the like. Each of the third chips130of the third chip stack CS3may include third signal pads131and third power/ground pads133that are alternately arranged along the first direction D1.

The first, second, and third chip stacks CS1, CS2, and CS3may output a plurality of input/output signals through different channels. The first, second, and third power/ground pads113,123, and133of the first, second, and third chips110,120, and130may be electrically connected to each other.

As discussed above, the first connection wires CW1may connect the first chips110to each other, and the second connection wires CW2may connect the second chips120to each other. The third connection wires CW3may connect the first power/ground pads113of the uppermost first chip110to the second power/ground pads123of the lowermost second chip120.

The fourth connection wires CW4may connect the third signal pads131of the third chips130to each other, and the fifth connection wires CW5may connect the third power/ground pads133of a lowermost one of the third chips130to the second power/ground pads123of the uppermost one of the second chips120.

In addition, as discussed above, the first upper wires UW1may connect the second signal pads121of one of the second chips120to the third bonding pads BP3of the package substrate100. The second upper wires UW2may connect the second power/ground pads123of one of the second chips120to the fourth bonding pads BP4of the package substrate100.

The third upper wires UW3may connect the third signal pads131of one of the third chips130to the fifth bonding pads BP5of the package substrate100. The fourth upper wires UW4may connect the third power/ground pads133of one of the third chips130to the sixth bonding pads BP6of the package substrate100.

The fourth upper wires UW4may have a length substantially the same as that of the third upper wires UW3. In an implementation, the fourth upper wires UW4may have a length different from that of the third upper wires UW3. In an implementation, the third upper wires UW3may be connected to the lowermost third chip130, and the fourth upper wires UW4may be connected to another third chip130other than the lowermost third chip130.

FIG.17illustrates a plan view of a semiconductor package according to some embodiments.FIGS.18A and18Billustrate cross-sectional views taken along lines A-A′ and B-B′ ofFIG.17.

According to the embodiment shown inFIGS.17,18A, and18B, a semiconductor package may include a package substrate100, a first chip stack CS1, a second chip stack CS2on the first chip stack CS1, a third chip stack CS3on the second chip stack CS2, a fourth chip stack CS4on the third chip stack CS3, first to fourth lower wires LW1to LW4, first to fourth upper wires UW1to UW4, first to sixth connection wires CW1to CW6, and a molding layer300.

The package substrate100, as discussed above, may include first to fourth bonding pads BP1to BP4. In addition, the package substrate100may further include fifth to eighth bonding pads BP5to BP8. The fifth and sixth bonding pads BP5and BP6may be alternately arranged along the first direction D1, the seventh bonding pads BP7may be spaced apart in the second direction D2from the fifth bonding pads BP5, and eighth bonding pads BP8may be spaced apart in the second direction D2from the sixth bonding pads BP6.

As discussed above, the first and second chip stacks CS1and CS2may respectively include a plurality of first chips110and a plurality of second chips120.

The third chip stack CS3may include a plurality of third chips130that are stacked through one or more adhesion layers ADL on the second chip stack CS2. In an implementation, two third chips130may be stacked, or the number of stacked third chips130may be, e.g., four, six, eight, or the like. Each of the third chips130of the third chip stack CS3may include third signal pads131and third power/ground pads133that are alternately arranged along the first direction D1.

The fourth chip stack CS4may include a plurality of fourth chips140that are stacked through one or more adhesion layers ADL on the third chip stack CS3. In an implementation, two fourth chips140may be stacked, or the number of stacked fourth chips140may be, e.g., four, six, eight, or the like. Each of the fourth chips140of the fourth chip stack CS4may each include fourth signal pads141and fourth power/ground pads143that are alternately arranged along the first direction D1.

In an implementation, each of the first to fourth chips110to140may have a first edge and a second edge, each first and second chip110and120may include chip pads that are arranged adjacent to the first edge, and each third and fourth chip130and140may include chip pads that are arranged adjacent to the second edge.

The first chips110and the second chips120may be stepwise stacked along the second direction D2, and the third chips130and the fourth chips140may be stepwise stacked along a direction opposite to the stacking direction of the first chips110and second chips120(e.g., the first chips110and second chips120may form a staircase structure in one direction, and the third chips130and the fourth chips140may form a staircase structure in a direction opposite to the one direction).

The first and second bonding pads BP1and BP2may be arranged adjacent to the first chip stack CS1, and the fifth and sixth bonding pads BP5and BP6may be arranged adjacent to the third chip stack CS3.

The first to fourth chip stacks CS1to CS4may output a plurality of input/output signals through different channels. In an implementation, the fourth connection wires CW4may electrically connect chip pads of the third chips130to each other. In an implementation, the third signal pads131of the third chips130may be connected to each other through the fourth connection wires CW4, and the third power/ground pads133of the third chips130may be connected to each other through the fourth connection wires CW4.

The fifth connection wires CW5may electrically connect chip pads of the fourth chips140to each other. In an implementation, the fourth signal pads141of the fourth chips140may be connected to each other through the fifth connection wires CW5, and the fourth power/ground pads143of the fourth chips140may be connected to each other through the fifth connection wires CW5.

The third and fourth power/ground pads133and143of the third and fourth chips130and140may be electrically connected to each other through the sixth connection wires CW6.

The third lower wires LW3may connect the third signal pads131of a lowermost third chip130of the third chip stack CS3to the fifth bonding pads BP5of the package substrate100.

The fourth lower wires LW4may connect the third power/ground pads133of the lowermost third chip130to the sixth bonding pads BP6of the package substrate100.

The third upper wires UW3may connect the fourth signal pads141of a lowermost fourth chip140of the fourth chip stack CS4to the seventh bonding pads BP7of the package substrate100. The third upper wires UW3may pass over the fourth connection wires CW4and the third lower wires LW3, thereby being bonded to the seventh bonding pads BP7. The third upper wires UW3may be longer than the third lower wires LW3.

The fourth upper wires UW4may connect the fourth power/ground pads143of the lowermost fourth chip140to the eighth bonding pads BP8of the package substrate100. The fourth upper wires UW4may pass over the fourth connection wires CW4, the sixth connection wires CW6, and the fourth lower wires LW4, thereby being bonded to the eighth bonding pads BP8. The fourth upper wires UW4may be longer than the fourth lower wires LW4. The fourth upper wires UW4may have a length substantially the same as that of the third upper wires UW3. Each of the fourth upper wires UW4may be between third upper wires UW3that are adjacent to each other in the first direction D1.

FIG.19illustrates a plan view of a semiconductor package according to some embodiments.FIG.20illustrates a cross-sectional view taken along line A-A′ ofFIG.19.

Referring toFIGS.19and20, a semiconductor package may include a package substrate100, first to fourth chip stack CS1to CS4, first to fourth lower wires LW1to LW4, first to fourth upper wires UW1to UW4, first to sixth connection wires CW1to CW6, and a molding layer300.

The package substrate100may include first to eighth bonding pads BP1to BP8that are provided in four columns along the second direction D2, and on each column, corresponding ones of the first to eighth bonding pads BP1to BP8may be arranged along the first direction D1.

The first chip stack CS1may include a plurality of first chips110that are stacked through one or more adhesion layers ADL on the package substrate100. The second chip stack CS2may include a plurality of second chips120that are stacked through one or more adhesion layers ADL on the package substrate100.

The package substrate100may be provided thereon with the third chip stack CS3spaced apart in the second direction D2from the first chip stack CS1. The third chip stack CS3may include a plurality of third chips130that are stacked through one or more adhesion layers ADL on the package substrate100. The fourth chip stack CS4may include a plurality of fourth chips140that are stacked through one or more adhesion layers ADL on the package substrate100.

The first and second bonding pads BP1and BP2of the package substrate100may be adjacent to the first chip stack CS1, and the fifth and sixth bonding pads BP5and BP6of the package substrate100may be adjacent to the third chip stack CS3.

In an implementation, each of the first to fourth chips110to140may have a first edge and a second edge, each first and second chip110and120may include chip pads that are arranged adjacent to the second edge, and each third and fourth chip130and140may include chip pads that are arranged adjacent to the first edge.

The first and second chips110and120may be stacked on the package substrate100in a direction opposite to the second direction D2, thereby constituting a staircase or cascade structure. The third and fourth chips130and140may be stepwise stacked along the second direction D2(e.g., the staircase structure of the first and second chips110and120may extend in a direction opposite to the staircase structure of the third and fourth chips130and140).

The first chips110may be stacked such that each of the first chips110may expose chip pads of its underlying first chip110. The second chips120may be stacked such that each of the second chips120may expose chip pads of its underlying first chip110or its underlying second chip120.

The third chips130may be stacked such that each of the third chips130may expose chip pads of its underlying third chip130. The fourth chips140may be stacked such that each of the fourth chips140may expose chip pads of its underlying third chip130or its underlying fourth chip140.

The first to fourth chips110and140may respectively include first to fourth signal pads111to141and first to fourth power/ground pads113to143.

As discussed above, the first upper wires UW1may connect the second signal pads121of one of the second chips120to the third bonding pads BP3, and the second upper wires UW2may connect the second power/ground pads123of one of the second chips120to the fourth bonding pads BP4.

The third upper wires UW3may connect the third signal pads131of one of the third chips130to the fifth bonding pads BP5, and the fourth lower wires LW4may connect the third power/ground pads133of one of the third chips130to the sixth bonding pads BP6.

The third upper wires UW3may connect the fourth signal pads141of one of the fourth chips140to the seventh bonding pads BP7, and the fourth upper wires UW4may connect the fourth power/ground pads143of one of the fourth chips140to the eighth bonding pads BP8.

The third signal pads131of the third chips130may be connected to each other through the fourth connection wires CW4, and the fourth signal pads141of the fourth chips140may be connected to each other through the fifth connection wires CW5.

The third and fourth power/ground pads133and143of the third and fourth chips130and140may be electrically connected to each other through the sixth connection wires CW6.

FIG.21Aillustrates a plan view of a semiconductor package according to some embodiments.FIG.21Billustrates a cross-sectional view taken along line A-A′ ofFIG.21A.

According to the embodiment shown inFIGS.21A and21B, a semiconductor package may include a package substrate100, first to fourth chip stacks CS1to CS4, a controller chip200, first to fourth lower wires LW1to LW4, first to fourth upper wires UW1to UW4, first to sixth connection wires CW1to CW6, and a molding layer300.

As discussed with reference toFIGS.19and20, a stacking direction of the first and second chips110and120may be opposite to that of the third and fourth chips130and140.

The controller chip200may have a first edge and a second edge that are opposite to each other, the first and second chip pads CP1and CP2may be adjacent to the first edge, and the third and fourth chip pads CP3and CP4may be adjacent to the second edge.

The package substrate100may include first to fourth bonding pads BP1to BP4that are between the first chip stack CS1and the controller chip200, and may also include fifth to eighth bonding pads BP5to BP8that are between the third chip stack CS3and the controller chip200.

In an implementation, the first upper wires UW1may connect the second signal pads121of one of the second chips120to the first chip pads CP1of the controller chip200. The second upper wires UW2may connect the second power/ground pads123of one of the second chips120to the second chip pads CP2of the controller chip200.

The third upper wires UW3may connect the fourth signal pads141of one of the fourth chips140to the third chip pads CP3of the controller chip200. The fourth upper wires UW4may connect the fourth power/ground pads143of one of the fourth chips140to the fourth chip pads CP4of the controller chip200.

FIG.22Aillustrates a plan view of a semiconductor package according to some embodiments.FIG.22Billustrates a cross-sectional view taken along line A-A′ ofFIG.22A.

According to the embodiment shown inFIGS.22A and22B, a semiconductor package may include a package substrate100, first to fourth chip stacks CS1to CS4, first and second controller chips200aand200b, first to fourth lower wires LW1to LW4, first to fourth upper wires UW1to UW4, first to sixth connection wires CW1to CW6, and a molding layer300.

The package substrate100may be provided thereon with the first controller chip200aadjacent to the first and second chip stacks CS1and CS2. The package substrate100may be provided thereon with the second controller chip200badjacent to the third and fourth chip stacks CS3and CS4. In an implementation, the first and second controller chips200aand200bmay be adjacent to each other.

Each of the first and second controller chips200aand200bmay have a first edge and a second edge that are opposite to each other, the first and second chip pads CP1and CP2may be adjacent to the first edge, and the third and fourth chip pads CP3and CP4may be adjacent to the second edge.

The package substrate100may include first to fourth bonding pads BP1to BP4that are between the first chip stack CS1and the first controller chip200a, and may also include fifth to eighth bonding pads BP5to BP8that are between the third chip stack CS3and the second controller chip200b. In an implementation, the package substrate100may further include bonding pads between the first controller chip200aand the second controller chip200b.

The first upper wires UW1may connect the second signal pads121of one of the second chips120to the third chip pads CP3of the first controller chip200a. The second upper wires UW2may connect the second power/ground pads123of one of the second chips120to the fourth chip pads CP4of the first controller chip200a. The first and second chip pads CP1and CP2of the first controller chip200amay be connected through wires to bonding pads of the package substrate100.

The third upper wires UW3may connect the fourth signal pads141of one of the fourth chips140to the third chip pads CP3of the second controller chip200b. The fourth upper wires UW4may connect the fourth power/ground pads143of one of the fourth chips140to the fourth chip pads CP4of the second controller chip200b. The first and second chip pads CP1and CP2of the second controller chip200bmay be connected through wires to bonding pads of the package substrate100.

FIG.23illustrates a plan view of a semiconductor package according to some embodiments.

According to the embodiment shown inFIG.23, a semiconductor package may include a package substrate100, first to fourth chip stacks CS1to CS4, a controller chip200, first to fourth lower wires LW1to LW4, first to fourth upper wires UW1to UW4, first to sixth connection wires CW1to CW6, and a molding layer300.

As discussed with reference toFIGS.2,3A, and3B, the package substrate100may be provided thereon with the first chip stack CS1that includes first chips110, and also with the second chip stack CS2that include second chips120stacked on the first chip stack CS1.

The package substrate100may be provided thereon with the third and fourth chip stacks CS3and CS4that are spaced apart in the first direction D1from the first and second chip stacks CS1and CS2. The third chip stack CS3may include a plurality of third chips130that are stacked on the package substrate100, and the fourth chip stack CS4may include a plurality of fourth chips140that are stacked on the third chip stack CS3.

The package substrate100, as discussed above, may include first and second bonding pads BP1and BP2that are alternately arranged along the first direction D1, third bonding pads BP3that are spaced apart in the second direction D2from the first bonding pads BP1, and fourth bonding pads BP4that are spaced apart in the second direction D2from the second bonding pads BP2. In this case, the first and second bonding pads BP1and BP2may be adjacent to the first chip stack CS1.

In an implementation, the package substrate100may further include fifth and sixth bonding pads BP5and BP6that are alternately arranged along the first direction D1, seventh bonding pads BP7that are spaced apart in the second direction D2from the fifth bonding pads BP5, and eighth bonding pads BP8that are spaced apart in the second direction D2from the sixth bonding pads BP6. In an implementation, the fifth to eighth bonding pads BP5to BP8may be between the controller chip200and the third chip stack CS3.

As discussed with reference toFIGS.2,3A, and3B, the first signal pads111of the first chips110may be electrically separated from the second signal pads121of the second chips120. The first power/ground pads113of the first chips110may be electrically connected to the second power/ground pads123of the second chips120.

As discussed above, the first upper wires UW1may connect the second signal pads121of one of the second chips120to the third bonding pads BP3, and the second upper wires UW2may connect the second power/ground pads123of one of the second chips120to the fourth bonding pads BP4.

The third upper wires UW3may connect the third signal pads131of one of the third chips130to the fifth bonding pads BP5, and the fourth lower wires LW4may connect the third power/ground pads133of one of the third chips130to the sixth bonding pads BP6.

The third signal pads131of the third chips130may be electrically separated from the fourth signal pads141of the fourth chips140. The third power/ground pads133of the third chips130may be electrically connected to the fourth power/ground pads143of the fourth chips140.

The third upper wires UW3may connect the fourth signal pads141of one of the fourth chips140to the first chip pads CP1of the controller chip200, and the fourth upper wires UW4may connect the fourth power/ground pads143of one of the fourth chips140to the second chip pads CP2of the controller chip200. The first chip pads CP1of the controller chip200may be connected through bonding wires to the seventh bonding pads BP7, and the second chip pads CP2of the controller chip200may be connected through bonding wires to the eighth bonding pads BP8.

By way of summation and review, with the development of electronic industry, improving reliability and durability of semiconductor packages has been considered. In order reduce a size and weight of electronic parts, a number of individual devices may be integrated into a single package and individual sizes of mounting parts may be reduced. Semiconductor packages operated at high frequency signals may have compactness and excellent electrical characteristics.

According to some embodiments, a semiconductor package may be configured such that signal pads of a lower chip stack may be connected through lower wires to a package substrate, and that signal pads of an upper chip stack may be connected through upper wires to the package substrate. Therefore, input/output signals of the lower and upper chip stacks may be input and output through different channels.

According to some embodiments, each of second upper wires connected to power/ground pads may be between first upper wires connected to signal pads of an upper chip stack. Therefore, when second chips are driven to operate, the second upper wires may shield electrical interference or crosstalk between the first upper wires. Accordingly, it is possible to help reduce or prevent a reduction in operating speed of the second chips and to help improve signal integrity of a semiconductor package.

One or more embodiments may provide a semiconductor package with improved electrical properties.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.