Patent ID: 12260928

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over, or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” “top,” “bottom” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The following disclosure describes various aspects of a memory device, e.g., a static random access memory (SRAM) device. Specifically, the disclosure describes different embodiments related to an SRAM memory write operation. For ease of explanation, certain SRAM circuit elements and control logic are disclosed to facilitate in the description of the different embodiments. It should be appreciated that SRAM devices also include other circuit elements and control logic. These other circuit elements and control logic are within the spirit and scope of this present disclosure.

A typical SRAM device includes an array of individual SRAM cells. Each SRAM cell is capable of storing a binary voltage value therein, which voltage value represents a logical data bit (e.g., “0” or “1”). One existing configuration for an SRAM cell includes a pair of cross-coupled devices such as inverters. With CMOS (complementary metal oxide semiconductor) technology, the inverters further include a pull-up PFET (p-channel) transistor connected to a complementary pull-down NFET (n-channel) transistor. The inverters, connected in a cross-coupled configuration, act as a latch that stores the data bit therein so long as power is supplied to the memory array. In a conventional six-transistor (6T) cell, a pair of access transistors or pass gates (when activated by a word line) selectively couples the inverters to a pair of complementary bit lines. Other SRAM cell designs may include a different number of transistors, e.g., 4T, 8T, etc.

The design of SRAM cells has traditionally involved a compromise between the read and write functions of the memory cell to maintain cell stability, read performance and write performance. The transistors which make up the cross-coupled latch must be weak enough to be overdriven during a write operation, while also strong enough to maintain their data value when driving a bit line during a read operation. The access transistors that connect the cross-coupled cell nodes to the true and complement bit lines affect both the stability and performance of the cell. In one-port SRAM cells, a single pair of access transistors is conventionally used for both read and write access to the cell. The gates are driven to a digital value in order to switch the transistors between an on state and off state. The optimization of an access for a write operation would drive the reduction of the on-resistance (Ron) for the device. On the other hand, the optimization of an access transistor for a read operation drives an increase in Ron in order to isolate the cell from the bit line capacitance and prevent a cell disturb.

One recently proposed approach to improving write performance of SRAM devices is to use so-called “negative boosting” to discharge a bit line to a voltage level below the nominal low supply rail value (e.g., ground). Alternatively stated, the corresponding bit line of an SRAM cell may present a negative voltage, when being written. Such a bit line is typically discharged to the negative voltage through a capacitor, or sometimes referred to as a boost capacitor. In this way, the pass gates of the SRAM cell coupled to the discharged bit line see a resultant increase in both the gate-to-source and drain-to-source voltages. This negative boosting may allow for an increased margin of 30 or more (in terms of expected device failures) as compared to more conventional write techniques, wherein the bit line is simply discharged to the value of the nominal low voltage rail (e.g., ground).

However, notwithstanding the benefits of negative boosting, the existing SRAM devices with negative boosting may still not be entirely satisfactory in many aspects. For example, the boost capacitor is typically formed as a metal-insulator-metal (MIM) or metal-oxide-metal (MOM) structure. Such a capacitor structure is typically disposed in one or more metallization layers on the frontside of a substrate where a number of active devices (e.g., the corresponding transistors of SRAM cells) are formed. With the ever progressively shrunk size of transistors in advanced technology nodes, a size of the boost capacitor may be forced to shrink accordingly, which can disadvantageously reduce a capacitive value of the boost capacitance. On the other hand, keeping the size of the boost capacitor significantly consumes precious real estate of the frontside metallization layers, which can be utilized for forming other routing signals.

The present disclosure provides various embodiment of an SRAM device with a negative voltage generator that includes one or more components formed on the backside of a substrate, which is opposite to a frontside of the substrate where corresponding SRAM cells are formed. In various embodiments, the negative voltage generator, as disclosed herein, can generate a negative voltage to a number of bit lines coupled to the SRAM cells, when writing those SRAM cells. The negative voltage generator may include at least one boost capacitor that has at least a majority portion formed on the backside of the substrate. For example, the boost capacitor can be formed by connecting a number of sub-capacitors in parallel. Respective (positive and negative) terminals of one or more of the sub-capacitors are formed as conductive lines on the backside of the substrate. Forming at least a portion of the boost capacitor on the backside can offer various advantages for the SRAM device as a whole. For example, with the backside conductive lines functioning as the boost capacitor, a significant amount of the frontside real estate (e.g., conductive lines) can be saved for other usage or application. In another example, the backside conductive lines can be formed with a higher thickness than the frontside conductive lines, which essentially increases the surface area of conductor plates of the boost capacitor. As such, within the same layout area, the boost capacitor, as disclosed herein, can be characterized with a higher capacitive value (e.g., about 16˜25% more), when compared to the conventional boost capacitor that is only formed on the frontside.

FIG.1illustrate a schematic view of an example static random access memory (SRAM) device/circuit100with a write assist circuit110that includes a boost capacitor, according to various embodiments of the present disclosure. The SRAM device100includes a row decoder120, a word line driver130, a column decoder140, a column multiplexer (MUX)150, a write driver circuit160, and an SRAM array180.

The SRAM array180includes a number of memory cells190. The memory cells190can be arranged in one or more arrays in the SRAM device100. In the illustrated example ofFIG.1, a single SRAM array180is shown to simplify the description of the disclosed embodiments. The SRAM array180has “M+1” number of rows and “N+1” number of columns. For example, the SRAM array180includes the memory cells190arranged over rows, row0to rowM, and columns1700to170N. Accordingly, the notation “19000” refers to one of the memory cells190located in row0and column1700. Similarly, the notation “190MN” refers to another one of the memory cells190located in rowMand column170N.

Each of the SRAM cells in the SRAM array180is accessed, e.g., for memory read and memory write operations, using a memory address. Based on a portion of the memory address, the row decoder120selects a row (e.g., one of the row0to rowM) of the memory cells to access via the word line driver130(e.g., a corresponding one of a number of word line drivers1300. . .130M). Also, based on the memory address, the column decoder140selects a column of memory cells1700-170Nto access via the write assist circuit110and the column MUX150, according to some embodiments of the present disclosure. Based on another portion of the memory address, the column decoder140outputs a corresponding YSEL signal to activate a corresponding pair of y-select transistors,152and154, in the column MUX150to access a corresponding column. Each column includes a bit line pair, BL and BLB. The notation “BL” refers to a bit line, and the notation “BLB” refers to the complement of “BL.” For example, to access the memory cells in the column1700, the column decoder140outputs YSEL[0] signal to active the pair of transistors152[0] and154[0] corresponding to the column1700so as to allow access the corresponding pair of bit line BL[0] and bit line bar BLB[0]. In another example, to access the memory cells in the column170N, the column decoder140outputs YSEL[N] signal to active the pair of transistors152[N] and154[N] corresponding to the column170Nso as to allow access the corresponding pair of bit line BL[N] and bit line bar BLB[N]. In some embodiments, the write driver circuit160generates voltages for the bit line pair of BL and BLB in the accessed one of columns1700to170N. As such, the intersection of the accessed row and the accessed column of memory cells results in access to a single memory cell190.

The memory cell190can have any of various circuit topologies. For example, the memory cell190can have a “6T” circuit topology.FIG.2illustrates an example 6T circuit topology for the memory cell190. The 6T circuit topology includes n-channel metal-oxide-semiconductor (NMOS) pass devices220and230, NMOS pull-down devices240and250, and p-channel metal-oxide-semiconductor (PMOS) pull-up devices260and270. A voltage from the word line driver130controls the NMOS devices220and230to pass voltages from the bit line pair of BL and BLB to a bi-stable flip-flop structure formed by the NMOS devices240and250and the PMOS devices260and270. The bit line pair of BL and BLB voltages can be used during a memory write operation. For example, if bit line BL is at a ‘1’ or a logic high value (e.g., a power supply voltage VDD such as 0.4V, 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V, or any combination thereof) and bit line BLB is at a ‘0’ or a logic low value (e.g., ground or 0V), the voltage applied by the word line driver130to the gate terminals of the NMOS pass devices220and230can be at a sufficient voltage level to pass the bit line BL's logic high value and the bit line bar BLB's logic low value to the bi-stable flip-flop structure. As a result, these logic values are written (or programmed) into the bi-stable flip-flop structure.

FIG.3illustrates a schematic diagram of an example of the write assist circuit110, in accordance with various embodiments of the present disclosure. The write assist circuit110is configured to provide a reference voltage118to the write driver circuit160as a reference voltage. The reference voltage118can be ground (e.g., 0V), a negative voltage (e.g., −100 mV, −200 mV, or −300 mV), or a combination thereof, according to some embodiments of the present disclosure. The write assist circuit110includes one or more boost capacitors configured to provide such a negative reference voltage118, which will be discussed as follows.

In some embodiments, the write driver circuit160includes level-shifter devices162and164that each receive the reference voltage118. With a logic low input received by either the level-shifter device162or164, the corresponding level-shifter device outputs a logic high value (e.g., a power supply voltage VDD of the inverter logic device such as 0.4V, 0.6V, 0.7V, 1.0V, 1.2V, 1.8V, 2.4V, 3.3V, 5V, or any combination thereof). Conversely, with a logic high input received by either the level-shifter device162or164, the corresponding level-shifter device outputs the reference voltage118. For example inFIG.3, the level-shifter device162receives a logic high value and the level-shifter device164receives a logic low value, and thus, the level-shifter device162outputs the reference voltage118to the BL of an accessed column (e.g., asserted by the YSEL signal) and the level shifter device164outputs a logic high value to the BLB of the same access column.

The write assist circuit110is coupled to the write driver circuit160at Node X. The write assist circuit110includes a NMOS switch transistor306coupled between ground and Node X and a boost capacitor304directly coupled between the drain (Node X) and gate terminals (Node Y) of the transistor306. In some embodiments, the switch transistor306and boost capacitor304can provide a negative voltage to a coupled bit line. The switch transistor306and boost capacitor304are sometimes collectively referred to as a (negative) voltage generator. A bit line boost enable control signal307is provided at Node Y from a logic circuit302, which is responsive to a write enable signal309. The logic circuit302may include a number of delay elements connected in series with one or more inverters that provide a delay to the write enable signal309. The write enable signal309can thus be delayed and inverted to provide the boost signal307at node Y. Before the write enable signal309goes high (at the start of the write operation/period), the boost signal307is high, which turns the transistor306on and charges the boost capacitor304. When the boost signal307is high, Node X is also connected to ground through the transistor306. After the delay, the boost signal307goes low, which turns off the transistor306and, at the same time, causes a discharge from the boost capacitor304, which drives Node X (i.e., the reference voltage118) from ground (low) to a negative value. This negative reference voltage118is then provided to bit lines (BL/BLB) through the write driver circuit160(as discussed above), which provides a boost for the write operation performed to the SRAM cell190coupled to the bit lines (BL/BLB).

FIG.4illustrates a schematic view of the boost capacitor304connected between node X and node Y, in accordance with various embodiments. Specifically, the boost capacitor304has a first terminal connected to node X and a second terminal connected to node Y. In accordance with various embodiments, the boost capacitor304has a number of sub-capacitors (or capacitors) connected in parallel. Each of the sub-capacitors has a respective pair of terminals sandwiching a dielectric material therebetween. In some embodiments, a capacitive value of the boost capacitor may be positively proportional to a number of the sub-capacitors connected in parallel.

For example inFIG.4, the boost capacitor304has sub-capacitors, C1, C2, C3, and C4connected in parallel, which are, at least in part, implemented as a number of first metal lines402and404and a number of second metal lines406,408, and410. The first metal lines402-404are connected to Node X functioning as the first terminal of the boost capacitor304, and the second metal lines406-410are connected to Node Y functioning as the second terminal of the boost capacitor304. Specifically, the sub-capacitor C1has the first metal line402and second metal line406as its corresponding terminals (or sub-terminals); the sub-capacitor C2has the first metal line402and second metal line408as its corresponding terminals (or sub-terminals); the sub-capacitor C3has the first metal line404and second metal line408as its corresponding terminals (or sub-terminals); and the sub-capacitor C4has the first metal line404and second metal line410as its corresponding terminals (or sub-terminals). Although the boost capacitor304is formed by two first metal lines and three second metal lines (e.g., as four parallel connected sub-capacitors), it should be understood that the boost capacitor304can be formed by any number of the first metal lines and any number of the second metal lines (as any number of parallel connected sub-capacitors), while remaining within the scope of the present disclosure.

FIG.5illustrates a cross-sectional view of a semiconductor device500that may be implemented as at least a portion of the SRAM device100, e.g., the write assist circuit110. The cross-sectional view ofFIG.5is cut along the lengthwise direction of channels of a plurality of transistors of the semiconductor device500, which are each implemented as a gate-all-around field-effect-transistor (GAA FET) device. However, it should be understood that the transistors of the semiconductor device500may be implemented as any of various other transistor structures (e.g., FinFETs, planar FETs, or otherwise nanostructure transistors, etc.), while remaining within the scope of the present disclosure. Additionally,FIG.5is simplified to illustrate relatively spatial configurations of the above-discussed components (e.g., the boost capacitor304, the switch transistor306), and thus, it should be understood that one or more features/structures of a completed GAA FET device may not be shown inFIG.5.

On the frontside of a substrate (which is enclosed by a dotted line, as it has been removed when forming backside interconnect structures), the semiconductor device500includes an active region502having portions being formed as channels504and portions being formed as source/drain structures506. The channels504each include one or more nanostructures (e.g., nanosheets, nanowires) vertically spaced apart from each other, in various embodiments. The semiconductor device500includes a number of (e.g., metal) gate structures508, each on which wraps around the nanostructures of a corresponding channel504.

Over the source/drain structure506, the semiconductor device500includes a number of source/drain interconnect structures (sometimes referred to as MDs)510, some of which are coupled with drain via structures (sometimes referred to as VDs)512formed thereupon. Over the gate structure508, the semiconductor device500includes a number of gate via structures (sometimes referred to as VGs)514.

The VD512can couple the MD510to a first metal line in the first (e.g., bottommost) frontside metallization layer (sometimes referred to as an M0 track)516. The VG514can couple the gate structure508to a second M0 track518. Over the M0 tracks516and518(and various other metal lines in the bottommost frontside metallization layer), the semiconductor device500includes a number of via structures (sometimes referred to as VOs),520and522, to couple the M0 tracks516and518to respective metal lines in the next frontside metallization layer farther away from the substrate (sometimes referred to as M1 tracks),524and526. Further, over the M1 tracks524and526(and various other metal lines in the same frontside metallization layer), the semiconductor device500includes a number of via structures (sometimes referred to as V1s),528and530, to couple the M1 tracks524and526to respective metal lines in the next frontside metallization layer farther away from the substrate (sometimes referred to as M2 tracks),532and534. Although three frontside metallization layers are shown, it should be understood that the semiconductor device500can include any number of frontside metallization layers. The metal tracks formed across such frontside metallization layers can be configured to electrically couple different components of the SRAM device100(so as to route signals and/or deliver power), in accordance with various embodiments.

On the backside of the substrate, the semiconductor device500includes a number of backside via structures (sometimes referred to as BVs),542and544, that can couple the source/drain structure506and gate structure508to a number of metal lines in the first (e.g., bottommost) backside metallization layer (sometimes referred to as BM0 tracks),546and548, respectively. Further, over the BM0 tracks546and548, the semiconductor device500includes a number of via structures (sometimes referred to as BV0s),550and552, that can couple the BM0 tracks546and548to a number of metal lines in the next backside metallization layer farther away from the substrate (sometimes referred to as BM1 tracks),554and556, respectively. Still further, over the BM1 tracks554and556, the semiconductor device500includes a number of via structures (sometimes referred to as BV1s),558and560, that can couple the BM1 tracks554and556to a number of metal lines in the next backside metallization layer farther away from the substrate (sometimes referred to as BM2 tracks),562and564, respectively.

In accordance with various embodiments of the present disclosure, at least one of the channels504, together with a corresponding one of the gate structures508wrapping around such a channel and with a corresponding pair of source/drain structures506, can form the switch transistor306of the write assist circuit110. Further, at least one pair of the backside metal lines can form at least a portion of the boost capacitor304of the write assist circuit110. For example inFIG.5, the BM0 track546coupled to one of the source/drain structures506of the switch transistor306can serve as a first terminal of the boost capacitor304's sub-capacitor (or capacitor) C1, and the BM0 track548coupled to the other of the source/drain structures506of the switch transistor306can serve as a second terminal of the boost capacitor304's sub-capacitor (or capacitor) C1. Referring again to the schematic view ofFIG.4, the BM0 tracks546and548ofFIG.5can correspond to the metal lines402and406ofFIG.4, respectively.

It should be understood that other sub-capacitors of the boost capacitor304can be formed by other BM0 tracks, i.e., other metal lines in the bottommost backside metallization layer. For example,FIG.6illustrates a portion of a layout600that includes a number of patterns602,604,606,608, and610configured to form the respective BM0 tracks that constitute the boost capacitor. As shown, the patterns604and608, configured to form the metal lines (e.g., embodied as BM0 tracks)402and404(FIG.4), respectively, may have their ends aligned with each other. Hereinafter, the patterns604and608are referred to as BM0 tracks604and608, respectively. The patterns602,606, and610, configured to form the metal lines (e.g., embodied as BM0 tracks)406,408, and410(FIG.4), respectively, may have their ends aligned with each other. Hereinafter, the patterns602,606, and610are referred to as BM0 tracks602,606, and610, respectively. As such, the sub-capacitors C1, C2, C3, and C4of the boost capacitor304can be formed by the combinations of BM0 tracks602and604, BM0 tracks604and606, BM0 tracks606and608, and BM0 tracks608and610, respectively.

Further, the patterns604and608are laterally shifted from the patterns602,606, and610with a certain offset, allowing the BM0 tracks604and608to be electrically coupled to each other through one or more interconnect structures (e.g., a pattern620configured to form an MD/M1 track620), and the BM0 tracks602,606, and610to be electrically coupled to each other through one or more interconnect structures (e.g., a pattern630configured to form an MD/M1 track630). The MD/M1 track620may be operatively connected to Node X (e.g., the drain of the switch transistor306), and the MD/M1 track630may be operatively connected to Node Y (e.g., the gate of the switch transistor306).

It should also be understood that the patterns of the layout600are not limited to forming BM0 tracks that constitute the boost capacitor304. The patterns602to610can also be utilized to form a number of other metal lines on the frontside and/or the backside. For example, the patterns602to610can be used to form a number of BM2 tracks (e.g.,562,564ofFIG.5) constituting at least a portion of the boost capacitor304. In another example, in addition to the BM0 and/or BM2 tracks constituting the boost capacitor304, the patterns602to610can be used to form a number of M0 tracks (e.g.,516,518ofFIG.5) and/or M2 tracks (e.g.,532,534ofFIG.5) constituting at least a portion of the boost capacitor304.

Referring again toFIG.5, the M0 tracks516and518can form one of a number of parallel connected sub-capacitors, C1′, to further increase the capacitive value of the boost capacitor304. The M0 tracks516and518, formed based on the patterns602and604of the layout600, respectively, may function as terminals of the sub-capacitors, C1′. Further, other M0 tracks, formed based on the patterns604and606of the layout600, respectively, may function as terminals of another sub-capacitors, C2′; yet other M0 tracks, formed based on the patterns606and608of the layout600, respectively, may function as terminals of yet another sub-capacitors, C3′; and yet other M0 tracks, formed based on the patterns608and610of the layout600, respectively, may function as terminals of yet another sub-capacitors, C4′.

Similarly, the M2 tracks532and534can form one of a number of parallel connected sub-capacitors, C1′, to further increase the capacitive value of the boost capacitor304. The M2 tracks532and534, formed based on the patterns602and604of the layout600, respectively, may function as terminals of the sub-capacitors, C1′. Further, other M2 tracks, formed based on the patterns604and606of the layout600, respectively, may function as terminals of another sub-capacitors, C2′; yet other M2 tracks, formed based on the patterns606and608of the layout600, respectively, may function as terminals of yet another sub-capacitors, C3′; and yet other M2 tracks, formed based on the patterns608and610of the layout600, respectively, may function as terminals of yet another sub-capacitors, C4′.

In accordance with various embodiments of the present disclosure, a thickness of the backside metal lines (e.g., BM0 tracks, BM2 tracks) is substantially greater than a thickness of the frontside metal lines (e.g., M0 tracks, M2 tracks). For example, with a certain technology node, the backside metal lines may have a thickness range of about 40 nanometers (nm) to about 400 nm, which is generally greater than a thickness range of the frontside meal lines. With such a greater thickness, a contact area of each sub-capacitor of the boost capacitor304can be proportionally increased. A capacitive value of each of the sub-capacitors can be increased accordingly (e.g., about 16% to about 25%), which can advantageously reduce discharge time of the boost capacitor304. Consequently, the reference voltage118may be pulled to a negative voltage more quickly, which allows read operations of the SRAM device100to be finished more quickly and efficiently.

FIG.7depicts a flowchart of an example method700of forming or manufacturing a semiconductor device (e.g., at least a portion of the SRAM device100), in accordance with some embodiments. It is understood that additional operations may be performed before, during, and/or after the method700depicted inFIG.7. Operations of the method700may be associated with cross-sectional views of an example semiconductor device800at various fabrication stages as shown inFIGS.9,10,11,12,13A,13B,14A,14B,15A,15B,16A,16B,17A,17B,18A, and18B, respectively, which will be discussed in further detail below. In some embodiments, the method700is usable to form a semiconductor device, according to various layout designs as disclosed herein.

In brief overview, the method700starts with operation702of providing a substrate. Next, the method700can proceed to operation704of forming a buried oxide layer. Alternatively, the buried oxide layer may be formed later (see operation714). Then, the method700proceeds to operation706of forming channel layers and sacrificial layers alternatively stacked on top of one another. The method700proceeds to operation708of defining a semiconductor fin. The method700proceeds to operation710of forming a dummy gate structure over the semiconductor fin. The method700proceeds to operation712of forming source and/or drain recesses. The method700can proceed to operation714of forming a buried oxide layer, if the buried oxide layer was not already formed in operation704. The method700proceeds to operation718of replacing the dummy gate structures with respective active structures. The method700proceeds to operation720of forming frontside interconnect structures. The method700proceeds to operation722of thinning down the substrate until the bottom oxide layer is exposed. The method700proceeds to operation724of forming backside interconnect structures.

As mentioned above,FIGS.8-18Billustrate cross-sectional views of an example semiconductor device800during various fabrication stages, made by method700, in accordance with some embodiments. The semiconductor device800may be an implementation of the SRAM device100, which includes a number of transistors (e.g.,306) and a number of boost capacitors (e.g.,304). Some of the transistors may be implemented in the GAA FET structure, in various embodiments. For example,FIGS.8-11are cross-sectional views of the semiconductor device800taken at various fabrication stages cut along the lengthwise (or longitudinal) direction of one or more dummy/active gate structures of the transistors, andFIGS.12-18Bare cross-sectional views of the semiconductor device800taken at various fabrication stages cut along the lengthwise (or longitudinal) direction of one or more channels of the transistors. AlthoughFIGS.8-18Billustrate the semiconductor device800including a GAA FET structure, it is understood that the semiconductor device800may include any of various other transistor structures and a number of other devices such as inductors, fuses, capacitors, coils, etc. which are not shown inFIGS.8-18Bfor purposes of clarity of illustration.

For simplicity,FIGS.8-12and those with numbers ending in “A” from13A to18A illustrate the semiconductor device800at various fabrication stages where operation704of the method700is performed. If operation704is not performed, operation714is performed to form the buried oxide layer as shown inFIG.13B. Accordingly, figures with numbers ending with “B” from13B to18B illustrate the semiconductor device800at various fabrication stages when operation714is performed.

Corresponding to operation702,FIG.8is a cross-sectional view of the semiconductor device800including a semiconductor substrate802at one of the various stages of fabrication. The cross-sectional view ofFIG.8is cut in a direction along the lengthwise direction of one or more active/dummy gate structures of the semiconductor device800.

The substrate802may be a semiconductor substrate, such as a bulk semiconductor, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate802may be a wafer, such as a silicon wafer. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate802may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof.

Corresponding to operation704,FIG.9is a cross-sectional view of the semiconductor device800including a buried oxide layer902at one of the various stages of fabrication. The cross-sectional view ofFIG.9is cut in a direction along the lengthwise direction of one or more active/dummy gate structures of the semiconductor device800. The semiconductor device800may further includes a layer of a semiconductor material904formed on the buried oxide layer902. Such a combination of the substrate802, the buried oxide layer902, and the semiconductor material904may sometimes be collectively referred to as a semiconductor-on-insulator (SOI) substrate.

Corresponding to operation706,FIG.10is a cross-sectional view of the semiconductor device800including a plurality of sacrificial layers1002and a plurality of channel layers1004at one of the various stages of fabrication. The cross-sectional view ofFIG.10is cut in a direction along the lengthwise direction of one or more active/dummy gate structures of the semiconductor device800.

A number of sacrificial layers1002and a number of channel layers1004are alternatingly disposed on top of one another to form a stack. For example, one of the channel layers1004is disposed over one of the sacrificial layers1002, then another one of the sacrificial layers1002is disposed over the channel layer1004, so on and so forth. The stack may include any number of alternately disposed sacrificial and channel layers1002and1004. For example in the illustrated embodiments ofFIG.10(and the following figures), the stack may include four sacrificial layers1002, with four channel layers1004alternatingly disposed therebetween and with one of the channel layers1004being the topmost semiconductor layer. It should be understood that the semiconductor device800can include any number of sacrificial layers and any number of channel layers, with either one of them being the topmost layer, while remaining within the scope of the present disclosure.

The layers1002and1004may have respective different thicknesses. Further, the sacrificial layers1002may have different thicknesses from one layer to another layer. The channel layers1004may have different thicknesses from one layer to another layer. The thickness of each of the layers1002and1004may range from few nanometers to few tens of nanometers. The first layer of the stack may be thicker than other semiconductor layers1002and1004. In an embodiment, each of the sacrificial layers1002has a thickness ranging from about 5 nanometers (nm) to about 20 nm, and each of the channel layers1004has a thickness ranging from about 5 nm to about 20 nm.

The two layers1002and1004may have different compositions. In various embodiments, the two layers1002and1004have compositions that provide for different oxidation rates and/or different etch selectivity between the layers. In an embodiment, the sacrificial layers1002may each include silicon germanium (Si1-xGex), and the channel layers may each include silicon (Si). In an embodiment, each of the channel layers1004is silicon that may be undoped or substantially dopant-free (i.e., having an extrinsic dopant concentration from about 0 cm−3to about 1×1017cm−3), where for example, no intentional doping is performed when forming the channel layers1004(e.g., of silicon).

In various embodiments, the semiconductor layers1004may be intentionally doped. For example, when the semiconductor device800is configured as an n-type transistor (and operates in an enhancement mode), each of the channel layers1004may be silicon that is doped with a p-type dopant such as boron (B), aluminum (Al), indium (In), and gallium (Ga); and when the semiconductor device800is configured as a p-type transistor (and operates in an enhancement mode), each of the channel layers1004may be silicon that is doped with an n-type dopant such as phosphorus (P), arsenic (As), antimony (Sb). In another example, when the semiconductor device800is configured as an n-type transistor (and operates in a depletion mode), each of the channel layers1004may be silicon that is doped with an n-type dopant instead; and when the semiconductor device800is configured as a p-type transistor (and operates in a depletion mode), each of the channel layers1004may be silicon that is doped with a p-type dopant instead.

In some embodiments, each of the sacrificial layers1002is Si1-xGexthat includes less than 50% (x<0.5) Ge in molar ratio. For example, Ge may comprise about 15% to 35% of the sacrificial layers1002of Si1-xGexin molar ratio. Furthermore, the sacrificial layers1002may include different compositions among them, and the channel layers1004may include different compositions among them. Either of the layers1002and1004may include other materials, for example, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, an alloy semiconductor such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or combinations thereof. The materials of the layers1002and1004may be chosen based on providing differing oxidation rates and/or etch selectivity.

The layers1002and1004can be epitaxially grown from the semiconductor substrate802. For example, each of the layers1002and1004may be grown by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process such as a metal organic CVD (MOCVD) process, and/or other suitable epitaxial growth processes. During the epitaxial growth, the crystal structure of the semiconductor substrate802extends upwardly, resulting in the layers1002and1004having the same crystal orientation with the semiconductor substrate802.

Corresponding to operation708,FIG.11is a cross-sectional view of the semiconductor device800including a number of semiconductor fins,1102and1104, at one of the various stages of fabrication. The cross-sectional view ofFIG.11is cut in a direction along the lengthwise direction of one or more active/dummy gate structures of the semiconductor device800.

Upon growing the layers1002and1004on the semiconductor substrate802(as a stack), the stack may be patterned to form the fin structures1102and1104, as shown inFIG.11. Each of the fin structures is elongated along a lateral direction and includes a stack of patterned sacrificial layers1002and channel layers1004interleaved with each other. The fin structures1102and1104are formed by patterning the stack of layers1002and1004and the semiconductor material904using, for example, photolithography and etching techniques.

For example, a mask layer (which can include multiple layers such as, for example, a pad oxide layer and an overlying hardmask layer) is formed over the topmost semiconductor layer of the stack (e.g.,1004inFIG.10). The pad oxide layer may be a thin film comprising silicon oxide formed, for example, using a thermal oxidation process. The pad oxide layer may act as an adhesion layer between the topmost channel layer1004and the hardmask layer. In some embodiments, the hardmask layer may include silicon nitride, silicon oxynitride, silicon carbonitride, the like, or combinations thereof. In some other embodiments, the hardmask layer may include a material similar as a material of the layers1002/1004such as, for example, Si1-yGey, Si, etc., in which the molar ratio (y) may be different from or similar to the molar ratio (x) of the sacrificial layers1002. The hardmask layer may be formed over the stack (i.e., before pattering the stack) using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD), for example.

The mask layer may be patterned using photolithography techniques. Generally, photolithography techniques utilize a photoresist material (not shown) that is deposited, irradiated (exposed), and developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material, such as the mask layer in this example, from subsequent processing steps, such as etching. For example, the photoresist material is used to pattern the pad oxide layer and pad nitride layer to form a patterned mask.

The patterned mask can be subsequently used to pattern exposed portions of the layers1002and1004and the semiconductor material904to form the fin structures1102and1104, thereby defining trenches (or openings) between adjacent fin structures. When multiple fin structures are formed, each of such trenches may be disposed between any adjacent ones of the fin structures. In some embodiments, the fin structures1102and1104are formed by etching the layers1002-1004and semiconductor material904in the trenches using, for example, reactive ion etching (RIE), neutral beam etching (NBE), the like, or combinations thereof. The etching may be anisotropic. In some embodiments, the trenches may be strips (when viewed from the top) parallel to each other, and closely spaced with respect to each other. In some embodiments, the trenches may be continuous and surround the respective fin structures.

Corresponding to operation710,FIG.12is a cross-sectional view of the semiconductor device800including a number of dummy gate structure,1202and1204, at one of the various stages of fabrication. The cross-sectional view ofFIG.12is cut in a direction along the lengthwise direction of one or more channels (formed by the fin structures) of the semiconductor device800.

The dummy gate structures1202and1204are formed over each of the fin structures1102and1104. The dummy gate structures1202and1204, in parallel with each other, extend along a lateral direction perpendicular to the lengthwise direction of the fin structures1102and1104. As such, each of the dummy gate structures1202and1204can straddle respective (e.g., central) portions of the fin structures1102and1104. That is, a top surface and sidewalls of each of the fin structures1102and1104, at least in part, are in contact with the dummy gate structures1202and1204.

The dummy gate structures1202and1204may each include a dummy gate dielectric and a dummy gate, which are not shown separately for purpose of clarity. To form the dummy gate structure, a dielectric layer may be formed over the fin structure1102or1104. The dielectric layer may be, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, multilayers thereof, or the like, and may be deposited or thermally grown.

A gate layer is formed over the dielectric layer, and a mask layer is formed over the gate layer. The gate layer may be deposited over the dielectric layer and then planarized, such as by a CMP. The mask layer may be deposited over the gate layer. The gate layer may be formed of, for example, polysilicon, although other materials may also be used. The mask layer may be formed of, for example, silicon nitride or the like. After the layers (e.g., the dielectric layer, the gate layer, and the mask layer) are formed, the mask layer may be patterned using suitable lithography and etching techniques. Next, the pattern of the mask layer may be transferred to the gate layer and the dielectric layer by a suitable etching technique to form the dummy gate structure1202/1204.

Upon forming the dummy gate structures1202and1204, a gate spacer (e.g.,1202,1204) may be formed on opposing sidewalls of a corresponding one of the dummy gate structures1202and1204, as shown inFIG.12. The gate spacer1202/1204may be a low-k spacer and may be formed of a suitable dielectric material, such as silicon oxide, silicon oxycarbonitride, or the like. Any suitable deposition method, such as thermal oxidation, chemical vapor deposition (CVD), or the like, may be used to form the gate spacer. The shapes and formation methods of the gate spacer1202/1204, as illustrated inFIG.12, are merely non-limiting examples, and other shapes and formation methods are possible. These and other variations are fully intended to be included within the scope of the present disclosure.

Corresponding to operation712,FIG.13Ais a cross-sectional view of the semiconductor device800including a number of source/drain (S/D) recesses1302at one of the various stages of fabrication. The cross-sectional view ofFIG.13Ais cut in a direction along the lengthwise direction of one or more channels (formed by the fin structures) of the semiconductor device800.

The dummy gate structures1202and1204(together with their corresponding gate spacers) can serve as a mask to recess (e.g., etch) the non-overlaid portions of each of the fin structures1102and1104, which results in the remaining fin structure1102/1104having respective remaining portions of the sacrificial layers1002and channel layers1004alternately stacked on top of one another. As a result, the S/D recesses1302can be formed on opposite sides of the remaining fin structure1102/1104.

The recessing step to form the S/D recesses1302may be configured to have at least some anisotropic etching characteristic. For example, the recessing step can include a plasma etching process, which can have a certain amount of anisotropic characteristic. In such a plasma etching process (including radical plasma etching, remote plasma etching, and other suitable plasma etching processes), gas sources such as chlorine (Cl2), hydrogen bromide (HBr), carbon tetrafluoride (CF4), fluoroform (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), hexafluoro-1,3-butadiene (C4F6), boron trichloride (BCl3), sulfur hexafluoride (SF6), hydrogen (H2), nitrogen trifluoride (NF3), and other suitable gas sources and combinations thereof can be used with passivation gases such as nitrogen (N2), oxygen (O2), carbon dioxide (CO2), sulfur dioxide (SO2), carbon monoxide (CO), methane (CH4), silicon tetrachloride (SiCl4), and other suitable passivation gases and combinations thereof. Moreover, for the recessing step, the gas sources and/or the passivation gases can be diluted with gases such as argon (Ar), helium (He), neon (Ne), and other suitable dilutive gases and combinations thereof to control the above-described etching rates.

Corresponding to operation714(which may be performed in the absence of performing operation704),FIG.13Bis a cross-sectional view of the semiconductor device800in which a buried (or bottom) oxide layer1310is formed upon forming the S/D recesses1302. The cross-sectional view ofFIG.13Ais cut in a direction along the lengthwise direction of one or more channels (formed by the fin structures) of the semiconductor device800. For example, after the S/D recesses1302are formed by etching the fin structures1102and1104that have no semiconductor material904and buried oxide layer902formed therebelow, portions of the substrate802(exposed by the S/D recesses1302) may also be removed (e.g., etched). Such removed portions of the substrate802may be refilled with a dielectric material to form the buried oxide layer1310.

Corresponding to operation716,FIG.14Ais a cross-sectional view of the semiconductor device800(with the buried oxide layer902) that includes source/drain (S/D) structures1402and an interlayer dielectric (ILD)1406, at one of the various stages of fabrication, andFIG.14Bis a cross-sectional view of the semiconductor device800(with the buried oxide layer1310) that includes the S/D structures1402and the ILD1406, at one of the various stages of fabrication. The cross-sectional views ofFIGS.14A-Bare each cut in a direction along the lengthwise direction of one or more channels (formed by the fin structures) of the semiconductor device800.

The S/D structures1402are disposed in the S/D recesses1302(FIGS.13A-B). As such, (at least a lower portion of) the S/D structure1402can inherit the dimensions and profiles of the recesses1302. The S/D structures1402are formed by epitaxially growing a semiconductor material (e.g., from the channel layers of the fin structure1102/1104) in the recesses1302using suitable methods such as metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), the like, or combinations thereof.

Prior to forming the S/D structures1402, end portions of the sacrificial layers1002can be removed (e.g., etched) using a “pull-back” process with a pull-back distance. In an example where the channel layers1004include Si, and the sacrificial layers1002include SiGe, the pull-back process may include a hydrogen chloride (HCl) gas isotropic etch process, which etches SiGe without attacking Si. As such, the Si layers (nanostructures)1004may remain substantially intact during this pull-back process. Consequently, a pair of recesses can be formed on the ends of each of the sacrificial layers1002, with respect to the neighboring channel layers1004. Next, such recesses on the ends of each sacrificial layer1002can be filled with a dielectric material to form inner spacers1410, as shown inFIGS.14A and14B. The dielectric material for the inner spacers may include silicon nitride, boron carbonitride, silicon carbonitride, silicon carbon oxynitride, or any other type of dielectric material (e.g., a dielectric material having a dielectric constant k of less than about 5) appropriate to the role of forming an insulating gate sidewall spacer for transistors.

As further shown inFIGS.14A and14B, the S/D structures1402are disposed on the opposite sides of the fin structure1102/1104to couple to the channel layers1004therein and separate from the sacrificial layers1002of the fin structure1102/1104with the inner spacers1410disposed therebetween. According to various embodiments of the present disclosure, the channel layers1004in each of the fin structures1102and1104may collectively function as the conductive channel of a completed transistor. The sacrificial layers1002in each of the fin structures1102and1104may be later replaced with a portion of an active gate structure that is configured to wrap around the corresponding channel layers.

In some embodiments, the ILD1406can be concurrently formed to respectively overlay at least the S/D structures1402. The ILD1406is formed of a dielectric material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate Glass (BPSG), undoped silicate glass (USG), or the like, and may be deposited by any suitable method, such as CVD, PECVD, or FCVD. After the ILD is formed, an optional dielectric layer (not shown) is formed over the ILD. The dielectric layer can function as a protection layer to prevent or reduces the loss of the ILD in subsequent etching processes. The dielectric layer may be formed of a suitable material, such as silicon nitride, silicon carbonitride, or the like, using a suitable method such as CVD, PECVD, or FCVD. After the dielectric layer is formed, a planarization process, such as a CMP process, may be performed to achieve a level top surface for the dielectric layer. After the planarization process, the top surface of the dielectric layer is level with the top surface of the dummy gate structures1202and1204, in some embodiments.

Corresponding to operation718,FIG.15Ais a cross-sectional view of the semiconductor device800(with the buried oxide layer902) that includes active metal gates,1502and1504, at one of the various stages of fabrication, andFIG.15Bis a cross-sectional view of the semiconductor device800(with the buried oxide layer1310) that includes the active metal gates1502and1504, at one of the various stages of fabrication. The cross-sectional views ofFIGS.15A-Bare each cut in a direction along the lengthwise direction of one or more channels (formed by the fin structures) of the semiconductor device800.

Subsequently to forming the ILD1406, the dummy gate structures1202-1204, and the (remaining) sacrificial layers1002may be concurrently removed. In various embodiments, the dummy gate structures1202-1204and the sacrificial layers1002can be removed by applying a selective etch (e.g., a hydrochloric acid (HCl)), while leaving the channel layers1004substantially intact. After the removal of the dummy gate structures, a gate trench, exposing respective sidewalls of each of the channel layers1004may be formed. After the removal of the sacrificial layers1002(which can further extend the gate trench), respective bottom surface and/or top surface of each of the channel layers1004may be exposed. Consequently, a full circumference of each of the channel layers1004can be exposed. Next, the active gate structure1502and1504are formed to wrap around each of the channel layers1004.

The active gate structures1502-1504each include a gate dielectric and a gate metal (which are not separately shown for the sake of clarity), in some embodiments. The gate dielectric can wrap around each of the channel layers1004, e.g., the top and bottom surfaces and sidewalls. The gate dielectric may be formed of different high-k dielectric materials or a similar high-k dielectric material. Example high-k dielectric materials include a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The gate dielectric may include a stack of multiple high-k dielectric materials. The gate dielectric can be deposited using any suitable method, including, for example, molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, and the like. In some embodiments, the gate dielectric may optionally include a substantially thin oxide (e.g., SiOx) layer, which may be a native oxide layer formed on the surface of each of the channel layers1004.

The gate metal may include a stack of multiple metal materials. For example, the gate metal may be a p-type work function layer, an n-type work function layer, multi-layers thereof, or combinations thereof. The work function layer may also be referred to as a work function metal. Example p-type work function metals may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Example n-type work function metals may include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. A work function value is associated with the material composition of the work function layer, and thus, the material of the work function layer is chosen to tune its work function value so that a target threshold voltage Vtis achieved in the device that is to be formed. The work function layer(s) may be deposited by CVD, physical vapor deposition (PVD), ALD, and/or other suitable process.

Upon forming the active gate structures1502-1504, a number of GAA FETs can be defined (or otherwise formed). For example inFIGS.15A-B, a first GAA FET1510and a second GAA FET1520are formed. The GAA FET1510has the active gate structure1502wrapping around the corresponding channel layers1004and the S/D structures1402disposed on the opposite sides of the active gate structure1502operatively serving as its gate (terminal) and source/drain (terminals), respectively. Similarly, the GAA FET1520has the active gate structure1504wrapping around the corresponding channel layers1004and the S/D structures1402disposed on the opposite sides of the active gate structure1504operatively serving as its gate (terminal) and source/drain (terminals), respectively. Such GAA FETs can respectively or collectively serve as one or more various components of the SRAM device100, for example, the switch transistor306, the transistors220-270of each memory cell190, etc., in accordance with various embodiments.

Corresponding to operation720,FIG.16Ais a cross-sectional view of the semiconductor device800(with the buried oxide layer902) that includes a number of frontside interconnect structures,1602,1604,1606, and1608, andFIG.16Bis a cross-sectional view of the semiconductor device (with the buried oxide layer1310) that includes the frontside interconnect structures1602to1608at one of the various stages of fabrication. The cross-sectional views ofFIGS.16A-Bare each cut in a direction along the lengthwise direction of one or more channels (formed by the fin structures) of the semiconductor device800.

The frontside interconnect structures1602to1608(formed of one or more metal materials, e.g., copper) may be formed based on a single damascene process, a dual damascene process, a reactive ion etching process, and other suitable processes. For example, in a damascene process, one or more trenches/openings are formed in an ILD, and then refilled with one or more metal materials to form the frontside interconnect structures1602to1608. Such an ILD is formed of a dielectric material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate Glass (BPSG), undoped silicate glass (USG), or the like, and may be deposited by any suitable method, such as CVD, PECVD, or FCVD.

It should be appreciated that the frontside interconnect structures1602to1608are provided for illustration purposes, and thus, the semiconductor device800can have any number of each of the frontside interconnect structures1602to1608, while remaining within the scope of the present disclosure. For example, the semiconductor device800can have any number of the frontside interconnect structure1602(which may be a VG connecting an active gate structure to one or more frontside metal tracks), any number of the frontside interconnect structure1604(which may be an MD coupling a S/D structure to one or more frontside metal tracks through a VD), any number of the frontside interconnect structure1606(which may be a VD coupling a S/D structure to one or more frontside metal tracks through an MD), and any number of the frontside interconnect structure1608(which may be an M0 track). Furthermore, the semiconductor device800can have any number of metal tracks disposed over the frontside interconnect structure1608(e.g., M1 tracks, M2 tracks, and so on).

In various embodiments, the frontside interconnect structures1602to1608can electrically connect a corresponding GAA FET to one or more other GAA FETs so as to collectively function as a desired circuit component of the SRAM device100(e.g., a memory cell, a logic gate, etc.). As such, these frontside interconnect structures1602to1608may each be configured to transmit or receive (or otherwise route) a signal.

In some other embodiments, some of these frontside interconnect structures (e.g., M0 tracks1608) may function as a part of the boost capacitor304(e.g., C1′, C2′, C3′, C4′, etc.), as discussed above with respect toFIG.5. For example, two adjacent ones of the metal tracks in one of the frontside metallization layers (e.g., M0 tracks1608shown inFIGS.16A-B) can operatively serve as first and second terminals of one of the sub-capacitors of the boost capacitor304, which cause an internal electric field (extending from one of the terminals to the other). A portion of the ILD interposed between such metal tracks can reduce the electric field and increase the corresponding capacitive value.

Corresponding to operation722,FIGS.17A and17Bare cross-sectional views of the semiconductor device800, with the buried oxide layers902and1310respectively, in which the substrate802is thinned down from its backside at one of the various stages of fabrication. The cross-sectional views ofFIGS.17A-Bare each cut in a direction along the lengthwise direction of one or more channels (formed by the fin structures) of the semiconductor device800.

In the example ofFIG.17A, the substrate802(which is enclosed by dotted lines) is thinned down from its backside through a polishing process (e.g., a chemical-mechanical polishing (CMP) process). The CMP process may not be stopped until the buried oxide layer902is exposed. In the example ofFIG.17B, the substrate802(which is enclosed by dotted lines) is thinned down from its backside through a polishing process (e.g., a chemical-mechanical polishing (CMP) process). The CMP process may not be stopped until the buried oxide layer1310is exposed.

Corresponding to operation724,FIG.18Ais a cross-sectional view of the semiconductor device800(with the buried oxide layer902) that includes a number of backside interconnect structures,1802and1804, andFIG.18Bis a cross-sectional view of the semiconductor device (with the buried oxide layer1310) that includes the backside interconnect structures1802to1804at one of the various stages of fabrication. The cross-sectional views ofFIGS.18A-Bare each cut in a direction along the lengthwise direction of one or more channels (formed by the fin structures) of the semiconductor device800.

The backside interconnect structures1802to1804(formed of one or more metal materials, e.g., copper) may be formed based on a single damascene process, a dual damascene process, a reactive ion etching process, and other suitable processes. For example, in a damascene process, one or more trenches/openings are formed in an ILD, and then refilled with one or more metal materials to form the backside interconnect structures1802to1804. Such an ILD is formed of a dielectric material such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate Glass (BPSG), undoped silicate glass (USG), or the like, and may be deposited by any suitable method, such as CVD, PECVD, or FCVD.

It should be appreciated that the backside interconnect structures1802to1804are provided for illustration purposes, and thus, the semiconductor device800can have any number of each of the backside interconnect structures1802to1804, while remaining within the scope of the present disclosure. For example, the semiconductor device800can have any number of the backside interconnect structure1802(which may be a BV connecting an active gate structure or S/D structure to one or more backside metal tracks), and any number of the backside interconnect structure1804(which may be an BM0 track). Furthermore, the semiconductor device800can have any number of metal tracks disposed over the backside interconnect structure1804(e.g., BM1 tracks, BM2 tracks, and so on).

In various embodiments, some of these backside interconnect structures (e.g., BM0 tracks1804) may function as a part of the boost capacitor304(e.g., C1, C2, C3, C4, etc.), as discussed above with respect toFIG.5. For example, two adjacent ones of the metal tracks in one of the backside metallization layers (e.g., BM0 tracks1804shown inFIGS.18A-B) can operatively serve as first and second terminals of one of the sub-capacitors of the boost capacitor304, which cause an internal electric field (extending from one of the terminals to the other). A portion of the ILD interposed between such metal tracks can reduce the electric field and increase the corresponding capacitive value.

In one aspect of the present disclosure, a memory device is disclosed. The memory device includes a memory cell; a bit line coupled to the memory cell; and a voltage generator coupled to the bit line and configured to provide a negative voltage to the bit line. The voltage generator includes a transistor; and a first capacitor having a first terminal and a second terminal electrically coupled to a drain and a gate of the transistor, respectively. The drain and the gate of the transistor are formed on a first side of a substrate, and the first and second terminals of the first capacitor are formed on a second side of the substrate opposite to the first side.

In another aspect of the present disclosure, a memory device is disclosed. The memory device includes a memory array formed on a front side of a substrate. The memory array is accessible through a plurality of bit lines. The memory device includes a switch transistor formed on the front side of the substrate. The switch transistor is operatively coupled to the plurality of bit lines. The memory device includes a first capacitor formed on a back side of the substrate. The first capacitor is configured to reduce a voltage level present on at least one of the plurality of bit lines, in response to the switch transistor being turned off.

In yet another aspect of the present disclosure, a method for fabricating memory devices is disclosed. The method includes forming, on a front side of a substrate, a plurality of memory transistors configured as a memory array. The method includes forming, on the front side of the substrate, a plurality of bit lines operatively coupled to the memory array. The method includes forming, on the front side of the substrate, a switch transistor operatively coupled to the plurality of bit lines. The method includes forming, on a back side of the substrate, a first capacitor configured to reduce a voltage level present on at least one of the plurality of bit lines to a negative value.

As used herein, the terms “about” and “approximately” generally mean plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, about 1000 would include 900 to 1100.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.