Patent ID: 12224009

DESCRIPTION OF THE EMBODIMENTS

The present invention is further described in detail in combination with the accompany drawings and specific embodiments.

1. A 1T-1MTJ Cell Structure and Operation Process:

As shown in part (a) ofFIG.1, a 1T-1MTJ cell comprises a MTJ and a NMOS, the two terminals of the MTJ device are respectively connected with a bit line BL and an NMOS drain, the NMOS gate is connected with a word line WL, and an NMOS source is connected with another bit line BLB. When magnetization directions of a free layer and a fixed layer in the MTJ are the same, the MTJ is in a parallel state, and the corresponding equivalent resistance RPis small, indicating that “0” is stored; and when the magnetization directions are opposite, the MTJ is in an anti-parallel state, and the corresponding equivalent resistance is RAPlarge, indicating that “1” is stored. A switching ratio of the MTJ is represented by

TMR(TMR=RAP-RPRP).
Bias conditions of read and write operations of the 1T-1MTJ cell are shown in part (b) ofFIG.1. When writing data, the WL is set to VEN-WRITEto turn on a transistor and provide appropriate bias voltages on the BL and BLB to generate a large current to control the magnetization direction of the free layer in the MTJ and realize writing “1” or “0”. When reading data, as shown inFIG.2, the WL is set to VEN-READto turn on the transistor and a read current IREADis applied on the cell, so that a read voltage VP(VAP) corresponding to the state “0” (“1”) is generated on a BL node. This voltage is compared with a reference voltage VREFthrough a two-stage detection amplifier SA. Note that RREFin part (a) and part (b) ofFIG.2is the equivalent resistance of a bias transistor, as shown in part (c) ofFIG.2, and the magnitude of the corresponding reference voltage VREFon the BL is between VPand VAPto achieve a read operation.
2. Overall Structure and Operation Process of a CAM Array of 1T-1MTJ:

As shown inFIG.3, the CAM array of 1T-1MTJ comprises an M*N CAM core for storing contents, additional reference rows for storing “0” and “1” and reference columns for storing “0” and “1”, a row decoder, a column decoder, transmission gates ENs, write driver WDs, search current sources Isearchs and two-stage detection amplifiers SAs etc. All 1T-1MTJ cells in the reference row for storing “0” and reference column for storing “0” store data “0”, and all 1T-1MTJ cells in the reference row for storing “1” and reference column for storing “1” store data “1”. Four cells located at the intersection of the reference row and reference column are a 2T structure, wherein one NMOS is also controlled by the word line WL, and another NMOS is under the control of gate potential Vbwith an equivalent resistance RREFbetween RPand RAP. The 2T cell ensures that the reference voltage on the BL of the reference row is different from read voltages of the other storage rows during the search. The BL of the storage row is connected to positive input terminals of two two-stage detection amplifiers SAs, and the two two-stage detection amplifiers SAs are a two-stage detection amplifier SA0and a two-stage detection amplifier SA1respectively. The BL of the reference row storing “0” is connected to negative input terminals of all the two-stage detection amplifiers SA0s, and the BL of the reference row storing “1” is connected to negative input terminals of all two-stage detection amplifiers SA1s.

FIG.4shows a specific structure of the two-stage detection amplifier SA, which comprises a first-stage differential pre-amplifier and a second-stage dynamic latch voltage comparator. When a clock signal CLK is at a high level, the two output terminals of the two-stage detection amplifier SA are precharged to a high level; when CLK is at a low level, a voltage difference between the two input terminals of the two-stage detection amplifier SA is amplified by a positive feedback of a cross-coupled invertor in a second-stage dynamic latch voltage comparator, so that the output terminals of the two-stage detection amplifier SA produces a comparison result. If the two-stage detection amplifier SA directly uses the second-stage dynamic latch voltage comparator, when CLK jumps, due to imbalance of capacitor loads on the two input terminals of the two-stage detection amplifier SA (namely, the BL of the storage row and the BL of the reference row), the two BLs have different levels of feedback noise, leading to a differential error. Therefore, the first-stage differential pre-amplifier is introduced to suppress the feedback noise and improve the search reliability.

The whole operation process of the CAM array of the 1T-1MTJ is as follows:

(1) Before the 1T-1MTJ CAM array starts to work, data is stored for each CAM cell, that is, after information is encoded into binary data, two Write Drivers WDs in each row provide a sufficient write current by enabling the transmission gates EN and WL. The write operation is performed row by row, which is divided into two steps of writing “0” and writing “1”. During the writing operation, the transmission gates ENs of all unselected rows and WLs of unselected columns should be turned off to avoid to write interference.

(2) For each search operation, a two-step search scheme is utilized:

(2.1) Step 1: finding all the mismatch conditions that “1” is stored while “0” is searched. As shown in part (a) ofFIG.5, a WL corresponding to all “0” bits in a search sequence and a WL of the reference column storing the “0” are enabled, WLs of the remaining columns are set to 0, the BLB is grounded, and the transmission gate is turned off. Assuming that there are K cells storing “1” out of I cells involved in the search for “0” in a row, there are I-K cells storing “0” in practice, as well as a cell storing “0” in the reference column storing “0”. The resistance of the I+1 cells connected in parallel is

RP+Ro⁢nI-K+1//RA⁢P+RonK,
where Ronis on-resistance of NMOS controlled by WL in each cell. Then a read voltage VSEARCH0generated on the BL of this row by applying the search current ISEARCHis as follows:

VSEARCH⁢0=ISEARCH(RP+Ro⁢nI-K+1//RA⁢P+Ro⁢nK)

At the same time, I cells storing “0” and 1 2T cell are enabled on the reference row storing “0”, and the resistance after being connected in parallel is

RP+Ro⁢nI//(Rr⁢e⁢f+Ro⁢n),
and then the reference voltage VREF0generated by applying the search current ISEARCHon the BL of the reference row storing “0” is as follows:

VR⁢E⁢F⁢0=IS⁢E⁢A⁢R⁢C⁢H(RP+Ro⁢nI//(Rref+Ro⁢n))

When CLK is at a high level (the precharging stage), the two output terminals of the two-stage detection amplifier SA0are precharged to a high level; when CLK becomes low (the search stage), if there is a mismatch condition that “1” is stored while “0” is searched in the row, VSEARCH0is greater than VREF0, so that ML0at the reverse output terminal of the two-stage detection amplifier SA0is pulled down to the ground; and if it matches for this row, VSEARCH0is less than VREF0and ML0remains a high level.

(2.2) Step 2: finding all the mismatch conditions that “0” is stored while “1” is searched. As shown in part (b) ofFIG.5, a WL corresponding to all “1” bits in a search sequence and a WL of the reference column storing the “1” are enabled, WLs of the remaining columns are set to 0, the BLB is grounded, and the transmission gate is turned off. Assuming that there are L cells storing “0” out of J cells involved in the search for “1” in a row, there are J-L cells storing “1” in practice, as well as a cell storing “1” in the reference column storing “1”. The resistance of the J+1 cells connected in parallel is

RAP+RonJ-L+1//RP+RonL,
and then a read voltage VSEARCH1generated on the BL of this row by applying the search current ISEARCHis as follows:

VSEARCH⁢1=ISEARCH(RAP+Ro⁢nJ-L+1//RP+Ro⁢nL)

At the same time, J cells storing “0” and 1 2T cell are enabled on the reference row storing “1”, and the resistance after being connected in parallel is

RA⁢P+Ro⁢nJ//(Rr⁢e⁢f+Ro⁢n),
and then the reference voltage VREF1generated by applying the search current ISEARCHon the BL of the reference row storing “1” is as follows:

VR⁢E⁢F⁢1=IS⁢E⁢A⁢R⁢C⁢H(RA⁢P+Ro⁢nJ//(Rref+Ro⁢n))

When CLK is at a high level (the precharging stage), the two output terminals of the two-stage detection amplifier SA1are precharged to a high level; when CLK becomes low (the search stage), if there is a mismatch condition that “0” is stored while “1” is searched in the row, VSEARCH1is less than VREF1, so that ML1at the positive output terminal of the two-stage detection amplifier SA0is pulled down to the ground; and if it matches for this row, VSEARCH1is greater than VREF1and ML1remains a high level.

Therefore, combining the above two-step search, only if ML0is high in the first step and ML1is high in the second step, it indicates that the stored content and the search sequence match, otherwise there is a mismatch.FIG.6shows an example of the two-step search scheme when the store content is “1100”. When the matched data “1100” is searched, as shown in part (a) ofFIG.6, ML0remains high in the first step and ML1remains high in the second step, so the search result matches. When the mismatched data “0110” is searched, as shown in part (a) ofFIG.6, in the first step, ML1is pulled down to the bottom in the search stage, and in the second step, ML1is pulled down to the bottom in the search stage, so the search result does not match. By using the above two-step search scheme, a parallel search function is realized in the 1T-1MTJ CAM array.

3. A Segmented Design Scheme of the 1T-1MTJ CAM Array:

As a search word length increases, the difference between the read voltage and the reference voltage becomes smaller, which would affect the search reliability. Therefore, the present invention provides a segmented design scheme to support a long byte search. As shown in part (a) ofFIG.7, the CAM array is segmented, and each segment contains reference rows, reference columns and a two-stage detection amplifier to generate the search result of each segment at the same time. Then, the search result of the whole row is obtained through the logic circuit and the global detector.FIG.7in part (b) explains internal structures of the logic circuit and the global detector, the output ML of each segment in the logic circuit is short-circuited together through a conventional inverter and a tilt inverter. The width to length ratio β of NMOS in the tilt invertor is smaller than the width to length ratio α of PMOS, which makes the tilt invertor have strong pull-down effect. Therefore, only when the output of each segment is at a high level, the output of each segment logic circuit after short-circuited is at a high level, thus forming an AND logic. Then, in the global detector, the search result in the first step is connected to an AND gate by a D-latch and the search result in the second step is also connected to the AND gate to obtain the search result of the whole row.FIG.7in part (c) shows a relationship between the clock signal and an enabling signal of D latch. Finally, the global detector output is observed in the search stage of the second step. If the level is high, it indicates that the row matches. If the level is low, a mismatch has occurred for at least one segment.

The functions and effects of the present invention are further illustrated and demonstrated by the following simulation experiment:

1. Simulation Conditions

In the experiment, the MTJ is simulated using a physical-circuit-based compatible SPECTRE and SPICE Model with efficient design and analysis. The basic transistors use a 45 nm Predictive Technology Model (PTM) with a voltage of 1.1V. The key technical parameters of the MTJ set by the simulation are shown in the following table.

Name of parameterDetailed descriptionDefault valueDDiameter of MTJ40nmTMR0TMR rate without Vbias150%TfreeThickness of free layer1.3nmToxideThickness of oxide layer0.75nmR · AResistance value * area5Ω · μm2ΔTMRProcess change rate of TMR rate3%ΔTfreeProcess change rate of thickness of3%oxide layerΔToxideProcess change rate of thickness of3%free layerVDDPower supply voltage1.1V

In the simulation, the CAM design of 1T-1MTJ is simulated using a SPECTRE software. In addition to the simulation of the CAM design in the present invention, we compare our results with five CAM designs proposed in a non-patent document 1 (A. T. Do, C. Yin, K. S. Yeo, and T. T.-H. Kim, “Design of a power-efficient cam using automated background checking scheme for small match line swing,” in 2013 Proceedings of the ESSCIRC (ESSCIRC). IEEE, 2013, pp. 209-212), a non-patent document 2 (S. Matsunaga, A. Katsumata, M. Natsui, T. Endoh, H. Ohno, and T. Hanyu, “Design of anine-transistor/two-magnetic-tunnel-junctioncell-based low-energy nonvolatile ternary content-addressable memory,” Japanese Journal of Applied Physics, vol. 51, no. 2S, p. 02BM06, 2012), a non-patent document 3 (B. Song, T. Na, J. P. Kim, S. H. Kang, and S.-O. Jung, “A 10t-4mtj nonvolatile ternary cam cell for reliable search operation and a compact area,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 6, pp. 700-704, 2016), a non-patent document 4 (C. Wang, D. Zhang, L. Zeng, E. Deng, J. Chen, and W. Zhao, “A novel mtj-based non-volatile ternary content-addressable memory for high-speed, low-power, and high-reliable search operation,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 4, pp. 1454-1464, 2018) and a non-patent document 5 (C. Wang, D. Zhang, L. Zeng, and W. Zhao, “Design of magnetic nonvolatile tcam with priority-decision in memory technology for high speed, low power, and high reliability,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 2, pp. 464-474, 2019).

The comparison metrics mainly include the number of transistors, the area of each CAM cell, write energy consumption of each CAM cell per write, search error rate, search delay and search energy consumption of each CAM cell per search. For the CAM design in the present invention, the measurement of the search error rate and search delay is in a worst case, that is, only one CAM cell does not match; the average energy consumption of writing unit data “0” and writing unit data “1” is taken as the write energy consumption. The measurement of search energy consumption is done by using an average case where half of the CAM cells in a row match.

2. Simulation Results

1) Functional Verification of the 1T-1MTJ CAM

1.1)FIG.8is simulation waveforms of writing “0” and “1” in the 1T-1MTJ CAM cell. The MTJ cell is initially in a parallel state, enabling ENTGand WL to control the transmission gate EN and the transistor of 1T-1MTJ cell conduction respectively. SL is set to zero, two write drivers WD1and WD2are set to be 2V and ground respectively to generate a write current, so that the MTJ becomes in an anti-parallel state. Then, the write drivers WD1and WD2are set to ground and 2V respectively, and the MTJ changes from the anti-parallel state back to the parallel state, so as to complete the verification of the write function.

1.2)FIG.9shows simulation waveforms of a 1T-1MTJ CAM array using a two-step search scheme to search “1010” for stored contents “1010”, “1011”, “0010” and “0011”. Enabling SL to generate the search current ISEARCH, ENTGis set to zero to turn off the transmission gate. In the first step of search, WL[P] corresponding to the reference column for storing “0” and WL[1] and WL[3] corresponding to all “0” bits in the search sequence are enabled. When CLK is low, ML0storing contents “1011” and “0011” becomes low, indicating that there is a mismatch condition that “1” is stored while “0” is searched. In the second step, WL[AP] corresponding to the reference column storing “1” and WL[2] and WL[4] corresponding to all “0” bits in the search sequence are enabled. When CLK is low, ML1storing contents “0010” and “0011” becomes low, indicating that there is a mismatch condition that “0” is stored while “1” is searched. Combining the above two steps, only the ML0storing content “1010” remains high in the first step and ML1remains high in the second step, indicating a match, and the remaining three rows do not match, thus completing the verification of the search function.

2) Write Speed and Write Energy Consumption Analysis

The setting of the transfer gate transistor width, the enabling voltage Venon WL and ENTGand the write voltage VWRITEon the write driver WD would affect the write efficiency of the 1T-1MTJ CAM array.FIG.10in part (a) shows the relationship between the minimum VWRITErequired to complete the write operation and Venon the WL and ENTGunder different transmission gate transistor widths. It can be seen that the required minimum VWRITEdecreases with the increase of Ven, while a large transmission gate transistor width can also lead to the reduced minimum VWRITE. In order to suppress area overhead and avoid transistor breakdown, the width of NMOS (PMOS) transistor in the transmission gate is set as 180 nm (360 nm), and the size of Venis 1.3V. In this configuration, the write speed and write energy consumption under different sizes of VWRITEare explored as shown in part (b) ofFIG.10. With the VWRITEincreases, the write time becomes shorter. When VWRITEis 2V, each write can be completed within 20 ns as shown inFIG.8, and the average energy consumption of each write is 1.26 pJ/bit.

3) Search Reliability Analysis

Under the premise that the process change rate of MTJ TMR rate, oxide layer thickness and free layer thickness is set as 3%, and the process change rate of transistor width and threshold voltage is set as 10%, the search error rate (SER) is obtained by performing a Monte Carlo simulation with only one CAM cell mismatch to perform search reliability analysis.FIG.11in part (a) shows that as the search word length N increases, SER also increases gradually, so segmented design is needed to ensure the search reliability. On the other hand, as shown in part (b) ofFIG.11, the increase of TMR rate of MTJ would lead to the increase of read voltage gap between different states of 1T-1MTJ CAM cell, thus reducing SER. At the same time, when the supply voltage increases, the current difference between the two discharge branches in the second-stage dynamic latch voltage comparator of SA would also increase, leading to the decrease of SER.FIG.11in part (d) shows that when the search current ISEARCHis too small, SA is difficult to accurately compare the voltage difference, thus introducing additional SER. However, when ISEARCHis greater than 25 μA, the effect on SER is negligible.

4) Search Delay and Search Energy Consumption Analysis

After confirming the search reliability of the 1T-1MTJ CAM design, it is necessary to analyze the search delay and search energy consumption. In the precharging stage (CLK is at a high level), not only the output of SA needs to be precharged to a high level, but also the first differential pre-amplifier needs to prepare two voltage signals for the input of the second stage to participate in the comparison, so that the SA can produce the comparison results when CLK becomes low. Therefore, when the bias current is increased to improve the bandwidth of the first stage, as shown in part (a) ofFIG.12, the time required for the precharge stage would be reduced. In addition,FIG.12in part (b) shows that the search delay increases with the increase of the word length N, which is caused by the increase of parasitic capacitance on the BL. At the same time, the energy consumption per unit search shows an opposite trend, which has two reasons: (1) the voltage on the BL decreases as the word length N increases, and (2) the search time does not increase substantially as the word length N increases.FIG.12in part (c) shows that a higher supply voltage can reduce the search delay and further improve the search energy efficiency.FIG.12in part (d) shows that with the increase of ISEARCH, the voltage difference between the read voltage and the reference voltage increases, which reduces the search delay, but also reduces the search energy efficiency.

5) Performance Comparison

The following table presents the comparison of the metrics of the CAM design based on the single MTJ in the present invention with other CAM designs.

Non-patentNon-patentNon-patentNon-patentNon-patentTheREFERENCEdocumentdocumentdocumentdocumentdocumentpresentDOCUMENTS12345inventionNon-volatilityNoYesYesYesYesYesCell structure10T9T-2MTJ10T-4MTJ15T-4MTJ20T-6MTJ1T-1MTJCell plane3.36.848.2810.7618.050.06(μm2)SER (144-bit)030.0%18.5%2.7%2.7%8.3%Search delay1.070.201.280.170.170.17(ns)Search energy0.7737.375.070.171.062.72consumption(fJ/bit)Writing energy0.030.555.791.592.381.26consumption(pJ/bit)

The above table summarizes the technical metrics of the 1T-1MTJ CAM and other CAMs, in which the word length of segment of the 1T-1MTJ CAM is set to 16 bit per segment. As can be seen from the above table, the cell area of the 1T-1MTJ CAM in the present invention is 1.82% of that of the 10T cell based on the traditional CMOS technology, and this advantage is further amplified when compared with other MTJ-based CAMs. Although the 1T-1MTJ CAM needs the reference rows, reference columns, and SAs to complete the search operation, these additional area overhead is negligible when performing the long byte search, and the search delay of the 1T-1MTJ CAM is only 16% of that of 10T CAM. Although the search energy consumption of 15T-4MTJ/20T-6MTJ CAMs is lower than that of the 1T-1MTJ CAM, the area overhead is much higher. In addition, the search energy consumption of the 1T-1MTJ CAM would be further reduced when the word length of the segment increased. At the same time, because there are fewer MTJs and transistors in the writing path of the 1T-1MTJ CAM, compared with 10T-4MTJ/15T-4MTJ/20T-6MTJ CAM, the writing energy efficiency is increased by 4.60 times/1.26 times/1.89 times. Although the writing energy consumption of 9T-2MTJ CAM is lower, the search error rate of 1T-1MTJ CAM is only 28% of that of 9T-2MTJ CAM.

It can be seen from the above results that the present invention not only has non-volatility which is difficult to be achieved by the CMOS design, and robustness against the process changes, but also has the characteristics of compact design, low energy consumption and low delay. In addition, the above results also validate the effectiveness of the 1T-1MTJ CAM array utilizing the two step search scheme and the segmented design in the data-intensive search applications.

The above embodiments are used to explain the present invention, not to restrict it, and without departing from the spirit and protection scope of claims in the present invention, any modification or alteration made to the present invention falls within the protection scope of the present invention.