Patent ID: 12190079

MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments will be described with reference to drawings. However, the embodiments can be implemented with many different modes, and it will be readily appreciated by those skilled in the art that modes and details thereof can be changed in various ways without departing from the spirit and scope thereof. Thus, the present invention should not be interpreted as being limited to the following description of the embodiments.

In this specification and the like, ordinal numbers such as first, second, and third are used in order to avoid confusion among components. Thus, the terms do not limit the number of components. In addition, the terms do not limit the order of components. For example, a “first” component in one embodiment in this specification and the like can be referred to as a “second” component in other embodiments or claims. Furthermore, for example, a “first” component in one embodiment in this specification and the like can be omitted in other embodiments or claims.

In the drawings, the same elements, elements having similar functions, elements formed of the same material, elements formed at the same time, or the like are sometimes denoted by the same reference numerals, and description thereof is not repeated in some cases.

<Structure of Semiconductor Device>

A structure of a semiconductor device of one embodiment of the present invention is described.

FIG.1is a block diagram of a semiconductor device10. The semiconductor device10includes a product-sum operation circuit11, a controller12, a data processing circuit13, and an SRAM14.

The product-sum operation circuit11includes a plurality of operation circuits21and a plurality of switch circuits22. Note that the product-sum operation circuit is a circuit that performs a product-sum operation. A product-sum operation is an operation in which data obtained by multiplication are added. The product-sum operation circuit11can perform a preset operation without being limited to a product-sum operation. Accordingly, the product-sum operation circuit11may be referred to as a programmable circuit.

The operation circuit21included in the product-sum operation circuit11is what is called a programmable operation circuit whose function can be changed to a function set by control by a context signal. The operation circuit21includes a multiplier circuit, an adder circuit, and a memory circuit. The multiplier circuit is a circuit that outputs multiplication data corresponding to a product of input data and data stored in the memory circuit. The adder circuit is a circuit that outputs addition data corresponding to the sum of data corresponding to an operation result input from a different operation circuit and the multiplication data. The data corresponding to the operation result input from the different operation circuit is addition data in the different operation circuit. The memory circuit is a circuit that stores data (weight data) corresponding to a weight parameter in a neural network. This data has high resistance to noise when being a digital signal, and switching of the weight data can be performed at high speed. The operation circuit21can perform product-sum operations using different weight parameters by switching the weight data in response to switching of the context signal. A context signal that is input to the product-sum operation circuit11and switches the function of the operation circuit21is referred to as a context signal context_W.

The product-sum operation circuit11is a circuit that performs a product-sum operation using a convolutional neural network, for example. By performing a produce-sum operation using different weight parameters in response to switching of a context and using a different connection state in response to the switching of the context, product-sum operations in different layers of a fully connected layer, a convolution layer, and the like can be performed. Input data input to the product-sum operation circuit11is, for example, image data.

The switch circuit22included in the product-sum operation circuit11is what is called a programmable switch circuit whose function can be switched to a function set by control by a context signal. The switch circuit22is provided between the operation circuits21. The switch circuit22includes a transistor functioning as a switch and a memory circuit. The switch included in the switch circuit22has a function of switching a connection state between the operation circuits21. The memory circuit included in the switch circuit22is a circuit that stores data for switching the connection state of the switch. The switch circuit22allows data obtained in the operation circuit21to be input to/output from a predetermined circuit by switching the connection state of the switch in response to switching of the context signal. A context signal that is input to the product-sum operation circuit11and switches the function of the switch circuit22is referred to as a context signal context_C.

The controller12is a circuit having a function of generating the context signal context_C and the context signal context_W on the basis of a context signal input from the outside. A context signal input to the controller12is referred to as a context signal context_in. In addition to the context signal context_in, a clock signal clk is input to the controller12.

The controller12performs output so that on the basis of the context signal context_in, the number of contexts switched on the basis of the context signal context_C becomes smaller than the number of contexts switched on the basis of the context signal context_W For example, inFIG.1, the context signal context_in is a 2-bit signal and denoted by context_in[1:0]. The context signal context_in [1:0] means a combination of a context signal context_in[0] and a context signal context_in[1].

In the example ofFIG.1, like the context signal context_in, the context signal context_W is denoted by context_W[1:0]. The context signal context_W[1:0] is a 2-bit signal and can switch four contexts. In the example ofFIG.1, the context signal context_C is denoted by context_C. In the example ofFIG.1, the context signal context_C is denoted by context_C. The context signal context_C is a 1-bit signal and can switch two contexts. Note that the numbers of contexts based on the context signal context_W and the context signal context_C are just examples, and as described above, the number of contexts switched on the basis of the context signal context_C is only required to be smaller than the number of contexts switched on the basis of the context signal context_W.

The data processing circuit13is a circuit that performs, on the data obtained in the product-sum operation circuit11, operation processing different from a product-sum operation. Examples of operation processing performed by the data processing circuit13include operation processing with a rectified linear unit (hereinafter, ReLU), which is an activation function, and pooling operation processing. As the activation function, besides ReLU, a sigmoid function, a hyperbolic tangent (tanh) function, or a step function can be used, for example.

The SRAM (Static Random Access Memory)14is a circuit having a function of holding data necessary for an operation in the product-sum operation circuit11. The SRAM14is referred to as a data holding circuit in some cases. The timing of input or output of held data to/from the SRAM14is determined by control by the controller12.

FIGS.2(A) to2(E)are block diagrams for describing operation of the operation circuit21and the switch circuit22for performing product-sum operation processing in the product-sum operation circuit11. The operation circuit21is a circuit capable of switching weight data used for multiplication processing in response to the context signal context_W, and the switch circuit22is a circuit capable of switching a connection between the operation circuits21in response to the context signal context_C.

The operation circuit21includes a register circuit that holds input data and a memory circuit that stores weight data. Input data Illand weight data Ware input to and held in the operation circuit21inFIG.2(A). The input data Illis held in the register in the operation circuit21. The weight data W includes a plurality of weight data (e.g., four weight data, W0, W1, W2, and W3) and is stored in the memory circuit in the operation circuit21.

The operation circuit21includes a decoder that decodes the context signal context_W and generates a switching signal for selecting weight data.FIG.2(B)shows the context signal context_W[1:0] input to the operation circuit21. The context signal context_W[1:0] is decoded by the decoder included in the operation circuit21.FIG.2(B)shows a state where the weight data W0is selected from the four weight data W by a switching signal obtained by decoding the context signal context_W[1:0].

FIG.2(C)shows operation of outputting, to an operation circuit21B, data obtained by multiplication of the input data hi held in an operation circuit21A and the selected weight data W0(represented by W0×Illin the diagram). In the operation circuit21A, a switching circuit therein is switched to output the obtained multiplication data.

The switch circuit22includes a decoder that decodes the context signal context_C and generates a switching signal for switching a conduction state of the switch.FIG.2(C)shows the context signal context_C input to the switch circuit22. The context signal context_C is decoded by the decoder included in the switch circuit22. By the switching signal obtained by the decoding, between which of the plurality of the operation circuits an electrical connection is made is selected.FIG.2(C)shows a state in which the switch circuit22between the operation circuit21A and the operation circuit21B is brought into a conduction state.

FIG.2(D)shows operation in which product-sum operation data (represented by W×I+W0×Illthe diagram; referred to as MAC) that is the sum of the multiplication data obtained in the operation circuit21A and data (W×I) output from a different operation circuit is output to the operation circuit21B. In the operation circuit21A, the switching circuit therein is switched to output the sum of the obtained multiplication data and the data output from the different operation circuit.FIG.2(D)shows a state different from the state of the output of the multiplication data inFIG.2(C)because of the switching circuit.

FIG.2(E)shows operation in which product-sum operation data held in the operation circuit21A (MAC1in the diagram) is output to the operation circuit21B, and product-sum operation data (MAC1+MAC2in the diagram) obtained by adding it and product-sum operation data held in the operation circuit21A (MAC2in the diagram) is output. In the operation circuit21A, the switching circuit therein is switched to output the sum of the held product-sum operation data and product-sum operation data output from a different operation circuit. The switch circuit22between the operation circuit21A and the operation circuit21B is brought into a conduction state by a switching signal obtained by decoding the context signal context_C.FIG.2(E)shows a state in which the switch circuit22between the operation circuit21A and the operation circuit21B is brought into a conduction state.

As described with reference toFIGS.2(A) to2(E), the operation circuit21and the switch circuit22can switch weight data used for operation processing, data output by operation processing, and the connection between the operation circuits21, in response to switching signals obtained by decoding the context signal context_W and the context signal context_C. Note that specific circuit examples of the operation circuit21and the switch circuit22are described later.

Here, an operation model in which product-sum operation processing is performed by switching of the weight data and switching of operation processing such as output of multiplication data or output of addition data shown inFIGS.2(A) to2(E)is described with reference toFIGS.3(A) to3(F).

In the description ofFIGS.3(A) to3(F), the case of performing the product-sum operation of filters (W11, W12, W13, W14), (W21, W22, W23, W24), (W31, W32, W33, W34), and (W41, W42, W43, W44) having four different types of weight data and input data (I1, I2, I3, I4) is described. By using the above method for the product-sum operation processing described with reference toFIG.2, product-sum operations can proceed in parallel while data obtained by a plurality of operation circuits are looped.

A product-sum operation with a plurality of filters (a convolutional operation) can be expressed by a matrix-vector product as shown in Formula (1).

(Y1Y2Y3Y4)=(W11W12W13W14W21W22W23W24W31W23W33W34W41W24W43W44)⁢(I1I2I3I4)(1)

A 4×4 matrix that consists of W corresponds to weight data (elements of one row correspond to components of one filter). A 1×4 matrix that is composed of I corresponds to input data. A 1×4 matrix that is composed of Y (Y1to Y4) corresponds to data obtained by a product-sum operation.

When applied to an operation model for performing a product-sum operation using the above-described operation circuit21, the matrix-vector product of Formula (1) can be shown as inFIG.3(A). That is, the input data I1to I4are held as input data31of respective operation circuits21. Furthermore, the data (weight data) corresponding to the weight parameters of the filters (W11, W12, W13, W14), (W21, W22, W23, W24), (W31, W32, W33, W34), and (W41, W42, W43, W44) can be written to the memory circuits in the respective operation circuits21, and the multiplication data can be generated using one of different weight data32_1to32_4in response to a switching signal obtained by decoding by the context signal context_W Hereinafter, the description is made assuming that the operation processing progresses every clock (1 clk).

After 1 clk after input data is written to the operation circuit21, given weight data from a set of weight parameters is set by a switching signal obtained by decoding the context signal context_W. Specifically, the weight data (W11, W22, W33, W44) that are underlined inFIG.3(B)are set, and the operation circuits21generate multiplication data with the held input data (I1, I2, I3, I4). The operation circuits21generate multiplication data (W11·I1, W22·I2, W33·I3, W44·I4) of the input data31and the weight data32_1.

Next, inFIG.3(C)after 1 clk from the state ofFIG.3(B), weight data different from those inFIG.3(B)are set by a switching signal obtained by decoding the context signal context_W. Specifically, the weight data (W41, W12, W23, W34) that are underlined inFIG.3(C)are set, and the operation circuits21generate multiplication data with the held input data (I1, I2, I3, I4). The operation circuits21generate multiplication data (W41·I1, W12·I2, W23·I3, W34·I4) of the input data31and the weight data32_2. Furthermore, the operation circuits21output, to the operation circuits21in the next columns, data33_1to33_4(W11·I1, W22·I2, W33·I3, W44·I4), which are generated in the state ofFIG.3(C), as next-column addition data.

Next, inFIG.3(D)after 1 clk from the state ofFIG.3(C), weight data different from those inFIG.3(C)are set by a switching signal obtained by decoding the context signal context_W. Specifically, the weight data (W31, W42, W13, W24) that are underlined inFIG.3(D)are set, and the operation circuits21generate multiplication data with the held input data (I1, I2, I3, I4). For example, the operation circuits21generate multiplication data (W31·I1, W42·I2, W13·I3, W24·I4) of the input data31and the weight data32_3. Furthermore, the operation circuits21output, to the operation circuits21in the next columns, the data33_1to33_4(W12·I2+W11·I1, W23·I3+W22·I2, W34·I4+W33·I3, W41·I1+W44·I4) obtained by adding the multiplication data (W41·I1, W12·I2, W23·I3, W34·I4) to the addition data (W11·I1, W22·I2, W33·I3, W44·I4), which are output inFIG.3(C), as next-column addition data (also referred to as product-sum operation data).

Next, inFIG.3(E)after 1 clk from the state ofFIG.3(D), weight data different from those inFIG.3(D)are set by a switching signal obtained by decoding the context signal context_W. Specifically, the weight data (W21, W32, W43, W14) that are underlined inFIG.3(E)are set, and the operation circuits21generate multiplication data with the held input data (I1, I2, I3, I4). For example, the operation circuits21generate multiplication data (W21·I1, W32·I2, W43·I3, W14·I4) of the input data31and the weight data32_4. Furthermore, the operation circuits21output, to the operation circuits21in the next columns, the data33_1to33_4(W13·I3+W12·I2+W11·I1, W24·I4+W23·I3+W22·I2, W31·I1±W34·I4+W33·I3, W42·I2+W41/1±W44·I4) obtained by adding the multiplication data (W31·I1, W42·I2, W13—I3, W24·I4) to the addition data (W12·I2+W11·I1, W23·I3+W22·I2, W34·I4+W33·I3, W41·I1+W44·I4), which are output inFIG.3(D), as next-column addition data.

Next, inFIG.3(F)after 1 clk from the state inFIG.3(E), the operation circuits21obtain data obtained by adding the multiplication data (W21·I1, W32·I2, W43·I3, W14·I4) to the addition data (W13·I3+W12·I2+W11·I1, W24·I4+W23·I3+W22·I2, W31·I1±W34·I4+W33·I3, W42·I2+W41·I1±W44·I4), which are output inFIG.3(E). As shown inFIG.3(F), the respective operation circuits21can obtain product-sum operation data such as data33_2(W21·I1+W24·I4+W23·I3+W22·I2), data33_3(W32·I2+W31·I1+W34·I4+W33·I3), data33_4(W43·I3+W42·I2+W41·I1+W44·I4), and data33_1(W14·I4+W13·I3+W12·I2+W11·I1). The obtained data correspond to Y (Y1to Y4) expressed by the matrix-vector product.

Data obtained by using the operation model ofFIGS.3(A) to3(F)are shifted in succession, whereby an enormous number of product-sum operations can be efficiently performed. The product-sum operation circuit11included in the semiconductor device10can execute product-sum operations by concurrently processing multiplication data and addition data between the operation circuits21as in pipeline processing in a processor, and by shifting the multiplication data and the addition data between the plurality of operation circuits21. Accordingly, when operation processing with product-sum operations is performed by limited hardware, massively parallel data processing can be efficiently performed with limited circuit resources.

With the architecture inFIGS.3(A) to3(F), data access to an external memory is unnecessary during an operation, and product-sum operation data can be efficiently obtained while data are transmitted in parallel between all the operation circuits21. Therefore, a problem of the increase in circuit size in a neural network, accompanied by the increase in input data, weight data, and the like, can be solved.

In the case where the operation model in which product-sum operation processing described with reference toFIGS.3(A) to3(F)is performed is applied to the semiconductor device10inFIG.1, the operation model can be achieved by switching weight data used for operation processing, data output by operation processing, or a connection between the operation circuits21in response to the context signal context_W and the context signal context_C as described with reference toFIGS.2(A) to2(E).

Specifically, in the case where the operation model shown inFIGS.3(A) to3(F)is achieved, the operation model can be achieved when the number of contexts for switching weight data for product-sum operation processing is four, that is, when a data set of the weight data W0, the weight data W1, the weight data W2, and the weight data W3is used in switching of weight data. Furthermore, in the case of addition processing as shown inFIG.2(E), in which the product-sum operation data obtained by the operation model shown inFIGS.3(A) to3(F)are added to each other, weight data is not necessary; however, the addition processing can be achieved by a data set of one of the weight data W0to W3. In that case, the context signal context_W may be decoded to obtain switching signals context_W0to context_W3for switching contexts.

In the case where the operation model shown inFIGS.3(A) to3(F)is achieved, the operation model can be achieved when the number of contexts in the connection structure is one, that is, the connection structure can be achieved by a switching signal context_C0. Furthermore, in the case where the product-sum operation data obtained by the operation model shown inFIGS.3(A) to3(F)are added to each other as shown inFIG.2(E), the addition processing can be achieved when the number of contexts in the connection structure is one, that is, the connection structure can be achieved by a switching signal context_C1. In that case, the context signal context_C may be decoded to obtain the switching signals context_C0and context_C1for switching contexts.

The above structure can be described with reference to block diagrams illustrated inFIGS.4(A) to4(E). InFIGS.4(A) to4(E), in addition to the operation circuit21and the switch circuit22, product-sum operation processing23(denoted by “×+” in the diagrams) is shown as a kind of operation processing. Moreover, addition processing24(denoted by “+” in the diagram) is shown as a kind of operation processing.

InFIGS.4(A) to4(D), product-sum operation processing is performed by fixing the connection structure by the switching signal context_C0and switching the weight data by the switching signals context_W0to W3. For example, inFIG.4(A), the connection structure is set by the switching signal context_C0, the weight data is set to the weight data W0by the switching signal context_W0, and product-sum operation processing in which addition data of a different operation circuit is added to multiplication data is performed. InFIG.4(B), the connection structure is set by the switching signal context_C0, the weight data is set to the weight data W1by the switching signal context_W1, and product-sum operation processing in which addition data of a different operation circuit is added to multiplication data is performed. InFIG.4(C), the connection structure is set by the switching signal context_C0, the weight data is set to the weight data W2by the switching signal context_W2, and product-sum operation processing in which addition data of a different operation circuit is added to multiplication data is performed. InFIG.4(D), the connection structure is set by the switching signal context_C0, the weight data is set to the weight data W3by the switching signal context_W3, and product-sum operation processing in which addition data of a different operation circuit is added to multiplication data is performed.

As inFIGS.4(A) to4(D), the multiplication data obtained by switching of the weight data W0to W3can be added to a value obtained by a different operation circuit and sequentially output to another operation circuit. Thus, it is possible to obtain product-sum operation data obtained by adding the multiplication data obtained by using the different weight data to each other. That is, the state inFIG.3(F)can be obtained.

InFIG.4(E), addition processing is performed by fixing the connection structure by the switching signal context_C1, and switching the weight data to the switching signal context_W0. The weight data is set to the weight data W0by the switching signal context_W0to perform addition processing in which the product-sum operation data obtained above are added to each other. With this structure, data corresponding to the sum of the product-sum operation data held in the operation circuits21can be obtained.

The connection structure is common to the above structures using the switching signal context_C0, and only the weight data are changed. With this structure, the number of contexts of the connection structure can be reduced. That is, the circuit area (a load of a signal line) can be reduced, leading to improvement in an operation speed and reduction in power consumption.

The structures inFIGS.3(A) to3(F)andFIGS.4(A) to4(E)are effective in a convolutional neural network in which product-sum operation processing is performed by switching weight data sequentially for input data having different forms.

In this specification, a neural network refers to a general model that is modeled on a biological neural network, determines the connection strength of neurons by learning, and has the capability of solving problems. A neural network includes an input layer, a middle layer (also referred to as a hidden layer), and an output layer. A neural network having two or more middle layers is referred to as a deep neural network (DNN). Learning by a deep neural network is referred to as deep learning. A circuit capable of executing a neural network by hardware is referred to as a neural network circuit.

In describing a neural network in this specification, to determine a connection strength of neurons (also referred to as a weight coefficient or a weight parameter) from existing information is sometimes referred to as learning.

Moreover, in this specification, to draw a new conclusion from a neural network formed using connection strengths obtained by learning is sometimes referred to as inference.

FIG.5is a block diagram showing the flow of operation processing of a convolutional neural network.FIG.5illustrates an input layer61, an intermediate layer62(also referred to as hidden layer), and an output layer63. In the input layer61, an input process (denoted by Input in the diagram) of input data is shown. In the intermediate layer62, a convolution layer65, a convolution layer66, a convolution layer68(denoted by Conv. in the diagram), a pooling layer67, and a pooling layer69(denoted by Pool. in the diagram) are shown. In the output layer63, a fully-connected layer70(denoted by Full in the diagram) is shown. The layers in which the operation processing is performed in the input layer61, the intermediate layer62, and the output layer63are examples, and another operation processing such as a softmax operation may be performed in actual operation processing of a convolutional neural network.

In the convolution layer65, the convolution layer66, the convolution layer68, and the fully-connected layer70illustrated inFIG.5, product-sum operation processing of input data and weight data is performed. In operation processing in each layer, input data having different forms are input, and weight data are switched, and product-sum operation processing is performed. An increase in the number of contexts due to an increase in a data set of weight data causes an increase in circuit size. In the structure of one embodiment of the present invention, in the controller12, a context signal is generated so that the number of contexts for switching the connection structure becomes smaller than the number of contexts for switching weight data. Therefore, a semiconductor device in which a reduction in sizes of a memory circuit for storing configuration data on the connection structure and a switch circuit is achieved can be obtained. In addition, when the circuit size is reduced, an increase in power consumption can be suppressed.

<Structure of Controller>

A structure example of the controller12included in the semiconductor device10is described.

FIG.6is a block diagram for describing a structure example of the controller12. The controller12inFIG.6includes a flip-flop42and an I2C controller44in addition to a decoder43and a lookup table45.

The controller12has a function of holding an input context signal context_in (denoted by context_in[1:0] in the diagram) in the flip-flop42and outputting it as a context signal context_W (denoted by context_W[1:0] in the diagram). The decoder43has a function of outputting the context signal context_C in response to an external signal through a serial bus such as I2C, referring to data stored in the lookup table45.

Note that other than I2C, a bus standard such as the Universal Serial Bus or the Serial Peripheral Interface can be used.

As illustrated inFIG.6, the controller12includes the lookup table45. The lookup table45defines a correspondence relation between the numbers of contexts of the context signal context_W and the context signal context_C, which are different from each other. As a method for setting a parameter of the lookup table45, for example, there is a method the context signal context_C is switched via the I2C controller44by I2C communication. Setting of the parameter of the lookup table45may be executed in configuration operation. When a parameter that can be controlled by a user by I2C communication can be defined, a variety of circuit structures can be achieved.

Next, the operation of the controller12is described.

FIG.7is a timing chart for describing the context signal context_in[1:0] and a circuit state of the product-sum operation circuit11inFIG.1. The context signal context_in[1:0] by external input is a signal that is not synchronized with the clock signal clk.

In the description ofFIG.7, the context signal context_in[1:0] is a 2-bit signal, and four contexts, i.e., “3” to “0”, can be represented. In the description ofFIG.7, the context signal context_W[1:0] is a 2-bit signal, and the context can be represented by four, “3” to “0”. In the description ofFIG.7, the context signal context_C is a 1-bit signal, and the context can be represented by two signals, an H-level signal and an L-level signal.

At Time T0, the context is changed from “3” to “0” by the context signal context_W[1:0]. The context signal context_W[1:0] is decoded by the decoder43illustrated inFIG.6. The context signal context_C is changed from “1” to “0” by setting of a parameter of the lookup table45. As a result, at Time T1when the next clock signal clk rises (changes from an L level to an H level), the switching signal context_W0and the switching signal context_C0become an H level. Furthermore, the switching signal context_W3and the switching signal context_C1become a L level, and the circuit structure circuit_state is changed from the state of the circuit D to the state of the circuit A.

At Time T1, the context is changed from “0” to “1” by the context signal context_W[1:0]. The context signal context_C is kept at “0” by setting of a parameter of the lookup table45. As a result, at Time T2when the next clock signal clk rises, the switching signal context_W1becomes an H level. Furthermore, the switching signal context_W0becomes an L level, and the circuit structure circuit_state is changed from the state of the circuit A to the state of the circuit B.

At Time T2, the context is changed from “1” to “2” by the context signal context_W[1:0]. The context signal context_C is kept at “0”. As a result, at Time T3when the next clock signal clk rises, the switching signal context_W2becomes an H level. Furthermore, the switching signal context_W1becomes an L level, and the circuit structure circuit_state is changed from the state of the circuit B to the state of the circuit C.

At Time T3, the context is changed from “2” to “3” by the context signal context_W[1:0]. The context signal context_C is changed from “0” to “1” by setting of a parameter of the lookup table45. As a result, at Time T4when the next clock signal clk rises, the switching signal context_W3becomes an H level. Furthermore, the switching signal context_W2becomes an L level, and the circuit structure circuit_state is changed from the state of the circuit C to the state of the circuit D.

As described above, the switching of the context is performed so that the number of contexts varies depending on objects such as the operation circuit21and the switch circuit. With this structure, a structure in which the context signal is not changed in the case where the circuit structure is not changed can be achieved. When the number of necessary contexts can be reduced, the switch circuits corresponding to the reduced contexts are unnecessary, leading to a reduction in the circuit area and an increase in the speed of the circuit operation.

<Structure of Operation Circuit>

An example of a structure of the operation circuit21included in the product-sum operation circuit11is described. As described with reference toFIGS.2(A) to2(E), the operation circuit21has a function of holding or outputting multiplication data obtained by multiplication of input data and weight data and a function of holding or outputting product-sum operation data obtained by adding the multiplication data and data (addition data) output from a different operation circuit.

FIG.8(A)is a block diagram illustrating an example of the operation circuit21. The operation circuit21includes, for example, an input register51, a memory circuit52, a multiplier circuit53, an adder circuit54, an output register55A, an output register55B, a switching circuit56A, a memory element57A, a switching circuit56B, a memory element57B, a switching circuit56C, and a memory element57C.

Data sin is input to the input register51. The input register51holds the data sin by control by a latch signal slat. The input register51outputs data sout. The input register51outputs data sdata to the multiplier circuit53through the switching circuit56A.

The switching circuit56A is a circuit for controlling, as the data sdata input to the multiplier circuit53, whether the data sin is output or whether data held in the input register51is output. The memory element57A has a function of switching electrical connection in the switching circuit56A in response to switching of the context signal context_C.

The context signal context_W[1:0] is input to the memory circuit52. The memory circuit52includes a dataset corresponding to contexts. A dataset is data corresponding to a plurality of weight data used in product-sum operation processing. The memory circuit52outputs one weight data among the plurality of weight data corresponding to contexts, as weight data cmout in accordance with the context signal. The plurality of weight data stored in the memory circuit52are effective when operations are performed while a context is changed, for example, when the number of filters used in convolutional operation processing is large. Performing multiplication of different weight data and input data while a context is changed enables multiplication using one multiplier circuit under a variety of conditions.

A nonvolatile memory is used as the memory circuit52. For the memory circuit52, an OS memory using a transistor (an OS transistor) whose channel formation region contains an oxide semiconductor (OS) is useful. By providing the memory circuit52in each operation circuit21, access to (read and write of) the above-described weight data is achieved at higher speed and lower power consumption than in the case of providing the memory circuit52outside the product-sum operation circuit11. A structure example of the memory circuit52is described later.

The multiplier circuit53generates multiplication data mout corresponding to the product of the data sdata and the weight data cmout. The multiplication data mout is output to the adder circuit54and the switching circuit56B.

The adder circuit54generates addition data aout corresponding to the sum obtained by adding the multiplication data mout to addition data ain. The addition data aout is output to the switching circuit56B.

The switching circuit56B is a circuit for controlling whether the multiplication data mout is output or whether the addition data aout is output. The switching circuit56B is a circuit for controlling whether the addition data ain is output or whether the addition data aout is output. The memory element57B has a function of switching electrical connection in the switching circuit56B in response to switching of the context signal context_C.

The output register55A and the output register55B hold data selected in the switching circuit56B and are reset by control by a reset signal reset. With the structure including the output register55A and the output register55B, it is possible to prevent an error of an operation result due to a signal delay.

The switching circuit56B is a circuit for controlling whether data held in the output register55A is output or whether data input to the output register55A is output as output data out as it is. The memory element57C has a function of switching electrical connection in the switching circuit56C in response to switching of the context signal context_C.

FIG.8(B)is a block diagram of a modification example of the operation circuit21described with reference toFIG.8(A). In the operation circuit21illustrated inFIG.8(B), a power switch58and a memory element57D are illustrated in addition to the components described with reference toFIG.8(A). The memory element57D can switch the on/off state of the power switch58in response to switching of the context signal context_C. With a structure in which the power switch58in the operation circuit21that is not used in operation processing can be turned off, power consumption due to current generated in standby operation can be reduced in unused operation circuits21among a large number of operation circuits21.

Next, the structure of the memory circuit52included in the operation circuit21is described with reference toFIGS.9(A) and9(B). The memory circuit52has a function of holding weight data for each of a plurality of memory cells provided in accordance with the number of contexts and outputting the weight data cmout selected in response to a switching signal obtained by decoding the context signal context_W, to the multiplier circuit53.

The memory circuit includes a flip-flop71, a decoder72, and a plurality of memory cells73. The memory cell73includes transistors74to76.

The flip-flop71has a function of holding the context signal context_W. The decoder72has a function of decoding the context signal context_W and outputting the switching signals context_W0to context_W3. The memory cell73has a function of storing weight data (configuration data) and performing output in accordance with control by the switching signals context_W0to context_W3.

One of a source and a drain of the transistor74is connected to a wiring for writing weight data. A gate of the transistor74is connected to a wiring through which a word signal word (denoted by words1to4in the diagram) is supplied. A gate of the transistor75is connected to the other of the source and the drain of the transistor74. A node where the gate of the transistor75is connected to the other of the source and the drain of the transistor74is referred to as a node FN (denoted by FN0to FN3in the diagram). One of a source and a drain of the transistor75is connected to a fixed potential line (a ground line in the diagram). The other of the source and the drain of the transistor75is connected to one of a source and a drain of the transistor76. A gate of the transistor76is connected to a wiring through which one of the switching signals context_W0to context_W3is supplied. The other of the source and the drain of the transistor76is connected to one of a source and a drain of the transistor77and an inverter latch78. The other of the source and the drain of the transistor77is connected to a wiring through which a precharge voltage (Vpre in the diagram) is supplied. A gate of the transistor77is connected to a precharge control line (precharge in the diagram). The inverter1atch78is connected to a wiring through which the weight data cmout is supplied.

The transistor74is a transistor (OS transistor) including an oxide semiconductor in a channel formation region. The OS transistor has a low off-state current. Therefore, the transistor74is brought into a non-conduction state, whereby a potential held in the node FN can be held. The potential held in the node FN corresponds to data for 1-bit weight data. The potential held in the node FN can control a conduction state or a non-conduction state of the transistor75. Therefore, when the transistor76is brought into a conduction state by the context signal W0, the potential of the wiring through which the weight data cmout corresponding to a potential held in the node FN is supplied can be switched.

Note that in the case where an OS transistor is not used unlike inFIG.9(A), a structure inFIG.9(B)may be employed in which data corresponding to weight data is stored using an inverter latch79.

In the semiconductor device10including the operation circuit21described in the above embodiment, the multiplier circuit and the adder circuit each including an Si transistor and the memory circuit including an OS transistor can be integrated into one die.

Furthermore, with reference toFIGS.10(A) and10(B), the operation of the memory circuit52illustrated inFIG.9(A)is described.FIG.10(A)is a circuit diagram illustrating extracted part of the circuit inFIG.9(A). InFIG.10(A), data of the wiring for reading the weight data cmout that is connected to the memory cell73, the transistor77, and the inverter latch78is shown as data cmout_b. The data of the wiring corresponds to a signal obtained by inversion of the logic of the weight data cmout.

Next,FIG.10(B)shows timing charts for describing an operation example of the memory circuit52illustrated inFIG.10(A).

In the timing charts shown inFIG.10(B), change in the potentials of a word signal word1(hereinafter, abbreviated to word1), a signal configuration data that corresponds to configuration data supplied to a bit line (hereinafter, abbreviated to configuration data), and the node FN0(hereinafter, abbreviated to FN0); change in the potentials of the switching signal context_W0(hereinafter, abbreviated to context_W0), and the precharge control line precharge (hereinafter, abbreviated to precharge); the data cmout_b (hereinafter, abbreviated to cmout_b); and the weight data cmout (hereinafter, abbreviated to cmout) are shown.

The operation of writing of the configuration data at Time t1to t4is described. First, at Time t2, the word1becomes an H level, and the configuration data is 1, and thus the FN0becomes an H level. At this time, the precharge is at an L level, and thus the cmout_b becomes an H level, and the cmout_b becomes an L level.

At Time t3, the word1becomes an L level, and after that, the FN0is fixed at an H level.

Next, the operation of reading of configuration data at Time t11to t15is described. At Time t12, the precharge becomes an L level. As a result, the cmout_b becomes an H level, and the cmout becomes an L level (precharge operation).

At Time t13, the precharge becomes an H level, and the context_W0becomes an H level. The FN0is kept at an H level. As a result, the cmout_b becomes an L level, and the cmout becomes an H level.

FIG.10(B)shows the case where the data held in the node FN0of the memory circuit52is 1 (H level). Note that in the case where the data is 0 (L level), even when the context_W0becomes an H level at Time t12, the cmout_b is kept at an H level, and the cmout is kept at an L level.

The operation of the memory circuit52illustrated inFIG.9(A)can be explained as described above.

Next, with reference toFIGS.11(A) to11(C), a read control circuit89that can generate a signal to be supplied to the precharge control line precharge illustrated inFIG.9(A)is described.

Note that the read control circuit89is a circuit for generating a signal to be supplied to the precharge control line precharge and the switching signals context_W0to context_W3to be supplied to the memory circuit52, on the basis of input switching signals context_IN_W0to context_IN_W3generated by the decoder72.

A structure example of the read control circuit89is described. The read control circuit89illustrated inFIG.11(B)includes a delay circuit90(denoted by Delay in the diagram) and a control circuit91(denoted by Read_CTR in the diagram).

The delay circuit90includes a plurality of stages of delay circuits including buffers. Wirings through which the input switching signals context_IN_W0to context_IN_W3are supplied are connected to the delay circuits. The delay circuit90has a function of delaying and outputting the input switching signals context_IN_W0to context_IN_W3.

The control circuit91has a function of generating a signal to be supplied to the precharge control line precharge and the switching signals context_W0to context_W3to be supplied to the memory circuit52, by using operation of the input switching signals context_IN_W0to context_IN_W3and the delay signals.

With reference to a timing chart ofFIG.11(C), the operation of generating each signal in the read control circuit89illustrated inFIG.11(B)is described. InFIG.11(C), Time t21to t24are shown for explanation.

At Time t22, the input switching signal context_IN_W0changes from an L level to an H level, and the input switching signal context_IN_W1changes from an H level to an L level. As a result, a signal supplied to the precharge control line precharge changes from an H level to an L level.

At Time t23, the input switching signal context_IN_W0changes from an L level to an H level because it is delayed by the delay circuit90. In addition, the input switching signal context_IN_W1changes from an H level to an L level because it is delayed by the delay circuit90. As a result, a signal supplied to the precharge control line precharge changes from an L level to an H level. Moreover, the switching signal context_W0changes from an L level to an H level, and the switching signal context_W1changes from an H level to an L level.

Thus, the operation of the read control circuit89illustrated inFIG.11(A)can be described.

FIG.12illustrates an example of an IC incorporating the semiconductor device. An IC7000illustrated inFIG.12includes a lead7001and a circuit portion7003. In the circuit portion7003, the various circuits described in the embodiment are provided on one die. The circuit portion7003has a stacked-layer structure, which is broadly divided into a Si transistor layer7031, a wiring layer7032, and an OS transistor layer7033. Since the OS transistor layer7033can be provided to be stacked over the Si transistor layer7031, the size of the IC7000can be easily reduced.

Although a QFP (Quad Flat Package) is used as a package of the IC7000inFIG.12, the embodiment of the package is not limited thereto.

All the multiplier circuits and the adder circuits including Si transistors and the memory circuits including OS transistors can be formed in the Si transistor layer7031, the wiring layer7032, and the OS transistor layer7033. In other words, elements included in the semiconductor device can be formed through the same manufacturing process. Thus, the number of steps in the manufacturing process of the IC illustrated inFIG.12does not need to be increased even when the number of elements is increased, and accordingly the semiconductor device can be incorporated into the IC at low cost.

<Structure of Switch Circuit>

The structure of the switch circuit22is described with reference to a semiconductor device10A different from the semiconductor device10illustrated inFIG.1.

FIG.13(A)is a block diagram for describing the semiconductor device10A. With the structure of the semiconductor device10A illustrated inFIG.13(A), the operation circuit21and the switch circuit22can be designed as a unit circuit in one area (a local area), which is preferable. The other structures are the same as those inFIG.1.

The switch circuit22illustrated inFIG.13(A)has a function of switching the connection state with the operation circuits21on the left, right, top, and bottom sides in order to switch the connection structure between the operation circuits21. InFIG.13(A), “U”, “D”, “L”, and “R” represent wirings for electrically connecting to the operation circuits21in a “top” direction, a “bottom” direction, a “left” direction, and a “right” direction.

FIG.13(B)is a diagram illustrating an example of the switch circuit22. In the diagram, the data sout and the operation data out correspond to output data of the operation circuit21described with reference toFIGS.8(A) and8(B). The wiring through which the data sout and the operation data out are output is connected to any of wirings on the left, right, top, and bottom sides. A switch25for connecting wirings is provided at the intersection point. The switch25includes a memory circuit for storing configuration data on a connection structure.

The structure of the switch25including a memory circuit is described with reference toFIGS.14(A) and14(B). The memory circuit included in the switch25has a function of holding data corresponding to a connection structure for each of a plurality of memory cells provided in accordance with the number of contexts and switching connection between the wirings on the left, right, top, and bottom sides and the operation circuit21selected in accordance with the switching signal obtained by decoding the context signal context_C.

The switch25includes a flip-flop80, a decoder81, and a plurality of memory cells83. The memory cell83includes transistors84to86. Note thatFIG.14(A)illustrates a switch for transmitting 4-bit data as an example.

The flip-flop80has a function of holding the context signal context_C. The decoder72has a function of decoding the context signal context_C and outputting the switching signals context_C0to context_C1. The memory cell83has a function of storing data corresponding to connection information and performing output in accordance with control by the switching signals context_C0to context_C1.

One of a source and a drain of the transistor84is connected to a wiring for writing connection information (configuration data). A gate of the transistor84is connected to a wiring through which the word signal word (denoted by words1and2in the diagram) is supplied. A gate of the transistor85is connected to the other of the source and the drain of the transistor84. A node where the gate of the transistor85and the other of the source and the drain of the transistor84are connected is referred to as a node FN (denoted by FN0and FN1in the diagram). One of a source and a drain of the transistor85is electrically connected to a wiring87. The other of the source and the drain of the transistor85is connected to one of a source and a drain of the transistor86. A gate of the transistor86is connected to a wiring for supplying one of the switching signal context_C0or the switching signal context_C1. The other of the source and the drain of the transistor86is connected to a wiring to which data (out, sout) of the operation circuit21is output.

The transistor84is a transistor (an OS transistor) including an oxide semiconductor in a channel formation region. The off-state current of an OS transistor is low. Thus, a potential held in the node FN can be held by bringing the transistor84into a non-conduction state.

The potential held in the node FN can control a conduction state or a non-conduction state of the transistor85. Thus, when the transistor86is brought into a conduction state by the switching signal context_C0, the potential of the data of the operation circuit21corresponding to the potential held in the node FN can be transmitted to the wiring87.

In the case where an OS transistor is not used, a structure inFIG.14(B)may be employed in which data corresponding to weight data is stored using an inverter latch88.

<Structure of Local Area>

A structure of a local area26illustrated inFIG.13(A)is described with reference toFIG.15.

As described above, the two context signals, the context signal context_W[1:0] and the context signal context_C are input from the controller12to the local area26illustrated inFIG.15.

In the local area26illustrated inFIG.15, the flip-flop71and the decoder72described above are illustrated. The decoder72decodes the context signal context_W[1:0] and outputs the switching signal context_W0to the switching signal context_W3to the operation circuit21.

The operation circuit21includes a configuration memory28, a transistor76, and an operation portion27. The configuration memory28is a memory including the transistor74and the transistor75illustrated inFIG.9(A)and can hold charge corresponding to data in the node FN. The transistor76corresponds to the transistor76illustrated inFIG.9(A). The operation portion27corresponds to the multiplier circuit53and the adder circuit54illustrated inFIGS.8(A) and8(B).

The switch circuit22includes a configuration memory29, the transistor86, and the wiring87. The configuration memory29is a memory including the transistor84and the transistor85illustrated inFIG.14(A)and can hold charge corresponding to data in the node FN. The transistor86corresponds to the transistor86illustrated inFIG.14(A). The wiring87corresponds to the wiring87illustrated inFIG.14(A).

FIG.16illustrates a structure for transmitting the context signal context_W and the context signal context_C from the controller12to a plurality of the local areas26included in the product-sum operation circuit11. The product-sum operation circuit11has a structure in which wirings for transmitting the context signal context_W and the context signal context_C have a structure similar to that of a clock tree, and the signals are input to the flip-flops71and80included in the local area26in order to achieve high-speed switching of contexts.

Output signals of the flip-flops71and80are decoded by the decoders72and81and then supplied to the transistors76and86for selecting a context in the local area26. The signals are supplied to the local area26that is a limited region; therefore, wiring delay and the like are reduced, and the transistors76and86can be controlled to be brought into a conduction state or a non-conduction state at high speed. In particular, when the number of contexts becomes large, the number of lines of signals to be supplied is increased because of a buffer tree; therefore, with the structure in which output signals of the flip-flops71and80in the local area26are decoded by the decoders72and81, the number of the context signals can be reduced. With this structure, timing control in switching of a context becomes easy, and thus the operation can be stabilized even at a high operation frequency.

<Electronic Device>

Examples of an electronic device including the above semiconductor device are described with reference toFIG.17.

A robot2100illustrated inFIG.17(A)includes an operation device2110, an illuminance sensor2101, a microphone2102, an upper camera2103, a speaker2104, a display2105, a lower camera2106, an obstacle sensor2107, and a moving mechanism2108.

The above semiconductor device can be used for the operation device2110, the illuminance sensor2101, the upper camera2103, the display2105, the lower camera2106, the obstacle sensor2107, and the like of the robot2100.

The microphone2102has a function of detecting a speaking voice of a user, an environmental sound, and the like. The speaker2104also has a function of outputting sound. The robot2100can communicate with a user using the microphone2102and the speaker2104.

The display2105has a function of displaying various kinds of information. The robot2100can display information desired by a user on the display2105. The display2105may be provided with a touch panel.

The upper camera2103and the lower camera2106each have a function of taking an image of the surroundings of the robot2100. The obstacle sensor2107can detect an obstacle in the direction where the robot2100advances with the moving mechanism2108. The robot2100can move safely by recognizing the surroundings with the upper camera2103, the lower camera2106, and the obstacle sensor2107.

A flying object2120illustrated inFIG.17(B)includes an operation device2121, a propeller2123, and a camera2122and has a function of flying autonomously.

The above semiconductor device can be used for the operation device2121and the camera2122of the flying object2120.

FIG.17(B)is an external view illustrating an example of a car. An automobile2980includes a camera2981and the like. The automobile2980also includes various sensors and the like such as an infrared radar, a millimeter wave radar, and a laser radar. The automobile2980judges traffic information therearound such as the presence of a guard rail1201or a pedestrian with analyzing an image taken by the camera2981, and thus can perform automatic driving.

In the automobile2980, the above semiconductor device can be used for the camera2981.

<Notes on Description of this Specification and the Like>

The following are notes on the description of the structures in the above embodiments.

One embodiment of the present invention can be constituted by appropriately combining the structure described in an embodiment with any of the structures described in the other embodiments. In addition, in the case where a plurality of structure examples are described in one embodiment, the structure examples can be combined with each other as appropriate.

Note that a content (or part thereof) in an embodiment can be applied to, combined with, or replaced with another content in the same embodiment and/or a content (or part thereof) in another embodiment or other embodiments.

Note that in each embodiment, a content described in the embodiment is a content described with reference to a variety of diagrams or a content described with text disclosed in the specification.

Note that by combining a diagram (or part thereof) described in one embodiment with another part of the diagram, a different diagram (or part thereof) described in the embodiment, and/or a diagram (or part thereof) described in another embodiment or other embodiments, much more diagrams can be created.

In this specification and the like, components are classified on the basis of the functions and shown as blocks independent of each other in block diagrams. However, in an actual circuit or the like, it may be difficult to separate components on the basis of the functions, so that one circuit may be associated with a plurality of functions or several circuits may be associated with one function. Therefore, the segmentation of a block in the block diagrams is not limited by any of the components described in the specification, and can be differently determined as appropriate depending on situations.

In drawings, the size, the layer thickness, or the region is determined arbitrarily for description convenience. Therefore, the size, the layer thickness, or the region is not limited to the illustrated scale. Note that the drawings are schematically shown for clarity, and embodiments of the present invention are not limited to shapes or values shown in the drawings. For example, the following can be included: variation in signal, voltage, or current due to noise or difference in timing.

In this specification and the like, the terms “one of a source and a drain” (or a first electrode or a first terminal) and “the other of the source and the drain” (or a second electrode or a second terminal) are used to describe the connection relation to a source and a drain of a transistor. This is because a source and a drain of a transistor are interchangeable depending on the structure, operation conditions, or the like of the transistor. Note that the source or the drain of the transistor can also be referred to as a source (or drain) terminal, a source (or drain) electrode, or the like as appropriate depending on the situation.

In addition, in this specification and the like, the term such as an “electrode” or a “wiring” does not limit a function of the component. For example, an “electrode” is used as part of a “wiring” in some cases, and vice versa. Moreover, the term “electrode” or “wiring” also includes the case where a plurality of “electrodes” or “wirings” are formed in an integrated manner, for example.

In this specification and the like, voltage and potential can be interchanged with each other as appropriate. The term “voltage” refers to a potential difference from a reference potential. When the reference potential is a ground voltage, for example, “voltage” can be replaced with “potential”. The ground potential does not necessarily mean 0 V. Potentials are relative values, and the potential applied to a wiring or the like is changed depending on the reference potential, in some cases.

Note that in this specification and the like, the terms such as “film” and “layer” can be interchanged with each other depending on the case or circumstances. For example, the term “conductive layer” can be changed into the term “conductive film” in some cases. For another example, the term “insulating film” can be changed into the term “insulating layer” in some cases.

In this specification and the like, a switch is in a conduction state (on state) or in a non-conduction state (off state) to determine whether current flows therethrough or not. Alternatively, a switch has a function of selecting and changing a current path.

Examples of a switch include an electrical switch and a mechanical switch. That is, any element can be used as a switch as long as it can control current, without limitation to a certain element.

Examples of the electrical switch include a transistor (e.g., a bipolar transistor or a MOS transistor), a diode (e.g., a PN diode, a PIN diode, a Schottky diode, a MIM (Metal Insulator Metal) diode, a MIS (Metal Insulator Semiconductor) diode, or a diode-connected transistor), and a logic circuit in which such elements are combined.

Note that in the case of using a transistor as a switch, a “conduction state” of the transistor refers to a state where a source and a drain of the transistor can be regarded as being electrically short-circuited. Furthermore, a “non-conduction state” of the transistor refers to a state where the source and the drain of the transistor can be regarded as being electrically disconnected. Note that in the case where a transistor operates just as a switch, there is no particular limitation on the polarity (conductivity type) of the transistor.

An example of a mechanical switch is a switch formed using a MEMS (micro electro mechanical systems) technology, such as a digital micromirror device (DMD). Such a switch includes an electrode that can be moved mechanically, and operates by controlling conduction and non-conduction in accordance with movement of the electrode.

In this specification and the like, the channel length refers to, for example, the distance between a source and a drain in a region where a semiconductor (or a portion where current flows in a semiconductor when a transistor is on) and a gate overlap each other, or a region where a channel is formed in a top view of the transistor.

In this specification and the like, the channel width refers to, for example, the length of a portion where a source and a drain face each other in a region where a semiconductor (or a portion where current flows in a semiconductor when a transistor is on) and a gate electrode overlap each other, or a region where a channel is formed.

In this specification and the like, the expression “A and B are connected” means the case where A and B are electrically connected as well as the case where A and B are directly connected. Here, the expression “A and B are electrically connected” means the case where electric signals can be transmitted and received between A and B when an object having any electric action exists between A and B.

REFERENCE NUMERALS

10: semiconductor device,10A: semiconductor device,11: product-sum operation circuit,12: controller,13: data processing circuit,14: SRAM, T0: time, T1: time, T2: time, T3: time, T4: time, W0: weight data, W1: weight data, W2: weight data, W3: weight data,21: operation circuit,21A: operation circuit,21B: operation circuit,22: switch circuit,31: input data,32_1to32_4: weight data,33_1to33_4: product-sum operation data,23: product-sum operation processing,24: sum operation processing,61: input layer,62: intermediate layer,63: output layer,65: convolution layer,66: convolution layer,67: pooling layer,68: convolution layer,69: pooling layer,70: fully-connected layer,42: flip-flop,43: decoder,44: I2C controller,45: lookup table,51: input register,56A-56C: switching circuit,57A-57D: memory element,52: memory circuit,53: multiplier circuit,54: adder circuit,55A-55B: output register,58: power switch,71: flip-flop,72: decoder,73: memory cell,74: transistor,75: transistor,76: transistor,77: transistor,78: inverter latch,7000: IC,7001: lead,7003: circuit portion,7031: Si transistor layer,7032: wiring layer,7033: OS transistor layer,26: local area,25: switch,27: operation portion,80: flip-flop,81: decoder,83: memory cell,84: transistor,85: transistor,86: transistor,87: wiring,89: read control circuit,90: delay circuit,91: control circuit,28: configuration memory,29: configuration memory,1201: guard rail,2100: robot,2101: illuminance sensor,2102: microphone,2103: upper camera,2104: speaker,2105: display,2106: lower camera,2107: obstacle sensor,2108: moving mechanism,2110: operation device,2120: flying object,2121: operation device,2122: camera,2123: propeller,2980: automobile,2981: camera