Patent ID: 12191377

DETAILED DESCRIPTION

To provide a better understanding of the present invention to those of ordinary skill in the art, several exemplary embodiments of the present invention will be detailed as follows, with reference to the accompanying drawings using numbered elements to elaborate the contents and effects to be achieved. The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute a part of this specification. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention.

FIG.1is a flow chart of a method for forming a semiconductor structure according to an embodiment of the present invention.FIG.2toFIG.6are schematic cross-sectional views of a semiconductor structure at different manufacturing steps of the method shown inFIG.1.FIG.9is a schematic diagram illustrating the temperature versus time during the deposition process and the in-situ annealing process of the method shown inFIG.1.

Please refer toFIG.1,FIG.2andFIG.3. The method100begins at step101, wherein a substrate202is provided. The substrate202may include a silicon substrate, a silicon-on-insulator substrate (SOI), a silicon germanium (SiGe) substrate, or any other suitable substrates. A plurality of shallow trench isolation (STI) structures203may be formed in the substrate202to define the active regions. The shallow trench isolation structures203may include a dielectric material such as silicon oxide (SiOx) or silicon nitride (SiN), but is not limited thereto.

Subsequently, the method100proceeds to step102, wherein a gate structure212is formed on the substrate202. The gate structure212may be a dummy gate structure used to form a metal gate structure. The process to form the gate structure212may include forming a gate stacked layer on the substrate202and then performing a patterning process to remove unnecessary portions of the gate stacked layer, thereby forming the gate structure212. According to an embodiment of the present invention, the gate structure212may include, from bottom to top, an interfacial layer204, a high-k dielectric layer206, a polysilicon layer208, and a hard mask layer210. The material of the interfacial layer204may include silicon oxide (SiOx), silicon nitride (SiN), or silicon oxynitride (SiON), but is not limited thereto. The high-k dielectric layer206may include a dielectric material with a dielectric constant (k) larger than 4. For example, the high-k dielectric layer206may be selected from hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalate (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT), barium strontium titanate (BaxSr1-xTiO3, BST) or a combination thereof, but is not limited thereto. The material of the polysilicon layer208may include doped polysilicon or un-doped polysilicon. The material of the hard mask layer210may include silicon carbide (SiC), silicon oxynitride (SiON), silicon nitride (SiN), or silicon nitride carbide (SiCN), but is not limited thereto.

Please refer toFIG.1,FIG.4andFIG.9. The method100proceeds to step104, wherein a deposition process P1is performed to form a nitride layer214on the substrate202in a blanket manner and conformally covering the substrate202and the gate structure212. According to an embodiment of the present invention, the deposition process P1is a low pressure chemical vapor deposition (LPCVD) process, such as an atomic layer deposition (ALD) process, and may be performed by a low pressure furnace equipment. More specifically, as shown inFIG.9, after moving the substrate202into the process chamber of the low pressure furnace equipment, a heating step (from t1to t2) is carried out under a nitrogen (N2) atmosphere to raise the temperature from T1to T2. Following, the deposition process P1(from t2to t3) is performed at the temperature T2and uses nitrogen as the carrier gas to transport source gases such as dichlorosilane (DCS) and ammonia (NH3) into the process chamber to react to form the nitride layer214deposited on the substrate202and the gate structure212. According to an embodiment of the present invention, the temperature T1is between approximately the room temperature and 200° C. The temperature T2is between approximately 600 and 650° C. The process time of the deposition process P1(from t2to t3) may be adjusted according to the pre-determined deposited thickness A0of the nitride layer214and the flow rate of the source gases. According to an embodiment of the present invention, the thickness A0of the nitride layer214is between approximately 80 and 100 Å. The flow rate of dichlorosilane (DCS) is between approximately 1 and 3 slm. The flow rate of the ammonia (NH3) is between approximately 4 and 6 slm. The process time of the deposition process P1is between approximately 2 and 4 hours. According to an embodiment of the present invention, a liner (such as a silicon oxide layer) may be formed on the substrate202and the gate structure212before forming the nitride layer214. The liner may be formed by the low pressure furnace equipment for forming the nitride layer214, or may be formed by another deposition equipment. The liner (not shown) may serve as a buffer layer between the nitride layer214and the substrate202and the gate structure212, and may also serve to provide an etching end-point signal for the subsequent anisotropic etching process of forming the spacer.

Please refer toFIG.1,FIG.5andFIG.9. The method100proceeds to step106, wherein an in-situ anneal process P2is performed to anneal the nitride layer214. More specifically, as shown inFIG.9, after finishing the deposition process P1, another heating step (from t3to t4) is carried out under a nitrogen (N2) atmosphere to raise the temperature from T2to the T4. Subsequently, the temperature is kept at T4, and the nitride layer214undergoes the in-situ anneal process P2(from t4to t5) at the temperature T4under the nitrogen (N2). According to an embodiment of the present invention, the nitrogen (N2) flow rate during the in-situ anneal process P2is between approximately 20 and 40 slm. The temperature T4of the in-situ anneal process P2is higher than 700° C. For example, the temperature T4may be between approximately 700 and 800° C., or between approximately 750 and 770° C. The process time (the period between t4to t5) of the in-situ annealing process P2is between approximately 30 and 120 minutes, or between approximately 50 and 60 minutes. Following, after the in-situ anneal process P2, a cooling step (from t5to t6) is carried out under a nitrogen (N2) atmosphere to lower the temperature from T4to T3. The substrate202is then moved out from the process chamber of the low pressure furnace equipment. According to an embodiment of the present invention, the temperature T3is preferably lower than 700° C.

Please refer toFIG.1andFIG.6. The method100proceeds to step108, wherein an anisotropic etching process P3is performed to etch the nitride layer214to form a spacer214aon the sidewall of the gate structure212. According to an embodiment of the present invention, the anisotropic etching process P3is a reactive ion etching process. The anisotropic etching process P3uses at least one of CF4, CHF3, and CH2F2as the etching gas and may optionally use oxygen (O2) as assistant gas to etch the nitride layer214by single or multiple etchings stages to form the spacer214a. According to an embodiment of the present invention, the anisotropic etching process P3uses CH2F2, CHF3, and O2, wherein the flow rates of CH2F2and CHF3are between approximately 45 and 200 sccm, and the power is between approximately 300 and 400 watts.

When the lateral removal rate of the nitride layer214during the anisotropic etching process P3is too high, it is likely to cause the width (or the thickness) of the spacer214atoo small or form an undercut profile at the bottom portion of the spacer214a(the portion of the spacer214aon the sidewall of the interfacial layer204). This may also increase the risk that the etching gas may penetrate into the bottom portion of the gate structure212and damage the interface layer204and/or the high-k dielectric layer206. To overcome the problem, it is advantageous that the present invention performs the in-situ annealing process P2after the deposition process P1to anneal and densify the as-deposited nitride layer214under the nitrogen (N2) atmosphere. The in-situ annealed nitride layer214may produce a spacer214awith an extended bottom portion and a larger bottom width (thickness) after the anisotropic etching process P3, and the risk of damage to the interface layer204and/or the high-k dielectric layer206during the anisotropic etching process P3may be reduced. According to an embodiment of the present invention, as shown inFIG.6, the portion of the spacer214aon the sidewall of the interface layer204has a bottom width A1, and the portion of the spacer214aon the sidewall of the polysilicon layer208has a middle width A2. According to an embodiment of the present invention, the bottom width A1is approximately 1.1 times of the middle width A2.

Please refer toFIG.7andFIG.8, which are schematic cross-sectional views of a semiconductor structure at the manufacturing steps after the step shown inFIG.6according to an embodiment of the present invention. As shown inFIG.7, after forming the spacer214a, source/drain regions216may be formed in the substrate202at two sides of the gate structure212and adjacent to the spacer214a. In some embodiments, the source/drain regions216may be formed by ion implantation process to implant a suitable dosage of dopants with suitable conductivity types into the substrate202. In some embodiments, the source/drain regions216may be formed by etching the substrate202to form recesses at two sides of the gate structure212and epitaxially growing a semiconductor material to fill the recesses.

Subsequently, as shown inFIG.8, a contact etching stop layer218and an interlayer dielectric layer220are formed on the substrate202. A replacement metal gate process is then performed to remove the hard mask layer210and replace the polysilicon layer208with a work-function metal layer222and a low resistance metal layer224, thereby obtaining a metal gate structure226. The material of the contact etching stop layer218may include silicon nitride, silicon oxynitride, silicon carbide, or nitride doped silicon carbide, but is not limited thereto. The material of the interlayer dielectric layer220may include silicon oxide or a low-k dielectric material. The material of the work-function metal layer222is selected according to the conductivity type of the semiconductor structure. For example, when the semiconductor structure is to form a NMOS transistor, the work function metal layer222may have a work function ranging between 3.9 eV and 4.3 eV and may include titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), titanium aluminum carbide (TiAlC), or a combination thereof, but it is not limited thereto. When the semiconductor structure is to form a PMOS transistor, the work function metal layer222may have a work function ranging between 4.8 eV and 5.2 eV and may include titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), or a combination thereof, but it is not limited thereto. The material of the low resistance metal layer224may include copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP), or a combination thereof, but is not limited thereto. According to an embodiment of the present invention, a barrier layer (not shown) may be formed between the work function metal layer222and the high-k dielectric layer206and/or between the work function metal layer222and the low resistance metal layer224. The material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof, but is not limited thereto.

In summary, the present invention provides a method for forming a semiconductor structure that includes performing an in-suit annealing process to the as-deposited nitride layer in the deposition equipment to densify the nitride layer. The in-suit annealing process is performed successively after the deposition process without moving the substrate out from the deposition equipment. The densified nitride layer may have a lower lateral removal rate during a subsequent anisotropic etching process, thereby producing a spacer with an extended bottom portion and a larger bottom width (thickness). The risk of damaging the interfacial layer or high-k dielectric layer under the gate structure during the anisotropic etching process may be reduced.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.