Patent ID: 12260131

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.

DETAILED DESCRIPTION

In the following, reference is made to embodiments of the disclosure. However, it should be understood that the disclosure is not limited to specifically described embodiments. Instead, any combination of the following features and elements, whether related to different embodiments or not, is contemplated to implement and practice the disclosure. Furthermore, although embodiments of the disclosure may achieve advantages over other possible solutions and/or over the prior art, whether or not a particular advantage is achieved by a given embodiment is not limiting of the disclosure. Thus, the following aspects, features, embodiments, and advantages are merely illustrative and are not considered elements or limitations of the appended claims except where explicitly recited in a claim(s). Likewise, reference to “the disclosure” shall not be construed as a generalization of any inventive subject matter disclosed herein and shall not be considered to be an element or limitation of the appended claims except where explicitly recited in a claim(s).

Improved automation can be achieved using command-parts. Rather than using a command to determine which key to use, command partitioning will generate a task-ID based on a key index table to determine what key to use. Based on the task-ID, an encryption engine (XTS) will know which key to use. The command is split into partitions with the same attributes. The amount of task-IDs created will equal the amount of partitions. Automation will be based on the task-IDs to create a completion for a host. The controller will then return to the key index table to count the completed commands and send the completion to the host.

FIG.1is a schematic block diagram illustrating a storage system100having a data storage device106that may function as a storage device for a host device104, according to certain embodiments. For instance, the host device104may utilize a non-volatile memory (NVM)110included in data storage device106to store and retrieve data. The host device104comprises a host dynamic random access memory (DRAM)138. In some examples, the storage system100may include a plurality of storage devices, such as the data storage device106, which may operate as a storage array. For instance, the storage system100may include a plurality of data storage devices106configured as a redundant array of inexpensive/independent disks (RAID) that collectively function as a mass storage device for the host device104.

The host device104may store and/or retrieve data to and/or from one or more storage devices, such as the data storage device106. As illustrated inFIG.1, the host device104may communicate with the data storage device106via an interface114. The host device104may comprise any of a wide range of devices, including computer servers, network-attached storage (NAS) units, desktop computers, notebook (i.e., laptop) computers, tablet computers, set-top boxes, telephone handsets such as so-called “smart” phones, so-called “smart” pads, televisions, cameras, display devices, digital media players, video gaming consoles, video streaming device, or other devices capable of sending or receiving data from a data storage device.

The host DRAM138may optionally include a host memory buffer (HMB)150. The HMB150is a portion of the host DRAM138that is allocated to the data storage device106for exclusive use by a controller108of the data storage device106. For example, the controller108may store mapping data, buffered commands, logical to physical (L2P) tables, metadata, and the like in the HMB150. In other words, the HMB150may be used by the controller108to store data that would normally be stored in a volatile memory112, a buffer116, an internal memory of the controller108, such as static random access memory (SRAM), and the like. In examples where the data storage device106does not include a DRAM (i.e., optional DRAM118), the controller108may utilize the HMB150as the DRAM of the data storage device106.

The data storage device106includes the controller108, NVM110, a power supply111, volatile memory112, the interface114, a write buffer116, and an optional DRAM118. In some examples, the data storage device106may include additional components not shown inFIG.1for the sake of clarity. For example, the data storage device106may include a printed circuit board (PCB) to which components of the data storage device106are mechanically attached and which includes electrically conductive traces that electrically interconnect components of the data storage device106or the like. In some examples, the physical dimensions and connector configurations of the data storage device106may conform to one or more standard form factors. Some example standard form factors include, but are not limited to, 3.5″ data storage device (e.g., an HDD or SSD), 2.5″ data storage device, 1.8″ data storage device, peripheral component interconnect (PCI), PCI-extended (PCI-X), PCI Express (PCIe) (e.g., PCIe ×1, ×4, ×8, ×16, PCIe Mini Card, MiniPCI, etc.). In some examples, the data storage device106may be directly coupled (e.g., directly soldered or plugged into a connector) to a motherboard of the host device104.

Interface114may include one or both of a data bus for exchanging data with the host device104and a control bus for exchanging commands with the host device104. Interface114may operate in accordance with any suitable protocol. For example, the interface114may operate in accordance with one or more of the following protocols: advanced technology attachment (ATA) (e.g., serial-ATA (SATA) and parallel-ATA (PATA)), Fibre Channel Protocol (FCP), small computer system interface (SCSI), serially attached SCSI (SAS), PCI, and PCIe, non-volatile memory express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), or the like. Interface114(e.g., the data bus, the control bus, or both) is electrically connected to the controller108, providing an electrical connection between the host device104and the controller108, allowing data to be exchanged between the host device104and the controller108. In some examples, the electrical connection of interface114may also permit the data storage device106to receive power from the host device104. For example, as illustrated inFIG.1, the power supply111may receive power from the host device104via interface114.

The NVM110may include a plurality of memory devices or memory units. NVM110may be configured to store and/or retrieve data. For instance, a memory unit of NVM110may receive data and a message from controller108that instructs the memory unit to store the data. Similarly, the memory unit may receive a message from controller108that instructs the memory unit to retrieve data. In some examples, each of the memory units may be referred to as a die. In some examples, the NVM110may include a plurality of dies (i.e., a plurality of memory units). In some examples, each memory unit may be configured to store relatively large amounts of data (e.g., 128 MB, 256 MB, 512 MB, 1 GB, 2 GB, 4 GB, 8 GB, 16 GB, 32 GB, 64 GB, 128 GB, 256 GB, 512 GB, 1 TB, etc.).

In some examples, each memory unit may include any type of non-volatile memory devices, such as flash memory devices, phase-change memory (PCM) devices, resistive random-access memory (ReRAM) devices, magneto-resistive random-access memory (MRAM) devices, ferroelectric random-access memory (F-RAM), holographic memory devices, and any other type of non-volatile memory devices.

The NVM110may comprise a plurality of flash memory devices or memory units. NVM Flash memory devices may include NAND or NOR-based flash memory devices and may store data based on a charge contained in a floating gate of a transistor for each flash memory cell. In NVM flash memory devices, the flash memory device may be divided into a plurality of dies, where each die of the plurality of dies includes a plurality of physical or logical blocks, which may be further divided into a plurality of pages. Each block of the plurality of blocks within a particular memory device may include a plurality of NVM cells. Rows of NVM cells may be electrically connected using a word line to define a page of a plurality of pages. Respective cells in each of the plurality of pages may be electrically connected to respective bit lines. Furthermore, NVM flash memory devices may be 2D or 3D devices and may be single level cell (SLC), multi-level cell (MLC), triple level cell (TLC), or quad level cell (QLC). The controller108may write data to and read data from NVM flash memory devices at the page level and erase data from NVM flash memory devices at the block level.

The power supply111may provide power to one or more components of the data storage device106. When operating in a standard mode, the power supply111may provide power to one or more components using power provided by an external device, such as the host device104. For instance, the power supply111may provide power to the one or more components using power received from the host device104via interface114. In some examples, the power supply111may include one or more power storage components configured to provide power to the one or more components when operating in a shutdown mode, such as where power ceases to be received from the external device. In this way, the power supply111may function as an onboard backup power source. Some examples of the one or more power storage components include, but are not limited to, capacitors, super-capacitors, batteries, and the like. In some examples, the amount of power that may be stored by the one or more power storage components may be a function of the cost and/or the size (e.g., area/volume) of the one or more power storage components. In other words, as the amount of power stored by the one or more power storage components increases, the cost and/or the size of the one or more power storage components also increases.

The volatile memory112may be used by controller108to store information. Volatile memory112may include one or more volatile memory devices. In some examples, controller108may use volatile memory112as a cache. For instance, controller108may store cached information in volatile memory112until the cached information is written to the NVM110. As illustrated inFIG.1, volatile memory112may consume power received from the power supply111. Examples of volatile memory112include, but are not limited to, random-access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, and the like)). Likewise, the optional DRAM118may be utilized to store mapping data, buffered commands, logical to physical (L2P) tables, metadata, cached data, and the like in the optional DRAM118. In some examples, the data storage device106does not include the optional DRAM118, such that the data storage device106is DRAM-less. In other examples, the data storage device106includes the optional DRAM118.

Controller108may manage one or more operations of the data storage device106. For instance, controller108may manage the reading of data from and/or the writing of data to the NVM110. In some embodiments, when the data storage device106receives a write command from the host device104, the controller108may initiate a data storage command to store data to the NVM110and monitor the progress of the data storage command. Controller108may determine at least one operational characteristic of the storage system100and store at least one operational characteristic in the NVM110. In some embodiments, when the data storage device106receives a write command from the host device104, the controller108temporarily stores the data associated with the write command in the internal memory or write buffer116before sending the data to the NVM110.

The controller108may include an optional second volatile memory120. The optional second volatile memory120may be similar to the volatile memory112. For example, the optional second volatile memory120may be SRAM. The controller108may allocate a portion of the optional second volatile memory to the host device104as controller memory buffer (CMB)122. The CMB122may be accessed directly by the host device104. For example, rather than maintaining one or more submission queues in the host device104, the host device104may utilize the CMB122to store the one or more submission queues normally maintained in the host device104. In other words, the host device104may generate commands and store the generated commands, with or without the associated data, in the CMB122, where the controller108accesses the CMB122in order to retrieve the stored generated commands and/or associated data.

FIG.2shows example of a table200of a simple namespace (NS) and logical block address (LBA) to flat LBA (FLBA) range, according to an exemplary embodiment. In table200there are three NSs, with NS1 having a size of 1024 LBAs, NS2 having a size of 2048 LBAs, and NS3 having a size of 1024 LBAs. The FLBA is taking all the NSs and arranging NSs on one line. Thus, in the case ofFIG.2, the FLBA for NS1 is from 0-1023, the FLBA for NS2 is 1024-3071, and the FLBA for NS3 is 3072-4095. The table200thus has 4096 LBAs in total. As each NS has LBAs mapped from 0 onwards (0 to 1023 as example for NS1), a mapping of NS+LBA to FLBA needs to be done.

FIG.3shows example of a table300with split NS and LBA to FLBA ranges, according to an exemplary embodiment. Following the previous example ofFIG.2, the first NS1 is increased to 5120 LBAs, but the LBAs are not continuous. NS1 holds two entries which are non-consecutive where the FLBA comes in mind. This partitioning might look much more complicated as more NSs are deleted and re-created. For NS1, the size is 5120 LBAs with the first portion of NS1 having a size of 1024 LBAs and a FLBA of 0-1023 with a start at 0. The second portion of NS1 has a size of 4096 LBAs and a FLBA of 4096-8191 with a start at 1024. The second namespace NS2 hasn't changed fromFIG.2and thus has a size of 2048 LBAs and a FLBA of 1024-3071 with a start at 0. The third namespace, NS3, has a size of 1024 LBAs and a FLBA of 3072-4095 with a start at 0. Hence, the increase of NS1 occurs after the end of NS3 because NS2 and NS3 are already set, as is NS1, first portion. Thus, the increase of NS1 is added after NS3 and therefore begins at FLBA 4096 from the FLBA perspective. In terms of the start, because the second portion of NS1 is discontinuous with the first portion, the second portion must start after the first portion which would be at 1024.

FIG.4shows example of a table400of a simple NS/LBA pair to FLBA and NS/LBA pair to security-key-index with unaligned ranges, according to an exemplary embodiment. Just as each section has its own FLBA range in the device, so can different sections hold different security keys (used to encrypt/decrypt user data), and the sections are not always aligned.FIG.4shows a table400with a single NS with four portions. The first portion of NS1 has a size of 10 LBAs, a FLBA of 0-9, and starts at 0. The second portion of NS1 has a size of 10 LBAs, a FLBA of 40-49, and starts at 10. The third portion of NS1 has a size of 10 LBAs, a FLBA of 120-129, and starts at 20. The fourth portion of NS1 has a size of 10 LBAs, a FLBA of 140-149, and starts at 30. Hence, NS1 has 40 LBAs, and the FLBA is split into four separate sections on 10 LBAs each. For security reasons, the host device has divided NS1 into two ranges, 15 and 25 LBAs shown as NS1 first portion of LBA to security key index with a size of 15 LBAs and a key index of 1 and a start of 0, and NS1 second portion with a size of 25 LBAs and a key index of 4 with a start of 15. Due to unalignment between FLBA and key-index ranges there are 5 different combined ranges for (i.e., 1-5). Due to the arrangement of LBA to FLBA and the host arrangement, a read command of LBA 5 to LBA 16 will be split into three parts: LBA 5-LBA 9 with FLBA 5-9 and key 1; LBA10-LBA 14 with FLBA 40-44 and key 1; and LBA 15-LBA 16 with FLBA 45-45 and key 4.

FIG.5is a schematic block diagram illustrating a storage system500in which a controller506has command acceleration functionality, according to certain embodiments. The storage system500shows a host504, a NAND512, and a controller506. In this example a read command (moving data from NAND512to the host504) is used. The controller506shows two ranges which are a control path502and a data path508. A completion unit510is present between the control path502and data path508.

The data path508contains a flash interface module (FIM)524that brings data from the NAND512. The data path508further contains some error correction capabilities in an error correction module526and an XTS528which uses the security key. There is end-2-end protection with XTS528, which checks that nothing “went wrong” in bringing the correct data from NAND512using an FLBA. The data path508further contains a direct memory access module (DMA)530, which writes the data to the host504.

The control path502contains a command fetching unit514to read commands from the host504. A command parsing unit516to check if the command is legal, and to classify the command (read, write, administrative). The control path502further contains LBA to FLBA module518, and LBA to KEY module520as previously explained. The control path502further contains a FLBA to physical LBA (PLBA) module522(place in NAND) translation, using logical to physical (L2P) tables.

The completion unit510tracks the size of each command. While the command is parsed, the command size is stored in the completion unit510. When the data is transferred, the expected size is decreased, and when the size reaches zero, a completion is sent to the host504.

The data path508is built to meet bandwidth requirements. The control path502is built to meet key per input/output (KIPO) requirement. Each command will go through the LBA to FLBA module518and the LBA to KEY module520lookup tables. Once the control path502finishes parsing, the control path502triggers the data path508with the required information.

As discussed herein, using command parts for automation, instead of fully commands, is beneficial. The normal command will break into several sub parts if needed and each will also be associated with the original command to allow auto-completion based on the normal command and not based upon part of the command.

FIG.6is a schematic block diagram illustrating a storage system600in which a controller506has partitioning functionality, according to certain embodiments. Instead of using commands to tell the XTS528which key to use, task to task or part of a command can be used through partitioning. The controller506will have to generate task-IDs and the XTS528will know what key index to use based on the task-ID.FIG.6is similar toFIG.5, but there are two changes. The first change is in the control path502where a partition logic unit602is added. In the completion unit510(i.e., command length database), a mapping table604is present between the part index and command index.

FIG.7is a flow chart illustrating a method700for partitioning, according to certain embodiments. The method700works per command. First the controller, such as the controller506ofFIG.6, looks for section table and security range table entries that match the LBA of the command. The controller then extracts the FLBA and security keys in accordance with the command. The controller checks how much of the command the section table and the security table covers. When at most either of the tables can cover the entire command or the size of the command that fits into the relevant entry. The section table's effective size (FLBA_LEN) and the security table's range effective size (KEY_LEN) are then compared. The overall effective size (LEN) is the minimum between both. Then an un-used task-id is allocated, and the part-mapping logic (inside the completion database) is updated. The method700continues by dispatching the part of the command to the data-path engine such as the data path508ofFIG.6for execution. If the part is the last (and possibly the only) part, the flow ends. Otherwise, the original command is manipulated to look smaller (without the dispatched part), and what remains is queued all over as a new command.

The partition algorithm updates the part-mapping block, such as the part-mapping532ofFIG.6, to associate the part-mapping block with a command length. Therefore, when the DMA, such as the DMA530ofFIG.6, sends ‘X’ flash memory unit (FMU) for task-ID there will be a request for the part-mapping to decrease the task-id length (as done with the command-ID before the suggested change, meaning no change in the flow for the DMA). The completion will decrease both the task-ID and the associated command-ID length by ‘X’. If the task-ID length reaches zero, the task-ID is released back to the partitioning part for re-use. If the command-ID length reaches zero, the DMA is updated so auto-completion might be sent to the host.

The method700begins at block702. At block702, a command arrives to the controller, such as the controller forFIG.6. The blocks (704-708) in the section table are completed in parallel with the blocks (710-714) in the security range table. At block704, the controller finds the section matching the NS+LBA. At block,706, the controller calculates the FLBA=section-flat-Iba+command-Iba−section-start. At block708, the controller calculates the FLBA_LEN=min (command-length, section-end−FLBA+1).

At block710, the controllers finds the entry matching the commands NS+LBA. At block712, the controller calculates the KEY=key index provided in the entry. At block714, the controller calculates KEY_LEN=min (command-length, entry-end−command-Iba+1).

At the completion of both block708and block714, the method700with proceed to block716. At block716, LEN=min (FLBA_LEN, KEY_LEN) is determined. Part-mapping contains block718and block720. At block718, the controller allocates an unused part-id. At block720, the controller associates the part-id with the command-id in the part-mapping table. At block722, the controller dispatches the task (task_id, FLBA, LEN, and KEY). At block724, the controller determines whether LEN=command-length. If the controller determines LEN=command-length then the last part is completed of the method700. If the controller determines LEN is not=command-length then portioning continues and the method700proceeds to block726. Part-mapping contains block726, block728, and block730. At block726, the controller updates the command-length=command-length−LEN. At block728, the controller updates the command-Iba=command-Iba+LEN. At block730, the controller queues as a new command.

By splitting a command into multiple sub-parts, and associating each part with the original command, the data path and control path automation can be kept even for split-range commands at full bandwidth. In so doing, performance can be maintained through multi-range commands in enterprise applications.

In one embodiment, a data storage device comprises: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: receive a read command to read data from the memory device; obtain a flat logical block address (FLBA) and a security key for the read command; split the read command into a first part and a second part; allocate a part identification (ID) to the first part and the second part; process the first part; process the second part; and report completion of the read command to a host device after processing the first part and the second part. The security key comprises a first security key and a second security key and wherein the first security key might be different from the second security key. The FLBA includes a discontinuous range. The FLBA, the security key, and the read command are associated with a single namespace (NS). The controller is configured to queue the first part and second part as separate commands for execution. The splitting occurs in a data path. The controller is further configured to associate the first part and the second part with the read command.

In another embodiment, a data storage device comprises: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: receive a read command to read data from the memory device; search a section table to find a section matching a logical block address (LBA) and namespace (NS) of the read command; calculate a flat LBA (FLBA) for the read command; search a security table to find an entry matching the LBA and NS of the read command; calculate a key for the read command; split the command into a first portion and a second portion; allocate a part identification (ID) to the first portion; execute the first portion; and queue the second portion for execution. Searching the section table occurs in parallel with searching the security table. The FLBA is equal to a section FLBA plus a command LBA minus a section start. The controller is further configured to calculate a key length for the calculated key, wherein the calculated key length equals an entry end minus a command LBA plus 1. The controller is further configured to associate the part ID with a command ID in a part mapping table. The controller is further configured to determine whether the first portion is a last portion of the read command. The controller is further configured to update a command length to equal the command length minus a length of the first portion to generate the second portion. The controller is configured to update a command LBA to equal the command LBA plus the length of the first portion as part of generating the second portion. The controller is configured to queue the second portion as a new command where a repetitive process might yield a third (or more portions) portion, until the third (or more portion) portion is the last portion of the read command. The controller includes a completion database having a mapping table associating a part index of part IDs and command index of command IDs.

In another embodiment, a data storage device comprises: means to store data; and a controller coupled to the means for storing data, wherein the controller is configured to: receive a read command to read data from the means for storing data; partition the read command into a first part and a second part, wherein the partitioning is based upon flat logical block address (FLBA) and a security key; associate a first part identification (ID) with the first part and a second part ID with the second part; execute the first part; execute the second part; and report completion of the command after executing both the first part and the second part. The first part has a first security key and the second part has a second security key that might be different from the first security key. The first part has a first FLBA and the second part has a second FLBA and wherein the second FLBA and the first FLBA are not necessarily continuous.

While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.