Patent ID: 12260917

In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.

DETAILED DESCRIPTION

FIG.1Ais a block diagram of the storage device10A for generating an identity code102according to the first embodiment of the present disclosure. Referring toFIG.1A, the storage device10A of the first embodiment includes a first storage circuit20, a second storage circuit30and a reading circuit40. In the storage device10A of the first embodiment, the first storage circuit20and the second storage circuit30are storage circuits which are physically separated from each other. The reading circuit40may be configured to read data from the first storage circuit20and the second storage circuit30respectively, and process these data to generate an identify code102.

More particularly,FIG.1Bare circuit diagrams of the memory array21of the first storage circuit20and the memory array31of the second storage circuit30according to the first embodiment of the present disclosure. Referring toFIG.1B, the memory array21of the first storage circuit20may refer to, for example, a random access memory (RAM) array of the type of one transistor and two resistors (1T2R, 1Transistor+2Re). The resistors Ra and Rb may determine the voltage of the gate of the transistor and may thus determine logic value as “1” or “0” stored in memory cells of the memory array21.

On the other hand, the memory array31of the second storage circuit30refers to a programmable memory array. The logic values stored in memory cells of the memory array31can be programmed according to user's definition. The memory array31of the second storage circuit30may refer to a RAM array of a type of one transistor and one resistor (1T1R, 1Transistor+1Re).

Memory types of the first storage circuit20and the second storage circuit30may also include static random access memory (SRAM) or read-only memory (ROM), such as mask ROM, fuse ROM, and anti-fuse ROM. Or, may include high precision NVM, charge storage memory, floating gate memory (FG), charge trapping memory, Silicon-Oxide-Nitride-Oxide-Silicon memory (SONOS), variable resistive memory (ReRAM), phase change memory (PCM), magnetic resistive random access memory (MRAM), ferroelectric tunneling memory (FTJ) and Ferroelectric random access memory (FeRAM), etc.

FIGS.1C and1Dare schematic diagrams illustrating the operation of the storage device10A to generate an identity code102according to the first embodiment of the present disclosure, andFIG.7is a flowchart of the identity code generating method700according to the first embodiment of the present disclosure. First, referring toFIG.1C(accompanied withFIG.1A), the first storage circuit20may be configured to store a plurality of first data104. The first data104may include, for example, sixteen bits {1, 0, 1, 1, 0, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1}, which are binary logic values. The first data104may be stored in sixteen (4×4) memory cells of the memory array21of the first storage circuit20sequentially and in order. The first data104may serve as “information”, that is, the first data104may serve as contents of the subsequently generated identity code102. However, in the technical solutions of the present disclosure, the sixteen bits {1, 0, 1, 1, 0, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1} of the original first data104may not form the final identity code102yet. After selecting bits of a first portion of the first data104by the second data106, the selected bits of the first data104can serve as the final identity code102.

In contrast to the usage of the first data104as “information”, the second data106may serve as “address”. According to the address provided by the second data106, the first portion of the first data104may be selected to form the final identity code102. In the first storage device10A of the first embodiment, the first data104may be stored in the first storage circuit20, while the second data106may be stored in the second storage circuit30. In other words, the first data104and the second data106are stored in different storage circuits, physically. The quantity of the second data106may be equal to that of the first data104. The second data106may also include sixteen bits of binary logic values. The sixteen bits of the second data106may be {1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0}. Similarly, the second data106may be sequentially stored in 4×4 memory cells of the memory array31of the second storage circuit30, in order. The sixteen bits of the second data106may correspond to the sixteen bits of the first data104in a manner of one-to-one correspondence. Logic “1” bits of the second data106may correspond to selected bits of the first data104. On the other hand, the bits of the first data104, which correspond to logic “0” bits of the second data106, are not selected. The selected portion of the first data104may refer to “first portion”, and the un-selected portion of the first data104may refer to “second portion”.

In the operation of the storage device10A of the first embodiment, the reading circuit40may read the second data106from the second storage circuit30. The read-out second data106may form a first sequence A. The first sequence A may be expressed as {1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0}, and bits of logic value “1” in the first sequence A may serve as selecting addresses. Also referring toFIG.7, the above-mentioned operation of the storage device10A may correspond to the step706of the identity code generating method700of the first embodiment: reading the second data106from the second storage circuit30to form the first sequence A.

Next, bits of the first portion of the first data104may be selected according to the bits of logic value “1” of the first sequence A. On the other hand, bits of the second portion of the first data104, which correspond to addressed of bits of logic value “0” of the first sequence A, may be discarded and not selected. For example, bits of logic value “1” of the first sequence A are bits a1, a4, a6, a11, a13and a14. Furthermore, bits b1, b4, b6, b11, b13and b14of the first portion of the first data104are selected, which correspond to address of the bits a1, a4, a6, a11, a13and a14of the first sequence A. Also referring toFIG.7, the above-mentioned operation of the storage device10A may correspond to the step708of the identity code generating method700: selecting bits of the first portion of the first data104according to address of the bits of logic value “1” of the first sequence A.

Next, the reading circuit40may read bits b1, b4, b6, b11, b13and b14of the first portion of the first data104from the first storage circuit20to form a target sequence P. The target sequence P may be expressed as {1, 1, 0, 1, 0, 1}, and the target sequence P may serve as the final identity code102. Also referring toFIG.7, the above-mentioned operation of the storage device10A may correspond to the step710of the identity code generating method700: reading bits of the first portion of the first data104from the first storage circuit20to form the target sequence P, and correspond to the step712: outputting the target sequence P to serve as the final identity code102.

In contrast to bits b1, b4, b6, b11, b13and b14of the selected first portion of the first data104, on the other hand, the other bits b2, b3, b5, b7, b8, b9, b10, b12, b15, b16of the second portion of the first data104may be discarded and not selected.

For the storage device10A of the first embodiment, logic value stored in the second storage circuit30may be programed by user in advance, so as to pre-define bits of logic value “1” in the second data106. In other words, the user may pre-define address to select which bits of the first data104and take these selected bits as the final identity code102.

Variations may appear in the physical characteristics of the hardware components of the first storage circuit20. For example, if the hardware components of the first storage circuit20are static random access memory, variations due to mismatch between NMOS transistors and PMOS transistors. If the hardware component of the first storage circuit20is a non-volatile memory (e.g., variable resistance memory, phase change memory or floating gate memory), the programming state of the memory is unpredictable. Based on the variations of the hardware components of the first storage circuit20, logical value of each bit of the first data104stored in the first storage circuit20is randomly distributed, therefore the logical value of each bit of the first data104will not be the same as that of another storage device. Hence, the target sequence P={1, 1, 0, 1, 0, 1} obtained by selecting the first portion of the first data104may achieve uniqueness and can serve as the identity code. The identity code102may be also expressed as {1, 1, 0, 1, 0, 1}.

In an example of another aspect, referring toFIG.1D, the hardware component of the first storage circuit20may have defects (e.g., variations in component parameters caused by change of temperature) and hence some bits of the first data104may be error bits or insufficient margin bits. For example, memory cells in address (1,3), (2,1), (3,3) and (4,4) of the memory array21of the first storage circuit20may have defects, that result in error bits “x” of the first data104stored in address (1,3), (2,1), (3,3) and (4,4) of the memory array21. In the technical solution of the present disclosure, the first portion of the first data104is selected as the final identity code102according to the address provided by the second data106, and the second portion of the first data104is discarded and not selected. The error bits “X” of the first data104correspond to address (1,3), (2,1) and (4,4) of memory array31of the second storage circuit30, and bits of the second data106stored in address (1,3), (2,1) and (4,4) of memory array31all have logic value “0”. Therefore, the error bits “x” of the first data104belong to the second portion and will be discarded and not selected, the error bits “x” of the first data104will not affect the target sequence {1, 1, 0, 1, 0, 1} and the final identity code102. In other words, address provided by the second data106can filter out the error bits “x” in the first data104, hence the generating mechanism of identity code102of the present disclosure may have error tolerance to tolerate error bits “x” in the first data104.

FIGS.2A and2Bare schematic diagrams of characteristic analysis of an identity code102generated in a simulation according to the first embodiment of the present disclosure. The amount of the first data104stored in the first storage circuit20may include five hundred bits (which can be expressed as 500 bits/chip). The second data106stored in the second storage circuit30may include one hundred bits with logical value “1” (which can be expressed as 100 bits/chip). Therefore, through the address provided by the second data106, one hundred bits can be selected from the five hundred bits of the first data104to form the target sequence P and serve as the final identity code102.

As shown inFIG.2A, the intra Hamming-distance (intra-HD) can show correlation between the five hundred bits of the first data104, and the correlation coefficient μ is 11.62%. As shown inFIG.2B, the correlation coefficient μ between the one hundred bits of the first data104selected through the address of the second data106(which forms the identity code102by the target sequence P) may be greatly reduced to 0.53%. The above simulation results show that, randomness of each the bits of the target sequence P may be increased through selection by the address provided by the second data106, and uniqueness of the identity code102may thus be ensured.

On the other hand, as shown inFIG.2A, the inter Hamming distance (inter-HD) can show the correlation between the logical value of each bit of the first data104stored in the first storage circuit20and other storage devices, wherein the correlation coefficient μ is 49.88%. As shown inFIG.2B, after one hundred bits of the first data104are selected through the address of the second data106, the correlation coefficient μ of the inter HD is 50.01%, which can still be maintained at a value of nearly 50%.

In the simulation settings related toFIGS.2A and2B, one hundred bits from the five hundred bits of the first data104are selected as the identity code102, and the selection ratio is one-fifth. In examples of other aspects, different selection ratios can be adopted, such as one-tenth or one-twentieth. The lower the selection ratio, the more error bits in the first data104can be filtered out, and the higher error tolerance may be achieved.

FIG.3is a block diagram of the storage device10B for generating an identity code102according to the second embodiment of the present disclosure. Referring toFIG.3, the storage device10B of the second embodiment includes a first storage circuit20and a reading circuit40. In the second embodiment, the storage device10B may include only one physical storage circuit (the first storage circuit20), and the first storage circuit20simultaneously stores the first data104and the second data106. The first storage circuit20may be divided into a first storage region201and a second storage region202to store the first data104and the second data106respectively.

FIG.4Ais a block diagram of the storage device10C for generating an identity code102according to the third embodiment of the present disclosure, andFIG.4Bis a schematic diagram illustrating the operation of the storage device10C to generate an identity code102according to the third embodiment of the present disclosure. Furthermore,FIG.8is a flowchart of the identity code generating method800according to the third embodiment of the present disclosure. First, referring toFIG.4A, the storage device10C of the third embodiment may be different from the storage device10A of first embodiment in that, the reading circuit40of the third embodiment reads the first data104from the first storage circuit20and simultaneously reads the second data106from second storage circuit30in a parallel manner.

Moreover, the reading circuit40of the third embodiment further includes a processing circuit41. The first data104and second data106may be simultaneously transmitted to the processing circuit41for performing calculation.

Next, referring toFIG.4B, in the operation of the storage device10C of the third embodiment, the reading circuit40reads the second data106from the second storage circuit30to form the first sequence A and simultaneously reads the first data104from the first storage circuit20to form the second sequence B. The first sequence A may be expressed as {1, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 1, 1, 0, 0}, and the second sequence B may be expressed as {1, 0, 1, 1, 0, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1}. Also referring toFIG.8, the above-mentioned operations of storage device10C correspond to step802of the identity code generating method800of the third embodiment: reading the second data106from the second storage circuit30, and reading the first data104from the first storage circuit20simultaneously. The second data forms the first sequence A, and the first data104forms the second sequence B.

Next, the first sequence A and the second sequence B are simultaneously transmitted to the processing circuit41to execute computation. This operation corresponds to the step804of the identity code generating method800: transmitting the first sequence A and the second sequence B to the processing circuit41simultaneously.

In the processing circuit41, bits of the first portion of the second sequence B are selected according to address of bits of logic value “1” of the first sequence A. On the other hand, bits of the second portion of the second sequence B correspond to bits of logic value “0” of the first sequence A, therefore the processing circuit41discards and not select bits of the second portion of the sequence B. As shown inFIG.4B, the processing circuit41selects bits b1,b4,b6,b11,b13and b14of the first portion of the second sequence B which correspond to bits a1,a4,a6,a11,a13and a14of logic value “1” of the first sequence A. Furthermore, the processing circuit40masks bits of the second portion of the second sequence B, these bits are not selected. Also referring toFIG.8, such operation corresponds to step806of identity code generating method800: selecting bits of the first portion of the second sequence B according to address of bits of logic value “1” of the first sequence A.

Next, the processing circuit41outputs the selected bits b1,b4,b6,b11,b13and b14of the first portion of the second sequence B to form the target sequence P. The target sequence P may be expressed as {1, 1, 0, 1, 0, 1} to serve as the final identity code102. This operation corresponds to step808of identity code generating method800: outputting selected bits b1, b4, b6, b11, b13and b14of the first portion of the second sequence B to form the target sequence P, which serves as the final identity code102.

As mentioned above, the operation of the storage device10cof the third embodiment (corresponding to the identity code generating method800of the third embodiment) is different from the operation of the storage device10A of the first embodiment (corresponding to the identity code generating method700of the first embodiment) in that: in the identity code generating method700of the first embodiment, the second data106is read from the second storage circuit30to form the first sequence A, thereafter, bits of the first portion of the first data104are selected according to address of bits of logic value “1” of the first sequence A. Then, selected bits of the first portion of the first data104are read from the first storage device20, which serves as the final identity code102. Unlike the first embodiment, in the identity code generating method800of the third embodiment, the second data106and the first data104are simultaneously read from the second storage circuit30and the first storage circuit20, which form the first sequence A and the second sequence B. Thereafter, the first portion of the second sequence B is selected to be the final identity code102.

FIGS.4C and4Dare circuit diagrams of two examples of different aspects of processing circuits41A and41B of the storage device10C according to the third embodiment of the present disclosure. The processing circuit41A and processing circuit41B may be logic circuits composed of logic gates, such as latches or flip-flops. The processing circuit41A and processing circuit41B may be configured to select bits “b” of the second sequence B by the bits “a” and their complements “a′” of the first sequence A, and then forms bits “p” of the target sequence P.

FIG.5is a schematic diagram illustrating the operation of the storage device to generate an identity code102according to the fourth embodiment of the present disclosure. Referring toFIG.5, the storage device of the fourth embodiment is different from the storage device of the first embodiment in that, logic value of each bit of the second data106of the first embodiment is defined and programmed by the user in advance. On the other hand, logic value of each bit of the second data106of the fourth embodiment is randomly distributed, which is not defined by the user. In other words, the logic values of the bits of the first data104and the second data106in the fourth embodiment are randomly distributed. Using the randomly distributed address provided by the second data106to select the randomly distributed information of the first data104, the randomness is increased to two dimensions for the fourth embodiment, which can ensure uniqueness of the identity code102formed by the selected bits of the first portion of the first data104. For example, the first sequence A, which is read from the randomly distributed second data106. is {0, 1, 0, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0}. Furthermore, the selected first portion from the first data104according to the address provided by the first sequence A may form the target sequence P={0, 1, 0, 0, 1, 0, 0, 0} to obtain the final identity code102. In operation, in step702ofFIG.7, firstly, it is determined whether the logical value of each bit of the second data106should be programmed and defined by the user. If not, the second storage circuit30directly generates random logic value of each bit of the second data106in a random manner according to the physical characteristics of the second storage circuit30, which may not need to program each bit of the second data106. Therefore, step704can be skipped, and step706can be executed directly to read the randomly distributed second data106from the second storage circuit30directly, forming the first sequence A.

FIG.6is a schematic diagram illustrating the operation of the storage device to generate an identity code102according to the fifth embodiment of the present disclosure. Referring toFIG.6, in the fifth embodiment, the user may re-program the second data106during the process so as to re-define the logic value of each bit of the second data106, thereby re-defining the address provided by the first sequence A. Hence, other bits of the first data104may be re-selected as a new target sequence P to generate a new identity code102. In other words, in the fifth embodiment, the identity code102may be changed again during process. In operation, in step714ofFIG.7, it is determined whether the user needs to re-program the second data106. If yes, executing step704to program the logic value of each bit of the second data106. Next, in step706, the re-defined and re-programmed second data106is read to form a new first sequence A={0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 1, 0, 1, 0, 0}. Next, in step708, re-selecting five bits b6, b7, b10, b12and b14from the first data104according to the new first sequence A so as to obtain a new target sequence P={0, 0, 0, 0, 1} to form a updated identity code102.

According to the technical solutions of the above-mentioned embodiments of the present disclosure, the first portion of the first data104is selected with the aid of the address provided by the first sequence A formed by the second data106, so as to generate the final identity code102. In addition, the second portion of the first data104is discarded, so that error bits in the second portion of the first data104may be tolerated, and hence uniqueness of the final identity code102may be further ensured. The first sequence A formed by the second data106can be pre-defined by the user or randomly distributed, and furthermore, the second sequence can also be re-programmed and re-defined by the user during process, so that coding mechanism of the identity code102may be more flexible, and uniqueness of the identity code102may be ensured. The above refers to technical effects achieved by the technical solution of the present disclosure.

It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.