Patent ID: 12205634

DETAILED DESCRIPTION

For a SRAM device, in a read or dummy read operation with bit line and bit line bar initially pre-charged high, when a word line rises, there will be a voltage bump on the storage node in the SRAM bit-cell which should maintain “0” during the read or dummy read operation. Once the voltage bump is higher than the latch trigger point, the internal state of the SRAM bit-cell will be flipped. This condition is referred to as a read disturbance.

Static direct current-resistant designs for semiconductor devices may be applied to suppress voltage bumps in word lines. However, such designs may cause over/bander voltage drops. The designs are inefficient and may induce further performance impairment, such as speed degradation, higher power consumption, and reduced process variation adaptability for the SRAM.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact in addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity, and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “upper,” “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, although terms such as “first,” “second” and “third” describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may only be used to distinguish one element, component, region, layer or section from another. Terms such as “first,” “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in the respective testing measurements. Also, as used herein, the terms “substantially,” “approximately” and “about” generally mean within a value or range that can be contemplated by people having ordinary skill in the art. Alternatively, the terms “substantially,” “approximately” and “about” mean within an acceptable standard error of the mean when considered by one of ordinary skill in the art. People having ordinary skill in the art can understand that the acceptable standard error may vary according to different technologies. Other than in the operating/working examples, or unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages such as those for quantities of materials, durations of times, temperatures, operating conditions, ratios of amounts, and the likes thereof disclosed herein should be understood as modified in all instances by the terms “substantially,” “approximately” or “about.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that can vary as desired. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges can be expressed herein as from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise.

FIG.1illustrates a schematic diagram of an exemplary electronic device1, in accordance with some embodiments of the present disclosure. The electronic device1comprises a word line11, a driver circuit12, a suppression circuit13, a control circuit14, and a SRAM device15. The driver circuit12is configured to provide drive voltage to the word line11of the electronic device1. The suppression circuit13is electrically connected to the driver circuit12and the word line11. The suppression circuit13is configured to generate a voltage drop in the drive voltage of the word line11. The control circuit14is electrically connected to the suppression circuit13. The control circuit14controls the suppression circuit13. The word line11controlled by the suppression circuit13is electrically connected to the SRAM device15.

FIG.2illustrates a schematic diagram of an exemplary SRAM bit-cell20, in accordance with some embodiments of the present disclosure.

The SRAM bit-cell20is a cell of the SRAM device15. The SRAM bit-cell20comprises a word line21, a bit line22, a bit line bar22′, and six transistors. The transistor of the SRAM bit-cell20may be metal-oxide-semiconductor field-effect transistors (MOSFET). In some embodiments, the SRAM bit-cell20comprises two p-type MOSFETs (PMOS)23and25and four n-type MOSFETs (NMOS)24,26,27and28. The gate electrode23G of the PMOS23is electrically connected to the gate electrode24G of the NMOS24. The drain electrode23D of the PMOS23is electrically connected to the drain electrode241of the NMOS24, The source electrode23S of the PMOS23is electrically connected to a power source29(e.g., VDD). The source electrode24S of the NMOS24is electrically connected to the ground. The PMOS23and NMOS24form an inverter.

The gate electrode25G of the PMOS25is electrically connected to the gate electrode26G of the NMOS26. The drain electrode25D of the PMOS25is electrically connected to the drain electrode26D of the NMOS26. The source electrode25S of the PMOS25is electrically connected to the power source29(e.g., VDD). The source electrode26S of the NMOS26is electrically connected to the ground. The PMOS25and NMOS26form an inverter.

The gate electrode27G of the NMOS27is electrically connected to the word line21. The drain electrode27D of the NMOS27is electrically connected to the bit line bar22′. The source electrode27S of the NMOS27is electrically connected to the drain electrode23D of the PMOS23and the drain electrode24D of the NMOS24. The source electrode27S of the NMOS27is electrically connected to the inverter formed by the PMOS23and the NMOS24. The gate electrode28G of the NMOS28is electrically connected to the word line21. The drain electrode28D of the NMOS28is electrically connected to the bit line22. The source electrode28S of the NMOS28is electrically connected to the drain electrode25D of the PMOS25and the drain electrode26D of the NMOS26. The source electrode28S of the NMOS28is electrically connected to the inverter formed by the PMOS25and the NMOS26.

A node QB electrically connects the drain electrode23D of the PMOS23and the drain electrode24D of the NMOS24. The node QB is also electrically connected to the gate electrode25G of the PMOS25and the gate electrode26G of the NMOS26. A node Q electrically connects the drain electrode25D of the PMOS25and the drain electrode26D of the NMOS26. The node Q is also electrically connected to the gate electrode23G of the PMOS23and the gate electrode24G of the NMOS24.

The SRAM bit-cell20has states of standby (the circuit is idle), reading (the data has been requested), or writing (updating the contents). The SRAM bit-cell20operated in read mode should have readability. The SRAM bit-cell20operated in the write mode should have write stability.

When the SRAM bit-cell20is in standby mode, the word line21is set to low. The two cross-coupled inverters formed by the POMS23and NMOS24and the POMS25and NMOS26are disconnected from the bit line22and the bit line bar22′ by the NMOS27and28. The data stored in the nodes Q and QB are kept.

When the data stored in the SRAM bit-cell20is “1,” the data stored in the node Q is “1” and the data stored in the node QB is “0.” When the SRAM bit-cell20is in read mode, the bit line22and bit line bar22′ are set to a “high” logic state (i.e., data “1”). Afterwards, the word line21is set to a “high” logic state, such that the NMOS27and28are enabled. Because the data stored in the node Q is the same as the initial value of the bit line22, the data stored in the node Q is maintained at “1”. Because the data stored in the node Q is “1,” the NMOS24is enabled and the PMOS23is disabled. This causes the data stored in the node QB to be “0.” Since the NMOS24and the NMOS27are enabled, the bit line bar22′ is electrically connected to the ground, and thus has a data “0.” Furthermore, because the data stored in the node QB is “0,” the PMOS25is enabled and the NMOS26is disabled. This causes the data stored in the node Q to be “1.” Since the PMOS25and the NMOS28are enabled, the bit line22is connected to the power source29, and thus has a data “1”.

If the data stored in the SRAM bit-cell20is “0,” the data stored in the node Q is “0” and the data stored in the node QB is “1.” When the SRAM bit-cell20is in read mode, the bit line22and bit line bar22′ are set to a “high” logic state (i.e., data “1”). Afterwards, the word line21is set to a “high” logic state, such that the NMOS27and28are enabled. Because the data stored in the node QB is the same as the initial value of the bit line bar22′, the data stored in the node QB is maintained at 1. Because the data stored in the node QB is “1,” the PMOS25is disabled and the NMOS26is enabled. This makes the data stored in the node Q “0.” Since the NMOS26and the NMOS28are enabled, the bit line22is electrically connected to the ground, and thus has data “0.” Furthermore, because the data stored in the node Q is “0,” the PMOS23is enabled and the NMOS24is disabled. This causes the data stored in the node QB to be “1.” Since the PMOS23and the NMOS27are enabled, the bit line bar22′ is connected to the power source29, and thus has a data “1.”

In some embodiments, the SRAM bit-cell20may comprise more than six transistors. In some embodiments, the SRAM bit-cell20may comprise eight transistors. In some embodiments, the SRAM bit-cell20may comprise ten transistors.

FIG.3illustrates a schematic diagram of an exemplary electronic circuit, in accordance with some embodiments of the present disclosure.FIG.3shows the driver circuit12, the suppression circuit13, and the control circuit14.

The suppression circuit13comprises a transistor. The transistor of the suppression circuit13may be a metal-oxide-semiconductor field-effect transistor (MOSFET). The suppression circuit13may comprise a p-type transistor or a p-type MOSFET (PMOS)31. The control circuit14comprises a p-type transistor or a p-type MOSFET (PMOS)32and an n-type transistor or a n-type MOSFET (NMOS)33.

In some embodiments, the transistor of the suppression circuit13may be a n-type transistor, the upper transistor of the control circuit14may be an n-type transistor, and the lower transistor of the control circuit14may be a p-type transistor.

The control circuit14is electrically connected to the suppression circuit13. The control circuit14controls the suppression circuit13to generate the voltage drop in the drive voltage of the word line11. The source electrode31S of the PMOS31is electrically connected to the word line11and the word line driver12. The drain electrode31D of the PMOS31is electrically connected to the ground. The gate electrode31G of the PMOS31is electrically connected to the control circuit14. The gate electrode31G of the PMOS31is electrically connected to the drain electrode32D of the PMOS32and the drain electrode33D of the NMOS33. The source electrode32S of the PMOS32is electrically connected to a power source. The source electrode33S of the NMOS33is electrically connected to the ground.

The PMOS31of the suppression circuit13may generate a voltage drop in the drive voltage of the word line11. The size of the voltage drop is determined by control voltage applied to the gate electrode31G of the PMOS31of the suppression circuit13. The suppression circuit13adjusts the drive voltage of the word line11. In some embodiments, the suppression circuit13decreases the drive voltage of the word line11based on the control voltage. In some embodiments, the control voltage applied to the gate electrode31G of the PMOS31is determined based on a voltage difference caused by the PMOS32and a voltage difference caused by the NMOS33. In some embodiments, the control circuit14is turned on based on the signal applied to the gate electrode32G of the PMOS32. In some embodiments, the control circuit14is turned on based on the signal applied to the gate electrode33G of the NMOS33. In some embodiments, the control circuit14is turned on based on one or more signals applied to at least one of the gate electrode32G of the PMOS32or the gate electrode33G of the NMOS33. In some embodiments, the one or more signals comprise pulse signals.

The behavior of a MOSFET operated in a linear region is similar to a voltage-controlled resistor. For a PMOS operated in the linear region, if the gate voltage applied thereto is lower, the equivalent resistance of the PMOS may be correspondingly lower, and the drain current of the PMOS increased under a given voltage between the drain and the source. The equivalent resistance of a PMOS operated in the linear region may be inversely proportional to its carrier mobility. For example, if a PMOS used for the suppression circuit13generates a higher drain current, a larger voltage drop in the voltage of the word line may be caused. For a NMOS operated in a linear region, if the gate voltage applied thereto is higher, the equivalent resistance of the NMOS may be correspondingly lower, and the drain current of the NMOS increased under a given voltage between the drain and the source. The equivalent resistance of a NMOS operated in the linear region may be inversely proportional to its carrier mobility. For example, if a NMOS used for the suppression circuit13generates a higher drain current, a larger voltage drop in the voltage of the word line may be caused.

In some embodiments, if the NMOS33is weaker and the PMOS32is stronger (i.e., slow NMOS fast PMOS (SF) corner), the carrier mobility of the NMOS33may be lower and the carrier mobility of the PMOS32may be higher. If the NMOS33is weaker and the PMOS32is stronger (i.e., slow NMOS fast PMOS (SF) corner), the voltage difference generated by the PMOS32itself may be less. This may increase the voltage applied to the gate electrode31G of the PMOS31. When the voltage applied to the gate electrode31G of the PMOS31increase, the equivalent resistance of the PMOS31(e.g., operated in linear region) may increase, and the drain current of the PMOS31lowered. Accordingly, less drop in the voltage of the word line may be incurred.

In some embodiments, if the NMOS33is stronger and the PMOS32is weaker (i.e., fast NMOS slow PMOS (FS) corner), the carrier mobility of the NMOS33may be higher and the carrier mobility of the PMOS32may be lower. If the NMOS33is stronger and the PMOS32is weaker (i.e., fast NMOS slow PMOS (FS) corner), the voltage difference generated by the PMOS32itself may be larger. This may reduce the voltage applied to the gate electrode31G of the PMOS31. When the voltage applied to the gate electrode31G of the PMOS31reduces, the equivalent resistance of the PMOS31(e.g., operated in linear region) may decrease, and the drain current of the PMOS31may increase. Accordingly, the drop in the voltage of the word line may increase.

The word “fast” in the preceding paragraphs can refer to less time to achieve an “on” state, higher drain current, or less on-state impedance of the MOSFET. The word “slow” in the preceding paragraphs can refer to more time to achieve an “on” state, less drain current, or larger on-state impedance of the MOSFET.

The control circuit14may control the logic state of the PMOS31of the suppression circuit13. The control circuit14may control the voltage applied to the gate electrode31G of the PMOS31of the suppression circuit13. A pulse signal35can be input to the gate electrode32G, so as to control the PMOS32of the control circuit14. A pulse signal36can be input to the gate electrode33G, so as to control the NMOS33of the control circuit14. By controlling the pulse signals35and36, the PMOS32and NMOS33of the control circuit14can be dynamically or adaptively controlled. If the gate electrode32G of the PMOS32of the control circuit14is subject to a “low” logic state or a low voltage and the gate electrode33G of the NMOS33of the control circuit14is subject to a “high” logic state or a high voltage, the output34of the control circuit14will apply the corresponding voltage to the gate electrode31G. Since the gate electrode31G is subject to the corresponding voltage, the drive voltage of the word line11may drop accordingly. In some embodiments, the output34of the control circuit14may be about 0.2V to about 0.3V. In some embodiments, the voltage of the word line11may drop about 10%.

When performing a read operation, the word line11is set to a “high” logic state. This may cause a voltage bump at the storage node Q shown inFIG.2. If the voltage bump at the storage node Q is higher than a latch trigger threshold, the data stored in the storage node Q may be flipped. If the voltage of the word line11can drop for a predetermined amount, the voltage bump at the storage node Q may be less than the latch trigger threshold. Accordingly, the read disturb of the SRAM bit-cell20shown inFIG.2is reduced.

If the gate electrode32G of the PMOS32of the control circuit14is subject to a “high” logic state or a high voltage and the gate electrode33G of the NMOS33of the control circuit14is subject to a “low” logic state or a low voltage, the output34of the control circuit14will not apply a voltage to the gate electrode31G. Since the gate electrode31G is not subject to voltage, the PMOS31of the suppression circuit13may be turned off. Accordingly, the voltage drop of the word line11may be minimal or none.

If the PMOS32of the control circuit14is in a “low” logic state and the NMOS33of the control circuit14is in a “high” logic state, the output34of the control circuit14depends on the reaction speeds of the PMOS32and NMOS33. If the reaction speed of the NMOS33is higher than that of the PMOS32, the output34of the control circuit14is closer to ground. The output34of the control circuit14is in a “low” logic state. This may cause the PMOS31to be closer achieving an “on” state, and cause a voltage drop of the word line11. Accordingly, the read disturb of the SRAM bit-cell20may be reduced.

When performing a read operation on the electronic device1, the word line11is set to a “high” logic state. There will be a voltage bump on the storage node Q in the SRAM bit-cell20. The storage node Q should keep its logic state during the read operation. If the voltage bump is higher than latch trigger point, the internal state of SRAM bit-cell will be flipped. The suppression circuit13can generate a voltage drop in the voltage of the word line11. The suppression circuit13can control the amount of the voltage drop in the voltage of the word line11. The voltage bump formed on the storage node Q may be compensated by the voltage drop from the suppression circuit13. Thus, the data stored in the SRAM bit-cell20is not flipped.

The control circuit14can optimize the voltage of the word line11by minimizing the over/under voltage drop of the word line11. The control circuit14can tune the voltage drop in the voltage of the word line11automatically based on for process variations of the SRAM device15and/or the SRAM bit-cell20. With the control circuit14the SRAM device15and/or the SRAM bit-cell20experience less speed degradation. With the control circuit14, the SRAM device15and/or the SRAM bit-cell20reduce power consumption (e.g., due to the voltage drop in the voltage of the word line11).

FIG.4illustrates a schematic diagram of an exemplary control circuit40, in accordance with some embodiments of the present disclosure. The control circuit40includes one transistor of first type and one transistor of second type. The control circuit40comprises a PMOS41and an NMOS42. The PMOS41comprises a gate electrode41G, a drain electrode41D, and a source electrode41S. The NMOS42comprises a gate electrode42G, a drain electrode42D, and a source electrode42S. A signal43is input to the gate electrode41G of the PMOS41. A signal44is input to the gate electrode42G of the NMOS42. The drain electrode41D of the PMOS41is electrically connected to the drain electrode42D of the NMOS42. The output of the control circuit40is at the node45connecting the drain electrode41D of the PMOS41and the drain electrode421of the NMOS42. The source electrode41S of the PMOS41is electrically connected to a power source46. The source electrode42S of the NMOS42is electrically connected to the ground. The control circuit40is turned on based on one or more signals applied to at least one of the gate electrode41G of the PMOS41or the gate electrode42G of the NMOS42.

FIG.5illustrates a schematic diagram of an exemplary control circuit50, in accordance with some embodiments of the present disclosure. The control circuit50includes one transistor of first type and one transistor of second type. The control circuit50comprises a PMOS51and an NMOS52. The gate electrode51G of the PMOS51is electrically connected to the gate electrode52G of the NMOS52. The drain electrode51D of the PMOS51is electrically connected to the drain electrode52D of the NMOS52. The gate electrodes51G and52G of the PMOS51and NMOS52are further electrically connected to the drain electrodes51D and52D of the PMOS51and the NMOS52. The output of the control circuit50is the node53connecting the two drain electrodes51D and52D and the two gate electrodes51G and52G of the PMOS51and NMOS52. The source electrode51S of the PMOS51is electrically connected to a power source54. The source electrode52S of the NMOS52is electrically connected to the ground. The logic state of the node53depends on the reaction speeds of the PMOS51and NMOS52. The configuration of the PMOS51may be similar to a diode. The configuration of the NMOS52may be similar to a diode.

FIG.6illustrates a schematic diagram of an exemplary control circuit60, in accordance with some embodiments of the present disclosure. The control circuit60includes two transistors of first type and one transistor of second type. Control circuit60shown inFIG.6differs from control circuit50inFIG.5in that the control circuit60further comprises one transistor of first type. The control circuit60shown inFIG.6differs from control circuit50inFIG.5in that the control circuit60comprises an additional PMOS63. The control circuit60comprises a PMOS61, another PMOS63, and an NMOS62. The gate electrode61G of the PMOS61is electrically connected to the gate electrode62G of the NMOS62. The drain electrode61D of the PMOS61is electrically connected to the drain electrode62D of the NMOS62. The gate electrodes61G and62G of the PMOS61and NMOS62are further electrically connected to the drain electrodes61D and62D of the PMOS61and the NMOS62. The output of the control circuit60is the node64connecting the two drain electrodes61D and62D and the two gate electrodes61G and62G of the PMOS61and NMOS62. The source electrode61S of the PMOS61is electrically connected to the drain electrode63D of the PMOS63. The gate electrode63G of the PMOS63is electrically connected to a signal65. The source electrode63S of the PMOS63is electrically connected to a power source66. The source electrode62S of the NMOS62is electrically connected to the ground. The control circuit60is turned on based on the signal65applied to the gate electrode63G of the PMOS63. The configuration of the PMOS61may be similar to a diode. The configuration of the NMOS62may be similar to a diode.

FIG.7illustrates a schematic diagram of an exemplary control circuit70, in accordance with some embodiments of the present disclosure. The control circuit70includes one transistor of first type and two transistors of second type. The control circuit70shown inFIG.7differs from control circuit50inFIG.5in that the control circuit70further comprises one transistor of second type. The control circuit70shown inFIG.7differs from control circuit50inFIG.5in that the control circuit70comprises an additional NMOS73. The control circuit70comprises a PMOS71, an NMOS72, and another NMOS73. The gate electrode71G of the PMOS71is electrically connected to the gate electrode72G of the NMOS72. The drain electrode71D of the PMOS71is electrically connected to the drain electrode72D of the NMOS72. The gate electrodes71G and72G of the PMOS71and NMOS72are further electrically connected to the drain electrodes71D and72D of the PMOS71and the NMOS72. The output of the control circuit70is the node74connecting the two drain electrodes71D and72D and the two gate electrodes71G and72G of the PMOS71and NMOS72. The source electrode72S of the NMOS72is electrically connected to the drain electrode73D of the NMOS73. The gate electrode73G of the NMOS73is electrically connected to a signal75. The source electrode71S of the PMOS71is electrically connected to a power source76. The source electrode73S of the NMOS73is electrically connected to the ground. The control circuit14is turned on based on the signal75applied to the gate electrode73G of the NMOS73. The configuration of the PMOS71may be similar to a diode. The configuration of the NMOS72may be similar to a diode.

FIG.8illustrates a schematic diagram of an exemplary control circuit80, in accordance with some embodiments of the present disclosure. The control circuit80includes one transistor of first type and one transistor of second type. The control circuit80comprises a PMOS81and an NMOS82. The drain electrode81D of the PMOS81is electrically connected to the drain electrode82D of the NMOS82. The gate electrode81G of the PMOS81is electrically connected to the drain electrodes81D of the PMOS81. The output of the control circuit80is the node83connecting the two drain electrodes81D and82D of the PMOS81and NMOS82and the gate electrode81G of the PMOS81. The gate electrode82G of the NMOS82is electrically connected to a signal84. The source electrode81S of the PMOS81is electrically connected to a power source85. The source electrode82S of the NMOS82is electrically connected to the ground. The control circuit14is turned on based on the signal84applied to the gate electrode82G of the NMOS82. The configuration of the PMOS81may be similar to a diode.

FIG.9illustrates a schematic diagram of an exemplary control circuit90, in accordance with some embodiments of the present disclosure. The control circuit90includes one transistor of first type and one transistor of second type. The control circuit90comprises a PMOS91and an NMOS92. The drain electrode91D of the PMOS91is electrically connected to the drain electrode92D of the MVOS92. The gate electrode92G of the NMOS92is electrically connected to the drain electrodes92D of the NMOS92. The output of the control circuit90is the node93connecting the two drain electrodes91D and92D of the PMOS91and NMOS92and the gate electrode92G of the NMOS92. The gate electrode91G of the PMOS91is electrically connected to a signal94. The source electrode91S of the PMOS91is electrically connected to a power source95. The source electrode92S of the NMOS92is electrically connected to the ground. The control circuit14is turned on based on the signal94applied to the gate electrode91G of the PMOS91. The configuration of the NMOS92may be similar to a diode.

FIG.10illustrates exemplary waveforms of different nodes of an electronic device, in accordance with some embodiments of the present disclosure. The waveforms shown inFIG.10may be measured from a memory device (e.g., the SRAM device15) or a memory cell (e.g., the SRAM bit-cell20). Line1001shown inFIG.10illustrates the waveform of the word line (WL)21inFIG.2. Line1004shown inFIG.10illustrates the waveform of the node QB inFIG.2. Line1007shown inFIG.10illustrates the waveform of the node Q inFIG.2. Line1010shown inFIG.10illustrates the waveform of the bit line (BL)22inFIG.2. Line1013shown inFIG.10illustrates the waveform of the bit line bar (BLB)22′ inFIG.2.

In some embodiments, the NMOS33is weaker and the PMOS32is stronger (i.e., slow NMOS fast PMOS (SF) corner).FIG.10illustrates a condition of reading data “0” in the SRAM bit-cell20. When a read operation is performed at a timing T1, the voltage of the word line11is pulled up, as shown in line1001. After pulling-up the voltage of the word line11, a voltage bump may occur at the node Q, as shown in line1007. At the same time, a voltage drop may occur at the node QB, as shown in line1004. Before timing T1, the bit line22is set to data “1” (as shown in line1010), and bit line bar22′ is set to data “1” (as shown in line1013). When the voltage of the word line11is pulled up from the timing T1, the voltage of the bit line22starts to drop to a “low” logic state (data “0”), as shown in line1010. The voltage of the bit line bar22′ remains the same (data “1”), as shown in line1013. When the read operation is finished at timing T2, the voltage of the word line11is pulled down, as shown in line1001. At the same time, the voltage of the bit line22is pulled up to a “high” logic state (data “1”), as shown in line1010. The voltage of the bit line bar22′ remains the same (data “1”), as shown in line1013.

Line1002shown inFIG.10illustrates the waveform of the word line21inFIG.2cooperating with the suppression circuit13. Line1005shown inFIG.10illustrates the waveform of the node QB inFIG.2cooperating with the suppression circuit13. Line1008shown inFIG.10illustrates the waveform of the node Q inFIG.2cooperating with the suppression circuit13. Line1011shown inFIG.10illustrates the waveform of the bit line22inFIG.2cooperating with the suppression circuit13.

If the suppression circuit13is used for the SRAM bit-cell20shown inFIG.2, the peak amplitude of the word line11of the SRAM bit-cell20with the suppression circuit13(as shown in line1002) is less than that without the suppression circuit13(as shown in line1001). Similarly, the voltage spike of the node Q of the SRAM bit-cell20with the suppression circuit13(as shown in line1008) is less than that without the suppression circuit13(as shown in line1007). The voltage drop of the node QB of the SRAM bit-cell20with the suppression circuit13(as shown in line1005) is less than that without the suppression circuit13(as shown in line1004). The voltage drop of the bit line22of the SRAM bit-cell20with the suppression circuit13(as shown in line1011) is less than that without the suppression circuit13(as shown in line1010).

However, if the voltage drop of the word line11is excessive, the word line may be not in a “high” logic state during the read operation, and thus the read operation fails. If the voltage drop of the word line11is excessive, the power consumption due to the voltage drop may be too much. If the voltage drop of the word line11is excessive, the speed of the memory device may be impaired.

Line1003shown inFIG.10illustrates the waveform of the word line21inFIG.2cooperating with the suppression circuit13and the control circuit14. Line1006shown inFIG.10illustrates the waveform of the node QB inFIG.2cooperating with the suppression circuit13and the control circuit14. Line1009shown inFIG.10illustrates the waveform of the node Q inFIG.2cooperating with the suppression circuit13and the control circuit14. Line1012shown inFIG.10illustrates the waveform of the bit line22inFIG.2cooperating with the suppression circuit13and the control circuit14.

If the suppression circuit13and the control circuit14may be used for the SRAM bit-cell20shown inFIG.2, the peak amplitude of the word line11of the SRAM bit-cell20with the suppression circuit13and control circuit14(as shown in line1003) is less than that without the suppression circuit13(as shown in line1001). The peak amplitude of the word line11of the SRAM bit-cell20with the suppression circuit13and control circuit14(as shown in line1003) exceeds that with only the suppression circuit13(as shown in line1002). The control circuit14can control the voltage drop in the voltage of the word line. The control circuit14can keep the word line in a “high” logic state during the read operation. Thus, the read operation will not fail. If the voltage drop of the word line11is adequate, the power consumption due to the voltage drop may be controlled. If the voltage drop of the word line11is adequate, the speed of the memory device may be maintained.

Similarly, the voltage spike of the node Q of the SRAM bit-cell20with the suppression circuit13and control circuit14(as shown in line1009) is less than that without the suppression circuit13(as shown in line1007). The voltage spike of the node Q of the SRAM bit-cell20with the suppression circuit13and control circuit14(as shown in line1009) is larger than that with only the suppression circuit13(as shown in line1008).

The voltage drop of the node QB of the SRAM bit-cell20with the suppression circuit13and control circuit14(as shown in line1006) is less than that without the suppression circuit13(as shown in line1004). The voltage drop of the node QB of the SRAM bit-cell20with the suppression circuit13and control circuit14(as shown in line1006) is larger than that with only the suppression circuit13(as shown in line1005).

The voltage drop of the bit line22of the SRAM bit-cell20with the suppression circuit13and control circuit14(as shown in line1012) is less than that without the suppression circuit13(as shown in line1010). The voltage drop of the bit line22of the SRAM bit-cell20with the suppression circuit13and control circuit14(as shown in line1012) is larger than that with only the suppression circuit13(as shown in line1011).

FIG.11illustrates exemplary waveforms of different nodes of an electronic device, in accordance with some embodiments of the present disclosure. The waveforms shown inFIG.11may be measured from a memory device (e.g., the SRAM device15) or a memory cell (e.g., the SRAM bit-cell20). Line1101shown inFIG.11illustrates the waveform of the word line21inFIG.2. Line1104shown in11illustrates the waveform of the node QB inFIG.2. Line1107shown inFIG.11illustrates the waveform of the node Q inFIG.2.

In some embodiments, the NMOS33is stronger and the PMOS32is weaker (i.e., fast NMOS slow PMOS (FS) corner).FIG.11illustrates a condition of reading data “0” in the SRAM bit-cell20. When a read operation is performed at timing T3, the voltage of the word line11is pulled up, as shown in line1101. After pulling-up the voltage of the word line, a voltage bump may occur at the node Q, as shown in line1107. At the same time, a voltage drop may occur at the node QB, as shown in line1104.

Line1102shown inFIG.11illustrates the waveform of the word line21inFIG.2cooperating with the suppression circuit13. Line1105shown inFIG.11illustrates the waveform of the node QB inFIG.2cooperating with the suppression circuit13. Line1108shown inFIG.11illustrates the waveform of the node Q inFIG.2cooperating with the suppression circuit13.

If the suppression circuit13is used for the SRAM bit-cell20shown inFIG.2, the peak amplitude of the word line11of the SRAM bit-cell20with the suppression circuit13(as shown in line1102) is less than that without the suppression circuit13(as shown in line1101). The voltage spike of the node Q of the SRAM bit-cell20with the suppression circuit13(as shown in line1108) is almost the same as that without the suppression circuit13(as shown in line1107). The voltage drop of the node QB of the SRAM bit-cell20with the suppression circuit13(as shown in line1105) is almost the same as that without the suppression circuit13(as shown in line1104).

Due to process variations, the voltage spike generated at the node Q may be sufficient to cause the data stored at the node Q to be erroneously read as “0” to “1.” The voltage drop generated at the node QB may be sufficient to cause the data stored at the node QB to be erroneously read as “1” to “0.” This may cause the data stored in the SRAM bit-cell20to flip. The data stored in the nodes Q and QB is sensitive to the process variations of manufacturing the SRAM bit-cell20. The SRAM bit-cell20with only the suppression circuit13exhibits reduced process variation adaptability.

Line1103shown inFIG.11illustrates the waveform of the word line21inFIG.2cooperating with the suppression circuit13and the control circuit14. Line1106shown inFIG.11illustrates the waveform of the node QB inFIG.2cooperating with the suppression circuit13and the control circuit14. Line1109shown inFIG.11illustrates the waveform of the node Q inFIG.2cooperating with the suppression circuit13and the control circuit14.

If the suppression circuit13and the control circuit14are both used for the SRAM bit-cell20shown inFIG.2, the peak amplitude of the word line11of the SRAM bit-cell20with the suppression circuit13and control circuit14(as shown in line1103) is less than that without the suppression circuit13(as shown in line1101). The peak amplitude of the word line11of the SRAM bit-cell20with the suppression circuit13and control circuit14(as shown in line1103) is less than that with only the suppression circuit13(as shown in line1102).

The voltage spike of the node Q of the SRAM bit-cell20with the suppression circuit13and control circuit14(as shown in line1109) is less than that without the suppression circuit13(as shown in line1107). The voltage spike of the node Q of the SRAM bit-cell20with the suppression circuit13and control circuit14(as shown in line1109) is less than that with only the suppression circuit13(as shown in line1108).

The voltage drop of the node QB of the SRAM bit-cell20with the suppression circuit13and control circuit14(as shown in line1106) is less than that without the suppression circuit13(as shown in line1104). The voltage drop of the node QB of the SRAM bit-cell20with the suppression circuit13and control circuit14(as shown in line1106) is less than that with only the suppression circuit13(as shown in line1105).

The voltage spike generated at the node Q is controlled to avoid causing data stored at the node Q to be misread as “0” to “1.” The voltage drop generated at the node QB may be controlled to avoid causing the data stored at the node QB to be misread as “1” to “0.” Thus the data stored in the SRAM bit-cell20may not be flipped. The SRAM bit-cell20with the suppression circuit13and control circuit14has better process variation adaptability than that without the suppression circuit13. The SRAM bit-cell20with the suppression circuit13and control circuit14also has better process variation adaptability than that with only the suppression circuit13.

FIG.12is a flowchart of a method1200for operating an electronic circuit, in accordance with various aspects of the present disclosure.

The method1200begins with operation S1201in which a control circuit is activated to control a suppression circuit of the electronic circuit. Referring back toFIG.1, the control circuit14can control the suppression circuit13of the electronic device1.

The method1200continues with operation S1202in which a drive voltage of a word line of the electronic circuit is provided. Referring back toFIG.1, a drive voltage of the word line11of the electronic device1is provided to the SRAM bit-cell20.

The method1200continues with operation S1203in which the drive voltage of the word line is adjusted by the suppression circuit. Referring back toFIG.1, the suppression circuit13can adjust the drive voltage of the word line11input to the SRAM bit-cell20.

In some embodiments, the control circuit is activated by one or more input signals. Referring back toFIG.3, the control circuit14is activated by one or more input signals35and36. In some embodiments, the control circuit14controls the suppression circuit13. The suppression circuit13controls the voltage drop generated to the voltage of the word line11. The voltage of the word line11is adjusted by the suppression circuit13and then input to the SRAM bit-cell20.

In some embodiments, the control circuit comprises a first transistor of the first type (PMOS) and a second transistor of a second type (NMOS). The control circuit generates a control voltage based on a voltage difference caused by the first transistor and a voltage difference caused by the second transistor. With reference back toFIG.3, the control circuit14comprises a first transistor32of the first type (PMOS) and a second transistor33of a second type (NMOS). The control circuit13generates a control voltage based on a voltage difference caused by the first transistor32and a voltage difference caused by the second transistor33.

In some embodiments, the suppression circuit decreases the drive voltage of the word line based on the control voltage. With reference back toFIGS.3and10, the suppression circuit13generates a voltage drop to the voltage of the word line and thus decreases the drive voltage of the word line11based on the control voltage input to the suppression circuit13.

The method1200is merely an example, and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, or after each operations of the method1200, and some operations described can be replaced, eliminated, or moved around for additional embodiments of the method. In some embodiments, the method1200can include further operations not depicted inFIG.12.

Some embodiments of the present disclosure provide an electronic circuit. The electronic circuit comprises a driver circuit configured to provide a drive voltage to a word line of the electronic circuit, a suppression circuit electrically connected to the driver circuit and the word line, and a control circuit electrically connected to the suppression circuit. The suppression circuit is configured to generate a voltage drop in the drive voltage. The control circuit controls the suppression circuit.

Some embodiments of the present disclosure provide a static random access memory (SRAM). The SRAM comprises a word line, a bit line, a bit line bar, a first inverter formed by a first transistor and a second transistor, a second inverter formed by a third transistor and a fourth transistor, a first node (QB) connected to a drain electrode of the first transistor and a drain electrode of the second transistor, a second node (Q) connected to a drain electrode of the third transistor and a drain electrode of the fourth transistor, a first control transistor electrically connected to the word line, the first inverter, and the bit line bar, a second control transistor electrically connected to the word line, the second inverter, and the bit line, a suppression circuit electrically connected to the word line, and a control circuit electrically connected to the suppression circuit. The suppression circuit is configured to generate a voltage drop in a drive voltage of the word line. The control circuit controls the suppression circuit to generate the voltage drop.

Some embodiments of the present disclosure provide a method for operating an electronic circuit. The method comprises activating a control circuit used for controlling a suppression circuit of the electronic circuit, providing a drive voltage of a word line of the electronic circuit, and adjusting the drive voltage of the word line by the suppression circuit.

The foregoing outlines structures of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.