Patent ID: 12243609

Throughout the drawings and the detailed description, the same reference numerals refer to the same elements. The drawings may not be to scale, and the relative size, proportions, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience.

DETAILED DESCRIPTION

The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and/or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatuses, and/or systems described herein will be apparent after an understanding of the disclosure of this application. For example, the sequences of operations described herein are merely examples, and are not limited to those set forth herein, but may be changed as will be apparent after an understanding of the disclosure of this application, with the exception of operations necessarily occurring in a certain order. Also, descriptions of features that are known in the art may be omitted for increased clarity and conciseness.

The features described herein may be embodied in different forms, and are not to be construed as being limited to the examples described herein. Rather, the examples described herein have been provided merely to illustrate some of the many possible ways of implementing the methods, apparatuses, and/or systems described herein that will be apparent after an understanding of the disclosure of this application.

Throughout the specification, when an element, such as a layer, region, or substrate, is described as being “on,” “connected to,” or “coupled to” another element, it may be directly “on,” “connected to,” or “coupled to” the other element, or there may be one or more other elements intervening therebetween. In contrast, when an element is described as being “directly on,” “directly connected to,” or “directly coupled to” another element, there can be no other elements intervening therebetween.

As used herein, the term “and/or” includes any one and any combination of any two or more of the associated listed items.

Although terms such as “first,” “second,” and “third” may be used herein to describe various members, components, regions, layers, or sections, these members, components, regions, layers, or sections are not to be limited by these terms. Rather, these terms are only used to distinguish one member, component, region, layer, or section from another member, component, region, layer, or section. Thus, a first member, component, region, layer, or section referred to in examples described herein may also be referred to as a second member, component, region, layer, or section without departing from the teachings of the examples.

Spatially relative terms such as “above,” “upper,” “below,” and “lower” may be used herein for ease of description to describe one element's relationship to another element as shown in the figures. Such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as being “above” or “upper” relative to another element will then be “below” or “lower” relative to the other element. Thus, the term “above” encompasses both the above and below orientations depending on the spatial orientation of the device. The device may also be oriented in other ways (for example, rotated 90 degrees or at other orientations), and the spatially relative terms used herein are to be interpreted accordingly.

The terminology used herein is for describing various examples only, and is not to be used to limit the disclosure. The articles “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms “comprises,” “includes,” and “has” specify the presence of stated features, numbers, operations, members, elements, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, members, elements, and/or combinations thereof.

Due to manufacturing techniques and/or tolerances, variations of the shapes shown in the drawings may occur. Thus, the examples described herein are not limited to the specific shapes shown in the drawings, but include changes in shape that occur during manufacturing.

The features of the examples described herein may be combined in various ways as will be apparent after an understanding of the disclosure of this application. Further, although the examples described herein have a variety of configurations, other configurations are possible as will be apparent after an understanding of the disclosure of this application.

The disclosure provides a method of an octo mode program and erase operation that may precisely screen a failed chip, where the failure is due, as an example, to a particle or a poly residue, and may reduce a test time in a non-volatile memory device.

A targeted problem of the disclosure is not limited by the problems which are mentioned above, and other problems may be understood by a person skilled in the relevant field of technology, from the following description.

A non-volatile memory device100including an octo mode program and erase operation for a test time reduction may be applied to a non-volatile memory device such as EEPROM (Electrically Erasable and Programmable ROM), flash memory, NAND flash memory, NOR flash memory, PRAM (Phase-change RAM), MRAM (Magnetic RAM), RRAM (Resistive RAM), FRAM (Ferroelectric RAM), etc., but it is not limited thereto.

Additionally, the octo mode program and erase operation may be applied to a memory system where different types of non-volatile memory devices are implemented. Moreover, technical features of the examples may be adopted in a storage device such as a Solid State Drive (SSD). The “octo” mode or “octo” signal may refer to the selection of word lines in multiples of 8.

Section 1:

<A Non-Volatile Memory Device Including an Octo Mode Program and Erase Operation for a Test Time Reduction>

A detailed description for the disclosure is given below, with attached drawings.

FIG.1illustrates each element of a non-volatile memory device including an octo mode program and erase operation for a test time reduction and its organic combination in accordance with one or more embodiments.

The examples relate to a high tech NVM memory implementing a program (PGM)/erase (ERS) operation of a FN tunneling method. Accordingly, a non-volatile memory device of the examples may perform a write operation of a FN tunneling method. The example also relates to a circuit technology that screens a fail sample to reduce a test time for a shorted fail sample of a word line (WL) due to a metal particle, etc. The examples relate to a circuit technology for an improved method since it may be difficult to do screening by a metal particle, etc. in a high tech environment.

Referring toFIG.1, a non-volatile memory device100including an octo mode program and erase operation that reduces a non-volatile memory device test time, includes a memory cell array110including M word lines and N bit lines; a control logic device120, that outputs an octo signal, a program signal and an erase signal based on the receipt of an external signal; an address decoder130, that receives the octo signal output from the control logic120, and outputs a word line selection signal and a bit line selection signal; a high voltage generator140, that receives the program signal and the erase signal output from the control logic120, and outputs a read voltage and a write voltage; a row decoder150, that receives the word line selection signal, and selects a word line of the memory cell array110; a column decoder160, that receives the bit line selection signal, and selects a bit line of the memory cell array110; a page buffer170, that receives the read voltage and the write voltage, and saves data to be programmed; a data latch180, that saves read data obtained on the basis of a read operation; and a write data input (DIN) and a read data output (DOUT). In the examples, the page buffer170may be referred to as a page program buffer.

Additionally, when the octo signal is applied to the address decoder130, a non-volatile memory device of the examples may simultaneously select M/8 word lines corresponding to an octo row, among the M word lines. A write voltage may be applied to memory cells connected to M/8 word lines corresponding to the octo row, and a voltage that is different from the write voltage may be applied to memory cells connected to the rest of the word lines, except for M/8 word lines corresponding to the octo row.

An EEPROM device may be embedded in a memory cell array110including a plurality of memory cells in accordance with one or more examples. In an example, an EEPROM device having a 512 Kbit memory size with 512 rows*1024 columns may be included.

That is, a memory cell array including a plurality of memory cells of the examples may include 64 KB EEPROM having 512ea word lines.

When a control signal is received, a program (PGM)/erase (ERS) signal that controls a high voltage generator140of a memory cell, may be supplied to a control logic device120in accordance with one or more embodiments.

Various signals may be included in a control signal that is inputted in a control logic device120of the examples. Typically, there are signals received such as Chip Enable (CEB) (To enable IP block, Chip Enable, B means low active), Write Enable (WEB) (Write enable signal, B means low active), Clock (CLK) (Clock signal), Read Enable (REB) (Read enable signal), Reset (RSTB) (reset signal), Power Down (PDB) (Power down enable signal), Page Buffer (PBRB) (page buffer reset signal), Load enable (LDEB) (Load enable signal), Erase Enable ERSB (Erase enable signal, B means low active), Program Enable (PGMB) (Program enable signal, B means low active), TEST[2:0], Write Enable (WRTEN) (Write enable signal of a chip), TRIM[5:0], etc.

In an example, the control logic device120may supply signals such as ALL, EVEN, ODD, OCTO, etc., to control an address decoder130. Among these signals, ALL, EVEN, ODD, and OCTO signals may control a word line (WL), which is an output of a row decoder150, by providing those signals with an address decoder130.

In an example, the control logic device120may further generate a hexa signal ( 1/16 signal) to select a word line by 16ea among a plurality of word lines of the memory cell array, besides ALL, EVEN, ODD, OCTO signals. In an example, the control logic may further generate a 1/32 signal to select a word line by 32ea among a plurality of word lines of the memory cell array.

Accordingly, a word line (WL), which is an output of a row decoder150, may be selected by ALL, EVEN, ODD, and OCTO signals. That is, a word line corresponding to all row, even row, odd row, and octo row (0, 8, 16, 24, 32, . . . , 504 row, etc.) may be selected. To reduce a program (PGM)/erase (ERS) test time in a PGM/ERS operation, by using ALL, EVEN, ODD, and OCTO signals, a program/erase (PGM/ERS) operation may be performed with a memory cell in all, even, odd, and octo mode.

Meanwhile, when a foreign substance (by product) such as a metal particle or a poly residue falls in a region of a row decoder150, a shorted fail may occur between adjacent word lines. In this example, before providing a sample to a customer, a shorted fail has to be screened. The screening process may take an extended period of time when cells connected to a word line are tested in serial to detect a shorted fail. For example, 2.5 ms per word line*512ea word lines=1.28 sec may be desired. The calculation is assumed with 512 word lines and a test time of 2.5 ms per word line.

Accordingly, to reduce a test time, screening may be performed by a page program/erase test method of ALL, EVEN, ODD mode. In the ALL page program/erase test method, 2.5 ms/512=4.88 μs are desired because the ALL page program/erase test method may test all cells at once. The EVEN or ODD test method may simultaneously test word lines corresponding to even numbers or odd numbers. Therefore, a test time=2.5 ms*2ea/512ea=9.7 μs may be desired, and thus, a test time is reduced considerably as compared to typical cases.

However, when a size of a metal particle or poly residue is large, a fail sample may not be screened properly because it may not be screened by a program/erase (PGM/ERS) operation of the ALL, EVEN, ODD mode. During a process of testing the fail sample, an octo mode PGM/ERS operation may be used to perform the screening operation.

Each ⅛ WL may be selected by an octo signal in an octo mode PMG/ERS operation. When the number of a word line is 512, word lines corresponding to 0, 8, 16, 24, 32, . . . , 504 row may be selected. Therefore, for a 64 KB EEPROM having 512ea word lines (WL) structure, a total test time may be reduced to be 2.5 ms*8ea/512ea=39 μs. A test time may be considerably reduced from a typical 1.28 sec, resulting in reducing a test cost. When a fail sample appears as a shorted fail because a metal particle or a poly residue falls in a region of a row decoder150, it may be possible to screen a fail sample. For a 64 KB EEPROM having 512ea WL through the implementation of an OCTO mode PGM/ERS operation, memory cells corresponding to 64ea WL may be erased or programmed simultaneously. An OCTO mode erase method of a non-volatile memory device (NVM memory) of the examples will be described inFIG.4.

Signals of the ALL, EVEN, ODD, and OCTO modes, etc. may be generated by using a control signal of TEST<2:0> in a control logic device120. In an OCTO ERS operation, 64ea word lines (WL) may be selected by an octo signal among 512ea word lines (WL), and a corresponding cell may be selected and erased simultaneously. In an OCTO PGM operation, 64ea word lines (WL) may be selected by an octo signal among 512ea word lines (WL), and a corresponding cell may be selected and programmed simultaneously.

The control logic device120, in accordance with one or more examples may be implemented to control various operations of a non-volatile memory device including an octo mode program and erase operation for a test time reduction. Additionally, the control logic120may be operated based on a control signal received from an external source. The control logic device120of the examples may be connected to an address decoder130, a high voltage generator140, etc.

Additionally, the control logic device120of the examples may further generate a hexa signal ( 1/16 signal) to simultaneously select word lines in multiples of 16 among a plurality of word lines of a memory (NVM) cell array110. Further, the control logic device120of the examples may further generate a 1/32 signal to simultaneously select word lines in multiples of 32 among a plurality of word lines of a memory cell array110.

Still referring toFIG.1, in order to control the high voltage generator140, the control logic device120of the examples may deliver a program (PGM) signal and/or an erase (ERS) signal to the high voltage generator140.

The address decoder130of the examples may decode an address signal (ADD) received from an external source and deliver the received address signal (ADD) to the row decoder150and/or the column decoder160. Additionally, the address decoder130of the examples may deliver a decoded signal to select a word line (WL) and a bit line (BL) of the memory cell array110to the row decoder150and/or the column decoder160.

In an example, the address decoder130of the examples may receive the ALL, ODD, EVEN, and/or OCTO signals from the control logic device120.

The ALL signal may refer to a command signal to select all word lines (WL) when a program operation and an erase operation, etc., is performed

The ODD signal may refer to a command signal to select odd-numbered word lines (WL) when a program operation and an erase operation, etc., is performed.

The EVEN signal may refer to a command signal to select even-numbered word lines (WL) when a program operation and an erase operation, etc., is performed.

The OCTO signal may refer to a command signal to simultaneously select word lines in multiples of 8 among a plurality of word lines of a memory cell array110when a program operation and an erase operation, etc., is performed. Word lines selected in multiples of 8 may be simultaneously programmed or erased.

In an example, the address decoder130may receive a hexa signal and 1/32 signal, etc. from the control logic device120. A hexa signal may refer to a command signal to simultaneously select word lines in multiples of 16 among a plurality of word lines of the memory (NVM) cell array110when performing a program operation and an erase operation, etc. 1/32 signal may refer to a command signal to simultaneously select word lines in multiples of 32 among a plurality of word lines of a memory cell array110when performing a program operation and an erase operation, etc.

In an example, the address decoder130may include an address buffer that saves a received address (ADD) signal.

In an example, the high voltage generator140may generate a voltage supplied to a plurality of word lines and memory cells based on a control operation of the control logic device120.

In an example, the high voltage generator140may receive a program signal and/or an erase signal from the control logic device120.

The high voltage generator140may be connected to the memory cell array110, the control logic device120, the row decoder150, etc. The high voltage generator140may receive power from an external source, for example, a power supply voltage (Vcc) and a ground voltage (Vss), etc. The high voltage generator140may generate voltages having various levels from a power supply voltage (Vcc) and a ground voltage (Vss), etc. based on a control of a control logic device120. Voltages generated in the high voltage generator140may be delivered to the memory cell array110, the row decoder150, and the page buffer170, etc. under a control of a control logic device120.

That is, the high voltage generator140may generate various types of word line voltages that may be supplied to each word line and a voltage that may be supplied to a bulk (for example, a well region, HDNW, HPW) where memory cells are formed, according to a control of the control logic device120. There may be a program voltage (Vpgm or VPP), a selection and unselection read voltage (Vrd, Vread), etc. for word line voltages that are supplied to each word line. The high voltage generator140may generate a source line voltage (Vssl, Vgsl) provided with source lines when performing a read operation and a program operation. Additionally, the high voltage generator140may generate an erase voltage (Vers) that may be supplied to a bulk, and may also be simultaneously supplied to a memory cell array110, when an erase operation is performed. Various voltages are described that may be generated in the high voltage generator140. However, the voltages are not limited thereto.

The row decoder150may select one or more cells among memory cells of the memory cell array110based on a received address (ADD) signal decoded from the address decoder130. That is, the row decoder150may select one of the memory blocks of the memory cell array110by responding to an address signal. The row decoder150may select one of a plurality of word lines of a selected memory block.

Additionally, since the row decoder150may be connected to the high voltage generator140in addition to being connected to the address decoder130, the row decoder150may receive a voltage that is generated in the high voltage generator140. Further, the row decoder150may deliver a word line voltage to a word line of a selected memory block. When performing a program operation, the row decoder150may deliver a program voltage (Vpgm or VPP) to a selected WL.

The row decoder150may decode a row address. Additionally, the row decoder150may perform different types of access operations such as program (PGM), erase (ERS), read, write, etc. The row decoder150may simultaneously select word lines in multiples of 8 among a plurality of word lines of the memory cell array110based on an octo signal, when performing operations such as a program operation and an erase operation, etc. Further, the row decoder150may simultaneously select word lines in multiples of 2, 4, 16, 32, etc. among a plurality of word lines of the memory cell array110, when performing a program operation and an erase operation, etc.

The column decoder160may select one of memory blocks of a memory cell array110according to an address (ADD) signal decoded from an address decoder130. The column decoder160may select one of a plurality of bit lines (BL) of a selected memory block. The column decoder160may decode a column address. The column decoder160may deliver a decoded column address signal to a read unit and write unit (not shown), or the page buffer170, etc.

The page buffer170may supply data desired in a program operation to the memory cell array110, by a page unit or by a bit unit. The non-volatile memory device100, including an octo mode program and erase operation with a reduced test time, may further include an input/output buffer (not shown). An input/output buffer may deliver write data that are inputted in a program operation to the page buffer170. An input/output buffer may output read data externally in a read operation that is provided from the page buffer170. An input/output buffer may deliver an inputted address or command to the control logic device120or to the row decoder150.

The data latch180may include a sense amplifier (sense AMP, not shown). The data latch180may receive data saved in a memory cell that is selected in a read operation through a bit line. By comparing received data with read data generated by a reference voltage, the data latch180may output read data (DOUT) for a memory cell selected externally.

Section 2:

<A Test Method of a Non-Volatile Memory Device Including an Octo Mode Program and Erase Operation with Reduced Test Time>

In a test method of a non-volatile memory device including an octo mode program and erase operation with a reduced test time reduction, elements of a non-volatile memory device may be applied correspondingly to Section 1 above.

A test method of a non-volatile memory device including an octo mode program and erase operation for a test time reduction may relate to circuit technology that reduces a test time, and may screen a fail sample due to a metal particle, poly residue, etc. where an adjacent word line (WL) is shorted in a high tech non-volatile memory performing a program (PGM)/erase (ERS) operation of a FN tunneling method.

An example test method of a non-volatile memory device may include an octo mode program and erase operations for a test time reduction may include transmitting an octo signal from a control logic device120to an address decoder130; transmitting the octo signal from the address decoder130to the row decoder150; transmitting the octo signal from the row decoder150to the memory cell array110; selecting M/8 word lines simultaneously corresponding to an octo row among M word lines of the memory cell array by the octo signal; and performing a write operation simultaneously in memory cells connected to M/8 word lines corresponding to the octo row.

In an example test method of a non-volatile memory device, the control logic device120may deliver a write signal to the high voltage generator140.

In an example test method of a non-volatile memory device, the high voltage generator140may supply a write voltage to the memory cell array110.

In an example test method of a non-volatile memory device, the write operation may be performed by supplying the write voltage to a memory cell connected to M/8 word lines corresponding to the octo row.

In an example test method of a non-volatile memory device, a voltage that is different from the write voltage may be applied to a memory cell that is not connected to M/8 word lines corresponding to the octo row.

In an example test method of a non-volatile memory device, the write operation may include an octo array erase mode, and the octo array erase mode may be controlled by a write enable signal (WEB) and an erase enable signal (ERSB) supplied from the control logic device120.

In an example test method of a non-volatile memory device, the write operation may include an octo array program mode, and the octo array program mode may be controlled by a write enable signal (WEB) and a program enable signal (PGMB) supplied from the control logic device120.

The address decoder130may receive an address signal from an external source, and may also receive an ALL signal, an ODD signal, an EVEN signal and/or an OCTO signal from the control logic device120, and decode each of the received signals. The address decoder130may deliver the decoded address signal, the decoded ALL signal, the decoded ODD signal, the decoded EVEN signal, and/or the decoded OCTO signal to the row decoder150. The address decoder130may receive a hexa signal and/or a 1/32 signal from the control logic device120, decode the received signal, and deliver a decoded hexa signal and/or a decoded 1/32 signal to the row decoder150.

An example test method may further include the high voltage generator140generating a voltage that is supplied to memory cells that are included in the memory cell array110and the plurality of word lines by the received program signal or erase signal.

The row decoder150may perform a program operation or an erase operation by selecting word lines simultaneously by 1ea, 2ea, 8ea (multiples of 8), 16ea (multiples of 16), 32ea (multiples of 32), etc. among a plurality of word lines of the memory cell array110. Based on the generation of the voltage by the high voltage generator140, a program operation or an erase operation of the memory cell array110by the row decoder150may be performed.

In an example test method of a non-volatile memory device including an octo mode program and erase operation for a test time reduction, a page program PGM)/erase (ERS) operation may be performed to screen a fail sample that is not screened due to an effect of a particle or a poly residue larger than typical examples, or a layout arrangement of a row decoder, etc.

In an example, an example may be made with a 64 KB EEPROM having 512 word lines (WL) and 1024 columns. In an example, it may be assumed that the 64 KB EEPROM has 512 pages instead of 512 word lines. Therefore, when performing each page program (PGM)/erase (ERS) operation, by an octo signal delivered from the control logic device120, the row decoder150may simultaneously select word lines in multiples of 8 among a plurality of word lines of the memory cell array110.

Accordingly, it may be possible to screen a fail sample precisely and rapidly that is not screened due to an effect of a particle or a poly residue larger than typical examples, or a layout arrangement of a row decoder, etc. Additionally, compared with a typical test method of performing a program (PGM)/erase (ERS) operation by a page unit, a test time may be reduced over 85%.

FIG.2andFIG.3illustrate an example process of performing an erase (ERS) operation or a program (PGM) operation by an octo signal in a test method of an example non-volatile memory device including an octo mode program and erase operations for a test time reduction, in accordance with one or more embodiments. The meaning of various abbreviations described inFIG.2andFIG.3are as indicated in Table 1 below.

TABLE 1Signal nameDescriptionCEBTo enable IP block, Chip Enable, B means low activeWRTENWrite enable signal of a ChipPGMBProgram enable signal, B means low activeERSBErase enable signal, B means low activeWEBWrite enable signal, B means low activeADD[7:5]Address, from 5 to 7Octo AddrjOcto Address, j is addressingtPGMProgram timetWHWrite hold timetCEHChip enable hold time7 HHexa 7, TEST<2:0> = 111tWSWrite set-up timetWCESChip write enable set-up time

Referring toFIG.2andFIG.3, in an example, TEST<2:0> is a control signal generated in the control logic device120, and based on the TEST<2:0> signal, an ALL signal, an ODD signal, an EVEN signal and/or an OCTO signal may be delivered to the address decoder130to control the address decoder130. Each condition of the TEST<2:0> mode is described with reference to Table 2 below.

TABLE 2MODESTATETEST[2:0]REBWEBLDEBERSBPGMBNormal modeXLLLXXXXXErase verifyREADLLHLHHHHProgram verifyREADLHLLHHHHAll RowErase/PGMLHHHLHL/HH/LOdd RowErase/PGMHLLHLHL/HH/LEven RowErase/PGMHLHHLHL/HH/LOcto RowErase/PGMHHHHLHL/HH/L

Referring to Table 2, REB refers to a Read enable signal, WEB refers to a Write enable signal, LDEB refers to a Load enable signal, ERSB refers to an Erase enable signal, and PGMB refers to a Program enable signal. In the examples, B refers to low (L) active. L refers to setting low, and H refers to setting high. In an example, when REB is set as H, it becomes inactive. When WEB is set as L, a WEB signal becomes active.

FIG.2illustrates an example process of performing an erase (ERS) operation based on an octo signal in an example test method of a non-volatile memory device including an octo mode program and erase operation for a test time reduction, in accordance with one or more embodiments.

Referring toFIG.2, an octo array erase mode may be controlled only by a Write enable signal (WEB) and an ERSB (Erase enable signal) input signal. A test bit (TEST[2:0]) may be set as 7H. By setting a test bit (TEST[2:0]) as a logic 7H, a selected page (64 Kbit) may be erased all at once. A page selected by ADD[7:5] may be erased simultaneously.

In an octo array erase mode, a control input signal: reset signal (RSTB), Power down enable signal (PDB), Read enable signal (REB), Load enable signal (LDEB) and Page buffer reset signal (PGMB) may remain as a high.

By designating an input signal Write enable (WEB) as a low, an octo array erase mode may be started. When an Erase enable signal (ERSB) input signal is activated, an octo array erase mode may be started from a falling edge of a WEB for an octo array. During an octo array erase mode, WEB and ERSB may be designated as a low and activated. Normally, an octo array erase mode may last for 2.5 ms. To complete an octo array erase mode, a WEB and ERSB input signal may be designated, and marked as a high.

FIG.3illustrates a process of performing a program (PGM) operation by an octo signal in an example test method of an example non-volatile memory device including an octo mode program and erase operation for a test time reduction, in accordance with one or more embodiments.

Referring toFIG.3, a program operation only programs “1” data of a page buffer that is currently selected. A page address (ADD[13:5]) and a column address (ADD[4:0]) may be designated separately, such as in an erase operation.

Referring toFIG.3, a program operation may be controlled by a Write enable (WEB) and a Program enable (PGMB) input signals. While a control input signal: RSTB, PDB, REB, LDEB, and ERSB may remain as a high, a program operation may be started by designating input signals WEB and PGMB as a low. When a PGMB input signal becomes a low, a program operation for a selected page may be started from a falling edge of WEB. A selected page may be latched from a falling edge of a WEB, after a PGMB input signal is marked as a low. During an entire write program operation that normally lasts 2.5 ms, a WEB and PGMB may be designated as a low. To complete a program operation, by designating a PGMB input signal and a WEB input signal as a high, a write cycle execution for a designated address page may be completed.

Referring toFIG.2andFIG.3, for 64 KB EEPROM having 512 word lines (WL) and 1024 columns, memory cells corresponding to 64ea word lines (WL) may be simultaneously erased or programmed by a test method of the disclosure.

Table 3 below illustrates an octo address (ADD [7:5]).

TABLE 3OctoTest[2:0]pageADD[7:5]Octo pages7 h00 hPage[0:504:8], 0, 8, 16, 24, . . . , 480,488, 496, 50411 hPage[1:505:8], 1, 9, 17, 25, . . . , 481,489, 497, 50522 hPage[2:506:8], 2, 10, 18, 26, . . . , 482,490, 498, 50633 hPage[3:507:8], 3, 11, 19, 27, . . . , 483,491, 499, 50744 hPage[4:508:8], 4, 12, 20, 28, . . . , 484,492, 500, 50855 hPage[5:509:8], 5, 13, 21, 29, . . . , 485,493, 501, 50966 hPage[6:510:8], 6, 14, 22, 30, . . . , 486,494, 502, 51077 hPage[7:511:8], 7, 15, 23, 31, . . . , 487,495, 503, 511

Referring to Table 3, an octo page is defined from 0 to 7. 64 word lines (page) may be simultaneously selected for each page. In an example, when an octo page is 0, page 0, page 8, . . . , page 504 are selected, and memory cells corresponding to 64ea word lines may be simultaneously erased or programmed. Octo rows corresponding to 0, 8, 16, 24, . . . , 480, 488, 496, 504 may be selected for a write operation.

Additionally, when an octo page is 1, page 1, page 9, . . . , page 505 may be selected, and memory cells corresponding to 64ea word lines may be simultaneously erased or programmed. Octo rows corresponding to 1, 9, 17, 25, . . . , 481, 489, 497, 505 may be selected for a write operation. Accordingly, a write operation may be performed such as an erase or program operation for 512 rows in total.

Table 4 below illustrates a cell bias condition for a page program operation, page erase operation, and read operation of an EEPROM, in accordance with one or more embodiments.

TABLE 4SelectedUn-selectedSelectedUn-selectedModeWLWLBLBLHPWHDNWPage ProgramVPP(16.5 V)0 V0 V9 V0 V0 VPage Erase0 V13.5 VFloatFloat13.5 V13.5 VRead3.0 V0 V0.6~1.2 VFloat0 V0 V

In an example, for a page program operation, a program voltage 16.5V (VPP) may be applied to a word line (WL) of a selected cell. Additionally, for a page program operation, 0V may be applied to bit line (BL) of a selected cell. 0V and 9V may be applied respectively to a word line and a bit line of an unselected cell. 0V may be applied to a high voltage P-type well (HPW) and a high voltage deep N-type well (HDNW) respectively. According to an example, a HDNW may be formed in a substrate, and a HPW may be formed inside a HDNW. A tunneling gate dielectric, a floating gate, an ONO insulating dielectric layer, and a control gate may be formed on a HPW.

Herein, a word line (WL) may be electrically connected to a control gate of a non-volatile memory cell (NVM memory cell), and a bit line (BL) may be electrically connected to a drain region of a NVM memory cell.

In an example, for a page erase operation, an erase voltage 0V may be applied to a word line of a selected cell. 13.5V may be applied to a word line of an unselected cell. Selected and unselected bit lines may be floated.

FIGS.4A to4Cillustrate diagrams of implementations of an erase operation by an octo signal in an example test method of an example non-volatile memory device including an octo mode program and erase operation for a test time reduction, in accordance with one or more embodiments.

Referring toFIGS.4A-4C, in a 64 KB EEPROM having 512 word lines (WL) and 1024 bit lines (BL), an erase operation by an octo signal may be performed by implementing an example test method. 1024 cells may be arranged in a column for a 64 KB EEPROM. There are 1024 cells in each page. One word line is connected to 1024 bit lines, and 1 bit line is connected to 512 word lines. When it is assumed that a memory cell array composes M word lines and N bit lines, for 64 KB EEPROM, M is 64*8=512, and N is 1024. 1024 cells are arranged widthwise in each page. Pages may exist from 0 to 511 pages. Therefore, M−1 page may become the maximum page.

When inputting an octo signal, memory cells corresponding to an octo row may be selected. Like 0, 8, 16, 324, 32, . . . , 504, etc., 0, 8, 16, 324, 32, . . . , 504 page or 0, 8, 16, 324, 32, . . . , 504 word line, which are multiples of 8, may be selected. That is, M/8=512/8=64 word lines or pages may be simultaneously selected. A write voltage, as illustrated in Table 4 above, may be applied to memory cells connected to a selected word line. In an example, in a program operation, 16.5V may be applied to a selected cell. In an erase operation, 0V may be applied to a selected cell. Additionally, a voltage that is different from a write voltage may be applied to memory cells connected to an unselected word line, which is 0V or 13.5V.

More specifically, referring toFIG.4A, in Octo0 write, page 0, page 8, . . . , page 504 may be selected, and simultaneously, memory cells corresponding to 64ea word lines (WL) may be erased.

Additionally, referring toFIG.4B, in Octo1 write, page 1, page 9, . . . , page 505 may be selected, and simultaneously, memory cells corresponding to 64ea word lines (WL) may be erased.

Additionally, referring toFIG.4C, after successively going through 2 to 6 write by an identical process, in Octo7 write, page 7, page 15, . . . , page 511 may be selected, and simultaneously, memory cells corresponding to 64ea word lines (WL) may be erased.

InFIGS.4A-4C, “FFFF****” or “0000****” are illustrated. In the examples, ‘F’ refers to an unselected cell and a programmed state. Number ‘0’ refers to an erase operation of a selected cell. All 1024 cells start with a programmed state in the beginning.

For a page erase operation, an erase voltage 0V may be applied to a word line (page) of a selected cell. 13.5V may be applied to a word line of an unselected cell. When there is a metal particle on word lines of opposite sides, 6-7V may be applied to a word line as an erase voltage, which is a median value. In that example, it may not be possible to perform an erase operation, and a cell may be considered as a fail. A selected word line and unselected word line may become short in an erase operation, and they may be in a state that an erase voltage is not applied.

Likewise, for a program operation, a program voltage 16.5V may be applied to a word line of a selected cell. 0V may be applied to a word line of an unselected cell. When there is a metal particle on word lines of opposite sides, 8-9V may be applied to a word line as a program voltage, which is a median value. In that example, it may not be possible to perform a program operation, and a cell may be considered as a fail. A selected word line and unselected word line may become short in a program operation, and they may be in a state that a program voltage is not applied.

When there is a huge metal particle, it may be formed from page 0 to page 9. When an erase operation test or a program operation test is conducted by selecting a word line per octo (multiples of 8), it may be easy to check a fail.

The examples may perform a program/erase operation in a word line selected in an octo mode, by generating an octo signal through an internal logic. However, an opposite state may appear in a peripheral, unselected word line. When a metal particle falls on a selected word line and unselected word line, they may be shorted. A program/erase (PGM/ERS) operation may not be performed normally. Likewise, it may be possible to determine whether there is a fallen metal particle.

According to the examples, by performing a program/erase (PGM/ERS) operation by selecting word lines in multiples of 8 among a plurality of word lines of a memory cell array110, it may be possible to precisely screen a fail chip due to a particle or poly residue. Additionally, a test time may be considerably reduced.

Further, a test cost may be considerable reduced to detect a failed chip based on particle or poly residue.

While this disclosure includes specific examples, it will be apparent after an understanding of the disclosure of this application that various changes in form and details may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in a descriptive sense only, and not for purposes of limitation. Descriptions of features or aspects in each example are to be considered as being applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and/or if components in a described system, architecture, device, or circuit are combined in a different manner, and/or replaced or supplemented by other components or their equivalents. Therefore, the scope of the disclosure is defined not by the detailed description, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents are to be construed as being included in the disclosure.