Patent ID: 12230498

DETAILED DESCRIPTION OF SOME EXAMPLE EMBODIMENTS

FIG.1is a schematic planar layout of a semiconductor device according some example embodiments of inventive concepts.

Referring toFIG.1, the semiconductor device according to some example embodiments of inventive concepts may include word lines WL extending in parallel in a first direction D1, bit lines BL extending in parallel in a second direction D2, active regions AR extending in a third direction D3while having an island shape when viewed in a plan view/top view, and landing pads LP each overlapping with opposite lateral ends of adjacent ones of the active regions AR. Directions D1and D2may be at right angles to one another; however, example embodiments are not limited thereto. Furthermore direction D3may be at an angle other than a right angle with respect to direction D1, for example at an angle of 70 degrees with respect to direction D1; however, example embodiments are not limited thereto. A plurality of active regions AR may collinearly extend in the third direction D3.

Two word lines WL may extend across one active region AR. For example, the word lines WL may be disposed such that each active region AR is divided, e.g. trisected, by corresponding ones of the word lines WL. One bit line BL may extend across one active region AR. The bit lines BL may be disposed to pass through central portions of the active regions AR, respectively. For example, the bit lines WL may be disposed such that each active region AR is divided, e.g. bisected, by a corresponding one of the bit lines WL.

FIG.2Ais a cross-sectional view of the semiconductor device according to some example embodiments of inventive concepts taken along line A-A′ ofFIG.1.FIG.2Bis a cross-sectional view of the semiconductor device according to some example embodiments of inventive concepts taken along line B-B′ ofFIG.1.FIG.2Cis a cross-sectional view of the semiconductor device according to some example embodiments of inventive concepts taken along line C-C′ ofFIG.1.FIG.3Ais an enlarged view of a region P1inFIG.2A.FIG.3Bis an enlarged view of a region P2inFIG.2A.

Referring toFIGS.1,2A,2B,2C,3A and3B, the semiconductor device may include a substrate10. The substrate10may be a semiconductor substrate made of, comprising, or consisting of a semiconductor material such as silicon, germanium, silicon-germanium, a Group III-V composite semiconductor material, etc. The substrate10may be doped, e.g. may be lightly doped with at least one of boron, phosphorus, or arsenic; however, example embodiments are not limited thereto.

An element isolation layer15may be disposed in/within the substrate10, and may define the active regions AR. The element isolation layer15may have the form of a dam filling a trench formed in the substrate10. The element isolation layer15may be or include a shallow trench isolation (STI) layer formed in the substrate10, and may be formed with a deposition process such as a high-density plasma (HDP) deposition process and/or a spin-on glass (SOG) process; however, example embodiments are not limited thereto.

The active regions AR may be two-dimensionally arranged in the first direction D1and the second direction D2. When viewed in a top view, the active regions AR may be arranged to have a zigzag form. Each of the active regions AR may have a bar shape/island shape, and may have a longer axis in the third direction D3that is a direction inclined from the first direction D1and the second direction D2. A first impurity region1aand a second impurity region1bmay be formed in each active region AR. The first and second impurity regions1aand1bmay be formed to have a specific (or, alternatively, predetermined) depth from the active region AR. The first impurity region1amay be formed at a central portion of the active region AR. The second impurity region1bmay be formed at each of opposite ends of the active region AR while being spaced apart from the first impurity region1a. The first and second impurity regions1bmay be doped with dopants having opposite conductivity types, respectively. For example, the first impurity region1amay be doped with phosphorous and/or arsenic, and the second impurity region1bmay be doped with boron; however, example embodiments are not limited thereto. Either or bother of a depth of impurities and a concentration of impurities may be the same as, or may be different between, the first impurity region1aand the second impurity region1b. The first impurity region1aand the second impurity region1bmay be formed with an implantation process such as an beamline ion implantation process and/or a plasma assisted doping (PLAD) implantation process; however, example embodiments are not limited thereto.

Word lines23(WL) may be disposed in the active regions AR of the substrate10. A pair of word lines23(WL) may extend across one active region AR in the first direction D1. The word lines23(WL) may be buried in the active region AR of the substrate10. For example, upper surfaces of the word lines23(WL) may be disposed at a lower level than an upper surface of the substrate10. Each word line23(WL) may include a conductive material. For example, each word line23(WL) may include at least one of undoped polysilicon, doped polysilicon, a metal material, or a metal silicide material.

A gate insulating film21may be disposed between the word lines23(WL) and the substrate10. The gate insulating film21may include, for example, silicon oxide. The gate insulating film21may be formed with a deposition process and/or an oxidation process, such as a thermal oxidation process and/or an in-situ steam generation (ISSG) process. A gate capping layer25may be disposed between the upper surfaces of the word lines23(WL) and the upper surface of the substrate10. An upper surface of the gate capping layer25may be disposed at the same level as the upper surface of the substrate10. A lower surface of the gate capping layer25may contact the upper surfaces of the word lines23(WL) and an upper surface of the gate insulating film21. For example, the gate capping layer25may include or consist of silicon oxide and/or silicon nitride.

An interlayer insulating layer17may be disposed on a surface of the substrate10. The interlayer insulating layer17may partially cover a surface of the element isolation layer15. The interlayer insulating layer17may be or include one or more of silicon oxide, silicon nitride, and combinations of various other insulating materials.

A contact recess R may be formed on each active region AR and the element isolation layer15adjacent to the active region AR. The contact recess R may be recessed inwards from the surface of the substrate10. A recess filler RF may be disposed in the contact recess R. The recess filler RF may include an insulating material such as at least one of silicon oxide or silicon nitride.

Bit line structures30may each include a bit line contact31, a bit line barrier layer33, a bit line35(BL), and a bit line capping layer37. Opposite side walls of the bit line contact31, the bit line barrier layer33, the bit line35(BL) and the bit line capping layer37may be vertically aligned. The bit line contact31may be disposed on the interlayer insulating layer17. A direct contact DC, which is a portion of the bit line contact31, may be disposed in the contact recess R of a corresponding one of the active regions AR, and may be connected, e.g. directly connected to the first impurity region1aof the corresponding active region AR. Accordingly, the bit line barrier layer33and the bit line35(BL) may be electrically connected through the bit line contact31. The bit line barrier layer33may include a barrier metal such as titanium nitride (TiN). The bit line35(BL) may include metal such as tungsten (W). The bit line capping layer27may include an oxidation-resistant insulating material having high density such as silicon nitride.

Storage node contacts BC may each be disposed between adjacent ones of the bit line structures30. Each storage node contact BC may extend along side walls of the corresponding bit line structures30in the second direction D2. When viewed in a top view, each storage node contact BC may be disposed between the corresponding word lines WL and the corresponding bit line structures30. For example, each storage node contact BC may include polysilicon doped with an impurity such as at least one of boron, phosphorus, or arsenic; alternative or additionally, the storage node contact BC may include a metal such as tungsten.

Each storage node contact BC may connect, e.g. directly contact the second impurity region1bof the corresponding active region AR. A lower end of the storage node contact BC may be disposed below the upper surface of the substrate10while being disposed above a lower surface of each of the corresponding bit line contacts31. The storage node contact BC may be insulated and/or isolated from the bit line contacts31by the corresponding recess filler RF. An upper surface of the storage node contact BC may be disposed below each of the corresponding bit lines35(BL).

A bit line spacer40may be disposed between each bit line structure30and each storage node contact BC disposed adjacent to each other. The bit line spacer40may extend in the second direction D2while covering a side wall of the bit line structure30. The bit line spacer40may include an inner spacer41, an air gap AG, and an outer spacer OS.

The inner spacer41may conformally cover a side surface of the corresponding bit line structure30. The inner spacer41may extend into the corresponding contact recess R, and may have a concave shape such as a U shape extending along a side wall of the corresponding bit line contact21and a surface of the contact recess R. The recess filler RF corresponding to the contact recess R may be disposed on the inner spacer41in the contact recess R.

The outer spacer OS may be disposed between the storage node contact BC and the inner spacer41. In some example embodiments, the outer spacer OS may include a seed pattern45a, a protective spacer47, and a main spacer49.

The main spacer49may be disposed between the inner spacer41and the storage node contact BC. An outer side surface of the main spacer49may contact the storage node contact BC. The main spacer49may be spaced apart from the inner spacer41. The main spacer49may be spaced apart from the interlayer insulating layer17and the recess filler RF. The thickness of the main spacer49may be greater than the thickness of the inner spacer41. In some example embodiments, the inner spacer41and the main spacer49may include, e.g. may consist of, the same material. For example, the inner spacer41and the main spacer49may include SiN.

The protective spacer47may be disposed on the seed pattern45awhile conformally covering inner side and bottom surfaces of the main spacer49. The protective spacer47may completely cover an upper surface of the seed pattern45a. The protective spacer47may define opposite sides of the air gap AG together with the inner spacer41. The protective spacer47may be or include a silicon thin film including carbon and/or nitrogen. In some example embodiments, the thickness of the protective spacer47may be 20 Å (2 nm) or less. For example, the thickness of the protective spacer47may be about 1 to 20 Å (0.1 nm to 2 nm). For example, the protective spacer47may include at least one of SiC, SiCN and SiBN.

The seed pattern45amay be interposed between the recess filler RF and the protective spacer47. The seed pattern45amay be interposed between the interlayer insulating layer17and the protective spacer47. One end of the seed pattern45amay be exposed through the air gap AG. The one end of the seed pattern45amay be aligned with an inner side surface of the protective spacer47. The other end of the seed pattern45amay contact the storage node contact BC. The seed pattern45amay be a silicon thin film not including carbon and nitrogen. The seed pattern45amay be or include a thin film and, as such, may have a thickness of 20 Å (2 nm) or less. For example, the thickness of the seed spacer45may be about 1 to 20 Å (0.1 nm to 2 nm).

The air gap AG may be disposed between the inner spacer41and the protective spacer47. For example, the width of the air gap AG may be defined by an outer side surface of the inner spacer41and the inner side surface of the protective spacer47. A lower end of the air gap AG may be defined by the recess filler RF and the inner spacer41. An upper end of the air gap AG may be defined by a pad isolation insulating layer60. In some example embodiments, the thickness of the air gap AG may be substantially equal to or greater than the thickness of the inner spacer41. The thickness of the air gap AG may be smaller than the thickness of the main spacer49. The air gap AG may be under pressure, e.g. may have a pressure less than that of atmospheric pressure; alternatively or additionally, the air gap AG may include a gas, such as clean, dry air (CDA).

The bit line spacer40may further include a capping pattern51. The capping pattern51may cover upper ends of the inner spacer41, the air gap AG and the outer spacer OS. The capping pattern51may define an upper end of a portion of the air gap AG. The capping pattern51may partially cover a side wall of the corresponding bit line capping layer37.

The semiconductor device may further include a buffer layer BF disposed on the storage node contact BC. For example, the buffer layer BF may include at least one of tungsten silicide (W—Si), titanium silicide (Ti—Si), tantalum silicide (Ta—Si), nickel silicide (Ni—Si), cobalt silicide (Co—Si), and other various metal silicides. In some example embodiments, the buffer layer BF may include a barrier layer such as titanium nitride (TiN).

A landing pad structure50may be disposed on the storage node contact BC and the buffer layer BF. The landing pad structure50may be electrically connected to the storage node contact BC. The landing pad structure50may include a landing pad barrier layer53and a landing pad55(LP). The landing pad barrier layer53may cover, e.g. may conformally cover a portion of an upper surface of the bit line structure BL, an upper surface of the buffer layer BF, and a surface of the capping pattern51. The landing pad barrier layer53may include a barrier metal such as titanium nitride (TiN). The landing pad55(LP) may be disposed on the landing pad barrier layer53in the form of a plug. The landing pad55(LP) may be made of, include, or consist of metal nitride such as titanium nitride and/or tantalum nitride and/or a metal material such as tungsten.

The pad isolation insulating layer60may be disposed between adjacent ones of landing pads55(LP). The pad isolation insulating layer60may include a first pad isolation insulating layer61and a second pad isolation insulating layer63. The first pad isolation insulating layer61may surround outer walls of the landing pads55(LP). The first pad isolating insulating layer61may physically and/or electrically isolate the landing pads55(LP) from one another. A lower end of the first pad isolation insulating layer61may contact an upper end of the bit line spacer40. A lower end of the first pad isolation insulating layer61may define an upper end of a portion of the air gap AG. The second pad isolation insulating layer63may be interposed between portions of the first pad isolation insulating layer61. For example, the first pad isolation insulating layer61may include SiN and may not include SiCN, whereas the second pad isolation insulating layer63may include SiCN and may not include SiN.

Referring toFIGS.2A,3A and3B, the air gap AG may have separate portions, e.g. may include an air spacer VT and an extension EX. The air spacer VT may be disposed on the recess filler RF and the inner spacer41while being disposed on the interlayer insulating layer17and the inner spacer41. The width of the air spacer VT may correspond to a distance between the protective spacer47and the inner spacer41. The extension EX may have a shape protruding downwards from a lower end of the air spacer VT. The extension EX may extend between the recess filler RF and the protective spacer47and between the recess filler RF and the seed pattern45a. The extension EX may extend between the inner spacer41and the protective spacer47and between the inner spacer41and the seed pattern45a. The width of the extension EX may be substantially equal to the thickness of the seed pattern45a.

FIG.4is a cross-sectional view of a semiconductor device according to some example embodiments of inventive concepts taken along line A-A′ ofFIG.1.

Referring toFIG.4, a bit line spacer40may include an inner spacer41, a capping spacer42, an air gap AG, and an outer spacer OS.

The capping spacer42may be disposed on the inner spacer41and a recess filler RF. The capping spacer42may conformally cover an inner side surface of the inner spacer41. The capping spacer42may define opposite sides of the air gap AG together with the seed space of the outer spacer OS. The capping spacer42may define a bottom surface of the air gap AG. A bottom surface of the capping spacer42may be disposed at a higher level than a bottom surface of the seed spacer45. In addition, the bottom surface of the capping spacer42may be disposed at a higher level than a bottom surface of the main spacer49.

The outer spacer OS may include the seed spacer45and the main spacer49. The seed spacer45may be disposed between the air gap AG and the main spacer49. The seed spacer45may be disposed between the capping spacer42and the main spacer49. The seed spacer45may cover, e.g. conformally cover inner side and bottom surfaces of the main spacer49. The seed spacer45may extend between the recess filler RF and the main spacer49. The seed spacer45may extend between an interlayer insulating layer17and the main spacer49.

The thickness of the capping spacer42may be substantially equal to the thickness of the seed spacer45; however, example embodiments are limited thereto. In some example embodiments, each of the seed spacer45and the capping spacer42may have a thickness of 20 Å (2 nm) or less. For example, each of the seed spacer45and the capping spacer42may have a thickness of 1 to 20 Å (0.1 nm to 2 nm). The capping spacer42and the seed spacer45may include the same material. For example, both the capping spacer42and the seed spacer45may include SiCN. In some example embodiments, the capping spacer42and the seed spacer45may include different materials, respectively. For example, the capping spacer42may include at least one of SiC and SiBN, whereas the seed spacer45may include SiCN and may not include either or both of SiC and SiBN. Alternatively, the capping spacer42may include SiCN, whereas the seed spacer45may include at least one of SiC and SiCN.

FIG.5is a cross-sectional view of a semiconductor device according to some example embodiments of inventive concepts taken along line A-A′ ofFIG.1.

Referring toFIG.5, an outer spacer OS may include a seed spacer45, a protective spacer47and a main spacer49. The protective spacer47may be disposed on the seed spacer45while being disposed between the seed spacer45and the main spacer49. The protective spacer47may cover, e.g. conformally cover inner side and bottom surfaces of the main spacer49. The seed spacer45may be spaced apart from the main spacer49by the protective spacer47. The protective spacer49may be spaced apart from an interlayer insulating layer17, a recess filler RF, and an inner spacer41. The seed spacer45and the protective spacer47may have substantially the same thickness; however, example embodiments are not limited thereto. In some example embodiments, each of the seed spacer45and the protective spacer47may have a thickness of 20 Å (2 nm) or less. For example, each of the seed spacer45and the protective spacer47may have a thickness of about 1 to 20 Å (0.1 nm to 2 nm). For example, each of the seed spacer45and the protective spacer47may include at least one of SiC, SiCN and SiBN, and may include or consist of the same material. In some example embodiments, any one of the seed spacer45and the protective spacer47may include SiCN.

Example embodiments are not limited to those described above, and, unless clear from context, none of the embodiments are mutually exclusive to one another. For example, some embodiments may include features described with reference to one figure, and also features described with reference to another figure.

FIGS.6to22are sectional views explaining a method for forming a semiconductor device in accordance with some example embodiments of inventive concepts.

Referring toFIG.6, the method may include forming an element isolation layer15in a substrate10, forming an interlayer insulating layer17on the substrate10, and forming a contact recess R.

Formation of the element isolation layer15may include forming trenches in the substrate, and filling the trenches with an insulating material, such as oxide such as high density plasma (HDP) oxide and/or spin-on glass (SOG) oxide; however, example embodiments are not limited thereto. An active region AR may be defined by the element isolation layer15.

Formation of the interlayer insulating layer17may include forming an insulating layer on a surface of the substrate10formed with the element isolation layer15. The interlayer insulating layer17may cover an upper surface of the substrate10and an upper surface of the element isolation layer15. The interlayer insulating layer17may expose a portion of the upper surface of the substrate10and a portion of the upper surface of the element isolation layer15. The interlayer insulating layer17may include at least one of silicon oxide, silicon nitride and various insulating materials. The interlayer insulating layer17may be formed with a deposition process such as a chemical vapor deposition (CVD) process; however, example embodiments are not limited thereto.

Formation of the contact recess R may include recessing an upper portion of a first impurity region1aof the substrate10using a selective etch process such as a selective wet etch process and/or a selective dry etch process. For example, the contact recess R may be formed as a part of an upper portion of the first impurity region1aand a part of an upper portion of the element isolation layer15, which are exposed by the interlayer insulating layer17.

Referring toFIG.7, the method may include forming bit line structures30. Each bit line structure30may include a bit line contact31, a bit line barrier layer33, a bit line35(BL), and a bit line capping layer37.

Formation of the bit line structure30may include forming a bit line contact material layer, a bit line barrier material layer, a bit line material layer, and a bit line capping material layer, and performing a patterning process. Each of the bit line contact material layer, the bit line barrier material layer, the bit line material layer, and the bit line capping material layer may be formed with a CVD process and/or a physical vapor deposition (PVD) process; however, example embodiments are not limited thereto. The patterning process may be or include a single-patterning process, or a double-patterning process, or a triple or quadruple patterning process; however, example embodiments are not limited thereto.

For example, the bit line contact31may include a conductor such as doped polycrystalline silicon. The bit line barrier layer33may include a barrier metal such as titanium nitride (TiN). The bit line35(BL) may include metal such as tungsten. The bit line capping layer37may include an oxidation-resistant insulating material having high density such as silicon nitride.

The bit line contact31on the first impurity region1amay extend into the contact recess R such that the bit line contact31may contact the first impurity region1aso as to be electrically connected thereto.

Referring toFIG.8, the method may include forming a preliminary inner spacer41pand a recess filler RF. The preliminary inner spacer41pmay be formed to partially fill the contact recess R while conformally covering the bit line structure30. Formation of the recess filler RF may include forming an insulating layer conformally covering the preliminary inner spacer41p, and anisotropically etching the insulating layer. The insulating layer may be formed with a CVD process, and the insulating layer may be etched with a dry etching process; however, example embodiments are not limited thereto. The recess filler RF may be formed to fill the contact recess R while being coplanar with the interlayer insulating layer17. For example, the preliminary inner spacer41pmay include silicon nitride, whereas the recess filler RF may include silicon oxide, silicon nitride or various insulating materials.

Referring toFIG.9, the method may include forming a preliminary sacrificial spacer43p. The preliminary sacrificial spacer43pmay be formed to conformally cover the preliminary inner spacer41p. In some example embodiments, the preliminary sacrificial spacer43pmay be formed to have a thickness substantially equal to or slightly greater than the thickness of the preliminary inner spacer41p. For example, the preliminary sacrificial spacer43pmay include silicon oxide.

Referring toFIG.10, the method may include forming an inner spacer41and a sacrificial spacer43. The inner spacer41and the sacrificial spacer43may be formed on each outer side wall, e.g. a first a second side wall, of the bit line structure30through anisotropic etching of the preliminary inner spacer41pand the preliminary sacrificial spacer43p.

Referring toFIG.11, the method may include forming a seed layer45pon the sacrificial spacer43. The seed layer45pmay conformally cover an upper surface of the interlayer insulating layer17, a surface of the inner spacer41, a surface of the recess filler RF, a surface of the sacrificial spacer43and a surface of the bit line capping layer37. In some example embodiments, the seed layer45pmay be formed through an atomic layer deposition (ALD) process, using a silicon source material. The seed layer45pmay be formed into a silicon film having the form of a thin film without including either or both of carbon or nitrogen. The seed layer45pmay be formed to have a thickness of 20 Å (2 nm) or less. For example, the seed layer45pmay be formed to have a thickness of 1 to 20 Å (0.1 nm to 2 nm). For example, the silicon source material may be or include a halogen-substituted silane-based silicon precursor such as at least one of hexachlorodisilane (HCD), dichlorosilane (DCS), disilane (DS), trichlorosilane (TCS: SiCl3H), etc. Alternatively or additionally, the silicon source material may be a silane-based silicon source material not including carbon or nitrogen, as expressed by the following Chemical Formula 1:
SinH2(N−1)+4[Chemical Formula 1]

Referring toFIG.12, the method may further include forming a protective layer47pon the seed layer45p. The protective layer47pmay conformally cover a surface of the seed layer45p. For example, the protective layer47pmay include at least one of SiC, SiBN, or SiCN. The protective layer47pmay take the form of a thin film through an atomic layer deposition (ALD) process, using at least one of a silicon source material, a nitrogen source material, a carbon source material and/or a boron source material. The protective layer47pmay be formed to have a thickness of 20 Å (2 nm) or less. For example, the protective layer47pmay be formed to have a thickness of about 1 to 20 Å (0.1 nm to 2 nm). For example, the protective layer47p, which includes SiC, may be formed through repeated execution of a cycle including introduction of a silicon source material and introduction of a carbon source material.

For example, as the silicon source material, the same material as the silicon source material used in formation of the seed layer45pmay be used. The nitrogen source material may be at least one of N2, NH3, hydrazine (N2H4), plasma N2, remote plasma N2, or a combination thereof. The carbon source material may be an organic material such as C2H4. The boron source material may be a halogen-substituted borane-based boron precursor such as diborane (B2H6).

The protective layer47pmay cover the seed layer45p, thereby preventing, or reducing the likelihood of, intermixing between the seed layer45pand a preliminary main spacer49pwhich will be subsequently formed. In addition, as the protective layer47pis not formed on the sacrificial spacer43, but is formed on the seed layer45p, an increase in density may be achieved through an improvement in incubation, e.g. in incubation of the ALD process. As a result, the effect of preventing or reducing the likelihood of intermixing between the seed layer45pand the preliminary main spacer49pmay be further enhanced.

Referring toFIG.13, the method may include forming the preliminary main spacer49pon the protective layer47p. The preliminary main spacer49pmay be formed to conformally cover an upper surface of the protective layer47p. The preliminary main spacer49pmay be formed to have a thickness greater than either or both of the thickness of the inner spacer41and the thickness of the sacrificial spacer43, or greater than a total thickness of the inner spacer41and the sacrificial spacer43. The preliminary main spacer49pmay include, e.g. may consist of, the same material as the inner spacer41. For example, the preliminary main spacer49pmay include SiN. The preliminary main spacer49pmay be formed through repeated execution of a second cycle including introduction of a silicon source material, purge, and introduction of a nitrogen source material. Since the preliminary main spacer49pis formed on the protective layer47p, it may be possible to prevent or reduce the likelihood of formation of a transition layer caused by intermixing between the seed layer45pand the preliminary main spacer49pand intermixing between the preliminary main spacer49pand the sacrificial spacer43. As a result, even when the thickness of the main spacer49is reduced in order to reduce the total thickness of the outer spacer OS, for reduction in size, e.g. for miniaturization or shrink of the resultant semiconductor device, it may be possible to avoid or reduce the likelihood of a phenomenon in which the outer spacer OS bursts or volcanoes due to a cleaning process (described later) for forming an air gap AG.

Detailed contents of the processes of forming the seed layer45p, the protective layer47pand the preliminary main spacer49pdescribed in conjunction withFIGS.11to13will be given later in conjunction withFIGS.31to33.

Referring toFIG.14, the method may include forming a seed spacer45, a protective spacer47, and a main spacer49while forming a contact hole CH. The seed spacer45and the protective spacer47may be formed on a side wall of the sacrificial spacer43, and the main spacer49may be formed on the protective spacer47through anisotropic etching of the seed layer45p, the protective layer47pand the preliminary main spacer49p. Thereafter, the interlayer insulating layer17exposed between the main spacers49respectively disposed at opposite sides of the bit line structure30may be etched, e.g. etched with a wet and/or dry etching process, thereby exposing the substrate10. An insulating film (not shown) may be formed on an exposed surface of the substrate10, and may then be patterned, thereby forming a contact hole CH.

The method may include forming a storage node contact BC and a buffer layer BF. The storage node contact BC may be formed in the contact hole CH by forming a storage contact material layer over the entire surface of or at least the entire upper surface of the substrate10, and then partially recessing the storage contact material layer through an etch-back process (e.g. a blanket etching process). The buffer layer BF may be formed on the storage node contact BC. The buffer layer BF may include a silicide layer.

Referring toFIG.15, the method may include anisotropically etching the bit line spacer40, thereby removing an upper portion of the bit line spacer40. For example, the method may include anisotropically etching the inner spacer41, the sacrificial spacer43, the seed spacer45, the protective spacer47and the main spacer49, thereby removing upper portions thereof. The levels of upper ends of, e.g. of upper ends of each of, the inner spacer41, the sacrificial spacer43, the seed spacer45, the protective spacer47, and the main spacer49may be lower than the level of the bit line capping layer37. As a result, upper side walls of the bit line capping layer37may be exposed. The levels of upper ends of, e.g. of upper ends of each of, the inner spacer41, the sacrificial spacer43, the seed spacer45, the protective spacer47and the main spacer49may be higher than the level of an upper surface of the buffer layer BF.

Referring toFIG.16, the method may include forming a capping pattern51. Formation of the capping pattern51may include forming a capping spacer material over the entire surface of or at least the entire upper surface of the substrate10, and performing an etch-back process (e.g. a blanket etching process), thereby forming the capping pattern51. The capping pattern51may cover exposed surfaces of upper ends of the inner spacer41, the sacrificial spacer43, the seed spacer45, the protective spacer47and the main spacer49. In addition, the capping pattern51may cover exposed side surfaces of the bit line capping layer37. For example, the capping pattern51may include at least one of SiN and SiBN.

Referring toFIG.17, the method may include forming a landing pad barrier material layer53pand a landing pad material layer55p. Formation of the landing pad barrier material layer53pmay include conformally forming a barrier metal such as titanium nitride (TiN) over the entire surface of the resultant structure. Formation of the landing pad material layer55pmay include forming a conductive material on the landing pad barrier material layer53pto completely fill a space between adjacent ones of the bit line structures30. For example, the landing pad material layer55pmay include a material such as tungsten (W).

Referring toFIG.18, the method may include forming first pad isolation trenches T1through an anisotropic etching process such as a dry etching process. As the first pad isolation trenches T1are formed, the landing pad barrier material layer53pand the landing pad material layer55pmay be isolated from each other and, as such, landing pad structures50may be formed. Each landing pad structure50may include a landing pad barrier layer53and a landing pad55. The landing pad structures50may be physically isolated from one another, and may be electrically insulated from one another. Referring toFIG.1, each first pad isolation trench T1may have the form of a trench defining a landing pad55.

Referring toFIG.19, the method may include forming second pad isolation trenches T2through an anisotropic etching process such as a dry etching process using different, process parameters than the etching process used in forming the first pad isolation trenches T1. Each second pad isolation trench T2may be formed as a portion of the landing pad structure50exposed through each first pad solation trench T1is recessed to be concave. The upper ends of the inner spacer41, the sacrificial spacer43, the seed spacer45, and the protective spacer47may be exposed through the corresponding second pad isolation trench T2. The anisotropic etching process for forming the second pad isolation trenches T2may have higher anisotropic etching characteristics than the anisotropic etching process for forming the first pad isolation trenches T1, e.g. may include different process parameters.

Referring toFIG.20, the method may include removing the sacrificial spacer43and the seed spacer45through the corresponding second pad isolation trench T2, thereby forming an air gap AG. The air gap AG may be formed between the inner spacer41and the protective spacer47corresponding to the second pad isolation trench T2. The air gap AG may reduce parasitic capacitance between the corresponding bit line structure30and the corresponding storage node contact BC, thereby reducing resistive-capacitive delay of electrical signals. For example, the sacrificial spacer43and the seed spacer45may be etched by a cleaning process such as a wet cleaning process. The cleaning process may include use of an etchant such as buffered hydrogen fluoride and/or hot phosphoric acid and/or ammonia; however, example embodiments are not limited thereto. As the seed spacer45is removed together with the sacrificial spacer43, the air gap AG may extend between the recess filler RF and the protective spacer47. A portion of the seed spacer45disposed under the protective spacer47may remain without being removed by the cleaning process and, as such, a seed pattern45amay be formed. As described above, the seed spacer45may achieve an increase in density through an improvement in incubation, and may secure an improved, e.g. a maximum, width of the air gap AG in accordance with subsequent removal thereof, thereby reducing, e g minimizing parasitic capacitance between the bit line structure30and the storage node contact BC.

Referring toFIG.21, the method may include forming a first pad isolation insulator61ppartially filling the first pad isolation trenches T1and the second pad isolation trenches T2. The first pad isolation insulator61pmay seal an opening of the upper end of the air gap AG. The second pad isolation trenches T2may be completely filled with the first pad isolation insulator61p, whereas a residual space may partially remain in each first pad isolation trench T1. For example, the first pad isolation insulator61pmay include silicon carbonitride. At this time, the air gap AG may be sealed, and may be under vacuum and/or may have a gas, such as clean, dry air, therebetween.

Referring toFIG.22, the method may include forming a second pad isolation insulator63pon the first pad isolation insulator61p. The second pad isolation insulator63pmay completely fill the residual space of each first pad isolation trench T1. The second pad isolation insulator63pmay include silicon nitride. The second pad isolation insulator63pmay include the same, or different, material than that of the first pad isolation insulator61p.

Again referring toFIG.2A, after formation of the first pad isolation insulator61pand the second pad isolation insulator63p, a planarization process such as a chemical mechanical polishing (CMP) process and/or an etch-back process may be performed to expose an upper surface of each landing pad55. In accordance with the planarization process, upper portions of the first pad isolation insulator61pand the second pad isolation insulator63pmay be removed and, as such, a first pad isolation insulating layer61and a second pad isolation insulating layer63may be formed.

FIG.23is a sectional view explaining a method for forming a semiconductor device in accordance with some example embodiments of inventive concepts.

First, referring toFIGS.11and12, in some example embodiments, in the method, a seed layer45pmay be formed using a silicon thin film including carbon, including carbon and nitrogen, or including boron and nitrogen, differently from the above-described embodiment. For example, the seed layer45pmay be or include SiC, SiCN, or SiBN. In addition, a protective layer47pbe formed to include any one of SiC, SiCN and SiBN under the condition that the material of the protective layer47pis different from that of the seed layer45p. Although only the seed layer45pand the protective layer47pare shown inFIG.12, a thin film may be additionally formed on the protective layer47in some example embodiments. For example, the additionally-formed thin film may include any or at least one of SiC, SiCN and SiBN under the condition that the material of the thin film is different from that of the protective layer47p. The material of the thin film may be identical to or different from that of the seed layer45p.

Thereafter, the same processes as the processes described in conjunction withFIGS.13to19may be performed. Subsequently, referring toFIG.23, the method may include removing a sacrificial spacer43through each second pad isolation trench T2, thereby forming an air gap AG. The air gap AG may be formed between an inner spacer41and a seed spacer45. Since the seed spacer45includes a material having an etch selectivity with respect to the sacrificial spacer43, the seed spacer45may not be removed during formation of the air gap AG. Both the seed spacer45and the protective spacer47may function to protect a main spacer49from a cleaning material of a cleaning process for removing the sacrificial spacer43. Since the main spacer49is protected or at least partially protected by the seed spacer45and the protective spacer47, as described above, a burst phenomenon of the main spacer49may be prevented or reduced in likelihood of occurrence even when the thickness of the main spacer49is reduced. There may be a reduction in likelihood of pin hole formation. Accordingly, through a reduction in the total thickness of an outer spacer OS, it may be possible to further increase the width of the air gap AG and to reduce parasitic capacitance between a bit line structure30and a storage node contact BC.

FIGS.24to30are sectional views explaining a method for forming a semiconductor device in accordance with some example embodiments of inventive concepts.

Referring toFIG.24, the method may further include forming a capping layer42pafter formation of a preliminary inner spacer41pand a recess filler RF as inFIG.8. The capping layer42pmay be formed to cover, e.g. conformally cover a surface of the preliminary inner spacer41pand a surface of the recess filler RF. The thickness of the capping layer42pmay be smaller than the thickness of the inner spacer41. For example, the capping layer42pmay include SiCN. The method of forming the capping layer42pmay be the same as the method of forming the protective layer47p, as described in conjunction withFIG.12. For example, the capping layer42pmay be formed in the form of a thin film through an ALD process, using at least one of a silicon source material, a nitrogen source material, a carbon source material and/or a boron source material. The capping layer42pmay be formed to have a thickness of about 1 to 20 Å (0.1 nm to 2 nm). The capping layer42pmay prevent or reduce the likelihood of intermixing between a preliminary sacrificial spacer43pand an inner spacer41which will be subsequently formed.

Referring toFIG.25, the method may include forming the preliminary sacrificial spacer43pon the capping layer42p. The preliminary sacrificial spacer43pmay be formed to cover, e.g. conformally cover a surface of the capping layer42p. The preliminary sacrificial spacer43pmay be formed to have a thickness substantially equal to or slightly greater than the thickness of the preliminary inner spacer41p. For example, the preliminary sacrificial spacer43pmay include silicon oxide.

Referring toFIG.26, the method may include forming a capping spacer42and a sacrificial spacer43. The capping spacer42and the sacrificial spacer43may be formed through anisotropic etching of the capping layer42pand the sacrificial spacer43.

The method may include forming a seed layer45pon the sacrificial spacer43. The seed layer45pmay cover an upper surface of an interlayer insulating layer17and a surface of the sacrificial spacer43. In addition, the seed layer45pmay cover, e.g. conformally cover opposite ends of the inner spacer41, opposite ends of the capping layer42p, and an upper surface of the capping layer42p.

Referring toFIG.27, the method may include forming a preliminary main spacer49pon the capping layer42p. The preliminary main spacer49pmay cover, e.g. conformally cover a surface of the capping layer42p. The preliminary main spacer49pmay be formed to have a thickness greater than the thickness of the inner spacer41and the thickness of the sacrificial spacer43. For example, the preliminary main spacer49pmay include silicon nitride. The preliminary main spacer49pmay include, e.g. may consist of the same material as the inner spacer41.

Referring toFIG.28, the method may include forming a seed spacer45and a main spacer49while forming a contact hole CH. The seed spacer45and the main spacer49may be formed on each side wall of the sacrificial spacer43through anisotropic etching of the seed layer45pand the preliminary main spacer49p. Thereafter, the interlayer insulating layer17exposed between the main spacer49may be etched, thereby exposing a substrate10. Formation of the contact hole CH may be achieved by forming an insulating film (not shown) on an exposed surface of the substrate10, and patterning the insulating film. Thereafter, the method may include forming a storage node contact BC and a buffer layer BF, as described in conjunction withFIG.14. Subsequently, the method may include anisotropically etching a bit line spacer40, thereby removing an upper portion of the bit line spacer40.

Referring toFIGS.29and30, the method may include forming a first pad isolation trench T1and forming a second pad isolation trench T2. Thereafter, the method may include removing the sacrificial spacer43through the second pad isolation trench T2, and forming an air gap AG. The air gap AG may be formed between the capping spacer42and the seed spacer45. For example, the sacrificial spacer43may be etched by a cleaning process.

Again referring toFIG.4, subsequently, the method may include forming a first pad isolation insulating layer61and a second pad isolation insulating layer62filling the first pad isolation trench T1and the second pad isolation trench T2.

FIG.31is a flowchart explaining a method for forming an outer spacer in accordance with some example embodiments of inventive concepts.

Referring toFIG.31, a substrate is loaded into a reaction space such as a chamber (S100), and source materials or precursors may be supplied to an interior of the reaction space in order to form an outer spacer on the substrate (S200). The source materials or precursors may be supplied through a shower-head (not shown); however, example embodiments are not limited thereto. When an outer spacer having a desired thickness is formed, the substrate may be unloaded from the chamber (S300). The thickness of the outer spacer may be measured in-situ within the chamber; however, example embodiments are not limited thereto.

The method of forming the outer spacer on the substrate in operation S200may be carried out or performed using any method known to a person of ordinary skill in the art. In some example embodiments, the method of forming the outer spacer may be carried out through atomic layer deposition (ALD). In particular, a method of forming a low-k dielectric film may be carried out through plasma enhanced ALD (PEALD). However, inventive concepts are not limited to such methods. The following description will be given in conjunction with the case in which the outer spacer is formed on the substrate through PEALD.

FIG.32is a process flowchart explaining a method for forming a seed layer, a protective layer, and a preliminary main spacer for formation of an outer spacer in accordance with some example embodiments of inventive concepts.FIGS.33and34are process flowcharts explaining a method for forming a protective layer ofFIG.32.

Referring toFIG.32, the method may include loading a semiconductor substrate into a chamber of semiconductor equipment (S10) such as a tool used in PEALD, depositing a seed layer (S20), supplying a purge gas (S30), depositing a protective layer on the seed layer (S40), and depositing a silicon nitride film (S50). The operations may be carried out in the same semiconductor equipment without vacuum interruption; e.g. the chamber may be under vacuum throughout the operations such as S20-S50.

The method may include loading a semiconductor substrate into a chamber of semiconductor equipment (S10). The semiconductor substrate, which is loaded into the chamber, may include structures and/or configurations such as a bit line structure30, an inner spacer41and a sacrificial spacer43formed through processes ofFIGS.6to10. For example, the prepared semiconductor substrate may be or include product formed with a sacrificial spacer45which is a silicon oxide film. The silicon oxide film may be on an upper surface of the substrate10.

The method may include forming a seed layer (“45p” inFIG.11) through execution of a seed layer deposition process for the prepared semiconductor substrate (S20). The seed layer deposition process may be or correspond to a deposition process using a silicon source material, and may be performed at a temperature of about 600 to 700° C. The silicon source material may or include be a halogen-substituted silane-based silicon precursor such as at least one of hexachlorodisilane (HCD), dichlorosilane (DCS), disilane (DS), trichlorosilane (TCS: SiCl3H), etc. Alternatively, the silicon source material may be or include a silane-based silicon source material not including carbon or nitrogen, as expressed by the following Chemical Formula 1:
SinH2(N−1)+4[Chemical Formula 1]

The method may include performing a process for supplying a purge gas to the seed layer (“45p” inFIG.11) when a film formed through a silicon deposition process has a specific (or, alternatively, predetermined) thickness (S30). In some example embodiments, the purge gas may be hydrogen gas, e.g. H2. For example, when hexachlorodisilane (HCD) is supplied as a silicon source material in operation S20, a chemical bond of two silicon atoms of the hexachlorodisilane (HCD) may be dissociated and, as such, the silicon atoms may be bonded to a substrate. For example, two —SiCl3bonds may be formed on the substrate. A chloro group has a large size and, as such, may interfere with adsorption of other molecules, for example, a carbon source, which is subsequently suppled, on to the substrate or reaction of the carbon source with silicon due to steric hindrance thereof. Accordingly, when hydrogen gas is supplied immediately after supply of a silicon source, hydrogen may substitute for chloro groups. As a result, the size of atoms bonded to a silane group may be reduced and, as such, steric hindrance may be reduced in size or minimized, and a carbon source material, which is subsequently supplied, may more smoothly react with silicon atoms. For example, by the above-described purge process, an enhancement in incubation may be achieved during subsequent deposition of a protective layer47p, and an increase in density of the seed layer (“45p” inFIG.11) and the protective layer47pmay be achieved.

Subsequently, the method may include depositing the protective layer47pon the seed layer45p(S40). Referring toFIG.33, the protective layer deposition process may include a single cycle of depositing a base source material (S41a) and depositing a silicon source material (S42a) in a sequential manner. The cycle may be repeated until the protective layer47pis formed to a desired thickness. Referring toFIG.34, the protective layer deposition process may further include depositing a silicon source material (S42b), and subsequently depositing a nitrogen source material (S43b). For example, the protective layer deposition process may include a single cycle of depositing a base source material (S41b), depositing a silicon source material (S42b) and depositing a nitrogen source material (S43b) in a sequential manner. In this case, the cycle may also be repeated until the protective layer is formed to a desired thickness.

The base source material may include a carbon source material and/or a boron source material. For example, the carbon source material may be or include an organic material such as C2H4. The boron source material may be or include a halogen-substituted borane-based boron precursor such as diborane (B2H6).

In some example embodiments, when the protective layer47pis SiC, a cycle of supplying a carbon source material to the seed layer45pand supplying a silicon source material to the seed layer45pmay be repeated to form the protective layer47p. The cycle may be repeated until the formed film has a specific (or, alternatively, predetermined) thickness.

In some example embodiments, when the protective layer47pis SiCN, a cycle of supplying a carbon source material to the seed layer45p, supplying a nitrogen source material and supplying a silicon source material to the seed layer45pmay be repeated to form the protective layer47p.

In some example embodiments, when the protective layer47pis SiBN, a cycle of supplying a boron source material to the seed layer45p, supplying a nitrogen source material and supplying a silicon source material to the seed layer45pmay be repeated to form the protective layer47p.

Subsequently, the method may include depositing, on the protective layer47p, a preliminary main spacer (“49p” inFIG.13) which is a silicon nitride film (S50). Deposition of the silicon nitride film may be achieved through repetition of a cycle including supplying a silicon source material to the protective layer47pand supplying a nitride source material to the protective layer47p.

In accordance with some example embodiments of inventive concepts, intermixing between a sacrificial spacer, which is an oxide, and a main spacer, which is a nitride, may be prevented or reduced in likelihood of occurrence by a seed layer and a protective layer and, as such, formation of a transition layer may be prevented or reduced in likelihood of occurrence. Accordingly, it may be possible to form an air gap without occurrence, or with reduced likelihood of occurrence, of a burst phenomenon thereof while minimizing the thickness of the main spacer. Alternatively or additionally, the seed layer is removed together with a sacrificial spacer and, as such, a large or maximum air gap margin may be secured. Accordingly, parasitic capacitance between a bit line and a storage node contact may be reduced or minimized.

While the embodiments of inventive concepts have been described with reference to the accompanying drawings, it should be understood by those of ordinary skill in the art that various transitions may be made without departing from the scope of inventive concepts and without changing essential features thereof. Therefore, the above-described embodiments should be considered in a descriptive sense only and not for purposes of limitation.