Patent ID: 12243893

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.

Terms used herein are only used to describe the specific embodiments, which are not used to limit the claims appended herewith. For example, unless limited otherwise, the term “one” or “the” of the single form may also represent the plural form. The terms such as “first” and “second” are used for describing various devices, areas and layers, etc., though such terms are only used for distinguishing one device, one area or one layer from another device, another area or another layer. Therefore, the first area can also be referred to as the second area without departing from the spirit of the claimed subject matter, and the others are deduced by analogy. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

A high absorption structure in a CMOS image sensor is a surface topography for increasing optical scattering and refraction, so as to enhance the optical injection efficiency, thereby increasing the absorption efficiency of the semiconductor layer. In different CMOS image sensor technology generation, raw materials with different orientations may be used, and thus the design and the end result of the CMOS image sensor may be changed correspondingly.

Embodiments of the present disclosure are directed to providing a semiconductor device and a method for manufacturing the semiconductor device, in which a semiconductor layer on a device layer has a surface having a lattice plane which is tilted with respect to a basal plane. The basal plane is the plane perpendicular to the principal axis in a crystal system, such as one of a { 100} family of planes of a cubic system. For example, the lattice plane may be one of a {110} family of planes of a cubic system or one of a {111} family of planes of the cubic system. Thus, when the semiconductor layer having the surface with the lattice plane, which is one of the {110} family of planes of the cubic system or one of the {111} family of planes of the cubic system, is used, an etching process performed on the surface of the semiconductor layer forms various pyramid pit portions or prism pit portions on the surface of the semiconductor layer, such that most of light may be scattered and refracted by the pit portions on the surface of the semiconductor layer, and then may enter the semiconductor layer and be absorbed by the semiconductor layer. Accordingly, quantum efficiency of the semiconductor device is significantly enhanced due to low reflection and high absorption.

FIG.1is schematic cross-sectional view of a semiconductor device in accordance with various embodiments. In some embodiments, a semiconductor device100is a CMOS image sensor device, which may be operated for sensing incident light110. The semiconductor device100has a front side100aand a back side100b. In some embodiments, the semiconductor device100is a BSI CMOS image sensor device, which is operated to sense the incident light110projected from its back side100b.

In some examples, as shown inFIG.1, the semiconductor device100includes a carrier120, a device layer130, and a semiconductor layer140. When the semiconductor device100is a general image sensor, in which light-sensing pixels and logic device are formed in the same wafer, the carrier120is a support base of the wafer for a flip chip process and/or a thinning process. When the semiconductor device100is a stacking image sensor, in which light-sensing pixels and logic devices are respectively formed on different wafers, the carrier120is a logic wafer on which the logic devices are formed.

The device layer130is disposed on the carrier120. The device layer130includes various devices132, such as transistors. In some exemplary examples, the semiconductor device100optionally includes a passivation layer150. The passivation layer150is disposed on the carrier120. The passivation layer150may be suitable for bonding the device layer130to the carrier120. The passivation layer150may be a dielectric film, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or any combinations thereof. Optionally, the semiconductor device100may include at least one inter-metal dielectric layer160. The inter-metal dielectric layer160is disposed between the passivation layer150and the device layer130. The inter-metal dielectric layer160includes conductive lines, which are electrically connected to the devices132of the device layer130. The inter-metal dielectric layer160includes a dielectric film, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or any combinations thereof.

Referring toFIG.1again, the semiconductor layer140is disposed on the device layer130. The semiconductor layer140includes various light-sensing regions142. Each of the light-sensing regions142may include a photodiode. The semiconductor layer140has a first surface140aand a second surface140bopposite to the first surface140a, and the first surface140ais adjacent to the device layer130. The second surface140bof the semiconductor layer140has a lattice plane which is tilted with respect to the basal plane. In some embodiments, the lattice plane of the second surface140bof the semiconductor layer140is one of a {110} family of planes of a cubic system or one of a {111} family of planes of the cubic system. The semiconductor layer140may include a group IV material, a group IV material compound, or a group III-V material compound. For example, the group IV material and the group IV material compound may include Si, Ge, or SiGe. The group III-V material compound may include GaN, GaAs, InAs, InGaN, or InGaAs.

In some examples, as shown inFIG.1, the semiconductor device100may optionally include various isolation structures170. The isolation structures170are disposed in the semiconductor layer140to define various pixel regions146. Each of the pixel regions146may include one of the light-sensing regions142. In some exemplary examples, each of the isolation structures170is a deep trench isolation (DTI) structure extending from the second surface140bof the semiconductor layer140to a predetermined depth of the semiconductor layer140, so as to isolate two adjacent ones of the light-sensing regions142. For example, each of the pixel regions146may be a rectangular region surrounded by the isolation structures170. In certain examples, portions the isolation structures170extend to cover the second surface140bof the semiconductor layer140. The isolation structures170include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or any combinations thereof.

The semiconductor layer140has various pit portions144arranged on the second surface140b. For example, the pit portions144may be pyramid pit portions or prism pit portions. In some examples, in each of the pixel regions146, the pit portions144are regularly arranged on the second surface140b. Any two adjacent ones of the pit portions144may adjoin to each other. In some examples, any two adjacent ones of the pit portions144are separated from each other. In addition, shapes of the pit portions144of the semiconductor layer140are substantially the same. For different semiconductor layers, pit portions on these semiconductor layers may have different shapes.

Referring toFIG.2AandFIG.2B,FIG.2Ais an enlarged schematic top view of a semiconductor layer and isolation structures in a pixel region of a semiconductor device in accordance with various embodiments, andFIG.2Bis an enlarged schematic three-dimensional view of a pyramid pit portion of a semiconductor layer of a semiconductor device in accordance with various embodiments. A second surface140b′ of a semiconductor layer140′ has a lattice plane, in which the lattice plane of the second surface140b′ of a semiconductor layer140′ is one of a 11101 family of planes of a cubic system, and pit portions144aare square based pyramid pit portions. The pit portions144aare regularly arranged on the second surface140b′. For example, the pit portions144amay be arranged in an array. In the examples, four edges145a,145b,145c, and145dof a base145of each of the pit portions144aare non-parallel with four edges146a,146b,146c, and146dof the pixel region146.

Referring toFIG.3AandFIG.3B,FIG.3Ais an enlarged schematic top view of a semiconductor layer and isolation structures in a pixel region of a semiconductor device in accordance with various embodiments, andFIG.3Bis an enlarged schematic three-dimensional view of a pyramid pit portion of a semiconductor layer of a semiconductor device in accordance with various embodiments. A second surface140b″ of a semiconductor layer140″ has a lattice plane, in which the lattice plane of the second surface140b″ of the semiconductor layer140″ is one of a {111} family of planes of a cubic system, and pit portions144bare triangular based pyramid pit portions. The pit portions144bare regularly arranged on the second surface140b″. For example, the pit portions144bmay be arranged in an array. In the examples, one edge147bof a base147of each of the pit portions144bis substantially parallel to two opposite edges146aand146cof the pixel region146, and the other two edges147aand147cof the base147of each of the pit portions144bare non-parallel with the two opposite edges146aand146cand the other two opposite edges146band146dof the pixel region146.

Referring toFIG.4AandFIG.4B,FIG.4Ais an enlarged schematic top view of a semiconductor layer and isolation structures in a pixel region of a semiconductor device in accordance with various embodiments, andFIG.4Bis an enlarged schematic three-dimensional view of a pyramid pit portion of a semiconductor layer of a semiconductor device in accordance with various embodiments. A second surface141′ of a semiconductor layer141has a lattice plane, in which the lattice plane of the second surface141′ of the semiconductor layer141is one of a {110} family of planes of a cubic system, and pit portions144care square based prism pit portion. The pit portions144care regularly arranged on the second surface141′. For example, the pit portions144cmay be arranged in an array. In the examples, two edges149aand149cof a base149of each of the pit portions144care substantially parallel with two edges146aand146cof the pixel region146, and the other two edges149band149dof the base149of each of the pit portions144care substantially parallel with two edges146band146dof the pixel region146.

In order to increase the rate and the resolution of the semiconductor device100, the semiconductor layer140having the second surface140bhas the lattice plane, which is tilted with respect to the basal plane, is used. Thus, an etching process performed on the second surface140bof the semiconductor layer140forms various pit portions144on the second surface140bof the semiconductor layer140, such that most of the incident light110is scattered and refracted by the pit portions144, and then enters the semiconductor layer140and is absorbed by the semiconductor layer140. Accordingly, quantum efficiency of the semiconductor device100is significantly enhanced due to low reflection and high absorption, and the rate and the resolution of the semiconductor device100are increased.

In some examples, as shown inFIG.1, the semiconductor device100optionally includes a buffer layer180. The buffer layer180overlies and covers the second surface140bof the semiconductor layer140and the isolation structures170. The buffer layer180may be directly disposed on and contact the second surface140bof the semiconductor layer140. In some exemplary examples, the second surface140bof the semiconductor layer140is covered by some portions of the isolation structures170, and the buffer layer180is disposed on the isolation structures170. The buffer layer180may be transparent and may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or any combinations thereof.

Referring toFIG.1again, the semiconductor device100may optionally include a metal grid layer190, in which the metal grid layer190is disposed on portions of the buffer layer180. The metal grid layer190may block the incident light110, and thus prevents the optical interference between the pixel regions146. For example, the metal grid layer190may include W, Ti, TiN, Ta, TaN, Al, Cu, AlCu, Ni, or any combinations or alloys thereof.

As shown inFIG.1, the semiconductor device100may optionally include a passivation layer195. The passivation layer195is disposed on and covering the metal grid layer190and the buffer layer180. The passivation layer195may be used to protect the metal grid layer190and the buffer layer180. The passivation layer195may be a dielectric film, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or any combinations thereof.

FIG.5AthroughFIG.5Kare schematic cross-sectional views of intermediate stages showing a method for manufacturing a semiconductor device in accordance with various embodiments. As shown inFIG.5A, a substrate200is provided. The substrate200may be provided to include a group IV material, a group IV material compound, or a group III-V material compound. For example, the group IV material may be Si or Ge, the group IV material compound may be SiGe, and the group III-V material compound may be sapphire.

A semiconductor layer210is formed on a surface200aof the substrate200. The semiconductor layer210is formed to include various light-sensing regions212. Each of the light-sensing regions212may be formed to include a photodiode. In some exemplary examples, the light-sensing regions212are formed by performing an implant process on the semiconductor layer210. The semiconductor layer210has a first surface210aand a second surface210b, in which the first surface210aand the second surface210bare opposite to each other. In the embodiments, the second surface210bof the semiconductor layer210has a lattice plane which is tilted with respect to a basal plane. In some examples, the lattice plane of the second surface210bof the semiconductor layer210is one of a {110} family of planes of a cubic system or one of a {111} family of planes of the cubic system. The semiconductor layer210may be formed to include a group IV material, a group IV material compound, or a group III-V material compound. For example, the group IV material and the group IV material compound may include Si, Ge, or SiGe. The group III-V material compound may include GaN, GaAs, InAs, InGaN, or InGaAs.

A device layer220is formed on the first surface210aof the semiconductor layer210, such that the first surface210ais adjacent to the device layer220. The device layer220is formed to include various devices222, such as transistors. Referring toFIG.5Aagain, at least one inter-metal dielectric layer230may be optionally formed on the device layer220. The inter-metal dielectric layer230may be formed to include conductive lines, in which conductive lines are electrically connected to the devices222of the device layer220. The inter-metal dielectric layer230is formed to include a dielectric film, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or any combinations thereof.

In some exemplary examples, as shown inFIG.5A, a passivation layer240is optionally formed on the inter-metal dielectric layer230. The passivation layer240may be formed by using a deposition process, such as a chemical vapor deposition (CVD) process. The passivation layer240may be formed to include a dielectric film, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or any combinations thereof.

In some examples, as shown inFIG.5A, a carrier250is provided. The substrate200and the structure formed thereon, which includes the semiconductor layer210, the device layer220, the inter-metal dielectric layer230, and the passivation layer240, are flipped and are bonded to the carrier250. The passivation layer240is suitable for bonding the inter-metal dielectric layer230and the carrier250. After the inter-metal dielectric layer230is bonded to the carrier250by using the passivation layer240, the device layer220and the semiconductor layer210are disposed on the carrier250.

As shown inFIG.5B, the substrate200is removed to expose the second surface210bof the semiconductor layer210. For example, the substrate200may be removed by using an etching process or a polishing process. The polishing process may be a chemical mechanical polishing (CMP) process. Optionally, a thinning process may be performed on the second surface210bof the semiconductor layer210to reduce a thickness of the semiconductor layer210. For example, the thinning process may be performed by using an etching process or a polishing process. In certain examples, removing the substrate200and thinning the semiconductor layer210may be performed by one single process.

In some examples, as shown inFIG.5C, after the substrate200is removed, various trenches214may be optionally formed in the semiconductor layer210to define various pixel regions270. For example, the trenches214may be formed by removing portions of the semiconductor layer210using a photolithography process and an etching process. The trenches214extend from the second surface210bof the semiconductor layer210to a predetermined thickness of the semiconductor layer210. The trenches214may be deep trenches. After the trenches214are formed, the trenches214are respectively filled with isolation fillers260, as shown inFIG.5D. Each of the pixel regions270may include one of the light-sensing regions212, and each of the isolation fillers260isolates two adjacent ones of the light-sensing regions212. For example, each of the pixel regions270may be formed as a rectangular region surrounded by the isolation fillers260.

Referring toFIG.5DthroughFIG.5F, an etching process is performed on the second surface210bof the semiconductor layer210to form various pit portions216on the second surface210bof the semiconductor layer210. In some examples, in the etching process, a hard mask material layer280is formed to cover the second surface210bof the semiconductor layer210and the isolation fillers260, as shown inFIG.5D. The hard mask material layer280may be formed by using a deposition technique, such as a chemical vapor deposition technique. The hard mask material layer280may be formed to include a dielectric film, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or any combinations thereof.

As shown inFIG.5E, the hard mask material layer280and the semiconductor layer210are patterned to remove portions of the hard mask material layer280and the underlying semiconductor layer210, so as to form various concavities282exposing portions of the semiconductor layer210. The portions of the hard mask material layer280are removed to form a hard mask layer280a. The hard mask layer280ais disposed on portions of the second surface210bof the semiconductor layer210and covers the isolation fillers260. Each of the concavities282extends from the hard mask layer280ato the semiconductor layer210, and a bottom282aof each of the concavities282is near the second surface210bof the semiconductor layer210. In some exemplary examples, patterning the hard mask material layer280and the semiconductor layer210includes using a photolithography technique and an etching technique, such as a dry etching technique.

As shown inFIG.5F, an etching operation is performed on the exposed portions of the semiconductor layer210. In some examples, the etching operation is a wet etching operation, and the semiconductor layer210exposed by the concavities282are isotropically etched, so as to form various pit portions216on the second surface210bof the semiconductor layer210. For example, the pit portions216may be pyramid pit portions or prism pit portions. The pit portions216are arranged on the second surface210bof the semiconductor layer210. In some examples, in each of the pixel regions270, the pit portions216are regularly arranged on the second surface210bof the semiconductor layer210. For example, the pit portions216may be arranged in an array. Any two adjacent ones of the pit portions216may adjoin to each other or may be separated from each other. In addition, shapes of the pit portions216of the semiconductor layer210are substantially the same.

In the embodiments, the second surface210bof the semiconductor layer210has a lattice plane which is tilted with respect to the basal plane, thus the pit portions216with different layouts and different shapes are obtained after the etching process due to different etching rates at different orientations of the second surface210bof the semiconductor layer210. In some examples, the lattice plane of the second surface210bof the semiconductor layer210is one of a {110} family of planes of a cubic system or one of a {111} family of planes of the cubic system. Referring toFIG.2A,FIG.2B, andFIG.5Fsimultaneously, in the examples that the lattice plane of the second surface210bof the semiconductor layer210is one of the {110} family of planes of the cubic system, the pit portions216are square based pyramid pit portions, which are similar to the pit portions144ashown inFIG.2AandFIG.2B. In addition, four edges of a base of each of the pit portions216are non-parallel with four edges of the pixel region270.

Referring toFIG.3A,FIG.3B, andFIG.5Fsimultaneously, in the examples that the lattice plane of the second surface210bof the semiconductor layer210is one of the {111} family of planes of the cubic system, the pit portions216are triangular based pyramid pit portions, which are similar to the pit portions144bshown inFIG.3AandFIG.3B. In addition, one edge of the as base of each of the pyramid pit portions216is substantially parallel to two opposite edges of the pixel region270.

Referring toFIG.4A,FIG.4B, andFIG.5Fsimultaneously, in the examples that the lattice plane of the second surface210bof the semiconductor layer210is one of the {110} family of planes of the cubic system, the pit portions216are square based prism pit portion, which are similar to the pit portions144cshown inFIG.4AandFIG.4B. In addition, two opposite edges of the base of each of the pit portions216are substantially parallel to two opposite edges of the pixel region270, and the other two opposite edges of the base of each of the pit portions216are substantially parallel to the other two opposite edges of the pixel region270.

As shown inFIG.5G, after the pit portions216are completed, the hard mask layer280ais removed to expose the isolation fillers260. In some exemplary examples, as shown inFIG.5G, the isolation fillers260are removed from the trenches214by using, for example, an etching technique. Then, the trenches214are filled with various isolation structures290. The isolation structures290may be formed by using a deposition technique, such as a chemical vapor deposition technique. In some exemplary examples, each of the isolation structures290is a deep trench isolation structure extending from the second surface210bof the semiconductor layer210to a predetermined depth of the semiconductor layer210, so as to isolate two adjacent ones of the light-sensing regions212. In certain examples, as shown inFIG.5H, in forming the isolation structures290, a dielectric layer292is formed on the second surface210bof the semiconductor layer210, in which the trenches214are filled with the dielectric layer292, such that the isolation structures290are respectively formed in the trenches214. The second surface210bof the semiconductor layer210and the pyramid pit portions216are covered by the dielectric layer292. For example, the dielectric layer292is formed to include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or any combinations thereof.

In some examples, as shown inFIG.5I, a buffer layer300is optionally formed to cover the second surface210bof the semiconductor layer210and the isolation structures290. The buffer layer300may be formed to directly on and contact the second surface210bof the semiconductor layer210. In the examples that the second surface210bof the semiconductor layer210is covered by the dielectric layer292, the buffer layer300is formed on the dielectric layer292. The buffer layer300may be formed by using a deposition technique. The buffer layer300may be transparent and may be formed to include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or any combinations thereof.

In some examples, as shown inFIG.5J, a metal grid layer310is optionally formed on portions of the buffer layer300. The metal grid layer310may be formed by using a deposition technique, a photolithography technique, and an etching technique, in which the deposition technique may be a physical vapor deposition technique or a chemical vapor deposition technique. For example, the metal grid layer310may be formed to include W, Ti, TiN, Ta, TaN, Al, Cu, AlCu, Ni, or any combinations or alloys thereof.

In some examples, as shown inFIG.5K, a passivation layer320is optionally formed on and covering the buffer layer300and the metal grid layer310, so as to substantially complete a semiconductor device330. The passivation layer320may be formed to protect the metal grid layer310and the buffer layer300. The passivation layer320may be formed to include a dielectric film, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or any combinations thereof.

Referring toFIG.6withFIG.5AthroughFIG.5K,FIG.6is a flow chart of a method for manufacturing a semiconductor device in accordance with various embodiments. The method begins at operation400, where a substrate200is provided. The substrate200may be provided to include Si, Ge, SiGe, or sapphire.

At operation410, as shown inFIG.5A, a semiconductor layer210including various light-sensing regions212is formed on a surface200aof the substrate200. In some exemplary examples, the light-sensing regions212are formed by using an implant technique. Each of the light-sensing regions212may be formed to include a photodiode. The semiconductor layer210has a first surface210aand a second surface210bopposite to each other. In the embodiments, the second surface210bof the semiconductor layer210is formed to have a lattice plane which is tilted with respect to a basal plane. In some examples, the lattice plane of the second surface210bof the semiconductor layer210is one of a {111} family of planes of a cubic system or one of a {111} family of planes of the cubic system. For example, the semiconductor layer210may be formed to include Si, Ge, SiGe, GaN, GaAs, InAs, InGaN, or InGaAs.

At operation420, as shown inFIG.5A, a device layer220is formed on the first surface210aof the semiconductor layer210. The device layer220is formed to include various devices222, such as transistors. At operation430, as shown inFIG.5A, at least one inter-metal dielectric layer230may be optionally formed on the device layer220. The inter-metal dielectric layer230may be formed to include conductive lines, in which conductive lines are electrically connected to the devices222of the device layer220. At operation440, a passivation layer240may be optionally formed on the inter-metal dielectric layer230by using, for example, a chemical vapor deposition process.

At operation450, referring toFIG.5Aagain, a carrier250is provided. The substrate200, and the semiconductor layer210, the device layer220, the inter-metal dielectric layer230, and the passivation layer240formed thereon are flipped and are bonded to the carrier250. After bonding, the device layer220and the semiconductor layer210are disposed on the carrier250.

At operation460, as shown inFIG.5B, the substrate200is removed to expose the second surface210bof the semiconductor layer210, by using, for example, an etching process or a polishing process. The polishing process may be a chemical mechanical polishing process. A thinning process may be optionally performed on the second surface210bof the semiconductor layer210to reduce a thickness of the semiconductor layer210by using, for example, an etching process or a polishing process. Removing the substrate200and thinning the semiconductor layer210may be performed by one single process, such as one chemical mechanical polishing process.

In some examples, as shown inFIG.5C, various trenches214may be optionally formed in the semiconductor layer210to define various pixel regions270. For example, the trenches214may be formed in the semiconductor layer210by removing portions of the semiconductor layer210using a photolithography process and an etching process. The trenches214may be deep trenches, and may extend from the second surface210bof the semiconductor layer210to a predetermined thickness of the semiconductor layer210. As shown inFIG.5D, the trenches214are respectively filled with the isolation fillers260. Each of the pixel regions270may include one of the light-sensing regions212, and each of the isolation fillers260isolates two adjacent ones of the light-sensing regions212. Each of the pixel regions270may be formed as a rectangular region surrounded by the isolation fillers260.

At operation470, referring toFIG.5DthroughFIG.5F, an etching process is performed on the second surface210bof the semiconductor layer210to form various pit portions216on the second surface210bof the semiconductor layer210. In some examples, as shown inFIG.5D, the etching process includes forming a hard mask material layer280to cover the second surface210bof the semiconductor layer210and the isolation fillers260by using, for example, a chemical vapor deposition technique. The hard mask material layer280is formed from a material which is different from a material of the semiconductor layer210.

As shown inFIG.5E, the hard mask material layer280and the semiconductor layer210are patterned to remove portions of the hard mask material layer280and the underlying semiconductor layer210, so as to form a hard mask layer280aand various concavities282exposing portions of the semiconductor layer210. The hard mask material layer280and the semiconductor layer210may be patterned by using a photolithography technique and an etching technique, such as a dry etching technique. The hard mask layer280ais formed to cover portions of the second surface210bof the semiconductor layer210and the isolation fillers260. The concavities282are shallow, and a bottom282aof each of the concavities282is near the second surface210bof the semiconductor layer210.

As shown inFIG.5F, an etching operation is performed on the exposed portions of the semiconductor layer210. In some examples, the etching operation is a wet etching operation, and the semiconductor layer210exposed by the concavities282are isotropically etched, so as to form various pit portions216on the second surface210bof the semiconductor layer210. For example, the pit portions216may be pyramid pit portions or prism pit portions. In each of the pixel regions270, the pit portions216may be regularly arranged on the second surface210bof the semiconductor layer210. The pit portions216may adjoin to each other or may be separated from each other. Shapes of the pit portions216of the semiconductor layer210are substantially the same.

In the embodiments, the second surface210bof the semiconductor layer210has a lattice plane which is tilted with respect to the basal plane, thus the pit portions216with different layouts and different shapes are obtained after the etching process due to different etching rates at different orientations of the second surface210bof the semiconductor layer210. In some examples, the lattice plane of the second surface210bof the semiconductor layer210is one of a {110} family of planes of a cubic system or one of a {111} family of planes of the cubic system. Referring toFIG.2A,FIG.2B, andFIG.5Fsimultaneously, in the examples that the lattice plane of the second surface210bof the semiconductor layer210is one of the {110} family of planes of the cubic system, the pit portions216are square based pyramid pit portions, which are similar to the pit portions144ashown inFIG.2AandFIG.2B. Furthermore, four edges of a base of each of the pit portions216are non-parallel with four edges of the pixel region270.

Referring toFIG.3A,FIG.3B, andFIG.5Fsimultaneously, in the examples that the lattice plane of the second surface210bof the semiconductor layer210is one of the {111} family of planes of the cubic system, the pit portions216are triangular based pyramid pit portions, which are similar to the pit portions144bshown inFIG.3AandFIG.3B. In addition, one edge of a base of each of the pyramid pit portions216is substantially parallel to two opposite edges of the pixel region270.

Referring toFIG.4A,FIG.4B, andFIG.5Fsimultaneously, in the examples that the lattice plane of the second surface210bof the semiconductor layer210is one of the {110} family of planes of the cubic system, the pit portions216are square based prism pit portion, which are similar to the pit portions144cshown inFIG.4AandFIG.4B. In addition, two opposite edges of the base of each of the pit portions216are substantially parallel to two opposite edges of the pixel region270, and the other two opposite edges of the base of each of the pit portions216are substantially parallel to the other two opposite edges of the pixel region270.

As shown inFIG.5G, the hard mask layer280ais removed to expose the isolation fillers260. Then, as shown inFIG.5H, the isolation fillers260are removed from the trenches214, and the trenches214are then filled with the isolation structures290. The isolation fillers260may be removed by using an etching technique, and the isolation structures290may be formed by using a chemical vapor deposition technique. In certain examples, as shown inFIG.5H, in forming the isolation structures290, a dielectric layer292is formed on the second surface210bof the semiconductor layer210, in which the trenches214are filled with the dielectric layer292, such that the isolation structures290are respectively formed in the trenches214. The second surface210bof the semiconductor layer210and the pyramid pit portions216are covered by the dielectric layer292.

At operation480, as shown inFIG.5I, a buffer layer300may be optionally formed to cover the second surface210bof the semiconductor layer210and the isolation structures290by using a deposition technique. In some examples, as shown inFIG.5I, the buffer layer300is formed to cover the dielectric layer292.

At operation490, as shown inFIG.5J, a metal grid layer310may be optionally formed on portions of the buffer layer300by using a deposition technique, a photolithography technique, and an etching technique. The deposition technique may be a physical vapor deposition technique or a chemical vapor deposition technique, and the etching technique may be a dry etching technique.

At operation500, as shown inFIG.5K, a passivation layer320may be optionally formed on and covering the buffer layer300and the metal grid layer310, so as to substantially complete a semiconductor device330.

In accordance with an embodiment, the present disclosure discloses a semiconductor device, which is operated for sensing incident light. The semiconductor device includes a carrier, a device layer, and a semiconductor layer. The device layer is disposed on the carrier. The semiconductor layer is disposed on the device layer. The semiconductor layer includes various light-sensing regions. The semiconductor layer has a first surface and a second surface opposite to the first surface that is adjacent to the device layer. The second surface has a lattice plane which is tilted with respect to a basal plane. The semiconductor layer has various pit portions arranged on the second surface.

In accordance with one embodiment, the semiconductor device further includes isolation structures disposed in the semiconductor layer to define various pixel regions, in which each of the pixel regions includes one of the light-sensing regions.

In accordance with one embodiment, the lattice plane of the second surface of the semiconductor layer is one of a {110} family of planes of a cubic system, and each of the pit portions is a square based pyramid pit portion or a square based prism pit portion.

In accordance with one embodiment, each of the pixel regions is a rectangular region, and four edges of a base of each of the square based pyramid pit portions are non-parallel with four edges of each of the pixel regions.

In accordance with one embodiment, each of the pixel regions is a rectangular region, two edges of a base of each of the square based prism pit portions are parallel with two edges of each of the pixel regions, and the other two edges of the base of each of the square based prism pit portions are parallel with the other two edges of each of the pixel regions.

In accordance with one embodiment, the lattice plane of the second surface of the semiconductor layer is one of a {111} family of planes of a cubic system, and each of the pit portions is a triangular based pyramid pit portion.

In accordance with one embodiment, each of the pixel regions is a rectangular region, and one of three edges of a base of each of the triangular based pyramid pit portions is substantially parallel to two opposite edges of each of the pixel regions.

In accordance with one embodiment, the semiconductor layer comprises a group IV material, a group IV material compound, or a group III-V material compound.

In accordance with one embodiment, the semiconductor device further includes a first passivation layer disposed on the carrier, an inter-metal dielectric layer disposed over the first passivation layer, a buffer layer overlying the second surface of the semiconductor layer, a metal grid layer disposed on portions of the buffer layer, and a second passivation layer covering the metal grid layer and the buffer layer.

In accordance with another embodiment, the present disclosure discloses a method for manufacturing a semiconductor device. In this method, a substrate is provided, in which the substrate has a surface. A semiconductor layer and a device layer are sequentially formed on the surface of the substrate. The semiconductor layer has a first surface and a second surface opposite to the first surface which is adjacent to the device layer. The second surface has a lattice plane which is tilted with respect to a basal plane. The semiconductor layer includes various light-sensing regions. The device layer is bonded to a carrier. The substrate is removed to expose the second surface of the semiconductor layer. An etching process is performed on the second surface of the semiconductor layer to form various pit portions on the second surface.

In accordance with one embodiment, after removing the substrate, the method further includes forming various trenches in the semiconductor layer to define a plurality of pixel regions, in which each of the pixel regions includes one of the light-sensing regions; and filling the trenches with various isolation fillers.

In accordance with one embodiment, performing the etching process includes: forming a hard mask layer that is on portions of the second surface of the semiconductor layer and covers the isolation fillers; etching the semiconductor layer; and removing the hard mask layer.

In accordance with one embodiment, after the etching process, the method further includes: removing the isolation fillers; filling the trenches with various isolation structures; and forming a buffer layer to cover the second surface of the semiconductor layer and the isolation structures.

In accordance with one embodiment, the lattice plane of the second surface of the semiconductor layer is one of a {110} family of planes of a cubic system, and each of the pit portions is a square based pyramid pit portion or a square based prism pit portion.

In accordance with one embodiment, each of the pixel regions is formed as a rectangular region, and four edges of a base of each of the square based pyramid pit portions are non-parallel with four edges of each of the pixel regions, or two edges of a base of each of the square based prism pit portions are parallel with two edges of each of the pixel regions, and the other two edges of the base of each of the square based prism pit portions are parallel with the other two edges of each of the pixel regions.

In accordance with one embodiment, the lattice plane of the second surface of the semiconductor layer is one of a {111} family of planes of a cubic system, and each of the pit portions is a triangular based pyramid pit portion.

In accordance with one embodiment, each of the pixel regions is formed as a rectangular region, and one of three edges of a base of each of the triangular based pyramid pit portions is substantially parallel to two opposite edges of each of the pixel regions.

In accordance with yet another embodiment, the present disclosure discloses a method for manufacturing a semiconductor device. In this method, a substrate having a surface is provided. A semiconductor layer is formed on the surface of the substrate. The semiconductor layer includes various light-sensing regions and has a first surface and a second surface opposite to the first surface. The second surface has a lattice plane which is tilted with respect to a basal plane. A device layer is formed on the first surface of the semiconductor layer. The device layer is bonded to a carrier. The substrate is removed to expose the second surface of the semiconductor layer. Various trenches are formed in the semiconductor layer to define various pixel regions, in which each of the pixel regions comprises one of the light-sensing regions. The trenches are filled with various isolation fillers. A hard mask material layer is formed to cover the second surface of the semiconductor layer and the isolation fillers. The hard mask material layer and the semiconductor layer are patterned to expose portions of the semiconductor layer. The portions of the semiconductor layer are etched to form various pit portions on the second surface via the hard mask material layer.

In accordance with one embodiment, the lattice plane of the second surface of the semiconductor layer is one of a {110} family of planes of a cubic system, and each of the pyramid pit portions is a square based pyramid pit portion or a square based prism pit portion. Each of the pixel regions is formed as a rectangular region. Four edges of a base of each of the pyramid pit portions are non-parallel with four edges of each of the pixel regions, or two edges of a base of each of the square based prism pit portions are parallel with two edges of each of the pixel regions, and the other two edges of the base of each of the square based prism pit portions are parallel with the other two edges of each of the pixel regions.

In accordance with one embodiment, the lattice plane of the second surface of the semiconductor layer is one of a {111} family of planes of a cubic system, and each of the pit portions is a triangular based pyramid pit portion. Each of the pixel regions is formed as a rectangular region, and one of three edges of a base of each of the triangular based pyramid pit portions is substantially parallel to two opposite edges of each of the pixel regions.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.