Patent ID: 12260100

DETAILED DESCRIPTION

In the following, numerous specific details are described to provide a thorough understanding of embodiments of the invention. However, one of skilled in the art will understand how to implement the invention in the absence of one or more specific details, or relying on other methods, elements or materials. In other instances, well-known structures, materials or operations are not shown or described in detail in order to avoid obscuring the main concepts of the invention.

Reference throughout this specification to “one embodiment”, “an embodiment”, “one example” or “an example” means that a particular feature, structure or characteristic described in connection with the embodiment or example is included in at least one embodiment of a plurality of embodiments. Thus, appearances of the phrases “in one embodiment”, “in an embodiment”, “one example” or “an example” in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures or characteristics may be combined in any suitable combinations and/or sub-combinations in one or more embodiments or examples.

In addition, in order to make the objects, features and advantages of the invention more comprehensible, specific embodiments of the invention are set forth in the accompanying drawings. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. It should be understood that the following embodiments can be implemented by software, hardware, firmware, or any combination thereof.

FIG.1shows an exemplary block diagram of a data storage device according to an embodiment of the invention. The data storage device100may comprise a memory device120and a memory controller110. The memory controller110is configured to access the memory device120and control operations of the memory device120. The memory device120may be a non-volatile (NV) memory (e.g., a Flash memory) device and may comprise one or more memory elements (e.g., one or more memory dies, or one or more memory chip, or the likes).

The data storage device100may be coupled to a host device130. The host device130may comprise at least one processor, a power supply circuit, and at least one random access memory (RAM), such as at least one dynamic RAM (DRAM), at least one static RAM (SRAM), . . . etc. (not shown inFIG.1). The processor and the RAM may be coupled to each other through a bus, and may be coupled to the power supply circuit to obtain power. The processor may be arranged to control operations of the host device130, and the power supply circuit may be arranged to provide the processor, the RAM, and the data storage device100with power. For example, the power supply circuit may output one or more driving voltages to the data storage device100. The data storage device100may obtain the one or more driving voltages from the host device130as the power of the data storage device100and provide the host device130with storage space.

According to an embodiment of the invention, the memory controller110may comprise a microprocessor112, a Read Only Memory (ROM)112M, a memory interface114, a buffer memory116and a host interface118. The ROM112M is configured to store program codes112C. The microprocessor112is configured to execute the program codes112C, thereby controlling access to the memory device120. The program codes112C may comprise one or more program modules, such as the boot loader code. When the data storage device100obtains power from the host device130, the microprocessor112may perform an initialization procedure of the data storage device100by executing the program codes112C. In the initialization procedure, the microprocessor112may load a group of In-System Programming (ISP) codes (not shown inFIG.1) from the memory device120. The microprocessor112may execute the group of ISP codes, so that the data storage device100has various functions. According to an embodiment of the invention, the group of ISP codes may comprise, but are not limited to: one or more program modules related to memory access (e.g., read, write and erase), such as a read operation module, a table lookup module, a wear leveling module, a read refresh module, a read reclaim module, a garbage collection module, a sudden power off recovery (SPOR) module and an uncorrectable error correction code (UECC) module, respectively provided for performing the operations of read, table lookup, wear leveling, read refresh, read reclaim, garbage collection, SPOR and error handling for detected UECC error.

The memory interface114may comprise an encoder132and a decoder134. The encoder132is configured to encode the data to be written into the memory device120, such as performing ECC encoding. The decoder134is configured decode the data read out from the memory device120.

Typically, the memory device120may comprise a plurality of memory elements, such as a plurality of memory dies or memory chips, and each memory element may comprise a plurality of memory blocks. The access unit of an erase operation performed by the memory controller110on the memory device120may be one memory block. In addition, a memory block may record (comprise) a predetermined number of pages, for example, the physical pages, and the access unit of a write operation performed by the memory controller110on the memory device120may be one page.

In practice, the memory controller110may perform various control operations by using its own internal components. For example, the memory controller110may use the memory interface114to control the access operations (especially the access operation for at least a memory block or at least a page) of the memory device120, use the buffer memory116to perform necessary data buffer operations, and use the host interface118to communicate with the host device130.

In an embodiment of the invention, the memory controller110may use the host interface118to communicate with the host device130in compliance with a standard communication protocol. For example, the standard communication protocol may comprise (but is not limited to) the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the CF interface standard, the Multi Media Card (MMC) interface standard, the eMMC interface standard, the UFS interface standard, the Advanced Technology Attachment (ATA) standard, the Serial ATA (SATA) standard, the Peripheral Component Interconnect Express (PCI-E) standard, the Parallel Advanced Technology Attachment (PATA) standard, etc.

In an embodiment, the buffer memory116may be implemented by a RAM. For example, the buffer memory116may be an SRAM, but the invention should not be limited thereto. In other embodiments, the buffer memory116may be a DRAM.

In an embodiment of the invention, the data storage device100may be a portable storage device (for example, the memory card in compliance with the SD/MMC, CF, MS and/or XD standard), and the host device130may be an electronic device, such as a mobile phone, a notebook computer, a desktop computer . . . etc., capable of connecting to the data storage device. In another embodiment of the invention, the data storage device100may be a solid state hard disk or an embedded storage device in compliance with the UFS or the eMMC standards, and may be equipped in an electronic device such as a mobile phone, a notebook computer, or a desktop computer. In such an embodiment, the host device130may be a processor of the electronic device.

The host device130may issue commands, such as the read command or the write command, to the data storage device100, so as to access the data stored in the memory device120, or the host device130may issue commands to further control or manage the data storage device100.

According to an embodiment of the invention, the memory blocks comprised in the memory device120may be Single-Level Cell (SLC) memory blocks, Multiple-Level Cell (MLC) memory blocks, Triple-Level Cell (TLC) memory blocks, Quad-Level Cell (QLC) memory blocks, or other types of memory blocks with further more levels. Each memory cell (for example, the floating-gate transistor or other charge trap element) of the SLC memory block stores one bit of data, each memory cell of the MLC memory block stores two bits of data, each memory cell of the TLC memory block stores three bits of data and each memory cell of the QLC memory block stores four bits of data.

To improve the access efficiency, the memory chips (or called memory dies or Logical Unit Numbers (LUNs), which may have different names or may be presented in different forms, depending on the packaging method of the memory device) may share the data bus. That is, the memory chips of the memory device120may be coupled to the memory controller110through shared data bus. It is to be noted that configuring a plurality of memory chips and coupling the memory chips to the memory controller110through the shared data bus is not a limit of the invention. In an alternative embodiment of the invention, it may also be configuring a plurality of memory dies or LUNs in a memory device and coupling the memory dies or LUNs to the memory controller110through shared data bus. In the following paragraphs, the memory dies will be utilized as the exemplary memory elements to simplify the description. In addition, it is to be noted that each of the abovementioned chips, dies or LUNs sharing the data bus may respectively comprise one or more internal registers and may respectively maintain their own operating status.

In addition, to further improve the access efficiency, in some embodiments of the invention, the memory device120may have a multi-channel configuration, where each channel may correspond to one data bus. With multi-channel configuration, greater parallel processing benefits can be obtained when writing and reading data.

In the embodiments of the invention, regardless of whether the memory device120has a single-channel configuration or a multi-channel configuration, by properly arranging the write order of writing data into the memory device120, the data written into a superblock (or, a read-write group) is specially arranged so that when the memory controller has to read the data in the future, the memory controller may directly read each portion of the data in a logical order (or called a logical data order), thereby solving the prior art problem of being necessary to temporarily buffer some portions of the data in the buffer memory116(or, in other data buffer of the memory controller110) causing the portions of the data being unable to be immediately provided to the host device130right after they have been read from the memory device120due to the drawback that the memory controller cannot sequentially obtain each portion of the data in the logical order. Here, the logical order (or the logical data order) is an order of transferring data between the memory controller110and the host device130. In this manner, the retention time that the data has to be buffered in the buffer memory116(or other data buffer) is greatly reduced and the data turnover rate of the buffer memory116(or other data buffer) is greatly improved.

According to an embodiment of the invention, the memory device120may comprise a plurality of memory dies and each memory die may comprise a plurality of planes. Each plane of each memory die may correspond to one of a plurality of plane indices (e.g., each plane of a memory die may be assigned a plane index), to differentiate between different planes. Therefore, one of the planes of each memory die corresponds to one of the plane indices. Each plane may comprise a plurality of memory blocks, and each memory block may comprise a plurality of pages. The memory blocks may form a plurality of superblocks, each superblock comprises a predetermine number of the memory blocks and the predetermine number of the memory blocks are respectively in different planes of different memory dies.

FIG.2shows an exemplary structure of a memory device according to an embodiment of the invention. In this embodiment, the memory device (e.g., the memory device120) may comprise four memory dies, such as the memory dies Die[0], Die[1], Die[2] and Die[3] shown inFIG.2, each memory die may correspond to one of a plurality of die indices (e.g., the numbers 0˜3 in the square brackets), to differentiate between different memory dies.

In an embodiment of the invention, to gain the benefits of parallel processing, the memory device120may have a multi-channel configuration, for example, two channels CH[0] and CH[1] may be configured, wherein the memory dies Die[0] and Die[2] may be coupled to the channel CH[0] and the memory dies Die[1] and Die[3] may be coupled to the coupled to the channel CH[1]. In addition, since the memory dies Die[0] and Die[2] are both coupled to the channel CH[0], the memory dies Die[0] and Die[2] may be coupled to the memory controller (e.g., the memory controller110) through the shared data bus. Similarly, the memory dies Die[1] and Die[3] may be coupled to the memory controller (e.g., the memory controller110) through the shared data bus. The memory controller110may use different chip enable signals to enable corresponding memory dies. As an example, the memory controller110may enable the memory dies Die[0] and Die[1] by using the chip enable signal CE[0] and enable the memory dies Die[2] and Die[3] by using the chip enable signal CE[1].

In this embodiment, each memory die may comprise two planes, such as the planes Plane[0] and Plane[1] shown inFIG.2, and the two planes of each memory die may be respectively assigned one of the two plane indices (e.g., the numbers 0˜1 in the square brackets) to differentiate between different planes. Each memory die may also comprise a plurality of memory blocks, such as the memory blocks Block[0]˜Block[K−1] shown inFIG.2, where K is a positive integer. Each memory block may correspond to one of a plurality of block indices (e.g., the numbers 0˜(K−1) in the square brackets) to differentiate between memory blocks. Each plane may comprise multiple memory blocks of the corresponding memory die. As an example, the plane Plane[0] (or called the first plane) may comprise memory blocks Block[0], Block[2], . . . . Block[K−2] and the plane Plane[1] (or called the second plane) may comprise memory blocks Block[1], Block[3], . . . . Block[K−1]. In addition, each memory block may comprise a plurality of pages, such as the pages Page[0], Page[1], Page[2], . . . , Page[M−2] and Page[M−1], where M is a positive integer.

According to an embodiment of the invention, the memory blocks Block[0]˜Block[K−1] may for a plurality of superblocks, such as the superblocks GP[0], GP[1], . . . . GP[N−1] shown inFIG.2, where N is a positive integer and the aforementioned superblock may also be regarded as a read-write group in the embodiments of the invention. Each superblock may comprise a predetermined number of memory blocks, and the predetermine number of the memory blocks may be respectively in different planes of different memory dies. For example, in the example shown inFIG.2, the predetermined number is 8.

In the embodiments of the invention, by applying the proposed data processing method, the memory controller110may arrange the order of writing each portion of predetermined data into the memory device120for the data stored in a superblock (e.g., a read-write group) being specially arranged. In this manner, when the memory controller110has to read the predetermined data from the memory device120in the future, the memory controller110may directly read each portion of the predetermined based on a logical order, which is just an order required for transferring data between the memory controller110and the host device130. In some embodiments, the order required for transferring data between the memory controller110and the host device130. In some embodiments of the invention, the order required for transferring data between the memory controller110and the host device130is just the order of logical addresses utilized by the host device130to identify the data. As an example, assuming that a piece of data comprises four portions Data_P[0]˜Data_P[3] which respectively correspond to the logical addresses LBA[0]˜LBA[3], after the data has been written into the memory device120by applying the proposed data processing method, when the memory controller110has to read the data, the memory controller110may sequentially read the four portions Data_P[0]˜Data_P[3] of the data from the memory device120, and the memory controller110may directly provide each read portion to the host device130right after the read operation of the corresponding portion is completed without the need of waiting for completion of the read operation of other portion of the data (since the memory controller110is able to obtain the four portions Data_P[0]˜Data_P[3] of the data in a correct order). In this manner, the retention time that the data has to be buffered in the buffer memory116(or other data buffer) is greatly reduced and the data turnover rate of the buffer memory116(or other data buffer) is greatly improved.

FIG.3is an exemplary flow chart of a data processing method according to an embodiment of the invention. The data processing method comprises the following steps performed by the memory controller110:

Step S302: performing a write operation in response to a write command received from the host device130to write predetermined data into the memory device120.

Step S304: selecting one from multiple superblocks as a first target superblock of the write operation.

Step S306: sequentially writing a plurality of portions of the predetermined data into the pages of the first target superblock (i.e., the pages belonging to the first target superblock) in a cyclic manner among the memory dies according to an order of plane indices. Note that steps S304and S306may also be regarded as parts of the operation comprised in step S302.

In some embodiments of the invention, the order of plane indices may be an order of ascending (or descending) values, but the invention is not limited thereto. In some other embodiments of the invention, the order of plane indices may also be an order in which the plane indices are arbitrarily arranged, and the spirit of operation in step S306is to sequentially write the portions of the predetermined data into the pages of the first target superblock in a cyclic manner among the memory dies according to a predetermined order of the plane indices.

To be more specific, according to an embodiment of the invention, step S306may further comprise the following detailed steps/operations performed by the memory controller110:

Sequentially performing a corresponding write operation on a first page on the first plane of all memory dies of the first target superblock; and

Sequentially performing a corresponding write operation on a first page on the second plane of all memory dies of the first target superblock.

For a corresponding write operation performed on one page, the memory controller110may write a portion, which has not been written into the memory device and has a size equal to the amount of data that can be stored in one page, of the predetermined data into the page. In the embodiments of the invention, the aforementioned one page may correspond to one physical page, but the invention is also not limited thereto. In alternative embodiments of the invention, the aforementioned one page may correspond to one physical address. As an example, one physical address may store 4 Kbytes (KB) of data, and the amount of data that can be stored in one physical page may be 16 KB.

According to an embodiment of the invention, the corresponding write operations performed on the first pages on the first plane are earlier than the corresponding write operations performed on the first pages on the second plane.

In addition, according to an embodiment of the invention, when the corresponding write operations performed on the first pages on the first plane of all memory dies of the first target superblock and the corresponding write operations performed on the first pages on the second plane of all memory dies of the first target superblock are completed, step S306may further comprise the following detailed steps/operations performed by the memory controller110:

Sequentially performing a corresponding write operation on a second page on the first plane of all memory dies of the first target superblock; and

Sequentially performing a corresponding write operation on a second page on the second plane of all memory dies of the first target superblock.

According to an embodiment of the invention, the corresponding write operations performed on the second pages on the first plane are earlier than the corresponding write operations performed on the second pages on the second plane. That is, when the corresponding write operations on the second pages on the first plane of all memory dies of the first target superblock are completed, the memory controller110continues to perform the corresponding write operations on the second pages on the second plane of all memory dies of the first target superblock.

FIG.4shows an exemplary write order of multiple pages of a superblock according to an embodiment of the invention. In this embodiment, the exemplary write order of the pages for a memory device having two memory dies (such as the memory dies Die[0] and Die[1] shown inFIG.4) and two planes (such as the planes Plane[0] and Plane[1] shown inFIG.4) is illustrated.

InFIG.4, one field written with a number marked by a underline, such as one of the numbers 0˜11 shown inFIG.4, represents one page, and one filed in the first row of such fields represents a first page of a predetermined memory block on the corresponding plane of the corresponding memory die, one filed in the second row of such fields represents a second page of the predetermined memory block on the corresponding plane of the corresponding memory die, and the rest may be deduced by analogy. In addition, inFIG.4, the numbers marked by underlines illustrate the write order of the pages of the superblock when the superblock is selected as a target superblock of a write operation, where smaller number means earlier the page is written. For example, the field written with the number 0 marked by underline is the earliest written page, the field written with the number 1 marked by underline is the secondary written page, and so on.

Taking the write order shown inFIG.4as an example, in the write operation of the predetermined data, corresponding write operations performed on the pages of a target superblock comprise, in a chronological order, the corresponding write operation performed on the first page on the first plane (e.g., the plane Plane[0]) of the first memory die (e.g., the memory die Die[0]), the corresponding write operation performed on the first page on the first plane of the second memory die (e.g., the memory die Die[1]), the corresponding write operation performed on the first page on the second plane (e.g., the plane Plane[1]) of the first memory die, the corresponding write operation performed on the first page on the second plane of the second memory die, the corresponding write operation performed on a second page on the first plane of the first memory die, the corresponding write operation performed on a second page on the first plane of the second memory die, the corresponding write operation performed on a second page on the second plane of the first memory die, and the corresponding write operation performed on a second page on the second plane of the second memory die, and the rest may be deduced by analogy. Note that the ordinal numbers used here to describe the first page, the second page, etc. may correspond to the numbers assigned based on physical positions or physical addresses of the pages in a memory block. As an example, the first page may be the first (starting) page of the memory block, the second page may a next page following the first page, and so on.

In this embodiment, the first memory die (e.g., the memory die Die[0]) and the second memory die (e.g., the memory die Die[1]) may be coupled to same or different channels of the memory device120, and the invention is not limited to any specific way of implementation.

FIG.5shows another exemplary write order of multiple pages of a superblock according to an embodiment of the invention. In this embodiment, the exemplary write order of the pages for a memory device having four memory dies (such as the memory dies Die[0], Die[1], Die[2] and Die[3] shown inFIG.5), dual-channel (such as the channels CH[0] and CH[1] shown inFIG.5) with two chip enable signals (such as the chip enable signals CE[0] and CE[1] shown inFIG.5) and two planes (such as the planes Plane[0] and Plane[1] shown inFIG.5) is illustrated.

Similarly, inFIG.5, one field written with a number marked by a underline, such as one of the numbers 0˜23 shown inFIG.5, represents one page, and one filed in the first row of such fields represents a first page of a predetermined memory block on the corresponding plane of the corresponding memory die, one filed in the second row of such fields represents a second page of the predetermined memory block on the corresponding plane of the corresponding memory die, and the rest may be deduced by analogy. In addition, inFIG.5, the numbers marked by underlines illustrate the write order of the pages of the superblock when the superblock is selected as a target superblock of a write operation, where smaller number means earlier the page is written. For example, the field written with the number 0 marked by underline is the earliest written page, the field written with the number 1 marked by underline is the secondary written page, and so on.

Taking the write order shown inFIG.5as an example, in the write operation of the predetermined data, corresponding write operations performed on the pages of a target superblock comprise, in a chronological order, the corresponding write operation performed on the first page on the first plane (e.g., the plane Plane[0]) of the first memory die (e.g., the memory die Die[0]), the corresponding write operation performed on the first page on the first plane of the second memory die (e.g., the memory die Die[1]), the corresponding write operation performed on the first page on the first plane of the third memory die (e.g., the memory die Die[2]), the corresponding write operation performed on the first page on the first plane of the fourth memory die (e.g., the memory die Die[3]), the corresponding write operation performed on the first page on the second plane (e.g., the plane Plane[1]) of the first memory die, the corresponding write operation performed on the first page on the second plane of the second memory die, the corresponding write operation performed on the first page on the second plane of the third memory die, the corresponding write operation performed on the first page on the second plane of the fourth memory die, the corresponding write operation performed on a second page on the first plane of the first memory die, the corresponding write operation performed on a second page on the first plane of the second memory die, the corresponding write operation performed on a second page on the first plane of the third memory die, the corresponding write operation performed on a second page on the first plane of the fourth memory die, the corresponding write operation performed on a second page on the second plane of the first memory die, the corresponding write operation performed on a second page on the second plane of the second memory die, the corresponding write operation performed on a second page on the second plane of the third memory die, and the corresponding write operation performed on a second page on the second plane of the fourth memory die. Note that the ordinal numbers used here to describe the first page, the second page, the third page and the fourth page, etc. may correspond to the numbers assigned based on physical positions or physical addresses of the pages in a memory block. As an example, the first page may be the first (starting) page of the memory block, the second page may a next page following the first page, the third page may a next page following the second page, and so on.

In this embodiment, the first memory die (e.g., the memory die Die[0]) and the third memory die (e.g., the memory die Die[2]) may be coupled to the first channel (e.g., the channel CH[0]) of the memory device120, and the second memory die (e.g., the memory die Die[1]) and the fourth memory die (e.g., the memory die Die[3]) may be coupled to the second channel (e.g., the channel CH[1]) of the memory device120.

According to an embodiment of the invention, when a size of an available space of the first target superblock selected in step S304is smaller than or equal to a threshold, as an example, when all the memory blocks in the first target superblock are full (e.g., the available space is zero or nearly zero) or when the available space of the memory blocks in the first target superblock is less than 5% or 3% of the overall capacity of a superblock, the memory controller110may perform the following steps after step S306is performed:selecting another from the superblocks as a second target superblock of the write operation according to an order of the superblock indices; andsequentially writing remaining portions of the predetermined data that have not been written in the memory device into the pages of the second target superblock in the cyclic manner among the memory dies according to the order of plane indices, which is similar to the write operation performed on the first target superblock.

In the embodiments of the invention, the order of superblock indices may be an order of ascending (or descending) values, but the invention is not limited thereto.

FIG.6shows another exemplary write order across multiple superblocks (read-write groups) according to an embodiment of the invention. In this embodiment, the exemplary write order of the pages for a memory device having four memory dies, dual-channel with two chip enable signals and two planes is illustrated. Different from the exemplary write order shown inFIG.5, in which the write order of multiple pages (e.g., the pages comprised in a corresponding memory block) is shown, in the exemplary write order shown inFIG.6, the write order of multiple memory blocks is shown.

InFIG.6, one field written with a symbol A-B marked by a underline represents one memory block, and one filed in the first row of such fields represents one memory block comprised in a first superblock (a first read-write group), one filed in the second row of such fields represents one memory block comprised in a second superblock (a second read-write group), and the rest may be deduced by analogy.

In addition, in the embodiment shown inFIG.6, the memory blocks Block[0]˜Block[99] having the same block index among the memory dies may belong to the same superblock (that is, the same read-write group), and each memory die comprises 100 memory blocks and two planes. Therefore, there are 50 superblocks shows inFIG.6.

The symbol A-B marked by a underline inFIG.6is used to represent the write order of the superblocks (that is, the read-write groups) and the write order of the memory blocks in a superblock, where smaller number means earlier the superblock/memory block is written. For easy distinction, the alphabet A in the symbol A-B is named as the first digit, and the alphabet B in the symbol A-B is named as the second digit. As an example, for the first digit A, the field written with the number 0 marked by a underline is the first (earliest) written superblock (read-write group), the field written with the number 1 marked by a underline is the second written superblock (read-write group), and so on. For the second digit B, the field written with the number 0 marked by a underline is the first (earliest) written memory block in the corresponding superblock (read-write group), the field written with the number 1 marked by a underline is the second written memory block in the corresponding superblock (read-write group), and so on. Therefore, for the second digit B, the field written with the number 7 marked by a underline is the last written memory block in the corresponding superblock (read-write group).

FIG.7shows another exemplary write order across multiple superblocks (read-write groups) according to an embodiment of the invention. This embodiment shows the write order of each page corresponding to the structure shown inFIG.2. In this embodiment, each memory block comprises 3457 pages. Therefore, the numbers 0˜27655 drawn inFIG.7show the write order of the pages in each corresponding superblock. In addition, in this embodiment, the memory controller110sequentially performs the corresponding write operation on the superblocks GP[0], GP[1], . . . , GP[N−1] according to the order of ascending superblock index value. That is, the data is written into the superblock GP[0] first. When the size of available space of the superblock GP[0] is smaller than or equal to a threshold, the data is written into the superblock GP[1], and the rest may be deduced by analogy.

Those skilled in the art can deduce the write order of other memory device structures based on the illustration inFIG.4˜FIG.7and the related description of any variance are omitted here for brevity.

Assuming that the predetermined data comprises a plurality of portions, such as a plurality of portions correspond to a plurality of consecutive logical addresses as described above, and each portion is written into one page of the memory device in the corresponding write operation as described above, in the embodiments of the invention, two or more adjacent portions of the predetermined data (for example, two or more portions with consecutive logical addresses) are written into two different memory dies.

FIG.8shows an exemplary write order adopted in the prior art for the memory device having two memory dies and two planes, where the memory device structure described herein corresponds to the embodiment shown inFIG.4.FIG.9shows an exemplary write order adopted in the prior art for the memory device having four memory dies, dual-channel with two chip enable signals and two planes, where the memory device structure described herein corresponds to the embodiment shown inFIG.5. In the prior art, data is consecutively written to different planes of the same memory die. After all the planes of a memory die are written with data, the data will be then written into the next memory die. Therefore, in prior art, adjacent portions of the data will be written into the same memory die.

Different from the write order adopted in the prior art, in the embodiments of the invention, the data is written in the order of plane indices, so that adjacent portions of the data are written into different memory dies. In this manner, when reading the data, each portion of the data is read based on the required logical order. As an example, in response to a read command received from the host device130to read the predetermined data, the memory controller110reads the predetermined data from the memory device based on a logical order (or, the aforementioned logical data order), wherein the logical order of reading the predetermined data equals to the write order (or called physical data order) of writing the predetermined data into the memory device120, and read data may be directly or immediately provided to the host device130without the need of being buffered in the buffer memory116to wait for completion of the read operation of other portion of the data. It is to be noted that, in the embodiment of the invention, the logical order (or called logical data order) is an order of transferring data between the memory controller110and the host device130, while the physical data order is an order of transferring data between the memory controller110and the memory device120.

FIG.10shows a timing diagram of a read operation to illustrate the corresponding physical data order and logical data order of the read operation performed on the data that was written based on the write order adopted by the prior art. InFIG.10, the part above the time axis shows the timing of reading data from the memory device, where the symbols of the pages P[0]˜P[15] are utilized therein to represent the read operations of the corresponding pages, and the part below the time axis shows the timing of providing the read data obtained by the memory controller110to the host device, where the symbols of the pages P[0]˜P[15] are utilized therein to represent the output operations of the corresponding read pages.

InFIG.10, the numbers in the square brackets correspond to the numbers marked by underlines inFIG.9. With the reference toFIG.9, those skilled in the art knows into which plane of which memory die each page inFIG.10was written, and the consecutive numbers 0˜15 in this example are also utilized to represent the continuity of data (e.g., the continuity of the logical addresses of the data, which also shows the logical data order).

As shown inFIG.10, it is assumed that the read operation of channel CH[0] is slightly earlier than the read operation of channel CH[1], the physical data order in the prior art is P[0], P[2], P[1], P[3], P[4], P[6], P[5], P[7], and so on (if the read operation of channel CH[0] and the read operation of channel CH[1] are finished at the same time, the physical data order in the prior art may be represented by (P[0] & P[2]), (P[1] &P[3]), and so on). As can be seen fromFIG.10, performance of the read operation of page P[2] is earlier than that of page[1], and performance of the read operation of page P[6] is earlier than that of page[5]. However, since it is necessary for the host device130to obtain the data in the logical data order P[0], P[1], P[2], P[3], P[4], P[5], P[6] and P[7], after obtaining the data of page P[2], the data of page P[2] has to be buffered in the buffer memory116and cannot be directly output and provided to the host device130until the memory controller110obtains the data of page[1] and provide it to the host device. Therefore, the retention time RT1is generated. Similarly, output of the data of page P[6] also generates the retention time RT2. It can also be seen inFIG.10that after outputting the data of pages P[0], P[4], P[8], P[12], in order to make the order of transferring data to be the required (correct) logical data order, there will always be a period of waiting time (e.g., the retention time shown inFIG.10) due to the inability to the output data continuously.

FIG.11shows a timing diagram of a read operation to illustrate the corresponding physical data order and logical data order of the read operation performed on the data that was written based on the proposed data processing method. Similarly, inFIG.11, the part above the time axis shows the timing of reading data from the memory device120, where the symbols of the pages P[0]˜P[15] are utilized therein to represent the read operations of the corresponding pages, and the part below the time axis shows the timing of providing the read data obtained by the memory controller110to the host device130, where the symbols of the pages P[0]˜P[15] are utilized therein to represent the output operations of the corresponding read pages.

Likewise, inFIG.11, the numbers in the square brackets correspond to the numbers marked by underlines inFIG.5. With the reference toFIG.5, those skilled in the art knows into which plane of which memory die each page inFIG.11was written, and the consecutive numbers 0˜15 in this example are also utilized to represent the continuity of data (e.g., the continuity of the logical addresses of the data, which also shows the logical data order).

As shown inFIG.11, it is assumed that the read operation of channel CH[0] is slightly earlier than the read operation of channel CH[1], the physical data order in the embodiments of the invention is P[0], P[2], P[1], P[3], P[4], P[6], P[5], P[7], and so on (If the read operation of channel CH[0] and the read operation of channel CH[1] are finished at the same time, the physical data order may be represented by (P[0] & P[1]), (P[2] &P[3]), and so on). As can be seen fromFIG.11, performance of the read operation of page P[1] is earlier than that of page[2], and performance of the read operation of page P[5] is earlier than that of page[6], and the order of reading the pages is just the correct logical data order which can be directly utilized to output the data to the host device130. Therefore, after the memory controller110obtains the data of the pages, the memory controller110may directly provide the data to the host device130according to the same order of obtaining the data of the pages.

In this embodiment, due to the requirement of parallel processing in dual-channel, the pages P[1], P[5], P[9], . . . and so on, have to be temporarily buffered in the buffer memory116. Therefore, the retention time RT3may still be generated for the output of the page[1] and the retention time RT4may still be generated for the output of the page[5]. However, the retention time RT3and the retention time RT4are relatively short as compared to the retention time RT1and the retention time RT2shown inFIG.10. As shown inFIG.11, the time difference obtained by subtracting the retention time RT3from the retention time RT1is the improved (that is, shortened) retention time TIP.

Therefore, in the embodiments of the invention, by properly arranging the write order of writing data into the memory device120, the data written into a superblock is specially arranged so that when the memory controller110has to read the data in the future, the memory controller110may directly read each portion of the data in a logical order (or called a logical data order), thereby solving the prior art problem of being necessary to temporarily buffer some portions of the data (which is usually about half or more than half of the data) in the buffer memory116(or, in other data buffer of the memory controller110) causing the portions of the data being unable to be immediately provided to the host device130right after they have been read from the memory device120due to the drawback that the memory controller cannot sequentially obtain each portion of the data in the logical data order required by the host device130. Here, the logical order (or the logical data order) is an order of transferring data between the memory controller110and the host device130. In this manner, the retention time that the data has to be buffered in the buffer memory116(or other data buffer) is greatly reduced and the data turnover rate of the buffer memory116(or other data buffer) is greatly improved.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.