Patent ID: 12200938

DETAILED DESCRIPTION

A driver, such as string driver, can be used to selectively supply access signals, such as programming signals (e.g., programming voltages), to an access line at a particular level of a stacked array to access (e.g., to program) the memory cells coupled to the access line. There can be a respective string driver coupled to each respective access line in the memory array. For example, a respective string driver can be coupled to each respective step corresponding to a respective access line. Note that such drivers can sometimes be referred to as access-line (e.g., word-line) drivers. Various current approaches place the respective string drivers under the array so that there is a respective string driver for each respective level of the array under the stacked array.

To meet the demand for higher capacity memories, designers continue to strive for increasing memory density (e.g., the number of memory cells in a given base area of an integrated circuit die). One way to increase the density of memory devices in stacked arrays is to increase the number of levels of memory cells, and thus the number of access lines and the number of sting drivers. However, there might not be enough room under the stacked memory array to accommodate the increased number of string drivers without increasing the base area (e.g., the footprint) of an integrated circuit die. Moreover, placing string drivers underneath the memory array can lead to more complex routing in a stacked array as the number of levels increases.

The present disclosure addresses the problem of accommodating the increased number of string drivers under stacked memory array by moving the string drivers above the memory array. Each of the drivers can have a monocrystalline semiconductor with a conductive region that is coupled to a respective access line. The monocrystalline semiconductor can act to reduce the resistance of the drivers and current leakage in the drivers compared to previous approaches that typically employ polycrystalline semiconductors, such as polysilicon. For example, the higher resistance and current leakage associated with using polycrystalline semiconductors can degrade the performance of the drivers, and thus of the memories that employ the drivers.

In some examples, the monocrystalline semiconductor formed and is subsequently transferred to a surface of a dielectric that is above the memory array using a transfer technique that avoids forming the monocrystalline semiconductor on the surface of the dielectric, such as by using various deposition techniques. For example, it can be difficult to form monocrystalline semiconductors on dielectrics.

FIG.1illustrates a portion of an apparatus, such as a portion of a memory100(e.g., a NAND memory) in accordance a number of embodiments of the present disclosure. Memory100can include a stacked memory array106, such as a stacked NAND memory array. Array106can include a memory-cell region101and a stair-step structure103adjacent to memory-cell region101.

Array106can include a stack of dielectrics102alternating with conductors104in the z-direction (e.g., the vertical direction) in the frame of reference ofFIG.1. Semiconductor structures105, such as semiconductor pillars, pass through the stack in memory cell region101in the z-direction and terminate at an upper surface of or in a semiconductor107. A select transistor108can be adjacent to each semiconductor structure105at a level corresponding to the uppermost conductor104, and a select transistor109can be adjacent to each semiconductor structure105at a level corresponding the lowermost conductor104.

Memory cells110can be adjacent to each semiconductor structure105at levels corresponding to the conductors104between the uppermost and lowermost conductors104. The memory cells110at each respective level are commonly coupled to the conductor104at the respective level. For example, the memory cells110at level in array106can be referred to as a level of memory cells, such as a tier of memory cells. The memory cells110adjacent to a semiconductor structure at the different levels105can be coupled in series to form a string (e.g., a vertical string) of series-coupled memory cells, such as a NAND string of memory cells.

The uppermost and lowermost conductors104can be select lines112that form or are coupled to gates of select transistors108and109, respectively. The conductors104between the uppermost and lowermost conductors104can be access lines114that can be referred to as word lines and that form or are coupled to control gates of memory cells110. Note that the memory cells110at each respective level are commonly coupled to the access line114at the respective level.

Stairstep structure103includes uppermost and lowermost steps116that can each include a portion of respective select line112over an adjacent dielectric102. A respective contact118is coupled to the respective select line112of each respective step116. Respective contacts118(e.g., vertical contacts) are coupled to activation circuitry by respective lines120. Data lines122are coupled to semiconductor structures105by data line contacts124.

In some examples, stairstep structure103includes steps127-1to127-N between the uppermost and lowermost steps116that can each include a portion of a respective access line114over an adjacent dielectric102. A respective contact129(e.g., vertical contact) is coupled to the respective access line114of each respective step127. For example, a step, such as a step127, including an access line, such as an access line114, can be referred to as an access line step.

In some examples, the respective contacts129are coupled to respective string drivers140that can be field effect transistors (FETs) and are over (e.g., above) stairstep structure103and thus array106. The respective string drivers140can be various string drivers disclosed herein. The string drivers can be configured to selectively couple the access lines114to access signals to access the memory cells110commonly coupled to the access lines. For example, the access signals can be programming signals, such as programming voltages, for programming memory cells110.

The respective string drivers140can include respective monocrystalline semiconductors130(e.g., of monocrystalline silicon (Si), monocrystalline silicon germanium (SiGe), monocrystalline germanium (Ge), or the like) that are over (e.g., above) stairstep structure103and thus array106. For example, above can be stairstep structure103, and thus array106, can be between string drivers140and semiconductor107. A respective string driver140can include a gate (not shown inFIG.1) formed over and coupled to a respective monocrystalline semiconductor130. The respective contacts129can be coupled to conductive regions, such as source/drains, (not shown inFIG.1) that can be formed in the respective monocrystalline semiconductors130. In some examples, the respective monocrystalline semiconductors130can be directly above (e.g., vertically above and horizontally aligned with) the respective steps127and can be formed over a dielectric (not shown inFIG.1) that can be formed over memory-cell region101and stairstep structure103.

Note that monocrystalline semiconductors130are distributed in the x-direction and extend in the y-direction in the frame of reference ofFIG.1. In some examples, a gate can extend in the x-direction and be commonly coupled to the monocrystalline semiconductors130distributed in the x-direction.

As discussed further herein, each monocrystalline semiconductor130can form a portion of at least one string driver so that the string drivers are above array. For example, a string driver can include a control gate (not shown inFIG.1) formed over a respective monocrystalline semiconductor130. The string drivers can be configured to selectively couple the access lines114to access signals to access the memory cells110commonly coupled to the access lines. For example, the access signals can be programming signals, such as programming voltages, for programming memory cells110.

In other examples, each respective monocrystalline semiconductor130can be replaced by a respective line, such as a line120(not shown inFIG.1), that can be coupled to a respective contact129so that there can be respective line coupled to each respective step127. Each respective line coupled to a respective step127can be coupled to a respective string driver that can be formed directly above memory-cell region101(not shown inFIG.1). For example, the string drivers might be formed over data lines122.

Array106can be divided into blocks135of memory cells110that can sometimes be referred to as subblocks. For example, a block of memory cells can refer to a group of memory cells that is commonly erased. Dielectrics (not shown inFIG.1) can be formed in openings137to electrically isolate blocks135from each other. Note that blocks135are distributed in the y-direction in the frame of reference ofFIG.1.

FIG.2illustrates a portion of a memory200that can be memory100in accordance with a number of embodiments of the present disclosure. Memory200can include string drivers240over a stacked memory array206that can be array106. Array206can be over logic circuitry242that can be over a semiconductor207. For example, string drivers240can be various string drivers disclosed herein. In some examples, there can be additional logic circuitry under array206(e.g., under semiconductor207) that can facilitate the operation of memory200.

String drivers240can be referred to as high-voltage string drivers because string drivers240might operate at around 30 volts, whereas logic circuitry242can be referred to as low-voltage logic circuitry because logic circuitry242might operate at around three volts. In some examples, string drivers240can include monocrystalline semiconductors, such as monocrystalline semiconductors130. Logic circuitry242can be coupled to gates of string drivers240for activating string drivers240. In some examples, logic circuitry242can include complementary-metal-oxide-semiconductor (CMOS) circuitry.

FIG.3illustrates a portion of a memory300that can be memory100in accordance with a number of embodiments of the present disclosure. Memory300can include string drivers340, such as high-voltage string drivers, over a stacked memory array306that can be array106. In some examples, string drivers340can include monocrystalline semiconductors, such as monocrystalline semiconductors130. Logic circuitry342, such as low-voltage CMOS circuitry, can be at the same level as string drivers340and can be over memory array306. Logic circuitry342can be coupled to control gates of string drivers340for activating string drivers340.

FIG.4Ais a top-down view of a portion of a memory400, that can be various memory described herein, in accordance with a number of embodiments of the present disclosure.FIGS.4B to4Dare various cross-sectional views associated withFIG.4Ain accordance with a number of embodiments of the present disclosure.FIG.4Bis a cross-sectional view in the y-z plane viewed along line4B-4B inFIG.4A;FIG.4Cis a cross-sectional view in the x-z plane viewed along line4C-4C inFIG.4A; andFIG.4Dis a cross-sectional view in the x-z plane viewed along line4D-4D inFIG.4A.

InFIG.4A, blocks435-1and435-2in memory-cell region401respectively correspond to respective stairstep structures403-1and403-2. For example, blocks435-1and435-2can be respectively coupled to stairstep structures403-1and403-2. Stairstep structures403-1and403-2each include steps427-(N−2) to427-N that respectively include access lines414-(N−2) to414-N, as shown inFIGS.4C and4D. Each of the respective access lines414-(N−2) to414-N is over a respective dielectric402. Each of the respective access lines414-(N−2) to414-N is commonly coupled to a respective level of memory cells in the respective block435.

String drivers440-(N−2) to440-N can be directly above stairstep structures403-1and403-2and can be respectively directly above steps427-(N−2) to427-N of each of stairstep structures403-1and403-2, as shown inFIG.4Dfor stairstep structure403-2. Each of string drivers440-(N−2) to440-N can include a monocrystalline semiconductor. For example, string drivers440-(N−2) to440-N can respectively include portions of monocrystalline semiconductors430-(N−2) to430-N.

Each of the string drivers440can include, in its respective monocrystalline semiconductor430, a respective conductive region, such as a respective source/drain444, coupled the respective access line414of a respective step427. For example, as shown inFIG.4C, monocrystalline semiconductors430-(N−2) to430-N respectively of string drivers440-(N−2) to440-N include source/drains444-(N−2) to444-N respectively coupled to access lines414-(N−2) to414-N.

Each of the respective string drivers440can include, in its respective monocrystalline semiconductor430, a respective source/drain445that can be coupled to receive access signals that can be selectively coupled to a respective access line in response to activating the respective string driver440. For example, as shown inFIG.4B, a source/drain445can be common to adjacent string drivers, such as the adjacent string drivers440-N. As such, adjacent string drivers can share a source/drain445. Note that source/drain445can be between stairstep structures403-1and403-2, and thus blocks435-1and435-2. In some examples, string drivers440can be field effect transistors (FETs).

As shown inFIGS.4A,4B, and4D, each of the respective string drivers440can include a portion of a common gate447. For example, the string drivers440-(N−2) to440-N of each of the respective blocks435-1and435-2can be commonly coupled to a respective gate447. As shown inFIGS.4B and4D, portions of a respective gate446can be adjacent to (e.g., over) a respective gate dielectric448(e.g., gate oxide) that can be over (e.g., in direct physical contact with) and common to the monocrystalline semiconductors430-(N−2) to430-N. For example, a gate447can be coupled to (e.g., by direct physical contact with) the gate dielectric448.

Each of the respective string drivers440can include a channel region449in its respective monocrystalline semiconductor430between source/drains444and445, as shown inFIG.4Bfor string drivers440-N, monocrystalline semiconductor430-N, and source/drains444-N and445. The gate dielectric448can be over (e.g., and in direct physical contact with) the channel region449. A conductive channel can be formed in the channel region449in response to activating the string driver440.

Source/drains444and445can be conductively doped to have an N+ conductivity level. In some examples, a portion450of each respective monocrystalline semiconductor430between the channel region449and the source/drain444, such as source/drain444-N inFIG.4B. Conductive regions451(e.g., N− conductive implants) can be formed in portions of each respective monocrystalline semiconductor430between the channel region449and the source/drain445by doping the portions to have an N− conductivity level that has a lower conductivity level that the N+ conductivity level.

Monocrystalline semiconductors430-(N−2) to430-N are directly above stairstep structures403-1and403-2and are respectively directly above steps427-(N−2) to427-N of stairstep structures403-1and403-2, as shown inFIG.4Dfor stairstep structure403-2. A dielectric456that can be oxide, nitride, or the like, can be formed adjacent to (e.g., over) each of stairstep structures403-1and403-2, as shown inFIGS.4B to4D. A dielectric458that can be oxide, nitride or the like, can then be formed over dielectric456. As such, dielectric458can be directly above stairstep structures403-1and403-2, as shown inFIGS.4B to4D. In some examples, dielectric458can extend over memory-cell region401(which is not shown inFIGS.4A to4D). For example, dielectric458can be over data lines122inFIG.1(not shown inFIG.1).

Monocrystalline semiconductors430-(N−2) to430-N are over and attached to dielectric458. For example, monocrystalline semiconductors430-(N−2) to430-N can be bonded in direct physical contact with an upper surface of dielectric458so that monocrystalline semiconductors430-(N−2) to430-N are above dielectric458. The gate dielectric448is formed over monocrystalline semiconductors430-(N−2) to430-N, as shown inFIGS.4B and4D, so that gate dielectric448is commonly coupled to monocrystalline semiconductors430-(N−2) to430-N. For example, gate dielectric448can be in direct physical contact with each of monocrystalline semiconductors430-(N−2) to430-N). Note that gate dielectric448can wrap around a portion of each of monocrystalline semiconductors430-(N−2) to430-N to be adjacent to the upper surface and the sides of each of monocrystalline semiconductors430-(N−2) to430-N.

A gate447can be adjacent to gate dielectric448, as shown inFIGS.4B and4D. Gate447is commonly coupled to each of monocrystalline semiconductors430-(N−2) to430-N through gate dielectric448. In some examples, gates447can be coupled to logic circuitry, such as logic circuitry242or342, to receive control signals such as activation signals, to activate the string drivers440commonly coupled thereto.

A respective contact460can be coupled to each respective source/drain445, such as to an upper surface of each respective source/drain445. As such, contacts460can be between the steps of stairstep structures403-1and403-2, and thus blocks435-1and435-2. In some examples, contacts460can be coupled to receive access signals.

A respective (e.g. vertical) contact464can be formed through each respective source/drain444, such as each of the respective source/drains444-(N−2) to444-N inFIGS.4B and4C. For example, each respective contact464can pass through a portion of dielectric458and can be coupled to (e.g., by direct physical contact with) a respective conductor, such as a respective conductive offset466, formed over (e.g., in direct physical contact with) an upper surface of dielectric456.

A respective conductor, such as a respective conductive plug468, can couple each respective conductive offset466to each of the respective access lines414-(N−2) to414-N. For example, a respective (e.g., vertical) conductive plug468can be coupled to (e.g., by direct physical contact with) the respective access line414and the respective conductive offset466and can pass through dielectric456.

Note that the respective conductive offset466can be a lateral offset that can extend laterally with respect to the z-direction (e.g., in the x-direction) over the upper surface of dielectric456from a respective contact464to a respective conductive plug468so that the respective contact464can be offset laterally from the respective conductive plug468. In some examples, a respective contact464, a respective conductive offset466, and a respective conductive plug468can be collectively referred to as a respective conductor that couples a respective source/drain444to a respective access line414, and thus a respective step427.

FIGS.5A to5Care various views corresponding to particular stages of processing associated with forming a memory in accordance with a number of embodiments of the present disclosure. In some examples, the processing described in conjunction withFIGS.5A to5Ccan be referred to as a transfer technique during which a monocrystalline semiconductor, such as monocrystalline silicon, can be formed and subsequently transferred to a surface of a dielectric. For example, it can be difficult to form a monocrystalline semiconductor in contact with a dielectric (e.g., using various deposition techniques).

InFIG.5A, hydrogen (H2) is implanted in a monocrystalline semiconductor530to form a hydrogen implant570in monocrystalline bulk semiconductor530. InFIG.5B, monocrystalline bulk semiconductor530, including hydrogen implant570, is coupled (e.g., attached) to a dielectric558, that can be dielectric458, formed over a stairstep structure503that can be stairstep structure103,403-1or403-2. For example, monocrystalline bulk semiconductor530can be inverted and subsequently attached to dielectric558by bonding monocrystalline bulk semiconductor530in direct physical contact with an upper surface of dielectric558.

After monocrystalline bulk semiconductor530is bonded to dielectric558, the structure inFIG.5Bis annealed (e.g., at about 400° C.) to remove the hydrogen and to create a relatively fragile (e.g., brittle) region at the site of the removed hydrogen. InFIG.5C, monocrystalline bulk semiconductor530is cleaved at the fragile region, leaving a portion of monocrystalline bulk semiconductor530bonded to dielectric530. Note that it can be difficult to form a monocrystalline semiconductor in contact with a dielectric, and it is for this reason, for example, that monocrystalline semiconductor530is formed and subsequently bonded to dielectric558in accordance with the process described inFIGS.5A to5C.

FIGS.6A to6Iare various views corresponding to particular stages of processing associated with forming a memory in accordance with a number of embodiments of the present disclosure.FIG.6Acan be a cross section in the x-z plane or the y-z plane corresponding to a particular stage of processing. In some examples, a processing stage can include a number of steps that can have a number of sub-steps.

InFIG.6A, a stacked memory array606, that can be various the memory arrays disclosed herein, is formed. A dielectric658that can be dielectric458or558can be formed above memory array606. A monocrystalline semiconductor629(e.g., monocrystalline silicon) that can be monocrystalline semiconductor530can be attached to an upper surface of dielectric658(e.g., as previously described in conjunction withFIGS.5A to5C) so that monocrystalline semiconductor629is above (e.g., and in direct physical contact with) the upper surface of dielectric658. For example, monocrystalline semiconductor629can be formed and subsequently transferred to the upper surface dielectric658using the transfer technique described in conjunction withFIGS.5A to5C, so as to avoid the difficulties associated with forming monocrystalline semiconductor629on the upper surface dielectric658.

FIG.6Bis a cross-section in the x-z plane corresponding to a particular stage of processing following the stage of processing corresponding toFIG.6A. For example, a mask (e.g., photoresist) can be formed over semiconductor629inFIG.6Aand patterned to expose portions of semiconductor629for removal. The portions can be subsequently removed (e.g., by etching), stopping at the upper surface of dielectric658to form monocrystalline semiconductor segments630-(N−2) to630-N than can respectively be monocrystalline semiconductors430-(N−2) to430-N.

FIG.6Cis a cross-section in the x-z plane corresponding to a particular stage of processing following the stage of processing corresponding toFIG.6B.FIG.6Dis a cross-section in the y-z plane, as viewed along any one of the lines D-D inFIG.6C, corresponding to the particular stage of processing ofFIG.6C. As such, reference number630can be used inFIG.6Dand subsequent views in the y-z plane to generally refer to each, or any, of monocrystalline semiconductor segments630-(N−2) to630-N. The structures inFIGS.6C and6Dcan be formed concurrently, for example.

InFIGS.6C and6D, a dielectric, such as a gate dielectric648that can be gate dielectric448, is formed over the structures ofFIGS.6C and6Dconcurrently. For example, gate dielectric648can be formed over each of monocrystalline semiconductor segments630-(N−2) to630-N and can wrap around a portion of each of monocrystalline semiconductor segments630-(N−2) to630-N so as to be adjacent to the upper surface and the sides of each of monocrystalline semiconductor segments630-(N−2) to630-N.

A conductor672, such as polysilicon, is then formed over (e.g., in direct physical contact with) gate dielectric648inFIGS.6C and6Dconcurrently such that conductor672wraps around a portion of each of monocrystalline semiconductor segments630-(N−2) to630-N. For example, conductor672can be adjacent to the upper surface and the sides of gate dielectric648that are adjacent to the upper surface and the sides of semiconductor segments630-(N−2) to630-N.

A conductor673, such as metal, is then formed over (e.g., in direct physical contact with) conductor672inFIGS.6C and6Dconcurrently such that conductor673wraps around a portion of each of monocrystalline segments630-(N−2) to630-N. For example, conductor673can be adjacent to the upper surface and the sides of conductor672that are adjacent to the upper surface and the sides of gate dielectric648. In some examples, conductor672and conductor673can collectively form a gate647that can be gate447.

A dielectric674that can be different from dielectric658is then formed over (e.g., in direct physical contact with) conductor673inFIGS.6C and6Dconcurrently such that dielectric674wraps around a portion of each of semiconductor segments630-(N−2) to630-N. For example, dielectric674can be adjacent to the upper surface and the sides of conductor673that are adjacent to the upper surface and the sides of gate conductor673. In some examples, dielectric674can be nitride when dielectric658is oxide and can be oxide when dielectric658is nitride.

FIG.6Eis a cross-section in the y-z plane, as viewed along any of the lines D-D inFIG.6C, corresponding to a particular stage of processing following the stage of processing corresponding toFIGS.6C and6D. For example, a mask (e.g., photoresist) can be formed over dielectric674inFIG.6Dand patterned to expose portions of dielectric674, conductor673, and conductor672for removal. The portions of dielectric674, conductor673, and conductor672can be subsequently removed (e.g., by etching), stopping in gate dielectric648to leave some of gate dielectric648over monocrystalline semiconductor segment630.

The removal process forms stacks675over monocrystalline semiconductor segment630that include gate dielectric648, conductor672over gate dielectric648, conductor673over conductor672, and dielectric674over conductor673. Subsequently, dielectric spacers677are formed on the (e.g., vertical) sides of stacks677. For example, dielectric spacers677can be formed on the (e.g., vertical) sides of dielectric674, conductor673, and conductor672and a portion of gate dielectric648. In some examples, dielectric spacers677can be the same dielectric as dielectric674. Spacers677can facilitate the formation of self-aligned conductive implants in monocrystalline semiconductor segment630in a subsequent processing stage.

FIG.6Fis a cross-section in the y-z plane, as viewed along any of the lines D-D inFIG.6C, corresponding to a particular stage of processing following the stage of processing corresponding toFIG.6E. InFIG.6F, the dielectric674and dielectric spacers677serve as a mask that protects stacks675while the portion of gate dielectric648that is not protected is removed from monocrystalline semiconductor segment630. Subsequently, conductive regions651(e.g., N− conductive implants) that can be conductive regions451are implanted in monocrystalline semiconductor segment630. For example, conductive regions651can be self-aligned as a result of spacers677.

FIG.6Gis a cross-section in the y-z plane, as viewed along any of the lines D-D inFIG.6C, corresponding to a particular stage of processing following the stage of processing corresponding toFIG.6F. InFIG.6G, mask elements679(e.g., of photoresist) are formed over stacks675and portions of conductive regions651. Subsequently, source/drains644and a source/drain645(e.g., N+ source/drains) that can be source/drains444and a source/drain445are implanted in portions of conductive regions651uncovered by mask elements679, extending into portions of monocrystalline semiconductor segment630that underlie the portions of conductive regions651uncovered by mask elements679. A channel region649that can be a channel region449can be between portions of conductive regions651covered by mask elements, and thus between a source/drain644and a source/drain645.

The adjacent string drivers640inFIG.6Gthat can be string drivers440can each include a respective portion of monocrystalline semiconductor segment630, including a respective source/drain644and shared source/drain645, and a stack675directly over a respective channel region649. Each respective string driver640can include a respective conductive region651between a respective channel649and a respective source/drain644and a respective conductive region651between the respective channel649and the source/drain645.

FIG.6His a cross-section in the x-z plane corresponding to a particular stage of processing following the stage of processing corresponding toFIG.6G.FIG.6Iis a cross-section in the y-z plane, as viewed along any one of the lines I-I inFIG.6H, corresponding to the particular stage of processing ofFIG.6H. As such, reference number630can be used inFIG.6Ito generally refer to each, or any, of monocrystalline semiconductor segments630-(N−2) to630-N. The structures inFIGS.6H and6Ican be formed concurrently, for example.

A dielectric681, such as a spin-on dielectric, can be formed concurrently over dielectric674inFIG.6Hand over string drivers640inFIG.6I. A portion of dielectric681can be subsequently removed, such as by chemical mechanical planarization (CMP), so that an upper surface dielectric681is coplanar with the uppermost surfaces of dielectric674.

A dielectric683, such as tetraethyl orthosilicate (TEOS), oxide, or the like, can then be formed over the upper surface dielectric681and the uppermost surfaces of dielectric674. A mask (not shown) can be formed over dielectric683and patterned to expose portions of dielectric683and dielectric681for removal. The portions can be subsequently removed (e.g., by etching) to form openings that can stop at or in conductor673and source/drain645.

A conductive contact660that can be a contact460can be formed in the opening that can stop at or in source/drain645so that contact660is in direct physical contact with source/drain645. A conductive contact684can be formed in the opening that can stop at or in conductor673so that contact684is in direct physical contact with conductor673. Conductive lines685and686can then be formed over dielectric683to be respectively in direct physical contact with contacts660and684. Conductive line685can be coupled to circuitry configured to supply access signals to string drivers640via source/drain645. Conductive line686can be coupled to logic circuitry, such as logic circuitry242or342, configured to supply control signals to conductor673, and thus to gate647, to activate the string drivers640commonly coupled thereto.

In some examples, source/drains644can be coupled to the access lines of steps of respective stairstep structures, as previously described in conjunction withFIGS.4B and4C. Note thatFIG.6Hcan correspond toFIG.4D, andFIG.6Ican correspond toFIG.4B.

FIG.7Ais a top-down view of a portion of a memory700A that can be various memories disclosed herein memory100in accordance with a number of embodiments of the present disclosure.FIG.7Bis a top-down view of a portion of a memory700B can be various memories disclosed herein in accordance with a number of embodiments of the present disclosure.FIG.7Cis a cross-section in the x-z plane viewed along any of the lines7C-7C inFIGS.7A and7B.

Memories700A and700B respectively include respective string drivers740A and740B that can be directly above stairstep structures, such as stairstep structures403-1and403-2respectively of blocks435-1and435-2. One of string drivers740A or one of the string drivers700B can be directly above and coupled to a step of a respective stairstep structure, such as stairstep structure403-1, and the other of the string drivers740A or the other of the string drivers740B can be directly above and coupled to a step of another respective stairstep structure, such as stairstep structure403-2.

String drivers740A can respectively include respective groups monocrystalline semiconductor fins788A (e.g., monocrystalline silicon fins) formed in respective portions of a monocrystalline semiconductor730A that can be a monocrystalline semiconductor430, monocrystalline semiconductor530, or a monocrystalline semiconductor segment630. A respective gate747can be over each respective group of fins788A. For example, the respective portions of the respective groups of monocrystalline semiconductor fins788A that are covered by a respective gate747can be respective channel regions749.

Each respective string driver740A can include a respective source/drain744A (e.g., an N+ source/drain) that can be analogous to a source/source drain444and that can be coupled to the step of the respective stairstep structure. For example, a respective contact790can couple each respective source/drain744A to the step of the respective stairstep structure. Note that the respective contacts790can be under their respective source/drains744A.

A source/drain745A (e.g., an N+ source/drain) that can be analogous to a source/drain445and that can be common to (e.g., shared by) the respective string drivers740A can be between the respective groups of fins788A. A contact792can couple source/drain745A to circuitry configured to supply access signals to the source/drain745A, and thus to the respective steps coupled to the respective string drivers740A upon activation of the respective string drivers740A. Note that contact792can be above source/drain745A.

In some examples, a respective conductive region793A (e.g., an N-region) can between a respective gate747and a respective source/drain744A. For example, the respective conductive region793A, including the portions of fins788A in the respective region793A, can be conductively doped (e.g., to an N-conductivity). In some examples, a respective conductive region794A (e.g., an N-region) can between a respective gate747and source/drain745A. For example, the respective conductive region794A, including the portions of fins788A in the respective region794A, can be conductively doped (e.g., to an N− conductivity).

InFIG.7B, a group of monocrystalline semiconductor fins788B is formed in a monocrystalline semiconductor730B that can be a monocrystalline semiconductor430, monocrystalline semiconductor530, or a monocrystalline semiconductor segment630. String drivers740B can respectively include respective portions of the group of monocrystalline semiconductor fins788B. For example, the group of monocrystalline semiconductor fins788B can be common to string drivers740B. A respective gate747of a respective string driver740B can be over the respective portion of the group of monocrystalline semiconductor fins788B. For example, the respective portions of the monocrystalline semiconductor fins788B that are covered by a respective gate747can be respective channel regions749.

Each respective string driver740B can include a respective source/drain744B (e.g., an N+ source/drain) that can be analogous to a source/source drain444and that can be coupled to the step of the respective stairstep structure. For example, each respective source/drain744B can include a respective portion of the group of fins788B such that the respective portion of the group of fins788B is conductively doped (e.g., to an N+ conductivity). A respective contact790can couple each respective source/drain744B to the step of the respective stairstep structure. Note that the respective contacts790can be under their respective source/drains744B.

A source/drain745B (e.g., an N+ source/drain) that can be analogous to a source/drain445and that can be common to (e.g., shared by) the respective string drivers740B can be between the respective control gates746. A contact792can couple source/drain745B to circuitry configured to supply access signals to the source/drain745B, and thus to the respective steps coupled to the respective string drivers740B upon activation of the respective string drivers740B. For example, source/drain745B can include a respective portion of the group of fins788B such that the respective portion of the group of fins788B is conductively doped (e.g., to an N+ conductivity). Note that contact792can be above source/drain745A.

In some examples, a respective conductive region793B (e.g., an N-region) can between a respective gate747and a respective source/drain744B. For example, the respective conductive region793B, including the portions of fins788A in the respective region793B, can be conductively doped (e.g., to an N-conductivity). In some examples, a respective conductive region794B (e.g., an N-region) can between a respective gate747and source/drain745B. For example, the respective conductive region794B, including the portions of fins788A in the respective region794B, can be conductively doped (e.g., to an N− conductivity).

InFIG.7C, the monocrystalline semiconductors730A and730B and the fins788A and788B inFIGS.7A and7Bare respectively generally referred to as monocrystalline semiconductor730and fins788. InFIG.7C, a dielectric758that can be dielectric458or dielectric658can be above a memory array706that can be various memory arrays disclosed herein. For example, dielectric758can be directly above a stairstep structure, such as stairstep structure103,403-1, or403-2and can extend above a memory-cell region of array706that can be various memory-cell regions disclosed herein.

A dielectric796that can be oxide can be formed over (e.g., in direct physical contact with) dielectric758. Monocrystalline semiconductor730can be above dielectric796, and thus can be directly above the stairstep structure or the memory-cell region. In some examples, monocrystalline semiconductor730can be attached to an upper surface of dielectric796as previously described in conjunction withFIGS.5A to5C. Fins788can be formed from monocrystalline semiconductor730so that fins788extend from an upper surface of dialectic796.

Respective gate dielectrics748that can be gate dielectrics448or648can be formed around the portions of the respective fins788. For example, a respective gate dielectric748can be in direct physical contact with a respective fin788and can be adjacent to the top and sides of the respective fin788. A gate747can be formed over (e.g., and in direct physical contact with) gate dielectrics748.

Gate747can be adjacent to the top and sides of the respective gate dielectrics748. This can increase the capacitive coupling area between gate747and fins788compared to the capacitive coupling area between a planar gate and a planar monocrystalline semiconductor. As such, for the same capacitive coupling area, the finned structure can take up less room in the x-direction than a planar structure, thereby allowing for higher string-driver densities (more string drivers) above array706.

FIG.8Ais a top-down view of a portion of a memory800, that can be various memories disclosed herein, in accordance with a number of embodiments of the present disclosure.FIGS.8B and8Care various cross-sectional views associated withFIG.8Ain accordance with a number of embodiments of the present disclosure.FIG.8Bis a cross-section in the x-z plane viewed along any of lines8B-8B inFIG.8A.FIG.8Cis a cross-section in the x-z plane viewed along any of lines8C-8C inFIG.8A.

Memory800includes respective sets of string drivers840-(N−2) to840-N that can be respectively directly above stairstep structures, such as stairstep structures403-1and403-2respectively of blocks435-1and435-2. For example, string drivers840-(N−2) to840-N can respectively replace string drivers440-(N−2) to440-N.

The string drivers840-(N−2) to840-N of the respective sets can be respectively directly above and respectively coupled to the steps827-(N−2) to827-N (shown inFIGS.8B and8C) of the respective stairstep structures. Note that the steps827-(N−2) to827-N can respectively include access lines814-(N−2) to814-N that can be access lines414-(N−2) to414-N and that can be respectively above dielectrics802that can be dielectrics102or402.

One string driver840from each set can include a respective portion of a monocrystalline semiconductor fin830. For example, a string driver840-(N−2) from each set can include a respective portion of fin830-(N−2); a string driver840-(N−1) from each set can include a respective portion of fin830-(N−1); and a string driver840-N from each set can include a respective portion of fin830-N. In some examples, fins830-(N−2) to830-N can respectively replace monocrystalline semiconductors430-(N−2) to430-N.

Each of the string drivers840from each set can include a respective source/drain844(e.g., an N+ source/drain) that can be analogous to a source/drain444and that can be coupled to the respective step of the respective stairstep structure. For example, a respective source/drain844of a respective string driver840can be formed in a respective portion of a respective fin830. A respective contact890can couple each respective source/drain844to a respective step. For example, source/drains844respectively in fins830-(N−2) to830-N can be respectively coupled to access lines814-(N−2) to814-N by contacts890, as shown inFIG.8C. Note that the respective contacts890can pass through their respective source/drains844.

A source/drain845(e.g., an N+ source/drain) that can be analogous to a source/drain445can be formed in each fin840between the respective string drivers corresponding to the respective fin840. For example, a source/drain845in fin830-(N−2) can be between and common to string drivers840-(N−2); a source/drain845in fin830-(N−1) can be between and common to string drivers840-(N−1); and a source/drain845in fin830-N can be between and common to string drivers840-N. A respective contact892can couple each respective source/drain845to circuitry configured to supply access signals to the respective source/drain845, and thus to the respective steps827coupled to the respective string drivers840sharing the respective source/drain845, upon activation of the respective string drivers840. Note that contacts892can be above their respective source/drains845.

A respective gate847that can be a gate447can be commonly coupled each set of string drivers840. The respective portions of fins830-(N−2) to830-N that are covered by a respective gate847can be respective channel regions849of the respective string drivers of a respective set. In some examples, the respective gates847can be coupled to receive control signals for activating the string drivers840coupled to the respective gates847. Note that string drivers840can be finFETs.

Respective conductive regions850(e.g., N− regions) that can be analogous to conductive regions450can be formed in each respective fin830respectively between gates847and source/drains844. Respective conductive regions851(e.g., N− regions) that can be analogous to conductive regions451can be formed in each respective fin830respectively between gates847and source/drain845.

InFIGS.8B and8C, a dielectric858that can be dielectric458or dielectric658can be directly above a stairstep structure803that can be a portion of stairstep structure103or a stairstep structure403. For example, dielectric858can be above a dielectric856that can be dielectric456and that can be over stairstep structure803. A dielectric896that can be oxide can be formed over (e.g., in direct physical contact with) dielectric858. Fins830can be formed from a monocrystalline semiconductor that can be attached to an upper surface of dielectric896as previously described in conjunction withFIGS.5A to5C. Fins830can extend from the upper surface of dielectric896.

Respective gate dielectrics848that can be gate dielectrics448,648, or748can be formed around portions of the respective fins830. For example, a respective gate dielectric848can be in direct physical contact with a respective fin830and can be adjacent to the top and sides of the respective fin830.

A gate847can be formed over (e.g., and in direct physical contact with) gate dielectrics848. Gate847can be adjacent to the top and sides of the respective gate dielectrics848. This can increase the capacitive coupling area between gate847and fins830compared to the capacitive coupling area between a planar control gate and a planar monocrystalline semiconductor. This allows for higher string-driver densities so that a respective string driver can be directly above each respective step827and coupled to each respective step by a straight contact890, as shown inFIG.8C. For example, the respective contacts890can pass through their respective source/drains844.

FIG.9is a cross-sectional view in the x-z plane of a portion of a memory900, that can be a portion of various memories disclosed herein, in accordance with a number of embodiments of the present disclosure.

Memory900can include a stacked memory array906that can be a portion of stacked memory array106, for example. Array906can include a memory-cell region901that can be a portion of memory-cell region101and a stairstep structure903adjacent to memory-cell region901that can be a portion of stairstep structure103. A group of string drivers940-1to940-N can be directly above stairstep structure903. For example, string drivers940can be various string drivers disclosed herein.

Stairstep structure903can include steps927-1to927-N that can be between and uppermost step916and a lowermost step916. Array906can include a (e.g., vertical) stack of access lines914-1to914-N in the z-direction such that steps927-1to927-N respectively include access lines914-1to914-N. Each step927can include a respective access line914over a respective dielectric902. Uppermost step916can include an upper select line912over a dielectric902, and lowermost step916can include a lower select line914over a dielectric902that can be over a semiconductor907that can be semiconductor107.

String drivers940-1to940-N can be respectively directly over and coupled to access lines914-1to914-N. In some examples, string drivers940-1to940-N can respectively include monocrystalline semiconductors930-1to930-N than can be monocrystalline semiconductors430, monocrystalline semiconductors430, monocrystalline semiconductor segments630, finned monocrystalline semiconductors730A, finned monocrystalline semiconductors730B, or monocrystalline semiconductor fins830.

String drivers940-1to940-N, and thus monocrystalline semiconductors930-1to930-N, can be over a dielectric958that can be dielectric458,658,758, or858and that can be over memory-cell region901and stairstep structure903, and thus over array906. For example, dielectric958can be over a dielectric956that can be dielectric456or856and that can be over memory-cell region901and stairstep structure903. Monocrystalline semiconductors930-1to930-N are respectively coupled to steps927-1to927-N by contacts929-1to929-N.

Access lines914-1to914-N can be respectively coupled to memory cells910-1to910-N. Memory cells910-1to910-N can be coupled in series to form a string of series-coupled memory cells that can be adjacent to a semiconductor structure905(e.g., that can pass vertically through memory cell region901) that can be a semiconductor structure105.

The string can be between a select transistor908and select transistor909. For example, select transistor908can be at an intersection of upper select line912and semiconductor structure905, and select transistor909can be at an intersection of lower select line912and semiconductor structure905.

Each of memory cells910-1to910-N can include a charge-storage structure9101, such as a charge trap or a floating gate, e.g., at the intersection of semiconductor structure905and a respective access line910. Each of memory cells910-1to910-N can include a dielectric9103, such as a blocking dielectric, that can be between a respective access line914and a respective charge-storage structure9101. For example, a dielectric9103of memory cell910-imay be between access line914-iand the charge-storage structure9101of memory cell910-i.

Each of memory cells910-1to910-N can include a dielectric9105, such as a tunnel dielectric, that can be between a respective charge-storage structure9101and semiconductor structure905. For example, a dielectric9105of memory cell910-ican be between the charge-storage structure9101of memory cell910-iand semiconductor structure905. Dielectric9103, charge-storage structure9101, and dielectric9105can wrap completely around semiconductor structure905, for example, and can be at the intersection of an access line914and semiconductor structure905.

Select transistor909can include a control gate that can be included in the lower select line912. A dielectric9108, such as a gate dielectric, of select transistor909can be between lower select line912and semiconductor structure905. Lower select line912and dielectric9108, and thus select transistor909, can wrap completely around semiconductor structure905, for example.

Select transistor908can include a control gate that can be included in the upper select line912. A dielectric9110, such as a gate dielectric, of select transistor908can be between upper select line912and semiconductor structure905. Upper select line912and dielectric9110, and thus select transistor908, can wrap completely around semiconductor structure905, for example. A data line922can be coupled to an end of semiconductor structure905, and thus to select transistor908, by a contact924, for example.

FIG.10is a block diagram of an apparatus in the form of a computing system10120in accordance with a number of embodiments of the present disclosure. Computing system10120includes a memory system10122that can be, for example, a storage system such as an SSD, a UFS device, an eMMC device, etc. However, embodiments are not limited to a particular type of memory system. For example, memory system10122could serve as main memory for system10120.

As shown inFIG.10, memory system10122can include a controller10125that may be referred to as a memory system controller, in that controller10125can control a memory10128that can be various memories disclosed herein. Controller10125is coupled to a host10130and to memory10128. For example, memory10128can include a number of memory devices (e.g., dies, chips, etc.) and can serve as a memory (e.g., main memory) and/or as a storage volume for computing system10120.

Memory10128can be coupled to controller10125via an interface10133(e.g., memory interface) that can include a data bus and that can support various standards and/or comply with various interface types, such as double data rate (DDR), etc. Controller10125can receive commands, such as read and write commands from host10130. Controller10125can, for example, receive host data to be written to memory10122from host10130via a host interface10137. As used herein, a memory system10122, a controller10125, a memory10128, or a controller10140might also be separately considered an “apparatus.”

Host10130can be, for example, a host system, such as a personal laptop computer, a desktop computer, a digital camera, a mobile device (e.g., cellular phone), network server, Internet of Things (IoT) enabled device, or a memory card reader, among various other types of hosts. For instance, host10130can include one or more processors capable of accessing memory10128(e.g., via controller10125) over interface10137that can include a bus. Interface10137may be a standardized interface, such as a serial advanced technology attachment (SATA), peripheral component interconnect express (PCIe), or a universal serial bus (USB), among various others.

Memory10128can include a number of memory arrays1006(e.g., referred to collectively as array1006) and a controller10140that may be referred to as an embedded controller. In some examples, array1006can be a stacked memory array (e.g., a 3D NAND array) that can be array106or906. String drivers, such as various string drivers disclosed herein. can be above memory array1006. For example, memory array1006can include a stairstep structure. Steps of the stairstep structure can be respectively commonly coupled to respective levels of non-volatile memory cells in memory array1006. The respective string drivers above memory array1006can include respective monocrystalline semiconductor structures respectively coupled to the steps.

Controller10140can be located internal to the memory10128, and can receive commands (e.g., write commands, read commands, etc.) from the controller10125via the memory interface10133. Controller10140can include a state machine and/or a sequencer. Controller10140can be configured to control the operation of memory10128.

In the preceding detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific examples. In the drawings, like numerals describe substantially similar components throughout the several views. Other examples may be utilized, and structural, logical, and/or electrical changes may be made without departing from the scope of the present disclosure.

The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, 130 may reference element “30” inFIG.1, and a similar element may be referenced as430inFIG.4A. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, as will be appreciated, the proportion and the relative scale of the elements provided in the figures are intended to illustrate the embodiments of the present disclosure and should not be taken in a limiting sense.

As used herein, “a number of” or a “quantity of” something can refer to one or more of such things. For example, a number of or a quantity of memory cells can refer to one or more memory cells. A “plurality” of something intends two or more. As used herein, multiple acts being performed concurrently refers to acts overlapping, at least in part, over a particular time period. As used herein, the term “coupled” may include electrically coupled, directly coupled, and/or directly connected with no intervening elements (e.g., by direct physical contact), indirectly coupled and/or connected with intervening elements, or wirelessly coupled. The term coupled may further include two or more elements that co-operate or interact with each other (e.g., as in a cause and effect relationship).

Although specific examples have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. The scope of one or more examples of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.