Patent ID: 12259662

DETAILED DESCRIPTION

FIG.1is a schematic sectional view of a semiconductor device according to some exemplary embodiments of the disclosure.

Referring toFIG.1, in some embodiments, a semiconductor device10may include a semiconductor substrate100, and a semiconductor device layer including a plurality of circuit patterns may be stacked on the semiconductor substrate100.

For example, the semiconductor substrate100may include silicon (Si). In some embodiments, the semiconductor substrate100may be a wafer including silicon. Alternatively, the semiconductor substrate100may include a semiconductor element such as germanium (Ge) or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). Otherwise, the semiconductor substrate100may have a silicon-on-insulator (SOI) structure. For example, the semiconductor substrate100may include a buried oxide layer (BOX layer). The semiconductor substrate100may include a conductive region, such as a well doped with impurities, or a structure doped with impurities. In addition, the semiconductor substrate100may have various element isolation structures such as a shallow trench isolation (STI) structure.

The semiconductor device layer may include an integrated circuit in which a plurality of circuit patterns are stacked. In some embodiments, the semiconductor device layer may include a first insulating layer200, a first layer300, a second insulating layer400, and a second layer500. For example, the first insulating layer200may be on the semiconductor substrate100, the first layer300may be on the first insulating layer200, the second insulating layer400may be on the first layer300, and the second layer500may be on the second insulating layer400.

In some embodiments, at least one of the first insulating layer200and the second insulating layer400may be omitted from the semiconductor device10. For example, the first layer300may be directly on the semiconductor substrate100. For example, the second layer500may be directly on the first layer300.

In some embodiments, in the semiconductor device10, other layers may be included among the semiconductor substrate100, the first insulating layer200, the first layer300, the second insulating layer400and the second layer500. For example, at least one additional insulating layer, at least one wiring layer or at least one semiconductor layer may be between the first layer300and the second layer500.

As an example, each of the first insulating layer200and the second insulating layer400may function as an interlayer insulating layer. Each of the first insulating layer200and the second insulating layer may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and/or a low-k dielectric having a lower permittivity than the silicon oxide, without being limited thereto. The first insulating layer200and the second insulating layer400may include different materials, in some embodiments.

In some embodiments, the first insulating layer200and the second insulating layer400may each function as a buffer layer configured to reduce stress caused by a lattice constant difference between layers adjacent thereto (for example, the semiconductor substrate100and the first layer300, or the first layer300and the second layer500). In some embodiments, each of the first insulating layer200and the second insulating layer400may function as a barrier layer configured to prevent impurities such as hydrogen (H), etc. from being diffused from layers adjacent thereto into other layers, and to prevent current flowing in the adjacent layers from leaking to other layers.

In some embodiments, elements may be arranged within the first layer300and/or the second layer300, and each element of the first layer300and the second layer500may be a pattern array structure having a fine pitch and a fine width. For example, each of the first layer300and the second layer500may be a layer formed with an element constituting a transistor or various wirings. For example, each of the first layer300and the second layer500may include a semiconductor material or a conductive material. In some embodiments, the first layer300may correspond to the above-described semiconductor substrate100.

At least one of the first layer300and the second layer500may include a cell pattern520constituting an integrated circuit. The cell pattern520may be formed to have a pitch in a predetermined range, for reliability. There may be a high possibility that, during a process of manufacturing the cell pattern520, the pitch shifts or deviates from a target value, and as such it is desirable that a shift degree of the pitch be measured in an accurate manner for reliability.

In some embodiments, patterns formed at the first layer300may be used in measuring the pitch of patterns formed at the second layer500. In some embodiments, the patterns formed at the second layer500may be used in measuring the pitch of the patterns formed at the first layer300.

In some embodiments, the distance (for example, the height difference) between the first layer300and the second layer500may be 2 μm or less. For example, when the distance between the first layer300and the second layer500is 2 μm or less, variations in measurement values that are dependent on distance may be relatively unimportant (or even ignorable) when measuring the pitch of the patterns formed at the second layer500. In addition, in some embodiments, when the distance between the first layer300and the second layer500is 2 μm or less, measurement of the pitch of patterns formed at the second layer500may be performed using a single focus.

The exemplary embodiments of the present disclosure are not limited to a particular distance between the first layer300and the second layer500. For example, when the distance between the first layer300and the second layer500exceeds 2 μm in accordance with some embodiments, the pitch of the patterns formed at the second layer500may be measured using multiple focuses (for example, a double focus).

In some embodiments, the first layer300may include a first comparative pitch pattern310and a second comparative pitch pattern320. The first comparative pitch pattern310and the second comparative pitch pattern320may be arranged adjacent to each other, although the present disclosure is not limited thereto.

The first comparative pitch pattern310may be a pattern array structure in which pattern structures having a predetermined line width are formed to have a first pitch. The second comparative pitch pattern320may be a pattern array structure in which pattern structures having a predetermined line width are formed to have a second pitch. In some embodiments, values of the first pitch and the second pitch may be different.

In some embodiments, the second layer500may include a key pattern510, a middle pitch pattern530, and a cell pattern520.

The key pattern510may be a pattern array structure in which pattern structures having a predetermined line width are formed to have a third pitch. In some embodiments, the key pattern510may overlap with the first comparative pitch pattern310in a vertical direction (or a height direction). In some embodiments, at least a partial region of the key pattern510may be arranged so as to overlap with at least a partial region of the first comparative pitch pattern310. The entire region of the key pattern510may overlap with at least a partial region of the first comparative pitch pattern310. In some embodiments, the area (e.g., a layout area when viewed in a plan view) of the key pattern510may be smaller than the area of the first comparative pitch pattern310.

The cell pattern520in the second layer500may include a pattern constituting an integrated circuit of the semiconductor device10. The cell pattern520may be a pattern array structure in which pattern structures having a predetermined line width are formed to have a fourth pitch. In some embodiments, the cell pattern520may be arranged so as to be spaced apart from the key pattern510in the second layer500. In some embodiments, the cell pattern520may overlap with the second comparative pitch pattern320in the vertical direction (or the height direction). In some embodiments, at least a partial region of the cell pattern520may overlap with a partial region of the second comparative pitch pattern320. In some embodiments, the area of the cell pattern520may be smaller than the area of the second comparative pitch pattern320.

The middle pitch pattern530may be a pattern array structure in which pattern structures having a predetermined line width are formed to have a fifth pitch. The middle pitch pattern530may be used to measure a pitch formed at the cell pattern520with reference to the key pattern510. In some embodiments, the middle pitch pattern530may be between the key pattern510and the cell pattern520in the second layer500. In some embodiments, a portion of the middle pitch pattern530may overlap with the first comparative pitch pattern310in the vertical direction (or the height direction). In some embodiments, the portion (a first region) of the middle pitch pattern530may overlap with a partial region of the first comparative pitch pattern310. In some embodiments, another portion (a second region) of the middle pitch pattern530may overlap with the second comparative pitch pattern320in the vertical direction (or the height direction). In some embodiments, the other portion (second region) of the middle pitch pattern530may overlap with a partial region of the second comparative pitch pattern320. In some embodiments, the area of the middle pitch pattern530may be equal to or greater than the area of the key pattern510.

In some embodiments, the third pitch of key pattern510may have a minimum or maximum value from among the first to fifth pitches, and, corresponding thereto, the fourth pitch cell pattern520may have the other of the maximum or minimum value from among the first to fifth pitches. In this case, the fifth pitch of the middle pitch pattern530may have a value between the third pitch and the fourth pitch. In this case, the first pitch of the first comparative pitch pattern310may have a value between the third pitch and the fifth pitch. In this case, the second pitch of the second comparative pitch pattern320may have a value between the fourth pitch and the fifth pitch.

In some embodiments, at least one of the key pattern510and the middle pitch pattern530may be omitted from the second layer500.

Hereinafter, a method for manufacturing the semiconductor device10that includes a procedure of measuring a pitch or a pitch shift of the cell pattern520formed at the second layer500, will be described. In some embodiments, the pitch shift (or the pitch) of the cell pattern520may be measured through an exposure pattern for formation of the cell pattern520in a procedure of manufacturing the second layer500.

FIG.2is a flowchart explaining a method for manufacturing a semiconductor device in accordance with some exemplary embodiments of the disclosure.FIGS.3to5are views explaining a procedure of measuring a pitch shift of a cell pattern. Here,FIG.3shows a sectional view of a semiconductor device10ain a part of procedures in a method for manufacturing the semiconductor device10shown inFIG.1.

Referring toFIG.2, the manufacturing method of the semiconductor device10amay include a first-layer formation operation S110, an exposure/development operation S210, a pitch measurement operation S130, and an etching operation S140. Here, the exposure/development operation S120, the pitch measurement operation S130, and the etching operation S140may be included in a procedure of forming the second layer500.

For convenience of understanding, a procedure of manufacturing the semiconductor substrate100and a procedure of manufacturing the first insulating layer200and the second insulating layer400are omitted from the following manufacturing method of the semiconductor device10a. Although not described clearly in the following description, for example, the manufacturing method of the semiconductor device10amay include a procedure of sequentially forming (for example, stacking) a semiconductor device100, a first insulating layer200, a first layer300, a second insulating layer400and a second layer500.

Referring toFIGS.1to4, the first-layer formation operation S110corresponds to a procedure of forming the first layer300which includes a plurality of comparative pitch patterns (for example, the first comparative pitch pattern310and the second comparative pitch pattern320ofFIG.1).

In some embodiments, an exposure/development process and an etching process may be included in the procedure of forming the first layer300. For example, the formation procedure of the first layer300may use a process (photolithography) of irradiating a resist film on a deposition material with light of a particular wavelength (exposure), thereby generating chemical structure variation of the resist film, selectively removing an exposed portion or an unexposed portion of the resist film using a solubility difference between the exposed portion and the unexposed portion (development), and removing a portion of the deposition material not overlapping with the remaining portion of the resist film (etching).

For example, the first layer300may be formed by first performing an exposure/development process at least one time, and then performing an etching process at least one time after the exposure process. In another example, the first layer300may be formed by repeatedly performing an exposure/development processes and etching processes. Here, the exposure/development process and the etching processes may use well-known methods used in manufacture of the semiconductor device10a.

In some embodiments, the procedure of forming the second layer500may include the exposure/development operation S120of at least one time, the pitch measurement operation S130at least one time, and the etching operation S140. For example, the formation procedure of the second layer500may include a photolithography process, similarly to the formation procedure of the first layer300.

As seen inFIG.3, in some embodiments, the second layer500may be a structure in which a deposition material layer501, a mask layer502, and a resist film503are sequentially stacked in the formation procedure of the second layer500. In some embodiments, the mask layer502may be omitted.

In some embodiments, the second layer500may be formed through the exposure/development operation S120performed at least one time, the pitch measurement operation S130performed at least one time, and the etching operation S140, The second layer500may include the key pattern510, the middle pitch pattern530and the cell pattern520described with reference toFIG.1.

In some embodiments, the exposure/development operation S120corresponds to a procedure of performing an exposure process and a development process at positions of the second layer500where the key pattern510, the cell pattern520and the middle pitch pattern530will be formed. Each of the key pattern510, the cell pattern520and the middle pitch pattern530has a predetermined line width and a predetermined pitch. As the exposure/development operation S120is performed, exposure patterns510a,520aand530arespectively corresponding to the key pattern510, the cell pattern520and the middle pitch pattern530may be formed at or in the resist film503.

The first exposure pattern510acorresponding to the key pattern510may be a pattern array structure in which pattern structures having a predetermine line width are formed to have a third pitch. The third pitch of the first exposure pattern510amay have the same value as the third pitch of the key pattern510. The first exposure pattern510amay be a reference for measurement of a pitch formed at the second exposure pattern520acorresponding to the cell pattern520. In some embodiments, the first exposure pattern510amay overlap with the first comparative pitch pattern310in the vertical direction (or the height direction). In some embodiments, the entire region of the first exposure pattern510amay overlap with a partial region of the first comparative pitch pattern310. In some embodiments, the area of the first exposure pattern510amay be smaller than the area of the first comparative pitch pattern310.

The second exposure pattern520acorresponding to the cell pattern520may include a pattern constituting, in the second layer500, an integrated circuit of the semiconductor device10a. The second exposure pattern520amay be a pattern array structure in which pattern structures having a predetermined line width are formed to have a fourth pitch. The fourth pitch of the second exposure pattern520amay have the same value as the fourth pitch of the cell pattern520. In some embodiments, the second exposure pattern520amay be spaced apart from the first exposure pattern510ain the second layer500. In some embodiments, the second exposure pattern520amay overlap with the second comparative pitch pattern320in the vertical direction (or the height direction). In some embodiments, at least a partial region of the second exposure pattern520amay overlap with a partial region of the first comparative pitch pattern310. In some embodiments, the area of the first exposure pattern510amay be smaller than the area of the first comparative pitch pattern310. In some embodiments, at least a partial region of the second exposure pattern520amay be disposed to overlap with a partial region of the second comparative pitch pattern320. In some embodiments, the area of the second exposure pattern520amay be smaller than the area of the second comparative pitch pattern320.

The third exposure pattern530acorresponding to the middle pitch pattern530may be a pattern array structure in which pattern structures having a predetermined line width are formed to have a fifth pitch. The fifth pitch of the third exposure pattern530amay have the same value as the fifth pitch of the middle pitch pattern530. The third exposure pattern530amay be used to measure a pitch formed at the second exposure pattern520awith reference to the first exposure pattern510a. In some embodiments, the third exposure pattern530amay be between the first exposure pattern510aand the second exposure pattern520a. In some embodiments, a portion of the third exposure pattern530amay overlap with the first comparative pitch pattern310in the vertical direction (or the height direction). In some embodiments, the portion (a first region) of the third exposure pattern530amay overlap with a partial region of the first comparative pitch pattern310. In some embodiments, another portion (a second region) of the third exposure pattern530amay overlap with the second comparative pitch pattern320in the vertical direction (or the height direction). In some embodiments, the other portion (second region) of the third exposure pattern530amay overlap with a partial region of the second comparative pitch pattern320. In some embodiments, the area of the third exposure pattern530amay be equal to or greater than the area of the first exposure pattern510a.

In some embodiments, the exposure patterns510a,520aand530amay be simultaneously formed in the exposure/development operation S120. In some embodiments, different exposure processes performed at positions where the exposure patterns510a,520aand530awill be formed may be performed at different times.

The pitch measurement operation S130may correspond to a procedure of measuring a shift degree of the pitch of the second exposure pattern520athrough a Moiré effect (seeFIG.5) generated due to overlap of the patterns formed at the first layer300(for example, the comparative pitch patterns310and320) with the exposure patterns510a,520aand530aformed at the second layer500.

Since the pitch of the second exposure pattern520amay be measured by measuring the shift degree of the pitch of the second exposure pattern520ain the pitch measurement operation S130, the terms “the shift degree of the pitch of the pattern” and “the pitch of the pattern” are used as similar meanings without being distinguished from each other.

For example, when patterns respectively having two pitches (for example, P and Q) finely different from each other overlap each other (for example, the patterns being the first comparative pitch pattern310of the first layer300and the first exposure pattern510aof the second layer500), a Moiré effect (seeFIG.5) may be exhibited due to the two pitches, and a pitch x of a Moiré pattern may be calculated through application of the following Expression 1. In this case, the two pitches (for example, P and Q) finely different from each other should be within a pitch difference range in which the Moiré pattern will be formed.

x=PQP-Q[Expression⁢1]

For example, assuming that pitches (target values) of two patterns X and Y (for example, the first exposure pattern510aand the second exposure pattern520a) formed at a particular layer (for example, the second layer500) are PXand PY, respectively, and shift degrees of the pitches PXand PYof the two patterns X and Y are dXand dY, respectively, the following Expression 2 may be applied.

dX=1xX⁢PX⁢MX+LX⁢dY=1xY⁢PY⁢MY+LY[Expression⁢2]

In Expression 2, MXand MYrepresent pitch shift degrees of the Moiré pattern (for example, shift degrees of the Moiré pattern from a predetermined pitch), and LXand LYrepresent shift degrees of pitches of patterns (for example, the first comparative pitch pattern310and the second comparative pitch pattern320) formed at a layer (for example, the first layer300) different from the above-described layer while overlapping with the above-described two patterns X and Y.

For example, assuming that two patterns X and Y formed at a particular layer (for example, the second layer500) are the first exposure pattern510aand the third exposure pattern530a, respectively, LXand LYmay be shift degrees of the pitch of the first comparative pitch pattern310overlapping with both the first exposure pattern510aand the third exposure pattern530a, respectively, and, as such, LXand LYmay have the same value.

In some embodiments, each pitch difference of the first exposure pattern510aand the second exposure pattern520amay be equal to or greater than a predetermined value, and as a result a Moiré pattern might not be generated in association with the same pattern formed at the first layer300(for example, in the case in which, although a Moiré pattern may be generated between the first exposure pattern510aand one pattern of the first layer300, no Moiré pattern may be generated between the second exposure pattern520aand the pattern of the first layer300due to an excessive pitch difference). Accordingly, in some embodiments the third exposure pattern530amay be introduced for calculation (e.g., relatively easy calculation) of the shift degree of the pitch of the second exposure pattern520afrom the first exposure pattern510a.

For example, a pitch shift of a Moiré pattern between the first pattern X formed at the second layer500(for example, the first exposure pattern510a) and the second pattern Y formed at the second layer500(for example, the third exposure pattern530a) may be measured through one pattern of the first layer300(for example, the first comparative pitch pattern310) overlapping with both the first pattern X and the second pattern Y. In addition, a pitch shift of a Moiré pattern between the second pattern Y formed at the second layer500(for example, the third exposure pattern530a) and a third pattern Z formed at the second layer500(for example, the second exposure pattern520a) may be measured through another pattern of the first layer300(for example, the second comparative pitch pattern320) overlapping with both the second pattern Y and the third pattern Z. Thereafter, a pitch shift of a Moiré pattern between the patterns X and Z may be finally calculated using a measured value of the pitch shift of the Moiré pattern between the patterns X and Y and a measured value of the pitch shift of the Moiré pattern between the patterns Y and Z.

In the following description, reference symbols are defined as in the following Table 1, for convenience of description, and a method of calculating a pitch shift of the second exposure pattern520athrough application of Expressions 1 and 2 will be described. To be finally derived through this calculation method is a difference between the pitch shift of the second exposure pattern520aand the pitch shift of the first exposure pattern510a.

TABLE 1Moiré PatternPredetermined PitchMeasurementSecond Layer 500First Layer 300of Moiré PatternFirst MeasurementSecond ExposureSecond Comparativeabetween A and θ2Pattern (A)Pitch Pattern 320 (θ2)Second MeasurementThird ExposureSecond Comparativeabetween B and θ2Pattern (B)Pitch Pattern 320 (θ2)Third MeasurementThird ExposureFirst Comparativeabetween C and θ2Pattern (C)Pitch Pattern 310 (θ1)Fourth MeasurementFirst ExposureFirst Comparativeabetween D and θ1Pattern (D)Pitch Pattern 310 (θ1)

Reference is made toFIG.4for the positions of A to D in Table 1. In Table 1, the third exposure pattern530a(B) refers to a region overlapping with the second comparative pitch pattern320, and the third exposure pattern530a(C) refers to a region overlapping with the first comparative pitch pattern310. Shift degrees dA, dB, dCand dDof respective patterns A, B, C and D may be expressed by the following Expression 3, corresponding to Expression 2.

[Expression⁢3]dA=1xA⁢PA⁢MA+LA(1)dB=1xB⁢PB(-MB)+LB(2)dC=1xC⁢PC⁢MC+LC(3)dD=1xD⁢PD(-MD)+LD(4)

Thereafter, expressions (1) to (4) in Expression 3 may be sequentially calculated as expressed in the following Expression 4 and, as such, an expression (8) may be expressed by the following Expression 5.

[Expression 4]
(1)−(2)  (5)
(2)−(3)  (6)
(3)−(4)  (7)
(5)+(6)+(7)  (8)

dA-dD=1x⁢(PA⁢MA+PB⁢MB+PC⁢MC+PD⁢MD)[Expression⁢5]

In Expression 4, LA=LB(for θ2) and LC=LD(for θ2) because LAand LBare associated with the same comparative pitch pattern, and LCand LDare associated with the same comparative pitch pattern. In addition, in Expression 4, dB=dCbecause dBand dCare associated with the same middle pitch pattern530. In addition, predetermined pitches xA, xB, xCand xDof Moiré patterns have a value of a and, as such, are equal (a=xA=xB=xC=xD). Accordingly, the expression (8) in Expression 4 may be expressed by Expression 5. As such, a difference dA−dDbetween the pitch shift of the second exposure pattern520aand the pitch shift of the first exposure pattern510amay be derived on the basis of measured Moiré patterns, through Expressions 3 to 5. The pitch shift of the first exposure pattern510amay be measured (calculated) in accordance with a relation thereof with the first comparative pitch pattern310and, as such, the pitch shift of the second exposure pattern520amay be estimated.

In some embodiments, in the pitch measurement operation S130, whether or not the difference between the pitch shift of the second exposure pattern520aand the pitch shift of the first exposure pattern510ais within a (predetermined) tolerance range may be determined. In other words, in the pitch measurement operation S130, whether or not the pitch shift (or the pitch) of the second exposure pattern520ais within a tolerance range may be determined.

In some embodiments, upon determining, in the pitch measurement operation S130, that the pitch shift of the second exposure pattern520ais within the tolerance range, the etching operation S140may be performed. When determined, in the pitch measurement operation S130, the pitch shift of the second exposure pattern520aexceeds the tolerance range, the exposure/development operation S120and the pitch measurement operation S130may be again performed.

The etching operation S140corresponds to a procedure of performing an etching process for the second layer500, which has been completely subjected to exposure and development. As the second layer500has been subjected to the etching operation S140, the cell pattern520, which has a pitch within a tolerance range, may be formed at the deposition material layer501of the second layer500. In this case, the mask layer502and the resist film503may be removed.

In some embodiments, a pitch shift of an exposure pattern (for example, the second exposure pattern520a) corresponding to the cell pattern520was measured through introduction of an exposure pattern (for example, the third exposure pattern530a) corresponding to one middle pitch pattern530. In some embodiments, it may be possible to measure a pitch shift of the second exposure pattern520athrough introduction of exposure patterns corresponding to a plurality of middle pitch patterns530between the second exposure pattern520aand the first exposure pattern510a.

FIG.6is a flowchart explaining an exposure procedure in the semiconductor device manufacturing method according to some exemplary embodiments of the disclosure.FIGS.7and8are views explaining procedures ofFIG.6, respectively.

Referring toFIG.6, in some embodiments, the exposure/development operation S120may include middle pitch pattern determination operations S121and S123of at least one time, and pitch range checking operations S122and S124of at least one time.

The middle pitch pattern determination operation S121corresponds to a procedure of determining a position and a pitch of the first middle pitch pattern530. In some embodiments, the pitch of the first middle pitch pattern530may be determined to be a value between the pitch of the cell pattern520and the pitch of the key pattern510. In some embodiments, the position of the first middle pitch pattern530may be determined to be between the position of the cell pattern520and the position of the key pattern510.

After the first middle pitch pattern determination operation S121, the pitch range checking operation S122may be performed. The pitch range checking operations S122and S124correspond to a procedure of checking whether or not each of pitch differences between the first middle pitch pattern530and patterns adjacent thereto at opposite sides thereof corresponds to a range in which a Moiré pattern will be formed. For example, whether or not the pitch difference between the first middle pitch pattern530and the cell pattern520corresponds to the Moiré pattern formation range and whether or not the pitch difference between the first middle pitch pattern530and the key pattern510corresponds to the Moiré pattern formation range may be checked.

When both the pitch differences between the first middle pitch pattern530and the patterns adjacent thereto at opposite sides thereof correspond to the Moiré pattern formation range, an exposure process operation S125may be performed.

On the other hand, when at least one of the pitch differences between the first middle pitch pattern530and the patterns adjacent thereto at opposite sides thereof is beyond the Moiré pattern formation range, additional middle pitch pattern determination operation S123may be performed.

Referring toFIGS.6and7, in the additional middle pitch pattern determination operation S123, a position and a pitch of an additional middle pitch pattern530to be introduced between patterns having a pitch difference beyond the Moiré pattern formation range from among the first middle pitch pattern530and the patterns adjacent thereto at opposite sides thereof may be determined. The position of the additional middle pitch pattern530may be determined to be between the first middle pitch pattern530and the adjacent pattern, which has a pattern difference beyond the Moiré pattern formation range with respect to the first middle pitch pattern530. The pitch of the additional middle pitch pattern530may be determined to be between the pitch of the first middle pitch pattern530and the pitch of the adjacent pattern, which has a pattern difference beyond the Moiré pattern formation range with respect to the first middle pitch pattern530.

Referring toFIGS.6and8, in some embodiments, after the additional middle pitch pattern determination S123, the pitch range checking operations S122and S124and the additional middle pitch pattern determination operation S123may be repeated. When the pitch range checking operations S122and S124and the additional middle pitch pattern determination operation S123are repeated a plurality of times, exposure patterns of a plurality of middle pitch patterns530and531may be formed between the second exposure pattern520aand the first exposure pattern510ain the second layer. In this case, in some embodiments, the first layer may include a plurality of comparative pitch patterns310,320,330and340.

FIG.9is a plan view schematically showing a semiconductor substrate according to some exemplary embodiments of the disclosure.FIGS.10to12are enlarged views of a semiconductor die ofFIG.9in accordance with some embodiments.

Referring toFIGS.9to12, a semiconductor substrate100may include a plurality of shot areas SA. Each of the shot areas SA may be an area of the semiconductor substrate100that is exposed by an exposure process at one time. For example, each shot area SA may include one chip area CA, or may include a plurality of chip areas CA. A scribe lane area SL may be arranged among or between the chip areas CA. The chip areas CA may be defined by the scribe lane area SL.

Each of the chip areas CA may include a plurality of circuit regions20. The circuit regions20may include a logic circuit region20a, a memory region20band an input/output device region20c, as examples. Here, the chip area CA may also be referred to as an “in-cell area.” In some embodiments, the logic circuit region20a, the memory region20band the input/output device region20cmay have the same pitch. In some embodiments, at least one of the logic circuit region20a, the memory region20band the input/output device region20cmay include the function of the above-described cell pattern520(seeFIG.1). InFIGS.10to12, a key pattern21may correspond to the key pattern510ofFIG.1, and a middle pitch pattern22may correspond to the middle pitch pattern530ofFIG.1.

In some embodiments, as shown inFIG.10, the middle pitch pattern22and the key pattern21may be formed in the chip area CA, as well as the at least one of the logic circuit region20a, the memory region20band the input/output device region20cthat includes the function of the above-described cell pattern520.

In some embodiments, as shown inFIGS.11and12, at least one of the middle pitch pattern22and the key pattern21may be formed in the scribe lane area SL.

FIG.13is an enlarged view of the semiconductor die ofFIG.9according to some embodiments.

Referring toFIG.13, a part of the plurality of circuit regions20may be in the scribe lane area SL, as compared to the embodiments ofFIGS.10to12. The plurality of circuit regions20may further include a separate cell pattern20dhaving the same pitch as the logic circuit region20a, the memory region20band the input/output device region20c, as compared to the embodiments ofFIGS.10to12.

In some embodiments, the cell pattern20dmay be within the scribe lane area SL. For example, all of the cell pattern20d, the middle pitch pattern22and the key pattern12may be formed in the scribe lane area SL.

Although not shown in the figures, in some embodiments, the separate cell pattern20dmay be omitted, and at least one of the logic circuit region20a, the memory region20band the input/output device region20cmay be within the scribe lane area SL and may perform a function of the cell pattern20d.

In accordance with some exemplary embodiments of the disclosure, in measurement of a pitch shift of a cell pattern, large volumes of measurement data may be rapidly processed.

In addition, it may be possible to measure the pitch shift of the cell pattern without using a scanning electron microscope.

Furthermore, the pitch shift of the cell pattern may be measured in a photolithography process, before an etching process, and, as such, even if and/or when formation of a layer is determined to have failed, an exposure process may be again performed without completely removing the layer (for example, without performing an etching process).

While some embodiments of the disclosure have been described with reference to the accompanying drawings, it should be understood by those skilled in the art that various modifications may be made without departing from the scope of the disclosure and without changing essential features thereof. Therefore, the above-described embodiments should be considered in a descriptive sense only and not for purposes of limitation.