Patent ID: 12243598

DETAILED DESCRIPTION

Embodiments provide a semiconductor storage device that can be highly integrated and a program operation method for a select gate line of the semiconductor storage device.

In general, according to one embodiment, there is provided a semiconductor storage device including a first memory string that includes a first select transistor and a plurality of first memory cell transistors connected in series, a first bit line that is connected to the first memory string, a select gate line that is connected to a gate electrode of the first select transistor, a plurality of word lines that are respectively connected to gate electrodes of the plurality of first memory cell transistors, a first sense amplifier unit that is connected to the first bit line, a control circuit configured to execute a program operation, and a voltage generation circuit configured to generate a voltage. The first sense amplifier unit includes a first sense amplifier circuit, a first transistor having a first end connected to the first bit line and a second end connected to the first sense amplifier circuit, and a second transistor having a first end connected to a node between the first end of the first transistor and the first bit line and a second end connected to the voltage generation circuit. In a first period of the program operation carried out on the select transistors connected to the select gate line, in a state where a voltage for causing the first transistor to be in an OFF state is supplied to a gate electrode of the first transistor and a voltage for causing the second transistor to be in an ON state is supplied to a gate electrode of the second transistor, a voltage of the first bit line is set as a first voltage and a voltage of the select gate line is set as a second voltage. In a second period of the program operation carried out on the select transistors connected to the select gate line, that is after the first period, in a state where a voltage for causing the first transistor to be in an ON state is supplied to the gate electrode of the first transistor and a voltage for causing the second transistor to be in an OFF state is supplied to the gate electrode of the second transistor, a voltage of the first bit line is set as a third voltage that is less than the first voltage and a voltage of the select gate line is set as a fourth voltage that is greater than the second voltage.

Next, semiconductor storage devices according to embodiments will be described in detail with reference to the drawings. The following embodiments are merely examples, and are not intended to limit the scope of the present disclosure.

In this specification, the term “semiconductor storage device” may mean a memory die (or memory chip), or may mean a memory system including a controller die such as a memory card or an SSD. Further, the term “semiconductor storage device” may also mean a configuration including a host computer, such as a smart phone, a tablet terminal, or a personal computer.

Also, in this specification, when it is described that a first configuration is “electrically connected” to a second configuration, the first configuration may be directly connected to the second configuration, or the first configuration may be connected to the second configuration via a wiring, a semiconductor member, a transistor, or the like. For example, when three transistors are connected in series, a first transistor is “electrically connected” to a third transistor even though a second transistor is in an OFF state.

Also, in this specification, when it is described that a first configuration is “connected between” a second configuration and a third configuration, this may mean that the first configuration, the second configuration, and the third configuration are connected in series, and the second configuration is connected to the third configuration through the first configuration.

Further, in this specification, when it is described that a circuit or the like “conducts” two wirings or the like, for example, this may mean that the circuit or the like includes a transistor or the like, the transistor or the like is provided in a current path between the two wirings, and the transistor or the like goes into an ON state.

First Embodiment

Memory System10

FIG.1is a schematic block diagram illustrating a configuration of a memory system10.

The memory system10reads, writes, and erases user data according to a signal transmitted from a host computer20. The memory system10is, for example, a memory card, an SSD, or another system that can store user data. The memory system10includes a plurality of memory dies MD for storing user data and a controller die CD connected to the plurality of memory dies MD and the host computer20. The controller die CD includes, for example, a processor, a RAM, and the like, and performs processes such as logical address/physical address conversion, bit error detection/correction, garbage collection (compaction), and wear leveling.

FIG.2is a schematic side view illustrating a configuration example of the memory system10.FIG.3is a schematic plan view illustrating the same configuration example. For convenience of description, a part of the configuration is omitted inFIGS.2and3.

As illustrated inFIG.2, the memory system10according to the present embodiment includes a mounting board MSB, the plurality of memory dies MD stacked on the mounting board MSB, and the controller die CD stacked on the memory dies MD. On an upper surface of the mounting board MSB, pad electrodes P are provided in a region of an end portion in a Y direction, and a partial remaining region is adhered to a lower surface of the memory die MD via an adhesive or the like. On an upper surface of the memory die MD, pad electrodes P are provided in a region of an end portion in the Y direction, and a remaining region is adhered to a lower surface of another memory die MD or the controller die CD via an adhesive or the like. On an upper surface of the controller die CD, Pad electrodes P are provided in a region of an end portion in the Y direction.

As illustrated inFIG.3, each of the mounting board MSB, the plurality of memory dies MD, and the controller die CD includes a plurality of pad electrodes P located in an X direction. The plurality of pad electrodes P provided on the mounting board MSB, the plurality of memory dies MD, and the controller die CD are connected to each other via bonding wires B.

The configurations illustrated inFIGS.2and3are merely examples, and specific configurations may be adjusted as appropriate. For example, in the examples illustrated inFIGS.2and3, the controller die CD is stacked on the plurality of memory dies MD, and these structures are connected by the bonding wires B. In such a configuration, the plurality of memory dies MD and the controller die CD are provided in one package. However, the controller die CD may be provided in a separate package from the memory die MD. Also, the plurality of memory dies MD and the controller die CD may be connected to each other not by the bonding wires B but by through vias or the like.

Configuration of Memory Die MD

FIG.4is a schematic block diagram illustrating a configuration of the memory die MD.FIG.5is a schematic circuit diagram illustrating a configuration of a part of the memory die MD.FIG.6is a schematic block diagram illustrating a configuration of a sense amplifier module SAM.FIG.7is a schematic circuit diagram illustrating a configuration of a sense amplifier unit SAU. For convenience of description, some configurations are omitted inFIGS.4to7.

FIG.4illustrates a plurality of control terminals and the like. The plurality of control terminals may be represented as control terminals corresponding to high active signals (positive logic signals), as control terminals corresponding to low active signals (negative logic signals), or as control terminals corresponding to both the high active signals and the low active signals. InFIG.4, reference letters of the control terminals corresponding to the low active signals include overlines. In this specification, reference letters of the control terminals corresponding to the low active signals include a slash (“/”). The description inFIG.4is an example, and specific aspects may be adjusted as appropriate. For example, some or all of the high active signals may be made low active signals, and some or all of the low active signals may be made high active signals.

As illustrated inFIG.4, the memory die MD includes a memory cell array MCA for storing user data and a peripheral circuit PC connected to the memory cell array MCA.

Configuration of Memory Cell Array MCA

The memory cell array MCA includes a plurality of memory blocks BLK, as illustrated inFIG.5. Each of the plurality of memory blocks BLK includes a plurality of string units SU. Each of the plurality of string units SU includes a plurality of memory strings MS. One end of each of the plurality of memory strings MS is connected to the peripheral circuit PC via a bit line BL. In addition, the other end of each of the plurality of memory strings MS is connected to the peripheral circuit PC via a common source line SL.

The memory string MS includes a drain-side select transistor STD connected in series between the bit line BL and the source line SL, a plurality of memory cells MC (which are memory cell transistors), a source-side select transistor STS, and a source-side select transistor STSB. Hereinafter, the drain-side select transistor STD, the source-side select transistor STS, and the source-side select transistor STSB may be simply referred to as select transistors (STD, STS, and STSB) or select transistors (STD and STS).

The memory cell MC is a field effect transistor including a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. The gate insulating film includes a charge storage film. A threshold voltage of the memory cell MC changes according to an amount of charge in the charge storage film. The memory cell MC stores 1-bit or multiple-bit user data. A word line WL is connected to each of gate electrodes of the plurality of memory cells MC corresponding to one memory string MS. Each word line WL is commonly connected to all memory strings MS in one memory block BLK.

The select transistors (STD, STS, and STSB) are field effect transistors each of which includes a semiconductor layer, a gate insulating film, and a gate electrode. The semiconductor layer functions as a channel region. A drain-side select gate line SGD, a source-side select gate line SGS, and a source-side select gate line SGSB are respectively connected to the gate electrodes of the select transistors (STD, STS, and STSB). The drain-side select gate line SGD is provided corresponding to the string unit SU and commonly connected to all memory strings MS in one string unit SU. The source-side select gate line SGS is commonly connected to all memory strings MS in the memory block BLK. The source-side select gate line SGSB is commonly connected to all memory strings MS in the memory block BLK. Hereinafter, the drain-side select gate line SGD, the source-side select gate line SGS, and the source-side select gate line SGSB may be simply referred to as select gate lines (SGD, SGS, and SGSB) or select gate lines (SGD and SGS).

Configuration of Peripheral Circuit PC

The peripheral circuit PC includes, as illustrated inFIG.4, a row decoder RD, a sense amplifier module SAM, a cache memory CM, a voltage generation circuit VG, and a sequencer SQC. The peripheral circuit PC also includes an address register ADR, a command register CMR, and a status register STR. Further, the peripheral circuit PC includes an input/output control circuit I/O and a logic circuit CTR.

Configuration of Row Decoder RD

The row decoder RD (FIG.4) includes an address decoder22for decoding address data ADD (FIG.4), as illustrated inFIG.5, for example. The row decoder RD (FIG.4) also includes a block select circuit23and a voltage select circuit24that transfer operating voltages to the memory cell array MCA according to an output signal of the address decoder22.

The address decoder22is connected to a plurality of block select lines BLKSEL and a plurality of voltage select lines33. The address decoder22sequentially references a row address RA of the address register ADR (FIG.4) according to, for example, a control signal from the sequencer SQC.

The block select circuit23has a plurality of block select circuits34corresponding to the memory blocks BLK. The block select circuit34includes a plurality of block select transistors35corresponding to word lines WL and select gate lines (SGD and SGS), respectively.

The block select transistor35is, for example, a high breakdown voltage field-effect transistor. Drain electrodes of the block select transistors35are respectively electrically connected to corresponding word lines WL or select gate lines (SGD and SGS). Source electrodes of the block select transistors35are respectively electrically connected to voltage supply lines31via wirings CG and the voltage select circuit24. Gate electrodes of the block select transistors35are commonly connected to the corresponding block select line BLKSEL.

The voltage select circuit24includes a plurality of voltage select units36corresponding to the word lines WL and the select gate lines (SGD and SGS). Each of the plurality of voltage select units36includes a plurality of voltage select transistors37. The voltage select transistor37is, for example, a high breakdown voltage field-effect transistor. Drain terminals of the voltage select transistors37are respectively electrically connected to the corresponding word lines WL or the select gate lines (SGD and SGS) via the wirings CG and the block select circuit23. Source terminals are electrically connected to the corresponding voltage supply lines31. Gate electrodes are respectively connected to the corresponding voltage select lines33. Circuit Configuration of Sense Amplifier Module SAM

The sense amplifier module SAM (FIG.4) includes a plurality of sense amplifier units SAU0to SAUm-1as illustrated inFIG.6, for example. The plurality of sense amplifier units SAU0to SAUm-1correspond to a plurality of bit lines BL0to BLm-1. m is an integer of 1 or more.

Among the first to mth sense amplifier units SAU0to SAUm-1, the sense amplifier units corresponding to odd-numbered bit lines BL0, BL2, . . . , BLm-2may be referred to as odd-numbered sense amplifier units SAU0, SAU2, . . . , SAUm-2. The odd-numbered sense amplifier units SAU0, SAU2, . . . , SAUm-2may be referred to as an odd-numbered sense amplifier unit SAU_O.

Among the first to mth sense amplifier units SAU0to SAUm-1, the sense amplifier units corresponding to even-numbered bit lines BL1, BL3, . . . , BLm-3, and BLm-1may be referred to as even-numbered sense amplifier units SAU1, SAU3, . . . , SAUm-3, and SAUm-1. The even-numbered sense amplifier units SAU1, . . . SAU3, SAUm-3, and SAUm-1may be referred to as an even-numbered sense amplifier unit SAU_E.

For example, as illustrated inFIG.7, the sense amplifier units SAU0to SAUm-1each include a sense amplifier circuit SA, a high breakdown voltage transistor45, a high breakdown voltage transistor60, a wiring LBUS, and latch circuits SDL, DL0to DLnL(nLis a natural number). A charging transistor55(FIG.7) for precharging is connected to the wiring LBUS. The wiring LBUS is connected to a latch circuit XDL in the cache memory CM via a switch transistor DSW and a wiring DBUS.

The sense amplifier circuit SA includes a sense transistor41as illustrated inFIG.7. The sense transistor41discharges charge of the wiring LBUS according to current flowing through the bit line BL. A source electrode of the sense transistor41is connected to a voltage supply line supplied with a ground voltage Vss. A drain electrode is connected to the wiring LBUS via a switch transistor42. A gate electrode is connected to the bit line BL via a sense node SEN, a discharging transistor43, a node COM, a clamp transistor44, and the high breakdown voltage transistor45. The sense node SEN is connected to an internal control signal line CLKSA via a capacitor48.

The high breakdown voltage transistor60has a gate electrode connected to a signal line BIAS, a source terminal connected to a voltage supply line to which voltages VERA and Vinhibit are supplied, and a drain terminal connected to the bit line BL.

In an erasing operation, the voltage generation circuit VG generates the voltage VERAnecessary for the erasing operation. The voltage VERAis supplied to the bit line BL via the voltage supply line and the high breakdown voltage transistor60. In this case, the high breakdown voltage transistor45goes into an OFF state.

Also, in a program operation for the drain-side select gate line SGD, which will be described below, the voltage generation circuit VG generates the voltage Vinhibit necessary for the program operation. The voltage Vinhibit is supplied to the bit line BL via the voltage supply line and the high breakdown voltage transistor60.

The sense amplifier circuit SA includes a voltage transfer circuit. The voltage transfer circuit selectively brings the node COM and the sense node SEN into conduction with a voltage supply line supplied with a voltage VDDor a voltage supply line supplied with a voltage VSRCaccording to data latched in the latch circuit SDL. The voltage transfer circuit includes a node N1, a charging transistor46, a charging transistor49, and an inverter including a charging transistor47and a discharging transistor50. The charging transistor46is connected between the node N1and the sense node SEN. The charging transistor49is connected between the node N1and the node COM. The charging transistor47is connected between the node N1and the voltage supply line to which the voltage VDDis supplied. The discharging transistor50is connected between the node N1and the voltage supply line to which the voltage VSRCis supplied. Gate electrodes of the charging transistor47and the discharging transistor50are commonly connected to a node INV_S of the latch circuit SDL. That is, an output terminal of the inverter including the charging transistor47and the discharging transistor50is connected to the node N1. Also, an input terminal of the inverter is connected to the node INV_S of the latch circuit SDL.

The sense transistor41, the switch transistor42, the discharging transistor43, the clamp transistor44, the charging transistor46, the charging transistor49, and the discharging transistor50are, for example, enhancement type NMOS transistors. The high breakdown voltage transistor45is, for example, a depression type NMOS transistor. The charging transistor47is, for example, a PMOS transistor.

Further, a gate electrode of the switch transistor42is connected to a signal line STB. A gate electrode of the discharging transistor43is connected to a signal line XXL. A gate electrode of the clamp transistor44is connected to a signal line BLC. A gate electrode of the high breakdown voltage transistor45is connected to a signal line BLS. A gate electrode of the charging transistor46is connected to a signal line HLL. A gate electrode of the charging transistor49is connected to a signal line BLX. These signal lines STB, XXL, BLC, BLS, HLL and BLX are connected to the sequencer SQC.

The latch circuit SDL includes nodes LAT_S and INV_S, an inverter51, an inverter52, a switch transistor53, and a switch transistor54. The inverter51has an output terminal connected to the node LAT_S and an input terminal connected to the node INV_S. The inverter52has an input terminal connected to the node LAT_S and an output terminal connected to the node INV_S. The switch transistor53is provided in a current path between the node LAT_S and the wiring LBUS. The switch transistor54is provided in a current path between the node INV_S and the wiring LBUS. The switch transistors53and54are, for example, NMOS transistors. A gate electrode of the switch transistor53is connected to the sequencer SQC via a signal line STL. A gate electrode of the switch transistor54is connected to the sequencer SQC via a signal line STI.

The latch circuits DL0to DLnLare configured in substantially the same manner as the latch circuit SDL. However, as described above, the node INV_S of the latch circuit SDL is brought into conduction with the gate electrodes of the charging transistor47and the discharging transistor50in the sense amplifier circuit SA. The latch circuits DL0to DLnLdiffer from the latch circuit SDL in this respect.

The switch transistor DSW is, for example, an NMOS transistor. The switch transistor DSW is connected between the wiring LBUS and the wiring DBUS. A gate electrode of the switch transistor DSW is connected to the sequencer SQC via a signal line DBS.

As illustrated inFIG.6, the above-described signal lines STB, HLL, XXL, BLX, and BLC are each commonly connected among all sense amplifier units SAU0to SAUm-1in the sense amplifier module SAM. The voltage supply line to which the voltage VDDis supplied and the voltage supply line to which the voltage VSRCis supplied are each commonly connected among all the sense amplifier units SAU0to SAUm-1in the sense amplifier module SAM. The signal line STI and the signal line STL of the latch circuit SDL are each commonly connected among all the sense amplifier units SAU0to SAUm-1in the sense amplifier module SAM. Similarly, signal lines TI0to TInL, and TL0to TLnLcorresponding to the signal lines STI and STL in the latch circuits DL0to DLnLare each commonly connected among all the sense amplifier units SAU0to SAUm-1in the sense amplifier module SAM.

The signal lines BLS and BIAS described above are divided into signal lines BLS_O and BIAS_O connected to the odd-numbered sense amplifier units SAU0, SAU2, . . . , SAUm-2and signal lines BLS_E and BIAS_E connected to the even-numbered sense amplifier units SAU1, SAU3, . . . , SAUm-3, SAUm-1. The signal lines BLS_O and BIAS_O are commonly connected among the odd-numbered sense amplifier units SAU0, SAU2, . . . , SAUm-2in the sense amplifier module SAM. The signal lines BLS_E and BIAS_E are commonly connected among the even-numbered sense amplifier units SAU1, SAU3, SAUm-3and SAUm-1in the sense amplifier module SAM.

A plurality of the signal lines DBS described above are provided corresponding to all the sense amplifier units SAU in the sense amplifier module SAM.

Configuration of Voltage Generation Circuit VG

The voltage generation circuit VG (FIG.4) is connected to a plurality of voltage supply lines31, for example as illustrated inFIG.5. The voltage generation circuit VG includes, for example, a step-down circuit such as a regulator and a step-up circuit such as a charge pump circuit32. The step-down circuit and the step-up circuit are each connected to voltage supply lines supplied with a power supply voltage Vcc and a ground voltage Vss (FIG.4). These voltage supply lines are connected, for example, to the pad electrodes P described with reference toFIGS.2and3.

The voltage generation circuit VG generates a plurality of operating voltages to be applied to the bit line BL, the source line SL, the word line WL, and the select gate lines (SGD, SGS, and SGSB) during a read operation, a program operation, and an erasing operation for the memory cell array MCA according to, for example, control signals from the sequencer SQC.

Further, the voltage generation circuit VG generates a plurality of operating voltages to be applied to the bit line BL, the source line SL, the word line WL, and the select gate lines (SGD, SGS, and SGSB) during the program operation for the drain-side select gate line SGD according to, for example, the control signal from the sequencer SQC.

The voltage generation circuit VG outputs the generated voltages to the plurality of voltage supply lines31. The operation voltage output from the voltage supply line31is appropriately adjusted according to the control signal from the sequencer SQC.

Configuration of Sequencer SQC

The sequencer SQC (FIG.4) outputs internal control signals to the row decoder RD, the sense amplifier module SAM, and the voltage generation circuit VG according to command data CMD stored in the command register CMR. The sequencer SQC also outputs status data Stt indicating a state of the memory die MD to the status register STR as appropriate.

The sequencer SQC generates a ready/busy signal RB and outputs the ready/busy signal RB to a terminal RBn. During a period (busy period) in which the terminal RBn is in an “L” state, access to the memory die MD is basically prohibited. Access to the memory die MD is permitted during a period (ready period) in which the terminal RBn is in an “H” state. The terminal RBn is implemented by, for example, the pad electrode P described with reference toFIGS.2and3.

Configuration of Address Register ADR

The address register ADR, as illustrated inFIG.4, is connected to the input/output control circuit I/O and stores the address data ADD input from the input/output control circuit I/O. The address register ADR has, for example, a plurality of 8-bit register rows. When an internal operation such as a read operation, a program operation, or an erasing operation is executed, the register row stores the address data ADD corresponding to the internal operation being executed.

The address data ADD includes, for example, a column address CA (FIG.4) and the row address RA (FIG.4). The row address RA includes, for example, a block address specifying the memory block BLK (FIG.5), a page address specifying the string unit SU and the word line WL, a plane address specifying the memory cell array MCA (plane), and a chip address specifying the memory die MD.

Configuration of Command Register CMR

The command register CMR is connected to the input/output control circuit I/O and stores the command data CMD input from the input/output control circuit I/O. The command register CMR has at least one set of 8-bit register rows, for example. When the command data CMD is stored in the command register CMR, a control signal is transmitted to the sequencer SQC.

Configuration of Status Register STR

The status register STR is connected to the input/output control circuit I/O and stores the status data Stt to be output to the input/output control circuit I/O. The status register STR has, for example, a plurality of 8-bit register rows. When an internal operation such as a read operation, a program operation, or an erasing operation is executed, the register row stores the status data Stt regarding the internal operation being executed. Also, the register row stores ready/busy information of the memory cell array MCA, for example.

Configuration of Input/Output Control Circuit I/O

The input/output control circuit I/O (FIG.4) includes data signal input/output terminals DQ0to DQ7, data strobe signal input/output terminals DQS and /DQS, a shift register, and a buffer circuit.

Each of the data signal input/output terminals DQ0to DQ7and data strobe signal input/output terminals DQS and /DQS is implemented by the pad electrode P described with reference toFIGS.2and3, for example. Data DAT input via the data signal input/output terminals DQ0to DQ7is input from a buffer circuit to the cache memory CM, the address register ADR, or the command register CMR according to an internal control signal from the logic circuit CTR. The data DAT output via the data signal input/output terminals DQ0to DQ7is input to the buffer circuit from the cache memory CM or the status register STR according to the internal control signal from the logic circuit CTR.

Signals (for example, data strobe signals and complementary signals thereof) input via the data strobe signal input/output terminals DQS and /DQS are used for data input via the data signal input/output terminals DQ0to DQ7. Data input via the data signal input/output terminals DQ0to DQ7is taken into a shift register in the input/output control circuit I/O at a timing of a rising edge (switching of the input signal) of the voltage of the data strobe signal input/output terminal DQS and a falling edge (switching of the input signal) of the voltage of the data strobe signal input/output terminal /DQS, and a timing of a falling edge (switching of the input signal) of the voltage of the data strobe signal input/output terminal DQS and a rising edge (switching of the input signal) of the voltage of the data strobe signal input/output terminal /DQS.

Configuration of Logic Circuit CTR

The logic circuit CTR (FIG.4) includes a plurality of external control terminals /CE, CLE, ALE, /WE, /RE, and RE, and a logic circuit connected to the plurality of external control terminals /CE, CLE, ALE, /WE, /RE, and RE. The logic circuit CTR receives an external control signal from the controller die CD via the external control terminals /CE, CLE, ALE, /WE, /RE, and RE and outputs an internal control signal to the input/output control circuit I/O according to the external control signal.

Further, each of the external control terminals /CE, CLE, ALE, /WE, /RE, and RE is implemented by the pad electrode P described with reference toFIGS.2and3, for example.

Configuration of Memory Die MD

Next, configuration examples of the semiconductor storage device according to the present embodiment will be described with reference toFIGS.8to11.FIG.8is a schematic perspective view illustrating a configuration of a part of the memory die MD.FIGS.9and10are schematic cross-sectional views illustrating configurations of a part of the memory die MD. FIG.11is a schematic cross-sectional view of a structure illustrated inFIG.10cut along line C-C′ and viewed in a direction of arrow.FIG.12is a schematic cross-sectional view illustrating a configuration of an N-type high voltage transistor TrNH.FIG.13is a schematic cross-sectional view illustrating a configuration of a P-type high voltage transistor TrPH.FIG.14is a schematic cross-sectional view illustrating a configuration of an N-type low voltage transistor TrNL.FIG.15is a schematic cross-sectional view illustrating a configuration of a P-type low voltage transistor TrPL.FIG.16is a schematic cross-sectional view illustrating a configuration of an N-type ultra-low voltage transistor TrNVL.FIG.17is a schematic cross-sectional view illustrating a configuration of a P-type ultra-low voltage transistor TrPVL.FIGS.8to17illustrate schematic configurations, and specific configurations thereof may be changed as appropriate. InFIGS.8to17, a part of the configuration is omitted.

As illustrated inFIG.8, the memory die MD includes a semiconductor substrate100, a transistor layer LTRprovided on the semiconductor substrate100, and a memory cell array layer LMCAprovided above the transistor layer LTR.

Structure of Memory Cell Array Layer LMCA

The memory cell array layer LMCAincludes a plurality of memory blocks BLK located in the Y direction. An inter-block insulating layer ST such as silicon oxide (SiO2) is provided between two memory blocks BLK adjacent in the Y direction, as illustrated inFIGS.8and10, for example. A plurality of string units SU are provided between two inter-block insulating layers ST adjacent in the Y direction. An inter-string unit insulating layer SHE such as silicon oxide (SiO2) is provided between two string units SU adjacent in the Y direction.

In the following description, as illustrated inFIGS.10and11, the plurality of string units SU in the memory block BLK may be respectively referred to as string units SUa, SUb, SUc, SUd, and Sue.

The memory block BLK includes, for example, as illustrated inFIG.8, a plurality of conductive layers110and a plurality of insulating layers101alternately located in a Z direction, a plurality of semiconductor pillars120extending in the Z direction, and a plurality of gate insulating films130respectively provided between the plurality of conductive layers110and the plurality of semiconductor pillars120.

The conductive layer110is a substantially plate-shaped conductive layer extending in the X direction. The conductive layer110may include a layered film or the like including a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). Also, the conductive layer110may contain, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). The insulating layer101such as silicon oxide (SiO2) is provided between the plurality of conductive layers110located in the Z direction.

Further, among the plurality of conductive layers110, two or more conductive layers110positioned at bottom layers function as, for example, as illustrated inFIG.11, the source-side select gate lines SGS and SGSB (FIG.5) and gate electrodes of a plurality of source-side select transistors STS and STSB connected to the source-side select gate lines SGS and SGSB. These plurality of conductive layers110are electrically independent for each memory block BLK.

Further, a plurality of conductive layers110positioned above above-described these plurality of conductive layers110function as the word lines WL (FIG.5) and gate electrodes of a plurality of memory cells MC (FIG.5) connected to the word lines WL. These plurality of conductive layers110are electrically independent for each memory block BLK.

In addition, one or more conductive layers110positioned above the plurality of conductive layers110described above function as the drain-side select gate lines SGD and gate electrodes of a plurality of drain-side select transistors STD (FIG.5) connected to the drain-side select gate lines SGD. These plurality of conductive layers110have smaller widths in the Y direction than the other conductive layers110.

A semiconductor layer112is provided below the conductive layer110. The semiconductor layer112may contain, for example, polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). The insulating layer101such as silicon oxide (SiO2) is provided between the semiconductor layer112and the conductive layer110.

The semiconductor layer112functions as the source line SL (FIG.5). For example, the source line SL is commonly provided for all memory blocks BLK in the memory cell array MCA.

The semiconductor pillars120are located in a predetermined pattern in the X direction and the Y direction, as illustrated inFIGS.8and10, for example. The semiconductor pillars120function as channel regions of the plurality of memory cells MC and the select transistors (STD, STS, and STSB) in one memory string MS (FIG.5). The semiconductor pillar120is, for example, a semiconductor layer such as polycrystalline silicon (Si). For example, as illustrated inFIG.8, the semiconductor pillar120has a substantially cylindrical shape with a bottom, and an insulating layer125such as silicon oxide is provided in a central portion. In addition, an outer peripheral surface of the semiconductor pillar120is surrounded by the conductive layer110and faces the conductive layer110.

An impurity region121containing an N-type impurity such as phosphorus (P) is provided at an upper end portion of the semiconductor pillar120. The impurity region121is connected to the bit line BL via a contact Ch and a contact Vy. A lower end portion of the semiconductor pillar120is connected to the semiconductor layer112. The semiconductor pillars120respectively function as channel regions of the plurality of memory cells MC and the select transistors (STD, STS, and STSB) in one memory string MS (FIG.5).

The gate insulating film130has a substantially cylindrical shape with a bottom that covers an outer peripheral surface of the semiconductor pillar120. The gate insulating film130includes, for example, a tunnel insulating film131, a charge storage film132, and a block insulating film133which are stacked between the semiconductor pillar120and the conductive layer110, as illustrated inFIG.9. The tunnel insulating film131and the block insulating film133are, for example, insulating films such as silicon oxide (SiO2). The charge storage film132is a film that can store charges, and is, for example, silicon nitride (SiN). The tunnel insulating film131, the charge storage film132, and the block insulating film133have a substantially cylindrical shape, and extend in the Z direction along the outer peripheral surface of the semiconductor pillar120excluding a contact portion between the semiconductor pillar120and the semiconductor layer112. That is, the gate insulating film130has the same configuration at a height position corresponding to the memory cell MC and at a height position corresponding to the drain-side select transistor STD.

The gate insulating film130may include a floating gate made of, for example, polycrystalline silicon containing N-type or P-type impurities.

As illustrated inFIG.8, a plurality of contacts CC are provided at end portions of the plurality of conductive layers110in the X direction. The plurality of conductive layers110are connected to the peripheral circuit PC via these plurality of contacts CC. These plurality of contacts CC extend in the Z direction and are connected to the conductive layer110at lower ends thereof. The contact CC may include, for example, a layered film including a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W).

Structure of Semiconductor Substrate100and Transistor Layer LTR

The semiconductor substrate100is, for example, a semiconductor substrate made of P-type silicon (Si) containing P-type impurities such as boron (B). A part of a surface of the semiconductor substrate100is provided with an N-type well implanted with N-type impurities such as phosphorus (P). A part of the surface of the semiconductor substrate100is provided with a P-type well implanted with P-type impurities such as boron (B). In addition, a part of the surface of the semiconductor substrate100is provided with a semiconductor substrate region where neither the N-type well nor the P-type well is provided. A part of the surface of the semiconductor substrate100is provided with an insulating region1001.

A plurality of transistors Tr forming the peripheral circuit PC are provided in the transistor layer LTR. A source region, a drain region and a channel region of the transistor Tr are provided on the surface of the semiconductor substrate100. A gate electrode gc of the transistor Tr is provided in the transistor layer LTR. Contacts CS are provided in the source region, the drain region and the gate electrode gc of the plurality of transistors Tr. The plurality of contacts CS are connected to other transistors Tr, components in the memory cell array layer LMCA, and the like via wirings D0, D1, and D2in the transistor layer LTR.

As the transistors Tr, for example, N-type high voltage transistors TrNH, P-type high voltage transistors TrPH, N-type low voltage transistors TrNL, P-type low voltage transistors TrPL, N-type ultra-low voltage transistors TrNVLand P-type ultra-low voltage transistors TrPVLare provided.

Structure of N-type High Voltage Transistor TrNH

The N-type high voltage transistor TrNHis provided in a semiconductor substrate region100S of the semiconductor substrate100as illustrated inFIG.12, for example. The N-type high voltage transistor TrNHincludes a part of the semiconductor substrate region100S, a gate insulating layer141such as silicon oxide (SiO2) provided on the surface of the semiconductor substrate100, a gate electrode member142such as polycrystalline silicon (Si) provided on an upper surface of the gate insulating layer141, a gate electrode member143such as tungsten (W) provided on an upper surface of the gate electrode member142, a cap insulating layer144such as silicon oxide (SiO2) or silicon nitride (Si3N4) provided on an upper surface of the gate electrode member143, and a side wall insulating layer145such as silicon oxide (SiO2) or silicon nitride (Si3N4) provided on side surfaces of the gate electrode member142, the gate electrode member143, and the cap insulating layer144in the X or Y direction. The gate electrode member142contains, for example, N-type impurities such as phosphorus (P) or arsenic (As), or P-type impurities such as boron (B).

In the illustrated example, a thickness T141matches a thickness of the gate insulating layer141in the Z direction.

Also, the N-type high voltage transistor TrNHincludes a liner insulating layer146such as silicon oxide (SiO2) and a liner insulating layer147such as silicon nitride (Si3N4) which are stacked on the surface of the substrate100, a side surface of the gate insulating layer141in the X or Y direction, a side surface of the sidewall insulating layer145in the X or Y direction, and an upper surface of the cap insulating layer144.

Also, three contacts CSHextending in the Z direction are connected to the N-type high voltage transistor TrNH. The contact CSHmay include, for example, a layered film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). One of the three contact CSHis connected to an upper surface of the gate electrode member143through the liner insulating layer147, the liner insulating layer146and the cap insulating layer144, and functions as a part of the gate electrode of the N-type high voltage transistor TrNH. Remaining two of the three contacts CSHare connected to the surface of the semiconductor substrate100through the liner insulating layer147and the liner insulating layer146, and function as a source electrode or a drain electrode of the N-type high voltage transistor TrNH.

In the illustrated example, a distance RCSHmatches a distance in the X or Y direction from a central axis of the contact CSHfunctioning as a part of the gate electrode to a central axis of the contact CSHfunctioning as a part of the drain electrode. Also, the distance RCSHmatches a distance in the X or Y direction from the central axis of the contact CSHfunctioning as the part of the gate electrode to a central axis of the contact CSHfunctioning as a part of the source electrode.

The N-type high voltage transistor TrNHuses the surface of the semiconductor substrate100facing the gate electrode member142as a channel region. Further, a high impurity concentration region148is provided on the surface of the semiconductor substrate100at a connection portion with the contact CSH. A low impurity concentration region149is provided on the surface of the semiconductor substrate100in a region (region not facing the gate electrode member142) between the channel region and the high impurity concentration region148. The high impurity concentration region148and the low impurity concentration region149contain, for example, N-type impurities such as phosphorus (P) or arsenic (As). An impurity concentration of the N-type impurities in the high impurity concentration region148is higher than an impurity concentration of the N-type impurities in the low impurity concentration region149.

A length (gate length) in the Y direction of the gate electrode of the N-type high voltage transistor TrNHis WH, and a width (gate width) in the X direction of the gate electrode is LH.

Structure of P-type High Voltage Transistor TrPH

The P-type high voltage transistor TrPHis basically configured similarly to the N-type high voltage transistor TrPH, as illustrated inFIG.13, for example. However, the P-type high voltage transistor Tr PH is provided not in the semiconductor substrate region100S but in an N-type well region100N. Also, instead of the high impurity concentration region148, a high impurity concentration region158is provided on the surface of the semiconductor substrate100at a connection portion with the contact CSH. Instead of the low impurity concentration region149, a low impurity concentration region159is provided on the surface of the semiconductor substrate100in a region (region not facing the gate electrode member142) between the channel region and the high impurity concentration region158. The high impurity concentration region158and the low impurity concentration region159contain P-type impurities such as boron (B). An impurity concentration of the P-type impurities in the high impurity concentration region158is higher than an impurity concentration of the P-type impurities in the low impurity concentration region159.

A length in the Y direction and a width in the X direction of the gate electrode of the P-type high voltage transistor TrPHare the same or substantially the same as the length in the Y direction and the width in the X direction of the gate electrode of the N-type high voltage transistor TrNH.

Structure of N-type Low Voltage Transistor TrNL

The N-type low voltage transistor TrNLis provided in a P-type well region100P of the semiconductor substrate100, as illustrated inFIG.14, for example. The N-type low voltage transistor TrNLincludes a part of the P-type well region100P, a gate insulating layer241such as silicon oxide (SiO2) provided on the surface of the semiconductor substrate100, a gate electrode member242such as polycrystalline silicon (Si) provided on an upper surface of the gate insulating layer241, a gate electrode member243such as tungsten (W) provided on an upper surface of the gate electrode member242, a cap insulating layer244such as silicon nitride (Si3N4) provided on an upper surface of the gate electrode member243, and a side wall insulating layer245such as silicon nitride (Si3N4) provided on side surfaces of the gate electrode member242, the gate electrode member243, and the cap insulating layer244in the X direction or the Y direction.

In the illustrated example, a thickness T241matches a thickness of the gate insulating layer241in the Z direction. The thickness T241is smaller than the thickness T141(FIG.12).

Also, the N-type low voltage transistor TrNLincludes a liner insulating layer246such as silicon oxide (SiO2) and a liner insulating layer247such as silicon nitride (Si3N4) which are stacked on the surface of the semiconductor substrate100, a side surface of the gate insulating layer241in the X or Y direction, a side surface of the sidewall insulating layer245in the X or Y direction, and an upper surface of the cap insulating layer244.

Also, three contacts CSLextending in the Z direction are connected to the N-type low voltage transistor TrNL. The contact CSLmay include, for example, a layered film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). One of the three contacts CSLis connected to an upper surface of the gate electrode member243through the liner insulating layer247, the liner insulating layer246, and the cap insulating layer244, and functions as a part of the gate electrode of the N-type low voltage transistor TrNL. Remaining two of the three contacts CSLare connected to the surface of the semiconductor substrate100through the liner insulating layer247and the liner insulating layer246, and function as a source electrode or a drain electrode of the N-type low voltage transistor TrNL.

In the illustrated example, a distance RCSLmatches a distance in the X or Y direction from a central axis of the contact CSLfunctioning as a part of the gate electrode to a central axis of the contact CSLfunctioning as a part of the drain electrode. The distance RCSLmatches a distance in the X or Y direction from the central axis of the contact CSLfunctioning as the part of the gate electrode to a central axis of the contact CSLfunctioning as a part of the source electrode. The distance RCSLis smaller than the distance RCSH(FIG.12).

In addition, the N-type low voltage transistor TrNLuses a part of the surface of the semiconductor substrate100facing the gate electrode member242as a channel region. A high impurity concentration region248is provided on the surface of the semiconductor substrate100in a region from a connection portion with the contact CSLto a surface facing the gate electrode member242. The high impurity concentration region248contains, for example, N-type impurities such as phosphorus (P) or arsenic (As).

A length in the Y direction of the gate electrode of the N-type low voltage transistor TrNLis WL, and a width in the X direction of the gate electrode is LL. The length WLin the Y direction of the gate electrode is smaller than the length WH(FIG.12) in the Y direction of the gate electrode, and the width LLin the X direction of the gate electrode is smaller than the width LHin the X direction of the gate electrode.

Structure of P-type Low Voltage Transistor TrPL

The P-type low voltage transistor TrPLis basically configured similarly to the N-type low voltage transistor TrNL, as illustrated inFIG.15, for example. However, the P-type low voltage transistor TrPLis provided not in the P-type well region100P but in the N-type well region100N. Instead of the high impurity concentration region248, a high impurity concentration region258is provided in a region of the surface of the semiconductor substrate100from a connection portion with the contact CSLto a surface facing the gate electrode member242. The high impurity concentration region258contains, for example, P-type impurities such as boron (B).

A length in the Y direction and a width in the X direction of the gate electrode of the P-type low voltage transistor TrPLare the same or substantially the same as the length in the Y direction and the width in the X direction of the gate electrode of the N-type low voltage transistor TrNL.

Structure of N-type Ultra-Low Voltage Transistor TrNVL

The N-type ultra-low voltage transistor TrNVLis basically configured similarly to the N-type low voltage transistor TrNLillustrated inFIG.14, as illustrated inFIG.16, for example. A gate insulating layer341, a gate electrode member342, a gate electrode member343, a cap insulating layer344, and a side wall insulating layer345in the N-type ultra-low voltage transistor TrNVLrespectively correspond to the gate insulating layer241, the gate electrode member242, the gate electrode member243, the cap insulating layer244, and the side wall insulating layer245in the N-type low voltage transistor TrNL. A liner insulating layer346and a liner insulating layer347in the N-type ultra-low voltage transistor TrNVLrespectively correspond to the liner insulating layer246and the liner insulating layer247in the N-type low voltage transistor TrNL.

However, in the N-type ultra-low voltage transistor TrNVL, a high impurity concentration region348is provided in a region of the surface of the semiconductor substrate100from a connection portion with the contact CSLto a surface facing the gate electrode member342. A first low impurity concentration region349is provided between the high impurity concentration region348and the channel region, in a partial region of the surface of the semiconductor substrate100facing the gate electrode member342. A second low impurity concentration region350is provided in a region near the surface of the semiconductor substrate100, which is closer to a back side of the semiconductor substrate100than the first low impurity concentration region349. The high impurity concentration region348and the first low impurity concentration region349contain, for example, N-type impurities such as phosphorus (P) or arsenic (As). An impurity concentration in the first low impurity concentration region349is lower than that in the high impurity concentration region348. The second low impurity concentration region350contains, for example, P-type impurities such as boron (B). The second low impurity concentration region350may be omitted.

In the illustrated example, a thickness T341matches a thickness of the gate insulating layer341in the Z direction. The thickness T341is smaller than the thickness T241(FIG.14).

In the illustrated example, a distance RCSVLmatches a distance in the X or Y direction from a central axis of the contact CSLfunctioning as a part of the gate electrode to a central axis of the contact CSLfunctioning as a part of the drain electrode. Also, the distance RCSVLmatches a distance in the X or Y direction from the central axis of the contact CSLfunctioning as the part of the gate electrode to a central axis of the contact CSLfunctioning as a part of the source electrode. The distance RCVSLis smaller than the distance RCSL(FIG.14).

A length in the Y direction of the gate electrode of the N-type ultra-low voltage transistor TrNVLis WVL, and a width in the X direction of the gate electrode is LVL. The length WVLin the Y direction of the gate electrode is smaller than the length WL(FIG.14) in the Y direction of the gate electrode, and the width LVLin the X direction of the gate electrode is smaller than the width LLin the X direction of the gate electrode.

Structure of P-type Ultra-Low Voltage Transistor TrPVL

The P-type ultra-low voltage transistor TrPVLis basically configured similarly to the N-type ultra-low voltage transistor TrNVL, as illustrated inFIG.17, for example. However, the P-type ultra-low voltage transistor TrPVLis provided not in the P-type well region100P but in the N-type well region100N. Instead of the high impurity concentration region348, a high impurity concentration region358is provided in a region of the surface of the semiconductor substrate100from a connection portion with the contact CSLto a surface facing the gate electrode member342. Instead of the first low impurity concentration region349, a first low impurity concentration region359is provided between the high impurity concentration region358and the channel region, in a partial region of the surface of the semiconductor substrate100facing the gate electrode member342. Instead of the second low impurity concentration region350, a second low impurity concentration region360is provided in a region near the surface of the semiconductor substrate100, which is closer to a back side of the semiconductor substrate100than the first low impurity concentration region359. The high impurity concentration region358and the first low impurity concentration region359contain, for example, P-type impurities such as boron (B). An impurity concentration in the first low impurity concentration region359is lower than that in the high impurity concentration region358. The second low impurity concentration region360contains N-type impurities such as phosphorus (P) or arsenic (As). The second low impurity concentration region360may be omitted.

A length in the Y direction and a width in the X direction of the gate electrode of the P-type ultra-low voltage transistor TrPVLare the same or substantially the same as the length in the Y direction and the width in the X direction of the gate electrode of the N-type ultra-low voltage transistor TrNVL.

The ultra-low voltage transistors TrNVLand TrPVL(FIGS.16and17) have at least one of a smaller gate insulating layer (241and341) thickness, a smaller gate length, and a lower impurity concentration in the well region than the low voltage transistors TrNLand TrPL(FIGS.14and15).

Operation

Program Operation

Next, a program operation for the memory cell MC will be described.FIG.18is a schematic cross-sectional view for illustrating the program operation. In the following description, the word lines WL as an operation target may be referred to as selected word lines WLS, and the other word lines WL may be referred to as non-selected word lines WLU. Further, in the following description, an example of executing a read operation on the memory cells MC (hereinafter, sometimes referred to as “selected memory cell MC” and referred to the other memory cells MC as “non-selected memory cell MC”) connected to the selected word lines WLSamong the plurality of memory cells MC in the string unit SU as an operation target will be described. In the following description, such a configuration including a plurality of selected memory cells MC may be referred to as a selected page portion PG.

In the program operation, the voltage VSRCis supplied to a bit line BL (hereinafter, referred to as a selected bit line BLW) connected to the selected memory cell MC (hereinafter, referred to as a write memory cell MC) that is programmed. Further, the voltage VDDhigher than the voltage VSRCis supplied to a bit line BL (hereinafter, referred to as a non-selected bit line BLP) connected to the selected memory cell MC (hereinafter, referred to as a inhibited memory cell MC) that is not programmed. A voltage VSGDis also supplied to the drain-side select gate line SGD. For example, “L” is latched in the latch circuit SDL (FIG.7) corresponding to the selected bit line BLW, and “H” is latched in the latch circuit SDL (FIG.7) corresponding to the non-selected bit line BLP. Also, states of the signal lines STB, XXL, BLC, BLS, HLL, and BLX are respectively set to be “L, L, H, H, L, H”.

The voltage VSGDis greater than the voltage VSRC. Further, a voltage difference between the voltage VSGDand the voltage VSRCis greater than a threshold voltage when the drain-side select transistor STD functions as an NMOS transistor. Therefore, an electron channel is formed in the channel region of the drain-side select transistor STD connected to the selected bit line BLW, and the voltage VSRCis transferred. Meanwhile, a voltage difference between the voltage VSGDand the voltage VDDis smaller than a threshold voltage when the drain-side select transistor STD functions as an NMOS transistor. Therefore, the drain-side select transistor STD connected to the non-selected bit line BLPgoes into an OFF state.

Also, in the program operation, the voltage VSRCis supplied to the source line SL, and the ground voltage Vss is supplied to the source-side select gate lines SGS and SGSB. As a result, the source-side select transistors STS and STSB go into an OFF state.

In the program operation, a write pass voltage VPASSis supplied to the non-selected word line WLU. A voltage difference between the write pass voltage VPASSand the voltage VSRCis greater than a threshold voltage when the memory cell MC functions as an NMOS transistor regardless of the data recorded in the memory cell MC. Therefore, an electron channel is formed in the channel region of the non-selected memory cell MC, and the voltage VSRCis transferred to the write memory cell MC.

Also, in the program operation, a program voltage VPGMis supplied to the selected word line WLS. The program voltage VPGMis greater than the write pass voltage VPASS.

Here, the voltage VSRCis supplied to the channel of the semiconductor pillar120(memory string MS) connected to the selected bit line BLW. A relatively large electric field is generated between such a semiconductor pillar120and the selected word line WLS. This causes electrons in the channel of the semiconductor pillar120to tunnel through the tunnel insulating film131(FIG.9) into the charge storage film132(FIG.9). This increases a threshold voltage of the write memory cell MC.

The channel of the semiconductor pillar120connected to the non-selected bit line BLPis in an electrically floating state, and the voltage of this channel is raised (boosted) to about the write pass voltage VPASSdue to capacitive coupling with the non-selected word line WLU. Between such a semiconductor pillar120and the selected word line WLS, only an electric field smaller than the electric field described above is generated. Therefore, electrons in the channel of the semiconductor pillar120do not tunnel into the charge storage film132(FIG.9). Therefore, a threshold voltage of the inhibited memory cell MC does not increase.

Adjustment of Threshold Voltage of Drain-side Select Transistor STD

As described above, selection of write/inhibition of the memory cell MC is executed by ON/OFF of the drain-side select transistor STD. However, the threshold voltage of the drain-side select transistor STD varies when the memory die MD is manufactured. Therefore, the ON/OFF of the drain-side select transistor STD may not be executed as expected. Therefore, the threshold voltage of the drain-side select transistor STD is adjusted before shipment of the memory die MD. In the following description, adjustment of the threshold voltage of the drain-side select transistor STD may be referred to as program operation for the drain-side select gate line SGD.

Selected Bit Line BLWand Non-selected Bit Line BLP

Next, a program operation for the drain-side select gate line SGD according to the present embodiment will be described. First, with reference toFIG.19, the selected bit line BLWon which the program operation is performed and the non-selected bit line BLPfor which the program operation is inhibited will be described.FIG.19is a schematic circuit diagram illustrating a configuration of the string unit SU inFIG.5. The memory block BLK on which the program operation is performed may be referred to as a selected memory block BLK. Also, the memory block BLK for which the program operation is inhibited may be referred to as a non-selected memory block BLK.

The string unit SU according to the present embodiment is connected to n word lines WL0to WLn-1as illustrated inFIG.19. n is an integer of 1 or more. The n word lines WL0to WLn-1are first to nth word lines WL counted in a direction from the source-side select gate line SGS to the drain-side select gate line SGD. Also, the n word lines WL0to WLn-1are respectively connected to the gate electrodes of first to nth memory cells MC0to MCn-1in the memory string MS.

The string unit SU according to the present embodiment is connected to m bit lines BL0to BLm-1as illustrated inFIG.19. m is an integer of 1 or more. The m bit lines BL0to BLm-1are respectively connected to first to mth memory strings MS0to MSm-1in the string unit SU.

Odd-numbered bit lines BL0, BL2, . . . , BLm-4, and BLm-2of the m bit lines BL0to BLm-1may be referred to as bit lines BL_O. Odd-numbered memory strings MS0, MS2, . . . , MSm-4, and MSm-2connected to the odd-numbered bit lines BL0, BL2, . . . , BLm-4, and BLm-2may be referred to as memory strings MS_O.

Even-numbered bit lines BL1, BL3, . . . , BLm-3, and BLm-1of the m bit lines BL0to BLm-1, may be referred to as bit lines BL_E. Even-numbered memory strings MS1, MS3, . . . , MSm-3, and MSm-1connected to the even-numbered bit lines BL1, BL3, . . . , BLm-3, and BLm-1may be referred to as memory strings MS_E.

For example, as illustrated inFIG.19, it is assumed that the even-numbered bit line BLm-3(BL_E) is the selected bit line BLWand the even-numbered bit line BLm-1(BL_E) is the non-selected bit line BLP. Although not illustrated inFIG.19, it is assumed that the even-numbered bit line BLm-5(BL_E) is also the non-selected bit line BLP. When the even-numbered bit line BLm-3(BL_E) is subjected to a program operation, two odd-numbered bit lines BLm-4(BL_O) and BLm-2(BL_O) adjacent to the bit line BLm-3(BL_E) are inhibited from the program operation.

It is also assumed that the odd-numbered bit line BLm-2(BL_O) is the selected bit line BLWand the odd-numbered bit line BLm-4(BL_O) is the non-selected bit line BLP. When the odd-numbered bit line BLm-2(BL_O) is subjected to a program operation, two even-numbered bit lines BLm-3(BL_E) and BLm-1(BL_E) adjacent to the bit line BLm-2(BL_O) are inhibited from the program operation.

In the present embodiment, after the program operation of the drain-side select transistor STD connected to the even-numbered bit line BLm-3(BL_E) is performed, the program operation of the drain-side select transistor STD connected to the odd-numbered bit line BLm-2(BL_O) is performed. However, after the program operation of the drain-side select transistor STD connected to the odd-numbered bit line BLm-2(BL_O) is performed, the program operation of the drain-side select transistor STD connected to the even-numbered bit line BLm-3(BL_E) may be performed.

Program Operation for Drain-Side Select Gate Line SGD

Next, the program operation for the drain-side select gate line SGD will be described.FIG.20is a schematic waveform diagram for illustrating the program operation for the drain-side select gate line SGD according to the first embodiment.FIGS.21to26are schematic circuit diagrams of the sense amplifier unit SAU for illustrating the program operation for the drain-side select gate line SGD according to the first embodiment.

FIG.21is a schematic circuit diagram of the sense amplifier unit SAU_E connected to the bit line BL_E (BLm-3) as a program operation target at timings t101to t102inFIG.20.FIG.22is a schematic circuit diagram of the sense amplifier unit SAU_O connected to the bit line BL_O (BLm-4) for which the program operation is inhibited at the timings t101to t102in FIG.FIG.23is a schematic circuit diagram of the sense amplifier unit SAU_E connected to the bit line BL_E (BLm-1) for which the program operation is inhibited at the timings t101to t102inFIG.20.FIG.24is a schematic circuit diagram of the sense amplifier unit SAU_O connected to the bit line BL_O (BLm-2) as a program operation target at the timings t101to t102inFIG.20.

FIG.25is a schematic circuit diagram of the sense amplifier unit SAU_E connected to the bit line BL_E (BLm-3) as a program operation target at timings t102to t103inFIG.20.FIG.26is a schematic circuit diagram of the sense amplifier unit SAU_E connected to the bit line BL_E (BLm-1) for which the program operation is inhibited at the timings t102to t103in FIG.

A schematic circuit diagram of the sense amplifier unit SAU_O connected to the bit line BL_O (BLm-4) for which the program operation is inhibited at the timings t102to t103is similar toFIG.22. Also, a schematic circuit diagram of the sense amplifier unit SAU_O connected to the bit line BL_O (BLm-2) as a program operation target at the timings t101to t102is similar toFIG.24. Therefore, these figures are omitted.

At the timings t101to t103inFIG.20, the voltage VDDis supplied from the voltage generation circuit VG (FIG.4) to a voltage input terminal of the sense amplifier unit SAU. The voltage VDDis, for example, 1.5 V.

Also, at the timing t101, by changing the signal line BIAS_E of the sense amplifier unit SAU_E corresponding to the bit line BL_E (BLm-3and BLm-1) from the “L” level to the “H” level, the high breakdown voltage transistor60goes into an ON state as illustrated inFIGS.21and23. The ON state of the high breakdown voltage transistor60continues during a period from the timing t101to the timing t102. In addition, “O” in the drawing indicates that the state is in an ON state. Also, at the timing t101, the signal line BLS_E is at the “L” level, and the high breakdown voltage transistor45is in an OFF state as illustrated inFIGS.21and23. The OFF state of the high breakdown voltage transistor45continues during the period from the timing t101to the timing t102. In addition, “X” in the drawing indicates an OFF state. At the timings t101to t102, the high breakdown voltage transistor60goes into an ON state, thereby conducting the bit line BL_E (BLm-3and BLm-1) and the voltage supply line. As a result, the voltage Vinhibit from the voltage generation circuit VG is supplied to the bit line BL_E (BLm-3and BLm-1) at the timings t101to t102. The voltage Vinhibit is, for example, 8 V.

Thus, the bit lines BLm-3and BLm-1are charged by the voltage Vinhibit supplied via the high breakdown voltage transistor60.

In the sense amplifier unit SAU_E connected to the bit line BLm-3inFIG.21, “L” is latched in the latch circuit SDL, and the node INV_S is at “H”. Meanwhile, in the sense amplifier unit SAU_E connected to the bit line BLm-1inFIG.23, “H” is latched in the latch circuit SDL, and the node INV_S is at “L”.

Also, at the timing t101, by changing the signal line BIAS_O of the sense amplifier unit SAU_E corresponding to the bit line BL_O (BLm-4and BLm-2) from the “L” level to the “H” level, the high breakdown voltage transistor60goes into the ON state as illustrated inFIGS.22and24. The ON state of the high breakdown voltage transistor60continues during a period from the timing t101to the timing t102. Further, at the timing t101, the signal line BLS_O is at the “L” level, and the high breakdown voltage transistor45is in an OFF state as illustrated inFIGS.22and24. The OFF state of the high breakdown voltage transistor45continues during the period from the timing t101to the timing t102. At the timings t101to t102, the high breakdown voltage transistor60goes into the ON state, thereby conducting the bit line BL_O (BLm-4and BLm-2) and the voltage supply line. As a result, the voltage Vinhibit from the voltage generation circuit VG is supplied to the bit line BL_O (BLm-4and BLm-2) at the timings t101to t102.

Thus, the bit lines BLm-4and BLm-2are charged by the voltage Vinhibit supplied via the high breakdown voltage transistor60.

In the sense amplifier unit SAU_O connected to the bit line BLm-4inFIG.22, “H” is latched in the latch circuit SDL, and the node INV_S is at “L”. Meanwhile, in the sense amplifier unit SAU_O connected to the bit line BLm-2inFIG.24, “L” is latched in the latch circuit SDL, and the node INV_S is at “H”.

Further, as illustrated inFIG.20, at the timings t101to t102, the signal line BLC is at the “L” level and the clamp transistor44is in an OFF state.

Also, at the timings t101to t102, the drain-side select gate line SGD (denoted as “SGDsel” inFIG.20) of the selected memory block BLK is supplied with a voltage Vsg. The voltage Vsg is higher than the ground voltage Vss and lower than the write pass voltage VPASS.

At the timings t101to t102, the drain-side select gate line SGD (denoted as “SGDusel” inFIG.20) of the non-selected memory block BLK and the word line WL are also supplied with the voltage Vsg. Further, the ground voltage Vss is supplied to the source-side select gate line SGS.

At the timing t102, by changing the signal line BIAS_E of the sense amplifier unit SAU_E corresponding to the bit line BL_E (BLm-3) from the “H” level to the “L” level, the high breakdown voltage transistor60goes into the OFF state as illustrated inFIG.25. The OFF state of the high breakdown voltage transistor60continues during a period from the timing t102to the timing t103. In addition, the high breakdown voltage transistor45goes into an ON state as illustrated inFIG.25by changing the signal line BLS_E from the “L” level to the “H” level. The ON state of the high breakdown voltage transistor45continues during the period from the timing t102to the timing t103. At the timing t102, the signal line BLC changes from the “L” level to the “H” level.

Here, as illustrated inFIG.25, “L” is latched in the latch circuit SDL corresponding to the bit line BLm-3, and the node INV_S is at “H”, so the charging transistor47goes into an OFF state and the discharging transistor50goes into an ON state. Further, the charging transistor49is in an ON state. An “H” level voltage is applied to the gate electrode of the clamp transistor44, and the voltage VSRCis applied to the source terminal of the clamp transistor44via the discharging transistor50and charging transistor49. In this case, since the voltage between the gate electrode and the source terminal of the clamp transistor44is higher than a threshold voltage of the clamp transistor44, the clamp transistor44goes into an ON state. As a result, the voltage supply line to which the voltage VSRCis supplied and the bit line BL_E (BLm-3) are conducted, and the voltage VSRCis supplied to the bit line BL_E (BLm-3). The voltage VSRCis, for example, 0 V.

At the timing t102, by changing the signal line BIAS_E of the sense amplifier unit SAU_E corresponding to the bit line BL_E (BLm-1) the “H” level to the “L” level, the high breakdown voltage transistor60goes into an OFF state as illustrated inFIG.26. The OFF state of the high breakdown voltage transistor60continues during a period from the timing t102to the timing t103. In addition, the high breakdown voltage transistor45goes into an “ON” state as illustrated inFIG.26by changing the signal line BLS_E from the “L” level to the “H” level. The ON state of the high breakdown voltage transistor45continues during the period from the timing t102to the timing t103. At the timing t102, the signal line BLC changes from the “L” level to the “H” level.

Here, as illustrated inFIG.26, “H” is latched in the latch circuit SDL corresponding to the bit line BLm-1, and the node INV_S is at “L”, so the charging transistor47goes into the “ON” state and the discharging transistor50goes into the “OFF” state. The charging transistor49is in the ON state. Further, the voltage of signal line BLC at the “H” level is applied to the gate electrode of the clamp transistor44, and the voltage VDDis applied to the source terminal/drain terminal of the clamp transistor44via the charging transistors47and49. In this case, since the voltage between the gate electrode and the source terminal of the clamp transistor44is lower than the threshold voltage of the clamp transistor44, the clamp transistor44goes into the OFF state. As a result, the bit line BL_E (BLm-1) is in a floating state. In this case, the voltage of the bit line BL_E (BLm-1) rises to a voltage between the voltage Vinhibit and the voltage VSRCdue to capacitive coupling with the bit line BL_O (BLm-2) (FIG.20).

Thus, since the bit line BL_E (BLm-1) is maintained at a high voltage, a voltage difference between the gate electrode of the drain-side select transistor STD connected to the bit line BL_O (BLm-1) and the semiconductor pillar120becomes smaller. As a result, the program operation for the drain-side select transistor STD is inhibited.

As illustrated inFIG.20, at the timings t102to t103, a program voltage Vsg_prog is supplied to the drain-side select gate line SGDsel of the selected memory block BLK. The program voltage Vsg_grog is higher than the voltage Vsg.

At the timings t102to t103, the voltage Vsg is supplied to the drain-side select gate line SGDusel of the non-selected memory block BLK and the word line WL. Also, the ground voltage Vss is supplied to the source-side select gate line SGS.

Such control causes a large voltage difference between the semiconductor pillar120and the gate electrode of the drain-side select transistor STD connected to the selected bit line BLW(BLm-3) in the selected memory block BLK. As a result, the program operation for the drain-side select transistor STD is executed.

The bit lines BLm-4and BLm-2(BL_O) are supplied with the voltage Vinhibit via the high breakdown voltage transistor60over a period from the timing t101to the timing t103(seeFIGS.22and24). Accordingly, the bit lines BLm-4and BLm-2(BL_O) serve to shield the bit line BLm-3(BL_E).

Comparative Example

Next, a semiconductor storage device according to a comparative example will be described.

In the semiconductor storage device according to the first embodiment, as described with reference toFIG.6, of the signal lines BLS, the signal line BLS (signal line BLS_O) corresponding to the odd-numbered sense amplifier unit SAU_O and the signal line BLS (signal line BLS_E) corresponding to the even-numbered sense amplifier unit SAU_E are configured to be independently controllable. Similarly, of the signal lines BIAS, the signal lines BIAS (signal line BIAS_O) corresponding to the odd-numbered sense amplifier unit SAU_O and the signal lines BIAS (signal line BIAS_E) corresponding to the even-numbered sense amplifier unit SAU_E are configured to be independently controllable. Meanwhile, in the semiconductor storage device according to the comparative example, all the signal lines BLS are controlled in unison. Similarly, all the signal lines BIAS are controlled in unison.

Further, in the semiconductor storage device according to the first embodiment, the latch circuit SDL described with reference toFIG.7is configured with the ultra-low voltage transistors TrPVLand TrNVLdescribed with reference toFIGS.16and17. Meanwhile, in the semiconductor storage device according to the comparative example, the latch circuit SDL is configured with the low voltage transistors TrPLand TrNLdescribed with reference toFIGS.16and17.

Next, a program operation for the drain-side select gate line SGD according to the comparative example will be described.FIG.27is a schematic waveform diagram for illustrating the program operation for the drain-side select gate line SGD according to the comparative example.FIGS.28and29are schematic circuit diagrams of the sense amplifier unit SAU for illustrating the program operation for the drain-side select gate line SGD according to the comparative example. The sense amplifier unit SAU inFIG.28is connected to the selected bit line BLW. The sense amplifier unit SAU inFIG.29is connected to the non-selected bit line BLP. The configuration of the sense amplifier unit SAU is basically the same as the configuration described with reference toFIG.7.

At timings t201to t202inFIG.27, the voltage VDDis supplied from the voltage generation circuit VG to a voltage input terminal of the sense amplifier unit SAU. The voltage VDDis, for example, 3 V.

Also, at the timing t201, the signal line BIAS of the sense amplifier unit SAU inFIG.28is at the “L” level, and the high breakdown voltage transistor60goes into the OFF state. In addition, the high breakdown voltage transistor45goes into the ON state by changing the signal line BLS from the “L” level to the “H” level. The clamp transistor44goes into the ON state by changing the signal line BLC from the “L” level to the “H” level. As illustrated inFIG.28, “L” is latched in the latch circuit SDL corresponding to the selected bit line BLW, and the node INV_S is at “H”, and thus the charging transistor47goes into the OFF state and the discharging transistor50goes into the ON state. Further, the charging transistor49is in the ON state. Therefore, the voltage VSRCis supplied to the selected bit line BLWvia the discharging transistor50, the charging transistor49, the clamp transistor44, and the high breakdown voltage transistor45.

Also, at the timing t201, the signal line BIAS of the sense amplifier unit SAU inFIG.29is at the “L” level, and the high breakdown voltage transistor60goes into the OFF state. In addition, the high breakdown voltage transistor45goes into the ON state by changing the signal line BLS from the “L” level to the “H” level. The clamp transistor44goes into the ON state by changing the signal line BLC from the “L” level to the “H” level. As illustrated inFIG.29, “H” is latched in the latch circuit SDL corresponding to the non-selected bit line BLPand the node INV_S is at “L”, and thus the charging transistor47goes into the ON state and the discharging transistor50goes into the OFF state. Further, the charging transistor49is in the ON state. Therefore, the voltage VDDis supplied to the non-selected bit line BLPvia the charging transistor47, the charging transistor49, the clamp transistor44, and the high breakdown voltage transistor45.

Effect

As described with reference toFIG.18, in the program operation for the memory cell MC, by supplying the voltage VSRCto the non-selected bit line and supplying the voltage VSGDto the drain-side select gate line SGD, the drain-side select transistor STD connected to the non-selected bit line BLPis in the OFF state (cut off). Further, by supplying the write pass voltage VPASSto the non-selected word line WLU, the voltage of the channel of the semiconductor pillar120connected to the non-selected bit line BLPis raised (boosted) to about the write pass voltage VPASSto reduce the voltage difference from the program voltage VPGM. This prevents fluctuations in the threshold voltage of the inhibited memory cells MC.

The drain-side select gate line SGD is provided above the word line WL. Therefore, in the program operation for the drain-side select gate line SGD, the drain-side select transistor STD connected to the non-selected bit line BLPcannot be cut off to raise (boost) the voltage of the channel of the semiconductor pillar120.

Therefore, in the program operation for the drain-side select gate line SGD according to the comparative example, for example, by setting the voltage VDDto a relatively high voltage (for example, about 3 V), a high voltage can be supplied to the non-selected bit line BLP. As a result, the voltage difference between the voltage VDDof the non-selected bit line BLPand the program voltage supplied to the drain-side select gate line SGD is reduced, and thus the state can be in a program inhibition state.

However, in the program operation for the drain-side select gate line SGD according to the comparative example, as described above, a relatively high voltage (for example, 3 V) is supplied as the voltage VDDto the source terminal of the charging transistor47. Therefore, as described with reference toFIG.28, in the sense amplifier circuit SA corresponding to the selected bit line BLW, in order to cause the state of the charging transistor47to be in the OFF state, it is necessary to supply a relatively high voltage to the gate electrode of the charging transistor47as well. For this purpose, it is necessary to supply this relatively high voltage from the latch circuit SDL connected to the gate electrode of the charging transistor47. Therefore, in order to perform the program operation for the drain-side select gate line SGD according to the comparative example, the latch circuit SDL of the sense amplifier unit SAU cannot be configured with the ultra-low voltage transistors TrNVLand TrPVL(FIGS.16and17), and is configured with the low voltage transistors TrNLand TrPL(FIGS.14and15).

For example,FIG.30is a schematic circuit diagram illustrating types of transistors forming the sense amplifier unit SAU according to the comparative example. As illustrated in FIG. the latch circuit SDL is configured with the low voltage transistors TrNLand TrPL(FIGS.14and15). The latch circuits DL0to DLnLother than the latch circuit SDL are configured with the ultra-low voltage transistors TrNVLand TrPVL(FIGS.16and17). The sense amplifier circuit SA is configured with the low voltage transistors TrNLand TrPL(FIGS.14and15). The high breakdown voltage transistor45and the high breakdown voltage transistor60are configured with the high voltage transistors TrNHand TrPH(FIGS.12and13).

Reducing an area of the peripheral circuit PC is desirable. In particular, the number of sense amplifier units SAU is very large because the sense amplifier units SAU are provided corresponding to bit lines BL. Since an area occupied by many sense amplifier units SAU is large, when the area of the sense amplifier unit SAU can be reduced even a little, the area of the sense amplifier module SAM can also be reduced.

Therefore, in the present embodiment, in the program operation for the drain-side select gate line SGD, as described with reference toFIGS.21and22, the voltage Vinhibit from the voltage generation circuit VG is supplied to the non-selected bit line BLPvia the high breakdown voltage transistor60. Further, as described with reference toFIGS.25and26, the voltage VSRCis supplied to the selected bit line BLWvia the clamp transistor44and the non-selected bit line BLPcuts off the clamp transistor44, in such a manner that a relatively high voltage is maintained. According to such a method, since it is not necessary to supply a relatively high voltage to the gate electrode of the charging transistor47, the latch circuit SDL of the sense amplifier unit SAU can be configured with the ultra-low voltage transistors TrNVLand TrPVL(FIGS.16and17). Therefore, the area of the sense amplifier unit SAU can be reduced.

For example,FIG.31is a schematic circuit diagram illustrating types of transistors forming the sense amplifier unit SAU according to the first embodiment. As illustrated inFIG.31, the latch circuit SDL is configured with the ultra-low voltage transistors TrNVLand TrPVL(FIGS.16and17). The latch circuits DL0to DLnLother than the latch circuit SDL are also configured with the ultra-low voltage transistors TrNVLand TrPVL. The sense amplifier circuit SA is configured with the low voltage transistors TrNLand TrPL(FIGS.14and15). The high breakdown voltage transistor45and the high breakdown voltage transistor60are configured with the high voltage transistors TrNHand TrPH(FIGS.12and13). The configuration of the transistor illustrated inFIG.31is an example, and the configuration is not limited to such a configuration.

In addition, in the first embodiment, the non-selected bit line BLPis in the floating state in the program operation for the drain-side select transistor. Therefore, for example, when the selected bit line BLWand the non-selected bit line BLPin the floating state are adjacent to each other in the X direction, the voltage of the non-selected bit line BLPmay drop due to capacitive coupling with the selected bit line BLW. Therefore, in the first embodiment, as described with reference toFIG.21, when executing the program operation on the drain-side select transistor corresponding to one of the bit line BL_O and the bit line BL_E, the other is supplied with a fixed voltage and used as a shield. According to such a method, it is possible to prevent fluctuations in the voltage of the non-selected bit line BLP, suitably maintain the cut-off state of the clamp transistor44, and prevent erroneous write.

Second Embodiment

In a program operation for a drain-side select gate line SGD according to a second embodiment, the program operation (FIG.20: first embodiment) is executed with the even-numbered bit line BL_E as the selected bit line BLWand the non-selected bit line BLP, and the program operation is executed with the odd-numbered bit line BL_O as the selected bit line BLWand the non-selected bit line BLP, and then a verification operation is executed.

FIG.32is a schematic waveform diagram for illustrating the program operation and a verification operation for the drain-side select gate line SGD according to the second embodiment. An operation (Even Prog) at timings t101to t103inFIG.32is the same as the operation at the timings t101to t103inFIG.20. Therefore, redundant description is omitted.

An operation (Odd Prog) at timings t104to t106inFIG.32is an operation in which “Even” and “Odd” are interchanged in the operation at the timings t101to t103inFIG.20. That is, in the operation at the timings t101to t103inFIG.20, the bit line BLm-3(BL_E) is set as the selected bit line BLW, the bit line BLm-1(BL_E) is set as the non-selected bit line BLP, and the bit lines BLm-4and BLm-2(BL_O) are set as shields. On the other hand, in the operation at the timings t104to t106inFIG.32, the bit line BLm-2(BL_O) is set as the selected bit line BLW, the bit line BLm-4(BL_O) is set as the non-selected bit line BL P , and the bit lines BLm-3and BLm-1(BL_E) are set as shields (FIG.19).

An operation at the timings t107to t111inFIG.32is the verification operation. At the timing t107, by changing the signal line BLS_E corresponding to the selected bit line BLW(BLm-3) from the “L” level to the “H” level, the high breakdown voltage transistor45goes into the ON state. In addition, the high breakdown voltage transistor45goes into the ON state by changing the signal line BLS_O corresponding to the selected bit line BLW(BLm-2) from the “L” level to the “H” level.

Although illustration is omitted, a verification voltage is supplied to the drain-side select gate line SGD during the timings t107to t110inFIG.32. The verification voltage is a voltage for confirming whether the threshold voltage of the drain-side select gate line SGD reaches the target value. The verification voltage may be, for example, a voltage as large as the voltage Vsg (FIG.20) or a voltage as large as the voltage VSGD(FIG.18). The verification voltage is at least greater than the ground voltage Vss and the voltage VSRCand less than the program voltage Vsg_grog (FIG.20).

At the timing t107, by changing the signal lines BLX and BLC corresponding to the selected bit line BLW(BLm-3and BLm-2) from the “L” level to the “H” level, the charging transistor49and the clamp transistor44go into the ON state. In this case, since “L” is latched in the latch circuit SDL and the node INV_S is at “H”, the voltage VDDis supplied to the selected bit line BLWfor charging.

At the timing t108, by changing the signal line HLL corresponding to the selected bit line BLW(BLm-3and BLm-2) from the “L” level to the “H” level, the charging transistor46goes into the ON state. In this case, the voltage VDDand the sense node SEN are electrically connected, and charge from voltage VDDis accumulated in the sense node SEN.

At the timing t109, by changing the signal line XXL corresponding to the selected bit line BLW(BLm-3and BLm-2) from the “L” level to the “H” level, the discharging transistor43goes into the ON state. In this case, the sense node SEN and the selected bit line BLWare electrically connected. The sense transistor41goes into the ON state or the OFF state depending on whether the charge accumulated in the sense node SEN flows to the selected bit line BLW, and the ON state/OFF state of the drain-side select transistor STD connected to the selected bit line BLWis determined.

Further, at the timing t110, by changing the signal line STB corresponding to the selected bit line BLW(BLm-3and BLm-2) from the “L” level to the “H” level, the switch transistor42goes into the ON state. The charge in the wiring LBUS is discharged depending on whether the sense transistor41is in the ON state. Then, the state of the wiring LBUS is set in the latch circuit SDL.

According to such a method, after the program operation for the even-numbered selected bit line BLWand the program operation for the odd-numbered selected bit line BLWare completed, the verification operation for those selected bit lines BLWcan be collectively performed. As a result, the program operation and the verification operation can be made more efficient.

Third Embodiment

FIG.33is a schematic waveform diagram for illustrating a program operation for a drain-side select gate line SGD according to a third embodiment. In the first embodiment described above, by changing the signal line BIAS_O from the “L” level to the “H” level at the timing t101inFIG.20, the voltage Vinhibit from the voltage generation circuit VG is supplied to the bit line BL_O to raise the voltage of the bit line BL_O to the voltage Vinhibit. In contrast, in the third embodiment, by changing the signal line BIAS_O from the “L” level to the “H” level at a timing t120after the timing t102, the voltage Vinhibit from the voltage generation circuit VG is supplied to the bit line BL_O to raise the voltage of the bit line BL_O to the voltage Vinhibit. As a result, the voltage of the bit line BL_E (BLm-1) in the floating state rises due to capacitive coupling with the bit line BL_O. The operation at the timings t101to t103inFIG.33is the same as the operation at the timings t101to t103inFIG.20, so redundant description will be omitted.

According to such a method, since the voltage of the bit line BL_E (BLm-1) in the floating state can be raised, erroneous write can be more reliably prevented by raising the channel voltage of the drain-side select transistor STD connected to the non-selected bit line BL P .

Other Embodiments

Hereinbefore, the semiconductor storage devices according to the embodiments are described above. However, the above descriptions are merely examples, and the configuration, method, and the like described above may be adjusted as appropriate.

For example, in the second embodiment, after the program operation for the even-numbered bit line BL_E is executed, the program operation for the odd-numbered bit line BL_O is executed. However, after the program operation for the odd-numbered bit line BL_O is executed, the program operation for the even-numbered bit line BL_E may be executed.

In addition, in the first to third embodiments, the sequencer SQC simultaneously switches the ON state/OFF state of the transistor by switching signals to a plurality of signal lines at the timing t101to the timing t111. However, the sequencer SQC may switch the ON state/OFF state of the transistor at different timings by switching the signals to the plurality of signal lines at different timings. For example, the timing at which the high breakdown voltage transistor60switches from the ON state to the OFF state may be shifted from the timing at which the high breakdown voltage transistor45switches from the OFF state to the ON state.

In each of the embodiments described above, a NAND flash memory with a three-dimensional structure is illustrated, and the embodiments of the present disclosure can also be applied to a NAND flash memory that does not have a three-dimensional structure.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.