Patent ID: 12255155

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Some embodiments of the disclosure are described. Additional operations can be provided before, during, and/or after the stages described in these embodiments. Some of the stages that are described can be replaced or eliminated for different embodiments. Additional features can be added to the semiconductor device structure. Some of the features described below can be replaced or eliminated for different embodiments. Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order.

Embodiments of the disclosure may relate to 3D packaging or 3D-IC devices. Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3D-IC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3D-IC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.

FIGS.1A-1Jare cross-sectional views of various stages of a process for forming a package structure, in accordance with some embodiments. As shown inFIG.1A, semiconductor dies104A and104B are attached or placed over a carrier substrate100, in accordance with some embodiments. An adhesive layer102may be used to affix the semiconductor dies104A and104B.

Each of the semiconductor dies104A and104B includes a semiconductor substrate106and an interconnection structure107formed on the semiconductor substrate106. The interconnection structure107includes multiple interlayer dielectric layers and multiple conductive features formed in the interlayer dielectric layers. These conductive features include conductive lines, conductive vias, and/or conductive contacts. Some portions of the conductive features may be used as conductive pads.

In some embodiments, various device elements are formed in and/or on the semiconductor substrate106. Examples of the various device elements include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc.), diodes, light sensors, one or more other suitable elements, or a combination thereof.

The device elements are interconnected through the interconnection structure107to form integrated circuit devices. The integrated circuit devices include logic devices, memory devices (e.g., static random access memories, SRAMs), radio frequency (RF) devices, input/output (I/O) devices, system-on-chip (SoC) devices, logic devices, one or more other applicable types of devices, or a combination thereof.

In some embodiments, the semiconductor die104A further includes conductive features110A, and the semiconductor die104B further includes conductive features110B. The conductive features110A and110B may include metal pillars. In some embodiments, each of the conductive features110A and110B has a vertical sidewall. The conductive features110A and110B may be made of or include copper, titanium, cobalt, gold, platinum, one or more other suitable materials, or a combination thereof. The conductive features110A and110B may be formed using an electroplating process, a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, one or more other applicable processes, or a combination thereof.

In some embodiments, each of the semiconductor dies104A and104B further includes a passivation layer108. The passivation layer108is used to protect the interconnection structure106and the device elements thereunder. The passivation layer108may include openings that expose the conductive features110A and110B. The passivation layer108may be made of or include polyimide (PI), poly-p-phenylenebenzobisthiazole (PBO), silicon nitride, silicon oxynitride, one or more other suitable materials, or a combination thereof. The passivation layer108may be formed using a spin coating process, a CVD process, a spray coating process, one or more other applicable processes, or a combination thereof. A patterning process may be used to make to passivation layer108with desired patterns.

Afterwards, a protective layer112is formed over the carrier substrate100, as shown inFIG.1Ain accordance with some embodiments. The protective layer112surrounds and covers the semiconductor dies104A and104B. The protective layer112may be made of or include a molding material (or a molding compound material). The molding material may include an epoxy-based resin with fillers dispersed therein. The fillers may include fibers (such as silica fibers), particles (such as silica particles), or a combination thereof. The protecting layer112may be formed using an injecting process, a spin coating process, a spray coating process, one or more other applicable processes, or a combination thereof.

Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the protective layer112is made of or includes silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, one or more other suitable materials, or a combination thereof. In these cases, the protective layer112may be deposited using a CVD process, a spin-coating process, a spray coating process, one or more other applicable processes, or a combination thereof.

As shown inFIG.1B, a planarization process is used to thin the protective layer112, in accordance with some embodiments. As a result, the conductive features110A and110B of the semiconductor dies104A and104B are exposed. In some embodiments, the top surfaces of the conductive features110A and110B are substantially coplanar with the top surface of the protective layer112that is thinned. In some embodiments, the top surfaces of the protective layer112, the passivation layer108, and the conductive features110A and110B are substantially coplanar. The planarization process may include a grinding process, a chemical mechanical polishing (CMP) process, a dry polishing process, an etching process, a cutting process, one or more other applicable processes, or a combination thereof.

As shown inFIG.1C, a dielectric layer114is formed over the protective layer112and the semiconductor dies104A and104B, in accordance with some embodiments. The dielectric layer114may be used to protect the semiconductor dies104A and104B. The conductive features110A and110B of the semiconductor dies104A and104B are covered by the dielectric layer114.

The dielectric layer114may be made of or include a polymer material. The polymer material includes, for example, polyimide (PI), poly-p-phenylenebenzobisthiazole (PBO), one or more other suitable polymer materials, or a combination thereof. The dielectric layer114may be formed using a spin coating process, a spray coating process, one or more other applicable processes, or a combination thereof.

In some other embodiments, the dielectric layer114is made of or includes an oxide material (such as silicon oxide), a nitride material (such as silicon nitride), one or more other suitable materials, or a combination thereof. In these cases, the dielectric layer114may be deposited using a CVD process, a spin coating process, a spray coating process, one or more other applicable processes, or a combination thereof.

As shown inFIG.1D, the dielectric layer114is patterned to form an opening116that partially exposes the semiconductor dies104A and104B, in accordance with some embodiments. Some of the conductive features110A of the semiconductor die104A are exposed by the opening116, and some other conductive features110A are still covered by the dielectric layer114. Similarly, some of the conductive features110B of the semiconductor die104B are exposed by the opening116, and some other conductive features110B are still covered by the dielectric layer114. In some embodiments, a portion of the protective layer112between the semiconductor dies104A and104B is also exposed by the opening116, as shown inFIG.1D.

In some embodiments, the opening116is formed using a photolithography process. In some other embodiments, the opening116is formed using a photolithography process and an etching process. In some other embodiments, the opening116is formed using an energy beam drilling process (such as a laser drilling process or an electron-beam drilling process).

However, embodiments of the disclosure are not limited thereto. Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the dielectric layer114is not formed.

As shown inFIG.1E, conductive elements118and conductive pillars120are formed over the dielectric layer114, in accordance with some embodiments. The conductive elements118may function as under bump metallization (UBM) structures and/or redistribution layers. In some embodiments, the conductive pillars120include vertical sidewalls. The conductive elements118and the conductive pillars120may be made of or include copper, cobalt, nickel, titanium, gold, platinum, one or more other suitable materials, or a combination thereof. The formation of the conductive elements118and the conductive pillars120may include an electroplating process, a PVD process, an electroless plating process, one or more other applicable processes, or a combination thereof.

Afterwards, a semiconductor die122is formed or received, as shown inFIG.1Fin accordance with some embodiments. The semiconductor die122may be used to form electrical connections between the semiconductor dies104A and104B. The semiconductor die122may function as a die-to-die communication medium. In some embodiments, the semiconductor die122includes multiple conductive features including conductive lines and conductive vias. Each of these conductive features may electrical connect device elements formed in the semiconductor dies104A and104B. The line width or pitch of the conductive features in the semiconductor die122may be smaller than about 0.4 μm. The line width or pitch of the conductive features in the semiconductor die122may be in a range from about 10 nm to about 0.4 μm. In some other embodiments, the semiconductor die122further includes device elements such as transistors. In some other embodiments, the semiconductor die122does not include any device element.

FIGS.2A-2Fare cross-sectional views of various stages of a process for forming a package structure, in accordance with some embodiments. In some embodiments,FIGS.2A-2Fshows various stages of a process for forming the semiconductor die122.

As shown inFIG.2A, a semiconductor substrate124is provided or received. In some embodiments, the semiconductor substrate124is a semiconductor wafer, such as a silicon wafer. In some embodiments, multiple conductive features126are formed in the semiconductor substrate124. In some embodiments, the conductive features extend from the front surface of the semiconductor substrate124towards the back surface of the semiconductor substrate124. The conductive features126may serve as conductive vias to provide electrical connections in vertical directions.

The conductive features126may be made of or include copper, cobalt titanium, aluminum, tungsten, gold, platinum, nickel, one or more other suitable materials, or a combination thereof. In some embodiments, a photolithography and an etching process are used to form multiple via openings that extend from the front surface towards the back surface of the semiconductor substrate126. Afterwards, a conductive material layer is deposited over the front surface to fill the via openings. The conductive material layer may be deposited using a PVD process, a CVD process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof.

Afterwards, a planarization process may be performed to remove the portion of the conductive material layer outside of the via openings. As a result, the remaining portions of the conductive material layer remaining in the via openings form the conductive features126. The planarization process may include a CMP process, a grinding process, a dry polishing process, an etching process, one or more other applicable processes, or a combination thereof.

In some embodiments, an insulating layer (not shown) is formed between the semiconductor substrate124and the conductive features126. The insulating layer is used to electrically isolate the semiconductor substrate124and the conductive features126. Therefore, any unwanted short circuiting between the conductive features126may be prevented. The insulating layer may be made of or include silicon oxide, silicon oxynitride, silicon nitride, germanium oxide, one or more other suitable materials, or a combination thereof.

In some embodiments, the insulating layer is deposited over the sidewalls and bottoms of the via openings before the formation of the conductive material layer. The insulating layer may be deposited using a CVD process, an atomic layer deposition (ALD) process, a PVD process, a thermal oxidation process, one or more other applicable processes, or a combination thereof.

In some embodiments, conductive elements128are formed over the conductive features126, as shown inFIG.2A. The conductive elements128may be used to receive or support subsequently formed conductive bumps. The conductive elements128may also be used to form electrical connections between some of the conductive features126.

In some embodiments, a passivation layer125is formed over the front surface of the semiconductor substrate124, as shown inFIG.2A. The passivation layer125may partially cover the conductive elements128. In some other embodiments, the top surface of the passivation layer125may be substantially coplanar with the top surfaces of the conductive elements128. The passivation layer125may have multiple openings that expose the conductive elements128. The material and formation method of the passivation layer125may be the same as or similar to those of the passivation layer108of the semiconductor die104A or104B.

As shown inFIG.2B, connectors130are formed over the conductive elements128, in accordance with some embodiments. The connectors130may include solder bumps. The solder bumps may include an alloy of tin and other metal materials. In some embodiments, the solder bumps are substantially free of lead. In some embodiments, the connectors130include metal pillars. The metal pillars may be made of or include copper, cobalt, titanium, aluminum, gold, one or more other suitable materials, or a combination thereof. The metal pillars may include vertical sidewalls.

The formation method of the connectors130may involve an electroplating process, an electroless plating process, a PVD process, one or more other applicable processes, or a combination thereof. The formation method of the connectors130may further involve a reflow process, an etching process, or other applicable processes. In some embodiments, each of the connectors130includes a combination of a solder bump and a metal pillar.

As shown inFIG.2C, an insulating film (or a non-conductive film)132is formed over the semiconductor substrate124to cover the connectors130, in accordance with some embodiments. In some embodiments, the insulating film132is made of or includes an epoxy-based resin. Similar to the molding material for forming the protective layer112, the insulating film132is made of or includes an epoxy-based resin with fillers dispersed therein, in accordance with some embodiments. The fillers may include fibers (such as silica fibers), particles (such as silica particles), or a combination thereof. In some embodiments, the insulating film132includes a smaller weight percentage of the fillers than that of the protective layer112. In some embodiments, the insulating film132has a weight percentage of the fillers that is in a range from about 20 wt % to about 30 wt %. The protective layer112may have a weight percentage of the fillers that is in a range from about 50 wt % to about 60 wt %. In some embodiments, the insulating film132is formed over the connectors130using a lamination process. In some embodiments, the insulating film132is adhesive.

As shown inFIG.2D, the insulating film132is partially removed to expose the connectors130, in accordance with some embodiments. The exposed connectors130may be used to electrically connect the conductive features110A and110B of the semiconductor dies104A and104B after a subsequent bonding process.

In some embodiments, a thinning process is used to partially remove the insulating film132. The thinning process may include a cutting process, a grinding process, a dry polishing process, a CMP process, an etching process, one or more other applicable processes, or a combination thereof. In some embodiments, the connectors130are also partially removed during the thinning process. In some embodiments, the top surfaces of the connectors130are substantially coplanar with the top surface of the insulating film132after the thinning process, as shown inFIG.2D.

As shown inFIG.2E, the structure shown inFIG.2Dis attached onto a carrier202, in accordance with some embodiments. The carrier202may be a dicing tape to temporarily adhere the wafer for performing a subsequent dicing process.

As shown inFIG.2F, the structure shown inFIG.2Eis diced to form trenches204, in accordance with some embodiments. A die saw may be used to form the trenches204. The trenches204separate the semiconductor substrate124into multiple semiconductor dies122.

Afterwards, one of the semiconductor dies122is picked up and disposed over the semiconductor dies104A and104B, as shown inFIG.1Fin accordance with some embodiments. The semiconductor die122partially covers the semiconductor dies104A and104B. The semiconductor die122is bonded with the semiconductor dies104A and104B through connectors130, in accordance with some embodiments. Because the dielectric layer114is patterned to expose the conductive features110A and110B of the semiconductor dies104A and104B, electrical connection between the connectors130and the conductive features110A and110B of the semiconductor dies104A and104B may be formed more easily. In some embodiments, the semiconductor die122is bonded with the semiconductor dies104A and104B simultaneously.

In some embodiments, some of the connectors130are bonded onto and electrically connected to the exposed conductive features110A of the semiconductor die104A. Some of the connectors130are bonded onto and electrically connected to the exposed conductive features110B of the semiconductor die104B. The semiconductor die122may function as a communication die to transmit electrical signals between the semiconductor dies104A and104B.

In some embodiments, because the opening116has a large size, the quality of the patterning process for forming the opening116in the dielectric layer114is ensured. No residues generated during the patterning process of the dielectric layer114is left on the conductive features110A and110B, which allows good connection between the connectors130and the exposed conductive features110A and110B.

In some other cases, smaller openings (such as openings each having a width smaller than about 7 μm) are designed to be formed in the dielectric layer114to expose the conductive features110A and110B. Because the photolithography process for forming smaller openings is more difficult than that for forming a larger opening, an under-development issue may occur. A portion of the dielectric layer114may be under-developed and still be remaining on the surfaces of the conductive features110A and110B. As a result, the residues might negatively affect the connection between the connectors130and the conductive features110A and110B. The performance and reliability of the package structure may be negatively affected.

In some embodiments, the semiconductor die122is bonded with the semiconductor dies104A and104B using a thermal compression bonding process. In some embodiments, the insulating film132is adhesive. Therefore, the semiconductor die122is affixed on the semiconductor dies104A and104B during the thermal compression bonding process. Due to the adhesion of the insulating film132, the thermal compression bonding process is facilitated.

In the thermal compression bonding process, a die holder may be used to handle and hold the semiconductor die122against the semiconductor dies104A and104B. The insulating film132also helps to improve adhesion between the semiconductor die122and the underlying elements. In the thermal compression bonding process, a compression pressure is applied on the semiconductor die122at a high temperature. The applied compression pressure may ensure the connectors130to be in direct contact with the conductive features110A and110B of the semiconductor dies104A and104B. Therefore, the cold-joint issues between the connectors130and the conductive features110A and110B may be prevented or reduced.

In some embodiments, the operation temperature of the thermal compression bonding process is in a range from about 150 degrees C. to about 350 degrees C. In some embodiments, the applied compression pressure of the thermal compression bonding process is in a range from about 1 MPa to about 100 MPa. However, in some other embodiments, the applied compression pressure and/or the operation temperature are tuned to be in different ranges.

The thermal compression bonding process and the adhesive insulating film132may allow the semiconductor die122to have a small thickness. The thickness of the semiconductor die122may be in a range from about 50 μm to about 150 μm. Due to the small thickness of the semiconductor die122, a subsequently formed protective layer (such as a molding layer) may also be formed thinner accordingly. Because the amount of the molding material for forming the protective layer is reduced, the warpage of the package structure after a subsequent thermal operation is significantly reduced. The quality and reliability of the package structure are improved.

In some other cases, the thermal compression bonding process and/or the insulating film132are/is not used. For example, the semiconductor die122is bonded using a reflow process where no additional compression pressure is applied. In these cases, the semiconductor die122may need to have a greater thickness (such as greater than 150 μm) to ensure a smooth bonding process and prevent the cold-joint issues since a thicker semiconductor die is easier to be handled than a thinner semiconductor die. However, if the semiconductor die122is greater than 150 μm, a large amount of warpage might occur after a subsequent thermal operation since a thicker molding layer may be needed to encapsulate the semiconductor die122that is thicker. The quality and reliability of the package structure may be negatively affected. For example, cold-joint issues due to the high warpage might happen.

In some embodiments, the insulating film132is not in direct contact with the dielectric layer114. As shown inFIG.1F, the insulating film132has an edge E1, and the dielectric layer has an edge E2. In some embodiments, the edge E1is the closet portion of the insulating film132to the dielectric layer114. The edge E1of the insulating film132is separated from the edge E2of the dielectric layer114by a distance D. The distance D may be in a range from about 2 μm to about 10 μm. In some embodiments, the distance D is the shortest distance between the insulating film132and the dielectric layer114.

As shown inFIG.1G, a protective layer134is formed to cover the structure shown inFIG.1F, in accordance with some embodiments. The material and formation method of the protective layer134may be the same as or similar to those of the protective layer112. The insulating film132is separated from the dielectric layer114by a portion of the protective layer134, as shown inFIG.1Gin accordance with some embodiments.

As shown inFIG.1H, the protective layer134is thinned, in accordance with some embodiments. As a result, the conductive pillars120are exposed. A planarization process may be used to thin the protective layer134. The planarization process may include a grinding process, a dry polishing process, a CMP process, a cutting process, an etching process, one or more other applicable processes, or a combination thereof.

In some embodiments, the planarization process further remove a portion of the conductive pillars120and a portion of the semiconductor die122. The semiconductor substrate124of the semiconductor die122is partially removed. As a result, conductive features114formed in the semiconductor die122are also exposed. The conductive features114may function as through substrate vias (TSVs).

As shown inFIG.1I, a redistribution structure136is formed over the structure shown inFIG.1H, in accordance with some embodiments. The redistribution structure136may include multiple dielectric layers and multiple conductive features formed between the dielectric layers. The conductive features include conductive vias and conductive lines. Some of the conductive features are electrically connected to the conductive pillars120. Some of the conductive features are electrically connected to the conductive features114of the semiconductor die122.

The dielectric layers of the redistribution structure132may be made of or include PBO, PI, silicon oxide, one or more other suitable materials, or a combination thereof. The conductive features of the redistribution structure132may be made of or include copper, aluminum, cobalt, titanium, gold, platinum, one or more other suitable materials, or a combination thereof. The formation of the redistribution structure132may involve multiple coating (or deposition) processes, photolithography processes, and/or etching processes.

Afterwards, conductive bumps138are formed over the redistribution structure136, as shown inFIG.1Iin accordance with some embodiments. The conductive bumps138may include solder bumps, metal pillars, one or more other suitable conductive elements, or a combination thereof. The solder bumps may include an alloy of tin and other metal materials. In some embodiments, the solder bumps is substantially free of lead. The metal pillars may be made of or include copper, cobalt, titanium, aluminum, gold, one or more other suitable materials, or a combination thereof. The metal pillars may include vertical sidewalls. The formation method of the conductive bumps138may involve an electroplating process, an electroless plating process, a PVD process, one or more other applicable processes, or a combination thereof. The formation method of the conductive bumps138may further involve a reflow process, an etching process, or other applicable processes.

As shown inFIG.1J, the carrier substrate100is removed, in accordance with some embodiments. As a result, a package structure is formed. The package structure may be integrated with other structures. For example, the package structure may be bonded onto a printed circuit board, a redistribution substrate, an interposer substrate, or another package structure. In some other embodiments, another redistribution structure is formed over the back surfaces of the protective layer112and the semiconductor dies104A and104B.

Many variations and/or modifications can be made to embodiments of the disclosure.FIG.3is a cross-sectional view of a package structure, in accordance with some embodiments. In some embodiments, each of the connectors130includes a metal pillar302and a solder element304. The material and formation method of the metal pillar302may be the same as or similar to those of the conductive pillars120. The solder element304may include an alloy of tin and other metal materials. In some embodiments, the solder bumps is substantially free of lead.

As illustrated in the embodiments shown inFIGS.2C-2F and1F, the insulating film132is partially removed before the semiconductor die122is bonded onto the semiconductor dies104A and104B. However, embodiments of the disclosure are not limited thereto. Many variations and/or modifications can be made to embodiments of the disclosure.FIGS.4A-4Bare cross-sectional views of various stages of a process for forming a package structure, in accordance with some embodiments.

As shown inFIG.4A, a structure the same as or similar to the structure shown inFIG.2Cis attached onto the carrier202, in accordance with some embodiments. The insulating film132is not partially removed. Therefore, the connectors130are covered by the insulating film132.

As shown inFIG.4B, the structure shown inFIG.4Ais diced to form trenches204, in accordance with some embodiments. The trenches204separate the semiconductor substrate124into multiple semiconductor dies122.

FIGS.5A-5Bare cross-sectional views of various stages of a process for forming a package structure, in accordance with some embodiments. As shown inFIG.5A, one of the semiconductor dies122shown inFIG.4Bis picked up and disposed over the semiconductor dies104A and104B, in accordance with some embodiments. The semiconductor die122is bonded with the semiconductor dies104A and104B through the connectors130, in accordance with some embodiments.

In some embodiments, the semiconductor die122is bonded onto the semiconductor dies104A and104B using a thermal compression bonding process. As mentioned above, a compression pressure is applied on the semiconductor die122during the thermal compression bonding process. In some embodiments, due to the compression pressure, the connectors130penetrate through the insulating film132to be in direct contact with the conductive features110A and110B of the semiconductor dies104A and104B. In some embodiments, a portion of the insulating film132is squeezed beyond an edge of the semiconductor die122due to the compression pressure applied during the thermal compression bonding process.

As shown inFIG.5A, after bonding the semiconductor die122to the semiconductor dies104A and104B, one (or more) squeezed portion502of the insulating film132are formed, in accordance with some embodiments. The squeezed portion502extends beyond an edge of the semiconductor substrate124of the semiconductor die122. In some embodiments, the squeezed portion502has a sidewall surface that curve outwards with respect to an inner portion of the squeezed portion502, as shown inFIG.5A.

In some embodiments, the insulating film132has multiple squeezed portions502, as shown inFIG.5A. In some embodiments, each of the squeezed portions502has a sidewall surface that curve outwards with respect to an inner portion of the squeezed portion502. In some embodiments, a top surface of the squeezed portion502is higher than an interface between the insulating film132and the passivation layer125of the semiconductor die122. In some embodiments, the squeezed portion502is separated from the dielectric layer114by a distance. The squeezed portion502is not in direct contact with the dielectric layer114.

Afterwards, processes that are the same as or similar to those illustrated inFIGS.1G-1Jare performed to form a package structure, as shown inFIG.5Bin accordance with some embodiments. In some embodiments, the squeezed portion502of the insulating film132is separated from the dielectric layer114by a portion of the protective layer134.

Many variations and/or modifications can be made to embodiments of the disclosure.FIG.6is a cross-sectional view of a package structure, in accordance with some embodiments.FIG.6shows a structure similar to that illustrated inFIG.5B. In some embodiments, each of the connectors130includes the metal pillar302and the solder element304. The material and formation method of the metal pillar302may be the same as or similar to those of the conductive pillars120. The solder element304may include an alloy of tin and other metal materials. In some embodiments, the solder bumps is substantially free of lead.

Many variations and/or modifications can be made to embodiments of the disclosure.FIG.7is a cross-sectional view of a package structure, in accordance with some embodiments. In some embodiments, the squeezed portion502of the insulating film132not only extends beyond the edge of the semiconductor die122but also comes in contact with the dielectric layer114. That is, the squeezed portion502of the insulating film132is in direct contact with the dielectric layer114, in accordance with some embodiments.

In some embodiments, the squeezed portion502of the insulating film132is in direct contact with an edge of the dielectric layer114. In some embodiments, a portion of the protective layer134is between the squeezed portion502and the dielectric layer114even if the squeezed portion502is in direct contact with an edge of the dielectric layer114, as shown inFIG.7.

As shown inFIG.7, the insulating film132also includes a squeezed portion502′. In some embodiments, the squeezed portion502′ extends beyond an edge of the dielectric layer114. In some embodiments, the squeezed portion502′ partially covers a top surface of the dielectric layer114. In some embodiments, the squeezed portion502′ is in direct contact with the top surface and the edge of the dielectric layer114.

Embodiments of the disclosure form a package structure with stacked semiconductor dies. A thermal compression bonding process is used to bond an upper semiconductor die onto lower semiconductor dies. Due to the characteristics of the thermal compression bonding process, the upper semiconductor die is allowed to have a small thickness without raising the cold-joint issue. Therefore, a subsequently formed protective layer (such as a molding layer) used to surround the upper semiconductor die may also have a small thickness, which significantly reduce the warpage of the package structure. Before the thermal compression bonding process, a large opening partially exposes the lower semiconductor dies is formed in a dielectric layer on the lower semiconductor dies. The photolithography process for forming the large opening is easier to perform. No residue is left on conductive features of the lower semiconductor dies. The under-development issue may thus be prevented. Accordingly, the electrical connections between the upper semiconductor die and the lower semiconductor dies are improved. The quality and reliability of the package structure are greatly improved.

In accordance with some embodiments, a method for forming a package structure is provided. The method includes disposing a first semiconductor die over a carrier substrate and forming a first protective layer to surround the first semiconductor die. The method also includes forming a dielectric layer over the first protective layer and the first semiconductor die. The method further includes patterning the dielectric layer to form an opening partially exposing the first semiconductor die and the first protective layer. In addition, the method includes bonding a second semiconductor die to the first semiconductor die after the opening is formed. The method further includes forming a second protective layer to surround the second semiconductor die.

In accordance with some embodiments, a method for forming a package structure is provided. The method includes forming a first protective layer to surround a first semiconductor die and a second semiconductor die. The method also includes forming a dielectric layer to cover the first semiconductor die, the second semiconductor die, and the first protective layer. The method further includes forming an opening in the dielectric layer, and the opening partially exposes the first semiconductor die, the second semiconductor die, and the first protective layer. In addition, the method includes disposing a third semiconductor die to partially cover the first semiconductor die and the second semiconductor die after the opening is formed. The third semiconductor die forms electrical connections between the first semiconductor die and the second semiconductor die. The method further includes forming a second protective layer to surround the third semiconductor die.

In accordance with some embodiments, a package structure is provided. The package structure includes a lower semiconductor die and a first protective layer surrounding the lower semiconductor die. The package structure also includes a dielectric layer partially covering the first protective layer and the lower semiconductor die. The package structure further includes an upper semiconductor die over the lower semiconductor die and the first protective layer. The upper semiconductor die is bonded with the lower semiconductor die through a connector. In addition, the package structure includes an insulating film surrounding the connector and a second protective layer surrounding the upper semiconductor die.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.