Patent ID: 12188982

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

The present disclosure is more particularly described in the following examples that are intended as illustrative only since numerous modifications and variations therein will be apparent to those skilled in the art. Like numbers in the drawings indicate like components throughout the views. As used in the description herein and throughout the claims that follow, unless the context clearly dictates otherwise, the meaning of “a”, “an”, and “the” includes plural reference, and the meaning of “in” includes “in” and “on”. Titles or subtitles can be used herein for the convenience of a reader, which shall have no influence on the scope of the present disclosure.

The terms used herein generally have their ordinary meanings in the art. In the case of conflict, the present document, including any definitions given herein, will prevail. The same thing can be expressed in more than one way. Alternative language and synonyms can be used for any term(s) discussed herein, and no special significance is to be placed upon whether a term is elaborated or discussed herein. A recital of one or more synonyms does not exclude the use of other synonyms. The use of examples anywhere in this specification including examples of any terms is illustrative only, and in no way limits the scope and meaning of the present disclosure or of any exemplified term. Likewise, the present disclosure is not limited to various embodiments given herein. Numbering terms such as “first”, “second” or “third” can be used to describe various components, signals or the like, which are for distinguishing one component/signal from another one only, and are not intended to, nor should be construed to impose any substantive limitations on the components, signals or the like.

A test method for delay circuit and a test circuitry are provided in the present disclosure to solve the problem that an integrated circuit such as a double data rate synchronous dynamic random access memory (DDR SDRAM) cannot be tested at a practical high-speed operating frequency (e.g., 800 MHz, or DDR at GHz level) when using a conventional delay circuit (i.e., a delay chain circuit), and can only be tested at a lower operating frequency. One of the objectives of the test method is to perform an at-speed test on a circuit under test with the delay chain circuit, especially a high-speed test. It should be noted that the test may not be sufficient if only low-speed test is done by the delay circuit because some production defects on the integrated circuits can only be found at a high-speed test.

The test can include a scan test and a function test. The scan test includes a high-speed test and a low-speed test. The high-speed test can be interpreted as a test having a speed that approaches the operating frequency of a circuit under test such as a high-speed DDR memory. The test circuitry includes a delay chain circuit. Multiple delay cells in the delay chain circuit can be flip flops. The delay chain circuit decides delay series by phase control. The greater the delay series are, the delay cells required are more and the longer the delay is. The high-speed test may therefore not be tested completely. More particularly, the provided test method for delay circuit and the test circuitry are applied to a wafer-level test, which is the test performed before packaging.

Reference is made toFIG.3, which shows an example of a delay chain circuit that is applied to a high-speed circuit. In the present example, data303generated by a circuit under test32is transmitted to a flip flop31at an output end. The circuit under test32generates clock signals301that are transmitted to a delay chain circuit30. The delay chain circuit30decides delay series according to a delay phase control signal33generated by a delay control circuit. Afterwards, delayed clock signals307are generated. The flip flop31performs sampling according to the delayed clock signals307so as to generate sampled data305.

In an exemplary example, the circuit under test32is such as a DDR SDRAM. The circuit under test32includes multiple pins that include a data-selection pulse pin (DQS) pin. The DQS pin is used to accurately distinguish every cycle within a clock cycle and then output clock signals301periodically.

The clock signals301are then transmitted to the delay chain circuit30for controlling the clock signals301to be delayed. The delayed clock signals307are then outputted to the flip flop31. A data signal pin (DQ) is also provided. A read-write sequence of the DQ pin is synchronized with the clock signals generated by the data-selection pulse, and therefore the DQ pin outputs the data303that is synchronized with the clock signals. The flip flop31then samples the delayed clock signals307, and the sampled data305is obtained. The sampled data305can be used to test and ensure the quality of the circuit under test32.

It should be noted that the conventional test circuitry can only test the delay circuit in a lower frequency, and therefore the test may not be complete since the conventional test circuitry cannot test the circuit (e.g., the integrated circuit) under a practical operating frequency when too many delay series are configured on the delay chain circuit that is used to control the delay of the circuit under test. Accordingly, the test circuitry of the present disclosure used to control the delay incorporates some additional circuits such as a clock pulse generator and a counter. The test circuitry embodies a test mode that can test a high-frequency circuit through a switching circuit. Referring toFIG.2, the switching circuit can switch a line to the conventional delay chain circuit for the test circuitry to operate a function mode.

Reference is made toFIG.4, which is a schematic diagram depicting a test circuitry that performs the test method for a delay circuit. The test circuitry includes a delay circuit40. The delay circuit40provides a delay function by combining multiple serially connected logic gates. More specifically, a series of flip flops, D-type flip-flops (DFF), or NAND gates form the delay chain circuit. The D-type flip-flops turn the clock signals from a high level to a low level for outputting data inputted to a D-end of the flip flop via a Q-end of the flip flop. This process takes up certain amounts of time and therefore a delay effect is provided.

According to one embodiment of the test circuitry, a first switching circuit41is disposed at an input end of the delay circuit40. The first switching circuit41can be implemented by a selector or a multiplexer. The first switching circuit41switches the sources of the clock signals according to a control signal403(1 or 0) generated by a control circuit (not shown in the diagram). For example, the original function mode operated by the circuit under test is maintained if the control signal is 0; on the contrary, the test circuitry is under the test mode if the control signal is 1. Under the test mode, an external control circuit (not shown in the diagram) generates a delay phase control signal404for deciding delay series specified to the delay circuit40. The first switching circuit41switches an input circuit45that is originally used to input a first clock signal401to the delay circuit40to a newly-added clock pulse generator43. The clock pulse generator43is disposed at the input end of the delay circuit40, and is used to generate one or more cycles of clock signals that is called second clock signal402in this embodiment. The second clock signal402is characterized by having a frequency that is similar to or higher than the operating frequency of the circuit under test (not shown in the diagram). The second clock signal402configured to be inputted to the delay circuit40can be the clock pulses with two or more cycles. Under the test mode, the clock pulse generator43generates the second clock signals402for testing the delay circuit40. The second clock signals402are outputted to an output circuit via the delay circuit40. The output circuit includes one or more flip flops46. The number of the flip flops used in the output circuit is designed to be able to record the number of cycles of the second clock signals402generated by the clock pulse generator43. For example, the number of the flip flops can be two.

The output end of the delay circuit40includes a second switching circuit42. The second switching circuit42can be implemented by a selector or a multiplexer, in which one end of the second switching circuit42is connected with a counter44, and the other end of the second switching circuit42is used to receive practical test data47. The test data47is generated by the circuit under test. An output end of the second switching circuit42is connected with a flip flop46. Under the test mode, the second switching circuit42is synchronized with the first switching circuit41. The second switching circuit42switches the line to the counter44according to a control signal403, and the counter44is triggered by a clock signal so as to obtain a counting result from the one or more flip flops46.

Further, under the test mode, the one or more flip flops46receives delayed second clock signals402′ which are delayed by the delay circuit40. The number of the flip flops46of the output circuit is decided according to the number of pulse cycles of the second clock signals402. The delayed second clock signals402′ trigger the counter44disposed at the output end of the delay circuit40so as to start counting. The counter44counts the delayed second clock signals402′. Under the test mode, sampled data48outputted from the output circuit is the counting result. The counting result is compared with the number of the clock signals generated by the clock pulse generator43in the beginning, such that the quality of the delay circuit40can be tested.

The flip flop46in the output circuit can be a D-type flip-flop. The delay circuit40delays the second clock signals402with two or more cycles of pulse clock and then outputs the delayed second clock signals402′ to the certain number of the flip flops which are able to record the number of cycles of the second clock signals402. The counter44relies on values (0 or 1) of the flip flops to conduct the counting. The counting result can be recorded in the one or more flip flops. The counting result is compared with the number of cycles of the clock signals generated by the clock pulse generator43so as to test if any error occurred to the delay circuit40.

Reference is made toFIG.5, which is a flow chart describing a test method for a delay circuit that can be implemented by the delay chain circuit shown inFIG.4according to the present disclosure.

When the test circuitry operates under the test mode, the first switching circuit at the input end of the delay circuit switches the line to the newly-added clock pulse generator so as to generate multiple cycles of clock signals (step S501). Under the test mode, the second switching circuit at the output end of the delay circuit switches the line to the counter from an original line used to receive data (step S503). The delay control circuit of the test circuitry is used to adjust a delay phase to a maximum. Practically, the input signals, i.e., the clock signals, are inputted to all the delay cells of the delay circuit before being outputted (step S505). An initial state of the test circuitry is to keep a logic value of the clock pulse generator to be “0”, and a logic value of the flip flop at the output end is also kept to be “0”. An internal register can be used to keep a control signal that is used to control the first switching circuit and the second switching circuit to conduct line switching. The register can be disposed inside the delay control circuit. When the delay circuit is to be tested, a control signal is generated to enable the delay circuit to enter a test mode.

Afterwards, under the test mode, the clock pulse generator generates two or more clock signals, which is a type of pulse signal with a specific pulse width. The pulse width can be the same as a practical clock cycle of the circuit under test (step S507). The clock signals are inputted to the delay circuit, and transmitted to the output end of the delay circuit through all the delay cells of the delay circuit. The output circuit includes one or more flip flops. The number of the flip flops can be decided according to the number of the pulse signals to be transmitted at the input end (S509). The clock signal triggers the counter to operate and the counter counts the number of cycles of the clock signals (step S511). A counting result can be obtained in the output circuit. The counting result in the output circuit is compared with the number of cycles of the clock signals at the input end of the delay circuit so as to check if the counting result meets the number of cycles of the clock signals (step S513).

In an exemplary example, when the clock pulse generator generates two pulses, the pulses trigger a counter to start counting and a counting result is 2. At the same time, an output value of the output circuit is also 2. Accordingly, the delay circuit is determined to have no defect. The output circuit is such as a flip flop that can be a negative edge triggered D-type flip-flop. The delay circuit can be determined to have any defect or not by checking whether or not the output of the D-type flip-flop is 2 by using the abovementioned method. Therefore, a built-in self-test is embodied in the circuit under test if the circuit passes the test.

In summation, in a design for testability of an integrated circuit, a test circuitry is implanted in the integrated circuit at a design stage such that a self-testing can be performed after production. The self-test can be used to ensure that the electronic element has no defect in its function or in the manufacturing process. In the test method for delay circuit and the test circuitry according to the present disclosure, the circuits such as a clock pulse generator and a counter are added in the test circuitry for implementing a test mode. A high-speed test for the delay circuit can be completed under the test mode. Therefore, test completeness of the subsequent circuit under test can be improved. The circuit under test such as a wafer-level circuit can be processed with a chip probing (CP) test before a packaging process for implementing a complete test in order to ensure the quality of the circuit made in mass production.

The foregoing description of the exemplary embodiments of the disclosure has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching.

The embodiments were chosen and described in order to explain the principles of the disclosure and their practical application so as to enable others skilled in the art to utilize the disclosure and various embodiments and with various modifications as are suited to the particular use contemplated. Alternative embodiments will become apparent to those skilled in the art to which the present disclosure pertains without departing from its spirit and scope.