Patent ID: 12250826

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

A magnetic tunnel junction (MTJ) includes first and second ferromagnetic films separated by a tunnel barrier layer. One of the ferromagnetic films (e.g., referred to as a “reference layer”) has a fixed magnetization direction, while the other ferromagnetic film (e.g., referred to as a “free layer”) has a variable magnetization direction. For MTJs with positive tunneling magnetoresistance (TMR), if the magnetization directions of the reference layer and free layer are in a parallel orientation, it is more likely that electrons will tunnel through the tunnel barrier layer, such that the MTJ is in a low-resistance state. Conversely, if the magnetization directions of the reference layer and free layer are in an anti-parallel orientation, it is less likely that electrons will tunnel through the tunnel barrier layer, such that the MTJ is in a high-resistance state. Consequently, the MTJ can be switched between two states of electrical resistance, a first state with a low resistance (RP: magnetization directions of reference layer and free layer are parallel) and a second state with a high resistance (RAP: magnetization directions of reference layer and free layer are anti-parallel). It is noted that MTJs can also have a negative TMR, e.g., lower resistance for anti-parallel orientation and higher resistance for parallel orientation.

Because of their binary nature, MTJs are used in memory cells to store digital data, with the low resistance state RP corresponding to a first data state (e.g., logical “0”), and the high-resistance state RAP corresponding to a second data state (e.g., logical “1”). For example, plural MRAM cells are arrayed in a chip, and each MRAM cell makes use of an MTJ to store a data state. However, when the chip comes under the presence of an external magnetic field, the chip may experience external turbulent of the external magnetic field, which may undesirably “flip” the data states stored in the MRAM cells, leading to data retention problems. External magnetic field could cause the operation window shift or storage data error, hence resulting in device reading or writing failure. Also, magnetic field may be generated by the MRAM cells may cause in-cell magnetic cross talk. For example, currents through one of the MRAM cells may generate magnetic field, which may undesirably “flip” the data states stored adjacent one of the MRAM cells.

In some embodiments of the present disclosure, to mitigate the adverse effects of external turbulent and in-cell magnetic cross talk, magnetic shielding elements are respectively inserted to spacers surrounding the MTJs. The magnetically-shielded zone, which lies within the magnetic shielding elements, has a first magnetic field magnitude that is less than a second magnetic field magnitude immediately outside of an outermost surface of the magnetic shielding elements. Thus, the magnetic shielding elements reduces the magnetic field experienced by the MRAM cells, thereby helping to improve data retention within the MRAM cells.

A magnetic random-access memory (MRAM) device and the method of forming the same are provided in accordance with various exemplary embodiments. The intermediate stages of forming the MRAM device are illustrated. The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

FIG.1Ais a schematic view of an integrated circuit device100having memory cells in accordance with some embodiments of the present disclosure. Magnetic shielding elements192are respectively disposed to surrounding memory cells MC, thereby shielding the memory cells MC and mitigating the adverse effects of external turbulent and in-cell magnetic cross talk.

FIG.1Bis a schematic cross-sectional view of the integrated circuit device100ofFIG.1A. The memory cells MC are arrayed and disposed between a metallization layer Mxover vias Vxand a metallization layer Mx+1above the metallization layer Mx. Each of the memory cells MC may include a bottom electrode142, a resistance switching element152over the bottom electrode142, a top electrode162over the resistance switching element152. The magnetic shielding elements192may be conductive, and designed not to establish an electrical connection between the metallization layer Mx, and the metallization layer Mx+1. For example, suitable elements may be used to space the magnetic shielding elements192apart from the memory cells MC, the metallization layer Mx, and the metallization layer Mx+1. For example, herein, the spacers182are used to space the magnetic shielding elements192apart from the resistance switching element152and the top electrode162of the memory cells MC. In some embodiments, ILD layers, identified as ILDxand ILDx+1, respectively surrounds the metallization layer Mxand the metallization layer Mx+1.

Through the configuration of the magnetic shielding elements192, the magnetic field flux/lines, which may result from the external turbulent and in-cell magnetic cross talk, may be directed to pass through the magnetic shielding elements192. Few or no magnetic field flux/lines pass through memory cells MC. Therefore, the configuration of the magnetic shielding elements192reduces the magnetic field experienced by the memory cells MC, thereby helping to improve data retention within the memory cells MC.

In some embodiments, for effectively shielding the memory cells MC from magnetic field, a thickness of the magnetic shielding elements192may be in a range from about 10 nanometers to about 200 nanometers. If the thickness of the magnetic shielding elements192is less than about 10 nanometers, the magnetic shielding elements192may not effectively shield memory cells from magnetic field. If the thickness of the magnetic shielding elements192is greater than about 200 nanometers, the difficulty of fabrication process of the device may increase.

In some embodiments, for effectively shielding the memory cells MC from magnetic field, a distance between the magnetic shielding elements192and the resistance switching element152of the memory cells MC (e.g., the thickness of the spacer182) may be in a range from about 50 angstroms to about 100 angstroms. If the distance between the magnetic shielding elements192and the memory cells MC (e.g., the thickness of the spacer182) is less than about 50 angstroms, due to process limitation, it may be hard to control the distance (e.g., the thickness of the spacer182) to effectively electrically isolate the magnetic shielding elements192from the memory cells MC. If the distance between the magnetic shielding elements192and the memory cells MC is greater than about 100 angstroms, the magnetic shielding elements192may not effectively shield memory cells from external turbulent and in-cell magnetic cross talk.

In the present embodiments, the memory cells MC are electrically connected to the metallization layer Mxthrough BEVAs130. In some other embodiments, the memory cells MC may be directly connected to the metallization layer Mxwithout the BEVAs130disposed therebetween. The memory cells MC may be fabricated by various process, and does not necessarily include the structure shown in embodiments of the present disclosure.

FIGS.2through13are cross-sectional views of an integrated circuit device in various stages of fabrication in accordance with some embodiments of the present disclosure. The illustration is merely exemplary and is not intended to limit beyond what is specifically recited in the claims that follow. It is understood that additional operations may be provided before, during, and after the operations shown byFIGS.2-14, and some of the operations described below can be replaced or eliminated for additional embodiments of the method. The order of the operations/processes may be interchangeable.

FIG.2illustrates a wafer having a substrate having an interconnect layer110thereon. The interconnect layer110includes an interlayer dielectric (ILD) layer or inter-metal dielectric (IMD) layer112with metallization pattern114therein. The ILD layer112may be an extra low-k dielectric (ELK) layer, such as carbon doped silicon dioxide, may be an oxide, such as silicon oxide, and/or may be the like or a combination thereof. In some embodiments, the ILD layer112may be formed of a low-k dielectric material having a k value less than about 3.9. The k value of the ILD layer112may even be lower than about 2.8. The metallization pattern114may be copper, aluminum, the like, and/or a combination thereof. For example, the metallization pattern114includes a conductive via114aand a conductive line/pad114bover the conductive via114ain the present embodiments. The substrate may also include active and passive devices, for example, underlying the interconnect layer110. These further components are omitted from the figures for clarity, and how these components are formed will be readily apparent to a person having ordinary skill in the art.

A dielectric layer120is formed over the interconnect layer110. The dielectric layer120in some embodiments is silicon carbide (SiC), silicon oxynitride (SiON), silicon nitride (SiN), silicon dioxide, the like, and/or combinations thereof. The dielectric layer120may be a single-layered structure or a multi-layered structure. For example, herein, the dielectric layer120includes a silicon carbide layer122and a silicon-rich oxide (SRO) layer124over the silicon carbide layer122. The dielectric layer120may be formed by acceptable deposition techniques, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), the like, and/or a combination thereof.

Reference is made toFIG.3. Plural via openings1200are etched in the dielectric layer120to expose the conductive line/pad114bof the metallization pattern114. In some embodiments, the metallization pattern114may have a higher etch resistance to the etch process, such that the metallization pattern114remains substantially intact after the second etching process.

Reference is made toFIG.4. Bottom electrode vias (BEVA)130are then formed in the via opening1200in the dielectric layer120. In the present embodiments, the via openings1200in the dielectric layer120are overfilled with a fill metal, and then a planarization process, such as a chemical-mechanical polish (CMP) process, is performed to remove excess materials of the fill metal outside the via openings1200in the dielectric layer120. The remaining fill metal in the via openings1200in the dielectric layer120can serve as the BEVAs130. In some embodiments, the BEVAs130are electrically connected to an underlying electrical component, such as a transistor, through the metallization pattern114.

In some embodiments, at least one of the BEVAs130is a multi-layered structure and includes, for example, a diffusion barrier layer and a filling metal filling a recess in the diffusion barrier layer. In some embodiments, the diffusion barrier layer is a titanium nitride (TiN) layer or a tantalum nitride (TaN) layer, which can act as a suitable barrier to prevent metal diffusion. Formation of the diffusion barrier layer may be exemplarily performed using CVD, PVD, ALD, the like, and/or a combination thereof. In some embodiments, the filling metal is titanium (Ti), tantalum (Ta), platinum (Pt), ruthenium (Ru), tungsten (W), aluminum (Al), copper (Cu), TiN, TaN, the like, and/or combinations thereof. Formation of the filling metal may be exemplarily performed using CVD, PVD, ALD, the like, and/or a combination thereof.

A blanket bottom electrode layer140is then formed over the BEVAs130and over the dielectric layer120, so that the bottom electrode layer140extends along top surfaces of the BEVAs130and of the dielectric layer120. In some embodiments, the bottom electrode layer140may include titanium (Ti), tantalum (Ta), platinum (Pt), ruthenium (Ru), tungsten (W), aluminum (Al), copper (Cu), TiN, TaN, the like, and/or a combination thereof. The bottom electrode layer140can be a single-layered structure or a multi-layered structure. For example, the bottom electrode layer140may include a TaN layer and a TiN layer over the TaN layer. Formation of the bottom electrode layer140may be exemplarily performed using CVD, PVD, ALD, the like, and/or a combination thereof.

In the present embodiments, the bottom electrode layer140is electrically connected to the metallization pattern114through the BEVAs130. In some other embodiments, the BEVAs130may be omitted, and the bottom electrode layer140may be deposited (for example, into the via openings1200in the dielectric layer120) to be in direct contact with the metallization pattern114.

Reference is made toFIG.5. A resistance switching layer150, a top electrode layer160, and a metal-containing mask layer170are formed over the bottom electrode layer140in a sequence.

In some embodiments, the resistance switching layer150may be a magnetic tunnel junction (MTJ) structure. To be specific, the resistance switching layer150includes at least a first magnetic layer, a tunnel barrier layer and a second magnetic layer formed in sequence over the bottom electrode layer140.

In some embodiments, the first magnetic layer includes an anti-ferromagnetic material (AFM) layer over the bottom electrode layer140and a ferromagnetic pinned layer over the AFM layer. In the AFM layer, magnetic moments of atoms (or molecules) align in a regular pattern with magnetic moments of neighboring atoms (or molecules) in opposite directions. A net magnetic moment of the AFM layer is zero. In certain embodiments, the AFM layer includes platinum manganese (PtMn). In some embodiments, the AFM layer includes iridium manganese (IrMn), rhodium manganese (RhMn), iron manganese (FeMn), or OsMn. An exemplary formation method of the AFM layer includes sputtering, PVD, ALD, e-beam or thermal evaporation, or the like.

The ferromagnetic pinned layer in the first magnetic layer forms a permanent magnet and exhibits strong interactions with magnets. A direction of a magnetic moment of the ferromagnetic pinned layer can be pinned by the AFM layer and is not changed during operation of a resulting resistance switching element (e.g. a MTJ stack) fabricated from the resistance switching layer150. In certain embodiments, the ferromagnetic pinned layer includes cobalt-iron-boron (CoFeB). In some embodiments, the ferromagnetic pinned layer includes CoFeTa, NiFe, Co, CoFe, CoPt, or the alloy of Ni, Co and Fe. An exemplary formation method of the ferromagnetic pinned layer includes sputtering, PVD, ALD, e-beam or thermal evaporation, or the like. In some embodiments, the ferromagnetic pinned layer includes a multilayer structure.

The tunnel barrier layer is formed over the first magnetic layer. The tunnel barrier layer can also be referred to as a tunneling layer, which is thin enough that electrons are able to tunnel through the tunnel barrier layer when a biasing voltage is applied to a resulting resistance switching element (e.g. a MTJ stack) fabricated from the resistance switching layer150. In certain embodiments, the tunnel barrier layer includes magnesium oxide (MgO), aluminum oxide (Al2O3), aluminum nitride (AlN), aluminum oxynitride (AlON), hafnium oxide (HfO2) or zirconium oxide (ZrO2). An exemplary formation method of the tunnel barrier layer includes sputtering, PVD, ALD, e-beam or thermal evaporation, or the like.

The second magnetic layer is formed over the tunnel barrier layer. The second magnetic layer is a ferromagnetic free layer in some embodiments. A direction of a magnetic moment of the second magnetic layer is not pinned because there is no anti-ferromagnetic material in the second magnetic layer. Therefore, the magnetic orientation of this layer is adjustable, thus the layer is referred to as a free layer. In some embodiments, the direction of the magnetic moment of the second magnetic layer is free to rotate parallel or anti-parallel to the pinned direction of the magnetic moment of the ferromagnetic pinned layer in the first magnetic layer. The second magnetic layer may include a ferromagnetic material similar to the material in the ferromagnetic pinned layer in the first magnetic layer. Since the second magnetic layer has no anti-ferromagnetic material while the first magnetic layer has an anti-ferromagnetic material therein, the first and second magnetic layers and have different materials. In certain embodiments, the second magnetic layer includes cobalt, nickel, iron or boron. An exemplary formation method of the second magnetic layer includes sputtering, PVD, ALD, e-beam or thermal evaporation, or the like.

A top electrode layer160is formed over the resistance switching layer150. The top electrode layer160includes a conductive material. In some embodiments, the top electrode layer160may include a metal, such as tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), ruthenium (Ru), aluminum (Al), copper (Cu), the like or combinations thereof. An exemplary formation method of the top electrode layer160includes sputtering, PVD, or the like. In some embodiments, prior to the formation of the top electrode layer160, a capping layer (not shown) is formed over the resistance switching layer150. The capping layer may be a thin metal layer that protects the resistance switching layer150from oxidation during fabrication process. The capping layer may be deposited by PVD, ALD, e-beam or thermal evaporation, or the like.

A metal-containing mask layer170is formed over the top electrode layer160in sequence. In some embodiments, the metal-containing mask layer170is formed from a metal material or a metal-containing compound material. For example, the metal-containing mask layer170may include a metal (e.g., Ta), a metal nitride (e.g., titanium nitride (TiN)), the like, and/or combinations thereof. The metal-containing mask layer170may be formed by acceptable deposition techniques, such as CVD, ALD, PVD, the like, and/or combinations thereof.

Reference is made toFIG.6. The metal-containing mask layer170, the top electrode layer160, and the resistance switching layer150(referring toFIG.5) are patterned into memory stacks MS. After the patterning process, each of the memory stacks MS may include a resistance switching element152, a top electrode162over the resistance switching element152, and a metal-containing mask172over the top electrode162.

In some embodiments, a patterned mask (not shown) is formed over the metal-containing mask layer170(referring toFIG.5), and then one or more etching processes are performed to etch the metal-containing mask layer170, the top electrode layer160, and the resistance switching layer150(referring toFIG.5) through the patterned mask, thereby achieving the patterning process. The patterned mask may be a photoresist formed by photolithography patterning processes, including photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), and/or other applicable processes. In some embodiments, the patterned mask may include a hard mask below the photoresist for protecting the underlying layers against subsequent etching process. The hard mask may include Si3N4and/or silicon oxynitride.

In some embodiments, the metal-containing mask layer170and the top electrode layer160(referring toFIG.5) are patterned into the metal-containing masks172and the top electrodes162by a first etching process through the patterned mask (not shown), and the resistance switching layer150is patterned into the resistance switching elements152by a second etching process. In some embodiments, the first and second etching processes are dry etching processes using suitable etchants.

In some embodiments, the first etching process may be a dry etch using fluoride-based etchants, such as CF4. For example, the dry etch may etch and remove portions of the metal-containing mask layer170and the top electrode layer160(referring toFIG.5) exposed by the patterned mask (not shown), while other portions of the metal-containing mask layer170and the top electrode layer160(referring toFIG.5) covered by the patterned mask (not shown) are protected from being etched during the dry etch.

In some embodiments, the second etching process may be a dry etch that employs pure chemical etching process (e.g., plasma etching) or dry etching techniques that employs both physical and chemical etching techniques (e.g., RIE). Gases, such as CH3OH, CO, NH3may be used during the second etching process. The metal-containing masks172and the top electrodes162may have a higher etch resistance to the second etching process than that of the resistance switching layer150(referring toFIG.5), such that the metal-containing masks172and the top electrodes162may serve as a etch mask during the second etching process. In some embodiments, the bottom electrode layer140has a higher etch resistance to the second etching process than that of the resistance switching layer150(referring toFIG.5), such that the bottom electrode layer140remain substantially intact after the second etching process. For example, the bottom electrode layer140remains covering the dielectric layer120.

Reference is made toFIG.7. A first spacer layer180, a magnetic shielding layer190, and a second spacer layer200are conformally deposited over the structure ofFIG.6in a sequence.

The first spacer layer180may be made of non-magnetic material. The first spacer layer180, in some embodiments may include SiN, but in other embodiments may include SiC, SiON, silicon oxycarbide (SiOC), the like, and/or combinations thereof. The first spacer layer180may be formed using CVD, PVD, ALD, the like, and/or combinations thereof.

The magnetic shielding layer190may be metal or insulator with magnetic properties, such as high permeability/susceptibility, soft ferromagnetic, low magnetic anisotropy/magnetostriction, and/or low or no hysteresis loop. The magnetic shielding layer190may include soft-magnetic materials. For example, the magnetic shielding layer190may include Co, Fe, Ni, the like, the alloy thereof and/or combinations thereof, and the magnetic shielding layer190can be doped with copper, silicon, carbon, or molybdenum (Mo). For example, the magnetic shielding layer190may include a Mu-metal, which is an alloy of Nickel-Iron (NiFe) doped with copper, silicon, or molybdenum. In some embodiments wherein the magnetic shielding layer190is made of NixFe(100−x), x is in a range from about 50 to about 100. In some embodiments wherein the magnetic shielding layer190is made of CoxNi(100−x), x is in a range from about 50 to about 100. In some embodiments wherein the magnetic shielding layer190is made of CoxFe(100−x), x is in a range from about 50 to about 100. If x is less than about 50, the magnetic shielding layer190may have a low ability to effectively shield memory cells from magnetic field, such that a thickness of the magnetic shielding layer190is required to be increased, which may increase the difficulty of fabrication process. The magnetic shielding layer190may be formed using CVD, PVD, ALD, the like, and/or combinations thereof. In some embodiments, the magnetic shielding layer190may be conductive.

The second spacer layer200may be made of non-magnetic material. The second spacer layer200, in some embodiments may include SiN, but in other embodiments may include SiC, SiON, silicon oxycarbide (SiOC), the like, and/or combinations thereof. The second spacer layer200may be formed using CVD, PVD, ALD, the like, and/or combinations thereof.

Reference is made toFIG.8. The second spacer layer200may be patterned into second spacers202by a suitable etching process. The etching process may be anisotropic dry etching process, using gas etchants such as CH2F2, CF4, CHxFy, CHF3, CH4, N2, O2, Ar, He, or the like. The etching process removes horizontal portions of the second spacer layer200(referring toFIG.7), and leaving vertical portions of the second spacer layer200(referring toFIG.7) on sidewalls of the memory stacks MS. The remaining vertical portions of the second spacer layer200(referring toFIG.7) may be referred to as the second spacers202hereinafter. In some embodiments, the second spacers202respectively enclose the memory stacks MS. The second spacers202may include multiple layers in some embodiments. In some embodiments, the magnetic shielding layer190may have a higher etch resistance to the etching process than that of the second spacers202, such that the etching process to the second spacer layer200(referring toFIG.7) may stop at the top surface of the magnetic shielding layer190. After the etching process, portions of the magnetic shielding layer190are exposed by the second spacers202.

Reference is made toFIG.9. The magnetic shielding layer190and the first spacer layer180(referring toFIG.8) are patterned into magnetic shielding element192and first spacers182. The patterning process may include a first etching process to the magnetic shielding layer190(referring toFIG.8) and a second etching process to the first spacer layer180(referring toFIG.8).

The first etching process is performed to remove horizontal portions of the magnetic shielding layer190(referring toFIG.8) exposed by the second spacers202. The first etching process may be anisotropic dry etching process, using gas etchants capable of etching metals (e.g., Co). For example, the first etching process may use chlorine-based gas. The second spacers202may have a higher etch resistance to the first etching process than that of the magnetic shielding layer190(referring toFIG.8), thereby may serve as an etch mask that protecting portions of the magnetic shielding layer190from being etched. The first spacer layer180(referring toFIG.8) may also have a higher etch resistance to the first etching process than that of the magnetic shielding layer190(referring toFIG.8), such that the first etching process may stop when the first spacer layer180(referring toFIG.8) is exposed. The remaining portions of the magnetic shielding layer190(referring toFIG.8) may be referred to as the magnetic shielding elements192hereinafter. In some embodiments, the magnetic shielding elements192respectively enclose the memory stacks MS. The magnetic shielding elements192may include multiple layers in some embodiments.

The second etching process may be anisotropic dry etching process, using gas etchants different from that of first etching process. For example, the second etching process may use fluorine-based gas, such as such as CH2F2, CF4, CHxFy, CHF3, or the like. The second etching process removes horizontal portions of the first spacer layer180(referring toFIG.8), and leaving second spacers202and vertical portions of the first spacer layer180(referring toFIG.8) on sidewalls of the memory stacks MS. The remaining vertical portions of the first spacer layer180(referring toFIG.8) may be referred to as the first spacers182hereinafter. In some embodiments, the first spacers182respectively enclose the memory stacks MS. The first spacers182may include multiple layers in some embodiments. In some embodiments, the bottom electrode layer140and the metal-containing masks172may have a higher etch resistance to the second etching process than that of the first spacers182, such that the second etching process to the first spacer layer180(referring toFIG.8) may stop at the top surface of the bottom electrode layer140and the metal-containing masks172. After the etching process, top surfaces of the metal-containing masks172and portions of the bottom electrode layer140are exposed by the first spacers182.

Reference is made toFIG.10. A third spacer layer210is deposited over the structure ofFIG.9. The third spacer layer210may be made of non-magnetic material. The third spacer layer210, in some embodiments may include SiN, but in other embodiments may include SiC, SiON, silicon oxycarbide (SiOC), the like, and/or combinations thereof. For example, herein, the third spacer layer210may include a silicon nitride layer210aand a silicon oxide layer210bover the silicon nitride layer210a. The third spacer layer210may be formed using CVD, PVD, ALD, the like, and/or combinations thereof.

Reference is made toFIG.11. The third spacer layer210may be patterned into third spacers212by a suitable etching process. The etching process may be anisotropic dry etching process, using gas etchants such as CH2F2, CF4, CHxFy, CHF3, CH4, N2, O2, Ar, He, or the like. The etching process removes horizontal portions of the third spacer layer210(referring toFIG.10), and leaving vertical portions of the third spacer layer210(referring toFIG.10) on sidewalls of the memory stacks MS. The remaining vertical portions of the third spacer layer210(referring toFIG.10) may be referred to as the third spacer212hereinafter. In some embodiments, the third spacer212respectively enclose the memory stacks MS. The third spacer212may include multiple layers in some embodiments. In some embodiments, the bottom electrode layer140and the metal-containing masks172may have a higher etch resistance to the etching process than that of the third spacer212, such that the etching process to the third spacer layer210(referring toFIG.10) may stop at top surface of the bottom electrode layer140and the metal-containing masks172. In some embodiments, a top of the third spacer212is higher than tops of the first spacers182, the magnetic shielding elements192, and the second spacers202. The silicon oxide layer210bmay be consumed by the etching process. After the etching process, portions of the bottom electrode layer140are exposed by the third spacer212.

Reference is made toFIG.12. The bottom electrode layer140(referring toFIG.11) is patterned into bottom electrodes142by suitable etching process. The bottom electrodes142are in contact with the BEVAs130. The bottom electrode layer140(referring toFIG.11) can be patterned using the third spacer212as an etch mask, and hence the bottom electrode layer140(referring toFIG.11) can be patterned in a self-aligned manner. In some embodiments, the patterning process may include one or more etching operations, such as dry etching, wet etching or a combination thereof. In some embodiments, the patterning process may include a dry etching using chlorine based, fluorine based, or oxygen containing gaseous etchant such as CO, O2, CO2, CF4, CH2F2, C4F8, NF3, SF6, Cl2, BCl3and/or other chemicals, as example. In some embodiments, the third spacers212have a higher etch resistance to the etching process than that of the bottom electrodes142, such that the resistance switching element152may be protected from being etched during the patterning the bottom electrode layer140(referring toFIG.11). In some embodiments, the metal-containing masks172may be consumed by the etching process. In some embodiments, a combination of the bottom electrodes142and the memory stacks MS may be referred to as a memory cell MC, such as MRAM cell.

Reference is made toFIG.13. An ILD layer220is formed over the structure ofFIG.12. In some embodiments, the ILD layer220includes silicon oxide, fluorinated silica glass (FSG), carbon doped silicon oxide, tetra-ethyl-ortho-silicate (TEOS) oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), Black Diamond® (Applied Materials of Santa Clara, Calif.), amorphous fluorinated carbon, low-k dielectric material, the like or combinations thereof. The material of ILD layer220may be the same as or different from the ILD layer112.

A metallization pattern230is then formed in the ILD layer220. In the present embodiments, the metallization pattern230include conductive lines connected to the top electrodes162, and does not include a conductive via intervened between conductive lines and the top electrodes162. In some other embodiments, the metallization pattern230may include conductive vias, conductive lines, or the combination thereof. Formation of the metallization pattern230may be formed by etching openings and/or trenches in the ILD layer220, and then filling one or more metals (e.g., copper) in the openings and/or trenches to form the metallization pattern260. In some embodiments where the ILD layer220is silicon oxide, the etchant used in etching the openings and/or trenches can be dilute hydrofluoric acid (HF), HF vapor, CF4, C4F8, CHxFy, CxFy, SF6, or NF3, Ar, N2, O2, Ne, gas. In some embodiments, the top electrodes162may has a higher etch resistance to the etching the openings and trenches than that of the ILD layer220, such that the etching the openings may stop at the top electrodes162and not damage the underlying layers. After the openings and trenches are filled with metals, a planarization is performed to remove an excess portion of the metals outside the openings, and therefore the metallization pattern230is formed.

Through the processes, the magnetic shielding elements192and the first to third spacers182,202,212are formed around the memory cell MC, in which the magnetic shielding elements192may be located between the first and second spacers182and202. In present embodiments, the first spacers182spaces the magnetic shielding elements192apart from the top electrodes162, the resistance switching element152, and the bottom electrode layer142. In present embodiments, the second spacers202serve as etch masks during patterning the magnetic shielding layer190(referring toFIGS.8-9). In present embodiments, the third spacers212serve as etch masks during patterning the bottom electrode layer140(referring toFIGS.11-12) and space the magnetic shielding elements192apart from the metallization pattern230. The third spacers212may be over a top surface of the bottom electrode142. In present embodiments, tops of the magnetic shielding elements192are lower than top surfaces of the top electrodes162, and higher than top surfaces of the resistance switching element152. In present embodiments, bottoms of the magnetic shielding elements192are higher than top surfaces of the bottom electrodes142.

In some embodiments, the top electrode162and the resistance switching element152are over a portion142aof the bottom electrode142, the magnetic shielding element192is over a portion142cof the bottom electrode142. The magnetic shielding element192may have a portion192aextending along a sidewall of the resistance switching element152and a portion192bextending along a top surface of the second portion142cof the bottom electrode142. The first spacer182may space the portion192bof the magnetic shielding element192apart from the top surface of the portion142cof the bottom electrode142, and space the portion192aof the magnetic shielding element192apart from the sidewall of the resistance switching element152. The second spacer202may be over the portion192bof the magnetic shielding element192, and a top of the magnetic shielding element192is free of coverage of the second spacer202. The third spacer212may be over a portion142bof the bottom electrode142, the third spacer212may cover the top of the magnetic shielding element192, and the portion142cof the bottom electrode142is between the portions142aand142bof the bottom electrode142.

Through the configuration, the magnetic shielding elements192is free of being contacting with the bottom electrodes142, the top electrodes162, and the metallization pattern230. Therefore, the magnetic shielding elements192are preventing from establishing an electrical connection between the bottom electrodes142and the top electrodes162or an electrical connection between the bottom electrodes142and the metallization pattern230.

FIGS.14through21are cross-sectional views of an integrated circuit device in various stages of fabrication in accordance with some embodiments of the present disclosure. The illustration is merely exemplary and is not intended to limit beyond what is specifically recited in the claims that follow. It is understood that additional operations may be provided before, during, and after the operations shown byFIGS.2-14, and some of the operations described below can be replaced or eliminated for additional embodiments of the method. The order of the operations/processes may be interchangeable.

FIG.14shows a first spacer layer180is deposited over the structure ofFIG.6in a sequence. The first spacer layer180may be made of non-magnetic material. The first spacer layer180, in some embodiments may include SiN, but in other embodiments may include SIC, SiON, silicon oxycarbide (SiOC), the like, and/or combinations thereof. The first spacer layer180may be formed using CVD, PVD, ALD, the like, and/or combinations thereof. The first spacer layer180include a in-situ spacer layer180aand an ex-situ spacer layer180b, in which the in-situ spacer layer180ais formed just after the formation of the memory stack MS, for example, with the chamber that patterning the resistance switching layer150(referring toFIG.5) during the formation of the memory stack MS.

Reference is made toFIG.15. The first spacer layer180may be patterned into e first spacers182by a suitable etching process. The etching process may be anisotropic dry etching process, using gas etchants such as CH2F2, CF4, CHxFy, CHF3, CH4, N2, O2, Ar, He, or the like. The etching process removes horizontal portions of the first spacer layer180(referring toFIG.14), and leaving vertical portions of the first spacer layer180(referring toFIG.14) on sidewalls of the memory stacks MS. The remaining vertical portions of the first spacer layer180(referring toFIG.14) may be referred to as the first spacers182hereinafter. In some embodiments, the first spacers182respectively enclose the memory stacks MS. The first spacers182may include multiple layers in some embodiments. In some embodiments, the bottom electrode layer140and the metal-containing masks172may have a higher etch resistance to the second etching process than that of the first spacers182, such that the etching process to the first spacer layer180(referring toFIG.14) may stop at the top surface of the bottom electrode layer140and the metal-containing masks172. After the etching process, portions of the bottom electrode layer140are exposed by the first spacers182.

Reference is made toFIG.16. A magnetic shielding layer190is deposited over the structure ofFIG.15. The magnetic shielding layer190may include Co, Fe, Ni, the like, the alloy thereof and/or combinations thereof, and the magnetic shielding layer190can be doped with copper, silicon, carbon, or molybdenum (Mo). For example, the magnetic shielding layer190may include a Mu-metal, which is an alloy of Nickel-Iron (NiFe) doped with copper, silicon, or molybdenum. In some embodiments wherein the magnetic shielding layer190is made of NixFe(100−x), x is in a range from about 50 to about 100. In some embodiments wherein the magnetic shielding layer190is made of CoxNi(100−x), x is in a range from about 50 to about 100. In some embodiments wherein the magnetic shielding layer190is made of CoxFe(100−x), x is in a range from about 50 to about 100. If x is less than about 50, the magnetic shielding layer190may have a low ability to effectively shield magnetic field, such that a thickness of the magnetic shielding layer190is required to be increased, which may increase the difficulty of fabrication process. The magnetic shielding layer190may be formed using CVD, PVD, ALD, the like, and/or combinations thereof.

Reference is made toFIG.17. A second spacer layer200is deposited over the structure ofFIG.16. The second spacer layer200may be made of non-magnetic material. The second spacer layer200, in some embodiments may include SiN, but in other embodiments may include SiC, SiON, silicon oxycarbide (SiOC), the like, and/or combinations thereof. For example, herein, the second spacer layer200may include a silicon nitride layer200aand a silicon oxide layer200bover the silicon nitride layer200a. The second spacer layer200may be formed using CVD, PVD, ALD, the like, and/or combinations thereof.

Reference is made toFIG.18. The second spacer layer200may be patterned into second spacers202by a suitable etching process. The etching process may be anisotropic dry etching process, using gas etchants such as CH2F2, CF4, CHxFy, CHF3, CH4, N2, O2, Ar, He, or the like. The etching process removes horizontal portions of the second spacer layer200(referring toFIG.17), and leaving vertical portions of the second spacer layer200(referring toFIG.17) on sidewalls of the memory stacks MS. The remaining vertical portions of the second spacer layer200(referring toFIG.17) may be referred to as the second spacers202hereinafter. In some embodiments, the second spacers202respectively enclose the memory stacks MS. In some embodiments, the silicon oxide layer200binFIG.17may be fully consumed during the etching process, such that the second spacers202are formed from the silicon nitride layer200a. The second spacers202may include multiple layers in some embodiments. In some embodiments, the magnetic shielding layer190may have a higher etch resistance to the etching process than that of the second spacers202, such that the etching process to the second spacer layer200(referring toFIG.17) may stop at the top surface of the magnetic shielding layer190. The silicon oxide layer200bmay be consumed by the etching process. After the etching process, portions of the magnetic shielding layer190are exposed by the second spacers202.

Reference is made toFIG.19. The magnetic shielding layer190and the bottom electrode layer140(referring toFIG.18) are respectively patterned into magnetic shielding elements192and bottom electrodes142by suitable etching process. The bottom electrodes142are in contact with the BEVAs130. The magnetic shielding layer190and the bottom electrode layer140(referring toFIG.18) can be patterned using the second spacer202as an etch mask, and hence the magnetic shielding layer190and the bottom electrode layer140(referring toFIG.18) can be patterned in a self-aligned manner. In some embodiments, the patterning process may include one or more etching operations, such as dry etching, wet etching or a combination thereof. In some embodiments, the patterning process may include a dry etching using chlorine based, fluorine based, or oxygen containing gaseous etchant such as CO, O2, CO2, CF4, CH2F2, C4F8, NF3, SF6, Cl2, BCl3and/or other chemicals, as example. In some embodiments, the second spacer202have a higher etch resistance to the etching process than that of the magnetic shielding elements192and the bottom electrodes142, such that the resistance switching element152may be protected from being etched during the patterning the magnetic shielding layer190and the bottom electrode layer140(referring toFIG.18). In some embodiments, the metal-containing masks172may be consumed by the etching process. In some embodiments, a combination of the bottom electrodes142and the memory stacks MS may be referred to as a memory cell MC, such as MRAM cell.

Reference is made toFIG.20. An ILD layer220is formed over the structure ofFIG.19, and then openings230O are etched in the ILD layer220. Depending on the profile of the metallization pattern subsequently formed in the openings230O, the openings230O may be a via opening, a trench opening, or the combination thereof. The openings230O may be etched such that the magnetic shielding elements192are not exposed. For example, etch parameters (e.g., etch time) may be controlled such that the ILD layer220over the magnetic shielding elements192is not entirely etched away. Through the configuration, after etching the openings230O, a portion of the ILD layer220or other dielectric material remains covering top surfaces of the magnetic shielding elements192and spacers182and202. For example, a bottom of the openings230O is higher than the top surfaces of the magnetic shielding elements192.

Reference is made toFIG.21. A metallization pattern230is then formed in the openings2200the ILD layer220. The metallization pattern230may be spaced apart from the magnetic shielding elements192by the portion of ILD layer220or other dielectric materials. In the present embodiments, the metallization pattern230include conductive lines connected to the top electrodes162, and does not include a conductive via intervened between conductive lines and the top electrodes162. In some other embodiments, the metallization pattern230may include conductive vias, conductive lines, or the combination thereof.

The magnetic shielding elements192may be located between the first and second spacers182and202. In some embodiments, the first spacers182space the magnetic shielding elements192apart from the top electrodes162, and the second spacers202serves as an etch mask during patterning the magnetic shielding layer190and the bottom electrode layer140(referring toFIGS.18-19). Through the configuration, the magnetic shielding elements192may be in contact with the bottom electrodes142, but not establish an electrical connection between the bottom electrodes142and the top electrodes162or an electrical connection between the bottom electrodes142and the metallization pattern230.

In some embodiments, the top electrode162and the resistance switching element152are over a first portion of the bottom electrode142, the magnetic shielding element192is over a second portion of the bottom electrode142. In the present embodiments, the first spacer182may space the portion192aof the magnetic shielding element192apart from the sidewall of the resistance switching element152, and the portion192bof the magnetic shielding element192may be in contact with the top surface of the second portion of the bottom electrode142. Other details of the embodiments inFIGS.14-21are similar to those illustrated in the embodiments ofFIGS.2-13, and therefore not repeated herein.

FIGS.22and23are cross-sectional views of an integrated circuit device in various stages of fabrication in accordance with some embodiments of the present disclosure. The present embodiments are similar to those illustrated inFIGS.14-21, except that third spacers212are formed around the memory stacks MS prior to forming the ILD layer220. The illustration is merely exemplary and is not intended to limit beyond what is specifically recited in the claims that follow. It is understood that additional operations may be provided before, during, and after the operations shown byFIGS.2-14, and some of the operations described below can be replaced or eliminated for additional embodiments of the method. The order of the operations/processes may be interchangeable.

Reference is made toFIG.22. Third spacers212are formed around the memory stacks MS, respectively. The third spacer212may be made of non-magnetic material. The third spacer212, in some embodiments may include SiN, but in other embodiments may include SiC, SiON, silicon oxycarbide (SiOC), the like, and/or combinations thereof. The formation of the third spacers212comprises depositing a third spacer layer over the structure ofFIG.20, and patterning the third spacer layer into the third spacers212. In some other embodiments, the deposited third spacer layer may be free of being patterned, such that the third spacers212respectively around the memory stacks MS are continuously connected with each other.

Reference is made toFIG.23. An ILD layer220is formed over the structure ofFIG.22, and then a metallization pattern230is then formed in the ILD layer220.

In the present embodiments, the third spacers212space the magnetic shielding elements192apart from the metallization pattern230. Similar to those illustrated above, the first spacers182space the magnetic shielding elements192apart from the top electrodes162, the second spacers202serves as an etch mask during patterning the magnetic shielding layer190and the bottom electrode layer140(referring toFIGS.18-19). Through the configuration, the magnetic shielding elements192may be in contact with the bottom electrodes142, but not establish an electrical connection between the bottom electrodes142and the top electrodes162or an electrical connection between the bottom electrodes142and the metallization pattern230. The third spacers212are not over the bottom electrodes142in the present embodiments. For example, bottoms of the third spacers212are lower than a top surface of the bottom electrode142. The third spacer212may be in contact with a top surface of the dielectric layer120. Other details of the embodiments inFIGS.22and23are similar to those illustrated in the embodiments ofFIGS.14-21, and therefore not repeated herein.

FIG.24is a cross-sectional view of another integrated circuit device in accordance with some embodiments of the present disclosure. The integrated circuit includes a logic region900and a memory region910. Logic region900may include circuitry, such as the exemplary transistor902, for processing information received from memory cells MC in the memory region910and for controlling reading and writing functions of memory cells MC. In some embodiments, the memory cells MC includes a bottom electrode142, a resistance switching element152over the bottom electrode142, a top electrode162over the resistance switching element152. In some embodiments, each of the memory cells MC are surrounded by a magnetic shielding element192.

As depicted, the integrated circuit is fabricated using six metallization layers, labeled as M1through M5, with five layers of metallization vias or interconnects, labeled as V1through V5. Other embodiments may contain more or fewer metallization layers and a corresponding more or fewer number of vias. Logic region900includes a full metallization stack, including a portion of each of metallization layers M1-M5connected by interconnects V2-V5, with the interconnect V1connecting the stack to a source/drain contact of logic transistor902. The memory region910includes a full metallization stack connecting memory cells MC to transistors912in the memory region910, and a partial metallization stack connecting a source line to transistors912in the memory region910. Memory cells MC are depicted as being fabricated in between the top of the metallization layer M4and the bottom of the metallization layer M5. The metallization layer M4is connected with the bottom electrode924through a BEVA130in a dielectric layer120, and the metallization layer M5is connected with the top electrode162. Six ILD layers, identified as ILD0through ILD5are depicted inFIG.24as spanning the logic region900and the memory region910. The ILD layers may provide electrical insulation as well as structural support for the various features of the integrated circuit during many fabrication process steps.

Based on the above discussions, it can be seen that the present disclosure offers advantages. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that magnetic shielding elements are respectively disposed to surrounding memory cells, thereby boosting the magnetic immunity. For example, magnetic field flux/lines are directed to pass more through the magnetic shielding elements, less through the memory cells. Therefore, the magnetic shielding elements mitigates the adverse effects of external turbulent and in-cell magnetic cross talk. Another advantage is that it is easy to integrate the magnetic shielding material in MRAM process loop. Still another advantage is that the fabrication process can be performed with much low cost reduction compared to shielding in package level.

According to some embodiments of the present disclosure, an integrated circuit device includes a substrate, a memory cell, a magnetic shielding element, an interlayer dielectric layer, and a metallization pattern. The memory cell is over the substrate. The memory cell includes a bottom electrode, a resistance switching element over the bottom electrode, a top electrode over the resistance switching element. The magnetic shielding element is around the memory cell. The interlayer dielectric layer surrounds the memory cell and the magnetic shielding element. The metallization pattern is in the interlayer dielectric layer and connected to the top electrode.

According to some embodiments of the present disclosure, an integrated circuit device includes a substrate, a memory cell, a magnetic shielding element, an interlayer dielectric layer, and a metallization pattern. The bottom electrode is over the substrate. The resistance switching element is over a first portion of the bottom electrode. The top electrode is over the resistance switching element. The magnetic shielding element is over a second portion of the bottom electrode. The interlayer dielectric layer surrounds the bottom electrode, the resistance switching element, the top electrode, and the magnetic shielding element. The metallization pattern is in the interlayer dielectric layer and connected to the top electrode.

According to some embodiments of the present disclosure, a method for fabricating an integrated circuit device is provided. The method includes forming a memory cell over a substrate, wherein the memory cell comprises a bottom electrode, a resistance switching element over the bottom electrode, a top electrode over the resistance switching element; forming a magnetic shielding element around the memory cell; depositing an interlayer dielectric layer around the memory cell and the magnetic shielding element; and forming a metallization pattern in the interlayer dielectric layer and connected to the top electrode.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.