Patent ID: 12211909

Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosure, and do not limit the scope of the disclosure.

The present disclosure will be described with respect to embodiments in a specific context, a lateral double-diffused metal oxide semiconductor (LDMOS) device including a split-gate structure. The embodiments of the disclosure may also be applied, however, to a variety of metal oxide semiconductor field effect transistors (MOSFETs).

FIG.3illustrates a simplified cross-sectional view of an LDMOS device having a split-gate structure in accordance with various embodiments of the present disclosure. The LDMOS device300include a substrate102, a first layer104, a drift layer106formed over the first layer104and a body region112. The LDMOS device300further comprises a first drain/source region114and a body contact region118formed in the body region112, a second drain/source region116formed in the drift layer106, a gate dielectric layer134, a local oxidation of silicon (LOCOS) structure132, a first gate124and a second gate126. The LDMOS device300further comprises a plurality of contacts including a source contact plug141, a source contact142, a first gate contact plug143, a first gate contact144, a second gate contact plug145, a second gate contact146, a drain contact plug147and a drain contact148.

In some embodiments, the substrate102, the body region112and the body contact region118have a first conductivity type. The first layer104, the drift layer106, the first drain/source region114and the second drain/source region116have a second conductivity type. In some embodiments, the first conductivity type is p-type, and the second conductivity type is n-type. The LDMOS device300is an n-type transistor. Alternatively, the first conductivity type is n-type, and the second conductivity type is p-type. The LDMOS device300is a p-type transistor.

The substrate102may be formed of suitable semiconductor materials such as silicon, silicon germanium, silicon carbide and the like. Depending on different applications and design needs, the substrate102may be n-type or p-type. In some embodiments, the substrate102is a p-type substrate. Appropriate p-type dopants such as boron and the like are doped into the substrate102. Alternatively, the substrate102is an n-type substrate. Appropriate n-type dopants such as phosphorous and the like are doped into the substrate102.

The first layer104may comprise an epitaxial layer and a buried layer. In some embodiments, both the epitaxial layer and the buried layer are n-type layers. The n-type buried layer is formed between the substrate102and the n-type epitaxial layer. The n-type buried layer is deposited over the substrate102for isolation purposes. For example, the n-type buried layer is employed to prevent the current from flowing into the substrate102, thereby avoiding the leakage in the LDMOS device300. The n-type epitaxial layer is grown over the substrate102. The epitaxial growth of the n-type epitaxial layer may be implemented by using any suitable semiconductor fabrication processes such as chemical vapor deposition (CVD) and the like. In some embodiments, the n-type epitaxial layer is of a doping density in a range from about 1014/cm3to about 1016/cm3.

The drift layer106is an n-type layer formed over the first layer104. In some embodiments, the drift layer106may be doped with an n-type dopant such as phosphorous to a doping density of about 1015/cm3to about 1017/cm3. It should be noted that other n-type dopants such as arsenic, antimony, or the like, could alternatively be used. It should further be noted that throughout the description, the drift layer106may be alternatively referred to as an extended drain region.

The body region112is a p-type body region. The p-type body regions may be formed by implanting p-type doping materials such as boron and the like. Alternatively, the p-type body region can be formed by a diffusion process. In some embodiments, a p-type material such as boron may be implanted to a doping density of about 1016/cm3to about 1018/cm3. The body region112may be alternatively referred to as a channel region.

The first drain/source region114is a first N+ region formed in the body region112. The first drain/source region114may be alternatively referred to as the first N+ region114. In accordance with an embodiment, the first N+ region114functions as a source region of the LDMOS device300. The source region may be formed by implanting n-type dopants such as phosphorous and arsenic at a concentration of between about 1019/cm3and about 1020/cm3. As shown inFIG.3, the source contact plug141and the source contact142are formed over the first N+ region114.

The body contact region118is a P+ region formed in the body region112. The body contact region118may be alternatively referred to as the P+ region118. As shown inFIG.3, the P+ region118is formed immediately adjacent to the first N+ region114in the body region112. The P+ region118may be formed by implanting a p-type dopant such as boron at a concentration of between about 1019/cm3and about 1020/cm3. The P+ region118may contact the p-type body. In order to eliminate the body effect, the P+ region may be connected to the source region (the first N+ region114) directly through the source contact plug141.

The second drain/source region116is a second N+ region. The second drain/source region116may be alternatively referred to as the second N+ region116. In accordance with an embodiment, the second N+ region116functions as a drain region of the LDMOS device300. The second N+ region116may be formed by implanting n-type dopants such as phosphorous and arsenic at a concentration of between about 1019/cm3and about 1020/cm3. As shown inFIG.3, the drain contact plug147and the drain contact148are formed over the second N+ region116.

The gate dielectric layer134is formed over the drift layer106. The upper portion of the LOCOS structure132is over the drift layer106. The lower portion of the LOCOS structure132extends into the drift layer106. As shown inFIG.3, the gate dielectric layer134is partially on top of the body region112, and partially on top of the drift layer106. The LOCOS structure132is formed between the gate dielectric layer134and the second N+ region116.

As shown inFIG.3, the thickness of the LOCOS structure132is much greater than the thickness of the gate dielectric layer134. In some embodiments, the gate dielectric layer134is of a thickness of between about 100 Angstroms and about 200 Angstroms. The thickness of the LOCOS structure132is in a range from about 5000 Angstroms to about 10000 Angstroms. In some embodiments, the gate dielectric layer134and the LOCOS structure132may be formed of suitable oxide materials such as silicon oxide, silicon oxynitride, hafnium oxide, zirconium oxide or the like.

The first gate124is formed on the gate dielectric layer133. The second gate126is formed on the LOCOS structure132. As shown inFIG.3, the first gate124covers a top surface of the gate dielectric layer134and a lower portion of a sidewall of the LOCOS structure132. The second gate126partially covers a top surface of the LOCOS structure132.

The second gate126is electrically connected to the source region of the LDMOS device300(the first N+ region114). The detailed layout of the connection between the second gate126and the source region will be described below with respect toFIG.4. The first gate124and the second gate126may be formed of polysilicon, polysilicon germanium, nickel silicide or other metal, metal alloy materials.

As shown inFIG.3, the first gate124fully covers the channel region (the portion of the body region between the first N+ region114and the drift layer106). The first gate124functions as a gate electrode configured to control the current flowing between the drain and source of the LDMOS device300. The second gate126partially covers the top surface of the LOCOS structure132. The second gate126and the LOCOS structure132form a field plate. This field plate helps to maintain the breakdown voltage of the LDMOS device300.

The first gate124and the second gate126form a split-gate structure. In comparison with a conventional LDMOS device having a gate extending over the LOCOS structure132(e.g., the LDMOS device shown inFIGS.1-2), the split-gate structure helps to reduce the gate-to-drain overlap capacitance, thereby improving the switching performance of the LDMOS device300.

The first gate124and the second gate126may be formed by depositing a polysilicon layer with a thickness of about 4000 Angstroms over the gate dielectric layers and the high voltage oxide region, depositing a photoresist layer over the polysilicon layer, developing the photoresist layer to define the first gate124and the second gate126, etching the polysilicon layer to form the first gate124and the second gate126.

As shown inFIG.3, the first gate contact plug143and the second gate contact plug145are formed in a dielectric layer140. The first gate contact144is connected to the first gate124through the first gate contact plug143. The second gate contact146is connected to the second gate126through the second gate contact plug145.

The dielectric layer140may be a low-k dielectric layer having a low dielectric constant. The dielectric layer140may also comprise a combination of materials such as silicon nitride, silicon oxy-nitride and the like. The dielectric layer140may be deposited using suitable deposition techniques such as sputtering, CVD and the like.

In some embodiments, an anisotropic etching process is applied to the dielectric layer140to form a plurality of openings. A suitable metal material is filled in the openings to form the contact plugs141,143,145and147. The metal material may be copper, tungsten, titanium, aluminum, any combinations thereof and/or the like.

FIG.3shows an LDMOS device having a split-gate structure. In comparison with a conventional LDMOS device having a gate extending over the LOCOS structure (e.g., the LDMOS device shown inFIGS.1-2), the split-gate structure is able to achieve better switching performance without degrading the breakdown voltage of the LDMOS device. Furthermore, the split-gate structure may reduce the total power losses of the LDMOS device. In particular, the field plate of the conventional LDMOS device may induce an accumulation layer in the drain extension after a positive gate voltage is applied to the gate of the conventional LDMOS device. The accumulation layer helps to lower the on resistance of the conventional LDMOS device. The split-gate structure shown inFIG.3cannot induce the accumulation layer because the second gate126is electrically connected to the source of the LDMOS device300. The on resistance of the LDMOS device having a split-gate structure may increase slightly. For example, for a 30-V LDMOS device, the on resistance may increase by 10% after having the split-gate structure. However, the split-gate structure is able to reduce the gate charge, which helps to lower the total power losses of the LDMOS device. A figure of merit (FOM) is a widely used performance index for measuring the total power losses of LDMOS devices. FOM is the product of RON×QG. RONis the on resistance of an LDMOS device. QGis the gate charge of the LDMOS device. By using the split-gate structure shown inFIG.3, for a 30-V LDMOS device, the FOM of this 30-V LDMOS device is lowered from 145 mΩ-nC to 86 mΩ-nC. The FOM is reduced by 41%.

FIG.4illustrates a simplified top view of the LDMOS device shown inFIG.3in accordance with various embodiments of the present disclosure. The P+ region118, the first N+ region114and the second N+ region116are formed over the drift layer106. The first gate124and the second gate126are formed over the drift layer106and between the first N+ region114and the second N+ region116. As shown inFIG.4, there is a gap between the first gate124and the second gate126.

A plurality of source contact plugs141is formed over the P+ region118and the first N+ region114. The plurality of source contact plugs141couples the P+ region118to the first N+ region114. The source contact142is formed over the plurality of source contact plugs141. As shown inFIG.4, the source contact142is a metal plane.

A plurality of drain contact plugs147is formed over the second N+ region116. The drain contact148is formed over the plurality of drain contact plugs147. As shown inFIG.4, the drain contact148is a metal plane.

A first gate contact plug143is formed over the first gate124. The first gate contact144is formed over the first gate contact plug143. As shown inFIG.4, the first gate contact144is a metal plane.

A second gate contact plugs145is formed over the second gate126. The second gate contact146is formed over the second gate contact plug145. As shown inFIG.4, the second gate contact146is a metal plane.

As shown inFIG.4, the metal plane of the second gate contact146is electrically connected to the metal plane of the source contact142. Through this connection, the second gate126is electrically connected to the first N+ region114.

The metal planes shown inFIG.4are substantially rectangular in shape. It is within the scope and spirit of the disclosure for the metal planes to comprise other shapes, such as, but not limited to oval, square, or circular.

FIG.5illustrates a comparison between an LDMOS device having a split-gate structure and a conventional LDMOS device in accordance with various embodiments of the present disclosure. The vertical axis represents the gate drive voltage (Vg). The horizontal axis represents the total gate charge (Qg). The total gate charge Qg is defined as the charge required for the gate of the LDMOS device to be charged from 0 V to the maximum gate voltage (e.g., 5 V).

As shown inFIG.5, the solid line represents the gate charge profile of the conventional LDMOS device. The dashed line represents the gate charge profile of the LDMOS device having a split-gate structure. Before the start of the Miller Plateau (dashed line A shown inFIG.5), the gate charge of the conventional LDMOS device (e.g., the LDMOS device shown inFIGS.1-2) is approximately equal to the gate charge of the LDMOS device having a split-gate structure. Qgdsplit_gateis the gate charge of the LDMOS device having a split-gate structure. As shown inFIG.5, Qgdsplit_gateis the gate charge from the start to the end of the Miller Plateau of the LDMOS device having a split-gate structure. Qgdconventionalis the gate charge of the conventional LDMOS device. As shown inFIG.5, Qgdconventionalis the gate charge from the start to the end of the Miller Plateau of the conventional LDMOS device. As shown inFIG.5, Qgdconventionalis much greater than Qgdsplit_gate. The comparison between Qgdsplit_gateand Qgdconventionalindicates the split-gate structure helps to reduce the gate charge from the start to the end of the Miller Plateau of the LDMOS device.

Qgsplit_gateis the gate charge of the LDMOS device having a split-gate structure. As shown inFIG.5, Qgsplit_gateis the gate charge from 0 V to the maximum gate drive voltage. Qgconventionalis the gate charge of the conventional LDMOS device. As shown inFIG.5, Qgconventionalis the gate charge from 0 V to the maximum gate drive voltage. As shown inFIG.5, Qgconventionalis much greater than Qgsplit_gate. The comparison between Qgsplit_gateand Qgconventionalindicates the split-gate structure helps to reduce the gate charge from 0 V to the maximum gate drive voltage.

FIG.6illustrates a simplified cross-sectional view of another LDMOS device having a split-gate structure in accordance with various embodiments of the present disclosure. The LDMOS device600shown inFIG.6is similar to the LDMOS device300shown inFIG.3except that the second gate126fully covers the top surface of the LOCOS structure132. The operating principle of the LDMOS device600is similar to the operating principle of the LDMOS device300, and hence is not discussed herein again.

FIG.7illustrates a simplified cross-sectional view of another LDMOS device having a split-gate structure in accordance with various embodiments of the present disclosure. The LDMOS device700shown inFIG.7is similar to the LDMOS device300shown inFIG.3except that the LOCOS structure is replaced by a high voltage oxide region132.

As shown inFIG.7, the gate dielectric layer134extends from an edge of the source region114to a sidewall of the high voltage oxide region132. The first gate124covers a top surface of the gate dielectric layer134and a lower portion of the sidewall of the high voltage oxide region132. The second gate126fully covers a top surface of the high voltage oxide region132.

The LDMOS device having a high voltage oxide region for improving the breakdown voltage is well known in the art, hence is not discussed again herein. The LDMOS device700shown inFIG.7may be used in medium voltage applications such as 24 V applications.

FIG.8illustrates a simplified cross-sectional view of another LDMOS device having a split-gate structure in accordance with various embodiments of the present disclosure. The LDMOS device800shown inFIG.8is similar to the LDMOS device300shown inFIG.3except that the LOCOS structure is replaced by a shallow trench isolation (STI) region132.

As shown inFIG.8, the gate dielectric layer134extends from an edge of the source region114to a sidewall of the STI region132. The first gate124covers a top surface of the gate dielectric layer134. The second gate126partially covers a top surface of the STI region132.

The LDMOS device with the STI region for improving the breakdown voltage is well known in the art, hence is not discussed again herein. The LDMOS device800shown inFIG.8may be used in medium voltage applications such as 24 V applications.

FIG.9illustrates a simplified cross-sectional view of another LDMOS device having a split-gate structure in accordance with various embodiments of the present disclosure. The LDMOS device900shown inFIG.9is similar to the LDMOS device700shown inFIG.7except that the LDMOS device900does not include a high voltage oxide region. The LDMOS device900shown inFIG.9may be used in medium voltage applications such as 12 V applications.

FIG.10illustrates a flow chart of a method for forming the LDMOS device shown inFIG.3in accordance with various embodiments of the present disclosure. This flowchart shown inFIG.10is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various steps illustrated inFIG.10may be added, removed, replaced, rearranged and repeated.

An LDMOS device comprises a first drain/source region and a second drain/source region formed over a substrate. In some embodiments, the first drain/source region is a source region. The second drain/source region is a drain region. The LDMOS device further comprises a drift layer over the substrate, a body region formed in the drift layer, and a dielectric region formed over the substrate and between the first drain/source region and the second drain/source region.

The dielectric region comprises a first portion and a second portion. The first portion is over the body region and the drift layer. The second portion is over the drift layer. The second portion is between the first portion and the drain region. In some embodiments, the second portion is an LOCOS structure.

The LDMOS device further comprises a first gate and a second gate formed over the first portion and the second portion of the dielectric region, respectively. The first gate and the second gate are electrically isolated from each other. One of the first gate and the second gate is electrically connected to the first drain/source region. In some embodiments, the first gate is electrically connected to the first drain/source region.

At step1002, an epitaxial layer (e.g., layer104shown inFIG.3) with a second conductivity type is grown over a substrate (e.g., layer102shown inFIG.3) with a first conductivity type. In some embodiments, the first conductivity is p-type, and the second conductivity is n-type.

At step1004, a drift layer (e.g., layer106shown inFIG.3) having the second conductivity type is formed over the epitaxial layer. At step1006, a body region (e.g., region112shown inFIG.3) with the first conductivity type is formed in the drift layer.

At step1008, ions with the second conductivity type are implanted to form a source region (e.g., region114shown inFIG.3) in the body region and a drain region (e.g., region116shown inFIG.3) in the drift layer.

At step1010, a first dielectric layer (e.g., layer134shown inFIG.3) is formed over the body region and the drift layer. At step1012, a second dielectric layer (e.g., layer132shown inFIG.3) is formed over the drift layer, and between the first dielectric layer and the drain region.

At step1014, a first gate (e.g., gate124shown inFIG.3) is formed over the first dielectric layer. At step1016, a second gate (e.g., gate126shown inFIG.3) is formed over the second dielectric layer. The second gate is electrically connected to the source region.

The method further comprises forming a body contact of the first conductivity type in the body region, wherein the body contact and the source region are electrically connected to each other.

With reference toFIG.3, the method further comprises forming the first dielectric layer from an edge of the source region to a sidewall of the second dielectric layer, and forming the first gate along the edge of the source region, wherein the first gate covers a top surface of the first dielectric layer and a lower portion of the sidewall of the second dielectric layer, and wherein the second gate partially covers a top surface of the second dielectric layer, and the second dielectric layer is a local oxidation of silicon (LOCOS) structure.

With reference toFIG.6, the method further comprises forming the first dielectric layer from an edge of the source region to a sidewall of the second dielectric layer, and forming the first gate along the edge of the source region, wherein the first gate covers a top surface of the first dielectric layer and a lower portion of the sidewall of the second dielectric layer, and wherein the second gate fully covers a top surface of the second dielectric layer, and the second dielectric layer is an LOCOS structure.

With reference toFIG.7, the method further comprises forming the first dielectric layer from an edge of the source region to a sidewall of the second dielectric layer, and forming the first gate along the edge of the source region, wherein the first gate covers a top surface of the first dielectric layer and a lower portion of the sidewall of the second dielectric layer, and wherein the second gate fully covers a top surface of the second dielectric layer, and the second dielectric layer is a high voltage oxide region.

With reference toFIG.8, the method further comprises forming the first dielectric layer from an edge of the source region to a sidewall of the second dielectric layer, and forming the first gate along the edge of the source region, wherein the first gate covers a top surface of the first dielectric layer, and wherein the second gate partially covers a top surface of the second dielectric layer, and the second dielectric layer is a shallow trench isolation (STI) region.

Although embodiments of the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.