Patent ID: 12225786

DETAILED DESCRIPTION

For clearer descriptions of the objectives, technical solutions, and advantages of the present disclosure, embodiments of the present disclosure are described in detail hereinafter with reference to the accompanying drawings.

In the related art, a camera of a display device may be disposed in a display region of a display panel to increase a screen-to-body ratio of the display panel. The display region of the display panel includes: an anode layer, a light-emitting layer, and a cathode layer that are sequentially stacked in a direction going away from a base substrate. The camera is disposed on a side of the anode layer distal from the light-emitting layer.

However, the cathode layer will affect a transmittance, thus an imaging effect of the camera disposed in the display region of the display panel being poor.

FIG.1is a schematic structural diagram of a display panel according to an embodiment of the present disclosure. Referring toFIG.1, a display panel10may include: a base substrate101, a first anode layer102, a first light-emitting layer103, a first cathode layer104, a second cathode layer105, a second anode layer106, a second light-emitting layer107, a third cathode layer108, and a first signal transmission layer109.

FIG.2is a top view of a base substrate according to an embodiment of the present disclosure. In combination withFIG.1andFIG.2, the base substrate101may include a first display region101a, a second display region101b, and a routing region101c. The first anode layer102, the first light-emitting layer103, and the first cathode layer104may be disposed in the first display region101a, and sequentially stacked in a direction going away from the base substrate101. The second cathode layer105, the second anode layer106, the second light-emitting layer107, and the third cathode layer108may be disposed in the second display region101b, and sequentially stacked in the direction going away from the base substrate101. The first signal transmission layer109may be disposed in the routing region101c, and a signal transmitted by the first signal transmission layer109being different from signals transmitted by the first anode layer102and the second anode layer106.

Referring toFIG.2, the routing region101cis a strip-shaped region and disposed on the same side of the first display region101aand the second display region101b. In addition, the routing region101cmay be a ring-shaped region surrounding the first display region101aand the second display region101b. The shape of the routing region101cis not limited in the embodiments of the present disclosure.

FIG.3is a schematic diagram of a portion of a third cathode layer according to an embodiment of the present disclosure. Referring toFIG.3, the third cathode layer108may include a plurality of first cathode patterns1081spaced apart. The first cathode pattern1081may include a first connecting portion (not shown in the drawing). The first cathode pattern1081may be connected to the second cathode layer105via the first connecting portion.

Optionally, the second anode layer106, the second light-emitting layer107, and the third cathode layer108may be divided into a plurality of first sub-pixels. An orthographic projection of a light-emitting region of the first sub-pixel on the base substrate101is within an overlapping region between the second cathode layer105and the third cathode layer108.

Referring toFIG.1, the second anode layer106may include a plurality of anode patterns1061. The second light-emitting layer107may include a plurality of light-emitting layer patterns1071. In addition, the anode patterns1061, the light-emitting layer patterns1071, and the first cathode patterns1081may correspond to each other. Each anode pattern1061, one corresponding light-emitting layer pattern1071and one corresponding first cathode pattern1081may form a first sub-pixel. Two adjacent anode patterns1061may correspond to the same first cathode pattern1081, or may respectively correspond to two different first cathode patterns1081, which is not limited in the embodiment of the present disclosure.

In the embodiment of the present disclosure, referring toFIG.1, an orthographic projection of the first signal transmission layer109on the base substrate101is partially overlapped with an orthographic projection of the second cathode layer105on the base substrate101. The first signal transmission layer109includes: a second connecting portion (not shown in the drawing). The first signal transmission layer109may be connected to the second cathode layer105via the second connecting portion. The first signal transmission layer109is further configured to receive a power supply signal.

That is, the second cathode layer105is connected to the first cathode pattern1081of the third cathode layer108, and the second cathode layer105is further connected to the first signal transmission layer109. Thus, the first signal transmission layer109may be connected to the first cathode pattern1081of the third cathode layer108via the second cathode layer105. The power supply signal received by the first signal transmission layer109may be transmitted to the first cathode pattern1081via the second cathode layer105to supply power to the first cathode pattern1081.

In addition, the orthographic projection of the first signal transmission layer109on the base substrate101may further partially overlap with an orthographic projection of the first cathode layer104on the base substrate101, and the first signal transmission layer109is connected to the first cathode layer104. Therefore, the power supply signal received by the first signal transmission layer109may be transmitted to the first cathode layer104to supply power to the first cathode layer104.

In the embodiment of the present disclosure, the second cathode layer105may entirely cover the second display region101b. Therefore, a resistance of the second cathode layer105may be smaller, such that a voltage difference of the power supply signal received by each first cathode pattern1081is smaller, thereby ensuring luminance uniformity of the second display region101b, and further ensuring a display effect of the display panel10.

In summary, the embodiment of the present disclosure provides a display panel. A plurality of first cathode patterns of a third cathode layer included in the display panel are spaced apart, such that the first cathode patterns will not entirely cover the second display region. In comparison with the cathode layer entirely covering the second display region, the impact on a light transmittance is effectively reduced, and the imaging effect of a camera disposed in the second display region is enhanced.

Optionally, the second cathode layer105in the display panel10may be made of a transparent conductive material. In this way, signal transmission may be performed, and a great impact on the light transmittance caused by the second cathode layer105may be avoided, thereby ensuring the imaging effect of the camera. Exemplarily, the second cathode layer105may be made of indium tin oxide (ITO).

In the embodiment of the present disclosure, the first anode layer102, the second anode layer106, and the first signal transmission layer109may be disposed in the same layer. The first light-emitting layer103and the second light-emitting layer107may be disposed in the same layer. The first cathode layer104and the third cathode layer108may be disposed in the same layer.

That is, the first anode layer102, the second anode layer106, and the first signal transmission layer109may be prepared by a same patterning process. The first light-emitting layer103and the second light-emitting layer107may be prepared by a same patterning process. The first cathode layer104and the third cathode layer108may be prepared by a same patterning process.

The signal transmitted by the first signal transmission layer109is different from the signals transmitted by the first anode layer102and the second anode layer106. For example, the signal transmitted by the first signal transmission layer109may be a power supply signal, and the signals transmitted by the first anode layer102and the second anode layer106may be anode driving signals.

In the embodiment of the present disclosure, the first anode layer102, the first light-emitting layer103, and the first cathode layer104may be divided into a plurality of second sub-pixels. An orthographic projection of a light-emitting region of the second sub-pixel on the base substrate101may be within the orthographic projection of the first cathode layer104on the base substrate101.

The first anode layer102may include: a plurality of anode patterns (not shown inFIG.1). The first light-emitting layer103may include a plurality of light-emitting layer patterns (not shown inFIG.1). The anode patterns one-to-one correspond to the light-emitting layer patterns. Each anode pattern, one corresponding light-emitting layer pattern, and the first cathode layer104may form a second sub-pixel.

In the embodiment of the present disclosure, the first sub-pixels may be categorized into a plurality of sub-pixel groups, each sub-pixel group may include a plurality of first sub-pixels, and the light-emitting regions of the first sub-pixels in at least one of the sub-pixel groups may be arranged in three rows and three columns.

The light-emitting regions of the first sub-pixels in the sub-pixel group are arranged in three rows and three columns means that the light-emitting regions of the first sub-pixels exist in at least part of nine positions in three rows and three columns. Exemplarily, the at least one of the sub-pixel groups may include: one first sub-pixel of a first color, two first sub-pixels of a second color, and one first sub-pixel of a third color. That is, the at least one of the sub-pixel groups includes four first sub-pixels, and the light-emitting region of each first sub-pixel in the four first sub-pixels may be disposed in any one of the mine positions in three rows and three columns.

Optionally, the first color may be red (R), the second color may be green (G), and the third color may be blue (B).

FIG.4is a schematic diagram of the first cathode pattern and the light-emitting region of the first sub-pixel according to an embodiment of the present disclosure. Referring toFIG.4, an orthographic projection of the first cathode pattern1081on the base substrate101may cover an orthographic projection of one sub-pixel group on the base substrate101. That is, the orthographic projection of the first cathode pattern1081on the base substrate101covers an orthographic projection of the light-emitting region of the one first sub-pixel of the first color on the base substrate101, covers orthographic projections of the light-emitting regions of the two first sub-pixels of the second color on the base substrate101, and covers an orthographic projection of the light-emitting region of the one first sub-pixel of the third color on the base substrate101.

Optionally, the shape of the first cathode pattern1081may be a first shape, and the first shape may be a centrosymmetric shape or an axisymmetric shape (the first shape being a regular shape). Exemplarily, referring toFIG.4, the shape of the first cathode pattern1081may be a rectangle. Alternatively, referring toFIG.5, the shape of the first cathode pattern1081may be a cross. Alternatively, referring toFIG.6, the shape of the first cathode pattern1081may be an octagon.

Alternatively, the shape of the first cathode pattern1081may be a second shape. Referring toFIG.7andFIG.8, the second shape may be formed by connecting a plurality of straight line segments and a plurality of arc line segments end to end (the second shape being an irregular shape). The shape of the first cathode pattern1081is not limited in the embodiment of the present disclosure.

In addition, an extending direction of at least one of the straight line segments may be parallel to an extending direction of a boundary of the light-emitting region of at least one of the first sub-pixels in the sub-pixel group.

Referring toFIG.4andFIG.7, in at least one of the sub-pixel groups, the light-emitting region of the first sub-pixel of the first color may be disposed in row 3 and column 1, the light-emitting region of one first sub-pixel of the second color is disposed in row 1 and column 3, the light-emitting region of the other second sub-pixel of the second color is disposed in row 3 and column 3, and the light-emitting region of the first sub-pixel of the third color is disposed in row 2 and column 2.

Referring toFIG.5,FIG.6andFIG.8, in at least one of the sub-pixel groups, the light-emitting region of the first sub-pixel of the first color is disposed in row 2 and column 3, the light-emitting region of one first sub-pixel of the second color is disposed in row 1 and column 2, the light-emitting region of the other first sub-pixel of the second color is disposed in row 3 and column 2, and the light-emitting region of the first sub-pixel of the third color is disposed in row 2 and column 1.

The first sub-pixels in the sub-pixel group may be arranged in other ways, which is not limited in the embodiment of the present disclosure.

In the embodiment of the present disclosure, the first cathode pattern1081is connected to the second cathode layer105via the first connecting portion. Thus, in order to avoid adverse impacts on normal light emission of the first sub-pixel in the sub-pixel group covered by the first cathode pattern1081due to the first connecting portion, a certain distance is required between the first connecting portion and the light-emitting region of the first sub-pixel in the sub-pixel group. Optionally, in at least one of the sub-pixel groups, the distance between the first connecting portion and the light-emitting region of at least one of the first sub-pixels in the sub-pixel group in a direction parallel to a bearing surface of the base substrate101may be greater than or equal to 2.5 microns. The bearing surface of the base substrate101may be interpreted as a plane of the base substrate101for disposing various film layers.

Exemplarily, in at least one of the sub-pixel groups, the distance between the first connecting portion and the light-emitting region of any first sub-pixel in the sub-pixel group in the direction parallel to the bearing surface of the base substrate101may be greater than or equal to 2.5 microns.

In at least one of the sub-pixel groups, the distance between the first connecting portion and the light-emitting region of any first sub-pixel in the sub-pixel group is greater than or equal to 2.5 microns may indicate: in at least one of the sub-pixel groups, a minimum distance between the first connecting portion and the light-emitting region of a first sub-pixel closest to the first connecting portion in the first sub-pixels included in the sub-pixel group may be 2.5 microns.

The distance between the first connecting portion and the light-emitting region of the first sub-pixel in the sub-pixel group should not be too large, otherwise an area of the first cathode pattern1081will be too large, which affects a transmittance of the display panel10. Optionally, in at least one of the sub-pixel groups, the distance between the first connecting portion and the light-emitting region of at least one of the first sub-pixels in the sub-pixel group in the direction parallel to the bearing surface of the base substrate101may be less than or equal to 15 microns.

Exemplarily, in at least one of the sub-pixel groups, the distance between the first connecting portion and the light-emitting region of any first sub-pixel in the sub-pixel group in the direction parallel to the bearing surface of the base substrate101may be less than or equal to 15 microns.

In at least one of the sub-pixel groups, the distance between the first connecting portion and the light-emitting region of any first sub-pixel of the sub-pixel group is less than or equal to 15 microns may indicate: a maximum distance between the first connecting portion and the light-emitting region of a first sub-pixel farthest from the first connecting portion in the first sub-pixels included in the sub-pixel group may be 15 microns.

FIG.9is a schematic structural diagram of a second cathode layer according to an embodiment of the present disclosure. Referring toFIG.9, the second cathode layer105may include: a joint1051. An orthographic projection of the joint1051on the base substrate101may partially overlap with the orthographic projection of the first signal transmission layer109on the base substrate101, such that the second connecting portion of the first signal transmission layer109is connected to the joint1051, and the power supply signal of the first signal transmission layer109is transmitted to the second cathode layer105. Pattern a1 in the first display region101ashown inFIG.9is a film layer with other functions prepared with the second cathode layer105by a same patterning process.

Referring toFIG.9, the second cathode layer105may include a plurality of joints1051. The joint1051may have a strip-shaped structure. Exemplarily, three joints1051are shown inFIG.9. The joint1051included in the second cathode layer105may be a sheet-shaped structure. The shape of the joint1051is not limited in the embodiment of the present disclosure.

Optionally, in response to the shape of the joint1051being the strip-shaped structure, a length of the joint1051in a first direction X1 is less than a length of a main body1052of the second cathode layer105in the first direction X1. In response to the shape of the joint1051being the sheet-shaped structure, the length of the joint1051in the first direction X1 may be equal to the length of the main body1052of the second cathode layer105in the first direction X1.

In addition, a length of the joint1051in a second direction X2 is related to a frame width of the display panel and a distance between the second display region101band the routing region101c, thus the length of the joint1051in the second direction X2 being not limited in the embodiment of the present disclosure. It is only necessary to ensure that the orthographic projection of the joint1051on the base substrate101is partially overlapped with the orthographic projection of the first signal transmission layer109on the base substrate101.

FIG.10is a schematic structural diagram of another display panel according to an embodiment of the present disclosure. Referring toFIG.10, the display panel10may further include: a first overcoat110disposed between the second cathode layer105and the third cathode layer108.FIG.11is a top view of the first overcoat according to an embodiment of the present disclosure. Referring toFIG.11, the first overcoat110is provided with a plurality of first via holes110aand a plurality of second via holes110b.

In the embodiment of the present disclosure, in order to illustrate respective via holes in the first overcoat110, the via holes are indicated by filling patterns inFIG.11. Other regions with no filling patterns indicate the regions that the first overcoat110made of a solid material. In addition, via holes a2 in the first display region101aand via holes a3 in the routing region101cshown inFIG.11are via holes with other functions.

FIG.12is a top view of the display panel ofFIG.10.FIG.13is a schematic diagram of the first connecting portion and the second connecting portion that are not shown inFIG.10. In combination withFIG.10,FIG.12andFIG.13, an orthographic projection of the first via hole110aon the base substrate101may be within the second display region101b, and the orthographic projection of the first via hole110aon the base substrate101is not overlapped with an orthographic projection of a light-emitting region b11 of a first sub-pixel b1 on the base substrate101. Therefore, an effect of the arrangement of the first via hole110aon the light-emitting region b11 of the first sub-pixel b1 nay be avoided, thereby ensuring that the first sub-pixel b1 can emit light normally.

Referring toFIG.10, the first connecting portion10811of the first cathode pattern1081includes a part disposed in the first via hole110a. Thus, the first cathode pattern1081may be connected to the second cathode layer105via the part of the first connecting portion10811disposed in the first via hole110a.

In combination withFIG.11toFIG.13, an orthographic projection of the second via hole110bon the base substrate101may be within the routing region101c. In addition, the orthographic projection of the second via hole110bon the base substrate101may be within the orthographic projection of the joint1051on the base substrate101. The second connecting portion1091of the first signal transmission layer109may have a part disposed in the second via hole110b. Thus, the first signal transmission layer109can be connected to the joint1051via the part of the second connecting portion1091disposed in the second via hole110b.

In the embodiment of the present disclosure, referring toFIG.10andFIG.13, the display panel10may further include: a plurality of pixel circuits (not shown in the drawing) disposed in the first display region101a, and a second signal transmission layer Ill disposed between the first overcoat110and the third cathode layer108. The pixel circuit may be electrically connected to the second anode layer106by the second signal transmission layer111, such that the pixel circuit can provide a driving signal to the second anode layer106.

Moreover, because of the pixel circuits being disposed in the first display region101a, the pixel circuits will not affect a transmittance of the second display region1011), and the imaging effect of a camera can be ensured.

FIG.14is a top view of a second signal transmission layer according to an embodiment of the present disclosure.FIG.15is a schematic diagram of a portion of the second signal transmission layer ofFIG.14. Referring toFIG.10andFIG.13toFIG.15, the second signal transmission layer111may include a plurality of transmission traces1111. One end of the transmission trace1111may be connected to the second anode layer106, and the other end of the transmission trace1111may be connected to the pixel circuit. That is, the pixel circuit may be connected to the second anode layer106via the transmission trace1111to provide a driving signal to the second anode layer106.

Optionally, the pixel circuits may include: a plurality of first-type pixel circuits and a plurality of second-type pixel circuits. The first-type pixel circuit may be connected to the anode pattern1061of the second anode layer106via the transmission trace1111. The second-type pixel circuit may be connected to the anode pattern1021of the first anode layer102. That is, the first-type pixel circuit may be configured to drive the first sub-pixel b1 disposed in the second display region101bto emit light, and the second-type pixel circuit may be configured to drive a second sub-pixel b2 in the first display region101ato emit light.

Referring toFIG.14, the second signal transmission layer111may further include: a plurality of first transmission patterns1112disposed in the second display region101b. Referring toFIG.10, the first transmission pattern1112may be disposed in the first via hole110aand configured to connect the second cathode layer105and the first connecting portion10811.

Because the second cathode layer105will be exposed by the first via hole110a, the first transmission pattern1112disposed in the first via hole110aof the first overcoat110may protect the second cathode layer105, thereby ensuring a quality of the second cathode layer105. Therefore, the reliability that the first signal transmission layer109transmits the power supply signal to the first cathode pattern1081by the second cathode layer105may be ensured.

In the embodiment of the present disclosure, a thickness of the first transmission pattern1112is generally less than a thickness of the first overcoat110, such that part of the first connecting portion10811may extend into the first via hole110a. The first connecting portion10811may be electrically connected to the second cathode layer105via the first transmission pattern1112. In response to the second signal transmission layer111not including the first transmission pattern1112disposed in the first via hole110a, the part of the first connecting portion10811may be disposed in the first via hole110aand directly electrically connected to the second cathode layer105. Therefore, in the above two cases, the first connecting portion10811includes a part disposed in the first via hole110a.

Referring toFIG.10,FIG.13andFIG.14, the second signal transmission layer111may further include: a plurality of second transmission patterns1113disposed in the routing region101c. The second transmission pattern1113may be disposed in the second via hole110band configured to electrically connect the second cathode layer105and the second connecting portion1091.

Because the first signal transmission layer109will be exposed by the second via hole110b, the second transmission pattern1113disposed in the second via hole110bof the first overcoat110may protect the first signal transmission layer109, thereby ensuring a quality of the first signal transmission layer109. In this way, the reliability that the first signal transmission layer109transmits the power supply signal to the second cathode layer105may be ensured.

In the embodiment of the present disclosure, a thickness of the second transmission pattern1113is generally less than the thickness of the first overcoat110, such that part of the second connecting portion1091may extend into the second via hole110b. The second connecting portion1091may be electrically connected to the first signal transmission layer109via the second transmission pattern1113. In response to the second signal transmission layer111not including the second transmission pattern1113disposed in the second via hole110b, the part of the second connecting portion1091may be disposed in the second via hole110b. The second connecting portion1091may be directly connected to the second cathode layer105. Therefore, in the above two cases, the second connecting portion1091includes a part disposed in the second via hole110b.

Optionally, the second signal transmission layer111in the display panel10according to the embodiment of the present disclosure may be made of a transparent conductive material. That is, the transmission trace1111, the first transmission pattern1112, and the second transmission pattern1113in the second signal transmission layer111are all made of the transparent conductive material. Therefore, on the premise of performing signal transmission, a great impact on the light transmittance caused by the second signal transmission layer111may be avoided, thereby ensuring the imaging effect of the camera.

Exemplarily, the transmission trace1111, the first transmission pattern1112, and the second transmission pattern1113in the second signal transmission layer111may all be made of the ITO.

Referring toFIG.10andFIG.13, the display panel10may further include: a second overcoat112disposed between the second signal transmission layer111and the third cathode layer108.FIG.16is a top view of the second overcoat according to an embodiment of the present disclosure. Referring toFIG.16, the second overcoat112may have a plurality of third via holes112aand a plurality of fourth via holes112b.

In the embodiment of the present disclosure, a first overlapping region may be between an orthographic projection of the third via hole112aon the base substrate101and the orthographic projection of the first via hole110aon the base substrate101. A ratio of an area of the first overlapping region to an area of the orthographic projection of the first via hole110aon the base substrate101may be greater than or equal to 80%. In combination withFIG.10andFIG.13, the first connecting portion10811may have a part disposed in the third via hole112a, and the first connecting portion10811may be configured to electrically connect the second signal transmission layer111and the third cathode layer108.

The second overcoat112is disposed between the second signal transmission layer111and the third cathode layer108, such that in response to the second overcoat112being formed, the second overcoat112may cover the first via hole110a. Therefore, by disposing the third via holes112ain the second overcoat112, the first overlapping region being between the orthographic projection of the third via hole112aon the base substrate101and the orthographic projection of the first via hole110aon the base substrate101, the first connecting portion10811may be disposed in the third via hole112afor electrical connection between the first transmission pattern1112and the first cathode pattern1081.

Furthermore, a second overlapping region may be between an orthographic projection of the fourth via hole112bon die base substrate101and the orthographic projection of the second via hole110bon the base substrate101. A ratio of an area of the second overlapping region to an area of the orthographic projection of the second via hole110bon the base substrate101is greater than or equal to 80%. In combination withFIG.10andFIG.13, the second connecting portion1091may have a part disposed in the fourth via hole112b, and the second connecting portion1091may be configured to electrically connect the first signal transmission layer109and the second signal transmission layer111.

The second overcoat112is disposed between the second signal transmission layer111and the third cathode layer108, such as being disposed between the second signal transmission layer111and the first signal transmission layer109. Therefore, in response to the second overcoat112being formed, the second overcoat112may cover the second via hole110b. Therefore, by disposing the fourth via holes1121) in the second overcoat112, the second overlapping region being between the orthographic projection of the fourth via hole112bon the base substrate101and the orthographic projection of the second via hole110bon the base substrate101, the second connecting portion1091may be disposed in the fourth via hole112bfor electrical connection between the second transmission pattern1113and the first signal transmission layer109.

In the embodiment of the present disclosure, referring toFIG.16, the second overcoat112may further have a plurality of fifth via holes112c. The anode pattern1061of the second anode layer106may include: a third connecting portion10611disposed in the fifth via hole112c, and the second anode layer106may be electrically connected to the transmission trace1111in the second signal transmission layer111via the third connecting portion10611.

Because of the second signal transmission layer111and the second anode layer106being respectively disposed on two sides of the second overcoat112, in order to electrically connect the second signal transmission layer111and the second anode layer106, the fifth via holes112care disposed in the second overcoat112. The third connecting portion10611disposed in the fifth via hole112emay be configured to electrically connect one transmission trace1111in the second signal transmission layer Ill and one anode pattern1061of the second anode layer106.

In the embodiment of the present disclosure, in order to illustrate respective via holes in the second overcoat112, the via holes are indicated by filling patterns inFIG.16. Other regions with no filling patterns indicate the regions that the second overcoat112made of a solid material. In addition, via holes a4 in the first display region101aand via holes a5 in the routing region101cshown inFIG.16are via holes with other functions.

Referring toFIG.10andFIG.13, the display panel10may further include: a pixel define layer113.FIG.17is a top view of the pixel define layer according to an embodiment of the present disclosure. Referring toFIG.17, the pixel define layer113may have a plurality of sixth via holes113aand a plurality of seventh via holes113b.

In the embodiment of the present disclosure, an orthographic projection of the sixth via hole113aon the base substrate101may be covered by an orthographic projection of the first light-emitting layer103on the base substrate101, and the first light-emitting layer103may be in contact with the first anode layer102via the sixth via hole113a.

The pixel define layer113may be disposed on a side, distal from the base substrate101, of the first anode layer102. The first anode layer102includes a plurality of anode patterns1021. Each sixth via hole113ain the pixel define layer113may be configured to expose part of one anode pattern1021of the first anode layer102. In addition, the light-emitting layer pattern1031of the first light-emitting layer103may be disposed in the sixth via hole113a. Therefore, the light-emitting layer pattern1031of the first light-emitting layer103contacts with the anode pattern1021of the first anode layer102, thereby ensuring that the second sub-pixel b2 disposed in the first display region101acan normally emit light.

In addition, an orthographic projection of the seventh via hole113bon the base substrate101may be covered by an orthographic projection of the second light-emitting layer107on the base substrate101, and the second light-emitting layer107may be in contact with the second anode layer106via the seventh via hole113b.

The pixel define layer113may be disposed on a side, distal from the base substrate101, of the second anode layer106. The second anode layer106includes a plurality of anode patterns1061. Each seventh via hole113bin the pixel define layer113may expose part of one anode pattern1061of the second anode layer106. In addition, the light-emitting layer pattern1071of the second light-emitting layer107may be disposed in the seventh via hole113b, to enable contact between the light-emitting layer pattern1071of the second light-emitting layer107and the anode pattern1061of the second anode layer106, thereby ensuring that the first sub-pixel b1 disposed in the second display region101bcan normally emit light.

Referring toFIG.17, the pixel define layer113may further have a plurality of eighth via holes113c. A third overlapping region may be between an orthographic projection of the eighth via hole113con the base substrate101and the orthographic projection of the first via hole110aon the base substrate101. A ratio of an area of the third overlapping region to the area of the orthographic projection of the first via hole110aon the base substrate101may be greater than or equal to 80%.

The pixel define layer113is disposed between the first overcoat110and the third cathode layer108, such that in response to the pixel define layer113being formed, the pixel define layer113will cover the first via hole110ain the first overcoat110. Thus, by disposing the eighth via holes113cin the pixel define layer113, the third overlapping region being between the orthographic projection of the eighth via hole113con the base substrate101and the orthographic projection of the first via hole110aon the base substrate101, the first connecting portion10811of the first cathode pattern1081of the third cathode layer108may be disposed in the eighth via hole113cand the first via hole110afor electrical connection between the second cathode layer105and the third cathode layer108.

Referring toFIG.17, the pixel define layer113may further have a plurality of ninth via holes113d. An orthographic projection of the ninth via hole113don the base substrate101may be within the orthographic projection of the first signal transmission layer109on the base substrate101. The first cathode layer104may be electrically connected to the first signal transmission layer109via the ninth via hole113d.

In the embodiment of the present disclosure, referring toFIG.17, the ninth via holes113dmay connect with each other. That is, the ninth via holes113dare not a plurality of isolated through holes.

The pixel define layer113is disposed between the first signal transmission layer109and the first cathode layer104, such that in response to the pixel define layer113being formed, the pixel define layer113will cover the first signal transmission layer109. That is, the power supply signal received by the first signal transmission layer109may not be transmitted to the first cathode layer104. Thus, by disposing the ninth via holes113din the pixel define layer113, the orthographic projection of the ninth via hole113don the base substrate101being within the orthographic projection of the first signal transmission layer109on the base substrate101, the first cathode layer104and the first signal transmission layer109can be connected via the ninth via hole113d, thus enabling signal transmission.

In the embodiment of the present disclosure, in order to illustrate respective via holes in the pixel define layer113, the via holes are indicated by filling patterns inFIG.17. Other regions with no filling patterns indicate the regions that the pixel define layer113made of a solid material.

FIG.18is a schematic structural diagram of yet another display panel according to an embodiment of the present disclosure. Referring toFIG.18, the display panel10may further include: a third overcoat114disposed on a side, proximal to the base substrate101, of the second cathode layer105.

FIG.19is a top view of the first anode layer, the second anode layer, and the first signal transmission layer according to an embodiment of the present disclosure. Referring toFIG.19, the first signal transmission layer109may have a tenth via hole109a(not shown inFIG.18), and the tenth via hole109aof the first signal transmission layer109may expose the third overcoat114. In addition, the tenth via hole109amay be filled with the pixel define layer113on a side, distal from the base substrate101, of the first signal transmission layer109.

Optionally, in combination withFIG.9,FIG.12, andFIG.19, in the tenth via holes109a, there is at least one of the tenth via holes109aof which an orthographic projection on the base substrate101is within the orthographic projection of the joint1051of the second cathode layer105on the base substrate101. In addition, an area of the orthographic projection of the tenth via hole109aon the base substrate101is smaller than an area of the orthographic projection of the joint1051of the second cathode layer105on the base substrate101.

Exemplarily, the second cathode layer105inFIG.9andFIG.12includes three joints1051. The orthographic projection of each joint1051on the base substrate101may cover the orthographic projection of one tenth via hole109aon the base substrate101.

Besides, a boundary of the tenth via hole109amay not overlap with a boundary of the joint1051. Thus, an orthographic projection of the second connecting portion1091on the base substrate101may surround the orthographic projection of the tenth via hole109aon the base substrate101. That is, the orthographic projection of the second connecting portion1091on the base substrate101may be a ring-shaped structure.

Referring toFIG.20, the third cathode layer108in the display panel10according to the embodiment of the present disclosure may further include: a plurality of second cathode patterns1082spaced apart. An orthographic projection of the second cathode patterns1082on the base substrate101may not overlap with the orthographic projection of the light-emitting region of the first sub-pixel b1 on the base substrate101. For example, the second cathode pattern1082is closer to the routing region101cthan the first cathode pattern1081.

Due to the orthographic projection of the second cathode pattern1082on the base substrate101being not overlapped with the orthographic projection of the light-emitting region of the first sub-pixel b1 on the base substrate101, the region that the second cathode pattern1082being disposed cannot emit light normally. An orthographic projection of a first-type second cathode pattern in the second cathode patterns1082on the base substrate101may be completely within the orthographic projection of the first signal transmission layer109on the base substrate101. An orthographic projection of a second-type second cathode pattern on the base substrate101is only partially within the orthographic projection of the first signal transmission layer109on the base substrate101. The first-type second cathode pattern is closer to the routing region101cthan the second-type second cathode pattern.

In the embodiment of the present disclosure, an orthographic projection of the part of the second-type second cathode pattern that is not overlapped with the first signal transmission layer109on the base substrate101may cover the orthographic projection of the joint1051of the second cathode layer105on the base substrate101. In this way, a transmittance of the region of the display panel10other than the regions where the second-type second cathode pattern and the joint1051are disposed is high, and the imaging effect of a camera is ensured.

The orthographic projection of the part of the second-type second cathode pattern that is not overlapped with the first signal transmission layer109on the base substrate101may not overlap with the orthographic projection of the joint1051of the second cathode layer105on the base substrate101. That is, the second-type second cathode pattern and the joint1051may be disposed in different regions. In this way, the impact on transmittance uniformity of respective regions of the display panel10due to part of the display panel10having a low transmittance and another part having a high transmittance may be avoided.

In the embodiment of the present disclosure, referring toFIG.18, the display panel10may further include: a first hole transport layer115and a first electron transport layer116disposed in the first display region101a, and a second hole transport layer117and a second electron transport layer118disposed in the second display region101b.

FIG.21is a top view of the first hole transport layer and the second hole transport layer according to an embodiment of the present disclosure. Referring toFIG.21, the first hole transport layer115may have a plate structure. The second hole transport layer117may include a plurality of hole transport patterns1171spaced apart.

In the embodiment of the present disclosure, a shape and size of the first electron transport layer116may be the same as the shape and size of the first hole transport layer115. For example, the shape of the first electron transport layer116may refer to the shape of the first hole transport layer115inFIG.21. The first electron transport layer116may have a plate structure. In addition, a shape and size of the second electron transport layer118may be the same as the shape and size of the second hole transport layer117. For example, the shape of the second electron transport layer118may refer to the shape of the second hole transport layer117inFIG.21. The second electron transport layer118may include a plurality of electron transport patterns1181spaced apart.

In the embodiment of the present disclosure, an area of the hole transport pattern1171and an area of the electron transport pattern1181are both smaller than an area of the first cathode pattern1081.

The second hole transport layer117and the second electron transport layer118are both disposed between the second cathode layer105and the third cathode layer108(the second cathode layer105being disposed on a side, proximal to the base substrate101, of the second hole transport layer117and the second electron transport layer118, and the third cathode layer108being disposed on a side, distal from the base substrate101, of the second hole transport layer117and the second electron transport layer118), and the second hole transport layer117and the second electron transport layer118are generally poor in conductivity.

Because of the area of the hole transport pattern1171and the area of the electron transport pattern1181being both smaller than the area of the first cathode pattern1081, the first cathode pattern1081of the third cathode layer108includes a target part that is not overlapped with the hole transport pattern1171and the electron transport pattern1181. Thus, the target part of the first cathode pattern1081may be connected to the second cathode layer105on a side, proximal to the base substrate101, of the hole transport pattern1171and the electron transport pattern1181.

Referring toFIG.20, an orthographic projection of the hole transport pattern1171on the base substrate101may cover the orthographic projection of the light-emitting region b11 of the first sub-pixel b1 on the base substrate101, and an orthographic projection of the electron transport pattern1181on the base substrate101may cover the orthographic projection of the light-emitting region b11 of the first sub-pixel b1 on the base substrate101. In addition, because of the first cathode pattern1081being connected to the second cathode layer105via the first connecting portion10811, the orthographic projection of the hole transport pattern1171on the base substrate101and the orthographic projection of the electron transport pattern1181on the base substrate101are required to not overlap with the orthographic projection of the first connecting portion10811on the base substrate101.

In the embodiment of the present disclosure, in addition to the anode pattern1061, the light-emitting layer pattern1071, and the first cathode pattern1081, the first sub-pixel may further include: at least part of the hole transport pattern1171and at least part of the electron transport pattern1181, Optionally, four first sub-pixels may share one hole transport pattern1171and one electron transport pattern1181.

In addition, the anode pattern of the first anode layer102, one light-emitting layer pattern corresponding to the first light-emitting layer103, the first cathode layer104, the first hole transport layer115, and the first electron transport layer116may form one second sub-pixel. That is, a plurality of second sub-pixels disposed in the first display region101amay share the first cathode layer104, the first hole transport layer115, and the first electron transport layer116.

Referring toFIG.18, the display panel10may further include: a first hole injection layer119and a first electron injection layer120disposed in the first display region101a, and a second hole injection layer120and a second electron injection layer122disposed in the second display region101b.

Each of the first hole injection layer119and the second hole injection layer121may include a plurality of hole injection patterns spaced apart. In addition, the first hole injection layer119and the second hole injection layer121may be prepared by using a fine metal mask (FMM). Each of the first electron injection layer120and the second electron injection layer122may include a plurality of electron injection patterns spaced apart. In addition, the first electron injection layer120and the second electron injection layer122may be prepared by using the FMM.

In the embodiment of the present disclosure, the first sub-pixel may further include: a hole injection pattern of the second hole injection layer121, and an electron injection pattern of the second electron injection layer122. The second sub-pixel may further include: a hole injection pattern of the first hole injection layer119and an electron injection pattern of the first electron injection layer120.

Optionally, four first sub-pixels may share one hole injection pattern of the second hole injection layer121and one electron injection pattern of the second electron injection layer122. Four second sub-pixels may share one hole injection pattern of the first hole injection layer119and one electron injection pattern of the first electron injection layer120.

Referring toFIG.18, the display panel10may further include: a barrier layer123, a buffer layer124, a poly layer125, a first gate insulator (GI) layer126, a first gate (G) layer127, a second GI layer128, a second G layer129, an inter-layer dielectric (ILD) layer130, and a source-drain electrode layer131. The source-drain electrode layer131may include a source (S) electrode and a drain (D) electrode.

In summary, the embodiment of the present disclosure provides the display panel. A plurality of first cathode patterns of a third cathode layer included in the display panel are spaced apart, such that the first cathode patterns will not entirely cover a second display region. In comparison with the cathode layer entirely covering the second display region, the impact on a light transmittance is effectively reduced, and the imaging effect of a camera disposed in the second display region is enhanced.

FIG.22is a flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure. This method is for manufacturing the display panel according to the foregoing embodiment. Referring toFIG.22, the method may include the following processes.

In201, a second cathode layer is formed on a side of a base substrate.

In the embodiment of the present disclosure, when the display panel10is prepared, referring toFIG.9, the second cathode layer105may be formed on a side of the base substrate101at first. The base substrate101may be a flexible substrate. For example, the base substrate101may be made of polyimide (PI). The second cathode layer105may be made of a transparent conductive material, such as ITO.

In202, a first overcoat is formed on a side, distal from the base substrate, of the second cathode layer.

In the embodiment of the present disclosure, referring toFIG.23andFIG.24, the first overcoat110may be formed on a side, distal from the base substrate101, of the second cathode layer105. The first overcoat110may have a plurality of first via holes110aand a plurality of second via holes110b.

In203, a second signal transmission layer is formed on a side, distal from the base substrate, of the first overcoat.

In the embodiment of the present disclosure, referring toFIG.25toFIG.27, the second signal transmission layer III may be formed on a side, distal from the base substrate101, of the first overcoat110. The second signal transmission layer Ill includes: a transmission trace1111, a first transmission pattern1112, and a second transmission pattern1113. The transmission trace1111is configured to connect a pixel circuit and an anode pattern1061of a second anode layer106disposed in a second display region101b. The first transmission pattern1112may be disposed in the first via hole110a, and the second transmission pattern1113may be disposed in the second via hole110b.

In204, a second overcoat is formed on a side, distal from the base substrate, of the second signal transmission layer.

In the embodiment of the present disclosure, referring toFIG.28toFIG.30, the second overcoat112may be formed on a side, distal from the base substrate101, of the second signal transmission layer111. The second overcoat112may have a plurality of third via holes112a, a plurality of fourth via holes112b, and a plurality of fifth via holes112c. The third via hole112amay expose the first transmission pattern1112disposed in the first via hole110a. The fourth via hole112bmay expose the second transmission pattern1113disposed in the second via hole110b. The fifth via hole112amay expose the transmission trace1111.

In205, a first anode layer, a second anode layer, and a first signal transmission layer are formed on a side, distal from the base substrate, of the second overcoat.

In the embodiment of the present disclosure, referring toFIG.31toFIG.33, the first anode layer102, the second anode layer106, and the first signal transmission layer109may be formed on a side, distal from the base substrate101, of the second overcoat112by a same patterning process. The first anode layer102may be disposed in a first display region101aof the base substrate101, the second anode layer106may be disposed in the second display region101bof the base substrate101, and the first signal transmission layer109may be disposed in the routing region101c.

Referring toFIG.31, the anode pattern1061of the second anode layer106includes a third connecting portion10611, and the third connecting portion10611may be disposed in the fifth via hole112cof the second overcoat112. The second connecting portion1091of the first signal transmission layer109may be disposed in the fourth via hole112bof the second overcoat112and the second via hole110bof the first overcoat110, and is connected to the second transmission pattern1113in the second via hole110b.

In206, a pixel define layer is formed on a side, distal from the base substrate, of the first anode layer, the second anode layer, and the first signal transmission layer.

In the embodiment of the present disclosure, referring toFIG.34toFIG.36, the pixel define layer113may be formed on a side, distal from the base substrate101, of the first anode layer102, the second anode layer106, and the first signal transmission layer109. The pixel define layer113may have a plurality of sixth via holes113a, a plurality of seventh via holes113b, a plurality of eighth via holes113c, and a plurality of ninth via holes113d. The sixth via hole113a, the seventh via hole113b, and the eighth via hole113care shown inFIG.34, and the ninth via hole113dis not shown inFIG.34.

The sixth via hole113amay expose part of the anode pattern1021of the first anode layer102. The seventh via hole113bmay expose part of the anode pattern1061of the second anode layer106. The eighth via hole113cmay be in communication with the third via hole112aand the first via hole110aand expose the first transmission pattern1112.

In207, a first hole injection layer, a first hole transport layer, a first light-emitting layer, a first electron transport layer, and a first electron injection layer are formed in a first display region, and a second hole injection layer, a second hole transport layer, a second light-emitting layer, a second electron transport layer, and a second electron injection layer are formed in a second display region.

In the embodiment of the present disclosure, referring toFIG.37toFIG.39, the first hole injection layer119and the second hole injection layer121may be disposed in the same layer, and the first hole transport layer115and the second hole transport layer117may be disposed in the same layer. The first light-emitting layer103and the second light-emitting layer109may be disposed in the same layer, the first electron transport layer116and the second electron transport layer118may be disposed in the same layer, and the first electron injection layer120and the second electron injection layer122may be disposed in the same layer.

That is, the first hole injection layer119and the second hole injection layer121may be prepared by a same patterning process. The first hole transport layer115and the second hole transport layer117may be prepared by a same patterning process. The first light-emitting layer103and the second light-emitting layer109may be prepared by a same patterning process. The first electron transport layer116and the second electron transport layer118may be prepared by a same patterning process. The first electron injection layer120and the second electron injection layer122may be prepared by a same patterning process.

In the embodiment of the present disclosure, each the first hole injection layer119and the second hole injection layer121may include a plurality of hole injection patterns spaced apart. In addition, the first hole injection layer119and the second hole injection layer121may be prepared by using an FMM. Each of the first electron injection layer120and the second electron injection layer122may include a plurality of electron injection patterns spaced apart. In addition, the first electron injection layer120and the second electron injection layer122may be prepared by using the FMM.

The first hole transport layer115and the first electron transport layer116may have a plate structure. The second hole transport layer117may include a plurality of hole transport patterns1171. The second electron transport layer118may include a plurality of electron transport patterns1181.

An orthographic projection of the hole transport pattern1171on the base substrate101covers an orthographic projection of a light-emitting region b11 of a first sub-pixel b1 disposed in the second display region101bon the base substrate101, and an orthographic projection of the electron transport pattern1181on the base substrate101covers the orthographic projection of the light-emitting region b11 of the first sub-pixel b1 disposed in the second display region101bon the base substrate101. In addition, the orthographic projection of the hole transport pattern1171on the base substrate101is not overlapped with an orthographic projection of the eighth via hole113cin the pixel define layer113on the base substrate101, and the orthographic projection of the electron transport pattern1181on the base substrate101is not overlapped with the orthographic projection of the eighth via hole113cin the pixel define layer113on the base substrate101.

In208, a first cathode layer is formed in the first display region, and a third cathode layer is formed in the second display region.

In the embodiment of the present disclosure, referring toFIG.10,FIG.12, andFIG.40, the first cathode layer104and the third cathode layer108may be disposed in the same layer. That is, the first cathode layer104and the third cathode layer108may be prepared by a same patterning process.

The first cathode layer104may be connected to the first signal transmission layer109disposed in the routing region101cvia the ninth via hole113din the pixel define layer113. The third cathode layer108includes a plurality of first cathode patterns1081spaced apart. A first connecting portion10811of the first cathode pattern1081may be disposed in the eighth via hole113c, the third via hole112a, and the first via hole110a, and connected to the first transmission pattern1112in the first via hole110a.

In the embodiment of the present disclosure, prior to step201, the method for manufacturing a display panel may further include: sequentially forming a barrier layer123, a buffer layer124, a poly layer125, a first gate insulator layer126, a first gate layer127, a second gate insulator layer128, a second gate layer129, an inter-layer dielectric layer130, a source-drain electrode layer131, and a third overcoat114on a side distal from the base substrate101.

In summary, the embodiment of the present disclosure provides the method for preparing a display panel. A plurality of first cathode patterns of a third cathode layer of the display panel prepared by the preparing method are spaced apart, such that the first cathode patterns will not entirely cover the second display region. In comparison with the cathode layer entirely covering the second display region, the impact on a light transmittance is effectively reduced, and the imaging effect of a camera disposed in the second display region is enhanced.

FIG.41is a schematic structural diagram of a display device according to an embodiment of the present disclosure. Referring toFIG.41, the display device may include: an image sensor30and the display panel10according to the above embodiment. The image sensor30may be disposed on a side, distal from the second anode layer106, of the base substrate101in the display panel10and disposed in the second display region101bof the base substrate101. The image sensor30may be a front camera of the display device, and configured to capture an image.

Optionally, the display device may be any product or component with a display function, such as an OLED display device, a liquid crystal display device, electronic paper, a mobile phone, a tablet, a television, a monitor, a laptop, a digital photo frame or a navigator.

Described above are merely exemplary embodiments of the present disclosure, and are not intended to limit the present disclosure. Within the spirit and principles of the present disclosure, any modifications, equivalent substitutions, improvements, and the like are within the protection scope of the present disclosure.