Patent ID: 12236976

DETAILED DESCRIPTION OF THE INVENTION

FIG.1shows a block diagram illustrating a voice activity detection (VAD) system100according to one embodiment of the present invention. In the embodiment, the VAD system100may be an analog system that operates on analog signals.

The VAD system100of the embodiment may include an amplifier11coupled to receive a sound signal converted from sound by a converter such as a microphone10, and configured to generate an amplified signal according to the sound signal. In the embodiment, the amplifier11may be a low-noise amplifier (LNA) capable of amplifying a low-power signal (e.g., the sound signal) without substantially degrading a signal-to-noise ratio (SNR).

The VAD system100of the embodiment may include an acoustic feature extraction (AFE) circuit12coupled to receive the amplified signal, and configured to generate a feature signal representing a feature extracted from the amplified signal.

The VAD system100of the embodiment may include a classifier13configured to identify the feature signal as a voice or a noise. In one embodiment, the classifier13may include an (analog) neural network circuit.

In one embodiment, the VAD system100may further include a buffer14, such as a unit-gain buffer, disposed between the amplifier11and the AFE circuit12, and configured to provide electrical impedance transformation from the amplifier11to the AFE circuit12, such that the amplified signal may not be affected by the AFE circuit12(i.e., the load).

FIG.2shows a detailed block diagram illustrating the acoustic feature extraction (AFE) circuit12ofFIG.1. In the embodiment, the AFE circuit12may include a plurality of band-pass filters (BPFs)121adaptable to a plurality of channels (three channels are exemplified here) with different band-pass frequency ranges respectively (e.g., 95-195 Hz, 150-310 Hz and 250-500 Hz), thereby generating corresponding filtered signals. Specifically, the band-pass filters121are switchably coupled to receive the amplified signal (from the amplifier11). According to one aspect of the embodiment, the amplified signal is time-division demultiplexed onto the BPFs121in different phases (e.g., phase1through phase3via phase switches P1-P3respectively).

The AFE circuit12of the embodiment may include a rectifier122switchably coupled to receive the filtered signals, which are time-division multiplexed onto the rectifier122in different phases (e.g., via phase switches P1-P3respectively), thereby generating a rectified signal. Therefore, a single rectifier122is needed for all the channels.

The AFE circuit12of the embodiment may include a plurality of low-pass filters (LPFs)123adaptable to the plurality of channels with the same low-pass frequency range (e.g., having a cut-off frequency of 30 Hz), thereby generating corresponding feature signals (e.g., 1st feature signal through 3rd feature signal as exemplified inFIG.2). Specifically, the low-pass filters123are switchably coupled to receive the rectified signal (from the rectifier122). The rectified signal is time-division demultiplexed onto the LPFs123in different phases (e.g., phase1through phase3via phase switches P1-P3respectively).

FIG.3Ashows a circuit diagram illustrating a BPF121ofFIG.2for one channel (e.g., channel1), andFIG.3Bshows a timing diagram illustrating time periods of corresponding phase. In the embodiment, each phase is divided into a first period (e.g., Φ1) and a second period (e.g., Φ2). For example, the first period Φ1lies in the first half of the phase signal P1, and the second period Φ2follows the first period first period Φ1until the beginning of the next phase signal P1.

In the embodiment, the BPF121may include a switched-capacitor (SC) circuit. Specifically, the BPF121may include an operational amplifier1211with a negative input node, a positive input node (connected to earth) and an output node. According to one aspect of the embodiment, a single operational amplifier1211may be shared among the channels in a time-division demultiplexing manner, thereby substantially reducing power consumption and circuit area.

The BPF121may include a first charge capacitor CR1with a first end switchably coupled to receive the amplified signal via a first period switch Φ1that is closed in the first period, and with a second end connected to earth. The BPF121may include a first filter capacitor CC1with a first end switchably connected to (the first end of) the first charge capacitor CR1via a second period switch Φ2that is closed in the second period, and with a second end switchably connected to the negative input node (of the operational amplifier1211) via a phase switch P1that is closed in a corresponding phase. The BPF121may include a second filter capacitor CC2with a first end connected to (the first end of) the first filter capacitor CC1, and with a second end switchably connected to the output node of the operational amplifier1211via another phase switch P1. The BPF121may include a second charge capacitor CR2with a first end switchably connected to the second end of the first filter capacitor CC1via another first period switch Φ1and switchably connected to the second end of the second filter capacitor CC2via another second period switch Φ2, and with a second end connected to earth.

According to another aspect of the embodiment, the BPF121may include a first stabilizing capacitor CL1with a first end switchably connected to the negative input node of the operational amplifier1211via the phase switch P1, and with a second end connected to earth. The first stabilizing capacitor CL1is configured to solve floating voltage issue at the interconnect node between the first filter capacitor CC1and the first stabilizing capacitor CL1in hold state. The BPF121may further include a second stabilizing capacitor CL2with a first end switchably connected to the output node of the operational amplifier1211via said another phase switch P1, and with a second end connected to earth. The second stabilizing capacitor CL2is configured to stabilize the voltage at the output node of the operational amplifier1211in charge state.

FIG.4Ashows a circuit diagram illustrating BPFs121for three channels, andFIG.4Bshows a timing diagram illustrating time periods of corresponding phases. It is noted that a single operational amplifier1211may be shared among the channels in a time-division demultiplexing manner.

FIG.5Ashows equivalent circuits of the BPFs121in the first period Φ1of the first phase P1, in which the BPF121of channel1is in charge state, the BPF121of channel2is in hold state, and the BPF121of channel3is in hold state.FIG.5Bshows equivalent circuits of the BPFs121in the second period Φ2of the first phase P1, in which the BPF121of channel1is in filter state, the BPF121of channel2is in hold state, and the BPF121of channel3is in hold state.FIG.5Cshows equivalent circuits of the BPFs121in the first period Φ3of the second phase P2, in which the BPF121of channel1is in rectifier state, the BPF121of channel2is in charge state, and the BPF121of channel3is in hold state.FIG.5Dshows a table illustrating states of the BPFs121in corresponding periods and phases. It is noted that the operational amplifier1211is utilized in charge and filter states, while the rectifier122is utilized in rectifier state.

FIG.6shows a circuit diagram illustrating the rectifier122ofFIG.2. In the embodiment, the rectifier122may include an operational amplifier1221with a positive input node coupled to receive the filtered signal, and with a negative input node coupled to receive a common-mode voltage VCM, thereby generating a switch signal Φ C. The filtered signal is switchably transferred via a first switch that is controlled by the switch signal Φ C, and the common-mode voltage VCM is switchably transferred via a second switch that is controlled by an inverted switch signal ΦC\. Accordingly, one of the filtered signal and the common-mode voltage VCM is transferred as the rectified signal, thereby resulting in a half-wave rectifier. In an alternative embodiment, the rectifier122may be implemented by a full-wave rectifier instead.

FIG.7shows a circuit diagram illustrating a LPF123for one channel. In the embodiment, the LPF123may include a switched-capacitor (SC) circuit. Specifically, the LPF123may include an operational amplifier1231with a negative input node, a positive input node (connected to earth) and an output node. The operational amplifier1231may act as a buffer or driving stage, and may be omitted when buffering or driving is not required. The LPF123may include a first charge capacitor CR1with a first end switchably coupled to receive the rectified signal via a first period switch Φ1that is closed in the first period, and with a second end connected to earth. The LPF123may include a filter capacitor CC1with a first end switchably connected to (the first end of) the first charge capacitor CR1via a second period switch Φ2that is closed in the second period, and with a second end connected to the output node (of the operational amplifier1231). The BPF121may include a second charge capacitor CR2with a first end switchably connected to the negative input node of the operational amplifier1231via another first period switch Φ1and switchably connected to the second end of the filter capacitor CC1via another second period switch Φ2, and with a second end connected to earth.

Although specific embodiments have been illustrated and described, it will be appreciated by those skilled in the art that various modifications may be made without departing from the scope of the present invention, which is intended to be limited solely by the appended claims.