Patent ID: 12199148

DETAILED DESCRIPTION

Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which the example embodiments are shown. The embodiments may, however, be implemented in many different forms and should not be construed as limited to the specific examples set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. Like numbers refer to like elements throughout, and prime notation is used to indicate similar elements in different embodiments.

Generally speaking, the present disclosure relates to the formation of semiconductor devices utilizing an enhanced semiconductor superlattice. The enhanced semiconductor superlattice may also be referred to as an “MST” layer/film or “MST technology” in this disclosure.

More particularly, the MST technology relates to advanced semiconductor materials such as the superlattice25described further below. Applicant theorizes, without wishing to be bound thereto, that certain superlattices as described herein reduce the effective mass of charge carriers and that this thereby leads to higher charge carrier mobility. Effective mass is described with various definitions in the literature. As a measure of the improvement in effective mass Applicant's use a “conductivity reciprocal effective mass tensor”, Me−1and Mh−1for electrons and holes respectively, defined as:

Me,ij-1(EF,T)=∑E>EF∫B.Z.(∇kE⁡(k,n))i⁢(∇kE⁡(k,n))j⁢∂F⁡(E⁡(k,n),EF,T)∂E⁢d3⁢k∑E>EF∫B.Z.f⁡(E⁡(k,n),EF,T)⁢d3⁢k
for electrons and:

Mi,ij-1(EF,T)=-∑E<EF∫B.Z.(∇kE⁡(k,n))i⁢(∇kE⁡(k,n))j⁢∂F⁡(E⁡(k,n),EF,T)∂E⁢d3⁢k∑E<EF∫B.Z.(1-f⁡(E⁡(k,n),EF,T))⁢d3⁢k
for holes, where f is the Fermi-Dirac distribution, EFis the Fermi energy, T is the temperature, E(k,n) is the energy of an electron in the state corresponding to wave vector k and the nthenergy band, the indices i and j refer to Cartesian coordinates x, y and z, the integrals are taken over the Brillouin zone (B.Z.), and the summations are taken over bands with energies above and below the Fermi energy for electrons and holes respectively.

Applicant's definition of the conductivity reciprocal effective mass tensor is such that a tensorial component of the conductivity of the material is greater for greater values of the corresponding component of the conductivity reciprocal effective mass tensor. Again, Applicant theorizes without wishing to be bound thereto that the superlattices described herein set the values of the conductivity reciprocal effective mass tensor so as to enhance the conductive properties of the material, such as typically for a preferred direction of charge carrier transport. The inverse of the appropriate tensor element is referred to as the conductivity effective mass. In other words, to characterize semiconductor material structures, the conductivity effective mass for electrons/holes as described above and calculated in the direction of intended carrier transport is used to distinguish improved materials.

Applicant has identified improved materials or structures for use in semiconductor devices. More specifically, Applicant has identified materials or structures having energy band structures for which the appropriate conductivity effective masses for electrons and/or holes are substantially less than the corresponding values for silicon. In addition to the enhanced mobility characteristics of these structures, they may also be formed or used in such a manner that they provide piezoelectric, pyroelectric, and/or ferroelectric properties that are advantageous for use in a variety of different types of devices, as will be discussed further below.

Referring now toFIGS.1and2, the materials or structures are in the form of a superlattice25whose structure is controlled at the atomic or molecular level and may be formed using known techniques of atomic or molecular layer deposition. The superlattice25includes a plurality of layer groups45a-45narranged in stacked relation, as perhaps best understood with specific reference to the schematic cross-sectional view ofFIG.1.

Each group of layers45a-45nof the superlattice25illustratively includes a plurality of stacked base semiconductor monolayers46defining a respective base semiconductor portion46a-46nand an energy band-modifying layer50thereon. The energy band-modifying layers50are indicated by stippling inFIG.1for clarity of illustration.

The energy band-modifying layer50illustratively includes one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. By “constrained within a crystal lattice of adjacent base semiconductor portions” it is meant that at least some semiconductor atoms from opposing base semiconductor portions46a-46nare chemically bound together through the non-semiconductor monolayer50therebetween, as seen inFIG.2. Generally speaking, this configuration is made possible by controlling the amount of non-semiconductor material that is deposited on semiconductor portions46a-46nthrough atomic layer deposition techniques so that not all (i.e., less than full or 100% coverage) of the available semiconductor bonding sites are populated with bonds to non-semiconductor atoms, as will be discussed further below. Thus, as further monolayers46of semiconductor material are deposited on or over a non-semiconductor monolayer50, the newly deposited semiconductor atoms will populate the remaining vacant bonding sites of the semiconductor atoms below the non-semiconductor monolayer.

In other embodiments, more than one such non-semiconductor monolayer may be possible. It should be noted that reference herein to a non-semiconductor or semiconductor monolayer means that the material used for the monolayer would be a non-semiconductor or semiconductor if formed in bulk. That is, a single monolayer of a material, such as silicon, may not necessarily exhibit the same properties that it would if formed in bulk or in a relatively thick layer, as will be appreciated by those skilled in the art.

Applicant theorizes without wishing to be bound thereto that energy band-modifying layers50and adjacent base semiconductor portions46a-46ncause the superlattice25to have a lower appropriate conductivity effective mass for the charge carriers in the parallel layer direction than would otherwise be present. Considered another way, this parallel direction is orthogonal to the stacking direction. The band modifying layers50may also cause the superlattice25to have a common energy band structure, while also advantageously functioning as an insulator between layers or regions vertically above and below the superlattice.

Moreover, this superlattice structure may also advantageously act as a barrier to dopant and/or material diffusion between layers vertically above and below the superlattice25. These properties may thus advantageously allow the superlattice25to provide an interface for high-K dielectrics which not only reduces diffusion of the high-K material into the channel region, but which may also advantageously reduce unwanted scattering effects and improve device mobility, as will be appreciated by those skilled in the art.

It is also theorized that semiconductor devices including the superlattice25may enjoy a higher charge carrier mobility based upon the lower conductivity effective mass than would otherwise be present. In some embodiments, and as a result of the band engineering achieved by the present invention, the superlattice25may further have a substantially direct energy bandgap that may be particularly advantageous for opto-electronic devices, for example.

The superlattice25also illustratively includes a cap layer52on an upper layer group45n. The cap layer52may comprise a plurality of base semiconductor monolayers46. By way of example, the cap layer52may have between 1 to 100 monolayers46of the base semiconductor, and, more preferably between 10 to 50 monolayers. However, in some applications the cap layer52may be omitted, or thicknesses greater than 100 monolayers may be used.

Each base semiconductor portion46a-46nmay comprise a base semiconductor selected from the group consisting of Group IV semiconductors, Group III-V semiconductors, and Group II-VI semiconductors. Of course, the term Group IV semiconductors also includes Group IV-IV semiconductors, as will be appreciated by those skilled in the art. More particularly, the base semiconductor may comprise at least one of silicon and germanium, for example.

Each energy band-modifying layer50may comprise a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, carbon and carbon-oxygen, for example. The non-semiconductor is also desirably thermally stable through deposition of a next layer to thereby facilitate manufacturing. In other embodiments, the non-semiconductor may be another inorganic or organic element or compound that is compatible with the given semiconductor processing as will be appreciated by those skilled in the art. More particularly, the base semiconductor may comprise at least one of silicon and germanium, for example.

It should be noted that the term monolayer is meant to include a single atomic layer and also a single molecular layer. It is also noted that the energy band-modifying layer50provided by a single monolayer is also meant to include a monolayer wherein not all of the possible sites are occupied (i.e., there is less than full or 100% coverage). For example, with particular reference to the atomic diagram ofFIG.2, a 4/1 repeating structure is illustrated for silicon as the base semiconductor material, and oxygen as the energy band-modifying material. Only half of the possible sites for oxygen are occupied in the illustrated example.

In other embodiments and/or with different materials this one-half occupation would not necessarily be the case as will be appreciated by those skilled in the art. Indeed, it can be seen even in this schematic diagram, that individual atoms of oxygen in a given monolayer are not precisely aligned along a flat plane as will also be appreciated by those of skill in the art of atomic deposition. By way of example, a preferred occupation range is from about one-eighth to one-half of the possible oxygen sites being full, although other numbers may be used in certain embodiments.

Silicon and oxygen are currently widely used in conventional semiconductor processing, and, hence, manufacturers will be readily able to use these materials as described herein. Atomic or monolayer deposition is also now widely used. Accordingly, semiconductor devices incorporating the superlattice25in accordance with the invention may be readily adopted and implemented, as will be appreciated by those skilled in the art.

It is theorized without Applicant wishing to be bound thereto that for a superlattice, such as the Si/O superlattice, for example, that the number of silicon monolayers should desirably be seven or less so that the energy band of the superlattice is common or relatively uniform throughout to achieve the desired advantages. The 4/1 repeating structure shown inFIGS.1and2, for Si/O has been modeled to indicate an enhanced mobility for electrons and holes in the X direction. For example, the calculated conductivity effective mass for electrons (isotropic for bulk silicon) is 0.26 and for the 4/1 SiO superlattice in the X direction it is 0.12 resulting in a ratio of 0.46. Similarly, the calculation for holes yields values of 0.36 for bulk silicon and 0.16 for the 4/1 Si/O superlattice resulting in a ratio of 0.44.

While such a directionally preferential feature may be desired in certain semiconductor devices, other devices may benefit from a more uniform increase in mobility in any direction parallel to the groups of layers. It may also be beneficial to have an increased mobility for both electrons and holes, or just one of these types of charge carriers as will be appreciated by those skilled in the art.

The lower conductivity effective mass for the 4/1 Si/O embodiment of the superlattice25may be less than two-thirds the conductivity effective mass than would otherwise occur, and this applies for both electrons and holes. Of course, the superlattice25may further comprise at least one type of conductivity dopant therein, as will also be appreciated by those skilled in the art.

Indeed, referring now additionally toFIG.3, another embodiment of a superlattice25′ in accordance with the invention having different properties is now described. In this embodiment, a repeating pattern of 3/1/5/1 is illustrated. More particularly, the lowest base semiconductor portion46a′ has three monolayers, and the second lowest base semiconductor portion46b′ has five monolayers. This pattern repeats throughout the superlattice25′. The energy band-modifying layers50′ may each include a single monolayer. For such a superlattice25′ including Si/O, the enhancement of charge carrier mobility is independent of orientation in the plane of the layers. Those other elements ofFIG.3not specifically mentioned are similar to those discussed above with reference toFIG.1and need no further discussion herein.

In some device embodiments, all of the base semiconductor portions of a superlattice may be a same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions may be a different number of monolayers thick. In still other embodiments, all of the base semiconductor portions may be a different number of monolayers thick.

InFIGS.4A-4C, band structures calculated using Density Functional Theory (DFT) are presented. It is well known in the art that DFT underestimates the absolute value of the bandgap. Hence all bands above the gap may be shifted by an appropriate “scissors correction.” However, the shape of the band is known to be much more reliable. The vertical energy axes should be interpreted in this light.

FIG.4Ashows the calculated band structure from the gamma point (G) for both bulk silicon (represented by continuous lines) and for the 4/1 Si/O superlattice25shown inFIG.1(represented by dotted lines). The directions refer to the unit cell of the 4/1 Si/O structure and not to the conventional unit cell of Si, although the (001) direction in the figure does correspond to the (001) direction of the conventional unit cell of Si, and, hence, shows the expected location of the Si conduction band minimum. The (100) and (010) directions in the figure correspond to the (110) and (−110) directions of the conventional Si unit cell. Those skilled in the art will appreciate that the bands of Si on the figure are folded to represent them on the appropriate reciprocal lattice directions for the 4/1 Si/O structure.

It can be seen that the conduction band minimum for the 4/1 Si/O structure is located at the gamma point in contrast to bulk silicon (Si), whereas the valence band minimum occurs at the edge of the Brillouin zone in the (001) direction which we refer to as the Z point. One may also note the greater curvature of the conduction band minimum for the 4/1 Si/O structure compared to the curvature of the conduction band minimum for Si owing to the band splitting due to the perturbation introduced by the additional oxygen layer.

FIG.4Bshows the calculated band structure from the Z point for both bulk silicon (continuous lines) and for the 4/1 Si/O superlattice25(dotted lines). This figure illustrates the enhanced curvature of the valence band in the (100) direction.

FIG.4Cshows the calculated band structure from both the gamma and Z point for both bulk silicon (continuous lines) and for the 5/1/3/1 Si/O structure of the superlattice25′ ofFIG.3(dotted lines). Due to the symmetry of the 5/1/3/1 Si/O structure, the calculated band structures in the (100) and (010) directions are equivalent. Thus, the conductivity effective mass and mobility are expected to be isotropic in the plane parallel to the layers, i.e. perpendicular to the (001) stacking direction. Note that in the 5/1/3/1 Si/O example the conduction band minimum and the valence band maximum are both at or close to the Z point.

Although increased curvature is an indication of reduced effective mass, the appropriate comparison and discrimination may be made via the conductivity reciprocal effective mass tensor calculation. This leads Applicant to further theorize that the 5/1/3/1 superlattice25′ should be substantially direct bandgap. As will be understood by those skilled in the art, the appropriate matrix element for optical transition is another indicator of the distinction between direct and indirect bandgap behavior.

Turning now toFIG.5, in some embodiments the above-described superlattice films 25 may be fabricated with one or more oxygen monolayers50which have an increased or enhanced amount of18O. In a typical fabrication process, the approximate concentration of stable oxygen isotopes present in the gas flow used for oxygen deposition may be as follows:

IsotopeMass (Da)[%]16O15.9949299.75717O16.999130.03818O17.999160.205

In the semiconductor device120shown inFIG.5, a superlattice125is formed adjacent a semiconductor layer121(e.g., substrate) which includes two groups of monolayers145a,145b, each including a base semiconductor portion146a,146bwith four semiconductor (e.g., silicon) monolayers146, and a respective oxygen monolayer150a,150b. However, it should be noted that other base semiconductor portion thicknesses may be used in different embodiments, e.g., up to twenty-five monolayers146or even fifty monolayers (or more) in some implementations. While the oxygen monolayer150bis fabricated using a typical gas flow, the oxygen monolayer150ais fabricated using a gas flow having an enhanced or increased amount of18O to thereby provide an18O enriched monolayer. By way of example, the monolayer150amay comprise an atomic percentage of18O greater than ten percent. That is, the number of18O atoms present in the monolayer150amay constitute 10% or more of the total oxygen atoms in this monolayer(s). In other example embodiments, the atomic percentage of18O atoms in the monolayer150amay be greater than fifty percent of the total oxygen atoms, and more particularly greater than ninety percent. In any case, the18O enriched monolayer150amay also include some portion of16O.

Referring additionally to the semiconductor device120′ ofFIG.6, in some implementations more than one18O enriched monolayer150a′ may be used. Here, each of the two groups of layers145a′,145b′ has a respective18O enriched monolayer150a′. Other superlattice layer configurations may also be used in different embodiments.

The use of one or more18O enriched monolayers150ain an MST layer may be advantageous in view of the kinetic isotope effect of interstitial oxygen within the semiconductor (e.g., silicon) lattice of the base semiconductor portions146a,146b. More particularly, free oxygen atoms in silicon are relatively highly mobile, which may lead to unwanted diffusion via an interstitial mechanism. Diffusion of oxygen is thermally activated, and is therefore susceptible to occur in subsequent thermal processing steps (e.g., gate formation, etc.) after the superlattice125formation. Because18O is chemically equivalent to16O in terms of its nuclear spin (both are 0), it is well suited for use in the above-described superlattice structures where oxygen monolayers with typical16O concentrations would otherwise be used. However, as a result of the kinetic isotope effect, activation energy for a lighter isotope is less than for a heavier isotope. In the present example,16O is a lighter isotope than18O, meaning that18O will have a higher activation energy than16O. Thus, activated processes for18O are accordingly slower, meaning that18O will diffuse more slowly than16O. As a result, and as theorized by Applicant without wishing to be bound thereto,18O enriched monolayers150awill experience less diffusion/oxygen loss during the above-noted thermal processing, for example.

The foregoing will be further understood with reference to the graph170ofFIG.7, table180ofFIG.8, and graphs190,195ofFIGS.9and10representing test results from a fabricated device including four16O monolayers and four18O enriched monolayers. The test device was fabricated using an etch-back procedure (referred to as “MEGA” in the figures) during fabrication that is described further in U.S. Pat. Nos. 10,566,191 and 10,811,498 to Weeks et al., which are assigned to the present Applicant and hereby incorporated herein in their entireties by reference. The18O concentration is represented by the plot line171, while the16O concentration is represented by the plotline172. It may be seen that the location of the oxygen monolayer150aoccurs between 20 and 30 nm from the surface and has an18O concentration in a range of 1×1021atoms/cm3. The corresponding measurements for the test film are shown in the table180ofFIG.8, the corresponding dose loss vs. anneal temperature is shown in the graph190, and the corresponding dose loss percentage vs. anneal temperature is shown in the graph195ofFIG.10.

Numerous types of semiconductor structures may be fabricated with, and benefit from, the above-described18O enhanced superlattices120or120′. One such device is a planar MOSFET220now described with reference toFIG.11. The illustrated MOSFET220includes a substrate221, source/drain regions222,223, source/drain extensions226,227, and a channel region therebetween provided by an18O enhanced superlattice225. The channel may be formed partially or completely within the superlattice225. Source/drain silicide layers230,231and source/drain contacts232,233overlie the source/drain regions as will be appreciated by those skilled in the art. Regions indicated by dashed lines234a,234bare optional vestigial portions formed originally with the superlattice225, but thereafter heavily doped. In other embodiments, these vestigial superlattice regions234a,234bmay not be present as will also be appreciated by those skilled in the art. A gate235illustratively includes a gate insulating layer237adjacent the channel provided by the superlattice225, and a gate electrode layer236on the gate insulating layer. Sidewall spacers240,241are also provided in the illustrated MOSFET220.

Referring additionally toFIG.12, in accordance with another example of a device in which an18O enriched superlattice325may be incorporated is a semiconductor device300, in which the superlattice is used as a dopant diffusion blocking superlattice to advantageously increase surface dopant concentration to allow a higher ND(active dopant concentration at metal/semiconductor interface) during in-situ doped epitaxial processing by preventing diffusion into a channel region330of the device. More particularly, the device100illustratively includes a semiconductor layer or substrate301, and spaced apart source and drain regions302,303formed in the semiconductor layer with the channel region330extending therebetween. The dopant diffusion blocking superlattice325illustratively extends through the source region302to divide the source region into a lower source region304and an upper source region305, and also extends through the drain region303to divide the drain region into a lower drain region306and an upper drain region307.

The dopant diffusion blocking superlattice325may also conceptually be considered as a source dopant blocking superlattice within the source region302, a drain dopant blocking superlattice within the drain region303, and a body dopant blocking superlattice beneath the channel330, although in this configuration all three of these are provided by a single blanket deposition of the MST material across the substrate301as a continuous film. The semiconductor material above the dopant blocking superlattice325in which the upper source/drain regions305,307and channel region330are defined may be epitaxially grown on the dopant blocking superlattice325either as a thick superlattice cap layer or bulk semiconductor layer, for example. In the illustrated example, the upper source/drain regions305,307may each be level with an upper surface of this semiconductor layer (i.e., they are implanted within this layer).

As such, the upper source/drain regions305,307may advantageously have a same conductivity as the lower source/drain regions304,306, yet with a higher dopant concentration. In the illustrated example, the upper source/drain regions305,307and the lower source/drain regions304,306are N-type for a N-channel device, but these regions may also be P-type for a P-channel device as well. Surface dopant may be introduced by ion implantation, for example. Yet, the dopant diffusion is reduced by the MST film material of the diffusion blocking superlattice325because it traps point defects/interstitials introduced by ion implantation which mediate dopant diffusion.

The semiconductor device300further illustratively includes a gate308on the channel region330. The gate illustratively includes a gate insulating layer309gate electrode310. Sidewall spacers311are also provided in the illustrated example. Further details regarding the device300, as well as other similar structures in which an18O enriched superlattice may be used, are set forth in U.S. Pat. No. 10,818,755 to Takeuchi et al., which is assigned to the present Applicant and hereby incorporated herein in its entirety by reference.

Turning toFIG.13, another example embodiment of a semiconductor device400in which an18O enriched superlattice may be used is now described. More particularly, in the illustrated example both source and drain dopant diffusion blocking superlattices425s,425dadvantageously provide for Schottky barrier height modulation via hetero-epitaxial film integration. More particularly, the lower source and drain regions404,406include a different material than the upper source and drain regions405,407. In this example, the lower source and drain regions404,406are silicon, and the upper source and drain regions405,407are SiGeC, although different materials may be used in different embodiments. Lower metal layers (Ti)442,443are formed on the upper source and drain regions (SiGeC layers)405,407. Upper metal layers (Co)444,445are formed on the lower metal layers442,443, respectively. Because the MST material is effective in integrating hetero-epitaxial semiconductor material, incorporation of C(1-2%) to Si or SiGe on Si may induce a positive conduction band offset. More particularly, this is a SiGeC/MST/n+Si structure that is effective for reducing Schottky barrier height. Further details regarding the device400are set forth in the above-noted '755 patent.

One skilled in the art, however, will appreciate that the materials and techniques identified herein may be used in many different types of semiconductor devices, such as discrete devices and/or integrated circuits. Referring again toFIG.6, in the context of dopant blocking applications, the18O enriched superlattice125′ divides the substrate121′ and the cap layer52′, but the substrate has a different conductivity type (P) than the cap layer (N) to thereby define a PN junction. In other example embodiments, the PN junction may be lateral, as opposed to vertically oriented as shown in the example ofFIG.6. Further PN junction applications in which18O enriched superlattice may be used are set forth in U.S. Pat. No. 7,227,174 to Mears et al., which is assigned to the present Applicant and hereby incorporated herein in its entirety by reference. It should also be noted that in some embodiments,18O enriched monolayers may also be incorporated in superlattices and associated applications such as those described in co-pending application Ser. Nos. 17/236,289 and 17/236,329 filed Apr. 21, 2021, which are hereby incorporated herein in their entireties by reference.

Applicant theorizes, without wishing to be bound thereto, that an18O source can be used interchangeably with traditional16O sources to fabricate the above-described semiconductor superlattices. Moreover, Applicant has found that similar18O flow rates yield similar oxygen dosages to those of16O. Furthermore, the semiconductor monolayer growth and etch rates are also similar between16O and18O sources. Phenomenological study/observations have revealed that16O incorporation in the18O superlattice layers is affected by the above-described MEGA etch. More particularly, with respect to the test device represented inFIG.7, implementations of the device without the MEGA etch showed the first16O to be lower than the other three16O peaks in the same stack, whereas adding a MEGA etch before the first oxygen dosing cycle resulted in a superlattice stack with all four16O peaks being of the same concentration. By way of example,18O dose retention may be 30% better (or more) than16O dose retention.

A related method for making a semiconductor device120may include forming a semiconductor layer121, and forming a superlattice125adjacent the semiconductor layer and including stacked groups of layers145a,145b. Each group of layers145a,145bmay include stacked base semiconductor monolayers146defining a base semiconductor portion146a,146b, and at least one oxygen monolayer150aconstrained within a crystal lattice of adjacent base semiconductor portions. The at least one oxygen monolayer150amay comprise an atomic percentage of18O greater than 10 percent, as discussed further above.

In accordance with the example ofFIG.11, further method aspects may include forming source and drain regions222,223on the semiconductor layer221and defining a channel in the superlattice225, and forming a gate235above the superlattice. In accordance with the example ofFIG.13, further method aspects may include forming a metal layer442/444and/or443/445above the superlattice425s,425d, as discussed further above.

Many modifications and other embodiments of the invention will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is understood that the invention is not to be limited to the specific embodiments disclosed, and that modifications and embodiments are intended to be included within the scope of the appended claims.