Patent ID: 12199025

DETAILED DESCRIPTION

The present invention will now be described in greater detail by referring to the following discussion and drawings that accompany the present invention. It is noted that the drawings of the present invention are provided for illustrative purposes only and, as such, the drawings are not drawn to scale. It is also noted that like and corresponding elements are referred to by like reference numerals.

In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiments of the present invention. However, it will be appreciated by one of ordinary skill in the art that the various embodiments of the present invention may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present invention.

It will be understood that when an element as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “beneath” or “under” another element, it can be directly beneath or under the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly beneath” or “directly under” another element, there are no intervening elements present.

As stated above, the present invention provides an interposer structure100such as is shown inFIG.1, which can be used in semiconductor packaging to electrically connect a printed circuit board to a plurality of die. The inventive interposer structure100shown inFIG.1includes a silicon-less link chiplet102having a first interconnect density laterally surrounded by, and embedded in, a redistribution layer (RDL) interposer110having a second interconnect density that is less than the first interconnect density. That is, and in the present invention, the amount of first interconnect structures (per unit volume) present in the silicon-less link chiplet102is greater than the amount of interconnect structures (per unit volume) present in the redistribution layer interposer110. In one embodiment of the present invention, the first interconnect density is10× greater than the second interconnect density. In yet another embodiment of the present invention, the first interconnect density is100× greater than the second interconnect density. Although the present invention describes and illustrates a single silicon-less link chiplet102within the interposer structure100, the present invention contemplates embodiments in which a plurality of silicon-less link chiplets102are present in the interposer structure100; in such embodiments each silicon-less link chiplet102is laterally surrounded, and embedded within, the redistribution layer interposer110.

In the present invention and within a semiconductor package device containing a plurality of die, the silicon-less link chiplet102provides high inter-die connection between two adjacent die of the plurality of die. Also, and within the same semiconductor package device, the redistribution layer interposer110that laterally surrounds the silicon-less link chiplet102provides connection to one of the die of the plurality of die. These aspects of the present invention will become more apparent when viewing the semiconductor packaging device shown inFIGS.2-6of the present invention.

The silicon-less link chiplet102comprises a first multilevel structure (104/106) including a plurality of first electrically conductive structures106(i.e., first interconnect structure) and a plurality of interconnect dielectric material layers104. In accordance with the present invention, the first electrically conductive structures106are embedded in the plurality of interconnect dielectric material layers104. The first electrically conductive structures106can include any combination of via structures and/or line (trench) structures. The first electrically conductive structures106can be composed of an electrically conductive metal or an electrically conductive metal alloy. Examples of electrically conductive metals that can provide the first electrically conductive structures106include, but are not limited to, copper (Cu), aluminum (Al), tungsten (W) or cobalt (Co). An example of an electrically conductive metal alloy that can provide the first electrically conductive structures106is a Cu—Al alloy. In one embodiment, each first electrically conductive structure106can be composed of a compositionally same electrically conductive material (i.e., electrically conductive metal or electrically conductive metal alloy). In another embodiment, each first electrically conductive structure106can be composed of a compositionally different electrically conductive material. In yet a further embodiment, a first set of first electrically conductive structures106can be composed of a first electrically conductive material, while a second set of first electrically conductive structures106can be composed of a second electrically conductive material that is compositionally different from the first electrically conductive material. Other variations for the compositionally make-up of the first electrically conductive structures106are possible in the present invention.

Although not shown, a diffusion barrier liner can be located on at least the sidewalls of the first electrically conductive structures106. The diffusion barrier liner can be composed of a diffusion material such as, for example, titanium (Ti), tantalum (Ta), titanium nitride (TiN) or tantalum nitride (TaN).

Each interconnect dielectric material layer of the plurality of interconnect dielectric material layers104that provides the silicon-less link chiplet102includes any interlevel dielectric material (inorganic or organic) that does not solely contain elemental silicon. Examples of interlevel dielectric materials that can be used as the interconnect dielectric material layer of the plurality of interconnect dielectric material layers104include, but are not limited to, undoped or doped silicate glass, silsesquioxanes, C doped oxides (i.e., organosilicates) that include atoms of Si, C, O and H, theremosetting polyarylene ethers or any multilayered combination thereof. In one embodiment, each of the interconnect dielectric material layers of the plurality of interconnect dielectric material layers104can be composed of a compositionally same interlevel dielectric material. In another embodiment, each of the interconnect dielectric material layers of the plurality of interconnect dielectric material layers104can be composed of a compositionally different interlevel dielectric material. In yet a further embodiment, a first set of interconnect dielectric material layers of the plurality of interconnect dielectric material layers104can be composed of first interlevel dielectric material, while a second set of interconnect dielectric material layers of the plurality of interconnect dielectric material layers104can be composed of second interlevel dielectric material that is compositionally different from the first interconnect dielectric material. Other variations for the compositionally make-up of the interconnect dielectric material layers of the plurality of interconnect dielectric material layers104are possible in the present invention.

In some embodiments (not shown inFIG.1), a dielectric capping layer can be present between the interconnect dielectric material layers of the plurality of interconnect dielectric material layers104When present, the dielectric capping layer may include any dielectric material such as, for example, silicon carbide (SiC), silicon nitride (Si3N4), silicon dioxide (SiO2), a carbon doped oxide, a nitrogen and hydrogen doped silicon carbide (SiC(N,H)) or a multilayered stack of at least one of the aforementioned dielectric capping materials.

The redistribution layer interposer110comprises a second multilevel structure that includes a plurality of second electrically conductive structures114(i.e., second interconnect structures) and a plurality of redistribution dielectric material layers112. In accordance with the present invention, the second electrically conductive structures114are embedded in the plurality of redistribution dielectric material layers112. The second electrically conductive structures114are typically metal lines. The second electrically conductive structures114can be composed of one of the electrically conductive metals or metal alloys that provide the first electrically conductive structure106; the electrically conductive material that provides the second electrically conductive structures can be compositionally the same as, or compositionally different from, the electrically conductive material that provides the first electrically conductive structures106In some embodiments, each second electrically conductive structures114can be composed of a compositionally same, or compositionally different electrical conductive material. In yet a further embodiment, a first set of second electrically conductive structures114can be composed of a first electrically conductive material, while a second set of second electrically conductive structures114can be composed of a second electrically conductive material that is compositionally different from the first electrically conductive material. Other variations for the compositionally make-up of the second electrically conductive structures are possible in the present invention.

Although not shown, a diffusion barrier liner can be located on at least the sidewalls of the second electrically conductive structures114. The diffusion barrier liner can be composed of a diffusion material such as, for example, titanium (Ti), tantalum (Ta), titanium nitride (TiN) or tantalum nitride (TaN).

Each redistribution dielectric material layer of the plurality of redistribution dielectric material layers112that provides redistribution layer interposer110is composed of an organic dielectric material. In one example, each redistribution dielectric material layer112is composed of a polyimide. The organic dielectric material that provides the redistribution dielectric material layer of the plurality of redistribution dielectric material layers112can be compositionally the same as, or compositionally different from, the dielectric material that provides the interconnect dielectric material layers104. Each redistribution dielectric material layer of the plurality of redistribution dielectric material layers112can be composed of a compositionally same, or compositionally different, organic dielectric material. In some instances, a first set of redistribution dielectric material layers of the plurality of redistribution dielectric material layers112can be composed of first organic dielectric material, while a second set of redistribution dielectric material layers of the plurality of redistribution dielectric material layers112can be composed of second organic dielectric material that is compositionally different from the first dielectric material. Other variations for the compositionally make-up of the redistribution dielectric material layers of the plurality of redistribution dielectric material layers112are possible in the present invention.

As is shown inFIG.1, a first portion of the redistribution layer interposer110is laterally adjacent to a first sidewall of the silicon-less link chiplet102and a second portion of the redistribution layer interposer110is laterally adjacent to a second sidewall of the silicon-less link chiplet102. The first and second portions of the redistribution layer interposer110are connected by a bridging portion that lies on (and thus embeds) the silicon-less link chiplet102. The first and second portions of the redistribution layer interposer110contain second electrically conductive structures114, while the bridging portion does not contain any second electrically conductive structure114.

FIG.1also shows interposer metallic pads116located on the redistribution layer interposer110that contains the second electrically conductive structures114. Each interposer metallic pad116is in direct physical contact with one of the second electrically conductive structures114. The interposer metallic pads116can be composed of Cu or any other conductive pad material. The interposer metallic pads116can be formed utilizing techniques well known to those skilled in the art.

FIG.1further shows micro metallic pads109embedded in, and located on, the bridging portion of the redistribution layer interposer110. Each micro metallic pad109contacts a pad structure108that is present in the silicon-less link chip. Each micro metallic pad109and pad structure108can be composed of Cu or any other conductive pad material. The pad structures108and micro pads109can be formed utilizing techniques well known to those skilled in the art.

Referring now toFIGS.2-6, there are shown various semiconductor packaging devices in accordance with various embodiments of the present invention and each including the interposer structure100ofFIG.1. Notably, each ofFIGS.2-6illustrates a semiconductor packaging device including an interposer structure100in accordance with the present invention electrically connecting a printed circuit board200to a plurality of die (D1, Dnwherein n is an integer greater than 1). As mentioned above in regard toFIG.1, interposer structure100includes a silicon-less link chiplet102having a first interconnect density laterally surrounded by, and embedded in, a redistribution layer interposer110having a second interconnect density that is less than the first interconnect density. Within the various embodiments shown inFIGS.2-6, the silicon-less link chiplet102provides inter-die connection between two adjacent die, e.g., D1, Dn, of the plurality of die (D1, Dn), while the redistribution layer interposer110surrounding the silicon-less link chiplet102provides a connection to one of the die (e.g., D1, or Dn) of the plurality of die (D1, Dn).

Printed circuit board (PCB)200includes at least one insulating material such as, for example, fiberglass or a glass-reinforced plastic, with conductive traces (e.g., copper traces) present in the at least one insulating material. PCB200may be single-layered or multilayered. PCB200can be made utilizing techniques well known to those skilled in the art.

Each die, e.g., D1, Dn, of the plurality of die (D1, Dn) is a small block of semiconductor material on which a given functional circuit is fabricated. Each die, e.g., D1, Dn, of the plurality of die (D1, Dn) includes materials well known to those skilled in the art, and the dies can be fabricated utilizing techniques well known to those skilled in the art. For example, integrated circuits are typically formed in large batches on a single semiconductor wafer through well known processes including, for example, photolithography. The wafer is then cut (i.e., diced) into many pieces (i.e., the dies), each containing a copy of the circuit.

Referring to the specific embodiment depicted inFIG.2(which represent a first embodiment of the present invention), the illustrated semiconductor packaging device ofFIG.2further includes organic substrate204positioned between the interposer structure100and the PCB200. The organic substrate204is optionally and can be omitted in some embodiments of the present invention. When present, the organic substrate204can be composed of a polymeric material such as, for example, a polyimide. The organic substrate204can act as an electrically conductive interconnect between the PCB200and the die, e.g., D1, Dn, of the plurality of die (D1, Dn). The organic substrate204also provides mechanical and environmental protection to the semiconductor packaging device, and the organic substrate204can also facilitate heat distribution, signal distribution and power distribution.

When present, a first surface of the organic substrate204is electrically attached to the PCB200by an array of solder balls202(commonly referred to as a ball grid array or BGA for short). The solder balls202are composed of any well known solder material used in semiconductor packaging devices, and solder balls202are formed utilizing techniques that are also well known to one skilled in the art. In one example, the solder balls202are lead-free solder balls formed utilizing a BGA solder forming process.

The second surface of the organic substrate204, which is opposite to the first surface of the organic substrate204, is electrically attached to the interposer structure100by another array of solder balls206. The another array of solder balls206can be composed of any well known solder material and can be formed utilizing techniques well known to those skilled art. In one example, the solder balls206are composed of a lead-tin alloy or a lead-free alloy and the solder balls206are formed utilizing a controlled collapse chip connection (C4) process. As is shown, some of the solder balls206are formed on a physically exposed surface of the second electrically conductive structures114that are present in the redistribution layer interposer110, while other solder balls206are formed on a physically exposed surface of the first electrically conductive structures106that are present in the silicon-less link chiplet102. Solder balls206are typically smaller in diameter than solder balls202.

The semiconductor packaging device ofFIG.2also includes an underfill material containing region205that laterally surrounds, and can be positioned above and below, the interposer structure100of the present invention. As is shown, the underfill material containing region205also encases solder balls206, exposed portions of the interposer metallic pads116and micro metallic pads109, and interposer metallic pillars210and micro metallic pillar214(pads116and pillars210electrically connect the redistribution layer interposer110to an overlying die of the plurality, while pads109and pillars214electrically connect the silicon-less link chiplet102to a neighboring pair of die of the plurality of die). The interposer metallic pillars210and micro metallic pillar214are composed of any well known conductive pillar material including, for example, copper. The interposer metallic pillars210and micro metallic pillar214can be formed utilizing techniques well known in the art.

Underfill material containing region205is composed of at least one resin having a coefficient of thermal expansion (CTE) that substantially matches (i.e., within ±10%) the CTE of the solder balls206. In one example, the resin that provides the underfill material containing region205is composed of a composite containing an epoxy polymer and a filler. The underfill material containing region205can be formed by depositing the resin and thereafter subjecting the deposited resin to a curing process. The underfill material containing region205acts as a cushion between the various components that are present in the underfill material containing region205, and also protects the solder joints provided by solder balls206. When the organic substrate204is present, the underfill material containing region205contacts the second surface of the organic substrate204. In some embodiments, the underfill material containing region205is optional.

The semiconductor packaging device shown inFIG.2further includes an epoxy molding compound containing layer216that laterally surrounds the plurality of die, and contacts a surface of the redistribution layer interposer110. The epoxy molding compound containing layer216protects the integrated circuits that are present in each die from moisture, heat and shock. The epoxy molding compound containing layer216can be composed of any well known material including for example, a composite of an epoxy resin, hardener, silica and additives. The epoxy molding compound containing layer216can be formed by deposition and curing.

The semiconductor packaging device shown inFIG.2further includes an integrated heat spreader218encasing the interposer structure100and the plurality of die (D1, Dn). In this illustrated embodiment, the integrated heat spreader218is located on a topmost surface of the epoxy molding compound containing layer216and a topmost surface of each die of the plurality of die (D1, Dn). The integrated heat spreader218of this embodiment of the present invention has a surface that contacts the second surface of the organic substrate204. In this embodiment, a void220is located between an interior sidewall of the integrated heat spreader218and both the epoxy molding compound containing layer216and the redistribution layer interposer110.

The integrated heat spreader218facilitates the transfer of heat that is generated by the die during operational use. The integrated heat spreader218can be composed of any well known material that is capable of transfer energy as heat from a hotter source to a colder source. Examples of materials that can be employed as the integrated heated spreader218include, but are not limited to, heat conductive metals and alloys, such as Cu, or other heat conductive materials, such as carbon nano-tube or grapheme. The integrated heat spreader218can be formed utilizing techniques well known to those skilled in the art.

Referring now toFIG.3, there is illustrated a semiconductor packaging device in accordance with second embodiment of the present invention. The semiconductor packaging device of the second embodiment of the present invention is similar to the semiconductor packaging device of the first embodiment of the present invention except that no organic substrate204, no array of solder balls202, and integrated heat spreader218are used. In the semiconductor packaging device of the second embodiment of the present invention, the epoxy molding compound containing layer216surrounds the plurality of die, and contacts a topmost surface of the redistribution layer interposer110. Although not shown, an underfill material containing region205can be located beneath the interposer structure100ofFIG.3so as to encase solder balls206.

Referring now toFIG.4, there is illustrated a semiconductor packaging device in accordance with third embodiment of the present invention. The semiconductor packaging device of the third embodiment of the present invention is similar to the semiconductor packaging device of the first embodiment of the present invention except that no organic substrate204and no array of solder balls are used. Also, in the third embodiment, integrated heat spreader218is confined to a topmost surface of the epoxy molding compound containing layer216and each die of the plurality of die (D1, Dn). Although not shown, an underfill material containing region205can be located beneath the interposer structure100ofFIG.4so as to encase solder balls206.

Referring now toFIG.5, there is illustrated a semiconductor packaging device in accordance with fourth embodiment of the present invention. The semiconductor packaging device of the fourth embodiment of the present invention is similar to the semiconductor packaging device of the first embodiment of the present invention except that no organic substrate204, no array of solder balls202, and no integrated heat spreader218are employed. In the semiconductor packaging device of the fourth embodiment of the present invention, the epoxy molding compound containing layer216surrounds the plurality of die and the interposer structure100, and is present on a topmost surface of each die of the plurality of die. As shown in the fourth embodiment of the present, a portion of the epoxy molding compound containing layer216contacts a sidewall of redistribution layer interposer110of the interposer structure100. Although not shown, an underfill material containing region205can be located beneath the interposer structure100ofFIG.5so as to encase solder balls206.

Referring now toFIG.6, there is illustrated a semiconductor packaging device in accordance with fifth embodiment of the present invention. The semiconductor packaging device of the fifth embodiment of the present invention is similar to the semiconductor packaging device of the fourth embodiment of the present invention except that the epoxy molding compound containing layer216only surrounds the plurality of die and the interposer structure100, and an integrated heat spreader218is present on a topmost surface of each die and a topmost surface of the epoxy molding compound containing layer216. Although not shown, an underfill material containing region205can be located beneath the interposer structure100ofFIG.6so as to encase solder balls206.

Referring now toFIGS.7-12, there are illustrated various processing steps that can be used in fabricating a silicon-less link chiplet102of the interposer structure100of the present invention. The process of fabricating the silicon-less link chiplet102begins by providing a supporting wafer300as is shown inFIG.7. Supporting wafer300is composed of any material that is capable of supporting a multilayered interconnect structure. Examples of materials that can be used as the supporting wafer300include, but are not limited to, silicon, glass, sapphire or a ceramic. Next, and as is shown inFIG.8, a buffer layer302is formed on the supporting wafer300. Buffer layer302can be composed of a dielectric material such as, for example, silicon dioxide and/or silicon nitride. Buffer layer302can be formed utilizing any well known deposition process including, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD).

After forming the buffer layer302and as is shown inFIG.9, a lower interconnect level including interconnect dielectric material layer304and electrically conductive structure306is formed; electrically conductive structure306is subsequently used as pad structure in the present invention. This lower interconnect level is formed utilizing a single damascene process in which interconnect dielectric material layer304is deposited and patterned to contain at least one opening The depositing of the interconnect dielectric material layer304includes, but is not limited to, CVD, PECD, evaporation or spin-on coating. The patterning includes photolithographic patterning. The interconnect dielectric material layer304includes any interlevel dielectric material (inorganic or organic) that does not solely contain elemental silicon, as is defined above for the plurality of interconnect dielectric material layers104. The opening is then filled with one of the electrically conductive metals or metal alloys mentioned above for first electrically conductive structures106The filling of the opening with an electrically conductive metal or metal alloy can include any well known deposition process including, for example, CVD, PECD, plating, or sputtering. A planarization process such as, for example, chemical mechanical planarization (CMP), can follow the deposition of the electrically conductive metal or metal alloy. These steps of metal fill and planarization provide electrically conductive structure306.

Next, and as is shown inFIG.10, a dielectric capping layer308is formed on the structure shown inFIG.9(formation of dielectric capping layer308is optional), followed by the formation of a next interconnect level which includes electrically conductive structures312embedded in interconnect dielectric material layer310; the dielectric capping layer308is patterned such that at least one of the electrically conductive structures312is formed in direct physical contact with electrically conductive structure306. The dielectric capping layer308is composed of one of the dielectric capping materials previously mentioned in this disclosure. The dielectric capping layer308can be formed utilizing a deposition process such as, for example, CVP, PECVD, PVD, atomic layer deposition (ALD) or spin-on coating. Next, interconnect dielectric material layer310is formed on the dielectric capping layer308. The interconnect dielectric material layer310can be formed utilizing one of the deposition processes mentioned above for interconnect dielectric material layer304. The interconnect dielectric material layer310includes any interlevel dielectric material that does not solely contain elemental silicon, as is defined above for the plurality of interconnect dielectric material layers104. Openings are then formed into interconnect dielectric material layer310utilizing at least one iteration of photolithographic patterning; during the forming of the opening into the interconnect dielectric material layer310, the dielectric capping layer308is opened so as to physically expose a surface of electrically conductive structure306. The openings are then filled with one of the electrically conductive metals or metal alloys mentioned above for first electrically conductive structures106. The filling of the opening with an electrically conductive metal or metal alloy can include any well known deposition process including, for example, CVD, PECD, plating, or sputtering. A planarization process such as, for example, chemical mechanical planarization (CMP), can follow the deposition of the electrically conductive metal or metal alloy. These steps of metal fill and planarization provide electrically conductive structure312.

Next, and as is shown inFIG.11, another dielectric capping layer314is formed on the structure shown inFIG.10(formation of dielectric capping layer314is also optional), followed by the formation of another interconnect level which includes electrically conductive structures318embedded in interconnect dielectric material layer316. The another dielectric capping layer314is composed of one of the dielectric capping materials previously mentioned in this disclosure. The another dielectric capping layer314can be formed utilizing a deposition process such as, for example, CVP, PECVD, PVD, atomic layer deposition (ALD) or spin-on coating. Next, interconnect dielectric material layer316is formed on the dielectric capping layer308. The interconnect dielectric material layer316can be formed utilizing one of the deposition processes mentioned above for interconnect dielectric material layer304. The interconnect dielectric material layer316includes any interlevel dielectric material (inorganic or organic) that does not solely contain elemental silicon, as is defined above for the plurality of interconnect dielectric material layers104. Openings are then formed into interconnect dielectric material layer316utilizing at least one iteration of photolithographic patterning; during the forming of the opening into the interconnect dielectric material layer316, the another dielectric capping layer314is opened so as to physically expose a surface of electrically conductive structure312. The openings are then filled with one of the electrically conductive metals or metal alloys mentioned above for first electrically conductive structures106. The filling of the opening with an electrically conductive metal or metal alloy can include any well known deposition process including, for example, CVD, PECD, plating, or sputtering. A planarization process such as, for example, chemical mechanical planarization (CMP), can follow the deposition of the electrically conductive metal or metal alloy. These steps of metal fill and planarization provide electrically conductive structure318. It is again noted that dielectric capping layers306and/or314are optional and need not be used in some embodiments of the present invention. For interconnect levels can be formed as appropriate.

Next, and as is shown inFIG.12, a physically exposed surface of the supporting wafer300shown inFIG.11is attached to a dicing tape that is present on a dicing frame of a dicing apparatus. The structure shown inFIG.12is then diced to provide a plurality of silicon-less link chiplets102; note that interconnect dielectric material layers304,310and316together with dielectric capping layers318and314provide the plurality of interconnect dielectric material layers104of the silicon-less link chiplet102, while the electrically conductive structures306,312, and318provide the first electrically conductive structures106of the silicon-less link chiplet102. After dicing the diced chiplets are removed from the dicing tape, and a ready for further processing. At this time of the present invention, the supporting wafer300and buffer layer302remain on a surface of each diced silicon-less link chiplet102. Each silicon-less link chiplet102that is formed has a width from about 0.2 mm to about 30 mm, and a length from about 0.2 mm to about 30 mm; the term “about” denoting that the value can be within ±10% of the given value.

Referring now toFIGS.13-19, there are illustrated the various processing steps used in fabricating the interposer structure100of the present invention. The process of fabricating the interposer structure100begins by forming a temporary bonding layer402on a surface of a handle substrate400as is shown inFIG.13. Handle substrate400is composed of any handler material including, but not limited to, silicon, glass, sapphire or a ceramic. In some embodiments, the handle substrate400can be in the form of a wafer. In other embodiments, the handle substrate400can be in the form of a panel. Temporary bonding layer402can be composed of any adhesive material including, for example, an adhesive tape or adhesive glue. The temporary bonding layer402can be applied to the surface of the handle substrate400utilizing techniques well known to those skilled in the art.

After forming the temporary bonding layer402on the handle substrate400, a multilevel structure is formed that includes the plurality of second electrically conductive structures114, as defined above, and the plurality of redistribution dielectric material layers112, as defined above. As stated above, the second electrically conductive structures114are embedded in the plurality of redistribution dielectric material layers112. The multilevel structure (112/114) can be formed by techniques well known in the art including a damascene process. Element114′ is a last level second electrically conductive structure that can be formed deposition and photolithography.

Next, and as is shown inFIG.15, cavities404are formed through portions of the redistribution dielectric material layers112that do not contain any second electrically conductive structures114. The cavities404, which extend to the underlying temporary bonding layer402, have dimensions (at least length and width) that are suitable for housing a silicon-less link chiplet102. Cavities404can be formed by etching physically exposed portions of the redistribution dielectric material layers112. In some embodiments, an etch mask can be formed prior to the etching so as to ensure proper alignment of the cavities. In some embodiments, and as is also shown inFIG.15, at least one dice opening402can be formed into portions of the redistribution dielectric material layers112. Each dice opening402also extends to the surface of the temporary bonding layer402; dice openings have dimensions that are much smaller than cavities404. The dice openings402can be formed together with, prior to, or after forming, the cavities404. Dice openings402can be formed by etching utilizing an etch mask.

After providing the cavities404and optional dice opening402as is shown inFIG.15, a pick and place method is used to insert one of the diced silicon-less link chiplets102including the supporting wafer300and buffer layer302into each of the cavities404.FIG.16illustrates the structure after performing the pick and place method. As can be seen inFIG.16, each diced silicon-less link chiplet102is inserted face down such that a surface of the diced silicon-less link chiplet102directly contacts the temporary bonding layer402.

Next, and as shown inFIG.17, a gap fill material layer406L is formed. The gap fill material layer406L is formed over the entire structure shown inFIG.16and within any gaps, including the optional dice openings402, that are present in that structure. The gap fill material layer406L is composed of any gap fill material including, for example, inorganic oxides and inorganic nitrides. The gap fill material layer406L can be formed utilizing any known gap filling deposition process such as, for example, CVD or PECVD.

After forming the gap fill material layer406L, a material removal process such as, for example, CMP, is employed to remove all material above electrically conductive structures318and314′. The resultant structure that is formed after performing this material removal process is shown inFIG.18. A portion of the gap fill material layer406L remains after the material removal process. The remaining portion of the gap fill material layer406L can be referred to herein as a gap fill material406.

Next, and as shown inFIG.19, an uppermost redistribution dielectric material layer408is then formed on the exposed surfaces of the structure shown inFIG.18. The uppermost redistribution dielectric material layer408includes one of the dielectric materials mentioned above for the redistribution dielectric material layer112. The uppermost redistribution dielectric material layer408can be formed utilizing one of the deposition processes mentioned above for forming the redistribution dielectric material layer112.

Metallic pads116and micro metallic pads109, as are also shown inFIG.19, can then formed. Metallic pads116and micro metallic pads109can be formed utilizing any well known process including, for example, under bump metallization (UBM). As is shown, each micro metallic pad109directly contacts a surface an underlying electrically conductive structure306, and each metallic pad119directly contacts a surface of the last level second electrically conductive structure114′.

Referring now toFIGS.20-23, there are illustrated processing steps used in assembling a semiconductor packaging device in accordance with the present invention. As shown inFIG.20, the assembly process begins by attaching die (D1, Dn) to the metallic pads116and micro metallic pads109shown inFIG.19. The die (D1, Dn) can be attached to utilizing a flip chip bonding process. Prior to attaching, a pick and place method is used to position the die (D1, Dn) on the appropriate metallic pads116or micro metallic pads109. An underfill material can be formed after the attaching of the die (D1, Dn).

Next, and as is shown inFIG.21, epoxy molding compound containing layer216, as defined above, can then be formed to at least laterally surround each die (D1, Dn). The epoxy molding compound containing layer216can be formed by a deposition process, followed by curing. In some embodiments, a material removal process such as, for example, CMP, can be used to remove the epoxy molding compound containing layer216from atop the die (D1, Dn).

The assembly shown inFIG.21is then flipped 180° degrees and then the flipped assembly is mounted on dicing tape410as is shown inFIG.22. Next, and as shown inFIG.23, the handle substrate400and temporary bonding layer402are removed utilizing techniques well known in the art, and thereafter solder balls206, as described above, are formed on the exposed surface of the second electrically conductive structures114that are embedded in the redistribution dielectric material layer112. After forming the solder balls206, and as is also shown inFIG.23, dicing is performed to form dice openings412in the assembly.

Next, the diced assemblies are removed from the dicing tape410, and the diced assemblies can then be attached to a PCB200. In some embodiments, the diced assemblies are first attached to an organic substrate204prior to attaching to a PCB200.

While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.