Patent ID: 12249390

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over, or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” “top,” “bottom” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In general, a memory system includes a number of memory arrays, and a number of circuits operatively coupled to the memory arrays. Each of the memory arrays can be operated through one or more of the circuits. Conventionally, those memory arrays and the circuits are formed over a single substrate (e.g., wafer), which can encounter various issues as the technology node continues to shrink in dimensions. For example, some of the circuits that operate a memory array may be more speed and power sensitive, which may require those circuits to be fabricated with a more advanced technology node (e.g., smaller in dimensions). However, the memory array itself may require a higher voltage to be successfully programmed or read. Under such a scenario, a trade-off between performance of the operating circuits and yield of the memory array is commonly made, which can disadvantageously drag evolution of the memory system.

In another example, a central circuit typically controls a certain number of memory arrays. Such a central circuit is operatively coupled to those memory arrays via one or more respective conductor structures. With the number of memory arrays integrated onto one wafer becoming larger, a length of those conductor structures can be significantly extended, which may cause various issues such as, for example, increased IR drop, increased RC delay, etc. All of these issues can significantly deteriorate the performance and power consumption of a memory system. Thus, integration of the existing memory system has not been entirely satisfactory in many aspects.

The present disclosure provides various embodiments of systems and methods to form (e.g., integrate) a memory system that includes a number of memory arrays (or sub-arrays) and a number of circuits. As disclosed herein, the memory arrays, together with a number of essential circuits, may be formed on a first substrate or chip (e.g., a wafer); and the remaining circuits may be formed on a second substrate or chip (e.g., a wafer). In various embodiments, these two substrates/chips are vertically disposed from each other (and are thus referred to as a first layer and second layer, respectively), but operatively coupled to each other through a number of interconnect structures. Based on such an integration principle, different layers can be fabricated with respective technology nodes (i.e., free from the above-discussed trade-off issues), which can advantageously improve performance of the disclosed memory system as a whole. Further, following the principle, one or more additional layers can be integrated into the memory system, and in each of these additional layers, a respective type of memory array that may be different from other layer can be formed. As such, the memory system can be built with multiple applications. Still further, by coupling different layers of circuits or memory arrays with the vertical interconnect structures, a length of the interconnect structures can be significantly shorten, which can solve the issues encountered by the laterally integrated memory system. Accordingly, performance and power consumption of the disclosed memory system can be greatly improved.

FIG.1illustrates a block diagram of an example memory system100, in accordance with various embodiments. The memory system100is a storage device configured to be connected to an external host device (not illustrated). It should be appreciated that the memory system100, as shown inFIG.1, is a simplified example, and thus, the memory system100can include any of various other components while remaining within the scope of the present disclosure. In general, the memory system100includes a memory controller102and a memory device104operatively coupled to each other.

The memory controller102is configured with, for example, an integrated circuit such as a system-on-a-chip (SoC) that may include one or more processing circuits, e.g., a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), an Internet-of-Things (IoT) device etc. The memory controller102can control the memory device104based on a request from the host device. For example, the memory controller102writes data requested to be written by the host device, into the memory device104. Further, the memory controller102reads data requested to be read from the host device from the memory device104, and transmits the data to the host device.

The memory device104is a memory that stores data in a non-volatile or volatile manner. The memory device104includes a number of circuits and a number of memory arrays, as will be discussed below. Each of the memory arrays, together with a number of corresponding essential circuits, are formed over a first chip, and the rest of circuits are formed over a second chip that is vertically separated from but operatively coupled to the first chip, in accordance with various embodiments.

The memory controller102and the memory device104are operatively coupled to each other through BUS, which may transmit and/or receive data based on an interface such as, for example, a single data rate (SDR) interface, a toggle double data rate (DDR) interface, an open NAND flash interface (ONFI), among others. As shown, various (e.g., control) signals may be transmitted through the BUS. For example, a command latch enable (CLE) signal, an address latch enable (ALE) signal, a write enable (WEn) signal, a read enable (REn) signal, a ready busy (RBn) signal, and an input and output (I/O) signal. It should be understood that the BUS can transmit/receive any of various other signals while remaining with the scope of the present disclosure.

In brief overview, the CLE and ALE signals are configured to notify the memory device104that the I/O signal to the memory device104are respectively a command and an address. The WEn signal is configured to incorporate the I/O signal into the memory device104. The REn signal is configured to read the I/O signal from the memory device104. The RBn signal is configured to indicate whether the memory device104is in a ready state or a busy state. The ready state is a state in which the memory device104can receive an instruction from the memory controller102. The busy state is a state in which the memory device104cannot receive the instruction from the memory controller102. The I/O signal includes, for example, 8 bits. The I/O signal is data communicated between the memory device104and the memory controller102. The I/O signal includes a command (CMD), an address information (ADD), and data (DAT), in some embodiments.

Referring next to the memory device104of the example inFIG.1, the memory device104includes an I/O circuit106, a logic control circuit108, a command register (circuit)110, an address register (circuit)112, a sequencer (circuit)114, a row decoder (circuit)116, and a sensing amplifier (circuit)118, and a memory array120. Although one memory array is shown, it should be understood that the memory system100can include any number of memory arrays while remaining within the scope of the present disclosure. In at least one aspect of the present disclosure, each memory array120may be fabricated with its row decoder116and sensing amplifier118(which are sometimes referred to as essential circuits of the memory array120) in one of a number of layers (e.g., substrates), while the remaining circuits106to114(which are sometimes referred to as peripheral circuits of the memory array120) and the memory controller102may be fabricated in one or more of other layers.

The memory array120may include a plural number of memory cells, each of the memory cells is configured to store data. For example, the memory array may include a dynamic random-access memory (DRAM) array, a static random-access memory (SRAM) array, a resistive random-access memory (RRAM) array, a magnetoresistive random access memory (MRAM) array, a phase change random access memory (PCRAM) array, etc. Each array has its memory cells arranged in a column-row configuration, allowing each of which to be accessed through one of a number bit lines (e.g., disposed along one of the columns) and one of a number of word lines (e.g., disposed along one of the rows).

The I/O circuit106is configured to communicate the I/O signal with the memory controller102. For example, when the I/O signal is received from the memory controller102, the I/O circuit106can distribute the I/O signal to the CMD, ADD, and DAT based on information received from the logic control circuit108. The I/O circuit106provides the CMD to the command register110and the ADD to the address register112, respectively. Further, the I/O circuit106communicates the DAT with the sensing amplifier118. The logic control circuit108is configured to receive the CLE, ALE, WEn, and Ren signals from the memory controller102. The logic control circuit108can send out the above-mentioned information to the I/O circuit106for identifying the CMD, the ADD, and the DAT in the I/O signal. In addition, the logic control circuit108provides the RBn signal to the memory controller102to notify a state of the memory device104.

The command register110is configured to store the CMD received from the I/O circuit106. The CMD includes, for example, an instruction for causing the sequencer114to execute a read operation, a write operation, an erasing operation, or the like. The address register14is configured to store the address information ADD received from the I/O circuit106. The ADD at least includes, for example, a row address (RAd) and a column address (CAd). The row address RAd and the column address CAd may be used to select a word line and a bit line, respectively. The sequencer114is configured to control an operation of the entire memory device104. For example, the sequencer114can control the row decoder116, the sensing amplifier118, or the like based on the CMD stored in the command register110, and execute a read operation, a write operation, an erasing operation, or the like.

The row decoder116, which may include or be integrated with a driver (circuit), is configured to generate a voltage used in the read operation, the write operation, the erasing operation, or the like. The row decoder116can apply the generated voltage to a corresponding access line (e.g., a word line) based on, for example, the RAd stored in the address register112. For example, one of the word lines may be selected by the row decoder116through three decoding stages: predecode, decode, and postdecode. The predecode stage determines which of a potentially hierarchical set of memory blocks contains the data, and recode address bits to reduce the fanout to the word line decoders of a single block. One or more word line decoders will respond to an address. The postdecode stage can then select a single word line. In some embodiments, the row decoder116can be implemented by a collection of 2Mlogic gates (e.g., NAND gates, NOR gates, etc.) organized in a regular, dense fashion.

The sensing amplifier118may include or be integrated with a column decoder. Accordingly, the sensing amplifier118may sometimes be referred to as a column sensing circuit. The sensing amplifier118is configured to receive a small signal from a selected memory cell and amplify it to a large signal, thereby differentiating a logic state of the data stored in the selected memory cell which may be provided as the DAT. The sensing amplifier118can read out the data from the selected cell that is an the intersection of a word line and bit line based on, for example, the CAd stored in the address register112. For example, during such a read operation, an entire row of data may be temporarily read out of the memory array based on the selected word line (as discussed above). The desired piece of the row of data (e.g., one of the bit lines) is then multiplexed onto the DAT through a column decoder included in or integrated with the sensing amplifier118.

FIG.2illustrates a perspective view of an example portion of a memory system200, which at least includes a first layer201and a second layer202, in accordance with various embodiments. The memory system200may include substantially similar components as the memory system100ofFIG.1. It should be understood that the configuration of memory system200shown inFIG.2is simplified for illustration purposes, and thus, the memory system200can include any of various other layers while remaining within the scope of the present disclosure.

In some embodiments, the first and second layers,201and202, are vertically arranged with respect to each other. Although such two layers,201and202, are shown as being separated from each other in the example ofFIG.2, it should be appreciated that these two layers may be (e.g., operatively and/or physically) coupled to each other through one or more interconnect structures (e.g., through-silicon-vias (TSVs)), which will be discussed below with reference toFIGS.7A-11E. Further, in some embodiments, the first layer201may include a first substrate (or chip) where a number of peripheral circuits of the memory system200are formed (hereinafter “peripheral layer201”); and the second layer202may include a second substrate (or chip) where at least one memory array of the memory system200and a number of its essential circuits are formed (hereinafter “memory array layer202”).

UsingFIG.1as a non-limiting example, the peripheral layer201may include the I/O circuit106, logic control circuit108, command register110, address register112, and sequencer114; and the memory array layer202may include the row decoder116, the sensing amplifier118, and the memory array120. The row decoder116and the sensing amplifier118can abut a first side and a second side of the memory array120, respectively. Further, devices (e.g., transistors) of the circuits on the peripheral layer201may be fabricated with a smaller technology node, while devices (e.g., transistors) of the circuits and memory cells on the memory array layer202may be separately fabricated with a larger technology node. In this way, while keeping high performance (e.g., high speed, low operation voltages, low delay) of certain control circuits of the memory system200, memory cells of the memory system200can still be properly programmed, read, and/or erased.

FIG.3illustrates a perspective view of another example portion of the memory system200, which includes a first layer211, a second layer212, a third layer213, and a fourth layer214, in accordance with various embodiments. The first through fourth layers,211to214, are vertically arranged with respect to each other. Although such four layers are shown as being separated from each other in the example ofFIG.3, it should be appreciated that these layers may be (e.g., operatively and/or physically) coupled to each other through one or more interconnect structures (e.g., through-silicon-vias (TSVs)).

In some embodiments, the first layer211includes a first substrate where a number of peripheral circuits of the memory system200are formed (hereinafter “peripheral layer211”); the second layer202includes a second substrate where at least four memory arrays and their corresponding essential circuits of the memory system200are formed (hereinafter “memory array layer212”); the third layer213includes a third substrate where at least four memory arrays and their corresponding essential circuits of the memory system200are formed (hereinafter “memory array layer213”); and the fourth layer214includes a fourth substrate where at least four memory arrays and their corresponding essential circuits of the memory system200are formed (hereinafter “memory array layer214”).

Similar as the example ofFIG.2, the peripheral layer211can include a number of control circuits (e.g.,106to114) to respectively control the memory arrays120(and their essential circuits,116and118) in the memory array layers212to214. InFIG.3, each of the memory arrays120is abutted to its essential circuits116and118, and neighboring memory arrays (together with their respective essential circuits) in a single memory array layer may be laterally separated from one another. The laterally disposed memory arrays (and their essential circuits) can be operatively coupled to one another through an interposer formed below, for example, the memory arrays. The interposer generally include an interposer substrate and a plurality of redistribution layers (RDLs) formed through at least a portion of the interposer substrate. Further, such a spacing between the neighboring memory arrays (together with their respective essential circuits) may be filled with a dielectric material, as shown inFIG.4A.

Specifically inFIG.4A, memory array120A is abutted to its row decoder116A and sensing amplifier118A; memory array120B is abutted to its row decoder116B and sensing amplifier118B; memory array120C is abutted to its row decoder116C and sensing amplifier118C; and memory array120D is abutted to its row decoder116D and sensing amplifier118D. Between the neighboring memory arrays (120A and120B) and (120C and120D), a dielectric spacer400is disposed; and between the neighboring memory arrays (120A and120C) and (120B and120D), a dielectric spacer420is disposed. Stated another way, a first dielectric spacer (e.g.,400) can be disposed between two neighboring memory arrays, with one side of the dielectric spacer abutted to one or more sensing amplifiers (e.g.,118A,118C) and the other opposite side of the dielectric spacer abutted to one or more memory arrays (e.g.,120B,120D); and a second dielectric spacer (e.g.,420) can be disposed between two neighboring memory arrays, with one side of the dielectric spacer abutted to one or more row decoders (e.g.,116A,116B) and the other opposite side of the dielectric spacer abutted to one or more memory arrays (e.g.,120C,120D). Other configurations of the memory arrays, essential circuits, and dielectric spacers (if any) in one memory array layer can also be implemented, while remaining within the scope of the present disclosure.

In some embodiments, such a dielectric spacer can provide real estate to allow one or more interconnect structures (e.g., TSVs) to pass therethrough. As will be discussed in detail below with reference toFIGS.7A-11E, such TSVs can operatively (e.g., electrically) couple one or more transistors in a peripheral layer to the memory arrays and their essential circuits in one of a number of memory array layer. However, each of these TSVs can be selectively coupled to one or more subsets of the memory array layers, in accordance with various embodiments. As such, some of the TSVs may pass through, but not electrically couple to, one or more of the memory array layers.

FIGS.4B,4C, and4Dillustrate various other configurations between the memory arrays120and their essential circuits116and118in one memory array layer, in accordance with some embodiments. Referring first toFIG.4B, a number of memory arrays, together with their essential circuits, abut to each other without a dielectric spacer disposed therebetween. Specifically, one memory array, with its corresponding essential circuits, directly abut neighboring memory arrays, with their corresponding essential circuits. Referring next toFIG.4C, a number of memory arrays are abutted to one another, without a dielectric spacer or essential circuit disposed therebetween. Specifically, such memory arrays may share global essential circuits. Referring then toFIG.4D, a number of memory arrays abut to each other, without a dielectric spacer but with a shared essential circuit disposed therebetween. Specifically, memory array120A abuts memory array120B, without a dielectric spacer but with a shared essential circuit (sensing amplifier)118A disposed therebetween; memory array120C abuts memory array120D, without a dielectric spacer but with a shared essential circuit (sensing amplifier)118B disposed therebetween; memory array120A abuts memory array120C, without a dielectric spacer but with a shared essential circuit (row decoder)116A disposed therebetween; and memory array120B abuts memory array120D, without a dielectric spacer but with a shared essential circuit (row decoder)116B disposed therebetween.

FIGS.5A,5B, and5Cillustrate perspective views of various other example memory systems500,530, and560, respectively, in accordance with various embodiments. The memory systems500to560may each include substantially similar components as the memory system discussed above, e.g.,100ofFIG.1. It should be understood that the configurations of memory systems500to560shown inFIGS.5A-Care simplified for illustration purposes, and thus, the memory systems500to560can each include any of various other layers while remaining within the scope of the present disclosure.

InFIG.5A, the memory system500includes a peripheral layer502, a first memory array layer504, a second memory array layer506, a third memory array layer508. Each of the memory array layers504to508is operatively coupled to the peripheral layer502, according to various embodiments. It should be appreciated that the memory system500can include any number of memory array layers between any of the memory array layers, or between the peripheral layer and one of the memory array layers, while remaining within the scope of the present disclosure. The peripheral layer502may be vertically disposed below a bottommost one of the memory array layers (e.g.,504). Each of the memory array layers506to508includes a number of memory arrays (120) each of which is abutted to its respective essential circuits (116and118), as configured in the example ofFIG.4B. The memory array layer504includes a number of memory arrays (120), some of which are abutted to each other and share global essential circuits (116and118), as configured in the example ofFIG.4C. As such, different memory array layers may have a similar or different number (or size) of memory arrays, as shown inFIG.5A.

InFIG.5B, the memory system530includes a first memory array layer532, a second memory array layer534, a peripheral layer536, and a third memory array layer538. Each of the memory array layers532-534and538is operatively coupled to the peripheral layer536, according to various embodiments. It should be appreciated that the memory system530can include any number of memory array layers between any of the memory array layers, or between the peripheral layer and one of the memory array layers, while remaining within the scope of the present disclosure. The peripheral layer536may be vertically disposed between the memory array layers534and538. Each of the memory array layers532and534includes a number of memory arrays (120) each of which is abutted to its respective essential circuits (116and118), as configured in the example ofFIG.4B. The memory array layer538includes a number of first sub-chips540(as similarly configured inFIG.4B) laterally separated apart from each other, and a number of second sub-chips542(as similarly configured inFIG.4C) laterally separated apart from each other. Alternatively stated, in any of the memory array layers (e.g.,538), a first number of memory arrays can abut each other (e.g., each of the sub-chips540) and a second number of memory arrays can abut each other (e.g., each of the sub-chips542), wherein the first number can be similar to or different from the second number.

InFIG.5C, the memory system560includes a peripheral layer562, a first memory array layer564, a second memory array layer566, and a third memory array layer568. Each of the memory array layers564to568is operatively coupled to the peripheral layer562, according to various embodiments. It should be appreciated that the memory system560can include any number of memory array layers between any of the memory array layers, or between the peripheral layer and one of the memory array layers, while remaining within the scope of the present disclosure. The peripheral layer562may be vertically disposed below a bottommost one of the memory array layers (e.g.,564). Similar as the layers538ofFIG.5B, each of the memory array layers564to568can include a “mixed” arrangement of sub-chips. For example, the memory array layer564includes a number of first sub-chips570, a number of second sub-chips572, a number of third sub-chips574, and a number of fourth sub-chips576. Each of the sub-chips can be configured in a different number of memory arrays (e.g., different sizes).

FIGS.6A,6B, and6Cillustrate perspective views of various other example memory systems600,630, and660, respectively, in accordance with various embodiments. The memory systems600to660may each include substantially similar components as the memory system discussed above, e.g.,100ofFIG.1. In some embodiments, the memory systems600to660each include different types of memory arrays integrated with one another. It should be understood that the configurations of memory systems600to660shown inFIGS.6A-Care simplified for illustration purposes, and thus, the memory systems600to660can each include any of various other layers while remaining within the scope of the present disclosure.

InFIG.6A, the memory system600includes a controller layer602, a first peripheral layer604, a first memory array layer606, a second peripheral layer608, a second memory array layer610, a third peripheral layer612, and a third memory array layer614. The first memory array layer606may include a number of a first type of memory arrays (e.g., MRAM arrays), the second memory array610may include a number of a second type of memory arrays (e.g., DRAM arrays), and the third memory array layer614may include a number of a third type of memory arrays (e.g., RRAM arrays). According to various embodiments, each of the memory array layers606,610, and614is operatively coupled to and disposed immediately below or above a corresponding one of the peripheral layers604,608, and612. For example, the peripheral layer604, operatively coupled to the MRAM array layer606, is disposed directly therebelow.

Further, the controller layer602can include a memory controller (e.g.,102ofFIG.1). In one aspect of the present disclosure, the controller layer602can be operatively coupled to each of the memory array layers606,610, and614and each of the peripheral layers604,608, and612. In another aspect of the present disclosure, the controller layer602can be operatively coupled to each of the memory array layers606,610, and614or each of the peripheral layers604,608, and612. The controller layer602may be vertically disposed below a bottommost one of the memory array layers or the peripheral layers (e.g.,604).

InFIG.6B, the memory system630includes a controller layer632, a first peripheral layer634, a first memory array layer636, a second peripheral layer638, a second memory array layer640, and a third memory array layer642. The first memory array layer636may include a number of a first type of memory arrays (e.g., DRAM arrays), and the second and third memory arrays640and642may each include a number of a second type of memory arrays (e.g., RRAM arrays). According to various embodiments, each of the memory array layers636,640, and642is operatively coupled to and disposed immediately below or above a corresponding one of the peripheral layers634and638. For example, the peripheral layer638, operatively coupled to the DRAM array layers640and642, is disposed directly thereunder.

Further, the controller layer632can include a memory controller (e.g.,102ofFIG.1). In one aspect of the present disclosure, the controller layer632can be operatively coupled to each of the memory array layers636,640, and642and each of the peripheral layers634and638. In another aspect of the present disclosure, the controller layer632can be operatively coupled to each of the memory array layers636,640, and642or each of the peripheral layers634and638. The controller layer632may be vertically disposed below a bottommost one of the memory array layers or the peripheral layers (e.g.,634).

InFIG.6C, the memory system660includes a controller layer662, a first peripheral layer664, a first memory array layer666, a second peripheral layer668, a second memory array layer670, a third peripheral layer672, and a third memory array layer674. The first memory array layer666may include a number of a first type of memory arrays (e.g., MRAM arrays), the second memory array670may include a number of a second type of memory arrays (e.g., DRAM arrays), and the third memory array layer674may include a number of a third type of memory arrays (e.g., RRAM arrays). According to various embodiments, each of the memory array layers666,670, and674is operatively coupled to and disposed immediately below or above a corresponding one of the peripheral layers664,668, and672. For example, the peripheral layer664, operatively coupled to the MRAM array layer666, is disposed directly thereunder.

Further, the controller layer662can include a memory controller (e.g.,102ofFIG.1). In one aspect of the present disclosure, the controller layer662can be operatively coupled to each of the memory array layers666,670, and674and each of the peripheral layers664,668, and672. In another aspect of the present disclosure, the controller layer662can be operatively coupled to each of the memory array layers666,670, and674or each of the peripheral layers664,668, and672. The controller layer662may be laterally disposed next to a bottommost one of the memory array layers or the peripheral layers (e.g.,664). That is, the controller layer662and the peripheral layer664may be formed over respective different portions of a same substrate/chip.

Although such different types (e.g., functions) of memory arrays are integrated in a vertically stacked manner, it should be understood that different types of memory arrays (or even circuits) can be laterally integrated while remaining within the scope of the present disclosure. The laterally disposed circuits can be operatively coupled to one another through an interposer formed below, for example, the circuits. The interposer generally includes an interposer substrate and a plurality of redistribution layers (RDLs) formed through at least a portion of the interposer substrate.

FIG.7Aillustrates a perspective view of an example memory system700including a number of interconnect structures,720and722, configured to operatively couple one layer to one or more other layers that are vertically integrated (e.g., stacked) on top of one another, in accordance with various embodiments. The memory system700may include substantially similar components as the memory system discussed above, e.g.,100ofFIG.1. It should be understood that the configuration of memory system700shown inFIG.7Ais simplified for illustration purposes, and thus, the memory system700can include any of various other layers and/or have different configurations (e.g., different layers coupled to each other, depending on desired designs, etc.), while remaining within the scope of the present disclosure.

As shown, the memory system700includes a peripheral layer702, a number of memory array layers704,706,708,710,712, and714disposed above the peripheral layer702. According to various embodiments of the present disclosure, the peripheral layer702can be operatively coupled to one or more of the memory array layers704to714through one or more interconnect structures, e.g., TSVs. Alternatively stated, each of the TSVs may be selectively coupled to one or more of the memory array layers704to714. With such a flexibility, (e.g., RC) loading of each of the TSVs can be optimally tuned, which can improve operation speed of the system700as a whole.

For example inFIG.7A, the peripheral layer702is operatively coupled to each of the memory array layers704to714through TSV720, while the peripheral layer702is operatively coupled to the memory array layers706,710, and714(but not to the memory array layers704,708, or712) through TSV722. As further shown inFIG.7B, the memory system700further includes: TSV724operatively coupled to the memory array layers708and714(but not to any other memory array layers); TSV726operatively coupled to the memory array layers706and714(but not to any other memory array layers); TSV728operatively coupled to the memory array layers704and714(but not to any other memory array layers); TSV730operatively coupled to the memory array layers704,708, and712(but not to any other memory array layers); TSV732operatively coupled to the memory array layers706and712(but not to any other memory array layers); and TSV734operatively coupled to the memory array layers704and712(but not to any other memory array layers).

FIG.8illustrates a flowchart of a method800to form a memory system including different layers operatively coupled to each other through TSVs, according to one or more embodiments of the present disclosure. For example, at least some of the operations (or steps) of the method800can be used to form a memory system discussed above. It is noted that the method800is merely an example, and is not intended to limit the present disclosure. Accordingly, it should be understood that additional operations may be provided before, during, and/or after the method800ofFIG.8, and that some other operations may only be briefly described herein. In some embodiments, operations of the method800may be associated with cross-sectional views of an example semiconductor device at various fabrication stages as shown inFIGS.9A,9B,9C,9D, and9E, respectively, which will be discussed in further detail below.

Corresponding to operation802ofFIG.8,FIG.9Aillustrates a cross-sectional view of a portion of a semiconductor device900including a first substrate (or chip)902with a number of TSVs904formed over a front surface of the first substrate902at one of the various stages of fabrication, in accordance with various embodiments.

The first substrate902may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The first substrate902may be a wafer, such as a silicon wafer. Generally, an SOI substrate includes a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate902may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof.

The TSV904is formed of a conductive material. The conductive material may comprise copper, although other suitable materials such as aluminum, alloys, doped polysilicon, combinations thereof, and the like, may alternatively be utilized. At this fabrication stage, the TSV904may not completely extend through the first substrate902, i.e., not extending from the front surface to back surface of the first substrate902. The TSV904may be forming by performing at least some of the following processes: forming an opening through the front surface of the first substrate902; lining the opening with a barrier layer (not shown); filling the opening with the above-mentioned conductive material; and polishing the first substrate902. Although not shown, it should be noted that the same processes to form the TSV904(and the following operations ofFIG.8except for operation810) can be concurrently performed on a second substrate (chip) of the semiconductor device900.

Corresponding to operation804ofFIG.8,FIG.9Billustrates a cross-sectional view of a portion of the semiconductor device900including a number of components906,908, and910formed over the front surface of the substrate902at one of the various stages of fabrication, in accordance with various embodiments.

In the illustrated example ofFIG.9B(and the following figures), the component906can represent a number of devices such as, for example, transistors, memory cells, etc.; the component908can represent a number of via structures electrically coupled to the TSVs904(and the component906), respectively; and the component910can represent a number of interconnect structures electrically coupled to the via structures908, respectively. Such components906to910may be overlaid by a dielectric layer912, typically referred to as an inter-layer dielectric (ILD) or inter-metal dielectric (IMD). Upon forming such components, one of the above-discussed memory array layer, peripheral layer, or controller layer may have been formed, in accordance with some embodiments. For example, for a memory array layer, the component906can represent: (i) a number of memory cells collectively functioning as one or more memory arrays (e.g.,120); and (ii) a number of transistors collectively functioning as one or more essential circuits (e.g.,116and118). And, the components908and910can represent: (i) a number of access lines (e.g., bit lines, word lines, source lines, etc.) of the memory arrays; and (ii) a number of interconnect structures coupled to the memory arrays.

Corresponding to operation806ofFIG.8,FIG.9Cillustrates a cross-sectional view of a portion of the semiconductor device900in which the first substrate902is thinned down from its back surface at one of the various stages of fabrication, in accordance with various embodiments. As shown, the first substrate902is thinned down from its back surface until a bottom surface of the TSV904is exposed. In some embodiments, the first substrate902may be thinned down using a polishing process (e.g., a chemical-mechanical polishing (CMP) process), while having its front surface coupled to a carrier wafer916.

Corresponding to operation808ofFIG.8,FIG.9Dillustrates a cross-sectional view of a portion of the semiconductor device900including a number of bonding pads920coupled to the TSVs904, respectively, at one of the various stages of fabrication, in accordance with various embodiments. Upon the bottom surface of the TSV904being exposed, the bonding pad920is formed to electrically couple to the TSV904, thereby allowing the TSV904to be electrically coupled to other components, as will be discussed as follows. The bonding pad920is formed of a conductive material. The conductive material may comprise copper, although other suitable materials such as aluminum, alloys, doped polysilicon, combinations thereof, and the like, may alternatively be utilized.

Corresponding to operation810ofFIG.8,FIG.9Eillustrates a cross-sectional view of a portion of the semiconductor device900including a first layer and a second layer bonded to each other at one of the various stages of fabrication, in accordance with various embodiments. As mentioned above, the operations802to808can be concurrently performed on a second substrate (chip), which results in a similar layer being formed. As shown inFIG.9E, after forming the bonding pads920, a first layer (which can be one of the above-described memory array layer, peripheral layer, or controller layer) is bonded to a second layer (which can be one of the above-described memory array layer, peripheral layer, or controller layer). Similar to the first layer, the second layer includes a thinned substrate922, one or more TSVs924extending through the thinned substrate922, components926,928, and930, an ILD/IMD932, and one or more bonding pads930. In the illustrated example ofFIG.9E, the first layer is bonded (e.g., operatively coupled) to the second layer through the TSVs904. It should be appreciated that each of the first and second layers can be coupled to one or more other layers through its respective TSVs to form one of the memory systems, as discussed above.

FIG.10illustrates a flowchart of a method1000to form a memory system including different layers operatively coupled to each other through TSVs, according to one or more embodiments of the present disclosure. For example, at least some of the operations (or steps) of the method1000can be used to form a memory system discussed above. It is noted that the method1000is merely an example, and is not intended to limit the present disclosure. Accordingly, it should be understood that additional operations may be provided before, during, and/or after the method1000ofFIG.10, and that some other operations may only be briefly described herein. In some embodiments, operations of the method1000may be associated with cross-sectional views of an example semiconductor device at various fabrication stages as shown inFIGS.11A,11B,11C,11D, and11E, respectively, which will be discussed in further detail below.

Corresponding to operation1002ofFIG.10,FIG.11Aillustrates a cross-sectional view of a portion of a semiconductor device1100including a first substrate (or chip)1102with a number of components1104,1106, and1108formed over a front surface of the first substrate1102at one of the various stages of fabrication, in accordance with various embodiments.

The first substrate1102may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The first substrate1102may be a wafer, such as a silicon wafer. Generally, an SOI substrate includes a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate1102may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof.

In the illustrated example ofFIG.11A(and the following figures), the component1104can represent a number of devices such as, for example, transistors, memory cells, etc.; the component1106can represent a number of via structures electrically coupled to the component1104; and the component1108can represent a number of interconnect structures electrically coupled to the via structures1106, respectively. Such components1104to1108may be overlaid by a dielectric layer1110, typically referred to as an inter-layer dielectric (ILD) or inter-metal dielectric (IMD). Upon forming such components, one of the above-discussed memory array layer, peripheral layer, or controller layer may have been formed, in accordance with some embodiments. For example, for a memory array layer, the component1104can represent: (i) a number of memory cells collectively functioning as one or more memory arrays (e.g.,120); and (ii) a number of transistors collectively functioning as one or more essential circuits (e.g.,116and118). And, the components1106and1108can represent: (i) a number of access lines (e.g., bit lines, word lines, source lines, etc.) of the memory arrays; and (ii) a number of interconnect structures coupled to the memory arrays. It should be noted that the same processes to form the components1104to1108can be concurrently performed on a second substrate (chip) of the semiconductor device1100, which will be shown as follows.

Corresponding to operation1004ofFIG.10,FIG.11Billustrates a cross-sectional view of a portion of a semiconductor device1100including a first layer and a second layer bonded to each other at one of the various stages of fabrication, in accordance with various embodiments. As shown inFIG.11B, a first layer including the first substrate1102and components1104to1108(which can be one of the above-described memory array layer, peripheral layer, or controller layer) is bonded to a second layer (which can be one of the above-described memory array layer, peripheral layer, or controller layer). Similar to the first layer, the second layer includes a (second) substrate1122, components1124,1126, and1128, and an ILD/IMD1130. In the illustrated example ofFIG.11B, the second layer is bonded to the first layer by being flipped upside down.

Corresponding to operation1006ofFIG.10,FIG.11Cillustrates a cross-sectional view of a portion of the semiconductor device1100in which the second substrate1122is thinned down from its back surface at one of the various stages of fabrication, in accordance with various embodiments. As shown, the second substrate1122is thinned down from its back surface. In some embodiments, the second substrate1122may be thinned down using a polishing process (e.g., a chemical-mechanical polishing (CMP) process), while having its front surface coupled to the first substrate1102.

Corresponding to operation1008ofFIG.10,FIG.11Dillustrates a cross-sectional view of a portion of the semiconductor device1100including one or more TSVs1134at one of the various stages of fabrication, in accordance with various embodiments. As shown, the TSV1134can extend from the back surface of the thinned substrate1122, through the thinned substrate1122and IMD/ILD1130, and to the component1108of the first layer. Consequently, the second layer can be operatively coupled to the first layer through the TSVs1134. The TSV1134can be formed through the same processes as the TSV904, and have the same material as the TSV904. Thus, the descriptions are not repeated.

Corresponding to operation1010ofFIG.10,FIG.11Eillustrates a cross-sectional view of a portion of the semiconductor device1100including a number of bonding pads1140coupled to the TSVs1134, respectively, at one of the various stages of fabrication, in accordance with various embodiments. The bonding pad1140can allow the TSV1134to be electrically coupled to other components such as, for example, one or more other layers to form one of the memory systems, as discussed above. The bonding pad1140is formed of a conductive material. The conductive material may comprise copper, although other suitable materials such as aluminum, alloys, doped polysilicon, combinations thereof, and the like, may alternatively be utilized.

FIG.12a perspective view of an example memory system1200, in accordance with some other embodiments. The memory system1200includes a first layer1202, a second layer1204, a third layer1206, a fourth layer1208, and a fifth layer1210. Different from the memory system discussed above, at least one the layers1202to1210may essentially consist of one or more memory arrays. In other words, essential circuits (e.g., row decoders, sensing circuits) of these memory arrays may be disposed in a different layer. For example, the layer1202may include a memory controller (e.g.,102ofFIG.1), the layer1204may include some control circuits of a memory device (e.g.,106,108,110,112,114ofFIG.1), the layer1206may include some decoders of a memory device (e.g., row decoders of116, column decoders of118ofFIG.1), the layer1208may include some drivers or high-voltage circuits of a memory device (e.g., drivers of116ofFIG.1), and the layer1210may include some memory arrays of a memory device (e.g.,120ofFIG.1). Further, a stacking sequence of these layers1202to1210can be changed in any manner, while remaining within the scope of the present disclosure.

In one aspect of the present disclosure, a memory device is disclosed. The memory device includes a first layer, wherein the first layer includes a first memory array, a first row decoder circuit, and a first column sensing circuit. The memory device includes a second layer disposed with respect to the first layer in a vertical direction. The second layer includes a first peripheral circuit operatively coupled to the first memory array, the first row decoder circuit, and the first column sensing circuit. The memory device includes a plurality of interconnect structures extending along the vertical direction. At least a first one of the plurality of interconnect structures operatively couples the second layer to the first layer.

In another aspect of the present disclosure, a memory device is disclosed. The memory device includes a first layer including a first memory array. The memory device includes a second layer including a second memory array. The memory device includes a third layer disposed with respect to the first and second layers in a vertical direction, wherein the third layer includes a plurality of peripheral circuits. The memory device includes a plurality of interconnect structures extending along the vertical direction, wherein at least a first one of the plurality of interconnect structures operatively couples the third layer to the first layer but not to the second layer, and at least a second one of the plurality of interconnect structures operatively couples the third layer to the second layer but not to the first layer.

In yet another aspect of the present disclosure, a method for fabricating a memory device is disclosed. The method includes providing a first layer including a first memory array, a first row decoder circuit, and a first column sensing circuit. The method includes providing a second layer vertically disposed with respect to the first layer and including a plurality of peripheral circuits. The method includes forming a plurality of through-silicon-via (TSV) structures, wherein at least a first one of the TSV structures is selected to operatively couple a first one of the plurality of peripheral circuits to the first memory array, the first row decoder circuit, and the first column sensing circuit.

As used herein, the terms “about” and “approximately” generally mean plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, about 1000 would include 900 to 1100.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.