Patent ID: 12197938

DETAILED DESCRIPTION

Virtualization can allow execution of multiple virtual machine (VM) instances on the same physical machine to meet growing demand for storage, computing, and communication resources required by the modern-day applications. In order to manage various resources efficiently, virtualization techniques may sometimes rely on VM migration to perform load balancing, fault tolerance, power management, online system maintenance, and resource sharing, among others. Live VM migration can allow migrating a VM instance between different physical machines without disconnecting the application or the client. During live migration, contents of the memory associated with a VM instance can be migrated from the source (or current) host machine to the target host machine.

Some systems may store one or more additional bits of metadata for every chunk of memory. As an example, some processor architectures may store a 4-bit tag with every 16 bytes of physical memory. An example of such tag data can be Memory Tagging Extension (MTE) bits used in some ARM based systems. MTE can be used to increase the memory safety of code execution. For example, the MTE bits can act as a key to access a memory location. Pro-actively detecting memory safety violations using MTE can prevent a large class of security vulnerabilities from being exploitable. However, when the data migration is performed for a VM instance, the metadata for the tag may have to be migrated along with the data associated with the VM instance from the source memory in the source host machine to the target memory in the target host machine.

The data associated with the VM instance (or simply “the VM instance data”) and the corresponding metadata for the tag (or simply “the tag data”) may be co-located in the same memory device, or located in separate memory devices. When the VM instance data and the corresponding tag data are stored in separate memory devices, separate memory accesses may be required to read the VM instance data and the corresponding tag data, which can affect the memory bandwidth and degrade system performance. When the VM instance data and the corresponding tag data are co-located in the same memory device, a read transaction to the memory device can read both the VM instance data as well the tag data. However, in both implementations, the tag data is provided from the memory controller to the processor, and an input/output (I/O) device performing the live migration may not have direct access to the tag data. Furthermore, the I/O bus width may not be wide enough to support transporting the extra tag data together with the VM instance data. To obtain the tag data for the live migration, the I/O device may have to read the memory twice. For example, the I/O device may perform a first read access to the memory to read the VM instance data and the corresponding tag data to obtain the VM instance data, and a second read access to the memory to read the VM instance data and the corresponding tag data to obtain the tag data.

Embodiments can provide systems and methods to efficiently transport the tag data when migrating the VM instance data from a source device to a target device. For example, the VM instance data and the tag data may be co-located in a source memory. In some embodiments, the I/O device, which is configured to initiate the data migration of the VM instance from the source device to the target device, can send a first read request to read the VM instance data from the source memory. A source memory controller in the source device can read the VM instance data and the tag data together from the source memory, and temporarily store the tag data in a source tag buffer, which is accessible to the I/O device. The I/O device can send a second read request to read the tag data from the source tag buffer, and send the tag data to the target device.

The I/O device can also send a write request to the target device to write the VM instance data together with the tag data. In some embodiments, the target device may temporarily store the tag data in a target tag buffer and a target memory controller can write the tag data from the target tag buffer together with the VM instance data received from the source device into a target memory. Thus, by implementing a tag buffer that is accessible by the I/O device, the tag data can be transferred from the source memory to the target memory when migrating the VM instance data.

The source device can determine that a read request is for the data migration based on an indication from the I/O device. In some embodiments, a first read request may include an address alias to indicate that the first read request is to initiate the data migration and a second read request may include an address alias to indicate that the second read request is to read the tag data from the source tag buffer. For example, the I/O device may indicate that the first read request is to initiate the data migration using one or more address bits (e.g., if a most significant bit (MSB) of the address is set to 1). In some embodiments, the I/O device can be a PCIe device, such as a network interface card (NIC), and the data migration indication can be implemented using a specific bus device function (BDF) that is designated for data migration. The source device can generate a first data migration command to read the VM instance data and the tag data together from the source memory based on the first read request, and a second data migration command to read the tag data from the source tag buffer based on the second read request. In some embodiments, the indication for the data migration can be in the form of a signal that can accompany the first read request and the second request.

Similarly, the target device can determine that the write request is to write the VM instance data and the tag data for the data migration based on an indication from the I/O device. For example, the I/O device can indicate the data migration using the address or the specific BDF. In some embodiments, the source device and the target device can be coupled using a single I/O device (e.g., when the I/O device acts as a hub), or the source device and the target device can each have a respective I/O device that are communicatively coupled with each other (e.g., via a network).

In some embodiments, the VM instance data and the tag data may be stored in separate memory devices coupled to the source device. In this case, reading the VM instance data and the tag data from the separate memory devices may require separate memory accesses by the memory controller. Similarly, in some embodiments, the VM instance data and the tag data may be migrated to separate memory devices coupled to the target device. The VM instance data and the tag data can also be co-located in the source memory, or stored together in the target memory after data migration. Note that although MTE is described as one example of the tag data, the tag data can include other types of metadata that is not re-constructable from the data itself. For example, the tag data can be used to tag a memory location to indicate what type of data is stored at the location.

In the following description, various embodiments will be described. For purposes of explanation, specific configurations and details are set forth in order to provide a thorough understanding of the embodiments. However, it will also be apparent to one skilled in the art that the embodiments may be practiced without the specific details. Furthermore, well-known features may be omitted or simplified in order not to obscure the embodiments being described.

FIG.1illustrates a system100, which can be used to describe data migration between a source device102and a target device104.

The source device102may include one or more processor cores108, a memory controller112and an I/O interface114configured to communicate via an on-chip interconnect120. The source device102may be coupled to a source memory116. The source device102may also include other components based on the functionality supported by the source device102, which are not shown here for ease of discussion. The target device104may also include one or more processor cores, memory controllers, I/O interfaces, interconnects, and any other components based on the functionality supported by the target device104. The target device104may also be coupled to a target memory122.

Each of the source device102and the target device104may include a computing device, which may be configured to support execution of one or more VM instances associated with one or more applications or clients. For example, the processor core(s)108may be configured to execute one or more VMs110, which may be managed by a hypervisor (not shown).

In some cases, a VM instance from the VMs110executing on the source device102may have to be migrated to the target device104to improve performance, perform power management, manage computing resources, fix hardware issues, or for other reasons. In most cases, data migration can be performed for live migration of a VM instance from the source device102to the target device104without disconnecting the application or the client. During the live migration, contents of the memory associated with the VM instance can be migrated from the source device102to the target device104. In various implementations, the source device102and the target device104can be part of different physical machines (e.g., servers), which can be located on the same or different racks.

In some systems, an I/O device106may be configured to initiate data migration for the VM instance from the source device102to the target device104. The I/O device106can be a network controller, a network adapter, a network interface card, or any other suitable I/O device, which can facilitate communication between the source device102and the target device104for data migration and other tasks. In some implementations, the I/O device106may provide a network connection to communicate with a remote server, where the target device may be located. In some implementations, the I/O device106may be a PCIe device which can communicate with the I/O interface114based on a PCIe protocol.

The source memory116may include a plurality of memory chunks, which may be configured to store data associated with the VMs110executing on the source device102. The source memory116and the target memory122can include DRAM, SDRAM, DDR SDRAM, SRAM, or any suitable type of memory.FIG.1shows an example memory chunk118, which can store data associated with a VM instance. The memory chunk118may comprise memory data118a, tag data118b, and ECC data118c. The memory data118amay include data or payload associated with the VM instance.

In some examples, the tag data118bmay include ARM's memory tagging extension (MTE) bits associated with the memory data118a, which can be used to detect and mitigate memory safety violations. In some implementations, a lock can be implemented on each memory chunk by tagging each 16 bytes of physical memory with 4 bits of metadata. In other implementations, a different ratio of tag data bits to memory data bytes can be used (e.g., to adjust the number of unique tags available). A key can be provided during memory access, which can be compared with the lock (e.g., the tag data). The memory access can be denied, and an error can be reported when the key does not match with the lock. The key can be provided as part of the pointer or the virtual address of the transaction. The MTE bits can be generated using a random seed, a pseudo-random seed, or any suitable mechanism.

The ECC data118ccan be used to detect and correct data corruption in the source memory116. In some implementations, 4 bytes of ECC data can be provided for each 16 bytes of physical memory data. In other implementations, a different ratio of ECC bytes to data bytes can be used (e.g., to adjust the error correction capability). The ECC data118ccan be computed using any suitable algorithm such as Hamming algorithm, Reed-Solomon algorithm, or BCH algorithm. Unlike the ECC data118c, the tag data118bis not derived from the memory data118a. As such, the ECC data118cneed not be transferred from the source device102to the target device104during data migration because the ECC data118ccan be recomputed from the data itself by the target device104.

In some implementations, one or more of the memory data118a, tag data118b, and the ECC data118cmay be stored in separate memory devices or memory modules. For example, the memory data118amay be stored with the ECC data118cin a first memory module and the tag data118bmay be stored in a separate memory module. In some implementations, the memory data118a, the tag data118b, and the ECC data118ccan be stored on the same memory module.

When the data migration is performed to move the memory data118afor the VM instance from the source memory116to the target memory122, the tag data118cis also transferred from the source memory116to the target memory122because the tag data118cmay not be derivable from the data itself. In some systems, the I/O device106may perform a read transaction to read the memory data118afor the VM instance. However, the memory controller112typically provides the tag data118bto the processor108and discards the tag data118bwhen providing the memory data118ato other components such as the I/O device106. As such, a mechanism to provide the tag data118bto the I/O device106is implemented to perform data migration.

FIG.2illustrates a system200, which can be used to read the tag data and the memory data from a source device202for data migration to a target device206, according to some embodiments.

Each of the source device202and the target device206may include a computing device, which may be configured to provide a virtualization environment to support various applications such as cloud computing, machine learning, artificial intelligence, gaming, high performance computing, web hosting, or application hosting, among others. For example, each of the source device202and the target device206may support execution of one or more VM instances associated with one or more applications or clients. Each of the source device202and the target device206may include a system-on-a-chip (SoC) or other suitable integrated circuits based on the functionality supported by the system200.

The source device202may be coupled to a source memory220and to an I/O device204. The I/O device204can be a network controller, a network adapter, a network interface card, or any other suitable I/O device, which may be configured to initiate data migration from the source device202to the target device206. The source memory220may store data associated with one or more VM instances executing on the source device202in multiple data chunks of a certain size (e.g., 16 bytes), as discussed with reference toFIG.1. An example memory chunk222may comprise memory data222a, tag data222b, and ECC data222cas shown inFIG.2. The source memory220may also store other data based on the functionalities supported by the source device202. The source memory220may include DRAM, SDRAM, DDR SDRAM, SRAM, or any suitable type of memory. The memory data222a, tag data222b, and the ECC data222cmay be similar to the memory data118a, tag data118b, and the ECC data118c, respectively, as discussed with reference toFIG.1.

The source device202may comprise one or more source processor cores208, a source memory controller212, and a source I/O interface216coupled to a source interconnect218. The source memory controller212may include a source tag buffer214, which may be configured to store tag data associated with the memory data for the data migration of the VM instance. Note that the source device202may include one or more source memory controllers based on the size and configuration of the source memory220; however, only the source memory controller212is shown inFIG.2for ease of discussion. In some embodiments, the source tag buffer214may be external to the source memory controller212. The source processor208may be configured to execute one or more VMs, which may be managed by a hypervisor (not shown). In some examples, the source processor208can be executing a VM instance210, which may need to be migrated to the target device206. The source interconnect218can be implemented using buses, meshes, crossbars, matrix, arbiters, nodes, ports, or other suitable components based on the bus protocol(s) supported by the source device202.

In some embodiments, the target device206may be located in a remote server, which may communicate with the I/O device204using a target I/O device (not shown inFIG.2). For example, the target I/O device can be another network device, similar to the I/O device204. However, for ease of discussion, the I/O device204is shown to communicate with both the source device202and the target device206.

In some embodiments, the I/O device204may execute a specific instruction to perform the data migration by reading the memory data and the tag data for the VM instance210from the source memory220. For example, the I/O device204may initiate the data migration by sending a first read request to the source device202, which can enable the source memory controller212to read the memory data222aand the tag data222btogether from the source memory220, and store the tag data222bat an address corresponding to the source tag buffer214, which is accessible to the I/O device204. The I/O device204can send a second read request to read the tag data222bfrom the source tag buffer214. The memory data222aand the tag data222bcan be transmitted to the target device206in response to the first read request and the second read request, respectively.

In some embodiments, the I/O device204may transmit a write request to the target device206, which may indicate writing the memory data222aand the tag data222btogether at the target device206. In some examples, the data migration may include migrating a 2 MB page at a time, and, therefore, the source tag buffer214may support storing 64 KB of the corresponding tag data222bfor each 2 MB page. The 2 MB region can be available at a known memory location for the I/O device204to initiate read transactions allowing alternate 2 MB data reads and 64 KB metadata reads to transfer each 2 MB page.

In various examples, the source memory controller212may read a certain size of the memory data at a time from the source memory220and store the corresponding tag data in the source tag buffer214until a certain size of the tag data has been accumulated in the source tag buffer214for migrating to the target device206. For example, the size of the memory data and the tag data, which may be read together from the source memory220or transported to the target device206may be determined based on the system architecture supported by the system200(e.g., size and configuration of the memory modules in the source memory220, memory bus width, width of the internal buses, I/O interface, etc.).

In some examples, the I/O device204may transmit the first read request to the source device202to initiate a data migration to move data from the source memory220to a target memory coupled to the target device206for the VM instance210. The source I/O interface216may receive the first read request from the I/O device204to migrate the data for the VM instance210. The source I/O interface216may determine that the first read request is for the data migration based on an address alias indicated by the first read request. As an example, one or more bits in the address of the first read request may indicate that the first read request is for the data migration for the VM instance210. The source I/O interface216may be configured to generate a first data migration command for the source memory controller212in response to determining that the first read request is to initiate the data migration.

The source memory controller212may receive the first data migration command and perform a read operation to read the memory chunk222comprising the memory data222afor the VM instance210, the tag data222bassociated with the memory data222a, and the ECC data222c. The source memory controller212may store the tag data222bin the source tag buffer214for transmitting to the I/O device204for the data migration. The source memory controller212may transmit the memory data222ato the target device206via the source I/O interface216. In some implementations, the memory data222amay be temporarily buffered in the target device206, or prior to reaching the target device206, e.g., in the I/O device204and/or in a target I/O device. In some implementations, the source memory controller212may use the ECC data222cto detect and correct any errors associated with the memory data222a. In some cases, the ECC data222cmay not need to be transmitted from the source device202to the target device206for the data migration of the VM instance210, but can be instead recalculated, for example, by a target memory controller in the target device206when storing the data being migrated.

In some embodiments, the I/O device204may transmit a second read request to the source device202to read the tag data222bassociated with the memory data222a. The second read request may be received by the source I/O interface216. The source I/O interface216may determine that the second read request is also for the data migration based on the one or more bits in the address of the second read request, similar to the first read request. The source I/O interface216may generate a second data migration command for the source memory controller212to read the tag data222bfrom the source tag buffer214. The source I/O interface216may transmit the tag data222bfrom the source tag buffer214to the I/O device204. The I/O device204may receive the tag data222band transmit the tag data222bto the target device206.

In some embodiments, the I/O device204can be a PCIe device, and the data migration indication can be implemented using a bus device function (BDF). For example, the first read request and the second read request from the I/O device204for the data migration can be associated with a specific BDF that can be identified by the source I/O interface216to generate the data migration command or message for the source memory controller212to read the tag data together with the memory data and temporarily store the tag data in the source tag buffer214. In some implementations, the source I/O interface216may include a PCIe root complex that can recognize the requests from the specific BDF and use the requests associated with the BDF to generate the data migration commands to be sent to the source memory controller212via the source interconnect218.

In some embodiments, the source interconnect218may be implemented using a bus protocol that can be similar to the Advanced extensible Interface (AXI) protocol, and the I/O device204may use a signal similar to the AXI USER signal to indicate to the source memory controller212to read the memory data222aand the tag data222btogether from the source memory220.

The target device206can be part of the same server rack or a different server rack. In some implementations, the I/O device204and the source device202can be part of the same server, and the I/O device204may communicate with a different I/O device coupled to the target device206on a different server. This is further explained with reference toFIG.3.

FIG.3illustrates a system300, which can be used to write the tag data and the memory data together into a target memory for the data migration of the VM instance, according to some embodiments.

The system300may include the target device206coupled to a target memory316and an I/O device314. The target device206can be a computing device, which can include an SoC or other suitable integrated circuits based on the functionality supported by the target device206. The I/O device314can be a network controller, a network adapter, a network interface card, or any other suitable I/O device, which can facilitate the data migration for the VM instance210executing on the source device202to the target device206. In various implementations, the I/O device314can be the I/O device204fromFIG.2, or a separate I/O device similar to the I/O device204based on the implementation.

The target device206may comprise one or more target processor cores304, a target memory controller302, a target I/O interface310, and a target tag buffer308coupled to a target interconnect312. The one or more target processor cores304may be configured to support execution of one or more VMs306. The target tag buffer308may be configured to temporarily store the tag data associated with the data for the data migration of the VM instance210from the source device206. The target memory316may be configured to store data associated with the migration of the one or more VM instances, and any other data based on the applications executing on the target device206. The target memory316may include DRAM, SDRAM, DDR SDRAM, SRAM, or any suitable type of memory. Note that the target device206may include one or more target memory controllers based on the size and configuration of the target memory316; however, only the target memory controller302is shown inFIG.3for ease of discussion.

The I/O device314may be configured to receive the memory data222afor the VM instance210and the tag data222bassociated with the memory data from the source device202(when the I/O device314is same as the I/O device204), or the I/O device204. The target I/O interface310may be configured to receive the memory data222afor the VM instance210and the corresponding tag data222b, and store the tag data222bin the target tag buffer308. In some embodiments, the I/O device314may transmit a write request to the target device206to write the memory data222aand the tag data222btogether to the target memory316for the data migration of the VM instance210. The target I/O interface310may be configured to determine that the write request is for the data migration based on the address of the write request. As discussed with reference toFIG.2, one or more bits in the address of the write request may indicate that the write request is for the data migration of the VM instance210.

In some embodiments, the I/O device314can be a PCIe device, and the data migration indication can be implemented using a BDF as discussed with reference to the I/O device204. For example, the write request from the I/O device314can be associated with a specific BDF that can be identified by the target I/O interface310to generate a data migration command or message for the target memory controller302to write the tag data222bstored in the target tag buffer308together with the memory data222afor the VM instance210into the target memory316. In some implementations, the target I/O interface310may include a PCIe root complex that can identify the requests from the specific BDF and use a message space associated with the BDF to generate the data migration commands to be sent to the target memory controller302via the target interconnect312.

In some implementations, the target memory controller302may generate ECC data for each memory chunk that is being written into the target memory316as part of the data migration of the VM instance210. As shown inFIG.3, the target memory controller302may write a memory chunk318comprising memory data318afor the data migration of the VM instance210, tag data318bassociated with the memory data318a, and ECC data318c. The memory data318acan be the memory data222a, and the tag data318bcan be the tag data222bbeing migrated from the source device202.

FIG.4illustrates a flowchart400for a method to perform data migration by an I/O device404from a source device402to a target device406, according to some embodiments. The source device402can be an example of the source device202, the target device406can be an example of the target device206, and the I/O device404can be an example of the I/O device204(e.g., in this case, the I/O device204and the I/O device314can be the same device). In step408, the I/O device404can send a first read request to the source device402to initiate data migration. The data migration may include moving data for the VM instance210from the source memory220to the target memory316. In some embodiments, the first read request may include an address alias to indicate that the first read request is to initiate the data migration. In some embodiments, the I/O device404can be a PCIe device and the first read request may be associated with a BDF that may indicate that the first read request is to initiate the data migration.

In step410, the source device402may determine that the first read request is to initiate the data migration. For example, the source I/O interface216may determine that the first read request is to initiate the data migration based on the address of the first read request. The source I/O interface216may generate the first data migration command for the source memory controller212in response to determining that the first read request is to initiate the data migration.

In step412, the source device402may read data for the data migration and the tag data. The source device402may read the data for the VM instance and tag data associated with the data from the source memory220. For example, the source memory controller212may read the memory data222afor the VM instance210, the tag data222bassociated with the memory data222a, and the ECC data222cbased on the first data migration command. The ECC data222cmay be used to detect and correct any errors in the memory data222a.

In step414, the source device402may store the tag data in a source tag buffer. The source memory controller212may store the tag data222bin the source tag buffer214. In some examples, the source memory controller212may perform multiple reads of the source memory220to migrate one memory page and the corresponding tag data at a time to the target device406. In some examples, the source memory controller212may continue storing the tag data in the source tag buffer214until the tag data is ready to be transmitted to the target device406(e.g., when a threshold amount of tag data has been stored).

In step416, the source device402may transmit the data for the data migration to the target device406. The source memory controller212may transmit the memory data222ato the target device206via the source I/O interface216. In some implementations, the source I/O interface216may transmit the memory data222ato the I/O device204, which may transmit the data to the target device206.

In step418, the data for the data migration may be received from the source device402. In some implementations, the I/O device204may receive the memory data222afor the migration from the source I/O interface216. In some embodiments, where the I/O device204and the I/O device314are separate I/O devices (e.g., coupled via a network connection), the I/O device204may transmit the memory data222ato the I/O device314, which may transmit the memory data222ato the target device206. In some implementations, the I/O device204and/or the I/O device314may buffer the memory data222atemporarily before transmitting to the target device206.

In step420, the target device406may receive the data for the data migration. For example, the target I/O interface310may receive the memory data222afrom the I/O device204or the I/O device314based on the implementation. In some implementations, the memory data222amay be buffered temporarily in the target device206until the tag data222bis obtained, such that the memory data222aand the tag data222bcan be written together into the target memory316. The memory data222amay also be received by the target device206after the tag data222bhas been obtained. For example, the memory data222acan be buffered at the source device202, the I/O device204, the I/O device314, and/or by the network such that the memory data222ais transmitted to the target device206after the tag data222bhas been transmitted to the target device206.

In step422, the I/O device404may send a second read request to the source device402to read tag data associated with the data for the data migration. The I/O device204may send a second read request to the source I/O interface216to read the tag data222bassociated with the memory data222afor the data migration. The source I/O interface216may determine that the second read request is also for the data migration based on the address alias indication in the second read request, similar to the first read request. The source I/O interface216may generate the second data migration command for the source memory controller212to read the tag data222bfrom the source tag buffer214.

In step424, the source device402may read the tag data from the source tag buffer. The source memory controller212may send the tag data222bfrom the source tag buffer214to the source I/O interface216.

In step426, the source device402may transmit the tag data from the source tag buffer to the target device. The source I/O interface216may transmit the tag data222bto the I/O device204, which can forward the tag data222bto the I/O device314, or to target device206in the absence of the I/O device314.

In step428, the I/O device404may receive the tag data associated with the data from the source device. In some implementations, the I/O device204may receive the tag data222bfrom the source I/O interface216. In some embodiments, where the I/O device204and the I/O device314are separate entities, the I/O device204may transmit the tag data222bto the I/O device314, which may transmit the tag data222bto the target device206.

In step430, the target device406may store the tag data in a target tag buffer. The target I/O interface310may store the tag data222bin the target tag buffer308.

In step432, the I/O device404may send a write request to the write the data for the data migration together with the tag data into the target memory. The target I/O interface310may receive the write request and determine that the write request is for the data migration based on the address alias indicated in the write request. For example, the target I/O interface310may send a data migration command to the target memory controller302to write the memory data222afor the VM instance210together with the tag data222bstored in the target tag buffer308into the target memory316.

In step434, the target device406may write the data for the VM instance together with the tag data into the target memory via the target memory controller. The tag data222bmay be read from the target tag buffer308and written into the target memory316by the target memory controller302along with the memory data222a.

FIG.5illustrates a flowchart500for a method executed by a computing device for data migration, according to some embodiments. The computing device can be the source device202as described with reference toFIG.2.

In step502, the method may include receiving a first read request from an I/O device. As discussed with reference toFIG.2, the source device202may receive the first read request from the I/O device204via the source I/O interface216. In some examples, the first read request may be generated by the I/O device204based on an instruction executed by the I/O device204for the data migration.

In step504, the method may include determining that the first read request is to initiate a data migration based on a data migration indication in the first read request. The source I/O interface216may determine that the first read request is to initiate a data migration based on a data migration indication in the first read request. The data migration indication may be embedded in an address of the first read request, or the data migration indication may be implemented using a BDF when the I/O device204is a PCIe device. The data migration may be initiated to migrate the data for the VM instance210from the source memory220to the target memory316. The source I/O interface216may be configured to generate the first data migration command for the source memory controller212in response to determining that the first read request is to initiate the data migration.

In step506, the method may include reading, by a memory controller of the computing device, data for the data migration and tag data associated with the data from a memory. The source memory controller212may receive the first data migration command and perform a read operation to read the memory data222afor the VM instance210, and the tag data222bassociated with the memory data222a. In some examples, the source memory controller212may also read the ECC data222c, which can be used to detect and correct any errors in the memory data222a.

In step508, the method may include storing, by the memory controller of the computing device, the tag data in a tag buffer. The source memory controller212may store the tag data222bin the source tag buffer214, and send the memory data222ato the source I/O interface216via the source interconnect218.

In step510, the method may include transmitting the data for the data migration to the I/O device. The source I/O interface216may transmit the memory data222ato the I/O device204for the data migration. The I/O device204may transmit the memory data222ato the I/O device314, or to the target device206if the I/O device314and the I/O device204are the same entity.

In step512, the method may include receiving a second read request from the I/O device to read the tag data. The source I/O interface216may receive the second read request from the I/O device204and determine that the second read request is also for the data migration based on the address alias indication in the second read request. The source I/O interface216may generate the second data migration command for the source memory controller212to read the tag data222bfrom the source tag buffer214.

In step514, the method may include transmitting the tag data from the tag buffer to the I/O device. The source I/O interface216may transmit the tag data222bfrom the source tag buffer214to the I/O device204. The I/O device204may receive the tag data222band transmit the memory data222aand the tag data222bto the target device206. The target memory controller302may write the memory data222atogether with the tag data222bto the target memory316. For example, the memory data318acan be the memory data222a, and the tag data318bcan be the tag data222b. In some examples, the ECC data318cmay have been calculated by the target memory controller302based on the memory data318b.

FIG.6illustrates a flowchart600for a method to facilitate data migration of a VM instance from a source device to a target device, according to some embodiments. In some examples, the data migration may be a live migration of a VM instance executing on the source device202to the target device206.

In step602, the method includes transmitting, by an I/O device, a first read request to a source device to initiate a data migration to move data from a source memory to a target memory. As discussed with reference toFIG.2, the first read request may be transmitted by the I/O device204to initiate the data migration to move the data from the source memory220to the target memory316. In some implementations, the first read request may include an address alias to indicate that the first read request is to initiate the data migration. In some implementations, the first read request may be transmitted using a BDF designated for the data migration. In response to the first read request, the source memory controller212may read the memory data222aand the tag data222btogether from the source memory220, and store the tag data222bin the source tag buffer214. The memory data222amay be transmitted to the I/O device204by the source I/O interface216.

In step604, the method includes receiving, from the source device, the data for the data migration. The memory data222amay be received from the source I/O interface216. The memory data222amay be received by the I/O device204, which may transmit the memory data222ato the I/O device314, or to the target device206based on the implementation.

In step606, the method includes transmitting, by the I/O device, a second read request to the source device to read tag data associated with the data for the data migration. The I/O device204may transmit the second read request to read the tag data222bassociated with the memory data222afor the data migration. The source memory controller212may send the tag data222bfrom the source tag buffer214to the source I/O interface216.

In step608, the method includes receiving, from the source device, the tag data associated with the data for the data migration. The tag data222bmay be received from the source tag buffer214via the source I/O interface216. The tag data222bmay be received by the I/O device204, which may transmit the data to the I/O device314.

In step610, the method includes transmitting, by the I/O device, the data and the tag data to a target device. The I/O device204may transmit the memory data222aand the tag data222bto the target device206. The target memory controller302may write the memory data222atogether with the tag data222bto the target memory316based on the write request sent by the I/O device204.

As discussed with reference toFIGS.2-6, various embodiments can be used to efficiently transport the tag data along with the VM instance data for migrating a VM instance from a source device to a target device. In some examples, when the tag data and the VM instance data are co-located in the source memory, the source memory controller can read the tag data together with the VM instance data using a single memory read access. Similarly, the target memory controller can write the tag data together with the VM instance data using a single memory write access. The tag data can be used to store MTE or other types of metadata based on the application.

FIG.7illustrates an example of a network device700. Functionality and/or several components of the network device700may be used without limitation with other embodiments disclosed elsewhere in this disclosure, without limitations. For example, the network device700can be an example of the I/O device204or the I/O device314. In some embodiments, some of the components of the network device700can be part of the source device202or the target device206. A network device700may facilitate processing of packets and/or forwarding of packets from the network device700to another device. As referred to herein, a “packet” or “network packet” may refer to a variable or fixed unit of data. In some instances, a packet may include a packet header and a packet payload. The packet header may include information associated with the packet, such as the source, destination, quality of service parameters, length, protocol, routing labels, error correction information, etc. In certain implementations, one packet header may indicate information associated with a series of packets, such as a burst transaction. In some implementations, the network device700may be the recipient and/or generator of packets. In some implementations, the network device700may modify the contents of the packet before forwarding the packet to another device. The network device700may be a peripheral device coupled to another computer device, a switch, a router or any other suitable device enabled for receiving and forwarding packets.

In one example, the network device700may include processing logic702, a configuration module704, a management module706, a bus interface module708, memory710, and a network interface module712. These modules may be hardware modules, software modules, or a combination of hardware and software. In certain instances, modules may be interchangeably used with components or engines, without deviating from the scope of the disclosure. The network device700may include additional modules, not illustrated here, such as components discussed with respect to the nodes disclosed inFIG.8. In some implementations, the network device700may include fewer modules. In some implementations, one or more of the modules may be combined into one module. One or more of the modules may be in communication with each other over a communication channel714. The communication channel714may include one or more busses, meshes, matrices, fabrics, a combination of these communication channels, or some other suitable communication channel.

The processing logic702may include application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), systems-on-chip (SoCs), network processing units (NPUs), processors configured to execute instructions or any other circuitry configured to perform logical arithmetic and floating point operations. Examples of processors that may be included in the processing logic702may include processors developed by ARM®, MIPS®, AMD®, Intel®, Qualcomm®, and the like. In certain implementations, processors may include multiple processing cores, wherein each processing core may be configured to execute instructions independently of the other processing cores. Furthermore, in certain implementations, each processor or processing core may implement multiple processing threads executing instructions on the same processor or processing core, while maintaining logical separation between the multiple processing threads. Such processing threads executing on the processor or processing core may be exposed to software as separate logical processors or processing cores. In some implementations, multiple processors, processing cores or processing threads executing on the same core may share certain resources, such as for example busses, level 1 (L1) caches, and/or level 2 (L2) caches. The instructions executed by the processing logic702may be stored on a computer-readable storage medium, for example, in the form of a computer program. The computer-readable storage medium may be non-transitory. In some cases, the computer-readable medium may be part of the memory710.

The memory710may include either volatile or non-volatile, or both volatile and non-volatile types of memory. The memory710may, for example, include random access memory (RAM), read only memory (ROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), flash memory, and/or some other suitable storage media. In some cases, some or all of the memory710may be internal to the network device700, while in other cases some or all of the memory may be external to the network device700. The memory710may store an operating system comprising executable instructions that, when executed by the processing logic702, provides the execution environment for executing instructions providing networking functionality for the network device700. The memory may also store and maintain several data structures and routing tables for facilitating the functionality of the network device700.

In some implementations, the configuration module704may include one or more configuration registers. Configuration registers may control the operations of the network device700. In some implementations, one or more bits in the configuration register can represent certain capabilities of the network device700. Configuration registers may be programmed by instructions executing in the processing logic702, and/or by an external entity, such as a host device, an operating system executing on a host device, and/or a remote device. The configuration module704may further include hardware and/or software that control the operations of the network device700.

In some implementations, the management module706may be configured to manage different components of the network device700. In some cases, the management module706may configure one or more bits in one or more configuration registers at power up, to enable or disable certain capabilities of the network device700. In certain implementations, the management module706may use processing resources from the processing logic702. In other implementations, the management module706may have processing logic similar to the processing logic702, but segmented away or implemented on a different power plane than the processing logic702.

The bus interface module708may enable communication with external entities, such as a host device and/or other components in a computing system, over an external communication medium. The bus interface module708may include a physical interface for connecting to a cable, socket, port, or other connection to the external communication medium. The bus interface module708may further include hardware and/or software to manage incoming and outgoing transactions. The bus interface module708may implement a local bus protocol, such as Peripheral Component Interconnect (PCI) based protocols, Non-Volatile Memory Express (NVMe), Advanced Host Controller Interface (AHCI), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Serial AT Attachment (SATA), Parallel ATA (PATA), some other standard bus protocol, or a proprietary bus protocol. The bus interface module708may include the physical layer for any of these bus protocols, including a connector, power management, and error handling, among other things. In some implementations, the network device700may include multiple bus interface modules for communicating with multiple external entities. These multiple bus interface modules may implement the same local bus protocol, different local bus protocols, or a combination of the same and different bus protocols.

The network interface module712may include hardware and/or software for communicating with a network. This network interface module712may, for example, include physical connectors or physical ports for wired connection to a network, and/or antennas for wireless communication to a network. The network interface module712may further include hardware and/or software configured to implement a network protocol stack. The network interface module712may communicate with the network using a network protocol, such as for example TCP/IP, Infiniband, RoCE, Institute of Electrical and Electronics Engineers (IEEE) 802.11 wireless protocols, User Datagram Protocol (UDP), Asynchronous Transfer Mode (ATM), token ring, frame relay, High Level Data Link Control (HDLC), Fiber Distributed Data Interface (FDDI), and/or Point-to-Point Protocol (PPP), among others. In some implementations, the network device700may include multiple network interface modules, each configured to communicate with a different network. For example, in these implementations, the network device700may include a network interface module for communicating with a wired Ethernet network, a wireless 802.11 network, a cellular network, an Infiniband network, etc.

The various components and modules of the network device700, described above, may be implemented as discrete components, as a System on a Chip (SoC), as an ASIC, as an NPU, as an FPGA, or any combination thereof. In some embodiments, the SoC or other component may be communicatively coupled to another computing system to provide various services such as traffic monitoring, traffic shaping, computing, etc. In some embodiments of the technology, the SoC or other component may include multiple subsystems as disclosed with respect toFIG.8.

FIG.8illustrates a network800, illustrating various different types of network devices700ofFIG.7, such as nodes comprising the network device, switches and routers. In certain embodiments, the network800may be based on a switched architecture with point-to-point links. As illustrated inFIG.8, the network800includes a plurality of switches804a-804d, which may be arranged in a network. In some cases, the switches are arranged in a multi-layered network, such as a Clos network. A network device700that filters and forwards packets between local area network (LAN) segments may be referred to as a switch. Switches generally operate at the data link layer (layer 2) and sometimes the network layer (layer 3) of the Open System Interconnect (OSI) Reference Model and may support several packet protocols. Switches804a-804dmay be connected to a plurality of nodes802a-802hand provide multiple paths between any two nodes.

The network800may also include one or more network devices700for connection with other networks808, such as other subnets, LANs, wide area networks (WANs), or the Internet, and may be referred to as routers806. Routers use headers and forwarding tables to determine the best path for forwarding the packets, and use protocols such as internet control message protocol (ICMP) to communicate with each other and configure the best route between any two devices.

In some examples, network(s)800may include any one or a combination of many different types of networks, such as cable networks, the Internet, wireless networks, cellular networks and other private and/or public networks. Interconnected switches804a-804dand router806, if present, may be referred to as a switch fabric, a fabric, a network fabric, or simply a network. In the context of a computer network, terms “fabric” and “network” may be used interchangeably herein.

Nodes802a-802hmay be any combination of host systems, processor nodes, storage subsystems, and I/O chassis that represent user devices, service provider computers or third party computers. In various examples, the source device202and the target device206can be part of the same node or different nodes in the nodes802a-802h.

User devices may include computing devices to access an application832(e.g., a web browser or mobile device application). In some aspects, the application832may be hosted, managed, and/or provided by a computing resources service or service provider. The application832may allow the user(s) to interact with the service provider computer(s) to, for example, access web content (e.g., web pages, music, video, etc.). The user device(s) may be a computing device such as for example a mobile phone, a smart phone, a personal digital assistant (PDA), a laptop computer, a netbook computer, a desktop computer, a thin-client device, a tablet computer, an electronic book (e-book) reader, a gaming console, etc. In some examples, the user device(s) may be in communication with the service provider computer(s) via the other network(s)808. Additionally, the user device(s) may be part of the distributed system managed by, controlled by, or otherwise part of the service provider computer(s) (e.g., a console device integrated with the service provider computers).

The node(s) ofFIG.8may also represent one or more service provider computers. One or more service provider computers may provide a native application that is configured to run on the user devices, which user(s) may interact with. The service provider computer(s) may, in some examples, provide computing resources such as, but not limited to, client entities, low latency data storage, durable data storage, data access, management, virtualization, cloud-based software solutions, electronic content performance management, and so on. The service provider computer(s) may also be operable to provide web hosting, databasing, computer application development and/or implementation platforms, combinations of the foregoing or the like to the user(s). In some embodiments, the service provider computer(s) may be provided as one or more virtual machines implemented in a hosted computing environment. The hosted computing environment may include one or more rapidly provisioned and released computing resources. These computing resources may include computing, networking and/or storage devices. A hosted computing environment may also be referred to as a cloud computing environment. The service provider computer(s) may include one or more servers, perhaps arranged in a cluster, as a server farm, or as individual servers not associated with one another and may host the application832and/or cloud-based software services. These servers may be configured as part of an integrated, distributed computing environment. In some aspects, the service provider computer(s) may, additionally or alternatively, include computing devices such as for example a mobile phone, a smart phone, a personal digital assistant (PDA), a laptop computer, a desktop computer, a netbook computer, a server computer, a thin-client device, a tablet computer, a gaming console, etc. In some instances, the service provider computer(s), may communicate with one or more third party computers.

In one example configuration, the node(s)802a-802hmay include at least one memory818and one or more processing units (or processor(s)820). The processor(s)820may be implemented in hardware, computer-executable instructions, firmware, or combinations thereof. Computer-executable instruction or firmware implementations of the processor(s)820may include computer-executable or machine-executable instructions written in any suitable programming language to perform the various functions described.

In some instances, the hardware processor(s)820may be a single core processor or a multi-core processor. A multi-core processor may include multiple processing units within the same processor. In some embodiments, the multi-core processors may share certain resources, such as buses and second or third level caches. In some instances, each core in a single or multi-core processor may also include multiple executing logical processors (or executing threads). In such a core (e.g., those with multiple logical processors), several stages of the execution pipeline and also lower level caches may also be shared.

The memory818may store program instructions that are loadable and executable on the processor(s)820, as well as data generated during the execution of these programs. Depending on the configuration and type of the node(s)802a-802h, the memory818may be volatile (such as RAM) and/or non-volatile (such as ROM, flash memory, etc.). The memory818may include an operating system828, one or more data stores830, one or more application programs832, one or more drivers834, and/or services for implementing the features disclosed herein.

The operating system828may support nodes802a-802hbasic functions, such as scheduling tasks, executing applications, and/or controller peripheral devices. In some implementations, a service provider computer may host one or more virtual machines. In these implementations, each virtual machine may be configured to execute its own operating system. Examples of operating systems include Unix, Linux, Windows, Mac OS, IOS, Android, and the like. The operating system828may also be a proprietary operating system.

The data stores830may include permanent or transitory data used and/or operated on by the operating system828, application programs832, or drivers834. Examples of such data include web pages, video data, audio data, images, user data, and so on. The information in the data stores830may, in some implementations, be provided over the network(s)808to user devices804. In some cases, the data stores830may additionally or alternatively include stored application programs and/or drivers. Alternatively or additionally, the data stores830may store standard and/or proprietary software libraries, and/or standard and/or proprietary application user interface (API) libraries. Information stored in the data stores830may be machine-readable object code, source code, interpreted code, or intermediate code.

The drivers834include programs that may provide communication between components in a node. For example, some drivers834may provide communication between the operating system828and additional storage822, network device824, and/or I/O device826. Alternatively or additionally, some drivers834may provide communication between application programs832and the operating system828, and/or application programs832and peripheral devices accessible to the service provider computer. In many cases, the drivers834may include drivers that provide well-understood functionality (e.g., printer drivers, display drivers, hard disk drivers, Solid State Device drivers). In other cases, the drivers834may provide proprietary or specialized functionality.

The service provider computer(s) or servers may also include additional storage822, which may include removable storage and/or non-removable storage. The additional storage822may include magnetic storage, optical disks, solid state disks, flash memory, and/or tape storage. The additional storage822may be housed in the same chassis as the node(s)802a-802hor may be in an external enclosure. The memory818and/or additional storage822and their associated computer-readable media may provide non-volatile storage of computer-readable instructions, data structures, program modules, and other data for the computing devices. In some implementations, the memory818may include multiple different types of memory, such as SRAM, DRAM, or ROM.

The memory818and the additional storage822, both removable and non-removable, are examples of computer-readable storage media. For example, computer-readable storage media may include volatile or non-volatile, removable or non-removable media implemented in a method or technology for storage of information, the information including, for example, computer-readable instructions, data structures, program modules, or other data. The memory818and the additional storage822are examples of computer storage media. Additional types of computer storage media that may be present in the node(s)802a-802hmay include, but are not limited to, PRAM, SRAM, DRAM, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, DVD or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, solid state drives, or some other medium which can be used to store the desired information and which can be accessed by the node(s)802a-802h. Computer-readable media also includes combinations of any of the above media types, including multiple units of one media type.

Alternatively or additionally, computer-readable communication media may include computer-readable instructions, program modules or other data transmitted within a data signal, such as a carrier wave or other transmission. However, as used herein, computer-readable storage media does not include computer-readable communication media.

The node(s)802a-802hmay also include I/O device(s)826, such as a keyboard, a mouse, a pen, a voice input device, a touch input device, a display, speakers, a printer, and the like. The node(s)802a-802hmay also include one or more communication channels836. A communication channel836may provide a medium over which the various components of the node(s)802a-802hcan communicate. The communication channel or channels836may take the form of a bus, a ring, a switching fabric, or a network.

The node(s)802a-802hmay also contain network device(s)824that allow the node(s)802a-802hto communicate with a stored database, another computing device or server, user terminals and/or other devices on the network(s)800. The network device(s)824ofFIG.8may include similar components discussed with reference to the network device700ofFIG.7.

In some implementations, the network device824is a peripheral device, such as a PCI-based device. In these implementations, the network device824includes a PCI interface for communicating with a host device. The term “PCI” or “PCI-based” may be used to describe any protocol in the PCI family of bus protocols, including the original PCI standard, PCI-X, Accelerated Graphics Port (AGP), and PCI-Express (PCIe) or any other improvement or derived protocols that are based on the PCI protocols discussed herein. The PCI-based protocols are standard bus protocols for connecting devices, such as a local peripheral device to a host device. A standard bus protocol is a data transfer protocol for which a specification has been defined and adopted by various manufacturers. Manufacturers ensure that compliant devices are compatible with computing systems implementing the bus protocol, and vice versa. As used herein, PCI-based devices also include devices that communicate using Non-Volatile Memory Express (NVMe). NVMe is a device interface specification for accessing non-volatile storage media attached to a computing system using PCIe. For example, the bus interface module708may implement NVMe, and the network device824may be connected to a computing system using a PCIe interface.

A PCI-based device may include one or more functions. A “function” describes operations that may be provided by the network device824. Examples of functions include mass storage controllers, network controllers, display controllers, memory controllers, serial bus controllers, wireless controllers, and encryption and decryption controllers, among others. In some cases, a PCI-based device may include more than one function. For example, a PCI-based device may provide a mass storage controller and a network adapter. As another example, a PCI-based device may provide two storage controllers, to control two different storage resources. In some implementations, a PCI-based device may have up to eight functions.

In some implementations, the network device824may include single-root I/O virtualization (SR-IOV). SR-IOV is an extended capability that may be included in a PCI-based device. SR-IOV allows a physical resource (e.g., a single network interface controller) to appear as multiple resources (e.g., sixty-four network interface controllers). Thus, a PCI-based device providing a certain functionality (e.g., a network interface controller) may appear to a device making use of the PCI-based device to be multiple devices providing the same functionality. The functions of an SR-IOV-capable storage adapter device may be classified as physical functions (PFs) or virtual functions (VFs). Physical functions are fully featured functions of the device that can be discovered, managed, and manipulated. Physical functions have configuration resources that can be used to configure or control the storage adapter device. Physical functions include the same configuration address space and memory address space that a non-virtualized device would have. A physical function may have a number of virtual functions associated with it. Virtual functions are similar to physical functions, but are light-weight functions that may generally lack configuration resources, and are generally controlled by the configuration of their underlying physical functions. Each of the physical functions and/or virtual functions may be assigned to a respective thread of execution (such as for example, a virtual machine) running on a host device.

The modules described herein may be software modules, hardware modules or a suitable combination thereof. If the modules are software modules, the modules can be embodied on a non-transitory computer readable medium and processed by a processor in any of the computer systems described herein. It should be noted that the described processes and architectures can be performed either in real-time or in an asynchronous mode prior to any user interaction. The modules may be configured in the manner suggested inFIG.7,FIG.8, and/or functions described herein can be provided by one or more modules that exist as separate modules and/or module functions described herein can be spread over multiple modules.

The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that various modifications and changes may be made thereunto without departing from the broader spirit and scope of the disclosure as set forth in the claims.

Other variations are within the spirit of the present disclosure. Thus, while the disclosed techniques are susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in the drawings and have been described above in detail. It should be understood, however, that there is no intention to limit the disclosure to the specific form or forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the disclosure, as defined in the appended claims.

The use of the terms “a” and “an” and “the” and similar referents in the context of describing the disclosed embodiments (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The terms “comprising,” “having,” “including,” and “containing” are to be construed as open-ended terms (i.e., meaning “including, but not limited to,”) unless otherwise noted. The term “connected” is to be construed as partly or wholly contained within, attached to, or joined together, even if there is something intervening. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein and each separate value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better illuminate embodiments of the disclosure and does not pose a limitation on the scope of the disclosure unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure.

Disjunctive language such as the phrase “at least one of X, Y, or Z,” unless specifically stated otherwise, is intended to be understood within the context as used in general to present that an item, term, etc., may be either X, Y, or Z, or any combination thereof (e.g., X, Y, and/or Z). Thus, such disjunctive language is not generally intended to, and should not, imply that certain embodiments require at least one of X, at least one of Y, or at least one of Z to each be present.

Various embodiments of this disclosure are described herein, including the best mode known to the inventors for carrying out the disclosure. Variations of those embodiments may become apparent to those of ordinary skill in the art upon reading the foregoing description. The inventors expect skilled artisans to employ such variations as appropriate and the inventors intend for the disclosure to be practiced otherwise than as specifically described herein. Accordingly, this disclosure includes all modifications and equivalents of the subject matter recited in the claims appended hereto as permitted by applicable law. Moreover, any combination of the above-described elements in all possible variations thereof is encompassed by the disclosure unless otherwise indicated herein or otherwise clearly contradicted by context.