Patent ID: 12205860

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In accordance with some embodiments, a sensor die is packaged in an InFO package. The sensor die may include sensing regions at the active and/or back surfaces of the sensor die. The InFO package may include openings that expose the sensing regions of the sensor die, while other regions (e.g., input/output (I/O) regions) of the sensor die may remain protected. Packaging a sensor die in an InFO package may allow the form factor of the final sensor package to be smaller, may increase the mechanical reliability of the packaged sensor, and may increase the manufacturing yield as compared to other (e.g., wire bond) packaging schemes.

FIGS.1through11illustrate cross-sectional views of intermediate steps during a process for forming a package component100, in accordance with some embodiments. A single package region is illustrated, and a sensor package101(seeFIG.12) is formed in the illustrated package region. The sensor package101may be an integrated fan-out (InFO) package. It should be appreciated that the package component100includes many package regions.FIG.12illustrates a sensing device200implementing the sensor package101, in accordance with some embodiments. The sensing device200may be any device that implements the sensor package101, such as a smartphone, a tablet, or the like.

InFIG.1, a carrier substrate102is provided, and a release layer104is formed on the carrier substrate102. The carrier substrate102may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate102may be a wafer, such that multiple packages can be formed on the carrier substrate102simultaneously. The release layer104may be formed of a polymer-based material, which may be removed along with the carrier substrate102from the overlying structures that will be formed in subsequent steps. In some embodiments, the release layer104is an epoxy-based thermal-release material, which loses its adhesive property when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer104may be an ultra-violet (UV) glue, which loses its adhesive property when exposed to UV lights. The release layer104may be dispensed as a liquid and cured, may be a laminate film laminated onto the carrier substrate102, or may be the like. The top surface of the release layer104may be leveled and may have a high degree of coplanarity.

InFIG.2, a back-side redistribution structure106is formed on the release layer104. In the embodiment shown, the back-side redistribution structure106includes a dielectric layer108and a metallization pattern no (sometimes referred to as redistribution layers or redistribution lines). The back-side redistribution structure106is optional. In some embodiments, the metallization pattern no is omitted and only the dielectric layer108is formed.

The dielectric layer108is formed on the release layer104. The bottom surface of the dielectric layer108may be in contact with the top surface of the release layer104. In some embodiments, the dielectric layer108is formed of a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, the dielectric layer108is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; or the like. The dielectric layer108may be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), laminating, the like, or a combination thereof. The dielectric layer108is then patterned to form an opening112exposing portions of the release layer104. The patterning may be by an acceptable process, such as by exposing the dielectric layer108to light when the dielectric layer108is a photo-sensitive material or by etching using, for example, an anisotropic etch. The opening112has a first width W1. In some embodiments, the first width W1is in the range of from about 20030 μm to about 32030 μm, which may be large enough to accommodate an integrated circuit die.

The metallization pattern no is formed on the dielectric layer108. As an example to form metallization pattern no, a seed layer is formed over the dielectric layer108and in the opening112. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including a plurality of sub-layers formed of different materials. In some embodiments, the seed layer is a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD) or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern110. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may be a metal, like copper, titanium, tungsten, aluminum, the like, or combinations thereof. Then, the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the metallization pattern110.

It should be appreciated that the back-side redistribution structure106may include any number of dielectric layers and metallization patterns. Additional dielectric layers and metallization patterns may be formed by repeating the processes for forming the dielectric layer108and metallization pattern110. The metallization patterns may include conductive lines and conductive vias. The conductive vias may be formed during the formation of the metallization pattern by forming the seed layer and conductive material of the metallization pattern in the opening of the underlying dielectric layer. The conductive vias may therefore interconnect and electrically connect the various conductive lines. In embodiments where the back-side redistribution structure106includes multiple layers, the opening112may extend through each respective dielectric layer.

In some embodiments the back-side redistribution structure106includes a topmost dielectric or passivation layer, covering and protecting the metallization pattern110. In the embodiment shown, the topmost layer is omitted, and a subsequently formed encapsulant is used to protect the metallization pattern no.

Further, conductive vias116are formed on and extending away from the dielectric layer108. As an example to form the conductive vias116, a seed layer is formed over the back-side redistribution structure106, e.g., on the dielectric layer108and metallization pattern110. The seed layer for the conductive vias116may be different than the seed layer for the metallization pattern110, and may be further formed over the metallization pattern110. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including a plurality of sub-layers formed of different materials. In a particular embodiment, the seed layer is a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to conductive vias. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may be a metal, like copper, titanium, tungsten, aluminum, the like, or combinations thereof. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the conductive vias116. In the embodiment shown, the conductive vias116are formed directly on the dielectric layer108and are connected to the metallization pattern no by conductive lines. In other embodiments (described below), the conductive vias116are plated from features of the metallization pattern110.

InFIG.3, an integrated circuit die126is adhered to the release layer104by an adhesive128. The integrated circuit die126may be disposed in the opening112of the back-side redistribution structure106. The integrated circuit die126may be any type of die, such as a sensor die, logic die (e.g., central processing unit, microcontroller, etc.), memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), power management die (e.g., power management integrated circuit (PMIC) die), radio frequency (RF) die, micro-electro-mechanical-system (MEMS) die, signal processing die (e.g., digital signal processing (DSP) die), front-end die (e.g., analog front-end (AFE) die), the like, or a combination thereof. The integrated circuit die126has a second width W2. When the integrated circuit die126is disposed in the opening112, the second width W2is less than or equal to the first width W1(seeFIG.2). In some embodiments, the second width W2is in the range of from about 20000 μM to about 32000 μm. In other embodiments, the integrated circuit die126may be disposed over the opening112, and in such embodiments, the second width W2is greater than the first width W1.

Before being adhered to the release layer104, the integrated circuit die126may be processed according to applicable manufacturing processes to form integrated circuits in the integrated circuit die126. For example, the integrated circuit die126includes a semiconductor substrate130, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. Devices, such as transistors, diodes, capacitors, resistors, etc., may be formed in and/or on the active surface of the semiconductor substrate130and may be interconnected by interconnect structures formed by, for example, metallization patterns in one or more dielectric layers on the semiconductor substrate130to form an integrated circuit.

The integrated circuit die126further includes pads134, such as aluminum pads, copper pads, or the like, to which external connections are made. The pads134are on the active surface of the integrated circuit die126. One or more passivation films136are on the integrated circuit die126and on portions of the pads134. Openings extend through the passivation films136to expose the pads134.

In some embodiments, the integrated circuit die126is a sensor die. The sensor die may be an image sensor, an acoustic sensor, or the like. The sensor die may include one or more transducers and may also include one or more features that emit signals for measurement during operation. For example, the sensor die may be a fingerprint sensor that operates by emitting ultrasonic acoustic waves and measuring reflected waves. The integrated circuit die126has an I/O region126A and a sensing region126B at the active surface. The I/O region126A may (or may not) surround the sensing region126B. The sensing region126B has a third width W3, which is less than the second width W2. In some embodiments, the third width W3is in the range of from about 16000 μm to about 30000 μm. In some embodiments, the sensor die is packaged in an InFO package, and is packaged in a manner that allows the sensing region126B to be exposed. In some embodiments, the integrated circuit die126further includes a sensing region126C at the back surface of the integrated circuit die126. In such embodiments, the sensing die is packaged in a manner that allows the sensing region126C to also be exposed.

The adhesive128is on the back surface of the integrated circuit die126and adheres the integrated circuit die126to the release layer104. The adhesive128may be any suitable adhesive, epoxy, die attach film (DAF), or the like. The adhesive128may be applied to a back-side of the integrated circuit die126or may be applied over the surface of the carrier substrate102. For example, the adhesive128may be applied to the back-side of the integrated circuit die126before singulating to separate the integrated circuit die126. Likewise, the adhesive128may be applied in the opening112of the back-side redistribution structure106, before attaching the integrated circuit die126.

Although one integrated circuit die126is illustrated as being adhered in the illustrated package region, it should be appreciated that more integrated circuit dies126may be adhered in each package region. For example, multiple integrated circuit dies126may be adhered in each package region. In such embodiments, the integrated circuit dies126may vary in size and type. In some embodiments, the integrated circuit die126may be dies with a large footprint, such as system-on-chip (SoC) devices. In embodiments where the integrated circuit die126have a large footprint, the space available for the conductive vias116in the package regions may be limited. Use of the back-side redistribution structure106allows for an improved interconnect arrangement when the package regions have limited space available for the conductive vias116. In embodiments where a sensor die is used, logic dies, memory dies, or a combination thereof may also be included with the sensor die.

InFIG.4, an encapsulant142is formed on the various components. After formation, the encapsulant142at least laterally encapsulates the conductive vias116and integrated circuit die126. The metallization pattern no is thus disposed between the encapsulant142and the dielectric layer108. The encapsulant142may be a molding compound, epoxy, or the like. The encapsulant142may be applied by compression molding, transfer molding, or the like. The encapsulant142is then cured. In the embodiment shown, the encapsulant142is formed by transfer molding, such that the conductive vias116and integrated circuit die126are exposed after molding, and planarization step(s) (e.g., a CMP) may be omitted. Because transfer molding is used to form the encapsulant142, recesses142R may be formed in the encapsulant142, between respective ones of the conductive vias116and the integrated circuit die126. Further, a topmost surface of the passivation films136may be above a topmost surface of the encapsulant142.

When the integrated circuit die126is adhered to the release layer104, it is pressed onto the release layer104to improve adhesion of the adhesive128. The adhesive128is a malleable material. As such, during adhesion, some of the adhesive128may extrude around the edges of the integrated circuit die126, and the encapsulant142may be formed around the extruded adhesive128.FIGS.5A through5Dare detailed views of a region100A inFIG.4, showing aspects of the adhesive128, in accordance with various embodiments.

FIGS.5A and5Bshow embodiments where the first width W1of the opening112(seeFIG.2) is greater than the second width W2of the integrated circuit die126(seeFIG.3). InFIG.5A, the adhesive128contacts the encapsulant142and a sidewall of the dielectric layer108. The adhesive128has a curved portion extending from the sidewall of the integrated circuit die126to the dielectric layer108. The curved portion of the adhesive128contacts the encapsulant142. The nearest edge of the dielectric layer108is physically separated from the sidewall of the integrated circuit die126by only the adhesive128. InFIG.5B, the adhesive128contacts the encapsulant142and is physically separated from the dielectric layer108. The adhesive128has a curved portion extending from the sidewall of the integrated circuit die126to beneath the integrated circuit die126. The curved portion of the adhesive128contacts the encapsulant142. The nearest edge of the dielectric layer108is physically separated from the sidewall of the integrated circuit die126by both the adhesive128and encapsulant142.

FIG.5Cshows an embodiment where the first width W1of the opening112(seeFIG.2) is equal to the second width W2of the integrated circuit die126(seeFIG.3). InFIG.5C, the adhesive128contacts the encapsulant142, a sidewall of the dielectric layer108, and a top surface of the dielectric layer108. The adhesive128has a curved portion extending from the sidewall of the integrated circuit die126to the dielectric layer108. The curved portion of the adhesive128contacts the encapsulant142. The nearest edge of the dielectric layer108is physically separated from the sidewall of the integrated circuit die126by only the adhesive128.

FIG.5Dshows an embodiment where the first width W1of the opening112(seeFIG.2) is less than the second width W2of the integrated circuit die126(seeFIG.3). InFIG.5D, the adhesive128contacts the encapsulant142, a sidewall of the dielectric layer108, and a top surface of the dielectric layer108. The adhesive128has a curved portion extending from the sidewall of the integrated circuit die126to the dielectric layer1o8. The curved portion of the adhesive128contacts the encapsulant142. The nearest edge of the dielectric layer108is physically separated from the sidewall of the integrated circuit die126by only the adhesive128.

FIGS.6through8illustrate formation of a front-side redistribution structure144(seeFIG.8) over the conductive vias116, encapsulant142, and integrated circuit die126. The front-side redistribution structure144includes a dielectric layer146, a metallization pattern148, and a dielectric layer150. The metallization patterns may also be referred to as redistribution layers or redistribution lines. The front-side redistribution structure144is shown as an example, and one example process to form the front-side redistribution structure144is discussed herein. More or fewer dielectric layers and metallization patterns may be formed in the front-side redistribution structure144. If more dielectric layers and metallization patterns are to be formed, steps and processes discussed below may be repeated.

The front-side redistribution structure144(seeFIG.8) includes an opening152exposing the sensing region126B of the integrated circuit die126. The opening152extends through the dielectric layers146and150of the front-side redistribution structure144. The metallization pattern148is not formed in the opening152, such that the opening152is free from the materials of the front-side redistribution structure144(e.g., materials of the metallization pattern148and the dielectric layers146and150). In other words, an air gap is over the sensing region126B, the air gap being laterally disposed between portions of the front-side redistribution structure144, the air gap being free from liquid and solid materials. The opening152exposes the sensing region126B of the integrated circuit die126, allowing it to be used even when the integrated circuit die126is packaged and encapsulated. After forming the opening152, the I/O region126A of the integrated circuit die126remains covered by the front-side redistribution structure144. The opening152has a fourth width W4, which may be greater than or equal to the third width W3. In some embodiments, the fourth width W4is in the range of from about 16006 μm to about 29734 μm.

InFIG.6, the dielectric layer146is deposited on the encapsulant142, conductive vias116, passivation films136, and pads134. In some embodiments, the dielectric layer146is formed of a photo-sensitive material such as PBO, polyimide, BCB, or the like, which may be patterned using a lithography mask. The dielectric layer146may be formed by spin coating, lamination, CVD, the like, or a combination thereof. When the encapsulant142has recesses142R, portions of the dielectric layer146fill the recesses142R. The dielectric layer146is then patterned. The patterning forms openings152,154, and156which, respectively, expose the sensing region126B, pads134, and conductive vias116. The width of the opening152is greater than the widths of the openings154and156. The patterning may be by an acceptable process, such as by exposing the dielectric layer146to light when the dielectric layer146is a photo-sensitive material or by etching using, for example, an anisotropic etch. If the dielectric layer146is a photo-sensitive material, the dielectric layer146can be developed after the exposure.

InFIG.7, the metallization pattern148is formed. The metallization pattern148includes conductive lines on and extending along the major surface of the dielectric layer146. The metallization pattern148further includes conductive vias extending through the dielectric layer146to be physically and electrically connected to the conductive vias116and the integrated circuit die126(e.g., by the pads134). When the encapsulant142has recesses142R, top surfaces of the encapsulant142, conductive vias116, and integrated circuit die126may not be level (e.g., in embodiments where a planarization step is omitted). In such embodiments, the vias of the metallization pattern148that are connected to the integrated circuit die126have different lengths than the vias of the metallization pattern148that are connected to the conductive vias116.

To form the metallization pattern148, a seed layer is formed over the dielectric layer146and in the openings152,154, and156extending through the dielectric layer146. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including a plurality of sub-layers formed of different materials. In some embodiments, the seed layer is a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photo resist is then formed and patterned on the seed layer. The photo resist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photo resist corresponds to the metallization pattern148. The patterning forms openings through the photo resist to expose the seed layer. A conductive material is then formed in the openings of the photo resist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may be a metal, like copper, titanium, tungsten, aluminum, the like, or combinations thereof. The combination of the conductive material and underlying portions of the seed layer form the metallization pattern148. The photo resist and portions of the seed layer on which the conductive material is not formed are removed. The photo resist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photo resist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching.

InFIG.8, the dielectric layer150is deposited on the metallization pattern148and dielectric layer146. The dielectric layer150may be formed in a manner similar to the dielectric layer146, and may be formed of the same material as the dielectric layer146. The opening152is then extended through the dielectric layer150by patterning the dielectric layer150in a similar manner as the patterning of the dielectric layer146. After the opening152is extended, it has a first depth D1extending from a major surface of the passivation films136to a topmost surface of the dielectric layer150. In some embodiments, the first depth D1is in the range of from about 17 μm to about 25 μm (such as less than about 25 μm).

In the embodiment shown, the opening152is formed during formation of the front-side redistribution structure144. The opening152may also be formed after formation of the front-side redistribution structure144. For example, the opening152may be formed through the dielectric layers146and150by an anisotropic etch after the dielectric layers146and150are both formed.

InFIG.9, a carrier substrate de-bonding is performed to detach (or “de-bond”) the carrier substrate102from the adhesive128and the back-side redistribution structure106(e.g., the dielectric layer108). In some embodiments, the de-bonding includes projecting a light such as a laser light or an UV light on the release layer104so that the release layer104decomposes under the heat of the light and the carrier substrate102can be removed. The structure is then flipped over and placed on a tape160.

InFIG.10, openings162are formed through the dielectric layer108to expose portions of the metallization pattern no and/or conductive vias116. The openings may be formed, for example, using laser drilling, etching, or the like. Further, during the opening process, the openings112in the back-side redistribution structure106are re-formed by removing at least a portion of the adhesive128. The adhesive128may be removed for example, using laser drilling, etching, or the like. In some embodiments, the openings162are formed and the opening112is re-formed in a same process, such as a same laser drilling process. A cleaning process may be performed after the laser drilling process, to remove remaining residue of the adhesive128and dielectric layer108. In embodiments where the integrated circuit die126includes a sensing region126C at the back surface, the opening112exposes the sensing region126C. Other features such as heatsinks or acoustic backing layers may be attached to the integrated circuit die126through the opening112. The InFO package allows such features to be more easily integrated with the sensor die than a wire bond package.

InFIG.11, conductive connectors164are formed in the openings162, physically and electrically connected the metallization pattern no and/or conductive vias116. The conductive connectors164may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors164are formed by initially forming a layer of solder through such commonly used methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shapes. In some embodiments, the conductive connectors164include flux and are formed in a flux dipping process. In some embodiments, the conductive connectors164include a conductive paste such as solder paste, silver paste, or the like, and are dispensed in a printing process.

The sensor package101(seeFIG.12) is formed by performing a singulation process along scribe line regions of the package component100. The singulation may be by sawing, laser drilling, or the like along the scribe lines between adjacent package regions. The singulation process separates the adjacent package regions of the package component100. The resulting singulated sensor packages are from one of the package regions of the package component100.

InFIG.12, the sensor package101is mounted to a package substrate202using the conductive connectors164. The package substrate202may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may also be used. Additionally, the package substrate202may be a SOI substrate. Generally, a SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. The package substrate202is, in one alternative embodiment, based on an insulating core such as a fiberglass reinforced resin core. One example core material is fiberglass resin such as FR4. Alternatives for the core material include bismaleimide-triazine BT resin, or alternatively, other PCB materials or films. Build up films such as ABF or other laminates may be used for package substrate202.

The package substrate202may include active and passive devices (not shown). As one of ordinary skill in the art will recognize, a wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the design for the sensing device200. The devices may be formed using any suitable methods.

The package substrate202may also include metallization layers and vias (not shown) and bond pads204over the metallization layers and vias. The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, or the like). In some embodiments, the package substrate202is substantially free of active and passive devices.

In some embodiments, the conductive connectors164are reflowed to attach the sensor package101to the bond pads204. The conductive connectors164electrically and/or physically connect the package substrate202, including metallization layers in the package substrate202, to the sensor package101. In some embodiments, passive devices (e.g., surface mount devices (SMDs), not illustrated) may be attached to the sensor package101(e.g., bonded to the bond pads204) prior to mounting on the package substrate202. In such embodiments, the passive devices may be bonded to a same surface of the sensor package101as the conductive connectors164.

The conductive connectors164may have an epoxy flux (not shown) formed thereon before they are reflowed, with at least some of the epoxy portion of the epoxy flux remaining after the sensor package101is attached to the package substrate202. This remaining epoxy portion may act as an underfill to reduce stress and protect the joints resulting from the reflowing the conductive connectors164. In some embodiments, an underfill (not shown) may be formed between the sensor package101and the package substrate202, surrounding the conductive connectors164. The underfill may be formed by a capillary flow process after the sensor package101is attached, or may be formed by a suitable deposition method before the sensor package101is attached.

In some embodiments, some residue of the adhesive128may remain after the opening112is re-formed.FIGS.13A through13Dare detailed views of a region100A inFIG.12, in accordance with various embodiments. The embodiments ofFIGS.13A through13Dcorrespond, respectively, to the embodiments ofFIGS.5A through5D, and show embodiments where portions of the extruded adhesive128remain around sidewalls of a portion of the integrated circuit die126after the removal process. As a result, the opening112exposes the adhesive128, but may not expose sidewalls of the integrated circuit die126.

InFIG.13A, remaining portions of the adhesive128have a curved portion extending from the sidewall of the integrated circuit die126to the dielectric layer108. The nearest edge of the dielectric layer108is physically separated from the sidewall of the integrated circuit die126by only the adhesive128. InFIG.13B, remaining portions of the adhesive128have a curved portion extending from the sidewall of the integrated circuit die126to beneath the integrated circuit die126. The nearest edge of the dielectric layer108is physically separated from the sidewall of the integrated circuit die126by both the adhesive128and encapsulant142. InFIG.13C, remaining portions of the adhesive128have a curved portion extending from the sidewall of the integrated circuit die126to the dielectric layer108, with no remaining adhesive128contacting sides of the dielectric layer108. InFIG.13D, remaining portions of the adhesive128has a curved portion extending from the sidewall of the integrated circuit die126to the dielectric layer108, and also has a portion between the integrated circuit die126and dielectric layer108, with no remaining adhesive128contacting sides of the dielectric layer108.

In some embodiments, no residue of the adhesive128remains after the opening112is re-formed.FIGS.14A through14Dare detailed view of a region100A inFIG.12, in accordance with various embodiments. The embodiments ofFIGS.14A through14Dcorrespond, respectively, to the embodiments ofFIGS.5A through5D, and show embodiments where no portions of the extruded adhesive128around the integrated circuit die126remain after the removal process. As a result, the opening112extends partially into the encapsulant142and exposes sidewalls of a portion of the integrated circuit die126.

InFIG.14A, the opening112has a curved portion extending from the sidewall of the integrated circuit die126to the dielectric layer108. InFIG.14B, the opening112has a curved portion in the encapsulant142. InFIG.14C, the opening112has a curved portion extending from the sidewall of the integrated circuit die126to the dielectric layer108, with an edge of the dielectric layer108being coplanar with an edge of the integrated circuit die126. InFIG.14D, the opening112has a curved portion extending from the sidewall of the integrated circuit die126to the dielectric layer108, with an edge of the dielectric layer108being under an edge of the integrated circuit die126.

FIGS.15through16illustrate cross-sectional views of intermediate steps during a process for forming the package component100, in accordance with some other embodiments. In this embodiment, the integrated circuit die126further includes a sacrificial film166over the passivation films136and pads134. The sacrificial film166is formed of a photo-sensitive polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like.

InFIG.15, the encapsulant142is formed. The encapsulant142is formed by compression molding, such that the conductive vias116and integrated circuit die126are buried after the molding.

InFIG.16, a planarization process is performed on the encapsulant142to expose the conductive vias116and sacrificial film166. The planarization process may also grind the sacrificial film166. Top surfaces of the conductive vias116, encapsulant142, and sacrificial film166are coplanar after the planarization process. The planarization process may be, for example, a chemical-mechanical polish (CMP), a grinding process, or the like. The sacrificial film166is then removed, exposing the sensing region126B of the integrated circuit die126. When the sacrificial film166is a photo-sensitive polymer, it may be removed by exposure and development.

FIG.17illustrates the sensing device200. Due to removal of the sacrificial film166, a topmost surface of the passivation films136is below a topmost surface of the encapsulant142. The opening152has a second depth D2extending from a major surface of the passivation films136to a topmost surface of the dielectric layer150. The second depth D2is greater than the first depth D1. In some embodiments, the second depth D2is in the range of from about 22.5 μm to about 32.5 μm.

FIGS.18through19illustrate cross-sectional views of intermediate steps during a process for forming the package component100, in accordance with some other embodiments. In this embodiment, the integrated circuit die126further includes die connectors138, such as conductive pillars (for example, formed of a metal such as copper), which extend through the openings in the passivation films136to be physically and electrically connected to respective one of the pads134. The die connectors138may be formed by, for example, plating, or the like. The die connectors138are thus electrically connected to the integrated circuits of the integrated circuit die126. A dielectric material140is over the active surface of the integrated circuit die126, such as on the passivation films136and the die connectors138. The dielectric material140laterally encapsulates the die connectors138, and the dielectric material140is laterally coterminous with the integrated circuit die126. The dielectric material140may be a nitride such as silicon nitride or the like, and may be formed, for example, by CVD or the like. The dielectric material140includes an opening168exposing the sensing region126B of the integrated circuit die126, which may be formed by acceptable photolithography and etching techniques. The sacrificial film166is initially formed over the dielectric material140and in the opening168.

InFIG.18, the encapsulant142is formed. The encapsulant142is formed by compression molding, such that the conductive vias116and integrated circuit die126are buried after the molding.

InFIG.19, a planarization process is performed on the encapsulant142to expose the conductive vias116and the die connectors138. The planarization process may also grind the sacrificial film166. Topmost surfaces of the conductive vias116, die connectors138, encapsulant, and dielectric material140are coplanar after the planarization process. The planarization process may be, for example, a CMP, a grinding process, or the like. The sacrificial film166is then removed, exposing the sensing region126B of the integrated circuit die126. When the sacrificial film166is a photo-sensitive polymer, it may be removed by exposure and development.

FIG.20illustrates the sensing device200. The opening168has a fifth width W5, which may be less than the fourth width W4of the opening152. In some embodiments, the fifth width W5is in the range of from about 15806 μm to about 29534 μm. The openings152and168have a combined third depth D3extending from a major surface of the passivation films136to a topmost surface of the dielectric layer150. The third depth D3is greater than the second depth D2. In some embodiments, the third depth D3is in the range of from about 22.5 μm to about 32.5 μm.

FIGS.21,22, and23illustrate the sensing device200, in accordance with some other embodiments.FIGS.21,22, and23are, respectively, variations of the embodiments shown inFIGS.12,17, and20. In these embodiments, the opening112is not formed through the back-side redistribution structure106. The opening112may not be formed in embodiments where the integrated circuit die126has no sensing region126C at its back surface. Such embodiments may have a lower cost of manufacturing.

FIGS.24A through24Cillustrate the package component100, in accordance with other embodiments.FIGS.24A through24Cshow variations of the embodiment ofFIG.21(e.g., where the encapsulant142is formed by transfer molding and the opening112is not formed through the back-side redistribution structure106), however, it should be appreciated that the variations shown inFIGS.24A through24Cmay be combined with any of the other embodiments described herein.FIG.24Ashows a variation of the package component100where the metallization pattern no is omitted, and only the dielectric layer108is formed.FIGS.24B and24Cshow variations where the conductive vias116are plated from features of the metallization pattern110. For example, the metallization pattern no may include pads114, from which the conductive vias116are plated (e.g., using a same seed layer as the pads114). InFIG.24B, the width of the pads114is greater than the width of the conductive vias116. For example, in such embodiments, the pads114may have a width in the range of from about 160 μm to about 320 μm, and the conductive vias116may have a width in the range of from about 150 μm to about 280 μm. InFIG.24C, the width of the pads114is less than the width of the conductive vias116. For example, in such embodiments, the pads114may have a width in the range of from about 140 μm to about 270 μm, and the conductive vias116may have a width in the range of from about 150 μm to about 280 μm.

Embodiments may achieve advantages. Packaging a sensor die (e.g., the integrated circuit die126) in an InFO package (e.g., the sensor package101) may allow the form factor of the final sensor package to be decreased. For example, some InFO sensor packages may be up to 500 μm smaller than wire bond sensor packages. Further, wire loops over the I/O region126A may be avoided, reducing the distance between the sensing region126B and a target, thereby increasing sensitivity of the sensor die. The mechanical reliability of the sensor package may also be improved over other (e.g., wire bond) packaging schemes. The manufacturing yield of InFO packages may also be greater than that of wire bond packages. Because an InFO package exposes less surface area of a sensor die than other packaging schemes, sensing regions of the sensor die may be easier to keep clean, improving sensing accuracy. Finally, supporting layers or heatsinks may be easier to integrated on an InFO package than on a wire bond package.

In an embodiment, a device includes: a sensor die having a first surface and a second surface opposite the first surface, the sensor die having an input/output region and a first sensing region at the first surface; an encapsulant at least laterally encapsulating the sensor die; a conductive via extending through the encapsulant; and a front-side redistribution structure on the first surface of the sensor die, the front-side redistribution structure being connected to the conductive via and the sensor die, the front-side redistribution structure covering the input/output region of the sensor die, the front-side redistribution structure having a first opening exposing the first sensing region of the sensor die.

In some embodiments, the device further includes: a back-side redistribution structure on the second surface of the sensor die, the back-side redistribution structure being connected to the conductive via. In some embodiments of the device, the back-side redistribution structure includes: a dielectric layer; and a metallization pattern disposed between the dielectric layer and the encapsulant, the metallization pattern being electrically connected to the conductive via. In some embodiments of the device, the sensor die has a second sensing region at the second surface, and the back-side redistribution structure has a second opening exposing the second sensing region of the sensor die. In some embodiments of the device, the second opening extends partially into the encapsulant and exposes sidewalls of a portion of the sensor die. In some embodiments, the device further includes: an adhesive surrounding a portion of the sensor die, the second opening exposing the adhesive. In some embodiments of the device, the sensor die includes: a semiconductor substrate; pads on the semiconductor substrate, the pads being connected to the front-side redistribution structure; and a passivation film on the pads and the semiconductor substrate, a topmost surface of the passivation film being above a topmost surface of the encapsulant. In some embodiments of the device, the sensor die includes: a semiconductor substrate; pads on the semiconductor substrate, the pads being connected to the front-side redistribution structure; and a passivation film on the pads and the semiconductor substrate, a topmost surface of the passivation film being below a topmost surface of the encapsulant. In some embodiments of the device, the sensor die includes: a semiconductor substrate; pads on the semiconductor substrate, the pads being connected to the front-side redistribution structure; a passivation film on the pads and the semiconductor substrate; and a dielectric layer over the passivation film, the dielectric layer having a second opening exposing the first sensing region of the sensor die, a width of the second opening being less than a width of the first opening. In some embodiments of the device, the first sensing region of the sensor die and the first opening of the front-side redistribution structure have the same width.

In an embodiment, a method includes: placing a sensor die adjacent to a conductive via, the sensor die having an input/output region and a first sensing region; encapsulating the sensor die and the conductive via with an encapsulant; forming a first dielectric layer on the encapsulant, the sensor die, and the conductive via; patterning the first dielectric layer with a first opening exposing the conductive via, a second opening exposing the input/output region of the sensor die, and a third opening exposing the first sensing region of the sensor die; forming a first metallization pattern extending through the first opening and the second opening of the first dielectric layer, the third opening of the first dielectric layer being free from the first metallization pattern; forming a second dielectric layer on the first metallization pattern and the first dielectric layer; and extending the third opening through the second dielectric layer to expose the first sensing region of the sensor die.

In some embodiments of the method, the sensor die includes a semiconductor substrate and pads on the semiconductor substrate, where encapsulating the sensor die includes: forming the encapsulant by transfer molding such that a recess in the encapsulant is disposed between the semiconductor substrate and the conductive via. In some embodiments of the method, the sensor die includes a semiconductor substrate and pads on the semiconductor substrate, where encapsulating the sensor die includes: forming the encapsulant by compression molding; and planarizing the encapsulant such that top surfaces of the encapsulant and the conductive via extend above a top surface of the semiconductor substrate. In some embodiments of the method, the sensor die further includes a sacrificial film over the semiconductor substrate, and further including: removing the sacrificial film to form a fourth opening exposing the first sensing region of the sensor die. In some embodiments, the method further includes: plating the conductive via on a third dielectric layer; and forming a second metallization pattern on the third dielectric layer. In some embodiments of the method, placing the sensor die includes: adhering the sensor die to the third dielectric layer with an adhesive. In some embodiments, the method further includes: forming a fourth opening in the third dielectric layer. In some embodiments of the method, placing the sensor die includes adhering the sensor die in the fourth opening with an adhesive, and further including: after encapsulating the sensor die, removing at least a portion of the adhesive to expose a second sensing region at a back surface of the sensor die.

In an embodiment, a method includes: forming a back-side redistribution structure, the back-side redistribution structure having a first opening; adhering a sensor die in the first opening of the back-side redistribution structure with an adhesive, the sensor die having a first surface and a second surface opposite the first surface; encapsulating the sensor die with an encapsulant; forming a front-side redistribution structure over the encapsulant and the sensor die, the front-side redistribution structure having a second opening exposing the second surface of the sensor die; and after forming the front-side redistribution structure, removing the adhesive to expose the first surface of the sensor die.

In some embodiments, the method further includes: attaching the back-side redistribution structure to a package substrate with conductive connectors, the conductive connectors extending through a dielectric layer of the back-side redistribution structure to contact a metallization pattern of the back-side redistribution structure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.