Patent ID: 12230676

The drawings are not necessarily to scale. The drawings are merely schematic representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention. In the drawings, like numbering represents like elements.

DETAILED DESCRIPTION

Detailed embodiments of the claimed structures and methods are disclosed herein; however, it can be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. This invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

For purposes of the description hereinafter, terms such as “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. Terms such as “above”, “overlying”, “atop”, “on top”, “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure may be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.

In the interest of not obscuring the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations that are known in the art may have been combined together for presentation and for illustration purposes and in some instances may have not been described in detail. In other instances, some processing steps or operations that are known in the art may not be described at all. It should be understood that the following description is rather focused on the distinctive features or elements of various embodiments of the present invention.

It is understood that although the disclosed embodiments include a detailed description of an exemplary nanosheet FET architecture having silicon and silicon germanium nanosheets, implementation of the teachings recited herein are not limited to the particular FET architecture described herein. Rather, embodiments of the present invention are capable of being implemented in conjunction with any other type of FET device now known or later developed.

Parasitic source-to-drain “punch-through” leakage through the substrate increases as the transistor gate length is scaled down. Due to the parasitic channel being below the nanosheet stack, the source/drain leakage current is very challenging for nanosheet transistors to suppress. A bottom dielectric isolation (BDI) layer which separates epitaxy of the source and of the drain regions from touching the substrate provides a solution to block the leakage in the sub-nanosheet region by adding an insulator layer beneath the source/drain and channel regions.

However, in current process of record (POR), the BDI is typically formed by a single layer of dielectric material that can be easily damaged during processes such as spacer and inner spacer formation, source/drain contact patterning and epitaxial pre-cleans. This damage can erode the BDI thickness leading back to increased source/drain leakage and degradation in device performance.

Therefore, embodiments of the present disclosure, provide a tri-layer bottom dielectric isolation (BDI), and a method of making the same, consisting of an isolation material sandwiched between layers of a high-k dielectric material. The proposed tri-layer BDI involves etch-resistant materials that can prevent over etching the BDI layer and electrically isolate source/drain epi regions from the semiconductor substrate. This in turn may reduce current leakage via the semiconductor substrate and improve device performance.

Embodiments by which the tri-layer bottom dielectric isolation can be formed to electrically isolate source/drain epi regions from the semiconductor substrate are described in detailed below by referring to the accompanying drawings inFIGS.1-13.

Referring now toFIG.1, a cross-sectional view of a semiconductor structure100including a nanosheet stack10formed over a semiconductor substrate102is shown, according to an embodiment of the present disclosure.

In this embodiment, an alternating sequence of layers of sacrificial semiconductor material and layers of semiconductor channel material vertically stacked one on top of another in a direction perpendicular to the semiconductor substrate102forms the nanosheet stack10, as illustrated in the figure. Specifically, the alternating sequence includes a nanosheet stack sacrificial layer104above the semiconductor substrate102, a sacrificial semiconductor layer106above the nanosheet stack sacrificial layer104, and a semiconductor channel layer108. In the example depicted in the figure, alternating sacrificial semiconductor layers106and semiconductor channel layers108are formed in a stack above the nanosheet stack sacrificial layer104on the semiconductor substrate102. The term sacrificial, as used herein, means a layer or other structure, that is (or a part thereof is) removed before completion of the final device. For instance, in the example being described, portions of the sacrificial semiconductor layers106will be removed from the stack in the channel region of the device to permit the semiconductor channel layers108to be released from the nanosheet stack10. It is notable that while in the present example the sacrificial semiconductor layers106and the semiconductor channel layers108are made of silicon germanium (SiGe) and silicon (Si), respectively, any combination of sacrificial and channel materials may be employed in accordance with the present techniques. For example, one might instead employ selective etching technology which permits Si to be used as the sacrificial material between SiGe channel layers.

The semiconductor substrate102may be, for example, a bulk substrate, which may be made from any of several known semiconductor materials such as, for example, silicon, germanium, silicon-germanium alloy, and compound (e.g. III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide, or indium gallium phosphide. Typically, the semiconductor substrate102may be approximately, but is not limited to, several hundred microns thick. In other embodiments, the semiconductor substrate102may be a layered semiconductor such as a silicon-on-insulator or SiGe-on-insulator, where a buried insulator layer, separates a base substrate from a top semiconductor layer.

With continued reference toFIG.1, a first layer in the stack (a sacrificial layer), i.e., the nanosheet stack sacrificial layer104, is formed on the semiconductor substrate102. According to an exemplary embodiment, the nanosheet stack sacrificial layer104in the nanosheet stack10is formed using an epitaxial growth process. For instance, in the described embodiment, the nanosheet stack sacrificial layer104is formed by epitaxially growing a layer of SiGe with a germanium concentration varying between approximately 50 atomic percent to approximately 70 atomic percent, and ranges therebetween. The higher concentration of germanium atoms allows the nanosheet stack sacrificial layer104to be subsequently removed selective to the remaining alternating layers of the nanosheet stack10, as will be described in detail below. By way of example only, the nanosheet stack sacrificial layer104may be formed having a thickness varying from approximately 20 nm to approximately 35 nm, although thicknesses greater than 20 nm and less than 35 nm may also be used.

In general, layers in the nanosheet stack10(e.g., SiGe/Si layers) can be formed by epitaxial growth by using the semiconductor substrate102as the seed layer. Terms such as “epitaxial growth and/or deposition” and “epitaxially formed and/or grown” refer to the growth of a semiconductor material on a deposition surface of a semiconductor material, in which the semiconductor material being grown has the same or substantially similar crystalline characteristics as the semiconductor material of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, an epitaxial semiconductor material has the same or substantially similar crystalline characteristics as the deposition surface on which it is formed. For example, an epitaxial semiconductor material deposited on a {100} crystal surface will take on a {100} orientation. In some embodiments, epitaxial growth and/or deposition processes are selective to forming on a semiconductor surface, and do not deposit material on dielectric surfaces, such as silicon dioxide or silicon nitride surfaces.

Non-limiting examples of various epitaxial growth processes include rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), metalorganic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), limited reaction processing CVD (LRPCVD), and molecular beam epitaxy (MBE). The temperature for an epitaxial deposition process can range from 500° C. to 900° C. Although higher temperatures typically results in faster deposition, the faster deposition may result in crystal defects and film cracking.

A number of different precursors may be used for the epitaxial growth of the alternating sequence of SiGe/Si layers in the nanosheet stack10. In some embodiments, a gas source for the deposition of epitaxial semiconductor material includes a silicon containing gas source, a germanium containing gas source, or a combination thereof. For example, an epitaxial silicon layer may be deposited from a silicon gas source including, but not necessarily limited to, silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source including, but not necessarily limited to, germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane and combinations thereof. While an epitaxial silicon germanium alloy layer can be formed utilizing a combination of such gas sources. Carrier gases like hydrogen, helium and argon can be used.

With continued reference toFIG.1, similar to the nanosheet stack sacrificial layer104, the sacrificial semiconductor layers106are formed by epitaxially growing a layer of SiGe. However, the germanium concentration of the sacrificial semiconductor layers106varies from approximately 20 atomic percent to approximately 40 atomic percent. In an exemplary embodiment, the sacrificial semiconductor layers106are made of SiGe with a germanium concentration of approximately 25 atomic percent.

To continue building the nanosheet stack10, the semiconductor channel layers108are formed by epitaxially growing a Si layer. As depicted in the figure, the sacrificial semiconductor layers106and the semiconductor channel layers108in the nanosheet stack10are thinner than the underlying nanosheet stack sacrificial layer104and have a substantially similar or identical thickness. As shown inFIG.1, the nanosheet stack10is grown by forming (SiGe) sacrificial semiconductor layers106and (Si) semiconductor channel layers108in an alternating manner onto the nanosheet stack sacrificial layer104. Accordingly, each of the sacrificial semiconductor layers106and the semiconductor channel layers108in the nanosheet stack10can be formed in the same manner as described above, e.g., using an epitaxial growth process, to a thickness varying from approximately 6 nm to approximately 12 nm, although other thicknesses are within the contemplated scope of the invention.

Thus, each of the layers in the nanosheet stack10have nanoscale dimensions, and thus can also be referred to as nanosheets. Further, as highlighted above, the (Si) semiconductor channel layers108in the nanosheet stack10will be used to form the channel layers of the device. Consequently, the dimensions of the semiconductor channel layers108dictate the dimensions of the channel region of the semiconductor structure100.

As highlighted above, the goal is to produce a stack of alternating (sacrificial and channel) SiGe and Si layers on the wafer. The number of layers in the stack can be tailored depending on the particular application. Thus, the configurations depicted and described herein are merely examples meant to illustrate the present techniques. For instance, the present nanosheet stack10can contain more or fewer layers than are shown in the figures.

The nanosheet stack10can be used to produce a gate all around device that includes vertically stacked semiconductor channel material nanosheets for a positive channel Field Effect Transistor (hereinafter “p-FET”) or a negative channel Field Effect Transistor (hereinafter “n-FET”) device. The cross-sectional view ofFIG.1runs along a length of the nanosheet stack10, where the nanosheet stack10runs from left to right.

Referring now toFIG.2, a 3D view of the semiconductor structure100is shown following the patterning of a nanosheet fin (hereinafter “fin”)202from the nanosheet stack10(FIG.1), according to an embodiment of the present disclosure. The fin202can be formed by, for example, a photolithographic patterning and etching process that removes portions of the nanosheet stack10(FIG.1) and portions of the semiconductor substrate102. Any suitable etching process can be used such as, for example, reactive ion etching (RIE).

Etching generally refers to the removal of a material from a substrate (or structures formed on the substrate), and is often performed with a mask in place so that material may selectively be removed from certain areas of the substrate, while leaving the material unaffected, in other areas of the substrate. There are generally two categories of etching, (i) wet etch and (ii) dry etch. Wet etch is performed with a solvent (such as an acid) which may be chosen for its ability to selectively dissolve a given material (such as oxide), while, leaving another material (such as polysilicon) relatively intact. This ability to selectively etch given materials is fundamental to many semiconductor fabrication processes. A wet etch will generally etch a homogeneous material (e.g., oxide) isotropically, but a wet etch may also etch single-crystal materials (e.g., silicon wafers) anisotropically. Dry etch may be performed using a plasma. Plasma systems can operate in several modes by adjusting the parameters of the plasma. Ordinary plasma etching produces energetic free radicals, neutrally charged, that react at the surface of the wafer. Since neutral particles attack the wafer from all angles, this process is isotropic. Ion milling, or sputter etching, bombards the wafer with energetic ions of noble gases which approach the wafer approximately from one direction, and therefore this process is highly anisotropic. RIE operates under conditions intermediate between sputter and plasma etching and may be used to produce deep, narrow features, such as shallow trench isolation (STI) trenches.

It should be noted that portions of the semiconductor substrate102removed during the photolithographic patterning process are subsequently filled with an insulating material to form STI regions210. The process of forming the STI regions210is standard and well-known in the art, it typically involves depositing the insulating material to substantially fill areas of the semiconductor structure100between adjacent fins202(not shown) for electrically isolating the fin202. The STI regions210may be formed by, for example, chemical vapor deposition (CVD) of a dielectric material. Non-limiting examples of dielectric materials to form the STI regions210include silicon oxide, silicon nitride, hydrogenated silicon carbon oxide, silicon based low-k dielectrics, flowable oxides, porous dielectrics, or organic dielectrics including porous organic dielectrics.

Referring now toFIG.3, a 3D view of the semiconductor structure100depicting the formation of a dummy gate304is shown, according to an embodiment of the present disclosure. The dummy gate304is formed and patterned over a top surface and along sidewalls of the fin202. The dummy gate304can be formed using conventional techniques known in the art. For example, the dummy gate304may be formed from amorphous silicon (a-Si). A hard mask308is typically formed over the dummy gate304to act as an etch stop. The hard mask308is generally formed from silicon nitride, silicon oxide, an oxide/nitride stack, or similar materials and configurations.

Referring now toFIG.4, a 3D view of the semiconductor structure100is shown after removing the nanosheet stack sacrificial layer104, according to an embodiment of the present disclosure. As depicted in the figure, removal of the nanosheet stack sacrificial layer104creates an opening or air gap402(FIG.5) in the semiconductor structure100, in the area from which the nanosheet stack sacrificial layer104was removed.FIG.5shows a cross-sectional view of the semiconductor structure100taken along line A-A′.

In an embodiment, the nanosheet stack sacrificial layer104is removed selective to the semiconductor substrate102, the sacrificial semiconductor layers106, the semiconductor channel layers108, the dummy gate304and the hard mask308. For example, a highly selective dry etch process can be used to selectively remove the nanosheet stack sacrificial layer104.

Referring now toFIG.6, a cross-sectional view of the semiconductor structure100taken along line A-A′ (FIG.4) is shown after forming a high-k dielectric layer620followed by a layer of a spacer material624, according to an embodiment of the present disclosure. As depicted in the figure, the high-k dielectric layer620is formed along an upper surface of the opening402(FIG.5), along a lower surface of the opening402(FIG.5) and on exposed surfaces of the semiconductor structure100. Specifically, the high-k dielectric layer620is also formed on exposed horizontal surfaces of the uppermost semiconductor channel layer108(i.e., horizontal surfaces not covered by the dummy gate304), vertical side surfaces (or opposite sidewalls) of the dummy gate304, and vertical side surfaces (or opposite sidewalls) and an upper surface of the hard mask308.

The high-k dielectric layer620may not entirely fill the opening402(FIG.5), leaving an innermost portion of the opening402(FIG.5) open for deposition of the spacer material624. Stated differently, deposition of the spacer material624occurs within a remainder of the opening402(FIG.5), with layers of the high-k dielectric layer620above the spacer material624and below the spacer material624, as depicted in the figure. More particularly, a (top) portion of the high-k dielectric layer620below the lowermost sacrificial semiconductor layer106is located above the spacer material624, while a (bottom) portion of the high-k dielectric layer620above the semiconductor substrate102is disposed below the spacer material624.

Accordingly, by depositing the spacer material624between layers of the high-k dielectric layer620, a tri-layer bottom dielectric isolation (BDI)640is formed within the opening402(FIG.5) which may provide an enhanced bottom dielectric isolation region for preventing source/drain leakage via the semiconductor substrate102.

According to an embodiment, the high-k dielectric layer620includes a material highly resistant to etching. Non-limiting examples of etch-resistant materials for forming the high-k dielectric layer620may include metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

The high-k dielectric layer620may be deposited using typical deposition techniques including, for example, atomic layer deposition (ALD). A thickness of the high-k dielectric layer620may vary from approximately 2 nm to approximately 3 nm, and ranges therebetween.

With continued reference toFIG.6, in addition to filling a remaining space of the opening402(FIG.5), the spacer material624may also cover upper exposed surfaces of the semiconductor structure100, as shown in the figure. Particularly, the spacer material624may be deposited above the high-k dielectric layer620located or disposed above the horizontal surface of the uppermost semiconductor channel layer108, above the high-k dielectric layer620located above the vertical side surfaces of the dummy gate304, and above the high-k dielectric layer620located on the vertical side surfaces and the upper surface of the hard mask308.

Non-limiting examples of various materials for forming the spacer material624may include silicon oxycarbide (SiOC), silicon carbon nitride (SiCN), silicon carbide (SiC), aluminum oxide (AlOx), and the like.

The spacer material624may be deposited using typical deposition techniques, for example, atomic layer deposition (ALD), molecular layer deposition (MLD), and chemical vapor deposition (CVD). A thickness of the spacer material624located between layers of the high-k dielectric layer620depends on a size of the remaining space. In an embodiment, the spacer material624may be at least 3 nm thick. In other embodiments, the spacer material624may be approximately 5 nm to approximately 20 nm thick.

At this point of the semiconductor manufacturing process, the semiconductor structure100, as depicted in the figure, includes a first portion of the high-k dielectric layer620over the semiconductor substrate102, the spacer material624above the first portion of the high-k dielectric layer620, a second portion of the high-k dielectric layer620above the spacer material624, all beneath the fin202including the alternating sacrificial semiconductor layers106and semiconductor channel layers108.

Referring now toFIG.7, a cross-sectional view of the semiconductor structure100taken along line A-A′ (FIG.4) is shown after etching the high-k dielectric layer620and the spacer material624, according to an embodiment of the present disclosure.

In this embodiment, a directional etch is conducted on the semiconductor structure100to partially remove bottom portions of the spacer material624and bottom portions of the high-k dielectric layer620located above the uppermost semiconductor channel layer108of the fin202. Stated differently, bottom portions of the spacer material624and bottom portions of the high-k dielectric layer620parallel to the uppermost semiconductor channel layer108are removed via a directional etch process. As illustrated in the figure, upper portions of the spacer material624and upper portion of the high-k dielectric layer620located on opposing sidewalls and an upper surface of the hard mask308may also be removed during the directional etch process exposing a top portion of the hard mask308in preparation for a replacement metal gate process.

In an exemplary embodiment, a reactive-ion-etching (RIE) process can be performed on the semiconductor structure100to remove bottom and upper portions of the spacer material624and high-k dielectric layer620.

Referring now toFIG.8, a cross-sectional view of the semiconductor structure100taken along line A-A′ (FIG.4) is shown after forming source/drain recesses802, according to an embodiment of the present disclosure.

As shown in the figure, exposed portions of the fins202are removed from the semiconductor structure100to form source/drain recesses802. As may be understood source/drain regions of the semiconductor structure100will be formed on the source/drain recesses802, as will be described in detail below. Specifically, portions of the fins202extending outwards from the high-k-dielectric layer620and dummy gate304(i.e., portions of the fins202not covered by the high-k-dielectric layer620and dummy gate304) are removed from the semiconductor structure100. Remaining portions of the fins202below the high-k dielectric layer620and below the dummy gate304may be vertically aligned.

In this embodiment, upper portions of the spacer material624along the dummy gate304and upper portions of the hard mask308can be used as a mask to recess portions of the fins202that are not under the upper portions of the spacer material624and high-k dielectric layer620and below the dummy gate304, as illustrated in the figure. In an exemplary embodiment, a RIE process can be used to recess such portions of the fins202. Because the fin etch is being performed before the dummy gate replacement steps (described in detail below), the semiconductor device fabrication processes described herein can be referred to as a fin first process.

It should be noted that due to the high-k material forming the high-k dielectric layer620being harder than currently used materials, the high-k dielectric layer620provides an improved etch stop that may prevent punch-through of the recess etch to the semiconductor substrate102.

Referring now toFIG.9, a cross-sectional view of the semiconductor structure100taken along line A-A′ (FIG.4) is shown after forming inner spacers902, source/drain regions910and an interlevel dielectric layer920, according to an embodiment of the present disclosure.

In this embodiment, an outer portion of each of the sacrificial semiconductor layers106may be removed using methods known in the art. The inner spacers902may be formed within an indented cavity (not shown) of the sacrificial semiconductor layers106. As depicted in the figure, outer vertical sides of the inner spacers902may vertically align with the semiconductor channel layers108, and thus with upper portions of the high-k dielectric layer620and spacer material624located on opposing sidewalls of the dummy gate304.

The inner spacers902can be formed, for example, by conformal deposition of an inner spacer material that pinches off the indented cavity (not shown) formed after recessing of the sacrificial semiconductor layers106. The inner spacers902may include any suitable dielectric material, such as silicon dioxide or silicon nitride, and may include a single layer or multiple layers of dielectric materials.

It should be noted that since the material forming the high-k dielectric layer620is substantially more etch-resistant than materials used in current art, the high-k dielectric layer620may also prevent over-etch of the bottom dielectric isolation (BDI)640during processing steps such as SiGe indentation etch, inner spacer etch, and epitaxial process pre-clean steps.

After forming the inner spacers902, source/drain regions910can be formed on the source/drain recesses802shown inFIG.8. The source/drain regions910can be formed using an epitaxial layer growth process on the exposed ends of the semiconductor channel layers108.

As depicted in the figure, the source/drain regions910are formed on opposing sides of the fins202in direct contact with end portions of the semiconductor channel layers108and end portions of the inner spacers902surrounding the sacrificial semiconductor layers106. The source/drain regions910are located above the tri-layer bottom dielectric isolation640. Specifically, the source/drain regions910are disposed above the upper portion of the high-k dielectric layer620in the tri-layer bottom dielectric isolation640. Thus, the tri-layer bottom dielectric isolation640may isolate the source/drain regions910from the semiconductor substrate102preventing epitaxial growth from the semiconductor substrate102. This critical feature withstands epitaxial patterning and pre-cleaning steps to prevent erosion and thinning. This may reduce current leakage through the semiconductor substrate102.

After forming the source/drain regions910, an interlevel dielectric (ILD) layer920is formed to fill voids in the semiconductor structure100. The interlevel dielectric layer920can be formed by, for example, CVD of a dielectric material. Non-limiting examples of dielectric materials to form the interlevel dielectric layer920may include silicon oxide, silicon nitride, hydrogenated silicon carbon oxide, silicon based low-k dielectrics, flowable oxides, porous dielectrics, or organic dielectrics including porous organic dielectrics.

Referring now toFIG.10, a cross-sectional view of the semiconductor structure100taken along line A-A′ (FIG.4) is shown after a planarization process and removal of the hard mask308and dummy gate304, according to an embodiment of the present disclosure.

After deposition of the interlevel dielectric layer920, a planarization process, such as a chemical mechanical polishing (CMP), can be conducted on the semiconductor structure100. This process may expose a top surface of the dummy gate304(FIG.9) in preparation for removal of the dummy gate304(FIG.9).

In an exemplary embodiment, the dummy gate304(FIG.9) can be removed by known etching processes including, for example, RIE or chemical oxide removal (COR). In a gate-last fabrication process, the removed dummy gate304(FIG.9) is thereafter replaced with a metal gate (not shown) as known in the art. A recess1010remains on the semiconductor structure100after removal of the dummy gate304(FIG.9). As illustrated in the figure, the recess1010exposes inner vertical surfaces of the high-k dielectric layer620and a top horizontal surface of the uppermost semiconductor channel layer108.

Referring now toFIG.11, a cross-sectional view of the semiconductor structure100taken along line A-A′ (FIG.4) is shown after removing portions of the high-k dielectric layer620exposed by the recess1010, according to an embodiment of the present disclosure.

In this embodiment, an isotropic etch can be conducted on the semiconductor structure100to remove vertical surfaces of the high-k dielectric layer620exposed by the recess1010and located on opposing sidewalls of the spacer material624, as depicted inFIG.10. Horizontal portions of the high-k dielectric layer920located above the uppermost semiconductor channel layer108and below the spacer material624remain in the semiconductor structure100, as depicted inFIG.11. In an exemplary embodiment, a wet etch or plasma etch can be performed on the semiconductor structure100to remove vertical portions of the high-k dielectric layer620from sidewalls of the spacer material624.

The sacrificial semiconductor layers106can now be removed from the semiconductor structure100. In an exemplary embodiment, the sacrificial semiconductor layers106can be removed by known etching processes including, for example, RIE, wet etch or dry gas (HCl). Removal of the sacrificial semiconductor layers106create cavities (not shown) between the inner spacers902that will subsequently be filled with corresponding work function metals, as will be described in detail below.

Referring now toFIG.12, a cross-sectional view of the semiconductor structure100taken along line A-A′ (FIG.4) is shown after deposition of a gate dielectric stack1210and a metal gate stack1212, according to an embodiment of the present disclosure.

The gate dielectric stack1210is formed within the recess1010(FIG.11) and cavities formed within the inner spacers902after removal of the sacrificial semiconductor layers106. In some embodiments, the gate dielectric stack1210includes a layer of silicon oxide and a layer of a high-k dielectric material, such as a hafnium based material. The metal gate stack1212is deposited above the gate dielectric stack1210to complete the gate formation. The metal gate stack1212may include one or more work function metals such as, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), titanium aluminum carbide (TiAlC), and conducting metals including, for example, aluminum (Al), tungsten (W) or cobalt (Co). As can be appreciated inFIG.12, the metal gate stack1212surround (stacked) semiconductor channel layers108. In some embodiments, a gate cap1216may be formed above the metal gate stack1212.

After forming the gate dielectric stack1210, the metal gate stack1212and the gate cap1216, a chemical mechanical polishing (CMP) may be conducted to remove excess material and polish upper surfaces of the semiconductor structure100.

Referring now toFIG.13, a cross-sectional view of the semiconductor structure100taken along line A-A′ (FIG.4) is shown after forming source/drain contacts1320, according to an embodiment of the present disclosure.

As illustrated in the figure, source/drain contacts1320extends through the source/drain regions910. The process of forming source/drain contacts is standard and well-known in the art. Typically, the process includes forming trenches (not shown) within the interlevel dielectric layer920and subsequently filling the trenches with a conductive material or a combination of conductive materials to form the source/drain contacts1320. The conductive material filling the source/drain contacts1320includes a conductive metal, for example, aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The conductive material may be deposited by a suitable deposition process, for example, CVD, PECVD, PVD, plating, thermal or e-beam evaporation, or sputtering. A planarization process, for example, CMP, is performed to remove any conductive material from upper surfaces of the semiconductor structure100.

Although not shown in the figure, gate contacts to the metal gate stack1212may also be formed on the semiconductor structure100using similar conductive materials and analogous processing techniques as for the source/drain contacts1320.

Therefore, embodiments of the present disclosure, provide a tri-layer bottom dielectric isolation (BDI) region located between the nanosheet stack10of alternating sacrificial semiconductor layers106and semiconductor channel layers108and the semiconductor substrate102in which an isolation material (i.e., the spacer material624) is sandwiched between layers of a high-k dielectric material (i.e., the high-k dielectric layer620) for providing a BDI consisting of etch-resistant materials that can prevent etch-out problems and electrically isolate source/drain epi regions from the semiconductor substrate102. This in turn may reduce leakage via the semiconductor substrate102and improve device performance.

The method as described above is used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. “Optional” or “optionally” means that the subsequently described event or circumstance may or may not occur, and that the description includes instances where the event occurs and instances where it does not.

Spatially relative terms, such as “inner,” “outer,” “beneath,” “below,” “lower,” “above,” “upper,” “top,” “bottom,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms may be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the example term “below” may encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about”, “approximately” and “substantially”, are not to be limited to the precise value specified. In at least some instances, the approximating language may correspond to the precision of an instrument for measuring the value. Here and throughout the specification and claims, range limitations may be combined and/or interchanged, such ranges are identified and include all the sub-ranges contained therein unless context or language indicates otherwise. “Approximately” as applied to a particular value of a range applies to both values, and unless otherwise dependent on the precision of the instrument measuring the value, may indicate +/−10% of the stated value(s).

The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.