Patent ID: 12256167

DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS

In order for the content of the disclosure to be more comprehensible, the following specific embodiments are given as examples according to which the disclosure can indeed be implemented. In addition, wherever possible, elements/components/steps using the same reference numerals in the drawings and the embodiments represent the same or similar parts.

FIG.1is a schematic circuit diagram of an image sensor according to an embodiment of the disclosure. Referring toFIG.1, an image sensor100includes a first pixel circuit110, a second pixel circuit120, a ramp signal generating circuit130, a comparator140, and a signal processing circuit150. The first pixel circuit110and the second pixel circuit120are coupled to the ramp signal generating circuit130and the comparator140. The comparator140is also coupled to the signal processing circuit150. In the embodiment, the image sensor100may be a CMOS image sensor (CIS) and may be an active pixel sensor (APS). The image sensor100may include a pixel array, and the pixel array may include multiple pixel groups, wherein each pixel group may include, for example, the first pixel circuit110and the second pixel circuit120. The pixel array may be disposed in an active area (AA) of the image sensor100. The ramp signal generating circuit130, the comparator140, and the signal processing circuit150may be disposed in a peripheral area of the image sensor100.

In the embodiment, the first pixel circuit110includes a sensing unit PD0, a transfer transistor T1, a reset transistor T2, a readout transistor T3, a selection transistor T4, and a ramp capacitor C0. The sensing unit PD0may be a photodiode. A first terminal of the transfer transistor T1is coupled to a terminal of the sensing unit PD0. The other terminal of the sensing unit PD0is coupled to a reference voltage (for example, a ground voltage). A second terminal of the transfer transistor T1is coupled to a floating diffusion node FD0. The transfer transistor T1is coupled between the sensing unit PD0and the floating diffusion node FD0. A control terminal of the transfer transistor T1receives a first transfer signal tx0. A first terminal of the reset transistor T2is coupled to an operating voltage VDD. A second terminal of the reset transistor T2is coupled to the floating diffusion node FD0. A control terminal of the reset transistor T2receives a reset signal rst. A first terminal of the readout transistor T3is coupled to the operating voltage VDD. A second terminal of the readout transistor T3is coupled to a first terminal of the selection transistor T4. A control terminal of the readout transistor T3is coupled to the floating diffusion node FD0. A second terminal of the selection transistor T4is coupled to the comparator140. A control terminal of the selection transistor T4receives a selection signal sel. A terminal of the ramp capacitor C0is coupled to the ramp signal generating circuit130and receives a first ramp signal Vr_0. The other terminal of the ramp capacitor C0is coupled to the floating diffusion node FD0.

In the embodiment, the second pixel circuit120includes a sensing unit PD1, a transfer transistor T5, a reset transistor T6, a readout transistor T7, a selection transistor T8, and a ramp capacitor C1. The sensing unit PD1may be a photodiode. A first terminal of the transfer transistor T5is coupled to a terminal of the sensing unit PD1. The other terminal of the sensing unit PD1is coupled to a reference voltage (for example, a ground voltage). A second terminal of the transfer transistor T5is coupled to a floating diffusion node FD1. The transfer transistor T5is coupled between the sensing unit PD1and the floating diffusion node FD1. A control terminal of the transfer transistor T5receives a second transfer signal tx1. A first terminal of the reset transistor T6is coupled to the operating voltage VDD. A second terminal of the reset transistor T6is coupled to the floating diffusion node FD1. A control terminal of the reset transistor T6receives the reset signal rst. A first terminal of the readout transistor T7is coupled to the operating voltage VDD. A second terminal of the readout transistor T7is coupled to a first terminal of the selection transistor T8. A control terminal of the readout transistor T7is coupled to the floating diffusion node FD1. A second terminal of the selection transistor T8is coupled to the comparator140. A control terminal of the selection transistor T8receives the selection signal sel. A terminal of the ramp capacitor C1is coupled to the ramp signal generating circuit130and receives a second ramp signal Vr_1. The other terminal of the ramp capacitor C1is coupled to the floating diffusion node FD1.

In the embodiment, the transfer transistor T1, the reset transistor T2, the readout transistor T3, the selection transistor T4, the transfer transistor T5, the reset transistor T6, the readout transistor T7, and the selection transistor T8may respectively be N-type transistors, but the disclosure is not limited thereto. In the embodiment, the comparator140may be a differential amplifier. In the embodiment, the first pixel circuit110, the second pixel circuit120, the ramp signal generating circuit130, the comparator140, and the signal processing circuit150may form a differential digital correlated double sampling circuit.

FIG.2is a flowchart of an image sensing method according to an embodiment of the disclosure. Referring toFIG.1andFIG.2, the image sensor100may execute, for example, Steps S210to S260below.

In Step S210, the ramp signal generating circuit130respectively provides the first ramp signal Vr_0and the second ramp signal Vr_1to the first floating diffusion node FD0of the first pixel circuit110and the second floating diffusion node FD1of the second pixel circuit120through the first ramp capacitor C0and the second ramp capacitor C1during a normal readout period. In the embodiment, the first ramp signal Vr_0and the second ramp signal Vr_1are a pair of up and down ramp signals. In an embodiment, the first ramp signal Vr_0and the second ramp signal Vr_1may be alternately switched to an up ramp signal and a down ramp signal. For example, during the normal readout period, the first ramp signal Vr_0may be the up ramp signal and the second ramp signal Vr_1may be the down ramp signal. During an operation period of a next normal readout period, the first ramp signal Vr_0may be the down ramp signal and the second ramp signal Vr_1may be the up ramp signal.

In Step S220, the comparator140may receive a first node voltage of the first floating diffusion node FD0and a second node voltage of the second floating diffusion node FD1. In the embodiment, the readout transistor T3of the first pixel circuit110may be operated as a source follower to read out the first node voltage of the first floating diffusion node FD0to a first input terminal of the comparator140in cooperation with the turned-on selection transistor T4. The readout transistor T7of the second pixel circuit120may be operated as a source follower to read out the second node voltage of the second floating diffusion node FD1to a second input terminal of the comparator140in cooperation with the turned-on selection transistor T5. In Step S230, the signal processing circuit150may obtain a digital value corresponding to a sensing signal through the comparator130.

In Step S240, the ramp signal generating circuit130may respectively provide the first ramp signal Vr_0and the second ramp signal Vr_1to the first floating diffusion node FD0of the first pixel circuit110and the second floating diffusion node FD1of the second pixel circuit120through the first ramp capacitor C0and the second ramp capacitor C1during a dark sun detection period. For example, during an operation period of the dark sun detection period, the first ramp signal Vr_0may be the up ramp signal and the second ramp signal Vr_1may be the down ramp signal. During an operation period of a next dark sun detection period, the first ramp signal Vr_0may be the down ramp signal and the second ramp signal Vr_1may be the up ramp signal.

In Step S250, the comparator140may receive another first node voltage of the first floating diffusion node FD0and another second node voltage of the second floating diffusion node FD1. In the embodiment, the readout transistor T3of the first pixel circuit110may be operated as a source follower to read out the another first node voltage of the first floating diffusion node FD0to the first input terminal of the comparator140in cooperation with the turned-on selection transistor T4. The readout transistor T7of the second pixel circuit120may be operated as a source follower to read out the another second node voltage of the second floating diffusion node FD1to the second input terminal of the comparator140in cooperation with the turned-on selection transistor T5.

In Step S260, the signal processing circuit150may determine whether to output an output signal and determine whether to overwrite the digital value corresponding to the sensing signal according to whether the comparator140is triggered. In the embodiment, the signal processing circuit150may overwrite the digital value corresponding to the sensing signal to the highest digital value corresponding to the maximum brightness. In other words, during the dark sun detection period, the image sensor100may apply the ramp signals to the first floating diffusion node FD0of the first pixel circuit110and the second floating diffusion node FD1of the second pixel circuit120, and judge whether the first floating diffusion node FD0and/or the second floating diffusion node FD1have a dark sun effect using the comparator130according to the first node voltage of the first floating diffusion node FD0and the second node voltage of the second floating diffusion node FD1, so as to automatically correct the digital value (pixel value) of the corresponding pixel in the sensing signal. It should be noted that the digital value of the pixel is originally determined by differential output results of the first pixel circuit110and the second pixel circuit120. The signal processing circuit150may directly modify the pixel value of the pixel having the dark sun effect due to irradiation by strong light (for example, the sun at noon or laser light) in a sensing image to the highest digital value of the maximum brightness, so as to effectively correct the sensing image.

FIG.3is a detailed schematic circuit diagram of the image sensor according to the embodiment ofFIG.1of the disclosure.FIG.4is a signal waveform diagram of multiple signals according to an embodiment of the disclosure. Referring toFIG.1andFIG.3, in the embodiment, the signal processing circuit150includes a judging logic151, a pulse generating logic152, a latch circuit153, and a counter154. In the embodiment, the ramp signal generating circuit130may receive a reference voltage Vcm and a timing signal CLK, and generate the first ramp signal Vr_0and the second ramp signal Vr_1to the first pixel circuit110and the second pixel circuit120according to the reference voltage Vcm and the timing signal CLK. In the embodiment, the first pixel circuit110and the second pixel circuit120are respectively coupled to the first input terminal and the second input terminal of the comparator140. An output terminal of the comparator140is coupled to the judging logic151. The judging logic151receives a readout enabling signal EN. The pulse generating logic152is coupled to the judging logic151and a control terminal (C) of the latch circuit153. The counter154receives the timing signal CLK and is coupled to a data input terminal (D) of the latch circuit153. The counter154may count according to the timing signal CLK, and output a count value to the latch circuit153. A data output terminal (Q) of the latch circuit153outputs a count value Sout. In the embodiment, the judging logic151determines whether to output a control signal to the pulse generating logic152according to whether an output signal is received, so that the pulse generating logic152outputs a pulse signal to the latch circuit153, and the latch circuit153outputs the count value Sout. The signal processing circuit150may judge whether the floating diffusion node FD0and the floating diffusion node FD1of the first pixel circuit110and the second pixel circuit120have the dark sun effect (that is, the judging logic151judges whether to generate the output signal according to whether the comparator140is triggered) through the judging logic151to overwrite the (original) digital value corresponding to the sensing signal according to the (new) count value Sout.

Referring toFIG.1,FIG.3, andFIG.4, during a period from time t0to time t8, the image sensor100operates in the normal readout period. During a period from time t0to time t1, the reset signal rst is switched to a high voltage level, and the first transfer signal tx0and the second transfer signal tx1are at low voltage levels to turn on the reset transistor T2and the reset transistor T6, and reset the first node voltage of the first floating diffusion node FD0and the second node voltage of the second floating diffusion node FD1through the operating voltage VDD. The first pixel circuit110and the second pixel circuit120respectively reset the voltages of the respective sensing units PD0and PD1, and then perform exposure. During a period from time t2to time t3, the reset signal rst, the first transfer signal tx0, and the second transfer signal tx1are at low voltage levels, and the ramp signal generating circuit130may respectively provide the first ramp signal Vr_0with an up ramp waveform and the second ramp signal Vr_1with a down ramp waveform to the first floating diffusion node FD0and the second floating diffusion node FD1through the ramp capacitor C0and the ramp capacitor C1, so that the comparator140may respectively read out a first background noise signal and a second background noise signal from the readout transistor T3and the readout transistor T7. The comparator140may differentially output a reference noise signal. The signal processing circuit150may obtain a digital value corresponding to the reference noise signal through the comparator140.

During a period from time t4to time t5, the first transfer signal tx0is at a high voltage level, and the reset signal rst and the second transfer signal tx1are at low voltage levels to turn on the transfer transistor T1, so that a sensing result of the first sensing unit PD0is transmitted to the first floating diffusion node FD0. During a period from time t6to time t7, the reset signal rst, the first transfer signal tx0, and the second transfer signal tx1are at low voltage levels, and the ramp signal generating circuit130may respectively provide the first ramp signal Vr_0with another up ramp waveform and the second ramp signal Vr_1with another down ramp waveform to the first floating diffusion node FD0and the second floating diffusion node FD1through the ramp capacitor C0and the ramp capacitor C1, so that the comparator140may respectively read out a first readout signal (including the first background noise and the sensing result of the first sensing unit PD0) and a second readout signal (including the second background noise) from the readout transistor T3and the readout transistor T7. The comparator140may differentially output a reference sensing signal. The signal processing circuit150may obtain a digital value corresponding to the reference sensing signal through the comparator140. In this way, the signal processing circuit150may subtract the digital value of the reference noise signal from the digital value of the reference sensing signal to obtain the digital value of the sensing signal without background noise.

During a period from time t8to time t14, the image sensor100operates in the dark sun detection period. During the period from time t8to time t14, the image sensor100detects an exposure result of the first sensing unit PD0, and judges whether the first floating diffusion node FD0and the second floating diffusion node FD1have the dark sun effect. During a period from time t8to time t9, the reset signal rst is switched to a high voltage level, and the first transfer signal tx0and the second transfer signal tx1are at low voltage levels to turn on the reset transistor T2and the reset transistor T6, and reset the first node voltage of the first floating diffusion node FD0and the second node voltage of the second floating diffusion node FD1through the operating voltage VDD. The first pixel circuit110and the second pixel circuit120respectively reset the voltages of the respective sensing units PD0and PD1, and then perform exposure.

During a period from time t10to time t11, the first transfer signal tx0is at a high voltage level, and the reset signal rst and the second transfer signal tx1are at low voltage levels to turn on the transfer transistor T1, so that the sensing result of the first sensing unit PD0is transmitted to the first floating diffusion node FD0. During a period from time t12to time t13, the reset signal rst, the first transfer signal tx0, and the second transfer signal tx1are at low voltage levels, and the ramp signal generating circuit130may respectively provide the first ramp signal Vr_0with another up ramp waveform and the second ramp signal Vr_1with another down ramp waveform to the first floating diffusion node FD0and the second floating diffusion node FD1through the ramp capacitor C0and the ramp capacitor C1. The first pixel circuit110and the second pixel circuit120respectively read the respective node voltages from the first floating diffusion node FD0and the second floating diffusion node FD1to the comparator140. The comparator140may respectively receive the first node voltage of the first floating diffusion node FD0and the second node voltage of the second floating diffusion node FD1from the readout transistor T3and the readout transistor T7. In the embodiment, the signal processing circuit150may determine whether to output the output signal and determine whether to overwrite the digital value corresponding to the sensing signal according to whether the comparator140is triggered.

During a period from time t14to time t22, the image sensor100operates in the next normal readout period. During a period from time t14to time t15, the reset signal rst is switched to a high voltage level, and the first transfer signal tx0and the second transfer signal tx1are at low voltage levels to turn on the reset transistor T2and the reset transistor T6, and reset the first node voltage of the first floating diffusion node FD0and the second node voltage of the second floating diffusion node FD1through the operating voltage VDD. The first pixel circuit110and the second pixel circuit120respectively reset the voltages of the respective sensing units PD0and PD1, and then perform exposure. During a period from time t15to time t18, the first sensing unit PD0and the second sensing unit PD1may be exposed. During a period from time t16to time t17, the reset signal rst, the first transfer signal tx0, and the second transfer signal tx1are at low voltage levels, and the ramp signal generating circuit130may respectively provide the first ramp signal Vr_0with a down ramp waveform and the second ramp signal Vr_1with an up ramp waveform to the first floating diffusion node FD0and the second floating diffusion node FD1through the ramp capacitor C0and the ramp capacitor C1, so that the comparator140may respectively read out the first background noise signal and the second background noise signal from the readout transistor T3and the readout transistor T7. The comparator140may differentially output the reference noise signal. The signal processing circuit150may obtain the digital value corresponding to the reference noise signal through the comparator140.

During a period from time t18to time t19, the second transfer signal tx1is at a high voltage level, and the reset signal rst and the first transfer signal tx0are at low voltage levels to turn on the transfer transistor T1, so that the sensing result of the first sensing unit PD0is transmitted to the first floating diffusion node FD0. During a period from time t20to time t21, the reset signal rst, the first transfer signal tx0, and the second transfer signal tx1are at low voltage levels, and the ramp signal generating circuit130may respectively provide the first ramp signal Vr_0with another down ramp waveform and the second ramp signal Vr_1with another up ramp waveform to the first floating diffusion node FD0and the second floating diffusion node FD1through the ramp capacitor C0and the ramp capacitor C1, so that the comparator140may respectively read out the first readout signal (including the first background noise and the sensing result of the first sensing unit PD0) and the second readout signal (including the second background noise) from the readout transistor T3and the readout transistor T7. The comparator140may differentially output the reference sensing signal. The signal processing circuit150may obtain the digital value corresponding to the reference sensing signal through the comparator140. In this way, the signal processing circuit150may subtract the digital value of the reference noise signal from the digital value of the reference sensing signal to obtain the digital value of the sensing signal without background noise.

A period from time t22to time t28is a second detection period DP1during which the image sensor100operates in the next dark sun detection period. During the period from time t22to time t28, the image sensor100detects an exposure result of the second sensing unit PD1, and judges whether the first floating diffusion node FD0and the second floating diffusion node FD1have the dark sun effect. During a period from time t22to time t23, the reset signal rst is switched to a high voltage level, and the first transfer signal tx0and the second transfer signal tx1are at low voltage levels to turn on the reset transistor T2and the reset transistor T6, and reset the first node voltage of the first floating diffusion node FD0and the second node voltage of the second floating diffusion node FD1through the operating voltage VDD. The first pixel circuit110and the second pixel circuit120respectively reset the voltages of the respective sensing units PD0and PD1, and then perform exposure.

During a period from time t24to time t25, the second transfer signal tx1is at a high voltage level, and the reset signal rst and the first transfer signal tx0are at low voltage levels to turn on the transfer transistor T5, so that a sensing result of the second sensing unit PD1is transmitted to the second floating diffusion node FD1. During a period from time t26to time t27, the reset signal rst, the first transfer signal tx0, and the second transfer signal tx1are at low voltage levels, and the ramp signal generating circuit130may respectively provide the first ramp signal Vr_0with another up ramp waveform and the second ramp signal Vr_1with another down ramp waveform to the first floating diffusion node FD0and the second floating diffusion node FD1through the ramp capacitor C0and the ramp capacitor C1. The first pixel circuit110and the second pixel circuit120respectively read out the respective node voltages from the first floating diffusion node FD0and the second floating diffusion node FD1to the comparator140. The comparator140may respectively receive the first node voltage of the first floating diffusion node FD0and the second node voltage of the second floating diffusion node FD1from the readout transistor T3and the readout transistor T7. In the embodiment, the signal processing circuit150may determine whether to output the output signal and determine whether to overwrite the digital value corresponding to the sensing signal according to whether the comparator140is triggered.

It should be noted that in the embodiment, the first pixel circuit110and the second pixel circuit120perform a very short exposure operation during the dark sun detection period. In other words, the time length of the exposure performed by the first pixel circuit110and the second pixel circuit120during the dark sun detection period is shorter than the time length of the exposure performed by the first pixel circuit110and the second pixel circuit120during the normal readout period.

With reference toFIG.5toFIG.8, how the signal processing circuit150determines whether to overwrite the digital value corresponding to the sensing signal according to an output result of the comparator140will be described with several exemplary embodiments.

For example, please refer toFIG.5.FIG.5is a variation graph of voltage difference between a first node voltage and a second node voltage during a dark sun detection period according to an embodiment of the disclosure. A voltage difference Vfd_diff between the first node voltage of the first floating diffusion node FD0and the second node voltage of the second floating diffusion node FD1(a voltage value of the first node voltage minus a voltage value of the second node voltage) may be shown inFIG.5. During a period from time ta (that is, time t10or time t24) to time tb (that is, time t12or time t26), since the first floating diffusion node FD0receives the sensing result of the first sensing unit PD0or the second floating diffusion node FD1receives the sensing result of the second sensing unit PD1, the voltage difference Vfd_diff may be pulled down. Then, during a period from time tb to time tc, the first node voltage of the first floating diffusion node PD0may be first changed to a first offset voltage level according to the first ramp signal Vr_0, and the second node voltage of the second floating diffusion node PD1may be first changed to a second offset voltage level according to the second ramp signal Vr_1. In this way, the voltage difference Vfd_diff may be pulled up (an offset voltage level RS caused by the pair of up and down ramp signals is increased) and exceed a comparator trigger voltage Vt (because the first floating diffusion node FD0and the second floating diffusion node FD1do not have the dark sun effect). Next, during a period from time tc to time td, the judging logic151receives the readout enabling signal EN switched to a high voltage level for judgment. In addition, since the first floating diffusion node FD0receives the first ramp signal Vr_0with an up ramp waveform or a down ramp waveform and the second floating diffusion node FD1receives the second ramp signal Vr_1with a down ramp waveform or an up ramp waveform, the voltage difference Vfd_diff may be gradually pulled up. In this regard, during a period from time tc to time te (that is, time t13or time t27), since the first floating diffusion node FD0and the second floating diffusion node FD1do not have the dark sun effect, the voltage difference Vfd_diff does not reach (not attain) the comparator trigger voltage Vt during the process of being gradually pulled up, so the comparator140is not triggered to output the output signal (the comparator140does not change an output voltage level). In this way, the judging logic151does not generate the control signal to the pulse generating logic152, and the pulse generating logic152also does not generate the pulse signal to the latch circuit153. As shown inFIG.5, a logic signal LP output by the pulse generating logic152is maintained at a low voltage level.

For example, please refer toFIG.6.FIG.6is a variation graph of voltage difference between a first node voltage and a second node voltage according to another embodiment of the disclosure. The voltage difference Vfd_diff between the first node voltage of the first floating diffusion node FD0and the second node voltage of the second floating diffusion node FD1(the voltage value of the first node voltage minus the voltage value of the second node voltage) may be shown inFIG.6. During the period from time ta (that is, time t10or time t24) to time tb (that is, time t12or time t26), since the first floating diffusion node FD0receives the sensing result of the first sensing unit PD0or the second floating diffusion node FD1receives the sensing result of the second sensing unit PD1, and the first floating diffusion node FD0and/or the second floating diffusion node FD1have the dark sun effect, the voltage difference Vfd_diff may be pulled down more. Then, during the period from time tb to time tc, the first node voltage of the first floating diffusion node PD0may be first changed to the first offset voltage level according to the first ramp signal Vr_0, and the second node voltage of the second floating diffusion node PD1may be first changed the second offset voltage level according to the second ramp signal Vr_1. In this way, the voltage difference Vfd_diff may be pulled up (the offset voltage level RS caused by the pair of up and down ramp signals is increased) and does not exceed the comparator trigger voltage Vt (because the first floating diffusion node FD0and/or the second floating diffusion node FD1have the dark sun effect). Next, during the period from time tc to time td, the judging logic151receives the readout enabling signal EN switched to a high voltage level for judgment. In addition, since the first floating diffusion node FD0receives the first ramp signal Vr_0with an up ramp waveform or a down ramp waveform and the second floating diffusion node FD1receives the second ramp signal Vr_1with a down ramp waveform or an up ramp waveform, the voltage difference Vfd_diff may be gradually pulled up. In this regard, during the period from time tc to time te (that is, time t13or time t27), since the first floating diffusion node FD0and/or the second floating diffusion node FD1have the dark sun effect, the voltage difference Vfd_diff reaches (attains) the comparator trigger voltage Vt during the process of being gradually pulled up, so the comparator140is triggered to output the output signal (the comparator140changes the output voltage level). In this way, the judging logic151may generate the control signal to the pulse generating logic152, and the pulse generating logic152may generate the pulse signal to the latch circuit153. As shown inFIG.6, the logic signal LP output by the pulse generating logic152correspondingly generates a pulse waveform (that is, as the pulse signal). Therefore, the latch circuit153may output the current count value Sout provided by the counter154according to the pulse signal to be used to overwrite the digital value corresponding to the sensing signal.

For example, please refer toFIG.7.FIG.7is a variation graph of voltage difference between a first node voltage and a second node voltage according to another embodiment of the disclosure. The voltage difference Vfd_diff between the first node voltage of the first floating diffusion node FD0and the second node voltage of the second floating diffusion node FD1(the voltage value of the first node voltage minus the voltage value of the second node voltage) may be shown inFIG.7. During a period from time tf (that is, time t10or time t24) to time tg (that is, time t12or time t26), since the first floating diffusion node FD0receives the sensing result of the first sensing unit PD0or the second floating diffusion node FD1receives the sensing result of the second sensing unit PD1, the voltage difference Vfd_diff may be pulled down. Next, during a period from time tg to time th, since the first floating diffusion node FD0receives the first ramp signal Vr_0with an up ramp waveform or a down ramp waveform and the second floating diffusion node FD1receives the second ramp signal Vr_1with a down ramp waveform or an up ramp waveform, the voltage difference Vfd_diff may be gradually pulled up. During a period from time th to time ti (that is, time t13or time t27), the judging logic151receives the readout enabling signal EN switched to a high voltage level for judgment. In this regard, since the first floating diffusion node FD0and the second floating diffusion node FD1do not have the dark sun effect, the voltage difference Vfd_diff exceeds the comparator trigger voltage Vt during the process of being gradually pulled up, so the comparator140is triggered to output the output signal (the comparator140changes the output voltage level). In this way, the judging logic151does not generate the control signal to the pulse generating logic152, and the pulse generating logic152also does not generate the pulse signal to the latch circuit153. As shown inFIG.7, the logic signal LP output by the pulse generating logic152is maintained at a low voltage level.

For example, please refer toFIG.8.FIG.8is a variation graph of voltage difference between a first node voltage and a second node voltage according to another embodiment of the disclosure. The voltage difference Vfd_diff between the first node voltage of the first floating diffusion node FD0and the second node voltage of the second floating diffusion node FD1(the voltage value of the first node voltage minus the voltage value of the second node voltage) may be shown inFIG.8. During the period from time tf (that is, time t10or time t24) to time tg (that is, time t12or time t26), since the first floating diffusion node FD0receives the sensing result of the first sensing unit PD0or the second floating diffusion node FD1receives the sensing result of the second sensing unit PD1, and the first floating diffusion node FD0and/or the second floating diffusion node FD1have the dark sun effect, the voltage difference Vfd_diff may be pulled down more. Next, during the period from time tg to time th, since the first floating diffusion node FD0receives the first ramp signal Vr_0with an up ramp waveform or a down ramp waveform and the second floating diffusion node FD1receives the second ramp signal Vr_1with a down ramp waveform or an up ramp waveform, the voltage difference Vfd_diff may be gradually pulled up. During the period from time th to time ti (that is, time t13or time t27), the judging logic151receives the readout enabling signal EN switched to a high voltage level for judgment. In this regard, since the first floating diffusion node FD0and/or the second floating diffusion node FD1have the dark sun effect, the voltage difference Vfd_diff does not exceed the comparator trigger voltage Vt during the process of being gradually pulled up, so the comparator140is not triggered to output the output signal (the comparator140changes the output voltage level). In this way, the judging logic151generates the control signal to the pulse generating logic152, and the pulse generating logic152generates the pulse signal to the latch circuit153. As shown inFIG.8, the logic signal LP output by the pulse generating logic152correspondingly generates the pulse waveform (that is, as the pulse signal). Therefore, the latch circuit153may output the current count value Sout provided by the counter154according to the pulse signal to be used to overwrite the digital value corresponding to the sensing signal.

In summary, the image sensor and the image sensing method of the disclosure may detect whether the first floating diffusion node and the second floating diffusion node of the first pixel circuit and the second pixel circuit have the dark sun effect through applying the ramp signals to the first floating diffusion node and the second floating diffusion node of the first pixel circuit and the second pixel circuit for differential output, and may automatically correct the sensing signal, so that the sensing image generated by the image sensor can have the correct pixel values.

Although the disclosure has been disclosed in the above embodiments, the embodiments are not intended to limit the disclosure. Persons skilled in the art may make some changes and modifications without departing from the spirit and scope of the disclosure. Therefore, the protection scope of the disclosure shall be defined by the appended claims.