Patent ID: 12249586

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Integrated chips are typically fabricated by forming transistor devices within a semiconductor wafer and subsequently forming an interconnect structure over the semiconductor wafer. The interconnect structure includes a plurality of conductive interconnect layers that increase in size as a distance from the semiconductor wafer increases. The interconnect layers terminate at a bond pad formed over a top of the interconnect structure. After forming the bond pad, the semiconductor wafer may be singulated by a dicing process that cuts the wafer into a plurality of separate integrated chip die. The dicing process may be performed by mounting the wafer onto a sticky surface of a piece of dicing tape. A wafer saw then cuts the wafer along scribe lines to separate the wafer into the separate integrated chip die.

Because a wafer sawing process may cause mechanical stress on a wafer, a crack-stop may be arranged within the interconnect structure along an outer perimeter of each integrated chip die of the wafer. The crack-stop includes a dense arrangement of conductive interconnect layers configured to prevent cracks caused by a wafer dicing process from propagating into an interior of an integrated chip die. It has been appreciated that traditional dicing processes may be undesirable for integrated chip die having a relatively small size (e.g., less than 5 mm2), because a size of a crack stop will consume a proportionally large area of the integrated chip die.

Therefore, an alternative to traditional dicing processes can be to etch deep trenches between adjacent integrated chip die within a wafer. The deep trenches may extend through an interconnect structure and into a front side of the wafer. The trenches are filled with a dielectric material prior to thinning a back-side of the wafer to expose the dielectric material within the trenches. The dielectric material is then acted upon by a fluorine based gas to remove the dielectric material and separate the adjacent integrated chip die. In some processes, bond pads may be formed within an integrated chip die prior to forming the deep trenches. The bond pads may be formed by depositing a bond pad stack comprising an aluminum-copper layer disposed between an underlying titanium layer and an overlying titanium-nitride layer. The bond pad stack is subsequently patterned according to a silicon oxynitride hard mask to define the bond pads. The titanium-nitride layer protects the aluminum-copper layer during patterning of the bond pads and is subsequently etched to uncover the aluminum-copper layer prior to exposing the dielectric material to the fluorine based gas.

While the titanium-nitride layer protects the aluminum-copper layer during patterning, etchants used to remove the silicon oxynitride hard mask can pass through the titanium-nitride layer and damage the underlying aluminum-copper layer. The damage to the aluminum-copper layer can increase a resistance of the aluminum-copper layer and the bond pads. Furthermore, the fluorine based gas used to remove the dielectric material may interact with the exposed aluminum-copper layer and leave a byproduct (e.g., a AlxFy byproduct) on the aluminum-copper layer, which can further increase the resistance of the aluminum-copper layer (e.g., to a resistance that is greater than or equal to 100 ohm). The increased resistance of the aluminum-copper layer and the bond pad can increase a power consumption of an integrated chip, thereby reducing performance and/or battery life of a device using the integrated chip.

The present disclosure relates to a method of forming an integrated chip die having a low resistance bond pad (e.g., a bond pad having a resistance of less than approximately 20 ohms). In some embodiments, the method forms a bond pad stack onto an interconnect structure over a semiconductor body. The bond pad stack may include a titanium contact layer. The bond pad stack is selectively etched according to a first masking layer to define bond pad structures. An etching process is then performed to form trenches extending through the interconnect structure and into the semiconductor body. The trenches are filled with a dielectric material, and the titanium contact layer is exposed by etching the dielectric material and the first masking layer. A back-side of the semiconductor body is subsequently thinned, to expose the dielectric material within the trenches, before acting on the dielectric material with a fluorine based gas to remove the dielectric material and separate the semiconductor body into a plurality of integrated chip die. Because the first masking layer is left in place after defining the bond pad structures, damage to the titanium contact layer is reduced. Furthermore, the titanium contact layer is largely resistant to damage and/or formation of a byproduct due to the fluorine based gas, so that the titanium contact layer has a lower resistance than a damaged aluminum-copper layer.

FIG.1illustrates a cross-sectional view of some embodiments of an integrated chip die100having a bond pad structure comprising a contact layer that is resistant to fluorine based etchants.

The integrated chip die100comprises a transistor device104arranged within a substrate102. An interconnect structure106is arranged over the substrate102and surrounds the transistor device104. The interconnect structure106comprises a plurality of interconnect layers108disposed within a dielectric structure110. The plurality of interconnect layers108are electrically coupled to the transistor device104. In some embodiments, the transistor device104may comprise a MOSFET, a bi-polar junction transistor (BJT), a high electron mobility transistor (HEMT), or the like.

A bond pad structure112is arranged over the interconnect structure106. The bond pad structure112comprises one or more conductive layers114electrically coupled to the plurality of interconnect layers108. The bond pad structure112further comprises a contact layer116disposed over the one or more conductive layers114. The contact layer116is largely resistant fluorine based etchants, such that a fluorine based etchant (e.g., a vapor hydrofluoric acid) will not form a byproduct on the contact layer116. For example, in some embodiments, the contact layer116may comprise titanium, chromium, platinum, gold, or the like. In some embodiments, the contact layer116may comprise a metal alloy that is devoid of aluminum and/or copper.

A first masking layer118is disposed over the contact layer116and a second masking layer120is disposed over the first masking layer118. In some embodiments, the first masking layer118is completely confined over the contact layer116. The first masking layer118and the second masking layer120have sidewalls that define an opening122that extends through the first masking layer118and the second masking layer120to the contact layer116. In some embodiments, the second masking layer120continuously extends from directly over the contact layer116to along sidewalls of the bond pad structure112, sidewalls of the interconnect structure106, and sidewalls of the substrate102. In some embodiments, the second masking layer120may extend to a horizontal line disposed along a bottommost surface103of the substrate102. In some embodiments, the second masking layer120may have a bottommost120bsurface that is substantially co-planar with the bottommost surface103of the substrate102.

In some embodiments, the first masking layer118and the second masking layer120may comprise or be a same material. For example, the first masking layer118and the second masking layer120may comprise or be a metal-oxide, such as aluminum-oxide, magnesium-oxide, iron-oxide, or the like. In other embodiments, first masking layer118and the second masking layer120may comprise or be different materials. For example, the first masking layer118and the second masking layer120may comprise or be different metal-oxides.

A conductive bump124is disposed on the contact layer116. The conductive bump124vertically extends from the contact layer116to over the first masking layer118and the second masking layer120. The conductive bump124is configured to electrically couple the contact layer116to another substrate (e.g., an integrated chip die, a package substrate, and interposer substrate, or the like).

Keeping the first masking layer118over the contact layer116during fabrication of the integrated chip die100can prevent damage to the contact layer116. Moreover, during the fabrication process the upper surface of the contact layer116may be exposed to fluorine based etchants (e.g., vapor hydrofluoric acid). Because the contact layer116is a material that is largely resistant to fluorine based etchants the formation of byproducts on the contact layer116is prevented, resulting in a contact layer116that is not covered by fluorine based byproducts. By preventing the formation of byproducts on the contact layer116, a resistance of the contact layer116can be kept relatively low (e.g., less than or equal to approximately 12 ohms). Furthermore, omitting an aluminum-copper layer from the bond pad structure112may reduce a number of deposition processes used in its formation and thereby reduce a cost of forming the bond pad structure112.

FIG.2Aillustrates a cross-sectional view of some additional embodiments of an integrated chip die200having a bond pad structure comprising a contact layer that is resistant to fluorine based etchants.

The integrated chip die200comprises a transistor device104arranged within a substrate102. In some embodiments, the transistor device104comprises a source region104sand a drain region104ddisposed within the substrate102. A gate electrode104eis arranged over the substrate102at a position that is between the source region104sand the drain region104d. The gate electrode104eis separated from the substrate102by way of a gate dielectric layer104g.

An interconnect structure106is arranged over the substrate102and surrounds the gate electrode104eof the transistor device104. The interconnect structure106comprises a plurality of interconnect layers108disposed within a dielectric structure110. In some embodiments, the plurality of interconnect layers108may comprise conductive contacts108a, interconnect wires108b, and interconnect vias108c. In some embodiments, the plurality of interconnect layers108may comprise copper, tungsten, aluminum, or the like. In some embodiments, the dielectric structure110may comprise a plurality of stacked inter-level dielectric (ILD) layers vertically separated from one another by etch stop layers. In some embodiments, the plurality of stacked ILD layers may comprise one or more of silicon dioxide, doped silicon dioxide (e.g., carbon doped silicon dioxide), silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), or the like. In some embodiments, the interconnect structure106does not have a crack-stop region around a perimeter of the integrated chip die200.

A redistribution structure202is disposed over the interconnect structure106. The redistribution structure202comprises a passivation layer204surrounding a conductive redistribution layer206. In some embodiments, the passivation layer204may comprise a nitride (e.g., silicon oxynitride), a carbide (e.g., silicon oxycarbide), an oxide (e.g., PESiON), or the like. In some embodiments, the conductive redistribution layer206may comprise a conductive contact having sidewalls that vertically extend completely through the passivation layer204. In some embodiments, the conductive redistribution layer206may comprise tungsten. In other embodiments, the conductive redistribution layer206may additionally or alternatively comprise one or more other types of metal (e.g., aluminum, copper, etc.)

A bond pad structure112is disposed over the redistribution structure202. In some embodiments, the bond pad structure112may comprise a first conductive layer208, a diffusion barrier layer210disposed over the first conductive layer208, and a contact layer116disposed over the diffusion barrier layer210and comprising a material that is resistant to fluorine based etchants. In some embodiments, the first conductive layer208may comprise or be titanium. In some embodiments, the diffusion barrier layer210may comprise or be titanium nitride. In some embodiments, the contact layer116may comprise or be titanium. In some embodiments, the first conductive layer208may have a thickness in a range of between approximately 50 angstroms and approximately 150 angstroms. In some embodiments, the diffusion barrier layer210may have a thickness in a range of between approximately 100 angstroms and approximately 5000 angstroms. In some embodiments, the contact layer116may have a thickness in a range of between approximately 100 angstroms and approximately 5000 angstroms.

A first masking layer118is disposed over the bond pad structure112. The first masking layer118has interior sidewalls that are disposed directly over an upper surface of the bond pad structure112and outermost sidewalls that are substantially aligned with outermost sidewalls of the bond pad structure112. In some embodiments, the contact layer116may have a greater thickness directly below the first masking layer118than laterally outside of the first masking layer118(e.g., between the interior sidewalls of the first masking layer118). In some embodiments, the first masking layer118may have a thickness in a range of between approximately 150 angstroms and approximately 450 angstroms. In other embodiments, the first masking layer118may have a thickness of approximately 300 angstroms.

A second masking layer120is disposed over the first masking layer118. The second masking layer120has interior sidewalls that are disposed directly over the upper surface of the bond pad structure112. The second masking layer120extends along outermost sidewalls of the bond pad structure112and over a top of the redistribution structure202. In some embodiments, the second masking layer120may have a thickness in a range of between approximately 150 angstroms and approximately 450 angstroms. In other embodiments, the second masking layer120may have a thickness of approximately 300 angstroms.

FIG.2Billustrates a cross-sectional view of some additional embodiments of an integrated chip die212having a bond pad structure comprising a contact layer that is resistant to fluorine based etchants.

The integrated chip die212comprises a redistribution structure202disposed over the interconnect structure106that includes a plurality of interconnect layers108within a dielectric structure110over a substrate102. The redistribution structure202comprises a first passivation layer204ahaving sidewalls that define a first opening directly over one of the plurality of interconnect layers108. A conductive redistribution layer214is disposed over an upper surface of the first passivation layer204aand extends through the first opening to the plurality of interconnect layers108. In some embodiments, the conductive redistribution layer214may comprise a vertically extending segment extending through the first opening and a horizontally extending segment protruding outward from a sidewall of the vertically extending segment. A second passivation layer204bis disposed over the first passivation layer204aand the conductive redistribution layer214. The second passivation layer204bhas sidewalls that define a second opening directly over the conductive redistribution layer214.

A bond pad structure112is disposed over an upper surface of the second passivation layer204band extends through the second opening to the conductive redistribution layer214. The bond pad structure112comprises a first conductive layer208, a diffusion barrier layer210disposed over the first conductive layer208, and a contact layer116disposed over the diffusion barrier layer210. The first conductive layer208, the diffusion barrier layer210, and the contact layer116generally conform to the sidewalls and an upper surface of the second passivation layer204b. The contact layer116has interior sidewalls coupled to a horizontally extending surface to define a recess within an upper surface of the contact layer116. A conductive bump124fills the recess and extends from within the recess to over a second passivation layer204b.

FIG.3illustrates a cross-sectional view of some additional embodiments of an integrated chip die300having a bond pad structure comprising a contact layer that is resistant to fluorine based etchants.

The integrated chip die300comprises an interconnect structure106including a dielectric structure110arranged over a substrate102. A redistribution structure202comprising a passivation layer204is disposed over the interconnect structure106. In some embodiments, the passivation layer204, the dielectric structure110, and the substrate102may have sidewalls that are angled at an obtuse angle α with respect to a bottommost surface of the substrate102. For example, in some embodiments, the obtuse angle α may be in a range of between 90° and approximately 95°. In some embodiments (not shown), the sidewalls of the passivation layer204, the dielectric structure110, and the substrate102may have a scalloped profile comprising plurality of arced surfaces.

The redistribution structure202couples the interconnect structure106to a bond pad structure112. The bond pad structure112comprises a conductive bonding pad302, which is laterally surrounded by an additional passivation layer304. The additional passivation layer304continuously extends from along sidewalls of the conductive bonding pad302to over the conductive bonding pad302. The additional passivation layer304comprises sidewalls that are disposed over the conductive bonding pad302and that define an opening within the additional passivation layer304. A first conductive layer208is disposed over the additional passivation layer304and extends through the opening to the conductive bonding pad302. A diffusion barrier layer210is disposed over the first conductive layer208and a contact layer116is disposed over the diffusion barrier layer210.

FIG.4illustrates a cross-sectional view of some additional embodiments of an integrated chip die400having a bond pad structure comprising a contact layer that is resistant to fluorine based etchants.

The integrated chip die400comprises a plurality of transistor devices104a-104bdisposed within a substrate102. A plurality of bond pad structure112a-112bare arranged over a redistribution structure202overlying the substrate102. The plurality of bond pad structures112a-112bcomprise a first bond pad structure112aelectrically coupled to a first transistor104aand a second bond pad structure112belectrically coupled to a second transistor104b. The first bond pad structure112ahas outermost sidewalls that are laterally separated from outermost sidewalls of the second bond pad structure112bby a non-zero distance.

A first masking layer118is disposed over the first bond pad structure112aand the second bond pad structure112b. A second masking layer120is disposed on the first masking layer118. The second masking layer120extends along the outermost sidewalls of the first bond pad structure112aand the second bond pad structure112b.

FIGS.5-6Billustrates some embodiments of an integrated chip package comprising a disclosed integrated chip die. It will be appreciated thatFIGS.5-6Bare examples of some packages that may be used, but that the integrated chip die is not limited to such packages and rather may be implemented into a wide range of packages.

FIG.5illustrates a cross-sectional view of some embodiments of an integrated chip package500comprising a disclosed integrated chip die.

The integrated chip package500comprises a package substrate502having a first horizontal routing layer504coupled to a second horizontal routing layer508by way of a vertical routing layer506extending through a substrate507. The first horizontal routing layer504is coupled to a plurality of solder bumps510. The second horizontal routing layer508is coupled to one or more bump structures512, which are further coupled to an integrated chip die514disposed over the package substrate502. In various embodiments, the one or more bump structures512may comprise solder bumps, copper posts, micro-bumps (having widths in a range from about 5 μm to about 30 μm), or other applicable bump structures.

The integrated chip die514comprises an interconnect structure518disposed over a substrate516. In some embodiments, interconnect layers within the interconnect structure518are coupled to the one or more bump structures512by way of through substrate vias (TSVs)517extending through the substrate516. A redistribution structure520couples the interconnect structure518to a first bond pad522aand a second bond pad522b. The first bond pad522aand the second bond pad522bare respectively further coupled to a first micro-bump524aand a second micro-bump524b. The first micro-bump524acouples the integrated chip die514to a first integrated chip die526aand the second micro-bump524bcouples the integrated chip die514to a second integrated chip die526b. The first integrated chip die526aand the second integrated chip die526brespectively comprise a second masking layer120that is disposed along outer sidewalls of the first integrated chip die526aand the second integrated chip die526b.

A dielectric material528is disposed over the integrated chip die514and surrounds the first integrated chip die526aand the second integrated chip die526b. In some embodiments, the dielectric material528may contact the second masking layer120along opposing sides of the first integrated chip die526aand the second integrated chip die526b. In various embodiments, the dielectric material528may comprise an oxide, a polymer, a resin, or the like. A molding compound530is disposed over the package substrate502and surrounds the dielectric material528. In various embodiments, the molding compound530may comprise a polymer, a resin, or the like.

FIG.6Aillustrates a cross-sectional view of some additional embodiments of an integrated chip package600having a plurality of integrated chip die.

The integrated chip package600comprises a first integrated chip die526acoupled to a package substrate502by way of a first micro-bump602a. The first integrated chip die526acomprises a first bond pad structure112athat is coupled to a second micro-bump602b. The second micro-bump602bis further coupled to a second bond pad structure112bof a second integrated chip die526b. A molding compound530is disposed over the package substrate502and surrounds the first integrated chip die526aand the second integrated chip die526b.

FIG.6Billustrates a cross-sectional view of some additional embodiments of an integrated chip package604having a plurality of integrated chip die.

The integrated chip package604comprises a first integrated chip die526acoupled to a package substrate502by way of a first micro-bump602a. The first integrated chip die526acomprises a first bond pad structure112athat is coupled to a conductive bonding structure606. The conductive bonding structure606is further coupled to a second bond pad structure112bof a second integrated chip die526b. The first integrated chip die526aand the second integrated chip die526bare respectively surrounded by a second masking layer120. The second masking layer120surrounding the first integrated chip die526aand the second masking layer120surrounding the second integrated chip die526bcontact one another along a hybrid bonding interface608comprising the conductive bonding structure606and the second masking layer120.

FIGS.7-21Dillustrate cross-sectional views700-2100of some embodiments of a method of forming an integrated chip die having a bond pad structure comprising a contact layer that is resistant to fluorine based etchants. AlthoughFIGS.7-21are described in relation to a method, it will be appreciated that the structures disclosed inFIGS.7-21are not limited to such a method, but instead may stand alone as structures independent of the method.

As shown in cross-sectional view700ofFIG.7, a semiconductor body702is provided. In various embodiments, the semiconductor body702may be any type of substrate (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer, as well as any other type of semiconductor and/or epitaxial layers, associated therewith. The semiconductor body702comprises a plurality of integrated chip die regions704-706. A plurality of transistor devices104are formed along a first side702si(e.g., a front-side) of the semiconductor body702within each of the plurality of integrated chip die regions704-706.

As shown in cross-sectional view800ofFIG.8, an interconnect structure106is formed along the first side702siof the semiconductor body702. The interconnect structure106comprises a plurality of interconnect layers108formed within a dielectric structure110. In some embodiments, the dielectric structure110may comprise a plurality of stacked inter-level dielectric (ILD) layers formed over the semiconductor body702. In some embodiments (not shown), the plurality of stacked ILD layers are separated by etch stop layers. In some embodiments, the plurality of interconnect layers108may comprise a conductive contact108a, an interconnect wire108b, and an interconnect via108c. The plurality of interconnect layers108may be formed by forming one of the one or more ILD layers over the semiconductor body702(e.g., an oxide, a low-k dielectric, or an ultra low-k dielectric), selectively etching the ILD layer to define a via hole and/or a trench within the ILD layer, forming a conductive material (e.g., copper, aluminum, etc.) within the via hole and/or the trench, and performing a planarization process (e.g., a chemical mechanical planarization process).

As shown in cross-sectional view900ofFIG.9, a redistribution structure202is formed over the interconnect structure106. In some embodiments, the redistribution structure202may be formed by depositing a passivation layer204over the interconnect structure106. The passivation layer204is subsequently etched to expose one or more of the plurality of interconnect layers108within the interconnect structure106. A conductive material (e.g., tungsten) is deposited over the passivation layer204. A part of the conductive material is subsequently removed to define a conductive redistribution layer206within the redistribution structure202.

As shown in cross-sectional view1000ofFIG.10, a bond pad stack1002comprising a contact layer1008is formed over the redistribution structure202. In some embodiments, the bond pad stack1002may comprise a first conductive layer1004, a diffusion barrier layer1006disposed over the first conductive layer1004, and a contact layer1008disposed over the diffusion barrier layer1006. In some embodiments, the first conductive layer1004may comprise a metal, such as titanium, tantalum, or the like. In some embodiments, the diffusion barrier layer1006may comprise a metal-nitride, such as titanium nitride, tantalum nitride, or the like. The contact layer1008is a conductive material that is largely resistant fluorine based etchants. For example, in some embodiments, the contact layer1008may comprise or be titanium, chromium, platinum, gold, or the like. In some embodiments, the contact layer1008may comprise a metal alloy that is devoid of aluminum and/or copper. In some embodiments, the bond pad stack1002may be formed by a plurality of deposition processes (e.g., CVD, PVD, sputtering, PE-CVD, or the like).

As shown in cross-sectional view1100ofFIG.11, a first masking layer118is formed over the bond pad stack1002. In some embodiments, the first masking layer118may comprise a metal-oxide, such as aluminum oxide, magnesium oxide, or the like. The first masking layer118may be formed by depositing a first masking material over the bond pad stack1002, and performing a lithographic patterning process to pattern the first masking material and define the first masking layer118. In some embodiments, the first masking material may be formed to a thickness of between approximately 250 angstroms and approximately 350 angstroms. Such a thickness of the first masking material prevents damage to the underlying contact layer1008.

As shown in cross-sectional view1200ofFIG.12, the bond pad stack (1002ofFIG.11) is patterned to define a plurality of bond pad structures112a-112d. In some embodiments, the bond pad stack (1002ofFIG.11) may be patterned by selectively exposing the bond pad stack to an etchant1202according to the first masking layer118. In some embodiments, the etchant1202may comprise a dry etchant (e.g., having a chlorine based chemistry).

As shown in cross-sectional view1300ofFIG.13, the dielectric structure110and the semiconductor body702are patterned to define trenches1302a-1302cextending into the first side702s1of the semiconductor body702. The trenches1302a-1302ccomprise a first trench1302adisposed along a first side of the first integrated chip region704, a second trench1302bdisposed between a second side of the first integrated chip region704and a first side of the second integrated chip region706, and a third trench1302cdisposed along a second side of the second integrated chip region706.

In some embodiments, the dielectric structure110and the semiconductor body702may be patterned by selectively exposing the dielectric structure110and the semiconductor body702to an etchant1306according to a trench masking layer1304. The trench masking layer1304extends over the plurality of bond pad structures112a-112dand comprises sidewalls that define openings disposed between adjacent ones of the integrated chip die regions704-706. In some embodiments, the trench masking layer1304may comprise an oxide, a nitride, a carbide, or the like. In some embodiments, the etchant1306may comprise a dry etchant. In some embodiments, the etchant1306may be part of a deep reactive ion etching process (e.g., a Bosch etch process). The trench masking layer1304may be removed after patterning of the dielectric structure110and the semiconductor body702.

As shown in cross-sectional view1400ofFIG.14, a second masking layer120is formed over the first masking layer118, and along sidewalls of the plurality of bond pad structures112a-112d, the redistribution structure202, the dielectric structure110, and the semiconductor body702that define the trenches1302a-1302c. In some embodiments, the second masking layer120may comprise a metal-oxide, such as aluminum oxide, for example. In some embodiments, the second masking layer120may be formed by way of a deposition process (e.g., CVD, PE-CVD, PVD, or the like). In some embodiments, the second masking layer120may be formed to a thickness of between approximately 250 angstroms and approximately 350 angstroms. Such a thickness of the second masking layer120prevents damage to the underlying layers during a subsequent exposure to a fluorine based etchant.

A dielectric fill material1402is formed over the second masking layer120. The dielectric fill material1402fills the trenches1302a-1302cand extends over top surfaces of the plurality of bond pad structures112a-112d. In some embodiments, the dielectric fill material1402may comprise an oxide (e.g., silicon oxide), a nitride, or the like. In some embodiments, the dielectric fill material1402may be formed by way of a deposition process (e.g., CVD, PE-CVD, PVD, or the like).

As shown in cross-sectional view1500ofFIG.15, the dielectric fill material1402, the second masking layer120, and the first masking layer118are patterned to define openings1502that expose the contact layer116within respective ones of the plurality of bond pad structures112a-112d. In some embodiments the dielectric fill material1402, the second masking layer120, and the first masking layer118may be selectively patterned using a photolithographic process and a dry etching process.

As shown in cross-sectional view1600ofFIG.16an additional dielectric material1602is formed over the dielectric fill material1402. The additional dielectric material1602fills in the openings1502in the dielectric fill material1402. In some embodiments, the additional dielectric material1602may comprise an oxide formed by way of a deposition process (e.g., CVD, PE-CVD, PVD, or the like). In some embodiments, after the additional dielectric material1602is deposited, a planarization process (e.g., a chemical mechanical planarization (CMP) process) may be performed so that the dielectric fill material1402and/or the additional dielectric material1602define a substantially flat surface overlying the semiconductor body702.

As shown in cross-sectional view1700ofFIG.17, the dielectric fill material1402and the additional dielectric material1602are bonded to a carrier substrate1702. In some embodiments, the dielectric fill material1402and the additional dielectric material1602may be bonded to the carrier substrate1702by way of a fusion bonding process. In some embodiments, the fusion bonding process is performed by bringing the carrier substrate1702into contact with the dielectric fill material1402and/or the additional dielectric material1602at an elevated temperature (e.g., a temperature greater than approximately 500° C.).

As shown in cross-sectional view1800ofFIG.18, a part of the semiconductor body (702ofFIG.17) is removed to thin the semiconductor body. Thinning the semiconductor body exposes both the dielectric fill material1402and the second masking layer120within the trenches (1302a-1302cofFIG.14) and defines a plurality of integrated chip die1802-1804. The plurality of integrated chip die1802-1804comprise a first integrated chip die1802and a second integrated chip die1804. The first integrated chip die1802has a first dielectric structure106adisposed over a first substrate102a. The first dielectric structure106ais coupled to bond pad structures112a-112bby way of a first redistribution structure202a. The second integrated chip die1804has a second dielectric structure106bdisposed over a second substrate102b. The second dielectric structure106bis coupled to bond pad structures112c-112dby way of a second redistribution structure202b.

In some embodiments, the part of the semiconductor body (702ofFIG.17) may be removed by operating upon a back-side of the semiconductor body with an etching process, a mechanical grinding process, a chemical mechanical polishing process, or the like. Removing the part of the semiconductor body causes the dielectric fill material1402to continuously extend between a first horizontal line1806extending along a top of the bond pad structures112a-112dand a second horizontal line1808extending along a bottommost surface of the plurality of integrated chip die1802-1804.

As shown in cross-sectional view1900ofFIG.19A, the dielectric fill material1402and the additional dielectric material1602are removed to separate the plurality of integrated chip die1802-1804from one another and from the carrier substrate1702. In some embodiments, the dielectric fill material1402and the additional dielectric material1602may be removed using an etchant1902comprising a vapor hydrofluoric acid (VHF). The second masking layer120prevents the VHF from damaging the plurality of integrated chip die1802-1804. Furthermore, the contact layer116has a low reactivity with fluorine based etchants, thereby preventing the VHF from forming a fluorine based byproduct on the contact layer116(so that the contact layer116has an upper surface that does not have a fluorine based byproduct) and maintaining a low resistance (e.g., less than approximately 12 ohms).

Cross-sectional view1904ofFIG.19Billustrates a cross-sectional view of an integrated chip die1802after removal of the dielectric fill material1402and the additional dielectric material1602.

FIGS.20A-21Dillustrate cross-sectional views of some embodiments of packaging processes used to package one or more of the plurality of integrated chip die1802-1804. It will be appreciated that the packaging processes ofFIGS.20A-21Dare non-limiting examples of packaging processes that may be used to package one or more of the plurality of integrated chip die1802-1804.

FIGS.20A-20Billustrate cross-sectional views of some embodiments of a packaging process used to package one or more of the plurality of integrated chip die1802-1804.

As shown in cross-sectional view2000ofFIG.20A, an integrated chip die1802is bonded to a package substrate502by way of one or more bump structures512. The one or more bump structures512are formed over the package substrate502to enable the package substrate502to be coupled to the integrated chip die1802. In various embodiments, the one or more bump structures512may comprise solder bumps, copper posts, micro-bumps (having widths in a range from about 5 μm to about 30 μm), or other applicable bump structures.

As shown in cross-sectional view2002ofFIG.20B, a molding compound530is formed over the package substrate502and around the integrated chip die1802. In some embodiments, the molding compound530may comprise an epoxy, an epoxy with thermally conductive filler materials, organic cylinders, plastic molding compound, plastic molding compound with fiber, or other suitable material. In some embodiments, the molding compound530is formed by a spin-on coating process, an injection molding process, and/or the like.

FIGS.21A-21Dillustrate cross-sectional views of some alternative embodiments of a packaging process used to package one or more of the plurality of integrated chip die1802-1804.

As shown in cross-sectional view2100ofFIG.21A, the plurality of integrated chip die1802-1804are bonded to a wafer2102by way of a plurality of bump structures524. In various embodiments, the plurality of bump structures524may comprise solder bumps, copper posts, micro-bumps, or other applicable bump structures. The wafer2102comprises an interconnect structure2106disposed over a substrate2104. A redistribution structure2108couples the interconnect structure2106to a plurality of bond pads522.

As shown in cross-sectional view2110ofFIG.21B, a dielectric material528is formed over the wafer2102and around the plurality of integrated chip die1802-1804. In some embodiments, the dielectric material528may comprise an oxide. In other embodiments, the dielectric material528may comprise an epoxy, a polymer, or other suitable material.

As shown in cross-sectional view2112ofFIG.21C, the wafer (2102ofFIG.21B) is singulated to form a plurality of integrated chip die514a-514b. In some embodiments, the wafer (2102ofFIG.21B) may be singulated by a dicing process that mounts the wafer onto a sticky surface of a piece of dicing tape2114. A wafer saw then cuts the wafer along scribe lines2116to separate the wafer into separate integrated chip die514a-514b. In some embodiments (not shown), the wafer (2102ofFIG.21B) may have a crack-stop disposed within the interconnect structure2106on opposing sides of the scribe lines2116. The crack-stop is a dense arrangement of interconnect layers that prevent the propagation of cracks caused by the dicing process.

As shown in cross-sectional view2118ofFIG.21D, one of the plurality of integrated chip die514ais bonded to a package substrate502by way of one or more bump structures512. The one or more bump structures512are formed over the package substrate502to enable the package substrate502to be coupled to the integrated chip die1802. In various embodiments, the one or more bump structures512may comprise solder bumps, copper posts, micro-bumps (having widths in a range from about 5 μm to about 30 μm), or other applicable bump structures.

A molding compound530is formed over the package substrate502and around the integrated chip die1802. In some embodiments, the molding compound530may comprise an epoxy, an epoxy with thermally conductive filler materials, organic cylinders, plastic molding compound, plastic molding compound with fiber, or other suitable material. In some embodiments, the molding compound530is formed by a spin-on coating process, an injection molding process, and/or the like.

FIG.22illustrates a flow diagram of some embodiments of a method2200of forming an integrated chip die having a bond pad structure comprising a contact layer that is resistant to fluorine based etchants.

While method2200is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

At2202, transistor devices are formed within integrated chip die regions of a semiconductor body.FIG.7illustrates a cross-sectional view700of some embodiments corresponding to act2202.

At2204, an interconnect structure is formed along a front-side of the semiconductor body.FIG.8illustrates a cross-sectional view800of some embodiments corresponding to act2204.

At2206, a bond pad stack comprising a contact layer is formed over the interconnect structure. In some embodiments, the contact layer may comprise or be titanium.FIG.10illustrates a cross-sectional view1000of some embodiments corresponding to act2206.

At2208, the bond pad stack is patterned according to a first masking layer to define a plurality of bond pad structures.FIGS.11-12illustrate cross-sectional views1100-1200of some embodiments corresponding to act2208.

At2210, the interconnect structure and the semiconductor body are patterned to define trenches extending into the semiconductor body between adjacent integrated chip die regions.FIG.13illustrates a cross-sectional view1300of some embodiments corresponding to act2210.

At2212, a second masking layer is formed within the trenches and over the first masking layer.FIG.14illustrates a cross-sectional view1400of some embodiments corresponding to act2212.

At2214, a dielectric fill material is formed over the second masking layer.FIG.14illustrates a cross-sectional view1400of some embodiments corresponding to act2214.

At2216, the first masking layer, the second masking layer, and the dielectric fill material are patterned to define openings that expose the contact layer within the bond pad structures.FIG.15illustrates a cross-sectional view1500of some embodiments corresponding to act2216.

At2218, an additional dielectric material is formed within the openings and over the dielectric fill material.FIG.16illustrates a cross-sectional view1600of some embodiments corresponding to act2218.

At2220, the additional dielectric material and/or the dielectric fill material is bonded to a carrier substrate.FIG.17illustrates a cross-sectional view1700of some embodiments corresponding to act2220.

At2222, a part of the semiconductor body is removed to expose the dielectric fill material along a back-side of the semiconductor body and to define a plurality of integrated chip die.FIG.18illustrates a cross-sectional view1800of some embodiments corresponding to act2222.

At2224, the dielectric fill material and the additional dielectric fill material are removed to separate the plurality of integrated chip die.FIG.19illustrates a cross-sectional view1900of some embodiments corresponding to act2224.

Accordingly, in some embodiments, the present disclosure relates to a method of forming an integrated chip die having a low resistance bond pad structure (e.g., a bond pad structure having a resistance of less than approximately 20 ohms). The method forms the bond pad structure as part of a process that uses deep trenches to singulate a semiconductor body into separate integrated chip die.

In some embodiments, a method of forming an integrated chip, comprising: forming a plurality of bond pad structures over an interconnect structure on a front-side of a semiconductor body, wherein the plurality of bond pad structures respectively comprise a titanium contact layer; patterning the interconnect structure and the semiconductor body to define trenches extending into the semiconductor body; forming a dielectric fill material within the trenches; etching the dielectric fill material to expose the titanium contact layer prior to bonding the semiconductor body to a carrier substrate; thinning the semiconductor body to expose the dielectric fill material along a back-side of the semiconductor body and to form a plurality of integrated chip die; and removing the dielectric fill material to separate the plurality of integrated chip die.

In other embodiments, a method of forming an integrated chip, comprising: forming a bond pad stack over an interconnect structure on a semiconductor body, the bond pad stack comprising a contact layer; patterning the bond pad stack according to a first masking layer to define a plurality of bond pad structures, wherein the first masking layer comprises a metal-oxide; patterning the interconnect structure and the semiconductor body to have sidewalls that define trenches extending into the semiconductor body; forming a dielectric fill material within the trenches; etching the dielectric fill material and the first masking layer to expose the contact layer; removing a part of the semiconductor body so that the dielectric fill material completely extends through the semiconductor body, wherein removing the part of the semiconductor body defines a plurality of integrated chip die; and exposing the dielectric fill material to an etchant to remove the dielectric fill material and separate the plurality of separate integrated chip die.

In yet other embodiments, an integrated chip, comprising: an interconnect structure disposed over a substrate, wherein the interconnect structure comprises a plurality of interconnect layers disposed within a dielectric structure; a bond pad structure disposed over the interconnect structure, wherein the bond pad structure comprises a contact layer; a first masking layer comprising a metal-oxide disposed over the bond pad structure, the first masking layer having interior sidewalls arranged directly over the bond pad structure to define an opening; and a conductive bump arranged within the opening and on the contact layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.