Patent ID: 12261215

For simplicity and clarity of illustration, the drawings illustrate the general manner of construction, and certain descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the discussion of the described embodiments of the devices. Additionally, elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some of the elements in the drawings may be exaggerated relative to other elements to help improve understanding of embodiments of the devices. The same reference numerals in different drawings denote the same elements, while similar reference numerals may, but do not necessarily, denote similar elements.

DETAILED DESCRIPTION

The following detailed description is exemplary in nature and is not intended to limit the devices or the application and uses of the devices. Furthermore, there is no intention to be bound by any theory presented in the preceding background of the devices or the following detailed description.

FIG.1Aillustrates a top view of a structure100, according to an embodiment of the disclosure. In one embodiment, the structure100may be a fin-type transistor, for example, a fin-type field effect transistor. In one embodiment, the structure100may be a planar and a fin-type field effect transistor. Referring toFIG.1A, fins116a,116band116cmay be arranged over an active layer102c. The fins116a,116band116cmay be spaced from each other. The active layer102cmay be surrounded by an isolation structure106. The isolation structure106may be a shallow trench isolation. A polysilicon layer122may be arranged over and traversing across the fins116a,116band116cand the active layer102c. The polysilicon layer122may have a first side surface148aand a second side surface148bopposite to the first side surface148a. A spacer126may be arranged along a periphery of the polysilicon layer122, for example, the spacer126may be arranged next to the first148aand second148bside surfaces. In one embodiment, the polysilicon layer122may be a gate polysilicon layer. An epitaxial structure142amay be arranged on the active layer102cand laterally spaced from the first side surface148aof the polysilicon layer122. An epitaxial structure142bmay be arranged on the active layer102cand laterally spaced from the second side surface148b. A fin epitaxial structure128amay be arranged over a portion of the fin116aand laterally spaced from the first side surface148aof the polysilicon layer122. A fin epitaxial structure128bmay be arranged over another portion of the fin116aand laterally spaced from the second side surface148bof the polysilicon layer122. Fin epitaxial structures128cand128dmay be arranged over fin116band laterally spaced from the first148aand second148bside surfaces, respectively. Fin epitaxial structures128eand128fmay be arranged over fin116cand laterally spaced from the first148aand second148bside surfaces, respectively.

The fin116amay have a first side surface146aand a second side surface146bopposite to the first side surface146a. The epitaxial structures142aand142bmay be arranged laterally spaced from the first side surface146aof the fin116a. An epitaxial structure142cmay be arranged on the active layer102cand laterally spaced from the second side surface146bof the fin116aand the first side surface148aof the polysilicon layer122. An epitaxial structure142dmay be arranged laterally spaced from the second side surface146bof the fin116aand the second side surface148bof the polysilicon layer122. The epitaxial structures142cand142dmay be arranged between the fins116aand116b. Epitaxial structures142eand142fmay be arranged between the fins116band116cand laterally spaced from a first side surface of the fin116c. Epitaxial structures142gand142hmay be laterally spaced from a second side surface of the fin116c. The second side surface of the fin116cmay be arranged opposite to the first side surface. For simplicity, silicide layers above the epitaxial structures142atoh, fin epitaxial structures128atofand the polysilicon layer122are not shown in this top down view. A contact electrode138amay be arranged over the epitaxial structures142a,142c,142e, and142g, and the fin epitaxial structures128a,128c, and128e. A contact electrode138bmay be arranged over the epitaxial structures142b,142d,142f, and142hand the fin epitaxial structures128b,128d, and128f. The contact electrodes138aand138bmay be continuous structures and are illustrated as dashed outlines.

FIG.1Billustrates a corresponding cross-sectional view of the structure100taken along section line X1-X1′ ofFIG.1A, according to an embodiment of the disclosure. Referring toFIG.1B, the structure100may include a semiconductor layer102aand a buried oxide layer102barranged over the semiconductor layer102a. The active layer102cmay be arranged over the buried oxide layer102b. The semiconductor layer102a, buried oxide layer102band active layer102cmay be a silicon on insulator substrate. The isolation structure106may be arranged laterally adjacent to the active layer102c, buried oxide layer102band over the semiconductor layer102a. The active layer102cmay have a top surface150. An insulating layer108may be arranged over a portion150aof the top surface150of the active layer102c. In one embodiment, the insulating layer108may be directly contacting the portion150a. A conductive layer110may be arranged over a top surface of the insulating layer108. In one embodiment, the conductive layer110may be directly contacting the top surface of the insulating layer108. A barrier layer112may be arranged over a top surface of the conductive layer110. In one embodiment, the barrier layer112may be directly contacting the top surface of the conductive layer110. The insulating layer108, conductive layer110and barrier layer112may be referred to as a barrier stack. The fin116cmay be arranged over a top surface of the barrier layer112. In one embodiment, a bottom surface of the fin116cmay be directly contacting the top surface of the barrier layer112. The fin116cmay be spaced from the portion150aby the barrier stack. The fin116cmay have a top surface152. A dielectric layer118may be arranged on a portion of the top surface152and a metal layer120may be arranged over a top surface of the dielectric layer118. In one embodiment, the metal layer120may be directly contacting the top surface of the dielectric layer118. In one embodiment, the metal layer120may be a gate metal layer. The polysilicon layer122may be arranged over a top surface of the metal layer120. In one embodiment, the polysilicon layer122may be directly contacting the top surface of the metal layer120. The fin epitaxial structure128emay be arranged on another portion different from the previous portion of the top surface152of the fin116cand laterally spaced from the first side surface148aof the polysilicon layer122. The fin epitaxial structure128fmay be arranged on yet another portion different from the previous portions of the top surface152and laterally spaced from the second side surface148bof the polysilicon layer122. The spacer structures126may be arranged on the first148aand second148bside surfaces, and side surfaces of the metal layer120and the dielectric layer118. The spacer structures126may separate the polysilicon layer122, the metal layer120and the dielectric layer118from the fin epitaxial structures128eand128f. Fin spacer structures158may be arranged on side surfaces of the fin116c, barrier layer112, conductive layer110and insulating layer108. Silicide layers132a,132band132cmay be arranged over the polysilicon layer122and fin epitaxial structures128eand128f, respectively. Contact electrodes138aand138bmay be arranged over the silicide layers132band132c, respectively. An interlayer dielectric (ILD)136layer may be arranged over the isolation structure106, the fin116c, silicide layers132atocand contact electrodes138aand138b.

FIG.1Cillustrates a corresponding cross-sectional view of the structure100taken along section line X2-X2′ ofFIG.1A, according to an embodiment of the disclosure. Referring toFIG.1C, a portion of the dielectric layer118may be arranged on a portion150bof the top surface150of the active layer102c. The metal layer120, may be arranged over the dielectric layer118and the polysilicon layer122may be arranged over the metal layer120. The epitaxial structure142amay be arranged on a portion150cof the top surface150of the active layer102cand laterally spaced from the first148aside surface of the polysilicon layer122. The epitaxial structure142bmay be arranged on a portion150dof the top surface150of the active layer102cand laterally spaced from the second side surface148bof the polysilicon layer122. Silicide layers132dand132emay be arranged on the epitaxial structures142aand142b, respectively. The contact electrodes138aand138bmay be arranged on the silicide layers132dand132e, respectively.

FIG.1Dillustrates a corresponding cross-sectional view of the structure100taken along section line Y1-Y1′ ofFIG.1A, according to an embodiment of the disclosure. Referring toFIG.1D, in one embodiment, the insulating layer108may be arranged on the portion150aof the top surface150of the active layer102c, the conductive layer110may be arranged over the insulating layer108and the barrier layer112may be arranged over the conductive layer110. The fins116a,116band116cmay be arranged over the barrier layer112. In another embodiment, the barrier layer112may be arranged on the portion150aof the top surface150of the active layer102c, in direct contact with the portion150a. The dielectric layer118may be conformally arranged over each of the fins116a,116band116c. In one embodiment, the dielectric layer118may directly contact the first side surface146a, a top surface152and second side surface146bof the fin116a. The dielectric layer118may extend to cover the side surfaces of the barrier layer112and over a portion150bof the top surface150between the fins116a,116band116c. The portion150bmay be adjacent to the insulating layer108. The dielectric layer118may be laterally adjacent to the insulating layer108. The dielectric layer118may also be arranged on the side surfaces and top surfaces of the fins116band116c. In one embodiment, the conductive layer110may have side surfaces, for example, a first side surface156aand a second side surface156bopposite to the first side surface156a. In yet another embodiment, the dielectric layer118may extend to cover the first156aand second156bside surfaces of the conductive layer110. The metal layer120may be arranged on the dielectric layer118. In one embodiment, the metal layer120over the fins116ato116cand over the portion150bof the top surface150of the active layer102claterally adjacent to the fins116ato116cmay be a continuous structure. In one embodiment, the metal layer120may extend to cover the dielectric layer118on the side surfaces of the barrier layer112and the conductive layer110, with the dielectric layer118separating the metal layer120from the conductive layer110. In another embodiment, the metal layer120may be in direct contact with the conductive layer110, for example, the metal layer120may be arranged on the first156aand second156bside surfaces of the conductive layer110. The polysilicon layer122may be arranged on the metal layer120. A gate contact electrode138cmay be arranged on the silicide layer132aover the polysilicon layer122. The interlayer dielectric layer136may be arranged over the silicide layer132aand the gate contact electrode138c.

During device operation, a bias may be applied to the contact electrode138aand the gate contact electrode138cwhile the contact electrode138bmay be grounded. A back-gate bias may also be applied to the semiconductor layer102a. In one embodiment, charge carriers may be generated in a channel region next to the side surfaces and top surfaces of the fins116atocand below the portion150bof the top surface150of the active layer102claterally adjacent to the fins116atoc, leading to a large drive current. In another embodiment, charge carriers may also be generated below the portion150aof the top surface of the active layer102cdirectly below the fins116atoc, further improving the drive current. For example, the charge carriers may be generated directly below the fins116atocwhen the metal layer120is in direct contact with the conductive layer110.

FIG.1Eillustrates a corresponding cross-sectional view of the structure100taken along section line Y2-Y2′ ofFIG.1A, according to an embodiment of the disclosure. Referring toFIG.1E, fin spacer structures158may be arranged on the side surfaces of the fins116a,116band116c. The fin spacer structures158may extend over side surfaces of the barrier layer112, conductive layer110and the insulating layer108. The epitaxial structures142a,142c,142eand142gmay be arranged on the portion150cof the top surface150of the active layer102c. The fin116amay be arranged between the epitaxial structures142aand142c. The fin116bmay be arranged between the epitaxial structures142cand142e. The fin116cmay be arranged between the epitaxial structures142eand142g. The fin spacer structures158may separate the epitaxial structures142aand142cfrom the insulating layer108, conductive layer110, barrier layer112and the fin116a. The fin spacer structures158may separate the epitaxial structures142cand142efrom the fin116b. The fin spacer structures158may separate the epitaxial structures142eand142gfrom the fin116c. Fin epitaxial structures128a,128cand128emay be arranged on the top surfaces of the fins116a,116band116c, respectively. Silicide layers may be formed on the epitaxial structures142a,142c,142eand142gand fin epitaxial structures128a,128cand128e. The contact electrode138amay be arranged on the silicide layers and over the fins116a,116b, and116c.

The semiconductor layer102amay be made of a suitable semiconductor material, for example, silicon. In one embodiment, the semiconductor layer102amay be doped with a suitable n-type dopant, for example, arsenic, phosphorus, or antimony. The buried oxide layer102bmay be made of a suitable dielectric material, for example, silicon dioxide. The active layer102cmay be made of a suitable semiconductor material, for example, silicon. In one embodiment, the active layer102cmay be doped with boron or any other suitable p-type dopants. The isolation structure106may be made of a suitable dielectric material, for example, silicon dioxide. The insulating layer108may be made of a suitable dielectric material, for example, silicon dioxide, silicon nitride, high dielectric constant material for example hafnium oxide, aluminum oxide or any other suitable dielectric materials. The term “high dielectric constant material” may refer to a dielectric material having a dielectric constant greater than 7. The conductive layer110may be made of a suitable conductive material, for example, titanium nitride, titanium, titanium aluminide or any other suitable conductive materials. The barrier layer112may be made of a suitable dielectric material, for example, silicon dioxide, silicon nitride, or any other suitable dielectric materials. The fins116atocmay be made of a suitable semiconductor material, for example, polysilicon, or any other suitable semiconductor materials. In one embodiment, the dielectric layer118may be made of silicon dioxide. In another embodiment, the dielectric layer118may be made of a suitable dielectric material, for example, silicon nitride, high dielectric constant materials, or any other suitable dielectric materials. In one embodiment, the insulating layer108and the dielectric layer118may be made of the same dielectric material. In another embodiment, the insulating layer108and the dielectric layer118may be made of different dielectric materials. The metal layer120may be made of a suitable metal, for example, titanium nitride, titanium, titanium aluminide, or any other suitable metals. In one embodiment, the metal layer120and the conductive layer110may be made of the same material. In another embodiment, the metal layer120and the conductive layer110may be made of different materials. The polysilicon layer122may be doped with a suitable n-type dopant, for example, arsenic, phosphorus, or antimony. The spacer structures126and the fin spacer structures158may be made of a suitable dielectric material, for example, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or any other suitable dielectric materials. The epitaxial structures142atohand fin epitaxial structures128atofmay be made of a suitable semiconductor material, for example, silicon germanium, silicon phosphide, or any other suitable semiconductor material. The silicide layers132atoemay be made of a suitable silicide material, for example, titanium silicide, cobalt silicide, nickel silicide, or any other suitable silicide materials. The interlayer dielectric layer136may be made of a suitable dielectric material, for example, silicon dioxide, high density plasma undoped silicate glass, tetraethyl orthosilicate, a low dielectric constant material, or any other suitable dielectric material. The term “a low dielectric constant material” may refer to a dielectric material having a dielectric constant lower than 3.9. The contact electrodes138aandband gate contact electrode138cmay be made of a suitable metal, for example, tungsten, or any other suitable metals.

FIGS.2A-Bto8A-D illustrate a fabrication process flow for the structure100shown inFIGS.1A to1E, according to some embodiments of the disclosure.FIG.2Aillustrates a top view of the structure100after the formation of the isolation structure106adjacent to the active layer102c, according to an embodiment of the disclosure. The isolation structure106may be formed adjacent to side surfaces of the active layer102cand in a substrate102.

FIG.2Billustrates a corresponding cross-sectional view of the structure100taken along section line X-X′ ofFIG.2A, at an exemplary processing step according to an embodiment of the disclosure. Referring toFIG.2B, a substrate102is provided, the substrate102may be a silicon on insulator substrate. The substrate102may include a semiconductor layer102a, a buried oxide layer102bover the semiconductor layer102aand an active layer102cover the buried oxide layer102b. Isolation structures106may be formed in the substrate102by a material removal process, for example, by forming an opening in the substrate102, through the active layer102c, buried oxide layer102band into the semiconductor layer102aby a conventional photolithography process followed by a wet or dry etch. The conventional photolithography process may include depositing a layer of photoresist material on a top surface of the active layer102cfollowed by exposure and developing to form a suitable photoresist pattern. A wet etch or dry etch process may be used to remove portions of substrate102not covered by the photoresist pattern to form the opening. The photoresist pattern may subsequently be removed. A layer of a suitable dielectric material, for example, silicon dioxide, may be deposited in the opening and over a top surface of the active layer102c. A suitable planarization process, for example, chemical mechanical planarization, may be used to remove portions of the silicon dioxide layer from the top surface of the active layer102c, leaving behind the silicon dioxide layer in the opening, thereby forming the isolation structure106.

FIG.3Aillustrates a top view of the structure100at a subsequent processing step, for example, after deposition of the insulating layer108, the conductive layer110, the barrier layer112and the fin material layer116, according to an embodiment of the disclosure. Although not shown for simplicity, the insulating layer108, the conductive layer110, and the barrier layer112may be arranged below the fin material layer116.

FIG.3Billustrates a corresponding cross-sectional view of the structure100taken along section line X-X′ ofFIG.3A, according to an embodiment of the disclosure. Referring toFIG.3B, the insulating layer108may be deposited on the top surface of the active layer102cand the isolation structure106. The deposition of the insulating layer108may include depositing a layer of a suitable insulating material, for example, silicon dioxide, silicon nitride, high dielectric constant material, for example, hafnium oxide, aluminum oxide, or any other suitable dielectric materials. The conductive layer110may be deposited on a top surface of the insulating layer108. The deposition of the conductive layer110may include depositing a layer of a suitable conductive material, for example, titanium nitride, titanium, titanium aluminide, or any other suitable conductive materials. In one embodiment, the barrier layer112may be deposited on a top surface of the conductive layer110. In an alternative embodiment, the barrier layer112may be deposited on the top surface of the active layer102cand the isolation structure106. The deposition of the barrier layer112may include depositing a layer of a suitable dielectric material, for example, silicon dioxide, silicon nitride, or any other suitable dielectric materials. The insulating layer108, conductive layer110, and barrier layer112may be deposited by atomic layer deposition, physical vapor deposition, chemical vapor deposition or any other suitable deposition processes. The fin material layer116may be deposited on a top surface of the barrier layer112. The deposition of the fin material layer116may include depositing a layer of a suitable semiconductor material, for example, polysilicon, or any other suitable semiconductor materials. The fin material layer116may be deposited by chemical vapor deposition, or any other suitable deposition processes.

FIG.4Aillustrates a top view of the structure100, at a subsequent processing step, after the formation of the fins116a,116band116cand patterning of the insulating layer108, the conductive layer110, and the barrier layer112, according to an embodiment of the disclosure. Referring toFIG.4A, for simplicity, the insulating layer108, the conductive layer110, and the barrier layer112under the fins116atocare not shown. The formation of the fins116atocand patterning of the barrier stack are described inFIGS.4B to4D

FIG.4Billustrates a corresponding cross-sectional view of the structure100taken along section line X1-X1′ ofFIG.4A, according to an embodiment of the disclosure. Referring toFIG.4B, the formation of the fins116atocand patterning of the barrier stack may include a photolithography process followed by a wet or dry etch process. The photolithography process may be used to form suitable photoresist patterns on a top surface of the fin material layer116. The wet etch or dry etch process may be used to remove portions of the fin material layer116and the barrier stack, through the barrier layer112, conductive layer110, and insulating layer108, not covered by the photoresist patterns. The etching processes may leave behind another portion of the barrier stack and fin material layer116under the photoresist patterns. The photoresist patterns may subsequently be removed. The patterning process may remove a portion of the barrier stack, for example, the barrier layer112, conductive layer110and insulating layer108, and the fin material layer116from the top surface of the isolation structure106.

FIG.4Cillustrates a corresponding cross-sectional view of the structure100taken along section line X2-X2′ ofFIG.4A, according to an embodiment of the disclosure. Referring toFIG.4C, the patterning process may expose the top surface of the active layer102claterally adjacent to the fins116atoc.

FIG.4Dillustrates a corresponding cross-sectional view of the structure100taken along section line Y-Y′ ofFIG.4A, according to an embodiment of the disclosure. Referring toFIG.4D, the patterning process may expose side surfaces and top surfaces of the fins116atocand the top surface of the active layer102cbetween the fins116aand116band between the fins116band116c. The patterning process may also expose side surfaces of the barrier layer112, conductive layer110and insulating layer108.

FIG.5Aillustrates a top view of the structure100at a subsequent processing step, after the formation of the dielectric layer118and deposition of the metal layer120, according to an embodiment of the disclosure. Referring toFIG.5A, the fins116atocare shown for clarity. The dielectric layer118under the metal layer120is not shown for simplicity.

FIG.5Billustrates a corresponding cross-sectional view of the structure100taken along section line X1-X1′ ofFIG.5A, according to an embodiment of the disclosure. Referring toFIG.5B, in one embodiment, the dielectric layer118may be deposited on the top surface of the isolation structure106and side surfaces and top surface of the fin116c, side surfaces of the barrier layer112and conductive layer110. The deposition of the dielectric layer118may include depositing a layer of a suitable dielectric material, for example, silicon dioxide, silicon nitride, high dielectric constant materials, or any other suitable dielectric materials. In one embodiment, the dielectric layer118may be deposited by a suitable deposition process, for example, atomic layer deposition, physical vapor deposition, chemical vapor deposition or any other suitable deposition processes. In another embodiment, for example, the dielectric layer118may be thermally grown silicon oxide which may be selectively grown on side surfaces and top surface of the fin116c. The metal layer120may be deposited on the top surface of the dielectric layer118. The deposition of the metal layer120may include depositing a layer of a suitable metal, for example, titanium nitride, titanium, titanium aluminide, or any other suitable metals. The metal layer120may be deposited by a suitable deposition process, for example, atomic layer deposition, physical vapor deposition, chemical vapor deposition or any other suitable deposition processes.

FIG.5Cillustrates a corresponding cross-sectional view of the structure100taken along section line X2-X2′ ofFIG.5A, according to an embodiment of the disclosure. Referring toFIG.5C, the dielectric layer118may be formed on the top surface of the active layer102claterally adjacent to the fin116aand the metal layer120may be deposited on the dielectric layer118.

FIG.5Dillustrates a corresponding cross-sectional view of the structure100taken along section line Y-Y′ ofFIG.5A, according to an embodiment of the disclosure. Referring toFIG.5D, in one embodiment, the dielectric layer118may be deposited on side surfaces and top surfaces of the fins116atoc, side surfaces of the barrier layer112and the conductive layer110and top surface of the active layer102claterally adjacent to the insulating layer108under the fins116atoc. The metal layer120may be deposited over the dielectric layer118. The dielectric layer118may separate the metal layer120from the conductive layer110below the fins116atoc. In an alternative embodiment, the barrier layer112may be in direct contact with the top surface of the active layer102c. The dielectric layer118may be deposited on the side surfaces and top surfaces of the fins116atoc, side surfaces of the barrier layer112and top surface of the active layer102claterally adjacent to the barrier layer112under the fins116atocand the metal layer120may be formed over the dielectric layer118. In yet another embodiment, the dielectric layer118may be thermally and selectively grown on the side surfaces and top surfaces of the fins116atoc, and top surface of the active layer102claterally adjacent to the insulating layer108under the fins116atoc. The metal layer120may be deposited over the dielectric layer118and on side surfaces of the barrier layer112and the conductive layer110. The metal layer120may be in direct contact with the conductive layer110.

FIG.6Aillustrates a top view of the structure100at a subsequent processing step, after the deposition of the polysilicon layer122and hard mask layer140, according to an embodiment of the disclosure. Referring toFIG.6A, the fins116atocare shown for clarity. The polysilicon layer122may be deposited over the isolation structure106, active layer102cand fins116atocand the hard mask layer140may be deposited over the polysilicon layer122. For simplicity, the polysilicon layer122under the hard mask layer140is not shown. The hard mask layer140may be made of silicon nitride. The polysilicon layer122and the hard mask layer140may be deposited by chemical vapor deposition or any other suitable deposition processes.

FIG.6Billustrates a corresponding cross-sectional view of the structure100taken along section line X1-X1′ ofFIG.6A, according to an embodiment of the disclosure. Referring toFIG.6B, the polysilicon layer122may be deposited on the top surface and side surfaces of the metal layer120over the fin116cand the isolation layer106. A suitable planarization process, for example, chemical mechanical planarization, may be used to planarize a top surface of the polysilicon layer122. The hard mask layer140may be deposited on the top surface of the polysilicon layer122.

FIG.6Cillustrates a corresponding cross-sectional view of the structure100taken along section line X2-X2′ ofFIG.6A, according to an embodiment of the disclosure. Referring toFIG.6C, the polysilicon layer122may be deposited on the top surface of the metal layer120over the top surface of the active layer102claterally adjacent to the fin116a.

FIG.6Dillustrates a corresponding cross-sectional view of the structure100taken along section line Y-Y′ ofFIG.6A, according to an embodiment of the disclosure. Referring toFIG.6D, the polysilicon layer122may be deposited on the top surfaces and side surfaces of the metal layer120over the fins116atoc. The polysilicon layer122may also be deposited on the top surface of the metal layer120arranged over the top surface of the active layer102claterally adjacent to the fins116atoc.

FIG.7Aillustrates a top view of the structure100at a subsequent processing step, after the patterning of the hard mask layer140, polysilicon layer122, metal layer120, and dielectric layer118, according to an embodiment of the disclosure. The polysilicon layer122, metal layer120and dielectric layer118may be referred to as a gate stack. Referring toFIG.7A, for simplicity, the polysilicon layer122, metal layer120and dielectric layer118under the hard mask layer140are not shown.

FIG.7Billustrates a corresponding cross-sectional view of the structure100taken along section line X1-X1′ ofFIG.7A, according to an embodiment of the disclosure. Referring toFIG.7B, the patterning process of the hard mask layer140and the gate stack may include a photolithography process followed by a wet or dry etch. A photoresist layer may be deposited on the top surface of the hard mask layer140and patterned by the photolithography process to form a suitable photoresist pattern. A wet etch or dry etch process may be used to remove portions of the hard mask layer140and the gate stack, through the polysilicon layer122, metal layer120and dielectric layer118, not covered by the photoresist pattern. The etching processes may leave behind the hard mask layer140and the gate stack under the photoresist pattern. The photoresist pattern may subsequently be removed. The patterning process may expose the top surface of the fin116claterally adjacent to side surfaces of the hard mask layer140and polysilicon layer122. Although not shown, the patterning process may expose the top surface of the fins116aand116blaterally adjacent to side surfaces of the hard mask layer140and polysilicon layer122. The patterning process may expose the side surfaces of the fin116c, barrier layer112, conductive layer110, and insulating layer108, and the top surface of the isolation structure106. Although not shown, the patterning process may expose the side surfaces of the fins116aand116b.

FIG.7Cillustrates a corresponding cross-sectional view of the structure100taken along section line X2-X2′ ofFIG.7A, according to an embodiment of the disclosure. Referring toFIG.7C, the patterning process may expose the top surface of the active layer102claterally adjacent to the polysilicon layer122and the fin116a. Although not shown, the patterning process may expose the top surface of the active layer102claterally adjacent to the fins116band116c.

FIG.8Aillustrates a top view of the structure100at a subsequent processing step, after the formation of spacer structures126, the fin epitaxial structures128atof, and the epitaxial structures142atoh, according to an embodiment of the disclosure. Referring toFIG.8A, the spacer structures126may be formed along the side surfaces of the hard mask layer140.

FIG.8Billustrates a corresponding cross-sectional view of the structure100taken along section line X1-X1′ ofFIG.8A, according to an embodiment of the disclosure. Referring toFIG.8B, the spacer structures126may be formed on the first148aand second148bside surfaces of the polysilicon layer122, side surfaces of the metal layer120, and dielectric layer118. Fin spacer structures158may be formed on the side surfaces of the fin116c, barrier layer112, conductive layer110and insulating layer108. The spacer structures126and the fin spacer structures158may be formed simultaneously. For example, the formation of the spacer structures126and the fin spacer structures158may include depositing a layer of a suitable dielectric material, for example, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or any other suitable dielectric materials, over the hard mask layer140, polysilicon layer122, metal layer120, and dielectric layer118, fin116c, isolation layer106, and active layer102c. An anisotropic etching process may be used to remove the silicon nitride layer from the top surfaces of the isolation layer106, active layer102c, hard mask layer140, and fin116c, leaving behind the silicon nitride layer on side surfaces of the hard mask layer140, and first148aand second148bside surfaces of the polysilicon layer122. The silicon nitride layer may also be left behind on side surfaces of the metal layer120, and dielectric layer118to form the spacer structures126. The silicon nitride layer may also be left behind on side surfaces of the fin116c, barrier layer112, conductive layer110and insulating layer108to form fin spacer structures158. The term “anisotropic etching” may refer to an etching process that is directional in nature. The fin epitaxial structures128eand128fmay be formed on the top surface of the fin116claterally spaced from the first148aand second148bside surfaces of the polysilicon layer122, respectively. The formation of the fin epitaxial structures128eand128fmay include epitaxial growth of a suitable semiconductor material, for example silicon germanium, silicon phosphide, or any other suitable semiconductor material. The fin epitaxial structures128eand128fmay be doped by a suitable n-type dopant, for example, arsenic, phosphorus, antimony, or any other suitable n-type dopants. The doping process may include implantation followed by annealing.

FIG.8Cillustrates a corresponding cross-sectional view of the structure100taken along section line X2-X2′ ofFIG.8A, according to an embodiment of the disclosure. Referring toFIG.8C, the epitaxial structures142aand142bmay be formed on the top surface of the active layer102claterally spaced from the first148aand second148bside surfaces of the polysilicon layer122, respectively. The formation of epitaxial structures142aand142bmay be done simultaneously with the formation of the fin epitaxial structures128eand128f.

FIG.8Dillustrates a corresponding cross-sectional view of the structure100taken along section line Y2-Y2′ ofFIG.8A, according to an embodiment of the disclosure. Referring toFIG.8D, fin spacer structures158may also be formed on the first146aand second146bside surfaces of the fin116a, and side surfaces of the fins116band116c, barrier layer112, conductive layer110and insulating layer108. The epitaxial structure142amay be formed on the top surface of the active layer102claterally spaced from the first side surface146a. Epitaxial structure142cmay be formed on the top surface of the active layer102cbetween the fins116aand116b. Epitaxial structure142emay be formed between the fins116band116c. Fin epitaxial structures128aand128cmay be formed on the top surfaces of the fins116aand116b, respectively.

The fabrication process may continue to form the structure100illustrated inFIGS.1B to1E. To form the structure100shown inFIG.1B, the hard mask layer140may be removed by a wet etch process using hot phosphoric acid, thereby exposing a top surface of the polysilicon layer122. Silicide layers132atocmay be formed on the top surfaces of the polysilicon layer122, and fin epitaxial structures128eand128f, respectively. The formation of the silicide layers132atocmay include depositing a layer of a suitable metal, for example, titanium, cobalt, nickel, or any other suitable metal over the polysilicon layer122and fin epitaxial structures128eand128f. The titanium may be annealed to form the silicide layers132atoc. The unreacted titanium may subsequently be removed. A layer of a suitable dielectric material, for example, silicon dioxide, high density plasma undoped silicate glass, tetraethyl orthosilicate, a low dielectric constant material, or any other suitable dielectric material, may be deposited over the top surface of the isolation structure106, fin116c, silicide layers132atoc, spacer structures126and fin spacer structures158. A suitable planarization process, for example, chemical mechanical planarization, may be used to planarize the top surface of the silicon dioxide thereby forming the interlayer dielectric layer136. Openings may be made in the interlayer dielectric layer136by patterning with a photolithography process followed by a wet or dry etch. A photoresist layer may be deposited on the top surface of the interlayer dielectric layer136and patterned by a photolithography process to form a suitable photoresist pattern. A wet or dry etch process may be used to remove portions of the interlayer dielectric layer136not covered by the photoresist pattern to form the openings, exposing portions of the silicide layers132band132c. The photoresist layer may subsequently be removed. A layer of a suitable metal, for example, tungsten, may be deposited in the openings. A suitable planarization process, for example, chemical mechanical planarization, may be used to remove the tungsten from the top surface of the interlayer dielectric layer136, leaving behind the tungsten in the openings, thereby forming the contact electrodes138aand138b.

To form the structure100shown inFIG.1C, silicide layers132dand132emay also be formed over the epitaxial structures142aand142b, respectively. The silicide layers132dand132emay be formed simultaneously with the silicide layers132a,132b, and132c. The interlayer dielectric layer136may also be formed over the silicide layers132dand132e. The contact electrodes138aand138bmay also be formed over the silicide layers132dand132e, respectively.

To form the structure100shown inFIG.1D, the gate contact electrode138cmay be formed by forming an opening in the interlayer dielectric layer136above the silicide layer132a. A layer of photoresist may be deposited on the top surface of the interlayer dielectric layer136and patterned by a photolithography process to form a suitable photoresist pattern. A wet etch or dry etch process may be used to remove a portion of the interlayer dielectric layer136not covered by the photoresist pattern to form the opening, exposing a portion of the silicide layer132a. The photoresist pattern may subsequently be removed. A layer of a suitable metal, for example, tungsten, may be deposited in the opening. A suitable planarization process, for example, chemical mechanical planarization, may be used to remove a portion of the tungsten from a top surface of the interlayer dielectric layer136, leaving behind the tungsten in the opening.

To form the structure shown inFIG.1E, silicide layers may be formed over epitaxial structures between the fins116aand116b, and between the fins116band116c, and over fin epitaxial structures on the top surfaces of the fins116aand116b. The contact electrode138amay be formed over the silicide layers and over the fin spacer structures158on side surfaces of the fins116atoc.

The terms “first”, “second”, “third”, and the like in the description and in the claims, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the device described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. The terms “left”, “right”, “front”, “back”, “top”, “bottom”, “over”, “under”, and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the device described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. Similarly, if a method is described herein as comprising a series of steps, the order of such steps as presented herein is not necessarily the only order in which such steps may be performed, and certain of the stated steps may possibly be omitted and/or certain other steps not described herein may possibly be added to the method. Furthermore, the terms “comprise”, “include”, “have”, and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or device that comprises a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or inherent to such process, method, article, or device.

While several exemplary embodiments have been presented in the above detailed description of the device, it should be appreciated that number of variations exist. It should further be appreciated that the embodiments are only examples, and are not intended to limit the scope, applicability, dimensions, or configuration of the devices in any way. Rather, the above detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the devices, it being understood that various changes may be made in the function and arrangement of elements and method of fabrication described in an exemplary embodiment without departing from the scope of this disclosure as set forth in the appended claims.