Patent ID: 12261577

Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.

DETAILED DESCRIPTION

An improved peak detector is provided for an amplifier protection system. The following discussion will assume that the amplifier being protected is a power amplifier in a transmitter, but it will be appreciated that other types of amplifiers may also benefit from the peak detector disclosed herein. The peak detector includes a voltage divider that functions to divide a power amplifier output signal into a divided signal. For example, the voltage divider may be a capacitive voltage divider that advantageously imposes relatively little loading on the amplifier and may be coupled to an output of the amplifier such as to a drain (or drains in differential embodiments) of a transistor (or transistors) which implement the amplification. In addition, the peak detector includes a threshold voltage detector that conducts or pulses a detection current in response to the divided signal being greater than a threshold voltage. The peak detector also includes a current mirror that mirrors the detection current into a mirrored current driven into a node. Finally, the peak detector includes at least one inverter configured to invert a voltage of the node to produce a binary output signal.

Should the divided signal as derived from the power amplifier output signal not exceed the threshold voltage, the threshold voltage detector conducts virtually no current. The threshold voltage detector thus pulses the detection current only in response to the divided signal exceeding the threshold voltage, which advantageously reduces power consumption. In addition, the response time of the threshold voltage detector is relatively fast so that the amplifier protection system may adjust the power amplifier gain relatively quickly before damage occurs to the power amplifier. The threshold voltage detector may be readily integrated with the power amplifier using core devices (thin-oxide transistors).

To increase robustness against noise causing a false peak detection, the peak detector may include a counter that counts the number of times that the binary output signal is asserted within a reset period. If the count exceeds a threshold count before the count is reset at the end of the reset period, the counter asserts a peak detection alarm signal. The amplifier protection system may then respond to an assertion of the peak detection alarm signal by reducing a gain of the power amplifier. Alternatively, the amplifier protection system may respond to an assertion of the binary output signal in implementations without a counter by reducing the gain of the power amplifier.

In a beamforming transmitter, the transmitter will include multiple power amplifiers, each power amplifier driving its own antenna or sub-array of antennas. Each power amplifier may be associated with its own peak detector generating its own peak detection alarm signal. The amplifier protection system may then respond to an assertion of any of the peak detection alarm signals (or the binary output signals in implementations without counters) by reducing a gain for all the power amplifiers. This is advantageous regarding a protection of the power amplifiers without disturbing beamforming and/or beamsteering combined with the beamforming.

An example peak detector100is shown inFIG.1for a differential power amplifier165. A capacitive voltage divider101includes a serial combination of a capacitor C1and C2that is coupled between a positive output of the differential power amplifier165and ground. Similarly, capacitive voltage divider101includes a serial combination of another set of capacitors C3and C4that is coupled between a negative output of the differential power amplifier165and ground. Capacitors C1and C3may be equal to each other. Similarly, capacitors C2and C4may be the same. For a single-ended power amplifier implementation, capacitive voltage divider101may include just one serial combination of capacitors. A node between capacitors C1and C2provides a divided version of the positive output signal whereas a node between capacitors C3and C4provides a divided version of the negative output signal. Note that the designations of “positive” and “negative” for a differential output signal is arbitrary as what is positive and negative will reverse roles depending upon the timing of the signal sampling. Capacitor C1may be directly connected to a drain of a first transistor that implements an amplification function of power amplifier165. Similarly, capacitor C3may be directly connected to a drain of a second transistor that implements an amplification function of power amplifier165. Other configurations for capacitive voltage divider101are possible.

To respond to the divided versions of the positive and negative output signals, a threshold voltage detector102includes a pair of matched transistors M1and M2having their sources connected together and having their drains connected together. The divided version of the positive output signal drives the gate of transistor M1whereas the divided version of the negative output signal drives the gate of transistor M2. To respond to the power amplifier output signals exceeding a peak threshold with an appropriate amount of pulsed current, threshold voltage detector102biases a source voltage, a gate voltage, and a drain voltage for transistors M1and M2. Some example circuits for this biasing will now be discussed.

A source voltage bias for transistors M1and M2in threshold voltage detector102is provided by source bias circuit formed by a PMOS transistor P1, a differential amplifier105, a variable current source115, a variable current source110, and resistor R1. A controller (not illustrated) controls variable current source110to drive resistor R1so as to produce a corresponding voltage at a terminal for resistor R1. This voltage at the resistor terminal is received at one input of the differential amplifier105. An output of the differential amplifier105drives a gate of transistor P1, which has a drain connected to ground and a source connected to the sources of transistors M1and M2. The source of transistor P1also couples to another input of differential amplifier105. A variable current source115drives a current into transistor P1(e.g., into a source of transistor P1) so that during operation of peak detector100, feedback through differential amplifier105will function to keep the source voltage of transistor P1(and hence the source voltage of transistors M1and M2) equal to the voltage across resistor R1. The source voltage of transistors M1and M2may thus be controlled by the current setting of variable current source110. It will be appreciated that variable current sources110and115may be fixed current sources in alternative implementations.

Threshold voltage detector102biases the gate voltages for transistors M1and M2using a gate bias circuit formed by an NMOS transistor M3, a variable current source125, a differential amplifier120, a variable current source126, and resistors R2, R3, and R4. Resistor R2connects between ground and an output of variable current source126. Resistor R2may be matched to resistor R1so that if variable current source126is controlled to output the same amount of current as variable current source110, the voltages across resistors R1and R2are equal. Since the voltage across resistor R1is the source voltage for transistors M1and M2, the voltage across resistor R2is also equal to the source voltage for transistors M1and M2for implementations in which the voltages across resistors R1and R2are equal. The voltage across resistor R2is received at a first input of differential amplifier120. An output of differential amplifier120drives a gate of transistor M3, which is matched to transistors M1and M2. Transistor M3has its source connected to ground and a drain connected to a second input of differential amplifier120. Current source125drives a biasing current into the drain of transistor M3. In implementations in which resistors R1and R2are matched and driven with the same amount of current, the voltage across resistor R2is equal to the source voltage of transistors M1and M2. Feedback through differential amplifier120will thus force the drain voltage of transistor M3to equal the source voltages of transistors M1and M2in such implementations. The output of differential amplifier120connects to the gate of transistor M2through resistor R4and to the gate of transistor M1through resistor R3. Resistor R3may be matched to resistor R4so that the bias to the gate voltages of transistor M1and M2are equal. This gate bias voltage equals the gate voltage of transistor M3. The gate bias voltage will be less than the source voltage of transistors M1and M2so that in a default state, transistors M1and M2are not conducting as the transistor threshold voltage is not satisfied. The gate-to-source bias of transistors M1and M2will depend upon the resistances of resistors R1and R2as well as the output currents of current sources110,125, and126and will vary in different implementations. In an example implementation, the gate voltage bias may be approximately 0.36 V whereas the source voltage is approximately 0.5V. The gate-to-source bias voltage for transistors M1and M2is thus approximately −0.24 V in such an example implementation, which assures that transistors M1and M2are non-conductive in the default state. But transistor M1is switched on to conduct current when the divided version of the positive amplifier output signal rises above a threshold voltage such that the gate-to-source voltage of transistor M1exceeds its transistor threshold voltage. Similarly, transistor M2is switched on to conduct current when the divided version of the negative amplifier output voltage rises above the threshold voltage such that the gate-to-source voltage of transistor M2exceeds its transistor threshold voltage.

The amount of current that transistor M1or transistor M2will conduct when its transistor threshold voltage is satisfied depends upon their drain-to-source bias voltage. To bias the drain voltage of transistors M1and M2and thus control the current conducted, threshold voltage detector102includes a drain bias circuit formed by a differential amplifier170, an NMOS transistor M4, a variable current source145, a resistor R5, and a current source135. The source of transistor M4connects to the drains of transistors M1and M2. Current source135couples between the source of transistor M4and ground to bias transistor M4with a source current. With transistor M4biased with the source current, a feedback loop is formed by differential amplifier170and transistor M4. In particular, current source145drives a current into a first terminal of resistor R5, which has a second terminal coupled to ground. The first terminal of resistor R5connects to a first input of differential amplifier170. The drains of transistors M1and M2as well as the source of transistor M4connect to a second input of differential amplifier170. An output of differential amplifier170drives the gate of transistor M4. The feedback loop formed by differential amplifier170and transistor M4thus functions to keep the drain voltage of transistors M1and M2equal to the voltage across resistor R5. In one implementation, the current from current source145and the resistance for resistor R5may be configured so that the voltage across resistor R5is approximately one volt so that the drain voltage of transistors M1and M2is also approximately one volt, but it will be appreciated that a smaller or larger drain voltage bias may be applied in alternative implementations.

Regardless of the exact bias voltages applied, biasing the gate, drain, and source voltages for transistors M1and M2allows a user to define the peak threshold voltage in the amplifier output signal that will trigger either of transistors M1and M2to conduct a defined amount of current, which is also denoted herein as a detection current. This detection current is mirrored by a current mirror such as formed by a PMOS transistor P2and a PMOS transistor P3. Transistor P2is diode connected and thus has its drain connected to its gate. A drain of transistor P2connects to the drain of transistor M4. A source for each of transistors P2and P3connects to a power supply node for a power supply voltage. The gate of transistor P2connects to the gate of transistor P3to complete the current mirror. It will be appreciated that each of transistors P2and P3may be repeated in series in alternative current mirror implementations. Regardless of how many transistors are used to form the current mirror, the current mirror mirrors the detection current into a mirrored current. The mirrored current is driven into a relatively-high impedance node151. A current source such as a variable current source140discharges current from node151into ground. By controlling the amount of current discharged by variable current source140, a controller may control the delay necessary for the mirrored current to charge node151to the trip voltage of an inverter155. Inverter155is in series with another inverter160to produce the binary output signal. The binary output signal will thus be asserted when the mirrored current charges node151above the trip point or threshold voltage for inverter155. The output of inverter155will then be discharged, which causes inverter160to assert the binary output signal.

As the input signal amplitude being amplified by amplifier165reduces, the threshold voltage detector102is no longer triggered such that whichever transistor M1or M2that had been conducting the detection current stops conducting. The binary output signal will then again be discharged to its default state. With regard to a single assertion of the binary output signal as triggered by peak detector100, this assertion may be due to noise in the amplifier output signal. To distinguish between noise and actual peaks in the amplifier output signal, peak detector100may include a counter such as a ripple counter150. Ripple counter150counts the number of assertions of the binary output signal as produced by inverters155and160within a reset period to provide a count. At the end of the reset period, ripple counter150resets its count. But if the count exceeds a threshold count (e.g., a programmable threshold count), ripple counter150asserts an alarm signal so that the gain of power amplifier165may be reduced accordingly. In alternative implementations, other types of counters may be used such as a synchronous counter. In some embodiments, a duration or length of time during which the divided output of power amplifier165exceeds the threshold voltage is used to determine if the alarm signal is asserted in lieu of using a count.

Example implementations of a divider, threshold voltage detector, current mirror, counter, and bias circuits are described above. Those of skill in the art will appreciate that these implementations are merely illustrative and that other implementations may be used. For example, any circuit or connection that couples a voltage at an output of an amplifier (e.g., the power amplifier165) to an input of a threshold voltage detector, and/or that scales down such voltage, may be used in place of the capacitive voltage divider101. In some embodiments, the current mirror is omitted and an output of the threshold voltage detector is directly connected or connected via another circuit to an input of a circuit configured to assert a binary or pulse signal or other signal that can be counted. In some embodiments, the counter is configured to count a rising and/or falling edge of a signal from the threshold voltage detector and/or current mirror (e.g., as generated at the node151). In some embodiments, the bias circuits (e.g., the loops therein) illustrated inFIG.1track process and temperature and minimize variation in operation due to supply fluctuations.

In some embodiments, all of the elements illustrated inFIG.1are implemented in an integrated circuit (IC). For example, the amplifier165may be configured to output signals having a frequency above approximately 20 GHz (e.g., millimeter wave (mmW) or FR2 signals), and the integrated circuit may therefore be configured as a mmW IC. In some such embodiments, the alarm signal may be provided to a component external to the IC (and potentially external to a module within which the IC is implemented). In some embodiments, the counter and/or the inverters (or other circuit elements configured to output a binary signal) are implemented external to the IC.

A plurality of peak detectors may be integrated within an amplifier protection system200as shown inFIG.2to protect a plurality of power amplifiers. Each power amplifier is the final amplifier in a corresponding transmit amplifier chain. For example, a power amplifier205is the fourth amplifier in an amplifier chain201that begins with a stage (stg) 0 amplifier and precedes through a stage 1 and a stage 2 amplifier to drive power amplifier205. Similarly, a power amplifier210is the fourth amplifier in an amplifier chain202that begins with a stage (stg) 0 amplifier and precedes through a stage 1 and a stage 2 amplifier to drive power amplifier210. One or both of power amplifiers205and210may be an example of power amplifier165(FIG.1).

Each amplifier chain functions to amplify an RF input signal such as generated by a mixer240. In a direct conversion architecture, mixer240mixes a baseband input signal such as produced by a modem235to form the RF input signal. In a heterodyne architecture, mixer240may instead upconvert an intermediate frequency signal to form the RF input signal. Amplifier protection system200may be incorporated into a beamforming transmitter. To apply a different phasing to the RF signal being amplified by each amplifier chain, amplifier chain201includes a phase shifter245whereas amplifier chain202includes a phase shifter250.

In general, a beamforming transmitter may have more than the two amplifier chains. It will thus be appreciated that amplifier chains201and202are merely representative and may be part of a larger plurality of amplifier chains. For example, amplifier chain201may be deemed as being the ith chain in such a plurality (i being a positive integer) whereas amplifier chain202may be deemed as the (i+1)th chain. Each chain has its own peak detector. For example, power amplifier205in chain201is monitored by a peak detector215that controls an ith alarm signal (Alarm i). Similarly, a peak detector220monitors power amplifier210in chain202to control an (i+1)th alarm signal designated as Alarm i+1. One or both of the peak detectors215and220may be an example of peak detector100(FIG.1).

To monitor whether any alarm signal is asserted, amplifier protection system200may include a logic gate such as an OR gate225. OR gate225functions to assert a system alarm signal whenever any monitored alarm signal is asserted. Other circuits for accumulating alarms from respective amplifier chains and for asserting a system alarm signal may be implemented. A controller236(which may be integrated with modem235in some implementations) responds to the assertion of the system alarm signal by asserting a gain reduction command. The amplifiers in each amplifier chain have their gain controlled by a corresponding gain control circuit230, which responds to the assertion of the gain reduction command by reducing a gain of all the amplifiers in the corresponding amplifier chain. In alternative implementations, just a subset of the amplifiers in each amplifier chain may have their gain reduced in this fashion. Note that controller236functions to reduce the gain for all the active amplifier chains in some embodiments. This is advantageous with regard to not disturbing any beamforming and/or beamsteering. For example, other methods may disable or adjust the gain or bias of one or a subset of power amplifiers in a phased array, potentially without reference to the operation of other power amplifiers in the array. Aspects described herein may provide a unified power control which considers operation of all transmit chains in a phased array so as to maintain proper beamforming and/or beamsteering operation. For example, a primary direction of a beam may be maintained, and/or a concentration of transmitted energy may be focused/maintained such that communications with a receiving device is not severed or significantly disturbed. In some embodiments, gain is uniformly reduced across all power amplifiers in the phased array. In some embodiments, gain is reduced to one or more power amplifiers in the array without adjusting a bias of the respective power amplifier. In some embodiments, the phase shifter(s) in a transmit chain (e.g.,245,250) may be adjusted (e.g., by the controller236) when the gain is reduced. In addition, controller236may coordinate the assertion of the gain reduction command so that the gain reduction is not applied in the middle of a current symbol transmission but instead at the beginning of a subsequent symbol.

In some embodiments, all of the elements illustrated inFIG.2except the modem235are implemented in an IC, for example a mmW IC. In some embodiments, the controller236and/or the logic gate (225) are implemented external to the IC.

An example beamsteering RF transceiver for a cellular telephone300is shown inFIG.3that includes an amplifier protection system with a peak detection as disclosed herein. The architecture includes a modem (modulator/demodulator)302, a digital to analog converter (DAC)304, a mixer306, and a splitter330. Mixer306upconverts a baseband signal to RF. In alternative embodiments, a heterodyne mixer array may be used instead that first upconverts from baseband to an intermediate frequency. The transceiver includes a plurality of amplifier chains. Each amplifier chain includes a first amplifier312, a phase shifter314, and a power amplifier316. Transmission lines or other waveguides, wires, traces, or the like are shown connecting the various components to illustrate how signals to be transmitted may travel between components. Each amplifier chain drives a corresponding antenna (or antennas)320. The antenna elements320may include patch antennas or other types of antennas arranged in a linear, two dimensional, or an alternative pattern. A spacing between antenna elements320may be such that signals with a desired wavelength transmitted separately by the antenna elements320may interact or interfere (e.g., to form a desired beam). For example, given an expected range of wavelengths or frequencies, the spacing may provide a quarter wavelength, half wavelength, or other fraction of a wavelength of spacing between neighboring antenna elements320to allow for interaction or interference of signals transmitted by the separate antenna elements320within that expected range.

The modem302processes and generates digital baseband signals and may also control operation of the DAC304, first amplifiers312, phase shifters314, and/or the power amplifiers316to transmit signals via one or more or all of the antenna elements320. The modem302may process signals and control operation in accordance with a communication standard such as 5G or according to an IEEE 802 standard (e.g., WiFi). The DAC304may convert digital baseband signals received from the modem302(and that are to be transmitted) into analog baseband signals. The mixer306upconverts analog baseband signals to analog RF signals.

In the illustrated architecture, signals upconverted by the mixer306are split or duplicated into multiple signals by the splitter330. The splitter330in cellular telephone300splits the RF signal into a plurality of identical or nearly identical RF signals. In other examples, the split may take place with any type of signal including with baseband digital, baseband analog, or IF analog signals. Each of these signals may correspond to an antenna element320and the signal travels through and is processed by amplifiers312,316, phase shifters314, and/or other elements to be transmitted by the corresponding antenna element320. In one example, the splitter330may be an active splitter that is connected to a power supply and provides some gain so that RF signals exiting the splitter330are at a power level equal to or greater than the signal entering the splitter330. In another example, the splitter330is a passive splitter that is not connected to a power supply and the RF signals exiting the splitter330may be at a power level lower than the RF signal entering the splitter330.

After being split by the splitter330, the resulting RF signals may enter an amplifier, such as a first amplifier312, or a phase shifter314corresponding to an antenna element320. The first amplifiers312and power amplifiers316are illustrated with dashed lines because one or both of them might not be necessary in some implementations. By way of example, if the splitter330is an active splitter, the first amplifier312may not be used. Each phase shifter314may provide a configurable phase shift or phase offset to a corresponding RF signal to be transmitted. The phase shifter314could be a passive phase shifter not directly connected to a power supply. Passive phase shifters might introduce some insertion loss. Each power amplifier316may boost the signal to compensate for the insertion loss. Each phase shifter314may be an active phase shifter connected to a power supply such that the active phase shifter provides some amount of gain or prevents insertion loss. The settings of each of the phase shifters314are independent meaning that each can be set to provide a desired amount of phase shift. In some embodiments, the phase shifters may be implemented such that a phase of a local oscillator signal coupled to an upconversion mixer in the amplifier chain is adjusted instead of the phase being adjusted in the signal path. For example, the mixer306may be configured to upconvert a baseband signal to an intermediate frequency signal, and an additional mixer (not illustrated) may be implemented in each amplifier chain to upconvert the intermediate frequency signal to a respective radio frequency (e.g., mmW) signal. The modem302may have at least one control line (not illustrated) connected to each of the phase shifters314to configure the phase shifters314to provide a desired amounts of phase shift or phase offset between antenna elements320.

A peak detector325is associated with each power amplifier316and functions as discussed herein to monitor its power amplifier's output signal(s) to determine whether an alarm signal should be asserted. Should one of the peak detectors325assert its alarm signal (or one or more of the peak detectors assert more than a threshold number of alarm signals during a reset period), a controller335functions to assert a gain reduction command to reduce the gain of the first amplifiers312and/or power amplifiers316. Gain control circuits230and OR gate225are not shown inFIG.3for illustration clarity but may be included.

The modem302may be an example of the modem235(FIG.2). The mixer306may be an example of the mixer240. The splitter330may be configured as illustrated inFIG.2. One or more of the amplifiers312may be an example of the stg 0 amplifier. One or more of the phase shifters314may be an example of the phase shifter245,250. One or more of the amplifiers316may be an example of the amplifier205,210. One or more of the peak detectors325may be an example of the peak detector215,220. The controller335may be an example of the controller236.

In some embodiments, all of the elements306-335are implemented together in a single module. In other embodiments, the mixer306and/or the splitter330are implemented external to the module (for example, when each amplifier chain includes a respective mixer, as described above). In some embodiments, the controller335and/or a portion thereof is implemented external to the module. In some embodiments, the elements312-316and325are implemented in an IC within the module. In other embodiments, the IC is not included in a module with the antennas320. The elements306,330, and/or335may be included in the IC.

An example method of peak detection will now be discussed with reference to the flowchart ofFIG.4. The method includes an act400of dividing an amplifier output signal to form a divided signal. The operation of capacitive divider101is an example of act400. In addition, the method includes an act405of conducting a detection current in response to the divided signal being greater than a threshold voltage. The conduction of the detection current by either of transistor M1and M2in threshold voltage detector102is an example of act405. The method also includes an act410of mirroring the detection current into a mirrored current driven into a node. The mirroring of the detection current into node151is an example of act410. Finally, the method includes an act415of asserting a binary output signal in response to a voltage of the node exceeding a trip voltage. The assertion of the binary output signal by inverters155and160is an example of act415.

The disclosure will now be summarized in the following example clauses:

Clause 1. A peak detector, comprising:

a voltage divider configured to divide an amplifier output signal into a divided signal;a threshold voltage detector configured to conduct a detection current in response to the divided signal being greater than a threshold voltage;a current mirror configured to mirror the detection current into a mirrored current and configured to drive the mirrored current into a node; andat least one inverter configured to invert a voltage of the node to produce a binary output signal.
Clause 2. The peak detector of clause 1, further comprising:a counter configured to count binary transitions in the binary output signal to form a count and configured to assert a peak detector alarm signal in response to the count exceeding a peak detection threshold count.
Clause 3. The peak detector of clause 2, wherein the counter is a ripple counter.
Clause 4. The peak detector of any of clauses 2-3, further comprising:a controller configured to command an amplifier to reduce a gain in response to an assertion of the peak detector alarm signal.
Clause 5. The peak detector of any of clauses 1-4, wherein the threshold voltage detector comprises:a first transistor having a gate configured to be driven by the divided signal.
Clause 6. The peak detector of clause 5, the threshold voltage detector further including a source bias circuit configured to bias a source of the first transistor, a gate bias circuit configured to bias a gate of the first transistor, and a drain bias circuit configured to bias a drain of the first transistor.
Clause 7. The peak detector of clause 6, wherein the source bias circuit comprises:a first current source configured to drive a resistor with a first current to develop a source bias voltage at a terminal of the resistor,a second transistor;a second current source configured to drive a second current into a drain of the second transistor; anda differential amplifier having a first input coupled to the terminal of the resistor, a second input coupled to the source of the first transistor; and an output coupled to a gate of the second transistor, wherein the differential amplifier and the second transistor are configured to form a feedback loop to bias the source of the first transistor with the source bias voltage.
Clause 8. The peak detector of clause 7, wherein the first transistor is an n-type-metal-oxide-semiconductor (NMOS) transistor, and the second transistor is a p-type-metal-oxide-semiconductor (PMOS) transistor.
Clause 9. The peak detector of any of clauses 6-7, wherein the first current source is a variable current source.
Clause 10. The peak detector of any of clauses 6-9, wherein the gate bias circuit comprises:a first current source configured to drive a first resistor with a first current to develop a bias voltage at a terminal of the first resistor,a second transistor;a second current source configured to drive a second current into a drain of the second transistor; anda differential amplifier having a first input coupled to the terminal of the first resistor, a second input coupled to a drain of the second transistor; and an output coupled to a gate of the second transistor, wherein the differential amplifier and the second transistor are configured to form a feedback loop to bias the gate of the first transistor with a gate bias voltage.
Clause 11. The peak detector of clause 10, wherein the gate bias circuit further comprises a second resistor coupled between the gate of the first transistor and the gate of the second transistor.
Clause 12. The peak detector of any of clause 6-11, wherein the drain bias circuit comprises:a first current source configured to drive a resistor with a first current to develop a drain bias voltage at a terminal of the resistor,a second transistor having a source coupled to a drain of the first transistor;a second current source configured to drive a second current into ground from the source of the second transistor; anda differential amplifier having a first input coupled to the terminal of the resistor, a second input coupled to the drain of the first transistor; and an output coupled to a gate of the second transistor, wherein the differential amplifier and the second transistor are configured to form a feedback loop to bias the drain of the first transistor with the drain bias voltage.
Clause 13. The peak detector of any of clauses 1-12, wherein the threshold voltage detector comprises an NMOS transistor configured to conduct the detection current, and wherein the current mirror comprises a diode-connected first PMOS transistor having a gate connected to a gate of a second PMOS transistor.
Clause 14. The peak detector of clause 13, wherein a drain of the second PMOS transistor is coupled to the node.
Clause 15. The peak detector of any of clauses 1-14, wherein the at least one inverter comprises a pair of inverters.
Clause 16. A method of peak detection for an amplifier, comprising:dividing an amplifier output signal from the amplifier to form a divided signal;conducting a detection current in response to the divided signal being greater than a threshold voltage;mirroring the detection current into a mirrored current driven into a node; andasserting a binary output signal in response to a voltage of the node exceeding a trip voltage.
Clause 17. The method of clause 16, further comprising:biasing a source, a gate, and a drain of a transistor to form a biased transistor, wherein conducting the detection current comprises conducting the detection current through the biased transistor.
Clause 18. The method of any of clauses 16-17, further comprising:counting binary transitions of the binary output signal to form a count; andasserting an alarm signal in response to the count exceeding a threshold count.
Clause 19. The method of clause 18, further comprising:reducing a gain of the amplifier in response to an assertion of the alarm signal.
Clause 20. The method of clause 19, further comprising reducing a gain of additional amplifiers in response to the assertion of the alarm signal.
Clause 21. A transmitter, comprising:a plurality of antennas;a plurality of power amplifiers corresponding to the plurality of antennas, each power amplifier configured to drive a respective one of the antennas with an amplified RF output signal;a plurality of peak detectors corresponding to the plurality of power amplifiers, each peak detector being configured to generate an alarm signal in response to the corresponding power amplifier's amplified RF output signal being greater than a peak threshold; anda controller configured to reduce a gain for at least one of the power amplifiers responsive to an assertion of any of the alarm signals.
Clause 22. The transmitter of clause 21, further comprising a logic gate configured to process the alarm signals to generate a system alarm, wherein the controller is further configured to reduce the gain of each of the power amplifiers in response to an assertion of the system alarm
Clause 23. The transmitter of clause 22, wherein the transmitter is a cellular telephone transmitter and the logic gate is an OR gate.
Clause 24. The transmitter of any of clauses 22-23, further comprising a plurality of amplifier chains, each amplifier chain including a respective one of the power amplifiers and at least one additional amplifier, wherein the controller is further configured to reduce the gain of each at least one additional amplifier responsive to the assertion of the system alarm.
Clause 25. The transmitter of any of clauses 22-24, wherein the transmitter is beamsteering transmitter, each amplifier chain further including a phase-shifter.
Clause 26. The transmitter of clause 24, wherein each at least one additional amplifier comprises a plurality of additional amplifiers.
Clause 27. The transmitter of any of clauses 21-26, wherein each power amplifier is a differential power amplifier.
Clause 28. The transmitter of any of clauses 22-26, wherein each peak detector includes a threshold voltage detector configured to pulse a detection current in response to the amplified RF output signal of the corresponding power amplifier being greater than a current threshold and includes a counter configured to count how many times the detection current is pulsed to form a count, the counter being further configured to assert the peak detector's alarm signal in response to the count exceeding a threshold count.
Clause 29. The transmitter of any of clauses 21-28, wherein the controller is configured to reduce the gain for all of the plurality of power amplifiers uniformly in response to the assertion of any of the alarm signals.
Clause 30. The transmitter of any of clauses 21-28, wherein the controller is configured to reduce the gain for multiple power amplifiers in response to the assertion of any of the alarm signals.
Clause 31. The transmitter of any of clauses 21-30, wherein each of the plurality of peak detectors is connected to a drain of a transistor which implements an amplification function of the respective power amplifier.
Clause 32. The transmitter of clause 21, further comprising an accumulator coupled to outputs of the plurality peak detectors and configured to assert a system alarm based on one or more of the alarm signals, wherein the controller is configured to reduce the gain of the at least one power amplifier in response to an assertion of the system alarm.
Clause 33. The transmitter of any of clauses 21-32, wherein the controller is configured to reduce the gain of the at least one power amplifier while maintaining a beamforming operation in response to an assertion of the system alarm.
Clause 34. The peak detector of any of clauses 1-15, wherein the voltage divider is connected to a drain of a transistor configured to amplify a signal in the amplifier.

As those of some skill in this art will by now appreciate and depending on the particular application at hand, many modifications, substitutions and variations can be made in and to the materials, apparatus, configurations and methods of use of the devices of the present disclosure without departing from the scope thereof In light of this, the scope of the present disclosure should not be limited to that of the particular embodiments illustrated and described herein, as they are merely by way of some examples thereof, but rather, should be fully commensurate with that of the claims appended hereafter and their functional equivalents.