Patent ID: 12230578

DETAILED DESCRIPTION

For the embodiment below is described in detail with the accompanying drawings, embodiments are not provided to limit the scope of the present disclosure. Moreover, the operation of the described structure is not for limiting the order of implementation. Any device with equivalent functions that is produced from a structure formed by a recombination of elements is all covered by the scope of the present disclosure. Drawings are for the purpose of illustration only, and not plotted in accordance with the original size.

It will be understood that when an element is referred to as being “connected to” or “coupled to”, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element to another element is referred to as being “directly connected” or “directly coupled,” there are no intervening elements present. As used herein, the term “and/or” includes an associated listed items or any and all combinations of more.

FIG.1is a schematic diagram of a semiconductor chiplet device in some embodiments of the present disclosure. The semiconductor chiplet device100includes a first die D10and at least one second die D20. In one embodiment, the first die D10may be a main Die or a System on a Chip. The second die D20may be a chiplet, or another slave die in the dual-main chip structure. The first die D10includes a first interface D11, and the second die D20includes a second interface D21. The first interface D11and the second interface D21is configured to perform a data transmission between the first die D10and the second die D20, to form a package interconnection transmission network between semiconductor chips.

The above the first interface D11and second interface D21may be implemented by a I/O interface circuit in the die (Transmitter/Receiver interface, Transmitter/Receiver interface phy). As shown inFIG.1, each die has multiple connection interfaces, but in other embodiments, the die can also be connected to other dies through only one connection interface. The present disclosure provides a decoupling area300between the two interfaces D11and D21, or in the vertical projection area of the two interfaces D11and D21. By the decoupling capacitor of the decoupling area300, the power integrity of the die and the quality of the transmission signal are improved.

FIG.2is a partial structure schematic diagram of a semiconductor chiplet device100in some embodiments of the present disclosure, which corresponds to a section line A-A′ of the semiconductor chiplet device100inFIG.1. For clarity,FIG.2omits the parts of the first die D10except the first interface D11, and omits the parts of the second die D20except the second interface D2.

As shown inFIG.2, the semiconductor chiplet device100is arranged on the circuit board110, include a package substrate120, an interposer layer130a first die D10and a second die D20. The circuit board110is electrically connected to a first power node Vdd and a second power node Vss (e.g., ground). The first power node Vdd is configured to provide a driving voltage to the semiconductor chiplet device100, so as to drive electronic components in the first die D10and the second die D20. In particular, the first power node Vdd and the second power node Vss is configured to refer to nodes connected to a specific potential.

In one embodiment, the package substrate120through multiple bumps BP1, BP2connected to the circuit board110by thin film process, electroless plating process technology, electroplating or printing technology, so as to electrically connect to the first power node Vdd and the second power node Vss through the circuit board110.

The first side (the upper side as shown inFIG.2) of the interposer layer130is configured to set the first die D10and the second die D20. The second side (the bottom side as shown inFIG.2) of the interposer layer130is configured to set the package substrate120, and is electrically connected to the package substrate120. The interposer layer130can also be connected to the package substrate120, the first die D10and the second die D20through multiple bumps BP3.

The first die D10and the second die D20is electrically connected to the first power node Vdd through the interposer layer130, the package substrate120and the circuit board110, so as to receive the driving voltage.

Specifically, the material of the interposer layer130can be a silicon interposer, which is provided with multiple layers of wires. The wires are configured to connect the electronic signals between the dies, and can be connected to external bumps by a through silicon vias (TSV) and a wire carrier, so that the dies are tightly connected to the package substrate.

The semiconductor chiplet device100further includes at least one decoupling capacitor Cd. The decoupling capacitor Cd is arranged on the interposer layer130or the package substrate120, and the position of the decoupling capacitor Cd corresponds to the setting positions of the first interface D11and the second interface D21. The first interface D11and the second interface D21are electrically connected to the second power node Vss through the decoupling capacitor Cd, so as to form a discharge path configured to eliminate noise (i.e., the first die D1and the second die D2form at least one discharge path with the decoupling capacitor Cd). As shown inFIG.2, the positions of the decoupling capacitor Cd corresponds to a position between vertical projection areas of the first interface D11and the second interface D21. In some other embodiments, the positions of the decoupling capacitor Cd can also be located at the vertical projection area of the first interface D11, the second interface D21, or be located between the first die D10the second die D20. “The vertical projection area” refers to the area where the first interface D11and the second interface D21are projected onto the package substrate120or the interposer layer130.

Accordingly, during the semiconductor chiplet device100is operating, if noise is generated on the first die D10or the second die D20, the noise will be conducted to the second power node Vss through the decoupling capacitor Cd without affecting other dies or other components of the circuit board110. By using the decoupling capacitor Cd to eliminate noise, the power supply voltage can be prevented from being interfered and reduce beyond the normal range, and the power integrity optimization of the semiconductor chiplet device100can be ensured.

In addition, since the decoupling capacitor Cd is located between the first interface D11and the second interface D21, or is located in the projection area of the first interface D11and the second interface D21, instead of being located at a position farther away from the same horizontal plane as the first die D1/the second die D21(i.e., the distance is shorter), the effect of the decoupling capacitor Cd can be ensured.

In one embodiment, the decoupling capacitor Cd is arranged on the package substrate120. As shown inFIG.2, the decoupling capacitor Cd is arranged between the package substrate120and the circuit board110(i.e., a side of the package substrate120facing the circuit board110). However, the present disclosure is not limited to this, the decoupling capacitor Cd can also be arranged between the package substrate120and the interposer layer130(e.g., a side of the package substrate120facing the interposer layer130).

As shown inFIG.2, in some other embodiments, the decoupling capacitor Cd is arranged on the interposer layer130, and is arranged between the interposer layer130and the package substrate120. In other words, the decoupling capacitor Cd is arranged on a side of the interposer layer130facing the package substrate120), such as setting between the bump BP1and the bump BP2. In some other embodiments, the decoupling capacitor Cd can also be arranged on a first side of the interposer layer130, which is located between the first die D10and the second die D20.

In some embodiments, the number of the decoupling capacitor Cd can be adjusted. For example, the semiconductor chiplet device100can provide one decoupling capacitor Cd under the space between the first interface D11and the second interface D21, or the semiconductor chiplet device100can also provide a decoupling capacitor Cd under the first interface D11and the second interface D21, respectively.

FIG.3is a schematic diagram of the vertical projection areas of die D1, D2on the package substrate120or the interposer layer130and the decoupling capacitor in some embodiments of the present disclosure, as mentioned above, in the present disclosure, the decoupling capacitor Cd of the decoupling area300is arranged adjacent to the vertical projection areas of the two interfaces D11and D21to solve the noise problem of the die.FIG.3shows the locations of multiple nodes B11-B15, B21-B25. In one embodiment, the nodes B11-B15, B21-B25represent bumps BP1between the package substrate120and the interposer layer130inFIG.2, or represent bumps BP2between the package substrate120and the circuit board110inFIG.2.

Nodes B11-B15is electrically connected to the first interface D11, and nodes B21-B25is electrically connected to the second interface D21. For example, the nodes B11, B12are used as multiple first power nodes of the first interface D11of the first die D10, and the node B13is used as the first ground node of the first interface D11of the first die D10. Similarly, the nodes B21and B22are used as multiple second power nodes of the second interface D21of the second die D20, and the nodes B23is used as the second ground node of the second interface D21of the second die D20. The nodes B11, B12, B21, B22are electrically connected to the first power node Vdd through the package substrate120and the circuit board110. The nodes B13and B23are connected to the second power node Vss through the decoupling capacitor Cd.

The embodiment inFIG.2draws one decoupling capacitor Cd, but in some other embodiments, the semiconductor chiplet device100may include multiple decoupling capacitors. As shown inFIG.3, in one embodiment, the semiconductor chiplet device100includes a first decoupling capacitor C1, a second decoupling capacitor C2and a third decoupling capacitor C3(i.e., the decoupling capacitor Cd inFIG.2). All of the decoupling capacitors C1-C3are electrically connected to the first power node Vdd and the second power node Vss through the interposer layer130, the package substrate120and the circuit board110. The decoupling capacitors C1-C3are connected in parallel with each other. As shown inFIG.3, the position of the first decoupling capacitor C1is arranged in a first vertical projection area of the first interface D11, and the second decoupling capacitor C2is arranged in a second vertical projection area of the second interface D21. The third decoupling capacitor C3is arranged between the first vertical projection area and the second vertical projection area. As mentioned above, the decoupling capacitors C1-C3can be arranged on the interposer layer130or the package substrate120. “The vertical projection area” refers to the projection area of the interfaces D11, D21on the interposer layer130or the package substrate120.

In one embodiment, the first decoupling capacitor C1is arranged between the nodes B11and B12connected to the first power node Vdd. The second decoupling capacitor C2is arranged between the nodes B21and B22, wherein the nodes B21and B22are connected to the first power node Vdd. The above “position” is a vertical projection position corresponding to the semiconductor chiplet device100.

In some embodiments, the first die D1and the second die D2operate in different power domains. In other words, the operating voltages of the first die D1and the second die D2are different from each other. In addition, when the first die D1and the second die D2operate in different power domains, the semiconductor chiplet device100will generate the switching noise (simultaneously switching noise, SSN). The switching noise is generated by the first die D1or the second die D2. The decoupling capacitor Cd may transmit the switching noise to the second power node Vss, so that the switching noise will not affect the power supply stability of the first power node Vdd.

The elements, method steps, or technical features in the foregoing embodiments may be combined with each other, and are not limited to the order of the specification description or the order of the drawings in the present disclosure.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this present disclosure provided they fall within the scope of the following claims.