Patent ID: 12225796

DETAILED DESCRIPTION

The invention will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the invention.

To clearly describe the invention, parts that are irrelevant to the description are omitted, and like numerals refer to like or similar constituent elements throughout the specification.

Further, since sizes and thicknesses of constituent elements shown in the accompanying drawings are arbitrarily given for better understanding and ease of description, the invention is not limited to the illustrated sizes and thicknesses. In the drawings, the thicknesses of layers, films, panels, regions, etc., are exaggerated for clarity. In the drawings, for better understanding and ease of description, the thicknesses of some layers and areas are exaggerated.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. Further, the word “over” or “on” means positioning on or below the object portion, and does not necessarily mean positioning on the upper side of the object portion based on a gravity direction.

It will be understood that, although the terms “first,” “second,” “third” etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, “a first element,” “component,” “region,” “layer” or “section” discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one,” unless the content clearly indicates otherwise. “At least one” is not to be construed as limiting “a” or “an.” “Or” means “and/or.” As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

Further, in the specification, the phrase “in a plan view” means when an object portion is viewed from above, and the phrase “in a cross-sectional view” means when a cross-section taken by vertically cutting an object portion is viewed from the side.

Hereinafter, an organic light emitting diode display including a clock wire according to an exemplary embodiment will be described in detail.

First,FIG.1illustrates an equivalent circuit diagram of one pixel of an organic light emitting diode display according to an exemplary embodiment.

Referring toFIG.1, a display device according to an exemplary embodiment includes a plurality of pixels, and one pixel includes a plurality of transistors T1, T2, and T3, a capacitor Cst, and at least one organic light emitting diode OLED connected to the plurality of transistors. Hereinafter, an example in which one pixel PX includes one organic light emitting diode OLED will be mainly described.

The transistors T1, T2, and T3include a first transistor T1, a second transistor T2, and a third transistor T3. A source electrode and a drain electrode, which will be described below, are used to distinguish two electrodes disposed on opposite sides of a channel of each of the transistors T1, T2, and T3, and they may be interchanged.

The gate electrode G1of the first transistor T1is connected to a first electrode C1of the capacitor Cst. A source electrode S1of the first transistor T1is connected to a driving voltage line for transferring a driving voltage ELVDD. A drain electrode D1of the first transistor T1is connected to an anode of the organic light emitting diode OLED and a second electrode C2of the capacitor Cst. The first transistor T1may receive a data voltage DATA depending on a switching operation of the second transistor T2, may store the data voltage DATA in the capacitor Cst, and may supply a driving current to the organic light emitting diode OLED depending on the stored voltage.

A gate electrode G2of the second transistor T2is connected to the first scan line that transfers a scan signal SC. A source electrode S2of the second transistor T2is connected to a data line capable of transferring the data voltage DATA or the reference voltage. A drain electrode D2of the second transistor T2is connected to the first electrode C1of the capacitor Cst and the gate electrode G1of the first transistor T1. The second transistor T2is turned on depending on the scan signal SC to transfer the reference voltage or data voltage DATA to the gate electrode G1of the first transistor T1and the first electrode C1of the capacitor Cst.

A gate electrode G3of the third transistor T3is connected to the sensing line transferring a sensing signal SS. A source electrode S3of the third transistor T3is connected to the second electrode C2of the capacitor Cst, the drain electrode D1of the first transistor T1, and the anode of the organic light emitting diode OLED. A drain electrode D3of the third transistor T3is connected to a sensing/initialization voltage line SI which transfers a sensing voltage SL or an initialization voltage INT. The third transistor T3is turned on in response to the sensing signal SS to transfer the initialization voltage INT to the anode of the organic light emitting diode OLED and the second electrode C2of the capacitor Cst, such that a voltage of the anode of the organic light emitting diode OLED may be initialized.

The first electrode C1of the capacitor Cst is connected to the gate electrode G1of the first transistor T1. The second electrode C2thereof is connected to the source electrode S3of the third transistor T3and the anode of the organic light emitting diode OLED. A cathode of the organic light emitting diode OLED is connected to the common voltage line which transfers the common voltage ELVSS.

The organic light emitting diode OLED may emit light depending on a driving current outputted from the first transistor T1.

The following describes an example of an operation of the circuit illustrated inFIG.1with reference toFIG.2, in particular an example of the operation during one frame.

FIG.2illustrates a timing chart of a signal applied to one pixel of a light emitting diode display according to an exemplary embodiment. Herein, a case in which the transistors T1, T2, and T3are N-type transistors will be described as an example, but the invention is not limited thereto.

When one frame is started, the scan signal SC of a high level and the sensing signal SS of a high level are supplied in an initialization period (“int” inFIG.2) so as to turn on the second transistor T2and the third transistor T3. The reference voltage from the data line is supplied to the gate electrode G1of the first transistor T1and the first electrode C1of the capacitor Cst through the turned-on second transistor T2. The initialization voltage INT is applied to the second electrode C2of the capacitor Cst, the drain electrode D1of the first transistor T1, and the anode of the organic light emitting diode OLED through the turned-on third transistor T3. Accordingly, the drain electrode D1of the first transistor T1and the anode of the organic light emitting diode OLED are initialized to the initialization voltage INT during the initialization period. In this case, a difference voltage between the reference voltage and the initialization voltage INT is stored in the capacitor Cst.

Next, when the scan signal SC is at the low level while the high-level sensing signal SS is maintained in the sensing period (“Sensing” inFIG.2), the third transistor T3is maintained to be turned on, and the second transistor T2is turned off. In this case, although the third transistor T3is turned on, the initialization voltage INT may no longer be applied in the sensing period, unlike the initialization period, and a threshold voltage of the first transistor T1may be prepared to be detected. In addition, since the second transistor T2is turned off, the voltage stored at the two electrodes of the capacitor Cst is maintained. As a result, the reference voltage from the data line is applied to the gate electrode G1of the first transistor T1, and the driving voltage ELVDD is applied to the source electrode S1, thereby outputting an output current to the drain electrode D1. The first transistor T1outputs a current from the source electrode S1to the drain electrode D1, and is turned off when the voltage of the drain electrode D1becomes a drain electrode's reference voltage (hereinafter “reference voltage-Vth”). This is because, when a voltage difference between the gate electrode G1and the drain electrode D1(hereinafter “voltage-Vgd”) becomes the threshold voltage of the first transistor T1, the channel near the drain electrode D1disappears. Therefore, the reference voltage-Vth becomes a voltage of the second electrode C2of the capacitor Cst, and the voltage difference between the two electrodes of the capacitor Cst becomes the threshold voltage of the first transistor T1. The sensing/initialization voltage line SI senses the voltage of the second electrode C2of the capacitor Cst, which is the reference voltage-Vth. Since the reference voltage from the data line is known, the threshold voltage of the first transistor T1may be checked. In this case, the common voltage ELVSS may have a high voltage to prevent a current from flowing through the organic light emitting diode OLED and preventing the organic light emitting diode OLED from emitting light. A characteristic deviation of the first transistor T1which may be different for each pixel may be externally compensated by generating a data signal that is compensated by reflecting characteristic information sensed for the sensing period.

Next, when the high-level scan signal SC and the high level sensing signal SS are supplied in the data input period (“Data” inFIG.2), the second transistor T2and the third transistor T3are turned on. The data voltage DATA from the data line is supplied to the gate electrode G1of the first transistor T1and the first electrode C1of the capacitor Cst through the turned-on second transistor T2. In this case, the initialization voltage INT is applied to the second electrode C2of the capacitor Cst, the drain electrode D1of the first transistor T1, and the anode of the organic light emitting diode OLED such that the applied data voltage DATA may be stored in the first electrode C1of the capacitor Cst consistently for each pixel.

Next, the first transistor T1, which is turned on by the data voltage DATA transferred to the gate electrode G1for a light emitting period, generates a driving current depending on the data voltage DATA, and the driving current may allow the organic light emitting diode OLED to emit light.

According to an exemplary embodiment, the high level scan signal SC and the high level sensing signal SS are supplied in the data input period, and thus the organic light emitting diode OLED should be turned on at the same timing. In this case, if the timing is different, a signal delay may occur, so an equivalent resistance design is required to simultaneously apply the scan signal and the sensing signal. Details of the equivalent resistance design will be described with reference toFIG.7toFIG.13.

Hereinafter, the gate driver of the organic light emitting diode display will be described before the equivalent resistance design is described.

FIG.3illustrates a plan view of an organic light emitting diode display including the pixel ofFIG.1according to an exemplary embodiment, andFIG.4schematically illustrates the gate driver ofFIG.3.

Referring toFIG.3, the organic light emitting diode display includes a substrate100, a gate driver200, a printed circuit board (“PCB”)300, a flexible printed circuit board (“FPCB”)310, and a data driver320.

The substrate100includes a display area DA and a non-display area NA. The display area DA is a portion for displaying an image thereon, and the display area DA includes a pixel PX including a thin film transistor, an organic light emitting diode OLED, and the like. The non-display area NA is a portion where an image is not displayed. The gate lines GL, portions of the data lines DL, the gate driver200, and the like for applying a voltage and a signal to the pixel PX in the display area DA are formed in the non-display area NA. A first side of the non-display area NA may be connected to the printed circuit board300by being bonded to the FPCB310. The data driver320mounted on the FPCB310applies a data signal to the data lines DL. Although not illustrated inFIG.3, the data lines DL for connecting to the pixel PX may extend in a first direction DR1, and the gate lines GL may extend in a second direction DR2.

The gate driver200serves to apply a gate signal to the gate lines GL, and is disposed along the first direction DR1at a first side of the non-display area NA.

The printed circuit board300disposed at a first side of the FPCB310may include a signal controller (not illustrated). The signal controller generates various signals for displaying an image in the display area DA, and transmits control signals to the gate driver200and the data driver320to control the gate driver200and the data driver320, respectively.

Referring toFIG.4, the gate driver200includes a clock wiring circuit210, a resistance adjusting circuit220, a gate driving circuit230, and a gate wiring circuit240. The gate driver200may be integrated in the non-display area NA.

The clock wiring circuit210includes a plurality of carry clock signal lines CLK_CR, a plurality of sensing clock signal line CLK_SS, a plurality of scan clock signal line CLK_SC, and a plurality of global clock signal line CLK_GB (Refers toFIG.6).

The resistance adjusting circuit220is disposed at a first side of the clock wiring circuit210, and is disposed along the first direction DR1. The resistance adjusting circuit220includes signal connection lines that are connected to signal lines such as a carry clock signal line CLK_CR, a sensing clock signal line CLK_SS, a scan clock signal line CLK_SC, and a global clock signal line CLK_GB. In addition, a signal deviation is reduced in the gate driving circuit230to be described later by disposing resistance wires having different resistivity, or having same resistivity but different lengths with respect to the sensing clock signal line CLK_SS and the scan clock signal line CLK_SC.

The gate driving circuit230is disposed at a first side of the resistance adjusting circuit220, and is disposed along the first direction DR1. The gate driving circuit230includes a plurality of stages SR for sequentially outputting gate signals. Each of the stages SR may be connected to several gate lines GL to output a gate signal to the pixel PX.

The gate wiring circuit240includes several gate lines GL connected to each stage SR of the gate driving circuit230. The gate lines GL apply a gate signal to each pixel PX by several stages SR. In another exemplary embodiment, the gate wiring circuit240may not be included in the gate driver200, but may be included in one configuration of the display area DA.

Hereinafter, the gate driver of the organic light emitting diode display according to an exemplary embodiment will be described in detail with reference toFIG.5.

FIG.5illustrates a block diagram of a gate driver according to an exemplary embodiment.

Referring toFIG.5, the gate driver200includes a shift register including first to mthstages SR1to SRm that are dependently connected to each other.

Each of the stages includes first and second carry clock terminals CR-CK1and CR-CK2, a first scan clock terminal SC-CK1, first to third global clock terminals S_CK1, S_CK2and S_CK3, a first input terminal IN1, a second input terminal IN2, a third input terminal IN3, a fourth input terminal IN4, and a first voltage input terminal V1, a second voltage input terminal V2, a third voltage input terminal V3, a first output terminal OUT1, a second output terminal OUT2, and a third output terminal CR.

The first and second carry clock terminals CR-CK1and CR-CK2receive a carry clock signal CLK_CR. For example, the first carry clock terminal CR-CK1of the first stage SR1receives a first carry clock signal CLK1_CR, and the second carry clock terminal CR-CK2receives a second carry clock signal CLK2_CR.

The first scan clock terminal SC-CK1receives a scan clock signal. For example, the first scan clock terminals SC-CK1of the first to fourth stages SR1, SR2, SR3, and SR4receive first to fourth scan clock signals CLK1_SC, CLK2_SC, CLK3_SC, and CLK4_SC, respectively.

The first sensing clock terminal SS-CK1receives a sensing clock signal. For example, the first sensing clock terminals SS-CK1of the first to fourth stages SR1, SR2, SR3, and SR4receive first to fourth sensing clock signals CLK1_SS, CLK2_SS, CLK3_SS, and CLK4_SS, respectively.

In this case, scan and sensing signals that are sequentially delayed in phase by a predetermined interval are applied as for the first to fourth scan clock signals CLK1_SC to CLK4_SC and the first to fourth sensing clock signals CLK1_SS to CLK4_SS. A delay problem of each scan and sensing signal applied to each stage may be solved through the resistance adjusting circuit. In an exemplary embodiment, since a structure of the resistance adjusting circuit220is illustrated inFIG.10andFIG.12, it will be described in detail below.

The first to third global clock terminals S_CK1, S_CK2, and S_CK3receive global clock signals S_CLK1to S_CLK3, respectively. The global clock signals of the present exemplary embodiment refer to a DC voltage (DC) signal applied to a gate driving circuit.

The first input terminal IN1receives a sensing start signal SSP, the second input terminal IN2and the third input terminal IN3receive global signals SEN_ON and DIS_ON, and the fourth input terminal IN4receives a sensing signal applied from the third output terminal CR of the next stage (e.g., if a current stage is SR1, the next stage is SR2).

The first voltage input terminal V1receives a high level voltage VGH, the second voltage input terminal V2receives a first low level voltage VGL1, and the third voltage input terminal V3receives a second low level voltage VGL2.

The first output terminal OUT1outputs a scan signal SC to a gate-embedded circuit, and the second output terminal OUT2outputs a sensing signal SC to a gate-embedded circuit.

The third output terminal CR applies a sensing start signal to the first input terminal INT1of the next.

Hereinafter, a detailed description will be given of a resistance adjusting circuit220in which an equivalent resistance design of a gate driver200is implemented.

FIG.6illustrates a connection relationship between a clock wiring circuit and a gate driving circuit in a gate driver according to an exemplary embodiment.

Referring toFIG.6, the clock wiring circuit210of the gate driver200includes a plurality of carry clock signal lines CLK_CR, sensing clock signal lines CLK_SS, scan clock signal lines CLK_SC, and global clock signal lines CLK_GB. In this exemplary embodiment, each of the signal lines includes six signal lines extending in the first direction DR1. InFIG.6, six signal lines of first to sixth carry clock signal lines CLK_CR1to CLK_CR6, first to sixth sensing clock signal lines CLK_SS1to CLK_SS6, first to sixth scan clock signal lines CLK_SC1to CLK_SC6, and first to sixth global clock signal lines CLK_GB1to CLK_GB6are illustrated as1,2,3,4,5, and6under the characters CLK_CR, CLK_SC, and CLK_GB, respectively, for convenience of illustration. In this exemplary embodiment, six sensing clock signal lines CLK_SS1, SS2, SS3, SS4, SS5, and SS6are disposed at a right side of the six carry clock signal lines CLK_CR1, CR2, CR3, CR4, CR5, and CR6, six scan clock signal lines CLK_SC1, SC2, SC3, SC4, SC5, and SC6are disposed at a right side of the sensing clock signal line CLK_SS, and six global clock signal lines CLK_GB1, GB2, GB3, GB4, GB5, and GB6are disposed at a right side of the scan clock signal lines CLK_SC. According to an exemplary embodiment, positions of the carry clock signal lines CLK_CR, the sensing clock signal lines CLK_SS, the scan clock signal lines CLK_SC, and the global clock signal lines CLK_GB may be changed, and the number of each signal line may be variously implemented.

Each of the first to sixth carry clock signal lines CLK_CR1, CR2, CR3, CR4, CR5, and CR6extends in the first direction DR1at a predetermined distance apart. The first carry clock signal line CLK_CR1is electrically connected to a first carry clock signal connection line211extending in the second direction DR2, and each of the second to sixth carry clock signal lines CLK_CR2, CR3, CR4, CR5, and CR6are also electrically connected to a corresponding carry clock signal connection line extending in the second direction DR2. The first carry signal connection line211is connected to the first stage SR1to transfer a first carry signal from the first carry clock signal line CLK_CR1to the first stage SR1. The other carry signal connection lines are connected to one corresponding stage SR to transfer carry signals from one carry clock signal line CLK_CR.

Each of the first to sixth sensing clock signal lines CLK_SS1, SS2, SS3, SS4, SS5, and SS6extends in the first direction DR1at a predetermined distance apart. The first sensing clock signal line CLK_SS1is electrically connected to a first sensing signal connection line212extending in the second direction DR2to transfer the first sensing signal to the first stage SR1. Each of the other sensing clock signal lines is also electrically connected to one corresponding sensing signal connection line extending in the second direction DR2to transmit a sensing signal to each corresponding stage SR. Herein, the first sensing clock signal line CLK_SS1may be referred to as a first signal line, and the first sensing signal connection line212may be referred to as a first signal connection line.

Each of the first to sixth scan clock signal lines CLK_SC1, SC2, SC3, SC4, SC5, and SC6extends in the first direction DR1at a predetermined distance apart. The first scan clock signal line CLK_SC1is electrically connected to a first scan signal connection line213extending in the second direction DR2to transfer the first scan signal to the first stage SR1. Each of the other scan clock signal lines is also electrically connected to one corresponding scan signal connection line extending in the second direction DR2to transmit a scan signal to each corresponding stage SR. Herein, the first scan clock signal line CLK_SC1may be referred to as a second signal line, and the first scan signal connection line213may be referred to as a second signal connection line.

Each of the first to sixth global clock signal lines CLK_GB1, GB2, GB3, GB4, GB5, and GB6extends in the first direction DR1at a predetermined distance apart. The first to sixth global clock signal lines CLK_GB1, GB2, GB3, GB4, GB5, and GB6are electrically connected to first to six global signal connection lines214extending in the second direction DR2, respectively, to transfer the first to sixth global signals to the first stage SR1. Corresponding connections to global clock signal lines CLK_GB are provided to the other stages SR2, SR3, . . . , and SR6.

Each of the stages SR1, SR2, SR3, SR4, SR5, and SR6is connected to a corresponding carry clock signal line CLK_CR, a corresponding sensing clock signal line CLK_SS, a corresponding scan clock signal line CLK_SC, and six global clock signal lines CLK_GB1, GB2, GB3, GB4, GB5, and GB6. For example, nine clock signals may be applied to one stage. The signal connection lines that are connected to each stage SR by being connected to the carry clock signal line CLK_CR, the sensing clock signal line CLK_SS, the scan clock signal line CLK_SC, and six global clock signal lines CLK_GB1, GB2, GB3, GB4, GB5, and GB6may be disposed over the clock wiring circuit210and the resistance adjusting circuit220. Herein, each of the connection lines may include all the horizontal lines disposed over the clock wiring circuit210and the resistance adjusting circuit220.

Since one sensing clock signal line CLK_SS and one scan clock signal line CLK_SC connected to one stage SR have different distances from the gate driving circuit230, lengths of the connection lines extending in the second direction DR2are different, and thus a resistance difference and an RC delay therefrom, that is, a signal delay, may occur. That is, a signal delay may occur due to the difference in length between the corresponding sensing signal connection line and the corresponding scan signal connection line. In general, the connection line connected to the clock signal circuit210disposed closer to the gate driving circuit230is longer than the connection line connected to the clock wiring circuit210disposed far from the gate driving circuit230in order to solve the signal delay by making the lengths of the two connection lines being the same. For example, the first scan signal connection line213of the scan clock signal line CLK_SC disposed close to the gate driving circuit230should be longer than the first sensing signal connection line212of the sensing clock signal line CLK-SS. In this case, a connection line including a winding concave-convex portion may be disposed in the resistance adjusting circuit220in order to increase a length of the first scan signal connection line213. However, in a high resolution organic light emitting diode display, since it is necessary to include a plurality of elements in a limited area, there is a need for designing the resistance adjusting circuit220efficiently in a constant area without forming a long length of the connection line. That is, referring back toFIG.4, it is necessary to design the resistance adjusting circuit220while a distance DS between a first end of the resistance adjusting circuit220and a first end of the gate driving circuit230as shown inFIG.4is constantly maintained.

Accordingly, in this exemplary embodiment, the resistance adjusting circuit220includes resistance wires having different resistivity, thereby maintaining the distance DS from the first end of the resistance adjusting circuit220to the first end of the gate driving circuit230and adjusting the resistance thereof.

Hereinafter, a resistance adjusting circuit220connected to a first stage and a second stage will be described with reference toFIG.7toFIG.9.

FIG.7illustrates a plan view of a partial region in a case where a resistance adjusting circuit220includes wires having different resistivity according to an exemplary embodiment,FIG.8illustrates a cross-sectional view taken along line VIII-VIII′ ofFIG.7, andFIG.9illustrates a cross-sectional view taken along line VIV-VIV′ ofFIG.7.

The resistance adjusting circuit220of the organic light emitting diode display according to an exemplary embodiment may include lower resistance lines222,223,221,224,225,226,227,228, and229, a first insulating layer11, a second insulating layer12, and upper resistance lines251,253,255,257, and259, an interlayer insulating layer13, and data upper resistance lines252,271,254,256,258,270,272,273, and274, which are disposed on the substrate100. The upper resistance lines251,253,255,257, and259and the data upper resistance lines252,271,254,256,258,270,272,273, and274may be referred to as upper resistance lines, in an exemplary embodiment.

The substrate100may be made of a glass substrate or a flexible substrate including plastic and polyimide (“PI”). A barrier film made of an inorganic material may be disposed on the flexible substrate100.

The lower resistance lines222,223,221,224,225,226,227,228, and229are disposed on the substrate100. The lower resistance lines222,223,221,224,225,226,227,228, and229may include a first lower resistance line222, a second lower resistance line223, a first carry signal resistance line221, and first to sixth global signal resistance lines224,225,226,227,228, and229. Herein, the first lower resistance line222, the second lower resistance line223, the first carry signal resistance line221, and the first to sixth global signal resistance lines224,225,226,227,228, and229show the connection lines connected to one stage. One first lower resistance line222, one second lower resistance line223, one first carry signal resistance line221, and first to sixth global signal resistance lines224,225,226,227,228, and229may be connected to the same stage. The lower resistance lines222,223,221,224,225,226,227,228, and229may be formed of or include a metal having resistivity of about 0.066 Ohms (Ω), for example. The lower resistance lines222,223,221,224,225,226,227,228, and229may be disposed in the same layer as the first carry signal connection line211, the first scan signal connection line213, the first sensing signal connection line212, and the first to sixth global signal connection lines214. The lower resistance lines222,223,221,224,225,226,227,228, and229may be a part of the first carry signal connection line211, the first scan signal connection line213, the first sensing signal connection line212, and the first to sixth global signal connection lines214, which are extended in the second direction DR2in the clock wiring circuit210.

The resistance adjusting circuit220of the first sensing signal connection line212includes a first lower resistance line222and a first upper resistance line252. The first lower resistance line222is a resistance line extending in the second direction DR2from the resistance adjusting circuit220. The first lower resistance line222is electrically connected to the first upper resistance line252, which will be described later, to transfer a first sensing signal. The first lower resistance line222includes a winding concave-convex portion.

The resistance adjusting circuit220of the first scan signal connection line213includes a second lower resistance line223and a second upper resistance line253. The second lower resistance line223is a resistance line extending in the second direction DR2from the resistance adjusting circuit220. The second lower resistance line223is electrically connected to the second upper resistance line253, which will be described later, to transfer a first scan signal. The second lower resistance line223includes a winding concave-convex portion, and the winding concave-convex portion of the second lower resistance line223is longer than the first lower resistance line222. In another exemplary embodiment, heights of the concave-convex portions of the first lower resistance line222and the second lower resistance line222itself may be higher than those shown inFIG.7in regions not overlapping other wires in a plan view. Accordingly, the resistance lines may be efficiently disposed in a fixed area.

Herein, the lengths of the first lower resistance line222and the second lower resistance line223may vary depending on delays of the first sensing signal and the first scan signal. In the exemplary embodiment shown inFIG.6, the sensing clock signal line CLK_SS is disposed farther to the gate driving circuit230than the scan clock signal line CLK_SC, and a number of other signal lines extending in the first direction DR1that the first sensing signal connection line212overlaps (i.e., intersects) is greater than a number of other signal lines that the first scan signal connection line213overlaps in a plan view. Thus, since the first scan signal has a lesser signal delay than the first sensing signal, the first lower resistance line222having large resistivity may be shorter than the second lower resistance line223, thereby reducing a deviation between the delay of the first sensing signal and the delay of the first scan signal. According to another exemplary embodiment, in the cases that the first sensing clock signal line CLK-SS1is disposed to be closer to the gate driving circuit230than the first scan clock signal line CLK_SC1, the number of other signal lines extending in the first direction DR1that the first scan signal connection line213overlaps (i.e., intersects) may be greater than the number of other signal lines that the first sensing signal connection line212overlaps. Thus, since the first sensing signal has a lesser signal delay than the first scan signal, the first lower resistance line222having large resistivity may be longer than the second lower resistance line223, thereby reducing a deviation between the delay of the first sensing signal and the delay of the first scan signal.

The resistance adjusting circuit220of the first carry signal connection line211includes a first carry signal resistance line221and a first gate upper resistance line251. The first carry signal resistance line221is a resistance line extending in the second direction DR2from the resistance adjusting circuit220. The first carry signal resistance line221is electrically connected to a first gate upper resistance line251, which will be described later, to transfer a first carry signal.

The resistance adjusting circuit220of the first to sixth global signal connection lines214may include first to sixth global signal resistance lines224,225,226,227,228, and229, second to fourth gate upper resistance lines255,257, and259, first to third data upper resistance lines254,256, and268, and second to fourth gate connections272,273and274. The first to sixth global signal resistance lines224,225,226,227,228, and229are six resistance wires extending from the resistance adjusting circuit220in the second direction DR2. The first global signal resistance line224is electrically connected to a first data upper resistance line254to be described later to transfer a first global signal, and the second global signal resistance line225is electrically connected to a second gate upper resistance line255which will be described later, to transmit a second global signal. The third global signal resistance line226is electrically connected to the second data upper resistance line256, which will be described later, to transfer a third global signal. The fourth global signal resistance line227is electrically connected to a third gate upper resistance line257to be described later to transfer a fourth global signal, and the fifth global signal resistance line228is electrically connected to a third data upper resistance line258to be described later to transfer a fifth global signal. The sixth global signal resistance line229is electrically connected to a fourth gate upper resistance line259to be described later to transfer a sixth global signal. In addition, the sixth global signal resistance line229and the fourth gate upper resistance line259are connected to both the first stage SR1and the second stage SR2, to commonly transfer a sixth global signal to the first stage SR1and the second stage SR2.

The first insulating layer11and the second insulating layer12are disposed on the lower resistance lines222,223,221,224,225,226,227,228, and229, and may be made of a silicon oxide (SiO2) or a silicon nitride (SiNx) including an inorganic material. The first insulating layer11and the second insulating layer12may be collectively referred to as an insulating layer.

Upper resistance lines251,253,255,257, and259are disposed on the second insulating layer12(SeeFIG.9). The upper resistance lines251,253,255,257, and259include a second upper resistance line253and first to fourth gate upper resistance lines251,255,257, and259. Herein, the second upper resistance line253and the first to fourth gate upper resistance lines251,255,257, and259represent resistance lines connected to one stage. One second upper resistance line253and first to fourth gate upper resistance lines251,255,257, and259may be connected to one of the plurality of stages. The upper resistance lines may be made of a metal having a resistivity of about 0.033Ω, for example.

The second upper resistance line253is a portion of the resistance line to which the first scan signal is transferred. The second upper resistance line253extends from a first end of the second lower resistance line223in the second direction DR2, and includes a curved line portion in a plan view. Specifically, referring toFIG.7, a first end of the second upper resistance line253and the first end of the second lower resistance line223may not overlap each other. The second upper resistance line253may be electrically connected to the second lower resistance line223by a resistance line connector271which will be described later. The second upper resistance line253having resistivity that is smaller than that of the second lower resistance line223may have a short length corresponding to a length of the second lower resistance line223formed to be long. Accordingly, an area of the resistance adjusting circuit220may be constantly maintained. In addition, the second upper resistance line253may be formed of a wire including a concave-convex portion having a wide width depending on the disposal of the first upper resistance line252formed at an upper side in a plan view. Accordingly, an area of the resistance wiring may be efficiently utilized without increasing the area in the resistance adjusting circuit220.

The first gate upper resistance line251is a portion of the resistance line to which the first carry signal is transferred. The first gate upper resistance line251extends from a first end of the first carry signal resistance line221in the second direction DR2, and includes a curved line portion in a plan view. A first end of the first carry signal resistance line221and the first end of the first gate upper resistance line251may not overlap each other. Herein, the first gate upper resistance line251may be electrically connected to the first carry signal resistance line221by a first gate connector270which will be described later.

The second gate upper resistance line255is a portion of the resistance line to which the second global signal is transferred. The second gate upper resistance line255extends from a first end of the second global signal resistance line225in the second direction DR2, and includes a curved line portion in a plan view. A first end of the second gate upper resistance line255and a first end of the second global signal resistance line225may not overlap each other. The second gate upper resistance line255is electrically connected to the second global signal resistance line225by a second gate connector272.

The third gate upper resistance line257is a portion of the resistance line to which the fourth global signal is transferred. The third gate upper resistance line257extends from a first end of the fourth global signal resistance line227in the second direction DR2, and includes a curved line portion in a plan view. The third gate upper resistance line257is electrically connected to the fourth global signal resistance line227by a third gate connector273.

The fourth gate upper resistance line259is a portion of the resistance line to which the sixth global signal is transferred. The fourth gate upper resistance line259is electrically connected to the sixth global signal resistance line229by a fourth gate connector274. The sixth global signal resistance line229and the fourth gate upper resistance line259are connected to both the first stage SR1and the second stage SR2, to commonly transfer a sixth global signal to the first stage SR1and the second stage SR2.

The interlayer insulating layer13is disposed on the upper resistance lines251,253,255,257, and259(Refer toFIG.9), and may be made of an organic material or an inorganic material.

The data upper resistance lines252,271,254,256,258,270,272,273, and274are disposed on the interlayer insulating layer13. The data upper resistance lines252,271,254,256,258,270,272,273, and274may include a first upper resistance line252, a resistance line connector271, first to third data upper resistance lines254,256, and258, and first to fourth gate connections270,272,273, and274. Herein, the first upper resistance line252, the resistance line connector271, the first to third data upper resistance lines254,256, and258, and the first to fourth gate connectors270,272,273, and274represent resistance lines connected to one stage. The first upper resistance line252, the resistance line connector271, the first to third data upper resistance lines254,256, and258, and the first to fourth gate connectors270and272,273, and274may be connected to one stage SR of the plurality of stages SR. The data upper resistance lines may be formed of or include a metal having a resistivity of about 0.033Ω, for example.

The first upper resistance line252is a resistance line extending in the second direction DR2. The first upper resistance line252is partially overlapped with the first lower resistance line222. Specifically, referring toFIG.8, the first upper resistance line252is electrically connected to the first lower resistance line222through an opening61defined in the first insulating layer11, the second insulating layer12, and the interlayer insulating layer13to transfer the first sensing signal. The first upper resistance line252includes a partially curved line portion in a plan view, and may have a long length corresponding to a short length of the first lower resistance line222. Accordingly, an area of the resistance adjusting circuit220may be constantly maintained.

The resistance line connector271is disposed to extend in the second direction DR2, and partially overlaps the second lower resistance line223and the second upper resistance line253in a plan view. Specifically, referring toFIG.8, the resistance line connector271and the second lower resistance line223are electrically connected to each other through an opening62defined in the first insulating layer11, the second insulating layer12, and the interlayer insulating layer13in a portion where the resistance line connector271and the second lower resistance line223overlap each other in a plan view. The resistance line connector271and the second upper resistance line253are electrically connected to each other through an opening63defined in the first insulating layer11, the second insulating layer12, and the interlayer insulating layer13in a portion where the resistance line connector271and the second upper resistance line253overlap each other in a plan view. That is, the first scan signal transferred to the second lower resistance line223may be connected to the second upper resistance line253through the resistance line connector271.

The first to third data upper resistance lines254,256, and258extend in the second direction DR2, and are part of the resistance line through which the first, third, and fifth global signals are transferred. The first to third data upper resistance lines254,256, and258include a partially curved line portion in a plan view. The first to third data upper resistance lines254,256, and258overlap with portions of the first global signal resistance line224, the third global signal resistance line226, and the fifth global signal resistance line228. Portions where the first to third data upper resistance lines254,256, and258and the first, third, and fifth global signal resistance lines224,226, and228overlap each other respectively may be electrically connected to each other through opening64,65, and66defined in the first insulating layer11, the second insulating layer12, and the interlayer insulating layer13, respectively (ReferFIG.7).

The first gate connector270is disposed to extend in the second direction DR2, and is a connector that transfers a first carry signal. The first gate connector270partially overlaps the first carry signal resistance line221and the first gate upper resistance line251in a plan view. The first carry signal resistance line221may be electrically connected to the first gate connection part270through an opening67defined in the first insulating layer11, the second insulating layer12, and the interlayer insulating layer13, and may be electrically connected to the first gate upper resistance line251through an opening68defined in the interlayer insulating layer13.

The second to fourth gate connectors272,273, and274are disposed to extend in the second direction DR2, and are connectors that transfer second, fourth, and sixth global signals. The second to fourth gate connections272,273, and274partially overlap the second, fourth, and sixth global signal resistance lines225,227, and229, respectively, and are electrically connected to each other through openings69,71, and73, respectively, defined in the first insulating layer11, the second insulating layer12, and the interlayer insulating layer13. In addition, the second to fourth gate connectors272,273, and274are partially overlapped with the second to fourth gate upper resistance lines255,257, and259, respectively, and are electrically connected to each other through openings70,72, and74, respectively, defined in the interlayer insulating layer13.

Although not illustrated inFIG.8andFIG.9, according to an exemplary embodiment, the first upper resistance line252may be formed at the same layer as the gate connector to be electrically connected to the first lower resistance line252through an opening defined in the second insulating layer12. The second upper resistance line253may be directly electrically connected to the second lower resistance line223without the resistance line connector271.

Referring toFIG.7again, one first gate upper resistance line251, the first upper resistance line252, the second upper resistance line253, the second to fourth gate upper resistance255,257, and259, and the first to third data upper resistance254,256, and258which are connected to the first stage SR1may be connected to the second stage SR2. In addition, the first gate upper resistance line251, the first upper resistance line252, the second upper resistance line253, the second to fourth gate upper resistance lines255,257, and259, and the first to third data upper resistance lines254,256, and258may be disposed to be connected symmetrically with respect to the second stage SR2about the fourth data upper resistance line254.

Although not illustrated inFIG.7, the carry clock signal line CLK_CR, the sensing clock signal line CLK_SS, the scan clock signal line CLK_SC, and the global clock signal line CLK_GB extending in the second direction DR2may be disposed in the same layer as the data upper resistance lines252,271,254,256,258,270,272,273, and274.

Hereinafter, a state of the resistance adjusting circuit connected to first to sixth stages will be described with reference toFIG.10. Referring again toFIG.7, the gate driving circuit230disposed at a right side of the resistance adjusting circuit220includes first to sixth stages SR1, SR2, SR3, SR4, SR5, and SR6. The first gate upper resistance line251, the first upper resistance line252, the second upper resistance line253, the second to fourth gate upper resistance lines255,257, and259, and the first to third data upper resistance lines254,256, and258are directly connected to one stage SR. The first gate upper resistance line251, the first upper resistance line252, the second upper resistance line253, the second to fourth gate upper resistance lines255,257, and259, and the first to third data upper resistance lines254,256, and258are connected to the first stage SR1, the third stage SR3, and the fifth stage SR5, that is, the odd-numbered stages. On the other hand, the resistance lines connected to the odd-numbered stages are symmetrically connected to the second stage SR2, the fourth stage SR4, and the sixth stage SR6, that is, the even-numbered stages, such that a bottom resistance line connected to the odd-numbered stages is connected at the top to the even-numbered stages in that order of the resistance lines. Herein, a third data upper resistance line258may be connected to the odd stage SR and the even stage SR together.

When the gate driving circuit230according to an exemplary embodiment sequentially outputs a gate signal from the sixth stage SR6to the first stage SR1and from the bottom stage to the top stage, a delay of the clock signal may occur going from the bottom stage to the top stage. The first lower resistance line222and the second lower resistance line223connected to the sixth stage SR6are longest compared with the first and second lower resistance lines222and223connected to the first to fifth stages SR1, SR2, SR3, SR4, and SR5in order to prevent such a signal delay. On the other hand, since the lengths of the first and second upper resistance lines252and253connected to the sixth stage SR6are short, an output signal delayed in the first stage SR1may be adjusted. That is, the first and second lower resistance lines222and223connected to the first stage SR1are the shortest compared with the first and second lower resistance lines222and223connected to the second to sixth stages SR2, SR3, SR4, SR5, and SR6. Accordingly, the first and second upper resistance lines252and253connected to the first stage SR1may be longer than those connected to the second to sixth stages SR2, SR3, SR4, SR5, and SR6, thereby constantly maintaining overall resistance of the resistance adjusting circuit220.

Positions of openings along lengths of the first lower resistance line222, the first upper resistance line252, the second lower resistance line223, and the second upper resistance line253will now be described. As the stage number increases from the first stage SR1to the sixth stage SR6, the position of the opening in which the first lower resistance line222and the first upper resistance line252are connected gradually moves to the right (indicated by circles inFIG.10). In addition, as the stage number increases from the first stage SR1to the sixth stage SR6, the position of the opening in which the second lower resistance line223and the second upper resistance line253are connected also gradually moves to the right (indicated by triangles inFIG.10).

Therefore, it is possible to design appropriate resistance by adjusting lengths of the first and second upper resistance lines252and253and the first and second lower resistance lines222and223having different resistivity without changing the area of the resistance adjusting circuit.

Although not illustrated inFIG.10, according to an exemplary embodiment, when gate signals are sequentially outputted from the bottom stage to the top stage among the plurality of stages, the first carry signal resistance line221connected to the first stage SR1is shortest compared with the first carry signal resistance line221connected to the second to sixth stages SR2, SR3, SR4, SR5, and SR6. Each carry signal resistance line connected to the second to sixth stages SR2, SR3, SR4, SR5, and SR6may be gradually longer, thereby constantly maintaining overall resistance of the resistance adjusting circuit220and preventing the carry clock signal applied to the stages from being delayed.

Hereinafter, a state in which wires having constant resistivity are included in a resistance adjusting circuit according to another exemplary embodiment will be described with reference toFIG.11andFIG.12.

FIG.11illustrates a plan view of a partial region in a case where a resistance adjusting circuit includes wires having the same resistance according to another exemplary embodiment, andFIG.12illustrates a plan view of a partial region in a case where a resistance adjusting circuit includes wires having the same resistance according to another exemplary embodiment.

FIG.11is similar to the resistance adjusting circuit according to the exemplary embodiment shown inFIG.7, and therefore, the following description will focus on differences.

Referring toFIG.11, the resistance adjusting circuit220of the organic light emitting diode display according to another exemplary embodiment may include lower resistance lines222,223,221,224,225,226,227,228, and229, the first insulating layer11, the second insulating layer12, and the upper resistance lines251,255,257, and259, the interlayer insulating layer13, and data upper resistance lines254,256,258,270,272,273, and274which are disposed on the substrate100.

The resistance adjusting circuit220of the first sensing signal connection line212includes a first lower resistance line222. The first lower resistance line222is a resistance line extending in the second direction DR2from the resistance adjusting circuit220to transfer a first sensing signal. The first lower resistance line222includes a winding concave-convex portion. Herein, the first lower resistance line is referred to as a first resistance line.

The resistance adjusting circuit220of the first scan signal connection line213includes a second lower resistance line223. The second lower resistance line223is a resistance line extending in the second direction DR2from the resistance adjusting circuit220to transfer a first scan signal. The second lower resistance line223includes a winding concave-convex portion, and the winding concave-convex portion is longer than the first lower resistance line222. Herein, the second lower resistance line is referred to as a second resistance line.

According to an exemplary embodiment, the first lower resistance line222and the second lower resistance line223may be disposed between the first insulating layer11and the second insulating layer12, and may be disposed on the second insulating layer12or the interlayer insulating layer13. That is, the first lower resistance line222and the second lower resistance line223positioned in the resistance adjusting circuit220may be implemented by wires having the same resistivity, thereby reducing delay deviations of delays of the first sensing signal and the scan signal depending on a length of the concave-convex portion.

In addition, heights of the concave-convex portions of the first lower resistance line222and the second lower resistance line222may be higher than those shown inFIG.11in regions not overlapping other wires in a plan view. Accordingly, the resistance lines may be efficiently disposed in a fixed area.

FIG.12is similar to the resistance adjusting circuit according to the exemplary embodiment shown inFIG.10, and therefore, the following description will focus on differences.

When the gate driving circuit230according to an exemplary embodiment sequentially outputs a gate signal from the sixth stage SR6to the first stage SR1and from the bottom stage to the top stage, a delay of the clock signal may occur going from the bottom stage to the top stage. The first lower resistance line222and the second lower resistance line223connected to the sixth stage SR6are longest compared with the first and second lower resistance lines222and223connected to the first to fifth stages SR1, SR2, SR3, SR4, and SR5in order to prevent such a signal delay.

A position of a first end of the concave-convex portion included in the first lower resistance line222and the second lower resistance line223will now be described. When connected to one from the first stage SR1to the sixth stage SR6, the position of first end of the concave-convex portion of the first lower resistance line222gradually moves to the right (indicated by circles inFIG.12). In addition, when connected to one from the first stage SR1to the sixth stage SR6, the position of first end of the concave-convex portion of the second lower resistance line223also gradually moves to the right (indicated by triangles inFIG.12).

According to an exemplary embodiment, the first lower resistance line222and the second lower resistance line223may be disposed between the first insulating layer11and the second insulating layer12, and may be disposed on the second insulating layer12or the interlayer insulating layer13. That is, the first lower resistance line222and the second lower resistance line223positioned in the resistance adjusting circuit220may be implemented by wires having the same resistivity, thereby reducing delays of the sensing signal and the scan signal depending on a length of the concave-convex portion.

In addition, heights of the concave-convex portions of the first lower resistance line222and the second lower resistance line222may be higher than those shown inFIG.12in regions not overlapping other wires in a plan view. Accordingly, the resistance lines may be efficiently disposed in a fixed area.

Hereinafter, a cross-sectional view of a display area of an organic light emitting diode display according to an exemplary embodiment will be described with reference toFIG.13.

Referring toFIG.13, an organic light emitting diode display according to an exemplary embodiment includes a lower metal layer111, a first insulating layer11, a semiconductor layer120, a second insulating layer12, a gate electrode150, an interlayer insulating layer13, a source electrode161, a drain electrode162, a planarization layer14, and an organic light emitting diode OLED which are sequentially stacked on a substrate100.

The substrate100may be a flexible substrate100including plastic and polyimide (PI). A barrier layer made of an inorganic material may be disposed on the substrate100.

The lower metal layer111is disposed on the substrate100. The lower metal layer111, which is a metal layer disposed in the display area DA including the pixel PX, may be disposed in the same layer as lower resistance lines222,223,221,224,225,226,227,228, and229illustrated inFIG.6toFIG.10, disposed in the non-display area NA, a carry signal connection line, a scan signal connection line, a sensing signal connection line, and a plurality of global signal connection lines.

The first insulating layer11is disposed on the lower metal layer111, and may be made of an inorganic material.

The semiconductor layer120is disposed on the first insulating layer11and may include polycrystalline silicon, an oxide semiconductor material, and amorphous silicon. The semiconductor layer120includes a source region, a drain region, and a channel region, wherein the source region and the drain region are doped with impurities, and the channel region is not doped with impurities.

The second insulating layer12is disposed on the semiconductor layer120, and may be made of an inorganic material.

The gate electrode150may be disposed on the second insulating layer12. The gate electrode150may be disposed to overlap a channel region of the semiconductor layer120.

The interlayer insulating layer13is disposed on the gate electrode150, and may be made of an organic material or an inorganic material.

The source electrode161and the drain electrode162are disposed on the interlayer insulating layer13, and may be electrically connected to the source region and the drain region of the semiconductor layer120. In this case, the source electrode161and the drain electrode162connected to the semiconductor layer120may form one thin film transistor together with the gate electrode150. The source electrode161and the drain electrode162may be disposed in the same layer as a carry clock signal line CLK_CR, a sensing clock signal line CLK_SS, a scan clock signal line CLK_SC, and a global clock signal line CLK_GB extending in the second direction DR2.

The planarization layer14is disposed on the source electrode161and the drain electrode162, and may be formed of or included an organic material.

The anode electrode191is disposed on the planarization layer14. The anode electrode191may be formed of or include a transparent conductive material or a reflective metal. The anode electrode191may be electrically connected to the drain electrode162through an opening defined in the planarization layer14to serve as a pixel electrode of the organic light emitting diode OLED.

A partition wall350covers the anode electrode191and the planarization layer14, and may be formed of or include an organic material.

An organic emission layer370is disposed in an open portion of the partition wall350. The organic emission member370may include at least one of an emission layer, a hole injection layer (HIL), a hole transporting layer (HTL), an electron transporting layer (ETL), and an electron injection layer (EIL).

The cathode electrode27is disposed on the partition wall350and the organic light emitting layer370. A cathode electrode27may be formed of or include a transparent conductive material or a reflective metal. The cathode electrode27may serve as a common electrode of the organic light emitting diode OLED. An anode electrode191, the organic emission layer370, and the cathode electrode27form an organic light emitting diode OLED.

While this invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

DESCRIPTION OF SYMBOLS

100: substrate200: gate driver300: printed circuit board (PCB)310: FPBC320: data driver210: clock wiring circuit220: resistance adjusting circuit230: gate driving circuit240: gate wiring circuitSR1, SR2, SR3, SR4, SR5, SR6: first, second, third, fourth, fifth, and sixth stage212: first sensing signal connection line213: first scan signal connection line211: first carry signal connection line214: first to sixth global signal connection lines222: first lower resistance line223: second lower resistance line252: first upper resistance line253: second upper resistance line271: resistance line connector