Patent ID: 12249633

PREFERRED EMBODIMENT OF THE PRESENT INVENTION

Hereinafter, an embodiment according to the disclosure is described with reference to the drawings. It should be noted that the disclosure is not limited to the embodiment described herein.

[Configuration of Shield Gate Trench Type FET]

FIG.1is a diagram schematically showing a structure of a field-effect transistor (shield gate trench type FET (n channel)) according to the embodiment.

In a semiconductor substrate10, a trench12having a vertical hole shape is formed inward from the surface thereof. In the embodiment, the semiconductor substrate10is a silicon (Si) substrate.

A drain region14which is an n+ region is formed on the back surface side of the semiconductor substrate10, and an n region16is formed above the drain region14. In this example, a lower part of the trench12extends from the surface side into the n region16. Alternatively, the lower part of the trench12may reach a boundary between the n region16and an n+ region20.

A p region18is formed above the n region16on the outer side of the trench12, and a source region20which is the n+ region is formed above the p region18. An upper part of the trench12is located closer to the inner side than the p region18and the source region20.

In addition, in this example, on the lateral side of the source region20(the side far away from the trench12), a conductive portion22having conductivity is formed which extends parallel to the trench12toward the inner side of the semiconductor substrate10and terminates in the p region18. A p+ region24in which the lateral side and bottom are surrounded by the p region18is formed between the lower end of the conductive portion22and the p region18, and the p region18is connected to the source (ground) by the p+ region24. Alternatively, the conductive portion22may reach a boundary between the p region18and the n region16, the p+ region24may be not surrounded by the p region18, and a lower part of the p+ region24may be the n region16.

The inside of the trench12is filled with an oxide insulating layer30that is formed from insulating SiO2, and the oxide insulating layer30reaches a position above the trench12and spreads with a predetermined thickness from there to a position above the source region20. Regarding the oxide insulating layer30, the oxide insulating layer30surrounding a gate region32is referred to as an oxide insulating layer30a, and the oxide insulating layer30above the gate region32is referred to as an oxide insulating layer30d.

The gate region32is disposed inside the oxide insulating layer30at the upper part inside the trench12, and a shield gate region34is disposed inside the oxide insulating layer30at the lower part of the trench12below the gate region32. The gate region32and the shield gate region34are formed by conductive polysilicon.

The oxide insulating layer30surrounding the gate region32and the shield gate region34is formed by, for example, thermal silicon oxide or silicon oxide of chemical vaper deposition (CVD).

Here, in the embodiment, on the outer side of the shield gate region34(on the lateral sides of the shield gate region34and below the shield gate region34) inside the trench12, there is an ONO structure in which a nitride insulating layer40having an insulation property is disposed inside the oxide insulating layer30. That is, there is a structure in which an oxide insulating layer (SiO2)30b, the nitride insulating layer (SiN)40, and an oxide insulating layer (SiO2)30care positioned in this order from the outer side. Moreover, by adopting the ONO structure, there is no need to separately form a nitride insulating layer for preventing thermal oxidation, and the manufacturing process can be simplified.

In addition, an oxide insulating layer30ewhich is relatively thick is disposed between the shield gate region34and the gate region32. Because the oxide insulating layer30eis located between the shield gate region34and the gate region32which are formed by polysilicon, the oxide insulating layer30eis referred to as an inter-poly oxide insulating layer (IPO). Note that, in the specification, the oxide insulating layer30ebetween the gate and the shield gate is referred to as an intermediate insulating layer.

In this shield gate type FET (n channel), when a positive voltage is applied to the gate region32in a state that a predetermined voltage is applied between the source region20and the drain region14, a vertical channel is formed in the p region18surrounding the gate region32by a generated electric field, the source and the drain are conductive to each other, and a current flows therebetween. Moreover, the shield gate region34may be electrically connected to the gate region32or the source region20.

The shield gate type FET has the shield gate region34in addition to the gate region32. The shield gate region34is connected to the source, and thus when a voltage is applied between the drain and the source, a depletion layer spreads not only from the p region18but also from the side surface of the ONO structure30b, and thereby the n region16between the trench12and the trench12can be quickly depleted. As a result, the capacitance between the gate and the drain can be reduced, and high-speed switching/switching loss can be reduced.

[Manufacturing Method]

Next, a method for manufacturing the field-effect transistor (shield gate type FET) according to the embodiment is described with reference toFIGS.2A to2DandFIGS.3A to3D.

The trench12is formed as a vertical hole from the surface to the inside of the semiconductor substrate10by photolithography (processing including processes such as deposition, exposure, development, etching, and the like of a photoresist) (FIG.2A).

That is, in the semiconductor substrate10having an oxide film50formed on the surface, the oxide film50is etched using a photoresist, the photoresist is removed, then the semiconductor substrate is etched (Si-etched) with the oxide film50serving as a mask, and the trench12is formed. In the drawing, the oxide film50remains on the surface of the semiconductor substrate10around the upper side of the trench12.

After the oxide film50is removed, a first oxide insulating layer (SiO2) O1, a nitride insulating layer (SiN) N (40), and a second oxide insulating layer (SiO2) O2 (30c) are formed in this order on the inner wall of the trench12and around an upper part of the trench12, and polysilicon52is formed inside the trench12and at the upper part of the trench12(FIG.2B). Note that, the oxide insulating layer O1 on the outer side is referred to as the first oxide insulating layer, is normally formed by thermal oxidation, and corresponds to the oxide insulating layer30binFIG.1. Thereafter, an upper part of the nitride insulating layer N is removed, and the nitride insulating layer N in which the upper part has been removed becomes the nitride insulating layer40inFIG.1. The second oxide insulating layer O2 is deposited by CVD or the like to become the oxide insulating layer30cinFIG.1.

Next, the polysilicon52is etched back to a predetermined height and shaped into a shape corresponding to the shield gate region34(FIG.2C).

On the oxide insulating layer O2 above and at the upper side walls of the shield gate region34, and above the shield gate region34, an oxide insulating layer O3 which becomes an IPO (the oxide insulating layer30e) is formed (FIG.2D).

A predetermined amount of the oxide insulating layer O3 (30e) remains above the shield gate region34, the oxide insulating layers O2 and O3 (the side walls) closer to the inner side than the nitride insulating layer40at the upper part inside the trench12are removed to expose the nitride insulating layer N thereof (FIG.3A).

The nitride insulating layer N in the exposed part is removed by etching (FIG.3B), and the remaining lower part of the nitride insulating layer N is taken as the nitride insulating layer40. Here, because the removal of the nitride insulating layer N to be removed is reliably performed, the upper end of the remaining nitride insulating layer40is recessed with respect to the surface of the surrounding oxide insulating layer O3, and a recessed part60is formed.

In order to make the oxide insulating layer30awhich becomes the side wall of a part forming the gate region32later have an appropriate thickness, the oxide insulating layer O3 is additionally deposited by CVD (FIG.3C).

In the embodiment, the recessed part60generated due to the removal of the nitride insulating layer N is sufficiently filled at this time. The surface of the oxide insulating layer O3 becomes to have a convex shape. Then, polysilicon54for the gate region32is deposited (FIG.3D).

Subsequently, the polysilicon54is etched back and shaped to have a predetermined size, the polysilicon54that has been etched back and shaped to have a predetermined size is taken as the gate region32, and an oxide insulating layer is further deposited on the gate region32. Thereafter, a source and the like are formed, and a shield gate trench type FET is formed.

[Removal of Nitride Insulating Layer]

FIGS.4A to4Cshow the state from the removal of the nitride insulating layer40to the subsequent formation of the oxide insulating layer O3 by the conventional method (Comparative example) here (corresponding toFIGS.3A to3C).

In this way, the recessed part60, which is formed after the nitride insulating layer N is removed, cannot be sufficiently filled by the subsequent formation of an oxide insulating layer (referred to as a third oxide insulating layer) by CVD, and the recessed part remains.

That is, before the gate region32is formed, in order to form the gate region32, the oxide insulating layer (SiO2) is etched, and then the nitride insulating layer N is etched. Accordingly, the recessed part60is formed on the upper end of the nitride insulating layer N. In the subsequent formation of the additional oxide insulating layer O3 by CVD, the layer thickness of the additional oxide insulating layer O3 is not thick enough to adjust the desirable gate oxide layer to have an appropriate thickness, and the recessed part60at the upper end of the nitride insulating layer N is not sufficiently filled. Therefore, when the gate region32is formed on the oxide insulating layer O3 (IPO) existing above the shield gate region34, a downward protrusion part of the gate region32is generated on the nitride insulating layer40.

When a voltage is applied to the gate region32, the electric field is concentrated on the protrusion part of the gate region32, and the leakage current increases.

FIG.5is a schematic diagram showing the electric field strength in a case in which the recessed part remains even when the oxide insulating layer30is additionally formed by CVD, and the black-painted part is a part having a great electric field strength. In this way, at a position where the oxide insulating layer30is thin and which faces the protrusion part of the gate region32, a part having a great electric field strength is generated. Thus, a current is likely to flow to this part, and a leakage current between the gate and the source is likely to increase.

FIGS.6A and6Bshow the state from the removal of the nitride insulating layer40to the subsequent formation of the oxide insulating layer according to the embodiment (corresponding toFIGS.3A to3C). In this way, by forming the oxide insulating layer thicker than a predetermined thickness by CVD, the recessed part generated along with the removal of the nitride insulating layer N (40) is backfilled, the surface thereof is made to have a convex shape, and the formation of the recessed part in the oxide insulating layer O3 is prevented.

In particular, as shown inFIG.6B, a thickness Δ1 of the oxide insulating layer on the side wall is set to be ½ of a thickness d of the nitride insulating layer or more (Δ1≥d/2), and a thickness Δ2 of the oxide insulating layer O3 (30e) from the nitride insulating layer40to the gate region32is set to be ½ of the thickness d of the nitride insulating layer or more (Δ2≥d/2).

Accordingly, the recess of the surrounding portion of the oxide insulating layer O3 (30e) is eliminated, and thus the protrusion part of the gate region32is also eliminated. As shown inFIG.7, the concentration of the electric field can be avoided.

The width of the recessed part generated along with the removal of the nitride insulating layer40corresponds to the thickness d of the nitride insulating layer40. The oxide insulating layer formed by CVD is deposited on the side walls and the surface of the bottom surface of the recessed part.

When an oxide insulating layer having a thickness of d/2 is deposited on the side walls, the recessed part is to be filled. Thus, when the condition of Δ1≥d/2 is satisfied, the recessed part is to be filled; and when the deposition on the bottom surface is added hereto, the oxide insulating layer which is enough to or more than enough to fill the recessed part is deposited.

When Δ2≥d/2 is satisfied, the concentration of the electric field can be reliably avoided.

Here, the concentration of the electric field can be avoided by satisfying either Δ1≥d/2 or Δ2≥d/2, but it is more effective when both Δ1≥d/2 and Δ2≥d/2 are satisfied.

Moreover, in order to maintain an appropriate thickness of the oxide insulating layer on the outer side of the gate region (outside the side walls of the gate region) inside the trench, it is preferable that the oxide insulating layer on the outer side of the nitride insulating layer is made relatively thin, and thus an appropriate thickness of the insulating layer on the lateral sides of the gate region is maintained even when a thick insulating layer is formed by CVD.

That is, as shown inFIG.8, the oxide insulating layer30bis formed by thermal oxidation at the inner wall of the trench12. The thickness of the oxide insulating layer30bis a distance from the inner wall of the trench12to the nitride insulating layer40. An oxide insulating layer30fof CVD is formed above the nitride insulating layer40and above the oxide insulating layer30eon the inner side. In this example, the thickness of the oxide insulating layer30bis made thinner than normal. Accordingly, even when the oxide insulating layer30fformed by CVD is made relatively thick, a thickness D from the inner wall of the trench12, including the oxide insulating layers30band30fon the inner side, can be made to achieve a desired thickness.

Effect of Embodiment

According to the shield gate trench type FET according to the embodiment, the oxide insulating layer30surrounding the shield gate region34is made to have a three-layer structure of ONO (oxide insulating layer/nitride layer/oxide insulating layer), but the recessed part, which is generated along with the removal of the nitride insulating layer in the surrounding portion of the IPO, can be sufficiently filled with the oxide insulating layer formed by CVD. Thus, the generation of the protrusion part in the gate region can be prevented, and the generation of the leakage current can be effectively prevented.

REFERENCE SIGNS LIST

10: semiconductor substrate12: trench14: drain region16: n region18: p region20: source region22: conductive portion24: p+ region30: oxide insulating layer32: gate region34: shield gate region40: nitride insulating layer