Patent ID: 12218059

DETAILED DESCRIPTION

In the following detailed description of the invention, numerous details, examples, and embodiments of the invention are set forth and described. However, it will be clear and apparent to one skilled in the art that the invention is not limited to the embodiments set forth and that the invention may be practiced without some of the specific details and examples discussed.

Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments (also referred to as interconnect lines or wires) that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers.

FIG.1illustrates a 3D circuit100of some embodiments of the invention. As shown, the circuit100includes two IC dies105and110that are in a vertically stacked, face-to-face arrangement. Although not shown inFIG.1, the stacked first and second dies in some embodiments are encapsulated into one integrated circuit package by an encapsulating epoxy and/or a chip case. The first die105includes a first semiconductor substrate120and a first set of interconnect layers125defined above the first semiconductor substrate120. Similarly, the second IC die110includes a second semiconductor substrate130and a second set of interconnect layers135defined above the second semiconductor substrate130. In some embodiments, a subset140of one or more interconnect layers of the second set interconnect layers135of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die105(e.g., to the interconnect layers and/or substrate of the first die105). This subset140is referred to below as the shared interconnect-layer subset.

In some embodiments, numerous electronic components (e.g., active components, like transistors and diodes, or passive components, like resistors and capacitors) are defined on the first semiconductor substrate120and on the second semiconductor substrate130. The electronic components on the first substrate120are connected to each other through interconnect wiring on the first set of interconnect layers125to form numerous microcircuits (e.g., Boolean gates) and/or larger circuits (e.g., functional blocks). Similarly, the electronic components on the second substrate130are connected to each other through interconnect wiring on the second set of interconnect layers135to form additional microcircuits (e.g., Boolean gates) and/or larger circuits (e.g., functional blocks).

In some embodiments, the electronic components on one die's substrate (e.g., the first substrate120of the first die105) are also connected to other electronic components on the same substrate (e.g., substrate120) through interconnect wiring on the other die's set of interconnect layers (e.g., the second set of interconnect layers135of the second die110) to form additional microcircuits and/or larger circuits.

In some embodiments, power, clock and/or data-bus signals from the shared interconnect-layer subset140of the second die110are supplied to several electronic components, microcircuits, and larger circuits of the first die105. Also, in some of these embodiments, the power, clock and/or data-bus signals from the shared interconnect-layer subset140are also supplied to electronic components, microcircuits, and larger circuits that are formed on the second substrate of the second die110.

To form the 3D circuit100ofFIG.1, the first and second dies are face-to-face stacked so that the first and second set of interconnect layers125and135are facing each other. The top interconnect layers160and165are bonded to each other through a direct bonding process that establishes direct-contact metal-to-metal bonding, oxide bonding, or fusion bonding between these two sets of interconnect layers. An example of such bonding is copper-to-copper (Cu—Cu) metallic bonding between two copper conductors in direct contact. In some embodiments, the direct bonding is provided by a hybrid bonding technique such as DBI® (direct bond interconnect) technology, and other metal bonding techniques (such as those offered by Invensas Bonding Technologies, Inc., an Xperi Corporation company, San Jose, CA). In some embodiments, DBI connects span across silicon oxide and silicon nitride surfaces.

The DBI process is further described in U.S. Pat. Nos. 6,962,835 and 7,485,968, both of which are incorporated herein by reference. This process is also described in U.S. patent application Ser. No. 15/725,030, now issued as U.S. Pat. No. 10,522,352, which is also incorporated herein by reference. As described in U.S. patent application Ser. No. 15/725,030, the direct bonded connections between two face-to-face mounted IC dies are native interconnects that allow signals to span two different dies with no standard interfaces and no input/output protocols at the cross-die boundaries. In other words, the direct bonded interconnects allow native signals from one die to pass directly to the other die with no modification of the native signal or negligible modification of the native signal, thereby forgoing standard interfacing and consortium-imposed input/output protocols.

In this manner, the direct bonded interconnects allow circuits to be formed across and/or to be accessed through the cross-die boundary of two face-to-face mounted dies. Examples of such circuits are further described in U.S. patent application Ser. No. 15/725,030. The incorporated U.S. Pat. Nos. 6,962,835, 7,485,968, and U.S. patent application Ser. No. 15/725,030 also describe fabrication techniques for manufacturing two face-to-face mounted dies.

As shown inFIG.1, the direct bonding techniques of some embodiments allow a large number of direct connections150to be established between the top interconnect layer165of the second die110and top interconnect layer160of the first die105. For these signals to traverse to other interconnect layers of the first die105or to the substrate120of the first die105, the first die in some embodiments uses other IC structures (e.g., vias) to carry these signals from its top interconnect layer to these other layers and/or substrate. In some embodiments, more than 1,000 connections/mm2, 10,000 connections/mm2, 100,000 connections/mm2, 1,000,000 connections/mm2or less, etc. can be established between the top interconnect layers160and165of the first and second dies105and110in order to allow power, clock and/or data-bus signals to traverse between the first and second IC dies.

The direct-bonded connections150between the first and second dies are very short in length. For instance, based on current manufacturing technologies, the direct-bonded connections can range from a fraction of a micron to a single-digit or low double-digit microns (e.g., 2-10 microns). As further described below, the short length of these connections allows the signals traversing through these connections to reach their destinations quickly while experiencing no or minimal capacitive load from nearby planar wiring and nearby direct-bonded vertical connections. The planar wiring connections are referred to as x-y wiring or connections, as such wiring stays mostly within a plane define by an x-y axis of the 3D circuit. On the other hand, vertical connections between two dies or between two interconnect layers are referred to as z-axis wiring or connections, as such wiring mostly traverses in the z-axis of the 3D circuit. The use of “vertical” in expressing a z-axis connection should not be confused with horizontal or vertical preferred direction planar wiring that traverse an individual interconnect layer, as further described below.

In some embodiments, the pitch between two neighboring direct-bonded connections150can be extremely small, e.g., the pitch for two neighboring connections is between 0.2 μm to 15 μm. This close proximity allows for the large number and high density of such connections between the top interconnect layers160and165of the first and second dies105and110. Moreover, the close proximity of these connections does not introduce much capacitive load between two neighboring z-axis connections because of their short length and small interconnect pad size. For instance, in some embodiments, the direct bonded connections are less then 1 or 2 μmin length (e.g., 0.1 to 0.5 μmin length), and facilitate short z-axis connections (e.g., 1 to 10 μmin length) between two different locations on the two dies even after accounting for the length of vias on each of the dies. In sum, the direct vertical connections between two dies offer short, fast paths between different locations on these dies.

Stacking IC dies to share power, clock and/or data-bus signals between two dies reduces the overall number of interconnect layers of the two dies because it allows the two dies to share some of the higher-level interconnect layers in order to distribute power, clock and/or data-bus signals. For example, as further described below, this sharing of interconnect layers allows the two dies to share one power mesh between them. In some embodiments, this shared power mesh is formed by direct bonding a power/ground top interconnect layer of one die (e.g., layer160of the first die105) with a power/ground top interconnect layer of the other die (e.g., layer165of the second die110). In other embodiments, this shared power mesh is formed by two interconnect layers of one die (e.g., the top two interconnect layers of the second die110) that are shared with the other die (e.g., the first die105). Reducing the higher-level interconnect layers is beneficial as the wiring on these layers often consume more space due to their thicker, wider and coarser arrangements. In addition, the ability to share the use of these interconnect layers on multiple dies may reduce the congestion and route limitations that may be more constrained on one die than another.

Stacking the IC dies in many cases also allows the wiring for delivering the power, clock and/or data-bus signals to be much shorter, as the stacking provides more candidate locations for shorter connections between power, clock and/or data-bus signal interconnects and the circuit components that are to receive these signals. For instance, as further described below, some embodiments provide data-bus signals to circuits on the first data through short direct-bonded connections from a data bus on a shared interconnect layer of the second die. These direct-bonded connections are much shorter than connections that would route data-bus signals on the first die about several functional blocks in order to reach a circuit within another block from that block's periphery. The data signals that traverse the short direct-bonded connections reach their destination circuits on the first die very quickly (e.g., within 1 or 2 clock cycles) as they do not need to be routed from the periphery of the destination block. On a less-congested shared interconnect layer, a data-bus line can be positioned over or near a destination circuit on the first die to ensure that the data-bus signal on this line can be provide to the destination circuit through a short direct-bonded connection.

Stacking the IC dies also allows the dies to share power, clock and/or data-bus circuits. For instance, as shown inFIGS.2-4, the first die105in some embodiments uses power circuits, clock circuits, and/or data-bus circuits that are formed on the substrate130of the second die110. In these figures, the examples of power, clock and data-bus circuits are respectively voltage regulators205, clock drivers305, and PHY (physical layer) interfaces405(e.g., chip I/O interface, memory I/O interface, etc.).

Having the first die share power, clock and/or data-bus circuits defined on the second die frees up space on the first die to implement other circuits and functional blocks of the 3D circuit. The resulting savings can be quite significant because power, clock and/or data-bus circuits can consume a significant portion of available space. For example, chip I/O circuits (e.g., SERDES I/O circuits) and memory I/O circuits (e.g., DDR memory I/O circuits) can be larger than many other circuits on an IC. Pushing off all or some of the power and clock circuits from the first die to the second die further frees up space on the first die because power and clock circuits often need to be isolated from other circuits and/or signals that can affect the operation of the power and clock circuits. Having system level circuits on just one die also allows for better isolation of such circuits (e.g., better isolation of voltage regulators and/or clock circuits).

In sum, stacking the IC dies optimizes the cost and performance of a chip stack system by combining certain functionalities into common interconnect layers and sharing these functions with multiple die in the stack. The functionalities provided by the higher-level interconnect layers can be shared with multiple dies in the stack. The higher-level interconnect layers require thicker and wider metal and coarser pitch. Removing them allows each chip to be connected with a few inner level interconnect layers with higher density vias to enable higher performance and lower cost. Examples of the high-level interconnect layers include system level circuitry layers, and RDL layers. The system circuits include power circuits, clock circuits, data bus circuits, ESD (electro-static discharge) circuits, test circuits, etc.

Each interconnect layer of an IC die typically has a preferred wiring direction (also called routing direction). Also, in some embodiments, the preferred wiring directions of successive interconnect layers of an IC die are orthogonal to each other. For example, the preferred wiring directions of an IC die typically alternate between horizontal and vertical preferred wiring directions, although several wiring architectures have been introduced that employ 45 degree and 60 degree offset between the preferred wiring directions of successive interconnect layers. Alternating the wiring directions between successive interconnect layers of an IC die has several advantages, such as providing better signal routing and avoiding capacitive coupling between long parallel segments on adjacent interconnect layers.

When face-to-face mounting of first and second IC dies, some embodiments have the preferred wiring directions of the top interconnect layers of the first and second dies be orthogonal to each other in order to realize these same benefits as well as other unique benefits of orthogonal preferred wiring directions at the juncture of the face-to-face mounting.FIG.5illustrates an example of the top interconnect layers of the first and second dies505and510having preferred wiring directions that are orthogonal to each other. In this example, the top interconnect layer502of the first die505has a preferred horizontal direction, while the top interconnect layer504of the second die510has a preferred vertical direction. As shown, the first die's top layer502can have short vertical wire segments, and the second die's top layer504can have short horizontal wire segments. However, the majority of the segments on the top layers502and504are respectively horizontal and vertical.

Different embodiments employ different techniques to ensure that the preferred wiring directions of the top interconnect layers of the first and second dies are orthogonal to each other.FIGS.6-8illustrate examples of several such techniques.FIG.6illustrates that the two dies605and610are manufactured with different processes in some embodiments. The process for the first die605defines the first interconnect layer of the first die to have a horizontal preferred wiring direction, while the process for the second die610defines the first interconnect layer of the second dies to have a vertical preferred wiring direction. As both these processes define seven interconnect layers above the IC substrate and alternate the preferred wiring directions between successive layers, the seventh layer of the first die has a horizontal preferred direction while the seventh layer of the second die has a vertical preferred direction.

FIG.7illustrates an example in which the first and second dies have different preferred wiring directions for their top interconnect layers because they have different number of interconnect layers. In this example, the preferred wiring direction of the first interconnect layer of both dies705and710has the same wiring direction (the horizontal in this example). However, the first die has seven interconnect layers while the second die has six interconnect layers. Hence, the top interconnect layer (the seventh layer) of the first die has a horizontal preferred wiring direction, while the top interconnect layer (the sixth layer) of the second die has a vertical preferred wiring direction.

FIG.8presents an example that illustrates achieving orthogonal preferred wmng directions between the top interconnect layers of the two face-to-face mounted dies805and810by rotating one of the two dies by 90 degrees. In this example, the preferred wiring directions of the interconnect layers of the first and second dies805and810are identical, i.e., they both start with a horizontal preferred wiring direction, alternate the preferred wiring directions for successive layers, and end with a vertical preferred wiring direction.

Also, in some embodiments, the first and second dies805and810are fabricated with several masks that are jointly defined as these two dies implement one IC design. The jointly defined masks for the two dies805and810share one or more common masks in some embodiments. In other embodiments, the first and second dies805and810are from different manufacturing processes and/or different foundries.

However, before face-to-face stacking the two dies805and810, the second die is rotated by 90 degrees. This rotation in effect flips the preferred wiring direction of each interconnect layer of the second die to be orthogonal to the preferred wiring direction of the corresponding interconnect layer of the first die. Thus, the top layer of the rotated second die has effectively a vertical preferred wiring direction compared to the horizontal preferred wiring direction of the top layer of the first die.

InFIG.8, the effective preferred wiring directions of the second die are specified by placing these directions in quotes to indicate that these directions are not indicative of the manufactured preferred directions but are indicative of the wiring directions compared to the first die's wiring direction and are achieved by rotating the second die with respect to the first die. In some embodiments, the two dies805and810are produced from the same mono crystalline silicon wafer or are produced from two mono crystalline silicon wafers with the same crystalline direction.

In some of these embodiments, the two dies805and810have orthogonal crystalline directions after they have been face-to-face mounted.

Having the preferred wiring direction of the top interconnect layers of the first and second dies be orthogonal to each other has several advantages. It provides better signal routing between the IC dies and avoids capacitive coupling between long parallel segments on adjacent interconnect layers of the two dies. Also, it allows the first and second dies to share the power lines on their top orthogonal layers, and thereby eliminating one or more of their power layers. Orthogonal wiring directions on the top layers of the first and second dies increases the overlap between the power wiring on these layers. This overlap increases the number of candidate locations for bonding different pairs of power wires on the top interconnect layers of the different dies to provide power signals from one die to another die.

FIG.9presents an example that illustrates a power mesh950that is formed by the top interconnect layers902and904of the first and second dies905and910in some embodiments. This mesh supplies power and ground signals to circuits defined on the first and second substrates920and930of the first and second dies905and910. As shown, the top interconnect layer902of the first die905has a set of alternating power lines915and ground lines920that traverse along the horizontal direction, while the top interconnect layer904of the second die910has a set of alternating power lines925and ground lines930that traverse along the vertical direction.

In some embodiments, the power/ground lines on one die's interconnect layer are directly bonded (e.g., through DBI interconnects) to corresponding power/ground lines on the other die's interconnect layer at each or some of the overlaps955between corresponding pairs of power lines and pairs of ground lines. This direct bonding creates a very robust power mesh950for the first and second dies without using two different interconnect layers for each of these two dies. This frees up at least one interconnect layer on each die and in total eliminates two interconnect layers from the 3D circuit (formed by the face-to-face bonded dies905and910) by having the two dies share one power mesh. Also, the face-to-face mounted top interconnect layers allow thicker and wider interconnect lines to be used for the power signals, which, in turn, allows these signals to face less resistance and suffer less signal degradation.

In some embodiments, the power and ground signals are supplied by power circuitry defined on the substrate of the second die910as described above by reference toFIG.2. In some of these embodiments, the power and ground signals from the power circuitry are supplied from the second die's substrate through vias to the power and ground lines on the top interconnect layer904of the second die910. From this interconnect layer904, these signals are supplied through direct bonded connections (e.g., DBI connections) to power and ground lines on the top interconnect layer902of the first die905, from where they are supplied to circuits and other interconnect layers of the first die905.

FIG.10presents another example for sharing a power mesh1050between the first and second dies1005and1010in some embodiments. In this example, the power mesh1050is formed by the top two interconnect layers1002and1004of the second die1010. Other than both of these interconnect layers belonging to the second die1010, these two interconnect layers1002and1004are similar to the interconnect layers902and904. Specifically, the interconnect layer1002has alternating power lines1015and ground lines1020while the interconnect layer1004has alternating power lines1025and ground lines1030, with vias defined at each or some of the overlaps1055between corresponding pairs of power lines and pairs of ground lines.

The power mesh architecture ofFIG.10consumes two interconnect layers of the second die1010but does not use any interconnect layers of the first die. Hence, like the power mesh950, the power mesh1050eliminates in total two interconnect layers from the 3D circuit by having the two dies share one power mesh. Also, defining the power mesh with the top two interconnect layers of the die1010allows thicker and wider interconnect lines to be used for the power signals, which, in turn, allows these signals to face less resistance and suffer less signal degradation.

In some embodiments, the power and ground signals are supplied by power circuitry defined on the substrate of the second die1010to the power and ground lines1015-1030on the top-two interconnect layers1002and1004of the second die1010. From these interconnect layers1002and1004, these signals are supplied to power and ground interconnect lines and/or pads on the top interconnect layer of the first die1005through direct-bonded connections (e.g., DBI connections) between the first and second dies1005and1010. From the top interconnect layer of the first die1005, the power and ground signals are then supplied through vias to other interconnect layers of the first die1005and to circuits defined on the substrate of the first die.

In power mesh architectures ofFIGS.9and10, as well as some of the other figures described below, the direct connections or vias that establish the electrical connections between two power lines on two different layers, or two ground lines on two different layers, electrically shield signals that traverse vertically in between these connections/vias through their own vertical connections or vias that traverse different interconnect layers on the same die or different dies. Also, in these examples, the power lines distribute power and ground signals. One of ordinary skill will realize that in other embodiments, the shared power distribution networks between two or more vertically stacked dies distribute other types of power signals, such as reference voltages (VREF) and low power state voltages.

Also, in some embodiments, a first power mesh is defined on the top two interconnect layers of a first die, while a second power mesh is defined on the top two interconnect layers of a second die that is face to face mounted with the first die through a direct bonding process. In some of these embodiments, the direction of the power/ground interconnects on the top interconnect layer of the first die is orthogonal to the direction of the power/ground interconnects on the top interconnect layer of the second die.

In other embodiments, two dies that are face-to-face mounted through a direct bonding process (e.g., a DBI process) have power/ground lines on the top two interconnect layers of a first die (like layers1002and1004ofFIG.10), but power/ground lines only on the top interconnect layer of the second die. In some of these embodiments, the direction of the power/ground interconnects on the top interconnect layer of the first die is orthogonal to the direction of the power/ground interconnects on the top interconnect layer of the second die. In this face-to-face mounted 3D chip arrangement, one power sub-mesh is formed by the top two interconnect layers of the first die, while another power sub-mesh is formed by the top interconnect layers of the first and second dies. These two sub-meshes form a three-layer shared power mesh on the two dies.

The shared power meshes that are formed by the top interconnect layers of one or both dies are used in some embodiments to shield other types of interconnect lines on these layers or between these layers. Specifically, some embodiments not only share a power mesh between two face-to-face mounted dies, but also share a clock tree that is formed on one or two interconnect layers that are shared between the two dies. In some embodiments, the clock tree is formed on the same shared interconnect layers that form the power mesh, while in other embodiments the interconnect layer or layers that contain the clock mesh are in between the interconnect layers that form the power mesh. The power mesh in some embodiments shields the clock lines from capacitive coupling of the other clock and data interconnect lines.

FIG.11illustrates a shared interconnect architecture of some embodiments. In this architecture, the top two interconnect layers1115and1120of two face-to-face mounted dies1105and1110(that form a 3D stacked chip1100) have power, ground and clock lines that form a power mesh1150and a clock tree1160.FIG.11has four sets of schematics. The first set shows the two face-to-face mounted dies1105and1110. The second set shows dies1105and1110, and expanded views of the top two interconnect layers1115and1120of these two dies. The top half of the third set of schematics shows just the power and ground lines on the top two interconnect layers1115and1120, while the bottom half of the third set shows just the clock lines on these two layers. Lastly, top half of the fourth set of schematics shows the power mesh formed by the power and ground lines of the top two interconnect layers1115and1120, while the bottom half of this set shows the clock tree1160formed by the clock lines on these two layers.

As shown in the second and third sets of schematics ofFIG.11, the top interconnect layer1115of the first die1105includes horizontal power lines1130, ground lines1135and clock lines1140, while the top interconnect layer1120of the second die1110includes vertical power lines1130, ground lines1135and clock lines1140. In these schematics, the power/ground lines1130and1135are thinner, long solid lines, while the clock lines1140are thicker, shorter line segments.

The power and ground lines1130and1135on each interconnect layer alternate in their order (i.e., a power line is followed by a ground line, which is followed by a power line, and so on). Also, one set of clock line segments are placed between each neighboring pair of power and ground lines1130and1135. Thus, each clock line segment1140on each interconnect layer is between two power/ground lines1130and1135that shield the clock line segment from nearby clock and data lines and thereby reduce the capacitive coupling between the clock line segment and the nearby clock and data lines. Also, by virtue of being in the top interconnect layers, the clock line segments are thicker and wider, which, in turn, reduces their resistance and allows the clock signals that they carry to be driven longer distances.

The horizontal and vertical clock line segments on the interconnect layers1115and1120form a shared H-tree clock structure1160that distributes a clock signal to the circuits on the first and second dies1105and1110. The H-tree clock structure will be further described below. To form the clock tree1160, each horizontal clock line segment on the interconnect layer1115is connected through at least one direct bonded connection (e.g., DBI connection) to at least one vertical clock line segment on the interconnect layer1120. Some of clock line segments on one top interconnect layer (e.g., layer1115) connect to three clock line segments on the other interconnect layer (e.g., layer1120) through three direct bonded connections (e.g., DBI connections). Similarly, to form the power mesh1150, (1) each power line on one interconnect layer (e.g., layer1115) connects through one or more direct bonded connections (e.g., DBI connections) to one or more power lines on the other interconnect layer (e.g., layer1120), and (2) each ground line on one interconnect layer (e.g., layer1115) connects through one or more direct bonded connections (e.g., DBI connections) to one or more ground lines on the other interconnect layer (e.g., layer1120).

The power mesh1150and clock tree1160eliminate two or more interconnect layers from the 3D circuit by having the two dies share two interconnect layers1105and1110that together form the power mesh1150and the clock tree1160. On each die1105or1110, the power, ground and clock signals are distributed among the interconnect layers of that die through vias between the interconnect layers. In some embodiments, power and clock circuits are defined on the substrate of only one of the dies (e.g., on the substrate of the second die1110). In other embodiments, the power circuits are defined on the substrate of one die (e.g., the substrate of the first die1105), while the clock circuits are defined on the substrate of the other die (e.g., the substrate of the second die1110). In other embodiments, power and/or clock circuits are defined on the substrate of both dies1105and1110.

The H-tree clock structure includes a hierarchical series of H-structures, with each H-structure distributing the same clock signal from the center of the H-structure to the outer four comers of the H-structure, where the signal is passed to the center of another, smaller H-structure, until the clock signal reaches the outer comer of the smallest H-structures. The center of the largest H-structure receives the clock signal from a clock circuit that is defined on the second die's substrate in some embodiments. In other embodiments, this signal is supplied to other locations of the H-structure from the clock circuit on the second die's substrate, or to a location on the H-structure from a clock circuit on the first die's substrate. In some embodiments, the clock signal is distributed from H-tree structure1160to circuits and interconnects of the first and second dies through vias.

FIG.12presents another example for sharing a power mesh1250and a clock tree1260between the first and second dies1205and1210in some embodiments. In this example, the power mesh1250and the clock tree1260are formed by the top two interconnect layers1215and1220of a second die1210that is face-to-face mounted through direct bonded connections with a first die1205to form a 3D chip1200. Other than both of these interconnect layers belonging to the second die1210, these two interconnect layers1215and1220are similar to the interconnect layers1115and1120.

Specifically, each interconnect layer1215or1220has alternating power lines1225and ground lines1230and clock line segments between neighboring pairs of power and ground lines. Vias are defined at each or some of the overlaps between corresponding pairs of power lines, corresponding pairs of ground lines and corresponding pairs of clock line segments, in order to create the power mesh1250and the clock tree1260. The shared interconnect architecture ofFIG.12eliminates two or more interconnect layers from the 3D circuit by having the two dies share the two interconnect layers1215and1220that form the power mesh1250and the clock tree1260.

In some embodiments, the power, ground and clock signals are supplied by power and clock circuitry defined on the substrate of the second die1210to the power, ground and clock lines on the interconnect layers1215and1220of the second die1210. From these interconnect layers1215and1220, the power, ground and clock signals are supplied to power, ground and clock interconnect lines and/or pads on the top interconnect layer of the first die1205through direct-bonded connections (e.g., DBI connections) between the first and second dies1205and1210. From the top interconnect layer of the first die1205, the power, ground and clock signals are then supplied through vias to other interconnect layers of the first die1205and to circuits defined on the substrate of the first die. In some embodiments, power circuits and/or clock circuits are also defined on the substrate of the first die1205.

FIG.13illustrates another shared interconnect architecture of some embodiments. In this example, a power mesh1350and a clock tree1360are formed by the top interconnect layer1315of a first die1305and the top two interconnect layers1320and1325of a second die1310, which is face-to-face mounted to the first die1305through direct bonded connections to form a 3D chip1300. The shared architecture of this example is similar to the shared interconnect architecture ofFIG.9, except that the top interconnect layer1320of the second die1310contains a shared H-tree clock structure1350for distributing a clock signal to the circuits on the first and second dies1305and1310, and this interconnect layer1320is between two power/ground interconnect layers1315and1325of the first and second dies1305and1310. This placement of the H-tree clock structure between the power/ground interconnect layers1315and1325shields the clock line segments in this structure from capacitively coupling to interconnect lines that carry data and other signals on other interconnect layers of the first and second dies1305and1310.

The power/ground lines in some embodiments alternate on each of the interconnect layers1315and1325. Also, in some embodiments, the power/ground lines on the interconnect layer1325of the second die connect to pads on this die's interconnect layer1320, and these pads are connected through direct bonded connections (e.g., DBI connections) to power lines on the interconnect layer1315. The power/ground signals in some embodiments are distributed to other interconnect and substrate layers on each die through vias.

Also, in some embodiments, the clock signal is distributed from H-tree structure1360to circuits and interconnects of the second die through vias, while it is distributed from this structure1360to circuits and interconnects of the first die through direct-bonded connections between this structure and clock pads on layer1315of the first die. The direct-bonded connections in some embodiments emanate from the comers of some of the H-structures and travel along the z-axis. The center of the largest H-structure in this clock tree receives the clock signal from a clock circuit that is defined on the second die's substrate in some embodiments. In other embodiments, this signal is supplied to other locations of the H-structure from the clock circuit on the second die's substrate, or to a location on the H-structure from a clock circuit on the first die's substrate.

FIG.14illustrates yet another shared power/clock interconnect architecture of some embodiments. This architecture1400is similar to the power/clock interconnect architecture1300ofFIG.13, except that the power and clock interconnect layers1415,1420and1425are all interconnect layers of the second die1410. In this example, the first die1405does not contain any interconnect layer that is dedicated to either the power or clock lines. Also, in this example, the H-tree clock structure1460is again between the power/ground interconnect layers1415and1425of the second die1410, and hence its clock line segments are shielded by these power/ground interconnect layers from capacitive couplings to other interconnect lines that carry data and other signals on other interconnect layers of the first and second dies1405and1410.

In the architecture1400, the power, ground and clock signals are supplied to circuits and interconnects of the first die by directly bonding these circuits and interconnects through direct-bonded connections from the power/ground lines and clock lines/pads on layer1415of the second die to lines/pads on the top layer1412of the first die1405. The power, ground and clock signals are supplied in some embodiments to circuits, interconnects, and pads of the second die through vias. Similarly, in some embodiments, the power, ground and clock signals are supplied from the top layer1412of the first die1405to circuits and interconnects of the first die1405through vias.

FIG.15illustrates yet another shared power/clock interconnect architecture of some embodiments. This architecture1500is similar to the power/clock interconnect architecture1300ofFIG.13. However, in the architecture1500, the H-tree structure1560is implemented by the top interconnect layers1515and1520of two dies1505and1510, which are face-to-face mounted through direct bonded connections (e.g., DBI connections) to form a 3D chip1500. The clock interconnect layer1515is the top interconnect layer of the first IC die1505and has the horizontal segments of the H-tree structure1560. The clock interconnect layer1510is the top interconnect layer of the second IC die1510, and has the vertical segments of the H-tree structure1560.

The vertical and horizontal segments of the H-tree structure1560are connected to each other through direct-bonded connections (e.g. DBI connections). The center of the largest H-structure receives the clock signal from a clock circuit that is defined on the second die's substrate in some embodiments. In other embodiments, this signal is supplied to other locations of the H-structure from the clock circuit on the second die's substrate, or to a location on the H-structure from a clock circuit on the first die's substrate. In some embodiments, the clock signal is distributed from the clock lines of the interconnect layer1515of the first die1505to circuits and interconnects of the first die through vias defined in the first die. Similarly, the clock signal is distributed from the clock lines on the interconnect layer1520of the second die1510to circuits and interconnects of the second die through vias.

As shown, the H-tree clock structure1560is between the interconnect layer1525of the first die1505and the top interconnect layer1530of the second die1510. Like the position of the H-tree structure1360, the placement of the H-tree clock structure1560between the power/ground interconnect layers1525and1530shields the clock line segments in this structure from capacitively coupling to interconnect lines that carry data and other signals on other interconnect layers of the first and second dies1505and1510.

In this example, the power/ground layers1525and1530connect to power/ground pads on clock interconnect layers1515and1520through vias. The power/ground pads on one of these interconnect layers (e.g., layer1515) connect to corresponding power/ground pads on the other interconnect layer (e.g., layer1520) through direct-bonded connections (e.g., DBI connections). Through these vias and direct-bonded connections, corresponding pairs of power/ground lines are connected on the interconnect layers1525and1530to form the power mesh1550.

The power/ground signals in some embodiments are distributed to other interconnect and substrate layers on each die through vias. In some embodiments, the four power/clock interconnect layers1515,1520,1525and1530are the interconnect layers of one of the dies (e.g., the second die1510), and these four layers are shared by the first die1505. In other embodiments, three of these interconnect layers belong to one die and one of them belongs to another die.

In some embodiments, the 3D chip structure that is formed by two face-to-face mounted dies has one or more clock interconnect layers in between a full power mesh that is formed on the first die and a full/half power mesh that is formed on the second die. A full power mesh on a die in some embodiments includes at least two interconnect layers that contain power/ground interconnect lines. In some of these embodiments, a partial power mesh on a die includes one interconnect layer that contains power/ground interconnect lines, and that connects through z-axis vertical connections (e.g., via and DBI connections) to the power mesh of the other die. In some of these embodiments, the full or partial power mesh layer(s) on one die do not include the top interconnect layer of that die as the top layer is used to carry clock or data interconnect lines (like the top interconnect layers1515and1520ofFIG.15, which carry clock lines).

In some embodiments, two vertically stacked IC dies do not share power-distributing interconnect layers but share interconnect layers for sharing clock signal or signals.FIGS.16-18illustrate examples of two such shared interconnect architectures. InFIG.16, two dies1605and1610are face-to-face mounted through direct bonded connections to form a 3D chip1600. The top interconnect layer1620of the die1610includes a clock tree1660that is used (1) to distribute a clock signal to other interconnect layers of the die1610through vias of this die, and (2) to distribute the clock signal to other interconnect layers of the die1605through direct-bonded connections (e.g., DBI connections) to the top interconnect layer1615of the die1605and then through vias of this die1605.

As in the examples illustrated inFIGS.13and14, the clock tree1660is an H-tree structure. One of ordinary skill will realize that other embodiments use other types of clock distribution structures. The center of the largest H-structure receives the clock signal from a clock circuit that is defined on the second die's substrate in some embodiments. In some of these embodiments, the first IC die1605does not include a clock circuit that generates a clock signal. In other embodiments, this signal is supplied to other locations of the H-structure from the clock circuit on the second die's substrate, or to a location on the H-structure from a clock circuit on the first die's substrate.

FIG.17illustrates two dies1705and1710are face-to-face mounted through direct bonded connections to form a 3D chip1700. In this example, the top interconnect layers1715and1720of these two dies1705and1710respectively include horizontal clock line segments1735and vertical clock line segments1740that together form a clock tree1760that is used to distribute a clock signal to other interconnect layers of the dies1705and1710. The horizontal and vertical line segments on the top interconnect layers1715and1720are connected through direct-bonded connections (e.g., DBI connections) in order to form the H-tree clock structure1760.

One or more clock line segments on the top layer1720of the second die1710in some embodiments receive the clock signal from a clock circuit that is defined on the second die's substrate. In some embodiments, the clock signal is distributed from the clock lines on the interconnect layer1715of the first die1705to circuits and interconnects of the first die through vias of the first die. Similarly, the clock signal is distributed from the clock lines on the interconnect layer1720of the second die1710to circuits and interconnects of the second die through vias.

FIG.18illustrate yet another shared interconnect structure for distributing clock signals between two face-to-face mounted IC dies. This architecture is similar to the architecture ofFIG.17, except that inFIG.18the horizontal and vertical clock interconnect layers1815and1820both belong to a second die1810that is face-to-face mounted through direct bonded connections to a first die1805to form a 3D chip1800. In this architecture, vias between the interconnect layers1815and1820of the second die establish the connections between the clock lines on these layers in order to create the clock structure1860(i.e., the H-tree structure1860) in this example.

Direct bonded connections between the first and second dies1805and1810then supply the clock signal from this clock structure to clock lines/pads on the top interconnect layer of the first die1805. The clock signal is then passed to other interconnect and substrate layers of the first die1805through vias. The clock signal is also passed to other interconnect and substrate layers of the second die1810through vias. In some embodiments, a clock circuit on the second die's substrate supplies the clock signal to one or more clock line segments on interconnect layer1815and/or interconnect layer1820of the second die1810. In other embodiments, the clock signal is generated by a clock circuit defined on the substrate of the first die1805.

One of the unique features of the 3D chips illustrated inFIGS.11-18is that in these chips, the clock lines are moved to the top interconnect layers of a die, or next to the top interconnect layer of the die. Typically, clock lines are not in the top interconnect layers as such a placement would expose the clock signals/lines to interfering signals outside of the chip. However, the face-to-face mounted dies ofFIGS.11-18can place the clock lines in their top interconnect layers as these layers are very well isolated from signals outside of their 3D chips because these interconnect layers are effectively in the middle of the die stack.

In addition to isolating the clock signals, the face-to-face mounted top interconnect layers allow thicker and wider interconnect lines to be used for the clock signals. These signals have less resistance and suffer less signal degradation. Hence, the clock signals can be driven longer distance with no clock signal regeneration (which would require the clock signals to travel to the buffer circuits formed on a semiconductor substrate) or with less clock signal regeneration. This lower resistance advantage (i.e., less signal degradation advantage) of thicker and wider interconnects on upper interconnect layers is also enjoyed by power and data interconnect line segments that are defined on the upper interconnect layers and that are shared between two or more vertically stacked IC dies (e.g., two face-to-face mounted IC dies).

As mentioned above, stacking IC dies also allows two or more dies to share a data bus on one or more share interconnect layers.FIG.19illustrates an example of one such shared interconnect layer architecture that allows two face-to-face mounted IC dies to share a data bus and a data storage that are defined on one of the dies. In this example, the data storage is an on-chip cache1960. In other embodiments, the shared data storage is any other type of storage. InFIG.19, the two face-to-face mounted IC dies1905and1910(that form a 3D chip1900) share a data bus1950that is defined on a top interconnect layer1920of the second die1910. As shown, this top interconnect layer1920connects to the top interconnect layer1915of the first die1905through direct bonded connections (e.g., DBI connections).

Although a data bus does not necessarily need to include parallel interconnect lines, the data bus1950in this example includes several parallel interconnect lines that connect to other interconnect lines on the first and second dies through vias and direct-bonded connections at one or more locations along each interconnect line. These lines are shown to be physically parallel, but in other cases, they are just topologically parallel (e.g., on one end, they connect to several adjacent locations at one position of a die or interconnect layer, while on another end, they connect to several other adjacent locations at another position in a die or interconnect layer). The data bus1950connects through interconnect lines and vias to an input/output interface1955of a cache storage1960that is defined on the substrate1965of the second die1910. Through interconnect lines and vias, the data bus1950also connects to circuits defined on the second die1910, so that through these connections and the I/O interface1955these circuits can receive output data read from the cache storage1960, and provide input data for storing in the cache storage1960.

Through the direct bonded connections, the data bus1950also connects to interconnect lines/pads on the top interconnect layer1915of the first die1905. These interconnect lines/pads on the interconnect layer1915connect to circuits on the first die1905through interconnect lines and vias of the first die1905. Through these connections (i.e., the interconnect lines, vias and direct-bonded connections) and the I/O interface1955, the circuits defined on the first die1905can receive output data read from the cache storage1960, and provide input data for storing in the cache storage1960.

Stacking the IC dies so that they can share one or more data buses allows the wiring for delivering the data to be much shorter, as the stacking provides more candidate locations for shorter connections between data bus interconnects and the circuit components that are to receive these signals. For instance, instead of routing data signals on the second die about several functional blocks in order to reach a circuit or component within another block from that block's periphery, the data signals can be provided directly to that circuit or component on the second die from data-bus interconnect on the shared interconnect layer of the first die. The data signal can be provided to its destination very quickly (e.g., within 1 or 2 clock cycles) as it does not need to be routed from the destination block's periphery, but rather is provided by a short interconnect from the shared interconnect layer above. Shorter connections for data signals reduce the capacitive load on the connections that carry these signals, which, in turn, reduces the signal skew on these lines and allows the 3D circuit to use no or less signal isolation schemes.

FIG.20Aillustrates another example of two face-to-face mounted IC dies sharing resources. In this example, the circuits of first and second dies2005and2010of the two dies share data I/O circuitry, which includes an I/O interface2025, an external data I/O unit2030(e.g., level shifting drivers), and a data I/O bus2022formed by a number of data bus lines. The data I/O unit2030can be an external memory I/O unit or another data interface unit, such as a SerDes unit. InFIG.20A, the two face-to-face mounted IC dies2005and2010form a 3D chip2000. Through silicon vias (TSVs) are defined on the backside of the second die2010. Through these TSVs and the I/O interface, data is received and supplied to the data I/O unit2030defined on the substrate of the second die2010.

The data I/O unit2030connects through interconnect lines and vias of the second die to the data bus2022that is defined on a top interconnect layer2020of the second die2010. As shown, this top interconnect layer2020connects to the top interconnect layer2015of the first die2005through direct bonded connections (e.g., DBI connections). In this example, the data bus2022is again shown to have several parallel interconnect lines that connect to other interconnect lines on the first and second dies through vias and direct-bonded connections at one or more locations along each interconnect line. However, as mentioned above, the interconnect lines of a data bus do not necessarily need to be parallel.

Through interconnect lines and vias, the data bus2022connects to circuits defined on the second die2010, so that through these connections these circuits can receive data from and supply data to the data I/O unit2030. Through the direct bonded connections, the data bus2022also connects to interconnect lines/pads on the top interconnect layer2015of the first die2005. These interconnect lines/pads on the interconnect layer2015connect to circuits on the first die2005through interconnect lines and vias of the first die2005. Through these connections (i.e., the interconnect lines, vias and direct-bonded connections), the circuits defined on the first die2005can receive data from and supply data to the data I/O unit2030.

Some embodiments distribute an IO circuit between two or more vertically stacked IC dies. For instance, some embodiments distribute a SerDes circuit between two vertically stacked IC dies. A SerDes circuit includes digital (logic) portions and analog portions. In some embodiments, the digital portions of the SerDes circuit are implemented on a first IC die, while the analog portions are implemented on a second IC die that is face-to-face mounted or otherwise vertically stacked with the first die. This IO interface has to involve the interaction between these two layers before signals are passed to the core circuitry. Only the two layers together complete the IO circuitry.

FIG.20Billustrates another example of two face-to-face mounted IC dies that form a 3D chip2052and that share data I/O circuits. In this example, the I/O circuitry is defined on both dies2055and2060in order to reduce the area that the I/O circuitry consumes on each die. The I/O circuitry in this example includes two sets of power and ground rails2062-2068, ESD (electro-static discharge) circuits2073, drivers2074, and decoupling capacitors (not shown).

The power/ground rails include two power rails2062and2066on the top interconnect layer2070of the second die2060and two ground rails2064and2068on the top interconnect layer2072of the first die2055. The power and ground rails2062and2064are the I/O interface power and ground rails that carry the power and ground signals for the I/O circuitry (e.g., I/O drivers). The power and ground rails2066and2068are the core power and ground rails that carry the power and ground signals for the core circuits of the first and second dies. The core circuits of the dies are the circuits that perform the computation operations of the dies.

In some embodiments, each power or ground rail is a rectangular ring formed by four rectangular segments, with each segment spanning one of the four sides of the die and connecting to two other rectangular segments of the same rail. In other embodiments, each power rail is not a contiguous ring that spans the entire periphery of the die, as it has one or more discontinuities (e.g., at the comers of the interconnect layer on which it resides). Also, while showing power and ground rails on the top interconnect layers2070and2072, one of ordinary skill will realize that in some embodiments power and ground rails exist on other interconnect layers of the dies (e.g., power rails on several interconnect layers of one die, and ground rails on several interconnect layers of the other die).

Multiple drivers2074are formed on the substrate2082of the first die2055. When signals traverse from circuits outside of the dies to core circuits of the die, the drivers2074level shift these signals to convert them from their external voltage levels to internal voltage levels. Similarly, when signals traverse from the core circuits of the die to circuits outside of the dies, the drivers2074level shift these signals to convert them from their internal voltage levels to external voltage levels. The drivers2074also provide signal buffering. To perform their operations (e.g., level shifting operations), the drivers receive power and ground signals from the power and ground rails2062-2068.

In some embodiments, the substrate2080of the second die2060includes the signal pads that are connected through TSVs to signal pads on the backside of the second die2060. These backside signal pads are connected to external interconnects (e.g., micro bump arrays) that receive signals from and supply signals to external circuits outside of the 3D chip2052. Through these backside signal pads, the signals pads on the front side of the second die substrate2080receive signals from external circuits for the I/O circuitry, and supply signals from the I/O circuitry to external circuits. One of ordinary skill will realize that other embodiments use other structures (e.g., copper pillars connected through interposers) to supply signals to the dies.

As shown, the second die2060includes the ESD circuits2073that are defined on its substrate, while the first die2055includes the drivers2074that are defined on its substrate. The ESD circuits are for maintaining signal stability inside of the chip. The ESD circuits are designed in some embodiments to dissipate quickly external irregular signal surges, in order to maintain signal stability inside of the chip. Each die2055or2060also includes decoupling capacitors that are for maintaining signal stability inside of the chip by eliminating signal noise from affecting signal quality on the chip.

The power or ground rail (I/O or core) on the top interconnect layer of each die has to provide its power signal or ground signal to the other die through the top interconnect layer of the other die. In some embodiments, this is done by having the power signal or ground signal traverse down one layer on the same die with one or more vias, traverse along interconnect lines on that layer, and then traverse back up along one or more vias to one or more pads on the top interconnect layer of its die. These pads have direct-bonded connections (e.g., DBI connections) to pads on the top interconnect layer of the other die. The pads on the other die then distribute to circuits on the other die the received power or ground signals through vias and interconnect lines. Also, between respective power and ground rails (e.g., I/O power and ground rails, or core power and ground rails), some embodiments define decoupling capacitors in the face-to-face mounted layer coupling the two dies, in order to suppress the effect of signal noise on the power supply.

In some embodiments, the core power and ground rails2066and2068respectively connect to interior power and ground lines on the same interconnect layers as the rails2066and2068. These interior power and ground lines in some embodiments form an interior power mesh, such as the power mesh shown in eitherFIG.9or10. Also, in some embodiments, the top interconnect layer of each die2055or2060has additional direct-bonded connections with the top interconnect layer of the other die in order to receive inputs for the I/O circuitry components (e.g., for the ESD circuits, drivers, etc.) from the other die, and to provide outputs from the I/O circuitry components (e.g., for the ESD circuits, drivers, etc.) to the other die.

In prior IC designs, the power/ground rails for the I/O circuitry and IC core are typically defined as four concentric rectangular rings that are placed on a single die along with the decoupling capacitors, drivers, and ESD circuits of the I/O circuitry. Placing these components on one die requires the I/O circuitry to consume a lot of area on the periphery of an IC die. This, in turn, leads to larger dies or leaves less space for the IC core. The 3D chip2052, on the other hand, does not suffer these shortcomings as its I/O circuitry is split on the two dies2055and2060. Also, by placing the power and ground rails (for the I/O and the core) on different dies, the 3D chip2052has far less area devoted to the power and ground rails, leaving more space to the circuits of the IC's core.

One of ordinary skill will understand that the 3D chip2052presents only one way by which the I/O circuits and power rails can be distributed among two vertically stacked (e.g., two face-to-face mounted dies). Other embodiments use other techniques to distribute the I/O circuits and power rails. For instance, in other embodiments, one I/O power rail is on the periphery of a top interconnect layer of a first die, while another I/O power rail is closer to the center of the top interconnect layer(s) of a second die vertically stacked (e.g., face-to-face mounted) with the first die. Still other embodiments define multiple stripes of I/O rails on the higher interconnect layers of two vertically stacked dies and then define multiple cores between different stripes. Accordingly, the architecture presented inFIG.22Bis only illustrative of how some embodiments distribute the I/O circuit and power rails between two vertically stacked dies.

FIG.21illustrates a device2102that uses a 3D IC2100(like any of the 3D IC100,900-2000). In this example, the 3D IC2100is formed by two face-to-face mounted IC dies2105and2110that have numerous direct bonded connections2115between them. In other examples, the 3D IC2100includes three or more vertically stacked IC dies. As shown, the 3D IC die2100includes a cap2150that encapsulates the dies of this IC in a secure housing2125. On the back side of the die2110one or more TSVs and/or interconnect layers2106are defined to connect the 3D IC to a ball grid array2120(e.g., a micro bump array) that allows this to be mounted on a printed circuit board2130of the device2102. The device2102includes other components (not shown). In some embodiments, examples of such components include one or more memory storages (e.g., semiconductor or disk storages), input/output interface circuit(s), one or more processors, etc.

In some embodiments, the first and second dies2105and2110are the first and second dies shown in any of theFIGS.1-20. In some of these embodiments, the second die2110receives power, clock and/or data bus signals through the ball grid array, and routes the received signals to shared power, clock and/or data bus lines on its shared interconnect layer(s), from where the received signals can be supplied to the interconnects/circuits of the first die through direct bonded connections between the first and second dies2105and2110.

FIG.22provides another example of a 3D chip2200that is formed by two face-to-face mounted IC dies2205and2210that are mounted on a ball grid array2240. In this example, the first and second dies2205and2210are face-to-face connected through direct bonded connections (e.g., DBI connections). As shown, several TSVs2222are defined through the second die2210. These TSVs electrically connect to interconnects/pads on the backside of the second die2210, on which multiple levels of interconnects are defined.

In some embodiments, the interconnects on the backside of the second die2210create the signal paths for defining one or more system level circuits for the 3D chip2200(i.e., for the circuits of the first and second dies2205and2210). Examples of system level circuits are power circuits, clock circuits, data I/O signals, test circuits, etc. In some embodiments, the circuit components that are part of the system level circuits (e.g., the power circuits, etc.) are defined on the front side of the second die2210. The circuit components can include active components (e.g., transistors, diodes, etc.), or passive/analog components (e.g., resistors, capacitors (e.g., decoupling capacitors), inductors, filters, etc.

In some embodiments, some or all of the wmng for interconnecting these circuit components to form the system level circuits are defined on interconnect layers on the backside of the second die2210. Using these backside interconnect layers to implement the system level circuits of the 3D chip2200frees up one or more interconnect layers on the front side of the second die2210to share other types of interconnect lines with the first die2205. The backside interconnect layers are also used to define some of the circuit components (e.g., decoupling capacitors, etc.) in some embodiments. As further described below, the backside of the second die2210in some embodiments can also connect to the front or back side of a third die.

In some embodiments, one or more of the layers on the backside of the second die2210are also used to mount this die to the ball grid array2240, which allows the 3D chip2100to mount on a printed circuit board. In some embodiments, the system circuitry receives some or all of the system level signals (e.g., power signals, clock signals, data I/O signals, test signals, etc.) through the ball grid array2240connected to the backside of the third die.

In some embodiments, the backside of the second die2210of chip2200is used to define one or more interconnect layers on which power/ground lines are defined. For instance, in some embodiments, a first interconnect layer on the backside of the second die provides a first set of alternating power and ground lines, while a second interconnect layer on this backside provides another set of alternating power and ground lines. These two sets of alternating power/ground lines form a power mesh (similar the meshes described above by reference toFIGS.9and10) as vias connect power lines in each set to power lines in the other set and ground lines in each set to ground lines in the other set.

The power/ground lines on such backside interconnect layer(s) are thicker and wider lines in some embodiments than the lines on the top interconnect layers on the front side(s) of the first and second dies2205and2210. Gate stress is an undesirable side effect of having very thick power lines on the top interconnect layers on the front sides of the first and second dies. However, this is not an issue when placing thick (e.g., wide) power lines on the backside of IC dies. The thicker and wider power lines on the backside of the second die have less resistance (suffer less signal degradation) and are ideal for supplying additional power signals to the core circuits on the first and second dies. The circuits towards the center of a die can experience power signal degradation due to the power consumption of the circuits that are closer to the periphery of the die. Accordingly, in some embodiments, the power/ground lines on the backside of the second die is used in some embodiments to provide non-degraded power signals to the circuits that are closer to the middle of the first and second dies.

Alternatively to, or conjunctively with, defining the power/ground lines on the backside of the second die2210, clock lines and/or data-bus lines are defined in some embodiments on the backside of the second die. Such clock lines and data-bus lines can be used to achieve analogous interconnect architectures to those described above by reference toFIGS.11-20B. As the backside interconnects can be thicker and wider, the clock lines and data-bus lines can enjoy the same benefits as those described above for the power lines that are defined on the backside of the second die2210. In some embodiments, the interconnect line widths on the backside of the second die2210are in the range of 1-10 microns, while the interconnect line widths on the interconnect layers on the front side of the first and second dies2205and2210are in the range of 1 microns or less.

FIG.23illustrates a manufacturing process2300that some embodiments use to produce the 3D chip2200ofFIG.22. This figure will be explained by reference toFIGS.24-27, which show two wafers2405and2410at different stages of the process. Once cut, the two wafers produce two stacked dies, such as dies2205and2210. Even though the process2300ofFIG.23cuts the wafers into dies after the wafers have been mounted and processed, the manufacturing process of other embodiments performs the cutting operation at a different stage at least for one of the wafers. Specifically, some embodiments cut the first wafer2405into several first dies that are each mounted on the second wafer before the second wafer is cut into individual second dies.

As shown, the process2300starts (at2305) by defining components (e.g., transistors) on the substrates of the first and second wafers2405and2410, and defining multiple interconnect layers above each substrate to define interconnections that form microcircuits (e.g., gates) on each die. To define these components and interconnects on each wafer, the process2300performs multiple IC fabrication operations (e.g., film deposition, patterning, doping, etc.) for each wafer in some embodiments.FIG.24illustrates the first and second wafers2405and2410after several fabrication operations that have defined components and interconnects on these wafers. As shown, the fabrication operations for the second wafer2410defines several TSVs2412that traverse the interconnect layers of the second wafer2410and penetrate a portion of this wafer's substrate2416.

After the first and second wafers have been processed to define their components and interconnects, the process2300face-to-face mounts (at2310) the first and second wafers2205and2210through a direct bonding process, such as a DBI process.FIG.25illustrates the first and second wafers2405and2410after they have been face-to-face mounted through a DBI process. As shown, this DBI process creates a number of direct bonded connections2426between the first and second wafers2405and2410.

Next, at2315, the process2300performs a thinning operation on the backside of the second wafer2410to remove a portion of this wafer's substrate layer. As shown inFIG.26, this thinning operation exposes the TSVs2412on the backside of the second wafer2410. After the thinning operation, the process2300defines (at2320) one or more interconnect layers2430the second wafer's backside.FIG.27illustrates the first and second wafers2405and2410after interconnect layers have been defined on the second wafer's backside.

These interconnect layers2430include one or more layers that allow the 3D chip stack to electrically connect to the ball grid array. In some embodiments, the interconnect lines/pads on the backside of the third wafer also produce one or more redistribution layers (RDL layers) that allow signals to be redistributed to different locations on the backside. The interconnect layers2430on the backside of the second die in some embodiments also create the signal paths for defining one or more system level circuits (e.g., power circuits, clock circuits, data I/O signals, test circuits, etc.) for the circuits of the first and second dies. In some embodiments, the system level circuits are defined by circuit components (e.g., transistors, etc.) that are defined on the front side of the second die. The process2300in some embodiments does not define interconnect layers on the backside of the second wafer to create the signal paths for the system level circuits, as it uses only the first and second dies' interconnect layers between their two faces for establishing the system level signal paths.

After defining the interconnect layers on the backside of the second wafer2410, the process cuts (at2325) the stacked wafers into individual chip stacks, with each chip stack include two stacked IC dies2205and2210. The process then mounts (at2330) each chip stack on a ball grid array and encapsulates the chip stack within one chip housing (e.g., by using a chip case). The process then ends.

In some embodiments, three or more IC dies are stacked to form a 3D chip.FIG.28illustrates an example of a 3D chip2800with three stacked IC dies2805,2810and2815. In this example, the first and second dies2805and2810are face-to-face connected through direct bonded connections (e.g., DBI connections), while the third and second dies2815and2810are face-to-back connected (e.g., the face of the third die2815is mounted on the back of the second die2810). In some embodiments, the first and second dies2805and2810are the first and second dies shown in any of theFIGS.1-20.

InFIG.28, several TSVs2822are defined through the second die2810. These TSVs electrically connect to interconnects/pads on the backside of the second die2810, which connect to interconnects/pads on the top interconnect layer of the third die2815. The third die2815also has a number of TSVs that connect signals on the front side of this die to interconnects/pads on this die's backside. Through interconnects/pads, the third die's backside connects to a ball grid array2840that allows the 3D chip2800to mount on a printed circuit board.

In some embodiments, the third die2815includes system circuitry, such as power circuits, clock circuits, data I/O circuits, test circuits, etc. The system circuitry of the third die2815in some embodiments supplies system level signals (e.g., power signals, clock signals, data I/O signals, test signals, etc.) to the circuits of the first and second dies2805and2810. In some embodiments, the system circuitry receives some or all of the system level signals through the ball grid array2840connected to the backside of the third die.

FIG.29illustrates another example of a 3D chip2900with more than two stacked IC dies. In this example, the 3D chip2900has four IC dies2905,2910,2915and2920. In this example, the first and second dies2905and2910are face-to-face connected through direct bonded connections (e.g., DBI connections), while the third and second dies2915and2910are face-to-back connected (e.g., the face of the third die2915is mounted on the back of the second die2910) and the fourth and third dies2920and2915are face-to-back connected (e.g., the face of the fourth die2920is mounted on the back of the third die2915). In some embodiments, the first and second dies2905and2910are the first and second dies shown in any of theFIGS.1-20.

InFIG.29, several TSVs2922are defined through the second, third and fourth die2910,2915and2920. These TSVs electrically connect to interconnects/pads on the backside of these dies, which connect to interconnects/pads on the top interconnect layer of the die below or the interconnect layer below. Through interconnects/pads and TSVs, the signals from outside of the chip are received from the ball grid array2940.

Other embodiments use other 3D chip stacking architectures. For instance, instead of face-to-back mounting the fourth and third dies2920and2915inFIG.29, the 3D chip stack of another embodiment has these two dies face-to-face mounted, and the second and third dies2910and2915back-to-back mounted. This arrangement would have the third and fourth dies2915and2920share a more tightly arranged set of interconnect layers on their front sides.

While the invention has been described with reference to numerous specific details, one of ordinary skill in the art will recognize that the invention can be embodied in other specific forms without departing from the spirit of the invention. For instance, one of ordinary skill will understand that even though several H-trees were described above as example of clock distribution networks, other embodiments use other types of clock distribution networks. Also, in some embodiments, the stacked dies in a 3D chip share multiple different clock trees on multiple shared interconnect layers in order to distribute multiple different clock signals (e.g., to distribute a different clock signal with each different shared clock tree).

In the examples illustrated inFIG.1-20, a first IC die is shown to be face-to-face mounted with a second IC die. In other embodiments, the first IC die is face-to-face mounted with a passive interposer that electrically connects the die to circuits outside of the 3D chip or to other dies that are face-to-face mounted or back-to-face mounted on the interposer. In some of these embodiments, the passive interposer can include the power, clock, and/or data bus interconnect line architectures that were described inFIGS.1-20for the second dies in these examples. In other words, the interposer can provide the interconnect layers for establishing the power, clock and data-bus lines of the 3D chip.

In some embodiments, the preferred wiring directions of the top layer of the interposer is orthogonal to the preferred wiring directions of the top layer of the first die. This can be achieved by using similar techniques to those described above by reference toFIGS.6-8. Some embodiments place a passive interposer between two faces of two dies. Some embodiments use an interposer to allow a smaller die to connect to a bigger die.

Also, the 3D circuits and ICs of some embodiments have been described by reference to several 3D structures with vertically aligned IC dies. However, other embodiments are implemented with a myriad of other 3D structures. For example, in some embodiments, the 3D circuits are formed with multiple smaller dies placed on a larger die or wafer.FIG.30illustrates one such example. Specifically, it illustrates a 3D chip3000that is formed by face-to-face mounting three smaller dies3010a-con a larger die3005. All four dies are housed in one chip3000by having one side of this chip encapsulated by a cap3020, and the other side mounted on a micro-bump array3025, which connects to a board3030of a device3035. Some embodiments are implemented in a 3D structure that is formed by vertically stacking two sets of vertically stacked multi-die structures.