Patent ID: 12249382

DETAILED DESCRIPTION OF THE DISCLOSURE

For ease of understanding the present disclosure, the present disclosure will be more fully described below with reference to relevant accompanying drawings. A preferred embodiment of the present disclosure is given in the accompanying drawings. However, the present disclosure may be implemented in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided for the purpose of providing a more thorough and comprehensive understanding of the present disclosure.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art belonging to the present disclosure. Terms used herein in the specification of the present disclosure are for a purpose of describing specific embodiments only and are not intended to limit the present disclosure.

A structure of an existing fuse resistance is large at both ends and thin in middle, which has a resistance value of about 50 to 200Ω. When there is current, a current density at a middle part is higher, so when a large current flows through the fuse for a period of time, the middle of the fuse is more likely to be burned off, and a resistance may be up to sevreral megohms (MΩ) after burning; and the fused fuse needs to be used with a larger current or burned for a longer period of time, while the fused fuse, due to residual bridging or electronic-migration, may be connected again to reduce the fused resistance value, such as from several MΩ “grow” to dozens or hundreds of kilohms (KΩ).

Read operation of fused OTP memory is usually done by comparing the voltage value with a threshold value by current flowing through the fuse unit. However, the fused fuse, due to residual bridging or electronic-migration, may be reconnected to reduce the fused resistance value, affecting the accuracy of data readout. The traditional approach to avoid this is to use a very high current burn-in for a long enough time to ensure that the fuse bums out, and at the same time, lower the threshold voltage for comparison, leaving room for the fuse to “grow”. However, such an excessive design will lead to waste of area and power consumption.

To solve such problems, a differential OTP memory is proposed in a prior art, which uses a double fuse cell, with data “0” or “1” corresponding to different fuses to be burned, and the same size of current flowing through the double fuse to get the read operation. The read operation uses the same size of current flow through the double fuse to get the voltage value directly compared, as long as the resistance value of the burned fuse is larger than the unburned one, the correct result may be compared. However, this method lowers the resistance detection threshold of the read circuit and reduces the design overscheduling, but the reliability of the readout data is still in doubt because the resistance value after the fuse “grows” is not known.

Based on this, the present disclosure provides an improved differential OTP reading circuit, which not only reads out a resistance difference between two fuses after a normal burn-in operation is completed, but also has a function of detecting a resistance value of each fuse to ensure accuracy and reliability of readout data in turn.

Hereinafter, the present disclosure is described in detail with reference to the accompanying drawings.

FIG.2shows a schematic block diagram of a reading circuit for a differential OTP memory according to a first embodiment of the present disclosure,FIG.3shows a structural schematic diagram of a detector in the reading circuit for the differential OTP memory shown inFIG.2,FIG.4shows a structural schematic diagram of a latch in the reading circuit for the differential OTP memory shown inFIG.2.

Referring toFIGS.2to4, a first embodiment of the present disclosure provides a reading circuit203for a differential OTP memory200, which includes a first memory cell201and a second memory cell202in a differentially symmetrical structure, and the reading circuit203is connected between the first memory cell201and the second memory cell202, which includes: a detector210, latch220and control unit230.

The detector210has a first input connected to the first memory cell201and a second input connected to the second memory cell202, and is configured to detect a resistance value of a first fuse N-fuse located in the first memory cell201, a resistance value of a second fuse P-fuse located in the second memory cell202, and a resistance difference between the first fuse N-fuse and the second fuse P-fuse after a bum-in operation of the first memory cell201or the second memory cell202is completed; the latch220is configured to provide readout data according to one of the resistance value of the first fuse N-fuse, the resistance value of the second fuse P-fuse, and the resistance difference between the first fuse N-fuse and the second fuse P-fuse detected by the detector210.

The control unit230is connected to the detector210for providing a plurality of control signals to the detector210, wherein the plurality of control signals are configured to control a detection operation of the detector210.

Further, the first memory cell201includes:the first fuse N-fuse and a first burn-in transistor M1 connected in series between the power supply terminal and ground, and a connection node of the first fuse N-fuse and the first burn-in transistor M1 serves as a first node connecting to a first input of the detector210.

Further, the second memory cell202includes:the second fuse P-fuse and a second burn-in transistor M2 connected in series between the power supply terminal and ground, and a connection node of this second fuse P-fuse and the second burn-in transistor M2 serves as a second node connecting to a second input of the detector210.

Further, burn-in signals include a first burn-in signal Burn_n and a second burn-in signal Burn_p, wherein the first bum-in signal Burn_n is provided to a control terminal of the first burn-in transistor M1 for controlling a burn-in operation of the first fuse N-fuse, and the second burn-in signal Burn_p is provided to a control terminal of the second bum-in transistor M2 for controlling a bum-in operation of the second fuse P-fuse.

Further, the detector210includes:a first switch SW1, a first transistor M3 and a first current source I1 connected in series between the first node and ground, a connection node X of the first transistor M3 and the first current source I1 serving as a first output of the detector210for providing a first detection signal;a second switch SW2, a second transistor M4 and a second current source I2 connected in series between the second node and ground, a connection node Y of the second transistor M4 and the second current source I2 serving as a second output of the detector210for providing a second detection signal.

As shown inFIG.3, the detector210further includes: a third switch SW3, a fourth switch SW4, a fifth switch SW5, a sixth switch SW6 and a seventh switch SW7.

Wherein, the third switch SW3 is connected between a control terminal of the first transistor M3 and a control terminal of the second transistor M4; the fourth switch SW4 is connected between a connection node of the third switch SW3 and the first transistor M3 and ground; the fifth switch SW5 is connected between a connection node of the third switch SW3 and the second transistor M4 and ground; the sixth switch SW6 is connected between the connection node of the third switch SW3 and the first transistor M3 and the first output; the seventh switch SW7 is connected between the connection node of the third switch SW3 and the second transistor M4 and the second output.

In the embodiment, the plurality of control signals include: a first control signal Rd1, a second control signal Rd2 (the same as the first control signal Rd1 for simultaneous control of connection of the first fuse N-fuse to the first transistor M3 and connection of the second fuse P-fuse to the second transistor M4), a third control signal NMod_sw, a fourth control signal Brside_p, a fifth control signal Brside_n, a sixth control signal Side_p and a seventh control signal Side_n.

Wherein, the first control signal Rd1 is configured to logically control on-off state of the first switch SW1; the second control signal Rd2 is configured to logically control an on-off state of the second switch SW2; the third control signal NMod_sw is configured to logically control an on-off state of the third switch SW3; the fourth control signal Brside_p is configured to logically control an on-off state of the fourth The fourth control signal Brside_p is configured to logically control an on-off state of the fourth switch SW4; the fifth control signal Brside_n is configured to logically control an on-off state of the fifth switch SW5; the sixth control signal Side_p is configured to logically control an on-off state of the sixth switch SW6; the seventh control signal Side_n is configured to logically control an on-off state of the seventh switch SW7.

Further, the first switch SW1 and the second switch SW2 are in the off state, and the first burn-in transistor M1 and the second burn-in transistor M2 are continuously on for a period of time, so that the first fuse N-fuse or the second fuse P-fuse completes the burn-in operation.

Then, the first switch SW1, the second switch SW2, the third switch SW3 and the sixth switch SW6 are in the on state, and the fourth switch SW4, the fifth switch SW5 and the seventh switch SW7 are in the off state. In this case, the detector210is configured to detect the resistance difference between the first fuse N-fuse and the second fuse P-fuse.

Further, the first switch SW1, the second switch SW2, the fifth switch SW5 and the sixth switch SW6 are in the on state, and the third switch SW3, the fourth switch SW4 and the seventh switch SW7 are in the off state. In this case, the detector210is configured to detect the resistance value of the second fuse P-fuse.

Further, the first switch SW1, the second switch SW2, the fourth switch SW4 and the seventh switch SW7 are in the on state, and the third switch SW3, the fifth switch SW5 and the sixth switch SW6 are in the off state. In this case, the detector210is configured to detect the resistance value of the first fuse N-fuse.

Further, in the embodiment, the first current source I1 and the second current source12have the same configuration parameters, that is, I1=12, wherien I1 is a current value provided by the first current source I1, I2 is t a current value provided by the second current source12.

Referring toFIG.4, in this embodiment, the latch220includes, for example, a logic component221having a third input connected to the first output (node X) of the detector210and a fourth input connected to the second output (node Y) of the detector210, the logic component221generates the readout data (data) according to the first detection signal and the second detection signal.

Further, any one of the first burn-in transistor M1, the second burn-in transistor M2, the first switch transistor M3 and the second switch transistor M4 is a Metal Oxide Semiconductor Field-Effect Transistor (MOS transistor).

Further, the first burn-in transistor M1 and the second burn-in transistor M2 are both N-type MOS transistors, and the first switch transistor M3 and the second switch transistor M4 are both P-type MOS transistors. Of course, the disclosure is not limited to this, in other alternative embodiments, the first burn-in transistor M1 and the second burn-in transistor M2 may be P-type MOS transistors, and the first switch transistor M3 and the second switch transistor M4 may be N-type MOS transistors, and accordingly the burn-in signals (Burn_n and Bum_p) received by each of the control terminals of the first burn-in transistor M1 and the second burn-in transistor M2 will be changed, but it is also possible to read one of the resistance value of the first fuse N-fuse, the resistance value of the second fuse P-fuse, and the resistance difference between the first fuse N-fuse and the second fuse P-fuse by use of the detector210after the burn-in operation is completed.

As shown inFIGS.5dand5e, in one embodiment of this embodiment, the detector210may further include:a plurality of third current sources connected in parallel at both ends of the first current source I1, any one of the plurality of third current sources providing a current proportional to a current provided by the first current source I1; anda plurality of fourth current sources connected in parallel at both ends of the second current source12, any one of the plurality of fourth current sources providing a current proportional to a current provided by the second current source12.

Specifically, for example, the plurality of third current sources all provide the same current as the first current source I1, and the plurality of fourth current sources all provide the same current as the second current source12. By designing the current source of the detector210as a multi-stage configuration, a corresponding resistance value judgment threshold may also have a number of grades to choose from, so that a range of the resistance after the fuse “grows” may be more clearly defined.

FIG.5ashows an equivalent circuit diagram of the detector in the reading circuit shown inFIG.3when reading a resistance difference between fuses normally after a burn-in operation of fuse;FIG.5bshows an equivalent circuit diagram of the detector in the reading circuit shown inFIG.3when determining a resistance value of a second fuse after a burn-in operation of fuse;FIG.5cshows an equivalent circuit diagram of the detector in the reading circuit shown inFIG.3when determining a resistance value of a first fuse after a burn-in operation of fuse;FIG.5dshows an equivalent circuit diagram of the detector in the reading circuit shown inFIG.5bwhen determining a resistance value of a second fuse after a burn-in operation of fuse in a further embodiment;FIG.5eshows an equivalent circuit diagram of the detector in the reading circuit shown inFIG.5bwhen determining a resistance value of a first fuse after a burn-in operation of fuse in a further embodiment;FIG.5fshows a schematic table of true values of logic levels of each control signal and readout data corresponding to various read operations in an OTP memory after the read circuit shown inFIGS.5dand5eis burned-in.

Specifically, the read circuit203for differential OTP memory200provided in this embodiment has a logic level of 0 for the first control signal Rdp1 to the fourth control signal Brside_p during the burn-in operation of the differential OTP memory200, that is, the first switch SW1 to the fourth switch SW4 are off.

When the differential OTP memory200is to be burned-in with data 1, Rd1=Rd2=0, the logic level of the first burn-in signal Burn_n is 0, the logic level of the second burn-in signal Burn_p is 1, the first fuse N-fuse is not burned-in with a small resistance value, and the second fuse P-fuse is burned-in with a large resistance value.

When the differential OTP memory200is to be burned-in with data 0, Rd1=Rd2=0, the logic level of the first burn-in signal Burn_n is 1, the logic level of the second burn-in signal Burn_p is 0, the second fuse P-fuse is not burned-in with a small resistance value, and the first fuse N-fuse is burned-in with a large resistance value.

The read circuit203in the differential OTP memory200read operation is divided into following cases:

1) When the data data of this differential OTP memory200is read normally, the control unit230adjusts Rd1=Rd2=1, the third control signal NMod_sw=1, logic levels of the sixth control signal Side_p=1, the fourth control signal Brside_p, the seventh control signal Side_n and the fifth control signal Brside_n are both 0, an equivalent circuit of the reading circuit203is shown inFIG.5ain this case.

Referring toFIG.5a, the reading circuit203may be equated to an amplifier, and a small difference (about a few tens of ohms) between the resistance value of the second fuse P-fuse and he resistance value of the first fuse N-fuse in this case is amplified by the reading circuit203and output via node Y. When the second fuse P-fuse is burned, a voltage of node Y is lower than a voltage of node X since the resistance value of the second fuse P-fuse is greater than that of the first fuse N-fuse, and the logic level of readout data is 1; when the first fuse N-fuse is burned, the voltage of node Y is higher than that of node X since the resistance value of the first fuse N-fuse is greater than that of the second fuse P-fuse, and the logic level of readout data is 0.

In this embodiment, the resistance difference between the first fuse N-fuse and the resistance value of the second fuse P-fuse is reflected on node X and node Y, and is finally output as the readout data (data) by use of latch220(logic component221).

When the resistance value of the fuse is to be determined:a) If the resistance value of the second fuse P-fuse is to be determined, adjustRd1=Rd2=1, NMod_sw=0, Side_p=1, Brside_p=0, Side_n=0, Brside_n=1, and I1=I2, in this case the equivalent circuit of this reading circuit203is shown inFIG.5b.

The voltage of the node X is: VX≈VDD-I1*RN-VTHP.

The voltage of the node Y is: VY≈VDD-I1*R.

A voltage difference between node X and node Y is: VX-VY=I1*(RP-RN)-VTHP, where RP is the resistance value of the second fuse P-fuse, RN is the resistance value of the first fuse N-fuse, and VTHP is a threshold voltage corresponding to the resistance value judgment threshold, from which it may be seen that if RP-RN>VTHP/I1 and VY-VX<0, the logic level of data is 1, otherwise the logic level of data is 0. So that the reading circuit203may determine whether the resistance value of the second fuse P-fuse is greater than VTHP/I1, that is, the resistance value judgment threshold is VTHP/I1. For example, assuming that the threshold voltage VTHP is 0.9V, if I1 is designed to be30uA, then it may determine whether the resistance value of the second fuse P-fuse is greater than 30KΩ.b) If the resistance value of the first fuse N-fuse is to be determined, adjustRd1=Rd2=1, NMod_sw=0, Side_p=0, Brside_p=1, Side_n=1, Brside_n=0, I1=I2, in this case the equivalent circuit of this reading circuit203is shown inFIG.5c.

The same reference in the above mentioned a) may be obtained:

If RP-RN>VTHP/I1 and VY-VX>0, the logic level of data is 0, otherwise the logic level of data is 1. So that the reading circuit203may determine whether the resistance value of the first fuse N-fuse is greater than VTHP/I1.

3) Multi-file reading of the resistance value of the fuse

Reading the resistance value of the fuse (first fuse N-fuse or second fuse P-fuse) is to confirm that the resistance value (tens of KΩ or more) after the fuse “grows” is still far from the judgment resistance value (tens of Ω) normally read by the differential OTP memory200, and furthermore, in order to make the differential OTP memory200is accurate and reliable. In the application process, the current source in the reading circuit203may be designed to be multi-stage configurable, as shown inFIGS.5dand5e, and the corresponding resistance value judgment threshold VTHP/I1 may also have many grades, so that the range of the resistance value after the fuse “grows” may be clarified.

For example, assuming that the threshold voltage VTHP is 0.9V, if the first current source I1 with the plurality of third current sources may be configured as 15 uA, 30 uA or 60 uA, the resistance threshold may be determined as 60KΩ, 30KΩ or 15KΩ.

Combining the cases of various read operations after the bum-in of this differential OTP memory200is completed, a schematic table of the corresponding read-out data is given according to the logic level true value of each control signal in the corresponding various read operations, as shown inFIG.5f. Among them, OTP_TH 00 is the normal readout data mode; OTP_TH 01 is the detection of fuse resistance threshold mode 1 (such as resistance threshold of 15KΩ), when the current source current is 2*I1 (or 2*I2); OTP_TH 10 is the detection of fuse resistance threshold mode 2 (such as resistance threshold of 60KΩ), when the current source current is I1/2; OTP_SIDE is The logic level of the readout data is 0 to determine the resistance value of the first fuse N-fuse, and the logic level of the readout data is 1 to determine the resistance value of the second fuse P-fuse. The multi-satge configuration makes it possible to specify the range of the resistance value of the fuse of the reading circuit203after “growth”.

FIG.6ashows a schematic block diagram of a reading circuit for a differential OTP memory according to a second embodiment of the present disclosure;FIG.6bshows a structural schematic diagram of a detector in the reading circuit for the differential OTP memory shown inFIG.6a;FIG.7shows a structural schematic diagram of a latch in the reading circuit for the differential OTP memory shown inFIG.6a.

Referring toFIGS.6ato7, in the differential OTP memory300provided in the second embodiment of the present disclosure, similar to the first embodiment described above, the differential OTP memory300also includes: a first memory cell301and a second memory cell302in a differentially symmetrical structure, and the reading circuit303is connected between the first memory cell301and the second memory cell302and includes: a detector310, a latch320and a control unit330.

Wherein, the detector310has a first input connected to the first memory cell301and a second input connected to the second memory cell302, and is configured to detect the resistance value of the first fuse N-fuse located in the first memory cell301, the resistance value of the second fuse P-fuse located in the second memory cell302, and the resistance difference between the first fuse N-fuse and the second fuse P-fuse, after the burn-in operation of the first memory cell301or the second memory cell302is completed.

The latch320is configured to provide readout data (data) according to one of the resistance value of the first fuse N-fuse, the resistance value of the second fuse P-fuse and the resistance difference between the first fuse N-fuse and the second fuse P-fuse detected by this detector310.

The control unit330is connected to the detector310for providing a plurality of control signals to the detector310according to burn-in signals (Burn_n and Burn_p) controlling the burn-in operation, wherein the plurality of control signals are configured to control a detection operation of the detector310.

A basic structure of the read circuit303in this embodiment is similar to that of the previous embodiment, where the differential OTP memory300is burned to read out data data=1 or data=0 by burning the second fuse P-fuse or the first fuse N-fuse. However, unlike the differential OTP memory200and reading circuit203in the previous embodiment, the circuit of the detector310in this example reads the resistance value of the first fuse N-fuse and the resistance value of the second fuse P-fuse by changing connection between the first fuse N-fuse and the second fuse P-fuse and the reading circuit303.

In this embodiment, this first memory cell301includes:a first fuse N-fuse and a first burn-in transistor M1 connected in series between a power supply terminal and ground, and a connection node of the first fuse N-fuse and the first burn-in transistor M1 serves as a first node connecting to a first input of the detector310.

Further, the second memory cell302includes:a second fuse P-fuse and a second burn-in transistor M2 connected in series between the power supply terminal and ground, and a connection node of this second fuse P-fuse and the second burn-in transistor M2 serves as a second node connecting to a second input of the detector310.

Further, the burn-in signals include a first burn-in signal Burn_n and a second burn-in signal Burn_p, wherein the first burn-in signal Burn_n is provided to a control terminal of the first burn-in transistor M1 for controlling a burn-in operation of the first fuse N-fuse, and the second burn-in signal Burn_p is provided to a control terminal of the second burn-in transistor M2 for controlling a burn-in operation of the second fuse P-fuse.

In this embodiment, the detector310also includes:a first switch SW1, a first transistor M3 and a first current source I1 connected in series between the first node and ground, a connection node X of the first transistor M3 and the first current source I1 serving as a first output of the detector310for providing a first detection signal;a second switch SW2, a second transistor M4 and a second current source I2 connected in series between the second node and ground, a connection node Y of the second transistor M4 and the second current source I2 serving as a second output of the detector310for providing a second detection signal.

The first detection signal is configured to represent the resistance value of the first fuse N-fuse, and the second detection signal is configured to represent the resistance value of the second fuse P-fuse.

Referring toFIG.6b, different form the previous embodiment, the detector310further includes: a third switch SW3, a fourth switch SW4 and a fifth switch SW5.

Wherein, the third switch SW3 is connected between the first node and a first terminal of the second transistor M4, which is connected to the second switch SW2, and a second terminal is connected to the second current source12as the second output of the detector310; the fourth switch SW4 is connected between the second node and a first terminal of the first transistor M3, which is connected to the second current source12; the fourth switch SW4 is connected between the second node and a first terminal of the first transistor M3, which is connected to the first switch SW1, and a second terminal serves as the first output of the detector310connecting to the first current source I1, the second terminal of the first transistor M3 is connected to a control terminal of the first transistor M3, and the control terminal of the first transistor M3 is connected to a control terminal of the second transistor M4; the fifth switch SW5 is connected between a first terminal of the second transistor M4 and its The fifth switch SW5 is connected between the first terminal and the second terminal of the second transistor M4.

Further, the plurality of control signals include: a first control signal Rdp1, a second control signal Rdp2, a third control signal Rdn1, a fourth control signal Brside_p, and a fifth control signal Mod_sw.

Wherein, the first control signal Rdp1 is configured to control an on-off state of the first switch SW1; the second control signal Rdp2 is configured to control an on-off state of the second switch SW2; the third control signal Rdn1 is configured to control an on-off state of the third switch SW3; the fourth control signal Brside_p is configured to control an on-off state of the fourth switch SW4; the fifth control signal Mod_sw is configured to control an on-off state of the fifth switch SW5.

Further, the first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4 are off, and the first fuse M1 and the second fuse M2 are continuously on for a period of time, so that the first fuse N-fuse or the second fuse P-fuse completes the bum-in operation.

Then, the first switch SW1 and the second switch SW2 are on, and the third switch SW3, the fourth switch SW4 and the fifth switch SW5 are off, and the detector310is configured to detect the resistance difference between the first fuse N-fuse and the second fuse P-fuse.

Further, the first switch SW1, the second switch SW2 and the fifth switch SW5 are on, and the third switch SW3 and the fourth switch SW4 are off. In this case, the detector310is configured to detect the resistance value of the second fuse P-fuse.

Further, the third switch SW3, the fourth switch SW4 and the fifth switch SW5 are on, and the first switch SW1 and the second switch SW2 are off. In this case, the detector310is configured to detect the resistance value of the first fuse N-fuse.

Further, the first control signal Rdp1 is the same as the second control signal Rdp2, and the third control signal Rdn1 is the same as the fourth control signal Brside_p.

Further, in this embodiment, this first current source I1 and this second current source12have the same configuration parameters, i.e. I1=I2, wherein I1 is a current value provided by this first current source I1 and 12 is a current value provided by this second current source12.

Referring toFIG.7, in this embodiment the latch320comprises, for example, a logic component321, the third input of which is connected to the first output (node X) of the detector310, the fourth input of which is connected to the second output (node Y) of the detector310, the logic component321generating the readout according to the first detection signal and the second detection signal The logic controls the generation of the readout datadata.

As shown inFIG.8bandFIG.8c, in one embodiment of this embodiment, the detector310may further include:a plurality of third current sources connected in parallel at both ends of the first current source I1, any one of the plurality of third current sources providing a current proportional to a current provided by the first current source I1; anda plurality of fourth current sources connected in parallel at both ends of the second current source12, any one of the plurality of fourth current sources providing a current proportional to a current provided by the second current source12.

Specifically, for example, the plurality of third current sources all provide the same current as the first current source I1, and the plurality of fourth current sources all provide the same current as the second current source12. By designing the current source of the detector210as a multi-stage configuration, a corresponding resistance value judgment threshold may also have a number of grades to choose from, so that a range of the resistance after the fuse “grows” may be more clearly defined.

FIG.8ashows an equivalent circuit diagram of the detector in the reading circuit shown inFIG.6awhen reading a resistance difference between fuses normally after a burn-in operation of fuse;FIG.8bshows an equivalent circuit diagram of the detector in the reading circuit shown inFIG.6awhen determining a resistance value of a second fuse after a burn-in operation of fuse in a further embodiment;FIG.8cshows an equivalent circuit diagram of the detector in the reading circuit shown inFIG.6awhen determining a resistance value of a first fuse after a burn-in operation of fuse in a further embodiment;FIG.8dshows a schematic table of true values of logic levels of each control signal and readout data corresponding to various read operations in an OTP memory after the read circuit shown inFIGS.5dand5eis burned-in.

Specifically, the read circuit303provided in this embodiment for differential OTP memory300has a logic level of 0 for the first control signal Rdp1 to the fourth control signal Brside_p during the burn-in operation of the differential OTP memory300, that is, the first switch SW1 to the fourth switch SW4 are off:

When the differential OTP memory300is to be burned-in with data 1, a logic level of the first burn-in signal Burn_n is 0, a logic level of the second burn-in signal Burn_p is 1, the first fuse N-fuse is not burned with a small resistance value, and the second fuse P-fuse is burned with a large resistance value;

When the differential OTP memory300is to be burned-in with data 0, a logic level of the first burn-in signal Burn_n is 1, a logic level of the second burn-in signal Burn_p is 0, the second fuse P-fuse is not burned with a small resistance value, and the first fuse N-fuse is burned with a large resistance value.

The reading circuit303for the differential OTP memory300in the reading operation is divided into following cases:

1) When data (data) of this differential OTP memory300is read normally, the control unit330adjusts Rd1=Rd2=1, logic levels of the sixth control signal Side_p=1, logic levels of the third control signal Rdn1, the fourth control signal Brside_p and the fifth control signal mod_sw are both 0, and an equivalent circuit of the reading circuit303is shown inFIG.8ain this case.

Referring toFIG.8a, the reading circuit303may also be equated to an amplifier, and in this case, a small difference (about a few tens of ohms) between the resistance value of the second fuse P-fuse and the resistance value of the first fuse N-fuse is amplified by the reading circuit303and output via node Y. When the second fuse P-fuse is burned, the voltage of node Y is lower than the voltage of node X because the resistance value of the second fuse P-fuse is greater than that of the first fuse N-fuse, and a logic level of readout data is 1; when the first fuse N-fuse is burned, the voltage of node Y is higher than that of node X since the resistance value of the first fuse N-fuse is greater than that of the second fuse P-fuse, and a logic level of readout data is 1. The voltage of node Y is higher than the voltage of node X, and a logic level of the readout data (data) is 0.

In this embodiment, the resistance difference between the first fuse N-fuse and the second fuse P-fuse is reflected on node X and node Y, and is finally output as the readout data (data) by use of latch320(logic component321).

When the resistance value of the fuse is to be determined (refer to the multi-stage reading process of the resistance value of the fuse in the previous embodiment):a) If the resistance value of the second fuse P-fuse is to be determined, adjustRdp1=Rdp2=1, Rdn1=Rdn2=0, mod_sw=1, I1=I2, in this case the equivalent circuit of this reading circuit303is shown inFIG.8b.

Similarly, referring to the operation of each node voltage in the scenario shown inFIG.5babove, we may get here

If RP-RN>VTHP/I1 and VY-VX<0, the logic level of data is 1, otherwise the logic level of data is 0. So that the reading circuit303may determine whether the resistance value of the second fuse P-fuse is greater than VTHP/I1.b) If the resistance value of the first fuse N-fuse is to be determined, adjustRdp1=Rdp2=0, Rdn1=Rdn2=1, mod_sw=1, and I1=I2, in this case, the equivalent circuit of this reading circuit303is shown inFIG.8c.

It may be seen that the positions of the second fuse P-fuse and the first fuse N-fuse are interchanged, so

If RN-RP>VTHP/I1 and VY-VX<0, the logic level of data is 1, otherwise the logic level of data is 0. Thus, the reading circuit303may determine whether the resistance value of the first fuse N-fuse is greater than VTHP/I1.

It is important to understand that reading the resistance value of the fuse (first fuse N-fuse or second fuse P-fuse) is to confirm that the resistance value (tens of KΩ or more) after the fuse “grows” is still far from the judgment resistance value (tens of Q) that the differential OTP memory300reads normally, and furthermore, in order to make the Further, in order to make the data read normally by the differential OTP memory300accurate and reliable. In the application process, the current source in the reading circuit303may be designed as multi-stage configurable, as shown inFIGS.8band8c, and the corresponding resistance value judgment threshold VTHP/I1 will also have many grades, so that the range of the resistance value after the fuse “grows” may be clear.

After the completion of the differential OTP memory300, the various read operations are combined, and the corresponding readout data is given according to the true value of the logic level of each control signal in the various read operations, as shown inFIG.8d. Among them, OTP_TH 00 is the normal readout data mode; OTP_TH 01 is the detection of fuse resistance threshold mode 1 (such as resistance threshold of 15KΩ), when the current source current is 2*I1 (or 2*I2); OTP_TH 10 is the detection of fuse resistance threshold mode 2 (such as resistance threshold of 60KΩ), when the current source current is I1/2; OTP_SIDE is The logic level of the readout data is 0 to determine the resistance value of the first fuse N-fuse, and the logic level of the readout data is 1 to determine the resistance value of the second fuse P-fuse. The multi-stage configuration makes it possible to clarify the range of the resistance value of the fuse of the reading circuit303after “growth”.

In summary, the embodiments of the present disclosure provide a reading circuit for differential OTP memory, which includes a first memory cell and a second memory cell in a differentially symmetrical structure, and the reading circuit is connected between the first memory cell and the second memory cell and includes: a detector having a first input connected to the first memory cell and a second input connected to the second memory cell, configured to detect one of a resistance value of a first fuse of the first memory cell, a resistance value of a second fuse of the second memory cell and a resistance difference between the first fuse and the second fuse after a burn-in operation of the first memory or the second memory is completed; and a latch connected to the detector, configured to provide a readout data according to one of the resistance value of the first fuse, the resistance value of the second fuse and the resistance difference between the first fuse and the second fuse detected by the detector. The reading circuit for differential OTP memory provided in each embodiment of the present disclosure may read out data normally and may detect the resistance value of the fuse to ensure accuracy and reliability of the readout data.

It should be noted that in the description of the present disclosure, it is to be understood that the terms “up”, “down”, “in”, etc., indicating orientation or location relationships, are used only to facilitate the description of the present disclosure and to simplify the description. They do not indicate or imply that the component or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore are not to be construed as limiting the present disclosure.

In addition, for purposes of this document, the terms “including”, “comprising” or any other variation thereof are intended to cover non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also other elements not expressly listed, or other elements not expressly listed, or elements that are inherent to such process, method, article, or apparatus. Without further limitation, the elements defined by the statement “including a . . . ” do not preclude the existence of additional identical elements in the process, method, article, or apparatus that include said elements.

Finally, it should be noted that, obviously, the above embodiments are examples only for the purpose of clearly illustrating the present disclosure and are not meant to limit the manner of implementation. For those of ordinary skill in the art, there are other variations or changes that may be made in different forms based on the above description. It is not necessary or possible to exhaust all embodiments here. The obvious variations or changes derived therefrom are still within the scope of protection of the present disclosure.