Patent ID: 12220992

DETAILED DESCRIPTION OF EMBODIMENTS

Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the features, as claimed. As used herein, the terms “comprises,” “comprising,” “has,” “having,” “includes,” “including,” or other variations thereof, are intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements, but may include other elements not expressly listed or inherent to such a process, method, article, or apparatus. In this disclosure, unless stated otherwise, relative terms, such as, for example, “about,” “substantially,” and “approximately” are used to indicate a possible variation of ±10% in the stated value. In this disclosure, unless stated otherwise, any numeric value may include a possible variation of ±10% in the stated value.

The terminology used below may be interpreted in its broadest reasonable manner, even though it is being used in conjunction with a detailed description of certain specific examples of the present disclosure. Indeed, certain terms may even be emphasized below; however, any terminology intended to be interpreted in any restricted manner will be overtly and specifically defined as such in this Detailed Description section. For example, in the context of the disclosure, the switching devices may be described as switches or devices, but may refer to any device for controlling the flow of power in an electrical circuit. For example, switches may be metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), insulated-gate bipolar transistors (IGBTs), or relays, for example, or any combination thereof, but are not limited thereto.

Various embodiments of the present disclosure relate generally to systems and methods for an adaptive gate driver for an inverter for an electric vehicle, and, more particularly, to systems and methods for an adaptive gate driver for a power device switch for an inverter for an electric vehicle.

Inverters, such as those used to drive a motor in an electric vehicle, for example, are responsible for converting High Voltage Direct Current (HVDC) into Alternating Current (AC) to drive the motor. A three phase inverter may include a bridge with six power device switches (for example, power transistors such as IGBT or MOSFET) that are controlled by Pulse Width Modulation (PWM) signals generated by a controller. An inverter may include three phase switches to control the phase voltage, upper and lower gate drivers to control the switches, a PWM controller, and glue logic between the PWM controller and the gate drivers. The PWM controller may generate signals to define the intended states of the system. The gate drivers may send the signals from the PWM controller to the phase switches. The phase switches may drive the phase voltage. The inverter may include an isolation barrier between low voltage and high voltage planes. Signals may pass from the PWM controller to the phase switches by passing across the isolation barrier, which may employ optical, transformer-based, or capacitance-based isolation. PWM signals may be distorted when passing through the glue logic, which may include resistive, capacitive, or other types of filtering. PWM signals may be distorted when passing through the gate driver, due to the galvanic isolation barrier and other delays within the gate driver. PWM signals may be distorted when the signals processed by the phase switch via the gate driver output.

Gate drivers may tolerate common-mode transients that occur during field-effect transistor (FET) switching and when one side of the floating high voltage terminal is shorted to ground or subject to an electro-static discharge. These voltage transients may result in fast edges, which may create bursts of common-mode current through the galvanic isolation. A gate driver may need to demonstrate common-mode transient immunity (CMTI) in order to be effective and safe.

Gate drivers may have a high-voltage domain in common to the voltage plane of an associated FET. Further, high-voltage planes may be supplied by a flyback converter that may be isolated through a transformer from the low-voltage plane. The high-voltage domain supply may be used to power circuits which source and sink gate current to drive the FET and which may detect FET faults so the faults can be acted upon and/or communicated to the low-voltage domain. Gate drivers may include a galvanic channel dedicated to FET commands, and one or more bidirectional or unidirectional galvanic channels dedicated to FET communications.

High current switching transients may create strong electro-magnetic (EM) fields that may couple into nearby metal traces. The magnitude and frequency of coupled currents may depend upon the layout of the FET packaging solution and the direction and length of metal traces between the FET and the control integrated circuit (IC). For example, typical values for coupled currents may be up to 1 A at AC frequencies up to 100 MHz. Typically, within a circuit, the gate driver IC may be placed far enough away from the FET that high EM fields do not couple directly into the internal metal traces within the gate driver IC. The gate driver is placed a distance from EM fields such that induced currents within the circuitry are below levels that will cause malfunction of the gate driver, or a metal shield is placed between the gate driver and the source of EM fields to protect the gate driver circuitry. The output terminals of the gate driver that connect to the FET are exposed to the EM fields at the point where the output terminals are no longer covered by a shield. The gate driver switches large currents (such as5A to15A, for example) through these exposed terminals. The switched large currents are generally greater in magnitude than the EM-induced currents. The gate driver is able to overdrive the induced currents to maintain control of the FETs. The high side of the gate drivers and the FET may share a common ground and a gate control signal trace, both of which may be susceptible to coupled currents.

Gate drivers may turn on low-resistance switches to source and sink gate currents. Series resistors may sometimes be added to limit gate current. Switched gate currents may be larger than coupled currents in order to maintain control of their respective FETs.

Gate drivers may be able to sense FET operating voltages or currents in order to provide feedback and react to faults. Over-current faults may typically be detected by sensing the FET drain to source voltage and comparing the sensed voltage to a reference value. Sensed voltages may be heavily filtered to reject coupled currents. Filtering may slow down the response to fault conditions, resulting in delays in response. For example, the rate of current increase due to a low resistance short circuit may reach damaging levels prior to being detected by the heavily filtered drain to source voltage detection strategy. The resulting short circuit may damage the FET or the vehicle, prior to being detected and shut off.

According to one or more embodiments, a FET driver circuit may provide rapid over-current detection by either shunt current sensing or by diverting a fraction of the load current through a parallel FET that may have a current sensing circuit. Utilizing either strategy may require a “point-of-use IC” where sensing circuitry is in close proximity to the FET. Even if a point-of-use IC and a remote controller are resistant to EM fields, communication between the point-of-use IC and remote controller remains susceptible to induced currents. Point-of-use ICs have been implemented in low EM field applications, such as smart FETs for automotive applications. However, point-of-use ICs have not been used in high EM field applications. A high EM field may be a field (i) that induces a current within an IC that is in excess of an operating current of the IC and leads to malfunction, or (ii) that induces a differential voltage within an IC which is in excess of the operating differential voltage and leads to malfunction. A high EM field may be a field that is greater than approximately 10 A or approximately 100V, for example.

As discussed above, for a phase power drive circuit, some circuits may include a gate driver to drive the gates terminals of the power switches. When both upper phase and lower phase power switches are the same type, then turn-on resistors for the upper phase and lower phase power switches are normally chosen to have low and equal resistance values, and turn-off resistors for the upper phase and lower phase power switches also have low and equal resistance values. The turn-on resistors normally have different resistance values than the turn-off resistors. To avoid shoot-through current in the upper phase and lower phase power switches, some circuits include a dead-time between the upper phase power switch turn-off and lower phase power switch turn-on times, and between lower phase power switch turn-off and upper phase power switch turn-on times. The switching losses of the power switches are directly determined by the values of the above-mentioned gate resistors and the total capacitance at the gate terminals of the power switches.

The values of these series gate resistors are chosen such that the turn-on gate voltage and drain current amplitude ringing and the turn-off drain to source voltage overshoot and ringing amplitude does not exceed the allowed maximum values under worst-case conditions. The worst-case conditions may include intrinsic parameters of the power switches, operating temperature, phase (load) current amplitude/slope, battery voltage magnitude, and parameter drift over the life of the power switches due to aging of the components. Any violation of the compliance voltage and current values may compromise the health of the power switches, and potentially cause permanent damage to the power switches. Therefore, the values of the gate resistors are increased to a suitable value higher than optimal resistance values so that the power switches do not experience any undue voltage and/or current stresses. However, the choice of higher values for the gate resistors significantly increases the switching losses of the power switches, which results in higher heat-sink and overall system costs.

One or more embodiments may provide a gate driver system that significantly reduces switching power losses while protecting the power switches with regard to the gate voltage and drain current ringing amplitude and the drain to source voltage overshoot and ringing amplitude. One or more embodiments may provide a gate driver system that computes optimum gate-drive turn-on and turn-off voltage profiles that incorporates intrinsic characteristics of power devices, load-current slope and amplitude, high-voltage battery amplitude, and operating temperature. One or more embodiments may provide a gate driver system that continuously measures threshold voltage drift over time of a power device, which may be used in the computation of the optimum gate-drive turn-on and turn-off voltage profiles, and in the detection of an open gate terminal fault. One or more embodiments may provide a gate driver system that uses a hybrid variable resistive driver along with fast transition switch-mode circuit, featuring a very low driving impedance for minimizing the switching turn-on and turn-off current and/or voltage ringing, while shortening the transition time to the full conduction time window. One or more embodiments may provide a gate driver system that continuously detects hard and/or soft short and/or open faults throughout the switching turn-on, turn-off, and conduction periods by continuously checking the gate voltage amplitude and rate of change of the gate voltage over time against several threshold voltages and pre-programmed time windows. One or more embodiments may provide a gate driver system that, for the case of turning on into hard short, computes a special turn-off profile to assure a safe turn-off of the power switch.

FIG.1depicts an exemplary system infrastructure for a vehicle including a combined inverter and converter, according to one or more embodiments. In the context of this disclosure, the combined inverter and converter may be referred to as an inverter. As shown inFIG.1, electric vehicle100may include an inverter110, a motor190, and a battery195. The inverter110may include components to receive electrical power from an external source and output electrical power to charge battery195of electric vehicle100. The inverter110may convert DC power from battery195in electric vehicle100to AC power, to drive motor190of the electric vehicle100, for example, but the embodiments are not limited thereto. The inverter110may be bidirectional, and may convert DC power to AC power, or convert AC power to DC power, such as during regenerative braking, for example. Inverter110may be a three-phase inverter, a single-phase inverter, or a multi-phase inverter.

FIG.2depicts an exemplary system infrastructure for the inverter110ofFIG.1with a point-of-use switch controller, according to one or more embodiments. Electric vehicle100may include inverter110, motor190, and battery195. Inverter110may include an inverter controller300(shown inFIG.3) to control the inverter110. Inverter110may include a low voltage upper phase controller120separated from a high voltage upper phase controller130by a galvanic isolator150, and an upper phase power module140. Upper phase power module140may include a point-of-use upper phase controller142and upper phase switches144. Inverter110may include a low voltage lower phase controller125separated from a high voltage lower phase controller135by galvanic isolator150, and a lower phase power module145. Lower phase power module145may include a point-of-use lower phase controller146and lower phase switches148. Upper phase switches144and lower phase switches148may be connected to motor190and battery195. Galvanic isolator150may be one or more of optical, transformer-based, or capacitance-based isolation. Galvanic isolator150may be one or more capacitors with a value from approximately 20 fF to approximately 100 fF, with a breakdown voltage from approximately 6 kV to approximately 12 kV, for example. Galvanic isolator150may include a pair of capacitors, where one capacitor of the pair carries a complementary (180 degree phase shifted) data signal from the other capacitor of the pair to create a differential signal for common-mode noise rejection. Galvanic isolator150may include more than one capacitor in series. Galvanic isolator150may include one capacitor located on a first IC, or may include a first capacitor located on a first IC and a second capacitor located on a second IC that communicates with the first IC.

Inverter110may include a low voltage area, where voltages are generally less than 5V, for example, and a high voltage area, where voltages may exceed 500V, for example. The low voltage area may be separated from the high voltage area by galvanic isolator150. Inverter controller300may be in the low voltage area of inverter110, and may send signals to and receive signals from low voltage upper phase controller120. Low voltage upper phase controller120may be in the low voltage area of inverter110, and may send signals to and receive signals from high voltage upper phase controller130. Low voltage upper phase controller120may send signals to and receive signals from low voltage lower phase controller125. High voltage upper phase controller130may be in the high voltage area of inverter110. Accordingly, signals between low voltage upper phase controller120and high voltage upper phase controller130pass through galvanic isolator150. High voltage upper phase controller130may send signals to and receive signals from point-of-use upper phase controller142in upper phase power module140. Point-of-use upper phase controller142may send signals to and receive signals from upper phase switches144. Upper phase switches144may be connected to motor190and battery195. Upper phase switches144and lower phase switches148may be used to transfer energy from motor190to battery195, from battery195to motor190, from an external source to battery195, or from battery195to an external source, for example. The lower phase system of inverter110may be similar to the upper phase system as described above.

FIG.3depicts an exemplary system infrastructure for inverter controller300ofFIG.2, according to one or more embodiments. Inverter controller300may include one or more controllers.

The inverter controller300may include a set of instructions that can be executed to cause the inverter controller300to perform any one or more of the methods or computer based functions disclosed herein. The inverter controller300may operate as a standalone device or may be connected, e.g., using a network, to other computer systems or peripheral devices.

In a networked deployment, the inverter controller300may operate in the capacity of a server or as a client in a server-client user network environment, or as a peer computer system in a peer-to-peer (or distributed) network environment. The inverter controller300can also be implemented as or incorporated into various devices, such as a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile device, a palmtop computer, a laptop computer, a desktop computer, a communications device, a wireless telephone, a land-line telephone, a control system, a camera, a scanner, a facsimile machine, a printer, a pager, a personal trusted device, a web appliance, a network router, switch or bridge, or any other machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. In a particular implementation, the inverter controller300can be implemented using electronic devices that provide voice, video, or data communication. Further, while the inverter controller300is illustrated as a single system, the term “system” shall also be taken to include any collection of systems or sub-systems that individually or jointly execute a set, or multiple sets, of instructions to perform one or more computer functions.

As shown inFIG.3, the inverter controller300may include a processor302, e.g., a central processing unit (CPU), a graphics processing unit (GPU), or both. The processor302may be a component in a variety of systems. For example, the processor302may be part of a standard inverter. The processor302may be one or more general processors, digital signal processors, application specific integrated circuits, field programmable gate arrays, servers, networks, digital circuits, analog circuits, combinations thereof, or other now known or later developed devices for analyzing and processing data. The processor302may implement a software program, such as code generated manually (i.e., programmed).

The inverter controller300may include a memory304that can communicate via a bus308. The memory304may be a main memory, a static memory, or a dynamic memory. The memory304may include, but is not limited to computer readable storage media such as various types of volatile and non-volatile storage media, including but not limited to random access memory, read-only memory, programmable read-only memory, electrically programmable read-only memory, electrically erasable read-only memory, flash memory, magnetic tape or disk, optical media and the like. In one implementation, the memory304includes a cache or random-access memory for the processor302. In alternative implementations, the memory304is separate from the processor302, such as a cache memory of a processor, the system memory, or other memory. The memory304may be an external storage device or database for storing data. Examples include a hard drive, compact disc (“CD”), digital video disc (“DVD”), memory card, memory stick, floppy disc, universal serial bus (“USB”) memory device, or any other device operative to store data. The memory304is operable to store instructions executable by the processor302. The functions, acts or tasks illustrated in the figures or described herein may be performed by the processor302executing the instructions stored in the memory304. The functions, acts or tasks are independent of the particular type of instructions set, storage media, processor or processing strategy and may be performed by software, hardware, integrated circuits, firm-ware, micro-code and the like, operating alone or in combination. Likewise, processing strategies may include multiprocessing, multitasking, parallel processing and the like.

As shown, the inverter controller300may further include a display310, such as a liquid crystal display (LCD), an organic light emitting diode (OLED), a flat panel display, a solid-state display, a cathode ray tube (CRT), a projector, a printer or other now known or later developed display device for outputting determined information. The display310may act as an interface for the user to see the functioning of the processor302, or specifically as an interface with the software stored in the memory304or in the drive unit306.

Additionally or alternatively, the inverter controller300may include an input device312configured to allow a user to interact with any of the components of inverter controller300. The input device312may be a number pad, a keyboard, or a cursor control device, such as a mouse, or a joystick, touch screen display, remote control, or any other device operative to interact with the inverter controller300.

The inverter controller300may also or alternatively include drive unit306implemented as a disk or optical drive. The drive unit306may include a computer-readable medium322in which one or more sets of instructions324, e.g. software, can be embedded. Further, the instructions324may embody one or more of the methods or logic as described herein. The instructions324may reside completely or partially within the memory304and/or within the processor302during execution by the inverter controller300. The memory304and the processor302also may include computer-readable media as discussed above.

In some systems, a computer-readable medium322includes instructions324or receives and executes instructions324responsive to a propagated signal so that a device connected to a network370can communicate voice, video, audio, images, or any other data over the network370. Further, the instructions324may be transmitted or received over the network370via a communication port or interface320, and/or using a bus308. The communication port or interface320may be a part of the processor302or may be a separate component. The communication port or interface320may be created in software or may be a physical connection in hardware. The communication port or interface320may be configured to connect with a network370, external media, the display310, or any other components in inverter controller300, or combinations thereof. The connection with the network370may be a physical connection, such as a wired Ethernet connection or may be established wirelessly as discussed below. Likewise, the additional connections with other components of the inverter controller300may be physical connections or may be established wirelessly. The network370may alternatively be directly connected to a bus308.

While the computer-readable medium322is shown to be a single medium, the term “computer-readable medium” may include a single medium or multiple media, such as a centralized or distributed database, and/or associated caches and servers that store one or more sets of instructions. The term “computer-readable medium” may also include any medium that is capable of storing, encoding, or carrying a set of instructions for execution by a processor or that cause a computer system to perform any one or more of the methods or operations disclosed herein. The computer-readable medium322may be non-transitory, and may be tangible.

The computer-readable medium322can include a solid-state memory such as a memory card or other package that houses one or more non-volatile read-only memories. The computer-readable medium322can be a random-access memory or other volatile re-writable memory. Additionally or alternatively, the computer-readable medium322can include a magneto-optical or optical medium, such as a disk or tapes or other storage device to capture carrier wave signals such as a signal communicated over a transmission medium. A digital file attachment to an e-mail or other self-contained information archive or set of archives may be considered a distribution medium that is a tangible storage medium. Accordingly, the disclosure is considered to include any one or more of a computer-readable medium or a distribution medium and other equivalents and successor media, in which data or instructions may be stored.

In an alternative implementation, dedicated hardware implementations, such as application specific integrated circuits, programmable logic arrays and other hardware devices, can be constructed to implement one or more of the methods described herein. Applications that may include the apparatus and systems of various implementations can broadly include a variety of electronic and computer systems. One or more implementations described herein may implement functions using two or more specific interconnected hardware modules or devices with related control and data signals that can be communicated between and through the modules, or as portions of an application-specific integrated circuit. Accordingly, the present system encompasses software, firmware, and hardware implementations.

The inverter controller300may be connected to a network370. The network370may define one or more networks including wired or wireless networks. The wireless network may be a cellular telephone network, an 802.11, 802.16, 802.20, or WiMAX network. Further, such networks may include a public network, such as the Internet, a private network, such as an intranet, or combinations thereof, and may utilize a variety of networking protocols now available or later developed including, but not limited to TCP/IP based networking protocols. The network370may include wide area networks (WAN), such as the Internet, local area networks (LAN), campus area networks, metropolitan area networks, a direct connection such as through a Universal Serial Bus (USB) port, or any other networks that may allow for data communication. The network370may be configured to couple one computing device to another computing device to enable communication of data between the devices. The network370may generally be enabled to employ any form of machine-readable media for communicating information from one device to another. The network370may include communication methods by which information may travel between computing devices. The network370may be divided into sub-networks. The sub-networks may allow access to all of the other components connected thereto or the sub-networks may restrict access between the components. The network370may be regarded as a public or private network connection and may include, for example, a virtual private network or an encryption or other security mechanism employed over the public Internet, or the like.

In accordance with various implementations of the present disclosure, the methods described herein may be implemented by software programs executable by a computer system. Further, in an exemplary, non-limited implementation, implementations can include distributed processing, component or object distributed processing, and parallel processing. Alternatively, virtual computer system processing can be constructed to implement one or more of the methods or functionality as described herein.

Although the present specification describes components and functions that may be implemented in particular implementations with reference to particular standards and protocols, the disclosure is not limited to such standards and protocols. For example, standards for Internet and other packet switched network transmission (e.g., TCP/IP, UDP/IP, HTML, HTTP) represent examples of the state of the art. Such standards are periodically superseded by faster or more efficient equivalents having essentially the same functions. Accordingly, replacement standards and protocols having the same or similar functions as those disclosed herein are considered equivalents thereof.

It will be understood that the operations of methods discussed are performed in one embodiment by an appropriate processor (or processors) of a processing (i.e., computer) system executing instructions (computer-readable code) stored in storage. It will also be understood that the disclosure is not limited to any particular implementation or programming technique and that the disclosure may be implemented using any appropriate techniques for implementing the functionality described herein. The disclosure is not limited to any particular programming language or operating system.

FIG.4depicts an exemplary system infrastructure for the point-of-use switch controller ofFIG.2, according to one or more embodiments. For a three-phase inverter, each of the upper phase and the lower phase may include three phases correlating with phases A, B, and C. For example, upper phase power module140may include upper phase power module140A for upper phase A, upper phase power module140B for upper phase B, and upper phase power module140C for upper phase C. Upper phase power module140A may include point-of-use upper phase A controller142A and upper phase A switches144A. Upper phase power module140B may include point-of-use upper phase B controller142B and upper phase B switches144B. Upper phase power module140C may include point-of-use upper phase C controller142C and upper phase C switches144C. Each of the upper phase A switches144A, upper phase B switches144B, and upper phase C switches144C may be connected to motor190and battery195.FIG.4depicts details of the upper phase power module140. Although not shown, the lower phase power module145may include a similar structure as the upper phase power module140for lower phases A, B, and C.

FIG.5depicts an exemplary system infrastructure for the upper power module ofFIG.4, according to one or more embodiments. For example,FIG.5provides additional details of upper phase power module140A. Although not shown, upper phase power module140B, upper phase power module140C, and respective lower phase power modules of lower phase power module145may include a similar structure as the upper phase power module140A shown inFIG.5. Moreover, the terms upper, lower, north, and south used in the disclosure are merely for reference, do not limit the elements to a particular orientation, and are generally interchangeable throughout. For example, the upper phase power module140could be referred to a lower phase power module, a north phase power module, a south phase power module, a first phase power module, or a second phase power module.

Upper phase power module140A may include point-of-use upper phase A controller142A and upper phase A switches144A. Upper phase A switches144A may include one or more groups of switches. As shown inFIG.5, upper phase A switches144A may include upper phase A north switches144A-N and upper phase A south switches144A-S. Point-of-use upper phase A controller142A may include one or more memories, controllers, or sensors. For example, point-of-use upper phase A controller142A may include a communication manager405, a functional safety controller410, a testing interface and controller415, a north thermal sensor420A, a south thermal sensor420B, a self-test controller425, a command manager430, a waveform adjuster435, a memory440, north switches control and diagnostics controller450N, and south switches control and diagnostics controller450S. Point-of-use upper phase A controller142A may include more or less components than those shown inFIG.5. For example, point-of-use upper phase A controller142A may include more or less than two switch control and diagnostics controllers, and may include more than two thermal sensors.

Communication manager405may control inter-controller communications to and from point-of-use upper phase A controller142A and/or may control intra-controller communications between components of point-of-use upper phase A controller142A. Functional safety controller410may control safety functions of point-of-use upper phase A controller142A. Testing interface and controller415may control testing functions of point-of-use upper phase A controller142A, such as end-of-line testing in manufacturing, for example. North thermal sensor420A may sense a temperature at a first location in point-of-use upper phase A controller142A, and south thermal sensor420B may sense a temperature at a second location in point-of-use upper phase A controller142A. Self-test controller425may control a self-test function of point-of-use upper phase A controller142A, such as during an initialization of the point-of-use upper phase A controller142A following a power on event of inverter110, for example. Command manager430may control commands received from communication manager405issued to the north switches control and diagnostics controller450N and south switches control and diagnostics controller450S. Waveform adjuster435may control a waveform timing and shape of commands received from communication manager405issued to the north switches control and diagnostics controller450N and south switches control and diagnostics controller450S. Memory440may include one or more volatile and non-volatile storage media for operation of point-of-use upper phase A controller142A. North switches control and diagnostics controller450N may send one or more signals to north switches144A-N to control an operation of north switches144A-N, and may receive one or more signals from north switches144A-N that provide information about north switches144A-N. South switches control and diagnostics controller450S may send one or more signals to south switches144A-S to control an operation of south switches144A-S, and may receive one or more signals from south switches144A-S that provide information about south switches144A-S. As stated above, the terms north and south are merely used for reference, and north switches control and diagnostics controller450N may send one or more signals to south switches144A-S, and south switches control and diagnostics controller450S may send one or more signals to south switches144A-N.

FIG.6depicts an exemplary system for a current-based adaptive gate driver for a power device switch, according to one or more embodiments.

One or more embodiments may provide a gate driver system to significantly reduce switching power losses while protecting against concerns regarding the gate voltage and drain current ringing amplitude and the drain-to-source voltage over-shoot and ringing amplitude discussed above.

With reference toFIG.2, for example, gate driver system600may be an implementation of upper phase power module140and lower phase power module145. As shown inFIG.6, upper phase power switch644(M2) may be connected to a positive terminal695P of battery195and a phase terminal690A (e.g. phase A) of motor190, and lower phase power switch648(M1) may be connected to a negative terminal695N of battery195and a phase terminal690A of motor190. For example, upper phase power switch644may be an implementation of one of upper phase switches144(e.g. upper phase A switches144A), and lower phase power switch648may be an implementation of one of lower phase switches148.

The gate terminal of lower phase power switch648may be driven, based on lower phase driving signal635, with varying source current drivers615and varying sink gate current drivers616. Isrc1through Isrcn may be source current drivers615with varying values for the turn-on period, and Isnk1through Isnkn may be sink current drivers616with varying values for the turn-off period of the lower phase power switch648, respectively. Source current drivers615and sink gate current drivers616may be dynamically selected by operation of the respective φ switches based on the respective turn-on and turn-off control signals. The source current drivers615and sink gate current drivers616may be selected using sense and control methods, to be presented below, in order to drive the gate terminal of the lower phase power switch648to minimize the switching losses based on one or more of variation in intrinsic parameters of the lower phase power switch648, parameter drift over the life of lower phase power switch648, or operating temperature of lower phase power switch648.

As shown inFIG.6, both lower phase power switch648and upper phase power switch644may have an independent gate driver system. More specifically, the gate terminal of upper phase power switch644may be driven, based on upper phase driving signal630, with varying source current drivers610and varying sink gate current drivers611. Upper phase power switch644may include source current drivers610with varying values for the turn-on period, and sink current drivers611with varying values for the turn-off period of the upper phase power switch644. Source current drivers610and sink gate current drivers611may be dynamically selected by operation of the respective φ switches based on the respective turn-on and turn-off control signals. The source current drivers610and sink gate current drivers611may be selected using sense and control methods, to be presented below, in order to drive the gate terminal of the upper phase power switch644to minimize the switching losses based on one or more of variation in intrinsic parameters of the upper phase power switch644, parameter drift over the life of upper phase power switch644, or operating temperature of upper phase power switch644.

FIG.7depicts an exemplary system for a resistor-based adaptive gate driver for a power device switch, according to one or more embodiments.

As shown inFIG.7, gate driver system700may include turn-on and turn-off programmable profile resistors, in addition to or in place of the source and sink current drivers of gate driver system600. Gate driver system700may provide persistent low impedance to the gate terminals of upper phase power switch644and lower phase power switch648during respective turn-on and turn-off events, and may provide maximum impunity to high strength electromagnetic corrupting fields.

The gate terminal of lower phase power switch648may be driven, based on lower phase driving signal635, with varying turn-on resistors715and varying turn-off resistors716. Ron1through Ronm may be turn-on resistors715with varying values for the turn-on period, and Roff1through Roffm may be turn-off resistors716with varying values for the turn-off period of the lower phase power switch648, respectively. Turn-on resistors715and turn-off resistors716may be dynamically selected by operation of the respective φ switches based on the respective turn-on and turn-off control signals. The turn-on resistors715and turn-off resistors716may be selected using sense and control methods, to be presented below, in order to drive the gate terminal of the lower phase power switch648to minimize the switching losses based on one or more of variation in intrinsic parameters of the lower phase power switch648, parameter drift over the life of lower phase power switch648, or operating temperature of lower phase power switch648.

As shown inFIG.7, both lower phase power switch648and upper phase power switch644may have an independent gate driver system. More specifically, the gate terminal of lower phase power switch648may be driven, based on upper phase driving signal635, with varying turn-on resistors710and varying turn-off resistors711. Ron1through Ronm may be turn-on resistors710with varying values for the turn-on period, and Roff1through Roffm may be turn-off resistors711with varying values for the turn-off period of the upper phase power switch644, respectively. Turn-on resistors710and turn-off resistors711may be dynamically selected by operation of the respective φ switches based on the respective turn-on and turn-off control signals. The turn-on resistors710and turn-off resistors711may be selected using sense and control methods, to be presented below, in order to drive the gate terminal of the upper phase power switch644to minimize the switching losses based on one or more of variation in intrinsic parameters of the upper phase power switch644, parameter drift over the life of upper phase power switch644, or operating temperature of upper phase power switch644.

As shown inFIG.7, the gate driver system700may also include upper phase clamp switches712(SU and SL), and lower phase clamp switches717(SU and SL). Upper phase clamp switches712and lower phase clamp switches717may play a crucial role in the switching loss reduction of the respective upper phase power switch644and lower phase power switch648. The Rdson value of the clamp switches712and717are chosen to be many times lower than the respective minimum gate drive series resistance. Further description of the operation of upper phase clamp switches712and lower phase clamp switches717will be provided below.

FIG.8depicts an exemplary system for a resistor-based adaptive gate driver800with sensing and control for a power device switch, according to one or more embodiments. As shown inFIG.8, differential amplifiers G1, G2, and G3provide three different output signals to differential analog comparators A1, A2, A3, A4, and A5, which provide different output signals to AN1, AN2, AN3, and AN4logic AND gates. The second input of the AN1, AN2, AN3, and AN4logic AND gates are controlled by a group of logic signals named “Enable_Gate_Drive” signal, to load current profile signals, into a load register, for example, to sequentially activate each of the state0, state1, state2, state3, and state4current profiles of Isrc1through Isrcn gate sourcing currents (e.g. using turn-on resistors715and lower phase clamp switches717as shown, or using any of the gate driver configurations as shown inFIGS.6,7, and10) to turn on lower phase power switch648with an unique computed gate turn-on profile. This current profile signals achieve minimum turn-on switching power loss while precisely controlling the gate-voltage ringing, drain-current ringing, and drain-to-source voltage overshoot and ringing to protect lower phase power switch648from experiencing any undue current and voltage stresses. AlthoughFIG.8depicts the adaptive gate driver for lower phase power switch648, the adaptive gate driver for upper phase power switch644may be similar to the adaptive gate driver for lower phase power switch648.

The turn-on switching process may include various operations as described below.

The Command-ON signal851is first asserted to enable the “Enable_Gate_Drive” signal and load state0programmed gate-current/drive profile. This facilitates several resistors (e.g. turn-on resistors715), and/or in the case of a current driver, several current source units (e.g. source current drivers615) to be connected to the gate terminal of lower phase power switch648to initiate a gate voltage rise of lower phase power switch648. The G2amplifier may continuously monitor the gate-to-source voltage of lower phase power switch648.

The output of the G2amplifier may next be fed to a first input of each of the comparators A2, A3, and A4, of which a second input of each is fed by outputs of three N-bit digital-to-analog converters (DACs) including DAC_VTH0_L, DAC_VTH1_L, and DAC_VTH2_L. The outputs of these DACs may be programmed to set any desired threshold voltage to the inputs of A2, A3, and A4comparators, which may each perform a comparison using a respective output of the DACs. The threshold voltage of DAC_VTH2_L may be programmed to be higher than that of DAC_VTH1_L, which may be higher than that of DAC_VTH0_L. These threshold voltages may be required to be set before initiating the next gate-drive signal turn-on current profile.

As soon as the output of the G2amplifier crosses the programmed threshold voltage set by the output of DAC_VTH0_L, the A4output signal V_comp_0is asserted high to AN4, and a programmed gate-current/resistor profile of I_profile_state1(a stored value which is determined using the electrical models of the lower phase power switch648, operating temperature, and last cycle load current value) is then loaded to steer the gate voltage to further rise according to I_profile_state1with a sourcing time duration set to a pre-calculated time value of t1. The value “t1’ may be a computed time duration for I_profile_state1, and may be used to detect a short or an open fault. If the monitored time is appreciably shorter than the computed value of t1, then an open fault exists. If the monitored time is appreciably longer than the computed value of t1, then a short fault exists. The equation to calculate t1 is: t1=[(Cgs+Cgd (at high value of Vds).(Iload+Irmm)/(gfs. I_profile_state1)].TCF.ICF. Here, gfs is the transconductance, Cgs and Cgd are the gate-to-source and gate-to-drain capacitances of lower phase power switch648, Iload is load current flowing through lower phase power switch648, Irmm is the reverse recovery peak current of the lower phase power switch648body diode, TCF is a temperature correction factor, and ICF is a computed load-current correction factor. The value of t1 may also be computed in advance and stored to be used for the I_profile_state1turn-on timing and definition. Before the expiration of t1, the state of the A3output signal V_comp_1is first checked to assure a logic state is high. If the logic state of A3output signal V_comp_1is not high, then a fault has occurred. Alternatively or additionally, when an elapsed time from when I_profile_state1has been loaded is longer than t1, a fault may be asserted. For the case of very low package stray values, corresponding t1 timing values may be computed to be used in monitoring t1 mission-mode timings. If the monitored t1 timings are outside the computed timings, then that indicates that a fault may have occurred. For this case, as soon as the state of the A3output signal V_comp_1becomes asserted high to AN3, the profile of I_profile_state2is loaded which causes a further rise in the gate voltage.

Next, after the output of the G2amplifier has crossed the programmed threshold voltage set by the output of DAC_VTH1_L, the A3output signal V_comp_1is asserted high to AN3, and a programmed gate current/resistor profile of I_profile_state2(a stored value), is loaded to steer the gate voltage rise according to the I_profile_state2value whose sourcing time duration is set to a pre-calculated time value of t2. The value “t2’ may be a computed time duration for I_profile_state2, and may be used to detect a short or an open fault. If the monitored time is appreciably shorter than the computed value of t1, then an open fault exists. If the monitored time is appreciably longer than the computed value of t1, then a short fault exists. The equation to calculate t2 is: t2=[(Cgd(at low Vds).(Vbattery+Vforward_bias_bodydiode−Iload .rdson/I_profile_state2)].TCF.ICF. Before the expiration of t2, the state of the comparator A2output signal V_comp_2is first checked to assure a logic state is high. If the logic state of A2output signal V_comp_2is not high, then a fault has occurred. The value of t2 may also be computed in advance and stored to be used in the I_profile_state2turn-on timing and definition. Again, for the case of very low package stray values, corresponding t2 timing values may be computed to be used in monitoring t2 mission-mode timings. If the monitored t2 timings are outside the computed timings, then that indicates that a fault may have occurred. For this case, as soon as the state of the A2output signal V_comp_2becomes asserted high to AN2, the profile of I_profile_state3is loaded which causes a further rise in the gate voltage.

Next, when the state of the comparator A2output signal V_comp_2becomes logic high to AN2, then a programmed gate current profile of I_profile_state3(a stored value), is loaded to steer the gate voltage to further rise according to I_profile_state3.

As the gate voltage continues rising until the state of the comparator A1output, V_comp_3, becomes logic high to AN1, then a programmed gate current/resistor profile of I_profile_state4(a stored value), is loaded to steer the gate voltage to rise toward the positive supply of the gate-drive power supply. At this point, the turn-on profile process is complete and lower phase power switch648has become fully on. The role of G1is to measure the differential voltage of VPS_U or VPS_L with respect to the upper phase driving signal630(voltage) or lower phase driving signal635(voltage). This measured voltage is used against DAC_VPS_U or DAC_VPS_L to determine when the I_Profile_State4is to begin.

The turn-off process is initiated by asserting high the Command OFF signal852, which in turn loads programmed gate current/resistor profile I_profile state5. This turns off (immediately after the falling edge of the PWL signal) the turn-on resistors715and/or source current drivers615, and turns on several current sink (or resistor) units (e.g. turn-off resistors716and/or sink gate current drivers616) connected to the gate terminal of lower phase power switch648to initiate lowering of the gate voltage. At the moment that the output of the G2amplifier crosses the programmed threshold voltage set by the output of DAC_VTH2_L block, a programmed gate-current/resistor profile of I_profile_state6(a stored value which is determined from the electrical models of lower phase power switch648) is then loaded to steer the gate voltage to fall according to this current/resistor profile value whose sourcing time duration is set to a pre-calculated time value of t3. The digital input code values of DAC_VTH2_L block, for example, may be updated twice during each PWM period, with the first update occurring just before State_0begins, and the second update occurring just before State_5begins. The time zero values of the DAC values may be determined during an end-of line test of the inverter, stored, and used as initial codes with values to be re-computed with any changes in temperature and/or any change in the parameters of the power switches, load current amplitude and slope (seeFIG.9), or battery voltage, for example. These values may be computed for each PWM cycle period. The equation to calculate t3 is: t3=[Cgd(at low Vds.(Vbattery+Vforward_bias_bodydiode-Iload.rdson/I_profile_state6)].TCF.ICF. Before the time t3 expires, the state of the A2output signal V_comp_2is first checked to assure a logic state is low. If the logic state of A2output signal V_comp_2is not low, then a fault has occurred. The value of t3 may also be obtained in advance and stored to be used in the state6turn-off timing and definition. Again, for the case of very low package stray values, corresponding t3 timing values may be computed to be used in monitoring t3 mission-mode timings. If the monitored t3 timings are outside the computed timings, then that indicates that a fault may have occurred.

Next, based on an output of the G2amplifier crossing the programmed threshold voltage set by the output of DAC_VTH1_L block, a programmed gate-current/resistor profile of I_profile_state7(a stored value), is loaded to steer the gate voltage to further fall according to this current/resistor profile value whose sourcing time duration is set to a pre-calculated time value of t4. The equation to calculate t4 is: t4=[(Cgs+Cgd(at low Vds)).(Iload)/(gfs. I_profile_state7)].TCF.ICF. Before the expiration of t4, the state of the comparator A3output signal V_comp_1is first checked to assure a logic state has gone low, If the logic state of A3output signal V_comp_1is not low, then a fault has occurred. The value of t4 may also be determined in advance and stored to be used in the state7turn-off timing and definition. Again, for the case of very low package stray values, corresponding t4 timing values may be computed to be used in monitoring t4 mission-mode timings. If the monitored t4 timings are outside the computed timings, then that indicates that a fault may have occurred. For this case as soon as the state of the A3output signal V_comp_1becomes asserted low, the profile of I_profile_state7is loaded causing the gate voltage to fall further.

Next, when the state of the comparator A4output, V_comp_0, becomes low, then programmed gate-current profile of I_profile_state8(a stored value), is loaded to steer the gate voltage to fall according to this current/resistor profile value. The gate voltage keeps falling until the state of the comparator A5output, V_comp_4, becomes logic low, then programmed gate-current/resistor profile of I_profile_state9(a stored value), is subsequently loaded to steer the gate voltage to further fall toward the negative supply voltage rail of the gate-drive power supply voltage. The role of G3(Vg-VMS) may be to operate so that when the amplitude of the differential amplifier G3crosses the programmed threshold voltage value of “DAC_VMS_L”, then the off-state goes to the next assigned state, a maintenance state, and a few clock cycles after entering the maintenance state, the SL clamping switch may be commanded on. At this point, the turn-off profile process is complete and lower phase power switch648has become fully turned off.

The calculations of gate current/resistor turn-on and turn-off profiles (Iprofile) may be provided as: Iprofile=Inom_prog_value.[Tref/(273+aTC.T)].βIlds, where Tref is the reference temperature (such as room temperature, for example), αTC is a stored fixed pre-determined value representing a suitable temperature coefficient factor, and T is the operating temperature. The stored nominal current profiles (Inom_prog_value) is computed at the module level such that the nominal current profile accounts for the parameter variations of all power switches in the module, and uses the measured value of the power FET parameters Vth, gfs and Rdson at a given temperature (such as at Tref, for example). The two multiplying correction factors in above account for the temperature variation (the terms in the bracket) and the current-profile-slope-correction factor of βIds, which further modifies Iprofile to minimize the switching power losses with the current flowing in the power FET devices. The device current correction factor, βids, is calculated during each PWM switching cycle for the calculation of βids, which is in turn used to compute Iprofile for the next PWM cycle.

With reference to lower phase power switch648ofFIG.7, switch SU of lower phase clamp switches717may be turned on when the output V_Comp_3of A1comparator ofFIG.8takes a high state, forcing the gate terminal voltage to positive supply value of the gate-drive power supply in a shortest amount of time, thus minimizing the total power FET losses. Furthermore, switch SL of lower phase clamp switches717may be turned on when the output V_Comp_4of A5comparator takes a high state, forcing the gate terminal voltage to negative supply value of the gate-drive power supply in a shortest amount time, thus minimizing the total power FET losses. State4may be a maintenance state, which is initiated when the gate potential is approaching toward VPS_U or VPS_L voltage. SU clamping switch turns on a few clock cycles after the turn-on gate drive enters State_4, and SL clamping switch turns on a few clock cycles after entering State9. SU clamping switch opens immediately after the falling edge of PWL signal.

FIG.9depicts an exemplary plot for a correction factor for an adaptive gate driver for a power device switch, according to one or more embodiments.

FIG.9shows a trajectory plot900of the βids correction factor. βids may be computed for each PWM cycle period based on the previous measurement of Ids magnitude and slope. As shown inFIG.9, βIds current-profile-slope-correction factor905may begin at a maximum value as Ids increases from zero, decrease in value along a slope ranging from approximately three to approximately one as Ids increases, and reach a minimum value of one at910at a maximum value of Ids. The two multiplying correction factors in Iprofile equation account for the temperature variation (the terms in the bracket) and the current-profile-slope-correction factor of βids, which further modifies Iprofile to minimize the switching power losses with the current flowing in the power FET devices. The device current is calculated during each PWM switching cycle for the calculation of βids, which is in turn used to compute Iprofile for the next PWM cycle.

FIG.10depicts an exemplary system for a current/resistor hybrid adaptive gate driver for a power device switch, according to one or more embodiments.

One or more embodiments may include a hybrid adaptive gate driver1000including both turn-on and turn-off (source/sink) programmable profile current drivers and turn-on and turn-off programmable profile resistors. Hybrid adaptive gate driver1000may provide both low impedance to the gate terminals of upper phase power switch644and lower phase power switch648during turn-on and turn-off events while maintaining the capability to drive a gate with any desired current drive profile. The infrastructure of the gate-drive technique may include a high-speed measurement of the current flowing into upper phase power switch644and lower phase power switch648, to be used to turn off the upper phase power switch644and lower phase power switch648in an overcurrent event in less than one microsecond.

Lower phase power switch648, for example, may include multiple devices in parallel to deliver a maximum requested power transfer to the load. Due to the device parameter mismatches from the non-ideal manufacturing process of the power FETs, the load current may not be equally shared among the parallel devices during both switching and conduction operations. However, one or more embodiments may separately drive the gate terminal of each device or a group of devices. This separate driving may offer the opportunity to schedule the turn-on and turn-off timings and calculated gate current profiles to minimize current imbalance in the parallel devices. For example, in the case when two devices are connected in parallel, if one device (or a group of parallel connected devices) has higher threshold voltage than a second device, the turn-on of the devices with a lower threshold voltage may be delayed with the respect to the turn-on time of the device with a higher threshold voltage, resulting in relatively equal current amplitude flowing in both devices. During the turn-off, the device with higher threshold voltage may be the device with delayed turn-off timing, contrary to the turn-on event delay. This separate driving may provide uniform and relatively equal temperature and relatively matched long-term longevity among the parallel devices.

In addition to introducing a turn-on/off delay between unmatched groups of devices, unique gate-drive profile may be computed to further equalize and improve current sharing among groups of devices. One or more embodiments may minimize the current imbalance among the parallel-connected devices by prioritizing the turn-on and turn-off delay timings and computing appropriate gate-drive profiles among the devices.

FIG.11depicts an exemplary system for a correction controller1100for an adaptive gate driver for a power device switch, according to one or more embodiments.

With reference toFIG.8, one or more embodiments may continuously measure threshold voltage drift of a power switch over time. As shown inFIG.11, this may be achieved by continuously measuring the gate-to-source voltage Vgs of the power switches with a high speed sensing circuit, to be converted into a digital code A0-A(k−1), by a flash analog-to-digital converter1105. The digital code may be used by a drift-correction-computing-engine1106to compute an optimum and/or safe gate drive turn-on and/or turn-off voltage profile, or, in an extreme case, to clear an open gate-terminal fault, for example.

FIG.12depicts an exemplary method1200for operating an adaptive gate driver for a power device switch, according to one or more embodiments.

Method1200may include receiving, by one or more controllers (e.g. point-of-use upper phase A controller142A or resistor-based adaptive gate driver800for lower phase power switch648), a voltage from a gate terminal to a source terminal of a power switch (e.g. upper phase A switches144A or lower phase power switch648) for an inverter110for an electric vehicle100(operation1210). Method1200may include comparing, by the one or more controllers, the voltage to one or more threshold values (e.g. DAC_VTH0_L, DAC_VTH1_L, or DAC_VTH2_L) (operation1220). Method1200may include loading, by the one or more controllers, a gate driver profile (e.g. I_profile_state1), from among a plurality of gate driver profiles, based on the comparing (operation1230). Method1200may include controlling, by the one or more controllers, a gate driver of the power switch based on the loaded gate driver profile (operation1240). Method1200may include controlling an operation of one or more switches of the gate driver to change one or more of a variable resistance of a resistive gate driver of the gate driver or a current of a current gate driver of the gate driver (operation1250). For example, turn-on resistors710and turn-off resistors711may be dynamically selected by operation of the respective φ switches based on the respective turn-on and turn-off control signals of the loaded gate driver profile. The gate driver profile may be determined based on one or more of an intrinsic characteristic of the power switch, load-current slope and amplitude value, high-voltage battery amplitude of the inverter, or operating temperature of the power switch.

One or more embodiments may provide a gate driver system that significantly reduces switching power losses while protecting the power switches with regard to the gate voltage and drain current ringing amplitude and the drain to source voltage overshoot and ringing amplitude. One or more embodiments may provide a gate driver system that computes optimum gate-drive turn-on and turn-off voltage profiles that incorporates intrinsic characteristics of power devices, load-current slope and amplitude, high-voltage battery amplitude, and operating temperature. One or more embodiments may provide a gate driver system that continuously measures threshold voltage drift over time of a power device, which may be used in the computation of the optimum gate-drive turn-on and turn-off voltage profiles, and in the detection of an open gate terminal fault. One or more embodiments may provide a gate driver system that uses a hybrid variable resistive driver along with fast transition switch-mode circuit, featuring a very low driving impedance for minimizing the switching turn-on and turn-off current and/or voltage ringing, while shortening the transition time to the full conduction time window. One or more embodiments may provide a gate driver system that continuously detects hard and/or soft short and/or open faults throughout the switching turn-on, turn-off, and conduction periods by continuously checking the gate voltage amplitude and rate of change of the gate voltage over time against several threshold voltages and pre-programmed time windows. One or more embodiments may provide a gate driver system that, for the case of turning on into hard short, computes a special turn-off profile to assure a safe turn-off of the power switch.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.