Patent ID: 12218282

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The embodiment of the application is illustrated in detail, and is plotted in the drawings. The same or the similar part is illustrated in the drawings and the specification with the same number.

FIG.1illustrates a top view of a light-emitting device1in accordance with an embodiment of the present application.FIG.2illustrates a cross-sectional view ofFIG.1along line A-A′.

As shown inFIG.1andFIG.2, a light-emitting device1includes a substrate11; and a semiconductor stack formed on the substrate11, wherein the semiconductor stack includes a first semiconductor layer111, and a plurality of semiconductor pillars12separated from each other and formed on the first semiconductor layer111. The plurality of semiconductor pillars12each includes a second semiconductor layer122and an active layer123. In an embodiment of the present application, the semiconductor pillar12includes a part of the first semiconductor layer111, and the active layer123is formed between the first semiconductor layer111and the second semiconductor layer122.

In an embodiment of the present application, the substrate11can be a growth substrate, including gallium arsenide (GaAs) wafer for growing aluminum gallium indium phosphide (AlGaInP), or sapphire (Al2O3) wafer, gallium nitride (GaN) wafer or silicon carbide (SiC) wafer for growing gallium nitride (GaN), indium gallium nitride (InGaN) or aluminum gallium nitride (AlGaN).

In an embodiment of the present application, a plurality of semiconductor layers including optical characteristics and consisting of semiconductor materials is formed on the substrate11by organic metal chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), physical vapor deposition (PVD), or ion plating, wherein physical vapor deposition (PVD) including sputtering or evaporation. The plurality of semiconductor layers is patterned by lithography and etching to remove portions of the semiconductor layers and to form the semiconductor stack including the first semiconductor layer111, and the plurality of semiconductor pillars12consisting of the active layer123and the second semiconductor layer122.

The first semiconductor layer111and the second semiconductor layer122can be cladding layers, have different conductivity types, electrical properties, polarities, or doping elements for providing electrons or holes. For example, the first semiconductor layer111is an n-type semiconductor and the second semiconductor layer122is a p-type semiconductor. The active layer123is formed between the first semiconductor layer111and the second semiconductor layer122. The electrons and holes combine in the active layer123under a current driving to convert electric energy into light energy and then light is emitted from the active layer123. The wavelength of the light emitted from the light-emitting device1is adjusted by changing the physical and chemical composition of one or more layers in the semiconductor stack. The material of the semiconductor stack includes a group III-V semiconductor material, such as AlxInyGa(1-x-y)N or AlxInyGa(1-x-y)P, wherein 0≤x, y≤1; (x+y)≤1. According to the material of the active layer123, when the material of the semiconductor stack is AlInGaP series material, red light having a wavelength between 610 nm and 650 nm or yellow light having a wavelength between 550 nm and 570 nm can be emitted. When the material of the semiconductor stack is InGaN series material, blue or deep blue light having a wavelength between 400 nm and 490 nm or green light having a wavelength between 490 nm and 550 nm can be emitted. When the material of the semiconductor stack is AlGaN series material, UV light having a wavelength between 400 nm and 250 nm can be emitted. The active layer123can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well structure, MQW). The material of the active layer123can be i-type, p-type, or n-type semiconductor.

In an embodiment of the present application, a buffer layer (not shown) is formed between the semiconductor stack and the substrate11to improve the epitaxial quality of the semiconductor stack. In an embodiment, an aluminum nitride (AlN) layer can be used as the buffer layer. In an embodiment, the method for forming aluminum nitride (AlN) is PVD, and the target is made of aluminum nitride. In another embodiment, a target made of aluminum which reacts in a nitrogen source environment with a PVD method is used to form aluminum nitride.

In an embodiment of the present application, the substrate11includes a sapphire (Al2O3) substrate, and the first semiconductor layer111includes an aluminum gallium nitride (AlGaN) layer. In order to reduce the epitaxial defects caused by the lattice difference between the AlGaN layer and the sapphire substrate, the AlN layer is formed as a buffer layer between the AlGaN layer and the sapphire substrate, wherein the AlN buffer layer includes a thickness greater than 300 nm, preferably greater than 1000 nm, and even greater than 2500 nm to fill the epitaxial defects. The aluminum nitride (AlN) buffer layer includes carbon (C), hydrogen (H), and/or oxygen (O) including a doping concentration lower than 2E+17. The aluminum (Al) composition percentage of the aluminum nitride (AlN) buffer layer is greater than that of aluminum gallium nitride (AlGaN) of the first semiconductor layer111.

As shown in the top view ofFIG.1and the cross-sectional view ofFIG.2taken along line A-A′ ofFIG.1, after the plurality of semiconductor layers is formed on the substrate11, the plurality of semiconductor layers is patterned by lithography and etching to remove portions of the semiconductor layers and to form the semiconductor stack including the first semiconductor layer III and the plurality of semiconductor pillars12separated from each other, wherein the plurality of semiconductor pillars12each includes the second semiconductor layer122and the active layer123.

In an embodiment of the present application, the semiconductor pillars12are separated from each other to expose a surface S1of the first semiconductor layer111. The substrate11includes a first sidewall11s, the first semiconductor layer111includes a second sidewall111s, and the plurality of semiconductor pillars12each includes a third sidewall12s. As shown inFIG.2, the first sidewall11sof the substrate11is aligned to the second sidewall111sof the first semiconductor layer111. An inclined angle or a right angle is between the third sidewall12sof the semiconductor pillar12and the surface S1of the first semiconductor layer111.

In an embodiment of the present application, the inclined angle between the third sidewall12sof the semiconductor pillar12and the surface S1of the first semiconductor layer111includes an angle between 10 degrees and 80 degrees, preferably less than 60 degrees, and more preferably less than 40 degrees.

In an embodiment of the present application, the first sidewall11sof the substrate11is separated from the second sidewall111sof the first semiconductor layer111by a distance to expose a surface S2of the substrate11. An obtuse angle or a right angle is between the second sidewall111sof the first semiconductor layer111and the surface S2of the substrate11.

In an embodiment of the present application, an inclined angle between the second sidewall111sof the first semiconductor layer111and the surface S2of the substrate11includes an angle between 10 degrees and 80 degrees, preferably less than 60 degrees, and more preferably less than 40 degrees. A height between the surface S1of the first semiconductor layer111and the surface S2of the substrate11is greater than 4000 Å, preferably greater than 6000 Å, and more preferably greater than 8000 Å.

In an embodiment of the present application, the surface S2of the substrate11is a flat surface, wherein the flat surface includes a roughness (Root mean square roughness, Rq) less than 8 nm, preferably less than 5 nm, and more preferably less than 2 nm.

In an embodiment of the present application, the surface S2of the substrate11includes a patterned surface (not shown), wherein the patterned surface includes a plurality of recesses extending from the surface S2of the substrate11toward the interior of the substrate11or a plurality of protrusions extending from the surface S2of the substrate11toward the surface S1of the first semiconductor layer111. From the top view of the light-emitting device1, the plurality of recesses or the plurality of protrusions each includes a circle, an ellipse, a rectangle, a polygon, or any other shape. From the top view of the light-emitting device1, the plurality of recesses or the plurality of protrusions each includes a bottom portion that is flush with the surface S2of the substrate11, and a top portion that is opposite to the bottom portion. The top portion may be a flat surface or a point. The depth or the height between the top portion and the bottom portion is between 0.1 μm and 2 μm, preferably between 0.2 μm and 0.9 μm, and more preferably between 0.5 μm and 0.7 μm. The bottom portion includes a width or a diameter between 0.05 μm and 1 μm, preferably between 0.2 μm and 0.8 μm, and more preferably between 0.3 μm and 0.5 μm.

In an embodiment of the present application, viewing from the top view of the light-emitting device1shown inFIG.1, the semiconductor pillars12each includes a circle, an ellipse, a rectangle, a polygon, or any other shape.

In an embodiment of the present application, reducing the diameter or the width of the semiconductor pillar12can reduce the forward voltage (Vf) of the light-emitting device1. From the top view of the light-emitting device1, the semiconductor pillar12includes a diameter or a width greater than 4 μm and/or less than 80 μm, preferably less than 50 μm, and more preferably less than 20 μm.

In an embodiment of the present application, the semiconductor pillars12are arranged in a plurality of columns, and the semiconductor pillars12arranged in any two adjacent columns or every two adjacent columns can be aligned with each other or staggered.

In an embodiment of the present application, the semiconductor pillars12can be arranged in a first column and a second column. A first shortest distance is between two adjacent semiconductor pillars12in the same column, and a second shortest distance is between one of the semiconductor pillars12in the first column and another adjacent one of the semiconductor pillars12in the second column, wherein the first shortest distance is greater than or less than the second shortest distance. When an external current is injected into the light-emitting device1, the dispersed disposition of the plurality of semiconductor columns12uniforms the light field distribution of the light-emitting device1and reduces the forward voltage of the light-emitting device1.

In an embodiment of the present application, the semiconductor pillars12can be arranged in a first column, a second column and a third column. A first shortest distance is between one of the semiconductor pillars12in the first column and another one of the semiconductor pillars12in the second column, and a second shortest distance is between one of the semiconductor pillars12in the second column and another one of the semiconductor pillars12in the third column, wherein the first shortest distance is less than the second shortest distance. When an external current is injected into the light-emitting device1, the dispersed disposition of the plurality of semiconductor columns12uniforms the light field distribution of the light-emitting device1and reduces the forward voltage of the light-emitting device1.

A first contact layer131is formed on the surface S1of the first semiconductor layer111by physical vapor deposition or chemical vapor deposition. The material of the first contact layer131includes metal material, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), rhodium (Rh), or an alloy of the above materials.

In an embodiment of the present application, the light emitted from the light-emitting device1includes a wavelength longer than 370 nm, and the material of the first contact layer131includes a metal having high reflectivity, such as silver (Ag), aluminum (Al), platinum (Pt) or rhodium (Rh). In order to increase the reflectivity of the first contact layer131, the metal layer of silver (Ag), aluminum (Al), platinum (Pt), or rhodium (Rh) includes a thickness greater than 400 angstroms (Å), preferably greater than 800 angstroms (Å), and more preferably greater than 1200 angstroms (Å).

In an embodiment of the present application, the light emitted from the light-emitting device1includes a wavelength shorter than 370 nm, and the material of the first contact layer131does not include silver (Ag).

In an embodiment of the present application, one side of the first contact layer131contacting with the surface S1of the first semiconductor layer111includes chromium (Cr) or titanium (Ti) to increase the bonding strength between the first contact layer131and the first semiconductor layer111. In order to reduce the light loss, the thickness of chromium (Cr) or titanium (Ti) layer is lower than 1000 angstroms (Å), preferably lower than 600 angstroms (Å), and more preferably lower than 400 angstroms (Å). And, in order to maintain sufficient bonding strength, chromium (Cr) and/or titanium (Ti) layers include a thickness greater than 10 angstroms (Å), preferably greater than 50 angstroms (Å), and more preferably greater than 100 angstroms (Å).

In an embodiment of the present application, the first semiconductor layer111includes AlxGa(1-x)N, where 0.3<x<0.8, preferably 0.35<x<0.7, and more preferably 0.4<x<0.6. In order to form an ohmic contact between the first contact layer131and the surface S1of the first semiconductor layer111, and maintain a sufficient bonding strength therebetween, the first contact layer131includes titanium (Ti) and aluminum (Al), wherein a ratio of a titanium (Ti) layer to an aluminum (Al) layer is between 0.1 and 0.2.

In an embodiment of the present application, the first contact layer131includes a first contact portion P1and a first extending portion E1. The first contact portion P1includes a projected area on the first semiconductor layer111that is larger than a projected area of one of the plurality of semiconductor pillars12on the first semiconductor layer111, wherein the projected area refers to a surface area along a normal direction perpendicular to the surface S2of the substrate11. As shown inFIG.1, the first extending portion E1extends from the first contact portion P1and surrounds the plurality of semiconductor pillars12.

In an embodiment of the present application, the first contact layer131includes a plurality of first contact portions P1and a plurality of first extending portions E1, wherein the plurality of first extending portions E1is extended from the plurality of first contact portions P1and are connected to each other, and the plurality of first contact portions P1is electrically connected by the plurality of first extending portions E1.

As shown inFIG.2, in an embodiment of the present application, the first contact portion P1of the first contact layer131includes a width larger than a width of the first extending portion E1.

A second contact layer132is formed on the second semiconductor layer122of the semiconductor pillar12by physical vapor deposition or chemical vapor deposition. The material of the second contact layer132includes metal, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), rhodium (Rh), or an alloy of the above materials.

In an embodiment of the present application, the light emitted from the light-emitting device1includes a wavelength longer than 370 nm, and the material of the second contact layer132includes a metal having high reflectivity, such as silver (Ag), aluminum (Al), platinum (Pt) or rhodium (Rh). In order to increase the reflectivity of the second contact layer132, the metal layer of silver (Ag), aluminum (Al), platinum (Pt), or rhodium (Rh) includes a thickness greater than 400 angstroms (Å), preferably greater than 800 angstroms (Å), and more preferably greater than 1200 angstroms (Å).

In an embodiment of the present application, the light emitted from the light-emitting device1includes a wavelength shorter than 370 nm, and the material of the second contact layer132does not include silver (Ag).

In an embodiment of the present application, a plurality of second contact layers132are respectively formed on the second semiconductor layer122of the plurality of semiconductor pillars12, and the plurality of second contact layers132are separated from each other.

In an embodiment of the present application, the second semiconductor layer122includes GaN, AlGaN or BN, and the second semiconductor layer122includes a doping element such as magnesium (Mg) to form a p-type semiconductor, wherein the doping element includes a concentration greater than 9E+18, preferably greater than 4E+19, and more preferably greater than 1E+20. The second contact layer132includes a transparent conductive material that is transparent to the light emitted from the active layer123and capable of forming ohmic contact with the second semiconductor layer122. The transparent conductive material includes a non-metal material such as graphene, metal, or metal oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO). The second contact layer132is substantially formed on the entire surface of the second semiconductor layer122and contacts the second semiconductor layer122. The electrical current is uniformly spread into the second semiconductor layer122through the second contact layer132. In an embodiment of the present application, the second contact layer132includes graphene, and the second contact layer132further includes a thin metal layer or a thin metal oxide layer with material such as nickel oxide (NiO), cobalt oxide (CO3O4), or copper oxide (Cu2O) formed between the second semiconductor layer122and the graphene layer for forming ohmic contact with the second semiconductor layer122. The thin metal layer or thin metal oxide layer includes a thickness between 0.1 and 100 nm, preferably between 0.1 and 50 nm, more preferably between 0.1 and 20 nm. In an embodiment of the present application, the thickness of the second contact layer132is between 0.1 nm and 100 nm. If the thickness of the second contact layer132is less than 0.1 nm, an ohmic contact with the second semiconductor layer122cannot be formed therebetween because the thickness is too thin. Besides, if the thickness of the second contact layer132is greater than 100 nm, the second contact layer132is too thick to partially absorb light emitted from the active layer123, and the luminance of the light-emitting device1is reduced.

In an embodiment of the present application, The positions of the first contact layer131and the second contact layers132formed on the semiconductor stack are misaligned and do not overlap each other.

A first insulating layer14is formed by physical vapor deposition or chemical vapor deposition to depositing an insulating material layer on the first contact layer131and the second contact layer132. The first insulating layer14is formed by patterning a portion of the insulating material layer by lithography and etching, and a first opening1401of the first insulating layer14is formed on the first contact layer131to expose the first contact layer131and a second opening1402of the first insulating layer14is formed on the second contact layer132to expose the second contact layer132.

In an embodiment of the present application, the first contact layer131includes the plurality of first contact portions P1and the plurality of first extending portions E1. The first insulating layer14includes a plurality of first openings1401respectively formed on the plurality of first contacts P1, wherein the plurality of first extending portions E1is covered by the first insulating layer14.

In an embodiment of the present application, the first insulating layer14includes a plurality of second openings1402respectively formed on the plurality of semiconductor pillars12. In other words, an amount of the plurality of second openings1402is same as that of the plurality of semiconductor pillars12.

In an embodiment of the present application, an amount of the plurality of second openings1402of the first insulating layer14is larger than that of the plurality of first openings1401.

In an embodiment of the present application, the second opening1402of the first insulating layer14includes a width smaller than that of the first opening1401.

In an embodiment of the present application, the first insulating layer14covers the third sidewalls12sof the plurality of semiconductor pillars12, covers the surface S1of the first semiconductor layer111, covers the second sidewall111sof the first semiconductor layer111, and/or covers the surface S2of the substrate11.

In an embodiment of the present application, the first insulating layer14protects the semiconductor structure, and includes two or more layers having different refractive indexes alternately stacked to form a Distributed Bragg reflector (DBR). The DBR selectively reflects light of a specific wavelength. The first insulating layer14is formed of a non-conductive material including organic material, inorganic material or dielectric material. The organic material includes Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymers (COC), polymethylmethacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, or fluorocarbon polymer. The inorganic material includes silicone or glass. The dielectric material includes aluminum oxide (Al2O3), silicon nitride (SiNx), silicon oxide (SiOx), titanium oxide (TiOx), or magnesium fluoride (MgFx).

A first electrode contact layer151and a second electrode contact layer152are respectively formed in the first opening1401and the second opening1402of the first insulating layer14by physical vapor deposition or chemical vapor deposition, and extend and cover portions of the surface of the first insulating layer14. The first electrode contact layer151is connected to the first contact portion P1of the first contact layer131through the first opening1401of the first insulating layer14. The second electrode contact layer152is connected to the plurality of second contact layers132through the second opening1402of the first insulating layer14.

In an embodiment of the present application, the second electrode contact layer152covers the plurality of semiconductor pillars12and portions of the first contact layer131, wherein the second electrode contact layer152is electrically isolated from the first contact layer131by the first insulating layer14.

In an embodiment of the present application, the first contact layer131includes the first contact portion P1including a width W1larger than a width W2of the semiconductor pillar12, the width W1of the first contact portion P1of the first contact layer131is larger than the width W3of the first electrode contact layer151, and the width W3of the first electrode contact layer151is larger than the width W2of the semiconductor pillar12.

In an embodiment of the present application, the first electrode contact layer151covers portions of the first contact layer131, the second electrode contact layer152covers all of the second contact layers132.

In an embodiment of the present application, the first electrode contact layer151covers portions of the first contact layer131, the second electrode contact layer152covers portions of the second contact layers132.

In an embodiment of the present application, the first electrode contact layer151covers all of the first contact layer131, the second electrode contact layer152covers portions of the second contact layers132.

In an embodiment of the present application, the first electrode contact layer151and the second electrode contact layer152are separated from each other by a distance. In the top view of the light-emitting device1, the second electrode contact layer152surrounds multiple sidewalls of the first electrode contact layer151.

In an embodiment of the present application, in the top view of the light-emitting device1, the second electrode contact layer152includes an area larger than an area of the first electrode contact layer151.

In an embodiment of the present application, when an external current is injected into the light-emitting device1, the electrical current is conducted to the first semiconductor layer111and the second semiconductor layer122by the first electrode contact layer151and the second electrode contact layer152.

As shown inFIG.1, the first electrode contact layer151is close to one side of the substrate11, such as the left or right side of a centerline of the substrate11.

In an embodiment of the present application, the material of the first electrode contact layer151and the second electrode contact layer152include a metal material, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), rhodium (Rh), or an alloy of the above materials.

In an embodiment of the present application, the light emitted from the light-emitting device1includes a wavelength shorter than 370 nm, and the material of the first electrode contact layer151and the second electrode contact layer152do not include silver (Ag). The material of the first electrode contact layer151and the second electrode contact layer152includes a metal having a high reflectivity for the UV light, such as aluminum (Al), platinum (Pt) or rhodium (Rh). In order to increase the reflectivity of the first electrode contact layer151and the second electrode contact layer152for the UV light, the layer including aluminum (Al), platinum (Pt), or rhodium (Rh) includes a thickness greater than 4000 angstroms (Å), preferably greater than 8000 angstroms (Å), and more preferably greater than 10000 angstroms (Å).

In an embodiment of the present application, one side of the first electrode contact layer151contacting with the first contact layer131includes chromium (Cr) or titanium (Ti) to increase the bonding strength between the first electrode contact layer151and the first contact layer131. The second electrode contact layer152contacting with the second contact layer132includes chromium (Cr) or titanium (Ti) to increase the bonding strength between the second electrode contact layer152and the second contact layer132. In order to reduce the brightness loss caused by the ultraviolet light of chromium (Cr) or titanium (Ti) material, a thickness of the layer including chromium (Cr) or titanium (Ti) material is lower than 1000 angstroms (Å), preferably lower than 800 angstroms (Å), and more preferably lower than 500 angstroms (Å). And, in order to maintain sufficient bonding strength, the layer including chromium (Cr) and/or titanium (Ti) includes a thickness greater than 10 angstroms (Å), preferably greater than 50 angstroms (Å), and more preferably greater than 100 angstroms (Å).

A second insulating layer16is formed by physical vapor deposition or chemical vapor deposition to deposit an insulating material layer on the first electrode contact layer151and the second electrode contact layer152. Then, the insulating material layer is patterned by lithography and etching to form the second insulating layer16, and the first opening1601and the second opening1602of the second insulating layer16respectively exposing the first electrode contact layer151and the second electrode contact layer152.

In an embodiment of the present application, the second insulating layer16includes one or a plurality of first openings1601and one or a plurality of second openings1602, wherein an amount of the plurality of first openings1601and an amount of the plurality of second openings1602are the same or different.

In an embodiment of the present application, the plurality of first openings1601of the second insulating layer16are respectively formed on the plurality of first electrode contact layers151, wherein an amount of the plurality of first openings1601and an amount of the plurality of first electrode contact layers151are the same.

In the top view ofFIG.1, the first opening1601and the second opening1602of the second insulating layer16are respectively formed on two sides of the centerline of the substrate11. For example, the first opening1601of the second insulating layer16is formed on the right side of the centerline of the substrate11, and the second opening1602of the second insulating layer16is formed on the left side of the centerline of the substrate11.

In an embodiment of the present application, the first opening1601of the second insulating layer16includes a width smaller than a width of the first opening1401of the first insulating layer14.

In an embodiment of the present application, the first opening1601of the second insulating layer16overlaps the first opening1401of the first insulating layer14, and the first opening1601of the second insulating layer16and the first opening1401of the first insulating layer14are both formed on the first contact layer131.

In an embodiment of the present application, the second opening1602of the second insulating layer16and the second opening1402of the first insulating layer14are misaligned. Specifically, the second opening1402of the first insulating layer14is formed on the second contact layer132, and the second opening1602of the second insulating layer16is formed on the first contact layer131.

In an embodiment of the present application, when the second insulating layer16includes a stack structure, and the stack structure includes two or more sublayers; wherein the sublayers have two materials with different refractive indexes alternately stacked to form a Distributed Bragg reflector (DBR). The DBR selectively reflects light of a specific wavelength. The second insulating layer16is formed of a non-conductive material including organic material, inorganic material or dielectric material. The organic material includes Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymers (COC), polymethylmethacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, or fluorocarbon polymer. The inorganic material includes silicone or glass. The dielectric material includes aluminum oxide (Al2O3), silicon nitride (SiNx), silicon oxide (SiOx), titanium oxide (TiOx), or magnesium fluoride (MgFx).

A first electrode171and a second electrode172are formed on the second insulating layer16by electroplating, physical vapor deposition or chemical vapor deposition. In the top view ofFIG.1, the first electrode171is close to one side of the substrate11, such as the right side of the centerline of the substrate11, and the second electrode172is close to the other side of the substrate11, such as the left side of the centerline of the substrate11. The first electrode171covers the first opening1601of the second insulating layer16to be in contact with the first electrode contact layer151, and is electrically connected with the first semiconductor layer111by the first contact layer131. The second electrode172covers the second opening1602of the second insulating layer16to be in contact with the second electrode contact layer152, and is electrically connected with the second semiconductor layer122by the second contact layer132.

In an embodiment of the present application, the plurality of semiconductor pillars12formed under a covering area of the first electrode171includes a first space D1to separate from each other. The plurality of semiconductor pillars12outside the covering area of the first electrode171includes a second space D2to separate from each other, and the first spacing D1is greater than the second spacing D2.

In an embodiment of the present application, the light emitting device1further includes a semiconductor mesa. The semiconductor mesa includes a first semiconductor layer, an active layer and a second semiconductor layer, and is formed under the first electrode171, wherein the plurality of semiconductor pillars12formed outside the covering area of the first electrode171includes a second space D2to separate from each other, and the second semiconductor layer of the semiconductor mesa includes a width larger than the second space D2between the plurality of semiconductor pillars12.

In an embodiment of the present application, the first contact portion P1of the first contact layer131is formed under the first electrode171and/or the second electrode172. The first extending portion E1of the first contact layer131is formed under the first electrode171and the second electrode172.

In an embodiment of the present application, the first electrode171includes a size equal to or different from a size of the second electrodes172. The size includes width or area.

In an embodiment of the present application, in the top view of the light-emitting device1, the shape of the first electrode171is the same as or similar to that of the second electrode172, for example, the shapes of the first electrode171and the second electrode172are rectangular, as shown inFIG.1.

In an embodiment of the present application, the first electrode171and the second electrode172include metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt) or an alloy of the above materials. The first electrode171and the second electrode172include a single layer or multiple layers. When the first electrode171and the second electrode172include multiple layers, the first electrode171includes a first upper pad and a first lower pad, and the second electrode172includes a second upper pad and a second lower pad. The upper pads and the lower pads have different functions.

In an embodiment of the present application, the function of the upper pad is mainly used for soldering and wire bonding. With the upper pad, the light-emitting device1can be mounted on a package substrate in a flip-chip form using solder or eutectic bonding, for example, an AuSn bonding. The metal material of the upper pad includes high-ductility material, such as tin (Sn), nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), copper (Cu), gold (Au), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru) osmium (Os), or alloys thereof. The upper pad can be a single layer or a laminated structure of the above materials. In an embodiment of the present application, the material of the upper pad includes nickel (Ni) and/or gold (Au), and the upper pad is a single layer or a laminated structure In an embodiment of the present application, the function of the lower pad is to form a stable interface with the first electrode contact layer151and the second electrode contact layer152, for example, to increase the interface bonding strength between the first lower pad and the first electrode contact layer151, or to increase the interface bonding strength between the second lower pad and the second electrode contact layer152. Another function of the lower pad is to prevent tin (Sn) in the solder or AuSn eutectic from diffusing into the reflective structure that destroys the reflectivity of the reflective structure. Therefore, the lower pad includes metal materials other than gold (Au), copper (Cu), such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), tungsten (W), zirconium (Zr). molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium (Os) or an alloy of the above materials. The lower pad can be a single layer or a laminated structure of the above materials. In an embodiment of the present application, the lower pad includes a laminated structure of titanium (Ti)/aluminum (Al) or a laminated structure of chromium (Cr)/aluminum (Al).

In an embodiment of the present application, in order to prevent tin (Sn) in the solder or AuSn eutectic from diffusing into the reflective structure that destroys the reflectivity of the reflective structure, one side of the first electrode contact layer151contacting with the first electrode171includes a metal material selected from the group consisting of titanium (Ti) and platinum (Pt). One side of the second electrode contact layer152contacting with the second electrode172includes a metal material selected from the group consisting of titanium (Ti) and platinum (Pt).

FIG.3Aillustrates a partial cross-sectional view of a light-emitting device2A in accordance with an embodiment of the present application.FIG.3Billustrates a partial top view of the light-emitting device2A in accordance with an embodiment of the present application. Since the light-emitting device2A and the light-emitting device1have substantially the same structure, the descriptions about the same structure of the light-emitting device2A and the light-emitting device1will be appropriately omitted or will not be repeated.

As shown inFIG.3AandFIG.3B, the light-emitting device2A illustrates another example of the structural embodiment of the semiconductor pillar12of the light-emitting device1illustrated inFIG.1. In an embodiment of the present application, the semiconductor stack includes a first semiconductor layer221, an active layer223, and a semiconductor pillar22on the active layer223. The active layer223includes one or more well layers and one or more barrier layer alternatively stacked, wherein the well layer includes AlxGa1-xN and 0.2<x<0.4, and the barrier layer includes AlyGa1-yN and 0.4<y<0.7. The semiconductor pillar12shown in the light-emitting device1ofFIG.2can be replaced by the semiconductor pillar22shown inFIGS.3A and3B, the semiconductor pillar22includes a second semiconductor layer222. In an embodiment of the present application, the semiconductor pillar22further includes a portion of the active layer223. The active layer223is formed between the first semiconductor layer221and the second semiconductor layer222, and the active layer223emits a UV light.

In an embodiment of the present application, the substrate11includes a first sidewall11s, the first semiconductor layer221includes a second sidewall221s, the second semiconductor layer222includes a third sidewall222s, and the active layer223includes a sidewall223s. As shown inFIG.3A, the third sidewall222sof the second semiconductor layer222is separated from the sidewall223sof the active layer223by a distance to expose a surface S3of the active layer223, wherein the exposed surface S3of the active layer223can be the well layer or the barrier layer, the well layer includes AlxGa1-xN and 0.2<x<0.4, and the barrier layer includes AlyGa1-yN and 0.4<y<0.7. An obtuse angle or a right angle is between the third sidewall222sof the second semiconductor layer222and the surfaces S3of the active layer223.

In an embodiment of the present application, in the top view of the light-emitting device2A shown inFIG.3B, the second semiconductor layer222each includes a circle, an ellipse, a rectangle, a polygon, or any other shape. The second semiconductor layer222is surrounded by the active layer223, and part of the surface S3of the active layer223is exposed to be formed outside the covering area of the second semiconductor layer222. Part of the surface S3of the active layer223is not covered by the second semiconductor layer222, wherein the exposed surface S3of the active layer223can be the well layer or the barrier layer, the well layer includes AlxGa1-xN and 0.2<x<0.4, and the barrier layer includes AlyGa1-yN and 0.4<y<0.7.

In an embodiment of the present application, the active layer223is surrounded by the first semiconductor layer221, and part of the surface S1of the first semiconductor layer221is exposed to be formed outside the covering area of the active layer223, wherein the first semiconductor layer221includes AlGaN. The part of the surface S1of the first semiconductor layer221is not covered by the active layer223.

FIG.4Aillustrates a partial cross-sectional view of a light-emitting device2B in accordance with an embodiment of the present application.FIG.4Billustrates a partial top view of the light-emitting device2B in accordance with an embodiment of the present application. Since the light-emitting device2B and the light-emitting device1have substantially the same structure, the descriptions about the same structure of the light-emitting device2B and the light-emitting device1will be appropriately omitted or will not be repeated.

As shown inFIG.4AandFIG.4B, the light-emitting device2B illustrates another example of the structural embodiment of the semiconductor pillar12of the light-emitting device1illustrated inFIG.2. In an embodiment of the present application, the semiconductor stack includes a first semiconductor layer321, an active layer323, and a plurality of semiconductor pillars32on the first semiconductor layer321. The semiconductor pillars32each includes a second semiconductor layer322, and the active layer323emits a UV light.

In an embodiment of the present application, the semiconductor pillar32further includes part of the active layer323. The active layer323is formed between the first semiconductor layer321and the second semiconductor layer322, and the active layer323emits UV light.

In an embodiment of the present application, in the top view of the light-emitting device2B shown inFIG.4B, the second semiconductor layer322each includes a circle, an ellipse, a rectangle, a polygon, or any other shape. The second semiconductor layer322is surrounded by the active layer323, and part of the surface S3of the active layer323is exposed to be formed outside the covering area of the second semiconductor layer322. The part of the surface S3of the active layer323is not covered by the second semiconductor layer323. The active layer323is surrounded by the first semiconductor layer321, and part of the surface S1of the first semiconductor layer321is exposed outside the coverage area of the active layer323. The part of the surface S1of the first semiconductor layer321is not covered by the active layer323, wherein the first semiconductor layer321includes AlGaN.

FIG.5is a schematic view of a light-emitting apparatus3in accordance with an embodiment of the present application. The light-emitting device1,2A, or2B in the foregoing embodiment is mounted on the first spacer511and the second spacer512of the package substrate51in the form of flip chip. The first spacer511and the second spacer512are electrically insulated from each other by an insulating portion53including an insulating material. The main light-extraction surface of the flip chip is one side of the growth substrate11opposite to the electrode-forming surface where the electrodes are formed on. A reflective structure54can be provided around the light-emitting device1,2A, or2B to increase the light extraction efficiency of the light-emitting apparatus3.

FIG.6illustrates a structure diagram of a light-emitting apparatus4in accordance with an embodiment of the present application. A light bulb includes an envelope602, a lens604, a light-emitting module610, a base612, a heat sink614, a connector616and an electrical connecting device618. The light-emitting module610includes a submount606and a plurality of light-emitting devices608on the submount606, wherein the plurality of light-emitting devices608can be the light-emitting device1,2A, or2B or the light-emitting apparatus3described in above embodiments.

The principle and the efficiency of the present application illustrated by the embodiments above are not the limitation of the application. Any person having ordinary skill in the art can modify or change the aforementioned embodiments. Therefore, the protection range of the rights in the application will be listed as the following claims.