Patent ID: 12199041

DESCRIPTION

This disclosure, its aspects and implementations, are not limited to the specific components, assembly procedures or method elements disclosed herein. Many additional components, assembly procedures and/or method elements known in the art consistent with the intended semiconductor packages will become apparent for use with particular implementations from this disclosure. Accordingly, for example, although particular implementations are disclosed, such implementations and implementing components may comprise any shape, size, style, type, model, version, measurement, concentration, material, quantity, method element, step, and/or the like as is known in the art for such semiconductor packages, and implementing components and methods, consistent with the intended operation and methods.

Referring toFIG.1, a cross-section side view of a first implementation of a semiconductor package is illustrated. In various implementations, the semiconductor packages disclosed herein may include power semiconductor devices, however, in other implementations other semiconductor device types (transistors, microprocessors, passive components, etc.) may be included in the semiconductor packages. In various implementations, the semiconductor package2includes a die4. The die4may be a silicon die, and in such implementations, the silicon die could be any type of silicon die including, by non-limiting example, an epitaxial silicon die, silicon-on-insulator, polysilicon, any combination thereof, or any other silicon-containing die material. Further, it is also understood that in various implementations a die other than a silicon-containing die may be used, such as, by non-limiting example, gallium arsenide, silicon carbide, gallium arsenide, or a metal-containing die. The die4has a first side6and a second side8opposite the first side. In various implementations, the thickness of the die4is less than 50 micrometers (um), however, in other implementations the thickness of the die may be 50 um or more than 50 um.

In various implementations, the semiconductor package2may include a first metal layer10coupled to the first side6of the die4. In such implementations, the first metal layer10may be, by non-limiting example, copper, aluminum, tin, silver, gold, titanium, nickel, or any other metal or metal alloy. In various implementations, the first metal layer10may be directly coupled to the first side6of the die4, while in other implementations, as is illustrated byFIG.1, the first metal layer may be indirectly coupled to the die4. In various implementations, the semiconductor package2may include a tin layer12coupled to the first metal layer10. While this disclosure primarily refers to a tin layer coupled over the first metal layer, it is understood that any other electrically and/or thermally conductive material, including any metal or metal alloy disclosed herein, may be used in place of the tin. Also, the tin used in the tin layer may be tin or a tin alloy, such as, by non-limiting example, tin/silver, tin/silver/copper, tin/antimony, and tin/lead. In various implementations, and as illustrated byFIG.1, the tin layer12may be directly coupled to the first metal layer10with the first metal layer10between the tin layer and the die4. In other implementations the tin layer12may be indirectly coupled to the first metal layer10.

In various implementations, the semiconductor package2may include a second metal layer14coupled between the die4and the first metal layer10. In such implementations, the semiconductor package2includes at least three metal layers over the die4. The second metal layer14may be any type of metal or metal alloy disclosed herein. In particular implementations, the second metal layer may include tin or a tin alloy, such as, by non-limiting example, tin/silver, tin/silver/copper, tin/antimony, and tin/lead. In other particular implementations, the second metal layer14may include aluminum, the first metal layer10may include copper, and the tin layer12may be over and coupled to the copper layer.

In various implementations, the tin layer12and the first metal layer10may be formed into and include a plurality of bumps/studs16. In implementations including a second metal layer14between the first metal layer10and the die4, the second metal layer14may also be patterned to form a portion of the plurality of bumps16. In particular implementations, not all three metal layers are patterned to form a plurality of bumps, but only the two outermost metal layers (in implementations having three or more metal layers over the die4) include the plurality of bumps. In still other implementations, only the tin layer12may be patterned to form or include the plurality of bumps. In various implementations, and as illustrated byFIG.1, the plurality of bumps16may include two bumps, however, in other implementations the plurality of bumps may include more than two bumps.

In various implementations, rather than having a plurality of metal layers forming the bumps as illustrated byFIG.1, a single metal or metal alloy layer, including, by non-limiting example, copper, aluminum, tin, a solder, or any combination thereof, may form the plurality of bumps and may be directly coupled to the die4. In other implementations, and as illustrated byFIG.1, each bump of the plurality of bumps16may include multiple layers with a tin layer12coupled over the copper layer. In such implementations, the semiconductor package2may have the benefit of being able to bond to external connections through the tin layer12while also maintaining the benefit of having a copper bump or stud. In various implementations, the tin layer12may be much thinner than the first metal layer10, while in other implementations, the tin layer12may be as thick as or thicker than the first metal layer10. In implementations with a second metal layer14coupled between the first metal layer10and the die4, the second metal layer may be less thick, as thick, or more thick than the first metal layer when viewed in a cross sectional view of the die4.

In various implementations, the semiconductor package2may include a backside metal layer18coupled to the second side8of the die4. The backside metal layer18may be any metal disclosed herein, and in various implementations, may include copper. In particular implementations, the backside metal layer may include, by non-limiting example, Ti/Ni/Cu, Ti/Cu, TiW/Cu, or any other type of metal stack or metal alloy including copper. In various implementations, and as illustrated byFIG.1, the length of the backside metal layer18may be less than the length of the die4. In such implementations, the die4may overhang the backside metal layer18. In other implementations, the length of the backmetal layer18may be substantially the same as the length of the die4with the sides of the backmetal layer coextensive with the sides/perimeter of the die. In still other implementations, the back metal layer may extend beyond the sides/perimeter of the die4. In various implementations, the back metal layer may be patterned.

Still referring toFIG.1, in various implementations the semiconductor package2may include a mold compound20. The mold compound20may be coupled to the die4. In various implementations, the mold compound may include, by non-limiting example, an epoxy mold compound, an acrylic mold compound, or any other type of mold compound or protective covering capable of hardening and providing physical support and protection to a semiconductor device. In various implementations, the mold compound20may cover a plurality of sidewalls22of the first metal layer10and a plurality of sidewalls24of the tin layer. In implementations with a plurality of bumps16, the mold compound may cover a first side26and a second side28of each bump. In various implementations, a surface30of the mold compound may be substantially coplanar and level with a surface32of the tin layer12. In various implementations, and as is illustrated byFIG.1, the mold compound20may cover the sides of the die. Specifically, the mold compound20may cover a third side34of the die4, a fourth side36of the die4, a fifth side (oriented as going into the page inFIG.1) of the die, and a sixth side (oriented as coming off the page inFIG.1) of the die. In the implementation illustrated byFIG.1, the entirety of the sides of the die are covered by the mold compound20, however, in other implementations the sides of the die4may only partially be covered by a mold compound20, while in still other implementations the mold compound20may not cover the sides of the die4. In various implementations, a portion of the second side8of the die may be covered by a mold compound. The mold compound covering the second side of the die4may be the same or a separate mold compound from the mold compound20. In such implementations, the mold compound20may also cover the sides of the backmetal layer18in implementations where the backmetal layer is the same length as or shorter than the length of the die4.

Referring toFIG.2, a cross-section side view of a second implementation of a semiconductor package is illustrated. The semiconductor package ofFIG.2may be similar to the semiconductor package ofFIG.1, with the difference being that the backside metal layer40may extend beyond the length of the die42and may be coextensive with the sides/perimeter of the semiconductor package38. Further, as illustrated byFIG.2, the backside metal layer40may include multiple layers, and in particular implementations, may include three layers. The backside metal layer may include, by non-limiting example, a metal or metal alloy including titanium, nickel, silver, vanadium, copper, and any combination thereof. In particular implementations, the backmetal layer40may include a layer including titanium, a layer including nickel, and a layer including a silver copper alloy. In other particular implementations, the backmetal layer may include a layer including titanium, a layer including a nickel vanadium alloy, and a layer including a silver-copper alloy.

Referring toFIGS.3A-3G, cross-section side views of a semiconductor device following various steps of an implementation of a method for forming the semiconductor package ofFIG.1are illustrated. Referring specifically toFIGS.3A-3B, a method for forming the semiconductor package ofFIG.1may include forming a plurality of bumps/studs44on a first side46of a wafer48. More specifically, the method may include forming a third metal50on the first side46of the wafer48. The third metal layer50may be any metal disclosed herein, and in particular implementations, may include aluminum. The third metal layer50may be patterned, as illustrated byFIG.3A, however, in other implementations the third metal layer may not necessarily be patterned.

Referring toFIG.3B, the method may include forming a first metal layer52over the third metal layer50. The first metal layer52may be any metal disclosed herein, and in particular implementations, includes copper. The first metal layer52may be patterned, as illustrated byFIG.3B, however, in other implementations the first metal layer may not be patterned. In various implementations, the method may also include forming a second metal layer54over the first metal layer52. The second metal layer54may be any metal disclosed herein, and in particular implementations, includes tin. The second metal layer54may also include a solder material. The second metal layer54may be patterned as illustrated byFIG.3B, however, in other implementations where additional conductive layers cover the second metal layer54, the second metal layer may not necessarily be patterned.

In various implementations, the method for forming the semiconductor package ofFIG.1includes forming non-patterned metal layers over the first side46of the wafer48. The method may then include etching through any number of the metal layers, including all of the metal layers coupled over the first side46of the wafer48, in order to form the plurality of bumps44. In various implementations, less than three metal layers may be coupled over the first side46of the wafer48, and in particular implementations, only a single metal layer may be formed and coupled directly to the first side46of the wafer48. In other implementations, more than three metal layers may be formed over the first side46of the wafer48. The metal layers coupled to the first side46of the wafer48may be used to form any number of bumps over the wafer.

Referring specifically toFIG.3B, the method for forming the semiconductor package ofFIG.1may include forming a plurality of recesses56into the first side46of the wafer48to a desired depth into the wafer. In particular implementations, the depth of each recess of the plurality of recesses56may be less than 50 um, while in other implementations the depth may be 50 or more micrometers depending on the thickness of the wafer. In various implementations, the plurality of recesses56may be formed using a saw, a laser, a plasma etch, a chemical etch, or any other method for forming a recess in a wafer. In implementations where an etch is used, the etch may be an etching process marketed under the tradename BOSCH® (the “Bosch process”) by Robert Bosch GmbH, Stuttgart, Germany, may be used to form the plurality of recesses56in the wafer48. In such implementations, the sidewalls of the plurality of recesses56may be slightly patterned or ridged which may facilitate adhesion of a mold compound to the sidewalls of the plurality of recesses56. In various implementations, the plurality of recesses56may be positioned in the wafer48so that they are between the semiconductor devices in the wafer.

Referring toFIG.3C, the method for forming the semiconductor package ofFIG.1includes applying a mold compound58to the first side46of the wafer48. The mold compound may include any type of mold compound disclosed herein and may be applied using, by non-limiting example, a liquid dispensing technique, a transfer molding technique, a vacuum molding technique, a glob top molding technique, or a compression molding technique. In various implementations, and as illustrated byFIG.3C, the mold compound58may encapsulate the plurality of bumps44and fill the plurality of recesses56. In other implementations, the mold compound58may only be applied within the plurality of recesses56and between the plurality of bumps44without flowing over the outer surfaces60of the plurality of bumps44.

Referring toFIG.3D, the method for forming the semiconductor package ofFIG.1may include thinning a second side62of the wafer48to the desired depth of the plurality of recesses56. In particular implementations, the method may include backgrinding a second side62of the wafer48to reach the plurality of recesses56and singulate a plurality of die64from the wafer. In implementations where the second side62of the wafer48is background, the backgrinding may use a process marketed under the trade name TAIKO by DISCO of Tokyo, Japan. The backgrinding leaves a ring of non-removed material (TAIKO ring) along the perimeter of the wafer which helps to prevent the wafer from curling, warping or otherwise bending during processing while at the same time removing most of the thickness and material of the second side62, or backside of the wafer48. The ring is then subsequently removed in a separate cutting step prior to singulation of the die. In other implementations of methods of forming semiconductor devices the TAIKO process may not be used, but some other backgrinding or other material-removal technique may be used, such as removing the material through a wet etch. In various implementations, the thinned wafer48, or plurality of die64, may be less than 50 um thick, while in other implementations the thinned wafer, or plurality of die, may be 50 or more um thick. The mold compound58coupled to the first side46of the wafer48and within the plurality of recesses56may facilitate thinning the wafer48by providing structural support to the wafer. In other implementations, the second side62of the wafer may not be thinned to the depth of the desired recesses56. In this manner, the die of each semiconductor package may be stepped upon singulating the wafer48.

Referring toFIG.3E, the method for forming the semiconductor package ofFIG.1may include coupling a backside metal layer66to the second side62of the wafer48or to the second side of the plurality of die64. The backside metal layer66may be any type of metal disclosed herein, and in particular implementations, may include copper. In various implementations, the backside metal layer may be coupled to the second side of the wafer through an electroplating process. In other implementations, the backside metal layer may be coupled to the second side of the wafer through a sputtering process or an electroplating process. In still other implementations, the backside metal layer may be a metal frame/film coupled to the wafer through, by non-limiting example, sintering, soldering, or fusion bonding. In various implementations, the backside metal layer66may be a thick backside metal layer and in particular implementations, may be as thick as or thicker than the thinned wafer48. In various implementations, the method for forming the semiconductor package ofFIG.1may include forming a plurality of openings68in the backside metal layer66. In other implementations, the backside metal layer66may not include any openings therein. In implementations where a plurality of openings68are formed in the backside metal layer66, the method may include, though not illustrated, applying a second mold compound to the second side62of the wafer48that fills the plurality of openings68. The second mold compound may be the same as or different from the first mold compound58. In various implementations, the second mold compound may also encapsulate the backside metal layer66. In such implementations, the method may include backgrinding the second mold compound to expose the backside metal layer. In implementations with the second mold compound applied to the second side62of the wafer48, the entirety of the die of the singulated semiconductor may be at least partially covered by a mold compound on all six sides of the die. In implementations where the second side62of the wafer48is background using the Taiko process, the Taiko ring may be removed after the backside metal is coupled to/formed on the second side of the wafer using a separate singulation process.

Referring toFIG.3F, the method for forming the semiconductor package ofFIG.1may include exposing the outer surface60of the plurality of bumps44through the mold compound58by grinding the mold compound58. In various implementations, only the mold compound may be ground until it is coextensive with the surface60, however, in other implementations the mold compound and a portion of the plurality of bumps44may be ground together. In this manner, the method may include planarizing the outer surface60of the plurality of bumps44with the outer surface70of the mold compound58. The backmetal layer66may facilitate the thinning of the mold compound58by adding structural support to the wafer48and the plurality of die64. In various implementations, and as illustrated by the order ofFIGS.3C-3F, the second side62of the wafer48may be thinned before the mold compound58is ground to expose the plurality of bumps44, however, in other implementations the method may include grinding the mold compound58to expose the plurality of bumps before the second side62of the wafer48is thinned.

Referring toFIG.3G, the method for forming the semiconductor package ofFIG.1includes singulating the mold compound58through the plurality of recesses56into a plurality of semiconductor packages71. The mold compound may be singulated using a saw, a laser, a plasma etch, water jet cutting, a chemical etch, or any other method for cutting or removing mold compound. In various implementations, the singulation line (or the width of the cut/etch made to singulate the mold compound) may be less wide as compared to the width of each recess of the plurality of recesses56. In such implementations, the sidewalls of each die of the plurality of semiconductor packages may be covered by the mold compound58. In implementations where the backside metal is not patterned, the backside metal may be singulated along with the mold compound to form the plurality of semiconductor packages.

Referring toFIGS.4A-4C, cross-section side views of a semiconductor device after steps of an implementation of a method for forming the semiconductor package ofFIG.2are illustrated. Referring specifically toFIG.4A, the method for forming the semiconductor package ofFIG.2may be similar to the method illustrated inFIGS.3A-3G, with the difference being that the method may include coupling a backside metal layer72to the second side74of the wafer76(or coupling a backside metal layer to a second side of the plurality of die), with the backside metal layer including multiple backside metal layers. In the implementation illustrated byFIG.4Athe method includes coupling a backside metal layer72which includes three different backside metal layers. In various implementations, the backside metal layer72may include more than or less than three backside metal layers. Each layer of the backside metal layer may be deposited to the wafer through, by non-limiting example, a sputtering or evaporation technique. In various implementations, the backside metal layer may include, by non-limiting example, titanium, nickel, silver, copper, vanadium, or any other metal. In particular implementations, the backside metal layer may include a titanium layer, a nickel layer, and a silver-copper layer. In other particular implementations, the backside metal layer may include a titanium layer, a nickel-vanadium layer, and a silver-copper layer. In various implementations, and as illustrated byFIG.4A, the backside metal layer72may be patterned or may not be patterned.

Referring toFIG.4B, the method for forming the semiconductor package ofFIG.2may include exposing the plurality of bumps78through the mold compound80by grinding the mold compound. The plurality of bumps may be exposed using the same method or a similar method as described above in relation toFIG.3F.

Referring toFIGS.4A and4C, the method for forming the semiconductor package ofFIG.2includes singulating the mold compound80through the plurality of recesses82and the backside metal layer72into a plurality of semiconductor packages84. The mold compound80and the backside metal layer72may be singulated using any method disclosed herein. As the backside metal layer is not patterned, the sidewalls of the backside metal layer may be coextensive with the sides of the respective semiconductor packages84.

The methods for forming semiconductor packages disclosed herein may allow for the formation of thin die without needing a dual metallization process for the purpose of stress balance. The mold compound and the backside metal layer may offer the necessary support needed to handle the thinned die and wafer during formation of the semiconductor packages.

In places where the description above refers to particular implementations of semiconductor packages and implementing components, sub-components, methods and sub-methods, it should be readily apparent that a number of modifications may be made without departing from the spirit thereof and that these implementations, implementing components, sub-components, methods and sub-methods may be applied to other semiconductor packages.