Patent ID: 12216751

In the drawings like reference numerals are used to indicate like elements.

SPECIFIC DESCRIPTION

Embodiments of the present disclosure are directed at design and manufacture of the layers of a pixel structure comprised in a touch sensitive surface.

FIG.1illustrates a sensor apparatus1having a sensor array10in which the pixel structure12of the present disclosure may be incorporated. An exemplary structure of a pixel12is shown in a detailed view in Inset A.FIG.2shows a similar sensor apparatus1comprising an alternative pixel structure12′, which is shown in Inset B.FIGS.1and2will be described together below.

The pixel array10comprises a plurality of touch sensitive pixels12,12′. Typically, other than in respect of its position in the array, each pixel12,12′ is identical to the others in the array10. As illustrated, each pixel12,12′ comprises a capacitive sensing electrode14for accumulating a charge in response to proximity of the surface of a conductive object to be sensed and a thin film transistor (TFT)20, the structure of which may be as illustrated in Inset A (top gate) or B (bottom gate) ofFIGS.1and2respectively.

A dielectric shield8provides the substrate on which layers of the pixel may be disposed. For example, a capacitive sensing electrode14and a TFT20may be “stacked” in layers on top of the dielectric shield8, wherein the dielectric shield8is the substrate/carrier.

The pixel array10comprises rows and columns of adjacent individual pixels12,12′. Individual pixels12,12′ are capable of being individually addressed. The size of each individual pixel12,12′ can be between 50 μm×50 μm and 125 μm×125 μm and is typically approximately square. The smaller the pixel area is, the greater the resolution that can be achieved. An example resolution is 500 pixels-per-inch (PPI), but the resolution can be in the range of between 500 PPI and 200 PPI. The resolution is variable and depends on the desired functionality of the array as well as the pixel area.

Typical geometry of the pixels in an array might be: for a resolution of 500 PPI, the pixels having a size of 50 μm×50 μm; for 300 PPI the pixels being 85 μm×85 μm in size; for 250 PPI the pixels being 100 μm×100 μm in size; and for a resolution of 200 PPI the pixels having a size of 125 μm×125 μm.

The structure of each individual pixel12,12′ stacked on the dielectric shield8, the dielectric shied having a thickness of less than 100 μm, comprises a capacitive sensing electrode14having a thickness between 10 nm and 1 μm, depending on the desired resistance, coupled to a TFT20with a thickness of a few hundred nanometers (depending on the precise materials and processes used). The capacitive sensing electrode14is disposed between the dielectric shield8and TFT20, and is connected to the TFT20by a conductive via40.

The capacitive sensing electrode14may be spaced away from the TFT20by an insulating layer42, for example a passivation layer or dielectric layer, by a distance of between 200-500 nm and 1-2 μm depending on the material and deposition method used. The insulating/passivation layer42may comprise an insulator material such as inorganic silicon nitride.

The conductive via40is disposed through the passivation layer42and/or the gate insulator layer36(depending on the TFT20configuration) to connect the capacitive sensing electrode14to the TFT20.

A top gate TFT, as shown by20(a) inFIG.1comprises: a first metalized layer comprising, for example, a source region30, and a drain region32; an active layer34disposed between the regions of the first metal layer; an insulating layer36, or gate insulator layer, disposed on the active layer34and first metal layer; and a second metal layer38, for example a gate region38, disposed on and separated from the source30, drain32and active34regions by the insulating layer. The first metal layer comprises a source region30and a drain region32, which are separated from one another. The first metal layer is adjacent the active layer34, for example a channel region34, which comprises a semiconductor. The active/channel layer is adjacent the gate insulator layer36, which comprises a dielectric. A second metal layer, adjacent the insulating layer36comprises a gate region38. The structure of the TFT20is such that the first and second metal layers are separated by the gate insulator layer36.

A TFT, as shown in20(b) inFIG.2shows a bottom gate TFT which can be fabricated by an alternative process order comprising: a first metal layer comprising, for example a gate region38; a gate insulator layer36disposed over the gate region38such that the gate region is covered by the insulating layer; an active layer34disposed over the insulating layer36; and a second metal layer comprising, for example, a source region30, and a drain region32. In both top gate and bottom gate configurations, the source and drain regions comprise metallic islands and are separated such that they are electrically/ohmically isolated in an “off” state. In an “on” state, the active region, comprising a semiconductor, provides a conductive path between the source and drain regions. The insulating layer36shields the first metalized layer from the second metalized layer in both top gate and bottom gate configurations.

The TFT20may be encapsulated by an additional passivation layer, for example a protective layer,44once it has been deposited in the stack on the dielectric shield8acting as the substrate.

The source region30and drain region32are connected by the active layer/channel region34comprising a semiconductor. The layer of metal which provides the source and drain regions of the TFT20can be referred to as a source-drain layer of the pixel. The source region30comprises a conductor and is connected to an input of the pixel. The drain region32also comprises a conductive material, and is typically made from the same material as the source region30for ease of manufacture. The drain region32is connected to an output of the pixel. The channel region, or active region,34comprises a thin film semi-conductor which provides a conduction path between the source30and drain32regions when biased or in an “on” state.

The conductive via40may connect the capacitive sensing electrode14to the drain region32of the TFT20.

In instances where the insulating/passivation layer42is on the thinner end of the range (200-500 nm), the TFT20may be a bottom gate TFT (FIG.2), such that the conductive via40passes through both insulating/passivation layer42and gate insulator layer36(of TFT20). In instances where the insulating layer42is thicker (1-2 μm), the TFT20may be a top gate TFT (FIG.1) such that the conductive via40passes only through the insulator layer42. These arrangements may provide improved performance of the capacitive sensing electrode14, although it will be appreciated that either can be used.

The spacing distance of the capacitive sensing electrode14from the TFT20“shields” the electronic circuit (or pixel circuit) from any external interference, for example from a resulting electromagnetic field. The electrode14and the spacing together provide the shielding effect.

In addition to each of the pixels12,12′ in pixel array10, such a pixel apparatus1comprises a gate drive circuit26, and a read out circuit24. The gate drive circuit26and the read out circuit24are connected to the TFT20of the pixel12,12′ via gate lines (rows) and source/data lines (columns) of the same conductive material as the source, drain and gate regions, such that a pixel can be individually addressed.

A connector25for connection to a host device may also be included. The connector carries a host interface27, such as a plug or socket, for example a flexf oil with a connector, for connecting the conductive lines in the connector to signal channels of a host device in which the pixel apparatus1is to be included.

The host interface27is connected by the connector25to the read out circuit24. A controller is connected to the gate drive circuit26for operating the pixel array, and to the read out circuit24for obtaining signals indicative of self-capacitance measured by pixels of the pixel array10.

Each pixel12,12′ can be individually addressed by virtue of the gate drive circuit26, which comprises a plurality of gate drive channels and is configured to activate the gate drive channels in sequence. The connector25is provided by a multi-channel connector having a plurality of conductive lines. This can be flexible, and may comprise a connector such as a flexi, or flexi-rigid PCB, a ribbon cable or similar.

The plurality of layers of the pixel12,12′ are disposed on the substrate, for example the dielectric shield8, using a plurality of techniques described later. The capacitive sensing electrode14and the TFT20being disposed on the dielectric shield8may improve encapsulation and may increase sensitivity to the object to be sensed, as well as performance of the pixel compared to previous pixels, whereby the dielectric shield does not provide the substrate. By disposing the layers of the pixel12onto the carrier substrate, the carrier substrate being the dielectric shield8, encapsulation may be improved. The method of manufacture of the pixel12,12′ can also simplified, in particular for large-area arrays.

The TFT20layers of the pixel can also be deposited onto the substrate, wherein the capacitive sensing electrode14is disposed between the TFT20and the dielectric shield8. Beneficially, the manufacturing process can be further simplified using this technique and pixel performance may be further enhanced by improving alignment, for example, as well as mechanical, thermal, UV-light sensitivity and electromagnetic field protection.

The combined elements of the sensor apparatus work to sense an interaction with the pixel array10at one or more pixels12,12′.

The pixel array10disposed on the dielectric shield8in the sensor apparatus1provides a sensor, for example an active area defined by the pixels12,12′, to be touched by an object50to be sensed. The capacitive sensing electrode14is adjacent to the first surface8aof the dielectric shield8. A change of capacitance in the capacitive sensing electrode14occurs when the second surface8bof the dielectric shield8is touched or an object50is sensed. Depositing the capacitive sensing electrode14adjacent to the first surface8aof the dielectric shield may advantageously provide greater sensitivity to the object50to be sensed. Sensing the object50comprises determining a change in capacitance of a pixel12,12′ (or pixels) in the pixel array10.

The pixels12,12′ can be arranged in a grid, for example a matrix, construction and are typically arranged linearly to simplify manufacturing. Linear arrangements in particular provides ease of manufacture when scaling up the array size, although the pixel array10is not limited to such a configuration. An image, for example a fingerprint image, may be built up by the same configuration of pixels.

Pixels may be addressed by a passive matrix, active matrix or multiplexing system, which can depend on physical aspects, such as device size, or for example the purpose of the sensing apparatus. Where fingerprint sensing is the main purpose, configurations comprising active matrix addressing may be preferable and multiplexing may provide better performance for, in particular, larger arrays.

The pixel array10dimensions range from 1 cm×1 cm to 100 cm×100 cm, preferably wherein the array is between 3.2 cm×2.4 cm and 50 cm×50 cm, more preferably wherein the array is between 6.4 cm×4.8 cm and 13 cm×8 cm. The pixel array10is not limited to being in a square or rectangular configuration and may take any shape, the dimensions are adjusted depending on the desired active area depending on the intended use of the pixel apparatus1.

Optionally, each pixel12,12′ in the array10may also comprise a reference capacitor. The reference capacitor may have a first plate connected to one of the metalized layers (i.e. the source-drain layer of the TFT20) and a second plate. The second plate, for example a separate metal island, may be made from the same material as, and in line with, the metal gate38whilst being electrically unconnected to the gate38and separated from the first plate by the insulator layer36. The reference capacitor may be deposited simultaneously with the metalized and insulator layers of the TFT20for ease of manufacture. The reference capacitor may help to reduce the influence of parasitic capacitance in the pixel array10and may also enable touch capacitance measurement.

FIG.3illustrates a possible interaction between an object50to be sensed and the pixel apparatus1. The pixel apparatus1inFIG.3has been rotated about the axis X labelled inFIGS.1and2. The sensor apparatus is configured with the pixel array ofFIGS.1and2disposed on the surface8a.

The object to be sensed50may come into contact with a top surface8bcomprising a dielectric shield8. The sensor apparatus1, and in particular the pixel array10, may be disposed on the opposite (or bottom) surface of the dielectric shield8ato the surface to be touched.

A pixel12,12′ in the exemplary configuration ofFIG.3, although it is not illustrated, comprises the capacitive sensing electrode14disposed on the first surface8aof the dielectric shield8, between the object to be sensed50and the TFT20of the pixel12,12′.

In fabricating the pixel apparatus1, the dielectric shield8may be the substrate onto which the pixels12,12′ in the pixel array10and the other components, such as the read out circuit24and the drive circuit26are disposed. The dielectric shield is planar; having two surfaces. The first surface8aof the dielectric shield8is the surface on which the layers of the pixel array10, including each individual pixel12,12′ are disposed. The second surface8bof the dielectric shield8is a surface to be touched by an object to be sensed. The object may be a finger, for example, as shown inFIG.3.

The pixel array10disposed on the dielectric shield8provides a surface to be touched and is, for example, one or more of: a screen, a dedicated segment of a screen, or an integrated area of a device. A typical device having the pixel apparatus might be a phone, laptop, TV or computer screen, or part of a touch sensitive security panel that may be used as a key to gain entry, for example, through a door. As technology develops, more and more surfaces are becoming interactive. The pixel array10can be integrated on any such device by virtue of the flexibility in the dimensions of the array. If the dielectric shield is thin and flexible, the sensing apparatus can also be shaped.

The second surface8bof the dielectric shield8may not have to be touched by an object in order to be sensed; a gesture or touch action may be sufficient to detect a signal.

FIG.4aillustrates a coplanar arrangement of a top gate TFT20(c) andFIG.4billustrates a coplanar bottom gate TFT20(d). The structure of the TFTs will be described in more detail below, also in relation to the TFTs20(a) and20(b) as illustrated inFIGS.1and2. The specific orientation and geometry of the TFT20(a-d) does not affect the performance of the pixel12,12′ and may be any one of the illustrated configurations.

The source30, drain32and channel34regions can be coplanar or staggered.FIGS.1and2show a staggered top gate TFT20(a) and bottom gate TFT20(b) respectively, whilstFIGS.4aand4billustrate coplanar arrangements.

A staggered top gate TFT20(a) (FIG.1) and a coplanar top gate TFT20(c) (FIG.4a) comprise the gate region38, or gate layer, disposed on top of the source-drain layer30,32, the active channel region34, and the gate insulator layer36. A staggered bottom gate TFT20(b) (FIG.2) or a coplanar bottom gate TFT20(d) (FIG.4b) comprises the source-drain layer disposed on top of the gate layer38, the gate insulator36and the active channel region34. The difference between coplanar and staggered arrangements is the method of manufacture; there is no functional difference.

Either a top gate TFT, bottom gate TFT, coplanar or staggered structure, can be used in combination with the capacitive sensing electrode14disposed on the dielectric shield8in each pixel12,12′. However, in a pixel array10, a single TFT arrangement is present, with each individual pixel12,12′ within the array being identical in structure to the other pixels in the array. The dielectric layer36, also known as a gate insulator layer, is between the gate layer and the source-drain layer in both arrangements.

FIG.5illustrates method steps that are taken to fabricate a pixel12for the pixel apparatus1.

Techniques used to deposit the layers comprise chemical vapour deposition (CVD), plasma enhanced CVD (PECVD), sputtering, spin coating, spray techniques, ink jet or flexo printing, patch coating, wet and/or dry etching, atomic layer deposition, or lithography techniques. It will be appreciated that other deposition methods may be used to deposit the layers onto the surface of the substrate, and that one or more of the techniques might be used in any combination.

In step500, the capacitive sensing electrode14is deposited on a first surface8aof the dielectric shield8.

The dielectric shield8that provides the support of the pixel apparatus1comprises an insulator having a high epsilon value such as glass (sodalime, bora-silicate, quarts/SiO2) but may also comprise a flexible substrate material such as flex-foil sheets and/or flex-foil substrates (Poly Imide (PI), PET, PEN, or other suitable polymers, or metal foils/plates with insulator coatings, etc.). Other appropriate insulating, and optionally transparent materials can also be used as the substrate. In addition, the material can be mechanically grinded and/or chemically etched to desired thickness. The thickness is preferably less than 100 μm.

The capacitive sensing electrode14comprises a dielectric layer disposed between two electrodes. The electrodes comprise a conductive material such as indium tin oxide or fluorine tin oxide, or another material that has high transparency; if transparency of the capacitive sensing electrode14is a desired quality of the pixel apparatus1. Other possible materials include copper, printed inks or other standard metal layers including: Al, an Al-alloy (e.g. AlNd), ITO, Moly, etc.

Step510is a step in which an insulating/passivation layer is deposited. The insulating layer is deposited over the capacitive sensing electrode and comprises a material such as inorganic silicon nitride.

In step520, a TFT20is fabricated. The TFT20can be fabricated over the insulating layer deposited in step510.

The source30, drain32and gate28regions are typically metallic, such as Al, AlNd or Mo, and can be made to be transparent by using indium tin oxide, for example. The channel region comprises a semiconductor material such as amorphous/microcrystalline silicon/polysilicon, cadmium selenide, zinc oxide or hafnium oxide or another suitable metal oxide and may have a thickness of a few hundred nanometers depending on the material used and the process used to deposit it. Organic materials may also be used.

Methods of manufacture of a TFT20comprises any of: sputtering, spin coating, spray techniques, inkjet printing, etching or CVD in particular PECVD which allows lower operating temperatures. Other methods such as lithography techniques may also be used. It will be appreciated that there are a number of techniques and methods that can used to fabricate a TFT20. There are also a number of different structures that can be fabricated.

TFTs are fabricated on a substrate, which may typically be insulating, for example, the dielectric shield8, electrode layer14and the insulator42. The layers are deposited using a number of techniques as described above. Main components of a TFT20comprise: a dielectric; a channel region/semiconductor layer; and source, drain and gate regions, which act as electrodes. The source and drain regions contact the channel region and are connected by it in an “on” state. The gate region is separated from the source, drain and gate regions by a gate insulator layer.

Fabricating a staggered top gate TFT20(a) as illustrated inFIG.1will be described herein below. A similar process comprising the steps in a different order is used in fabricating a bottom gate TFT. Coplanar arrangements can also be fabricated using the below described steps.

A first step comprises depositing the source-drain layer by depositing a conductor material. The source-drain layer comprises a source region and a drain region, which are conducting and act as electrodes. A degree of patterning may be required to deposit the source and drain regions in the desired locations with the desired geometry and dimensions over the channel region. Channel length L, which separates the source region30from the drain region32, varies from 2-3 μm to 10 μm. Channel width W varies from 2-3 μm up to larger values of up to between 10 μm and 50 μm or more. The W/L ratio determines the electrical behaviour.

A second step comprises depositing a channel region in a channel layer of the TFT20. The channel region comprises a semi-conductor material, and fills the channel region L, W between the source and drain regions of the first metalized layer. The channel region may be deposited in a homogeneous, planar deposition, with a thickness of a few hundred nanometers.

A third step comprises depositing a gate insulator layer. The gate insulator layer separates the gate region from the source, drain and channel regions. The gate insulator layer may be deposited by a homogeneous planar deposition across the array area, with a thickness of a few hundred nanometers.

A fourth step comprises depositing a gate region made from a conductive material. A degree of patterning may be required to deposit the gate region in the desired location with the desired geometry and dimensions over the gate insulator layer. The gate region needs to cover the above mentioned channel L and W. So may typically be slightly larger than these dimensions by a couple of micrometers.

A final step comprises depositing an insulating coating44, for example a protective layer or shield, over the TFT layers to encapsulate and protect them. This coating may be made using a glob top encapsulating material, and may be quite thick so processes such as spin coating may be appropriate.

Step530is an optional step, which may be performed in parallel with step520. A reference capacitor comprising a first and a second plate is deposited. The first and second plates of the reference capacitor may be connected to the drain region32of the TFT20and a common electrode, Worn, comprising a metal island in line with the gate region38, and may be deposited simultaneously with the metalized layers of the TFT20. When deposited simultaneously, the first plate is deposited concurrently with the source30and drain32regions of the TFT20and the second plate is deposited concurrently with the gate region38.

Advantageously, by depositing the plates of the reference capacitor concurrently with the TFT20, the total number of manufacturing steps of the pixel may be reduced, beneficially decreasing fabrication time. The accuracy and performance of the resulting pixel may also be improved, for example, by improvements in alignment and connectivity.

In step540, the capacitive sensing electrode14deposited on the dielectric shield8is coupled to the TFT20. A conductive via40is fabricated and connects the capacitive sensing electrode14to the TFT20. Fabrication of the conductive via40is integrated with steps520and530above and depends on whether the TFT is a top gate or bottom gate TFT. After deposition of insulating layer42(FIG.1—top gate configuration) or gate insulator layer36(FIG.2—bottom gate configuration), a hole is made in the respective layer(s) via lithography. During deposition of the metalized source-drain layer30/32, the hole is filled with the same metal as the metalized layer and connects the capacitive sensing electrode14to the drain region32. Techniques such as lithography or wet etching can be used to create a passage for the via40, into which the conductive material may be deposited. Via material is typically the same as the metal as used for the source-drain layer30/32. The conductive via40is typically made concurrently with the fabrication of the plurality of layers of the pixel.

It will be appreciated that it may be possible to alternatively fabricate the TFT20separately from the capacitive sensing electrode14disposed on the dielectric shield8and connect the two in an additional step. However, making an electrical connection, for example by connecting the via40between the TFT20and the capacitive sensing electrode14, may be difficult to achieve when using this alternative process.

FIG.6illustrates a pixel circuit, which can be formed from the above described structure and deposition methods. The circuit comprises a TFT30,32,38, a reference capacitor16and a capacitive sensing electrode14and is addressed by a gate line27and a source-data line28and outputs to a common line, for example a Vcomconnection. The TFT comprises a source region30, a drain region32and a gate region38.

The pixel structure described above comprises three conductive layers which may be provided by metallisation layers, such as those deposited in the above method. The first metallisation layer, m1, for example the layer deposited on the carrier substrate (the dielectric shield8), provides the capacitive sensing electrode14. A second metallisation layer, m2, in a top gate arrangement (seeFIG.1, Inset A), provides the source30and drain32region of the TFT20. One of the plates of the reference capacitor16is also provided by the second metallisation layer and can further be connected to the drain region32, which may also be provided by that same metallisation layer. The third metallisation layer, m3, comprises the gate electrode38. A second plate of the reference capacitor16may also be provided by the third metallisation layer, although it may be separated from the gate region38as it is inFIG.6, for example by patterning (for example by lithography or etching) during manufacture. In a bottom gate configuration (seeFIG.2, Inset B), the second and third metallisation layers are reversed. The conductive via40provides an electrical connection between the capacitive sensing electrode14and the drain region32of the TFT20, as can be seen inFIG.6.

As illustrated inFIG.6, the deposited metal layers denoted as m1, m2and m3adjacent the features of the circuit inFIG.6can be connected to form the circuit. The illustrated circuit components if the circuit diagram inFIG.6depicts both top gate and bottom gate arrangements. A top gate configuration is illustrated inFIG.6; it will be appreciated that m2and m3can be swapped in order to correspond to a bottom gate configuration.

It will be appreciated that the disclosure, as a whole, may be used to provide pixel circuits such as that described with reference toFIG.6. It will however also be appreciated in the context of the present disclosure that other circuits may also be used, whereby the layers of the pixel are connected in a different manner such that a different circuit is made. The fundamental layers and the method of deposition methods would remain substantially consistent with the above disclosed embodiments. Advantages achieved by using the surface to be touched in a touch sensor also as the substrate for deposition of the pixel stack may of course be provided in other pixel circuits.

Pixel structures of the present disclosure may find application is a sensor array (e.g. as described above). Figure

FIG.7shows a sensor apparatus2001in which the sensor array2010of the present disclosure may be incorporated.FIG.8illustrates a circuit diagram of one such sensor array2010. The description which follows shall refer toFIG.7andFIG.8together. It can be seen from an inspection ofFIG.7andFIG.8that inset C ofFIG.7shows a detailed view of one pixel of this array2010.

The sensor array2010comprises a plurality of touch sensitive pixels2012. Typically, other than in respect of its position in the array, each pixel2012is identical to the others in the array2010. As illustrated, each pixel2012comprises a capacitive sensing electrode2014for accumulating a charge in response to proximity of the surface of a conductive object to be sensed. A reference capacitor2016is connected between the capacitive sensing electrode2014and a connection to a gate drive channel2024-1of a gate drive circuit2024. Thus, a first plate of the reference capacitor2016is connected to the gate drive channel2024-1, and a second plate of the reference capacitor2016is connected to the capacitive sensing electrode2014.

Each pixel2012may also comprise a sense VCI (voltage controlled impedance)2020having a conduction path, and a control terminal (2022; inset C,FIG.7) for controlling the impedance of the conduction path. The conduction path of the sense VCI2020may connect the gate drive channel2024-1to an output of the pixel2012. The control terminal2022of the VCI is connected to the capacitive sensing electrode2014and to the second plate of the reference capacitor2016. Thus, in response to a control voltage applied by the gate drive channel2024-1, the reference capacitor2016and the capacitive sensing electrode2014act as a capacitive potential divider.

The capacitance of the capacitive sensing electrode2014depends on the proximity, to the capacitive sensing electrode2014, of a conductive surface of an object to be sensed. Thus, when a control voltage is applied to the first plate of the reference capacitor2016, the relative division of that voltage between that sensing electrode2014and the reference capacitor2016provides an indication of the proximity of the surface of that conductive object to the capacitive sensing electrode2014. This division of the control voltage provides an indicator voltage at the connection2018between the reference capacitor2016and the capacitive sensing electrode2014. This indicator voltage can be applied to the control terminal2022of the sense VCI2020to provide an output from the pixel2012which indicates proximity of the conductive object.

Pixels may be positioned sufficiently close together so as to be able to resolve contours of the skin such as those associated with epidermal ridges, for example those present in a fingerprint, palmprint or other identifying surface of the body. It will be appreciated in the context of the present disclosure that contours of the skin may comprise ridges, and valleys between those ridges. During touch sensing, the ridges may be relatively closer to a sensing electrode than the “valleys” between those ridges. Accordingly, the capacitance of a sensing electrode adjacent a ridge will be higher than that of a sensing electrode which is adjacent a valley. The description which follows explains how systems can be provided in which sensors of sufficiently high resolution to perform fingerprint and other biometric touch sensing may be provided over larger areas than has previously been possible.

As shown inFIG.7andFIG.8in addition to the sensor array2010, such a sensor may also comprise a dielectric shield2008, a gate drive circuit2024, and a read out circuit2026. A connector2025for connection to a host device may also be included. This may be provided by a multi-channel connector having a plurality of conductive lines. This may be flexible, and may comprise a connector such as a flexi, or flexi-rigid PCB, a ribbon cable or similar. The connector2025may carry a host interface2027, such as a plug or socket, for connecting the conductive lines in the connector to signal channels of a host device in which the sensor apparatus2001is to be included.

The host interface2027is connected by the connector2025to the read-out circuit2026. A controller (2006;FIG.8) may be connected to the gate drive circuit2024for operating the sensor array, and to the read-out circuit2026for obtaining signals indicative of the self-capacitance of pixels of the sensor array2010.

The dielectric shield2008is generally in the form of a sheet of an insulating material which may be transparent and flexible such as a polymer or glass. The dielectric shield2008may be flexible, and may be curved. An ‘active area’ of this shield overlies the sensor array2010. In some embodiments, the VCIs and other pixel components are carried on a separate substrate, and the shield2008overlies these components on their substrate. In other embodiments the shield2008provides the substrate for these components.

The sensor array2010may take any one of the variety of forms discussed herein. Different pixel designs may be used, typically however the pixels2012comprise at least a capacitive sensing electrode2014, a reference capacitor2016, and at least a sense VCI2020.

The array illustrated inFIG.8comprises a plurality of rows of pixels such as those illustrated inFIG.7. Also shown inFIG.8is the gate drive circuit2024, the read out circuit2026, and a controller2006. The controller2006is configured to provide a clock signal, e.g. a periodic trigger, to the gate drive circuit2024, and to the read-out circuit2026.

The gate drive circuit2024comprises a plurality of gate drive channels2024-1,2024-2,2024-3, which it is operable to control separately, e.g. independently. Each such gate drive channel2024-1,2024-2,2024-3comprises a voltage source arranged to provide a control voltage output. And each channel2024-1is connected to a corresponding row of pixels2012of the sensor array2010. In the arrangement shown inFIG.8each gate drive channel2024-1,2024-2,2024-3is connected to the first plate of the reference capacitor2016in each pixel2012of its row of the sensor array2010. During each clock cycle, the gate drive circuit2024is configured to activate one of the gate drive channels2024-1,2024-2,2024-3by applying a gate drive pulse to those pixels. Thus, over a series of cycles the channels (and hence the rows) are activated in sequence, and move from one step in this sequence to the next in response to the clock cycle from the controller2006.

The read-out circuit2026comprises a plurality of input channels2026-1,2026-2,2026-3. Each input channel2026-1,2026-2,2026-3is connected to a corresponding column of pixels2012in the sensor array2010. To provide these connections, the conduction path of the sense VCI2020in each pixel2012is connected to the input channel2026-1for the column.

Each input channel2026-1,2026-2,2026-3of the read out circuit2026may comprise an analogue front end (AFE) and an analogue-to-digital converter (ADC) for obtaining a digital signal from the column connected to that input channel2026-1. For example it may integrate the current applied to the input channel during the gate pulse to provide a measure of the current passed through the sense VCI2020of the active pixel2012in that column. The read out circuit2026may convert this signal to digital data using the ADC. Furthermore, the analogue front end performs impedance matching, signal filtering and other signal conditioning and may also provide a virtual reference.

In the sensor array2010shown inFIG.8, the conduction channel of the sense VCI2020in each pixel connects the input channel of the read out circuit for that column to the gate drive channel for the pixel's row. InFIG.8, the gate drive channel for the row thus provides a reference input. Operation of the sense VCI2020modulates this reference input to provide the pixel output. This output signal from a pixel indicates the charge stored on the capacitive sensing electrode2014in response to that reference input relative to that stored on the reference capacitor.

FIG.7includes a grid as a very schematic illustration of the rows and columns of pixels2012which make up the array. Typically this will be a rectilinear grid, and typically the rows and columns will be evenly spaced. For example the pixels may be square. It will of course be appreciated that the grid shown inFIG.7is not to scale. Typically the sensor array has a pixel spacing of at least 200 dots per inch, dpi (78 dots per cm). The pixel spacing may be at least 300 dpi (118 dots per cm), for example at least 500 dpi (196 dots per cm).

Operation of the sensor array2010ofFIG.8will now be described.

On each cycle of operation, the gate drive circuit2024and the read out circuit2026each receive a clock signal from the controller2006.

In response to this clock signal, the gate drive circuit operates one of the gate drive channels to apply a control voltage to one of the rows of the array. In each pixel in the row, the control voltage from the gate drive channel is applied to the series connection of the reference capacitor2016and the capacitive sensing electrode2014. The voltage at the connection2018between the two provides an indicator voltage indicating the proximity of a conductive surface of an object to be sensed to the capacitive sensing electrode2014. This indicator voltage may be applied to the control terminal of the sense VCI2020to control the impedance of the conduction path of the sense VCI2020. A current is thus provided through the conduction path of the sense VCI2020from the gate drive to the input channel for the pixel's column. This current is determined by the gate drive voltage, and by the impedance of the conduction channel.

In response to the same clock signal, the read-out circuit2026senses the pixel output signal at each input channel. This may be done by integrating the current received at each input of the read-out circuit2026over the time period of the gate pulse. The signal at each input channel, such as a voltage obtained by integrating the current from the corresponding column of the array, may be digitised (e.g. using an ADC). Thus, for each gate pulse, the read-out circuit2026obtains a set of digital signals, each signal corresponding to a column of the active row during that gate pulse. So the set of signals together represent the active row as a whole, and the output from each pixel being indicative of the charge stored on and/or the self-capacitance of the capacitive sensing electrode2014in that pixel.

Following this same process, each of the gate-drive channels is activated in sequence. This drives the sense VCI2020of each pixel connected to that channel into a conducting state for a selected time (typically the duration of one gate pulse). By activating the rows of the array in sequence the read out circuit, can scan the sensor array row-wise. Other pixel designs, other scan sequences, and other types of sensor array, may be used.

FIG.9illustrates another sensor array which may be used in the apparatus illustrated inFIG.7.

FIG.9shows a sensor array2010comprising a plurality of pixels, and a reference signal supply2028for supplying a reference signal to the pixels. This can avoid the need for the gate drive power supply also to provide the current necessary for the read-out signal.

Also shown inFIG.9is the gate drive circuit2024, the read-out circuit2026, and the controller2006.

The sensor array2010may also benefit from the inclusion of a reset circuit2032,2034in each pixel. This may allow the control terminal2022of the pixel to be pre-charged to a selected reset voltage whilst the pixel is inactive (e.g. while another row of the array is being activated by the application of a gate pulse to another, different, row of the array).

In these embodiments the sensor may also comprise a reset voltage provider2042for providing a reset voltage to each of the pixels2012of the array as described below. The reset voltage provider2042may comprise voltage source circuitry, which may be configured to provide a controllable voltage, and may be connected to the controller2006to enable the controller2006to adjust and fix the reset voltage.

The reset voltage may be selected to tune the sensitivity of the pixel. In particular, the output current of the sense VCI2020typically has a characteristic dependence on the indicator voltage at the control terminal2022and its switch-on voltage. Thus the reset voltage may be chosen based on the switch-on voltage of the sense VCI2020. The characteristic may also comprise a linear region in which it may be preferable to operate.

The pixels illustrated inFIG.9are similar to those illustrated inFIG.7andFIG.8in that each comprise a capacitive sensing electrode2014, and a reference capacitor2016connected with a capacitive sensing electrode2014. The connection between these two capacitances provides an indicator voltage, which can for example be connected to the control terminal2022of a sense VCI2020. In addition, the pixels of the sensor array illustrated inFIG.9also comprise a further two VCIs2034,2038, and a connection to the reset voltage provider2042, and a connection to the reference signal supply2028.

As noted above, the sense VCI2020is arranged substantially as described above with reference toFIG.7, in that its control terminal2022is connected to the connection between the reference capacitor2016and the capacitive sensing electrode2014. However, the conduction path of the sense VCI2020is connected differently inFIG.9than inFIG.7. In particular, the conduction channel of the select VCI2038connects the conduction channel of the sense VCI2020to the reference signal supply2028which provides a voltage Vref. Thus, the conduction channel of the sense VCI2020is connected in series between the conduction channel of the select VCI2038and the input of the read-out circuit for the column. The select VCI2038therefore acts as a switch that, when open, connects the sense VCI2020between, Vref, the reference signal supply2028and the input of the read-out circuit and, when closed, disconnects the sense VCI from the reference signal supply2028. In the interests of clarity, the connection between the conduction channel of the select VCI and Vref, the output of the reference signal supply2028is shown only in the top row of the array of pixels. The connection reference signal supply2028in the lower rows of the array is indicated in the drawing using the label Vref.

The select VCI2038is therefore operable to inhibit the provision of signal from any inactive pixel to the input of the read-out circuit2026. This can help to ensure that signal is only received from active pixels (e.g. those in the row to which the gate drive pulse is being applied).

In an embodiment each column of pixels is virtually connected to a ground or reference voltage. As such there may be no voltage differences on each of the columns thereby minimising parasitic capacitance. Furthermore, the reference signal supply may apply a current-drive rather than a voltage-drive which further reduces any effect parasitic capacitance could have on the signal applied by the active pixels on the inputs of the read-out circuit2026.

The gate drive channel for the pixel row is connected to the first plate of the reference capacitor2016, and to the control terminal of a select VCI2038. As in the pixel illustrated inFIG.7, andFIG.8, the connection to the reference capacitor2016and capacitor sensing electrode2014means that the gate drive voltage is divided between the reference capacitor2016and the capacitive sensing electrode2014to provide the indicator voltage which controls the sense VCI2020. The connection to the control terminal2040of the select VCI2038however means that, when the pixel is not active, the conduction path of the sense VCI2020is disconnected from the reference signal supply2028.

A control terminal2022of the sense VCI2020is connected to the second plate of the reference capacitor2016. The conduction path of the sense VCI2020connects the reference signal supply2028to the input of the read-out circuit2026for the pixel's column.

A conduction path of the reset VCI2034is connected between the second plate of the reference capacitor2016and a voltage output of the reset voltage provider, for receiving the reset voltage. The control terminal2032of the reset VCI2034is connected to a reset signal provider, such as the gate drive channel of another row of the sensor array. This can enable the reset VCI2034to discharge the reference capacitor2016during activation of another row of the array (e.g. a row of the array which is activated on the gate pulse prior to the pixel's row) or to pre-charge the control terminal2022of the sense VCI2020to the reset voltage.

Operation of the sensor array ofFIG.9will now be described.

The gate drive circuit2024and the read-out circuit2026each receive a clock signal from the controller2006. In response to this clock signal, the gate drive circuit2024activates a first gate drive channel of the gate drive circuit2024to provide a gate pulse to a row of the array2010. A control voltage is thus applied to the control terminal of the select VCI2038of the pixels in the first row (the active row during this gate pulse).

The control voltage is also applied to the control terminal of the reset VCI2034of the pixels in a second row (inactive during this gate pulse).

In the first row (the active row), the conduction channel of the select VCI2038is switched into a conducting state by the control voltage (e.g. that which is provided by the gate pulse). The conduction channel of the select VCI2038thus connects the conduction channel of the sense VCI2020to the reference signal supply2028.

The control voltage is also applied to the first plate of the reference capacitor2016. The relative division of voltage between the sensing electrode2014and the reference capacitor2016provides an indicator voltage at the connection between the reference capacitor2016and the capacitive sensing electrode2014as described above with reference toFIG.7andFIG.8. The indicator voltage is applied to the control terminal2022of the sense VCI2020to control the impedance of the conduction channel of the sense VCI2020. Thus, the sense VCI2020connects the reference signal supply2028to the input channel of the read-out circuit2026for that column, and presents an impedance between the two which indicates the capacitance of the capacitive sensing electrode2014. Please note, the reference signal supply may be provided by a constant voltage current supply.

A current is thus provided through the conduction path of the sense VCI2020from the reference signal supply2028to the input channel of the read-out circuit2026for the pixel's column. This current is determined by the voltage of the reference signal supply and by the impedance of the conduction channel of the sense VCI.

In response to the same clock signal from the controller2006, the read-out circuit2026senses the pixel output signal at each input channel (e.g. by integrating the current provided to each input channel), and digitises this signal. The integration time of the read-out circuit2026may match the duration of the gate pulse.

Thus, in each clock cycle, the read-out2026circuit obtains a set of digital signals, each signal corresponding to the signals sensed from each column of the active row during the gate pulse. The output from each pixel2012in the row (each channel during that gate pulse) being indicative of the charge stored on the capacitive sensing electrode in that pixel.

In the second (inactive) row the control voltage is applied to the control terminal2032of the reset VCI2034. This causes the reset VCI2034of the pixels in the inactive row to connect the second plate of their reference capacitors2016to a reset voltage provided by the reset voltage provider. This may discharge (e.g. at least partially remove) charge accumulated on the pixels of the inactive row, or it may charge them to the reset voltage, before they are next activated in a subsequent gate pulse. This reset voltage may be selected to tune the sensitivity of the pixels.

At the boundaries of the pixel array, where an N−1 gate line is not available, a dummy signal may be used to provide the control signal to the reset VCI. The gate drive circuit2024may provide the dummy signal. This may be provided by a gate drive channel which is only connected to the rest VCIs of a row at the boundary of the array, but not to any sense or select VCIs.

As illustrated inFIG.9, the reset VCI2034of the pixels may be connected to the gate drive circuit so that each row is discharged in this way by the gate pulse which activates the immediately preceding row, which may be an adjacent row of the array.

In other examples of pixel structures, a reference capacitor need not be provided.FIG.10illustrates one example pixel circuit in which a reference capacitor is not provided. This pixel circuit can be formed from the above described structure and deposition methods. The circuit comprises a TFT3030,3032,3038, and a capacitive sensing electrode3014. The pixel circuit may be addressed by a gate line3027and a source-data line3028, and outputs to a common line, for example a Vcom connection. The TFT comprises a source region3030, a drain region3032and a gate electrode3038. The gate line3027is connected to the gate electrode3038. The source region3030is connected to the source-data line3028. The capacitive sensing electrode is connected to the drain region3032, which is connected to the source region3030, as shown inFIG.10.

The example pixel circuit ofFIG.10may be provided by a layered pixel structure. For example the layered pixel structure may comprise three conductive layers m1, m2, m3are provided. These may be metallisation layers, such as those deposited in the above method. A first metallization layer m1provides the capacitive sensing electrode3014. The first metallization layer m1may be deposited on a carrier substrate, such as a dielectric shield. A second metallisation layer, m2, provides the source3030and drain3032region of the TFT. The second layer m2may be the type as would be provided in a top gate arrangement (see e.g.FIG.1, Inset A). A third metallisation layer, m3, provides the gate electrode3038. In a bottom gate configuration (seeFIG.2, Inset B), second and third metallisation layers are reversed. A conductive via may be provided to provide an electrical connection between the capacitive sensing electrode3014and the drain region3032of the TFT, as can be seen inFIG.10.

As illustrated inFIG.10, the deposited metal layers denoted as m1, m2and m3adjacent the features of the circuit inFIG.10can be connected to form the circuit. The illustrated circuit components of the circuit diagram inFIG.10may depict both top gate and bottom gate arrangements. A top gate configuration is illustrated inFIG.10, but it will be appreciated that m2and m3can be swapped in order to correspond to a bottom gate configuration.

In some examples, a reference capacitor could be included in the pixel circuit ofFIG.10. The reference capacitor may be connected to the drain region3032. For example, one of the plates of the reference capacitor may be provided by the second metallisation layer. A second plate of the reference capacitor may also be provided by the third metallisation layer. The second plate of the reference capacitor may be separated from the gate electrode3038, for example by patterning (e.g. lithography or etching) during manufacture.

It will be appreciated that the disclosure, as a whole, may be used to provide pixel circuits such as that described with reference toFIG.10, It will however also be appreciated in the context of the present disclosure that other circuits may also be used, whereby the layers of the pixel are connected in a different manner such that a different circuit is made. The fundamental layers and the method of deposition methods would remain substantially consistent with the above disclosed embodiments. Advantages achieved by using the surface to be touched in a touch sensor also as the substrate for deposition of the pixel stack may of course be provided in other pixel circuits.

It will be appreciated from the above description that many features of the different examples are interchangeable with one another. The disclosure extends to further examples comprising features from different examples combined together in ways not specifically mentioned. Indeed, there are many features presented in the above examples and it will be apparent to the skilled person that these may be advantageously combined with one another.

Certain features of the methods described herein may be implemented in hardware, and one or more functions of the apparatus may be implemented in method steps. It will also be appreciated in the context of the present disclosure that the methods described herein need not be performed in the order in which they are described, nor necessarily in the order in which they are depicted in the drawings. Accordingly, aspects of the disclosure which are described with reference to products or apparatus are also intended to be implemented as methods and vice versa. The methods described herein may be implemented in computer programs, or in hardware or in any combination thereof. Computer programs include software, middleware, firmware, and any combination thereof. Such programs may be provided as signals or network messages and may be recorded on computer readable media such as tangible computer readable media which may store the computer programs in non-transitory form. Hardware includes computers, handheld devices, programmable processors, general purpose processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), and arrays of logic gates.

The specification can be readily understood with reference to the following Numbered Paragraphs:Numbered Paragraph 1. A pixel structure comprising a plurality of layers for providing a touch sensitive pixel of a sensing array, the layers comprising:a thin film transistor; anda conductive layer deposited on a dielectric shield to be touched by an object to be sensed and arranged to provide a capacitive sensing electrode coupled to the thin film transistor.Numbered Paragraph 2. The pixel structure of Numbered Paragraph 1 wherein the dielectric shield provides a substrate on which the layers of the structure are disposed.Numbered Paragraph 3. The pixel structure of Numbered Paragraph 2 wherein the thin film transistor comprises a plurality of layers deposited on the capacitive sensing electrode.Numbered Paragraph 4. The pixel structure of any preceding Numbered Paragraph wherein the dielectric shield comprises a first surface to be touched by the object to be sensed; and wherein the capacitive sensing electrode is disposed on a second surface of the dielectric shield.Numbered Paragraph 5. The pixel structure of Numbered Paragraph 1 wherein an insulating layer separates the capacitive sensing electrode from the thin film transistor.Numbered Paragraph 6. The pixel structure of Numbered Paragraph 5 wherein the capacitive sensing electrode is connected to the thin film transistor by a conductive via through the insulating layer.Numbered Paragraph 7. The pixel structure of any preceding Numbered Paragraph wherein a source-drain layer of the pixel structure comprises a source region and a drain region of the thin film transistor.Numbered Paragraph 8. The pixel structure of Numbered Paragraph 7 comprising a channel region comprising a semiconductor, which connects the source region and the drain region of the thin film transistor in an “on” state.Numbered Paragraph 9. The pixel structure of any preceding Numbered Paragraph comprising a gate layer of the pixel structure comprising a gate region of the thin film transistor.Numbered Paragraph 10. The pixel structure of Numbered Paragraph 9 when dependent on Numbered Paragraph 7 or Numbered Paragraph 8 wherein the gate layer is disposed between the capacitive sensing electrode and the source-drain layer.Numbered Paragraph 11. The pixel structure of Numbered Paragraph 9 when dependent on Numbered Paragraph 7 or Numbered Paragraph 8 wherein the source-drain layer is disposed between the capacitive sensing electrode and the gate layer.Numbered Paragraph 12. The pixel structure of Numbered Paragraph 11 when dependent on Numbered Paragraph 6 wherein the conductive via connects the capacitive sensing electrode to the TFT.Numbered Paragraph 13. The pixel structure of any preceding Numbered Paragraph comprising a reference capacitor.Numbered Paragraph 14. The pixel structure of Numbered Paragraph 13 as dependent upon Numbered Paragraph 7, 8, or 9 wherein at least one of the source-drain layer and the gate layer are arranged to provide a plate of the reference capacitor.Numbered Paragraph 15. The pixel structure of any of Numbered Paragraphs 9 to 14 wherein the gate layer is connected to the capacitive sensing electrode.Numbered Paragraph 16. The pixel structure of any of Numbered Paragraphs 9 to 14 wherein the drain region is connected to the capacitive sensing electrode.Numbered Paragraph 17. The pixel structure of Numbered Paragraphs 13, 14 or 15 comprising an input for coupling a bias voltage to a first plate of the reference capacitor for pre charging the pixel.Numbered Paragraph 18. A method of manufacturing a pixel structure comprising a plurality of layers for providing a touch sensitive pixel of a touch sensitive array, the method comprising:depositing a conductive layer on a first surface of a dielectric shield and arranged to provide a capacitive sensing electrode, wherein the dielectric shield comprises a second surface, opposite to the first surface, and arranged to be touched by an object to be sensed by the pixel; andfabricating a thin film transistor wherein the thin film transistor is connected to the capacitive sensing electrode.Numbered Paragraph 19. The method of Numbered Paragraph 17, wherein the thin film transistor is fabricated over the capacitive sensing electrode.Numbered Paragraph 20. The method of any of Numbered Paragraphs 17 to 19 comprising:depositing a passivation layer between the capacitive sensing electrode and the thin film transistor.Numbered Paragraph 21. The method of Numbered Paragraph 19 wherein the connection between the capacitive sensing electrode and the thin film transistor comprises a conductive via through the insulating layer.Numbered Paragraph 22. The method of any of Numbered Paragraphs 17 to 21 wherein fabricating the thin film transistor comprises:depositing a source-drain layer and a gate layer;wherein the source-drain layer comprises a source region and a drain region of the thin film transistor; andwherein the gate layer comprises a gate region of the thin film transistor.Numbered Paragraph 23. The method of Numbered Paragraph 22 wherein fabricating the thin film transistor further comprises depositing a channel region adjacent the source-drain layer and a gate-insulator layer between the channel region and the gate layer.Numbered Paragraph 24. The method of any of Numbered Paragraphs 18 to 23 further comprising fabricating a reference capacitor arranged to be connected to the thin film transistor and the capacitive sensing electrode.Numbered Paragraph 25. The method of Numbered Paragraph 24 when dependent on Numbered Paragraph 22 or Numbered Paragraph 23 wherein a first plate of the reference capacitor is deposited simultaneously with the source-drain layer; anda second plate of the reference capacitor is deposited simultaneously with the gate layer.