Patent ID: 12261528

DETAILED DESCRIPTION

A detailed description of one or more embodiments of the disclosed apparatus and method are presented herein by way of exemplification and not limitation with reference to the Figures.

FIG.1shows an example of a generic buck converter100. This converter100will be used to show certain elements and to explain certain shortcomings thereof that embodiments disclosed herein may improve. The discussion ofFIG.1may be aided by additional reference toFIGS.2a-2cwhich show, respectively, load current during a reset of the load, current through the inductor Ls of the buck converter100and the output voltage of the buck converter100.

The buck converter100includes DC input102and that receives an input voltage from a DC voltage source106.

As illustrated, the buck converter100includes an input capacitor Cin across the DC input102that smooths the input voltage received from the DC voltage source106. The converter100provides a stepped down DC voltage that is lower than the input voltage at its output104. The voltage can be provided to a load110such as a digital signal processor (DSP) or a controller that, in one embodiment, can be an FPGA. The converter100can also be a single monolithic IC. Eg(LT8620)

The converter100also includes an output capacitor Cout across the output104to smooth the output. A switch112is connected between the DC input102and the inductor Ls. The inductor Ls is an energy storage element that is selectively switched into and out of electrical contract with the DC input102by the switch112. It is understood that a controller114can be provided to control the switch112and based on the duty cycle of the switch, control how much the converter100steps down voltage at the output104(Vout) from the voltage received at the DC input102(e.g., the voltage provided by voltage source106). As in known in the art, a control element116(such as a diode as illustrated or another transistor) can be provided that controls a direction current flow from the inductor Ls when Ls is disconnected from the source106.

In certain instances, the load110can require accurate voltage be provided to it. To that end, a voltage monitor (VMON)120can be provided to monitor the output voltage Vout provide to the load. If the voltage is too high above or too far below a set threshold the monitor can indicate that an abnormal condition has occurred. Optionally, to help reduce the chances of fast, transitory changes causes too many alarms, an alarm or “glitch” filter122can be provided. This filter is shown as an independent element but can be part of the voltage monitor120in some cases. The alarm filter122may require that the “alarm condition” (e.g., VMON120provides a positive or alarm output indication) remain for a period of time before an alarm is recognized as an actual alarm as opposed to an anomaly or a momentary voltage fluctuation that resolves in a timely manner such that the load does not need to be reset.

The inventors hereof have discovered that is some instances, the converter100can experience extreme load transients conditions. These conditions can make it difficult for the converter100to maintain its output voltage (e.g, to avoid tripping the voltage monitor120) under the following extreme load transient scenarios:a) Out of reset condition—load110draws large surge currents10A or higher typically within 1 usec; andb) Going to reset condition—load suddenly stops drawing current.

To address “condition (a)” type load transient, the buck converter100can be modified to respond faster by using higher switching frequency (e.g., per controller114) and using additional bulk capacitance at the output104. The additional capacitance (Cadd inFIG.1) is in addition to the output capacitance Cout and in connected across the output104. Cadd is not typically present in prior art buck converters.

However, it has been discovered by the inventors hereof that the addition of the bulk capacitance Cadd may reduce performance under “condition (b)” type load transient.

With reference now toFIGS.1and2a-2c, the larger output capacitance (Cadd) added to handle sudden demand in load under condition (a) type implies that large energy is stored in the output capacitor. Hence, under condition (b) type transient, when the load is suddenly removed (e.g., the load goes into reset), additional stored energy will take more time to discharge. This causes an initial overshoot and results in much larger settling time (greater than glitch time). This causes the voltage at buck converter output104to be above the over voltage trip threshold set by voltage monitor120. As mentioned above, the voltage monitor120can be any type of circuit that can monitor over and under voltage rail voltages (e.g, Vout) and provide indication whether they are within the allowable voltage levels or not. However, due to the reduced settling time caused by Cadd, the monitor may generate nuisance trips/incorrect indication that buck converter is faulty which is not acceptable in safety critical applications.

For example, considerFIGS.2a-2cwhich show various currents/voltages over time, as the load110enters reset. In the reset condition, the current drawn by the load110drops from an normal operating value (in this case, about 500 mA) to a nominal/almost zero level at time t1. Also, at t1, the current through the inductor Ls sees a dramatic drop. This drop is not quit as fast as the current drop across the load and smooths out at a time t2. In this case, t241can be about 0.1 ms but that is just an example. However, it is noted that inFIG.2cthe voltage across the output (Vout) has an initial rise (see peak202) that decays as capacitors Cout and Cadd discharge through the load. In the example shown, Vout does not get back to stable output until t3(about 1.3 ms after t2). This time, however, can result in faulty or nuisance trips as the time may be longer than that of the alarm filter122.

To mitigate this problem, traditionally designers put some additional constant load on the output rail so that output capacitors (Cout/Cadd) can discharge faster reducing the settling time or utilize a linear regulator based design. Both these options result in increased power consumption.

To address the above noted issues related to condition b above, provided is system in the form of a circuit300that provides a constant output that is a stepped down version of a voltage provide at its input. The circuit300includes a buck converter301as shown inFIG.3. The buck converter301includes the same elements as that ofFIG.1and includes further elements. It should be noted that the buck converter301can be modified from the exact circuit shown inFIGS.1/3as long as it provides a constant stepped down output voltage. For example, the diodes116/316could be replaced by a transistor or other type of current flow control device. It shall be understood that the circuit300can be connected to a DC voltage source and load (and other elements) to form a system as shown inFIG.3.

The circuit300may have reduced the settling time under “condition (b)” type load transient, so that incorrect fault indication is avoided in safety critical applications. This may allow for a simple buck regulator/converter to be used in safety critical applications where a fault has to be indicated quickly and correctly under “condition (b)” type load transient conditions.

The circuit300includes a buck converter301and a selectively connectable transient suppression circuit340. The buck converter301can be as above or may be modified. While describe in greater detail below, the suppression circuit340is connected between the DC output304of the buck converter and the load310. The suppression circuit340is an R/C circuit in one embodiment and is selectively connected into the circuit300(e.g., to the DC output304of the buck converter301) by a control switch SW1when a “condition (b)” type transient occurs. The suppression circuit340may reduce the overshoot and/or settling time across the output (Vout) and is connected for fixed duration. This duration can be selected based on the switching speed of the buck converter301.

The circuit300includes a DC input302that is configured to receive an input voltage from a DC voltage source306. Any DC voltage source discussed herein can be any source of a DC voltage such as, for example, a battery, a fly back converter, or DC rails to name but few.

The buck converter301shares this DC input302and, thus, is also configured to receive this a voltage across the DC input302and does so in operation. The buck converter301includes an input capacitor Cin across the DC input302that smooths the input voltage received from the DC voltage source306. Herein, the circuit is shown as having a positive rail360and neutral rail362that are fed by the DC voltage source306and define the DC input302. In operation, the converter301provides a stepped down DC voltage (Vout) at its DC output304that is lower than the voltage provided by DC voltage source306.

The voltage can be provided to a load310such as a digital signal processor (DSP) or a controller that, in one embodiment, can be an FPGA. The converter301also includes an output capacitor Cout across the DC output304to smooth the output. The converter301can also be a single monolithic IC, eg LT8620. Other portions of the system ofFIG.3can also be included in the same or a different IC including but not limited to, the selectively connectable transient suppression circuit, the dissipation circuit, and the suppression circuit switch are included in the integrated circuit all mentioned below.

An inductor Ls is connected between the DC input302and the DC output304as in a conventional buck converter. A control switch312is connected between the DC input302on the positive rail360and the inductor Ls. The inductor Ls is an energy storage element that is selectively switched into and out of electrical contact with the DC input302by the control switch312. It is understood that a controller314can be provided to control the control switch312and based on the duty cycle of the switch, control how much the converter301steps down voltage at the DC output304(Vout) from the voltage received at the DC input302(e.g, the voltage provided by the DC voltage source306). As in known in the art, a control element116(such as a diode as illustrated or another device such as transistor) can be connected between the rails360and362, to control the direction of current flow from the inductor Ls when Ls is disconnected from the DC voltage source306.

Similar to the above, a voltage monitor (VMON)320can be provided to monitor the output voltage Vout provided to the load310. If the voltage is too high (e.g., above threshold) or too low the VMON320can indicate that an abnormal condition has occurred. That is, the VMON320can provide an output that is based on the DC output304.

Optionally, to help reduce the chances of fast, transitory changes causes too many alarms, an alarm or glitch filter322can be provided. This filter is shown as an independent element but can be part of the voltage monitor320in some cases. The alarm filter322may require that the “alarm condition” (e.g., VMON320provides a positive or alarm output indication) remain for a period of time before an alarm is recognized as an actual alarm as opposed to an anomaly or a momentary voltage fluctuation that resolves in a timely manner such that the load does not need to be reset.

As in the above example, to address “condition (a)” type load transient discussed above, the buck converter301can includes additional bulk capacitance at the DC output304. The additional capacitance (Cadd inFIG.3) is in addition to the output capacitance Cout and in connected across the DC output304.

To address the reduction long settling time introduced by Cadd, provided herein is the selectively connectable transient suppression circuit340(suppression circuit for short). The suppression circuit340can be electrically connected into the circuit300in the event of reset of the load310in one embodiment.

As shown, the suppression circuit340is connected in parallel with the DC output304and the load310/VMON320. As shown, the suppression circuit340is connected between the DC output304and the load310. The exact location is, however, not so limited unless expressly stated in the claims below.

The selectively connectable transient suppression circuit340includes a trigger342that is connected to the output of the VMON320. That is, it is connected, in one embodiment, to the same signal provided to the alarm filter322. In operation, the trigger342will “hold” (on its output) the signal it receives at its input for specific amount to time. In this manner, the trigger342can be a mono-shot element/circuit. In one embodiment, the trigger342is a monostable multi-vibrator implemented either using IC based solution or discrete solution, which detects rising edge/falling edge based on the output of the VMON320and provides an ON output for a fixed duration.

The output of the trigger342is connected to a switch (SW1) and controls whether SW1is conductive or non-conductive. In one embodiment, the fixed duration that the trigger342forces SW1into the conductive (or ON) state is related to the switch frequency provided to the control switch312by the controller314. In one embodiment, the duration is about 30 switching cycles (e.g.,30xthe period of the signal provided to the control switch312. While the switch SW1is conductive, the suppression circuit340is electrically connected across the output DC304and when the switch SW1non-conductive, the suppression circuit340in not electrically connected across the output DC304and is thereby effectively electrically removed from the circuit. Herein, the switch SW1can also be called a suppression circuit control switch.

The suppression circuit340also includes a dissipation circuit370. The dissipation circuit is an RC circuit that includes charge capacitor Cchg serially connected to a current limiting resistor Rser. Cchg and Rser are serially connected between the positive rail and suppression circuit control switch SW1inFIG.3such that SW1controls current flow through Cchg and Rser. When SW1is closed charge balancing occurs between Cadd and Cchg resulting in overshoot limited to much smaller voltage that shown above and much faster settling time. Rser serves limit current through Cchg. The dissipation circuit370also includes a dissipation resistor Radd connected in parallel the serially connected Cchg and Rser to discharge the capacitor Cchg after SW1is in the returned to the non-conductive state (e.g., after the trigger342expired).

In this manner, wherein selectively connectable transient suppression circuit340is configured such that the suppression circuit switch SW1is configured to electrically connect the dissipation circuit370to the DC output304when the VMON320determines that the voltage across the DC output304is above a threshold (e.g., is out of range). Similarly, to disconnect, the suppression circuit switch SW1can electrically disconnect the dissipation circuit370from the DC output304when the VMON320determines that the voltage across the DC output304is below the threshold and that the trigger322time has expired.

FIGS.4a-4cshown a simulation of the circuit300during a condition (b)″ event.FIGS.4a-4cshow various currents/voltages over time as the load310enters reset. In the reset condition, the current drawn by the load310(FIG.4a) drops from a normal operating value (in this case, about 500 mA) to a nominal/almost zero level at time t1. Also, at t1, the current through the inductor Ls (FIG.4b) sees a dramatic drop.FIG.4cshows the voltage across the output (Vout) and has an initial rise (see peak402) that decays as capacitors Cout and Cadd discharge through the load and into Cchg (e.g, charge balancing). In the example shown, Vouts get back to stable output at t3.

With further reference toFIGS.3and4a-4c, as compared to buck converter100above, adding the additional capacitance Cchg allows for charge balancing between it and Cout/Cadd reducing in lower overshoot (e.g., peak402is lower than peak202ofFIG.2c). Further, this additional capacitance can reduce settling time bringing t3much closer to t1than in the prior circuit (e.g., less than 0.2 ms in the simulations ofFIGS.4a-4c).

Based on the above, the skilled artisan will realize that circuit300(e.g., a buck convert301in combination with the suppression circuit340) can provide one or more of advantages. These can include in some embodiments one or more of: Very fast settling time (˜8× improvement); Reduced overshoot (˜2× improvement); No continuous power dissipation due to dummy load addition; Low power dissipation and high power density for a given regulator design and Simplicity of implementation due to easy scaling to different output voltage levels. to implement.

By way of example, in the simulation ofFIGS.4a-4ccertain component values were used. These values are listed below but are not meant as limiting:Cin=20 uF;Ls=3.76 uHCout=14 uF;Cadd=170 uF;Cchg=10 uF;Rser=5 ohms; andRadd=120 ohms.

The term “about” is intended to include the degree of error associated with measurement of the particular quantity based upon the equipment available at the time of filing the application.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, element components, and/or groups thereof.

While the present disclosure has been described with reference to an exemplary embodiment or embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the present disclosure. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present disclosure without departing from the essential scope thereof. Therefore, it is intended that the present disclosure not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this present disclosure, but that the present disclosure will include all embodiments falling within the scope of the claims.