Patent ID: 12249376

DETAILED DESCRIPTION OF EMBODIMENTS

Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown.

As is traditional in the field, the embodiments are described, and illustrated in the drawings, in terms of functional blocks, units and/or modules. Those skilled in the art will appreciate that these blocks, units and/or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, and the like, which may be formed using semiconductor-based fabrication techniques or other manufacturing technologies. In the case of the blocks, units and/or modules being implemented by microprocessors or similar, they may be programmed using software (e.g., microcode) to perform various functions discussed herein and may optionally be driven by firmware and/or software. Alternatively, each block, unit and/or module may be implemented by dedicated hardware, or as a combination of dedicated hardware to perform some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) to perform other functions. Also, each block, unit and/or module of the embodiments may be physically separated into two or more interacting and discrete blocks, units and/or modules without departing from the present scope. Further, the blocks, units and/or modules of the embodiments may be physically combined into more complex blocks, units and/or modules without departing from the present scope.

FIG.1is a block diagram illustrating a storage system according to example embodiments.

Referring toFIG.1, a storage system50may include a host100and a storage device200. The host100may include a storage interface (I/F)140. The storage device200may be any kind of storage device.

The storage device200may include a storage controller300, a plurality of nonvolatile memory devices400ato400k(where k is an integer greater than two), a power management integrated circuit (PMIC)600and a host interface240. The host interface240may include a signal connector241and a power connector243. The storage device200may further include a volatile memory device250.

The plurality of nonvolatile memory devices400ato400kmay be used as a storage medium of the storage device200. In some example embodiments, each of the plurality of nonvolatile memory devices400ato400kmay include a flash memory or a vertical NAND memory device. The storage controller300may be coupled to the plurality of nonvolatile memory devices400ato400kthrough a plurality of channels CHG1to CHGk, respectively.

The storage controller300may be configured to receive a request REQ from the host100and communicate data DTA with the host100through the signal connector241. The storage controller300may write the data DTA to the plurality of nonvolatile memory devices400ato400kor read the data DTA from plurality of nonvolatile memory devices400ato400kbased on the request REQ.

The storage controller300may communicate the data DTA with the host100using the volatile memory device250as an input/output buffer. In some example embodiments, the volatile memory device250may include a dynamic random access memory (DRAM).

The PMIC600may be configured to receive a plurality of power supply voltages VES1-VESt, which may be for example external supply voltages, from the host100through the power connector243. For example, the power connector243may include a plurality of power lines P1to Pt, and the power connector243may be configured to receive the plurality of power supply voltages VES1to VESt from the host100through the plurality of power lines P to Pt, respectively, and provide the plurality of power supply voltages VES1to VESt to the PMIC600. Here, t represents a positive integer greater than one.

The PMIC600may generate at least one first operating voltage VOP1used by the storage controller, at least one second operating voltage VOP2used by the plurality of nonvolatile memory devices400ato400k, and at least one third operating voltage VOP3used by the volatile memory device250based on the plurality of power supply voltages VES1to VESt.

For example, when the PMIC600receives all of the plurality of power supply voltages VES1to VESt from the host100, the PMIC600may generate the at least one first operating voltage VOP1, the at least one second operating voltage VOP2, and the at least one third operating voltage VOP3using all of the plurality of power supply voltages VES1to VESt. In embodiments, when the PMIC600receives less than all of the plurality of power supply voltages VES1to VESt from the host100, the PMIC600may generate the at least one first operating voltage VOP1, the at least one second operating voltage VOP2, and the at least one third operating voltage VOP3using all of the part of the plurality of power supply voltages VES1to VESt that is received from the host100.

FIG.2is a block diagram illustrating the host inFIG.1according to example embodiments.

Referring toFIG.2, the host100may include a central processing unit (CPU)110, a read-only memory (ROM)120, a main memory130, a storage interface (I/F)140, a user interface (I/F)150and a bus160.

The bus160may refer to a transmission channel via which data is transmitted between the CPU110, the ROM120, the main memory130, the storage interface140and the user interface150of the host100. The ROM120may store various application programs. For example, application programs supporting storage protocols such as Advanced Technology Attachment (ATA), Small Computer System Interface (SCSI), embedded Multi Media Card (eMMC), and/or Universal flash storage (UFS) protocols are stored.

The main memory130may temporarily store data or programs. The user interface150may be a physical or virtual medium for exchanging information between a user and the host100, a computer program, etc., and includes physical hardware and logical software. For example, the user interface150may include an input device for allowing the user to manipulate the host100, and an output device for outputting a result of processing an input of the user.

The CPU110may control overall operations of the host100. The CPU110may generate a command for storing data in the storage device200or a request (or a command) for reading data from the storage device200by using an application stored in the ROM120, and transmit the request to the storage device200via the storage interface140.

FIG.3is a block diagram illustrating an example of the storage controller in the storage device inFIG.1according to example embodiments.

Referring toFIG.3, the storage controller300may include a processor310, an error correction code (ECC) engine500, an on-chip memory330, randomizer340, a host interface (I/F)350, a ROM360and a nonvolatile memory (NVM) interface (I/F)370which are connected via a bus305.

The processor310controls an overall operation of the storage controller300. The processor310may control the ECC engine500, the on-chip memory330, the randomizer340, the host interface350, the ROM360and the nonvolatile memory interface370. The processor310may include one or more cores (e.g., a homogeneous multi-core or a heterogeneous multi-core). The processor310may be or include, for example, at least one of a central processing unit (CPU), an image signal processing unit (ISP), a digital signal processing unit (DSP), a graphics processing unit (GPU), a vision processing unit (VPU), and a neural processing unit (NPU). The processor310may execute various application programs (e.g., a flash translation layer (FTL)335and firmware) loaded onto the on-chip memory330.

The on-chip memory330may store various application programs that are executable by the processor310. The on-chip memory330may operate as a cache memory adjacent to the processor310. The on-chip memory330may store a command, an address, and data to be processed by the processor310or may store a processing result of the processor310. The on-chip memory330may be, for example, a storage medium or a working memory including a latch, a register, a static random access memory (SRAM), a dynamic random access memory (DRAM), a thyristor random access memory (TRAM), a tightly coupled memory (TCM), etc.

The processor310may execute the FTL335loaded onto the on-chip memory330. The FTL335may be loaded onto the on-chip memory330as firmware or a program stored in the one of the nonvolatile memory devices400ato400k. The FTL335may manage mapping between a logical address provided from the host100and a physical address of the nonvolatile memory devices400ato400kand may include an address mapping table manager managing and updating an address mapping table. The FTL335may further perform a garbage collection operation, a wear leveling operation, and the like, as well as the address mapping described above. The FTL335may be executed by the processor310for addressing one or more of the following aspects of the nonvolatile memory devices400ato400k: overwrite- or in-place write-impossible, a life time of a memory cell, a limited number of program-erase (PE) cycles, and an erase speed slower than a write speed.

The FTL335may provide the ECC engine500with a location index LIDX that divide a plurality of memory cells included in each of a page of each of the nonvolatile memory devices400ato400kinto outer cells and inner cells, which may mean grouping the plurality of memory cells such that each memory cell of the plurality of memory cells is designated as an outer cell or an inner cell. A distance between the outer cell and a word-line cut region is smaller than a distance between the inner cell and the word-line cut region.

Memory cells of the nonvolatile memory devices400ato400kmay have a physical characteristic in which a threshold voltage distribution varies due to causes, such as a program elapsed time, a temperature, program disturbance, read disturbance and etc. For example, data stored at the nonvolatile memory devices400ato400kmay become erroneous due to the above causes.

The storage controller300may utilize a variety of error correction techniques to correct such errors. For example, the storage controller300may include the ECC engine500. The ECC engine500may correct errors which occur in the data stored in the nonvolatile memory devices400ato400k. The ECC engine500may include an ECC encoder510and an ECC decoder520. The ECC encoder510may perform an ECC encoding operation on data to be stored in the nonvolatile memory devices400ato400k. The ECC decoder520may perform an ECC decoding operation on data read from the nonvolatile memory devices400ato400k.

The storage controller300may divide a plurality of target memory cells coupled to a target word-line into outer cells and inner cells based on the location index LIDX of each of the target memory cells in a read operation on the plurality of target memory cells. A distance between the outer cell and the word-line cut region is smaller than a distance between the inner cell and the word-line cut region. The ECC decoder520may perform an ECC decoding operation on an ECC sector by applying different log likelihood ratio (LLR) values to outer cell bits and inner cell bits. For example, the ECC decoder520may perform an ECC decoding operation on an ECC sector by applying a first LLR value to one or more outer cell bits, and applying a second LLR value to one or more inner cell bits, and the first LLR value may be different from the second LLR value. The outer cell bits are read from the outer cells in an ECC sector, the inner cell bits are read from the inner cells in the ECC sector, and the ECC sector corresponds to a unit of an ECC operation.

The ROM360may store a variety of information, needed for the storage controller300to operate, in firmware.

The randomizer340may randomize data to be stored in one of the nonvolatile memory devices400ato400k. For example, the randomizer340may randomize data to be stored in one of the nonvolatile memory devices400ato400kby a word-line.

Data randomizing may include processing data such that program states of memory cells connected to a word-line have the same ratio. For example, if memory cells connected to one word-line are quad-level cells (QLC) each storing 4-bit data, each of the memory cells may have one of an erase state and first through fifteenth program states. In this case, the randomizer340may randomize data such that in memory cells connected to one word-line, the number of memory cells having the erase state, and each of the number of memory cells having the first through fifteenth program states, may be substantially the same as one another. For example, memory cells in which randomized data is stored have program states of which the number is equal to one another.

The randomizer340may randomize page data. An example of an operation of the randomizer340is described below, however embodiments are not limited thereto. For example, the randomizer340may randomize data such that in memory cells connected to one word-line, the number of memory cells having the erase state and each of the number of memory cells having the first through fifteenth program states are approximately the same value. For example, memory cells in which randomized data is stored have program states of which the number may be similar to one another.

In embodiments, when the number of memory cells having the erase state and each of the number of memory cells having the first through fifteenth program states are approximately the same value, this may mean that the number of the number of memory cells having the erase state and each of the number of memory cells having the first through fifteenth program states are within a particular threshold number of each other.

The storage controller300may communicate with the host100through the host interface350. For example, the host interface350may include Universal Serial Bus (USB), Multimedia Card (MMC), embedded-MMC, peripheral component interconnection (PCI), PCI-express, Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, small computer small interface (SCSI), enhanced small disk interface (ESDI), Integrated Drive Electronics (IDE), Mobile Industry Processor Interface (MIPI), Nonvolatile memory express (NVMe), Universal Flash Storage (UFS), and etc. The storage controller300may communicate with the nonvolatile memory devices400ato400kthrough the nonvolatile memory interface370.

FIG.4is a block diagram illustrating a connection relationship between the storage controller and one nonvolatile memory device in the storage device ofFIG.1.

Referring toFIG.4, the nonvolatile memory device400amay operate based on the first operating voltage VOP1.

The nonvolatile memory device400amay perform an erase operation, a program operation, and/or a write operation under control of the storage controller300. The nonvolatile memory device400amay receive a command CMD, an address ADDR, and data DTA, which may be for example user data such as a write data WD, through input/output lines from the storage controller300for performing such operations. In addition, the nonvolatile memory device400amay receive a control signal CTRL through a control line and receives a power PWR1through a power line from the storage controller300. In addition, the nonvolatile memory device400amay provide the storage controller300with the data DTA, for example a read data RD.

The storage controller300may include the ECC engine500, and the ECC engine500may include the ECC encoder510and the ECC decoder520. The ECC encoder510may perform an ECC encoding operation on data to be stored in the nonvolatile memory device400a. The ECC decoder520may perform an ECC decoding operation on data read from the nonvolatile memory device400a.

The storage controller300may divide a plurality of target memory cells coupled to a target word-line into outer cells and inner cells based on the location index LIDX of each of the target memory cells in a read operation on the plurality of target memory cells. A distance between the outer cell and the word-line cut region is smaller than a distance between the inner cell and the word-line cut region. The ECC decoder520may perform an ECC decoding operation on an ECC sector by applying different log likelihood ratio (LLR) values to outer cell bits and inner cell bits. The outer cell bits are read from the outer cells in an ECC sector, the inner cell bits are read from the inner cells in the ECC sector, and the ECC sector corresponds to a unit of an ECC operation.

FIG.5is a block diagram illustrating the nonvolatile memory device inFIG.4according to some example embodiments.

Referring toFIG.5, the nonvolatile memory device400amay include a memory cell array420, an address decoder450, a page buffer circuit430, a data input/output (I/O) circuit440, a control circuit460, and a voltage generator470.

The memory cell array420may be coupled to the address decoder450through a string selection line SSL, a plurality of word-lines WLs, and a ground selection line GSL. In addition, the memory cell array420may be coupled to the page buffer circuit430through a plurality of bit-lines BLs.

The memory cell array420may include a plurality of memory cells coupled to the plurality of word-lines WLs and the plurality of bit-lines BLs.

In some example embodiments, the memory cell array420may be or include a three-dimensional memory cell array, which is formed on a substrate in a three-dimensional structure (e.g., a vertical structure). In this case, the memory cell array420may include vertical cell strings that are vertically oriented such that at least one memory cell is located over another memory cell.

FIG.6is a block diagram illustrating the memory cell array in the nonvolatile memory device ofFIG.5.

Referring toFIG.6, the memory cell array420may include a plurality of memory blocks BLK1to BLKz. The memory blocks BLK1to BLKz extend along a first horizontal direction HID1, which may be for example an X-axis direction, a second horizontal direction HD2, which may be for example a Y-axis direction, and a vertical direction VD, which may be for example a Z-axis direction. In some example embodiments, the memory blocks BLK1to BLKz are selected by the address decoder450inFIG.5. For example, the address decoder450may select a memory block BLK corresponding to a block address among the memory blocks BLK1to BLKz.

FIG.7is a circuit diagram illustrating one of the memory blocks ofFIG.6.

The memory block BLKi ofFIG.7may be formed on a substrate SUB in a three-dimensional structure (or a vertical structure). For example, a plurality of memory cell strings included in the memory block BLKi may be formed in the vertical direction VD perpendicular to the substrate SUB.

Referring toFIG.7, the memory block BLKi may include memory cell strings NS11to NS33coupled between bit-lines BL1, BL2and BL3and a common source line CSL. Each of the memory cell strings NS11to NS33may include a string selection transistor SST, a plurality of memory cells MC1to MC8, and a ground selection transistor GST. InFIG.7, each of the memory cell strings NS11to NS33is illustrated to include eight memory cells MC1to MC8. However, embodiments are not limited thereto. In some example embodiments, each of the memory cell strings NS11to NS33may include any number of memory cells.

The string selection transistor SST may be connected to corresponding string selection lines SSL1to SSL3. The plurality of memory cells MC1to MC8may be connected to corresponding word-lines WL1to WL8, respectively. The ground selection transistor GST may be connected to corresponding ground selection lines GSL1to GSL3. The string selection transistor SST may be connected to corresponding bit-lines BL1, BL2and BL3, and the ground selection transistor GST may be connected to the common source line CSL.

Word-lines (e.g., word-line WL1) having the same height may be commonly connected, and the ground selection lines GSL1to GSL3and the string selection lines SSL1to SSL3may be separated. InFIG.5, the memory block BLKi is illustrated to be coupled to eight word-lines WL1to WL8and three bit-lines BL1to BL3. However, embodiments are not limited thereto. In some example embodiments, the memory cell array420may be coupled to any number of word-lines and bit-lines.

FIG.8illustrates an example of a structure of a cell string CS in the memory block ofFIG.7.

Referring toFIGS.7and8, a pillar PL is provided on the substrate SUB such that the pillar PL extends in a direction perpendicular to the substrate SUB, for example a vertical direction VD, to make contact with the substrate SUB. Each of the ground selection line GSL, the word lines WL1to WL8, and the string selection lines SSL illustrated inFIG.18may be formed of a conductive material parallel with the substrate SUB, for example, a metallic material. The pillar PL may be in contact with the substrate SUB through the conductive materials forming the string selection lines SSL, the word lines WL1to WL8, and the ground selection line GSL.

A sectional view taken along a line V-V′ is also illustrated inFIG.8. In some example embodiments, a sectional view of a first memory cell MC1corresponding to a first word line WL1is illustrated. The pillar PL may include a cylindrical body BD. An air gap AG may be defined in the interior of the body BD.

The body BD may include P-type silicon and may be an area where a channel will be formed. The pillar PL may further include a cylindrical tunnel insulating layer TI surrounding the body BD and a cylindrical charge trap layer CT surrounding the tunnel insulating layer TI. A blocking insulating layer BI may be provided between the first word line WL and the pillar PL. The body BD, the tunnel insulating layer TI, the charge trap layer CT, the blocking insulating layer BI, and the first word line WL may constitute or be included in a charge trap type transistor that is formed in a direction perpendicular to the substrate SUB or to an upper surface of the substrate SUB. A string selection transistor SST, a ground selection transistor GST, and other memory cells may have the same structure as the first memory cell MC1.

Referring back toFIG.5, the control circuit460may receive a command signal including the command CMD and an address signal including the address ADDR from the storage controller300, and may control an erase loop, a program loop and/or a read operation of the nonvolatile memory device400abased on the command CMD and the address ADDR. The program loop may include a program operation and a program verification operation. The erase loop may include an erase operation and an erase verification operation.

For example, the control circuit460may generate control signals CTLs, which are used for controlling the voltage generator470, based on at least one of the command signal and the command CMD, and generate a row address R_ADDR and a column address C_ADDR based on at least one of the address signal and the address signal ADDR. The control circuit460may provide the row address R_ADDR to the address decoder450and may provide the column address C_ADDR to the data I/O circuit440.

The address decoder450may be coupled to the memory cell array420through the string selection line SSL, the plurality of word-lines WLs, and the ground selection line GSL. During the program operation or the read operation, the address decoder450may determine one of the plurality of word-lines WLs as a first word-line (e.g., a selected word-line) and determine rest of the plurality of word-lines WLs except for the first word-line as unselected word-lines based on the row address R_ADDR.

The voltage generator470may generate word-line voltages VWLs, which are required for the operation of the nonvolatile memory device400a, based on the control signals CTLs. The voltage generator470may receive the power PWR1from the storage controller300. The word-line voltages VWLs may be applied to the plurality of word-lines WLs through the address decoder450.

For example, during the erase operation, the voltage generator470may apply an erase voltage to a well of the memory block and may apply a ground voltage to entire word-lines of the memory block. During the erase verification operation, the voltage generator470may apply an erase verification voltage to the entire word-lines of the memory block or sequentially apply the erase verification voltage to word-lines in a word-line basis.

For example, during the program operation, the voltage generator470may apply a program voltage to the first word-line and may apply a program pass voltage to the unselected word-lines. In addition, during the program verification operation, the voltage generator470may apply a program verification voltage to the first word-line and may apply a verification pass voltage to the unselected word-lines.

Furthermore, during the read operation, the voltage generator470may apply a read voltage to the first word-line and may apply a read pass voltage to the unselected word-lines.

The page buffer circuit430may be coupled to the memory cell array420through the plurality of bit-lines BLs. The page buffer circuit430may include a plurality of page buffers. In some example embodiments, one page buffer may be connected to one bit-line. In some example embodiments, one page buffer may be connected to two or more bit-lines.

The page buffer circuit430may temporarily store data to be programmed in a selected page or data read out from the selected page.

The data I/O circuit440may be coupled to the page buffer circuit430through data lines DLs. During the program operation, the data I/O circuit440may receive the data DTA for example the write data WD, from the storage controller300provide the data DTAto the page buffer circuit430based on the column address C_ADDR received from the control circuit460.

During the read operation, the data I/O circuit440may provide the data DTA for example the read data RD, which are stored in the page buffer circuit430, to the storage controller300based on the column address C_ADDR received from the control circuit460.

The control circuit460may control the page buffer circuit430and data I/O circuit440.

The control circuit460may include a status signal generator465and the status signal generator465may generate a status signal RnB indicating whether each of the program operation, the erase operation and the read operation is completed or and/or is in progress.

The storage controller300may determine idle state or busy state of each of the nonvolatile memory devices400ato400kbased on the status signal RnB.

FIG.9is a block diagram illustrating an example of the memory cell array in the nonvolatile memory device ofFIG.5according to example embodiments.

Referring toFIG.9, a memory cell array420may include a plurality of memory blocks BLK1to BLKz. Each of the plurality of memory blocks BLK1to BLKz may include a plurality of pages PAG1to PAGq (where q is an integer equal to or greater than 2).

The memory cell array420may include a normal cell region NCA to store the user data DTA and a parity cell region PCA to store parity bits.

Memory cells of the normal cell region NCA and the parity cell region PCA may be coupled to first bit-lines BL1to BLn (n is an integer equal to or greater than 4). Each of the pages in the normal cell region NCA and the parity cell region PCA may include a plurality of sectors SEC1through SECk (k is an integer equal to or greater than 3).

FIG.10is a perspective view illustrating one of the memory blocks inFIG.6. andFIGS.11A-11Care top views of examples of the memory block ofFIG.10.

Referring toFIG.10, the memory block BLKi may be implemented such that at least one ground selection line GSL, a plurality of word-lines WLs and at least one string selection line SSL are stacked on a substrate between word-line cut regions WLC. Doping regions DOP may be formed in top portions of the substrate of the word-line cut regions WLC. The doping region may be used as common source lines CSL or common source nodes CSN to which a common source voltage is applied. The at least one string selection line SSL may be divided by a string selection line cut region SSLC extending in the first horizontal direction HD1.

A plurality of vertical channels or channel holes penetrate the at least one ground selection lines GSL, the plurality of word-lines WLs and the at least one string selection lines SSL. The at least one ground selection lines GSL, the plurality of word-lines WL and the at least one string selection lines SSL may be formed in the shape of planks. Bit-lines BL are connected to top surfaces of the channel holes.

FIGS.11A through11Care top views of examples of the memory block ofFIG.10, respectively andFIG.12is a circuit diagram illustrating connection relationship of NAND strings in the memory block inFIG.11A.

InFIG.11A, dotted circles represent inner cells or inner channel holes and white circuits represent outer cells or outer channel holes. The common source lines corresponding to the doping region DOP inFIG.9are disposed in the word-line cut regions WLC.

Referring toFIG.11A, the channel holes may be formed in a zig-zag structure in the memory block BLKi. Through the zig-zag structure, the area of the memory block BLKi may be reduced. Outer channel holes and inner channel holes are disposed in the second horizontal direction HD2between the adjacent two word-line cut regions WLC in the memory block BLKi. One of the inner channel holes and the outer channel holes may be connected to even-numbered bit-line and the other may be connected to odd-numbered bit-line. For convenience of illustration, only one bit-line pair BLo and BLi are illustrated and the other bit-lines are omitted inFIG.11A.

As illustrated inFIG.11A, the outer cells may be formed in the outer channel holes and the inner cells may be formed on the inner channel holes where a distance Do between the outer channel hole and the word-line cut region WLC is smaller than a distance Di between the inner channel hole and the word-line cut region WLC.

Referring toFIG.12, an inner NAND string NSi is formed in the inner channel hole and an outer NAND string NSo is formed in the outer channel hole. One end of the inner NAND string NSi is connected to the inner bit-line BLi and the other end of the inner NAND string NSi is connected to the common source line CSL through an inner resistor Ri. One end of the outer NAND string NSo is connected to the outer bit-line BLo and the other end of the outer NAND string NSo is connected to the common source line CSL through an outer resistor Ro.

Because the distance Do between the outer channel hole and the word-line cut region WLC is smaller than a distance Di between the inner channel hole and the word-line cut region WLC as illustrated inFIG.11A, the resistance value of the inner resistor Ri is greater than the resistance value of the outer resistor Ro.

As such, the inner NAND string NSi and the outer NAND string NSo may be connected to the common source line CSL through the resistors Ri and Ro of the different resistance values. The inner cells in the inner NAND string NSi and the outer cells in the outer NAND string NSo may have different electrical characteristics due to the asymmetric connection structure of the inner NAND string NSi and the outer NAND string NSo. Such different electrical characteristics may result in the difference in the error bit levels. That is, a probability of error occurrence in the outer cells which is closer to the word-line cut region WLC than the inner cells is greater than a probability of error occurrence in the inner cells.

Referring toFIG.11B, the storage controller300ofFIG.3may divide a plurality of memory cells in a memory block into outer cells disposed within a first distance D11from the word-line cut region WLC, inner cells disposed out of the first distance D11and within a second distance D12and mid cells disposed between the inner cells based on a distance from the word-line cut region WLC.

The ECC decoder520may perform the ECC decoding operation by applying different LLR values to outer cell bits read from the outer cells, inner cell bits read from the inner cells and mid cell bits read from the mid cells. For example, the ECC decoder520may perform the ECC decoding operation by applying a first LLR value to one or more outer cell bits, applying a second LLR value to one or more inner cell bits, and applying a third LLR value to one or more mid cell bits, and the first LLR value, the second LLR value, and the third LLR value may be different from each other.

Referring toFIG.11C, the storage controller300ofFIG.3may divide a plurality of memory cells in a memory block into outer cells disposed within a first distance D21from the word-line cut region WLC and inner cells disposed out of the first distance D21and within a second distance D22based on a distance from the word-line cut region WLC. The storage controller300may further divide each of the outer cells and the inner cells into at least two groups based on the distance from the word-line cut region WLC. The ECC decoder520may perform the ECC decoding operation by applying different LLR values to bits read from groups of the outer cells and bits read from groups of the inner cells.

FIG.13Ais a graph showing a threshold voltage distribution of memory cells when a memory cell included in the memory cell array inFIG.5is a 4-bit quadrature level cell (QLC).

Referring toFIG.13A, a horizontal axis represents a threshold voltage Vth and the vertical axis represents the number of memory cells. When each of the memory cells is a 4-bit quadrature level cell programmed to store 4 bits, the memory cell may have one from among an erase state E and first through fifteenth program states P1through P15. When a memory cell is a multi-level cell, unlike a single-level cell, because an interval between threshold voltages distributions is small, a small change in the threshold voltage Vth may cause a large problem.

A first read voltage Vr1has a voltage level between a distribution of a memory cell having the erase state E and a distribution of a memory cell having the first program state P1. Each of second through fifteenth read voltages Vr2through Vr15have a voltage level between distributions of memory cells having adjacent program states.

In example embodiments, assuming that the first read voltage Vr1is applied, when a memory cell is turned on, data ‘1’ may be stored, and when the memory cell is turned off, data ‘0’ may be stored. However, embodiments are not limited thereto. For example, in embodiments, assuming that the first read voltage Vr1is applied, when a memory cell is turned on, data ‘0’ may be stored, and when the memory cell is turned off, data ‘1’ may be stored. As such, a logic level of data may vary according to embodiments.

FIG.13BandFIG.13Care graphs showing examples in which a threshold voltage of memory cells in the graph ofFIG.13Ais changed, respectively.

FIG.13Bshows that a threshold voltage of inner cells is changed andFIG.13Cshows that a threshold voltage of outer cells is changed.

Referring toFIGS.13B and13C, memory cells respectively programmed to the erase state E and the first through fifteenth program states P1through P15may have a changed distribution as shown inFIGS.13B and13Caccording to a read environment. InFIGS.13Band13C, memory cells belonging to hatched portions may have read errors, thereby reducing the reliability of a nonvolatile memory device. A number of read errors inFIG.13Cmay be larger than a number of read errors inFIG.13B.

For example, when a read operation is performed on a memory device by using the first read voltage Vr1, although memory cells included in a hatched portion are programmed to the first program state P1, the memory cells may be determined to have the erase state E due to a decrease in the threshold voltage Vth. Accordingly, an error may occur in the read operation, thereby reducing the reliability of the nonvolatile memory device.

When data is read from the nonvolatile memory device400a, a raw bit error rate (RBER) may vary according to a voltage level of a read voltage. An optimum or otherwise desirable voltage level of a read voltage may be determined according to a distribution pattern of the memory cells. Accordingly, as a distribution of the memory cells changes, an optimum or otherwise desirable voltage level of a read voltage needed to read data from the nonvolatile memory device may change.

FIG.13Dillustrates a table for explaining bit mapping for programming memory cells according to example embodiments.

For convenience of explanation, the present embodiment relates to a QLC memory cell. However, in other embodiments the memory cell may be a different type other than a QLC type.

Referring toFIG.13D, when memory cells are QLCs, each of the memory cells may store a least significant bit (LSB), an extra significant bit (ESB), an upper significant bit (USB), and a most significant bit (MSB). Further referring toFIG.8, LSBs stored in memory cells in a first row from among the memory cells connected to the word-line WL1may form a first page, and MSBs stored therein may form a fourth page. USBs stored in the memory cells in the first row from among the memory cells connected to the word-line WL1may form a third page, and ESB stored therein may form a second page.

FIG.14shows an example of a Tanner graph for explaining an ECC decoding operation according to example embodiments.

In embodiments, the ECC decoder520according toFIG.4andFIG.14may perform an ECC decoding operation based on a low-density parity check (LDPC) code, however embodiments are not limited thereto.

An LDPC code has an error correction capability near a channel capacity and is widely used in communication systems, communication standards, memory controllers, etc. The LDPC code is a linear block code that may be defined as a parity check matrix (PCM). Here, a code may refer to a relation between information and parity.

The LDPC code having a codeword length of n and an information length of k may be represented by the PCM having a size of (n-k)*n. In general, the LDPC code has a higher correction capability as the codeword length is long. The codeword may correspond to an ECC sector.

Referring toFIG.14, the Tanner graph includes variable nodes a, b, c, d, e and f, check nodes A, B, C and D and edges connecting the variable nodes a, b, c, d, e and f and the check nodes A, B, C and D. The variable nodes a, b, c, d, e and f are related with codeword bits and the check nodes A, B, C and D are related with parity check constraints. The component “1” of the PCM corresponds to an edge of the Tanner graph. The number of the edges connected to each node is defined as a degree of the node.

The ECC decoder520may apply first LLR values LLRV1to the variable nodes a and d and may apply second LLR values LLRV2to the variable nodes b, c, e and f.

FIG.15is a block diagram illustrating an example of an ECC decoder according to example embodiments.

The nonvolatile memory device400amay perform a read operation including a hard decision read operation and/or a soft decision read operation. The hard decision read operation is a read operation to read hard decision data from memory cells coupled to the target word-line based on on/off states of the memory cells by applying a default read voltage to the target word-line, the ECC decoder520may perform hard decision-type of error correction using the hard decision data and an ECC such as LDPC code. In addition, the soft decision read operation is a read operation to read soft decision data having reliability information on the hard decision data from memory cells coupled to the target word-line by applying a plurality of offset read voltages having regular gaps to the target word-line, the ECC decoder520may perform soft decision-type of error correction using the hard decision data, an ECC such as LDPC code and the reliability information on the hard decision data.

Referring toFIG.15, the ECC decoder520may include a read data manager525, an LLR mapper530, an LLR register540and a decoder550.

The read data manager525may receive and store read data RD read from a target page coupled to the target word-line and may provide the read data RD to the LLR mapper530by unit of an ECC sector. The read data manager525may provide the LLR mapper530with the location index LIDX of each of data bits in the read data RD.

The read data manager525may receive data read using a default read voltage from the target word-line and may store the received data as a first read data RD1. The read data manager525may receive data read using offset read voltages different from the default read voltage from the target word-line and may store the received data as a second read data RD2. The read data manager525may provide the first read data RD1and the second read data RD2to the LLR mapper530and may provide the location index LIDX along with the second read data RD2to the LLR mapper530.

The LLR register540may store a plurality sets of LLR values including a first set of LLR values LLRST1, a second set of LLR values LLRST2and a third set of LLR values LLRST3, and may provide the plurality sets of LLR values to the LLR mapper530.

In a soft decision decoding on the second read data RD2, the LLR mapper530may map the first set of LLR values LLRST1and the second set of LLR values LLRST2to the read data provided from the read data manager525by unit of an ECC sector to output an LLR data LLRD. The LLR mapper530may map the first set of LLR values LLRST1to outer cell bits of the second read data RD2and may map the second set of LLR values LLRST2to inner cell bits of the second read data RD2.

In example embodiments, the LLR mapper530may map the third set of LLR values LLRST3to mid cell bits of the second read data RD2.

The decoder550may update values of variable nodes and values of check nodes by performing node operation based on the LLR data LLRD and may output a decoded data CD or an error message ERR by performing a decoding on the LLR data LLRD based on the updated values of the variable nodes. The decoder550may output the decoded data CD in response to errors in the read data RD being corrected and the decoder550may output the error message ERR in response to at least one of errors in the read data RD being not corrected.

The decoder550may include a variable node processor VNP551, a first switch network SWN1553, a check node processor CNP555, a second switch network SWN25574, and a decision logic560, which may be for example a decision logic circuit.

During the LDPC decoding, a nonzero element in the parity check matrix means that a corresponding variable node and a corresponding check node are connected to each other. The decoding is performed through data transmitted according to the connection of the variable node and the check node.

The variable node processor VNP551may include the variable nodes a, b, c, d, e and f inFIG.14, may store the LLR data LLRD and may provide the stored LLR data LLRD, as a variable node message VNM, to the first switch network553. The check node processor CNP555may be connected to the variable node processor VNP551through the first switch network553, may include the check nodes A, B, C and D inFIG.14, may process values of the variable nodes with respect to each check node with reference to the variable node message VNM, and may provide a check node message CNM to the second switch network557.

The variable node processor VNP551may be connected to the check node processor CNP555through the second switch network557, may update values of the variable nodes with reference to the check node message CNM and may perform decoding on the LLR data LLRD according to the updated values of the variable nodes.

The decision logic560may correct the second read data RD based on a result of decoding to output the decoded data CD or the error message ERR in response to uncorrectable errors.

FIG.16illustrates an example of the read data inFIG.15.

Referring toFIG.16, the read data RD may include a first ECC sector ECCS1, a second ECC sector ECCS2, a third ECC sector ECCS3and a fourth ECC sector ECCS4.

As described above, each of the first ECC sector ECCS1, the second ECC sector ECCS2, the third ECC sector ECCS3and the fourth ECC sector ECCS4may correspond to a unit of ECC operation.

FIG.17illustrates an example of data bits in the first ECC sector inFIG.16.

Referring toFIG.17, the first ECC sector ECCS1may include outer cell bits OCD, which may be for example first data bits, and inner cell bits ICD, which may be for example second data bits. The outer cell bits are read from the outer cells and the inner cell bits are read from the inner cells and a distance between the outer cells and the word-line cut region is smaller than a distance between the inner cells and the word-line cut region.

The ECC decoder520may apply the first set of LLR values LLRST1to the outer cell bits OCD and may apply the second set of LLR values LLRST2to the inner cell bits ICD.

FIG.18illustrates an example in which the ECC decoder520performs an ECC decoding operation on data bits read from the inner cells, andFIG.19illustrates an example in which the ECC decoder520performs an ECC decoding operation on data bits read from the outer cells. In.FIGS.18and19, the ECC decoder520performs a hard decision decoding HD and first and second soft decision decodings SD1and SD2for discriminating two adjacent states Si and Si+1 which are partially overlapped.

Referring toFIG.18, the ECC decoder520may perform a hard decision decoding HD on the inner cell bits read from the inner cells using a default read voltage VH, and may perform a first soft decision decoding SD1and a second soft decision decoding SD2on the inner cell bits read from the inner cells using offset read voltages VS11, VS12, VS21and VS22. A reliability of each of the inner cell bits on which the hard decision decoding HD is performed corresponds to ‘−6, −2, −1, 1, 2 and 6’ which are determined by the second set of LLR values LLRST2.

Referring toFIG.19, the ECC decoder520may perform a hard decision decoding HD on the outer cell bits read from the outer cells using the default read voltage VH, and may perform a first soft decision decoding SD1and a second soft decision decoding SD2on the inner cell bits read from the inner cells using offset read voltages VS11, VS12, VS21, VS22, VS23and VS24. A reliability of each of the outer cell bits on which the hard decision decoding HD is performed corresponds to ‘−6, −2, −1, −0.5, 0.5, 1, 2 and 6’ which are determined by the first set of LLR values LLRST1.

The ECC decoder520may apply different LLR values to the outer cell bits and the inner cell bits and may apply different LLR intervals to the outer cell bits and the inner cell bits. In addition, the processor310may control the ECC decoder520such that the ECC decoder520applies to a first LLR value to the outer cell bits and applies a second LLR value to the inner cell bits during the same LLR interval from among the different LLR intervals. An absolute value of the first LLR value is smaller than an absolute value of the second LLR value. That is, the processor310may control the ECC decoder520such that a reliability of the outer cell bits read from the outer cells having a higher probability of error occurrence is smaller than a reliability of the inner cell bits read from the inner cells having a lower probability of error occurrence.

FIG.20is a graph showing enlarged first and second program states ofFIG.13A.

Referring toFIG.20, a read window RDW between the first and second program states P1and P2may be defined as a difference between a fall voltage VF corresponding to the first program state P1and a rise voltage VR corresponding to the second program state P2. Here, the fall voltage VF may represent a threshold voltage where the number of “off” cells corresponds to a reference number REF, based on an “off” cell count result for memory cells programmed to the first program state P1. The rise voltage VR may represent a threshold voltage where the number of “off” cells corresponds to the reference number REF, based on an “off” cell count result for memory cells programmed to the second program state P2. A read voltage Vr2for determining the second program state P2should have a voltage level within the read window RWD, and in order to decrease a read error, the read window RWD should be sufficiently widely secured.

FIG.21illustrates a cell region in which the memory cell array ofFIG.6is formed according to example embodiments.

Referring toFIG.21, a cell region CR includes a plurality of channel holes CH.

A channel hole size, for example, a channel hole diameter, may be varied according to positions within the cell region CR. For example, channel holes CH adjacent to the first and second edges EDG1and EDG2have a low peripheral density, and thus may have a different diameter from those of other channel holes CH. A memory block BLKa may be adjacent to the second edge EDG2, and may be spaced apart from the second edge EDG2by a first distance d1. A memory block BLKb may not be adjacent to the first and second edges EDG1and EDG2, and be in a center of the cell region CR, and may be spaced apart from the second edge EDG2by a second distance d2. The second distance d2may be greater than the first distance d1. A first diameter D1of a first channel hole CHa included in the memory block BLKa may be smaller than a second diameter D2of a second channel hole CHb included in the memory block BLKb.

FIGS.22A and22Billustrate cross-sections of strings of the memory blocks BLKa and BLKb ofFIG.21, respectively.

Referring toFIG.22A, a pillar including a channel layer314and an internal layer315may be formed in the first channel hole CHa included in the memory block BLKa, and a charge storage layer CS may be formed around the first channel hole CHa, and the charge storage layer CS may have an (oxide-nitride-oxide) ONO structure.

Referring toFIG.22B, a pillar including a channel layer314and an internal layer315may be formed in the second channel hole CHb included in the memory block BLKb, and a charge storage layer CS may be formed around the second channel hole CHb, and the charge storage layer CS may have an ONO structure.

In an example embodiment, a thickness of the charge storage layer CS included in the memory block BLKb may be different from a thickness of the charge storage layer CS included in the memory block BLKa. Characteristics of memory cells may vary due to the difference in the channel hole diameters. For example, in a NAND flash nonvolatile memory device having a gate all around structure in which a gate electrode is disposed around a circumference of a channel hole, if a channel hole diameter is reduced, the magnitude of an electric field formed between a gate electrode and a channel layer314is increased. Thus, program and erase speeds of a memory cell having a relatively small channel hole diameter like the first channel hole CHa may be higher than those of a memory cell having a relatively large channel hole diameter like the second channel hole CHb.

Referring back toFIG.21, a memory block is formed in the cell region CR to include all memory cells corresponding to one page in the first horizontal direction HD1, that is, in a word-line direction, and to include some strings in the second horizontal direction HD2, that is, in a bit-line direction. Thus, each memory block extends in the first horizontal direction HD1, and channel hole sizes, that is, channel hole diameters may differ in units of memory blocks. Thus, program and erase speeds of memory cells included in the memory block BLKa may be higher than program and erase speeds of memory cells included in the memory block BLKb.

FIG.23illustrates an example of a vertical structure of one of channel holes inFIG.21.

Referring toFIG.23, a channel hole CH1corresponding to a string included in a nonvolatile memory device is illustrated. As described above, the channel hole CH1is formed by etching portions of gate electrodes and insulation layers stacked on a substrate, and thus, the channel hole CH1may be a tapered etching profile where a diameter of the channel hole CH1is becoming downwardly smaller. Thus, a diameter of the channel hole CH1may be smaller towards the substrate.

In an example embodiment, the channel hole CH1may be divided into three zones according to channel hole diameters. For example, a zone in which a channel hole diameter is smaller than a first value may be referred to as a first zone Z1, and a zone in which a channel hole diameter is equal to or greater than the first value and smaller than a second value may be referred to as a second zone Z2, and a zone in which a channel hole diameter is equal to or greater than the second value and smaller than a third value may be referred to as a third zone Z3. Therefore, characteristics of memory cells included in one channel hole may be different according to positions along the vertical direction VD.

A word-line WLb is provided in the first zone Z1, a word-line WLa is provided in the second zone Z2, and a word-line WLc is provided in the third zone Z3. Because the word-line WLb is adjacent to a lower edge of the channel hole CH1, the word-line WLb is adjacent to a ground selection line or the substrate, a probability of bridge occurring between the word-line WLb and the channel. When the bridge occurs between the word-line WLb and the channel, a current leakage may occur through the bridge and program/read operation and erase operation may operate abnormally in the word-line WLb due to the bridge.

Because the word-line WLc is adjacent to an upper edge of the channel hole CH1, the word-line WLc is adjacent to a string selection line or the substrate, a probability of bridge occurring between the word-line WLc and the channel.

Error occurrence probability of pages coupled to the word-line WLc which is adjacent to an upper edge of the channel hole CH1or coupled to the word-line WLb which is adjacent to the lower edge of the channel hole CH1may be greater than error occurrence probability of pages coupled to the word-line WLa which is disposed at a center region of the channel hole CH1.

FIGS.20through23relate to embodiments in which an error attribute of the target page may be different based on a location of the target word-line and an error occurrence probability of the target page may be different based on the error attribute.

The processor310in the storage controller300according to example embodiments, may apply different location indices to the plurality of NAND strings, respectively. In addition, the processor310may apply the same location index to at least two NAND strings sharing a same channel hole from among the plurality of channel holes, from among the plurality of NAND strings. In addition, the processor310may apply individual location indices to the plurality of memory blocks, respectively. In addition, the processor310may apply the location index to at least one word-line or a portion of word-lines including the inner cells and outer cells having difference of error occurrence probability.

FIG.24is a flow chart illustrating a method of operating a storage device according to example embodiments.

Referring toFIGS.3through24, there is provided a method of operating a storage device200including a nonvolatile memory device400awhich includes a memory cell array and a storage controller300to control the nonvolatile memory device400a, where the memory cell array includes a plurality of word-lines stacked on a substrate, a plurality of memory cells provided in a plurality of channel holes extending in a vertical direction with respect to the substrate and a word-line cut region extending in a first horizontal direction and dividing the plurality of word-lines into a plurality of memory blocks.

According to the method, at operation S110the storage controller300divides a plurality of target memory cells coupled to a target word-line into outer cells and inner cells based on a location index of each of the target memory cells in which a distance between the outer cell and the word-line cut region is smaller than a distance between the inner cell and the word-line cut region, in a read operation on the plurality of target memory cells (operation S110).

At operation S130, an ECC decoder520in the storage controller300applies different LLR values to outer cell bits and inner cell bits in which the outer cell bits are read from the outer cells in an ECC sector, the inner cell bits are read from the inner cells in the ECC sector and the ECC sector corresponds to a unit of an ECC operation.

At operation S150, the ECC decoder520performs an ECC decoding operation on an ECC sector based on the different LLR values.

In example embodiments, for applying the different LLR values, an LLR mapper530in the ECC decoder520applies a first set of LLR values LLRST1to the outer cell bits and applies a second set of LLR values LLRST2to the inner cell bits.

Therefore, in the storage device and the method of operating the storage device, the storage controller divides a plurality of target memory cells coupled to a target word-line into outer cells and inner cells based on a location index of each of the target memory cells, and the ECC decoder performs a soft decision decoding by applying different LLR values to outer cell bits read from the outer cells and inner cell bits read from the inner cells, during a read operation on the target page. The processor controls the ECC decoder such that a reliability of the outer cell bits read from the outer cells having a higher probability of error occurrence is smaller than a reliability of the inner cell bits read from the inner cells and thus may correct errors occurring in the outer cell bits efficiently.

FIG.25is a cross-sectional view of a nonvolatile memory device according to example embodiments.

Referring toFIG.25, a nonvolatile memory device2000, which may be referred to as a memory device, may have a chip-to-chip (C2C) structure. The C2C structure may refer to a structure formed by manufacturing an upper chip including a memory cell region or a cell region CELL on a first wafer, manufacturing a lower chip including a peripheral circuit region PERI on a second wafer, separate from the first wafer, and then bonding the upper chip and the lower chip to each other. Here, the bonding process may include a method of electrically connecting a bonding metal formed on an uppermost metal layer of the upper chip and a bonding metal formed on an uppermost metal layer of the lower chip. For example, when the bonding metals may include copper (Cu) using a Cu-to-Cu bonding. The example embodiment, however, may not be limited thereto. For example, the bonding metals may also be formed of aluminum (Al) or tungsten (W).

Each of the peripheral circuit region PERI and the cell region CELL of the memory device2000may include an external pad bonding area PA, a word-line bonding area WLBA, and a bit-line bonding area BLBA.

The peripheral circuit region PERI may include a first substrate2210, an interlayer insulating layer2215, a plurality of circuit elements2220a,2220b, and2220cformed on the first substrate2210, first metal layers2230a,2230b, and2230crespectively connected to the plurality of circuit elements2220a,2220b, and2220c, and second metal layers2240a,2240b, and2240cformed on the first metal layers2230a,2230b, and2230c. In an example embodiment, the first metal layers2230a,2230b, and2230cmay be formed of tungsten having relatively high electrical resistivity, and the second metal layers2240a,2240b, and2240cmay be formed of copper having relatively low electrical resistivity.

In an example embodiment illustrated inFIG.23, although only the first metal layers2230a,2230b, and2230cand the second metal layers2240a,2240b, and2240care shown and described, the example embodiment is not limited thereto, and one or more additional metal layers may be further formed on the second metal layers2240a,2240b, and2240c. At least a portion of the one or more additional metal layers formed on the second metal layers2240a,2240b, and2240cmay be formed of aluminum or the like having a lower electrical resistivity than those of copper forming the second metal layers2240a,2240b, and2240c.

The interlayer insulating layer2215may be disposed on the first substrate2210and cover the plurality of circuit elements2220a,2220b, and2220c, the first metal layers2230a,2230b, and2230c, and the second metal layers2240a,2240b, and2240c. The interlayer insulating layer2215may include an insulating material such as silicon oxide, silicon nitride, or the like.

Lower bonding metals2271band2272bmay be formed on the second metal layer2240bin the word-line bonding area WLBA. In the word-line bonding area WLBA, the lower bonding metals2271band2272bin the peripheral circuit region PERI may be electrically bonded to upper bonding metals2371band2372bof the cell region CELL. The lower bonding metals2271band2272band the upper bonding metals2371band2372bmay be formed of aluminum, copper, tungsten, or the like. Further, the upper bonding metals2371band2372bin the cell region CELL may be referred as first metal pads and the lower bonding metals2271band2272bin the peripheral circuit region PERI may be referred as second metal pads.

The cell region CELL may include at least one memory block. The least one memory block may include a first region and a second region. The first region may store compensation data set and may correspond to SLC block. The cell region CELL may include a second substrate2310and a common source line2320. On the second substrate2310, a plurality of word-lines2330, which may include word-line2331, word-line2332, word-line2333, word-line2334, word-line2335, word-line2336, word-line2337, and word-line2338may be stacked in a vertical direction VD (e.g., a Z-axis direction), perpendicular to an upper surface of the second substrate2310. At least one string selection line and at least one ground selection line may be arranged on and below the plurality of word-lines2330, respectively, and the plurality of word-lines2330may be disposed between the at least one string selection line and the at least one ground selection line.

In the bit-line bonding area BLBA, a channel structure CH may extend in the vertical direction VD, perpendicular to the upper surface of the second substrate2310, and pass through the plurality of word-lines2330, the at least one string selection line, and the at least one ground selection line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, and the like, and the channel layer may be electrically connected to a first metal layer and a second metal layer. For example, the first metal layer may be a bit-line contact2350c, and the second metal layer may be a bit-line2360c. In an example embodiment, the bit-line2360cmay extend in a second horizontal direction HD2(e.g., a Y-axis direction), parallel to the upper surface of the second substrate2310.

In an example embodiment illustrated inFIG.23, an area in which the channel structure CH, the bit-line2360c, and the like are disposed may be defined as the bit-line bonding area BLBA. In the bit-line bonding area BLBA, the bit-line2360cmay be electrically connected to the circuit elements2220cproviding a page buffer circuit2393in the peripheral circuit region PERI. The bit-line2360cmay be connected to upper bonding metals2371cand2372cin the cell region CELL, and the upper bonding metals2371cand2372cmay be connected to lower bonding metals2271cand2272cconnected to the circuit elements2220cof the page buffer circuit2393.

In the word-line bonding area WLBA, the plurality of word-lines2330may extend in a first horizontal direction HD1(e.g., an X-axis direction), parallel to the upper surface of the second substrate2310and perpendicular to the second horizontal direction HD2, and may be connected to a plurality of cell contact plugs2340, which may include cell contact plug2341, cell contact plug2342, cell contact plug2343, cell contact plug2344, cell contact plug2345, cell contact plug2346, and cell contact plug2347. The plurality of word-lines2330and the plurality of cell contact plugs2340may be connected to each other in pads provided by at least a portion of the plurality of word-lines2330extending in different lengths in the first horizontal direction HD1. A first metal layer2350band a second metal layer2360bmay be connected to an upper portion of the plurality of cell contact plugs2340connected to the plurality of word-lines2330, sequentially. The plurality of cell contact plugs2340may be connected to the peripheral circuit region PERI by the upper bonding metals2371band2372bof the cell region CELL and the lower bonding metals2271band2272bof the peripheral circuit region PERI in the word-line bonding area WLBA.

The plurality of cell contact plugs2340may be electrically connected to the circuit elements2220bforming an address decoder2394in the peripheral circuit region PERI. In an example embodiment, operating voltages of the circuit elements2220bforming the address decoder2394may be different than operating voltages of the circuit elements2220cforming the page buffer circuit2393. For example, operating voltages of the circuit elements2220cforming the page buffer circuit2393may be greater than operating voltages of the circuit elements2220bforming the address decoder2394.

A common source line contact plug2380may be disposed in the external pad bonding area PA. The common source line contact plug2380may be formed of a conductive material such as a metal, a metal compound, polysilicon, or the like, and may be electrically connected to the common source line2320. A first metal layer2350aand a second metal layer2360amay be stacked on an upper portion of the common source line contact plug2380, sequentially. For example, an area in which the common source line contact plug2380, the first metal layer2350a, and the second metal layer2360aare disposed may be defined as the external pad bonding area PA.

Input/output pads2205and2305may be disposed in the external pad bonding area PA. A lower insulating film2201covering a lower surface of the first substrate2210may be formed below the first substrate2210, and a first input/output pad2205may be formed on the lower insulating film2201. The first input/output pad2205may be connected to at least one of the plurality of circuit elements2220a,2220b, and2220cdisposed in the peripheral circuit region PERI through a first input/output contact plug2203, and may be separated from the first substrate2210by the lower insulating film2201. In addition, a side insulating film may be disposed between the first input/output contact plug2203and the first substrate2210to electrically separate the first input/output contact plug2203and the first substrate2210.

An upper insulating film2301covering the upper surface of the second substrate2310may be formed on the second substrate2310and a second input/output pad2305may be disposed on the upper insulating film2301. The second input/output pad2305may be connected to at least one of the plurality of circuit elements2220a,2220b, and2220cdisposed in the peripheral circuit region PERI through a second input/output contact plug2303. In the example embodiment, the second input/output pad2305is electrically connected to a circuit element2220a.

According to embodiments, the second substrate2310and the common source line2320may not be disposed in an area in which the second input/output contact plug2303is disposed. Also, the second input/output pad2305may not overlap the word-lines2330in the vertical direction HD. The second input/output contact plug2303may be separated from the second substrate2310in the direction, parallel to the upper surface of the second substrate2310, and may pass through the interlayer insulating layer2315of the cell region CELL to be connected to the second input/output pad2305.

According to embodiments, the first input/output pad2205and the second input/output pad2305may be selectively formed. For example, the memory device2000may include only the first input/output pad2205disposed on the first substrate2210or the second input/output pad2305disposed on the second substrate2310. In embodiments, the storage device200may include both the first input/output pad2205and the second input/output pad2305.

A metal pattern provided on an uppermost metal layer may be provided as a dummy pattern or the uppermost metal layer may be absent, in each of the external pad bonding area PA and the bit-line bonding area BLBA, respectively included in the cell region CELL and the peripheral circuit region PERI.

In the external pad bonding area PA, the memory device2000may include a lower metal pattern2273a, corresponding to an upper metal pattern2372aformed in an uppermost metal layer of the cell region CELL, and having the same cross-sectional shape as the upper metal pattern2372aof the cell region CELL so as to be connected to each other, in an uppermost metal layer of the peripheral circuit region PERI. In the external pad bonding area PA, the memory device2000may include lower bonding metals2271aand2271bconnected to the lower metal pattern2273a. In the peripheral circuit region PERI, the lower metal pattern2273aformed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a contact. Similarly, in the external pad bonding area PA, an upper metal pattern2372a, corresponding to the lower metal pattern2273aformed in an uppermost metal layer of the peripheral circuit region PERI, and having the same shape as a lower metal pattern2273aof the peripheral circuit region PERI, may be formed in an uppermost metal layer of the cell region CELL. Similarly, in the external pad bonding area PA, an upper bonding metal2371amay be formed and may be electrically connected to the upper metal pattern2372a.

The lower bonding metals2271band2272bmay be formed on the second metal layer2240bin the word-line bonding area WLBA. In the word-line bonding area WLBA, the lower bonding metals2271band2272bof the peripheral circuit region PERI may be electrically connected to the upper bonding metals2371band2372bof the cell region CELL by a Cu-to-Cu bonding.

Further, in the bit-line bonding area BLBA, an upper metal pattern2392, corresponding to a lower metal pattern2252formed in the uppermost metal layer of the peripheral circuit region PERI, and having the same cross-sectional shape as the lower metal pattern2252of the peripheral circuit region PERI, may be formed in an uppermost metal layer of the cell region CELL. A contact may not be formed on the upper metal pattern2392formed in the uppermost metal layer of the cell region CELL.

In an example embodiment, corresponding to a metal pattern formed in an uppermost metal layer in one of the cell region CELL and the peripheral circuit region PERI, a reinforcement metal pattern having the same cross-sectional shape as the metal pattern may be formed in an uppermost metal layer in the other one of the cell region CELL and the peripheral circuit region PERI. A contact may not be formed on the reinforcement metal pattern.

The word-line voltages may be applied to at least one memory block in the cell region CELL through the lower bonding metals2271band2272bin the peripheral circuit region PERI and upper bonding metals2371band2372bof the cell region CELL.

FIG.26is a block diagram illustrating an electronic system including a semiconductor device according to example embodiments.

Referring toFIG.26, an electronic system3000may include a semiconductor device3100and a controller3200electrically connected to the semiconductor device3100. The electronic system3000may be a storage device including one or a plurality of semiconductor devices3100or an electronic device including a storage device. For example, the electronic system3000may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device that may include one or a plurality of semiconductor devices3100.

The semiconductor device3100may be a nonvolatile memory device, for example, a nonvolatile memory device that will be illustrated with reference toFIGS.5through13D. The semiconductor device3100may include a first structure3100F and a second structure3100S on the first structure3100F. The first structure3100F may be a peripheral circuit structure including a decoder circuit3110, a page buffer circuit3120, and a logic circuit3130. The second structure3100S may be a memory cell structure including a bit-line BL, a common source line CSL, word-lines WL, first and second upper gate lines UL1and UL2, first and second lower gate lines LL1and LL2, and memory cell strings CSTR between the bit line BL and the common source line CSL.

In the second structure3100S, each of the memory cell strings CSTR may include lower transistors LT1and LT2adjacent to the common source line CSL, upper transistors UT1and UT2adjacent to the bit-line BL, and a plurality of memory cell transistors MCT between the lower transistors LT1and LT2and the upper transistors UT1and UT2. The number of the lower transistors LT1and LT2and the number of the upper transistors UT1and UT2may be varied in accordance with example embodiments.

In example embodiments, the upper transistors UT1and UT2may include string selection transistors, and the lower transistors LT1and LT2may include ground selection transistors. The lower gate lines LL1and LL2may be gate electrodes of the lower transistors LT1and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, respectively, and the upper gate lines UL1and UL2may be gate electrodes of the upper transistors UT1and UT2, respectively.

In example embodiments, the lower transistors LT1and LT2may include a lower erase control transistor LT1and a ground selection transistor LT2that may be connected with each other in serial. The upper transistors UT1and UT2may include a string selection transistor UT1and an upper erase control transistor UT2. At least one of the lower erase control transistor LT1and the upper erase control transistor UT2may be used in an erase operation for erasing data stored in the memory cell transistors MCT through gate induced drain leakage (GIDL) phenomenon.

The common source line CSL, the first and second lower gate lines LL1and LL2, the word lines WL, and the first and second upper gate lines UL1and UL2may be electrically connected to the decoder circuit3110through first connection wirings1115extending to the second structure3110S in the first structure3100F. The bit-lines BL may be electrically connected to the page buffer circuit3120through second connection wirings3125extending to the second structure3100S in the first structure3100F.

In the first structure3100F, the decoder circuit3110and the page buffer circuit3120may perform a control operation for at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit3110and the page buffer circuit3120may be controlled by the logic circuit3130. The semiconductor device3100may communicate with the controller3200through an input/output pad3101electrically connected to the logic circuit3130. The input/output pad3101may be electrically connected to the logic circuit3130through an input/output connection wiring3135extending to the second structure3100S in the first structure3100F.

The controller3200may include a processor3210, a NAND controller3220, and a host interface3230. The electronic system3000may include a plurality of semiconductor devices3100, and in this case, the controller3200may control the plurality of semiconductor devices3100.

The processor3210may control operations of the electronic system3000including the controller3200. The processor3210may be operated by firmware, and may control the NAND controller3220to access the semiconductor device3100. The NAND controller3220may include a NAND interface3221for communicating with the semiconductor device3100. Through the NAND interface3221, control command for controlling the semiconductor device3100, data to be written in the memory cell transistors MCT of the semiconductor device3100, data to be read from the memory cell transistors MCT of the semiconductor device3100, etc., may be transferred. The host interface3230may provide communication between the electronic system3000and an outside host. When control command is received from the outside host through the host interface3230, the processor3210may control the semiconductor device3100in response to the control command.

A nonvolatile memory device or a storage device according to example embodiments may be packaged using various package types or package configurations.

The present disclosures may be applied to various electronic devices including a nonvolatile memory device. For example, the present disclosures may be applied to systems such as be a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a camcorder, personal computer (PC), a server computer, a workstation, a laptop computer, a digital TV, a set-top box, a portable game console, a navigation system, etc.

The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the disclosure. Accordingly, all such modifications are intended to be included within the scope of the disclosure as defined in the claims.