Patent ID: 12216553

DETAILED DESCRIPTION

With reference to those figures, a memory architecture comprising an array of memory cells, in particular a Flash memory array provided with a selecting circuit implementing interconnection redundancy will be disclosed herein.

The example embodiment ofFIG.1Ais a memory architecture100comprising a Flash memory subarray110, the memory architecture comprising a plurality of subarrays all having a same structure.

More particularly, the Flash memory subarray110is connected to a sense amplifier120, in turn connected to a boundary or Jtag cell130, able to manage input and output serial data, SIN and SOUT, as well as input and output parallel data, PIN and POUT, respectively.

The output parallel data POUT are provided to a SoC (not shown) comprising the memory architecture100. The memory architecture100is connected to the SoC using any packaging techniques.

A low signal count interface140, with capability to modify the internal content of the Flash memory subarray110, in particular using functional pins and corresponding signals TDI, TDO, tms, tck, trst according to the Jtag protocol, could be also included in the memory architecture100, between the sense amplifiers120and the SoC, connected to the Jtag cells130whose parallel outputs POUT form interconnection channels150with the SoC, as shown inFIG.1B.

As will be explained in the following description, the memory architecture100implements an interconnection redundancy able to correct defects tied to the interconnections between the memory architecture100and the Soc comprising it. Redundancy is replicated for each subarray of the memory architecture, the subarray outputs being the interconnection channels150with a SoC, not shown in the figures.

In particular, interconnection defects are tied to defective pads or defective connection between pads and the memory architecture100according to the embodiments of the present disclosure provides redundancy for all possible defective or defectively connected pads.

According to the subdivision of a memory architecture into a plurality of subarrays, 168 pads per channel is the current targeted implementation for a Flash memory architecture to be embedded in a SoC. Suitably, the present disclosure relates to a memory architecture100managing one or more defect(s) on any of the 168 pads.

In order to implement interconnection redundancy, the memory architecture100suitably comprises a redundant register200, schematically shown inFIG.2A. The redundant register200is addressed using a Jtag port in case of factory redundancy and the Flash controller or the host in case of on-field redundancy so as to properly set the redundancy, with or without the low pin count interface140, such as a Jtag interface.

In particular, as shown inFIG.2A, for each extended page of the Flash memory subarray110, the redundant register200receives from the communication channel a bit address of an addressed memory cell of the Flash memory subarray110connected to a corresponding addressed pad, by means of a number of bit sufficient to identify the defective pad, for instance 8 bits, to be able to address256possible defective pads, sufficient for the example embodiment of 168 pads per channel and hence able to manage one defective pad. The pads bar for each Flash memory subarray110is indicated as210inFIG.2A.

The redundant register200stores, using the Jtag interface, the info to enable the redundancy: the register can be programmed in factory and/or by the flash controller and/or the SoC, when the on field redundancy, also called on the fly, is implemented and available. More particularly, when the redundancy on the fly is implemented, the Jtag and/or the SoC and/or the Host can be used to program the register.

Moreover, an address bus, when latched, is used as read address in the raw data buffers associated to the raw address buffers.

As will be clear from the following description, the redundant register200implements a logic intercepting defects which is always on and compares any address used by each Flash memory subarray110of the memory architecture100and the SoC embedding it so to be sure that the data is correctly routed to the SoC.

When implementing single-pad redundancy, according to the embodiment shown inFIG.2A, the redundant register200comprises a first portion220being a redundant flag of 1 bit (ON/OFF) indicating the usage of the redundancy, a second portion230for storing a location or address of the pads out of 168 that defective and a third portion240for storing a further location or address of a spare pad being used as redundant resource.

When implementing multi-pads redundancy, according to the embodiment shown inFIG.2Bfor up to 4 pads redundancy, the redundant register200comprises a first portion220being a redundant flag of 1 bit (ON/OFF) indicating the usage of the redundancy, a second portion230comprising 4 (in the example here described) groups of bits for storing four locations or addresses of the pads out of 168 that defective (for example each group includes 8 bits, to be able to address256possible combinations and therefore one of the 168 possibly defective pads) and a third portion240for storing a further location or address of four spare pads being used as redundant resources.

It can be indicated that the multi-pads redundancy is thus implemented increasing the defective pads location fields of the second portion230and by increasing the Redundant Resource bits of the third portion240: according to an example, with reference to the embodiment shown inFIG.2B, the defective pads location fields are 8 bits, and the second portion230is thus 8 bits multiplied by 4, i.e. the number of the pads that can be used for the redundancy and similarly, the Redundant Resource bits are up to 4, each bit enabling the intercepting of the failing pad in the channel according to the following logic:Bit 0: redundancy resource pad 0Bit 1: redundancy resource pad 1Bit 2: redundancy resource pad 2Bit 3: redundancy resource pad 3

More particularly, according to the single-pad redundancy embodiment of the present disclosure only a spare pad is uses, the third portion240being a field of 1 bit, in essence a further flag. In some embodiments, such third portion or further flag is not used, and the sole redundancy resource pad is directly activated: for example, the pad may be hard wired. According to the multi-pads redundancy embodiment, more than one spare pad is used, the third portion240being more than one bit, for instance, a 4 bits field able to implement up to four redundant locations or addresses of the spare pads, along with a four fields of 8 bits of the second portion230.

It can be thus indicated that the first portion220of the redundant register200is a flag indicating that the redundancy is ON, the second portion230of the redundant register200is a pads defective area and the third portion240of the redundant register200is a redundancy resource field.

According to the embodiment, when a pad is found defective, its address is stored in the second portion230and the redundant flag of the first portion220is enabled (ON), so that one of the redundant pads, having been enabled by the further enabling signal stored in the third portion240, is switched with the defective one. In other words, when the redundant flag of the first portion220is ON, the corresponding logic intercepting defects is always on and compares any address used by each Flash memory subarray110to substitute the address of memory cells corresponding to pads being found defective.

In particular, the redundant flag of the first portion220is ON, the content of the third portion240being the redundant resource is used to send the data to the SoC.

During the normal working, the universe of pads is monitored and compared with the universe of defective pad location sections of the whole enable redundant registers: when the defective location is addressed, the switch with the redundant resources is executed, the redundant flag of the first portion220being checked for its own status: enable or disable, i.e. ON or OFF.

In the case that the enable status is set (ON), the redundant pad whose address is stored in the third portion240is routed using a multi-channel MUX, so to replace the defective pad whose address is stored in the second portion230.

The redundancy register200is replicated in each sub array and the content of the corresponding portions220,230and240stored in the Flash configuration area, because the corresponding stored data, as other setting data, are stored only once.

As already indicated, according to the embodiments of the disclosure, the redundancy is always on after the power up of the Flash memory architecture100and the SoC embedding it so as to monitor continuously the communication channel, i.e. 168 pads, in the case taken as an example in the present description.

In case of a multilayer memory architecture100, a defective pad is to be substituted for all layers or pages connected to such a defective pad.

For instance, in case of an embedded Flash Replacement architecture, as schematically shown inFIG.2C, the redundant register200, also indicated as Red_R, is usually split in a high page200H and a low page200L.

According to the above explained interconnection redundancy mechanism, in case a defective pad is found and the redundant flag of the first portion220is enabled (ON), the redundant register200provides for substituting an original cell address230H with a redundant cell address240H in the high page200H as well as an original cell address230L with a redundant cell address240L in the low page200L. The pad redundancy applies to all the extended pages of the subarray and any data in, if the defect is in the used pads, as for flexible TDI.

In particular, a MUX250will receive the output parallel data POUT of the redundant cells240H and240L instead of the output parallel data POUT of the original cells230H and230L when the redundant flag220is enabled or ON. The MUX250functionality is described below with reference toFIGS.3A and3B.

The memory architecture100may in particular comprise a selection circuit300for implementing the interconnection redundancy according to an embodiment of the disclosure, as shown inFIG.3A.

In particular, the selection circuit300is connected to a pad of the memory architecture100, indicated as original pad OP as well as at least one redundant pad RP and receives addresses and enable signals from the redundant register200.

More particularly, the selection circuit300comprises a first switch SW1inserted between multiple data lines DL and the original pad OP and a second switch SW2inserted between the data lines DL and the redundant pad RP. The first switch SW1is driven by a first redundant signal RS1being an inverted value of the redundant flag stored in the first portion220of the redundant register200obtained through an inverting gate INV, while the second switch SW2is driven by a combination between the first redundant signal RS1and a second redundant signal RS2stored in the third portion240of the redundant register200obtained through a logic gate LG, being an AND gate.

In the example embodiment ofFIG.3A, the communication channel provides the redundant register200with an address corresponding to a bit being found as connected to a correctly working original pad OP, whose address AddOP is stored in the second portion230of the redundant register200. In particular, the Bit #4 (000 . . . 1000) of a memory page is connected to a “correct”, i.e. a not defective original pad OP.

In this case, the enabling flag stored in the first portion220is set equal to 1, so that the first redundant signal RS1is set equal to 0 and the first switch SW1is closed by the inverted value equal to 1. Moreover, independently from the value of the second redundant signal RS2, the logic gate LG opens the second switch SW2due to the first redundant signal RS1being set equal to 0.

In this way, the data of the data lines DL are provided to the original pad OP, which is correctly working.

In the example embodiment ofFIG.3B, the communication channel provides the redundant register200with an address corresponding to a bit being found as connected to a defective original pad OP, whose address AddOP is stored in the second portion230of the redundant register200. In particular, the Bit #4 (000 . . . 1000) of a memory page is connected to a “bad”, i.e. a defective original pad OP.

In this case, the enabling flag stored in the first portion220is set equal to 0, so that the first redundant signal RS1is set equal to 1 and the first switch SW1is open by the inverted value equal to 0. Moreover, the value of the second redundant signal RS2is set equal to 1 so that the logic gate LG, also receiving the first redundant signal RS1being set equal to 1, closes the second switch SW2.

In this way, the data of the data lines DL are provided to the redundant pad RP, so effectively bypassing the original pad OP which is not correctly working.

The redundant register200and the selection circuit300thus form an interconnection redundancy managing block included into the memory architecture100.

The exemplary configurations shown inFIGS.3A and3Brelates to a single defective pad, but it is immediate to verify that the selection circuit300can implement the proposed interconnection redundancy for any number of defective pads, up to 168, by increasing the number of registers to store the defect pad and the new one.

The memory architecture100can be included, in particular embedded, in a System-on-Chip (SoC) component and the interconnection redundancy may apply to pads connected to the SoC.

An exemplary method for managing interconnection redundancy of a memory architecture100comprising a plurality of subarrays of memory cells and a plurality of original pads OP is schematically shown inFIG.4, the method400comprising the steps of:step410: verifying a correct working of one of the original pads OP; andstep420: in case the original pad OP is correctly working, connect the original pad OP to multiple data lines DL: orstep430: in case the original pad OP is not correctly working, connect a redundant pad RP to the data lines DL.

More particularly, making reference toFIG.5, the method500comprises the steps of:step510: storing, using the Jtag interface, info to enable the redundancy;step520: storing a redundant flag in a first portion220of the redundant register200for indicating the use of a redundant pad RP; a first redundant signal RS1is associated to the redundant flag;step530: storing an address of a defective original pad OP to be switched with the redundant pad RP in a second portion230of the redundant register200; andstep540: storing in a third portion240of the redundant register200for addressing the redundant pad RP when the original pad OP is defective by not correctly working; a second redundant signal RS2is associated to the address stored in the third portion240.

It should be remarked that the redundant register200comprises only one redundant flag per Flash memory subarray110. In particular, in case of multi position defective, the redundant flag enabling redundancy is not to be repeated.

Summing up, the present disclosure provides a memory architecture comprising a plurality of subarrays, each provided with an interconnection redundancy mechanism implemented by a selection circuit connected to a redundant register.

In this way, latent defects and/or a life defects can be fixed on the fly by a SoC comprising the memory architecture, using firmware routines able to correctly control the redundant register and thus the selection circuit connected thereto.

It is underlined that the number of redundant pads being used can be customized according to needs simply managing the address to be stored and the enabling flag.

The exemplary memory architecture implementing interconnection redundancy also improves safety of the memory and of the Soc; in particular the interconnection redundancy allows to reset errors due to defective or defectively connected pads, thus increasing the ECC coverage, the ECC saving the system from single defect.

Moreover, the interconnection redundancy is suitably replicated for each subarray of the memory architecture.

It should be also remarked that the redundant register, in particular implemented in the embedded Flash Replacement device, is in the SoC that the read page has a bit re-routed somewhere else.

In this way, the interconnection redundancy is a transparent strategy.

Moreover, the redundant register is addressed using the low signal count interface140or Jtag interface, with or without a flexible TDI, which is a programmable option to improve the performance of the working of the memory architecture as a whole.

The redundant register size would depend on the number of possible redundant pads, a full interconnection redundancy being theoretically possible.

In a real implementation, the number of possible redundant pads and defects that can be corrected is limited in view of the yield study and/or the pads topology. In some embodiments, each channel (150or210) has its own redundant pad resources to repair one or more defective pads (among the 168 pads, in the example described above). In other embodiments, the redundant pad resources may be shared among different channels; e.g., a spare pad resource for redundancy may be addressed to redund a defective pads in any of the interconnection channels of the system. For example, the redundant registers200of different channels may flag that redundancy is enabled (in first portion220), store the address of the failing pad (in second portion230) and store (in third portion240) a location or address of a spare pad being used as redundant resource, the redundant resource being a shared resource.

Finally, it is underlined that the defective pads are also stored in the SoC, so as to be able to read the content of a defective pad in the redundant pad instead of the original one.

In the preceding detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific examples. In the drawings, like numerals describe substantially similar components throughout the several views. Other examples may be utilized, and structural, logical and/or electrical changes may be made without departing from the scope of the present disclosure.

Similar elements or components between different figures may be identified by the use of similar digits. As will be appreciated, elements shown in the various embodiments herein can be added, exchanged, and/or eliminated so as to provide a number of additional embodiments of the present disclosure. In addition, as will be appreciated, the proportion and the relative scale of the elements provided in the figures are intended to illustrate the embodiments of the present disclosure and should not be taken in a limiting sense.

As used herein, “a,” “an,” or “a number of” something can refer to one or more of such things. A “plurality” of something intends two or more. As used herein, the term “coupled” may include electrically coupled, directly coupled, and/or directly connected with no intervening elements (e.g., by direct physical contact) or indirectly coupled and/or connected with intervening elements. The term coupled may further include two or more elements that co-operate or interact with each other (e.g., as in a cause and effect relationship).

Although specific examples have been illustrated and described herein, those of ordinary skill in the art will appreciate that an arrangement calculated to achieve the same results can be substituted for the specific embodiments shown. This disclosure is intended to cover adaptations or variations of one or more embodiments of the present disclosure. It is to be understood that the above description has been made in an illustrative fashion, and not a restrictive one. The scope of one or more examples of the present disclosure should be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled.