Patent ID: 12198653

DETAILED DESCRIPTION

In the specification, it should be noted that like reference numerals already used to denote like elements in other drawings are used for elements wherever possible. In the following description, when a function and a configuration known to those skilled in the art are irrelevant to the essential configuration of the present disclosure, their detailed descriptions will be omitted. The terms described in the specification should be understood as follows.

Advantages and features of the present disclosure, and implementation methods thereof will be clarified through following embodiments described with reference to the accompanying drawings. The present disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Further, the present disclosure is only defined by scopes of claims.

A shape, a size, a ratio, an angle, and a number disclosed in the drawings for describing embodiments of the present disclosure are merely an example, and thus, the present disclosure is not limited to the illustrated details. Like reference numerals refer to like elements throughout. In the following description, when the detailed description of the relevant known function or configuration is determined to unnecessarily obscure the important point of the present disclosure, the detailed description will be omitted.

In a case where ‘comprise’, ‘have’, and ‘include’ described in the present specification are used, another part may be added unless ‘only’ is used. The terms of a singular form may include plural forms unless referred to the contrary.

In construing an element, the element is construed as including an error range although there is no explicit description.

It will be understood that, although the terms “first”, “second”, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.

Features of various embodiments of the present disclosure may be partially or overall coupled to or combined with each other, and may be variously inter-operated with each other and driven technically as those skilled in the art can sufficiently understand. The embodiments of the present disclosure may be carried out independently from each other, or may be carried out together in co-dependent relationship.

Hereinafter, a display device according to the present disclosure will be described in detail with reference toFIG.1.

FIG.1is a block diagram illustrating a display device according to one embodiment of the present disclosure.

Referring toFIG.1, the display device according to one embodiment of the present disclosure may include a display panel100, a timing controller110, a data drive unit120, a multiplexer unit MUX, a gate drive unit140, and a host system150.

The display panel100may be implemented as a flat panel display such as a liquid crystal display (LCD) or an organic light emitting diode (OLED) display.

The display panel100includes a plurality of gate lines G1to Gn, a plurality of data lines D1to Dm, and a plurality of pixels (not illustrated) to display an image having a predetermined gradation.

Each of the plurality of gate lines G1to Gn receives a scan pulse during a display period DP. Each of the plurality of data lines D1to Dm receives a data signal during the display period DP. The plurality of gate lines G1to Gn and the plurality of data lines D1to Dm are located on a substrate to intersect each other so as to define the plurality of pixels. Each of the plurality of pixels may include a thin film transistor (TFT) connected to an adjacent gate line and an adjacent data line, a pixel electrode PE and a common electrode CE connected to the TFT, a liquid crystal capacitor Clc between the pixel electrode PE and the common electrode CE, and a storage capacitor Cst connected to the pixel electrode PE.

The timing controller110receives, from an external system (not illustrated), various timing signals including a vertical sync signal Vsync, a horizontal sync signal Hsync, a data enable signal DE, a clock signal CKL, and the like and generates a gate control signal GCS for controlling the gate drive unit140and a data control signal DCS for controlling the data drive unit120. Further, the timing controller110receives image data from the external system, converts the received image data into image data in a form that may be processed by the data drive unit120, and outputs the converted image data.

The data drive unit120receives the data control signal DCS and the image data RGB′ from the timing controller110during the display period DP. The data control signal DCS may include a source start pulse SSP, a source sampling clock SSC, a source output enable signal SOE, and the like. The source start pulse SSP controls sampling start timings of n source drive ICs (not illustrated) constituting the data drive unit120. The source sampling clock SSC is a clock signal that controls a sampling timing of data in each source drive IC. The source output enable signal SOE controls an output timing of each source drive IC.

Further, the data drive unit120converts the received image data into an analog data signal and supplies the converted analog data signal to the pixels through the plurality of data lines D1to Dm.

The multiplexer unit MUX may time-divide the data signal and distribute the time-divided data signal to the data lines, thereby reducing the number of source drive ICs required for driving the display panel100. Further, the multiplexer unit MUX may be disposed at an end of the data lines D1to Dm through which the signal output from the data drive unit120is received in the display panel100. That is, the multiplexer unit MUX may receive the data signal output from the data drive unit120and output the received data signal to the data lines D1to Dm. The multiplexer unit MUX will be described below in detail with reference toFIGS.2to4.

The gate drive unit140receives a gate control signal GCS from the timing controller110. The gate control signal GCS may include a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal, and the like. The gate drive unit140generates a gate pulse (or a scan pulse) synchronized with the data signal through the received gate control signal GCS and shifts the generated gate pulse to sequentially supply the shifted gate pulse to the gate lines G1to Gn. To this end, the gate drive unit140may include a plurality of gate drive ICs (not illustrated). The gate drive ICs sequentially supply a gate pulse synchronized with the data signal to the gate lines G1to Gn under a control of the timing controller110during the display period DP and selects the data line in which the data signal is written. The gate pulse swings between a gate high voltage and a gate low voltage.

The host system150converts digital image data into a format suitable for displaying on the display panel100. The host system transmits the timing signals together with the digital image data to the timing controller110. The host system is implemented as any one of a television system, a set-top box, a navigation system, a digital versatile disc player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system to receive an input image.

Hereinafter, a data drive unit and a multiplexer unit according to one embodiment of the present disclosure will be described in detail with reference toFIG.2.

FIG.2is a view illustrating a data drive unit according to one embodiment of the present disclosure.

Referring toFIG.2, the data drive unit120includes a shift register circuit121, a latch circuit122, a level shifter circuit123, a digital-analog converter circuit124, a multiplexer unit MUX, and an output buffer circuit125.

The shift register circuit121receives the source start pulse SSP and the source sampling clock SSC from the timing controller110, sequentially shifts the source start pulse SSP according to the source sampling clock SSC, and outputs sampling data. The shift register circuit121transmits the sampling data to the latch circuit122.

The latch circuit122sequentially samples and latches the image data into predetermined units according to the sampling data. The latch circuit122transmits the latched image data to the level shifter circuit123.

The level shifter circuit123amplifies the level of the latched image data. In detail, the level shifter circuit123amplifies the level of the image data to a level in which the digital-analog converter circuit124may be driven. The level shifter circuit123transmits the level-amplified image data to the digital-analog converter circuit124.

The digital-analog converter circuit124converts the image data into the data signal that is an analog signal. The digital-analog converter circuit124transmits the data signal converted into the analog signal to the output buffer circuit125.

The output buffer circuit125outputs a source signal to the data lines. In detail, the output buffer circuit125buffers and outputs the source signal according to the source output enable signal SOE generated by the timing controller110.

The output buffer circuit125, which is a buffer amplifier, supplies a positive (+) data signal or a negative (−) data signal to source channels ch1-ch6. For example, the output buffer circuit125may supply the positive (+) data signal to first, third, and fifth source channels ch1, ch3, and ch5, and the output buffer circuit125may supply the negative (−) data signal to second, fourth, and sixth source channels ch2, ch4, and ch6.

The multiplexer unit MUX time-divides and supplies the data signal input from the digital-analog converter circuit124to the data lines D1to Dm according to the signal output from the timing controller110. A 2:1 multiplexer time-divides the data signal input through one output line of the digital-analog converter circuit124by the timing controller110and supplies the time-divided data signal to two output buffer circuits125. Thus, when the 2:1 multiplexer is used, the number of shift register circuits121, the number of latch circuits122, the number of level shifter circuits123, the number of digital-analog converter circuit124, and the number of output buffer circuits125may be reduced by half, and thus the area of the source drive IC can be reduced by half.

According to one embodiment of the present disclosure, the multiplexer unit MUX includes a first multiplexer MUX1and a second multiplexer MUX2.

Hereinafter, the multiplexer unit and the pixel array according to one embodiment of the present disclosure will be described in detail with reference toFIGS.3to5H.

FIG.3is a view illustrating a multiplexer unit and a pixel array according to one embodiment of the present disclosure.FIG.4is a view illustrating a gate signal and a signal waveform output from a multiplexer according to one embodiment of the present disclosure.FIGS.5A to5Hare views illustrating respective drive operations of the multiplexer unit and the pixel array according to one embodiment of the present disclosure.

According to one embodiment of the present disclosure, the multiplexer unit MUX includes first to fourth switches T1to T4. First and second multiplexer control signals M1and M2may be supplied to gates of the first to fourth switches T1to T4. The switches T1to T4are connected to the source channels ch1-ch6and the data lines D1to Dm of the data drive unit120.

The multiplexer unit MUX time-divides a data voltage output from the source drive IC according to the first and second multiplexer control signals M1and M2provided from the timing controller110and distributes the time-divided data voltage to the data lines D1to Dm. The first and second multiplexer control signals M1and M2are generated in opposite phases. The second multiplexer control signal M2may be generated by inverting the first multiplexer control signal M1using an inverter. A switching period of the first and second multiplexer control signals M1and M2is one horizontal period. The one horizontal period is a time required to input data to pixels arranged in one horizontal line of the pixel. Accordingly, the first and second multiplexers MUX1and MUX2have the switching period of one horizontal period, are turned on during half of the horizontal period, and are turned off during half of the horizontal period.

According to one embodiment of the present disclosure, the source channels ch1-ch6are connected to data lines D1-D12through the first and second multiplexers MUX1and MUX2. As illustrated inFIG.3, the first source channel ch1is connected to the first and third data lines D1and D3through the first and second multiplexers MUX1and MUX2, and the second source channel ch2is connected to the second and fourth data lines D2and D4through the first and second multiplexers MUX1and MUX2.

In detail, a (4n-3)thdata line (n is a natural number) may receive a data signal output from a (2n-1)thsource channel (n is a natural number) through the first multiplexer MUX1, and a (4n-2)thdata line (n is a natural number) may receive a data signal output from a 2nthsource channel (n is a natural number) through the first multiplexer MUX1. Further, a (4n-1)thdata line (n is a natural number) may receive the data signal output from the (2n-1)thsource channel (n is a natural number) through the second multiplexer MUX2, and a (4n)thdata line (n is a natural number) may receive the data signal output from the 2nthsource channel (n is a natural number) through the second multiplexer MUX2.

The first switch T1is connected between the first source channel ch1and the first data line D1and supplies, to the first data line D1, a positive data voltage output through the first source channel ch1in response to the first multiplexer control signal M1. The second switch T2is connected between the second source channel ch2and the second data line D2and supplies, to the second data line D2, a negative data voltage output through the second source channel ch2in response to the first multiplexer control signal M1. Although not illustrated, the first and second switches T1and T2may be alternately turned on.

The third switch T3is connected between the first source channel ch1and the third data line D3and supplies, to the third data line D3, a positive data voltage output through the first source channel ch1in response to the second multiplexer control signal M2. The fourth switch T4is connected between the second source channel ch2and the fourth data line D4and supplies, to the fourth data line D4, a negative data voltage output through the second source channel ch2in response to the second multiplexer control signal M2. Although not illustrated, the third and fourth switches T3and T4may be alternately turned on.

First to third vertical lines C1to C3respectively extending along the first to third data lines D1to D3may be defined. A first color pixel, a second color pixel, and a third color pixel are arranged on the first vertical line C1to the third vertical line C3, respectively. In this case, the first color may be red (R), the second color may be green (G), and the third color may be blue (B).

Pixels of odd-numbered horizontal lines GATE1and GATE3and pixels of even-numbered horizontal lines GATE2and GATE4may be connected in a zigzag manner in a direction in which the pixels are connected to the data lines. For example, the pixels arranged on the odd-numbered horizontal lines GATE1and GATE3are connected to the data lines arranged on the left side of the corresponding pixels, and the pixels arranged on the even-numbered horizontal lines GATE2and GATE4are connected to the data lines arranged on the right side of the corresponding pixels.

Referring toFIGS.3to5H, the multiplexer unit and the pixels according to one embodiment of the present disclosure may be driven to display an image according to first to eighth drive operations ST1-ST8.

According to one embodiment of the present disclosure, the pixels may be driven according to the gate signals and the first and second multiplexer control signals illustrated inFIG.4.

According to one embodiment of the present disclosure, as illustrated inFIG.4, in the first to fourth drive operations ST1-ST4, when the gate signal is input to the first horizontal line GATE1and the second horizontal line GATE2, the first multiplexer MUX1and the second multiplexer MUX2are sequentially turned on.

In the first drive operation ST1and the second drive operation ST2, the gate signal is input to the pixels located on the first horizontal line GATE1. That is, as illustrated inFIG.4, in the first drive operation ST1, the first multiplexer MUX1is turned on, and in the second drive operation ST2, the second multiplexer MUX2is turned on. Accordingly, as illustrated inFIG.5A, in the first drive operation ST1, the first and second switches T1and T2connected to the first multiplexer MUX1are turned on, and thus, the pixels located on the first horizontal line GATE1and connected to the first multiplexer MUX1are turned on, and as illustrated inFIG.5B, in the second drive operation ST2, the third and fourth switches T3and T4connected to the second multiplexer MUX2are turned on, and thus, the pixels located on the first horizontal line GATE1and connected to the second multiplexer MUX2are turned on. For example, as illustrated inFIGS.4,5A, and5B, in the first drive operation ST1, a pixel G12located on the first horizontal line GATE1and connected to the third source channel ch3through the first multiplexer MUX1is turned on, and in the second drive operation ST2, a pixel R13located on the first horizontal line GATE1and connected to the third source channel ch3through the second multiplexer MUX2is turned on.

Further, in the third drive operation ST3and the fourth drive operation ST4, the gate signal is input to the pixels located on the second horizontal line GATE2. That is, as illustrated inFIG.4, in the third drive operation ST3, the first multiplexer MUX1is turned on, and in the second drive operation ST4, the second multiplexer MUX2is turned on. Accordingly, as illustrated inFIG.5C, in the third drive operation ST3, the first and second switches T1and T2connected to the first multiplexer MUX1are turned on, and thus, the pixels located on the second horizontal line GATE2and connected to the first multiplexer MUX1are turned on, and as illustrated inFIG.5D, in the fourth drive operation ST4, the third and fourth switches T3and T4connected to the second multiplexer MUX2are turned on, and thus, the pixels located on the second horizontal line GATE2and connected to the second multiplexer MUX2are turned on. For example, as illustrated inFIGS.4,5C, and5D, in the third drive operation ST3, a pixel R22located on the second horizontal line GATE2and connected to the third source channel ch3through the first multiplexer MUX1is turned on, and in the fourth drive operation ST4, a pixel B22located on the second horizontal line GATE2and connected to the third source channel ch3through the second multiplexer MUX2is turned on.

According to one embodiment of the present disclosure, as illustrated inFIG.4, in the fifth to eighth drive operations ST5to ST8, when the gate signal is input to the third horizontal line GATE3and the fourth horizontal line GATE4, the first multiplexer MUX1and the second multiplexer MUX2are turned on in a reverse order.

In the fifth drive operation ST5and the sixth drive operation ST6, the gate signal is input to the pixels located on the third horizontal line GATE3. That is, as illustrated inFIG.4, in the fifth drive operation ST5, the second multiplexer MUX2is turned on, and in the sixth drive operation ST6, the first multiplexer MUX1is turned on. Accordingly, as illustrated inFIG.5E, in the fifth drive operation ST5, the third and fourth switches T3and T4connected to the second multiplexer MUX2are turned on, and thus, the pixels located on the third horizontal line GATE3and connected to the second multiplexer MUX2are turned on, and as illustrated inFIG.5F, in the sixth drive operation ST6, the first and second switches T1and T2connected to the first multiplexer MUX1are turned on, and thus, the pixels located on the third horizontal line GATE3and connected to the first multiplexer MUX1are turned on. For example, as illustrated inFIGS.4,5E, and5F, in the fifth drive operation ST5, a pixel R33located on the third horizontal line GATE3and connected to the third source channel ch3through the second multiplexer MUX2is turned on, and in the sixth drive operation ST6, a pixel G32located on the third horizontal line GATE3and connected to the third source channel ch3through the first multiplexer MUX1is turned on.

Further, in the seventh drive operation ST7and the eighth drive operation ST8, the gate signal is input to the pixels located on the fourth horizontal line GATE4. That is, as illustrated inFIG.4, in the seventh drive operation ST7, the second multiplexer MUX2is turned on, and in the eighth drive operation ST8, the first multiplexer MUX1is turned on. Accordingly, as illustrated inFIG.5G, in the seventh drive operation ST7, the third and fourth switches T3and T4connected to the second multiplexer MUX2are turned on, and thus, the pixels located on the fourth horizontal line GATE4and connected to the second multiplexer MUX2are turned on, and as illustrated inFIG.5H, in the eighth drive operation ST8, the first and second switches T1and T2connected to the first multiplexer MUX1are turned on, and thus, the pixels located on the fourth horizontal line GATE4and connected to the first multiplexer MUX1are turned on. For example, as illustrated inFIGS.4,5G, and5H, in the seventh drive operation ST7, a pixel B42located on the fourth horizontal line GATE4and connected to the third source channel ch3through the second multiplexer MUX2is turned on, and in the eighth drive operation ST8, a pixel R42located on the fourth horizontal line GATE4and connected to the third source channel ch3through the first multiplexer MUX1is turned on.

According to one embodiment of the present disclosure, while the gate signal is input to the first to fourth horizontal lines GATE1to GATE4, the multiplexer unit MUX is driven in the first to eighth drive operations ST1to ST8. In detail, the first multiplexer MUX1and the second multiplexer MUX2are driven sequentially in the first to fourth drive operation ST1to ST4and are driven in the fifth to eighth drive operation ST5to ST8in a reverse order. Accordingly, since the pixels located on one vertical line are not displayed in the same order, display defects due to vertical line recognition can be prevented.

A display device and a method of driving the same according to the present disclosure can uniformly display an image by changing an operation order of multiplexers.

It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure.

In addition, at least a part of the methods described herein may be implemented using one or more computer programs or components. These components may be provided as a series of computer instructions through a computer-readable medium or a machine-readable medium, which includes volatile and non-volatile memories. The instructions may be provided as software or firmware and may be entirely or partially implemented in a hardware configuration such as application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), digital signal processors (DSPs), or other similar devices. The instructions may be configured to be executed by one or more processors or other hardware components, and when one or more processors or other hardware components execute the series of computer instructions, one or more processors or other hardware components may entirely or partially perform the methods and procedures disclosed herein.

Therefore, it should be understood that the above-described embodiments are not restrictive but illustrative in all aspects. The scope of the present disclosure is defined by the appended claims rather than the detailed description, and it should be construed that all alternations or modifications derived from the meaning and scope of the appended claims and the equivalents thereof fall within the scope of the present disclosure.