Patent ID: 12253876

DETAILED DESCRIPTION

In principle it is possible to create, in advance, a respective latency table for every elementary operation that can be executed on a specific FPGA, from which table the latency of the respective operation can be read as a function of the clock rate and the bit width of the input data. By means of these tables, the latency of a data path in an FPGA model as a function of the clock rate can then be identified in a simple way by adding up the individual latencies for each elementary operation of the data path. To this end,FIG.1shows a plot of the latency of a multiplication operation on a specific FPGA as a function of the clock rate of the FPGA and of the bit width of the operation. InFIG.1, the latency is specified in periods. What is represented, therefore, is how many periods at a given bit width of the operation and a respective clock rate are required to operate the FPGA for complete execution of the operation.

If it is now of interest to identify the clock rate at a given bit width for which the fastest possible execution will result, then the product of the clock rate and the number of periods required for complete execution is key. The same is represented inFIG.2, which shows a plot of the latency of the same multiplication operation as inFIG.1as a function of the clock rate of the FPGA and of the bit width of the operation, wherein inFIG.2the latency is now specified in nanoseconds (ns). The clock rate at which the lowest latency results is shown inFIG.2as a cross-hatched bar for each of the bit widths of 8 bits, 16 bits, 24 bits, and 32 bits. It can be seen that this lowest latency of approximately 10 ns is in a range of a little over 100 MHz. As is evident fromFIG.2, a significantly longer latency results in each case for higher clock rates to above 500 MHz, so that a relatively low clock rate provides the best results here.

The latencies are represented as three-dimensional bar charts inFIG.1andFIG.2, in one case specified in the number of periods and in one case specified in the time (in ns) for complete execution of the operation as a function of the bit width and the clock rate. However, this manner of representation merely serves the purpose of illustration in the present case. For provision of a respective latency table for the elementary operations of the provided library that can be executed on the FPGA in order to execute a method according to the invention, however, it is advantageous to provide these data in the form of a numeric table in which a latency as a time quantity, for example in nanoseconds, is associated with each pair formed of a bit width and a clock rate. A table of this nature can be stored as a lookup table, for example, which can be accessed digitally during the execution of a method according to the invention. Such a table can in principle appear as follows, wherein only latencies for clock rates of 60 to 140 MHz and 8 to 40 bits are specified here by way of example.

60 MHz80 MHz100 MHz120 MHz140 MHz. . .8 bits40 ns21 ns18 ns10 ns14 ns. . .16 bits40 ns21 ns19 ns10 ns15 ns. . .24 bits40 ns32 ns22 ns12 ns18 ns. . .32 bits40 ns35 ns23 ns13 ns19 ns. . .40 bits40 ns36 ns25 ns15 ns21 ns. . .. . .. . .. . .. . .. . .. . .. . .

These clock rates correspond to a different operation that is not the basis forFIGS.1and2. Apart from this, it should be noted that tables are always provided that are created for discrete clock rates, with a spacing of 20 MHz from one another in the case of the above table. In this regard, it is of course also possible to provide a finer grid of clock rates; even though this increases the effort for creating the latency tables, it does permit more precise identification of the clock rate that allows the fastest execution in the FPGA for an elementary operation or a specific data path.

Now, as regards the identification of the total latency for a data path that is formed of a multiplicity of elementary operations, please refer toFIG.3. It is shown schematically there that the data path considered in the present case includes an addition with an input bit width of 16 bits, a multiplication with an input bit width of 16 bits and an output bit width of 32 bits, and a root function with an input bit width of 32 bits and an output bit width of 16 bits. If the total latency is now to be determined for this data path represented inFIG.3, then the latencies (in ns) specified in the respective associated latency table for the three functions of addition, multiplication, and root function must be added up for all clock rates and at the respective input bit width of the corresponding operation.

This is represented schematically inFIG.4, in which the axis labels have been omitted in the three-dimensional bar charts for the sake of clarity. The arrows indicate by way of example how, for a certain clock rate, it is necessary to add up, firstly, the latency for the addition for 16 bits, then the corresponding latency for the multiplication for 16 bits, and finally the latency for the root function of 32 bits. This results in the bar chart for all clock rates depicted at the very bottom inFIG.4that depict the total latency, which is to say the totals of the latencies of the addition, the multiplication, and the root function, as a function of the respective clock rate. It can be seen that the addition path, shown by way of example with arrows, is associated with the particular clock rate that delivers the lowest total latency overall. It is notable in this regard that the lowest latency in each case for the three different elementary operations occurs at entirely different and significantly lower clock rates (represented inFIG.4as cross-hatched bars). However, when these three elementary operations are combined, the procedure described here results in an entirely different clock rate that delivers the best result in the present case for the operation of the FPGA.

In this way, it is possible to determine, for every data path intended to be used in operation of the FPGA, a clock rate that is “optimal” inasmuch as it corresponds to the clock rate with the lowest total latency. As already addressed above, it may be the primary goal to minimize the latency of the data paths for a control loop. However, there are also other goals, such as the maximum possible precision, lowest possible resource demand or energy consumption, etc. Since the FPGA always prescribes certain boundary conditions, such as existing resources and maximum power consumption, there consequently is never only a single goal, but instead always at least one secondary goal in addition to a primary goal. As a rule, therefore, it is always necessary to aim for multiple goals at once, which is achieved in the present case by the means that a quality factor is determined for every clock rate while taking into account the total latency as well as the utilization of the FPGA. This is described in detail below.

InFIG.5, a resource profile is depicted that correlates with the clock cycle count profile fromFIG.1and the latency time profile fromFIG.2. Here, the resource demand measured as a percentage of the total FPGA resources is plotted on the z-axis. The profiles can be provided separately for the most important FPGA resources of LUTs, flipflops, DSPs, blockRAM, and can be extended to additional FPGA resources of AI cores of FPGAs. It is thus also possible to address dedicated, especially scarce resources during the method. For easier visualization, the percentage values of the individual components inFIG.5are added with equal weighting and divided by the number of components.

In order to illustrate that some clock rate changes produce especially large potential savings, delta resource profiles (Δ resources), which correspond to the first derivative of the resources with respect to the clock cycle, have been calculated inFIG.6from the resource profiles.FIG.6should be understood here such that the high bars cause a great change in the resources. This means that an increase in the clock rate at certain points produces a disproportionately high increase in the resource demand.

With the aid of the profiles described with reference toFIGS.1to4and the resource profiles described earlier, a large data set of information relating to the quantities of clock rate, latency, processing speed, resource demand, and precision/bit width (power demand) can be obtained. Various questions can be answered very efficiently from these data, e.g., the following questions:1. The data path width is set, a low latency is very important, and the desire is to determine an implementation that can still be accommodated in the FPGA or does not exceed a given FPGA size under these boundary conditions.2. The desire is to determine the widest data path, which is to say the data path with the highest precision, that can still be accommodated in the FPGA or does not exceed a specified FPGA size at a given processing speed or at a given latency. In this way, it is also possible, e.g., to efficiently identify whether a design can be converted from the fixed-point format to the simpler-to-model but more resource-intensive floating-point format.

In addition, a power profile can also be created for each operation as a function of bit width and clock rate. For this reason, another question can be:3. The bit width is set, and the desire is to optimize the data paths in order to obtain the greatest power saving with the smallest possible changes so that a predetermined power budget is not exceeded.

Question 1 is considered by way of example below. The principle of the method is represented inFIG.7:

A new clock rate is sought that leads to maximum resource saving with minimal degradation in latency. In principle,FIG.7corresponds toFIG.4, wherein dashed lines are now additionally depicted as examples with similarly low total latencies at lower clock rates that generally lead to a lower resource consumption.

The procedure for optimizing the FPGA resources for a data path is explained below. This procedure is used when the FPGA implements only one data path or when each data path gets its own clock domain, and it can therefore be assumed that all data paths can be optimized independently of one another. When there are multiple data paths and, e.g., only one clock domain for all of the logic, then cross-dependencies arise during optimization of an individual data path because a change in the clock rate directly affects the other data paths.

The individual steps for optimization of a data path are as follows:

First, a latency profile l(c) as a function of the clock rate c and the optimal-latency clock rate now are determined, as described above on the basis ofFIGS.1to4. Then the identification of the data path resource demand r(c) or/and, if applicable, the data path power demand p(c) takes place. All values that are above a specific resource or power limit (provided by the total resources of the FPGA or the available current/the available cooling capacity) are set to −1 and thus are invalid solutions. Then the identification of the gain gpath(c) of the data path with an alternative, resource-saving or/and energy-saving clock cycle relative to the result with optimal total latency takes place. For this purpose, the minimum latency l(clopt) at the clock rate cloptand in general the latency l(c) as a function of the clock rate c as well as the lowest resource demand r(cropt) and the resource demand r(c) (or power demand p(cpopt), p(c)) are placed in a ratio as in the formula below. The weighting of the optimization goals of latency or resources/power can be carried out by a weighting wlfor latency and wrfor resources/power on the basis of a gain function, for example the following gain function (1.1):

gpath(c)=12⁢(wl⁢l⁡(clopt)l⁡(c)+wr⁢r⁡(cropt)r⁡(c))(1.1)

The value of the function gpathis the quality factor of the clock rate c, on which basis a decision is made as to whether the clock rate c is a suitable clock rate for operation of the FPGA. It can be seen inFIG.8that the highest gain is close to a more resource-saving, lower clock rate. If the resources were to have more than 50% weight, the difference would be more pronounced. In this example, no resource limit was drawn, which is to say no gains were set to −1. Oftentimes, the optimal-latency frequency is not available at all due to a resource limit, and clearer gain ratios arise.

The step of resource identification/power identification is depicted inFIG.9. It can essentially be seen there that a frequency with lower resource demand was found through the gain function.

It represents an option that, in the case of multiple data paths, the model does not operate with separate clock frequencies for each data path, but instead there is a grouping of multiple data paths into one clock domain. Then it is not the gains of the individual paths that are to be identified, but instead the gains of the individual domains, and in each case the clock frequency for an entire domain is to be replaced. Also optional is a change in the implementation variant: Most computation operations exist as both LUT and DSP implementation variants. In order to conserve certain scarce resources such as LUTs or DSPs, it is also possible for the analysis to take into account an automatic switching the implementation variant in an additional step. The latency behavior can also change as a result, of course.

The following applies in general:

The method can be formulated as follows for the FPGA modeling in general and for arbitrary optimization goals z that are dependent on the clock frequency c and have different weightings w:

gpath(c)=1∑iwi⁢∑iwi⁢zi(ciopt)zi(c)(1.2)

Since the profiles used are also dependent on the bit width b, the method can in principle also be applied to the bit width and accordingly be formulated as follows:

gpath(b)=1∑iwi⁢∑iwi⁢zi(biopt)zi(b)(1.3)

The bit width of an operation is set in formula 1.2 so that only the clock rate can be varied, which influences the processing speed. In formula 1.3, in contrast, the bit width is varied at a fixed clock rate, which influences precision. If there are no specifications with regard to the processing speed or the precision, a two-dimensional gain function can ultimately also be formulated:

gpath(b,c)=1∑iwi⁢∑iwi⁢zi(biopt,ciopt)zi(b,c)(1.4)

In the case of the two-dimensional gain function, a two-dimensional result function is obtained in the representation of the result instead of a one-dimensional result function as inFIGS.7,8, and9. Practice-oriented questions can generally be mapped to the one-dimensional gain functions 1.2 and 1.3, however.

Accordingly, the complete generalization of the multi-goal optimizations dependent on n parameters p is:

gpath(p1,p2,…,pn)=1∑iwi⁢∑iwi⁢zi(p1iopt,p2iopt,…,pniopt)zi(p1,p2,…,pn)(1.5)

The method can work with default values for the weights, or can offer the user parameterization, for example via sliders from 0 to 1 for each goal, as depicted inFIG.10. The latency La, the resources Re, the power Po, and an additional parameter Pa can be adjusted as goals here. The difference by which the weight of a goal has been shifted is distributed among the other goals uniformly and inversely.

The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are to be included within the scope of the following claims.