Patent ID: 12250487

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to embodiments illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. In the drawings, the shape and thickness may be exaggerated for clarity and convenience. This description will be directed in particular to elements forming part of, or cooperating more directly with, methods and apparatus in accordance with the present disclosure. It is to be understood that elements not specifically shown or described may take various forms well known to those skilled in the art. Many alternatives and modifications will be apparent to those skilled in the art, once informed by the present disclosure.

Unless otherwise specified, some conditional sentences or words, such as “can”, “could”, “might”, or “may”, usually attempt to express what the embodiment in the invention has, but it can also be interpreted as a feature, element, or step that may not be needed. In other embodiments, these features, elements, or steps may not be required.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Certain terms are used throughout the description and the claims to refer to particular components. One skilled in the art appreciates that a component may be referred to using different names. This disclosure does not intend to distinguish between components that differ in name but not in function. In the description and in the claims, the term “comprise” is used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to.” The phrases “be coupled to,” “couples to,” and “coupling to” are intended to encompass any indirect or direct connection. Accordingly, if this disclosure mentions that a first device is coupled with a second device, it means that the first device may be directly or indirectly connected to the second device through electrical connections, wireless communications, optical communications, or other signal connections with/without other intermediate devices or connection means.

The invention is particularly described with the following examples which are only for instance. Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the following disclosure should be construed as limited only by the metes and bounds of the appended claims. In the whole patent application and the claims, except for clearly described content, the meaning of the articles “a” and “the” includes the meaning of “one or at least one” of the elements or components. Moreover, in the whole patent application and the claims, except that the plurality can be excluded obviously according to the context, the singular articles also contain the description for the plurality of elements or components. In the entire specification and claims, unless the contents clearly specify the meaning of some terms, the meaning of the article “wherein” includes the meaning of the articles “wherein” and “whereon”. The meanings of every term used in the present claims and specification refer to a usual meaning known to one skilled in the art unless the meaning is additionally annotated. Some terms used to describe the invention will be discussed to guide practitioners about the invention. The examples in the present specification do not limit the claimed scope of the invention.

In the following description, an image readout device will be described. The image readout device employs a control capacitor and a control switch to control the transition time points of output signals not to occur at the same time, in other words, to control the transition time points of output signals to occur at different times, thereby reducing a peak current and an IR drop (voltage drop). The image readout devices described below may also be applied to other circuit configurations.

FIG.4is a diagram schematically illustrating an image sensor according to a first embodiment of the invention. Referring toFIG.4, an image sensor3is introduced as follows. The image sensor3includes a row decoder30, an image sensor array31which is taken as a sensing pixel array, a ramp generator32, and an image readout device33. The row decoder30is coupled to the image sensor array31. The image sensor array31and the ramp generator32are coupled to the image readout device33. The row decoder30drives the pixels of the image sensor array31row by row to transmit pixel signals VPIX of each pixel row (depicted in a vertical direction inFIG.4) to the image readout device33. The ramp generator32generates and transmits reference signals to the image readout device33. The reference signal may be, but not limited to, a ramp signal VRMP. The image readout device33includes a plurality of comparator circuits330. Each comparator circuit330is corresponding to a sensing pixel column (depicted in a horizontal direction inFIG.4) and receives the pixel signals VPIX from the sensing pixel column, and each comparator circuit330compares the pixel signal VPIX and the ramp signal VRMP to generate a comparison signal. The image readout device33inverts the comparison signals to generate output signals VOUT. In order to control the transition time points of voltage levels of the output signals VOUT not to occur at the same time, the comparator circuits330can be divided into a plurality of groups and respective control signals may be applied to the respective groups of the comparator circuits330. For clarity and convenience, the comparator circuits330can be divided into two groups. In addition, two different control signals AZ1D[0] and AZ1D[1] are respectively provided to the two groups of the comparator circuits330to control the transition time points of voltage levels of the output signals VOUT not to occur at the same time. For example, one group of the comparator circuits330outputs the output signals VOUT earlier and the other group of the comparator circuits330outputs the output signals VOUT later. In the first embodiment (as shown inFIG.4) of the image sensor3, a plurality of comparator circuits330of each group of the comparator circuits330are corresponding to a plurality of adjacent sensing pixel columns. However, the invention is not limited to the arrangement of sensing pixel columns corresponding to each group of the comparator circuits330.

FIG.5is a diagram schematically illustrating an image sensor according to a second embodiment of the invention. Referring toFIG.5, the second embodiment of the image sensor3is introduced as follows. The second embodiment of the image sensor3is different from the first embodiment of the image sensor3in the arrangement of groups of the comparator circuits330and corresponding sensing pixel columns. The other technical features have been described previously so it will not be reiterated. In the second embodiment of the image sensor3, the comparator circuits330are divided into a first group and a second group. Two different control signals AZ1D[0] and AZ1D[1] are respectively provided to the first and the second groups of the comparator circuits330, to control the output signals VOUT of different groups of the comparator circuits transiting at different times. The comparator circuits330in the first group and the second group are alternately arranged, which means that positions of sensing pixel columns corresponding to the first group of the comparator circuits330and positions of the other sensing pixel columns corresponding to the second group of the comparator circuits330are alternately arranged.

FIG.6is a diagram schematically illustrating an image sensor according to a third embodiment of the invention. Referring toFIG.6, the third embodiment of the image sensor3is introduced as follows. The third embodiment of the image sensor3is different from the first embodiment of the image sensor3in the arrangement groups of the of the comparator circuits330corresponding sensing pixel columns. The other technical features have been described previously so it will not be reiterated. In the third embodiment of the image sensor3, the comparator circuits330are divided into a first group and a second group. The comparator circuits330in the first group and the second group are randomly arranged, which means that positions of sensing pixel columns corresponding to the first group of the comparator circuits330and positions of the other sensing pixel columns corresponding to the second group of the comparator circuits330are neither adjacent nor alternate, but randomly arranged.

FIG.7is a diagram schematically illustrating a comparator circuit according to a first embodiment of the invention.FIG.8is a diagram schematically illustrating the waveforms of the auto-zero control signal, the first control signal, the pixel signal, the reference signal, the input voltages of the amplifier, the comparison signal, and the output signal of the comparator circuit corresponding toFIG.7. Referring toFIG.7andFIG.8, the first embodiment of the comparator circuit330is introduced as follows. The comparator circuit330includes an amplifier3300, an input capacitor3301named as a first input capacitor, an auto-zero switch3302named as a first auto-zero switch, and at least one control capacitor3303named as a first control capacitor. For clarity and convenience, the first embodiment exemplifies one control capacitor3303. The amplifier3300has a first input node, a second input node, and a first output node. In the first embodiment, the first input node may be a negative (a.k.a. inverting) input node, the second input node may be a positive (a.k.a. non-inverting) input node, and the first output node may be a positive output node. The input capacitor3301has a first end and a second end. The first end of the input capacitor3301is coupled to the first input node of the amplifier3300. The auto-zero switch3302has a first end, a second end, and a control end. The first end of the auto-zero switch3302is coupled to the first input node of the amplifier3300. The second end of the auto-zero switch3302is coupled to the first output node of the amplifier3300. The control capacitor3303has a first end and a second end. The first end of the control capacitor3303is coupled to the first input node of the amplifier3300.

In order to effectively read the pixel signals VPIX, the image readout device may further include a plurality of inverters331and a plurality of counters332. The inverters331are respectively coupled to the first output nodes of the amplifiers3300of the comparator circuits330. The counters332are respectively coupled to the inverters331.

The operation of the first embodiment of the comparator circuit330is introduced as follows. The first input node and the second input node of the amplifier3300respectively receive a pixel signal VPIX from the image sensor array and a reference signal. The reference signal may be, but not limited to, a ramp signal VRP. The amplifier3300compares the pixel signal VPIX to the ramp signal VRMP to generate a comparison signal VCMP from the first output node. The second end of the input capacitor3301is coupled to the pixel signal VPIX. The control end of the auto-zero switch3302is coupled to an auto-zero control signal VAZ. The auto-zero control signal VAZ is configured to couple or decouple the first input node of the amplifier3300to the first output node of the amplifier3300. The second end of the control capacitor3303is coupled to a respective control signal AZ1D named as a respective first control signal. In addition, the input voltage of the negative input node of the amplifier3300is represented with VIN. The input voltage of the positive input node of the amplifier3300is represented with VIP. The inverters331convert the comparison signals VCMP generated from the comparator circuits330into a plurality of output signals VOUT which transition between a high level and a low level based on a predetermined voltage level. Each counter332counts one of the output signals VOUT to generate a digital counting value corresponding to the pixel signal VPIX.

As illustrated inFIG.8, the input voltages VIN and VIP respectively follow the voltage levels of the pixel signal VPIX and the ramp signal VRMP. The respective control signal AZ1D is different from the auto-zero control signal VAZ. Specifically, the active period of the respective control signal AZ1D may be larger than the active period of the auto-zero control signal VAZ. The leading edge of the respective control signal AZ1D is at the same time as the leading edge of the auto-zero control signal VAZ. The trailing edge of the respective control signal AZ1D is later than the trailing edge of the auto-zero control signal VAZ. When the voltage level of the auto-zero control signal VAZ rises from a logic low level to a logic high level, the auto-zero switch3302is turned on to couple the first input node of the amplifier3300to the first output node of the amplifier3300, such that the input voltage VIN is equal to the input voltage VIP. Simultaneously, the voltage level of the respective control signal AZ1D rises from a logic low level to a logic high level. When the voltage level of the auto-zero control signal VAZ descends from the logic high level to the logic low level, the auto-zero switch3302is turned off to decouple the first input node of the amplifier3300to the first output node of the amplifier3300. Afterwards, the voltage level of the respective control signal AZ1D descends from the logic high level to the logic low level. For example, the voltage level of the respective control signal AZ1D is decreased by ΔAZ1D. When the voltage level of the respective control signal AZ1D is decreased by ΔAZ1D, the voltage level of the input voltage VIN is decreased by ΔVIN, thereby changing the transition time points of voltages of the comparison signal VCMP and the output signal VOUT. The comparator circuits330are divided into a plurality of groups. Based on the foregoing mechanism, the voltage level transition of the respective control signal AZ1D causes the transition time points of the comparison signal VCMP and the output signal VOUT change. The transition time points of the comparison signal VCMP and the output signal VOUT depend on the input capacitor3301, the control capacitor3303, the respective control signal AZ1D, and the ramp signal VRP as the reference signal. The transition time points of the output signals VOUT of the groups of the comparator circuits330are respectively set and partially or completely occurring at different times (i.e., the output signals VOUT do not transit at the same time), thereby reducing the peak current and the IR drop (voltage drop). Compared to the comparison signal VCMP inFIG.3(which is also depicted inFIG.8by the dashed waveform), the comparison signal VCMP (depicted in solid waveform) inFIG.8changes due to the voltage difference ΔVIN and results in that the transition time point of the output signal VOUT is delayed by a time delay denoted as td. Specifically, ΔVIN and td are respectively represented by equations (1) and (2).

Δ⁢VIN=COSNCOSN+CINN⁢Δ⁢AZ⁢1⁢D(1)td=COSNCOSN+CINN⁢Δ⁢AZ⁢1⁢D⁢dtdVVRMP(2)

COSNrepresents the capacitance of the control capacitor3303. CINNrepresents the capacitance of the input capacitor3301. t represents time. VVRMPrepresents the voltage of the ramp signal VRMP.

FIG.9is a diagram schematically illustrating a comparator circuit coupled to an inverter and a counter according to a second embodiment of the invention. Referring toFIG.9, the second embodiment of the comparator circuit330is introduced as follows. Compared to the first embodiment of the comparator circuit330, the second embodiment of the comparator circuit330further includes a control capacitor3305named as a second control capacitor. The control capacitor3305has a first end and a second end. The first end of the control capacitor3305is coupled to the second input node of the amplifier3300. The second end of the control capacitor3305is grounded. The control capacitor3305does not influence the waveforms of the auto-zero control signal VAZ, the control signal AZ1D, the pixel signal VPIX, the ramp signal VRMP, the input voltages VIN and VIP, the comparison signal VCMP, and the output signal VOUT inFIG.8. The other technical features ofFIG.9have been described previously so it will not be reiterated.

FIG.10is a diagram schematically illustrating a comparator circuit coupled to an inverter and a counter according to a third embodiment of the invention. Referring toFIG.10, the third embodiment of the comparator circuit330is introduced as follows. Compared to the first embodiment of the comparator circuit330, the third embodiment of the comparator circuit330further includes an input capacitor3304named as a second input capacitor and an auto-zero switch3306named as a second auto-zero switch. In the third embodiment, the amplifier3300has a second output node implemented with a negative output node. The input capacitor3304has a first end and a second end. The first end of the input capacitor3304is coupled to the second input node of the amplifier3300. The second end of the input capacitor3304is coupled to the ramp signal VRMP as the reference signal. The auto-zero switch3306has a first end, a second end, a control end. The first end of the auto-zero switch3306is coupled to the second input node of the amplifier3300. The second end of the auto-zero switch3306is coupled to the second output node of the amplifier3300.

The control end of the auto-zero switch3306is coupled to the auto-zero control signal VAZ. The auto-zero control signal VAZ is configured to couple or decouple the second input node of the amplifier3300and the second output node of the amplifier3300. When the voltage level of the auto-zero control signal VAZ rises from a logic low level to a logic high level, the auto-zero switch3306is turned on to couple the second input node and the second output node of the amplifier3300and help cancel the voltage offset between the input voltages VIN and VIP. When the voltage level of the auto-zero control signal VAZ descends from the logic high level to the logic low level, the auto-zero switch3306is turned off to decouple the second input node and the second output node of the amplifier3300. The input capacitor3304and the auto-zero switch3306do not influence the waveforms of the auto-zero control signal VAZ, the control signal AZ1D, the pixel signal VPIX, the ramp signal VRMP, the input voltages VIN and VIP, the comparison signal VCMP, and the output signal VOUT inFIG.8. In addition, the auto-zero switch3306may be applied to the second embodiment ofFIG.9. The other technical features ofFIG.10have been described previously so it will not be reiterated.

FIG.11is a diagram schematically illustrating a comparator circuit coupled to an inverter and a counter according to a fourth embodiment of the comparator circuit330. Referring toFIG.11andFIG.10, the fourth embodiment of the comparator circuit330is introduced as follows. Compared to the third embodiment of the comparator circuit330ofFIG.10, the fourth embodiment of the comparator circuit330does not have the input capacitor3304. The omitted input capacitor3304does not influence the waveforms of the auto-zero control signal VAZ, the control signal AZ1D, the pixel signal VPIX, the ramp signal VRMP, the input voltages VIN and VIP, the comparison signal VCMP, and the output signal VOUT inFIG.8. The other technical features ofFIG.11have been described previously so it will not be reiterated.

FIG.12is a diagram schematically illustrating a comparator circuit coupled to an inverter and a counter according to a fifth embodiment of the invention. Referring toFIG.12, the fifth embodiment of the comparator circuit330is introduced as follows. Compared to the third embodiment of the comparator circuit330, the fifth embodiment of the comparator circuit330further includes a control capacitor3305named as a second control capacitor. The control capacitor3305has a first end and a second end. The first end of the control capacitor3305is coupled to the second input node of the amplifier3300. The second end of the control capacitor3305is grounded. The control capacitor3305does not influence the waveforms of the auto-zero control signal VAZ, the control signal AZ1D, the pixel signal VPIX, the ramp signal VRMP, the input voltages VIN and VIP, the comparison signal VCMP, and the output signal VOUT inFIG.8. The other technical features ofFIG.12have been described previously so it will not be reiterated.

FIG.13is a diagram schematically illustrating a comparator circuit coupled to an inverter and a counter according to a sixth embodiment of the invention.FIG.14is a diagram schematically illustrating the waveforms of the auto-zero control signal, the first control signals, the pixel signal, the reference signal, the input voltages of the amplifier, the comparison signal, and the output signal corresponding toFIG.13. Referring toFIG.13andFIG.14, the sixth embodiment of the comparator circuit330is introduced as follows. Compared to the first embodiment of the comparator circuit330, the sixth embodiment of the comparator circuit330exemplifies a plurality of control capacitors3303. The second ends of the control capacitors3303are respectively coupled to the respective control signals AZ1D[1]˜AZ1D[N]. N is a natural number greater than 1. The number of the control capacitors3303is greater than or equal to the number of the groups of the comparator circuit330. If the number of the groups of the comparator circuit330is equal to two, the number of the control capacitors3303is greater than or equal to two, and two of the control capacitors3303may be respectively selected to receive the respective control signals AZ1D[1] and AZ1D[2] and the remains of the control capacitors3303may be electrically floating. The other technical features ofFIG.13have been described previously so it will not be reiterated.

As illustrated inFIG.14, AZ1D[N:1] includes the respective control signals AZ1D[1]˜AZ1D[N]. The input voltages VIN and VIP respectively follow the voltage levels of the pixel signal VPIX and the ramp signal VRMP. Each of the respective control signals AZ1D[1]˜AZ1D[N] is different from the auto-zero control signal VAZ. Specifically, the active period of each of the respective control signals AZ1D[1]˜AZ1D[N] may be larger than the active period of the auto-zero control signal VAZ. The leading edge of each of the respective control signals AZ1D[1]˜AZ1D[N] is at the same time as the leading edge of the auto-zero control signal VAZ. The trailing edge of each of the respective control signals AZ1D[1]˜AZ1D[N] is later than the trailing edge of the auto-zero control signal VAZ. When the voltage level of the auto-zero control signal VAZ rises from a logic low level to a logic high level, the auto-zero switch3302is turned on to couple the first input node of the amplifier3300to the first output node of the amplifier3300, such that the input voltage VIN is equal to the input voltage VIP. Simultaneously, the voltage level of each of the respective control signals AZ1D[1]˜AZ1D[N] rises from a logic low level to a logic high level. When the voltage level of the auto-zero control signal VAZ descends from the logic high level to the logic low level, the auto-zero switch3302is turned off to decouple the first input node of the amplifier3300to the first output node of the amplifier3300. Afterwards, the voltage level of each of the respective control signals AZ1D[1]˜AZ1D[N] descends from the logic high level to the logic low level. For example, the voltage levels of the respective control signals AZ1D[1]˜AZ1D[N] are respectively decreased by ΔAZ1D[1]˜ΔAZ1D[N]. ΔAZ1D[N:1] includes ΔAZ1D[1]˜ΔAZ1D[N]. When the voltage levels of the respective control signals AZ1D[1]˜AZ1D[N] are respectively decreased by ΔAZ1D[1]˜ΔAZ1D[N], the voltage level of the input voltage VIN is decreased by ΔVIN, thereby changing the transition time points of voltages of the comparison signal VCMP and the output signal VOUT. The comparator circuits330are divided into a plurality of groups. Based on the foregoing mechanism, the voltage level transition of each of the respective control signals AZ1D[1]˜AZ1D[N] causes the transition time points of the comparison signal VCMP and the output signal VOUT change. The transition time points of the comparison signal VCMP and the output signal VOUT depend on the input capacitor3301, the control capacitors3303, the respective control signals AZ1D[1]˜AZ1D[N], and the ramp signal VRMP as the reference signal. The transition time points corresponding to the groups are respectively set and partially or completely occurring at different times, thereby reducing the peak current and the IR drop. Compared to the comparison signal VCMP inFIG.3(which is also depicted inFIG.14by the dashed waveform), the comparison signal VCMP (depicted in solid waveform) inFIG.14changes due to the voltage difference ΔVIN and results in that the transition time point of the output signal VOUT is delayed by the time delay td. Specifically, ΔVIN and td are respectively represented by equations (3) and (4).

Δ⁢VIN=∑i=1NCOSN[i]⁢Δ⁢AZ⁢1⁢D[i]∑i=1NCOSN[i]+CINN(3)td=∑i=1NCOSN[i]⁢Δ⁢AZ⁢1⁢D[i]∑i=1NCOSN[i]+CINN⁢dtdVVRMP(4)

COSN[i] represents the capacitance of the i-th control capacitor3303.

FIG.15is a diagram schematically illustrating a comparator circuit coupled to an inverter and a counter according to a seventh embodiment of the invention.FIG.16is a diagram schematically illustrating the waveforms of the auto-zero control signal, the first control signals, the second control signals, the pixel signal, the reference signal, the input voltages of the amplifier, the comparison signal, and the output signal corresponding toFIG.15. Referring toFIG.15andFIG.16, the seventh embodiment of the comparator circuit330is introduced as follows. Compared to the sixth embodiment of the comparator circuit330, the seventh embodiment of the comparator circuit330further includes an input capacitor3304, at least one control capacitor3305, and an auto-zero switch3306. The technical features of the input capacitor3304and the auto-zero switch3306have been described in the third embodiment ofFIG.10. The seventh embodiment of the comparator circuit330exemplifies a plurality of control capacitors3305. Each control capacitor3305has a first end and a second end. The first end of each control capacitor3305is coupled to the second input node of the amplifier3300. The second ends of the control capacitors3305are respectively coupled to respective control signals AZ1DB[1]˜AZ1DB[N] named as respective second control signals. The number of the control capacitors3305is greater than or equal to the number of the groups of the comparator circuit330. If the number of the groups of the comparator circuit330is equal to two, the number of the control capacitors3305is greater than or equal to two, and two of the control capacitors3305may be respectively selected to receive the respective control signals AZ1DB[1] and AZ1DB[2] and the remains of the control capacitors3305may be electrically floating. The other technical features ofFIG.15have been described previously so it will not be reiterated.

As illustrated inFIG.16, AZ1DB[N:1] includes the respective control signals AZ1DB[1]˜AZ1D[N]. The input voltages VIN and VIP respectively follow the voltage levels of the pixel signal VPIX and the ramp signal VRMP. The waveform of the input voltage VIN inFIG.16is identical to the waveform of the input voltage VIN inFIG.14. Each of the respective control signals AZ1DB[1]˜AZ1DB[N] is different from the auto-zero control signal VAZ. Specifically, the active period of each of the respective control signals AZ1DB[1]˜AZ1DB[N] may be larger than the active period of the auto-zero control signal VAZ. The leading edge of each of the respective control signals AZ1DB[1]˜AZ1DB[N] is at the same time as the leading edge of the auto-zero control signal VAZ. The trailing edge of each of the respective control signals AZ1DB[1]˜AZ1DB[N] is later than the trailing edge of the auto-zero control signal VAZ. When the voltage level of the auto-zero control signal VAZ rises from a logic low level to a logic high level, the auto-zero switch3302and the auto-zero switch3306are turned on to couple the first input node of the amplifier3300to the first output node of the amplifier3300and couple the second input node of the amplifier3300to the second output node of the amplifier3300, such that the input voltage VIN is equal to the input voltage VIP. Simultaneously, the voltage level of each of the respective control signals AZ1DB[1]˜AZ1DB[N] descends from a logic high level to a logic low level. When the voltage level of the auto-zero control signal VAZ descends from the logic high level to the logic low level, the auto-zero switch3302and the auto-zero switch3306are turned off to decouple the first input node of the amplifier3300to the first output node of the amplifier3300and decouple the second input node of the amplifier3300to the second output node of the amplifier3300. Afterwards, the voltage level of each of the respective control signals AZ1DB[1]˜AZ1DB[N] rises from the logic low level to the logic high level. For example, the voltage levels of the respective control signals AZ1DB[1]˜AZ1DB[N] are respectively increased by ΔAZ1DB[1]˜ΔAZ1DB[N]. ΔAZ1DB[N:1] includes ΔAZ1DB[1]˜ΔAZ1DB[N]. When the voltage levels of the respective control signals AZ1DB[1]˜AZ1DB[N] are respectively increased by ΔAZ1DB[1]˜ΔAZ1DB[N], the voltage level of the input voltage VIP is increased by ΔVIP, thereby changing the transition time points of voltages of the comparison signal VCMP and the output signal VOUT. The comparator circuits330are divided into a plurality of groups. Based on the foregoing mechanism, the voltage level transition of each of the respective control signals AZ1D[1]˜AZ1D[N] and the respective control signals AZ1DB[1]˜AZ1DB[N] causes the transition time points of the comparison signal VCMP and the output signal VOUT change. The transition time points of the comparison signal VCMP and the output signal VOUT depend on the input capacitor3301, the control capacitors3303, the respective control signals AZ1D[1]˜AZ1D[N], the input capacitor3304, the control capacitors3305, the respective control signals AZ1DB[1]˜AZ1DB[N], and the ramp signal VRMP as the reference signal. The transition time points corresponding to the groups are respectively set and partially or completely occurring at different times, thereby reducing the peak current and the IR drop. Compared to the comparison signal VCMP inFIG.3(which is also depicted inFIG.16by the dashed waveform), the comparison signal VCMP (depicted in solid waveform) inFIG.16changes due to the voltage difference ΔVIP and results in that the transition time point of the output signal VOUT is delayed by the time delay td. Specifically, ΔVIP and td are respectively represented by equations (5) and (6).

Δ⁢VIP=∑i=1NCOSP[i]⁢Δ⁢AZ⁢1⁢DB[i]∑i=1NCOSP[i]+CINP(5)td=(∑i=1NCOSN[i]⁢Δ⁢AZ⁢1⁢D[i]∑i=1NCOSN[i]+CINN+∑i=1NCOSP[i]⁢Δ⁢AZ⁢1⁢DB[i]∑i=1NCOSP[i]+CINP)⁢dtdVVRMP(6)

COSP[i] represents the capacitance of the i-th control capacitor3305. CINPrepresents the capacitance of the input capacitor3304.

FIG.17is a diagram schematically illustrating a voltage generation circuit according to an embodiment of the invention. Referring toFIG.17andFIG.7, the second end of the control capacitor3303may be coupled to a voltage generation circuit4. The voltage generation circuit4may include, but is not limited to, a voltage dividing resistor string40, a plurality of electrical switches41, a first buffer42, and a second buffer43. The voltage dividing resistor string40includes a plurality of resistors400coupled in series. Anode between the two adjacent resistors400is coupled to an end of the electrical switch41and another end of the electrical switch41is coupled to the input of the first buffer42. The output of the first buffer42is coupled to the second buffer43. The output of the second buffer43may be coupled to the second end of the control capacitor3303. The voltage dividing resistor string40receives a reference voltage VREF to generate an adjustable voltage A. By turning one of the electrical switches41, the adjustable voltage A is transmitted to the first buffer42and the second buffer43. The second buffer43receives an input signal IN and the adjustable voltage A to generate the respective control signal AZ1D. The respective control signal AZ1D has an active period and an amplitude in the active period, wherein the amplitude depends on the adjustable voltage A.

FIG.18is a diagram schematically illustrating a comparator circuit coupled to an inverter and a counter according to an eighth embodiment of the invention.FIG.19is a diagram schematically illustrating the waveforms of the auto-zero control signal, the first control signal, the pixel signal, the reference signal, the input voltages of the amplifier, the comparison signal, and the output signal corresponding toFIG.18. Referring toFIG.18andFIG.19, the eighth embodiment of the comparator circuit330is introduced as follows. The comparator circuit330includes an amplifier3300, an input capacitor3304named as a first input capacitor, an auto-zero switch3306named as a first auto-zero switch, and at least one control capacitor3305named as a first control capacitor. For clarity and convenience, the ninth embodiment exemplifies one control capacitor3305. The amplifier3300has a first input node, a second input node, a first output node, and a second output node. In the eighth embodiment, the first input node may be a positive input node, the second input node may be a negative input node, and the first output node and the second output node may be respectively a negative output node and a positive output node. The input capacitor3304has a first end and a second end. The first end of the input capacitor3304is coupled to the first input node of the amplifier3300. The auto-zero switch3306has a first end, a second end, and a control end. The first end of the auto-zero switch3306is coupled to the first input node of the amplifier3300. The second end of the auto-zero switch3306is coupled to the first output node of the amplifier3300. The control capacitor3305has a first end and a second end. The first end of the control capacitor3305is coupled to the first input node of the amplifier3300.

In order to effectively read the pixel signals VPIX, the image readout device may further include a plurality of inverters331and a plurality of counters332. The inverters331are respectively coupled to the second output nodes of the amplifiers3300of the comparator circuits330. The counters332are respectively coupled to the inverters331.

The operation of the eighth embodiment of the comparator circuit330is introduced as follows. The first input node and the second input node of the amplifier3300respectively receive a reference signal and a pixel signal VPIX from the image sensor array. The reference signal may be, but not limited to, a ramp signal VRMP. The amplifier3300compares the pixel signal VPIX to the ramp signal VRMP to generate a comparison signal VCMP from the second output node. The second end of the input capacitor3304is coupled to the ramp signal VRMP. The control end of the auto-zero switch3306is coupled to an auto-zero control signal VAZ. The auto-zero control signal VAZ is configured to couple or decouple the first input node of the amplifier3300to the first output node of the amplifier3300. The second end of the control capacitor3305is coupled to a respective control signal AZ1DB named as a respective first control signal. In addition, the input voltage of the negative input node of the amplifier3300is represented with VIN. The input voltage of the positive input node of the amplifier3300is represented with VIP. The inverters331convert the comparison signals VCMP generated from the comparator circuits330into a plurality of output signals VOUT which transition between a high level and a low level based on a predetermined voltage level. Each counter332counts one of the output signals VOUT to generate a digital counting value corresponding to the pixel signal VPIX.

As illustrated inFIG.19, the input voltages VIN and VIP respectively follow the voltage levels of the pixel signal VPIX and the ramp signal VRMP. The respective control signal AZ1DB is different from the auto-zero control signal VAZ. Specifically, the active period of the respective control signal AZ1DB may be larger than the active period of the auto-zero control signal VAZ. The leading edge of the respective control signal AZ1DB is at the same time as the leading edge of the auto-zero control signal VAZ. The trailing edge of the respective control signal AZ1DB is later than the trailing edge of the auto-zero control signal VAZ. When the voltage level of the auto-zero control signal VAZ rises from a logic low level to a logic high level, the auto-zero switch3306is turned on to couple the first input node of the amplifier3300to the first output node of the amplifier3300, such that the input voltage VIN is equal to the input voltage VIP. Simultaneously, the voltage level of the respective control signal AZ1DB descends from a logic high level to a logic low level. When the voltage level of the auto-zero control signal VAZ descends from the logic high level to the logic low level, the auto-zero switch3306is turned off to decouple the first input node of the amplifier3300to the first output node of the amplifier3300. Afterwards, the voltage level of the respective control signal AZ1DB rises from the logic low level to the logic high level. For example, the voltage level of the respective control signal AZ1DB is increased by ΔAZ1DB. When the voltage level of the respective control signal AZ1DB is increased by ΔAZ1DB, the voltage level of the input voltage VIP is increased by ΔVIP, thereby changing the transition time points of voltages of the comparison signal VCMP and the output signal VOUT. The comparator circuits330are divided into a plurality of groups. Based on the foregoing mechanism, the voltage level transition of the respective control signal AZ1DB causes the transition time points of the comparison signal VCMP and the output signal VOUT change. The transition time points of the comparison signal VCMP and the output signal VOUT depend on the input capacitor3304, the control capacitor3305, the respective control signal AZ1DB, and the ramp signal VRMP as the reference signal. The transition time points corresponding to the groups are respectively set and partially or completely occurring at different times, thereby reducing the peak current and the IR drop. Compared to the comparison signal VCMP inFIG.3(which is also depicted inFIG.19by the dashed waveform), the comparison signal VCMP (depicted in solid waveform) inFIG.19changes due to the voltage difference ΔVIP and results in that the transition time point of the output signal VOUT is delayed by the time delay td. Specifically, ΔVIP and td are respectively represented by equations (7) and (8).

Δ⁢VIP=COSPCOSP+CINP⁢Δ⁢AZ⁢1⁢DB(7)td=COSPCOSP+CINP⁢Δ⁢AZ⁢1⁢DB⁢dtdVVRMP(8)

COSPrepresents the capacitance of the control capacitor3305. CINPrepresents the capacitance of the input capacitor3304.

Referring toFIG.17andFIG.18, the output of the second buffer43may be coupled to the second end of the control capacitor3305. The second buffer43may receive the input signal IN and the adjustable voltage A to generate the respective control signal AZ1DB.

FIG.20is a diagram schematically illustrating a comparator circuit coupled to an inverter and a counter according to a ninth embodiment of the invention. Referring toFIG.20, the ninth embodiment of the comparator circuit330is introduced as follows. Compared to the eighth embodiment of the comparator circuit330, the ninth embodiment of the comparator circuit330further includes a control capacitor3303named as a second control capacitor. The control capacitor3303has a first end and a second end. The first end of the control capacitor3303is coupled to the second input node of the amplifier3300. The second end of the control capacitor3303is grounded. The control capacitor3303does not influence the waveforms of the auto-zero control signal VAZ, the control signal AZ1DB, the pixel signal VPIX, the ramp signal VRMP, the input voltages VIN and VIP, the comparison signal VCMP, and the output signal VOUT inFIG.19. The other technical features ofFIG.20have been described previously so it will not be reiterated.

FIG.21is a diagram schematically illustrating a comparator circuit coupled to an inverter and a counter according to a tenth embodiment of the invention. Referring toFIG.21, the tenth embodiment of the comparator circuit330is introduced as follows. Compared to the eighth embodiment of the comparator circuit330, the tenth embodiment of the comparator circuit330further includes an input capacitor3301named as a second input capacitor and an auto-zero switch3302. The input capacitor3301has a first end and a second end. The first end of the input capacitor3301is coupled to the second input node of the amplifier3300. The second end of the input capacitor3301is coupled to the pixel signal VPIX. The auto-zero switch3302has a first end, a second end, and a control end. The first end of the auto-zero switch3302is coupled to the second input node of the amplifier3300. The second end of the auto-zero switch3302is coupled to the second output node of the amplifier3300. The control end of the auto-zero switch3302is coupled to the auto-zero control signal VAZ. The auto-zero control signal VAZ is configured to couple or decouple the second input node of the amplifier3300and the second output node of the amplifier3300. When the voltage level of the auto-zero control signal VAZ rises from a logic low level to a logic high level, the auto-zero switch3302is turned on to couple the second input node and the second output node of the amplifier3300and help cancel the voltage offset between the input voltages VIN and VIP. When the voltage level of the auto-zero control signal VAZ descends from the logic high level to the logic low level, the auto-zero switch3302is turned off to decouple the second input node and the second output node of the amplifier3300. The input capacitor3301and the auto-zero switch3302do not influence the waveforms of the auto-zero control signal VAZ, the control signal AZ1DB, the pixel signal VPIX, the ramp signal VRMP, the input voltages VIN and VIP, the comparison signal VCMP, and the output signal VOUT inFIG.19. In addition, the auto-zero switch3302may be applied to the ninth embodiment ofFIG.20. The other technical features ofFIG.21have been described previously so it will not be reiterated.

FIG.22is a diagram schematically illustrating a comparator circuit coupled to an inverter and a counter according to an eleventh embodiment of the invention. Referring toFIG.22andFIG.21, the eleventh embodiment of the comparator circuit330is introduced as follows. Compared to the tenth embodiment of the comparator circuit330, the eleventh embodiment of the comparator circuit330further includes a control capacitor3303named as a second control capacitor. The control capacitor3303has a first end and a second end. The first end of the control capacitor3303is coupled to the second input node of the amplifier3300. The second end of the control capacitor3303is grounded. The control capacitor3303does not influence the waveforms of the auto-zero control signal VAZ, the control signal AZ1DB, the pixel signal VPIX, the ramp signal VRMP, the input voltages VIN and VIP, the comparison signal VCMP, and the output signal VOUT inFIG.19. The other technical features ofFIG.22have been described previously so it will not be reiterated.

FIG.23is a diagram schematically illustrating a comparator circuit coupled to an inverter and a counter according to a twelfth embodiment of the invention.FIG.24is a diagram schematically illustrating the waveforms of the auto-zero control signal, the first control signals, the pixel signal, the reference signal, the input voltages of the amplifier, the comparison signal, and the output signal corresponding toFIG.23. Referring toFIG.23andFIG.24, the twelfth embodiment of the comparator circuit330is introduced as follows. Compared to the eighth embodiment of the comparator circuit330, the twelfth embodiment of the comparator circuit330exemplifies a plurality of control capacitors3305. The second ends of the control capacitors3305are respectively coupled to the respective control signals AZ1DB[1]˜AZ1DB[N]. The number of the control capacitors3305is greater than or equal to the number of the groups of the comparator circuit330. If the number of the groups of the comparator circuit330is equal to two, the number of the control capacitors3305is greater than or equal to two, and two of the control capacitors3305are respectively selected to receive the respective control signals AZ1DB[1] and AZ1DB[2] and the remains of the control capacitors3305are electrically floating. The other technical features ofFIG.23have been described previously so it will not be reiterated.

As illustrated inFIG.24, AZ1DB[N:1] includes the respective control signals AZ1DB[1]˜AZ1DB[N]. The input voltages VIN and VIP respectively follow the voltage levels of the pixel signal VPIX and the ramp signal VRMP. Each of the respective control signals AZ1DB[1]˜AZ1DB[N] is different from the auto-zero control signal VAZ. Specifically, the active period of each of the respective control signals AZ1DB[1]˜AZ1DB[N] may be larger than the active period of the auto-zero control signal VAZ. The leading edge of each of the respective control signals AZ1DB[1]˜AZ1DB[N] is at the same time as the leading edge of the auto-zero control signal VAZ. The trailing edge of each of the respective control signals AZ1DB[1]˜AZ1DB[N] is later than the trailing edge of the auto-zero control signal VAZ. When the voltage level of the auto-zero control signal VAZ rises from a logic low level to a logic high level, the auto-zero switch3306is turned on to couple the first input node of the amplifier3300to the first output node of the amplifier3300, such that the input voltage VIN is equal to the input voltage VIP. Simultaneously, the voltage level of each of the respective control signals AZ1DB[1]˜AZ1DB[N] descends from a logic high level to a logic low level. When the voltage level of the auto-zero control signal VAZ rises from the logic low level to the logic high level, the auto-zero switch3306is turned off to decouple the first input node of the amplifier3300to the first output node of the amplifier3300. Afterwards, the voltage level of each of the respective control signals AZ1DB[1]˜AZ1DB[N] rises from the logic low level to the logic high level. For example, the voltage levels of the respective control signals AZ1DB[1]˜AZ1DB[N] are respectively increased by ΔAZ1DB[1]˜ΔAZ1DB[N]. ΔAZ1DB[N:1] includes ΔAZ1DB[1]˜ΔAZ1DB[N]. When the voltage levels of the respective control signals AZ1DB[1]˜AZ1DB[N] are respectively decreased by ΔAZ1DB[1]˜ΔAZ1DB[N], the voltage level of the input voltage VIP is increased by ΔVIP, thereby changing the transition time points of voltages of the comparison signal VCMP and the output signal VOUT. The comparator circuits330are divided into a plurality of groups. Based on the foregoing mechanism, the voltage level transition of each of the respective control signals AZ1DB[1]˜AZ1DB[N] causes the transition time points of the comparison signal VCMP and the output signal VOUT change. The transition time points of the comparison signal VCMP and the output signal VOUT depend on the input capacitor3304, the control capacitors3305, the respective control signals AZ1DB[1]˜AZ1DB[N], and the ramp signal VRMP as the reference signal. The transition time points corresponding to the groups are respectively set and partially or completely occurring at different times, thereby reducing the peak current and the IR drop. Compared to the comparison signal VCMP inFIG.3(which is also depicted inFIG.24by the dashed waveform), the comparison signal VCMP (depicted in solid waveform) inFIG.24changes due to the voltage difference ΔVIP and results in that the transition time point of the output signal VOUT is delayed by the time delay td. Specifically, ΔVIP and td are respectively represented by equations (9) and (10).

Δ⁢VIP=∑i=1NCOSP[i]⁢Δ⁢AZ⁢1⁢DB[i]∑i=1NCOSP[i]+CINP(9)td=∑i=1NCOSP[i]⁢Δ⁢AZ⁢1⁢DB[i]∑i=1NCOSP[i]+CINP⁢dtdVVRMP(10)

FIG.25is a diagram schematically illustrating a comparator circuit coupled to an inverter and a counter according to a thirteenth embodiment of the invention.FIG.26is a diagram schematically illustrating the waveforms of the auto-zero control signal, the first control signal, the pixel signal, the reference signal, the input voltages of the amplifier, the comparison signal, and the output signal corresponding toFIG.25. Referring toFIG.25andFIG.26, the thirteenth embodiment of the comparator circuit330is introduced as follows. The comparator circuit330includes an amplifier3300, an input capacitor3301named as a first input capacitor, an auto-zero switch3302named as a first auto-zero switch, and at least one control switch3307named as a first control switch. For clarity and convenience, the thirteenth embodiment exemplifies one control switch3307. The control switch3307may be, but not limited to, a metal-oxide-semiconductor field-effect transistor (MOSFET) or a suitable transistor. The amplifier3300has a first input node, a second input node, a first output node, and a second output node. In the thirteenth embodiment, the first input node, the second input node, the first output node, and the second output node may be respectively a negative input node, a positive input node, a positive output node, and a negative output node. The input capacitor3301has a first end and a second end. The first end of the input capacitor3301is coupled to the first input node of the amplifier3300. The auto-zero switch3302has a first end, a second end, and a control end. The first end of the auto-zero switch3302is coupled to the first input node of the amplifier3300. The second end of the auto-zero switch3302is coupled to the first output node of the amplifier3300. The control switch3307has a first end, a second end, and a control end. The first end of the control switch3307is coupled to the first input node of the amplifier3300. The second end of the control switch3307is coupled to the first output node of the amplifier3300.

In order to effectively read the pixel signals VPIX, the image readout device may further include a plurality of inverters331and a plurality of counters332. The inverters331are respectively coupled to the first output nodes of the amplifiers3300of the comparator circuits330. The counters332are respectively coupled to the inverters331.

The operation of the thirteenth embodiment of the comparator circuit330is introduced as follows. The first input node and the second input node of the amplifier3300respectively receive a pixel signal VPIX from the image sensor array and a reference signal. The reference signal may be, but not limited to, a ramp signal VRMP. The amplifier3300compares the pixel signal VPIX to the ramp signal VRMP to generate a comparison signal VCMP from the first output node. The second end of the input capacitor3301is coupled to the pixel signal VPIX or the reference signal. In the thirteenth embodiment, the second end of the input capacitor3301is coupled to the pixel signal VPIX. The control end of the auto-zero switch3302is coupled to an auto-zero control signal VAZ. The auto-zero control signal VAZ is configured to couple or decouple the first input node of the amplifier3300to the first output node of the amplifier3300. The control end of the control switch3307is coupled to a respective control signal AZ1D named as a respective first control signal. In addition, the input voltage of the negative input node of the amplifier3300is represented with VIN. The input voltage of the positive input node of the amplifier3300is represented with VIP. The inverters331convert the comparison signals VCMP generated from the comparator circuits330into a plurality of output signals VOUT which transition between a high level and a low level based on a predetermined voltage level. Each counter332counts one of the output signals VOUT to generate a digital counting value corresponding to the pixel signal VPIX.

As illustrated inFIG.26, the input voltages VIN and VIP respectively follow the voltage levels of the pixel signal VPIX and the ramp signal VRMP. The respective control signal AZ1D is identical to the auto-zero control signal VAZ. When the voltage level of the auto-zero control signal VAZ rises from a logic low level to a logic high level, the auto-zero switch3302is turned on to couple the first input node of the amplifier3300to the first output node of the amplifier3300, such that the input voltage VIN is equal to the input voltage VIP. Simultaneously, the voltage level of the respective control signal AZ1D rises from a logic low level to a logic high level. When the voltage level of the auto-zero control signal VAZ descends from the logic high level to the logic low level, the auto-zero switch3302is turned off to decouple the first input node of the amplifier3300to the first output node of the amplifier3300. Simultaneously, the voltage level of the respective control signal AZ1D descends from the logic high level to the logic low level. For example, the voltage levels of the respective control signal AZ1D and the auto-zero control signal VAZ are respectively decreased by ΔAZ1D and ΔVAZ. When the voltage levels of the respective control signal AZ1D and the auto-zero control signal VAZ are respectively decreased by ΔAZ1D and ΔVAZ, the voltage level of the input voltage VIN is decreased by ΔVIN, thereby changing the transition time points of voltages of the comparison signal VCMP and the output signal VOUT. Assume that the auto-zero switch3302and the control switch3307are implemented with NMOSFETs. The source and the drain of the NMOSFET are respectively coupled to the first input node and the first output node of the amplifier3300. The gate of the NMOSFET receives the respective control signal AZ1D or the auto-zero control signal VAZ. In other words, ΔVIN is caused by ΔAZ1D, ΔVAZ, and the parasitic gate-source capacitances of the NMOSFETs. The comparator circuits330are divided into a plurality of groups. Based on the foregoing mechanism, the voltage level transition of the respective control signal AZ1D causes the transition time points of the comparison signal VCMP and the output signal VOUT change. The transition time points of the comparison signal VCMP and the output signal VOUT depend on the input capacitor3301, the parasitic gate-source capacitances, the respective control signal AZ1D, the auto-zero control signal VAZ, and the ramp signal VRMP as the reference signal. The transition time points corresponding to the groups are respectively set and partially or completely occurring at different times, thereby reducing the peak current and the IR drop. Compared to the comparison signal VCMP inFIG.3(which is also depicted inFIG.26by the dashed waveform), the comparison signal VCMP (depicted in solid waveform) inFIG.27changes due to the voltage difference ΔVIN and results in that the transition time point of the output signal VOUT is delayed by the time delay td. Specifically, ΔVIN and td are respectively represented by equations (11) and (12).

Δ⁢VIN=CGSN⁢Δ⁢VAZ+CgsN⁢Δ⁢AZ⁢1⁢DCGSN+CgsN+CINN(11)td=CGSN⁢Δ⁢VAZ+CgsN⁢Δ⁢AZ⁢1⁢DCGSN+CgsN+CINN⁢dtdVVRMP(12)

COSNrepresents the parasitic gate-source capacitance of the auto-zero switch3302. CgsNrepresents the parasitic gate-source capacitance of the control switch3307.

FIG.27is a diagram schematically illustrating a comparator circuit coupled to an inverter and a counter according to a fourteenth embodiment of the invention.FIG.28is a diagram schematically illustrating the waveforms of the auto-zero control signal, the first control signal, the pixel signal, the reference signal, the input voltages of the amplifier, the comparison signal, and the output signal corresponding toFIG.27. Referring toFIG.25andFIG.27, the fourteenth embodiment of the comparator circuit330is introduced as follows. Compared to the thirteenth embodiment of the comparator circuit330, the fourteenth embodiment of the comparator circuit330further includes an input capacitor3304named as a second input capacitor and an auto-zero switch3306named as a second auto-zero switch. The input capacitor3304has a first end and a second end. The first end of the input capacitor3304is coupled to the second input node of the amplifier3300. The second end of the input capacitor3304is coupled to the reference signal or the pixel signal VPIX. In the fourteenth embodiment, the second end of the input capacitor3304is coupled to the reference signal. The auto-zero switch3306has a first end, a second end, and a control end. The first end of the auto-zero switch3306is coupled to the second input node of the amplifier3300. The second end of the auto-zero switch3306is coupled to the second output node of the amplifier3300. The control end of the auto-zero switch3306is coupled to the auto-zero control signal VAZ which is configured to couple or decouple the second input node of the amplifier3300and the second output node of the amplifier3300.

As illustrated inFIG.28, the input voltages VIN and VIP respectively follow the voltage levels of the pixel signal VPIX and the ramp signal VRMP. The respective control signal AZ1D is identical to the auto-zero control signal VAZ. When the voltage level of the auto-zero control signal VAZ rises from a logic low level to a logic high level, the auto-zero switch3302and the auto-zero switch3306are turned on to couple the first input node of the amplifier3300to the first output node of the amplifier3300and couple the second input node of the amplifier3300to the second output node of the amplifier3300, such that the input voltage VIN is equal to the input voltage VIP. Simultaneously, the voltage level of the respective control signal AZ1D rises from a logic low level to a logic high level. When the voltage level of the auto-zero control signal VAZ descends from the logic high level to the logic low level, the auto-zero switch3302and the auto-zero switch3306are turned off to decouple the first input node of the amplifier3300to the first output node of the amplifier3300and decouple the second input node of the amplifier3300to the second output node of the amplifier3300. Simultaneously, the voltage level of the respective control signal AZ1D descends from the logic high level to the logic low level. For example, the voltage levels of the respective control signal AZ1D and the auto-zero control signal VAZ are respectively decreased by ΔAZ1D and ΔVAZ. When the voltage levels of the respective control signal AZ1D and the auto-zero control signal VAZ are respectively decreased by ΔAZ1D and ΔVAZ, the voltage levels of the input voltages VIN and VIP are respectively decreased by ΔVIN and ΔVIP, thereby changing the transition time points of voltages of the comparison signal VCMP and the output signal VOUT. Assume that the auto-zero switch3302, the auto-zero switch3306, and the control switch3307are implemented with NMOSFETs. The source and the drain of each of the auto-zero switch3302and the control switch3307are respectively coupled to the first input node and the first output node of the amplifier3300. The gate of each of the auto-zero switch3302and the control switch3307receives the respective control signal AZ1D or the auto-zero control signal VAZ. The source and the drain of the auto-zero switch3306are respectively coupled to the second input node and the second output node of the amplifier3300. The gate of the auto-zero switch3306receives the auto-zero control signal VAZ. In other words, ΔVIN is caused by ΔAZ1D, ΔVAZ, and the parasitic gate-source capacitances of the auto-zero switch3302and the control switch3307. ΔVIP is caused by ΔVAZ and the parasitic gate-source capacitance of the auto-zero switch3306. The comparator circuits330are divided into a plurality of groups. Based on the foregoing mechanism, the voltage level transition of the respective control signal AZ1D causes the transition time points of the comparison signal VCMP and the output signal VOUT change. The transition time points of the comparison signal VCMP and the output signal VOUT depend on the input capacitors3301and3304, the parasitic gate-source capacitances, the respective control signal AZ1D, the auto-zero control signal VAZ, and the ramp signal VRMP as the reference signal. The transition time points corresponding to the groups are respectively set and partially or completely occurring at different times, thereby reducing the peak current and the IR drop. The transition time point of the output signal VOUT is delayed by the time delay td. Specifically, ΔVIP and td are respectively represented by equations (13) and (14).

Δ⁢VIP=CGSP⁢Δ⁢VAZCGSP+CINP(13)td=(CGSN⁢Δ⁢VAZ+CgsN⁢Δ⁢AZ⁢1⁢DCGSN+CgsN+CINN-CGSP⁢Δ⁢VAZCGSP+CINP)⁢dtdVVRMP(14)

CGSPrepresents the parasitic gate-source capacitance of the auto-zero switch3306.

However, when the input capacitor3304inFIG.27is omitted, the input voltage VIP recovers its original voltage level to cancel ΔVIP, as illustrated inFIG.26.

FIG.29is a diagram schematically illustrating a comparator circuit coupled to an inverter and a counter according to a fifteenth embodiment of the invention.FIG.30is a diagram schematically illustrating the waveforms of the auto-zero control signal, the first control signals, the second control signals, the pixel signal, the reference signal, the input voltages of the amplifier, the comparison signal, and the output signal corresponding toFIG.29. Referring toFIG.29andFIG.30, the fifteenth embodiment of the comparator circuit330is introduced as follows. Compared to the fourteenth embodiment of the comparator circuit330, the fifteenth embodiment of the comparator circuit330further includes at least one control switch3308named as a second control switch.

In addition, the fifteenth embodiment of the comparator circuit330exemplifies a plurality of control switches3307and a plurality of control switches3308. Each control switch3307has a first end, a second end, and a control end. The first end and the second end of each control switch3307are respectively coupled to the first input node and the first output node of the amplifier3300. The control ends of the control switches3307are respectively coupled to respective control signals AZ1D[1]˜AZ1D[N] named as respective first control signals. The number of the control switches3307is greater than or equal to the number of the groups of the comparator circuit330. If the number of the groups of the comparator circuit330is equal to two, the number of the control switches3307is greater than or equal to two, and two of the control switches3307are respectively selected to receive the respective control signals AZ1D[1] and AZ1D[2] and the remains of the control switches3307are electrically floating. Each control switch3308has a first end, a second end, and a control end. The first end and the second end of each control switch3308are respectively coupled to the second input node and the second output node of the amplifier3300. The control ends of the control switches3308are respectively coupled to respective control signals AZ1DB[1]˜AZ1DB[N] named as respective second control signals. The number of the control switches3308is greater than or equal to the number of the groups of the comparator circuit330. If the number of the groups of the comparator circuit330is equal to two, the number of the control switches3308is greater than or equal to two, and two of the control switches3308are respectively selected to receive the respective control signals AZ1DB[1] and AZ1DB[2] and the remains of the control switches3308are electrically floating. The other technical features ofFIG.35have been described previously so it will not be reiterated.

As illustrated inFIG.30, AZ1D[N:1] includes the respective control signal AZ1D[1]˜AZ1D[N]. AZ1DB[N:1] includes the respective control signal AZ1DB[1]˜AZ1DB[N]. The input voltages VIN and VIP respectively follow the voltage levels of the pixel signal VPIX and the ramp signal VRMP. Each of the respective control signals AZ1D[1]˜AZ1D[N] is identical to the auto-zero control signal VAZ. The voltage level of each of the respective control signals AZ1DB[1]˜AZ1DB[N] is maintained at a logic low level. The voltage difference between the logic low level and the logic high level of each of the respective control signals AZ1DB[1]˜AZ1DB[N] is defined as ΔAZ1DB[1], . . . , ΔAZ1DB[N−1], or ΔAZ1DB[N]. ΔAZ1DB[N:1] includes ΔAZ1DB[1]˜ΔAZ1DB[N]. When the voltage level of the auto-zero control signal VAZ rises from a logic low level to a logic high level, the auto-zero switch3302and the auto-zero switch3306are turned on to couple the first input node of the amplifier3300to the first output node of the amplifier3300and couple the second input node of the amplifier3300to the second output node of the amplifier3300, such that the input voltage VIN is equal to the input voltage VIP. Simultaneously, the voltage level of each of the respective control signals AZ1D[1]˜AZ1D[N] rises from a logic low level to a logic high level. When the voltage level of the auto-zero control signal VAZ descends from the logic high level to the logic low level, the auto-zero switch3302and the auto-zero switch3306are turned off to decouple the first input node of the amplifier3300to the first output node of the amplifier3300and decouple the second input node of the amplifier3300to the second output node of the amplifier3300. Simultaneously, the voltage level of each of the respective control signals AZ1D[1]˜AZ1D[N] descends from the logic high level to the logic low level. For example, the voltage levels of the respective control signals AZ1D[1]˜AZ1D[N] are respectively decreased by ΔAZ1D[1]˜ΔAZ1D[N]. ΔAZ1D[N:1] includes ΔAZ1D[1]˜ΔAZ1D[N]. The voltage level of the auto-zero control signal VAZ is decreased by ΔVAZ. When the voltage levels of the respective control signals AZ1D[1]˜AZ1D[N] are respectively decreased by ΔAZ1D[1]˜ΔAZ1D[N] and the voltage level of the auto-zero control signal VAZ is decreased by ΔVAZ, the voltage levels of the input voltages VIN and VIP are respectively decreased by ΔVIN and ΔVIP, thereby changing the transition time points of voltages of the comparison signal VCMP and the output signal VOUT. Assume that the auto-zero switch3302, the auto-zero switch3306, the control switch3307, and the control switch3308are implemented with NMOSFETs. The source and the drain of each of the auto-zero switch3302and the control switch3307are respectively coupled to the first input node and the first output node of the amplifier3300. The gate of each of the auto-zero switch3302and the control switch3307receives one of the respective control signals AZ1D[1]˜AZ1D[N], or the auto-zero control signal VAZ. The source and the drain of each of the auto-zero switch3306and the control switch3308are respectively coupled to the second input node and the second output node of the amplifier3300. The gate of each of the auto-zero switch3306and the control switch3308receives one of the respective control signals AZ1DB[1]˜AZ1DB[N] or the auto-zero control signal VAZ.

In other words, ΔVIN is caused by ΔAZ1D[N:1], ΔVAZ, and the parasitic gate-source capacitances of the auto-zero switch3302and the control switch3307. ΔVIP is caused by ΔVAZ and the parasitic gate-source capacitance of the auto-zero switch3306. ΔVIP will be caused by ΔAZ1DB[N:1] and the gate-source capacitances of the control switches3308if the phases of the respective control signals AZ1DB[N:1] are adjusted to be the same to the phases of the respective control signals AZ1D[N:1]. The comparator circuits330are divided into a plurality of groups. Based on the foregoing mechanism, the voltage levels of the respective control signals AZ1D[N:1] and AZ1DB[N:1] transition to change the transition time points of the comparison signal VCMP and the output signal VOUT. The transition time points of the comparison signal VCMP and the output signal VOUT depend on the input capacitors3301and3304, the parasitic gate-source capacitances, the respective control signals AZ1D[N:1] and AZ1DB[N:1], the auto-zero control signal VAZ, and the ramp signal VRMP as the reference signal. The transition time points corresponding to the groups are respectively set and partially or completely occurring at different times, thereby reducing the peak current and the IR drop. The dashed waveforms of the comparison signal VCMP and the output signal VOUT are generated when the control switches3307and the control switches3308do not receive the respective control signals AZ1D[N:1] and AZ1DB[N:1]. The transition time point of the output signal VOUT is delayed by the time delay td. Specifically, ΔVIN, ΔVIP and td are respectively represented by equations (15), (16), and (17).

Δ⁢VIN=CGSN⁢Δ⁢VAZ+∑i=1NCgsN[i]⁢Δ⁢AZ⁢1⁢D[i]CGSN+∑i=1NCgsN[i]+CINN(15)Δ⁢VIP=CGSP⁢Δ⁢VAZ+∑i=1NCgsP[i]⁢Δ⁢AZ⁢1⁢DB[i]CGSP+∑i=1NCgsP[i]+CINP(16)td=(CGSN⁢Δ⁢VAZ+∑i=1NCgsN[i]⁢Δ⁢AZ⁢1⁢D[i]CGSN+∑i=1NCgsN[i]+CINN-CGSP⁢Δ⁢VAZ+∑i=1NCgsP[i]⁢Δ⁢AZ⁢1⁢DB[i]CGSP+∑i=1NCgsP[i]+CINP)⁢dtdVVRMP(17)

CgsN[i] represents the parasitic gate-source capacitance of the i-th control switch3307. CgsP[i] represents the parasitic gate-source capacitance of the i-th control switch3308.

FIG.31is a diagram schematically illustrating a comparator circuit coupled to an inverter and a counter according to a sixteenth embodiment of the invention.FIG.32is a diagram schematically illustrating the waveforms of the auto-zero control signal, the first control signal, the pixel signal, the reference signal, the input voltages of the amplifier, the comparison signal, and the output signal corresponding toFIG.31. Referring toFIG.31andFIG.32, the sixteenth embodiment of the comparator circuit330is introduced as follows. The comparator circuit330includes an amplifier3300, an input capacitor3304named as a first input capacitor, an auto-zero switch3306named as a first auto-zero switch, and at least one control switch3308named as a first control switch. For clarity and convenience, the sixteenth embodiment exemplifies one control switch3308. The control switch3308may be, but not limited to, a metal-oxide-semiconductor field-effect transistor (MOSFET) or a suitable transistor. The amplifier3300has a first input node, a second input node, a first output node, and a second output node. In the sixteenth embodiment, the first input node, the second input node, the first output node, and the second output node may be respectively a positive input node, a negative input node, a negative output node, and a positive output node. The input capacitor3304has a first end and a second end. The first end of the input capacitor3304is coupled to the first input node of the amplifier3300. The auto-zero switch3306has a first end, a second end, and a control end. The first end of the auto-zero switch3306is coupled to the first input node of the amplifier3300. The second end of the auto-zero switch3306is coupled to the first output node of the amplifier3300. The control switch3308has a first end, a second end, and a control end. The first end of the control switch3308is coupled to the first input node of the amplifier3300. The second end of the control switch3308is coupled to the first output node of the amplifier3300.

In order to effectively read the pixel signals VPIX, the image readout device may further include a plurality of inverters331and a plurality of counters332. The inverters331are respectively coupled to the second output nodes of the amplifiers3300of the comparator circuits330. The counters332are respectively coupled to the inverters331.

The operation of the sixteenth embodiment of the comparator circuit330is introduced as follows. The second input node and the first input node of the amplifier3300respectively receive a pixel signal VPIX from the image sensor array and a reference signal. The reference signal may be, but not limited to, a ramp signal VRMP. The amplifier3300compares the pixel signal VPIX to the ramp signal VRMP to generate a comparison signal VCMP from the second output node. The second end of the input capacitor3304is coupled to the pixel signal VPIX or the reference signal. In the sixteenth embodiment, the second end of the input capacitor3304is coupled to the ramp signal VRMP. The control end of the auto-zero switch3306is coupled to an auto-zero control signal VAZ. The auto-zero control signal VAZ is configured to couple or decouple the first input node of the amplifier3300to the first output node of the amplifier3300. The control end of the control switch3308is coupled to a respective control signal AZ1DB named as a respective first control signal. In addition, the input voltage of the negative input node of the amplifier3300is represented with VIN. The input voltage of the positive input node of the amplifier3300is represented with VIP. The inverters331convert the comparison signals VCMP generated from the comparator circuits330into a plurality of output signals VOUT which transition between a high level and a low level based on a predetermined voltage level. Each counter332counts one of the output signals VOUT to generate a digital counting value corresponding to the pixel signal VPIX.

As illustrated inFIG.32, the input voltages VIN and VIP respectively follow the voltage levels of the pixel signal VPIX and the ramp signal VRMP. The voltage level of the respective control signal AZ1DB is maintained at a logic low level. The voltage difference between the logic low level and the logic high level of the respective control signal AZ1DB is defined as ΔAZ1DB. When the voltage level of the auto-zero control signal VAZ rises from a logic low level to a logic high level, the auto-zero switch3306is turned on to couple the first input node of the amplifier3300to the first output node of the amplifier3300, such that the input voltage VIN is equal to the input voltage VIP. When the voltage level of the auto-zero control signal VAZ descends from the logic high level to the logic low level, the auto-zero switch3306is turned off to decouple the first input node of the amplifier3300to the first output node of the amplifier3300. For example, the auto-zero control signal VAZ is decreased by ΔVAZ. When the voltage level of the auto-zero control signal VAZ is decreased by ΔVAZ, the voltage level of the input voltage VIP is decreased by ΔVIP, thereby changing the transition time points of voltages of the comparison signal VCMP and the output signal VOUT. Assume that the auto-zero switch3306and the control switch3308are implemented with NMOSFETs. The source and the drain of the NMOSFET are respectively coupled to the first input node and the first output node of the amplifier3300. The gate of the NMOSFET receives the respective control signal AZ1DB or the auto-zero control signal VAZ. In other words, ΔVIP is caused by ΔVAZ and the parasitic gate-source capacitances of the auto-zero switch3306. ΔVIP will be caused by ΔAZ1DB and the gate-source capacitance of the control switch3308if the phase of the respective control signal AZ1DB is adjusted to be the same to the phase of the auto-zero control signal VAZ. The comparator circuits330are divided into a plurality of groups. Based on the foregoing mechanism, the voltage level transition of the respective control signal AZ1DB causes the transition time points of the comparison signal VCMP and the output signal VOUT change. The transition time points of the comparison signal VCMP and the output signal VOUT depend on the input capacitor3304, the parasitic gate-source capacitances, the respective control signal AZ1DB, the auto-zero control signal VAZ, and the ramp signal VRMP as the reference signal. The transition time points corresponding to the groups are respectively set and partially or completely occurring at different times, thereby reducing the peak current and the IR drop. The transition time point of the output signal VOUT is delayed by the time delay td. Specifically, ΔVIP and td are respectively represented by equations (18) and (19).

Δ⁢VIP=CGSP⁢Δ⁢VAZ+CgsP⁢Δ⁢AZ⁢1⁢DBCGSP+CgsP+CINP(18)td=-CGSP⁢Δ⁢VAZ+CgsP⁢Δ⁢AZ⁢1⁢DBCGSP+CgsP+CINP⁢dtdVVRMP(19)

CGSPrepresents the parasitic gate-source capacitance of the auto-zero switch3306. CgsPrepresents the parasitic gate-source capacitance of the control switch3308.

FIG.33is a diagram schematically illustrating a comparator circuit coupled to an inverter and a counter according to a seventeenth embodiment of the invention.FIG.34is a diagram schematically illustrating the waveforms of the auto-zero control signal, the first control signal, the pixel signal, the reference signal, the input voltages of the amplifier, the comparison signal, and the output signal corresponding toFIG.33. Referring toFIG.33andFIG.34, the seventeenth embodiment of the comparator circuit330is introduced as follows. Compared to the sixteenth embodiment of the comparator circuit330, the seventeenth embodiment of the comparator circuit330further includes an input capacitor3301named as a second input capacitor and an auto-zero switch3302named as a second auto-zero switch. The input capacitor3301has a first end and a second end. The first end of the input capacitor3301is coupled to the second input node of the amplifier3300. The second end of the input capacitor3301is coupled to the reference signal or the pixel signal VPIX. In the seventeenth embodiment, the second end of the input capacitor3301is coupled to the pixel signal VPIX. The auto-zero switch3302has a first end, a second end, and a control end. The first end of the auto-zero switch3302is coupled to the second input node of the amplifier3300. The second end of the auto-zero switch3302is coupled to the second output node of the amplifier3300. The control end of the auto-zero switch3302is coupled to the auto-zero control signal VAZ which is configured to couple or decouple the second input node of the amplifier3300and the second output node of the amplifier3300.

As illustrated inFIG.34, the input voltages VIN and VIP respectively follow the voltage levels of the pixel signal VPIX and the ramp signal VRMP. The voltage level of the respective control signal AZ1DB is maintained at a logic low level. The voltage difference between the logic low level and the logic high level of the respective control signal AZ1DB is defined as ΔAZ1DB. When the voltage level of the auto-zero control signal VAZ rises from a logic low level to a logic high level, the auto-zero switch3302and the auto-zero switch3306are turned on to couple the first input node of the amplifier3300to the first output node of the amplifier3300and couple the second input node of the amplifier3300to the second output node of the amplifier3300, such that the input voltage VIN is equal to the input voltage VIP. When the voltage level of the auto-zero control signal VAZ descends from the logic high level to the logic low level, the auto-zero switch3302and the auto-zero switch3306are turned off to decouple the first input node of the amplifier3300to the first output node of the amplifier3300and decouple the second input node of the amplifier3300to the second output node of the amplifier3300. For example, the voltage level of the auto-zero control signal VAZ is decreased by ΔVAZ. When the voltage level of the auto-zero control signal VAZ is decreased by ΔVAZ, the voltage levels of the input voltages VIN and VIP are respectively decreased by ΔVIN and ΔVIP, thereby changing the transition time points of voltages of the comparison signal VCMP and the output signal VOUT. Assume that the auto-zero switch3302, the auto-zero switch3306, and the control switch3308are implemented with NMOSFETs. The source and the drain of each of the auto-zero switch3306and the control switch3308are respectively coupled to the first input node and the first output node of the amplifier3300. The gate of each of the auto-zero switch3306and the control switch3308receives the respective control signal AZ1DB and the auto-zero control signal VAZ. The source and the drain of the auto-zero switch3302are respectively coupled to the second input node and the second output node of the amplifier3300. The gate of the auto-zero switch3302receives the auto-zero control signal VAZ. In other words, ΔVIP is caused by ΔVAZ and the parasitic gate-source capacitances of the auto-zero switch3306. ΔVIN is caused by ΔVAZ and the parasitic gate-source capacitance of the auto-zero switch3302. ΔVIP will be caused by ΔAZ1DB and the gate-source capacitance of the control switch3308if the phase of the respective control signals AZ1DB is adjusted to be the same to the phase of the auto-zero control signal VAZ. The comparator circuits330are divided into a plurality of groups. Based on the foregoing mechanism, the voltage level transition of the respective control signal AZ1DB causes the transition time points of the comparison signal VCMP and the output signal VOUT change. The transition time points of the comparison signal VCMP and the output signal VOUT depend on the input capacitors3301and3304, the parasitic gate-source capacitances, the respective control signal AZ1DB, the auto-zero control signal VAZ, and the ramp signal VRMP as the reference signal. The transition time points corresponding to the groups are respectively set and partially or completely occurring at different times, thereby reducing the peak current and the IR drop. The dashed waveforms of the comparison signal VCMP and the output signal VOUT are generated when the control switch3308does not receive the respective control signal AZ1DB. The transition time point of the output signal VOUT is delayed by the time delay td. Specifically, ΔVIN and td are respectively represented by equations (20) and (21).

Δ⁢VIN=CGSN⁢Δ⁢VAZCGSN+CINN(20)td=(CGSN⁢Δ⁢VAZCGSN+CINN-CGSP⁢Δ⁢VAZ+CgsP⁢Δ⁢AZ⁢1⁢DBCGSP+CgsP+CINP)⁢dtdVVRMP(21)

CGSNrepresents the parasitic gate-source capacitance of the auto-zero switch3302.

However, when the input capacitor3301inFIG.33is omitted, the input voltage VIN recovers its original voltage level to cancel ΔVIN, as illustrated inFIG.32.

FIG.35is a diagram schematically illustrating a comparator circuit coupled to an inverter and a counter according to an eighteenth embodiment of the invention.FIG.36is a diagram schematically illustrating the waveforms of the auto-zero control signal, the pixel signal, the reference signals, the input voltages of the amplifier, the comparison signals, and the output signals corresponding toFIG.35. Referring toFIG.35andFIG.36, the eighteenth embodiment of the comparator circuit330is introduced as follows. The comparator circuit330includes an amplifier3300, an input capacitor3304named as a first input capacitor, an input capacitor3301named as a second input capacitor, an auto-zero switch3302named as a first auto-zero switch, and an auto-zero switch3306named as a second auto-zero switch. The amplifier3300has a first input node, a second input node, a first output node, and a second output node. In the eighteenth embodiment, the first input node may be a negative input node, the second input node may be a positive input node, and the first output node and the second output node may be respectively a positive output node and a negative output node. The input capacitor3301has a first end and a second end. The first end of the input capacitor3301is coupled to the first input node of the amplifier3300, and the second end of the input capacitor3301is coupled to the pixel signal VPIX. The input capacitor3304has a first end and a second end. The first end of the input capacitor3304is coupled to the second input node of the amplifier3300, and the second end of the input capacitor3304is coupled to a ramp signal (as a reference signal) VRMP[i], wherein i=1 to N, for N groups of comparator circuit330. The auto-zero switch3302has a first end, a second end, and a control end. The first end of the auto-zero switch3302is coupled to the first input node of the amplifier3300. The second end of the auto-zero switch3302is coupled to the first output node of the amplifier3300. The auto-zero switch3306has a first end, a second end, and a control end. The first end of the auto-zero switch3306is coupled to the second input node of the amplifier3300. The second end of the auto-zero switch3306is coupled to the second output node of the amplifier3300.

In order to effectively read the pixel signals VPIX, the image readout device may further include a plurality of inverters331and a plurality of counters332. The inverters331are respectively coupled to the first output nodes of the amplifiers3300of the comparator circuits330. The counters332are respectively coupled to the inverters331.

The operation of the eighteenth embodiment of the comparator circuit330is introduced as follows. The first input node and the second input node of the amplifier3300respectively receive a pixel signal VPIX from the image sensor array and a reference signal. The reference signal may be, but not limited to, a ramp signal VRMP[i]. i is a positive integer. The amplifier3300compares the pixel signal VPIX to the ramp signal VRMP[i] to generate a comparison signal VCMP[i] from the first output node. The second end of the input capacitor3304is coupled to the ramp signal VRMP[i]. The control end of the auto-zero switch3302is coupled to an auto-zero control signal VAZ. The control end of the auto-zero switch3306is coupled to the auto-zero control signal VAZ. The auto-zero control signal VAZ is configured to couple or decouple the first input node of the amplifier3300to the first output node of the amplifier3300and to couple or decouple the second input node of the amplifier3300to the second output node of the amplifier3300. In addition, the input voltage of the negative input node of the amplifier3300is represented with VIN. The input voltage of the positive input node of the amplifier3300is represented with VIP[i]. The inverters331respectively convert the comparison signals VCMP[1]˜VCMP[N] generated from the comparator circuits330into a plurality of output signals VOUT[1]˜VOUT[N] which transition between a high level and a low level based on a predetermined voltage level. Each counter332counts one of the output signals VOUT[1]˜ VOUT[N] to generate a digital counting value corresponding to the pixel signal VPIX.

As illustrated inFIG.36, VRMP[N:1] includes VRMP[1]˜VRMP[N]. One of the ramp signals VRMP[N:1], represented with a solid waveform, has the highest voltage level. One of the ramp signals VRMP[N:1], represented with a dashed waveform, has the lowest voltage level. At the same time point, the voltage difference between the ramp signal VRMP[i] and the ramp signal with the lowest voltage level is defined as ΔVRMP[i]. ΔVRMP[N:1] includes ΔVRMP[1]˜ΔVRMP[N]. VIP[N:1] includes VIP[1]˜VIP[N]. One of the ramp signals VIP[N:1], represented with a solid waveform, has the highest voltage level. One of the ramp signals VIP[N:1], represented with a dashed waveform, has the lowest voltage level. VCMP[N:1] includes VCMP[1]˜VCMP[N]. The waveforms of the comparison signals VCMP[N:1] vary between the solid line and the dashed line. VOUT[N:1] includes VOUT[1]˜VOUT[N]. The waveforms of the output signals VOUT[N:1] vary between the solid line and the dashed line. The transition time points of the output signals VOUT[1]˜VOUT[N] are respectively represented with td[1]˜td[N]. td[N:1] includes td[1]˜td[N].

The input voltages VIN and VIP[i] respectively follow the voltage levels of the pixel signal VPIX and the ramp signal VRMP[i]. When the voltage level of the auto-zero control signal VAZ rises from a logic low level to a logic high level, the auto-zero switch3302is turned on to couple the first input node of the amplifier3300to the first output node of the amplifier3300and the auto-zero switch3306is turned on to couple the second input node of the amplifier3300to the second output node of the amplifier3300, such that the input voltage VIN is equal to the input voltage VIP[i] and the voltage offset between the input voltages VIN and VIP[i] is cancelled. When the voltage level of the auto-zero control signal VAZ descends from the logic high level to the logic low level, the auto-zero switch3302is turned off to decouple the first input node of the amplifier3300to the first output node of the amplifier3300and the auto-zero switch3306is turned off to decouple the second input node of the amplifier3300to the second output node of the amplifier3300. The voltage levels of all or parts of the ramp signals VRMP[1]˜VRMP[N] are adjusted to be different, thereby changing the transition time points of voltages of the comparison signal VCMP[i] and the output signal VOUT[i]. The comparator circuits330are divided into a plurality of groups. The transition time points of the comparison signals VCMP[N:1] respectively corresponding to the groups differ from each other when the respective reference signals are respectively coupled to the groups have different level. The transition time points of the comparison signal VCMP[i] and the output signal VOUT[i] depend on ΔVRMP[i] and VRMP[i]. The transition time points corresponding to the groups are respectively set and partially or completely occurring at different times, thereby reducing the peak current and the IR drop. The transition time point of the output signal VOUT[i] is delayed by the time delay td[i]. Specifically, td[i] is represented by equation (22).

td[i]=Δ⁢VRMP[i]⁢dtdVVRMP[i](22)

VVRMPrepresents the voltage of the ramp signal VRMP[i].

According to the embodiments provided above, the image readout device employs the control capacitor and the control switch or controls the levels of the reference signals to control the transition time points of output signals not to occur at the same time, thereby reducing the peak current and the IR drop.

The embodiments described above are only to exemplify the invention and not to limit the scope of the invention. Therefore, any equivalent modification or variation according to the shapes, structures, features, or spirit disclosed by the invention is to be also included within the scope of the invention.