Patent ID: 12254237

DESCRIPTION OF THE EMBODIMENTS

In the output driver according to the disclosure, a bias current flowing in a differential signaling circuit, which generates a pair of differential signals obtained by making a binary input signal into differential signal, is controlled based on a differential voltage representing the difference between a center voltage of the pair of differential signals and a reference voltage. Further, a pre-emphasis processing is executed in response to changes in a level of an input signal, generating a current based on the differential voltage as a pre-emphasis current and adding it to the bias current.

Thus, according to the disclosure, a current value of the bias current flowing in the differential signaling circuit is increased by the pre-emphasis processing, such that a high slew rate of the output driver can be achieved.

Embodiment 1

FIG.1is a block diagram showing a schematic configuration of a display device100including an output driver according to the disclosure.

As shown inFIG.1, the display device100includes a display control unit11, a scan driver12, a data driver13, and a display panel20that includes a liquid crystal panel or the like.

The display panel20is formed with m (m is a natural number greater than or equal to 2) scan lines GL1to GLm each extending in the horizontal direction of a two-dimensional screen, and n (n is a natural number greater than or equal to 2) data lines DL1to DLn each extending in the vertical direction of the two-dimensional screen. Further, display cells serving as pixels are formed in each intersection region of the scan line and the data line.

The display control unit11receives a video signal VS, generates a horizontal scan signal HS indicating horizontal scan timing for each horizontal synchronization signal included in the video signal VS, and supplies it to the scan driver12.

Further, the display control unit11generates, for each pixel, a series of pixel data PD representing the luminance level of that pixel based on the video signal VS. Then, the display control unit11converts a video digital data signal including the series of pixel data PD, a clock signal CLK having a unit cycle 1UI of a serial signal for one pixel data PD, and a synchronization signal into a group compliant with the LVDS (Low Voltage (Differential Signaling) standard, for example.

That is, the display control unit11generates a differential data signal DFD, obtained by converting the series of pixel data PD and the synchronization signal into the form of a serial differential signal. Further, the display control unit11generates a differential clock signal DFC by making the clock signal CLK into differential signal. Then, the display control unit11transmits the differential clock signal DFC and the differential data signal DFD to the data driver13.

The scan driver12generates a horizontal scan pulse having a predetermined peak voltage in synchronization with the horizontal scan signal HS, and sequentially and selectively applies it to each of the scan lines GL1to GLm of the display panel20.

The data driver13receives the differential data signal DFD and the differential clock signal DFC. Based on the differential data signal DFD and the differential clock signal DFC, the data driver13generates analog driving signals G1to Gn respectively corresponding to the data lines DL1to DLn of the display panel20, and supplies them to the data lines DL1to DLn of the display panel20.

FIG.2is a circuit diagram showing the configuration of an output driver200_1included in the display control unit11, which generates the differential data signal DFD and the differential clock signal DFC and supplies each to the data driver13.

The output driver200_1includes a clock driver part200a, a data driver part200b, and pre-emphasis control unit30.

Moreover, the clock driver part200areceives the clock signal CLK and an inverted clock signal CLKb obtained by logically inverting the clock signal CLK. Thereby, the clock driver part200agenerates the differential clock signal DFC including a positive differential clock signal vp_ck and a negative differential clock signal vn_ck, obtained by making the clock signal CLK into differential signal. The data driver part200breceives a digital data signal DAT representing the series of pixel data PD and the synchronization signal, and an inverted digital data signal DATb obtained by logically inverting the digital data signal DAT. Thereby, the data driver part200bgenerates the differential data signal DFD including a positive differential data signal vp_da and a negative differential data signal vn_da, obtained by making the digital data signal DAT and the inverted digital data signal DATb into differential signals.

As shown inFIG.2, the clock driver part200aincludes an operational amplifier31, a differential signaling circuit33, pre-emphasis circuits34and35, and terminating resistors R1and R2.

The operational amplifier31receives a common mode voltage vi_ck detected by the differential signaling circuit33at its non-inverting input terminal, and receives a predetermined reference voltage Vref1at its inverting input terminal. The operational amplifier31generates a differential voltage em_ck representing a difference between the common mode voltage vi_ck and the reference voltage Vref1, and outputs it to the differential signaling circuit33and the pre-emphasis circuit34.

The differential signaling circuit33includes a P-channel MOS transistor MP1, an N-channel MOS transistor MN1, switch elements S2to S5, and resistors r1and r2.

The transistor MP1receives a power supply voltage VDD at its own source, and receives the differential voltage em_ck at its own gate. A drain of the transistor MP1is connected to one end of each of the switch elements S2and S3. Thereby, the transistor MP1generates a current having a current value based on the differential voltage em_ck as a bias current, and sends to one end of each of the switch elements S2and S3.

The other end of a switch element S2is connected to one end of the resistor r1and one end of a switch element S4via a node n1. The other end of the resistor r1is connected to one end of the resistor r2and the non-inverting input terminal of the operational amplifier31.

The switch element S2receives the clock signal CLK, and becomes OFF state while the clock signal CLK is at logic level 0, for example. On the other hand, while the clock signal CLK is at logic level 1, the switch element S2becomes ON state, electrically connecting the drain of the transistor MIP and the node n1.

The other end of a switch element S3is connected to the other end of the resistor r2and one end of a switch element S5via a node n2. The switch element S3receives the inverted clock signal CLKb, and becomes OFF state while the inverted clock signal CLKb is at logic level 0, for example. On the other hand, while the inverted clock signal CLKb is at logic level 1, the switch element S3becomes ON state, electrically connecting the drain of the transistor MP1and the node n2.

The other end of the switch element S4is connected to a drain of the transistor MN1. The switch element S4receives the inverted clock signal CLKb, and becomes OFF state while the inverted clock signal CLKb is at logic level 0, for example. On the other hand, while the inverted clock signal CLKb is at logic level 1, the switch element S4becomes ON state, electrically connecting the node n1and the drain of the transistor MN1.

The other end of the switch element S5is connected to the drain of the transistor MN1. The switch element S5receives the clock signal CLK, and becomes OFF state while the clock signal CLK is at logic level 0, for example. On the other hand, while the clock signal CLK is at logic level 1, the switch element S5becomes ON state, electrically connecting the node n2and the drain of the transistor MN1.

Here, a voltage generated at a connection point between the resistors r1and r2is supplied to the non-inverting input terminal of the operational amplifier31as the common mode voltage vi_ck.

The terminating resistors R1and R2connected in series are connected between the node n1and the node n2. That is, one end of the terminating resistor R1is connected to the node n1, and one end of the terminating resistor R2is connected to the node n2. Further, the other ends of the terminating resistors R1and R2are connected to each other.

At this time, the voltage generated at the node n1is output as the positive differential clock signal vp_ck, and the voltage generated at the node n2is output as the negative differential clock signal vn_ck.

The transistor MN1receives a ground voltage VSS at its own source, and receives a bias voltage Vbs having a predetermined fixed voltage value at its own gate. Thereby, the transistor MN1allows a current to flow based on the bias voltage Vbs.

The pre-emphasis circuit34includes a P-channel MOS transistor MP2and a switch element S1. The transistor MP2receives the power supply voltage VDD at its own source, and receives the differential voltage em_ck at its own gate. A drain of the transistor MP2is connected to one end of the switch element S1. The other end of the switch element S1is connected to the drain of the transistor MP1. The switch element S1receives a pre-emphasis signal SW1from the pre-emphasis control unit30, and becomes OFF state while the pre-emphasis signal SW1is at logic level 0, for example. On the other hand, while the pre-emphasis signal SW1is at logic level 1 instructing execution of pre-emphasis, the switch element S1becomes ON state, connecting the drain of the transistor MP2and the drain of the transistor MP1.

With such a configuration, in response to the pre-emphasis signal SW1of logic level 1 instructing execution of pre-emphasis, the pre-emphasis circuit34generates a current having a current value based on the differential voltage em_ck as a pre-emphasis current. Then, the pre-emphasis circuit34adds the pre-emphasis current to the bias current sent out by the transistor MP of the differential signaling circuit33.

The pre-emphasis circuit35includes an N-channel MOS transistor MN2and a switch element S6. The transistor MN2receives the ground voltage VSS at its own source, and receives the bias voltage Vbs at its own gate. A drain of the transistor MN2is connected to one end of the switch element S6. The other end of the switch element S6is connected to the drain of the transistor MN1. The switch element S6receives a pre-emphasis signal SW4from the pre-emphasis control unit30, and becomes OFF state while the pre-emphasis signal SW4is at logic level 0, for example. On the other hand, while the pre-emphasis signal SW4is at logic level 1, the switch element S6becomes ON state, connecting the drain of the transistor MN2and the drain of the transistor MN1.

With such a configuration, in response to the pre-emphasis signal SW1of logic level 1 instructing execution of pre-emphasis, the pre-emphasis circuit35extracts a fixed pre-emphasis current based on the bias voltage Vbs from the drain of the transistor MN1of the differential signaling circuit33.

As shown inFIG.2, the data driver part200bincludes an operational amplifier41, a differential signaling circuit43, pre-emphasis circuits44and45, and terminating resistors R11and R12.

The operational amplifier41receives a common mode voltage vi_da detected by the differential signaling circuit43at its non-inverting input terminal, and receives the reference voltage Vref1at its inverting input terminal. The operational amplifier41generates a differential voltage em_da representing a difference between the common mode voltage vi_da and the reference voltage Vref1, and outputs it to the differential signaling circuit43and the pre-emphasis circuit44.

The differential signaling circuit43includes a P-channel MOS transistor MP3, an N-channel MOS transistor MN3, switch elements S12to S15, and resistors r11and r12.

The transistor MP3receives the power supply voltage VDD at its own source, and receives the differential voltage em_da at its own gate. A drain of the transistor MP3is connected to one end of each of the switch elements S12and S13. Thereby, the transistor MP3generates a current having a current value based on the differential voltage em_da as a bias current, and sends it to one end of each of the switch elements S12and S13.

The other end of the switch element S12is connected to one end of the resistor r11and one end of a switch element S14via a node n11. The other end of the resistor r11is connected to one end of the resistor r12and the non-inverting input terminal of the operational amplifier41.

The switch element S12receives the digital data signal DAT, and becomes OFF state while the digital data signal DAT is at logic level 0, for example. On the other hand, while the digital data signal DAT is at logic level 1, the switch element S12becomes ON state, electrically connecting the drain of the transistor MP3and the node n11.

The other end of a switch element S13is connected to the other end of the resistor r12and one end of a switch element S15via a node n12. The switch element S13receives the inverted digital data signal DATb, and becomes OFF state while the inverted digital data signal DATb is at logic level 0, for example. On the other hand, while the inverted digital data signal DATb is at logic level 1, the switch element S13becomes ON state, electrically connecting the drain of the transistor MP3and the node n12.

The other end of the switch element S14is connected to a drain of the transistor MN3. The switch element S14receives the inverted digital data signal DATb, and becomes OFF state while the inverted digital data signal DATb is at logic level 0, for example. On the other hand, while the inverted digital data signal DATb is at logic level 1, the switch element S14becomes ON state, electrically connecting the node n11and the drain of the transistor MN3.

The other end of the switch element S15is connected to the drain of the transistor MN3. The switch element S15receives the digital data signal DAT, and becomes OFF state while the digital data signal DAT is at logic level 0, for example. On the other hand, while the digital data signal DAT is at logic level 1, the switch element S15becomes ON state, electrically connecting the node n12and the drain of the transistor MN3.

Here, a voltage generated at a connection point between the resistors r11and r12is supplied to the non-inverting input terminal of the operational amplifier41as the common mode voltage vi_da.

The terminating resistors R11and R12connected in series are connected between the node n11and the node n12. That is, one end of the terminating resistor R11is connected to the node n11, and one end of the terminating resistor R12is connected to the node n12. Further, the other ends of the terminating resistors R11and R12are connected to each other.

At this time, the voltage generated at the node n11is output as the positive differential data signal vp_da, and the voltage generated at the node n12is output as the negative differential data signal vn_da.

The transistor MN3receives the ground voltage VSS at its own source, and receives the bias voltage Vbs at its own gate. Thereby, the transistor MN3allows a current to flow based on the bias voltage Vbs.

The pre-emphasis circuit44includes a P-channel MOS transistor MP4and a switch element S11. The transistor MP4receives the power supply voltage VDD at its own source, and receives the differential voltage em_da at its own gate. A drain of the transistor MP4is connected to one end of the switch element S11. The other end of the switch element S11is connected to the drain of the transistor MP3. The switch element S11receives the pre-emphasis signal SW4from the pre-emphasis control unit30, and becomes OFF state while the pre-emphasis signal SW4is at logic level 0, for example. On the other hand, while the pre-emphasis signal SW4is at logic level 1, the switch element S11becomes ON state, connecting the drain of the transistor MP3and the drain of the transistor MP4.

With such a configuration, in response to the pre-emphasis signal SW4of logic level 1 instructing execution of pre-emphasis, the pre-emphasis circuit44generates a current having a current value based on the differential voltage em_da as a pre-emphasis current. Then, the pre-emphasis circuit44adds the pre-emphasis current to the bias current sent out by the transistor MP3of the differential signaling circuit43.

The pre-emphasis circuit45includes an N-channel MOS transistor MN4and a switch element S16. The transistor MN4receives the ground voltage VSS at its own source, and receives the bias voltage Vbs at its own gate. A drain of the transistor MN4is connected to one end of the switch element S16. The other end of the switch element S16is connected to the drain of the transistor MN3. The switch element S16receives the pre-emphasis signal SW4from the pre-emphasis control unit30, and becomes OFF state while the pre-emphasis signal SW4is at logic level 0, for example. On the other hand, while the pre-emphasis signal SW4is at logic level 1, the switch element S16becomes ON state, connecting the drain of the transistor MN4and the drain of the transistor MN3.

With such a configuration, in response to the pre-emphasis signal SW4of logic level 1 instructing execution of pre-emphasis, the pre-emphasis circuit45extracts a fixed pre-emphasis current based on the bias voltage Vbs from the drain of the transistor MN3of the differential signaling circuit43.

For each unit cycle 1UI of the serial signal for one pixel data PD, the pre-emphasis control unit30generates the pre-emphasis signal SW4of logic level 1 within this unit cycle while the clock signal CLK changes from logic level 1 to logic level 0 or from logic level 0 to logic level 1. On the other hand, when the clock signal CLK remains at logic level 1 or 0 beyond the unit cycle 1UI, the pre-emphasis control unit30generates the pre-emphasis signal SW1of logic level 0 instructing stop of the re-emphasis.

Moreover, since the cycle of the clock signal CLK is originally fixed at the unit cycle 1UI, the pre-emphasis control unit30supplies the pre-emphasis signal SW1of logic level 1 instructing execution of pre-emphasis to the switch element S1of the pre-emphasis circuit34and the switch element S6of the pre-emphasis circuit35.

Moreover, the pre-emphasis control unit30generates the pre-emphasis signal SW4of logic level 1 instructing execution of pre-emphasis, or logic level 0 instructing stop of pre-emphasis based on the digital data signal DAT. That is, for each unit cycle 1UI, the pre-emphasis control unit30generates the pre-emphasis signal SW4of logic level 1 instructing execution of pre-emphasis within this unit cycle while the logic level of the digital data signal DAT changes. On the other hand, when the digital data signal DAT remains at logic level 1 or 0 beyond the unit cycle 1UI, the pre-emphasis control unit30generates the pre-emphasis signal SW4of logic level 0 instructing to stop pre-emphasis. Then, the pre-emphasis control unit30supplies the pre-emphasis signal SW4to the switch element S11of the pre-emphasis circuit44and the switch element S16of the pre-emphasis circuit45included in the data driver part200b.

The operation of the clock driver part200aand the data driver part200bincluded in the output driver200_1shown inFIG.2will be described below with reference to internal operating waveforms shown inFIG.3.

[Operation of the Clock Driver Part200a]

In the clock driver part200a, the differential signaling circuit33receives a clock signal CLK and an inverted clock signal CLKb which alternately alternate between logic levels 0 and 1 in the unit cycle 1UI, as shown inFIG.3. Thus, while the clock signal CLK is at logic level 1, the bias current sent from the transistor MP1based on the differential voltage em_ck as shown inFIG.3flows in a path including the switch element S2, the resistors r1and r2, the switch element S5, and the transistor MN1. On the other hand, while the clock signal CLK is at logic level 0, that is, while the inverted clock signal CLKb is at logic level 1, the bias current based on the differential voltage em_ck flows in a path including the switch element S3, the resistors r2and r1, the switch element S4, and the transistor MN1.

Thereby, as shown inFIG.3, the positive differential data signal vp_da corresponding to the clock signal CLK and the negative differential data signal vn_da corresponding to the inverted clock signal CLKb are output. Moreover, the center voltages of the positive differential data signal vp_da and the negative differential data signal vn_da are supplied to the operational amplifier31as the common mode voltage vi_ck shown inFIG.3. Thus, the operational amplifier31controls the bias current sent out from the transistor MP1by the differential voltage em_ck such that the common mode voltage vi_ck becomes equal to the reference voltage Vref1.

Here, in the clock driver part200a, as shown inFIG.3, the switch element S1of the pre-emphasis circuit34becomes ON state in response to the pre-emphasis signal SW1of logic level 1 instructing execution of pre-emphasis. Thereby, the transistor MP2of the pre-emphasis circuit34generates a pre-emphasis current based on the differential voltage em_ck shown inFIG.3, and adds it to the bias current sent out from the transistor MP1(pre-emphasis processing).

Thus, by the pre-emphasis processing of the pre-emphasis circuit34, the bias current flowing in the differential signaling circuit33increases, thus the slew rate of the clock driver part200abecomes higher. Further, the increase of the bias current makes it possible to follow the fluctuations of the common mode voltage vi_ck and quickly converge the voltage value of the common mode voltage vi_ck to the vicinity of the reference voltage Vref1.

[Operation of the Data Driver Part200b]

In the data driver part200b, the differential signaling circuit43receives the digital data signal DAT and the inverted digital data signal DAT of logic level 0 or logic level 1 corresponding to the content of the data, as shown inFIG.3, for example. Thus, while the digital data signal DAT is at logic level 1, a bias current sent from the transistor MP3based on the differential voltage em_da as shown inFIG.3flows in a path including the switch element S12, the resistors r11and r12, the switch element S15, and the transistor MN3. On the other hand, while the digital data signal DAT is at logic level 0, that is, while the inverted digital data signal DATb is at logic level 1, the bias current based on the differential voltage em_da flows in a path including the switch element S13, the resistors r12and r11, the switch element S14, and the transistor MN3.

Thereby, as shown inFIG.3, the positive differential data signal vp_da corresponding to the digital data signal DAT and the negative differential data signal vn_da corresponding to the inverted digital data signal DATb are output. Moreover, the center voltages of the positive differential data signal vp_da and the negative differential data signal vn_da are supplied to the operational amplifier41as the common mode voltage vi_da shown inFIG.3. Thus, the operational amplifier41controls the bias current sent out from the transistor MP3by the differential voltage em_da such that the common mode voltage vi_da becomes equal to the reference voltage Vref1.

Here, in the data driver part200b, as shown inFIG.3, the switch element S11of the pre-emphasis circuit44becomes ON state in response to the pre-emphasis signal SW4of logic level 1 instructing execution of pre-emphasis. Thereby, the transistor MP4of the pre-emphasis circuit44generates a pre-emphasis current based on the differential voltage em_da, and adds it to the bias current sent out from the transistor MP3(pre-emphasis processing).

Thus, by the pre-emphasis processing by the pre-emphasis circuit44, the bias current flowing through the differential signaling circuit43increases, thus the slew rate of the data driver part200bbecomes higher. Further, the increase of the bias current makes it possible to follow the fluctuations of the common mode voltage vi_da and quickly converge the voltage value of the common mode voltage vi_da to the vicinity of the reference voltage Vref1.

However, since the logic level of the digital data signal DAT changes randomly depending on the content of the data, the change cycle of the logic level is not constant.

Thereby, in the data driver part200b, the pre-emphasis processing is stopped when the change cycle of the logic level of the digital data signal DAT becomes longer than the unit cycle 1UI, as shown inFIG.3. Moreover, while the pre-emphasis processing is stopped, since the bias current is not increased by the pre-emphasis circuit44, the differential voltage em_da gradually decreases as shown inFIG.3.

Thus, when the output driver2001is required to further increase its speed, the operational amplifier41and the pre-emphasis circuit44cannot follow changes in the common mode voltage vi_da as shown inFIG.3. Thus, a problem arises in that fluctuations in the common mode voltage, which is the center voltage of the positive differential data signal vp_da and the negative differential data signal vn_da, cannot be suppressed.

Embodiment 2

FIG.4is a circuit diagram showing the configuration of an output driver200_2as a second embodiment of the disclosure.

Moreover, in the configuration of the output driver200_2shown inFIG.4, the other configurations are the same as that shown inFIG.1, except that operational amplifiers31aand31bare used instead of the operational amplifier31, and an operational amplifier41ais used instead of the operational amplifier41.

InFIG.4, the operational amplifier31aof the clock driver part200areceives the common mode voltage vi_ck detected by the differential signaling circuit33at the non-inverting input terminal, and receives the reference voltage Vref1at the inverting input terminal. The operational amplifier31agenerates a differential voltage representing the difference between the common mode voltage vi_ck and the reference voltage Vref1, and supplies it to the gate of the transistor MP1of the differential signaling circuit33.

The operational amplifier31breceives the common mode voltage vi_ck at the non-inverting input terminal, and receives the reference voltage Vref1at the inverting input terminal. The operational amplifier31bgenerates the differential voltage em_ck representing the difference between the common mode voltage vi_ck and the reference voltage Vref1. The operational amplifier31bsupplies the generated differential voltage em_ck to the gate of the transistor MP2of the pre-emphasis circuit34and the gate of the transistor MP4of the pre-emphasis circuit44of the data driver part200b.

The operational amplifier41aof the data driver part200breceives the common mode voltage vi_da detected by the differential signaling circuit43at the non-inverting input terminal, and receives the reference voltage Vref1at the inverting input terminal. The operational amplifier41agenerates the differential voltage em_da representing the difference between the common mode voltage vi_da and the reference voltage Vref1, and supplies it to the gate of the transistor MP3of the differential signaling circuit43.

That is, in the output driver200_2, each of the operational amplifiers31aand31bgenerates a differential voltage representing the difference between the reference voltage Vref1and the common mode voltage vi_ck. Here, the differential voltage generated by the operational amplifier31ais supplied only to the transistor MP1among the transistor MP1of the differential signaling circuit33and the transistor MP2of the pre-emphasis circuit34. Moreover, the differential voltage representing the difference between the reference voltage Vref1generated by the operational amplifier41aand the common mode voltage vi_da on the data driver part200bside is supplied only to the transistor MP3among the transistor MP3of the differential signaling circuit43and the transistor MP4of the pre-emphasis circuit44. Then, the differential voltage generated by the operational amplifier31bis supplied to the gate of the transistor MP2in the pre-emphasis circuit34of the clock driver part200a, and to the gate of the transistor MP4in the pre-emphasis circuit44of the data driver part200b.

Moreover, the configuration of the differential signaling circuits33and43, the pre-emphasis circuits34,35,44and45, and the terminating resistors R1, R2, R11and R12included in the output driver2002shown inFIG.4are the same as those shown inFIG.1, respectively, and their operating waveforms are also similar to those shown inFIG.3.

However, in the output driver200_2, the pre-emphasis circuit34on the clock driver part200aside and the pre-emphasis circuit44on the data driver part200bside are driven by the differential voltage em_ck generated based on the common mode voltage vi_ck on the clock driver part200aside. At this time, the differential voltage em_ck is generated based on the clock signal CLK whose change cycle of the logic level is fixed at the unit cycle 1UI, the amount of variation is smaller than that of the differential voltage em_da generated based on the digital data signal DAT whose change cycle of the logic level is not constant.

Thus, when the pre-emphasis circuit44executes a pre-emphasis processing, the pre-emphasis current for increasing the bias current sent out by the transistor MP4can be kept constant. Thereby, the center voltage of the positive differential data signal vp_da and the negative differential data signal vn_da, namely the common mode voltage, can be made constant.

Embodiment 3

FIG.5is a block diagram showing the configuration of an output driver200_3as a third embodiment of the disclosure.

The output driver200_3includes one single clock driver part200aandnsystems of data driver parts200b_1to200b_n.

Moreover, the clock driver part200ashown inFIG.5is the same as the clock driver part200ashown in the output driver200_2shown inFIG.4. The clock driver part200asupplies the differential voltage em_ck output from the operational amplifier31bshown inFIG.4to each of the data driver parts200b_1to200b_n.

Each of the data driver parts200b_1to200b_nhas the same configuration as the data driver part200bshown inFIG.4, except that a buffer amplifier50is newly added. The buffer amplifier50is a voltage follower with its own output terminal connected to an inverting input terminal, it receives the differential voltage em_ck at its own non-inverting input terminal, and supplies a signal obtained by amplifying the differential voltage em_ck to the gate of the transistor MP4of the pre-emphasis circuit44.

In this manner, in the output driver2003, the pre-emphasis circuit44of each of the multiple data driver parts200bis controlled by the differential voltage em_ck generated by the single clock driver part200a.

At this time, in the output driver2003, the data driver parts200b_1to200b_nreceives the differential voltage em_ck sent out by the clock driver part200arespectively via the buffer amplifier50provided therein. In other words, the buffer amplifier50separates the clock driver part200afrom each of the data driver parts200b_1to200b_n. Thereby, it is possible to prevent the fluctuation of the feedback result caused by the operation of the data driver parts200b_1to200b_n, that is, the fluctuation of the differential voltage representing the difference between the common mode voltage vi_da and the reference voltage Vref1, from propagating to the clock driver part200aside.

Moreover, in the embodiment shown inFIGS.2,4, and5, the pre-emphasis current on an N-channel MOS side (MN2, MN4) is fixed, and the pre-emphasis current on a P-channel MOS side (MP2, MP4) is adjusted by feedback. However, the pre-emphasis current on the P-channel MOS side may be fixed, and the pre-emphasis current on the N-channel MOS side may be adjusted by feedback.

Further, in the embodiments shown inFIGS.2,4, and5, an example of a circuit that outputs the clock signal CLK and the digital data signal DAT respectively from the clock driver part200aand the data driver part200b, which are separate drivers, is described. However, by using the clock driver (200a) as a built-in replica circuit, the disclosure is also applicable to an embedded clock method in which a clock signal is embedded in a digital data signal.

Moreover, in this embodiment, an example of a circuit applied when the cycle (1UI) of the clock signal CLK is equal to or less than the cycle of the digital data signal is described, but the disclosure is also applicable to standards such as LVDS where the cycle of the clock signal is longer than the cycle of the digital data signal.

Further, in this embodiment, the clock signal (CLK) and the digital data signal (DAT) are used to be converted into differential signals, but the content of the input signal to be made into differential signal is not limited as long as it is a binary signal of logic level 0 or 1.

Moreover, althoughFIG.2orFIG.4shows the specific circuit configuration of the differential signaling circuits33and43, the circuit configuration of the differential signaling circuit is not limited as long as it generates differential signals that are inverted in phase with each other on a pair of nodes (n1and n2, or n11and n12) by receiving a bias current.

In short, as the output driver (200_1or200_2) according to the disclosure, it is sufficient to include the following differential signaling circuit, differential voltage circuit, and pre-emphasis circuit.

The differential signaling circuit (33or43) includes a first transistor (MP1, MP3) that generates a bias current, first and second nodes (n1, n2or n11, n12), and a resistance circuit (r1, r2or r11, r12) connected between the first and second nodes. Here, the differential signaling circuit (33or43) outputs voltages generated at the first and second nodes as a pair of differential signals (vp_ck, vn_ck or vp_da, vn_da) by supplying the bias current to one of the first and second nodes based on the level (0, 1) of the input signal (CLK or DAT).

The differential voltage circuit (31,31a,31b,41, or41a) supplies a differential voltage (em_ck or em_da) representing a difference between the center voltage (vi_ck or vi_da) of the voltages between the first and second nodes and a predetermined reference voltage (Vref1) to the gate of the first transistor (MP1or MP3).

In response to changes in the level (0, 1) of the input signal (DAT or CLK), the pre-emphasis circuit (34or44) performs a pre-emphasis processing, generating a current based on the differential voltage and adding it as a pre-emphasis current to the bias current.

Further, an output driver (200_2) according to the disclosure includes a clock driver part that outputs a clock signal (CLK) as a differential signal, and a data driver part that outputs a data signal (DAT) as a differential signal.

The clock driver part (200a) includes the following first differential signaling circuit, first and second operational amplifiers, and a first pre-emphasis circuit.

The first differential signaling circuit (33) includes the first transistor (MP1) that generates a first bias current, the first and second nodes (n1, n2), the first resistor (r1) with one end connected to the first node (n1), and the second resistor (r2) with one end connected to the second node (n2) and the other end connected to the other end of the first resistor. The first differential signaling circuit (33) outputs the voltages respectively generated at the first and second nodes as a pair of differential clock signals (vp_ck, vn_ck) by supplying the first bias current to one of the first and second nodes based on the level (0, 1) of the clock signal (CLK).

The first operational amplifier (31a) takes the voltage generated at the other end of the first resistor as a first center voltage (vi_ck) indicating the center voltage of the pair of differential clock signals, and supplies a differential voltage representing a difference between this first center voltage and the predetermined reference voltage (Vref1) to the gate of the first transistor (MP1).

The second operational amplifier (31b) generates a first differential voltage (em_ck) representing a difference between the first center voltage (vi_ck) and the reference voltage (Vref1).

The first pre-emphasis circuit (34) executes a pre-emphasis processing in response to changes in the level (0, 1) of the clock signal, generating a current (pre-emphasis current) based on the first differential voltage (em_ck) and adding it to the first added to the bias current.

The data driver part (200b) includes the following second differential signaling circuit, a third operational amplifier, and a second pre-emphasis circuit.

The second differential signaling circuit (43) includes the second transistor (MP3) that generates a second bias current, the third and fourth nodes (n3, n4), the third resistor (r11) with one end connected to the third node (n3), and the fourth resistor (r12) with one end connected to the fourth node (n4) and the other end connected to the other end of the third resistor. The second differential signaling circuit (43) outputs voltages respectively generated at the third and fourth nodes as a pair of differential data signals (vp_da, vn_da) by supplying the second bias current to one of the third and fourth nodes based on the level (0, 1) of the data signal (DAT).

The third operational amplifier (41a) takes the voltage generated at the other end of the third resistor (r11) as a second center voltage (vi_da) indicating the center voltage of the pair of differential data signals, and supplies a differential voltage representing a difference between this second center voltage and the reference voltage (Vref1) to the gate of the second transistor (MP3).

The second pre-emphasis circuit (44) executes a pre-emphasis processing in response to changes in the level (0, 1) of the data signal (DAT), generating a current (pre-emphasis current) based on the first differential voltage (em_ck) generated by the second operational amplifier (31b) of the clock driver part (200a) and adding it to the second bias current.