Patent ID: 12213311

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Embodiments of the invention encompass methods used in forming a memory array, for example an array of NAND or other memory cells that may have at least some peripheral control circuitry under the array (e.g., CMOS-under-array). Embodiments of the invention encompass so-called “gate-last” or “replacement-gate” processing, so-called “gate-first” processing, and other processing whether existing or future-developed independent of when transistor gates are formed. First example method embodiments are described with reference toFIGS.1-40which may be considered as a “gate-last” or “replacement-gate” process, and starting withFIGS.1and2.

FIGS.1and2show a construction10having an array or array area12in which elevationally-extending strings of transistors and/or memory cells will be formed. Construction10comprises a base substrate11having any one or more of conductive/conductor/conducting, semiconductive/semiconductor/semiconducting, or insulative/insulator/insulating (i.e., electrically herein) materials, Various materials have been formed elevationally over base substrate11. Materials may be aside, elevationally inward, or elevationally outward of theFIGS.1and2-depicted materials. For example, other partially or wholly fabricated components of integrated circuitry may be provided somewhere above, about, or within base substrate11. Control and/or other peripheral circuitry for operating components within an array (e.g., array12) of elevationally-extending strings of memory cells may also be fabricated and may or may not be wholly or partially within an array or sub-array. Further, multiple sub-arrays may also be fabricated and operated independently, in tandem, or otherwise relative one another. In this document, a “sub-array” may also be considered as an array.

In some embodiments and as shown, a conductor tier16comprising conductor material17having an uppermost surface19has been formed above substrate11. In one embodiment, conductor material17comprises upper conductor material43(e.g., n-type or p-type conductively-doped polysilicon) directly above (e.g., directly against) lower conductor material44(e.g., WSix) of different composition from upper conductor material43. Conductor tier16may comprise part of control circuitry (e.g., peripheral-under-array circuitry and/or a common source line or plate) used to control read and write access to the transistors and/or memory cells that will be formed within array12.

A lower portion18L of a stack18* has been formed above substrate11and conductor tier16when present (an * being used as a suffix to be inclusive of all such same-numerically-designated components that may or may not have other suffixes). Stack18* will comprise vertically-alternating conductive tiers22* and insulative tiers20*, with material of conductive tiers22* being of different composition from material of second tiers20*. Conductive tiers22* (alternately referred to as first tiers) may not comprise conducting material and insulative tiers20* (alternately referred to as second tiers) may not comprise insulative material or be insulative at this point in processing in conjunction with the hereby initially-described example method embodiment which is “gate-last” or “replacement-gate”. In one embodiment and as shown, lower portion18L comprises a lowest20zof second tiers20* directly above (e.g., directly against) conductor material17material. A lowest tier22zof first tiers22* is directly above (e.g., directly against) lowest second tier20zand comprises first sacrificial material21(e.g., doped or undoped polysilicon, or silicon nitride). A first layer45of second-tier material24(e.g., silicon dioxide) is directly above (e.g., directly against) lowest first tier22z. A second layer46(e.g., material21) of different composition from first layer45is directly above (e.g., directly against) first layer45. Lowest first tier22zis thicker than second layer46. A third layer60(e.g., material24) of different composition from second layer46is directly above (e.g., directly against) second layer46.

Stack18* comprises laterally-spaced memory-block regions58that will comprise laterally-spaced memory blocks58in a finished circuitry construction. In this document, “block” is generic to include “sub-block”. Memory-block regions58and resultant memory blocks58(not yet shown) may be considered as being longitudinally elongated and oriented, for example along a direction55. Memory-block regions58may not be discernable at this point of processing.

Referring toFIGS.3and4, horizontally-elongated troughs79have been formed in lower portion18L and extend through third layer60, second layer46, first layer45, lowest first tier22z, lowest second tier20z, and into conductor material17. Troughs79extend into conductor material17to a depth D that is less than a thickness T of lowest first tier22z. In one embodiment and as shown, lowest first tier22zis thicker than upper conductor material43and horizontally-elongated troughs79are formed through upper conductor material43to extend to lower conductor material44(e.g., into conductor material44as shown).

Referring toFIGS.5-8, conductor material17(e.g., upper conductor material43), first sacrificial material21of lowest first tier22z, and second layer46have been laterally recessed selectively relative to lowest second tier20z, first layer45, and third layer60to form laterally-opposed recesses78longitudinally-along individual troughs79in conductor material17, in first sacrificial material21of lowest first tier22z, and in second layer46. In one embodiment, such act or acts of laterally recessing comprises isotropic etching of conductor material17, first sacrificial material21of lowest first tier22z, and second layer46. In one such embodiment where conductor material17(e.g., upper conductor material43), first sacrificial material21of lowest first tier22z, and second layer46comprise the same composition relative one another, such isotropic etching thereof may occur simultaneously. For example, where material21(and43, in one embodiment) comprise polysilicon and other exposed materials comprise silicon dioxide and WSix, an example isotropic etching chemistry to produce the construction ofFIGS.5-8from that ofFIGS.3and4is tetramethyl ammonium hydroxide (TMAH). In one embodiment, only two of conductor material17, first sacrificial material21of lowest first tier22z, and second layer46are of the same composition relative one another, and the isotropic etching thereof may not occur simultaneously. In one embodiment, none of conductor material17, first sacrificial material21of lowest first tier22z, and second layer46are of the same composition relative one another, and the isotropic etching thereof may not occur simultaneously. Regardless and in one embodiment and as shown, such laterally recessing has also laterally recessed upper conductor material43selectively relative to lower conductor material44to form laterally-opposed recesses78in conductor material17to be in upper conductor material43.

Referring toFIG.9, insulating material61(e.g., silicon dioxide) has been deposited along sidewalls of troughs79and into recesses78. Insulating material61fills recesses78in conductor material17and recesses78in second layer46. Insulating material61less-than-fills recesses78in lowest first tier22z.

Referring toFIGS.10-13, insulating material61has been removed (e.g., by isotropic etching thereof) from recesses78in lowest first tier22zwhile leaving insulating material61in recesses78in conductor material17and in recesses78in second layer46.

Referring toFIGS.14and15, horizontally-elongated lines13have been formed in troughs79and are individually between immediately-laterally-adjacent memory-block regions58. Lines13individually comprise laterally-opposing projections66longitudinally there-along that are in laterally-opposed recesses78in lowest first tier22z. Lines13comprise second sacrificial material15of different composition from first sacrificial material21. In one embodiment, second sacrificial material15comprises metal material, for example elemental tungsten above a thin layer of TiN. An optional insulative liner47(e.g., silicon dioxide) has been formed in troughs79and recesses78prior to forming material15of lines13, and in one such embodiment at least a portion of insulative liner is in a finished circuitry construction. In one embodiment, second sacrificial material15of individual lines13may extend laterally into respective immediately-laterally-adjacent memory-block regions58, for example as shown occurs by example lateral projections66. In one embodiment, lines13individually comprise an uppermost surface31that is above lowest first tier22z. In one embodiment, lines13individually comprise a bottom surface59that is not directly against conductor material17(e.g., due to presence of insulative liner47). Lines13may taper laterally-inward (not shown) moving deeper into lower stack portion18L.

Referring toFIGS.16-19, vertically-alternating first tiers22* and second tiers20* of an upper portion18U of stack18* have been formed above lower portion18L and lines13. Example conductive tiers22* comprise first material26(e.g., silicon nitride if gate-last processing) which may be wholly or partially sacrificial. Example insulative tiers20* comprise second material24that is of different composition from that of first material26and which may be wholly or partially sacrificial. Example thickness for each of tiers20* and22* is 20 to 60 nanometers. Only a small number of tiers20* and22* is shown, with more likely stack18U (and thereby stack18*) comprising dozens, a hundred or more, etc. of tiers20* and22*. Further, other circuitry that may or may not be part of peripheral and/or control circuitry may be between conductor tier16and stack18*. For example, multiple vertically-alternating tiers of conductive material and insulative material of such circuitry may be below a lowest of the conductive tiers22* and/or above an uppermost of the conductive tiers22*. For example, one or more select gate tiers (not shown) may be between conductor tier16and the lowest conductive tier22* and one or more select gate tiers may be above an uppermost of conductive tiers22*. Alternately or additionally, at least one of the depicted uppermost and lowest conductive tiers22* may be a select gate tier.

Channel openings25have been formed (e.g., by etching) through insulative tiers20* and conductive tiers22* in upper portion18U to lowest first tier22zin lower portion18U and to conductor tier16as shown. By way of example and for brevity only, channel openings25are shown as being arranged in groups or columns of staggered rows of four and five channel openings25per row. Channel openings25may taper radially-inward (not shown) moving deeper in stack18*. In some embodiments, channel openings25may go into conductor material17of conductor tier16as shown or may stop there-atop (not shown). Alternately, as an example, channel openings25may stop atop or within lowest insulative tier20zor lowest first tier22z. A reason for extending channel openings25ultimately at least to or into conductor material17of conductor tier16is to provide an anchoring effect to material that is within channel openings25. Etch-stop material (not shown) may be within or atop conductor material17of conductor tier16to facilitate stopping of the etching of channel openings25relative to conductor tier16when such is desired. Such etch-stop material may be sacrificial or non-sacrificial.

Transistor channel material36has been formed in individual channel openings25elevationally along the first tiers and the second tiers, thus comprising individual channel-material strings53that extend through first tiers22* and second tiers20* in upper portion18U to lowest first tier22zin lower portion18L. Channel material36in channel-material strings53will be directly electrically coupled with conductor material17in conductor tier16. Individual memory cells of the example memory array being formed may comprise a gate region (e.g., a control-gate region) and a memory structure laterally between the gate region and the channel material. In one such embodiment, the memory structure is formed to comprise a charge-blocking region, storage material (e.g., charge-storage material), and an insulative charge-passage material. The storage material (e.g., floating gate material such as doped or undoped silicon or charge-trapping material such as silicon nitride, metal dots, etc.) of the individual memory cells is elevationally along individual of the charge-blocking regions. The insulative charge-passage material (e.g., a band gap-engineered structure having nitrogen-containing material [e.g., silicon nitride] sandwiched between two insulator oxides [e.g., silicon dioxide]) is laterally between the channel material and the storage material.FIGS.16-19show one embodiment wherein charge-blocking material30, storage material32, and charge-passage material34have been formed in individual channel openings25devotionally along insulative tiers20* and conductive tiers22*. Transistor materials30,32, and34(e.g., memory-cell materials) may be formed by, for example, deposition of respective thin layers thereof over stack18* and within individual openings25followed by planarizing such back at least to a top surface of stack18*.

Channel material36may be considered as having a lowest surface71thereof. Channel-material strings53in one embodiment have memory-cell materials (e.g.,30,32, and34) there-along and with second-tier material (e.g.,24) being horizontally-between immediately-adjacent channel-material strings53. Materials30,32,34, and36are collectively shown as and only designated as material37inFIGS.16and17due to scale. Example channel materials36include appropriately-doped crystalline semiconductor material, such as one or more silicon, germanium, and so-called III/V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). Example thickness for each of materials30,32,34, and36is 25 to 100 Angstroms. Punch etching may be conducted to remove materials30,32, and34from the bases of channel openings25(not shown) to expose conductor tier16such that channel material36is directly against conductor material17of conductor tier16. Such punch etching may occur separately with respect to each of materials30,32, and34(as shown) or may occur with respect to only some (not shown). Alternately, and by way of example only, no punch etching may be conducted and channel material36may be directly electrically coupled to conductor material17of conductor tier16only by a separate conductive interconnect (not yet shown). Channel openings25are shown as comprising a radially-central solid dielectric material38(e.g., spin-on-dielectric, silicon dioxide, and/or silicon nitride). Alternately, and by way of example only, the radially-central portion within channel openings25may include void space(s) (not shown) and/or be devoid of solid material (not shown).

Prior to forming channel openings25, sacrificial pillars (not shown) may have been formed in lower stack portion18L and would be horizontally-located (i.e., in x, y coordinates) where individual channel openings25will be formed. Channel openings25would then be formed to such sacrificial pillars and which would then be removed to thereby effectively extend channel openings25into lowest first tier22zbefore forming materials37and38.

Referring toFIGS.20and21, horizontally-elongated trenches40have been formed into stack18* (e.g., by anisotropic etching) and are individually between immediately-laterally-adjacent memory-block regions58and extend to line13there-between. In one embodiment, trenches40extend vertically into second sacrificial material15of lines13.FIG.22shows optional additional vertical etching (e.g., isotropically; see below for an example chemistry) of second sacrificial material15.

Referring toFIG.23, and in one embodiment, lining material35(e.g., doped or undraped polysilicon or silicon dioxide) has been formed to cover sidewalls and bases of trenches40and thereafter has been removed from covering the trench bases (e.g., by maskless anisotropic spacer-like etching) to re-expose second sacrificial material15.

Referring toFIGS.24and25, second sacrificial material15(not shown) of lines13(not shown) and projections66(not shown) has been removed (e.g., by selective isotropic etching) through trenches40. Portions of optional liner47that are not masked by lining material35have also been removed (e.g., using HF when silicon dioxide). In one embodiment, first sacrificial material21in lowest first tier22zhas been exposed. The artisan is capable of selecting a suitable isotropic etching chemistry that will etch second sacrificial material15selectively relative to other exposed materials. As an example, a W material15can be isotropically etched selectively relative to SiO2and Si3N4using a mixture of ammonia and hydrogen peroxide or a mixture of sulfuric acid and hydrogen peroxide.

Referring toFIGS.26-28, exposed first sacrificial material21in lowest first tier22z(not shown in22z) has been isotropically etched therefrom through trenches40, for example selectively relative to other exposed materials. The artisan is capable of selecting one or more suitable etching chemistries (e.g., using liquid or vapor H3PO4as a primary etchant where material21is silicon nitride and exposed other materials comprise one or more oxides or polysilicon or using TMAH where material21is polysilicon).

In one embodiment, a sidewall of the channel material of the channel-material strings in the lowest first tier is exposed.FIGS.29and30show example such subsequent processing wherein, in one embodiment, material30(e.g., silicon dioxide), material32(e.g., silicon nitride), and material34(e.g., silicon dioxide or a combination of silicon dioxide and silicon nitride) have been etched in each of tiers20zand20xto expose a sidewall41of channel material36of channel-material strings53in lowest first tier22z. Any of materials30,32, and34in tier20zmay be considered as being sacrificial material therein. As an example, consider an embodiment where materials21,36, and43are polysilicon, materials24and47are silicon dioxide, and memory-cell materials30,32, and34individually are one or more of silicon dioxide and silicon nitride layers. In such example, the depicted construction can result by using modified or different chemistries for sequentially etching silicon dioxide and silicon nitride selectively relative to the other. As examples, a solution of 100:1 (by volume) water to HF will etch silicon dioxide selectively relative to silicon nitride, whereas a solution of 1000:1 (by volume) water to HF will etch silicon nitride selectively relative to silicon dioxide. Accordingly, and in such example, such etching chemistries can be used in an alternating manner where it is desired to achieve the example construction shown byFIGS.29and30. The artisan is capable of selecting other chemistries for etching other different materials where a construction as shown inFIGS.29and30is desired.

Referring toFIGS.31and32, and in one embodiment, conductive/conducting material42has been deposited into void-space in lowest first tier22zleft as a result of removing first sacrificial material21. In one such embodiment, conductive material42is directly against exposed sidewall41of the channel material36of channel-material strings53in lowest first tier22zand in one embodiment is directly against an uppermost surface19of conductor material17(e.g., upper conductor material43) of conductor tier16. Such is but one example whereby conductive material42has been deposited to directly electrically couple together channel material36of individual channel-material strings53and conductor material17of conductor tier16(e.g., through channel-material sidewall41). Example conductive materials42are conductively-doped semiconductor material (e.g., conductively-doped polysilicon) and metal material.

Referring toFIGS.33and34, conductive material42has been removed from trenches40, for example by timed isotropic etching. Such may result in removal of lining material35as shown or such may be separately removed. Alternately, lining material35may have been removed earlier (not shown). A reason for removing lining material35is to provide access to material26in first tiers22for removal thereof in a replacement gate process. The etching of conductive material42may result in some etching of conductor material17when exposed (not shown). Example etching chemistries where material42is conductively-doped polysilicon, material24is silicon dioxide, material26is silicon dioxide is HBr (anisotropic) and TMAH (isotropic). An optional selective oxidation may be conducted (not shown) to form an oxide layer (not shown) atop conductor material17at bases of trenches40.

Referring toFIGS.35-40, material26(not shown) of conductive tiers22* has been removed, for example by being isotropically etched away through trenches40ideally selectively relative to the other exposed materials (e.g., using liquid or vapor H3PO4as a primary etchant where material26is silicon nitride and other materials comprise one or more oxides or polysilicon). Material26(not shown) in conductive tiers22* in the example embodiment is sacrificial and has been replaced with conducting material48, and which has thereafter been removed from trenches40, thus forming individual conductive lines29(e.g., wordlines) and elevationally-extending strings49of individual transistors and/or memory cells56.

A thin insulative liner (e.g., Al2O3and not shown) may be formed before forming conducting material48. Approximate locations of transistors and/or memory cells56are indicated with a bracket inFIG.40and some with dashed outlines inFIGS.35,37,39, with transistors and/or memory cells56being essentially ring-like or annular in the depicted example. Alternately, transistors and/or memory cells56may not be completely encircling relative to individual channel openings25such that each channel opening25may have two or more elevationally-extending strings49(e.g., multiple transistors and/or memory cells about individual channel openings in individual conductive tiers with perhaps multiple wordlines per channel opening in individual conductive tiers, and not shown). Conducting material48may be considered as having terminal ends50(FIG.40) corresponding to control-gate regions52of individual transistors and/or memory cells56. Control-gate regions52in the depicted embodiment comprise individual portions of individual conductive lines29. Materials30,32, and34may be considered as a memory structure65that is laterally between control-gate region52and channel material36. In one embodiment and as shown with respect to the example “gate-last” processing, conducting material48of conductive tiers22* is formed after forming channel openings25and/or trenches40. Alternately, the conducting material of the conductive tiers may be formed before forming channel openings25and/or trenches40(not shown), for example with respect to “gate-first” processing.

A charge-blocking region (e.g., charge-blocking material30) is between storage material32and individual control-gate regions52. A charge block may have the following functions in a memory cell: In a program mode, the charge block may prevent charge carriers from passing out of the storage material (e.g., floating-gate material, charge-trapping material, etc.) toward the control gate, and in an erase mode the charge block may prevent charge carriers from flowing into the storage material from the control gate. Accordingly, a charge block may function to block charge migration between the control-gate region and the storage material of individual memory cells. An example charge-blocking region as shown comprises insulator material30. By way of further examples, a charge-blocking region may comprise a laterally (e.g., radially) outer portion of the storage material (e.g., material32) where such storage material is insulative (e.g., in the absence of any different-composition material between an insulative storage material32and conducting material48). Regardless, as an additional example, an interface of a storage material and conductive material of a control gate may be sufficient to function as a charge-blocking region in the absence of any separate-composition-insulator material30. Further, an interface of conducting material48with material30(when present) in combination with insulator material30may together function as a charge-blocking region, and as alternately or additionally may a laterally-outer region of an insulative storage material (e.g., a silicon nitride material32). An example material30is one or more of silicon hafnium oxide and silicon dioxide.

In one embodiment and as shown, lowest surface71of channel material36of channel-material strings53is never directly against any of conductor material17of conductor tier16.

Intervening material57has been formed in trenches40and void-spaces left as a result of the removing of second sacrificial material15of lines13, and thereby laterally-between and longitudinally-along immediately-laterally-adjacent memory blocks58. Intervening material57may provide lateral electrical isolation (insulation) between immediately-laterally-adjacent memory blocks. Such may include one or more of insulative, semiconductive, and conducting materials and, regardless, may facilitate conductive tiers22from shorting relative one another in a finished circuitry construction. Example insulative materials are one or more of SiO2, Si3N4, Al2O3, and undoped polysilicon, Intervening material57may include through array vias (not shown). Some material in trenches40formed prior to forming that which is designated as intervening material57may remain and thereby comprise part of the intervening material57.

Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used in the embodiments shown and described with reference to the above embodiments.

FIG.4shows an embodiment where horizontally-elongated troughs79are formed through upper conductor material43to extend into conductor material44.FIG.41shows an example alternate embodiment construction10awherein horizontally-elongated troughs79aare formed to extend only partially into upper conductor material43. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “a” or with different numerals. Analogous processing to that shown and described above with respect toFIGS.5-40may occur to result in one or more analogous finished constructions such as shown byFIGS.35-40. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

In some embodiments, a method used in forming a memory array (e.g.,12) comprising strings (e.g.,49) of memory cells (e.g.,56) comprises forming a conductor tier (e.g.,16) comprising conductor material (e.g.,17) on a substrate (e.g.,11). A lower portion (e.g.,18L) of a stack (e.g.,18*) that will comprise vertically-alternating first tiers (e.g.,22*) and second tiers (e.g.,20*) is formed above the conductor tier. The stack comprises laterally-spaced memory-block regions (e.g.,58). Material of the first tiers is of different composition from material of the second tiers. A lowest of the first tiers (e.g.,22z) comprises first sacrificial material (e.g.,21). Horizontally-elongated lines (e.g.,13) are formed in the lower portion and are individually between immediately-laterally-adjacent of the memory-block regions. The lines comprise second sacrificial material (e.g.,15) of different composition from the first sacrificial material. The lines individually comprise laterally-opposing projections (e.g.,66) longitudinally there-along in the lowest first tier. Vertically-alternating first tiers and second tiers of an upper portion (e.g.,18U) of the stack are formed above the lower portion and the lines. Channel-material strings (e.g.,13) are formed that extend through the first tiers and the second tiers in the upper portion to the lowest first tier in the lower portion, Horizontally-elongated trenches (e.g.,40) are formed into the stack that are individually between the immediately-laterally-adjacent memory-block regions and extend to the line there-between. The second sacrificial material of the lines and projections is removed through the trenches. Intervening material (e.g.,57) is formed in the trenches and void-spaces left as a result of the removing of the second sacrificial material of the lines. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

In some embodiments, a method used in forming a memory array (e.g.,12) comprising strings (e.g.,49) of memory cells (e.g.,56) comprises forming a lower portion (e.g.,18L) of a stack (e.g.,18*) that will comprise vertically-alternating first tiers (e.g.,22*) and second tiers (e.g.,20*) on a substrate (e.g.,11). The stack comprises laterally-spaced memory-block regions (e.g.,58). Material of the first tiers is of different composition from material of the second tiers. Horizontally-elongated lines (e.g.,13) are formed in the lower portion and are individually between immediately-laterally-adjacent of the memory-block regions. The lines comprise sacrificial material (e.g.,15), The lines individually comprising laterally-opposing projections (e.g.,66) longitudinally there-along in a lowest of the first tiers (e.g.,22z). Vertically-alternating first tiers and second tiers of an upper portion (e.g.,18U) of the stack are formed above the lower portion and the lines. Channel-material strings (e.g.,53) are formed and extend through the first tiers and the second tiers in the upper portion to the lower portion. Horizontally-elongated trenches (e.g.,40) are formed into the stack and are individually between the immediately-laterally-adjacent memory-block regions and extend to the line there-between. The sacrificial material of the lines and projections is removed through the trenches. Intervening material (e.g.,57) is formed in the trenches and void-spaces left as a result of the removing of the sacrificial material of the lines. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

The above processing(s) or construction(s) may be considered as being relative to an array of components formed as or within a single stack or single deck of such components above or as part of an underlying base substrate (albeit, the single stack/deck may have multiple tiers). Control and/or other peripheral circuitry for operating or accessing such components within an array may also be formed anywhere as part of the finished construction, and in some embodiments may be under the array (e.g., CMOS under-array). Regardless, one or more additional such stack(s)/deck(s) may be provided or fabricated above and/or below that shown in the figures or described above. Further, the array(s) of components may be the same or different relative one another in different stacks/decks and different stacks/decks may be of the same thickness or of different thicknesses relative one another. Intervening structure may be provided between immediately-vertically-adjacent stacks/decks (e.g., additional circuitry and/or dielectric layers). Also, different stacks/decks may be electrically coupled relative one another. The multiple stacks/decks may be fabricated separately and sequentially (e.g., one atop another), or two or more stacks/decks may be fabricated at essentially the same time.

The assemblies and structures discussed above may be used in integrated circuits/circuitry and may be incorporated into electronic systems, Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

In this document unless otherwise indicated, “elevational”, “higher”, “upper”, “lower”, “top”, “atop”, “bottom”, “above”, “below”, “under”, “beneath”, “up”, and “down” are generally with reference to the vertical direction. “Horizontal” refers to a general direction (i.e., within 10 degrees) along a primary substrate surface and may be relative to which the substrate is processed during fabrication, and vertical is a direction generally orthogonal thereto. Reference to “exactly horizontal” is the direction along the primary substrate surface (i.e., no degrees there-from) and may be relative to which the substrate is processed during fabrication. Further, “vertical” and “horizontal” as used herein are generally perpendicular directions relative one another and independent of orientation of the substrate in three-dimensional space. Additionally, “elevationally-extending” and “extend(ing) elevationally” refer to a direction that is angled away by at least 45° from exactly horizontal. Further, “extend(ing) elevationally”, “elevationally-extending”, “extend(ing) horizontally”, “horizontally-extending” and the like with respect to a field effect transistor are with reference to orientation of the transistor's channel length along which current flows in operation between the source/drain regions. For bipolar junction transistors, “extend(ing) elevationally” “elevationally-extending”, “extend(ing) horizontally”, “horizontally-extending” and the like, are with reference to orientation of the base length along which current flows in operation between the emitter and collector. In some embodiments, any component, feature, and/or region that extends elevationally extends vertically or within 10° of vertical.

Further, “directly above”, “directly below”, and “directly under” require at least some lateral overlap (i.e., horizontally) of two stated regions/materials/components relative one another. Also, use of “above” not preceded by “directly” only requires that some portion of the stated region/material/component that is above the other be elevationally outward of the other (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components). Analogously, use of “below” and “under” not preceded by “directly” only requires that some portion of the stated region/material/component that is below/under the other be elevationally inward of the other (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components).

Any of the materials, regions, and structures described herein may be homogenous or non-homogenous, and regardless may be continuous or discontinuous over any material which such overlie. Where one or more example composition(s) is/are provided for any material, that material may comprise, consist essentially of, or consist of such one or more composition(s). Further, unless otherwise stated, each material may be formed using any suitable existing or future-developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implanting being examples.

Additionally, “thickness” by itself (no preceding directional adjective) is defined as the mean straight-line distance through a given material or region perpendicularly from a closest surface of an immediately-adjacent material of different composition or of an immediately-adjacent region. Additionally, the various materials or regions described herein may be of substantially constant thickness or of variable thicknesses. If of variable thickness, thickness refers to average thickness unless otherwise indicated, and such material or region will have some minimum thickness and some maximum thickness due to the thickness being variable. As used herein, “different composition” only requires those portions of two stated materials or regions that may be directly against one another to be chemically and/or physically different, for example if such materials or regions are not homogenous. If the two stated materials or regions are not directly against one another, “different composition” only requires that those portions of the two stated materials or regions that are closest to one another be chemically and/or physically different if such materials or regions are not homogenous. In this document, a material, region, or structure is “directly against” another when there is at least some physical touching contact of the stated materials, regions, or structures relative one another. In contrast, “over”, “on”, “adjacent”, “along”, and “against” not preceded by “directly” encompass “directly against” as well as construction where intervening material(s), region(s), or structure(s) result(s) in no physical touching contact of the stated materials, regions, or structures relative one another.

Herein, regions-materials-components are “electrically coupled” relative one another if in normal operation electric current is capable of continuously flowing from one to the other and does so predominately by movement of subatomic positive and/or negative charges when such are sufficiently generated. Another electronic component may be between and electrically coupled to the regions-materials-components. In contrast, when regions-materials-components are referred to as being “directly electrically coupled”, no intervening electronic component (e.g., no diode, transistor, resistor, transducer, switch, fuse, etc.) is between the directly electrically coupled regions-materials-components.

Any use of “row” and “column” in this document is for convenience in distinguishing one series or orientation of features from another series or orientation of features and along which components have been or may be formed. “Row” and “column” are used synonymously with respect to any series of regions, components, and/or features independent of function. Regardless, the rows may be straight and/or curved and/or parallel and/or not parallel relative one another, as may be the columns. Further, the rows and columns may intersect relative one another at 90° or at one or more other angles (i.e., other than the straight angle).

The composition of any of the conductive/conductor/conducting materials herein may be metal material and/or conductively-doped semiconductive/semiconductor/semiconducting material. “Metal material” is any one or combination of an elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compound(s).

Herein, any use of “selective” as to etch, etching, removing, removal, depositing, forming, and/or formation is such an act of one stated material relative to another stated material(s) so acted upon at a rate of at least 2:1 by volume. Further, any use of selectively depositing, selectively growing, or selectively forming is depositing, growing, or forming one material relative to another stated material or materials at a rate of at least 2:1 by volume for at least the first 75 Angstroms of depositing, growing, or forming.

Unless otherwise indicated, use of “or” herein encompasses either and both.

Conclusion

In some embodiments, a method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A lower portion of a stack that will comprise vertically-alternating first tiers and second tiers is formed above the conductor tier. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. A lowest of the first tiers comprises first sacrificial material. Horizontally-elongated lines are formed in the lower portion and that are individually between immediately-laterally-adjacent of the memory-block regions. The lines comprise second sacrificial material of different composition from the first sacrificial material. The lines individually comprise laterally-opposing projections longitudinally there-along in the lowest first tier. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion and the lines, and channel-material strings are formed that extend through the first tiers and the second tiers in the upper portion to the lowest first tier in the lower portion. Horizontally-elongated trenches are formed into the stack that are individually between the immediately-laterally-adjacent memory-block regions and extend to the line there-between. The second sacrificial material of the lines and projections is removed through the trenches. Intervening material is formed in the trenches and void-spaces left as a result of the removing of the second sacrificial material of the lines.

In some embodiments, a method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers on a substrate. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. Horizontally-elongated lines are formed in the lower portion that are individually between immediately-laterally-adjacent of the memory-block regions. The lines comprise sacrificial material. The lines individually comprise laterally-opposing projections longitudinally there-along in a lowest of the first tiers. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion and the lines, and channel-material strings are formed that extend through the first tiers and the second tiers in the upper portion to the lower portion. Horizontally-elongated trenches are formed into the stack that are individually between the immediately-laterally-adjacent memory-block regions and extend to the line there-between. The sacrificial material of the lines and projections is removed through the trenches. Intervening material is formed in the trenches and void-spaces left as a result of the removing of the sacrificial material of the lines.

In some embodiments, a method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A lower portion of a stack is formed that will comprise vertically-alternating first tiers and second tiers above the conductor tier. The stack comprises laterally-spaced memory-block regions. Material of the first tiers is of different composition from material of the second tiers. The lower portion comprises a lowest of the second tiers directly above the conductor material. A lowest of the first tiers is directly above the lowest second tier. The lowest first tier comprises first sacrificial material. A first layer of second-tier material is directly above the lowest first tier. A second layer of different composition from the first layer is directly above the first layer. A third layer of different composition from the second layer is directly above the second layer. The lowest first tier is thicker than the second layer. Horizontally-elongated troughs are formed in the lower portion that extend through the third layer, the second layer, the first layer, the lowest first tier, the lowest second tier, and into the conductor material. The troughs extend into the conductor material to a depth less than thickness of the lowest first tier. The conductor material, the first sacrificial material of the lowest first tier, and the second layer are laterally recessed selectively relative to the lowest second tier, the first layer, and the third layer to form laterally-opposed recesses longitudinally-along individual of the troughs in the conductor material, in the first sacrificial material of the lowest first tier, and in the second layer. Insulating material is deposited along sidewalls of the troughs and into the recesses. The insulating material fills the recesses in the conductor material and the recesses in the second layer. The insulating material less-than-fills the recesses in the lowest first tier. The insulating material is removed from the recesses in the lowest first tier while leaving the insulating material in the recesses in the conductor material and the recesses in the second layer. After removing the insulating material, horizontally-elongated lines are formed in the troughs that are individually between immediately-laterally-adjacent of the memory-block regions. The lines individually comprise laterally-opposing projections longitudinally there-along that are in the laterally-opposed recesses in the lowest first tier. The lines comprise second sacrificial material of different composition from the first sacrificial material. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion and the lines. Channel-material strings are formed that extend through first tiers and the second tiers in the upper portion to the lowest first tier in the lower portion. Horizontally-elongated trenches are formed into the stack that are individually between the immediately-laterally-adjacent memory-block regions and extend to the line there-between. The second sacrificial material of the lines and projections is removed through the trenches and exposing the first sacrificial material in the lowest first tier. The exposed first sacrificial material is isotropically etched from the lowest first tier through the trenches. After the isotropic etching, conductive material is formed in the lowest first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier.

In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are thus to be afforded full scope as literally worded, and to be appropriately interpreted in accordance with the doctrine of equivalents.