Patent ID: 12244242

DETAILED DESCRIPTION

FIG.1shows a two-stage power-conversion circuit11having a first terminal12that connects to the first stage and a second terminal14that connects to a second stage. The first terminal12is at a first voltage V1and the second terminal14is at a second voltage V2.

In the illustrated embodiment, the first stage is implemented as a switch-mode pre-regulator16and the second stage is implemented as an adiabatic switched-capacitor circuit18. However, in alternative embodiments, this second stage is non-adiabatic, or diabatic.

The pre-regulator16can be implemented in a variety of ways, so long as the essential function thereof, namely regulation of an output voltage, can be carried out. In the illustrated embodiment, the pre-regulator16includes a pre-regulator switch S0, a transformer TO, a diode DO, and a filter capacitor CX. A particularly useful implementation of a pre-regulator16is a magnetically-isolated converter, an example of which is a fly-back converter.

A variety of fly-back converters can be used to implement the pre-regulator16. These include a quasi-resonant fly-back converter, an active-clamp fly-back converter, an interleaved fly-back converter, and a two-switch fly-back converter.

Other examples of magnetically-isolated converters are forward converters. Examples of suitable forward converters include a multi-resonant forward converter, an active-clamp forward converter, an interleaved forward converter, and a two-switch forward converter.

Yet other examples of magnetically-isolated converters are half-bridge converters and full-bridge converters. Examples of half-bridge converters include an asymmetric half-bridge converter, a multi-resonant half-bridge converter, and an LLC resonant half-bridge converter. Examples of full-bridge converters include an asymmetric full-bridge converter, a multi-resonant full-bridge converter, and an LLC resonant full-bridge converter.

It is also possible to implement the pre-regulator16using a non-isolated converter. Examples include a buck converter, a boost converter, and a buck-boost converter.

As used herein, two functional components are said to be “isolated,” or more specifically, “galvanically isolated,” if energy can be communicated between those components without a direct electrical conduction path between those components. Such isolation thus presupposes the use of another intermediary for communicating energy between the two components without having actual electrical current flowing between them. In some cases, this energy may include information.

Examples include the use of a wave, such as an electromagnetic, mechanical, or acoustic wave. As used herein, electromagnetic waves include waves that are in span the visible range, the ultraviolet range, and the infrared range. Such isolation can also be mediated through the use of quasi-static electric or magnetic fields, capacitively, inductively, or mechanically.

Most functional components have circuitry in which different parts of the circuit are at different electrical potentials. However, there is always a potential that represents the lowest potential in that circuit. This is often referred to as “ground” for that circuit.

When a first and second functional component are connected together, there is no guarantee that the electrical potential that defines ground for the first component will be the same as the electrical potential that defines ground for the second circuit. If this is the case, and if these components are connected together, it will be quite possible for electrical current to flow from the higher of the two grounds to the lower of the two grounds. This condition, which is called a “ground loop,” is undesirable. It is particularly undesirable if one of the two components happens to be a human being. In such cases, the current in the ground loop may cause injury.

Such ground loops can be discouraged by galvanically isolating the two components. Such isolation essentially forecloses the occurrence of ground loops and reduces the likelihood that current will reach ground through some unintended path, such as a person's body.

The switched-capacitor circuit18can be implemented as a switched-capacitor network. Examples of such networks include ladder networks, Dickson networks, Series-Parallel networks, Fibonacci networks, and Doubler networks. These can all be adiabatically charged and configured into multi-phase networks. A particularly useful switched-capacitor network is an adiabatically charged version of a full-wave cascade multiplier. However, diabatically charged versions can also be used.

As used herein, changing the charge on a capacitor “adiabatically” means causing an amount of charge stored in that capacitor to change by passing the charge through a non-capacitive element. A positive adiabatic change in charge on the capacitor is considered adiabatic charging while a negative adiabatic change in charge on the capacitor is considered adiabatic discharging. Examples of non-capacitive elements include inductors, magnetic elements, resistors, and combinations thereof.

In some cases, a capacitor can be charged adiabatically for part of the time and diabatically for the rest of the time. Such capacitors are considered to be adiabatically charged. Similarly, in some cases, a capacitor can be discharged adiabatically for part of the time and diabatically for the rest of the time. Such capacitors are considered to be adiabatically discharged.

Diabatic charging includes all charging that is not adiabatic and diabatic discharging includes all discharging that is not adiabatic.

As used herein, an “adiabatic switched-capacitor circuit” is a network having at least one capacitor that is both adiabatically charged and adiabatically discharged. A “diabatic switched-capacitor circuit” is a network that is not an adiabatic switched-capacitor circuit.

Examples of pre-regulators16, switched-capacitor circuits18, their accompanying circuitry, and packaging techniques can be found U.S. Pat. Nos. 9,362,826, 9,497,854, 8,723,491, 8,503,203, 8,693,224, 9,502,968, 8,619,445, 9,203,299, and 9,041,459, U.S. Patent Publications 2016/0197552, 2015/0102798, 2014/0301057, 2013/0154600, 2015/0311786, 2014/0327479, 2016/0028302, 2014/0266132, 2015/0077175, and 2015/0077176, and PCT publications WO2014//062279, WO2015//138378, WO2015//138547, WO2016//149063, and WO 2017/007991, the contents of which are herein incorporated by reference.

A controller20controls the operation of the first and second stages. The controller20includes a primary side22that controls the first stage and a secondary side24that controls the second stage. An isolation barrier26separates the primary side22from the secondary side26.

The primary side22of the controller20controls the pre-regulator switch S0. Opening and closing the pre-regulator switch S0controls the current provided to a primary side of the transformer TO. This, in turn, controls the voltage across the filter capacitor CX. When the pre-regulator switch S0is on, the diode DO is off and when the pre-regulator switch S0is off, the diode DO is on.

The pre-regulator16also includes a regulator-output terminal28maintained at an intermediate voltage VX1that is lower than the first voltage V1. This regulator-output terminal28connects to the adiabatic switched capacitor circuit18. The adiabatic switched capacitor circuit18thus receives this intermediate voltage VX1and transforms it into the second voltage V2.

The switched-capacitor circuit18operates in discrete steps. Thus, it only provides coarse regulation of its output. It cannot provide fine regulation of its output. It is for the pre-regulator16to carry out this fine regulation. The two-stage design shown inFIG.1reduces the need for the pre-regulator16to sustain a high-current burden. This means that the secondary winding of the transformer TO can instead carry a much smaller RMS current. This, in turn, lowers winding loss and reduces the voltage ripple at the regulator-output terminal28. It also means that the filter capacitor CX that couples the pre-regulator16to the switched-capacitor circuit18can be made smaller.

However, the improved performance of the pre-regulator16cannot be completely offset by the increased size and power loss of having the switched-capacitor circuit18in the second stage. Therefore, it is imperative that the switched-capacitor circuit18be both extremely efficient and small.

FIG.2shows a power-conversion circuit10similar to that shown inFIG.1but with additional circuitry for receiving an AC voltage VAC provided by an AC source4and converting that AC voltage VAC into the second voltage V2. The AC voltage VAC is provided to input terminals of a bridge rectifier65having bridge diodes DB1, DB2, DB3, and DB4arranged to form a bridge and having an output across a bridge capacitor CB. The output across the bridge capacitor CB becomes the first voltage V1presented at the first terminal12. A power-conversion circuit10of this type may be incorporated into a travel adapter13, as shown inFIG.16. Such a travel adapter13outputs a DC voltage at a USB port15.

Some embodiment include circuitry for controlling harmonic current and thus boosting the ratio of real power to apparent power that flows through the power supply. This is particularly useful for power supplies that attach to a wall outlet that supplies an AC voltage. An example of such circuitry is an active power-factor corrector67disposed between the bridge rectifier65and the pre-regulator16.

FIG.2also shows a fuse61between the AC power source4and the remaining components of the power-conversion circuit10for safety. An electromagnetic interference filter63is also provided to suppress the uncontrolled emission of electromagnetic waves that may arise during operation of the power-conversion circuit10.

FIG.3shows a first embodiment of a switched-capacitor circuit18that is designed to accept a nominal voltage of 20 volts and to produce a variety of output voltages, such as 5 volts and 10 volts. This is particularly useful for Type-C travel adapters. This is because, unlike the older USB standards, in which the output is always five volts, the newer USB Type C standard permits higher output voltages, such as ten, fifteen, and even twenty volts.

The illustrated switched-capacitor circuit18features a first switched-capacitor stage32, a second switched-capacitor stage34, a first bypass-switch S1, a second bypass-switch S2, and a third bypass-switch S3. An LC filter having an output inductor L1and an output capacitor C0permit adiabatic operation. By selectively opening and closing the bypass-switches S1, S2, S3, it is possible to selectively bypass selected ones of the first and second switched-capacitor stages32,34.

Each of the first and second stages32,34is a 2× voltage divider having a maximum voltage conversion from VX1to VX2of 4:1. The resulting switched-capacitor circuit18is designed to accept an intermediate voltage VX1of 20 volts and to provide an output voltage V2of either 20 volts, 10 volts, or 5 volts. Some embodiments deliver an 15 volt output voltage, which is sometimes required by the Type-C standard. This can be provided by having the pre-regulator16deliver 15 volts to the switched-capacitor circuit18instead of 20 volts and running the switched-capacitor circuit18in the 1:1 mode.

The switched-capacitor circuit18shown inFIG.3has three modes of operation, a 1:1 mode, a 2:1 mode, and a 4:1 mode.

In the 1:1 mode, the first bypass-switch S1closes, and the second and third bypass-switches S2and S3open.

In the 2:1 mode, the second bypass-switch S2closes and the first and third bypass-switches S1and S3open.

In the 4:1 mode, the third bypass-switch S3closes and the first and second bypass-switches S1and S2open. All bypassed stages run in a low-power mode to save power since they are not needed to provide voltage conversion (i.e., they are not switching at a specific frequency).

FIG.4shows a component list for one implementation of the switched-capacitor circuit18shown inFIG.3. The components were selected so the solution provides a high efficiency, a small solution size, and a maximum output voltage ripple of 100 mV peak-to-peak. The total value column specifies the total amount of inductance and/or capacitance required of the components at their operating condition. For example, capacitor C3has a nominal dc bias of 5 volts, therefore, a 22 μF capacitor was selected because it provides approximately 10 μF under this condition.

FIG.5illustrates a circuit36inside the first stage. A similar circuit is within the second stage. During operation, this circuit transitions between first and second states. In the first state, all switches labeled “1” close and all switches labeled “2” open. In the second state, all switches labeled “1” open and all switches labeled “2” close. The circuit36alternates between the first and second state at a specific frequency that is selected to produce a second intermediate voltage VX2that is half of the intermediate voltage VX1.

FIGS.6and7illustrate the predicted efficiency across output power for operation in the 2:1 mode and in the 4:1 mode at an intermediate voltage VX1of 20 volts for two different die sizes.FIG.6is fora nominal die andFIG.7is for a larger die. Since the efficiency at full-load is dominated by resistive losses, the larger silicon die size will result in improved performance. In some, but not all embodiments, a nominal die is 12 mm2and a larger die is 16 mm2

It is worth noting that the power loss in the second stage is approximately equal to the power loss in the first stage. This results in a larger percentage of the die being consumed by the second stage. Furthermore, the efficiency of the 5-volt output configuration is not equal to the square of the efficiency of the 10-volt output configuration because some losses are common to both stages.

FIG.8summarizes performance at an intermediate voltage VX1of 20 volts and an output voltage T72of 5 volts. The passive footprint area is calculated by adding up the area of all of the passive components and adding 0.2 mm of space between them. The solution footprint area is the sum of the silicon die and the passive footprint area. As can be seen from the table, the full-load efficiency is higher with the larger die size. The maximum height is 1.25 mm through the exclusive use of SMT components.

Unlike, conventional switched-capacitor converters, the architecture disclosed herein includes an LC filter that enables adiabatic charging and discharging of the capacitors within each switched-capacitor stage. This adiabatic operation permits high efficiencies at small solution sizes.

FIG.9illustrates another embodiment of the switched-capacitor circuit18that is similar to that shown inFIG.3. However, unlike in the switched-capacitor circuit18shown inFIG.3, the one shown inFIG.9accepts an intermediate voltage VX1of 40 volts instead of 20 volts.

To achieve this requirement, the switched-capacitor circuit18includes a third switched-capacitor stage38. As before, an output voltage V2of either 20 volts, 10 volts, or 5 volts. However, the operating modes are now a 2:1 mode, a 4:1 mode, and an 8:1 mode. Remaining details on the structure and operation of the embodiment shown inFIG.8are similar to those forFIG.3and are omitted for brevity.

FIG.10shows a component list for one implementation of the switched-capacitor circuit18shown inFIG.8.

FIGS.11and12show predicted efficiency across output power for modes 2:1, 4:1, and 8:1 at an intermediate voltage VX1of 20 volts.

FIG.13shows an embodiment of a switched-capacitor circuit18that avoids the use of multiple switched-capacitor stages and bypass switches. Instead, it relies on a single switched-capacitor stage. To achieve the various voltage conversion ratios, the embodiment shown inFIG.13uses different switching patterns for different voltage conversion ratios. Another difference between the embodiment shown inFIG.13and that shown inFIGS.3and9is that the embodiment shown inFIG.13cycles between four distinct states instead of two distinct states. Like the first and second embodiments, this third embodiment also has an LC filter at its output enabling adiabatic charging and discharging of the capacitors C1-C3.

The third embodiment of the switched-capacitor circuit18can receive an intermediate voltage VX1of 20 volts and produce a voltage of 20 volts, 15 volts, 10 volts, or 5 volts. For example, if the intermediate voltage VX1is 20 volts,FIGS.14and15illustrate the corresponding four states required to produce an output voltage VX2of 5 volts and 15 volts, respectively. For best performance, it is preferable that the switched-capacitor circuit18switch between the states in the order shown inFIGS.14-15.