Patent ID: 12200920

DETAILED DESCRIPTION

Various integrated circuit devices include an inverter that includes two transistors having different conductivity types. For example, a static random access memory (SRAM) may include a pair of inverters. A stacked transistor structure in which an upper transistor and a lower transistor are stacked may be used to form an inverter to reduce an area and/or to simplify interconnections between those two transistors. The reduced area of the inverter may result in an increase in a number of metal wires (e.g., a wordline, a bit-line and a power rail) of a back-end structure per a unit area, and those metal wires may be provided at multiple levels and/or may have non-linear shapes to be arranged in the reduced area.

According to some embodiments, only a first group of metal wires (e.g., a wordline and a bit-line) may be provided in a back-end structure, and a second group of metal wires (e.g., a power rail) may be provided in a power distribution network (PDN) structure that is on a back side of a substrate. This configuration may simplify layouts of the back-end structure and each of the metal wires may have a linear shape.

FIG.1is a circuit diagram of an SRAM. The SRAM may include an SRAM unit including six transistors (i.e., first and second pull-up transistors PU1and PU2, first and second pull-down transistors PD1and PD2, and first and second path gate transistors PG1and PG2). The SRAM may also include a word line WL, bit lines BL and BLB, and two power lines electrically connected to a first power having a first voltage (e.g., a drain voltage Vdd) and a second power having a second voltage (e.g., a source voltage Vss). The first pull-up transistor PU1and the first pull-down transistor PD1constitute a right-side inverter INV_R, and the second pull-up transistor PU2and the second pull-down transistor PD2constitute a left-side inverter INV_L. In some embodiments, each of the first and second pull-up transistors PU1and PU2may be a first conductivity type transistor (e.g., a PMOS transistor), and each of the first and second pull-down transistors PD1and PD2and the first and second path gate transistors PG1and PG2may be a second conductivity type transistor (e.g., an NMOS transistor).

FIG.2is a schematic diagram of an SRAM according to some embodiments. Referring toFIG.2, an SRAM may be formed to include multiple stacked structures. The SRAM may include a lower structure S1, an upper structure S2and a back-end structure S3, which are stacked in a vertical direction Z. A PDN structure S4may be provided below the lower structure S1. The lower structure S1may include a substrate (e.g., a substrate100inFIG.4A) and lower transistors (e.g., e.g., a first pull-down transistor PD1and a second pull-down transistor PD2inFIG.3B). The upper structure S2may include upper transistors (e.g., a first pull-up transistor PU1and a second pull-up transistor PU2inFIG.3A) and interconnectors (e.g., a source/drain connector SDC inFIG.4A). The back-end structure S3may include metal wires (e.g., a first wordline WL1and a first bit-line BL1inFIG.4A). The PDN structure S4may include power rails (e.g., a first power rail PR1and a second power rail PR2inFIG.4A).

According to some embodiments, two transistors of a single inverter may be provided in the lower transistor structure and the upper transistor structure, respectively. For example, the first pull-up transistors PU1of the right-side inverter INV_R may be provided in the upper transistor structure, and the first pull-down transistors PD1of the right-side inverter INV_R may be provided in the lower transistor structure. In some embodiments, the first pull-up transistor PU1may overlap the first pull-down transistor PD1. For example, a source/drain of the first pull-up transistor PU1may overlap a source/drain of the first pull-down transistor PD1.

FIGS.3A,3B,3C and3Dare layouts of stacked structures of a first integrated circuit device1000according to some embodiments, andFIGS.4A and4Bare cross-sectional views of the first integrated circuit device1000taken along a line A-A and a line B-B inFIGS.3A to3Daccording to some embodiments.FIG.3Ais a layout of an upper structure,FIG.3Bis a layout of a lower structure,FIG.3Cis a layout of a back-end structure, andFIG.3Dis a layout of a PDN structure.

Referring toFIGS.3A to3D, the first integrated circuit device1000may include a first SRAM unit SRAM1and a second SRAM unit SRAM2. The first SRAM unit SRAM1and the second SRAM unit SRAM2may be arranged in a first horizontal direction X. The dotted lines inFIGS.3A to3Drepresent unit boundaries. In some embodiments, the first SRAM unit SRAM1and the second SRAM unit SRAM2may have layouts symmetric with respect to the unit boundary therebetween as illustrated inFIGS.3A to3D. Those symmetrical layouts allow the first and second SRAM units SRAM1and SRAM2to have a contact (e.g., a first power contact PC1or a first wordline contact WLC1) shared by those two units such that an area of an individual SRAM unit can be reduced.

Referring toFIG.3A, the upper structure may include first and second pull-up transistors PU1and PU2of each SRAM unit. A first upper transistor including a first upper gate electrode UG1may be the first pull-up transistor PU1of the first SRAM unit SRAM1, and a second upper transistor including a second upper gate electrode UG2may be the first pull-up transistor PU1of the second SRAM unit SRAM2. The first upper transistor may also include a first upper channel region UCH1and first and second upper source/drain regions USD1and USD2contacting the first upper channel region UCH1. The second upper transistor may also include a second upper channel region UCH2and third and fourth upper source/drain regions USD3and USD4contacting the second upper channel region UCH2.

A third upper transistor including a third upper gate electrode UG3may be the second pull-up transistor PU2of the first SRAM unit SRAM1, and a fourth upper transistor including a fourth upper gate electrode UG4may be the second pull-up transistor PU2of the second SRAM unit SRAM2. The third upper transistor may also include a third upper channel region UCH3and fifth and sixth upper source/drain regions USD5and USD6contacting the third upper channel region UCH3. The fourth upper transistor may also include a fourth upper channel region UCH4and seventh and eighth upper source/drain regions USD7and USD8contacting the fourth upper channel region UCH4. In some embodiments, the first, second, third and fourth upper transistors may have the same conductivity type (e.g., p-type).

Referring toFIG.3B, the lower structure may include first and second pull-down transistors PD1and PD2and first and second gate path transistors PG1and PG2of each SRAM unit. A first lower transistor including a first lower gate electrode LG1may be the first pull-down transistor PD1of the first SRAM unit SRAM1, and a second lower transistor including a second lower gate electrode LG2may be the first pull-down transistor PD1of the second SRAM unit SRAM2. The first lower transistor may also include a first lower channel region LCH1and first and second lower source/drain regions LSD1and LSD2contacting the first lower channel region LCH1. The second lower transistor may also include a second lower channel region LCH2and third and fourth lower source/drain regions LSD3and LSD4contacting the second lower channel region LCH2.

The second lower source/drain region LSD2may be electrically connected to the second upper source/drain region USD2through a conductive contact that may contact both the second lower source/drain region LSD2and the second upper source/drain region USD2. The fourth lower source/drain region LSD4may be electrically connected to the fourth upper source/drain region USD4through a conductive contact that may contact both the fourth lower source/drain region LSD4and the fourth upper source/drain region USD4. In some embodiments, the second upper source/drain region USD2may overlap the second lower source/drain region LSD2, and the fourth upper source/drain region USD4may overlap the fourth lower source/drain region LSD4.

A third lower transistor including a third lower gate electrode LG3may be the second pull-down transistor PD2of the first SRAM unit SRAM1, and a fourth lower transistor including a fourth lower gate electrode LG4may be the second pull-down transistor PD2of the second SRAM unit SRAM2. The third lower transistor may also include a third lower channel region LCH3and fifth and sixth lower source/drain regions LSD5and LSD6contacting the third lower channel region LCH3. The fourth lower transistor may also include a fourth lower channel region LCH4and seventh and eighth lower source/drain regions LSD7and LSD8contacting the fourth lower channel region LCH4.

The fifth lower source/drain region LSD5may be electrically connected to the fifth upper source/drain region USD5through a conductive contact that may contact both the fifth lower source/drain region LSD5and the fifth upper source/drain region USD5. The seventh lower source/drain region LSD7may be electrically connected to the seventh upper source/drain region USD7through a conductive contact that may contact both the seventh lower source/drain region LSD7and the fourth upper source/drain region USD7. In some embodiments, the fifth upper source/drain region USD5may overlap the fifth lower source/drain region LSD5, and the seventh upper source/drain region USD7may overlap the seventh lower source/drain region LSD7.

A fifth lower transistor including a fifth lower gate electrode LG5may be the first path gate transistor PG1of the first SRAM unit SRAM1, and a sixth lower transistor including a sixth lower gate electrode LG6may be the first path gate transistor PG1of the second SRAM unit SRAM2. The fifth lower transistor may also include a fifth lower channel region LCH5and a ninth lower source/drain region LSD9contacting the fifth lower channel region LCH5. In some embodiments, the second lower source/drain region LSD2of the first lower transistor may be shared with the fifth lower transistor, and the fifth lower channel region LCH5may contact the second lower source/drain region LSD2of the first lower transistor. The sixth lower transistor may also include a sixth lower channel region LCH6and a tenth lower source/drain region LSD10contacting the sixth lower channel region LCH6. In some embodiments, the fourth lower source/drain region LSD4of the second lower transistor may be shared with the sixth lower transistor, and the sixth lower channel region LCH6may contact the fourth lower source/drain region LSD4of the second lower transistor.

A seventh lower transistor including a seventh lower gate electrode LG7may be the second path gate transistor PG2of the first SRAM unit SRAM1, and an eighth lower transistor including an eighth lower gate electrode LG8may be the second path gate transistor PG2of the second SRAM unit SRAM2. The seventh lower transistor may also include a seventh lower channel region LCH7and an eleventh lower source/drain region LSD11contacting the seventh lower channel region LCH7. In some embodiments, the fifth lower source/drain region LSD5of the third lower transistor may be shared with the seventh lower transistor, and the seventh lower channel region LCH7may contact the fifth lower source/drain region LSD5of the third lower transistor. The eighth lower transistor may also include an eighth lower channel region LCH8and a twelfth lower source/drain region LSD12contacting the eighth lower channel region LCH8. In some embodiments, the seventh lower source/drain region LSD7of the fourth lower transistor may be shared with the eighth lower transistor, and the eighth lower channel region LCH8may contact the seventh lower source/drain region LSD7of the fourth lower transistor.

The first upper transistor and the first lower transistor constitute a first inverter of the first SRAM unit SRAM1, the second upper transistor and the second lower transistor constitute a second inverter of the second SRAM unit SRAM2, the third upper transistor and the third lower transistor constitute a third inverter of the first SRAM unit SRAM1, and the fourth upper transistor and the fourth lower transistor constitute a fourth inverter of the second SRAM unit SRAM2.

Referring toFIG.3C, the back-end structure may include wordlines (e.g., first, second and third wordlines WL1, WL2, WL3) and bit-lines (e.g., first and second bit-lines BL1and BL2), which are alternately arranged along the first horizontal direction X. In some embodiments, each of the wordlines and the bit-lines may have a linear shape extending longitudinally in a second horizontal direction Y that is perpendicular to the first horizontal direction X, as illustrated inFIG.3C.

Referring toFIG.3D, the PDN structure may include power rails (e.g., first, second, third, fourth, fifth, sixth and seventh power rails PR1, PR2, PR3, PR4, PR5, PR6and PR7). In some embodiments, two adjacent power rails (e.g., the first and second power rails PR1and PR2or the fourth and fifth power rails PR4and PR5) may be electrically connected to different power sources having different voltages. The first, fourth and sixth power rails PR1, PR4and PR6may be electrically connected to a first power having a first voltage (e.g., a drain voltage Vdd), and the second, third, fifth and seventh power rails PR2, PR3, PR5and PR7may be electrically connected to a second power having a second voltage (e.g., a source voltage Vss). In some embodiments, each of the power rails may have a linear shape extending longitudinally in the second horizontal direction Y, as illustrated inFIG.3D.

Referring toFIGS.3A to3D and4A, the lower structure may include a substrate100on which upper and lower transistors are provided. The substrate100may include a front side100F facing those transistors and a back side100B opposite the front side100F. The first horizontal direction X and the second horizontal direction Y may be parallel to the front side100F and/or the back side100B of the substrate100. The first integrated circuit device1000may further include multiple insulating layers (e.g., a first insulating layer120, a second insulating layer140, a third insulating layer160, a fourth insulating layer220, a fifth insulating layer240and a sixth insulating layer320). In some embodiments, some of those insulating layers may include the same material. The second insulating layer140may separate the first upper source/drain region USD1from the first lower source/drain region LSD1and may separate the third upper source/drain region USD3from the third lower source/drain region LSD3.

The substrate100may include one or more semiconductor materials, for example, Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC and/or InP. For example, the substrate100may be a silicon layer. In some embodiments, the substrate100may be a portion of a wafer (e.g., a single crystal silicon wafer). Each of the first to sixth insulating layers120,140,160,220,240and320may include an insulating material (e.g., silicon oxide, silicon nitride, silicon oxynitride or low-k material). The low k material may include, for example, fluorine-doped silicon dioxide, organosilicate glass, carbon-doped oxide, porous silicon dioxide, porous organosilicate glass, a spin-on organic polymeric dielectric, or a spin-on silicon based polymeric dielectric.

Each of the gate electrodes may include a semiconductor layer (e.g., a poly silicon layer), a work function layer (e.g., TiC layer, TiAl layer, TiAlC layer or TiN layer) and/or a metal layer (e.g., a tungsten layer, an aluminum layer or a copper layer). Each of the source/drain regions may be formed through an epitaxial growth process using a channel region to which that source/drain region contacts. Each of the source/drain regions may include one or more semiconductor materials, for example, Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC and/or InP and may optionally include impurities (e.g., boron, phosphorus or arsenic).

The upper structure may also include a source/drain connector SDC provided on the first upper source/drain region USD1and the third upper source/drain region USD3. The source/drain connector SDC may extend longitudinally in the first horizontal direction X and may electrically connect the first upper source/drain region USD1and the third upper source/drain region USD3. In some embodiments, the source/drain connector SDC may contact upper surfaces of the first upper source/drain region USD1and the third upper source/drain region USD3.

The first integrated circuit device1000may further include first, second, third, fourth, fifth, sixth and seventh power contacts PC1, PC2, PC3, PC4, PC5, PC6and PC7. Each of those power contacts may electrically connect one of the power rails to one of the source/drain regions. Each of those power contacts may extend through the substrate100.

The first power contact PC1may be provided on the unit boundary of the first and second SRAM units SRAM1and SRAM2, as illustrated inFIG.3Aand may electrically connect the source/drain connector SDC to the first power rail PR1. The first power contact PC1may extend through the substrate100and may be in the first, second and third insulating layers120,140and160. In some embodiments, the first power contact PC1may contact both the source/drain connector SDC and the first power rail PR1.

The second power contact PC2may electrically connect the first lower source/drain region LSD1to the second power rail PR2, and the third power contact PC3may electrically connect the third lower source/drain region LSD3to the third power rail PR3. In some embodiments, the second power contact PC2may contact both the first lower source/drain region LSD1and the second power rail PR2, and the third power contact PC3may contact both the third lower source/drain region LSD3and the third power rail PR3. Each of the second power contact PC2and the third power contact PC3may extend through the substrate100.

In some embodiments, each of the first, second and third power contacts PC1, PC2and PC3may have a wider width in the first horizontal direction X adjacent the back side100B of the substrate100, and the width of each of the first, second and third power contacts PC1, PC2and PC3may decrease along the vertical direction Z from the back side100B to the front side100F of the substrate100. The vertical direction Z may be perpendicular to the first and second horizontal directions X and Y.

AlthoughFIG.4Aillustrates that the first, second and third power contacts PC1, PC2and PC3contact the first, second and third power rails PR1, PR2and PR3, respectively, in some embodiments, a connection structure including insulating layers, conductive vias and conductive wires may be provided between the first, second and third power contacts PC1, PC2and PC3and the first, second and third power rails PR1, PR2and PR3, and the first, second and third power contacts PC1, PC2and PC3may be electrically connected to the first, second and third power rails PR1, PR2and PR3through the connection structure. For example, the first power contact PC1may be electrically connected to the first power rail PR1through at least one conductive wire and at least one via of the connection structure provided between the first power contact PC1and the first power rail PR1.

Referring toFIGS.4A and4B, the first wordline WL1and the first and second bit-lines BL1and BL2may be provided in the fifth insulating layer240. The first wordline WL1, the first and second bit-lines BL1and BL2and the fifth insulating layer240constitute the back-end structure. The substrate100may extend between the PDN structure including the first and second power rails PR1and PR2and the first wordline WL1and may also extend between the PDN structure and the first and second bit-lines BL1and BL2.

In some embodiments, lower surfaces of the first wordline WL1and the first bit-line BL1may be at an equal height from the substrate100. In some embodiments, the second and third wordlines WL2and WL3and the second bit-line BL2may also be provided in the fifth insulating layer240and lower surfaces of the second and third wordlines WL2and WL3and the second bit-line BL2may be at an equal height from the substrate100. In some embodiments, the first wordline WL1may overlap at least one power rail (i.e., the first power rail PR1).

The first integrated circuit device1000may further include wordline contacts (e.g., first, second and third wordline contacts WLC1, WLC2and WLC3) and bit-line contacts (e.g., first, second, third and fourth bit-line contacts BLC1, BLC2, BLC3and BLC4). Each wordline contact may electrically connect one of the gate electrodes to one of the wordlines, and each bit-line contact may electrically connect one of the source/drain regions to one of the bit-lines. For example, the first wordline contact WLC1may electrically connect the fifth lower gate electrode LG5to the first wordline WL1, and the third bit-line contact BLC3may electrically connect the ninth lower source/drain region LSD9to the first bit-line BL1. In some embodiments, the first wordline contact WLC1may contact both the fifth lower gate electrode LG5and the first wordline WL1, and the first bit-line contact BLC1may contact both the ninth lower source/drain region LSD9and the first bit-line BL1.

In some embodiments, the first wordline contact WLC1may be provided on the unit boundary between the first SRAM unit SRAM1and the second SRAM unit SRAM2, as illustrated inFIG.3B, and may be electrically connected to both the fifth lower gate electrode LG5of the first SRAM unit SRAM1and the sixth lower gate electrode LG6of the second SRAM unit SRAM2.

Referring againFIGS.3A and4A, the first integrated circuit device1000may further include a first shared contact SHC1electrically connecting the first upper gate electrode UG1to the fifth upper source/drain region USD5. The first shared contact SHC1may be formed in the third insulating layer160and may be formed on the first upper gate electrode UG1and the fifth upper source/drain region USD5. In some embodiments, the first shared contact SHC1may contact upper surfaces of the first upper gate electrode UG1and the fifth upper source/drain region USD5.

Additionally, the first integrated circuit device1000may include a second shared contact SHC2, a third shared contact SHC3, and a fourth shared contact SHC4. The second shared contact SHC2may electrically connect the second upper gate electrode UG2to the seventh upper source/drain region USD7, the third shared contact SHC3may electrically connect the third upper gate electrode UG3to the second upper source/drain region USD2, and the fourth shared contact SHC4may electrically connect the fourth upper gate electrode UG4to the fourth upper source/drain region USD4. In some embodiments, the second shared contact SHC2, the third shared contact SHC3, and the fourth shared contact SHC4may be formed in the third insulating layer160.

The source/drain connector SDC, the wordlines (e.g., the first wordline WL1), the bit-lines (e.g., the first bit-line BL1), the power rails (e.g., the first power rail PR1), the wordline contacts (e.g., the first wordline contact WLC1), the bit-line contacts (e.g., the first bit-line contact BLC1), the power contacts (e.g., the first power contact PC1), and the shared contacts (e.g., the first shared contact SHC1) may include a metal (e.g., tungsten, cobalt, aluminum, ruthenium or copper) and/or a metal nitride layer (e.g., titanium nitride or tantalum nitride).

FIG.5is a cross-sectional view of the first integrated circuit device1000taken along the line A-A ofFIGS.3A to3Daccording to some embodiments. The cross-sectional view ofFIG.5is similar to that ofFIG.4Awith a primary difference being that the first power contact PC1includes an upper portion PC1U and a lower portion PC1L. The lower portion PC1L may be in the substrate100and may have a wider width in the first horizontal direction X adjacent the back side100B of the substrate100, and the width of the lower portion PC1L may decrease along the vertical direction Z from the back side100B to the front side100F of the substrate100. The upper portion PC1U may be in the first, second and third insulating layers120,140and160. The upper portion PC1U may have a width in the first horizontal direction X, which is narrow adjacent the front side100F of the substrate100and increases along the vertical direction Z from the front side100F of the substrate100toward the shared source/drain connector SDC.

FIGS.6A,6B,6C and6Dare layouts of stacked structures of a second integrated circuit device2000according to some embodiments, andFIGS.7A and7Bare cross-sectional views of the integrated circuit device2000taken along a line C-C and a line D-D inFIGS.6A to6Daccording to some embodiments.FIG.6Ais a layout of an upper structure,FIG.6Bis a layout of a lower structure,FIG.6Cis a layout of a back-end structure, andFIG.6Dis a layout of a PDN structure. A primary difference between the first integrated circuit device1000and the second integrated circuit device2000is the numbers of transistors included in the upper and lower structures.

Referring toFIGS.6A to6D, the integrated circuit device2000may include a first SRAM unit SRAM1and a second SRAM unit SRAM2. In some embodiments, the first SRAM unit SRAM1and the second SRAM unit SRAM2may have layouts symmetric with respect to the unit boundary therebetween as illustrated inFIGS.6A to6D.

Referring toFIG.6A, the upper structure may include first and second pull-down transistors PD1and PD2and first and second gate path transistors PG1and PG2of each SRAM unit. A first upper transistor including a first upper gate electrode UG1may be the first pull-down transistor PD1of the first SRAM unit SRAM1, and a second upper transistor including a second upper gate electrode UG2may be the first pull-down transistor PD1of the second SRAM unit SRAM2. The first upper transistor may also include a first upper channel region UCH1and first and second upper source/drain regions USD1and USD2contacting the first upper channel region UCH1. The second upper transistor may also include a second upper channel region UCH2and third and fourth upper source/drain regions USD3and USD4contacting the second upper channel region UCH2.

A third upper transistor including a third upper gate electrode UG3may be the second pull-down transistor PD2of the first SRAM unit SRAM1, and a fourth upper transistor including a fourth upper gate electrode UG4may be the second pull-down transistor PD2of the second SRAM unit SRAM2. The third upper transistor may also include a third upper channel region UCH3and fifth and sixth upper source/drain regions USD5and USD6contacting the third upper channel region UCH3. The fourth upper transistor may also include a fourth upper channel region UCH4and seventh and eighth upper source/drain regions USD7and USD8contacting the fourth upper channel region UCH4.

A fifth upper transistor including a fifth upper gate electrode UG5may be the first path gate transistor PG1of the first SRAM unit SRAM1, and a sixth upper transistor including a sixth upper gate electrode UG6may be the first path gate transistor PG1of the second SRAM unit SRAM2. The fifth upper transistor may also include a fifth upper channel region UCH5and a ninth upper source/drain region USD9contacting the fifth upper channel region UCH5. In some embodiments, the second upper source/drain region USD2of the first lower transistor may be shared with the fifth lower transistor, and the fifth upper channel region UCH5may contact the second upper source/drain region USD2of the first upper transistor. The sixth upper transistor may also include a sixth upper channel region UCH6and a tenth upper source/drain region USD10contacting the sixth upper channel region UCH6. In some embodiments, the fourth upper source/drain region USD4of the second upper transistor may be shared with the sixth upper transistor, and the sixth upper channel region UCH6may contact the fourth upper source/drain region USD4of the second upper transistor.

A seventh upper transistor including a seventh upper gate electrode UG7may be the second path gate transistor PG2of the first SRAM unit SRAM1, and an eighth upper transistor including an eighth upper gate electrode UG8may be the second path gate transistor PG2of the second SRAM unit SRAM2. The seventh upper transistor may also include a seventh upper channel region UCH7and an eleventh upper source/drain region USD11contacting the seventh upper channel region UCH7. In some embodiments, the fifth upper source/drain region USD5of the third upper transistor may be shared with the seventh upper transistor, and the seventh upper channel region UCH7may contact the fifth upper source/drain region USD5of the third upper transistor. The eighth upper transistor may also include an eighth upper channel region UCH8and a twelfth upper source/drain region USD12contacting the eighth upper channel region UCH8. In some embodiments, the seventh upper source/drain region USD7of the fourth upper transistor may be shared with the eighth upper transistor, and the eighth upper channel region UCH8may contact the seventh upper source/drain region USD7of the fourth lower transistor.

Referring toFIG.6B, the lower structure may include first and second pull-up transistors PU1and PU2of each SRAM unit. A first lower transistor including a first lower gate electrode LG1may be the first pull-up transistor PU1of the first SRAM unit SRAM1, and a second lower transistor including a second lower gate electrode LG2may be the first pull-up transistor PU1of the second SRAM unit SRAM2. The first lower transistor may also include a first lower channel region LCH1and first and second lower source/drain regions LSD1and LSD2contacting the first lower channel region LCH1. The second lower transistor may also include a second lower channel region LCH2and third and fourth lower source/drain regions LSD3and LSD4contacting the second lower channel region LCH2.

A third lower transistor including a third lower gate electrode LG3may be the second pull-up transistor PU2of the first SRAM unit SRAM1, and a fourth lower transistor including a fourth lower gate electrode LG4may be the second pull-up transistor PU2of the second SRAM unit SRAM2. The third lower transistor may also include a third lower channel region LCH3and fifth and sixth lower source/drain regions LSD5and LSD6contacting the third lower channel region LCH3. The fourth lower transistor may also include a fourth lower channel region LCH4and seventh and eighth lower source/drain regions LSD7and LSD8contacting the fourth lower channel region LCH4.

The layout of the back-end structure of the second integrated circuit device2000illustrated inFIG.6Cmay be similar to the layout of the back-end structure of the first integrated circuit device1000illustrated inFIG.3C. Referring toFIG.6C, each of the wordlines and the bit-lines may have a linear shape extending longitudinally in the second horizontal direction Y.

The layout of the PDN structure of the second integrated circuit device2000illustrated inFIG.6Dmay be similar to the layout of the PDN structure of the first integrated circuit device1000illustrated inFIG.3D. Referring toFIG.6D, the first, fourth and sixth power rails PR1, PR4and PR6may be electrically connected to a second power having a second voltage (e.g., a source voltage Vss), and the second, third, fifth and seventh power rails PR2, PR3, PR5and PR7may be electrically connected to a first power having a first voltage (e.g., a drain voltage Vdd). In some embodiments, each of the power rails may have a linear shape extending longitudinally in the second horizontal direction Y, as illustrated inFIG.6D.

The cross-sectional view ofFIG.7Amay be similar to the cross-sectional view ofFIG.4Awith primary difference being that the first power rail PR1is electrically connected to the second power having a second voltage (e.g., a source voltage Vss), and the second and third power rails PR2and PR3are electrically connected to the first power having a first voltage (e.g., a drain voltage Vdd).

The cross-sectional view ofFIG.7Bmay be similar to the cross-sectional view ofFIG.4Bwith primary difference being that both a gate electrode (i.e., the fifth upper gate electrode UG5and the sixth upper gate electrode UG6) electrically connected to the first wordline WL1, and a source/drain region (i.e., the ninth upper source/drain region USD9) electrically connected to the first bit-line BL1are in the upper structure. Accordingly, the first wordline contact WLC1and the third bit-line contact BLC3may be provided higher than the second insulating layer140.

FIG.7Cshows cross-sectional views of the second integrated circuit device2000taken along a line E-E and a line F-F inFIG.6Baccording to some embodiments. For simplicity of illustration,FIG.7Cshows only the lower structure and the upper structure of the second integrated circuit device2000. Referring toFIG.7C, the first shared contact SHC1electrically connecting the first lower gate electrode LG1of the first inverter to the fifth lower source/drain region LSD5of the third inverter may be provided in the substrate100. In some embodiments, the first lower gate electrode LG1may contact the first upper gate electrode UG1for electrical connection therebetween, as illustrated inFIG.7C. In some embodiments, the first upper gate electrode UG1may be spaced apart from the first lower gate electrode LG1in the vertical direction Z, and a separate conductor electrically connecting the first upper gate electrode UG1and the first lower gate electrode LG1may be provided. The fifth lower source/drain region LSD5may be electrically connected to the eighth upper source/drain region USD8through a interconnection contact IC that extends through the second insulating layer140.

FIG.8is a flow chart of methods of forming the integrated circuit device1000according to some embodiments, andFIGS.9through12are cross-sectional views illustrating methods of forming the integrated circuit device1000, specifically a portion illustrated inFIG.4A, according to some embodiments.

Referring toFIGS.8and9, the methods may include forming lower transistors including first and third lower source/drain regions LSD1and LSD3and upper transistors including first and third upper source/drain regions USD1and USD3on a front side100F of a substrate100(Block10). First, second and third insulating layers120,140and160may also be formed on the front side100F of the substrate100.

Referring toFIGS.8and10, a source/drain connector SDC may be formed on the upper transistors (Block20). The source/drain connector SDC may be formed in the third insulating layer160and may contact upper surfaces of the first and third upper source/drain regions USD1and USD3. A fourth insulating layer220may be formed on the source/drain connector SDC, and then a back-end structure including the first wordline WL1and first and second bit-lines BL1and BL2may be formed on the fourth insulating layer220(Block30). The back-end structure may also include a fifth insulating layer240.

Referring toFIGS.8and11, the structure shown inFIG.10may be turned around (e.g., flipped), and then a portion of the substrate100may be removed to reduce a thickness of the substrate100. A thickness of the substrate100may be in a range of 50 nm to 100 nm after removing the portion of the substrate100.

After removing the portion of the substrate100, an etch process may be performed on a back side100B of the substrate100to form first, second and third openings OP1, OP2and OP3. In some embodiments, the first opening OP1may extend through the substrate100and may expose the source/drain connector SDC, and the second and third openings OP2and OP3may extend through the substrate100and may expose the first and third lower source/drain regions LSD1and LSD3, respectively.

Referring toFIGS.8and12, the methods may include forming first, second and third power contacts PC1, PC2and PC3in the first, second and third openings OP1, OP2and OP3, respectively (Block40). In some embodiments, the first shared contact SHC1inFIG.7Cmay be formed using the process of forming the first, second and third power contacts PC1, PC2and PC3. The etch process of forming the first, second and third openings OP1, OP2and OP3may also form a shared contact opening in the substrate, in which the first shared contact SHC1is formed subsequently, and then the first shared contact SHC1may be formed while forming the first, second and third power contacts PC1, PC2and PC3. For example, the first, second and third power contacts PC1, PC2and PC3and the first shared contact SHC1may be formed by forming a conductive layer in the first, second and third openings OP1, OP2and OP3and the shared contact opening, and then removing a portion of the conductive layer, thereby separating the first, second and third power contacts PC1, PC2and PC3and the first shared contact SHC1from each other.

Referring toFIGS.8and12, a PDN structure may be formed on power contacts (e.g., the first, second and third power contacts PC1, PC2and PC3) (Block50). For example, power rails (e.g., the first, second and third power rails PR1, PR2and PR3) may be formed on the power contacts and then an insulating layer (e.g., the sixth insulating layer320) may be formed on the power rails for electrical isolation between those power rails.

Example embodiments are described herein with reference to the accompanying drawings. Many different forms and embodiments are possible without deviating from the scope of the present invention. Accordingly, the present invention should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete and will convey the scope of the present invention to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference numbers refer to like elements throughout.

Example embodiments of the present invention are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments and intermediate structures of example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments of the present invention should not be construed as limited to the particular shapes illustrated herein but include deviations in shapes that result, for example, from manufacturing, unless the context clearly indicates otherwise.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used in this specification, specify the presence of the stated features, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components and/or groups thereof. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element could be termed a second element without departing from the scope of the present invention.

The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the scope of the invention. Thus, to the maximum extent allowed by law, the scope is to be determined by the broadest permissible interpretation of the following claims and their equivalents and shall not be restricted or limited by the foregoing detailed description.