Patent ID: 12207463

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Like components in the drawings will be referred to as like reference numerals, and will not be repeatedly described.

FIG.1is an equivalent circuit diagram of a memory cell of a vertical non-volatile memory device, according to an embodiment of the inventive concept.

Referring toFIG.1, a vertical non-volatile memory device100(hereinafter, simply referred to as a ‘memory device’) according to the current embodiment of the inventive concept may include a common source line CSL, a plurality of bit lines BL0through BLm, and a plurality of cell strings CSTR. The plurality of bit lines BL0through BLm may be arranged two-dimensionally, and the plurality of cell strings CSTR may be respectively connected to the plurality of bit lines BL0through BLm in parallel. The plurality of cell strings CSTR may be connected in common to the common source line CSL.

Each of the cell strings CSTR may include first and second string selection transistors SSt1and SSt2, memory cell transistors MCT, and a ground selection transistor GST. Each of the memory cell transistors MCT may include a data storage element. More specifically, the first and second string selection transistors SSt1and SSt2may be serially connected to each other, the second string selection transistor SSt2may be connected to a corresponding bit line, and the ground selection transistor GST may be connected to the common source line CSL. The memory cell transistors MCT may be serially connected between the first string selection transistor SSt1and the ground selection transistor GST. Meanwhile, according to an embodiment of the inventive concept, one string selection transistor may be arranged in each cell string CSTR.

As shown inFIG.1, each cell string CSTR may include a first dummy cell transistor DMC1connected between the first string selection transistor SSt1and the memory cell transistor MCT and a second dummy cell transistor DMC2connected between the ground selection transistor GST and the memory cell transistor MCT. However, according to an embodiment of the inventive concept, at least one of the first dummy cell transistor DCM1or the second dummy cell transistor DMC2may be omitted.

One cell string CSTR includes a plurality of memory cell transistors MCT having different distances from the common source line CSL, such that multi-layer word lines WL0through WLn may be arranged between the common source line CSL and the bit lines BL0through BLm. Gate electrodes of the memory cell transistors MCT, arranged substantially in the same distance from the common source line CSL, may be connected in common to one of the word lines WL0through WLn and thus may be in an equipotential state. Terms such as “same,” “equal,” “planar,” or “coplanar,” as used herein when referring to orientation, layout, location, shapes, sizes, compositions, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, composition, amount, or other measure, but are intended to encompass nearly identical orientation, layout, location, shapes, sizes, compositions, amounts, or other measures within acceptable variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise. For example, items described as “substantially the same,” “substantially equal,” or “substantially planar,” may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes.

The memory device100according to the current embodiment of the inventive concept may include a thermoelectric device120in a cell array area (see CAA ofFIG.2A) where the plurality of cell strings CSTR are arranged. The thermoelectric device120may include at least one N-type semiconductor pillar N-SP and at least one P-type semiconductor pillar P-SP. The N-type semiconductor pillar N-SP and the P-type semiconductor pillar P-SP may have a structure that is similar to a vertical channel structure (see VCS ofFIG.2A) constituting the cell string CSTR. Thus, the N-type semiconductor pillar N-SP and the P-type semiconductor pillar P-SP may have a structure extending through a stacked structure (see ST ofFIG.2B) on a substrate (see101ofFIG.2B) in a direction perpendicular to a top surface of the substrate101. The N-type semiconductor pillar N-SP may be formed of an N-type semiconductor material, and the P-type semiconductor pillar P-SP may be formed of a P-type semiconductor material. For example, the N-type semiconductor pillar N-SP may be formed of polysilicon doped with N-type impurities, and the P-type semiconductor pillar P-SP may be formed of polysilicon doped with P-type impurities. Materials of the N-type semiconductor pillar N-SP and the P-type semiconductor pillar P-SP are not limited to polysilicon. For example, the N-type semiconductor pillar N-SP and the P-type semiconductor pillar P-SP may be formed of a semiconductor such as bismuth, tellurium, etc.

The N-type semiconductor pillar N-SP and the P-type semiconductor pillar P-SP may be connected, through lower portions thereof, to a conductive layer on the substrate101, and may be electrically connected to each other through the conductive layer. The conductive layer may be, for example, the common source line CSL. When the thermoelectric device120operates, the N-type semiconductor pillar N-SP may be connected, through an upper portion thereof, to a power source and the P-type semiconductor pillar P-SP may be connected, through an upper portion thereof, to ground. In the memory device100according to the current embodiment of the inventive concept, heat generated in the substrate101and/or the stacked structure ST may be effectively released to the outside by an operation of the thermoelectric device120through the N-type semiconductor pillar N-SP and the P-type semiconductor pillar P-SP. Thus, the memory device100according to the current embodiment of the inventive concept may stably maintain an operating temperature in a chip level.

The detailed structure and principle of the thermoelectric device120will be described in more detail with reference toFIGS.2A through5B.

FIG.2Ais a plane view of a memory device according to an embodiment of the inventive concept, andFIG.2Bis a cross-sectional view of a portion I-I′, a portion II-II′, and a portion III-III′ taken from the memory device ofFIG.2A. A description will be made with reference toFIGS.2A and2Btogether withFIG.1.

Referring toFIGS.2A and2B, the memory device100according to the current embodiment of the inventive concept may include a cell array area CAA and an extension area EA which are defined on the substrate101.

The substrate101may have a top surface FS extending in a first direction x and a second direction y, perpendicular to the first direction x. The substrate101may include a semiconductor material, for example, a Group IV-semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. On the substrate101, a cell area and a peripheral area arranged outside the cell area may be defined. The cell area may include the cell array area CAA and the extension area EA.

The cell array area CAA may be an area where the string selection transistors SSt1and SSt2, the memory cell transistor MCT, and the ground selection transistor GST, which constitute the cell strings CSTR described with reference toFIG.1, are arranged. The plurality of bit lines BL0through BLm may be arranged on the cell array area CAA, and impurity areas and the common source line CSL may be arranged under the cell array area CAA.

The extension area EA may be an area where an electrode pad ELp, formed by extending gate electrode layers EL of the string selection transistors SSt1and SSt2, the memory cell transistor MCT, and the ground selection transistor GST from the cell array area CAA in the first direction x, is arranged. In the extension area EA, the electrode pad ELp may be connected to a vertical contact VC. For example, the gate electrode layer EL may form the electrode pad ELp in the extension area EA, and the stacked structure ST or the gate electrode layer EL may have a step structure in the extension area EA, as can be seen fromFIG.2B. Thus, in the extension area EA, the length of the gate electrode layer EL in the first direction x may decrease in a direction away from the substrate101along a third direction z (perpendicular to the first direction x and the second direction y), and the height of the stacked structure ST in the third direction z may decrease in a direction away from the cell array area CAA. Side end portions of the gate electrode layer EL may be arranged apart from each other at specific intervals in the first direction x such that a stepped shaped structure is formed.

The stacked structure ST may extend to the extension area EA in the first direction x from the cell array area CAA on the substrate101. The stacked structure ST may be provided in plural on the substrate101, and the stacked structures ST may be arranged apart from one another in the second direction y. For example, an isolation area extending in the first direction x may be arranged in the second direction y, and the stacked structures ST may be separated by the isolation area. Herein, the isolation area may be referred to as a word line cut area. A buffer insulation layer110may be between the stacked structure ST and the substrate101.

The stacked structure ST may include a plurality of gate electrode layers EL and interlayer insulation layers ILD that are stacked alternately in the third direction z perpendicular to the top surface FS of the substrate101. The thicknesses of the gate electrode layers EL may be substantially the same as one another. The thicknesses of the interlayer insulation layers ILD may vary with characteristics of a memory device. The thickness of the interlayer insulation layer ILD may be less than that of the gate electrode layer EL.

As described above, each gate electrode layer EL may constitute the electrode pad ELp in the extension area EA. The electrode pads ELp of the gate electrode layer EL may be in different positions horizontally and vertically. For example, the stacked structure ST may include the gate electrode layer EL and the interlayer insulation layer ILD that are stacked alternately in the third direction z, and the gate electrode layer EL constituting the electrode pad ELp in the extension area EA may have a step structure.

A planarizing insulation layer150may cover the stacked structure ST on the substrate101. The planarizing insulation layer150may cover the step structure of the stacked structure ST in the extension area EA. The planarizing insulation layer150may include one insulation layer or a plurality of stacked insulation layers.

In the cell array area CAA, the plurality of vertical channel structures VCS may pass through the stacked structure ST. In the cell array area CAA, a plurality of semiconductor pillars N-SP and P-SP may pass through the stacked structure ST. Although not shown, in the extension area EA, a plurality of dummy channel structures may pass through the planarizing insulation layer150and the stacked structure ST.

The plurality of semiconductor pillars N-SP and P-SP may be arranged in the second direction y. The plurality of semiconductor pillars N-SP and P-SP may include at least one N-type semiconductor pillar N-SP and at least one P-type semiconductor pillar P-SP. In addition, the at least one N-type semiconductor pillar N-SP and the at least one P-type semiconductor pillar P-SP may be electrically connected to each other to constitute the thermoelectric device120.

The plurality of semiconductor pillars N-SP and P-SP may have various arrangement structures in the cell array area CAA. For example, the plurality of semiconductor pillars N-SP and P-SP may be arranged in at least one pair of two in one block along the first direction x. As shown inFIG.2A, the pair of two may be arranged in the second direction y. According to an embodiment of the inventive concept not illustrated, the plurality of semiconductor pillars N-SP and P-SP may be arranged in at least one pair of three or more in one block along the first direction x. The pair of three or more may be arranged in the second direction y. According to an embodiment of the inventive concept, at least one of the plurality of semiconductor pillars N-SP and P-SP may be arranged in one block along the first direction x.

In the third direction z, bottom surfaces of the vertical channel structure VCS and the semiconductor pillars N-SP and P-SP may be in substantially the same level. The vertical channel structure VCS and the semiconductor pillars N-SP and P-SP may have substantially the same length in the third direction z. This is because a through-hole for the vertical channel structure VCS and through-holes for the semiconductor pillars N-SP and P-SP may be formed through similar processes or the same process.

The vertical channel structure VCS may include a lower semiconductor pattern LSP, an upper semiconductor pattern USP, a data storage pattern VP, and a buried insulation pattern VI. The lower semiconductor pattern LSP may contact the substrate101and may include an epitaxial layer in the shape of a pillar growing from the substrate101. A gate insulation layer115may be arranged in a part of a sidewall of the lower semiconductor pattern LSP. The upper semiconductor pattern USP may contact the lower semiconductor pattern LSP. The inside of the upper semiconductor pattern USP may be filled with the buried insulation pattern VI including an insulation material. The lower semiconductor pattern LSP and the upper semiconductor pattern USP may be electrically connected to each other by passing through the data storage pattern VP. It will be understood that when an element is referred to as being “connected” or “coupled” to or “on” another element, it can be directly connected or coupled to or on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as “contacting” or “in contact with” another element, there are no intervening elements present at the point of contact.

The data storage pattern VP may be arranged between the stacked structure ST and the upper semiconductor pattern USP. The data storage pattern VP may extend in the third direction z and surround a sidewall of the upper semiconductor pattern USP. The data storage pattern VP may include one thin film or a plurality of thin films. In embodiments of the inventive concept, the data storage pattern VP, which is a data storage film of a NAND flash memory device, may include a tunnel insulation layer, a charge storage film, and a blocking insulation layer. A structure of the data storage pattern VP will be described in more detail in a description of the vertical channel structure VCS ofFIG.4A.

A horizontal insulation pattern HP may extend to top surfaces and bottom surfaces of the gate electrode layer EL between the gate electrode layer EL and the vertical channel structure VCS. The horizontal insulation pattern HP as a part of the data storage film of the NAND flash memory device may include the charge storage film and the blocking insulation layer. However, the horizontal insulation pattern HP may include the blocking insulation layer.

The semiconductor pillars N-SP and P-SP may include a semiconductor layer in the shape of a pillar extending in the third direction z from the substrate101. For example, the N-type semiconductor pillar N-SP may include an N-type semiconductor layer in the shape of a pillar and the P-type semiconductor pillar P-SP may include a P-type semiconductor layer in the shape of a pillar. The semiconductor layer may be formed of, for example, doped polysilicon. A material of the semiconductor layer is not be limited to polysilicon. According to an embodiment of the inventive concept, the semiconductor pillars N-SP and P-SP may include an epitaxial layer such as the lower semiconductor pattern LSP of the vertical channel structure VCS. In this case, the semiconductor pillars N-SP and P-SP may have a structure including an epitaxial layer and a semiconductor layer on the epitaxial layer. Meanwhile, side surfaces of the semiconductor pillars N-SP and P-SP may be surrounded by a pillar insulation layer PIS. Thus, the semiconductor pillars N-SP and P-SP may be electrically insulated from the gate electrode layer EL of the stacked structure ST by the pillar insulation layer PIS. Structures of the semiconductor pillars N-SP and P-SP and the pillar insulation layer PIS will be described in more detail in a description of the semiconductor pillars N-SP and P-SP to be made with reference toFIG.4B.

A bit line electrode pad BP and a bit line contact plug BCP connected thereto may be on a top end of the upper semiconductor pattern USP. A side surface of the bit line electrode pad BP may be surrounded by the data storage pattern VP. According to an embodiment of the inventive concept, the bit line electrode pad BP may be on a top surface of the upper semiconductor pattern USP and a top surface of the data storage pattern VP, and a side surface of the bit line electrode pad BP may be surrounded by a first upper interlayer insulation layer160.

A power pad PP and a ground pad GP and a power contact plug PCP and a ground contact plug GCP respectively connected thereto may be on top ends of the semiconductor pillars N-SP and P-SP. Side surfaces of the power pad PP and the ground pad GP may be surrounded by the pillar insulation layer PIS. According to an embodiment of the inventive concept, the power pad PP and the ground pad GP may be on the top surfaces of the semiconductor pillars N-SP and P-SP and a top surface of the pillar insulation layer PIS, and the side surfaces of the power pad PP and the ground pad GP may be surrounded by the first upper interlayer insulation layer160.

A common source area CSA may extend in the first direction x in parallel with the stacked structures ST, and may be formed by doping the substrate101with impurities. A common source plug CSP may be connected to the common source area CSA between the stacked structures ST. InFIG.2A, the common source area CSA may be arranged under a common source plug CSP in the third direction z. The common source area CSA may constitute a part of the common source line CSL. An insulation spacer IS may be arranged on opposite side surfaces of the common source plug CSP. For example, the insulation spacer IS may be between the common source plug CSP and the stacked structures ST. According to an embodiment of the inventive concept, the common source plug CSP may be arranged in a part on the common source area CSA, and an isolating insulation layer may be arranged on the common source plug CSP. The common source plug CSP, the insulation spacer IS, the isolating insulation layer, etc., may be arranged in the above-described isolation area.

The first upper interlayer insulation layer160may be arranged on the planarizing insulation layer150in the extension area EA. The first upper interlayer insulation layer160may constitute an interlayer insulation layer ILD in the cell array area CAA, and may cover a top surface of the vertical channel structure VCS and the top surfaces of the semiconductor pillars N-SP and P-SP. The second upper interlayer insulation layer170may be arranged on the first upper interlayer insulation layer160.

In the extension area EA, the vertical contact VC may contact the electrode pad ELp of the gate electrode layer EL by passing through the first and second upper interlayer insulation layers160and170and the planarizing insulation layer150. A vertical length, i.e., a length in the third direction z, of the vertical contact VC may decrease toward the cell array area CAA. Top surfaces of the vertical contacts VC may be formed on substantially the same plane.

A sub bit line SBL may be arranged on the second upper interlayer insulation layer170in the cell array area CAA, and may be electrically connected to the vertical channel structure VCS through the bit line contact plug BCP. A sub power line SPL and a sub ground line SGL may be arranged on the second upper interlayer insulation layer170in the cell array area CAA, and may be electrically connected to the semiconductor pillars N-SP and P-SP through the power contact plug PCP and the ground contact plug GCP. In the extension area EA, a gate connection line GCL may be arranged on the second upper interlayer insulation layer170and may be electrically connected to the electrode pad ELp through the vertical contact VC.

A third upper interlayer insulation layer180may be arranged on the second upper interlayer insulation layer170and may cover the sub bit line SBL, the sub power line SPL and the sub ground line SGL, and the gate connection line GCL. The bit line BL, a power line VDDL, and a ground line GNDL may be arranged on the third upper interlayer insulation layer180, and may extend in the second direction y across the stacked structure ST. Although not shown, the bit lines BL may be connected to the sub bit lines SBL through a contact, and the power line VDDL and the ground line GNDL may be respectively connected to the sub power line SPL and the sub ground line SGL through a contact. According to an embodiment of the inventive concept, the power line VDDL and the ground line GNDL may be directly and respectively connected to the sub power line SPL and the sub ground line SGL without a separate contact.

When the thermoelectric device120operates, power may be applied to the N-type semiconductor pillar N-SP through the power line VDDL, the sub power line SPL, the power contact plug PCP, and the power pad PP, and the ground may be applied to the P-type semiconductor pillar P-SP through the ground line GNDL, the sub ground line SGL, the ground contact plug GCP, and the ground pad GP. Meanwhile, a connection structure of the semiconductor pillars N-SP and P-SP with the power line VDDL and the ground line GNDL may vary according to an arrangement structure of the semiconductor pillars N-SP and P-SP. The connection structure of the semiconductor pillars N-SP and P-SP with the power line VDDL and the ground line GNDL will be described in more detail with reference toFIGS.5A and5B.

Contacts and lines PP, GP, PCP, GCP, SPL, SGL, VDDL, and GNDL on the semiconductor pillars N-SP and P-SP may have substantially the same structure as the contacts and the lines BP, BCP, SBL, and BL on the vertical channel structure VCS except that the power line VDDL and the ground line GNDL are isolated from each other. In a simplification of a process, the contacts and the lines PP, GP, PCP, GCP, SPL, SGL, VDDL, and GNDL on the semiconductor pillars N-SP and P-SP are formed when the contacts and the lines BP, BCP, SBL, and BL on the vertical channel structure VCS are formed. However, according to an embodiment of the inventive concept, the contacts and the lines on the semiconductor pillars N-SP and P-SP may be formed separately from the contacts and the lines BP, BCP, SBL, and BL on the vertical channel structure VCS. In this case, at least two adjacent ones among the power pad PP, the power contact plug PCP, and the sub power line SPL may be formed as one contact structure by being integrally connected to each other. Also, at least two adjacent ones among the ground pad GP, the ground contact plug GCP and the sub ground line SGL may be formed as one contact structure by being integrally connected to each other. For example, the power pad PP, the power contact plug PCP, and the sub power line SPL may be formed as one integrated contact, the power line VDDL may be directly connected to the N-type semiconductor pillar N-SP through the integrated contact. Also the ground pad GP, the ground contact plug GCP, and the sub ground line SGL may be formed as one integrated contact, the ground line GNDL may be directly connected to the P-type semiconductor pillar P-SP through the integrated contact.

The memory device100according to the current embodiment of the inventive concept may have a multi-stack structure formed through a multi-stack process. Herein, the multi-stack process may be a process in which as the height of the vertical non-volatile memory device in the vertical direction increases, it becomes difficult to form holes passing through a mold structure to the substrate at one time, such that a mold structure is formed in a divided manner two or more times and a through-hole for a vertical channel structure and the vertical channel structure are formed in a divided manner for each mold structure. When the memory device100according to the current embodiment of the inventive concept has a multi-stack structure, the semiconductor pillars N-SP and P-SP may be formed in a divided manner for each mold structure like the vertical channel structure.

FIGS.3A through3Care conceptual views for describing a heat dissipation operation using a thermoelectric device in the memory device ofFIG.2A.

Referring toFIGS.3A through3C, in general, the thermoelectric device may be any device using various effects obtained by interaction between heat and electricity. The thermoelectric device may include a thermistor device which is a device using a temperature change of an electric resistance, a device using a Seebeck effect which is a phenomenon where an electromotive force is generated by a temperature difference, a Peltier device using the Peltier effect which is a phenomenon where absorption (or generation) of heat occurs by electric current, etc.

The Peltier effect is a phenomenon where when two types of metals are connected and current flows therethrough, heat absorption occurs in a terminal of a side and heat generation occurs in a terminal of the other side depending on the direction of the current. Semiconductors such as bismuth, tellurium, etc., having different electric conduction schemes may be used. Alternatively, a P-type semiconductor and an N-type semiconductor may be used, in place of the two types of the metals, and a Peltier device having high efficiency may be implemented through combinations of various semiconductors. The Peltier device is capable of switching between heat absorption and heat generation depending on the direction of the current, and adjusting the amount of heat absorption and the amount of heat generation according to the amount of current. The Peltier device may thus be applicable to manufacturing of a cooling device (e.g., a refrigerator) with a small capacity or a thermostat.

In the memory device100according to the current embodiment of the inventive concept, the thermoelectric device120may be a Peltier device using the Peltier effect. The thermoelectric device120may correspond to a thermoelectric cooler (TEC) that absorbs heat in a certain part through voltage application and dissipates heat to the outside.

Describing in more detail an operation of the TEC that is a thermoelectric device with reference toFIG.3A, the TEC may include a P-type semiconductor P-S and an N-type semiconductor N-S which may be electrically connected to each other by contacting the conductive layer CL through an end of any one side, e.g., a lower end thereof. The conductive layer CL may include, for example, metal. However, a material of the conductive layer CL is not limited to metal. For example, the conductive layer CL may include semiconductor, metal oxide, metal silicide, etc., having conductivity. When the TEC operates, a target portion TP, which is a cooling target, may be arranged adjacent to the conductive layer CL, and the P-type semiconductor P-S and the N-type semiconductor N-S may be connected to the power source and the ground through an end of the other side, e.g., a top end thereof. More specifically, the P-type semiconductor P-S may be connected to the ground, and the N-type semiconductor N-S may be connected to the power source. Based on such a connection relationship, carriers of the N-type semiconductor N-S, i.e., electrons, may move to the power source and carriers of the P-type semiconductor P-S, i.e., holes, may move to the ground. Heat may be absorbed in the target portion TP for cooling due to movement of the carriers, and heat may be dissipated by being transferred to the power source and the ground through the P-type semiconductor P-S and the N-type semiconductor N-S.

FIG.3Bconceptually shows the thermoelectric device120that operates as the TEC in the memory device100according to the current embodiment of the inventive concept. More specifically, the thermoelectric device120may include an N-type semiconductor pillar N-SP and a P-type semiconductor pillar P-SP. The N-type semiconductor pillar N-SP and the P-type semiconductor pillar P-SP may extend in a cylindrical shape passing through the stacked structure ST on the substrate101. Each of the N-type semiconductor pillar N-SP and the P-type semiconductor pillar P-SP may contact, through a lower end thereof, a common source line105corresponding to the conductive layer. Thus, the N-type semiconductor pillar N-SP and the P-type semiconductor pillar P-SP may be electrically connected to each other through the common source line105. The substrate101may be arranged under the common source line105.

When the thermoelectric device120operates, the N-type semiconductor pillar N-SP may be connected to the power source VDD through a first internal connection line 1st-INC and the P-type semiconductor pillar P-SP may be connected to the ground GND through a second internal connection line 2nd-INC. Describing a relationship of line connection to the outside of a chip with reference toFIG.8, the first internal connection line 1st-INC may be connected to the power source VDD of a main board through a chip pad190of the memory device100, an external connection line300, a substrate pad210, an internal line220of a package substrate200, and an external connection terminal250, and the second internal connection line 2nd-INC may be connected to the ground GND of the main board through the chip pad190of the memory device100, the external connection line300, the substrate pad210, the internal line220of the package substrate200, and the external connection terminal250. Herein, the first internal connection line 1st-INC may include, for example, the power pad PP, the power contact plug PCP, the sub power line SPL, and the power line VDDL, and the second internal connection line 2nd-INC may include, for example, the ground pad PGP, the ground contact plug GCP, the sub ground line SGL, and the ground line GNDL.

Based on the arrangement and connection relationship of the thermoelectric device120, as can be seen inFIG.3C, the thermoelectric device120may absorb heat of the substrate101and the common source line105, i.e., a heat absorption part (H.A.P.), perform heat transfer (H.T.) through the semiconductor pillars N-SP and P-SP, and release heat through the first and second internal connection lines 1st-INC and 2nd-INC, i.e., a heat release part (H.R.P.), thereby cooling the substrate101and the common source line105. The thermoelectric device120may also release heat of the stacked structure ST adjacent to side surfaces of the semiconductor pillars N-SP and P-SP as well as heat of the substrate101and the common source line105corresponding to the H.A.P., for cooling.

Heat release in the H.R.P. side may occur more actively in the outside of the chip than in the first and second internal connection lines 1st-INC and 2nd-INC inside the chip. For example, an external connection terminal (see250ofFIG.8) such as a solder ball arranged on a bottom surface of a package substrate (see200ofFIG.8) connected to the power source VDD and the ground GND may be connected to a substrate having a wide contact area with an air, and thus, heat release may relatively actively occur therein.

FIGS.4A and4Bare perspective views of a vertical channel structure and a thermoelectric device in the memory device ofFIG.2A. A description already made with reference toFIGS.1through3Cwill be simplified or omitted.

Referring toFIG.4A, in the memory device100according to the current embodiment of the inventive concept, the vertical channel structure VCS may have a cylindrical shape passing through the stacked structure ST. However, the shape of the vertical channel structure VCS is not limited to a cylindrical shape. For example, the vertical channel structure VCS may have a polygonal or elliptic cylindrical shape. Although the stacked structure ST is illustrated inFIG.4Ain the shape of a circular tube for convenience, actually, the stacked structure ST may be a structure in which the plurality of gate electrode layers EL and the plurality of interlayer insulation layers ILD are stacked alternately in the third direction z and extend in the first direction x and in the second direction y, as shown inFIG.2B.

The vertical channel structure VCS may include the upper semiconductor pattern USP, the data storage pattern VP, and the buried insulation pattern VI. As shown inFIG.4A, the buried insulation pattern VI may have a cylindrical shape and each of the upper semiconductor pattern USP and the data storage pattern VP may have a circular tube shape.

The data storage pattern VP may include ONO insulation layers, e.g., a first oxide insulation layer IO1, a nitride insulation layer IN, and a second oxide insulation layer102. Each of the first oxide insulation layer IO1, the nitride insulation layer IN, and the second oxide insulation layer IO2may have a circular tube shape. The first oxide insulation layer IO1and the second oxide insulation layer IO2may be formed of, e.g., silicon oxide SiO2, and the nitride insulation layer IN may be formed of, e.g., silicon nitride SiNx. The shapes and materials of the first oxide insulation layer IO1, the second oxide insulation layer IO2, and the nitride insulation layer IN are not limited to the above-described shapes and materials.

Referring toFIG.4B, in the memory device100according to the current embodiment of the inventive concept, the semiconductor pillars N-SP and P-SP may have a cylindrical shape passing through the stacked structure ST. However, the shape of the semiconductor pillars N-SP and P-SP is not limited to a cylindrical shape. For example, the semiconductor pillars N-SP and P-SP may have a polygonal or elliptic cylindrical shape. InFIG.4B, the stacked structure ST is illustrated in the shape of a circular tube for convenience.

The side surfaces of the semiconductor pillars N-SP and P-SP may be surrounded by the pillar insulation layer PIS. For example, the pillar insulation layer PIS may have a circular tube shape surrounding the side surfaces of the semiconductor pillars N-SP and P-SP. Thus, the semiconductor pillars N-SP and P-SP may be electrically insulated from the gate electrode layers EL of the stacked structure ST by the pillar insulation layer PIS.

The semiconductor pillars N-SP and P-SP may be formed through a process that is similar to that of the vertical channel structure VCS. For example, through-holes for the semiconductor pillars N-SP and P-SP may be formed and filled with the pillar insulation layer PIS and a material layer for the semiconductor pillars N-SP and P-SP, thereby forming the semiconductor pillars N-SP and P-SP. Herein, the pillar insulation layer PIS may be formed of, for example, silicon oxide SiO2. However, a material of the pillar insulation layer PIS is not limited thereto. The semiconductor pillars N-SP and P-SP and the vertical channel structure VCS may be formed through different processing phases because of different material layers. However, according to an embodiment of the inventive concept, the through-hole for the vertical channel structure VCS and the through-holes for the semiconductor pillars N-SP and P-SP may be formed through the same process phase.

FIGS.5A and5Bare perspective views of a line connection structure in a top end of a thermoelectric device in the memory device ofFIG.2A. A description already made with reference toFIGS.1through4Bwill be simplified or omitted.

Referring toFIG.5A, in the memory device100according to the current embodiment of the inventive concept, the vertical channel structure VCS may be connected to the bit line BL through a bit line connection line INCb, and the semiconductor pillars N-SP and P-SP may be connected to the power line VDDL and the ground line GNDL through the first and second lower connection lines 1st-INCI and 2nd-INCI. In the extension area EA, the gate connection line GCL may be connected to the electrode pad ELp including the gate electrode layer EL of the stacked structure ST through the vertical contact VC.

The bit line connection line INCb may include, for example, the bit line electrode pad BP, the bit line contact plug BCP, the sub bit line SBL, etc. InFIG.5A, for convenience, the bit line connection line INCb is illustrated simply in the shape of a pillar. The first and second lower connection lines 1st-INCI and 2nd-INCI may include the power and ground pads PP and GP, the power and ground contact plugs PCP and GCP, the sub power and sub ground lines SPL and SGL, etc.

In the memory device100, according to the current embodiment of the inventive concept, the semiconductor pillars N-SP and P-SP may be arranged alternately in the second direction y. The N-type semiconductor pillar N-SP may be connected to the power line VDDL through a first lower connection line 1st-INCI, and the P-semiconductor pillar P-SP may be connected to the ground line GNDL through the second lower connection line 2nd-INCI. As shown inFIG.5A, the power line VDDL may be arranged in a position lower than the ground line GNDL in the third direction z. Thus, a contact on a top part of the second lower connection line 2nd-INCI may be longer than that of the first lower connection line 1st-INCI, or the second lower connection line 2nd-INCI may further include an additional contact. The first lower connection line 1st-INCI may include a side connection line INCs connected to the power line VDDL in a side surface direction. According to an embodiment of the inventive concept, the power line VDDL may be arranged in a position higher than the ground line GNDL in the third direction z. In this case, the first lower connection line 1st-INCI may include the side connection line INCs connected to the ground line GNDL in the side surface direction.

In the memory device100according to the current embodiment of the inventive concept, the N-type semiconductor pillar N-SP and the P-type semiconductor pillar P-SP may be arranged alternately in the second direction y. However, as the power line VDDL and the ground line GNDL are arranged to different heights in the third direction z, the N-type semiconductor pillar N-SP may be connected in common to the power line VDDL and the P-type semiconductor pillar P-SP may be connected in common to the ground line GNDL. As a result, in the memory device100according to the current embodiment of the inventive concept, as the thermoelectric device120including a pair of the N-type semiconductor pillar N-SP and the P-type semiconductor pillar P-SP is arranged in plural in the second direction y, a heat dissipation effect obtained by the thermoelectric device120may be uniform and maximized over the entire cell array area CAA.

Referring toFIG.5B, a memory device100aaccording to the current embodiment of the inventive concept may be different from the memory device100ofFIG.5Ain that the N-type semiconductor pillar N-SP and the P-type semiconductor pillar P-SP are arranged collectively for the same conductive type in the second direction y, and the power line VDDL and the ground line GNDL are arranged in substantially the same position in the third direction z. More specifically, in the memory device100aaccording to the current embodiment of the inventive concept, the power line VDDL and the ground line GNDL may be arranged in substantially the same position in the third direction z, the N-type semiconductor pillar N-SP may be connected to the power line VDDL through the first lower connection line 1st-INCI, and the P-semiconductor pillar P-SP may be connected to the ground line GNDL through the second lower connection line 2nd-INCI. The first lower connection line 1st-INCI and the second lower connection line 2nd-INCI may have substantially the same line structure. For example, the first lower connection line 1st-INCI may include, for example, the power pad PP, the power contact plug PCP, the sub power line SPL, etc., and the second lower connection line 2nd-INCI may include, for example, the ground pad GP, the ground contact plug GCP, the sub ground line SGL, etc.

In the memory device100aaccording to the current embodiment of the inventive concept, the N-type semiconductor pillar N-SP and the P-type semiconductor pillar P-SP may be arranged collectively for the same conductive type in the second direction y. Based on the arrangement structure of the semiconductor pillars N-SP and P-SP, the power line VDDL and the ground line GNDL may be arranged to substantially the same height in the third direction z, and the N-type semiconductor pillar N-SP may be connected in common to the power line VDDL and the P-type semiconductor pillar P-SP may be connected in common to the ground line GNDL. As a result, in the memory device100aaccording to the current embodiment of the inventive concept, the entire N-type semiconductor pillar N-SP and the entire P-type semiconductor pillar P-SP may constitute one thermoelectric device120. In addition, in the memory device100aaccording to the current embodiment of the inventive concept, the power line VDDL and the ground line GNDL may be arranged in substantially the same position in the third direction z and the first lower connection line 1st-INCI and the second lower connection line 2nd-INCI may have substantially the same line structure, such that the line structure may be simplified and thus a wiring process on the semiconductor pillars N-SP and P-SP may be facilitated.

FIGS.6A and6Bare cross-sectional views of a memory device according to embodiments of the inventive concept. A description already made with reference toFIGS.1through5Bwill be simplified or omitted.

Referring toFIG.6A, a memory device100baccording to the current embodiment of the inventive concept may be different from the memory device100ofFIG.1in further including a temperature sensor130in the substrate101. More specifically, in the memory device100baccording to the current embodiment of the inventive concept, the temperature sensor130based on a P-N diode may be arranged in the substrate101. In general, an I-V graph of the P-N diode may vary with a temperature. More specifically, a current or slope at a certain voltage of the I-V graph of the P-N diode may vary according to temperature. Thus, by quantizing the current or slope at a certain voltage of the I-V graph of the P-N diode according to temperature, the temperature may be measured through the P-N diode. For example, inFIG.6A, by applying a voltage to the temperature sensor130based on the P-N diode through an upper vertical contact VCU and the substrate101and detecting current, the temperature of a part of the substrate101in which the temperature sensor130is arranged may be measured.

Referring toFIG.6B, a memory device100caccording to the current embodiment of the inventive concept may be different from the memory device100bofFIG.6Ain that a temperature sensor130abased on a P-N diode is arranged in a part of the stacked structure ST. More specifically, in the memory device100caccording to the current embodiment of the inventive concept, the temperature sensor130abased on the P-N diode may be arranged in the stacked structure ST. An operation principle of the temperature sensor130ais the same as described with reference toFIG.6A. By applying a voltage to the temperature sensor130athrough the upper vertical contact VCU, the substrate101, and the lower vertical contact VCD and detecting current, the temperature of the part of the stacked structure ST in which the temperature sensor130ais arranged may be measured.

The memory device according to the current embodiment of the inventive concept may control the thermoelectric device120by using the temperature sensors130and130abased on a P-N diode ofFIGS.6A and6B. However, in the memory device according to the current embodiment of the inventive concept, the temperature sensor may not be limited to the temperature sensor based on a P-N diode. A position in which the temperature sensor is arranged may not be limited to the ones illustrated inFIGS.6A and6B. For example, in the memory device according to the current embodiment of the inventive concept, various types of temperature sensors may be arranged in various positions of the memory device to measure temperature, thereby controlling the thermoelectric device120.

FIG.7is a cross-sectional view of a memory device according to an embodiment of the inventive concept. A description already made with reference toFIGS.1through6Bwill be simplified or omitted.

Referring toFIG.7, a memory device100daccording to the current embodiment of the inventive concept may include a cell area CA and a peripheral circuit area PCA. The cell area CA may include, for example, the cell array area CCA and the extension area EA of the memory device100ofFIG.2A. Thus, inFIG.7, a part corresponding to the cell area CA may be substantially the same as the portion I-I′, the portion II-II′, and the portion III-III′ ofFIG.2A. The structure of the cell area CA of the memory device100daccording to the current embodiment of the inventive concept is not limited to the structure of the cell area CA of the memory device100ofFIG.2A.

In the memory device100daccording to the current embodiment of the inventive concept, the peripheral circuit area PCA may be arranged under the substrate101of the cell area CA. In other words, the cell area CA may be stacked on the peripheral circuit area PCA. Thus, the peripheral circuit area PCA and the cell area CA may overlap each other. Likewise, the structure or memory device in which the cell area CA is arranged on the peripheral circuit area PCA may be referred to as a cell on Peri (COP) structure or COP memory device. For reference, in the vertical non-volatile memory device100ofFIG.2A, the peripheral circuit area may be arranged near the cell area on a top surface FS of the substrate101in the horizontal direction.

The peripheral circuit area PCA may be formed on a base substrate205. The base substrate205may be as described above regarding the substrate101of the vertical non-volatile memory device100ofFIG.2A. The base substrate205may include an n-well area NW doped with n-type impurities and a p-well area PW doped with p-type impurities. In the n-well area NW and the p-well area PW, active areas may be defined by a device isolation layer215.

In the peripheral circuit area PCA, a high-voltage and/or low-voltage transistor and a passive element such as a resistor, a capacitor, etc., may be arranged. More specifically, the peripheral circuit area PCA may include a peripheral circuit gate electrode PG, a source/drain area S/D, a peripheral circuit plug PCP, a peripheral circuit line ICL, and a lower buried insulation layer225. The lower buried insulation layer225may be formed as a single layer or multiple layers. A p-channel metal-oxide semiconductor (PMOS) transistor may be formed on the n-well area NW and an n-channel MOS (NMOS) transistor may be formed on the p-well area PW.

Although not shown, a through-via line area may be arranged in the cell array area CAA or the extension area EA. A through-via may be formed in the through-via line area, and lines on the cell array area CAA or the extension area EA may be connected to lines of the peripheral circuit area PCA through the through-via. In addition, the substrate101may be formed of polysilicon. For example, a substrate trench area may be formed in an upper portion of the lower buried insulation layer225and the trench area may be filled with polysilicon, thus forming the substrate101. As such, when the substrate101is formed of polysilicon, the peripheral circuit area PCA may be formed on the lower base substrate205and the substrate101may be formed in the lower buried insulation layer225. Thereafter, the cell array area CAA and the extension area EA may be formed on the substrate101and the through-via may be formed in the through-via line area, thus implementing a COP structure.

FIG.8is a cross-sectional view of a semiconductor package including a vertical non-volatile memory device according to an embodiment of the inventive concept. A description will be made with reference toFIGS.1through2Btogether and a description already made with reference toFIGS.1through7will be simplified or omitted.

Referring toFIG.8, a semiconductor package1000including a vertical non-volatile memory device according to the current embodiment of the inventive concept (hereafter, simply referred to as a ‘semiconductor package’) may include the package substrate200, the semiconductor chip100, the external connection line300, and a sealant400.

The package substrate200may include a body layer201, the substrate pad210, and the internal line220. The body layer201may be formed of various materials. For example, the body layer201may be formed of silicon, ceramic, an organic material, glass, epoxy resin, etc., according to a type of the package substrate200. In the semiconductor package1000according to the current embodiment of the inventive concept, the package substrate200may be a printed circuit board (PCB) based on epoxy resin. The internal line220may be arranged in the body layer201and may be formed as a single layer or multiple layers. The substrate pad210may be electrically connected to the external connection terminal250on the bottom surface through the internal line220. A protection layer such as a solder resist SR may be formed on a top surface and a bottom surface of the body layer201.

The external connection terminal250may be arranged on a bottom surface of the package substrate200. The external connection terminal250may be formed of, for example, a solder ball. The external connection terminal250may include data signal terminals, command/address signal terminals, and power/ground terminals. The data signal terminals and the command/address terminals may be arranged separately for each area on the bottom surface of the package substrate200. The power/ground terminals may be arranged more or less randomly between the data signal terminals and the command/address signal terminals on the bottom surface of the package substrate200. The external connection terminal250may include dummy connection terminals that do not function electrically. The dummy connection terminals may be arranged for warpage improvement, heat dissipation, additional power/ground application, etc., of the package substrate200.

The semiconductor chip100may be the memory device100ofFIG.2A. Thus, the semiconductor chip100may include the thermoelectric device120in the cell array area CAA. However, the semiconductor chip100may not be limited to the memory device100ofFIG.2A. For example, the semiconductor chip100may be any one of the memory devices100athrough100dofFIGS.5B through7.

The semiconductor chip100may be stacked in plural on the package substrate200. For example, eight semiconductor chips100may be stacked on the package substrate200. However, the number of semiconductor chips100stacked on the package substrate200is not limited to 8. For example, one or more semiconductor chips100may be stacked in multiple stages on the package substrate200.

The semiconductor chip100may be fixed by being stacked on the package substrate200and the corresponding lower semiconductor chip100through an adhesive layer195such as a die attach film (DAF) or a non-conductive film (NCR). In addition, the semiconductor chip100may be mounted as a wire bonding structure on the package substrate200. Thus, in the semiconductor chip100, an active surface may be directed upward and the chip pad190may be exposed upward.

To expose the chip pad190upward, the semiconductor chip100may be stacked as a step structure in the first direction x. For example, as shown inFIG.8, each of first through fifth semiconductor chips100may stacked to the right by a certain distance and each of sixth through eighth semiconductor chips100may be stacked to the left by the certain distance. As the semiconductor chips100are stacked in a step structure or a cascade structure, the first through fourth semiconductor chips100may be wire-bonded through a left side and the fifth through eighth semiconductor chips100may be wire-bonded through a right side.

The external connection line300may electrically connect the semiconductor chips100to the package substrate200. The external connection line300may be, for example, a bonding wire, and connect the chip pad190of the semiconductor chip100to the substrate pad210of the package substrate200.

The sealant400may seal the semiconductor chips100to protect the semiconductor chips100from an external physical and electrical shock. The sealant400may be formed of polymer such as resin. For example, the sealant400may be formed of an epoxy molding compound (EMC).

In the semiconductor package1000according to the current embodiment of the inventive concept, the semiconductor chip100may include the thermoelectric device120therein and perform heat dissipation in a chip level through the thermoelectric device120, thereby stably maintaining the operating temperature of the memory device in the chip level. In the semiconductor package1000according to the current embodiment of the inventive concept, a heat dissipation path based on the thermoelectric device120may be as described below. For example, the N-type semiconductor pillar N-SP of the thermoelectric device120may be connected to the chip pad190through the first internal connection line 1st-INC, and the chip pad190may be connected to the power source VDD through the external connection line300, the substrate pad210, the internal line220of the package substrate200, and the external connection terminal250. The P-type semiconductor pillar P-SP of the thermoelectric device120may be connected to the chip pad190through the second internal connection line 2nd-INC, and the chip pad190may be connected to the ground GND through the external connection line300, the substrate pad210, the internal line220of the package substrate200, and the external connection terminal250. Based on such a connection relationship of the thermoelectric device120, heat may be transferred toward the power source VDD and the ground GND, such that heat dissipation may occur beyond the N-type semiconductor pillar N-SP and the P-type semiconductor pillar P-SP and in particular, much heat dissipation may occur in the external connection terminal250contacting the air.

The first internal connection line 1st-INC and the second internal connection line 2nd-INC have been separately described, but the chip pad190, the external connection line300, the substrate pad210, the internal line220of the package substrate200, and the external connection terminal250may also be separated as a group connected to the first internal connection line 1st-INC and a group connected to the second internal connection line 2nd-INC. As will be described in the following description to be made with reference toFIGS.10A and10B, according to an embodiment of the inventive concept, at least one of the chip pad190, the external connection line300, the substrate pad210, the internal line220of the package substrate200, or the external connection terminal250may be a dummy element. Herein, the dummy element may mean lines, pads, and terminals capable of supplying power and ground regardless of an operation of a memory of the cell array area.

FIGS.9A through10Bare cross-sectional views of a semiconductor package according to embodiments of the inventive concept. A description will be made with reference toFIGS.1through2Btogether and a description already made with reference toFIG.8will be simplified or omitted.

Referring toFIG.9A, a semiconductor package1000aaccording to the current embodiment of the inventive concept may be different from the semiconductor package1000ofFIG.8in view of a stacked structure of the semiconductor chip100. More specifically, in the semiconductor package1000aaccording to the current embodiment of the inventive concept, the semiconductor chips100may be stacked in a zigzag structure in the first direction x. As the semiconductor chips100are stacked in the zigzag structure, the first, third, fifth, and seventh semiconductor chips100may be wire-bonded through a left side and the second, fourth, sixth, and eighth semiconductor chips100may be wire-bonded through a right side.

When the semiconductor chips100has a rectangular structure having a longer side and the chip pad190is arranged in opposite short sides, the semiconductor chips100may be stacked by being arranged alternately in a cross shape, thereby implementing a wire-bonding structure.

Referring toFIG.9B, a semiconductor package1000baccording to the current embodiment of the inventive concept may be different from the semiconductor package1000ofFIG.8in that a semiconductor chip100eincludes a through electrode107therein, through which the semiconductor chip100eis electrically connected to the package substrate200. More specifically, in the semiconductor package1000baccording to the current embodiment of the inventive concept, the semiconductor chip100emay include the through electrode107and may be mounted on the package substrate200and the corresponding lower semiconductor chip100ethrough a minute bump103and the adhesive layer195. In the semiconductor chip100e, an active surface may be directed downward and the chip pad190may be directed downward. The semiconductor chip100emay be electrically connected to the package substrate200through the through electrode107and the minute bump103.

In the semiconductor package1000baccording to the current embodiment of the inventive concept, four semiconductor chips100eare stacked, but the number of semiconductor chips100estacked on the package substrate200is not limited to 4. For example, one through three, or five or more semiconductor chips100emay be stacked on the package substrate200. As shown inFIG.9B, the semiconductor chip100earranged on a top portion may not include a through electrode.

In the semiconductor package1000baccording to the current embodiment of the inventive concept, the semiconductor chip100emay include the thermoelectric device120which may be connected to a substrate pad of the package substrate200through the through electrode107and the minute bump103. In the semiconductor package1000baccording to the current embodiment of the inventive concept, a heat dissipation path based on the thermoelectric device120may be as described below. For example, the N-type semiconductor pillar N-SP of the thermoelectric device120may be connected to the chip pad through the first internal connection line 1st-INC, and the chip pad may be connected to the power source VDD through the through electrode107and the minute bump103, the substrate pad, the internal line of the package substrate200, and the external connection terminal250. In addition, the P-type semiconductor pillar P-SP of the thermoelectric device120may be connected to the chip pad through the second internal connection line 2nd-INC, and the chip pad may be connected to the ground GND through the through electrode107and the minute bump103, the substrate pad, the internal line of the package substrate200, and the external connection terminal250. Based on such a connection relationship of the thermoelectric device120, heat may be transferred to the power source VDD and the ground GND.

Referring toFIG.10A, a semiconductor package1000caccording to the current embodiment of the inventive concept may be different from the semiconductor package1000ofFIG.8in further including a switching element SW. More specifically, in the semiconductor package1000caccording to the current embodiment of the inventive concept, the switching element SW may be arranged on the package substrate200. The substrate pad210may be connected to the internal line220of the package substrate200through the switching element SW. The external connection line300may be selectively connected to the external connection terminal250connected to the power source VDD and the ground GND by switching of the switching element SW. As a result, the external connection line300, the chip pad190, etc., connected to the power source VDD and the ground GND through the switching element SW, may correspond to dummy elements.

While it is described with reference toFIG.10Athat the switching element SW is arranged on the package substrate200to connect the substrate pad210with the internal line220, the switching element SW may be in various spots such that elements connected through the switching element SW may correspond to dummy elements. The switching element SW may be arranged outside the semiconductor package and in this case, the external connection terminal250through to the chip pad190may correspond to the dummy elements.

The switching element SW may operate by a temperature measured by a temperature sensor (see130ofFIG.6A) arranged inside the semiconductor chip100. For example, when the temperature measured by the temperature sensor130exceeds the reference temperature, the switching element SW may operate such that the power source VDD and the ground GND may be connected to the semiconductor pillars N-SP and P-SP.

Referring toFIG.10B, a semiconductor package1000daccording to the current embodiment of the inventive concept may be different from the semiconductor package1000ofFIG.8in further including a voltage regulator VR. More specifically, in the semiconductor package1000daccording to the current embodiment of the inventive concept, the voltage regulator VR may be arranged on the package substrate200. The voltage regulator VR may regulate a voltage level to a desired level. The voltage regulator VR may include, for example, a control circuit and a switching logic circuit. The control circuit may include a plurality of transistors for voltage regulation, and the switching logic circuit may include at least two transistors for selecting a path of electric current. The switching logic circuit of the voltage regulator VR may function as the switching element SW ofFIG.10A. The semiconductor package1000daccording to the current embodiment of the inventive concept may include the voltage regulator VR to apply power of appropriate voltage to the thermoelectric device120for optimal heat dissipation.

FIG.11is a flowchart illustrating a heat dissipation method of a vertical non-volatile memory device, according to an embodiment of the inventive concept. A description will be made with reference toFIGS.1through2Btogether and a description already made with reference toFIGS.1through7will be simplified or omitted.

Referring toFIG.11, in a heat dissipation method of a vertical non-volatile memory device (hereinafter, simply referred to as a ‘heat dissipation method’) according to the current embodiment of the inventive concept, the memory device100may determine whether to maintain an operation of the thermoelectric device120in operation S110. Herein, the memory device100, which is the memory device100ofFIG.2A, may include the thermoelectric device120in the cell array area CAA. Operation of the thermoelectric device120may be determined based on various causes such as amount of use (or non-use) of the memory device100or an operating age of the memory device100in a home appliance, a defect of the memory device100, etc.

When the thermoelectric device120maintains the operation in S110(Yes), a first temperature of the substrate101and/or the stacked structure ST may be measured through the temperature sensor (see130ofFIG.6A) in operation S120. When the thermoelectric device120does not maintain the operation in S110(No), a heat dissipation operation may be terminated by the thermoelectric device120to finish the heat dissipation method.

After the first temperature is measured in operation S120, it is determined whether the first temperature exceeds the reference temperature in operation S130. Herein, the reference temperature may be determined based on an operating temperature of the memory device100, a maximum allowable temperature, etc. When the first temperature exceeds the reference temperature (Yes) in operation S130, the thermoelectric device120may be turned on in operation S140. For example, the power source VDD may be connected to the N-type semiconductor pillar N-SP of the thermoelectric device120and the ground GND may be connected to the P-type semiconductor pillar P-SP, thereby performing a heat dissipation operation. Connection between the power source VDD and the ground GND may be performed through the switching element (see SW ofFIG.10A). As the thermoelectric device120is turned on, the substrate101and/or the stacked structure ST may be heat-dissipated and cooled such that the temperature of the substrate101and/or the stacked structure ST may decrease. When the first temperature is less than or equal to the reference temperature (No) in operation S130, the operation S110of determining whether to maintain the operation of the thermoelectric device120may be performed.

After the thermoelectric device120is turned on in operation S140, a second temperature of the substrate101and/or the stacked structure ST may be measured through the temperature sensor130after a set first time period in operation S150. Herein, the first time period may be set based on performance and temperature decreasing speed of the thermoelectric device120, for example. After the second temperature is measured in operation S150, it is determined whether the second temperature is less than or equal to the reference temperature in operation S160. When the second temperature is less than or equal to the reference temperature (Yes) in operation S160, the thermoelectric device120may be turned off in operation S170. For example, connection of the power source VDD to the N-type semiconductor pillar N-SP of the thermoelectric device120and connection of the ground GND to the P-type semiconductor pillar P-SP may be released (i.e., disconnected). Disconnection of the power source VDD and the ground GND from the semiconductor pillars N-SP and P-SP may also be made by the switching element SW. According to an embodiment of the inventive concept, the reference temperature to be compared with the second temperature may be set lower than the reference temperature to be compared with the first temperature. After the thermoelectric device120is turned off, the operation S110of determining whether to maintain the operation of the thermoelectric device120may be performed. When the second temperature exceeds the reference temperature (No), the operation S150of measuring the second temperature may be performed.

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the principles of the present disclosure.