Patent ID: 12219763

DETAILED DESCRIPTION

FIG.1illustrates an equivalent circuit diagram of a memory cell array of an integrated circuit device, according to example embodiments.FIG.1illustrates an equivalent circuit diagram of a vertical NAND flash memory device having a vertical channel structure.

Referring toFIG.1, a memory cell array MCA may include a plurality of memory cell strings MS. The memory cell array MCA may include first through mthbit lines BL1through BLm, first through nthword lines WL1through WLn, at least one string selection line SSL, at least one ground selection line GSL, and a common source line CSL. The plurality of memory cell strings MS may be formed between the first through mthbit lines BL1through BLm and the common source line CSL.

Each of the plurality of memory cell strings MS may include a string selection transistor SST, a ground selection transistor GST, and first through nthmemory cell transistors MC1through MCn. A conductive plug of the string selection transistor SST may be connected to the first through mthbit lines BL1through BLm, and a source region of the ground selection transistor GST may be connected to the common source line CSL. The common source line CSL may be a region where the source regions of the plurality of ground selection transistors GST are connected to each other in common.

The string selection transistor SST may be connected to the string selection line SSL, and the ground selection transistor GST may be connected to the ground selection line GSL. The first through nthmemory cell transistors MC1through MCn may be connected to the first through nthword lines WL1through WLn, respectively.

FIGS.2through11Billustrate cross-sectional views of stages in a fabrication method of an integrated circuit device according to example embodiments.FIGS.2through8,10A, and11Aillustrate cross-sectional views taken along an X-Z plane in a cell region CR and an interconnection region IR, andFIGS.9,10B, and11Billustrate cross-sectional views taken along a Y-Z plane in the cell region CR.

Referring toFIG.2, a structure may be formed in which a plurality of first insulating layers112and a plurality of first sacrificial layers PL1are alternately stacked one by one on a substrate102that has the cell region CR and the interconnection region TR. In an implementation, the substrate102may include, e.g., Si, Ge, or SiGe. In an implementation, the substrate110may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. In an implementation, the plurality of first sacrificial layers PL1may include a silicon nitride layer, and the plurality of first insulating layers112may include a silicon oxide layer.

Next, by removing a portion of the structure in which the plurality of first insulating layers112and the plurality of first sacrificial layers PL1are alternately stacked one by one in the interconnection region IR, edge portions of the structure in which the plurality of first insulating layers112and the plurality of first sacrificial layers PL1are alternately stacked one by one may be formed to have a stepwise structure in the interconnection region IR. For example, the structure in which the plurality of first insulating layers112and the plurality of first sacrificial layers PL1are alternately stacked one by one may have a roughly sloped profile in the interconnection region IR.

A first filling insulating layer172may be formed in a portion where the portion of the structure in which the plurality of first insulating layers112and the plurality of first sacrificial layers PL1are alternately stacked one by one has been removed, and a first protective insulating layer114, which covers the structure in which the plurality of first insulating layers112and the plurality of first sacrificial layers PL1are alternately stacked one by one in the cell region CR and the interconnection region IR, may be formed. In an implementation, the first protective insulating layer114may be omitted.

The first protective insulating layer114may include, e.g., silicon oxide. The first filling insulating layer172may include, e.g., silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

A first stack ST1may include a portion in which the plurality of first insulating layers112and the plurality of first sacrificial layers PL1are arranged. The first stack ST1may be referred to as a portion in which a plurality of first cell channel holes (152H inFIG.3) and a plurality of first dummy channel holes (154H inFIG.3) are formed in a vertical direction (Z direction).

Referring toFIG.3, a plurality of first cell channel holes152H penetrating through the plurality of first insulating layers112and the plurality of first sacrificial layers PL1may be formed in the cell region CR, and a plurality of first dummy channel holes154H penetrating through the first filling insulating layer172, the plurality of first insulating layers112, and the plurality of first sacrificial layers PL1may be formed in the interconnection region IR. When the first protective insulating layer114is formed on the plurality of first insulating layers112and the plurality of first sacrificial layers PL1, the plurality of first cell channel holes152H and the plurality of first dummy channel holes154H may also penetrate through the first protective insulating layer114.

The plurality of first cell channel holes152H and the plurality of first dummy channel holes154H may be formed by anisotropic etching of the first protective insulating layer114, the first filling insulating layer172, the plurality of first insulating layers112, and the plurality of first sacrificial layers PL1. The substrate102may be exposed at bottoms of the plurality of first cell channel holes152H and the plurality of first dummy channel holes154H.

The first stack ST1may indicate a portion from top ends to bottom ends of the plurality of first cell channel holes152H and the plurality of first dummy channel holes154H in the vertical direction (Z direction). The first stack ST1may include the first protective insulating layer114, the first filling insulating layer172, the plurality of first insulating layers112, and the plurality of first sacrificial layers PL1. When the plurality of first cell channel holes152H and the plurality of first dummy channel holes154H extend inwardly from a top surface of the substrate102, the first stack ST1may further include an upper portion of the substrate102.

In an implementation, the plurality of first cell channel holes152H and the plurality of first dummy channel holes154H may have a tapered shape such that widths thereof in a horizontal direction (X direction or Y direction) decrease toward (e.g., proximate or closer to) the substrate102. In an implementation, widths in the horizontal direction (the X direction or the Y direction) of the first cell channel hole152H and the first dummy channel hole154H may have maximum values below the uppermost end (e.g., mouths or openings) of each of the first cell channel hole152H and the first dummy channel hole154H, respectively, and may have decreasing values toward the substrate102from the portions having the maximum widths, respectively, due to a bowing phenomenon that could occur in the process of anisotropic etching of the first protective insulating layer114, the first filling insulating layer172, the plurality of first insulating layers112, and the plurality of first sacrificial layers PL1.

The width in the horizontal direction (X direction or Y direction) at the uppermost end of each of the plurality of first dummy channel holes154H may be less than the width in the horizontal direction (X direction or Y direction) at the uppermost end of each of the plurality of first cell channel holes152H. In an implementation, the width in the horizontal direction (X direction or Y direction) at the lowermost end (e.g., bottom) of each of the plurality of first dummy channel holes154H may be less than the width in the horizontal direction (X direction or Y direction) at the lowermost end of each of the plurality of first cell channel holes152H.

Referring toFIG.4, a mold layer108filling each of the plurality of first cell channel holes152H and the plurality of first dummy channel holes154H may be formed. The mold layer108may include a material having different characteristics from the first protective insulating layer114, the first filling insulating layer172, the plurality of first insulating layers112, the plurality of first sacrificial layers PL1, and the substrate102, and a plurality of second insulating layers116, a plurality of second sacrificial layers PL2, a second filling insulating layer174, and a second protective insulating layer190, which are to be formed inFIG.5. In an implementation, the mold layer108may include, e.g., a material containing carbon (C).

Referring toFIG.5, in the cell region CR and the interconnection region IR, a structure in which the plurality of second insulating layers116and the plurality of second sacrificial layers PL2are alternately stacked one by one may be formed. In the present specification, the structure in which the plurality of first insulating layers112and the plurality of first sacrificial layers PL1are alternately stacked one by one may be referred to as a first preliminary stacked structure, and the structure in which the plurality of second insulating layers116and the plurality of second sacrificial layers PL2are alternately stacked one by one may be referred to as a second preliminary stacked structure. In an implementation, the plurality of second sacrificial layers PL2may include a silicon nitride layer, and the plurality of second insulating layers116may include a silicon oxide layer. In an implementation, the plurality of first sacrificial layers PL1and the plurality of second sacrificial layers PL2may include the same material, and the plurality of first insulating layers112and the plurality of second insulating layers116may include the same material. For example, the plurality of first sacrificial layers PL1and the plurality of second sacrificial layers PL2may include different materials having similar etching characteristics, and the plurality of first insulating layers112and the plurality of second insulating layers116may include different materials having similar etching characteristics.

Next, by removing a portion of the structure in which the plurality of second insulating layers116and the plurality of second sacrificial layers PL2are alternately stacked one by one in the interconnection region IR, e.g., by removing a portion of the second preliminary stacked structure, an edge portion of the second preliminary stacked structure may be formed to have a stepwise structure in the interconnection region TR. For example, the second preliminary stacked structure may have a roughly sloped profile in the interconnection region TR. In addition, the first preliminary stacked structure and the second preliminary stacked structure may have a sloped profile in the interconnection region R.

The second filling insulating layer174may be formed in a portion where a portion of the second preliminary stacked structure has been removed, and the second protective insulating layer190covering the second preliminary stacked structure and the second filling insulating layer174may be formed in the cell region CR and the interconnection region IR. The second protective insulating layer190may include an oxide layer, a nitride layer, or a combination thereof. The second filling insulating layer174may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

The second protective insulating layer190may include a first layer192and a second layer194. In an implementation, the first layer192may include the same material as the first protective insulating layer114. In an implementation, the second protective insulating layer190may be omitted. In an implementation, the second protective insulating layer190may include only the first layer192, and the second layer194may be omitted.

A second stack ST2may include a portion in which the plurality of second insulating layers116and the plurality of second sacrificial layers PL2are arranged. The second stack ST2may be referred to as a portion in which a plurality of second cell channel holes (162H inFIG.6) and a plurality of second dummy channel holes (164H inFIG.6) are formed in the vertical direction (Z direction).

Referring toFIG.6, in the cell region CR, a plurality of second cell channel holes162H penetrating through the plurality of second insulating layers116and the plurality of second sacrificial layers PL2may be formed. In the interconnection region IR, a plurality of second dummy channel holes164H penetrating through the second filling insulating layer177, the plurality of second insulating layers116, and the plurality of second sacrificial layers PL2may be formed. When the second protective insulating layer190is formed on the plurality of first insulating layers112and the plurality of second sacrificial layers PL2, the plurality of second cell channel holes162H and the plurality of second dummy channel holes164H may also penetrate through the second protective insulating layer190.

The plurality of second cell channel holes162H and the plurality of second dummy channel holes164H may be formed by anisotropic etching of the second protective insulating layer190, the second filling insulating layer174, the plurality of second insulating layers116, and the plurality of second sacrificial layers PL2. The mold layer108filling the plurality of first cell channel holes152H and the plurality of first dummy channel holes154H may be exposed at bottoms of the plurality of second cell channel holes162H and the plurality of second dummy channel holes164H.

The second stack ST2may indicate a portion from uppermost ends (e.g., mouths or openings) to lowermost ends (e.g., bottoms) of the plurality of second cell channel holes162H and the plurality of second dummy channel holes164H in the vertical direction (Z direction). The second stack ST2may include the second protective insulating layer190, the second filling insulating layer174, the plurality of second insulating layers116, and the plurality of second sacrificial layers PL2.

In an implementation, the plurality of second cell channel holes162H and the plurality of second dummy channel holes164H may have a tapered shape such that a width thereof in the horizontal direction (X direction or Y direction) decreases toward or closer to the substrate102. In an implementation, the widths of the second cell channel hole162H and the second dummy channel hole164H in the horizontal direction (the X direction or the Y direction) may have maximum values below the uppermost end of each of the second cell channel hole162H and the second dummy channel hole164H, respectively, and may have decreasing values toward the substrate102from the portions having the maximum widths, respectively, due to a bowing phenomenon that could occur in the process of anisotropic etching of the second protective insulating layer190, the second filling insulating layer174, the plurality of second insulating layers116, and the plurality of second sacrificial layers PL2.

In an implementation, the width in the horizontal direction (the X direction or the Y direction) at the uppermost end of each of the plurality of second dummy channel holes164H may be less than the width in the horizontal direction (the X direction or the Y direction) at the uppermost end of each of the plurality of second cell channel holes162H. In an implementation, the width in the horizontal direction (the X direction or the Y direction) at the lowermost end of each of the plurality of second dummy channel holes164H may be less than the width in the horizontal direction (the X direction or the Y direction) at the lowermost end of each of the plurality of second cell channel holes162H.

The width of the uppermost end of each of the plurality of second dummy channel holes164H in the horizontal direction (X direction or Y direction) may be less than the width of the uppermost end of each of the plurality of first dummy channel holes154H in the horizontal direction (X direction or Y direction). The width of the lowermost end of each of the plurality of second dummy channel holes164H in the horizontal direction (X direction or Y direction) may be less than the width of the uppermost end of each of the plurality of first dummy channel holes154H in the horizontal direction (X direction or Y direction). The width of the lowermost end of each of the plurality of second dummy channel holes164H in the horizontal direction (X direction or Y direction) may be less than the width of the lowermost end of each of the plurality of first dummy channel holes154H in the horizontal direction (X direction or Y direction).

The width of the uppermost end of each of the plurality of second cell channel holes162H in the horizontal direction (X direction or Y direction) may be less than the width of the uppermost end of each of the plurality of first cell channel holes152H in the horizontal direction (X direction or Y direction). The width of the lowermost end of each of the plurality of second cell channel holes162H in the horizontal direction (X direction or Y direction) may be less than the width of the uppermost end of each of the plurality of first cell channel holes152H in the horizontal direction (X direction or Y direction). The width of the lowermost end of each of the plurality of first dummy channel holes154H in the horizontal direction (X direction or Y direction) may be less than the width of the lowermost end of each of the plurality of first cell channel holes152H in the horizontal direction (X direction or Y direction).

Referring toFIG.7, by removing the mold layer (108inFIG.6) from the plurality of first cell channel holes152H and the plurality of first dummy channel holes154H by using the plurality of second cell channel holes162H and the plurality of second dummy channel holes164H, the plurality of second cell channel holes162H may be communicatively connected to the plurality of first cell channel holes152H, and the plurality of second dummy channel holes164H may be communicatively connected to the plurality of first dummy channel holes154H.

The first cell channel hole152H and the second cell channel hole162H that are communicatively connected to each other may be referred to as cell channel holes, and the first dummy channel hole154H and the second dummy channel hole164H that are communicatively connected to each other may be referred to as dummy channel holes.

The cell channel hole may include the first cell channel hole152H extending from a first level LV1to a second level LV2in the vertical direction (Z direction), and the second cell channel hole162H extending from the second level LV2to a third level LV3in the vertical direction (Z direction). The dummy channel hole may include the first dummy channel hole154H extending from the first level LV1to the second level LV2in the vertical direction (Z direction), and the second dummy channel hole164H extending from the second level LV2to the third level LV3in the vertical direction (Z direction). The second level LV2may be farther from the substrate102than the first level LV1in the vertical direction (Z direction), and the third level LV3may be farther from the substrate102than the second level LV2in the vertical direction (Z direction).

Referring toFIG.8, a plurality of cell channel structures150C filling the plurality of second cell channel holes162H and the plurality of first cell channel holes152H, and a plurality of dummy channel structures150D filling the plurality of second dummy channel holes164H and the plurality of first cell channel holes152H may be formed.

Each of the plurality of cell channel structures150C and the plurality of dummy channel structures150D may include a semiconductor pattern120, a charge storage structure130, a channel layer140, a filling insulating layer145, and a conductive plug layer156.

The semiconductor pattern120may be in contact with the substrate102, and may fill a portion of each of the plurality of cell channel holes and the plurality of dummy channel holes, e.g., a lower portion of each of the plurality of first cell channel holes152H and the plurality of first dummy channel holes154H. The semiconductor pattern120may be formed by performing a selective epitaxial growth (SEG) using the substrate102that is exposed at the bottoms of the plurality of first cell channel holes152H and the plurality of first dummy channel holes154H as a seed. A top surface of the semiconductor pattern120may be at a level that is between a top surface of the first sacrificial layer PL1closest to the substrate102among the plurality of first sacrificial layers PL1, and a bottom surface of the first insulating layer112closest to the substrate102among the plurality of first insulating layers112. The semiconductor pattern120may function as a channel similarly to the channel layer140. The semiconductor pattern120may include Si or Ge. In an implementation, the semiconductor pattern120may include a semiconductor doped with impurities.

The channel layer140may contact the semiconductor pattern120and may extend in the vertical direction (Z direction) in each of the plurality of cell channel structures150C and the plurality of dummy channel structures150D. In an implementation, the channel layer140may have a cylindrical shape having an internal space therein (e.g., a hollow cylindrical shape). The channel layer140may include polysilicon doped with impurities and polysilicon not doped with impurities.

The filling insulating layer145may fill an inner space of each of the plurality of cell channel holes and the plurality of dummy channel holes defined by the channel layer140. The filling insulating layer145may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In an implementation, the filling insulating layer115may be omitted, and in this case, the channel layer140may have a pillar structure without an internal space therein.

The conductive plug layer156may be in contact with the filling insulating layer145and the channel layer140, and may fill an upper portion of an inlet side (e.g., mouth or opening) of each of the plurality of cell channel holes and the plurality of dummy channel holes. The conductive plug layer156may include a polysilicon layer doped with impurities. The plurality of conductive plug layers156included in the plurality of cell channel structures150C and the plurality of dummy channel structures150D may be insulated from each other by the second protective insulating layer190.

The charge storage structure130may include a tunneling dielectric layer132, a charge storage layer134, and a blocking dielectric layer138. The charge storage structure130may be between the plurality of first sacrificial layers PL1and the plurality of channel layers140, and between the plurality of second sacrificial layers PL2and the plurality of channel layers140. In an implementation, the charge storage structure130may have a cylindrical shape extending in the vertical direction (Z direction) along a sidewall of each of the plurality of cell channel holes and the plurality of dummy channel holes. In an implementation, at least one of the tunneling dielectric layer132, the charge storage layer134, and the blocking dielectric layer138, which constitute the charge storage structure130, may be spaced apart from each other in the vertical direction (Z direction) and have a ring shape.

The tunneling dielectric layer132may include a silicon oxide layer. The charge storage layer134may include silicon nitride, polysilicon, or polysilicon doped with impurities. In an implementation, the charge storage layer134may include a charge trap layer including a silicon nitride layer. In an implementation, the charge storage layer134may be a floating gate including polysilicon or polysilicon doped with impurities. The blocking dielectric layer138may include a silicon oxide layer or a silicon oxynitride layer.

Referring toFIG.9, by removing a portion of the second stack ST2including the plurality of second sacrificial layers PL2and the plurality of second insulating layers116, and a portion of the first stack ST1including the plurality of first sacrificial layers PL1and the plurality of first insulating layers112, a word line cut region WLC may be formed. The substrate102may be exposed at a bottom of the word line cut region WLC.

Referring toFIGS.10A and10Btogether, by removing the plurality of first sacrificial layers PL1and the plurality of second sacrificial layers PL2by using the word line cut region WLC, a plurality of word line spaces DH communicatively connected to the word line cut region WLC may be formed.

Referring toFIGS.11A and11Btogether, a plurality of word line structures WS filling the plurality of word line spaces (DH inFIGS.10A and10B) may be formed. After forming a word line material layer filling the plurality of word line spaces DH and the word line cut region WLC, the plurality of word line structures WS may be formed by removing a portion of the word line material layer formed in the word line cut region WLC.

The plurality of word line structures WS may extend in the horizontal direction (X direction or Y direction) on the substrate102and overlap each other in the vertical direction (Z direction) perpendicular to the substrate102. The word line structure WS may include a metal such as tungsten, nickel, cobalt, and tantalum, a metal silicide such as tungsten silicide, nickel silicide, cobalt silicide, and tantalum silicide, polysilicon doped with impurities, or a combination thereof.

In the present specification, a structure in which the plurality of first insulating layers112and the plurality of word line structures WS are alternately stacked one by one in the first stack ST1may be referred to as a first stacked structure, and a structure in which the plurality of second insulating layers116and the plurality of word line structures WS are alternately stacked one by one in the second stack ST2may be referred to as a second stacked structure. In addition, the first insulating layer112may be referred to as an insulating layer of the first stack ST1, and the second insulating layer116may be referred to as an insulating layer of the second stack ST2. Edge portions of the first stacked structure and the second stacked structure may have a stepwise structure.

Next, a common source line CSL filling the word line cut region WLC may be formed. The common source line CSL may extend in a first horizontal direction (X direction). An insulating spacer184covering a sidewall of the common source line CSL may be formed in the word line cut region WLC. The insulating spacer184may electrically insulate spaces between the common source line CSL and the plurality of word line structures WS. The common source line CSL may include a metal, e.g., tungsten, copper, and aluminum, a conductive metal nitride such as titanium nitride and tantalum nitride, a transition metal such as titanium and tantalum, or a combination thereof. The insulating spacer184may include, e.g., a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. A common source region may be formed in a portion of the substrate102in contact with the common source line CSL. The common source region may be an impurity region including n-type impurities heavily doped thereon.

In an implementation, a metal silicide layer170(for reducing contact resistance) may be between the common source region and the common source line CSL. For example, the metal silicide layer170may include cobalt silicide, tungsten silicide, nickel silicide, or the like.

In an implementation, a capping insulating layer covering a top surface of the common source line CSL may be formed on an upper portion of the word line cut region WLC. The capping insulating layer may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof.

FIGS.12A and12Billustrate cross-sectional views of an integrated circuit device according to example embodiments, andFIG.12Cillustrates a plan layout of some components of the integrated circuit device.

Referring toFIGS.12A and12Btogether, a string selection line cut region SLC limited or formed by removing a portion of the second protective insulating layer190, an upper portion of at least one of the plurality of second insulating layers116, and an upper portion of at least one of the plurality of word line structures WS may be formed, and a cut insulating layer196filling the string selection line cut region SLC may be formed. The cut insulating layer196may include an oxide layer, a nitride layer, or a combination thereof.

Next, a first conductive stud232and a bit line BL on the conductive plug layer156included in each of the plurality of cell channel structures150C, and an upper conductive via234between the first conductive stud232and the bit line BL, may be formed. An interlayer insulating layer210may surround the first conductive stud232and the upper conductive via234. A plurality of the bit lines BL may have a generally constant distance from each other in the first horizontal direction (X direction) and may extend in a second horizontal direction (Y direction). In an implementation, the plurality of cell channel structures150C may be connected to the bit lines BL through the first conductive stud232and the upper conductive via234. In an implementation, according to an arrangement of the plurality of cell channel structures150C, a horizontal width of the plurality of cell channel structures150C, and/or a horizontal width of the bit lines BL, and the like, the plurality of cell channel structures150C may be connected to the plurality of bit lines BL in various ways.

In the interconnection region IR, a conductive contact plug MCP may be formed that fills a contact hole MCH exposing the word line structure WS between at least two dummy channel structures150D, and may be electrically connected to the word line structure WS. The interconnection region IR may include an inner interconnection region IR (IN) relatively close (e.g., proximate) to the cell region CR and an outer interconnection region IR (OUT) relatively far from (e.g., distal to) the cell region CR. Here, the terms of the inner interconnection region IR (IN) and the outer interconnection region IR (OUT) may be merely to compare and explain two portions in the interconnection region that have relatively different distances in the horizontal direction (for example, the first horizontal direction (X direction)) from the cell region CR, and may not indicate particular portions. In addition, for convenience of explanation, ‘(I)’ may be added after a member number corresponding to the inner interconnection region IR (IN), and ‘(O)’ may be added after a member number corresponding to the outer interconnection region IR (OUT). A member number to which ‘(I)’ or ‘(O)’ is not added may correspond to a case where it is not particularly necessary to differentiate whether the member number is in the inner interconnection region IR(IN) or the outer interconnection region IR(OUT).

The conductive contact plug MCP may extend in the vertical direction (Z direction) from the word line structure WS to which the conductive contact plug MCP is electrically connected.FIG.12Aillustrates an example in which the conductive contact plug MCP penetrates through the second protective insulating layer190, the second filling insulating layer174, and the first protective insulating layer114and is connected to one of the plurality of word line structures WS of the first stack ST1. In an implementation, the conductive contact plug MCP may be formed in various ways such that the conductive contact plug MCP is connected to one of the plurality of word line structures WS included in the second stack ST2, e.g., by penetrating through the second protective insulating layer190, or is connected to one of the plurality of word line structures WS included in the second stack ST2by penetrating through the second protective insulating layer190and the second filling insulating layer174, or is connected to one of the plurality of word line structures WS included in the first stack ST1by penetrating the second protective insulating layer190, the second filling insulating layer174, the first protective insulating layer114, and the first filling insulating layer172.

The conductive contact plug MCP may be electrically connected to a conductive connection wire224via a second conductive stud222. The first conductive stud232and the second conductive stud222may include the same material. In an implementation, the uppermost end of the first conductive stud232and the uppermost end of the second conductive stud222may have the same level (e.g., may be the same distance from the substrate102in the vertical Z direction).

The conductive connection wire224may extend on a horizontal level closer to the substrate102than the bit line BL. In an implementation, the conductive connection wire224may extend, e.g., in the first horizontal direction (X direction). For example, the conductive connection wire224may extend in the first horizontal direction (X direction), be bent, and extend in the second horizontal direction (Y direction), or may extend in the second horizontal direction (Y direction), or may extend in the second horizontal direction (Y direction), be bent, and extend in the first horizontal direction (X direction).

The plurality of word line structures WS between two neighboring word line cut regions WLC may include the ground selection line GSL, the first through nthword lines WL1through WLn, and the string selection line SSL. The number of word line structures WS stacked on the substrate102in the vertical direction (Z direction) may be variously selected as desired. The word line structure WS that is closest to the substrate102among the plurality of word line structures WS may constitute the ground selection line GSL. Each of two word line structures WS on the uppermost end of the plurality of word line structures WS may constitute the string selection line SSL. The string selection line SSL may include portions separated by the string selection line cut region SLC.

Referring toFIGS.12A through12Ctogether, an integrated circuit device1may include the plurality of cell channel structures150C filling the plurality of cell channel holes including the first cell channel hole152H and the second cell channel hole162H, which are communicatively connected to each other, and the plurality of dummy channel structures150D filling the plurality of dummy channel holes including the first dummy channel hole154H and the second dummy channel hole164H, which are communicatively connected to each other.

The first cell channel hole152H and the first dummy channel hole154H may extend in the vertical direction (Z direction) from the first level LV1to the second level LV2, and the second cell channel hole162H and the second dummy channel hole164H may extend in the vertical direction (Z direction) from the second level LV2to the third level LV3.

A width of the first dummy channel hole154H at the second level LV2, e.g., a first dummy top width WIU1, which is a width of an uppermost end of the first dummy channel hole154H, may be greater than a width of the first dummy channel hole154H at the first level LV1, e.g., a first dummy bottom width WID1, which is a width of a lowermost end of the first dummy channel hole154H.

A width of the second dummy channel hole164H at the third level LV3, e.g., a second dummy top width WIU2, which is a width of an uppermost end of the second dummy channel hole164H, may be greater than a width of the second dummy channel hole164H on the second level LV2, e.g., a second dummy bottom width WID2, which is a width of a lowermost end of the second dummy channel hole164H.

The first dummy upper width WIU1may be greater than the second dummy upper width WIU2. In an implementation, the first dummy lower width WID1may be greater than the second dummy lower width WID2. In an implementation, according to a ratio of a height of the first stack ST1over a height of the second stack ST2in the vertical direction (Z direction), the first dummy lower width WID1and the second dummy lower width WID2may have generally the same value, and the first dummy lower width WID1may be less than the second dummy lower width WID2.

A distance between a pair of first dummy channel holes154H adjacent to each other with the conductive contact plug MCP therebetween (e.g., in the X direction) at the second level LV2, e.g., a first dummy top distance DIU1that is a distance between uppermost ends of the pair of first dummy channel holes154H adjacent to each other with the conductive contact plug MCP therebetween, may be less than a distance between the pair of first dummy channel holes154H adjacent to each other with the conductive contact plug MCP therebetween at the first level LV1, e.g., a first dummy top distance DID1that is a distance between lowermost ends of the pair of first dummy channel holes154H adjacent to each other with the conductive contact plug MCP therebetween.

A distance between a pair of second dummy channel holes164H adjacent to each other with the conductive contact plug MCP therebetween at the third level LV3, e.g., a second dummy top distance DIU2that is a distance between uppermost ends of the pair of second dummy channel holes164H adjacent to each other with the conductive contact plug MCP therebetween, may be less than a distance between the pair of second dummy channel holes164H adjacent to each other with the conductive contact plug MCP therebetween at the second level LV2, e.g., a second dummy bottom distance DID2that is a distance between lowermost ends of the pair of second dummy channel holes164H adjacent to each other with the conductive contact plug MCP therebetween.

The second dummy upper distance DIU2may be greater than the first dummy upper distance DIU1. The second dummy lower distance DID2may be greater than the first dummy upper distance DIU1.

In an implementation, the second dummy lower distance DID2may be less than the first dummy lower distance DID1. In an implementation, according to a ratio of the height of the first stack ST1over the height of the second stack ST2in the vertical direction (Z direction), the first dummy lower distance DID1and the second dummy lower distance DID2may have generally the same value, and the first dummy lower distance DID1may be less than the second dummy lower distance DID2.

A width of the first cell channel hole152H at the second level LV2, e.g., a first cell top width WCU1, which is a width of an uppermost end of the first cell channel hole152H, may be greater than a width of the first cell channel hole152H at the first level LV1, e.g., a first cell lower width WCD1, which is a width of a lowermost end of the first cell channel hole152H.

A width of the second cell channel hole162H at the third level LV3, e.g., a second cell top width WCU2, which is a width of an uppermost end of the second cell channel hole162H, may be greater than a width of the second cell channel hole162H at the second level LV2, e.g., a second cell lower width WCD2, which is a width of a lowermost end of the second cell channel hole162H.

The first cell upper width WCU1may be substantially the same as the second cell upper width WCU2. In an implementation, the first cell bottom width WCD1may be substantially the same as the second cell bottom width WCD2. In an implementation, according to the ratio of the height of the first stack ST1over the height of the second stack ST2in the vertical direction (Z direction), the first cell lower width WCD1may be greater than the second cell lower width WCD2, and the first cell lower width WCD1may be less than the second cell lower width WCD2.

A distance between a pair of first cell channel holes152H adjacent to each other in a diagonal direction at the second level LV2, e.g., an inclined direction with respect to the first horizontal direction (X direction) and the second horizontal direction (Y direction), e.g., a first cell top distance DCU1that is a distance between the uppermost ends of the pair of first cell channel holes152H adjacent to each other in the diagonal direction may be less than a distance between a pair of first cell channel holes152H adjacent to each other in a diagonal direction at the first level LV1, e.g., a first cell lower distance DCD1that is a distance between the lowermost ends of the pair of first cell channel holes152H adjacent to each other in the diagonal direction.

A distance between a pair of second cell channel holes162H adjacent to each other in a diagonal direction at the third level LV3, e.g., an inclined direction with respect to the first horizontal direction (X direction) and the second horizontal direction (Y direction), e.g., a second cell upper distance DCU2that is a distance between the uppermost ends of the pair of second cell channel holes162H adjacent to each other in the diagonal direction may be less than a distance between a pair of second cell channel holes162H adjacent to each other in a diagonal direction at the second level LV2, e.g., a second cell lower distance DCD2that is a distance between the lowermost ends of the pair of second cell channel holes162H adjacent to each other in the diagonal direction.

The second cell upper distance DCU2may be substantially the same as the first cell upper distance DCU1. In an implementation, the first cell lower distance DCD1and the second cell lower distance DCD2may have substantially the same value. In an implementation, according to the ratio of the height of the first stack ST1over the height of the second stack ST2in the vertical direction (Z direction), the first cell lower distance DCD1may be greater than the second cell lower distance DCD2, and the first cell lower distance DCD1may be less than the second cell lower distance DCD2.

In an implementation, the first cell upper width WCU1, the second cell upper width WCU2, the first cell lower width WCD1, and the second cell lower width WCD2may be greater than the first dummy upper width WIU1, the second dummy upper width WIU2, the first dummy lower width WID1, and the second dummy lower width WID2, respectively.

A first dummy upper width WIU1(I), a first dummy lower width WID1(I), a second dummy upper width WIU2(I), and a second dummy lower width WID2(I) in the inner interconnection region IR(IN) may be greater than a first dummy upper width WIU1(O), a first dummy lower width WID1(O), a second dummy upper width WIU2(O), and a second dummy lower width WID2(O) in the outer interconnection region IR, respectively. For example, a first dummy channel hole154H(I) and a second dummy channel hole164H(I) in the inner interconnection region IR(IN) may have greater widths than a first dummy channel hole154H(O) and a second dummy channel hole164H(O) in the outer interconnection region IR(IN), respectively. For example, at the same level, a dummy channel structure150D(I) in the inner interconnection region IR(IN) may have a greater diameter than a dummy channel structure150D(O) in the outer interconnection region IR(OUT).

A first dummy upper distance DIU1(I), a first dummy lower distance DID1(I), a second dummy upper distance DIU2(I), and a second dummy lower distance DID2(I) in the inner interconnection region IR(IN) may be less than a first dummy upper distance DIU1(O), a first dummy lower distance DID1(O), a second dummy upper distance DIU2(O), and a second dummy lower distance DID2(O) in the outer interconnection region IR, respectively.

In the integrated circuit device1according to embodiments, by forming the second dummy upper width WIU2to be less than the first dummy upper width WIU1, the second dummy upper distance DIU2may be greater than the first dummy upper distance DIU1. For example, an area at the third level LV3for forming the contact hole MCH filling the conductive contact plug MCP, e.g., an area between the dummy channel structures150D may be secured, and a process margin for forming the contact hole MCH and the conductive contact plug MCP may increase.

In addition, in the integrated circuit device1according to embodiments, the first dummy upper width WIU1may be greater than the second dummy upper width WIU2, and, in a process of forming the second dummy channel hole164H on the first dummy channel hole154H, a misalignment between the first dummy channel hole154H and the second dummy channel hole164H communicatively connected to each other may be prevented. For example, a bridge between the word line structures WS that could otherwise be generated when the misalignment occurs between the first dummy channel hole154H and the second dummy channel hole164H that are communicatively connected to each other, may be prevented.

In addition, in the integrated circuit device1according to embodiments, the first dummy upper distance DIU1(I), the first dummy lower distance DID(I), the second dummy upper distance DIU2(I), and the second dummy lower distance DIU2(I) in the inner interconnection region IR(IN) may be greater than the first dummy upper distance DIU1(O), the first dummy lower distance DID(O), the second dummy upper distance DIU2(O), and the second dummy lower distance DIU2(O) in the outer interconnection region IR(OUT), respectively, and a process margin for forming the contact hole MCH and the conductive contact plug MCP that are formed at a relatively far distance from the cell region CR may increase.

FIGS.13and14illustrate cross-sectional views of stages in a fabrication method of the integrated circuit device according to example embodiments.FIG.13illustrates a cross-sectional view of a stage after the operation illustrated inFIG.3, and repeated descriptions already given with respect toFIGS.1through11Bmay be omitted from the descriptions to be given with respect toFIGS.13and14.

Referring toFIG.13, the semiconductor pattern120, a lower charge storage structure130L, a lower channel layer140L, a lower filling insulating layer145L, and a connection conductive plug layer158may be formed in each of the plurality of first cell channel holes152H and each of the plurality of first dummy channel holes154H.

Except for filling each of the plurality of first cell channel holes152H and each of the plurality of first cell channel holes152H, the semiconductor pattern120, the lower charge storage structure130L, the lower channel layer140L, the lower filling insulating layer145L, and the connection conductive plug layer158may be generally similar to the semiconductor pattern120, the charge storage structure130, the channel layer140, the filling insulating layer145, and the conductive plug layer156, which fill each of the plurality of cell channel structures150C and each of the plurality of dummy channel structures150D described with respect toFIG.8.

Referring toFIG.14, similar to the method described with reference toFIGS.5through7, a structure in which the plurality of second insulating layers116and the plurality of sacrificial layers PL2are alternately stacked one by one on the first stack ST1in the cell region CR and the interconnection region IR may be formed, by removing a portion of the structure in which the plurality of second insulating layers116and the plurality of second sacrificial layers PL2are alternately stacked one by one in the interconnection region IR, e.g., by removing a portion of the second preliminary stacked structure, the edge portions of the second preliminary stacked structure may be formed to have a stepwise structure, the second filling insulating layer174may be formed at a portion where the portion of the second preliminary stacked structure has been removed, and the second protective insulating layer190covering the second preliminary stacked structure and the second filling insulating layer174in the cell region CR and the interconnection region IR may be formed. Next, in the cell region CR, a plurality of second cell channel holes162H penetrating through the plurality of second insulating layers116and the plurality of second sacrificial layers PL2may be formed, and in the interconnection region IR, a plurality of second dummy channel holes164H penetrating through the second filling insulating layer177, the plurality of second insulating layers116, and the plurality of second sacrificial layers PL2may be formed. The connection conductive plug layer158may be exposed at the bottom surfaces of the plurality of second cell channel holes162H and the plurality of second dummy channel holes164H.

Unlike the mold layer (108inFIG.6) filling the plurality of first cell channel holes152H and the plurality of first dummy channel holes154H is removed inFIG.7, the semiconductor pattern120, the lower charge storage structure130L, the lower channel layer140L, the lower filling insulating layer145L, and the connection conductive plug layer158, which fill the plurality of first cell channel holes152H and the plurality of first dummy channel holes154H, may not be removed.

FIG.15illustrates a cross-sectional view of an integrated circuit device according to example embodiments.

Referring toFIG.15, an upper charge storage structure130H, an upper channel layer140H, and an upper filling insulating layer145H may be arranged in each of the plurality of second cell channel holes162H and each of the plurality of second dummy channel holes164H. Except for filling each of the plurality of first cell channel holes152H and each of the plurality of first cell channel holes152H, the upper charge storage structure130H, the upper channel layer140H, the upper filling insulating layer145H, and the conductive plug layer156may be generally similar to the charge storage structure130, the channel layer140, the filling insulating layer145, and the conductive plug layer156, which fill each of the plurality of cell channel structures150C and each of the plurality of dummy channel structures150D, respectively.

Each of a plurality of cell channel structures150Ca filling the plurality of second cell channel holes162H and the plurality of first cell channel holes152H, and each of a plurality of dummy channel structures150Da filling the plurality of second dummy channel holes164H and the plurality of first dummy channel holes154H may include the semiconductor pattern120, the lower charge storage structure130L, the lower channel layer140L, the lower filling insulating layer145L, and the connection conductive plug layer158, which fill each of the plurality of first cell channel holes152H and each of the plurality of first dummy channel holes154H, and the upper charge storage structure130H, the upper channel layer140H, the upper filling insulating layer145H, and the conductive plug layer156, which fill each of the plurality of second cell channel holes162H and each of the plurality of second dummy channel holes164H. The lower channel layer140L may contact the semiconductor pattern120, and may be electrically connected to the upper channel layer140H via the connection conductive plug layer158.

The integrated circuit device1illustrated inFIGS.12A through12Cand the integrated circuit device1aillustrated inFIG.15may be generally the same except configurations of the plurality of cell channel structures150C and the plurality of dummy channel structures150D included in the integrated circuit device1, and configurations of the plurality of cell channel structures150Ca and the plurality of dummy channel structures150D included in the integrated circuit device1a, and thus, a repeated detailed description thereof may be omitted.

FIG.16illustrates a cross-sectional view of an integrated circuit device according to example embodiments.FIG.16illustrates a cross-sectional view of a stage after the operation illustrated inFIG.3, and descriptions already given with respect toFIGS.1through11Bmay be omitted from the descriptions to be given with respect toFIG.16.

Referring toFIG.16, by removing a portion of the first protective insulating layer114in the interconnection region IR, a plurality of first dummy channel holes154Ha may be formed that have been expanded such that a width of an upper portion thereof is greater than a width of the remaining portion thereof with respect to the plurality of first dummy channel holes154H illustrated inFIG.3. An upper portion that is limited or defined by the first protective insulating layer114and having a greater width than the remaining portion among the plurality of first dummy channel holes154Ha may be referred to as an expansion dummy hole154E.

FIG.17Aillustrates a cross-sectional view of an integrated circuit device according to example embodiments, andFIG.17Billustrates a plan layout of some components of the integrated circuit device2.

Referring toFIG.17A, the integrated circuit device2may be formed by performing a method similar to the method described with reference toFIGS.4through12B.

The integrated circuit device2illustrated inFIG.17Amay be generally similar to the integrated circuit device1illustrated inFIGS.12A and12B, except that the integrated circuit device2may include a plurality of dummy channel structures150Db filling a plurality of dummy channel holes including the first dummy channel hole154Ha and a second dummy channel hole164H that are communicatively connected to each other, instead of the plurality of dummy channel structure150D filling the plurality of dummy channel holes including the first dummy channel hole154H and the second dummy channel hole164H that are communicatively connected to each other.

Referring toFIGS.17A and17Btogether, the integrated circuit device2may include the plurality of cell channel structures150C filling the plurality of cell channel holes including the first cell channel holes152H and the second cell channel hole162H, which are communicatively connected to each other, and the plurality of dummy channel structures150Db filling the plurality of dummy channel holes including the first dummy channel holes154Ha and the second dummy channel holes164H, which are communicatively connected to each other. The first dummy channel hole154Ha may include the expansion dummy hole154E limited by the first protective insulating layer114at an upper portion of the first dummy channel hole154Ha.

The first cell channel hole152H and the first dummy channel hole154Ha may extend in the vertical direction (Z direction) from the first level LV1to the second level LV2, and the second cell channel hole162H and the second dummy channel hole164H may extend in the vertical direction (Z direction) from the second level LV2to the third level LV3.

A width of the first dummy channel hole154Ha at the second level LV2, e.g., a first dummy top width WIU1a, which is a width of an uppermost end of the first dummy channel hole154Ha, may be greater than a width of the first dummy channel hole154Ha at the first level LV1, e.g., a first dummy lower width WID1, which is a width of a lowermost end of the first dummy channel hole154Ha. A width of the second dummy channel hole164H at the third level LV3, e.g., a second dummy upper width WIU2, which is a width of an uppermost end of the second dummy channel hole164H, may be greater than a width of the second dummy channel hole164H at the second level LV2, e.g., a second dummy lower width WID2, which is a width of a lowermost end of the second dummy channel hole164H. At a fourth level LV4, a width of the first dummy channel hole154Ha, e.g., a width WIU1bat the same level as the bottom surface of the first protective insulating layer114of the first dummy channel hole154Ha may be greater than the first dummy lower width WID1and less than the first dummy upper width WIU1a.

The first dummy upper width WIU1amay be greater than the second dummy upper width WIU2. In an implementation, the first dummy lower width WID1may be greater than the second dummy lower width WID2. In an implementation, according to the ratio of the height of the first stack ST1over the height of the second stack ST2in the vertical direction (Z direction), the first dummy lower width WID1and the second dummy lower width WID2may have generally the same value, and the first dummy lower width WID1may be less than the second dummy lower width WID2.

A distance between a pair of first dummy channel holes154Ha adjacent to each other with the conductive contact plug MCP therebetween at the second level LV2, e.g., a first dummy upper distance DIU1athat is a distance between uppermost ends of the pair of first dummy channel holes154Ha adjacent to each other with the conductive contact plug MCP therebetween may be less than a distance between the pair of first dummy channel holes154Ha adjacent to each other with the conductive contact plug MCP therebetween at the first level LV1, e.g., the first dummy upper distance DID1that is a distance between lowermost ends of the pair of first dummy channel holes154Ha adjacent to each other with the conductive contact plug MCP therebetween. A distance between a pair of second dummy channel holes164H adjacent to each other with the conductive contact plug MCP therebetween at the third level LV3, e.g., a second dummy upper distance DIU2that is a distance between uppermost ends of the pair of second dummy channel holes164H adjacent to each other with the conductive contact plug MCP therebetween may be less than a distance between the pair of second dummy channel holes164H adjacent to each other with the conductive contact plug MCP therebetween at the second level LV2, e.g., a second dummy lower distance DID2that is a distance between lowermost ends of the pair of second dummy channel holes164H adjacent to each other with the conductive contact plug MCP therebetween. At the fourth level LV4, a distance between the pair of adjacent first dummy channel holes154Ha with the conductive contact plugs MCP therebetween, e.g., a distance DIU1bof the pair of adjacent first pairs with the conductive contact plugs MCP therebetween at the same level as the bottom surface of the first protective insulating layer114, may be less than the first dummy lower distance DID1and greater than the first dummy upper distance DIU1a.

The second dummy upper distance DIU2may be greater than the first dummy upper distance DIU1a. The second dummy lower distance DID2may be greater than the first dummy upper distance DIU1a. In an implementation, the second dummy lower distance DID2may be less than the first dummy lower distance DID1. In an implementation, according to the ratio of the height of the first stack ST1over the height of the second stack ST2in the vertical direction (Z direction), the first dummy lower distance DID1and the second dummy lower distance DID2may have generally the same value, and the first dummy lower distance DID1may be less than the second dummy lower distance DID2.

At each of the first level LV1, the second level LV2, and the third level LV3, the width of the first cell channel hole152H, the width of the second cell channel hole162H, and the distance between the pair of first cell channel holes152H adjacent to each other in the diagonal direction, and the distance between the pair of second cell channel holes162H adjacent to each other in the diagonal direction may be substantially the same as those described with reference toFIG.12C, and repeated detailed descriptions thereof may be omitted.

At the fourth level LV4, the width of the first dummy channel hole154H, e.g., a width WCU1bat the same level as the bottom surface of the first protective insulating layer114of the first dummy channel hole154H may be greater than the first dummy lower width WCD1and equal to or less than the first dummy upper width WCU1.

The distance between the pair of first cell channel holes152H adjacent to each other in the diagonal direction at the fourth level LV4, e.g., in an inclined direction with respect to the first horizontal direction (X direction) and the second horizontal direction (Y direction), e.g., a distance DCU1bof the pair of first cell channel holes152H adjacent to each other in the diagonal direction at the same level as the bottom surface of the first protective insulating layer114may be less than the first cell lower distance DCD1and equal to or greater than the first upper distance DCU1.

A first dummy upper width WIU1a(I), a first dummy lower width WID1(I), a second dummy upper width WIU2(I), and a second dummy lower width WID2(I), and a width WIU1b(I) of a first dummy channel hole154Ha(I) at the fourth level LV4in the inner interconnection region IR(IN) may be greater than a first dummy upper width WIU1a(O), a first dummy lower width WID1(O), a second dummy upper width WIU2(O), and a second dummy lower width WID2(O), and a width WIU1b(O) of a first dummy channel hole154Ha(O) at the fourth level LV4in the inner interconnection region IR(IN), respectively. For example, a first dummy channel hole154Ha(I) and a second dummy channel hole164H(I) in the inner interconnection region IR(IN) may have greater widths than a first dummy channel hole154Ha(O) and a second dummy channel hole164H(O) in the outer interconnection region IR(IN), respectively. For example, at the same level, a dummy channel structure150Db(I) in the inner interconnection region IR(IN) may have a greater diameter than a dummy channel structure150Db(O) in the outer interconnection region IR(OUT).

A first dummy upper distance DIU1a(I), a first dummy lower distance DID1(I), a second dummy upper distance DIU2(I), a second dummy lower distance DID2(I), and a distance DIU1b(I) between a pair of first dummy channel holes154Ha(I) adjacent to each other with the conductive contact plug MCP therebetween at the fourth level LV4in the inner interconnection region IR(IN) may be less than a first dummy upper distance DIU1a(O), a first dummy lower distance DID1(O), a second dummy upper distance DIU2(O), a second dummy lower distance DID2(O), and a distance DIU1b(O) between a pair of first dummy channel holes154Ha(O) adjacent to each other with the conductive contact plug MCP therebetween at the fourth level LV4in the inner interconnection region IR(IN), respectively.

FIG.18illustrates a cross-sectional view of an integrated circuit device according to example embodiments.

Referring toFIG.18, the integrated circuit device2amay be generally similar to the integrated circuit device1aillustrated inFIG.15, except that the integrated circuit device2sincludes a plurality of dummy channel structures150Dc filling a plurality of dummy channel holes including a first dummy channel hole154Ha and the second dummy channel hole164H that are communicatively connected to each other, instead of the plurality of dummy channel structure150Da filling the plurality of dummy channel holes including the first dummy channel hole154H and the second dummy channel hole164H that are communicatively connected to each other.

Each of the plurality of dummy channel structures150Dc may be similar to each of the plurality of dummy channel structures150Da illustrated inFIG.15except that the connection conductive plug layer158may be formed in the expansion dummy hole154E, and a repeated detailed description thereof may be omitted.

FIG.19illustrates a cross-sectional view of an integrated circuit device according to example embodiments.FIG.19illustrates a cross-sectional view of a stage after the operation illustrated inFIG.3, and repeated descriptions already given with respect toFIGS.1through11Bmay be omitted from the descriptions to be given with respect toFIG.19.

Referring toFIG.19, by removing a portion of the first protective insulating layer114in the cell region CR and the interconnection region IR, a plurality of first cell channel holes152Ha in which a width of an upper portion thereof is greater than a width of the remaining portion thereof with respect to the plurality of first cell channel holes152H, and a plurality of first dummy channel holes154Ha in which a width of an upper portion thereof is expanded with respect to the plurality of first dummy channel holes154H may be formed. An upper portion of the plurality of first cell channel holes152Ha defined by the first protective insulating layer114and having a width greater than the remaining portion may be referred to as an expansion cell hole152E, and an upper portion of the plurality of first dummy channel holes154Ha limited by the first protective insulating layer114and having a width greater than the remaining portion may be referred to as the expansion dummy hole154E.

FIG.20Aillustrates a cross-sectional view of an integrated circuit device according to example embodiments, andFIG.20Billustrates a plan layout of some components of the integrated circuit device ofFIG.20A.

Referring toFIG.20A, the integrated circuit device3may be formed by performing a method similar to the method described with reference toFIGS.4through12B.

The integrated circuit device3illustrated inFIG.20Ais generally similar to the integrated circuit device2illustrated inFIG.17A, except that the integrated circuit device3may include a plurality of cell channel structures150Cb filling a plurality of dummy channel holes including the first cell channel hole152Ha and the second cell channel hole162H that are communicatively connected to each other, instead of the plurality of cell channel structure150C filling the plurality of dummy channel holes including the first cell channel hole152H and the second cell channel hole162H that are communicatively connected to each other. For example, repeated descriptions to be given with respect toFIGS.20A and20Bwhich are the same as those given with respect toFIGS.17A and17Bmay be omitted.

Referring toFIGS.20A and20Btogether, the integrated circuit device3may include the plurality of cell channel structures150Cb filling the plurality of cell channel holes including the first cell channel hole152Ha and the second cell channel hole162H, which are communicatively connected to each other, and the plurality of dummy channel structures150Db filling the plurality of dummy channel holes including the first dummy channel hole154Ha and the second dummy channel hole164H, which are communicatively connected to each other. The first cell channel hole152Ha and the first dummy channel hole154Ha may include, at upper portions thereof, the expansion cell hole152E and the expansion dummy hole154E limited by the first protective insulating layer114, respectively.

The first cell channel hole152Ha and the first dummy channel hole154Ha may extend in the vertical direction (Z direction) from the first level LV1to the second level LV2, and the second cell channel hole162H and the second dummy channel hole164H may extend in the vertical direction (Z direction) from the second level LV2to the third level LV3.

At each of the first level LV1, the second level LV2, the third level LV3, and the fourth level LV4, the width of the first dummy channel hole154Ha, the width of the second dummy channel hole164H, the distance between the pair of first dummy channel holes154Ha adjacent to each other with the conductive contact plug MCP therebetween, and the distance between the pair of second dummy channel holes164H adjacent to each other with the conductive contact plug MCP therebetween may be substantially the same as those described with reference toFIG.17B, and repeated detailed descriptions thereof may be omitted.

A width of the first cell channel hole152Ha at the second level LV2, e.g., a first cell upper width WCU1a, which is a width of an uppermost end of the first cell channel hole152Ha, may be greater than a width of the first cell channel hole152Ha at the first level LV1, e.g., a first cell lower width WCD1, which is a width of a lowermost end of the first cell channel hole152Ha.

The width of the second cell channel hole162H at the third level LV3, e.g., the second cell upper width WCU2, which is the width of the uppermost end of the second cell channel hole162H, may be greater than the width of the second cell channel hole162H at the second level LV2, e.g., the second cell lower width WCD2, which is the width of the lowermost end of the second cell channel hole162H.

At the fourth level LV4, a width of the first dummy channel hole154Ha, e.g., the width WCU1bat the same level as the bottom surface of the first protective insulating layer114of the first dummy channel hole154H may be greater than the first dummy lower width WCD1and less than the first dummy upper width WCU1a.

The first cell upper width WCU1amay be greater than the second cell upper width WCU2. In an implementation, the first cell lower width WCD1and the second cell lower width WCD2may have generally the same value. In an implementation, according to the ratio of the height of the first stack ST1over the height of the second stack ST2in the vertical direction (Z direction), the first cell lower width WCD1may be greater than the second cell lower width WCD2, and the first cell lower width WCD1may be less than the second cell lower width WCD2.

A distance between a pair of first cell channel holes152Ha adjacent to each other in a diagonal direction at the second level LV2, e.g., in an inclined direction with respect to the first horizontal direction (X direction) and the second horizontal direction (Y direction), e.g., a first cell upper distance DCU1athat is a distance between the uppermost ends of the pair of first cell channel holes152Ha adjacent to each other in the diagonal direction may be less than a distance between a pair of first cell channel holes152Ha adjacent to each other in the diagonal direction at the first level LV1, e.g., a first cell lower distance DCD1that is a distance between the lowermost ends of the pair of first cell channel holes152Ha adjacent to each other in the diagonal direction.

A distance between a pair of second cell channel holes162H adjacent to each other in the diagonal direction at the third level LV3, e.g., in an inclined direction with respect to the first horizontal direction (X direction) and the second horizontal direction (Y direction), e.g., a second cell upper distance DCU2that is a distance between the uppermost ends of the pair of first cell channel holes162H adjacent to each other in the diagonal direction may be less than a distance between a pair of second cell channel holes162H adjacent to each other in the diagonal direction at the second level LV2, e.g., a second cell lower distance DCD2that is a distance between the lowermost ends of the pair of second cell channel holes162H adjacent to each other in the diagonal direction.

The distance between the pair of first cell channel holes152Ha adjacent to each other in the diagonal direction at the fourth level LV4, e.g., in an inclined direction with respect to the first horizontal direction (X direction) and the second horizontal direction (Y direction), e.g., a distance DCU1bof the pair of first cell channel holes152Ha adjacent to each other in the diagonal direction at the same level as the bottom surface of the first protective insulating layer114may be less than the first cell lower distance DCD1and greater than the first upper distance DCU1a.

The second cell upper distance DCU2may be greater than the first cell upper distance DCU1. In an implementation, the first cell bottom distance DCD1and the second cell bottom distance DCD2may have substantially the same value. In an implementation, according to the ratio of the height of the first stack ST1over the height of the second stack ST2in the vertical direction (Z direction), the first cell lower distance DCD1may be greater than the second cell lower distance DCD2, and the first cell lower distance DCD1may be less than the second cell lower distance DCD2.

In an implementation, the first cell upper width WCU1a, the second cell upper width WCU2, the first cell lower width WCD1, and the second cell lower width WCD2may be greater than the first dummy upper width WIU1a, the second dummy upper width WIU2, the first dummy lower width WID1, and the second dummy lower width WID2, respectively.

FIG.21illustrates a cross-sectional view of an integrated circuit device according to example embodiments.

Referring toFIG.21, the integrated circuit device3amay be generally similar to the integrated circuit device2aillustrated inFIG.18, except that the integrated circuit device3includes a plurality of cell channel structures150Cc filling a plurality of dummy channel holes including the first cell channel hole152Ha and the second cell channel hole162H that are communicatively connected to each other, instead of the plurality of cell channel structure150Ca filling the plurality of dummy channel holes including the first cell channel hole152H and the second cell channel hole162H that are communicatively connected to each other.

Each of the plurality of cell channel structures150Cc may be similar to the plurality of cell channel structures150Ca illustrated inFIG.18, except that the connection conductive plug layer158is formed in the expansion cell hole152E, and a repeated detailed description thereof may be omitted.

By way of summation and review, a vertical memory device may increase the degree of integration by increasing the number of stacks of memory cells in the vertical direction. As the number of stacks of memory cells in the vertical direction increases in the vertical memory devices, issues could occur in a fabrication process, and electrical reliability of the integrated circuit devices could be degraded.

One or more embodiments may provide an integrated circuit device having excellent electrical characteristics and an increased degree of integration.

One or more embodiments may provide an integrated circuit device including a non-volatile vertical memory device and a fabrication method of the integrated circuit device.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.