Patent ID: 12199057

DESCRIPTION OF EMBODIMENTS

The embodiments described below each show a specific example of the present disclosure. The numeral values, shapes, materials, constituent elements, the arrangement and connection of the constituent elements, etc. indicated in the following embodiments are mere examples, and therefore do not intend to limit the present disclosure.

In the present disclosure, the expression “A and B are electrically connected” includes a case in which A and B are directly connected via a wire, a case in which A and B are directly connected without a wire, and a case in which A and B are indirectly connected via a resistive component (a resistive element, a resistive wire).

Embodiment 1

[1. Structure of Semiconductor Device]

Hereinafter, a structure of a semiconductor device according to Embodiment 1 is described. The semiconductor device according to Embodiment 1 is a facedown mountable, chip-size-package (CSP) type semiconductor device in which two vertical metal-oxide semiconductor (MOS) transistors are provided on a semiconductor substrate. The above-described two vertical MOS transistors are power transistors and what is called trench MOS field-effect transistors (FETs).

FIG.1is a cross-sectional view illustrating an example of a structure of semiconductor device1according to Embodiment 1.FIG.2Ais a plan view illustrating an example of an arrangement of pads in semiconductor device1. The size and shape of semiconductor device1are an example except that semiconductor device1is in a rectangular shape. Additionally, the sizes, shapes, and arrangement of the pads are also an example.

FIG.1is a cross-sectional view taken along line I-I ofFIG.2A.

As shown inFIG.1andFIG.2A, semiconductor device1includes: semiconductor layer40; metal layer41; first vertical MOS transistor10(hereinafter also referred to as transistor10) that is provided in first region A1in semiconductor layer40; second vertical MOS transistor20(hereinafter also referred to as transistor20) that is provided in second region A2in semiconductor layer40; and third region A3that does not overlap first region A1and second region A2.

In the present disclosure, a semiconductor layer provided on semiconductor substrate32is referred to as semiconductor layer40with the inclusion of semiconductor substrate32. Semiconductor layer40is configured by stacking semiconductor substrate32and low-concentration impurity layer33. Semiconductor substrate32is disposed on a back surface side of semiconductor layer40, and includes silicon containing impurities of a first conductivity type. Low-concentration impurity layer33is an impurity layer of the first conductivity type that is disposed on a front surface side of semiconductor layer40, in contact with semiconductor substrate32, and contains impurities of the first conductivity type having a concentration lower than a concentration of the impurities of the first conductivity type contained in semiconductor substrate32. Low-concentration impurity layer33may be provided on semiconductor substrate32by, for example, epitaxial growth.

Metal layer41is provided in contact with the back surface side of semiconductor layer40, and includes silver (Ag) or copper (Cu). It should be noted that metal layer41may include a trace amount of chemical element other than metal mixed in as impurities in a step of manufacturing a metal material. Moreover, metal layer41may or may not be provided on an entire surface on the back surface side of semiconductor layer40.

As shown inFIG.1andFIG.2A, first body region18of a second conductivity type containing impurities of the second conductivity type is provided in first region A1of low-concentration impurity layer33, the second conductivity type being different from the first conductivity type. First source region14of the first conductivity type containing impurities of the first conductivity type is provided in first body region18. In first region A1, a plurality of first gate trenches17that penetrate through first source region14and first body region18from a top surface of semiconductor layer40to a depth that reaches a portion of low-concentration impurity layer33are provided, and first gate conductor15is further provided on first gate insulating film16inside each of the plurality of first gate trenches17.

First source electrode11includes portion12and portion13. Portion12is connected to first source region14and first body region18via portion13. First gate conductor15is an embedded gate electrode embedded inside semiconductor layer40, and is electrically connected to first gate pad119.

Portion12of first source electrode11is a layer joined with solder at the time of reflow in facedown mounting, and may comprise a metal material including at least one of nickel, titanium, tungsten, or palladium as a non-limiting example. The surface of portion12may be plated with gold etc.

Portion13of first source electrode11is a layer that connects portion12and semiconductor layer40, and may comprise a metal material including at least one of aluminum, copper, gold, or silver as a non-limiting example.

Second body region28of the second conductivity type containing impurities of the second conductivity type is provided in second region A2of low-concentration impurity layer33. Second source region24of the first conductivity type containing impurities of the first conductivity type is provided in second body region28. In second region A2, a plurality of second gate trenches27that penetrate through second source region24and second body region28from the top surface of semiconductor layer40to a depth that reaches a portion of low-concentration impurity layer33are provided, and second gate conductor25is further provided on second gate insulating film26inside each of the plurality of second gate trenches27.

Second source electrode21includes portion22and portion23. Portion22is connected to second source region24and second body region28via portion23. Second gate conductor25is an embedded gate electrode embedded inside semiconductor layer40, and is electrically connected to second gate pad129.

Portion22of second source electrode21is a layer joined with solder at the time of reflow in facedown mounting, and may comprise a metal material including at least one of nickel, titanium, tungsten, or palladium as a non-limiting example. The surface of portion22may be plated with gold etc.

Portion23of second source electrode21is a layer that connects portion22and semiconductor layer40, and may comprise a metal material including at least one of aluminum, copper, gold, or silver as a non-limiting example.

The above-described configurations of transistors10and20allow semiconductor substrate32and an area of low-concentration impurity layer33in proximity to a location immediately above semiconductor substrate32to serve as a common drain region having a first drain region of transistor10and a second drain region of transistor20in common. Moreover, metal layer41serves as a common drain electrode (hereinafter also referred to as a back-surface-side drain electrode) disposed on the back surface side of semiconductor layer40and having a drain electrode of transistor10and a drain electrode of transistor20in common.

As shown inFIG.1, first body region18is covered with interlayer insulating layer34having an opening, and portion13of first source electrode11is connected to first source region14via the opening of interlayer insulating layer34. Interlayer insulating layer34and portion13of first source electrode11are covered with passivation layer35having an opening, and portion12is connected to portion13of first source electrode11via the opening of passivation layer35.

Second body region28is covered with interlayer insulating layer34having an opening, and portion23of second source electrode21is connected to second source region24via the opening of interlayer insulating layer34. Interlayer insulating layer34and portion23of second source electrode21are covered with passivation layer35having an opening, and portion22is connected to portion23of second source electrode21via the opening of passivation layer35.

Accordingly, a plurality of first source pads111refer to a region in which first source electrode11is partially exposed to the surface of semiconductor device1, that is, a terminal portion; and a plurality of second source pads121refer to a region in which second source electrode21is partially exposed to the surface of semiconductor device1, that is, a terminal portion. Similarly, first gate pad119refers to a region in which first gate electrode19(not shown inFIG.1andFIG.2A) is partially exposed to the surface of semiconductor device1, that is, a terminal portion; and second gate pad129refers to a region in which second gate electrode29(not shown inFIG.1andFIG.2A) is partially exposed to the surface of semiconductor device1, that is, a terminal portion.

FIG.3Ais a cross-sectional view taken along line II-II ofFIG.2A. As shown inFIG.3A, in third region A3of low-concentration impurity layer33, drain lead-out region58of the first conductivity type containing impurities of the first conductivity type having a concentration higher than the concentration of the impurities of the first conductivity type contained in low-concentration impurity layer33is provided inside low-concentration impurity layer33. It should be noted that drain lead-out region58may be provided to a depth that reaches semiconductor substrate32, inside low-concentration impurity layer33.

Drain electrode51(hereinafter also referred to as a front-surface-side drain electrode) includes portion52and portion53. Portion52is connected to drain lead-out region58via portion53.

Portion52of drain electrode51is a layer joined with solder at the time of reflow in facedown mounting, and may comprise a metal material including at least one of nickel, titanium, tungsten, or palladium as a non-limiting example. The surface of portion52may be plated with gold etc.

Portion53of drain electrode51is a layer that connects portion52and drain lead-out region58. Accordingly, drain electrode51has a common drain potential of transistor10and transistor20. Moreover, portion53of drain electrode51may comprise a metal material including at least one of aluminum, copper, gold, or silver as a non-limiting example.

As shown inFIG.3A, low-concentration impurity layer33is covered with interlayer insulating layer34having an opening, and portion53of drain electrode51is connected to drain lead-out region58via the opening of interlayer insulating layer34. Interlayer insulating layer34and portion53of drain electrode51are covered with passivation layer35having an opening, and portion52is connected to portion53of drain electrode51via the opening of passivation layer35.

Accordingly, drain pad151refers to a region in which drain electrode51is partially exposed to the surface of semiconductor device1, that is, a terminal portion.

According to a standard design example of each structure in semiconductor device1, semiconductor layer40has a thickness of 10 to 90 μm, metal layer41has a thickness of 10 to 90 μm, and the sum of thicknesses of interlayer insulating layer34and passivation layer35is 3 to 13 μm.

As shown inFIG.1andFIG.2A, transistor10includes, on a front surface of semiconductor layer40, the plurality of first source pads111and first gate pad119that are joined to a mounting substrate via a bonding material at the time of facedown mounting. Moreover, transistor20includes, on the front surface of semiconductor layer40, the plurality of second source pads121and second gate pad129that are joined to the mounting substrate via the bonding material at the time of facedown mounting. In addition, third region A3includes, on the front surface of semiconductor layer40, drain pad151joined to the mounting substrate via the bonding material at the time of facedown mounting.

As shown inFIG.1andFIG.2A, semiconductor device1and semiconductor layer40are both in a rectangular shape in a plan view. It should be noted that although semiconductor device1and semiconductor layer40are both in the rectangular shape inFIG.2A, semiconductor device1and semiconductor layer40may be both in a square shape.

Among directions parallel to the outer peripheral sides of semiconductor device1in the plan view, a direction in which first region A1and second region A2are arranged is defined as a first direction. First region A1and second region A2being arranged in the first direction in the plan view means that first region A1and second region A2face each other most in the first direction.

Facing each other most in the first direction means that border line90C between first region A1and second region A2that is described later has a longest portion orthogonal to the first direction in the plan view. For example, when border line90C is in a crank shape in the plan view, border line90C is divided into constituent line segments, and a direction that is orthogonal to a direction in which the sum of line segments in the same direction is longest is defined as the first direction.

As shown inFIG.2A, in a plan view of semiconductor layer40, first region A1and second region A2are adjacent to each other, and are one region and an other region that divide an area of semiconductor layer40excluding third region A3in half.

As shown inFIG.2A, center line90is a line that divides semiconductor layer40in half in the first direction in the plan view of semiconductor layer40. Center line90is a straight line in a direction orthogonal to the first direction in the plan view of semiconductor layer40.

The center of third region A3of semiconductor layer40is located on center line90of semiconductor layer40in the plan view of semiconductor layer40. InFIG.2A, a center refers to the center of a circular shape such as drain pad151, to the point of intersection between the diagonal lines of a rectangular shape such as third region A3, and to the point of intersection between a long axis and a short axis of, for example, an elliptical shape.

Moreover, inFIG.2A, a dashed line indicates virtual border line90C that separates between first region A1, second region A2, and third region A3of semiconductor layer40. Border line90C in a region in which first region A1and second region A2are adjacent to each other may be viewed as a virtual line that passes through the middle position of a space between portion13of first source electrode11and portion23of second source electrode21. Additionally, border line90C may be viewed as the space having a finite width (even though border line90C is the space, it is possible to recognize the space as a line by the naked eye or external appearance at low magnification).

Border line90C in a region in which first region A1and third region A3are adjacent to each other may be viewed as a virtual line that passes through the middle position of a space between portion13of first source electrode11and portion53of drain electrode51. Additionally, border line90C may be viewed as the space having a finite width.

Border line90C in a region in which second region A2and third region A3are adjacent to each other may be viewed as a virtual line that passes through the middle position of a space between portion23of second source electrode21and portion53of drain electrode51. Additionally, border line90C may be viewed as the space having a finite width.

It should be noted that although border line90C divides the area of semiconductor layer40excluding third region A3in half in the plan view of semiconductor layer40, border line90C need not be a straight line. In addition, center line90and border line90C may at least partially coincide with each other in the plan view of semiconductor layer40.

Drain pad151is contained in third region A3of semiconductor layer40in the plan view of semiconductor layer40. In the example shown inFIG.2A, the center of drain pad151and the center of third region A3coincide with each other. Drain pad151need to be contained in third region A3, but the center of drain pad151and the center of third region A3need not coincide with each other.

In the plan view of semiconductor layer40, an area of third region A3of semiconductor layer40may be smaller than an area of first region A1and an area of second region A2. As will be described later, this is because the areas of first region A1and second region A2are required to be as large as possible to reduce conduction resistance of a primary pathway. In contrast, a secondary pathway in semiconductor device1may be capable of passing a relatively small current, and it is unnecessary to increase the area of third region A3. Typically, a shape of third region A3in the plan view may be a rectangular shape that externally touches drain pad151contained in third region A3, except for a setup margin, regardless of a shape of drain pad151.

Additionally, drain pad151is not necessarily limited to the shape exemplified inFIG.2A, and may be in a substantially circular shape as exemplified inFIG.2Aor a substantially rectangular shape.

The number of the plurality of first source pads111of transistor10and the number of the plurality of second source pads121of transistor20are not necessarily limited to five exemplified inFIG.2A, and may be a plural number other than five. Moreover, shapes of the plurality of first source pads111of transistor10and shapes of the plurality of second source pads121of transistor20are not necessarily limited to the substantially rectangular shapes exemplified inFIG.2A, and may be the substantially rectangular shapes exemplified inFIG.2Aor substantially circular shapes. Furthermore, an arrangement of the plurality of first source pads111of transistor10and an arrangement of the plurality of second source pads121of transistor20are not necessarily limited to the arrangements exemplified inFIG.2A.

The number of first gate pads119of transistor10and the number of second gate pads129of transistor20are not necessarily limited to one exemplified inFIG.2A, and may be a plural number greater than or equal to two. Moreover, a shape of first gate pad119and a shape of second gate pad129may or may not be a substantially circular shape as exemplified inFIG.2A. Furthermore, an arrangement of first gate pad119and an arrangement of second gate pad129are not necessarily limited to the arrangements exemplified inFIG.2A.

Although not shown inFIG.1andFIG.2A, in the plan view of semiconductor layer40, a first equipotential ring (EQR) that is electrically connected to a drain region of transistor10may be disposed on an outer peripheral side of first region A1. Similarly, in the plan view of semiconductor layer40, a second EQR that is electrically connected to a drain region of transistor20may be disposed on an outer peripheral side of second region A2. The first EQR and the second EQR may be shared in a portion in which transistor10and transistor20are adjacent to and face each other.

The first EQR is disposed in transistor10in expectation of a function to impede a leak current from flowing between an outside and first body region18. Moreover, the second EQR is disposed in transistor20in expectation of a function to impede a leak current from flowing between the outside and second body region28.

The first EQR and the second EQR may each comprise, as a non-limiting example, a metal material including at least one of aluminum, copper, gold, or silver. Moreover, the first EQR and the second EQR may be electrically connected to front-surface-side drain electrode51, or may be electrically connected to back-surface-side drain electrode41via semiconductor substrate32that is the common drain region.

[2. Operation of Semiconductor Device]

FIG.4AandFIG.4Bare a plan view and a perspective view of an approximate single unit configuration of transistor10or transistor20that is repeatedly formed in an X direction and a Y direction of semiconductor device1, respectively. For the sake of clarity, neitherFIG.4AnorFIG.4Billustrates semiconductor substrate32, metal layer41, passivation layer35, first source electrode11or second source electrode21, and interlayer insulating layer34.

The Y direction is a direction that is parallel to the top surface of semiconductor layer40and in which first gate trench17extends. The X direction is a direction that is parallel to the top surface of semiconductor layer40and orthogonal to the Y direction. A Z direction is a direction that is orthogonal to both the X direction and the Y direction and indicates a height direction of semiconductor device1.

In the following description, although directions are described according to the definitions above, the Y direction and the X direction may be interchanged. In other words, the X direction may be the direction that is parallel to the top surface of semiconductor layer40and in which first gate trench17extends. In this case, the Y direction is a direction that is parallel to the top surface of semiconductor layer40and orthogonal to the X direction.

As shown inFIG.4AandFIG.4B, transistor10includes first connector18athat electrically connects first body region18and first source electrode11. First connector18ais a region of first body region18in which first source region14is not provided, and contains the same impurities of the second conductivity type as those of first body region18. First source region14and first connector18aare alternately and periodically disposed in the Y direction. The same applies to transistor20.

In semiconductor device1, for example, assuming that the first conductivity type is N-type and the second conductivity type is P-type, first source region14, second source region24, drain lead-out region58, semiconductor substrate32, and low-concentration impurity layer33may be N-type semiconductors, and first body region18, first connector18a, second body region28, and second connector28amay be P-type semiconductors.

Moreover, in semiconductor device1, for example, assuming that the first conductivity type is P-type and the second conductivity type is N-type, first source region14, second source region24, drain lead-out region58, semiconductor substrate32, and low-concentration impurity layer33may be P-type semiconductors, and first body region18, first connector18a, second body region28, and second connector28amay be N-type semiconductors.

The following description illustrates a bidirectional conducting pathway in which a principal current of semiconductor device1shown inFIG.2Bflows, when, assuming that the first conductivity type is N-type and the second conductivity is P-type, transistors10and20are what is called N-channel transistors.

In semiconductor device1, when a high voltage and a low voltage are applied to first source electrode11and second source electrode21, respectively, and a voltage higher than or equal to a threshold value with reference to second source electrode21is applied to second gate electrode29(second gate conductor25), a conducting channel is formed in the vicinity of second gate insulating film26in second body region28. As a result, a principal current flows in a pathway from first source electrode11to first connector18ato first body region18to low-concentration impurity layer33to semiconductor substrate32to metal layer41to semiconductor substrate32to low-concentration impurity layer33to the conducting channel formed in second body region28to second source region24to second source electrode21, and semiconductor device1becomes conductive. This conducting pathway is referred to as a primary pathway in the present disclosure. A contact surface between first body region18and low-concentration impurity layer33in the primary pathway is a PN junction and serves as a body diode.

In semiconductor device1, when a high voltage and a low voltage are applied to second source electrode21and first source electrode11, respectively, and a voltage higher than or equal to a threshold value with reference to first source electrode11is applied to first gate electrode19(first gate conductor15), a conducting channel is formed in the vicinity of first gate insulating film16in first body region18. As a result, a principal current flows in a pathway from second source electrode21to second connector28ato second body region28to low-concentration impurity layer33to semiconductor substrate32to metal layer41to semiconductor substrate32to low-concentration impurity layer33to the conducting channel formed in first body region18to first source region14to first source electrode11, and semiconductor device1becomes conductive. This conducting pathway is also referred to as the primary pathway in the present disclosure. A contact surface between second body region28and low-concentration impurity layer33in the primary pathway is a PN junction and serves as a body diode.

Furthermore, in semiconductor device1, a conducting channel may be formed in the vicinity of first gate insulating film16in first body region18by applying a voltage higher than or equal to a threshold value to first gate electrode19; and at the same time, a conducting channel may be formed in the vicinity of second gate insulating film26in second body region28by applying a voltage higher than or equal to the threshold value to second gate electrode29. As a result, a principal current may flow in a pathway from first source electrode11to first source region14to the conducting channel formed in first body region18to low-concentration impurity layer33to semiconductor substrate32to metal layer41to semiconductor substrate32to low-concentration impurity layer33to the conducting channel formed in second body region28to second source region24to second source electrode21, or a principal current may flow in a reverse pathway, and semiconductor device1may become conductive. This bidirectional conducting pathway is also referred to as the primary pathway in the present disclosure.

It should be noted that the principal current and the primary pathway in the present disclosure are convenient designations to distinguish them from a secondary current and a secondary pathway to be described later.

FIG.3Bis a cross-sectional view illustrating a secondary current flowing through semiconductor device1. A secondary current refers to a current the conduction of which is controlled by an external switching element (e.g., a vertical MOS transistor of a single type) that is not shown inFIG.3Band is connected in series with drain electrode51of semiconductor device1, and is a relatively small current compared to the principal current. It should be noted that a conducting pathway in which the secondary current flows in semiconductor device1is referred to as the secondary pathway in the present disclosure.

In semiconductor device1, when a high voltage and a low voltage are applied to first source electrode11and drain electrode51, respectively, and the external switching element connected in series with drain electrode51becomes conductive, the secondary current flows in a pathway from first source electrode11to first connector18ato first body region18to low-concentration impurity layer33to semiconductor substrate32to metal layer41to semiconductor substrate32to low-concentration impurity layer33to drain lead-out region58to drain electrode51, and semiconductor device1becomes conductive. It should be noted that when a high voltage and a low voltage are applied to first source electrode11and drain electrode51, respectively, the external switching element becomes conductive, and a voltage higher than or equal to a threshold value with reference to first source electrode11is applied to first gate electrode19, a conducting channel is formed in the vicinity of first gate insulating film16in first body region18, the secondary current flows in a pathway from first source electrode11to first source region14to the conducting channel formed in first body region18to low-concentration impurity layer33to semiconductor substrate32to metal layer41to semiconductor substrate32to low-concentration impurity layer33to drain lead-out region58to drain electrode51, and semiconductor device1becomes conductive.

When a high voltage and a low voltage are applied to second source electrode21and drain electrode51, respectively, and the external switching element connected in series with drain electrode51becomes conductive, the secondary current flows in a pathway from second source electrode21to second connector28ato second body region28to low-concentration impurity layer33to semiconductor substrate32to metal layer41to semiconductor substrate32to low-concentration impurity layer33to drain lead-out region58to drain electrode51, and semiconductor device1becomes conductive. It should be noted that when a high voltage and a low voltage are applied to second source electrode21and drain electrode51, respectively, the external switching element becomes conductive, and a voltage higher than or equal to a threshold value with reference to second source electrode21is applied to second gate electrode29, a conducting channel is formed in the vicinity of second gate insulating film26in second body region28, the secondary current flows in a pathway from second source electrode21to second source region24to the conducting channel formed in second body region28to low-concentration impurity layer33to semiconductor substrate32to metal layer41to semiconductor substrate32to low-concentration impurity layer33to drain lead-out region58to drain electrode51, and semiconductor device1becomes conductive.

Those conducting pathways in which the secondary current flows are secondary pathways. A secondary pathway in semiconductor device1is controlled by causing the external switching element connected in series with drain electrode51to be conductive or non-conductive. When the switching element is conductive, the secondary pathway in semiconductor device1becomes conductive. It should be noted that a contact surface between first body region18and low-concentration impurity layer33and a contact surface between second body region28and low-concentration impurity layer33in the secondary pathway are each a PN junction and each serve as a body diode.

When the primary pathway becomes conductive, since it is necessary to cause the external switching element connected in series with drain electrode51to be non-conductive, the secondary pathway becomes non-conductive, and only the primary pathway becomes conductive.

FIG.2Cis a plan view illustrating an example of shapes of, among the constituent elements of semiconductor device1, first body region18, second body region28, first active region112, and second active region122in the plan view of semiconductor layer40. For the sake of clarity of a top surface structure of semiconductor layer40that cannot be actually viewed, passivation layer35, first source electrode11, first gate electrode19, second source electrode21, second gate electrode29, drain electrode51, and interlayer insulating layer34are omitted fromFIG.2Cas if they are transparent. In addition, first source region14, second source region24, and drain lead-out region58are also omitted from the figure.

In order to reduce conduction resistance of the primary pathway in semiconductor device1, it is necessary to cause first active region112and second active region122to be as broad as possible. First active region112refers to a minimum area that contains an entire portion in which a conducting channel is formed when a voltage higher than or equal to a threshold value is applied to first gate electrode19(first gate conductor15) of transistor10. The portion in which the conducting channel is formed is a portion in which each of the plurality of first gate trenches17is adjacent to first source region14. As shown inFIG.2C, first active region112is contained in first body region18in the plan view of semiconductor layer40. Second active region122refers to a minimum area that contains an entire portion in which a conducting channel is formed when a voltage higher than or equal to a threshold value is applied to second gate electrode29(second gate conductor25) of transistor20. The portion in which the conducting channel is formed is a portion in which each of the plurality of second gate trenches27is adjacent to second source region24. As shown inFIG.2C, second active region122is contained in second body region28in the plan view of semiconductor layer40.

Since the primary pathway expands when an area of first active region112and an area of second active region122are large, the conduction resistance of the primary pathway in semiconductor device1is reduced.

FIG.2Dis a plan view obtained by enlarging a portion in which first gate pad119shown inFIG.2Ais disposed.FIG.2Dis an example of shapes of, among the constituent elements of semiconductor device1, portion13of first source electrode11, first gate electrode19, and first gate pad119in the plan view of semiconductor layer40. For the sake of clarity of the top surface structure of semiconductor layer40that cannot be actually viewed, passivation layer35and interlayer insulating layer34are omitted fromFIG.2Das if they are transparent. In addition, first source region14is also omitted from the figure.

Although not shown in the figure, portion23of second source electrode21, second gate electrode29, and second gate pad129are each in a shape that is line-symmetrical to a corresponding one of portion13of first source electrode11, first gate electrode19, or first gate pad119shown inFIG.2Dwith reference to center line90as a symmetrical axis.

A region immediately below first gate electrode19and a proximate region of the region, and a region immediately below second gate electrode29and a proximate region of the region, are regions that do not contribute to conduction of the primary pathway. Here, the proximate regions are regions along the outer peripheries of first gate electrode19and second gate electrode29, and may be considered as a region between first gate electrode19and portion13of first source electrode11shown inFIG.2Dand a region between second gate electrode29and portion23of second source electrode21not shown in the figure.

Similarly, third region A3containing drain pad151is also a region that does not contribute to the conduction of the primary pathway.

To put it another way, in semiconductor device1, although the region immediately below first gate electrode19and the proximate region, the region immediately below second gate electrode29and the proximate region, and third region A3are regions necessary for semiconductor device1to function, they are regions the reduction of which is desired as much as possible in a limited device area to reduce the conduction resistance of the primary pathway in semiconductor device1.

[3. Application Example of Semiconductor Device]

FIG.5Ais a circuit diagram illustrating an application example in which semiconductor device1according to the present disclosure is applied to a protection circuit of lithium-ion battery5. In this application example, semiconductor device1controls bidirectional conduction that is a primary pathway in response to a control signal sent from control IC4to first gate electrode19and second gate electrode29, and controls a discharging operation from lithium-ion battery5to load6or a charging operation from load6to lithium-ion battery5. At this time, since charging current C1or discharging current C2that flows through semiconductor device1is a relatively large current, a secondary pathway is not used. When semiconductor device1according to the present disclosure is applied to a battery protection circuit, controlling bidirectional conduction of charging and discharging using the primary pathway is a main function of semiconductor device1in a manner. Since the primary pathway passes a relatively large current, the primary pathway may reduce conduction resistance as much as possible.

The use of the secondary pathway is next described with reference toFIG.5A. Semiconductor device1includes the secondary pathway in which drain electrode51is used, in addition to the primary pathway. Charging current C3flows in the secondary pathway at the time of precharging. When a voltage of lithium-ion battery5is in a state of overdischarge, it is dangerous to perform a charging operation using relatively large charging current C1that is the same as a current used in normal charging. The precharging refers to performing a charging operation using relatively small charging current C3.

InFIG.5A, since semiconductor device1alone is not capable of controlling conduction of the secondary pathway, external switching element S1(e.g., the vertical MOS transistor of the single type) that is capable of controlling a conducting state and a non-conducting state is connected in series with drain electrode51of semiconductor device1. The conducting state and the non-conducting state of external switching element S1are controlled by a control signal sent from control IC4. External switching element S1controls a charging operation from load6to lithium-ion battery5using relatively small charging current C3, by (i) causing the secondary pathway of semiconductor device1to be in the conducting state when switching element S1is in the conducting state and (ii) causing the secondary pathway of semiconductor device1to be in the non-conducting state when switching element S1is in the non-conducting state. It should be noted that when the primary pathway of semiconductor device1is conducted, it is necessary for external switching element S1to always be controlled in the non-conducting state.

In the precharging, charging is started using relatively small charging current C3, and is switched to a charging operation using relatively large charging current C1after lithium-ion battery5is charged to a certain level. Since the secondary pathway is required to only pass relatively small charging current C3, a reduction of conduction resistance in the secondary pathway is not emphasized.

FIG.5Bis an application example of semiconductor device1, and is a circuit diagram illustrating an application example in which semiconductor device1is applied to a protection circuit of lithium-ion battery5used in a lithium-ion battery pack, as withFIG.5A. Also inFIG.5B, a main function of semiconductor device1is the same as that illustrated inFIG.5A, that is, controlling charging current C1and discharging current C2. On the other hand,FIG.5Bdiffers fromFIG.5Ain the use of a secondary pathway. Drain electrode51of semiconductor device1is connected to control IC4, and is used as a monitor terminal for a drain voltage common to transistor10and transistor20. InFIG.5B, since the secondary pathway of semiconductor device1is connected to control IC4and caused to be in the non-conducting state by control IC4, a secondary current does not flow in the secondary pathway. When control IC4controls charging current C1and discharging current C2of lithium-ion battery5, control IC4monitors a voltage of drain electrode51using the secondary pathway. When the voltage of drain electrode51deviates from a normal voltage range of lithium-ion battery5, control IC4determines that lithium-ion battery5is in an abnormal state, and suspends a charging and discharging operation. This makes it possible to prevent lithium-ion battery5from being overdischarged and overcharged.

[4. Advantageous Effects of Semiconductor Device1According to Embodiment 1]

Above-described semiconductor device1in the present disclosure has the following characteristics.

Semiconductor device1according to one aspect of the present disclosure is facedown mountable, chip-size-package type semiconductor device1, semiconductor device1including: semiconductor substrate32; low-concentration impurity layer33that is provided on semiconductor substrate32; first vertical MOS transistor10that is provided in first region A1of semiconductor layer40that is a combination of semiconductor substrate32and low-concentration impurity layer33; second vertical MOS transistor20that is provided in second region A2adjacent to first region A1in a plan view of semiconductor layer40; a plurality of first source pads111that are provided in first region A1in the plan view and connected to first source electrode11of first vertical MOS transistor10; first gate pad119that is provided in first region A1in the plan view and connected to first gate electrode19of first vertical MOS transistor10; a plurality of second source pads121that are provided in second region A2in the plan view and connected to second source electrode21of second vertical MOS transistor20; second gate pad129that is provided in second region A2in the plan view and connected to second gate electrode29of second vertical MOS transistor20; and metal layer41that is provided in contact with a back surface of semiconductor substrate32. Semiconductor substrate32is a common drain region for first vertical MOS transistor10and second vertical MOS transistor20. In the plan view, semiconductor layer40is in a rectangular shape. In the plan view, first vertical MOS transistor10and second vertical MOS transistor20are arranged in a first direction. In the plan view, semiconductor layer40includes third region A3that does not overlap first region A1and second region A2. In the plan view, first region A1and second region A2are one region and an other region that divide an area of a region of semiconductor layer40excluding third region A3in half. In the plan view, a center of third region A3is located on center line90that is straight and orthogonal to the first direction and divides semiconductor layer40in half in the first direction. In the plan view, semiconductor layer40includes one drain pad151that is connected to the common drain region. In the plan view, drain pad151is contained in third region A3.

According to the above-described configuration, providing only one drain pad151that is a minimum necessary number for configuring a secondary pathway makes it possible to reduce an area of third region A3compared to a case in which a plurality of drain pads are provided, and providing the secondary pathway makes it possible to inhibit an increase in conduction resistance in a primary pathway as much as possible.

Moreover, in a plan view of semiconductor layer40, it is possible to dispose third region A3of semiconductor layer40on center line90of semiconductor layer40, and use to a certain degree a region that does not originally contribute to conduction of the primary pathway as a region in which drain pad151is disposed. For this reason, it is possible to inhibit an increase in conduction resistance of the primary pathway compared to a case in which third region A3is disposed in a location other than center line90in the plan view of semiconductor layer40.

Furthermore, since the center of third region A3is located on center line90of semiconductor layer40in the plan view of semiconductor layer40, even though third region A3(drain pad151) is disposed, it is difficult to prevent first active region112and second active region122from becoming identical in area and shape. Accordingly, a lack of balance in electrical characteristics of the bidirectional conduction and heat dissipation property between transistor10and transistor20is less likely to occur.

Since the principal current of semiconductor device1flows bidirectionally, as with the above-described configuration, transistor10and transistor20may include pad arrangements that are line-symmetrical with reference to border line90C as a symmetrical axis or point-symmetrical with reference to the center of semiconductor layer40as a point of symmetry. At this time, a lack of balance in electrical characteristics and heat dissipation property due to a difference in principal current direction is less likely to occur. For example, when a protection circuit that uses semiconductor device1is included in a lithium-ion battery pack of a smartphone or a tablet etc., either in charging or in discharging, it is unnecessary to make any special difference with regard to a conducting direction in semiconductor device1

Semiconductor device2according to a comparative example of Embodiment 1 is described with reference toFIG.6AandFIG.6B. Constituent elements of semiconductor device2according to the comparative example that are similar to those of semiconductor device1are assigned the same reference signs, and the detailed description thereof is omitted, because they have already been described.

In semiconductor device2, third region A3in the plan view of semiconductor layer40includes third vertical MOS transistor30(hereinafter also referred to as transistor30). Accordingly, semiconductor device2is semiconductor device2including a triple configuration in which three vertical MOS transistors (transistor10, transistor20, transistor30) each having a separate control function are provided inside one device.

Transistor30has a configuration similar to that of transistor10or transistor20. Semiconductor device2does not include drain pad151and drain lead-out region58included in semiconductor device1according to Embodiment 1.

Transistor30includes third source pad131and third gate pad139in the surface (third region A3) of semiconductor layer40. A drain region of transistor30is commonized along with the drain regions of transistor10and transistor20.

FIG.6Bis a circuit diagram illustrating an application example in which semiconductor device2according to the comparative example is applied to the same protection circuit of lithium-ion battery5as illustrated inFIG.5A. A main function of semiconductor device2inFIG.6Bis the same as that of semiconductor device1according to Embodiment 1 (FIG.5A). On the other hand, a secondary pathway of semiconductor device2according to the comparative example is a pathway from first source electrode11of transistor10through the inside of semiconductor device2to third source electrode31of transistor30. Alternatively, the secondary pathway is a pathway from second source electrode21of transistor20through the inside of semiconductor device2to third source electrode31of transistor30.

InFIG.6B, conduction of the secondary pathway of semiconductor device2is controlled by a control signal sent from control IC4to third gate electrode39of transistor30. In other words, semiconductor device2according to the comparative example has a function of controlling the conduction of the secondary pathway. For this reason, external switching element S1that is necessary in Embodiment 1 (FIG.5A) is unnecessary.

A comparison between the secondary pathway in semiconductor device1according to Embodiment 1 and the secondary pathway in semiconductor device2according to the comparative example shows that semiconductor device1according to Embodiment 1 makes it possible to reduce an area of semiconductor device1as much as semiconductor device1does not have the control function in the secondary pathway. Alternatively, since it is possible to increase an area used as the primary pathway as much as the reduction, it is possible to reduce conduction resistance of the primary pathway.

FIG.7AtoFIG.7D,FIG.8AtoFIG.8D,FIG.9A,FIG.9B, andFIG.10AtoFIG.10Care each a plan view illustrating an example of an arrangement of pads that satisfies conditions for semiconductor device1according to Embodiment 1.

As shown inFIG.7AtoFIG.7D, the center of third region A3may be located on center line90of semiconductor layer40in the plan view of semiconductor layer40, first region A1and second region A2need not be disposed between third region A3and an outer peripheral side of semiconductor layer40that is closest to third region A3and parallel to the first direction, and drain pad151may be contained in third region A3.

According to the above-described configuration, in the plan view of semiconductor layer40, it is possible to dispose drain pad151as close as possible to an outer peripheral side of semiconductor layer40. For this reason, it is possible to reduce the possibility of a solder joint defect occurring due to warpage occurring in semiconductor device1, compared to a case in which drain pad151is disposed at the center of semiconductor layer40.

The following describes warpage of semiconductor layer1. Thinning semiconductor layer40(mainly semiconductor substrate32) that is a resistance component for the principal current that flows in the vertical direction inFIG.2Bis effective as a means to reduce conduction resistance of semiconductor device1. Moreover, thickening metal layer41is also useful in reducing the conduction resistance. In other words, thinning semiconductor layer40and thickening metal layer41are effective in reducing the conduction resistance in semiconductor device1. However, when semiconductor layer40and metal layer41become similar in thickness, warpage that occurs in semiconductor device1increases at high temperatures due to a difference in physical property value, such as a thermal expansion coefficient or a Young's modulus, between a semiconductor and a metal.

Warpage that occurs in semiconductor device1mainly occurs in a high-temperature environment when heat treatment is performed at approximately 250 degrees Celsius at the time of reflow in facedown mounting. In the facedown mounting, since metal layer41expands more than semiconductor layer40at high temperatures, warpage that protrudes in a direction away from the mounting substrate occurs.

As shown inFIG.11, warpage of semiconductor device1causes inconvenience when semiconductor device1is mounted. A deficiency of solder in the vicinity of the center of semiconductor device1that corresponds to the protruding portion can cause a joint defect (insufficient spread of solder). In contrast, since force for pushing in a mounting substrate direction increases in an outer peripheral region of semiconductor device1due to the warpage, a phenomenon (solder protrusion) in which solder protrudes from a region in which the solder should be originally contained is found.

When semiconductor layer40is in a rectangular shape, although warpage that occurs in semiconductor device1curves semiconductor layer40most significantly in a direction parallel to a longer side of semiconductor layer40, the warpage also curves semiconductor layer40slightly in a direction parallel to a shorter side of semiconductor layer40.

The warpage of semiconductor device1that occurs at high temperatures in reflow soldering is warpage that occurs in a central portion of semiconductor40and protrudes in the direction away from the mounting substrate. Although a deficiency of solder in the vicinity of the center of semiconductor device1that corresponds to the protruding portion can cause a joint defect, since drain pad151is disposed in an outer peripheral portion of semiconductor layer40by causing semiconductor device1to be configured as shown in each ofFIG.7AtoFIG.7D, it is possible to reduce the possibility of a solder joint defect occurring due to the warpage of semiconductor device1, compared to a case in which drain pad151is disposed in the central portion of semiconductor layer40.

In particular, when semiconductor layer40is in a rectangular shape that has a longer side in a direction orthogonal to the first direction as shown inFIG.7B,FIG.7C, andFIG.7D, semiconductor layer40is effective in preventing a solder joint defect.

As shown inFIG.8AtoFIG.8D, in the plan view of semiconductor layer40, the center of third region A3may be located on the center line of semiconductor layer40and coincide with the point of intersection between two diagonal lines of semiconductor layer40, and drain pad151may be contained in third region A3.

According to the above-described configuration, compared to the pad arrangements shown inFIG.7AtoFIG.7D, it is possible to inhibit a solder protrusion mounting defect due to warpage of semiconductor device1that occurs at high temperatures in reflow soldering.

Since the warpage of semiconductor device1that occurs at high temperatures in reflow soldering curves semiconductor layer40in a direction parallel to the longer side of semiconductor layer40, solder is pressed down more strongly to a mounting substrate side than to a central portion of semiconductor device1in a region close to one shorter side of semiconductor layer40and a region close to an other shorter side of semiconductor layer40, and a solder protrusion mounting defect occurs.

However, since drain pad151is disposed in the central portion of semiconductor layer40by causing semiconductor device1to be configured as shown in each ofFIG.8AtoFIG.8D, it is possible to inhibit a solder protrusion mounting defect due to the warpage of semiconductor device1, compared to a case in which drain pad151is disposed in the outer peripheral portion of semiconductor layer40.

In particular, when semiconductor layer40is in a rectangular shape that has a longer side in a direction orthogonal to the first direction as shown inFIG.8D, semiconductor layer40is effective in preventing a solder protrusion mounting defect, compared to a case in which drain pad151is disposed closest to the outer peripheral side of semiconductor layer40.

It should be noted that, in addition to the above-described configuration, in the plan view of semiconductor layer40, first gate pad119, second gate pad129, and drain pad151may each be in a circular shape, have the same diameter, and have the smallest area among pads included in semiconductor layer40.

According to the above-described configuration, in the plan view of semiconductor layer40, it is possible to minimize an area of a region that does not contribute to conduction of the primary pathway in semiconductor device1. For this reason, it is possible to inhibit an increase in conduction resistance of the primary pathway by providing the secondary pathway.

It should be noted that drain pad151is not limited to circular shapes as shown inFIG.7AtoFIG.7DandFIG.8AtoFIG.8D. As shown inFIG.9AandFIG.9B, drain pad151may be in a substantially rectangular shape. A substantially rectangular shape is a generic term that includes not only a rectangle having an end shape that is rectangular but also a semicircle or a polygon.

InFIG.9AandFIG.9B, in the plan view of semiconductor layer40, first gate pad119and second gate pad129are each in a circular shape and have the same diameter, and first gate pad119, second gate pad129, and drain pad151are contained in the same stripe-shaped region.

Since an arrangement as shown inFIG.9Amakes it possible to dispose, within the same width in the first direction, first gate pad119, second gate pad129, and drain pad151that block the principal current flowing bidirectionally in the first direction in a plan view, it is possible to prevent each of first gate pad119, second gate pad129, and drain pad151from becoming a factor in individually blocking the conduction of the principal current. In addition, since an arrangement as shown inFIG.9Bmakes it possible to dispose first gate pad119, second gate pad129, and drain pad151in the region that does not originally contribute to the conduction of the primary pathway, it is possible to prevent each of first gate pad119, second gate pad129, and drain pad151from becoming a factor for the increase in conduction resistance of the principal current.

Moreover, as shown inFIG.10AtoFIG.10C, in addition to the examples shown inFIG.7AtoFIG.7D, in the plan view of semiconductor layer40, semiconductor layer40may be in a rectangular shape, drain pad151may be in a substantially rectangular shape, and a longitudinal direction of drain pad151, center line90of semiconductor device1, and a longitudinal direction of semiconductor layer40may be parallel to each other.

Since center line90and border line90C usually coincide for the most part in the plan view of semiconductor layer40, the above-described configuration makes it possible to use third region A3of semiconductor layer40that is the region that does not originally contribute to the conduction of the primary pathway, as a region in which drain pad151is disposed, and inhibit the increase in conduction resistance of the primary pathway.

Furthermore, it is possible to inhibit the solder protrusion mounting defect due to the warpage of semiconductor device1that occurs at high temperatures in reflow soldering. In the case where semiconductor layer40is in a rectangular shape that has a longer side in a direction orthogonal to the first direction, when drain pad151is in a substantially rectangular shape that has a longitudinal direction in a direction parallel to a longitudinal direction of semiconductor layer40, the longitudinal direction of drain pad151is parallel to a direction of solder pressed out by the warpage of semiconductor device1that occurs at high temperatures in the reflow soldering. Accordingly, it is possible to inhibit solder protrusion, and alleviate the influence of the warpage of semiconductor device1that occurs at high temperatures in the reflow soldering on a mounting defect.

Embodiment 2

Semiconductor device1A according to Embodiment 2 that is configured by changing part of semiconductor device1according to Embodiment 1 is described below. Constituent elements of semiconductor device1A according to Embodiment 2 that are similar to those of semiconductor device1are assigned the same reference signs, and the detailed description thereof is omitted, because they have already been described. The following mainly describes differences from semiconductor device1.

FIG.12Ais a plan view illustrating an example of an arrangement of pads in semiconductor device1A according to Embodiment 2. The size and shape of semiconductor device1A are an example except that semiconductor device1A is in a rectangular shape. Additionally, the sizes, shapes, and arrangement of the pads are also an example. A cross section along line I-I inFIG.12Ais equivalent toFIG.1illustrating the cross section along line I-I inFIG.2Aillustrating the example of the arrangement of the pads in semiconductor device1according to Embodiment 1.

Transistor10of semiconductor device1according to Embodiment 1 inFIG.1corresponds to first vertical MOS transistor10A (hereinafter also referred to as transistor10A) in semiconductor device1A according to Embodiment 2 shown inFIG.12B.

Similarly, transistor20of semiconductor device1according to Embodiment 1 inFIG.1corresponds to second vertical MOS transistor20A (hereinafter also referred to as transistor20A) in semiconductor device1A according to Embodiment 2 shown inFIG.12B.

First region A1and second region A2of semiconductor device1according to Embodiment 1 inFIG.2Acorrespond to first region A1A and second region A2A in semiconductor device1A according to Embodiment 2 shown inFIG.12A, respectively.

Moreover, the plurality of first source pads111and first gate pad119of semiconductor device1according to Embodiment 1 inFIG.2Acorrespond to a plurality of first source pads111A and first gate pad119A in semiconductor device1A according to Embodiment 2 shown inFIG.12A, respectively.

Similarly, the plurality of second source pads121and second gate pad129of semiconductor device1according to Embodiment 1 inFIG.2Acorrespond to a plurality of second source pads121A and second gate pad129A in semiconductor device1A according to Embodiment 2 shown inFIG.12A, respectively.

As shown inFIG.12AandFIG.1, semiconductor device1A includes: semiconductor layer40; metal layer41; transistor10A provided in first region A1A in semiconductor layer40; and transistor20A provided in second region A2A in semiconductor layer40. Semiconductor device1A according to Embodiment 2 differs from semiconductor device1according to Embodiment 1 in not including third region A3.

As shown inFIG.12A,FIG.12B, andFIG.1, first region A1A of semiconductor device1A according to Embodiment 2 includes first drain electrode51A in addition to the constituent elements of first region A1of semiconductor device1according to Embodiment 1.

Similarly, second region A2A of semiconductor device1A includes second drain electrode61A in addition to the constituent elements of second region A2of semiconductor device1according to Embodiment 1.

A cross section along line II-II inFIG.12A, that is, a cross section of first drain electrode51A is equivalent to that inFIG.3A. It should be noted that the same applies to a cross section of second drain electrode61A.

Portion52of semiconductor device1according to Embodiment 1 inFIG.3Acorresponds to portion52A and portion62A in semiconductor device1A according to Embodiment 2.

Furthermore, portion53of semiconductor device1according to Embodiment 1 inFIG.3Acorresponds to portion53A and portion63A in semiconductor device1A according to Embodiment 2.

Similarly, drain electrode51including portion52and portion53of semiconductor device1according to Embodiment 1 inFIG.3Acorresponds to first drain electrode51A that includes portion52A and portion53A and second drain electrode61A that includes portion62A and portion63A in semiconductor device1A according to Embodiment 2.

Moreover, drain lead-out region58of semiconductor device1according to Embodiment 1 inFIG.3Acorresponds to first drain lead-out region58A and second drain lead-out region68A in semiconductor device1A according to Embodiment 2.

First drain lead-out region58A of the first conductivity type containing impurities of the first conductivity type having a concentration higher than a concentration of impurities of the first conductivity type in low-concentration impurity layer33of first region A1A is provided inside low-concentration impurity layer33of first region A1A. It should be noted that first drain lead-out region58A may be provided to a depth that reaches semiconductor substrate32, inside low-concentration impurity layer33.

First drain electrode51A includes portion52A and portion53A. Portion52A is connected to first drain lead-out region58A via portion53A.

Portion52A of first drain electrode51A is a layer joined with solder at the time of reflow in facedown mounting, and may comprise a metal material including at least one of nickel, titanium, tungsten, or palladium as a non-limiting example. The surface of portion52A may be plated with gold etc.

Portion53A of first drain electrode51A is a layer that connects portion52A and first drain lead-out region58A. Accordingly, first drain electrode51A has the same electric potential as a common drain region between transistor10A and transistor20A. Moreover, portion53A of first drain electrode51A may comprise, as a non-limiting example, a metal material including at least one of aluminum, copper, gold, or silver.

As shown inFIG.3AandFIG.12B, low-concentration impurity layer33is covered with interlayer insulating layer34having an opening, and portion53A of first drain electrode51A is connected to first drain lead-out region58A via the opening of interlayer insulating layer34. Interlayer insulating layer34and portion53A of first drain electrode51A are covered with passivation layer35having an opening, and portion52A is connected to portion53A of first drain electrode51A via the opening of passivation layer35.

Accordingly, first drain pad151A refers to a region in which first drain electrode51A is partially exposed to the surface of semiconductor device1A, that is, a terminal portion.

Similarly, second drain lead-out region68A of the first conductivity type containing impurities of the first conductivity type having a concentration higher than a concentration of impurities of the first conductivity type in low-concentration impurity layer33of second region A2A is provided inside low-concentration impurity layer33of second region A2A. It should be noted that second drain lead-out region68A may be provided to a depth that reaches semiconductor substrate32, inside low-concentration impurity layer33.

Second drain electrode61A includes portion62A and portion63A. Portion62A is connected to second drain lead-out region68A via portion63A.

Portion62A of second drain electrode61A is a layer joined with solder at the time of reflow in facedown mounting, and may comprise a metal material including at least one of nickel, titanium, tungsten, or palladium as a non-limiting example. The surface of portion62A may be plated with gold etc.

Portion63A of second drain electrode61A is a layer that connects portion62A and second drain lead-out region68A. Accordingly, second drain electrode61A has the same electric potential as the common drain region between transistor10A and transistor20A. Moreover, portion63A of second drain electrode61A may comprise, as a non-limiting example, a metal material including at least one of aluminum, copper, gold, or silver.

As shown inFIG.3AandFIG.12B, low-concentration impurity layer33is covered with interlayer insulating layer34having an opening, and portion63A of second drain electrode61A is connected to second drain lead-out region68A via the opening of interlayer insulating layer34. Interlayer insulating layer34and portion63A of second drain electrode61A are covered with passivation layer35having an opening, and portion62A is connected to portion63A of second drain electrode61A via the opening of passivation layer35.

Accordingly, second drain pad161A refers to a region in which second drain electrode61A is partially exposed to the surface of semiconductor device1A, that is, a terminal portion.

As shown inFIG.1,FIG.3A, andFIG.12A, transistor10A includes, on the front surface of semiconductor layer40, a plurality of first source pads111A, first gate pad119A, and first drain pad151A that are joined to the mounting substrate via a bonding material at the time of facedown mounting. Additionally, transistor20A includes, on the front surface of semiconductor layer40, a plurality of second source pads121A, second gate pad129A, and second drain pad161A that are joined to the mounting substrate via the bonding material at the time of facedown mounting.

As shown inFIG.1andFIG.12A, semiconductor device1A and semiconductor layer40are each in a rectangular shape in a plan view. It should be noted that although semiconductor device1A and semiconductor layer40are each in the rectangular shape inFIG.12A, semiconductor device1A and semiconductor layer40may each be in a square shape.

Among directions parallel to the outer peripheral sides of semiconductor device1A in the plan view, a direction in which first region A1A and second region A2A are arranged is defined as a first direction. First region A1A and second region A2A being arranged in the first direction in the plan view means that first region A1A and second region A2A face each other most in the first direction.

Facing each other most in the first direction means that border line90C between first region A1A and second region A2A that is described later has a longest portion orthogonal to the first direction in the plan view. For example, when border line90C is in a crank shape in the plan view, border line90C is divided into constituent line segments, and a direction that is orthogonal to a direction in which the sum of line segments in the same direction is longest is defined as the first direction.

As shown inFIG.12A, in the plan view of semiconductor layer40, first region A1A and second region A2A are one region and an other region that are adjacent to each other and divide an area of semiconductor layer40in half.

As shown inFIG.12A, center line90is a line that divides semiconductor layer40in half in the first direction in the plan view of semiconductor layer40. Accordingly, center line90is a straight line in a direction orthogonal to the first direction in the plan view of semiconductor layer40.

Moreover, in the plan view of semiconductor layer40, a middle point of a line segment that connects the center of first gate pad119A of transistor10A and the center of second gate pad129A of transistor20A is located on border line90C of semiconductor device1A.

Furthermore, in the plan view of semiconductor layer40, a middle point of a line segment that connects the center of first drain pad151A of transistor10A and the center of second drain pad161A of transistor20A is located on border line90C of semiconductor device1A.

Moreover, as shown inFIG.12A, no portion of first source pad111A is disposed between first gate pad119A and first drain pad151A. Accordingly, first gate pad119A and first drain pad151A are disposed adjacent to each other.

Similarly, no portion of second source pad121A is disposed between second gate pad129A and second drain pad161A. Accordingly, second gate pad129A and second drain pad161A are disposed adjacent to each other.

As shown inFIG.12A, in the plan view of semiconductor layer40, first gate pad119A and second gate pad129A of semiconductor device1A are in the same shape and have the same area. In addition, first drain pad151A and second drain pad161A are in the same shape and have the same area.

It should be noted that, as inFIG.12A, first gate pad119A, second gate pad129A, first drain pad151A, and second drain pad161A may be in the same shape and have the same area.

A principal current and a primary pathway of semiconductor device1A according to Embodiment 2 are similar to those of semiconductor device1according to Embodiment 1.

FIG.12Bis a cross-sectional view illustrating a secondary current flowing through semiconductor device1A. The secondary current of semiconductor device1A is similar to that of semiconductor device1according to Embodiment 1, is a current the conduction of which is controlled by an external switching element connected in series with first drain electrode51A and second drain electrode61A of semiconductor device1A, and is a relatively small current compared to the principal current. A conducting pathway for the secondary current of semiconductor device1A is described below.

In semiconductor device1A, when a high voltage is applied to first source electrode11, a low voltage is applied to first drain electrode51A and second drain electrode61A, and the external switching element connected in series with first drain electrode51A and second drain electrode61A becomes conductive, the secondary current flows in a pathway from first source electrode11to first connector18ato first body region18to low-concentration impurity layer33to semiconductor substrate32to metal layer41to semiconductor substrate32to low-concentration impurity layer33to first drain lead-out region58A to first drain electrode51A, and semiconductor device1A becomes conductive. It should be noted that at this time the secondary current may also flow in a pathway from first source electrode11to first connector18ato first body region18to low-concentration impurity layer33to semiconductor substrate32to metal layer41to semiconductor substrate32to low-concentration impurity layer33to second drain lead-out region68A to second drain electrode61A.

Moreover, when a high voltage is applied to first source electrode11, a low voltage is applied to first drain electrode51A and second drain electrode61A, the external switching element becomes conductive, and a voltage higher than or equal to a threshold value with reference to first source electrode11is applied to first gate electrode19, a conducting channel is formed in the vicinity of first gate insulating film16in first body region18, the secondary current flows in a pathway from first source electrode11to first source region14to the conducting channel formed in first body region18to low-concentration impurity layer33to semiconductor substrate32to metal layer41to semiconductor substrate32to low-concentration impurity layer33and then in a pathway from first drain lead-out region58A to first drain electrode51A or a pathway from second drain lead-out region68A to second drain electrode61A, and semiconductor device1A becomes conductive.

Similarly, when a high voltage is applied to second source electrode21, a low voltage is applied to first drain electrode51A and second drain electrode61A, and the external switching element connected in series with first drain electrode51A and second drain electrode61A becomes conductive, the secondary current flows in a pathway from second source electrode21to second connector28ato second body region28to low-concentration impurity layer33to semiconductor substrate32to metal layer41to semiconductor substrate32to low-concentration impurity layer33to second drain lead-out region68A to second drain electrode61A, and semiconductor device1A becomes conductive. It should be noted that at this time the secondary current may also flow in a pathway from second source electrode21to second connector28ato second body region28to low-concentration impurity layer33to semiconductor substrate32to metal layer41to semiconductor substrate32to low-concentration impurity layer33to first drain lead-out region58A to first drain electrode51A.

Furthermore, when a high voltage is applied to second source electrode21, a low voltage is applied to first drain electrode51A and second drain electrode61A, the external switching element becomes conductive, and a voltage higher than or equal to a threshold value with reference to second source electrode21is applied to second gate electrode29, a conducting channel is formed in the vicinity of second gate insulating film26in second body region28, the secondary current flows in a pathway from second source electrode21to second source region24to the conducting channel formed in second body region28to low-concentration impurity layer33to semiconductor substrate32to metal layer41to semiconductor substrate32to low-concentration impurity layer33and then in a pathway from second drain lead-out region68A to second drain electrode61A or a pathway from first drain lead-out region58A to first drain electrode51A, and semiconductor device1A becomes conductive.

Those conducting pathways in which the secondary current flows are secondary pathways in semiconductor device1A. A secondary pathway in semiconductor device1A is controlled by causing the external switching element connected in series with first drain electrode51A and second drain electrode61A to be conductive or non-conductive. When the switching element is conductive, the secondary pathway in semiconductor device1A becomes conductive.

When the primary pathway becomes conductive, since it is necessary to cause the external switching element connected in series with first drain electrode51A and second drain electrode61A to be non-conductive, the secondary pathway becomes non-conductive, and only the primary pathway becomes conductive.

FIG.12Cis a plan view obtained by enlarging a portion in which first drain pad151A and first gate pad119A shown inFIG.12Aare disposed.FIG.12Cis an example of shapes of, among the constituent elements of semiconductor device1A, portion13of first source electrode11, portion53A of first drain electrode51A, first drain pad151A, first gate electrode19, first gate pad119A, the first EQR, and a first gate resistive element in the plan view of semiconductor layer40.

The gate resistive element is electrically connected to a gate electrode, and is disposed in expectation of a protective function that prevent transistor from breaking down when an excess voltage is applied to the gate electrode. In other words, the gate resistive element is an element disposed to improve electrostatic discharge (ESD) tolerance.

It should be noted that a gate resistive element and an EQR are not necessarily disposed, and may or may not be disposed in the semiconductor device according to the present disclosure.

For the sake of clarity of the top surface structure of semiconductor layer40that cannot be actually viewed, passivation layer35and interlayer insulating layer34are omitted fromFIG.12Cas if they are transparent. In addition, first source region14and first drain lead-out region58A are also omitted from the figure.

Although not shown in the figure, portion23of second source electrode21, portion63A of second drain electrode61A, second drain pad161A, second gate electrode29, second gate pad129A, the second EQR, and a second gate resistive element are each in a shape that is line-symmetrical to a corresponding one of portion13of first source electrode11, portion53A of first drain electrode51A, first drain pad151A, first gate electrode19, first gate pad119A, the first EQR, or the first gate resistive element shown inFIG.12Cwith reference to center line90as a symmetrical axis.

A region immediately below first drain electrode51A and a proximate region of the region, and a region immediately below second drain electrode61A and a proximate region of the region, are regions that do not contribute to conduction of the primary pathway. Here, the proximate regions are regions along the outer peripheries of first drain electrode51A and second drain electrode61A, and may be considered as a region between portion53A of first drain electrode51A and portion13of first source electrode11shown inFIG.12Cand a region between portion63A of second drain electrode61A and portion23of second source electrode21not shown in the figure.

To put it another way, in semiconductor device1A, although a region immediately below first gate electrode19and a proximate region of the region, the region immediately below first drain electrode51A and the proximate region, a region immediately below second gate electrode29and a proximate region of the region, and the region immediately below second drain electrode61A and the proximate region, are regions necessary for semiconductor device1A to function, they are regions the reduction of which is desired as much as possible in a limited device area to reduce the conduction resistance of the primary pathway in semiconductor device1A.

It should be noted that, as shown inFIG.12C, the first gate resistive element may be disposed at a position between first gate pad119A and first drain pad151A in the plan view of semiconductor layer40. Additionally, portion53A of first drain electrode51A and the first EQR may be directly connected to each other.

Similarly, although not shown in the figure, the second gate resistive element may be disposed at a position between second gate pad129A and second drain pad161A in the plan view of semiconductor layer40. Additionally, portion63A of second drain electrode61A and the second EQR may be directly connected to each other.

Above-described semiconductor device1A in the present disclosure has the following characteristics.

Semiconductor device1A according to one aspect of the present disclosure is facedown mountable, chip-size-package type semiconductor device1A, semiconductor device1A including: semiconductor substrate32; low-concentration impurity layer33that is provided on semiconductor substrate32; first vertical MOS transistor10A that is provided in first region A1A of semiconductor layer40that is a combination of semiconductor substrate32and low-concentration impurity layer33; second vertical MOS transistor20A that is provided in second region A2A adjacent to first region A1A in a plan view of semiconductor layer40; a plurality of first source pads111A that are provided in first region A1A in the plan view and connected to first source electrode11of first vertical MOS transistor10A; first gate pad119A that is provided in first region A1A in the plan view and connected to first gate electrode19of first vertical MOS transistor10A; first drain pad151A that is provided in first region A1A in the plan view and connected to first drain electrode51A of first vertical MOS transistor10A; a plurality of second source pads121A that are provided in second region A2A in the plan view and connected to second source electrode21of second vertical MOS transistor20A; second gate pad129A that is provided in second region A2A in the plan view and connected to second gate electrode29of second vertical MOS transistor20A; second drain pad161A that is provided in second region A2A in the plan view and connected to second drain electrode61A of second vertical MOS transistor20A; and metal layer41that is provided in contact with a back surface of semiconductor substrate32. Semiconductor substrate32is a common drain region for first vertical MOS transistor10A and second vertical MOS transistor20A. In the plan view, semiconductor layer40is in a rectangular shape. In the plan view, first region A1A and second region A2A are one region and an other region that divide an area of semiconductor layer40in half. In the plan view, a middle point of a line segment that connects a center of first gate pad119A and a center of second gate pad129A is located on border line90C between first region A1A and second region A2A. In the plan view, a middle point of a line segment that connects a center of first drain pad151A and a center of second drain pad161A is located on border line90C. No portion of first source pad111A is disposed between first gate pad119A and first drain pad151A. No portion of second source pad121A is disposed between second gate pad129A and second drain pad161A.

FIG.13AtoFIG.13C,FIG.14AtoFIG.14D,FIG.15A,FIG.15B, andFIG.16AtoFIG.16Dare each a plan view illustrating an example of an arrangement of pads that satisfies conditions for semiconductor device1A according to Embodiment 2.

According to the above-described configuration, in the plan view of semiconductor layer40, first gate pad119A and first drain pad151A are disposed adjacent to each other, and second gate pad129A and second drain pad161A are disposed adjacent to each other. Since a current density of the principal current is originally unlikely to increase relatively in a region around first gate pad119A and a region around first drain pad151A even though the regions are first active region112, when it is possible to dispose first gate pad119A and first drain pad151A adjacent to each other, it is possible to expand an area that first active region112is capable of being used effectively, compared to a case in which first gate pad119A and first drain pad151A are disposed apart from each other. Similarly, when it is possible to dispose second gate pad129A and second drain pad161A adjacent to each other, it is possible to expand an area that second active region122is capable of being used effectively, compared to a case in which second gate pad129A and second drain pad161A are disposed apart from each other. For this reason, it is possible to inhibit an increase in conduction resistance of the primary pathway due to the inclusion of the secondary pathway as much as possible.

Moreover, since it is possible to dispose first gate pad119A, first drain pad151A, second gate pad129A, and second drain pad161A to cause (i) first gate pad119A and second gate pad129A and (ii) first drain pad151A and second drain pad161A to be line-symmetrical with reference to border line90C as a symmetrical axis or point-symmetrical with reference to the center of semiconductor layer40as a point of symmetry in the plan view of semiconductor layer40, even though the secondary pathway is provided, it is difficult to prevent first active region112and second active region122from becoming identical in area and shape. Accordingly, a lack of balance in electrical characteristics of the bidirectional conduction and heat dissipation property between transistor10A and transistor20A is less likely to occur.

As shown inFIG.14AtoFIG.14D, first drain pad151A and first gate pad119A may be arranged in a direction parallel to border line90C, and no portion of an other pad may be disposed between first drain pad151A and an outer peripheral side of semiconductor layer40closest to first drain pad151A.

Similarly, second drain pad161A and second gate pad129A may be arranged in the direction parallel to border line90C, and no portion of an other pad may be disposed between second drain pad161A and an outer peripheral side of semiconductor layer40closest to second drain pad161A.

According to the above-described configuration, since it is possible to dispose first drain pad151A, first gate pad119A, second drain pad161A, and second gate pad129A close to the outer peripheral sides of semiconductor layer40in the plan view of semiconductor layer40, it is possible to reduce the possibility of a solder joint defect occurring due to warpage of semiconductor device1A, compared to a case in which first drain pad151A, first gate pad119A, second drain pad161A, and second gate pad129A are disposed at the center of semiconductor layer40.

As shown inFIG.14A, for example, the arrangement of first drain pad151A and first gate pad119A and the arrangement of second drain pad161A and second gate pad129A may be alternated. In this case, although (i) first gate pad119A and second gate pad129A and (ii) first drain pad151A and second drain pad161A are not line-symmetrical with reference to border line90C as the symmetrical axis, it is possible to dispose (i) first gate pad119A and second gate pad129A and (ii) first drain pad151A and second drain pad161A to be point-symmetrical with reference to the center of semiconductor layer40as the center of symmetry.

It should be noted that first drain pad151A and second drain pad161A is not limited to circular shapes as shown inFIG.14AtoFIG.14D. As shown inFIG.15A, first drain pad151A and second drain pad161A may each be in a substantially rectangular shape.

As shown inFIG.15AandFIG.15B, first drain pad151A and first gate pad119A may be arranged in a direction orthogonal to border line90C, second drain pad161A and second gate pad129A may be arranged in the direction orthogonal to border line90C, and a middle point of a line segment that connects the center of first drain pad151A and the center of second drain pad161A may coincide with the center of semiconductor layer40.

According to the above-described configuration, since it is possible to dispose first drain pad151A and second drain pad161A to be line-symmetrical with reference to border line90C as the symmetrical axis, the lack of balance in electrical characteristics of the bidirectional conduction and heat dissipation property between transistor10A and transistor20A is less likely to occur. In addition, since first drain pad151A and first gate pad119A are disposed to at least partially overlap each other in the first direction in which the principal current flows, it is possible to prevent each of first drain pad151A and first gate pad119A from becoming a factor in individually blocking the principal current, compared to a case in which first drain pad151A and first gate pad119A are arranged in a direction parallel to border line90C.

It should be noted that, as shown inFIG.16AtoFIG.16D, first drain pad151A and the plurality of first source pads111A may be disposed at regular intervals in a first band pattern, first drain pad151A and the plurality of first source pads111A may have the same width in a direction in which the first band pattern is formed, second drain pad161A and the plurality of second source pads121A may be disposed at regular intervals in a second band pattern, and second drain pad161A and the plurality of second source pads121A may have the same width in a direction in which the second band pattern is formed. Additionally, the first band pattern and the second band pattern may be the same band pattern.

In an arrangement as described above, it is possible to replace one of the plurality of first source pads111A and one of the plurality of second source pads121A with first drain pad151A and second drain pad161A, respectively. Accordingly, when usage that does not require the secondary pathway is switched to usage that requires the secondary pathway, it is possible to use semiconductor device1A without significantly changing an arrangement of wires in the mounting substrate.

Embodiment 3

Semiconductor device1B according to Embodiment 3 that is configured by changing part of semiconductor device1A according to Embodiment 2 is described below. Constituent elements of semiconductor device1B according to Embodiment 3 that are similar to those of semiconductor device1A are assigned the same reference signs, and the detailed description thereof is omitted, because they have already been described. The following mainly describes differences from semiconductor device1A.

FIG.17Ais a plan view illustrating an example of an arrangement of pads in semiconductor device1B according to Embodiment 3. The size and shape of semiconductor device1B are an example except that semiconductor device1B is in a rectangular shape. Additionally, the sizes, shapes, and arrangement of the pads are also an example. A cross section along line I-I inFIG.17Ais equivalent toFIG.1. In addition, a cross section along line II-II inFIG.17Ais equivalent toFIG.3A, and the constituent elements of semiconductor device1B according to Embodiment 3 are similar to those of semiconductor device1A according to Embodiment 2.

As shown inFIG.17AandFIG.1, semiconductor device1B includes: semiconductor layer40; metal layer41; transistor10A provided in first region A1A in semiconductor layer40; and transistor20A provided in second region A2A in semiconductor layer40.

The constituent elements of transistor10A and transistor20A of semiconductor device1B according to Embodiment 3 are equivalent to those of transistor10A and transistor20A of semiconductor device1A according to Embodiment 2.

As shown inFIG.17A, in a plan view of semiconductor layer40, first region A1A and second region A2A are one region and an other region that are adjacent to each other and divide an area of semiconductor layer40in half.

Moreover, inFIG.17A, a dashed line indicates virtual border line90C that separates between first region A1A and second region A2A of semiconductor layer40.

As shown inFIG.17A, in the plan view of semiconductor layer40, a middle point of a line segment that connects the center of first drain pad151A and the center of second drain pad161A is located on border line90C of semiconductor device1B.

It should be noted that, as shown inFIG.17Ashowing an example of semiconductor device1B, a middle point of a line segment that connects the center of first gate pad119A and the center of second gate pad129A may be located on border line90C of semiconductor device1B.

Moreover, in the plan view of semiconductor layer40, some of the plurality of first source pads111A are disposed between first drain pad151A and border line90C.

Similarly, in the plan view of semiconductor layer40, some of the plurality of second source pads121A are disposed between second drain pad161A and border line90C.

A principal current and a primary pathway of semiconductor device1B according to Embodiment 3 are similar to those of semiconductor device1according to Embodiment 1.

Additionally, a secondary current and a secondary pathway of semiconductor device1B according to Embodiment 3 are similar to those of semiconductor device1A according to Embodiment 2.

Above-described semiconductor device1B in the present disclosure has the following characteristics.

Semiconductor device1B according to one aspect of the present disclosure is facedown mountable, chip-size-package type semiconductor device1B, semiconductor device1B including: semiconductor substrate32; low-concentration impurity layer33that is provided on semiconductor substrate32; first vertical MOS transistor10A that is provided in first region A1A of semiconductor layer40that is a combination of semiconductor substrate32and low-concentration impurity layer33; second vertical MOS transistor20A that is provided in second region A2A adjacent to first region A1A in a plan view of semiconductor layer40; a plurality of first source pads111A that are provided in first region A1A in the plan view and connected to first source electrode11of first vertical MOS transistor10A; first gate pad119A that is provided in first region A1A in the plan view and connected to first gate electrode19of first vertical MOS transistor10A; first drain pad151A that is provided in first region A1A in the plan view and connected to first drain electrode51A of first vertical MOS transistor10A; a plurality of second source pads121A that are provided in second region A2A in the plan view and connected to second source electrode21of second vertical MOS transistor20A; second gate pad129A that is provided in second region A2A in the plan view and connected to second gate electrode29of second vertical MOS transistor20A; second drain pad161A that is provided in second region A2A in the plan view and connected to second drain electrode61A of second vertical MOS transistor20A; and metal layer41that is provided in contact with a back surface of semiconductor substrate32. Semiconductor substrate32is a common drain region for first vertical MOS transistor10A and second vertical MOS transistor20A. In the plan view, semiconductor layer40is in a rectangular shape. In the plan view, first region A1A and second region A2A are one region and an other region that divide an area of semiconductor layer40in half. In the plan view, a middle point of a line segment that connects a center of first drain pad151A and a center of second drain pad161A is located on border line90C between first region A1A and second region A2A. In the plan view, at least part of the plurality of first source pads111A are disposed between first drain pad151A and border line90C. In the plan view, at least part of the plurality of second source pads121A are disposed between second drain pad161A and border line90C.

FIG.17BtoFIG.17D,FIG.18A, andFIG.18Bare each a plan view illustrating an example of an arrangement of pads that satisfies conditions for semiconductor device1B according to Embodiment 3.

According to the above-described configuration, in the plan view of semiconductor layer40, at least some of the plurality of first source pads111A and at least some of the plurality of second source pads121A are disposed not to cause first drain pad151A and second drain pad161A to be located between (i) the plurality of first source pads111A and the plurality of second source pads121A and (ii) border line90C. Accordingly, since first drain pad151A and second drain pad161A are disposed, in the vicinity of border line90C along which a current density of the principal current increases most, not to block the conduction of the principal current, providing the secondary pathway makes it possible to inhibit an increase in conduction resistance in the primary pathway as much as possible.

In particular, inFIG.17AandFIG.17C, since the plurality of first source pads111A and the plurality of second source pads121A are disposed, over the entire length of border line90C, to face each other with no other pads interposed therebetween, this is effective in reducing the conduction resistance of the primary pathway.

As shown inFIG.18AandFIG.18B, in the plan view of semiconductor layer40, first drain pad151A may be disposed closest to a corner portion defined by two intersecting sides among four sides that constitute outer peripheral sides of semiconductor layer40, and second drain pad161A may be disposed closest to an other corner portion that is diagonally opposite to the corner portion of semiconductor layer40to which first drain pad151A is disposed closest.

According to the above-described configuration, since it is possible to dispose first drain pad151A and second drain pad161A closest to an outer peripheral portion of semiconductor layer40, it is possible to reduce the possibility of a solder joint defect occurring due to warpage of semiconductor device1B, compared to a case in which first drain pad151A and second drain pad161A are disposed at a central portion of semiconductor layer40.

Although only some exemplary embodiments of the present disclosure have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure.

INDUSTRIAL APPLICABILITY

The semiconductor device including the vertical MOS transistor according to the present disclosure is widely applicable as a device that controls a conducting state of a current pathway.