Patent ID: 12256540

The present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. As such, other configurations and arrangements can be used without departing from the scope of the present disclosure. Also, the present disclosure can also be employed in a variety of other applications. Functional and structural features as described in the present disclosures can be combined, adjusted, and modified with one another and in ways not specifically depicted in the drawings, such that these combinations, adjustments, and modifications are within the scope of the present disclosure.

In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

It should be readily understood that the meaning of “on,” “above,” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something).

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the term “substrate” refers to a material onto which subsequent material layers are added. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a wide array of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.

As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layers thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductors and contact layers (in which interconnect lines and/or vertical interconnect access (via) contacts are formed) and one or more dielectric layers.

In some 3D NAND memory devices, semiconductor plugs are selectively grown to surround the sidewalls of channel structures, e.g., known as sidewall selective epitaxial growth (SEG). Compared with another type of semiconductor plugs that is formed at the source end of the channel structures, e.g., bottom SEG, the formation of sidewall SEG avoids the etching of the memory film and the semiconductor channel at the bottom surface of channel holes (a.k.a. SONO punch), thereby increasing the process window, in particular when fabricating 3D NAND memory devices with advanced technologies, such as having 90 or more levels with a multi-deck architecture.

However, because intrinsic (pure, undoped) semiconductor materials, such as intrinsic polysilicon, are used to form the semiconductor channel, a relatively high potential barrier exists between the semiconductor channel and the sidewall SEG or the conductive layer in contact with the semiconductor channel, thereby introducing high contact resistance therebetween. The electric performance of the 3D memory device can be affected by the high contact resistance.

To address the aforementioned issues, the present disclosure introduces a solution in which the contact resistance between the semiconductor channel and the sidewall SEG or the conductive layer can be reduced. In some implementations, the semiconductor channel is partially doped such that part of the semiconductor channel that forms the source contact is highly doped to lower the potential barrier while leaving another part of the semiconductor channel that forms the memory cells remaining undoped or lowly doped. In some implementations, one end of each channel structure is opened from the backside to expose the doped part of the respective semiconductor channel, and the 3D memory device further includes a doped semiconductor layer electrically connecting the exposed doped parts of the semiconductor channels to further reduce the contact resistance and sheet resistance. As a result, the electric performance of the 3D memory devices can be improved.

Consistent with the scope of the present disclosure, the doped part of the semiconductor channel and the doped semiconductor layer can be locally activated, e.g., through local annealing, to activate the dopants therein without damaging other parts on the device chip that are sensitive to heat, such as the bonding interface and copper interconnects. For example, the heat for activating the dopants may be confined in an area that excludes thermal-sensitive components on the device chip. In some implementations, the local activation process also serves as an in-situ doping process to dope part of the intrinsic semiconductor channel that is in contact with the doped semiconductor layer.

FIG.1illustrates a side view of a cross-section of an exemplary 3D memory device100, according to some aspects of the present disclosure. In some implementations, 3D memory device100is a bonded chip including a first semiconductor structure102and a second semiconductor structure104stacked over first semiconductor structure102. First and second semiconductor structures102and104are jointed at a bonding interface106therebetween, according to some implementations. As shown inFIG.1, first semiconductor structure102can include a substrate101, which can include silicon (e.g., single crystalline silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable materials.

First semiconductor structure102of 3D memory device100can include peripheral circuits108on substrate101. It is noted that x and y axes are included inFIG.1to further illustrate the spatial relationship of the components in 3D memory device100having substrate101. Substrate101includes two lateral surfaces (e.g., a top surface and a bottom surface) extending laterally in the x-direction (i.e., the lateral direction). As used herein, whether one component (e.g., a layer or a device) is on, above, or below another component (e.g., a layer or a device) of a semiconductor device (e.g., 3D memory device100) is determined relative to the substrate of the semiconductor device (e.g., substrate101) in the y-direction (i.e., the vertical direction) when the substrate is positioned in the lowest plane of the semiconductor device in the y-direction. The same notion for describing spatial relationships is applied throughout the present disclosure.

In some implementations, peripheral circuit108is configured to control and sense 3D memory device100. Peripheral circuit108can be any suitable digital, analog, and/or mixed-signal control and sensing circuits used for facilitating the operation of 3D memory device100including, but not limited to, a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), a charge pump, a current or voltage reference, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). Peripheral circuit108can include transistors formed on substrate101, in which the entirety or part of the transistors are formed in substrate101(e.g., below the top surface of substrate101) and/or directly on substrate101. Isolation regions (e.g., shallow trench isolations (STIs)) and doped regions (e.g., source regions and drain regions of the transistors) can be formed in substrate101as well. The transistors are high-speed with advanced logic processes (e.g., technology nodes of 90 nm, 65 nm, 45 nm, 32 nm, 28 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 2 nm, etc.), according to some implementations. It is understood that in some implementations, peripheral circuit108may further include any other circuits compatible with the advanced logic processes including logic circuits, such as processors and programmable logic devices (PLDs), or memory circuits, such as static random-access memory (SRAM) and dynamic RAM (DRAM).

In some implementations, first semiconductor structure102of 3D memory device100further includes an interconnect layer (not shown) above peripheral circuits108to transfer electrical signals to and from peripheral circuits108. The interconnect layer can include a plurality of interconnects (also referred to herein as contacts), including lateral interconnect lines and vertical interconnect access (VIA) contacts. As used herein, the term interconnects can broadly include any suitable types of interconnects, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnect layer can further include one or more interlayer dielectric (ILD) layers (a.k.a. intermetal dielectric (IMD) layers) in which the interconnect lines and VIA contacts can form. That is, the interconnect layer can include interconnect lines and VIA contacts in multiple ILD layers. The interconnect lines and VIA contacts in the interconnect layer can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in the interconnect layer can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof.

As shown inFIG.1, first semiconductor structure102of 3D memory device100can further include a bonding layer110at bonding interface106and above the interconnect layer and peripheral circuits108. Bonding layer110can include a plurality of bonding contacts111and dielectrics electrically isolating bonding contacts111. Bonding contacts111can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of bonding layer110can be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts111and surrounding dielectrics in bonding layer110can be used for hybrid bonding.

Similarly, as shown inFIG.1, second semiconductor structure104of 3D memory device100can also include a bonding layer112at bonding interface106and above bonding layer110of first semiconductor structure102. Bonding layer112can include a plurality of bonding contacts113and dielectrics electrically isolating bonding contacts113. Bonding contacts113can include conductive materials including, but not limited to, W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of bonding layer112can be formed with dielectrics including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Bonding contacts113and surrounding dielectrics in bonding layer112can be used for hybrid bonding. Bonding contacts113are in contact with bonding contacts111at bonding interface106, according to some implementations.

As described below in detail, second semiconductor structure104can be bonded on top of first semiconductor structure102in a face-to-face manner at bonding interface106. In some implementations, bonding interface106is disposed between bonding layers110and112as a result of hybrid bonding (also known as “metal/dielectric hybrid bonding”), which is a direct bonding technology (e.g., forming bonding between surfaces without using intermediate layers, such as solder or adhesives) and can obtain metal-metal bonding and dielectric-dielectric bonding simultaneously. In some implementations, bonding interface106is the place at which bonding layers112and110are met and bonded. In practice, bonding interface106can be a layer with a certain thickness that includes the top surface of bonding layer110of first semiconductor structure102and the bottom surface of bonding layer112of second semiconductor structure104.

In some implementations, second semiconductor structure104of 3D memory device100further includes an interconnect layer (not shown) above bonding layer112to transfer electrical signals. The interconnect layer can include a plurality of interconnects, such as MEOL interconnects and BEOL interconnects. The interconnect layer can further include one or more ILD layers in which the interconnect lines and VIA contacts can form. The interconnect lines and VIA contacts in the interconnect layer can include conductive materials including, but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layers in the interconnect layer can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

In some implementations, 3D memory device100is a NAND Flash memory device in which memory cells are provided in the form of an array of NAND memory strings. Each NAND memory string can include a respective channel structure124. As shown inFIG.1, each channel structure124can extend vertically through a plurality of pairs each including a stack conductive layer116and a stack dielectric layer118. The interleaved stack conductive layers116and stack dielectric layers118are part of a memory stack114. The number of the pairs of stack conductive layers116and stack dielectric layers118in memory stack114determines the number of memory cells in 3D memory device100. It is understood that in some implementations, memory stack114may have a multi-deck architecture (not shown), which includes a plurality of memory decks stacked over one another. The numbers of the pairs of stack conductive layers116and stack dielectric layers118in each memory deck can be the same or different.

Memory stack114can include a plurality of interleaved stack conductive layers116and stack dielectric layers118. Stack conductive layers116and stack dielectric layers118in memory stack114can alternate in the vertical direction. In other words, except the ones at the top or bottom of memory stack114, each stack conductive layer116can be adjoined by two stack dielectric layers118on both sides, and each stack dielectric layer118can be adjoined by two stack conductive layers116on both sides. Stack conductive layers116can include conductive materials including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicides, or any combination thereof. Each stack conductive layer116can include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of stack conductive layer116can extend laterally as a word line, ending at one or more staircase structures of memory stack114. Stack dielectric layers118can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

As shown inFIG.1, second semiconductor structure104of 3D memory device100can also include a filling layer120above memory stack114. Filling layer120can include polysilicon, a high dielectric constant (high-k) dielectric, or a metal. For example, a high-k dielectric may include any dielectric materials having a dielectric constant higher than that of silicon oxide (e.g., >3.7Different from some known solutions in which filling layer120acts as the sidewall SEGs surrounding channel structures124and/or a conductive layer electrically connecting channel structures124, such as a doped polysilicon layer, filling layer120in second semiconductor structure104of 3D memory device100may not work as the sidewall SEGs and/or the conductive layer and thus, may include materials other than doped polysilicon, such as dielectrics (e.g., high-k dielectrics), metals (e.g., W, Co, Cu, or Al), metal silicides, or undoped polysilicon. It is understood that in some examples, filling layer120may include doped polysilicon as well.

In some implementations, each channel structure124includes a channel hole filled with a semiconductor layer (e.g., as a semiconductor channel128) and a composite dielectric layer (e.g., as a memory film126). In some implementations, semiconductor channel128includes silicon, such as amorphous silicon, polysilicon, or single crystalline silicon. In some implementations, memory film126is a composite layer including a tunneling layer, a storage layer (also known as a “charge trap layer”), and a blocking layer. The remaining space of the channel hole can be partially or fully filled with a capping layer including dielectric materials, such as silicon oxide, and/or an air gap. Channel structure124can have a cylinder shape (e.g., a pillar shape). The capping layer, semiconductor channel128, the tunneling layer, storage layer, and blocking layer of memory film126are arranged radially from the center toward the outer surface of the pillar in this order, according to some implementations. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, high-k dielectrics, or any combination thereof. In one example, memory film126can include a composite layer of silicon oxide/silicon oxynitride/silicon oxide (ONO).

In some implementations, channel structure124further includes a channel plug129in the bottom portion (e.g., at the lower end) of channel structure124. As used herein, the upper end of a component (e.g., channel structure124) is the end farther away from substrate101in the y-direction, and the lower end of the component (e.g., channel structure124) is the end closer to substrate101in the y-direction when substrate101is positioned in the lowest plane of 3D memory device100. Channel plug129can include semiconductor materials (e.g., polysilicon). In some implementations, channel plug129functions as the drain of channel structure124.

As shown inFIG.1, each channel structure124can extend vertically through interleaved stack conductive layers116and stack dielectric layers118of memory stack114into filling layer120. The upper end of memory film126is not aligned with the upper end of semiconductor channel128in the vertical direction because part of memory film126may be removed during the fabrication process as described below in detail, according to some implementations. In some implementations, the upper end of memory film126is below the upper end of semiconductor channel128in channel structure124, as shown inFIG.1. In some implementations, the upper end of memory film126is flush with the interface between filling layer120and memory stack114, i.e., the bottom surface of filling layer120and the top surface of memory stack114. Although not shown, it is understood that in some examples, the upper end of memory film126may be between the top surface and bottom surface of filling layer120. That is, the upper end of memory film126can be flush with or exceeds the top surface of memory stack114. In some implementations, the upper end of memory film126is not below the top surface of memory stack114.

As shown inFIG.1, the upper end of semiconductor channel128is above the upper end of memory film126, according to some implementations. In other words, semiconductor channel128can extend further into filling layer120than memory film126. For example, as shown inFIG.1, memory film126may end at the top surface of memory stack114, while semiconductor channel128may extend above the top surface of memory stack114to face filling layer120. Also referred to the enlarged side view of channel structure124inFIG.2, semiconductor channel128can include a doped portion128aand an undoped portion128b. In some implementations, at least part of doped portion128aof semiconductor channel128extends beyond memory stack114in a first direction (e.g., the positive y-direction inFIG.2). That is, the upper end of doped portion128acan be above the interface between filling layer120and memory stack114, i.e., the bottom surface of filling layer120and the top surface of memory stack114. In some implementations, doped portion128aof semiconductor channel128also extends beyond one of stack conductive layers116in a second direction opposite to the first direction (e.g., the negative y-direction inFIG.2). It is understood that one or more of stack conductive layers116that are close to filling layer120may be source select gate line201(SSG, sometimes referred to as bottom select gate (BSG) line), and the rest of stack conductive layer116may include word lines203. Doped portion128aof semiconductor channel128also extends beyond a source select gate line201that is closest to filling layer120, according to some implementations. It is understood that if second semiconductor structure104of 3D memory device100includes more than one source select gate line201, doped portion128amay extend beyond all source select gate lines201. On the other hand, doped portion128amay not extend further to face word lines203. That is, the lower end of doped portion128ais between source select gate lines201and word lines203in the vertical direction, according to some implementations. For example, as shown inFIG.2, part of doped portion128aof semiconductor channel128that extends beyond memory stack114may face filling layer120, while the remainder of doped portion128amay face source select gate line(s)201.

In some implementations, doped portion128aof semiconductor channel128includes N-type doped polysilicon. The dopant can be any suitable N-type dopants, such as phosphorus (P), arsenic (Ar), or antimony (Sb), which contribute free electrons and increase the conductivity of the intrinsic semiconductor. In some implementations, the doping concentration of doped portion128ais between about 1019cm−3and about 1021cm−3, such as between 1019cm−3and 1021cm−3(e.g. 1019cm−3, 2×1019cm−3, 3×1019cm−3, 4×1019cm−3, 5×1019, cm−3, 6×1019cm−3, 7×1019cm−3, 8×1019cm−3, 9×1019cm−3, 1020cm−3, 2×1020cm−3, 3×10°cm−3, 4×1020cm−3, 5 ×1020cm−3, 6×1020cm−3, 7×1020cm−3, 8×1020cm−3, 9×1020cm−3, 1021cm−3, any range bounded by the lower end by any of these values, or in any range defined by any two of these values). The doping concentrations of doped portion128adisclosed herein can significantly reduce the contact resistance between semiconductor channel128and doped semiconductor channel122compared with intrinsic semiconductors. It is understood that in some examples, the diffusion of the dopant may be confined in doped portion128aof semiconductor channel128, such that the rest of semiconductor channel128, i.e., the part that faces word lines203, is undoped portion128bthat still includes intrinsic semiconductor, such as intrinsic polysilicon (i.e., the doping concentration is nominally zero). The doping concentration profile described above can reduce the potential barrier, the contact resistance, and the sheet resistance at doped portion128aof semiconductor channel128, which makes electrical connections for the source of the corresponding NAND memory string, without altering the intrinsic nature of undoped portion128bof semiconductor channel128that forms the memory cells of the NAND memory string.

In some implementations, second semiconductor structure104of 3D memory device100includes a doped semiconductor layer122that can electrically connect multiple channel structures124. For example, doped semiconductor layer122may provide electrical connections between the sources of an array of NAND memory strings in the same block, i.e., the array common source (ACS), with or without filling layer120(depending on whether filling layer120is conductive or not). In other words, filling layer120may not have to include conductive materials, such as metals or doped polysilicon, as doped semiconductor layer122alone can electrically connect the sources of multiple NAND memory strings. As a result, the material and dimension constraints on filling layer120can be relaxed.

As shown inFIGS.1and2, in some implementations, doped semiconductor layer122includes two portions: a first portion121in contact with the sidewall of at least part of doped portion128aof semiconductor channel128that extends beyond memory stack114, and a second portion123above and in contact with filling layer120. That is, part of doped semiconductor layer122(i.e., second portion123) is on filling layer120, and the remainder of doped semiconductor layer122(i.e., first portion121) surrounding the upper end of each channel structure124is in contact with doped portion128aof semiconductor channel128, according to some implementations. Filling layer120can be formed between memory stack114and second portion123of doped semiconductor layer122in the vertical direction. It is understood that in some implementations, first portion121of doped semiconductor layer122may be above and in contact with the top surface of doped portion128aof semiconductor channel128as well. That is, doped semiconductor layer122may be in contact with both the top surface and the sidewall of doped portion128aof semiconductor channel128that extends beyond memory stack114to increase the contact area.

As shown inFIG.1, channel structure124can extend through memory stack114and filling layer120to doped semiconductor layer122. In some implementations, at least part of semiconductor channel128that is between doped semiconductor layer122and source select gate line(s)201(e.g., one of stack conductive layers116that is closest to doped semiconductor layer122) is doped. As a result, part of doped semiconductor layer122(e.g., first portion121) can be in contact with the doped part of semiconductor channel128(e.g., doped portion128a), and filling layer120can be formed between memory stack114and another part of the doped semiconductor layer122(e.g., second portion123) in the vertical direction. As described below in detail, the formation of memory stack114and the formation of doped portion128aof semiconductor channel128and doped semiconductor layer122occur at opposite sides of filling layer120, thereby avoiding any deposition or etching process through openings extending through memory stack114, thereby reducing the fabrication complexity and cost and increasing the yield and vertical scalability.

Similar to doped portion128aof semiconductor channel128, in some implementations, doped semiconductor layer122also includes N-type doped polysilicon. The dopant can be any suitable N-type dopants, such as P, Ar, or Sb, which contribute free electrons and increase the conductivity of the intrinsic semiconductor. Similar to doped portion128aof semiconductor channel128, in some implementations, the doping concentration of doped semiconductor layer122is between about 1019cm−3and about 1021cm−3, such as between1019cm−3and 1021cm−3(e.g., 1019cm−3, 2×1019cm−3, 3×1019cm−3, 4×1019cm−3, 5×1019cm−3, 6×1019cm−3, 7×1019cm−3, 8×1019cm−3, 9×1019cm−3, 1020cm−3, 2×1020cm−3, 3 ×1020cm−3, 4×1020cm−3, 5×1020cm3, 6×1020cm−3, 7×1020cm−3, 8 ×1020cm−3, 9×1020cm−3, 1021cm−3, any range bounded by the lower end by any of these values, or in any range defined by any two of these values). The doping concentrations of doped semiconductor layer122disclosed herein can significantly reduce the contact resistance between semiconductor channel128and doped semiconductor channel122as well asl the sheet resistance of doped semiconductor layer122, compared with intrinsic semiconductors. As described below in detail, in some implementations, doped portion128aof semiconductor channel128and doped semiconductor layer122have the same material (e.g., N-type doped polysilicon) with the same dopant as well as a continuous doping profile due to the same local activation process performed thereon. Thus, it is understood that the interface and boundary between doped portion128aof semiconductor channel128and first portion121of doped semiconductor layer122may become indistinguishable and thus cannot be discerned in 3D memory device100.

By doping and contacting semiconductor channel128and doped semiconductor layer122, the contact resistance between the NAND memory strings (i.e., at the ACS of NAND memory strings in the same block) can be reduced, thereby improving the electrical performance of 3D memory device100. N-type doped semiconductor layer122, which surrounds doped portion128aof semiconductor channel128, can enable gate-induced drain leakage (GIDL)-assisted body biasing for erase operations for 3D memory device100. The GIDL around source select gate line(s)201can generate hole current (i.e., source leakage current) into semiconductor channel128from the source of the corresponding NAND memory string to raise the body potential for erase operations. That is, 3D memory device100is configured to generate GIDL-assisted body biasing when performing an erase operation, according to some implementations. In some implementations, by also doping part of semiconductor channel128facing source select gate line(s)201, the GIDL effect can be further enhanced.

As shown inFIG.1, second semiconductor structure104of 3D memory device100can further include insulating structures130each extending vertically through interleaved stack conductive layers116and stack dielectric layers118of memory stack114. Different from channel structure124that extends further into filling layer120, insulating structures130stops at the bottom surface of filling layer120, i.e., does not extend vertically into filling layer120, according to some implementations. That is, the top surface of insulating structure130can be flush with the bottom surface of filling layer120. Each insulating structure130can also extend laterally to separate channel structures124into a plurality of blocks. That is, memory stack114can be divided into a plurality of memory blocks by insulating structures130, such that the array of channel structures124can be separated into each memory block. Different from the slit structures in existing 3D NAND memory devices, which include front side ACS contacts, insulating structure130does not include any contact therein (i.e., not functioning as the source contact) and thus, does not introduce parasitic capacitance and leakage current with stack conductive layers116, according to some implementations. In some implementations, each insulating structure130includes an opening (e.g., a slit) filled with one or more dielectric materials, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, each insulating structure130may be filled with silicon oxide. It is understood that in some examples, insulating structure130may be partially filled with non-dielectric materials, such as polysilicon, to adjust the mechanical properties, e.g., the hardness and/or stress, of insulating structure130.

Moreover, as described below in detail, because the opening for forming insulating structure130is not used for forming doped semiconductor layer122and doped portion128aof semiconductor channel128, the increased aspect ratio of the opening (e.g., greater than 50) as the number of interleaved stack conductive layers116and stack dielectric layers118increases would not affect the formation of doped semiconductor layer122and doped portion128aof semiconductor channel128.

Instead of the front side source contacts, 3D memory device100can include one or more backside source contacts132above and in contact with doped semiconductor layer122, as shown inFIG.1. Source contact132and memory stack114(and insulating structure130therethrough) can be disposed at opposite sides of filling layer120and thus, viewed as a “backside” source contact. In some implementations, source contact132is electrically connected to semiconductor channel128of channel structure124through doped semiconductor layer122. Source contacts132can include any suitable types of contacts. In some implementations, source contacts132include a VIA contact. In some implementations, source contacts132include a wall-shaped contact extending laterally. Source contact132can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., titanium nitride (TiN)).

As shown inFIG.1, 3D memory device100can further include a BEOL interconnect layer133above and electrically connected to source contact132for pad-out, e.g., transferring electrical signals between 3D memory device100and external circuits. In some implementations, interconnect layer133includes one or more ILD layers134on doped semiconductor layer122and a redistribution layer136on ILD layers134. The upper end of source contact132is flush with the top surface of ILD layers134, and the bottom surface of redistribution layer136, and source contact132extends vertically through ILD layers134to be in contact with doped semiconductor layer122, according to some implementations. ILD layers134in interconnect layer133can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Redistribution layer136in interconnect layer133can include conductive materials including, but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In some implementations, interconnect layer133further includes a passivation layer138as the outmost layer for passivation and protection of 3D memory device100. Part of redistribution layer136can be exposed from passivation layer138as contact pads140. That is, interconnect layer133of 3D memory device100can also include contact pads140for wire bonding and/or bonding with an interposer. As described below with respect to the fabrication process, in some implementations, source contacts132and redistribution layer136may be formed by the same process and have the same material, e.g., Al. Thus, source contacts132may be viewed as part of BEOL interconnect layer133as well in some examples.

In some implementations, second semiconductor structure104of 3D memory device100further includes contacts142and144through doped semiconductor layer122and filling layer120. As doped semiconductor layer122can include polysilicon, contacts142and144are through silicon contacts (TSCs), according to some implementations. In some implementations, contact142extends through doped semiconductor layer122, filling layer120, and ILD layers134to be in contact with redistribution layer136, such that first portion121of doped semiconductor layer122is electrically connected to contact142through source contact132and redistribution layer136of interconnect layer133. In some implementations, contact144extends through doped semiconductor layer122, filling layer120, and ILD layers134to be in contact with contact pad140. Contacts142and144each can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN). In some implementations, at least contact144further includes a spacer (e.g., a dielectric layer) to electrically separate contact144from doped semiconductor layer122and filling layer120.

In some implementations, 3D memory device100further includes peripheral contacts146and148each extending vertically outside of memory stack114. Each peripheral contact146or148can have a depth greater than the depth of memory stack114to extend vertically from bonding layer112to filling layer120in a peripheral region that is outside of memory stack114. In some implementations, peripheral contact146is below and in contact with contact142, such that first portion121of doped semiconductor layer122is electrically connected to peripheral circuit108in first semiconductor structure102through at least source contact132, redistribution layer136, contact142, and peripheral contact146. In some implementations, peripheral contact148is below and in contact with contact144, such that peripheral circuit108in first semiconductor structure102is electrically connected to contact pad140for pad-out through at least contact144and peripheral contact148. Peripheral contacts146and148each can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

As shown inFIG.1, 3D memory device100also includes a variety of local contacts (also known as “C1”) as part of the interconnect structure, which are in contact with a structure in memory stack114directly. In some implementations, the local contacts include channel local contacts150each below and in contact with the lower end of respective channel structure124. Each channel local contact150can be electrically connected to a bit line contact (not shown) for bit line fan-out. In some implementations, the local contacts further include word line local contacts152each below and in contact with respective stack conductive layer116(including a word line) at the staircase structure of memory stack114for word line fan-out. Local contacts, such as channel local contacts150and word line local contacts152, can be electrically connected to peripheral circuits108of first semiconductor structure102through at least bonding layers112and110. Local contacts, such as channel local contacts150and word line local contacts152, each can include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., TiN).

Although an exemplary 3D memory device100is shown inFIG.1, it is understood that by varying the relative positions of first and second semiconductor structures102and104, the usage of backside source contacts132or known front side source contacts (not shown), and/or the pad-out locations (e.g., through first semiconductor structure102and/or second semiconductor structure104), any other suitable architectures of 3D memory devices may be applicable in the present disclosure without further detailed elaboration.

FIG.5illustrates a block diagram of an exemplary system500having a 3D memory device, according to some aspects of the present disclosure. System500can be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic devices having storage therein. As shown inFIG.5, system500can include a host508and a memory system502having one or more 3D memory devices504and a memory controller506. Host508can be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP).

3D memory device504can be any 3D memory devices disclosed herein, such as 3D memory device100shown inFIGS.1and2. In some implementations, each 3D memory device504includes a NAND Flash memory. Consistent with the scope of the present disclosure, the semiconductor channel of 3D memory device504can be partially doped such that part of the semiconductor channel that forms the source contact is highly doped to lower the potential barrier while leaving another part of the semiconductor channel that forms the memory cells remaining undoped or lowly doped. One end of each channel structure of 3D memory device504can be opened from the backside to expose the doped part of the respective semiconductor channel. 3D memory device504can further include a doped semiconductor layer electrically connecting the exposed doped parts of the semiconductor channels to further reduce the contact resistance and sheet resistance. As a result, the electric performance of 3D memory device504can be improved, which in turn improves the performance of memory system502and system500, e.g., achieving higher operation speed.

Memory controller506is coupled to 3D memory device504and host508and is configured to control 3D memory device504, according to some implementations. Memory controller506can manage the data stored in 3D memory device504and communicate with host508. In some implementations, memory controller506is designed for operating in a low duty-cycle environment like secure digital (SD) cards, compact Flash (CF) cards, universal serial bus (USB) Flash drives, or other media for use in electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some implementations, memory controller506is designed for operating in a high duty-cycle environment SSDs or embedded multi-media-cards (eMMCs) used as data storage for mobile devices, such as smartphones, tablets, laptop computers, etc., and enterprise storage arrays. Memory controller506can be configured to control operations of 3D memory device504, such as read, erase, and program operations. Memory controller506can also be configured to manage various functions with respect to the data stored or to be stored in 3D memory device504including, but not limited to bad-block management, garbage collection, logical-to-physical address conversion, wear leveling, etc. In some implementations, memory controller506is further configured to process error correction codes (ECCs) with respect to the data read from or written to 3D memory device504. Any other suitable functions may be performed by memory controller506as well, for example, formatting 3D memory device504. Memory controller506can communicate with an external device (e.g., host508) according to a particular communication protocol. For example, memory controller506may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

Memory controller506and one or more 3D memory devices504can be integrated into various types of storage devices, for example, be included in the same package, such as a universal Flash storage (UFS) package or an eMMC package. That is, memory system502can be implemented as and packaged into different types of end electronic products. In one example as shown inFIG.6A, memory controller506and a single 3D memory device504may be integrated into a memory card602. Memory card602can include a PC card (PCMCIA, personal computer memory card international association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, mini SD, microSD, SDHC), a UFS, etc. Memory card602can further include a memory card connector604electrically coupling memory card602with a host (e.g., host508inFIG.5). In another example as shown inFIG.6B, memory controller506and multiple 3D memory devices504may be integrated into an SSD606. SSD606can further include an SSD connector608electrically coupling SSD606with a host (e.g., host508inFIG.5). In some implementations, the storage capacity and/or the operation speed of SSD606is greater than those of memory card602.

FIGS.3A-3Oillustrate a fabrication process for forming an exemplary 3D memory device, according to some implementations of the present disclosure.FIG.4illustrates a flowchart of a method400for forming an exemplary 3D memory device, according to some implementations of the present disclosure. Examples of the 3D memory device depicted inFIGS.3A-30and4include 3D memory device100depicted inFIG.1.FIGS.3A-3O and4will be described together. It is understood that the operations shown in method400are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown inFIG.4.

Referring toFIG.4, method400starts at operation402, in which a peripheral circuit is formed on a first substrate. The first substrate can be a silicon substrate. As illustrated inFIG.3G, a plurality of transistors are formed on a silicon substrate350using a plurality of processes including, but not limited to, photolithography, etching, thin film deposition, thermal growth, implantation, chemical mechanical polishing (C1VIP), and any other suitable processes. In some implementations, doped regions (not shown) are formed in silicon substrate350by ion implantation and/or thermal diffusion, which function, for example, as source regions and/or drain regions of the transistors. In some implementations, isolation regions (e.g., STIs) are also formed in silicon substrate350by wet etching and/or dry etching and thin film deposition. The transistors can form peripheral circuits352on silicon substrate350.

As illustrated inFIG.3G, a bonding layer348is formed above peripheral circuits352. Bonding layer348includes bonding contacts electrically connected to peripheral circuits352. To form bonding layer348, an ILD layer is deposited using one or more thin film deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof; the bonding contacts through the ILD layer are formed using wet etching and/or dry etching, e.g., reactive ion etching (RIE), followed by one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

Method400proceeds to operation404, as illustrated inFIG.4, in which a filling layer is formed above a second substrate, and a stack structure is formed above the filling layer. The filling layer and stack structure can be formed on the front side of the second substrate on which semiconductor devices can be formed. The second substrate can be a silicon substrate. It is understood that since the second substrate will be removed from the final product, the second substrate may be part of a dummy wafer, for example, a carrier substrate, made of any suitable materials, such as glass, sapphire, plastic, silicon, to name a few, to reduce the cost of the second substrate. In some implementations, the substrate is a carrier substrate. In some implementations, the filling layer includes polysilicon, a high-k dielectric, or a metal, and the stack structure includes a dielectric stack having interleaved stack dielectric layers and stack sacrificial layers. It is understood that in some examples, the stack structure may include a memory stack having interleaved stack dielectric layers (e.g., silicon oxide layers) and stack conductive layers (e.g., polysilicon layers).

To better control the gauging and surface flatness of various structures to be formed on the second substrate, a variety of stop layers can be formed between the second substrate and the filling layer. In some implementations, a first stop layer, a second stop layer, and a third stop layer are sequentially formed between the second substrate and the filling layer. The first stop layer can include silicon oxide or silicon nitride, the second stop layer can include silicon oxide or polysilicon, and the third stop layer can include silicon nitride or polysilicon. In some implementations, a single stop layer, such as a silicon oxide layer or a high-k dielectric layer, is formed between the second substrate and the filling layer.

As illustrated inFIG.3A, a first stop layer303is formed above a carrier substrate302, a second stop layer304is formed on first stop layer303, a third stop layer305is formed on second stop layer304, and a filling layer306is formed on third stop layer305. Filling layer306can include polysilicon, a high-k dielectric, or a metal. As described below in detail, third stop layer305can act as an etch stop layer when etching the memory films of channel structures from the backside and thus, may include any suitable materials other than silicon oxide used in memory films, such as polysilicon or silicon nitride. Second stop layer304can act as an etch stop layer when etching the channel holes from the front side and thus, may include any suitable materials that have a high etching selectivity (e.g., greater than about 5) with respect to the material directly on second stop layer304), such as silicon oxide or polysilicon. First stop layer303can act as a CMP/etch stop layer when removing carrier substrate302from the backside and thus, may include any suitable materials other than the material of carrier substrate302, such as silicon nitride or silicon oxide. It is understood that in some examples, pad oxide layers (e.g., silicon oxide layers) may be formed between carrier substrate302and first stop layer303or between second stop layer304and third stop layer305to relax the stress between different layers and avoid peeling.

As shown inFIG.3A, a stack of silicon oxide layer (pad oxide layer), silicon nitride layer (first stop layer303), silicon oxide layer (second stop layer304), and silicon nitride layer (third stop layer305) can be sequentially formed on carrier substrate302using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. In some implementations, filling layer306is formed by depositing polysilicon, or any other suitable materials, such as a high-k dielectric or a metal, on third stop layer305using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. For ease of description, the combination of the stop layers shown inFIG.3Ais used through the present disclosure to describe the fabrication process. It is understood that, however, any other suitable combinations of stop layer(s) may be used in other examples as well. In one example not shown, a stack of silicon oxide layer (as first stop layer303), polysilicon layer (as second stop layer304), silicon oxide layer (pad oxide layer), and polysilicon layer (as third stop layer305) may be sequentially formed on carrier substrate302using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. In another example not shown, a single oxide layer or a high-k dielectric layer (as first, second, and third stop layers303,304, and305) may be formed on carrier substrate302using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

As illustrated inFIG.3B, a dielectric stack308including a plurality pairs of a first dielectric layer (referred to herein as “stack sacrificial layer”312) and a second dielectric layer (referred to herein as “stack dielectric layers”310, together referred to herein as “dielectric layer pairs”) is formed on filling layer306. Dielectric stack308includes interleaved stack sacrificial layers312and stack dielectric layers310, according to some implementations. Stack dielectric layers310and stack sacrificial layers312can be alternatingly deposited on filling layer306above carrier substrate302to form dielectric stack308. In some implementations, each stack dielectric layer310includes a layer of silicon oxide, and each stack sacrificial layer312includes a layer of silicon nitride. Dielectric stack308can be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. As illustrated inFIG.3B, a staircase structure can be formed on the edge of dielectric stack308. The staircase structure can be formed by performing a plurality of so-called “trim-etch” cycles to the dielectric layer pairs of dielectric stack308toward carrier substrate302. Due to the repeated trim-etch cycles applied to the dielectric layer pairs of dielectric stack308, dielectric stack308can have one or more tilted edges and a top dielectric layer pair shorter than the bottom one, as shown inFIG.3B.

Method400proceeds to operation406, as illustrated inFIG.4, in which a channel structure extending vertically through the dielectric stack and the filling layer is formed. The channel structure can include a memory film and a semiconductor channel. In some implementations, to form the channel structure, a channel hole extending vertically through the dielectric stack, the filling layer, and the third stop layer is formed, stopping at the second stop layer, and the memory film and the semiconductor channel are sequentially formed along a sidewall of and a bottom surface of the channel hole.

As illustrated inFIG.3B, each channel hole is an opening extending vertically through dielectric stack308, filling layer306, and third stop layer305, stopping at second stop layer304. In some implementations, a plurality of openings are formed, such that each opening becomes the location for growing an individual channel structure314in the later process. In some implementations, fabrication processes for forming the channel holes of channel structures314include wet etching and/or dry etching, such as deep RIE (DRIE). The etching of the channel holes continues until being stopped by second stop layer304, such as silicon oxide or polysilicon, according to some implementations. In some implementations, the etching conditions, such as etching rate and time, can be controlled to ensure that each channel hole has reached and stopped by second stop layer304to minimize the gouging variations among the channel holes and channel structures314formed therein. It is understood that depending on the specific etching selectivity, one or more channel holes may extend into second stop layer304to a small extent, which is still viewed as being stopped by second stop layer304in the present disclosure.

As illustrated inFIG.3B, a memory film including a blocking layer317, a storage layer316, and a tunneling layer315, and a semiconductor channel318are sequentially formed in this order along sidewalls and the bottom surface of the channel hole. In some implementations, blocking layer317, storage layer316, and tunneling layer315are first deposited along the sidewalls and bottom surface of the channel hole in this order using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, to form the memory film. Semiconductor channel318then can be formed by depositing a semiconductor material, such as polysilicon (e.g., undoped polysilicon), over tunneling layer315using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some implementations, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (a “SONO” structure) are sequentially deposited to form blocking layer317, storage layer316, and tunneling layer315of the memory film and semiconductor channel318.

As illustrated inFIG.3B, a capping layer is formed in the channel hole and over semiconductor channel318to completely or partially fill the channel hole (e.g., without or with an air gap). The capping layer can be formed by depositing a dielectric material, such as silicon oxide, using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. A channel plug can then be formed in the top portion of the channel hole. In some implementations, parts of the memory film, semiconductor channel318, and the capping layer that are on the top surface of dielectric stack308are removed and planarized by CMP, wet etching, and/or dry etching. A recess then can be formed in the top portion of the channel hole by wet etching and/or drying etching parts of semiconductor channel318and the capping layer in the top portion of the channel hole. The channel plug can then be formed by depositing semiconductor materials, such as polysilicon, into the recess by one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof. Channel structure314is thereby formed through dielectric stack308, filling layer306, and third stop layer305, stopping at second stop layer304, according to some implementations.

As illustrated inFIG.3C, a slit320is an opening that extends vertically through dielectric stack308and stops at filling layer306. In some implementations, fabrication processes for forming slit320include wet etching and/or dry etching, such as DRIE. A gate replacement then can be performed through slit320to replace dielectric stack308with a memory stack330(shown inFIG.3E).

As illustrated inFIG.3D, lateral recesses322are first formed by removing stack sacrificial layers312(shown inFIG.3C) through slit320. In some implementations, stack sacrificial layers312are removed by applying etchants through slit320, creating lateral recesses322interleaved between stack dielectric layers310. The etchants can include any suitable etchants that etch stack sacrificial layers312selective to stack dielectric layers310.

As illustrated inFIG.3E, stack conductive layers328(including gate electrodes and adhesive layers) are deposited into lateral recesses322(shown inFIG.3D) through slit320. In some implementations, a gate dielectric layer332is deposited into lateral recesses322prior to stack conductive layers328, such that stack conductive layers328are deposited on gate dielectric layer332. Stack conductive layers328, such as metal layers, can be deposited using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some implementations, gate dielectric layer332, such as a high-k dielectric layer, is formed along the sidewall and at the bottom of slit320as well. Memory stack330including interleaved stack conductive layers328and stack dielectric layers310is thereby formed, replacing dielectric stack308(shown inFIG.3D), according to some implementations.

As illustrated inFIG.3E, an insulating structure336extending vertically through memory stack330is formed, stopping on the top surface of filling layer306. Insulating structure336can be formed by depositing one or more dielectric materials, such as silicon oxide, into slit320to fully or partially fill slit320(with or without an air gap) using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. In some implementations, insulating structure336includes gate dielectric layer332(e.g., including high-k dielectrics) and a dielectric capping layer334(e.g., including silicon oxide). Although not shown, in some examples, dielectric capping layer334may partially fill the slit320, and a polysilicon core layer (not shown) may fill the remaining space of slit320as part of insulating structure336to adjust the mechanical properties, such as hardness or stress, of insulating structure336.

As illustrated inFIG.3F, after the formation of insulating structure336, local contacts, including channel local contacts344and word line local contacts342, and peripheral contacts338and340are formed. A local dielectric layer can be formed on memory stack330by depositing dielectric materials, such as silicon oxide or silicon nitride, using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof, on top of memory stack330. Channel local contacts344, word line local contacts342, and peripheral contacts338and340can be formed by etching contact openings through the local dielectric layer (and any other ILD layers) using wet etching and/or dry etching, e.g., RIE, followed by filling the contact openings with conductive materials using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

As illustrated inFIG.3F, a bonding layer346is formed above channel local contacts344, word line local contacts342, and peripheral contacts338and340. Bonding layer346includes bonding contacts electrically connected to channel local contacts344, word line local contacts342, and peripheral contacts338and340. To form bonding layer346, an ILD layer is deposited using one or more thin film deposition processes, such as CVD, PVD, ALD, or any combination thereof, and the bonding contacts are formed through the ILD layer using wet etching and/or dry etching, e.g., RIE, followed by one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof.

Method400proceeds to operation408, as illustrated inFIG.4, in which the first substrate and the second substrate are bonded in a face-to-face manner, such that the memory stack is above the peripheral circuit. The bonding can include hybrid bonding. As illustrated inFIG.3G, carrier substrate302and components formed thereon (e.g., memory stack330and channel structures314formed therethrough) are flipped upside down. Bonding layer346facing down is bonded with bonding layer348facing up, i.e., in a face-to-face manner, thereby forming a bonding interface354between carrier substrate302and silicon substrate350, according to some implementations. In some implementations, a treatment process, e.g., a plasma treatment, a wet treatment, and/or a thermal treatment, is applied to the bonding surfaces prior to the bonding. After the bonding, the bonding contacts in bonding layer346and the bonding contacts in bonding layer348are aligned and in contact with one another, such that memory stack330and channel structures314formed therethrough can be electrically connected to peripheral circuits352and are above peripheral circuits352.

Method400proceeds to operation410, as illustrated inFIG.4, in which the second substrate and part of the memory film are sequentially removed to expose part of the semiconductor channel facing the filling layer. The removal can be performed from the backside of the second substrate. In some implementations, the removed part of the memory film faces the filling layer. In some implementations, to sequentially remove the second substrate and the part of the memory film, the second substrate is removed, stopping at the first stop layer, the first stop layer and the second stop layer are removed, stopping at the third stop layer, the third stop layer is patterned to expose the memory film, and the exposed memory film is etched, stopping prior to or at an interface between the stack structure and the filling layer, to form a recess surrounding the exposed part of the semiconductor channel. In some implementations, the exposed part of the semiconductor channel is doped. The dopants can include an N-type dopant.

As illustrated inFIG.3H, carrier substrate302(and a pad oxide layer between carrier substrate302and first stop layer303, shown inFIG.3G) are completely removed from the backside until being stopped by first stop layer303(e.g., a silicon nitride layer). Carrier substrate302can be completely removed using CMP, grinding, dry etching, and/or wet etching. In some implementations, carrier substrate302is peeled off In some implementations in which carrier substrate302includes silicon and first stop layer303includes silicon nitride, carrier substrate302is removed using silicon CMP, which can be automatically stopped when reaching first stop layer303having materials other than silicon, i.e., acting as a backside CMP stop layer. In some implementations, carrier substrate302(a silicon substrate) is removed using wet etching by tetramethylammonium hydroxide (TMAH), which is automatically stopped when reaching first stop layer303having materials other than silicon, i.e., acting as a backside etch stop layer. First stop layer303can ensure the complete removal of carrier substrate302without the concern of thickness uniformity after thinning.

As shown inFIG.31, first and second stop layers303and304(shown inFIG.3H) then can be completely removed as well using wet etching with suitable etchants, such as phosphoric acid and hydrofluoric acid, until being stopped by third stop layer305having a different material (e.g., silicon nitride) from second stop layer304. In some implementations, third stop layer305is patterned to expose the memory film (having storage layer316, blocking layer317, and tunneling layer315) of each channel structure314using lithography and etching, while still covering filling layer306. It is understood that in case each channel structure314extends through stopped by third stop layer305, the patterning process may be skipped. In some implementations, third stop layer305is removed after removing second stop layer304using wet etching by phosphoric acid.

As illustrated inFIG.3J, parts of storage layer316, blocking layer317, and tunneling layer315(shown inFIG.31) facing filling layer306are removed to form a recess357surrounding the top portion of semiconductor channel318extending beyond memory stack330. For example, the exposed memory film of channel structure314may be etched, stopping prior to or at the interface between memory stack330and filling layer306, to form recess357surrounding the exposed part of semiconductor channel318. In some implementations, two wet etching processes are sequentially performed. For example, storage layer316including silicon nitride is selectively removed using wet etching with suitable etchants, such as phosphoric acid. The etching of storage layer316can be controlled by controlling the etching time and/or etching rate, such that the etching does not continue beyond the top surface of memory stack330. Then, blocking layer317and tunneling layer315including silicon oxide may be selectively removed using wet etching with suitable etchants, such as hydrofluoric acid, without etching semiconductor channel318including polysilicon. The etching of blocking layer317and tunneling layer315can be controlled by controlling the etching time and/or etching rate, such that the etching does not continue beyond the top surface of memory stack330. That is, the etching of the memory film can be controlled such that the bottom surface of resulting recess357is above or flush with the top surface of memory stack330.

In some implementations, a single dry etching process is performed, using third stop layer305(shown inFIG.31) as the etching mask. For example, third stop layer305may not be removed when performing the dry etching, but instead, may be patterned to expose only storage layer316, blocking layer317, and tunneling layer315at the upper ends of channel structure314, while still covering other areas as an etching mask. A dry etching then may be performed to etch parts of storage layer316, blocking layer317, and tunneling layer315facing filling layer306. The dry etching can be controlled by controlling the etching time and/or etching rate, such that the etching does not continue beyond the top surface of memory stack330. Third stop layer305may be removed once the dry etching is finished.

Nevertheless, the removal of parts of storage layer316, blocking layer317, and tunneling layer315facing filling layer306from the backside is much less challenging and has a higher production yield compared with the known solutions using front side wet etching via the openings (e.g., slit320inFIG.3D) through dielectric stack308/memory stack330with a high aspect ratio (e.g., greater than 50). By avoiding the issues introduced by the high aspect ratio of slit320, the fabrication complexity and cost can be reduced, and the yield can be increased. Also, the vertical scalability (e.g., the increasing level of dielectric stack308/memory stack330) can be improved as well.

As illustrated in FIG,3J, the top portion of the memory film (including blocking layer317, storage layer316, and tunneling layer315) of each channel structure314can be removed to form recess357, exposing the top surface and the sidewall of at least part of semiconductor channel318extending beyond memory stack330(facing filling layer306), according to some implementations. In some implementations, the top portion of semiconductor channel318exposed by recess357is doped to increase its conductivity. For example, a tilted ion implantation process may be performed to dope the top portion of semiconductor channel318(e.g., including polysilicon) exposed by recess357with any suitable dopants (e.g., N-type dopants such as P, As, or Sb) to a desired doping concentration. In some implementations, the bottom surface of recess357is flush with the top surface of memory stack330to expose the entire sidewall of the part of semiconductor channel318extending beyond memory stack330to maximize the area for ion implantation.

Method400proceeds to operation412, as illustrated inFIG.4, in which a doped semiconductor layer in contact with the exposed part of the semiconductor channel is formed. In some implementations, the dopants include an N-type dopant. In some implementations, to form the doped semiconductor layer, a layer of polysilicon is deposited into the recess and onto the filling layer, and the deposited layer of polysilicon is doped.

As illustrated inFIG.3K, a doped semiconductor layer360is formed in recess357(shown inFIG.3J), surrounding and in contact with the exposed part of semiconductor channel318, as well as outside of recess357on filling layer306. In some implementations, to form doped semiconductor layer360, a semiconductor layer (e.g., polysilicon) is deposited in recess357in contact with the exposed part of semiconductor channel318and outside of recess357in contact with filling layer306using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. The deposited semiconductor layer can be doped with N-type dopant(s), such as P, As, or Sb, using ion implantation and/or thermal diffusion. In some implementations, to form doped semiconductor layer360, in-situ doping of N-type dopants, such as P, As, or Sb, is performed when depositing the semiconductor layer into recess357and on filling layer306. In some implementations, a ClVIP process can be performed to remove any excess doped semiconductor layer360as needed.

Method400proceeds to operation414, as illustrated inFIG.4, in which the doped semiconductor layer and the part of the semiconductor channel in contact with the doped semiconductor layer are locally activated. In some implementations, to locally activate, heat is applied in a confined area having the doped semiconductor layer and the part of the semiconductor channel to activate dopants in the doped semiconductor layer and the part of the semiconductor channel. The confined area can be between the stack structure and the doped semiconductor layer. In some implementations, the doping concentration of the doped semiconductor layer and the doping concentration of the part of the semiconductor channel in contact with the doped semiconductor layer each is between 1019cm−3and 1021cm−3after the activation.

As illustrated inFIG.3L, doped semiconductor layer360and the part of semiconductor channel318in contact with doped semiconductor layer360are locally activated. In some implementations, heat is applied in a confined area having doped semiconductor layer360and the part of semiconductor channel318to activate the dopant(s) therein, such as N-type dopants (e.g., P, As, or Sb). For example, the confined area may be between memory stack330and doped semiconductor layer360in the vertical direction. The heat can be applied and focused by any suitable techniques, such as annealing, laser, ultrasound, or any other suitable thermal processes. In some implementations, the confined area that can be affected by the heat during the local activation process does not extend to and beyond bonding interface354to avoid heating bonding interface354and Cu interconnects used for connecting peripheral circuits352. The local activation process can activate the dopants doped into doped semiconductor layer360(and the exposed part of semiconductor channel318in case it is already doped). As a result, the doping concentration of doped semiconductor layer360and the doping concentration of the exposed part of semiconductor channel318each is between 1019cm−3and 1021cm−3after the activation. In some implementations, the local activation process is controlled such that the dopants in doped semiconductor layer360(and in the exposed part of semiconductor channel318in case it is already doped) can diffuse from the source of channel structure314towards the drain of channel structure314until beyond the source select gate line(s) (e.g., one or more stack conductive layers328closest to filling layer306), but not facing the word lines, as described above with respect toFIG.2.

The local activation process can activate the dopants such that the dopants can occupy the silicon lattices to reduce the contact resistance between doped semiconductor layer360and semiconductor channel318as well as to reduce the sheet resistance of doped semiconductor layer360. On the other hand, by confining the heat during the local activation process into an area without heat-sensitive structures, any potential damages to the heat-sensitive structures, such as bonding interface354and Cu interconnects used for connecting peripheral circuits352, can be reduced or avoided.

Method400proceeds to operation416, as illustrated inFIG.4, in which a source contact is formed in contact with the doped semiconductor layer. As illustrated inFIG.3M, one or more ILD layers356are formed on doped semiconductor layer360. ILD layers356can be formed by depositing dielectric materials on the top surface of doped semiconductor layer360using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof. As illustrated inFIG.3N, source contact openings358can be formed through ILD layers356to expose parts of doped semiconductor layer360. In some implementations, source contact opening358is formed using wet etching and/or dry etching, such as RIE.

As illustrated inFIG.3O, a source contact, as part of conductive layer370, is formed in each source contact opening358(shown inFIG.3N) at the backside of filling layer306. The source contact is above and in contact with doped semiconductor layer360, according to some implementations. In some implementations, conductive layer370, such as Al, is deposited into source contact opening358using one or more thin film deposition processes, such as ALD, CVD, PVD, any other suitable processes, or any combination thereof, to fill source contact opening358. A planarization process, such as CMP, can then be performed to remove excess conductive layer370.

As illustrated inFIG.3O, in some implementations, conductive layer370also includes a redistribution layer above and in contact with the source contacts. That is, conductive layer370is not only deposited into source contact openings358as the source contacts, but also deposited outside of source contact openings358onto ILD layers356as the redistribution layer that electrically connects multiple source contacts, according to some implementations.

As illustrated inFIG.3O, in some implementations, conductive layer370further includes contacts extending through ILD layers356, doped semiconductor layer360, and filling layer306. That is, conductive layer370is not only deposited into source contact openings358as the source contacts, but also deposited into contact openings363and361(shown inFIG.3N) as the contacts that are electrically connected to peripheral contacts338and340. As illustrated inFIGS.3M and3N, contact openings363and361each extending through a spacer layer371, ILD layers356, doped semiconductor layer360, and filling layer306are formed using wet etching and/or dry etching, such as RIE. In some implementations, contact openings363and361are patterned using lithography to be aligned with peripheral contacts338and340, respectively. The etching of contact openings363and361can stop at the upper ends of peripheral contacts338and340to expose peripheral contacts338and340. As illustrated inFIG.3N, a spacer362is formed from spacer layer371along the sidewalls of contact openings363and361to electrically separate doped semiconductor layer360.

According to one aspect of the present disclosure, a 3D memory device includes a stack structure including interleaved conductive layers and dielectric layers, a channel structure extending through the stack structure, and a doped semiconductor layer. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion and an undoped portion. A part of the doped portion of the semiconductor channel extends beyond the stack structure in a first direction. A part of the doped semiconductor layer is in contact with a sidewall of the part of the doped portion of the semiconductor channel that extends beyond the stack structure.

In some implementations, a doping concentration of the doped portion of the semiconductor channel and a doping concentration of the doped semiconductor layer each is between 1019cm−3and 1021cm−3.

In some implementations, the doped portion of the semiconductor channel and the doped semiconductor layer each includes N-type doped polysilicon.

In some implementations, the doped portion of the semiconductor channel extends beyond one of the conductive layers in a second direction opposite to the first direction.

In some implementations, the one of the conductive layers includes a source select gate line.

In some implementations, the 3D memory device further includes a filling layer between the stack structure and another part of the doped semiconductor layer in the first direction.

In some implementations, the filling layer includes polysilicon, a high-k dielectric, or a metal.

In some implementations, the 3D memory device further includes a source contact in contact with the doped semiconductor layer.

In some implementations, one end of the memory film is flush with or exceeds a corresponding surface of the stack structure.

In some implementations, the 3D memory device is configured to generate GIDL-assisted body bias when performing an erase operation.

According to another aspect of the present disclosure, a 3D memory device includes a stack structure including interleaved conductive layers and dielectric layers, a doped semiconductor layer, and a channel structure extending through the stack structure to the doped semiconductor layer. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion. The doped portion of the semiconductor channel is between the doped semiconductor layer and one of the conductive layers that is closest to the doped semiconductor layer.

In some implementations, a doping concentration of the doped portion of the semiconductor channel and a doping concentration of the doped semiconductor layer each is between 1019cm−3and 1021cm−3.

In some implementations, the doped portion of the semiconductor channel and the doped semiconductor layer each includes N-type doped polysilicon.

In some implementations, the one of the conductive layers comprises a source select gate line.

In some implementations, part of the doped semiconductor layer is in contact with the doped portion of the semiconductor channel.

In some implementations, the 3D memory device further includes a filling layer between the stack structure and another part of the doped semiconductor layer.

In some implementations, the filling layer comprises polysilicon, a high-k dielectric, or a metal.

In some implementations, the 3D memory device further includes a source contact in contact with the doped semiconductor layer.

In some implementations, one end of the memory film is flush with or exceeds a corresponding surface of the stack structure.

In some implementations, the 3D memory device is configured to generate GIDL-assisted body bias when performing an erase operation.

According to still another aspect of the present disclosure, a method for forming a 3D memory device is provided. A filling layer is formed above a substrate. A stack structure is formed above the filling layer. A channel structure extending through the stack structure and the filling layer is formed. The channel structure includes a memory film and a semiconductor channel. The substrate and part of the memory film are sequentially removed to expose part of the semiconductor channel facing the filling layer. A doped semiconductor layer is formed in contact with the exposed part of the semiconductor channel. The doped semiconductor layer and the part of the semiconductor channel in contact with the doped semiconductor layer are locally activated.

In some implementations, to locally activate, heat is applied in a confined area having the doped semiconductor layer and the part of the semiconductor channel to activate dopants in the doped semiconductor layer and the part of the semiconductor channel.

In some implementations, each of the channel structures includes a memory film and a semiconductor channel, and the metal silicide layer is in contact with the semiconductor channels of the plurality of channel structures.

In some implementations, the confined area is between the stack structure and the doped semiconductor layer.

In some implementations, the dopants include an N-type dopant, and after the activation, a doping concentration of the doped semiconductor layer and a doping concentration of the part of the semiconductor channel in contact with the doped semiconductor layer each is between 1019cm−3and 1021cm−3.

In some implementations, prior to forming the doped semiconductor layer, the exposed part of the semiconductor channel is doped.

In some implementations, a first stop layer, a second stop layer, and a third stop layer are sequentially formed between the substrate and the filling layer.

In some implementations, the first stop layer includes silicon oxide or silicon nitride, the second stop layer includes silicon oxide or polysilicon, the third stop layer includes silicon nitride or polysilicon, and the filling layer includes polysilicon.

In some implementations, to form the channel structure, a channel hole is formed extending through the stack structure, the filling layer, and the third stop layer, stopping at the second stop layer, and the memory film and the semiconductor channel are sequentially formed along a sidewall and a bottom surface of the channel hole.

In some implementations, to sequentially remove the substrate, and the part of the memory film, the substrate is removed, stopping at the first stop layer, the first stop layer and the second stop layer are removed, stopping at the third stop layer, the third stop layer is patterned to expose the memory film, and the exposed memory film is etched, stopping prior to or at an interface between the stack structure and the filling layer, to form a recess surrounding the exposed part of the semiconductor channel.

In some implementations, to form the doped semiconductor layer, a layer of polysilicon is deposited into the recess and onto the filling layer, and the deposited layer of polysilicon is doped.

In some implementations, after locally activating the doped semiconductor layer, a source contact is formed in contact with the doped semiconductor layer.

According to yet another aspect of the present disclosure, a system includes a 3D memory device configured to store data and a memory controller coupled to the 3D memory device and configured to control the 3D memory device. The 3D memory device includes a stack structure including interleaved conductive layers and dielectric layers, a channel structure extending through the stack structure, and a doped semiconductor layer. The channel structure includes a memory film and a semiconductor channel. The semiconductor channel includes a doped portion and an undoped portion. A part of the doped portion of the semiconductor channel extends beyond the stack structure in a first direction. A part of the doped semiconductor layer is in contact with a sidewall of the part of the doped portion of the semiconductor channel that extends beyond the stack structure.

In some implementations, the system further includes a host coupled to the memory controller.

In some implementations, a doping concentration of the doped portion of the semiconductor channel and a doping concentration of the doped semiconductor layer each is between 1019cm−3and 1021cm−3.

In some implementations, the doped portion of the semiconductor channel and the doped semiconductor layer each includes N-type doped polysilicon.

In some implementations, the doped portion of the semiconductor channel extends beyond one of the conductive layers in a second direction opposite to the first direction.

In some implementations, the one of the conductive layers includes a source select gate line.

In some implementations, the 3D memory device further includes a filling layer between the stack structure and another part of the doped semiconductor layer in the first direction.

In some implementations, the filling layer includes polysilicon, a high-k dielectric, or a metal.

In some implementations, the 3D memory device further includes a source contact in contact with the doped semiconductor layer.

In some implementations, one end of the memory film is flush with or exceeds a corresponding surface of the stack structure.

In some implementations, the 3D memory device is configured to generate GIDL-assisted body bias when performing an erase operation.

The foregoing description of the specific implementations can be readily modified and/or adapted for various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents.