Patent ID: 12236098

DETAILED DESCRIPTION OF THE EMBODIMENTS

In the following detailed description, certain embodiments of the present disclosure have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification. In the flowchart described with reference to the drawings, the order of operations may be changed, several operations may be merged, a certain operation may be divided, and a specific operation may not be performed.

In addition, expressions written in the singular can be interpreted as singular or plural, unless explicit expressions such as “one” or “single” are used. Terms containing ordinal numbers, such as first and second, may be used to describe various configurations elements, but constituent elements are not limited by these terms. These terms may be used for the purpose of distinguishing one constituent element from another constituent element.

FIG.1is a block diagram of a computing system according to an embodiment of the present disclosure.

Referring toFIG.1, a computer system100may include a host110, a memory120, and at least one compute express link (CXL) device150. The computer system100may be used by a plurality of users, and each user may use at least one CXL device150through the host110. At least one CXL device150may include first to nthCXL devices150-1to150-n, where n is a natural number greater than or equal to 1. In some embodiments, the computer system100may be included in user computing devices, such as a personal computer (PC), a laptop computer, a server, a media player, a digital camera, and the like, or an automotive device, such as a navigation device, a black box, and electric vehicle equipment. Alternatively, the computer system100may be a mobile system, such as a portable communication terminal (e.g., a mobile phone), a smart phone, a tablet PC, a wearable device, a health care device, or an Internet of Things (IoT) device.

The host110may control the overall operation of the computer system100. In an embodiment, the host110may be implemented by various processors, such as one of a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a data processing unit (DPU), and the like. In an embodiment, the host110may include a single core processor or a multicore processor.

In an embodiment, at least one CXL device150may operate as a cache buffer for the host110. That is, the host110may use memories153-1to153-nof the at least one CXL device150as a cache buffer.

The host110may generate a signal for the at least one CXL device150and/or the memory120. A signal may include a command and an address. In some embodiments, commands may include write commands or read commands. In some embodiments, the command may include an activate command and a read/write command. In some embodiments, the command may further include a pre-charge command, a refresh command, and the like.

The activate command may be a command that converts a target row of the memories153-1to153-nof the at least one CXL device150into an active state to write data to or read data from the at least one CXL device150. Alternatively, the activate command may be a command that activates a target row of the memory120to write data to or read data from the memory120. The at least one CXL device150and/or the memory120may activate (e.g., drive) a memory cell of a target row in response to an activate command. The read/write command may be a command for performing a read or write operation of a target memory cell of a row converted to an active state.

The host110may communicate with the at least one CXL device150using a different protocol. For example, the host110may communicate with the at least one CXL device150using at least one of a CXL.io protocol, a CXL.mem protocol, and a CXL.cache protocol.

The CXL.io protocol may be a protocol supported by the at least one CXL device150. The host110may perform an initial configuration of the at least one CXL device150, a memory capacity configuration, a virtualization, a device search and connection, and a register access using the CXL.io protocol.

The CXL.mem protocol may be a protocol that supports the host110to access the memories153-1to153-nof the at least one CXL device150. The host110may recognize the memories153-1to153-nas additional memory spaces using the CXL.mem protocol. The CXL.mem protocol may support architectural memories153-1to153-n, such as a volatile memory and a persistent memory.

The CXL.cache protocol may be a protocol supporting the at least one CXL device150to access the memory120of the host110to implement cache coherence. The CXL.cache protocol defines the interaction between the host110and the at least one CXL device150, and the at least one CXL device150may effectively cache the memory120of the host110.

In an embodiment, the host110may execute at least one process using a requester. By executing the process, the host110may simultaneously transmit a first signal and a second signal to one CXL device (e.g., the CXL device150-1). That is, the CXL device150-1may simultaneously receive the first signal and the second signal. The first signal may include a requester identifier (ID). The second signal may include a command, an address, and a metadata field. The metadata field may include information indicating a request type. The request type may include an emergency request and a normal request. In some embodiments, the first signal and the second signal may further include additional data. The host110may transmit a first signal to the at least one CXL device150using the CXL.io protocol. The host110may transmit the second signal different than the first signal to the at least one CXL device150using the CXL.mem protocol.

The at least one CXL device150may generate a command queue in which a plurality of commands are scheduled. In some embodiments, the command queue may be a “first-in-first-out” (FIFO) command queue. The at least one CXL device150may operate based on the command queue. In some embodiments, the CXL device150-1that receives the first signal and the second signal schedules a plurality of commands (commands included in the second signal and scheduled in the command queue of the CXL device150-1) based on the first signal and the second signal.

Since the CXL protocol operates with non-deterministic latency, a CXL device may sequentially process a plurality of commands output from a host in a conventional computer system. In the embodiments described herein, the computer system100schedules a plurality of commands based on the first signal and the second signal. Accordingly, while the CXL protocol may still operate with non-deterministic latency, the at least one CXL device150prioritizes an urgent process. An embodiment in which the at least one CXL device150schedules a plurality of commands using a first signal and a second signal is described below with reference toFIGS.2-5.

The memory120may be a main memory or a system memory of the computer system100. In an embodiment, the memory120may be a dynamic random access memory (DRAM) device and may have a form factor of a dual in-line memory module (DIMM). However, the present disclosure is not limited thereto, and the memory120may include a non-volatile memory, such as a flash memory, a phase-change memory (PRAM), a resistive random-access memory (RRAM), and a magnetoresistive random-access memory (MRAM).

In some embodiments, the host110may be directly connected to the memory120. In some embodiments, the memory120may communicate directly with the host110through a double data rate (DDR) interface. In an embodiment, the host110may include a memory controller formed to control the memory120. However, one or more embodiments of the present disclosure are not limited thereto, and the memory120may communicate with the host110through various interfaces.

The at least one CXL device150may include CXL controllers151-1to151-nand the memories153-1to153-n. In an embodiment, the memories153-1to153-nmay operate as cache buffers for each of the at least one CXL devices150. That is, the at least one CXL device150may use each of memories153-1to153-nas a cache buffer.

The CXL controllers151-1to151-nmay include an intellectual property (IP) circuit (or IP cores) designed to implement an application specific integrated circuit (ASIC) and/or a field-programmable gate array (FPGA). In various embodiments, the CXL controllers151-1-151-nmay be implemented to support the CXL protocol (e.g., the CXL 2.0 protocol, the CXL 3.0 protocol, or various other CXL protocols). The CXL controllers151-1to151-nmay exchange CXL packets and signals of a memory interface of the memory120with each other.

In an embodiment, each of the at least one CXL device150may be implemented as an individual memory device or memory module. Each of the at least one CXL device150may be connected to the CXL interface140through different physical ports. That is, the at least one CXL device150connected to the CXL interface140may be used as an individual memory device or memory module, and a memory region managed by the host110may be increased to have high-capacity.

The memories153-1to153-ninclude at least one of a Dynamic Random Access Memory (DRAM), a Not-AND (NAND) flash memory, a High Bandwidth Memory (HBM), a Hybrid Memory Cube (HMC), a Dual In-line Memory Module (DIMM), an Optane DIMM, a Non-Volatile Memory DIMM (NVMDIMM), a Double Data Rate Synchronous DRAM (DDR SDRAM), and a Low-Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR SDRAM) or a combination thereof.

In an embodiment, the host110and the at least one CXL device150may share the same interface. For example, the host110and the at least one CXL device150may communicate with each other through the CXL interface140. In an embodiment, the CXL interface140may be a low-latency and high-bandwidth link that enables various connections between accelerators, memory devices, or various electronic devices by supporting coherency, memory access, and dynamic protocol multiplexing (MUX) of an input/output protocol (I/O protocol).

InFIG.1, the host110and at least one CXL device150may communicate with each other through the CXL interface140, but this is not restrictive. For example, the host110and the at least one CXL device150may communicate with each other based on various computing interfaces, such as a GEN-Z protocol, an NVLink protocol, a cache coherent interconnect for accelerators (CCIX) protocol, and an Open coherent accelerator processor interface (CAPI) protocol.

FIG.2is provided for description of operations of a host and a CXL device according to an embodiment, andFIG.3is a schematic block diagram of a CXL device according to an embodiment.

Referring toFIG.2, a host200according to an embodiment is used by at least one requester and may execute a plurality of processes. The plurality of processes may each correspond to at least one requester. That is, at least one requester may issue a plurality of processes. Each process may generate a command and transmit the generated command to a CXL device300. That is, the CXL device300may receive a plurality of commands based on a plurality of processes. The CXL device300may schedule and process the plurality of commands according to a processing policy. For example, the processing policy may include a requester's priority, a request type, and the like.

The host200may transmit a first signal and a second signal to the CXL device300using different protocols. For example, the host200may transmit a first signal to the CXL device300using the CXL.io protocol and transmit a second signal to the CXL device300using the CXL.mem protocol. The first signal may include a requester identifier. The second signal may include a command, an address, and a metadata field. In some embodiments, the first signal and the second signal may include additional data. For example, additional data may include data indicating size of the first signal and the second signal.

The CXL device300may include a request register310that receives the first signal and a checker module320that receives the second signal. The time at which the request register310receives the first signal and the time at which the checker module320receives the second signal may be the same. The request register310may transmit the priority of the requester to the checker module320based on the first signal. The checker module320may determine the priority of the plurality of commands based on the second signal and the determined requester. In other words, the CXL device300may schedule a plurality of commands output by a plurality of processes of the host200based on the first signal and the second signal. The CXL device300may control memory operations based on the scheduled commands.

Referring toFIG.3, the CXL device300according to an embodiment may include the request register310, the checker module320, a command generator330, a memory controller340, and a memory350.

The request register310may store requester IDs of a plurality of requesters (or a plurality of processes) using the host200and priorities corresponding to the requester IDs. The host200may record a plurality of requester IDs and priorities in the request register310using the CXL.io protocol. The plurality of requesters may have different priorities. For example, the plurality of requesters may use host200with different service-level agreements (SLAs). The host200may determine priorities of the plurality of requesters based on the SLA. The host200may determine a high priority for a requester with a relatively short SLA and a low priority for a requester with a relatively long SLA. In some embodiments, the host200may record, in the request register310, the requester ID of the requester to be processed with priority.

Upon receiving the first signal from the host200, the request register310may transmit the priority of the requester corresponding to the requester identifier included in the first signal to the checker module320.

The checker module320may determine the priorities of the plurality of commands of the host200according to a processing policy. For example, the processing policy may include requester's priority, request type, and the like.

The checker module320may receive the priority of the requester from the request register310. The checker module320may receive a second signal including a command, an address, and a metadata field from the host200. The host200may generate and fill the metadata field with a first value for emergency requests. The host200may generate and fill the metadata field with a second value for normal requests. The first value and the second value may be different from each other. In an embodiment, the first value may be “1” and the second value may be “0”. However, the first value and the second value are not limited thereto, and the first value may be “0” and the second value may be “1”.

In an embodiment, the metadata field may be 2 bits. The host200may fill the metadata field with a third value for emergency requests. For example, the third value may be any one of “11”, “10”, “01”, and “00”. The host200may fill the metadata field with a fourth value that is different from the third value for a normal request. For example, the third value may be “10” and the fourth value may be “01”, but an embodiment of the present disclosure may not be limited thereto.

The checker module320may determine the priorities of the plurality of commands based on the priority of the requester and the request type (or the value of the metadata field). For example, the checker module320may determine the priorities of the plurality of commands as shown in Table 1. In Table 1, the lower the priority number of the command, the higher priority may be indicated. That is, the lower the number, the higher the priority.

TABLE 1COMMAND PRIORITYREQUESTER PRIORITYREQUEST TYPE1HIGHEMERGENCY2LOWEMERGENCY3HIGHNORMAL4LOWNORMAL

Referring to Table 1, the checker module320may determine the priority of a command with an emergency request type higher than that of a command with a normal request type. The checker module320may determine the priority of a command having a high requester priority higher than that of a command having a low requester priority.

The checker module320may determine the priority of the plurality of commands based on the request type and the priority of the requester. For example, the checker module320may first determine the priority of a command with an emergency request type higher than that of a command with a normal request type. Afterwards, the checker module320may determine a higher priority of a command having a higher requester priority than a command having a lower requester priority with respect to commands having the same request type.

That is, the checker module320may determine the priority of a command with an emergency request type and a high requester priority as “1”, the priority of a command with an emergency request type and a low requester priority as “2”, the priority of a command with a general request type and a high requester priority as “3”, and the priority of a command with a normal request type and a low requester priority as “4”.

In the present embodiment, it has been described that the checker module320primarily considers the request type and secondarily considers the priority of the requester, but is not necessarily limited thereto, and the checker module320may be implemented to primarily consider the priority of the requester and secondarily consider the request type in other embodiments.

In an embodiment, when the host200records only the ID of the requester to be processed with priority in the request register310, the priority of the requester in Table 1 can be classified as YES or NO. In this case, yes/no may respectively correspond to the above-described high/low classifications.

The checker module320may transmit a plurality of commands, a plurality of addresses, and priorities of the plurality of commands to the command generator330.

The command generator330may generate internal commands based on the plurality of commands, the plurality of addresses, and the priorities of the plurality of commands. The internal commands may include information indicating a command type, an address, and a priority. The command generator330may transmit the internal command to the memory controller340. In some embodiments, the command generator330may be implemented such that it is disposed within the memory controller340.

The memory controller340may create a command queue by scheduling a plurality of internal commands. The memory controller340may perform scheduling according to the priority of commands. For example, the memory controller340may include a heuristic scheduler that processes commands according to priorities. The memory controller340may generate a command queue using the heuristic scheduler. In an embodiment, the memory controller340may dispose a high-priority internal command to the right of the command queue. The memory controller340may dispose an internal command having a low priority to the left side of the command queue. In this case, the memory controller340may sequentially transmit internal commands to the memory350from the right side based on the command queue.

The memory350may operate based on the internal commands. Internal commands for urgent processes are disposed on the right side of the command queue and transmitted to the memory350first, and thus the memory350can process urgent processes first. That is, while a conventional CXL device does not process an urgent process in one embodiment, the CXL device300has an advantage of processing an urgent process with priority.

FIG.4illustrates an operation of a host and a CXL device according to an embodiment, andFIG.5is a schematic block diagram of the CXL device according to an embodiment.

Referring toFIG.4, a host400according to an embodiment is used by at least one requester, and may execute a plurality of processes. A plurality of processes may each correspond to at least one requester. Each process may generate a first command and transmit the first command to a CXL device500. That is, the CXL device500may receive a plurality of first commands from the plurality of processes. In addition, the CXL device500may process a plurality of second commands output by an accelerator530within the CXL device500. The CXL device500may schedule and process a plurality of commands including a first command and a second command according to a processing policy. For example, the processing policy may include a requester's priority, a request type, and the like.

The host400may transmit a first signal and a second signal to the CXL device500using different protocols. For example, the host400may transmit the first signal to the CXL device500using a CXL.io protocol and transmit the second signal to the CXL device500using a CXL.mem protocol. The first signal may include a requester identifier. The second signal may include the first command, an address, and a metadata field.

The accelerator530may transmit a third signal to a checker module520of the CXL device500using the CXL.mem protocol. The third signal may include the second command, an address, and a metadata field. In an embodiment, the accelerator530may be disposed inside the CXL device500. In some embodiments, the accelerator530may be implemented such that it is disposed externally from the CXL device500. In addition, the first signal, the second signal, and the third signal may further include additional data.

The CXL device500may include a request register510for receiving the first signal and the checker module520for receiving the second signal and the third signal. The time at which the request register510receives the first signal and the time at which the checker module520receives the second signal may be the same. The request register510may transmit the priority of the requester to the checker module520based on the first signal. The checker module520may determine the priority of a plurality of first commands based on the priority of the second signal and the requester.

The CXL device500may schedule a plurality of first commands output by a plurality of processes of the host400and a plurality of second commands output by the accelerator530based on the first signal, the second signal, and the third signal. The CXL device500may control memory operations based on scheduled commands.

Referring toFIG.5, the CXL device500according to an embodiment may include the request register510, the checker module520, an accelerator530, a command generator540, a memory controller550, and a memory560.

The request register510may store requester IDs of a plurality of requesters (or a plurality of processes) using the host400and priorities corresponding to the requester IDs. The host400may record a plurality of requester IDs and priorities in the request register510using the CXL.io protocol. A plurality of requesters may have different priorities. For example, the plurality of requesters may use the host400with different SLAs. The host400may determine priorities of the plurality of requesters based on the SLA. The host400may determine a high priority for a requester with a relatively short SLA and a low priority for a requester with a relatively long SLA. In some embodiments, the host400may record, in the request register510, only the requester ID of the requester to be processed with priority.

Upon receiving the first signal from the host400, the request register510may transmit the priority of the requester corresponding to the requester identifier included in the first signal to the checker module520.

The checker module520may receive the priority of the requester from the request register510. The checker module520may receive a second signal including a first command, an address, and a metadata field from the host400. The checker module520may receive a third signal including a second command, an address, and a metadata field from the accelerator530. The metadata field may include information indicating a request type. The request type may include an emergency request and a normal request. For example, the host400and the accelerator530may indicate an emergency to the checker module520by filling different values in the metadata field. For example, in a 2-bit metadata field, “10” may indicate an emergency request, and “01” may indicate a normal request. However, it should be understood that the 2-bit metadata field of the present disclosure is not limited thereto and other representations may be employed.

The checker module520may determine priorities of the plurality of commands output by the host400and the accelerator530according to a processing policy. For example, the processing policy may include a requester's priority, a request type, and the like.

The checker module520may determine the priorities of the plurality of commands based on the priority of the requester and the request type (or a value of the metadata field). For example, the checker module520may determine the priorities of the plurality of commands as shown in Table 2. In Table 2, the lower the priority number of the command, the higher priority processing may be indicated. That is, the lower the number, the higher the priority.

TABLE 2COMMANDREQUESTERPRIORITYPRIORITYREQUEST TYPEFROM1HIGHEMERGENCYHOST2LOWEMERGENCYHOST3—EMERGENCYACCELERATOR4HIGHNORMALHOST5LOWNORMALHOST5—NORMALACCELERATOR

Referring to Table 2, the checker module520may determine the priority of a command with an emergency request type higher than that of a command with a normal request type. The checker module520may determine the priority of a command having a high requester priority higher than that of a command having a low requester priority.

When determining the priority of a plurality of commands, the checker module520may primarily consider the request type, secondarily consider the priority of the requester, and thirdly consider a command source. That is, the checker module320may first determine the priority of a command with an emergency request type higher than that of a command with a normal request type. Subsequently, the checker module320may determine a higher priority of a command having a higher requester priority than a command having a lower requester priority with respect to commands having the same request type. The checker module520may determine a higher priority of a command of the host400than a command of the accelerator530among commands having an emergency request type. In addition, the checker module520may determine the priority of the command of the accelerator530and the priority of the command of the host400having a low requester priority among commands of a general request type are equal.

That is, the checker module520may determine the priority of a command from the host400with an emergency request type and a high requester priority as “1”, the priority of a command from the host400with an emergency request type and a low requester priority as “2”, the priority of a command from the accelerator530with an emergency request type and a high requester priority as “3”, the priority of a command from the host400with a normal request type and a high requester priority as “4”, and the priority of the command of the accelerator530, which is the priority of a command from the host400with a normal request type and a low requester priority, as “5”. Since the command from the host300with a normal request type and a low requester priority and the command from the accelerator530with a normal request type have the same priority, the CXL device500may process commands with the same command priority in chronological order.

In the present embodiment, it has been described that the checker module520primarily considers the request type and secondarily considers the priority of the requester, but is not necessarily limited thereto, and the checker module520may be implemented to primarily consider the priority of the requester and secondarily consider the request type in other embodiments.

In an embodiment, when the host400records only the ID of the requester to be processed with priority in the request register510, the priority of the requester in Table 2 can be classified as YES or NO. In this case, yes/no may respectively correspond to the above-described high/low classifications.

The checker module520may transmit the plurality of commands, a plurality of addresses, and priorities of the plurality of commands to the command generator540.

The command generator540may generate internal commands based on the plurality of commands, the plurality of addresses, and the priorities of the plurality of commands. The internal commands may include information indicating a command type, address, and priority. The command generator540may transmit the internal commands to the memory controller550. In some embodiments, the command generator540may be implemented such that it is disposed within the memory controller550.

The memory controller550may create a command queue by scheduling a plurality of internal commands. The memory controller550may perform scheduling according to the priority of the command. For example, the memory controller550may include a heuristic scheduler that processes commands according to priorities. The memory controller550may generate a command queue using the heuristic scheduler. In an embodiment, the memory controller550may dispose high priority internal commands to the right of the command queue. The memory controller550may dispose an internal command having a low priority to the left side of the command queue. In this case, the memory controller550may sequentially transmit internal commands to the memory560from the right side based on the command queue.

The memory560may operate based on the internal commands. Internal commands for urgent processes are disposed on the right side of the command queue and transmitted to the memory560first, and thus the memory560can process urgent processes first. That is, while a conventional CXL device does not process an urgent process in one embodiment, the CXL device500has an advantage of processing an urgent process with priority.

FIG.6is a flowchart of a scheduling method according to an embodiment.

Referring toFIG.6, a scheduling method according to an embodiment may be performed by a CXL device. The CXL device may schedule a command using the scheduling method according to an embodiment and operate a memory according to the scheduling method. For example, the CXL device may receive a command from at least one of a host and an accelerator, and schedule the command according to a priority.

The CXL device may receive a requester identifier (ID) from the host using a first protocol (S610). The first protocol may be a CXL.io protocol. The host is used by at least one requester, and the at least one requester may execute at least one process using the host. At least one process may transmit a signal including information such as a command, an address, and a requester identifier to the CXL device.

The CXL device may determine a first priority corresponding to the requester identifier based on the predetermined priority of the requester (S620). The CXL device may include a request register that stores predetermined requester priorities. In an embodiment, the request register may store priorities among a plurality of requesters as a number. In an embodiment, the request register may classify and store priorities of a plurality of requesters as high or low. In an embodiment, a request register may classify and store a requester to be processed with priority among a plurality of requesters as having priority or not having priority. The request register may output the first priority corresponding to the requester identifier in the predetermined priority of the requester.

The CXL device may receive a signal including a command and request type from the host using a second protocol that is different from the first protocol (S630). The second protocol may be a CXL.mem protocol. The command may include an activate command, a read/write command, a precharge command, a refresh command, and the like. The request type may include an emergency request and a normal request. A signal received using the second protocol includes a metadata field, and emergency requests and normal requests may be distinguished by different values in the metadata field. The signal received using the second protocol may further include an address corresponding to a command.

The CXL device may determine a second priority of the command based on the first priority and the request type (S640). The CXL device may determine the second priority primarily based on the request type. The CXL device may determine a second priority of a command whose request type is an emergency request higher than a second priority of a command whose request type is a normal request. When the request type is the same, the CXL device may determine the second priority based on the first priority. For example, the CXL device may determine the second priority of each of the first command and the second command. The request type of the first command may be an emergency request and the first priority may be high, and the request type of the second command may be an emergency request and the second priority may be low. The CXL device may determine the second priority of the first command higher than the second priority of the second command. Even when the request type of the first command and the second command are normal requests, the above description may be similarly applied.

The CXL device may generate an internal command from the command (S650). A CXL device may create a command queue where internal commands are disposed. A command queue may refer to a queue of internal commands. In an embodiment, the CXL device may dispose an internal command with a second higher priority on the right side, and an internal command with a lower second priority on the left side. The CXL device may dispose internal commands with the same second priority in the order of received time from the right. The CXL device may schedule internal commands based on the second priority and transmit them to a memory.

FIG.7is a flowchart of a scheduling method according to an embodiment.

Referring toFIG.7, a CXL device according to an embodiment may receive a signal including a command and request type from an accelerator (S635). To distinguish a command received from the accelerator by the CXL device from a command received from the host, the command from the accelerator may be expressed as an accelerator command COMMAND_ACC.

In an embodiment, the CXL device may receive a first command and a second command from the host and receive a third command from the accelerator. The CXL device may determine second priorities of the first to third commands. For example, the CXL device may determine the second priority of commands, and the second priority of third commands based on the second priority of the first command, the request type of the first command, the first priority of the first command, the request type of the second command, the first priority of the second command, and the request type of the third command.

When the request type of the first command and the request type of the second command are the same, the CXL device may determine the second priority of the first command and the second priority of the second command based on the first priority of the first command and the first priority of the second command.

The CXL device may determine the second priority of a command whose request type is an emergency request higher than the second priority of a command whose request type is a normal request.

When the request type of the first command and the request type of the third command are emergency requests, the CXL device may determine the second priority of the first command to be higher than the second priority of the third command.

When the request type of the first command and the request type of the third command are normal requests and the first priority of the first command is high, the CXL device may determine the second priority of the first command to be higher than the second priority of the third command.

The CXL device may determine the second priority of the first command and the second priority of the third command are equal when the request type of the first command and the request type of the third command are normal requests and the first priority of the first command is low. The CXL device may sequentially process the received first command and third command with the same second priority.

FIG.8is a block diagram of a computer system according to another embodiment.

Referring toFIG.8, a computer system1000may include a first CPU1010a, a second CPU1010b, a GPU1030, an NPU1040, a CXL switch1015, a CXL memory1050, a CXL storage1052, a PCIe device1054, and an accelerator (CXL device)1056.

The first CPU1010a, the second CPU1010b, the GPU1030, the NPU1040, the CXL memory1050, the CXL storage1052, the PCIe device1054, and the accelerator1056may be commonly connected to a CXL switch1015, and each of these components may communicate with each other through the CXL switch1015.

In an embodiment, the first CPU1010a, the second CPU1010b, the GPU1030, and the NPU1040may be implemented by the host described with reference toFIG.1toFIG.7(e.g., the host110, the host200, or the host400), and each of these components may be directly connected to individual memories1020a,1020b,1020c,1020d, and1020e.

In an embodiment, the CXL memory1050and the CXL storage1052may be implemented by the CXL device described with reference toFIG.1toFIG.7(e.g., the CXL device150-1to150-n, the CXL device300, or the CXL device500), and at least some regions of memories1060aand1060bof the CXL memory1050and the CXL storage1052, respectively, may be allocated to a cache buffer of at least one of the first CPU1010a, the second CPU1010b, the GPU1030, the NPU1040, the CXL memory1050, the CXL storage1052, the PCIe device1054, and the accelerator1056by any one or more of the first CPU1010a, the second CPU1010b, the GPU1030, and the NPU1040.

In an embodiment, the CXL switch1015may be connected to the PCIe device1054or the accelerator1056formed to support various functions, and the PCIe device1054or the accelerator1056may communicate with the first CPU1010a, the second CPU1010b, the GPU1030, and the NPU1040or access the CXL memory1050and the CXL storage1052through the CXL switch1015.

In an embodiment, the CXL switch1015may be connected to an external network1060or fabric and may be configured to communicate with an external server through the external network1060or fabric.

FIG.9is a block diagram of a server system according to an embodiment.

Referring toFIG.9, a data center1100is a facility that collects various data and provides services, and may be referred to as a data storage center. The data center1100may be a system for operating a search engine and a database, and may be a computer system used by companies, such as banks or government agencies. The data center1100may include application servers1110ato1110hand storage servers1120ato1120h. The number of application servers and the number of storage servers may be selected according to various embodiments, and the number of application servers and the number of storage servers may be different than each other.

Hereinafter, the configuration of the first storage server1120awill be mainly described. Each of the application servers1110ato1110hand the storage servers may have a similar structure, and the application servers1110ato1110hmay communicate with each other through a network NT.

The first storage server1120amay include a processor1121, a memory1122, a switch1123, a storage device1125, a CXL memory1124, and a network interface card (NIC)1126. The processor1121may control the overall operation of the first storage server1120a, access the memory1122, execute instruction commands loaded in the memory1122, and/or process data. The processor1121and the memory1122may be directly connected, and the number of processors1121and memories1122included in one storage server1120amay vary.

In an embodiment, the processor1121and the memory1122may provide a processor-memory pair. In an embodiment, the number of processors1121and the number of memories1122may be different. The processor1121may include a single core processor or a multi-core processor. The above description of the storage server1120may be similarly applied to each of the application servers1110ato1110h.

The switch1123may be configured to mediate or route communication between various configurations elements included in the first storage server1120a. In an embodiment, the switch1123may be the CXL switch described with reference toFIG.8(e.g., the CXL switch1015). That is, the switch1123may be a switch implemented based on the CXL protocol.

The CXL memory1124and the storage device1125may be the CXL device described with reference toFIG.1toFIG.8(e.g., the CXL memory1050and the CXL storage1052, respectively).

The CXL memory1124may be connected to the switch1123. The storage device1125may include a CXL interface circuit (CXL_IF1125a), a controller (CTRL1125b), and a NAND flash (NAND1125c). The storage device1125may store data or output stored data according to a request of the processor1121.

The application servers1110ato1110hmay not include the storage device1125.

The NIC1126may be connected to the switch1123. The NIC1126may communicate with other storage servers1120ato1120hor other application servers1110ato1110hthrough the network NT.

In an embodiment, the NIC1126may include a network interface card, a network adapter, and the like. The NIC1126may be connected to the network NT through a wired interface, wireless interface, Bluetooth interface, optical interface, or the like. The NIC1126may include an internal memory, a digital signal processor (DSP), a host bus interface, and the like, and may be connected to the processor1121and/or the switch1123through the host bus interface. In an embodiment, the NIC1126may be integrated with at least one of the processor1121, the switch1123, and the storage device1125.

In an embodiment, the network NT may be implemented using Fiber Channel (FC) or Ethernet. In this case, the FC is a medium used for relatively high-speed data transmission, and an optical switch providing high performance/high availability can be used. Depending on an access method of the network (NT), storage servers may be provided as a file storage, a block storage, or an object storage.

In an embodiment, the network NT may be a storage-only network, such as a storage area network (SAN). For example, the SAN may be an FC-SAN using an FC network and implemented according to the FC Protocol (FCP). As another example, the SAN may be an IP-SAN using a TCP/IP network and implemented according to an SCSI over TCP/IP or Internet SCSI (iSCSI) protocol. In an embodiment, the network NT may be a general network, such as a TCP/IP network. For example, the network NT may be implemented according to protocols such as FC over Ethernet (FCoE), Network Attached Storage (NAS), and NVMe over Fabrics (NVMe-oF).

In an embodiment, at least one of the application servers1110ato1110hmay store data requested by a user or client in one of the storage servers1120ato1120hthrough the network NT. At least one of the application servers1110ato1110hmay acquire data requested by a user or client to read from one of the storage servers1120ato1120hthrough the network NT. For example, at least one of the application servers1110ato1110hmay be implemented as a web server or a database management system (DBMS).

In an embodiment, at least one of the application servers1110ato1110hmay access a memory, a CXL memory, or a storage device contained in another application server through the network NT, or may access memories included in the storage servers1120ato1120h, CXL memories, or storage devices through the network NT. Thus, at least one of the application servers1110ato1110hmay perform various operations on data stored in other application servers and/or storage servers. For example, at least one of the application servers1110ato1110hmay execute instruction commands for moving or copying data between other application servers and/or storage servers. In this case, data may be moved from the storage devices of storage servers through memories of storage servers or CXL memories, or directly to memories of application servers or CXL memories. Data moving through the network may be encrypted data for security or privacy.

In some embodiments, the combination of constituent elements of each constituent element or two or more described with reference toFIG.1toFIG.9may be implemented as a digital circuit, a programmable or unprogrammable logic device or array, an application specific integrated circuit (ASIC), and the like.

While this disclosure has been described in connection with what is presently considered to be practical embodiments, it is to be understood that the disclosure is not limited to the disclosed embodiments. That is, the present disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.