Patent ID: 12232254

DETAILED DESCRIPTION

In order to describe in detail the technical content, structural features, achieved objectives and effects of the instant application, the following detailed descriptions are given in conjunction with the drawings and specific embodiments. It should be understood that these embodiments are only used to illustrate the application and not to limit the scope of the instant application.

FromFIG.1AtoFIG.1G, which illustrates a first embodiment of a method for manufacturing a printed circuit board of the present disclosure. As shown inFIG.1A, a first substrate1is provided, and the first substrate1has a first surface10and a second surface12, and the first surface10and the second surface12are corresponding to each other along a Y-axis. As aforesaid, the first surface10and the second surface12being corresponding to each other along the Y-axis means the first surface10and the second surface12being not the same height on the Y-axis, and the directions of the first surface10and the second surface12being opposite to each other. In this embodiment, the first substrate1is, for example, a polypropylene substrate. However, in other embodiments, the first substrate1can be a polyimide substrate, a polymethyl methacrylate substrate, a glass substrate, a ceramic substrate, or an insulating silicon substrate as well.

Referring toFIG.1B, the first surface10and the second surface12of the first substrate1form a first circuit layer2respectively. For the embodiment, the material of the first circuit layer2is copper, but in other embodiments, the material of the first circuit layer2can also be other conductive materials, such as aluminum. In addition, the first circuit layer2only forms either on the first surface10or the second surface12for other embodiments.

According toFIG.1C, an etching process, such as wet etching, is applied to the first circuit layer2, so as to form a plurality of first traces20. After the etching process, a first gap22is formed via etching and beside the first trace20. The dimensions or width of the first gap22is tapered toward the substrate1, and the first gap22exposes the surfaces, the first surface10and the second surface12, of the first substrate1. For the embodiment, an etching factor of the first trace20is greater than or equal to 2.3. That is, the etching factor of a wall of the first gap22is greater than or equal to 2.3. The definition of the etching factor of the present disclosure is 2*an etched thickness/(the lower width of an etched layer—the upper width of the etched layer). For instance, The definition of the etching factor of the first trace20is 2*the thickness of the first trace20/(the lower width of the first trace20—the upper width of the first trace20). More, the etching factor is also defined as that of the thickness of an etched layer/the undercut of a wall.

With reference toFIG.1DandFIG.1E, at least one second circuit layer3is provided and stacked on the first circuit layer2with the plurality of first traces20. As shown inFIG.1D, the directions of the two arrows are the directions of stacking the second circuit layers3. In the embodiment, the second circuit layers3is a metal plate with the material of copper. Before stacking the second circuit layer3on the first circuit layer2, both the surfaces of the second circuit layer3and the first circuit layer2are treated by a planarization technique, which is a chemical mechanical polishing technique.

According toFIG.1E, a low-temperature Cu—Cu direct bonding technique is applied to a connection of the first trace20and the second trace30. For the low-temperature Cu—Cu direct bonding technique, please refer to the following information. Chien-Min Liu, Han-Wen Lin, Yi-Sa Huang, Yi-Cheng Chu, Chih Chen, Dian-Rong Lyu, Kuan-Neng Chen & King-Ning Tu. (2015). Low-temperature direct copper-to-copper bonding enabled by creep on (111) surfaces ofnanotwinned Cu. Scientific Reports, 5:09734. doi: 10.1038/srep09734.

The lowest temperature of Cu—Cu direct bonding is 150° C., and the spending time is 1 hour. If the temperature is up to 250° C., the spending time is 10 minutes. In the field of printed circuit board, the working temperature is generally less than 200° C. Accordingly, the range of the working temperature is between 190° C. and 200° C. for the embodiment.

As forFIG.1F, an etching process is applied to the second circuit layer3in order to form a plurality of second traces30. After the etching process, a plurality of second gaps32are beside the second traces30and formed by etching. For the embodiment, the second gap32penetrates through the second circuit layer3, and the first gap22and the second gap32are through to each other. Further, the dimensions or width of the second gaps32is tapered from a side that is far from the first gap22to another side that is close to the first gap22. An etching factor of the second trace30is greater than or equal to 2.3. That is, the etching factor of a wall of the second gap32is greater than and equal to 2.3. Since the etching factors of the first trace20and the second trace30are greater than or equal to 2.3, the etching factor of a stacked trace40, connecting the first trace20and the second trace30along the Y-axis, is greater than or equal to 4.6. Besides, in the embodiment or other embodiments, the first gap22and the second gap32can be a hole or a line spacing among the traces.

It is to be noted that the steps fromFIG.1DtoFIG.1Fmay be repeated, so as to produce stacked traces40with higher etching factors. For example, the second trace30can be stacked one more conductive layer, then etching it in order to gain a new stacked trace40with higher etching factor.

As shown inFIG.1G, the first gaps22and the second gaps32are filled with a dielectric material4, which can be resin, epoxy resin, solder mask or other adhesive materials. The dielectric material4is beneficial to avoid shorts among stacked traces40or isolation breaking. In the embodiment, after filling out the dielectric material4, a surface treatment process is applied to two outer surface of the dielectric material4and the stacked trace40, precisely in the second circuit layer3. The surface treatment process is to coat a surface protection layer7and a solder mask ink8, wherein the surface protection layer7is on the stacked trace40, the solder mask ink8is on the dielectric material4and covers partial surface of the stacked trace40. The surface protection layer7is to protect the stacked trace40and can be the materials of ENEPIG, organic solderability preservatives (OSP), or Electroless Nickel Immersion Gold (ENIG), but not limit thereto.

According to aforesaid, the printed circuit board100is completely produced, and the trace (the stacked trace40) of the printed circuit board100is with a higher etching factor. In the manufacturing processes of the printed circuit board100, the etching process is applied to every conductive layer, such as the first circuit layer2and the second circuit layer3, so as to gain the printed circuit board100with the traces of a higher etching factor.

Following will be the descriptions for the second embodiment of the method for manufacturing the printed circuit board, please refer toFIG.2AtoFIG.2F. In the second embodiment, the same or similar components as those of the first embodiment will be designated with the same reference numerals. According toFIG.2A, a first substrate1is provided, and the first substrate1has a first surface10and a second surface12, and the first surface10and the second surface12are corresponding to each other along a Y-axis. Referring toFIG.2B, a first circuit layer2is formed on the first surface10and the second surface12of the first substrate1respectively. Please refer toFIG.2C, an etching process is applied to the first circuit layer2in order to form a plurality of first traces20. After the etching process, a first gap22is formed by etching and beside the first trace20, and the first gap22exposes the surfaces (the first surface10and the second surface12) of the first substrate1. For the embodiment, an etching factor of the first trace20is greater than or equal to 2.3. That is, the etching factor of a wall of the first gap22is greater than or equal to 2.3. The first circuit layer2with the plurality of first traces20is treated by a planarization technique, which is a chemical mechanical polishing technique for the embodiment. Continuously referring toFIG.2D, the first gap22is filled with a dielectric material4a.

With reference toFIG.2E, a second substrate6is provided, and a second circuit layer3is formed on two surfaces of the second substrate6respectively, wherein the two surfaces are corresponding to each other. In addition, the second circuit layer3has a plurality of second traces30formed by etching, and a second gap32is beside the second trace30and made by etching, wherein an etching factor of the second trace30is greater than or equal to 2.3. The second gap32is filled with a dielectric material4b. For the embodiment, the method for forming the second trace30, the second gap32and the dielectric material4bon the second substrate6is the same as the method for forming the first trace20, the first gap22and the dielectric material4aon the first substrate1. Therefore, the descriptions for forming the second trace30, the second gap32and the dielectric material4bmay not be discussed any further hereinafter.

Referring toFIG.2E, the second trace30on one of the two surfaces of the second substrate6is connected with the first trace20on one of the two surfaces of the first substrate1along the Y-axis. The first gap22and the second gap32are corresponding to each other while in connection. That is to say, the first gap22and the second gap32are through to each other along the Y-axis after connection, as shown inFIG.2F. Further, the first trace20and the second trace30are corresponding to each other as well. There is one thing that must be noted, a planarization technique is applied to the surface of the second trace30, and the planarization technique is a chemical mechanical polishing technique. As for the present embodiment, a low-temperature Cu—Cu direct bonding technique is applied to the connection of the first trace20and the second trace30.

In accordance withFIG.2F, the second trace30is combined with the first trace20to form a stacked trace40. Since the etching factors of the first trace20and the second trace30both are greater than or equal to 2.3, the etching factor of the stacked trace40, connecting the first trace20and the second trace30along the Y-axis, is greater than or equal to 4.6 as well. After producing the stacked trace40, an outer surface of the second trace30of another outer surface of the second substrate6and an outer surface of the first trace20of another outer surface of the first substrate1can also be applied by a surface treatment process. For the embodiment, the surface treatment process is to add a surface protection layer7and a solder mask ink8, wherein the surface protection layer7is on the first trace20and the second trace30, in order to protect them. The solder mask ink8is disposed on the dielectric material4aand the dielectric material4b, wherein the solder mask ink8covers the partial first trace20and the partial second trace30.

According to aforesaid, the printed circuit board200is completely produced, and the trace (the stacked trace40) of the printed circuit board200is with a higher etching factor. Compared with the first embodiment, the second embodiment adopts that of etching the second circuit layer3first and then combining the second circuit layer3with the first circuit layer2. Since the two conductive layers (the first circuit layer2and the second circuit layer3) are etched individually, the printed circuit board200with the traces of a higher etching factor is obtained.

Following will be the descriptions for the third embodiment of the method for manufacturing the printed circuit board, please refer toFIG.3AtoFIG.3H. In the third embodiment, the same or similar components as those of the second embodiment will be designated with the same reference numerals. According toFIG.3A, a first substrate1is provided, and the first substrate1has a first surface10and a second surface12, and the first surface10and the second surface12are corresponding to each other along a Y-axis. Referring toFIG.3B, a first circuit layer2is formed on the first surface10and the second surface12of the first substrate1respectively. Please refer toFIG.3C, an etching process is applied to the first circuit layer2in order to form a plurality of first traces20. After the etching process, a first gap22is formed by etching and beside the first trace20, and the first gap22exposes the surfaces (the first surface10and the second surface12) of the first substrate1. For the third embodiment, an etching factor of the first trace20is greater than or equal to 2.3. That is, the etching factor of a wall of the first gap22is greater than or equal to 2.3. Continuously referring toFIG.3D, the first gap22is filled with a dielectric material4a.

On the basis ofFIG.3E, an adhesive layer9is coated on the dielectric material4aon the first surface10. The material of the adhesive layer9is mainly resin, epoxy resin or other non-conductive adhesive materials. According toFIG.3F, a conductive glue5is coated on the first trace20of the first surface10, wherein the conductive glue5is, for example, Cu paste. In this embodiment, the conductive adhesive5can be coated on the first trace20by printing.

Referring toFIG.3G, a second substrate6is provided, and a second circuit layer3is formed on two surfaces of the second substrate6respectively, wherein the two surfaces are corresponding to each other. In addition, the second circuit layer3has a plurality of second traces30formed by etching, and a second gap32is beside the second trace30and made by etching, wherein an etching factor of the second trace30is greater than or equal to 2.3. The second gap32is filled with a dielectric material4b. For the embodiment, the method for forming the second trace30, the second gap32and the dielectric material4bon the second substrate6is the same as the method for forming the first trace20, the first gap22and the dielectric material4aon the first substrate1. Therefore, the descriptions for forming the second trace30, the second gap32and the dielectric material4bmay not be discussed any further hereinafter.

With reference toFIG.3G, the second trace30on one of the two surfaces of the second substrate6and the first trace20on one of the two surfaces of the first substrate1are jointed along an X-axis by means of the adhesive layer9and the conductive glue5. The first gap22and the second gap32are corresponding to each other while in combination, and so do the first trace20and the second trace30, wherein the combination for the second trace30and the first trace20is executed under a certain temperature, in order to cure the adhesive layer9and the conductive glue5.

Referring toFIG.3H, to combine the second trace30, the conductive glue5and the first trace20is to form a stacked trace40. Since the etching factors of the first trace20and the second trace30both are greater than or equal to 2.3, the etching factor of the stacked trace40, combining the first trace20with the second trace30along the X-axis, is greater than or equal to 4.6 as well. After producing the stacked trace40, an outer surface of the second trace30of another outer surface of the second substrate6and an outer surface of the first trace20of another outer surface of the first substrate1can also be applied by a surface treatment process. For the embodiment, the surface treatment process is to add a surface protection layer7and a solder mask ink8.

According to aforesaid, the printed circuit board300is completely produced, and the trace (the stacked trace40) of the printed circuit board300is with a higher etching factor. Compared with the second embodiment, the third embodiment adopts the conductive glue5to combine the second circuit layer3with the first circuit layer2, but not the low-temperature Cu—Cu direct bonding technique. More, a planarization technique as chemical mechanical polishing technique may not be necessary to the third embodiment. Since the two conductive layers (the first circuit layer2and the second circuit layer3) are etched individually in the third embodiment, the printed circuit board300with the traces of a higher etching factor is obtained.

As above embodiment, both the first surface10and the second surface12of the first substrate1are disposed the first conductive layer2respectively. On the other hand, only one surface (the first surface10or the second surface12) disposed the first conductive layer2is another option.

Please refer toFIG.4, which illustrate a schematic view of a fourth embodiment of the printed circuit board of the present disclosure. In the embodiment, the printed circuit board400includes a first substrate1, a first circuit layer2and a second circuit layer3, wherein the first substrate1includes a first surface10and a second surface20, the first surface10and the second surface20are corresponding to each other along an Y-axis. The first circuit layer2forms on the first surface10of the first substrate1, and has at least one first trace20(multiple for the fourth embodiment). At least one first gap22(multiple for the fourth embodiment) is beside the first trace20and made by etching. Further, an etching factor of the first trace20is greater than or equal to 2.3. Additionally, the second circuit layer3is formed on the first circuit layer2, wherein the second circuit layer3has at least one second trace30(multiple for the fourth embodiment), the second trace30has at least one second gap32(multiple for the fourth embodiment), and an etching factor of the second trace30is greater than or equal to 2.3. More, the first gap22and the second gap32are through to each other along the Y-axis, and the first gap22and the second gap32are filled with the dielectric material4. Further, the first trace20and the second trace30are combined with each other along the Y-axis, so as to form a stacked trace40, wherein an etching factor of the stacked trace40is greater than or equal to 4.6. In addition, a surface protection layer7and a solder mask ink8form on an outer surface of the dielectric material4and the stacked trace40. The surface protection layer7is disposed on the stacked trace40, and the solder mask ink8is disposed on the dielectric material4, especially the solder mask ink8covers the partial stacked trace40. The method for manufacturing the printed circuit board400is almost the same as the method for manufacturing the printed circuit board100, as shown fromFIG.1AtoFIG.1G. The main difference is as follows: there is no need to produce any component on the second surface12while manufacturing the printed circuit board400. However, the method for manufacturing the printed circuit board400may not be discussed any further hereinafter.

As a conclusion, while manufacturing the printed circuit boards of the present disclosure, since the conductive layers are etched individually, the printed circuit board with the traces of a higher etching factor is then obtained. For those embodiments as aforesaid, the first gap22and the second gap32both are filled with the dielectric material4, in order to increase the insulation among the stacked conductors40; on the other hand, a person having ordinary skill in the art may have other options that the first gap22and the second gap are not filled with the dielectric material4, but somewhere else.

Although the disclosure has been disclosed and illustrated with reference to particular embodiments, the principles involved are susceptible for use in numerous other embodiments that will be apparent to a person having ordinary skill in the art. This disclosure is, therefore, to be limited only as indicated by the scope of the appended claims.