Patent ID: 12237772

Like reference numbers and designations in the various drawings indicate like elements unless stated otherwise.

DETAILED DESCRIPTION

The present invention encompasses circuits and methods for providing a “bootstrap” power supply for level-shifter/driver (LS/D) circuits in a FET-based power converter.

Linear Regulator Embodiment

FIG.3Ais a block diagram of one embodiment of a FET-based buck power converter300utilizing linear regulators and bootstrap capacitors provide a bootstrap power supply for level-shifter/driver circuits (note that reference numbers have not been applied to all similar components of the power converter300to avoid clutter). The buck power converter300is a 5-level converter that steps a higher positive input voltage down to a lower voltage and is particularly efficient as compared to a standard 2-level topology when the voltage step-down ratio is large and there is an inductor size constraint such that the inductor has the dominant power loss. In addition, the power FETs are not required to be rated for at least VIN, but instead can be rated for VIN/4.

In the example illustrated inFIG.3A, the two sets of series-connected power switches, Sw1-Sw4and Sw5-Sw8ofFIG.2are implemented by a set of power FETs Mn (in this example, n=1 . . . 8). The control gate of each power FET Mn is coupled to a corresponding level-shifter/driver (LS/D) circuit302. A clock signal φncoupled as an input to each LS/D circuit302controls the ON or OFF state of the corresponding power FET Mn. The clock signals may be generated by, for example, the controller108shown inFIG.1.

Power to each LS/D circuit302is provided by charge stored on a corresponding bootstrap capacitor Cn (in this example, n=1 . . . 8) coupled to target (shifted) voltage inputs of the LS/D circuit302, as described in detail below with respect toFIG.3B. Each bootstrap capacitor Cn should be sized to provide at least sufficient charge, with minimal voltage drop, to allow the LS/D circuit302to switch the state of a coupled power FET Mn, the control gates of which are relatively large capacitive structures.

The charge on each bootstrap capacitor C1-C7is replenished during startup and operation from a corresponding parallel-connected linear regulator304. In the illustrated embodiment, a linear regulator is omitted for the bottom bootstrap capacitor C8and corresponding power FET M8, since the bootstrap capacitor C8can simply be coupled between a supply voltage VDD(e.g., 3.3V) and circuit ground. However, in some embodiments, it may be useful to provide a linear regulator304for all bootstrap capacitors. Each power FET M1-M8and the associated driving circuitry and linear regulator circuitry can be considered as “tier” of the power converter300.

FIG.3Bis a more detailed block diagram350of one embodiment of a linear regulator304coupled to a bootstrap capacitor Cn and a corresponding LS/D circuit302for a power FET Mn. The linear regulator304is shown coupled, via an input TOP, to a charge pump306that provides a boosted input voltage of VIN+VDDgenerated from input voltages VDD(e.g., 3.3V from a controller108, as shown inFIG.1) and VIN(i.e., the voltage applied to the input of the power converter300, such as 3.3V to 14.4V). The boosted voltage VIN+VDDis needed to charge the coupled bootstrap capacitors Cn. The linear regulator304is also coupled, via an input IN, to VINas a reference voltage; thus, the difference in the two input voltages to the linear regulator304is VDD(=VIN+VDDminus VIN). This difference is used to regulate the voltage on each capacitor Cn to have the same voltage difference but referenced to a lower voltage than VIN. Alternatively, if the linear regulator304has its own internally generated reference voltage, it then would only need one voltage input, namely VIN+VDD, to generator Cn voltages. For each coupled bootstrap capacitor Cn and LS/D circuit302, the linear regulator304provides a suitable Relative Supply Voltage. The linear regulator304, the bootstrap capacitor Cn, and the LS/D circuit302are also coupled to a Relative Reference Voltage defined by the voltage at the source of the corresponding power FET Mn.

Within the LS/D circuit302, a level shifter310receives a corresponding input IN (e.g., a clock signal φn, as shown inFIG.3A, that controls the ON or OFF state of the corresponding power FET Mn) and converts that input into a level-shifted output OUTP. In the illustrated example, the input signal is a voltage within an input voltage range from VDDto circuit ground, which are respectively applied to the level shifter310at terminals VDD1and Gnd1. The shifted voltage range varies between the Relative Supply Voltage provided by the corresponding linear regulator304and the Relative Reference Voltage, which are respectively applied to the level shifter310at terminals VDD2and Gnd2(which may also be called “target voltage” terminals).

The Relative Supply Voltage and the Relative Reference Voltage are also coupled to a driver circuit312within the LS/D circuit302at terminals VDD3and Gnd3. An input IN to the driver circuit312receives the level-shifted output OUTP from the level shifter310and provides a suitable drive voltage to the control gate of a coupled power FET Mn, in known fashion (note that the drive voltage may be provided through other components, not shown, such as a gate resistor or resistor network).

The linear regulator304for each corresponding bootstrap capacitor Cn is set to provide a suitable Relative Supply Voltage to charge the bootstrap capacitor Cn (see the arrow inFIG.3Bindicating charging flow) to a voltage level that provides an adequate, stable source of power and charge to the LS/D circuit302. For example, the drain of power FET M1is at VIN, which may, for example, range from about 3.3V to about 14.4V in some applications. The required Relative Supply Voltage required to switch that power FET OFF may be about VIN+ΔV, and to switch that power FET ON may be about Vsource+ΔV, where ΔV is dependent on the type of transistor used for power FET M1; for a commonly used N-type FET, ΔV may be about 3.3V. Accordingly, the linear regulator304corresponding to power FET M1should be configured to charge the corresponding bootstrap capacitor C1to 3.3V in the illustrated example. Similarly, the linear regulators304corresponding to power FETs M2-M7should be configured to charge the corresponding bootstrap capacitors C2-C7to the required Relative Supply Voltage required to switch those power FETs.

In the embodiment shown inFIGS.3A and3B, the top node (plate) of each bootstrap capacitor Cn is constantly charged by the output voltage VIN+VDDfrom the charge pump306with the same average current, since the charge needed to replenish the bootstrap capacitors is fixed. The voltage delta from the top-most bootstrap capacitor C1to the bottom-most bootstrap capacitor C8varies depending on the ON/OFF state of the power FETs Mn, but in general, there is less voltage drop for the upper bootstrap capacitors and the voltage drop increases for each successive bootstrap capacitor going lower. The power loss per linear regulator304would be V×I (totaling 8×V×I in the example shown inFIG.3A), where V is the voltage drop between VIN+VDDand the top node of each bootstrap capacitor. This voltage drop can be quite large, leading to appreciable loss. For example, for VIN=5V and VDD=3.3V, the voltage delta between VIN+VDDand the top node of bootstrap capacitor C7can be as high as 5V. Thus, taking into account the average voltage drop across a power FET Mn (which typically can be a few tenths of a volt across a power FET Mn having an RONof around 10 ohms), the embodiment shown inFIG.3Amay not be preferred for applications where power savings is an important design criteria.

FIG.3Cis a more detailed block diagram of one embodiment of a charge pump306. Clock signals P1and P2are complementary and non-overlapping phases, while the /P1and/P2clock signals are inverted versions of P1and P2. PFET M1and NFET M3conduct and block charge flow at the same times, while NFET M2and PFET M4conduct and block charge flow at the same times (but complementary to PFET M1and NFET M3). FETs M1and M2and FETs M4and M3are respectively coupled in series between a voltage source VDDand circuit ground. A cross-coupled set of FET pairs (NFET M5and PFET M6on the left, NFET M8and PFET M7on the right) is coupled between VINand a capacitor COUT, which in turn is coupled to circuit ground. Toggling of the P1and P2clocks signals (and their complementary versions) periodically connects VINthrough FETs M5and M8to the “top” plates of capacitors CAand CB, thus charging those capacitors to VIN, and then periodically connects VDDthrough FETs M1and M4to the “bottom” plates of capacitors CAand CB, thus adding VDDon the fly to VIN. In greater detail, in a first phase, capacitor CAis charged to VINthrough switches M5and M2in closed (ON) states, or capacitor CBis charged to VINthrough switches M8and M3in closed states. In a second phase, capacitor CAis discharged to the output with a voltage of VIN+VDDthrough switches M1and M6in closed states, or capacitor CBis discharged to the output with a voltage of VIN+VDDthrough switches M4and M7in closed states.

FIG.3Dis a more detailed block diagram of one embodiment of a linear regulator304. Connected between an input voltage VIN+VDDand a reference voltage VIN, a diode-connected PFET D1and resistor R1provide a source voltage-dependent bias voltage to PFET M1. PFET M1and diode-connected NFET D2function as a current mirror to a source-follower NFET M2having its gate connected in common with the gate of the diode-connected NFET D2. The source-follower NFET M2is connected between the input voltage VIN+VDDand a bias resistor RBIAS, and resistors R2and RBIASare coupled to a common rail. The source of NFET M2provides a regulated output VOUT+ (e.g., the Relative Supply Voltage ofFIG.3B) and the common rail connecting resistors R2and RBIASprovides a regulated output VOUT− (e.g., the Relative Reference Voltage ofFIG.3B) for an associated tier of the power converter300ofFIG.3A. Accordingly, the current mirror configuration mirrors the current in R1to R2so VR1=VR2if R1=R2. The voltage VR2then gets replicated to VOUT+/VOUT− through the D2/M2pair of devices. An optional stabilizing capacitor CHOLDmay be included in some embodiments, but in other embodiments the associated bootstrap capacitor Cn provides that function (e.g., seeFIG.3B).

FIG.3Eis a more detailed block diagram of one embodiment of a driver circuit312. In the illustrated embodiment, the driver circuit312comprises four series-coupled inverter stages312a-312dof increasing size (and hence driver power). In alternative embodiments, the number of stages may be fewer or greater, and non-inverting stages (buffer amplifiers) may be used rather than inverting stages. Further, the multipliers for the stages may differ from the 1×, 3×, 9×, and 27× ratios shown.

Floating Charge Circuit Embodiment

An improved bootstrap power supply for bootstrap capacitors and level-shifter and driver circuits of a FET-based power converter uses a successive bootstrap capacitor charge transfer technique which can minimize power loss during charge transfer and thereby maximize the efficiency of the power converter.

A. Example Embodiment Circuit Details

FIG.4Ais a block diagram of one embodiment of a FET-based buck power converter400utilizing floating charge circuits and bootstrap capacitors to provide an improved bootstrap power supply for level-shifter and driver circuits (to avoid clutter, note that reference numbers have not been applied to all similar components of the power converter400and the clock signals φnshown inFIG.3Band the controller108shown inFIG.1have been omitted).FIG.4B, described below, shows a magnified view of two tiers ofFIG.4Ain greater detail.

In the example illustrated inFIG.4A, the two sets of series-connected power switches, Sw1-Sw4and Sw5-Sw8ofFIG.2are again implemented by power FETs M1-M8. The control gate of each power FET Mn is coupled to a corresponding driver circuit402. Each driver circuit402is controlled by a corresponding dual-output level-shifter circuit404, described in detail below with respect toFIGS.4C-4E. Power to each driver circuit402and dual-output level-shifter circuit404is provided by charge stored on a corresponding bootstrap capacitor Cn. Each bootstrap capacitor Cn should be sized to provide at least sufficient charge to allow the driver circuit402to switch the state of a coupled power FET Mn.

Each set of circuits comprising a driver circuit402, a dual-output level-shifter circuit404, and a bootstrap capacitor Cn is coupled to a floating charge circuit406. Each FET M1-M8and such associated driving circuitry and charge circuitry can be considered as a “tier” of the power converter400. For example, the first tier of the power converter400includes FET M1and the following labeled components: the driver circuit402, the dual-output level-shifter circuit404, the bootstrap capacitor C1, and the floating charge circuit406.

Each floating charge circuit406has a power input v1and a first reference input g1, and a power output v2and second reference input g2. For the top-most floating charge circuit406, the power input v1is coupled to VIN+VDD(e.g., from a charge pump306such as shown inFIG.3B) and the first reference input g1is coupled to VIN. However, for each lower floating charge circuit406, the power input v1and the first reference input g1are respectively coupled to the power output v2(and thus to the top plate of the corresponding bootstrap capacitor Cn) and the second reference input g2(and thus to the bottom plate of the corresponding bootstrap capacitor Cn) of the next higher floating charge circuit406, in a cascaded architecture. For example,FIG.4Bis a block diagram420showing one example of connecting the floating charge circuit406of a first tier to the floating charge circuit406of a next tier. For the floating charge circuit406associated with power FET M2, the power input v1and the first reference input g1of the floating charge circuit406are respectively coupled to the power output v2(denoted v21) and the second reference input g2(denoted g21) of the floating charge circuit406associated with power FET M1. Accordingly, the floating charge circuit406associated with power FET M2is also coupled to bootstrap capacitor C1. A controller422, which may be separate from or part of the controller108shown inFIG.1, provides respective clock signals φ1-φnto the level shifters404in the set of tiers. In normal operation, the clock signals φ1-φnprovide periodic ON or OFF signals to the level shifters404, and may have a controllable duty cycle. In addition, for some scenarios, such as startup, the controller422may force some or all of the clock signals φ1-φnto specific ON or OFF states for some duration of time or until some event occurs (e.g., the charge across the associated bootstrap capacitors C1-C7has reached some target level).

In preferred embodiments, the floating charge circuits406perform two functions. First, before the power FETs Mn can start switching, the floating charge circuits406provide a circuit path through which the bootstrap capacitors Cn are pre-charged to VMIN, where VMINis the minimum voltage (e.g., about 2V) needed for the gate driver circuits402to work in a particular embodiment (note that in some embodiments, the bottom bootstrap capacitor C8is coupled to VDD, and hence can be charged to VMINfrom that power source). Second, during normal operation, the floating charge circuits406provide a circuit path through which the charge on a bootstrap capacitor Cn is rebalanced when the corresponding power FET Mn turns ON. For example, the charge on bootstrap capacitor C1is rebalanced when power FET M1is ON, the charge on bootstrap capacitor C2is rebalanced when power FET M2is ON, and so forth.

FIG.4Cis a block diagram showing the internal circuitry of one embodiment of a floating charge circuit406. Note that in this figure, components external to the floating charge circuit406are shown connected by dotted lines, indicating externality, not optionality. A first sub-circuit includes a P-type FET MP1coupled in series with a resistor R and controlled by a first level shifter410, which in turn is controlled by a voltage detector412. The resistor R limits the maximum current level that can flow through FET MP1. As should be clear, other components that can limit current may be used in place of, or in conjunction with, the resistor R. A second sub-circuit includes a P-type FET MP2controlled by a second level shifter414, which in turn is controlled by a control signal, VGS_IN, from the level shifter404that is coupled to the driver circuit402that drives the associated power FET Mn (not shown). The output of the driver circuit402is coupled to the control gate of a corresponding power FET Mn (as shown inFIG.4A).

The power input v1of the floating charge circuit406is coupled to the respective sources of the FETs MP1and MP2, to a VDD1terminal of the first level shifter410, and to a VDD3terminal of the second level shifter414. The power output v2of the floating charge circuit406is coupled to the respective drains of the FETs MP1(through the resistor R) and MP2, to a VDD2terminal of the first level shifter410, to a VDD4terminal of the second level shifter414, and to the voltage detector412.

The first reference input g1of the floating charge circuit406is coupled to a Gnd1input of the first level shifter410and to a Gnd3input of the second level shifter414. The second reference input g2of the floating charge circuit406is coupled to a Gnd2input of the first level shifter410, to a Gnd4input of the second level shifter414, and to the voltage detector412.

The corresponding bootstrap capacitor Cn, level shifter404, and driver circuit402are also coupled in parallel with the power output v2and second reference input g2of the floating charge circuit406. The second reference input g2of the floating charge circuit406is also coupled to the source of the corresponding power FET Mn, as shown inFIG.4A.

The first level shifter410and the second level shifter414within the floating charge circuit406are conventional level shifters in which the input is level-shifted at the output. The voltages applied at VDD1and VDD3should be greater than or equal to the respective target voltages VDD2and VDD4. Similarly, voltage at the first reference inputs (Gnd1and Gnd3) should be greater than or equal to the respective voltage at the second reference inputs (Gnd2and Gnd4).

As noted above with respect toFIG.4A, the power input v1and the first reference input g1of each floating charge circuit406(except for the top tier) are also coupled to the bootstrap capacitor of the previous (next higher) tier. For example, if the floating charge circuit406shown inFIG.4Cis coupled across bootstrap capacitor Cn, then the associated power input v1and the first reference input g1are coupled across bootstrap capacitor Cn-1(equivalent to being coupled to the power output v2and second reference input g2of the floating charge circuit406of the immediately upper tier, as shown inFIG.4A). For the top tier, corresponding to power FET M1, the power input v1and the first reference input g1of the floating charge circuit406are respectively coupled to VIN+VDDand to VIN. In some embodiments, in the bottom tier (corresponding to power FET M8in this example), the power output v2and the second reference input g2of the floating charge circuit406are respectively coupled to VDDand to circuit ground.

FIG.4Dis a schematic diagram of one embodiment of a level shifter404that may be used in the circuit ofFIG.4C. A lower level of circuitry is coupled between VDD2and Gnd2, and an upper level of circuitry is coupled between VDD1and Gnd1. VDD1and Gnd1can be at the same or higher voltages with respect to VDD2and Gnd2. In the lower level, a clock signal φnmay be applied as an input to a first buffering inverter442powered by VDD2. The output of the first buffering inverter442controls the gate of a FET M1and is also coupled to a second buffering inverter444powered by VDD2, which in turn controls the gate of a FET M2. FETs M1and M2are thus complementary.

In the upper level of circuitry, FETs M3, M4, M5, and M6form a latch446, the output of which is coupled to an inverter448, which in turn is coupled to an inverter449which provides a level-shifted control signal output OUT. Since FETs M1and M2are complementary, when one is ON (conducting), the other is OFF (blocking). Thus, FET M1turning ON sets OUT low, while FET M2turning ON sets OUT high. Note that, in general, the pull-down strength of FETs M1and M2needs to be much higher than FETs M3and M5to flip the state of the latch446.

The control signal output OUT of the main level shifter circuitry may be used directly as the control signal “OUTP” in the circuit ofFIG.3B. However, for the level shifter404shown inFIGS.4A-4C, a special delayed control signal is desirable for application to the input of the second level shifter414of the corresponding floating charge circuit406inFIG.4C. Accordingly, the OUT signal is applied to a first delay line450(shown as comprising 4 series-coupled inverters; fewer or more may be used in a particular application). The output of the first delay line450is OUTP, which may be applied to the input of an associated driver circuit402inFIGS.4A-4C.

The OUT signal is also applied to a second delay line452(shown as comprising 4 series-coupled inverters; fewer or more may be used in a particular application) and to a first input of a NAND gate454. The output of the second delay line452is coupled to a second input of the NAND gate454. The output of the NAND gate454is applied to inverter456, the output of which is an OUTS control signal. When OUT goes high, the second delay line452, the NAND gate454, and the inverter456will delay OUTS from going high until sometime after OUTP goes high. However, when OUT goes low, the output of the NAND gate454will quickly go high, meaning that the output of the inverter (OUTS) will quickly go low before OUTP from the first delay line450can go low. Note that the number of inverters used in the first delay line450and the second delay line453are only to show a relative delay between the different paths. The actual number of inverters may vary to provide proper delays for optimal circuit function.

FIG.4Eis timing diagram of OUT, OUTP, and OUTS fromFIG.4D. As shown, OUTP and OUTS go high a delayed time after OUT goes high, and go low a delayed time after OUT goes low. In addition, OUTS goes high after OUTP goes high, and OUTS goes low shortly before OUTP goes low; thus, when asserted, OUTS is nested within the waveform of the asserted OUTP.

FIG.4Fis a block diagram of one embodiment of the voltage detector412, as previously described/shown inFIG.4C. The voltage detector412senses the voltage across the v2and g2terminals of the floating charge circuit406with respect to a reference voltage that represents the minimum voltage for the gate driver circuit402to work. In the illustrated example, a bandgap voltage generator470provides a reference voltage VBGto a first input of a comparator472. Resistors R1and R2are series coupled as a voltage divider between the v2and g2terminals of the floating charge circuit406, to scale the voltage from the v2terminal to the input range of the comparator472. The output OUT of the voltage detector412is asserted by the comparator472when the sensed scaled voltage across the v2and g2terminals is above VBG. The desired voltage VMINat which OUT is asserted can be set by choosing the values of R1and R2such that VMIN=VBG/[R2/(R1+R2)].

B. Startup Mode

During startup of the power converter400before the power FETs Mn start switching, the bootstrap capacitors Cn (only C1to C7in the example ofFIG.4A) are pre-charged to VMINby the first sub-circuit of the corresponding floating charge circuit406with the following progression of events. Initially, FET MP1is ON (conductive) in each floating charge circuit406of all of the tiers (except the last tier in some embodiments). The charge pump306(which turns ON at the beginning and operates concurrently with pre-charging of the bootstrap capacitors to VMIN) begins to generate the VIN+VDDvoltage, which is applied to the power input v1of the top tier floating charge circuit406. Meanwhile, the power FETs Mn remain OFF due to low gate-source voltages (VGS). Since FET MP1is conductive, the VIN+VDDvoltage applied at the power input v1of the top tier floating charge circuit406will flow through FET MP1and the resistor R and thus charge the corresponding bootstrap capacitor C1of the top tier, which is coupled to the power output v2and second reference input g2of the top tier floating charge circuit406. The presence of the resistor R (or other current-limiting component) limits in-rush current that might damage circuitry in the various tiers.

Because of the cascaded architecture of the power converter400, the input voltage applied to the floating charge circuit406of the top tier also flows through lower tiers and charges the respective bootstrap capacitor Cn of those tiers. For example, bootstrap capacitor C1is coupled to the v1and g1terminals of the floating charge circuit406of the second tier. Since FET MP1of the second tier is also conductive during startup, charge from bootstrap capacitor C1will flow into bootstrap capacitor C2. Similarly, charge will cascade down through all successive floating charge circuits406to pre-charge their corresponding bootstrap capacitor Cn (as noted above, in some embodiments, the last bootstrap capacitor may be directly pre-charged by VDD).

Once the voltage detector412in a tier senses that the voltage between v2and Gnd2of the corresponding floating charge circuit406exceeds VMIN(which reflects that a minimum charge has accumulated on the associated bootstrap capacitor Cn), the voltage detector412asserts a control signal to an IN port of the associated first level shifter410, which in response asserts a gate control signal from an OUT port coupled to the control gate of FET MP1, which turns FET MP1OFF. In embodiments in which the bootstrap capacitor of the last tier (C8in this example) is tied to VDD—which is above VMIN—the FET MP1of the bottom-most floating charge circuit406will be forced OFF at the beginning of the startup phase by the corresponding voltage detector412and first level shifter410since the corresponding bootstrap capacitor is pre-charged. Once the bootstrap capacitor Cn in each tier reaches at least VMIN, the pre-charging function of the floating charge circuits406is complete.

In essence, the first sub-circuit of a floating charge circuit406in each tier provides a current-limited pre-charging pathway through the floating charge circuit406to a next floating charge circuit406in an adjacent tier. By tying the top tier to a boosted power supply, VIN+VDD, charge will flow through all tiers until the associated bootstrap capacitor Cn in each tier is charged to VMIN.

C. Operational Mode

Once all bootstrap capacitor Cn are charged to a voltage at or above VMIN, thereby providing sufficient VGSlevels for the power FETs Mn, the power FETs Mn start to toggle in response to control signals applied to the corresponding level shifter404and driver circuit402(e.g., a clock signal φnthat controls the ON or OFF state of the corresponding power FET Mn). In this operational mode, the bootstrap capacitors Cn are periodically rebalanced by the pathways enabled by the second sub-circuit of the corresponding floating charge circuit406.

For example, while power FET M1in the first tier is in an OFF state, the second level shifter414in the corresponding floating charge circuit406will hold FET MP2in a non-conducting OFF state. When the associated control signal to the corresponding level shifter404(e.g., a clock signal φ1) causes OUTP to be asserted, power FET M1toggles to a conducting ON state. As a result of turning power FET M1ON, the charge on the corresponding bootstrap capacitor C1is partially depleted. Accordingly, charge will transfer from VIN+VDD(applied to v1of the corresponding floating charge circuit406) to the bootstrap capacitor C1through FET MP2and replenish the charge lost to charging/discharging the control gate of power FET M1as well as its associated level shifter/gate driver circuitry.

When the nested logic-level output OUTS of the level shifter404corresponding to power FET M1is asserted and applied to an IN port of the associated second level shifter414, a gate control signal VGS_INis asserted from an OUT port of the associated second level shifter414coupled to the control gate of FET MP2, which switches FET MP2to a non-conducting (OFF) state. In general, it is desirable that OUTS be de-asserted before the corresponding power FET M1is turned OFF, as shown by the timing diagram inFIG.4E.

Viewed another way, FET MP1turns ON whenever the voltage on its corresponding capacitor Cn is below a predetermine threshold, and turns OFF when the Cn voltage is at or above a desired level (for example, such as turning ON below 2.2V and turning OFF at or above 2.2V), regardless of the state of the associated FET Mn. On the other hand, FET MP2turns ON shortly after the associated FET Mn turns ON, and turns OFF shortly before the associated FET Mn turns OFF. Because the state of FET MP1is independent of state of the associated FET Mn, the voltage drop across FET MP1and the resistor R can be as high as the VDs voltage of the associated FET Mn when OFF. This voltage can be large so the resistor R or other current limiter serves to limit the maximum current level that can flow through FET MP1. In normal operation, FET MP1almost never turns ON because each bootstrap capacitor will be charged to near VDDlevel by the MP2path. By choosing VMINto be sufficiently below VDD(e.g., 2.2V versus 3.3V), the MP1path is kept OFF during normal operation.

Because of the cascaded interconnection of power connections throughout the tiers, charge will transfer from bootstrap capacitor C1to bootstrap capacitor C2when power FET M2is ON, from bootstrap capacitor C2to bootstrap capacitor C3when power FET M3is ON, and so forth. For example, terminals v2and g2of tier1(corresponding to power FET M1) are respectively coupled to terminals v1and g1of tier2(corresponding to power FET M2), and accordingly the charge on bootstrap capacitor C1can transfer to bootstrap capacitor C2when FET MP2in tier2is conducting.

In the embodiment illustrated inFIG.4A, the bottom tier is tied to VDDand circuit ground, and accordingly bootstrap capacitor C8is charged from VDD. Thus, while the upper tiers transfer charge downward from tier1, simultaneously charge is transferred upward from the bottom tier (corresponding to power FET M8in this example). Thus, when power FET M8is ON, charge will transfer from bootstrap capacitor C8to bootstrap capacitor C7, and when power FET M7is ON, charge will transfer from bootstrap capacitor C7to bootstrap capacitor C6, and so forth. In other embodiments in which the bottom tier is not tied to VDD, charge will only transfer downward, from tier1to the last tier.

In essence, during charge transfer, the two bootstrap capacitors in adjacent tiers are periodically connected through the second sub-circuit of the floating charge circuit406in one of those tiers, allowing charge to be equalized (rebalanced) between the two bootstrap capacitors.

Note that terminal VDD2of the first level shifter410inFIG.4Cmay function as either an input or an output. While terminal VDD2is nominally an output, for the case where the lowest tier FET driver circuit402is powered from VDD(e.g., as inFIG.4A), once normal operation starts, VDD2can become an input that feeds current flowing through FET MP2to terminal VDD1, which will charge the bootstrap capacitor in the tier immediately above the lowest tier and continue to ripple up to higher tiers in the same manner. Basically, when FET MP2in the floating charge circuit406of the lowest tier is ON, the capacitor charge equalizes and charge flows from the higher voltage capacitor to the lower voltage capacitor, which dictates the direction of the charge flow.

In the embodiment shown inFIG.4A, in which the bottom tier is connected to VDDand circuit ground, the charge on each bootstrap capacitor Cn in the remaining seven tiers is rebalanced through FETs MP2. Those FETs have an RONwhich can be on the order of a few ohms to tens of an ohm, depending on the size of the FETs. Power loss essentially will be the conduction loss and is I2×RONper bootstrap capacitor Cn (totaling 7×I2×RONin the example shown inFIG.4A), where I is the average current (there is also gate capacitance switching loss from turning FET MP2ON or OFF, but that loss is much less than the conduction loss of FET MP2). Another factor that influences power loss is the value of the capacitors Cn. Larger Cn values would reduce the power loss due to FET MP2ON resistance, which is the same power loss due to capacitor charge redistribution loss, which follows the equation, ¼Cn(V12+V22−2V1V2), where V1and V2are the two coupled adjacent capacitor initial voltages (i.e., before FET MP2turns ON and equalizes the two voltages). As can be seen from the equation, larger capacitor values are preferred to minimize the voltage difference between V1and V2, which minimizes the power loss. Further, during the operational mode, there is essentially no power loss in the floating charge circuit406while FET MP2is OFF and thus not passing charge for rebalancing (as noted above, because the associated Cn voltage should be above VMINduring normal operation, FET MP1should be held in the OFF state, thereby incurring essentially no power loss). Compared to the architecture shown inFIG.3A, the power saving for the architecture shown inFIG.4Ais expected to be 2 to 5 times or more. A higher VIN−VSSvoltage would increase the power loss for the architecture ofFIG.3A, while the power loss for the architecture inFIG.4Ashould be relatively constant as a function of VIN−VSS. VSSis the source voltage of FET M8inFIG.3A, which is ground; for the case of an inverting buck-boost power converter, VSScan be a negative voltage.

Other Benefits

In some embodiments of the architecture inFIG.4A, a relatively large charge pump306is used to generate VIN+VDDin order to charge all or some of the bootstrap capacitors Cn in a “top-rippling-down” fashion during both startup and normal operation. A relatively large charge pump circuit is needed because high efficiency is desirable during normal operation. In general, such a charge pump would require a relatively large circuit area, additional package pins, and relatively large external capacitors. Using a charge pump to constantly generate VIN+VDDalso incurs some power loss during all modes of operation.

As shown in the example ofFIG.4A, a separate supply (VDD) may be used to power the lowest tier. An added benefit of the architecture inFIG.4Afor buck power converters is that charge transfer between adjacent capacitors Cn can take place from VIN+VDDrippling down from the top tier and/or from VDDrippling up from the bottom tier. Accordingly, the VIN+VDDcharge pump306can be disabled in the normal operational mode since the path at the bottom tier from the VDDsource enables charge transfer to ripple up through all of the tiers to the top tier. The result would be power loss from the charge pump306only during startup of the power converter, leading to an overall reduction in power loss for the power converter as a whole.

Thus, in some buck converter embodiments, the charge pump306can be realized as a much smaller charge pump using smaller on-chip charge pump capacitors to generate VIN+VDDonly during startup mode to power the bootstrap capacitors Cn to a minimum required level of voltage. Then during normal operation, the charge pump is disabled and all bootstrap capacitors are charged from VDDby the “bottom-rippling-up” charge flow. This approach would have the benefit of eliminating the need for external charge pump capacitors and extra package pins. There may also be a layout area savings from the reduced charge pump size, but this area saving may be somewhat offset by the use of on-chip capacitors. However, depending on the type of on-chip capacitors used—for example, if metal capacitors are used that are located on top of charge pump active circuits—the total layout area savings may still be realized if the capacitor area is not too large.

OTHER EMBODIMENTS

It should be appreciated that while the examples shown inFIGS.3A and4Aare 5-level buck power converters, the inventive concepts may be used in conjunction with other multi-level power converters (e.g., 3-level, 4-level, n-level).

The inventive concepts also may be used in conjunction with boost power converters. For example, the architecture shown inFIG.4Acan be transformed to a 5-level boost topology by treating the VINas the VOUTterminal, and the VOUTterminal as the VINterminal (i.e., by switching the functions of the illustrated terminals).

The inventive concepts also may be used in conjunction with inverting buck-boost power converters. Inverting buck-boost power converters generate an inverted output voltage which can range from near 0V down to very large negative voltages, subject to transistor operational voltage limits. For example, the architecture shown inFIG.4Acan be transformed to a 5-level inverting buck-boost topology by switching the power FETs Mn in certain patterns and not tying the bottom tier floating charge circuit406and corresponding bootstrap capacitor C8to VDD. In addition, the VOUTterminal would be coupled to circuit ground, and the illustrated ground terminal would become VOUT. In such a configuration, rebalancing charge flows only one way, from the top tier to the bottom tier.

As noted above with respect toFIG.4C, FET MP1in each floating charge circuit406of all of the tiers (except the last tier in some embodiments) is initially ON (conductive) and stays ON until the voltage detector412in a tier senses that the voltage between v2and Gnd2of the corresponding floating charge circuit406exceeds VMIN(which reflects that a minimum charge has accumulated on the associated bootstrap capacitor Cn), at which time the voltage detector412asserts a control signal to an IN port of the associated first level shifter410, which in response asserts a gate control signal from an OUT port coupled to the control gate of FET MP1, which turns FET MP1OFF. Thus, FET MP1in each floating charge circuit406is effectively in parallel with a corresponding power FET M1of the power converter400. This characteristic can be used in alternative embodiments to omit the charge pump otherwise required to provide power to the top-most floating charge circuit406.

Pre-Charging Embodiment

In a variation of the power converter architecture shown inFIG.4A, using a sequence of bootstrap capacitor pre-charging phases during a startup stage allows omission of a charge pump for the top-most floating charge circuit406of a power converter400like that shown inFIG.4A. By using selected switch configurations in a sequence of bootstrap capacitor pre-charging phases of a startup stage, the bootstrap capacitors Cn may be sufficiently pre-charged to enable normal operation of the level shifters404and driver circuits402controlling the operation of the power FETs Mn. An additional benefit is that the fly capacitors CFXmay be partially pre-charged, thereby speeding up the overall startup process.

FIG.5Ais a simplified schematic diagram of a circuit like the circuit shown inFIG.4Ashowing the end of a first bootstrap capacitor pre-charging phase. Each of the bootstrap P-type FETs MP1within the floating charge circuit406(seeFIG.4C) is represented as a bootstrap switch SwB1to SwB8(generically, “SwBn”) coupled to a first plate of a corresponding bootstrap capacitor Cn. In addition, bootstrap switch SwB8is coupled to a voltage source VDD(the remaining circuitry of each floating charge circuit406, as well as the corresponding level-shifter circuits404and driver circuits402, is omitted to reduce clutter). Each of the N-type power FETs M1-M8(generically, “Mn”) is represented as a power switch Sw1to Sw8(generically, “Swn”). Of course, the number of switches SwBn and Swn will vary with the number of tiers in the power converter400.

Referring toFIG.5A, all fly capacitors CFXinitially are either uncharged (e.g., when the entire power converter400is first being powered up after a long OFF state) or are actively discharged using known techniques (e.g., when the power converter400is recovering from or entering into a state of operation and some charge remains on the fly capacitors CFX). At this point, VDD=0V and VIN=0V, and the first and second level shifters410,414in the floating charge circuits406default to an output of zero volts. That zero-output value, applied to the P-type FETs MP1(corresponding to the bootstrap switches SwBn) in the floating charge circuits406means that all of the bootstrap switches SwBn switches are OPEN, as shown inFIG.5A. Similarly, the level shifters404corresponding to the power switches Swn also default to an output of zero volts. That zero-output value, applied to the N-type power FETs Mn, means that all of the power switches Swn switches are also OPEN, as shown inFIG.5A.

As part of the startup sequence, the controller422(seeFIG.4B) is operated to output a set of startup control signals φnto the power FETs Mn (i.e., the power switches Swn), as shown inFIGS.4B and4C. The startup control signals φnare also applied, in delayed form, to the corresponding second level shifters414in the floating charge circuits406via the OUTS signal (seeFIG.4C). This startup set of control signals is generally different from the periodic clock signals normally generated after startup is completed. This startup state of operation of the controller422may be initiated and controlled by a command signal generated within the power converter400or by externally supplied commands. In the illustrated example, the controller422respectively sets the control signals φ1-φ8for the power switches Sw1-Sw8to the pattern “01101111”, where “0” means OPEN and “1” means CLOSED. Note that this special pattern of control signals φ1-φ8represents desired target switch states for the power switches Sw1-Sw8; the respective power switches Sw1-Sw8are initially all OPEN (i.e., have a pattern of “00000000”) and will only achieve the actual target states of “01101111” corresponding to the special pattern of control signals φ1-φ8when the corresponding bootstrap capacitors C1-C8are sufficiently charged to power the corresponding level shifter404and driver circuit402. Accordingly,FIG.5Ashows the switches SwBn and Swn in an initial all-OPEN state rather than in their desired target states (that is, with switches Sw2, Sw3, Sw5-Sw8CLOSED).

An added startup signal (indicated by the dotted arrow inFIG.5A) is applied to the floating charge circuit406for the top bootstrap switch SwB1(e.g., by selectively connecting the gate of the P-type FET MP1in the floating charge circuit406of switch SwB1to circuit ground during the bootstrap capacitor pre-charging phases of the startup stage) to force bootstrap switch SwB1to be in a CLOSED state even when sufficiently powered (again noting that this is a target switch state). Thus, while control signal (pi targets power switch Sw1to be OPEN, the added startup signal targets bootstrap switch SwB1to be CLOSED. The added startup signal may be provided by the controller422.

FIG.5Bis a simplified schematic diagram of the circuit ofFIG.5Ashowing the end of a second bootstrap capacitor pre-charging phase. When VDDis applied to terminal v2of the floating charge circuit406for the bottom bootstrap switch SwB8, bootstrap capacitor C8is charged. Since the control signal φ8for power switch Sw8has a target value of “1” (CLOSED), when the charge on bootstrap capacitor C8has become sufficient to power the corresponding level shifter404and driver circuit402, power switch Sw8will remain CLOSED for the rest of the bootstrap capacitor pre-charging phases. In addition, the voltage differential between the gate and drain of the P-type FET MP1in the floating charge circuit406for the bottom bootstrap switch SwB8will cause FET MP1to begin conducting, and thus bootstrap switch SwB8will be in a CLOSED state, matching the target state for switch Sw8.

Because the P-type FET MP1in the floating charge circuit406for the bottom bootstrap switch SwB8is now CLOSED, charge will flow from VDDto the floating charge circuit406for the next upward bootstrap switch SwB7, as described above. Accordingly, bootstrap capacitor C7will be charged, power switch Sw8will CLOSE to match its target state set by the control signal φ7, and corresponding bootstrap switch SwB7will transition to a CLOSED state.

In a similar fashion, charge will transfer from bootstrap capacitor C7through bootstrap switch SwB7to bootstrap capacitor C6(thus CLOSING power switch Sw6to match its target state), from bootstrap capacitor C6through bootstrap switch SwB6to bootstrap capacitor C5(thus CLOSING power switch Sw5to match its target state), and from bootstrap capacitor C5through bootstrap switch SwB5to bootstrap capacitor C4. At this point in the startup sequence, bootstrap switches SwB5-SwB8all match the target state (“1111”) for their corresponding power switches Sw5-Sw8.

The target state set by the control signal φ4for power switch Sw4is OPEN (“0”). Accordingly, while there is sufficient charge on bootstrap capacitor C4to close bootstrap switch SwB4and power switch Sw4, they will instead remain OPEN to match the target state (i.e., φ4=“0”). At this point, the cascade of charge from VDDupwards through the set of tiers ends, and power switches Sw1-Sw3are not affected by the flow of charge from VDD, and hence nominally remain OPEN (but see the discussion ofFIG.5C). Thus, at the end of the second bootstrap capacitor pre-charging phase, the switches Swn and SwBn are as shown inFIG.5B.

Of note, by closing power switches Sw5-Sw8, each of the fly capacitors CFX(C4to C8) have one plate coupled to circuit ground.

FIG.5Cis a simplified schematic diagram of the circuit ofFIG.5Ashowing the end of a third bootstrap capacitor pre-charging phase. As or after VDDis applied, as described above, VINmay be applied. Since VINis tied to the source of the P-type FET MP1in the floating charge circuit406of the topmost bootstrap switch SwB1, bootstrap switch SwB1begins to conduct (turns ON) when VINis above the threshold voltage VTHof the P-type FET. Accordingly, charge will flow from VINto bootstrap capacitor C1. When bootstrap capacitor C1is sufficiently charged, the corresponding level shifter404and driver circuit402for power switch Sw1(an N-type FET) can maintain the original OPEN state of that switch, thus matching its target state (i.e., φ1=“0”). However, while bootstrap switch SwB1would normally follow the OPEN/CLOSED state of power switch Sw1, the added startup signal (indicated by the dotted arrow inFIG.5C) maintains bootstrap switch SwB1in a CLOSED state, which allows charge to flow from VINto bootstrap switch SwB2.

As was the case with bootstrap switch SwB1, bootstrap switch SwB2begins to conduct (turns ON) when VINis above the VTHof the P-type FET MP1in the corresponding floating charge circuit406. As a result, charge will flow from VINthrough bootstrap switches SwB1and SwB2to bootstrap capacitor C2. When bootstrap capacitor C2is sufficiently charged, the corresponding level shifter404and driver circuit402will have sufficient power to set power switch Sw2to a CLOSED state, thus matching its target state (i.e., φ2=“1”).

In a similar fashion, bootstrap switch SwB3begins to conduct, enabling power switch Sw3to be set to a CLOSED state, thus matching its target state (i.e., φ3=“1”). Accordingly, just before the end of the third phase of the bootstrap capacitor pre-charging phases, switches SwB1-SwB3, SwB5-SwB8, Sw2-Sw3, and Sw5-Sw8are CLOSED, and switches Sw1, SwB4, and Sw4are OPEN. Thus, near the end of the third bootstrap capacitor pre-charging phase, the switches Swn and SwBn are as shown inFIG.5Cand bootstrap capacitors Cn are pre-charged.

In general, after the voltages across bootstrap capacitors C1-C3reach desired respective values, the bootstrap switches SwB1-SwB3and the power switches Sw2-Sw3may be opened by the controller422to isolate the bootstrap capacitors from VIN. Further, when the voltage across bootstrap capacitor C3reaches a desired value, the added startup signal may be removed by the controller422, thus allowing the state of bootstrap switch SwB1to follow the state of power switch Sw1.

Of note, when bootstrap switches SwB1-SwB3are in a CLOSED state and the corresponding bootstrap capacitors C1-C3are charged, then fly capacitors CF1-CF3will also begin to charge since power switches Sw6-Sw8are also closed and thus each of the fly capacitors CFXhas one plate coupled to circuit ground. Because the fly capacitors CF1-CF3are much larger than their corresponding bootstrap capacitors C1-C3, the voltage across the fly capacitors CF1-CF3will rise much slower than the voltage across the corresponding bootstrap capacitors C1-C3. Accordingly, the fly capacitors CFXmay still need to be more fully charged before the startup stage is fully completed. Additional circuitry (not shown) may be used to accomplish such charging. Examples of such circuitry may be found, for instance, in U.S. Pat. No. 10,720,843, entitled “Multi-Level DC-DC Converter with Lossy Voltage Balancing”, issued Jul. 21, 2020, assigned to the assignee of the present invention, the contents of which are incorporated by reference.

Note that all of the SwBn and Swn switches cannot be closed or there will be a shorting path from VINto GND, so the path must be interrupted somewhere. For the illustrated example, selecting the SwB4and Sw4switches to be OPEN is particularly useful, because doing so would not only interrupt the shorting path but also allow the fly capacitors CFXto initiate charging.

In summary, with this sequence of bootstrap capacitor pre-charging phases during the startup stage, the lower bootstrap capacitors (C4-C8in this example) may be pre-charged to VDD, which can provide the associated floating charge circuits406with sufficient power to operate their corresponding level-shifter circuits404and driver circuits402and drive their corresponding power FETs Swn to the target states defined by the control signals φ4-φ8. The upper bootstrap capacitors (C1-C3in this example) may also be pre-charged from VIN, as described above. Accordingly, a separate charge pump is not needed to sufficiently charge the bootstrap capacitors Cn to enable normal operation of the level shifters404and driver circuits402.

In the example embodiment described above, as bootstrap switches SwB1-SwB3become CLOSED, and with power switches Sw2and Sw3set to a CLOSED target state, bootstrap capacitors C1-C3will be coupled in parallel. In an alternative embodiment, power switches Sw2and Sw3may be left OPEN (i.e., the control signals φ1-φ8for the power switches Sw1-Sw8would have the pattern “00001111”) if the floating charge circuits406for power switches Sw2and Sw3are also controlled by a respective added startup signal to force bootstrap switches SwB2and SwB3to be in a CLOSED state when sufficiently powered (again noting that this is a target switch state). Thus, while control signals φ1-φ3target power switches Sw1-Sw3to be OPEN, the added startup signals target bootstrap switches SwB1-SwB3to be CLOSED during the bootstrap capacitor pre-charging phases. Note that there may be other valid sequences, but a key characteristic of this aspect of the invention is that a start-up sequence that is different from operational switching states may be used to eliminate the need for a charge pump.

Example Control Circuitry for an M-Level Multi-Level Converter Cell

FIG.6is a block diagram of one embodiment of control circuitry600for an M-level converter cell602coupled to an output block604comprising an inductor L and an output capacitor COUT(conceptually, the inductor L also may be considered as being included within the M-level converter cell602). This example control circuitry600is adapted from the teachings set forth in U.S. Patent Application Ser. No. 63/276,923, filed Nov. 8, 2021, entitled “Controlling Charge-Balance and Transients in a Multi-Level Power Converter”, assigned to the assignee of the present invention, the contents of which are incorporated by reference. However, the present invention may be used in combination with other types of control circuitry for an M-level converter cell602.

The control circuitry600functions as a control loop coupled to the output of the M-level converter cell602and to switch control inputs of the M-level converter cell602. In general, the control circuitry600is configured to monitor the output (e.g., voltage and/or current) of the M-level converter cell602and dynamically generate a set of switch control inputs to the M-level converter cell602that attempt to stabilize the output voltage and/or current at specified values, taking into account variations of VINand output load. In alternative embodiments, the control circuitry600may be configured to monitor the input of the M-level converter cell602(e.g., voltage and/or current) and/or an internal node of the M-level converter cell602(e.g., the voltage across one or more fly capacitors or the current through one or more power switches). Accordingly, most generally, the control circuitry600may be configured to monitor the voltage and/or current of a node (e.g., input terminal, internal node, or output terminal) of the M-level converter cell602. The control circuitry600may be incorporated into, or separate from, the overall controller104for a power converter100embodying the M-level converter cell602.

A first block comprises a feedback controller606, which may be a traditional controller such as a fixed frequency voltage mode or current mode controller, a constant-on-time controller, a hysteretic controller, or any other variant. The feedback controller606is shown as being coupled to VOUTfrom the M-level converter cell602. In alternative embodiments, the feedback controller606may be configured to monitor the input of the M-level converter cell602and/or an internal node of the M-level converter cell602. The feedback controller606produces a signal directly or indirectly indicative of the voltage at VOUTthat determines in general terms what needs to be done in the M-level converter cell602to maintain desired values for VOUT: charge, discharge, or tri-state (i.e., open, with no current flow).

In the illustrated example, the feedback controller606includes a feedback circuit608, a compensation circuit610, and a PWM generator612. The feedback circuit608may include, for example, a feedback-loop voltage detector which compares VOUT(or an attenuated version of VOUT) to a reference voltage which represents a desired VOUTtarget voltage (which may be dynamic) and outputs a control signal to indicate whether VOUTis above or below the target voltage. The feedback-loop voltage detector may be implemented with a comparison device, such as an operational amplifier (op-amp) or transconductance amplifier (gm amplifier).

The compensation circuit610is configured to stabilize the closed-loop response of the feedback controller606by avoiding the unintentional creation of positive feedback, which may cause oscillation, and by controlling overshoot and ringing in the step response of the feedback controller606. The compensation circuit610may be implemented in known manner, and may include LC and/or RC circuits.

The PWM generator612generates the actual PWM control signal which ultimately sets the duty cycle of the switches of the M-level converter cell602. In some embodiments, the PWM generator612may pass on additional optional control signals CTRL indicating, for example, the magnitude of the difference between VOUTand the reference voltage (thus indicating that some levels of the M-level converter cell602should be bypassed to get to higher or lower levels), and the direction of that difference (e.g., VOUTbeing greater than or less than the reference voltage). In other embodiments, the optional control signals CTRL can be derived from the output of the compensation circuit610, or from the output of the feedback circuit608, or from a separate comparator (not shown) coupled to, for example, VOUT. One purpose of the optional control signals CTRL is for advanced control algorithms, when it may be beneficial to know how far away VOUTis from a target output voltage, thus allowing faster charging of the inductor L if the VOUTis severely under regulated.

A second block comprises an M-level controller614, the primary function of which is to select the switch states that generate a desired VOUTwhile maintaining a charge-balance state on the fly capacitors within the M-level converter cell602every time an output voltage level is selected, regardless of what switch state or states were used in the past.

The M-level controller614includes a Voltage Level Selector616which receives the PWM control signal and the additional control signals CTRL if available. In addition, the Voltage Level Selector616may be coupled to VOUTand/or VIN, and, in some embodiments, to HIGH/LOW status signals, CFx_H/L, from voltage detectors coupled to corresponding fly capacitors CFXwithin the M-level converter cell602. A function of the Voltage Level Selector616is to translate the received signals to a target output voltage level (e.g., on a cycle-by-cycle basis). The Voltage Level Selector616typically will consider at least VOUTand VINto determine which target level should charge or discharge the output of the M-level converter cell602with a desired rate.

The output of the Voltage Level Selector616is coupled to an M-level Switch State Selector618, which generally would be coupled to the status signals, CFx_H/L, from the capacitor voltage detectors for the fly capacitors CFx. Taking into account the target level generated by the Voltage Level Selector616, the M-level Switch State Selector618determines which switch state for the desired output level should be best for capacitor charge-balance. The M-level Switch State Selector618may be implemented, for example, as a look-up table (LUT) or as comparison circuitry and combinatorial logic or more generalized processor circuitry. The output of the M-level Switch State Selector618is coupled to the switches of the M-level converter cell602(through appropriate level-shifter circuits and drivers circuits, as may be needed for a particular converter cell) and includes the switch state settings determined by the M-level Switch State Selector618(which selects the configuration of switches within the M-level converter cell602corresponding to a selected target level).

In general (but not always), the Voltage Level Selector616and the M-level Switch State Selector618only change their states when the PWM signal changes. For example, when the PWM signal goes high, the Voltage Level Selector616selects which level results in charging of the inductor L and the M-level Switch State Selector618sets which version to use of that level. Then when the PWM signal goes low, the Voltage Level Selector616selects which level should discharge the inductor L and the M-level Switch State Selector618sets which version of that level to use. Thus, the Voltage Level Selector616and the M-level Switch State Selector618generally only change states when the PWM signal changes (the PWM signal is in effect their clock signal). However, there may be situations or events where it is desirable for the CTRL signals to change the state of the Voltage Level Selector616. Further, there may be situations or events where it is desirable for the CFx_H/Lstatus signal(s) from voltage detectors coupled to the fly capacitors CFxwithin the M-level converter cell602to cause the M-level Switch State Selector618to select a particular configuration of power switch settings, such as when a severe mid-cycle imbalance occurs. In some embodiments, it may be useful to include a timing function that forces the M-level Switch State Selector618to re-evaluate the optimal version of the state periodically, for example, in order to avoid being “stuck” at one level for a very long time, potentially causing charge imbalances.

In embodiments that utilize the teachings set forth in the patent application entitled “Controlling Charge-Balance and Transients in a Multi-Level Power Converter” referenced above, the M-level controller614implements a control method for the M-level converter cell602that selects an essentially optimal switch state which moves the fly capacitors CFxtowards a charge-balance state every time a voltage level at the LXnode is selected, regardless of what switch state or states were used in the past. Accordingly, such multi-level converter circuits are free to select a different switch state or LXvoltage level every switching cycle without a need to keep track of any prior switch state or sequence of switch states.

One notable benefit of the control circuitry shown inFIG.6is that it enables generation of voltages in boundary zones between voltage levels, which represent unattainable output voltages for conventional multi-level DC-to-DC converter circuits.

In alternative unregulated charge-pumps embodiments, the feedback controller606and the Voltage Level Selector616may be omitted, and instead a clock signal CLK may be applied to the M-level Switch State Selector618. The M-level Switch State Selector618would generate a pattern of switch state settings that periodically charge balances the fly capacitors CFxregardless of what switch state or states were used in the past (as opposed to cycling through a pre-defined sequency of states). This ensures that if VINchanges or anomalous evens occur, the system generally always seeks charge balance for the fly capacitors CFx.

In some embodiments, the M-level Switch State Selector618may take into account the current IL flowing through the inductor L by way of an optional current-measurement input620, which may be implemented in conventional fashion.

WhileFIG.6shows a particular embodiment of control circuitry for an M-level converter cell as modified in accordance with the present invention, it should be appreciated that other control circuits may be adapted or devised to provide suitable switching signals for the switches within a converter cell.

Methods

FIG.7is a process flow chart showing one method for providing a bootstrap power supply for LS/D circuits in a power converter without using a charge pump. Utilizing a circuit like that shown inFIG.4Aand simplified inFIGS.5A-5C, the method includes: applying a startup pattern of control signals to the power switches representing desired target switch states for the power switches and the bootstrap switches (Block702); applying an added startup signal to the bootstrap switch of the top-level floating charge circuit to force that bootstrap switch to be in a CLOSED state even when sufficiently powered (Block704); applying a supply voltage to the voltage supply terminal to enable a sequential transfer of charge to those bootstrap capacitors coupled to the lower set of power switches, wherein as each bootstrap capacitor in the sequence reaches a sufficient level to provide operational power to the corresponding floating charge circuits, the corresponding bootstrap switches and power switches are set to a state matching the corresponding desired target switch state (Block706); and applying an input voltage to the input terminal to enable a sequential transfer of charge to those bootstrap capacitors coupled to the upper set of power switches, wherein as each bootstrap capacitor in the sequence reaches a sufficient level to provide operational power to the corresponding floating charge circuits, the corresponding bootstrap switches and power switches are set to a state matching the corresponding desired target switch state, except for the bootstrap switch of the top-level floating charge circuit to which the added startup signal is applied (Block708). Some embodiments may further include applying an added startup signal to the bootstrap switch of at last one other floating charge circuit to force that bootstrap switch to be in a CLOSED state even when sufficiently powered.

Another aspect of the invention includes methods for providing a power-efficient bootstrap power supply for level-shifter/driver (LS/D) circuits in a power converter, such as a FET-based multi-level power converter. For example,FIG.8is a process flow chart800showing one method for providing a bootstrap power supply for LS/D circuits in a power converter. The method includes: in a startup mode, providing a pre-charging pathway from a boosted power supply (which may be current-limited) to a bootstrap capacitor in each tier of a plurality of tiers of LS/D circuits for the power converter until the bootstrap capacitor in each tier is charged to a minimum voltage (Block802); and in an operational mode, connecting (which may be periodically) the bootstrap capacitors in adjacent tiers to allow charge to be rebalanced between the connected bootstrap capacitors (Block804).

ADDITIONAL CONTROL AND OPERATIONAL CONSIDERATIONS

It may be desirable to provide additional control and operational circuitry (or one or more shutdown procedures) that enables reliable and efficient operation of a power converter utilizing a multi-level converter cell designed in accordance with the present disclosure. For example, in a step-down power converter, the output voltage of a converter cell is less than the input voltage of the converter cell. Shutting down or disabling (e.g., because of a fault event, such as a short) a converter cell having a designed-in inductance connected to the output while the output load current is non-zero generally requires some means for discharging the inductor current. In some embodiments, a bypass switch may be connected in parallel with a designed-in inductance connected to the output of a converter cell and controlled to be open during normal operation and closed when shutting down the converter cell or if a fault event occurs. Ideally, in order to prevent transient ringing and to provide safe discharge of the inductor current, the bypass switch can be closed before disabling converter cell switching. In alternative embodiments using MOSFETs for the main switches of the converter, the inherent body diode connected between the body and drain terminals of each MOSFET can also discharge the inductor current. Details of these solutions, as well as alternative shutdown solutions, are taught in U.S. Pat. No. 10,686,367, issued Jun. 16, 2020, entitled “Apparatus and Method for Efficient Shutdown of Adiabatic Charge Pumps”, assigned to the assignee of the present invention, the contents of which are incorporated by reference.

Another consideration when combining converter cells in parallel is controlling multiple parallel power converters in order to avoid in-rush current (e.g., during a soft-start period for the power converters) and/or switch over-stress if all of the power converters are not fully operational, such as during startup or when a fault condition occurs. Conditional control may be accomplished by using node status detectors coupled to selected nodes within parallel-connected power converters to monitor voltage and/or current. Such node status detectors may be configured in some embodiments to work in parallel with an output status detector measuring the output voltage of an associated power converter during startup. The node status detectors ensure that voltages across important components (e.g., fly capacitors and/or switches) within the converter cell(s) of the power converters are within desired ranges before enabling full power steady-state operation of the parallel power converters, and otherwise prevent full power steady-state operation. The node status detectors may be coupled to a master controller that controls one or more of the parallel power converters using one or more common control signals. In furtherance of a master controller configuration, the parallel power converters may each report a power good signal (Pgood) when ready to leave a startup phase for full power steady-state operation. The master controller may essentially “AND” all such Pgood signals together, possibly along with one or more status signals from other circuits, such that the master controller does not enable full power steady-state operation of any the parallel power converter unless all of the parallel power converters are ready for that state. In essence, the Pgood signals from each parallel power converter are all tied together such that the parallel power converters may not transition out of startup phase until all the Pgood signals indicate that they are ready to transition to steady operation. Furthermore, if the Pgood signal changes due to a fault condition in one or more of the parallel power converters, the parallel power converters can transition from a steady state operation to an auto-restart or shutdown operation. Details of these solutions, as well as alternative shutdown solutions, are taught in U.S. Pat. No. 10,992,226, issued Apr. 27, 2021, entitled “Startup Detection for Parallel Power Converters”, assigned to the assignee of the present invention, the contents of which are incorporated by reference.

Another consideration in operating multi-level converter cells is attaining (i.e., pre-charging) and maintaining fly capacitor voltages that are essentially fully proportionally balanced so that all switches are subjected to a similar voltage stress, since unbalanced fly capacitors can lead to breakdown of a switch (particularly FET switches) due to exposure to high voltages. One solution to both pre-charging capacitor voltages and operational balancing of capacitor voltages in a multi-level DC-to-DC converter circuit is to provide a parallel “shadow” circuit that conditionally couples a fly capacitor to a voltage source or other circuit to pre-charge that capacitor, or conditionally couples two or more fly capacitors together to transfer charge from a higher voltage capacitor to a lower voltage capacitor, or conditionally couples a fly capacitor to a voltage sink to discharge that capacitor, all under the control of real-time capacitor voltage measurements. Each parallel “shadow” circuit may comprise a switch and a resistor coupled in parallel with a main switch that is part of a multi-level converter cell (in some cases, one switch-resistor pair may span two series-connected switches). This particular solution for pre-charging and/or balancing charge on fly capacitors is very fast, provides slow pre-charging of the fly capacitors during a pre-charge period, protects switches from in-rush current, and provides stable voltages for converter cell switches. Details of this solution, as well as alternative pre-charging and charge balancing solutions, are taught in U.S. Pat. No. 10,720,843, issued Jul. 21, 2020, entitled “Multi-Level DC-DC Converter with Lossy Voltage Balancing”, assigned to the assignee of the present invention, the contents of which are incorporated by reference.

Another solution to balancing capacitor voltages in a multi-level DC-to-DC converter circuit is to provide a lossless voltage balancing solution where out-of-order state transitions of a multi-level DC-to-DC converter cell are allowed to take place during normal operation. The net effect of out-of-order state transitions is to increase or decrease the voltage across specific fly capacitors, thus preventing voltage overstress on the main switches of the DC-to-DC converter. In some embodiments, restrictions are placed on the overall sequence of state transitions to reduce or avoid transition state toggling, thereby allowing each capacitor an opportunity to have its voltage steered as necessary, rather than allowing one capacitor to be voltage balanced before voltage balancing another capacitor. Details of this solution, as well as alternative charge balancing solutions, are taught in U.S. Pat. No. 10,770,974, issued Sep. 8, 2020, entitled “Multi-Level DC-DC Converter with Lossless Voltage Balancing”, assigned to the assignee of the present invention, the contents of which are incorporated by reference.

An additional consideration for some embodiments is enabling operation of multi-level converter cells such that voltages can be generated in boundaries zones between voltage levels. “Boundary zones” represent unattainable output voltages for conventional multi-level DC-to-DC converter circuits. In order to generate output voltages within a boundary zone, some embodiments essentially alternate (toggle) among adjacent (or even nearby) zones by setting states of the converter cell switches in a boundary zone transition pattern. For example, a 3-level DC-to-DC converter circuit may operate in Zone 1 for a selected time and in adjacent Zone 2 for a selected time. Thus, Zones 1 and 2 are treated as a single “super-zone”. More generally, in some cases, it may be useful to create super-zones using non-adjacent zones or using more than two zones (adjacent and/or non-adjacent). Details of this solution are taught in U.S. Pat. No. 10,720,842, issued Jul. 21, 2020, entitled “Multi-Level DC-DC Converter with Boundary Transition Control”, assigned to the assignee of the present invention, the contents of which are incorporated by reference.

Yet another consideration for some embodiments is protection of the main power switches and other components within a power converter from stress conditions, particular from voltages that exceed the breakdown voltage of such switches (particularly FET switches). One means for protecting a multi-level power converter uses at least one high-voltage FET switch while allowing all or most other main power switches to be low-voltage FET switches.

In power converters, particularly multi-level power converters, the power switches may be implemented with FETs, especially MOSFETs. For each power FET, a driver circuit is generally required. In addition, for some power FETs, a level shifter may be required to translate ground-referenced low-voltage logic ON/OFF signals from an analog or digital controller into a signal with the same voltage swing but referenced to the source voltage of the power FET that the signal is driving in order to charge or discharge the gate of the power FET and thereby control the conducting or blocking state of the power FET. In some applications, the functions of a level shifter and a driver circuit may be incorporated into one circuit.

As should be clear, the multi-level power converter embodiments described in this disclosure may be synergistically combined with the teachings of one or more of the additional control and operational circuits and methods described in this section.

General Benefits and Advantages of Multi-Level Power Converters

Embodiments of the current invention improve the power density and/or power efficiency of incorporating circuits and circuit modules or blocks. As a person of ordinary skill in the art should understand, a system architecture is beneficially impacted utilizing embodiments of the current invention in critical ways, including lower power and/or longer battery life. The current invention therefore specifically encompasses system-level embodiments that are creatively enabled by inclusion in a large system design and application.

More particularly, multi-level power converters provide or enable numerous benefits and advantages, including:adaptability to applications in which input and/or output voltages may have a wide dynamic-range (e.g., varying battery input voltage levels, varying output voltages);efficiency improvements on the run-time of devices operating on portable electrical energy sources (batteries, generators or fuel cells using liquid or gaseous fuels, solar cells, etc.);efficiency improvements where efficiency is important for thermal management, particularly to protect other components (e.g., displays, nearby ICs) from excessive heat;enabling design optimizations for power efficiency, power density, and form-factor of the power converter—for example, smaller-size multi-level power converters may allow placing power converters in close proximity to loads, thus increasing efficiency, and/or to lower an overall bill of materials;the ability to take advantage of the performance of smaller, low voltage transistors;adaptability to applications in which power sources can vary widely, such as batteries, other power converters, generators or fuel cells using liquid or gaseous fuels, solar cells, line voltage (AC), and DC voltage sources (e.g., USB, USB-C, power-over Ethernet, etc.);adaptability to applications in which loads may vary widely, such as ICs in general (including microprocessors and memory ICs), electrical motors and actuators, transducers, sensors, and displays (e.g., LCDs and LEDs of all types);the ability to be implemented in a number of IC technologies (e.g., MOSFETs, GaN, GaAs, and bulk silicon) and packaging technologies (e.g., flip chips, ball-grid arrays, wafer level scale chip packages, wide-fan out packaging, and embedded packaging).

The advantages and benefits of multi-level power converters enable usage in a wide array of applications. For example, applications of multi-level power converters include portable and mobile computing and/or communication products and components (e.g., notebook computers, ultra-book computers, tablet devices, and cell phones), displays (e.g., LCDs, LEDs), radio-based devices and systems (e.g., cellular systems, WiFi, Bluetooth, Zigbee, Z-Wave, and GPS-based devices), wired network devices and systems, data centers (e.g., for battery-backup systems and/or power conversion for processing systems and/or electronic/optical networking systems), internet-of-things (IOT) devices (e.g., smart switches and lights, safety sensors, and security cameras), household appliances and electronics (e.g., set-top boxes, battery-operated vacuum cleaners, appliances with built-in radio transceivers such as washers, dryers, and refrigerators), AC/DC power converters, electric vehicles of all types (e.g., for drive trains, control systems, and/or infotainment systems), and other devices and systems that utilize portable electricity generating sources and/or require power conversion.

Radio system usage includes wireless RF systems (including base stations, relay stations, and hand-held transceivers) that use various technologies and protocols, including various types of orthogonal frequency-division multiplexing (“OFDM”), quadrature amplitude modulation (“QAM”), Code-Division Multiple Access (“CDMA”), Time-Division Multiple Access (“TDMA”), Wide Band Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G, and WiFi (e.g., 802.11a, b, g, ac, ax), as well as other radio communication standards and protocols.

Fabrication Technologies & Options

In various embodiments of multi-level power converters, it may be beneficial to use specific types of capacitors, particularly for the fly capacitors. For example, it is generally useful for such capacitors to have low equivalent series resistance (ESR), low DC bias degradation, high capacitance, and small volume. Low ESR is especially important for multi-level power converters that incorporate additional switches and fly capacitors to increase the number of voltage levels. Selection of a particular capacitor should be made after consideration of specifications for power level, efficiency, size, etc. Various types of capacitor technologies may be used, including ceramic (including multi-layer ceramic capacitors), electrolytic capacitors, film capacitors (including power film capacitors), and IC-based capacitors. Capacitor dielectrics may vary as needed for particular applications, and may include dielectrics that are paraelectric, such as silicon dioxide (SiO2), hafnium dioxide (HFO2), or aluminum oxide Al2O3. In addition, multi-level power converter designs may beneficially utilize intrinsic parasitic capacitances (e.g., intrinsic to the power FETs) in conjunction with or in lieu of designed capacitors to reduce circuit size and/or increase circuit performance. Selection of capacitors for multi-level power converters may also take into account such factors as capacitor component variations, reduced effective capacitance with DC bias, and ceramic capacitor temperature coefficients (minimum and maximum temperature operating limits, and capacitance variation with temperature).

Similarly, in various embodiments of multi-level power converters, it may be beneficial to use specific types of inductors. For example, it is generally useful for the inductors to have low DC equivalent resistance, high inductance, and small volume.

The controller(s) used to control startup and operation of a multi-level power converter may be implemented as a microprocessor, a microcontroller, a digital signal processor (DSP), register-transfer level (RTL) circuitry, and/or combinatorial logic.

The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and/or semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.

As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.

Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high-resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.

Voltage levels may be adjusted, and/or voltage and/or logic signal polarities reversed, depending on a particular specification and/or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functionality without significantly altering the functionality of the disclosed circuits.

Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and/or in modules for ease of handling, manufacture, and/or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and/or modules are then typically combined with other components, often on a printed circuit board, to form an end product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

CONCLUSION

A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and/or parallel fashion.

It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).