Patent ID: 12243613

DESCRIPTION OF EMBODIMENTS

Specific implementations of a voltage output test circuit, a voltage divider output circuit, and a memory provided in the embodiments of this invention are descried in detail below with reference to the accompanying drawings.

FIG.1is a circuit diagram of a voltage output test circuit according to some embodiments of this invention. As shown inFIG.1, the voltage output test circuit includes a first voltage divider unit101and a second voltage divider unit102. The first voltage divider unit101includes a first terminal and a second terminal, the first terminal of the first voltage divider unit101is electrically connected to a test power supply Vtest, and the second terminal of the first voltage divider unit101is electrically connected to an output terminal Vout. The second voltage divider unit102includes a first terminal and a second terminal, the first terminal of the second voltage divider unit102is connected to a ground Vss, and the second terminal of the second voltage divider unit102is electrically connected to the output terminal Vout. The output terminal Vout is configured to output a read-out voltage.

The output voltage read out by using the voltage output test circuit can be inaccurate. The reason for this problem can be that the output terminal is a DQ pad. In a data transmission process, a drive circuit needs to be added to the output terminal. To adapt to the design of SRAMs such as LPDDR5, a leakage current range allowed by the DQ pad is larger, for example, +/−5 μA. When the last-stage drive circuit has a relatively large leakage current during data transmission, that is, a leakage current between the output terminal Vout and the ground Vss is relatively large, a voltage drop on the second voltage divider unit102is relatively large, so that a voltage of the output terminal Vout increases. Consequently, a read-out voltage of the output terminal Vout is inaccurate.

In view of this, this embodiment of this invention provides a voltage output test circuit.

The voltage output test circuit includes a first voltage divider unit, a second voltage divider unit, and a third voltage divider unit. The first voltage divider unit includes a first terminal and a second terminal, the first terminal of the first voltage divider unit is electrically connected to a test power supply, and the second terminal of the first voltage divider unit is electrically connected to an output terminal. The second voltage divider unit includes a first terminal and a second terminal, the first terminal of the second voltage divider unit is connected to a ground, and the second terminal of the second voltage divider unit is electrically connected to the output terminal. The third voltage divider unit is configured to adjust a resistance between the output terminal and the ground.

The third voltage divider unit adjusts a drive current of the voltage output test circuit by adjusting the resistance between the output terminal and the ground, to reduce impact caused by a leakage current between the output terminal and the ground to the read-out voltage of the output terminal, so that the read-out voltage of the output terminal remains in a tolerable error range, improving the accuracy of the read-out voltage of the output terminal Vout, and improving the reliability of a chip test.

For example, when the leakage current between the output terminal and the ground is relatively large, the read-out voltage of the output terminal increases. In this case, the third voltage divider unit reduces the resistance between the output terminal and the ground to increase the drive current of the voltage output test circuit and reduce the read-out voltage of the output terminal, so that the read-out voltage of the output terminal remains in the tolerable error range. When the leakage current between the output terminal and the ground decreases, if the drive current of the voltage output test circuit remains unchanged, the read-out voltage of the output terminal decreases. In this case, the third voltage divider unit increases the resistance between the output terminal and the ground to reduce the drive current of the voltage output test circuit and increase the read-out voltage of the output terminal, so that the read-out voltage of the output terminal remains in the tolerable error range.

In addition, the voltage drop, between the output terminal and the ground, caused by the leakage current between the output terminal and the ground also changes with the resistance between the output terminal and the ground. If the resistance between the output terminal and the ground decreases, the voltage drop, between the output terminal and the ground, caused by the leakage current between the output terminal and the ground also decreases, thereby reducing impact caused by the leakage current to the read-out voltage of the output terminal. As a result, the read-out voltage of the output terminal Vout remains in the tolerable error range, and the accuracy of the read-out voltage is improved.

FIG.2is another circuit diagram of a voltage output test circuit according to some embodiments of this invention. As shown inFIG.2, the voltage output test circuit includes a first voltage divider unit201, a second voltage divider unit202, and a third voltage divider unit203.

The first voltage divider unit201includes a first terminal and a second terminal, where the first terminal of the first voltage divider unit201is electrically connected to a test power supply Vtest, and the second terminal of the first voltage divider unit201is electrically connected to an output terminal Vout. The first voltage divider unit201is a resistor unit, which may include a plurality of sub-resistors connected in series, a plurality of sub-resistors connected in parallel, or some sub-resistors connected in series and some sub-resistors connected in parallel. For example, in this embodiment, the first voltage divider unit201includes two sub-resistors R1and R2that are connected in series. One terminal of the sub-resistor R1is used as the first terminal of the first voltage divider unit201, and is electrically connected to the test power supply Vtest. The other terminal of the sub-resistor R1is electrically connected to one terminal of the sub-resistor R2. The other terminal of the sub-resistor R2is used as the second terminal of the first voltage divider unit201, and is electrically connected to the output terminal Vout. The output terminal Vout is configured to output a read-out voltage. In some embodiments, resistances of the sub-resistor R1and the sub-resistor R2are the same. In some other embodiments, the resistances of the sub-resistor R1and the sub-resistor R2may alternatively be different.

In this embodiment, the first voltage divider unit201is connected to the test power supply Vtest through a switch unit. The switch unit includes a PMOS transistor MP1. When the voltage output test circuit needs to work, a signal En is enabled to control the PMOS transistor to get connected, so that the first voltage divider unit201is electrically connected to the test power supply Vtest. When the voltage output test circuit does not need to work, the signal En is enabled to control the PMOS transistor to get disconnected, so that the first voltage divider unit201is disconnected from the test power supply Vtest.

The second voltage divider unit202includes a first terminal and a second terminal, where the first terminal of the second voltage divider unit202is connected to a ground Vss, and the second terminal of the second voltage divider unit202is electrically connected to the output terminal Vout. In this embodiment, the second voltage divider unit202is a resistor unit, which may include a plurality of sub-resistors connected in series, a plurality of sub-resistors connected in parallel, or some sub-resistors connected in series and some sub-resistors connected in parallel. For example, in this embodiment, the second voltage divider unit202includes one sub-resistor R3. One terminal of the sub-resistor R3is used as the second terminal of the second voltage divider unit202, and is electrically connected to the output terminal Vout. The other terminal of the sub-resistor R3is used as the first terminal of the second voltage divider unit202, and is configured to connect to the ground Vss. In some embodiments, a resistance of the sub-resistor R3is the same as the resistance of the sub-resistor R1and the resistance of the sub-resistor R2. In some other embodiments, the resistance of the sub-resistor R3may alternatively be different from the resistance of the sub-resistor R1and the resistance of the sub-resistor R2, or may be the same as the resistance of either the sub-resistor R1or the sub-resistor R2.

The third voltage divider unit203is configured to adjust a resistance between the output terminal Vout and the ground Vss. The third voltage divider unit230is connected in parallel between the output terminal Vout and the ground Vss. In this embodiment, the third voltage divider unit203and the second voltage divider unit202are connected in parallel, so that a resistance between the output terminal Vout and the ground Vss can be reduced, and a drive current of the voltage output test circuit is increased, and impact caused by a leakage current between the output terminal Vout and the ground Vss to a read-out voltage of the output terminal Vout is reduced.

In some embodiments, the third voltage divider unit203is a fixed resistor R4, which can reduce the resistance between the output terminal Vout and the ground Vss to a predetermined value. One terminal of the fixed resistor R4is used as a second terminal of the third voltage divider unit203, and is electrically connected to the output terminal Vout. The other terminal of the resistor fixed R4is used as a first terminal of the third voltage divider unit203, and is configured to connect to the ground Vss. A resistance of the resistor fixed R4may be set based on a value of a leakage current, so that a read-out voltage of the output terminal Vout remains in a tolerable error range. In some embodiments, resistances of the resistor fixed R4and the sub-resistor R3are the same. In some other embodiments, the resistance of the fixed resistor R4may alternatively be greater than or equal to the resistance of the sub-resistor R3.

In another embodiment of this invention, the third voltage divider unit203is a variable resistor, which can change the resistance between the output terminal Vout and the ground Vss based on the value of the leakage current, so that the read-out voltage of the output terminal Vout remains in the tolerable error range. For example, refer toFIG.3, which is a circuit diagram of a voltage output test circuit according to some embodiments of this invention. The difference betweenFIG.3andFIG.2is that the third voltage divider unit203is a variable resistor R5. When the leakage current between the output terminal Vout and the ground Vss increases, the resistance of the third voltage divider unit203is reduced; and when the leakage current between the output terminal Vout and the ground Vss decreases, the resistance between the third voltage divider unit203is increased, so that the read-out voltage of the output terminal Vout remains in the tolerable error range. In some embodiments, the variable resistor includes a plurality of resistors connected in parallel, and a resistance of the variable resistor is changed by changing a quantity of resistors connected in parallel.

In some embodiments, the third voltage divider unit203and the second voltage divider unit202are connected in parallel, and work together to adjust the resistance between the output terminal Vout and the ground Vss. In another embodiment of this invention, either the second voltage divider unit202or the third voltage divider unit203may be electrically connected to the output terminal Vout to adjust the resistance between the output terminal and the ground.

For example, refer toFIG.4, which is yet another circuit diagram of a voltage output test circuit according to some embodiments of this invention. The difference betweenFIG.4andFIG.2is that either the second voltage divider unit202or the third voltage divider unit203can be electrically connected to the output terminal Vout. Specifically, the third voltage divider unit203is connected in parallel between the output terminal Vout and the ground Vss. Either the second voltage divider unit202or the third voltage divider unit203can be electrically connect to the output terminal Vout based on the value of the leakage current, so that the read-out voltage of the output terminal Vout remains in the tolerable error range.

The third voltage divider unit203includes a first terminal and a second terminal, where the first terminal of the third voltage divider unit203is configured to connect to the ground Vss, and the second terminal of the third voltage divider unit203is electrically connected to the output terminal Vout. A resistance threshold of the third voltage divider unit203is less than a resistance of the second voltage divider unit202. When the leakage current between the output terminal Vout and the ground Vss increases, the third voltage divider unit203is electrically connected to the output terminal Vout; and when the leakage current between the output terminal Vout and the ground Vss decreases, the second voltage divider unit202is electrically connected to the output terminal Vout, so that the read-out voltage of the output terminal Vout remains in the tolerable error range.

In some embodiments, the second voltage divider unit202and the third voltage divider unit203are separately electrically connected to the output terminal Vout through a switch unit. The switch unit may be a transistor. For example, the second voltage divider unit202is electrically connected to the output terminal Vout through a PMOS transistor MP2, and the third voltage divider unit203is electrically connected to the output terminal Vout through a PMOS transistor MP3. When the leakage current between the output terminal Vout and the ground Vss increases, the PMOS transistor MP2is disconnected to cut off the electrical connection between the second voltage divider unit202and the output terminal Vout, and the PMOS transistor MP3is connected to implement the electrical connection between the third voltage divider unit203and the output terminal Vout; and when the leakage current between the output terminal Vout and the ground Vss decreases, the PMOS transistor MP2is connected to implement the electrical connection between the second voltage divider unit202and the output terminal Vout, and the PMOS transistor MP3is disconnected to cut off the electrical connection between the third voltage divider unit203and the output terminal Vout, so that the read-out voltage of the output terminal Vout remains in the tolerable error range.

In some embodiments, the third voltage divider unit203includes one unit, in other words, the third voltage divider unit203is electrically connected to the output terminal Vout as a whole. However, in another embodiment of this invention, the third voltage divider unit203includes at least two voltage divider sub-units, each voltage divider sub-unit is connected to the output terminal Vout and the ground Vss, resistances of the at least two voltage divider sub-units are different, and one of the at least two voltage divider sub-units can be electrically connected to the output terminal Vout.

For example, refer toFIG.5, which is yet another circuit diagram of a voltage output test circuit according to some embodiments of this invention. The third voltage divider unit203includes two voltage divider sub-units, which are a first voltage divider sub-unit203A and a second voltage divider sub-unit203B. The first voltage divider sub-unit203A and the second voltage divider sub-unit203B are connected in parallel, and are connected to the output terminal Vout and the ground Vss. Either the first voltage divider sub-unit203A or the second voltage divider sub-unit203B can be electrically connected to the output terminal Vout.

Resistances of the first voltage divider sub-unit203A and the second voltage divider sub-unit203B are different. For example, in this embodiment, the resistance of the first voltage divider sub-unit203A is less than the resistance of the second voltage divider sub-unit203B, and the resistances of both the first voltage divider sub-unit203A and the second voltage divider sub-unit203B are less than the resistance of the second voltage divider unit202. In some embodiments, the resistance of the second voltage divider unit202, the resistance of the second voltage divider sub-unit203B, and the resistance of the first voltage divider sub-unit203A may be reduced in equal proportions. For example, the second voltage divider unit202includes a sub-resistor R3, and a resistance thereof is R; the second voltage divider sub-unit203B includes a sub-resistor R6, and a resistance thereof is R/2; and the first voltage divider sub-unit203A includes a sub-resistor R7, and a resistance thereof is R/4, to effectively reduce the impact caused by the leakage current on the read-out voltage of the output terminal Vout.

In some embodiments, the first voltage divider sub-unit203A and the second voltage divider sub-unit203B are separately electrically connected to the output terminal Vout through a switch unit, so that either the first voltage divider sub-unit203A or the second voltage divider sub-unit203B is electrically connected to the output terminal Vout.

In another embodiment of this invention, the third voltage divider unit203may further include three or more voltage divider sub-units. A principle thereof is the same as that ofFIG.5, and details are not described herein again.

In some embodiments of this invention, the first voltage divider unit201is a variable resistor; and by changing a resistance of the first voltage divider unit201, a ratio of the resistance of the first voltage divider unit201to the resistance between the output terminal Vout and the ground Vss can be equal to a predetermined value. Specifically, when the resistance between the output terminal Vout and the ground Vss decreases, the resistance of the first voltage divider unit201is reduced, so that the ratio of the resistance of the first voltage divider unit201to the resistance between the output terminal Vout and the ground Vss is equal to the predetermined value; and when the resistance between the output terminal Vout and the ground Vss increases, the resistance of the first voltage divider unit201is increased, so that the ratio of the resistance of the first voltage divider unit201to the resistance between the output terminal Vout and the ground Vss is equal to the predetermined value. Therefore, when a drive current increases, it is further ensured that the read-out voltage of the output terminal Vout remains in the tolerable error range, improving the stability of the read-out voltage.

For example, still refer toFIG.5, the first voltage divider unit201is a variable resistor R8. In this case, when the output terminal Vout is connected to the ground Vss through the second voltage divider unit202, the first voltage divider unit201is a first resistance; when the output terminal Vout is connected to the ground Vss through the second voltage divider sub-unit203B, the first voltage divider unit201is a second resistance; and when the output terminal Vout is connected to the ground Vss through the first voltage divider sub-unit203A, the first voltage divider unit201is a third resistance. The first resistance is greater than the second resistance, and the second resistance is greater than the third resistance.

Some embodiments of this invention further provides a voltage output test circuit.FIG.6is yet another circuit diagram of the voltage output test circuit according to some embodiments of this invention. The voltage output test circuit includes a first branch300and a second branch310.

The first branch300includes a first voltage divider unit201and a second voltage divider unit202.

The first voltage divider unit201includes a first terminal and a second terminal, where the first terminal of the first voltage divider unit201is electrically connected to a test power supply Vtest, and the second terminal of the first voltage divider unit201is electrically connected to an output terminal Vout. The first voltage divider unit201is a resistor unit, which may include a plurality of sub-resistors connected in series, a plurality of sub-resistors connected in parallel, or some sub-resistors connected in series and some sub-resistors connected in parallel. In this embodiment, an example in which the first voltage divider unit201includes only one sub-resistor R9is used for description.

The second voltage divider unit202includes a first terminal and a second terminal, where the first terminal of the second voltage divider unit202is connected to a ground Vss, and the second terminal of the second voltage divider unit202is electrically connected to the output terminal Vout. In this embodiment, the second voltage divider unit202is a resistor unit, which may include a plurality of sub-resistors connected in series, a plurality of sub-resistors connected in parallel, or some sub-resistors connected in series and some sub-resistors connected in parallel. In this embodiment, an example in which the second voltage divider unit202includes only one sub-resistor R10is used for description.

The second branch310includes a third voltage divider unit203and a fourth voltage divider unit204.

The third voltage divider unit203includes a first terminal and a second terminal, the first terminal of the third voltage divider unit203is connected to the ground Vss, and the second terminal of the third voltage divider unit203is electrically connected to the output terminal Vout. In this embodiment, the third voltage divider unit203is a resistor unit, which may include a plurality of sub-resistors connected in series, a plurality of sub-resistors connected in parallel, or some sub-resistors connected in series and some sub-resistors connected in parallel. In this embodiment, an example in which the third voltage divider unit203includes only one sub-resistor R11is used for description. A resistance of the third voltage divider unit203is less than a resistance of the second voltage divider unit202. For example, a resistance of the sub-resistor R11is less than a resistance of the sub-resistor R10.

The fourth voltage divider unit204includes a first terminal and a second terminal, where the first terminal of the fourth voltage divider unit204is electrically connected to a test power supply Vtest, and the second terminal of the fourth voltage divider unit204is electrically connected to an output terminal Vout. The fourth voltage divider unit204is a resistor unit, which may include a plurality of sub-resistors connected in series, a plurality of sub-resistors connected in parallel, or some sub-resistors connected in series and some sub-resistors connected in parallel. In this embodiment, an example in which the fourth voltage divider unit204includes only one sub-resistor R12is used for description.

In some embodiments, either the first branch300or the second branch310can be electrically connected to the test power supply Vtest and the voltage output terminal Vout based on a value of a leakage current between the output terminal Vout and the ground Vss. For example, when the leakage current between the output terminal Vout and the ground Vss increases, the second branch310is electrically connected to the test power supply Vtest and the voltage output terminal Vout. The resistance of the third voltage divider unit203of the second branch310is less than the resistance of the second voltage divider unit202of the first branch300. Therefore, when the second branch310is electrically connected to the test power supply Vtest and the voltage output terminal Vout, the resistance between the output terminal Vout and the ground Vss is reduced, so that a read-out voltage of the output terminal Vout remains in a tolerable error range. When the leakage current between the output terminal Vout and the ground Vss decreases, the first branch is electrically connected to the test power supply Vtest and the voltage output terminal Vout, and the resistance between the output terminal Vout and the ground Vss is increased, so that the read-out voltage of the output terminal Vout remains in the tolerable error range.

In this embodiment, a ratio of the resistance of the first voltage divider unit201to the resistance of the fourth voltage divider unit204is equal to a ratio of the resistance of the second voltage divider unit202to a resistance of the third voltage divider unit204, that is, a ratio of the resistance of the sub-resistor R9to the resistance of the sub-resistor R10is equal to a ratio of the resistance of the sub-resistor R12to the resistance of the sub-resistor R11. Therefore, when the drive current increases, it is further ensured that the read-out voltage of the output terminal Vout remains in the tolerable error range, improving the stability of the read-out voltage.

In this embodiment, the first voltage divider unit201and the fourth voltage divider unit204are separately connected to the test power supply Vtest through a switch unit. The output test circuit further includes a logic gate circuit, and the logic gate circuit is configured to provide a control signal of the switch unit. The switch unit may be a transistor. In this embodiment, the logic gate circuit is used to reduce a quantity of control signals, reducing data bits occupied by the control signals, and avoiding greatly affecting a storage capacity of a memory.

Specifically, still refer toFIG.6. The first voltage divider unit201is connected to the test power supply Vtest through a PMOS transistor MP6. The logic gate circuit is configured to provide a control signal of the PMOS transistor MP6. The logic gate circuit includes an OR gate circuit. The fourth voltage divider unit204is connected to the test power supply Vtest through a PMOS transistor MP7. The logic gate circuit is configured to provide a control signal of the PMOS transistor MP7. The logic gate circuit includes an OR gate circuit. By applying two complementary enable signals EnVilDiv and EnVilDivf, either the first branch300or the second branch310is electrically connected to the test power supply Vtest and the voltage output terminal Vout.

Still refer toFIG.6. To reduce the power consumption, the first branch300and the second branch310are separately connected to the output terminal Vout through a switch unit. For example, the first branch300is connected to the output terminal Vout through an NMOS transistor MN1, and the second branch310is connected to the output terminal Vout through an NMOS transistor MN2. A control signal of the NMOS transistor MN1may be the complementary signal EnVilDivf for the enable signal EnVilDiv. A control signal of the NMOS transistor MN2may be may be the complementary signal EnVilDiv for the enable signal EnVilDivf.

In some embodiments, the fourth voltage divider unit204is connected to the test power supply Vtest through a PMOS transistor MP7. However, in some embodiments of this invention, as shown inFIG.7, the fourth voltage divider unit204is connected to the test power supply Vtest through an NMOS transistor MN3. A drive capability of an NMOS transistor is stronger than that of a PMOS transistor when they are of the same size. Therefore, a voltage drop lost on the NMOS transistor is smaller, further maintaining the stability of the read-out voltage of the output terminal Vout. It can be understood that the logic gate circuit configured to provide the control signal for the NMOS transistor MN3is an OR gate circuit, and an enable signal thereof is the enable signal EnVilDiv. In this embodiment, the logic gate circuit is used to reduce a quantity of control signals, reducing data bits occupied by the control signals, and avoiding greatly affecting a storage capacity of a memory.

In some embodiments the voltage output test circuit includes one second branch. However, in another embodiment of this invention, the voltage output test circuit includes a plurality of second branches, where resistances of third voltage divider units of the different second branches are different and are all less than the resistance of the second voltage divider unit, and one of the first branch and the plurality of second branches can be electrically connected to the test power supply and the voltage output terminal.

Specifically, refer toFIG.8, which is yet another circuit diagram of a voltage output test circuit according to some embodiments of this invention. In this embodiment, the voltage output test circuit includes two second branches, which are a second branch310A and a second branch310B. Resistances of a third voltage divider unit203C of the second branch310A and a third voltage divider unit203D of the second branch310B are different, and are both less than a resistance of a second voltage divider unit202. One of the first branch300, the second branch310A, and the second branch310B can be electrically connected to the test power supply Vtest and the voltage output terminal Vout based on a leakage current between an output terminal Vout and a ground Vss.

In this embodiment, a ratio of a resistance of a fourth voltage divider unit204A to a resistance of a third voltage divider unit203C of the second branch310A is equal to a ratio of a resistance to a resistance of a fourth voltage divider unit204B to a third voltage divider unit203D of the second branch310B, to improve the stability of the read-out voltage of the output terminal Vout.

The first voltage divider unit201is connected to the test power supply Vtest through a PMOS transistor MP6. The logic gate circuit is configured to provide a control signal of the PMOS transistor MP6. The logic gate circuit includes an OR gate circuit. The fourth voltage divider unit204A is connected to the test power supply Vtest through a PMOS transistor MP7. The logic gate circuit is configured to provide a control signal of the PMOS transistor MP7. The logic gate circuit includes an OR gate circuit. The fourth voltage divider unit204B is connected to the test power supply Vtest through a PMOS transistor MP7. The logic gate circuit is configured to provide a control signal of the PMOS transistor MP8. The logic gate circuit includes an OR gate circuit.

By applying enable signals EnVilDiv and EnVilDivf, EnVilDiv1 and EnVilDiv1f enable one of the first branch300, the second branch310A, and the second branch310B to electrically connect to the test power supply Vtest and the voltage output terminal Vout.

In some embodiments, to further reduce the power consumption, a control signal of an NMOS transistor MN2is applied by the logic gate circuit to a control terminal of the NMOS transistor MN2, and a control signal of an NMOS transistor MN3is applied by the logic gate circuit to a control terminal of the NMOS transistor MN3. Specifically, the control signal of the NMOS transistor MN2and the control signal of the NMOS transistor MN3are applied by an OR gate circuit to the control terminals of the NMOS transistor MN2and the NMOS transistor MN3. Control signals of the OR gate circuit include an enable signal EnVilDiv, an enable signal EnVilDivf, an enable signal EnVilDiv1, and an enable signal EnVilDiv1f.

Still refer toFIG.8. In this embodiment, the output test circuit further includes a feedback unit320, where the feedback unit320is separately electrically connected to the first branch300, the second branches, and a voltage output terminal Vout, and is configured to selectively drive, based on a value of a leakage current or a voltage of the output terminal Vout, the first branch300or the second branches to electrically connect to the test power supply and the voltage output terminal Vout. Specifically, in this embodiment, the feedback unit320is separately electrically connected to the first branch300, the second branch310A, the second branch310B, and the voltage output terminal Vout. The feedback unit320can generate enable signals EnVilDiv0 and EnVilDiv1 based on the value of the leakage current or the voltage of the output terminal Vout, so that one of the first branch300, the second branch310A, and the second branch310B is electrically connected to the test power supply and the voltage output terminal Vout.

According to the voltage output test circuit provided in the embodiments of this invention, the third voltage divider unit can adjust a drive current of the voltage output test circuit by adjusting the resistance between the output terminal and the ground, to reduce impact caused by a leakage current between the output terminal and the ground to the read-out voltage of the output terminal, so that the read-out voltage of the output terminal remains in a tolerable error range, improving the accuracy of the read-out voltage of the output terminal Vout, and improving the reliability of a chip test. The voltage output test circuit provided in the embodiments of this invention can be configured to test a memory, such as an LPDDR 5.

An embodiment of this invention further provides a voltage divider output circuit using the foregoing voltage output test circuit.FIG.9is yet another schematic circuit diagram of a voltage divider output circuit according to some embodiments of this invention. The voltage divider output circuit includes a plurality of voltage output test circuits. In the figure, voltage output test circuits900,910, and920are illustrated as examples. Enable signals of the voltage output test circuits900,910, and920are respectively EnF1, EnF2, and EnF3. The enable signal merely represents that the voltage output test circuit corresponding to the enable signal has an enable signal, but does not limit the voltage output test circuit to having only one enable signal. One of the voltage output test circuits902,910, and920can be electrically connected to a voltage output terminal Vout. In this embodiment, one of the voltage output test circuits902,910, and920is electrically connected to the voltage output terminal Vout by controlling switch units by using the enable signals En1, En2, and EnF3. The switch units include an NMOS transistor MN4, an NMOS transistor MN5, and an NMOS transistor MN6.

All the voltage output test circuits are electrically connected to the voltage output terminal Vout through a connection circuit940. In this embodiment, the connection circuit940includes a first connection branch940A and a second connection branch940B. Either the first connection branch940A or the second connection branch940B can be electrically connected to the voltage output test circuit and the voltage output terminal Vout.

The first connection branch940A includes a first terminal and a second terminal, where the first terminal of the first connection branch940A is electrically connected to an output terminal of the voltage output test circuit, and the second terminal of the first connection branch940A is electrically connected to the voltage output terminal Vout. The first connection branch940A includes an NMOS transistor NM7. One terminal of the NMOS transistor NM7 is electrically connected to the output terminal of the voltage output test circuit, and the other terminal of the NMOS transistor NM7 is electrically connected to the voltage output terminal Vout. An enable signal EnAmpF is used as a control signal of the NMOS transistor NM7, and controls connection and disconnection of the NMOS transistor MN7, to control whether the voltage output test circuit is electrically connected to the voltage output terminal Vout through the first connection branch.

The second connection branch940B and the first connection branch940A are connected in parallel. The second connection branch940B includes one feedback amplifier950to reduce impact caused by a leakage current of the output terminal Vout to a read-out voltage. When a driving force of the feedback amplifier950is big enough, a value of the read-out voltage is not affected by the leakage current of the output terminal Vout.

In this embodiment, the second connection branch940B includes a switch unit. The switch unit is an NMOS transistor MN8. The NMOS transistor MN8, disposed between the voltage output test circuit and the feedback amplifier950, is used as a switch of the second connection branch940B, and controls, by using an enable signal EnAmp, whether the voltage output test circuit is electrically connected to the voltage output terminal Vout through the second connection branch940B.

In this embodiment, the second connection branch940B further includes an NMOS transistor MN9. The NMOS transistor MN9is disposed between the feedback amplifier950and the output terminal Vout, and controls, by using an enable signal EnAmp, whether the voltage output test circuit is electrically connected to the voltage output terminal Vout through the second connection branch940B, to reduce the power consumption.

According to the voltage divider output circuit provided in this embodiment of this invention, the impact caused by the leakage current to the read-out voltage of the output terminal is reduced by using the voltage output test circuit, improving the accuracy of the read-out voltage. In addition, according to the voltage divider output circuit provided in this embodiment of this invention, the impact caused by the leakage current of the output terminal Vout to the read-out voltage is further reduced by using a gain function of a feedback amplifier.

An embodiment of this invention further provides a memory, including the voltage output test circuit described above. The memory may be a dynamic random access memory satisfying the LPDDR5 standard. The memory can provide an accurate read-out voltage, improving the chip test accuracy.

The foregoing descriptions are merely preferable implementations of this invention. It should be noted that a person of ordinary skill in the art may further make several improvements and modifications without departing from the principle of this invention, and these improvements and modifications shall also be considered as falling within the protection scope of this invention.