Patent ID: 12193270

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Technical solutions of the present disclosure are clearly and completely described below with reference to the accompanying drawings in the implementations of the present disclosure. Apparently, the described implementations are merely some implementations rather than all the implementations of the present disclosure. All other implementations obtained by a person of ordinary skill in the art based on the implementations of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

In the present disclosure, unless otherwise explicitly stipulated and defined, that a first feature is “above” or “under” a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but in contact by using other features therebetween. In addition, that the first feature is “above”, “over”, or “on” the second feature may include that the first feature is directly above and obliquely above the second feature, or may merely indicate that the horizontal height of the first feature is higher than that of the second feature. That the first feature is “below”, “under”, and “beneath” the second feature may include that the first feature is right below the second feature and at an inclined bottom of the second feature, or may merely indicate that the horizontal position of the first feature is lower than that of the second feature. In addition, terms “first” and “second” are used merely for the purpose of description, and shall not be construed as indicating or implying relative importance or implying a quantity of indicated technical features. Therefore, features defining “first” and “second” may explicitly or implicitly include one or more such features.

The present disclosure provides a flexible display panel and a flexible array substrate. The display panel in the embodiments of the present disclosure can be used for mobile phones, tablet computers, e-readers, electronic display screens, notebook computers, mobile phones, augmented reality (AR)\virtual reality (VR) devices, media players, wearable devices, digital cameras, in-vehicle navigation devices, etc.

The display panel can be an Organic Light-emitting Diode (OLED) display panel, a Quantum Dot Light-emitting Diode (QLED) display panel, or a Micro Light-emitting Diode (Micro-LED) display panel, a Mini Light-emitting Diode (Mini-LED) display panel, or a liquid crystal display panel.

Referring toFIG.1andFIG.2, the flexible display panel1includes a flexible array substrate100. The flexible array substrate100includes a flexible base10and a thin film transistor20arranged on the flexible base10. The flexible array substrate100may further include a buffer layer BL arranged between the flexible base10and the thin film transistor20.

A material of the flexible base10is selected from one of polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyarylate (PAR), polycarbonate (PC), polyetherimide (PEI), and polyethersulfone (PES).

The thin film transistor20includes an active layer AL, a gate electrode GE, a gate electrode insulation layer GI, a source electrode SE, a drain electrode DE, an interlayer insulation layer IL, and a passivation layer PV. The active layer AL is arranged on the flexible base10; the gate electrode GE is arranged on one side of the active layer AL away from the flexible base10; the gate electrode insulation layer GI is arranged between the gate electrode GE and the active layer AL; the source electrode SE and drain electrode DE are arranged on sides of the gate electrode GE and the active layer AL away from flexible base10; the interlayer insulation layer IL is arranged among the source electrode SE, the drain electrode DE, and the active layer AL; and the passivation layer PV is covered on sides of the source electrode SE and the drain electrode DE away from the flexible base10. The source electrode SE and the drain electrode DE are respectively connected with two ends of the active layer AL through contact holes formed in the interlayer insulation layer IL.

Open pores OP are formed in the active layer, and the open pores OP penetrate through at least one part of the active layer AL. The open pore OP may be a through hole or a blind hole, that is, the open pore OP may completely penetrate through the active layer AL, or may penetrate through a part of the active layer AL. By means of forming the open pores OP in the active layer AL, when a bending force is applied to the flexible display panel1, stress on the thin film transistor20is concentrated in the open pores OP, which can effectively reduce the damage of bending to the thin film transistor20. Even if a crack is generated in the active layer AL due to extremely high bending force, the open pores OP in the active layer AL can also effectively prevent spreading of the crack and protect the thin film transistor20.

The active layer AL includes a channel region AL1, a source electrode connecting part AL2, and a drain electrode connecting part AL3. The source electrode connecting part AL2and the drain electrode connecting part AL3are located on two opposite sides of the channel region AL1. The source electrode SE is connected with the source electrode connecting part AL2, and the drain electrode DE is connected with the drain electrode connecting part AL3.

The open pores OP may be located in at least one of the channel region AL1, the source electrode connecting part AL2, and the drain electrode connecting part AL3. When the open pores OP are located in at least one of the source electrode connecting part AL2and the drain electrode connecting part AL3, at least one of the source electrode SE and the drain electrode DE extends into the open pores OP to be connected with the active layer AL. In this implementation, the open pores OP are located in the source electrode connecting part AL2and the drain electrode connecting part AL3. The source electrode SE extends into the open pores OP of the source electrode connecting part AL2to be connected with the source electrode connecting part AL2, and the drain electrode DE extends into the open pores OP of the drain electrode connecting part AL3to be connected with the drain electrode connecting part AL3. When the open pores OP are located in the channel region AL1, a film layer covering one side of the channel region AL1away from the flexible base10can extend into the open pores OP to fill the open pores OP. The film layer covering the side of the channel region AL1away from the flexible base10is, for example, a gate electrode insulation layer in a top-gate transistor, and is, for example, a source electrode and drain electrode, an ohmic contact layer, or a channel protection layer in a bottom-gate transistor. The setting of the open pores OP can enlarge overlap areas between the active layer AL and the source electrode SE as well as between the active layer AL and the drain electrode DE, reduce the contact resistance, and improve the device performance of the thin film transistor20.

The number and arrangement of the open pores OP are not limited in the present disclosure. Alternatively, in this implementation, 16 open pores OP may be respectively formed in the source electrode connecting part AL2and the drain electrode connecting part AL3. The 16 open pores OP in the source electrode connecting part AL2are arranged in a matrix, and the 16 open pores OP in the drain electrode connecting part AL3are also arranged in a matrix. Further, the open pores OP in the source electrode connecting part AL2and the open pores OP in the drain electrode connecting part AL3can be disposed symmetrically with respect to the channel region AL1, which can avoid damage to the active layer due to stress relief dislocation. Specifically, the symmetrical arrangement with respect to the channel region AL1means that when the channel region AL1is a symmetrical pattern, the open pores OP in the source electrode connecting part AL2and the open pores OP in the drain electrode connecting part AL3are symmetrical with respect to a symmetry axis O of the channel region ALL When the channel region AL1is not a standard symmetrical pattern, the open pores OP in the source electrode connecting part AL2and the open pores OP in the drain electrode connecting part AL3may be disposed symmetrically with respect to a center line of the channel region AL1serving as the symmetry axis. The shape of the open pore OP may be circular or square. In order to prevent the open pore OP from being too large and affecting the function of the active layer AL, an area of the open pore OP may be 0.1 square micrometers to 20 square micrometers. Alternatively, when the number of the open pore OP is one, the area of the open pore OP may be 20 square micrometers, for example, a rectangular hole of 4 μm×5 μm.

In this implementation, a self-alignment type top-gate thin film transistor will be described as an example. It can be understood that, in other implementations of the present disclosure, the thin film transistor may also be a bottom-gate thin film transistor.

It should be noted that although only one thin film transistor20is shown in the figure, the flexible array substrate100may include a plurality of thin film transistors20. A drive circuit of an OLED display panel may be 2T1C, 3T1C, 5T1C, or 7T1C. According to different structures of a pixel drive circuit, the type and number of thin film transistors20included in the flexible array substrate100may be different. In the present disclosure, open pores OP may be formed in the active layers AL of part of the thin film transistors20, or open pores OP may be formed in the active layers AL of all the thin film transistors20, or open pores OP may also be selectively formed in the thin film transistors20in a display region and/or a non-display region.

The flexible display panel1further includes a passivation layer PLN, a first electrode200, a pixel defining layer300, a light-emitting layer400, and a second electrode500. The passivation layer PLN covers the flexible array substrate100; the first electrode200is arranged on one side of the passivation layer PLN away from the flexible array substrate100; the pixel defining layer300is arranged on one side of the first electrode200away from the flexible array substrate100; an opening300ais formed in the pixel defining layer300; the light-emitting layer400is arranged in the opening300a; and the second electrode500covers the pixel defining layer300and the light-emitting layer400. The first electrode200may be an anode and the second electrode500may be a cathode; or the first electrode200may be a cathode and the second electrode500may be an anode. A first via VIA1is formed in the passivation layer PV, and a second via VIA2is formed in an organic flat layer30. The second via VIA2is in communication with the first via VIA1. The first electrode200overlaps the thin film transistor through the second via hole VIA2and the first via hole VIA1.

Referring toFIG.3, a difference between the flexible display panel of the second implementation of the present disclosure and the flexible display panel of the first implementation is as follows.

The thin film transistor20further includes an ohmic contact layer OL, and the ohmic contact layer OL includes a first ohmic contact part OL1and a second ohmic contact part OL2. The first ohmic contact part OL1is located between the source electrode connecting part AL2and the source electrode SE; the second ohmic contact part OL2is located between the drain electrode connecting part AL3and the drain electrode DE; and the first ohmic contact part OL1and the second ohmic contact part OL2extend into the open pores OP to be connected with the active layer AL.

It can be understood that in this implementation, the open pores OP are formed in both the source electrode connecting part AL2and the drain electrode connecting part AL3. In other implementation, the open pores OP may be formed in one of the source electrode connecting part AL2and the drain electrode connecting part AL3.

Referring toFIG.4andFIG.5, a difference between the flexible display panel of the third implementation of the present disclosure and the flexible display panel of the first implementation is as follows.

The open pores OP are located not only in the source electrode connecting part AL2and the drain electrode connecting part AL3, but also in the channel region AL1. The gate electrode insulation layer GI covers the channel region AL1, and the gate electrode insulation layer GI fills the open pores OP. Further, the open pores OP in the channel region AL1are disposed symmetrically, which can avoid damage to the active layer due to stress relief dislocation. Specifically, the symmetrical arrangement with respect to the channel region AL1means that when the channel region AL1is a symmetrical pattern, the open pores OP in the channel region AL1are symmetrical with respect to the symmetry axis O of the channel region AL′. When the channel region AL1is not a standard symmetrical pattern, the open pores OP in the channel region AL1may be arranged approximately symmetrically with respect to the center line of the channel region AL1serving as the symmetry axis.

It can be understood that although the third implementation discloses that the open pores OP are formed in the channel region AL1, the source electrode connecting part AL2, and the drain electrode connecting part AL3. However, in other implementations of the present disclosure, the open pores OP are formed in the channel region AL1only, and no open pore OP is formed in the source electrode connecting part AL2and the drain electrode connecting part AL3.

Referring toFIG.6, a difference between the flexible display panel of the fourth implementation of the present disclosure and the flexible display panel of the first implementation is as follows.

The thin film transistor20may also be a bottom-gate thin film transistor. The thin film transistor20includes a gate electrode GE, a gate electrode insulation layer GI, an active layer AL, a source electrode SE, a drain electrode DE, and a passivation layer PV. The gate electrode GE is arranged on the flexible base10; the active layer AL is arranged on one side of the gate electrode GE away from the flexible base10; the gate electrode insulation layer GI is arranged between the gate electrode GE and the active layer AL and covers the gate electrode GE and the flexible base10; the source electrode SE and the drain electrode DE are arranged on one side of the active layer AL away from the gate electrode GE and are respectively connected with two ends of the active layer AL; and the passivation layer PV covers sides of the source electrode SE and the drain electrode DE away from the active layer AL.

What is the same as that of the first implementation, the open pores OP may be located in the source electrode connecting part AL2and the drain electrode connecting part AL3. The source electrode SE extends into the open pores OP of the source electrode connecting part AL2to be connected with the source electrode connecting part AL2, and the drain electrode DE extends into the open pores OP of the drain electrode connecting part AL3to be connected with the drain electrode connecting part AL3.

The present disclosure further provides a method for manufacturing a flexible display panel, which is used for manufacturing the above-mentioned flexible display panel. As shown inFIG.7(a)toFIG.7(h), the method for manufacturing the flexible display panel includes the following steps:

Step101: referring toFIG.7(a), a flexible base10is provided.

A material of the flexible base10is selected from one or more of polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyarylate (PAR), polycarbonate (PC), polyetherimide (PEI), and polyethersulfone (PES).

Step102: a buffer layer BL is deposited. A material of the buffer layer may be a single layer of silicon nitride, a single layer of silicon oxide, or a two-layer or more-layer film layer of silicon oxide, silicon nitride and silicon oxide. A thickness of the buffer layer is 1000 angstroms to 5000 angstroms.

Step103: referring toFIG.7(b)andFIG.7(c), a semiconductor material layer CL is deposited. A material of the semiconductor material layer CL may be IGZO, ITZO or IGZTO. A thickness of the semiconductor material layer CL is 100 angstroms to 1000 angstroms. The semiconductor material layer CL is divided into a channel region CL1, a source electrode overlap region CL2, and a drain electrode overlap region CL3. Open pores OP are respectively formed in the source electrode overlap region CL2and the drain electrode overlap region CL3. The open pores OP in the source electrode connecting part AL2and the open pores OP in the drain electrode connecting part AL3are disposed symmetrically with respect to the channel region AL1. The shape of the open pore OP may be circular or square. In order to prevent the open pore OP from being too large and affecting the function of the active layer, an area of the open pore OP may be 0.1 square micrometers to 20 square micrometers. Alternatively, when the number of the open pore OP is one, the area of the open pore OP may be 20 square micrometers, for example, a rectangular hole of 4 μm×5 μm. Step104: referring toFIG.7(d)andFIG.7(e), a gate electrode insulation material layer (not shown) is deposited on the active layer AL. A material of the gate electrode insulation material layer is silicon oxide with a thickness of 1000 angstroms to 3000 angstroms.

Step105: a gate electrode metal layer (not shown) is deposited on the gate electrode insulation material layer. A material of the gate electrode metal layer may be a single layer of Mo, Al, Cu, Ti and the like, or may be a multilayer metal such as Mo/Al/Mo, Al/Mo, Mo/Cu, and MoTi/Cu, with a thickness of 500 angstroms to 10000 angstroms.

Step106: a photomask is used to define the gate electrode GE and the gate electrode insulation layer GI; wet etching is used to etch the gate electrode metal layer first, and then a gate pattern is used for self-alignment; and the gate electrode insulation layer GI is formed by dry etching.

Step107: the semiconductor material layer without the protection of the gate electrode insulation layer GI is conducted by plasma treatment to form N-doped conductor regions used as a source electrode connecting part AL2and a drain electrode connecting part AL3which are in contact with the source electrode and the drain electrode. The semiconductor material layer below the gate electrode insulation layer GI is not treated and is used as a channel region AL1of a thin film transistor20.

Step108: referring toFIG.7(f), a silicon oxide film is deposited to serve as an interlayer insulation layer IL with a thickness of 3000 angstroms to 10000 angstroms, and contact holes CH of the source electrode, the drain electrode, and the active layer AL are etched in the interlayer insulation layer IL.

Step109: referring toFIG.7(g), a source and drain electrode metal layer is deposited, which has a single-layer or multilayer structure, such as Cu, Al, MoTi/Cu, Ti/Al/Ti, Mo/Al/Mo, MoTi/Cu/MoTi, Mo/Cu/Mo, i/Cu/Ti and the like, and a thickness of the source and drain electrode metal layer is 2000-10000 A; the source electrode SE and drain electrode DE are formed by patterning and are respectively connected with the conducted source electrode connecting part AL2and drain electrode connecting part AL3through the contact holes CH.

Step110: a passivation layer PV is deposited. The passivation layer PV may be a silicon oxide thin film with a thickness of 1000 angstroms to 5000 angstroms.

Step111: referring toFIG.7(h), a first via VIA1is formed in the passivation layer PV.

Step112: an organic photoresist material is deposited to serve as an organic flat layer PLN, and a second via VIA2is formed in the organic flat layer PLN. The second via VIA2is in communication with the first via VIA1. It can be a photoresist layer of different compositions. A thickness of the organic flat layer PLN is 10000 angstroms to 50000 angstroms, and the organic flat layer PLN fills the vias VIA.

Step113: an anode200is deposited. The anode200includes a metal material with high reflectivity, including, but not limited to, ITO/Ag/ITO, IZO/Ag/IZO, ITO/Al/ITO or IZO/Al/IZO, and the anode200overlaps the thin film transistor20through the second via VIA2and the first via VIA1.

Step114: a pixel defining layer300is formed. A thickness of the pixel defining layer300is 10000 angstroms to 20000 angstroms, and an opening300ais defined by a yellow light process.

Step115: a light-emitting layer400is formed in the opening300a.

Step116: a cathode500is formed on the light-emitting layer400and the pixel defining layer300, thus obtaining a complete display panel.

The foregoing specific steps describe the method for manufacturing the flexible display panel of the first implementation of the present disclosure. The manufacturing methods of the flexible display panel of the second implementation to the fourth implementation of the present disclosure can be adjusted in the foregoing manufacturing methods, and the descriptions are omitted herein.

The implementations of the present disclosure are described in detail above. The principles and implementations of the present disclosure are described through specific examples in this specification, and the descriptions of the foregoing implementations are merely intended to help understand the present disclosure. Meanwhile, a person skilled in the art may make modifications to the specific implementations and application scopes according to the ideas of the present disclosure. In conclusion, the content of this specification should not be construed as a limitation to the present disclosure.