Patent ID: 12243843

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Embodiments will be described with respect to embodiments in a specific context, namely integrated circuit packages and methods of forming the same. In various embodiments presented herein, a package comprises a package component mounted on a package substrate. The package component may comprise an optical integrated circuit die attached to a redistribution structure or an interposer. The optical integrated circuit die may comprise an optical coupler, such as an edge coupler. A dam structure may be formed on the redistribution structure or the interposer near an edge of the package component, such that the dam is near the edge coupler of the optical integrated circuit die. The dam prevents an underfill that is formed between the package component and the redistribution structure or the interposer from extending along a sidewall of the optical integrated circuit die and from shielding the edge coupler. An optical glue layer may be formed over the dam and may cover the sidewall of the optical integrated circuit die near the edge coupler. The optical glue layer prevents an encapsulant that encapsulates the optical integrated circuit die from extending along the sidewall of the optical integrated circuit die and from shielding the edge coupler. A solder resist trench may be formed in a solder resist layer over the package substrate near an edge of the package component. The solder resist trench allows an underfill that is formed between the package component and the package substrate to at least partially fill the solder resist trench and prevents the underfill from extending along a sidewall of the package component and from shielding the edge coupler of the optical integrated circuit die that is disposed near the sidewall of the package component. Various embodiments presented herein allow for integration of optical integrated circuit dies comprising edge couplers or grating couplers, achieving high bandwidth with ultra-low power consumption through the edge coupler, extensive integration for co-package optics, and no extra cost for adding the dam.

FIG.1illustrates a cross-sectional view of an integrated circuit die50, in accordance with some embodiments. Integrated circuit dies50will be packaged in subsequent processing to form integrated circuit packages. Each integrated circuit die50may be a logic device (e.g., application-specific integrated circuit (ASIC) die, central processing unit (CPU), graphics processing unit (GPU), microcontroller, etc.), a memory device (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management device (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) device, a sensor device, a micro-electro-mechanical-system (MEMS) device, a signal processing device (e.g., digital signal processing (DSP) die), a front-end device (e.g., analog front-end (AFE) dies), the like, or a combination thereof (e.g., a system-on-a-chip (SoC) die). The integrated circuit die50may be formed in a wafer, which may include different die regions that are singulated in subsequent steps to form a plurality of integrated circuit dies50. The integrated circuit die50includes a semiconductor substrate52, an interconnect structure54, and conductive connectors56.

The semiconductor substrate52may be a substrate of silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate52may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. The semiconductor substrate52has an active or a front-side surface (e.g., the surface facing upward) and an inactive or a backside surface (e.g., the surface facing downward). Devices are at the active surface of the semiconductor substrate52. The devices may be active devices (e.g., transistors, diodes, etc.) and/or passive devices (capacitors, resistors, inductors, etc.). The inactive surface may be free from devices.

The interconnect structure54is over the active surface of the semiconductor substrate52, and is used to electrically connect the devices of the semiconductor substrate52to form an integrated circuit. The interconnect structure54may include one or more dielectric layer(s) and respective metallization layer(s) in the dielectric layer(s). Acceptable dielectric materials for the dielectric layers include low-k dielectric materials such as phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Acceptable dielectric materials for the dielectric layers further include oxides such as silicon oxide or aluminum oxide; nitrides such as silicon nitride; carbides such as silicon carbide; the like; or combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride or the like. Other dielectric materials may also be used, such as a polymer such as polybenzoxazole (PBO), polyimide, a Benzocyclobutene (BCB) based polymer, or the like. The metallization layers may include conductive vias and/or conductive lines to interconnect the devices of the semiconductor substrate52. The metallization layers may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, combinations thereof, or the like. The interconnect structure54may be formed by a damascene process, such as a single damascene process, a dual damascene process, or the like.

Conductive connectors56are formed at the front-side50F of the integrated circuit die50. The conductive connectors56may comprise underbump metallizations (UBMs)56A and solder regions56B over the UBMs56A. The UBMs56A may be conductive pillars, pads, or the like. In some embodiments, the UBMs56A may be formed by forming a seed layer over the interconnect structure54. The seed layer may be a metal layer, which may be a single layer or a composite layer including a plurality of sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the UBMs56A. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may include a metal, such as copper, titanium, tungsten, aluminum, nickel, or the like. Then, the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process. The remaining portions of the seed layer and conductive material form the UBMs56A.

In some embodiments, the UBMs56A may include three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. Other arrangements of materials and layers, such as an arrangement of chrome/chrome-copper alloy/copper/gold, an arrangement of titanium/titanium tungsten/copper, or an arrangement of copper/nickel/gold, may be utilized for the formation of the UBMs56A. Any suitable materials or layers of material that may be used for the UBMs56A are fully intended to be included within the scope of the current application.

The solder regions56B may comprise a solder material and may be formed over the UBMs56A by dipping, printing, plating, or the like. The solder material may comprise, for example, lead-based and lead-free solders, such as Pb-Sn compositions for lead-based solder; lead-free solders including InSb; tin, silver, and copper (SAC) compositions; and other eutectic materials that have a common melting point and form conductive solder connections in electrical applications. For lead-free solder, SAC solders of varying compositions may be used, such as SAC105(Sn 98.5%, Ag 1.0%, Cu 0.5%), SAC305, and SAC405, as examples. Lead-free solders may further include SnCu compounds as well, without the use of silver (Ag). Lead-free solders may also include tin and silver, Sn—Ag, without the use of copper. In some embodiments, a reflow process may be performed, giving the solder regions56B a shape of a partial sphere in some embodiments. In other embodiments, the solder regions56B may have other shapes, such as non-spherical shapes.

In some embodiments, the solder regions56B may be used to perform chip probe (CP) testing on the integrated circuit die50. For example, the solder regions may be solder balls, solder bumps, or the like, which are used to attach a chip probe to the conductive connectors56. Chip probe testing may be performed on the integrated circuit die50to ascertain whether the integrated circuit die50is a known good die (KGD). Thus, only integrated circuit dies50, which are KGDs, undergo subsequent processing and are packaged, and dies which fail the chip probe testing are not packaged. In some embodiments, after testing, the solder regions56B may be removed in subsequent processing steps.

FIG.2illustrates a cross-sectional view of an integrated circuit die60, in accordance with some embodiments. The integrated circuit die60is a stacked device that includes multiple semiconductor substrates52. For example, the integrated circuit die60may be a memory device that includes multiple memory dies such as a hybrid memory cube (HMC) device, a high bandwidth memory (HBM) device, or the like. In such embodiments, the integrated circuit die60includes multiple semiconductor substrates52interconnected by through-substrate vias (TSVs) such as through-silicon vias (not shown). Each of the semiconductor substrates52may (or may not) have a separate interconnect structure.

FIG.3illustrates a cross-sectional view of an integrated circuit die70, in accordance with some embodiments. The integrated circuit die70may be an optical integrated circuit die, such as an optical engine die. The integrated circuit die70may include an electrical integrated circuit (EIC)70A bonded to a photonic integrated circuit (PIC)70B. The EIC70A may comprise a semiconductor substrate52, active and/or passive electric devices on the active side of the semiconductor substrate52, and an interconnect structure54on the active side of the semiconductor substrate52. The EIC70A may be formed in a similar manner as the integrated circuit die50described above with reference toFIG.1, and the description is not repeated herein. The PIC70B may comprise optical devices, such as waveguides, modulators, or the like. The PIC70B may also include an optical coupler, such as an edge coupler72. In some embodiments, the edge coupler72may comprise a dielectric material (such as, silicon nitride, or the like) and may be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), or the like. In other embodiments, the edge coupler72may comprise a semiconductor layer (such as, a silicon layer, or the like) and may be formed from an SOI substrate. The edge coupler72may be disposed within the PIC70B and near a sidewall (or an edge)70E of the integrated circuit die70. As described below with greater detail, the edge coupler72provides optical coupling between the integrated circuit die70and an optical fiber coupled to the integrated circuit die70.

The integrated circuit die70may be formed in a wafer, which may include different die regions that are singulated in subsequent steps to form a plurality of integrated circuit dies70. In some embodiments, the wafer may be formed by hybrid bonding an EIC wafer (comprising a plurality of EICs70A) to a PIC wafer (comprising a plurality of PICs70B).

FIGS.4-7,8A,8B,9,10,11A and11Billustrate top and cross-sectional views of intermediate stages in the manufacturing of package components400, in accordance with some embodiments.FIGS.4-7,8A,8B,9,10, and11Aillustrate cross-sectional views, andFIG.11Billustrates a top view. In particular,FIGS.4-7,8A,8B,9, and10illustrate formation of a wafer-level package component200, in accordance with some embodiments. In some embodiments, the wafer-level package component200comprises a plurality of die-level regions (such as a region200A) that correspond to die-level package components (such as package components400). The plurality of die-level regions of the wafer-level package component200are singulated to form individual die-level packaged components400as described below inFIGS.11A and11B.

InFIG.4, a carrier wafer100is provided or formed. The carrier wafer100is used as a platform or a support for a packaging process described below. In some embodiments, the carrier wafer100comprises a semiconductor material (such as silicon, or the like), a dielectric material (such as glass, a ceramic material, quartz, or the like), a combination thereof, or the like.

In some embodiments, conductive vias102are formed on the carrier wafer100. The conductive vias102may be also referred to as through vias, through molding vias, or through encapsulant vias. As an example to form the conductive vias102, a seed layer (not shown) is formed over the carrier wafer100. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In a particular embodiment, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to conductive vias. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the conductive vias102.

In some embodiments, the integrated circuit dies104are attached to the carrier wafer. The integrated circuit dies104may be embedded local interconnect (eLSI) dies. The integrated circuit dies104may have a similar structure as the integrated circuit die50described above with reference toFIG.1, and the description is not repeated herein. In some embodiments, the integrated circuit dies104comprise passive electrical devices and do not comprise active electrical devices. In some embodiments, the integrated circuit dies104comprise both active and passive electrical devices.

In some embodiments, backsides104B of the integrated circuit dies104are attached to the carrier wafer100, such that front sides104F (such as sides on which electrical device and conducive interconnects are formed) of the integrated circuit dies104face away from the carrier wafer100. In some embodiments, the integrated circuit dies104are attached to the carrier wafer100using adhesives106. The adhesives106may be any suitable adhesive, epoxy, die attach film (DAF), or the like. The adhesives106may be applied to the backsides104B of the integrated circuit dies104or may be applied over a surface of the carrier wafer100.

InFIG.5, an encapsulant108is formed on and around the integrated circuit dies104and the conductive vias102. After formation, the encapsulant108encapsulates the integrated circuit dies104and the conductive vias102. The encapsulant108may be a molding compound, epoxy, or the like. The encapsulant108may be applied by compression molding, transfer molding, or the like, and is formed over the carrier wafer100such that the integrated circuit dies104and the conductive vias102are buried or covered. The encapsulant108may be applied in liquid or semi-liquid form and then subsequently cured. The encapsulant108may be thinned to expose the integrated circuit dies104. The thinning process may be a grinding process, a chemical mechanical polishing (CMP), an etch-back, combinations thereof, or the like. After the thinning process, the front side surfaces104F of the integrated circuit dies104, top surfaces of the conductive vias102, and a top surface of the encapsulant108are coplanar (within process variations), such that they are level with one another. The thinning is performed until a desired amount of the integrated circuit dies104, the encapsulant108, and/or the conductive vias102has been removed.

InFIG.6, a redistribution structure110is formed over the integrated circuit dies104, the encapsulant108, and the conductive vias102. In the embodiment shown, the redistribution structure110includes metallization patterns112and116(sometimes referred to as redistribution layers or redistribution lines) and insulating layers114and118.

The metallization pattern112may be formed on the integrated circuit dies104, the encapsulant108, and the conductive vias102. As an example to form the metallization pattern112, a seed layer is formed over the integrated circuit dies104, the encapsulant108, and the conductive vias102. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist (not shown) is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern112. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. Then, the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and conductive material form the metallization pattern112.

The insulating layer114may be formed on the metallization pattern112. In some embodiments, the insulating layer114is formed of a polymer, which may be a photo-sensitive material such as PBO, polyimide, BCB, or the like, that may be patterned using a lithography mask. In other embodiments, the insulating layer114is formed of a nitride such as silicon nitride; an oxide such as silicon oxide, PSG, BSG, BPSG; or the like. The insulating layer114may be formed by spin coating, lamination, CVD, the like, or a combination thereof. The insulating layer114is then patterned to form openings exposing portions of the metallization pattern112. The patterning may be performed by an acceptable process, such as by exposing the insulating layer114to light when the insulating layer114is a photo-sensitive material or by etching using, for example, an anisotropic etch. If the insulating layer114is a photo-sensitive material, the insulating layer114can be developed after the exposure.

The metallization pattern116is then formed. The metallization pattern116includes conductive elements extending along the major surface of the insulating layer114and extending through the insulating layer114to physically and electrically couple to the metallization pattern112. As an example to form the metallization pattern116, a seed layer is formed over the insulating layer114and in the openings extending through the insulating layer114. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern116. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material and underlying portions of the seed layer form the metallization pattern116. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching.

After forming the metallization pattern116, an insulating layer118is formed over the metallization pattern116and the insulating layer114. The insulating layer118may be formed using similar materials and methods as the insulating layer114. In the illustrated embodiment, the redistribution structure110includes two metallization patterns (such as metallization patterns112and116) and two insulating layers (such as the insulating layers114and118). In some embodiments, the redistribution structure110may include any number of insulating layers and metallization patterns. If more insulating layers and metallization patterns are to be formed, steps and processes discussed above may be repeated.

Further inFIG.6, conductive connectors120are formed on and in electrical contact with the redistribution structure110. The conductive connectors120may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold (ENEPIG) technique formed bumps, or the like. The conductive connectors120may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors120are formed by initially forming a layer of solder through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shapes. In another embodiment, the conductive connectors120comprise metal pillars (such as copper pillars) formed by a sputtering, printing, electro plating, electroless plating, CVD, or the like. The metal pillars may be solder free and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on the top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof and may be formed by a plating process.

In some embodiments, the conductive connectors120comprise UBMs120A and solder regions120B over the UBMs120A. The UBMs120A may be formed using similar materials and methods as the UBMs56A described above with reference to FIG.1, and the description is not repeated herein. The solder regions120B may be formed using similar materials and methods as the solder regions56B described above with reference toFIG.1, and the description is not repeated herein.

In some embodiments, one or more dam structures122are formed over the redistribution structure110, such as over the insulating layer118. The dam structure122may comprise a lower portion122A, and an upper portion122B over the lower portion122A. In some embodiments, the conductive connectors120and the one or more dam structures122are formed in a same process, such that the lower portions122A of the dam structure122are formed in a same process as the UBMs120A, and the upper portions122B of the dam structure122are formed in a same process as the solder regions120B. In such embodiments, the lower portions122A of the dam structures122and the UBMs120A comprise a same material, and the upper portions122B of the dam structures122and the solder regions120B comprise a same material. In some embodiments, the lower portions122A of the dam structures122and the UBMs120A have a same width. In other embodiments, lower portions122A of the dam structures122and the UBMs120A have different widths. In some embodiments, the dam structures122and the conductive connectors120have a same height. In other embodiments, the dam structures122and the conductive connectors120have different heights. The dam structures122have a height H1and a width W1. The height H1may be between about 5 μm and about 80 μm. The width W1may be between about 20 μm and about 1.0 mm. A ratio of the height H1to the width W1(H1/W1) may be between about 0.1 and about 1.5.

In some embodiments, the one or more dam structures122may be electrically dummy or electrically non-fictional structures. In such embodiments, the one or more dam structures122may be electrically isolated from the conductive connectors120and the metallization patterns112and116of the redistribution structure110by the insulating layers114and118of the redistribution structure110.

InFIG.7, integrated circuit dies50,60and70are attached to the redistribution structure110. In the illustrated cross-sectional view, each die-level region (such as the region200A illustrated inFIG.9) of the wafer-level package component200(seeFIG.9) comprises two integrated circuit dies50, a single integrated circuit die60and a single integrated circuit die70. The first one of the integrated circuit dies50may be a logic device, such as an application-specific integrated circuit (ASIC) die, a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), a microcontroller, or the like. The second one of the integrated circuit dies50may be a memory device, such as a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, or the like. In some embodiments, the integrated circuit dies50may be the same type of dies, such as SoC dies, ASIC dies, or the like. Although a single integrated circuit die60and a single integrated circuit die70are shown in the cross-sectional view inFIG.7, there may be a plurality of integrated circuit dies60and a plurality of single integrated circuit dies70in each die-level region (such as the region200A illustrated inFIG.9) of the wafer-level package component200(seeFIG.9) as shown inFIG.11B, as an example.

In some embodiments, the integrated circuit dies50,60and70are attached to the redistribution structure110using the conductive connectors56(seeFIGS.1-3) and120(seeFIG.6). The integrated circuit dies50,60and70may be placed on the redistribution structure110using, e.g., a pick-and-place tool. After placing the integrated circuit dies50,60and70on the redistribution structure110, the solder regions56B of the conductive connectors56(seeFIGS.1-3) are in physical contact with respective solder regions120B of respective conductive connectors120(seeFIG.6). After placing the integrated circuit dies50,60and70on the redistribution structure110, a reflow process in performed on the conductive connectors56and120(seeFIGS.1-3and6). The reflow process melts and merges the solder regions56B and120B into solder joints124. The solder joints124electrically and mechanically couple the integrated circuit dies50,60and70to the redistribution structure110.

Further inFIG.7, an underfill126may be formed around the solder joints124, and in a gap between the redistribution structure110and the integrated circuit dies50,60and70. The gap may have a height H2between about 5 μm and about 55 μm. The height H2of the gap may be greater than the height H1(seeFIG.6) of the dam structures122. A ratio of the height H1to the height H2(H1/H2) may be between about 0.1 and about 0.95. The underfill126may reduce stress and protect the solder joints124. The underfill126may be formed of an underfill material such as a molding compound, epoxy, or the like. The underfill126may be formed by a capillary flow process after the integrated circuit dies50,60and70are attached to the redistribution structure110, or may be formed by a suitable deposition method before the integrated circuit dies50,60and70are attached to the redistribution structure110. The underfill126may be applied in liquid or semi-liquid form and then subsequently cured. In some embodiments, the underfill126partially or fully fills gaps between adjacent ones of the integrated circuit dies50,60and70, such that the underfill126extends along sidewalls of the integrated circuit dies50,60and70. In some embodiments, the dam structure122prevents the underfill126from physically contacting and extending along the sidewall70E of the integrated circuit die70. In such embodiments, the dam structure122is in physical contact with the underfill126. Accordingly, the underfill126does not shield the edge coupler72of the integrated circuit die70.

FIGS.8A and8Billustrate the structure ofFIG.7after formation an optical glue128, in accordance with some embodiments.FIG.8Aillustrates a cross-sectional view, andFIG.8Billustrates a magnified view of a region130ofFIG.8A. In some embodiment, the optical glue128comprises a polymer material such as epoxy-acrylate oligomers. The polymer material may have a refractive index between about 1 and about 3. In some embodiments, the optical glue128is formed over the redistribution structure110near the sidewall70E of the integrated circuit die70, such that the optical glue128covers the dam structure122. The optical glue128is in physical contact with the dam structure122and the underfill126. Furthermore, the optical glue128extends along and is in physical contact with the sidewall70E of the integrated circuit die70. The optical glue128may have a height H3between about 6 μm and about 787 μm. In some embodiments, the height H3of the optical glue128is less than a height of the integrated circuit die70.

InFIG.9, an encapsulant132is formed on and around the integrated circuit dies50,60and70. After formation, the encapsulant132encapsulates the integrated circuit dies50,60and70, the underfill126, and the optical glue128. The optical glue128prevents the encapsulant132from shielding the edge coupler72of the integrated circuit die70. The encapsulant132may be a molding compound, epoxy, or the like. The encapsulant132may not include fillers therein. The encapsulant132may be applied by compression molding, transfer molding, or the like, and is formed over the carrier wafer100such that the integrated circuit dies50,60and70are buried or covered. The encapsulant132may be applied in liquid or semi-liquid form and then subsequently cured. The encapsulant132may be thinned to expose the integrated circuit dies50,60and70. The thinning process may be a grinding process, a CMP, an etch-back, combinations thereof, or the like. After the thinning process, top surfaces of the integrated circuit dies50,60and70, and the encapsulant132are coplanar (within process variations), such that they are level with one another. The thinning is performed until a desired amount of the integrated circuit dies50,60and70, and/or the encapsulant132has been removed. In some embodiments, the encapsulants108and132comprise a same material. In some embodiments, the encapsulants108and132comprise different materials. A refractive index of the encapsulant132may be between about 1.5 and about 3.0. In some embodiments, a difference between the refractive index of the optical glue128and the refractive index of the encapsulant132is between about 0.2 and about 0.3.

InFIG.10, the carrier wafer100(seeFIG.9) is de-bonded from the wafer-level package component200, such that the carrier wafer100is de-bonded from the encapsulant108and the integrated circuit dies104. In some embodiments, the de-bonding process may also remove adhesives106from the integrated circuit dies104. Subsequently, the wafer-level package component200is flipped over and attached to a carrier wafer300. The carrier wafer300may be formed using similar materials and methods as the carrier wafer100described above with reference toFIG.4, and the description is not repeated herein. In some embodiments, the wafer-level package component200is attached to the carrier wafer300using an adhesive (not shown).

After attaching the wafer-level package component200to the carrier wafer300, conductive connectors134are formed over the integrated circuit dies104and the encapsulant108. The conductive connectors134are electrically coupled to the conductive vias102and/or integrated circuit dies104. The conductive connectors134may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connectors134may be formed using similar materials and methods as the conductive connectors120described above with reference toFIG.6, and the description is not repeated herein. In the illustrated embodiment, the conductive connectors134comprise UBMs134A, and solder regions134B over the UBMs134A. The UBMs134A and the solder regions134B may be formed using similar material and methods as the UBMs120A and the solder regions120B, respectively, described above with reference toFIG.6, and the description is not repeated herein.

Further, a singulation process is performed on the wafer-level package component200by cutting along scribe line regions, e.g., around the region200A. The singulation process may include sawing, etching, dicing, a combination thereof, or the like. For example, the singulation process can include sawing the encapsulants108and132, the redistribution structure110and the optical glue128. The singulation process singulates the region200A from adjacent regions to form a singulated package component400illustrated inFIGS.11A and11B. The singulated package component400is from the region200A.

FIGS.11A and11Billustrate top and cross-sectional views of the package component400, in accordance with some embodiments. In particular,FIG.11Aillustrates a cross-sectional view andFIG.11Billustrates a top view. Furthermore, not all features of the package component400are illustrated in the top view ofFIG.11Bfor clarity of presentation. As a result of the singulation process described above with reference toFIG.10, the outer sidewalls of the encapsulants108and132, the redistribution structure110, and the optical glue128are laterally coterminous (within process variations) as illustrated inFIG.11A. After the singulation process, the encapsulant132has a thickness T1on the sidewall70E of the integrated circuit die70. The thickness T1may be between about 5 mm to about 10 mm. In some embodiments, the dam structures122have a rectangular shape in a plan view as illustrated inFIG.11B. In other embodiments, the dam structures122may have any desired shape in the plan view based on design requirement of the package component400. In the illustrated embodiment, the dam structures122overlap with respective integrated circuit dies70, such that sidewalls122L of the dam structures122are covered by the respective integrated circuit dies70, while sidewalls122R (opposite to the sidewalls122L) of the dam structures122are not covered by the respective integrated circuit dies70as shown inFIG.11B.

FIGS.12A,12B and12Cillustrate top and cross-sectional views of a package component400′, in accordance with some embodiments. In particular,FIG.12Aillustrates a cross-sectional view,FIG.12Billustrates a magnified view of a region136ofFIG.12A, andFIG.12Cillustrates a top view. Furthermore, not all features of the package component400′ are illustrated in the top view ofFIG.12Cfor clarity of presentation. The package component400′ is similar to the package component400, with similar features being labeled by similar numerical references, and descriptions of the similar features are not repeated herein. The package component400′ may be formed using process steps that are similar to the process steps described above with reference toFIGS.4-7,8A,8B,9,10,11A and11B, and the description is not repeated herein. The dam structures122of the package component400′ are formed such that the dam structures122do not overlap with respective integrated circuit dies70in a plan view as shown inFIG.12C. In illustrated embodiment, sidewalls122L of the dam structures122are vertically aligned with sidewalls70E of respective integrated circuit dies70. Accordingly, sidewalls122L of the dam structures122are illustrated as collinear with the sidewalls70E of the respective integrated circuit dies70in the top view shown inFIG.12C. Sidewalls122R (opposite to the sidewalls122L) of the dam structures122are not covered by the respective integrated circuit dies70as shown inFIG.12C.

FIGS.13-16illustrate cross-sectional views of intermediate stages in the manufacturing of package components600, in accordance with some embodiments.FIGS.13-15illustrate formation of a wafer-level package component500, in accordance with some embodiments. In some embodiments, the wafer-level package component500comprises a plurality of die-level regions (such as a region500A) that correspond to die-level package components (such as package components600). The plurality of die-level regions of the wafer-level package component500are singulated to form individual die-level packaged components600as described below inFIG.16. Process steps described below with reference toFIGS.13-16are similar to the process steps described above with reference toFIGS.4-7,8A,8B,9,10,11A and11B, and descriptions of the similar processes and structures are not repeated. In distinction with the package component400(seeFIGS.11A and11B), the package component600comprises one or more dam structures502instead of the one or more dam structures122(seeFIGS.11A and11B).

InFIG.13, a carrier wafer100is provided or formed. The carrier wafer100is used as a platform or a support for a packaging process described below. In some embodiments, the carrier wafer100comprises a semiconductor material (such as silicon, or the like), a dielectric material (such as glass, a ceramic material, quartz, or the like), a combination thereof, or the like.

In some embodiments, conductive vias102are formed on the carrier wafer100as described above with reference toFIG.4, and the description is not repeated herein. Subsequently, integrated circuit dies104are attached to the carrier wafer100as described above with reference toFIG.4, and the description is not repeated herein. The integrated circuit dies104may be embedded local interconnect (eLSI) dies.

In some embodiments, an encapsulant108is formed on and around the integrated circuit dies104and the conductive vias102as described above with reference toFIG.5, and the description is not repeated herein. The encapsulant108may be thinned to expose the integrated circuit dies50. The thinning process may be a grinding process, a CMP, an etch-back, combinations thereof, or the like. After the thinning process, front side surfaces104F of the integrated circuit dies104, top surfaces of the conductive vias102, and a top surface of the encapsulant108are coplanar (within process variations), such that they are level with one another. The thinning is performed until a desired amount of the integrated circuit dies104, the encapsulant108, and/or the conductive vias102has been removed.

After forming the encapsulant108, a redistribution structure110is formed over the integrated circuit dies104, the encapsulant108, and the conductive vias102as described above with reference toFIG.6, and the description is not repeated herein. Subsequently, conductive connectors120are formed on and in electrical contact with the redistribution structure110as described above with reference toFIG.6, and the description is not repeated herein.

InFIG.14, after forming the conductive connectors120, one or more dam structures502are formed on the redistribution structure110. The dam structures502may comprise a metallic material, an underfill material, a polymer material, a dielectric material, or the like, and may be formed using a suitable deposition process. In some embodiments, the dam structures502have a rectangular shape in a plan view. In other embodiments, the dam structures502may have any desired shape in the plan view based on design requirement of the package component600. In the illustrated embodiments, the dam structures502are formed after forming the conductive connectors120. In other embodiments, the dam structures502may be formed prior to forming the conductive connectors120.

InFIG.15, process steps described above with reference toFIGS.7,8A,8B,9, and10are performed on the structure of theFIG.14to form the wafer-level package component500. In some embodiments, the dam structure502prevents the underfill126from physically contacting and extending along the sidewall70E of the integrated circuit die70. In such embodiments, the dam structure502is in physical contact with the underfill126. Accordingly, the underfill126does not shield the edge coupler72of the integrated circuit die70. In the illustrated embodiments, the dam structure502overlaps with the integrated circuit die70(similar to the dam structure122illustrated inFIGS.11A and11B), such that a first sidewall of the dam structure502is covered by the integrated circuit die70and a second sidewall (opposite to the first sidewall) of the dam structure502is not covered by the integrated circuit die70. In other embodiments, the dam structure502does not overlap with the integrated circuit die70(similar to the dam structure122illustrated inFIGS.12A-12C), such that the first sidewall of the dam structure502is vertically aligned to the sidewall of the integrated circuit die70and the second sidewall (opposite to the first sidewall) of the dam structure502is not covered by the integrated circuit die70.

Further, a singulation process is performed on the wafer-level package component500by cutting along scribe line regions, e.g., around the region500A. The singulation process may include sawing, etching, dicing, a combination thereof, or the like. For example, the singulation process can include sawing the encapsulants108and132, the redistribution structure110and the optical glue128. The singulation process singulates the region500A from adjacent regions to form a singulated package component600as illustrated inFIG.16. The singulated package component600is from the region500A.

FIGS.17-20illustrate cross-sectional views of intermediate stages in the manufacturing of package components800, in accordance with some embodiments. The package components800may be chip-on-wafer (CoW) package components. InFIG.17, an interposer wafer700is obtained or formed. The interposer wafer700comprises a plurality of package regions, such as the package region700A. The interposer wafer700comprises an interposer702in a package region (such as the package region700A), which will be singulated in subsequent processing to be included in the package component800. In some embodiments, the interposers702include a substrate704, an interconnect structure706, and conductive vias708.

The substrate704may be formed using similar materials and methods as the semiconductor substrate52described above with reference toFIG.1, and the description is not repeated herein. In some embodiments, the substrate704generally does not include active devices therein, although the interposers702may include passive devices formed in and/or on an active or a front surface (e.g., the surface facing upward inFIG.17) of the substrate704. In other embodiments, active devices such as transistors, capacitors, resistors, diodes, and the like, may be formed in and/or on the front surface of the substrate704.

The interconnect structure706is formed over the front surface of the substrate704, and is used to electrically connect the devices (if any) of the substrate704. The interconnect structure706may include one or more dielectric layer(s) and respective metallization layer(s) in the dielectric layer(s). The interconnect structure706may be formed using similar materials and methods as the interconnect structure54described above with reference toFIG.1, and the description is not repeated herein. In some embodiments, conductive connectors120and one or more dam structures122are formed at the front-side700FS of the interposer wafer700as described above with reference toFIG.6, and the description is not repeated herein.

The conductive vias708extend into the interconnect structure706and/or the substrate704. The conductive vias708are electrically connected to metallization layer(s) of the interconnect structure706. The conductive vias708are also sometimes referred to as through substrate vias (TSVs). As an example to form the conductive vias708, recesses can be formed in the interconnect structure706and/or the substrate704by, for example, etching, milling, laser techniques, a combination thereof, and/or the like. A thin dielectric material may be formed in the recesses, such as by using an oxidation technique. A thin barrier layer may be conformally deposited in the openings, such as by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, a combination thereof, and/or the like. The barrier layer may be formed of an oxide, a nitride, a carbide, combinations thereof, or the like. A conductive material may be deposited over the barrier layer and in the openings. The conductive material may be formed by an electro-chemical plating process, CVD, ALD, PVD, a combination thereof, and/or the like. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, a combination thereof, and/or the like. Excess conductive material and barrier layer is removed from a surface of the interconnect structure706or the substrate704by, for example, a CMP. Remaining portions of the barrier layer and conductive material form the conductive vias708.

InFIG.18, process steps described above with reference toFIGS.7,8A,8B, and9are performed on the structure of theFIG.17to form a wafer-level package component. In some embodiments, the dam structure122prevents the underfill126from physically contacting and extending along the sidewall70E of the integrated circuit die70. Accordingly, the underfill126does not shield the edge coupler72of the integrated circuit die70.

InFIG.19, the wafer-level package component ofFIG.17is flipped over and attached to a carrier wafer710. The carrier wafer710may be formed using similar materials and methods as the carrier wafer100described above with reference toFIG.4, and the description is not repeated herein. In some embodiments, the wafer-level package component is attached to the carrier wafer710using an adhesive (not shown).

In some embodiments, the substrate704is thinned to expose the conductive vias708. Exposure of the conductive vias708may be accomplished by a thinning process, such as a grinding process, a CMP, an etch-back, combinations thereof, or the like. In some embodiments (not separately illustrated), the thinning process for exposing the conductive vias708includes a CMP, and the conductive vias708protrude at the back-side700BS of the wafer700as a result of dishing that occurs during the CMP. In such embodiments, an insulating layer (not separately illustrated) may optionally be formed on the back surface of the substrate704, surrounding the protruding portions of the conductive vias708. The insulating layer may be formed of a silicon-containing insulator, such as, silicon nitride, silicon oxide, silicon oxynitride, or the like, and may be formed by a suitable deposition method such as spin coating, CVD, plasma-enhanced CVD (PECVD), high density plasma CVD (HDP-CVD), or the like. After the substrate704is thinned, the exposed surfaces of the conductive vias708and the insulating layer (if present) or the substrate704are coplanar (within process variations), such that they are level with one another, and are exposed at the back-side700BS of the interposer wafer700. Subsequently, conductive connectors134are formed on the back-side700BS of the interposer wafer700as described above with reference toFIG.10, and the description is not repeated herein.

Further, a singulation process is performed by cutting along scribe line regions, e.g., around the package region700A. The singulation process may include sawing, etching, dicing, a combination thereof, or the like. For example, the singulation process can include sawing the encapsulant132, the optical glue128, the interconnect structure706, and the substrate704. The singulation process singulates the package region700A from adjacent package regions to form a singulated package component800as illustrated inFIG.20. The singulated package component800is from the package region700A.

The singulation process forms interposers702from the singulated portions of the interposer wafer700. As a result of the singulation process, the outer sidewalls of the interposer702, the encapsulant132, and the optical glue128are laterally coterminous (within process variations) as illustrated inFIG.20. In the illustrated embodiment, the dam structures122of the package component800overlap with respective integrated circuit dies70in a plan view as described above with reference toFIGS.11A and11B, and the description is not repeated herein.

FIG.21illustrates a cross-sectional view of a package component800′, in accordance with some embodiments. The package component800′ is similar to the package component800(seeFIG.20), with similar features being labeled by similar numerical references, and descriptions of the similar features are not repeated herein. In some embodiments, the package component800′ may be formed using process steps that are similar to the process steps described above with reference toFIGS.17-20, and the description is not repeated herein. In the illustrated embodiment, the dam structures122of the package component800′ do not overlap with respective integrated circuit dies70in a plan view as described above with reference toFIGS.12A-12C, and the description is not repeated herein.

FIG.22illustrates a cross-sectional view of a package component900, in accordance with some embodiments. The package component900is similar to the package component800(seeFIG.20), with similar features being labeled by similar numerical references, and descriptions of the similar features are not repeated herein. In distinction with package component800(seeFIG.20), the package component900comprises the one or more dam structures502instead of the one or more dam structures122. In some embodiments, the package component900may be formed using process steps that are similar to the process steps described above with reference toFIGS.17-20, where, instead of the one or more dam structures122, the one or more dam structures502are formed as described above with reference toFIG.14.

FIGS.23,24A,24B,24C,25A and25Billustrate top and cross-sectional views of intermediate stages in the manufacturing of a package1100, in accordance with some embodiments. In particular,FIGS.23,24A and25Aillustrate cross-sectional views,FIG.24Billustrates a top view,FIG.24Cillustrates a magnified view of a region1034ofFIG.24B, andFIG.25Billustrates a magnified view of a region1052ofFIG.25A.

InFIGS.23, a package component400′ is placed on a package substrate1000. The package substrate1000includes a substrate core1002, which may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, or the like, may also be used. Additionally, the substrate core1002may be a SOI substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In another embodiment, the substrate core1002is an insulating core such as a fiberglass reinforced resin core. One example core material is fiberglass resin such as FR4. Alternatives for the core material include bismaleimide-triazine (BT) resin, or alternatively, other printed circuit board (PCB) materials or films.

In some embodiments, the substrate core1002may include active and passive devices (not separately illustrated). Devices such as transistors, capacitors, resistors, combinations thereof, and the like may be used to generate the structural and functional requirements of the design for the system. The devices may be formed using any suitable methods. In some embodiments, the substrate core1002is substantially free of active and passive devices. In some embodiments, the substrate core1002further includes conductive vias1004, which may be also referred to as TSVs. In some embodiments, the conductive vias1004may be formed using similar materials and methods as the conductive vias708described above with reference toFIG.17, and the description is not repeated herein.

The package substrate1000may also include a redistribution structure. In some embodiments, the redistribution structure may be formed of alternating layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material, and may be formed through any suitable process (such as deposition, damascene, or the like). In other embodiments, the redistribution structure may be formed of alternating layers of dielectric material (e.g., build up films such as Ajinomoto build-up film (ABF) or other laminates) and conductive material (e.g., copper) with vias interconnecting the layers of conductive material, and may be formed through any suitable process (such as lamination, plating, or the like).

In the illustrated embodiment, the package substrate1000comprises redistribution structures1006and1008formed on opposing surfaces of the substrate core1002, such that the substrate core1002is interposed between the redistribution structure1006and the redistribution structure1008. The conductive vias1004electrically couple the redistribution structure1006to the redistribution structure1008. In some embodiments, the redistribution structure1006or the redistribution structure1008may be omitted.

In some embodiments, bond pads1010and a solder resist layer1012are formed on the redistribution structure1006, with the bond pads1010being exposed by openings formed in the solder resist layer1012. The bond pads1010may be a part of the redistribution structure1006and may be formed together with other conductive features of the redistribution structure1006. The solder resist layer1012may comprise a suitable insulating material (such as a dielectric material, a polymer material, or the like) and may be formed using any suitable deposition methods.

In some embodiments, conductive connectors1014extend through the opening in the solder resist layer1012and contact the bond pads1010. The conductive connectors1014may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connectors1014may be formed using similar materials and methods as the conductive connectors120described above with reference toFIG.6, and the description is not repeated herein. In the illustrated embodiment, the conductive connectors1014comprise solder balls.

In some embodiments, bond pads1016and a solder resist layer1018are formed on the redistribution structure1008, with the bond pads1016being exposed by openings formed in the solder resist layer1018. The bond pads1016may be a part of the redistribution structure1008and may be formed together with other conductive features of the redistribution structure1008. The solder resist layer1018may comprise a suitable insulating material (such as a dielectric material, a polymer material, or the like) and may be formed using any suitable deposition methods.

In some embodiments, conductive connectors1020extend through the openings in the solder resist layer1018and contact the bond pads1016. The conductive connectors1020may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold (ENEPIG) technique formed bumps, or the like. The conductive connectors1020may be formed using similar materials and methods as the conductive connectors120described above with reference toFIG.6, and the description is not repeated herein. In the illustrated embodiment, the conductive connectors1020comprise solder balls.

In some embodiment, the solder resist layer1012is patterned to form one or more trenches1022in the solder resist layer1012. The patterning process may comprise suitable photolithography and etching methods. The suitable etching methods may include a dry etching method or a wet etching method. The etching methods may be anisotropic. In some embodiments, the trenches1022extend through the solder resist layer1012and expose conductive features of the redistribution structure1006. In other embodiments, the trenches1022partially extend into the solder resist layer1012and do not expose conductive features of the redistribution structure1006.

In some embodiments, the package component400′ may be placed on the package substrate1000using, e.g., a pick-and-place tool. After placing the package component400′ on the package substrate1000, the conductive connectors134are in physical contact with respective conductive connectors1014, such that the solder regions134B of the conductive connectors134are in physical contact with the respective conductive connectors1014.

InFIGS.24A-24C, after placing the package component400′ on the package substrate1000, a reflow process is performed to mechanically and electrically attach the package component400′ to the package substrate1000. The reflow process melts and merges the solder regions134B of the conductive connectors134(seeFIG.23) and respective solder materials of the conductive connectors1014(seeFIG.23) into solder joints1024. The solder joints1024electrically and mechanically couple the package component400′ to the package substrate1000.

In some embodiments, an underfill1026may be formed around the solder joints1024, and in a gap between the package component400′ and the package substrate1000. The underfill1026may be formed using similar materials and methods as the underfill126described above with reference toFIG.7, and the description is not repeated herein. In some embodiments, the underfill1026extends into and at least partially fills the trenches1022. The trenches1022prevent the underfill1026from extending along a sidewall400R of the package component400′ that is proximate to the edge coupler72of the integrated circuit die70. Accordingly, the edge coupler72of the integrated circuit package70is not shielded by the underfill1026. In some embodiments, the underfill1026extends along and physically contacts a sidewall400L of the package component400′, with the sidewall400L being opposite to the sidewall400R.

In some embodiments, a warpage control structure1030is attached to the package substrate1000. The warpage control structure1030may be attached to the package substrate1000by an adhesive1028, such that the adhesive1028is interposed between the warpage control structure1030and the solder resist layer1012. The adhesive1028may be any suitable adhesive, epoxy, or the like. The warpage control structure1030may be an annular structure (seeFIG.24B) and may comprise a hole1032. The package component400′ may be disposed in the hole1032of the warpage control structure1030. The warpage control structure1030may comprise a metal, a metal alloy, a dielectric material, a semiconductor material, or the like.

Referring toFIGS.24B and24C, in the illustrated embodiment, each of the trenches1022has a first sidewall1022L that is vertically aligned to a sidewall400R of the package component400′ and a second sidewall1022R (opposite to the first sidewall1022L) that is laterally spaced apart from sidewall400R of the package component400′. In other embodiments, the trenches1022may partially or fully overlap with the package component400′ in a plan view.

In some embodiment, a center of an edge coupler72, a center of a respective dam structure122, and a center of a respective trench1022are aligned along a same line (illustrated by a dashed line1036inFIG.24C). The edge of the dam structure122is spaced apart from the line1036by a distance D1along a direction parallel to a sidewall70E of a respective integrated circuit die70. The distance D1may be between about 100 μm and about 5.0 mm. A dam structure122has a first width W1as measured along a first direction perpendicular to the sidewall70E of the respective integrated circuit die70and a second width W2as measured along a second direction parallel to the sidewall70E of the respective integrated circuit die70. The width W2is 2 times the distance D1. The width W1is between about 20 μm and about 1.0 mm. The width W2is between about 200 μm and about 10.0 mm.

An edge of the trench1022is spaced apart from the line1036by a distance D2along a direction parallel to a sidewall70E of a respective integrated circuit die70. The distance D2may be between about 100 μm and about 5.0 mm. The trench1022has a first width W3as measured along a first direction perpendicular to the sidewall70E of the respective integrated circuit die70and a second width W4as measured along a second direction parallel to the sidewall70E of the respective integrated circuit die70. The width W4is 2 times the distance D2. The width W3is between about 20 μm and about 1.0 mm. The width W4is between about 200 μm and about 10.0 mm.

InFIGS.25A and25B, a fiber array unit1042is attached to the package component400′. The fiber array unit1042provides an interface between the edge coupler72of the integrated circuit die70and an optical fiber1050that is attached to the fiber array unit1042. In some embodiments, before attaching the fiber array unit1042to the package component400′, a support structure1040is attached to the solder resist layer1012of the package substrate1000using an adhesive1038. The support structure1040may comprise a semiconductor material (such as, for example, silicon), a dielectric material, a combination thereof, or the like. The adhesive1038may be formed using similar materials and methods as the adhesive1028.

The fiber array unit1042may be attached to a top surface of the package component400′ using an adhesive1044, such that the adhesive1044is in physical contact with the top surface of the integrated circuit die70and the top surface of the encapsulant132. The fiber array unit1042may be attached to a top surface of the support structure1040using an adhesive1046. The fiber array unit1042may be also attached to the sidewall400R of the package component400′ using an optical glue1048, such that the optical glue1048is in physical contact with a sidewall of the optical glue128and is interposed between the optical glue128and the fiber array unit1042. The adhesives1044and1046may be formed using similar materials and methods as the adhesive1028. The optical glue1048may be formed using similar materials and methods as optical glue128.

In the illustrated embodiment, the optical glues128and1048are interposed between the edge coupler72of the integrated circuit die70and the fiber array unit1042. By forming the dam structure122, the optical glue128and the trench1022as described above, materials of the underfills126and1026and the encapsulant132are not formed between the edge coupler72of the integrated circuit die70and the fiber array unit1042. Accordingly, the edge coupler72of the integrated circuit die70is not shielded from the fiber array unit1042by the materials of the underfills126and1026and the encapsulant132.

FIG.26illustrates a cross-sectional view of a package1200, in accordance with some embodiments. The package1200is similar to the package1100(seeFIGS.25A and25B), with similar features being labeled by similar numerical references, and descriptions of the similar features are not repeated herein. The package1200may formed using the process steps described above with reference withFIGS.23,24A,24B,24C,25A and25B, with a distinction that the package component400(seeFIGS.11A and11B) is attached to the package substrate1000instead of the package component400′ (seeFIGS.25A and25B).

FIG.27illustrates a cross-sectional view of a package1300, in accordance with some embodiments. The package1300is similar to the package1100(seeFIGS.25A and25B), with similar features being labeled by similar numerical references, and descriptions of the similar features are not repeated herein. The package1300may formed using the process steps described above with reference withFIGS.23,24A,24B,24C,25A and25B, with a distinction that the package component600(seeFIG.16) is attached to the package substrate1000instead of the package component400′ (seeFIGS.25A and25B).

FIGS.28A and28Billustrate cross-sectional views of a package1400, in accordance with some embodiments.FIG.28Billustrates a magnified view of a region1054ofFIG.28A. The package1400is similar to the package1100(seeFIGS.25A and25B), with similar features being labeled by similar numerical references, and descriptions of the similar features are not repeated herein. The package1400may formed using the process steps described above with reference withFIGS.23,24A,24B,24C,25A and25B, and the description is not repeated herein. In the illustrated embodiment, the underfill1026extends along the sidewall400R of the package component400′ (such as sidewalls of the encapsulant108and the redistribution structure110) and does not extend along a sidewall of the optical glue128.

FIG.29illustrates a cross-sectional view of a package1500, in accordance with some embodiments. The package1500is similar to the package1100(seeFIGS.25A and25B), with similar features being labeled by similar numerical references, and descriptions of the similar features are not repeated herein. The package1500may formed using the process steps described above with reference withFIGS.23,24A,24B,24C,25A and25B, with a distinction that the package component800′ (seeFIG.21) is attached to the package substrate1000instead of the package component400′ (seeFIGS.25A and25B).

FIG.30illustrates a cross-sectional view of a package1600, in accordance with some embodiments. The package1600is similar to the package1100(seeFIGS.25A and25B), with similar features being labeled by similar numerical references, and descriptions of the similar features are not repeated herein. The package1600may formed using the process steps described above with reference withFIGS.23,24A,24B,24C,25A and25B, with a distinction that the package component800(seeFIG.20) is attached to the package substrate1000instead of the package component400′ (seeFIGS.25A and25B).

FIG.31illustrates a cross-sectional view of a package1700, in accordance with some embodiments. The package1700is similar to the package1100(seeFIGS.25A and25B), with similar features being labeled by similar numerical references, and descriptions of the similar features are not repeated herein. The package1700may formed using the process steps described above with reference withFIGS.23,24A,24B,24C,25A and25B, with a distinction that the package component900(seeFIG.22) is attached to the package substrate1000instead of the package component400′ (seeFIGS.25A and25B).

FIG.32illustrates a cross-sectional view of a package1800, in accordance with some embodiments. The package1800is similar to the package1500(seeFIG.29), with similar features being labeled by similar numerical references, and descriptions of the similar features are not repeated herein. The package1800may formed in a similar manner as the package1500, the description is not repeated herein. In the illustrated embodiment, the underfill1026extends along a sidewall800R of the package component800′ (such as a sidewall of the interposer702) and does not extend along a sidewall of the optical glue128.

FIG.33illustrates a cross-sectional view of a package1900, in accordance with some embodiments. The package1900is similar to the package1100(seeFIGS.25A and25B), with similar features being labeled by similar numerical references, and descriptions of the similar features are not repeated herein. The package1900may be formed in a similar manner as the package1100, with a distinction that a heat dissipation lid1060is attached to the package substrate1000instead of the warpage control structure1030(seeFIGS.25A and25B). In some embodiments, the heat dissipation lid1060comprises a high thermal conductivity material, such as a metal, a metal alloy, or the like. The heat dissipation lid1060may be attached to the solder resist layer1012by an adhesive1056. The adhesive1056may be formed using similar material and methods as the adhesive1038. In some embodiment, a thermal interface material1058is interposed between the top surface of the package component400′ and the heat dissipation lid1060. The thermal interface material1058may comprise a thermal interface material having a high thermal conductivity. In some embodiments, the heat dissipation lid1060comprises an opening1062that exposed the fiber array unit1042. In such embodiments, the optical fiber1050extends into the opening1062and is attached to the fiber array unit1042.

FIG.34illustrates a cross-sectional view of a package2000, in accordance with some embodiments. The package2000is similar to the package1200(seeFIG.26), with similar features being labeled by similar numerical references, and descriptions of the similar features are not repeated herein. The package2000may be formed in a similar manner as the package1200, with a distinction that a heat dissipation lid1060is attached to the package substrate1000instead of the warpage control structure1030(seeFIG.26). In some embodiments, the heat dissipation lid1060is attached to the package substrate1000as described above with reference toFIG.33, and the description is not repeated herein.

FIG.35illustrates a cross-sectional view of a package2100, in accordance with some embodiments. The package2100is similar to the package1300(seeFIG.27), with similar features being labeled by similar numerical references, and descriptions of the similar features are not repeated herein. The package2100may be formed in a similar manner as the package1300, with a distinction that a heat dissipation lid1060is attached to the package substrate1000instead of the warpage control structure1030(seeFIG.27). In some embodiments, the heat dissipation lid1060is attached to the package substrate1000as described above with reference toFIG.33, and the description is not repeated herein.

FIGS.36A and36Billustrate cross-sectional views of a package2200, in accordance with some embodiments.FIG.36Billustrates a magnified view of a region1064ofFIG.36A. The package2200is similar to the package1400(seeFIGS.28A and28B), with similar features being labeled by similar numerical references, and descriptions of the similar features are not repeated herein. The package2200may be formed in a similar manner as the package1400, with a distinction that a heat dissipation lid1060is attached to the package substrate1000instead of the warpage control structure1030(seeFIGS.28A and28B). In some embodiments, the heat dissipation lid1060is attached to the package substrate1000as described above with reference toFIG.33, and the description is not repeated herein.

FIG.37illustrates a cross-sectional view of a package2300, in accordance with some embodiments. The package2300is similar to the package1500(seeFIG.29), with similar features being labeled by similar numerical references, and descriptions of the similar features are not repeated herein. The package2300may be formed in a similar manner as the package1500, with a distinction that a heat dissipation lid1060is attached to the package substrate1000instead of the warpage control structure1030(seeFIG.29). In some embodiments, the heat dissipation lid1060is attached to the package substrate1000as described above with reference toFIG.33, and the description is not repeated herein.

FIG.38illustrates a cross-sectional view of a package2400, in accordance with some embodiments. The package2400is similar to the package1600(seeFIG.30), with similar features being labeled by similar numerical references, and descriptions of the similar features are not repeated herein. The package2400may be formed in a similar manner as the package1600, with a distinction that a heat dissipation lid1060is attached to the package substrate1000instead of the warpage control structure1030(seeFIG.30). In some embodiments, the heat dissipation lid1060is attached to the package substrate1000as described above with reference toFIG.33, and the description is not repeated herein.

FIG.39illustrates a cross-sectional view of a package2500, in accordance with some embodiments. The package2500is similar to the package1700(seeFIG.31), with similar features being labeled by similar numerical references, and descriptions of the similar features are not repeated herein. The package2500may be formed in a similar manner as the package1700, with a distinction that a heat dissipation lid1060is attached to the package substrate1000instead of the warpage control structure1030(seeFIG.31). In some embodiments, the heat dissipation lid1060is attached to the package substrate1000as described above with reference toFIG.33, and the description is not repeated herein.

FIG.40illustrates a cross-sectional view of a package2600, in accordance with some embodiments. The package2600is similar to the package1800(seeFIG.32), with similar features being labeled by similar numerical references, and descriptions of the similar features are not repeated herein. The package2600may be formed in a similar manner as the package1800, with a distinction that a heat dissipation lid1060is attached to the package substrate1000instead of the warpage control structure1030(seeFIG.32). In some embodiments, the heat dissipation lid1060is attached to the package substrate1000as described above with reference toFIG.33, and the description is not repeated herein.

Embodiments may achieve advantages. By forming a package (such as, for example, the package1100illustrated inFIGS.25A and25B) comprising a dam structure (such as, for example, the dam structure122illustrated inFIGS.25A and25B), an optical glue (such as, for example, the optical glue128illustrated inFIGS.25A and25B), and a solder resist trench (such as, for example, the trench1022illustrated inFIGS.25A and25B) as described above various advantages may be achieved. The dam prevents an underfill (such as, for example, the underfill126illustrated inFIGS.25A and25B) that is formed between a package component (such as, for example, the package component400′ illustrated inFIGS.25A and25B) and a redistribution structure or an interposer (such as, for example, the redistribution structure110illustrated inFIGS.25A and25B) from extending along a sidewall of an optical integrated circuit die (such as, for example, the integrated circuit die70illustrated inFIGS.25A and25B) and from shielding an edge coupler (such as, for example, the edge coupler72illustrated inFIGS.25A and25B) of the optical integrated circuit die. The optical glue prevents an encapsulant (such as, for example, the encapsulant132illustrated inFIGS.25A and25B) that encapsulates the optical integrated circuit die from extending along the sidewall of the optical integrated circuit die and from shielding the edge coupler. The solder resist trench allows an underfill (such as, for example, the underfill1026illustrated inFIGS.25A and25B) that is formed between the package component and a package substrate (such as, for example, the package substrate1000illustrated inFIGS.25A and25B) to at least partially fill the solder resist trench and prevents the underfill from extending along a sidewall of the package component and from shielding the edge coupler of the optical integrated circuit die that is disposed near the sidewall of the package component. Accordingly, improved coupling between the edge coupler of the optical integrated circuit die and a fiber array unit (such as, for example, the fiber array unit1042illustrated inFIGS.25A and25B) is achieved. Various embodiments presented herein allow for integration of optical integrated circuit dies comprising edge couplers or grating couplers, achieving high bandwidth with ultra-low power consumption through the edge coupler, extensive integration for co-package optics, and no extra cost for adding the dam structure.

In accordance with an embodiment, a package includes a package substrate including an insulating layer having a trench and a package component bonded to the package substrate adjacent to the trench. The package component includes a redistribution structure, an optical die bonded to the redistribution structure, the optical die including an edge coupler near a first sidewall of the optical die, a dam structure on the redistribution structure near the first sidewall of the optical die, a first underfill between the optical die and the redistribution structure, an encapsulant encapsulating the optical die, and an optical glue in physical contact with the first sidewall of the optical die. The first underfill is in physical contact with the dam structure. The first underfill does not extend along the first sidewall of the optical die. The optical glue separates the dam structure from the encapsulant. The package further includes a second underfill between the insulating layer of the package substrate and the package component. The second underfill is partially disposed in the trench. In an embodiment, the package further includes a fiber array unit coupled to the optical die, where the optical glue is interposed between the edge coupler and the fiber array unit. In an embodiment, the package further includes an optical fiber attached to the fiber array unit. In an embodiment, the dam structure partially overlaps with the optical die in a plan view. In an embodiment, the first sidewall of the optical die is vertically aligned to a first sidewall of the dam structure. In an embodiment, the trench partially overlaps with the optical die in a plan view. In an embodiment, a center of the edge coupler, a center of the dam structure and a center of the trench are aligned along a same line in a plan view.

In accordance with another embodiment, a package includes a package substrate including an insulating layer having a trench, a package component bonded to the package substrate, a first sidewall of the package component being proximate to the trench, and a fiber array unit attached to the first sidewall of the package component. The package component includes a redistribution structure and an optical die bonded to the redistribution structure. The optical die includes an edge coupler. A first sidewall of the optical die and the first sidewall of the package component are proximate to the edge coupler. The package component further includes an optical glue in physical contact with the first sidewall of the optical die and between the edge coupler and the fiber array unit, a dam structure on the redistribution structure adjacent to the first sidewall of the optical die, and a first underfill between the optical die and the redistribution structure. The dam structure is embedded into the optical glue. The first underfill is in physical contact with the dam structure and the optical glue. The first underfill does not extending between the edge coupler and the optical glue. The package further includes a second underfill between the insulating layer of the package substrate and the package component. The second underfill partially fills the trench. The second underfill does not extend between the edge coupler and the fiber array unit. In an embodiment, the package further includes a support structure on the package substrate adjacent to the first sidewall of the package component, where the fiber array unit is attached to the support structure. In an embodiment, the package component further includes an encapsulant over the redistribution structure, where the optical die and the optical glue are embedded in the encapsulant, and where the encapsulant does not extend between the edge coupler and the optical glue. In an embodiment, the encapsulant does not extend between the edge coupler and the fiber array unit. In an embodiment, the package further includes a heat dissipation lid attached to the package substrate and covering the package component, where the heat dissipation lid includes an opening exposing the fiber array unit. In an embodiment, the package further includes an optical fiber within the opening in the heat dissipation lid and attached to the fiber array unit. In an embodiment, the first sidewall of the package component is vertically aligned to a first sidewall of the trench.

In accordance with yet another embodiment, a method includes forming a package component. Forming the package component includes forming a redistribution structure. A dam structure is formed on the redistribution structure. An optical die is bonded to the redistribution structure. The optical die includes an edge coupler proximate to a first sidewall of the optical die. The first sidewall of the optical die is adjacent to the dam structure. A first underfill is deposited in a first gap between the optical die and the redistribution structure. The first underfill is in physical contact with the dam structure. The first underfill does not extend along the first sidewall of the optical die. An optical glue is formed over the dam structure. The optical glue extends along and is in physical contact with the first sidewall of the optical die. An encapsulant is formed over the optical glue. The optical glue separates the dam structure from the encapsulant. The method further includes forming a trench in an uppermost insulating layer of a package substrate. The package component is bonded to the package substrate. The edge coupler of the optical die is adjacent to the trench. A second underfill is deposited in a second gap between the package component and the package substrate. The second underfill partially fills the trench. The second underfill does not extend along the first sidewall of the optical die. In an embodiment, the method further includes attaching a fiber array unit to the first sidewall of the optical die, where no portion of the first underfill, no portion of the second underfill and no portion of the encapsulant extend between the edge coupler and the fiber array unit. In an embodiment, the method further includes, before attaching the fiber array unit to the first sidewall of the optical die, attaching a support structure to the uppermost insulating layer of the package substrate adjacent to the first sidewall of the optical die, where the fiber array unit is attached to the support structure. In an embodiment, the method further includes attaching a heat dissipation lid to the package substrate, the heat dissipation lid covering the package component, where the heat dissipation lid includes an opening exposing the fiber array unit. In an embodiment, the method further includes attaching an optical fiber to the fiber array unit, where the optical fiber is disposed in the opening of the heat dissipation lid. In an embodiment, the method further includes, before bonding the optical die to the redistribution structure, forming a plurality of conductive connectors on the redistribution structure, where the plurality of conductive connectors and the dam structure are formed in a same process.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.