Patent ID: 12228961

DETAILED DESCRIPTION

The disclosed embodiments relate the design of an asymmetric, source-synchronous clocking system for a clocked memory that facilitates changing a clock frequency without producing gaps in memory traffic. This clocking system generates a multiplied timing signal from a reference timing signal by generating a “burst” comprising multiple timing events for each timing event in the reference timing signal. (A “timing event” can be defined as a change in the timing signal, such as a rising clock edge or a falling clock edge.) For example, each rising edge in the reference timing signal can generate a burst comprising two complete clock cycles in the multiplied timing signal, wherein each complete clock cycle includes a rising edge which constitutes a timing event. In this case, the timing events in a given burst are separated by a bit time, and this bit time does not substantially change when the frequency of the reference timing signal changes. Note that, instead of the bit timing changing, the interval between bursts of timing events changes as the reference clock frequency changes.

The disclosed embodiments may optionally be applied to memory systems for portable devices, where an operating system environment of the portable device dynamically changes clock speed with little or no advance notice. As mentioned previously, in such systems, frequency limitations associated with clock distribution may restrict the bandwidth that can be used for intra-chip or intra-system signaling. Moreover, using a clock multiplier at a destination of a distributed clock can facilitate driving higher bandwidths without suffering from the practical limits in clock distribution frequency. By generating the multiplied clocks in a manner that keeps the bit times substantially constant, the delay between timing events does not significantly change as the frequency of the reference timing signal changes. As a consequence, the bit time can be calibrated at any reference frequency and the calibration will remain valid as the reference frequency changes. This makes it possible to calibrate the bit time without stopping ongoing memory operations.

However, as the reference frequency changes, the interval between bursts of timing events changes, and this change may lead to a slight increase in ISI. To compensate for this increase in ISI, some of the disclosed embodiments nominally increase the bit time when the frequency of the reference timing signal decreases. These embodiments are described in more detail below with reference toFIGS.5A-5B.

Memory System

FIG.1illustrates an exemplary memory system100that uses asymmetric clocking. Memory system100includes a memory controller102which is coupled to a memory device104. Memory controller102receives a reference timing signal CKIN108and uses an asymmetric multiplier circuit110to produce a multiplied timing signal which feeds across a DQS signal line116in channel106to memory device104. Note that channel106also carries DQ signals118. Each of the memory controller and the memory device are optionally embodied as dedicated integrated circuit devices, with the memory device optionally being a discrete random access memory (“DRAM”) integrated circuit device.

As illustrated in the timing diagram in the lower left-hand portion ofFIG.1, each rising edge in CKIN108generates a burst containing two full clock cycles in CK2signal114. Note that CK2signal114is routed into DQS signal line116, which feeds across channel106and is used to clock DQ signals118. As illustrated in the timing diagram in the lower right-hand corner ofFIG.1, when CKIN108transitions to a lower frequency, each rising edge in CKIN108still generates a burst containing two full clock cycles in CK2signal114, However, the bursts become separated by larger time intervals.

As also illustrated inFIG.1, the memory controller transmits CK2to the memory device, which the memory device divides down to regenerate CK1. The memory device then uses CK1for timing of its core operations. That is to say, memory device times its own internal operations using a version of asymmetric clock CK1, regenerated from CK2. The memory device also uses CK2to generate a controller-bound strobe signal, which the memory device transmits to the memory controller in a manner that is source-synchronous with read data. The controller uses this strobe from the memory device to time the sampling of data from the memory device. In one embodiment, read data is transmitted using a serial, differential signal, with the controller deriving both a timing signal for a sampler and a word framing signal from the strobe from the memory device. Note that because the asymmetric multiplier circuit110always generates the same number of transitions in CK2irrespective of variation in rate of CK1, a change in underlying clock frequency does not affect framing boundaries for serially transmitted data words. In the embodiment seen inFIG.1, the strobe path is bidirectional, that is, write data is accompanied by a source synchronous strobe from the memory controller (based on CK2signal114) over DQS signal line116, and read data is accompanied by a source synchronous strobe from the memory device over the DQS signal line116, traveling in the opposite direction.

As noted inFIG.1, the DQ path can further comprise multiple signal lanes, with transmission between memory controller and memory device being in parallel or using a combination of serial and parallel transmission. When parallel communications are used, the controller advantageously includes per lane deskew circuitry as part of its transmit (TDQ) and receive (RDQ) circuits, to align each signal lane to a common phase of DQS signal116.

Clock Multiplication Circuitry

FIG.2Apresents a timing diagram illustrating an un-multiplied timing signal CK1and a multiplied timing signal CK2for a number of different reference clock frequencies (F/1, F/2, F/3and F/4) in accordance with the disclosed embodiments. Each rising edge in the un-multiplied timing signal generates a burst comprising two full clock cycles in the multiplied timing signal, with each clock cycle in the multiplied timing signal being equivalent to two bit intervals “tBIT.” Note that as the reference clock frequency decreases, the bursts are spaced farther apart.

An exemplary circuit that generates bursts for each rising edge in the reference timing signal is illustrated inFIG.2B. In this circuit, a reference timing signal CKIN108feeds through a chain of delay elements202, wherein the delay through two consecutive delay elements is a bit time tBIT. Outputs from some of the delay elements pass through a number of logic gates206-208to produce multiplied CK2signal114. The delay through each of the delay elements in the chain can be adjusted by adjusting delay control signals210. Note that the un-multiplied clock signal, CK1signal115, is adjusted by delay match elements so as to match delays introduced by logic gates206-208.

FIG.2Cillustrates an exemplary delay element220which receives an input signal IN+222and produces a delayed output signal OUT+224. Note that delay element220receives16delay control signals S[7:0] and T[7:0] which are used to adjust the delay through delay element220as is described in more detail below with reference toFIG.10. Also note that each delay element220provides a delay of one-half of a bit interval tBIT/2.

Calibration Circuitry

Delay element220can be calibrated to compensate for “drift” while the memory system is operating by using the circuitry illustrated inFIG.3A. This drift can arise from a number of factors including changes in temperature or operating voltage. The circuitry illustrated inFIG.3Ais designed to calibrate the delay elements at a number of different clock frequencies for reference timing signal CKIN108, namely F/1, F/2, F/3and F/4. During operation, the reference timing signal CKIN108feeds through a delay chain302comprising pairs of delay elements, with all of the delay elements being substantially identical in design (and therefore corresponding to substantially identical time delay). An enable signal END304(generated by a finite state machine (FSM)306) controls the feeding of reference timing signal CKIN108into delay chain302. During operation of the calibration circuitry, as a first rising edge in reference timing signal CKIN108passes through delay chain302, a second rising edge in reference timing signal CKIN108causes a set of latches308to take snapshot of the signal in delay chain302; each latch in the set of latches308transfers its input to its output on a rising edge of its input clock.

A number of these latches308store values Se, Re, Qe and Pe, based on their specific locations in delay chain302; these values enable control logic309to determine which of four clock frequencies (F/1, F/2, F/3or F/4) reference timing signal CKIN108is operating at. The timing diagram which appears in the top portion ofFIG.3Aillustrates how each of the frequencies F/1, F/2, F/3and F/4produces a different pattern of values for signals Se, Re, Qe and Pc.

Other latches in the set of latches308capture timing information for edge transitions associated with different reference clock frequencies, namely E1, E2, E3and E4. In particular, E1is associated with a rising edge for reference frequency F/1, E2is associated with a rising edge for reference frequency F/2, E3is associated with a rising edge for reference frequency F/3, and E4is associated with a rising edge for reference frequency F/4. The table inFIG.3Billustrates how the delay through each of the delay elements is incremented or decremented based on the observed values for Se, Re, Qe and Pe for each of the possible reference clock frequencies. Note that the 16-bit delay control value S[7:0], T[7:0] for the delay elements can be incremented or decremented by one LSB (least-significant bit) by finite state machine (FSM)306.

The circuitry illustrated inFIG.3Acan be extended to operate with a wider range of reference clock frequencies, for example F/1, F/2, F/4, F/8, F/16, F/32and F/64. However, as the range of frequencies gets larger, so too does the supporting circuitry. To reduce the required amount of supporting circuitry, an alternate embodiment (illustrated inFIG.4A) provides a feedback path402that permits a given amount of circuitry to support an extended range of frequencies. As illustrated inFIG.4A, feedback path402effectively extends the size of the delay chain by allowing a clock transition to propagate through the chain of delay elements404multiple times before a snapshot of the reference timing signal is taken by latches406. Note that the set of latches406contains two layers of latches for the signals E0, . . . , E9, and these two layers of latches are activated by different clock edges.

FIG.4Billustrates the timing of signals E0, . . . , E9and F7, . . . . F9relative to the reference timing signal CKIN108. (The dashed lines inFIG.4Brepresent timing markers.) Note that signals F7, . . . , F9are captured on a rising edge of CKINsignal108, whereas signals E0, . . . , E9are captured on a preceding falling edge of CKINsignal108in the upper row in latches406and are subsequently outputted from latches406on the following rising edge of CKINsignal108. Also note that the timing relationships shown inFIG.4Bwill remain approximately constant as CKIN108is scaled over a64:1frequency range.FIG.4Balso indicates when the increment and decrement signals are generated for the delay elements. The feedback loop latency is very fast so the delay control value can be updated every 2-4 cycles of CKIN108. In contrast,FIG.4Cpresents an associated table which shows how the delay elements are adjusted based on the latched values for each of the possible reference clock frequencies. Note thatFIG.4Cis analogous toFIG.3B, and it show how the13sampled signals (F9:F7and E9:E0) determine both the current operating frequency and whether the delay value should be incremented or decremented. The “0/1” entries in the table inFIG.4Bindicate that the latched value is indeterminate because of a rising edge transition, and the “1/0” entries indicate that the latched value is indeterminate because of a falling edge transition.

Finally,FIG.4Dillustrates how the signals E0, . . . , E9and signals F7, . . . . F9are associated with rising and falling clock edges for different reference clock frequencies F/1, F/2, F/4, F/8, F/16, F/32and F/64. Note thatFIG.4Dis drawn as if tCKINis constant and the tDdelay value becomes smaller. In fact, tCKINwill scale over a range of 64:1 and the tDdelay value of the delay element will remain approximately constant.FIG.4Dis drawn with tCKINconstant to see the repeated looping of the CKINsignal108through the delay chain once the enable signal EN430is asserted. For example, in the F/8case, EN430is asserted high, and the next rising edge of CKIN108propagates through the delay chain to the C[5] point. The signal continues to the end of the delay chain and is inverted and propagates through the chain to become a falling edge at C[5] a time 9*tDlater. This process is repeated two more times, so that a characteristic pattern of 1's and 0's may be sampled on the E0, . . . , E9and F7, . . . . F9signals at the falling edge of tCKIN(including the E5signal which contains the increment/decrement indication). Note that the length of the loop was chosen to be 9*tDso that the set of reference clock frequencies F/1, F/2, F/4, F/8, F/16, F/32and F/64would each give a unique set of sampled values at the falling edge of tCKIN.

Note that if the system supports the extended range of reference clock frequencies F/1, F/2, F/4, F/8, F/16, F/32and F/64that the circuitry ofFIG.2Bbecomes slightly more complex, with an extended chain of delay elements202, additional instances of logic gates206-208, and a multiplexer to select between these instances. Delay matching for CK1is also extended so as to match any latency in generating CK2.

Compensating for ISI

As mentioned above, when the reference clock frequency changes, the interval between bursts of timing events changes, and this change can potentially cause a slight increase in ISI, for example due to different transmission line reflections caused by the frequency change. To compensate for this potential increase in ISI, some of the disclosed embodiments nominally increase the bit time when the frequency of the reference timing signal decreases. This provides additional timing margin to deal with potential ISI problems. For example,FIG.5Aillustrates how the bit time tBITcan be lengthened whenever the reference clock frequency is less than F/1. Note that the resulting bursts, which comprise two clock cycles, lengthen to provide more timing margin for potential ISI problems.

Circuitry which implements this bit time lengthening is illustrated inFIG.5B. Note that the clock multiplying circuit illustrated inFIG.5Bis the same as the clock multiplying circuitry illustrated inFIG.2B, except that the circuit includes additional adders502, which add a small constant value to the delay values produced by offset logic508, and these increased delay values increase the delay times through delay elements506. This small constant value is generated by control logic associated with finite state machine (FSM)510. Making the small constant value larger provides more time to allow ISI problems to dissipate before a subsequent clock edge samples the next data value. The optimal size of this small constant value can be determined empirically by increasing the small constant value and observing the effect of the increase on error rate. When the error rate fall within an acceptable range, the small constant value does not have to be increased further.

In one implementation, the adjustment made to the delay times is only made once, as the clock falls below (or conversely rises above) F/1, using a constant value. The amount of adjustment is relatively small relative to a single period of signal CK1at F/1, i.e., it is typically a constant of less than 10% of this period and thus does not represent a significant change in a bit time of signal CK2, which is substantially invariant for all supported frequencies of signal CK1.

Process of Generating a Multiplied Clock Frequency

FIG.6Apresents a flow chart illustrating how a multiplied timing signal is produced in accordance with the disclosed embodiments. First, the system receives a reference timing signal (step602). Next, the system produces a multiplied timing signal from the reference timing signal by generating a burst comprising multiple timing events for each timing event in the reference timing signal, wherein consecutive timing events in each burst of timing events are separated by a bit time (step604). Then, as the reference clock frequency changes, the interval between bursts of timing events changes while the bit time remains substantially constant (step606).

FIG.6Bpresents a flow chart illustrating how delay elements are calibrated in accordance with the disclosed embodiments. First, the system feeds a reference timing signal through a chain of adjustable delay elements (step612). The chain of adjustable delay elements can include a set of latches which simultaneously latch the reference timing signal at selected locations along the chain. Next, the system determines a frequency of the reference timing signal by examining values in the set of latches after the reference timing signal has been latched (step614). Then, the system uses the determined frequency to identify an expected location along the chain for a preceding timing event in the reference timing signal when a new timing event enters the chain (step616). Finally, the system calibrates the delay elements by iteratively (1) using a new timing event to latch a value for the reference timing signal at the expected location, and (2) adjusting a delay through each of the adjustable delay elements based on the latched value (step618).

Delay Element

FIG.7illustrates the internal structure of a digitally controlled delay element700in accordance with the disclosed embodiments. The goal of delay element700is to produce an overall delay (from IN+702to OUTB1+704nodes) that matches the tDparameter (one-half the bit time interval tBIT), which in this example is about 0.3 ns. As illustrated inFIG.7, delay element700receives an input IN+702and produces outputs two OUTB1+704and OUTB2+705. These two equivalent outputs are provided so one can be used to drive the input of a subsequent delay element and the other can be used to provide a buffered copy of the delay element's output; the latter copy can be used to drive other logic without disturbing the accuracy of the delay that is produced. Delay element700also includes a delay chain706coupled to input IN+702. The delay chain comprises inverter pairs which include a set of taps for selecting signals between the inverter pairs. Delay element700also includes two multiplexers (MUXes), including MUX M0708and MUX M1710. MUX M0708is coupled to the set of taps and selects an “early signal” from a given tap in the delay chain. MUX M1710is also coupled to the set of taps and selects an associated “late signal” from a following tap in the delay chain, wherein the following tap immediately follows the given tap in the delay chain. Note that the delay chain taps are given equivalent loads, including the dummy buffer loads attached to the d[0] and d[8] output signals which couple to just one multiplexer input instead of two multiplexer inputs as the d[1] through d[7] output signals do.

Delay element700also includes an interpolator707which interpolates between the early signal and the late signal. The interpolator includes a plurality of current paths that selectively couple either the early signal or the late signal to the output. Note that adjusting interpolator707involves adjusting a number of current paths which are coupled to the early signal and a number of current paths which are coupled to the late signal. The control signals T[7:0] provide a thermometer code which specifies how may current paths are coupled to the early signal and how many are coupled to the late signal. If all of the current paths are coupled to the early signal, the output of the interpolator is simply the early signal. Similarly, if all of the current paths are coupled to the late signal, the output of the interpolator is simply the late signal. On the other hand, if some of the current paths are coupled to the early signal and some of the current paths are coupled to the late signal, the output of the interpolator is between the early signal and the late signal, and the thermometer code in T[7:0] can be used to adjust where the output of the interpolator falls between the early signal and the late signal. The operations of these current paths is described in more detail below with reference toFIG.9A.

FIG.8illustrates the internal structure of a multiplexer800, such as multiplexers708and710, in accordance with the disclosed embodiments. MUX M0800receives eight select signals S[0]-S[7] and eight data inputs. For MUX708, the eight data inputs are d[0]+ to d[7]+, and for MUX M1710, the eight data inputs are d[1]+ to d[8]+. The select signals S[0] to S[7] are “one hot” which means that only one of the select signals is asserted and the rest are not asserted. When a specific select signal is asserted, the associated data signal pulls the output802either to VDDor ground. Note that multiplexer800implements a conventional CMOS circuit topology, in which the output (in the steady state) is pulled high through active PMOS devices, or pulled low through active NMOS devices.

FIG.9Aillustrates the internal structure of an interpolator900in accordance with the disclosed embodiments. Interpolator900allows delay element700to provide 8 incremental delay settings between early signal M0−902and late signal M1−904. This enables delay element700to provide finer resolution than what can be provided by a signal delay element in delay chain706. More specifically, interpolator900receives as inputs: (1) early signal M0−902, (2) late signal M1−904, and (2) an enable signal E+906. Interpolator900uses these inputs to produce two outputs OUTB1+704and OUTB2+705, which carry the same signal. OUTB1+704feeds to a next delay element in a chain of delay elements, whereas OUTB2+705provides a tap that can be used to sample the output signal from the delay element. Interpolator900also receives eight control values T[0]-T[7], wherein the eight control values T[0]-T[7] which provide a thermometer code identifying the number of current paths that couple the output to the early signal or the late signal.

During operation of interpolator circuit900, the enable signal E+906shuts off either the NMOS transistors or the PMOS transistors, wherein the NMOS transistors are shut off during rising edge transitions and the PMOS transistors are shut off during the falling edge transitions. This helps to prevent the NMOS transistors and the PMOS transistors from interfering with each other during these transitions. Interpolator900also includes a weak “keeper” circuit which maintains the output of interpolator900at either VDDor ground. This keeper circuit ensures that the output of the interpolator does spuriously switch multiple times during a rising or falling edge transition for the output signal.

FIG.9Bpresents a timing diagram for interpolator circuit900in accordance with the disclosed embodiments. As can be seen in the timing diagram inFIG.9Band in associatedFIG.7, input signal IN+702feeds through delay chain706, and the multiplexers708and710select an early signal M0+912and a late signal M1+914. In this example, the early signal is from the d[1] delay element (inverter pair) and the late signal is from the d[2] delay element. These early and late signals feed through interpolator706to produce an output signal OUTB1+704. Note that enable signal E+906is low during the rising edge transition, which shuts off the NMOS transistors and activates the PMOS transistors in interpolator707. Conversely, enable signal E+906is high during the subsequent falling edge transition, which shuts off the PMOS transistors and activates the NMOS transistors in interpolator707. This prevents the pull-up interpolation and the pull-down interpolation circuits from interfering with each other by preventing the corresponding PMOS and NMOS transistors from sourcing and sinking current at the same time.

FIG.10Aillustrates updating circuitry for a delay element which provides a glitch-less update in accordance with the disclosed embodiments. In order to avoid glitches in the output of the delay element, the circuitry updates the control values S[7:0] and T[7:0] at specific times. To facilitate this glitch-less update, the delay element700illustrated inFIG.10Ais coupled to a set of dynamic holding latches1001, which hold control values S[7:0] and T[7:0]. These holding latches only change values when the signal LDST-1003is asserted. Note that LDSTZsignal1003is generated from LDSTX1006, LDSTY1008and CKIN-X1010signals, each received from the illustrated state machine. The delay element700generates signals F+712and E+714. AlthoughFIG.7shows the F+ signal712being driven from the IN+ node, it is also possible to tap F+ signal712off the unused buffer from the d[0] signal from the first “d” element in delay chain706; this will avoid impacting delay chain706.

The circuitry illustrated inFIG.10Aensures that holding latches1001only change values when it is safe to do so, without causing glitches. Note that glitches can potentially arise if an input signal transition passes through a delay element while the control values S[7:0] and T[7:0] for the delay element are changing. In this case, the input signal transition can potentially cause multiple output signal transitions from the delay element. The timing for the circuitry illustrated inFIG.10Ais illustrated in the timing diagram which appears inFIG.10B. Note that the new values for S[7:0] and T[7:0] are latched only when CKIN-X1010is low and LDSTX1006, LDSTY1008, F+712and E+714are all asserted. This is accomplished by the incremental logic added to delay element700(shown in the1004box), which allows the control values SF [7:0] and TF [7:0] to update the S[7:0] and T[7:0] at the earliest possible time, regardless of the relative timing of the IN+702/OUTB1+704pulsing and the CKINclock domain.

More specifically, in each delay element700, the F+ signal712is used to sample the CKIN-Xtiming signal1010. The sampled CKIN-X1010signal controls whether an extra half clock of delay is added to the LDSTWsignal1011(the LDSTY1008case) or no delay is added (LDSTX1006case). The appropriate LDST value is loaded by the E+ signal714, and is then used to produce the LDSTZsignal1014. LDSTZ, in turn, opens the holding latches1001, allowing the updated control value to flow through to the delay element700. This new control value will be used for the next edge that appears on IN+107. Note that this circuitry ensures that the control value will never change while an IN+702edge is propagating through the delay element700.

FIG.11presents a flow chart illustrating how a delay element operates in accordance with the disclosed embodiments. First, the system feeds an input signal through a delay chain. The delay chain comprises inverter pairs including a set of taps which tap signals between the inverter pairs (step1102). Next, the system uses a first multiplexer which is coupled to the set of taps to select an early signal from a first tap in the delay chain (step1104). The system also uses a second multiplexer which is coupled to the set of taps to select a late signal from a second tap in the delay chain. The second tap immediately follows the first tap in the delay chain (step1106). Finally, the system uses an interpolator to interpolate between the early signal and the late signal. The interpolator includes a plurality of current paths which selectively couple one of the early signal and the late signal to the output. The interpolator is adjusted using a number of current paths which are coupled to the early signal and a number of current paths which are coupled to the late signal.

The preceding description was presented to enable any person skilled in the art to make and use the disclosed embodiments, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the disclosed embodiments. Thus, the disclosed embodiments are not limited to the embodiments shown, but are to be accorded the widest scope consistent with the principles and features disclosed herein. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art. Additionally, the above disclosure is not intended to limit the present description. The scope of the present description is defined by the appended claims.

Also, some of the above-described methods and processes can be embodied as code and/or data, which can be stored in a computer-readable storage medium as described above. When a computer system reads and executes the code and/or data stored on the computer-readable storage medium, the computer system performs the methods and processes embodied as data structures and code and stored within the computer-readable storage medium. Furthermore, the methods and apparatus described can be included in but are not limited to, application-specific integrated circuit (ASIC) chips, field-programmable gate arrays (FPGAs), and other programmable-logic devices.