Patent ID: 12191249

DETAILED DESCRIPTION

The following description provides specific details, such as material compositions, shapes, and sizes, in order to provide a thorough description of embodiments of the disclosure. However, a person of ordinary skill in the art would understand that the embodiments of the disclosure may be practiced without employing these specific details. Indeed, the embodiments of the disclosure may be practiced in conjunction with conventional microelectronic device fabrication techniques employed in the industry. In addition, the description provided below does not form a complete process flow for manufacturing a microelectronic device (e.g., a memory device, such as NAND Flash memory device). The structures described below do not form a complete microelectronic device. Only those process acts and structures necessary to understand the embodiments of the disclosure are described in detail below. Additional acts to form a complete microelectronic device from the structures may be performed by conventional fabrication techniques.

Drawings presented herein are for illustrative purposes only, and are not meant to be actual views of any particular material, component, structure, device, or system. Variations from the shapes depicted in the drawings as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes or regions as illustrated, but include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as box-shaped may have rough and/or nonlinear features, and a region illustrated or described as round may include some rough and/or linear features. Moreover, sharp angles that are illustrated may be rounded, and vice versa. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of a region and do not limit the scope of the claims. The drawings are not necessarily to scale. Additionally, elements common between figures may retain the same numerical designation.

As used herein, a “memory device” means and includes a microelectronic device exhibiting memory functionality, but not necessarily limited to memory functionality. Stated another way, and by way of non-limiting example only, the term “memory device” includes not only conventional memory (e.g., conventional non-volatile memory, such as conventional NAND memory; conventional volatile memory, such as conventional dynamic random access memory (DRAM)), but also includes an application specific integrated circuit (ASIC) (e.g., a system on a chip (SoC)), a microelectronic device combining logic and memory, and a graphics processing unit (GPU) incorporating memory.

As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” are in reference to a major plane of a structure and are not necessarily defined by earth's gravitational field. A “horizontal” or “lateral” direction is a direction that is substantially parallel to the major plane of the structure, while a “vertical” or “longitudinal” direction is a direction that is substantially perpendicular to the major plane of the structure. The major plane of the structure is defined by a surface of the structure having a relatively large area compared to other surfaces of the structure. With reference to the figures, a “horizontal” or “lateral” direction may be perpendicular to an indicated “Z” axis, and may be parallel to an indicated “X” axis and/or parallel to an indicated “Y” axis; and a “vertical” or “longitudinal” direction may be parallel to an indicated “Z” axis, may be perpendicular to an indicated “X” axis, and may be perpendicular to an indicated “Y” axis.

As used herein, features (e.g., regions, materials, structures, devices) described as “neighboring” one another means and includes features of the disclosed identity (or identities) that are located most proximate (e.g., closest to) one another. Additional features (e.g., additional regions, additional materials, additional structures, additional devices) not matching the disclosed identity (or identities) of the “neighboring” features may be disposed between the “neighboring” features. Stated another way, the “neighboring” features may be positioned directly adjacent one another, such that no other feature intervenes between the “neighboring” features; or the “neighboring” features may be positioned indirectly adjacent one another, such that at least one feature having an identity other than that associated with at least one of the “neighboring” features is positioned between the “neighboring” features. Accordingly, features described as “vertically neighboring” one another means and includes features of the disclosed identity (or identities) that are located most vertically proximate (e.g., vertically closest to) one another. Moreover, features described as “horizontally neighboring” one another means and includes features of the disclosed identity (or identities) that are located most horizontally proximate (e.g., horizontally closest to) one another.

As used herein, reference to an element as being “on” or “over” another element means and includes the element being directly on top of, directly adjacent to (e.g., directly laterally adjacent to, directly vertically adjacent to), directly underneath, or in direct contact with the other element. It also includes the element being indirectly on top of, indirectly adjacent to (e.g., indirectly laterally adjacent to, indirectly vertically adjacent to), indirectly underneath, or near the other element, with other elements present therebetween. In contrast, when an element is referred to as being “directly on” or “directly adjacent to” another element, there are no intervening elements present.

As used herein, spatially relative terms, such as “beneath,” “below,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” “right,” and the like, may be used for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Unless otherwise specified, the spatially relative terms are intended to encompass different orientations of the materials in addition to the orientation depicted in the figures. For example, if materials in the figures are inverted, elements described as “below” or “beneath” or “under” or “on bottom of” other elements or features would then be oriented “above” or “on top of” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below, depending on the context in which the term is used, which will be evident to one of ordinary skill in the art. The materials may be otherwise oriented (e.g., rotated 90 degrees, inverted, flipped) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

As used herein, “and/or” includes any and all combinations of one or more of the associated listed items.

As used herein, the term “configured” refers to a size, shape, material composition, orientation, and arrangement of one or more of at least one structure and at least one apparatus facilitating operation of one or more of the structure and the apparatus in a pre-determined way.

As used herein, the phrase “coupled to” refers to structures operatively connected with each other, such as electrically connected through a direct Ohmic connection or through an indirect connection (e.g., by way of another structure).

As used herein, the term “substantially” in reference to a given parameter, property, or condition means and includes to a degree that one of ordinary skill in the art would understand that the given parameter, property, or condition is met with a degree of variance, such as within acceptable tolerances. By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be at least 90.0 percent met, at least 95.0 percent met, at least 99.0 percent met, at least 99.9 percent met, or even 100.0 percent met.

As used herein, “about” or “approximately” in reference to a numerical value for a particular parameter is inclusive of the numerical value and a degree of variance from the numerical value that one of ordinary skill in the art would understand is within acceptable tolerances for the particular parameter. For example, “about” or “approximately” in reference to a numerical value may include additional numerical values within a range of from 90.0 percent to 108.0 percent of the numerical value, such as within a range of from 95.0 percent to 105.0 percent of the numerical value, within a range of from 97.5 percent to 102.5 percent of the numerical value, within a range of from 99.0 percent to 101.0 percent of the numerical value, within a range of from 99.5 percent to 100.5 percent of the numerical value, or within a range of from 99.9 percent to 100.1 percent of the numerical value.

As used herein, “conductive material” means and includes electrically conductive material, such as one or more of a metal (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pd), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), an alloy (e.g., a Co-based alloy, an Fe-based alloy, an Ni-based alloy, an Fe- and Ni-based alloy, a Co- and Ni-based alloy, an Fe- and Co-based alloy, a Co- and Ni- and Fe-based alloy, an Al-based alloy, a Cu-based alloy, a magnesium (Mg)-based alloy, a Ti-based alloy, a steel, a low-carbon steel, a stainless steel), a conductive metal-containing material (e.g., a conductive metal nitride, a conductive metal silicide, a conductive metal carbide, a conductive metal oxide), and a conductively-doped semiconductor material (e.g., conductively-doped polysilicon, conductively-doped germanium (Ge), conductively-doped silicon germanium (SiGe)). In addition, a “conductive structure” means and includes a structure formed of and including a conductive material.

As used herein, “insulative material” means and includes electrically insulative material, such one or more of at least one dielectric oxide material (e.g., one or more of a silicon oxide (SiOx), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, an aluminum oxide (AlOx), a hafnium oxide (HfOx), a niobium oxide (NbOx), a titanium oxide (TiOx), a zirconium oxide (ZrOx), a tantalum oxide (TaOx), and a magnesium oxide (MgOx)), at least one dielectric nitride material (e.g., a silicon nitride (SiNy)), at least one dielectric oxynitride material (e.g., a silicon oxynitride (SiOxNy)), and at least one dielectric carboxynitride material (e.g., a silicon carboxynitride (SiOxCzNy)). Formulae including one or more of “x,” “y,” and “z” herein (e.g., SiOx, AlOx, HfOx, NbOx, TiOx, SiNy, SiOxNy, SiOxCzNy) represent a material that contains an average ratio of “x” atoms of one element, “y” atoms of another element, and “z” atoms of an additional element (if any) for every one atom of another element (e.g., Si, Al, Hf, Nb, Ti). As the formulae are representative of relative atomic ratios and not strict chemical structure, an insulative material may comprise one or more stoichiometric compounds and/or one or more non-stoichiometric compounds, and values of “x,” “y,” and “z” (if any) may be integers or may be non-integers. As used herein, the term “non-stoichiometric compound” means and includes a chemical compound with an elemental composition that cannot be represented by a ratio of well-defined natural numbers and is in violation of the law of definite proportions. In addition, an “insulative structure” means and includes a structure formed of and including an insulative material.

As used herein, the term “homogeneous” means relative amounts of elements included in a feature (e.g., a material, a structure) do not vary throughout different portions (e.g., different horizontal portions, different vertical portions) of the feature. Conversely, as used herein, the term “heterogeneous” means relative amounts of elements included in a feature (e.g., a material, a structure) vary throughout different portions of the feature. If a feature is heterogeneous, amounts of one or more elements included in the feature may vary stepwise (e.g., change abruptly), or may vary continuously (e.g., change progressively, such as linearly, parabolically) throughout different portions of the feature. The feature may, for example, be formed of and include a stack of at least two different materials.

As used herein, the term “amorphous,” when referring to a material, means and refers to a material having a substantially noncrystalline structure.

As used herein, the term “sacrificial,” when used in reference to a material or structure, means and includes a material, structure, or a portion of a material or structure that is formed during a fabrication process but which is at least partially removed (e.g., substantially removed) prior to completion of the fabrication process.

As used herein, the term “high-k dielectric material” means and includes a dielectric oxide material having a dielectric constant greater than the dielectric constant of silicon dioxide (SiO2). The high-k dielectric material may include a high-k oxide material, a high-k metal oxide material, or a combination thereof. By way of example only, the high-k dielectric material may be aluminum oxide, gadolinium oxide, hafnium oxide, niobium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium silicate, a combination thereof, or a combination of one or more of the listed high-k dielectric materials with silicon oxide.

As used herein, the term “selectively etchable” means and includes a material that exhibits a greater etch rate responsive to exposure to a given etch chemistry relative to another material exposed to the same etch chemistry. For example, the material may exhibit an etch rate that is at least about three times (3×) greater than the etch rate of another material, such as about five times (5×) greater than the etch rate of another material, such as an etch rate of about ten times (10×) greater, about twenty times (20×) greater, or about forty times (40×) greater than the etch rate of the another material. Etch chemistries and etch conditions for selectively etching a desired material may be selected by a person of ordinary skill in the art.

Unless otherwise specified, materials described herein may be formed by conventional techniques including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced ALD, physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), or low pressure chemical vapor deposition (LPCVD). Alternatively, the materials may be grown in situ. Depending on the specific material to be formed, the technique for depositing or growing the material may be selected by a person of ordinary skill in the art. The removal of materials may be accomplished by any suitable technique including, but not limited to, etching, abrasive planarization (e.g., chemical-mechanical planarization), or other known methods unless the context indicates otherwise.

FIGS.1A through13Bare simplified, partial top-down views (FIGS.1A,2A,3A,4A,5A,6A,7A,8A,9A,10A,11A,12A, and13A) and simplified, partial cross-sectional views (FIGS.1B,1C,2B,2C,3B,3C,4B,4C,5B,5C,5D,6B,6C,6D,7B,7C,7D,8B,8C,8D,9B,9C,9D,10B,10C,10D,11B,11C,11D,12B,12C,12D, and13B) illustrating different processing stages of a method of forming a microelectronic device (e.g., a memory device, such as a three-dimensional (3D) NAND Flash memory device), in accordance with embodiments of the disclosure.FIG.13Aillustrates an enlarged portion of the top-down view of box A ofFIG.12A, andFIG.13Billustrates an enlarged portion of the cross-sectional view of box B ofFIG.12B. With the description provided below, it will be readily apparent to one of ordinary skill in the art that the methods and structures described herein with reference toFIGS.1A through13Bmay be used in the formation and configuration of various devices and electronic systems. In other words, the methods of the disclosure may be used whenever it is desired to form a microelectronic device. For convenience in describingFIGS.1A through13B, a first horizontal direction may be defined as the X-direction shown in some ofFIGS.1A through13B; a second horizontal direction transverse (e.g., orthogonal, perpendicular) to the first horizontal direction may be defined as the Y-direction shown in some ofFIGS.1A through13B; and a third direction (e.g., a vertical direction) transverse (e.g., orthogonal, perpendicular) to each of the first horizontal direction and the second horizontal direction may be defined as the Z-direction shown in some ofFIGS.1A through13B. Similar directions are shown in14, which is discussed in further detail below.

With reference toFIG.1A, a microelectronic device structure100may be formed to include a preliminary stack structure102(FIGS.1B and1C) and a dielectric material116overlying the preliminary stack structure102. The microelectronic device structure100may include a staircase region105including a staircase structure, as described in further detail with reference toFIGS.2A through2C. The microelectronic device structure100may also include an array region horizontally (e.g., in the X-direction) neighboring the staircase region105. For example, the array region may include memory pillar structures (e.g., cell pillar structures) employed as memory cells (e.g., strings of NAND memory cells), as described in further detail with reference toFIG.14. While not illustrated inFIGS.1A through13B, features of the array region of the microelectronic device structure100may be formed during (e.g., substantially simultaneous with) formation of corresponding features of the staircase region105. The preliminary stack structure102of the staircase region105is described in further detail below, along with additional components (e.g., structures, features) of the microelectronic device structure100at the processing stage depicted inFIG.1A.FIG.1Bis a simplified, partial cross-sectional view of the microelectronic device structure100about the line B-B shown inFIG.1A, andFIG.1Cis a simplified, partial cross-sectional view of the microelectronic device structure100about the line C-C shown inFIG.1A. For clarity and ease of understanding of the drawings and related description, not all features depicted in one ofFIGS.1A through1Care depicted in each of the others ofFIGS.1A through1C.

Referring toFIGS.1B and1C, the preliminary stack structure102may be formed to include a vertically alternating (e.g., in the Z-direction) sequence of insulative structures104(also referred to herein as “insulative levels”) and additional insulative structures106(also referred to herein as “additional insulative levels”) arranged in tiers108. Each of the tiers108of the preliminary stack structure102may include at least one (1) of the insulative structures104vertically neighboring at least one (1) of the additional insulative structures106. The insulative structures104may be interleaved with the additional insulative structures106.

The insulative structures104of the preliminary stack structure102may be formed of and include at least one insulative material. In some embodiments, the insulative structures104are formed of and include silicon dioxide (SiO2). Each of the insulative structures104may individually include a substantially homogeneous distribution or a substantially heterogeneous distribution of the at least one insulative material. The insulative structures104may each be substantially planar, and may each independently exhibit any desired thickness. In addition, each of the insulative structures104may be substantially the same (e.g., exhibit substantially the same material composition, material distribution, size, and shape) as one another, or at least one of the insulative structures104may be different (e.g., exhibit one or more of a different material composition, a different material distribution, a different size, and a different shape) than at least one other of the insulative structures104. In some embodiments, each of the insulative structures104is substantially the same as each other of the insulative structures104.

The additional insulative structures106may be formed of and include at least one insulative material that is different than, and that exhibits etch selectivity with respect to, the insulative structures104. For example, the additional insulative structures106may individually be formed of and include at least one dielectric nitride material (e.g., SiNy) or at least one oxynitride material (e.g., SiOxNy). In some embodiments, the additional insulative structures106are formed of and include Si3N4. Each of the additional insulative structures106may individually include a substantially homogeneous distribution or a substantially heterogeneous distribution of the at least one additional insulative material. The additional insulative structures106may serve as sacrificial structures for the subsequent formation of conductive structures, as described in further detail below.

AlthoughFIGS.1B and1Cillustrate a particular quantity of tiers108of the insulative structures104and the additional insulative structures106, the disclosure is not so limited. In some embodiments, the preliminary stack structure102includes a desired quantity of the tiers108, such as within a range from thirty-two (32) of the tiers108to two hundred fifty-six (256) of the tiers108. In some embodiments, the preliminary stack structure102includes sixty-four (64) of the tiers108. In other embodiments, the preliminary stack structure102includes a different quantity of the tiers108, such as less than sixty-four (64) of the tiers108(e.g., less than or equal to sixty (60) of the tiers108, less than or equal to fifty (50) of the tiers108, less than or equal to forty (40) of the tiers108, less than or equal to thirty (30) of the tiers108, less than or equal to twenty (20) of the tiers108, less than or equal to ten (10) of the tiers108); or greater than sixty-four (64) of the tiers108(e.g., greater than or equal to seventy (70) of the tiers108, greater than or equal to one hundred (100) of the tiers108, greater than or equal to about one hundred twenty-eight (128) of the tiers108, greater than or equal to two hundred fifty-six (256) of the tiers108) of the insulative structures104and the additional insulative structures106. In addition, in some embodiments, the preliminary stack structure102overlies a deck structure comprising additional tiers108of insulative structures104and the additional insulative structures, separated from the preliminary stack structure102by at least one dielectric material, such as an interdeck insulative material.

With continued reference toFIGS.1B and1C, the microelectronic device structure100further includes a source tier110vertically underlying (e.g., in the Z-direction) the preliminary stack structure102. The source tier110may comprise, for example, a first conductive material112and a second conductive material114. In some embodiments, the first conductive material112comprises conductively-doped silicon. In some such embodiments, the second conductive material114is formed of and include one or more of a metal silicide material (e.g., tungsten silicide (WSix)), a metal nitride material (e.g., tungsten nitride), and a metal silicon nitride material (e.g., tungsten silicon nitride (WSixNy)). In some embodiments, the second conductive material114comprises tungsten silicide.

The dielectric material116, which may serve as a mask material, may vertically (e.g., in the Z-direction) overlie a vertically uppermost tier108of the insulative structures104and the additional insulative structures106of the preliminary stack structure102. The dielectric material116may comprise one or more of the materials described above with reference to the insulative structures104. In some embodiments, the dielectric material116comprises silicon dioxide.

In some embodiments, the source tier110is formed to include one or more source structures118(e.g., a source plate) horizontally extending into a horizontal area of the staircase region105. Source structures118may be operatively associated with vertically extending strings of memory cells within a memory array region of the microelectronic device structure100, as described in further detail below. The source structures118may be formed of and include the first conductive material112and the second conductive material114, and may be electrically isolated from other portions of the first conductive material112and the second conductive material114(e.g., other portions employed as conductive routing structures117and/or as conductive pad structures) by insulative material119.

Referring collectively toFIGS.2A through2C, at least one staircase structure120(FIGS.2B and2C) may be formed within the staircase region105of the preliminary stack structure102(FIGS.2B and2C). A first insulative liner material127and a second insulative liner material128may be formed to vertically (e.g., in the Z-direction) overlie the staircase structure120, and then a dielectric fill material126may be formed to fill at least one valley124(e.g., space, gap, trench, opening) vertically overlying the staircase structure120. The dielectric fill material126may be formed to laterally intervene (e.g., in the X-direction) between portions of the dielectric material116, as shown inFIG.2A.FIGS.2B and2Care simplified, partial cross-sectional views of the microelectronic device structure100(about the line B-B and the line C-C, respectively) at the processing stage shown inFIG.2A. For clarity and ease of understanding of the drawings and related description, not all features depicted in one ofFIGS.2A through2Care depicted in each of the others ofFIGS.2A through2C.

As shown inFIGS.2B and2C, the staircase structure120may be formed to include steps122comprising edges (e.g., horizontal ends) of the tiers108of the insulative structures104and additional insulative structures106. AlthoughFIG.2Billustrates two (2) of the tiers108of the insulative structures104and the additional insulative structures106corresponding to one (1) step122of the staircase structure120, the quantity of steps122of the staircase structure120may correspond to the quantity of tiers108, such that a single (e.g., only one) step122corresponds to one of the tiers108. The staircase structure120(and the valley124at least partially defined by the staircase structure120) include a stepped cross-sectional profile in the ZY-plane, as shown inFIG.2B. The stepped cross-sectional profile of the staircase structure120(and of the valley124) may be defined by the geometric configurations of the steps122of the staircase structure120.

For clarity and ease of understanding the description,FIG.2Billustrates only a particular quantity of steps122in the staircase structure120. However, it will be understood that the staircase structure120may include a greater quantity of steps122than those illustrated. For example, the staircase structure120may include greater or equal to eight (8) of the steps122, greater than or equal to sixteen (16) of the steps122, greater than or equal to thirty-two (32) of the steps122, greater than or equal to sixty-four (64) of the steps122, greater than or equal to one-hundred and twenty-eight (128) of the steps122, or greater than or equal to two-hundred and fifty-six (256) of the steps122.

In some embodiments, the staircase structure120forms a portion of a stadium structure including opposing staircase structures120each having steps122defined by horizontal ends of the tiers108of the preliminary stack structure102. In some such embodiments, multiple (e.g., more than one) stadium structures individually including one or more initial staircase structures may be formed to be positioned at substantially the same elevations (e.g., vertical locations) as one another within the preliminary stack structure102. During formation of the steps122of the staircase structure120, an initial staircase structure (e.g., configured substantially similar to the staircase structure120) may be formed at an upper vertical position within the preliminary stack structure102within horizontal boundaries of the staircase region105of the microelectronic device structure100using conventional processes (e.g., conventional photolithographic patterning processes, conventional material removal processes), and conventional processing equipment, which are not described in detail herein. The microelectronic device structure100may then be subjected to one or more additional material removal processes (e.g., one or more chopping processes) to increase the depth(s) (e.g., in the Z-direction) of the initial staircase structure relative to an upper surface of the preliminary stack structure102and form the staircase structure120. The staircase structure120may be substantially similar to the initial staircase structure used to form the staircase structure120, except located at a relatively lower vertical position within the microelectronic device structure100(e.g., within the preliminary stack structure102). The additional material removal processes may permit a lower boundary of the staircase structure120to be positioned at or below a lower boundary of the preliminary stack structure102.

In some embodiments, upper regions of the valley124(e.g., corresponding to the upper vertical position of the initial staircase structure within the preliminary stack structure102) include substantially linear, elongated openings vertically overlying the steps122of the staircase structure120, as shown inFIG.2C. In some such embodiments, the valley124is vertically extended into the preliminary stack structure102using at least one material removal process (e.g., at least one chopping process) to terminate vertically below a location of the initial staircase structure and form the staircase structure120. In additional embodiments, each of the tiers108of the preliminary stack structure102includes one or more steps122of the staircase structure120therein, and substantially linear, elongated openings are not formed above the staircase structure120. In some embodiments, a lowermost boundary of the valley124is defined by two of the steps122extending in the X-direction, as shown inFIG.2C. In additional embodiments, the lowermost boundary of the valley124is defined by a single (e.g., only one) step122extending in the X-direction.

With continued reference toFIGS.2B and2C, the first insulative liner material127may, optionally, be formed to vertically (e.g., in the Z-direction) overlie the staircase structure120, the vertically uppermost tier108of the insulative structures104and the additional insulative structures106. In addition, the second insulative liner material128may be formed to vertically overlie the first insulative liner material127. As shown inFIG.2B, the second insulative liner material128may include upper portions128aand side portions128bproximate to and intervening between neighboring portions of the upper portions128a. For example, the upper portions128amay horizontally extend across (e.g., in the Y-direction) and substantially cover upper surfaces of the steps122, and the side portions128bmay vertically extend across (e.g., in the Z-direction) and substantially cover side surfaces of the steps122. The second insulative liner material128may be formed to include a substantially continuous material (e.g., a substantially continuous liner material) on or over the steps122of the staircase structure120.

The first insulative liner material127, if present, may be formed of and include at least one insulative material, such as one or more of the materials described above with reference to the insulative structures104. In some embodiments, the first insulative liner material127comprises substantially the same material composition as the insulative structures104. In other embodiments, the first insulative liner material127comprises a different material composition than the insulative structures104. In some embodiments, the first insulative liner material127comprises silicon dioxide. In additional embodiments, the first insulative liner material127is formed of and includes a high-k dielectric material. The first insulative liner material127may have a thickness (e.g., height) in the vertical direction (e.g., in the Z-direction) within a range from about 10 nanometers (nm) to about 80 nm, such as from about 10 nm to about 20 nm, from about 20 nm to about 40 nm, from about 40 nm to about 60 nm, or from about 60 nm to about 80 nm. For convenience, the first insulative liner material127is absent in subsequent views of the drawings, although it is understood that the first insulative liner material127may be present in additional embodiments of the disclosure.

The second insulative liner material128may exhibit etch selectivity relative to the dielectric material116, the dielectric fill material126, and the first insulative liner material127. The second insulative liner material128may be formed of and include one or more of the materials described above with reference to the additional insulative structures106. In some embodiments, the second insulative liner material128comprises substantially the same material composition as the additional insulative structures106. In other embodiments, the second insulative liner material128comprises a different material composition than the additional insulative structures106. The second insulative liner material128may, alternatively, be formed of and include one or more of silicon oxycarbide (SiOxCy), silicon oxynitride (SiOxNy), hydrogenated silicon oxycarbide (SiCxOyHz), or silicon oxycarbonitride (SiOxCyNz). The second insulative liner material128may include a low-k dielectric material, such as a dielectric nitride material or a dielectric oxide material, having a dielectric constant (k) lower than the dielectric constant of a silicon nitride (Si3N4) material, of a silicon oxide (SiOx, SiO2) material, or of a carbon-doped silicon oxide material that includes silicon atoms, carbon atoms, oxygen atoms, and hydrogen atoms.

In additional embodiments, the second insulative liner material128is formed of and includes a high-k dielectric material. The second insulative liner material128may, for example, be formed of and include a high-k dielectric oxide, such as one or more of aluminum oxide (AlOx), hafnium oxide (HfOx), niobium oxide (NbOx), zirconium oxide (ZrOx), titanium oxide (TiOx), and tantalum oxide (TaOx), or a combination of a non-high-k dielectric oxide (e.g., SiOx) and one or more high-k dielectric oxides. In some embodiments, the second insulative liner material128is formed of and includes hafnium-doped silicon dioxide, where the ratio of hafnium to silicon is controlled to achieve a desired etch selectivity of the high-k dielectric material of the second insulative liner material128. The second insulative liner material128may also exhibit etch selectivity relative to the insulative structures104of the tiers108of the preliminary stack structure102, as well as the second conductive material114of the source tier110. In some such embodiments, the second insulative liner material128is formed of and includes a nitride material having a material composition that differs from that of the additional insulative structures106, although other materials of the second insulative liner material128may be contemplated, so long as the second insulative liner material128exhibits etch selectivity relative to each of the dielectric material116, the dielectric fill material126, the first insulative liner material127(FIG.2B), the insulative structures104, and the second conductive material114, as well as additional materials (e.g., conductive materials, additional insulative materials formed during subsequent processing of the microelectronic device structure100).

As shown inFIG.2B, the upper portion128aof the second insulative liner material128may be formed to include a sacrificial portion140(e.g., a sacrificial plug) formulated to be removed during subsequent processing acts and a remaining portion142designated to remain on or over the steps122of the staircase structure120. The remaining portion142of the upper portions128aof the second insulative liner material128may be located horizontally proximate to and at least partially surrounding the sacrificial portion140thereof. As will be described herein, the sacrificial portion140of the upper portions128aof the second insulative liner material128may be replaced with another material (e.g., a conductive material of strapping structures174(FIG.12B)).

The second insulative liner material128may have a thickness T1(e.g., height) in the vertical direction within a range from about 10 nm to about 100 nm, such as from about 10 nm to about 20 nm, from about 20 nm to about 40 nm, from about 40 nm to about 60 nm, from about 60 nm to about 80 nm, or from about 80 nm to about 100 nm. In some embodiments, the thickness T1is about 80 nm. In some embodiments, the thickness T1of the second insulative liner material128may be greater than a thickness of the first insulative liner material127. Accordingly, the first insulative liner material127and the second insulative liner material128may have a combined thickness (e.g., height) in the vertical direction within a range from about 10 nm to about 180 nm, for example. The thickness T1of the second insulative liner material128may be tailored to facilitate use of the second insulative liner material128as the sacrificial material, and subsequently a thickness of structures (e.g., the strapping structures174) to be formed within regions vacated by the sacrificial portion140of the upper portions128aof the second insulative liner material128.

The second insulative liner material128may be formed by one or more of CVD, ALD, plasma enhanced ALD, PVD, PECVD, or LPCVD. In some embodiments, the second insulative liner material128is formed at a temperature greater than about 600° C., such as greater than about 650° C. In some embodiments, the second insulative liner material128is formed at a temperature of about 680° C. In some embodiments, forming the second insulative liner material128at a temperature greater than about 600° C. (e.g., about 680° C.) may increase a density of the second insulative liner material128relative to the density of the first insulative liner material127formed at lower temperatures. The increased density of the second insulative liner material128may increase etch selectivity of the second insulative liner material128relative to the first insulative liner material127. By way of comparison, liner materials formed at lower temperatures (e.g., about 570° C.) may exhibit a reduced etch selectivity relative to other insulative liner materials.

Referring now toFIG.3A, first openings130(e.g., contact openings) may be formed to vertically extend (e.g., in the Z-direction) through the dielectric fill material126and the preliminary stack structure102(FIGS.3B and3C), such as through the dielectric fill material126and the tiers108of the insulative structures104and the additional insulative structures106within the staircase region105. Formation of the first openings130is described in further detail below, along with additional components (e.g., structures, features) of the microelectronic device structure100at the processing stage depicted inFIG.3A.FIG.3Bis a simplified, partial cross-sectional view of the microelectronic device structure100about the line B-B shown inFIG.3A, andFIG.3Cis a simplified, partial cross-sectional view of the microelectronic device structure100about the line C-C shown inFIG.3A. For clarity and ease of understanding of the drawings and related description, not all features depicted in one ofFIGS.3A through3Care depicted in each of the others ofFIGS.3A through3C.

Referring toFIGS.3B and3C, the first openings130(e.g., initial first openings) may be formed to extend through the preliminary stack structure102. At least portions of each of the dielectric fill material126, the second insulative liner material128, the first insulative liner material127(FIG.2B), if present, the insulative structures104, and the additional insulative structures106are removed by exposing the respective materials to wet etch and/or dry etch chemistries, for example, in one or more material removal processes. Portions of the initial material of the second insulative liner material128(e.g., central portions of the sacrificial portion140(FIG.2B)) may be removed (e.g., etched) in one or more material removal processes resulting in a dimension (e.g., width) of each of the first openings130being relatively less than that of the upper portions128aof the second insulative liner material128(e.g., corresponding to upper surfaces of the steps122of the staircase structure120). Additional portions of the sacrificial portion140and the remaining portion142of the upper portions128aof the second insulative liner material128may remain on the upper surfaces of the steps122of the staircase structure120following formation of the first openings130. Further, the first openings130extend beyond the upper surfaces of the steps122of the staircase structure120and through the materials of the preliminary stack structure102. Accordingly, the first openings130may be formed to extend from an upper surface of the dielectric fill material126to the source tier110underlying the preliminary stack structure102. In other words, the first openings130extend entirely through a vertical extent (e.g., a height) of the preliminary stack structure102, as shown inFIGS.3B and3C. Thus, a height of each of the first openings130in the vertical direction (e.g., the Z-direction) may be substantially similar to (e.g., substantially the same as) one another irrespective of horizontal orientation relative to the steps122of the staircase structure120. Manufacturing processes may be simplified by forming the first openings130to extend entirely through the vertical extent of the preliminary stack structure102, without forming the first openings130to extend to varying (e.g., differing) depths corresponding to various locations of individual steps122of the staircase structure120.

The first conductive material112of the source tier110may act as an etch stop material during removal of each of the dielectric fill material126, the second insulative liner material128, the first insulative liner material127(FIG.2B), the insulative structures104, and the additional insulative structures106, and formation of the first openings130. In some such embodiments, the first openings130terminate within the source tier110, such as at or within the first conductive material112at the processing stage depicted inFIGS.3B and3C. In other embodiments, the first openings130terminate at or within an insulative material overlying the first conductive material112. In additional embodiments, the first openings130extend through the first conductive material112and terminate at or within the second conductive material114. By way of non-limiting example, the first openings130may terminate at or within the first conductive material112at the process stage shown inFIGS.3A through3C, and fourth openings131(FIG.10B) may terminate at or within the second conductive material114through subsequent processing of the microelectronic device structure100. As will be described herein, the fourth openings131may be used to form conductive contacts (e.g., conductive contacts172(FIG.12B)) in contact with conductive contact structures (e.g., the strapping structures174(FIG.12B)) of the staircase structure120.

Referring next toFIG.4A, a first sacrificial material132may be formed within the first openings130(FIG.3A) to form first sacrificial structures133. The first sacrificial material132of the first sacrificial structures133is described in further detail below, along with additional components (e.g., structures, features) of the microelectronic device structure100at the processing stage depicted inFIG.4A.FIG.4Bis a simplified, partial cross-sectional view of the microelectronic device structure100about the line B-B shown inFIG.4A, andFIG.4Cis a simplified, partial cross-sectional view of the microelectronic device structure100about the line C-C shown inFIG.4A. For clarity and ease of understanding of the drawings and related description, not all features depicted in one ofFIGS.4A through4Care depicted in each of the others ofFIGS.4A through4C.

Referring toFIGS.4B and4C, prior to forming the first sacrificial structures133within the first openings130(FIG.3B), lateral (e.g., in the X-direction, in the Y-direction) portions of the additional insulative structures106may be selectively removed through the first openings130to form recessed regions134. By way of non-limiting example, exposed portions of the additional insulative structures106may be exposed to an etchant (e.g., a wet etchant) through the first openings130to selectively remove portions of the additional insulative structures106with respect to the insulative structures104. In some embodiments, the additional insulative structures106are exposed to phosphoric acid (H3PO4) to selectively remove portions of the additional insulative structures106proximate the first openings130.

After selectively removing portions of the additional insulative structures106proximate the first openings130(FIG.3B), a liner material136may be formed within selected portions of the first openings130(e.g., within the recessed regions134proximate remaining portions of the additional insulative structures106) without fully filling the first openings130. For example, the liner material136may be formed within the recessed regions134to effectively “pinch off” and close (e.g., seal) the recessed regions134immediately adjacent to the first openings130. The liner material136may be formed to extend between vertically neighboring insulative structures104proximate the recessed regions134, such that the liner material136substantially vertically fills portions of the recessed regions134proximate the first openings130without entirely filling the first openings130. The liner material136is formed by conventional techniques, such as one or more of in situ growth, CVD, ALD, and PVD using conventional processing equipment. In some embodiments, the liner material136may be formed (e.g., deposited) using a single, continuous ALD process or a single, continuous CVD process. In other embodiments, an initial material (e.g., a silicon nitride material of the additional insulative structures106) may be oxidized to form the liner material136.

The liner material136may comprise one or more of the materials described above with reference to the insulative structures104. In some embodiments, the liner material136comprises silicon dioxide. The liner material136may be formed of and include at least one insulative material that is different than, and that exhibits etch selectivity with respect to, one or more of the additional insulative structures106and the second insulative liner material128. In some embodiments, the liner material136is formed of and includes a single high quality silicon oxide material, such as an ALD SiOx. For example, the liner material136may be a highly uniform and highly conformal silicon oxide material (e.g., a highly uniform and highly conformal silicon dioxide material) so that substantially no voids are present in the liner material136. In particular, the liner material136may be formulated to be formed in high aspect ratio (HAR) openings, such as those having a HAR of at least about 20:1, at least about 50:1, at least about 100:1, or at least about 1000:1, without forming voids. The liner material136may, alternatively, be formed of and include one or more of silicon oxycarbide (SiOxCy), silicon oxynitride (SiOxNy), hydrogenated silicon oxycarbide (SiCxOyHz), or silicon oxycarbonitride (SiOxCyNz). The liner material136may include a low-k dielectric material, such as a dielectric nitride material or a dielectric oxide material, having a dielectric constant (k) lower than the dielectric constant of a silicon nitride (Si3N4) material, of a silicon oxide (SiOx, SiO2) material, or of a carbon-doped silicon oxide material that includes silicon atoms, carbon atoms, oxygen atoms, and hydrogen atoms. In other embodiments, the liner material136may include another metal oxide, such as zirconium oxide (ZrOx), tantalum oxide (TaOx), or magnesium oxide (MgOx), for example.

Formation of the liner material136within the recessed regions134may result in formation of isolation regions146between the first openings130(FIG.3B) and the additional insulative structures106, such that the additional insulative structures106are remote (e.g., isolated) from the first openings130by the isolation regions146. Stated another way, process acts may be selected to provide (e.g., facilitate, promote) formation of the liner material136within the recessed regions134proximate the first openings130for formation of the isolation regions146between the horizontally neighboring additional insulative structures106and subsequently formed materials (e.g., the first sacrificial material132of the first sacrificial structures133) within the first openings130.

After forming the liner material136, the first sacrificial material132of the first sacrificial structures133may be formed within remaining portions of the first openings130(FIG.3B). The first sacrificial material132may substantially fill the first openings130and may be in contact with each of the dielectric fill material126, the second insulative liner material128, the first insulative liner material127(FIG.2B), as well as the liner material136of the recessed regions134and the insulative structures104of the preliminary stack structure102. Accordingly, the first sacrificial structures133may be formed to extend from the upper surface of the dielectric fill material126to the source tier110underlying the preliminary stack structure102. The first sacrificial structures133may terminate at (e.g., land on) the first conductive material112of the source tier110, for example, without terminating at the second conductive material114. Alternatively, the first sacrificial structures133may terminate at or within an insulative material overlying the first conductive material112. After forming the first sacrificial material132, the microelectronic device structure100may be exposed to a chemical mechanical planarization (CMP) process to remove sacrificial material outside of the first openings130.

Once formed, each of the first sacrificial structures133may vertically extend completely through the preliminary stack structure102, as shown inFIGS.4B and4C. For example, the first sacrificial material132of the first sacrificial structures133may vertically extend (e.g., in the Z-direction) from a vertically uppermost boundary of the dielectric fill material126(e.g., at an elevational level of a vertically uppermost tier108of the preliminary stack structure102) to or beyond a vertically uppermost boundary of the first conductive material112of the source tier110, without terminating on the steps122of the staircase structure120. Accordingly, the steps122of the staircase structure120are free of additional contact structures terminating thereon.

The first sacrificial material132may be formed of and include at least one material exhibiting etch selectivity with respect to each of the dielectric fill material126, the second insulative liner material128, the first insulative liner material127(FIG.2B), the insulative structures104, the liner material136, and one or more materials of the source tier110(e.g., the first conductive material112), as well as additional materials (e.g., additional conductive materials) formed during subsequent processing of the microelectronic device structure100. In some embodiments, the first sacrificial material132comprises conductive material. By way of non-limiting example, the first sacrificial material132may be formed of and include one or more of polysilicon, tungsten, titanium, titanium nitride, aluminum oxide, or another material. In some embodiments, the first sacrificial material132comprises amorphous silicon or polycrystalline silicon. In some such embodiments, the first sacrificial material132may be doped with one or more dopants, such as with at least one N-type dopant (e.g., one or more of arsenic, phosphorous, antimony, and bismuth) or at least one P-type dopant (e.g., one or more of boron, aluminum, and gallium). In other embodiments, the first sacrificial material132comprises tungsten.

Referring next toFIG.5A, second openings144(e.g., support structure openings, pillar openings) may be formed to vertically extend (e.g., in the Z-direction) through the dielectric material116and the preliminary stack structure102(FIGS.5B through5D), such as through the dielectric material116, the dielectric fill material126, and the tiers108of the insulative structures104and the additional insulative structures106. Slots160(also referred to herein as “replacement gate slots”) may also be formed through the preliminary stack structure102to facilitate the replacement of the additional insulative structures106with conductive structures. Formation of the second openings144and the slots160is described in further detail below, along with additional components (e.g., structures, features) of the microelectronic device structure100at the processing stage depicted inFIG.5A.FIG.5Bis a simplified, partial cross-sectional view of the microelectronic device structure100about the line B-B shown inFIG.5A,FIG.5Cis a simplified, partial cross-sectional view of the microelectronic device structure100about the line C-C shown inFIG.5A, andFIG.5Dis a simplified, partial cross-sectional view of the microelectronic device structure100about the line D-D shown inFIG.5A. For clarity and ease of understanding of the drawings and related description, not all features depicted in one ofFIGS.5A through5Dare depicted in each of the others ofFIGS.5A through5D.

As shown inFIG.5A, the second openings144may horizontally (e.g., in the X-direction, in the Y-direction) neighbor the first sacrificial structures133(shown in dashed lines). For example, the second openings144may be horizontally aligned in columns extending in the Y-direction with individual second openings144positioned out of horizontal alignment (e.g., staggered) with individual first sacrificial structures133horizontally aligned in additional columns extending in the Y-direction. At least some of the second openings144may be horizontally aligned with each other (e.g., in the X-direction, in the Y-direction) and horizontally offset from the first sacrificial structures133(e.g., in the Y-direction), although other configurations of the second openings144relative to the first sacrificial structures133may be contemplated.

Referring toFIGS.5B through5D, the second openings144(e.g., initial second openings) and the slots160(e.g., initial slots) may be formed to extend through each of the dielectric material116and the preliminary stack structure102. At least portions of each of the dielectric material116, the dielectric fill material126, the second insulative liner material128, the first insulative liner material127(FIG.2B), the insulative structures104, and the additional insulative structures106are removed by exposing the respective materials to wet etch and/or dry etch chemistries, for example, in one or more material removal processes. Prior to formation of the second openings144and the slots160, portions of the dielectric fill material126and the preliminary stack structure102may be covered with an additional dielectric material (e.g., an additional portion of the dielectric material116) and/or an additional mask material configured and positioned to protect the dielectric fill material126and the first sacrificial material132of the first sacrificial structures133from being removed (e.g., exhumed) during the material removal processes of the dielectric material116and the materials of the preliminary stack structure102. For ease of understanding the disclosure, the additional dielectric material overlying the preliminary stack structure102is hereinafter collectively referred to as the dielectric material116. The second openings144may be formed in the staircase region105. The second openings144may terminate within the source tier110, such as at or within the first conductive material112at the processing stage depicted inFIGS.5B through5D. Alternatively, the second openings144may terminate at or within an insulative material overlying the first conductive material112.

The slots160may be formed to vertically extend (e.g., in the Z-direction) though the preliminary stack structure102, such as through the dielectric material116, the second insulative liner material128, the first insulative liner material127(FIG.2B), and the tiers108of the insulative structures104and the additional insulative structures106. The slots160may extend to the source tier110, such as to or within the first conductive material112. Alternatively, the slots160may terminate at or within an insulative material overlying the first conductive material112. The slots160may separate (e.g., divide) the microelectronic device structure100into block structures162. AlthoughFIG.5Aillustrates only three slots160and only two block structures162, the disclosure is not so limited. The microelectronic device structure100may include a plurality of (e.g., four, five, six, eight) block structures162, each separated from laterally neighboring (e.g., in the Y-direction) block structures162by a slot160. In other words, the slots160may divide the microelectronic device structure100into any desired quantity of block structures162. The slots160may or may not be formed during (e.g., substantially simultaneous with) formation of the second openings144in order to simplify manufacturing processes.

Referring next toFIG.6A, a second sacrificial material148may be formed within the second openings144(FIG.5A) to form second sacrificial structures150and an additional portion of the second sacrificial material148may be formed within the slots160(FIG.5A) to form third sacrificial structures151. The second sacrificial material148of the second sacrificial structures150and the third sacrificial structures151is described in further detail below, along with additional components (e.g., structures, features) of the microelectronic device structure100at the processing stage depicted inFIG.6A.FIG.6Bis a simplified, partial cross-sectional view of the microelectronic device structure100about the line B-B shown inFIG.6A,FIG.6Cis a simplified, partial cross-sectional view of the microelectronic device structure100about the line C-C shown inFIG.6A, andFIG.6Dis a simplified, partial cross-sectional view of the microelectronic device structure100about the line D-D shown inFIG.6A. For clarity and ease of understanding of the drawings and related description, not all features depicted in one ofFIGS.6A through6Dare depicted in each of the others ofFIGS.6A through6D.

Referring toFIGS.6B through6D, the second sacrificial material148may substantially fill the second openings144(FIG.5D) and the slots160(FIGS.5C and5D). The third sacrificial structures151may or may not be formed during (e.g., substantially simultaneous with) formation of the second sacrificial structures150in order to simplify manufacturing processes. The second sacrificial material148may be in contact with each of the dielectric material116, the dielectric fill material126, the second insulative liner material128, the first insulative liner material127(FIG.2B), and the tiers108of the insulative structures104and the additional insulative structures106. Accordingly, the second sacrificial structures150and the third sacrificial structures151may be formed to extend from the upper surface of the dielectric material116to the source tier110underlying the preliminary stack structure102. Each of the second sacrificial structures150and the third sacrificial structures151may terminate at (e.g., land on) the first conductive material112of the source tier110, for example, without terminating at the second conductive material114. Alternatively, each of the second sacrificial structures150and the third sacrificial structures151may terminate at or within an insulative material overlying the first conductive material112. In additional embodiments, the second sacrificial structures150are formed within the second openings144without forming the third sacrificial structures151within the slots160, such that the slots160remain open at the process stage ofFIGS.6A through6D. After forming the second sacrificial material148, the microelectronic device structure100may be exposed to a chemical mechanical planarization (CMP) process to remove sacrificial material outside of the second openings144and the slots160.

The second sacrificial material148may be formed of and include at least one material exhibiting etch selectivity with respect to each of the dielectric material116, the dielectric fill material126, the second insulative liner material128, the first insulative liner material127(FIG.2B), the insulative structures104, the additional insulative structures106, and one or more materials of the source tier110(e.g., the first conductive material112), as well as additional materials (e.g., additional conductive materials) formed during subsequent processing of the microelectronic device structure100. In some embodiments, the second sacrificial material148of the second sacrificial structures150and the third sacrificial structures151comprises the same material composition as the first sacrificial material132of the first sacrificial structures133(e.g., amorphous silicon or polycrystalline silicon).

Referring next toFIG.7A, following formation of the second sacrificial structures150and the third sacrificial structures151(FIG.6A), the third sacrificial structures151may be removed (e.g., exhumed) to again form the slots160extending vertically through the preliminary stack structure102(FIGS.7B through7D) so as to facilitate the replacement of the additional insulative structures106(FIGS.7B through7D) with conductive structures152(FIGS.8B through8D). The reformation of the slots160is described in further detail below, along with additional components (e.g., structures, features) of the microelectronic device structure100at the processing stage depicted inFIG.7A.FIG.7Bis a simplified, partial cross-sectional view of the microelectronic device structure100about the line B-B shown inFIG.7A,FIG.7Cis a simplified, partial cross-sectional view of the microelectronic device structure100about the line C-C shown inFIG.7A, andFIG.7Dis a simplified, partial cross-sectional view of the microelectronic device structure100about the line D-D shown inFIG.7A. For clarity and ease of understanding of the drawings and related description, not all features depicted in one ofFIGS.7A through7Dare depicted in each of the others ofFIGS.7A through7D.

Referring toFIGS.7B through7D, the second sacrificial material148of the third sacrificial structures151(FIG.6A) may be removed to again form the slots160(corresponding to the size, shape, and location of the initial slots). The slots160may terminate within the source tier110, such as at or within the first conductive material112at the processing stage depicted inFIGS.7B through7D. Prior to again forming the slots160, the first sacrificial structures133may be covered with an additional dielectric material (e.g., an additional portion of the dielectric material116) and/or an additional mask material configured and positioned to protect the first sacrificial material132of the first sacrificial structures133from being removed (e.g., exhumed) during the material removal processes of the second sacrificial material148of the third sacrificial structures151, as shown inFIG.7B. In some embodiments, the second sacrificial structures150are also covered with an additional dielectric material (e.g., an additional portion of the dielectric material116) and/or an additional mask material configured and positioned to protect the second sacrificial material148of the second sacrificial structures150from being removed (e.g., exhumed) during the material removal processes of the second sacrificial material148of the third sacrificial structures151. Accordingly, portions of the second sacrificial material148of the third sacrificial structures151may be removed without removing additional portions of the second sacrificial material148of the second sacrificial structures150.

The slots160may vertically extend (e.g., in the Z-direction) though the preliminary stack structure102at the process stage ofFIGS.7A through7D, such as through the dielectric material116, the second insulative liner material128, the first insulative liner material127(FIG.2B), and the tiers108of the insulative structures104and the additional insulative structures106. The slots160may extend to the source tier110, such as to the first conductive material112. In additional embodiments, the slots160remain open prior to the process stage ofFIGS.7A through7D, such as when the second sacrificial structures150are formed within the second openings144(FIG.5A) without forming the third sacrificial structures151within the slots160at the process stage ofFIGS.6A through6D.

Referring next toFIG.8A, the additional insulative structures106(FIG.7B) may be at least partially (e.g., substantially) replaced with the conductive structures152comprising at least one conductive material156to form a stack structure155comprising tiers154of the conductive structures152vertically interleaved with the insulative structures104through so-called “replacement gate” or “gate last” processing acts. The slots160(FIG.7A) may then be filled with dielectric material164. Formation of the conductive structures152is described in further detail below, along with additional components (e.g., structures, features) of the microelectronic device structure100at the processing stage depicted inFIG.8A.FIG.8Bis a simplified, partial cross-sectional view of the microelectronic device structure100about the line B-B shown inFIG.8A,FIG.8Cis a simplified, partial cross-sectional view of the microelectronic device structure100about the line C-C shown inFIG.8A, andFIG.8Dis a simplified, partial cross-sectional view of the microelectronic device structure100about the line D-D shown inFIG.8A. For clarity and ease of understanding of the drawings and related description, not all features depicted in one ofFIGS.8A through8Dare depicted in each of the others ofFIGS.8A through8D.

Referring toFIGS.8B through8D, the additional insulative structures106(FIG.7B) may be selectively removed (e.g., exhumed) through the slots160(FIG.7A). Spaces between vertically neighboring (e.g., in the Z-direction) insulative structures104may be filled with the conductive material156to form the conductive structures152and the stack structure155including the tiers154of the insulative structures104and the conductive structures152. In some embodiments, a conductive liner material158is formed within the spaces between the vertically neighboring insulative structures104. In some such embodiments, the conductive structures152individually comprise the conductive liner material158in contact with the insulative structures104and the conductive material156in contact with the conductive liner material158. The conductive liner material158may be vertically interposed between the conductive material156and an insulative structure104. For ease of illustration and understanding, the conductive liner material158is illustrated within a single space between the vertically neighboring insulative structures104inFIG.8B, but it will be understood that the microelectronic device structure100may include the conductive liner material158within additional (e.g., each of the) spaces between the vertically neighboring insulative structures104. The conductive structures152may be located at locations corresponding to the locations of the additional insulative structures106removed through the slots160.

In some embodiments, the conductive material156of the conductive structures152comprises tungsten (W). In other embodiments, the conductive material156of the conductive structures152comprises conductively doped polysilicon. For each of the conductive structures152, the conductive material156thereof may be substantially homogeneous or may be substantially heterogeneous. In some embodiments, each of the conductive structures152is substantially homogeneous. In additional embodiments, at least one of the conductive structures152is substantially heterogeneous.

The conductive liner material158(if formed) surrounding the conductive structures152may be formed of and include, for example, at least one seed material from which the conductive material156may be formed. The conductive liner material158may be formed of and include, for example, one or more of at least one metal (e.g., titanium, tantalum), at least one metal nitride (e.g., tungsten nitride, titanium nitride, tantalum nitride), or at least one additional material. In some embodiments, the conductive liner material158comprises titanium nitride (TiNx).

At least one vertically (e.g., in the Z-direction) lower conductive structure152of the stack structure155may be employed as at least one lower select gate (e.g., at least one source side select gate (SGS)) of the microelectronic device structure100. In some embodiments, a single (e.g., only one) conductive structure152of a vertically lowermost tier154of the stack structure155is employed as a lower select gate (e.g., a SGS) of the microelectronic device structure100. In addition, vertically (e.g., in the Z-direction) upper conductive structure(s)152of the stack structure155may be employed as upper select gate(s) (e.g., drain side select gate(s) (SGDs)) of the microelectronic device structure100. In some embodiments, horizontally neighboring conductive structures152of a vertically uppermost tier154of the stack structure155(e.g., separated from each other by slots) are employed as upper select gates (e.g., SGDs) of the microelectronic device structure100. In some embodiments, more than one (e.g., two, four, five, six) conductive structures152are employed as upper select gates (e.g., SGDs) of the microelectronic device structure100.

The first sacrificial structures133and the second sacrificial structures150may serve as support structures during and/or after the formation of one or more components of the microelectronic device structure100. For example, the first sacrificial structures133and the second sacrificial structures150may serve as support structures for the formation of the conductive structures152during replacement of the additional insulative structures106(FIG.7B) to form the conductive structures152. The first sacrificial structures133and the second sacrificial structures150may impede (e.g., prevent) tier collapse during the selective removal of the additional insulative structures106. By forming the first sacrificial structures133to extend entirely through the vertical extent of the preliminary stack structure102(e.g., below the steps122of the staircase structure120), lower portions of the first sacrificial structures133may provide additional support to lowermost portions of the preliminary stack structure102, compared to conventional device structures having conductive contacts that terminate at steps of staircase structures. Further, formation of the first sacrificial structures133and the second sacrificial structures150prior to performing replacement gate processing acts may provide increased structural support within the staircase structure120of the staircase region105, without undesirably increasing the overall width (e.g., horizontal footprint) of the staircase region105.

As shown inFIG.8B, the presence of the liner material136within the recessed regions134provides isolation regions176(e.g., corresponding to locations of the isolation regions146(FIG.4B)) between the first sacrificial structures133and the conductive structures152, such that the conductive structures152are remote (e.g., isolated) from the first sacrificial material132of the first sacrificial structures133by the isolation regions176. After forming the conductive material156and the conductive liner material158of the conductive structures152of the stack structure155, the slots160(FIG.7A) may be filled with the dielectric material164, as shown inFIGS.8C and8D.

The dielectric material164may be formed of and include at least one insulative material, such as one or more of at least one dielectric oxide material (e.g., one or more of SiOx, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, AlOx, HfOx, NbOx, TiOx, ZrOx, TaOx, and MgOx), at least one dielectric nitride material (e.g., SiNy), at least one dielectric oxynitride material (e.g., SiOxNy), and at least one dielectric carboxynitride material (e.g., SiOxCzNy). A material composition of the dielectric material164may be substantially the same as a material composition of one or more of the dielectric material116and the insulative structures104of the stack structure155, or the material composition of the dielectric material164may be different than the material composition of the dielectric material116and insulative structures104. In some embodiments, the dielectric material164is formed of and includes silicon dioxide.

Referring next toFIG.9A, following formation of the dielectric material164within the slots160(FIG.7A), the second sacrificial material148(FIG.8D) of the second sacrificial structures150(FIG.8D) may be removed (e.g., exhumed) to form third openings145within horizontal areas of the second openings144(FIGS.5A and5D) and extending vertically through the stack structure155(FIG.9B) to the source tier110(FIG.9B). A liner material170aof support structures170(e.g., pillar structures) (FIG.9D) may be formed in the third openings145. Formation of the third openings145and the liner material170aof support structures170is described in further detail below, along with additional components (e.g., structures, features) of the microelectronic device structure100at the processing stage depicted inFIG.9A.FIG.9Bis a simplified, partial cross-sectional view of the microelectronic device structure100about the line B-B shown inFIG.9A,FIG.9Cis a simplified, partial cross-sectional view of the microelectronic device structure100about the line C-C shown inFIG.9A, andFIG.9Dis a simplified, partial cross-sectional view of the microelectronic device structure100about the line D-D shown inFIG.9A. For clarity and ease of understanding of the drawings and related description, not all features depicted in one ofFIGS.9A through9Dare depicted in each of the others ofFIGS.9A through9D.

Referring toFIGS.9B through9D, to form the third openings145, the second sacrificial material148(FIG.8D) of the second sacrificial structures150(FIG.8D) and portions of the first conductive material112may be removed. The third openings145may extend through the first conductive material112and may terminate at or within the second conductive material114. In some such embodiments, a so-called “punch through” etch is then performed to remove portions of the first conductive material112and expose the underlying portions of the second conductive material114or, alternatively, remove portions of an insulative material overlying the first conductive material112and expose the underlying portions of the first conductive material112.

Prior to forming the third openings145, each of the dielectric fill material126and the first sacrificial structures133may be covered with an additional dielectric material (e.g., an additional portion of the dielectric material116) and/or an additional mask material configured and positioned to protect the dielectric fill material126and the first sacrificial material132of the first sacrificial structures133from being removed (e.g., exhumed) during the material removal processes of the second sacrificial material148of the second sacrificial structures150. Accordingly, portions of the second sacrificial material148of the second sacrificial structures150may be removed without removing portions of the first sacrificial material132of the first sacrificial structures133and without removing portions of the dielectric material164within the slots160(FIG.7A). Since the second sacrificial material148of the second sacrificial structures150exhibits etch selectivity relative to the insulative structures104and the conductive structures152of the tiers154of the stack structure155, portions of the second sacrificial material148of the second sacrificial structures150may also be removed without removing portions of the insulative structures104and the conductive structures152.

As shown inFIG.9D, the liner material170aof the support structures170may be continuous along a vertical dimension (e.g., a vertical height) of the stack structure155. The liner material170amay be formed of and include insulative material, such as a dielectric oxide material. For example, the material of the liner material170amay include a silicon oxide material (e.g., relatively high quality silicon oxide material, such as an ALD SiOx). The liner material170amay be formed by conventional techniques, such as by CVD or ALD. In some embodiments, the liner material170ais formed by plasma enhanced ALD (PEALD).

The liner material170aof the support structures170may be in contact with each of the dielectric material116, the dielectric fill material126, the second insulative liner material128, the first insulative liner material127(FIG.2B), as well as the insulative structures104and the conductive structures152of the stack structure155, and the first conductive material112of the source tier110. Accordingly, the liner material170amay be formed to extend from the upper surface of the dielectric material116to the source tier110underlying the stack structure155. The liner material170aof the support structures170may terminate at or within the second conductive material114of the source tier110. Alternatively, the liner material170amay terminate at or within the first conductive material112.

In some embodiments, each block structure162(FIG.5A) includes three (3) columns of the support structures170located between horizontally (e.g., in the X-direction) neighboring portions of the dielectric material164within the slots160(FIG.7A). However, the disclosure is not so limited and, in other embodiments, each block structure162includes fewer (e.g., two, one) columns of the support structures170; or each block structure162includes more (e.g., four, five, six, seven, eight) columns of the support structures170.

Referring next toFIG.10A, following formation of the liner material170aof the support structures170(FIG.10D) within the third openings145(FIG.10D), a mask material166may be formed over the microelectronic device structure100. The first sacrificial material132(FIG.9B) of the first sacrificial structures133(FIG.9B) may then be removed (e.g., exhumed) to form the fourth openings131within horizontal areas of the first openings130(FIGS.3A through3C) and extending vertically through the stack structure155(FIG.10B) to the source tier110(FIG.10B). Formation of the mask material166and the fourth openings131is described in further detail below, along with additional components (e.g., structures, features) of the microelectronic device structure100at the processing stage depicted inFIG.10A.FIG.10Bis a simplified, partial cross-sectional view of the microelectronic device structure100about the line B-B shown inFIG.10A,FIG.10Cis a simplified, partial cross-sectional view of the microelectronic device structure100about the line C-C shown inFIG.10A, andFIG.10Dis a simplified, partial cross-sectional view of the microelectronic device structure100about the line D-D shown inFIG.10A. For clarity and ease of understanding of the drawings and related description, not all features depicted in one ofFIGS.10A through10Dare depicted in each of the others ofFIGS.10A through10D.

Referring toFIGS.10B through10D, to form the fourth openings131, the first sacrificial material132(FIG.9B) of the first sacrificial structures133(FIG.9B) and portions of the first conductive material112may be removed. The fourth openings131may extend through the first conductive material112and may terminate at or within the second conductive material114at the process stage ofFIGS.10A through10D. In some embodiments, portions of the first conductive material112are removed by so-called punch through etch processes to expose the underlying portions of the second conductive material114or, alternatively, portions of an insulative material overlying the first conductive material112are removed to expose the underlying portions of the first conductive material112.

Prior to forming the fourth openings131, each of the dielectric material116, the liner material170aof the support structures170, and the dielectric material164may be covered with the mask material166configured and positioned to protect the dielectric material116, the liner material170aof the support structures170, and the dielectric material164from being removed (e.g., exhumed) during the material removal processes of the first sacrificial material132(FIG.9B) of the first sacrificial structures133(FIG.9B). Accordingly, portions of the first sacrificial material132of the first sacrificial structures133may be removed without removing portions of the dielectric material116, the liner material170aof the support structures170, and the dielectric material164. Since the first sacrificial material132of the first sacrificial structures133exhibits etch selectivity relative to the insulative structures104of the tiers154of the stack structure155, as well as the liner material136within the recessed regions134, portions of the first sacrificial material132of the first sacrificial structures133may also be removed without removing portions of the insulative structures104and the liner material136.

The mask material166may be formed of and include one or more of amorphous carbon, silicon, a silicon oxide, a silicon nitride, a silicon oxycarbide, aluminum oxide, and a silicon oxynitride. In some embodiments, the mask material166is formed of and includes at least one dielectric oxide material (e.g., one or more of silicon dioxide and aluminum oxide). In other embodiments, the mask material166is formed of and includes silicon nitride. The mask material166may be homogeneous (e.g., may include a single material), or may be heterogeneous (e.g., may include a stack including at least two different materials). The mask material166may be formed using conventional processes and patterned using conventional patterning and material removal processes, such as conventional photolithographic exposure processes, conventional development processes, conventional etching processes and conventional processing equipment, which are not described in detail herein.

Referring next toFIG.11A, after forming the fourth openings131, portions of the upper portions128aof the second insulative liner material128(e.g., the sacrificial portion140thereof (FIG.4B)) may be selectively removed (e.g., exhumed) to form lateral openings168(e.g., lateral recesses) in communication with the fourth openings131. Formation of the lateral openings168is described in further detail below, along with additional components (e.g., structures, features) of the microelectronic device structure100at the processing stage depicted inFIG.11A.FIG.11Bis a simplified, partial cross-sectional view of the microelectronic device structure100about the line B-B shown inFIG.11A,FIG.11Cis a simplified, partial cross-sectional view of the microelectronic device structure100about the line C-C shown inFIG.11A, andFIG.11Dis a simplified, partial cross-sectional view of the microelectronic device structure100about the line D-D shown inFIG.11A. For clarity and ease of understanding of the drawings and related description, not all features depicted in one ofFIGS.11A through11Dare depicted in each of the others ofFIGS.11A through11D.

Referring toFIGS.11B through11D, portions of the second insulative liner material128overlying the steps122of the staircase structure120may be recessed to form the lateral openings168. Recessing the second insulative liner material128increases the horizontal width of the fourth openings131in the stack structure155, forming the lateral openings168adjacent to the second insulative liner material128. For example, additional portions of the sacrificial portion140(FIG.4B) of the individual upper portions128aof the second insulative liner material128may be selectively removed relative to the liner material136within the recessed regions134, to recess the second insulative liner material128a lateral distance. Portions of the first insulative liner material127(FIG.2B), if present, may or may not be removed during formation of the lateral openings168.

In some embodiments, the sacrificial portion140(FIG.4B) of the individual upper portions128aof the second insulative liner material128is removed by exposing the second insulative liner material128to one or more etchants, such as wet etchants, through the first openings130. The wet etchants may include one or more of phosphoric acid, acetic acid, nitric acid, hydrochloric acid, aqua regia, or hydrogen peroxide. In some embodiments, the sacrificial portion140may be removed by a phosphoric acid/acetic acid/nitric acid (PAN) etch chemistry. However, the disclosure is not so limited and the sacrificial portion140of the individual upper portions128aof the second insulative liner material128may be removed with other etchants and/or material removal processes (e.g., vapor phase removal processes, atomic layer removal processes). For example, the sacrificial portion140may be removed by performing a sequence of self-limiting processes of an atomic layer removal process to modify a surface of a material (e.g., the second insulative liner material128), followed by selective removal of the modified surface material. In additional embodiments, the sacrificial portion140is removed by a plasma etching process (e.g., an inductively coupled plasma (ICP) etching process) comprising one or more of hydrogen fluoride (HF), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), or another material. The second insulative liner material128may, optionally, be exposed to hydrogen (H2), nitrogen (N2), oxygen (O2), argon (Ar), or a combination thereof. The sacrificial portion140may, alternatively, be removed by exposure to one or more dry etchants.

Forming the lateral openings168shortens the individual upper portions128aof the second insulative liner material128, and the remaining portion142thereof laterally surrounding the lateral openings168. The sacrificial portion140(FIG.4B) of the individual upper portions128aof the second insulative liner material128vertically adjacent (e.g., underlying) the dielectric fill material126and laterally surrounding the first openings130may be locations designated for the lateral openings168. Accordingly, the lateral openings168are defined in at least one horizontal direction (e.g., the X-direction, the Y-direction) by the remaining portion142of the individual upper portions128aof the second insulative liner material128, and the lateral openings168are defined in the vertical direction (e.g., the Z-direction) by the dielectric fill material126and the liner material136within the recessed regions134, as well as portions of the conductive structures152. By controlling the amount of material removal that occurs, the lateral openings168may extend into a portion of the second insulative liner material128overlying the steps122, enabling subsequent formation of the strapping structures174(FIG.12B) to be formed adjacent to and extending laterally from the conductive contacts172(FIG.12B) subsequently formed within the first openings130, as described in further detail below.

Referring next toFIG.12A, after forming the lateral openings168(FIG.11B), the mask material166may be removed to expose each of the fourth openings131(FIG.11B) and the third openings145(FIG.11D). Thereafter, the strapping structures174(FIGS.12B and12C) may be formed within the lateral openings168, and the conductive contacts172(FIGS.12B and12C) may be formed within the fourth openings131. In addition, a fill material170b(e.g., a conductive material, an insulative material) of the support structures170(FIG.12D) may be formed adjacent to the liner material170awithin the third openings145. The conductive contacts172, the strapping structures174, and the support structures170are described in further detail below, along with additional components (e.g., structures, features) of the microelectronic device structure100at the processing stage depicted inFIG.12A.FIG.12Bis a simplified, partial cross-sectional view of the microelectronic device structure100about the line B-B shown inFIG.12A,FIG.12Cis a simplified, partial cross-sectional view of the microelectronic device structure100about the line C-C shown inFIG.12A, andFIG.12Dis a simplified, partial cross-sectional view of the microelectronic device structure100about the line D-D shown inFIG.12A. For clarity and ease of understanding of the drawings and related description, not all features depicted in one ofFIGS.12A through12Dare depicted in each of the others ofFIGS.12A through12D.

Referring toFIGS.12B through12D, a conductive material of the conductive contacts172may substantially fill the fourth openings131(FIG.11B) and be in contact with each of the dielectric material116, the dielectric fill material126, the first insulative liner material127(FIG.2B), the liner material136within the recessed regions134, and the insulative structures104of the stack structure155, as well as the first conductive material112and the second conductive material114of the source tier110. Accordingly, the conductive contacts172may be formed to extend from the upper surface of the dielectric material116to the source tier110underlying the stack structure155. The conductive contacts172may terminate at or within the second conductive material114of the source tier110. Alternatively, the conductive contacts172may terminate at or within the first conductive material112. In such embodiments, the conductive contacts172are formed to be self-aligned with the underlying conductive materials (e.g., the first conductive material112) using a so-called “assisted self-alignment” process.

Once formed, each of the conductive contacts172may vertically extend completely through the stack structure155without terminating on the steps122of the staircase structure120, as shown inFIGS.12B and12C. For example, conductive contacts172may vertically extend (e.g., in the Z-direction) from a vertically uppermost boundary of the dielectric fill material126(e.g., at an elevational level of a vertically uppermost tier108of the stack structure155) to or beyond a vertically uppermost boundary of the second conductive material114of the source tier110. In some embodiments, the staircase structure120is substantially free of conductive contacts formed to terminate on the steps122thereof.

During formation of the conductive contacts172, the conductive material thereof may also substantially fill the lateral openings168(FIG.11B) to form the strapping structures174. The conductive contacts172may be integral and continuous with the strapping structures174. The strapping structures174may horizontally project outward from the conductive contacts172. The conductive material of the strapping structures174may be in contact with each of the second insulative liner material128(e.g., the remaining portion142of the upper portions128athereof), the liner material136within the recessed regions134, and one or more of the conductive material156and the conductive liner material158of the conductive structures152of the stack structure155. After forming the conductive contacts172and the strapping structures174, the microelectronic device structure100may be exposed to a chemical mechanical planarization (CMP) process to remove sacrificial material outside of the first openings130(FIG.11B).

The conductive contacts172and the strapping structures174may individually be formed of and include at least one conductive material. By way of non-limiting example, the conductive contacts172and the strapping structures174may be formed of and include one or more of polysilicon, tungsten, titanium, titanium nitride, or another material. In some embodiments, the conductive material comprises polysilicon. In some such embodiments, the conductive material may be doped with one or more dopants, such as with at least one N-type dopant (e.g., one or more of arsenic, phosphorous, antimony, and bismuth) or at least one P-type dopant (e.g., one or more of boron, aluminum, and gallium). In other embodiments, the conductive material of the conductive contacts172and the strapping structures174comprises tungsten.

The strapping structures174may be considered portions (e.g., outwardly horizontally projecting portions) of the conductive contacts172. For example, as shown inFIGS.12B and12C, the conductive contacts172may individually include a first portion178in electrical communication with the source tier110, such as with the second conductive material114thereof, without being in electrical communication with all of the conductive structures152of the stack structure155vertically (e.g., in the Z-direction) underlying individual steps122of the staircase structure120. In addition, the conductive contacts172may also individually include a second portion180, corresponding to one of the strapping structures174, in electrical communication with the first portion178and with the conductive material156of one of the conductive structures152. For example, an uppermost one of the conductive structures152defining each step122(e.g., an uppermost conductive structure152a) may be configured as a contact region for the second portion180of each of the conductive contacts172. The size and location of the first portion178may correspond to the size and location of the fourth openings131(FIG.11B), and the size and location of the second portion180may correspond to the size and location of the lateral openings168(FIG.11B).

Accordingly, an individual conductive contact172may be configured to facilitate electrical communication between the source tier110and an uppermost conductive structure152adefining an individual step122of the staircase structure120. Further, the strapping structure174of at least one of the conductive contacts172is vertically offset from the strapping structure174of at least one other of the conductive contacts172. Forming the conductive contacts172to facilitate electrical communication between the source tier110and the conductive structures152may reduce a quantity of support structures170within the staircase region105. For example, facilitating electrical communication between the source tier110and the conductive structures152through the conductive contacts172facilitates forming the support structures170proximate the conductive contacts172without the need to form complex conductive pathways above the stack structure155. Accordingly, a greater quantity of the steps122of the staircase structure120may be provided within a given area of the microelectronic device structure100as compared to conventional microelectronic device structure configurations. By providing the conductive contacts172(including the first portions178and the second portions180thereof) within the staircase structure120, such configurations may also allow for reduced congestion in conductive pathways above the stack structure155. By reducing congestion in conductive pathways above the stack structure155, spacing of the conductive features may be increased, resulting in a decrease in parasitic (e.g., stray) capacitance between adjacent conductive features during use and operation of the microelectronic device structure100.

As shown inFIG.12B, presence of the liner material136within the recessed regions134provides the isolation regions176between the conductive contacts172and additional conductive structures152underlying each of the uppermost conductive structures152a, such that the additional conductive structures152are remote (e.g., isolated) from the conductive contacts172by the isolation regions176.

As shown inFIGS.12B and12C, each of the conductive contacts172may vertically extend completely through the stack structure155. For example, the first portion178of the conductive contacts172may vertically extend (e.g., in the Z-direction) from a vertically uppermost boundary of the dielectric fill material126(e.g., at an elevational level of a vertically uppermost boundary of a vertically uppermost tier154of the stack structure155) to or beyond a vertically uppermost boundary of the second conductive material114of the source tier110underlying the stack structure155. In some embodiments, vertically (e.g., in the Z-direction) upper surfaces of the conductive contacts172are substantially vertically coplanar with upper surfaces of the support structures170(FIG.12D) and lower surfaces of the conductive contacts172are substantially vertically coplanar with lower surfaces of the support structures170. Accordingly, each of the conductive contacts172may have about a same height as the support structures170.

The conductive contacts172may individually exhibit a substantially circular horizontal cross-sectional shape, as shown in the top-down view ofFIG.12A. However, the disclosure is not so limited. As a non-limiting example, in additional embodiments, the conductive contacts172individually exhibit a substantially rectangular cross-sectional shape (e.g., a substantially square cross-sectional shape), or a different elongate cross-sectional shape (e.g., an oblong cross-sectional shape). At least some of the conductive contacts172may exhibit a different geometric configuration (e.g., one or more different dimensions, a different shape) and/or different horizontal spacing than at least some other of the conductive contacts172, or each of the conductive contacts172may exhibit substantially the same geometric configuration (e.g., the same dimensions and the same shape) and horizontal spacing (e.g., in the X-direction) as each of the other conductive contacts172. For example, individual conductive contacts172of the microelectronic device structure100may exhibit a height (e.g., in the Z-direction) that is substantially similar to a height of each other of the conductive contacts172.

Accordingly, manufacturing processes may be simplified by forming the conductive contacts172to extend entirely through the vertical extent of the stack structure155and to terminate at a single location (e.g., at or within the source tier110), without forming the conductive contacts172to extend to varying (e.g., differing) depths of individual steps122of the staircase structure120. In contrast, conventional microelectronic device structures include conductive contacts that terminate at (e.g., land on) upper surfaces of individual steps of staircase structures, resulting in varying heights of conductive contacts throughout the staircase structures. In some instances, damage may occur within the staircase structures during fabrication of conventional microelectronic device structures. Particularly, damage to the tier materials of the tiers, also called “clipping,” may be a source of defect, which can adversely affect memory device performance. In addition, misaligned conductive contacts that terminate on upper surfaces of the individual steps of staircase structures, may be susceptible to bridging (e.g., shorting, electrical connection) between neighboring portions of the conductive structures152. Further, terminating the conductive contacts at varying (e.g., differing) depths of the steps of the staircase structure of conventional microelectronic device structures may result in so-called “overetch” or “underetch” during processing. Accordingly, each of the conductive contacts172of the microelectronic device structure100may be formed to extend entirely through the vertical extent of the stack structure155and to terminate at the single location in order to substantially reduce (e.g., substantially prevent) damage within the staircase structure120during fabrication.

As shown inFIG.12D, the fill material170bof the support structures170may be formed adjacent (e.g., over) the liner material170awithin the third openings145(FIG.11D). In some embodiments, the fill material170bis formed of and includes an insulative material, such as a silicon oxide material. In other embodiments, the fill material170bis formed of and includes a conductive material including, but not limited to, n-doped polysilicon, p-doped polysilicon, undoped polysilicon, or a metal, such as tungsten. A material composition of the fill material170bmay be substantially the same as a material composition of the conductive material of the conductive contacts172(including the second portions180thereof also referred to herein as the strapping structures174), or the material composition of the fill material170bmay be different than the material composition of the conductive material of the conductive contacts172. In some such embodiments, the fill material170bof the support structures170may be formed during (e.g., substantially simultaneous with) formation of the conductive contacts172in order to simplify manufacturing processes. The liner material170amay substantially surround sidewalls of the fill material170b. In some embodiments, such as where the fill material170bcomprises an insulative material, the support structures170may not include the liner material170aon sidewalls of the fill material170b, and the support structures170may only include the fill material170b(e.g., the insulative material).

The fill material170bof the support structures170may be formed to substantially fill remaining portions of the third openings145(FIG.11D). The support structures170may be proximate to the conductive contacts172within the horizontal area of the staircase region105. Accordingly, some of the conductive contacts172and some of the support structures170may be located within horizontal boundaries of individual block structures162(FIG.5A). The support structures170may each individually exhibit a desired geometric configuration (e.g., dimensions and shape) and spacing. The geometric configurations and spacing of the support structures170may be selected at least partially based on the configurations and positions of other components (e.g., the steps122of the staircase structure120, the conductive contacts172, the source tier110) of the microelectronic device structure100. Each of the support structures170may exhibit substantially the same geometric configuration (e.g., the same dimensions and the same shape) and horizontal spacing (e.g., in the X-direction) as each of the other support structures170, or at least some of the support structures170may exhibit a different geometric configuration (e.g., one or more different dimensions, a different shape) and/or different horizontal spacing than at least some other of the support structures170. In some embodiments, the support structures170are at least partially uniformly spaced in the X-direction and in the Y-direction.

As shown inFIG.12D, each of the support structures170may vertically extend completely through the stack structure155. For example, at least some of the support structures170may be formed to extend vertically from an upper surface of the stack structure155to an upper surface of the second conductive material114of the source tier110. Alternatively or additionally, at least some of the support structures170(e.g., including the conductive material as the fill material170b) may be formed to extend below the upper surface of second conductive material114into the second conductive material114. In some embodiments, the support structures170are configured to provide one or more functions (e.g., electrical connections) in addition to support functions. In additional embodiments, the support structures170are configured to substantially only serve support functions, without being in electrical communication with the conductive structures152of the stack structure155, such as when the conductive contacts172physically contact the second conductive material114of the source tier110. Upper surfaces of each of the liner material170aand the fill material170bof the support structures170may be substantially vertically (e.g., in the Z-direction) coplanar with an upper surface of the dielectric material116overlying the dielectric fill material126and the stack structure155. Further, lower surfaces of the support structures170may be substantially vertically coplanar with lower surfaces of the conductive contacts172, without being vertically coplanar with lower surfaces of the dielectric material164within the slots160(FIG.7A) as a result of each of the support structures170and the conductive contacts172terminating at or within the second conductive material114of the source tier110and the dielectric material164terminating at or within the first conductive material112thereof.

The support structures170may individually exhibit a substantially circular horizontal cross-sectional shape, as shown in the top-down view ofFIG.12A. However, the disclosure is not so limited. As a non-limiting example, in additional embodiments, the support structures170individually exhibit a substantially rectangular cross-sectional shape (e.g., a substantially square cross-sectional shape), or a different elongate cross-sectional shape (e.g., an oblong cross-sectional shape). A lateral dimension (e.g., a second width W2, a diameter in the X-direction) of one or more of the support structures170may be relatively larger than a lateral dimension (e.g., a first width W1, a diameter in the X-direction) of one or more (e.g., each) of the conductive contacts172. In some embodiments, the first width W1of the conductive contacts172may be within a range of from about 50 nm to about 200 nm, such as from about 50 nm to about 100 nm, from about 100 nm to about 150 nm, or from about 150 nm to about 200 nm, and the second width W2of the support structures170may be within a range of from about 200 nm to about 500 nm, such as from about 200 nm to about 300 nm, from about 300 nm to about 400 nm, or from about 400 nm to about 500 nm. In additional embodiments, a lateral dimension (e.g., the first width W1in the X-direction, a width in the Y-direction) of one or more of the conductive contacts172is substantially the same as (e.g., substantially equal to) a lateral dimension of one of the support structures170or, alternatively, the lateral dimension of one or more of the conductive contacts172is relatively larger than the lateral dimension of one of the support structures170, such as when one or more of the conductive contacts172exhibit an oblong cross-sectional shape. By way of non-limiting example, at least one lateral dimension of one or more of the conductive contacts172may be within a range of from about 200 nm to about 700 nm, such as from about 200 nm to about 300 nm, from about 300 nm to about 400 nm, from about 400 nm to about 500 nm, from about 500 nm to about 600 nm, or from about 600 nm to about 700 nm. The relative widths of the conductive contacts172and the support structures170may be tailored to have a desired value that may be selected at least partially based on design requirements of the microelectronic device structure100.

FIG.13Aillustrates an enlarged portion of box A ofFIG.12A, in accordance with the embodiment of the microelectronic device structure100ofFIG.12A. For clarity and ease of understanding the drawings and associated description, surrounding materials including the dielectric material116and the dielectric fill material126are absent fromFIG.13A. In some embodiments, portions (e.g., the remaining portion142of the upper portions128a) of the second insulative liner material128are maintained (e.g., remain) vertically over each step122of the staircase structure120(FIG.13B). The remaining portion142of the upper portions128aof the second insulative liner material128may laterally (e.g., in the X-direction, in the Y-direction) surround the strapping structures174(also described here as the second portions180(FIGS.12A through12C)) of the conductive contacts172(FIGS.12A through12C), and the strapping structures174may laterally surround portions (e.g., the first portions178(FIG.12A through12C)) of the conductive contacts172at an elevational level of the second insulative liner material128over each step122of the staircase structure120. Accordingly, the second portion180(also described herein as the strapping structures174) of an individual conductive contact172may be located horizontally proximate to and may at least partially (e.g., substantially) surround the first portion178thereof. The first portion178and the second portion180of the conductive contacts172may include substantially the same material composition with no easily discernable physical interface therebetween. Alternatively, the first portion178and the second portion180thereof may include a material composition that differs from one another, such that a material composition of the strapping structures174differs from a material composition of the conductive contacts172.

As shown inFIG.13A, each of the conductive contacts172and the strapping structures174may be horizontally centered within individual steps122of the staircase structure120(FIG.13B), although other configurations may be contemplated. A lateral dimension (e.g., a fourth width W4in the X-direction) of one or more of the steps122may be relatively larger than a lateral dimension (e.g., a third width W3, a diameter in the X-direction) of an individual conductive contact172(including the first portion178and the second portion180thereof). By way of non-limiting example, the third width W3may be within a range from about 300 nm to about 1000 nm (e.g., 1 μm), such as from about 300 nm to about 400 nm, from about 400 nm to about 500 nm, from about 500 nm to about 600 nm, from about 600 nm to about 700 nm, from about 700 nm to about 800 nm, from about 800 nm to about 900 nm, or from about 900 nm to about 1000 nm. In some embodiments, the fourth width W4is within a range from about 1.5 times greater than the third width W3of the second portion180(also described as the strapping structure174) of the conductive contact172to about 2.5 times the third width W3of the second portion180. In some embodiments, the fourth width W4is at least about 2.0 times the third width W3. In some embodiments, the fourth width W4is about the same size as the third width W3. In other embodiments, the fourth width W4is such that the lateral boundary of the second portion180of the conductive contact172at an elevational level of the second insulative liner material128overlying the staircase structure120does not laterally extend beyond the steps122to reduce or prevent electrical shorting of the conductive contacts172to the conductive structures152of the stack structure155. Stated another way, the fourth width W4may be sized such that the second portions180of the conductive contacts172do not laterally extend beyond the lateral boundary of the steps122.

FIG.13Billustrates an enlarged portion of box B ofFIG.12B, in accordance with the embodiment of the microelectronic device structure100ofFIG.12B. For clarity and ease of understanding the drawings and associated description, surrounding materials including the dielectric fill material126are absent fromFIG.13B. As shown inFIG.13B, the conductive structures152may individually comprise the conductive liner material158in contact with the insulative structures104and the conductive material156in contact with the conductive liner material158. While not illustrated inFIG.13B, the first insulative liner material127(FIG.2B) may, optionally, be present below the second insulative liner material128, as described in greater detail with reference toFIG.2B. In some such embodiments, at least portions of one or more of the conductive liner material158and the first insulative liner material127are removed prior to formation of the strapping structures174. Accordingly, the strapping structures174may be formed directly neighboring (e.g., in the Z-direction) the uppermost conductive structure152aof individual steps122. In some such embodiments, only a lower surface of each of the strapping structures174is in physical contact with any of the conductive structures152of the stack structure155. Alternatively, at least one material (e.g., the conductive liner material158) may vertically intervene between the strapping structures174and the uppermost conductive structure152a.

Since each of the conductive contacts172vertically extend completely through the stack structure155(FIG.12B), the conductive contacts172vertically extend through the steps122of the staircase structure120without terminating at upper surfaces thereof. As shown inFIG.13B, the liner material136within the recessed regions134horizontally intervenes between the conductive contacts172and the additional conductive structures152aligned below the uppermost conductive structure152a, such that the additional conductive structures152are remote (e.g., isolated) from the conductive contacts172by the isolation regions176. For example, the conductive contacts172may extend through the dielectric fill material126to individually contact the uppermost conductive structure152aand the steps122of the staircase structure120, without contacting the additional conductive structures152thereunder. Each step122may individually be in contact with one of the conductive contacts172through the second portion180thereof (also described as one of the strapping structures174). The second portion180of each conductive contact172may be configured (e.g., sized and shaped) to maximize (e.g., increase) overlap with the contact region of the uppermost conductive structure152a.

As shown inFIG.13B, the uppermost conductive structures152amay be separated from the first portions178of the conductive contacts172, by the isolation regions176, by a distance D1in the Y-direction. By way of non-limiting example, the distance D1may be within a range from about 20 nm to about 100 nm, such as from about 20 nm to about 40 nm, from about 40 nm to about 60 nm, from about 60 nm to about 80 nm, or from about 80 nm to about 100 nm. In some embodiments, the distance D1is about 80 nm, which corresponds to a horizontal width of the liner material136within the recessed regions134in the Y-direction. Further, the horizontal width of the liner material136may vary along a vertical height of each of the conductive structures152. The second portions180of the conductive contacts172(also described herein as the strapping structures174) may individually have a thickness T2(e.g., height) in the vertical direction within a range from about 10 nm to about 100 nm, such as from about 10 nm to about 20 nm, from about 20 nm to about 40 nm, from about 40 nm to about 60 nm, from about 60 nm to about 80 nm, or from about 80 nm to about 100 nm. In some embodiments, the thickness T2is about 80 nm, which corresponds to the thickness T1of the second insulative liner material128. In other embodiments, the thickness T2is within a range from about 10 nm to about 180 nm, which corresponds to a combined thickness of the second insulative liner material128and the first insulative liner material127(FIG.2B).

FIG.14illustrates a simplified, partial cutaway perspective view of a portion of a microelectronic device201(e.g., a memory device, such as a dual deck 3D NAND Flash memory device) including a microelectronic device structure200. The microelectronic device structure200may be substantially similar to the microelectronic device structure100following the processing stage previously described with reference toFIGS.12A through12D. As shown inFIG.14, the microelectronic device structure200may include a staircase structure220(e.g., including the staircase structure120(FIG.12B)) defining contact regions for connecting conductive contacts206(e.g., corresponding to the conductive contacts172(FIG.12B)) directly to conductive tiers205(e.g., conductive layers, conductive plates, such as the conductive structures152(FIG.12B)). The microelectronic device structure200may include vertically extending strings207of memory cells203that are coupled to each other in series. The vertically extending strings207may extend vertically (e.g., in the Z-direction) and orthogonally to data lines202, a source tier204(e.g., corresponding to the source tier110(FIG.12B)), the conductive tiers205, first select gates208(e.g., upper select gates, drain select gates (SGDs)), select lines209, and a second select gate210(e.g., a lower select gate, a source select gate (SGS)). The microelectronic device201may include multiple blocks232(e.g., corresponding to the block structures162(FIG.5A)) horizontally separated (e.g., in the Y-direction) from one another by filled slot structures230(e.g., corresponding to the slots160(FIG.7A) filled with the dielectric material164(FIG.12A)).

Conductive contacts213and additional conductive contacts211may, optionally, electrically couple components to each other as shown. For example, the select lines209may be electrically coupled to the first select gates208. The microelectronic device201may also include a control unit212positioned under and within a horizontal area of the memory array including the vertically extending strings207of memory cells203. The control unit212may include control logic devices configured to control various operations of other features (e.g., the vertically extending strings207of memory cells203) of the microelectronic device201. By way of non-limiting example, the control unit212may include one or more (e.g., each) of charge pumps (e.g., VCCPcharge pumps, VNEGWLcharge pumps, DVC2 charge pumps), delay-locked loop (DLL) circuitry (e.g., ring oscillators), Vddregulators, drivers (e.g., string drivers), decoders (e.g., local deck decoders, column decoders, row decoders), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSAs), PMOS sense amplifiers (PSAs)), repair circuitry (e.g., column repair circuitry, row repair circuitry), I/O devices (e.g., local I/O devices), memory test devices, MUX, error checking and correction (ECC) devices, self-refresh/wear leveling devices, and other chip/deck control circuitry. The control unit212may be electrically coupled to the data lines202, the source tier204, the conductive contacts206, the first select gates208, and the second select gates210, for example. In some embodiments, the control unit212includes CMOS (complementary metal-oxide-semiconductor) circuitry. In such embodiments, the control unit212may be characterized as having a “CMOS under Array” (“CuA”) configuration, wherein the CMOS circuitry of a logic region is at least partially (e.g., substantially) positioned within horizontal areas of memory array regions of a microelectronic device including the microelectronic device structure100.

Source structures218(e.g., corresponding to the source structures118(FIG.12D)) of the source tier204may be electrically isolated from other portions thereof (e.g., other portions employed as conductive routing structures217(e.g., corresponding to the conductive routing structures117(FIG.12D))). The conductive routing structures217may electrically couple components (e.g., the conductive contacts206, the source structures218) to circuitry of the control unit212.

The first select gates208may extend horizontally in a first direction (e.g., the X-direction) and may be coupled to respective first groups of vertically extending strings207of memory cells203at a first end (e.g., an upper end) of the vertically extending strings207. The second select gate210may be formed in a substantially planar configuration and may be coupled to the vertically extending strings207at a second, opposite end (e.g., a lower end) of the vertically extending strings207of memory cells203.

The data lines202(e.g., bit lines) may extend horizontally in a second direction (e.g., in the Y-direction) that is at an angle (e.g., perpendicular) to the first direction in which the first select gates208extend. The data lines202may be coupled to respective second groups of the vertically extending strings207at the first end (e.g., the upper end) of the vertically extending strings207. A first group of vertically extending strings207coupled to a respective first select gate208may share a particular vertically extending string207with a second group of vertically extending strings207coupled to a respective data line202. Thus, a particular vertically extending string207may be selected at an intersection of a particular first select gate208and a particular data line202. Accordingly, the first select gates208may be used for selecting memory cells203of the vertically extending strings207of memory cells203.

The conductive tiers205(e.g., word line plates, such as the conductive structures152(FIG.12B)) may extend in respective horizontal planes. The conductive tiers205may be stacked vertically, such that each conductive tier205is coupled to all of the vertically extending strings207of memory cells203, and the vertically extending strings207of the memory cells203extend vertically through the stack of conductive tiers205. The conductive tiers205may be coupled to or may form control gates of the memory cells203to which the conductive tiers205are coupled. Each conductive tier205may be coupled to one memory cell203of a particular vertically extending string207of memory cells203.

The first select gates208and the second select gates210may operate to select a particular vertically extending string207of the memory cells203between a particular data line202and the source tier204. Thus, a particular memory cell203may be selected and electrically coupled to a data line202by operation of (e.g., by selecting) the appropriate first select gate208, second select gate210, and conductive tier205that are coupled to the particular memory cell203.

The staircase structure220may be configured to provide electrical connection directly between the conductive contacts206and the conductive tiers205. In other words, a particular conductive tier205may be selected via a conductive contact206in electrical communication therewith. The data lines202may be electrically coupled to the vertically extending strings207through conductive contact structures234.

Thus, in accordance with embodiments of the disclosure a microelectronic device comprises a stack structure overlying a source tier. The stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The microelectronic device comprises a staircase structure within the stack structure and having steps comprising lateral edges of the tiers, support structures vertically extending through the stack structure and within a horizontal area of the staircase structure, and conductive contacts vertically extending through the stack structure and horizontally neighboring the support structures within the horizontal area of the staircase structure. Each of the conductive contacts has a horizontally projecting portion in contact with one of the conductive structures of the stack structure at one of the steps of the staircase structure.

Thus, in accordance with additional embodiments of the disclosure, a memory device comprises a stack structure comprising conductive structures vertically interleaved with insulative structures, strings of memory cells vertically extending through the stack structure, a staircase structure within the stack structure defined by steps comprising lateral ends of the conductive structures and the insulative structures, and conductive contacts vertically extending through the stack structure. Each of the conductive contacts individually comprise a first portion vertically extending from an uppermost boundary of the stack structure to conductive material underlying a lowermost boundary of the stack structure, and a second portion laterally surrounding the first portion and in physical contact with one of the conductive structures of the stack structure at an elevational level of one of the steps of the staircase structure.

Furthermore, in accordance with further embodiments of the disclosure, a method of forming a microelectronic device comprises forming a stack structure over a source tier including conductive material. The stack structure comprises a vertically alternating sequence of insulative structures and additional insulative structures arranged in tiers. Each of the tiers individually comprises at least one of the insulative structures and at least one of the additional insulative structures. The method comprises forming at least one insulative liner material over a staircase structure within the stack structure. The staircase structure has steps comprising lateral edges of the tiers of the stack structure. The method comprises forming first openings extending through the stack structure within a horizontal area of the staircase structure and exposing portions of the conductive material of the source tier, forming first sacrificial structures within the first openings, at least partially replacing the additional insulative structures with conductive structures, removing the first sacrificial structures to form contact openings extending to and exposing portions of additional conductive material underlying the conductive material of the source tier, and forming conductive contacts within the contact openings. The conductive contacts are in electrical communication with the additional conductive material and with the conductive structures at the steps of staircase structure.

Microelectronic devices (e.g., the microelectronic device201including microelectronic device structures (e.g., the microelectronic device structures100,200)) of the disclosure may be included in embodiments of electronic systems of the disclosure. For example,FIG.15is a schematic block diagram of an electronic system303, in accordance with embodiments of the disclosure. The electronic system303may comprise, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular telephone, a digital camera, a personal digital assistant (PDA), portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet such as, for example, an iPAD® or SURFACE® tablet, an electronic book, a navigation device, etc. The electronic system303includes at least one memory device305. The memory device305may include, for example, an embodiment of a microelectronic device structure previously described herein (e.g., the microelectronic device structure100,200previously described with reference toFIGS.1A through13BandFIG.14) or a microelectronic device (e.g., the microelectronic device201) previously described with reference toFIG.14)FIG.14.

The electronic system303may further include at least one electronic signal processor device307(often referred to as a “microprocessor”). The electronic signal processor device307may, optionally, include an embodiment of one or more of a microelectronic device and a microelectronic device structure previously described herein. The electronic system303may further include one or more input devices309for inputting information into the electronic system303by a user, such as, for example, a mouse or other pointing device, a keyboard, a touchpad, a button, or a control panel. The electronic system303may further include one or more output devices311for outputting information (e.g., visual or audio output) to a user such as, for example, a monitor, a display, a printer, an audio output jack, a speaker, etc. In some embodiments, the input device309and the output device311may comprise a single touchscreen device that can be used both to input information to the electronic system303and to output visual information to a user. The input device309and the output device311may communicate electrically with one or more of the memory device305and the electronic signal processor device307.

With reference toFIG.16, depicted is a processor-based system400. The processor-based system400may include one or more of a microelectronic device and a microelectronic device structure previously described herein and manufactured in accordance with embodiments of the disclosure. The processor-based system400may be any of a variety of types such as a computer, pager, cellular phone, personal organizer, control circuit, or other electronic device. The processor-based system400may include one or more processors402, such as a microprocessor, to control the processing of system functions and requests in the processor-based system400. The processor402and other subcomponents of the processor-based system400may include one or more of a microelectronic device and a microelectronic device structure previously described herein and manufactured in accordance with embodiments of the present disclosure.

The processor-based system400may include a power supply404in operable communication with the processor402. For example, if the processor-based system400is a portable system, the power supply404may include one or more of a fuel cell, a power scavenging device, permanent batteries, replaceable batteries, and rechargeable batteries. The power supply404may also include an AC adapter; therefore, the processor-based system400may be plugged into a wall outlet, for example. The power supply404may also include a DC adapter such that the processor-based system400may be plugged into a vehicle cigarette lighter or a vehicle power port, for example.

Various other devices may be coupled to the processor402depending on the functions that the processor-based system400performs. For example, a user interface406may be coupled to the processor402. The user interface406may include input devices such as buttons, switches, a keyboard, a light pen, a mouse, a digitizer and stylus, a touch screen, a voice recognition system, a microphone, or a combination thereof. A display408may also be coupled to the processor402. The display408may include an LCD display, an SED display, a CRT display, a DLP display, a plasma display, an OLED display, an LED display, a three-dimensional projection, an audio display, or a combination thereof. Furthermore, an RF sub-system/baseband processor410may also be coupled to the processor402. The RF sub-system/baseband processor410may include an antenna that is coupled to an RF receiver and to an RF transmitter (not shown). A communication port412, or more than one communication port412, may also be coupled to the processor402. The communication port412may be adapted to be coupled to one or more peripheral devices414, such as a modem, a printer, a computer, a scanner, or a camera, or to a network, such as a local area network, remote area network, intranet, or the Internet, for example.

The processor402may control the processor-based system400by implementing software programs stored in the memory. The software programs may include an operating system, database software, drafting software, word processing software, media editing software, or media playing software, for example. The memory is operably coupled to the processor402to store and facilitate execution of various programs. For example, the processor402may be coupled to system memory416, which may include one or more of spin torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), racetrack memory, and other known memory types. The system memory416may include volatile memory, non-volatile memory, or a combination thereof. The system memory416is typically large so that it can store dynamically loaded applications and data. In some embodiments, the system memory416may include semiconductor devices, such as one or more of a microelectronic devices and a microelectronic device structure previously described herein.

The processor402may also be coupled to non-volatile memory418, which is not to suggest that system memory416is necessarily volatile. The non-volatile memory418may include one or more of STT-MRAM, MRAM, read-only memory (ROM) such as an EPROM, resistive read-only memory (RROM), and flash memory to be used in conjunction with the system memory416. The size of the non-volatile memory418is typically selected to be just large enough to store any necessary operating system, application programs, and fixed data. Additionally, the non-volatile memory418may include a high-capacity memory such as disk drive memory, such as a hybrid-drive including resistive memory or other types of non-volatile solid-state memory, for example. The non-volatile memory418may include microelectronic devices, such as one or more of a microelectronic device and a microelectronic device structure previously described herein.

Thus, in accordance with embodiments of the disclosure an electronic system comprises a processor operably coupled to an input device and an output device, and a memory device operably coupled to the processor. The memory device comprises a stack structure comprising dielectric materials and conductive materials vertically alternating with the dielectric materials, conductive contacts vertically extending through the stack structure from an uppermost boundary of the stack structure to conductive routing structures underlying a lowermost boundary of the stack structure. At least some of the conductive materials of the stack structure are in electrical communication with at least some of the conductive routing structures by way of the conductive contacts. The memory device comprises strings of memory cells vertically extending through the stack structure.

While certain illustrative embodiments have been described in connection with the figures, those of ordinary skill in the art will recognize and appreciate that embodiments encompassed by the disclosure are not limited to those embodiments explicitly shown and described herein. Rather, many additions, deletions, and modifications to the embodiments described herein may be made without departing from the scope of embodiments encompassed by the disclosure, such as those hereinafter claimed, including legal equivalents. In addition, features from one disclosed embodiment may be combined with features of another disclosed embodiment while still being encompassed within the scope of the disclosure.