Patent ID: 12236049

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various exemplary embodiments of the invention. As used herein “embodiments” are non-limiting examples of devices or methods employing one or more of the inventive concepts disclosed herein. It is apparent, however, that various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring various exemplary embodiments. Further, various exemplary embodiments may be different, but do not have to be exclusive. For example, specific shapes, configurations, and characteristics of an exemplary embodiment may be used or implemented in another exemplary embodiment without departing from the inventive concepts.

Unless otherwise specified, the illustrated exemplary embodiments are to be understood as providing exemplary features of varying detail of some ways in which the inventive concepts may be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and/or aspects, etc. (hereinafter individually or collectively referred to as “elements”), of the various embodiments may be otherwise combined, separated, interchanged, and/or rearranged without departing from the inventive concepts.

The use of cross-hatching and/or shading in the accompanying drawings is generally provided to clarify boundaries between adjacent elements. As such, neither the presence nor the absence of cross-hatching or shading conveys or indicates any preference or requirement for particular materials, material properties, dimensions, proportions, commonalities between illustrated elements, and/or any other characteristic, attribute, property, etc., of the elements, unless specified. Further, in the accompanying drawings, the size and relative sizes of elements may be exaggerated for clarity and/or descriptive purposes. When an exemplary embodiment may be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order. Also, like reference numerals denote like elements.

When an element, such as a layer, is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it may be directly on, connected to, or coupled to the other element or layer or intervening elements or layers may be present. When, however, an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present. To this end, the term “connected” may refer to physical, electrical, and/or fluid connection, with or without intervening elements. Further, the D1-axis, the D2-axis, and the D3-axis are not limited to three axes of a rectangular coordinate system, such as the x, y, and z-axes, and may be interpreted in a broader sense. For example, the D1-axis, the D2-axis, and the D3-axis may be perpendicular to one another, or may represent different directions that are not perpendicular to one another. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be construed as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as, for instance, XYZ, XYY, YZ, and ZZ. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

Although the terms “first,” “second,” etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the teachings of the disclosure.

Spatially relative terms, such as “beneath,” “below,” “under,” “lower,” “above,” “upper,” “over,” “higher,” “side” (e.g., as in “sidewall”), and the like, may be used herein for descriptive purposes, and, thereby, to describe one elements relationship to another element(s) as illustrated in the drawings. Spatially relative terms are intended to encompass different orientations of an apparatus in use, operation, and/or manufacture in addition to the orientation depicted in the drawings. For example, if the apparatus in the drawings is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. Furthermore, the apparatus may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and, as such, the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms, “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Moreover, the terms “comprises,” “comprising,” “includes,” and/or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It is also noted that, as used herein, the terms “substantially,” “about,” and other similar terms, are used as terms of approximation and not as terms of degree, and, as such, are utilized to account for inherent deviations in measured, calculated, and/or provided values that would be recognized by one of ordinary skill in the art.

Various exemplary embodiments are described herein with reference to sectional and/or exploded illustrations that are schematic illustrations of idealized exemplary embodiments and/or intermediate structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, exemplary embodiments disclosed herein should not necessarily be construed as limited to the particular illustrated shapes of regions, but are to include deviations in shapes that result from, for instance, manufacturing. In this manner, regions illustrated in the drawings may be schematic in nature and the shapes of these regions may not reflect actual shapes of regions of a device and, as such, are not necessarily intended to be limiting.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is a part. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.

Hereinafter, the inventive concepts will be explained in detail with reference to the accompanying drawings.

FIG.1is an assembled perspective view showing an electronic apparatus EA according to an exemplary embodiment of the present invention.FIG.2is an exploded perspective view showing the electronic apparatus EA according to an exemplary embodiment of the present invention.

The electronic apparatus EA may be an apparatus activated in response to an electrical signal. The electronic apparatus EA may include various embodiments. The electronic apparatus EA may be a tablet computer, a notebook computer, a computer, or a smart television. In the present exemplary embodiment, a smart phone will be described as a representative example of the electronic apparatus EA.

Referring toFIG.1, the electronic apparatus EA may display an image IM through a front surface FS. The front surface FS may include a transmission area TA and a bezel area BZA defined adjacent to the transmission area TA.

The front surface FS is defined to be substantially parallel to a surface defined by a first direction DR1and a second direction DR2. A normal line direction of the front surface FS, i.e., a thickness direction of the electronic apparatus EA, may indicate a third direction DR3. In the following descriptions, the expression “when viewed in a plan view or in a plan view” may mean a state of being viewed in the third direction DR3. Front (or upper) and rear (or lower) surfaces of each layer or each unit are distinguished from each other in the third direction DR3. However, directions indicated by the first, second, and third directions DR1, DR2, and DR3are relative to each other, and thus, the directions indicated by the first, second, and third directions DR1, DR2, and DR3may be changed to other directions, for example, opposite directions.

The electronic apparatus EA may display the image IM through the transmission area TA. The image IM may include a still image and a motion image.FIG.1shows a clock widget and application icons as a representative example of the image IM.

The transmission area TA may have a quadrangular shape parallel to each of the first direction DR1and the second direction DR2. However, this is merely exemplary. The transmission area TA may have a variety of shapes, and the inventive concepts should not be particularly limited.

The bezel area BZA may surround the transmission area TA. However, this is merely exemplary. The bezel area BZA may be disposed adjacent to only one side of the transmission area TA or may be omitted entirely. The electronic apparatus according to the exemplary embodiment of the present invention may include various embodiments, and it should not be particularly limited.

The electronic apparatus EA may sense a user input TC applied thereto from the outside. The user input TC may include external inputs of various forms, such as a part of the user's body, light, heat, or pressure. In addition, the electronic apparatus EA may sense the external inputs, e.g., a proximity input, applied when approaching close to or adjacent to the electronic apparatus EA as well as a touch input.

In the present exemplary embodiment, the user input TC is shown as a touch operation using the user's hand applied to the front surface FS. However, this is merely exemplary. As described above, the user input TC may be provided in various forms, and the electronic apparatus EA may sense the user input TC applied to a side or rear surface of the electronic apparatus EA depending on a structure of the electronic apparatus EA, and, it should not be limited to a particular embodiment.

Referring toFIG.2, the electronic apparatus EA may include a window100, a display module200, a circuit board300, an electronic module400, and an outer case500. The window100and the outer case500are coupled to each other to define an exterior of the electronic apparatus EA.

The window100may be disposed on the display module200and may cover a front surface IS of the display module200. The window100may include an optically transparent insulating material. For example, the window100may include glass or plastic. The window100may have a single-layer or multi-layer structure. For example, the window100may have a stack structure of a plurality of plastic films attached to each other by an adhesive or may have a stack structure of a glass substrate and a plastic film attached to the glass substrate by an adhesive.

The window100may include a front surface FS exposed to the outside. The front surface FS of the electronic apparatus EA may be defined by the front surface FS of the window100. The transmission area TA may be an optically transparent area. The transmission area TA may have a shape corresponding to an active area AA defined in the display module200. For example, the transmission area TA may overlap an entire surface or at least a portion of the active area AA. The image IM displayed through the active area AA of the display module200may be viewed from the outside through the transmission area TA.

The bezel area BZA may have a relatively lower light transmittance than the transmission area TA. The bezel area BZA may define the shape of the transmission area TA. The bezel area BZA may be defined adjacent to the transmission area TA and may surround the transmission area TA.

The bezel area BZA may have a predetermined color. When the window100includes a glass or plastic substrate, the bezel area BZA may be a color layer printed or deposited on one surface of the glass or plastic substrate. Alternatively, the bezel area BZA may be formed by coloring a corresponding area of the glass or plastic substrate.

The bezel area BZA may cover a non-active area NAA of the display module200to prevent the non-active area NAA from being viewed from the outside. However, this is merely exemplary. In the window100according to the exemplary embodiment of the present invention, the bezel area BZA may be omitted.

The display module200may include a display panel DP and an sensing unit ISU, which are described with reference toFIG.3. The display panel DP may include configurations appropriate to generate the image IM. The image IM generated by the display panel DP may be viewed from the outside by a user through the transmission area TA. The sensing unit ISU may sense the external input TC applied thereto. As described above, the sensing unit ISU may sense the external input TC provided to the window100. In the present exemplary embodiment, the sensing unit ISU may be described as an input sensing layer.

According to the exemplary embodiment of the present invention, the front surface IS of the display module200may include a first area and a second area adjacent to the first area. The first area may correspond to a module area MA and the active area AA surrounding the module area MA, and the second area may correspond to the non-active area NAA. The active area AA may be activated in response to an electrical signal. The module area MA and the second area may be defined as a non-display area in which the image is not displayed.

The active area AA may be a display area through which the image IM is displayed and may be a sensing area in which the external input TC is sensed. The transmission area TA may overlap at least the active area AA. For example, the transmission area TA may overlap the entire surface or at least a portion of the active area AA. Accordingly, the user may view the image IM through the transmission area TA or may provide the external input TC through the transmission area TA. However, this is merely exemplary. In the active area AA, an area through which the image IM is displayed and an area in which the external input TC is sensed may be separated from each other. However, the inventive concepts should not be limited thereto or thereby.

The non-active area NAA may be covered by the bezel area BZA. The non-active area NAA may be disposed adjacent to the active area AA. The non-active area NAA may surround the active area AA. A driving circuit or a driving wiring line may be disposed in the non-active area NAA to drive the active area AA.

Various signal lines, pads PD, or electronic devices, which provide electrical signals to the active area AA, may be disposed in the non-active area NAA. The non-active area NAA may be covered by the bezel area BZA, and thus, the non-active area NAA may not be viewed from the outside.

In the present exemplary embodiment, the display module200may be assembled in a flat state such that the active area AA and the non-active area NAA face the window100. However, this is merely exemplary. A portion of the non-active area NAA of the display module200may be bent. In this case, the portion of the non-active area NAA may be bent toward a rear surface of the electronic apparatus EA, and thus, the area of the bezel area BZA is reduced in the front side of the electrode apparatus EA. Alternatively, the display module200may have a partially-bent shape in the active area AA. In addition, the non-active area NAA may be omitted from the display module200according to another exemplary embodiment of the present invention.

The module area MA may have a relatively high transmittance relative to the same area as compared with the active area AA. The module area MA may be defined at a position overlapping the electronic module400described later when viewed in a plan view.

At least a portion of the module area MA may be surrounded by the active area AA. In the present exemplary embodiment, the module area MA may be spaced apart from the non-active area NAA. The module area MA may be defined in the active area AA such that an entire edge of the module area MA is surrounded by the active area AA.

The display module200may include a panel hole MH defined through the display module200in the module area MA. The panel hole MH may penetrate through at least one of the display panel DP and the sensing unit ISU. The edge of the module area MA may be spaced apart from an edge of the panel hole MH and may extend along the edge of the panel hole MH. The edge of the module area MA may have a shape corresponding to the panel hole MH.

The circuit board300may be connected to the display module200. The circuit board300may include a flexible board CF and a main board MB. The flexible board CF may include an insulating film and conductive lines mounted on the insulating film. The conductive lines may be connected to the pads PD to electrically connect the circuit board300to the display module200.

In the present exemplary embodiment, the flexible board CF may be bent while being assembled. Therefore, the main board MB may be disposed on the rear surface of the display module200and may be stably accommodated in a space provided by the outer case500. In the present exemplary embodiment, the flexible board CF may be omitted, and in this case, the main board MB may be connected directly to the display module200.

The main board MB may include signal lines and electronic devices, which are not shown. The electronic devices may be connected to the signal lines and may be electrically connected to the display module200. The electronic devices may generate various electrical signals, for example, signals to generate the image IM or signals to sense the external input TC, or may process the sensed signal. A plurality of the main boards MB may be provided to respectively correspond to the electrical signals to be generated or processed. However, the inventive concepts should not be particularly limited.

In the electronic apparatus EA according to the exemplary embodiment of the present invention, the driving circuit that provides the electrical signal to the active area AA may be mounted directly on the display module200. In this case, the driving circuit may be mounted in a chip form or may be formed together with pixels PX. In this case, the area of the circuit board300may be reduced, or the circuit board300may be omitted entirely. The electronic apparatus EA according to the exemplary embodiment of the present invention may include various embodiments, and, the electronic apparatus EA should not be particularly limited.

The electronic module400may be disposed under the window100. The electronic module400may overlap the panel hole MH defined in the module area MA. The electronic module400may receive the external input transmitted through the module area MA or may provide an output through the module area MA.

Among components of the electronic module400, a receiving unit receiving the external input or an outputting unit providing the output may overlap the module area MA in the plan view. All or a portion of the electronic module400may be accommodated in the module area MA or the panel hole MH. According to the present exemplary embodiment, since the electronic module400is disposed to overlap the active area AA, the size of the bezel area BZA may be reduced.

FIG.3is a cross-sectional view showing the display module200according to an exemplary embodiment of the present invention.

Referring toFIG.3, the display panel DP may include a base substrate BS, a circuit element layer DP-CL, a display element layer DP-OLED, and an insulating layer TFL, which are disposed on the base substrate BS.

According to the exemplary embodiment of the present invention, the display panel DP may be a light-emitting type display panel, however, it should not be particularly limited. For instance, the display panel DP may be an organic light emitting display panel or a quantum dot light emitting display panel. A light emitting layer of the organic light emitting display panel may include an organic light emitting material. A light emitting layer of the quantum dot light emitting display panel may include a quantum dot and a quantum rod. Hereinafter, the organic light emitting display panel will be described as a representative example of the display panel DP.

The display panel DP may include a display area DP-DA and a non-display area DP-NDA. The display area DP-DA of the display panel DP may correspond to the active area AA shown inFIG.2, and the non-display area DP-NDA of the display panel DP may correspond to the non-active area NAA shown inFIG.2.

The base substrate BS may include at least one plastic film. The base substrate BS may be a flexible substrate and may include a plastic substrate, a glass substrate, a metal substrate, or an organic/inorganic composite substrate.

The circuit element layer DP-CL may include at least one intermediate insulating layer and a circuit element. The intermediate insulating layer may include at least one intermediate inorganic layer and at least one organic layer. The circuit element may include signal lines and a pixel driving circuit.

The display element layer DP-OLED may include a plurality of display elements. As an example, the display element layer DP-OLED may be organic light emitting diodes. The display element layer DP-OLED may further include an organic layer such as a pixel definition layer.

The insulating layer TFL may encapsulate the display element layer DP-OLED. As an example, the insulating layer TFL may be a thin film encapsulation layer. The insulating layer TFL may protect the display element layer DP-OLED from moisture, oxygen, and a foreign substance, such as dust particles.

The sensing unit ISU may be disposed directly on the display panel DP to sense the input applied thereto from the outside. The input from the outside may be the user input TC described with reference toFIG.1. In this specification, the expression “component “A” is directly disposed on component “B”” means that no intervening elements, such as an adhesive layer, are present between the component “A” and the component “B”. In the present exemplary embodiment, the sensing unit ISU may be formed together with the display panel DP through successive processes.

FIG.4Ais a plan view showing the display panel according to an exemplary embodiment of the present invention.FIG.4Bis an enlarged view showing an area XX′ shown inFIG.2.FIG.4Cis a cross-sectional view showing a portion of the display panel overlapping a display area according to an exemplary embodiment of the present invention.

The display panel DP may include the base substrate BS, the pixels PX, the signal lines GL, DL, and PL, and the pads PD.

Referring toFIG.4A, the display panel DP may include the base substrate BS, the pixels PX, the signal lines GL, DL, and PL, and the display pads PD. The base substrate BS may include an insulating substrate. For example, the base substrate BS may include a glass substrate, a plastic substrate, or a combination thereof.

The signal lines GL, DL, and PL may be connected to the pixels PX and may transmit the electrical signals to the pixels PX. Among the signal lines included in the display panel DP, a scan line GL, a data line DL, and a power line PL are shown as a representative example. However, these are merely exemplary. The signal lines GL, DL, and PL may further include at least one of a power line, an initialization voltage line, and a light emitting control line, and the inventive concepts should not be limited to a particular embodiment.

The pixels PX may be arranged in the display area DP-DA. In the present exemplary embodiment, a signal circuit diagram of one pixel PX among the pixels is enlarged and shown. The pixel PX may include a first transistor T1, a capacitor CP, a second transistor T2, and an organic light emitting diode OLED. The first transistor T1may be a switching device that controls an ON/OFF of the pixel PX. The first transistor T1may transmit or block a data signal applied thereto through the data line DL in response to a scan signal applied thereto through the scan line GL.

The capacitor CP may be connected to the first transistor T1and the power line PL. The capacitor CP may be charged with electric charges corresponding to a difference in electric potential between the data signal provided from the first transistor T1and a first power signal applied to the power line PL.

The second transistor T2may be connected to the first transistor T1, the capacitor CP, and the organic light emitting diode OLED. The second transistor T2may control a driving current flowing through the organic light emitting diode OLED in response to an amount of the electric charges charged in the capacitor CP. A turn-on time of the second transistor T2may be determined by the amount of the electric charges charged in the capacitor CP. The second transistor T2may apply the first power signal provided through the power line PL to the organic light emitting diode OLED during its turn-on time.

The organic light emitting diode OLED may generate the light or may control an amount of the light in response to the electrical signals. For example, the organic light emitting diode OLED may include an organic light emitting device, a quantum dot light emitting device, an electrophoretic device, or an electrowetting device.

The organic light emitting diode OLED may receive a first power source voltage ELVDD provided from the power line PL and may receive a second power source voltage ELVSS from a power electrode (not shown). The first power source voltage ELVDD may be applied to a first electrode of the organic light emitting diode OLED through the second transistor T2, and the second power source voltage ELVSS may be applied to a second electrode of the organic light emitting diode OLED through the power electrode (not shown). The second power source voltage ELVSS may be lower than the first power source voltage ELVDD.

The driving current corresponding to a difference between the first power source voltage ELVDD provided from the second transistor T2and the second power source voltage ELVSS may flow through the organic light emitting diode OLED, and the organic light emitting diode OLED may generate the light corresponding to the driving current. However, this is merely exemplary, and each of the pixels PX may include electronic devices having various configurations and arrangements, and the inventive concepts should not be particularly limited.

The pixels PX may be arranged around the panel hole MH and may surround the panel hole MH in a plan view.

The pads PD may include a first pad P1and a second pad P2. The first pad P1may be provided in plural and may be respectively connected to the data lines DL. The second pad P2may be connected to a power pattern VDD to be electrically connected to the power line PL. The display panel DP may apply the electrical signals provided thereto from the outside through the pads PD to the pixels PX. The pads PD may further include pads to receive other electrical signals in addition to the first pad P1and the second pad P2. However, the pads PD should not be limited thereto or thereby.

InFIG.4B, the module area MA shown inFIG.2is represented by a dotted line. The area XX′ includes the area in which the panel hole MH is defined. Hereinafter, the display panel DP in the area where the panel hole MH is defined will be described in detail with reference toFIG.4B.

As described above, the panel hole MH may be defined in the display area DP-DA. Accordingly, at least some of the pixels PX may be arranged adjacent to the panel hole MH. Some of the pixels PX may surround the panel hole MH.

A predetermined groove pattern GV may be defined in the module area MA. The groove pattern GV may be disposed along an edge of the panel hole MH in a plan view, and in the present exemplary embodiment, the groove pattern GV may have a circular ring shape that surrounds the panel hole MH. However, this is merely exemplary. The groove pattern GV may have a shape different from that of the panel hole MH, a polygonal shape, an oval shape, a closed line shape provided with at least a curved line, or a shape including a plurality of patterns that are partially cut, and the inventive concepts should not be limited to a specific embodiment.

The groove pattern GV may correspond to a portion recessed from the front surface of the display panel DP and may block a path through which moisture and oxygen that penetrates through the panel hole MH flows into the pixel PX.

A plurality of signal lines SL1and SL2connected to the pixels PX may be disposed in the module area MA. The signal lines SL1and SL2may be connected to the pixels PX through the module area MA. For the convenience of explanation,FIG.4Bshows a first signal line SL1and a second signal line SL2among the signal lines connected to the pixels PX as a representative example.

The first signal line SL1may extend in the first direction DR1. The first signal line SL1may be connected to pixels arranged in the same row along the first direction DR1among the pixels PX. The first signal line SL1will be described as corresponding to the scan line GL.

Some pixels among the pixels connected to the first signal line SL1may be arranged at a left side with respect to the panel hole MH, and the other pixels may be disposed at a right side with respect to the panel hole MH. Therefore, the pixels arranged in the same row and connected to the first signal line SL1may be turned on/off by the same gate signal even though some pixels are omitted with respect to the panel hole MH.

The second signal line SL2may extend in the second direction DR2. The second signal line SL2may be connected to pixels arranged in the same column along the second direction DR2among the pixels PX. The second signal line SL2will be described as corresponding to the data line DL.

Some pixels among the pixels connected to the second signal line SL2may be arranged at an upper side with respect to the panel hole MH, and the other pixels may be disposed at a lower side with respect to the panel hole MH. Therefore, the pixels arranged in the same column and connected to the second signal line SL2may receive the data signal through the same data line even though some pixels are omitted with respect to the panel hole MH.

Referring toFIG.4C, the display panel DP may include a plurality of insulating layers, a semiconductor pattern, a conductive pattern, and a signal line. An insulating layer, a semiconductor layer, and a conductive layer may be formed by a coating or depositing process. Then, the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by a photolithography process. The semiconductor pattern, the conductive pattern, and the signal line included in the circuit element layer DP-CL and the display element layer DP-OLED may be formed. The display panel DP shown inFIG.4Cwill be described as including additional elements when compared with the first transistor T1and the second transistor T2of the pixel PX shown inFIG.4B.

The base substrate BS may include a synthetic resin film. The synthetic resin film may include a heat-curable resin. The base substrate BS may have a multi-layer structure. For instance, the base substrate BS may have a three-layer structure of a synthetic resin layer, an adhesive layer, and a synthetic resin layer. In particular, the synthetic resin layer may be a polyimide-based resin layer, and a material for the synthetic resin layer should not be particularly limited. The synthetic resin layer may include at least one of an acrylic-based resin, a methacrylic-based resin, a polyisoprene, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin. The base substrate BS may include a glass substrate, a metal substrate, or an organic/inorganic composite substrate.

At least one inorganic layer may be formed on an upper surface of the base substrate BS. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The inorganic layer may be formed in multiple layers. The inorganic layers may form a barrier layer and/or a buffer layer. In the present exemplary embodiment, the display panel DP may include a buffer layer BFL.

The buffer layer BFL may increase a coupling force between the base substrate BS and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer, and the silicon oxide layer and the silicon nitride layer may be alternately stacked with each other.

The semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon. However, the inventive concepts should not be limited thereto or thereby. The semiconductor pattern may include amorphous silicon or metal oxide.

FIG.4Cshows only a portion of the semiconductor pattern, and the semiconductor pattern may be further disposed in other areas of the pixels in a plan view. The semiconductor pattern may be arranged with a specific rule over the pixels PX. The semiconductor pattern may have different electrical properties depending on whether it is doped. The semiconductor pattern may include a doped region and a non-doped region. The doped region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with the P-type dopant.

The doped region may have a conductivity greater than that of the non-doped region and may substantially serve as an electrode or signal line. The non-doped region may substantially correspond to an active region (or channel). In other words, a portion of the semiconductor pattern may be the active region of the transistor, another portion of the semiconductor pattern may be a source or a drain of the transistor, and still another portion of the semiconductor pattern may be a connection electrode or a connection signal line.

As shown inFIG.4C, a source S1, an active region A1, and a drain D1of the first transistor T1may be formed from the semiconductor pattern, and a source S2, an active region A2, and a drain D2of the second transistor T2may be formed from the semiconductor pattern. The sources S1and S2and the drains D1and D2may extend in opposite directions to each other from the active regions A1and A2.FIG.4Cshows a portion of a connection signal line SCL formed from the semiconductor pattern. Although not shown in figures, the connection signal line SCL may be connected to the drain D2of the second transistor T2in a plan view.

A first insulating layer10may be disposed on the buffer layer BFL. The first insulating layer10may commonly overlap the pixels PX and may cover the semiconductor pattern. The first insulating layer10may be an inorganic layer and/or an organic layer and may have a single-layer or multi-layer structure. The first insulating layer10may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In the present exemplary embodiment, the first insulating layer10may have a single-layer structure of a silicon oxide layer. Not only the first insulating layer10, but also an insulating layer of the circuit element layer DP-CL described later may be an inorganic layer and/or an organic layer and may have a single-layer or multi-layer structure. The inorganic layer may include at least one of the above-mentioned materials.

Gates G1and G2may be disposed on the first insulating layer10. The gates G1and G2may be portions of a metal pattern. The gates G1and G2may overlap the active regions A1and A2, respectively. The gates G1and G2may be used as a mask in a process of doping the semiconductor pattern.

A second insulating layer20may be disposed on the first insulating layer10and may cover the gates G1and G2. The second insulating layer20may commonly overlap the pixels PX. The second insulating layer20may be an inorganic layer and/or an organic layer and may have a single-layer or multi-layer structure. In the present exemplary embodiment, the second insulating layer20may have a single-layer structure of silicon oxide.

An upper electrode UE may be disposed on the second insulating layer20. The upper electrode UE may overlap the gate G2of the second transistor T2. The upper electrode UE may be a portion of a metal pattern. A portion of the gate G2and the upper electrode UE overlapping the portion of the gate G2may define the capacitor CP (refer toFIG.4A).

A third insulating layer30may be disposed on the second insulating layer20and may cover the upper electrode UE. In the present exemplary embodiment, the third insulating layer30may have a single-layer structure of a silicon oxide layer. A first connection electrode CNE1may be disposed on the third insulating layer30. The first connection electrode CNE1may be connected to the connection signal line SCL through a contact hole CNT-1defined through the first, second, and third insulating layers10,20, and30.

A fourth insulating layer40may be disposed on the third insulating layer30to cover the first connection electrode CNE1. The fourth insulating layer40may have a single-layer structure of a silicon oxide layer. A fifth insulating layer50may be disposed on the fourth insulating layer40. The fifth insulating layer50may be an organic layer. A second connection electrode CNE2may be disposed on the fifth insulating layer50. The second connection electrode CNE2may be connected to the first connection electrode CNE1through a contact hole CNT-2defined through the fourth insulating layer40and the fifth insulating layer50.

A sixth insulating layer60may be disposed on the fifth insulating layer50and may cover the second connection electrode CNE2. The sixth insulating layer60may be an organic layer. The first electrode AE may be disposed on the sixth insulating layer60. The first electrode AE may be connected to the second connection electrode CNE2through a contact hole CNT-3defined through the sixth insulating layer60. An opening OP may be defined through a pixel definition layer PDL. At least a portion of the first electrode AE may be exposed through the opening OP of the pixel definition layer PDL.

As shown inFIG.4C, the display area DA may include a pixel area PXA and a light blocking area NPXA defined adjacent to the pixel area PXA. The light blocking area NPXA may surround the pixel area PXA. In the present exemplary embodiment, the pixel area PXA may be defined to correspond to the portion of the first electrode AE exposed through the opening OP.

A hole control layer HCL may be commonly disposed in the pixel area PXA and the light blocking area NPXA. The hole control layer HCL may include a hole transport layer and may further include a hole injection layer. A light emitting layer EML may be disposed on the hole control layer HCL. The light emitting layer EML may be disposed in an area corresponding to the opening OP. That is, the light emitting layer EML may be formed in each of the pixels PX after being divided into portions.

An electron control layer ECL may be disposed on the light emitting layer EML. The electron control layer ECL may include an electron transport layer and may further include an electron injection layer. The hole control layer HCL and the electron control layer ECL may be commonly formed in the plural pixels using an open mask. The second electrode CE may be disposed on the electron control layer ECL. The second electrode CE may have an integral shape and may be commonly disposed in the pixels PX.

The insulating layer TFL may be disposed on the second electrode CE. According to the present disclosure, the insulating layer TFL may include a plurality of thin layers. For instance, although not shown in figures, the insulating layer TFL may have a structure in which an inorganic layer and an organic layer are stacked.

FIG.5is a cross-sectional view showing the sensing unit according to an exemplary embodiment of the present invention.

Referring toFIG.5, the sensing unit ISU may include a first sensing insulating layer IS-IL1, a first conductive layer IS-CL1, a second sensing insulating layer IS-IL2, a second conductive layer IS-CL2, and a third sensing insulating layer IS-IL3. The first sensing insulating layer IS-IL1may be disposed directly on the insulating layer TFL. However, the inventive concepts should not be limited thereto or thereby. The first sensing insulating layer IS-IL1may be omitted, and in this case, the first conductive layer IS-CL1may be disposed directly on the insulating layer TFL.

Each of the first conductive layer IS-CL1and the second conductive layer IS-CL2may have a single-layer structure or a multi-layer structure of layers stacked in the third direction DR3. The conductive layer having the multi-layer structure may include at least two layers among transparent conductive layers and metal layers. The conductive layer having the multi-layer structure may include metal layers including different metals from each other.

The transparent conductive layer may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), PEDOT, a metal nanowire, or a graphene. The metal layer may include molybdenum, silver, titanium, copper, aluminum, or alloys thereof. For instance, each of the first conductive layer IS-CL1and the second conductive layer IS-CL2may have a three-layer structure of titanium/aluminum/titanium. A metal layer having a relatively high durability and a relatively low reflectance may be applied as an outer layer, and a metal layer having a high electrical conductivity may be applied as an inner layer.

According to the present exemplary embodiment, each of the first conductive layer IS-CL1and the second conductive layer IS-CL2may include a conductive pattern. For example, the first conductive layer IS-CL1may include a first conductive pattern including a first electrode portion and a first line portion, and the second conductive layer IS-CL2may include a second conductive pattern including a second electrode portion and a second line portion.

Each of the first sensing insulating layer IS-IL1, the second sensing insulating layer IS-IL2, and the third sensing insulating layer IS-IL3may include an inorganic layer or an organic layer. In the present exemplary embodiment, the first sensing insulating layer IS-IL1may be an inorganic layer. However, the inventive concepts should not be limited thereto or thereby. For instance, the first sensing insulating layer IS-IL1and the second sensing insulating layer IS-IL2may be the inorganic layer, and the third sensing insulating layer IS-IL3may be the organic layer.

FIG.6is a plan view showing the sensing unit ISU according to an exemplary embodiment of the present invention.FIG.7Ais an enlarged view showing an area AA shown inFIG.6according to an exemplary embodiment of the present invention.FIG.7Bis an enlarged view showing an area shown inFIG.7A.

Referring toFIG.6, the sensing unit ISU may include a sensing area AR and a peripheral area NAR, which are defined therein. The sensing area AR and the peripheral area NAR of the sensing unit ISU may correspond to the active area AA and the non-active area NAA of the display module200shown inFIG.2. The sensing area AR may be activated in response to an electrical signal. For example, the sensing area AR may be an area in which an input is sensed. The peripheral area NAR may surround the sensing area AR.

Although not shown inFIG.6, a hole area corresponding to the panel hole MH shown inFIG.2may be defined in the sensing area AR of the sensing unit ISU. The hole area may be defined by removing all or at least a portion of components forming the sensing unit ISU.

In detail, referring toFIGS.5and6, the sensing unit ISU may include first sensing electrodes E1, second sensing electrodes E2, dummy patterns DMP, sensing lines SL-T, SL-R1, and SL-R2, and pad portions PD1, PD2a, and PD2b. The first sensing electrodes E1, the second sensing electrodes E2, and the dummy patterns DMP may be disposed in the sensing area AR, and the sensing lines SL-T, SL-R1, and SL-R2may be disposed in the peripheral area NAR.

The sensing unit ISU may obtain information about the external input based on a variation in capacitance between the first sensing electrodes E1and the second sensing electrodes E2. The first sensing electrodes E1may be arranged in the first direction DR1and may extend in the second direction DR2. Each of the first sensing electrodes E1may include first sensing patterns SP1and first connection patterns BP1. The first connection patterns BP1may electrically connect two first sensing patterns SP1adjacent to each other.

The second sensing electrodes E2may extend in the first direction DR1and may be arranged in the second direction DR2. Each of the second sensing electrodes E2may include second sensing patterns SP2and second connection patterns BP2. The second connection patterns BP2may electrically connect two second sensing patterns SP2adjacent to each other. The two adjacent second sensing patterns SP2may be connected to each other by the two connection patterns BP2. However, the inventive concepts should not be limited thereto or thereby.

According to the present exemplary embodiment, the first sensing patterns SP1, the first connection patterns BP1, and the second sensing patterns SP2may be included in the second conductive layer IS-CL2. The first sensing patterns SP1, the second sensing patterns SP2, and the first connection patterns BP1may be formed on the second sensing insulating layer IS-IL2through the same process and may be defined as a second electrode portion of the second conductive layer IS-CL2.

The second connection patterns BP2may be included in the first conductive layer IS-CL1. The second connection patterns BP2may be disposed on the first sensing insulating layer IS-IL1and may be defined as a first electrode portion of the first conductive layer IS-CL1.

Each of the first sensing patterns SP1may include a first portion SP1a, a second portion SP1b, and a third portion SP1c.

The first portion SP1amay extend in the second direction DR2. One end of the first portion SP1amay be connected to one first connection pattern BP1, and the other end of the first portion SP1amay be connected to another first connection pattern BP1. The first portion SP1amay be referred to as a trunk portion. Since the first connection patterns BP1and the first sensing patterns SP1have a single connected structure, the first connection patterns BP1may be defined as portions of the first portion SP1a.

The second portion SP1bmay protrude from the first portion SP1ato the first direction DR1. For example, the second portion SP1bmay protrude in a direction away from a center area of the first portion SP1a. The second portion SP1bmay be referred to as a protrusion portion.

A plurality of the third portions SP1cmay be provided. The third portions SP1cmay extend in a fourth direction DR4or a fifth direction DR5from the first portion SP1a. Some portions of the third portions SP1cmay extend in the fourth direction DR4, and the other portions of the third portions SP1cmay extend in the fifth direction DR5. Each of the third portions SP1cmay be referred to as a “branch portion”.

The fourth direction DR4may be a direction crossing the first direction DR1and the second direction DR2. For example, the fourth direction DR4may be a direction between the first direction DR1and the second direction DR2. The fifth direction DR5may be a direction crossing the fourth direction DR4. For example, the fourth direction DR4and the fifth direction DR5may be substantially perpendicular to each other.

Each of the second sensing patterns SP2may have a shape corresponding to a shape of the first sensing patterns SP1adjacent thereto. Each of the second sensing patterns SP2may surround at least two third portions SP1cof each of the first sensing patterns SP1adjacent thereto.

The sensing lines SL-T, SL-R1, and SL-R2may overlap the peripheral area NAR and may be disposed on the second sensing insulating layer IS-IL2. The sensing lines SL-T, SL-R1, and SL-R2may be formed on the second sensing insulating layer IS-IL2through the same process as the first sensing electrodes E1and the second sensing electrodes E2.

The sensing lines SL-T, SL-R1, and SL-R2may include first sensing lines SL-T and second sensing lines SL-R1and SL-R2. The pad portions PD1, PD2a, and PD2bmay overlap the peripheral area NAR and may include first sensing pads PD1, first sub-sensing pads PD2a, and second sub-sensing pads PD2b. The first sensing pads PD1may be disposed between the first sub-sensing pads PD2aand the second sub-sensing pads PD2b.

One ends of the first sensing lines SL-T may be electrically connected to the first sensing electrodes E1, respectively, and the other ends of the first sensing lines SL-T may be electrically connected to the first sensing pads PD1, respectively.

The second sensing lines SL-R1and SL-R2may include first sub-sensing lines SL-R1disposed at a left side with respect to the second sensing electrodes E2and second sub-sensing lines SL-R2disposed at a right side with respect to the second sensing electrodes E2. The first sensing lines SL-T may be disposed between the first sub-sensing lines SL-R1and the second sub-sensing lines SL-R2.

One ends of the first sub-sensing lines SL-R1may be electrically connected to some second sensing electrodes among the second sensing electrodes E2, respectively, and the other ends of the first sub-sensing lines SL-R1may be electrically connected to the first sub-sensing pads PD2a, respectively.

One ends of the second sub-sensing lines SL-R2may be electrically connected to the other second sensing electrodes among the second sensing electrodes E2, respectively, and the other ends of the second sub-sensing lines SL-R2may be electrically connected to the second sub-sensing pads PD2b, respectively.

However, the connection structure of the sensing lines SL-T, SL-R1, and SL-R2should not be limited to the exemplary embodiment shown inFIG.6and may be changed to have various shapes.

According to the exemplary embodiment of the present invention, each of the sensing lines SL-T, SL-R1, and SL-R2may have a double-layered invention. Each of the sensing lines SL-T, SL-R1, and SL-R2may be electrically in contact with an auxiliary sensing line (not shown) disposed on the first sensing insulating layer IS-IL1through at least one contact hole defined through the second sensing insulating layer IS-IL2. The sensing lines SL-T, SL-R1, and SL-R2may correspond to the second line portion of the second conductive layer IS-CL2.

A plurality of the auxiliary sensing lines may be provided to respectively correspond to the sensing lines SL-T, SL-R1, and SL-R2, and may be disposed on the first sensing insulating layer IS-IL1. The auxiliary sensing lines may correspond to the first line portion of the first conductive layer IS-CL1.

As described above, since the sensing lines SL-T, SL-R1, and SL-R2electrically make contact with the auxiliary sensing lines disposed on different layers from each other, respectively, reliability of the electrical signals transmitted to the sensing electrodes E1and E2may be improved. For instance, although some of the sensing lines are disconnected, the electrical signals may be transmitted to the sensing electrodes through the auxiliary sensing lines electrically making contact with the sensing lines. Details on the above will be described with reference toFIGS.8A and8B.

The dummy patterns DMP may be spaced apart from the first sensing patterns SP1and the second sensing patterns SP2. The dummy patterns DMP may be formed on the second sensing insulating layer IS-IL2through the same process as the first sensing patterns SP1and the second sensing patterns SP2. Accordingly, the dummy patterns DMP may include the same material as and may have the same stack structure as the first sensing patterns SP1, the second sensing patterns SP2, and the sensing lines SL-T, SL-R1, and SL-R2. The dummy patterns DMP may be referred to as “auxiliary patterns”, “additional patterns”, “sub-patterns”, or “boundary patterns”.

The dummy patterns DMP may include a first pattern DMPa and a second pattern DMPb. The first pattern DMPa may be disposed between the first sensing pattern SP1and the second sensing pattern SP2. The second pattern DMPb may be disposed between the second sensing patterns SP2. For example, the second pattern DMPb may be disposed between two second sensing patterns SP2adjacent to each other in the second direction DR2, and thus, the two second sensing patterns SP2may be spaced apart from each other.

The second pattern DMPb may include a first boundary pattern MP1and second boundary patterns MP2. The first boundary pattern MP1may have a lozenge shape in a plan view. The second boundary patterns MP2may be spaced apart from each other with the first boundary pattern MP1interposed therebetween. Each of the second boundary patterns MP2may extend in the first direction DR1. Each of the second boundary patterns MP2may be connected to the first boundary pattern MP1and the first pattern DMPa.

As the first pattern DMPa is disposed between the first sensing patterns SP1and the second sensing patterns SP2and the second pattern DMPb is disposed between the second sensing patterns SP2, a visibility of a boundary area between the first sensing patterns SP1and the second sensing patterns SP2and a boundary area between the second sensing patterns SP2may be reduced.

Some dummy patterns among the dummy patterns DMP may be floating electrodes that are not electrically connected to the first sensing patterns SP1and the second sensing patterns SP2. Alternatively, some dummy patterns among the dummy patterns DMP may be grounded. The other dummy patterns among the dummy patterns DMP may be connected to the first sensing patterns SP1or the second sensing patterns SP2to improve a sensitivity of the sensing unit ISU.

Referring toFIGS.7A and7B, each of the first sensing patterns SP1, the first connection patterns BP1, the second sensing patterns SP2, the second connection patterns BP2, and the dummy patterns DMP may have a mesh structure. Boundaries BD between the first sensing patterns SP1, the second sensing patterns SP2, and the dummy patterns DMP may be defined by removing portions of the mesh structure. InFIG.7A, the boundaries BD are indicated by solid lines to clearly show the boundaries BD. The removed portions of the mesh structures shown inFIG.7Bmay correspond to the boundaries BD. In addition, disconnection portions CTP defined by removing portions of the mesh structures may be further provided to prevent the boundaries from being viewed.

FIG.8Ais a plan view showing the sensing signal lines shown inFIG.6according to an exemplary embodiment of the present invention.FIG.8Bis a cross-sectional view taken along a line I-I′ shown inFIG.8Aaccording to an exemplary embodiment of the present invention.

As described with reference toFIG.6, each of the sensing lines SL-T, SL-R1, and SL-R2may have a double-layered structure. That is, the sensing lines SL-T, SL-R1, and SL-R2may be electrically in contact with the auxiliary sensing lines disposed on different layers from each other, respectively. According to the present exemplary embodiment, each of the sensing lines SL-T, SL-R1, and SL-R2may have substantially the same double-layered structure.

Referring toFIGS.8A and8B, each of the first sensing lines SL-T may be electrically in contact with a first auxiliary sensing line SL-Td through a plurality of first contact holes CH1spaced apart from each other in a plan view.

A plurality of the first auxiliary sensing lines SL-Td may be provided to correspond to the number of the first sensing lines SL-T and may be disposed on the first sensing insulating layer IS-IL1. The first sensing lines SL-T may overlap the first auxiliary sensing lines SL-Td and may be disposed on the second sensing insulating layer IS-IL2. The first sensing lines SL-T may be electrically in contact with the first auxiliary sensing lines SL-Td through the first contact holes CH1defined through the second sensing insulating layer IS-IL2, respectively.

Each of the first sub-sensing lines SL-R1may be electrically in contact with a second auxiliary sensing line SL-R1dthrough a plurality of second contact holes CH2spaced apart from each other in a plan view. Similarly, the first sub-sensing lines SL-R1may be electrically in contact with the second auxiliary sensing lines SL-R1dthrough the second contact holes CH2defined through the second sensing insulating layer IS-IL2, respectively.

Each of the second sub-sensing lines SL-R2may be electrically in contact with a third auxiliary sensing line SL-R2dthrough a plurality of third contact holes CH3spaced apart from each other in a plan view. Similarly, the second sub-sensing lines SL-R2may be electrically in contact with the third auxiliary sensing lines SL-R2dthrough the third contact holes CH3defined through the second sensing insulating layer IS-IL2, respectively.

FIG.9is an enlarged view showing an area BB shown inFIG.6according to an exemplary embodiment of the present invention.FIG.10is a cross-sectional view taken along a line II-II′ shown inFIG.9according to an exemplary embodiment of the present invention.

Referring toFIGS.5and9, the sensing unit ISU may further include first connection electrodes CNE-T respectively connected to ends of the first sensing patterns SP1and second connection electrodes CNE-R respectively connected to ends of the second sensing patterns SP2. The first connection electrodes CNE-T may be spaced apart from each other and may be formed on the second sensing insulating layer IS-IL2through the same process as the first sensing patterns SP1. The second connection electrodes CNE-R may be spaced apart from each other and may be formed on the second sensing insulating layer IS-IL2through the same process as the second sensing patterns SP2. According to the present exemplary embodiment, the first connection electrodes CNE-T and the second connection electrodes CNE-R may be formed on the second sensing insulating layer IS-IL2through the same process.

Each of the first connection electrodes CNE-T and the second connection electrodes CNE-R may be connected to the end of the corresponding sensing pattern of the sensing patterns SP1and SP2having the mesh structure at at least two points. In this case, the end of the sensing pattern may mean a portion adjacent to the peripheral area NAR.

According to the present invention, each of the first connection electrodes CNE-T and the second connection electrodes CNE-R may have the double-layered structure. For instance, the first connection electrodes CNE-T may be electrically in contact with first auxiliary connection electrodes (not shown), respectively, through contact holes defined through the second sensing insulating layer IS-IL2. The second connection electrodes CNE-R may be electrically in contact with second auxiliary connection electrodes (not shown), respectively, through contact holes defined through the second sensing insulating layer IS-IL2. The first auxiliary connection electrodes and the second auxiliary connection electrodes may be formed on the first sensing insulating layer IS-IL1.

In detail, as shown inFIG.6, the first sensing lines SL-T may be disposed between the first sub-sensing lines SL-R1and the second sub-sensing lines SL-R2and may be electrically connected to one ends of the first sensing electrodes E1. The one ends of the first sensing electrodes E1may be areas adjacent to the pad portions PD1, PD2a, and PD2b(refer toFIG.6).

As shown inFIG.9, the first sensing lines SL-T may include a first sensing line SL-Ta, and the second sub-sensing lines SL-R2may include a second sensing line SL-R2a. The first sensing line SL-Ta may be closest to the second sub-sensing lines SL-R2among the first sensing lines SL-T, and the second sensing line SL-R2amay be closest to the first sensing lines SL-T among the second sub-sensing lines SL-R2.

The first sensing line SL-Ta may be electrically connected to a corresponding first connection electrode CNE-T among the first connection electrodes CNE-T. The first connection electrode CNE-T may be connected to one end of one first sensing electrode E1among the first sensing electrodes E1. The first connection electrode CNE-T may be connected directly to the first sensing pattern SP1of the first sensing electrode E1. The first sensing line SL-Ta may be disposed on the same layer as the first connection electrode CNE-T.

The second sensing line SL-R2amay be electrically connected to one second connection electrode CNE-R among the second connection electrodes CNE-R. The second connection electrode CNE-R may be connected to one end of one second sensing electrode E2adjacent to the one end of the first sensing electrode E1among the second sensing electrodes E2. The second connection electrode CNE-R may be connected directly to the second sensing pattern SP2of the second sensing electrode E2. The second sensing line SL-R2amay be disposed on the same layer as the second connection electrode CNE-R and may be formed through the same process as the first sensing line SL-Ta and the first connection electrode CNE-T.

The first sensing line SL-Ta according to the present invention may be disposed between the second connection electrode CNE-R and second sensing line SL-R2ain a plan view. In particular, one end of the second sensing line SL-R2amay be spaced apart from the second connection electrode CNE-R with the first sensing line SL-Ta interposed therebetween. As a result, the second sensing line SL-R2amay be electrically separated from the second connection electrode CNE-R by the first sensing line SL-Ta.

According to the exemplary embodiment of the present invention, the sensing unit ISU may include a connection portion BRE disposed on a different layer from the first sensing line SL-Ta and the second sensing line SL-R2a. The connection portion BRE may be formed on the first sensing insulating layer IS-IL1and may correspond to the first line portion of the first conductive layer IS-CL1. The connection portion BRE may electrically connect the second sensing line SL-R2ato the second connection electrode CNE-R through contact holes defined through the second sensing insulating layer IS-IL2. As a result, the electrical signal transmitted through the second sensing line SL-R2amay be applied to the second sensing pattern SP2through the connection portion BRE and the second connection electrode CNE-R.

In particular, according to the present invention, the second sensing line SL-R2amay include a first line area LR1and a second line area LR2, which have different line widths from each other. The connection portion BRE may be connected to the second auxiliary sensing line overlapping the second line area LR2having the line width greater than the first line area LR1.

The connection portion BRE may include a first connection line BREa and a second connection line BREb. Each of the first connection line BREa and the second connection line BREb may be disposed on the first sensing insulating layer IS-IL1corresponding to the first conductive layer IS-CL1.

According to the present invention, the first connection line BREa may intersect the first sensing line SL-Ta disposed on another layer in a plan view. In addition, the first connection line BREa may not overlap a first auxiliary sensing line SL-Tda electrically making contact with the first sensing line SL-Ta, which will be described with reference toFIG.11.

That is, the first connection line BREa may be spaced apart from the first auxiliary sensing line SL-Tda and may include one end electrically connected to the second connection electrode CNE-R and the other end electrically connected to the second sensing line SL-R2b.

In detail, referring toFIG.10, the second sensing insulating layer IS-IL2may define a first contact hole CH1aand a second contact hole CH2a. The second connection electrode CNE-R may be electrically connected to a second auxiliary connection electrode CNE-Rd through the first contact hole CH1a. The second sensing line SL-R2amay be electrically connected to a second auxiliary sensing line SL-R2adthrough the second contact hole CH2a.

One end of the first connection line BREa may be connected to the second auxiliary connection electrode CNE-Rd, and the other end of the first connection line BREa may be connected to the second auxiliary sensing line SL-R2ad. According to the present invention, the first connection line BREa, the second auxiliary connection electrode CNE-Rd, and the second auxiliary sensing line SL-R2admay be formed on the first sensing insulating layer IS-IL1in an integral shape through the same process.

The electrical signal transmitted through the second sensing line SL-R2amay be applied to the second connection electrode CNE-R through the second auxiliary sensing line SL-R2ad, the first connection line BREa, and the second auxiliary connection electrode CNE-Rd. As a result, the electrical signal may be transmitted to the second sensing pattern SP2connected to the second connection electrode CNE-R.

The first sensing line SL-Ta may overlap at least a portion of the first connection line BREa and may be disposed on the second sensing insulating layer IS-IL2. When viewed in a plan view, the first connection line BREa may intersect the first sensing line SL-Ta.

In particular, the first sensing line SL-Ta may overlap the first connection line BREa and may include a first portion Ta1, a second portion Ta2, and a third portion Ta3, which are spaced apart from each other in a plan view. The first portion Ta1, the second portion Ta2, and the third portion Ta3may be disposed between the second connection electrode CNE-R and the second sensing line SL-R2a.

Referring toFIG.9again, the second connection line BREb may be spaced apart from the first connection line BREa and may intersect the first sensing line SL-Ta. In addition, the second connection line BREb may not overlap the first auxiliary sensing line SL-Tda that electrically makes contact with the first sensing line SL-Ta, which will be described with reference toFIG.11. The second connection line BREb may be spaced apart from the first auxiliary sensing line SL-Tda when viewed in a plan view and may include one end electrically connected to the second connection electrode CNE-R and the other end electrically connected to the second sensing line SL-R2b.

In addition, although not shown, the second connection line BREb may have substantially the same structure as the first connection line BREa shown inFIG.10. For instance, one end of the second connection line BREb may be connected to the second auxiliary connection electrode CNE-Rd, and the other end of the second connection line BREb may be connected to the second auxiliary sensing line SL-R2ad.

The electrical signal transmitted through the second sensing line SL-R2amay be applied to the second connection electrode CNE-R through the second auxiliary sensing line SL-R2ad, the second connection line BREb, and the second auxiliary connection electrode CNE-Rd. As a result, the electrical signal may be transmitted to the second sensing pattern SP2connected to the second connection electrode CNE-R.

As described above, the second sensing line SL-R2aaccording to the present invention may be separated from the second connection electrode CNE-R by the first sensing line SL-Ta. However, the second sensing line SL-R2aand the second connection electrode CNE-R may be electrically connected to each other by the connection portion BRE.FIG.9shows the connection portion BRE that includes two connection lines BREa and BREb. However, the inventive concepts should not be limited thereto. That is, the connection portion BRE may include at least one connection line that connects the second sensing line SL-R2aand the second connection electrode CNE-R.

FIG.11is an exploded perspective view showing the first sensing line SL-Ta and the first auxiliary sensing line SL-Tda shown inFIG.9according to an exemplary embodiment of the present invention.

Referring toFIGS.9and11, the first sensing line SL-Ta among the first sensing lines SL-T may include first and second line portions SA1and SA2, each having a first line width DS1, and a third line portion SA3having a second line width DS2greater than the first line width DS1. The third line portion SA3may be disposed between the first line portions SA1and SA2.

One end of the first line portion SA1may be connected to a corresponding second sub-sensing pad among the second sub-sensing pads PD2b, and the other end of the first line portion SA1may be connected to one end of the third line portion SA3. One end of the second line portion SA2may be connected to the first connection electrode CNE-T, and the other end of the second line portion SA2may be connected to the other end of the third line portion SA3. The first line portion SA1, the second line portion SA2, and the third line portion SA3may be integrally formed with each other.

According to the exemplary embodiment of the present invention, the third line portion SA3may be provided with at least one opening OPk defined therethrough and extending in a longitudinal direction of the first sensing line SL-Ta.FIG.11shows two openings OPk as a representative example.

The third line portion SA3may include the first portion Ta1, the second portion Ta2, and the third portion Ta3, which are spaced apart from each other in the plan view shown inFIG.10. Each of the first portion Ta1, the second portion Ta2, and the third portion Ta3may have a line width less than a line width of each of the first sensing lines except for the first sensing line SL-Ta among the first sensing lines SL-T.

In particular, the first connection line BREa and the second connection line BREb may cross the third line portion SA3in a plan view. A coupling between the first connection line BREa and the third line portion SA3that cross each other may be reduced through the openings OPk defined through the third line portion SA3. Similarly, a coupling between the second connection line BREb and the third line portion SA3that cross each other may be reduced through the openings OPk defined through the third line portion SA3.

In addition, as shown inFIG.9, the second line width DS2of the third line portion SA3may be greater than the line width of the second sensing line SL-R2a.

The first auxiliary sensing line SL-Tda may include first auxiliary portions TP1aand TP1brespectively overlapping the first and second line portions SA1and SA2, and a second auxiliary portion TP2overlapping the third line portion SA3. The second auxiliary portion TP2may be disposed between the first auxiliary portions TP1aand TP1band may be spaced apart from the first auxiliary portions TP1aand TP1b.

According to the present invention, the first connection line BREa and the second connection line BREb may be respectively disposed in spaces OPa and OPb between the second auxiliary portion TP2and the first auxiliary portion TP1aand between the second auxiliary portion TP2and the first auxiliary portion TP1b. The first connection line BREa and the second connection line BREb may be electrically separated from the first auxiliary sensing line SL-Tda by the spaces OPa and OPb.

FIG.12is an enlarged view showing an area BB shown inFIG.6according to another exemplary embodiment of the present invention.FIG.13is a cross-sectional view taken along a line III-III′ shown inFIG.12according to another exemplary embodiment of the present invention.

Referring toFIGS.12and13, the first sensing line SL-Ta1may have a constant line width. That is, the first sensing lines SL-T may have the same line width as each other.

The connection portion BRE-1may correspond to a first line portion of a first conductive layer IS-CL1and may include a first connection line BRE1and a second connection line BRE2. As described with reference toFIG.9, each of the first connection line BRE1and the second connection line BRE2may electrically connect a second connection electrode CNE-R and a second sub sensing line SL-R2.

Each of the first connection line BRE1and the second connection line BRE2of the connection portion BRE-1may include at least one sub-connection lines crossing the first sensing line SL-Ta1. According to the present invention, each of the first connection line BRE1and the second connection line BRE2may include three sub-connection lines. However, the number of the sub-connection lines may vary.

As shown inFIG.13, the first connection line BRE1may include three sub-connection lines BRE1a, BRE1b, and BRE1cspaced apart from each other in a plan view. At least a portion of each of the three sub-connection lines BRE1a, BRE1b, and BRE1cmay overlap the first sensing line SL-Ta1.

In addition, the three sub-connection lines BRE1a, BRE1b, and BRE1cmay not overlap a first auxiliary line SL-Tda1. For instance, the three sub-connection lines BRE1a, BRE1b, and BRE1cmay be disposed in the spaces OPa and OPb described with reference toFIG.11.

According to the above, the input sensing layer includes the first sensing line connected to the first sensing pattern and the second sensing line connected to the second sensing pattern spaced apart from the first sensing pattern. The first sensing line is disposed between the connection electrode and the second sensing line in a plan view.

The connection portion crosses the first sensing line in the plan view, is disposed on the first insulating layer, and electrically connects the second sensing line to the connection electrode through the contact holes defined through the second insulating layer. As a result, the electrical signals transmitted through the second sensing line are transmitted to the sensing pattern through the connection portion and the connection electrode.

Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concepts are not limited to such embodiments, but rather to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as would be apparent to a person of ordinary skill in the art.