Patent ID: 12248783

DETAILED DESCRIPTION

Embodiments of methods for frequency scaling for per-core accelerator assignments and associated apparatus are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

For clarity, individual components in the Figures herein may also be referred to by their labels in the Figures, rather than by a particular reference number. Additionally, reference numbers referring to a particular type of component (as opposed to a particular component) may be shown with a reference number followed by “(typ)” meaning “typical.” It will be understood that the configuration of these components will be typical of similar components that may exist but are not shown in the drawing Figures for simplicity and clarity or otherwise similar components that are not labeled with separate reference numbers. Conversely, “(typ)” is not to be construed as meaning the component, element, etc. is typically used for its disclosed function, implement, purpose, etc.

Under today's CPU architecture, when a core sees an AVX instruction of a certain type (e.g., an AVX2/512 instruction), the core informs a central Power Control Unit (PCU) and waits for a response as these instructions require more current/power to execute. The response that comes back from the PCU informs the requesting core at what frequency it needs to run. This is called license granting and is done to keep total current draw and power consumption in check and avoid damage to the CPU. The core frequency is then switched to execute the AVX instruction.

Subsequently, when the core detects regular instructions (e.g., SSE or “light” AVX2 instructions), it informs the PCU and switches back to normal mode of operation, also referred to herein as the SSE mode. Whenever a core is switching from a lower power to a higher power license mode (e.g., SSE to AVX512), there is a wait time during which no instructions are executed by the requesting core. This wait time is to allow for voltage and current to ramp up.

For examples, latencies can occur during frequency scaling transitions for some accelerator instructions such as AVX3 instructions for processing computational intense L1 (Layer 1) baseband processing for 5G applications such as FlexRAN (Radio Access Network) (referred to herein as AVX3/5G-ISA instructions, which include AVX3, AVX/5G-ISA, and AVX512 instructions). Latencies as high as several hundred microseconds can occur during frequency scaling transitions between processing AVX3/5G-ISA and non-AVX3/5G-ISA instructions.

Certain workloads like FlexRAN are susceptible to this wait time given strict time budgets to process incoming/outgoing data. As a result, FlexRAN-like workloads tend to put either the CPU or entire system in a fixed license mode to avoid jitter caused by wait times when switching between license modes. While this avoids jitter related issues, performance suffers due to lower frequency, as all cores are stuck in a fixed license irrespective of the type of instructions they are executing.

In accordance with aspects of the embodiments disclosed herein, a solution is provided to alleviate this problem by enabling pre-granting of license modes on a per-core basis instead of at the CPU or system level. This allows users to keep cores that execute time sensitive code in a pre-granted license mode without impacting other cores in the system, supporting higher overall performance. Moreover, the cores may be dynamically (re)configured during runtime on a per-core basis, and the frequency of cores may also be dynamically adjusted on a per core basis.

In some embodiments cores may be autonomously configured in response to detection of extended instructions (e.g., AVX3, AVX/5G-ISA, and AVX512 instructions) with substantially no latency and jitter. The ability to support per core licensing increases CPU performance since cores can change licensing mode on an as-needed basis and thus frequency scaling and power can be dynamically adjusted based on the requirements of individual applications and/or threads executing on the CPU cores.

In some embodiments herein, some cores are depicted as operating in an AVX3/5G-ISA license mode. These AVX3 instructions support HFNI (half-float new instructions). HFNI, also referred to as FP16 (16-bit floating point) architecture, provides separate denormal controls for FP16 operations that facilitate using the full dynamic range of the FP16 numbers. It is expected that denormal operations on FP16 will operate at near full speed.

A comparison between the core frequency operation for a current CPU100supporting per-socket frequency scaling for accelerator assignments and a CPU102supporting per-core frequency scaling for accelerator assignments is shown inFIG.1. CPU100includes 32 cores104that are operating in a license mode supporting AVX instructions. To meet the CPU TDP specification (in this example 185 (W)atts), all cores104are operated at a frequency of 1.4 GHz. Under a maximum performance “turbo mode,” all cores104may operate a 1.9 GHz. By comparison, if all cores were operated in the lower-power SSE license mode, the based TDP frequency would be 1.5 GHz and the max turbo mode would be 2.4 GHz.

Under the per-core frequency scaling for accelerator assignment provided by CPU102, eight cores106are configured to operate in SSE mode, while 24 cores104are configured to operate in license mode supporting AVX instructions (in this example including AVX3/5G-ISA instructions). For TDP, the processor power specification is 185 W, the same as for CPU100.

Under an aspect of CPU102, the cores are configured with one or more separate Fused Multiply Add (FMA) units that are used for selected AVX instructions (including AVX3/5G-ISA instructions). The FMA unit is also referred to as an ISA extension unit since it supports a set of one or more instructions that comprise an extension to the set of ISA instructions provided in a core's main logic circuitry. The power states of the FMA unit may be controlled separately from the cores such that an FMA unit may be selectively placed in a low power or idle power state under which the FMA unit consumes substantially no power. Accordingly, for cores106the FMA unit is idled (or effectively disabled), enabling cores106to support x86 and SSE instructions. Under some embodiments, the “main” core circuitry may also support some AVX instructions that require lower power than other higher-power AVX instructions implemented in the FMA unit; these AVX instructions are called “light” AVX-light instructions.

Returning to the 185 W TDP specification, this is a power budget for the cumulative power consumed by all the CPU cores for the processor. Since the FMA units for cores106are idled or disabled, the power consumed by cores106at a given frequency is lower than for cores104. This enables the frequencies of both cores106and104for CPU102to be increased while staying within the 185 W power budget. As discussed and illustrated in further detail below, different combinations of frequencies may be applied to cores106and104and be at or below the TDP level or, when operating under turbo mode, the maximum power level. For illustrative purposes,FIG.1shows base TDP frequencies of 1.8 GHz for both cores106and104, and respective turbo mode frequencies of 2.7 GHz for cores106and 2.6 GHz for cores104.

FIG.2shows a core frequency table200for the 32 core (8 SSE/24 AVX) configuration of CPU102at a TDP of 185 W, with SSE frequencies on the Y-axis and AVX3 (short for AVX3/5G-ISA) frequencies on the X-axis. Each SSE/AVX3 frequency combination with a white background results in a power consumption level of 185 W or less, while SSE/AVX3 frequency combinations with a gray background exceed 185 W (and thus would not meet the 185 W TDP limit). As illustrated by the table entries that are encircled, there are multiple combination of SSE/AVX3 frequencies that are at or close to the 185 W TDP limit.

FIG.3shows a core frequency table300for a 32 core 16 SSE/16 AVX configuration for a CPU at a TDP of 185 W. In the 184 W highlighted example shown in bold outline, the base TDP SSE frequency is 2.1 GHz and the base AVX3/5G-ISA frequency of 1.8 GHz. Under the turbo mode the maximum SSE frequency is 2.7 GHz and the maximum AVX3/5G-ISA frequency is 2.3 GHz. As before, different combinations of frequencies for the SSE cores and the AVX cores may be used to meet the TDP power budget of 185 W and higher power levels for the turbo mode.

FIG.4shows a core frequency table400for a 32 core 8 SSE/24 AVX configuration for a CPU at a TDP of 225 W. In the 225 W highlighted example shown in bold outline, the base TDP SSE frequency is 2.5 GHz and the base AVX3/5G-ISA frequency is 2.3 GHz. Under the turbo mode the maximum SSE frequency is 3.0 GHz and the maximum AVX3/5G-ISA frequency is 2.6 GHz. Different combinations of frequencies for the SSE cores and the AVX cores may be used to meet the TDP power budget of 225 W and higher power levels for the turbo mode.

FIG.5shows a core frequency table500for a 32 core 16 SSE/16 AVX configuration for a CPU at a TDP of 225 W. In the 225 W highlighted example shown in bold outline, the base TDP SSE frequency is 2.5 GHz and the base AVX3/5G-ISA frequency is 2.5 GHz. Under the turbo mode the maximum SSE frequency is 3.0 GHz and the maximum AVX3/5G-ISA frequency is 2.8 GHz. Different combinations of frequencies for the SSE cores and the AVX cores may be used to meet the TDP power budget of 225 W and higher power levels for the turbo mode.

FIG.6aillustrates a processor core600configured to be selectively operated as an SSE core or an AVX core, according to one embodiment including a single FMA unit. Processor core600includes core logic602, an AVX2 logic block604, an FMA unit606, and an FMA power and frequency control logic block608. Core logic602includes circuitry for implementing core ISA instructions, such as x86 instructions and SSE instructions in one embodiment. AVX2 logic block604includes circuitry to implement AVX2 and (optionally) AVX instructions. FMA unit606includes circuitry for implementing AVX3 instructions (e.g., AVX3/5G-ISA instructions). FMA power and frequency control logic block608is used to selectively control the frequency of processor core600and selectively control whether FMA unit606is enabled or disabled (by controlling the power state of the FMA unit).

FIG.6bshows a processor core600bconfigured to support AVX3/5G-ISA instructions. This configuration may be implemented by having FMA power and frequency control logic block608activate FMA unit606.FIG.6cshows a processor core600cconfigured to operate as an SSE core that has FMA unit606disabled (i.e., put in a low or idle power state). As discussed above, processor core600c(an SSE core) consumes less power than processor core600b(an AVX3 core) when both cores are operated at the same frequency. Generally, a given processor core can be preconfigured in the SSE and AVX3 core configurations during processor boot, as well as being dynamically reconfigured during ongoing runtime processor operations.

FIG.7aillustrates a processor core700configured to be selectively operated as an SSE core or an AVX core, according to one embodiment including two FMA units. Processor core700includes core logic702, an AVX2 logic block704, FMA unit706-1and706-2, and an FMA power and frequency control logic block708. Core logic702includes circuitry for implementing core ISA instructions, such as x86 instructions and SSE instructions in one embodiment. AVX2 logic block704includes circuitry to implement AVX2 and (optionally) AVX instructions. FMA units706-1and706-2include circuitry for implementing AVX3 instructions (e.g., AVX3/5G-ISA and AVX512 instructions). FMA power and frequency control logic block708is used to selectively control the frequency of processor core700and selectively control whether FMA units706-1and706-2are enabled or disabled (by controlling the power state of the FMA units).

FIG.7bshows a processor core700bconfigured to support AVX3/5G-ISA instructions. This configuration may be implemented by having FMA power and frequency control logic block708activate FMA units706-1and706-2.FIG.7cshows a processor core700cconfigured to operate as an SSE core that has FMA units706-1and706-2disabled (i.e., put in a low or idle power state). As before, processor core700c(an SSE core) consumes less power than processor core700b(an AVX3 core) when both cores are operated at the same frequency. Generally, a given processor core can be preconfigured in the SSE and AVX3 core configurations during processor boot, as well as being dynamically reconfigured during ongoing runtime processor operations.

Autonomous Configuration

In some embodiments all or a portion of the cores may be autonomously configured to enable and disable one or more FMA units. Operations and logic implemented by one embodiment are shown in a flowchart800inFIG.8. The process begins in a start back802in which a core is configured and executing in SSE license mode. The core executes a thread of instructions using it core circuitry, as depicted in a block804. In conjunction with execution of instructions in the instruction thread, extended instructions may be encountered, as depicted by a decision block806. An extended instruction is any instruction that is not supported by the ISA in the core block of circuitry, such as an AVX3, AVX5G-ISA, AVX512, or any other instruction that is implemented in an FMA unit or other ISA extension unit.

In response to detection of an extended instruction, the core is dynamically switched to AVX license mode as shown in a block808. This enables/activates circuitry in one of more FMA units (as applicable). In one embodiment, that latency to activate an FMA unit is on the order of a few microseconds. In an optional block810, the frequency of the core is adjusted. For example, the core frequency may be adjusted downward. In a block812an FMA unit is used to execute the extended instruction. As shown in a block814and a decision block816, the core continues to execute instructions in AVX license mode until an SSE return event occurs (i.e., and event under which the core is to be returned to SSE license mode). For example, in one embodiment a core is returned to SSE license mode if no extended instructions have been executed for a predetermined amount of time.

Cores with Multiple ISA Extension Units with Different Instructions

In some embodiments there are cores with multiple ISA extension units with different instructions. In some embodiments, the multiple ISA extension units including first FMA unit supporting a first set of one or more instructions that operate at a first frequency and a second FMA unit supporting a second set of one or more instructions that operates at a second frequency. In some embodiments the first and second FMA units can be enabled and disabled independently.

For example,FIG.9aillustrates a processor core900having two FMA units configured to be selectively operated in three license modes: SSE, AVX2, and AVX3. Processor core900includes core logic902, FMA unit906-1and906-2, and an FMA power and frequency control logic block908. Core logic902includes circuitry for implementing core ISA instructions, such as x86 instructions and SSE instructions in one embodiment. In another embodiment, core logic902includes circuitry for also implementing the first generation of AVX instructions. FMA unit906-1includes circuitry for implementing AVX2 instructions. FMA unit906-2include circuitry for implementing AVX3 instructions (e.g., AVX3/5G-ISA and AVX512 instructions). FMA power and frequency control logic block908is used to selectively control the frequency of processor core900and selectively control whether FMA units906-1and906-2are enabled or disabled (by controlling the power state of the FMA units).

FIG.9bshows a processor core900bconfigured to operate as an SSE core (i.e., in SSE license mode) that has FMA units906-1and906-2disabled (i.e., put in a low or idle power state).FIG.9cshows a processor core900cconfigured to further support AVX2 instructions and corresponding to an AVX2 license mode. This configuration may be implemented by having FMA power and frequency control logic block908activate FMA unit906-1while leaving FMA unit906-2inactive.FIG.9dshows a processor core900dconfigured to support AVX3/5G-ISA instructions (e.g., AVX3/5G-ISA and AVX512 instructions), corresponding to an AVX3 license mode. This configuration may be implemented by having FMA power and frequency control logic block908activate FMA unit906-2while leaving FMA unit906-1inactive.FIG.9eshows a processor core900ewith both FMA units906-1and906-2enabled to support AVX2, AVX3/5G-ISA, and AVX512 instructions and corresponding to an AVX2+AVX3 license mode. This configuration may be implemented by having FMA power and frequency control logic block908activate FMA units906-1and906-2. Generally, a given processor core can be preconfigured in any of the configurations shown inFIGS.9b,9c,9d, and9eduring processor boot, as well as being dynamically reconfigured during ongoing runtime processor operations.

FIGS.10a,10b, and10cshow flowcharts illustrating operations for transitioning between some license modes. As depicted by a block1002in flowchart1000ofFIG.10a, the core is initially operating in an SSE license mode at a first frequency 1 corresponding to core900binFIG.9b. To transition to the AVX2 license mode (block1008) the core frequency is reduced to frequency 2 in block1004prior to activating FMA unit 1 in block1006. This configuration corresponds to core900cinFIG.9c.

Flowchart1010ofFIG.10bshows a transition from an SSE license mode to an AVX3 license mode. The process begins in a block1012with the core operating in SSE license mode (core900binFIG.9b) at frequency 1. In a block1014, the frequency is reduced from frequency 1 to frequency 3, followed by FMA unit 2 being activated in a block1016to obtain the core configuration of900dshown inFIG.9dand the AVX3 license mode depicted in block1018.

Flowchart1020ofFIG.10cshows a transition from the AVX2 license mode to an AVX2+AVX3 license mode. The process begins in a block1022with the core operating in AVX2 license mode (core900cinFIG.9c) at frequency 2. In a block1024, the frequency is reduced from frequency 2 to frequency 4, followed by FMA unit 2 being activated in a block1026to obtain the core configuration of900eshown inFIG.9eand as depicted by AVX2+AVX3 license mode in block1028. Under the core configuration900e, both FMA unit 1 and unit 2 are activated. Accordingly, to maintain power consumption balance, frequency 4 is less that frequency 3.

Transitioning from an AVX2 license mode to an SSE license mode entails operations that are the reverse of those shown in flowchart1000ofFIG.10a, except FMA unit 1 is deactivated in block1006and the frequency is increased from frequency 2 to frequency 1 in block1004. Similarly, transitioning from an AVX3 license mode to an SSE license mode entails operations that are the reverse of those shown in flowchart1010ofFIG.10b, except FMA unit 2 is deactivated in block1016and the frequency is increased from frequency 3 to frequency 1 in block1004. Likewise, transitioning from an AVX2+AVX3 license mode to an AVX2 license mode entails operations that are the reverse of those shown in flowchart1020ofFIG.10c, except FMA unit 2 is deactivated in block1026and the frequency is increased from frequency 4 to frequency 2 in block1014.

In some embodiments, an FMA unit includes circuitry for implementing Advanced Matrix Extension (AMX) instructions. AMX instructions are targeted for performing matrix operations used for machine learning (ML) algorithms and artificial intelligence (AI) applications. For example, ML algorithms and frameworks used for deep learning employ multiple layers of artificial neurons that are interconnected to form a neural network, commonly referred to as an ANN. ML algorithms for ANNs employ a tremendous level of matrix mathematics, and AMX instructions are designed enhance the performance of such algorithms.

For example,FIG.11illustrates a processor core1100having two FMA units configured to be selectively operated in three license modes: SSE, AMX, and AVX3. Processor core1100includes core logic1102, an optional AVX2 logic block1104, FMA units1106-1and1106-2, and an FMA power and frequency control logic block1108. Core logic1102includes circuitry for implementing core ISA instructions, such as x86 instructions and SSE instructions in one embodiment. Optional AVX2 logic block1104includes circuitry to implement AVX2 and (optionally) AVX instructions. FMA unit1106-1includes circuitry for implementing AMX instructions. FMA unit1106-2include circuitry for implementing AVX3 instructions (e.g., AVX3/5G-ISA and AVX512 instructions). FMA power and frequency control logic block1108is used to selectively control the frequency of processor core1100and selectively control whether FMA units1106-1and1106-2are enabled or disabled (by controlling the power state of the FMA units).

In a manner similar to that described above for processor core900, FMA units1106-1and1106-2may be individually enabled (activated) and disabled (deactivated). A processor implementing processor core1100may support autonomous per-core configuration, as well as pre-configuration on a per-core basis.

FIG.12shows a server platform1200that includes a SoC processor1202with a plurality of cores configured to support per-core frequency scaling for accelerator assignment in accordance with aspects of the embodiments discussed above. SoC1202includes 48 tiles1204arranged in six rows and eight columns. Each tile1204includes a respective mesh stop1206, with the mesh stops interconnected in each row by a ring interconnect1208and in each column by a ring interconnect1210. Generally, ring interconnects1208and1210may be implemented as uni-directional rings (as shown) or bi-directional rings. Each ring interconnect1208and1210includes many wires (e.g., upwards of 1000) that are shown as single arrows for simplicity. The ring interconnects wiring is generally implemented in 3D space using multiple layers, and selected mesh stops support “turning” under which the direction of data, signals, and/or messages that are routed using the ring interconnects may change (e.g., from a horizontal direction to vertical direction and vice versa).

Processor SoC1202includes 32 cores1212, each implemented on a respective tile1204and co-located with an L1 and L2 cache, as depicted by caches1214for simplicity. Processor SoC1202further includes a pair of memory controllers1216and1218, each connected to one of more DIMMs (Dual In-line Memory Modules)1220via one or more memory channels1222. Generally, DIMMs may be any current or future type of DIMM such as DDR4 (double data rate, fourth generation) or DDR5. Alternatively, or in addition to, NVDIMMs (Non-volatile DIMMs) may be used, such as but not limited to Intel® 3D-Xpoint® NVDIMMs.

In the illustrated embodiment, memory controllers1216and1218are in a row including 12 Last Level Caches (LLCs)1223. The number of LLCs may vary by processor design. Under some architectures, each core is allocated a respective “slice” of an aggregated LLC (a single LLC that is shared amongst the cores). In other embodiments, allocation of the LLCs is more or less granular.

Processor SoC1202further includes a pair of inter-socket links1224and1226, and six Input-Output (IO) tiles1228,1229,1230,1231,1232, and1233. Generally, IO tiles are representative of various types of IO components that are implemented on SoCs, such as Peripheral Component Interconnect (PCIe) IO components, storage device IO controller (e.g., SATA, PCIe), high-speed interfaces such as DMI (Direct Media Interface), Low Pin-Count (LPC) interfaces, Serial Peripheral Interface (SPI), etc. Generally, a PCIe IO tile may include a PCIe root complex and one or more PCIe root ports. The IO tiles may also be configured to support an IO hierarchy (such as but not limited to PCIe), in some embodiments.

As further illustrated inFIG.12, IO tile1228is connected to a firmware storage device1234via an LPC link, while IO tile1230is connected to a non-volatile storage device1236such as a Solid-State Drive (SSD), or a magnetic or optical disk via a SATA link. Additionally, IO interface1233is connected to a Network Interface Controller (NIC)1238via a PCIe link, which provides an interface to an external network1240.

Inter-socket links1224and1226are used to provide high-speed serial interfaces with other SoC processors (not shown) when server platform1200is a multi-socket platform. In one embodiment, inter-socket links1224and1226implement Universal Path Interconnect (UPI) interfaces and SoC processor1202is connected to one or more other sockets via UPI socket-to-socket interconnects.

It will be understood by those having skill in the processor arts that the configuration of SoC processor1202is simplified for illustrative purposes. A SoC processor may include additional components that are not illustrated, such as additional LLC tiles, as well as components relating to power management, and manageability, just to name a few. In addition, the use of 32 cores and 32 core tiles illustrated in the Figures herein is merely exemplary and non-limiting, as the principles and teachings herein may be applied to SoC processors with any number of cores.

Tiles are depicted herein for simplification and illustrative purposes. Generally, a tile is representative of a respective IP (intellectual property) block or a set of related IP blocks or SoC components. For example, a tile may represent a processor core, a combination of a processor core and L1/L2 cache, a memory controller, an IO component, etc. Each of the tiles may also have one or more agents associated with it (not shown).

Each tile includes an associated mesh stop node, also referred to as a mesh stop, which are similar to ring stop nodes for ring interconnects. Some embodiments may include mesh stops (not shown) that are not associated with any particular tile, and may be used to insert additional message slots onto a ring, which enables messages to be inserted at other mesh stops along the ring; these tiles are generally not associated with an IP block or the like (other than logic to insert the message slots).FIG.12illustrates an example an SoC Processor showing tiles and their associated mesh stops.

Cores1212may be selectively configured as to operate in any of the license modes described and illustrated herein (for simplicity and lack of space, the depiction of cores1212is abstracted inFIG.12). Power management facilities on processor SoC (not separately shown) may be used to provide control signals or commands to the FMA power and frequency control logic block for each core.

Exemplary Application Contexts

FIG.13shows an exemplary application context the applies to a telecommunications system including a cell tower1300having a plurality of antennas1302and having a street cabinet1304at its base that is coupled to a data center edge1306via a high-bandwidth link1307. Each one or more server platforms1308are installed in street cabinet1304and multiple server platforms1308are installed in data center edge1306. Server platform1308may be a single socket platform or a dual-socket platform, with each socket (i.e., SoC processor) having 32 cores. Under the illustrated configuration, 20-22 of the 32 cores are configured to operate in the AVX3 license mode (and have configurations700bwith FMA units706-1and706-2enabled), while 8-10 of the 32 cores are configured as SSE cores (and have configuration700cwith FMA units706-1and706-2disabled).

In one embodiment server platforms1308are running Intel's® FlexRAN software (a type of virtual RAN or vRAN), which provides optimized libraries and L1/L2 pipeline for LTE and for 5G NR Layer 1 (L1) workload acceleration. This set of libraries supports Forward Error Correction (FEC), rate matching, cyclic redundancy check (CRC), channel estimation, MIMO detection, beamforming and other appropriate functions as specified in the 3rd Generation Partnership Project (3GPP) standards. FlexRAN is also designed to be integrated with the Data Plane Development Kit (DPDK) Wireless Baseband device library (BBDEV) virtual Poll Mode Driver (PMD).

DPDK logically divides workload processing into data plane and control plane operations. For FlexRAN, the data plane operations include LTE and 5G L1 (Physical Layer) signal processing. The AVX3/5G-ISA instructions include instructions that are specifically designed to address LTE and 5G L1 signal processing, including the HFNI instructions discussed above. In one embodiment, the workload is split between the data plane and control plane such that 70-75% of the cores are used to support signal processing and/or baseband operations with the remaining 25-30% of the cores being used to support control plane operations. This split is shown inFIG.13, where the 20-22 AVX cores are used to perform data plane operations and signal processing, as depicted in a block1310, while the 8-10 SSE cores are used for performing control plane operations.

FIGS.14and15shows further details of a VRAN application context, according to one embodiment. Diagram1400inFIG.14depicts a remote radio unit (RRU)1402implemented in a cell tower1404having a baseband unit (BBU)1406and coupled to a mobile backhaul network1408. RRU1402includes digital to analog and analog to digital radio frequency (DAC/ADC RF) equipment and is configured to implement Fast Fourier transforms and inverse Fast Fourier transforms in an FFT/iFFT block1410and is configured to implement downlink and uplink beamforming1412. BBU implements hardware-based Forward Error Correction (FEC) using an one or more accelerators implemented as an FPGA or ASIC1414and runs a software stack1416on a processor1418. Software stack1416is partitioned into an L1 stack1420used for baseband processing and an L2-rt (real-time) stack1422used for scheduling and packet processing.

FIG.15shows further details of processor1416, according to one configuration. As shown, processor1416includes 32 cores with 12 cores1500configured in an SSE license mode, 12 cores1502configured in an AMX license mode, and 8 cores1504configured in an AVX3 license mode. Cores1502execute software including AMX instructions to perform an AMX workload1508. Cores1504execute software including AVX3 instructions (e.g., AVX3/5G-ISA instructions) to perform an AVX3 workload, while cores1500execute SSE and optionally AVX/AVX2 instruction to perform a non-AVMX workload1506. Exemplary base and turbo mode frequencies for cores1500,1502, and1504are also shown in the right side ofFIG.15.

In some embodiments, the cores in the processor of a BBU are pre-configured based on the workload. An advantage of pre-configuration is that it eliminates the possibility of jitter caused by switching between licensing modes; rather selected cores are preconfigured to perform workloads via execution of instructions associated with the workloads. In the context of mobile networking, facilities are used for managing various distributed equipment, such as BBUs. In some environments these facilities include a management and orchestration layer (MANO) comprising one or more servers that run management and orchestration code.

FIG.16shows a flowchart1600illustrating an example of pre-configurating the processor of a BBU in consideration of the workload that is to be handled. The process begins in a block6012where the BBU is booted. This includes booting of the system firmware and may also include booting of an operating system on the hardware in some embodiments, while other embodiments that are implemented using bare metal (Type-1) hypervisors or containers will boot up applicable software to support those environments.

In a block1604communication is enabled (e.g., communication between the BBU and a management entity). Under some embodiments, the communication will be supported by software components running on the processor, such as a conventional networking stack. In other embodiments, out-of-band (OOB) communication between a management entity such and the BBU may be supported under which the processor cores are configured using an OOB channel.

In a block1606the cores are (pre-)configured. As depicted, one or more workloads1608are provided to a MANO1610that examines the workload(s) and determines how to preconfigure the cores for the BBU processor to best perform them. Workload(s)1608is illustrative of one or more identified workloads or otherwise may identify a particular deployment package to be executed on the processor, such as a VRAN package.

After the cores are configured, the workload(s) are executed using the processor cores, as depicted in a block1612. As an illustrative example, cores1500,1502, and1504for processor1416inFIGS.14and15are preconfigured in one embodiment.

The processor SoCs and server platforms described and illustrated herein may be used to support other types of workloads using existing and future software applications/libraries. For instance, applications requiring workload acceleration provided by a portion of a processors ISA instructions that are implemented in a separate unit or block of circuitry in a core (that can be selectively enabled and disabled) may be well-suited for implementation with these processor SoCs and server platforms. As used herein, selectively enabled and disabled include cores include one or more ISA extension units that may be one or more of pre-configured prior to runtime and dynamically configured during runtime. Dynamically configured includes having some entity or component on the processor enable and disable cores as well as cores that perform autonomous configuration changes.

Although some embodiments have been described in reference to particular implementations, other implementations are possible according to some embodiments. Additionally, the arrangement and/or order of elements or other features illustrated in the drawings and/or described herein need not be arranged in the particular way illustrated and described. Many other arrangements are possible according to some embodiments.

In each system shown in a figure, the elements in some cases may each have a same reference number or a different reference number to suggest that the elements represented could be different and/or similar. However, an element may be flexible enough to have different implementations and work with some or all of the systems shown or described herein. The various elements shown in the figures may be the same or different. Which one is referred to as a first element and which is called a second element is arbitrary.

In the description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. Additionally, “communicatively coupled” means that two or more elements that may or may not be in direct contact with each other, are enabled to communicate with each other. For example, if component A is connected to component B, which in turn is connected to component C, component A may be communicatively coupled to component C using component B as an intermediary component.

An embodiment is an implementation or example of the inventions. Reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments, of the inventions. The various appearances “an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments.

Not all components, features, structures, characteristics, etc. described and illustrated herein need be included in a particular embodiment or embodiments. If the specification states a component, feature, structure, or characteristic “may”, “might”, “can” or “could” be included, for example, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the element. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional element.

As discussed above, various aspects of the embodiments herein may be facilitated by corresponding software and/or firmware components and applications, such as software and/or firmware executed by an embedded processor or the like. Thus, embodiments of this invention may be used as or to support a software program, software modules, firmware, and/or distributed software executed upon some form of processor, processing core or embedded logic a virtual machine running on a processor or core or otherwise implemented or realized upon or within a non-transitory computer-readable or machine-readable storage medium. A non-transitory computer-readable or machine-readable storage medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a non-transitory computer-readable or machine-readable storage medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form accessible by a computer or computing machine (e.g., computing device, electronic system, etc.), such as recordable/non-recordable media (e.g., read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). The content may be directly executable (“object” or “executable” form), source code, or difference code (“delta” or “patch” code). A non-transitory computer-readable or machine-readable storage medium may also include a storage or database from which content can be downloaded. The non-transitory computer-readable or machine-readable storage medium may also include a device or product having content stored thereon at a time of sale or delivery. Thus, delivering a device with stored content, or offering content for download over a communication medium may be understood as providing an article of manufacture comprising a non-transitory computer-readable or machine-readable storage medium with such content described herein.

Various components referred to above as processes, servers, or tools described herein may be a means for performing the functions described. The operations and functions performed by various components described herein may be implemented by software running on a processing element, via embedded hardware or the like, or any combination of hardware and software. Such components may be implemented as software modules, hardware modules, special-purpose hardware (e.g., application specific hardware, ASICs, DSPs, etc.), embedded controllers, hardwired circuitry, hardware logic, etc. Software content (e.g., data, instructions, configuration information, etc.) may be provided via an article of manufacture including non-transitory computer-readable or machine-readable storage medium, which provides content that represents instructions that can be executed. The content may result in a computer performing various functions/operations described herein.

As used herein, a list of items joined by the term “at least one of” can mean any combination of the listed terms. For example, the phrase “at least one of A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C.

The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification and the drawings. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.