Patent ID: 12199576

DETAILED DESCRIPTION

An electronic device may be provided with wireless communications circuitry. The wireless communications circuitry may include a transceiver circuit for transmitting and receiving radio-frequency signals, one or more radio-frequency amplifiers for amplifying the radio-frequency signals, and an antenna for radiating and receiving the radio-frequency signals. The radio-frequency amplifier may be operable in at least a nominal (high) gain mode and one or more low gain modes across a wide range of frequency bands. The term “radio-frequency amplifier” referred to herein may be a power amplifier, a low noise amplifier, or other amplifying circuits in the wireless communications circuitry.

The radio-frequency amplifier can include input transistors and capacitance neutralization transistors cross-coupled with the input transistors. The capacitance neutralization transistors can be coupled in series with large resistors to ensure zero current density through the capacitance neutralization transistors during the nominal (high) gain mode.

The radio-frequency (RF) amplifier can further include one or more gain adjustment switches that are selectively activated and deactivated to operate the radio-frequency amplifier in the low gain mode(s) and the high gain mode. In one exemplary embodiment, the gain adjustment switches can be coupled in parallel with the large resistors. During the high gain mode, the gain adjustment switches are turned off. During the low gain mode, one or more processors in the electronic device can turn on the gain adjustment switches to allow current that is out-of-phase with the current flowing through the input transistors to flow through the capacitance neutralization transistors, which reduces the gain of the radio-frequency amplifier. Configured and operated in this way, a wide range of gain attenuation can be achieved with fine resolution without negatively impacting the noise figure and frequency response between the high and low gain modes.

FIG.1is a diagram of an electronic device such as electronic device10that can be provided with such wireless transmission circuitry. Electronic device10may be a computing device such as a laptop computer, a desktop computer, a computer monitor containing an embedded computer, a tablet computer, a cellular telephone, a media player, or other handheld or portable electronic device, a smaller device such as a wristwatch device, a pendant device, a headphone or earpiece device, a device embedded in eyeglasses or other equipment worn on a user's head, or other wearable or miniature device, a television, a computer display that does not contain an embedded computer, a gaming device, a navigation device, an embedded system such as a system in which electronic equipment with a display is mounted in a kiosk or automobile, a wireless internet-connected voice-controlled speaker, a home entertainment device, a remote control device, a gaming controller, a peripheral user input device, a wireless base station or access point, equipment that implements the functionality of two or more of these devices, or other electronic equipment.

As shown in the schematic diagramFIG.1, device10may include components located on or within an electronic device housing such as housing12. Housing12, which may sometimes be referred to as a case, may be formed of plastic, glass, ceramics, fiber composites, metal (e.g., stainless steel, aluminum, metal alloys, etc.), other suitable materials, or a combination of these materials. In some situations, parts or all of housing12may be formed from dielectric or other low-conductivity material (e.g., glass, ceramic, plastic, sapphire, etc.). In other situations, housing12or at least some of the structures that make up housing12may be formed from metal elements.

Device10may include control circuitry14. Control circuitry14may include storage such as storage circuitry16. Storage circuitry16may include hard disk drive storage, nonvolatile memory (e.g., flash memory or other electrically-programmable-read-only memory configured to form a solid-state drive), volatile memory (e.g., static or dynamic random-access-memory), etc. Storage circuitry16may include storage that is integrated within device10and/or removable storage media.

Control circuitry14may include processing circuitry such as processing circuitry18. Processing circuitry18may be used to control the operation of device10. Processing circuitry18may include on one or more microprocessors, microcontrollers, digital signal processors, host processors, baseband processor integrated circuits, application processors, application specific integrated circuits, central processing units (CPUs), general purpose processors, or other types of processors. Control circuitry14may be configured to perform operations in device10using hardware (e.g., dedicated hardware or circuitry), firmware, and/or software. Software code for performing operations in device10may be stored on storage circuitry16(e.g., storage circuitry16may include non-transitory (tangible) computer readable storage media that stores the software code). The software code may sometimes be referred to as program instructions, software, data, instructions, or code. Software code stored on storage circuitry16may be executed by processing circuitry18.

Control circuitry14may be used to run software on device10such as satellite navigation applications, internet browsing applications, voice-over-internet-protocol (VOIP) telephone call applications, email applications, media playback applications, operating system functions, etc. To support interactions with external equipment, control circuitry14may be used in implementing communications protocols. Communications protocols that may be implemented using control circuitry14include internet protocols, wireless local area network (WLAN) protocols (e.g., IEEE 802.11 protocols—sometimes referred to as Wi-Fi®), protocols for other short-range wireless communications links such as the Bluetooth® protocol or other wireless personal area network (WPAN) protocols, IEEE 802.11ad protocols (e.g., ultra-wideband protocols), cellular telephone protocols (e.g., 3G protocols, 4G (LTE) protocols, 5G New Radio (NR) protocols, etc.), MIMO protocols, antenna diversity protocols, satellite navigation system protocols (e.g., global positioning system (GPS) protocols, global navigation satellite system (GLONASS) protocols, etc.), antenna-based spatial ranging protocols (e.g., radio detection and ranging (RADAR) protocols or other desired range detection protocols for signals conveyed at millimeter and centimeter wave frequencies), or any other desired communications protocols. Each communications protocol may be associated with a corresponding radio access technology (RAT) that specifies the physical connection methodology used in implementing the protocol.

Device10may include input-output circuitry20. Input-output circuitry20may include input-output devices22. Input-output devices22may be used to allow data to be supplied to device10and to allow data to be provided from device10to external devices. Input-output devices22may include user interface devices, data port devices, and other input-output components. For example, input-output devices22may include touch sensors, displays, light-emitting components such as displays without touch sensor capabilities, buttons (mechanical, capacitive, optical, etc.), scrolling wheels, touch pads, key pads, keyboards, microphones, cameras, buttons, speakers, status indicators, audio jacks and other audio port components, digital data port devices, motion sensors (accelerometers, gyroscopes, and/or compasses that detect motion), capacitance sensors, proximity sensors, magnetic sensors, force sensors (e.g., force sensors coupled to a display to detect pressure applied to the display), etc. In some configurations, keyboards, headphones, displays, pointing devices such as trackpads, mice, electronic pencil (e.g., a stylus), and joysticks, and other input-output devices may be coupled to device10using wired or wireless connections (e.g., some of input-output devices22may be peripherals that are coupled to a main processing unit or other portion of device10via a wired or wireless link).

Input-output circuitry20may include wireless communications circuitry such as wireless communications circuitry24(sometimes referred to herein as wireless circuitry24) for wirelessly conveying radio-frequency signals. While control circuitry14is shown separately from wireless communications circuitry24for the sake of clarity, wireless communications circuitry24may include processing circuitry that forms a part of processing circuitry18and/or storage circuitry that forms a part of storage circuitry16of control circuitry14(e.g., portions of control circuitry14may be implemented on wireless communications circuitry24). As an example, control circuitry14(e.g., processing circuitry18) may include processor circuitry or other control components that form a part of wireless communications circuitry24.

Wireless communications circuitry24may include radio-frequency (RF) transceiver circuitry formed from one or more integrated circuits, power amplifier circuitry configured to amplify uplink radio-frequency signals (e.g., radio-frequency signals transmitted by device10to an external device), low-noise amplifiers configured to amplify downlink radio-frequency signals (e.g., radio-frequency signals received by device10from an external device), passive radio-frequency components, one or more antennas, transmission lines, and other circuitry for handling radio-frequency wireless signals. Wireless signals can also be sent using light (e.g., using infrared communications).

Wireless circuitry24may include radio-frequency transceiver circuitry for handling transmission and/or reception of radio-frequency signals in various radio-frequency communications bands. For example, the radio-frequency transceiver circuitry may handle wireless local area network (WLAN) communications bands such as the 2.4 GHz and 5 GHz Wi-Fi® (IEEE 802.11) bands, wireless personal area network (WPAN) communications bands such as the 2.4 GHz Bluetooth® communications band, cellular telephone communications bands such as a cellular low band (LB) (e.g., 600 to 960 MHz), a cellular low-midband (LMB) (e.g., 1400 to 1550 MHz), a cellular midband (MB) (e.g., from 1700 to 2200 MHz), a cellular high band (HB) (e.g., from 2300 to 2700 MHz), a cellular ultra-high band (UHB) (e.g., from 3300 to 5000 MHz), or other cellular communications bands between about 600 MHz and about 5000 MHz (e.g., 3G bands, 4G LTE bands, 5G New Radio Frequency Range 1 (FR1) bands below 10 GHz, 5G New Radio Frequency Range 2 (FR2) bands at millimeter and centimeter wavelengths between 20 and 60 GHz, etc.), a near-field communications (NFC) band (e.g., at 13.56 MHz), satellite navigations bands (e.g., an L1 global positioning system (GPS) band at 1575 MHz, an L5 GPS band at 1176 MHz, a Global Navigation Satellite System (GLONASS) band, a BeiDou Navigation Satellite System (BDS) band, etc.), an ultra-wideband (UWB) communications band supported by the IEEE 802.15.4 protocol and/or other UWB communications protocols (e.g., a first UWB communications band at 6.5 GHz and/or a second UWB communications band at 8.0 GHz), and/or any other desired communications bands. The communications bands handled by such radio-frequency transceiver circuitry may sometimes be referred to herein as frequency bands or simply as “bands,” and may span corresponding ranges of frequencies. In general, the radio-frequency transceiver circuitry within wireless circuitry24may cover (handle) any desired frequency bands of interest.

FIG.2is a diagram showing illustrative components within wireless circuitry24. As shown inFIG.2, wireless circuitry24may include a processor such as processor26, radio-frequency (RF) transceiver circuitry such as radio-frequency transceiver28, radio-frequency front end circuitry such as radio-frequency front end module (FEM)40, and antenna(s)42. Processor26may be a baseband processor, application processor, general purpose processor, microprocessor, microcontroller, digital signal processor, host processor, or other type of processor. Processor26may be coupled to transceiver28over path34. Transceiver28may be coupled to antenna42via radio-frequency transmission line path36. Radio-frequency front end module40may be disposed on radio-frequency transmission line path36between transceiver28and antenna42.

In the example ofFIG.2, wireless circuitry24is illustrated as including only a single processor26, a single transceiver28, a single front end module40, and a single antenna42for the sake of clarity. In general, wireless circuitry24may include any desired number of processors26, any desired number of transceivers36, any desired number of front end modules40, and any desired number of antennas42. Each processor26may be coupled to one or more transceiver28over respective paths34. Each transceiver28may include a transmitter circuit30configured to output uplink signals to antenna42, may include a receiver circuit32configured to receive downlink signals from antenna42, and may be coupled to one or more antennas42over respective radio-frequency transmission line paths36. Each radio-frequency transmission line path36may have a respective front end module40disposed thereon. If desired, two or more front end modules40may be disposed on the same radio-frequency transmission line path36. If desired, one or more of the radio-frequency transmission line paths36in wireless circuitry24may be implemented without any front end module disposed thereon.

Radio-frequency transmission line path36may be coupled to an antenna feed on antenna42. The antenna feed may, for example, include a positive antenna feed terminal and a ground antenna feed terminal. Radio-frequency transmission line path36may have a positive transmission line signal path such that is coupled to the positive antenna feed terminal on antenna42. Radio-frequency transmission line path36may have a ground transmission line signal path that is coupled to the ground antenna feed terminal on antenna42. This example is merely illustrative and, in general, antennas42may be fed using any desired antenna feeding scheme. If desired, antenna42may have multiple antenna feeds that are coupled to one or more radio-frequency transmission line paths36.

Radio-frequency transmission line path36may include transmission lines that are used to route radio-frequency antenna signals within device10(FIG.1). Transmission lines in device10may include coaxial cables, microstrip transmission lines, stripline transmission lines, edge-coupled microstrip transmission lines, edge-coupled stripline transmission lines, transmission lines formed from combinations of transmission lines of these types, etc. Transmission lines in device10such as transmission lines in radio-frequency transmission line path36may be integrated into rigid and/or flexible printed circuit boards.

In performing wireless transmission, processor26may provide transmit signals (e.g., digital or baseband signals) to transceiver28over path34. Transceiver28may further include circuitry for converting the transmit (baseband) signals received from processor26into corresponding radio-frequency signals. For example, transceiver circuitry28may include mixer circuitry for up-converting (or modulating) the transmit (baseband) signals to radio-frequencies prior to transmission over antenna42. The example ofFIG.2in which processor26communicates with transceiver28is merely illustrative. In general, transceiver28may communicate with a baseband processor, an application processor, general purpose processor, a microcontroller, a microprocessor, or one or more processors within circuitry18. Transceiver circuitry28may also include digital-to-analog converter (DAC) and/or analog-to-digital converter (ADC) circuitry for converting signals between digital and analog domains. Transceiver28may use transmitter (TX)30to transmit the radio-frequency signals over antenna42via radio-frequency transmission line path36and front end module40. Antenna42may transmit the radio-frequency signals to external wireless equipment by radiating the radio-frequency signals into free space.

In performing wireless reception, antenna42may receive radio-frequency signals from the external wireless equipment. The received radio-frequency signals may be conveyed to transceiver28via radio-frequency transmission line path36and front end module40. Transceiver28may include circuitry such as receiver (RX)32for receiving signals from front end module40and for converting the received radio-frequency signals into corresponding baseband signals. For example, transceiver28may include mixer circuitry for down-converting (or demodulating) the received radio-frequency signals to baseband frequencies prior to conveying the received signals to processor26over path34.

Front end module (FEM)40may include radio-frequency front end circuitry that operates on the radio-frequency signals conveyed (transmitted and/or received) over radio-frequency transmission line path36. FEM40may, for example, include front end module (FEM) components such as radio-frequency filter circuitry44(e.g., low pass filters, high pass filters, notch filters, band pass filters, multiplexing circuitry, duplexer circuitry, diplexer circuitry, triplexer circuitry, etc.), switching circuitry46(e.g., one or more radio-frequency switches), radio-frequency amplifier circuitry48(e.g., one or more power amplifier circuits50and/or one or more low-noise amplifier circuits52), impedance matching circuitry (e.g., circuitry that helps to match the impedance of antenna42to the impedance of radio-frequency transmission line36), antenna tuning circuitry (e.g., networks of capacitors, resistors, inductors, and/or switches that adjust the frequency response of antenna42), radio-frequency coupler circuitry, charge pump circuitry, power management circuitry, digital control and interface circuitry, and/or any other desired circuitry that operates on the radio-frequency signals transmitted and/or received by antenna42. Each of the front end module components may be mounted to a common (shared) substrate such as a rigid printed circuit board substrate or flexible printed circuit substrate. If desired, the various front end module components may also be integrated into a single integrated circuit chip.

Filter circuitry44, switching circuitry46, amplifier circuitry48, and other circuitry may be disposed along radio-frequency transmission line path36, may be incorporated into FEM40, and/or may be incorporated into antenna42(e.g., to support antenna tuning, to support operation in desired frequency bands, etc.). These components, sometimes referred to herein as antenna tuning components, may be adjusted (e.g., using control circuitry14) to adjust the frequency response and wireless performance of antenna42over time.

Transceiver28may be separate from front end module40. For example, transceiver28may be formed on another substrate such as the main logic board of device10, a rigid printed circuit board, or flexible printed circuit that is not a part of front end module40. While control circuitry14is shown separately from wireless circuitry24in the example ofFIG.1for the sake of clarity, wireless circuitry24may include processing circuitry that forms a part of processing circuitry18and/or storage circuitry that forms a part of storage circuitry16of control circuitry14(e.g., portions of control circuitry14may be implemented on wireless circuitry24). As an example, processor26and/or portions of transceiver28(e.g., a host processor on transceiver28) may form a part of control circuitry14. Control circuitry14(e.g., portions of control circuitry14formed on processor26, portions of control circuitry14formed on transceiver28, and/or portions of control circuitry14that are separate from wireless circuitry24) may provide control signals (e.g., over one or more control paths in device10) that control the operation of front end module40.

Transceiver circuitry28may include wireless local area network transceiver circuitry that handles WLAN communications bands (e.g., Wi-Fi® (IEEE 802.11) or other WLAN communications bands) such as a 2.4 GHz WLAN band (e.g., from 2400 to 2480 MHz), a 5 GHz WLAN band (e.g., from 5180 to 5825 MHz), a Wi-Fi® 6E band (e.g., from 5925-7125 MHz), and/or other Wi-Fi® bands (e.g., from 1875-5160 MHz), wireless personal area network transceiver circuitry that handles the 2.4 GHz Bluetooth® band or other WPAN communications bands, cellular telephone transceiver circuitry that handles cellular telephone bands (e.g., bands from about 600 MHz to about 5 GHz, 3G bands, 4G LTE bands, 5G New Radio Frequency Range 1 (FR1) bands below 10 GHz, 5G New Radio Frequency Range 2 (FR2) bands between 20 and 60 GHz, etc.), near-field communications (NFC) transceiver circuitry that handles near-field communications bands (e.g., at 13.56 MHz), satellite navigation receiver circuitry that handles satellite navigation bands (e.g., a GPS band from 1565 to 1610 MHz, a Global Navigation Satellite System (GLONASS) band, a BeiDou Navigation Satellite System (BDS) band, etc.), ultra-wideband (UWB) transceiver circuitry that handles communications using the IEEE 802.15.4 protocol and/or other ultra-wideband communications protocols, and/or any other desired radio-frequency transceiver circuitry for covering any other desired communications bands of interest.

Wireless circuitry24may include one or more antennas such as antenna42. Antenna42may be formed using any desired antenna structures. For example, antenna42may be an antenna with a resonating element that is formed from loop antenna structures, patch antenna structures, inverted-F antenna structures, slot antenna structures, planar inverted-F antenna structures, helical antenna structures, monopole antennas, dipoles, hybrids of these designs, etc. Two or more antennas42may be arranged into one or more phased antenna arrays (e.g., for conveying radio-frequency signals at millimeter wave frequencies). Parasitic elements may be included in antenna42to adjust antenna performance. Antenna42may be provided with a conductive cavity that backs the antenna resonating element of antenna42(e.g., antenna42may be a cavity-backed antenna such as a cavity-backed slot antenna).

As described above, front end module40may include one or more power amplifiers (PA) circuits50in the transmit (uplink) path and one or more low noise amplifier (LNA) circuits52in the receive (downlink) path. A radio-frequency amplifier (e.g., power amplifier50, low noise amplifier52, or other amplifying circuits within wireless communications circuitry24) may be configured to amplify a radio-frequency signal without changing the signal shape, format, or modulation. A radio-frequency amplifier may, for example, be used to provide 10 dB of gain, 20 dB of gain, 10-20 dB of gain, less than 20 dB of gain, more than 20 dB of gain, or other suitable amounts of gain.

A radio-frequency amplifier (sometimes referred to as amplifier circuitry) may have an adjustable gain.FIG.3is a state diagram showing how a radio-frequency amplifier can be operable in at least a high gain mode60and a low gain mode62. When operated in high gain mode60, the radio-frequency amplifier may be configured to provide a first amount of gain. The RF amplifier may include gain adjustment switches (e.g., gain adjustment transistors) that are deactivated during the high gain mode. When operated in the low gain mode62, the gain adjustment transistors may be activated so that the radio-frequency amplifier is configured to provide a second amount of gain that is less than the first amount of gain. The second amount of gain can be 2 dB less than the first amount of gain, 4 dB less than the first amount of gain 2-10 dB less than the first amount of gain, 10-20 dB less than the first amount of gain, 20-50 dB less than the first amount of gain, or other suitable attenuations of gain.

The example ofFIG.3showing only two different gain modes is merely illustrative. If desired, an radio-frequency amplifier can be operated in a high (nominal) gain mode and one or more low gain modes having gains that are reduced relative to the high gain mode (e.g., the RF amplifier can have at least three different gain modes, four or more different gain modes, 5-10 different gain modes, 10-100 different gain modes, etc.). It can be challenging to design a satisfactory radio-frequency amplifier with multiple gain modes for an electronic device.

FIG.4is a circuit diagram showing one illustrative implementation of a radio-frequency amplifier51. Amplifier51may represent power amplifier50, low noise amplifier52, or other amplifier circuitry within wireless communications circuitry24. As shown inFIG.4, amplifier51may include input transistors M1and M2. Transistors M1and M2may be n-type (n-channel) transistors such as n-type metal-oxide-semiconductor (NMOS) devices. Transistor M1may have a source terminal coupled to a ground power supply line80(e.g., a ground line on which ground power supply voltage Vss is provided), a drain terminal, and a gate terminal coupled to a positive input terminal In+ of amplifier51. Transistor M2may have a source terminal coupled to ground power supply line80, a drain terminal, and a gate terminal coupled to a negative input terminal In− of amplifier51. Input terminals In+ and In− serve collectively as the differential input port of amplifier51, so transistors M1and M2are sometimes referred to as input transistors.

The terms “source” and “drain” terminals used to refer to current-conveying terminals in a transistor may be used interchangeably and are sometimes referred to as “source-drain” terminals. Thus, the source terminal of transistor M1can sometimes be referred to as a first source-drain terminal, and the drain terminal of transistor M1can be referred to as a second source-drain terminal (or vice versa). The drain terminal of the first input transistor M1may be directly or indirectly (via one or more intervening components) coupled to a negative output terminal Out− of amplifier51. The drain terminal of the second input transistor M2may be directly or indirectly (via one or more intervening components) coupled to a positive output terminal Out+ of amplifier51. Output terminals Out+ and Out−, sometimes referred to as amplifier output terminals, serve collectively as the differential output port of amplifier51.

Amplifier51may further include n-type transistors M3and M4(e.g., NMOS devices). Transistor M3may have a source terminal coupled to ground power supply line80via a first resistor Rbig1, a gate terminal coupled to negative input terminal In−, and a drain terminal cross-coupled to the drain terminal of input transistor M1(at node N1). Transistor M4may have a source terminal coupled to ground power supply line80via a second resistor Rbig2, a gate terminal coupled to positive input terminal In+, and a drain terminal cross-coupled to the drain terminal of input transistor M2(at node N2). Configured in this way, transistors M3and M4are sometimes considered to be cross-coupled with input transistors M1and M2can be used to neutralize the gate-to-drain parasitic capacitance of input transistors M1and M2, which improves the overall gain of amplifier51. Thus, transistors M3and M4are sometimes referred to as parasitic capacitance neutralization transistors or capacitance cancellation transistors.

Resistors Rbig1and Rbig2that are connected to the source terminals of the capacitance neutralization transistors M3and M4are sometimes referred to as source resistors. Source resistors Rbig1and Rbig2should have relatively large resistance values so that in the nominal use case (e.g., in the high gain mode), all of the current flowing into nodes N1and N2will only flow into the input transistors M1and M2, respectively, without flowing into neutralization transistors M3and M4. Resistors Rbig1and Rbig2can each be at least ten thousand ohms, at least a thousand ohms, ten thousand to a hundred thousand ohms, or even millions of ohms. Thus, the use of capacitance neutralization transistors M3and M4with zero current density can be used to achieve high gain.

Conventional radio-frequency amplifiers with such type of differential pair topology achieves gain reduction by reducing the current density through the input transistors M1and M2. Reducing the amount of current flowing through the input transistors, however, degrades the noise performance of the amplifier while also potentially altering the in-band frequency response of that amplifier.

In accordance with an embodiment, radio-frequency amplifier51ofFIG.4may be provided with gain adjustment switches that can be used to adjust the gain of amplifier51without degrading the noise performance and while maintaining the in-band frequency response of amplifier51. As shown inFIG.4, a first gain adjustment switch Madj1(e.g., an n-type transistor) may have a source terminal coupled to ground line80, a drain terminal coupled to the source terminal of capacitance neutralization transistor M3, and a gate terminal configured to receive control signal Vcon. Gain adjustment transistor Madj1is therefore coupled in parallel with source resistor Rbig1. A second gain adjustment switch Madj2(e.g., an n-type transistor) may have a source terminal coupled to ground line80, a drain terminal coupled to the source terminal of capacitance neutralization transistor M4, and a gate terminal configured to receive control signal Vcon. Gain adjustment transistor Madj2is therefore coupled in parallel with source resistor Rbig2.

Gain adjustment transistors Madj1and Madj2can be controlled by signal Vcon generated by one or more processors88. Processor(s)88may, for example, represent one or more microprocessors, microcontrollers, digital signal processors, host processors, baseband processors, application processors, application specific integrated circuits, central processing units (CPUs), general purpose processors, and/or other types of processors. Processor88may sometimes be considered part of processor circuitry18shown inFIG.1, processor26of the type shown inFIG.2, or other types of processors.

During high gain mode, processor88may deassert signal Vcon (e.g., drive Vcon to a low voltage level) to deactivate gain adjustment transistors Madj1and Madj2. While transistors Madj1and Madj2are deactivated (turned off), there is zero current density through capacitance neutralization transistors M3and M4due to the large source resistance of Rbig1and Rbig2.

During low gain mode, processor88may assert signal Vcon (e.g., drive Vcon to a high voltage level) to activate gain adjustment transistors Madj1and Madj2. Activating (turning on) transistors Madj1and Madj2allows capacitance neutralization transistors M3and M4to now carry DC current (e.g., current from node N1can now flow through transistors M3and Madj2, whereas current from node N2can now flow through transistors M4and Madj2). Signal Vcon is therefore sometimes referred to as a gain control voltage or a gain adjustment voltage.

In particular, the current flowing through the capacitance neutralization transistors M3and M4will flow in the opposite phase (e.g., 180° phase offset) as the current flowing through the input transistors M1and M2. In other words, the current through transistor M3will be out-of-phase with the current flowing through transistor M1, whereas the current through transistor M4will be out-of-phase with the current flowing through transistor M2. Turning on gain adjustment transistors Madj1and Madj2to allow out-of-phase current to flow through capacitance neutralization transistors M3and M4achieves gain reduction for radio-frequency amplifier51while potentially canceling out multiplicative large signal noise such as bias noise without altering the frequency response between the high and low gain modes. Attaining gain reduction in this way can also improve noise characteristics in the low gain mode(s).

The sizing of gain adjustment transistors Madj1and Madj2can be fixed or variable. Very fine resolution in gain attenuation can be achieved by making the size of transistors Madj1and Madj2variable.FIG.5is a circuit diagram showing one suitable implementation of transistor Madj with variable/adjustable sizing. Transistor Madj may represent transistor Madj1and/or Madj2ofFIG.4. As shown inFIG.5, gain adjustment transistor Madj may include multiple transistors that are selectively switched into use using respective gate control voltages. For example, a first transistor90-1can be selectively activated by asserting a first gate control signal Vcon1; a second transistor90-2can be selectively activated by asserting a second gate control signal Vcon2; . . . ; and an Nthtransistor90-N can be selectively activated by asserting gate control signal VconN. The size of transistors90can be the same or can be different.

Control voltages Vcon1-VconN can be asserted (e.g., driven high) and deasserted (e.g., driven low) by processor88(seeFIG.4) to set the overall drive strength or sizing of transistor Madj. Increasing the size of gain adjustment transistor Madj can increase the amount of gain reduction and thus provide even more gain attenuation. If desired, a large range of gain attenuation may be achieved by setting the magnitude of the current through the capacitance neutralization transistors equal to the magnitude of the current through the input transistors (but still opposite in phase) in the lowest gain mode.

The example ofFIG.4in which capacitance neutralization transistors M3and M4are coupled to different source resistors Rbig1and Rbig2is merely illustrative.FIG.6illustrates another embodiment of amplifier51having capacitance neutralization transistors M3and M4coupled to a single source resistor Rbig. As shown inFIG.6, source resistor Rbig has a first terminal that is coupled to the source terminals of transistors M3and M4and a second terminal coupled to ground line80. Resistor Rbig can be at least ten thousand ohms, at least a thousand ohms, ten thousand to a hundred thousand ohms, or even millions of ohms to ensure that the current density in capacitance neutralization transistors M3and M4is zero in the nominal high gain use case.

In the example ofFIG.6, amplifier51includes a single gain adjustment switch Madj (e.g., an n-type transistor) that is coupled in parallel with source resistor Rbig. Gain adjustment transistor Madj can be controlled by signal Vcon generated by one or more processors88. During high gain mode, processor88may deassert signal Vcon (e.g., drive Vcon to a low voltage level) to deactivate gain adjustment transistor Madj. While transistor Madj is deactivated (turned off), there is zero current density through capacitance neutralization transistors M3and M4due to the large source resistance of Rbig.

During low gain mode, processor88may assert signal Vcon (e.g., drive Vcon to a high voltage level) to activate gain adjustment transistor Madj. Activating (turning on) transistor Madj allows capacitance neutralization transistors M3and M4to now carry DC current. In particular, the current flowing through the capacitance neutralization transistors M3and M4will flow in the opposite phase or out-of-phase with respect to the current flowing through the input transistors M1and M2. Turning on gain adjustment transistor Madj to allow out-of-phase current to flow through capacitance neutralization transistors M3and M4achieves gain reduction for amplifier51while potentially canceling out multiplicative large signal noise such as bias noise without altering the frequency response between the high and low gain modes. The sizing of gain adjustment transistor Madj can be fixed or variable (see, e.g.,FIG.5).

The examples ofFIGS.4and6in which at least one gain adjustment switch is coupled to the source terminals of the capacitance neutralization transistors are merely illustrative.FIG.7illustrates another embodiment of amplifier51having cascode transistors and a gain adjustment switch coupled to the source terminals of the cascode transistors Mcas1and Mcas2. As shown inFIG.7, radio-frequency amplifier51may include input transistors M1and M2, cascode transistors Mcas1and Mcas2, and gain adjustment transistor Madj′. Transistors M1and M2may be n-type (n-channel) transistors such as NMOS devices. Transistor M1may have a source terminal coupled to ground power supply line80, a drain terminal, and a gate terminal coupled to a positive input terminal In+. Transistor M2may have a source terminal coupled to ground power supply line80, a drain terminal, and a gate terminal coupled to a negative input terminal In−.

Transistor Mcas1may have a source terminal coupled to the drain terminal of input transistor M1, a gate terminal configured to receive a cascode bias voltage Vcas_bias, and a drain terminal coupled to negative output terminal Out−. Transistor Mcas2may have a source terminal coupled to the drain terminal of input transistor M2, a gate terminal configured to receive cascode bias voltage Vcas_bias, and a drain terminal coupled to positive output terminal Out+. Bias voltage Vcas_bias may have some intermediate voltage level between ground voltage level Vss and a positive power supply voltage Vdd. If desired, voltage Vcas_bias may also be equal to positive power supply voltage Vdd.

Transistors M3and M4interposed between the drain terminals of the input transistors and the differential output port in this way are sometimes referred to collectively as cascode transistors. A cascode transistor (stage) can be defined as an amplifier stage with an amplifying transistor that has its gate terminal coupled to a common (fixed) voltage source (e.g., Vcas_bias). The cascode transistor stage with Mcas1and Mcas2may enable the use of higher supply voltages (since the high voltage stress at high output power is distributed between the cascode transistors and the input transistors), increase the output impedance of radio-frequency amplifier51, reduce the transformation loss in the output matching network, improve the overall efficiency of amplifier51. In general, amplifier51can include other load components coupled to the input or output terminals of amplifier51.

Gain adjustment switch Madj′ may be a p-type (p-channel) transistor such as a p-type metal-oxide-semiconductor (PMOS) device having a first source-drain terminal coupled to the source terminal of cascode transistor Mcas1, a second source-drain terminal coupled to the source terminal of cascode transistor Mcas2, and a gate terminal configured to receive control voltage Vcon. Control voltage Vcon may be generated using one or more processor(s) in the electronic device (see, e.g., processor88described in connection withFIG.4). Gain adjustment transistor Madj′ may be deactivated (turned off) in the high gain mode by deasserted (driven high) signal Vcon. Since the source terminals of the cascode transistors are low impedance nodes, the parasitic capacitance of PMOS transistor Madj′ has a minor impact on the signal transfer function in the high gain mode.

Control voltage Vcon may be asserted (driven low) to activate transistor Madj′ in the low gain mode. Turning on transistor Madj′ steers or diverts some of the current that otherwise would have flowed from the input transistors to the output terminals but instead through transistor Madj′. Diverting a fraction of the current away from the output terminals effectively decreases the gain of amplifier51and decreases its output power. Operated in this way, the input transistors M1and M2continues to operate at a high current density even during the low gain mode(s) and thus maintains the same noise characteristics as the high gain mode. P-type gain adjustment switch Madj′ can have a fixed size or variable sizing (see, e.g., adjustable-sizing transistor of the type shown inFIG.5).

The example ofFIG.7in which amplifier51has a p-type gain adjustment transistor coupled to the source terminals of the cascode transistors is merely illustrative. The embodiment ofFIG.7is not mutually exclusive with the embodiments ofFIGS.4and6and can thus be combined with the embodiments ofFIGS.4and6.FIG.8shows an example of radio-frequency amplifier51that combines the embodiment ofFIG.4and the embodiment ofFIG.7. As shown inFIG.8, input transistors M1and M2may be coupled to cascode transistors Mcas1and Mcas2and cross-coupled with capacitance neutralization transistors M3and M4. P-type gain adjustment transistor Madj′ may be coupled across the source terminals of the cascode transistors. N-type gain adjustment transistors Madj1and Madj2may be coupled (shunted) in parallel with source resistors Rbig1and Rbig2, respectively.

In the example ofFIG.8, n-type gain adjustment transistors Madj1and Madj2have gate terminals configured to receive a first control voltage Vcon1from processor88, whereas p-type gain adjustment transistor Madj′ has a gate terminal configured to receive a second control voltage Vcon2from processor88. Processor(s)88may, for example, represent one or more microprocessors, microcontrollers, digital signal processors, host processors, baseband processors, application processors, application specific integrated circuits, central processing units (CPUs), general purpose processors, and/or other types of processors. Processor88may sometimes be considered part of processor circuitry18shown inFIG.1, processor26of the type shown inFIG.2, or other types of processors.

Processor88may control voltages Vcon1and Vcon2in tandem or separately. For example, processor88may simultaneously assert voltages Vcon1and Vcon2(e.g., by driving Vcon1high and driving Vcon2low) when operating amplifier51in the lowest gain mode. As another example, processor88may assert only voltage Vcon1while deasserting voltage Vcon2. As another example, processor88may assert only voltage Vcon2while deasserting voltage Vcon1. Processor may deassert both voltages Vcon1and Vcon2(e.g., by driving Vcon1low and driving Vcon2high) when operating amplifier51in the high (maximum) gain mode.

The methods and operations described above in connection withFIGS.1-8may be performed by the components of device10using software, firmware, and/or hardware (e.g., dedicated circuitry or hardware). Software code for performing these operations may be stored on non-transitory computer readable storage media (e.g., tangible computer readable storage media) stored on one or more of the components of device10(e.g., storage circuitry16and/or wireless communications circuitry24ofFIG.1). The software code may sometimes be referred to as software, data, instructions, program instructions, or code. The non-transitory computer readable storage media may include drives, non-volatile memory such as non-volatile random-access memory (NVRAM), removable flash drives or other removable media, other types of random-access memory, etc. Software stored on the non-transitory computer readable storage media may be executed by processing circuitry on one or more of the components of device10(e.g., processing circuitry in wireless circuitry24, processing circuitry18ofFIG.1, etc.). The processing circuitry may include microprocessors, application processors, digital signal processors, central processing units (CPUs), application-specific integrated circuits with processing circuitry, or other processing circuitry.

The foregoing is merely illustrative and various modifications can be made to the described embodiments. The foregoing embodiments may be implemented individually or in any combination.