Patent ID: 12260810

DETAILED DESCRIPTION OF ILLUSTRATED EMBODIMENTS

The following description of the embodiments refers to the accompanying drawings to illustrate specific embodiments in which the present disclosure may be implemented. Directional terms, such as upper, lower, front, back, left, right, inner, outer, side, etc., mentioned in the present disclosure only refer to directions of the accompanying drawings. Therefore, the directional terms used are to illustrate and understand the present disclosure, but not to limit the present disclosure. In the drawings, units with similar structures are represented by the same numerals.

The present disclosure will be further described below with reference to the accompanying drawings and specific embodiments.

An embodiment of the present disclosure provides a pixel driving circuit that can prevent a threshold voltage from drifting significantly due to long-term voltage application, thereby solving a problem of poor display caused by the drifting of the threshold voltage.

As shown inFIG.1, which is a schematic structural diagram of a pixel driving circuit of an embodiment of the present disclosure. The pixel driving circuit includes a writing module10, a driving transistor TO, and a light-emitting element11. The writing module10is electrically connected to a data signal terminal Data, and is also electrically connected to a first node A and a second node B. The writing module10is configured to connect the data signal terminal Data to the first node A and the second node B, or to disconnect the data signal terminal Data from the first node A or the second node B.

For example, the writing module10can connect the data signal terminal Data and the first node A under a control of a scan signal, so as to transmit a data signal output by the data signal terminal Data to the first node A through the data writing module10. The writing module10can also disconnect the data signal terminal Data from the first node A under the control of the scan signal. At this time, the first node A cannot receive the data signal output by the data signal terminal Data. The writing module10can selectively connect the data signal terminal Data to one of the first node A and the second node B under the control of the scan signal, and disconnect the connection between the data signal terminal Data and the other one of the first node A and the second node B under the control of the scan signal. The writing module10can also disconnect the connection between the data signal terminal Data and the first node A and the connection between the data signal terminal Data and the second node B at the same time under the control of the scan signal. Alternatively, the writing module10can also connect the data signal terminal Data to the first node A and the second node B simultaneously under the control of the scan signal.

The driving transistor T0is a double-gate transistor. A first gate G1of the driving transistor T0is electrically connected to the first node A. A second gate G2of the driving transistor T0is electrically connected to the second node B. A source of driving transistor T0is electrically connected to a first power signal terminal VDD. A drain of driving transistor T0is electrically connected to a third node S. The driving transistor T0is configured to connect the first power signal terminal VDD and the third node S, or to disconnect the first power signal terminal VDD from the third node S. For example, the driving transistor T0can connect the first power signal terminal VDD and the third node S under the control of the data signal, so that a first power signal output by the first power signal terminal VDD is transmitted to the third node S through the driving transistor T0. The driving transistor T0can also disconnect the first power signal terminal VDD from the third node S under the control of the data signal.

In some embodiments of the present disclosure, the driving transistor T0is a metal oxide semiconductor thin film transistor. A material of a semiconductor layer of the driving transistor can be selected from any one of Indium Gallium Zinc Oxide (IGZO), Indium Zinc Oxide (IZO), Indium Gallium Zinc Tin Oxide (IGZTO), etc. A film layer structure of the driving transistor T0can refer to a film layer structure of the transistor of the existing display panel, and is not limited herewith.

The light-emitting element11is electrically connected to a second power signal terminal VSS and electrically connected to the third node S. When a circuit between the first power signal terminal VDD and the second power signal terminal VSS is turned on, the light-emitting element11emits light.

In some embodiments of the present disclosure, the light-emitting element11is a micro light-emitting diode (Mirco LED) chip. A size of the Micro LED chip is less than 100 micrometers. In practical applications, a type of the light-emitting element11is not limited to the Micro LED chip as the above embodiment, but can also be a mini light-emitting diode (Mini LED) or an organic light-emitting diode (OLED).

As shown inFIG.1, in any one frame period, one of the first gate G1and the second gate G2is controlled by the data signal to turn on the driving transistor T0. In a plurality of frame periods, the first gate G1and the second gate G2are alternately controlled by the data signal to turn on the driving transistor T0. For example, the driving transistor T0can be turned on alternately through the first gate G1and the second gate G2every N frames. The number of N can be 10, 30, 50, 70 or 100, etc., there is no limit here. Under this structure, the first gate G1and the second gate G2are alternately controlled to turn on the driving transistor T0. This can prevent long-term voltage application to the same gate from causing some negative electrons in a channel layer to be captured into an interface between the channel layer and a gate insulating layer or directly into the gate insulating layer under the action of a gate voltage. Therefore, it is possible to prevent a threshold voltage of the driving transistor from significantly drifting due to long-term pressurization, thereby solving the problem of poor display caused by the drifting of the threshold voltage.

In some embodiments of the present disclosure, the writing module10includes a first transistor T1and a second transistor T2. A gate of the first transistor T1is electrically connected to a first scan signal terminal WR1. A source of the first transistor T1is electrically connected to the data signal terminal Data. A drain of the first transistor T1is electrically connected to the first node A. A first scan signal output by the first scan signal terminal WR1can control the turning on and off of the first transistor T1. A gate of the second transistor T2is electrically connected to a second scan signal terminal WR2. A source of the second transistor T2is electrically connected to the data signal terminal Data. A drain of the second transistor T2is electrically connected to the second node B. A second scan signal output by the second scan signal terminal WR2can control the turning on and off of the second transistor T2.

In some embodiments of the present disclosure, a driving time sequence of the pixel driving circuit includes a data writing stage and a data clearing stage. The driving time sequence of the driving circuit includes a first driving time sequence and a second driving time sequence. Both the first driving time sequence and the second driving time sequence have a complete one frame period.

As shown inFIG.1, in the data writing stage of the first driving time sequence, the first scan signal is at a high potential and the second scan signal is at a low potential. The first transistor T1is turned on by the first scan signal. The second transistor T2is turned off under the control of the second scan signal. The first transistor T1outputs the data signal to the first node A, and the data signal is at the high potential. The first gate G1is controlled by the data signal to turn on the driving transistor T0, so that the driving transistor T0is in an on-state in the data writing stage of the first driving time sequence, thereby charging the first gate G1, that is, the first node A. In the data clearing stage of the first driving time sequence, the first scan signal is at the low potential and the second scan signal is at the high potential. The first transistor T1is turned off under the control of the first scan signal. The second transistor T2is turned on by the second scan signal. The second transistor T2outputs the data signal to the second node B, and the data signal is at the low potential. The second gate G2is controlled by the data signal to turn off the driving transistor T0, so that the driving transistor is in an off-state in the data clearing stage of the first driving time sequence, thereby clearing the voltage at the second gate G2, that is, the second node B.

In the data writing stage of the second driving time sequence, the first scan signal is at the low potential and the second scan signal is at the high potential. The first transistor T1is turned off under the control of the first scan signal. The second transistor T2is turned on by the second scan signal. The second transistor T2outputs the data signal to the second node B, and the data signal is at the high potential. The second gate G2is controlled by the data signal to turn on the driving transistor T0to charge the second gate G2, that is, the second node B. In the data clearing stage of the second driving time sequence, the first scan signal is at the high potential and the second scan signal is at the low potential. The first transistor T1is turned on by the first scan signal. The second transistor T2is turned off under the control of the second scan signal. The first transistor T1outputs the data signal to the first node A, and the data signal is at the low potential. The first gate G1is controlled by the data signal to turn off the driving transistor T0, so that the driving transistor is in the off-state in the data clearing stage of the second driving time sequence, thus clearing the voltage at the first gate G1, that is, the first node A.

In some embodiments of the present disclosure, in any one frame period, the pixel driving circuit is driven by one of the first driving time sequence and the second driving time sequence. In a plurality of frame periods, the pixel driving circuit is alternately driven by the first driving time sequence and the second driving time sequence. This can prevent the threshold voltage of the driving transistor from drifting significantly due to long-term pressurization, thereby solving the problem of poor display caused by the drifting of the threshold voltage.

In some embodiments of the present disclosure, the pixel driving circuit further includes a storage module12. The storage module12is electrically connected to the first node A, the second node B, and the third node S. The storage module12is configured to store and maintain the threshold voltage of the driving transistor10.

In one embodiment, as shown inFIG.1, the storage module12includes a first storage capacitor Cst1and a second storage capacitor Cst2. A first electrode of the first storage capacitor Cst1is electrically connected to the first node A. A second electrode of the first storage capacitor Cst1is electrically connected to the third node S. A first electrode of the second storage capacitor Cst2is electrically connected to the second node B. A second electrode of the second storage capacitor Cst2is electrically connected to the third node S.

The driving time sequence of the pixel driving circuit also includes a threshold voltage acquisition and storage stage and a light-emitting stage. In the threshold voltage acquisition and storage stage of the first driving time sequence, the first storage capacitor Cst1is configured to store the threshold voltage of the driving transistor T0. Also, in the light-emitting stage of the first driving time sequence, the first storage capacitor Cst1is configured to maintain a voltage difference between the first node A and the third node S, so that the driving transistor T0keeps in the on-state, so that the light-emitting element11emits light. In the threshold voltage acquisition and storage stage of the second driving time sequence, the second storage capacitor Cst2is configured to store the threshold voltage of the driving transistor T0. Also, in the light-emitting stage of the second driving time sequence, the second storage capacitor Cst2is configured to maintain a voltage difference between the second node B and the third node S, so that the driving transistor T0keeps in the on-state, so that the light-emitting element11emits light.

As shown inFIG.1, the pixel driving circuit also includes a reset module13. The reset module13includes a first capacitor C1and a third transistor T3. A first electrode of the first capacitor C1is electrically connected to the first power signal terminal VDD. A second electrode of the first capacitor C1is electrically connected to the third node S. A gate of the third transistor T3is electrically connected to a third scan signal terminal RD. A source of the third transistor T3is electrically connected to a sensing signal terminal Vneg. A drain of the third transistor T3is electrically connected to the third node S.

The driving time sequence of the pixel driving circuit also includes an initialization stage. In the initialization stage, a third scan signal output by the third scan signal terminal RD is at the high potential. The third transistor T3is turned on by the third scan signal. A voltage of the third node S is the same as a voltage of the sensing signal terminal Vneg.

As shown inFIG.1, the pixel driving circuit also includes a light-emitting control module14. The light-emitting control module14includes a fourth transistor T4. A gate of the fourth transistor T4is electrically connected to a fourth scan signal terminal EM. A source of the fourth transistor T4is electrically connected to the first power signal terminal VDD. A drain of the fourth transistor T4is electrically connected to the source of the driving transistor T0. By setting the light-emitting control module14between the driving transistor T0and the first power signal terminal VDD, the driving transistor T0can be prevented from being accidentally turned on during the data writing stage to output the first power signal to the third node S to cause the light-emitting element11to emit light.

In the threshold voltage acquisition and storage stage, the third scan signal output by the third scan signal terminal RD is at the low potential. The third transistor T3is turned off under the control of the third scan signal, and the driving transistor T0is turned off. The fourth scan signal output by the fourth scan signal terminal EM is at the high potential. The fourth transistor T4is turned on by the fourth scan signal. The third node S is charged until its voltage is equal to a voltage difference between the first node or the second node and the threshold voltage of the driving transistor T0, thereby realizing the acquisition and storage of the threshold voltage of the driving transistor T0.

In some embodiments of the present disclosure, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4are all N-type low-temperature polysilicon thin film transistors.

According to the pixel driving circuit provided in the above embodiments of the present disclosure, embodiments of the present disclosure also provide a driving method of the pixel driving circuit. The driving method is adapted to be configured as the pixel driving circuit provided in any of the above embodiments. As shown inFIG.2, a driving time sequence of the driving method includes an initialization stage t1, a threshold voltage acquisition and storage stage t2, a data writing stage t3, a data clearing stage t4, and a light-emitting stage t5. In the initialization stage t1, the first node A, the second node B, and the third node S are reset. In the threshold voltage acquisition and storage stage t2, the third node S is charged until the voltage difference between the first node A or the second node B and the third node S is equal to the threshold voltage of the driving transistor T0. In the data writing stage t3, the writing module10outputs the data signal to one of the first node A and the second node B. One of the first gate G1and the second gate G2is controlled by the data signal to turn on the driving transistor T0. In the data clearing stage t4, the writing module10outputs the data signal to the other one of the first node A and the second node B. The other one of the first gate G1and the second gate G2is controlled by the data signal to turn off the driving transistor T0. In the light-emitting stage t5, the light-emitting element11emits light.

In any one frame period, one of the first gate G1and the second gate G2is controlled by the data signal to turn on the driving transistor T0. In a plurality of frame periods, the first gate G1and the second gate G2are alternately controlled by the data signal to turn on the driving transistor T0.

In the embodiment of the present disclosure, the driving time sequence of the driving method includes the first driving time sequence and the second driving time sequence. In the data writing stage t3of the first driving time sequence, the writing module10connects the data signal terminal Data and the first node A. The data signal terminal Data outputs the data signal to the first node A. The data signal is at the high potential. The first gate G1is controlled by the data signal to turn on the driving transistor T0. The writing module10disconnects the data signal terminal Data from the second node B. In the data clearing stage t4of the first driving time sequence, the writing module10connects the data signal terminal Data and the second node B. The data signal terminal Data outputs the data signal to the second node B. The data signal is at the low potential. The second gate G2is controlled by the data signal to turn off the driving transistor T0. The writing module10disconnects the data signal terminal Data from the first node A. In the data writing stage t3of the second driving time sequence, the writing module10connects the data signal terminal Data and the second node B. The data signal terminal Data outputs the data signal to the second node B. The data signal is at the high potential. The second gate G2is controlled by the data signal to turn on the driving transistor T0. The writing module10disconnects the data signal terminal Data from the first node A. In the data clearing stage t4of the second driving time sequence, the writing module10connects the data signal terminal Data and the first node A. The data signal terminal Data outputs the data signal to the first node A. The data signal is at the low potential. The first gate G1is controlled by the data signal to turn off the driving transistor T0. The writing module10disconnects the data signal terminal Data from the second node B.

In some embodiments of the present disclosure, in any one frame period, one of the first driving time sequence and the second driving time sequence is used to drive the pixel driving circuit. In a plurality of frame periods, the first driving time sequence and the second driving time sequence are alternately used to drive the pixel driving circuit. This can prevent the threshold voltage from drifting significantly due to long-term voltage application, thereby solving the problem of poor display caused by the drifting of the threshold voltage.

In some embodiments of the present disclosure, the first driving time sequence and the second driving time sequence are alternated every 100 frames. For example, in frames 1 to 100, the pixel driving circuit is driven in the first driving time sequence. In frames 101 to 200, the pixel circuit is driven in the second driving time sequence. In frames 201 to 300, the pixel driving circuit is driven in the first driving time sequence. In frames 301 to 400, the pixel driving circuit is driven in the second driving time sequence. The following analogy will not be repeated. In practical applications, the first driving time sequence and the second driving time sequence can be alternated every 1 frame, 10 frames, 20 frames, or more than 20 frames, which is not limited here.

Taking the first driving time sequence as an example, refer toFIG.2toFIG.7.FIG.2is a driving timing diagram of a first driving time sequence of the pixel driving circuit of an embodiment of the present disclosure, and the details are as follows:

Referring toFIG.2andFIG.3,FIG.3is a schematic diagram showing turning on and off on each transistor in an initialization stage of the first driving time sequence of the pixel driving circuit of an embodiment of the present disclosure. In the initialization stage t1, the first scan signal, the second scan signal, the data signal, and the fourth scan signal are all at the low potential. The third scan signal is at the high potential. The driving transistor T0, the first transistor T1, the second transistor T2, and the fourth transistor T4are all turned off. The third transistor T3is turned on. A potential VG1of the first gate and a potential VG2of the second gate are both equal to a precharge potential Vpre, that is, VG1=VG2=Vpre. A potential Vsof the third node S is equal to a potential Vnegof the sensing signal of the sensing signal terminal, that is, Vs=Vneg. Through the initialization stage, the potentials at the first gate G1(i.e., the first node A), the second gate G2(i.e., the second node B), and third node S can be cleared.

Referring toFIG.2andFIG.4,FIG.4is a schematic diagram showing turning on and off on each transistor in a threshold voltage acquisition and storage stage of the first driving time sequence of the pixel driving circuit of an embodiment of the present disclosure. In threshold voltage acquisition and storage stage t2, the first scan signal, the second scan signal, the data signal, and the third scan signal are all at the low potential. The fourth scan signal is at the high potential. The driving transistor T0, the first transistor T1, the second transistor T2, and the third transistor T3are all turned off. The fourth transistor T4is turned on. The potential Vsof the third node S is charged until the voltage difference between the first node A or the second node B and the third node S is equal to the threshold voltage Vthof the driving transistor T0, that is, Vs=Vpre-Vth. The potential VG1of the first gate and the potential VG2of the second gate are still equal to the precharge potential Vpre, that is, VG1=VG2=Vpre. Through the threshold voltage acquisition and storage stage t2, the threshold voltage Vthof the driving transistor T0can be read and stored.

Referring toFIG.2andFIG.5,FIG.5is a schematic diagram showing turning on and off on each transistor in a data writing stage of the first driving time sequence of the pixel driving circuit of an embodiment of the present disclosure. In the data writing stage t3, the first scan signal is at the high potential and the data signal is at the high potential. The first transistor T1is turned on. The potential VG1of the first gate G1is the same as the potential Vdataof the data signal, that is, VG1=Vdata, so that the driving transistor T0can be turned on. A capacitive coupling of the first storage capacitor Cst1increases the potential Vsof the third node S, that is, Vs=(Vpre−Vth)+ (Vdata−Vpre)*Cst1/(C1+Cst1+Cst2). The voltage between the first gate G1and the third node S is Vg1s(Vdata−Vpre)*(Cst2+C1)/(C1+Cst1+Cst2)+Vth. Through the data writing stage t3, the target voltage required by the light-emitting element11can be set.

Referring toFIG.2andFIG.6,FIG.6is a schematic diagram showing turning on and off on each transistor in a data clearing stage of the first driving time sequence of the pixel driving circuit of an embodiment of the present disclosure. In the data clearing stage t4, the second scan signal is at the high potential. The data signal, the first scan signal, the third scan signal, and the fourth scan signal are all at the low potential. The second transistor T2is turned on. Since the data signal is at the low potential, the driving transistor T0cannot be turned on. Due to the capacitive coupling of the second storage capacitor Cst2in the data writing stage t3, in the data clearing stage t4, the voltage between the second gate G2and the third node S is Vg2s=(Vdata−Vpre)*(Cst2+C1)/(C1+Cst1+Cst2)+Vth. Through the data clearing stage t4, the potential at the second gate G2can be cleared.

Referring toFIG.2andFIG.7,FIG.7is a schematic diagram showing turning on and off on each transistor in a light-emitting stage of the first driving time sequence of the pixel driving circuit of an embodiment of the present disclosure. In the light-emitting stage t5, the first scan signal, the second scan signal, the data signal, and the third scan signal are all at the low potential. The fourth scan signal is at the high potential. The first transistor T1, the second transistor T2, and the third transistor T3are all turned off. The fourth transistor T4is turned on. The first storage capacitor Cst1maintains the voltage difference between the first gate G1and the third node S, causing the driving transistor T0to turn on. The potential at the third node S is Vs=Vled+VSS, where Vied is a potential of an anode of the light-emitting element11. The potential at the first gate G1is VG1=Vdata+Vled+VSS−(Vpre−Vth)−(Vdata−Vpre)*Cst1/(C1+Cst1+Cst2). The voltage difference between a voltage between the first gate G1and the third node S and the threshold voltage Vthis: Vg1s−Vth=Vdata−Vpre−(Vdata−Vpre)*Cst1/(C1+Cst1+Cst2).

It should be noted that the above embodiment only takes the first driving time sequence as an example. The second driving time sequence can refer to the first driving time sequence to drive the pixel driving circuit, which will not be described again here.

The pixel driving circuit provided in the above embodiments is provided according to the present disclosure. An embodiment of the present disclosure also provides a display panel. The display device includes the pixel driving circuit provided in any of the above embodiments. The display panel can be applied to, but is not limited to, display devices such as smartphones, smart watches, desktop computers, laptops, and televisions.

Advantages of the embodiments of the present disclosure are as follows. The embodiments of the present disclosure provide the pixel driving circuit, the driving method for the pixel driving circuit, and the display panel. The pixel driving circuit includes the writing module, the driving transistor, and the light-emitting element. The writing module is electrically connected to the data signal terminal, and is electrically connected to the first node and the second node. The writing module is configured to transmit the data signal output by the data signal terminal to the first node and the second node. The driving transistor is the double-gate transistor. The first gate of the driving transistor is electrically connected to the first node. The second gate of the driving transistor is electrically connected to the second node. The source of the driving transistor is electrically connected to the first power signal terminal. The drain of the driving transistor is electrically connected to the third node. The driving transistor is configured to transmit the first power signal output from the first power signal terminal to the third node. The light-emitting element is electrically connected to the second power signal terminal and electrically connected to the third node. In any one frame period, one of the first gate and the second gate is controlled by the data signal to turn on the driving transistor. Moreover, in the plurality of frame periods, the first gate and the second gate are alternately controlled by the data signal to turn on the driving transistor. It can prevent long-term voltage application to the same gate from causing some negative electrons in a channel layer to be captured into an interface between the channel layer and a gate insulating layer or directly into the gate insulating layer under the action of a gate voltage. Therefore, it can prevent the threshold voltage from drifting significantly due to long-term voltage application, thereby solving the problem of poor display caused by the drifting of the threshold voltage.

In summary, although the present disclosure is disclosed as above in preferred embodiments, the above preferred embodiments are not intended to limit the present disclosure. Those of ordinary skill in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure is based on the scope defined by the claims.