Patent ID: 12243970

DETAILED DESCRIPTION

In order to make objectives, technical details and advantages of the embodiments of the present disclosure more clearly, the technical solutions of the embodiments will be described in a clearly and fully understandable way in connection with the drawings related to the embodiments of the present disclosure. Apparently, the described embodiments are just a part but not all of the embodiments of the present disclosure. Based on the described embodiments herein, those skilled in the art can obtain other embodiment(s), without any inventive work, which should be within the scope of the present disclosure.

Unless otherwise defined, all the technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms “first,” “second,” etc., which are used in the present disclosure, are not intended to indicate any sequence, amount or importance, but distinguish various components. Also, the terms “comprise,” “comprising,” “include,” “including,” etc., are intended to specify that the elements or the objects stated before these terms encompass the elements or the objects and equivalents thereof listed after these terms, but do not preclude the other elements or objects.

Generally, by reducing the pixels per inch (PPI) of four corner regions of a display substrate and setting a stretchable structure with opening patterns in these four corner regions, the edges or corners of the display substrate can be bent according to a certain bending radius, thus realizing the four curved surface screen design. At this time, the greater the stretching amount of the stretchable structure located in the four corner regions, the lower the PPI of these four corner regions, which is a low PPI region. On the other hand, because these four corner regions are provided with opening patterns, these opening patterns divide the pixel array into isolated pixel islands; the driving lines (such as gate lines, data lines, etc.) of pixels in these pixel islands need to be connected with each other, but these driving lines cannot directly cross these opening patterns, so the control lines and data lines of pixel units need to be routed bypass the opening patterns.

In this regard, embodiments of the present disclosure provide a display substrate and a display device. The display substrate includes: a plurality of pixel islands, a first opening, a second opening and a first passage region. The plurality of pixel islands are arranged in an array in a first direction and a second direction; the first opening is located between two pixel islands adjacent in the second direction; the second opening is located between two pixel islands adjacent in the first direction; the first passage region is at least partially located between the first opening and the second opening and connects two pixel islands adjacent in the first direction; each of the plurality of pixel islands overlaps with the first opening in the first direction, each of the plurality of pixel islands includes at least one pixel, each pixel includes a plurality of first driving lines extending in the first direction, the first passage region is provided with a plurality of first connection lines, each of the plurality of pixel islands further includes a plurality of transfer lines extending in the second direction, and the plurality of transfer lines are arranged in different layers from the plurality of first driving lines and cross each other to form a plurality of overlapping regions; the plurality of transfer lines are electrically connected with the plurality of first driving lines through via holes located in part of the overlapping regions, and the transfer lines in two pixel islands adjacent in the first direction are respectively connected with the plurality of first connection lines in the first passage region. The display substrate leads out the plurality of first driving lines in each of the plurality of pixel islands through the plurality of transfer lines, and respectively connects a plurality of first driving lines of two pixel islands adjacent in the first direction through a plurality of first connection lines in the first passage region, thereby realizing the connection of the plurality of first driving lines of two pixel islands adjacent in the first direction. Therefore, the display substrate can realize the wiring of the driving lines in the stretchable region or the bending region with opening patterns.

Hereinafter, the display substrate and the display device provided by the embodiments of the present disclosure will be described in detail with reference to the drawings.

An embodiment of the present disclosure provides a display substrate.FIG.1is a schematic plan view of a display substrate according to an embodiment of the present disclosure. As illustrated inFIG.1, the display substrate100includes a plurality of pixel islands110, a first opening121, a second opening122and a first passage region130. The plurality of pixel islands110are arranged in an array in a first direction and a second direction. The distance between pixel islands110is large, for example, the distance between adjacent pixel islands110is greater than the distance between adjacent pixels140in pixel islands110. The first opening121is located between two pixel islands110adjacent in the second direction; the second opening122is located between two pixel islands110adjacent in the first direction; the first passage region130is at least partially located between the first opening121and the second opening122and connects two pixel islands110adjacent in the first direction. Each of the plurality of pixel islands110overlaps with the first opening121in the first direction, that is, an orthographic projection of the pixel island on a reference line extending in the first direction overlaps with an orthographic projection of the first opening on the reference line.

Each of the plurality of pixel islands110includes at least one pixel140, each pixel140includes a plurality of first driving lines142extending in the first direction, the first passage region130is provided with a plurality of first connection lines132, and each of the plurality of pixel islands110further includes a plurality of transfer lines112extending in the second direction, the plurality of transfer lines are arranged in different layers from the plurality of first driving lines142and cross each other to form a plurality of overlapping regions150. The plurality of transfer lines112are electrically connected with the plurality of first driving lines142through the via holes152located in part of the overlapping region150, and the transfer lines112in two pixel islands110adjacent in the first direction are respectively connected with the plurality of first connection lines132in the first passage region130. It should be noted that in the display substrate, the first driving line can be a gate line, which is located in one of a first gate layer and a second gate layer; at this time, the above-mentioned transfer line can be located in other conductive layers, such as the other of the first gate layer and the second gate layer, a first source-drain metal layer, a second source-drain metal layer, or a light shielding layer. In addition, the above-mentioned via holes have different depths according to the difference of the plurality of first driving lines and the plurality of transfer lines connected by the via holes, and adjacent via holes are arranged in a staggered way to avoid mutual interference. In the display substrate provided by the embodiment of the present disclosure, in each of the plurality of pixel islands110, the plurality of first driving lines142of each pixel140can be led out through the transfer lines112, and then the transfer lines112of two pixel islands110adjacent in the first direction are respectively connected with the plurality of first connection lines132in the first passage region130, thereby connecting the plurality of first driving lines142of two pixel islands110adjacent in the first direction. Therefore, the display substrate can realize the wiring of the driving lines in the stretchable region or the bending region with opening patterns. In addition, by fully utilizing the first passage region between the first opening and the second opening, the display substrate can ensure that the first opening and the second opening have larger sizes, thereby improving the stretching or bending performance of the display substrate.

In some examples, as illustrated inFIG.1, each of the plurality of pixel islands110includes two sub-regions114and a transfer region116located between the two sub-regions114, the at least one pixel140included in the pixel island110is arranged in the two sub-regions114, and the transfer lines112are located in the transfer region116. Therefore, the display substrate places the above-mentioned transfer lines112by setting the transfer region116in the pixel island110, and setting the transfer region116between the two sub-regions114, so that the distribution symmetry of the pixels140in the pixel island110can be improved.

In some examples, as illustrated inFIG.1, a plurality of first driving lines142pass through the two sub-regions114and the transfer region116, and the plurality of first driving lines142are configured to drive the at least one pixel140in the two sub-regions114for light-emitting display. It should be noted that one of the two sub-regions can be a dummy region, that is, a region that is not for displaying.

For example, the above-mentioned first driving lines142can include driving lines extending in the first direction, such as gate lines, light-emitting control lines, and initialization lines.

In some examples, as illustrated inFIG.1, the first openings121extend in the first direction and the second openings122extend in the second direction. The first openings121and the second openings122are alternately arranged in the first direction and also alternately arranged in the second direction. Therefore, in the region where the first openings and the second openings are located, the display substrate can be better bent or folded, which is convenient to realize the design of the four curved surface screen.

In some examples, as illustrated inFIG.1, the first passage region130is located between the pixel island110and the first opening121, and between the first opening121and the end of the second opening122close to the first opening121. Therefore, the first passage region130can bypass the first opening121and the second opening122, and realize efficient use of the space on the display substrate.

In some examples, as illustrated inFIG.1, the first opening121overlaps with both of the two pixel islands110adjacent in the first direction. Therefore, the distribution area of the first opening is large, which is beneficial to the bending of the display substrate.

In some examples, as illustrated inFIG.1, an orthographic projection of the second opening122on the first opening121is located in the middle of the first opening121. Therefore, the distribution of the second opening and the first opening of the display substrate has high symmetry, so that the display substrate can be flexibly bent.

In some examples, as illustrated inFIG.1, each pixel140includes a plurality of sub-pixels160, and each sub-pixel160includes a pixel driving circuit162and an anode164electrically connected to the pixel driving circuit162.

FIG.2is a schematic plan view of a pixel in a display substrate according to an embodiment of the present disclosure.FIG.3is a schematic section view of a display substrate along the AA direction inFIG.2according to an embodiment of the present disclosure. As illustrated inFIGS.2and3, the display substrate100includes a base substrate101, a semiconductor layer102, a gate insulating layer103, a first gate layer104, an interlayer insulating layer105, a second gate layer106, a passivation layer107and a first conductive layer108. The semiconductor layer102is located on the base substrate101; the gate insulating layer103is located at the side of the semiconductor layer102away from the base substrate101. The first gate layer104is located at the side of the gate insulating layer103away from the semiconductor layer102. The interlayer insulating layer105is located at the side of the first gate layer104away from the gate insulating layer103. The second gate layer106is located at the side of the interlayer insulating layer105away from the first gate layer104. The passivation layer107is located at the side of the second gate layer106away from the interlayer insulating layer105. The first conductive layer108is located at the side of the passivation layer104away from the second gate layer106. The above-mentioned plurality of first driving lines142are located in at least one of the first gate layer104and the second gate layer106, and the above-mentioned transfer line112is located in the first conductive layer108. Therefore, by arranging the transfer line112on the first conductive layer108, on the one hand, the existing conductive layer in the display substrate can be utilized, and on the other hand, the transfer line112can be arranged in a different layer from the first driving line, which is convenient for forming the above-mentioned overlapping region150, thus enabling flexible connection.

In some examples, as illustrated inFIGS.2and3, the display substrate100further includes an insulating layer109and a second conductive layer1010. The insulating layer109is located at the side of the first conductive layer108away from the passivation layer107. The second conductive layer1010is located at the side of the insulating layer109away from the first conductive layer108. The second conductive layer1010includes a conductive grid118located on the pixel island110, and the conductive grid118is electrically connected with a plurality of power lines in the pixel island110.

FIGS.4A-4Dare schematic diagrams of a plurality of film layers of a pixel driving circuit in a display substrate according to an embodiment of the present disclosure;FIG.5is an equivalent schematic diagram of a pixel driving circuit in a display substrate according to an embodiment of the present disclosure. As illustrated inFIGS.4A and5, each pixel driving circuit162includes: a first semiconductor unit221, a second semiconductor unit222, a third semiconductor unit223, a fourth semiconductor unit224, a fifth semiconductor unit225, a sixth semiconductor unit226and a seventh semiconductor unit227located in the semiconductor layer102; a first electrode block241located in the first gate layer104; and a second electrode block261located in the second gate layer106. The first semiconductor unit221includes a first channel region221C and a first source region221S and a first drain region221D located at two sides of the first channel region221C. The second semiconductor unit222includes a second channel region222C and a second source region222S and a second drain region222D on two sides of the second channel region222C. The third semiconductor unit223includes a third channel region223C and a third source region223S and a third drain region223D on two sides of the third channel region223C. The fourth semiconductor unit224includes a fourth channel region224C and a fourth source region224S and a fourth drain region224D on two sides of the fourth channel region224C. The fifth semiconductor unit225includes a fifth channel region225C and a fifth source region225S and a fifth drain region225D on two sides of the fifth channel region225C. The sixth semiconductor unit226includes a sixth channel region226C and a sixth source region226S and a sixth drain region226D on two sides of the sixth channel region226C. The seventh semiconductor unit227includes a seventh channel region227C and a seventh source region227S and a seventh drain region227D on two sides of the seventh channel region227C.

As illustrated inFIGS.4A and5, the third source region223S, the first drain region221D and the fifth source region225S are connected to a first node N1, the sixth drain region226D is connected to the third drain region223D, and the first source region221S, the second drain region222D and the fourth drain region224D are connected to a second node N2, the fifth drain region225D is connected to the seventh drain region227D. The orthographic projection of the second electrode block261on the base substrate101at least partially overlaps with the orthographic projection of the first electrode block241on the base substrate101to form a storage capacitor Cst.

As illustrated inFIG.4B,FIG.4CandFIG.5, the plurality of first driving lines142include: an initialization signal line1421located in the second gate layer106; a reset signal line1422located in the first gate layer104; a gate line1423located in the first gate layer104; and a light-emitting control line1424located in the first gate layer104. The initialization signal line1421is connected with the seventh source region227S and the sixth source region226S, the reset signal line1422overlaps with the seventh channel region217C and the sixth channel region226C to form the seventh thin film transistor T7and the sixth thin film transistor T6with the seventh semiconductor unit227and the sixth semiconductor unit226, the gate line1423respectively overlaps with the third channel region223C and the second channel region222C to form the third thin film transistor T3and the second thin film transistor T2with the third semiconductor unit223and the second semiconductor unit222. The first electrode block241overlaps the first channel region221C to form a first thin film transistor T1with the first semiconductor unit221, and the light-emitting control line1424overlaps the fourth channel region224C and the fifth channel region225C to form a fourth thin film transistor T4and a fifth thin film transistor with the fourth semiconductor unit224and the fifth semiconductor unit225.

As illustrated inFIGS.4D and5, the display substrate100further includes a plurality of second driving lines148. The plurality of second driving lines148include: a plurality of power lines1481located in the first conductive layer108, and each power line1481is connected with the fourth source region224S in the pixel driving circuit162; and a plurality of data lines1482located in the first conductive layer108, and each data line1482is connected with the second source region222S in the pixel driving circuit162.

In some examples, as illustrated inFIG.1, the number of the plurality of transfer lines112is smaller than the number of the plurality of first driving lines142. Therefore, the number of the transfer lines112can be reduced, the area occupied by the plurality of transfer lines112can be reduced, and the PPI can be improved.

In some examples, as illustrated inFIG.1, each of the plurality of pixel islands110includes at least two pixels140arranged in the second direction, and at least two of the plurality of first driving lines142are connected to the same transfer line112. Therefore, the number of transfer lines112can be reduced, so that the area occupied by the plurality of transfer lines112can be reduced, the PPI can be improved, and the first opening and the second opening can be further ensured to have larger sizes, so that the stretching or bending performance of the display substrate can be further improved.

In some examples, as illustrated inFIG.1, each of the plurality of pixel islands110includes four pixels140arranged in a matrix. Each of the plurality of pixel islands110includes a first sub-region114A, a second sub-region114B and a transfer region116between the first sub-region114A and the second sub-region114B. The first sub-region114A includes a first pixel1401and a second pixel1402arranged in the second direction, and the second sub-region114B includes a third pixel1403and a fourth pixel1404. The initialization signal line1421of the first pixel1401and the initialization signal line1421of the third pixel1403are a first initialization signal line1421A, and the initialization signal line1421of the second pixel1402and the initialization signal line1421of the fourth pixel1404are a second initialization signal line1421B. The plurality of transfer lines112include a first transfer line, the first initialization signal line1421A of the first pixel1401and the third pixel1403are electrically connected to the first transfer line1121through a via hole152, and the second initialization signal line1421B of the second pixel1402and the fourth pixel1404are electrically connected to the first transfer line1121through the via hole152. Therefore, the display substrate can lead out the initialization signal lines of four pixels through only one transfer line, thereby reducing the number of transfer lines, reducing the area occupied by plurality of transfer lines and improving the PPI.

In some examples, as illustrated inFIG.1, the reset signal line1422of the first pixel1401and the reset signal line1422of the third pixel1403are a first reset signal line1422A, and the reset signal line1422of the second pixel1402and the reset signal line1422of the fourth pixel1404are a second reset signal line1422B. The plurality of transfer lines include a second transfer line1122and a third transfer line1123, the first reset signal line1422A of the first pixel1401and the third pixel1403are electrically connected to the second transfer line1122through the via hole152, and the second reset signal line1422B of the second pixel1402and the fourth pixel1404are electrically connected to the third transfer line1123through the via hole. Therefore, the display substrate can lead out the reset signal lines of four pixels only through two transfer lines, thereby further reducing the number of transfer lines, reducing the area occupied by the plurality of transfer lines and improving the PPI.

In some examples, as illustrated inFIG.1, the gate line1423of the first pixel1401and the gate line1423of the third pixel1403are a first gate line1423A, and the gate line1423of the second pixel1402and the gate line1423of the fourth pixel1404are a second gate line1423B. The plurality of transfer lines112include a fourth transfer line1124, the first gate line1423A of the first pixel1401and the third pixel1403are electrically connected to the third transfer line1123through the via hole152, and the second gate line1423B of the second pixel1402and the fourth pixel1404are electrically connected to the fourth transfer line1124through the via hole152. Therefore, the display substrate can lead out the gate lines of four pixels only by adding one transfer line, thereby further reducing the number of transfer lines, reducing the area occupied by the plurality of transfer lines and improving the PPI.

In some examples, as illustrated inFIG.1, the light-emitting control line1424of the first pixel1401and the light-emitting control line1424of the third pixel1403are a first light-emitting control line1424A, the light-emitting control line1424of the second pixel1402and the light-emitting control line1424of the fourth pixel1404are a second light-emitting control line1424B. The plurality of transfer lines112include a fifth transfer line1125and a sixth transfer line1126, the first light-emitting control line1424A of the first pixel1401and the third pixel1403are electrically connected to the fifth transfer line1125through the via hole152, and the second light-emitting control line1424B of the second pixel1402and the fourth pixel1404are electrically connected to the sixth transfer line1126through the via hole152. Therefore, the display substrate can lead out the light-emitting control lines of four pixels only by adding two transfer lines, thereby further reducing the number of transfer lines, reducing the area occupied by the plurality of transfer lines and improving the PPI.

FIG.6is a schematic plan view of another display substrate according to an embodiment of the present disclosure. As illustrated inFIG.6, the light-emitting control line1424of the first pixel1401and the light-emitting control line1424of the third pixel1403are first light-emitting control line1424A, the light-emitting control line1424of the second pixel1402and the light-emitting control line1424of the fourth pixel1404are a second light-emitting control line1424B. The plurality of transfer lines112include a fifth transfer line1125, the first light-emitting control line1424A of the first pixel1401and the third pixel1403are electrically connected to the fifth transfer line1125through the via hole152, and the second light-emitting control line1424B of the second pixel1402and the fourth pixel1404are electrically connected to the fifth transfer line1125through the via hole152. Therefore, the display substrate can lead out the light-emitting control lines of four pixels only by adding one transfer line, thereby further reducing the number of transfer lines, reducing the area occupied by the plurality of transfer lines and improving the PPI.

It should be noted that the embodiments illustrated inFIG.1andFIG.6only illustrate the case where one pixel island110includes four pixels140arranged in a matrix, but the embodiments of the present disclosure include but are not limited to this. The display substrate can connect different first driving lines with the same or time-sharing signals through a transfer line, thereby reducing the number of transfer lines.

In some examples, as illustrated inFIG.1, the plurality of first connection lines132are arranged in the first gate layer104and the second gate layer106. For example, the plurality of first connection lines132are alternately arranged in the first gate layer104and the second gate layer106. At this time, the distance between the orthographic projections of adjacent first connection lines132on the base substrate101can be set smaller, that is, the plurality of first connection lines can be set more densely, so that the width of the first passage region can be reduced or the number of first connection lines in the first passage region can be increased.

In some examples, as illustrated inFIG.1, the number of the plurality of transfer lines112is the same as the number of the plurality of first connection lines132, and the plurality of transfer lines112are arranged in one-to-one correspondence with the plurality of first connection lines132. Therefore, the display substrate can connect the transfer lines in two pixel islands adjacent in the first direction through the first connection lines, thereby connecting a plurality of first driving lines in two pixel islands adjacent in the first direction.

FIG.7is a schematic plan view of a display substrate according to an embodiment of the present disclosure. As illustrated inFIG.7, the display substrate100further includes: a second passage region170, located between the first opening121and the second opening122and connecting two pixel islands110adjacent in the second direction. Each of the plurality of pixel islands110includes a plurality of second driving lines148extending in the second direction, and the second passage region170is provided with a plurality of second connection lines172, the plurality of second connection lines172respectively connect the second driving lines148of two pixel islands110adjacent in the second direction.

In some examples, as illustrated inFIG.2,FIG.3andFIG.7, the plurality of second driving lines148include: a plurality of power lines1481, located in the first conductive layer108, each power line1481being connected with the fourth source region224S in the pixel driving circuit162; and a plurality of data lines1482, located in the first conductive layer108, and each data line1482being connected with the second source region222S in the pixel driving circuit162.

In some examples, as illustrated inFIGS.2,3and7, the display substrate100further includes an insulating layer109and a second conductive layer1010. The insulating layer109is located at the side of the first conductive layer108away from the passivation layer107. The second conductive layer1010is located at the side of the insulating layer109away from the first conductive layer108. The second conductive layer1010includes a conductive grid118located on the pixel island110, and the conductive grid118is electrically connected with the plurality of power lines1481in the pixel island110.

At this time, as illustrated inFIG.7, the plurality of second connection lines172include a power connection line1721, located in the second conductive layer1010and connected with the conductive grid118. Because the conductive grid118is electrically connected with the plurality of power lines1481in the pixel island110, the power lines1481of all pixels140in two pixel islands110adjacent in the second direction can be connected by only one second connection line172.

FIG.8is a schematic diagram of a second conductive layer in a display substrate according to an embodiment of the present disclosure. As illustrated inFIG.8, the power connection line1721is located in the second conductive layer1010and connected with the conductive grid118. Because the conductive grid118is electrically connected with the plurality of power lines1481in the pixel island110, the power lines1481of all pixels140in the two pixel islands110adjacent in the second direction can be connected by only one second connection line172.

In some examples, as illustrated inFIG.7, the plurality of second connection lines172further include a plurality of data connection lines1722, the plurality of data connection lines1722are arranged and connected with the plurality of data lines1482in one-to-one correspondence. Therefore, the display substrate can connect the data lines1482of all the pixels140in the two pixel islands110adjacent in the second direction through the plurality of data connection lines.

In some examples, as illustrated inFIG.7, the plurality of second connection lines172are arranged in the first conductive layer108and the second conductive layer1010. For example, the plurality of second connection lines172are alternately arranged in the first conductive layer108and the second conductive layer1010. At this time, the distance between the orthographic projections of adjacent second connection lines172on the base substrate101can be set smaller, that is, the plurality of second connection lines can be set more densely, so that the width of the second passage region can be reduced or the number of second connection lines in the second passage region can be increased.

In some examples, as illustrated inFIG.7, each pixel140includes a first color sub-pixel1601, a second color sub-pixel1602and a third color sub-pixel1603, each of the plurality of pixel islands110includes four pixels140arranged in a matrix, and each of the plurality of pixel islands140includes a first sub-region144A, a second sub-region144B and a transfer region146located between the first sub-region144A and the second sub-region144B. The first sub-region144A includes a first pixel1401and a second pixel1402arranged in the second direction, and the second sub-region144B includes a third pixel1403and a fourth pixel1404arranged in the second direction. The data line1482of the first color sub-pixel1601in the first pixel1401and the data line1482of the first color sub-pixel1401in the second pixel1402are a first data line1482A, the data line1482of the second color sub-pixel1602in the first pixel1401and the data line1482of the second color sub-pixel1602in the second pixel1402are a second data line1482B, the data line1482of the third color sub-pixel1603in the first pixel1401and the data line1482of the third color sub-pixel1603in the second pixel1402are a third data line1482C, and the data line1482of the first color sub-pixel1601in the third pixel1403and the data line1482of the first color sub-pixel1601in the fourth pixel1404are a fourth data line1482D, the data line1482of the second color sub-pixel1602in the third pixel1403and the data line1482of the second color sub-pixel1602in the fourth pixel1404are a fifth data line1482E, the data line1482of the third color sub-pixel1603in the third pixel1403and the data line1482of the third color sub-pixel1603in the fourth pixel1404are sixth data lines1482F. It should be noted that144A,144B,146,1401,1402,1403and1404are not illustrated inFIG.7for clarity. The division of the first sub-region144A, the second sub-region144B, the transfer region146, the first pixel1401, the second pixel1402, the third pixel1403and the fourth pixel1404can be seen inFIG.1.

As illustrated inFIGS.7and8, the plurality of second connection lines172include a first data connection line1722A, a second data connection line1722B, a third data connection line1722C, a fourth data connection line1722D, a fifth data connection line1722E and a sixth data connection line1722F. The first data connection line1722A is connected with the first data line1482A, the second data connection line1722B is connected with the second data line1482B, the third data connection line1722C is connected with the third data line1482C, the fourth data connection line1722D is connected with the fourth data line1482D, the fifth data connection line1722E is connected with the fifth data line1284E, and the sixth data connection line1722F is connected with the sixth data line1482F. Therefore, the display substrate can connect the data lines of sub-pixels located in the same column in two pixel islands adjacent in the second direction through the same data connection line.

In some examples, as illustrated inFIGS.7and8, the first data connection line1722A, the second data connection line1722B and the fifth data connection line1722E are located in the first conductive layer108; the power connection line1721, the third data connection line1722C, the fourth data connection line1722D and the sixth data connection line1722F are located in the second conductive layer1010. Therefore, the distance between the orthographic projections of the first data connection line1722A, the second data connection line1722B, the third data connection line1722C, the fourth data connection line1722D, the fifth data connection line1722E, the sixth data connection line1722F and the power connection line1721on the base substrate101can be set smaller, that is, these second connection lines can be set more densely, thereby reducing the width of the second passage region or increasing the number of the second connection lines in the second passage region.

FIG.9is a schematic plan view of a display substrate according to an embodiment of the present disclosure. As illustrated inFIG.9, the display substrate100includes a first display region181and a second display region182. The PPI of the first display region181is greater than the PPI of the second display region182, and the pixel island110is located in the second display region182.

It should be noted that because the PPI of the first display region181is greater than the PPI of the second display region182, there are more pixels in the first display region181, and these pixels can be connected with the corresponding driving circuits through the third connection lines. At this time, the third connection lines can also be routed through the first passage region, the second passage region and the transfer region.

In some examples, the display substrate100further includes a transfer region183located between the first display region181and the second display region182. The PPI of the transfer region183is smaller than the PPI of the first display region181, but the PPI of the transfer region183can be greater than or equal to the PPI of the second display region182. The transfer region183is not provided with the above-mentioned opening, and can be provided with a row driving circuit for driving the pixels of the display substrate100to perform light-emitting display. In some examples, as illustrated inFIG.9, the second display region182is located at the corner of the first display region181. For example, the planar shape of the display substrate100is approximately a rounded rectangle, and the second display region182is located at four corner regions of the display substrate100, that is, the above-mentioned second display region182can be bent, so that the four curved surface screen design can be realized.

In some examples, as illustrated inFIG.9, the planar shape of the first display region181includes a first rectangle and two second rectangles located at two sides of the first rectangle in the second direction, and the planar shape of the second display region includes four sectors located at two sides of the two second rectangles in the first direction.

In some examples, the second display region182of the display substrate100is bendable in a direction perpendicular to the first display region181. For example, the display substrate100includes a light-emitting side, that is, the side where the light emitted from the display substrate100exits, and the portion of the display substrate100located in the second display region182can be bent to the side opposite to the light-emitting side, thereby realizing a curved 3D stereoscopic effect, thereby creating a stereoscopic immersion feeling.

An embodiment of the present disclosure further provides a display device.FIG.10is a schematic diagram of a display device according to an embodiment of the present disclosure. As illustrated inFIG.10, the display device900includes the display substrate100described above. Because the display substrate100can realize the wiring of the driving lines in the stretchable or bent regions with opening patterns, the display device900including the display substrate100can also realize the wiring of the driving lines in the stretchable or bent regions with opening patterns, thus realizing a four curved surface screen design while having a narrow frame width.

For example, the above-mentioned display device can be an electronic product with display function such as a television, a mobile phone, a computer, a navigator, and an electronic picture frame, etc.

It is to be noted that:(1) The accompanying drawings involve only the structure(s) in connection with the embodiment(s) of the present disclosure, and other structure(s) can be referred to common design(s).(2) In case of no conflict, features in one embodiment or in different embodiments of the present disclosure can be combined.

What have been described above are only specific implementations of the present disclosure, the protection scope of the present disclosure is not limited thereto, and easily conceivable changes or substitutions should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.