Patent ID: 12224204

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In accordance with some embodiments, an etch-stop layer (ESL) is formed between adjacent dielectric layers, such as between inter-layer dielectric (ILDs). The ESL is formed of aluminum oxide, and the ILDs are formed of silicon oxide, allowing the ESL and ILDs to have high etch selectivity relative a set of etching processes. Over-etching of the ESL may thus be avoided, decreasing pattern loading effects. When forming openings for source/drain or gate contacts, a multi-step etch is performed. In particular, a dry etch is performed to pattern the overlying ILD, and a wet etch is then performed to extending the openings through the ESL. The wet etch includes a dielectric protective agent, which helps control the amount of lateral etching of the ESL by forming protective layers on sidewalls of the ESL during etching. By controlling the amount of lateral etching, the amount of the lateral etching of the ESL may be reduced, which helps reduce the amount of current leakage from the contacts subsequently formed in the openings.

FIG.1illustrates an example of simplified Fin Field-Effect Transistors (FinFETs) in a three-dimensional view, in accordance with some embodiments. Some other features of the FinFETs (discussed below) are omitted for illustration clarity. The FinFETs may be electrically connected or coupled in a manner to operate as, for example, one transistor or more, such as four transistors. The FinFETs comprise a substrate70and fins72extending from the substrate70. Shallow trench isolation (STI) regions74are disposed over the substrate70, and the fins72protrude above and from between neighboring STI regions74. The FinFETs further comprise gate stacks76disposed on the fins72and STI regions74. The gate stacks76extend along the sidewalls and over the top surfaces of the fins72, and cover respective channel regions78(seeFIG.2) of the fins72. The FinFETs further comprise source/drain regions80disposed in the fins72on opposite sides of the gate stacks76, adjoining the channel regions78of the fins72. Gate spacers82are disposed along the sidewalls of the gate stacks76, and physically and electrically separate the source/drain regions80from the gate stacks76. A first inter-layer dielectric (ILD)84is disposed over the source/drain regions80, along opposing sides of the gate stacks76. As discussed further below, a second ILD can be deposited over the first ILD84.

The substrate70may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate70may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate70may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. For example, when p-type devices are formed, the substrate70may be a strained material such as silicon germanium (SixGe1-x, where x can be in the range of 0 to 1) having a germanium concentration in the range of about 0% to about 40%, such that FinFETs with p-type fully strained channel (PFSC) regions are formed.

The fins72are semiconductor strips. In some embodiments, the fins72may be formed in the substrate70by etching trenches in the substrate70, with remaining material of the substrate70between the trenches forming the fins72. The etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etch process may be anisotropic.

The STI regions74are formed of an insulation material. The insulation material may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable chemical vapor deposition (FCVD) (e.g., a chemical vapor deposition (CVD) based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In some embodiments, the insulation material is silicon oxide formed by a FCVD process. In some embodiments a liner (not shown) may first be formed along a surface of the substrate70and the fins72, and a fill material (such as the insulation material described above) may be formed on the liner. A removal process is applied to the insulation material to expose the fins72. In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch back process, combinations thereof, or the like may be utilized to expose the fins72, with portions of the insulation material remaining after the planarization process forming the STI regions74.

The process described above is just one example of how the fins72may be formed. The fins72and STI regions74may be formed with any acceptable process. In another embodiment, the fins72are formed after the STI regions74. For example, a layer of insulation material may be formed over the substrate70, and openings may be formed in the insulation material. The fins72may then be grown in the openings by an epitaxial growth process, with the portions of the insulation material remaining between the fins72forming the STI regions74.

Appropriate wells (not shown) may be formed in the fins72and/or substrate70. When n-type devices, such as NMOS transistors, e.g., n-type FinFETs are formed, p-type wells may be formed. When p-type devices, such as PMOS transistors, e.g., p-type FinFETs are formed, n-type wells may be formed. In some embodiments, the wells are formed by implantation doping. In some embodiments, the grown materials of the fins72and/or substrate70may be in-situ doped during growth, which may obviate the implantation doping, although in-situ and implantation doping may be used together.

The gate stacks76may be formed with a gate-first process or a gate-last process. When a gate-first process is used, the gate stacks76are initially formed over the respective channel regions78of the fins72, the gate spacers82are then deposited along the sidewalls of the gate stacks76, the source/drain regions80are grown adjacent the gate spacers82, and the first ILD84is deposited over the source/drain regions80. When a gate-last process is used, dummy gate stacks are initially formed on the channel regions78of the fins72, the gate spacers82are deposited along the sidewalls of the dummy gate stacks, the source/drain regions80are grown adjacent the gate spacers82, the first ILD84is deposited over the source/drain regions80, and the dummy gate stacks are then replaced with replacement gate stacks76. The gate stacks76include gate dielectrics86on the fins72and STI regions74, and gate electrodes88over the gate dielectrics86. When a gate-last process is used, the gate dielectrics86can extend along sidewalls of the gate spacers82; when a gate-first process is used, the gate dielectrics86do not extend along sidewalls of the gate spacers82.

The gate spacers82may be formed of a dielectric material, such as silicon nitride, silicon carbon nitride, a combination thereof, or the like. In some embodiments (not shown), the gate spacers82are formed of a multi-layered insulating material, and include multiple layers. For example, the gate spacers82may include multiple layers of silicon nitride, or may include a layer of silicon oxide disposed between two layers of silicon nitride.

The gate dielectrics86may be formed of a dielectric material, such as silicon oxide, silicon nitride, or multilayers thereof. In some embodiments, the gate dielectrics86include a high-k dielectric material, and in these embodiments, the gate dielectrics86may have a k value greater than about 7.0, and may include a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The formation methods of the gate dielectrics86may include Molecular-Beam Deposition (MBD), atomic layer deposition (ALD), PECVD, and the like.

The gate electrodes88are deposited over the gate dielectrics86. The gate electrodes88may include a metal-containing material such as TiN, TiO, TaN, TaC, Co, Ru, Al, W, combinations thereof, or multi-layers thereof. For example, although single-layered gate electrodes88are illustrated inFIG.1, the gate electrodes88may comprise any number of liner layers (not shown), any number of work function tuning layers, and a fill material88A (seeFIG.2). In some embodiments, the gate electrodes88include a capping layer88B (seeFIG.2), which can help lower the resistance of subsequently formed gate contacts. After the filling of the gate electrodes88, a planarization process, such as a CMP, may be performed to remove the excess portions of the gate dielectrics86and gate electrodes88over the gate spacers82.

The source/drain regions80may be formed by an epitaxial growth process. In such embodiments, recesses are formed in the fins72, adjacent the gate spacers82. One or more epitaxy processes are performed to grow the source/drain regions80in the recesses. The source/drain regions80may be formed of any acceptable material for p-type or n-type devices. For example, when n-type devices are desired, the source/drain regions80can include materials exerting a tensile strain in the channel regions of the fins72, such as silicon, SiC, SiCP, SiP, or the like. Likewise, when p-type devices are desired, the source/drain regions80can include materials exerting a compressive strain in the channel regions of the fins72, such as SiGe, SiGeB, Ge, GeSn, or the like. The source/drain regions80are doped with n-type and/or p-type impurities, and can be in situ doped during growth, or can be implanted with dopants after growth. In embodiments where multiple transistors are formed, the source/drain regions80may be shared between various transistors. For example, in embodiments where one transistor is formed of multiple fins72, neighboring source/drain regions80may be electrically connected, such as through coalescing the source/drain regions80during epitaxial growth, or through coupling the source/drain regions80with a same source/drain contact.

After formation of the source/drain regions80, the first ILD84is deposited over the source/drain regions80. The first ILD84may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), undoped Silicate Glass (USG), or the like. Other insulation materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) is disposed between the first ILD84and the gate stacks76, source/drain regions80, and gate spacers82. A planarization process, such as a CMP, may then be performed to level the top surface of the first ILD84with the top surfaces of the gate stacks76and gate spacers82. Top surfaces of the gate stacks76, gate spacers82, and first ILD84are thus level. Accordingly, the top surfaces of the gate stacks76are exposed through the first ILD84.

FIGS.2through19are cross-sectional views of intermediate stages in the manufacturing of contacts for FinFETs, in accordance with some embodiments.FIGS.2through19are shown along a reference cross-section A-A illustrated inFIG.1, except for multiple FinFETs. Cross-section A-A is along a longitudinal axis of a fin72and in a direction of, for example, a current flow between the source/drain regions80.

FIG.2illustrates a region70A and a region70B of the substrate70, after the formation of features similar to the FinFETs shown inFIG.1. In some embodiments, the region70A is used for forming n-type devices, and the region70B is used for forming p-type devices. In some embodiments, the regions70A and70B are used for forming the same types of devices. The regions70A and70B may include the same fins72or different fins72.

InFIG.3, gate masks102are formed over the gate stacks76. The gate masks102protect the gate stacks76during subsequent processing, and subsequently formed gate contacts will penetrate through the gate masks102to contact the top surfaces of the gate electrodes88. The gate masks102may also be formed over the gate spacers82. As an example to form the gate masks102, the gate dielectrics86and gate electrodes88are recessed by, e.g., an acceptable etching process, such as a wet or dry etch. The gate spacers82may also be partially recessed by the etching process. Due to differences in etching rates of the different materials, the gate electrodes88may be recessed further than the gate dielectrics86and gate spacers82. One or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, are filled in the recesses. In some embodiments, the gate masks102are formed of silicon nitride. A planarization process may be performed to remove excess portions of the dielectric material extending over the first ILD84. Remaining portions of the dielectric material in the recesses forms the gate masks102.

InFIG.4A, lower source/drain contacts104are formed through the first ILD84to be physically and electrically coupled to the source/drain regions80.FIG.4Bis a detailed view of a region4B inFIG.4A, showing additional details of the lower source/drain contacts104. Openings for the lower source/drain contacts104are formed through the first ILD84. The openings may be formed using acceptable photolithography and etching techniques. For example, a liner104A, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material104B can be formed in the openings. The liner104A may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material104B may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. In some embodiments, the conductive material104B is cobalt. A planarization process, such as a CMP, may be performed to remove excess material from the top surface of the first ILD84. The remaining liner104A and conductive material104B form the lower source/drain contacts104. An anneal process may be performed to form a silicide at the interface between the lower source/drain contacts104and the source/drain regions80.

In some embodiments, contact liners106are formed around the lower source/drain contacts104. The contact liners106may be formed by conformally depositing a layer of dielectric material such as silicon nitride, silicon oxynitride, or the like in the openings for the lower source/drain contacts104. The deposition may be by MBD, ALD, PECVD, or the like. An acceptable etch, such as an anisotropic etch, may then be performed to remove horizontal portions of the dielectric layer, with remaining portions along the sidewalls of the openings forming the contact liners106. The lower source/drain contacts104may then be formed in the openings. The contact liners106are additional layers that help physically and electrically separate the lower source/drain contacts104from the gate stacks76.

InFIG.5, an etch stop layer108is formed over the first ILD84, gate masks102, lower source/drain contacts104, and contact liners106(when formed). A second ILD110is then formed over the etch stop layer108. The etch stop layer108is formed of a material that has a high etch selectivity with the second ILD110, such that the second ILD110is etched at a higher rate than the etch stop layer108relative a same etching process. For example, the etch stop layer108is formed of an insulating material, such as a single layer of aluminum oxide. The etch stop layer108may be formed by a deposition process such as ALD, CVD, PECVD, or the like. Because the etch stop layer108has a high etch selectivity with the second ILD110relative a same etching process, it can be formed to a small thickness T1. For example, the etch stop layer108can have a thickness T1in the range of about 20 {acute over (Å)} to about 50 {acute over (Å)}.

The second ILD110is a flowable film that can be formed by a flowable CVD method. In some embodiments, the second ILD110is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD and PECVD.

InFIG.6, source/drain contact openings112are formed through second ILD110. The source/drain contact openings112expose the etch stop layer108. The source/drain contact openings112may be formed using acceptable photolithography and etching techniques. A photoresist (not shown) is formed over the second ILD110and patterned with the pattern of the source/drain contact openings112. In some embodiments, a dry etch process114is performed to transfer the pattern of the photoresist to the second ILD110, thus forming the source/drain contact openings112. For example, in some embodiments the dry etch process114comprises generating a plasma sheath over the second ILD110using chlorine or bromine gas. The dry etch process114can be performed in an environment comprising argon or nitrogen, and can be performed for a duration in the range of about 10 seconds and about 150 seconds.

The material of the etch stop layer108(e.g., aluminum oxide) has a high etch selectivity with the material of the second ILD110(e.g., silicon oxide), such that the second ILD110is etched at a higher rate than the etch stop layer108relative the dry etch process114. For example, the ratio of the etching rate of the second ILD110to the etching rate of the etch stop layer108, relative the dry etch process114, can be in the range of about 10:1 to about 100:1. As such, substantially no reduction or very little reduction in thickness T1of the etch stop layer108occurs during the dry etch process114. Loading effects in subsequent processing may be reduced by reducing over-etching of the etch stop layer108

FIG.7illustrates additional details of a region70C ofFIG.6, after the dry etch process114is performed. Although substantially no reduction in thickness T1of the etch stop layer108occurs during the dry etch process114, some regions108D of the etch stop layer108are damaged (or more generally, modified) by the dry etch process114. For example, the etchants of the dry etch process114may react with the material of the etch stop layer108, changing the material composition of the damaged etch stop layer regions108D. Depending on the precise parameters of the dry etch process114, the new material composition of the damaged etch stop layer regions108D may be more porous. In some embodiments, the dry etch process114replaces oxygen in the damaged etch stop layer regions108D with fluoride or bromide compounds. Thus, the damaged etch stop layer regions108D are a different material than undamaged etch stop layer regions108U. For example, the undamaged etch stop layer regions108U may still be formed of aluminum oxide, but the damaged etch stop layer regions108D may be formed of aluminum chloride, aluminum bromide, or the like. As discussed further below, the damaged etch stop layer regions108D will be more quickly etched in subsequent processing.

InFIG.8, the source/drain contact openings112are extended through the etch stop layer108. The extended source/drain contact openings112expose the lower source/drain contacts104. The source/drain contact openings112may be extended using an acceptable etching technique. In some embodiments, a wet etch process116is performed to extend the source/drain contact openings112through the etch stop layer108.

FIG.9Aillustrates additional details of the region70C ofFIG.8, after the wet etch process116is performed. The wet etch process116is performed until the damaged etch stop layer regions108D are removed and the lower source/drain contacts104are exposed. The wet etch process116is selective to the material of the damaged etch stop layer regions108D (e.g., aluminum chloride or aluminum bromide), such that the damaged etch stop layer regions108D are etched at a higher rate than the lower source/drain contacts104and the undamaged etch stop layer regions108U. The wet etch process116can be anisotropic, but some unevenness in the profile of the sidewalls of the undamaged etch stop layer regions108U can still occur. For example,FIG.9Billustrates an embodiment where the undamaged etch stop layer regions108U have a curved profile in their etched sidewalls.

The wet etch process116is performed by exposing the etch stop layer108to an etching solution that comprises an etching agent, a dielectric protective agent, and a cobalt protective agent. The etching solution can include deionized water at a concentration of about 20% to about 98% (such as about 95%), the etching agent at a concentration of about 0.1% to about 3% (such as about 2.5%), the dielectric protective agent at a concentration of about 0.01% to about 3% (such as about 2.5%), and the cobalt protective agent at a concentration of about 0.01% to about 3% (such as less than about 1%). In some embodiments, the etching solution can also include an ammonia peroxide mixture (APM) or carbonated deionized water. The etching agent reacts with the material of the damaged etch stop layer regions108D to remove the damaged etch stop layer regions108D while removing limited amounts of the undamaged etch stop layer regions108U, as discussed in greater detail below. In some embodiments, the etching agent is an acid with a high alkalinity, such as hydrofluoric acid, ammonia, or the like.

The dielectric protective agent reacts with the materials of the etch stop layer108(e.g., aluminum oxide) to slow the etch rate of the undamaged etch stop layer regions108U. In some embodiments, the dielectric protective agent is an oxidizer, such as hydrogen peroxide (H2O2), ozone, or the like. During the wet etch process116, the damaged etch stop layer regions108D are quickly removed. As sidewalls of the undamaged etch stop layer regions108U are exposed, the dielectric protective agent reacts with the material of the undamaged etch stop layer regions108U (e.g., aluminum oxide) to form protective layers117. The protective layers117comprise a product of the dielectric protective agent and the material of the undamaged etch stop layer regions108U. For example, when the undamaged etch stop layer regions108U are aluminum oxide, the protective layers117can comprise high-density aluminum oxide or aluminum hydroxide. The density of the protective layers117can be greater than the density of the undamaged etch stop layer regions108U. In some embodiments, a thermal process is performed to promote formation of the protective layers117. For example, an anneal or baking process can be performed before the etching to thermally oxidize the sidewalls of the undamaged etch stop layer regions108U. The protective layers117protect the sidewalls of the undamaged etch stop layer regions108U. The amount of the undamaged etch stop layer regions108U removed during the wet etch process116may thus be greatly reduced or controlled.

The cobalt protective agent reacts with the materials of the lower source/drain contacts104(e.g., cobalt) to slow the etch rate of the lower source/drain contacts104. In some embodiments, the cobalt protective agent is a cobalt inhibitor, such as a benzotriazole (BTA) polymer having a methyl or ethyl side chain. During the wet etch process116, the cobalt protective agent passivates exposed surfaces of the lower source/drain contacts104to form a protective layer119that covers the lower source/drain contacts104. The protective layer119can be, e.g., anthracene, and can be electrically conductive. Some protective layer119can remain after the wet etch process116. The lower source/drain contacts104may thus remain protected during the wet etch process116. Further, because the dielectric protective agent is an oxidizer, it can form an oxide (e.g., cobalt oxide) of the material of the lower source/drain contacts104. The cobalt protective agent may also remove the oxide from the lower source/drain contacts104, thus decreasing contact resistance.

After formation, the source/drain contact openings112have upper widths WU1through the second ILD110, and lower widths WL1through the etch stop layer108. The upper widths WU1can be in the range of about 3 nm to about 100 nm. As noted above, the wet etch process116is selective to the material of the damaged etch stop layer regions108D (e.g., aluminum chloride or aluminum bromide). Thus, although some lateral etching of the undamaged etch stop layer regions108U occurs during the wet etch process116, the amount of lateral etching is small. For example, the wet etch process116laterally etches the undamaged etch stop layer regions108U by an amount that can be in the range of about 1 nm to about 9 nm (such as less than about 1.5 nm). Thus, the lower widths WL1can be in the range of about 4 nm to about 109 nm. Because the amount of lateral etching is small, the ratio of the upper widths WU1to the lower widths WL1is close to 1, such as in the range of about 3:4 to about 100:109. Depending on the amount of lateral etching, portions of the gate masks102and/or contact liners106may also be exposed.

In some embodiments, source/drain contact openings112of differing widths can be formed. For example, a first subset of the source/drain contact openings112A can have small upper widths WU1, such as upper widths WU1of about 3 nm, and a second subset of the source/drain contact openings112B can have large upper widths WU1, such as upper widths WU1of about 10 nm. The desired widths of the source/drain contact openings112can depend on the limits of the photolithographic processes used for initially forming the source/drain contact openings112. When wider source/drain contact openings112are formed, they may also expose one or more of the gate masks102and/or contact liners106. Because the wet etch process116is selective to the material of the undamaged etch stop layer regions108U (e.g., aluminum oxide), etching of the material of the gate masks102(e.g., silicon nitride) may be avoided or reduced. For example, the ratio of the etching rate of the undamaged etch stop layer regions108U to the etching rate of the gate masks102, relative the wet etch process116, can be greater than about 100:1.

InFIG.10, upper source/drain contacts118are formed through the second ILD110and etch stop layer108to be physically and electrically coupled to some of the lower source/drain contacts104. In some embodiments, the upper source/drain contacts118comprises a liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material formed in the source/drain contact openings112. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. In some embodiments, the conductive material is tungsten. In some embodiments, the lower source/drain contacts104are formed of a first conductive material (e.g., cobalt), and the upper source/drain contacts118are formed of a different second conductive material (e.g., tungsten). A planarization process, such as a CMP, may be performed to remove excess material from the top surface of the second ILD110. The remaining liner and conductive material form the upper source/drain contacts118.

FIG.11illustrates additional details of the region70C ofFIG.10, after the upper source/drain contacts118are formed. The portions of the upper source/drain contacts118that extend through the second ILD110have the upper widths WU1, and the portions of the upper source/drain contacts118that extend through the etch stop layer108have the lower widths WL1. The upper source/drain contacts118include upper source/drain contacts118A in the source/drain contact openings112A, and upper source/drain contacts118B in the source/drain contact openings112B.

It should be appreciated that not all lower source/drain contacts104have a corresponding upper source/drain contact118. In some types of devices, a subset of the lower source/drain contacts104remain covered, and will be subsequently coupled to shared contacts, e.g., contacts that are shared between gate stacks76(seeFIG.10) and source/drain regions80. Shared contacts can be used for forming some types of memory devices, such as static random-access memory (SRAM) devices.

InFIG.12, gate contact openings120are formed through the second ILD110. The gate contact openings120expose the etch stop layer108. The gate contact openings120may be formed using acceptable photolithography and etching techniques. A photoresist (not shown) is formed over the second ILD110and patterned with the pattern of the gate contact openings120. In some embodiments, a dry etch process122is performed to transfer the pattern of the photoresist to the second ILD110, thus forming the gate contact openings120. The material of the etch stop layer108(e.g., aluminum oxide) has a high etch selectivity with the material of the second ILD110(e.g., silicon oxide), such that the second ILD110is etched at a higher rate than the etch stop layer108relative the dry etch process122. As such, substantially no reduction in thickness T1of the etch stop layer108occurs during the dry etch process122. Loading effects in subsequent processing may be reduced by reducing over-etching of the etch stop layer108.

The dry etch process122can be similar to the dry etch process114(seeFIG.6). After the dry etch process122, a post-etch cleaning process is performed. During the post-etch cleaning process, the intermediate structure is exposed to a tungsten protective agent. The tungsten protective agent adsorbs to exposed surfaces of the upper source/drain contacts118(e.g., tungsten) to form a protective layer123that protects the upper source/drain contacts118during subsequent processing. In some embodiments, the tungsten protective agent is a tungsten inhibitor, such as a benzotriazole (BTA) polymer having a chlorine side chain. The protective layer123can be, e.g., anthracene, and can be electrically conductive. Some protective layer123can remain after the dry etch process122.

FIG.13illustrates additional details of a region70D ofFIG.12, after the dry etch process122is performed. As discussed above, although substantially no reduction in thickness T1of the etch stop layer108occurs during the dry etch process122, some regions108D of the etch stop layer108are modified or damaged by the dry etch process122. The damaged etch stop layer regions108D are a different material than undamaged etch stop layer regions108U, and will be more quickly etched in subsequent processing.

InFIG.14, the gate contact openings120are extended through the etch stop layer108. The extended gate contact openings120expose the gate masks102. The gate contact openings120may be extended using an acceptable etching technique. In some embodiments, a wet etch process124is performed to extend the gate contact openings120through the etch stop layer108.

FIG.15illustrates additional details of the region70D ofFIG.14, after the wet etch process124is performed. The wet etch process124is performed until the damaged etch stop layer regions108D are removed and the gate masks102are exposed. The wet etch process124is selective to the material of the damaged etch stop layer regions108D (e.g., aluminum chloride or aluminum bromide), such that the damaged etch stop layer regions108D are etched at a higher rate than the lower source/drain contacts104and the undamaged etch stop layer regions108U. The wet etch process124forms protective layers117, which protect the undamaged etch stop layer regions108U from etching.

The wet etch process124is performed by exposing the etch stop layer108to an etching solution that comprises an etching agent, a dielectric protective agent, and a cobalt protective agent. The etching solution can include the water at a concentration of about 20% to about 98% (such as about 95%), the etching agent at a concentration of about 0.1% to about 3% (such as about 2.5%), the dielectric protective agent at a concentration of about 0.01% to about 3% (such as about 2.5%), and the cobalt protective agent at a concentration of about 0.01% to about 3% (such as less than about 1%). The etching agent, dielectric protective agent, and cobalt protective agent are similar to the corresponding agents used in the wet etch process116. The material of the etch stop layer108(e.g., aluminum oxide) has a high etch selectivity with the material of the gate masks102(e.g., silicon nitride), such that the etch stop layer108is etched at a higher rate than gate masks102relative the wet etch process124. As such, substantially no reduction in height of the gate masks102occurs.

During the wet etch process124, the upper source/drain contacts118are protected. In some embodiments, the upper source/drain contacts118are protected by including a tungsten protective agent in the etching solution for the wet etch process124. The tungsten protective agent can be similar to the tungsten protective agent used during the post-etch cleaning process after the dry etch process122. In some embodiments, the upper source/drain contacts118are protected by adjusting the environment of the wet etch process124to reduce the etch rate of tungsten. For example, the wet etch process124may be performed at a low temperature, such as a temperature of about 20° C. to about 40° C., and with an etching solution having a low pH, such as a pH of about 5 to about 7, thereby lowering the etch rate of tungsten and limiting or reducing any removal of tungsten. In some embodiments, both a tungsten protective agent and an adjusted environment are used during the wet etch process124. By protecting the upper source/drain contacts118, substantially no reduction in height of the upper source/drain contacts118occurs.

InFIG.16, the gate contact openings120are extended through the gate masks102. The extended gate contact openings120expose the gate stacks76. The gate contact openings120may be extended using an acceptable etching technique. In some embodiments, a dry etch process126is performed to extend the gate contact openings120through the gate masks102. For example, in some embodiments the dry etch process126comprises generating a plasma sheath over the second ILD110using a fluorocarbon (e.g., CxFy) gas. The dry etch process126can be performed in an environment comprising argon or nitrogen, and can be performed for a duration in the range of about 10 seconds and about 150 seconds. The dry etch process126is performed until portions of the gate masks102are removed and the gate stacks76are exposed. Some portions of the gate stacks76(e.g., portions of the capping layer88B) may also be removed. The material of the gate masks102(e.g., silicon nitride) has a high etch selectivity with the material of the second ILD110(e.g., silicon oxide) and the material of the etch stop layer108(e.g., aluminum oxide) such that the gate masks102are etched at a higher rate than the etch stop layer108and the second ILD110relative the dry etch process126. Thus, substantially no reduction in height of the second ILD110occurs, and substantially no lateral etching of the etch stop layer108occurs. Further, because the upper source/drain contacts118and lower source/drain contacts104were exposed to cobalt and tungsten protective agents during the wet etch process124, substantially no reduction in height of the upper source/drain contacts118or lower source/drain contacts104occurs during the dry etch process126.

FIG.17illustrates additional details of the region70D ofFIG.16, after the dry etch process126is performed. After formation, the gate contact openings120have upper widths WU2through the second ILD110, intermediate widths WI2through the etch stop layer108, and lower widths WL2through the gate masks102. The upper widths WU2can be in the range of about 3 nm to about 100 nm. As noted above, the wet etch process124is selective to the material of the damaged etch stop layer regions108D (e.g., aluminum chloride or aluminum bromide). Thus, although some lateral etching of the undamaged etch stop layer regions108U occurs during the wet etch process124, the amount of lateral etching is small. For example, the wet etch process124laterally etches the undamaged etch stop layer regions108U by an amount that can be in the range of about 1 nm to about 9 nm (such as less than about 1.5 nm). Thus, the intermediate widths WI2can be in the range of about 4 nm to about 109 nm. Further, the lower widths WL2can be smaller than the intermediate widths WI2. For example, the lower widths WL2can be in the range of about 2 nm to about 90 nm.

In some embodiments, gate contact openings120of differing widths can be formed. For example, a first subset of the gate contact openings120A can have small upper widths WU2, such as upper widths WU2of about 3 nm, and a second subset of the gate contact openings120B can have large upper widths WU2, such as upper widths WU2of about 10 nm. The first subset of the gate contact openings120A can be for gate contacts that are only for gate stacks76, and the second subset of the gate contact openings120B can be for shared contacts, e.g., contacts that are shared between gate stacks76and source/drain regions80. Thus, the second subset of the gate contact openings120B may also expose one or more of the lower source/drain contacts104and/or contact liners106.

InFIG.18, gate contacts128are formed through the second ILD110, etch stop layer108, and gate masks102to be physically and electrically coupled to the gate stacks76and optionally to some of the lower source/drain contacts104. A liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the gate contact openings120. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. In some embodiments, the conductive material is tungsten. In some embodiments, the gate contacts128and upper source/drain contacts118are formed of the same conductive material (e.g., tungsten). A planarization process, such as a CMP, may be performed to remove excess material from the top surface of the second ILD110. The remaining liner and conductive material form the gate contacts128. The gate contacts128include gate contacts128A in the gate contact openings120A, and gate contacts128B in the gate contact openings120B. The gate contacts128B may each be a shared contact that couples a source/drain region80to a gate stack76.

Although the shared contacts are shown as being formed during the process for forming the gate contacts128, it should be appreciated that shared contacts may also be formed during the process for forming the upper source/drain contacts118. For example, a dry etch process similar to the dry etch process126may be performed to extend the source/drain contact openings112B (seeFIG.8) through the gate masks102. Some of the upper source/drain contacts118may thus also be shared contacts. In other words, the shared contacts may be formed concurrently with the source/drain contacts, the gate contacts, or both.

FIG.19illustrates additional details of the region70D ofFIG.18, after the gate contacts128are formed. The portions of the gate contacts128that extend through the second ILD110have the upper widths WU2, the portions of the gate contacts128that extend through the etch stop layer108have the intermediate widths WI2, and the portions of the gate contacts128that extend through the gate masks102have the lower widths WL2.

FIGS.20through28are cross-sectional views of intermediate stages in the manufacturing of contacts for FinFETs, in accordance with some other embodiments.FIGS.20through28are shown along the reference cross-section A-A illustrated inFIG.1, except for multiple FinFETs. In this embodiment, a buffer layer130is formed over the etch stop layer108, which helps protect the etch stop layer108from over-etching during the dry etch process114for the second ILD110.

InFIG.20, a structure similar to the intermediate structure ofFIG.5is shown. A buffer layer130is formed between the etch stop layer108and the second ILD110. The buffer layer130is formed of a material that has a high etch selectivity with the etch stop layer108, such that the buffer layer130is etched at a higher rate than the underlying etch stop layer108relative a same etching process. The buffer layer108can help control etching of the etch stop layer108. For example, the buffer layer130is formed of an insulating material, such as a layer of silicon nitride, silicon oxynitride, silicon oxycarbide, tungsten carbide, or the like. The buffer layer130may be formed by a deposition process such as ALD, CVD, PECVD, or the like. The buffer layer130may be the same material as the gate masks102. In the embodiment shown, the buffer layer130is a single layer of silicon nitride. The etch stop layer108may be formed to a small thickness T2. For example, the etch stop layer108can have a thickness T2in the range of about 20 {acute over (Å)} to about 50 {acute over (Å)}. The buffer layer130may also be formed to a small thickness T3. For example, the buffer layer130can have a thickness T3in the range of about 20 {acute over (Å)} to about 50 {acute over (Å)}.

InFIG.21, a dry etch process is performed to form the source/drain contact openings112through the second ILD110and buffer layer130. The dry etch process may be similar to the dry etch process114discussed above with reference toFIG.6. The dry etch process114is selective to the materials of the second ILD110and buffer layer130, and removes the material of both layers, albeit at differing rates.

InFIG.22, a wet etch process is performed to extend the source/drain contact openings112through the etch stop layer108. The wet etch process may be similar to the wet etch process116discussed above with reference toFIG.8. The wet etch process116is selective to the material of the damaged etch stop layer regions108D (seeFIG.7), such that the damaged etch stop layer regions108D are etched at a higher rate than the lower source/drain contacts104, undamaged etch stop layer regions108U, gate masks102, and buffer layer130.

InFIG.23, the upper source/drain contacts118are formed through the second ILD110, etch stop layer108, and buffer layer130to be physically and electrically coupled to some of the lower source/drain contacts104. The upper source/drain contacts118may be formed in the source/drain contact openings112using a similar method as that discussed above with respect toFIG.10. Although not separately illustrated, a protective layer119(seeFIG.9A) can be formed between the upper source/drain contacts118and the lower source/drain contacts104.

InFIG.24, a dry etch process is performed to form the gate contact openings120through the second ILD110and buffer layer130. The dry etch process may be similar to the dry etch process122discussed above with reference toFIG.12. The dry etch process122is selective to the materials of the second ILD110and buffer layer130, and removes the material of both layers, albeit at differing rates. Although not separately illustrated, a protective layer123(seeFIG.12) can be formed on the upper source/drain contacts118during the dry etch process.

InFIG.25, a wet etch process is performed to extend the gate contact openings120through the etch stop layer108. The wet etch process may be similar to the wet etch process124discussed above with reference toFIG.14. The wet etch process124is selective to the material of the damaged etch stop layer regions108D (seeFIG.7), such that the damaged etch stop layer regions108D are etched at a higher rate than the lower source/drain contacts104, undamaged etch stop layer regions108U, and buffer layer130.

InFIG.26, a dry etch process is performed to extend the gate contact openings120through the gate masks102. The dry etch process may be similar to the dry etch process126discussed above with reference toFIG.16. The extended gate contact openings120expose the gate stacks76. The dry etch process may also laterally etch the etch stop layer108, but the etching rate of the etch stop layer108is negligible compared to the etching rate of the gate masks102.

InFIG.27, the gate contacts128are formed through the second ILD110, etch stop layer108, gate masks102, and buffer layer130to be physically and electrically coupled to the gate stacks76and optionally to some of the lower source/drain contacts104. The gate contacts128may be formed in the gate contact openings120using a similar method as that discussed above with respect toFIG.18.

FIG.28illustrates additional details of a region70E ofFIG.27, after the gate contacts128are formed. The portions of the gate contacts128that extend through the second ILD110have the upper widths WU2, the portions of the gate contacts128that extend through the etch stop layer108have the intermediate widths WI2, and the portions of the gate contacts128that extend through the gate masks102have the lower widths WL2. Further, the portions of the gate contacts128that extend through the buffer layer130have intermediate widths WI3, which are less than the intermediate widths WI2. For example, the intermediate widths WI3can be in the range of 3 nm to 100 nm.

FIGS.29through38are cross-sectional views of intermediate stages in the manufacturing of contacts for FinFETs, in accordance with some other embodiments.FIGS.29through38are shown along the reference cross-section A-A illustrated inFIG.1, except for multiple FinFETs. In this embodiment, a buffer layer132is formed beneath the etch stop layer108, which helps protect the lower source/drain contacts104during the wet etch process116.

InFIG.29, a structure similar to the intermediate structure ofFIG.5is shown. A buffer layer132is formed over the first ILD84, and the etch stop layer108is formed over the buffer layer132. The buffer layer132is formed of a material that has a high etch selectivity with the etch stop layer108, relative a same etching process. For example, the buffer layer132is formed of an insulating material, such as a layer of silicon nitride, silicon oxynitride, silicon oxycarbide, tungsten carbide, or the like. The buffer layer132may be formed by a deposition process such as ALD, CVD, PECVD, or the like. The buffer layer132may be the same material as the gate masks102. In the embodiment shown, the buffer layer132is a single layer of silicon nitride. The etch stop layer108may be formed to a small thickness T4. For example, the etch stop layer108can have a thickness T4in the range of about 20 {acute over (Å)} to about 50 {acute over (Å)}. The buffer layer132may also be formed to a small T5. For example, the buffer layer132can have a T5in the range of about 20 {acute over (Å)} to about 50 {acute over (Å)}.

InFIG.30, a dry etch process is performed to form the source/drain contact openings112through the second ILD110. The dry etch process may be similar to the dry etch process114discussed above with reference toFIG.6.

InFIG.31, a wet etch process is performed to extend the source/drain contact openings112through the etch stop layer108. The wet etch process may be similar to the wet etch process116discussed above with reference toFIG.8. The wet etch process116is selective to the material of the damaged etch stop layer regions108D (seeFIG.7), such that the damaged etch stop layer regions108D are etched at a higher rate than the lower source/drain contacts104and undamaged etch stop layer regions108U.

InFIG.32, the source/drain contact openings112are extended through the buffer layer132. The extended source/drain contact openings112expose the lower source/drain contacts104. The source/drain contact openings112may be extended using an acceptable etching technique. In some embodiments, a dry etch process134is performed to extend the source/drain contact openings112through the buffer layer132. For example, in some embodiments the dry etch process134comprises generating a plasma sheath over the second ILD110using fluorocarbon (e.g., CxFy) gas. The dry etch process134can be performed in an environment comprising argon or nitrogen, and can be performed for a duration in the range of about 10 seconds and about 150 seconds. The dry etch process134is performed until portions of the buffer layer132are removed and the lower source/drain contacts104are exposed. Some portions of the gate masks102may also be removed. The dry etch process134is similar to the dry etch process126, but can be performed for a different duration. In embodiments in which the material of the gate masks102and buffer layer132are the same material or materials having similar etch rates, the dry etch process134can remove some of the gate masks102. As such, the dry etch process134may be a timed etch such that the buffer layer132is removed, and the dry etch process134is stopped while removing little or no material of the gate masks102. For example, the dry etch process134can be performed for a duration of about 10 seconds to about 150 seconds. Thus, substantially no reduction in height of the gate masks102occurs.

InFIG.33, the upper source/drain contacts118are formed through the second ILD110, etch stop layer108, and buffer layer132to be physically and electrically coupled to some of the lower source/drain contacts104. The upper source/drain contacts118may be formed in the source/drain contact openings112using a similar method as that discussed above with respect toFIG.10. Although not separately illustrated, a protective layer119(seeFIG.9A) can be formed between the upper source/drain contacts118and the lower source/drain contacts104.

InFIG.34, a dry etch process is performed to form the gate contact openings120through the second ILD110. The dry etch process may be similar to the dry etch process122discussed above with reference toFIG.12. Although not separately illustrated, a protective layer123(seeFIG.12) can be formed on the upper source/drain contacts118during the dry etch process.

InFIG.35, a wet etch process is performed to extend the gate contact openings120through the etch stop layer108. The wet etch process may be similar to the wet etch process124discussed above with reference toFIG.14. The wet etch process124is selective to the material of the damaged etch stop layer regions108D (seeFIG.7), such that the damaged etch stop layer regions108D are etched at a higher rate than the lower source/drain contacts104, undamaged etch stop layer regions108U, and buffer layer132.

InFIG.36, a dry etch process is performed to extend the gate contact openings120through the buffer layer132and gate masks102. The dry etch process may be similar to the dry etch process126discussed above with reference toFIG.16. The extended gate contact openings120expose the gate stacks76. Because the buffer layer132and gate masks102can be formed of similar materials, the dry etch process126can remove the material of both layers at similar rates.

InFIG.37, the gate contacts128are formed through the second ILD110, etch stop layer108, gate masks102, and buffer layer132to be physically and electrically coupled to the gate stacks76and optionally to some of the lower source/drain contacts104. The gate contacts128may be formed in the gate contact openings120using a similar method as that discussed above with respect toFIG.18.

FIG.38illustrates additional details of a region70F ofFIG.37, after the gate contacts128are formed. The portions of the gate contacts128that extend through the second ILD110have the upper widths WU2, the portions of the gate contacts128that extend through the etch stop layer108have the intermediate widths WI2, the portions of the gate contacts128that extend through the buffer layer132have the intermediate widths WI3, and the portions of the gate contacts128that extend through the gate masks102have the lower widths WL2, which can be measured at the tops of the gate masks102.

FIGS.39through47are cross-sectional views of intermediate stages in the manufacturing of contacts for FinFETs, in accordance with some other embodiments.FIGS.39through47are shown along the reference cross-section A-A illustrated inFIG.1, except for multiple FinFETs. In this embodiment, another etch stop layer136is formed, and a buffer layer138is formed between the etch stop layers108and136.

InFIG.39, a structure similar to the intermediate structure ofFIG.5is shown. An etch stop layer136is formed over the first ILD84, a buffer layer138is formed over the etch stop layer136, and the etch stop layer108is formed over the buffer layer138. The use of multiple etch stop layers can help better control pattern loading in a subsequent process for forming source/drain contact openings. The etch stop layer136is formed of a material that has a high etch selectivity with the second ILD110, relative a same etching process. For example, the etch stop layer136is formed of an insulating material, such as a single layer of aluminum oxide. The etch stop layer136may be formed by a deposition process such as ALD, CVD, PECVD, or the like. Because the etch stop layer136has a high etch selectivity with the second ILD110relative a same etching process, it can be formed to a small thickness T6. For example, the etch stop layer136can have a thickness T6in the range of about 20 {acute over (Å)} to about 40 {acute over (Å)}.

The buffer layer138is formed of a material that has a high etch selectivity with the etch stop layers108and136, relative a same etching process. For example, the buffer layer138is formed of an insulating material, such as a layer of silicon nitride, silicon oxynitride, silicon oxycarbide, tungsten carbide, or the like. The buffer layer138may be formed by a deposition process such as ALD, CVD, PECVD, or the like. The buffer layer138may be the same material as the gate masks102. In the embodiment shown, the buffer layer138is a single layer of silicon nitride. The buffer layer138may also be formed to a small thickness T7. For example, the buffer layer138can have a thickness T7in the range of about 20 {acute over (Å)} to about 40 {acute over (Å)}. The etch stop layer108may be formed to a small thickness T8. For example, the etch stop layer108can have a thickness T8in the range of about 20 {acute over (Å)} to about 40 {acute over (Å)}.

InFIG.40, a dry etch process is performed to form the source/drain contact openings112through the second ILD110. The dry etch process may be similar to the dry etch process114discussed above with reference toFIG.6.

InFIG.41, the source/drain contact openings112are extended through the etch stop layers108and136, and through the buffer layer138. The extended source/drain contact openings112expose the lower source/drain contacts104. The source/drain contact openings112may be extended using an acceptable etching technique. In some embodiments, a combination etch process140is performed to extend the source/drain contact openings112. The combination etch process140can include two wet etches and a dry etch. Each of the wet etches is similar to the wet etch process116, and etch the etch stop layers108and136with a small amount of lateral etching. The dry etch etches the buffer layer138and may be similar to the dry etch process134.

InFIG.42, the upper source/drain contacts118are formed through the second ILD110, etch stop layers108and136, and buffer layer138to be physically and electrically coupled to some of the lower source/drain contacts104. The upper source/drain contacts118may be formed in the source/drain contact openings112using a similar method as that discussed above with respect toFIG.10. Although not separately illustrated, a protective layer119(seeFIG.9A) can be formed between the upper source/drain contacts118and the lower source/drain contacts104.

InFIG.43, a dry etch process is performed to form the gate contact openings120through the second ILD110. The dry etch process may be similar to the dry etch process122discussed above with reference toFIG.12. Although not separately illustrated, a protective layer123(seeFIG.12) can be formed on the upper source/drain contacts118during the dry etch process.

InFIG.44, the gate contact openings120are extended through the etch stop layers108and136, and through the buffer layer138. The gate contact openings120may be extended using an acceptable etching technique. In some embodiments, a combination etch process142is performed to extend the gate contact openings120. The combination etch process142is similar to the combination etch process140discussed above with respect toFIG.41.

InFIG.45, a dry etch process is performed to extend the gate contact openings120through the buffer layer138and gate masks102. The dry etch process may be similar to the dry etch process126discussed above with reference toFIG.16. The extended gate contact openings120expose the gate stacks76.

InFIG.46, the gate contacts128are formed through the second ILD110, etch stop layers108and136, gate masks102, and buffer layer138to be physically and electrically coupled to the gate stacks76and optionally to some of the lower source/drain contacts104. The gate contacts128may be formed in the gate contact openings120using a similar method as that discussed above with respect toFIG.18.

FIG.47illustrates additional details of a region70G ofFIG.46, after the gate contacts128are formed. The portions of the gate contacts128that extend through the second ILD110have the upper widths WU2, the portions of the gate contacts128that extend through the etch stop layers108and136have the intermediate widths WI2, the portions of the gate contacts128that extend through the buffer layer138have the intermediate widths WI3, and the portions of the gate contacts128that extend through the gate masks102have the lower widths WL2.

FIGS.48through57are cross-sectional views of intermediate stages in the manufacturing of contacts for FinFETs, in accordance with some other embodiments.FIGS.48through57are shown along the reference cross-section A-A illustrated inFIG.1, except for multiple FinFETs. In this embodiments, two buffer layers144and146are formed sandwiching the etch stop layer108.

InFIG.48, a structure similar to the intermediate structure ofFIG.5is shown. A buffer layer144is formed over the first ILD84, the etch stop layer108is formed over the buffer layer144, and a buffer layer146is formed over the etch stop layer108. The buffer layers144and146are formed of a material that has a high etch selectivity with the etch stop layer108, relative a same etching process. For example, the buffer layers144and146are formed of an insulating material, such as a layer of silicon nitride, silicon oxynitride, silicon oxycarbide, tungsten carbide, or the like. The buffer layers144and146may be formed by a deposition process such as ALD, CVD, PECVD, or the like. The buffer layers144and146may be the same material as the gate masks102. In the embodiment shown, the buffer layers144and146are each a single layer of silicon nitride. The buffer layer144is formed to a small thickness T9. For example, the buffer layer144can have a thickness T9in the range of about 20 {acute over (Å)} to about 40 {acute over (Å)}. The etch stop layer108may be formed to a small thickness T10. For example, the etch stop layer108can have a thickness T10in the range of about 20 {acute over (Å)} to about 40 {acute over (Å)}. Further, the buffer layer146is formed to a small thickness T11. For example, the buffer layer146can have a thickness T11in the range of about 20 {acute over (Å)} to about 40 {acute over (Å)}.

InFIG.49, a dry etch process is performed to form the source/drain contact openings112through the second ILD110and buffer layer146. The dry etch process may be similar to the dry etch process114discussed above with reference toFIG.6. The dry etch process114is selective to the materials of the second ILD110and buffer layer146, and removes the material of both layers, albeit at differing rates.

InFIG.50, a wet etch process is performed to extend the source/drain contact openings112through the etch stop layer108. The wet etch process may be similar to the wet etch process116discussed above with reference toFIG.8. The wet etch process116is selective to the material of the damaged etch stop layer regions108D (seeFIG.7), such that the damaged etch stop layer regions108D are etched at a higher rate than the undamaged etch stop layer regions108U and the buffer layers144and146.

InFIG.51, the source/drain contact openings112are extended through the buffer layer144. The extended source/drain contact openings112expose the lower source/drain contacts104. The source/drain contact openings112may be extended using an acceptable etching technique. In some embodiments, a dry etch process148is performed to extend the source/drain contact openings112through the buffer layer144. For example, in some embodiments the dry etch process148comprises generating a plasma sheath over the second ILD110using fluorocarbon (e.g., CxFy) gas. The dry etch process148can be performed in an environment comprising argon or nitrogen, and can be performed for a duration in the range of about 10 seconds and about 150 seconds. The dry etch process148is performed until portions of the buffer layer144are removed and the lower source/drain contacts104are exposed. Some portions of the gate masks102may also be removed. The dry etch process148is similar to the dry etch process126, but can be performed for a different duration. Because the material of the gate masks102and buffer layer144are similar, the dry etch process148can remove some of the gate masks102. As such, the dry etch process148may be a timed etch such that the buffer layer144is removed, and the dry etch process148is stopped while removing little or no material of the gate masks102. For example, the dry etch process148can be performed for a duration of about 10 seconds to about 150 seconds. Thus, substantially no reduction in height of the gate masks102occurs.

InFIG.52, the upper source/drain contacts118are formed through the second ILD110, etch stop layer108, and buffer layers144and146to be physically and electrically coupled to some of the lower source/drain contacts104. The upper source/drain contacts118may be formed in the source/drain contact openings112using a similar method as that discussed above with respect toFIG.10. Although not separately illustrated, a protective layer119(seeFIG.9A) can be formed between the upper source/drain contacts118and the lower source/drain contacts104.

InFIG.53, a dry etch process is performed to form the gate contact openings120through the second ILD110and buffer layer146. The dry etch process may be similar to the dry etch process122discussed above with reference toFIG.12. The dry etch process122is selective to the materials of the second ILD110and buffer layer146, and removes the material of both layers, albeit at differing rates. Although not separately illustrated, a protective layer123(seeFIG.12) can be formed on the upper source/drain contacts118during the dry etch process.

InFIG.54, a wet etch process is performed to extend the gate contact openings120through the etch stop layer108. The wet etch process may be similar to the wet etch process124discussed above with reference toFIG.14. The wet etch process124is selective to the material of the damaged etch stop layer regions108D (seeFIG.7), such that the damaged etch stop layer regions108D are etched at a higher rate than the undamaged etch stop layer regions108U and the buffer layers144and146.

InFIG.55, a dry etch process is performed to extend the gate contact openings120through the buffer layer144and gate masks102. The dry etch process may be similar to the dry etch process126discussed above with reference toFIG.16. The extended gate contact openings120expose the gate stacks76. Because the buffer layer144and gate masks102can be formed of similar materials, the dry etch process126can remove the material of both layers at similar rates.

InFIG.56, the gate contacts128are formed through the second ILD110, etch stop layer108, gate masks102, and buffer layers144and146to be physically and electrically coupled to the gate stacks76and optionally to some of the lower source/drain contacts104. The gate contacts128may be formed in the gate contact openings120using a similar method as that discussed above with respect toFIG.18.

FIG.57illustrates additional details of a region70H ofFIG.56, after the gate contacts128are formed. The portions of the gate contacts128that extend through the second ILD110have the upper widths WU2, the portions of the gate contacts128that extend through the etch stop layer108have the intermediate widths WI2, the portions of the gate contacts128that extend through the buffer layers144and146have the intermediate widths WI3, and the portions of the gate contacts128that extend through the gate masks102have the lower widths WL2.

Embodiments may achieve advantages. By forming the etch stop layer108of a material that has a high etch selectivity with the gate masks102and second ILD110, relative the same etching processes, the amount of over-etching of the etch stop layer108may be reduced. Loading effects in subsequent processing may be reduced by reducing over-etching of the etch stop layer108. Further, by opening the etch stop layer108with an etching solution that includes a dielectric protective agent, the amount of lateral etching of the etch stop layer108may be reduced when forming the source/drain contact openings112and gate contact openings120. Reducing the lateral etching of the etch stop layer108may allow the amount of current leakage of the upper source/drain contacts118and gate contacts128to be reduced.

In an embodiment, a method includes: depositing a etch stop layer over a first inter-layer dielectric (ILD), the etch stop layer including a first dielectric material; depositing a second ILD over the etch stop layer; etching a first opening through the second ILD with a first dry etching process, the first opening exposing a first region of the etch stop layer, the first region being modified by the first dry etching process to be a second dielectric material, a second region of the etch stop layer remaining covered by the second ILD, the second region being the first dielectric material after the first dry etching process; and extending the first opening through the etch stop layer with a first wet etching process, the etch stop layer being exposed to a first etching solution during the first wet etching process, the first etching solution including a dielectric protective agent for the first dielectric material and an etching agent for the second dielectric material.

In some embodiments of the method, the first dielectric material is aluminum oxide and the second dielectric material is aluminum chloride or aluminum bromide. In some embodiments of the method, the etching agent is hydrofluoric acid or ammonia, and the dielectric protective agent is hydrogen peroxide or ozone. In some embodiments, the method further includes: forming a first conductive feature over a semiconductor substrate, the first conductive feature including a first conductive material; and depositing the first ILD over the first conductive feature, where the first etching solution further includes a first metal protective agent for the first conductive material. In some embodiments, the method further includes: forming a first contact in the first opening, the first contact being physically and electrically coupled to the first conductive feature, the first contact including a second conductive material; etching a second opening through the second ILD with a second dry etching process; and extending the second opening through the etch stop layer with a second wet etching process, the etch stop layer being exposed to a second etching solution during the second wet etching process, the second etching solution including the dielectric protective agent, the etching agent, the first metal protective agent, and a second metal protective agent for the second conductive material. In some embodiments of the method, the first conductive material is cobalt and the second conductive material is tungsten. In some embodiments of the method, the first metal protective agent is a benzotriazole polymer having a methyl or ethyl side chain, and the second metal protective agent is a benzotriazole polymer having a chlorine side chain. In some embodiments, the method further includes: forming a second conductive feature over the semiconductor substrate; depositing a mask over the second conductive feature; and depositing the etch stop layer over the mask. In some embodiments, the method further includes: extending the second opening through the mask with a third dry etching process; and forming a second contact in the second opening, the second contact being physically and electrically coupled to the second conductive feature. In some embodiments, the method further includes: depositing a buffer layer over the mask, the etch stop layer being deposited over the buffer layer; and extending the second opening through the buffer layer with the third dry etching process. In some embodiments, the method further includes: depositing a buffer layer over the etch stop layer, the second ILD being deposited over the buffer layer; and extending the first opening through the buffer layer with the first dry etching process.

In an embodiment, a device includes: a semiconductor substrate; a first inter-layer dielectric (ILD) over the semiconductor substrate; a first conductive feature extending through the first ILD; a first etch stop layer over the first conductive feature and the first ILD, the first etch stop layer being a first dielectric material; a second ILD over the first etch stop layer; a contact having a first portion extending through the second ILD and a second portion extending through the first etch stop layer, the contact being physically and electrically coupled to the first conductive feature; and a first protective layer surrounding the second portion of the contact, the first portion of the contact being free from the first protective layer, the first protective layer being a second dielectric material, the second dielectric material being different from the first dielectric material.

In some embodiments of the device, the first etch stop layer is aluminum oxide. In some embodiments of the device, the first protective layer is aluminum hydroxide. In some embodiments of the device, the first portion of the contact has a first width, the second portion of the contact has a second width, the second width is larger than the first width by a first distance, and the first distance is in a range of 1 nm to 9 nm. In some embodiments, the device further includes: a buffer layer disposed between the first conductive feature and the first etch stop layer, the contact having a third portion extending through the buffer layer, the third portion of the contact being free from the first protective layer. In some embodiments, the device further includes: a buffer layer disposed between the first etch stop layer and the second ILD, the contact having a third portion extending through the buffer layer, the third portion of the contact being free from the first protective layer. In some embodiments, the device further includes: a second etch stop layer disposed between the buffer layer and the second ILD the second etch stop layer being the first dielectric material, the contact having a fourth portion extending through the second etch stop layer; and a second protective layer surrounding the fourth portion of the contact, the second protective layer being the second dielectric material. In some embodiments, the device further includes: a first buffer layer disposed between the first ILD and the first etch stop layer, the contact having a third portion extending through the first buffer layer, the third portion of the contact being free from the first protective layer; and a second buffer layer disposed between the first etch stop layer and the second ILD, the contact having a fourth portion extending through the second buffer layer, the fourth portion of the contact being free from the first protective layer.

In an embodiment, a device includes: a semiconductor substrate; a first conductive feature over the semiconductor substrate; a first etch stop layer over the first conductive feature, the first etch stop layer being a first dielectric material; an inter-layer dielectric (ILD) over the first etch stop layer; and a contact having a first portion extending through the ILD and a second portion extending through the first etch stop layer, the contact being physically and electrically coupled to the first conductive feature, where the first portion of the contact has a first width, the second portion of the contact has a second width, the second width is larger than the first width by a first distance, and the first distance is in a range of 1 nm to 9 nm.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.