Patent ID: 12223181

DETAILED DESCRIPTION

Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some example embodiments are shown.

In the following descriptions, numerous specific details are set forth, such as examples of specific types of processors and system configurations, specific hardware structures, specific architectural and micro architectural details, specific register configurations, specific instruction types, specific system components, specific measurements/heights, specific processor pipeline stages and operation etc. in order to provide a thorough understanding of this disclosure. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice the principles and solutions discussed in this disclosure.

Among various interconnect fabric architectures, example embodiments are described based on a Peripheral Component Interconnect (PCI) Express (PCIe) architecture. A primary goal of PCIe is to enable components and devices from different vendors to inter-operate in an open architecture, spanning multiple market segments; Clients (Desktops and Mobile), Servers (Standard and Enterprise), and Embedded and Communication devices. PCI Express is a high performance, general purpose I/O interconnect defined for a wide variety of future computing and communication platforms.

Some PCI attributes, such as its usage model, load-store architecture, and software interfaces, have been maintained through its revisions, whereas previous parallel bus implementations have been replaced by a highly scalable, fully serial interface. The more recent versions of PCI Express take advantage of advances in point-to-point interconnects, Switch-based technology, and packetized protocol to deliver new levels of performance and features. Power Management, Quality Of Service (QoS), Hot-Plug/Hot-Swap support, Data Integrity, Error Handling and Credit-based Flow Control are among some of the advanced features supported by PCI Express.

FIG.1is a block diagram illustrating a storage system according to example embodiments.

Referring toFIG.1, a storage system50may include a host100and a storage device200connected to each other through a link30.FIG.1illustrates only the elements for describing example embodiments, and each of the host100and the storage device200may further include various elements depending on its own functionality.

The host100may control overall operations of the storage system50. For example, the host100may store data in the storage device200or may read data stored in the storage device200. The host100may communicate with the storage device200through a first port PT1. In an embodiment, the first port PT1may be a physical port that is based on a PCIe protocol. However, the present disclosure is not limited thereto.

The host100may include a processor110, a host memory buffer (HMB)120and a root complex150.

The processor110may be referred to as a host processor and may include a CPU core(s)111and a cache dedicated to the CPU core111.

The HMB120may include a submission queue SQ131and a completion queue CQ133. The submission queue131may be storage such as dedicated storage that stores a command to be provided to the storage device200. The completion queue133may be storage such as dedicated storage that stores completion information about an operation completed in the storage device200based on the command. The command stored in the submission queue131may be defined by an NVMe specification.

The root complex150may be connected to the processor110and the HMB120.

The storage device200may include a storage controller300and a plurality of nonvolatile memory devices NVM500a,500b, . . . ,500k. Each of the plurality of nonvolatile memory devices500a,500b, . . . ,500kmay be connected to the storage controller300through a respective one of a plurality of channels CHa, CHb, . . . , CHk. Here, k is an integer greater than two.

Each of the plurality of nonvolatile memory devices500a,500b, . . . ,500kmay operate under control of the storage controller300. Each of the plurality of nonvolatile memory devices500a,500b, . . . ,500kmay be a NAND flash memory device, however, the present disclosure is not limited thereto.

The storage controller300may include a temperature sensor370and a transmission (TX) driver470.

The temperature sensor370may sense an operating temperature of the storage device200and may generate temperature signal (temperature information) based on the sensed operating temperature.

The transmission driver470may adjust an eye height of a transmission signal transmitted to the host100by adjusting a transmission impedance (impedance) based on the temperature signal. The transmission driver470may increase the eye height of the transmission signal transmitted to the host100in response to an increase of the operating temperature, thereby to enhance reliability of the link30. Therefore, the storage controller200may adaptively adjust the impedance of the transmission driver470that transmits the transmission signal to the host100through the link30based on a change of an operating temperature of the storage device200. The storage controller200may decrease the impedance of the transmission driver470in response to an increase of the operating temperature such that the eye height of the transmission signal is increased.

In example embodiment, the link30may be according to PCIe standards.

Hereinafter, example embodiments are described based on relationship between one host and one storage device and it will be understood that example embodiment may be applied to multiple transceiver devices performing a bi-directional communication as illustrated inFIG.1.

FIG.2is a block diagram illustrating an example of the host in the storage system ofFIG.1according to example embodiments.

Referring toFIG.2, the host100may include a processor110, a HMB120, a root complex150, a user interface160and a storage interface circuit170connected to each other through a bus105.

The bus105may refer to a transmission channel via which data is transmitted between the processor110, the HMB120, the root complex150, the user interface160and the storage interface170of the host100.

The processor100may include a CPU core11and a cache115. The processor110may output a command may receive a completion information associated with completion of processing of the command.

The HMB120may include a command buffer130and a DMA buffer140. The command buffer130may include the submission queue131and the completion queue133. The DMA buffer140may include data that is processed based on a DMA transmission. The DMA transmission may be associated with transmitting data based on the DMA without intervention of the CPU core111.

The user interface160may be a physical or virtual medium for exchanging information between a user and the host100, a computer program, etc., and includes physical hardware and logical software. The storage interface circuit170may be configured to communicate with the storage device200. The storage interface circuit170may include a transmitter and a receiver.

FIG.3is a block diagram illustrating an example of the storage controller in the storage system ofFIG.1according to example embodiments.

Referring toFIG.3, the storage controller300may include a processor310, an SRAM315, a ROM320, an error correction code (ECC) engine325, a host interface circuit400, a command manager340, a DMA engine350, a memory interface circuit360which are connected via a bus305. The storage controller300may further include the temperature sensor370, a temperature monitor380and a transmission (TX) impedance controller390.

The processor310controls an overall operation of the storage controller300. The SRAM315may store various application programs that are executable by the processor310. The SRAM315may operate as a buffer memory, a cache memory or a working memory of the processor310. The ECC engine325may detect and/or correct errors which occur in the data read from the plurality of nonvolatile memory devices500a,500b, . . . ,500k.

The command manager340may manage the command received from the host100. The DMA engine350may control a DMA operation on the command output from the host100.

In example embodiments, the command manager340and the DMA engine350may be implemented in the form of software, hardware, or a combination thereof. The ROM320may store operating method of the command manager340and operating method of the DMA engine350. The processor310may control the command manager340and the DMA engine350.

The storage controller300may communicate with the host100through the host interface circuit400. For example, the host interface circuit400may be configured to communicate with the host100according to the DMA transmission. The host interface circuit400may include a transmission (TX) driver470.

The storage controller300may communicate with the plurality of nonvolatile memory devices500a,500b, . . . ,500kthrough the memory interface circuit360. For example, the memory interface circuit360may be configured to communicate with the plurality of nonvolatile memory devices500a,500b, . . . ,500kaccording to the DMA transmission.

The temperature sensor370may sense an operating temperature of the storage device200and may generate a temperature signal TS corresponding to the sensed operating temperature. The temperature monitor380may monitor the operating temperature of the storage device200based on the temperature signal TS and may generate an alert signal ALRT in response to the operation temperature exceeding at least one threshold value. The alert signal ALRT may include a plurality of bits.

The transmission impedance controller390may generate an impedance control code ICCD for adjusting the impedance of the transmission driver470based on the alert signal ALRT. The transmission driver470may adjust the impedance in response to the impedance control code ICCD to adjust an eye height of the transmission signal.

The temperature monitor380may compare the operating temperature with the at least one threshold value based on the temperature signal TS and may change of a state of the plurality of bits of the alert signal ALRT based on a result of the comparison. For example, the temperature monitor380may set the plurality of bits of the alert signal ALRT to have a first state in response to the operating temperature being equal to or smaller than a first threshold value of the at least one threshold value, may set the plurality of bits of the alert signal ALRT to have a second state different from the first state in response to the operating temperature exceeding the first threshold value, and may set the plurality of bits of the alert signal ALRT to have a third state different from the second state and the first state in response to the operating temperature exceeding a second threshold value greater than the first threshold value of the at least one threshold value.

The transmission impedance controller470may generate the impedance control code ICCD to have a first impedance value in response to the alert signal ALRT having the first state, may generate the impedance control code ICCD to have a second impedance value smaller than the first impedance value in response to the alert signal ALRT having the second state, and may generate the impedance control code ICCD to have a third impedance value smaller than the second impedance value in response to the alert signal ALRT having the third state.

As will be described later, the transmission impedance controller470may store a table or a firmware that stores the first state, the second state and the third state of the alert signal ALRT and values of the impedance control code ICCD corresponding to the first state, the second state and the third state.

FIG.4Ais a block diagram illustrating an example of the command manager in the storage controller ofFIG.3according to example embodiments.

Referring toFIG.4A, the command manager340may include a control register block341, a main control block342, a completion block343, a command fetch block344, a command parser345and an interrupt generator346.

The control register block341may be configured to include a register capable of being set by the host100or to process one or a series of operations for recognizing a register value set by the host100. For example, the control register block341may include various registers for determining information provided from the host100. The host100may notify the command manager340of various information by setting a register value of the control register block341.

The command fetch block344may perform or process one or a series of operations for fetching a command stored in the submission queue131of the host100. For example, the command fetch block344may transmit a memory read request to the host100and may receive a command stored in the submission queue131from the host100.

The main control block342may control overall operations of the command manager340or may process one or a series of operations to be performed in the command manager340.

The command parser345may parse the command from the host100and may provide the parsed command to at least one of the plurality of nonvolatile memory devices NVM500a,500b, . . . ,500kthrough the memory interface circuit380.

The completion block343may process one or a series of operations of writing completion information indicating that an operation is completed, to the completion queue133of the host100. For example, when an operation associated with a command fetched from the host100is completed, the completion block343may write the completion information indicating that the operation is completed, to the completion queue133of the host100.

The interrupt generator346may process one or a series of operations of providing an interrupt signal to the host100. For example, after the completion block343writes the completion information to the completion queue133, the interrupt generator346may notify the host100that the completion information is written to the completion queue133, by providing the interrupt signal to the host100. In an embodiment, the interrupt signal may be provided in a signaling manner such as pin-based interrupt, message signaled interrupts (MSI), MSI-X, etc.

FIG.4Bis a block diagram illustrating an example of the temperature monitor in the storage controller ofFIG.3according to example embodiments.

Referring toFIG.4B, the temperature monitor380may include a first comparator381, a second comparator383and an alert signal generator385.

The first comparator381may compare the temperature signal TS indicating the operating temperature with a first threshold value TV1and may output a first comparison signal CS1based on a result of the comparison. The second comparator383may compare the temperature signal TS indicating the operating temperature with a second threshold value TV2and may output a second comparison signal CS2based on a result of the comparison.

The alert signal generator385may receive the first comparison signal CS1and the second comparison signal CS2, may determine a state of the plurality of bits of the alert signal ALRT based on logic levels of the first comparison signal CS1and the second comparison signal CS2and may output the alert signal ALRT.

For example, when the alert signal ALRT includes two bits and the first comparison signal CS1and the second comparison signal CS2indicate that the operating temperature is equal to or smaller than the first threshold value TV1, the alert signal generator385may generate the alert signal ALRT having a first state of ‘00’. For example, when the first comparison signal CS1and the second comparison signal CS2indicate that the operating temperature exceeds the first threshold value TV1and is equal to or smaller than the second threshold value TV2, the alert signal generator385may generate the alert signal ALRT having a second state of ‘01’. For example, when the first comparison signal CS1and the second comparison signal CS2indicate that the operating temperature exceeds the second threshold value TV2, the alert signal generator385may generate the alert signal ALRT having a third state of ‘11’.

FIG.5is a block diagram illustrating an example of the host interface circuit in the storage controller ofFIG.3according to example embodiments.

Referring toFIG.5, the host interface circuit400may include a receiver410, a transmitter440, a locking circuit490and a clock multiplier495.

The locking circuit490may receive a reference clock signal CREF from the host100and may output an internal reference clock signal iCREF synchronized with the reference clock signal CREF. For example, the locking circuit490may include a delay locked loop or a phase locked loop.

The clock multiplier495may receive the internal reference clock signal iCREF from the locking circuit490. The clock multiplier495may generate a first clock signal CLK1and a second clock signal CLK2through frequency multiplication of the internal reference clock signal iCREF.

The receiver410may include an amplifier AMP415, a reception (RX) equalizer420, a deserializer425, a decoder430and a receiver logic435. The transmitter440may include a transmitter logic445, an encoder450, a serializer460, a transmission (TX) equalizer465and the transmission driver470.

The amplifier415may receive a signal RXS from the host100through the link30. The signal RXS received by the amplifier415may be a signal of a first type (e.g., a serial type). The signal RXS received by the amplifier415may be a portion of a packet or a portion of a symbol. The amplifier415may amplify the received signal RXS and may provide an amplified signal AMS to the reception equalizer420.

The reception equalizer420may receive the amplified signal AMS, may generate an equalized signal REQ by performing an equalization on the amplified signal AMS for compensating for distortion generated in the signal RXS in the link30and may provide the equalized signal REQ to the deserializer415. The deserializer415may deserialize (or, parallelize) the equalized signal REQ based on the first clock signal CLK1to generate with a deserialized signal DSER of a second type (e.g., a parallel type), and may provide the deserialized signal DSER to the decoder430.

The decoder430may perform decoding on the deserialized signal DSER to generate a decoded signal DES For example, the decoder430may perform symbol decoding to extract bits from a symbol. The decoder430may extract 8-bit data from a 10-bit symbol. Alternatively, the decoder430may extract 128-bit data from a 130-bit symbol. The decoder430may provide the decoded signal DES to the receiver logic435.

The receiver logic435may perform pattern check on the decoded signal DES to determine compliance. For example, the receiver logic435may determine whether the decoded signal coincides with a communication protocol (e.g., a PCIe); when the decoded signal coincides with the communication protocol (e.g., a PCIe), the receiver logic435may determine which generation corresponds to a generation of the communication protocol coinciding with the decoded signal. When the pattern check is successful, the receiver logic435may provide the decoded signal DES to the processor310through the bus305.

The transmitter logic445may receive a signal of the second type (e.g., a parallel type) from the processor310through the bus305. The transmitter logic445may combine the signal of the second type and a pattern. For example, the pattern may indicate which generation corresponds to the communication protocol (e.g., a PCIe). The transmitter logic445may provide a combined signal TXD to the encoder450.

The encoder450may perform encoding on the combined signal TXD to generate an encoded signal ENS. For example, the encoder450may perform symbol encoding to generate a symbol from bits of the combined signal. The encoder450may generate a 10-bit symbol from 8-bit data. Alternatively, the encoder450may generate a 130-bit symbol from 128-bit data. The encoder450may provide the encoded signal to the serializer460.

The serializer460may generate a serialized signal SER of the first type (e.g., a serial type) by performing serialization on the encoded signal ENS based on the second clock signal CLK2and may provide the serialized signal SER to the transmission equalizer465. The transmission equalizer465may generate an equalized signal TEQ by performing an equalization on the serialized signal SER for compensating for distortion that may occur in the signal in the link30and may provide the equalized signal TEQ to the transmission driver470. As will be described later, the transmission equalizer465may include a finite impulse response (FIR) filter and the FIR filter may generate the equalized signal TEQ by performing arithmetic operation on a symbol sequence extracted from the serialized signal SER and a filter coefficient sequence. The transmission equalizer465may provide the equalized signal TEQ to the transmission driver470.

The transmission driver470may amplify the equalized signal TEQ to generate a transmission signal TXS and may transmit the transmission signal TXS to the host100through the link30. When the transmission driver470amplifies the equalized signal TEQ, the transmission driver470may increase an eye height of the transmission signal TXS by reducing (decreasing) an impedance of the transmission driver470based on the impedance control code ICCD as the operating temperature increases.

FIGS.6A and6Bare diagrams illustrating examples of an interconnect architecture applied to a system according to example embodiments.

Referring toFIGS.6A and6B, an embodiment of a layered protocol stack is illustrated. A layered protocol stack includes any form of a layered communication stack, such as a Quick Path Interconnect (QPI) stack, a PCIe stack, a next generation high performance computing interconnect stack, or other layered stack. Although example embodiments are in relation to a PCIe stack, the same concepts may be applied to other interconnect stacks. In one embodiment, the protocol stack is a PCIe protocol stack including a transaction layer, a data link layer, and a physical layer.

The PCI Express uses packets to communicate information between components. The packets are formed in the transaction layer and the data Link Layer to carry the information from the transmitting component to the receiving component. As the transmitted packets flow through the other layers, they are extended with additional information necessary to handle packets at those layers. At the receiving side the reverse process occurs and packets get transformed from their physical layer representation to the data link layer representation and finally (for transaction layer packets) to the form that may be processed by the transaction layer of the receiving device.

In one embodiment, the transaction layer is to provide an interface between a device's processing core and the interconnect architecture, such as the data link layer and the physical layer. In this regard, a primary responsibility of the transaction layer is the assembly and disassembly of packets (i.e., the transaction layer packets, or TLPs). The translation layer typically manages credit-based flow control for TLPs. The PCIe implements split transactions, i.e. transactions with request and response separated by time, allowing a link to carry other traffic while the target device gathers data for the response.

In one embodiment, the transaction layer assembles packet header/payload. The payload may include data and an error detection code, i.e. ECRC. Format for current packet headers/payloads may be found in the PCIe specification at the PCIe specification website.

The link layer, also referred to as the data link layer, acts as an intermediate stage between the transaction layer and the physical layer or the PHY layer. In one embodiment, a responsibility of the data link layer is providing a reliable mechanism for exchanging the transaction layer packets (TLPs) between two components100(HOST) and200(STORAGE DEVICE) through a link. One side of the data link layer accepts TLPs assembled by the transaction layer, applies packet sequence identifier, i.e. a sequence number, an identification number or a packet number, calculates and applies an error detection code, i.e. LCRC, and submits the modified TLPs to the physical layer for transmission across a physical to an external device.

In one embodiment, the physical layer includes a logical sub block and an electrical sub-block to physically transmit a packet to an external device. Here, the logical sub-block is responsible for the “digital” functions of the physical layer. In this regard, the logical sub-block includes a transmitter section to prepare outgoing information for transmission by the physical sub-block, and a receiver section to identify and prepare received information before passing it to the link layer.

The physical block includes a transmitter TX and a receiver RX. The transmitter TX is supplied by the logical sub-block with symbols, which the transmitter serializes and transmits onto to an external device. The receiver RX is supplied with serialized symbols from an external device and transforms the received signals into a bit-stream. The bit-stream is de-serialized and supplied to the logical sub-block. In one embodiment, an 8b/10b transmission code is employed, where ten-bit symbols are transmitted/received. Here, special symbols are used to frame a packet with frames. In addition, in one example, the receiver RX also provides a symbol clock recovered from the incoming serial stream.

As stated above, although the transaction layer, the link layer, and physical layer are discussed in reference to a specific embodiment of a PCIe protocol stack, a layered protocol stack is not so limited. In fact, any layered protocol may be included/implemented.

FIG.7illustrates an example of a register of the storage controller ofFIG.3.

The register illustrated inFIG.7may be, for example, a link control register for a control of the link30.

Referring toFIGS.3and7, a 0-th bit and a first bit of the register may be used for active state power management (ASPM) control. A third bit of the register may be used for read completion boundary. A fourth bit of the register may be used for link disable. A fifth bit of the register may be used to retrain the link30. A retrain may refer to redoing some parts of a transmitter equalization process of the link30.

A sixth bit of the register may be used for common clock configuration. A seventh bit of the register may be used for extended synch. An eighth bit of the register may be used to enable clock power management. A ninth bit of the register may be used for hardware autonomous width disable.

A tenth bit of the register may be used for a link bandwidth management interrupt enable. An eleventh bit of the register may be used for a link autonomous bandwidth interrupt enable. A fourteenth bit and a fifteenth bit of the register may be used for device readiness status (DRS) signaling control.

A second bit, a twelfth bit, and a thirteenth bit of the register may be used for dynamic link control.

For example, the host100may perform polling to read the register periodically. After reading the register, the host100and the storage device200may decrease multiplication ratios through the retrain operation.

FIG.8Aillustrates a process in which the storage device establishes the link with the host.

Referring toFIGS.1and8A, an initial state may be a detect state. In the detect state, when a connection with any other device (e.g., the host device100) is detected, the storage device200may enter a polling state.

In the polling state, a generation version of a protocol (e.g., a PCIe) of the host100and a generation version of a protocol (e.g., a PCIe) of the storage device200may be checked, and a data transfer rate may be determined based on the highest generation version compatible with each other. Also, in the polling state, the storage controller300may set a bit lock, a symbol lock, a block lock, and a lane polarity. In the polling state, the storage controller300may transmit TS1and TS2being an ordered set at a transmission rate of 2.5 GT/s (gigatransfers per second). A transfer may refer to one data transfer event in a given data-transfer channel.

After the polling state, the storage device200may enter a configuration state. In the configuration state, the storage controller300may set the number of lanes of the link30, that is, a link width. Also, in the configuration state, the storage controller300may exchange TS1and TS2with the host device100at a transmission rate of 2.5 GT/s. The storage controller300may allocate a lane number and may check and calibrate a lane reversal. The storage controller300may de-skew a lane-to-lane timing difference (reduce a time skew between lanes).

After the configuration state, the storage controller300may enter an L0 state. The L0 state may be a normal state. In the L0 state, the storage controller300may communicate with the host100through the link30.

An L0s state may be an ASPM state. The storage controller300may reduce power consumption in the L0s state until the storage controller300enters the L0 state. An L1 state may be a power saving state in which power consumption is reduced more than in the L0s state. In an L2 state, a voltage low enough to detect a wake-up event may be used.

Entering a disabled state may be made when the storage controller300disables the link30. A loopback state may be a state that the storage controller300uses for test and fault isolation. A hot reset state may be used when the storage controller300resets the link30through in-band signaling.

A recovery state may be used for the storage controller300to adjust a data transfer rate. For example, in the recovery state, the storage controller300may adjust the frequency multiplication ratios of a clock multiplier of the host100and the clock multiplier495of the storage device200.

For example, by setting the dynamic link control bit of the link control register in the L0 state and requesting the retrain operation, the storage controller300may adjust the frequency multiplication ratios of the clock multiplier of the host device100and the clock multiplier495of the storage device200.

As the retrain operation is requested, the storage controller300may enter the recovery state and may adjust the frequency multiplication ratios of the clock multiplier of the host100and the clock multiplier495of the storage device200. Afterwards, the storage controller300may return to the L0 state, may return to the configuration state, or may return to the detect state. Alternatively, the storage controller300may return to the detect state through the hot reset state.

FIG.8Billustrates an example of the link established between the storage circuit of the host and the host interface circuit of the storage device.

Referring toFIGS.1,2,3, and8B, the link30may include at least one lane LANE.

For example, the link30may include lanes LANE, the number of lanes corresponds to a number selected from numbers of 1, 2, 4, 8, and 16. In an example embodiment, it is assumed that four lanes LANE are included in the link30. The lanes LANE may transmit or receive signals at the same time. The lanes LANE may correspond to parallel signal lines. For example, each lane may contain two pairs of wires, one pair to send and one pair to receive. A link including one lane is thus made up of four wires. The lanes LANE may be set to have the same link speed.

A data transfer rate of the link30may be determined by a product of the number of lanes LANE included in the link30, that is, a link width and a link speed of each of the lanes LANE. To adjust a data transfer rate of the link30, the storage device200according to an example embodiment may adjust a link width, that is, the number of lanes LANE included in the link30.

Each of the lanes LANE may include a transmit channel and a receive channel. The transmit channel of the host interface circuit400may correspond to a dotted arrow facing toward the storage interface circuit170from the host interface circuit400. The receive channel of the host interface circuit400may correspond to a dotted arrow facing toward the host interface circuit400from the storage interface circuit170.

FIG.9illustrates an example of the transmission equalizer in the host interface circuit ofFIG.5according to example embodiments.

Referring toFIG.9, the transmission equalizer465may be implemented with an FIR filter and may generate the equalized signal TEQ from the serialized signal SER. In the example ofFIG.9, the transmission equalizer465may include two delayers D1and D2, three multipliers M1, M2and M3and two adders A1and A2and may operate as a 3-tap feed forward equalizer (FFE).

The transmission equalizer465may calculate the symbol sequence in the serialized data SER and a filter coefficient sequence including the filter coefficients of the FIR filter. For example, as shown inFIG.9, the symbol sequence may include three symbols S1, S2and S3corresponding to three filter coefficients C1, C2, and C3of the filter coefficient sequence, respectively. The three symbols S1, S2and S3may be multiplied with the three filter coefficients C1, C2, and C3respectively, and the multiplication results may be summed.

As such, as illustrated inFIG.9, the serialized data SER including symbols corresponding to the predetermined levels may be equalized as the equalized signal TEQ including a waveform modified according to the characteristics of the bus305.

FIG.10is a circuit diagram illustrating an example of the transmission driver in the host interface circuit ofFIG.5according to example embodiments.

Referring toFIG.10, the transmission driver470may include a plurality of driver segments470a,470band470c.

The plurality of driver segments470a,470band470cmay be connected in parallel between a power supply voltage VDD and a ground voltage VSS and may receive a first sub equalization signal TEQ_P and a second sub equalization signal TEQ_S commonly from the transmission equalizer465.

The transmission driver470may adjust the impedance by adjusting a number of driver segments, which are enabled, from among the plurality of driver segments470a,470band470c, in response to the impedance control code ICCD. The transmission driver470may increase a number of driver segments which are enabled, from among the plurality of driver segments470a,470band470cbased on an increase of the operating temperature.

InFIG.10, a configuration of the driver segment470afrom among the plurality of driver segments470a,470band470cand each configuration of the driver segments470band470cmay be substantially the same as the configuration of the driver segment470a. In addition, it is assumed that the equalized signal TEQ inFIG.10is a differential signal.

The driver segment470amay include a p-channel metal-oxide semiconductor (PMOS) transistor471and first through fifth n-channel metal-oxide semiconductor (NMOS) transistors472,473,474,475and476.

The PMOS transistor471may be connected between the power supply voltage VDD and a first node N11and have a gate to receive a corresponding bit PUCD1of a pull-up control code PUCD of the impedance control code ICCD.

The first NMOS transistor472may be transistor connected between connected between the first node N11and a second node N12and have a gate to receive the first sub equalized signal TEQ_P. The second NMOS transistor473may be connected between the first node N11and a third node N13in parallel with the first NMOS472transistor and have a gate to receive the second sub equalized signal TEQ_S. The third NMOS transistor474may be connected between the second node N12and a fourth node N14and have a gate to receive the second sub equalized signal TEQ_S. The fourth NMOS transistor475may be connected between the third node N13and the fourth node N14in parallel with the third NMOS transistor474and have a gate to receive the first sub equalized signal TEQ_P.

The fifth NMOS transistor476may be connected between the fourth node N14and the ground voltage VSS and have a gate to receive a corresponding bit PDCD1of a pull-down control code PDCD of the impedance control code ICCD.

A first component TXS_P of the transmission signal TXS is provided to a first transmission pad TXPD at the second node N12and the first component TXS_P is transmitted to the host100through the link30and the second component TXS_N of the transmission signal TXS is provided to a second transmission pad TXND at the third node N13and the second component TXS_N is transmitted to the host100through the link30.

When the driver segment470ais enabled from among the plurality of driver segments470a,470band470cin response to the pull-up control code PUCD and the pull-down control code PDCD of the impedance control code ICCD, the transmission driver470may provide the impedance having a first impedance value provided by connecting the PMOS transistor471and the first through fifth NMOS transistors472,473,474,475and476.

When the driver segments470aand470bare enabled from among the plurality of driver segments470a,470band470cin response to the pull-up control code PUCD and the pull-down control code PDCD of the impedance control code ICCD, the transmission driver470may provide the impedance having a second impedance value provided by connecting the PMOS transistor471and the first through fifth NMOS transistors472,473,474,475and476. The second impedance value may correspond to two parallel connected impedances having first impedance value.

When the driver segments470a,470band470care enabled in response to the pull-up control code PUCD and the pull-down control code PDCD of the impedance control code ICCD, the transmission driver470may provide the impedance having a third impedance value provided by connecting the PMOS transistor471and the first through fifth NMOS transistors472,473,474,475and476. The third impedance value may correspond to three parallel connected impedances having first impedance value.

Therefore, the transmission driver470may reduce the impedance by adjusting a number of driver segments, which are enabled, from among the plurality of driver segments470a,470band470c, as the operating temperature increases.

FIG.11is a graph illustrating an eye height of a transmission signal received at the host depending on the operating temperature of the storage device.

Referring toFIG.11, it is noted that an eye height of the transmission signal TXS received at the host100decreases as the operating temperature of the storage device200increases. The eye height of the transmission signal TXS received at the host100decreases because electronics in a path between the storage device200and the host move actively and possibility of the transmission signal TXS colliding with the electronics as the operating temperature of the storage device200increases.

Therefore, when the storage controller300maintains the impedance of the transmission driver470as the operating temperature of the storage device200increases, the eye height of the transmission signal TXS may be decreased and thus, reliability of the link30may be reduced.

FIG.12is a table illustrating relationship between impedance of the transmission driver of the host interface circuit ofFIG.5and the eye height of the transmission signal received at the host.

Referring toFIG.12, when the impedance of the transmission driver470has a first impedance value IMP11, a second impedance value IMP12and a third impedance value IMP13, respectively, eye height of the transmission signal TXS received at the host100has a first eye height EH11, a second eye height EH12and a third eye height EH13.

The first impedance value IMP11is greater than the second impedance value IMP12and the second impedance value IMP12is greater than the third impedance value IMP13. The second eye height EH12is greater than the first eye height EH11and the third eye height EH13is greater the second eye height EH12. That is, the eye height of the transmission signal TXS received at the host100increases as the impedance of the transmission driver470decreases.

FIG.13is a table illustrating relationship between state of the alert signal and impedance of the transmission driver depending on the operating temperature in the storage device according to example embodiments.

Referring toFIGS.3,4B,10and13, when the operating temperature of the storage device200is equal to or greater than a first temperature TEMP1and is smaller than a second temperature TEMP2, the temperature monitor380provides the transmission impedance controller390with the alert signal ALRT having a first state of ‘00’, and the transmission impedance controller390applies the impedance control code ICCD in response to the alert signal ALRT having the first state such that the impedance of the transmission driver470has a first impedance value IMP21. In this case, the eye height of the transmission signal TXS received at the host100has a first eye height.

The first impedance value IMP21may be is determined based on a transmission preset value and a coefficient value optimized for a third phase of equalization process of a PCIe link training between the host100and the storage controller300.

When the operating temperature of the storage device200arrives at the second temperature TEMP2corresponding to the first threshold value TV1, the temperature monitor380provides the transmission impedance controller390with the alert signal ALRT having a second state of ‘01’, and the transmission impedance controller390applies the impedance control code ICCD in response to the alert signal ALRT having the second state such that the impedance of the transmission driver470has a second impedance value IMP22smaller than the first impedance value IMP21. That is, when the operating temperature of the storage device200is equal to or greater than the second temperature TEMP2and is smaller than a third temperature TEMP3, the impedance of the transmission driver470has the second impedance value IMP22and the eye height of the transmission signal TXS received at the host100has a second eye height greater than the first eye height.

When the operating temperature of the storage device200arrives at the third temperature TEMP3corresponding to the second threshold value TV2, the temperature monitor380provides the transmission impedance controller390with the alert signal ALRT having a third state of ‘11’, and the transmission impedance controller390applies the impedance control code ICCD in response to the alert signal ALRT having the third state such that the impedance of the transmission driver470has a third impedance value IMP23smaller than the second impedance value IMP22. That is, when the operating temperature of the storage device200is equal to or greater than the third temperature TEMP3, the impedance of the transmission driver470has the third impedance value IMP23and the eye height of the transmission signal TXS received at the host100has a third eye height greater than the second eye height.

FIGS.14A,14B and14Care eye diagrams of a transmission signal received at the host depending on the impedance of the transmission driver according to example embodiments.

InFIGS.14A,14B and14C, a horizontal axis denotes time and a vertical axis denotes a voltage level of the transmission signal TXS received at the host100.

FIG.14Aillustrates an eye diagram of the transmission signal TXS received at the host100when the impedance of the transmission driver470has the first impedance value IMP21. The transmission signal TXS has a first eye height EH21.

FIG.14Billustrates an eye diagram of the transmission signal TXS received at the host100when the impedance of the transmission driver470has the second impedance value IMP22. The transmission signal TXS has a second eye height EH22greater than the first eye height EH21.

FIG.14Cillustrates an eye diagram of the transmission signal TXS received at the host100when the impedance of the transmission driver470has the third impedance value IMP23. The transmission signal TXS has a third eye height EH23greater than the second eye height EH22.

FIG.15is a flow chart illustrating a method of operating a storage device according to example embodiments.

Referring toFIGS.1through15, a power is applied to the storage system50(operation S110). That is, the storage system50is powered on. The link30is established between the host100and the storage device200(operation S115) and the storage device200starts normal operation. The temperature monitor380in the storage controller300performs temperature monitoring based on the temperature signal TS from the temperature sensor370(operation S120) and determines whether the operating temperature exceeds at least one threshold value (operation S130).

When operating temperature does not exceed the at least one threshold value (NO in operation S130), the temperature monitor380monitors the operating temperature while providing the transmission impedance controller390with the alert signal ALRT having a first state.

When the operating temperature exceeds the at least one threshold value (YES in operation S130), the temperature monitor380provides the transmission impedance controller390with the alert signal ALRT having a second state different from the first state (operation S140) and notifies the transmission impedance controller390of the operating temperature exceeding the at least one threshold value.

The transmission impedance controller390adjusts the impedance of the transmission driver470by applying the impedance control code ICCD to the transmission driver470(operation S150). The transmission driver470drives the transmission signal TXS based on the adjusted impedance value to increase an eye height of the transmission signal TXS (operation S160).

Therefore, the storage device and the method of operating a storage device according to example embodiments, may increase an eye height of the transmission signal transmitted to the host through the link by decreasing impedance of the transmission driver as the operating temperature increases. Therefore, the storage device and the method of operating a storage device according to example embodiments may maintain reliability of the link30even though the operating temperature of the storage device200increases.

FIG.16is a block diagram illustrating an example of one of the plurality of nonvolatile memory devices in the storage system ofFIG.1according to some example embodiments.

InFIG.16, a configuration of the nonvolatile memory device500ais illustrated and each configuration of the nonvolatile memory devices500b, . . . ,500kmay be substantially the same as the configuration of the nonvolatile memory device500a.

Referring toFIG.16, the nonvolatile memory device500amay include a memory cell array520, an address decoder550, a page buffer circuit530, a data input/output (I/O) circuit540, a control circuit560, and a voltage generator570.

The memory cell array520may be coupled to the address decoder550through a string selection line SSL, a plurality of word-lines WLs, and a ground selection line GSL. In addition, the memory cell array520may be coupled to the page buffer circuit530through a plurality of bit-lines BLs.

The memory cell array520may include a plurality of memory cells coupled to the plurality of word-lines WLs and the plurality of bit-lines BLs.

In some example embodiments, the memory cell array520may be or include a three-dimensional memory cell array, which is formed on a substrate in a three-dimensional structure (e.g., a vertical structure). In this case, the memory cell array520may include vertical cell strings that are vertically oriented such that at least one memory cell is located over another memory cell.

FIG.17is a block diagram illustrating the memory cell array in the nonvolatile memory device ofFIG.16.

Referring toFIG.17, the memory cell array520may include a plurality of memory blocks BLK1to BLKz. Here, z may be an integer greater than two. The memory blocks BLK1to BLKz extend along a first horizontal direction HD1, a second horizontal direction HD2and a vertical direction VD. In some example embodiments, the memory blocks BLK1to BLKz are selected by the address decoder550inFIG.16. For example, the address decoder550may select a memory block BLK corresponding to a block address among the memory blocks BLK1to BLKz.

FIG.18is a circuit diagram illustrating one of the memory blocks ofFIG.17.

The memory block BLKi ofFIG.18may be formed on a substrate SUB in a three-dimensional structure (or a vertical structure). For example, a plurality of memory cell strings included in the memory block BLKi may be formed in the direction VD perpendicular to the substrate SUB.

Referring toFIG.18, the memory block BLKi may include memory cell strings NS11to NS33coupled between bit-lines BL1, BL2and BL3and a common source line CSL. Each of the memory cell strings NS11to NS33may include a string selection transistor SST, a plurality of memory cells MC1to MC8, and a ground selection transistor GST. InFIG.18, each of the memory cell strings NS11to NS33is illustrated to include eight memory cells MC1to MC8. However, present disclosures are not limited thereto. In some example embodiments, each of the memory cell strings NS11to NS33may include any number of memory cells.

The string selection transistor SST may be connected to corresponding string selection lines SSL1to SSL3. The plurality of memory cells MC1to MC8may be connected to corresponding word-lines WL1to WL8, respectively. The ground selection transistor GST may be connected to corresponding ground selection lines GSL1to GSL3. The string selection transistor SST may be connected to corresponding bit-lines BL1, BL2and BL3, and the ground selection transistor GST may be connected to the common source line CSL.

Word-lines (e.g., WL1) having the same height may be commonly connected, and the ground selection lines GSL1to GSL3and the string selection lines SSL1to SSL3may be separated. InFIG.18, the memory block BLKi is illustrated to be coupled to eight word-lines WL1to WL8and three bit-lines BL1to BL3. However, present disclosures are not limited thereto. In some example embodiments, the memory cell array520may be coupled to any number of word-lines and bit-lines.

FIG.19illustrates an example of a structure of a cell string CS in the memory block ofFIG.18.

Referring toFIGS.18and19, a pillar PL is provided on the substrate SUB such that the pillar PL extends in a direction perpendicular to the substrate SUB to make contact with the substrate SUB. Each of the ground selection line GSL, the word lines WL1to WL8, and the string selection lines SSL illustrated inFIG.18may be formed of a conductive material parallel with the substrate SUB, for example, a metallic material. The pillar PL may be in contact with the substrate SUB through the conductive materials forming the string selection lines SSL, the word lines WL1to WL8, and the ground selection line GSL.

A sectional view taken along a line V-V′ is also illustrated inFIG.19. In some example embodiments, a sectional view of a first memory cell MC1corresponding to a first word line WL1is illustrated. The pillar PL may include a cylindrical body BD. An air gap AG may be defined in the interior of the body BD.

The body BD may include P-type silicon and may be an area where a channel will be formed. The pillar PL may further include a cylindrical tunnel insulating layer TI surrounding the body BD and a cylindrical charge trap layer CT surrounding the tunnel insulating layer TI. A blocking insulating layer BI may be provided between the first word line WL and the pillar PL. The body BD, the tunnel insulating layer TI, the charge trap layer CT, the blocking insulating layer BI, and the first word line WL may constitute or be included in a charge trap type transistor that is formed in a direction perpendicular to the substrate SUB or to an upper surface of the substrate SUB. A string selection transistor SST, a ground selection transistor GST, and other memory cells may have the same structure as the first memory cell MC1.

Referring back toFIG.16, the control circuit560may receive the command (signal) CMD and the address (signal) ADDR from the storage controller300, and may control an erase loop, a program loop and/or a read operation of the nonvolatile memory device500abased on the command signal CMD and the address signal ADDR. The program loop may include a program operation and a program verification operation. The erase loop may include an erase operation and an erase verification operation.

For example, the control circuit560may generate control signals CTLs, which are used for controlling the voltage generator570, based on the command signal CMD, and generate a row address R_ADDR and a column address C_ADDR based on the address signal ADDR. The control circuit560may provide the row address R_ADDR to the address decoder550and may provide the column address C_ADDR to the data I/O circuit540.

The address decoder550may be coupled to the memory cell array520through the string selection line SSL, the plurality of word-lines WLs, and the ground selection line GSL. During the program operation or the read operation, the address decoder550may determine one of the plurality of word-lines WLs as a first word-line (e.g., a selected word-line) and determine rest of the plurality of word-lines WLs except for the first word-line as unselected word-lines based on the row address R_ADDR.

The voltage generator570may generate word-line voltages VWLs, which are required for the operation of the nonvolatile memory device500a, based on the control signals CTLs. The voltage generator570may receive a power PWR1from the storage controller300. The word-line voltages VWLs may be applied to the plurality of word-lines WLs through the address decoder550.

For example, during the erase operation, the voltage generator570may apply an erase voltage to a well of the memory block and may apply a ground voltage to entire word-lines of the memory block. During the erase verification operation, the voltage generator570may apply an erase verification voltage to the entire word-lines of the memory block or sequentially apply the erase verification voltage to word-lines in a word-line basis.

For example, during the program operation, the voltage generator570may apply a program voltage to the first word-line and may apply a program pass voltage to the unselected word-lines. In addition, during the program verification operation, the voltage generator570may apply a program verification voltage to the first word-line and may apply a verification pass voltage to the unselected word-lines.

Furthermore, during the read operation, the voltage generator570may apply a read voltage to the first word-line and may apply a read pass voltage to the unselected word-lines.

The page buffer circuit530may be coupled to the memory cell array520through the plurality of bit-lines BLs. The page buffer circuit530may include a plurality of page buffers. In some example embodiments, one page buffer may be connected to one bit-line. In some example embodiments, one page buffer may be connected to two or more bit-lines.

The page buffer circuit530may temporarily store data to be programmed in a selected page or data read out from the selected page.

The data I/O circuit540may be coupled to the page buffer circuit430through data lines DLs. During the program operation, the data input/output circuit540may receive the data DTA from the storage controller300provide the data DTA to the page buffer circuit530based on the column address C_ADDR received from the control circuit560.

During the read operation, the data I/O circuit540may provide the data DTA which are stored in the page buffer circuit430, to the storage controller300based on the column address C_ADDR received from the control circuit560.

The control circuit560may control the page buffer circuit530and data I/O circuit540.

FIG.20is a block diagram illustrating an electronic device according to example embodiments. The electronic device600may correspond to a server.

Referring toFIG.20, the electronic device600may be, e.g., a server. The electronic device600may include a power supply610and a power receiver620. The power supply610may generate a power PWR from an external power, and may supply the generated power PWR to the power receiver620. The power PWR may be provided in the form of two or more different voltages.

The power receiver620may receive the power PWR from the power supply610, and may operate based on the power PWR. The power receiver620may include a baseboard630, a first solid state drive (SSD) backplane640, a second SSD backplane650, a third SSD backplane660, a cooling control board670, coolers680, and sensors690.

The baseboard630may include a first central processing unit (CPU)631, a second CPU632, first memories633and second memories634connected with the first CPU631, third memories635and fourth memories636connected with the second CPU632, and a baseboard management controller (BMC)637. The baseboard630may supply the power PWR received from the power supply610to the first CPU631, the second CPU632, the first memories633, the second memories634, the third memories635, and the fourth memories636.

The first CPU631may use the first memories633and the second memories634as working memories. The second CPU632may use the third memories635and the fourth memories636as working memories. The first CPU631and the second CPU632may execute an operating system and various applications. The first CPU631and the second CPU632may control components of the power receiver620. For example, the first CPU631and the second CPU632may control the components of the power receiver620based on PCIe.

The first CPU631and the second CPU632may access the first SSD backplane640, the second SSD backplane650, and the third SSD backplane660. For example, the first CPU631and the second CPU632may access the first SSD backplane640, the second SSD backplane650, and the third SSD backplane660based on nonvolatile memory express (NVMe). The first memories633, the second memories634, the third memories635, and the fourth memories636may include dual in-line memory module (DIMM) memories installed in DIMM slots.

The BMC637may be a separate system that is separate from an operating system of the first CPU631and the second CPU632. The BMC637may collect information from the components of the electronic device600, and may access the components. The BMC637may be based on a separate communication interface that is separate from communication interfaces (e.g., PCIe) of the first CPU631and the second CPU632. For example, the BMC637may be based on an intelligent platform management interface (IPMI). The communication interface of the BMC637may communicate with the communication interfaces of the first CPU631and the second CPU632.

The first SSD backplane640may receive the power PWR from the power supply610, may exchange signals SIG with the baseboard630, and may receive power signals PS from the baseboard630. The first SSD backplane640may exchange the signals SIG with the first CPU631, the second CPU632, or the BMC637of the baseboard630, and may receive the power signals PS therefrom. A plurality of SSDs may be installed in the first SSD backplane640. This may mean that the first SSD backplane640includes a plurality of SSDs.

The first CPU631and the second CPU632of the baseboard630may access (e.g., write, read, and erase) the SSDs of the first SSD backplane640through the signals SIG. The BMC637of the baseboard630may monitor the first SSD backplane640through the signals SIG, and may access and control the first SSD backplane640. The first CPU631, the second CPU632, or the BMC637of the baseboard630may power on or power off the first SSD backplane640by using the power signals PS.

Structures and operations of the second SSD backplane650and the third SSD backplane660may be the same as the structure and the operation of the first SSD backplane640. Thus, additional description will be omitted to avoid redundancy.

The baseboard630may power on and power off the first SSD backplane640, the second SSD backplane650, and the third SSD backplane660independently of each other. For example, services that are supported by using the first SSD backplane640, the second SSD backplane650, and the third SSD backplane660may be different. While the electronic device600does not provide a specific service, an SSD backplane corresponding to the specific service may be powered off, and the remaining SSD backplane(s) may be powered on.

For example, the frequencies of use of the services that are supported by using the first SSD backplane640, the second SSD backplane650, and the third SSD backplane660may be different for each time zone. In a time zone when the frequencies of use of the services that are supported by using the first SSD backplane640, the second SSD backplane650, and the third SSD backplane660are low, at least one of the first SSD backplane640, the second SSD backplane650, and the third SSD backplane660may be powered off.

The cooling control board670may receive the power PWR from the power supply610. The cooling control board670may control the coolers680under control of the baseboard630. For example, the cooling control board670may control the coolers680under control of the first CPU631, the second CPU632, or the BMC637of the baseboard630. The cooling control board670may control operation activation and deactivation of the coolers680and the intensity of cooling.

The coolers680may receive the power PWR from the power supply610. The coolers680may perform cooling under control of the cooling control board670such that a temperature of the electronic device600decreases. The coolers680may include fans, but embodiments are not limited thereto. The coolers680are not limited to the case where the coolers680are collectively disposed at one place. For example, the coolers680may be distributed and disposed at two or more places. A part of the coolers680may be attached to a chassis of the electronic device600and may inject an external air into the electronic device600. The rest of the coolers680may be disposed at a specific component and may take full charge of cooling of the specific component.

The sensors (SENS)690may receive the power PWR from the power supply610. The sensors690may be disposed adjacent to the components of the electronic device600. The sensors690may collect a variety of information under control of the baseboard630, and may provide the collected information to the baseboard630.

For example, the sensors690may collect information under control of the BMC637of the baseboard630, and may provide the collected information to the BMC637. The sensors690may provide the collected information to the BMC637through sensor data repository (SDR) of the IPMI. For example, different record IDs may be assigned to the sensors690. The sensors690may provide information to the BMC637based on different record IDs. The sensors690may include various sensors such as a temperature sensor, a humidity sensor, and a vibration sensor.

FIG.21illustrates an example in which SSDs are installed in the first SSD backplane, the second SSD backplane, and the third SSD backplane.

Referring toFIGS.20and21, to reduce the size of the electronic device600, SSDs may be closely installed in each of the first SSD backplane640, the second SSD backplane650, and the third SSD backplane660. Also, to reduce the size of the electronic device600, the first SSD backplane640, the second SSD backplane650, and the third SSD backplane660may be in close contact with each other. Each of the SSDs may correspond to the storage device200inFIG.1and each of SSDs may include a storage controller and a plurality of nonvolatile memory devices and may include a temperature sensor TPS.

When one of the first SSD backplane640, the second SSD backplane650, and the third SSD backplane660is in a power-off state, the remaining SSD backplanes may be in a power-on state. A temperature of the SSD backplane being in the power-off state may increase due to heat generated at the SSD backplanes being in the power-on state. A temperature of the SSD backplane being in the power-off state may increase due to heat convected by the coolers680.

When a temperature of the SSD backplane that is in the powered-off state increases, the increased temperature may accelerate a reduction of retention of the SSDs installed in the powered-off SSD backplane. The reduction of retention may be recovered by a retention recovery operation. However, the retention recovery operation is not performed when the SSD backplane is in the power-off state. Accordingly, due to the reduction of retention, a data loss may occur at the SSDs installed in the SSD backplane being in the power-off state.

As such, the electronic device600according to an example embodiment may power on at least one of SSDs installed in an SSD backplane that is in a power-off state in response to an increase in a temperature of the powered-off SSD backplane. The powered-on SSD(s) may perform the retention recovery operation to recover the reduction of retention. Accordingly, data can be prevented from being lost due to the reduction of retention accelerated by a high temperature at an SSD backplane being in a power-off state.

In addition, the operating temperature of the SSDs installed in each of the first SSD backplane640, the second SSD backplane650, and the third SSD backplane660may vary depending on distance from the coolers680, and thus, a characteristic of the signal SIG transmitted to the based board630may vary. Each of the SSDs installed in each of the first SSD backplane640, the second SSD backplane650, and the third SSD backplane660may include a temperature sensor, a temperature monitor and a transmission impedance controller. The transmission impedance controller adjusts impedance of a transmission driver by adjusting an impedance control code in response to the operating temperature of each of the SSDs exceeding at least one threshold value, and the transmission driver reduces impedance based on the adjusted impedance to increase an eye height of the signal SIG transmitted to the base board630. Therefore, when the operating temperature of the SSDs installed in each of the first SSD backplane640, the second SSD backplane650, and the third SSD backplane660may vary, the transmission impedance controller may individually adjust an impedance of the transmission driver and thus, may increase (or maintain) reliability of link established between each of the SSDs and the base board630.

FIG.22illustrates an example of an SSD backplane according to example embodiments.

An SSD backplane700may correspond to the first SSD backplane640, the second SSD backplane650, and the third SSD backplane660inFIG.21.

Referring toFIGS.20and22, the SSD backplane700may include first through fourth SSD slots711,712,713, and714. However, the number of slots is not limited. A respective SSD may be installed in each of the first SSD slot711, the second SSD slot712, the third SSD slot713, and the fourth SSD slot714. The SSDs may exchange the signals SIG with the baseboard630through signal lines.

The SSD backplane700may include first through fourth bi-metals721,722,723, and724respectively corresponding to the first through fourth SSD slots711,712,713, and714, and may include first through fourth regulators (REG)s731,732,733, and734respectively corresponding to the first through fourth SSD slots711,712,713, and714. Each of the first bi-metal721, the second bi-metal722, the third bi-metal723, and the fourth bi-metal724may include two separate materials (or metals) joined together and having different thermal expansion coefficients.

In response to an increase of temperature, a material having a greater thermal expansion coefficient may expand more than a material having a smaller thermal expansion coefficient. Accordingly, each of the first bi-metal721, the second bi-metal722, the third bi-metal723, and the fourth bi-metal724may be bent toward a material having a smaller thermal expansion coefficient upon heating. Conversely, in response to a decrease of temperature, a material having a greater thermal expansion coefficient may contract more than a material having a smaller thermal expansion coefficient. Accordingly, each of the first bi-metal721, the second bi-metal722, the third bi-metal723, and the fourth bi-metal724may be bent toward a material having a greater thermal expansion coefficient upon cooling.

Each of the first bi-metal721, the second bi-metal722, the third bi-metal723, and the fourth bi-metal724may be respectively disposed adjacent to the first SSD slot711, the second SSD slot712, the third SSD slot713, and the fourth SSD slot714, such that the first bi-metal721, the second bi-metal722, the third bi-metal723, and the fourth bi-metal724may be bent in response to temperatures of the first SSD slot711, the second SSD slot712, the third SSD slot713, and the fourth SSD slot714.

The first bi-metal721, the second bi-metal722, the third bi-metal723, and the fourth bi-metal724may respectively receive voltages from the first regulator731, the second regulator732, the third regulator733, and the fourth regulator734. In response to an increase of temperature, the first bi-metal721, the second bi-metal722, the third bi-metal723, and the fourth bi-metal724may be bent so as to be connected to (or spaced or disconnected from (e.g., the contacts may be normally open or normally closed, and appropriate logic may be implemented in accordance therewith)) terminals of the first regulator731, the second regulator732, the third regulator733, and the fourth regulator734. Accordingly, the first bi-metal721, the second bi-metal722, the third bi-metal723, and the fourth bi-metal724may return (or may not return) the voltages received from the first regulator731, the second regulator732, the third regulator733, and the fourth regulator734to the first regulator731, the second regulator732, the third regulator733, and the fourth regulator734.

Conversely, in response to a decrease of temperature, the first bi-metal721, the second bi-metal722, the third bi-metal723, and the fourth bi-metal724may be bent so as to be spaced from (or attached to) the terminals of the first regulator731, the second regulator732, the third regulator733, and the fourth regulator734. Accordingly, the first bi-metal721, the second bi-metal722, the third bi-metal723, and the fourth bi-metal724may not return (or may return) the voltages received from the first regulator731, the second regulator732, the third regulator733, and the fourth regulator734to the first regulator731, the second regulator732, the third regulator733, and the fourth regulator734.

The SSD backplane700may be powered on or powered off in response to the power signals PS from the baseboard630. When the SSD backplane700is powered on, the first regulator731, the second regulator732, the third regulator733, and the fourth regulator734may supply a power to the SSDs of the first SSD slot711, the second SSD slot712, the third SSD slot713, and the fourth SSD slot714. When the SSD backplane700is powered off, the first regulator731, the second regulator732, the third regulator733, and the fourth regulator734may block the power from being supplied to the SSDs of the first SSD slot711, the second SSD slot712, the third SSD slot713, and the fourth SSD slot714.

When the SSD backplane700is powered off, the first regulator731, the second regulator732, the third regulator733, and the fourth regulator734may monitor whether voltages are transferred from the first bi-metal721, the second bi-metal722, the third bi-metal723, and the fourth bi-metal724. When the voltages are not transferred (or are transferred), the first regulator731, the second regulator732, the third regulator733, and the fourth regulator734may maintain power interruption. When the voltages are transferred (or are not transferred), the first regulator731, the second regulator732, the third regulator733, and the fourth regulator734may supply the power to the SSDs of the first SSD slot711, the second SSD slot712, the third SSD slot713, and the fourth SSD slot714.

Each of the first regulator731, the second regulator732, the third regulator733, and the fourth regulator734may include a capacitor CP that stores power. When an ambient temperature is sufficiently high that a voltage is transferred from one of the first bi-metal721, the second bi-metal722, the third bi-metal723, and the fourth bi-metal724(or that a voltage is not transferred therefrom), the corresponding regulator may supply a power to the corresponding SSD. In the case where a voltage is not transferred (or is transferred) from one bi-metal as an ambient temperature decreases before the retention recovery operation of the corresponding SSD is completed, the corresponding regulator may block power from being supplied to the corresponding SSD. In this case, the corresponding SSD may complete the retention recovery operation by using a power stored in the capacitor CP. For example, the capacitor CP may be connected with an output terminal of the corresponding regulator, from which the power PWR is output.

FIG.23is a block diagram illustrating a data center including a storage device according to example embodiments.

Referring toFIG.23, a data center6000may be a facility that collects various types of data and provides various services, and may be referred to as a data storage center. The data center6000may be a system for operating search engines and databases, and may be a computing system used by companies such as banks or government agencies. The data center6000may include application servers6100to6100nand storage servers6200to6200m. The number of the application servers6100to6100nand the number of the storage servers6200to6200mmay be variously selected according to example embodiments, and the number of the application servers6100to6100nand the number of the storage servers6200to6200mmay be different from each other.

The application server6100may include at least one processor6110and at least one memory6120, and the storage server6200may include at least one processor6210and at least one memory6220. An operation of the storage server6200will be described as an example. The processor6210may control overall operations of the storage server6200, and may access the memory6220to execute instructions and/or data loaded in the memory6220. The memory6220may include at least one of a double data rate (DDR) synchronous dynamic random access memory (SDRAM), a high bandwidth memory (HBM), a hybrid memory cube (HMC), a dual in-line memory module (DIMM), an Optane DIMM, a nonvolatile DIMM (NVDIMM), etc. The number of the processors6210and the number of the memories6220included in the storage server6200may be variously selected according to example embodiments. In some example embodiments, the processor6210and the memory6220may provide a processor-memory pair. In some example embodiments, the number of the processors6210and the number of the memories6220may be different from each other. The processor6210may include a single core processor or a multiple core processor. The above description of the storage server6200may be similarly applied to the application server6100. The application server6100may include at least one storage device6150, and the storage server6200may include at least one storage device6250. In some example embodiments, the application server6100may not include the storage device6150. The number of the storage devices6250included in the storage server6200may be variously selected according to example embodiments.

The application servers6100to6100nand the storage servers6200to6200mmay communicate with each other through a network6300. The network6300may be implemented using a fiber channel (FC) or an Ethernet. The FC may be a medium used for a relatively high speed data transmission, and an optical switch that provides high performance and/or high availability may be used. The storage servers6200to6200mmay be provided as file storages, block storages or object storages according to an access scheme of the network6300.

In some example embodiments, the network6300may be a storage-only network or a network dedicated to a storage such as a storage area network (SAN). For example, the SAN may be an FC-SAN that uses an FC network and is implemented according to an FC protocol (FCP). For another example, the SAN may be an IP-SAN that uses a transmission control protocol/internet protocol (TCP/IP) network and is implemented according to an iSCSI (a SCSI over TCP/IP or an Internet SCSI) protocol. In other example embodiments, the network6300may be a general or normal network such as the TCP/IP network. For example, the network6300may be implemented according to at least one of protocols such as an FC over Ethernet (FCoE), a network attached storage (NAS), a nonvolatile memory express (NVMe) over Fabrics (NVMe-oF), etc.

Hereinafter, example embodiments will be described based on the application server6100and the storage server6200. The description of the application server6100may be applied to the other application server6100n(including switch6130n, and NIC6140n), and the description of the storage server6200may be applied to the other storage server6200m(including switch6230m, memory6220m, processor6210m, storage device6250m, NIC6240m, DRAM6253m, CTRL6251m, I/F6254m, and NAND6252m).

The application server6100may store data requested to be stored by a user or a client into one of the storage servers6200to6200mthrough the network6300. In addition, the application server6100may obtain data requested to be read by the user or the client from one of the storage servers6200to6200mthrough the network6300. For example, the application server6100may be implemented as a web server or a database management system (DBMS).

The application server6100may access a memory6120nor a storage device6150nincluded in the other application server6100nthrough the network6300, and/or may access the memories6220to6220mor the storage devices6250to6250mincluded in the storage servers6200to6200mthrough the network6300. Thus, the application server6100may perform various operations on data stored in the application servers6100to6100nand/or the storage servers6200to6200m. For example, the application server6100may execute a command for moving or copying data between the application servers6100to6100nand/or the storage servers6200to6200m. The data may be transferred from the storage devices6250to6250mof the storage servers6200to6200mto the memories6120to6120nof the application servers6100to6100ndirectly or through the memories6220to6220mof the storage servers6200to6200m. For example, the data transferred through the network6300may be encrypted data for security or privacy.

In the storage server6200, an interface6254may provide a physical connection between the processor6210and a controller6251and/or a physical connection between a network interface card (NIC)6240and the controller6251. For example, the interface6254may be implemented based on a direct attached storage (DAS) scheme in which the storage device6250is directly connected with a dedicated cable. For example, the interface6254may be implemented based on at least one of various interface schemes such as an advanced technology attachment (ATA), a serial ATA (SATA) an external SATA (e-SATA), a small computer system interface (SCSI), a serial attached SCSI (SAS), a peripheral component interconnection (PCI), a PCI express (PCIe), an NVMe, an IEEE 1394, a universal serial bus (USB), a secure digital (SD) card interface, a multi-media card (MMC) interface, an embedded MMC (eMMC) interface, a universal flash storage (UFS) interface, an embedded UFS (eUFS) interface, a compact flash (CF) card interface, etc.

The storage server6200may further include a switch6230and the NIC6240. The switch6230may selectively connect the processor6210with the storage device6250or may selectively connect the NIC6240with the storage device6250under a control of the processor6210. Similarly, the application server6100may further include a switch6130and an NIC6140.

In some example embodiments, the NIC6240may include a network interface card, a network adapter, or the like. The NIC6240may be connected to the network6300through a wired interface, a wireless interface, a Bluetooth interface, an optical interface, or the like. The NIC6240may further include an internal memory, a digital signal processor (DSP), a host bus interface, or the like, and may be connected to the processor6210and/or the switch6230through the host bus interface. The host bus interface may be implemented as one of the above-described examples of the interface6254. In some example embodiments, the NIC6240may be integrated with at least one of the processor6210, the switch6230and the storage device6250.

In the storage servers6200to6200mand/or the application servers6100to6100n, the processor may transmit a command to the storage devices6150to6150nand6250to6250mor the memories6120to6120nand6220to6220mto program or read data. For example, the data may be error-corrected data by an error correction code (ECC) engine. For example, the data may be processed by a data bus inversion (DBI) or a data masking (DM), and may include a cyclic redundancy code (CRC) information. For example, the data may be encrypted data for security or privacy.

The storage devices6150to6150mand6250to6250mmay transmit a control signal and command/address signals to NAND flash memory devices6252to6252min response to a read command received from the processor. When data is read from the NAND flash memory devices6252to6252m, a read enable (RE) signal may be input as a data output control signal and may serve to output data to a DQ bus. A data strobe signal (DQS) may be generated using the RE signal. The command and address signals may be latched in a page buffer based on a rising edge or a falling edge of a write enable (WE) signal.

The controller6251may control overall operations of the storage device6250. In some example embodiments, the controller6251may include a static random access memory (SRAM). The controller6251may write data into the NAND flash memory device6252in response to a write command, or may read data from the NAND flash memory device6252in response to a read command. For example, the write command and/or the read command may be provided from the processor6210in the storage server6200, the processor6210min the other storage server6200m, or the processors6110to6110nin the application servers6100to6100n. A DRAM6253may temporarily store (e.g., may buffer) data to be written to the NAND flash memory device6252or data read from the NAND flash memory device6252. Further, the DRAM6253may store meta data. The meta data may be data generated by the controller6251to manage user data or the NAND flash memory device6252.

The storage device6250may correspond to a storage device according to example embodiments and may increase an eye height of a transmission signal by reducing an impedance of a transmission driver as an operating (ambient) temperature of the storage device6250increases.

The present disclosures may be applied to various electronic devices including a nonvolatile memory device. For example, the present disclosures may be applied to systems such as be a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a camcorder, personal computer (PC), a server computer, a workstation, a laptop computer, a digital TV, a set-top box, a portable game console, a navigation system, etc.

The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims.