Patent ID: 12225302

DETAILED DESCRIPTIONS

FIG.1is a block diagram of an image sensing system1according to an example embodiment.

Referring toFIG.1, the image sensing system1may include an image sensor100and an image signal processor900.

The image sensor100may sense an image of a sensing target using light to generate an image signal IMS. The generated image signal IMS may be, e.g., a digital signal.

The image signal IMS may be provided to and processed by the image signal processor900. The image signal processor900may receive the image signal IMS output from a buffer1170of the image sensor100and process the received image signal IMS to facilitate displaying thereof.

The image signal processor900may perform digital binning on the image signal IMS output from the image sensor100. In various implementations, the image signal IMS output from the image sensor100may be a raw image signal from a pixel array1140which is not subjected to analog binning, or may be an image signal IMS on which the analog binning has already been performed.

The image sensor100and the image signal processor900may be disposed separately from each other as shown inFIG.1. For example, the image sensor100may be mounted on a first chip, while the image signal processor900may be mounted on a second chip. The image sensor100and the image signal processor900may communicate with each other over a predefined interface. In another implementation, the image sensor100and the image signal processor900may be integrated into one package, e.g., a multi-chip package (MCP).

The image sensor100may include a control register block1110, a timing generator1120, a row driver1130, the pixel array1140, a readout circuit1150, a ramp signal generator1160, and the buffer1170.

The control register block1110may control all operations of the image sensor100. The control register block1110may directly transmit an operation signal to the timing generator1120, the ramp signal generator1160and the buffer1170.

The timing generator1120may generate a signal as a reference for an operation timing of each of the various components of the image sensor100. The operation timing reference signal generated by the timing generator1120may be transmitted to the row driver1130, the readout circuit1150, the ramp signal generator1160, and the like.

The ramp signal generator1160may generate and transmit a ramp signal to be used in the readout circuit1150. The readout circuit1150may include a correlated double sampler (CDS), a comparator, etc. The ramp signal generator1160may generate and transmit the ramp signal to be used in the correlated double sampler (CDS), the comparator, and the like.

The buffer1170may include, e.g., a latch. The buffer1170may temporarily store therein the image signal IMS, to be provided to an external component. The image signal IMS may be transmitted to an external memory or an external device.

The pixel array1140may sense an external image. The pixel array1140may include a plurality of pixels (or unit pixels). The row driver1130may selectively activate a row of the pixel array1140.

The readout circuit1150may sample a pixel signal received from the pixel array1140, compare the sampled pixel signal with the ramp signal, and convert an analog image signal (data) into a digital image signal (data) based on the comparison result.

FIG.2is a diagram of a conceptual layout of the image sensor ofFIG.1.FIG.3is a plan view of the image sensor layout ofFIG.2.

Referring toFIG.2andFIG.3, the image sensor100may include a first area S1and a second area S2stacked in a third direction Z. Each of the first area S1and the second area S2may extend in a first direction X and a second direction Y intersecting the third direction Z as shown. The blocks shown inFIG.1may be disposed in the first area S1and the second area S2.

Although not shown in the drawing, a third area in which a memory is disposed may be disposed under the second area S2. The memory disposed in the third area may receive image data from the first area S1and the second area S2, store the data or process the data and retransmit the image data to the first area S1and the second area S2. The memory may include a memory element such as a DRAM (dynamic random access memory) element, an SRAM (static random access memory) element, an STT-MRAM (spin transfer torque magnetic random access memory) element, and a flash memory element. When the memory includes, e.g., the DRAM element, the memory may receive and process the image data at a relatively high speed. In an implementation, the memory may be disposed in the second area S2.

The first area S1may include a sensor array area SAR and a first peripheral area PH1. The second area S2may include a logic circuit area LC and a second peripheral area PH2. The first area S1and the second area S2may be sequentially stacked vertically.

In the first area S1, the sensor array area SAR may include a light-receiving area APS for an active pixel sensor array, which may correspond to the pixel array1140ofFIG.1. In the sensor array area SAR, a plurality of unit pixels may be arranged two-dimensionally (for example, in a matrix form).

The sensor array area SAR may include the light-receiving area APS and a light-blocking area OB to which light is exposed. Arrays of active pixel sensors that receive light and generate an active signal may be arranged in the light-receiving area APS. Optical black pixels that block light and generate an optical black signal may be arranged in the light-blocking area OB. The light-blocking area OB may be formed, e.g., along a perimeter of the light-receiving area APS.

Dummy pixels (not shown) may be formed in a portion of the light-receiving area APS adjacent to the light-blocking area OB.

The first peripheral area PH1may include a connection area CR and a pad area PR. The connection area CR may be formed around the sensor array area SAR. The connection area CR may be formed on one side of the sensor array area SAR. Lines may be formed in the connection area CR to transmit and receive electrical signals of the sensor array area SAR.

The pad area PR may be formed around the sensor array area SAR. The pad area PR may be adjacent to an edge of the image sensor. The pad area PR may be connected to the external device and the like, such that the image sensor100and the external device transmit and receive electrical signals to and from each other via the pad area.

In the second area S2, the logic circuit area LC may include electronic elements including a plurality of transistors. The electronic elements contained in the logic circuit area LC may be electrically connected to a pixel array PA (see, e.g.,FIG.4) to provide a constant signal to each of the unit pixels of the active pixel sensor array APS or to control an output signal.

The control register block1110, the timing generator1120, the row driver1130, the pixel array1140, the readout circuit1150, the ramp signal generator1160, the buffer1170, etc. as described above with reference toFIG.1may be disposed in the logic circuit area LC. Blocks other than the active pixel sensor array APS among the blocks ofFIG.1may be disposed in the logic circuit area LC.

The second peripheral area PH2may be disposed in the second area S2in a positionally corresponding manner to the first peripheral area PH1of the first area S1.

FIG.4andFIG.5are diagrams of a pixel array area according to an example embodiment.

Referring toFIG.4andFIG.5, the pixel array area PA may include a plurality of pixel areas PX. The pixel array area PA may be contained in the image sensor100. For example, the pixel array area PA may be implemented as the active pixel sensor array APS ofFIG.3or the pixel array140ofFIG.1.

The plurality of pixel areas PXs may include at least one of the unit pixels contained in the pixel array area PA. Each of the plurality of pixel areas PXs may be defined by a pixel defining pattern221formed in a mesh form including a first row R1and a second row R2extending in the first direction X. The first row R1and the second row R2may be arranged in a direction opposite to the second direction Y.

For example, the plurality of pixel areas PXs may be arranged and spaced apart from each other by a constant spacing along each of the first direction X and the second direction Y as shown inFIG.4.

FIG.4may be a view of the pixel array area PA ofFIG.3in a direction opposite to the third direction Z. The plurality of pixel areas PXs may be regularly arranged along the first direction X and the second direction Y. Thus, the pixel array area PA may include one pixel area PX.

A color filter grid250(seeFIG.5) may be stacked on the pixel defining pattern221in the third direction Z. The color filter grid250may be contained in the image sensor100, and may be contained in the pixel array area PA.

The color filter grid250may be formed in the same form as the mesh form of the pixel defining pattern221, so that at least a portion thereof overlaps with the pixel defining pattern221in the third direction Z.

An area where the color filter is disposed may be defined by the color filter grid250formed in a mesh form including the first row R1and the second row R2extending in the first direction X.

A first red color filter Re1, a first green color filter Gr1, a second red color filter Re2, and a second green color filter Gr2may be arranged in the first row R1. A third green color filter Gr3, a first blue color filter Bl1, a fourth green color filter Gr4, and a second blue color filter Bl2may be arranged in the second row R2.

Types of color filters between adjacent ones of the green color filters Gr1to Gr4may be different from each other in the first direction X or the second direction Y. The arrangement of the green color filters Gr1to Gr4may be equally applied to an arrangement of the red color filters Re1and Re2and an arrangement of the blue color filters Bl1and Bl2. In the arrangement of the color filters inFIG.5, the green color filters Gr1to Gr4may be arranged in an adjacent manner to each other in each of a first diagonal direction D1and a second diagonal direction D2intersecting the first direction X and the second direction Y.

When each unit pixel that is exposed to light through each of the green color filters Gr1to Gr4operates as an autofocusing (AF) pixel, the unit pixels are adjacent to each other in each of the first diagonal direction D1and the second diagonal direction D2. Thus, AF performance may be improved when performing an autofocusing operation directly in each of the first diagonal direction D1and the second diagonal direction D2.

FIG.6is an enlarged view of a layout of a pixel ofFIG.4.FIG.7is cross-sectional views taken along lines A-A, B-B, C-C, and D-D ofFIG.3.FIG.8is an enlarged view of an area R ofFIG.7.

Referring toFIG.3,FIG.4, andFIG.6toFIG.8, an image sensor according to an example embodiment may include a first semiconductor substrate110, a first line structure IS1, a second semiconductor substrate220, a second line structure IS2, a surface insulating layer210, a grid pattern for the color filter grid250, a color filter CF, and a micro lens ML.

The first semiconductor substrate110may be implemented as a bulk silicon or SOI (silicon-on-insulator). The first semiconductor substrate110may be implemented as a silicon substrate, or may include a material other than silicon, e.g., silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide. In an implementation, the first semiconductor substrate110may include a base substrate and an epitaxial layer formed on the base substrate.

The first semiconductor substrate110may include opposite first and second faces110aand110b. The first face110aof the first semiconductor substrate110may face toward a third face SF1of the second semiconductor substrate220.

A plurality of electronic elements may be formed on the first semiconductor substrate110. For example, a first electronic element TR1may be formed on the first face110aof the first semiconductor substrate110. The first electronic element TR1may be electrically connected to a sensor array area SARa, and may transmit/receive an electrical signal to and from each of unit pixel areas PX of the sensor array area SARa. For example, the first electronic element TR1may act as an electronic element constituting each of the control register block1110, the timing generator1120, the row driver1130, the active pixel sensor array APS, the readout circuit1150, the ramp signal generator1160, and the buffer1170inFIG.1.

The first line structure IS1may be formed on the first semiconductor substrate110. For example, the first line structure IS1may cover the first face110aof the first semiconductor substrate110. The first semiconductor substrate110and the first line structure IS1may constitute a first substrate structure101.

The first line structure IS1may be attached to the second line structure IS2. For example, as shown inFIG.7, a top face of the first line structure IS1may be attached to a bottom face of the second line structure IS2.

The first line structure IS1may be composed of one line or a plurality of lines. For example, the first line structure IS1may include a first inter-line insulating film130, and a plurality of lines ML1, ML2, and ML3in the first inter-line insulating film130. The first inter-line insulating film130may include, e.g., at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material having a lower dielectric constant than that of silicon oxide. The first line structure IS1may include the same material as that of the second line structure IS2.

At least some of the lines ML1, ML2, and ML3of the first line structure IS1may be connected to the first electronic element TR1. The first line structure IS1may include a first line ML1in the sensor array area SARa, a second line ML2in the connection area CR, and a third line ML3in the pad area PR. The second line ML2may act as a topmost line among a plurality of lines in the connection area CR, and the third line ML3may act as a topmost line among a plurality of lines in the pad area PR.

Each of the first line ML1, the second line ML2and the third line ML3may include, e.g., at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof.

The second semiconductor substrate220may be implemented as a semiconductor substrate. For example, the second semiconductor substrate220may be implemented as bulk silicon or an SOI (silicon-on-insulator). The second semiconductor substrate220may be implemented as a silicon substrate, or may include a material other than silicon, e.g., a semiconductor material including, e.g., silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. In another implementation, the second semiconductor substrate220may include a base substrate, and an epitaxial layer formed on the base substrate.

The second semiconductor substrate220may include third and fourth faces SF1and SF2facing opposite each other. The third face SF1may be referred to as a front face of the second semiconductor substrate220, while the fourth face SF2may be referred to as a rear face of the second semiconductor substrate220. The fourth face SF2of the second semiconductor substrate220may act as a light receiving face to which light may be incident. A portion of the fourth face SF2in the pixel area PX may be exposed to the light. Thus, the image sensor may be implemented as a back-side illumination (BSI) image sensor.

The plurality of pixel areas PXs may be formed in the second semiconductor substrate220of the sensor array area SARa. A micro lens ML and a color filter CF may be disposed on each of the plurality of pixel areas PXs. Although only a micro lens of a normal pixel is illustrated in the drawing, e.g., a super PD lens may be disposed on each of the plurality of pixel areas PXs.

The pixel area PX may include the second semiconductor substrate220, first to eighth photodiodes PD1to PD8, a second transistor TR2, a pixel defining pattern221, a first division pattern224, a second division pattern225, a first diagonal division pattern226_1, and a second diagonal division pattern226_2.

The second transistor TR2may be disposed on the third face SF1of the second semiconductor substrate220. The second transistor TR2may include, e.g., at least some of various transistors (for example, a transfer transistor, a reset transistor, a source follower transistor, and a select transistor) constituting the unit pixel of the image sensor.

The second transistor TR2may act as the transfer transistor of the image sensor100, and may be implemented to have a vertical transfer gate (VTG) structure. The second transistor TR2may include, e.g., a second-second and a second-third transistors TR2_2and TR2_3.

The transfer transistor as the second transistor TR2may transfer a sensed signal (charge) generated in a corresponding photodiode to a floating diffusion area. An impurity area corresponding to a source/drain of the transfer transistor may act as the floating diffusion area. In one example, the second-second transistor2_2may transmit the sensed signal generated in a second photodiode PD2to the floating diffusion area, while the second-third transistor TR2_3may transmit the sensed signal generated in the second photodiode PD2to the floating diffusion area.

However, the second transistor TR2may be other than the transfer transistor.

The pixel defining pattern221may be formed in a mesh form and in the second semiconductor substrate220, and may define each of the plurality of pixel areas PXs along the mesh form. Each of the plurality of pixel areas PXs may correspond to the unit pixel. The plurality of pixel areas PXs may be arranged in a two-dimensional matrix form in the first direction X and the second direction Y in a plan view. The pixel defining pattern221may be formed by embedding an insulating material into a deep trench formed by patterning the second semiconductor substrate220.

The pixel defining pattern221may include an insulating spacer film222and a conductive filling pattern223. The insulating spacer film222may extend conformally to and along a side face of the trench in the second semiconductor substrate220. The conductive filling pattern223may be formed on the insulating spacer film222to fill a portion of the trench in the second semiconductor substrate220.

The pixel defining pattern221may have a width of about 10 nm to about 500 nm. For example, the pixel isolation pattern120may have a width of about 100 nm to about 400 nm. Although the width of the pixel defining pattern221is shown to be uniform, the width of the pixel defining pattern221may be non-uniform.

The pixel area PX may include the first division pattern224, the second division pattern225, the first and second diagonal division patterns226_1and226_2, and the first to eighth photodiodes PD1to PDB.

A length in the first direction X or the second direction Y of the pixel area PX defined by the pixel defining pattern221may be, e.g., in a range of about 0.3 μm to about 3.0 μm, and, e.g., in a range of about 0.9 μm to about 1.5 μm. It is illustrated that the length in the first direction X and the length of the second direction Y are identical to each other in each pixel area PX. The length in the first direction X and the length of the second direction Y may be different from each other.

The first division pattern224may pass through a center O of the pixel area PX, and may extend in the first direction X and divide the pixel area PX into an upper half portion and a lower half portion arranged in the second direction Y.

A width of the first division pattern224may be, e.g., in a range of about 10 nm to about 500 nm, and, e.g., in a range of about 100 nm to about 400 nm. A material and a structure of the first division pattern224may be the same as those of the pixel defining pattern221.

The second division pattern225may pass through the center O of the pixel area PX, and may extend in the second direction Y and divide the pixel area PX into a left half portion and a right half portion arranged in the first direction X.

A width of the second division pattern225may be, e.g., in a range of about 10 nm to about 500 nm, and, e.g., in a range of about 100 nm to about 400 nm. A material and a structure of the second division pattern225may be the same as those of the pixel defining pattern221.

The first diagonal division pattern226_1may pass through the center O of the pixel area PX, and may extend in the first diagonal direction D1and divide the pixel area PX into two diagonal half portions along the first diagonal direction D1.

A width of the first diagonal division pattern226_1may be, e.g., in a range of about 10 nm to about 500 nm, and, e.g., in a range of about 100 nm to about 400 nm. A material and a structure of the first diagonal division pattern226_1may be the same as those of the pixel defining pattern221.

The second diagonal division pattern226_2may pass through the center O of the pixel area PX, and may extend in the second diagonal direction D2and divide the pixel area PX into two diagonal half portions along the second diagonal direction D2.

A width of the second diagonal division pattern226_2may be, e.g., in a range of about 10 nm to about 500 nm, and, e.g., in a range of about 100 nm to about 400 nm. A material and a structure of the second diagonal division pattern226_2may be the same as those of the pixel defining pattern221.

The first to eighth photodiodes PDs may be formed in the second semiconductor substrate220. The first to eighth photodiodes PDs may generate charges in proportion to an amount of light incident thereto from an outside. The first to eighth photodiodes PDs may be formed by doping impurities into the second semiconductor substrate220. When the second semiconductor substrate220is doped with a p-type impurity, the first to eighth photodiodes PDs may be doped with an n-type impurity. Thus, a type of the impurity doped into the second semiconductor substrate220may be different from a type of the impurity doped into the first to eighth photodiodes PDs.

Each of the first and fifth photodiodes PD1and PD5may be disposed between the first division pattern224and the first diagonal division pattern226_1, and may be separated from each other via the first division pattern224and the first diagonal division pattern226_1.

Each of the second and sixth photodiodes PD2and PD6may be disposed between the second division pattern225and the first diagonal division pattern226_1, and may be separated from each other via the second division pattern225and the first diagonal division pattern226_1.

Each of the third and seventh photodiodes PD3and PD7may be disposed between the second division pattern225and the second diagonal division pattern226_2, and may be separated from each other via the second division pattern225and the second diagonal division pattern226_2.

Each of the fourth and eighth photodiode PD4and PD8may be disposed between the first division pattern224and the second diagonal division pattern226_2, and may be separated from each other via the first division pattern224and the second diagonal division pattern226_2.

The first photodiode PD1and the second photodiode PD2may be separated from each other via the first diagonal division pattern226_1, and may be disposed adjacent to each other. The fifth photodiode PD5and the sixth photodiode PD6may be separated from each other via the first diagonal division pattern226_1and disposed adjacent to each other.

The third photodiode PD3and the fourth photodiode PD4may be separated from each other via the second diagonal division pattern226_2, and disposed adjacent to each other. The seventh photodiode PD7and the eighth photodiode PD8may be separated from each other via the second diagonal division pattern226_2and disposed adjacent to each other.

The first photodiode PD1and the eighth photodiode PD8may be separated from each other via the first division pattern224and disposed adjacent to each other. The fourth photodiode PD4and the fifth photodiode PD5may be separated from each other via the first division pattern224and disposed adjacent to each other.

The second photodiode PD2and the third photodiode PD3may be separated from each other via the second division pattern225and disposed adjacent to each other. The sixth photodiode PD6and the seventh photodiode PD7may be separated from each other via the second division pattern225and disposed adjacent to each other.

The pixel area PX may include the surface insulating layer210, the grid pattern for the color filter grid250, a first liner253, the color filter CF, the micro lens ML, and a second liner254, and the like.

The surface insulating layer210may be stacked on the fourth face SF2of the second semiconductor substrate220. The color filter grid250, the first liner253, the color filter CF, the micro lens ML and the second liner254may be disposed in an area defined by the surface insulating layer210.

The color filter CF may be formed on the surface insulating layer210. A respective color filter CF may correspond to each unit pixel. Each color filter CF may have a two-dimensional shape in a plan view. The color filter CF may include a red color filter, a blue color filter, and a green color filter. However, when a pixel corresponding to the pixel area PX acts as an AF pixel, the color filter CF may be implemented as the green color filter Gr1. Further, when the color filters CFs are arranged as shown inFIG.5, the green color filters may be successively arranged in the first diagonal direction D1and the second diagonal direction D2, so that phase difference information in the first diagonal direction D1and the second diagonal direction D2is precisely obtained.

The micro lens ML may be formed on the color filter CF. A respective micro lens ML may correspond to each pixel area PX, and may be disposed across each of the first to eighth photodiodes PD1to PD8. The micro lens ML may have a convex shape with a predefined radius of curvature to condense incident light to the first to eighth photodiodes PD1to PD8. The micro lens ML may include, e.g., light-transmissive resin. In one example, the micro lens ML of each pixel PX may cover one face of each pixel.

The color filter grid250may be formed in a mesh form, and may be disposed between the color filter CFs, and may define an area of each of the color filters CFs. Accordingly, at least a portion of the color filter grid250may overlap the pixel defining pattern221in the third direction Z.

The color filter grid250may be formed on the surface insulating layer210. The color filter grid250may include, e.g., a metal pattern251and a low refractive index pattern252. The metal pattern251and the low refractive index pattern252may be sequentially stacked on the surface insulating layer210.

The first liner253may be formed on the surface insulating layer210and the color filter grid250. The first liner253may extend along a surface of each of the surface insulating layer210and the color filter grid250. The first liner253may include, e.g., aluminum oxide.

The second liner254may extend along a surface of the micro lens ML. The second liner254may be implemented as a film made of an inorganic material oxide such as silicon oxide, titanium oxide, zirconium oxide, hafnium oxide, and combinations thereof.

The pixel area PX may include a second inter-line insulating film230and a connection structure. The connection structure may be formed in the second inter-line insulating film230. The connection structure may include a fourth line ML4and a plurality of contacts (not shown) in the sensor array area SARa. The components of the pixel area PX and the components of the image sensor100may be electrically connected to each other via the connection structure.

In the pixel area PX, a P-type barrier PB may be formed in the second semiconductor substrate220. Each P-type barrier PB may be spaced apart from each of the first to eighth photodiodes PD1to PD8by a predetermined spacing. For example, each P-type barrier PB may be disposed around each of the first to eighth photodiodes PD1to PD8and may surround each of the first to eighth photodiodes PD1to PD8. For example, each of the P-type barriers PB may be spaced apart from each of the first to eighth photodiodes PD1to PD8in the first direction X and the second direction Y. Further, each P-type barrier PB may extend in the third direction Z and along a photoelectric conversion layer PD. Thus, each P-type barrier PB may extend vertically in the second semiconductor substrate220. While the photoelectric conversion layer PD may be doped with an n-type impurity, the P-type barrier PB may be doped with a p-type impurity.

Further, although not shown in the drawing, the pixel area PX of the pixel array area PA may include a storage diode, a storage gate, etc., disposed adjacent to each of the first to eighth photodiodes PD1to PD8.

The image sensor may further include a first connection structure350, a second connection structure450, and a third connection structure550.

The first connection structure350may be formed in the light-blocking area OB. A portion of the first connection structure350may be formed on a portion of the surface insulating layer210in the light-blocking area OB. The first connection structure350may be in contact with the second division pattern225. For example, a first trench355texposing the second division pattern225may be formed in the second semiconductor substrate220and the surface insulating layer210and in the light-blocking area OB. The first connection structure350may be formed in the first trench355tand may contact a portion of the second division pattern225in the light-blocking area OB. The first connection structure350may extend along a profile of a side face and a bottom face of the first trench355t.

The first connection structure350may be electrically connected to the second division pattern225to apply a ground voltage or a negative voltage to the conductive filling pattern227. Accordingly, charges generated by ESD or the like may be discharged to the first connection structure350through the second division pattern225, such that ESD bruising may be effectively prevented.

The first connection structure350may include a titanium (Ti) film, a titanium nitride (TiN) film, and a tungsten (W) film sequentially stacked in the first trench355t.

A first pad355filling the first trench355tmay be formed on the first connection structure350. The first pad355may include, e.g., at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof.

The first liner253may cover the first connection structure350and the first pad355. For example, the first liner253may extend along a profile of each of the first connection structure350and the first pad355.

The second connection structure450may be formed in the connection area CR. A portion of the second connection structure450may be formed on a portion of the surface insulating layer210in the connection area CR. The second connection structure450may electrically connect the first substrate structure101and the second substrate structure200to each other. For example, a second trench455texposing the second line ML2and the fifth line ML5may be formed in the first substrate structure101and the second substrate structure200and in the connection area CR. The second connection structure450may be formed in the second trench455tand may connect the second line ML2and the fifth line ML5to each other. The second connection structure450may extend along a profile of a side face and a bottom face of the second trench455t.

The second connection structure450may include a titanium (Ti) film, a titanium nitride (TiN) film, and a tungsten (W) film that are sequentially stacked in the second trench455t.

The first liner253may cover the second connection structure450. For example, the first liner253may extend along a profile of the second connection structure450.

A first filling insulating film460filling the second trench455tmay be formed on the second connection structure450. The first filling insulating film460may include, e.g., at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof.

The third connection structure550may be formed in the pad area PR. The third connection structure550may be formed on a portion of the surface insulating layer210in the pad area PR. The third connection structure550may electrically connect the first substrate structure101and an external device to each other.

A third trench550texposing the third line ML3may be formed in the first substrate structure101and the second substrate structure200and in the pad area PR. The third connection structure550may be formed in the third trench550tand contact the third line ML3.

A fourth trench555tmay be formed in a portion of the second semiconductor substrate220in the pad area PR. The third connection structure550may be formed in the fourth trench555tand may be exposed outwardly. The third connection structure550may extend along a profile of a side face and a bottom face of each of the third trench550tand the fourth trench555t.

A second filling insulating film560filling the third trench550tmay be formed on the third connection structure550. The second filling insulating film560may include, e.g., at least one of silicon oxide, aluminum oxide, tantalum oxide, and combinations thereof.

A second pad555filling the fourth trench555tmay be formed on the third connection structure550. The second pad555may include, e.g., at least one of tungsten (W), copper (Cu), aluminum (Al), gold (Au), silver (Ag), and alloys thereof.

The third connection structure550may include a titanium (Ti) film, a titanium nitride (TiN) film, and a tungsten (W) film that are sequentially stacked in the third trench550t.

The first liner253may cover the third connection structure550. For example, the first liner253may extend along a profile of the third connection structure550. The first liner253may expose the second pad555.

A fourth color filter370C may be formed on the first connection structure350and the second connection structure450. For example, the fourth color filter370C may be formed to cover a portion of the first liner253in each of the light-blocking area OB and the connection area CR.

The fourth color filter370C may include, e.g., a blue color filter.

A protective film380may be formed on the fourth color filter370C. For example, the protective film380may be formed to cover a portion of the first liner253in each of the light-blocking area OB, the connection area CR, and the pad area PR. The second liner254may extend along a surface of the protective film380. The protective film380may include, e.g., light-transmissive resin. The protective film380may include the same material as that of the micro lens180.

The second liner254and the protective film380may expose the second pad555. For example, an exposure opening ER exposing the second pad555may be formed in the second liner254and the protective film380. Accordingly, the second pad555may be connected to the external device such that the image sensor and the external device may transmit and receive an electrical signal to and from each other via the second pad.

FIG.9is an example circuit diagram of a unit pixel of an image sensor according to an example embodiment.

Referring toFIG.9, the image sensor includes a unit pixel corresponding to the pixel area PX. Hereinafter, for convenience of description, the pixel area PX is referred to as a unit pixel PX.

A plurality of unit pixels PXs may be arranged in a matrix form along a row direction and a column direction. Each unit pixel PX may include first to eighth photodiodes PD1to PD8, a floating diffusion area FD, and control transistors TX1to TX8, RX, SX, and AX.

The control transistors TX1and TX8, RX, SX, and AX may include first to eighth transfer transistors TX1to TX8, a reset transistor RX, a select transistor SX and an amplification transistor AX. Gate electrodes of the first to eighth transfer transistors TX1to TX8, the reset transistor RX, and the select transistor SX may be connected to driving signal lines TG1to TG8, RG, and SG, respectively.

The driving signal lines TG1to TG8, RG, and SG may be controlled by the row driver1130ofFIG.1. The driving signal lines TG1to TG8, RG, and SG may constitute a single row line ROW.

Each unit pixel PX may include eight individual photodiodes PD1to PD8. Each of the first to eighth photodiodes PD1to PD8may generate electric charges in proportion to the amount of light incident thereto from the outside. The first photodiode PD1may be coupled to the first transfer transistor TX1, and the second photodiode PD2may be coupled to the second transfer transistor TX2. Remaining third to eighth photodiode PD3to PD8may be coupled with remaining third to eighth transfer transistors TX3to TX8, respectively.

The floating diffusion area FD converts charges into voltage. The area FD has parasitic capacitance such that charges may be stored therein in an accumulated manner. The first transfer transistor TX1may be turned on by a first transfer line TG1that applies a predefined bias, such that the electric charge generated from the first photodiode PD1may be transmitted as a sensed signal to the floating diffusion area FD. The second transfer transistor TX2may be turned on by a second transfer line TG2that applies a predefined bias, so that the charge generated from the second photodiode PD2may be transmitted as a sensed signal to the floating diffusion area FD. Operations of the remaining third to eighth transfer transistors TX3to TX8may correspond with the descriptions of the operations of the first and second transfer transistors TX1and TX2.

The first to eighth transfer transistors TX1to TX8may share the floating diffusion area FD. For example, one end of the first transfer transistor TX1may be connected to the first photodiode PD1, and the opposite end of the first transfer transistor TX1may be connected to the floating diffusion area FD. Further, one end of the second transfer transistor TX2may be connected to the second photodiode PD2, and the opposite end of the second transfer transistor TX2may be connected to the floating diffusion area FD. One end of each of the remaining third to eighth transfer transistors TX3to TX8may be connected to each of the third to eighth photodiodes PD3to PD8, and the opposite end thereof may be connected to the floating diffusion area FD.

The sensed signals respectively generated from the first to eighth photodiodes PD1to PD8may be analog-binned in the floating diffusion area FD via the first to eighth transfer lines TG1to TG8.

The reset transistor RX may periodically reset the floating diffusion area FD. The reset transistor RX may be turned on by a reset line RG that applies a predefined bias. When the reset transistor RX is turned on, a predefined electrical potential, e.g., power voltage VDDprovided to a drain of the reset transistor RX may be transferred to the floating diffusion area FD.

The amplification transistor AX may amplify a change in the potential of the floating diffusion area FD when the area FD has received the charges from at least one of the analog-binned sensed signals respectively generated in the first to eighth photodiodes PD1to PD8. Then, the amplification transistor AX may output the change as an output voltage VOUT. The amplification transistor AX may be implemented as a source follower buffer amplifier that generates a source-drain current in proportion to an amount of charge in the floating diffusion area FD. For example, a gate electrode of the amplification transistor AX may be connected to the floating diffusion area FD. Thus, a predefined electrical potential, e.g., power voltage VDDprovided to a drain of the amplification transistor AX may be transferred to a drain of the select transistor SX.

The select transistor SX may select a unit pixel PX to be readout on a row basis. The select transistor SX may be turned on by a select line SG that applies a predefined bias. Thus, the output voltage VOUTof the unit pixel PX selected by the select transistor SX may be output. The output voltage VOUTmay be an analog-binned pixel signal SIG_PX.

FIG.10andFIG.11are diagrams of an operation of a unit pixel of an image sensor according to an example embodiment.

Referring toFIG.9toFIG.11, when a unit pixel PX performs an auto-focus (AF) function on a first object OBJ1extending in the second direction Y, the unit pixel PX may act as an AF pixel and may perform a first operation mode Mode1.

In the first operation mode Mode1, an analog binning operation may be performed based on sensed signals generated from the first and second photodiodes PD1and PD2and the seventh and eighth photodiodes PD7and PD8, and an analog binning operation is performed based on sensed signals generated from the third to sixth photodiode PD3to PD6. The analog binning operation is described below with reference toFIG.11.

Under control of the row driver1130inFIG.1, the first and second transfer lines TG1and TG2and the seventh and eighth transfer lines TG7and TG8are activated on at an a-th time-point Ta. Thus, the sensed signals generated from the first and second photodiodes PD1and PD2and the seventh and eighth photodiodes PD7and PD8are subjected to the analog binning operation in the floating diffusion area FD. The unit pixel PX may output the pixel signal SIG_PX generated via the analog binning operation.

After the a-th time-point Ta, the reset control line RG may be activated at a first time-point t1, such that the reset transistor RX may be turned on, and thus the power voltage Vddmay be applied to the floating diffusion area FD such that the area FD may be reset.

After the first time-point t1, the third to sixth transfer lines TG3to TG6may be activated at a b-th time-point Tb, such that the sensed signals generated from the third to sixth photodiode PD3to PD6are subjected to an analog binning operation in the floating diffusion area FD. The unit pixel PX may output the pixel signal SIG_PX generated via the analog binning operation.

After the b-th time-point tb, the reset control line RG may be activated at a second time-point t2to turn on the reset transistor RX. Thus, the power voltage Vddis applied to the floating diffusion area FD such that the area FD is reset.

After the second time-point t2, the first and second transfer lines TG1and TG2and the seventh and eighth transfer lines TG7and TG8may be activated at a c-th time-point Tc, so that the sensed signals generated from the first and second photodiodes PD1and PD2and the seventh and eighth photodiodes PD7and PD8are subjected to an analog binning operation in the floating diffusion area FD. The unit pixel PX may output the pixel signal SIG_PX generated via the analog binning operation.

After the c-th time-point Tc, the reset control line RG may be activated at a third time-point t3, such that the reset transistor RX may be turned on, and thus the power voltage Vdd may be applied to the floating diffusion area FD such that the area FD may be reset.

After the third time-point t3, the third to sixth transfer lines TG3to TG6may be activated at a d-th time-point Td, such that the sensed signals generated from the third to sixth photodiodes PD3to PD6are subjected to an analog binning operation in the floating diffusion area FD. The unit pixel PX may output the pixel signal SIG_PX generated via the analog binning operation.

For a first exposure time duration T1between the a-th time-point Ta and the c-th time-point Tc, the first and second photodiodes PD1and PD2and the seventh and eighth photodiodes PD7and PD8may be charged with photoelectric charges. For a second exposure time duration T2between the b-th time-point Tb and the d-th time-point Td, the third to sixth photodiodes PD3to PD6may be charged with photoelectric charges.

FIG.12toFIG.14are diagrams of an operation of a unit pixel of an image sensor according to an example embodiment.

Referring toFIG.9andFIG.12, when a unit pixel PX performs an autofocusing (AF) function on a second object OBJ2extending in the first direction X, the unit pixel PX may act as an AF pixel and may perform a second operation mode Mode2.

In the second operation mode Mode2, an analog binning operation may be performed based on sensed signals generated from the first to fourth photodiodes PD1to PD4, and an analog binning operation may be performed based on sensed signals generated from fifth to eighth photodiodes PDS to PD8.

As in the analog binning operation ofFIG.11, the analog binning operation ofFIG.12may be performed such that an execution time of the analog binning operation on the sensed signal generated from the first to fourth photodiodes PD1to PD4is different from an execution time of the analog binning operation on the sensed signal generated from the fifth to eighth photodiodes PD5to PD8.

Referring toFIG.9andFIG.13, when the unit pixel PX performs the autofocusing (AF) function on a third object OBJ3extending in the first diagonal direction D1, the unit pixel PX may act as an AF pixel and may perform a third operation mode Mode3.

In the third operation mode Mode3, an analog binning operation may be performed based on sensed signals generated from the first photodiode PD1and the sixth to eighth photodiodes PD6to PD8, and an analog binning operation may be performed based on sensed signals generated from the second to fifth photodiodes PD2to PD5.

When the unit pixel PX performs the autofocusing (AF) function on an object extending in the second diagonal direction D2, an analog binning operation may be performed based on sensed signals generated from the eighth photodiode PD8and the first to third photodiodes PD1to PD3, and an analog binning operation may be performed based on sensed signals generated from the fourth to seventh photodiodes PD4to PD7.

As in the analog binning operation ofFIG.11, the analog binning operation ofFIG.13may be performed such that an execution time of the analog binning operation on the sensed signal generated from the first photodiode PD1and the sixth to eighth photodiodes PD6to PD8is different from an execution time of the analog binning operation on the sensed signal generated from the second to fifth photodiodes PD2to PDS.

Referring toFIG.9andFIG.14, when the unit pixel PX performs an image detection function on a fourth object OBJ4, the unit pixel PX may act as an image detection pixel, and may perform a fourth operation mode Mode4.

In the fourth operation mode Mode4, an analog binning operation may be concurrently performed based on sensed signals generated from the first to eighth photodiodes PD1to PD8.

FIG.15is an example circuit diagram of a unit pixel of an image sensor according to another example embodiment.

Hereinafter, a configuration of a unit pixel PX′ according to another example embodiment will be described with reference toFIG.15. Following descriptions are focused on differences thereof from a configuration of the unit pixel PX shown inFIG.10.

As compared to the unit pixel PX inFIG.10, the unit pixel PX′ further includes first to eighth reset transistors RX1to RX8, first to eighth select transistors SX1to SX8, first to eighth amplification transistors AX1to AX8, and first to eighth floating diffusion areas FD1to FD8.

Each of the first to eighth reset transistors RX1to RX8, each of the first to eighth select transistors SX1to SX8, each of the amplification transistors AX1to AX8, and each of the first to eighth floating diffusion areas FD1to FD8may respectively correspond to the reset transistor RX, the select transistor SX, the amplification transistor AX, and the floating diffusion area FD inFIG.10

Each of the first to eighth transfer transistors TX1to TX8may be turned on by each of the first to eighth transfer lines TG1to TG8that applies a predefined bias, such that electric charges generated from each of the first to eighth photodiodes PD1to PD8may be transmitted, as each of first to eighth sensed signals, to each of the first to eighth floating diffusion areas FD1to FD8.

Each of the first to eighth transfer transistors TX1to TX8may be coupled to each of the first to eighth floating diffusion areas FD1to FD8. The first to eighth floating diffusion areas FD1to FD8may be separated from each other.

Each of the first to eighth reset transistors RX1to RX8may periodically reset each of the first to eighth floating diffusion areas FD1to FD8. The first to eighth reset transistors RX1to RX8may be turned on by a reset line RG that applies a predefined bias. When the first to eighth reset transistors RX1to RX8are turned on, a predefined electrical potential, e.g., a power voltage VDDprovided to a drain of each of the first to eighth reset transistors RX1to RX8may be transferred to each of the first to eighth floating diffusion areas FD1to FD8.

Each of the first to eighth amplification transistors AX1to AX8may amplify a change in the potential of each of the first to eighth floating diffusion areas FD1to FD8when each of the first to eighth floating diffusion areas FD1to FD8has received the charges from each of the first to eighth sensed signals generated from each of the first to eighth photodiodes PD1to PD8. Then, each of the first to eighth amplification transistors AX1to AX8may output each amplified change as each of first to eighth output voltages VOUT1to VOUT8. Each of the first to eighth amplification transistors AX1to AX8may be implemented as a source follower buffer amplifier that generates a source-drain current in proportion to a charge amount of each of the first to eighth floating diffusion areas FD1to FD8. For example, a gate electrode of each of the first to eighth amplification transistors AX1to AX8may be connected to each of the first to eighth floating diffusion areas FD1to FD8. Thus, a predefined electrical potential, e.g., a power voltage VDDprovided to a drain of each of the first to eighth amplification transistors AX1to AX8may be delivered to a drain of each of the first to eighth select transistors SX1to SX8.

Each of the first to eighth select transistors SX1to SX8may select a unit pixel PX′ to be readout on a row basis. Each of the first to eighth select transistors SX1to SX8may be turned on by a select line SG that applies a predefined bias. Thus, each of the first to eighth output voltages VOUT1to VOUT8of the unit pixel PX′ selected by each of the first to eighth select transistors SX1to SX8may be output. Each of the first to eighth output voltages VOUT1to VOUT8may be each of first to eighth pixel signals SIG_PX1to SIG_PX8.

The first to eighth pixel signals SIG_PX1to SIG_PX8may be output to one column line COL. The first to eighth pixel signals SIG_PX1to SIG_PX8may be individually output from the unit pixel PX′, and may be input to the readout circuit1150inFIG.1at the same time.

FIG.16is a diagram of an operation of an image sensing system according to another example embodiment.FIG.16illustrates an operation of the image sensing system including the unit pixel PX′ inFIG.15.

Referring toFIG.1,FIG.15andFIG.16, the readout circuit1150may include a binning determiner1151, a correlated double sampler (CDS)1152, and an analog-digital converter1153.

The binning determiner1151may receive the pixel signals SIG_PX output from the unit pixel PX′. The pixel signals SIG_PX may include the first to eighth pixel signals SIG_PX1to SIG_PX8. The binning determiner1151may determine whether to perform a binning operation on the pixel signals SIG_PX.

The binning determiner1151may determine performing the binning operation according to an operation mode of the unit pixel PX′. The binning determiner1151may perform an analog binning operation on the first to eighth pixel signals SIG_PX1to SIG_PX8as the pixel signals SIG_PX to output an image signal IMS as a binned image signal SIG_BIN.

When the unit pixel PX′ performs the autofocusing (AF) function on the first object OBJ1extending in the second direction Y as in the first operation mode Mode1inFIG.10, the binning determiner1151may determine to perform a first analog binning operation based on first and second pixel signals SIG_PX1and SIG_PX2and seventh and eighth pixel signals SIG_PX7and SIG_PX8respectively generated from first and second photodiodes PD1, PD2and the seventh and eighth photodiodes PD7and PD8, and to perform a second analog binning operation based on third to sixth pixel signals SIG_PX3to SIG_PX6generated respectively from the third to sixth photodiodes PD3to PD6.

When the unit pixel PX′ performs the autofocusing (AF) function on the second object OBJ2extending in the first direction X as in the second operation mode Mode2inFIG.12, the binning determiner1151may determine to perform a first analog binning operation based on the first to fourth pixel signals SIG_PX1to SIG_PX4generated respectively from the first to fourth photodiodes PD1to PD4, and to perform a second analog binning operation based on the fifth to eighth pixel signals SIG_PX5to SIG_PX8generated respectively from the fifth to eighth photodiodes PD5to PD8.

When the unit pixel PX′ performs the autofocusing (AF) function on the third object OBJ3extending in the first diagonal direction D1as in the third operation mode Mode3inFIG.13, the binning determiner1151may determine to perform a first analog binning operation based on the first pixel signal SIG_PX1and the sixth to eighth pixel signals SIG_PX6to SIG_PX8generated respectively from the first photodiode PD1and the sixth to eighth photodiodes PD6to PD8, and to perform a second analog binning operation based on the second to fifth pixel signals SIG_PX2to SIG_PX5generated respectively from the second to fifth photodiodes PD2to PDS.

When the unit pixel PX′ performs the image detection function on the fourth object OBJ4as in the fourth operation mode Mode4ofFIG.14, the binning determiner1151may determine to perform an analog binning operation based on the first to eighth pixel signals SIG_PX1to SIG_PX8generated respectively from the first to eighth photodiodes PD1to PD8.

FIG.17is a diagram of an operation of an image sensing system according to another example embodiment.FIG.17illustrates the operation of the image sensing system including the unit pixel PX′ inFIG.15.

Referring toFIG.1,FIG.15, andFIG.17, the buffer1170may receive first to eighth image signals IMS corresponding to the first to eighth pixel signals SIG_PX1to SIG_PX8from the readout circuit1150, and deliver the first to eighth image signals IMS to the image signal processor900. The image signal processor900may perform a digital binning operation on the first to eighth image signals IMS to generate a binned image signal SIG_BIN.

The image signal processor900may determine performing the binning operation according to the operation mode of the unit pixel PX′. Thus, the image signal processor900may perform a digital binning operation on first to eighth image signals IMS corresponding to the first to eighth pixel signals SIG_PX1to SIG_PX8to output a binned image signal SIG_BIN.

When the unit pixel PX′ performs the autofocusing (AF) function on the first object OBJ1extending in the second direction Y, as in the first operation mode Mode1inFIG.10, the image signal processor900may perform a first digital binning operation on first and second image signals IMS1and IMS2and seventh and eighth image signals IMS7and IMS8respectively based on the first and second pixel signals SIG_PX1and SIG_PX2and the seventh and eighth pixel signals SIG_PX7and SIG_PX8, and perform a second digital binning operation third to sixth image signals IMS3to IMS6respectively based on the third to sixth pixel signals SIG_PX3to SIG_PX6.

When the unit pixel PX′ performs the autofocusing (AF) function on the second object OBJ2extending in the first direction X, as in the second operation mode Mode2inFIG.12, the image signal processor900may perform a first digital binning operation on the first to fourth image signals IMS1to IMS4respectively based on the first to fourth pixel signals SIG_PX1to SIG_PX4, and perform a second digital binning operation on the fifth to eighth image signal IMS5to IMS8respectively based on the fifth to eighth pixel signals SIG_PX5to SIG_PX8.

When the unit pixel PX′ performs the autofocusing (AF) function on the third object OBJ3extending in the first diagonal direction D1, as in the third operation mode Mode3inFIG.13, the image signal processor900may perform a first digital binning operation on the first and sixth to eighth image signals IMS1and IMS6to IMS8respectively based on the first pixel signal SIG_PX1and the sixth to eighth pixel signals SIG_PX6to SIG_PX8, and perform a second digital binning operation on the second to fifth image signals IMS2to IMS5respectively based on the second to fifth pixel signals SIG_PX2to SIG_PX5.

When the unit pixel PX′ performs the image detection function on the fourth object OBJ4, as in the fourth operation mode Mode4ofFIG.14, the image signal processor900may perform a digital binning operation on the first to eighth image signals IMS1to IMS8respectively based on the first to eighth pixel signals SIG_PX1to SIG_PX8.

An image sensing system according to an example embodiment may efficiently and quickly perform the autofocusing operation on the diagonal directions in the third operation mode Mode2of each of the unit pixel PX and the unit pixel PX′.

An image sensing system according to an example embodiment may provide a dual pixel that may efficiently perform the autofocusing operation on various directions, and may efficiently perform the image detection operation in the first to fourth operation modes Mode1to Mode4of each of the unit pixel PX and the unit pixel PX′.

FIG.18is a diagram of an image sensor according to another example embodiment.

Hereinafter, an image sensor according to another example embodiment will be described with reference toFIG.18. The following description will be focused on differences thereof from the image sensor shown inFIG.7.

As compared to the pixel defining pattern221inFIG.7, a width of a pixel defining pattern221′ inFIG.18decreases as the pixel defining pattern221′ extends in a direction from the third face SF1of the second semiconductor substrate220toward the fourth face SF2of the second semiconductor substrate220.

The structure of the pixel defining pattern221′ may be formed using characteristics of an etching process that forms the pixel defining pattern221′. For example, the process of etching the second semiconductor substrate220to form the pixel defining pattern221′ may be performed on the third face SF1of the second semiconductor substrate220.

FIG.19is a diagram of an image sensor according to another example embodiment.

Hereinafter, an image sensor according to another example embodiment will be described with reference toFIG.19. The following description will be focused on differences thereof from the image sensors shown inFIG.18.

As compared to the pixel defining pattern221′ inFIG.18, a width of a pixel defining pattern221″ inFIG.19decreases as the pixel defining pattern221″ extends in a direction from the fourth face SF2of the second semiconductor substrate220toward the third face SF1of the second semiconductor substrate220.

The structure of the pixel defining pattern221″ may be formed using characteristics of an etching process that forms the pixel defining pattern221″. For example, the process of etching the second semiconductor substrate220to form the pixel defining pattern221″ may be performed on the fourth face SF2of the second semiconductor substrate220.

The pixel defining pattern221″ may not completely extend through the second semiconductor substrate220. For example, the pixel defining pattern221″ may extend from the fourth face SF2of the second semiconductor substrate220, but may not reach the third face SF1of the second semiconductor substrate220. Thus, the lowermost face of the pixel defining pattern221″ may be spaced apart from the third face SF1of the second semiconductor substrate220.

FIG.20is a diagram of an image sensor according to another example embodiment.

Hereinafter, an image sensor according to another example embodiment will be described with reference toFIG.20. The following description will be focused on differences thereof from the image sensor shown inFIG.7.

The image sensor inFIG.20may include a connection pattern451instead of the second connection structure450in the connection area CR. The connection pattern451may include a first connection pattern451_1, a second connection pattern451_2, and a third connection pattern451_3.

The first connection pattern451_1may extend through the surface insulating layer210, the second semiconductor substrate220, and the second inter-line insulating film230in the third direction Z, and may be connected to the fifth line ML5in the connection area CR.

The second connection pattern451_2may extend through the surface insulating layer210, the second semiconductor substrate220, the second inter-line insulating film230, and the first inter-line insulating film130in the third direction Z, and may be connected to the second line ML2in the connection area CR.

The second connection pattern451_2may be spaced apart from the first connection pattern451_1. A portion of each of the surface insulating layer210, the second semiconductor substrate220, and the second inter-line insulating film230may be disposed between the first connection pattern451_1and the second connection pattern451_2.

The third connection pattern451_3may be disposed on a top face of the surface insulating layer210. The third connection pattern451_3may connect the first connection pattern451_1and the second connection pattern451_2to each other.

FIG.21is a block diagram showing an electronic device including a multi-camera module according to an example embodiment.FIG.22is a detailed block diagram of a camera module ofFIG.21.

Hereinafter, referring toFIG.21andFIG.22, an electronic device1000according to another example embodiment will be described. For convenience of descriptions, duplicate descriptions to those with reference toFIG.1toFIG.20are briefly made or omitted.

Referring toFIG.21, the electronic device1000may include a camera module group1100, an application processor1200, a PMIC1300, and an external memory1400.

The camera module group1100may include a plurality of camera modules1100a,1100b, and1100c. AlthoughFIG.21shows an embodiment in which three camera modules1100a,1100b, and1100care arranged, the camera module group1100may be modified to include, e.g., only two camera modules, or four or more camera modules.

One of the three camera modules1100a,1100b, and1100cmay include the image sensor100described usingFIG.1toFIG.20.

Hereinafter, with reference toFIG.22, a detailed configuration of the camera module1100bwill be described in more detail. However, the following description may be equally applied to other camera modules1100aand1100caccording to embodiments.

Referring toFIG.22, the camera module1100bmay include a prism1105, an optical path folding element (OPFE)1111, an actuator1131, an image sensing device1141, and a storage1155.

The prism1105may include a reflective face1107made of a reflective material, and may modify a path of light L that is incident from an outside. For example, the prism1105may change the path of the light L such that the light incident thereto in the first direction X is output therefrom in a second direction Y perpendicular to the first direction X. Further, the prism1105may rotate the reflective face1107of the reflective material in an A direction about a central axis1106or may rotate the central axis1106in a B direction so that the light incident thereto in the first direction X is output therefrom in the second direction Y perpendicular to the first direction X. The OPFE1111may move in a third direction Z normal to a plane defined by the first direction X and the second direction Y. In an implementation, a maximum rotation angle in the A direction of the prism1105may be smaller than or equal to 15 degrees in a plus (+) A direction, and may be greater than 15 degrees in a minus (−) A direction. The prism1105may move by a range of, e.g., around 20 degrees, or between 10 and 20 degrees, or between 15 and 20 degrees in the plus (+) or minus (−) B direction. The prism1105may move by the same angle in the plus (+) and minus (−) B directions. In another implementation, angles by which the prism1105may move in the plus (+) and minus (−) B directions, respectively may have a difference of about 1 degree therebetween. The prism1105may move the reflective face1107made of the light reflective material in the third direction, e.g., the Z direction parallel to an extension direction of the central axis1106.

The OPFE1111may include a group of m optical lenses (m being a natural number). The group of m optical lenses may move in the second direction Y to change an optical zoom ratio of the camera module1100b. For example, a basic optical zoom ratio of the camera module1100bmay be Z. When the m optical lenses included in the OPFE1111move, the optical zoom ratio of the camera module1100bmay be changed to an optical zoom ratio equal to or higher than 3 Z or 5 Z.

The actuator1131may move the OPFE1111or the optical lens to a specific position. For example, the actuator1131may adjust a position of the optical lens so that the image sensor1142is located at a focal length of the optical lens for accurate sensing.

The image sensing device1141may include an image sensor1142, a control logic1144and a memory1146. The image sensor1142may sense an image of a sensing target using the light L provided through the optical lens. The control logic1144may control all of operations of the camera module1100b. For example, the control logic1144may control an operation of the camera module1100bbased on a control signal provided through a control signal line CSLb.

The memory1146may store therein information used for operation of the camera module1100b, such as calibration data1147. The calibration data1147may include information used when the camera module1100bgenerates image data using the light L provided from the outside. The calibration data1147may include, e.g., information about a degree of rotation, information about a focal length, information about an optical axis, and the like. When the camera module1100bis implemented in a multi-state camera form in which the focal length varies based on a position of the optical lens, the calibration data1147may include a focal length value based on each position (or each state) of the optical lens, and information related to auto focusing.

The storage1155may store therein image data sensed via the image sensor1142. The storage1155may be disposed outside the image sensing device1141, and may be implemented to be stacked on a sensor chip constituting the image sensing device1141. The storage1155may be implemented as an EEPROM (Electrically Erasable Programmable Read-Only Memory).

Referring toFIG.21andFIG.22together, each of the plurality of camera modules1100a,1100b, and1100cmay include a respective actuator1131. Accordingly, each of the plurality of camera modules1100a,1100b, and1100cmay include the same or different calibration data1147based on an operation of the actuator1131included therein.

One camera module (e.g.,1100b) among the plurality of camera modules1100a,1100b, and1100cmay be a camera module in a folded lens form including the prism1105and the OPFE1111as described above, while each of the remaining camera modules (e.g.,1100aand1100c) may be a vertical-type camera module that does not include the prism1105and the OPFE1111.

One camera module (e.g.,1100c) among the plurality of camera modules1100a,1100b, and1100c, may be a depth camera of a vertical form that extracts depth information, e.g., using IR (Infrared Ray). In this case, the application processor1200may merge image data provided from the depth camera and image data provided from another camera module (e.g.,1100aor1100b) to generate a three-dimensional depth image (3D depth image).

At least two camera modules (e.g.,1100aand1100b) among the plurality of camera modules1100a,1100b, and1100cmay have different fields of view (FOVs). In this case, e.g., at least two of the plurality of camera modules1100a,1100b, and1100c, e.g., optical lenses of at least two (e.g.,1100aand1100b) of the plurality of camera modules1100a,1100b, and1100cmay be different from each other. FOVs of the plurality of camera modules1100a,1100b, and1100cmay be different from each other. In this case, the optical lenses respectively included in the plurality of camera modules1100a,1100b, and1100cmay also be different from each other.

The plurality of camera modules1100a,1100b, and1100cmay be physically separated from each other. Thus, instead of a structure in which a sensing area of one image sensor1142is divided into a plurality of sub-areas which correspond to the plurality of camera modules1100a,1100b, and1100c, an individual image sensor1142may be disposed in each of the plurality of camera modules1100a,1100b, and1100c.

Referring toFIG.21, the application processor1200may include an image processing device1210, a memory controller1220, and an internal memory1230. The application processor1200may be implemented to be separated from the plurality of camera modules1100a,1100b, and1100c. For example, the application processor1200and the plurality of camera modules1100a,1100b, and1100cmay be implemented as separate semiconductor chips.

The image processing device1210may include a plurality of auxiliary image processors1212a,1212b, and1212c, an image generator1214and a camera module controller1216. The number of the auxiliary image processors1212a,1212b, and1212cmay correspond to the number of camera modules1100a,1100b, and1100c. Image data generated from each of the camera modules1100a,1100b, and1100cmay be provided to each of the auxiliary image processors1212a,1212b, and1212cvia each of image signal lines ISLa, ISLb, and ISLc separated from each other. For example, the image data generated from the camera module1100amay be transmitted to the auxiliary image processor1212avia the image signal line ISLa. The image data generated from the camera module1100bmay be transmitted to the auxiliary image processor1212bvia the image signal line ISLb. The image data generated from the camera module1100cmay be transmitted to the auxiliary image processor1212cvia the image signal line ISLc. The image data transmission may be performed, e.g., using a camera serial interface (CSI) based on a Mobile Industry Processor Interface (MIPI).

One auxiliary image processor may correspond to a plurality of camera modules. For example, the auxiliary image processor1212aand the auxiliary image processor1212cmay not be implemented separately from each other, but may be integrated into one auxiliary image processor. The image data provided from the camera module1100aand the camera module1100cmay be selected via a selection element, e.g., a multiplexer, and then may be provided to the integrated auxiliary image processor.

The image data provided to each of the auxiliary image processors1212a,1212b, and1212cmay be provided to the image generator1214. The image generator1214may generate an output image using the image data provided from each of the auxiliary image processors1212a,1212b, and1212cand based on image generation information or a mode signal. The image generator1214may merge at least a portion of the image data generated from the camera modules1100a,1100b, and1100chaving different FOVs, based on the image generation information or the mode signal, and thus may generate the output image as the merging result. The image generator1214may select one of the image data generated from the camera modules1100a,1100b, and1100chaving different FOVs, and based on the image generation information or the mode signal and thus may generate the output image as the selected data.

The image generation information may include a zoom signal or a zoom factor. The mode signal may be, e.g., a signal based on a mode selected by a user. When the image generation information is the zoom signal or the zoom factor, and the camera modules1100a,1100b, and1100chave different FOVs, the image generator1214may perform different operations based on types of the zoom signal. For example, when the zoom signal is a first signal, the image generator may merge the image data output from the camera module1100aand the image data output from the camera module1100cwith each other, and generate the output image using the merged image data, and the image data output from the camera module1100bnot used in the merging operation. When the zoom signal is a second signal different from the first signal, the image generator1214may not perform such an image data merging operation, but may select one of the image data output from the camera modules1100a,1100b, and1100cand may generate the selected data as the output image.

The image generator1214may receive a plurality of image data having different exposure times from at least one of the plurality of auxiliary image processors1212a,1212b, and1212c, and may perform HDR (high dynamic range) processing on the received plurality of image data, thereby generating merged image data having an increased dynamic range.

The camera module controller1216may provide a control signal to each of the camera modules1100a,1100b, and1100c. The control signal generated from the camera module controller1216may be provided to a corresponding one of the camera modules1100a,1100b, and1100cvia a corresponding one of the control signal lines CSLa, CSLb, and CSLc separated from each other.

One of the plurality of camera modules1100a,1100b, and1100cmay be designated as a master camera (e.g.,1100b) based on the image generation information including the zoom signal or the mode signal, while each of the remaining camera modules (e.g.,1100aand1100c) may be designated as a slave camera. This designation information may be included in the control signal and may be provided to a corresponding one of the camera modules1100a,1100b, and1100cvia a corresponding one of the control signal lines CSLa, CSLb, and CSLc separated from each other.

The camera module acting as the master or slave camera may vary based on the zoom factor or an operation mode signal. For example, when the FOV of the camera module1100ais larger than that of the camera module1100b, and the zoom factor indicates a low zoom ratio, the camera module1100bmay act as a master camera, while the camera module1100amay act as a slave camera. Conversely, when the zoom factor indicates a high zoom ratio, the camera module1100amay act as a master camera, while the camera module1100bmay act as a slave camera.

The control signal from the camera module controller1216provided to each of the camera modules1100a,1100b, and1100cmay include a sync enable signal. For example, when the camera module1100bis the master camera, and each of the camera modules1100aand1100cis the slave camera, the camera module controller1216may transmit the sync enable signal to the camera module1100b. Upon receiving such a sync enable signal, the camera module1100bmay generate a sync signal based on the provided sync enable signal, and may provide the generated sync signal to the camera modules1100aand1100cvia a sync signal line SSL. The camera module1100band the camera modules1100aand1100cmay transmit the image data to the application processor1200while the camera module1100band the camera modules1100aand1100care synchronized with each other using the sync signal.

The control signal from the camera module controller1216provided to each of the plurality of camera modules1100a,1100b, and1100cmay include mode information according to the mode signal. Based on this mode information, the plurality of camera modules1100a,1100b, and1100cmay operate in a first operation mode or a second operation mode in relation to a sensing speed.

In a first operation mode, the plurality of camera modules1100a,1100b, and1100cmay generate an image signal at a first speed (for example, may generate an image signal at a first frame rate), may encode the image signal at a second speed higher than the first speed (for example, encode the image signal at a second frame rate higher than the first frame rate) and may transmit the encoded image signal to the application processor1200. The second speed may be lower than or equal to 30 times of the first speed. The application processor1200may store the received image signal, i.e., the encoded image signal, in the internal memory1230provided therein, or the external memory1400external to the application processor1200, and then, read and decode the encoded image signal from the internal memory1230or the external memory1400, and then, display image data generated based on the decoded image signal. For example, a corresponding auxiliary processor among the plurality of auxiliary image processors1212a,1212b, and1212cof the image processing device1210may perform the decoding, and may perform the image processing on the decoded image signal.

In a second operation mode, the plurality of camera modules1100a,1100b, and1100cmay generate an image signal at a third speed lower than the first speed (for example, generate an image signal at a third frame rate lower than the first frame rate), and then transmit the image signal to the application processor1200. The image signal provided to the application processor1200may be an unencoded signal. The application processor1200may perform image processing on the received image signal or may store the image signal in the internal memory1230or the external memory1400.

The PMIC1300may supply power, e.g., a power supply voltage to each of the plurality of camera modules1100a,1100b, and1100c. For example, the PMIC1300may supply first power to the camera module1100athrough a first power signal line PSLa, supply second power to the camera module1100bthrough a second power signal line PSLb, and supply third power to the camera module1100cthrough a third power signal line PSLc, under control of the application processor1200. The PMIC1300may generate power corresponding to each of the plurality of camera modules1100a,1100b, and1100cand adjust a power level, in response to a power control signal PCON from the application processor1200. The power control signal PCON may include an operation mode-based power adjustment signal for the plurality of camera modules1100a,1100b, and1100c. For example, the operation mode may include a low power mode. The power control signal PCON may include information about a camera module operating in the low power mode and information about a set power level. Levels of powers respectively provided to the plurality of camera modules1100a,1100b, and1100cmay be the same as or different from each other. Further, the level of the power may vary dynamically.

By way of summation and review, autofocusing may be used to automatically set a focus of an image sensor. Phase difference autofocusing (PDAF) may be considered for a fast focus detection speed. In the PDAF, light passing through an imaging lens is divided into light beams, which in turn are detected at different focus detection pixels, and then a focusing lens automatically operates to allow detected signals to have the same intensity at the same phase to adjust a focal length. It is useful to detect foci of various directions efficiently and automatically. Autofocusing may be performed using a separate AF sensor having a size that is much smaller than that of an image sensor, or autofocusing may be performed by placing a focus detection pixel separately from an image detection pixel into a portion of the image sensor and using an AF module inside the image sensor. Another structure uses a dual pixel image sensor, in which every one of the focus detection pixels or every one of the image detection pixels is composed of a pair of photoelectric conversion elements to increase a focus detection speed. The dual pixel image sensor may perform the phase-difference autofocusing detection operation on a pixel-by-pixel basis to significantly improve focus detection speed and accuracy. In this structure, every one of the image detection pixels is composed of the dual pixels, while a separate focus detection pixel is absent. Thus, autofocusing may be accurately and quickly performed without degrading an image resolution.

As described above, embodiments may to provide an image sensor that efficiently performs an autofocusing operation on a diagonal direction. Embodiments may provide an image sensing system that efficiently performs an autofocusing operation on a diagonal direction. Embodiments may provide an image sensor including a dual pixel that efficiently performs an autofocusing operation on various directions.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. Where used herein, the terms “first,” “second,” “third,” etc., are simply to aid in referring to various features, and do not indicate or imply a specific order unless expressly stated as such. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.