Patent ID: 12218189

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “on,” “above,” “over,” “underneath,” “beneath,” “proximate,” “distal,” “lower,” “higher,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The present disclosure is directed to semiconductor devices and methods for manufacturing the same. The semiconductor devices may be power MOSFETs, which may be bipolar, complementary metal-oxide semiconductor (CMOS) diffusion metal-oxide semiconductor (DMOS) devices (bipolar-CMOS-DMOS (BCD) devices), for example, but not limited to, LDMOS transistors (lateral diffused metal oxide semiconductor field effect transistors) or other suitable transistors/power devices.

FIG.1is a flow diagram illustrating a method100for manufacturing a semiconductor device in accordance with some embodiments.FIGS.2to11illustrate schematic views of the intermediate stages of the method100.

Referring toFIGS.1and2, the method100begins at step101, where a trench210is formed in a semiconductor layer21. In some embodiments, the semiconductor layer21may include crystalline silicon, polycrystalline silicon, or a combination thereof. Other suitable semiconductor materials are within the contemplated scope of the present disclosure. The trench210may be formed using a photolithography process and an etching process. The photolithography process may include, for example, but not limited to, coating a photoresist (not shown), soft-baking, exposing the photoresist through a photomask, post-exposure baking, and developing the photoresist, followed by hard-baking so as to form a patterned photoresist on the semiconductor layer21. The etching process may be implemented by etching the semiconductor layer21through the patterned photoresist using, for example, but not limited to, a dry etching process, a wet etching process, other suitable processes, or combinations thereof.

Referring toFIGS.1and3, the method100proceeds to step102, where a dielectric layer220is formed on the semiconductor layer21to fill the trench210shown inFIG.2. The dielectric layer220may include, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. Other suitable dielectric materials are within the contemplated scope of the present disclosure. The dielectric layer220may be deposited by, for example, but not limited to, sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable processes.

Referring toFIGS.1and4, the method100proceeds to step103, where a planarization process is conducted to remove an excess of the dielectric layer220shown inFIG.3, to expose the semiconductor layer21so as to obtain a dielectric film22. The dielectric film22may also be referred to as a shallow trench isolation (STI) region. Step103may be implemented using a chemical mechanical polishing (CMP) process or other suitable techniques. Other suitable processes may be used for formation of the STI region22.

Referring toFIGS.1and5, the method100proceeds to step104, where an anti-type doping layer23is formed beneath the STI region22. In some embodiments, the anti-type doping layer23may have a thickness (T) ranging from about 50 Å to about 200 Å, although a slightly larger or smaller thickness may be used based on the device performance or the designs of the product to be produced. Step104may be implemented by (i) forming a patterned mask24on the semiconductor layer21to expose the STI region22and a first surrounding surface of the semiconductor layer21around the STI region22, and (ii) doping a region beneath the STI region22through the patterned mask24using an ion implantation process or other suitable processes so as to form the anti-type doping layer23. After step104, the patterned mask24may be removed. For an N-type MOS device, a P-type dopant is used in the ion implantation process for forming the anti-type doping layer23with a P-type conductivity, and may include, for example, but not limited to, boron, BF2, indium, the like, or combinations thereof. For a P-type MOS device, an N-type dopant is used in the ion implantation process for forming the anti-type doping layer23with an N-type conductivity, and may include, for example, but not limited to, arsenic, phosphorus, the like, or combinations thereof. Other suitable P-type dopants and N-type dopants are within the contemplated scope of the present disclosure. In alternative embodiments, the patterned mask24may be replaced by a patterned photoresist. Other suitable processes may be used for formation of the anti-type doping layer23.

Referring toFIGS.1and6, the method100proceeds to step105, where a drift region211is formed in the semiconductor layer21to have a doping concentration lower than that of the anti-type doping layer23. After step105, the anti-type doping layer23is located between the drift region211and the STI region22. Step105may be implemented by (i) forming a patterned mask25on the semiconductor layer21to expose the STI region22and a second surrounding surface of the semiconductor layer21around the STI region22and the anti-type doping layer23, and (ii) doping the semiconductor layer21through the patterned mask25using an ion implantation process or other suitable processes so as to form the drift region211. After step105, the patterned mask25may be removed. In some embodiments, the drift region211has a first type conductivity, and the anti-type doping layer23has a second type conductivity opposite to the first type conductivity. Thus, the drift region211may be formed using the above-mentioned N-type dopant for forming the N-type MOS device, or using the above-mentioned P-type dopant for forming the P-type MOS device. In some embodiments, an upper surface of the drift region211(which corresponds to the second surrounding surface of the semiconductor layer21mentioned above) may have a first surface portion211aand a second surface portion211bwhich are located at two opposite sides of the STI region22and the anti-type doping layer23. In alternative embodiments, the patterned mask25may be replaced by a patterned photoresist. Other suitable processes may be used for formation of the drift region211. Please note that the term “anti-type doping layer” means a layer having a conductivity type opposite to that of the drift region211.

Referring toFIGS.1and7, the method100proceeds to step106, where a well region212is formed in the semiconductor layer21. Step106may be implemented by (i) forming a patterned mask26on the semiconductor layer21to cover the STI region22, the anti-type doping layer23, and the drift region211, and (ii) doping the semiconductor layer21through the patterned mask26using an ion implantation process or other suitable processes so as to form the well region212. After step106, the patterned mask26may be removed. In some embodiments, the well region212has the second type conductivity, and thus may be formed using the above-mentioned P-type dopant for forming the N-type MOS device, or using the above-mentioned N-type dopant for forming the P-type MOS device. In some embodiments, an upper surface of the well region212may have a first surface portion212aand a second surface portion212bwhich are proximate to and distal from the STI region22, respectively. In alternative embodiments, the patterned mask26may be replaced by a patterned photoresist. Other suitable processes may be used for formation of the well region212.

Referring toFIGS.1and8, the method100proceeds to step107, where a gate structure27is formed on the semiconductor layer21. In some embodiments, the gate structure27includes a gate dielectric271formed on the semiconductor layer21, a gate electrode272formed on the gate dielectric271, and two spacers273formed at two opposite sides of a stack of the gate electrode272and the gate dielectric271. The gate dielectric271may include, for example, but not limited to, silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof. Other suitable gate dielectric materials are within the contemplated scope of the present disclosure. The gate electrode272may include, for example, but not limited to, a metallic material, a metal compound, polycrystalline silicon, or doped silicon. Other suitable gate materials are within the contemplated scope of the present disclosure. The metallic material may include, for example, but not limited to, silver, aluminum, copper, tungsten, nickel, other suitable materials, alloys thereof, or combinations thereof. The metal compound may include, for example, but not limited to, titanium nitride, tantalum nitride, metal silicide, other suitable materials, or combinations thereof. The spacers273may include, for example, but not limited to, silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof. Other suitable spacer materials are within the contemplated scope of the present disclosure. The stack of the gate electrode272and the gate dielectric271may be formed by, for example, a process including (i) sequentially depositing a gate dielectric layer (not shown) and a gate electrode layer (not shown), and (ii) patterning the gate dielectric layer and the gate electrode layer to form the gate dielectric271and the gate electrode272using a photolithography process and an etching process similar to those described in step101. The spacers273may be formed by, for example, a process including (i) depositing a spacer-forming layer over the stack of the gate electrode272and the gate dielectric271, and (ii) anisotropically etching the spacer-forming layer. In some embodiments, the stack of the gate dielectric271and the gate electrode272may be formed over a portion of the STI region22, a portion of the anti-type doping layer23, the second surface portion211bof the drift region211, and a part212a1of the first surface portion212aof the well region212. Other suitable processes may be also used for forming the gate structure27.

Referring toFIGS.1and9, the method100proceeds to step108, where a body contact28is formed in the well region212. Step108may be implemented by (i) forming a patterned mask29on the semiconductor layer21to expose the second surface portion212bof the well region212, and (ii) doping the well region212through the patterned mask29using an ion implantation process or other suitable processes so as to form the body contact28within the well region212. After step108, the patterned mask29may be removed. In some embodiments, the body contact28has the second type conductivity, and thus may have a higher doping concentration than that of the well region212. Therefore, the body contact28may be formed using the above-mentioned P-type dopant for forming the N-type MOS device, or using the above-mentioned N-type dopant for forming the P-type MOS device. In alternative embodiments, the patterned mask29may be replaced by a patterned photoresist. Other suitable processes may be also used for forming the body contact28.

Referring toFIGS.1and10, the method100proceeds to step109, where a source area31and a drain area32are respectively formed within the well region212and the drift region211and may have a doping concentration higher than that of the anti-type doping layer23. Step109may be implemented by (i) forming a patterned mask30on the semiconductor layer21to expose a remaining part212a2of the first surface portion212aof the well region212and to expose the first surface portion211aof the drift region211, and (ii) doping the well region212and the drift region211through the patterned mask30using an ion implantation process or other suitable processes so as to form the source area31within the well region212and the drain area32within the drift region211. After step109, the patterned mask30may be removed. In some embodiments, the source area31and the drain area32have the first type conductivity, and thus may be formed using the above-mentioned N-type dopant for forming the N-type MOS device, or using the above-mentioned P-type dopant for forming the P-type MOS device. In alternative embodiments, the patterned mask30may be replaced by a patterned photoresist. Other suitable processes may be also used for forming the source area31and the drain area32.

Referring toFIG.11, after removing the patterned mask30, a semiconductor device200is obtained and a channel length (L) is defined by a distance between the drift region211and the source area31. The anti-type doping layer23is located between the drift region211and the STI region22. The STI region22is located between the source area31and the drain area32. The well region212is disposed to separate the source area31and the body contact28from the drift region211.

In some embodiments, in the semiconductor device200, the doping concentration of the anti-type doping layer23may be higher than that of the drift region211by two orders of magnitude and may be lower than that of the drain area32by two orders of magnitude. For example, when the doping concentration of the anti-type doping layer23ranges from about 1×1018atom/cm 3 to about 1×1019atom/cm3, the doping concentration of the drift region211may range from about 1×1016atom/cm 3 to about 1×1017atom/cm3, and the doping concentration of the drain area32may range from about 1×1020atom/cm3to about 1×1021atom/cm3. In some embodiments, steps101to109may not be performed in the above order. In alternative embodiments, other suitable methods may also be applied for forming the semiconductor device200. In yet alternative embodiments, additional features may be added in the semiconductor device200, and some features in the semiconductor device200may be modified, replaced, or eliminated without departure of the spirit and scope of the present disclosure.

In the semiconductor device200, dielectric damages (electron trapping) may be induced by certain operations or process fabrications, and may be formed on a bottom wall and/or sidewalls of the dielectric film (STI region)22. During a reading operation, an on-current flows from the source area31, through the well region212and the drift region211, and then into the drain area32. When the anti-type doping layer23is not provided, the electron trapping may produce coulomb forces affecting the mobility of the electrons of the on-current. Although this disclosure is not bound by any theory, it is believed that in the semiconductor device200, because the anti-type doping layer23with the thickness (T) is provided underneath the dielectric film22and has a conductivity type opposite to that of the drift region211, a current path of an on-current in the drift region211may be changed, for example, to flow away from the dielectric film22. Therefore, the on-current is less likely to be influenced by coulomb forces of the electron trapping (i.e., the influence of the dielectric damages on the on-current is reduced), and the semiconductor device200may have improved operation performance and reliability.

In alternative embodiments, a doping layer (which may be also exemplified as the anti-type doping layer23) is formed between a semiconductor region (which may be also exemplified as the drift region211) and a dielectric film (which may be also exemplified as the STI region22), and has a conductivity type to direct a current path away from the dielectric film, thereby reducing an influence of dielectric damages of the dielectric film on the semiconductor region.

FIG.12illustrates a schematic view of a semiconductor device200A in accordance with some embodiments. The semiconductor device200A is similar to the semiconductor device200except that, in the semiconductor device200A, an additional STI region22′ is formed between the source area31and the body contact28to isolate the source area31from the body contact28.

The semiconductor device200A may be made using a method100A similar to the method100except for steps101,102,103, and106.FIGS.13to16illustrate schematic views of the intermediate stages in steps101,102,103, and106of the method100A.

Referring toFIG.13, the method100A begins at step101, where a trench210and a trench210′ are formed in the semiconductor layer21. The formation of the trenches210,210′ is similar to that described in step101of the method100, and the details thereof are omitted for the sake of brevity.

Referring toFIG.14, the method100A proceeds to step102, a dielectric layer220is formed on the semiconductor layer21to fill the trenches210,210′ shown inFIG.13. The materials and formation for the dielectric layer220are similar to those described in step102of the method100, and the details thereof are omitted for the sake of brevity.

Referring toFIG.15, the method100A proceeds to step103, where a planarization process is conducted to remove an excess of the dielectric layer220shown inFIG.14, to expose the semiconductor layer21so as to obtain the STI region22and the additional STI region22′. The planarization process may be similar to that described in step103of the method100, and the details thereof are omitted for the sake of brevity.

Referring toFIG.16, the method100A proceeds to step106, where the well region212is formed in the semiconductor layer21to have a first surface portion212aand a second surface portion212bat two opposite sides of the additional STI region22′. Step106of the method100A may be similar to step106of the method100, and the details thereof are omitted for the sake of brevity.

In alternative embodiments, other suitable methods may also be applied for forming the semiconductor device200A. In yet alternative embodiments, additional features may be added in the semiconductor device200A, and some features in the semiconductor device200A may be modified, replaced, or eliminated without departure of the spirit and scope of the present disclosure.

FIG.17illustrates a schematic view of a semiconductor device200B in accordance with some embodiments. The semiconductor device200B is similar to the semiconductor device200A except that, in the semiconductor device200B, a drift region211and a lightly doped source region311are formed within the semiconductor layer21, and a remaining part of the semiconductor layer21serves as a well region213. The well region213is located between the lightly doped source region311and the drift region211. In addition, a channel length (L) is defined by a distance between the lightly doped source region311and the drift region211. The lightly doped source region311may have the first type conductivity, and may have a doping concentration lower than that of the source area31. The well region213has the second type conductivity. The lightly doped source region311is disposed to separate the source area31and the body contact28from the well region213.

The semiconductor device200B may be made using a method100B similar to the method100A except that in the method100B: (i) the semiconductor layer21may be lightly doped to have a P-type conductivity for the N-type MOS device or to have an N-type conductivity for the P-type MOS device; (ii) in step105, the drift region211, the lightly doped source region311, and the well region213may be formed simultaneously; and (iii) step106may be omitted.

FIG.18illustrates a schematic view of the intermediate stage in step105of the method100B. In step105of the method100B, the drift region211and the lightly doped source region311may be formed simultaneously by (i) forming a patterned mask33on the semiconductor layer21to permit the patterned mask33to be spaced apart from the STI region22and the anti-type doping layer23by a predetermined distance, and (ii) doping the semiconductor layer21through the patterned mask33using an ion implantation process or other suitable processes so as to form the drift region211and the lightly doped source region311at two opposite sides of the patterned mask33. After step105of the method100B, the patterned mask33may be removed, and a remaining part of the semiconductor layer21may serve as the well region213. In alternative embodiments, the patterned mask33may be replaced by a patterned photoresist.

In alternative embodiments, other suitable methods may also be applied for forming the semiconductor device200B. In yet alternative embodiments, additional features may be added in the semiconductor device200B, and some features in the semiconductor device200B may be modified, replaced, or eliminated without departure of the spirit and scope of the present disclosure.

FIG.19illustrates a schematic view of a semiconductor device200C in accordance with some embodiments. The semiconductor device200C is similar to the semiconductor device200except that in the semiconductor device200C, a dielectric film (field oxide region)33and a gate structure37are formed to replace the STI region22and the gate structure27of the semiconductor device200, respectively.

The semiconductor device200C may be made using a method100C similar to the method100except that in the method100C, steps301to307are used for replacement of steps101to107of the method100.FIG.20is a flow diagram illustrating steps301to307of the method100C in accordance with some embodiments.FIGS.21to28illustrate schematic views of the intermediate stages of the method100C.

Referring toFIGS.20and21, the method100C begins at step301, where a first dielectric layer34and a second dielectric layer35are sequentially formed over a semiconductor layer21. The materials for the semiconductor layer21is similar to those described in step101, and the details thereof are omitted for the sake of brevity. In some embodiments, the first dielectric layer34may be formed by deposition similar to that for the dielectric layer220described in step102, and/or by a thermal oxidation process which may implemented by introducing a thermal vapor to oxidize a surface of the semiconductor layer21. In some embodiments, the second dielectric layer35has a material different from that of the first dielectric layer34, and may be formed by deposition similar to that for the dielectric layer220described in step102. Other suitable processes may be used for formation of the first dielectric layer34and the second dielectric layer35.

Referring toFIGS.20and22, the method100C proceeds to step302, where a selective etching process is conducted through a patterned photomask36to partially and selectively etching the second dielectric layer35and to expose a portion of the dielectric layer34. Step302may be implemented using, for example, but not limited to, a dry etching process, a wet etching process, other suitable processes, or combinations thereof. In alternative embodiments, the patterned photomask36may be replaced by a patterned mask layer.

Referring toFIGS.20and23, the method100C proceeds to step303, where a dielectric film33is formed in replacement of the exposed portion of the first dielectric layer34. The dielectric film33may include a dielectric material similar to those for the dielectric layer220described in step102, but the material of the dielectric film33is different from those of the first dielectric layer34and the second dielectric layer35. Step303may be implemented by (i) removing the patterned mask layer36shown inFIG.22using an etchant which also etches the exposed portion of the first dielectric layer34and the semiconductor layer21beneath the first dielectric layer34to expose a portion of the semiconductor layer21, (ii) forming the dielectric film33on the exposed portion of the semiconductor layer21(which is not covered by the second dielectric layer35), and (iii) removing the second dielectric layer35and the remaining first dielectric layer34. Other suitable processes may be used for formation of the dielectric film33. The dielectric film33may be also referred to as a field oxide (FOX) region.

Referring toFIGS.20and24, the method100C proceeds to step304, where an anti-type doping layer23is formed beneath the FOX region33using a patterned mask24. The formation of the anti-type doping layer23in step304may be similar to that described in step104, and the details thereof are omitted for the sake of brevity.

Referring toFIGS.20and25, the method100C proceeds to step305, where a drift region211is formed in the semiconductor layer21using a patterned mask25. Step305may be implemented in a manner similar to step105, and the details thereof are omitted for the sake of brevity. After step305, an upper surface of the drift region211may have a first surface portion211aand a second surface portion211bwhich are located at two opposite sides of the FOX region33and the anti-type doping layer23.

Referring toFIGS.20and26, the method100C proceeds to step306, where a well region212is formed in the semiconductor layer21. Step306may be implemented in a manner similar to step106, and the details thereof are omitted for the sake of brevity. After step306, an upper surface of the well region212may have a first surface portion212aand a second surface portion212bwhich are proximate to and distal from the FOX region33, respectively.

Referring toFIGS.20and27, the method100C proceeds to step307, where a gate structure37is formed on the semiconductor layer21. The gate structure37include s a gate dielectric371formed on the semiconductor layer21and a gate electrode372formed on the gate dielectric371. The materials and formation for the gate dielectric371and the gate electrode372may be similar to those for the gate dielectric271and the gate electrode272described in step107, and the details thereof are omitted for the sake of brevity. In some embodiments, the gate structure37may be formed over a portion of the FOX region33, a portion of the anti-type doping layer23, the second surface portion211bof the drift region211, and a part212a1of the first surface portion212aof the well region212. The subsequent steps for manufacturing the semiconductor device200C may be similar to steps108and109, and are omitted for the sake of brevity.

In some embodiments, the steps for manufacturing the semiconductor device200C may not be performed in the above order. In alternative embodiments, other suitable methods may also be applied for forming the semiconductor device200C. In yet alternative embodiments, additional features may be added in the semiconductor device200C, and some features in the semiconductor device200C may be modified, replaced, or eliminated without departure of the spirit and scope of the present disclosure.

In the semiconductor device200,200A,200B,200C of this disclosure, because the anti-type doping layer23is provided between the drift region211and the dielectric film (the STI region22or the FOX region33) and has a conductivity type opposite to that of the drift region211, a current in the drift region211is less likely to be influenced by dielectric damages (if any) of the dielectric film22or23. Therefore, the semiconductor device200,200A,200B,200C of this disclosure may have improved performance, such as improved reliability, less leakage current, and so on. In addition, the formation of the anti-type doping layer23may be implanted simply after formation of the dielectric film22or33, and may not influence formation of other elements in the semiconductor device200,200A,200B,200C. In alternative embodiments of this disclose, a doping layer (which may be also exemplified as the anti-type doping layer23) may be provided to direct a current path in a semiconductor region (which may be also exemplified as the drift region211) away from a dielectric film (which may be also exemplified as the STI region22or the FOX region33), thereby reducing an influence of dielectric damages of the dielectric film on the semiconductor region.

In accordance with some embodiments of the present disclosure, a semiconductor device includes a drift region, a dielectric film, and an anti-type doping layer. The drift region has a first type conductivity. The anti-type doping layer is located between the drift region and the dielectric film, and has a second type conductivity opposite to the first type conductivity so as to change a current path of a current in the drift region, to thereby prevent the current from being influenced by the dielectric film.

In accordance with some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes: forming a dielectric film in a semiconductor layer; forming an anti-type doping layer in the semiconductor layer beneath the dielectric film; and forming a drift region in the semiconductor layer such that the anti-type doping layer is located between the dielectric film and the drift region. The drift region has a first type conductivity and the anti-type doping layer has a second type conductivity opposite to the first type conductivity.

In accordance with some embodiments of the present disclosure, a method for reducing an influence of a dielectric film on a semiconductor region is provided. The method includes forming a doping layer which is located between the semiconductor region and the dielectric film and which has a conductivity type so as to direct a current path away from the dielectric film, thereby reducing the influence of the dielectric film.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes or structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.