Patent ID: 12237364

DETAILED DESCRIPTION

The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments are shown. The present disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will filly convey the scope of the present disclosure to those skilled in the art.

It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it may be directly on, connected, or coupled to the other element or layer or one or more intervening elements or layers may also be present. When an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present. For example, when a first element is described as being “coupled” or “connected” to a second element, the first element may be directly coupled or connected to the second element or the first element may be indirectly coupled or connected to the second element via one or more intervening elements.

In the figures, dimensions of the various elements, layers, etc. may be exaggerated for clarity of illustration. The same reference numerals designate the same elements. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Further, the use of “may” when describing embodiments of the present disclosure relates to “one or more embodiments of the present disclosure.” Expressions, such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. As used herein, the terms “use,” “using,” and “used” may be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively. As used herein, the terms “substantially,” “about,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent variations in measured or calculated values that would be recognized by those of ordinary skill in the art.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, and/or sections, these elements, components, regions, layers, and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section discussed below could be termed a second element, component, region, layer, or section without departing from the teachings of example embodiments.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” or “over” the other elements or features. Thus, the term “below” may encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

The terminology used herein is for the purpose of describing particular example embodiments of the present disclosure and is not intended to be limiting of the described example embodiments of the present disclosure. As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “includes,” “including,” “comprises,” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Also, any numerical range disclosed and/or recited herein is intended to include all sub-ranges of the same numerical precision subsumed within the recited range. For example, a range of “1.0 to 10.0” is intended to include all subranges between (and including) the recited minimum value of 1.0 and the recited maximum value of 10.0, that is, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein, and any minimum numerical limitation recited in this specification is intended to include all higher numerical limitations subsumed therein. Accordingly, Applicant reserves the right to amend this specification, including the claims, to expressly recite any sub-range subsumed within the ranges expressly recited herein. All such ranges are intended to be inherently described in this specification such that amending to expressly recite any such subranges would comply with the requirements of 35 U.S.C. § 112(a) and 35 U.S.C. § 132(a).

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

FIG.1is a plan view of a display device according to an embodiment.

Referring toFIG.1, a display device10displays (e.g., is configured to display) a moving image and/or a still image. The display device10may refer to all electronic devices that include a display screen, for example, televisions, laptop computers, monitors, billboards, the Internet of Things (IoT) devices, mobile phones, smartphones, tablet personal computers (PCs), electronic watches, smartwatches, watch phones, head mounted displays, mobile communication terminals, electronic organizers, electronic books, portable multimedia players (PMPs), navigation devices, game machines, digital cameras, camcorders, and the like.

The display device10includes a display panel having a display screen. Examples of the display panel include an inorganic light emitting diode display panel, an organic light emitting diode display panel, a quantum dot light emitting display panel, a plasma display panel, a field emission display panel, and the like. Hereinafter, an embodiment in which an inorganic light emitting diode display panel is applied as an example of the display panel will be described by way of example, but the present disclosure is not limited thereto, and the same technical idea may be applied to other display panels if applicable.

Hereinafter, a first direction DR1, a second direction DR2, and a third direction DR3are defined in the drawings for describing the display device10. The first direction DR1and the second direction DR2may be perpendicular to each other in one plane. The third direction DR3may be perpendicular to the plane in which the first direction DR1and the second direction DR2are positioned. The third direction DR3is perpendicular to each of the first direction DR1and the second direction DR2. The third direction DR3may refer to a thickness direction of the display device10.

The display device10may have a rectangular shape, in a plan view, which includes long sides and short sides with the first direction DR1being longer than the second direction DR2. A corner portion at where the long side and the short side of the display device10meet, in a plan view, may be right-angled, but it is not limited thereto and may have a rounded curved shape. The shape of the display device10in a plan view is not limited to that described above, and the display device10may have other shapes, such as a square shape, a quadrangular shape with rounded corners (e.g., vertices), a polygonal shape, and a circular shape.

A display surface of the display device10may be disposed on one side in the third direction DR3, which is the thickness direction. Unless otherwise stated, “upper portion” refers to one side in the third direction DR3and refers to a display direction, and “upper surface” refers to a surface facing one side in the third direction DR3. In addition, “lower portion” refers to the other (e.g., the opposite) side in the third direction DR3and refers to a direction opposite to the display direction, and “lower surface” refers to a surface facing the other side in the third direction DR3. In addition, “left”, “right”, “upper”, and “lower” refer to directions when the display panel10is viewed in a plan view. For example, “right side” refers to one side in the first direction DR1, “left side” refers to the other side in the first direction DR1, “upper side” refers to one side in the second direction DR2, and “lower side” refers to the other side in the second direction DR2.

The display device10may have a display area DPA and a non-display area NDA. The display area DPA is an area in which a screen is provided (e.g., where an image is displayed), and the non-display area NDA is an area in which a screen is not provided (e.g., where an image is not displayed).

A shape of the display area DPA may follow the shape of the display device10. For example, the display area DPA may have a rectangular shape in a plan view, similar to the overall shape of the display device10. The display area DPA may occupy substantially the center of the display device10.

The display area DPA may include a plurality of pixels PX. The pixel PX may refer to a minimum unit repeated for display. The plurality of pixels PX may be arranged in a matrix pattern.

The non-display area NDA may be disposed around (e.g., may extend around a periphery of) the display area DPA. The non-display area NDA may entirely or partially surround (or extend around the periphery of) the display area DPA. In an embodiment, the display area DPA may have a rectangular shape, and the non-display area NDA may be disposed adjacent to four sides of the display area DPA. The non-display area NDA may form a bezel of the display device10. Wirings, circuit drivers, or a pad part on which an external device is mounted, which are included in the display device10, may be disposed in the non-display area NDA.

FIG.2is a schematic layout view illustrating a layout (or arrangement) of emission areas and sub-areas of the display device10shown inFIG.1according to an embodiment.

Referring toFIG.2, each pixel PX may include a plurality of sub-pixels SPX emitting light of different colors to display full color (e.g., to display full color images). Each pixel PX may include a first sub-pixel SPX1configured to emit light of a first color, a second sub-pixel SPX2configured to emit light of a second color, and a third sub-pixel SPX3configured to emit light of a third color. For example, the first color may be red, the second color may be green, and the third color may be blue. Although it is illustrated inFIG.2that one pixel PX includes three sub-pixels SPX, the present disclosure is not limited thereto. For example, one pixel PX may also include a greater number of sub-pixels SPX.

As described above, the respective pixels PX including the plurality of sub-pixels SPX may be alternately arranged in the matrix pattern (or the matrix direction). In an embodiment, shapes, in a plan view, and arrangements of the sub-pixels SPX in each pixel PX may be the same as each other. For example, each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3may have a rectangular shape, in a plan view, including short sides in the first direction DR1and long sides in the second direction DR2, and the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3of each pixel PX may be arranged along the second direction DR2. Accordingly, a plurality of first sub-pixels SPX1may be arranged side-by-side (e.g., arranged adjacent to each other) along the second direction DR2, a plurality of second sub-pixels SPX2may be arranged side-by-side along the second direction DR2, and a plurality of third sub-pixels SPX3may be arranged side-by-side along the second direction DR2. For example, the same sub-pixels SPX may be arranged side-by-side along the second direction DR2, and the first to third sub-pixels SPX1, SPX2, and SPX3may be alternately and repeatedly disposed along the first direction DR1.

Each pixel PX may have an emission area EMA and a non-emission area NEM. The emission area EMA may be an area in which a light emitting element ED, to be described later (see, e.g.,FIG.4), is disposed and light emitted from the light emitting element ED is emitted, and the non-emission area NEM may be an area in which the light emitting element ED is not disposed and light emitted from the light emitting element ED is not emitted.

The emission area EMA may have a first emission area EMA1, a second emission area EMA2, and a third emission area EMA3. The first emission area EMA1may be an emission area EMA of the first sub-pixel SPX1, the second emission area EMA2may be an emission area EMA of the second sub-pixel SPX2, and the third emission area EMA3may be an emission area EMA of the third sub-pixel SPX3.

In an embodiment, the light emitting elements ED disposed in each of the first to third emission areas EMA1, EMA2, and EMA3may emit light in the same wavelength band (e.g., may emit the same color light). For example, light emitted by the light emitting elements ED each disposed in the first to third emission areas EMA1, EMA2, and EMA3may be light of a third color, that is, blue light. However, the present disclosure is not limited thereto, and the light emitting elements ED disposed in the first to third emission areas EMA1, EMA2, and EMA3may emit light of different colors.

A shape, in a plan view, of the emission area EMA included in each sub-pixel SPX may be similar to a shape of the corresponding sub-pixel SPX in a plan view. For example, the emission area EMA included in each sub-pixel SPX may have a rectangular shape, in a plan view, in which the second direction DR2is longer than the first direction DR1.

The non-emission area NEM may be disposed to surround (e.g., to extend around a periphery of) the emission area NEM. For example, the non-emission area NEM may be disposed to surround the first emission area EMA1, the second emission area EMA2, and the third emission area EMA3.

Each pixel PX may have a sub-area SA positioned in the non-emission area NEM and spaced apart from the emission area EMA. The sub-area SA may be disposed on the upper side (or on one side) in the second direction DR2or the lower side (or on the other side) in the second direction DR2of the emission area EMA. The sub-area SA may be an area in which electrode layers200(see, e.g.,FIG.4) of the respective sub-pixels SPX neighboring (e.g., adjacent each other) in the second direction DR2are separated.

The sub-area SA may have a first sub-area SA1, a second sub-area SA2, and a third sub-area SA3. The first sub-area SA1may be a sub-area SA of the first sub-pixel SPX1, the second sub-area SA2may be a sub-area SA of the second sub-pixel SPX2, and the third sub-area SA3may be a sub-area SA of the third sub-pixel SPX3.

In an embodiment, a direction in which the sub-area SA is disposed with respect to the emission area EMA in each pixel PX may be different for each of the sub-pixels SPX adjacent to each other in the first direction DR1. For example, a direction in which the first sub-area SA1is disposed with respect to the first emission area EMA1and a direction in which the second sub-area SA2is disposed with respect to the second emission area EMA2may be opposite to each other. Similarly, the direction in which the second sub-area SA2is disposed with respect to the second emission area EMA2and a direction in which the third sub-area SA3is disposed with respect to the third emission area EMA3may be opposite to each other. For example, the first sub-area SA1may be disposed on the upper side (inFIG.2) of the first emission area EMA1, the second sub-area SA2may be disposed on the lower side (inFIG.2) of the second emission area EMA2, and the third sub-area SA3may be disposed on the upper side (inFIG.2) of the third emission area EMA3. Accordingly, the first sub-areas SA1and the first emission areas EMA1may be alternately and repeatedly disposed along an opposite direction to the second direction DR2, the second sub-areas SA2and the second emission areas EMA2may be alternately and repeatedly disposed along the second direction DR2, and the third sub-area SA3and the third emission area EMA3may be alternately and repeatedly disposed along the opposite direction to the second direction DR2.

The first sub-area SA1of the first sub-pixel SPX1, the second emission area EMA2of the second sub-pixel SPX2, and the third sub-area SA3of the third sub-pixel SPX3may be arranged side-by-side in the first direction DR1in the same row. For example, the first sub-area SA1, the second emission area EMA2, and the third sub-area SA3may be alternately and repeatedly disposed along the first direction DR1in odd-numbered rows. A reference line crossing a central portion of the first sub-area SA1in the first direction DR1, a reference line crossing a central portion of the second emission area EMA2in the first direction DR1, and a reference line crossing a central portion of the third sub-area SA3in the first direction DR1may be positioned on the same straight line.

Similarly, the first emission area EMA1of the first sub-pixel SPX1, the second sub-area SA2of the second sub-pixel SPX2, and the third emission area EMA3of the third sub-pixel SPX3may be arranged side-by-side in the first direction DR1in the same row. For example, the first emission area EMA1, the second sub-area SA2, and the third emission area EMA3may be alternately and repeatedly disposed along the first direction DR1in even-numbered rows. A reference line crossing a central portion of the first emission area EMA1in the first direction DR1, a reference line crossing a central portion of the second sub-area SA2in the first direction DR1, and a reference line crossing a central portion of the third emission area EMA3in the first direction DR1may be positioned on the same straight line.

FIG.3is an enlarged view illustrating an example of a relative layout, in a plan view, of an emission area, a sub-area, and a first bank disposed in the area P1ofFIG.2.

Referring toFIGS.2and3, the display device10may include a first bank600. Hereinafter, a relative layout and shape between the emission area EMA and the sub-area SA of the display device10and the first bank600in a plan view will be described.

The first bank600may be disposed in the non-emission area NEM and may not be disposed in the emission area EMA. The first bank600may be disposed to surround (e.g., extend around) a portion of the emission area EMA and the sub-area SA. The first bank600may be disposed to surround the sub-area SA of each sub-pixel SPX to define the sub-area SA.

The first bank600may act as a wall disposed to surround portions of the emission areas EMA and the sub-areas SA and may guide ink in which light emitting elements ED (see, e.g.,FIG.4) are dispersed so that the ink is not deposited (e.g., jetted) to the sub-area SA and is stably deposited into the emission area EMA during an inkjet process for aligning the light emitting elements ED from among processes of manufacturing the display device10. In addition, the first bank600may surround a portion of the emission area EMA of each sub-pixel SPX, may not be disposed on at least a portion of the upper side or the lower side (inFIG.3) of the emission area EMA, and may act to adjust a shape of the ink so that a surface shape of the ink deposited into the emission area EMA is substantially flat.

The first bank600may include a first wall610, a second wall620, and a third wall630. The first bank600may further include a fourth wall640.

The first wall610may be disposed to surround the first sub-area SA1of the first sub-pixel SPX1. The first wall610may include an opening overlapping the first sub-area SA1in the third direction DR3to define the first sub-area SA1(e.g., the first wall610may extend around the first sub-area SA1to define the first sub-area SA1).

As described above, the first sub-areas SA1and the first emission areas EMA1of the first sub-pixel SPX1are alternately and repeatedly disposed in the second direction DR2, and thus, the first wall610surrounding the first sub-area SA1may be disposed between the first emission areas EMA1disposed adjacent to each other in the second direction DR2. For example, the first walls610may be disposed on the upper side and the lower side (inFIG.3) of the first emission area EMA1, respectively.

In addition, as described above, the first sub-area SA1may be arranged side by side with the second emission area EMA2and the third sub-area SA3in the first direction DR1. Accordingly, the first wall610surrounding the first sub-area SA1of one pixel PX may be disposed between the second emission area EMA2of the one pixel PX and a third sub-area SA3of another pixel PX disposed adjacent to the one pixel PX on the left side of the one pixel PX.

The first wall610disposed in one pixel PX may be disposed between the first emission areas EMA1arranged side-by-side in the second direction DR2in an area between the third sub-area SA3of another pixel PX disposed on the left side in a plan view and the second emission area EMA2of the one pixel PX. The first wall610may be disposed on the upper side of the first emission area EMA1and, at the same time, may be disposed on the left side of the second emission area EMA2, in one pixel PX.

The second wall620may be disposed to be spaced apart from the first wall610. The second wall620may be disposed adjacent to the first wall610in a diagonal direction and may be spaced apart from the first wall610in the second direction DR2. For example, the second wall620disposed in one pixel PX may be disposed adjacent to the first wall610on the lower right side of the first wall610disposed in the same pixel PX but may be spaced apart from the first wall610in the second direction DR2.

The second wall620may be disposed to surround the second sub-area SA2of the second sub-pixel SPX2. The second wall620may include an opening overlapping the second sub-area SA2in the third direction DR3to define the second sub-area SA2.

As described above, the second sub-areas SA2and the second emission areas EMA2of the second sub-pixel SPX2are alternately and repeatedly disposed in the second direction DR2, and thus, the second wall620surrounding the second sub-area SA2may be disposed between the second emission areas EMA2disposed adjacent to each other in the second direction DR2. For example, the second walls620may be disposed on the upper side and the lower side (inFIG.3) of the second emission area EMA2, respectively.

In addition, as described above, the second sub-area SA2may be arranged side-by-side with the first emission area EMA1and the third emission area EMA3in the first direction DR1. Accordingly, the second wall620surrounding the second sub-area SA2of one pixel PX may be disposed between the first emission area EMA1and the third emission area EMA3of the same pixel PX.

For example, the second wall620disposed in one pixel PX may be disposed between the second emission areas EMA2arranged side-by-side in the second direction DR2in an area between the first emission area EMA1and the third emission area EMA3of the one pixel PX in a plan view. The second wall620may be disposed on the lower side of the second emission area EMA2and, at the same time, may be disposed on the right side of the first emission area EMA1and the left side of the third emission area EMA3, in one pixel PX.

The third wall630may be disposed to be spaced apart from the second wall620. The third wall630may be disposed adjacent to the second wall620in a diagonal direction but may be spaced apart from the second wall620in the second direction DR2. For example, the third wall630disposed in one pixel PX may be disposed adjacent to the second wall620on the upper right side of the second wall620disposed in the same pixel PX and may be spaced apart from the second wall620in the second direction DR2. In addition, the third wall630may be disposed to spaced apart from the first wall610disposed in the same pixel PX in the first direction DR1. The third wall630may be spaced apart from the first wall610disposed in the same one pixel PX in the first direction DR1, but may be integrated with a first wall610of a pixel PX disposed adjacent to the one pixel PX in the first direction DR1to form one pattern.

The third wall630may be disposed to surround the third sub-area SA3of the third sub-pixel SPX3. The third wall630may include an opening overlapping the third sub-area SA3in the third direction DR3to define the third sub-area SA3.

As described above, the third sub-areas SA3and the third emission areas EMA3of the third sub-pixel SPX3are alternately and repeatedly disposed in the second direction DR2, and thus, the third wall630surrounding the third sub-area SA3may be disposed between the third emission areas EMA3disposed adjacent to each other in the second direction DR2. For example, the third walls630may be disposed on the upper side and the lower side of the third emission area EMA3, respectively.

In addition, as described above, the third sub-area SA3may be arranged side-by-side with the second emission area EMA2and the first sub-area SA1in the first direction DR1. Accordingly, the third wall630surrounding the third sub-area SA3of one pixel PX may be disposed between the second emission area EMA2of the one pixel PX and a first sub-area SA1of another pixel PX adjacent to the one pixel PX on the right side of the one pixel PX.

The third wall630disposed in one pixel PX may be disposed between the third emission areas EMA3arranged side by side in the second direction DR2in an area between the first sub-area SA1of another pixel PX disposed on the right side in a plan view and the second emission area EMA2of the one pixel PX. The third wall630may be disposed on the upper side of the first emission area EMA3and at the same time, be disposed on the right side of the second emission area EMA2, in one pixel PX.

The fourth wall640may be disposed at a boundary between the respective pixels PX adjacent to each other in the first direction DR1. The fourth wall640may be disposed at the boundary between the respective pixels PX adjacent to each other in the first direction DR1and may not be disposed at a boundary between the respective pixels PX adjacent to each other in the second direction DR2. The fourth wall640may have a shape extending in the second direction DR2in a plan view. The fourth wall640may be formed to have a shape extending in the second direction DR2in a plan view at the boundary between the respective pixels PX and may act to divide the pixels PX adjacent to each other in the first direction DR1.

The first wall610may include portions extending in the first direction DR1and the second direction DR2in a plan view. Hereinafter, unless otherwise stated in embodiments describing shapes of the first to third walls610,620, and630of the first bank600in a plan view, portions of the first to third walls610,620, and630extending in the first direction DR1may be referred to as transverse portions of the first to third walls610,620, and630and portions of the first to third walls610,620, and630extending in the second direction DR2may be referred to as longitudinal portions of the first to third walls610,620, and630.

The transverse portions of the first wall610may be disposed at boundaries between the first emission areas EMA1and the first sub-area SA1. For example, the transverse portions of the first wall610may be disposed at the boundaries between the first emission areas EMA1disposed adjacent to the first sub-area SA1in the second direction DR2and the first sub-area SA1. The transverse portions of the first wall610may be disposed at the boundaries between the first emission areas EMA1disposed on the upper side and the lower side of the first sub-area SA1and the first sub-area SA1. Accordingly, the first emission area EMA1and the first sub-area SA1may be divided by the transverse portion of the first wall610.

The longitudinal portions of the first wall610may be disposed at a boundary between the first sub-pixel SPX1and the second sub-pixel SPX2disposed on the right side of the first sub-pixel SPX1and a boundary between the first sub-pixel SPX1and the third sub-pixel SPX3disposed on the left side of the first sub-pixel SPX1. For example, the longitudinal portions of the first wall610may be disposed at a boundary between the second emission area EMA2disposed on the right side of the first sub-area SA1and the first sub-area SA1and may be disposed at a boundary between a third sub-area SA3of another pixel PX disposed on the left side of the first sub-area SA1and the first sub-area SA1. The longitudinal portion of the first wall610is disposed at least at the boundary between the first sub-area SA1and the second emission area EMA2such that the first sub-area SA1and the second emission area EMA2may be divided by the longitudinal portion of the first wall610.

The second wall620may include portions extending in the first direction DR1and the second direction DR2in a plan view.

The transverse portions of the second wall620may be disposed at boundaries between the second emission areas EMA2and the second sub-area SA2. For example, the transverse portions of the second wall620may be disposed at the boundaries between the second emission areas EMA2disposed adjacent to the second sub-area SA2in the second direction DR2and the second sub-area SA2. The transverse portions of the second wall620may be disposed at the boundaries between the second emission areas EMA2disposed on the upper side and the lower side of the second sub-area SA2and the second sub-area SA2. Accordingly, the second emission area EMA2and the second sub-area SA2may be divided by the transverse portion of the second wall620.

The longitudinal portions of the second wall620may be disposed at a boundary between the second sub-pixel SPX2and the first sub-pixel SPX1and a boundary between the second sub-pixel SPX2and the third sub-pixel SPX3disposed on the right side of the second sub-pixel SPX2. For example, the longitudinal portions of the second wall620may be disposed at a boundary between the first emission area EMA1disposed on the left side of the second sub-area SA2and the second sub-area SA2and may be disposed at a boundary between the third emission area EMA3disposed on the right side of the second sub-area SA2and the second sub-area SA2.

The longitudinal portions of the second wall620are disposed at the boundaries between the first and third emission areas EMA1and EMA3and the second sub-area SA2in one pixel PX such that the first and third emission areas EMA1and EMA3and the second sub-area SA2may be divided by the second wall620.

The third wall630may include portions extending in the first direction DR1and the second direction DR2in a plan view.

The transverse portions of the third wall630may be disposed at boundaries between the third emission areas EMA3and the third sub-area SA3. For example, the transverse portions of the third wall630may be disposed at the boundaries between the third emission areas EMA3disposed adjacent to the third sub-area SA3in the second direction DR2and the third sub-area SA3. The transverse portions of the third wall630may be disposed at the boundaries between the third emission areas EMA3disposed on the upper side and the lower side of the third sub-area SA3and the third sub-area SA3. Accordingly, the third emission area EMA3and the third sub-area SA3may be divided by the transverse portion of the third wall630.

The longitudinal portions of the third wall630may be disposed at a boundary between the third sub-pixel SPX3and the first sub-pixel SPX1disposed on the right side of the third sub-pixel SPX3and a boundary between the third sub-pixel SPX3and the second sub-pixel SPX2disposed on the left side of the third sub-pixel SPX3. For example, the longitudinal portions of the third wall630may be disposed at a boundary between the second emission area EMA2disposed on the left side of the third sub-area SA3and the third sub-area SA3and may be disposed at a boundary between a first sub-area SA1of another pixel PX disposed on the right side of the third sub-area SA3and the third sub-area SA3. The longitudinal portion of the third wall630is disposed at least at the boundary between the third sub-area SA3and the second emission area EMA2such that the third sub-area SA3and the second emission area EMA2may be divided by the longitudinal portion of the third wall630.

The third wall630disposed in one pixel PX and the first wall610disposed in another pixel PX disposed on the right side of the one pixel PX may be integrated with each other to form one pattern. Accordingly, the longitudinal portion of the third wall630and the longitudinal portion of the first wall610may be disposed between the third sub-area SA3of one pixel PX and the first sub-area SA1of another pixel PX disposed on the right side of the one pixel PX, and the longitudinal portion of the third wall630and the longitudinal portion of the first wall610disposed between the third sub-area SA3and the first sub-area SA1may contact each other such that they may not be physically apparent (e.g., may be integrally formed).

The fourth wall640may be disposed at a boundary between the third emission area EMA3of one pixel PX and the first emission area EMA1of another pixel PX disposed on the right side of the one pixel PX. The fourth wall640may be disposed at the boundary between the third emission area EMA3and the first emission area EMA1to divide the third emission area EMA3and the first emission area EMA1.

In an embodiment, the fourth wall640may extend in the second direction DR2and may be integrated with the first wall610and the third wall630disposed on the upper side and the lower side thereof to form one pattern. The fourth wall640is formed to divide the pixels PX disposed adjacent to each other in the first direction DR1such that the fourth wall640may prevent or substantially prevent ink in which the plurality of light emitting elements ED are dispersed from overflowing into the pixels PX disposed adjacent to each other in the first direction DR1during the inkjet process for aligning the light emitting elements ED among the processes of manufacturing the display device10.

In an embodiment, widths W1, in the second direction DR2, of the emission areas EMA of each sub-pixel SPX may be the same as each other. For example, a width W1of the first emission area EMA1in the second direction DR2, a width W1of the second emission area EMA2in the second direction DR2, and a width W1of the third emission area EMA3in the second direction DR2may be equal to each other. However, the present disclosure is not limited thereto, and the widths of the first emission area EMA1and the third emission area EMA3disposed in the same row may be the same as each other while the width of the second emission area EMA2disposed in a different row may be different from the width of the first emission area EMA1or the third emission area EMA3in the second direction DR2.

The width W1of the emission area EMA in the second direction DR2may be measured as an interval between the walls disposed on the upper side and the lower side of each emission area EMA. For example, the width W1of the first emission area EMA1in the second direction DR2may be measured as an interval W1between the first walls610each disposed on the upper side and the lower side of the first emission area EMA1, the width W1of the second emission area EMA2in the second direction DR2may be measured as an interval W1between the second walls620each disposed on the upper side and the lower side of the second emission area EMA2, and the width W1of the third emission area EMA3in the second direction DR2may be measured as an interval W1between the third walls630each disposed on the upper side and the lower side of the third emission area EMA3.

Widths W2, in the second direction DR2, of the sub-areas SA of each sub-pixel SPX may be the same as each other. For example, a width W2of the first sub-area SA1in the second direction DR2, a width W2of the second sub-area SA2in the second direction DR2, and a width W2of the third sub-area SA3in the second direction DR2may be equal to each other. However, the present disclosure is not limited thereto, and the widths of the first sub-area SA1and the third sub-area SA3disposed in the same row may be the same as each other while the width of the second sub-area SA2disposed in a different row may be different from the width of the first sub-area SA1or the third sub-area SA3in the second direction DR2.

The width W2of the sub-area SA in the second direction DR2may be measured as an interval W2between the transverse portions of the wall surrounding each sub-area SA. For example, the width W2of the first sub-area SA1in the second direction DR2may be measured as an interval W2between the transversal portions of the first wall610surrounding the first sub-area SA1, the width W2of the second sub-area SA2in the second direction DR2may be measured as an interval W2between the transversal portions of the second wall620surrounding the second sub-area SA2, and the width W2of the third sub-area SA3in the second direction DR2may be measured as an interval W2between the transversal portions of the third wall630surrounding the third sub-area SA3.

The width W1of the emission area EMA in the second direction DR2and the width W2of the sub-area SA in the second direction DR2may be different from each other. In an embodiment, the width W1of the emission area EMA in the second direction DR2may be greater than the width W2of the sub-area SA in the second direction DR2.

A length W5of each of the first to third walls610,620, and630in the second direction DR2may be smaller than the width W1of the emission area EMA in the second direction DR2. The length W5of each of the first to third walls610,620, and630in the second direction DR2is smaller than the width W1of the emission area EMA in the second direction DR2, such that the second wall620may be disposed to be spaced apart from the first wall610or the third wall630.

Specifically, the length W5, in the second direction DR2, of the second wall620disposed adjacent to the first emission area EMA1on the right side of the first emission area EMA1may be smaller than the width W1of the first emission area EMA1in the second direction DR2. For example, the length W5, in the second direction DR2, of the second wall620disposed adjacent to the first emission area EMA1on the right side of the first emission area EMA1may be smaller than the interval W1between the first walls610each disposed adjacent to the first emission area EMA1on the upper side and the lower side of the first emission area EMA1. The length W5of the second wall620in the second direction DR2is smaller than the width W1of the first emission area EMA1in the second direction DR2such that the first walls610each disposed on the upper side and the lower side of the first emission area EMA1may be spaced apart from the second wall620in the second direction DR2.

The second wall620may also be disposed adjacent to the third emission area EMA3on the left side of the third emission area EMA3. The length W5, in the second direction DR2, of the second wall620disposed adjacent to the third emission area EMA3on the left side of the third emission area EMA3may be smaller than the width W1of the third emission area EMA3in the second direction DR2, similar to the first emission area EMA1. For example, the length W5, in the second direction DR2, of the second wall620disposed adjacent to the third emission area EMA3on the left side of the third emission area EMA3may be smaller than the interval W1between the third walls630each disposed adjacent to the third emission area EMA3on the upper side and the lower side of the third emission area EMA3. The length W5of the second wall620in the second direction DR2is smaller than the width W1of the third emission area EMA3in the second direction DR2such that the third walls630each disposed on the upper side and the lower side of the third emission area EMA3may be spaced apart from the second wall620in the second direction DR2.

The second wall620is disposed to surround the second sub-area SA2between the first emission area EMA1and the third emission area EMA3, and the length W5of the second wall620in the second direction DR2is smaller than the width W1of the first and third emission areas EMA1and EMA3in the second direction DR2such that the first bank600may not be disposed on the upper side or the lower side of each emission area EMA in a boundary area of each sub-pixel SPX. Accordingly, passages PA1and PA2defined as areas between the first and second walls610and620may be formed between the first and second emission areas EMA1and EMA2, and passages PA3and PA4defined as areas between the second and third walls620and630may be formed between the second and third emission areas EMA2and EMA3. The passages PA1and PA2defined as the areas between the first and second walls610and620between the first and second emission areas EMA1and EMA2may include a first passage PA1defined as an area between the first and second walls610and620included in the same pixel PX and a second passage PA2defined as an area between a first wall610included in another pixel PX adjacent in the second direction DR2and the second wall620. Similarly, the passages PA3and PA4defined as the areas between the second and third walls620and630between the second and third emission areas EMA2and EMA3may include a third passage PA3defined as an area between the third and second walls630and620included in the same pixel PX and a fourth passage PA4defined as an area between a third wall630included in another pixel PX adjacent in the second direction DR2and the second wall620.

The first to fourth passages PA1, PA2, PA3, and PA4may be flow passages through which ink jetted into the emission area EMA may flow (e.g., move) from upper and lower sides of the emission area EMA to the other emission areas EMA during the inkjet process for aligning the light emitting elements ED from among the processes of manufacturing the display device10. Accordingly, the ink jetted into the emission area EMA of the one sub-pixel SPX may flow to the emission area EMA of another sub-pixel SPX disposed in at least the same pixel PX through the first to fourth passages PA1, PA2, PA3, and PA4. The ink jetted into each emission area EMA is induced to flow from one emission area EMA to the other emission areas EMA through the first to fourth passages PA1, PA2, PA3, and PA4such that a surface shape of the ink jetted into the emission area EMA may be flat at an upper side and a lower side of each emission area EMA. Accordingly, a flow of the ink that may be generated by the surface shape of the ink may be prevented or substantially prevented to prevent or substantially prevent the light emitting elements aligned during the process for aligning the light emitting elements from being collected upward and downward in the emission areas EMA due to the shape of the ink. A detailed description thereof will be provided later.

In an embodiment, an interval W3between the first wall610disposed on the upper side of the first emission area EMA1and the second wall620disposed on the right side of the first emission area EMA1may be the same as an interval W4between the first wall610disposed on the lower side of the first emission area EMA1and the second wall620disposed on the right side of the first emission area EMA1. However, the present disclosure is not limited thereto, and the interval W3between the first wall610and the second wall620disposed on the right side of the first emission area EMA1and the interval W4between the first wall610disposed on the lower side of the first emission area EMA1and the second wall620disposed on the right side of the first emission area EMA1may also be different from each other.

The interval W3between the first wall610disposed on the upper side of the first emission area EMA1and the second wall620disposed on the right side of the first emission area EMA1may be smaller than the length W5of the second wall620in the second direction DR2. In addition, the interval W4between the first wall610disposed on the lower side of the first emission area EMA1and the second wall620disposed on the right side of the first emission area EMA1may be smaller than the length W5of the second wall620in the second direction DR2. Because the interval W3between the first wall610disposed on the upper side of the first emission area EMA1and the second wall620disposed on the right side of the first emission area EMA1and the interval W4between the first wall610disposed on the lower side of the first emission area EMA1and the second wall620disposed on the right side of the first emission area EMA1are smaller than the length W5of the second wall620in the second direction DR2, the light emitting element ED may not move to the other emission areas EMA through the passages PA1, PA2, PA3, and PA4when the ink flows through the passages PA1, PA2, PA3, and PA4.

The second wall620is disposed to be spaced apart from not only the first wall610and the third wall630disposed in the same pixel PX but also from the first wall610and the third wall630disposed in another pixel PX disposed adjacent to the same pixel on the lower side of the same pixel such that the ink jetted into the emission area EMA may also flow to the emission area EMA of the sub-pixel SPX included in another pixel PX.

FIG.4is a schematic plan layout view of one pixel according to the embodiment shown inFIG.3.

Referring toFIG.4, the display device10may include a second bank400, the electrode layer200, a contact electrode700, a plurality of light emitting elements ED, and the first bank600. The second bank400, the electrode layer200, the contact electrode700, and the plurality of light emitting elements ED may be disposed for each sub-pixel SPX.

The electrode layer200may be disposed over the emission area EMA and the sub-area SA. For example, the electrode layer200may be disposed over the first emission area EMA1and the first sub-area SA1of the first sub-pixel SPX1, over the second emission area EMA2and the second sub-area SA2of the second sub-pixel SPX2, and over the third emission area EMA3and the third sub-area SA3of the third sub-pixel SPX3.

The electrode layer200may include a plurality of electrodes extending in the second direction DR2and spaced apart from each other in the first direction DR1. For example, the electrode layer200may include a first electrode210and a second electrode220.

The first electrode210and the second electrode220may be disposed over the emission area EMA and the sub-area SA of each sub-pixel SPX but may be spaced apart from a first electrode210and a second electrode220included in a sub-pixel SPX neighboring in the second direction DR2, respectively, at a separation part ROP positioned in the sub-area SA. For example, the first electrode210and the second electrode220included in the first sub-pixel SPX1may extend in the second direction DR2in a plan view but may be spaced apart from a first electrode210and a second electrode220included in a first sub-pixel SPX1neighboring in the second direction DR2, respectively, at the first separation part ROP1positioned in the first sub-area SA1. Similarly, the first electrode210and the second electrode220included in the second sub-pixel SPX2may extend in the second direction DR2in a plan view but may be spaced apart from a first electrode210and a second electrode220included in a second sub-pixel SPX2neighboring in the second direction DR2, respectively, at a second separation part ROP2positioned in the second sub-area SA1. The first electrode210and the second electrode220included in the third sub-pixel SPX3may extend in the second direction DR2in a plan view but may be spaced apart from a first electrode210and a second electrode220included in a third sub-pixel SPX3neighboring in the second direction DR2, respectively, at a third separation part ROP3positioned in the third sub-area SA3.

The first electrode210and the second electrode220separated at the separation part ROP of each sub-pixel SPX may be formed after the process for aligning a plurality of light emitting elements ED from among the processes of manufacturing the display device10. For example, during the process for aligning a plurality of light emitting elements ED from among the processes of manufacturing the display device10, an electric field may be generated using alignment lines extending in the second direction DR2, and the plurality of light emitting elements ED may be aligned by a dielectrophoretic force caused by the electric field generated on (or between) the alignment lines. After the process for aligning the light emitting elements ED is performed, a plurality of alignment lines are separated at the separation part ROP positioned in the sub-area SA of each sub-pixel SPX such that the first electrode210and the second electrode220separated at the separation part ROP of each sub-pixel SPX may be formed, as illustrated inFIG.4.

The first electrode210may be electrically connected to a circuit element layer CCL, to be described later (see, e.g.,FIG.5), through a first electrode contact opening (e.g., a first electrode contact hole) CTD. The second electrode220may be electrically connected to a circuit element layer CCL, to be described later, through a second electrode contact opening (e.g., a second electrode contact hole) CTS. The first electrode210is electrically connected to the circuit element layer CCL through the first electrode contact hole CTD and the second electrode220is electrically connected to the circuit element layer CCL through the second electrode contact hole CTS such that an electrical signal applied to the circuit element layer CCL may be transferred to both ends of the light emitting element ED through the first electrode210and the second electrode220. While it is illustrated inFIG.4that the first and second electrode contact holes CTD and CTS are disposed to overlap the first bank600in the third direction DR3, positions of the first and second electrode contact holes CTD and CTS are not limited thereto.

The second bank400may be disposed in the emission area EMA. For example, the second bank400may be disposed in each of the first to third emission areas EMA1, EMA2, and EMA3, which are the respective emission areas EMA of the first to third sub-pixels SPX1, SPX2, and SPX3.

The second bank400may include a plurality of sub-banks extending in the second direction DR2and that are spaced apart from each other in the first direction DR1. For example, the second bank400may include a first sub-bank410and a second sub-bank420.

The first sub-bank410may be disposed to overlap the first electrode210in the third direction DR3in the emission area EMA of each sub-pixel SPX. The second sub-bank420may be disposed to overlap the second electrode220in the third direction DR3in the emission area EMA of each sub-pixel SPX.

The plurality of light emitting elements ED may be disposed in the emission area EMA. For example, the plurality of light emitting elements ED may be disposed in each of the first to third emission areas EMA1, EMA2, and EMA3, which are the respective emission areas EMA of the first to third sub-pixels SPX1, SPX2, and SPX3. The plurality of light emitting elements ED may not be disposed in the sub-area SA. As described above, the first bank600is disposed around the sub-area SA of each sub-pixel SPX such that the ink in which the plurality of light-emitting elements ED are dispersed is jetted only into the emission area EMA. Thus, the plurality of light emitting elements ED may be disposed in the emission area EMA and may not be disposed in the sub-area SA.

The plurality of light emitting elements ED may be disposed between the first sub-bank410and the second sub-bank420in the emission area EMA. The light emitting element ED may have a shape extending in one direction, and an extension direction of the light emitting element ED may be substantially perpendicular to an extension direction of the first electrode210and the second electrode220. However, the present disclosure is not limited thereto, and the extension direction of the light emitting element ED may be oblique to the extension direction of the first electrode210and the second electrode220. The light emitting element ED may be disposed so that at least one of both ends (e.g., opposite ends) thereof is on the first electrode210or the second electrode220in an area in which the first sub-bank410and the second sub-bank420are spaced apart from and face each other.

The plurality of light emitting elements ED may be disposed to be spaced apart from each other. The plurality of light emitting elements ED may be disposed to be spaced apart from each other along the second direction DR2between the first sub-bank410and the second sub-bank420. The plurality of light emitting elements ED may be aligned in one column between the first sub-bank410and the second sub-bank420, and distances between the light emitting elements ED disposed adjacent to each other in the second direction DR2may vary (e.g., may be random).

The contact electrode700may be disposed over the emission area EMA and the sub-area SA. For example, the contact electrode700may be disposed over the first emission area EMA1and the first sub-area SA1of the first sub-pixel SPX1, over the second emission area EMA2and the second sub-area SA2of the second sub-pixel SPX2, and over the third emission area EMA3and the third sub-area SA3of the third sub-pixel SPX3.

The contact electrode700may include a plurality of contact electrodes extending in the second direction DR2and spaced apart from each other in the first direction DR1. For example, the contact electrode700may include a first contact electrode710and a second contact electrode720.

The first contact electrode710may be disposed to overlap the first electrode210in the third direction DR3in the emission area EMA and the sub-area SA of each sub-pixel SPX. The first contact electrode710may be disposed to overlap one end of the plurality of light emitting elements ED in the emission area EMA of each sub-pixel SPX.

The first contact electrode710may contact the first electrode210through a first contact part CT1in the sub-area SA of each sub-pixel SPX and may contact one end of the plurality of light emitting elements ED in the emission area EMA of each sub-pixel SPX. The first contact electrode710contacts each of one end of the light emitting element ED and the first electrode210such that the first contact electrode710may electrically connect one end of the light emitting element ED and the first electrode210to each other. While it has been illustrated inFIG.4that the first contact electrode710contacts the first electrode210in the sub-area SA of each sub-pixel SPX, the present disclosure is not limited thereto. For example, the first contact electrode710may contact the first electrode210in the emission area EMA of each sub-pixel SPX.

The second contact electrode720may be disposed to overlap the second electrode220in the third direction DR3in the emission area EMA and the sub-area SA of each sub-pixel SPX. The second contact electrode720may be disposed to overlap the other ends of the plurality of light emitting elements ED in the emission area EMA of each sub-pixel SPX.

The second contact electrode720may contact the second electrode220through a second contact part CT2in the sub-area SA of each sub-pixel SPX and may contact the other end of the plurality of light emitting elements ED in the emission area EMA of each sub-pixel SPX. The second contact electrode720contacts each of the other end of the light emitting element ED and the second electrode220such that the second contact electrode720may electrically connect the other end of the light emitting element ED and the second electrode220to each other. While it has been illustrated inFIG.4that the second contact electrode720contacts the second electrode220in the sub-area SA of each sub-pixel SPX, the present disclosure is not limited thereto. For example, the second contact electrode720may contact the second electrode220in the emission area EMA of each sub-pixel SPX.

The first contact electrode710and the second contact electrode720disposed in the first sub-pixel SPX1may contact the first electrode210and the second electrode220, respectively, in the first sub-area SA1disposed on the upper side of the first emission area EMA1. The first contact electrode710and the second contact electrode720disposed in the second sub-pixel SPX2may contact the first electrode210and the second electrode220, respectively, in the second sub-area SA2disposed on the lower side of the second emission area EMA2. The first contact electrode710and the second contact electrode720disposed in the third sub-pixel SPX3may contact the first electrode210and the second electrode220, respectively, in the third sub-area SA3disposed on the upper side of the third emission area EMA3.

The first sub-area SA1of the first sub-pixel SPX1is disposed on the upper side of the first emission area EMA1, the second sub-area SA2of the second sub-pixel SPX2is disposed on the lower side of the second emission area EMA2, and the third sub-area SA3of the third sub-pixel SPX3is disposed on the upper side of the third emission area EMA3such that the second emission area EMA2may overlap upper and lower areas of the first emission area EMA1and the third emission area EMA3in the first direction DR1.

As described above, the first contact electrode710and the second contact electrode720may be spaced apart from each other in the first direction DR1. An interval between the first contact electrode710and the second contact electrode720may be smaller than a length of the light emitting element ED in the extension direction of the light emitting element ED. Accordingly, the first contact electrode710and the second contact electrode720may be spaced apart from each other in the first direction DR1but may contact both ends (e.g., may respectively contact opposite ends) of the light emitting element ED, respectively.

The first bank600may be disposed to surround the sub-area SA so as to divide the sub-area SA and the emission area EMA and to guide the ink in which the plurality of light emitting elements ED are dispersed so that the ink is not jetted to the sub-area SA and is stably jetted to the emission area EMA during the inkjet process for aligning the plurality of light emitting elements ED.

The first bank600may include a hydrophobic material. Because the first bank600includes a hydrophobic material, even though the ink in which the plurality of light emitting elements ED are dispersed is jetted onto the first bank600positioned at a boundary between the sub-area SA and the emission area EMA, the ink may be induced to be positioned in the emission area EMA.

The first bank600may also adjust a cross-sectional shape of the ink so that a shape of the ink jetted onto the emission area EMA and applied into the emission area EMA is flat at an upper side or a lower side of the emission area EMA in a plan view. For example, the first bank600includes the hydrophobic material such that a surface contact angle may be formed at an edge of the ink applied into the emission area EMA. As described above, the first to third walls610,620, and630included in one pixel PX are disposed to be spaced apart from each other in the second direction DR2such that the passages PA1, PA2, PA3, and PA4may be formed between the first to third emission areas EMA1, EMA2, and EMA3. Accordingly, the ink applied into the first to third emission areas EMA1, EMA2, and EMA3may flow to the other emission areas EMA1, EMA2, and EMA3through the passages PA1, PA2, PA3, and PA4. Accordingly, the inks jetted into the first to third emission areas EMA1, EMA2, and EMA3and applied into each emission area EMA may be connected to each other through the passages PA1, PA2, PA3, and PA4and may have a flat cross-sectional shape even at the upper side or the lower side of each emission area EMA.

The plurality of light emitting elements ED dispersed in the ink applied into the emission area EMA may move according to the flow of the ink as well as due to a dielectrophoretic force generated by an electric field generated on the electrode layer200, and the light emitting elements ED may be aligned at specific positions in the emission area EMA. For example, during the process for aligning the plurality of light emitting elements ED, the ink may be jetted into the first to third emission areas EMA1, EMA2, and EMA3and an alignment signal may be applied to the alignment lines using the alignment lines corresponding to the electrode layer200. An electric field may be generated on the alignment lines by the alignment signal, and the plurality of light emitting elements ED dispersed in the ink applied into the emission area EMA may be seated on the alignment lines while changing their orientations direction and/or positions according to the electric field. The electric field may cause the ink in which the plurality of light emitting elements ED are dispersed to flow in a specific direction. Accordingly, the positions of the plurality of light emitting elements ED may be affected by a flow direction and a flow velocity of the ink as well as a direction of the electric field and an electric field strength. The flow direction and flow velocity of the ink may be adjusted according to the cross-sectional shape of the applied ink. For example, when the surface contact angle of the ink at the edge of the ink is relatively large, the flow direction of the ink may be a direction from an inner portion of the ink toward the edge of the ink due to a difference in a flow velocity in the ink. On the other hand, when the surface of the ink is flat, a difference in flow velocity in the ink is small, such that the flow of the ink may be relatively small.

Accordingly, in the display device10according to the present disclosure, an alignment degree of the light emitting elements ED may be improved by adjusting the surface shape of the ink jetted into the emission area EMA by using the shape of the first bank600, which acts as the wall in the inkjet process for aligning the light emitting elements ED. For example, the display device10may have the emission area EMA and the sub-area SA adjacent to each other in the second direction DR2and may include the plurality of electrodes210and220extending in the second direction DR2and crossing the emission area EMA and the sub-area SA and the first bank600. The first bank600may surround the sub-area SA and the emission area EMA, but the passages PA1, PA2, PA3, and PA4may be formed to expose an upper area and a lower area of the emission area EMA. Accordingly, during the inkjet process for aligning the light emitting elements ED, the ink jetted into the emission area EMA is induced to flow from one emission area EMA to the other emission areas EMA through the passages, such that the surface shape of the ink seated in the emission area EMA may be flat even at an upper side and a lower side of the emission area EMA. Accordingly, the flow of the ink that may be generated by the surface shape of the ink may be prevented or substantially prevented to prevent or substantially prevent the light emitting elements ED aligned in the process for aligning the light emitting elements ED from being collected upward and downward in the emission areas EMA due to the shape of the ink. Therefore, the alignment degree of the light emitting elements ED aligned between the plurality of electrodes210and220in the emission area EMA may be improved to improve a display quality of the display device.

FIG.5is a cross-sectional view illustrating an example taken along the line I-I′ ofFIG.4.

Hereinafter, a schematic cross-sectional structure of the first sub-pixel SPX1of the display device10will be described with reference toFIG.5. The schematic cross-sectional structure of the first sub-pixel SPX1may be similarly applied to the second sub-pixel SPX2and the third sub-pixel SPX3. Accordingly, a description for cross-sectional structures of the second sub-pixel SPX2and the third sub-pixel SPX3will be replaced with a description of the cross-sectional structures of the first sub-pixel SPX1.

The display device10may include a substrate SUB, a circuit element layer CCL, and a light emitting element layer EML.

The substrate SUB may be a base substrate or a base member. The substrate SUB may include (or may be made of) an insulating material, such as glass, quartz, or a polymer resin. The substrate SUB may be a rigid substrate or may be a flexible substrate capable of being bent, folded, or rolled.

The circuit element layer CCL may be disposed on the substrate SUB. The circuit element layer CCL may include at least one transistor and the like to drive the light emitting element layer EML of each sub-pixel SPX.

The circuit element layer CCL may include a lower metal layer110, a semiconductor layer120, a first conductive layer130, a second conductive layer140, a third conductive layer150, and a plurality of insulating films.

The lower metal layer110is disposed on the substrate SUB. The lower metal layer110may include a light blocking pattern BML. The light blocking pattern BML may be disposed below a transistor TR so as to cover at least a channel region of an active layer ACT of the transistor TR. However, the present disclosure is not limited thereto, and the light blocking pattern BML may be omitted. The lower metal layer110may include a light blocking material. For example, the lower metal layer110may be formed of an opaque metal material that blocks or substantially blocks transmission of light therethrough.

A buffer layer161may be disposed on the lower metal layer110. The buffer layer161may be disposed to cover the entire surface of the substrate SUB on which the lower metal layer110is disposed. The buffer layer161may protect a plurality of transistors from moisture permeating through the substrate SUB, which may be vulnerable to moisture permeation.

The semiconductor layer120is disposed on the buffer layer161. The semiconductor layer120may include the active layer ACT of the transistor TR. The active layer ACT of the transistor TR may be disposed to overlap the light blocking pattern BML of the lower metal layer110, as described above.

The semiconductor layer120may include polycrystalline silicon, single crystal silicon, an oxide semiconductor, or the like. In an embodiment, when the semiconductor layer120includes the polycrystalline silicon, the polycrystalline silicon may be formed by crystallizing amorphous silicon. When the semiconductor layer120includes the polycrystalline silicon, the active layer ACT of the transistor TR may include a plurality of doped regions doped with impurities and a channel region between the plurality of doped regions. In another embodiment, the semiconductor layer120may include an oxide semiconductor. The oxide semiconductor may be, for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin Oxide (IZTO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium gallium zinc tin oxide (IGZTO), or the like.

A gate insulating film162may be disposed on the semiconductor layer120. The gate insulating film162may be formed as multiple layers in which inorganic layers, including at least one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiOxNy), are alternately stacked.

The first conductive layer130may be disposed on the gate insulating film162. The first conductive layer130may include a gate electrode GE of the transistor TR. The gate electrode GE may be disposed to overlap the channel region of the active layer ACT in the third direction DR3, which is the thickness direction of the substrate SUB.

A first interlayer insulating film163may be disposed on the first conductive layer130. The first interlayer insulating film163may be disposed to cover the gate electrode GE. The first interlayer insulating film163may be an insulating film between the first conductive layer130and other layers disposed on the first conductive layer130and may protect the first conductive layer130.

The second conductive layer140may be disposed on the first interlayer insulating film163. The second conductive layer140may include a drain electrode SD1of the transistor TR and a source electrode SD2of the transistor TR.

The drain electrode SD1and the source electrode SD2of the transistor TR may be electrically connected to both end regions of the active layer ACT of the transistor TR through contact openings (e.g., contact holes) penetrating through the first interlayer insulating film163and the gate insulating film162, respectively. In addition, the source electrode SD2of the transistor TR may be electrically connected to the light blocking pattern BML of the lower metal layer110through another contact opening (e.g., another contact hole) penetrating through the first interlayer insulating film163, the gate insulating film162, and the buffer layer161.

A second interlayer insulating film164may be disposed on the second conductive layer140. The second interlayer insulating film164may be disposed to cover the drain electrode SD1of the transistor TR and the source electrode SD2of the transistor TR. The second interlayer insulating film164may be an insulating film between the second conductive layer140and other layers disposed on the second conductive layer140and may protect the second conductive layer140.

The third conductive layer150may be disposed on the second interlayer insulating film164. The third conductive layer150may include a first voltage line VL1, a second voltage line VL2, and a conductive pattern CDP.

The first voltage line VL1may overlap at least a portion of the drain electrode SD1of the transistor TR in the thickness direction of the substrate SUB. A high potential voltage (e.g., a first source voltage) supplied to the transistor TR may be applied to the first voltage line VL1.

The second voltage line VL2may be electrically connected to the second electrode220through the second electrode contact hole CTS penetrating through a via layer166and a passivation layer165, to be described later. A low potential voltage (e.g., a second source voltage) lower than the high potential voltage supplied to the first voltage line VL1may be applied to the second voltage line VL2. For example, the high potential voltage (e.g., the first source voltage) supplied to the transistor TR may be applied to the first voltage line VL1, and the low potential voltage (e.g., the second source voltage) lower than the high potential voltage supplied to the first voltage line VL1may be applied to the second voltage line VL2.

The conductive pattern CDP may be electrically connected to the source electrode SD2of the transistor TR. The conductive pattern CDP may be electrically connected to the source electrode SD2of the transistor TR through a contact opening (e.g., a contact hole) penetrating through the second interlayer insulating film164. In addition, the conductive pattern CDP may be electrically connected to the first electrode210through the first electrode contact hole CTD penetrating through a via layer166and the passivation layer165, to be described later.

The passivation layer165may be disposed on the third conductive layer150. The passivation layer165may be disposed to cover the third conductive layer150. The passivation layer165may protect the third conductive layer150.

Each of the buffer layer161, the gate insulating film162, the first interlayer insulating film163, the second interlayer insulating film164, and the passivation layer165described above may be formed as a plurality of inorganic layers that are alternately stacked. For example, each of the buffer layer161, the gate insulating film162, the first interlayer insulating film163, the second interlayer insulating film164, and the passivation layer165described above may be formed as a double layer in which inorganic layers, including at least one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiOxNy), are stacked on each other or multiple layers in which these layers are alternately stacked on each other. However, the present disclosure is not limited thereto, and each of the buffer layer161, the gate insulating film162, the first interlayer insulating film163, the second interlayer insulating film164, and the passivation layer165may also be formed as one inorganic layer including the insulating material described above.

The via layer166may be disposed on the passivation layer165. The via layer166may have a substantially flat surface regardless of a shape or presence or absence of a pattern disposed therebelow. For example, the via layer166may planarize an upper portion of the passivation layer165. The via layer166may include an organic insulating material, for example, an organic material, such as polyimide (PI).

Referring toFIGS.4and5, the light emitting element layer EML may be disposed on the circuit element layer CCL. The light emitting element layer EML may include the second bank400, the electrode layer200, a first insulating layer510, the first bank600, the light emitting elements ED, a second insulating layer520, and the contact electrode700. The light emitting element layer EML may further include a protective layer810.

The second bank400may be disposed on the via layer166. The second bank400may be directly disposed on an upper surface of the via layer166. Each of the first sub-bank410and the second sub-bank420included in the second bank400may have a structure in which at least a portion thereof protrudes from the upper surface of the via layer166in a cross-sectional view.

The first sub-bank410and the second sub-bank420may induce the plurality of light emitting elements ED to be disposed between the first electrode210and the second electrode220during the process for aligning the plurality of light emitting elements ED from among the processes of manufacturing the display device10. A spaced space between the first sub-bank410and the second sub-bank420may provide an area in which the plurality of light emitting elements ED are disposed.

In addition, the first sub-bank410and the second sub-bank420may have inclined side surfaces to change a traveling direction of light emitted from the light emitting element ED that travels toward the side surfaces of the first sub-bank410and the second sub-bank420into an upward direction. For example, the second bank400may provide a space in which the light emitting element ED is disposed and also acts as a reflective wall changing the traveling direction of the light emitted from the light emitting element ED into the upward direction.

While it has been illustrated inFIG.5that each side surface of the plurality of sub-banks410and420included in the second bank400has a linear inclined shape, the present disclosure is not limited thereto. For example, the side surfaces (or outer surfaces) of the plurality of sub-banks410and420included in the second bank400may also have a curved semicircular or semielliptical shape. In an embodiment, the second bank400may include an organic insulating material, such as polyimide (PI), but is not limited thereto.

The electrode layer200may be disposed on the second bank400and the via layer166exposed by the second bank400. The electrode layer200may be disposed over the first emission area EMA1and the first sub-area SA1.

Each of the first electrode210and the second electrode220may be disposed on the via layer166exposed by the second bank400in the first emission area EMA1and may be disposed on the via layer166in the non-emission area NEM.

In the first emission area EMA1, the first electrode210may be disposed on the first sub-bank410, and the second electrode220may be disposed on the second sub-bank420. In the first emission area EMA1, the first electrode210and the second electrode220may be disposed on at least the inclined side surfaces of the first sub-bank410and the second sub-bank420, respectively. The first and second electrodes210and220may be disposed to cover one side surface of each of the first and second sub-banks410and420that face each other to reflect the light emitted from the light emitting element ED.

The first electrode210may be electrically connected to the circuit element layer CCL through the first electrode contact hole CTD penetrating through the via layer166and the passivation layer165, and the second electrode220may be electrically connected to the circuit element layer CCL through the second electrode contact hole CTS penetrating through the via layer166and the passivation layer165. For example, the first electrode210may be electrically connected to the conductive pattern CDP through the first electrode contact hole CTD, and the second electrode220may be electrically connected to the second voltage line VL2through the second electrode contact hole CTS. The first electrode210may contact an upper surface of the conductive pattern CDP exposed by the first electrode contact hole CTD, and the second electrode220may contact an upper surface of the second voltage line VL2exposed by the second electrode contact hole CTS. The first electrode210may be electrically connected to the transistor TR through the conductive pattern CDP. The second source voltage may be applied to the second electrode220through the second voltage line VL2. While it has been illustrated inFIG.5that the first and second electrode contact holes CTD and CTS are disposed to overlap the first bank600(e.g., the first wall610) in the third direction DR3, positions of the first and second electrode contact holes CTD and CTS are not limited thereto.

As described above, the first electrode210and the second electrode220may be spaced apart from the first electrode210and the second electrode220included in the first sub-pixel SPX1neighboring in the second direction DR2, respectively, at the first separation part ROP1positioned in the first sub-area SA1. Accordingly, in the first separation part ROP1, the via layer166may be exposed by (or through) the first electrode210and the second electrode220.

The first electrode210and the second electrode220may be electrically connected to the light emitting element ED. The first electrode210and the second electrode220may be connected to both ends (e.g., opposite ends) of the light emitting element ED through the first contact electrode710and the second contact electrode720, respectively, and may transfer the electrical signal applied from the circuit element layer CCL to the light emitting element ED.

The electrode layer200may include a conductive material having high reflectivity. For example, the electrode layer200may include a metal, such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), or titanium (Ti), or may include an alloy including aluminum (Al), nickel (Ni), lanthanum (La), or the like as the material having the high reflectivity. The electrode layer200may reflect the light emitted from the light emitting element ED that travels toward the side surfaces of the second bank400in an upward direction of the first sub-pixel SPX1. However, the present disclosure is not limited thereto, and the electrode layer200may further include a transparent conductive material. For example, the electrode layer200may include a material such as ITO, IZO, or ITZO. In some embodiments, the electrode layer200may have a structure in which one or more layers including (or made of) the transparent conductive material and one or more layers including (or made of) the metal having the high reflectivity are stacked or may be formed as one layer including the transparent conductive material and the metal having the high reflectivity. For example, the electrode layer200may have a stacked structure, such as ITO/Ag/ITO, ITO/Ag/IZO, or ITO/Ag/ITZO/IZO.

The first insulating layer510may be disposed on the electrode layer200. The first insulating layer510may be disposed to cover the electrode layer200and the via layer166exposed by the electrode layer200. The first insulating layer510may protect the electrode layer200and may insulate the first electrode210and the second electrode220from each other.

The first insulating layer510may include first and second contact parts CT1and CT2exposing at least portions of the first electrode210and the second electrode220. The contact electrode700and the electrode layer200may be electrically connected to each other through the first and second contact parts CT1and CT2penetrating through the first insulating layer510. While it has been illustrated inFIG.5that the first and second contact parts CT1and CT2, which expose a portion of the electrode layer200, are positioned in the first sub-area SA1, the present disclosure is not limited thereto. For example, the first and second contact parts CT1and CT2exposing portions of the electrode layer200may also be positioned in the first emission area EMA1.

The first bank600may be disposed on the first insulating layer510. The first bank600may be disposed to surround the sub-area SA to define the sub-area SA. The first bank600may be disposed in the non-emission area NEM along a boundary between the sub-area SA and the emission area EMA and may divide the sub-area SA and the emission area EMA. InFIG.5, which illustrates the cross-sectional structure of the first sub-pixel SPX1, the first bank600, for example, the first wall610, may be disposed at the boundary between the first sub-area SA1and the first emission area EMA1on the first insulating layer510to divide the first emission area EMA1and the first sub-area SA1.

The first bank600may be disposed on the first insulating layer510and formed to have a height (e.g., a predetermined height). The height of the first bank600may be greater than that of the second bank400. Because the first bank600has the height and is disposed to surround the first sub-area SA1, the ink in which the plurality of light emitting elements ED are dispersed may be jetted into the first emission area EMA1and may not be jetted into the first sub-area SA1during the inkjet process for aligning the light emitting elements ED from among the processes of manufacturing the display device10. In an embodiment, the first bank600may include an organic insulating material, such as polyimide (PI), but is not limited thereto.

The light emitting element ED may be disposed on the first insulating layer510in the first emission area EMA1. The light emitting element ED may be disposed in the first emission area EMA1and may not be disposed in the first sub-area SA1. The light emitting element ED may be disposed between the first sub-bank410and the second sub-bank420in the first emission area EMA1. The light emitting element ED may be disposed so that both ends thereof are on the first electrode210and the second electrode220, respectively.

The light emitting element ED may emit light in a wavelength band. For example, the light emitting element ED may emit light of a third color (e.g., blue light) having a peak wavelength in the range of 480 nm or less or a peak wavelength in the range of 445 nm to 480 nm or less.

The second insulating layer520may be disposed on the light emitting element ED. The second insulating layer520may be disposed to partially surround an outer surface of the light emitting element ED but may be disposed so as not to cover both ends of the light emitting element ED. Accordingly, a width of the second insulating layer520may be smaller than a length of the light emitting element ED. A portion of the second insulating layer520disposed on the light emitting element ED may be disposed to extend in the second direction DR2on the first insulating layer510in a plan view to form a linear or island-shaped pattern in the first sub-pixel SPX1. The second insulating layer520may protect the light emitting element ED and fix the light emitting element ED during the process of manufacturing the display device10.

The contact electrode700may be disposed on the second insulating layer520. The first contact electrode710and the second contact electrode720included in the contact electrode700may be spaced apart from each other with the second insulating layer520interposed therebetween. The first and second contact electrodes710and720may electrically connect the first and second electrodes210and220to the light emitting element ED, respectively.

The first contact electrode710may contact each of the first electrode210and one end of the light emitting element ED. For example, the first contact electrode710may contact one end of the light emitting element ED exposed by the second insulating layer520in the first emission area EMA1and may contact the first electrode210exposed by the first contact part CT1penetrating through the first insulating layer510in the first sub-area SA1. The first contact electrode710contacts each of one end of the light emitting element ED and the first electrode210such that the first contact electrode710may electrically connect one end of the light emitting element ED and the first electrode210to each other.

The second contact electrode720may contact each of the second electrode220and the other end of the light emitting element ED. For example, the second contact electrode720may contact the other end of the light emitting element ED exposed by the second insulating layer520in the first emission area EMA1and may contact the second electrode220exposed by the second contact part CT2penetrating through the first insulating layer510in the first sub-area SA1. The second contact electrode720contacts each of the other end of the light emitting element ED and the second electrode220such that the second contact electrode720may electrically connect the other end of the light emitting element ED and the second electrode220to each other.

The contact electrode700may include a conductive material. For example, the contact electrode700may include ITO, IZO, ITZO, aluminum (Al), or the like. As an example, the contact electrode700may include a transparent conductive material, and the light emitted from the light emitting element ED may be transmitted through the contact electrode700and then travel toward the first electrode210and the second electrode220and may be reflected by outer surfaces of the first electrode210and the second electrode220.

The protective layer810may be disposed on the contact electrode700. The protective layer810may be disposed to cover the entire surface of the substrate SUB to protect the second bank400, the electrode layer200, the plurality of light emitting elements ED, the contact electrode700, and the first bank600disposed below the protective layer810.

FIG.6is a schematic perspective view of a light emitting element according to an embodiment.

Referring toFIG.6, the light emitting element ED is a particle type element and may have a rod or cylindrical shape having an aspect ratio (e.g., a predetermined aspect ratio). A length of the light emitting element ED is greater than a diameter of the light emitting element ED, and the aspect ratio of the light emitting element ED may be 6:5 to 100:1, but the present disclosure is not limited thereto.

The light emitting element ED may have a size of a nanometer scale (1 nm or more but less than 1 μm) to a micrometer scale (1 μm or more but less than 1 mm). In an embodiment, the light emitting element ED may have a size of a nanometer scale or have a size of a micrometer scale in both the length and the diameter. In some embodiments, the diameter of the light emitting element ED may have a size of a nanometer scale, while the length of the light emitting element ED may have a size of a micrometer scale. In some embodiments, some of the light emitting elements ED have sizes of a nanometer scale in diameter and/or length, while the others of the light emitting elements ED may have a size of a micrometer scale in diameter and/or length.

In an embodiment, the light emitting element ED may be an inorganic light emitting diode. The inorganic light emitting diode may include a plurality of semiconductor layers. For example, the inorganic light emitting diode may include a first conductivity-type (e.g., n-type) semiconductor layer, a second conductivity-type (e.g., p-type) semiconductor layer, and an active semiconductor layer interposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer. The active semiconductor layer may receive holes and electrons from the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, respectively, and the holes and the electrons reaching the active semiconductor layer may be combined with each other to emit light.

In an embodiment, the above-described semiconductor layers may be sequentially stacked along one direction, which is a length direction of the light emitting element ED. The light emitting element ED may include a first semiconductor layer31, an element active layer33, and a second semiconductor layer32that are sequentially stacked in the one direction. The first semiconductor layer31, the element active layer33, and the second semiconductor layer32may be the above-described first conductivity-type semiconductor layer, active semiconductor layer, and second conductivity-type semiconductor layer, respectively.

The first semiconductor layer31may be doped with a first conductivity-type dopant. The first conductivity-type dopant may be Si, Ge, Sn, or the like. In an embodiment, the first semiconductor layer31may be made of n-GaN doped with n-type Si.

The second semiconductor layer32may be disposed to be spaced apart from the first semiconductor layer31with the element active layer33interposed therebetween. The second semiconductor layer32may be doped with a second conductivity-type dopant, such as Mg, Zn, Ca, Se, or Ba. In an embodiment, the second semiconductor layer32may be made of p-GaN doped with p-type Mg.

The element active layer33may include a material having a single or multiple quantum well structure. As described above, the element active layer33may emit light by a combination of electron-hole pairs according to an electrical signal applied through the first semiconductor layer31and the second semiconductor layer32.

In some embodiments, the element active layer33may have a structure in which semiconductor materials having large band gap energy and semiconductor materials having small band gap energy are alternately stacked and may include other Group III to Group V semiconductor materials depending on a wavelength band of emitted light.

The light emitted from the element active layer33may be emitted not only to both end surfaces of the light emitting element ED in the length direction but also to an outer circumferential surface (or an outer surface or a side surface) of the light emitting element. For example, an emission direction of the light from the element active layer33is not limited to one direction.

The light emitting element ED may further include an element electrode layer37disposed on the second semiconductor layer32. The element electrode layer37may contact the second semiconductor layer32. The element electrode layer37may be an ohmic contact electrode, but is not limited thereto. In some embodiments, the element electrode layer37may be a Schottky contact electrode.

The element electrode layer37may be disposed between the second semiconductor layer32and the contact electrode700to reduce resistance therebetween when both ends of the light emitting element ED and the contact electrode700are electrically connected to each other to apply an electrical signal to the first semiconductor layer31and the second semiconductor layer32. The element electrode layer37may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). The element electrode layer37may include an n-type or p-type doped semiconductor material.

The light emitting element ED may further include an element insulating film38surrounding (e.g., extending around) outer peripheral surfaces of the first semiconductor layer31, the second semiconductor layer32, the element active layer33, and/or the element electrode layer37. The element insulating film38may be disposed to surround at least an outer surface of the element active layer33and may extend in one direction in which the light emitting element ED extends. The element insulating film38may protect the first semiconductor layer31, the second semiconductor layer32, the element active layer33, and the element electrode layer37. The element insulating film38may include (or may be made of) materials having insulating properties to prevent an electrical short-circuit that may otherwise occur i the element active layer33directly contacted an electrode through which an electrical signal is transferred to the light emitting element ED. In addition, the element insulating film38protects the outer peripheral surfaces of the first and second semiconductor layers31and32as well as the element active layer33and, thus, may prevent a decrease in luminous efficiency.

FIG.7is an enlarged cross-sectional view illustrating an example of the area A ofFIG.5.

Referring toFIGS.6and7, the light emitting element ED may be disposed so that an extension direction of the light emitting element ED is parallel to one surface of the substrate SUB. The plurality of semiconductor layers included in the light emitting element ED may be sequentially disposed along a direction parallel to an upper surface of the substrate SUB. For example, the first semiconductor layer31, the element active layer33, and the second semiconductor layer32of the light emitting element ED may be sequentially disposed to be parallel to the upper surface of the substrate SUB.

In the light emitting element ED, in a cross section crossing both ends of the light emitting element ED, the first semiconductor layer31, the element active layer33, the second semiconductor layer32, and the element electrode layer37may be sequentially formed in the direction horizontal to the upper surface of the substrate SUB.

The light emitting element ED may be disposed so that one end thereof is on the first electrode210and the other end thereof is on the second electrode220. However, the present disclosure is not limited thereto, and the light emitting element ED may be disposed so that one end thereof is on the second electrode220and the other end thereof is on the first electrode210.

The second insulating layer520may be disposed on the light emitting element ED. The second insulating layer520may be disposed to surround an outer surface of the light emitting element ED. In an area at where the light emitting element ED is disposed, the second insulating layer520may be disposed to surround the outer surface of the light emitting element ED, and in an area at where the light emitting element ED is not disposed, the second insulating layer520may be disposed on the first insulating layer510exposed by the light emitting element ED.

The first contact electrode710may contact one end of the light emitting element ED exposed by the second insulating layer520. For example, the first contact electrode710may be disposed to surround one end surface of the light emitting element ED exposed by the second insulating layer520. The first contact electrode710may contact the element insulating film38and the element electrode layer37of the light emitting element ED.

The second contact electrode720may contact the other end of the light emitting element ED exposed by the second insulating layer520. For example, the second contact electrode720may be disposed to surround the other end surface of the light emitting element ED exposed by the second insulating layer520. The second contact electrode720may contact the element insulating film38and the first semiconductor layer31of the light emitting element ED.

The first contact electrode710and the second contact electrode720may be spaced apart from each other with the second insulating layer520interposed therebetween. The first contact electrode710and the second contact electrode720may expose at least a portion of an upper surface of the second insulating layer520.

The first contact electrode710and the second contact electrode720may be formed on the same layer and may include the same material. For example, the first contact electrode710and the second contact electrode720may be simultaneously formed through one mask process. Accordingly, an additional mask process for forming the first contact electrode710and the second contact electrode720may be omitted, and thus, manufacturing process efficiency of the display device10may be improved.

FIG.8is an enlarged cross-sectional view illustrating the area A ofFIG.5according to another embodiment.

Referring toFIG.8, a display device10according to the embodiment is different from the display device10according to the embodiment described above with reference toFIG.7in that a contact electrode700_1includes a first contact electrode710and a second contact electrode720_1formed on different layers and a light emitting element layer EML further includes a third insulating layer530.

The contact electrode700_1may include the first contact electrode710and the second contact electrode720_1formed on the different layers.

The first contact electrode710may be disposed on the first electrode210and one end of the light emitting element ED. The first contact electrode710may extend from one end of the light emitting element ED toward the second insulating layer520to be also disposed on one sidewall of the second insulating layer520and an upper surface of the second insulating layer520. The first contact electrode710may be disposed on the upper surface of the second insulating layer520but may expose at least a portion of the upper surface of the second insulating layer520.

The third insulating layer530may be disposed on the first contact electrode710. The third insulating layer530may be disposed to completely cover the first contact electrode710. The third insulating layer530may be disposed to completely cover one sidewall and the upper surface of the second insulating layer520but may not be disposed on the other sidewall of the second insulating layer520. One end of the third insulating layer530may be aligned with the other sidewall of the second insulating layer520.

The second contact electrode720_1may be disposed on the second electrode220and the other end of the light emitting element ED. The second contact electrode720_1may extend from the other end of the light emitting element ED toward the second insulating layer520to be also disposed on the other sidewall of the second insulating layer520and an upper surface of the third insulating layer530.

In the embodiment, a process of the display device10is added by forming the first contact electrode710and the second contact electrode720_1on the different layers and interposing the third insulating layer530between the first contact electrode710and the second contact electrode720_1such that the manufacturing process efficiency of the display device10may decrease but reliability of the display device10may be improved. For example, a problem that the first contact electrode710and the second contact electrode720_1are short-circuited in the process of manufacturing the display device10may be reduced or minimized by forming the first contact electrode710and the second contact electrode720_1on the different layers and further disposing the third insulating layer530between the first contact electrode710and the second contact electrode720_1.

Hereinafter, other embodiments of a display device will be described with reference to other drawings.

FIG.9is a schematic plan layout view of one pixel according to another embodiment.

Referring toFIG.9, a display device10according to this embodiment is different from the display device10according to the embodiment described above with reference toFIG.4in that first to third walls610_1,620_1, and630_1have protrusion parts protruding from partial areas of the first to third walls610_1,620_1, and630_1in the second direction DR2.

As shown inFIG.9, the first to third walls610_1,620_1, and630_1may further include protrusion parts protruding upwardly or downwardly in a plan view, respectively.

The first wall610_1may further include a protrusion part protruding toward the second wall620_1at a boundary between the first sub-pixel SPX1and the second sub-pixel SPX2. A width of the protrusion part in the first direction DR1may be smaller than a width of the longitudinal portion of the first610_1in the first direction DR1.

Similarly, the second wall620_1may further include protrusion parts protruding toward the wall610_1or the third wall630_1at the boundary between the first sub-pixel SPX1and the second sub-pixel SPX2and at a boundary between the second sub-pixel SPX2and the third sub-pixel SPX3. A width of the protrusion part in the first direction DR1may be smaller than a width of the longitudinal portion of the second wall620_1in the first direction DR1.

The third wall630_1may further include a protrusion part protruding toward the second wall620_1at the boundary between the second sub-pixel SPX2and the third sub-pixel SPX3. A width of the protrusion part in the first direction DR1may be smaller than a width of the longitudinal portion of the third wall630_1in the first direction DR1.

Even though the first to third walls610_1,620_1, and630_1further include the protrusion parts protruding in the second direction DR2in boundary areas between the sub-pixels SPX, the respective protrusion parts of the first to third walls610_1,620_1, and630_1may be spaced apart from each other. Accordingly, the ink jetted into the emission area EMA may flow to the other emission areas EMA through areas between the first to third walls610_1,620_1and630_1spaced apart from each other, for example, the first to fourth passages PA1, PA2, PA3, and PA4.

The protrusion parts of the first to third walls610_1,620_1, and630_1may adjust widths or shapes, in a plan view, of the above-described passages PA1, PA2, PA3, and PA4. For example, widths of the passages PA1, PA2, PA3, and PA4in the second direction DR2may be adjusted by adjusting lengths of the protrusion parts of the first to third walls610_1,620_1, and630_1. Accordingly, during the process for aligning the light emitting elements ED, the ink jetted into each emission area EMA is induced to flow from one emission area EMA to the other emission areas EMA through the passages PA1, PA2, PA3, and PA4, but the movement of the plurality of light emitting elements ED dispersed in the ink from one emission area EMA to the other emission areas EMA through the passages PA1, PA2, PA3, and PA4is may be prevented or substantially prevented. Accordingly, a display quality of the display device10may be improved by reducing or minimizing a deviation between the numbers of light emitting elements ED aligned in the emission areas EMA of the respective sub-pixels SPX.

FIG.10is a schematic plan layout view of one pixel according to an embodiment.

Referring toFIG.10, a display device10according to this embodiment is different from the display device10illustrated inFIG.4in that the electrode layer200further includes a third electrode230, the second bank400further includes a third sub-bank430, and the contact electrode700further includes a third contact electrode730, in each sub-pixel SPX included in the display device10.

As shown inFIG.10, the electrode layer200disposed in each sub-pixel SPX may further include the third electrode230spaced apart from each of the first electrode210and the second electrode220. The third electrode230may be spaced apart from the first electrode210with the second electrode220interposed therebetween in the first direction DR1and may be spaced apart from the second electrode220in the first direction DR1.

The third electrode230may be disposed over the emission area EMA and the sub-area SA of each sub-pixel SPX. The third electrode230may have a shape in which it extends in the second direction DR2in a plan view. Similar to the first electrode210and the second electrode220, the third electrode230may be disposed over the emission area EMA and the sub-area SA of each sub-pixel SPX but may be spaced apart from a third electrode230included in a sub-pixel SPX neighboring in the second direction DR2at a separation part ROP positioned in the sub-area SA. The third electrode230may not be electrically connected to the circuit element layer CCL, different from the first electrode210and the second electrode220.

The second bank400may further include the third sub-bank430spaced apart from the first sub-bank410and the second sub-bank420. The third sub-bank430may be spaced apart from the first sub-bank410with the second sub-bank420interposed therebetween in the first direction DR1and may be spaced apart from the second sub-bank420in the first direction DR1. The third sub-bank430may be disposed to overlap the third electrode230in the third direction DR3in the emission area EMA of each sub-pixel SPX.

The plurality of light emitting elements ED may be disposed between a plurality of sub-banks410,420, and430in the emission area EMA. The plurality of light emitting elements ED may include a plurality of first light emitting elements ED1disposed between the first sub-bank410and the second sub-bank420and a plurality of second light emitting elements ED2disposed between the second sub-bank420and the third sub-bank430.

The plurality of first light emitting elements ED1may be disposed so that at least one ends thereof are on the first electrode210or the second electrode220in an area in which the first sub-bank410and the second sub-bank420are spaced apart from and face each other. The plurality of second light emitting elements ED2may be disposed so that at least one ends thereof are on the second electrode220or the third electrode230in an area in which the second sub-bank420and the third sub-bank430are spaced apart from and face each other.

The plurality of first light emitting elements ED1disposed between the first sub-bank410and the second sub-bank420may be connected to each other in parallel, and the plurality of second light emitting elements ED2disposed between the second sub-bank420and the third sub-bank430may be connected to each other in parallel. The first light emitting element ED1and the second light emitting element ED2may be connected to each other in series. The first light emitting element ED1and the second light emitting element ED2may be connected to each other in series through a third contact electrode730, to be described later.

The contact electrode700may further include the third contact electrode730spaced apart from the first contact electrode710and the second contact electrode720.

The first contact electrode710may be disposed to overlap the first electrode210in the third direction DR3in the emission area EMA and the sub-area SA of each sub-pixel SPX. The first contact electrode710may be disposed to overlap one end of the plurality of first light emitting elements ED1in the emission area EMA of each sub-pixel SPX. The first contact electrode710may have a shape in which it extends in the second direction DR2in a plan view.

The second contact electrode720may be disposed to overlap the second electrode220in the third direction DR3in the emission area EMA and the sub-area SA of each sub-pixel SPX. The second contact electrode720may be disposed to overlap one end of the plurality of second light emitting elements ED2in the emission area EMA of each sub-pixel SPX. The second contact electrode720may have a shape in which it extends in the second direction DR2in a plan view.

The third contact electrode730may be disposed to be spaced apart from the first contact electrode710and the second contact electrode720. The third contact electrode730may have a first area731, a second area732, and a third area733.

The first area731of the third contact electrode730may be disposed in the emission area EMA of each sub-pixel SPX. The first area731of the third contact electrode730may have a shape in which it extends in the second direction DR2in a plan view in the emission area EMA of each sub-pixel SPX.

The first area731of the third contact electrode730may be disposed to overlap the second electrode220in the third direction DR3in the emission area EMA of each sub-pixel SPX. The first area731of the third contact electrode730may be disposed to overlap the other ends of the plurality of first light emitting elements ED1in the emission area EMA of each sub-pixel SPX.

The second area732of the third contact electrode730may be disposed over the emission area EMA and the sub-area SA of each sub-pixel SPX. The second area732of the third contact electrode730may have a shape in which it extends in the second direction DR2in a plan view.

The second area732of the third contact electrode730may be spaced apart from the first area731of the third contact electrode730in the first direction DR1. The second area732of the third contact electrode730may be disposed to overlap the third electrode230in the third direction DR3in the emission area EMA and the sub-area SA of each sub-pixel SPX. The second area732of the third contact electrode730may be disposed to overlap the other end of the plurality of second light emitting elements ED2in the emission area EMA of each sub-pixel SPX. The second area732of the third contact electrode730may contact the third electrode230through a third contact part CT3in the sub-area SA of each sub-pixel SPX. The second area732of the third contact electrode730and the third electrode230contact each other through the third contact part CT3such that the occurrence of a parasitic capacitance between the second area732of the third contact electrode730and the third electrode230may be reduced or minimized.

The third area733of the third contact electrode730may be disposed between the first area731of the third contact electrode730and the second area732of the third contact electrode730. The third area733of the third contact electrode730may be disposed between the first area731of the third contact electrode730and the second area732of the third contact electrode730to connect the first area731of the third contact electrode730and the second area732of the third contact electrode730to each other.

FIG.11is a cross-sectional view illustrating an example taken along the line II-II′ ofFIG.10.

Hereinafter, a schematic cross-sectional structure of the first sub-pixel SPX1of the display device10illustrated inFIG.10will be described. The schematic cross-sectional structure of the first sub-pixel SPX1may be similarly applied to the second sub-pixel SPX2and the third sub-pixel SPX3. Accordingly, a description for cross-sectional structures of the second sub-pixel SPX2and the third sub-pixel SPX3will be replaced with a description of the cross-sectional structures of the first sub-pixel SPX1.

Referring toFIGS.10and11, the second bank400may be directly disposed on the via layer166. The first to third sub-banks410,420, and430may be disposed to be spaced apart from each other along the first direction DR1on the via layer166.

The electrode layer200may be disposed on the second bank400. For example, the first electrode210may be disposed on the first sub-bank410, the second electrode220may be disposed on the second sub-bank420, and the third electrode230may be disposed on the third sub-bank430.

The first insulating layer510may be disposed on the electrode layer200. The first insulating layer510may be disposed to cover the first to third electrodes210,220, and230in the first emission area EMA1. The first insulating layer510may further include the third contact part CT3exposing at least a portion of the third electrode230in the first sub-area SA1. The second area732of the third contact electrode730and the third electrode230may be electrically connected to each other through the third contact part CT3penetrating through the first insulating layer510.

The first light emitting element ED1and the second light emitting element ED2may be disposed on the first insulating layer510in the first emission area EMA1. The first light emitting element ED1may be disposed between the first sub-bank410and the second sub-bank420in the first emission area EMA1, and the second light emitting element ED2may be disposed between the second sub-bank420and the third sub-bank430in the first emission area EMA1. For example, the first light emitting element ED1and the second light emitting element ED2may be disposed to be spaced apart from each other with the second sub-bank420interposed therebetween. The first light emitting element ED1may be disposed so that both ends thereof are on the first electrode210and the second electrode220, respectively, and the second light emitting element ED2may be disposed so that both ends thereof are on the second electrode220and the third electrode230, respectively.

The second insulating layer520may be disposed on the light emitting element ED. The second insulating layer520may include a first insulating pattern521and a second insulating pattern522.

The first insulating pattern521may be disposed on the first light emitting element ED1. The first insulating pattern521may be disposed to partially cover an outer surface of the first light emitting element ED1but may be disposed so as not to cover both ends of the first light emitting element ED1.

The second insulating pattern522may be disposed on the second light emitting element ED2. The second insulating pattern522may be disposed to partially cover an outer surface of the second light emitting element ED2but may be disposed so as not to cover both ends of the second light emitting element ED2.

The first contact electrode710may be disposed on the first electrode210. The first contact electrode710may contact one end of the first light emitting element ED1exposed by the first insulating pattern521of the second insulating layer520. The first contact electrode710may be electrically connected to the first electrode210through the first contact part CT1. The first contact electrode710may contact each of one end of the first light emitting element ED1and the first electrode210to electrically connect the first electrode210and one end of the first light emitting element ED1to each other.

The second contact electrode720may be disposed on the second electrode220. The second contact electrode720may contact one end of the second light emitting element ED2exposed by the second insulating pattern522of the second insulating layer520. The second contact electrode720may be electrically connected to the second electrode220through the second contact part CT2. The second contact electrode720may contact each of one end of the second light emitting element ED2and the second electrode220to electrically connect the second electrode220and one end of the second light emitting element ED2to each other.

The first area731of the third contact electrode730may be disposed on the second electrode220. The first area731of the third contact electrode730may be spaced apart from the first contact electrode710with the first insulating pattern521of the second insulating layer520interposed therebetween. The first area731of the third contact electrode730may be spaced apart from the second contact electrode720on the second electrode220. The first area731of the third contact electrode730may be in contact with the other end of the first light emitting element ED1exposed by the first insulating pattern521of the second insulating layer520.

The second area732of the third contact electrode730may be disposed on the third electrode230. The second area732of the third contact electrode730may be spaced apart from the second contact electrode720with the second insulating pattern522of the second insulating layer520interposed therebetween. The second area732of the third contact electrode730may be in contact with the other end of the second light emitting element ED2exposed by the second insulating pattern522of the second insulating layer520.

The first contact electrode710may contact each of the first electrode210and one end of the first light emitting element ED1to electrically connect the first electrode210and the first light emitting element ED1to each other. The second contact electrode720may contact each of the second electrode220and one end of the second light emitting element ED2to electrically connect the second electrode220and the second light emitting element ED2to each other. The third contact electrode730may contact each of the other end of the first light emitting element ED1and the other end of the second light emitting element ED2to connect the first light emitting element ED1and the second light emitting element ED2to each other in series.

FIG.12is an enlarged view illustrating a relative layout, in a plan view, of an emission area, a sub-area, and a first bank disposed in the area P1ofFIG.2according to another embodiment.

Referring toFIG.12, this embodiment is different from the embodiment described above with reference toFIG.3in that a fourth wall640_3included in a first bank600_3is spaced apart from the first and third walls610and630disposed on the upper side and the lower side of the fourth wall640_3.

The fourth wall640_3may be disposed at a boundary between the respective pixels PX adjacent to each other in the first direction DR1. The fourth wall640_3may be disposed at a boundary between the first emission area EMA1and the third emission area EMA3of the respective pixels PX disposed adjacent to each other in the first direction DR1. The fourth wall640_3may be disposed adjacent to the third emission area EMA3and the first emission area EMA1on the right side of the third emission area EMA3and the left side of the first emission area EMA1and may expose portions of the third emission area EMA3and the first emission area EMA1in the first direction DR1.

The fourth wall640_3may be spaced apart from the first wall610and the third wall630that are integrated with each other and formed as one pattern. For example, a length of the fourth wall640_3in the second direction DR2may be smaller than widths of the first emission area EMA1and the third emission area EMA3in the second direction DR2. The length of the fourth wall640_3in the second direction DR2is smaller than the width of the first emission area EMA1in the second direction DR2and the width of the third emission area EMA3in the second direction DR2such that the fourth wall640_3may be spaced apart from the first walls610and the third walls630each disposed on the upper side and the lower side of the first emission area EMA1and the third emission area EMA3in the second direction DR2. Accordingly, fifth and sixth passages PA5and PA6defined as areas between the first and third walls610and630and the fourth wall640_3may be formed between the third emission area EMA3of one pixel PX and the first emission area EMA1of another pixel PX disposed on the right side of the one pixel PX.

In the embodiment, the length of the fourth wall640_3in the second direction DR2is smaller than the width of the first emission area EMA1in the second direction DR2and the width of the third emission area EMA3in the second direction DR2, such that the fifth and sixth passages PA5and PA6may be formed between the third emission area EMA3and the first emission area EMA1. Accordingly, ink jetted into each of the first emission area EMA1and the third emission area EMA3of the pixels PX neighboring in the first direction DR1may flow to emission areas EMA of different pixels PX through the fifth and sixth passages PA5and PA6. The ink jetted into each of the first and third emission areas EMA1and EMA3is induced to flow from the emission area EMA of one pixel PX to the emission area EMA of another pixel PX through the fifth and sixth passages PA5and PA6, such that a surface shape of the ink jetted into the emission areas EMA may be flat at an upper side or a lower side of each emission area EMA. Accordingly, it is possible to more effectively prevent the light emitting elements aligned during the process for aligning the light emitting elements from being collected upward and downward in the emission areas EMA due to the shape of the ink.

FIG.13is a schematic layout view illustrating a layout of emission areas and sub-areas of a display device according to an embodiment.

Referring toFIG.13, a display device10according to this embodiment is different from the display device10described above with reference toFIG.2in that it includes first pixels PX1and second pixels PX2of which arrangement directions of emission areas EMA and sub-areas SA are opposite to each other.

The pixels PX may include first pixels PX1and second pixels PX2disposed adjacent to each other in the first direction DR1. Each of the first pixel PX1and the second pixel PX2may include an emission area EMA and a sub-area SA, and an arrangement direction of the emission area EMA and the sub-area SA of the first pixel PX1may be opposite to an arrangement direction of the emission area EMA and the sub-area SA of the second pixel PX2.

An arrangement of the emission area EMA and the sub-area SA of the first pixel PX1may be substantially the same as that of the pixel PX described with reference toFIG.2. For example, a first sub-area SA1included in a first sub-pixel SPX1of the first pixel PX1may be disposed on the upper side of a first emission area EMA1, a second sub-area SA2included in a second sub-pixel SPX2of the first pixel PX1may be disposed on the lower side of a second emission area EMA2, and a third sub-area SA3included in a third sub-pixel SPX3of the first pixel PX1may be disposed on the upper side of a third emission area EMA3.

An arrangement of the emission area EMA and the sub-area SA of the second pixel PX2may be opposite to that of the first pixel PX in the second direction DR2. For example, a first sub-area SA1included in a first sub-pixel SPX1of the second pixel PX2may be disposed on the lower side of a first emission area EMA1, a second sub-area SA2included in a second sub-pixel SPX2of the second pixel PX2may be disposed on the upper side of a second emission area EMA2, and a third sub-area SA3included in a third sub-pixel SPX3of the second pixel PX2may be disposed on the lower side of a third emission area EMA3.

The first sub-area SA1, the second emission area EMA2, and the third sub-area SA3of the first pixel PX1and the first emission area EMA1, the second sub-area SA2, and the third emission area EMA3of the second pixel PX2may be arranged side-by-side in the first direction DR1in the same row. Similarly, the first emission area EMA1, the second sub-area SA2, and the third emission area EMA3of the first pixel PX1and the first sub-area SA1, the second emission area EMA2, and the third sub-area SA3of the second pixel PX2may be arranged side-by-side in the first direction DR1in the same row.

FIG.14is an enlarged view illustrating an example of a relative layout, in a plan view, of an emission area, a sub-area, and a first bank disposed in the area P2ofFIG.13, andFIG.15is a schematic plan layout view of a first pixel and a second pixel according to the embodiment shown inFIG.14.

Referring toFIGS.14and15, a first bank600_4according to this embodiment may include first to third walls610,620, and630disposed in the first pixel PX1and fifth to seventh walls650,660, and670disposed in a second pixel PX2.

The first wall610may be disposed to surround the first sub-area SA1of the first sub-pixel SPX1included in the first pixel PX1, the second wall620may be disposed to surround the second sub-area SA2of the second sub-pixel SPX2included in the first pixel PX1, and the third wall630may be disposed to surround the third sub-area SA3of the third sub-pixel SPX3included in the first pixel PX1.

The fifth wall650may be disposed to surround the first sub-area SA1of the first sub-pixel SPX1included in the second pixel PX2, the sixth wall660may be disposed to surround the second sub-area SA2of the second sub-pixel SPX2included in the second pixel PX2, and the seventh wall670may be disposed to surround the third sub-area SA3of the third sub-pixel SPX3included in the second pixel PX2.

The first to third walls610,620, and630and the fifth to seventh walls650,660, and670may be disposed to be spaced apart from each other. For example, the first wall610, the third wall630, and the sixth wall660may be arranged side-by-side in the first direction DR1but may be spaced apart from each other in the first direction DR1. The second wall620, the fifth wall650, and the seventh wall670may be arranged side-by-side in the first direction DR1but may be spaced apart from each other in the first direction DR1. The first wall610, the third wall630, and the sixth wall660may be spaced apart from the second wall620, the fifth wall650, and the seventh wall670in the second direction DR2.

In an embodiment, the fifth wall650surrounding the first sub-area SA1of the second pixel PX2may be disposed adjacent to the third wall630on the lower right side of the third wall630but may be disposed to be spaced apart from the third wall630in the second direction DR2. Therefore, passages PA5and PA6defined as areas between the third wall630and the fifth wall650may be further formed between the third emission area EMA3of the first pixel PX1and the first emission area EMA1of the second pixel PX2.

Referring toFIG.15, because the first sub-area SA1of the second pixel PX2is disposed on the lower side of the first emission area EMA1, first and second contact electrodes710and720disposed in the first sub-pixel SPX1of the second pixel PX2may contact first and second electrodes210and220, respectively, in the first sub-area SA1disposed on the lower side of the first emission area EMA1. Similarly, first and second contact electrodes710and720disposed in the second sub-pixel SPX2of the second pixel PX2may contact first and second electrodes210and220, respectively, in the second sub-area SA2disposed on the upper side of the second emission area EMA2, and first and second contact electrodes710and720disposed in the third sub-pixel SPX3of the second pixel PX2may contact first and second electrodes210and220, respectively, in the third sub-area SA3disposed on the lower side of the third emission area EMA3.

In an embodiment, the display device10includes the first pixels PX1and the second pixels PX2which the arrangement directions of the emission areas EMA and the sub-areas SA are opposite to each other such that the first emission area EMA1of the second pixel PX2may be disposed adjacent to the third emission area EMA3of the first pixel PX1in a diagonal direction, and the third emission area EMA3of the second pixel PX2may be disposed adjacent to the first emission area EMA1of the first pixel PX1in a diagonal direction. Accordingly, the emission areas EMA of the sub-pixels SPX disposed adjacent to each other in the first direction DR1are disposed in a diagonal direction, and thus, ink jetted into the emission areas EMA may more easily flow from one emission area EMA to the other emission areas EMA to more effectively prevent the light emitting elements ED from being collected upward and downward in the emission areas EMA due to the shape of the ink in the process for aligning the light emitting elements ED.

FIG.16is a schematic layout view illustrating a layout of emission areas and sub-areas of a display device according to an embodiment.

Referring toFIG.16, in a display device10according to this embodiment, first to third sub-areas SA1, SA2, and SA3may be arranged side-by-side in the first direction DR1in the same row, and first to third emission areas EMA1, EMA2, and EMA3may be arranged side-by-side in the first direction DR1in the same row. For example, directions in which emission areas EMA and sub-areas SA of a plurality of sub-pixels SPX included in one pixel PX are arranged may be the same as each other, and directions in which the sub-areas SA are disposed with respect to each of the emission areas EMA of the first to third sub-pixels SPX1, SPX2, and SPX3may be the same as each other. For example, the first to third sub-areas SA1, SA2, and SA3may be disposed on the upper sides of the first to third emission areas EMA1, EMA2, and EMA3, respectively.

FIG.17is an enlarged view illustrating an example of a relative layout, in a plan view, of an emission area, a sub-area, and a first bank disposed in the area P3ofFIG.16, andFIG.18is a schematic plan layout view of one pixel according to the embodiment shown inFIG.17.

Referring toFIGS.17and18, a first bank600_5may include a first pattern680, an eighth wall691, a ninth wall692, and a tenth wall693.

The first pattern680may be disposed to surround the sub-area SA of each sub-pixel SPX. For example, the first pattern680may include a first wall681surrounding the first sub-area SA1of the first sub-pixel SPX1, a second wall682surrounding the second sub-area SA2of the second sub-pixel SPX2, and a third wall683surrounding the third sub-area SA3of the third sub-pixel SPX3. The first to third walls681,682, and683may be integrated and formed as one pattern. Accordingly, the first to third walls681,682, and683may not be physically apparent (e.g., physically apparent as separate structures).

The first pattern680may be disposed to surround the sub-area SA of each sub-pixel SPX as a wall to guide the ink so that the ink is not jetted to the sub-area SA during the inkjet process for aligning the light emitting elements ED from among the processes of manufacturing the display device10.

The eighth wall691may be disposed at a boundary between the first emission area EMA1and the second emission area EMA2. Widths of the first emission area EMA1and the second emission area EMA2in the second direction DR2may be greater than a length of the eighth wall691in the second direction DR2. The eighth wall691may be disposed between the first emission area EMA1and the second emission area EMA2but may be spaced apart from the first pattern680in the second direction DR2. Accordingly, passages PA11and PA12defined as areas between the eighth wall691and the first pattern680may be formed between the first emission area EMA1and the second emission area EMA2.

The ninth wall692may be disposed at a boundary between the second emission area EMA2and the third emission area EMA3. Widths of the second emission area EMA2and the third emission area EMA3in the second direction DR2may be greater than a length of the ninth wall692in the second direction DR2. The ninth wall692may be disposed between the second emission area EMA2and the third emission area EMA3but may be spaced apart from the first pattern680in the second direction DR2. Accordingly, passages PA13and PA14defined as areas between the ninth wall692and the first pattern680may be formed between the second emission area EMA2and the third emission area EMA3.

The tenth wall693may be disposed at a boundary between the third emission area EMA3of one pixel PX and the first emission area EMA1of another pixel PX disposed on the right side of the one pixel PX. A width of the first emission area EMA1in the second direction DR2and a width of the third emission area EMA3in the second direction DR2may be greater than a length of the tenth wall693in the second direction DR2. The tenth wall693may be disposed between the first emission area EMA1and the third emission area EMA3of the pixels PX neighboring in the first direction DR1but may be spaced apart from the first pattern680in the second direction DR2. Accordingly, passages PA15and PA16defined as areas between the tenth wall693and the first pattern680may be formed between the third emission area EMA3and the first emission area EMA1.

In an embodiment, even though the emission areas EMA of the respective sub-pixels SPX are arranged side-by-side along the first direction DR1, the eighth to tenth walls691,692, and693disposed in boundary areas between the emission areas EMA of the respective sub-pixels SPX are formed to be smaller than the widths of the emission areas EMA in the second direction DR2such that the ink jetted into the emission areas EMA may flow to other emission areas EMA through the passages PA11, PA12, PA13, PA14, PA15, and PA16. When the emission areas EMA of the respective sub-pixels SPX are arranged side-by-side along the first direction DR1, a flow of the ink in an upward or downward direction may not be easier than when the emission areas EMA of the respective sub-pixels SPX are disposed adjacent to each other in a diagonal direction, but a design of the first bank600-5is easier, such that manufacturing process efficiency of the display device10may be improved.

FIG.19is a schematic layout view illustrating a layout of emission areas and sub-areas of a display device according to an embodiment.

Referring toFIG.19, this embodiment is different from the embodiment described above with reference toFIG.2in that directions in which emission areas EMA and sub-areas SA of a plurality of sub-pixels SPX included in one pixel PX are arranged are the same as each other.

Directions in which the sub-areas SA are disposed with respect to each of the emission areas EMA of first to third sub-pixels SPX1, SPX2, and SPX3may be the same as each other. For example, the first to third sub-areas SA1, SA2, and SA3may be disposed on the lower sides of the first to third emission areas EMA1, EMA2, and EMA3, respectively.

The first to third sub-pixels SPX1, SPX2, and SPX3included in one pixel PX may be arranged in a diagonal direction. For example, the first to third sub-pixels SPX1, SPX2, and SPX3may be arranged side-by-side in a direction toward the upper right side.

The first sub-area SA1may be disposed on the lower side of the first emission area EMA1, and the second sub-area SA2may be disposed on the right side of the first emission area EMA1. The second sub-area SA2may be disposed on the right side of the first emission area EMA1, but a lower side of the second sub-area SA2may be aligned with a lower side of the first emission area EMA1. The lower side of the second sub-area SA2is aligned with the lower side of the first emission area EMA1, but a width of the second sub-area SA2in the second direction DR2is smaller than a width of the first emission area EMA1in the second direction DR2such that an upper area of the first emission area EMA1and a lower area of the second emission area EMA2in a plan view may overlap each other in the first direction DR1.

Similarly, the second sub-area SA2may be disposed on the lower side of the second emission area EMA2, and the third sub-area SA3may be disposed on the right side of the second emission area EMA2. The third sub-area SA3may be disposed on the right side of the second emission area EMA2, but a lower side of the third sub-area SA3may be aligned with a lower side of the second emission area EMA2. The lower side of the third sub-area SA3is aligned with the lower side of the second emission area EMA2, but a width of the third sub-area SA3in the second direction DR2is smaller than a width of the second emission area EMA2in the second direction DR2such that an upper area of the second emission area EMA2and a lower area of the third emission area EMA3may overlap each other in the first direction DR1.

In addition, the first sub-area SA1may be disposed on the left side of a second emission area EMA2of another pixel PX disposed adjacent to one pixel PX on the lower side of the one pixel PX. An upper side of the first sub-area SA1may be aligned with an upper side of the second emission area EMA2of another pixel PX disposed adjacent to one pixel PX on the lower side of the one pixel PX. Similarly, the second sub-area SA2may be disposed on the left side of a third emission area EMA3of another pixel PX disposed adjacent to one pixel PX on the lower side of the one pixel PX. An upper side of the second sub-area SA2may be aligned with an upper side of the third emission area EMA3of another pixel PX disposed adjacent to one pixel PX on the lower side of the one pixel PX. The third sub-area SA3may be disposed on the left side of a first emission area EMA1of another pixel PX disposed adjacent to one pixel PX on the right side of the one pixel PX. An upper side of the third sub-area SA3may be aligned with an upper side of the first emission area EMA1of another pixel PX disposed adjacent to one pixel PX on the right side of the one pixel PX.

FIG.20is an enlarged view illustrating an example of a relative layout, in a plan view, of an emission area, a sub-area, and a first bank disposed in the area P4ofFIG.19, andFIG.21is a schematic plan layout view of one pixel according to the embodiment shownFIG.20.

Referring toFIGS.20and21, a first bank600according to this embodiment may include first to fourth walls610,620,630, and640integrated with each other to form one pattern (e.g., one continuous or integrated pattern).

The first bank600may be disposed to surround each emission area EMA, but to expose a portion of each emission area EMA.

The first wall610may be disposed to surround the first sub-area SA1, the second wall620may be disposed to surround the second sub-area SA2, and the third wall630may be disposed to surround the third sub-area SA3. The fourth wall640may be disposed at a boundary between the third emission area EMA3of one pixel PX and the first emission area EMA1of another pixel PX disposed on the right side of the one pixel PX. The fourth wall640may be disposed at the boundary between the third emission area EMA3and the first emission area EMA1to divide the third emission area EMA3and the first emission area EMA1.

The first walls610may be disposed on the upper side and the lower side of the first emission area EMA1, respectively, the second wall620may be disposed on the right side of the first emission area EMA1, and the fourth wall640may be disposed on the left side of the first emission area EMA1. The first walls610, the second wall620, and the fourth wall640may be integrated to form one pattern. Accordingly, the first walls610, the second wall620, and the fourth wall640disposed adjacent to the first emission area EMA1may not be physically apparent.

The second wall620disposed on the right side of the first emission area EMA1may be spaced apart from the first wall610disposed on the upper side of the first emission area EMA1, in the second direction DR2. Accordingly, an upper area of the first emission area EMA1may be exposed in the first direction DR1by at least the second wall620. A portion of the first emission area EMA1exposed in the first direction DR1by the second wall620may overlap a lower area of the second emission area EMA2in the first direction DR1to form a passage PA17. The passage PA17may be defined as an area between the first wall610and the second wall620between the first emission area EMA1and the second emission area EMA2.

The second walls620may be disposed on the upper side and the lower side of the second emission area EMA2, respectively, the third wall630may be disposed on the right side of the second emission area EMA2, and the first wall610(e.g., the first wall610disposed in another pixel PX adjacent to one pixel PX on the upper side of the one pixel PX) may be disposed on the left side of the second emission area EMA2. The second wall620disposed on the lower the second emission area EMA2and the third wall630disposed on the right side of the second emission area EMA2may be integrated and be not physically apparent, and the second wall620disposed on the upper side of the second emission area EMA2and the first wall610disposed on the left side of the second emission area EMA2may be integrated and be not physically apparent.

The third wall630disposed on the right side of the second emission area EMA2may be spaced apart from the second wall620disposed on the upper side of the second emission area EMA2, in the second direction DR2. Accordingly, an upper area of the second emission area EMA2may be exposed in the first direction DR1by at least the third wall630. A portion of the second emission area EMA2exposed in the first direction DR1by the third wall630may overlap a lower area of the third emission area EMA3in the first direction DR1to form a passage PA18. The passage PA18may be defined as an area between the second wall620and the third wall630between the second emission area EMA2and the third emission area EMA3.

The fourth wall640disposed on the right side of the third emission area EMA3may be integrated with the third walls630each disposed on the upper side and the lower side of the third emission area EMA3to form one pattern. Accordingly, the third walls630, the second wall620, and the fourth wall640disposed adjacent to the third emission area EMA3may not be physically apparent.

In this embodiment, the first bank600may be disposed at a boundary between the respective pixels PX so as to one pixel PX to divide one pixel PX and another pixel PX. In addition, the first bank600may be formed so that the passages PA17and PA18defined by the first to third walls610,620, and630are formed between the first emission area EMA1, the second emission area EMA2, and the third emission area EMA3arranged in the diagonal direction in one pixel PX. Accordingly, ink jetted into the respective emission areas EMA1, EMA2, and EMA3may flow to the other emission areas EMA disposed in the diagonal direction through the passages PA17and PA18. Accordingly, a surface shape of the ink jetted into the emission areas EMA may be flat at an upper side and an lower side of each emission area EMA, and the light emitting elements ED aligned in the process for aligning the light emitting elements ED may not be collected upward and downward in the emission areas EMA due to the shape of the ink.

In concluding the detailed description, those skilled in the art will appreciate that many variations and modifications can be made to the embodiments described herein without substantially departing from the aspects and features of the present disclosure. Therefore, the embodiments of the present disclosure described herein are used in a generic and descriptive sense and not for purposes of limitation.