Patent ID: 12254259

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

FIG.1is an illustration of a single row height system, in accordance with some embodiments. According to some embodiments, a single row height system100includes three rows101,102and103of the same height, which corresponds to the same number of fins. According to some embodiments, the rows101,102and103all have two fins. According to some embodiments, a first cell121is deployed over the first row101, and a second cell122is deployed over the second and the third rows102and103.

FIG.2is an illustration of a hybrid row height system, in accordance with some embodiments. According to some embodiments, a hybrid row height system200includes a plurality of rows of at least two different heights. According to some embodiments, the rows201,203and205are of a first height, and the rows202and204are of a second height. According to some embodiments, the first height corresponds to two fins and the second height corresponds to one fin. According to some embodiments, a first cell221is deployed over the row201with the first row height, and a second cell222is deployed over rows203and204with the first row height and the second row height respectively. According to some embodiments, the row204has a smaller row height compared to the row203with the first row height. Or alternatively, the row203has more fins than the row204, thus the row203has a larger driving strength than row204because smaller row height results in weaker driving strength. According to some embodiments, the area of cell222needs to be enlarged to cell222′ to compensate for the performance degradation. According to some embodiments, the cell222′ is deployed over rows203,204and205, of which, the rows203and205are of larger height, or more fins, and the row204is of smaller height, or less fins. According to some embodiments, the cell area shrinkage ratio cannot be maintained on multi-row height cells in the hybrid row-height system because the cell height is modified while maintaining the cell width.

FIG.3is an illustration of another hybrid row height system, in accordance with some embodiments. According to some embodiments, another hybrid row height system300includes a plurality of rows of at least two different heights. According to some embodiments, rows301,302,304and305are of a first height, and a row303is of a second height. According to some embodiments, the first height corresponds to a larger number of fins, and the second row height corresponds to a smaller number of fins. Similar to the discussion inFIG.2, a first cell321is deployed over the row301, and a second cell322is deployed over the rows303and304of second height and first height respectively. For the same reasons discussed above inFIG.2, the second cell322needs to be enlarged to322′ to cover rows302,303and304to compensate for performance degradation. And as discussed above, the cell area shrinkage ratio cannot be maintained on multi-row height cells in the hybrid row-height system because the cell height is modified while maintaining the cell width.

FIG.4is an illustration of four discrete multi-row cells systems, in accordance with some embodiments. According to some embodiments, rows401,403,405and407are of a first row height, and rows402,404,406and408are of a second row height. According to some embodiments, the first row height corresponds to two fins, and the second row height corresponds to one fin. According to some embodiments, rows401-408are of more than two row heights. According to some embodiments, a first discrete multi-row cell410deployed over rows401,402and403is split into two discrete sub-cells411and412each deployed over the rows401and403respectively. FEOL, front-end-of-line, is the first portion of IC fabrication process where individual devices such as transistors, capacitors and resistors are patterned on the semiconductor. FEOL generally covers everything up to, but not including, the deposition of metal interconnect layers. BEOL, back-end-of-line is the second portion of IC fabrication process where the individual devices get interconnected with wiring on the wafer, the metallization layer. According to some embodiments, BEOL generally starts when the first layer of metal is deposited on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels and bonding sites for chip-to-package connections. MEOL, middle-end-of-line, refers to the process or process unit making metal channels either in wafer fabs, or in outsourced assembly and test houses. The process and the process unit are beyond what described in FEOL and BEOL. MEOL has emerged after the appearance of 3DS ICs. According to some embodiments, the sub-cells411and412are connected by wires410A and410B in MEOL or BEOL. According to some embodiments, the empty space between the sub-cells411and412can be used to fill in with other cells or signal routing. According to some embodiments, similarly, a discrete multi-row cell420is split into sub-cells421,422and423over the rows401,403and405respectively, connected by wires420A,420B and420C in MEOL or BEOL. According to some embodiments, similarly, a discrete multi-row cell430is split into sub-cells431,432and433over the rows401,403and405respectively, connected by wires430A,430B and430C in MEOL or BEOL. According to some embodiments, the sub-cells are not aligned. For example, the sub-cell432is not aligned with either the sub-cell431or the sub-cell433. According to some embodiments, the wires connect sub-cells separated by more than one rows. For example, wire430A connects the sub-cells431and433separated by the rows402-404. According to some embodiments, similarly, a discrete multi-row cell440is split into sub-cells441,442,443and444over the rows401,403,405and407respectively, connected by wires440A,440B,440C and440D in MEOL or BEOL. According to some embodiments, the sub-cells are of varying sizes. For example, the sub-cell442is smaller than the sub-cells441and443, and the sub-cell444is larger than the sub-cells441-443. Empty spaces surrounding all the sub-cells can be used to fill in with other cells or signal routing.

FIG.5is an illustration of another four discrete multi-row cells systems, in accordance with some embodiments. According to some embodiments, a discrete multi-row cell450deployed over the rows401-407is split into three discrete sub-cells451,452and453each deployed over the rows401,405and407respectively. According to some embodiments, the sub-cells451,452and453are connected by wires450A,450B and450C in MEOL or BEOL. According to some embodiments, a discrete multi-row cell460deployed over the rows401-407is split into three discrete sub-cells461,462and463each deployed over rows401,403and407respectively. According to some embodiments, the sub-cells461,462and463are connected by wires460A,460B and460C in MEOL or BEOL. According to some embodiments, a discrete multi-row cell470deployed over the rows401-407is split into three discrete sub-cells471,472and473each deployed over rows401,403-405and407respectively. According to some embodiments, the sub-cells471,472and473are connected by wires470A,470B,470C and470D in MEOL or BEOL. According to some embodiments, a sub-cell covers more than one rows. According to some embodiments, a sub-cell covers rows of different heights. For example, the sub-cell473covers three rows403-405of at least two different heights. According to some embodiments, the wires connect the sub-cells within a discrete multi-row cell with components outside the discrete multi-row cell. For example, the wires470A and470E connect the sub-cells471and473with components outside the discrete multi-row cell470. According to some embodiments, a discrete multi-row cell480deployed over rows401-408is split into two discrete sub-cells481and482each deployed over rows403and405respectively. According to some embodiments, the sub-cells481and482are connected by wires480A,480B,480C and480D in MEOL or BEOL. As discussed above, all empty spaces surrounding sub-cells can be used to fill in with other cells or signal routing. According to some embodiments, rows401-408are of more than two row heights.

FIG.6is an illustration of empty spaces and a marker layer in discrete multi-row cells systems, in accordance with some embodiments. For illustration purpose, a discrete multi-row cell610has the same configuration as the discrete multi-row cell410discussed above, the cell610is deployed over rows401,402and403. The cell610is split into two discrete sub-cells611and612deployed over rows401and403respectively, connected by wires610A and610B. According to some embodiments, the space615between the discrete sub-cells611and612is an empty space, which can be used to fill in with other cells, for example a cell682of matching geometry. According to some embodiments, the other cell682is another functional cell of matching geometry. According to some embodiments, the other cell682is a spare cell, or a dummy, of matching geometry. According to some embodiments, the other cell682of matching geometry does not need to occupy the entirety of the empty space615, instead, the other cell682of matching geometry may only fill part of the empty space615.

For illustration purpose, a discrete multi-row cell640has the same configuration as the discrete multi-row cell440discussed above. According to some embodiments, the cell640is split into four discrete sub-cells641,642,643and644over the rows401,403,405and407respectively, connected by wires640A,640B,640C and640D in MEOL or BEOL. Empty spaces surrounding sub-cells are used to fill in with other cells or signal routing. According to some embodiments, an empty space645is filled with another cell685of matching geometry, an empty space646is filled with another cell686of matching geometry, empty spaces647and647′ are filled with another cell687of matching geometry, an empty space649is filled with another cell689of matching geometry, an empty space648is left empty. As illustrated, other cells can be placed entirely inside the empty spaces, or partially inside the empty spaces as long as the geometry matches. According to some embodiments, some other cells681,683and684are outside any empty spaces of the discrete multi-row cells610and640. According to some embodiments, a marker layer is implemented either as text or polygons to the layout to identify the empty spaces645,646,647,647′,648and649.

FIG.7is illustration of cell placement and wiring in discrete multi-row cells systems, in accordance with some embodiments. According to some embodiments, the empty spaces surrounding the discrete sub-cells can be used for signal, power and ground wiring and clock networking. In addition to the discrete sub-cells and other cells inFIG.6,FIG.7illustrates horizontal wire connections710A,710B,710C,720A,720B and720C. For example, the wire710C is implemented as a wire feedthrough. According to some embodiments, these wire connections are implemented to connect among discrete sub-cells, other functional cells, spare cells, or for feedthrough. According to some embodiments, such effective usage of the empty spaces between or among the discrete sub-cells maintains cell area shrinkage ratio and performance while reducing negative impacts on other cells.

FIG.8is a flowchart illustrating the method for multi-row cell design in discrete multi-row cells systems, in accordance with some embodiments. According to some embodiments, a method for multi-row cell design in discrete multi-row cells system800includes step810, obtaining hybrid-row specifications, which includes for example, geometric configurations of hybrid rows, row heights, number of fins, locations and orders. At step820, obtaining cell driving target specifications, which includes for example cell driving target information for each cell, discrete sub-cell, etc. At step830, analyzing discrete multi-row specification. According to some embodiments, each row has a row height corresponding to a number of fins. According to some embodiments, all the row-heights are the same. According to some embodiments, there are at least two different row-heights corresponding to at least two different number of fins. Step830involves decomposing the hybrid-row system to understand the specification of each row style, such as row heights and available fins of oxide diffusion. Step830also involves estimating the achievable driving strength of discrete multi-row cells according to the hybrid-row specification and cell driving target specification. At step840, deriving discrete multi-row cell styles. According to some embodiments, by analyzing row heights and cell configurations, cells are split into discrete multi-row sub-cells matching the row-heights and cell driving target specifications, as discussed above. Step840involves generating available discrete multi-row styles and compositions, such as cells410-480illustrated inFIG.4andFIG.5. At step850, generating discrete multi-row cells by splitting cells into sub-cells with matching geometry and target cell driving specification. Step850involves generating the target discrete multi-row cells based on the styles and specifications discussed above. At step860, conducting discrete multi-row cell quality control to ensure the generated discrete multi-row cells match quality control targets. Step860involves analyzing each generated cells to ensure no design rule violation in the cells and among cells. At step870, if the quality control fails, then go back to step850to re-generate discrete multi-row cells. At step870, if the quality control passes, then go to step880. At step880, generating marker layers on the empty spaces to potentially accommodate other cells in the empty space with matching geometry and performance specification. Step880involves implementing marker layers on the empty spaces to allow wire feedthrough and other cell placement to achieve better area shrinking ratio and to reduce the impact of discrete multi-row cells. At step890, discrete multi-row cells matching specifications are completed.

FIG.9is a system chart illustrating a layout design system, in accordance with some embodiments. According to some embodiments, a layout design system900include at least a processor990for processing all information related to design of floor plan and cell layout, etc. The layout design system900also include at least a memory module920for storing information related to design of floor plan and cell layout. The memory module920can also be implemented to store software and tools for layout design and related tasks. According to some embodiments, the layout design system900can include input and output modules930, the layout design system900can also be connected to network910for information exchange. According to some embodiments, the layout design system900can be connected to fabrication tools940, after the layout design is finalized, the layout design is forwarded to the fabrication tools940for fabrication of the integrated circuit according to the layout design. According to some embodiments, the layout design system900can be connected to layout generation tools, IC fabrication tools and mask fabrication tools.

According to some embodiments, an IC is disclosed. The IC includes: a plurality of rows of at least two different row-heights, a first sub-cell deployed on a first row of cells with a first row-height; a second sub-cell deployed on a second row of cells with a second row-height, wherein the second row and the first row is separated by a third row of cells with a third row-height, wherein the third row-height is different from the first row-height, wherein the first sub-cell and the second sub-cell are electrically connected by at least a wire.

According to some embodiments, the third row-height is different from the second row-height. According to some embodiments, the first row-height and the second row-height are the same. According to some embodiments, the first row-height and the second row-height are different. According to some embodiments, the third row-height is smaller than the first row-height. According to some embodiments, the third row-height is smaller than both the first row-height and the second row-height. According to some embodiments, the first sub-cell is of the same size as the second sub-cell. According to some embodiments, first sub-cell is of a size different from the second sub-cell.

According to some embodiments, a method for multi-row cell design in discrete multi-row cells systems is disclosed. The method includes: obtaining hybrid-row specifications; obtaining cell driving target specifications; analyzing discrete multi-row specifications; deriving discrete multi-row cell styles; generating the discrete multi-row cell by splitting a cell into discrete sub-cells with matching geometry and target cell driving specifications; conducting the discrete multi-row cell quality control to ensure the generated discrete multi-row cell match quality control targets; and under a condition when the quality control fails, re-generating the discrete multi-row cell by splitting the cell into sub-cells with matching geometry and target cell driving specifications.

According to some embodiments, the method further comprises: under a condition when the quality control passes, generating a marker layer of empty spaces to potentially accommodate other cells in the empty space with matching geometry and performance specifications. According to some embodiments, the method further comprises: completing the generation of discrete multi-row cell with matching specifications. According to some embodiments, analyzing discrete multi-row specification further comprises: decomposing the hybrid-row system to understand the specification of each row style. According to some embodiments, analyzing discrete multi-row specification further comprises: estimating an achievable driving strength of the discrete multi-row cell according to the hybrid-row specification and the cell driving target specifications. According to some embodiments, deriving discrete multi-row cell styles further comprises: generating available discrete multi-row styles and compositions. According to some embodiments, conducting discrete multi-row cell quality control further comprises: analyzing the generated discrete multi-row cell to ensure no design rule violation in the generated discrete multi-row cell and among other cells. According to some embodiments, generating a marker layer of the empty spaces further comprises: implementing a marker layer of the empty spaces to allow wire feedthrough. According to some embodiments, generating a marker layer of the empty spaces further comprises: implementing a marker layer of the empty spaces to allow other cell placement. According to some embodiments, generating a marker layer on the empty spaces is implemented to achieve better area shrinking ratio and to reduce the impact of discrete multi-row cells.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.