Patent ID: 12253558

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are of course, merely examples and are not intended to be limiting.

FIG.1depicts a three-dimensional integrated circuit (3DIC)100including at least one Kelvin structure110. 3DIC100includes a top chip102over an interposer104. Top chip102includes a conductive line120. Conductive line120is a continuous line extending around a perimeter of top chip102and positioned parallel to the exterior edges of top chip102. Conductive line120is spaced a predefined distance from the exterior edge of top chip102. Conductive line120is electrically connected to connectors112. Connectors112are positioned between top chip102and interposer104and configured to provide electrical connection between top chip102and interposer104. Testing sites114are positioned on each of top chip102and interposer104and are electrically connected to connectors112on each of top chip102and interposer104.

Top chip102includes active devices such as transistors or other suitable circuitry. In some embodiments, 3DIC100includes one top chip102. In some embodiments, 3DIC100includes more than one top chip102. In some embodiments, top chip102is an integrated circuit. In some embodiments, top chip102is a high speed integrated circuit. In some embodiments having more than one top chip102, a Kelvin structure is formed on each top chip102. In some embodiments having more than one top chip102, a Kelvin structure is formed on only one top chip102.

Interposer104is configured to electrically connect to top chip102. Interposer104contains conductive routing layers and vias configured to transfer signals within interposer104. In some embodiments having more than one top chip102, interposer104is configured to electrically connect each top chip102. In some embodiments, interposer104is configured to transfer signals between top chips102. In some embodiments, interposer104is electrically connected to a substrate.

In some embodiments, interposer104comprises a dielectric material such as silicon dioxide or a low k dielectric material. A low k dielectric material is a dielectric material having a dielectric constant, k, below 3.5 such as fluorine doped silicon dioxide, carbon doped silicon dioxide, aerogel or other suitable dielectric material. The dielectric material provides electrical isolation between the routing layers and vias of interposer104to reduce the risk of short circuits.

Connectors112are configured to provide electrical connection between top chip102and interposer104. In some embodiments, connectors112comprise a solder material. In some embodiments, the solder material is a lead free solder. In some embodiments, the solder material comprises tin and silver. In some embodiments, connectors112are configured to attach to top chip102through bump pad structures on a back surface of top chip102. In some embodiments, connectors112are configured to attach to top chip102through copper pillar structures on the back surface of top chip102. In some embodiments, connectors112are configured to attach to interposer104through bump pad structures on a front surface of interposer104. In some embodiments, connectors112are configured to attach to interposer104through copper pillar structures on the front surface of interposer104. In some embodiments, a spacing between adjacent connectors112ranges from 30 μm to 50 μm.

Testing sites114are configured to electrically connect to connectors112on top chip102and interposer104. That is, for each connector112on top chip102, a testing site114positioned on top chip102is configured to electrically connect to the connector112and for each connector112or interposer104, a testing site114positioned on interposer104is configured to electrically connect to the connector112. In some embodiments, testing sites114comprise a conductive pad. In some embodiments, testing sites114comprise a through substrate via (TSV). In some embodiments, testing sites114comprise copper, aluminum, nickel, titanium, alloys or other suitable conductive material.

Conductive line120is configured to electrically connect to connectors112on top chip102. Conductive line120is a continuous conductive element extending parallel to the exterior edges of top chip102and set back from the exterior edges by a predefined distance. Conductive line120is configured to permit current and voltage to travel between connectors112. In some embodiments, conductive line120comprises copper, aluminum, nickel, titanium, alloys or other suitable conductive materials. In the embodiment ofFIG.1, conductive line120is formed only on top chip102. In some embodiments, both top chip102and interposer104include conductive line120. Conductive line120on interposer104is positioned in substantially the same manner as conductive line120on top chip102.

In some embodiments, conductive line120is a sealing ring formed on top chip102. The sealing ring is a metal ring formed between elements of 3DIC100to prevent moisture or debris from entering an interior portion of the circuit layers. Moisture and debris increase the likelihood of short circuits in the circuit layers. In some embodiments, conductive line120on top chip102is separate from the sealing ring. In some embodiments, conductive line120is a sealing ring formed on interposer104. In some embodiments, conductive line on interposer104is separate from the sealing ring. In some embodiments, conductive line120on one of top chip102or interposer104is the sealing ring and conductive line120on the other of top chip102and interposer104is separate from the sealing ring. In an embodiment in which the conductive line120is separate from the sealing ring, conductive line120is displaced from the sealing ring toward an interior portion of top chip102or interposer104.

FIG.2depicts an example Kelvin structure110. In some embodiments, a group of connectors112and testing sites114collective form a Kelvin structure110.FIG.2depicts top chip102and interposer104electrically connected by connectors112.FIG.2further depicts testing sites114a1,114a2,114b1and114b2on interposer104. Testing sites114a1and114a2are conductive pads and testing sites114b1and114b2are TSVs. Connectors112on top chip102are configured to be electrically connected by conductive line120.

By applying a voltage to one of testing sites114a1and one of testing sites114a2and measuring a current between the other of testing sites114a1and the other of testing sites114a2, a resistance of the connectors112and conductive line120is determined. If a substantially zero resistance is determined, then a short circuit is likely present. If a substantially infinite resistance is determined, then connectors112likely failed to provide sufficient electrical connection between top chip102and interposer104. If the determined resistance substantially equals a resistance calculated from the known materials of the connectors112, testing sites114a1,114a2,114b1and114b2, and conductive line120, then connectors112provide sufficient electrical connection between top chip102and interposer104.

In some embodiments, top chip102is substantially rectangular having one Kelvin structure110at each of the four corners of top chip102, as shown inFIG.1. In some embodiments, top chip102has a different shape. In some embodiments, top chip102has at least one Kelvin structure110at each corner of top chip102. In some embodiments, top chip102has at least one Kelvin structure110at each corner of top chip102and at an additional location along at least one side of top chip102.

Because conductive line120is configured to electrically connect each of connectors112, Kelvin structure110on 3DIC100facilitates measuring whether top chip102is damaged during a bonding process. In some embodiments, a bonding process to connect top chip102to interposer104involves pressing top chip102and interposer104together. If the force exerted during the bonding process exceeds the mechanical strength of top chip102, top chip102can warp or fracture. In some embodiments, the warping or fracture of top chip102results in a breaking or bending in conductive line120. The breaking or bending of conductive line120increases the resistance of conductive line120. The increased resistance is detectable by applying a voltage to testing sites114and measuring a current resulting from the applied voltage. By connecting conductive line120to connectors112, 3DIC is testable to determine warping or fracturing of top chip102and the existence of sufficient electrical connection between top chip102and interposer104.

In some embodiments, the resistance of conductive line120and connectors112is measured following the completion of the bonding process. In some embodiments, the resistance of conductive line120and connectors112is measured during the bonding process. Measuring the resistance during the bonding process provides information regarding when top chip102and interposer104are sufficiently electrically connected. Stopping the bonding process when top chip102and interposer104are sufficiently electrically connected avoids the exertion of unnecessary force on top chip102and interposer104, reducing the likelihood of warping or fracture.

FIG.3depicts a 3DIC200including top chip102and interposer104. 3DIC200also includes connectors112configured to electrically connect top chip102and interposer104. Conductive line120is positioned on top chip102and is configured to electrically connect connectors112on top chip102. 3DIC200also includes a test circuit130on top chip102and a test circuit140on interposer104. Test circuit130is configured to electrically connect to each of connectors112on top chip102. Test circuit140is configured to electrically connect to each of connectors112on interposer104.

In some embodiments, the materials, shape and composition of top chip102, interposer104, connectors112and conductive line120for 3DIC200are substantially the same as 3DIC100.

Test circuit130is configured to determine the resistance between connectors112on top chip102. In some embodiments, a probe is connected to test circuit130to supply a testing voltage to connectors112and measure the resulting voltage. In some embodiments, test circuit130is configured to connect to a supply voltage of top chip102. In some embodiments, test circuit130includes a voltage supplying unit configured to supply a testing voltage. In some embodiments, test circuit130is configured to provide an alert when the resistance between connectors112is outside a predetermined range. In this manner test circuit130determines whether top chip102is warped or fractured.

In some embodiments, connectors112on interposer104are electrically connected through test circuit140. If connectors112on interposer104are electrically connected through test circuit140, test circuit130can measure the resistance between connectors112on top chip102and connectors112on interposer104. The measured resistance between connectors112on top chip102and connectors112on interposer104helps a manufacturer determine whether connectors112provide sufficient electrical connection between top chip102and interposer104.

In some embodiments, connectors112on interposer104are not electrically connected through test circuit140. If connectors112on interposer104are not electrically connected through test circuit140, test circuit130cannot measure the resistance between connectors112on top chip102and connectors112on interposer104. Test circuit140is configured to measure the resistance between connectors112on top chip102and connectors112on interposer104. In some embodiments, test circuit140is substantially the same as test circuit130.

FIG.4depicts a 3DIC300including top chip102and interposer104. 3DIC300also includes connectors112configured to electrically connect top chip102and interposer104. Conductive line120positioned on top chip102is configured to electrically connect connectors112on top chip102. 3DIC300also includes testing sites114aand114bon interposer104. Testing sites114aand114bare configured to electrically connect to connectors112on interposer104. Testing sites114aare on a front surface of interposer104. Testing sites114bare on a back surface of interposer104opposite the front surface. Testing sites114bare configured to electrically connect to testing sites114aby TSVs142.

In some embodiments, the materials, shape and composition of top chip102, interposer104, connectors112and conductive line120for 3DIC300are substantially the same as 3DIC100.

In some embodiments, testing sites114aallow detection of the resistance of connectors112and conductive line120in a manner substantially the same as testing sites114in 3DIC100. In some embodiments, the front surface of interposer104is not accessible following the bonding process. Testing sites114bare configured to electrically connect to testing sites114aand allow testing of the resistance of connectors112and conductive line120. In a manner similar to 3DIC100, 3DIC300includes a Kelvin structure110′, comprising connectors112and testing sites114aand114b, in each of the four corners of interposer104. By applying a voltage to appropriate testing sites114band measuring a current at other testing sites114b, the resistance of connectors112and conductive line120of 3DIC300is determined. The resistance helps the manufacturer determine whether top chip102is warped or fractured and whether connectors112provide sufficient electrical connection between top chip102and interposer104.

FIG.5depicts a 3DIC400including top chip102and interposer104. 3DIC400also includes connectors112configured to electrically connect top chip102and interposer104. Conductive line120, positioned on top chip102is configured to electrically connect connectors112on top chip102. 3DIC400also includes a test circuit130on top chip102and a test circuit140on interposer104. Test circuit130is configured to electrically connect to each of connectors112on top chip102. Test circuit140is configured to electrically connect to each of connectors112on interposer104. 3DIC400also includes testing sites114bconfigured to electrically connect to test circuit140through TSVs142.

In some embodiments, the materials, shape and composition of top chip102, interposer104, connectors112and conductive line120for 3DIC400are substantially the same 3DIC100.

In some embodiments, test circuit140detects the resistance of connectors112and conductive line120in a manner substantially the same as test circuit140in 3DIC200. In some embodiments, the front surface of interposer104is not accessible following the bonding process. Testing sites114bare configured to electrically connect to test circuit140and allow testing of the resistance of connectors112and conductive line120. In some embodiments, a voltage is supplied to test circuit140through testing sites114b. In some embodiments, test circuit140is configured to electrically connect to a supply voltage in top chip102. In some embodiments, test circuit140includes a voltage supply. In some embodiments, test circuits130and140of 3DIC400are substantially the same as test circuits130and140of 3DIC200. In a manner substantially the same as test circuit140in 3DIC200, test circuit140in 3DIC400measures the resistance of connectors112and conductive line120. The resistance helps the manufacturer determine whether top chip102is warped or fractured and whether connectors112provide sufficient electrical connection between top chip102and interposer104.

FIG.6depicts an interposer104including conductive line120on the front surface of interposer104. Interposer104further includes testing sites114aand114b. Conductive line120is configured to electrically connect to testing sites114aand114b. Testing sites114aare on the front surface of interposer104. Testing sites114bare on the back surface of interposer104and configured to electrically connect to testing sites114athrough TSVs142.

In the embodiment ofFIG.6, testing sites114aare located at each corner of interposer104. In some embodiments, interposer104includes additional testing sites114aand114bpositioned along at least one side between the corners on the front surface of interposer104. In some embodiments, the front surface of interposer104is not accessible following the bonding process. Testing sites114bare configured to electrically connect to testing sites114aand allow testing of the resistance of conductive line120.

If the force exerted during the bonding process exceeds the mechanical strength of interposer104, interposer104can warp or fracture. In some embodiments, the warping or fracture of interposer104results in a breaking or bending in conductive line120. The breaking or bending of conductive line120increases the resistance of conductive line120. The increased resistance is detectable by applying a voltage to testing sites114aor114band measuring a current resulting from the applied voltage. The inclusion of conductive line120on interposer104makes interposer104testable to determine warping or fracturing of interposer104.

FIG.7depicts an interposer104including conductive line120on the front surface of interposer104. Interposer104further includes test circuit140and testing sites114b. Conductive line120is configured to electrically connect to test circuit140and testing sites114b. Test circuit140is on the front surface of interposer104. Testing sites114bare on the back surface of interposer104and configured to electrically connect to test circuit140through TSVs142.

In some embodiments, test circuit140detects the resistance of conductive line120in a manner substantially similar to test circuit130in 3DIC200. In some embodiments, the front surface of interposer104is not accessible following the bonding process. Testing sites114bare configured to electrically connect to test circuit140and allow measurement of the resistance of conductive line120. In some embodiments, a voltage is supplied to test circuit140through testing sites114b. In some embodiments, test circuit140is configured to electrically connect to a supply voltage in top chip102. In some embodiments, test circuit140includes a voltage supply. In a manner substantially the same as test circuit130in 3DIC200, test circuit140measures the resistance of conductive line120. The resistance helps determine whether interposer104is warped or fractured.

FIG.8depicts an interposer104including conductive line120on the back surface of interposer104. Interposer104further includes testing sites114aand114b. Conductive line120is configured to electrically connect to testing sites114aand114b. Testing sites114aare on the back surface of interposer104. Testing sites114bare on the back surface of interposer104and configured to electrically connect to testing sites114a.

In the embodiment ofFIG.8, testing sites114aare located at each corner of interposer104. In some embodiments, interposer104includes additional testing sites114aand114bpositioned along at least one side between the corners on the back surface interposer104.

In some embodiments, a substrate is bonded to the back surface of interposer104. Following, the bonding of the substrate to the back surface of interposer104, the back surface of interposer104is no longer accessible, in some embodiments. Testing sites114bare configured to electrically connect to testing sites114aand allow measurement of the resistance of conductive line120.

If the force exerted during the bonding process exceeds the mechanical strength of interposer104, interposer104can warp or fracture. In some embodiments, the warping or fracture of interposer104results in a breaking or bending in conductive line120. The breaking or bending of conductive line120increases the resistance of conductive line120. The increased resistance is detectable by applying a voltage to testing sites114aor114band measuring a current resulting from the applied voltage. The inclusion of conductive line120on interposer104makes interposer104testable to determine warping or fracturing of interposer104.

FIG.9depicts an interposer104including conductive line120on the back surface of interposer104. Interposer104further includes test circuit140and testing sites114b. Conductive line120is configured to electrically connect to test circuit140and testing sites114b. Test circuit140is on the back surface of interposer104. Testing sites114bare on the back surface of interposer104and configured to electrically connect to test circuit140through TSVs142.

In some embodiments, a substrate is bonded to the back surface of interposer104. Following, the bonding of the substrate to the back surface of interposer104, the back surface of interposer104is no longer accessible, in some embodiments. Testing sites114bare configured to electrically connect to test circuit140and allow testing of the resistance of conductive line120.

In some embodiments, test circuit140detects the resistance of conductive line120in a manner substantially similar to test circuit130in 3DIC200. In some embodiments, a voltage is supplied to test circuit140through testing sites114b. In some embodiments, test circuit140is configured to electrically connect to a supply voltage in top chip102. In some embodiments, test circuit140includes a voltage supply. In a manner substantially the same as test circuit130in 3DIC200, test circuit140measures the resistance of conductive line120. The resistance helps the manufacturer determine whether interposer104is warped or fractured.

An aspect of this description relates to a circuit test structure. The circuit test structure includes a chip including a conductive line which traces a perimeter of the chip. The circuit test structure further includes an interposer electrically connected to the chip, wherein the conductive line is over both the chip and the interposer. The circuit test structure further includes a test structure connected to the conductive line. The circuit test structure further includes a testing site, wherein the test structure is configured to electrically connect the testing site to the conductive line. In some embodiments, the test structure is on the chip. In some embodiments, the circuit test structure further includes a second testing site electrically connected to the conductive line, wherein the second testing site is on the interposer. In some embodiments, the test structure is on the interposer. In some embodiments, the test structure extends from the chip to the interposer. In some embodiments, the testing site is on the chip. In some embodiments, the testing site is on the interposer.

An aspect of this description relates to a circuit test structure. The circuit test structure includes a chip including a conductive line which traces a perimeter of the chip. The circuit test structure further includes an interposer electrically connected to the chip. The circuit test structure further includes a test structure connected to the conductive line, wherein the test structure is on a first side of the interposer. The circuit test structure further includes a testing site on a second side of the interposer, wherein the test structure is configured to electrically connect the testing site to the conductive line. In some embodiments, the test structure extends between the chip and the interposer. In some embodiments, the circuit test structure further includes a through silicon via (TSV) extending through the interposer, wherein the TSV electrically connects the testing site to the test structure. In some embodiments, the circuit test structure further includes a second testing site, wherein the second testing site is on the first side of the interposer. In some embodiments, the chip is free of testing sites. In some embodiments, the circuit test structure further includes a test circuit on the interposer. In some embodiments, the test circuit is electrically between the testing site and the conductive line.

An aspect of this description relates to a circuit test structure. The circuit test structure includes a chip including a conductive line along at least two sides of the chip. The circuit test structure further includes a first test circuit on the chip. The circuit test structure further includes an interposer electrically connected to the chip. The circuit test structure further includes a second test circuit on the interposer, wherein the first test circuit is electrically connected to the second test circuit through the conductive line. The circuit test structure further includes a testing site on the interposer, wherein the testing site is connected to the second test circuit. In some embodiments, the second test circuit is on a first side of the interposer, and the testing site is on a second side of the interposer opposite the first side. In some embodiments, the chip is free of testing sites. In some embodiments, the circuit test structure further includes a test structure extending between the chip and the interposer. In some embodiments, the test structure electrically connects the second test circuit to the conductive line. In some embodiments, the circuit test structure further includes a through silicon via (TSV) extending through the interposer, wherein the TSV electrically connects the testing site to the second test circuit.

It will be readily seen by one of ordinary skill in the art that the disclosed embodiments fulfill one or more of the advantages set forth above. After reading the foregoing specification, one of ordinary skill will be able to affect various changes, substitutions of equivalents and various other embodiments as broadly disclosed herein. It is therefore intended that the protection granted hereon be limited only by the definition contained in the appended claims and equivalents thereof.