Patent ID: 12223865

DETAILED DESCRIPTION OF THE INVENTION

In order to make the structure and characteristics as well as the effectiveness of the present application to be further understood and recognized, the detailed description of the present application is provided as follows along with embodiments and accompanying figures.

In the specifications and subsequent claims, certain words are used for representing specific devices. A person having ordinary skills in the art should know that hardware manufacturers might use different nouns to call the same device. In the specifications and subsequent claims, the differences in names are not used for distinguishing devices. Instead, the differences in functions are the guidelines for distinguishing. In the whole specifications and subsequent claims, the word “comprising” is an open language and should be explained as “comprising but not limited to”. Besides, the word “couple” includes any direct and indirect electrical connection. Thereby, if the description is that a first device is coupled to a second device, it means that the first device is connected electrically to the second device directly, or the first device is connected electrically to the second device via another device or connecting means indirectly.

When the drivers of the existing display panel perform self-tests, a new test circuit is added inside the display panel, and the test circuit is used to perform built-in self-tests on the drivers inside the display panel. However, the problem caused by the new circuit is that it occupies the internal space of the display panel. Hence, the overall circuit layout should be changed according to the self-test method.

The present application provides a display driving circuit and the method for testing the drivers thereof. By equipping the original circuit with a testing module, self-tests may be performed on the display panel, thereby saving circuit layout area and reducing the use of external testing equipment.

In the following description, various embodiments of the present application are described using figures for describing the present application in detail. Nonetheless, the concepts of the present application may be embodied in various forms. Those embodiments are not used to limit the scope and range of the present application.

Please refer toFIG.1A, which shows a circuit diagram of the display driving circuit according to the first embodiment of the present application. As shown in the figure, according to the first embodiment of the present application, a display driving circuit1comprises a control circuit10and a plurality of driver rows20. The control circuit10is coupled to the driver rows20. Each driver row20includes a plurality of (for example, N) drivers201˜20N connected in series. A first data node D0of the control circuit10is coupled to a data line DL0, and a second data node D1of the control circuit10is coupled to a second data line DL1; a control clock node CKC of the control circuit10is coupled to a first clock line CL0, and a data clock node CKD of the control circuit10is coupled to a second clock line CL1. An enable output node ENO of the control circuit10is coupled to an enable line ENL. The first data line DL0, the second data line DL1, the first clock line CL0, and the second clock line CL1according to the present embodiment are connected in series with the plurality of drivers201˜20N. Enable lines ENL are connected between the plurality of drivers201˜20N according to the present embodiment. The control circuit10is coupled to the first driver201via the enable line ENL.

Please further refer toFIG.1B, which shows a partial circuit diagram of the display driving circuit according to the first embodiment of the present application. As shown in the figure, according to the circuit diagram shown inFIG.1A, the first driver201, the second driver202, and the coupled control circuit10are taken as an example The first driver201and the second driver202include a clock driving unit302, a data control unit304, a light-emitting driving unit306, an enable unit308, and a power control unit310, respectively. The control clock node CKC of the clock driving unit302is coupled to the control circuit10via the first clock line CL0for receiving a clock control signal CLK. The data clock node CKD, the first data node DO, and a second data node D1of the data control unit304are coupled to the control circuit10via the second clock line CL1, the first data line DL0, and the second data line DL1. The data control unit304receives the data clock signal DLK via the second clock line CL1. The data clock signal DLK is used for controlling the driver rows20to drive a display device (not shown in the figure) of the display panel30, such as driving AMOLED, mini LED, or micro LED, to display.

The light-emitting driving unit306is coupled to a driving voltage node VDD, a first reference voltage node VREF1, a second reference voltage node VREF2, and a third reference voltage node VREF3of the control circuit10for receiving a driving voltage VDR, a first reference voltage VR1, a second reference voltage VR2, and a third reference voltage VR3of the control circuit10. Each enable unit308includes an enable input node ENI and an enable output node ENO. The enable input node ENI of the first driver201is coupled to the enable output node ENO of the control circuit10. The enable input node ENI of the second driver202is coupled to the enable output node ENO of the first driver201. The enable output node ENO of the second driver202is coupled to the enable input node ENI of the next driver, and so on, to the Nth driver20N. Each power control unit310is coupled to a supply voltage node VCC and a ground GND of the control circuit10.

Please refer toFIG.1CandFIG.1Dtogether, in which the drawings ofFIG.1CandFIG.1Dshow block diagrams of the control circuit and the driver according to the first embodiment of the present application. As shown inFIG.1C, the control circuit10according to the present application includes a first testing module12for performing self-tests. The first testing module12includes a system control and processing unit SC, a clock signal unit CG, a panel testing model control element M1, a control counter CC, and a data detector DE. The system control processing unit SC receives the clock control signal CLK generated by the clock signal unit CG for correspondingly generating the enable signal EN and a testing command CMD according to the clock control signal CLK. The enable signal EN is outputted via the enable output node ENO. In addition, the system control processing unit SC generates the testing command CMD to the panel testing model control element M1, which generates a start signal ST according to the testing command CMD. The control counter CC counts a first counting value according to the data comparison result of the data detector DE. For example, when the comparison result is YES, the first counting value is increased by one.

As shown inFIG.1D, according to the present embodiment, a driver22is taken as an example for illustrating the drivers201˜20N as described above. The driver22includes a second testing module222used for performing self-tests and includes a data control unit304, an enable unit308, and a panel testing model driving unit M2. The enable unit308includes a driving counter UC and an output control unit P. The panel testing model driving unit M2is used for receiving the start signal ST for initializing the testing mode. Thereby, the enable unit308will drive the driver22to perform testing upon receiving the enable signal EN. The first data node DO, the second data node D1, and the data clock node CKD of the data control unit304are coupled to the first data node DO, the second data node D1, and the data clock node CKD of the data detector DE via the first data line DL0, the second data line DL1, and the second clock line CL1, respectively. The driving counter UC of the enable unit308receives the enable signal EN via the enable input node ENI of the enable unit308and counts a second counting value CN2according to the enable signal EN. For example, each time when the enable signal EN is enabled, namely, the voltage level is high, the second counting value is increased by one. Besides, the driving counter UC of the driver22drives the output control unit P to receive the enable signal EN via enable input node ENI of the enable unit308. Thereby, the enable output node ENO of the driver22may output the enable signal EN to the next driver connected in series with thereof.

Please further refer toFIG.2, which shows a flowchart of the method for testing the display driving circuit according to the first embodiment of the present application. As shown in the figure, the method for testing a plurality of drivers connected in series according to the present application is that the control circuit10tests the plurality of drivers201˜20N, which are connected in series. The control circuit10transmits the enable signal EN to the plurality of drivers201˜20N for driving them to perform self-tests sequentially. Namely, the tests are performed from the first driver201to the Nth driver20N. According to the present embodiment, the control circuit10testing the first driver201and the second driver202is taken as an example. The testing method according to the present application comprises the following step:

Step S10: Control circuit testing drivers according to first voltage level and/or second voltage level so that control circuit comparing first returned voltage level and/or second returned voltage level with first preset parameter and/or second preset parameter.

In the step S10, the control circuit10transmits the first voltage level and the second voltage level via the first data line DL0, the second data line DL1, or their combination for testing the first driver201. By this method, the plurality of drivers201˜2N may perform self-tests. The first driver201may generate the corresponding first returned voltage level and the second returned voltage level according to the first voltage level and the second voltage level and returned voltage level along the original path or switch their paths to the control circuit10, so that the control circuit10compares the first returned voltage level and/or the second returned voltage level returned by the first driver201with the first preset parameter and/or the second preset parameter and thus performing self-tests.

In addition, the testing method according to the present application further comprises:Step S20: Judging if first counting value equal to N;Step S30: Generating abnormal signal; andStep S40: Generating end signal.

In the step S20, the system control processing unit SC judges if the counter CC has increased its counting value to N, meaning that the system control processing unit SC may judge if the Nth driver20N has completed self-tests. When the judgment is false (NO), the system control processing unit SC executes the step S30for stopping self-tests and generating an abnormal signal. When the judgment is true (YES), the system control processing unit SC executes the step S40for generating an end signal represented that the first driver201to the Nth driver20N has completed self-tests already.

The detailed steps of the step S10is described in the following.

Please further refer toFIG.3A, which shows a flowchart of the method for testing the display driving circuit according to the second embodiment of the present application. The step S10includes the following steps:Step S100: Control circuit transmitting first voltage level to first driver;Step S110: First driver returning the first returned voltage level to control circuit;Step S120: Judging if first returned voltage level equal to first preset parameter;Step S130: Control circuit transmitting second voltage level to first driver;Step S140: First driver returning the second returned voltage level to control circuit;Step S150: Judging if second returned voltage level equal to second preset parameter;Step S160: Control circuit stopping testing second driver; andStep S170: First driver transmitting enable signal to second driver.

When the first returned voltage level is not equal to the first preset parameter or the second returned voltage level is not equal to the second preset parameter, the control circuit10stops proceeding to test the next driver.

Please refer toFIG.1C,FIG.1D, and FFIG.3AtoFIG.3F. As shown inFIG.3AtoFIG.3F, according to the present embodiment, the control circuit10transmitting data to the first driver201and the second driver202via the first data line DL0is taken as an example for following illustration.

In the step S100, the first testing module12of the control circuit10transmits a first voltage level V1to the data control unit304of the first driver201via the first data node D0of the data detector DE.

In the step S110, the data control unit304of the first driver201generates a first returned voltage level B0according to the first voltage level V1and transmits the first returned voltage level B0to the control circuit10via the first data node D0of the data control unit304.

In the step S120, the data detector DE of the control circuit10compares the first returned voltage level B0and the first preset parameter DE0. When the first returned voltage level B0is equal to the first preset parameter DE0, the control circuit10executes the step S130. When the first returned voltage level B0is not equal to the first preset parameter DE0, the control circuit10executes the step S160.

In the step S130, the first data node D0of the data detector DE of the control circuit10transmits a second voltage level V2to the data control unit304of the first driver201.

In the step S140, the data control unit304of the first driver201generates a second returned voltage level B1according to the second voltage level V2and transmits the second returned voltage level B1to the control circuit10via the first data node D0of the data control unit304.

In the step S150, the data detector DE of the control circuit10compares the second returned voltage level B1and the second preset parameter DEL. When the second returned voltage level B1is equal to the second preset parameter DE1, the control circuit10executes the step S170. When the second returned voltage level B1is not equal to the second preset parameter DEL, the control circuit10executes the step S160.

In the step S160, the control circuit10will stops testing via the system control processing unit SC. In particular, the system control processing unit SC drives the panel testing model control element M1to stop the corresponding driver22for stopping self-tests.

In the step S170, the system control processing unit SC of the control circuit10outputs the enable signal EN to the enable unit308for enabling the driving counter UC to drive the output control unit P outputting the enable signal EN to the next driver via the enable line ENL, namely, inputting the enable signal EN to the enable unit308of the second driver202.

To further illustrate that the control circuit10and the first driver201perform self-tests according to the present application, please further refer toFIG.3C, which shows a schematic diagram of the steps of the control circuit according to the first embodiment of the present application, and together refer toFIG.3D, which shows a schematic diagram of the steps of the driver according to the first embodiment of the present application. As shown inFIG.3CandFIG.3D, the flowcharts of the control circuit10and the first driver201performing self-tests. In the step S200, the control circuit10starts to execute self-tests. The system control processing unit SC receives a clock control signal CL from a clock signal unit CG for driving a panel testing model control element M1. In the step S210, the system control processing unit SC drives the control counter CC to execute zeroing. In other words, the first counting value CN1of the control counter CC is driven to zero. The control circuit10transmits the enable signal EN to the first driver201via the system control processing unit SC. The panel testing model control element M1of the first testing module12transmits the start signal ST to the panel testing model driving unit M2of the second testing module222.

The first driver201executes the step S330. The second testing module222of the first driver201receives the start signal ST, which enables the driving counter UC to start counting and hence executing self-tests is started. In the step S310, the first driver201zeros the driving counter UC. In other words, the driving counter UC zeros the second counting value CN2. In the step S320, the driving counter UC is zeroed and second counting value CN2is not increased to 1, 2, or 3. Thereby, the judgment is maintained as false (NO) for executing the step S340to the step S380. In the step S380, the first driver201receives the start signal ST and the first driver201is driven to set in the input mode. Namely, the first data node D0of the first driver201is set to the input mode. Next, in the step S390, the first driver201judges if the received enable signal EN is enabled. If the judgment is true (YES), the step S400will be executed. The driving counter UC of the first driver201counts the second counting value CN2as the second counting value CN2is increased by one. At this moment, the first counting value CN1is 0 and the second counting value is 1. Then, the control circuit10executes the step S220for transmitting the first voltage level V1to the first driver201, which continues to execute the steps S320to S360. In the step S360, since the second counting value CN2is 1, the step S370is executed for transmitting the first returned voltage level B0to the control circuit10according to the first voltage level V1. In addition, the step S390is executed until the received enable signal EN is judged to be enabled. When the first driver201receives the enable signal EN in enabled, the step S400is executed, in which the driving counter UC counts the second counting value CN2as the second counting value CN2is increased by one. At this moment, the second counting value CN2is 2.

Please refer toFIG.3EandFIG.3F, which shows a signal timing diagram and a schematic diagram of signal transmission according to the first embodiment of the present application. According to the present embodiment, when the enable signal EN is enabled, the control circuit10starts to execute self-tests and transmits the start signal ST to the first driver201concurrently so that the first driver201starts self-tests as well. The control circuit10transmits a first voltage level V1to the data control unit304of the first driver201via the data detector DE and the first data line DL0. The first data node D0of the first driver201is used for receiving the first voltage level V1. According to the first embodiment, the second counting value CN2is 1 and the first voltage level V1is enabled. The control circuit10transmits the first voltage level V1to the first driver201so that the first driver201may return the first returned voltage level B0to the control circuit10via the first data line DL0. In other words, the first voltage level V1is transmitted to the control circuit10. The first voltage level V1is used to judge if short circuit occurs at the first driver201. According to the present embodiment, although the first voltage level V1is proposed to be high level, it is not limited to a high level. Once the first voltage level V1may be used to make sure that the first driver201is not short-circuited, the tests may go on.

Please together refer toFIG.1C,FIG.1D, andFIG.3AtoFIG.3F. The control circuit10continues to execute the step S230. The data detector DE of the control circuit10compares the first returned voltage level B0and the first preset parameter DE0. When the judgment is true (YES), the step S240is executed, in which the control circuit10transmits the second voltage level V2to the first driver201. When the judgment is false (NO), the step S20is executed. According to the present embodiment, the corresponding voltage of the first preset parameter DE0is the first voltage level V1. Thereby, the control circuit10receives the first returned voltage level B0via the data detector DE and compares it with the first preset parameter DE0, which is equivalent to comparing the first voltage level with the first voltage level and hence making the judgment true (YES). Next, the step S240is executed. Nonetheless, when the judgment is false (NO), the step S20will be executed, in which the control circuit10judges if the first counting value CN1is equal to N, meaning to judge if the tests have been performed to the Nth driver20N. When the first counting value CN1is N, the step S40is executed, meaning that the self-tests have been completed and ended. If not, the step S30is executed, meaning that the current driver test is abnormal. At this time, the control circuit10stops testing and the system control processing unit SC will generate an abnormal signal for notifying. For example, if the second driver202is abnormal, the abnormal signal will correspond to the second driver202.

Please refer toFIG.1C,FIG.1D, andFIG.3AtoFIG.3F. In the step S240, the control circuit10transmits a second voltage level V2to the data control unit304of the first driver201via the data detector DE and the first data line DL0. The first data node D0of the first driver201is used for receiving the second voltage level V2.

According to the present embodiment, the second voltage level V2is low level. The control circuit10transmits the second voltage level V2to the first driver201. The data control unit304of the first driver judges if the voltage level variation occurs in the first driver201according to the pull-down second voltage level V2. Thereby, the second voltage level V2must be different from the first voltage level V1. According to the present embodiment, although the second voltage level V2is proposed to be low level, it is not limited to a low level. Once the second voltage level V2may be used to make sure that the voltage level variation occurs in the first driver201, the tests may go on.

At this time, the first driver201executes the step S320and judges false (NO). Then the first driver201transmits the second returned voltage level B1to the control circuit10via the first data line DL0. The control circuit10may use the second returned voltage level B1to judge if the voltage variation occurs in the first driver201. The first driver201returns the second returned voltage level B1to the control circuit10via the first data line DL0, which means that the first driver201returns the second voltage level V2to the control circuit10directly. The first driver201executes the steps S350and S390until the received enable signal EN is judged to be enabled. If the first driver201receives the enable signal EN, the step S400is executed, in which the driving counter UC counts and the second counting value CN2is increased by one. At this time, the second counting value CN2is 3.

Please refer toFIG.1CandFIG.1Dagain and toFIG.3AtoFIG.3F. After the control circuit10receives the second returned voltage level B1, the step S250is executed, in which the second returned voltage level B1is compared with the second preset parameter DE1preset in the control circuit10or input to the control circuit10during the testing process. According to the present embodiment, the corresponding voltage level of the second preset parameter DE1is the second voltage level V2. When the two are equal, the control circuit10continues to execute the step S260. When the two are not equal or the control circuit10does not receive the second returned voltage level B1, the control circuit10continues to execute the step S20. The control circuit10judges if the first counting value CN1is equal to N. The steps S20to S40will not be described again.

After finishing the step S250and the second returned voltage level B1equal to the second preset parameter DE1, the control circuit10executes the step S260. The control counter CC of the control circuit10is increased by one. Namely, the first counting value CN1is increased by one. At this time, CN1is equal to 1. Meanwhile, the control circuit10transmits the enable signal EN to the first driver201. At this time, the second counting value CN2is 3. The first driver201continues to execute the step S320. Since the judgment is true, the step S330is executed next. The first driver201is set to the input mode. Namely, the first data node D0of the first driver201is set to the input mode. Besides, the driving counter UC of the first driver201drives the output control unit P to output the enable signal EN to the enable input node ENI of the next driver202connected in series via the enable output node ENO. For example, as shown inFIG.1B, the enable output node ENO of the first driver201is coupled to the enable input node ENI of the second driver202. Thereby, the first driver201transmits the enable signal EN to the second driver202. The control circuit10executes the steps220to S260repeatedly and the second driver202executes the steps S300to S400repeatedly until the first counting value CN1is N (meaning that tests of the plurality of drivers201˜20N have been completed) or executes the step S30for judging abnormality and stopping testing.

Please refer toFIG.3Eagain. ENI(201) inFIG.3Erepresents the signal at the enable input node ENI of the first driver201; D0(201) represents the signal at the first data node D0of the first driver201; ENI(202) represents the signal at the enable input node ENI of the second driver202; and D0(202) represents the signal at the first data node D0of the second driver202. According to a preferred embodiment, the first voltage level V1and the second voltage level V2are reversed. Nonetheless, the present application is not limited to the embodiment. Once the first voltage level V1and the second voltage level V2may achieve the testing function, the embodiment will be applicable. According to the present embodiment, the control circuit10outputs the first voltage level V1and the second voltage level V2at different times.

Please refer toFIG.3AandFIG.3Cagain. InFIG.3A, the steps S100-S150are executed for judging if the step S170should be executed. According to another embodiment, if the judgment in the step S150is true, then the steps S100-S120will be added. At this time, if the judgment in the step S120is true, then the step S170will be executed. InFIG.3C, the steps S220˜S250are executed for judging if the step S260should be executed. According to another embodiment, if the judgment in the step S250is true, then the steps S220˜S230will be added. At this time, if the judgment in the step S230is true, then the step S260will be executed.

According to the previous embodiment of the method for testing display driving circuit of the present application, the panel circuit is adopted for testing. A data line DL0between the control circuit10and the drivers is used to transmit the voltage levels V1, V2and the returned voltage levels B0, B1for performing built-in self-tests. Thereby, the problem of requiring external testing circuits or testers may be solved.

Next, please refer toFIG.4AtoFIG.4F, which show a flowchart and a schematic diagram of the control circuit, the drivers, and the data lines, a schematic diagram of the steps of the control circuit, a schematic diagram of the steps of the driver, and a signal timing diagram of the method for testing the display driving circuit according to the present application. Based on the previous embodiment, the present application further includes a third voltage level V3and a fourth voltage level V4. The first voltage level V1and the third voltage level V3are transmitted via the first data line DL1; the second voltage level V2and the fourth voltage level V4are transmitted via the second data line DL1. Preferably, the third voltage level V3and the fourth voltage level V4may be the reversed state of the first voltage level V1and the second voltage level V2. Alternatively, the fourth voltage level V4is equal to the first voltage level V1; the third voltage level V3is equal to the second voltage level V2. Nonetheless, the present application is not limited to the above embodiments. Once the third voltage level V3and the fourth voltage level V4may achieve the testing function, the embodiment will be applicable. In addition, the first driver201returns the corresponding returned voltage levels B0˜B3to the control circuit10via the first data line DL0and the second data line DL1for testing.

Please refer toFIG.1CandFIG.1Dagain and toFIG.4AtoFIG.4F. The present embodiment comprises steps of:Step S102: Control circuit transmitting first voltage level and second voltage level to first driver;Step S112: First driver transmitting first returned voltage level and second returned voltage level to control circuit;Step S122: Control circuit comparing if first returned voltage level and second returned voltage level equal to first preset parameter and second preset parameter;Step S132: Control circuit transmitting third voltage level and fourth voltage level to first driver;Step S142: First driver transmitting third returned voltage level and fourth returned voltage level to control circuit;Step S152: Control circuit comparing if third returned voltage level and fourth returned voltage level equal to third preset parameter and fourth preset parameter;Step S160: Control circuit stopping testing second driver; andStep S170: Driver transmitting enable signal to next driver.

The steps S160and S170are identical to the previous embodiment; the details will not be repeated. Next, in the step S102, the control circuit10transmits the first voltage level V1to the first driver201via the first data line DL0and the second voltage level V2to the first driver201via the second data line DL0. The first data node D0of the first driver201is used for receiving the first voltage level V1; the second data node D1of the first driver201is used for receiving the second voltage level V2. According to the present embodiment, the first voltage level V1is high level; the second voltage level V2is low level. The judgment if the first driver201is short-circuited is performed by pulling up the first voltage level V1and pulling down the second voltage level V2. According to the present embodiment, although the first voltage level V1is high level and the second voltage level V2is low level. Nonetheless, the present application is not limited to the embodiment. Once the first voltage level V1and the second voltage level V2may be used to make sure that the first driver201is not short-circuited, the tests may go on.

In the step S112, after judging if the first driver201is short-circuited, the first driver201returns the first returned voltage level B0to the control circuit10via the first data line DL0and returns the second returned voltage level B1to the control circuit10via the second data line DL1. According to the present embodiment, the first driver201may return the first voltage level V1and the second voltage level V2to the control circuit10directly. Next, in the step S122, the first returned voltage level B0and the second returned voltage level B1are compared with the first preset parameter DE0and the second preset parameter DEL. When they are equal, the step S132is executed.

In the step S132, the control circuit10transmits the third voltage level V3and the fourth voltage level V4. According to the present embodiment, the third voltage level V3is low level and the fourth voltage level V4is high level. The judgment if the voltage level variation occurs in the first driver201is performed by pulling down the third voltage level V3and pulling up the fourth voltage level V4. Thereby, the third voltage level V3must be different from the first voltage level V1, and the fourth voltage level V4must be different from the third voltage level V3. According to the second embodiment, although the third voltage level V3is low level and the fourth voltage level V4is high level, their voltage levels are not limited. Once the third voltage level V3and the fourth voltage level V4may be used to make sure that the voltage variation occurs in the first driver201, the tests may go on. In the step S142, the first driver201transmits the third returned voltage level B2and the fourth returned voltage level B3via the first data line DL0and the second data line DL1to the control circuit10. According to the present embodiment, the first driver201may return the third voltage level V3and the fourth voltage level V4to the control circuit10directly. Next, in the step S152, compare the third returned voltage level B2and the fourth returned voltage level B3according to the third preset parameter DE2and the fourth preset parameter DE3. When they are equal, the step S132is executed. When one of them is not equal, the step S160is executed.

After finishing a cycle of tests on the first driver201, likewise, the enable signal EN of the first driver201is transmitted to the next driver202for testing. The driving counter UC of the first driver201drives the output control unit P to output the enable signal EN to the enable input node ENI of the next driver via the enable output node ENO. For example, as shown inFIG.1B, the enable output node ENO of the first driver201is coupled to the enable input node ENI of the second driver202. Thereby, the first driver201transmits the enable signal EN to the second driver202. The steps222to S260shown inFIG.4Cand the steps S300to S400shown inFIG.4Dare executed repeatedly.

Furthermore, please refer toFIG.4CandFIG.4D, which show schematic diagrams of the steps with reference to the flowchart shown inFIG.4A. The difference betweenFIG.3CandFIG.3Daccording to the previous embodiment is that, inFIG.4CandFIG.4D, the control circuit10further transmits the third voltage level V3and the fourth voltage level V4to the first driver201and the second driver202. In addition, the first driver201and the second driver202further return the third returned voltage level B2and the fourth returned voltage level B3.

The steps S200˜S210, S260, S20˜S40, S300˜S310, and S390˜S400are identical to the previous embodiment. Hence, the details will not be repeated. In the step S222, instead, the control circuit10transmits the first voltage level V1and the second voltage level V2to the first driver201. Since the second counting value CN2is 0, the step S382is executed. The driver201is set to the input mode. In other words, the first data node D0and the second data node D1of the first driver201are set to the input mode. Then the step S400is executed to make the second counting value CN2to be 1. Then, in the step S362, since the second counting value CN2is 1, the step S372is executed, in which the driving counter UC of the first driver201drives the data control unit304to return the first returned voltage level B0and the second returned voltage level B1to the control circuit10. Next, the step S400is executed to make the second counting value CN2to be 2. Afterward, the control circuit10executes the step S232for comparing according to the first preset parameter DE0and the second preset parameter DE1of the data detector DE. When the first returned voltage level B0is not equal to the first preset parameter DE0or the second returned voltage level B1is not equal to the second preset parameter DE1, the control circuit10executes the step S20for driving the first driver201to output the enable signal EN to the second driver202and judging if the first counting value CN1is N. When the judgment is false (NO), the control circuit10executes the step S30. When the judgment is true (YES), the control circuit10executes the step S40.

When the first returned voltage level B0is equal to the first preset parameter DE0and the second returned voltage level B1is equal to the second preset parameter DE1, the control circuit10executes the step S242. As shown inFIG.4F, the data detector DE transmits the third voltage level V3and the fourth voltage level V4to the data control unit304of the first driver201. Then the first driver201executes the step S342. Since the second counting value CN2is 2, the first driver201continues to execute the step S352and then to execute the step S400, the second counting value CN2is increased to be 3. As shown inFIG.4F, the driving counter UC of the first driver201drives the data control unit304to transmit the third returned voltage level B2and the fourth returned voltage level B3to the data detector DE of the control circuit10. In the step S252, the data detector DE of the control circuit10compares the third returned voltage level B2and the fourth returned voltage level B3according to the third preset parameter DE2and the fourth preset parameter DE3. When the third returned voltage level B2is not equal to the third preset parameter DE2or the fourth returned voltage level B3is not equal to the fourth preset parameter DE3, the control executes the step S20. The steps S20to S40will not be described again.

When the third returned voltage level B2is equal to the third preset parameter DE2and the fourth returned voltage level B3is equal to the fourth preset parameter DE3, the step S260is executed. Meanwhile, the first driver201continues to execute the step S320. Since the judgment is true, the step S332is executed. The first driver201is set to the input mode. Namely, the first data node D0and the second data node D1of the first driver201are set to the input mode. In addition, the driving counter UC of the first driver201drives the output control unit P to output the enable signal EN to the enable input node ENI of the next driver via the enable output node ENO. For example, as shown inFIG.1B, the enable output node ENO of the first driver201is coupled to the enable input node ENI of the second driver202. Thereby, the first driver201transmits the enable signal EN to the second driver202.

Please refer again toFIG.4E. ENI(201) inFIG.4Erepresents the signal at the enable input node ENI of the first driver201; D0(201) represents the signal at the first data node D0of the first driver201; ENI(202) represents the signal at the enable input node ENI of the second driver202; D0(202) represents the signal at the first data node D0of the second driver202; and D1(202) represents the signal at the second data node D1of the second driver202.

Please refer toFIG.4AandFIG.4Cagain. InFIG.4A, the steps S102˜S152are executed for judging if the step S170should be executed. According to another embodiment, if the judgment in the step S152is true, then the steps S102˜S122will be added. At this time, if the judgment in the step S122is true, then the step S170will be executed. InFIG.4C, the steps S222˜S252are executed for judging if the step S260should be executed. According to another embodiment, if the judgment in the step S252is true, then the steps S222˜S232will be added. At this time, if the judgment in the step S232is true, then the step S260will be executed.

The method for testing the display driving circuit according to the second embodiment of the present application is based on the first embodiment of the present application. The second embodiment provides a testing method using multiple data lines. Thereby, the problem of requiring external testing circuits or testers may be solved. In addition, by using multiple data lines to test concurrently, the testing process may be further simplified.

To sum up, the various embodiments of the present application provide several improved methods for testing display driving circuit. By using the data transmitted between the control circuit and the drivers, built-in self-tests may be performed and the problem of requiring external testing circuits or testers may be solved. Furthermore, the present application provides a testing method using multiple data lines. In addition to solving the problem of requiring external testing circuits or testers, by using multiple data lines to test concurrently, the testing process may be further simplified.

Accordingly, the present application conforms to the legal requirements owing to its novelty, nonobviousness, and utility. However, the foregoing description is only embodiments of the present application, not used to limit the scope and range of the present application. Those equivalent changes or modifications made according to the shape, structure, feature, or spirit described in the claims of the present application are included in the appended claims of the present application.