Patent ID: 12250009

DETAILED DESCRIPTION

In describing the present disclosure, detailed descriptions of publicly-known technologies related to the present disclosure will be omitted so as not to obscure the subject matter of the present disclosure. Various embodiments are described below with reference to the accompanying drawings, in order to describe in detail the present disclosure so that those with ordinary skill in art to which the present disclosure pertains may easily carry out the technical spirit of the present disclosure.

It will be understood that when an element is referred to as being “connected to” or “coupled to” another element, the element may be directly connected to or coupled to the another element, or electrically connected to or coupled to the another element with one or more elements interposed therebetween. In addition, it will also be understood that the terms “comprises,” “comprising,” “includes,” and “including” when used in this specification do not preclude the presence of one or more other elements, but may further include or have the one or more other elements, unless stated otherwise. In the description throughout the specification, some components are described in singular forms, but the present disclosure is not limited thereto, and it will be understood that the components may be formed in plural.

FIG.1is a block diagram illustrating an interface device10A supporting combo-PHY in accordance with an embodiment of the present disclosure.

As illustrated inFIG.1, the interface device10A may include a digital PHY100A and an analog PHY200A.

The digital PHY100A may include a C-PHY logic110A and a D-PHY logic120A, and output received parallel data in a parallel data format modified according to a selected interface protocol. For example, when the digital PHY100A operates in a C-PHY mode, the C-PHY logic110A may be activated, and the digital PHY100A may modify the received parallel data for a C-PHY protocol and output the modified data in the parallel data format. On the other hand, when the digital PHY100A operates in a D-PHY mode, the D-PHY logic120A may be activated, and the digital PHY100A may modify the received parallel data for a D-PHY protocol and output the modified data in the parallel data format.

The analog PHY200A may include a serializing block210A, a multiplexer block220A, a driver control block230A and a driver block240A. The serializing block210A may receive the parallel data from the digital PHY100A, convert the received parallel data in a parallel-to-serial manner, and output the converted data in a serial data format. The multiplexer block220A may transmit the serial data received from the serializing block210A to the driver control block230A through a path selected according to the selected interface protocol. The driver control block230A may generate a control signal for controlling the driver block240A according to the received serial data. The driver block240A may output the serial data according to the control signal received from the driver control block230A.

FIG.2is a block diagram illustrating an interface device10in accordance with an embodiment of the present disclosure.

The interface device10illustrated inFIG.2may include a digital PHY100and an analog PHY200.

The digital PHY100may include a C-PHY logic110, a D-PHY logic120and a test logic130. The C-PHY logic110and the D-PHY logic120may correspond to the C-PHY logic110A and the D-PHY logic120A, respectively, described with reference toFIG.1.

The test logic130may be activated during a test mode operation, convert received parallel data in a parallel data format for a test operation, and output the converted data.

The analog PHY200may include a serializing block210, a multiplexer block220, a driver control block230and a driver block240.

The serializing block210, the multiplexer block220, the driver control block230and the driver block240may correspond to the serializing block210A, the multiplexer block220A, the driver control block230A and the driver block240A, respectively, described with reference toFIG.1.

FIG.3is a diagram for describing a D-PHY mode operation of the interface device10illustrated inFIG.2in accordance with an embodiment of the present disclosure.

Since the C-PHY logic110and the test logic130included in the digital PHY100are deactivated or disabled during the D-PHY mode operation, illustrations thereof are omitted inFIG.3.

The digital PHY100may receive mode information MODE composed of one or more bits, and select one operation mode of the D-PHY mode, the C-PHY mode and the test mode.

During the D-PHY mode operation, the C-PHY logic110and the test logic130may be deactivated according to the mode information MODE.

During the D-PHY mode operation, the D-PHY logic120included in the digital PHY100may be activated according to the mode information MODE, and receive parallel data DATA1<7:0>, DATA2<7:0>, DATA3<7:0> and DATA4<7:0> to be outputted to an external device.

A D-PHY interface protocol may be composed of one clock lane and a maximum of four data lanes.FIG.3illustrates a case in which the D-PHY interface protocol is composed of four data lanes, and the number of data lanes may be less than four according to various embodiments.

The D-PHY logic120may receive the parallel data DATA1<7:0> to DATA4<7:0>. Each of the parallel data DATA1<7:0> to DATA4<7:0> may be 8-bit data to be outputted to one data lane.

The D-PHY logic120may include emphasis circuits (EMPs)121to124that generate emphasis information EMP1to EMP4, respectively, for each data lane. The emphasis circuits121to124may generate the emphasis information EMP1to EMP4, respectively, in parallel for adjusting a driving force of final output signals according to values of the inputted parallel data. For example, the emphasis circuit121may generate the emphasis information EMP1for an emphasis operation on the parallel data DATA1<7:0>, and the emphasis circuit123may generate the emphasis information EMP3for the emphasis operation on the parallel data DATA3<7:0>. Types of the emphasis operation may include a de-emphasis operation and/or a pre-emphasis operation.

The emphasis circuits121to124may be activated/deactivated according to whether to perform the emphasis operation.

During the D-PHY mode operation, the digital PHY100may receive the parallel data DATA1<7:0> to DATA4<7:0> through the respective data lanes, and output the parallel data DATA1<7:0> to DATA4<7:0> and the emphasis information EMP1to EMP4corresponding to the parallel data DATA1<7:0> to DATA4<7:0>, respectively.

The D-PHY logic120may further include a clock pattern generation circuit125for outputting a clock signal. The clock pattern generation circuit125may output clock patterns CLK_PATTERN<7:0> in parallel and emphasis information EMP_CLK for the clock patterns CLK_PATTERN<7:0>.

The analog PHY200may include the serializing block210, the multiplexer block220, the driver control block230and the driver block240.

The analog PHY200may receive the mode information MODE, and select one operation mode of the D-PHY mode, the C-PHY mode and the test mode.

During the D-PHY mode operation, the serializing block210, the multiplexer block220, the driver control block230and the driver block240are configured to output data using a D-PHY protocol according to the mode information MODE.

The serializing block210may include 18 parallel-to-serial conversion circuits SER1<1> to SER9<1> and SER1<0> to SER9<0>. When the D-PHY mode is selected according to the mode information MODE, among the 18 parallel-to-serial conversion circuits SER1<1> to SER9<1> and SER1<0> to SER9<0> of the serializing block210, 10 parallel-to-serial conversion circuits SER1<1>, SER1<0>, SER3<1>, SER3<0>, SER5<1>, SER5<0>, SER7<1>, SER7<0>, SER9<1> and SER9<0> may be activated, and the other 8 parallel-to-serial conversion circuits SER2<1>, SER2<0>, SER4<1>, SER4<0>, SER6<1>, SER6<0>, SER8<1> and SER8<0> may be deactivated.

The activated parallel-to-serial conversion circuits SER1<1>, SER1<0>, SER3<1>, SER3<0>, SER5<1>, SER5<0>, SER7<1>, SER7<0>, SER9<1> and SER9<0> may receive the parallel data DATA1<7:0> to DATA4<7:0>, the clock patterns CLK_PATTERN<7:0> and the emphasis information EMP1to EMP4and EMP_CLK, convert the parallel data DATA1<7:0> to DATA4<7:0>, the clock patterns CLK_PATTERN<7:0> and the emphasis information EMP1to EMP4and EMP_CLK at a ratio of 8:1 in a parallel-to-serial manner. For example, an output S11of the parallel-to-serial conversion circuit SER1<1> may be a result of the parallel-to-serial conversion of the parallel data DATA1<7:0> at the ratio of 8:1, and an output S10of the parallel-to-serial conversion circuit SER1<0> may be a result of the parallel-to-serial conversion of the emphasis information EMP1at the ratio of 8:1.

During the D-PHY mode operation, the multiplexer block220may receive the outputs S11, S10, S31, S30, S51, S50, S71, S70, S91and S90of the serializing block210, and set signal paths so that each of the data lanes and the clock lane are outputted in a differential signal format. The multiplexer block220may invert some of the outputs of the serializing block210by using inverters301to310therein, and transmit the inverted outputs to the driver control block230. For example, a driver control circuit DRVCON1may receive the output S11of the parallel-to-serial conversion circuit SER1<1>, the inverted output S11outputted from the inverter301, and the output S10of the parallel-to-serial conversion circuit SER1<0>. Likewise, a driver control circuit DRVCON4may receive the output S31of the parallel-to-serial conversion circuit SER3<1>, the inverted output S31outputted from the inverter304, and the output S30of the parallel-to-serial conversion circuit SER3<0>.

The driver control block230may include 10 driver control circuits DRVCON1to DRVCON10.

During the D-PHY mode operation, all of the 10 driver control circuits DRVCON1to DRVCON10of the driver control block230may be activated.

The driver control circuits DRVCON1to DRVCON10may each receive a pair of serial data in the differential signal format from the multiplexer block230, and convert the received serial data into a plurality of pull-up signals PU1to PU10and a plurality of pull-down signals PD1to PD10, respectively. In addition, the driver control circuits DRVCON1to DRVCON10may reflect (e.g., add) the emphasis information transmitted from the multiplexer block230into the pull-up signals PU1to PU10and the pull-down signals PD1to PD10so that a driving force of data outputted from the driver block240is adjusted. For example, the driver control circuit DRVCON7may determine a logic level of data outputted from a driver circuit DRIVER7in response to differential data (i.e., the serial data S71outputted from the parallel-to-serial conversion circuit SER7<1> and the inverted serial data S71outputted from the inverter307), determine a driving force of the driver circuit DRIVER7by using emphasis information EMP3outputted from the parallel-to-serial conversion circuit SER7<0>, and generate the pull-up signal PU7and the pull-down signal PD7according to the determination result.

The driver block240may include 10 driver circuits DRIVER1to DRIVER10.

During the D-PHY mode operation, all of the 10 driver circuits DRIVER1to DRIVER10included in the driver block240may be activated.

The driver circuits DRIVER1to DRIVER10may be controlled by respective pull-up and pull-down signals among the pull-up signals PU1to PU10and the pull-down signals PD1to PD10to output data. For example, a logic level of data outputted from the driver circuit DRIVER10and the driving force thereof may be determined according to the pull-up signal PU10and the pull-down signal PD10.

FIG.4is a diagram for describing an operation of the driver block240in the D-PHY mode illustrated inFIG.3in accordance with an embodiment of the present disclosure. The operation of the driver block240is described below using the driver circuits DRIVER1and DRIVER2as an example.

The driver circuit DRIVER1may include a plurality of pull-up switches411to413, a plurality of pull-down switches414to416, and resistance elements417to422. The driver circuit DRIVER2may include a plurality of pull-up switches431to433, a plurality of pull-down switches434to436, and resistance elements437to442. The pull-up switches411to413may be controlled by the pull-up signal PU1, and the pull-down switches414to416may be controlled by the pull-down signal PD1. The pull-up signal PU1and the pull-down signal PD1may have as many bits as the number of pull-up switches411to413and the number of pull-down switches414to416, respectively. That is, on/off of each of the pull-up switches411to413may be independently controlled by the pull-up signal PD1with multiple bits corresponding to the serialized data, and on/off of each of the pull-down switches414to416may be independently controlled by the pull-down signal PD1. Likewise, the pull-up switches431to433may be controlled by the pull-up signal PU2, and the pull-down switches434to436may be controlled by the pull-down signal PD2. Each of the pull-up switches411,412,413,431,432and433and the pull-down switches414,415,416,434,435and436may include a PMOS transistor or an NMOS transistor.

Referring toFIGS.3and4together, the parallel data DATA1<7:0> inputted to the D-PHY logic120in the D-PHY mode may be transmitted to the serializing block210together with the emphasis information EMP1generated from the emphasis circuit121included in the D-PHY logic120. In this case, the emphasis information EMP1may be generated in an 8-bit parallel data format, and include information for adjusting the driving force of the driver when data having the same logic value is continuously outputted.

The parallel-to-serial conversion circuit SER1<1> included in the serializing block210may receive the parallel data DATA1<7:0> transmitted from the D-PHY logic120, convert the parallel data DATA1<7:0> in the parallel-to-serial manner, and output the output (i.e., serial data) S11. The parallel-to-serial conversion circuit SER1<0> may receive the 8-bit emphasis information EMP1from the emphasis circuit121, convert the emphasis information EMP1in the parallel-to-serial manner, and output the converted emphasis information as the output S10having a serial data format.

The multiplexer block220may receive the serial data S11outputted from the parallel-to-serial conversion circuit SER1<1>, and set a data transmission path so that the driver control circuits DRVCON1and DRVCON2included in the driver control block230generate the pull-up signals PU1and PU2and the pull-down signals PD1and PD2for controlling the drivers DRIVER1and DRIVER2to output a pair of differential data. The multiplexer block220may transmit the serial data S11transmitted from the parallel-to-serial conversion circuit SER1<1> to a positive input terminal of the driver control circuit DRVCON1, and transmit data obtained by inverting the serial data S11to a negative input terminal of the driver control circuit DRVCON1. The multiplexer block220may invert the serial data S11transmitted from the parallel-to-serial conversion circuit SER1<1>, transmit the inverted data to a positive input terminal of the driver control circuit DRVCON2, and transmit the serial data S11to a negative input terminal of the driver control circuit DRVCON2. The multiplexer block220may transmit the serial emphasis information S10received from the parallel-to-serial conversion circuit SER1<0> to each of emphasis terminals of the driver control circuits DRVCON1and DRVCON2.

The driver control circuit DRVCON1included in the driver control block230may generate the pull-up signal PU1and the pull-down signal PD1for controlling the driver circuit DRIVER1included in the driver block240, by using the data and information received through the positive input terminal, the negative input terminal and the emphasis terminal. Likewise, the driver control circuit DRVCON2may generate the pull-up signal PU2and the pull-down signal PD2for controlling the driver circuit DRIVER2. As described above, each of the pull-up signals PU1and PU2and pull-down signals PD1and PD2may have multiple bits corresponding to the serialized data.

In the D-PHY mode, data may be outputted in the differential signal format, and the outputted signal may have one of two logic values, i.e., a logic high level (“H”) or a logic low level (“L”). For example, when the data inputted to the positive input terminal of the driver control circuit DRVCON1has the logic high level (“H”) and the data inputted to the negative input terminal of the driver control circuit DRVCON1has a logic low level (“L”), the logic low level data may be inputted to the positive input terminal of the driver control circuit DRVCON2, and the logic high level data may be inputted to the negative input terminal of the driver control circuit DRVCON2.

Each of the pull-up switches411to413and431to433of the driver circuits DRIVER1and DRIVER2may be composed of a PMOS transistor, and each of the pull-down switches414to416and434to436may be composed of an NMOS transistor. In this case, the driver control circuit DRVCON1may output, to the driver circuit DRIVER1, the pull-up signal PU1composed of all low bits (“L”) or a large number of low bits and a small number of high bits according to the emphasis information EMP1, and output the pull-down signal PD1composed of all low bits to the driver circuit DRIVER1. The driver control circuit DRVCON2may output, to the driver circuit DRIVER2, the pull-up signal PU2composed of all high bits (“H”) or a large number of high bits and a small number of low bits according to the emphasis information EMP1, and output the pull-down signal PD2composed of all high bits to the driver circuit DRIVER2. In some cases, each of the pull-up switches411to413and431to433may be composed of an NMOS transistor. In this case, levels of the pull-up signals that control the pull-up switches411to413and431to433may be opposite to levels of the pull-up signals in the case where each of the pull-up switches411to413and431to433is composed of a PMOS transistor.

When the driver circuit DRIVER1receives, from the driver control circuit DRVCON1, the pull-up signal PU1composed of all low bits or a large number of low bits and a small number of high bits and the pull-down signal PD2composed of all low bits, the pull-up switches411to413each composed of the PMOS transistor may be mostly turned on, the pull-down switches414to416each composed of the NMOS transistor may be turned off, and the driver circuit DRIVER1may finally output the logic high level data.

When the driver circuit DRIVER2receives, from the driver control circuit DRVCON2, the pull-up signal PU2composed of all high bits (“H”) or a large number of high bits and a small number of low bits and the pull-down signal PD2composed of all high bits, the pull-up switches431to433each composed of the PMOS transistor may be mostly turned off, the pull-down switches434to436each composed of the NMOS transistor may be turned on, and the driver circuit DRIVER2may finally output the logic low level data.

When outputting data, the driver circuit DRIVER1and the driver circuit DRIVER2may adjust the driving force thereof, by changing the number of switches that are turned on according to the emphasis information EMP1. Reference symbol “TX” inFIG.4refers to the driver circuits' side that transmits data, and reference symbol “RX” refers to the receiving circuits' side that receives the data transmitted from the driver circuits DRIVER1and DRIVER2. The receiving circuits' side may include resistors to terminate the output of the driver circuit DRIVER1and the output of the driver circuit DRIVER2, which are differential signals.

FIG.5is a diagram for describing a C-PHY mode operation of the interface device10illustrated inFIG.2in accordance with an embodiment of the present disclosure.

Since the D-PHY logic120and the test logic130included in the digital PHY100are deactivated or disabled during the C-PHY mode operation, illustrations thereof are omitted inFIG.5.

During the C-PHY mode operation, the D-PHY logic120and the test logic130may be deactivated according to the mode information MODE.

During the C-PHY mode operation, the C-PHY logic110included in the digital PHY100may be activated according to the mode information MODE, and receive parallel data DATA1<15:0>, DATA2<15:0> and DATA3<15:0> to be outputted to an external device.

A C-PHY interface protocol may be composed of a maximum of three data lanes without a separate clock lane, and each of the data lanes may use three lines.FIG.5illustrates a case in which the C-PHY interface protocol is composed of three data lanes, and the number of data lanes may be greater or less than three according to embodiments.

The C-PHY logic110may receive the parallel data DATA1<15:0>, DATA2<15:0> and DATA3<15:0>. Each of the parallel data DATA1<15:0>, DATA2<15:0> and DATA3<15:0> may be 16-bit data to be outputted to one data lane.

The C-PHY logic110may include mappers111to113and encoders114to116. One mapper and one encoder may correspond to each data lane. The mappers111to113may convert the respective parallel data DATA1<15:0>, DATA2<15:0> and DATA3<15:0> into 7 symbols, and transmit the 7 symbols to the respective encoders114to116. Each of the encoders114to116may convert the 7 symbols into a wire state. The wire state may include six states, and determine driving levels of the three lines constituting one data lane according to each of the states. The encoders114to116may divide write state information of each line into pull-up information DATA1A<15:8>, DATA1B<15:8>, DATA1C<15:8>, DATA2A<15:8>, DATA2B<15:8>, DATA2C<15:8>, DATA3A<15:8>, DATA3B<15:8> and DATA3C<15:8> and pull-down information DATA1A<7:0>, DATA1B<7:0>, DATA1C<7:0>, DATA2A<7:0>, DATA2B<7:0>, DATA2C<7:0>, DATA3A<7:0>, DATA3B<7:0> and DATA3C<7:0>, and output the pull-up and pull-down information to the serializing block210.

During the C-PHY mode operation, all 18 parallel-to-serial conversion circuits SER1<1> to SER9<1> and SER1<0> to SER9<0> included in the serializing block210may be activated. The parallel-to-serial conversion circuits SER1<1> to SER9<1> and SER1<0> to SER9<0> may convert and output the wire state information DATA1A<15:8>, DATA1B<15:8>, DATA1C<15:8>, DATA2A<15:8>, DATA2B<15:8>, DATA2C<15:8>, DATA3A<15:8>, DATA3B<15:8>, DATA3C<15:8>, DATA1A<7:0>, DATA1B<7:0>, DATA1C<7:0>, DATA2A<7:0>, DATA2B<7:0>, DATA2C<7:0>, DATA3A<7:0>, DATA3B<7:0> and DATA3C<7:0>, respectively, transmitted from the encoders114to116, in a parallel-to-serial manner. For example, the parallel-to-serial conversion circuit SER1<1> may convert the pull-up information DATA1A<15:8> at a ratio of 8:1 in the parallel-to-serial manner and output the converted information, and the parallel-to-serial conversion circuit SER1<0> may convert the pull-down information DATA1A<7:0> at a ratio of 8:1 in the parallel-to-serial manner and output the converted information.

During the C-PHY mode operation, the multiplexer block220may set signal paths so that outputs S11, S10, S21, S20, S31, S30, S41, S40, S51, S50, S61, S60, S71, S70, S81, S80, S91and S90of the serializing block210are transmitted to the driver control block230as they are. That is, the multiplexer block220may be bypassed during the C-PHY mode operation.

During the C-PHY mode operation, 9 driver control circuits DRVCON1to DRVCON9among the 10 driver control circuits DRVCON1to DRVCON10included in the driver control block230may be activated, and one driver control circuit DRVCON10may be deactivated. Each of the driver control circuits DRVCON1to DRVCON9may receive pull-up information and pull-down information from a pair of corresponding parallel-to-serial conversion circuits, and generate a pull-up signal and a pull-down signal for controlling a corresponding driver circuit. For example, the driver control circuit DRVCON4may receive pull-up information S41and pull-down information S40outputted from the parallel-to-serial conversion circuits SER4<1> and SER4<0>, and generate a pull-up signal PU4and a pull-down signal PD4for controlling a driver circuit DRIVER4.

During the C-PHY mode operation, 9 driver circuits DRIVER1to DRIVER9among the 10 driver circuits DRIVER1to DRIVER10included in the driver block240may be activated, and one driver circuit DRIVER10may be deactivated. The 9 activated driver circuits DRIVER1to DRIVER9may output data according to respective pull-up signals PU1to PU9and respective pull-down signals PD1to PD9received from the respective driver control circuits DRVCON1to DRVCON9.

FIG.6is a diagram for describing an operation of the driver block240in the C-PHY mode illustrated inFIG.5in accordance with an embodiment of the present disclosure.

In the C-PHY interface protocol, the outputs of the driver circuits DRIVER1to DRIVER3may have one of three logic values. Driving levels of three lines constituting one data lane may be determined based on the respective pull-up signals PU1to PU3and the respective pull-down signals PD1to PD3generated from the driver control circuits DRVCON1to DRVCON3according to the wire state outputted from the encoder114. In the example ofFIG.6, the driver circuit DRIVER1may output logic high level (“H”) data, the driver circuit DRIVER2may output middle (“M”) data whose logic level is between logic high level data and logic low level (“L”) data, and the driver circuit DRIVER3may output logic low level data.

Each of the pull-up switches411to413,431to433and451to453of the driver circuits DRIVER1, DRIVER2and DRIVER3may be composed of a PMOS transistor, and each of the pull-down switches414to416,434to436and454to456of the driver circuits DRIVER1, DRIVER2and DRIVER3may be composed of an NMOS transistor. In this case, the pull-up signal PU1composed of all low bits and the pull-down signal PD1composed of all low bits may be inputted to the driver circuit DRIVER1. The pull-up signal PU2composed of one low bit and the other high bits and the pull-down signal PD2composed of one high bit and the other low bits may be inputted to the driver circuit DRIVER2. The pull-up signal PU3composed of all high bits and the pull-down signal PD3composed of all high bits may be inputted to the driver circuit DRIVER3. Accordingly, the pull-up switches411to413may be turned on, and the pull-down switches414to416may be turned off, and therefore, the driver circuit DRIVER1may output the logic high level data. Only one pull-up switch431and one pull-down switch434may be turned on, and the other switches432,433,435and436may be turned off, and therefore, the driver circuit DRIVER2may output the middle data. The pull-down switches454,455and456may be turned on, and the pull-up switches451,452and453may be turned off, and therefore, the driver circuit DRIVER3may output the logic low level data.

Herein, it is described as an example that one pull-up switch431and one pull-down switch434are turned on when the driver circuit DRIVER2outputs the middle data, but the number of pull-up and pull-down switches that are turned on may be different from that in this example. For example, half of the pull-up switches431to433of the driver circuit DRIVER2may be turned on, and half of the pull-down switches434to436of the driver circuit DRIVER2may be turned on, and therefore, the middle data may be outputted from the driver circuit DRIVER2.

FIG.7is a diagram for describing a test mode operation according to the interface device10illustrated inFIG.2in accordance with an embodiment of the present disclosure.

Since the D-PHY logic120and the C-PHY logic110included in the digital PHY100are deactivated or disabled during the test mode operation, illustrations thereof are omitted inFIG.7.

During the test mode operation, the D-PHY logic120and the C-PHY logic110may be deactivated according to the mode information MODE.

During the test mode operation, the test logic130included in the digital PHY100may be activated according to the mode information MODE, and receive parallel data DATA1<7:0>, DATA2<7:0>, DATA3<7:0> and DATA4<7:0> to be outputted to an external device.

During the test mode operation, all circuits included in the analog PHY200may be used to operate to output data through a D-PHY interface protocol.

The test logic130may receive the four parallel data DATA1<7:0> to DATA4<7:0> as in the D-PHY mode operation. Each of the parallel data DATA1<7:0>, DATA2<7:0>, DATA3<7:0> and DATA4<7:0> may be outputted to a corresponding data lane. The test logic130may set signal paths to output each of the parallel data DATA1<7:0>, DATA2<7:0>, DATA3<7:0> and DATA4<7:0> through a pair of driver circuits as a differential signal.

The test logic130may include a clock pattern generation circuit131for outputting a clock signal (i.e., a clock pattern corresponding to parallel data, which serves as a part of a test parallel data pattern). The test logic130may further include inverters132to140for inverting the parallel data and the clock signal. Each of the inverters132to140illustrated in the figure may represent 8 inverters. For example, the inverter133may represent 8 inverters for inverting the 8-bit parallel data DATA1<7:0>.

During the test mode operation, the test logic130may receive the parallel data DATA1<7:0>, transmit the parallel data DATA1<7:0> to parallel-to-serial conversion circuits SER1<1> and SER2<0> without inverting the parallel data DATA1<7:0>, and transmit inverted parallel data to parallel-to-serial conversion circuits SER1<0> and SER2<1>. The parallel data DATA1<7:0> transmitted to the parallel-to-serial conversion circuit SER1<1> may be used to generate output (i.e., serial data) S11to be inputted to a positive input terminal of a driver control circuit DRVCON1, and serial data S10outputted from the parallel-to-serial conversion circuit SER1<0> may be inputted to a negative input terminal of the driver control circuit DRVCON1. Serial data S21outputted from the parallel-to-serial conversion circuit SER2<1> may be inputted to a positive input terminal of a driver control circuit DRVCON2, and serial data S20outputted from the parallel-to-serial conversion circuit SER2<0> may be inputted to a negative input terminal of the driver control circuit DRVCON2.

During the test mode operation, the test logic130may receive the parallel data DATA4<7:0>, transmit the parallel data DATA4<7:0> to a parallel-to-serial conversion circuit SER9<1> without inverting the parallel data DATA4<7:0>, and transmit inverted parallel data to the parallel-to-serial conversion circuit SER9<0>. Since the number of parallel-to-serial conversion circuits SER1<1> to SER9<1> and SER1<0> to SER9<0> included in the serializing block210is 18, one of data and clock lanes may be connected to only two parallel-to-serial conversion circuits.

During the test mode operation, all 18 parallel-to-serial conversion circuits SER1<1> to SER9<1> and SER1<0> to SER9<0> included in the serializing block210may be activated, and the test parallel data pattern received from the test logic130may be converted in a parallel-to-serial manner, and the converted data may be outputted to the multiplexer block220. The test parallel data pattern includes inverted and non-inverted parallel data DATA1<7:0>, DATA2<7:0>, DATA3<7:0> and DATA4<7:0>, and the clock pattern generated from the clock pattern generation circuit131.

During the test mode operation, the multiplexer block220is configured to transmit serial data S11, S10, S21, S20, S31, S30, S41, S40, S51, S50, S61, S60, S71, S70, S81, S80, S91and S90outputted from the parallel-to-serial conversion circuits SER1<1> to SER9<1> and SER1<0> to SER9<0> to the driver control block230. In this case, the serial data S91outputted from the parallel-to-serial conversion circuit SER9<1> and the serial data S90outputted from the parallel-to-serial conversion circuit SER9<0> may be simultaneously transmitted to driver control circuits DRVCON9and DRVCON10, respectively. Since the number of parallel-to-serial conversion circuits SER1<1> to SER9<1> and SER1<0> to SER9<0> is 18, and the number of driver control circuits DRVCON1to DRVCON10is 10, a pair of parallel-to-serial circuits SER9<0> and SER9<1> may transmit the serial data S91and S90to the two driver control circuits DRVCON9and DRVCON10, respectively.

During the test mode operation, all 10 driver control circuits DRVCON1to DRVCON10included in the driver control block230may be activated. The driver control circuits DRVCON1to DRVCON10may generate respective pull-up signals PU1to PU10and respective pull-down signals PD1to PD10according to the serial data inputted to respective positive input terminals and respective negative input terminals thereof, and output the generated pull-up and pull-down signals to the driver block240.

During the test mode operation, all parallel-to-serial conversion circuits SER1<1> to SER9<1> and SER1<0> to SER9<0> of the serializing block210may operate, all driver control circuits DRVCON1to DRVCON10of the driver control block230may operate, and all driver circuits DRIVER1to DRIVER10of the driver block240may operate. That is, all circuits and data paths of the analog PHY200may operate and be tested. Accordingly, it may be possible to verify the operations of all circuits and data paths included in the analog PHY200during the test mode operation.

FIG.8is a diagram illustrating the test mode operation illustrated inFIG.7in accordance with an embodiment of the present disclosure.

FIG.8illustrates an example in which the clock lane and the parallel data DATA3<7:0> may be tested by changing locations thereof during the test mode operation.

In order to generate an 8-bit parallel signal in which a low bit or a high bit are repeated, in the clock pattern generation circuit131, the high bit or the low bit may be fixed and connected according to bit locations. When fixed levels are the same as levels that are fixedly outputted from the clock pattern generation circuit131even though defects in which some of inputs of parallel-to-serial conversion circuits that receive outputs of the clock pattern generation circuit131are fixed to the high bit or the low bit occur, the defects may not be detected during the test mode operation.

The defects may be detected during the test mode operation, by repeatedly performing test operations while changing the location of the clock lane with one of data lanes.

According to embodiments of the present disclosure, it is possible to provide a test mode circuit that allows an interface device supporting two or more different interface protocols to test, by using one interface protocol, signal paths and circuits used by other interface protocols, which makes it possible to test the signal paths and circuits used by other interface protocols at once only with test equipment supporting one interface protocol.

While the present disclosure has been illustrated and described with respect to specific embodiments, the disclosed embodiments are provided for the description, and not intended to be restrictive. Further, it is noted that the present disclosure may be achieved in various ways through substitution, change, and modification that fall within the scope of the following claims, as those skilled in the art will recognize in light of the present disclosure. Therefore, the scope of the present disclosure encompasses all variations that fall within the scope of the claims including their equivalents. Furthermore, the embodiments may be combined to form additional embodiments.