Patent ID: 12222596

DESCRIPTION OF EMBODIMENTS

In order to make objectives, technical solutions and advantages of the present disclosure more apparent, the present disclosure will be described in further detail with reference to the accompanying drawings. All embodiments, which can be obtained by a person skilled in the art without making any creative effort based on embodiments described in the present disclosure, belong to a protection scope of the present disclosure.

Shapes and sizes of components in the drawings are not to scale, but are merely intended to facilitate an understanding of contents of the embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which the present disclosure belongs. The use of “first”, “second”, and the like in the present disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms “a”, “an”, or “the” and similar referents do not denote a limitation of quantity, but rather denote a presence of at least one. The word “include” or “comprise”, and the like, means that the element or item preceding the word contains the element or item listed after the word and its equivalent, but does not exclude other elements or items. The terms “connected” or “coupled” and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms “upper”, “on”, “under”, “below” and the like are used only to indicate relative positional relationships, and when an absolute position of an object being described is changed, the relative positional relationships may be changed accordingly.

The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of configurations formed based on a manufacturing process. Thus, areas illustrated in the figures have schematic properties, and shapes of the areas shown in the figures illustrate specific shapes of the areas of elements, but are not intended to be limiting.

As shown inFIG.1,FIG.1illustrates a top view of an example of a display substrate according to an embodiment of the present disclosure, the display substrate having a display area Q1, and a bonding area Q2on at least one side of the display area Q1. The display area Q1has a plurality of sub-pixels100arranged in an array therein, and the bonding area Q2has a plurality of bonding pads3therein, and the bonding pads3are configured to receive signals transmitted by an external driving integrated circuit and transmit the signals to the sub-pixels100in the display area. The display substrate further includes a plurality of gate lines2extending in a first direction, and a plurality of data lines5extending in a second direction, the gate lines2crossing the data lines5to define areas of the sub-pixels100. In the following embodiment, a case where the first direction is a row direction of the sub-pixels100arranged in the array and the second direction is a column direction of the sub-pixels100arranged in the array is taken as an example.

It should be noted that the display substrate may further include a frame sealing area Q3, the frame sealing area Q3is disposed around the display area Q1, the bonding area Q2is disposed on at least one side of the frame sealing area Q3away from the display area Q1, and the frame sealing area Q3is configured for disposing frame sealing glue to seal the display substrate and a color filter substrate when they are aligned and combined. In addition, the frame sealing area Q3may be further provided with a driving integrated circuit, such as a Gate On Array (GOA). The GOA may be disposed at any end of each gate line2, and the gate line2is coupled to the GOA at the end thereof to receive a scanning signal transmitted by the GOA. The display substrate may be provided with the GOA on a single side, that is, the GOA is provided at only one end of the gate line2, or may be provide with GOAs on both sides, that is, the GOAs are provided at both ends of the gate line2, which is not limited herein. In the embodiment of the present disclosure, the display substrate is described by taking a case where the GOAs are disposed on both sides.

Note that, the bonding area Q2of the display substrate may be located at different positions according to different locations of the driving integrated circuit, and for example, if the gate line2is driven by a gate driving integrated circuit (G-IC), and a data line5is driven by a source driving integrated circuit (S-IC), two sides of the display substrate opposite to two ends of the gate line2and one side of the display substrate opposite to any one end of the data line5may be taken as the bonding area Q2. If the gate line2is driven by the GOA, only one side of the display substrate opposite to any one end of the data line5is taken as the bonding area Q2. In the following, a case where the display substrate has one bonding area Q2, and the bonding area Q2is disposed on an upper side of the display substrate is taken as an example, but the embodiment of the present disclosure is not limited thereto.

In a first aspect, referring toFIG.1andFIG.2,FIG.2is an example of cross-sectional view of a display substrate provided in the embodiment, the display substrate provided in the embodiment of the present disclosure includes a base1, and a first conductive layer on the base1, where the first conductive layer is located in the display area Q1, the first conductive layer includes a plurality of gate lines2, and the plurality of gate lines2are coupled to GOAs on two sides thereof. The display substrate further includes a light shielding layer4arranged on a side of the first conductive layer proximal to the base1, since the gate lines2reflect external light when the external light is irradiated thereon, a phenomenon in which a display side of a display device including the display substrate reflect light occurs, consequently, the light shielding layer4arranged on a side of the gate lines2proximal to the base1can avoid the phenomenon of reflection caused by the gate lines2, that is to say, an orthographic projection of the light shielding layer4on the base1covers at least orthographic projections of the gate lines2on the base1.

Further, with continued reference toFIG.1andFIG.2, the display substrate further includes a plurality of bonding pads3, the plurality of bonding pads3are disposed on the base1at intervals, and the plurality of bonding pads3are located in the bonding area Q2, the bonding area Q2includes a plurality of sub-areas Q21disposed side by side, each sub-area Q21corresponds to one connector, that is, the plurality of bonding pads3are divided into a plurality of groups, each sub-area Q21is provided therein with one group of bonding pads3, the bonding pads3are exposed electrodes, first ends of the bonding pads3in each group are coupled to and packaged with pins of one connector, second ends of the bonding pads3in each group are coupled to data lines5or the GOA in the display area Q1, and an external integrated driving circuit (e.g., a source driving circuit) is coupled to the pins of the connector, and transmits signals to the bonding pads3through the connector. The connector may be any of various types of connectors, such as a Chip On Flex (COF) connector or a Chip On Glass (COG) connector, and each group of bonding pads3are pressed against the connector by using anisotropic conductive film (ACF) adhesive and are electrically coupled with the connector through conductive gold balls in the ACF adhesive. Taking an exemplary of the display substrate as an example, the bonding pads3are usually disposed in the same layer and made of the same material as the gate lines2, that is, the bonding pads3are disposed in the first conductive layer and made of the same film as the gate lines2, and thus usually, the light shielding layer4is formed on the base1, the first conductive layer is formed on the side of the light shielding layer4away from the base1, and then the first conductive layer is patterned to form the gate lines2and the bonding pads3, so that the light shielding layer4is also disposed below the bonding pads3. In the process of manufacturing the display substrate, pressing qualities of the bonding pads3need to be detected, specifically, a camera takes an image of the bonding pads3from a side of the base1away from the bonding pads3to observe the number of particles pressed by the ACF adhesive, but the bonding pads3cannot be observed due to the light shielding layer4arranged between the bonding pads3and the base1. In order to solve the above problem, in the display substrate provided in the present disclosure, orthogonal projections of at least a portion of the bonding pads3on the base1are not overlapped with an orthogonal projection of the light shielding layer4on the base1. Therefore, if the orthographic projections of all the bonding pads3on the base1are not overlapped with the orthographic projection of the light shielding layer4on the base1, that is, the light shielding layer4is not arranged under the bonding pads3(as shown inFIG.2), the camera can observe the pressing quality of each bonding pad3from the side of the base1away from the bonding pads3; if the orthographic projections of a portion of the bonding pads3on the base1are not overlapped with the orthographic projection of the light shielding layer4on the base1, that is, the light shielding layer4is not arranged under the portion of the bonding pads3, the camera can observe the pressing qualities of the bonding pads3without the light shielding layer4therebelow from the side of the base1away from the bonding pads3, and a difference between the pressing qualities of the bonding pads3is relatively small because the bonding pads3are pressed by a same process, so that the pressing qualities of all the bonding pads3can be determined according to the pressing qualities of the portion of the bonding pads3.

In some examples, taking observing the pressing qualities of all the bonding pads3as an example, referring toFIGS.1to6, the orthographic projections of all the bonding pads3on the base1are not overlapped with the orthographic projection of the light shielding layer4on the base1. Specifically, the bonding pads3are disposed in the first conductive layer, that is, the bonding pads3and the gate lines2are disposed in a same layer and have a same material, but the light shielding layer4is further disposed between the gate lines2and the base1, but the bonding pads3are directly formed on the base1. Referring toFIG.3,FIG.3is a cross-sectional view taken along a line A-B inFIG.1at the gate lines2in the display area Q1, and the light shielding layer4is disposed between the gate lines2and the base1to prevent the gate lines2from reflecting light. Referring toFIG.4,FIG.4is a cross-sectional view taken along a line C-D at the bonding pads3in the bonding area Q2, the light shielding layer4is not disposed between the bonding pads3and the base1, the bonding pads3are made of the same material as the gate lines2, and are directly formed on the base1. Therefore, the pressing quality of each bonding pad3can be observed directly from the side of the base1away from the bonding pads3.

In some examples, referring toFIGS.1to6, the display substrate further includes a gate insulating layer01disposed on a side of the first conductive layer (the layer where the bonding pads3and the gate lines2are located) away from the base1; an active layer04is arranged on a side of the gate insulating layer01away from the base1; a source electrode05and a drain electrode06are arranged on a side of the active layer04away from the base1, the source electrode05and the drain electrode06are arranged in a same layer and are made of a same material, a gate electrode, the gate insulating layer01, the active layer04, the source electrode05and the drain electrode06form a thin film transistor, each film layer of the thin film transistor is only arranged in the display area Q1, it needs to be noted that, the gate electrode of the thin film transistor and the gate lines2are formed in a same film layer, the gate line2is coupled to the gate electrode, and a reference sign2inFIG.2indicates a position of the gate electrode; in the display substrate, each sub-pixel100has a thin film transistor, one gate line2is coupled to thin film transistors of the sub-pixels100in a same row, and one data line5is coupled to thin film transistors of the sub-pixels100in a same column; a planarization layer03is arranged on a side of the source electrode05and the drain electrode06away from the base1, the planarization layer03may be an organic film (ORG film), and the planarization layer03flattens a top layer of the thin film transistors for facilitating to form a subsequent film layer; a pixel electrode07is arranged on a side of the planarization layer03away from the base1, and the pixel electrode07is coupled to the drain electrode06through a via hole in the planarization layer03; a protective layer02is arranged on a side of the pixel electrode07away from the base1for protecting each film layer of the thin film transistors.

In some examples, referring toFIG.2, a common electrode002is arranged on a side of the protective layer02of the display substrate away from the base1, and is located in the display area Q1, the common electrode002is disposed opposite to the pixel electrode07, an orthogonal projection of the common electrode002on the base1and an orthogonal projection of the pixel electrode07on the base1have an overlapping area, the common electrode002receives a common voltage, the pixel electrode07receives a data voltage provided by the data line5, thereby an electric field is generated between the common electrode002and the data line5, and if the display substrate and the color filter substrate are aligned and combined to form a display device, and liquid crystal is poured between the display substrate and the color filter substrate, the electric field between the common electrode002and the data line5can change deflection angles of liquid crystal molecules in the liquid crystal, accordingly, a transmittance of light can be changed, and thus, the display device can emit light of a desired gray scale by controlling a voltage difference between the common electrode002and the pixel electrode07.

In some examples, referring toFIGS.2and8,FIG.8is a top view illustrating a part of the common electrode002covering the sub-pixels100arranged in 3×3 array, the common electrode002and an auxiliary electrode001are both disposed in the display area Q1, the common electrode002is a planar electrode, the common electrode002has a plurality of slits021, and an electric field can be formed between the pixel electrode07and the common electrode002through the slits021. In order to increase aperture ratios of the sub-pixels100and brightness of the sub-pixels100, pixel openings P may be disposed in areas of the common electrode002corresponding to the sub-pixels100, so as to expose the thin film transistors of the sub-pixels100, that is, orthographic projections of the pixel openings P on the base1coincide with orthographic projections of the thin film transistors (especially, gate electrodes) on the base1. The common electrode002and the pixel electrode07each may be made of indium tin oxide (ITO) to increase a light transmittance of the sub-pixels100, but the ITO has a relatively large resistivity, which may cause a difference in magnitude of common voltage on the common electrode002at the sub-pixels100of the display substrate, therefore, in order to reduce a resistance of the common electrode002, the auxiliary electrode001may be disposed on a side of the common electrode002proximal to the base1, the auxiliary electrode001and the common electrode002are stacked, as shown inFIG.7,FIG.7is a top view of a part of the auxiliary electrode001covering the sub-pixels100arranged in 3×3 array, the auxiliary electrode001is disposed around the pixel openings P of the corresponding common electrode002, and the auxiliary electrode001covers the gate lines2and the data lines5, so as to reduce resistances of the gate lines2and the data lines5, and reduce signal loss.

In some examples, referring toFIG.2, the auxiliary electrode001is only disposed under a partial area of the common electrode002, and the common electrode002wraps the auxiliary electrode001, that is, the common electrode002covers a top surface and side surfaces of the auxiliary electrode001, so that during manufacturing the display substrate, a film layer of the auxiliary electrode001is formed on the side of the protective layer02away from the base1, the auxiliary electrode001is formed by patterning the film layer, and a film layer of the common electrode002is formed, then the common electrode002is formed by patterning the film layer, the patterning including exposure, development and etching processes, since a developing solution for developing the common electrode002is corrosive to the auxiliary electrode001, in order to prevent the developing solution from affecting the auxiliary electrode001during developing the common electrode002, the common electrode002may wrap the auxiliary electrode001.

In some examples, referring toFIG.1toFIG.6, the display substrate provided in the embodiment of the present disclosure further includes a plurality of first marks6disposed in the frame sealing area Q3, and the plurality of first marks6are disposed in the frame sealing area Q3, for example, may be disposed at four corners of the frame sealing area Q3, so that when the display substrate and the color filter substrate are aligned and combined, alignment can be performed through the first marks6. Similarly, taking an exemplary of the display substrate as an example, the first marks6are usually disposed in the same layer and made of the same material as the gate lines2, that is, the first marks6are disposed in the first conductive layer and made of the same film as the gate lines2, so that the light shielding layer4is usually formed on the base1, the first conductive layer is formed on the side of the light shielding layer4away from the base1, and then the first conductive layer is patterned to form the gate lines2, the first marks6, and the bonding pads3, so that the light shielding layer4is also disposed below the first marks6. In the process of manufacturing the display substrate, the first marks6need to be identified from the side of the base1away from the first marks6, but the light shielding layer4is arranged between the first marks6and the base1, so that the first marks6cannot be identified. In order to solve the above problem, in the display substrate provided in the present disclosure, orthographic projections of the first marks6on the base1are not overlapped with the orthographic projection of the light shielding layer4on the base1(as shown inFIG.2), so that a camera can identify each of the first marks6from the side of the base1away from the first marks6.

In some examples, taking a case where all the first marks6can be identified as an example, referring toFIGS.1to6,FIG.5is a cross-sectional view taken along a line E-F inFIG.1at the first marks6in the frame sealing area Q3, and the orthographic projections of all the first marks6on the base1are not overlapped with the orthographic projection of the light shielding layer4on the base1. Specifically, the first marks6are arranged in the first conductive layer, that is, the first marks6and the gate lines2are arranged in a same layer and have a same material, but the light shielding layer4is further arranged between the gate lines2and the base1, the first marks6are directly formed on the base1, so that each first mark6can be directly and accurately identified from the side of the base1away from the first marks6.

In some examples, referring toFIG.1, the display substrate provided in the embodiment further includes a plurality of second marks7, each sub-area Q21is provided therein with one group of bonding pads3, each group of bonding pads3are coupled to one connector, each group of bonding pads3are coupled to two second marks7, and specifically, the second marks7are respectively coupled to outer sides of two outermost bonding pads in each group of bonding pads3, so as to determine a pressing bonding state of the conductive gold balls in the ACF adhesive after the connector is bonded to the bonding pads3. The structure of the second marks7is the same as that of the first marks6, and orthographic projections of the second marks7on the base1is also not overlapped with the orthographic projection of the light shielding layer4on the base1, so that each second mark7can be accurately identified directly from the side of the base1away from the second mark7. Specifically, the second marks7are disposed in the first conductive layer, that is, the second marks7are disposed in the same layer and are made of the same material as the gate lines2, but the light shielding layer4is further disposed between the gate lines2and the base1, and the second marks7are directly formed on the base1.

In some examples, referring toFIG.1andFIG.2, the display substrate provided in the embodiment further includes a plurality of fan-out wires8, the plurality of fan-out wires8are disposed on the base1at intervals, each fan-out wire8is correspondingly coupled to one bonding pad3, one end of the fan-out wire8is coupled to one bonding pad3(as shown inFIG.2), and the other end of the fan-out wire8extends from the bonding area Q2to the display area Q1and is coupled to the GOA or the data line5in the display area Q1. The film layer structure of the fan-out lines8is the same as that of the gate lines2, that is, the orthographic projection of the light shielding layer4on base1covers orthographic projections of the fan-out wires8on base1. Specifically, the fan-out wires8and the gate lines2are arranged in a same layer and are made of a same material, and the light shielding layer4is further arranged between the fan-out wires8and the base1.

In summary, in the display substrate provided in the embodiment of the present disclosure, the film structure of the marks such as the first marks6and the second marks7is the same as that of the bonding pads3, and orthographic projections of the first marks6and the second marks7on the base1are not overlapped with the orthographic projection of the light shielding layer4on the base1; the film layer structure of the fan-out wires8is the same as that of the gate lines2, and the orthographic projections of the fan-out wires8on the base1are overlapped with the orthographic projection of the light shielding layer4on the base1. The first marks6may include any mark disposed in the frame sealing area Q3, for example, the first marks6may be at least one of a cutting mark, a grinding mark, a process mark, an overlapping mark, and a total pitch mark.

In some examples, a shape of each of the marks such as the first marks6or the second marks7may be any of various shapes, such as a cross shape, a T shape, a rectangle shape, a circle shape, a triangle shape, and the like, and in the embodiment of the present disclosure, a case where the shape of the first mark6is cross, and the shape of the second mark7is a T shape is taken as an example, but the present disclosure is not limited thereto.

In some examples, in the display substrate provided in the embodiment of the present disclosure, the light shielding layer4may be made of any of various materials, for example, the light shielding layer4may be made of molybdenum oxide, the molybdenum oxide is black, and can effectively absorb light irradiated onto the gate lines2. Certainly, the light shielding layer4may be made of other materials, which is not limited herein.

In some examples, the pressing qualities of a portion of the bonding pads3are observed, and as shown inFIGS.9and10,FIG.9is an exemplary distribution diagram of the bonding pads to which one connector is coupled, andFIG.10is a cross-sectional view taken along a line K-L inFIG.9. In the display substrate provided in the embodiment, the bonding pads3in the bonding area Q2include functional bonding pads31and redundant bonding pads (dummy leads)32, the functional bonding pads31and the redundant bonding pads32are both disposed on the base1, usually, external signals are input only to the functional bonding pads31, that is, pins of the connector are coupled only to the functional bonding pads31, and the functional bonding pads31are further coupled to the data lines5or GOA in the display area Q1, or coupled through the fan-out wires8, and the redundant bonding pads32are dummy electrodes and are not coupled to the pins of the connector, and do not receive any electrical signal. Since the signals received by the functional bonding pads31include positive and negative signals (e.g., positive and negative data voltages input to the data lines5), in order to ensure that no crosstalk occurs in the signals between the functional bonding pads31receiving the positive and negative signals, at least one dummy redundant bonding pad32is provided between the functional bonding pad31receiving the positive signal and the functional bonding pad31receiving the negative signal for separating the functional bonding pad31receiving the positive signal from the functional bonding pad31receiving the negative signal, and the redundant bonding pad32itself does not receive any electrical signal, so that the redundant bonding pads32may be formed in a different film layer from the functional bonding pads31to have a different layer structure. Specifically, referring toFIG.10, orthographic projections of the redundant bonding pads32on the base1are not overlapped with the orthographic projection of the light shielding layer4on the base1, and orthographic projections of the functional bonding pads31on the base1at least partially overlaps with the orthographic projection of the light shielding layer4on the base1, that is, the light shielding layer4is disposed only under the functional bonding pads31in the bonding area Q2, and the light shielding layer4is not disposed under the redundant bonding pads32. It should be noted that, the light shielding layer4is disposed on the side of the functional bonding pads31proximal to the base1, and the pattern of the light shielding layer4may be consistent with the patterns of the functional bonding pads32, that is, the orthographic projections of the functional bonding pads31on the base1may completely overlap with the orthographic projection of the light shielding layer4on the base1. Therefore, the pressing quality of each redundant bonding pad32can be observed from the side of the base1away from the bonding pads3, and the entire pressing qualities of the functional bonding pads31and redundant bonding pads32can be determined by observing the pressing qualities of the redundant bonding pads32.

In some examples, since the redundant bonding pads32do not receive any electrical signal, and thus it is not necessary to consider wiring thereof, the redundant bonding pads32may be formed by using any conductive film layer in the display substrate. Taking the exemplary of the display substrate shown inFIG.11as an example,FIG.11is a cross-sectional view of the display substrate corresponding to the embodiment ofFIG.9, and first, film structures of the display substrate will be described. The display substrate includes a base1, a light shielding layer4arranged on the base1, and a first conductive layer arranged on a side of the light shielding layer4away from the base1, a part of the first conductive layer located in the display area Q1includes a plurality of gate lines2, a part of the first conductive layer located in the bonding area Q1includes a plurality of function bonding pads31, an orthographic projection the light shielding layer4on base1covers orthographic projections of the gate lines2and the function bonding pads31on base1, the light shielding layer4is arranged on a side of the gate lines2proximal to the base1, and can prevent the gate lines2from reflecting light. The display substrate further includes a gate insulating layer01arranged on a side of the first conductive layer (the layer where the functional bonding pads31and the gate lines2are located) away from the base1; an active layer04is arranged on a side of the gate insulating layer01away from the base1; a source electrode05and a drain electrode06are arranged on a side of the active layer04away from the base1, the source electrode05and the drain electrode06are arranged in a same layer and are made of a same material, a gate electrode, the gate insulating layer01, the active layer04, the source electrode05and the drain electrode06form a thin film transistor, each film layer of the thin film transistor is only arranged in the display area Q1, it needs to be noted that the gate electrode of the thin film transistor and the gate lines2are formed in a same film layer, the gate line2is coupled to the gate electrode, and the reference sign2inFIG.2indicates a position of the gate electrode; in the display substrate, each sub-pixel100has a thin film transistor, one gate line2is coupled to thin film transistors of the sub-pixels100in a same row, and one data line5is coupled to thin film transistors of the sub-pixels100in a same column; a planarization layer03is arranged on a side of the source electrode05and the drain electrode06away from the base1, the planarization layer03may be an organic film (ORG film), and the planarization layer03flattens a top layer of the thin film transistors for facilitating to form a subsequent film layer; a pixel electrode07is arranged on a side of the planarization layer03away from the base1, and the pixel electrode07is coupled to the drain electrode06through a via hole in the planarization layer03; a protective layer02is arranged on a side of the pixel electrode07away from the base1for protecting each film layer of the thin film transistors.

In some examples, referring toFIG.2, a common electrode002is arranged on a side of the protective layer02of the display substrate away from the base1, and is located in the display area Q1, the common electrode002is disposed opposite to the pixel electrode07, an orthogonal projection of the common electrode002on the base1and an orthogonal projection of the pixel electrode07on the base1have an overlapping area, the common electrode002receives a common voltage, the pixel electrode07receives a data voltage provided by the data line5, thereby an electric field is generated between the common electrode002and the data line5, and if the display substrate and the color filter substrate are aligned and combined to form a display device, and liquid crystal is poured between the display substrate and the color filter substrate, the electric field between the common electrode002and the data line5can change deflection angles of liquid crystal molecules in the liquid crystal, accordingly, a transmittance of light can be changed, and thus, the display device can emit light of a desired gray scale by controlling a voltage difference between the common electrode002and the pixel electrode07.

In some examples, referring toFIGS.2and8,FIG.8is a top view of a portion of the common electrode002covering the sub-pixels100arranged in 3×3 array, the common electrode002and an auxiliary electrode001are both disposed in the display area Q1, the common electrode002is a planar electrode, the common electrode002has a plurality of slits021, and an electric field can be formed between the pixel electrode07and the common electrode002through the slits021. In order to increase aperture ratios of the sub-pixels100and brightness of the sub-pixels100, pixel openings P may be disposed in areas of the common electrode002corresponding to the sub-pixels100, so as to expose the thin film transistors of the sub-pixels100, that is, orthographic projections of the pixel openings P on the base1coincide with orthographic projections of the thin film transistors (especially, gate electrodes) on the base1. The common electrode002and the pixel electrode07may be made of indium tin oxide (ITO) to increase a light transmittance of the sub-pixels100, but the ITO has a relatively large resistivity, which may cause a difference in magnitude of common voltage on the common electrode002at the sub-pixels100of the display substrate, therefore, in order to reduce a resistance of the common electrode002, the auxiliary electrode001may be disposed at a side of the common electrode002proximal to the base1, the auxiliary electrode001and the common electrode002are disposed at the side of the first conductive layer away from the base1, and the auxiliary electrode001is electrically coupled to the common electrode002, so that a cross section of the common electrode002is increased, a resistance thereof is reduced accordingly, as shown inFIG.7, the auxiliary electrode001and the common electrode002are sequentially disposed along a direction away from the base1,FIG.7is a top view of a portion of the auxiliary electrode001covering the sub-pixels100arranged in 3×3 array, the auxiliary electrode001is disposed around the pixel openings P in the corresponding common electrode002, and the auxiliary electrode001covers the gate lines2and the data lines5to reduce resistances of the gate lines2and the data lines5and reduce signal loss.

In some examples, referring toFIG.2, the auxiliary electrode001is only disposed under a partial area of the common electrode002, and the common electrode002wraps the auxiliary electrode001, that is, the common electrode002covers a top surface and side surfaces of the auxiliary electrode001, so that during manufacturing the display substrate, a film layer of the auxiliary electrode001is formed on the side of the protective layer02away from the base1, the auxiliary electrode001is formed by patterning the film layer, a film layer of the common electrode002is formed, and then the common electrode002is formed by patterning the film layer, the patterning including exposure, development and etching processes, and since a developing solution for developing the common electrode002is corrosive to the auxiliary electrode001, in order to prevent the developing solution from affecting the auxiliary electrode001during developing the common electrode002, the common electrode002may wrap the auxiliary electrode001.

In some examples, with continued reference toFIG.11, redundant bonding pads32may be prepared using an electrode layer in the same layer as the auxiliary electrodes001, and an electrode layer in the same layer as the common electrode002. Note that, inFIG.11, for convenience of illustrating positional relationships of film layers where the functional bonding pads31and the redundant bonding pads32are located, the functional bonding pads31and the redundant bonding pads32are illustrated in a same cross-sectional view, but if one functional bonding pad31is cut, the redundant bonding pad32is not shown above the functional bonding pad31, and if one redundant bonding pad32is cut, the functional bonding pad31is not shown below the redundant bonding pad32, and the light shielding layer4is not shown. Specifically, each redundant bonding pad32includes a first conductive part321and a second conductive part322disposed on a side of the first conductive layer away from the base1, where the first conductive part321is electrically coupled to the second conductive part322, the first conductive part321located in the bonding area Q2and the common electrode002located in the display area Q1are disposed in a same layer and made of a same material, that is, the first conductive part321and the common electrode002are prepared by using a same film process; correspondingly, the second conductive part322located in the bonding area Q2and the auxiliary electrode001located in the display area Q1are arranged in a same layer and are made of a same material, that is, the second conductive part322and the auxiliary electrode001are prepared by a same film layer process, and the light shielding layer4is not arranged below the first conductive part321and the second conductive part322of the redundant bonding pad32, so that the pressing qualities of the redundant bonding pads32can be observed from the side of the base1away from the redundant bonding pads32(also away from the functional bonding pads31), and the entire pressing qualities of the bonding pads3(including the functional bonding pads31and the redundant bonding pads32) are determined. Certainly, the redundant bonding pads32may be made of other conductive film layers, which is not limited herein.

In some examples, continuing to refer toFIG.11, since the functional bonding pads31are to be coupled to the data lines5or signal lines of the data lines, the gate lines2or signal lines of the gate lines in the display area Q1, it needs to be manufactured by using a film layer below the pixel electrode07, and specifically, the functional bonding pads31may be disposed in the first conductive layer, that is, the functional bonding pads31are disposed in the same layer and made of the same material as the gate lines2(and also the gate electrodes), and the light shielding layer4is disposed below the functional bonding pads31. Certainly, the functional bonding pads31may be made of other conductive film layers, which is not limited herein.

In some examples, with continued reference toFIG.11, as described above, the display substrate in the embodiment of the present disclosure further includes a plurality of first marks6arranged in the frame sealing area Q3, and in order to solve the problem that the first marks6cannot be identified from the side of the base1away from the first marks6due to the light shielding layer4being provided between the first marks6and the base1, in the display substrate provided in the present disclosure, orthographic projections of the first marks6on the base1are not overlapped with the orthographic projection of the light shielding layer4on the base1(as shown inFIG.2), specifically, in addition to that the first marks6are disposed in the first conductive layer, the first marks6may be prepared by using other conductive film layers, for example, the first mark6include a third conductive part62and a fourth conductive part61disposed on the side of the first conductive layer away from the base1, and the third conductive part62and the fourth conductive part61are electrically coupled, the third conductive part62and the common electrode002are disposed in a same layer and made of a same material, that is, the third conductive part62and the common electrode002are prepared by a same film process, and the fourth conductive part61and the auxiliary electrode001are disposed in a same layer and made of a same material, that is, the fourth conductive part61and the auxiliary electrode001are prepared by a same film process. The light shielding layer4is not arranged under the third conductive part62and the fourth conductive part61of the first mark6, so that each first mark6can be accurately identified directly from the side of the base1away from the first marks6.

In some examples, referring toFIG.1, the display substrate provided in the embodiment further includes a plurality of second marks7, each sub-area Q21is provided therein with one group of bonding pads3, each group of bonding pads3are coupled to one connector, each group of bonding pads3are coupled to two second marks7, and specifically, the second marks7are respectively coupled to outer sides of two outermost bonding pads3(functional bonding pads31or redundant bonding pads32) in each group of bonding pads3, so as to determine a pressing bonding state of the conductive gold balls in the ACF adhesive after the connector is bonded to the bonding pads3. The structure of the second marks7is the same as that of the first marks6, and orthographic projections of the second marks7on the base1are not overlapped with the orthographic projection of the light shielding layer4on the base1, so that each second mark7can be accurately identified directly from the side of the base1away from the second marks7. Specifically, the second mark7include a fifth conductive part and a sixth conductive part which are stacked, the fifth conductive part and the common electrode002are disposed in a same layer and are made of a same material, that is, the fifth conductive part and the common electrode002are prepared by a same film process, and the sixth conductive part and the auxiliary electrode001are disposed in a same layer and are made of a same material, that is, the sixth conductive part and the auxiliary electrode001are prepared by a same film process.

In some examples, referring toFIG.1andFIG.11, the display substrate provided in the embodiment further includes a plurality of fan-out wires8, the plurality of fan-out wires8are disposed on the base1at intervals, each fan-out wire8is correspondingly coupled to one functional bonding pad31, one end of the fan-out wire8is coupled to one functional bonding pad31(as shown inFIG.11), and the other end of the fan-out wire8extends from the bonding area Q2to the display area Q1and is coupled to the GOA or the data line5in the display area Q1. The film layer structure of fan-out lines8is the same as that of the gate lines2, that is, the orthographic projection of the light shielding layer4on base1covers orthographic projections of the fan-out wires8on base1. Specifically, the fan-out wires8and the gate lines2are arranged in a same layer and are made of a same material, and the light shielding layer4is further arranged between the fan-out wires8and the base1.

In summary, in the display substrate provided in the embodiment of the present disclosure, the film structure of the marks such as the first marks6and the second marks7is the same as that of the redundant bonding pads32, and the orthographic projections of the first marks6and the second marks7on the base1are not overlapped with the orthographic projection of the light shielding layer4on the base1; the film layer structure of the fan-out wires8is the same as that of the gate lines2and the functional bonding pads31, and the orthographic projections of the fan-out wires8on the base1are overlapped with the orthographic projection of the light shielding layer4on the base1. The first marks6may include any mark disposed in the frame sealing area Q3, for example, may include at least one of a cutting mark, a grinding mark, a process mark, an overlapping mark, and a total pitch mark.

In some examples, in the display substrate provided in the embodiment of the present disclosure, the light shielding layer4may be made of any of various materials, for example, the light shielding layer4may be made of molybdenum oxide, the molybdenum oxide is black, and can effectively absorb light irradiated onto the gate lines2. Certainly, the light shielding layer4may be made of other materials, which is not limited herein.

In some examples, the material of the gate lines2in the first conductive layer may be copper, molybdenum, niobium, aluminum, etc., and taking copper as an example of the material of the gate lines2, a film thickness of the gate lines2(also the first conductive layer) may range from 1000 to 2000 angstroms (Å), and a film thickness of the light shielding layer4may range from 400 to 500 Å.

It should be noted that, in the present embodiment, the thin film transistor may be a top gate thin film transistor, and may also be a bottom gate thin film transistor, and a position of a structure (for example, the functional bonding pads31) in the same layer as a film layer where the gate electrode of the thin film transistor is located (that is, the first conductive layer where the gate lines2are located) may vary with the position of the gate electrode. In the above description, a case where the thin film transistor is a bottom gate thin film transistor is taken as an example, but the present application is not limited thereto.

In a second aspect, as shown inFIG.12, an embodiment of the present disclosure further provides a method for manufacturing a display substrate, where the method in the present embodiment may be used to form the display substrate described above, and is described by taking the display substrate shown inFIG.2as an example, the film structure of the display substrate shown inFIG.2is described above, and details are not repeated here, and certainly, the structure of the display substrate formed by the method in the present embodiment is not limited to the display substrate shown inFIG.2. The display substrate has a display area Q1, and a bonding area Q2located on at least one side of the display area Q1, and may further have a frame sealing area Q3disposed around the display area Q1, and the bonding area Q2is disposed on at least one side of the frame sealing area Q3away from the display area Q1.

Referring toFIGS.13and14,FIG.13is a side view illustrating a process for manufacturing the display substrate, andFIG.14is a plan view illustrating a process for manufacturing the display substrate and corresponding to that ofFIG.13, the method includes following steps S11to S14.

S11, forming a light shielding layer4on a base1.

Specifically, referring toFIG.13(a1) andFIG.14(a1), taking a case where the light shielding layer4is made of molybdenum oxide as an example, the molybdenum oxide is first sputtered on the base1by a sputter process to form the light shielding layer4covering the base1.

S12, removing a part of the light shielding layer4located in the bonding area Q2.

Specifically, referring to (a1) to (b1) inFIG.13, and (a2) to (b2) inFIG.14, the light shielding layer4is preliminarily patterned through a mask, specifically, the part of the light shielding layer4covering the bonding area Q2can be removed through exposure, development and etching processes, so as to form the light shielding layer4of the display substrate as shown inFIG.14(b2), and no light shielding layer4is in the bonding area Q2, thereby preventing the light shielding layer4from affecting an identification of the bonding pads3in the bonding area Q2.

In some implementations, a plurality of first marks6may be arranged at positions of the base1corresponding to the frame sealing area Q3, the light shielding layer4being patterned includes removing the light shielding layer4at the positions where the first marks6are to be disposed in the frame sealing area Q3, that is, a plurality of hollow parts63are formed at the positions of the light shielding layer4where the first marks6are to be disposed, where each hollow part63is a position where the first mark6is subsequently formed, so as to ensure that there is no light shielding layer4between the first marks6and the base1, and thus the first marks6can be identified from the side of the base1away from the first marks6. It should be noted that, since the frame sealing area Q3has an area through which a portion of the fan-out wires8passes, the part of the light shielding layer4located in the frame sealing area Q3cannot be completely removed.

S13, forming a first conductive layer D1on the side of the light shielding layer4away from the base1.

Specifically, referring to (b1) to (c1) inFIG.13, (b2) to (c2) inFIG.14, a material layer of the first conductive layer D1is sputtered on the side of the light shielding layer3away from the base1, for example, a layer of conductive material such as copper, silver, molybdenum, niobium, etc., is sputtered, by a sputtering process, the first conductive layer D1covers the display area Q2, and since the bonding pads3and the first marks6are also formed in the first conductive layer D1, the first conductive layer D1also covers the frame sealing area Q3and the bonding area Q2. Since the light shielding layer4is relatively thin, a slope of the light shielding layer4at an edge thereof proximal to the bonding area Q3is relatively small, and thus a film formation quality of the first conductive layer D1is not affected when the first conductive layer D1is provided over the light shielding layer4.

S14, patterning the first conductive layer D1, to form a plurality of gate lines2at a part of the first conductive layer D1located in the display area Q1, and form a plurality of bonding pads3at a part of the first conductive layer D1located in the bonding area Q2.

Specifically, referring to (c1) to (d1) inFIG.13, (c2) to (d2) inFIG.14, S14may include:

exposing, developing and etching the first conductive layer D1, and the light shielding layer4disposed on the side of the first conductive layer D1proximal to the base1and only in the display area Q1by a mask made according to patterns of the gate lines2and the bonding pads3, to form the gate lines2located in the display area Q1, the bonding pads3located in the bonding area Q2, the second marks7coupled to the bonding pads3, and the first marks6located in the frame sealing area Q3. That is, the first conductive layer D1and the light shielding layer4are etched through a single process using a same mask (e.g., a UV mask), if the material of the first conductive layer D1includes copper or molybdenum niobium, and the material of the light shielding layer4includes molybdenum oxide, and an etching solution for copper or molybdenum niobium may also act on the molybdenum oxide, and thus the first conductive layer D1and the light shielding layer4can be etched simultaneously in the display area Q1to form the patterns of the gate lines2(e.g., patterns shown in (d2) inFIG.14), and the bonding pads3(e.g., patterns shown in (d2) inFIG.14) and the second marks7coupled to the bonding pads can be etched in the portion of the first conductive layer D1located in the bonding area Q2by using a same mask, and the first marks6(e.g., patterns shown in (d2) inFIG.14) can be etched in the portion of the first conductive layer D1located in the frame sealing area Q3. By etching the first conductive layer D1and the light shielding layer4in a same process, a mask only used for etching the light shielding layer4can be omitted, and compared with a method in which the light shielding layer4is etched first and then the first conductive layer D1is etched, the method provided by the embodiment of the present disclosure does not suffer from a problem that patterns may be misaligned due to drilling phenomenon in a case where the light shielding layer4is etched first and then the first conductive layer D1is etched, and patterns of the gate lines2in the first conductive layer D1can be overlapped with the pattern of the light shielding layer4on the side of the gate lines2proximal to the base1as much as possible, so that a precision of manufacturing is improved.

In some implementations, the display substrate provided in the embodiment further includes a plurality of fan-out wires8and a GOA circuit arranged in the frame sealing area Q2disposed at an edge of the display area Q1, and the light shielding layer4is disposed below both the fan-out wires8and the GOA circuit, and thus, in S14, patterning the first conductive layer D1further includes etching the first conductive layer D1and the light shielding layer4simultaneously in the same process of etching the gate lines2by using the mask as above, so as to form patterns of the fan-out wires8and the GOA circuit in the frame sealing area Q2.

In some implementations, if the material of the first conductive layer D1includes copper or molybdenum niobium, the material of the light shielding layer4includes molybdenum oxide, and the etching solution for copper or molybdenum niobium may also act on the molybdenum oxide, specifically, the etching solution for copper may include at least one of ammonium oxalate, hydrogen peroxide, and a surfactant, and certainly, the etching solution for copper may also include other components, which is not limited herein.

In some examples, referring toFIG.2, the method for manufacturing the display substrate provided by the embodiment of the present disclosure further includes:

after patterning the first conductive layer D1, forming a gate insulating layer01on the side of the first conductive layer D1(the layer where the bonding pads3and the gate lines2are located) away from the base1; forming a film layer where the active layer04is located on a side of the gate insulating layer01away from the base1, and patterning the film layer to form the active layer04; forming a film layer where the source electrode05and the drain electrode06are located on a. side of the active layer04away from the base1, patterning the film layer to form the source electrode05, the drain electrode06and a plurality of data lines5, the source electrode05and the drain electrode06are arranged in a same layer and are made of a same material; forming a planarization layer03on a side of the source electrode05and the drain electrode06away from the base1, the planarization layer03may be an organic film (ORG film), and the planarization layer03flattens atop layer of the thin film transistors for facilitating to form a subsequent film layer; forming a pixel electrode07on a side of the planarization layer03away from the base1, the pixel electrode07is coupled to the drain electrode06through a via hole in the planarization layer03; forming a protective layer02on a side of the pixel electrode07away from the base1, for protecting each film layer of the thin film transistors; forming a film layer where the auxiliary electrode001is located on a side of the protective layer02away from the base1, patterning the film layer to form the auxiliary electrode001, the auxiliary electrode001is provided with pixel openings P, and the auxiliary electrode001covers the gate lines2and the data lines5; forming a film layer where the common electrode002is located on a side of the auxiliary electrode001away from the base1, and patterning the film layer to form the common electrode002the common electrode002is provided with a plurality of slits021and pixel openings P, and the slits021are opposite to the pixel electrodes06. Certainly, the structure of the display substrate is not limited to above, and for convenience of description, the above description is made only by taking the process for manufacturing the display substrate shown inFIG.2as an example.

In a third aspect, as shown inFIG.15, an embodiment of the present disclosure further provides a method for manufacturing a display substrate, where the method for manufacturing the display substrate in the embodiment may be used to form the display substrate described above, and is described by taking forming the display substrate shown inFIG.11as an example, the film structure of the display substrate inFIG.11is described above and will not repeated here, and certainly, the structure of the display substrate formed by the method in the present embodiment is not limited to that of the display substrate shown inFIG.11. The display substrate has a display area Q1, and a bonding area Q2located on at least one side of the display area Q1, and may further have a frame sealing area Q3disposed around the display area Q1, and the bonding area Q2is disposed on at least one side of the frame sealing area Q3away from the display area Q1. In the display substrate formed by the method of the present embodiment, a plurality of bonding pads3are formed in the bonding area, the bonding pads3include functional bonding pads31and redundant bonding pads32, usually, external signals are only input into the functional bonding pads, that is, usually, pins of the connector are only coupled to the functional bonding pads31, and the functional bonding pads31are further coupled to the data lines5or the GOA in the display area Q1, or coupled through the fan-out wires8, and the redundant bonding pads32are dummy electrodes, and are not coupled to the pins of the connector, and do not receive any electrical signal.

Referring toFIG.16,FIG.16is a side view illustrating a process for manufacturing the display substrate, the method including following steps S21to S24.

S21, forming a light shielding layer4on a base1.

Specifically, referring to (a) inFIG.16, taking a case where the light shielding layer4is molybdenum oxide as an example, molybdenum oxide is first sputtered on the base1by a sputter process to form the light shielding layer4covering the base1.

S22, forming a first conductive layer D1on a side of the light shielding layer4away from the base1.

Specifically, referring to (a) inFIG.16, taking the first conductive layer D1as copper for example, copper is sputtered on the side of the light shielding layer4away from the base1to form the first conductive layer D1covering the base1.

S23, patterning the first conductive layer D1and the light shielding layer4, to form a plurality of gate lines2at a part of the first conductive layer D1located in the display area Q1, and form a plurality of functional bonding pads31at a part of the first conductive layer D1located in the bonding area Q2.

Specifically, referring to (a) to (b) inFIG.16, the first conductive layer D1and the light shielding layer4are patterned together by a mask made according to patterns of the gate lines2and the functional bonding pads31, to form the gate lines in the display area Q1and form the functional bonding pads31in the bonding area Q2through exposure, development and etching processes.

In some implementations, the display substrate further includes a plurality of fan-out wires8and a GOA circuit disposed in the frame sealing area Q3, and when the first conductive layer D1and the light shielding layer4are patterned together in S23, patterns of the fan-out wires8and the GOA circuit are further formed in the frame sealing area Q3. That is, after S23, the orthographic projection of the light shielding layer4on the base1only covers patterns of the gate lines, the functional bonding pads31, the fan-out wires8and the GOA circuit.

As described above, by etching the first conductive layer D1and the light shielding layer4in a same process, a mask only used for etching the light shielding layer4can be omitted, and compared with the method of etching the light shielding layer4first and then etching the first conductive layer D1, the method provided by the embodiment of the present disclosure does not suffer from a problem that patterns are misaligned due to drilling phenomenon when the light shielding layer4is etched first and the first conductive layer D1is then etched, and patterns of the gate lines2, the functional bonding pads31, the fan-out wires8and the GOA circuit in the first conductive layer D1can coincide with the pattern of the light shielding layer4as much as possible, thereby improving the accuracy of manufacturing.

Further, referring to (b) to (d) inFIG.16, after S23and before S24, the method for manufacturing the display substrate according to the embodiment of the present disclosure further includes:

forming a gate insulating layer01on the side of the first conductive layer D1(the layer where the functional bonding pads31and the gate lines2are located) away from the base1; forming a film layer where the active layer04is located on a side of the gate insulating layer01away from the base1, and patterning the film layer to form the active layer04; forming a film layer where the source electrode05and the drain electrode06are located on a side of the active layer04away from the base1, patterning the film layer to form the source electrode05, the drain electrode06and a plurality of data lines5, the source electrode05and the drain electrode06are arranged in a same layer and are made of a same material; forming a planarization layer03on a side of the source electrode05and the drain electrode06away from the base1, the planarization layer03may be an organic film (ORG film), and the planarization layer03flattens the top layer of the thin film transistors for facilitating to form a subsequent film layer; forming a pixel electrode07on a side of the planarization layer03away from the base1, the pixel electrode07is coupled to the drain electrode06through a via hole in the planarization layer03; and forming a protective layer02on a side of the pixel electrode07away from the base1, for protecting each film layer of the thin film transistors.

S24, forming a plurality of redundant bonding pads32on a side of the first conductive layer D1away from the base1.

In some examples, the display substrate further includes: an auxiliary electrode001and a common electrode002arranged on the side of the first conductive layer D1away from the base1, and the auxiliary electrode001and the common electrode002are arranged successively along a direction away from base1, and the auxiliary electrode001and the common electrode002are electrically coupled, specifically, the auxiliary electrode001and the common electrode002are arranged on a side of the protective layer02away from base1, and the auxiliary electrode001is arranged on a side of the common electrode002proximal to base1. The redundant bonding pad32include a first conductive part321and a second conductive part322disposed on the side of the first conductive layer D1away from the base1, and the first conductive part321is electrically coupled to the second conductive part322, the first conductive part321and the common electrode002are disposed in a same layer and are made of a same material, and the second conductive part322and the auxiliary electrode001are disposed in a same layer and are made of a same material.

S24may specifically include following S241to S244.

S241, forming a second conductive layer on the side of the first conductive layer D1away from the base.

Specifically, referring to (d) to (e) inFIG.16, the second conductive layer is formed on the side of the first conductive layer D1away from the base1, and specifically, the second conductive layer where the auxiliary electrode001is located is formed on a side of the protective layer02(located on the side of the first conductive layer D1away from the base1) away from the base1.

S242, patterning the second conductive layer to form the auxiliary electrode001at a part of the second conductive layer located in the display area Q1, and form the second conductive part322of the redundant bonding pad32at a part of the second conductive layer located in the bonding area Q2.

Specifically, referring to (d) to (e) inFIG.16, the display substrate further includes a plurality of first marks6disposed in the frame sealing area Q3, and a plurality of second marks7(not shown in the figure) disposed in the bonding area Q2and coupled to the functional bonding pads31or the redundant bonding pads32, the first mark6include a third conductive part62and a fourth conductive part61, and the second mark7include a fifth conductive part and a sixth conductive part. The second conductive layer is patterned through a mask according to the pattern of the auxiliary electrode001, the patterns of the redundant bonding pads32, the patterns of the first marks6and the patterns of the second marks7, through exposure, development and etching processes, the pattern of the auxiliary electrode001is formed in the display area Q1(as shown inFIG.7), the auxiliary electrode001is provided with pixel openings P, and the auxiliary electrode001covers the gate lines2and the data lines5; the pattern of the second conductive part322of the redundant bonding pad32, the pattern of the sixth conductive part of the second mark7are formed in the bonding area Q2; the pattern of the fourth conductive part61of the first mark6is formed in the frame sealing area Q3.

S243, forming a third conductive layer on a side of the second conductive layer away from the base.

Specifically, referring to (e) to (f) inFIG.16, the third conductive layer is formed on the side of the second conductive layer (the film layer where the auxiliary electrode001and the second conductive part322are located) away from the base1, where the third conductive layer is the film layer where the common electrode001is located.

S244, patterning the third conductive layer to form a common electrode at a part of the third conductive layer in the display area, and form the first conductive part of the redundant bonding pad at a part of the third conductive layer in the bonding area.

Specifically, referring to (e) to (f) inFIG.16, the second conductive layer is patterned by the same mask as that in S242according to the pattern of the common electrode002, the patterns of the redundant bonding pads32, the patterns of the first marks6and the patterns of the second marks7, through exposure, development and etching processes, the pattern of the common electrode002(as shown inFIG.8) is formed in the display area Q1, where the common electrode002has pixel openings P and a plurality of slits021, and the slits021are opposite to the pixel electrode06; the pattern of the first conductive part321of the redundant bonding pad32, the pattern of the fifth conductive part of the second mark7are formed in the bonding area Q2; and the third conductive part62of the first mark6is formed in the frame sealing area Q3.

It should be noted that the auxiliary electrode001is only disposed under a partial area of the common electrode002, and the common electrode002wraps the auxiliary electrode001, that is, the common electrode002covers a top surface and side surfaces of the auxiliary electrode001, and thus in the process of manufacturing the display substrate, a film layer of the auxiliary electrode001is formed on the side of the protective layer02away from the base1, the auxiliary electrode001is formed by patterning the film layer, then a film layer of the common electrode002is formed, and then the common electrode002is formed by patterning the layer, the patterning including exposure, development and etching processes, and since a developing solution for the common electrode002is corrosive to the auxiliary electrode001, in order to prevent the developing solution from affecting the auxiliary electrode001during developing the common electrode002, the common electrode002may wrap the auxiliary electrode001. Certainly, the structure of the display substrate is not limited to above, and for convenience of description, the above description has been made only by taking the process for manufacturing the display substrate shown inFIG.11as an example.

In a fourth aspect, an embodiment of the present disclosure further provides a display device, which includes the display substrate described above. It should be noted that, the display device provided in the present embodiment may be: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device are further included, which can be understood by those skilled in the art, and are not described herein, but should not be construed as limiting of the present disclosure.

In some implementations, the display device further includes a color filter substrate, the color filter substrate and the display substrate are aligned and combined, and liquid crystal is poured between the color filter substrate and the display substrate to form the liquid crystal display device. The color filter substrate includes color filters, and the color filters may include various types of color filters, for example, may include a quantum dot color filter.

It will be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the present disclosure, and the present disclosure is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and scope of the present disclosure, and such modifications and improvements are also considered to be within the scope of the present disclosure.