Patent ID: 12230711

DETAILED DESCRIPTION

Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

Expressions such as “at least one of,” when preceding a list of elements (e.g., A, B, and C), modify the entire list of elements and do not modify the individual elements of the list. For example, “at least one of A, B, and C,” “at least one of A, B, or C,” “one of A, B, C, or a combination thereof,” and “one of A, B, C, and a combination thereof,” respectively, may be construed as covering any one of the following combinations: A; B; C; A and B; A and C; B and C; and A, B, and C.”

Hereinafter, when an element is described as being “on” or “above” another element, the element may be directly on the other element or may be above the other element without contacting the other element. As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when a part “includes” or “comprises” an element, unless otherwise defined, the part may further include other elements, not excluding the other elements.

The term “the” and other equivalent determiners may correspond to a singular referent or a plural referent. Unless orders of operations included in a method are specifically described or there are contrary descriptions, the operations may be performed according to appropriate orders. It is not necessarily limited to the described orders of the operations. The use of all examples and example terms are merely for describing the disclosure in detail and the disclosure is not limited to the examples and the example terms, unless they are not defined in the scope of the claims.

Electronic devices described in embodiments described hereinafter may include semiconductor-based devices and may have a gate stack structure including a gate electrode and a high-k dielectric having a higher dielectric constant than silicon oxide. These electronic devices may include, for example, logic devices or memory devices.

FIG.1is a cross-sectional view of an electronic device according to an example embodiment.

Referring toFIG.1, the electronic device100may include a substrate110, and a crystallization prevention layer130, a ferroelectric crystallization layer140, and a gate electrode150sequentially stacked on the substrate110. A channel element115may be provided on a location of the substrate110, the location corresponding to the gate electrode150, and a source S121and a drain D122may be provided at both sides of the channel element115.

The source S121may be electrically connected to a side of the channel element115, and the drain D122may be electrically connected to the other side of the channel element115. The source S121and the drain D122may be formed by implanting impurities into different areas of the substrate110, and an area of the substrate110between the source S121and the drain D122may be defined as the channel element115.

The substrate110may include, for example, a Si substrate. However, the substrate110may also include a substrate including other semiconductor materials than Si, such as Ge, SiGe, Groups III-V semiconductors, etc. In this case, the channel element115may include Si, Ge, SiGe, or Groups III-V semiconductors. However, materials of the substrate110are not limited thereto and may vary. As described below, the channel element115may be formed as a material layer that is separate from the substrate110, rather than being included in the substrate110.

The crystallization prevention layer130and the ferroelectric crystallization layer140may be sequentially provided on an upper surface of the channel element115of the substrate110. The ferroelectric crystallization layer140may have at least a portion that is crystallized, and the ferroelectric crystallization layer140may include a dielectric material having ferroelectricity or anti-ferroelectricity.

The ferroelectric crystallization layer140may be formed by crystallizing at least a portion of an amorphous dielectric material through an annealing process, as described below. The ferroelectric crystallization layer140formed by using this method may include a ferroelectric material or an anti-ferroelectric material. The ferroelectric crystallization layer140may have an effect of decreasing a sub-threshold swing SS of the electronic device100due to its ferroelectricity or anti-ferroelectricity.

The ferroelectric material may have non-centrosymmetric charge distribution in a unit cell in a crystallized material structure, and thus, may have a spontaneous dipole (electric dipole), that is, spontaneous polarization. The ferroelectric material may have remnant polarization due to the dipole, even when there is no external electric field. Also, a direction of polarization may be switched in each domain due to the external electric field.

The anti-ferroelectric material may include an array of electric dipoles. However, remnant polarization of the anti-ferroelectric material may be 0 or close to 0. Directions of adjacent dipoles become the opposite in a state when there is no electric field, so as to offset polarization, and thus, overall spontaneous polarization and remnant polarization may be 0 or close to 0. However, when an external electric field is applied, the anti-ferroelectric material may have polarization characteristics and switching characteristics.

The ferroelectric crystallization layer140may include a crystalline dielectric material having a dielectric constant that is, for example, greater than about 20. However, it is not limited thereto. For example, the ferroelectric crystallization layer140may include oxide including at least one of Si, Al, Hf, and Zr. As a detailed example, the ferroelectric crystallization layer140may include at least one of Hf-based oxide and Zr-based oxide. Here, the Hf-based oxide may include, for example, HfO or HfZrO and the Zr-based oxide may include, for example, ZrO.

FIG.2shows examples of dielectric constants (in detail, static dielectric constants) and band gaps of high-k dielectric materials. Here, the high-k dielectric materials denote materials having a higher dielectric constant than silicon oxide. Referring toFIG.2, the ferroelectric crystallization layer140may include, for example, ZrO2, HfO2, La2O3, Ta2O5, BaO, or TiO2. However, it is an example, and the ferroelectric crystallization layer140may include other various high-k dielectric materials than the described materials.

The ferroelectric crystallization layer140may further include a dopant, according to necessity. The dopant may include, for example, at least one of Si, Al, Zr, Y, La, Gd, Sr, and Hf, but is not limited thereto. When the ferroelectric crystallization layer140includes a dopant, the dopant may be doped throughout the ferroelectric crystallization layer140in a uniform concentration or may be doped in different concentrations according to areas of the ferroelectric crystallization layer140. Also, different types of dopants may be doped according to areas of the ferroelectric crystallization layer140.

The crystallization prevention layer130may be provided between the ferroelectric crystallization layer140and the channel element115. The crystallization prevention layer130may limit and/or prevent crystallization in the ferroelectric crystallization layer140based on the annealing process from being spread toward the channel element115.

The crystallization prevention layer130may include a different high-k dielectric material from the ferroelectric crystallization layer140. For example, the crystallization prevention layer130may include a dielectric material having a higher dielectric constant than silicon oxide. In detail, the crystallization prevention layer130may include a dielectric material having a dielectric constant greater than about 4.

As a detailed example, the crystallization prevention layer130may include at least one of AlOx(0<x<1), LaOx(0<x<1), YOx(0<x<1), LaAlOx(0<x<1), TaOx(0<x<1), TiOx(0<x<1), SrTiOx(0<x<1), CaO, MgO, ZrSiO, and a two-dimensional (2D) dielectric material. Here, the 2D dielectric material may be a 2D material having a dielectric property. For example, the 2D dielectric material may include hexagonal boron nitride (h-BN), etc. The materials described above are only examples, and the crystallization prevention layer130may include other various dielectric materials.

As described below, the ferroelectric crystallization layer140may be formed by crystallizing at least a portion of an amorphous dielectric material via an annealing process. The ferroelectric crystallization layer140formed through this crystallization process may include a polycrystalline dielectric material.

When the crystallization prevention layer130is not provided below the ferroelectric crystallization layer140, a bonding orbital, which is formed in the ferroelectric crystallization layer140as the ferroelectric crystallization layer140is crystallized through the annealing process, may be spread toward the channel element115of the substrate110. When the bonding orbital of the ferroelectric crystallization layer140is spread toward the channel element115, current leakage may occur due to a grain boundary formed in a polycrystalline dielectric material of the ferroelectric crystallization layer140, and the current leakage may deteriorate the performance of the electronic device100.

According to the present embodiment, the crystallization prevention layer130is provided between the ferroelectric crystallization layer140and the channel element115of the substrate110, and thus, the effects of the crystallization of the ferroelectric crystallization layer140may not be spread to an area below the crystallization prevention layer130. In detail, when the ferroelectric crystallization layer140is crystallized through the annealing process, the bonding orbital may be formed in the ferroelectric crystallization layer140. Here, the crystallization prevention layer130may limit and/or prevent the bonding orbital from being spread to the channel element115below the crystallization prevention layer130.

The gate electrode150may be provided on an upper surface of the ferroelectric crystallization layer140. Here, the gate electrode150may be arranged to face the channel element115of the substrate110. The gate electrode150may include conductive metal.

The electronic device100described above according to the present embodiment described above may include the ferroelectric crystallization layer140having ferroelectricity or anti-ferroelectricity, and thus, a sub-threshold swing SS of the electronic device100may be decreased.

FIG.3is a graph for describing an effect of improving sub-threshold swing characteristics of a logic transistor, according to an example embodiment. Here, a ferroelectric crystallization layer including ferroelectrics has been used in the logic transistor according to an example embodiment. InFIG.3, A indicates characteristics of an operation voltage Vg and a current Id of a previous silicon-based logic transistor and B indicates characteristics of an operation voltage Vg and a current Id of the logic transistor according to an example embodiment.

Referring toFIG.3, in the case of the previous silicon-based transistor, the sub-threshold swing SS may be limited to about 60 mV/dec. However, in the case of the logic transistor according to an example embodiment, the sub-threshold swing SS may be decreased to a value equal to or less than 60 mV/dec, based on voltage amplification occurring when a domain in the ferroelectrics is switched.

In the electronic device100according to an embodiment, the crystallization prevention layer130may be provided between the ferroelectric crystallization layer140and the channel element115; thus, crystallization of the ferroelectric crystallization layer140via an annealing process may be limited and/or prevented from being spread toward the channel element115, so as to prevent current leakage of the electronic device100. Like this, since the crystallization prevention layer130prevents the crystallization in the ferroelectric crystallization layer140from affecting an area below the crystallization prevention layer130, the ferroelectric crystallization layer140may maintain the effect of ferroelectricity or anti-ferroelectricity based on the crystallization, while current leakage is limited and/or prevented. Accordingly, the performance of the electronic device100may be improved.

FIG.4is a cross-sectional view of an electronic device200according to another example embodiment. Hereinafter, different aspects from the aspects of the embodiment described above will be mainly described.

Referring toFIG.4, the electronic device200may include a substrate210, and a channel layer215, a crystallization prevention layer230, a ferroelectric crystallization layer240, and a gate electrode250sequentially stacked on the substrate210. A source electrode221and a drain electrode222may be provided at both sides of the channel layer215.

The substrate210may include, for example, Si, Ge, SiGe, Groups III-V semiconductors, etc., but is not limited thereto. The channel layer215may be provided on an upper surface of the substrate210. The channel layer215may be formed as a material layer that is separate from the substrate210, rather than being included in the substrate210. The channel layer215may include, for example, at least one of an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a 2D semiconductor material, quantum dots, and an organic semiconductor. Here, the oxide semiconductor may include, for example, InGaZnO, etc., the 2D semiconductor material may include transition metal dichalcogenide (TMD) or graphene, and the quantum dots may include colloidal QD, a nanocrystal structure, etc. However, it is only an example, and the present embodiment is not limited thereto.

The source electrode221and the drain electrode222may be provided at both sides of the channel layer215. The source electrode221may be connected to a side of the channel layer215, and the drain electrode222may be connected to the other side of the channel layer215. The source electrode221and the drain electrode222may include a conductive material, such as a metal, a metal compound, a conductive polymer, etc.

The crystallization prevention layer230, the ferroelectric crystallization layer240, and the gate electrode250sequentially stacked on the channel layer225are described above, and thus, their detailed descriptions will be omitted.

FIG.5is a cross-sectional view of an electronic device300according to another example embodiment.

Referring toFIG.5, the electronic device300may include a substrate310, and a high dielectric layer360, a crystallization prevention layer330, a ferroelectric crystallization layer340, and a gate electrode350sequentially stacked on the substrate310. A channel element315may be provided on a location of the substrate310, the location corresponding to the gate electrode350, and a source S321and a drain D332may be provided at both sides of the channel element315.

The source S321may be electrically connected to a side of the channel element315and the drain D322may be electrically connected to the other side of the channel element315. The source S321and the drain D322may be formed by implanting impurities into different areas of the substrate310and an area of the substrate310between the source S321and the drain D322may be defined as the channel element315.

The substrate310may include, for example, Si, Ge, SiGe, Groups III-V semiconductors, etc. In this case, the channel element315may include Si, Ge, SiGe, or Groups III-V semiconductors. However, materials of the substrate310are not limited thereto and may vary. The channel element315may be formed as a material layer that is separate from the substrate310, as illustrated inFIG.4, rather than being included in the substrate310.

The high dielectric layer360, the crystallization prevention layer330, and the ferroelectric crystallization layer340may be sequentially provided on an upper surface of the channel element315of the substrate310.

As described above, at least a portion of the ferroelectric crystallization layer340may be crystallized and the ferroelectric crystallization layer340may include a dielectric material having ferroelectricity or anti-ferroelectricity. The ferroelectric crystallization layer340may include a crystalline dielectric material having a dielectric constant that is, for example, greater than about 20. However, it is not limited thereto. For example, the ferroelectric crystallization layer340may include oxide including at least one of Si, Al, Hf, and Zr. As a detailed example, the ferroelectric crystallization layer340may include at least one of Hf-based oxide and Zr-based oxide. Here, the Hf-based oxide may include, for example, HfO or HfZrO and the Zr-based oxide may include, for example, ZrO.

The ferroelectric crystallization layer340may further include a dopant, according to necessity. The dopant may include, for example, at least one of Si, Al, Zr, Y, La, Gd, Sr, and Hf, but is not limited thereto.

The crystallization prevention layer330may be provided at a lower surface of the ferroelectric crystallization layer340. As described above, the crystallization prevention layer330may limit and/or prevent crystallization in the ferroelectric crystallization layer340through an annealing process from being spread toward the channel element315.

The crystallization prevention layer330may include a different high-k dielectric material from the ferroelectric crystallization layer340. For example, the crystallization prevention layer330may include a dielectric material having a higher dielectric constant than silicon oxide. In detail, the crystallization prevention layer330may include a dielectric material having a dielectric constant greater than about 4.

As a detailed example, the crystallization prevention layer330may include at least one of AlOx(0<x<1), LaOx(0<x<1), YOx(0<x<1), LaAlOx(0<x<1), TaOx(0<x<1), TiOx(0<x<1), SrTiOx(0<x<1), CaO, MgO, ZrSiO, and a 2D dielectric material. Here, the 2D dielectric material may be a 2D material having a dielectric property. For example, the 2D dielectric material may include hexagonal boron nitride (h-BN), etc. The materials described above are only examples, and the crystallization prevention layer330may include other various dielectric materials.

The high dielectric layer360may be provided at a lower surface of the crystallization prevention layer330. The high dielectric layer360may, together with the crystallization prevention layer330, control the crystallization of the ferroelectric crystallization layer340. To this end, the high dielectric layer360may include a different dielectric material from the crystallization prevention layer330. In detail, the high dielectric layer360may include a high-k dielectric material having a greater dielectric constant than silicon oxide.

The high dielectric layer360may include an amorphous dielectric material or a crystalline dielectric material. For example, the high dielectric layer360may include the same dielectric material as the ferroelectric crystallization layer340. However, it is not limited thereto, and the high dielectric layer360may include a different high-k dielectric material from the ferroelectric crystallization layer340.

The gate electrode350may be provided on an upper surface of the ferroelectric crystallization layer340. Here, the gate electrode350may be arranged to face the channel element315of the substrate310. The gate electrode350may include conductive metal.

In the electronic device300according to the present embodiment, the crystallization prevention layer330and the high dielectric layer360may be provided below the ferroelectric crystallization layer340, and the crystallization prevention layer330and the high dielectric layer360may include different materials from each other. Thus, crystallization of the ferroelectric crystallization layer340may be effectively controlled. Accordingly, current leakage may be limited and/or prevented and the performance of the electronic device300may be improved.

WhileFIG.5illustrates the crystallization prevention layer330formed on the high k dielectric layer360, inventive concepts are not limited thereto. In some embodiments, the crystallization prevention layer330may be formed between the substrate310and the high k dielectric layer360and the ferroelectric crystallization layer340may be formed on top of the high k dielectric layer360.

FIG.6is a cross-sectional view of an electronic device400according to another example embodiment.

Referring toFIG.6, the electronic device400may include a substrate410, and a high band gap layer470, a high dielectric layer460, a crystallization prevention layer430, a ferroelectric crystallization layer440, and a gate electrode450sequentially stacked on the substrate410. A channel element415may be provided on a location of the substrate410, the location corresponding to the gate electrode450, and a source S421and a drain D422may be provided at both sides of the channel element415.

The substrate410may include, for example, Si, Ge, SiGe, Groups III-V semiconductors, etc. In this case, the channel element415may include Si, Ge, SiGe, or Groups III-V semiconductors. However, materials of the substrate410are not limited thereto and may vary. The channel element415may be formed as a material layer that is separate from the substrate410, as illustrated inFIG.4, rather than being included in the substrate410.

The high band gap layer470, the high dielectric layer460, the crystallization prevention layer430, and the ferroelectric crystallization layer440may be sequentially provided on an upper surface of the channel element115of the substrate410.

As described above, at least a portion of the ferroelectric crystallization layer440may be crystallized and the ferroelectric crystallization layer440may include a dielectric material having ferroelectricity or anti-ferroelectricity. The ferroelectric crystallization layer440may include a crystalline dielectric material having a dielectric constant that is, for example, greater than about 20. However, it is not limited thereto. For example, the ferroelectric crystallization layer440may include oxide including at least one of Si, Al, Hf, and Zr. The ferroelectric crystallization layer440may further include a dopant, according to necessity.

The crystallization prevention layer430may be provided at a lower surface of the ferroelectric crystallization layer440. As described above, the crystallization prevention layer430may limit and/or prevent crystallization in the ferroelectric crystallization layer440through an annealing process from being spread toward the channel element415.

The crystallization prevention layer430may include a different high-k dielectric material from the ferroelectric crystallization layer440. For example, the crystallization prevention layer430may include a dielectric material having a higher dielectric constant than silicon oxide. In detail, the crystallization prevention layer430may include a dielectric material having a dielectric constant greater than about 4. For example, the crystallization prevention layer430may include at least one of AlOx(0<x<1), LaOx(0<x<1), YOx(0<x<1), LaAlOx(0<x<1), TaOx(0<x<1), TiOx(0<x<1), SrTiOx(0<x<1), CaO, MgO, ZrSiO, and a 2D dielectric material.

The high dielectric layer460may be provided at a lower surface of the crystallization prevention layer430. The high dielectric layer460may, together with the crystallization prevention layer430, control the crystallization of the ferroelectric crystallization layer440. To this end, the high dielectric layer460may include a different dielectric material from the crystallization prevention layer430. In detail, the high dielectric layer460may include a high-k dielectric material having a greater dielectric constant than silicon oxide. The high dielectric layer460may include an amorphous dielectric material or a crystalline dielectric material.

The high band gap layer470may be provided between the high dielectric layer460and the channel element415. The high band gap layer470may suppress or prevent current leakage and also may be used for capacitance matching in a gate stack structure. The high band gap layer470may include an amorphous dielectric material having a greater band gap than a material of the high dielectric layer460formed above the high band gap layer470. For example, the high band gap layer470may include oxide including at least one of Si, Al, Hf, and Zr. However, it is not limited thereto.

The gate electrode450may be provided on an upper surface of the ferroelectric crystallization layer440. Here, the gate electrode450may be arranged to face the channel element415of the substrate410. The gate electrode450may include conductive metal.

The electronic device400according to the present embodiment may include the crystallization prevention layer430and the high dielectric layer460below the ferroelectric crystallization layer440, and thus, may effectively control the crystallization of the ferroelectric crystallization layer440. Also, the electronic device400may include, between the high dielectric layer460and the channel element415, the high band gap layer470including the amorphous dielectric material having a greater band gap than the amorphous dielectric material of the high dielectric layer460, and thus, may effectively limit and/or prevent current leakage of the electronic device400.

WhileFIG.6illustrates the crystallization prevention layer430formed on the high k dielectric layer460and the high band gap layer470, inventive concepts are not limited thereto. In some embodiments, the crystallization prevention layer430, high k-dielectric layer460, and high band gap layer470may be stacked in a different order.

FIGS.7A through7Fare views for describing a method of manufacturing an electronic device, according to an example embodiment.

Referring toFIG.7A, a substrate510, on which a channel element515, a source S521, and a drain D522are provided, may be prepared. The source S521and the drain D522may be formed by implanting and doping impurities in different areas of the substrate510, and an area of the substrate510between the source S521and the drain D522may be defined as the channel element515. The substrate510may include, for example, Si, Ge, SiGe, Groups III-V semiconductors, etc. In this case, like the substrate510, the channel element515may include Si, Ge, SiGe, or Groups III-V semiconductors. Materials of the substrate510are not limited thereto and may vary. The source S521and the drain D522may formed at a different time point. For example, after forming a gate electrode550(seeFIG.7D) described below, the source S521and the drain D522may be formed in the substrate510.

The channel element515may be formed on an upper surface of the substrate510, as a material layer separate from the substrate510, rather than being included in the substrate510. In this case, materials of the channel element515may vary. For example, the channel element515may include at least one of an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a 2D semiconductor material, quantum dots, and an organic semiconductor. The oxide semiconductor may include, for example, InGaZnO, etc., the 2D semiconductor material may include TMD or graphene, and the quantum dots may include colloidal QDs, a nanocrystal structure, etc. However, it is only an example, and the present embodiment is not limited thereto.

Referring toFIG.7B, a crystallization prevention layer530may be formed on an upper surface of the channel element515of the substrate510. The crystallization prevention layer530may be formed by depositing an amorphous dielectric material on the upper surface of the channel element515by using, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD).

The crystallization prevention layer530may limit and/or prevent the crystallization in a ferroelectric crystallization layer540, which is formed by crystallizing an amorphous dielectric material layer540′ (seeFIG.7C) through an annealing process, from being spread toward the channel element515.

The crystallization prevention layer530may include a high-k dielectric material. For example, the crystallization prevention layer530may include a dielectric material having a higher dielectric constant than silicon oxide. In detail, the crystallization prevention layer530may include a dielectric material having a dielectric constant greater than about 4.

As a detailed example, the crystallization prevention layer530may include at least one of AlOx(0<x<1), LaOx(0<x<1), YOx(0<x<1), LaAlOx(0<x<1), TaOx(0<x<1), TiOx(0<x<1), SrTiOx(0<x<1), CaO, MgO, ZrSiO, and a 2D dielectric material. Here, the 2D dielectric material may be a 2D material having a dielectric property. For example, the 2D dielectric material may include hexagonal boron nitride (h-BN), etc. The materials described above are only examples, and the crystallization prevention layer530may include other various dielectric materials.

Referring toFIG.7C, the amorphous dielectric material layer540′ may be formed on an upper surface of the crystallization prevention layer530. The amorphous dielectric material layer540′ may be formed by depositing a dielectric material different from the dielectric material of the crystallization prevention layer530on the upper surface of the crystallization prevention layer530, by using, for example, CVD or ALD.

The ferroelectric crystallization layer540may be formed by crystallizing at least a portion of the amorphous dielectric material layer540′ through an annealing process described below. The ferroelectric crystallization layer540formed by using this method may include a crystalline dielectric material having a dielectric constant that is, for example, greater than about 20, as described below. However, it is not limited thereto.

The amorphous dielectric material layer540′ may include, for example, oxide including at least one of Si, Al, Hf, and Zr. As a detailed example, the amorphous dielectric material layer540′ may include at least one of Hf-based oxide and Zr-based oxide. Here, the Hf-based oxide may include, for example, HfO or HfZrO and the Zr-based oxide may include, for example, ZrO. The amorphous dielectric material layer540′ may further include a dopant, according to necessity. The dopant may include, for example, at least one of Si, Al, Zr, Y, La, Gd, Sr, and Hf, but is not limited thereto.

Referring toFIG.7D, the gate electrode550may be formed on an upper surface of the amorphous dielectric material layer540′. The gate electrode550may be formed by depositing conductive metal on the upper surface of the amorphous dielectric material layer540′ by using, for example, CVD, ALD, or physical vapor deposition (PVD).

Referring toFIG.7E, the annealing process may be performed to form the ferroelectric crystallization layer540by crystallizing the amorphous dielectric material layer540′. The annealing process may be performed, for example, at a temperature of about 400° C. to about 1000° C. Also, the period of the annealing process may be within about one minute. However, it is not limited thereto, and the temperature and the period of the annealing process may vary. At least a portion of the amorphous dielectric material layer540′ may be crystallized through this annealing process to form the ferroelectric crystallization layer540as illustrated inFIG.7Fand the electronic device500may be manufactured.

The crystallization prevention layer530may limit and/or prevent the effect of the crystallization of the amorphous dielectric material layer540′ through the annealing process from being spread toward the channel element515. In detail, the crystallization of the amorphous dielectric material layer540′ through the annealing process may be started from an area contacting the gate electrode550and proceed downwardly to form a polycrystalline dielectric material. Also, as the crystallization process is completed, the ferroelectric crystallization layer540including the polycrystalline dielectric material may be formed.

The crystallization prevention layer530may maintain an amorphous state while the annealing process is performed, and thus, may limit and/or prevent a bonding orbital formed in the ferroelectric crystallization layer540from being spread toward the channel element515of the substrate510. Like this, the crystallization prevention layer530may be provided between the amorphous dielectric material layer540′ and the channel element515to limit and/or prevent the effect of the crystallization of the amorphous dielectric material layer540′ from being spread toward the channel element515.

The ferroelectric crystallization layer540formed by crystallizing the amorphous dielectric material layer540′ may include a dielectric material having ferroelectricity or anti-ferroelectricity. The ferroelectric crystallization layer440may include a crystalline dielectric material having a dielectric constant that is, for example, greater than about 20. However, it is not limited thereto.

For example, the ferroelectric crystallization layer540may include oxide including at least one of Si, Al, Hf, and Zr. As a detailed example, the ferroelectric crystallization layer540may include at least one of Hf-based oxide and Zr-based oxide. Here, the Hf-based oxide may include, for example, HfO or HfZrO and the Zr-based oxide may include, for example, ZrO. The ferroelectric crystallization layer540may further include a dopant, according to necessity.

The method of manufacturing the electronic device500described above may further include, before forming the crystallization prevention layer530, forming a high dielectric layer (not shown) on an upper surface of the channel element515of the substrate510. Here, the high dielectric layer may be formed by depositing a certain dielectric material on the upper surface of the channel element515by using, for example, CVD or AVD. The high dielectric layer may, together with the crystallization prevention layer530, control the crystallization of the ferroelectric crystallization layer540. To this end, the high dielectric layer may include a different dielectric material from the crystallization prevention layer530. In detail, the high dielectric layer may include a high-k dielectric material having a higher dielectric constant than silicon oxide.

The high dielectric layer may include an amorphous dielectric material. Also, the high dielectric layer may include a crystalline dielectric material. In this case, the high dielectric layer may be formed by depositing an amorphous dielectric material on the upper surface of the channel element515and then crystallizing the amorphous dielectric material through a certain annealing process.

The method may further include, before forming the high dielectric layer described above, forming a high band gap layer (not shown) on the upper surface of the channel element515of the substrate510. The high band gap layer may be formed by depositing a certain amorphous dielectric material on the upper surface of the channel element515by using, for example, CVD or ALD.

The high band gap layer may suppress or prevent current leakage and may also be used for capacitance matching in a gate stack structure. The high band gap layer may include an amorphous dielectric material having a greater band gap than a material of the high dielectric layer formed above the high band gap layer. For example, the high band gap layer may include at least one of Si, Al, Hf, and Zr. However, it is not limited thereto.

FIGS.8A through8Care views for describing a method of manufacturing an electronic device, according to an example embodiment.

FIGS.8A to8Cillustrate a method of manufacturing the electronic device inFIG.4, according to an example embodiment. InFIG.8A, a channel film may be formed on the substrate210and patterned into the channel layer215. Then a conductive layer may be formed on the channel layer215and patterned into the source electrode221and drain electrode222. InFIG.8B, a crystallization prevention layer230, amorphous dielectric material layer240′, and gate electrode250may be sequentially formed on the channel layer215, source electrode221, and drain electrode222through deposition processes. Next, inFIG.8C, an annealing process may convert the amorphous dielectric material layer240′ into the ferroelectric crystallization layer240ofFIG.4.

FIGS.9A through9Bare views for describing a method of manufacturing an electronic device, according to an example embodiment, such as the electronic device inFIG.5.

FIGS.9A and9Bare similar toFIGS.7A to7D, except a high-k dielectric layer360may be formed on the substrate before forming the crystallization prevention layer530to provide a stacked structure shown inFIG.9A. Then, inFIG.9B, the stacked structure may be annealed. After the annealing process, the electronic device inFIG.5is provided.

FIGS.10A through10Bare views for describing a method of manufacturing an electronic device, according to an example embodiment, such as the electronic device inFIG.6.

FIGS.10A and10Bare similar toFIGS.7A to7D, except a high band gap layer470and a high-k dielectric layer360may be formed on the substrate before forming the crystallization prevention layer530to provide a stacked structure shown inFIG.10A. Then, inFIG.10B, the stacked structure may be annealed. After the annealing process, the electronic device inFIG.6may be provided.

In the electronic devices according to the example embodiments, the ferroelectric crystallization layers have ferroelectricity or anti-ferroelectricity, and thus, sub-threshold swings of the electronic devices may be decreased. Also, the crystallization prevention layers may be provided between the ferroelectric crystallization layers and the channel elements, and thus, crystallization of the ferroelectric crystallization layers via annealing processes may be limited and/or prevented from being spread toward the channel elements, so as to limit and/or prevent current leakage of the electronic devices. Like this, since the crystallization prevention layers limit and/or prevent the crystallization in the ferroelectric crystallization layers from affecting an area below the crystallization prevention layers, the ferroelectric crystallization layers may maintain the effect of ferroelectricity or anti-ferroelectricity based on the crystallization, while current leakage is limited and/or prevented. Accordingly, the performance of the electronic devices may be improved.

Also, the crystallization prevention layers and the high dielectric layers may be provided between the ferroelectric crystallization layers and the channel elements and the crystallization prevention layers and the high dielectric layers may include different materials from each other. Thus, crystallization of the ferroelectric crystallization layers may be effectively controlled. Accordingly, current leakage may be limited and/or prevented and the performance of the electronic devices may be improved. Embodiments that are described herein are only examples and various modifications may be made from these embodiments by one of ordinary skill in the art.

It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.