Patent ID: 12211773

DETAILED DESCRIPTION OF THE DRAWINGS

The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices. The terms “semiconductor die” and “die” are used interchangeably.

Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, and resistors, create a relationship between voltage and current necessary to perform electrical circuit functions.

Back-end manufacturing refers to cutting or singulating the finished wafer into the individual semiconductor die and packaging the semiconductor die for structural support, electrical interconnect, and environmental isolation. To singulate the semiconductor die, the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections can be made with conductive layers, bumps, stud bumps, conductive paste, or wirebonds. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.

FIG.1ashows a semiconductor wafer100with a base substrate material102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor die or components104is formed on wafer100separated by a non-active, inter-die wafer area or saw street106. Saw street106provides cutting areas to singulate semiconductor wafer100into individual semiconductor die104. In one embodiment, semiconductor wafer100has a width or diameter of 100-450 millimeters (mm).

FIG.1Bshows a cross-sectional view of a portion of semiconductor wafer100. Each semiconductor die104has a back or non-active surface108and an active surface110containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface110to implement analog circuits or digital circuits, such as digital signal processor (DSP), application specific integrated circuits (ASIC), memory, or other signal processing circuit. Semiconductor die104may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing.

An electrically conductive layer112is formed over active surface110using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer112can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive material. Conductive layer112operates as contact pads electrically connected to the circuits on active surface110.

An electrically conductive bump material is deposited over conductive layer112using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductive layer112using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form balls or bumps114. In one embodiment, bump114is formed over an under bump metallization (UBM) having a wetting layer, barrier layer, and adhesive layer. Bump114can also be compression bonded or thermocompression bonded to conductive layer112. Bump114represents one type of interconnect structure that can be formed over conductive layer112. The interconnect structure can also use bond wires, conductive paste, stud bump, micro bump, or other electrical interconnect.

InFIG.1c, semiconductor wafer100is singulated through saw street106using a saw blade or laser cutting tool118into individual semiconductor die104. The individual semiconductor die104can be inspected and electrically tested for identification of known good die or unit (KGD/KGU) post singulation.

FIGS.2a-2jillustrate a process of forming an integrated antenna-in-package (AiP)150.FIG.2ais a partial cross-sectional view of a substrate152. While only a single substrate152is shown, hundreds or thousands of substrates are commonly processed on a common carrier, using the same steps described herein for a single unit but performed en masse. Substrate152could also start out as a single large substrate for multiple units, which are singulated from each other during or after the manufacturing process.

Substrate152includes one or more insulating layers154interleaved with one or more conductive layers156. Insulating layer154is a core insulating board in one embodiment, with conductive layers156patterned over the top and bottom surfaces, e.g., a copper-clad laminate substrate. Conductive layers156also include conductive vias electrically coupled through insulating layers154. Substrate152can include any number of conductive and insulating layers interleaved over each other. A solder mask or passivation layer can be formed over either side of substrate152. Any suitable type of substrate or leadframe is used for substrate152in other embodiments.

Forming AiP150begins with mounting semiconductor die104, discrete components160, board-to-board (B2B) connector162, other discrete active or passive components, additional semiconductor die, and any other desired components to substrate152. Any number, type, and combination of semiconductor die and other electrical components can be used to make AiP150. In one embodiment, semiconductor die104is a 5G transceiver and discrete components160form a radio frequency (RF) filter.

Solder paste is used to electrically and mechanically couple discrete component160and B2B connector162to conductive layer156. Any combination of discrete active and passive components can be mounted as desired, e.g., to implement a radio frequency (RF) filter. B2B connector162is used to attach another PCB, a ribbon cable, or another electrical system to AiP150to allow other packages to communicate with, and utilize the functionality of, semiconductor die104. Semiconductor die104is connected to B2B connector162and discrete components160through conductive layer156.

InFIG.2b, an encapsulant or molding compound176is deposited over substrate152, covering top and side surfaces of semiconductor die104and discrete components160. Encapsulant176also extends under semiconductor die104and discrete components160between the components and substrate152. In other embodiments, a separate mold underfill (MUF) is used instead.

Encapsulant176is an electrically insulating material deposited using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable application process. Encapsulant176can be polymer composite material, such as an epoxy resin, epoxy acrylate, or polymer with or without a filler. Encapsulant176is non-conductive and environmentally protects the semiconductor device from external elements and contaminants.

B2B connector162remains outside of encapsulant176by utilizing a lid or mask that can be removed after encapsulation or by using a mold that protects the B2B connector within a non-molding compartment. Encapsulant176is typically deposited with substrate152remaining as a larger panel with multiple AiP150being formed at once. The larger panel of substrate152and encapsulant176is then singulated after manufacturing is complete.

InFIG.2c, a conductive material is optionally sputtered over AiP150to form a conductive shielding layer180. Shielding layer180is formed using any suitable metal deposition technique, e.g., PVD, CVD, other sputtering methods, spraying, or plating. The sputtered material can be copper, steel, aluminum, gold, combinations thereof, or any other suitable conductive material. In some embodiments, shielding layer180can be made by sputtering on multiple layers of differing material, e.g., stainless steel-copper-stainless steel or titanium-copper.

Shielding layer180reduces EMI between the components of AiP150and other nearby electronic devices. Shielding layer180is optionally connected to a ground voltage node through conductive layers156to improve EMI reduction. Shielding layer180can be connected to conductive layer156by sputtering the shielding layer onto an exposed side surface of substrate152where the conductive layer is exposed, or onto a contact pad of conductive layer156on the top surface of substrate152. B2B connector162remains outside of shielding layer180by sputtering the shielding layer while the B2B connector is protected by a lid or can. Shielding layer180is formed directly on and covers top and side surfaces of encapsulant176.

FIG.2dshows a view perpendicular toFIG.2c, illustrating how contact pads182are formed over a side surface of substrate152. Contact pads182are formed as a conductive via through insulating layers154, or as a series of stacked conductive vias and conductive layers. Singulating through substrate152using, e.g., a laser cutting tool as illustrated, exposes contact pad182at a side surface of the substrate.

FIG.2eshows an external view of a completed subpackage181from the same angle as the cross-section ofFIG.2c, illustrating contact pads182formed on side surface184of substrate152. Subpackage181includes substrate152, encapsulated semiconductor die104, any other desired electrical components, and B2B connector162.

Contact pads182are formed as part of conductive layers156in one embodiment, e.g., as one or more conductive vias and conductive layers that are exposed as part of the process of singulating substrate152. In another embodiment, contact pads182are formed as part of shielding layer180directly on exposed portions of conductive layers156and then chemical or laser etched to separate the contact pads from the shielding layer. In a third embodiment, contact pads182are formed separately from conductive layers156and shielding layer180in an independent process.FIG.2fshows a top-down view of AiP150. Having contact pads on edge184allows subpackage181to be mounted to another substrate oriented perpendicularly, i.e., standing up on edge184.

FIG.2gshows a panel or sheet of antennae200. In one embodiment, antennae200are dielectric resonator antennae (DRA). DRA are radio antennae commonly used at microwave frequencies and higher, consisting of a block of ceramic material of various shapes, the dielectric resonator, mounted on a metal surface that operates as a ground plane. Radio waves are introduced into the inside of the resonator material from the transmitter circuit and bounce back and forth between the resonator walls, forming standing waves. The walls of the resonator are partially transparent to radio waves, allowing the radio power to radiate into space. Any other suitable type of antenna is used for antennae200in other embodiments.

Antennae200are formed or disposed on a substrate202having a similar structure to substrate152, with one or more conductive layers206interleaved between insulating layers204. Any suitable type of substrate can be used for substrate202, including those described above for substrate152. In one embodiment, a ground plane for the antenna is formed in substrate202. InFIG.2h, bumps210are formed on substrate202opposite antenna200in a manner similar to the above description of bumps114being formed on semiconductor die104. Other types of interconnect structures are used in other embodiments.

InFIG.2i, construction of AiP150is continued by mounting subpackages181onto substrate202of antenna200. Subpackages181are mounted with substrate152oriented perpendicularly to substrate202. In other embodiments, the angle can be non-perpendicular. Bumps210are reflowed between conductive layer206of substrate202and contact pads182on surface184to electrically and mechanically connect substrate152to substrate202. Other types of interconnect structures are used in other embodiments. Semiconductor die104are electrically coupled to antennae200through substrates152and202. AiP150are singulated from each other by cutting through substrate202and antennae200using a laser cutting tool212, a saw blade, or another suitable mechanism inFIG.2jto complete the integrated AiP structures.

Substrate152is oriented perpendicularly to substrate202, which allows a main board to easily connect to B2B connector162via a corresponding B2B connector directly mounted onto the main board, while antenna200remains oriented perpendicularly to the main board. AiP150is an integrated5gantenna-in-package structure that is easily integrated into any mobile device design, connects to the mobile device's main board via B2B connector162, and provides a perpendicularly oriented antenna as desired for advanced 5G communication protocols. Mounting substrate152with semiconductor die104directly to substrate202of antenna200perpendicularly saves having to utilize a flexible substrate to orient the two portions perpendicular to each other, greatly reducing cost and complexity of manufacturing AiP150compared to the prior art.

FIGS.3a-3cillustrate forming an AiP220with the side contacts being formed using a metal bar222to form contact pads on the side subpackage224rather than embedding conductive material within the substrate as with subpackage181.FIG.3ashows two AiP220units being formed back-to-back sharing a metal bar222between the two units. Metal bar222extends across a saw street between the units so that, after singulation through the metal bar, a portion of the metal bar remains exposed at a side surface of encapsulant176of each unit as shown inFIG.3b.

Metal bar222is disposed directly on conductive layer156to provide electrical connection to semiconductor die104. Metal bar222is optionally soldered onto substrate152or attached using a conductive adhesive. Shielding layer180can optionally be used with metal bar222.

FIG.3cshows completion of AiP220by attaching subpackage224to substrate202via metal bar222and solder bump210. Metal bar222operates as a contact pad exposed at a side surface of subpackage224. However, metal bar222is disposed on substrate152rather than being embedded within or formed on a side surface of substrate152as in subpackage181. In other embodiments, a contact pad on the side surface of a submodule extends vertically across both substrate152and encapsulant176rather than being contained only within one or the other.

FIG.4shows an AiP230with additional features that can be independently used with any of the above-described embodiments. An adhesive or epoxy bead or bump232is disposed between subpackage234and substrate202. Epoxy232is dispensed onto either substrate202along with bumps210or onto subpackage234. Epoxy232may physically contact, and even completely surround, bumps210in some embodiments.

Epoxy232stabilizes the physical connection between subpackage234and antenna200by providing physical contact points along an extra axis as compared to just solder bumps210that are all oriented in a line together. Epoxy232can be added to any of the above embodiments to improve stability. In embodiments with metal bar222embedded in encapsulant176instead of contact pad182formed on a side surface of substrate152, epoxy232is disposed between substrate152and substrate202instead of between encapsulant176and substrate202as illustrated inFIG.4. Epoxy232is usable in any of the above embodiments, with or without shielding layer180.

Also shown inFIG.4, B2B connector162is placed on the opposite side of substrate152from semiconductor die104and other electrical components. In other embodiments, electrical components are mounted on both sides of substrate152. B2B connector162on the bottom of substrate152can be used with contact pads182or metal bar222, with or without epoxy232, and with or without shielding layer180.

FIGS.5aand5billustrate integrating the above-described semiconductor packages, e.g., AiP230, into a larger electronic device400.FIG.5aillustrates a partial cross-section of AiP230mounted onto a printed circuit board (PCB) or other substrate402as part of electronic device400. In one embodiment, electronic device400is a mobile phone and PCB402is the main board of the phone. AiP230is mounted by interfacing B2B connector162on PCB152with a corresponding B2B connector406on PCB402. In some embodiments, AiP230is sufficiently secured by B2B connectors162and406snapping together. In other embodiments, an adhesive or other support mechanism is disposed between substrate152and PCB402. When semiconductor die104and encapsulant176are disposed on the bottom of substrate152, the encapsulant can physically contact PCB402to physically support AiP230on the PCB. Semiconductor die104is electrically coupled to PCB402through substrate152and B2B connectors162and406.

FIG.5billustrates electronic device400including PCB402with a plurality of semiconductor packages mounted on a surface of the PCB, including AiP230. Electronic device400can have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. Electronic device400can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electronic device400can be a subcomponent of a larger system. For example, electronic device400can be part of a tablet computer, cellular phone, digital camera, communication system, or other electronic device. Electronic device400can also be a graphics card, network interface card, or another signal processing card that is inserted into a computer. The semiconductor packages can include microprocessors, memories, ASICs, logic circuits, analog circuits, RF circuits, discrete active or passive devices, or other semiconductor die or electrical components.

InFIG.5b, PCB402provides a general substrate for structural support and electrical interconnection of the semiconductor packages mounted on the PCB. Conductive signal traces404are formed over a surface or within layers of PCB402using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces404provide for electrical communication between the semiconductor packages, mounted components, and other external systems or components. Traces404also provide power and ground connections to the semiconductor packages as needed.

In some embodiments, a semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. Second level packaging involves mechanically and electrically attaching the intermediate substrate to PCB402. In other embodiments, a semiconductor device may only have the first level packaging where the die is mechanically and electrically mounted directly to PCB402.

For the purpose of illustration, several types of first level packaging, including bond wire package408and flipchip409, are shown on PCB402. Additionally, several types of second level packaging, including ball grid array (BGA)410, bump chip carrier (BCC)407, land grid array (LGA)416, multi-chip module (MCM)418, quad flat non-leaded package (QFN)420, quad flat package422, and embedded wafer level ball grid array (eWLB)426are shown mounted on PCB402along with AiP230. Conductive traces404electrically couple the various packages and components disposed on PCB402to AiP230, giving use of the components within AiP230to other components on the PCB.

Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electronic components, can be connected to PCB402. In some embodiments, electronic device400includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because the semiconductor packages include sophisticated functionality, electronic devices can be manufactured using less expensive components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.

While one or more embodiments of the present invention have been illustrated in detail, the skilled artisan will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the present invention as set forth in the following claims.