Patent ID: 12198630

DETAILED DESCRIPTION OF THE EMBODIMENTS

The embodiments will now be described more fully hereinafter with reference to the accompanying drawings. The embodiments may, however, be provided in different forms and should not be construed as limiting. The same reference numbers indicate the same components throughout the disclosure. In the accompanying figures, the thickness of layers and regions may be exaggerated for clarity.

Some of the parts which are not associated with the description may not be provided in order to describe embodiments of the disclosure.

It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In contrast, when an element is referred to as being “directly on” another element, there may be no intervening elements present.

Further, the phrase “in plan view” means when an object portion is viewed from above, and the phrase “in a schematic cross-sectional view” means when a schematic cross-section taken by vertically cutting an object portion is viewed from the side. The terms “overlap” or “overlapped” mean that a first object may be above or below or to a side of a second object, and vice versa. Additionally, the term “overlap” may include layer, stack, face or facing, extending over, covering, or partly covering or any other suitable term as would be appreciated and understood by those of ordinary skill in the art. The expression “not overlap” may include meaning such as “apart from” or “set aside from” or “offset from” and any other suitable equivalents as would be appreciated and understood by those of ordinary skill in the art. The terms “face” and “facing” may mean that a first object may directly or indirectly oppose a second object. In a case in which a third object intervenes between a first and second object, the first and second objects may be understood as being indirectly opposed to one another, although still facing each other.

The spatially relative terms “below,” “beneath,” “lower,” “above,” “upper,” or the like, may be used herein for ease of description to describe the relations between one element or component and another element or component as illustrated in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. For example, in the case where a device illustrated in the drawing is turned over, the device positioned “below” or “beneath” another device may be placed “above” another device. Accordingly, the illustrative term “below” may include both the lower and upper positions. The device may also be oriented in other directions and thus the spatially relative terms may be interpreted differently depending on the orientations.

When an element, such as a layer, is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it may be directly on, connected to, or coupled to the other element or layer or intervening elements or layers may be present. When, however, an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present. To this end, the term “connected” may refer to physical, electrical, and/or fluid connection, with or without intervening elements. It will be further understood that when the terms “comprises,” “comprising,” “has,” “have,” “having,” “includes” and/or “including” are used, they may specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and/or any combination thereof.

It will be understood that, although the terms “first,” “second,” “third,” or the like may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element or for the convenience of description and explanation thereof. For example, when “a first element” is discussed in the description, it may be termed “a second element” or “a third element,” and “a second element” and “a third element” may be termed in a similar manner without departing from the teachings herein.

The terms “about” or “approximately” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (for example, the limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

In the specification and the claims, the term “and/or” is intended to include any combination of the terms “and” and “or” for the purpose of its meaning and interpretation. For example, “A and/or B” may be understood to mean “A, B, or A and B.” The terms “and” and “or” may be used in the conjunctive or disjunctive sense and may be understood to be equivalent to “and/or.” In the specification and the claims, the phrase “at least one of” is intended to include the meaning of “at least one selected from the group of” for the purpose of its meaning and interpretation. For example, “at least one of A and B” may be understood to mean “A, B, or A and B.”

Unless otherwise defined or implied, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this disclosure pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an ideal or excessively formal sense unless clearly defined in the specification.

FIG.1is a schematic plan view of a display device1according to an embodiment.

InFIG.1, a first direction DR1, a second direction DR2, and a third direction DR3are shown. The first direction DR1may be a direction parallel to a side of the display device1in plan view, for example, a horizontal direction of the display device1. The second direction DR2may be a direction parallel to another side in contact with the above side of the display device1in plan view, for example, a vertical direction of the display device1. For case of description, a side in the first direction DR1is referred to as a right direction in plan view, another side in the first direction DR1is referred to as a left direction in plan view, a side in the second direction DR2is referred to as an upward direction in plan view, and another side in the second direction DR2is referred to as a downward direction in plan view. The third direction DR3may be a thickness direction of the display device1. However, directions mentioned in embodiments may be relative directions, and the embodiments are not limited to the mentioned directions.

Unless otherwise defined, the terms “upper” and “upper surface” used herein based on the third direction DR3refer to a display surface side of a display panel10, and the terms “lower,” “lower surface” and “back surface” refer to an opposite side of the display panel10from the display surface side.

Referring toFIG.1, examples of the display device1may include various electronic devices including a display screen. Examples of the display device1may include a mobile phone, a smartphone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an electronic book, a personal digital assistant (PDA), a portable multimedia player (PMP), a navigation device, an ultra-mobile PC (UMPC), a television, a game console, a wristwatch-type electronic device, a head mounted display, a monitor of a PC, a notebook computer, a car dashboard, a digital camera, a camcorder, an external billboard, an electronic board, various medical devices, various inspection devices, various home appliances including a display area such as a refrigerator and a washing machine, and an Internet of things (IoT) device. However, embodiments are not limited thereto. Representative examples of the display device1to be described later may include a smartphone, a tablet PC, and a notebook computer. However, embodiments are not limited thereto.

The display device1may include the display panel10, a panel driving circuit20, a circuit board30, and a readout circuit40.

The display device1may include the display panel10having an active area AAR and a non-active area NAR. The active area AAR may include a display area in which a screen is displayed. The active area AAR may completely overlap the display area. Pixels PX displaying an image may be disposed in the display area. Each pixel PX may include a light emitting element EL (seeFIG.6).

For example, the active area AAR further may include a fingerprint sensing area. The fingerprint sensing area may be an area that reacts to light and an area configured to sense the amount or wavelength of incident light. The fingerprint sensing area may overlap the display area. For example, the fingerprint sensing area may be disposed only in a limited area necessary for fingerprint recognition (or fingerprint detection) within the active area AAR. For example, the fingerprint sensing area may overlap a part of the display area but may not overlap the other part of the display area. In another example, the fingerprint sensing area may be defined as an area exactly the same as the active area AAR. For example, the entire active area AAR may be utilized as an area for fingerprint sensing. Light sensors (or photo sensors) PS that react to light may be disposed in the fingerprint sensing area. Each of the light sensors PS may include a light sensing element PD (seeFIG.6) that senses incident light and converts the incident light into an electrical signal.

The non-active area NAR may be disposed around the active area AAR. The non-active area NAR may be a bezel area. The non-active area NAR may surround all sides (e.g., four sides in the drawing) of the active area AAR, but embodiments are not limited thereto.

The non-active area NAR may be disposed around the active area AAR. The panel driving circuit20may be disposed in the non-active area NAR. The panel driving circuit20may drive the pixels PX and/or the light sensors PS. The panel driving circuit20may output signals and voltages for driving the display panel10. The panel driving circuit20may be formed as an integrated circuit and mounted on the display panel10. In the non-active area NAR, signal lines for transmitting signals between the panel driving circuit20and the active area AAR may be further disposed. In another example, the panel driving circuit20may be mounted on the circuit board30.

For example, signal lines or the readout circuit40for transmitting signals to the active area AAR may be disposed in the non-active area NAR. The readout circuit40may be connected to each light sensor PS through a signal line and may receive a current flowing through each light sensor PS to sense a user's fingerprint input. The readout circuit40may be formed as an integrated circuit and attached onto a display circuit board by using a chip on film (COF) method. However, embodiments are not limited thereto, and the readout circuit40may be attached onto the non-active area NAR of the display panel10by using a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method.

The circuit board30may be attached to an end of the display panel10by using an anisotropic conductive film (ACF). Lead lines of the circuit board30may be electrically connected to a pad portion of the display panel10. The circuit board30may be a flexible film such as a flexible printed circuit board or a chip on film.

FIG.2is a block diagram of the display device1ofFIG.1.

Referring toFIG.2, the pixels PX and the light sensors PS disposed in the active area AAR of the display panel10may be driven by the panel driving circuit20.

The panel driving circuit20may include a data driver22for driving the pixels PX of the display panel10, a scan driver23for driving the pixels PX and the light sensors PS, and a timing controller21for controlling driving timings of the data driver22and the scan driver23. For example, the panel driving circuit20may further include a power supply unit24and an emission control driver25.

The timing controller21may receive an image signal supplied from outside the display device1. The timing controller21may output image data DATA and a data control signal DCS to the data driver22. For example, the timing controller21may generate a scan control signal SCS for controlling the operation timing of the scan driver23and an emission control driving signal ECS for controlling the operation timing of the emission control driver25. For example, the timing controller21may generate the scan control signal SCS and the emission control driving signal ECS and may output the scan control signal SCS to the scan driver23through a scan control line and output the emission control driving signal ECS to the emission control driver25through an emission control driving line.

The data driver22may convert the image data DATA into analog data voltages and output the analog data voltages to data lines DL. The scan driver23may generate scan signals according to the scan control signal SCS and sequentially output the scan signals to scan lines SL1through SLn.

The power supply unit24may generate a driving voltage ELVDD (seeFIG.6) and supply the driving voltage ELVDD to a power supply voltage line VL and may generate a common voltage ELVSS (seeFIG.6) and supply the common voltage ELVSS to the power supply voltage line VL. The power supply voltage line VL may include a driving voltage line and a common voltage line. The driving voltage ELVDD may be a high potential voltage for driving light emitting elements and light sensing elements, and the common voltage ELVSS may be a low potential voltage for driving the light emitting elements and the light sensing elements. For example, the driving voltage ELVDD may have a higher potential than the common voltage ELVSS.

The emission control driver25may generate emission control signals according to the emission control driving signal ECS and sequentially output the emission control signals to emission control lines EML. The emission control signals of the emission control driver25may have pulses of a first-level voltage VGL supplied from a first-level voltage line or pulses of a second-level voltage VGH supplied from a second-level voltage line. Although the emission control driver25is illustrated as being separate from the scan driver23, embodiments are not limited thereto, and the emission control driver25may be included in the scan driver23.

The readout circuit40may be connected to each light sensor PS through a readout line ROL and may receive a current flowing through each light sensor PS to sense a user's fingerprint input. The readout circuit40may generate fingerprint sensing data according to the magnitude of a current sensed by each light sensor PS and transmit the fingerprint sensing data to a processor. The processor may analyze the fingerprint sensing data and determine whether the fingerprint sensing data matches a user's fingerprint by comparing the fingerprint sensing data with a preset fingerprint. In case that the preset fingerprint and the fingerprint sensing data transmitted from the readout circuit40are the same, preset functions may be performed.

The display panel10may further include pixels PX, light sensors PS, scan lines SL1through SLn connected to the pixels PX and the light sensors PS, data lines DL and emission control lines EML connected to the pixels PX, and readout lines ROL connected to the light sensors PS.

Each of the pixels PX may be connected to at least any one of the scan lines SL1through SLn, any one of the data lines DL, at least one of the emission control lines EML, and the power supply voltage line VL.

Each of the light sensors PS may be connected to any one of the scan lines SL1through SLn, any one of the readout lines ROL, and the power supply voltage line VL.

The scan lines SL1through SLn may connect the scan driver23to the pixels PX and the light sensors PS. The scan lines SL1through SLn may provide scan signals output from the scan driver23to the pixels PX and the light sensors PS.

The data lines DL may connect the data driver22to the pixels PX. The data lines DL may provide image data output from the data driver22to the pixels PX.

The emission control lines EML may connect the emission control driver25to the pixels PX. The emission control lines EML may provide emission control signals output from the emission control driver25to the pixels PX.

The readout lines ROL may connect the light sensors PS to the readout circuit40. The readout lines ROL may provide a sensing current generated according to a photocurrent output from each of the light sensors PS to the readout circuit40. Accordingly, the readout circuit40may sense a user's fingerprint.

Power supply voltage lines VL may connect the power supply unit24to the pixels PX and the light sensors PS. The power supply voltage lines VL may provide the driving voltage ELVDD or the common voltage ELVSS received from the power supply unit24to the pixels PX and the light sensors PS.

FIG.3is a schematic diagram illustrating fingerprint sensing of the display device1according to an embodiment.

Referring toFIG.3, the display device1may further include a window WDL disposed on the display panel10. The display panel10may include a substrate SUB, a display layer DPL disposed on the substrate SUB and including the pixels PX and the light sensors PS, and an encapsulation layer TFE disposed on the display layer DPL.

In case that a user's finger touches an upper surface of the window WDL of the display device1, light output from the pixels PX of the display panel10may be reflected by ridges RID and valleys VAL between the ridges RID of the user's fingerprint F. For example, the ridges RID of the fingerprint F contact the upper surface of the window WDL, but the valleys VAL of the fingerprint F may not contact the window WDL. For example, the upper surface of the window WDL may contact air in the valleys VAL.

In case that the fingerprint F contacts the upper surface of the window WDL, light output from light emitting portions of the pixels PX may be reflected by the ridges RID and the valleys VAL of the fingerprint F. Here, since a refractive index of the fingerprint F and a refractive index of air are different, the amount of light reflected from the ridges RID of the fingerprint F and the amount of light reflected from the valleys VAL may be different. Accordingly, the ridges RID and the valleys VAL of the fingerprint F may be distinguished based on a difference in the amount of reflected light, e.g., the amount of light incident on the light sensors PS. Since the light sensors PS output electrical signals (i.e., photocurrents) according to the difference in the amount of light, a fingerprint pattern of the finger may be identified.

FIG.4is a schematic layout view illustrating pixels PX and light sensors PS in a display area DA of a display panel10according to an embodiment.

Referring toFIG.4, the display area DA may include first pixels PX1, second pixels PX2, third pixels PX3, and fourth pixels PX4. The pixels PX may be divided into the first pixels PX1, the second pixels PX2, the third pixels PX3, and the fourth pixels PX4.

Each unit pixel UPX may include a first pixel PX1, a second pixel PX2, a third pixel PX3, and a fourth pixel PX4. The first pixel PX1, the second pixel PX2, the third pixel PX3, and the fourth pixel PX4may be defined as a unit pixel UPX. The unit pixel UPX may be defined as the smallest unit of pixels that displays white light.

The first pixel PX1may include a first light emitting portion ELU1emitting first light and a first pixel driver PDU1for supplying a driving current to a light emitting element of the first light emitting portion ELU1. The first light may be light of a red wavelength band. For example, a main peak wavelength of the first light may be located at about 600 nm to about 750 nm.

The second pixel PX2may include a second light emitting portion ELU2emitting second light and a second pixel driver PDU2for supplying a driving current to a light emitting element of the second light emitting portion ELU2. The second light may be light of a green wavelength band. For example, a main peak wavelength of the second light may be located at about 480 nm to about 560 nm.

The third pixel PX3may include a third light emitting portion ELU3emitting third light and a third pixel driver PDU3for supplying a driving current to a light emitting element of the third light emitting portion ELU3. The third light may be light of a blue wavelength band. For example, a main peak wavelength of the third light may be located at about 370 nm to about 460 nm.

The fourth pixel PX4may include a fourth light emitting portion ELU4emitting the second light and a fourth pixel driver PDU4for supplying a driving current to a light emitting element of the fourth light emitting portion ELU4.

The first pixel driver PDU1, the second pixel driver PDU2, the third pixel driver PDU3, and the fourth pixel driver PUD4may be disposed along the first direction DR1or the second direction DR2. For example, the first pixel driver PDU1and the fourth pixel driver PDU4may be adjacent to each other along the first direction DR1, and the second pixel driver PDU2and the third pixel driver PDU3may be adjacent to each other along the first direction DR1. The first pixel driver PDU1and the third pixel driver PDU3may be alternately disposed along the second direction DR2, and the second pixel driver PDU2and the fourth pixel driver PDU4may be alternately disposed along the second direction DR2.

Each of the first light emitting portion ELU1, the second light emitting portion ELU2, the third light emitting portion ELU3, and the fourth light emitting portion ELU4may overlap at least two pixel drivers. For example, the first light emitting portion ELU1may overlap the first pixel driver PDU1and the fourth pixel driver PDU4, and the third light emitting portion ELU3may overlap the second pixel driver PDU2and the third pixel driver PDU3. Each of the second light emitting portion ELU2and the fourth light emitting portion ELU4may overlap the first through fourth pixel drivers PDU1through PDU4and two sensing drivers PSDU.

The first light emitting portion ELU1, the second light emitting portion ELU2, the third light emitting portion ELU3, and the fourth light emitting portion ELU4may have an octagonal planar shape. However, embodiments are not limited thereto. The first light emitting portion ELU1, the second light emitting portion ELU2, the third light emitting portion ELU3, and the fourth light emitting portion ELU4may have a quadrilateral planar shape such as a rhombus or a polygonal planar shape other than a quadrilateral and an octagon.

Each of the light sensors PS may include a light sensing portion PSU and a sensing driver PSDU. The light sensing portion PSU may be disposed between the first light emitting portion ELU1and the third light emitting portion ELU3adjacent to each other in the first direction DR1and may be disposed between the second light emitting portion ELU2and the fourth light emitting portion ELU4adjacent to each other in the second direction DR2. The light sensing portion PSU may overlap the sensing driver PSDU.

Each of the light sensing portions PSU may have an octagonal planar shape. However, embodiments are not limited thereto. Each of the light sensing portions PSU may have a quadrilateral planar shape such as a rhombus or a polygonal planar shape other than a quadrilateral and an octagon.

Due to the placement positions and planar shapes of the first light emitting portion ELU1, the second light emitting portion ELU2, the third light emitting portion ELU3, and the fourth light emitting portion ELU4, a distance D12between a center C1of the first light emitting portion ELU1and a center C2of the second light emitting portion ELU2adjacent to each other, a distance D23between the center C2of the second light emitting portion ELU2and a center C3of the third light emitting portion ELU3adjacent to each other, a distance D14between the center C1of the first light emitting portion ELU1and a center C4of the fourth light emitting portion ELU4adjacent to each other, and a distance D34between the center C3of the third light emitting portion ELU3and the center C4of the fourth light emitting portion ELU4adjacent to each other may be substantially the same.

For example, due to the placement positions and planar shapes of the first light emitting portion ELU1, the second light emitting portion ELU2, the third light emitting portion ELU3, the fourth light emitting portion ELU4, and the light sensing portion PSU, a distance D11between the center C1of the first light emitting portion ELU1and a center C5of the light sensing portion PSU adjacent to each other, a distance D22between the center C2of the second light emitting portion ELU2and the center C5of the light sensing portion PSU adjacent to each other, a distance D33between the center C3of the third light emitting portion ELU3and the center C5of the light sensing portion PSU adjacent to each other, and a distance D44between the center C4of the fourth light emitting portion ELU4and the center C5of the light sensing portion PSU adjacent to each other may be substantially the same.

FIG.5illustrates pixel drivers PDU, sensing drivers PSDU, scan write lines GWLk−1 and GWLk, scan initialization lines GILk−1 and GILk, scan control lines GCLk−1 and GCLk, emission control lines EMLk−1 and EMLk, reset control lines RSTLk−1 and RSTLk, data lines DLj−2 through DLj+1, and readout lines ROLq−1 through ROLq+1 according to an embodiment.

Referring toFIG.5, a sensing driver PSDU may be disposed for every two pixel drivers among the first through fourth pixel drivers PDU1through and PDU4. For example, a sensing driver PSDU may be disposed between the first pixel driver PDU1and the second pixel driver PDU2. For example, the third pixel driver PDU3, the second pixel driver PDU2, the sensing driver PSDU, the first pixel driver PDU1, and the fourth pixel driver PDU4may be sequentially disposed along the first direction DR1. For example, the sensing driver PSDU may be disposed on a side of the first pixel driver PDU1, and the fourth pixel driver PDU4may be disposed on another side of the first pixel driver PDU1.

In another example, a sensing driver PSDU may be disposed between the third pixel driver PDU3and the fourth pixel driver PDU4. For example, the first pixel driver PDU1, the fourth pixel driver PDU4, the sensing driver PSDU, the third pixel driver PDU3, and the second pixel driver PDU2may be sequentially disposed along the first direction DR1. For example, the sensing driver PSDU may be disposed on a side of the third pixel driver PDU3, and the second pixel driver PDU2may be disposed on another side of the third pixel driver PDU3.

The sensing drivers PSDU may be disposed in the second direction DR2. The first pixel drivers PDU1and the third pixel drivers PDU3may be alternately disposed in the second direction DR2. The second pixel drivers PDU2and the fourth pixel drivers PDU4may be alternately disposed in the second direction DR2.

The scan write lines GWLk−1 and GWLk, the scan initialization lines GILk−1 and GILk, the scan control lines GCLk−1 and GCLk, the emission control lines EMLk−1 and EMLk, and the reset control lines RSTLk−1 and RSTLk may extend along the first direction DR1. The data lines DLj−2 through DLj+1 and the readout lines ROLq−1 through ROLq+1 may extend along the second direction DR2.

Each of the sensing drivers PSDU may overlap any one of the scan write lines GWLk−1 and GWLk, any one of the scan initialization lines GILk−1 and GILk, any one of the scan control lines GCLk−1 and GCLk, any one of the emission control lines EMLk−1 and EMLk, any one of the reset control lines RSTLk−1 and RSTLk, and any one of the readout lines ROLq−1 through ROLq+1. Each of the first through fourth pixel drivers PDU1through PDU4may overlap any one of the scan write lines GWLk−1 and GWLk, any one of the scan initialization lines GILk−1 and GILk, any one of the scan control lines GCLk−1 and GCLk, any one of the emission control lines EMLk−1 and EMLk, any one of the reset control lines RSTLk−1 and RSTLk, and any one of the data lines DLj−2 through DLj+1.

However, the arrangement relationship of the pixel drivers PDU and the sensing drivers PSDU is not limited to the embodiment ofFIG.5. For example, the sensing drivers PSDU may be disposed to correspond one-to-one to the first through fourth pixel drivers PDU1through PDU4. One sensing driver PSDU may be disposed on a side of each of the first through fourth pixel drivers PDU1through PDU4.

FIG.6is a schematic diagram of an equivalent circuit of a pixel PX and a light sensor PS according to an embodiment.

For case of description,FIG.6illustrates a schematic diagram of an equivalent circuit of a first pixel PX1connected to a kthscan initialization line GILk, a kthscan write line GWLk, a kthscan control line GCLk, a (k−1)thscan write line GWLk−1 and a jthdata line DLj and a light sensor PS connected to the kthscan write line GWLk, a kthreset control line RSTLk and a qthreadout line ROLq.

The first pixel PX1may include a light emitting element EL and a first pixel driver PDU1controlling the amount of light emitted from the light emitting element EL. The light emitting element EL may include a first light emitting portion ELU1. The first pixel driver PDU1may include a driving transistor DT, switch elements, and a first capacitor Cst. The switch elements include first through sixth transistors T1through T6.

The driving transistor DT may include a gate electrode, a first electrode, and a second electrode. The driving transistor DT controls a drain-source current Isd (hereinafter, referred to as a “driving current”) flowing between the first electrode and the second electrode according to a data voltage applied to the gate electrode. The driving current Isd flowing through a channel layer of the driving transistor DT may be proportional to the square of a difference between a voltage Vsg between the first electrode and the gate electrode of the driving transistor DT and a threshold voltage as shown in Equation 1.

I⁢sd=k′×(V⁢s⁢g-V⁢t⁢h)2Equation⁢1
Where Isd is a driving current and a source-drain current flowing through the channel layer of the driving transistor DT, k′ is a proportional coefficient determined by the structure and physical characteristics of the driving transistor DT, Vsg is a voltage between the first electrode and the gate electrode of the driving transistor DT, and Vth is a threshold voltage of the driving transistor DT.

The light emitting element EL emits light according to the driving current Isd. As the driving current Isd increases, the amount of light emitted from the light emitting element EL may increase.

The light emitting element EL may be an organic light emitting diode including an organic light emitting layer disposed between an anode and a cathode. In another example, the light emitting element EL may be a quantum dot light emitting element including a quantum dot light emitting layer disposed between an anode and a cathode. In another example, the light emitting element EL may be an inorganic light emitting element including an inorganic semiconductor disposed between an anode and a cathode. In case that the light emitting element EL is an inorganic light emitting element, the light emitting element EL may include a micro light emitting diode or a nano light emitting diode. InFIG.12, the anode of the light emitting element EL corresponds to a pixel electrode171, and the cathode corresponds to a common electrode173.

The anode of the light emitting element EL may be connected to a second electrode of the fifth transistor T5and a first electrode of the sixth transistor T6, and the cathode of the light emitting element EL may be connected to a common voltage line VSL to which the common voltage ELVSS is applied.

The first transistor T1may be turned on by a kthscan write signal of the kthscan write line GWLk to connect (e.g., electrically connect) the first electrode of the driving transistor DT to the jthdata line DLj. Accordingly, a data voltage of the jthdata line DLj may be applied to the first electrode of the driving transistor DT. The first transistor T1may have a gate electrode connected to the kthscan write line GWLk, a first electrode connected to the jthdata line DLj, and a second electrode connected to the first electrode of the driving transistor DT.

The second transistor T2may be turned on by a kthscan control signal of the kthscan control line GCLk to connect (e.g., electrically connect) the gate electrode and the second electrode of the driving transistor DT. In case that the gate electrode and the second electrode of the driving transistor DT are connected, the driving transistor DT may be driven as a diode. The second transistor T2may have a gate electrode connected to the kthscan control line GCLk, a first electrode connected to the gate electrode of the driving transistor DT, and a second electrode connected to the second electrode of the driving transistor DT.

The third transistor T3may be turned on by a kthscan initialization signal of the kthscan initialization line GILk to connect (e.g., electrically connect) the gate electrode of the driving transistor DT to a first initialization voltage line VIL1. Accordingly, a first initialization voltage of the first initialization voltage line VIL1may be applied to the gate electrode of the driving transistor DT. The third transistor T3may have a gate electrode connected to the kthscan initialization line GILk, a first electrode connected to the first initialization voltage line VIL1, and a second electrode connected to the gate electrode of the driving transistor DT.

The fourth transistor T4may be turned on by a kthemission control signal of a kthemission control line EMLk to connect (e.g., electrically connect) the first electrode of the driving transistor DT to a driving voltage line VDL to which the driving voltage ELVDD is applied. The fourth transistor T4may have a gate electrode connected to the kthemission control line EMLk, a first electrode connected to the driving voltage line VDL, and a second electrode connected to the first electrode of the driving transistor DT.

The fifth transistor T5may be turned on by the kthemission control signal of the kthemission control line EMLk to connect (e.g., electrically connect) the second electrode of the driving transistor DT to the anode of the light emitting element EL. The fifth transistor T5may have a gate electrode connected to the kthemission control line EMLk, a first electrode connected to the second electrode of the driving transistor DT, and the second electrode connected to the anode of the light emitting element EL.

In case that both the fourth transistor T4and the fifth transistor T5are turned on, the driving current Isd of the driving transistor DT according to the voltage of the gate electrode of the driving transistor DT may flow to the light emitting element EL.

The sixth transistor T6may be turned on by a (k−1)thscan write signal of the (k−1)thscan write line GWLk−1 to connect (e.g., electrically connect) the anode of the light emitting element EL to a second initialization voltage line VIL2. A second initialization voltage VAINT of the second initialization voltage line VIL2may be applied to the anode of the light emitting element EL. The sixth transistor T6may have a gate electrode connected to the (k−1)thscan write line GWLk−1, the first electrode connected to the anode of the light emitting element EL, and a second electrode connected to the second initialization voltage line VIL2.

The first capacitor Cst may be formed between the gate electrode of the driving transistor DT and the driving voltage line VDL. A first capacitor electrode of the first capacitor Cst may be connected to the gate electrode of the driving transistor DT, and a second capacitor electrode of the first capacitor Cst may be connected to the driving voltage line VDL.

In case that the first electrode of each of the driving transistor DT and the first through sixth transistors T1through T6is a source electrode, the second electrode may be a drain electrode. In another example, in case that the first electrode of each of the driving transistor DT and the first through sixth transistors T1through T6is a drain electrode, the second electrode may be a source electrode.

An active layer of each of the driving transistor DT and the first through sixth transistors T1through T6may be made of any one of polysilicon, amorphous silicon, and an oxide semiconductor. For example, the active layer of each of the driving transistor DT, the first transistor T1, and the fourth through sixth transistors T4through T6may be made of polysilicon. The active layer of each of the second transistor T2and the third transistor T3may be made of an oxide semiconductor. For example, the driving transistor DT, the first transistor T1, and the fourth through sixth transistors T4through T6may be formed as P-type metal oxide semiconductor field effect transistors (MOSFETs), and the second transistor T2and the third transistor T3may be formed as N-type MOSFETs.

Each light sensor PS may include a light sensing element PD and a sensing driver PSDU for controlling a sensing current according to a photocurrent of the light sensing element PD. The sensing driver PSDU may include sensing transistors and various signal lines for controlling a sensing current generated by the light sensing element PD. The sensing transistors may include first through third sensing transistors LT1through LT3.

Each light sensing element PD may be a photodiode including a sensing anode, a sensing cathode, and a photoelectric conversion layer disposed between the sensing anode and the sensing cathode. Each light sensing element PD may convert light incident from the outside into an electrical signal. The light sensing element PD may be an inorganic photodiode or phototransistor made of an inorganic material of a pn type or a pin type. In another example, the light sensing element PD may be an organic photodiode including an electron donor material that generates donor ions and an electron acceptor material that generates acceptor ions. InFIG.15, the sensing anode of the light sensing element PD corresponds to a first electrode175, and the sensing cathode of the light sensing element PD corresponds to the common electrode173.

The light sensing element PD may generate photocharges in case that it is exposed to external light, and the generated photocharges may be accumulated in the sensing anode of the light sensing element PD. For example, a voltage of a first node N1electrically connected to the sensing anode may increase. In case that the light sensing element PD and the qthreadout line ROLq are connected according to the turn-on state of the first and third sensing transistors LT1and LT3, a sensing voltage may be accumulated in a third node N3between the qthreadout line ROLq and the third sensing transistor LT3in proportion to the voltage of the first node N1in which electric charges are accumulated.

The first sensing transistor LT1may be turned on by the voltage of the first node N1applied to a gate electrode to connect (e.g., electrically connect) the second initialization voltage line VIL2and a second electrode of the third sensing transistor LT3. The first sensing transistor LT1may have the gate electrode connected to the first node N1, a first electrode connected to the second initialization voltage line VIL2, and a second electrode connected to a first electrode of the third sensing transistor LT3. The first sensing transistor LT1may be a source follower amplifier that generates a source-drain current in proportion to the amount of charge of the first node N1input to the gate electrode. Although the first electrode of the first sensing transistor LT1is illustrated as being connected to the second initialization voltage line VIL2, embodiments are not limited thereto, and the first electrode of the first sensing transistor LT1may be connected (e.g., electrically connected) to the driving voltage line VDL or the first initialization voltage line VIL1.

The second sensing transistor LT2may be turned on by a kthreset control signal of the kthreset control line RSTLk to connect (e.g., electrically connect) the first node N1to a reset voltage line VRL for applying a reset voltage Vrst. The second sensing transistor LT2may have a gate electrode connected to the kthreset control line RSTLk, a first electrode connected to the reset voltage line VRL, and a second electrode connected to the first node N1.

The third sensing transistor LT3may be turned on by the kthscan write signal of the kthscan write line GWLk to connect (e.g., electrically connect) the second electrode of the first sensing transistor LT1and the qthreadout line ROLq. The third sensing transistor LT3may have a gate electrode connected to the kthscan write line GWLk, the first electrode connected to the second electrode of the first sensing transistor LT1, and the second electrode connected to the third node N3and the qthreadout line ROLq.

An active layer of each of the first through third sensing transistors LT1through LT3may be made of any one of polysilicon, amorphous silicon, and an oxide semiconductor. For example, the active layers of the first sensing transistor LT1and the third sensing transistor LT3may be made of polysilicon. The active layer of the second sensing transistor LT2may be made of an oxide semiconductor. For example, the first sensing transistor LT1and the third sensing transistor LT3may be formed as P-type MOSFETs, and the second sensing transistor LT2may be formed as an N-type MOSFET.

Schematic diagrams of equivalent circuits of a second pixel driver PDU2of a second pixel PX2, a third pixel driver PDU3of a third pixel PX3, and a fourth pixel driver PDU4of a fourth pixel PX4may be substantially the same as the schematic diagram of an equivalent circuit the first pixel driver PDU1of the first pixel PX1described above with reference toFIG.6. Therefore, the schematic diagrams of the equivalent circuits of the second pixel driver PDU2of the second pixel PX2, the third pixel driver PDU3of the third pixel PX3, and the fourth pixel driver PDU4of the fourth pixel PX4will not be described for descriptive convenience.

FIGS.7A and7Bare a waveform diagram of a kthscan initialization signal Glk, a kthscan control signal GCk, a (k−1)thscan write signal GWk−1, a kthscan write signal GWk, a kthemission control signal EMk, and a kthreset control signal RSTk transmitted to a pixel PX and a light sensor PS according to an embodiment.FIG.7Ashows a signal waveform of a first pixel PX1, andFIG.7Bshows a signal waveform of a light sensor PS.

Referring toFIGS.7A and7Bin conjunction withFIG.6, the kthemission control signal EMk may be a signal transmitted to the kthemission control line EMLk and a signal for controlling turn-on and turn-off of the fourth transistor T4and the fifth transistor T5. The kthscan initialization signal Glk may be a signal transmitted to the kthscan initialization line GILk and a signal for controlling turn-on and turn-off of the third transistor T3. The kthscan control signal GCk may be a signal transmitted to the kthscan control line GCLk and a signal for controlling turn-on and turn-off of the second transistor T2. The (k−1)thscan write signal GWk−1 may be a signal transmitted to the (k−1)thscan write line GWLk−1 and a signal for controlling turn-on and turn-off of the sixth transistor T6. The kthscan write signal GWk may be a signal transmitted to the kthscan write line GWLk and a signal for controlling turn-on and turn-off of the first transistor T1and the third sensing transistor LT3. The kthreset control signal RSTk may be a signal transmitted to the kthreset control line RSTLk and a signal for controlling turn-on and turn-off of the second sensing transistor LT2.

InFIG.7A, the kthemission control signal EMk, the kthscan initialization signal GIk, the kthscan control signal GCk, the (k−1)thscan write signal GWk−1, and the kthscan write signal GWk may have a signal repeated every one frame period. According to the operation of the first pixel PX1, one frame period may include a first period t1in which the voltage of the gate electrode of the driving transistor DT is initialized to the first initialization voltage VINT, a second period t2in which the voltage of the anode of the light emitting element EL is initialized to the second initialization voltage VAINT, a third period t3in which a data voltage is supplied to the first electrode of the driving transistor DT and a threshold voltage of the driving transistor DT is sampled, a fourth period t4in which a data voltage is supplied to the first electrode of the driving transistor DT, and a fifth period t5in which the light emitting element EL emits light.

The kthscan initialization signal Glk may have a second-level voltage VGH during the first period t1and may have a first-level voltage VGL during the other periods. The (k−1)thscan write signal GWk−1 may have the first-level voltage VGL during the second period t2and may have the second-level voltage VGH during the other periods. The kthscan control signal GCk may have the second-level voltage VGH during the third period t3and may have the first-level voltage VGL during the other periods. The kthscan write signal GWk may have the first-level voltage VGL during the fourth period t4and may have the second-level voltage VGH during the other periods. The kthemission control signal EMk may have the second-level voltage VGH during the first through fourth periods t1through t4and may have the first-level voltage VGL during the fifth period t5. The first-level voltage VGL may be a gate low voltage (or a lower voltage), and the second-level voltage VGH may be a gate high voltage (or a higher voltage).

Since the first transistor T1, the fourth through sixth transistors T4through T6, and the first and third sensing transistors LT1and LT3are formed as P-type MOSFETs, they may be turned on in case that a signal of the first-level voltage VGL is transmitted to their gate electrode and may be turned off in case that a signal of the second-level voltage VGH is transmitted to their gate electrode. For example, since the second transistor T2, the third transistor T3, and the second sensing transistor LT2are formed as N-type MOSFETs, they may be turned on in case that a signal of the second-level voltage VGH is transmitted to their gate electrode and may be turned off in case that a signal of the first-level voltage VGL is transmitted to their gate electrode.

The operation of the first pixel PX1during the first through fifth periods t1through t5will now be described in detail.

During the first period t1, the kthscan initialization signal Glk having the second-level voltage VGH may be supplied to the kthscan initialization line GILk. Accordingly, the third transistor T3may be turned on by the kthscan initialization signal Glk having the second-level voltage VGH. Due to the turn-on state of the third transistor T3, the gate electrode of the driving transistor DT may be initialized to the first initialization voltage VINT1of the first initialization voltage line VIL1.

Then, during the second period t2, the (k−1)thscan write signal GWk−1 having the first-level voltage VGL may be supplied to the (k−1)thscan write line GWLk−1. Accordingly, the sixth transistor T6may be turned on by the (k−1)thscan write signal GWk−1 having the first-level voltage VGL. Due to the turn-on state of the sixth transistor T6, the anode of the light emitting element EL may be initialized to the second initialization voltage VINT2of the second initialization voltage line VIL2.

Then, during the third period t3, the kthscan control signal GCk having the second-level voltage VGH may be supplied to the kthscan control line GCLk. Accordingly, the second transistor T2may be turned on by the kthscan control line GCLk having the second-level voltage VGH. Due to the turn-on state of the second transistor T2, the gate electrode and the second electrode of the driving transistor DT may be connected (e.g., electrically connected) to each other, and the driving transistor DT may be driven as a diode.

Then, during the fourth period t4, the kthscan write signal GWk having the first-level voltage VGL may be supplied to the kthscan write line GWLk, and the kthscan control signal GCk having the second-level voltage VGH may be supplied to the kthscan control line GCLk. Accordingly, the first transistor T1may be turned on by the kthscan write signal GWkline having the first-level voltage VGL, and the second transistor T2may be turned on by the kthscan control signal GCk having the second-level voltage VGH. Due to the turn-on state of the first transistor T1, a data voltage of the jthdata line DLj may be supplied to the first electrode of the driving transistor DT.

For example, since a voltage difference (Vsg=Vdata−VINT1) between the first electrode and the gate electrode of the driving transistor DT is smaller than the threshold voltage of the driving transistor DT, the driving transistor DT may form a current path until the voltage difference between the first electrode and the gate electrode reaches the threshold voltage. For this reason, during the third period t3, the voltage of the gate electrode of the driving transistor DT may rise to a voltage (Vdata-Vth) obtained by subtracting the threshold voltage Vth of the driving transistor DT from a data voltage Vdata.

Then, during the fifth period t5, the kthemission control signal EMk having the first-level voltage VGL may be supplied to the kthemission control line EMLk. Accordingly, the fourth transistor T4and the fifth transistor T5may be turned on by the kthemission control signal EMk having the first-level voltage VGL. Due to the turn-on state of the fourth transistor T4, the first electrode of the driving transistor DT may be connected to the driving voltage line VDL. Due to the turn-on state of the fifth transistor T5, the second electrode of the driving transistor DT may be connected (e.g., electrically connected) to the anode of the light emitting element EL.

In case that the fourth transistor T4and the fifth transistor T5are turned on, the driving current Isd flowing according to the voltage of the gate electrode of the driving transistor DT may be supplied to the light emitting element EL. The driving current Isd may be defined as Equation 2.

I⁢sd=k′×(V⁢D⁢D-(V⁢d⁢a⁢t⁢a-V⁢t⁢h)-V⁢t⁢h)2Equation⁢2
In Equation 2, Vth is a threshold voltage of the driving transistor DT, VDD is a driving voltage of the driving voltage line VDL, and Vdata is a data voltage. A gate voltage of the driving transistor DT is (Vdata-Vth), and a voltage of the first electrode is VDD. Equation 2 is rearranged into Equation 3.

I⁢sd=k′×(V⁢D⁢D-V⁢d⁢a⁢t⁢a)2Equation⁢3
Ultimately, the driving current Isd may not depend on the threshold voltage Vth of the driving transistor DT as shown in Equation 3. For example, the threshold voltage Vth of the driving transistor DT may be compensated, and the light emitting element EL may emit light according to the driving current Isd controlled by the driving voltage VDD and the data voltage Vdata.

The operation of the light sensor PS will now be described in detail with reference toFIG.7B.

The kthreset control signal RSTk and the kthscan write signal GWk may have a signal repeated every one frame period. One frame period in which the light sensor PS operates may proceed independently of one frame period in which the first pixel PX1operates, but embodiments are not limited thereto.

One frame period of the light sensor PS may include a reset period RSP (in which the sensing anode of the light sensing element PD is reset to the reset voltage Vrst), a light exposure period EP (in which the light sensing element PD is exposed to external light, photocharges are generated according to the intensity of the external light, and accordingly, the voltage of the sensing anode of the light sensing element PD and the voltage of the first node N1rise), and a fingerprint reading period ROP (in which the second sensing transistor LT2is turned on to read a fingerprint according to the magnitude of a sensing current flowing through the qthreadout line ROLq).

The kthreset control signal RSTk may have the second-level voltage VGH during the reset period RSP and may have the first-level voltage VGL during the light exposure period EP and the fingerprint reading period ROP. The kthscan write signal GWk may have the first-level voltage VGL during the reset period RSP and may have the second-level voltage VGH and the first-level voltage VGL during each of the light exposure period EP and the fingerprint reading period ROP. For example, a processor may recognize (or detect) the second-level voltage VGH of the kthscan write signal GWk generated after the light exposure period EP as a valid turn-on signal.

During the reset period RSP, the kthreset control signal RSTk having the second-level voltage VGH may be supplied to the kthreset control line RSTLk. Accordingly, the second sensing transistor LT2may be turned on, and the first node N1and the sensing anode of the light sensing element PD may be connected to the reset voltage line VRL. Since the common voltage ELVSS corresponding to a voltage higher than the reset voltage Vrst is applied to the sensing cathode of the light sensing element PD and a second node N2, the light sensing element PD may be kept reverse-biased. For example, the voltage level of the first node N1may be about −6.5 V, and the voltage level of the second node N2may be about −2.5 V.

For example, during the light exposure period EP, the light sensing element PD may be exposed to external light, and photocharges may be generated according to the intensity of the external light. Accordingly, the voltage of the sensing anode of the light sensing element PD and the voltage of the first node N1may rise. In case that a user's touch occurs, the light sensing element PD may generate photocharges corresponding to light reflected by ridges RID (seeFIG.3) or valleys VAL (seeFIG.3) between the ridges RID of a fingerprint, and a reverse current may be generated in proportion to the amount of the generated photocharges. For example, a photocurrent Iph flowing from the second node N2to the first node N1may be generated. Accordingly, the voltage of the first node N1may increase. Since the voltage of the first node N1increases as the amount of charge accumulated in the first node N1increases, the light exposure period EP may be set sufficiently long.

During the fingerprint reading period ROP, the third sensing transistor LT3may be turned on to read the fingerprint according to the magnitude of the sensing current flowing through the qthreadout line ROLq. During the fingerprint reading period ROP, the kthscan write signal GWk having the first-level voltage VGL may be supplied to the kthscan write line GWLk. Accordingly, the third sensing transistor LT3may be turned on, and a sensing current of the first sensing transistor LT1may be output to the qthreadout line ROLq through the third sensing transistor LT3. The sensing current may be a source-drain current generated in proportion to the amount of charge of the first node N1input to the gate electrode of the first sensing transistor LT1. The readout circuit40(seeFIG.2) may sense a sensing voltage charged in the qthreadout line ROLq and the third node N3by the sensing current and may read the ridges RID or valleys VAL of the fingerprint.

In the display device1according to an embodiment, the first sensing transistor LT1may be turned on in case that the voltage Vsg between the first electrode and the gate electrode of the first sensing transistor LT1reach the threshold voltage Vth during the light exposure period EP. Accordingly, the sensing current may be changed in proportion to the amount of charge of the first node N1input to the gate electrode of the first sensing transistor LT1.

For example, since the first sensing transistor LT1remains turned off before the voltage of the first node N1reaches the threshold voltage Vth of the first sensing transistor LT1, the gate electrode of the first sensing transistor LT1may be a floating electrode to which an external voltage is not applied. For example, the voltage of the gate electrode of the first sensing transistor LT1may be changed by parasitic capacitance formed between the gate electrode of the first sensing transistor LT1and a signal line adjacent to the gate electrode of the first sensing transistor LT1. For example, in case that a signal change occurs in a signal line adjacent to the gate electrode of the first sensing transistor LT1, the voltage of the gate electrode of the first sensing transistor LT1may change. For example, a leakage current may flow through the first sensing transistor LT1. Since the leakage current of the first sensing transistor LT1causes a noise signal irrelevant to the sensing current, the accuracy of the fingerprint reading operation of the display device1may be reduced or degraded.

The display device1according to an embodiment may include a shielding electrode SHE (seeFIG.8) disposed between the gate electrode of the first sensing transistor LT1and a signal line adjacent to the gate electrode of the first sensing transistor LT1or overlapping the signal line. Accordingly, a parasitic capacitor between the gate electrode of the first sensing transistor LT1and the signal line adjacent to the gate electrode of the first sensing transistor LT1may be prevented or minimized. For example, since the leakage current of the first sensing transistor LT1is prevented, a decrease or degradation in the accuracy of the fingerprint reading operation may be prevented. The display device1according to an embodiment will be described in detail below.

The operations of a second pixel PX2, a third pixel PX3, and a fourth pixel PX4may be substantially the same as the operation of the first pixel PX1described above with reference toFIGS.6and7. Therefore, the operation of the second pixel PX2, the third pixel PX3, and the fourth pixel PX4will not be described for descriptive convenience.

FIG.8is a schematic layout view illustrating a first active layer, a first gate metal layer, a second gate metal layer, a second active layer, a third gate metal layer and a first data layer of a first pixel driver PDU1and a sensing driver PSDU according to an embodiment.FIG.9is a schematic layout view illustrating the first active layer, the first gate metal layer, the second gate metal layer, the second active layer, the third gate metal layer, the first data layer and a second data layer of the first pixel driver PDU1and the sensing driver PSDU according to an embodiment.

Referring toFIGS.8and9, the first pixel driver PDU1may include a driving transistor DT, first through sixth transistors T1through T6, a first capacitor Cst, connection electrodes BE1through BE5, and a first anode connection electrode ANDE1. The sensing driver PSDU may include first through third sensing transistors LT1through LT3, sensing connection electrodes LBE1through LBE3, and a second anode connection electrode ANDE2. A shielding electrode SHE may be further disposed in the first pixel driver PDU1and the sensing driver PSDU.

A kthreset control line RSTLk, a kthemission control line EMLk, a kthscan write line GWLk, a kthscan control line GCLk, and a kthscan initialization line GILk may extend in the first direction DR1. A jthdata line DLj may extend in the second direction DR2. A driving voltage line VDL may extend in the second direction DR2. A qthreadout line ROLq may extend in the second direction DR2.

The arrangement relationship of the first pixel driver PDU1will be described.

The driving transistor DT may include a channel layer DTA, a gate electrode DTG, a first electrode DTS, and a second electrode DTD. The channel layer DTA of the driving transistor DT may overlap the gate electrode DTG of the driving transistor DT. The gate electrode DTG of the driving transistor DT may be disposed on the channel layer DTA of the driving transistor DT.

The gate electrode DTG of the driving transistor DT may be connected (e.g., electrically connected) to a first connection electrode BE1through a first contact hole CNT1. The first connection electrode BE1may be connected (e.g., electrically connected) to a second electrode D2of the second transistor T2through a second contact hole CNT2. The first connection electrode BE1may cross the kthscan control line GCLk.

The first electrode DTS of the driving transistor DT may be connected (e.g., electrically connected) to a first electrode S1of the first transistor T1and a second electrode D4of the fourth transistor T4.

The second electrode DTD of the driving transistor DT may be connected (e.g., electrically connected) to a second connection electrode BE2through a third contact hole CNT3. The second connection electrode BE2may be connected (e.g., electrically connected) to the second electrode D2of the second transistor T2through a fourth contact hole CNT4.

For example, a region of the gate electrode DTG of the driving transistor DT which overlaps a second capacitor electrode CE12may correspond to a first capacitor electrode CE11of the first capacitor Cst.

The first transistor T1may be connected (e.g., electrically connected) to a channel layer A1, a gate electrode G1, the first electrode S1, and a second electrode D1. The channel layer A1of the first transistor T1may overlap the gate electrode G1of the first transistor T1. The gate electrode G1of the first transistor T1may be disposed on the channel layer A1of the first transistor T1. The gate electrode G1of the first transistor T1may be integral with the kthscan write line GWLk. The gate electrode G1of the first transistor T1may be a portion of the kthscan write line GWLk.

The first electrode S1of the first transistor T1may be connected to a third connection electrode BE3through a fifth contact hole CNT5. The third connection electrode BE3may be connected (e.g., electrically connected) to the jthdata line DLj through a sixth contact hole CNT6. The second electrode D1of the first transistor T1may be connected (e.g., electrically connected) to the first electrode DTS of the driving transistor DT and the second electrode D4of the fourth transistor T4. The second electrode D1of the first transistor T1may extend in the second direction DR2and thus overlap the kthscan control line GCLk, a first light blocking layer BML1, a second initialization voltage line VIL2, and the shielding electrode SHE.

The second transistor T2may be connected (e.g., electrically connected) to a channel layer A2, a gate electrode G2, a first electrode S2, and the second electrode D2. The channel layer A2of the second transistor T2may overlap the gate electrode G2of the second transistor T2. The gate electrode G2of the second transistor T2may be disposed on the channel layer A2of the second transistor T2. The gate electrode G2of the second transistor T2may be integral with the kthscan control line GCLk. The gate electrode G2of the second transistor T2may be a portion of the kthscan control line GCLk.

The first electrode S2of the second transistor T2may be connected (e.g., electrically connected) to a second electrode D3of the third transistor T3. For example, the second electrode D2of the second transistor T2may be connected (e.g., electrically connected) to the second connection electrode BE2through the fourth contact hole CNT4. The second electrode D2of the second transistor T2may be connected (e.g., electrically connected) to the first connection electrode BE1through the second contact hole CNT2.

The third transistor T3may be connected (e.g., electrically connected) to a channel layer A3, a gate electrode G3, a first electrode S3, and the second electrode D3. The channel layer A3of the third transistor T3may overlap the gate electrode G3of the third transistor T3. The gate electrode G3of the third transistor T3may be disposed on the channel layer A3of the third transistor T3. The gate electrode G3of the third transistor T3may be integral with the kthscan initialization line GILk. The gate electrode G3of the third transistor T3may be a portion of the kthscan initialization line GILk.

The first electrode S3of the third transistor T3may be connected (e.g., electrically connected) to a fourth connection electrode BE4through a seventh contact hole CNT7. The fourth connection electrode BE4may be connected (e.g., electrically connected) to a first initialization voltage line VIL1through an eighth contact hole CNT8. The second electrode D3of the third transistor T3may be connected (e.g., electrically connected) to the second electrode D2of the second transistor T2.

The fourth transistor T4may be connected (e.g., electrically connected) to a channel layer A4, a gate electrode G4, a first electrode S4, and the second electrode D4. The channel layer A4of the fourth transistor T4may overlap the gate electrode G4of the fourth transistor T4. The gate electrode G4of the fourth transistor T4may be disposed on the channel layer A4of the fourth transistor T4. The gate electrode G4of the fourth transistor T4may be integral with the kthemission control line EMLk. The gate electrode G4of the fourth transistor T4may be a portion of the kthemission control line EMLk.

The first electrode S4of the fourth transistor T4may be connected (e.g., electrically connected) to the shielding electrode SHE through a ninth contact hole CNT9. The shielding electrode SHE may be connected (e.g., electrically connected) to the driving voltage line VDL through a fourteenth contact hole CNT14. The second electrode D4of the fourth transistor T4may be connected (e.g., electrically connected) to the first electrode DTS of the driving transistor DT and the first electrode S1of the first transistor T1.

The fifth transistor T5may be connected (e.g., electrically connected) to a channel layer A5, a gate electrode G5, a first electrode S5, and a second electrode D5. The channel layer A5of the fifth transistor T5may overlap the gate electrode G5of the fifth transistor T5. The gate electrode G5of the fifth transistor T5may be disposed on the channel layer A5of the fifth transistor T5. The gate electrode G5of the fifth transistor T5may be integral with the kthemission control line EMLk. The gate electrode G5of the fifth transistor T5may be a portion of the kthemission control line EMLk.

The first electrode S5of the fifth transistor T5may be connected (e.g., electrically connected) to the second connection electrode BE2through the third contact hole CNT3. The second electrode D5of the fifth transistor T5may be connected (e.g., electrically connected) to a fifth connection electrode BE5through an eleventh contact hole CNT11. The fifth connection electrode BE5may be connected (e.g., electrically connected) to the first anode connection electrode ANDE1through a twelfth contact hole CNT12. A first electrode of a light emitting element EL may be connected (e.g., electrically connected) to the first anode connection electrode ANDE1through a first anode contact hole CNTA1.

The sixth transistor T6may be connected (e.g., electrically connected) to a channel layer A6, a gate electrode G6, a first electrode S6, and a second electrode D6. The channel layer A6of the sixth transistor T6may overlap the gate electrode G6of the sixth transistor T6. The gate electrode G6of the sixth transistor T6may be disposed on the channel layer A6of the sixth transistor T6. The gate electrode G6of the sixth transistor T6may be integral with a (k−1)thscan write line. The gate electrode G6of the sixth transistor T6may be a portion of the (k−1)thscan write line.

The first electrode S6of the sixth transistor T6may be connected (e.g., electrically connected) to the second initialization voltage line VIL2through a thirteenth contact hole CNT13. The first electrode S6of the sixth transistor T6may overlap the kthscan initialization line GILk. The second electrode D6of the sixth transistor T6may be connected (e.g., electrically connected) to the second initialization voltage line VIL2through the thirteenth contact hole CNT13.

The first capacitor Cst may include the first capacitor electrode CE11and the second capacitor electrode CE12. The first capacitor electrode CE11may be a portion of the gate electrode DTG of the driving transistor DT and may correspond to a region of the gate electrode DTG of the driving transistor DT which overlaps the second capacitor electrode CE12of the first capacitor Cst. The second capacitor electrode CE12may overlap the first capacitor electrode CE11of the first capacitor Cst. The second capacitor electrode CE12may be connected (e.g., electrically connected) to the shielding electrode SHE through a tenth contact hole CNT10.

For example, the arrangement relationship of the sensing driver PSDU will be described.

The first sensing transistor LT1may be connected (e.g., electrically connected) to a channel layer LA1, a gate electrode LG1, a first electrode LS1, and a second electrode LD1. The channel layer LA1of the first sensing transistor LT1may overlap the gate electrode LG1of the first sensing transistor LT1. The gate electrode LG1of the first sensing transistor LT1may be disposed on the channel layer LA1of the first sensing transistor LT1.

The gate electrode LG1of the first sensing transistor LT1may be connected (e.g., electrically connected) to a first sensing connection electrode LBE1through a first sensing contact hole LCT1. The first sensing connection electrode LBE1may be connected (e.g., electrically connected) to a first electrode LS2of the second sensing transistor LT2through a second sensing contact hole LCT2. The first sensing connection electrode LBE1may be connected to the second anode connection electrode ANDE2through a fifth sensing contact hole LCT5. A first electrode of a light sensing element PD may be connected (e.g., electrically connected) to the second anode connection electrode ANDE2through a second anode contact hole CNTA2. The gate electrode LG1of the first sensing transistor LT1, the first sensing connection electrode LBE1, and the second anode connection electrode ANDE2may sequentially overlap in the thickness direction of a substrate.

The gate electrode LG1of the first sensing transistor LT1may be adjacent to the jthdata line DLj. The shielding electrode SHE may be disposed outside (or around) a side of the gate electrode LG1of the first sensing transistor LT1, e.g., in plan view. At least a portion of the shielding electrode SHE may be disposed between the gate electrode LG1of the first sensing transistor LT1and the jthdata line DLj. The shielding electrode SHE may be connected (e.g., electrically connected) to the driving voltage line VDL through the fourteenth contact hole CNT14and may be connected (e.g., electrically connected) to the first electrode S4of the fourth transistor T4through the ninth contact hole CNT9. The shielding electrode SHE may be connected (e.g., electrically connected) to the second capacitor electrode CE12through the tenth contact hole CNT10.

Since the shielding electrode SHE is connected (e.g., electrically connected) to the driving voltage line VDL, a driving voltage ELVDD of a certain level may be applied to the shielding electrode SHE. The shielding electrode SHE may be disposed outside (or around) a side of the gate electrode LG1of the first sensing transistor LT1(e.g., in plan view) to minimize the formation of a parasitic capacitor between the jthdata line DLj and the gate electrode LG1. This will be described in more detail with reference toFIGS.10and11.

The first electrode LS1of the first sensing transistor LT1may be connected (e.g., electrically connected) to the second initialization voltage line VIL2through a seventh sensing contact hole LCT7. The first electrode LS1of the first sensing transistor LT1may extend in the second direction DR2.

The second electrode LD1of the first sensing transistor LT1may be connected (e.g., electrically connected) to a first electrode LS3of the third sensing transistor LT3.

The second sensing transistor LT2may be connected (e.g., electrically connected) to a channel layer LA2, a gate electrode LG2, the first electrode LS2, and a second electrode LD2. The channel layer LA2of the second sensing transistor LT2may overlap the gate electrode LG2of the second sensing transistor LT2. The gate electrode LG2of the second sensing transistor LT2may be disposed on the channel layer LA2of the second sensing transistor LT2. The gate electrode LG2of the second sensing transistor LT2may be integral with the kthreset control line RSTLk. The gate electrode LG2of the second sensing transistor LT2may be a portion of the kthreset control line RSTLk.

The first electrode LS2of the second sensing transistor LT2may be connected (e.g., electrically connected) to a reset voltage line VRL through a third sensing contact hole LCT3. The second electrode LD2of the second sensing transistor LT2may be connected (e.g., electrically connected) to the first sensing connection electrode LBE1through the second sensing contact hole LCT2. The second electrode LD2of the second sensing transistor LT2may overlap a portion of the shielding electrode SHE disposed in the first direction DR1.

The third sensing transistor LT3may be connected (e.g., electrically connected) to a channel layer LA3, a gate electrode LG3, the first electrode LS3, and a second electrode LD3. The channel layer LA3of the third sensing transistor LT3may overlap the gate electrode LG3of the third sensing transistor LT3. The gate electrode LG3of the third sensing transistor LT3may be disposed on the channel layer LA3of the third sensing transistor LT3. The gate electrode LG3of the third sensing transistor LT3may be integral with the kthscan write line GWLk. The gate electrode LG3of the third sensing transistor LT3may be a portion of the kthscan write line GWLk. The third sensing transistor LT3may overlap the kthscan write line GWLk twice to form a dual gate.

The first electrode LS3of the third sensing transistor LT3may be connected (e.g., electrically connected) to the second electrode LD1of the first sensing transistor LT1. The second electrode LD3of the third sensing transistor LT3may be connected (e.g., electrically connected) to a second sensing connection electrode LBE2through a fourth sensing contact hole LCT4. The second sensing connection electrode LBE2may be connected (e.g., electrically connected) to the qthreadout line ROLq through a sixth sensing contact hole LCT6.

A second pixel driver PDU2, a third pixel driver PDU3, and a fourth pixel driver PDU4are substantially the same as the first pixel driver PDU1described with reference toFIGS.8and9and thus will not be described for descriptive convenience.

FIG.10is a schematic layout view illustrating a first pixel driver PDU1, a sensing driver PSDU, and a third pixel driver PDU3adjacent to the first pixel driver PDU1and the sensing driver PSDU according to an embodiment.FIG.11is a schematic enlarged layout view of a shielding electrode SHE ofFIG.10.

The arrangement relationship between the shielding electrode SHE, the first pixel driver PDU1, the sensing driver PSDU, and the third pixel driver PDU3adjacent to the first pixel driver PDU1and the sensing driver PSDU will be described with reference toFIGS.10and11. The third pixel driver PDU3may further include a (j−1)thdata line DLj−1 and a driving voltage line VDL extending in the second direction DR2. A qthreadout line ROLq may be disposed between a gate electrode LG1of a first sensing transistor LT1and a jthdata line DLj and may not be disposed between the gate electrode LG1of the first sensing transistor LT1and the (j−1)thdata line DLj−1.

The shielding electrode SHE may include a first shielding portion SHEa, a second shielding portion SHEb, a third shielding portion SHEc, a fourth shielding portion SHEd, and a fifth shielding portion SHEe connected (e.g., electrically connected) to each other. The first shielding portion SHEa may extend in the second direction DR2, and the second shielding portion SHEb may extend in the second direction DR2and may be spaced apart from the first shielding portion SHEa. The third shielding portion SHEc may be connected to the first shielding portion SHEa, and the fourth shielding portion SHEd may be connected (e.g., electrically connected) to the second shielding portion SHEb. The fifth shielding portion SHEe may extend in the first direction DR1and may connect the third shielding portion SHEc and the fourth shielding portion SHEd.

The area (or size) of the first shielding portion SHEa and the area (or size) of the second shielding portion SHEb may be substantially the same as each other. The area (or size) of the third shielding portion SHEc and the area (or size) of the fourth shielding portion SHEd may be substantially the same as each other. A width of the first shielding portion SHEa in the first direction DR1and a width of the second shielding portion SHEb in the first direction DR1may be substantially the same as each other. A width of the third shielding portion SHEc in the first direction DR1and a width of the fourth shielding portion SHEd in the first direction DR1may be substantially the same as each other. The width of the first shielding portion SHEa or the second shielding portion SHEb in the first direction DR1may be smaller than the width of the third shielding portion SHEc or the fourth shielding portion SHEd in the first direction DR1. A length of the fifth shielding portion SHEe in the first direction DR1may be greater than the width of the first shielding portion SHEa or the second shielding portion SHEb in the first direction DR1.

The first shielding portion SHEa, the second shielding portion SHEb, the third shielding portion SHEc, the fourth shielding portion SHEd, and the fifth shielding portion SHEe may be disposed outside (or around) a side (e.g., a right side) of the gate electrode LG1of the first sensing transistor LT1, e.g., in plan view. For example, the first shielding portion SHEa and the third shielding portion SHEc may be disposed outside (or around) a side of the gate electrode LG1of the first sensing transistor LT1in the first direction DR1, e.g., in plan view. The second shielding portion SHEb and the fourth shielding portion SHEd may be disposed outside (or around) another side (e.g., a left side) of the gate electrode LG1of the first sensing transistor LT1in the first direction DR1, e.g., in plan view. The fifth shielding portion SHEe may be disposed outside (or around) a side of the gate electrode LG1of the first sensing transistor LT1in the second direction DR2, e.g., in plan view. The first shielding portion SHEa, the second shielding portion SHEb, the third shielding portion SHEc, the fourth shielding portion SHEd, and the fifth shielding portion SHEe may surround three sides of the gate electrode LG1of the first sensing transistor LT1. Accordingly, the gate electrode LG1of the first sensing transistor LT1may be protected from voltage changes of adjacent signal lines.

A length of the shielding electrode SHE in the second direction DR2may be greater than a length of the gate electrode LG1of the first sensing transistor LT1in the second direction DR2. For example, the sum of lengths of the first shielding portion SHEa and the third shielding portion SHEc in the second direction DR2may be greater than the length of the gate electrode LG1of the first sensing transistor LT1in the second direction DR2. The sum of lengths of the second shielding portion SHEb and the fourth shielding portion SHEd in the second direction DR2may be greater than the length of the gate electrode LG1of the first sensing transistor LT1in the second direction DR2.

A length of the shielding electrode SHE in the first direction DR1may be greater than a length of the gate electrode LG1of the first sensing transistor LT1in the first direction DR1. For example, the length of the fifth shielding portion SHEe in the first direction DR1may be greater than the length of the gate electrode LG1of the first sensing transistor LT1in the first direction DR1.

The shielding electrode SHE may be disposed between the gate electrode LG1of the first sensing transistor LT1and a signal line or may overlap the signal line. In an embodiment, the signal line may be the jthdata line DLj or the (j−1)thdata line DLj−1.

For example, the first shielding portion SHEa may be disposed between the gate electrode LG1of the first sensing transistor LT1and the jthdata line DLj, the second shielding portion SHEb may be disposed between the gate electrode LG1of the first sensing transistor LT1and the (j−1)thdata line DLj−1, the third shielding portion SHEc may overlap the jthdata line DLj, and the fourth shielding portion SHEd may overlap the (j−1)thdata line DLj−1. The fifth shielding portion SHEe may overlap a channel layer LA2of a second sensing transistor LT2.

A portion of each of the first shielding portion SHEa, the third shielding portion SHEc, and the fifth shielding portion SHEe may overlap the qthreadout line ROLq.

The shielding electrode SHE may shield a voltage change of a first sensing connection electrode LBE1connected (e.g., electrically connected) to the gate electrode LG1and may shield a voltage change of a second anode connection electrode ANDE2connected (e.g., electrically connected) to the first sensing connection electrode LBE1. For example, the shielding electrode SHE may be disposed outside (or around) a side of the first sensing connection electrode LBE1or may be disposed outside (or around) a side of the second anode connection electrode ANDE2. The shielding electrode SHE may be disposed between the first sensing connection electrode LBE1and a signal line or may overlap the signal line. The shielding electrode SHE may be disposed between the second anode connection electrode ANDE2and a signal line or may overlap the signal line. In an embodiment, the signal line may be the jthdata line DLj or the (j−1)thdata line DLj−1.

The display device1according to an embodiment may include the shielding electrode SHE disposed between the gate electrode LG1of the first sensing transistor LT1and a signal line adjacent to the gate electrode LG1of the first sensing transistor LT1or overlapping the signal line. Since a voltage (e.g., the driving voltage ELVDD) is applied to the shielding electrode SHE, a parasitic capacitor formed between the gate electrode LG1of the first sensing transistor LT1and the signal line adjacent to the gate electrode LG1of the first sensing transistor LT1may be prevented or minimized. Accordingly, the voltage change of the gate electrode LG1of the first sensing transistor LT1, which is caused by a change in a signal transmitted through the signal line, may be prevented or minimized. For example, since the voltage of the gate electrode LG1is maintained constant during the light exposure period EP in which the first sensing transistor LT1is turned off, a leakage current of the first sensing transistor LT1may be prevented, and the generation of a noise signal that reduces the accuracy of the fingerprint reading operation may be prevented.

In the description, the shielding electrode SHE may be disposed between the jthdata line DLj and the (j−1)thdata line DLj−1 adjacent to the gate electrode LG1of the first sensing transistor LT1to shield, prevent, or minimize data voltage changes. However, embodiments are not limited thereto, and the shielding electrode SHE may be disposed at various positions to shield areas between various signal lines in which voltage changes exist and the gate electrode LG1. For example, the shielding electrode SHE may shield an area between a kthscan control line GCLk and the gate electrode LG1or an area between a kthemission control line EMLk and the gate electrode LG1. For example, at least a portion of the shielding electrode SHE, which extends in the first direction DR1, may be disposed between the kthscan control line GCLk and the gate electrode LG1or may be disposed between the kthemission control line EMLk and the gate electrode LG1.

FIG.12is an example of a schematic cross-sectional view taken along line A-A′ ofFIGS.8and9.FIG.13is an example of a schematic cross-sectional view taken along lines B-B′ and C-C′ ofFIGS.8and9.FIG.14is an example of a schematic cross-sectional view taken along line D-D′ ofFIGS.8and9.FIG.15is an example of a schematic cross-sectional view taken along line E-E′ ofFIGS.8and9.FIG.16is an example of a schematic cross-sectional view taken along line F-F′ ofFIGS.8and9.FIG.17is an example of a schematic cross-sectional view taken along lines G-G′ and H-H′ ofFIG.10.

Referring toFIGS.12through17, a thin-film transistor layer, a light emitting element layer, and an encapsulation layer TFE may be sequentially formed on a substrate SUB.

The thin-film transistor layer may be a layer in which the driving transistor DT, the first through sixth transistors T1through T6and the first capacitor Cst of each of the pixel drivers PDU1through PDU4and the first through third sensing transistors LT1through LT3of the sensing driver PSDU1are formed. The thin-film transistor layer may include a first active layer ACT1, a second active layer ACT2, a first gate metal layer GTL1, a second gate metal layer GTL2, a third gate metal layer GTL3, a first data metal layer DTL1, a second data metal layer DTL2, a buffer layer BF, a first gate insulating layer131, a first interlayer insulating layer141, a second interlayer insulating layer142, a second gate insulating layer132, a third interlayer insulating layer143, a first organic layer160, and a second organic layer161.

The buffer layer BF may be disposed on a surface of the substrate SUB. The buffer layer BF may be formed on the surface of the substrate SUB to protect thin-film transistors and an organic light emitting layer172of the light emitting element layer from moisture introduced through the substrate SUB which is vulnerable to moisture penetration. The buffer layer BF may be formed as inorganic layers stacked alternately. For example, the buffer layer BF may be a multilayer in which one or more inorganic layers selected from a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. In another example, the buffer layer BF may be omitted.

The first active layer ACT1may be disposed on the buffer layer BF. The first active layer ACT1may include a silicon semiconductor such as polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, or amorphous silicon.

The first active layer ACT1may include the channel layer DTA, the first electrode DTS, and the second electrode DTD of the driving transistor DT. The channel layer DTA of the driving transistor DT may be a region overlapping the gate electrode DTG of the driving transistor DT in the third direction DR3which is the thickness direction of the substrate SUB. The first electrode DTS of the driving transistor DT may be disposed on a side of the channel layer DTA, and the second electrode DTD may be disposed on another side of the channel layer DTA. The first electrode DTS and the second electrode DTD of the driving transistor DT may be regions not overlapping the gate electrode DTG in the third direction DR3. The first electrode DTS and the second electrode DTD of the driving transistor DT may be regions formed to have conductivity by doping a silicon semiconductor with ions or impurities.

For example, the first active layer ACT1may further include the channel layers A1and A4through A6, the first electrodes S1and S4through S6, and the second electrodes D1and D4through D6of the first and fourth through sixth transistors T1and T4through T6. Each of the channel layers A1and A4through A6of the first and fourth through sixth transistors T1and T4through T6may overlap a corresponding gate electrode among the gate electrodes G1and G4through G6in the third direction DR3. The first electrodes S1and S4through S6and the second electrodes D1and D4through D6of the first and fourth through sixth transistors T1and T4through T6may be regions formed to have conductivity by doping a silicon semiconductor with ions or impurities.

The first gate insulating layer131may be disposed on the first active layer ACT1. The first gate insulating layer131may be made of an inorganic layer, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

The first gate metal layer GTL1may be disposed on the first gate insulating layer131. The first gate metal layer GTL1may include the gate electrode DTG of the driving transistor DT. For example, the first gate metal layer GTL1may include the gate electrodes G1and G4through G6of the first and fourth through sixth transistors T1and T4through T6and the gate electrodes LG1and LG3of the first and third sensing transistors LT1and LT3. For example, the first gate metal layer GTL1may further include the first capacitor electrode CE11, the kthscan write line GWLk, and the kthemission control line EMLk. The first gate metal layer GTL1may be a single layer or a multilayer made of any one or more selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

The first interlayer insulating layer141may be disposed on the first gate metal layer GTL1. The first interlayer insulating layer141may be made of an inorganic layer, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

The second gate metal layer GTL2may be disposed on the first interlayer insulating layer141. The second gate metal layer GTL2may include the second capacitor electrode CE12, first through third light blocking layers BML1through BML3, and the first initialization voltage line VIL1. The first through third light blocking layers BML1through BML3may prevent light incident from under the display panel10from entering the second active layer ACT2disposed on the light blocking layers BML1through BML3. The second gate metal layer GTL2and the first gate metal layer GTL1may include the same material described above.

The second interlayer insulating layer142may be disposed on the second gate metal layer GTL2. The second interlayer insulating layer142and the first interlayer insulating layer141may include the same material described above.

The second active layer ACT2may be disposed on the second interlayer insulating layer142. The second active layer ACT2may include an oxide semiconductor such as IGZO (indium (In), gallium (Ga), zinc (Zn) and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn) and oxygen (O)), or IGTO (indium (In), gallium (Ga), tin (Sn) and oxygen (O)).

The second active layer ACT2may include the channel layers A2and A3, the first electrodes S2and S3, and the second electrodes D2and D3of the second and third transistors T2and T3. The channel layers A2and A3of the second and third transistors T2and T3may overlap the gate electrodes G2and G3in the third direction DR3, respectively. For example, the second active layer ACT2may include the channel layer LA2, the first electrode LS2, and the second electrode LD2of the second sensing transistor LT2. The channel layer LA2of the second sensing transistor LT2may overlap the gate electrode LG2in the third direction DR3.

The first electrodes S2and S3and the second electrodes D2and D3of the second and third transistors T2and T3and the first electrode LS2and the second electrode LD2of the second sensing transistor LT2may be regions formed to have conductivity by doping an oxide semiconductor with ions or impurities.

The second gate insulating layer132may be disposed on the second active layer ACT2. The second gate insulating layer132and the first gate insulating layer131may include the same material described above.

The third gate metal layer GTL3may be disposed on the second gate insulating layer132. The third gate metal layer GTL3may include the gate electrodes G2and G3of the second and third transistors T2and T3, the gate electrodes LG2and LG3of the second and third sensing transistors LT2and LT3, the kthscan initialization line GILk, the kthscan control line GCLk, and the kthreset control line RSTLk. The third gate metal layer GTL3and the first gate metal layer GTL1may include the same material described above.

The third interlayer insulating layer143may be disposed on the third gate metal layer GTL3. The third interlayer insulating layer143and the first interlayer insulating layer141may include the same material described above.

The first data metal layer DTL1may be formed on the third interlayer insulating layer143. The first data metal layer DTL1may include the second initialization voltage line VIL2, the reset voltage line VRL, the first through fifth connection electrodes BE1through BE5, the first and second sensing connection electrodes LBE1and LBE2, and the shielding electrode SHE. The first data metal layer DTL1may be a single layer or a multilayer made of any one or more selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

The first organic layer160may be formed on the first data metal layer DTL1to flatten steps (or to compensate the step differences) formed by the first active layer ACT1, the second active layer ACT2, the first gate metal layer GTL1, the second gate metal layer GTL2, the third gate metal layer GTL3, and the first data metal layer DTL1. The first organic layer160may be made of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

The second data metal layer DTL2may be formed on the first organic layer160. The second data metal layer DTL2may include the first anode connection electrode ANDE1, the second anode connection electrode ANDE2, the driving voltage line VDL, the jthdata line DLj, and the qthreadout line ROLq. The second data metal layer DTL2may be a single layer or a multilayer made of any one or more selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

The second organic layer161may be formed on the second data metal layer DTL2to flatten steps (or to compensate the step differences). The second organic layer161may be made of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

The first contact hole CNT1may be a hole penetrating the first interlayer insulating layer141, the second interlayer insulating layer142, the second gate insulating layer132, and the third interlayer insulating layer143to expose the gate electrode DTG of the driving transistor DT. The second contact hole CNT2may be a hole penetrating the second gate insulating layer132and the third interlayer insulating layer143to expose the second electrode D2of the second transistor T2. The first connection electrode BE1may be connected (e.g., electrically connected) to the gate electrode DTG of the driving transistor DT through the first contact hole CNT1and may be connected (e.g., electrically connected) to the second electrode D2of the second transistor T2through the second contact hole CNT2.

The third contact hole CNT3may be a hole penetrating the first gate insulating layer131, the first interlayer insulating layer141, the second interlayer insulating layer142, the second gate insulating layer132, and the third interlayer insulating layer143to expose the second electrode DTD of the driving transistor DT. The fourth contact hole CNT4may be a hole penetrating the second gate insulating layer132and the third interlayer insulating layer143to expose the second electrode D2of the second transistor T2. The second connection electrode BE2may be connected (e.g., electrically connected) to the second electrode DTD of the driving transistor DT through the third contact hole CNT3and may be connected (e.g., electrically connected) to the second electrode D2of the second transistor T2through the fourth contact hole CNT4.

The fifth contact hole CNT5may be a hole penetrating the first gate insulating layer131, the first interlayer insulating layer141, the second interlayer insulating layer142, the second gate insulating layer132, and the third interlayer insulating layer143to expose the first electrode S1of the first transistor T1. The sixth contact hole CNT6may be a hole penetrating the first organic layer160to expose the third connection electrode BE3. The third connection electrode BE3may be connected (e.g., electrically connected) to the first electrode S1of the first transistor T1through the fifth contact hole CNT5, and the jthdata line DLj may be connected (e.g., electrically connected) to the third connection electrode BE3through the sixth contact hole CNT6.

The seventh contact hole CNT7may be a hole penetrating the second gate insulating layer132and the third interlayer insulating layer143to expose the first electrode S3of the third transistor T3. The eighth contact hole CNT8may be a hole penetrating the second interlayer insulating layer142, the second gate insulating layer132, and the third interlayer insulating layer143to expose the first initialization voltage line VIL1. The fourth connection electrode BE4may be connected (e.g., electrically connected) to the first electrode S3of the third transistor T3through the seventh contact hole CNT7and may be connected (e.g., electrically connected) to the first initialization voltage line VIL1through the eighth contact hole CNT8.

The ninth contact hole CNT9may be a hole penetrating the first gate insulating layer131, the first interlayer insulating layer141, the second interlayer insulating layer142, the second gate insulating layer132, and the third interlayer insulating layer143to expose the first electrode S4of the fourth transistor T4. The fourteenth contact hole CNT14may be a hole penetrating the first organic layer160to expose the shielding electrode SHE. The shielding electrode SHE may be connected (e.g., electrically connected) to the first electrode S4of the fourth transistor T4through the ninth contact hole CNT9, and the driving voltage line VDL may be connected (e.g., electrically connected) to the shielding electrode SHE through the fourteenth contact hole CNT14. For example, the shielding electrode SHE may connect (e.g., electrically connect) the first electrode S4of the fourth transistor T4and the driving voltage line VDL.

The eleventh contact hole CNT11may be a hole penetrating the first gate insulating layer131, the first interlayer insulating layer141, the second interlayer insulating layer142, the second gate insulating layer132, and the third interlayer insulating layer143to expose the second electrode D5of the fifth transistor T5. The twelfth contact hole CNT12may be a hole penetrating the first organic layer160to expose the fifth connection electrode BE5. The fifth connection electrode BE5may be connected (e.g., electrically connected) to the second electrode D5of the fifth transistor T5through the eleventh contact hole CNT11, and the first anode connection electrode ANDE1may be connected (e.g., electrically connected) to the fifth connection electrode BE5through the twelfth contact hole CNT12.

The thirteenth contact hole CNT13may be a hole penetrating the first gate insulating layer131, the first interlayer insulating layer141, the second interlayer insulating layer142, the second gate insulating layer132, and the third interlayer insulating layer143to expose the second electrode D6of the sixth transistor T6. The second initialization voltage line VIL2may be connected (e.g., electrically connected) to the second electrode D6of the sixth transistor T6through the thirteenth contact hole CNT13.

The tenth contact hole CNT10may be a hole penetrating the second interlayer insulating layer142, the second gate insulating layer132, and the third interlayer insulating layer143to expose the second capacitor electrode CE12. The shielding electrode SHE may be connected (e.g., electrically connected) to the second capacitor electrode CE12through the tenth contact hole CNT10.

The first sensing contact hole LCT1may be a hole penetrating the first interlayer insulating layer141, the second interlayer insulating layer142, the second gate insulating layer132, and the third interlayer insulating layer143to expose the gate electrode LG1of the first sensing transistor LT1. The second sensing contact hole LCT2may be a hole penetrating the second gate insulating layer132and the third interlayer insulating layer143to expose the second electrode LD2of the second sensing transistor LT2. The first sensing connection electrode LBE1may be connected (e.g., electrically connected) to the gate electrode LG1of the first sensing transistor LT1through the first sensing contact hole LCT1and may be connected (e.g., electrically connected) to the second electrode LD2of the second sensing transistor LT2through the second sensing contact hole LCT2.

The third sensing contact hole LCT3may be a hole penetrating the second gate insulating layer132and the third interlayer insulating layer143to expose the first electrode LS2of the second sensing transistor LT2. The reset voltage line VRL may be connected (e.g., electrically connected) to the first electrode LS2of the second sensing transistor LT2through the third sensing contact hole LCT3.

The fourth sensing contact hole LCT4may be a hole penetrating the first gate insulating layer131, the first interlayer insulating layer141, the second interlayer insulating layer142, the second gate insulating layer132, and the third interlayer insulating layer143to expose the second electrode LD3of the third sensing transistor LT3. The second sensing connection electrode LBE2may be connected (e.g., electrically connected) to the second electrode LD3of the third sensing transistor LT3through the fourth sensing contact hole LCT4.

The fifth sensing contact hole LCT5may be a hole penetrating the first organic layer160to expose the first sensing connection electrode LBE1. The second anode connection electrode ANDE2may be connected (e.g., electrically connected) to the first sensing connection electrode LBE1through the fifth sensing contact hole LCT5.

The sixth sensing contact hole LCT6may be a hole penetrating the first organic layer160to expose the second sensing connection electrode LBE2. The qthreadout line ROLq may be connected (e.g., electrically connected) to the second sensing connection electrode LBE2through the sixth sensing contact hole LCT6.

The seventh sensing contact hole LCT7may be a hole penetrating the first gate insulating layer131, the first interlayer insulating layer141, the second interlayer insulating layer142, the second gate insulating layer132, and the third interlayer insulating layer143to expose the first electrode LS1of the first sensing transistor LT1. The second initialization voltage line VIL2may be connected (e.g., electrically connected) to the first electrode LS1of the first sensing transistor LT1through the seventh sensing contact hole LCT7.

The light emitting element layer may be formed on the thin-film transistor layer. The light emitting element layer may include light emitting elements EL, light sensing elements PD, and a bank180. The light emitting element layer may be disposed on the second organic layer161.

Each of the light emitting elements EL may include a pixel electrode171, an organic light emitting layer172, and a common electrode173. Each of the light sensing elements PD may include a first electrode175, a photoelectric conversion layer174, and the common electrode173. The light emitting elements EL and the light sensing elements PD may share the common electrode173.

The respective pixel electrodes171of the light emitting elements EL and the respective first electrodes175of the light sensing elements PD may be formed on the second organic layer161. The pixel electrode171of each of the light emitting elements EL may be connected (e.g., electrically connected) to the first anode connection electrode ANDE1through the first anode contact hole CNTA1penetrating the first organic layer160. The first electrode175of each of the light sensing elements PD may be connected (e.g., electrically connected) to the second anode connection electrode ANDE2through the second anode contact hole CNTA2penetrating the second organic layer161.

The pixel electrode171of each of the light emitting elements EL may have a single-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu) or aluminum (Al) or a stacked layer structure, for example, a multilayer structure of ITO/Mg, ITO/MgF, ITO/Ag, or ITO/Ag/ITO including indium-tin-oxide (ITO), indium-zinc-oxide (IZO), zinc oxide (ZnO) or indium oxide (In2O3) and silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au) or nickel (Ni). However, embodiments are not limited thereto.

The first electrode175of each of the light sensing elements PD may have a single-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu) or aluminum (Al) or a multilayer structure of ITO/Mg, ITO/MgF, ITO/Ag or ITO/Ag/ITO. However, embodiments are not limited thereto.

The bank180may be formed on the second organic layer161to define the light emitting portions ELU1through ELU4of the pixels PX1through PX4and the light sensing portions PSU of the light sensors PS. The bank180may separate (or define) the light emitting portions ELU1through ELU4and the light sensing portions PSU. Each of the light emitting portions ELU1through ELU4may be an area in which the pixel electrode171, the organic light emitting layer172, and the common electrode173are sequentially stacked so that holes from the pixel electrode171and electrons from the common electrode173are recombined in the organic light emitting layer172to emit light. Each of the light sensing portions PSU may be an area in which the first electrode175, the photoelectric conversion layer174, and the common electrode173are sequentially stacked to convert light incident from the outside into an electrical signal.

The bank180may cover edges of the pixel electrode171of each of the light emitting elements EL and the first electrode175of each of the light sensing elements PD. The bank180may be made of an organic layer such as acryl resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

The organic light emitting layer172may be formed on the pixel electrode171of each of the light emitting elements EL. The organic light emitting layer172may include an organic material to emit light of a color. For example, the organic light emitting layer172may include a hole transporting layer, an organic material layer, and an electron transporting layer. The organic light emitting layer172of the first light emitting portion ELU1may emit first light, and the organic light emitting layer172of the second light emitting portion ELU2may emit second light. The organic light emitting layer172of the third light emitting portion ELU3may emit third light, and the organic light emitting layer172of the fourth light emitting portion ELU4may emit the second light.

The photoelectric conversion layer174may be formed on the first electrode175of each of the light sensing elements PD. The photoelectric conversion layer174may generate photocharges in proportion to incident light. The incident light may be light transmitted to the photoelectric conversion layer174after being emitted from the organic light emitting layer172and reflected or may be light provided from the outside regardless of the organic light emitting layer172. Charges generated and accumulated in the photoelectric conversion layer174may be converted into electrical signals required for a light sensing operation.

The photoelectric conversion layer174may include an electron donor material and an electron acceptor material. The electron donor material may generate donor ions in response to light, and the electron acceptor material may generate acceptor ions in response to light. In case that the photoelectric conversion layer174is made of an organic material, the electron donor material may include a compound such as sub-phthalocyanine (SubPc) or di-butyl-phosphate (DBP). However, embodiments are not limited thereto. The electron acceptor material may include a compound such as fullerene, a fullerene derivative, or perylene diimide. However, embodiments are not limited thereto.

In another example, in case that the photoelectric conversion layer174is made of an inorganic material, the light sensing element PD may be a pn-type or pin-type phototransistor. For example, the photoelectric conversion layer174may have a structure in which an N-type semiconductor layer, an I-type semiconductor layer, and a P-type semiconductor layer are sequentially stacked.

The common electrode173may be disposed on the organic light emitting layer172, the photoelectric conversion layer174, and the bank180. The common electrode173may cover the organic light emitting layer172and the photoelectric conversion layer174. The common electrode173may be formed in common to overlap the light emitting portions ELU1through ELU4and the light sensing portions PSU. The common electrode173may include a conductive material having a low work function, such as Li, Ca, LiF/Ca, LiF/Al, Al, Mg, Ag, Pt, Pd, Ni, Au Nd, Ir, Cr, BaF, Ba, or a compound or mixture thereof (e.g., a mixture of Ag and Mg). In another example, the common electrode173may include a transparent metal oxide such as indium-tin-oxide (ITO), indium-zinc-oxide (IZO), or zinc oxide (ZnO).

The encapsulation layer TFE may be formed on the light emitting element layer. The encapsulation layer TFE may include at least one inorganic layer to prevent penetration of oxygen or moisture into the light emitting element layer. For example, the encapsulation layer TFE may include at least one organic layer to protect the light emitting element layer from foreign substances such as dust.

Referring toFIG.17, according to an embodiment, the first shielding portion SHEa of the shielding electrode SHE may be disposed between the jthdata line DLj and the gate electrode LG1of the first sensing transistor LT1, e.g., in plan view or in a diagonal direction between a horizontal direction (e.g., the first or second direction DR1or DR2) and a vertical direction (e.g., the third direction DR3). Accordingly, the first shielding portion SHEa may prevent the formation of parasitic capacitance between the jthdata line DLj and the gate electrode LG1of the first sensing transistor LT1.

The second shielding portion SHEb of the shielding electrode SHE may be disposed between the (j−1)thdata line DLj−1 and the gate electrode LG1of the first sensing transistor LT1, e.g., in plan view or in a diagonal direction between a horizontal direction (e.g., the first or second direction DR1or DR2) and a vertical direction (e.g., the third direction DR3). Accordingly, the second shielding portion SHEb may prevent the formation of parasitic capacitance between the (j−1)thdata line DLj−1 and the gate electrode LG1of the first sensing transistor LT1.

The third shielding portion SHEc of the shielding electrode SHE may be disposed between the jthdata line DLj and the first sensing connection electrode LBE1and may partially overlap the jthdata line DLj, e.g., in plan view or in a diagonal direction between a horizontal direction (e.g., the first or second direction DR1or DR2) and a vertical direction (e.g., the third direction DR3). Accordingly, the third shielding portion SHEc may prevent the formation of parasitic capacitance between the jthdata line DLj and the first sensing connection electrode LBE1.

The fourth shielding portion SHEd of the shielding electrode SHE may be disposed between the (j−1)thdata line DLj−1 and the first sensing connection electrode LBE1and may partially overlap the (j−1)thdata line DLj−1, e.g., in plan view or in a diagonal direction between a horizontal direction (e.g., the first or second direction DR1or DR2) and a vertical direction (e.g., the third direction DR3). Accordingly, the fourth shielding portion SHEd may prevent the formation of parasitic capacitance between the (j−1)thdata line DLj−1 and the first sensing connection electrode LBE1.

The qthreadout line ROLq may be disposed outside (or around) a right side of each of the gate electrode LG1of the first sensing transistor LT1, the first sensing connection electrode LBE1, and the second anode connection electrode ANDE2, e.g., in plan view. The qthreadout line ROLq may be a direct current (DC) line to which a sensing signal is not transmitted during a period other than the fingerprint reading period ROP (seeFIGS.7A and7B). For example, the qthreadout line ROLq may be disposed between the gate electrode LG1of the first sensing transistor LT1and the jthdata line DLj, between the first sensing connection electrode LBE1and the jthdata line DLj, and between the second anode connection electrode ANDE2and the jthdata line DLj to prevent the formation of parasitic capacitance between them.

Accordingly, the voltage change of the gate electrode LG1of the first sensing transistor LT1, which is caused by the change in data signals transmitted through the data lines DLj and DLj−1 adjacent to the gate electrode LG1of the first sensing transistor LT1, may be prevented or minimized. Therefore, since the voltage of the gate electrode LG1is maintained constant during the light exposure period EP, a leakage current of the first sensing transistor LT1may be prevented or minimized, and the noise signal that causes the degradation of the accuracy of the fingerprint reading operation may be prevented or minimized.

A display device1according to an embodiment will now be described with reference toFIGS.18through20.

FIG.18is a schematic layout view illustrating a first active layer, a first gate metal layer, a second gate metal layer, a second active layer, a third gate metal layer, a first data layer and a second data layer of a first pixel driver PDU1, a sensing driver PSDU, and a third pixel driver PDU3adjacent to the first pixel driver PDU1and the sensing driver PSDU according to an embodiment.FIG.19is an example of a schematic cross-sectional view taken along line I-I′ ofFIG.18.FIG.20is an example of a schematic cross-sectional view taken along lines J-J′ and K-K′ ofFIG.18.

The display device1ofFIG.18is different from the embodiments described above in that a reset voltage line further includes a second sub-reset voltage line VRL2extending in the second direction DR2in addition to a first sub-reset voltage line VRL1extending in the first direction DR1.

Referring toFIG.18, the first sub-reset voltage line VRL1may be disposed at substantially the same position as the reset voltage line of the embodiment ofFIGS.8through10. The first sub-reset voltage line VRL1may be disposed in a first data metal layer DTL1.

The second sub-reset voltage line VRL2may extend in the second direction DR2and may be disposed outside (or around) a left side of a gate electrode LG1of a first sensing transistor LT1, e.g., in plan view. The second sub-reset voltage line VRL2may be disposed between a (j−1)thdata line DLj−1 of the third pixel driver PDU3and the gate electrode LG1of the first sensing transistor LT1, e.g., in plan view or in a diagonal direction between a horizontal direction (e.g., the first or second direction DR1or DR2) and a vertical direction (e.g., the third direction DR3). The second sub-reset voltage line VRL2may overlap the first sub-reset voltage line VRL1, a kthreset control line RSTLk, a shielding electrode SHE, a kthemission control line EMLk, a kthscan control line GCLk, a second initialization voltage line VIL2, a kthscan initialization line GILk, and a first initialization voltage line VIL1.

For example, a qthreadout line ROLq may extend in the second direction DR2and may be disposed outside (or around) a right side of the gate electrode LG1of the first sensing transistor LT1, e.g., in plan view.

Referring toFIG.19, the second sub-reset voltage line VRL2may be disposed in a second data metal layer DTL2and may partially overlap a channel layer LA2of a second sensing transistor LT2. The second sub-reset voltage line VRL2may be connected (e.g., electrically connected) to the first sub-reset voltage line VRL1through an eighth sensing contact hole LCT8. The eighth sensing contact hole LCT8may be a hole penetrating a first organic layer160to expose the first sub-reset voltage line VRL1.

Referring toFIG.20, in the display device1according to an embodiment, the second sub-reset voltage line VRL2disposed between the (j−1)thdata line DLj−1 and the gate electrode LG1of the first sensing transistor LT1may prevent the formation of parasitic capacitance between the (j−1)thdata line DLj−1 and the gate electrode LG1of the first sensing transistor LT1.

The second data metal layer DTL2may include the (j−1)thdata line DLj−1, the second sub-reset voltage line VRL2, a second anode connection electrode ANDE2, the qthreadout line ROLq, and a jthdata line DLj sequentially disposed along a horizontal direction. The second sub-reset voltage line VRL2, a second shielding portion SHEb, and a fourth shielding portion SHEd may prevent the formation of parasitic capacitance between the (j−1)thdata line DLj−1 and the gate electrode LG1of the first sensing transistor LT1(or a first sensing connection electrode LBE1). The qthreadout line ROLq, a first shielding portion SHEa, and a third shielding portion SHEc may prevent the formation of parasitic capacitance between the jthdata line DLj and the gate electrode LG1of the first sensing transistor LT1(or the first sensing connection electrode LBE1). The gate electrode LG1of the first sensing transistor LT1(or the first sensing connection electrode LBE1) may be disposed between the second sub-reset voltage line VRL2and the qthreadout line ROLq and may be protected from its surrounding voltages.

Accordingly, the voltage change of the gate electrode LG1of the first sensing transistor LT1, which is caused by the change in data signals transmitted through the data lines DLj and DLj−1 adjacent to the gate electrode LG1of the first sensing transistor LT1, may be prevented or minimized. Therefore, since the voltage of the gate electrode LG1is maintained constant during a light exposure period EP, a leakage current of the first sensing transistor LT1may be prevented, and the noise signal that causes the degradation of the accuracy of the fingerprint reading operation may be prevented or minimized.

A display device1according to an embodiment will now be described with reference toFIGS.21through23.

FIG.21is a schematic layout view illustrating a first active layer, a first gate metal layer, a second gate metal layer, a second active layer, a third gate metal layer and a first data layer of a first pixel driver and a sensing driver according to an embodiment.FIG.22is a schematic layout view further illustrating a second data layer inFIG.21.FIG.23is an example of a schematic cross-sectional view taken along line L-L′ ofFIGS.21and22.

The display device1ofFIG.21is different from the embodiment ofFIGS.8through17in that a shielding electrode SHE′ includes a first shielding portion SHEa′ and a second shielding portion SHEb′ extending in the second direction DR2and a third shielding portion SHEe′ connecting them. The shielding electrode SHE′ may be connected (e.g., electrically connected) to a second initialization voltage line VIL2through the first shielding portion SHEa′ to receive a second initialization voltage VAINT.

The first shielding portion SHEa′ may extend in the second direction DR2and may be disposed outside (or around) a right side of a gate electrode LG1of a first sensing transistor LT1, e.g., in plan view. The first shielding portion SHEa′ may be disposed between the gate electrode LG1of the first sensing transistor LT1and a jthdata line DLj, e.g., in plan view or in a diagonal direction between a horizontal direction (e.g., the first or second direction DR1or DR2) and a vertical direction (e.g., the third direction DR3).

The second shielding portion SHEb′ may be spaced apart from the first shielding portion SHEa′ and may extend in the second direction DR2. The second shielding portion SHEb′ may be disposed outside (or around) a left side of the gate electrode LG1of the first sensing transistor LT1, e.g., in plan view. The second shielding portion SHEb′ may be disposed between the gate electrode LG1of the first sensing transistor LT1and a (j−1)thdata line DLj−1, e.g., in plan view or in a diagonal direction between a horizontal direction (e.g., the first or second direction DR1or DR2) and a vertical direction (e.g., the third direction DR3).

The third shielding portion SHEe′ may extend in the first direction DR1and may connect the first shielding portion SHEa′ and the second shielding portion SHEb′. The third shielding portion SHEe′ may be disposed outside (or around) the right side of the gate electrode LG1of the first sensing transistor LT1, e.g., in plan view. The third shielding portion SHEc′ may overlap a channel layer LA2of a second sensing transistor LT2.

The first shielding portion SHEa′, the second shielding portion SHEb′, and the third shielding portion SHEe′ may surround at least three sides of the gate electrode LG1of the first sensing transistor LT1, e.g., in plan view. The first shielding portion SHEa′, the second shielding portion SHEb′, and the third shielding portion SHEe′ may surround three sides of a first sensing connection electrode LBE1. A length of the first shielding portion SHEa′ or the second shielding portion SHEb′ in the second direction DR2may be greater than a length of the gate electrode LG1in the second direction DR2. The length of the first shielding portion SHEa′ or the second shielding portion SHEb′ in the second direction DR2may be greater than a length of the first sensing connection electrode LBE1in the second direction DR2.

The display device1according to an embodiment may further include a sixth connection electrode BE6. The sixth connection electrode BE6may be included in a first data metal layer DTL1. The sixth connection electrode BE6may connect (e.g., electrically connect) a first electrode S4of a fourth transistor T4and a second capacitor electrode CE12to a driving voltage line VDL.

A fifteenth contact hole CNT15may be a hole penetrating a first gate insulating layer131, a first interlayer insulating layer141, a second interlayer insulating layer142, a second gate insulating layer132, and a third interlayer insulating layer143to expose the first electrode S4of the fourth transistor T4. A sixteenth contact hole CNT16may be a hole penetrating the second interlayer insulating layer142, the second gate insulating layer132, and the third interlayer insulating layer143to expose the second capacitor electrode CE12. The sixth connection electrode BE6may be connected (e.g., electrically connected) to the first electrode S4of the fourth transistor T4through the fifteenth contact hole CNT15and may be connected (e.g., electrically connected) to the second capacitor electrode CE12through the sixteenth contact hole CNT16. The driving voltage line VDL may connect a seventeenth contact hole CNT17to the sixth connection electrode BE6.

According to an embodiment, the shielding electrode SHE′ may prevent the formation of parasitic capacitance between the gate electrode LG1of the first sensing transistor LT1and the data lines DLj and DLj−1 adjacent to the gate electrode LG1of the first sensing transistor LT1. Accordingly, the voltage change of the gate electrode LG1of the first sensing transistor LT1, which is caused by the change in data signals transmitted through the data lines DLj and DLj−1, may be prevented or minimized. Therefore, since the voltage of the gate electrode LG1is maintained constant during a light exposure period EP, a leakage current of the first sensing transistor LT1may be prevented or minimized, and the noise signal that causes the degradation of the accuracy of the fingerprint reading operation may be prevented or minimized.

A display device1according to an embodiment will now be described with reference toFIGS.24through27.

FIG.24is a schematic diagram of an equivalent circuit of a first pixel PX1and a light sensor PS according to an embodiment.FIG.25is a schematic layout view illustrating a first active layer, a first gate metal layer, a second gate metal layer, a second active layer, a third gate metal layer and a first data layer of a first pixel driver and a sensing driver ofFIG.24.FIG.26is a schematic layout view further illustrating a second data layer inFIG.25.FIG.27is an example of a schematic cross-sectional view taken along line M-M′ ofFIGS.25and26. The display device1ofFIG.24is different from the embodiment ofFIGS.8through17in that it further includes a second capacitor Cst2of the light sensor PS in addition to a first capacitor Cst1of the first pixel PX1. The first capacitor Cst1may be substantially the same as the first capacitors Cst of the embodiments described above.

The second capacitor Cst2may be formed between a second initialization voltage line VIL2and a gate electrode LG1of a first sensing transistor LT1. The second capacitor Cst2may include a first capacitor electrode CE21and a second capacitor electrode CE22. The first capacitor electrode CE21of the second capacitor Cst2may be connected (e.g., electrically connected) to the gate electrode LG1of the first sensing transistor LT1, and the second capacitor electrode CE22of the second capacitor Cst2may be connected (e.g., electrically connected) to the second initialization voltage line VIL2.

The first capacitor electrode CE21may be a portion of the gate electrode LG1of the first sensing transistor LT1and may correspond to a region of the gate electrode LG1of the first sensing transistor LT1which overlaps the second capacitor CE22of the second capacitor Cst2. The second capacitor electrode CE22may overlap the first capacitor electrode CE21of the second capacitor Cst2. The second capacitor electrode CE22may be a portion of the second initialization voltage line VIL2and may correspond to a region of the second initialization voltage line VIL2which overlaps the first capacitor electrode CE21of the second capacitor Cst2.

According to an embodiment, the second capacitor Cst2formed by the first capacitor electrode CE21and the second capacitor electrode CE22may prevent the voltage of the gate electrode LG1of the first sensing transistor LT1from being changed by a voltage change of an adjacent signal line.

Therefore, since the voltage of the gate electrode LG1of the first sensing transistor LT1is maintained constant, a leakage current of the first sensing transistor LT1may be prevented or minimized, and the noise signal that causes the degradation of the accuracy of the fingerprint reading operation may be prevented or minimized.

The above description is an example of technical features of the disclosure, and those skilled in the art to which the disclosure pertains will be able to make various modifications and variations. Therefore, the embodiments of the disclosure described above may be implemented separately or in combination with each other.

Therefore, the embodiments disclosed in the disclosure are not intended to limit the technical spirit of the disclosure, but to describe the technical spirit of the disclosure, and the scope of the technical spirit of the disclosure is not limited by these embodiments. The protection scope of the disclosure should be interpreted by the following claims, and it should be interpreted that all technical spirits within the equivalent scope are included in the scope of the disclosure.