Patent ID: 12199150

DETAILED DESCRIPTION OF THE EMBODIMENTS

The present invention is further described below with reference to the accompanying drawings.

FIG.1is an architecture diagram of a multi-level gate driver applied to the SiC MOSFET according to the present invention. To simulate a switching status of the SiC MOSFET in a half-bridge structure, an application circuit shown inFIG.1is used. The multi-level gate driver provided in the present invention drives a first SiC MOSFET M1. A parasitic diode of a second SiC MOSFET M2, as a freewheeling diode, is in a constant turn-on state. Main parasitic parameters of the SiC MOSFET are listed inFIG.1. When the first SiC MOSFET M1is turned on, a current on an inductor L flows into M1. When the first SiC MOSFET M1is turned off, a body diode of the second SiC MOSFET M2is freewheeled. A gate-source capacitance Cgs of the SiC MOSFET is a constant value, a drain-source capacitance Cds is reduced with the increase of voltages at two ends of the SiC MOSFET, and a gate-drain capacitance Cgd is reduced sharply with the increase of the voltages at two ends of the SiC MOSFET. InFIG.1, a parasitic inductor is introduced by encapsulation. At a turn-on stage, a drain-source capacitance Cds2of the second SiC MOSFET M2is reduced with the reduction of VSW. dVSW/dt depends on the drain-source capacitance Cds2of the second SiC MOSFET M2, a sum of a drain-source capacitance Cds1and a gate-drain capacitance Cgd1of the first SiC MOSFET M1, and a gate-source voltage Vgs1of the first SiC MOSFET. At a turn-off stage, an overshoot of VSWdepends on parasitic inductances LD2and LS2of the second SiC MOSFET M2. Similarly, dVSW/dt depends on the drain-source capacitance Cds2of the second SiC MOSFET M2, the sum of the drain-source capacitance Cds1and the gate-drain capacitance Cgd1of the first SiC MOSFET M1, and the gate-source voltage of the first SiC MOSFET. By adjusting a driving current, the gate-source voltage Vgs1of the first SiC MOSFET is controlled, and then dVSW/dt, dIds/dt, and overshoot current and voltage are controlled. A change rate of a drain-source current Idsof the first SiC MOSFET is detected by using a voltage drop VIdsSense on a source parasitic inductor LS1of the first SiC MOSFET M1. That is,

Vids⁢_⁢Sense=LS⁢1×dId⁢s⁢1dt

Therefore, a switching status of the first SiC MOSFET M1is fed back to the segmented driving circuit according to VLS1. A high-voltage first capacitor C1and a high-voltage second capacitor C2feedback a change condition of VSWto the segmented driving circuit. The driving circuit determines a magnitude of a driving current according to information about a drain-source voltage and a drain-source current of the first SiC MOSFET M1. Based on this, the driving current may be fed back to A driving control circuit in real time according to an operating condition of the SiC MOSFET, and further the magnitude of the driving current is adjusted, to control a switching speed of the SiC MOSFET.

FIG.2is a method for designing a turn-on segmented driving circuit based on the SiC MOSFET. At S1and S2stages, Vgs1rises from VEE to a Miller platform stage, and a moderate driving current is adopted, so that a change speed of a current generated by a channel of the SiC MOSFET can be reduced, that is, dIds/dt can be controlled. A relatively high driving current indicates the fast rising-speed of Vgs1, and a relatively high di/dt signal cannot be fed back in time by using a feedback mechanism, which is easy to cause damage to a device. Because when Ids does not rise to IL, a relatively small driving current is used to increase a turn-on time of the SiC MOSFET, and the turn-on time of the SiC MOSFET and dIds/dt need to be set in a reasonable range by controlling t1. Therefore, at a first stage, that is, S1, a constant driving current is used. At a second stage, that is, S2, whether to reduce the driving current is determined by using a drain-source current Ids of the first SiC MOSFET M1, that is, a rising edge of On_Flag1. In addition, the driving current may be adjusted according to external application. At a S3stage, an overshoot current depends on a current on Cds2. When VSWis equal to VIN, Cds2is the largest, and even a small dVSW/dt is easy to produce a relatively large overshoot current ΔIds. In this case, Vgs1should maintain a small value, that is, a low driving current Ig is used. With the reduction of VSW, Cds2is sharply reduced, and a rising speed of Vgs1may be appropriately accelerated within an allowable range. Because dVSW/dt has a certain limitation and also produces the overshoot current ΔIds, the driving current Ig may be appropriately increased, but a maximum driving current Ig cannot be used. At this stage, when VSWis reduced in segments, the trade-off between a falling speed of VSW and dVSW/dt can be achieved by controlling t2. At this stage, a falling edge of On_Flag1may be determined by using VSW, and whether the driving current needs to be increased is determined. At a S4stage, when the SiC MOSFET enters a linear region, the maximum driving current Ig may be used to charge Vgs1to VDD. When a supply voltage of the driving circuit is equal to VDD, even if the maximum driving current is used, Vgs1is close to VDD, a driving transistor has entered the linear region, and an actual driving current is not excessive high. In this way, a rising speed of Vgs1can still be accelerated without causing excessive high dv/dt of Vgs1. At this stage, whether the maximum driving current is used may be determined depending on whether VSWis close to a ground potential, that is, On_Flag2, so that the first SiC MOSFET M1is turned on.

FIG.3is a method for designing a turn-on segmented driving circuit based on the SiC MOSFET. At S5and S6stages, a relatively small driving current Ig is used, a falling speed of Vgs1of the first SiC MOSFET M1is also reduced, and a falling speed of a current of the channel is also reduced. Therefore, a rising speed of VSWis slower. When the current Ids_int of the channel of the first SiC MOSFET M1is reduced to a specific value, VSWstarts rising. In this case, a gate driving current Ig is reduced to a minimum value, and the falling speed of Vgs1of the first SiC MOSFET M1is the slowest. With the increase of VSW, Ids_int is increased and gradually approaches Ids_int. The rising speed of VSWis slow down, and a current on a parasitic capacitor of the first SiC MOSFET M1is reduced. Whether a relatively small driving current is used may be determined by using a voltage value of VSW, that is, an Off_Flag1signal. Alternatively, dVSW/dt may be controlled into a set range by adjusting the magnitude of the driving current. At a S7stage, after VSWis close to VIN, the gate driving current may be increased appropriately, the gate-source voltage Vgs1of the first SiC MOSFET M1starts to reduce, and Ids and Ids_int are reduced simultaneously. In this case, the current on the parasitic capacitor is ignored because VSWis greater than VIN and the change speed is relatively small. A falling speed of Ids is also a rising speed of a positive turn-on current of a body diode of the second SiC MOSFET M2. Therefore, in this case, the falling speed of the gate-source Vgs1of the first SiC MOSFET still needs to be controlled, to control the falling speed of Ids. Therefore, overshoots of dIds/dt and VSWmay be controlled. A larger difference between Ids and the current Ids_int of the channel of the first SiC MOSFET M1indicates a larger dv/dt, and a shorter time required by rising of VSW. At this stage, the trade-off between dv/dt and the turn-on time may be achieved by adjusting a time t3. At a S8stage, when Ids is reduced to 0, the gate-source voltage Vgs1of the first SiC MOSFET M1may be quickly pulled to VEE to complete a turn-off process of the SiC MOSFET. That is, in this case, the gate driving current is a maximum value. Whether the maximum driving current is used may be determined depending on whether the drain-source current Ids of the first SiC MOSFET M1is turned off, that is, Off_Flag2.

The foregoing is the method for designing SiC MOSFET-based segmented driving circuit. The circuit is designed according to the method. An implementation of SiC MOSFET-based segmented driving circuit is described below in detail with reference toFIG.4toFIG.9.

FIG.4is the SiC MOSFET drain-source voltage detection circuit. When a first SiC MOSFET is turned on or turned off, VSWsense is restored to GND after detecting a change of VSW, so that the change of VSWis detected next time. When the first SiC MOSFET M1is turned on, VSWand VSW_Senseare reduced. A first NOT gate INV1_M to a fourth NOT gate INV4_H are used as comparators, and a flipped voltage is determined by setting a flipped voltage of a NOT gate. When VSW_Senseis reduced to a middle point between VEE and GND, the first NOT gate INV1_M is flipped, and a first rising edge detection circuit works, and an output signal On_VSW1is changed to a low level short pulse. When VSW_Senseis continuously reduced to a lowest point, the second NOT gate INV2_L and the third NOT gate INV3_L are flipped, a second rising edge detection circuit and a third rising edge detection circuit work, and an output signal On_VSW2is changed into a low level short pulse. A first latch Latch1works and a signal On_ctrl is flipped to VEE, and a first PMOS transistor is turned on, and VSW_Senseis pulled to (GND-VF). When VSW_Senserises, the fourth NOT gate INV4_H is flipped, and the first latch1works after a specific delay. When On_Ctrl is flipped from VEE to GND, and the first PMOS transistor MP1is turned off. A first delay circuit is used to ensure that VSW_Senseis restored to near GND, so that the change of VSWis detected next time. A first Zener diode D2is used to ensure that VSW_Senseis not reduced indefinitely, and a second Schottky diode D2is used to prevent a current of the first PMOS transistor MP1from backflow when VSW_Senseis greater than GND. A power rail used by a turn-on stage drain-source voltage sampling circuit of the SiC MOSFET inFIG.2is GND to VEE, where GND is 0V, and VEE is −5V When the first SiC MOSFET M1is turned off, VSWrises, and VSW_Sensealso rises. An eighth NOT gate INV8_L to a tenth NOT gate INV10_H and a twelfth NOT gate INV12_L are also used as comparators, and a flipped voltage is determined by setting a flipped voltage of a NOT gate. When VSWsense rises, the eighth NOT gate INV8_L is flipped, a first falling edge detection circuit works and a signal Off_VSW1is outputted as a high level short pulse. When VSW_Sensecontinuously rises to the highest, the ninth NOT gate INV9_H is flipped, a second falling edge detection circuit works, and a signal Off_VSW2is outputted as a high level short pulse. In addition, the tenth NOT gate INV10_H is flipped, and an eleventh NOT gate INV11and a sixth rising edge detection circuit work, a second latch Latch2works, Off_Ctrl rises from GND to V5V, and a first NMOS transistor MN1is turned on. When VSWsense starts to reduce and is reduced to a minimum value, the twelfth NOT gate INV12_L is flipped, a seventh detection circuit, a second delay circuit, and a second AND gate work, a second latch Latch2outputs a low level signal, Off_ctrl is flipped to GND, and the first NMOS transistor MN1is turned off. A second delay circuit is used to ensure that VSW_Senseis restored to near GND, so that the change of VSWis detected next time. A third Zener diode D3is used to ensure that VSW_Sensedoes not rise indefinitely. A fourth Schottky diode D4is used to prevent a current of the first PMOS transistor MP1from backflow when VSW_Senseis greater than GND. A power rail used by a turn-off stage drain-source voltage sampling circuit of the SiC MOSFET inFIG.4is GND to V5V, where GND is 0V, and V5V is 5V. InFIG.4, a rising edge detection circuit or a falling edge detection circuit is used because the switching speed of the SiC MOSFET is relatively fast. The detected VSWsense may partially coincide with a subsequent current sampling voltage pulse, which may cause spurious triggering and even chaos on a subsequent circuit.

FIG.5is the SiC MOSFET drain-source current detection circuit. It can be learned fromFIG.1that

VIds⁢_⁢Sense=LS⁢1×d⁡(Iq+Id⁢s⁢1)dt

when the first SiC MOSFET is turned on, IN is flipped to a high level, a ninth rising edge detection circuit works, a third latch Latch3outputs a high level signal, and a divide-by-two circuit works normally. When the driving circuit starts outputting a gate driving current Ig, although the drain-source current Ids of the first SiC MOSFET M1is 0, VIds_Senseis overshoot. After Ig is stable, VIdssense is restored to GND. When the first SiC MOSFET M1has the drain-source current Ids, VIds sense rises again, a thirteen NOT gate INV13and a fourteen NOT gate INV14are flipped, the divide-by-two circuit makes a response to output a high level signal, and an eleventh rising edge detection circuit, a fifteen NOT gate INV15, and a third AND gate work, to cause an output signal On_Ids to be flipped to a high level. When On_Ids is flipped to the high level, a tenth rising edge detection circuit works, a third latch Latch3outputs a low level signal, and the divide-by-two circuit fails, to wait for detecting turn-on of the SiC MOSFET in a next cycle. When the first SiC MOSFET M1is turned off, information about the drain-source current of the first SiC MOSFET M1is transmitted to a signal Off Ids by using a sixteen NOT gate INV16, a first Schmitt trigger SMIT1, and a seventeen NOT gate INV17. A fifth Zener transistor D5and a sixth Zener transistor D6are used to clamp VIds_Sensewithin an appropriate voltage range, to prevent excessive voltage from damaging an internal circuit. A power rail of an effective voltage of VIds_Senseat a turn-on stage of the first SiC MOSFET M1is GND to V5V. Therefore, a corresponding logical signal is processed herein. The power rail of the effective voltage of VIds_Senseat a turn-off stage of the first SiC MOSFET M1is VEE to GND. A corresponding logical signal is processed subsequently, otherwise, a level shifter circuit needs to be added, to increase a chip area. Because VIds_Sensemay be a positive voltage or may be a negative voltage, gate-source voltages of devices used by the thirteenth NOT gate INV13and the fourteenth NOT gate INV14need to withstand positive and negative voltages.

FIG.6is the SiC MOSFET segmented driving circuit.FIG.7andFIG.8are schematic diagrams of key nodes of the segmented driving circuit. First, a working principle of the SiC MOSFET turn-on segmented driving circuit is described. InFIG.6, a power rail used by a turn-on circuit is VDD and VSSH, where VDD is 15V, and VSSH is 10V The turn-on stage may be divided into four working processes. An operating condition of a driving circuit at each stage is analyzed in detail below with reference toFIG.6andFIG.7.

At a S1stage: when both an input signal IN_HS and a turn-on deadband signal On_Dead are at a high level, a fourth AND gate AND4outputs a high level signal, a twentieth NOT gate INV20outputs a low level signal, and a second PLDMOS transistor PLD2outputs a specific driving current. When the first SiC MOSFET is not turned on, Flag1_HS is always a low level signal. Therefore, after a second PLDMOS transistor PLD2is turned on, a first PLDMOS transistor PLD1is turned on through a twenty-first NOT gate INV21, a first AND-NOT gate NAND1, a twenty-third NOT gate INV23, and a twenty-fourth NOT gate INV24, to increase the driving current. The process is shown in the S1stage inFIG.4. At this stage, the driving current is turned on in segments. This mainly because a gate parasitic inductance of the SiC MOSFET is relatively large, and the current changes too fast, which is easy to cause a large voltage difference at two ends of the parasitic inductance, resulting in more serious oscillation.

At a S2stage: after the SiC MOSFET is turned on, the drain-source current Ids starts rising, a drain-source current detection circuit of the SiC MOSFET works, and Ids_s_HS after passing through a level shifter circuit is a high level pulse circuit. After a twelfth rising edge detection circuit works, an S end of a fourth latch Latch4outputs a low level pulse signal, and the fourth latch Latch4outputs a high level signal Flag1_HS. The first PLDMOS transistor PLD1is turned off through a twenty-second NOT gate INV22, the first AND-NOT NAND1, the twenty-third NOT gate INV23, and the twenty-fourth NOT gate INV24, to reduce the driving current. In this case, a rising speed of the gate-source voltage Vgs1of the first SiC MOSFET M1is slow down, and a falling speed of VSWis also slow down.

At a S3stage: because dVSW/dt is reduced, an overshoot of Ids is also reduced. With the reduction of VSW, a low level pulse signal occurs at VSW_S_HS1. After passing through an eighteen NOT gate INV18and a first OR-NOT gate NOR1, an R end of the fourth latch Latch4generates a low level signal, Flag1_HS is flipped from high level to low level, and the first PLDMOS transistor PLD1is turned on again, to increase the driving current. At a VSWreduction stage, two segments of driving current are adopted. This is because Cds2is reduced rapidly with the reduction of VSW. If the driving current and a falling rate of VSWare appropriately increased, Ids does not cause too much overshoot.

At a S4stage: when VSWis reduced to a linear region of the first SiC MOSFET M1, the VSWhas a low potential. In this case, VSW_S_HS2has a low level pulse signal, an S end of a fifth latch Latch5is at a low level, Flag2_HS is at a high level, a third PLDMOS transistor PLD3is turned on through the second AND-NOR gate NAND2, a twenty-fifth NOT gate INV25, and a twenty-sixth NOT gate INV26, to output a maximum driving current, to rapidly pull the gate-source voltage Vgs1of the first SiC MOSFET M1to VDD, thereby completing a turn-on action of the SiC MOSFET.

When IN_HS is flipped from a high level to a low level, Flag1_HS and Flag2_HS are restored to a low level by using a nineteen NOT gate INV19. This is to prevent other subsequent logic errors caused by the misoperation of the drain-source detection circuit of the SiC MOSFET in a cycle. In the turn-on stage segmented driving circuit, the second PLDMOS transistor PLD2outputs a minimum driving current, the first PLDMOS transistor PLD1output a moderate driving current, and the third PLDMOS transistor PLD3outputs a maximum driving current. Segmented driving is implemented by adjusting three different levels of driving current.

InFIG.6, a power rail used by a turn-off stage segmented driving circuit is GND and VEE, where GND is 0V, and VEE is −5V The turn-off stage may also be divided into four working processes. An operating condition of a driving circuit at each stage is analyzed in detail below with reference toFIG.6andFIG.8.

At a S5stage: when both an input signal IN_LS and a turn-off deadband signal Off_Dead are at a low level, a third OR-AND gate NOR3outputs a high level signal, a second NLDMOS transistor NLD2is turned on, to output a driving current. A first NLDMOS transistor NLD1is turned on through a sixth AND gate AND6, a thirty-first NOT gate INV31, and a thirty-second NOT gate INV32, to increase the driving current. A reason for turning on the driving current in segments at this stage is the same as the turn-on stage.

At a S6stage: when VSWstarts rising, VSW_S_LS1is a high level pulse signal, Flag1_LS is at a high level through a sixth latch Latch6, and the first NLDMOS transistor NLD1is turned off, to reduce the driving current. When the driving current is reduced, a falling speed of the gate-source voltage Vgs1of the first SiC MOSFET M1is reduced. Therefore, the rising speed of VSWis reduced, that is, dVSW/dt is reduced. When VSWrises to VIN, VSW_S_LS2is a high level pulse signal, after the second OR-NOT gate NOR2and a twenty-seventh NOT gate INV27, an output signal Flag1_LS of the sixth latch Latch6is at a low level, and the first NLDMOS transistor NLD1is turned on again, to increase the driving current. A main issue is rising of VSWat this stage. The rising speed of VSWis reduced by reducing the falling speed of the gate-source voltage Vgs1of the first SiC MOSFET M1.

At a S7stage: when Flag1_LS1is flipped to a low level, a third falling edge detection circuit works, so that an output end of a seventh latch Latch7is at a high level until IN_LS is flipped from a low level to a high level, the output end is restored to a low level state. With the continuous rising of VSW, a body diode of the second SiC MOSFET transistor M2starts to be conducted forward, and Ids starts to reduce until being 0. A main issue is the reduction of Ids at this stage. A maximum driving current cannot be used for controlling dIds/dt.

At a S8stage: when Ids is reduced to 0, Ids_S_LS is flipped from a high level to a low level, and a fourth falling edge detection circuit outputs a high level signal. Both two inputs of a third AND-NOT gate NAND3are at a high level, and an output thereof is a low level signal. After a fifth AND gate AND5and an eighth latch Latch8, Flag2_LS is at a high level, a third NLDMOS transistor NLD3is turned on, to output a maximum driving current to rapidly reduce the gate-source voltage Vgs1of the first SiC MOSFET M1to VEE. The turn-off process of the SiC MOSFET is completed.FIG.5is a schematic diagram of key nodes.

In the turn-off segmented driving circuit, Flag2_LS depends on Ids_S_LS or Flag1_LS. This is because the source parasitic inductance of the SiC MOSFET is relatively small, when a speed of Ids is relatively small, the drain-source current sampling circuit of the SiC MOSFET may not work, Flag1_LS can still lift Flag2_LS after a specific delay, to increase the driving current. When IN_LS is flipped from a low level to a high level, Flag1_LS and Flag2_LS are restored to the low level signals, to prevent a logic error in a subsequent cycle caused by spurious triggering in a cycle. In the turn-off stage segmented driving circuit, the second NLDMOS transistor NLD2outputs a minimum driving current, the first NLDMOS transistor NLD1outputs a moderate driving current, and the third NLDMOS transistor NLD3outputs a maximum driving current. Segmented driving is implemented by adjusting three different levels of driving current.

FIG.9is an edge detection circuit used in the circuit. The edge detection circuit mainly includes a rising edge detection circuit and a falling edge detection circuit. A working principle of the rising edge detection circuit is that: when an input signal is changed from a low level to a high level, one input end of a fourth AND-NOT gate NAND4is at a high level. Due to delays of a thirty-fifth NOT gate INV35, a thirty-sixth NOT gate INV36, and a thirty-seventh NOT gate INV37, the other input end of the fourth AND-NOT gate NAND4maintains a temporary high level. Therefore, the fourth AND-NOT gate NAND4outputs a low level short pulse. Therefore, a rising edge signal is detected, and a low level short pulse signal is outputted. A working principle of the falling edge detection circuit is that: when an input signal is changed from a high level to a low level, one input end of a fourth OR-NOT gate NOR4is at a low level. Due to delays of a thirty-eighth NOT gate INV38, a thirty-ninth NOT gate INV39, and a fortieth NOT gate INV40, the other input end of the fourth OR-NOT gate NOR4maintains a temporary low level. Therefore, the fourth OR-NOT gate NOR4outputs a high level short pulse. Therefore, a falling edge signal is detected, and a high level short pulse signal is outputted.