Patent ID: 12249958

DETAILED DESCRIPTION OF THIS DISCLOSURE

The present disclosure is directed to LC oscillator. While the specification describes several example embodiments of the disclosure considered favorable modes of practicing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the particular examples described below or to the particular manner in which any features of such examples are implemented. In other instances, well-known details are not shown or described to avoid obscuring aspects of the disclosure.

Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as “voltage,” “current,” “oscillator,” “LC oscillator,” “frequency,” “resonance,” “resonant network,” “LC tank,” “impedance,” “power supply,” “ground,” “noise,” “phase noise,” “CMOS (complementary metal oxide semiconductor),” “NMOST (n-channel metal-oxide semiconductor transistor),” “PMOST (p-channel metal-oxide semiconductor transistor),” “inductor,” “capacitor,” “via,” and “cross couple.” Terms like these are used in a context of microelectronics, and the associated concepts are apparent to those of ordinary skill in the art and thus will not be explained in detail here.

Those of ordinary skill in the art can recognize a capacitor symbol, an inductor symbol, a mutual inductive coupling symbol, and can recognize a MOS (n-channel metal-oxide semiconductor) transistor symbol, and identify the “source,” the “gate,” and the “drain” terminals thereof, for both PMOST and NMOST. Those of ordinary skill in the art can read schematics of a circuit comprising components such as capacitors, inductors, MOS transistors, and so on, and do not need a verbose description about how one component connects with another in the schematics.

This present disclosure is disclosed from an engineering perspective. For instance, regarding two variables X and Y, when it is said that “X is equal to Y,” it means that “X is approximately equal to Y,” i.e. “a difference between X and Y is smaller than a specified engineering tolerance.” When it is said that “X is zero,” it means that “X is approximately zero,” i.e. “X is smaller than a specified engineering tolerance.” When it is said that “X is substantially smaller than Y,” it means that “X is negligible with respect to Y,” i.e. “a ratio between X and Y is smaller than an engineering tolerance and therefore X is negligible when compared to Y.”

A power supply node is a circuit node of a voltage that is approximately equal to a power supply voltage that is higher than zero but might have a small high-frequency fluctuation. A ground node is a circuit node of a voltage that is approximately zero but might have a small high-frequency fluctuation. Throughout this disclosure, “VDD” denotes a power supply node and “VSS” denotes a ground node.

As is known, a circuit is a collection of a transistor, a resistor, an inductor, a capacitor, and/or other electronic devices inter-connected in a certain manner to embody a certain function.

An inductor comprises an electrical conduction path, usually embodied by a metal wire (or trace) that allows a current to flow through and excite a magnetic field. An inductor is often embodied by a metal wire (or trace) configured in a loop topology with two open ends including a first end and a second end, wherein a current can flow from the first end to the second end.

A CMOS process technology allows integrating a plurality of transistors, capacitors, and inductors that are laid out in a multi-layer structure and inter-connected using metal traces and inter-metal-layer vias. An objective of this present disclosure is to integrate a LC oscillator using a CMOS process technology with a compact layout area while achieving a low phase noise. A multi-layer structure of a CMOS technology comprises a polysilicon layer, multiple metal layers including a UTM (ultra-thick metal) layer, a RDL (re-distribution layer), and a plurality of lower metal layers, and a plurality of via layers configured to provide inter-metal connection. By way of example but not limitation, a 28 nm 1P7M (comprising one poly-silicon layer, one UTM layer, six lower metal layers, and a RDL in the multi-layer structure) CMOS technology is used.

A schematic diagram of a LC oscillator200in accordance with an embodiment of the present invention is depicted inFIG.2A. By way of example but not limitation, LC oscillator200is integrated and fabricated on a silicon substrate using a 28 nm 1P7M CMOS technology. LC oscillator200comprises: a LC tank210comprising a parallel connection of a main inductor LM and a main capacitor CM placed across a first drain node ND1and a second drain node ND2; a first cross-coupling pair CCP1comprising a first NMOST NM1and a second NMOST NM2connected to a first source node NS1and configured to cross couple the first drain node ND1and the second drain node ND2; a second cross-coupling pair CCP2comprising a first PMOST PM1and a second PMOST PM2connected to a second source node NS2and configured to cross couple the first drain node ND1and the second drain node ND2; a first source degeneration network SDN1comprising a parallel connection of a first auxiliary capacitor CA1and a first auxiliary inductor LA1that is split into a first half LA1_1and a second half LA1_2placed across the first source node NS1and a ground node VSS; and a second source degeneration network SDN2comprising a parallel connection of a second auxiliary capacitor CA2and a second auxiliary inductor LA2that is split into a first half LA2_1and a second half LA2_2placed across the second source node NS2and a power supply node VDD.

The LC tank210is configured to form a resonant network of a resonant frequency f0to establish an oscillation of an oscillation frequency approximately equal to f0. The first cross-coupling pair CCP1and the second cross-coupling pair CCP2are both regenerative networks used to compensate an Ohmic loss of the LC tank210and thus sustain the oscillation. The first source degeneration network SDN1is configured to form a resonance and thus provide a high impedance at twice of the oscillation frequency, which is approximately 2×f0, to suppress an up-conversion of a noise of the first cross-coupling pair CCP1. The second source degeneration network SDN2is configured to form a resonance and thus provide a high impedance at twice of the oscillation frequency, which is approximately 2×f0, to suppress an up-conversion of a noise of the second cross-coupling pair CCP2. Functionally, LC oscillator200is the same as the LC oscillator100ofFIG.1, only that inductor131ofFIG.1is replaced by the first auxiliary inductor LA1embodied by the parallel connection of LA1_1and LA1_2, while inductor151ofFIG.1is replaced by the second auxiliary inductor LA2embodied by the parallel connection of LA2_1and LA2_2.

However, LC oscillator differs in the following aspects: LA1_1and LA2_1are laid out in a highly close proximity so that there is a strong mutual coupling k24between LA1_1and LA2_1(see callout box B210), inductors LA1_2and LA2_2are laid out in a highly close proximity so that there is strong mutual coupling k35between LA1_2and LA2_2(see callout box B220), and therefore there is a strong mutual coupling between the first auxiliary inductor LA1and the second auxiliary inductor LA2; the first auxiliary inductor LA1(comprising LA1_1and LA1_2) is laid out symmetrically inside the main inductor LM (see callout box B230); and the second auxiliary inductor LA2(comprising LA2_1and LA2_2) is also laid out symmetrically inside the main inductor LM (see callout box B240), wherein the main inductor LM is laid out symmetrically with respect to a plane of symmetry (see callout box B250). By laying out LA1and LA2inside LM, the layout area can be very compact. By taking advantage of the strong mutual coupling between the first auxiliary inductor LA1(comprising LA1_1and LA1_2) and the second auxiliary inductor LA2(comprising LA2_1and LA2_2) due to the highly close proximity in layout that leads to a strong enhancement of magnetic flux linkage, one can boost a quality factor of LA1and LA2and consequently an effectiveness of source degeneration and phase noise suppression of SDN1and SDN2.

In addition, since LA1_1and LA1_2are laid out inside LM in a symmetrical manner with respect to LM, a magnetic coupling between LM and LA1_1can be canceled by a magnetic coupling between LM and LA1_2, thus suppressing an overall coupling between the LC tank210and the first source degeneration network SDN1. Likewise, LA2_1and LA2_2are laid out inside LM in a symmetrical manner with respect to LM, so that a magnetic coupling between LM and LA2_1can be canceled by a magnetic coupling between LM and LA2_2, thus suppressing an overall coupling between the LC tank210and the second source degeneration network SDN2. This helps to mitigate an adverse effect of quality factor degradation of LC tank210due to an undesired coupling between the LC tank210and the two source degeneration networks SDN1and SDN2. As a result, two objectives can be reached: compact layout area and low phase noise.

A top view of a layout of LC oscillator200, by way of example but not limitation, is shown inFIG.2B. A legend is shown inside box B200. The main inductor LM comprises a first metal trace LM_1laid out on the UTM layer, a second metal trace LM_2and a third metal trace LM_3laid out on the RDL, along with two inter-metal connection vias LM_4and LM_5configured to connect LM_1to LM_4and LM_5, respectively. LM_1is the main part of the main inductor LM, LM_2and LM_3are two ends of the main inductor LM that connect to the main capacitor CM, the first coupling pair CCP1, and the second cross coupling pair CCP2. Note that LM_2and LM_3electrically embody the first drain node ND1and the second drain node ND2, respectively. The first auxiliary inductor LA1(that is split into two halves LA1_1and LA1_2connected in parallel) is laid out on the RDL. The second auxiliary inductor LA2(that is split into two halves LA2_1and LA2_2connected in parallel) is laid out on the UTM layer. LM is laid out symmetrical with respect to a plane of symmetry (which in the top view appears to be a central line). LA1_1and LA1_2are mirror images to one another with respect to the plane of symmetry. Likewise, LA2_1and LA2_2are mirror images to one another with respect to the plane of symmetry. LA1_1and LA2_1are laid out in highly close proximity. Likewise, LA2_1and LA2_2are also laid out in very close proximity.

The main capacitor CM is laid symmetrically between LM_2and LM_3across the plane of symmetry. The first auxiliary capacitor CA1is laid symmetrically between LA1_1and LA1_2across the plane of symmetry. When a current flows from the power supply node VDDto the second source node NS2through LA2_1in a counterclockwise direction, there will always be another current of the same magnitude flows from the power supply node VDDto the second source node NS2through LA2_2in a clockwise direction due to the geometrical symmetry. A magnetic coupling between LM and LA2_1will be the same as a magnetic coupling between LM and LA2_2in magnitude but opposite in polarity; as a result, a net magnetic coupling between the main LM and the second auxiliary inductor LA2(comprising LA2_1and LA2_2) is zero, indicating a perfect isolation. Likewise, when a current flows from the first source node NS1to the ground node VSSthrough LA1_1in a counterclockwise direction, there will always be another current of the same magnitude flows from the first source node NS1to the ground node VSSthrough LA1_2in a clockwise direction due to the geometrical symmetry. A magnetic coupling between LM and LA1_1will be the same as a magnetic coupling between LM and LA1_2in magnitude but opposite in polarity; as a result, a net magnetic coupling between LM and the first auxiliary inductor LA1(comprising LA1_1and LA1_2) is zero, indicating a perfect isolation. As a result, an effectiveness of LM in terms of magnetic flux generation and consequently a quality factor can be preserved despite the existence of the first auxiliary inductor LA1(comprising LA1_1and LA1_2) and the second auxiliary inductor LA2(comprising LA2_1and LA2_2). Moreover, there is a very strong mutual coupling between LA1_1and LA2_1, and also a very strong mutual coupling between LA1_2and LA2_2, due to the proximity in layout. The current flows from VDDto NS2through LA2_1and the current flows from NS1to VSSthrough LA1_1will increase the magnetic flux linkage for one another due to the strong mutual coupling. Likewise, the current flows from VDDto NS2through LA2_2and the current flows from NS1to VSSthrough LA1_2will increase the magnetic flux linkage for one another due to the strong mutual coupling. As a result, a quality factor of the first auxiliary inductor LA1(comprising LA1_1and LA1_2) and the second auxiliary inductor LA2(comprising LA2_1and LA2_2) is enhanced, and the source degeneration and noise suppression of SDN1and SDN2can be more effective. Therefore, phase noise of the LC oscillator200can be low despite a compact layout.

Although LM inFIG.2Bis shown to be of a single turn topology, this is just a non-limiting example. In an embodiment not shown in figure but clear to those of ordinary skill in the art, the main inductor LM is of a multi-turn topology with at least one turn of metal trace laid out on the UTM layer. UTM layer is favorable for laying out the main inductor LM due to low resistance. In an embodiment, the first auxiliary inductor LA1(comprising LA1_1and LA1_2) is of a multi-turn topology with at least one turn of metal trace laid out on one of the UTM layer and the RDL. In an embodiment, the second auxiliary inductor LA2(comprising LA2_1and LA2_2) is of a multi-turn topology with at least one turn of metal trace laid out on one of the UTM layer and the RDL. The RDL has larger resistance than the UTM layer; however, by using a combination of RDL and UTM layer, an overall layout area can be more compact.

As illustrated by a flow diagram inFIG.3, in accordance with an embodiment of this present invention, a method of integrating an oscillator comprises the following steps: (step310) incorporating a main inductor and a main capacitor for establishing an oscillation; (step320) incorporating two cross-coupling NMOST and two cross-coupling PMOST for sustaining the oscillation; (step330) incorporating a first auxiliary inductor and a first auxiliary capacitor for suppressing a noise of the two cross-coupling NMOST; (step340) incorporating a second auxiliary inductor and a second auxiliary capacitor for suppressing a noise of the two cross-coupling PMOST; (step350) laying out the main inductor symmetrically with respect to a plane of symmetry; (step360) laying out the first auxiliary inductor as a parallel connection of two halves that are inside the main inductor and symmetrical with respect to the plane of symmetry; and (step370) laying out the second auxiliary inductor as a parallel connection of two halves that are inside the main inductor in a close proximity to the first auxiliary inductor and symmetrical with respect to the plane of symmetry.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the disclosure. Accordingly, the above disclosure should not be construed as limited only by the metes and bounds of the appended claims.