Patent ID: 12212232

DETAILED DESCRIPTION

FIGS.1-2show cascade multipliers that receive an input voltage VI from a voltage source16and provide an output voltage VO to a load18. Consistent with conventional circuit representations, a capacitor's anode is shown as a straight line and its cathode is shown as a curved line.

Switches MO-M5connect the anodes of the capacitors C1-C3to some other element, which is either the anode of another capacitor or a first or second terminal of the cascade multiplier. The capacitors' cathodes connect to one of two phase voltages VP1, VP2, which are 180-degrees out-of-phase.

InFIG.1, there is one switch M1between anodes of two capacitors C1, C2. However, inFIG.2, there are two switches M1, M2between the anodes of the same two capacitors.

In normal operation, packets of charge are pumped along a chain of diode-connected NMOS transistors M0-M5as pump capacitors C1-C3are successively being charged and discharged. As shown inFIGS.1-2, phase voltages VP1, VP2are one hundred and eighty degrees out of phase.

Each of the NMOS transistors M0-M5is diode-connected, thereby only permitting boost operation (i.e. VO greater than VI). Additionally, the efficiency is severely impacted because a significant amount of voltage is dropped across each of the transistors M0-M5during normal operation. Therefore, there is a desire to operate the NMOS transistors M0-M5in their ohmic region, but due difficulty and/or complexity of driving the transistors M0-M5, a combination of both PMOS transistors and high-voltage transistors are typically used.

If the transistors in the switched-capacitor power converter are integrated on a single substrate then it can be desirable to use as few different types of devices as possible. This is because the cost of fabrication increases as the number of mask layers increases. As the number of different types of devices in a semiconductor process increases so does the number of mask layers and hence the cost.

The switches define a power path from a source16to a load18. It is useful to minimize the number of PMOS devices along the power path since hole mobility is somewhat less than electron mobility in silicon. As a result, PMOS devices tend to have higher on-resistance and higher gate capacitance that NMOS devices. It is also desirable to replace as many high-voltage devices with low-voltage devices.

A number of approaches are described below for use in the context of active control of switched capacitor power converters. The approaches address one or more of the following goals:

Increase in efficiency of the converter by reducing the charge deposited and discharged from the gates of control transistors

Permitting use of low-voltage transistors for switching.

Generally, an approach to achieving these goals is by efficiently limiting the gate-to-source voltages though the design and powering of circuits driving the switching transistors during operation. A number of specific approaches, some of which are described below, use control circuitry for switching transistors, which couple the capacitors in the charge transfer path, that are themselves powered by capacitors in the same path, and/or by capacitors in different parallel paths in the case of multi-phase converters.

Referring toFIG.3, a single-phase cascade multiplier circuit30makes use of transistors M0-M5coupling to first, second, and third pump capacitors C1-C3on the charge transfer path between a high-voltage terminal (i.e. VO) and a low-voltage terminal (i.e. VI). In the embodiment illustrated inFIG.3, the pump capacitors C1-C3are coupled by cascaded transistor switches (e.g., M1and M2in series), but it should be understood that single transistors could also be used while still achieving at least some of the advantages of the configuration shown.

Each transistor is driven by a corresponding gate driver circuit. As described in more detail below, at least some of the gate driving circuits are powered from the pump capacitors C1-C3in the charge transfer path between the high-voltage terminal and the low-voltage terminal. The voltage across each of the pump capacitors C1-C3is a fraction of the high voltage, thereby permitting efficient generation of gate driving signals that maintain desired limits on the gate-to-source voltages of the transistors.

A driver set32provides the gate signals to activate or de-activate each transistor in the cascade multiplier circuit30. The driver set32includes four low-voltage gate driver circuits34, two high-voltage gate driver circuits35, and four voltage followers36A-36D. Each gate driver circuit receives a driver signal with a label either beginning with an “A” or a “B.” The driver signals AO, BO, B1, A1, A2, B2control transistors M0, M1, M2, M3, M4, M5, respectively. Furthermore, the voltage followers36A-36D receive corresponding bias voltages V1-V4, respectively. A control circuit (not shown inFIG.3) generates the driver signals A0-B2and the bias voltages V1-V4.

The low-voltage gate driver circuits34are coupled to the transistors M0, M2, M4, M5, whereas, the high-voltage gate driver circuits35are coupled to the transistors M1, M3. The high-voltage gate driver circuits35support twice the supply voltage of the low-voltage gate driver circuits34. Each of the voltage followers36A-36D receive a voltage from one of the pump capacitors C1-C3and provides a constant voltage to their corresponding gate driver circuit (i.e.34or35) that is equal to or lower in value. When the received voltage is equal to the provided voltage, the corresponding voltage follower (e.g.36A) behaves like a switch. To achieve this behavior, the bias voltages VJ-V3are at least a threshold voltage above the corresponding source voltage while the bias voltage V4is at least a threshold voltage below the corresponding source voltage. Furthermore, the voltage followers36A-36D experience the same voltage stress as the transistors M0-M5in the cascade multiplier circuit30.

Also illustrated inFIG.3is an example of a pre-charge circuit38that is used to initialize the voltages on the pump capacitors C1-C3prior to clocked operation of the cascade multiplier circuit30. By pre-charging the pump capacitors C1-C3, the drain-to-source voltages across the transistors M0-M5within the cascade multiplier circuit30can be maintained within required limits during startup, and further, the pre-charged pump capacitors C1-C3can provide the needed power to the gate driving circuits immediately upon the start of clocked operation of the cascade multiplier circuit30. Upon clocked operation, the pre-charge circuit38can be disabled.

To facilitate the use of low-voltage transistors throughout the whole power converter, the pre-charge circuit38uses a combination of low-voltage transistors and bias resistors. A resistor divider sets up the pre-charge voltage for each of the pump capacitors C1-C3during startup, wherein the source voltage of each transistor within the pre-charge circuit38is at least a threshold voltage below its corresponding gate voltage. As a result, none of the transistors within either the pre-charge circuit38or the cascade multiplier circuit30are exposed to voltage stresses that can damage the devices during startup or clocked operation.

Operation of the cascade multiplier circuit30and the resulting voltage levels powering the gate driving circuits can be understood with reference toFIGS.4-5that show the two states of operation. The cascade multiplier circuit30transfers energy from a source16to a load18by cycling between a first state and a second state at a specific frequency. All of the transistors coupled with the “A” signals are activated and de-activated at the same time; as is the case for all of the transistors coupled with the “B” signals. To ensure a clean transition between the first and second state, the “A” signals and “B” signals are non-overlapping. Furthermore, first and second phase voltages VP1, VP2are synchronized with the “A” signals and “B” signals.

Assuming an input voltage VI of five volts, then the cascade multiplier circuit30produces an output voltage VO that is twenty volts. The maximum voltage across any transistor is five volts. Furthermore, the low-voltage gate driver circuits34support five volts while the high-voltage gate driver circuits35must support ten volts.

FIG.4illustrates the first state, wherein the first phase voltage VP1is at five volts while the second phase voltage VP2is at zero volts. The gate driver circuits that receive a “B” signal activate their corresponding transistors and the gate driver circuits that receive an “A” signal de-activate their corresponding transistors. Consequently, a gate voltage of fifteen volts activates the transistors M1, M2, M5while gate voltages of five volts, ten volts, and fifteen volts de-activate the transistors M0, M3, M4, respectively.

In contrast,FIG.5illustrates the second state, wherein the first phase voltage VP1is at zero volts while the second phase voltage VP2is at five volts. The gate driver circuits that receive an “A” signal activate their corresponding transistors and the gate driver circuits that receive a “B” signal de-activate their corresponding transistors. Consequently, gate voltages of five volts, ten volts, and twenty volts de-activate the transistors M1, M2, M5, respectively; while gate voltages of ten volts, twenty volts, and twenty volts activate the transistors M0, M3, M4, respectively.

Unfortunately, the voltage followers36A-36D associated with the transistors M0, M1, M2, M5consume power. Each voltage follower drops five volts across its drain and source terminals while sinking or source current for its corresponding gate driver. In the case of the transistors M1, M2, M5, this occurs during the first state while for transistor MO this occurs during the second state.

In the cascade multiplier circuit30, charge transfers to the load18from the source16at a rate dictated by the load18. Because this is a single-phase design, there is only one charge transfer path that a unit of charge can follow. For example, at the start of a first clock cycle, the unit of charge leaves the source16and flows into the first pump capacitor C1. After a state transition, the unit of charge moves to the second pump capacitor C2. When a second clock cycle begins, the unit of charge then moves from the second pump capacitor C2to the third pump capacitor C3and after one more state transition, the unit of charge finally reaches the load18. It took two full clock cycles (i.e. four consecutive states) for the initial charge to reach the load18from the source16.

In general, as the conversion gain of a cascade multiplier increases, the number of pump capacitors increases. Consequently, it takes a longer time for a unit of charge from the source16to reach the load18because the unit of charge needs to bounce between more pump capacitors. The number of clock cycles in the charge transfer path is M-2, where M is equal to the conversion gain. In this example, M is equal to four; therefore, the number of clock cycles is two.

FIGS.6-7illustrate two alternative designs of the gate driving circuits. Both of which can be used for the high-voltage gate driver circuits35and the low-voltage gate driver circuits34. However, as will be made clear in the following description, the gate driver inFIG.6is more suitable for the low-voltage gate driver34while the gate driver inFIG.7is more suitable for the high-voltage gate driver35.

As illustrated inFIG.6, a tapered gate driver features an input terminal IN, an output terminal OUT, and supply terminals VDD, VSS. The input terminal IN couples with the output terminal OUT through first, second, third, and fourth inverters, in that order. The four inverters include high-side PMOS transistors MP1-MP4and low-side NMOS transistors MN1-MN4. Due to the difference in electron and hole mobilities, each of the PMOS transistors MP1-MP4is typically sized larger than their corresponding NMOS transistors MN1-MN4.

Starting at the input terminal IN, each subsequent inverter is k times larger than the previous inverter. For example, if k is equal to five and the width of the first inverter is one micron, then the width of the second, third, and fourth inverters is five microns, twenty-five microns, and one hundred and twenty-five microns, respectively. By tapering the inverters, a small logic gate coupled to the input terminal IN is able to drive a large power transistor coupled to the output terminal OUT.

The maximum supply voltage of the tapered gate driver is equal to or less than the breakdown voltage of the transistors. Therefore, the tapered gate driver is a good choice for the low-voltage gate driver circuits34in the cascade multiplier circuit30. Unfortunately, due to the higher voltage requirements of the high-voltage gate driver circuit35inFIGS.3-5, the tapered gate driver circuit requires transistors with twice the breakdown voltage.

An alternative method of increasing the supply voltage without the need of higher voltage transistors is to use a cascaded gate driver. As illustrated inFIG.7, a cascaded gate driver includes an input terminal IN, an output terminal OUT, and supply terminals VDD, VSS. The cascaded gate driver features an output stage that includes first and second high-side transistors MP5, MP6and first and second low-side transistors MN5, MN6. The output stage requires additional support circuitry, such as a level shifter, two gate drivers, a delay block, and a voltage regulator, all of which can be designed using transistors with the same breakdown voltage as that of the transistors in the output stage.

During normal operation of the cascaded gate driver, the high-side transistors MP5, MP6are activated when the low-side transistors MN5, MN6are de-activated and vice-versa. Therefore, the cascaded gate driver can support twice the supply voltage because the differential voltage across the supply terminals VDD, VSS is always supported by two de-activated transistors. In general, a larger number of transistors can be cascaded to increase the supply voltage further. For example, if the output stage included three high-side transistors and three low-side transistors then the maximum supply voltage would be tripled and so on. Unfortunately, as the number of cascaded transistors increases, so does the complexity of the support circuitry.

In general, a single-phase cascade multiplier can be converted into a multi-phase cascade multiplier featuring multiple charge transfer paths that are shifted in time. As illustrated inFIG.8, a dual-phase cascade multiplier circuit40can be constructed by placing two copies, of the single-phase cascade multiplier circuit30in parallel. Each copy is referred to as a phase (not to be confused with state), therefore, the cascade multiplier circuit30features a first phase and a second phase. The first phase includes capacitors C1A-C3A, transistors MOA-MSA, and phase voltages VP1, VP2while the second phase includes capacitors C1B-C3B, transistors M0B-M5B, and phase voltages VP3, VP4. Each of the transistors M0A-M5B has a corresponding gate driver circuit34that receives a driver signal with a label either beginning with an “A” or a “B”. The first phase includes driver signals A0a-B2awhile the second phase includes driver signals A0b-B2b.

The control signals of the first phase and the second phase are shifted by one-hundred and eighty degrees. This can be achieved by swapping the “A” and “B” signals in one of the two phases and then inverting the corresponding phase voltages. For example, in normal operation, the phase voltages VP1, VP3are high when the phase voltages VP2, VP4are low and vice versa. Furthermore, the voltage followers in the first phase receive bias voltages V1a-V4awhile the voltage followers in the second phase receive bias voltage V1b-V4b. As in the previous single-phase example, a control circuit (not shown inFIG.8) can generate the drivers signals A0a-B2band the bias voltages Vla-V4b.

Additionally, by having the source16and the load18trade places, a step-down power converter can be converted into a step-up converter and vice versa. Therefore, the cascade multiplier circuit40is step-down power converter instead of a step-up power converter as inFIG.3.

There are several benefits of a dual-phase construction over a single-phase construction. The most obvious benefit is that there is always a charge transfer path between the source16and the load18regardless of the state of operation (first or second). A less obvious benefit is that the one phase can derive energy from an alternate phase to power circuitry and vice versa. Furthermore, this technique allows the cascade multiplier circuit40to only use low-voltage gate driver circuits34.

Since a dual-phase converter is essentially two single-phase converters operated in parallel, the cascade multiplier circuit40operates as described in connection withFIGS.3-5. Assuming the input voltage VI is twenty volts, the resulting voltage levels powering the gate driving circuits can be understood with reference toFIG.9that show one state of operation. The other state of operation is not shown because it is simply a mirror image of the state shown inFIG.9.

In the cascade multiplier circuit40, the transistors MOA-M3B derive power from opposing phases while the transistors M4A-M5B derive power from the input voltage VI. Powering the gate drivers from a parallel charge transfer path (i.e. opposing phase) results in one less voltage follower per phase and the voltage followers do not consume power. This is because the transistors M0A, M2A, M5A, M0B, M2B, M5B are de-activated while voltage is being dropped across their corresponding voltage followers. Because of the more efficient voltage followers and the lack of high-voltage gate driver circuits35, the energy required to drive the gates in a dual-phase design is less than a single-phase design.

As in the single-phase construction ofFIG.3, it takes two full clock cycles for the initial charge into the cascade multiplier circuit40to reach the load18. However, in the dual-phase construction, there are two charge transfer paths between the source16and the load18, instead of one, as in the single-phase construction. Furthermore, the two distinct charge transfer paths are shifted in time with respect to each other.

For example, a first unit of charge from the source16enters a first charge transfer path at the input of the cascade multiplier circuit40. During each state transition, the first unit of charge hops between the positive terminals of the capacitors C3B, C2B, C1B, in that order, thereby being delivered to the load18after four state transitions. Similarly, in a second charge transfer path, a second unit of charge leaves the source16and then precedes to hop between the positive terminals of the capacitors C3B, C2B, C1B each state transition. After the fourth state transition, the second unit of charge is delivered to the load18. By shifting the first and second charge transfer paths one hundred and eighty out of phase, a path for charge always exists between the source16and the load18.

It should be appreciated that the above described dual-phase cascade multiplier circuit40is one of many different implementations.FIG.10illustrates an alternative dual-phase cascade multiplier circuit50, formed by removing the cascade switches M2A, M4A, M2B, M4B in the cascade multiplier circuit40, thereby reducing control complexity and perhaps improving robustness. Unfortunately, without the cascade switches, all of the inner switches M1A, M3A, M1B, M3B need to support twice the output voltage VO as well as their corresponding gate drivers35.

Additionally, the pump capacitors C3A, C3B in the cascade multiplier circuit50are pumped in series with their corresponding pump capacitors CIA, C1B, compared to being pumped in parallel as in the cascade multiplier circuit40. The series arrangement reduces the voltage across the pump capacitors C3A, C3B. For example, if the output voltage VO is five volts, then the voltage across the capacitors C3A, C3B is ten volts inFIG.10compared to fifteen volts inFIG.8. Due to the similarity between the cascade multiplier circuits40,50, the cascade multiplier circuit50operates as described in connection withFIG.10

In addition to efficient generation of gate driving signals, the capacitor voltages can also be used to efficiently drive the phase signals that drive the capacitors. Two examples of the phase generator110are shown inFIGS.11-12, suitable to use with the dual-phase cascade multiplier circuit50shown inFIG.10.

FIG.11illustrates a phase generator110that receives an output voltage VO and produces first, second, third, and fourth phase voltages VP1-VP4. The first and second phase voltages VP1, VP2correspond to the first phase of the cascade multiplier circuit50while the third and fourth phase voltages VP3, VP4correspond to the second phase of the cascade multiplier circuit50.

The phase generator110features four transistor pairs, wherein each transistor pair generates one of the phase voltages VP1-VP4. A first pair of transistors MH1, ML1generates the first phase voltage VP1; a second pair of transistors MH2, ML2generates the second phase voltage VP2; a third pair of transistors MH3, ML3generates the third phase voltage VP3; and a fourth pair of transistors MH4, ML4generates the fourth phase voltage VP4. In each transistor pair, the high-side transistor (e.g. MH1) is a PMOS device while the low-side transistor (e.g. ML1) is a NMOS device.

Separate gate driver circuits control each transistor in the phase generator110, thereby allowing tri-state operation of each transistor pair. The output voltage VO powers each gate driver circuit. The gate driver circuits can be implemented using numerous circuit topologies, such as the tapered gate driver illustrated inFIG.6. Each gate driver circuit receives a driver signal with a label beginning with either an “A” or a “B”. The driver signals AL1, BL1, AL2, BL2control low-side transistors ML1, ML2, ML3, ML4, respectively while the driver signals BH1, AH1, BH2, AH2control high-side transistors MH1, MH2, MH3, MH4, respectively.

In normal operation, the phase generator110cycles between a first state and a second state at a specific frequency. During the first state, the gate driver circuits that receive a “B” signal activate their corresponding transistors and the gate driver circuits that receive an “A” signal de-activate their corresponding transistors. Consequently, the first and third phase voltages VP1, VP3are equal to the output voltage VO while the second and fourth phase voltages VP2, VP4are equal to zero volts.

In contrast, during the second state, the gate driver circuits that receive a “B” signal de-activate their corresponding transistors and the gate driver circuits that receive an “A” signal activate their corresponding transistors. Consequently, the first and third phase voltages VP1, VP3are equal to zero volts while the second and fourth phase voltages VP2, VP4are equal to the output voltage VO.

FIG.12illustrates an alternative phase generator110that receives an output voltage VO and produces first, second, third, and fourth phase voltages VP1-VP4. In a dual-phase design, the first and third phase voltages VP1, VP3are in phase; and the second and fourth phase voltages VP2, VP2are in phase. Consequently, as illustrated inFIG.12, the first and third phase voltages VP1, VP3can be shorted together and the second and fourth phase voltages VP2, VP4can be shorted together.

Additionally, high-side transistors MH1, MH2can utilize NMOS transistors instead of PMOS transistors as inFIG.11. The higher mobility of electrons in NMOS transistors allows for the use of smaller high-side transistors MH1, MH2, thereby reducing the energy required to activate. Because NMOS transistors require a gate voltage higher than their source to activate, the high-side transistors MH1, MH2derive this boost voltage from the pump capacitors within the cascade multiplier that the phase generator110is driving.

For example, if the phase generator110is coupled to the cascade multiplier circuit50, then the gate driver of the high-side transistor MH1is coupled to the positive terminal of the pump capacitor CIA from phase one. In contrast, the gate driver of the high-side transistor MH2is coupled to the positive terminal of the pump capacitor C1B from phase two. Therefore, each gate driver and its corresponding high-side transistor is powered by a pump capacitor from a distinct parallel charge transfer path.

Because of the similarity of the phase generators110inFIGS.11-12, the operation of the phase generator110inFIG.12operates as described in connection withFIG.11. The differences mainly being the shorted phase voltages and boosted high-side transistors MH1, MH2.

A number of alternatives to the switched capacitor power converter designs discussed make use of the approaches embodied in those designs. For example, the converter illustrated inFIG.13is a dual-phase series-parallel switched capacitor circuit that includes some gate drivers that are powered by capacitors in either the same charge transfer path or a parallel charge transfer path.

The switched capacitor circuit60includes a pair of phases. A first phase includes capacitors C1C-C3C, odd transistors M1C-M7C, and even transistors M2C-M12C. Similarly, a second phase includes capacitors C1D-C3D, odd transistors M1D-M7D, and even transistors M2D-M12D. All of the transistors coupled with signals having an “A” prefix through corresponding gate drivers are activated and de-activated at the same time; as is the case for all of the transistors coupled with signals having a “B” prefix through corresponding gate drivers.

The switched capacitor circuit60produces an output voltage VO that is four times lower than an input voltage VI by cycling between a first state and a second state at a specific frequency. During the first state, the first phase odd transistors M1C-M7C and the second phase even transistors M2D-M12D are activated while the first phase even transistors M2C-M12C and the second phase odd transistors M1D-M7D are de-activated. This switch activation pattern places the second phase capacitors C1D-C3D in parallel with the load18and places a series arrangement of the first phase capacitors C1C-C3C in between the source16and the load18.

In contrast, during the second state, the first phase odd transistors M1C-M7C and the second phase even transistors M2D-M12D are de-activated while the first phase even transistors M2C-M12C and the second phase odd transistors M1D-M7D are activated. This switch activation pattern places the first phase capacitors C1C-C3C in parallel with the load18and places a series arrangement of the second phase capacitors C1D-C3D in between the source16and the load18.

Unlike either of the dual-phase cascade multiplier circuits40or50, within a single phase of the switched capacitor circuit60, the gate drivers derive their power from capacitors in both phases. For example, the gate drivers for the corresponding transistors M1C, M3C, MSC are powered from the capacitors C1C, C2C, C3C, respectively while the gate drivers for the corresponding transistors M4C, MBC, M12C are powered from the capacitor C1D.

Furthermore, the voltage stress across the transistors in a series-parallel switched capacitor power converter can be quite high in comparison to cascade multipliers. Assuming the input voltage VI is equal to twenty volts then the maximum voltage across the transistors M12C, M12D is fifteen volts. In this embodiment, the gate-to-source voltage is always five volts and the gate drivers for the top PMOS transistors require two series connected voltage followers that are biased using voltages V1c-V2d.

Although described in the context of single-phase and dual-phase converters, it should be understood that other multi-phase converter configurations can be used. For example, a four-phase cascade multiplier can be constructed by placing two copies of the cascade multiplier circuit40in parallel and shifting their respective clocks by ninety degrees. Adding an even number of phases is straightforward because every subsequent pair of phases can be run in isolation.

However, if the switched capacitor power converter includes an odd number of phases, it is a little more difficult to power gate drivers from capacitors in different parallel charge transfer paths. In this case, each gate driver draws power from capacitors in multiple parallel charge transfer paths, as compared to a single parallel charge transfer path in the even-numbered phase case.

In general, switched capacitor converters feature a large number of switches and capacitors. By necessity, at least a few of the switches are floating, which means that neither switch terminal is attached to a constant electric potential. It should be appreciated that switched capacitor converters that have at least one floating switch can benefit by deriving power from the same charge transfer path or a parallel charge transfer path. Examples of such switched capacitor converters include the cascade multiplier, series-parallel, parallel-series, Fibonacci, and voltage-doubler topologies.

The switched capacitor power converters and the associated gate drivers illustrated herein can all be integrated on one or multiple semiconductor substrates. If all of the transistors are integrated on a single substrate and any of the transistors are floating then the transistors must be isolated from the substrate. For example, in a CMOS process, NMOS transistors are typically formed in a p-type substrate. These devices can only float if the bulk of the NMOS transistors is isolated from the substrate. If this were not the case, then an alternative possibility would be to use multiple semiconductor substrates.

The capacitors in a switched capacitor power converter can either be integrated, discrete, or a combination thereof. The discrete capacitors are typically multi-layer ceramic capacitors while the integrated capacitors are typically planar or trench capacitors. If the capacitors are integrated, then they can be integrated on the same wafer with their switches, or they can be integrated on a separate wafer, or a combination thereof. Furthermore, if the capacitors and switches are on different wafers then there are various attachment methods, some of which remove the pin count limitation of the overall converter.

The ability to re-purpose the pump capacitors is of benefit when the switched capacitor power converter uses either integrated capacitors or discrete capacitors. If discrete capacitors are used, then each capacitor uses at least one pin. Adding extra pins for the gate driver circuitry is quite painful because pins on an integrated circuit are of limited supply for a given die area. On the other hand, integrated capacitors do not eat into your pin count, but they are quite expensive and have a low capacitance per area so it is valuable to limit their use.

Typically, a controller produces control signals for activating and de-activating the switches within a switched capacitor power converter. For example, in most of the embodiments described above, a controller could have generated the driver signals that are labeled with an “A” or a “B” prefix. By controlling the on and off time of the individual switches, a controller can provide many functions. A few such functions include the ability to regulate the output voltage, the ability to shut off the power converter in the event of a fault condition, and the ability to change the gain of the switched capacitor network.

Various features, aspects, and embodiments of switched capacitor power converters have been described herein. The features, aspects, and numerous embodiments described are susceptible to combination with one another as well as to variation and modification, as will be understood by those having ordinary skill in the art. The present disclosure should, therefore, be considered to encompass such combinations, variations, and modifications. Additionally, the terms and expressions which have been employed herein are used as terms of description and not of limitation. There is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Other modifications, variations, and alternatives are also possible. Accordingly, the claims are intended to cover all such equivalents.