Patent ID: 12199122

MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments will be described with reference to drawings. However, the embodiments can be implemented with many different modes, and it will be readily appreciated by those skilled in the art that modes and details thereof can be changed in various ways without departing from the spirit and scope thereof. Thus, the present invention should not be construed as being limited to the description in the embodiments given below.

A plurality of embodiments described below can be combined as appropriate. In addition, in the case where a plurality of structure examples are described in one embodiment, the structure examples can be combined as appropriate.

In the drawings and the like, the size, the layer thickness, the region, or the like is exaggerated for clarity in some cases. Therefore, the size, the layer thickness, or the region is not limited to the illustrated scale. The drawings schematically show ideal examples, and shapes, values, or the like are not limited to shapes, values, or the like shown in the drawings.

In the drawings and the like, the same elements, elements having similar functions, elements formed of the same material, elements formed at the same time, or the like are sometimes denoted by the same reference numerals, and description thereof is not repeated in some cases.

In this specification and the like, the term “film” and the term “layer” can be interchanged with each other. For example, the term “conductive layer” can be changed into the term “conductive film” in some cases. For another example, the term “insulating film” can be changed into the term “insulating layer” in some cases.

In this specification and the like, the terms for describing arrangement such as “over” and “below” do not necessarily mean “directly over” and “directly below”, respectively, in the positional relationship between components. For example, the expression “a gate electrode over a gate insulating layer” does not exclude the case where there is an additional component between the gate insulating layer and the gate electrode.

In this specification and the like, ordinal numbers such as “first”, “second”, and “third” are used in order to avoid confusion among components, and the terms do not limit the components numerically.

In this specification and the like, “electrically connected” includes the case where connection is made through an “object having any electric function”. Here, there is no particular limitation on the “object having any electric function” as long as electric signals can be transmitted and received between the connected components. Examples of the “object having any electric function” include a switching element such as a transistor, a resistor, an inductor, a capacitor, and other elements with a variety of functions as well as an electrode and a wiring.

In this specification and the like, “voltage” often refers to a potential difference between a given potential and a reference potential (e.g., a ground potential). Thus, a voltage and a potential difference can be interchanged with each other.

In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. A channel formation region is included between the drain (a drain terminal, a drain region, or a drain electrode) and the source (a source terminal, a source region, or a source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, a channel formation region refers to a region through which current mainly flows.

Furthermore, functions of a source and a drain might be switched when a transistor of opposite polarity is employed or a direction of current flow is changed in circuit operation, for example. Thus, the terms of source and drain are interchangeable for use in this specification and the like.

Unless otherwise specified, off-state current in this specification and the like refers to a drain current of a transistor in an off state (also referred to as a non-conducting state or a cutoff state). Unless otherwise specified, the off state of an n-channel transistor refers to a state where a voltage Vgs of a gate with respect to a source is lower than a threshold voltage Vth, and the off state of a p-channel transistor refers to a state where the voltage Vgs of a gate with respect to a source is higher than the threshold voltage Vth. That is, the off-state current of an n-channel transistor sometimes refers to a drain current at the time when the voltage Vgs of a gate with respect to a source is lower than the threshold voltage Vth.

In the above description of the off-state current, the drain may be replaced with the source. That is, the off-state current sometimes refers to a source current when the transistor is in an off state. In addition, leakage current sometimes expresses the same meaning as off-state current. In this specification and the like, the off-state current sometimes refers to a current that flows between a source and a drain when a transistor is in the off state.

In this specification and the like, a metal oxide means an oxide of metal in a broad sense. Metal oxides are classified into an oxide insulator, an oxide conductor (including a transparent oxide conductor), an oxide semiconductor, and the like. For example, in the case where a metal oxide is used in a channel formation region of a transistor, the metal oxide is called an oxide semiconductor in some cases. That is, in the case where a metal oxide has at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be called a metal oxide semiconductor. Hereinafter, a transistor including a metal oxide in a channel formation region is also referred to as an “oxide semiconductor transistor” or an “OS transistor”. Furthermore, the “transistor including an oxide semiconductor” described above is also the transistor including a metal oxide in a channel formation region.

Furthermore, in this specification and the like, a metal oxide containing nitrogen is in some cases also collectively referred to as a metal oxide. A metal oxide containing nitrogen may be referred to as a metal oxynitride. The details of a metal oxide will be described later.

Embodiment 1

In this embodiment, structure examples of an imaging device of embodiments of the present invention will be described. An imaging device of one embodiment of the present invention has a structure in which a layer including a transistor formed over a semiconductor substrate and a layer including an OS transistor are stacked, and the transistor formed over the semiconductor substrate and a layer including a photodiode are stacked and bonded.

<Structure Example of Imaging Device>

FIG.1(A)is a perspective view illustrating a structure example of an imaging device10of one embodiment of the present invention.

The imaging device10includes a layer100, a layer200, and a layer300. The imaging device10has a stacked-layer structure in which the layer200is stacked over the layer100, and the layer300is stacked over the layer200as illustrated inFIG.1(A). Note that an interlayer insulating layer can be provided between the layer100and the layer200.

FIG.1(B)is a perspective view for easy understanding of the structure example of the imaging device10.

Each of the layer100, the layer200, and the layer300is provided with a device or a circuit which can function by utilizing semiconductor characteristics; the layer100is provided with a signal processing circuit110, the layer200is provided with a memory device210, and the layer300is provided with an image sensor310.

<Signal Processing Circuit110>

The signal processing circuit110has a function of controlling operation of the memory device210and the image sensor310, a function of processing image data generated by the image sensor310, and a function of transmitting and receiving data, a control signal, and the like to and from an electronic device including the imaging device10, for example.

Specifically, for example, the signal processing circuit110includes a control circuit111, a control circuit112, an image processing circuit113, and an input/output circuit114(seeFIG.1(B)).

The control circuit111has a function of supplying data to be written to the memory device210, an address signal for specifying an address of the memory device210that performs data reading/writing, a control signal for controlling operation of the memory device210, and the like. The control circuit111also has a function of receiving data read out from the memory device210.

The control circuit112has a function of receiving image data generated by the image sensor310and a function of supplying a control signal or the like for controlling the operation of the image sensor310. The control circuit112may include an analog-digital conversion circuit (Analog-Digital Converter: ADC).

The image processing circuit113has a function of performing, for example, gamma correction, dimming, toning, noise removal, distortion correction, video codic, and the like on image data generated by the image sensor310. The image processing circuit113may also have a function of performing face detection, automatic scene recognition, and high dynamic range rendering (HDR).

Here, the automatic scene recognition means that a scene such as ambient environment is recognized and exposure, focus, flash, and the like are automatically adjusted. The image processing circuit113does not need to perform all of the above-described processing steps and can select processing steps as needed.

The input/output circuit114has a function of transmitting and receiving data, a control signal, and the like to/from the electronic device including the imaging device10. For the input/output circuit114, for example, an interface, such as LVDS (Low-Voltage Differential Signaling), MIPI (Mobile Industry Processor Interface), or SPI (Serial Peripheral Interface), is used.

In addition, the signal processing circuit110may include a bus line115, a power supply circuit116, and the like.FIG.1(B)illustrates a state in which the control circuit111, the control circuit112, the image processing circuit113, and the input/output circuit114are connected through the bus line115.

The signal processing circuit110is formed with transistors formed over a semiconductor substrate SUB1. The semiconductor substrate SUB1is not particularly limited as long as a channel region of a transistor can be formed thereon. For example, a single crystal silicon substrate, a single crystal germanium substrate, a compound semiconductor substrate (such as a SiC substrate or a GaN substrate), an SOI (Silicon on Insulator) substrate, or the like can be used.

As the SOI substrate, the following substrate may be used: an SIMOX (Separation by Implanted Oxygen) substrate which is formed in such a manner that after an oxygen ion is implanted into a mirror-polished wafer, an oxide layer is formed at a certain depth from the surface and defects generated in a surface layer are eliminated by high-temperature annealing, or an SOI substrate formed by using a Smart-Cut method in which a semiconductor substrate is cleaved by utilizing growth of a minute void, which is formed by implantation of a hydrogen ion, by thermal treatment; an ELTRAN method (a registered trademark: Epitaxial Layer Transfer). A transistor formed using a single crystal substrate contains a single crystal semiconductor in a channel region.

In this embodiment, a case in which a single crystal silicon substrate is used as the semiconductor substrate SUB1will be described as an example. Hereinafter, a transistor formed over a single crystal silicon substrate is referred to as a Si transistor.

<Memory Device210>

The memory device210is connected to the control circuit111through a wiring CL that connects the layer100to the layer200. The wiring CL is formed of a conductor formed in a contact hole in the layer100and the layer200. Then, input/output of data and signals between the memory device210and the control circuit111are performed through the wiring CL.

The memory device210provided in the layer200includes a cell array211, a driver circuit221, and a driver circuit222. The cell array211is composed of a plurality of memory cells212arranged in a matrix.

The memory cell212has a function of storing data. The memory cell212may have a function of storing binary (high level and low level) data or may have a function of storing multilevel data of four or more levels. The memory cell212may have a function of storing analog data.

The driver circuit221has a function of selecting the memory cell212. Specifically, the driver circuit221has a function of supplying a signal for selecting a memory cell212which is subjected to data writing or reading (hereinafter also referred to as a selection signal) to a wiring connected to the memory cell212.

The driver circuit222has a function of writing data to the memory cell212and a function of reading out data stored in the memory cell212. Specifically, the driver circuit222has a function of supplying a potential (hereinafter also referred to as a writing potential) corresponding to data stored in the memory cell212to the wiring BL connected to the memory cell212to which data is to be written. Furthermore, the driver circuit222has a function of reading a potential corresponding to data stored in the memory cell212(hereinafter also referred to as a reading potential) and outputting the potential to the control circuit111through the wiring CL

An address signal, a clock signal, a timing signal, and the like are input from the control circuit111provided in the layer100to the driver circuit221through the wiring CL. The driver circuit221generates a selection signal with the use of these signals. Note that the timing at which a selection signal is output from the driver circuit221is controlled by a timing signal input from the control circuit111.

In addition, an address signal, a clock signal, a timing signal, data to be written to the memory cell212, and the like are supplied from the control circuit111provided in the layer100to the driver circuit222through the wiring CL. The driver circuit222generates writing potentials with the use of these signals. Note that the timing at which the writing potential is output from the driver circuit222is controlled by the timing signal input from the control circuit111.

Note that inFIG.1(B), wirings CL connected to the driver circuit221and the driver circuit222are illustrated as one wiring.

The memory cell212, the driver circuit221, and the driver circuit222are formed with OS transistors. An oxide semiconductor has a bandgap of 2.5 eV or larger, preferably 3.0 V or larger; thus, an OS transistor has a low leakage current due to thermal excitation and also has an extremely low off-state current. Note that off-state current refers to current that flows between a source and a drain when a transistor is off.

An oxide semiconductor used in a channel formation region of a transistor is preferably an oxide semiconductor containing at least one of indium (In) and zinc (Zn). Typical examples of such an oxide semiconductor include an In-M-Zn oxide (an element M is Al, Ga, Y, or Sn, for example). Reducing both impurities serving as electron donors, such as moisture or hydrogen, and oxygen vacancies can make an oxide semiconductor i-type (intrinsic) or substantially i-type. Such an oxide semiconductor can be referred to as a highly purified oxide semiconductor. Note that the details of an OS transistor will be described in Embodiment 3.

An OS transistor has an extremely low off-state current and thus is suitably used as a transistor included in the memory cell212. An off-state current per micrometer of channel width of an OS transistor can be, for example, lower than or equal to 100 zA/μm, lower than or equal to 10 zA/μm, lower than or equal to 1 zA/μm, or lower than or equal to 10 yA/μm. The use of an OS transistor in the memory cell212enables data stored in the memory cell212can be retained for a long time.

With the use of an OS transistor for the memory cell212, the refresh rate of the memory cell212can be reduced. Alternatively, refresh operation of the memory cell212can be unnecessary. In addition, the low refresh rate of the memory cell212can reduce the power consumption of the memory device210. Alternatively, eliminating the need for the refresh operation of the memory cell212can reduce circuits needed for the refresh operation.

Owing to an extremely low leakage current of an OS transistor, the memory cell212can retain multilevel data or analog data. Since off-state current of the OS transistor is not easily increased even at high temperatures, data stored in the memory cell212is less likely to be lost even at high temperatures caused by heat generation by the signal processing circuit110or the image sensor310. The use of an OS transistor can increase the reliability of the memory device210.

FIG.2(A)is a circuit diagram illustrating a configuration example of the memory cell212including an OS transistor. The memory cell212illustrated inFIG.2(A)includes a transistor213and a capacitor214. Note that “OS” in drawings indicates an OS transistor.

A gate of the transistor213is connected to a node a1, one of a source and a drain thereof is connected to one electrode of the capacitor214, and the other of the source and the drain thereof is connected to a node a2. The other electrode of the capacitor214is connected to a node a3to which a constant potential (e.g., a low power supply potential) is supplied. The node a1is connected to the driver circuit221inFIG.1(B), and the node a2is connected to the driver circuit222inFIG.1(B). Note that a node that is connected to the one of the source and the drain of the transistor213and the one electrode of the capacitor214is referred to as a node N1.

When data is written to the memory cell212, a writing potential is supplied to the node a2. Then, a selection signal (high-level potential) is supplied to the node a1to turn on the transistor213. As a result, the writing potential is written to the node N1. After that, a low-level potential is supplied to the node a1to turn off the transistor213. As a result, the node N1is brought into a floating state and the writing potential is retained.

When data stored in the memory cell212is read out, the potential of the node N1is a reading potential. A selection signal (high-level potential) is supplied to the node a1to turn on the transistor213. Accordingly, the potential of the node a2is determined in accordance with the potential of the node N1. In this manner, data stored in the memory cell212is read out.

Since an OS transistor is used as the transistor213, the potential of the node N1is held for a long period. Accordingly, the data refresh rate can be reduced and thus power consumption can be reduced. The memory device210including the memory cells212with a circuit illustrated inFIG.2(A)is referred to as a DOSRAM in this specification and the like.

For the memory cell212, a transistor having a back gate may be used.FIG.2(B)illustrates a configuration example of the memory cell212including a transistor215having a back gate. The memory cell212illustrated inFIG.2(B)includes the transistor215and the capacitor214.

The back gate of the transistor215is connected to a node a4. By applying a given potential to the node a4, a threshold voltage of the transistor215can be increased or decreased. For example, when a negative potential (a potential which is lower than the potentials of the node a2and the node N1) is applied to the back gate, the threshold voltage can be increased and the off-state current can be reduced.

As illustrated inFIG.2(C), the back gate of the transistor215may be connected to the node a1. When the back gate of the transistor215is connected to the node a1, the amount of current flowing through the transistor215can be increased when the transistor215is in an on state. Note that the description except for the back gate inFIGS.2(B) and2(C)is similar to that inFIG.2(A)and thus omitted.

Like the memory cell212, the driver circuit221and the driver circuit222illustrated inFIG.1(B)are also formed with OS transistors. That is, the memory cell212, the driver circuit221, and the driver circuit222do not include Si transistors and are formed with n-channel OS transistors. A circuit formed with transistors having the same polarity is hereinafter also referred to as a single-polarity circuit. That is, the layer200includes the memory device210including the single-polarity circuit using OS transistors.

Note that the control circuit111for controlling the memory device210is provided in the layer100, and can be formed with a CMOS circuit or the like including Si transistors. Accordingly, the control circuit111with high operation speed and high performance can be formed and the memory device210can be operated with the use of the control circuit111.

Although the configuration in which OS transistors are used in the circuit provided in the layer200is described above, a transistor whose channel formation region is formed in a film containing a semiconductor material other than an oxide semiconductor may be used. Examples of such a transistor include a transistor using an amorphous silicon film, a microcrystalline silicon film, a polycrystalline silicon film, a single crystal silicon film, an amorphous germanium film, a microcrystalline germanium film, a polycrystalline germanium film, or a single crystal germanium film for a semiconductor layer.

<Image Sensor310>

The image sensor310is formed using a transistor formed over a semiconductor substrate SUB2. The semiconductor substrate SUB2is not particularly limited as long as a channel region of a transistor can be formed thereon. The description of the semiconductor substrate SUB2is similar to that of the semiconductor substrate SUB1and thus is omitted. In this embodiment, a case where a single crystal silicon substrate is used as the semiconductor substrate SUB2will be described as an example.

The image sensor310is connected to the control circuit112by electrical connections between the wiring CL that connects the layer100to the layer200, a conductor201provided on an outermost surface of the layer200, and a conductor301provided on an outermost surface of the layer300. Input/output of data and signals between the image sensor310and the control circuit112is performed through the wiring CL, the conductor201, and the conductor301.

Here, the surface of the layer200is a surface where the memory device210is formed, and the surface of the layer300is a surface where the image sensor310is formed. In other words, the layer300is stacked over the layer200such that the surface where the image sensor310is formed is in contact with the surface where the memory device210is formed.

The image sensor310includes a pixel array311, a driver circuit321, and a driver circuit322. The pixel array311includes a plurality of pixels312arranged in a matrix.

The pixel312has a function of converting light intensity into an electric signal. An electric signal obtained by the plurality of pixels312is read out by the driver circuit322and output as image data from the image sensor310to the control circuit112.

Here, since the layer300is stacked such that the surface where the image sensor310is formed is in contact with the surface where the memory device210is formed, light20enters from a surface of the layer300where the image sensor310is not formed (seeFIG.1(B)). For this reason, the layer300is thin enough to transmit light.

The driver circuit321has a function of selecting the pixels312. Specifically, the driver circuit321has a function of supplying a selection signal for selecting the pixels312on which data reading is to be performed, to a wiring connected to the pixels312.

The driver circuit322has a function of reading out an electric signal from the pixel312. The driver circuit322may have a function of performing noise removal, analog-digital conversion, or the like with respect to the read-out electric signal. For example, in some cases, a CDS (Correlated Double Sampling) circuit may be included as a circuit for noise removal, and a column-parallel (column type) analog-digital conversion circuit may be included as a circuit for performing analog-digital conversion.

The analog-digital conversion circuit is provided in the driver circuit322or the control circuit112provided in the layer100. Alternatively, the analog-digital conversion circuit may be provided in each of the driver circuit322and the control circuit112. With the use of the analog-digital conversion circuit, image data generated by the image sensor310can be processed as a digital signal.

A clock signal, a timing signal, and the like are input from the control circuit112provided in the layer100to the driver circuit321through the wiring CL, the conductor201, and the conductor301. The driver circuit321generates a selection signal with the use of these signals. Note that the timing at which a selection signal is output from the driver circuit321is controlled by the timing signal input from the control circuit112.

The driver circuit322has a function of outputting an electric signal read out from the pixel312as image data. The driver circuit322outputs image data to the control circuit112through the conductor301, the conductor201, and the wiring CL.

Note that inFIG.1(B), the wirings CL connected to the driver circuit321and the driver circuit322are illustrated as one wiring, and the conductors201and the conductors301are each collectively illustrated.

<Pixel312>

FIG.2(D)is a circuit diagram illustrating a configuration example of the pixel312. The pixel312illustrated inFIG.2(D)includes a photoelectric conversion element313, a transistor314, a transistor315, a transistor316, a transistor317, and a capacitor318.

As the photoelectric conversion element313, for example, a pn-junction photodiode using a p-type silicon semiconductor and an n-type silicon semiconductor can be used. The photoelectric conversion element313may be a pin-junction photodiode in which an i-type silicon semiconductor layer is provided between a p-type silicon semiconductor and an n-type silicon semiconductor. Alternatively, a pin diode element using an amorphous silicon film or a microcrystalline silicon film, a diode-connected transistor, or a variable resistor utilizing a photoelectric effect may be formed using silicon, germanium, selenium, or the like.

A material capable of generating electric charge by absorbing radiation may be used for the photoelectric conversion element313. Examples of the material capable of generating electric charge by absorbing radiation include lead iodide, mercury iodide, gallium arsenide, CdTe, and CdZn.

One of a source and a drain of the transistor314is electrically connected to a cathode of the photoelectric conversion element313, and the other thereof is electrically connected to the node331(charge accumulation portion). An anode of the photoelectric conversion element313is electrically connected to a wiring334.

One of a source and a drain of the transistor315is electrically connected to the node331, and the other of the source and the drain of the transistor315is electrically connected to a wiring332. A gate of the transistor316is electrically connected to the node331, one of a source and a drain of the transistor316is electrically connected to a wiring333, and the other of the source and the drain of the transistor316is electrically connected to one of a source and a drain of the transistor317. The other of the source and the drain of the transistor317is electrically connected to the wiring332. One electrode of the capacitor318is electrically connected to the node331, and the other electrode of the capacitor318is electrically connected to the wiring334.

The transistor314has a function as a transfer transistor. A gate of the transistor314is supplied with a transfer signal TX. The transistor315has a function as a reset transistor. A gate of the transistor315is supplied with a reset signal RST. The transistor316has a function as an amplifier transistor. The transistor317has a function as a selection transistor. A gate of the transistor317is supplied with a selection signal SEL.

A high power supply potential VDD is supplied to the wiring332, and a low power supply potential VSS is supplied to the wiring334. Here, in this specification and the like, a high power supply potential is a power supply potential higher than a low power supply potential. The low power supply potential is a power supply potential lower than the high power supply potential.

Next, operation of the pixel312illustrated inFIG.2(D)will be described.

First, the transistor315is turned on so that VDD is supplied to the node331(reset operation). Then, the transistor315is turned off so that VDD is retained at the node331.

Next, the transistor314is turned on so that the potential of the node331is changed in accordance with the amount of light received by the photoelectric conversion element313(accumulation operation). After that, the transistor314is turned off so that the potential of the node331is retained.

Then, the transistor317is turned on so that a potential corresponding to the potential of the node331is output from the wiring333(selection operation). By measuring the potential of the wiring333, the amount of light received by the photoelectric conversion element313can be determined.

The above operation is performed in all the pixels312included in the pixel array311, and the driver circuit322reads out an electric signal; thus, the image sensor310can generate image data.

Note that the above configuration of the pixel312is an example, and does not include part of the circuit, part of the transistors, part of the capacitor, or the like in some cases. Alternatively, a circuit, a transistor, a capacitor, or the like that is not included in the above configuration of the pixel312is included in some cases. Alternatively, some of the power supply potentials may be different.

<Imaging Device10>

As described above, the imaging device10has a structure in which the layer200is stacked over the layer100and the layer300is stacked over the layer200, and includes the signal processing circuit110, the memory device210, and the image sensor310. The imaging device10performs analog-digital conversion, noise removal, or the other various image processing on the image data generated by the image sensor310, and then can output data to an electronic device including the imaging device10. Accordingly, the electronic device including the imaging device10can be reduced in size and weight.

The structure in which the imaging device10includes the memory device210including OS transistors and data of a captured image is stored in the memory device210enables high-speed imaging exceeding a speed of transmitting and receiving data (a data transferring speed) between the input/output circuit114and an electronic device including the imaging device10.

Since OS transistors can be formed over the layer100, the number of steps for bonding and steps for film thickness reduction can be smaller than that in the method of manufacturing an imaging device described in Non-Patent Document 1. The imaging device10may include a plurality of layers200.FIG.3illustrates an example in which the imaging device10includes two layers200. An imaging device15illustrated inFIG.3includes the layer100, a layer200a, the layer200, and the layer300. Although the description of the layer200a, which is the same as the layer200except that it does not include the conductor201, is omitted, the storage capacity of the imaging device10can be easily increased by an increase in the number of layers200.

Owing to an extremely low leakage current of the OS transistor included in the memory device210, data stored in the memory cell212can be retained for a long time. This can make the refresh rate of the memory cell212low or refresh operation unnecessary; accordingly, the power consumption of the memory device210can be reduced. Moreover, the OS transistor does not easily increase the off-state current even at high temperatures; thus, data stored in the memory cell212is unlikely to be lost even at high temperatures. That is, the reliability of the memory device210can be increased.

Note that this embodiment can be implemented in combination with the other embodiments described in this specification as appropriate.

Embodiment 2

In this embodiment, a cross-sectional structure example of the imaging device10described in the above embodiment will be described.

Note that the signal processing circuit110includes transistors formed on the semiconductor substrate SUB1and the image sensor310includes transistors formed on the semiconductor substrate SUB2, that is, transistors of the layer100and transistors of the layer300are formed on the different semiconductor substrates. Since the memory device210includes OS transistors and the layer200is formed over the layer100, the layer200is formed above the semiconductor substrate SUB1.

FIG.4andFIG.5illustrate a cross-sectional structure example of the layer100and the layer200, andFIG.6illustrates a cross-sectional structure example of the layer300.

<Layer100and Layer200>

The cross-sectional structure example of the layers100and200illustrated inFIG.4includes a transistor400a, a transistor400b, a transistor500, and a capacitor600.FIG.5(A)is a cross-sectional view of the transistor500in the channel length direction.FIG.5(B)is a cross-sectional view of the transistor500in the channel width direction.FIG.5(C)is a cross-sectional view of the transistor400ain the channel width direction.

The transistor500is a transistor including a metal oxide in its channel formation region. Since the off-state current of the transistor500is extremely low, the memory cell212including the transistor500can retain stored data for a long time. In other words, power consumption of the memory device210can be reduced because the refresh operation rate is low or the refresh operation is unnecessary.

As illustrated inFIG.4, the transistor500is provided above the transistor400aand the transistor400b, and the capacitor600is provided above the transistor500.

The transistor400ais provided over a semiconductor substrate411and includes a conductor416, an insulator415, a semiconductor region413that is formed of part of the substrate411, and a low-resistance region414aand a low-resistance region414bfunctioning as a source region and a drain region. Similarly, the transistor400bis provided on the semiconductor substrate411and includes a conductor416, an insulator415, a semiconductor region417that is formed of part of the semiconductor substrate411, and a low-resistance region418aand a low-resistance region418bfunctioning as a source region and a drain region. Note that the semiconductor substrate411corresponds to the semiconductor substrate SUB1in Embodiment 1.

As illustrated in the cross-sectional view of the transistor400ain the channel width direction inFIG.5C, a top surface and a side surface in the channel width direction of the semiconductor region413are covered with the conductor416with the insulator415therebetween. Thus, the transistors400aand400bare Fin-type transistors. The effective channel width is increased in the Fin-type transistors used as the transistors400aand400b, whereby the on-state characteristics of the transistors can be improved. In addition, since contribution of electric fields of a gate electrode can be increased, the off-state characteristics of the transistors400aand400bcan be improved.

Note that in this embodiment, an n-type single crystal silicon substrate is used as the semiconductor substrate411, for example. The semiconductor region417is part of a well of a p-type semiconductor provided in part of the semiconductor substrate411. That is, the transistor400afunctions as a p-channel transistor, and the transistor400bfunctions as an n-channel transistor.

The semiconductor substrate411may be formed using a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A structure may be employed in which silicon whose effective mass is controlled by applying stress to the crystal lattice and thereby changing the lattice spacing is used. Alternatively, the transistor400may be an HEMT (High Electron Mobility Transistor) with GaAs and GaAlAs, or the like.

The low-resistance regions414aand414band the semiconductor region417contain an element which imparts p-type conductivity, such as boron, in addition to a semiconductor material used for the semiconductor region413. The low-resistance regions418aand418bcontain an element which imparts n-type conductivity, such as arsenic or phosphorus, in addition to a semiconductor material used for the semiconductor region417.

The conductor416functioning as a gate electrode can be formed using a semiconductor material such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron, or using a conductive material such as a metal material, an alloy material, or a metal oxide material.

Note that since the work function of a conductor depends on a material of the conductor, threshold voltage of the transistor can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Moreover, in order to ensure both conductivity and embeddability, it is preferable to use stacked layers of metal materials such as tungsten and aluminum for the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.

Note that the transistor400aand the transistor400billustrated inFIG.4is just an example and the structure is not limited thereto; an appropriate transistor can be used in accordance with a circuit configuration or a driving method. For example, like the transistor500, the transistor400aand the transistor400bmay be formed using an oxide semiconductor.

An insulator420, an insulator422, an insulator424, and an insulator426are stacked in this order to cover the transistor400aand the transistor400b.

The insulator420, the insulator422, the insulator424, and the insulator426can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride.

The insulator422may have a function as a planarization film for planarizing a level difference caused by the transistor400aor the like provided below the insulator422. For example, a top surface of the insulator422may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve planarity.

The insulator424is preferably formed using a film having a barrier property that prevents diffusion of hydrogen or impurities from the semiconductor substrate411, the transistor400a, or the like into a region where the transistor500is provided. For example, for the film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used.

The diffusion of hydrogen to a semiconductor element including an oxide semiconductor, such as the transistor500, degrades the characteristics of the semiconductor element in some cases. Therefore, a film that inhibits hydrogen diffusion is preferably provided between the transistor500and the transistors400aand400b. The film that inhibits hydrogen diffusion is specifically a film from which a small amount of hydrogen is released.

The amount of released hydrogen can be measured by thermal desorption spectroscopy (TDS), for example. The amount of hydrogen released from the insulator424that is converted into hydrogen atoms per area of the insulator424is less than or equal to 10×1015atoms/cm2, preferably less than or equal to 5×1015atoms/cm2, in the TDS analysis in a film-surface temperature range of 50° C. to 500° C., for example.

Note that the permittivity of the insulator426is preferably lower than that of the insulator424. For example, the dielectric constant of the insulator426is preferably lower than 4, further preferably lower than 3. The dielectric constant of the insulator426is, for example, preferably 0.7 times or less, further preferably 0.6 times or less the dielectric constant of the insulator424. When a material with a low permittivity is used for an interlayer film, the parasitic capacitance generated between wirings can be reduced.

A conductor428, a conductor430, and the like that are connected to the capacitor600or the transistor500are embedded in the insulator420, the insulator422, the insulator424, and the insulator426. Note that the conductor428and the conductor430have a function as a plug or a wiring.

Here, a plurality of conductors that has a function as plugs or wirings are collectively denoted by the same reference numeral in some cases. Furthermore, in this specification and the like, a wiring and a plug connected to the wiring may be a single component. That is, there are cases where part of a conductor functions as a wiring and another part of the conductor functions as a plug.

As a material of each of plugs and wirings (the conductor428, the conductor430, and the like), a single layer or stacked layers of a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used. It is preferable to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is preferable to use tungsten. Alternatively, it is preferable to use a low-resistance conductive material such as aluminum or copper. The use of a low-resistance conductive material can reduce wiring resistance.

A wiring layer may be provided over the insulator426and the conductor430. For example, inFIG.4an insulator450, an insulator452, and an insulator454are provided to be stacked in this order. Furthermore, a conductor456is formed in the insulator450, the insulator452, and the insulator454. The conductor456has a function as a plug or a wiring that is connected to the transistor400aand the like. Note that the conductor456can be provided using a material similar to those for the conductor428and the conductor430.

For example, like the insulator424, the insulator450is preferably formed using an insulator having a barrier property against hydrogen. Furthermore, the conductor456preferably contains a conductor having a barrier property against hydrogen. In this case, the conductor having a barrier property against hydrogen is formed in an opening of the insulator450having a barrier property against hydrogen. With this structure, the transistor400a, the transistor400b, and the transistor500can be separated by a barrier layer, so that the diffusion of hydrogen from the transistor400aand the transistor400binto the transistor500can be inhibited.

Note that for the conductor having a barrier property against hydrogen, tantalum nitride is preferably used, for example. The use of a stack including tantalum nitride and tungsten having high conductivity can inhibit the diffusion of hydrogen from the transistor400aand the transistor400bwhile the conductivity of a wiring is kept. In that case, the tantalum nitride layer having a barrier property against hydrogen is preferably in contact with the insulator450having a barrier property against hydrogen.

A wiring layer may be provided over the insulator454and the conductor456. For example, inFIG.4, an insulator460, an insulator462, and an insulator464are provided to be stacked in this order. Furthermore, a conductor466is formed in the insulator460, the insulator462, and the insulator464. The conductor466has a function as a plug or a wiring. Note that the conductor466can be provided using a material similar to those for the conductor428and the conductor430.

For example, like the insulator424, the insulator460is preferably formed using an insulator having a barrier property against hydrogen. Furthermore, the conductor466preferably contains a conductor having a barrier property against hydrogen. In this case, the conductor having a barrier property against hydrogen is formed in an opening of the insulator460having a barrier property against hydrogen. With this structure, the transistor400a, the transistor400b, and the transistor500can be separated by a barrier layer, so that the diffusion of hydrogen from the transistor400aand the transistor400binto the transistor500can be inhibited.

Although a wiring layer including the conductor456and a wiring layer including the conductor466are described in the above, the cross-sectional structures of the layer100and the layer200are not limited to this. A wiring layer which is similar to the wiring layer including the conductor456may be provided, or three or more wiring layers which are similar to the wiring layer including the conductor456may be provided.

Here, a gate of the transistor400ais electrically connected to one of a source and a drain of the transistor500through the conductor428, the conductor430, the conductor456, the conductor466, and the like. This series of wirings corresponds to the wiring CL in Embodiment 1.

An insulator510, an insulator512, an insulator514, and an insulator516are provided to be stacked in this order over the insulator464. A substance having a barrier property against oxygen or hydrogen is preferably used for one of the insulator510, the insulator512, the insulator514, and the insulator516.

For example, the insulator510and the insulator514are preferably formed using a film having a barrier property that prevents diffusion of hydrogen or impurities from the semiconductor substrate411, the regions where the transistor400aand the transistor400bare provided, or the like into the region where the transistor500is provided. Therefore, a material similar to that for the insulator424can be used.

For the film having a barrier property against hydrogen used as the insulator510and the insulator514, for example, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used.

In particular, aluminum oxide has a high blocking effect that inhibits the passage of both oxygen and impurities such as hydrogen and moisture which are factors of a change in electrical characteristics of the transistor. Accordingly, aluminum oxide can prevent the entry of impurities such as hydrogen and moisture into the transistor500in the fabrication process and after the fabrication of the transistor. In addition, release of oxygen from the oxide included in the transistor500can be inhibited. Therefore, aluminum oxide is suitably used for a protective film of the transistor500.

The insulator512and the insulator516can be formed using a material similar to that for the insulator420, for example. When a material with a relatively low permittivity is used for the insulator, the parasitic capacitance between wirings can be reduced. A silicon oxide film, a silicon oxynitride film, or the like can be used as the insulator512and the insulator516, for example.

A conductor518, a conductor included in the transistor500(a conductor503(seeFIG.5(A))), and the like are embedded in the insulator510, the insulator512, the insulator514, and the insulator516. Note that the conductor518functions as a plug or a wiring that is connected to the capacitor600or the transistor400a. The conductor518can be provided using a material similar to those for the conductor428and the conductor430.

In particular, the conductor518in a region in contact with the insulator510and the insulator514is preferably a conductor having a barrier property against oxygen, hydrogen, and water. With this structure, the transistors400aand400band the transistor500can be separated by the layer having a barrier property against oxygen, hydrogen, and water; thus, the diffusion of hydrogen and the like from the transistor400aand the transistor400binto the transistor500can be inhibited.

The transistor500is provided above the insulator516.

As illustrated inFIGS.5(A) and5(B), the transistor500includes the conductor503positioned to be embedded in the insulator514and the insulator516; an insulator520positioned over the insulator516and the conductor503; an insulator522positioned over the insulator520; an insulator524positioned over the insulator522; an oxide530apositioned over the insulator524; an oxide530bpositioned over the oxide530a; a conductor542aand a conductor542bpositioned apart from each other over the oxide530b; an insulator580that is positioned over the conductor542aand the conductor542band includes an opening overlapping a region between the conductor542aand the conductor542b; a conductor560positioned in the opening; an insulator550positioned between the conductor560and the oxide530b, the conductor542a, the conductor542b, and the insulator580; and an oxide530cpositioned between the insulator550and the oxide530b, the conductor542a, the conductor542b, and the insulator580.

As illustrated inFIGS.5(A) and5(B), an insulator544is preferably positioned between the insulator580and the oxide530a, the oxide530b, the conductor542a, and the conductor542b. In addition, as illustrated inFIGS.5(A) and5(B), the conductor560preferably includes a conductor560aprovided inside the insulator550and a conductor560bembedded inside the conductor560a. Moreover, as illustrated inFIGS.5(A) and5(B), an insulator574is preferably positioned over the insulator580, the conductor560, and the insulator550.

Hereinafter, the oxide530a, the oxide530b, and the oxide530cmay be collectively referred to as an oxide530. The conductor542aand the conductor542bmay be collectively referred to as a conductor542.

The transistor500has a structure in which three layers of the oxide530a, the oxide530b, and the oxide530care stacked in the region where the channel is formed and its vicinity; however, the present invention is not limited thereto. For example, a single layer of the oxide530b, a two-layer structure of the oxide530band the oxide530a, a two-layer structure of the oxide530band the oxide530c, or a stacked-layer structure of four or more layers may be provided. Although the conductor560is shown to have a stacked-layer structure of two layers in the transistor500, the present invention is not limited thereto. For example, the conductor560may have a single-layer structure or a stacked-layer structure of three or more layers. Note that the transistor500illustrated inFIG.4andFIGS.5(A) and5(B)is an example, and the structure is not limited thereto; an appropriate transistor can be used in accordance with a circuit configuration or a driving method.

Here, the conductor560functions as a gate electrode of the transistor, and the conductor542aand the conductor542bfunction as a source electrode and a drain electrode. As described above, the conductor560is formed to be embedded in the opening of the insulator580and the region between the conductor542aand the conductor542b. The positions of the conductor560, the conductor542a, and the conductor542bare selected in a self-aligned manner with respect to the opening of the insulator580. That is, in the transistor500, the gate electrode can be positioned between the source electrode and the drain electrode in a self-aligned manner. Therefore, the conductor560can be formed without an alignment margin, resulting in a reduction in the area occupied by the transistor500. Accordingly, for example, miniaturization and high integration of the memory device210provided in the layer200can be achieved.

In addition, since the conductor560is formed in the region between the conductor542aand the conductor542bin a self-aligned manner, the conductor560does not have a region overlapping the conductor542aor the conductor542b. Thus, parasitic capacitance formed between the conductor560and each of the conductor542aand the conductor542bcan be reduced. As a result, the switching speed of the transistor500can be increased, and the transistor500can have high frequency characteristics.

The conductor560sometimes functions as a first gate (also referred to as top gate) electrode. The conductor503sometimes functions as a second gate (also referred to as bottom gate) electrode. In that case, the threshold voltage of the transistor500can be controlled by changing a potential applied to the conductor503independently of a potential applied to the conductor560. In particular, the threshold voltage of the transistor500can be higher than 0 V and the off-state current can be reduced by applying a negative potential to the conductor503. Thus, a drain current at the time when a potential applied to the conductor560is 0 V can be lower in the case where a negative potential is applied to the conductor503than in the case where a negative potential is not applied to the conductor503.

The conductor503is positioned to be overlapped by the oxide530and the conductor560. Thus, when potentials are applied to the conductor560and the conductor503, an electric field generated from the conductor560and an electric field generated from the conductor503are connected, so that the channel formation region formed in the oxide530can be covered. In this specification and the like, a transistor structure in which a channel formation region is electrically surrounded by electric fields of a first gate electrode and a second gate electrode is referred to as a surrounded channel (S-channel) structure.

The conductor503has a structure similar to that of the conductor518; a conductor503ais formed in contact with an inner wall of an opening in the insulator514and the insulator516, and a conductor503bis formed on the inner side.

The insulator520, the insulator522, the insulator524, and the insulator550have a function of a gate insulator.

Here, as the insulator524in contact with the oxide530, an insulator that contains oxygen more than oxygen in the stoichiometric composition is preferably used. That is, an excess-oxygen region is preferably formed in the insulator524. When such an insulator containing excess oxygen is provided in contact with the oxide530, oxygen vacancies in the oxide530can be reduced and the reliability of the transistor500can be improved.

As the insulator including an excess-oxygen region, specifically, an oxide that releases part of oxygen by heating is preferably used. An oxide that releases oxygen by heating is an oxide film in which the amount of released oxygen converted into oxygen atoms is greater than or equal to 1.0×1018atoms/cm3, preferably greater than or equal to 1.0×1019atoms/cm3, further preferably greater than or equal to 2.0×1019atoms/cm3or greater than or equal to 3.0×1020atoms/cm3in thermal desorption spectroscopy analysis (TDS analysis). Note that the temperature of the film surface in the TDS analysis is preferably higher than or equal to 100° C. and lower than or equal to 700° C., or higher than or equal to 100° C. and lower than or equal to 400° C.

In the case where the insulator524includes an excess-oxygen region, it is preferred that the insulator522have a function of inhibiting diffusion of oxygen (e.g., an oxygen atom, an oxygen molecule, or the like) (or that the insulator522do not easily transmit the above oxygen).

When the insulator522has a function of inhibiting diffusion of oxygen or impurities, oxygen contained in the oxide530is not diffused to the insulator520side, which is preferable. Furthermore, the conductor503can be prevented from reacting with oxygen contained in the insulator524or the oxide530.

For example, the insulator522is preferably formed using a single layer or stacked layers of an insulator containing what is called a high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3(BST). With miniaturization and high integration of transistors, a problem such as leakage current may arise because of a thinner gate insulator. When a high-k material is used for an insulator functioning as the gate insulator, a gate potential during operation of the transistor can be reduced while the physical thickness of the gate insulator is kept.

It is particularly preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material having a function of inhibiting diffusion of impurities, oxygen, and the like (or an insulating material through which the oxygen is less likely to pass). As the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. In the case where the insulator522is formed using such a material, the insulator522functions as a layer that inhibits release of oxygen from the oxide530and entry of impurities such as hydrogen from the periphery of the transistor500into the oxide530.

Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators, for example. Alternatively, these insulators may be subjected to nitriding treatment. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the insulator.

It is preferable that the insulator520be thermally stable. For example, when an insulator which is a high-k material is combined with silicon oxide or silicon oxynitride, the insulator520having a stacked-layer structure that has thermal stability and a high dielectric constant can be obtained because silicon oxide and silicon oxynitride have thermal stability.

Note that the insulator520, the insulator522, and the insulator524may each have a stacked-layer structure of four or more layers. In that case, without limitation to a stacked-layer structure formed of the same material, a stacked-layer structure formed of different materials may be employed.

In the transistor500, a metal oxide functioning as an oxide semiconductor is preferably used as the oxide530including a channel formation region. For example, as the oxide530, a metal oxide such as an In-M-Zn oxide (the element M is one or more kinds selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like) is preferably used. Furthermore, as the oxide530, an In—Ga oxide or an In—Zn oxide may be used.

The metal oxide functioning as the channel formation region in the oxide530has a band gap of preferably 2 eV or higher, further preferably 2.5 eV or higher. With the use of a metal oxide having such a wide band gap, the off-state current of the transistor can be reduced.

When the oxide530includes the oxide530aunder the oxide530b, it is possible to inhibit diffusion of impurities into the oxide530bfrom the components formed below the oxide530a. Moreover, including the oxide530cover the oxide530bmakes it possible to inhibit diffusion of impurities into the oxide530bfrom the components formed above the oxide530c.

Note that the oxide530preferably has a stacked-layer structure of oxides that differ in the atomic ratio of metal atoms. Specifically, the atomic ratio of the element M to the constituent elements in the metal oxide used for the oxide530ais preferably greater than the atomic ratio of the element M to the constituent elements in the metal oxide used for the oxide530b. Moreover, the atomic ratio of the element M to In in the metal oxide used for the oxide530ais preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide530b. Furthermore, the atomic ratio of In to the element Min the metal oxide used for the oxide530bis preferably greater than the atomic ratio of In to the element M in the metal oxide used for the oxide530a. A metal oxide that can be used for the oxide530aor the oxide530bcan be used for the oxide530c.

The energy of the conduction band minimum of each of the oxide530aand the oxide530cis preferably higher than the energy of the conduction band minimum of the oxide530b. In other words, the electron affinity of each of the oxide530aand the oxide530cis preferably smaller than the electron affinity of the oxide530b.

The energy level of the conduction band minimum gradually changes at junction portions of the oxide530a, the oxide530b, and the oxide530c. In other words, the energy level of the conduction band minimum at the junction portions of the oxide530a, the oxide530b, and the oxide530ccontinuously changes or is continuously connected. To obtain this, the density of defect states in a mixed layer formed at an interface between the oxide530aand the oxide530band an interface between the oxide530band the oxide530cis preferably made low.

Specifically, when the oxide530aand the oxide530bor the oxide530band the oxide530ccontain the same element (as a main component) in addition to oxygen, a mixed layer with a low density of defect states can be formed. For example, in the case where the oxide530bis an In—Ga—Zn oxide, an In—Ga—Zn oxide, a Ga—Zn oxide, gallium oxide, or the like is preferably used for the oxide530aand the oxide530c.

At this time, the oxide530bserves as a main carrier path. When the oxide530aand the oxide530chave the above structure, the density of defect states at the interface between the oxide530aand the oxide530band the interface between the oxide530band the oxide530ccan be made low. Thus, the influence of interface scattering on carrier conduction is small, and the transistor500can have a high on-state current.

The conductor542(the conductor542aand the conductor542b) functioning as the source electrode and the drain electrode is provided over the oxide530b. For the conductor542, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum; an alloy containing any of the above metal elements; an alloy containing a combination of the above metal elements; or the like. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like. Tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are preferable because they are oxidation-resistant conductive materials or materials that retain their conductivity even after absorbing oxygen.

As illustrated inFIG.5(A), a region543(a region543aand a region543b) is sometimes formed as a low-resistance region at and near the interface between the oxide530and the conductor542. In that case, the region543afunctions as one of a source region and a drain region, and the region543bfunctions as the other of the source region and the drain region. The channel formation region is formed in a region between the region543aand the region543b.

When the conductor542is provided in contact with the oxide530, the oxygen concentration in the region543sometimes decreases. In addition, a metal compound layer that contains the metal contained in the conductor542and the component of the oxide530is sometimes formed in the region543. In such a case, the carrier density of the region543increases, and the region543becomes a low-resistance region.

The insulator544is provided to cover the conductor542and inhibits oxidation of the conductor542. At this time, the insulator544may be provided to cover a side surface of the oxide530and to be in contact with the insulator524.

A metal oxide containing one or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used as the insulator544.

For the insulator544, it is particularly preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate). In particular, hafnium aluminate has higher heat resistance than a hafnium oxide film. Therefore, hafnium aluminate is preferable because it is less likely to be crystallized by heat treatment in a later step. Note that the insulator544is not an essential component when the conductor542is an oxidation-resistant material or does not significantly lose its conductivity even after absorbing oxygen. Design is appropriately set in consideration of required transistor characteristics.

The insulator550functions as a gate insulator. The insulator550is preferably positioned in contact with the inner side (the top surface and the side surface) of the oxide530c. The insulator550is preferably formed using an insulator from which oxygen is released by heating. For example, the insulator550is an oxide film in which the amount of released oxygen converted into oxygen atoms is greater than or equal to 1.0×1018atoms/cm3, preferably greater than or equal to 1.0×1019atoms/cm3, further preferably greater than or equal to 2.0×1019atoms/cm3or greater than or equal to 3.0×1020atoms/cm3in thermal desorption spectroscopy analysis (TDS analysis). Note that the temperature of the film surface in the TDS analysis is preferably higher than or equal to 100° C. and lower than or equal to 700° C.

Specifically, silicon oxide containing excess oxygen, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, or the like can be used. In particular, silicon oxide and silicon oxynitride, which have thermal stability, are preferable.

When an insulator from which oxygen is released by heating is provided as the insulator550in contact with the top surface of the oxide530c, oxygen can be efficiently supplied from the insulator550to the channel formation region of the oxide530bthrough the oxide530c. Furthermore, as in the insulator524, the concentration of impurities such as water or hydrogen in the insulator550is preferably reduced. The thickness of the insulator550is preferably greater than or equal to 1 nm and less than or equal to 20 nm.

In order to efficiently supply excess oxygen in the insulator550to the oxide530, a metal oxide may be provided between the insulator550and the conductor560. The metal oxide preferably inhibits diffusion of oxygen from the insulator550to the conductor560. Providing the metal oxide that inhibits diffusion of oxygen inhibits diffusion of excess oxygen from the insulator550to the conductor560. That is, a reduction in the amount of excess oxygen supplied to the oxide530can be inhibited. Moreover, oxidization of the conductor560due to excess oxygen can be inhibited. For the metal oxide, a material that can be used for the insulator544is used.

Although the conductor560functioning as the first gate electrode has a two-layer structure inFIGS.5(A) and5(B), a single-layer structure or a stacked-layer structure of three or more layers may be employed.

For the conductor560a, it is preferable to use a conductive material having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N2O, NO, NO2, and the like), and a copper atom. Alternatively, it is preferable to use a conductive material having a function of inhibiting diffusion of oxygen (e.g., an oxygen atom, an oxygen molecule, and the like). When the conductor560ahas a function of inhibiting oxygen diffusion, it is possible to prevent a reduction in conductivity of the conductor560bdue to oxidation caused by oxygen contained in the insulator550. As a conductive material having a function of inhibiting oxygen diffusion, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used.

The conductor560bis preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. The conductor560balso functions as a wiring and thus is preferably formed using a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as its main component can be used. The conductor560bmay have a stacked-layer structure, for example, a stacked-layer structure of any of the above conductive materials and titanium or titanium nitride.

The insulator580is provided over the conductor542with the insulator544therebetween. The insulator580preferably includes an excess-oxygen region. For example, the insulator580preferably contains silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, a resin, or the like. In particular, silicon oxide and silicon oxynitride, which have thermal stability, are preferable. In particular, silicon oxide and porous silicon oxide, in which an excess-oxygen region can be easily formed in a later step, are preferable.

The insulator580preferably includes an excess-oxygen region. When the insulator580from which oxygen is released by heating is provided in contact with the oxide530c, oxygen in the insulator580can be efficiently supplied to the oxide530through the oxide530c. Note that the concentration of impurities such as water or hydrogen in the insulator580is preferably lowered.

The opening of the insulator580is formed to overlap a region between the conductor542aand the conductor542b. Accordingly, the conductor560is formed to be embedded in the opening of the insulator580and the region between the conductor542aand the conductor542b.

The gate length needs to be short for miniaturization of the semiconductor device, but it is necessary to prevent a reduction in conductivity of the conductor560. When the conductor560is made thick to achieve this, the conductor560might have a shape with a high aspect ratio. In this embodiment, the conductor560is provided to be embedded in the opening of the insulator580; hence, even when the conductor560has a shape with a high aspect ratio, the conductor560can be formed without collapsing during the process.

The insulator574is preferably provided in contact with the top surface of the insulator580, the top surface of the conductor560, and the top surface of the insulator550. When the insulator574is deposited by a sputtering method, excess-oxygen regions can be provided in the insulator550and the insulator580. Accordingly, oxygen can be supplied from the excess-oxygen regions to the oxide530.

For example, a metal oxide containing one or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used as the insulator574.

In particular, aluminum oxide has a high barrier property, and even a thin aluminum oxide film having a thickness of greater than or equal to 0.5 nm and less than or equal to 3.0 nm can inhibit diffusion of hydrogen and nitrogen. Accordingly, aluminum oxide deposited by a sputtering method serves as an oxygen supply source and can also have a function of a barrier film against impurities such as hydrogen.

An insulator581functioning as an interlayer film is preferably provided over the insulator574. As in the insulator524or the like, the concentration of impurities such as water or hydrogen in the insulator581is preferably lowered.

A conductor540aand a conductor540bare positioned in openings formed in the insulator581, the insulator574, the insulator580, and the insulator544. The conductor540aand the conductor540bare provided to face each other with the conductor560therebetween. The structures of the conductor540aand the conductor540bare similar to a structure of a conductor546and a conductor548that will be described later.

An insulator582is provided over the insulator581. A substance having a barrier property against oxygen or hydrogen is preferably used for the insulator582. Therefore, a material similar to that for the insulator514can be used for the insulator582. For the insulator582, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide is preferably used, for example.

In particular, aluminum oxide has a high blocking effect that inhibits the passage of both oxygen and impurities such as hydrogen and moisture which are factors of a change in electrical characteristics of the transistor. Accordingly, aluminum oxide can prevent the entry of impurities such as hydrogen and moisture into the transistor500in the fabrication process and after the fabrication of the transistor. In addition, release of oxygen from the oxide included in the transistor500can be inhibited. Therefore, aluminum oxide is suitably used for a protective film of the transistor500.

An insulator586is provided over the insulator582. For the insulator586, a material similar to that for the insulator420can be used. When a material with a relatively low permittivity is used for the insulator, the parasitic capacitance between wirings can be reduced. For example, a silicon oxide film, a silicon oxynitride film, or the like can be used for the insulator586.

The conductor546, the conductor548, and the like are embedded in the insulator520, the insulator522, the insulator524, the insulator544, the insulator580, the insulator574, the insulator581, the insulator582, and the insulator586.

The conductor546and the conductor548have functions as plugs or wirings that are connected to the capacitor600, the transistor500, or the transistors400aand400b. The conductor546and the conductor548can be provided using a material similar to those for the conductor428and the conductor430.

In addition, the capacitor600is provided above the transistor500. The capacitor600includes a conductor610, a conductor620, and an insulator630.

A conductor612may be provided over the conductor546and the conductor548. The conductor612has a function of a plug or a wiring that is connected to the transistor500. The conductor610has a function of an electrode of the capacitor600. The conductor612and the conductor610can be formed at the same time.

The conductor612and the conductor610can be formed using a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium; a metal nitride film containing any of the above elements as its component (a tantalum nitride film, a titanium nitride film, a molybdenum nitride film, or a tungsten nitride film); or the like. Alternatively, it is possible to use a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added.

Although the conductor612and the conductor610each of which has a single-layer structure are illustrated inFIG.4, the structure is not limited thereto; a stacked-layer structure of two or more layers may be employed. For example, between a conductor having a barrier property and a conductor having high conductivity, a conductor that is highly adhesive to the conductor having a barrier property and the conductor having high conductivity may be formed.

The conductor620is provided to overlap the conductor610with the insulator630therebetween. The conductor620can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is particularly preferable to use tungsten. In the case where the conductor620is formed concurrently with another component such as a conductor, Cu (copper), Al (aluminum), or the like, which is a low-resistance metal material, can be used.

An insulator650is provided over the conductor620and the insulator630. The insulator650can be provided using a material similar to that for the insulator420. The insulator650may function as a planarization film that covers an uneven shape thereunder.

A conductor646and a conductor648are embedded in the insulator650. The conductor646and the conductor648have a function as a plug connected to the transistor500, the transistor400a, the transistor400b, and the like. The conductor646and the conductor648can be provided using a material similar to those of the conductor428and the conductor430.

A conductor660is provided over the conductor646and the conductor648. The conductor660can be provided using a material similar to those of the conductor612and the conductor610. The conductor660corresponds to the conductor201in Embodiment 1. In other words, electrical connection with the layer300can be obtained through the conductor660.

Note that a layer including an element similar to the transistor500and the capacitor600may be provided over the transistor500and the capacitor600. When a plurality of layers including the transistor500and the capacitor600are provided, the storage capacity of the memory device210can be increased.

With the use of the above structure, a change in electrical characteristics can be inhibited and reliability can be improved in the layer200including a transistor including an oxide semiconductor. Alternatively, a transistor including an oxide semiconductor and having a high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor and having a low off-state current can be provided. Alternatively, the memory device210with low power consumption can be provided. Alternatively, the memory device210using a transistor including an oxide semiconductor can be miniaturized or highly integrated.

<Layer300>

FIG.6illustrates a cross-sectional structure example of the layer300. The cross-sectional structure example of the layer300inFIG.6includes a transistor700aand a pn-junction photodiode700c. Note that the photodiode700cfunctions as the photoelectric conversion element313in Embodiment 1.

The transistor700ais provided over a semiconductor substrate711and includes a conductor716, an insulator715, a semiconductor region713that is formed of part of the semiconductor substrate711, and a low-resistance region714aand a low-resistance region714bfunctioning as a source region and a drain region. Note that the semiconductor substrate711corresponds to the semiconductor substrate SUB2in Embodiment 1.

Note that in this embodiment, an n-type single crystal silicon substrate is used as the semiconductor substrate711, for example. Part of the semiconductor substrate711functions as an n-type semiconductor of the photodiode700cand a p-type semiconductor region718provided in the semiconductor substrate711functions as a p-type semiconductor of the photodiode700c. The transistor700afunctions as a p-channel transistor. An n-channel transistor can be formed in a manner similar to that of the above-described transistor400bthough not being illustrated inFIG.6.

The low-resistance region714a, the low-resistance region714b, and the p-type semiconductor region718contain an element that imparts p-type conductivity, such as boron, in addition to a semiconductor material used for the semiconductor region713.

The conductor716functioning as a gate electrode can be formed using a semiconductor material such as silicon containing the element which imparts n-type conductivity, such as arsenic or phosphorus, or the element which imparts p-type conductivity, such as boron, or using a conductive material such as a metal material, an alloy material, or a metal oxide material.

Note that the work function depends on a material of the conductor; thus, the threshold voltage of the transistor can be adjusted by changing the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Moreover, in order to ensure both conductivity and embeddability, it is preferable to use a stacked layer of metal materials such as tungsten and aluminum for the conductor, and it is particularly preferable to use tungsten in terms of heat resistance.

An insulator720, an insulator722, an insulator724, and an insulator726are sequentially stacked to cover the transistor700aand the photodiode700c.

The insulator720, the insulator722, the insulator724, and the insulator726can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride.

The insulator722may have a function of a planarization film for eliminating a level difference caused by the transistor700aor the like underlying the insulator722. For example, a top surface of the insulator722may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve planarity. By the CMP treatment, unevenness of a sample surface can be reduced, and coverage with an insulating layer or a conductive layer to be formed later can be increased. For the insulator722, a low-dielectric constant material (a low-k material), a siloxane-based resin, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), or the like may be used.

A conductor728, a conductor730, and the like are embedded in the insulator720, the insulator722, the insulator724, and the insulator726. Note that the conductor728and the conductor730have a function as plugs or wirings.

As a material of each of the plugs and wirings (the conductor728, the conductor730, and the like), a single layer or a stacked layer of a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material can be used. It is preferable to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is preferable to use tungsten. Alternatively, a low-resistance conductive material such as aluminum or copper is preferably used. The use of a low-resistance conductive material can reduce wiring resistance.

A wiring layer may be provided over the insulator726and the conductor730. For example, inFIG.6, an insulator750, an insulator752, and an insulator754are stacked sequentially. Furthermore, a conductor756is formed in the insulator750, the insulator752, and the insulator754. The conductor756has a function as a plug or a wiring that is connected to the transistor700aor the like. Note that the conductor756can be provided using a material similar to those for the conductor728and the conductor730. The insulator750, the insulator752, and the insulator754can be provided using a material similar to that for the insulator720and the like.

A wiring layer may be provided over the insulator754and the conductor756. For example, inFIG.6, an insulator760, an insulator762, and an insulator764are provided to be stacked in this order. Furthermore, a conductor766is formed in the insulator760, the insulator762, and the insulator764. The conductor766has a function as a plug or a wiring. Note that the conductor766can be provided using a material similar to those for the conductor728and the conductor730. The insulator760, the insulator762, and the insulator764can be formed using a material similar to that for the insulator720or the like.

Although a wiring layer including the conductor756and a wiring layer including the conductor766are described in the above, the cross-sectional structure of the layer300is not limited to this. A wiring layer which is similar to the wiring layer including the conductor756may be provided, or three or more wiring layers which are similar to the wiring layer including the conductor756may be provided.

A conductor770is provided over the conductor766. The conductor770can be provided using a material similar to those for the conductor728and the conductor730. The conductor770corresponds to the conductor301in Embodiment 1. In other words, electrical connection with the layer100and the layer200can be obtained through the conductor770.

<Imaging Device10>

The imaging device10is formed by bonding the above-described layers100and200to the layer300.FIG.7illustrates a cross-sectional structure example of the imaging device10.

The imaging device10is formed by bonding surfaces of the layer100and the layer200, over the semiconductor substrate411, where the transistor400a, the transistor400b, the transistor500, the capacitor600, and the like are provided to a surface of the layer300where the transistor700a, the photodiode700c, and the like are provided. Note that the imaging device10illustrated inFIG.7is different from the imaging device10inFIG.4andFIG.6in that some reference numerals, the layer including the conductor466, and the layer including the conductor756are omitted and the scale of part of the drawing is changed.

InFIG.7, the layers100and200are bonded to the layer300, whereby the conductor660and the conductor770are electrically connected. After the bonding of the layers100and200to the layer300, the semiconductor substrate711included in the layer300is reduced in thickness, whereby the imaging device10is formed.

The photodiode700ccaptures light transmitted through the semiconductor substrate711and converts the light to an electric signal. The electric signal converted by the photodiode700cis converted into a digital signal in an analog-digital conversion circuit included in the signal processing circuit110or the image sensor310. The electric signal converted by the photodiode700cis transmitted to the signal processing circuit110through the conductor770and the conductor660.

Structure Example 1 of Transistor

AlthoughFIG.4andFIG.5illustrate a structure example in which the conductor542that functions as a source electrode or a drain electrode is in contact with the oxide530, the structure of the OS transistor is not limited to this. For example, a structure in which the conductor542is not provided and the resistance of the oxide530is selectively reduced so as to form a source region or a drain region in the oxide530bcan be employed. A structure example of such a transistor is illustrated inFIG.8.

FIG.8(A)is a cross-sectional view of a transistor500A in the channel length direction, andFIG.8(B)is a cross-sectional view of the transistor500A in the channel width direction. Note that the transistor500A illustrated inFIG.8is a modification example of the transistor500illustrated inFIG.5. Therefore, what is different from the transistor500is mainly described to avoid repeated description.

In the transistor500A, a metal oxide functioning as an oxide semiconductor can be used as the oxide530including a channel formation region, as in the transistor500.

When an element that forms an oxygen vacancy or an element that is bonded to an oxygen vacancy is added to the oxide530, the carrier density is increased and the resistance is lowered in some cases. Typical examples of an element that lowers the resistance of the oxide530include boron and phosphorus. Moreover, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, a rare gas, or the like may be used. Typical examples of the rare gas are helium, neon, argon, krypton, and xenon.

Note that the concentration of the above element is measured by secondary ion mass spectrometry (SIMS) or the like.

Boron and phosphorus are particularly preferable because an apparatus in a manufacturing line for amorphous silicon or low-temperature polysilicon can be used. Using the existing facility can reduce capital investment.

The region543(the region543aand the region543b) illustrated inFIG.8is a region where the above element is added to the oxide530b. The region543can be formed with the use of a dummy gate, for example.

For example, a dummy gate is provided over the oxide530b, and an element that lowers the resistance of the oxide530bis added using the dummy gate as a mask. That is, the element is added to regions of the oxide530that are not overlapped by the dummy gate, whereby the region543is formed. Note that as a method for adding the element, an ion implantation method by which an ionized source gas is subjected to mass separation and then added, an ion doping method by which an ionized source gas is added without mass separation, a plasma immersion ion implantation method, or the like can be used.

Next, an insulating film to be the insulator544and an insulating film to be an insulator545may be formed over the oxide530band the dummy gate. The insulating film to be the insulator544and the insulating film to be the insulator545are stacked, whereby a region where the region543is overlapped by the oxide530cand the insulator550can be provided.

Specifically, after an insulating film to be the insulator580is provided over the insulating film to be the insulator545, the insulating film to be the insulator580is subjected to CMP (Chemical Mechanical Polishing) treatment, whereby part of the insulating film to be the insulator580is removed and the dummy gate is exposed. Then, when the dummy gate is removed, part of the insulator544in contact with the dummy gate is preferably also removed. Thus, the insulator545and the insulator544are exposed at the side surface of the opening provided in the insulator580, and the region543provided in the oxide530bis partly exposed at the bottom surface of the opening. Next, an oxide film to be the oxide530c, an insulating film to be the insulator550, and a conductive film to be the conductor560are formed in this order in the opening, and then, the oxide film to be the oxide530c, the insulating film to be the insulator550, and the conductive film to be the conductor560are partly removed by CMP treatment or the like until the insulator580is exposed; thus, the transistor illustrated inFIG.8can be formed.

Note that the insulator544and the insulator545are not essential components. Design is appropriately set in consideration of required transistor characteristics.

Since the existing device can be used as the transistor illustrated inFIG.8and the conductor542is not provided, a cost reduction can be achieved.

Structure Example 2 of Transistor

AlthoughFIG.4andFIG.5illustrate a structure example in which the conductor560that functions as a gate is formed in an opening of the insulator580, the structure of the OS transistor is not limited to this. For example, a structure in which the insulator is provided above the conductor can be employed. A structure example of such a transistor is illustrated inFIG.9andFIG.10.

FIG.9(A)is a top view of a transistor andFIG.9(B)is a perspective view of the transistor.FIG.10(A)is a cross-sectional view taken along X1-X2inFIG.9(A), andFIG.10(B)is a cross-sectional view taken along Y1-Y2inFIG.9(A).

The transistor illustrated inFIG.9andFIG.10includes a conductor BGE having a function as a back gate, an insulator BGI having a function as a gate insulating film, an oxide semiconductor S, an insulator FGI having a function as a gate insulating film, a conductor FGE having a function as a front gate, and a conductor WE having a function as a wiring. A conductor PE has a function as a plug for connecting the conductor WE to the oxide S, the conductor BGE, or the conductor FGE. Note that an example in which the oxide semiconductor S includes three layers of oxides S1, S2, and S3is shown here.

<Electrical Characteristics of Transistors>

Next, electrical characteristics of an OS transistor will be described below. A transistor including a first gate and a second gate is described below as an example. In the transistor including the first gate and the second gate, the threshold voltage can be controlled by applying different potentials to the first gate and the second gate. For example, by applying a negative potential to the second gate, the threshold voltage of the transistor can be higher than 0 V and the off-state current can be reduced. That is, when a negative potential is applied to the second gate electrode, a drain current when the potential applied to the first electrode is 0 V can be reduced.

When impurity such as hydrogen is added to an oxide semiconductor, the carrier density is increased in some cases. For example, hydrogen added to an oxide semiconductor reacts with oxygen bonded to a metal atom to be water, so that an oxygen vacancy is formed in some cases. Entry of hydrogen into the oxygen vacancy increases carrier density. Furthermore, in some cases, bonding of part of hydrogen to oxygen bonded to a metal atom causes generation of an electron serving as a carrier. That is, the oxide semiconductor to which an impurity such as hydrogen is added becomes n-type and has a reduced resistance.

Therefore, the resistance of the oxide semiconductor can be selectively reduced. That is, a region which has a low carrier density and functions as a semiconductor functioning as a channel formation region and a low-resistance region which has a high carrier density and functions as a source region or a drain region can be provided in the oxide semiconductor.

Here, evaluated is the influence of the structure of a low-resistance region and a high-resistance region provided in the oxide semiconductor on electrical characteristics of the transistor in the case where different potentials are applied to the first gate and the second gate.

[Structure of Transistor]

FIGS.11(A) and11(C)are each a cross-sectional view of a transistor used for the electrical characteristics evaluation. For clarity of the drawings, some components are not illustrated inFIGS.11(A) and11(C).

The transistor illustrated inFIGS.11(A) and11(C)includes a conductor TGE that functions as a first gate, an insulator TGI that functions as a first gate insulating film, an insulator SW that functions as a sidewall provided on a side surface of the first gate, an oxide semiconductor S, a conductor BGE that functions as a second gate, and an insulator BGI that functions as a second gate insulator. The insulator BGI has a three-layer structure formed of a first layer in contact with the conductor BGE, a second layer over the first layer, and a third layer over the second layer. Note that the third layer is in contact with the oxide semiconductor S.

Here, the oxide semiconductor S included in the transistor illustrated inFIG.11(A)has an n+region and an i region overlapping with the conductor TGE. On the other hand, the oxide semiconductor S included in the transistor illustrated inFIG.11(C)has the n+region, the i region overlapping with the conductor TGE, and an n−region between the n+region and the i region.

Note that the n+region functions as a source region or a drain region and has a high carrier density and reduced resistance. The i region functions as a channel formation region and is a high-resistance region whose carrier density is lower than the n+region. Then region has a lower carrier density than the n+region and a higher carrier density than the i region.

Although not illustrated, the n+region of the oxide semiconductor S is in contact with an S/D electrode functioning as a source or a drain.

[Results of Electrical Characteristics Evaluation]

The Id-Vg characteristics of the transistor illustrated inFIG.11(A)and the transistor illustrated inFIG.11(C)are calculated to evaluate electrical characteristics of the transistors.

Here, as an index of the electrical characteristics of a transistor, the amount of change (hereinafter also referred to as ΔVsh) in the threshold voltage (hereinafter also referred to as Vsh) of the transistor is used. Note that in the Id-Vg characteristics, Vsh is defined as the value of Vg when Id=1.0×10−12[A] is satisfied.

Note that the Id-Vg characteristics are characteristics of a change in a current between the source and the drain (hereinafter also referred to as a drain current (Id)) when a potential applied to the conductor TGE functioning as a first gate of the transistor (hereinafter also referred to as a gate potential (Vg)) is changed from a first value to a second value.

Here, evaluated are changes in a drain current (Id) when a potential between a source and a drain (hereinafter also referred to as a drain potential Vd) is set to +0.1 V and a potential between the source and the conductor TGE functioning as a first gate is changed from −1 V to +4 V.

A device simulator “Atlas” developed by Silvaco Inc. is used for the calculation. Table 1 lists parameters used for the calculation. Note that Eg represents an energy gap, Nc represents the effective density of states in the conduction band, and Nv represents the effective density of states in the valence band.

TABLE 1SoftwareAtlas 2D produced by Silvaco Inc.StructureChannel length (L)350nmChannel width (W)350nmBGEWork function5.0eVFilm thickness (wiring)20nmLength in L direction510nmBGIThird layerRelative permittivity4.1Film thickness10nmSecond layerRelative permittivity16.4Film thickness10nmFirst layerRelative permittivity4.1Film thickness10nmOSElectron affinity4.5eVEg2.9eVRelative permittivity15Electron mobility20cm2/VsHole mobility0.01cm2/VsNc5E+18cm−3Nv5E+18cm−3Film thickness15nmn+regionLength in L direction655 or 700nmCarrier concentration5E+18cm−3n−regionLength in L direction45 or 0nmCarrier concentration1E+17cm−3TGIRelative permittivity4.1Film thickness10nmSWRelative permittivity4.1Width15nmTGEWork function5.0eVFilm thickness20nmLength in L direction350nmS/D electrodeWork function4.5eV

In the transistor illustrated inFIG.11(A), one of the n+regions is set to 700 nm, and one of then regions is set to 0 nm. In the transistor illustrated inFIG.11(C), one of the n+regions is set to 655 nm and one of the n regions is set to 45 nm. Each of the transistor illustrated inFIG.11(A)and the transistor illustrated inFIG.11(C)has a structure in which the second gate is larger than the i region. Note that in this evaluation, a potential of the conductor BGE functioning as a second gate (hereinafter also referred to as a backgate potential (Vbg)) is set to 0.00 V, −3.00 V, or −6.00 V.

FIG.11(B)shows the results of the Id-Vg characteristics obtained by the calculation of the transistor illustrated inFIG.11(A). The amount of change in the threshold voltage (ΔVsh) of the transistor when the backgate potential is set to −3.00 V is +1.2 V as compared with that when the backgate potential is set to 0.00 V. The amount of change in the threshold voltage (ΔVsh) of the transistor when the backgate potential is set to −6.00 V is +2.3 V as compared with that when the backgate potential is set to 0.00 V. That is, the amount of change in the threshold voltage (ΔVsh) of the transistor when the backgate potential is set to −6.00 V is +1.1 V as compared with that when the backgate potential is set to −3.00 V. Therefore, even when the potential of the conductor BGE functioning as a second gate is made higher, the amount of change in the threshold voltage of the transistor is hardly changed. In addition, even when the backgate potential is increased, the rising characteristics are not changed.

FIG.11(D)shows the results of the Id-Vg characteristics obtained by the calculation of the transistor illustrated inFIG.11(C). The amount of change in the threshold voltage (ΔVsh) of the transistor when the backgate potential is set to −3.00 V is +1.2 V as compared with that when the backgate potential is set to 0.00 V. The amount of change in the threshold voltage (ΔVsh) of the transistor when the backgate potential is set to −6.00 V is +3.5 V as compared with that when the backgate potential is set to 0.00 V. That is, the amount of change in the threshold voltage (ΔVsh) of the transistor when the backgate potential is set to −6.00 V is +2.3 V as compared with that when the backgate potential is set to −3.00 V. Therefore, the higher the potential of the conductor BGE functioning as a second gate is made, the larger the amount of change in the threshold voltage of the transistor becomes. As the backgate potential is increased, the rising characteristics become worse.

As described above, it is found that in the transistor illustrated inFIG.11(C), the higher the potential of the conductor BGE functioning as a second gate is made, the larger the amount of change in the threshold voltage of the transistor becomes. In contrast, in the transistor illustrated inFIG.11(A), the amount of change in the threshold voltage of the transistor is not changed even when the potential of the conductor BGE functioning as a second gate is increased.

Note that this embodiment can be implemented in combination with the other embodiments described in this specification as appropriate.

Embodiment 3

In this embodiment, the composition of a metal oxide that can be used in the OS transistor described in the above embodiment, will be described.

<Composition of Metal Oxide>

In this specification and the like, “CAAC (c-axis aligned crystal)” or “CAC (Cloud-Aligned Composite)” might be stated. Note that CAAC refers to an example of a crystal structure, and CAC refers to an example of a function or a material composition.

A CAC-OS or a CAC-metal oxide has a conducting function in a part of the material and has an insulating function in a part of the material, and has a function of a semiconductor as the whole material. Note that in the case where the CAC-OS or the CAC-metal oxide is used in a channel formation region of a transistor, the conducting function is a function of allowing electrons (or holes) serving as carriers to flow, and the insulating function is a function of not allowing electrons serving as carriers to flow. By the complementary action of the conducting function and the insulating function, the CAC-OS or the CAC-metal oxide can have a switching function (On/Off function). In the CAC-OS or the CAC-metal oxide, separation of the functions can maximize each function.

In addition, the CAC-OS or the CAC-metal oxide includes conductive regions and insulating regions. The conductive regions have the above-described conducting function, and the insulating regions have the above-described insulating function. In some cases, the conductive regions and the insulating regions in the material are separated at the nanoparticle level. In some cases, the conductive regions and the insulating regions are unevenly distributed in the material. The conductive regions are observed to be coupled in a cloud-like manner with their boundaries blurred, in some cases.

Furthermore, in the CAC-OS or the CAC-metal oxide, the conductive regions and the insulating regions each have a size of greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 0.5 nm and less than or equal to 3 nm and are dispersed in the material, in some cases.

The CAC-OS or the CAC-metal oxide is formed of components having different bandgaps. For example, the CAC-OS or the CAC-metal oxide is formed of a component having a wide gap due to the insulating region and a component having a narrow gap due to the conductive region. When carriers flow in such a structure, carriers mainly flow in the component having a narrow gap. The component having a narrow gap complements the component having a wide gap, and carriers also flow in the component having a wide gap in conjunction with the component having a narrow gap. Therefore, in the case where the above-described CAC-OS or CAC-metal oxide is used in a channel formation region of a transistor, high current drive capability in the on state of the transistor, that is, high on-state current and high field-effect mobility, can be obtained.

In other words, the CAC-OS or the CAC-metal oxide can also be called a matrix composite or a metal matrix composite.

<Structure of Metal Oxide>

An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single crystal oxide semiconductor. Examples of a non-single crystal oxide semiconductor include a CAAC-OS (c-axis aligned crystalline oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor.

Note that as a metal semiconductor used for a semiconductor of a transistor, a thin film having high crystallinity is preferably used. With the use of the thin film, the stability or the reliability of the transistor can be improved. Examples of the thin film include a thin film of a single-crystal oxide semiconductor and a thin film of a polycrystalline oxide semiconductor. However, to form the thin film of a single-crystal oxide semiconductor or the thin film of a polycrystalline oxide semiconductor over a substrate, a high-temperature process or a laser heating process is needed. Thus, the manufacturing cost is increased, and in addition, the throughput is decreased.

Non-Patent Document 2 and Non-Patent Document 3 have reported that an In—Ga—Zn oxide having a CAAC structure (referred to as CAAC-IGZO) was found in 2009. It has been reported that CAAC-IGZO has c-axis alignment, a crystal grain boundary is not clearly observed in CAAC-IGZO, and CAAC-IGZO can be formed over a substrate at low temperatures. It has also been reported that a transistor using CAAC-IGZO has excellent electrical characteristics and high reliability.

In addition, in 2013, an In—Ga—Zn oxide having an nc structure (referred to as nc-IGZO) was found (see Non-Patent Document 4). It has been reported that nc-IGZO has periodic atomic arrangement in a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) and there is no regularity of crystal orientation between different regions.

Non-Patent Document 5 and Non-Patent Document 6 have shown a change in average crystal size due to electron beam irradiation to thin films of the above CAAC-IGZO, the above nc-IGZO, and IGZO having low crystallinity. In the thin film of IGZO having low crystallinity, crystalline IGZO with a crystal size of approximately 1 nm was observed even before the electron beam irradiation. Thus, it has been reported that the existence of a completely amorphous structure was not observed in IGZO. In addition, it has been shown that the thin film of CAAC-IGZO and the thin film of nc-IGZO each have higher stability to electron beam irradiation than the thin film of IGZO having low crystallinity. Thus, the thin film of CAAC-IGZO or the thin film of nc-IGZO is preferably used for a semiconductor of a transistor.

The CAAC-OS has c-axis alignment, a plurality of nanocrystals are connected in the a-b plane direction, and its crystal structure has distortion. Note that distortion refers to a portion where the direction of a lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in a region where the plurality of nanocrystals are connected.

The nanocrystal is basically a hexagon but is not always a regular hexagon and is a non-regular hexagon in some cases. Furthermore, a pentagonal lattice arrangement, a heptagonal lattice arrangement, and the like are included in the distortion in some cases. Note that a clear crystal grain boundary (also referred to as grain boundary) cannot be observed even in the vicinity of distortion in the CAAC-OS. That is, formation of a crystal grain boundary is inhibited by the distortion of a lattice arrangement. This is probably because the CAAC-OS can tolerate distortion owing to a low density of oxygen atom arrangement in an a-b plane direction, a change in interatomic bond distance by replacement of a metal element, and the like.

Furthermore, the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter, In layer) and a layer containing the element M, zinc, and oxygen (hereinafter, (M, Zn) layer) are stacked. Note that indium and the element M can be replaced with each other, and when the element M of the (M, Zn) layer is replaced by indium, the layer can also be referred to as an (In, M, Zn) layer. Furthermore, when indium of the In layer is replaced by the element M, the layer can also be referred to as an (In, M) layer.

The CAAC-OS is an oxide semiconductor with high crystallinity. By contrast, in the CAAC-OS, it can be said that a reduction in electron mobility due to the crystal grain boundary is less likely to occur because a clear crystal grain boundary cannot be observed. Moreover, since the crystallinity of an oxide semiconductor might be decreased by entry of impurities, formation of defects, or the like, the CAAC-OS can be regarded as an oxide semiconductor that has small amounts of impurities and defects (oxygen vacancies or the like). Thus, an oxide semiconductor including a CAAC-OS is physically stable. Therefore, the oxide semiconductor including a CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable with respect to high temperature in the manufacturing process (what is called thermal budget). Accordingly, the use of the CAAC-OS for the OS transistor can extend a degree of freedom of the manufacturing process.

The nc-OS has a periodic atomic arrangement in a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm). In addition, no regularity of crystal orientation is observed between different nanocrystals in the nc-OS. Thus, the orientation is not observed in the whole film. Accordingly, in some cases, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.

The a-like OS is an oxide semiconductor that has a structure between those of the nc-OS and the amorphous oxide semiconductor. The a-like OS has a void or a low-density region. That is, the a-like OS has low crystallinity as compared with the nc-OS and the CAAC-OS.

An oxide semiconductor has various structures with different properties. Two or more kinds among the amorphous oxide semiconductor, the polycrystalline oxide semiconductor, the a-like OS, the nc-OS, and the CAAC-OS may be included in an oxide semiconductor of one embodiment of the present invention.

<Transistor Including Oxide Semiconductor>

Next, the case where the above oxide semiconductor is used for a transistor will be described.

Note that when the above oxide semiconductor is used for a transistor, a transistor with high field-effect mobility can be achieved. In addition, a transistor with high reliability can be achieved.

Non-Patent Document 7 shows that the transistor using an oxide semiconductor has an extremely low leakage current in an off state; specifically, the off-state current per micrometer in the channel width of the transistor is of the order of yA/μm (10−24A/μm). For example, a low-power-consumption CPU utilizing a characteristic of low leakage current of the transistor using an oxide semiconductor is disclosed (see Non-Patent Document 8).

Furthermore, application of a transistor using an oxide semiconductor to a display device that utilizes the characteristic of a low leakage current of the transistor has been reported (see Non-Patent Document 9). In the display device, a displayed image is changed several tens of times per second. The number of times an image is changed per second is referred to as a refresh rate. The refresh rate is also referred to as driving frequency. Such high-speed screen change that is hard for human eyes to recognize is considered as a cause of eyestrain. Thus, it is proposed that the refresh rate of the display device is lowered to reduce the number of times of image rewriting. Moreover, driving with a lowered refresh rate enables the power consumption of the display device to be reduced. Such a driving method is referred to as idling stop (IDS) driving.

An oxide semiconductor with a low carrier density is preferably used for a transistor. In the case where the carrier density of an oxide semiconductor film is lowered, the impurity concentration in the oxide semiconductor film is lowered to lower the density of defect states. In this specification and the like, a state with a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic state. For example, the carrier density of the oxide semiconductor is lower than 8×1011/cm3, preferably lower than 1×1011/cm3, more preferably lower than 1×1010/cm3, and greater than or equal to 1×10−9/cm3.

In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states and accordingly has a low density of trap states in some cases.

Furthermore, charges trapped by the trap states in the oxide semiconductor take a long time to disappear and may behave like fixed charges. Thus, a transistor whose channel region is formed in an oxide semiconductor with a high density of trap states has unstable electrical characteristics in some cases.

Thus, in order to stabilize electrical characteristics of the transistor, reducing the impurity concentration in the oxide semiconductor is effective. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferred that the impurity concentration in an adjacent film be also reduced. Examples of impurities include hydrogen, nitrogen, an alkali metal, an alkaline earth metal, iron, nickel, and silicon.

<Impurity>

Here, the influence of each impurity in the oxide semiconductor will be described.

When silicon or carbon, which is one of the Group 14 elements, is contained in the oxide semiconductor, defect states are formed in the oxide semiconductor. Thus, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon in the vicinity of an interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are set lower than or equal to 2×1018atoms/cm3, preferably lower than or equal to 2×1017atoms/cm3.

Furthermore, when the oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states are formed and carriers are generated in some cases. Thus, a transistor using an oxide semiconductor that contains an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. Accordingly, it is preferred to reduce the concentration of an alkali metal or an alkaline earth metal in the oxide semiconductor. Specifically, the concentration of an alkali metal or an alkaline earth metal in the oxide semiconductor obtained by SIMS is set lower than or equal to 1×1018atoms/cm3, preferably lower than or equal to 2×1016atoms/cm3.

Furthermore, when containing nitrogen, the oxide semiconductor easily becomes n-type by generation of electrons serving as carriers and an increase of carrier density. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. For this reason, nitrogen in the oxide semiconductor is preferably reduced as much as possible; the nitrogen concentration in the oxide semiconductor obtained by SIMS is set, for example, lower than 5×1019atoms/cm3, preferably lower than or equal to 5×1018atoms/cm3, more preferably lower than or equal to 1×1018atoms/cm3, and still more preferably lower than or equal to 5×1017atoms/cm3.

Furthermore, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to be water, and thus forms an oxygen vacancy in some cases. Entry of hydrogen into the oxygen vacancy generates an electron serving as a carrier in some cases. Furthermore, in some cases, bonding of part of hydrogen to oxygen bonded to a metal atom causes generation of an electron serving as a carrier. Thus, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Accordingly, hydrogen in the oxide semiconductor is preferably reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor obtained by SIMS is lower than 1×1020atoms/cm3, preferably lower than 1×1019atoms/cm3, more preferably lower than 5×1018atoms/cm3, and still more preferably lower than 1×1018atoms/cm3.

When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be given.

The discovery of the CAAC structure and the nc structure has contributed to an improvement in electrical characteristics and reliability of a transistor using an oxide semiconductor having the CAAC structure or the nc structure, a reduction in manufacturing cost, and an improvement in throughput. Furthermore, applications of the transistor to a display device and an LSI utilizing the characteristics of a low leakage current of the transistor have been studied.

Note that this embodiment can be implemented in combination with the other embodiments described in this specification as appropriate.

Embodiment 4

In this embodiment, examples of electronic devices each including the imaging device10described in the above embodiment will be described.

FIG.12(A)illustrates a surveillance camera which includes a housing951, a lens952, a support portion953, and the like. The surveillance camera can include the imaging device of one embodiment of the present invention as a component for obtaining an image. Thus, the surveillance camera can be reduced in size and weight. Furthermore, a highly reliable surveillance camera can be provided even in a high temperature environment. Note that a surveillance camera is a name in common use and the name does not limit the use thereof. A device that has a function as a surveillance camera is also referred to as a camera or a video camera, for example.

FIG.12(B)illustrates a video camera which includes a first housing971, a second housing972, a display portion973, operation buttons974, a lens975, a connection portion976, and the like. The operation button974and the lens975are provided on the first housing971, and the display portion973is provided on the second housing972. The video camera can include the imaging device of one embodiment of the present invention as a component for obtaining an image. Thus, the video camera can be reduced in size and weight. Furthermore, a video camera capable of performing imaging for a long time with low power consumption can be provided. A video camera capable of high-speed imaging can be provided.

FIG.12(C)illustrates a digital camera which includes a housing961, a shutter button962, a microphone963, a light-emitting portion967, a lens965, and the like. The digital camera can include the imaging device of one embodiment of the present invention as a component for obtaining an image. Thus, the digital camera can be reduced in size and weight. Furthermore, a digital camera capable of high-speed imaging can be provided.

FIG.12(D)illustrates a mobile phone (smartphone) which includes a display portion982, a microphone987, a speaker984, a camera989, an input/output terminal986, an operation button985, and the like in a housing981. A touch panel function of the display portion982enables input and output of information. The mobile phone can include the imaging device of one embodiment of the present invention as a component for obtaining an image. Thus, the mobile phone can be reduced in size and weight. Furthermore, a mobile phone capable of high-speed imaging can be provided. A mobile phone in which power consumption of an imaging operation is reduced can be provided.

A robot900illustrated inFIG.13includes an arithmetic device910, an illuminance sensor901, a microphone902, an upper camera903, a speaker904, a display905, a lower camera906, an obstacle sensor907, and a moving mechanism908. The upper camera903and the lower camera906each have a function of taking an image of the surroundings of the robot900. The obstacle sensor907can detect, with the use of the moving mechanism908, the presence of an obstacle in the direction where the robot900advances. The robot900can move safely by recognizing the surroundings with the upper camera903, the lower camera906, and the obstacle sensor907.

In the robot900, the upper camera903and the lower camera906can each include the imaging device of one embodiment of the present invention as a component for obtaining an image. Thus, the robot can be reduced in size and weight. Furthermore, a highly reliable robot capable of transferring safely even in a high temperature environment can be provided.

Note that the electronic devices, the functions of the electronic devices, its effects, and the like described in this embodiment can be combined as appropriate with the description of another electronic device. This embodiment can be implemented in combination with the other embodiments described in this specification as appropriate.

EXAMPLE

In this example, a DRAM (DOSRAM) in which a transistor using an oxide semiconductor is used for a memory cell was fabricated, and it was confirmed that the fabricated DOSRAM can retain the stored content for 100000 seconds. Furthermore, it was estimated that a reduction in refresh rate can achieve a 50% reduction in power consumption at maximum as compared with a conventional DRAM.

Table 2 shows the specifications of the fabricated DOSRAM. In the DOSRAM, a 60-nm OSFET process is used for the memory cell and an oxide semiconductor transistor is used. For a driver circuit that has a function of selecting a memory cell, writing data to a memory cell, reading out data stored in a memory cell, or the like, a 65-nm CMOS process is employed and a Si transistor is used.

TABLE 2CMOS 65 nmTechnologyOSFET 60 nmSupply VoltageVDD: 1.2 V/VPP: 3.3 VCell element1Tr1CCs value3.5fFDensity64kbitCycle time10nsRetention time100,000sec.I/O width×32

FIG.14(A)shows a Shmoo plot at 25° C. andFIG.14(B)shows a Shmoo plot at 85° C. It is found that operation with a cycle time of 10 ns can be performed under conditions that the supply voltage is 1.2 V and the temperature range is from 25° C. to 85° C. This satisfies the specifications of the conventional DRAM; accordingly, the fabricated DRAM can probably maintain compatibility with the conventional DRAM.

FIG.15shows memory retention characteristics (Retention characteristics) at 85° C. Favorable data retention characteristics with a rate of correct bit of 99.97% are shown after 105seconds.

FIG.16shows the estimation results of the power consumption (Power Consumption Ratio) in the case where power gating is performed in a DRAM, a DOSRAM, and a DOSRAM. InFIG.16, it is assumed that the oxide semiconductor transistor can be miniaturized and the same cell size and memory capacitance as a DRAM can be achieved.FIG.16(A)shows an I/O number of ×4 and memory capacity of 4 Gbit,FIG.16(B)shows an I/O number of ×8 and memory capacity of 8 Gbit, andFIG.16(C)shows an I/O number of ×16 and memory capacitance of 16 Gbit.

Since refresh operation is unnecessary for a DOSRAM, power needed for the refresh operation can be saved. Furthermore, power gating can reduce standby power. The proportion of the power required for the refresh operation increases as the memory density is higher and the I/O number is smaller. As a result, it was estimated that the total power can be reduced by 50% at maximum (seeFIG.16(A)). Note that for the calculation, “Micron DDR4 SDRAM System-Power Calculator” produced by Micron Technology, Inc. was used.

REFERENCE NUMERALS

a1: node, a2: node, a3: node, a4: node, N1: node, S: oxide, S1: oxide, SUB1: semiconductor substrate, SUB2: semiconductor substrate,10: imaging device,15: imaging device,20: light,100: layer,110: signal processing circuit,111: control circuit,112: control circuit,113: image processing circuit,114: input/output circuit,115: bus line,116: power supply circuit,200: layer,200a: layer,201: conductor,210: memory device,211: cell array,212: memory cell,213: transistor,214: capacitor,215: transistor,221: driver circuit,222: driver circuit,300: layer,301: conductor,310: image sensor,311: pixel array,312: pixel,313: photoelectric conversion element,314: transistor,315: transistor,316: transistor,317: transistor,318: capacitor,321: driver circuit,322: driver circuit,331: node,332: wiring,333: wiring,334: wiring,400: transistor,400a: transistor,400b: transistor,411: semiconductor substrate,413: semiconductor region,414a: low-resistance region,414b: low-resistance region,415: insulator,416: conductor,417: semiconductor region,418a: low-resistance region,418b: low-resistance region,420: insulator,422: insulator,424: insulator,426: insulator,428: conductor,430: conductor,450: insulator,452: insulator,454: insulator,456: conductor,460: insulator,462: insulator,464: insulator,466: conductor,500: transistor,500A: transistor,503: conductor,503a: conductor,503b: conductor,510: insulator,512: insulator,514: insulator,516: insulator,518: conductor,520: insulator,522: insulator,524: insulator,530: oxide,530a: oxide,530b: oxide,530c: oxide,540a: conductor,540b: conductor,542: conductor,542a: conductor,542b: conductor,543: region,543a: region,543b: region,544: insulator,545: insulator,546: conductor,548: conductor,550: insulator,560: conductor,560a: conductor,560b: conductor,574: insulator,580: insulator,581: insulator,582: insulator,586: insulator,600: capacitor,610: conductor,612: conductor,620: conductor,630: insulator,646: conductor,648: conductor,650: insulator,660: conductor,700a: transistor,700c: photodiode,711: semiconductor substrate,713: semiconductor region,714a: low-resistance region,714b: low-resistance region,715: insulator,716: conductor,718: p-type semiconductor region,720: insulator,722: insulator,724: insulator,726: insulator,728: conductor,730: conductor,750: insulator,752: insulator,754: insulator,756: conductor,760: insulator,762: insulator,764: insulator,766: conductor,770: conductor,900: robot,901: illuminance sensor,902: microphone,903: upper camera,904: speaker,905: display,906: lower camera,907: obstacle sensor,908: moving mechanism,910: arithmetic device,951: housing,952: lens,953: support portion,961: housing,962: shutter button,963: microphone,965: lens,967: light-emitting portion,971: housing,972: housing,973: display portion,974: button,975: lens,976: connection portion,981: housing,982: display portion,984: speaker,985: button,986: input/output terminal,987: microphone,989: camera.