Patent ID: 12231270

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

While this invention is susceptible of embodiment in many different forms, there is shown in the drawings and will herein be described in detail several specific embodiments with the understanding that the present disclosure is to be considered as an exemplification of the principles of the invention and is not intended to limit the invention to the embodiments illustrated.

DICE Applique System Embodiment

FIG.1shows an applique embodiment of the invention, which aids performance of a conventional MUOS radio embedded in the system. The system uses a receive array comprising a plurality of any of spatially and/or polarization diverse antenna feeds (for example, four feeds from spatially separated antennas as shown in thisFIG.1a-1d) to receive analog signals-in-space; filtering those analog signals-in-space to remove unwanted signal energy outside the 360-380 MHz MUOS Base-to-User (B2U) band, denoted by the B2U bandpass filter (BPF) (2a-2d) shown on each antenna feed; and passing those filtered signals through a low-noise amplifier (LNA) (5a-5d) to boost signal gain for subsequent processing stages, with gain adjustment, shown inFIG.1using variable-loss attenuators (ATT's) (3a-3d) adapted using shared automatic gain control (AGC) circuitry (4), to avoid desensitization of those processing stages as interferers appear and disappear in the environment. The B2U BPF must especially suppress any energy present in the 300-320 MHz MUOS User-to-Base (U2B) band, which is 40 MHz from the B2U band, as the received signal environment is likely to contain strong U2B emissions generated by the MUOS radio (18) embedded in the appliqué.

Example receive feeds that could be employed here include, but are not limited to: feeds derived from spatially separated antennas; feeds derived from dual-polarized antennas, including feeds from a single dual-polarized antenna; feeds derived from an RF mode-forming matrix, e.g., a Butler mode former fed by a uniform circular, linear, or rectangular array; feeds from a beam-forming network, e.g., in which the feeds are coupled to a set of beams substantively pointing at a MUOS SV; or any combination thereof. The key requirement is that at least one of these feeds receive the Base-to-User signal emitted by a MUOS SV at a signal-to-noise ratio (SNR) that allows reception of that signal in the absence of co-channel interference (CCI), and at least two of the feeds receive the CCI with a linearly independent gain and phase (complex gain, under complex-baseband representation) that allows the CCI to be substantively removed using linear combining operations.

In this embodiment, the signals received by each antenna in MUOS B2U band is then directly converted down to complex-baseband by passing each LNA (5a-5d) output signal-in-space {xLNA(t,m)}m=14through a Dual Downconverting Mixer (6a-6d)) that effectively generates complex-baseband mixer output signal xbase(t,m)=sLO(t)xLNA(t,m) on receive feed m, where “( )” denotes the complex conjugation operation, and where sLO(t)=exp(j2 fLOt) is a complex sinusoid with frequency fLO=370 MHZ, generated in a local oscillator (LO)(7) preferably shared by all the mixers in the system. The resultant complex-baseband signals {xbase(t,m)}m=14should each have substantive energy between −10 MHZ (corresponding to the received signal component at 360 MHz) and +10 MHz (corresponding to the received signal component at 380 MHZ). The real or “in-phase” (I) and imaginary or “quadrature” (Q) components or “rails” of each complex-baseband mixer output signal is then filtered by a pair of lowpass filters (dual LPF) (8a-8d) that has substantively flat gain within a ±10 MHz “passband” covering the downconverted B2U signal band, and that substantively suppresses energy outside a “stopband” determined by the LPF design; and passed through a pair of analog-to-digital converters (ADC's) (9a-9d) that convert each rail to a sampled and digitized representation of the B2U signal. In the embodiment shown inFIG.1, the ADC sampling rate fADCis set to 40 million samples per second (Msps), which requires the LPF stopband to begin at ±30 MHz to provide a ±10 MHz passband that is “protected” against aliasing from interferers outside that band; this is sufficient bandwidth to suppress vestigial U2B received emissions present after the B2U BPF (covering −50 MHz to −30 MHz in the downconverted frequency spectrum).

The digitized ADC output signal on each receiver feed is then input to a DICE Digital Signal Processing Subsystem (10; further described below, seeFIG.4), which substantively removes co-channel interference (CCI) from the desired MUOS B2U signals transmitted from MUOS satellite vehicles (SV's) in the system's field of view (FoV). The resultant cleaned up B2U signals are then output in complex format from the Subsystem.

In the applique embodiment shown inFIG.1, the DICE Digital Signal Processing Subsystem output signals are further processed to convert them from digital to analog representation, by applying a digital-to-analog converter (DAC's) (11) with a 40 Msps interpolation rate to each rail of the output signal (Dual DAC), followed by a Dual LPF (13) to remove frequency-translated images induced by the Dual DAC (11). The ADC sampling rate and interpolation rate are controlled by a clock (12) that connects to each Dual ADC (9a-9d) and Dual DAC (11), as well as the DICE Digital Signal Processing Subsystem (4). The resultant analog complex-baseband signal ybase(t) is then directly frequency-shifted to the 360-380 MHz band using a Dual Upconverting Mixer (14) that generates output radio-frequency (RF) signal-in-space yRF(t)=Re{ybase(t)sLO(t)}, where sLO(t) is the complex sinusoid LO output signal preferably shared by all the Dual Downconverting Mixers (6a-6d). Using the same LO signal in every mixer in the system has two primary advantages. First, it ensures that any time-varying phase noise present in the mixer signal is shared in every receiver feed, except for a constant phase offset induced by differences in pathlength between the LO (7) and mixers (6a-6d;14). Time-varying phase noise induces reciprocal mixing components in the presence of strong interference, which can place an upper limit on the degree of interference excision possible using linear combining methods. However, if that phase noise is shared by each mixer, then those reciprocal mixing components will also be shared and can be removed by linear combining methods, thereby removing that upper limit. Second, using the same LO signal in every mixer ensures that any frequency offset from the desired LO frequency fLOis shared in the Downconverting (6a-6d) and Upconverting (14) Mixers. Therefore, any frequency offset induced in the complex-baseband signal at the output of the Downconverting Mixers (6a-6d) will be removed by the Upconverting Mixer (14). Both of these advantages allow the use of a relatively inexpensive LO (7) in this appliqué embodiment, which need not be synchronized to the other digital circuitry in the system.

The Dual Upconverting Mixer output signal is then adjusted in power by an attenuator (ATT) (15), the result is passed through a final B2U BPF (16), and into Port1of a circulator (17), which routes the BPF output signal to a MUOS radio (18) connected to Port2of the circulator. Port2of the circulator (17) also routes MUOS user-to-base (U2B) signals transmitted from the MUOS radio (18) to a U2B BPF (19) connected to Port3, which passes energy received over the 300-320 MHz MUOS U2B band into a transmit antenna (20), and which suppresses energy received over the MUOS B2U band that might otherwise propagate into the MUOS radio due to nonideal performance of the circulator. In alternate embodiments of the invention, the transmit antenna (20) can also be shared with one of the receive antennas, however, this requires an additional diplexer component to maintain isolation between the B2U and U2B frequency bands.

FIG.2is a high-level block diagram of an alternate DICE appliqué system, in a configuration where the received B2U signals are directly converted to an intermediate frequency (IF), by passing each LNA output signals through not a Downconverting Mixer but a second B2U BPF (22a-22d) to remove residual energy that may be present in the MUOS U2B band, and then through an ADC (23a-23d) with a 118.272 Msps sampling rate. This sampling rate aliases the MUOS B2U and U2B bands, and their negative-frequency images, to separate, nonoverlapping IF bands within the +59.136 MHz bandwidth of the ADC output signal, as depicted inFIG.3. Specifically, the 118.272 Msps ADC sampling rate aliases the 360-380 MHz MUOS B2U band to 5.184-25.184 MHZ, and the 300-320 MHz MUOS U2B band to 38.816-54.186 MHZ, such that the aliased B2U and U2B bands are separated by 9.632 MHz. This is sufficient frequency separation to allow any residual U2B energy in that band, e.g., from MUOS radios operating inside or within the physical vicinity of the DICE appliqué, to be suppressed by subsequent digital signal processing operations.

In the alias-to-IF system embodiment shown inFIG.2, the unprocessed and real radio signals sensed on a plurality of any of spatially and/or polarization diverse antenna feeds (1a-1d) are converted from analog to digital format and frequency shifted (in one embodiment) from the 360-680 MHz MUOS B2U band to a new Intermediate Frequency (‘IF’) frequency using a subsampling direct-conversion operation. The digitized ADC output signals are then passed to a DICE Digital Signal Processing Subsystem (10) that substantively removes co-channel interference present in the IF B2U band, and generates a complex-baseband signal with a 59.136 Msps sample rate. This digital signal is then converted to analog complex-baseband format using a Dual DAC (11) with a 59.136 Msps interpolation rate, and passed through the same operations shown inFIG.1to upconvert that signal to the MUOS B2U band and pass it into a MUOS radio (18). The DICE Digital Signal Processing Subsystem (10) thus takes as its input each digitized IF antenna feed and completes the transformation of the analog representation of the signal as received into a digital representation of the intended signal, filtering out the non-signal aspects (co-channel interference) incorporated into the analog transmission by the environmental factors experienced, including the hardware of the receiving unit.

The alias-to-IF receiver implementation provides a number of advantages in the DICE system. These include:Lack of a mixer, which reduces cost, SWAP, and linearity of the receiver.Absence of mixer phase noise, which can adversely affect coherence of the receive signals if applied independently to each antenna.Absence of in-phase/quadrature imbalance, which can introduce interference images and dispersion into the received signal. In addition, the use of Dual ADC's to process pairs of antenna feeds can reduce effects of independent aperture jitter between those ADC's servicing those feeds.

Drawbacks of this implementation include:Reliance on in-band BPF's, which can limit capability to devices built to operate in that band, especially if operating in a band where economic forces have not minimized cost of those devices. In particular, the quality of the adaptive beamforming can be greatly compromised by cross-antenna frequency dispersion induced by those BPF's.Requirement for a high-quality ADC with a bandwidth that greatly exceeds its sampling rate. The resultant system can also be highly sensitive to aperture jitter caused by oversampling of that ADC.Need for additional digital processing to convert the real-IF output signal to complex-baseband format.Potential need for precise calibration and compensation for frequency errors in the upconversion stage.

For this reason, while a digital subsampling approach can substantively reduce part-count for the receiver, other receiver designs may be superior in other applications, or for system instantiations that address other signal bands, e.g., cellular WCDMA bands.

The direct-to-IF applique shown inFIG.2presents a known weakness: the need to exactly upconvert the DAC output signal to the MUOS frequency band. In contrast, the direct-frequency conversion applique shown inFIG.1downconverts the MUOS B2U band to baseband, and upconverts the DICE subsystem output back to the MUOS B2U band, using the same LO. This eliminated the need to calibrate and compensate for any error in the DAC upconverter, because any LO frequency error during the downconversion operations will be cancelled by the corresponding upconversion operation.

In alternate embodiments of the invention, the DICE system can connect digitally to, or be integrated with, the MUOS radio to arbitrary degree; and can be integrated with purpose-built antenna arrays that maximally exploit capabilities of the system. An embodiment implemented as an appliqué can be operate at the lower PHY and be effected without need for implementation of TRANSEC, COMSEC, or higher abstraction layers. However, the ability to operate without any intercommunication with either the host radio using the system, or the antenna arrays used by the system, is a benefit of the invention that can increase both its utility to existing radio infrastructure, and cost of integrating the system into larger networks. The ability to operate at the lower PHY, and without use of TRANSEC, COMSEC, or higher-layer operations, is also expected to provide operational benefit in many use scenarios.

In further alternate embodiments of the invention, the DICE system can provide multiple outputs, each corresponding to a separate network element in the field of view of the receive array. This capability can be used to remove multiple-access interference (MAI) received by the array, and to boost both the potential link-rate of the radio (by allowing simultaneous access to multiple network nodes) and to reduce the uplink capacity of the network.

Although a MUOS reception use scenario is described here, the system can be used in numerous non-MUOS applications, including but not limited to: reception of commercial cellular waveforms, reception of signals in wireless local area networks (WLAN's) and wireless personal area networks (WPAN's), GNSS reception in the presence of jamming, and operation of wireless repeater networks.

FIG.3depicts the effect of the alias-to-IF process for the MUOS B2U and U2B bands, using the 118.272 Msps ADC sampling rate employed in the embodiment shown inFIG.2. The B2U and U2B bands are depicted here as asymmetric energy distributions, in order to better illustrate the effect of the receiver on these spectra. Excluding addition of noise intermodulation products introduced by nonlinearity in the receive LNA (5a-5d) for each feed, the dominant effect of the receiver is to suppress out-of-band energy using the Rx BPF, and to alias all of the remaining signal components into the [59.136 MHz +59.136 MHz] ADC output frequency band. As the ADC input and output signals are both real, both the positive frequency components of the input signals, and their reversed-spectrum images at negative frequencies, are aliased into this band. As a result of this operation, the B2U band aliases into the [+5.184 MHz +25.184 MHz] band, with a reversed-spectrum image at the corresponding negative frequencies, and the U2B reversed-spectrum negative frequency image aliases into the [+34.816 MHz +54.816 MHz] band, with a non-reversed image at the corresponding negative frequencies. This provides a 10.368 MHz lower transition band and 9.632 MHz upper transition band between the B2U positive frequency image and the interfering B2U and U2B negative-frequency images, respectively. These images are suppressed further in subsequent digital processing steps implemented in the FPGA (30).

DICE Digital Signal Processing Subsystem

FIG.4shows a top-level block diagram of the digital operations of the DICE digital signal processing subsystem (10) implemented in the alias-to-IF embodiment shown inFIG.2. The digital signal processing subsystem embodiment shown here comprises a field-programmable gate array (FPGA) (30) to perform highly-regular, high rate digital signal processing operations; a digital signal processing (DSP) element (31) to implement more complex algorithms performed by the invention, in particular, calculation of beamforming network (BFN) weights employed in the FPGA (30) to substantively excise interference present in the MUOS B2U band; and a External Memory Interface (EMIF) bus (32) to route pertinent data between the FPGA (30) and DSP element (32). The system shown inFIG.4also depicts a Beamforming network element (34) implemented in the FPGA (30) that uses beamforming combiner weights, obtained through an implementation of an algorithm in the DSP element (31) (that exploits underlying features that are synchronous with known 10 ms periodicities, also referred to as framing intervals, known framing intervals, frame buffers, data frames, or just frames in the MUOS signal) via the External Memory Interface (EMIF) bus (32) used to transport small amounts of data to the DSP element (31) in order to implement the beamforming weight adaptation algorithm and to transfer computed weights back to the FPGA (30). The FPGA (30) also possesses input and output data buffers (respectively38,39;40,42) that can be used to perform ancillary tasks such as calculation and reporting of ADC output quality metrics, calibration of output frequency offset for the IQ RF Upconverter, and calculation and reporting of output quality metrics, and report these metrics over the EMIF bus (32).

Within the FPGA (30), the incoming received signals output from the set of four ADC “feeds” (not shown here, seeFIG.2), operating at a 118.272 Msps sampling rate, is each passed through a dedicated digital downconverter and analysis filter bank (33a-33d; with one such further explained below and inFIG.5) performing decimation and analysis operations that downconverts that signal into 256 frequency channels, each separated by 115.5 kHz in frequency, and each with a data rate of 231 kilosamples per second (ksps), i.e., covering a 29.568 MHz bandwidth and oversampled by a factor of 2. Preferentially, the Analysis filter bank (53) is implemented using a method allowing substantively perfect reconstruction of the complex-baseband input signal in an accompanying Synthesis Filter Bank (35); this technique is used to reconstruct the beamformed channels in the Synthesis Filter-Bank (35) and Interpolation filter (37). Several methods for accomplishing this are well known to those skilled in the art.

The frequency channels for each feed are then transported to a beamforming network element (BFN) (34), which linearly combines each frequency channel over the “feed” dimension as described below to substantively excise interference present in that frequency channel. The resultant beamformed output frequency channels are then passed to a frequency Synthesis filter bank (35) that combines those frequency channels into a complex-baseband signal with a 29.568 Msps data rate, which signal next is modified by a combiner (36) that multiplies that signal by a frequency shift that compensates for offset error in the LO (7) shown inFIG.2, and passes the compensated signal to an 1:2 interpolator element (37) which interpolates that signal to a 59.136 Msps data rate. This signal is then output to the Dual DAC (11) shown inFIG.2.

In addition to these operations, portions of the ADC output data, BFN input data, and interpolator output data are passed to an ADC buffer (38), Frame buffer (39), and DAC buffer (40), respectively, and routed to the DSP element (31) over the EMIF buffer (32). This data is used to control the AGC (4) shown inFIG.2; to compute input/output (I/O) metrics describing operation of the invention; and to adapt both the linear combining weights used in the BFN (34), and to compute LO offset values kLOused to correct errors between the intended and actual LO signal applied to the Dual Upconversion Mixer (14) shown inFIG.2. The BFN weights and LO offset (or complex sinusoid that implements that offset) are also input over the EMIF bus (32) respectively from the DSP element (31) to the BFN Weight Buffer (41) and LO Buffer (42) for use within the FPGA (30).

The DICE digital signal processing subsystem embodiment shown inFIG.4works within the alias-to-IF embodiment, by using the FPGA (30) to convert the IF signal output from each ADC feed into a digital complex-baseband representation of the intended signal, by filtering out the undesired adjacent-channel interference (ACI) received along with the desired MUOS B2U signals received by the system, including MUOS U2B emissions generated within the hardware of the receiving unit. The FPGA (30) digitally converts the IF signal on each feed to a complex-baseband signal comprising a real in-phase (I) component or “rail” (I-rail), and an imaginary quadrature (Q) component or rail (Q-rail), such that the center of the MUOS B2U band is frequency-shifted to a 400 KHz frequency offset from baseband; separate the complex-baseband signal into frequency channels that allow at least independent processing of the component of each 5 MHz MUOS subband modulated by the MUOS B2U signal; linearly combine the antenna feeds over each frequency channel, using beamforming combiner weights that substantively excises interference and boosts the signal-to-noise ratio of the MUOS B2U signal received over that channel; and recombine the frequency channels into a complex-baseband signal covering the full MUOS B2U band. A processed digital complex-baseband output signal is converted to analog format using a pair of digital-to-analog combiner (DAC) operating against the in-phase (I) and quadrature (Q) rails of the complex-baseband signal; frequency-shifted back to the 360-380 MHz band in an IQ RF Upconverter operation; and output to the attached radio (18) as shown inFIG.1andFIG.2.

FIG.5describes the digital downconversion and analysis filter bank (33a-33d) implemented on each feed inFIG.4, which provides the frequency-channelized inputs to the BFN, and which provides the data used to compute BFN weights inside the DSP element. The data output from each ADC is first downconverted by −⅛ Hz normalized frequency (−14.784 MHz at the 118.272 ADC sampling rate) (50), using a pair of 1:2 decimators (halfband LPF's and 1:2 subsamplers) (51a,51b) separated by a −¼ Hz normalized frequency shift (52). This results in a complex-baseband signal with a 29.568 MHz data rate, in which the MUOS U2B band has been substantively eliminated and the MUOS B2U band has been downconverted to a 400 KHz center frequency.

Each complex-baseband signal feed is then channelized by an Analysis filter bank (53), which separates data on that feed into frequency channels covering the 29.568 MHz downconverter output band, thus allowing independent processing of each 5 MHz B2U subband at a minimum, with each channel providing data with a reduced sampling rate on the order of the bandwidth of the frequency channels. In the alias-to-IF embodiment shown here, the Analysis filter bank (53) produces 256 frequency channels separated by 115.5 kHz, with a 115.5 kHz half-power bandwidth and 231 kHz full-power bandwidth (50% overlap factor), and with an output rate of 231 kilosamples (thousands of samples) per second (ksps) on each channel (54), in order to facilitate implementation of simplified adaptation algorithms in the DSP element. In alternate embodiments, the output rate can be reduced to 115.5 ksps, trading higher complexity during analysis and subsequent synthesis operations against lower complexity during intervening beamforming operations. The analysis filter bank approach allows both narrowband and wideband co-channel interference (CCI) emissions to be cancelled efficiently, and can significantly increase the number of narrowband CCI emissions that can be eliminated by the beamforming network.

Segments of the analysis filter bank data are also captured over every 10 ms MUOS data frame, and placed in a Frame buffer (39), for later transport to the DSP element (31) via the EMIF bus (13). In the embodiment shown inFIG.5, the first 64 complex samples (277 μs) of every 2,310 samples (10 ms) output on each channel and feed are captured and placed in the Frame buffer (39) over every 10 ms MUOS data frame. It should be noted that the Frame buffer (39) is not synchronized in time to any MUOS data frame, that is, the start of the 10 ms DICE frame buffer bears no relation to the start of a 10 ms MUOS data frame, either at the MUOS SV or observed at the receiver, and no synchronization between the invention and the MUOS signals need be performed prior to operation of the Frame buffer (39).

Adaptive response is provided by and through the DSP element (31) implementing any of a set of beamforming weight adaptation algorithms using beamforming weights derived from any of the ADC buffer (38) and Frame buffer (39), which weights after being computed by the DSP element (31) are sent to a BFN weight buffer (41) available to the beamforming network (34), which applies them to each frequency channel.

The beamforming element (34) combines signals on the same frequency channel of the digital downconverter and analysis filter banks (33a-33d) across antenna inputs, using beamforming weights that substantively improve the signal-to-interference-and-noise ratio (SINR) of a MUOS B2U signal present in the received data over that frequency channel, i.e., that excises co-channel interference (CCI) present on that channel, including multiple-access interference (MAI) from other MUOS transmitters in the antennas' field of view in some embodiments, and otherwise improves the signal-to-noise ratio (SNR) of the MUOS B2U signal. These beamforming weights are provided by the DSP element (31) through the BFN weight buffer (41).

Further specific implementation details of the FPGA (30) are described in the following sections.

Each digital downconverter and filter analysis bank (33a-33d) is responsible for completing the downconversion of the desired MUOS 20 MHz band incoming analog signal into a complex-baseband digital representation of the received signal while removing undesired signal components. This is somewhat complicated for the alias-to-IF sampling approach shown inFIG.2. The ADC sampling rate used must consider the analog filter suppression of out-of band signals and placement of aliased U2B signals in the aliased output band. In addition, for ease of implementation of the adaptation algorithms, the sample rate should allow implementation of an analysis filter bank that provides an integer number of baseband samples in a 10 ms MUOS frame. A sampling rate of 118.272 MHz was selected based upon the following factors:The lower edge of the MUOS band is 5.184 MHz above the third Nyquist sample rate (354.816 MHz) which provides a 2*5.184=10.368 MHz analog transition band. Based on the cascaded analog filters, this provides greater than 40 dB analog suppression of potential out-of-band radio frequency (RF) energy.The U2B band aliases out of band and has sufficient transition bandwidth for filtering.There are exactly 2,310 samples per 10 ms MUOS frame.

The FPGA (30) uses the EMIF bus (32) to transfer a small subset of beamformer input data from the ADC Buffer (38) and Frame Buffer (39) to the DSP element (31) over every 10 ms adaptation frame, e.g., 16,384 complex samples (64 samples/channel×256 channels) out of 591,360 complex samples available every 10 ms (2,310 samples/channel×256 channels), or 2.77% of each frame. The DSP element (31) computes beamforming weights that substantively improve the SINR of a MUOS B2U signal present on the frequency channel, and transfer these weights back to the FPGA (30), where they are used in the beamforming element (34) to provide this improvement to the entire data stream. The FPGA (30) also possesses input and output data buffers and secondary processing elements known to the art (not shown) that can also be used to perform ancillary tasks such as calculation and reporting of ADC output quality metrics, calibration of output frequency offset used to compensate errors in LO (7) feeding the Dual Upconverting Mixer (14), and calculation and reporting of output quality metrics, and report these metrics over the EMIF (32).

In addition to receive thermal noise and the B2U signal, the DICE system is expected to operate in the presence of a number of additional interference sources. See Franke1996 and MacMullen1999 for a description of exemplary downlink interference present in the UHF SatCom bands encompassing the MUOS B2U band. These include:Narrowband co-channel interference (NBCCI) from other signals operating in the B2U band, and occupying a fraction of each MUOS subband. These can include “friendly” interference from other radios operating in this band, including tactical radios communicating over the legacy UHF follow-on (UFO) system; spurs or adjacent-channel interference (ACI) from narrowband terrestrial radios operating in or near the B2U band; and intentional jamming. Exemplary NBCCI in non-MUOS bands can include narrowband cellular signals at geographical boundaries between 2G/2.5G and 3G service areas.Wideband co-channel interference (WBCCI) that may occupy entire B2U subbands, or that may cover the entire MUOS band (as shown inFIG.3). These can include Land-Mobile Radio Systems (LMRS) also operating in or near this band (see pg. 16, Federal Spectrum Use Summary, 30 MHz-3000 GHZ, National Telecommunications And Information Management Office of Spectrum Management, June 2010, for a list of authorized uses of the MUOS B2U band), quasi-Gaussian noise from computer equipment operating in vicinity of the DICE system, and multiple-access interference (MAI) from MUOS satellites in same field of view of the DICE system.

In alternate embodiments, the DSP element (31) can calculate weights associated with multiple desired signals present in the received data, which are then passed back to the FPGA (30) and used to generate multiple combiner output signals. Each of these signals can be interpolated, filtered, and passed to multiple DAC's (not shown). These signals can correspond to signals present on other frequency subbands within the received data passband, as well as signals received in the same band from other spatially separated transmitters, e.g., MAI due to multiple MUOS satellites in the receiver's field of view.

In alternate embodiments, the algorithms can be implemented in the FPGA (30) or in application specific integrated circuits (ASIC's), allowing the DSP to be removed from the design to minimize overall size, weight and power (SWaP) of the system.

FIG.6shows an inverse fast Fourier transform (IFFT) based Decimation-in-Frequency approach used to implement each Analysis filter bank (Analysis FB) (53) shown inFIG.5. Conceptually and in certain embodiments, e.g., multi-bank FGPAs, multi-bank or multi-core GPUs, or multi-core DSPs, the computational processes implemented by each analyzer in a given Analysis filter bank (53) are performed simultaneously (i.e., in parallel). Alternatively, they could be performed by a single analyzer serially at different times, e.g., within a “do loop” taking first the upper leg (l=0), then the lower leg (l=1) and then recombining the stored results.

The overall computational process implemented by each Analysis filter bank (53) is given in general by:

xchn(nchn)=[xchn(kchn,nchn)]kchn=0Kchn⁢1=[∑m=0Qchn⁢Mchn⁢h⁡(m)×(nchn⁢Mchn+m)⁢ej⁢2⁢(nchn⁢Mchn+m)⁢kchn/Lchn⁢Mchn]kchn=0Lchn⁢Mchn⁢1(1)
for discrete-time input signal x(n), where Kchn=LchnMchnis the total number of channels in the Analysis filter bank (53), {h(m)}m=0QchnMchnis a real, causal, finite-impulse-response (FIR) discrete-time prototype analyzer filter with order QchnMchn, such that h(m)=0 for m<0 and m>QchnMchn, and where Lchn, Mchn, and Qchnare the frequency decimation factor, number of critically-sampled analyzer filter bank channels, and polychannel filter order, respectively, employed in the analyzer embodiment.

Introducing path l incrementally frequency-shifted signal x(n;l), given by

x⁡(n;ℓ)=Δx⁡(n)⁢e-j⁢2⁢π⁢nℓ/Lchn⁢Mchn,(2)ℓ=0,…,Lchn-1,
time-channelized representations of x(n;l) and {h(m)}m=0QchnMchn, given by

x⁡(nchn;ℓ)=Δ[x⁡(nchn⁢Mchn+m;ℓ)]m=0Mchn-1,(3)h⁡(qchn)=Δ[h⁡(qchn⁢Mchn+m)]m=0Mchn-1,(4)qchn=0,…,Qchn,
and path l frequency-interleaved critically-sampled analyzer output signal xsub(nchn;l), given by

xsub(nchn;ℓ)=Δ[xchn(ksub⁢Lchn+ℓ,nchn)]ksub=0Mchn-1,(5)ℓ=0,…,Lchn-1,
then {xsub(nchn;l)}l=0Lchn1is formed from {x(nchn;l)}l=0Lchn1and {h(qchn)}q=0Qchnusing succinct vector operations

xsub(nchn;ℓ)=DFTMchn⁢{∑qchn=0Qchnh⁡(qchn)∘x⁡(nchn+qchn;ℓ)},(6)ℓ=0,…,Lchn-1,
where “∘” denotes the element-wise (Hadamard) product and DFTMchn( ) is the row-wise unnormalized Mchn-point discrete Fourier transform (DFT), given generally by

(x)k=m=0M⁢1(x)m⁢ej⁢2⁢k⁢m/M,(7)
for M 1 DFT input and output vectors x=[(x)m]m=0M1and X=[(X)k]k=0M1, respectively. The analyzer filter-bank output signal xchn(nchn) is then formed from {xsub(nchn;l)}l=0Lchn1using a multiplexing operation that de-interleaves the critically-sampled analyzer filter-bank output signals. The element-wise filtering operation shown in Equation (6) is not a conventional convolution operation, as “n+qchn” indexing is used inside the summation, rather than the “n qchn” indexing used in conventional convolution. This operation is transformed to a conventional element-wide convolution, by defining QchnMchn-order time-reversed prototype filter

g⁡(m)=Δ{h⁡(Qchn⁢Mchn-m),m=0,…,Qchn⁢Mchn0,otherwise.(8)

Frequency responses H(ej2f)=nh(m)ej2fmand G(ej2f)=mg(m)ej2fmare given by G(ej2f)=H(ej2f)ej2QchnMchnf, i.e., the two prototype filters have identical frequency response magnitude (|G(ej2f)|=|H(ej2f)|), but effectively reversed frequency response phase, except for a QchnMchn-sample time-advancement required to make both filters causal (∠G(ej2f)=2QchnMchnf∠H(ej2f)). Defining time-channelized filter

g⁡(qchn)=[g⁡(qchn⁢Mchn+m)]m=0Mchn⁢1,(9)qchn=0,▯,Qchn,
then Equation (6) can be expressed as

xsub(nchn;ℓ)=IDFTMchn⁢{∑qchn=0Qchng⁡(qchn)∘x⁡((nchn+Qchn)-qchn;ℓ)},(10)
where IDFTMchn( ) is the row-wise Mchn-point unnormalized inverse-DFT (IDFT), given by

(x)m=k=0M⁢1(x)k⁢e+j⁢2⁢k⁢m/M(11)
for general M 1 IDFT input and output vectors X=[(X)k]k=0M1and x=[(x)m]m=0M1, respectively, implemented using computationally efficient radix-2 IFFT methods if M is a power of two, and where the element-wise convolution performed ahead of the IDFT operation in Equation (10) is now a conventional operation for a polyphase filter (76). Note that the analyzer output signal shown in Equation (10) is “advanced” in time by Qchnoutput samples relative to the “conventional” analyzer output signal shown in Equation (6); if desired, the analyzer output time indices can be delayed by Qchn(nchn¬nchnQchn) to remove this effect.

Using the general decimation-in-frequency method described above, the operations used to compute path l output signal xsub(nchn;l) from analyzer input signal x(n) for this Analysis filter bank embodiment are shown in the upper part ofFIG.6. These operations are described as follows: the input signal x(n) (70) is first passed to a multiplier (89) where it is multiplied by the conjugate of channel twiddles

{exp⁡(j⁢2⁢ℓn⁢mod⁢256256)}n=0255
(said conjugation denoted by the “ ” operation applied to the stored Channel Twiddles (72) to form path l incrementally frequency-shifted signal x(n;l), where the channel twiddles are generated from a prestored Look-Up Table (LUT) to reduce processing complexity, and where ( )mod 256 is the modulo-256 operation. The path l incrementally frequency-shifted signal x(n;l) is then passed through a 128-channel critically-sampled analyzer (73), sequentially comprising a 1:128 serial-to-parallel (S:P) converter (77), a Polyphase filter (76) which integrates the prestored polyphase filter coefficients (75), and a 128-point (radix-2) IFFT (81), implemented to produce path (output critically-sampled analyzer output signal xsub(nchn;l). All of the output signals {xsub(nchn:l)}l=0Lchn1from every critically-sampled analyzer are then fed to the multiplexer (78) (not shown on the upper part ofFIG.6) to produce the full channelizer output signal xchn(nchn).

For the full Analysis filter-bank (53) shown in the lower part ofFIG.6, where Kchn=256 and Lchn=2, that Analysis filter-bank (53) is implemented using 2 parallel critically-sampled analyzers (73,74) with Mchn=128 channels per critically-sampled analyzer, and QchnMchn=1,536, such that each critically-sampled analyzer (73,74) employs a polyphase filter (76) of order Qchn=12. This path also explicitly exploits the property that

exp⁡(j⁢2⁢ℓn/256⁢ℓn⁢mod⁢256256)
1 on the l=0 path, which allows omission of the channel twiddle multiplication and x(n;0) x(n). Consequently, for the specific embodiment shown inFIG.6, where Lchn=2, the channel twiddles

{exp⁡(j⁢2⁢n⁢mod⁢256256)}n=0255
are only applied on the l=1 path. The output signals {xsub(nchn;l)}l=0Lchn1from the parallel critically-sampled analyzers (73,74) are then interleaved together to form the full Analysis filter-bank signal xchn(nchn), using the multiplexer (78) shown inFIG.6to produce the output (71).

In the embodiment shown inFIG.6, the IDFT operation is performed using a “radix-2” fast inverse Fourier transform (IFFT) algorithm that is well-known in the art. The prior art of using a ‘butterfly’ or interleaved implementation can reduce the computational density and complexity as well. Also, computational efficiency is improved when the implementation specifically recognizes, and builds into the processing, tests to reduce butterfly multiplications; for example, later stages of an IFFT do not require a complex multiply, since multiplication by ±j can be performed by simply swapping the I and Q samples; and multiplies by ‘±1’ need not be done.

FIG.7shows the FFT-based Decimation-in-Frequency implementation of the substantively perfect Synthesis filter-bank (35) applied to the BFN output channels inFIG.4. The structure shown is the dual of the Analysis filter-bank structure shown inFIG.6. The polyphase filter coefficient (75) stores the same data in both Figures. However, that data is applied in the polyphase filter (76) in reverse order (i.e. it is time-channelized) in each Figure. So inFIG.6a time-channelized version of g(m)=h(1,536 m) is used in the polyphase filter (76), while inFIG.7a time-channelized version of h(m) is used in the polyphase filter (76). The polyphase filtering operation is the same in both Figures, but the data given to it is different. Again these computational processes implemented by each synthesizer could be in parallel or serial as described above.

The general case, as shown in the upper part ofFIG.7is: the input (80) is processed by an IFFT (81) then a polyphase filter (76), which uses the pre-stored polyphase filter coefficients (75), then by a parallel-to-serial converter (90), then a multiplier (89) applying the prestored Channel twiddles (72), to produce the output (91)

The computational process provided by each synthesizer operation is given generally by

x⁡(n)=kchn=0Kchn⁢1ej⁢2⁢kchn⁢n/Kchnnchn⁢xchn(kchn,nchn)⁢h⁡(n⁢nchn⁢Mchn)=ℓ=0Lchn⁢1ej⁢2⁢n⁢ℓ/Lchn⁢Mchn⁢x⁡(n;ℓ),(12)
for Kchn1 synthesizer input signal xchn(nchn)=[xchn(kchn,nchn)]kchn=0Kchn1(80), where Kchn=LchnMchnand interpolation function h(m) is the same real, causal, FIR QchnMchn-order discrete-time prototype filter used in the Analysis filter-bank (53), and where x(n;l) is an incrementally frequency-shifted signal, given by

x⁡(n;ℓ)=ksub=0Mchn⁢1ej⁢2⁢kn/Mchnnchn⁢xsub(ksub,nchn)⁢h⁡(n⁢nchn⁢Mchn).(13)

Using notation for time-channelized representations of x(n;l) and {h(m)}m=0QchnMchngiven in Equation (3) and Equation (4), respectively, and defining frequency-interleaved critically-sampled synthesizer input signals {xsub(nchn;l)}l=0Lchn1={[xchn(ksubLchn+l,nchn)]ksub=0Mchn1}l=0Lchn1, i.e., using notation given by Equation (5), then the time-channelized representation of x(n;l) can be expressed succinctly as

x⁡(n;ℓ)=∑Qchnqchn=0h⁡(qchn)∘IDFTMchn⁢{xsub(nchn-qchn;ℓ)},(14)
where IDFTMchn( ) is the row-wise Mchn-point unnormalized IDFT used in the Analysis filter-bank (53), implemented using IFFT operations if Mchnis a power of two.

The Synthesis filter-bank (35) shown inFIG.7is then implemented using the following procedure:First, separate the Kchn1 synthesizer input signal (80) into LchnMchn1 frequency-interleaved signals using a demultiplexer (DMX) (83).Then, on each critically-sampled synthesizer path:implement Equation (14) by taking the row-wise unnormalized IDFT of xsub(nchn;l) (80) using a radix-2 IFFT operation (81), and then performing an element-wise convolution of that signal and the polyphase filter (76) with time-channelized prestored polyphase filter coefficients {h(qchn)}qchn=0Qchn(75);then multiply the P: S output signal (89) by the Channel Twiddles for that path (without conjugation).Then, sum together the signals on each path to form the synthesizer output signal x(n)(91).

The reconstruction response of the Synthesis filter-bank (35) can be determined by computing the Fourier transform of the finite-energy signal xout(n) generated by passing a finite-energy signal xin(n) through a hypothetical test setup comprising concatenated analyzer and synthesizer filter-banks. Assuming that xin(n) has Fourier transform Xin(ej2f)=nxin(n)ej2fn, then the Fourier transform of xout(n) is given by

Xout(ej⁢2⁢f)=∑Mchn⁢1ksub=0Dksub(ej⁢2⁢f)⁢Xin(ej⁢2⁢(f+ksubMchn),(15)
where reconstruction frequency responses {Dksub(ej2f)}ksub=0Mchn1are given by

Dksub(ej⁢2⁢f)=1Kchn⁢∑Kchn⁢1kchn=0H⁢(ej⁢2⁢(f⁢kchnKchn))⁢H⁡(ej⁢2⁢(f⁢kchnKchn⁢ksubMchn)).(16)

Ideally, {Dksub(ej2f)}ksub=0Mchn1satisfies perfect reconstruction response

Dksub(ej⁢2⁢f)≡{ej⁢2⁢f,ksub=00,ksub=1,▯,Mchn⁢1(17)
for a given prototype filter. If the analyzer is implemented using Equation (6), then D0(ej2f) is real and nonnegative, and hence the concatenated analyzer-synthesizer filter-bank pair has an apparent group delay of 0. If the critically-sampled analyzers are implemented using Equation (10), and the analyzer output time index is delayed by Qchnsamples to produce a causal output, then the end-to-end delay through the analyzer-synthesizer pair is equal to QchnMchn, i.e., the order of h(m), plus the actual processing time needed to implement operations of the analysis and synthesis filter banks.

In the analysis and synthesis filter bank embodiments shown inFIG.6andFIG.7, the Analysis filter-bank output channels and Synthesis filter-bank input channels are both separated by 29,568/256=115.5 kHz, and are implemented using a 1,536-tap nonlinear-phase prototype filter with a half-power bandwidth (HPBW) of 57.75 kHz, and an 80 dB rejection stopband of 113.5 kHz, resulting in a 97% overlap factor between channels. The reconstruction response for this prototype filter is close to 0 dB over the entire 29.568 MHz bandwidth of the analyzer input data, while the nonzero frequency offsets quickly degrades to <−80 dB. In practice, this should mean that strong interferers should not induce additional artifacts that must be removed by spatial beamforming operations.

In alternate embodiments, the output rate can be further reduced to 115.5 kHz (output sample rate equal to the channel separation), as shown in T. Karp, N. Fliege, “Modified DFT Filter Banks with Perfect Reconstruction,”IEEE Trans. Circuits and Systems—II: Analog and Digital Signal Proc., vol. 46, no. 11, November 1999, pp. 1404-1414 (Karp1999). These methods trade higher complexity during analysis and subsequent synthesis operations against lower complexity in intervening beamforming operations.

In this detailing of the embodiment, the active bandwidth of the MUOS signal (frequency range over which the MUOS signal has substantive energy) in each MUOS subband is covered by Kactive=40 frequency channels, referred to here as the active channel set for each subband, denoted herein as Ksubband(lsubband) for subband lsubband. This can be treated as a constraint which, if altered, must be reflected by compensating changes. This subband-channel set definition has the following specific effects:the active bandwidth of the B2U signal in MUOS Subband 0 (360-365 MHZ) is covered by analysis filter bank frequency channels Ksubband(0)={(85+kactive)mod 256}kactive=0Kactive1,the active bandwidth of the B2U signal in MUOS Subband 1 (365-370 MHZ) is covered by analysis filter bank frequency channels Ksubband(1)={(38+kactive) mod 256}kactive=0Kactive1,the active bandwidth of the B2U signal in MUOS Subband 2 (370-375 MHz) is covered by analysis filter bank frequency channels Ksubband(2)={(6+kactive) mod 256}kactive=0Kactive1, andthe active bandwidth of the B2U signal in MUOS Subband 3 (375-380 MHZ) is covered by analysis filter bank frequency channels Ksubband(3)={(49+kactive) mod 256}kactive=0Kactive1.

The intervening frequency channels do not contain substantive B2U signal energy, and can be set to zero as a means for additionally filtering the received signal data.

FIG.8shows an exemplary list of channelizer sizes, pertinent parameters, complexity in giga-cycles (billions of cycles) per second (Gcps), and active channel ranges (taken mod Kchannelto convert to 0:(Kchannel1) channel indices for an analyzer filter bank with Kchannelfrequency channels) for each subband is provided in for the 29.568 Msps analyzer input sampling rate used in the embodiment shown inFIG.4. Alternate analyzer/synthesizer filter bank parameters can be used to allow processing of additional and/or more narrowband interferers at increased system complexity, or fewer and/or more wideband interferers at decreased system complexity.FIG.8also provides the number of samples available within each channel over a 10 ms adaptation frame. AsFIG.8shows, increasing the number of analyzer channels from 32 to 512 only incurs a 23.5% increase in the complexity of the analyzer (or synthesizer).

The beamforming operation is also implemented using FPGA (30) as noted above. The beamforming element (34) multiplies the complex output of each analyzer frequency channel by a complex beamforming weight (provided in the BFN weight buffer (41)), and combines the multiplied channels over the antenna dimension. This set of linear combining weights, also known as diversity combining weights are developed (i.e., calculated) by the DSP element (31) performing the Beamforming Weight Adaptation Task which computes linear diversity combining weights over 10 ms adaptation frames to substantively improve the signal-to-interference-and-noise ratio (SINR) of any MUOS signal, by substantively excising interference received in each frequency channel along with that signal, including multiple access interference (MAI) received from other MUOS satellites in the DICE system's field of view (FoV), and by otherwise substantively improving the signal-to-noise ratio (SNR) of the MUOS signal within that frequency channel. In the presence of frequency and time dispersion (differences in spatial signatures of emissions over frequency channels or adaptation frames), including dispersion due to multipath or nonidealities in the DICE receiver, the weights can also substantively suppress or exploit effects of that dispersion, to further improve quality of the signal generated by the appliqué.

Each complex multiply requires 4 real multiplies. At four clock cycles per complex multiply and frequency channels, all beamforming weights can be applied by a single DSP slice for a given antenna path,

(4⁢cycles/antenna)⁢(0.231Msps/channel)⁢(256⁢channels)=236.544Mcps/antenna.(18)

The complex samples from each antenna are cascaded and summed to generate the beamformer output.

It should be noted that the total cycle count needed to perform the beamforming operation over all frequency channels is unchanged for the alternate analyzer sizes given inFIG.8, because the product of (the number of channels)×(the output rate per channel) remains constant for each analyzer size. However, this cycle count can be dropped by a factor of 2 and further computational efficiency attained if additional operations such as those shown in Karp1999 are performed to reduce the analyzer output rate by 50%, and by an additional 37.5% if the beamforming is only performed over the active channels in each subband. The cycle count is increased by a factor of 2 if the beamforming is used to provide two output ports, e.g., corresponding to each MUOS satellite in the DICE system's field of view.

The output of the beamforming element (20) are 256 frequency channels, comprising 160 modulated frequency channels and 96 zero-filled channels if beamforming is only performed over the active channels in each subband. These frequency channels are converted to a single complex-baseband signal with a 29.568 Msps sampling rate, using a reciprocal Synthesis filter-bank (53) employing efficient FFT-based implementation methods well known to those skilled in the art. The symmetry between the analyzer and synthesizer allows the synthesizer implementation to be identical to the analyzer, only with the blocks rearranged, and with the FFT replaced by an inverse-FFT (IFFT). The IFFT is the same design as the FFT with complex-conjugate twiddle factors. The polyphase filter in the critically-sampled synthesizer is identical to that in the critically-sampled analyzer, with lag-reversed filter coefficients. Therefore the same FPGA HDL design is used.

The 29.568 Msps synthesizer output signal from the Synthesis filter-bank (35) is then multiplied by an LO offset correction in a multiplier (36), and 1:2 interpolated in an interpolation filter (37), resulting in a complex-baseband signal with a 59.136 Msps sampling rate. This signal is then output to the Digital-to-Analog Converter (11) shown inFIG.2.

The LO offset correction (not needed for the direct-frequency downconversion based system shown inFIG.1) removes any frequency error introduced by subsequent analog frequency upconversion operations, such as the Dual Upconverting Mixer operation shown inFIG.2. In the DICE Digital Signal Processing Subsystem embodiment shown inFIG.4, the LO offset frequency is quantized to values

{kLO/KLO}kLO=KLO2KLO2⁢1,
allowing the offset values to be stored in a KLO-point look-up table.

The offset frequency index kLOcan be set via a variety of means, including automatically during calibration intervals (e.g., by transmitting a calibrated tone from the system transmitter and measuring end-to-end frequency offset of that tone through the full system), or by monitoring lock metrics from the MUOS radio. Combined with appropriate calibration operations to measure this frequency offset, this can allow the DICE system to provide an output signal without any offset induced by the system. In this case, the DICE applique will not impair the frequency budget of the radio attached to it, nor will it affect internal radio functions that may use the MUOS satellite Doppler shift, e.g., as a geo-observable for radio location or synchronization purposes. Alternate embodiments can incorporate this frequency shift into the LO (7) used to perform frequency upconversion to 370 MHz, or can use higher-quality LO's that obviate the LO offset correction term.

In this embodiment, the interpolation process is effected by first zero-filling the 29.568 Msps interpolator input data with alternating zeros to generate a 59.136 Msps signal, then applying a real 16-tap linear-phase FIR filter with a lowpass-filter response to each IQ rail to suppress the image at ±29.568 MHz. Since every other data sample is zero, the FIR filter is implemented with 8 real multiplies per I and Q rail at a sample rate of 59.136 Msps. This upconversion simplifies the analog filtering and is extremely simple to implement.

A 1:2 interpolation factor is used in the embodiment shown inFIG.2, in order to reduce frequency rolloff induced by the square DAC time pulses to less than 0.4 dB. In alternate embodiments, the interpolation filter or the frequency channels input to the synthesizer can be preemphasized to remove the ˜2 dB rolloff induced by a DAC operating at 29.568 Msps interpolation rate, allowing removal of the 1:2 interpolator. However, this will also require the use of sharper antialiasing filters to remove the DAC output images repeating at multiples of 28.568 MHz

The required FPGA resource utilization needed to implement the end-to-end data processing depends on two main resources, respectively DSP slices and internal block RAM. The basic processing as described above only utilizes 135 DSP slices. A Xilinx Kintex® 410T used in one embodiment has, for example, 1590 BRAMs and 1540 DSP slices, therefore less than 8% of that specific FPGA is used in the system.

Based on these numbers, a very low power, low cost FPGA can be used. The above-referenced specific FPGA from Xilinx is but one member of a family (Artix-7) of low power, low cost FPGAs and thus one choice. An additional benefit from using an FPGA from the Artix-7 family is that they are a series of pin compatible devices, which would allow upgrading the FPGA if and as needed in the future. Further processing refinements, e.g., to eliminate the 2× oversampling of analyzer channels or to restrict processing to only the active channels in each subband, should allow use of the other FPGAs, widening the definition of which have ‘enough’ DSP slices and ‘more than enough’ BRAM's to process a set of MUOS subbands.

In the embodiments shown here, the FPGA (30) has an additional master counter (not shown) that separates the received data into 10 ms adaptation frame, e.g., covering exactly 2,310 output samples at the output of each frequency channel in the Analyzer Filter Bank (33a-33d) for the embodiment shown inFIG.2. As shown inFIG.5, at the beginning of each 10 ms adaptation frame, the FPGA (30) collects 64 consecutive complex samples from each analyzer frequency channel, and writes those samples into a Frame Buffer (39) whose logical structure is shown inFIG.9.

The contents of the Frame Buffer (39) are then transported to the DSP element (31) over the EMIF Bus (32), where they are deposited into memory in the DSP element in accordance with the logical memory structure shown inFIG.10. Specifically, data is deposited into a “Ping Pong” buffer over even and odd frame intervals, such that the “Ping” subbuffer is overwritten with new data every even interval, and the “Pong” subbuffer is overwritten with new data over every odd interval.

In one DICE embodiment, the data in the Frame Buffer (39) is reduced in precision from the 25 bit precision used in the FPGA (30) to 16 bit precision prior to transfer to the DSP element (31), in order to minimize storage requirements of that chip. This operation has minimal effect in environments dominated by wideband CCI (WBCCI) or MAI; however, it can greatly reduce dynamic range of data in each frequency channel, particularly in environments containing narrowband CCI (NBCCI) with wide variation in dynamic range. Alternate approaches can transport the data to DSP element (31) at full 25 bit precision (or as 32-bit integers), thereby preserving the full dynamic range of the data. The entire buffer requires 512 KB of storage, comprising 256 KB per subbuffer, if data is transferred from the FPGA (30) at 16 bit precision, and requires 1,024 KB (1 MB) of storage, comprising 512 KB/subbuffer, if data is transferred into 32-bit memory, e.g., at the full 25-bit precision of the FPGA (30).

There are various ‘mapping’ alternatives which may be used for this buffering operation, with performance and accuracy varying by the quality of the match between the mapping choice, the signals environment, and the received/transmitted signal complexity or length. Example mappings include:“Dense mapping” strategies, in which consecutive data samples are written to the DSP within each adaptation frame, as performed in the primary embodiment. This mapping minimizes effects of sample rate offset and jitter within each frame, and allows additional filtering of data within and between channels in the DSP processing.“Sparse mapping” strategies, in which subsampled data is written to the DSP within each adaptation frame. This mapping provides additional sensitivity to time-varying interference effects within each frame, e.g., interference bursts with <10 ms duration that may be missed by a dense mapping strategy, but is also more sensitive to sample rate offset and jitter within each frame.“Randomly” or “pseudorandomly” mapping strategies, in which data is written to the DSP in accordance with a random or pseudorandom sample selection process, for example, to MAI from other emitters that may be adjusting their power levels synchronously with the MUOS transmitter, or to avoid spoofing, interception, or jamming by electronic attack (‘EA’) measures that might be employed by adversaries attempting to exploit or disrupt the process.

In all cases, variation, however, should be synchronous across at least pairs of adaptation frames (time) and across and for all antenna feeds at each time (sourcing).

Alternate embodiments can also be chosen in which the sampling rate does not provide an integer number of samples per adaptation frame at the output of the Analyzer Filter Bank. This strategy can allow sampling rates that are simpler and/or consistent with other pertinent system parameters, for example, MUOS subband bandwidths or known interference bandwidths and frequency distributions, at cost of additional complexity in the implementation of a beamforming adaptation algorithm to resample the DSP input data to the 10 ms adaptation frame.

One DICE embodiment used for its DSP element a Texas Instruments (TI) TMS320C6455 as the DSP element (31) in the prototype DICE system. This particular embodiment is a fixed-point processor with a 1,200 MHz clock speed, capable of performing a real multiply and add in a single clock cycle, and with 32 KB (kilobytes=1,024 bytes) of “L1 cache” memory to hold data used in direct calculations and 2,048 KB of “L2 cache” memory to hold data input from the FPGA (30), beamforming weights output to the FPGA (30), weight calibration data, and intermediate data and statistics held during and between adaptation frames. The DSP element (31) can read and write registers and data buffers in the FPGA (30) via the EMIF bus (32); in the embodiments shown here, it reads complex Analyzer Filter Bank in from the FPGA (30) using the Frame Buffer (39), and writes beamforming weights resulting from the implementation of a beamforming weight adaptation algorithm to the FPGA (30) using the BFN weight buffer (41).

In this embodiment, the DSP employs the TI-RTOS real-time operation system to implement the beamforming weight adaptation algorithm, a preemptive operating system (OS) that allows multiple tasks to be run “concurrently” with different priority levels. The main task in this embodiment is the Beamforming Weight Adaptation Task shown inFIG.11.

Once a Beamforming Weight Adaptation Task (99) is created (101), it performs its initial setup (102) and drops into a “while” state where it pends on the Data Ready semaphore (103). When the FPGA (30) has data to send to the DSP element (31) it lowers a general purpose input/output (GPIO) line that triggers an external dynamic memory access (DMA) transfer operation (104). This operation transfers the full antenna data from the Frame Buffer (39) to the appropriate L2 memory subbuffer as shown inFIG.10. Once data has been transferred from all four feeds, the FPGA (30) then triggers an interrupt, which posts the Data Ready semaphore (105) to the DSP element (31). The latter is now able to run the implementation of the beamforming weight adaptation algorithm task. The implementation of any weight adaptation algorithm available then processes the data (106), adapting the beamforming weights, and transfers data to and from L2 to L1 as needed using an internal dynamic memory access (IDMA) driver.

When the implementation of the Beamforming Weight Adaptation Algorithm has new weights ready (107), it triggers an EDMA transfer to transfer the weights (108) to the BFN weight buffer (41) of the FPGA (30). On completion of this transfer the DSP element (31) will signal the FPGA (30) that new beamforming weights have been transferred and are ready for the latter's use (109).

This transfer can be trigged in several manners. One approach is to call a trigger function provided by an external DMA (EDMA) driver (110). Another approach is to set up the transfer to be triggered on a GPIO interrupt, and then lower this line via software in the method. The latter approach can serve dual purpose of signaling the FPGA (30) of the beamforming transfer, and triggering the transfer.

After triggering the transfer, the implementation of the Beamforming Weight Adaptation Algorithm can continue processing if necessary, or pend on the Data Ready semaphore to wait (105) until new data is ready from the FPGA (30); or that specific task can be destroyed (111). In alternate embodiments, the data transfer from FPGA (30) to DSP element (31) and weight transfer from DSP element (31) to FPGA (30) can be linked, such that the former process does not ensue until after the latter process has occurred; or such that data transfer can occur “on demand” from the DSP element (31), e.g., to respond quickly to new events, or allow random or pseudorandom data transfers to defeat electronic attack (EA) measures by adversaries attempting to corrupt the algorithm. On demand approaches could also have merit if algorithms that require more than 10 ms are implemented in the DSP element (31), e.g., if a low-cost DSP is used by the system, or more advanced methods are implemented in the DSP element (31).

At least one embodiment uses a lower-cost floating-point or hybrid fixed/floating point DSP element (31), with processing speed and capabilities matched to the algorithm implementation used in the system, and with random-access memory (external or internal to the DSP element (31)) to hold data transferred from the FPGA (30) and intermediate run parameters held over between adaptation frames. In alternate embodiments, some or all of this processing can be brought into the FPGA (30), in particular, to perform regular operations easily performed in fixed-point such as per-channel statistics accumulations.

The system embodiment shown inFIG.1allows implementation of a DICE Digital Signal Processing Subsystem, in which Dual ADC output data is input to the DSP Subsystem at a 40 Msps complex data rate (i.e., over 2×4=8 data rails, each operating at a 40 Msps data rate), rather than a 118.272 Msps real data rate, and with several optional simplifying differences. Example simplifying differences include:Simplification of the digital downconversion and Analysis filter-bank shown inFIG.4and described inFIG.5, by replacing that stage with a single 2:1 decimator ahead of the Analysis Filter Bank (53).Operation of the Analysis filter-bank (53) shown inFIG.5and described inFIG.6, using exactly the same implementation process, except at a 20 Msps input date rate rather than a 29.568 Msps input data rate, to provide 128 output frequency channels, each operating at a 312.5 ksps output data rate (3,125 samples per 10 ms frame), with 156.25 kHz separation between frequency channels, such that exactly 32 channels covers each subband in the MUOS B2U band without gaps between frequency channels, and using a prototype filter of order768resulting in a 36% decrease in computation complexity over the Analysis filter-bank shown inFIG.6.Operation of the BFN over 128 channels at a 312.5 ksps/channel data rate, without any zero-filling of channels outside the MUOS B2U subband.Operation of the Synthesis filter-bank (35) shown inFIG.4and described inFIG.7at a 20 Msps output data rate in parallel with the Analysis filter-bank (53).Elimination of the LO Offset operation (86) shown inFIG.4, and of the LO Buffer (42) and all algorithms needed to calibrate that operation.Operation of the 1:2 interpolator (37) shown inFIG.4at a 20 Msps input data rate.

In an alternate embodiment, the 2:1 decimator and 1:2 interpolator can be dispensed with, and the Analysis filter-bank (53) and Synthesis filter-bank (35) can be implemented with a 40 Msps input and output rate, respectively, and with 256 frequency channels, each with a 312.5 ksps data rate, and with 156.25 kHz separation between frequency channels. In this case, 128 of the channels would cover the MUOS B2U band (32 channels covering each subband), and the 128 channels outside the MUOS B2U band would be zero-filled during the BFN operation; subsamples from channels outside the B2U band would not be captured and transferred to the Frame buffer (39).

Two general classes of implementation of Beamformer Weight Adaptation Algorithms are described in detail herein:Low-complexity subband-channelized implementation of beamforming weight adaptation algorithms, which compute common weights over each frequency channel covering the active bandwidth of a MUOS subband (“active channels” in a subband), with adjustments to compensate for calibrated frequency dispersion induced in the system front-end. In the primary embodiment, the implementation of the subband-channelized beamforming weight adaptation algorithm uses a multiport self-coherence restoral (SCORE) to adapt the subband weights and avoid specific emitters that can be captured by the method, e.g., continuous wave (CW) tones.More powerful/complex fully-channelized implementation of beamforming weight adaptation algorithms, which compute independent beamforming weights on each frequency channel, with adjustments to remove gain offset induced by ambiguities in the implementation of the adaptation algorithm. These implementations of such algorithms can excise independent narrowband interference present in a frequency channel, without expending degrees of freedom to excise interferers that do not occupy that channel. In the primary embodiment, the implementation of the fully-channelized weight adaptation algorithm uses fully-channelized frame-synchronous feature extraction (FC-FSFE) to blindly adapt the 4-element complex spatial combining weights independently in each frequency channel

Both implementations of the selected algorithm exploit the first-order almost-periodic aggregated common pilot channel (CPICH) component of the MUOS B2U signal. The aggregated CPICH (A-CPICH) comprises sixteen (16) CPICH's transmitted from the MUOS satellite vehicle (SV) with offset scrambling code, carrier frequency (induced by Doppler shift over the ground-station to satellite link), and carrier phase/gain (induced by beam separation). The resultant A-CPICH signal-in-space observed at the radio can be modeled in general by

pA-CPICH(t)=2⁢Re⁢{∑16b=1gTR(b)⁢pCPICH(tTR⁢(b);b)⁢ej⁢2⁢fTR(b)⁢t},(19)
where pCPICH(t;b)=pCPICH(t+Tframe;b) is the first-order periodic beam b CPICH transmitted in beam b, (distorted by local multipath in the field of view of the radio receiver), and where gTR(b),TR(b), and fTR(b) are the observed bulk gain, time-of-flight delay, and receive frequency of the beam b CPICH, and where Tframe=10 ms is the known frame duration of the MUOS signal. The A-CPICH can therefore be modeled as a first-order almost-periodic component of the MUOS B2U signal. This property also induces a 10 ms cross-frame coherence (nonzero correlation coefficient between signal components separated by 10 ms in time) in the signal received at the DICE system. Moreover, all of these properties are held by that component of the A-CPICH present in each channel of the analysis filter bank, and in the Frame Buffer data passed to the DSP element, regardless of the actual content of the A-CPICH, or the time and frequency offset between the Frame Buffer data and the actual MUOS frame.

The subband-channelized and fully-channelized implementations are described below.

Subband-Channelized Beamforming Weight Adaptation Embodiment

FIG.12shows the flow diagram of the implementation of a subband-channelized beamforming weight adaptation algorithm in one embodiment. The beamforming weight calculation process begins whenever a “Data Ready” message from the DSP element (31) is received (121). Once this message is received, and under normal operating conditions, the implementation first computes subband cross-correlation matrix (CCM) and autocorrelation matrix (ACM) statistics (122), and1045retrieves the past ACM statistics for the past frame (123) from the L2 cache of the DSP element (31). The implementation then steps through the 40 frequency channels covering the active bandwidth of the MUOS signal in that subband (“active channels” in that subband); retrieves 128 four-feed data samples written to L2 cache data for that channel over the current and prior data frame (64 four-feed samples per data frame within each frequency channel, out of 2,310 samples available within each 10 ms MUOS frame and frequency channel) (124); and computes unweighted ACM statistics for the current frame and CCM statistics for the current and prior frame (125), as described in further detail below (‘Statistics Computation’). The implementation then adjusts those statistics to compensate for known dispersion in that channel (126), (126), using for that channel the precomputed data, i.e. the calibration statistic adjustment (127), stored in the L2 cache. (These just-adjusted current statistics are also used in the computation of channel kurtosis described further below.)

The channel CCM and current ACM statistics are then accumulated over the 40 active channels in the subband (128), to create the subband CCM and current ACM statistics; the Cholesky factor of the current ACM statistics is computed; and those statistics are checked for “pathological condition,” e.g., zero-valued Cholesky factor inverse-diagonals. If a pathological condition is not detected, the current ACM statistics are written to L2 cache (129) for the next use; otherwise, processing is terminated without weight adaptation or statistics storage (130).

If prior-frame ACM statistics do not exist, e.g., if the implementation is newly initialized, a pathological data frame is detected during the previous frame, or more than one frame transpires since the “Data Ready” message is received, the implementation initializes the prior-frame ACM statistics as well, and computes ACM statistics and Cholesky factors for the prior and current frame. This is expected to be an infrequent occurrence over operation of the implementation and is not shown.

The CCM statistics and current/prior ACM Cholesky factors are then used to compute the 4×4 spatially-whitened cross-correlation matrix (SW-CCM) of the received data (131). The 4×4 right-singular vectors and 4×1 modes of the singular-value decomposition (SVD) of the SW-CCM are then estimated using an iterative QR method, described below, which provides both spatially-whitened beamforming combiner weights (updated multiport SCORE weights) (132) that can be used to extract the MUOS signal from the received environment (after spatial unwhitening operations), and an estimate of the cross-frame coherence strength (magnitude of the cross-frame correlation coefficient between the current and prior data frames) of the signal extracted by those weights, which are stored (133). The cross-frame coherence strength is also used as a sorting statistic to detect the MUOS signal-of-interest (SOI) and differentiate it from other SOI's and signals not of interest (SNOI's) in the environment. The next two steps, where the embodiment will update the multiport SCORE weights (132) and compute channel kurtosis for each SCORE port (135), are described in detail below

(‘Multiport Self-Coherence Restoral Weight Adaptation Procedure’ and ‘Channel Kurtosis Calculation Procedure’).

In alternate embodiments, the QR method can be accelerated using Hessenberg decomposition and shift-and-deflation methods well known to those skilled in the art. The specific QR method used here can also be refined to provide the eigendecomposition of the SW-CCM, allowing tracking and separation of signals on the basis of cross-frame coherence phase as well as strength. This last capability can substantively improve performance in environments containing multiple-access interference (MAI) received at equal or nearly-equal power levels.

The SCORE combining weights are then passed to an implementation of a SOI tracking algorithm (136), shown inFIG.13, which matches those weights to prior SOI beamforming weights (SOI tracking weights) (137) in a manner that minimizes effects of unknown dispersion in the receiver channel. Lastly, those weights are adjusted to compensate for known channel dispersion in the receiver front-end (138), using a prestored, calibrated weight adjustment for each frequency channel (139), and (if necessary) converted to complex 16-bit format usable by the DICE FPGA. The beamforming weights are then downloaded to the FPGA (30) which is triggered by a ‘Weights Ready’ message (140) to process the channelizer output signal over every sample and channel in the active subband (141).

Further details of the SOI tracking algorithm implemented in this embodiment are described below.

Statistics Computation Procedure

The statistics computation is compactly and generally described by expressing the prior-frame and current frame data signals as NTBPMfeeddata matrices Xprior(kchn) and Xcurrent(kchn), respectively,

Xprior(kchn)=(xT⁢(kchn,Nframe⁢(nframe-1))⋮xT(kchn,Nframe(nframe-1)+NTBP-1))(20)Xcurrent(kchn)=(xT(kchn,Nframe⁢nframe)⋮xT(kchn,Nframe⁢nframe+NTBP-1))(21)
where Mfeedis the number of antenna feeds (Mfeed=4 in an embodiment), kchnis the index of a frequency channel covering a portion of the subband modulated by substantive MUOS signal energy (active channel of the subband), nframeis the index of a 10 ms DICE adaptation frame (unsynchronized with the true MUOS frame), Nframeis the number of channelizer output samples per 10 ms DICE data frame (2,310 samples for the 231 ksps channelizer output sampling rate used in the DICE prototype system), and NTBPis the number of samples or DICE time-bandwidth product (TBP) used for DICE statistics accumulation over each frame (NTBP=64 in the embodiments shown here), and where x(kchn,nchn)=[xchn(kchn,nchn;mfeed)]mfeed=1Mfeedis the Mfeed1 output signal over frequency channel kchnand channelizer output time sample nchn, and ( )Tdenotes the matrix transpose operation.

In the simplest DSP instantiation, Nframeshould be an integer; however, more complex instantiations, e.g., using sample interpolation methods, can relax this condition if doing so results in significant cost/complexity reduction in the overall system. The important requirement is that Xprior(kchn) and Xcurrent(kchn) be separated in time by 10 ms (or an integer multiple of 10 ms), e.g., a single period of the MUOS CPICH (or an integer multiple of that period).

Using this notation, the per-channel CCM and current ACM statistics are given by

Rxprior⁢xcurrent(kchn)=XpriorH(kchn)⁢Xcurrent(kchn)(22)Rxcurrent⁢xcurrent(kchn)=XcurrentH(kchn)⁢Xcurrent(kchn)(23)
for frequency channel kchn, where ( )Hdenotes the conjugate (Hermitian) transpose. If dispersion compensation is performed by the system (discussed in more detail below), the per-channel CCM and current-ACM statistics are then adjusted to remove dispersion by setting

Rxprior⁢xcurrent(kchn)←Rxprior⁢xcurrent(kchn)∘(wcal*(kchn)⁢wcalT(kchn)),(24)Rxcurrent⁢xcurrent(kchn)←Rxcurrent⁢xcurrent(kchn)∘(wcal*(kchn)⁢wcalT(kchn)),(25)
where “∘” denotes the element-wise (Hadamard) product and ( ) denotes the complex conjugation operation, and where {wcal(kchn)} is a set of calibration weight adjustments (the Current Mulitport Score weights (133), computed during prior calibration operations and stored in L2 cache). In the embodiments shown here, calibration statistic adjustments (‘Cal statistic adjustments’) (127)

Rcal(kchn)=△wcal*(kchn)⁢wcalT(kchn)(26)
are also precomputed and stored in L2 cache, in order to minimize computation required to perform the processes implementing computation of Equations (24)-(25). The per-channel current-ACM statistics also are written to L2 cache (129), where they are used in the implementation of the channel kurtosis calculation (135) (described in more detail below).

The per-channel CCM and current-ACM statistics are then accumulated (128) using formula

Rxprior⁢xcurrent=∑kchn∈𝒦subbandRxprior⁢xcurrent(kchn)(27)Rxcurrent⁢xcurrent=∑kchn∈𝒦subbandRxcurrent⁢xcurrent(kchn)(28)
for DICE adaptation frame nframe, where Ksubbandis the set of active frequency channels covering the bandwidth of the MUOS signal with substantive energy. (To simplify notation used here, the reference to a specific subband lsubbandshall be dropped except when needed to explain operation of the system, and it shall be understood that Ksubbandis referring to one of the specific active subbands {Ksubband(lsuband)}lsubband=03processed by the DICE system.)

The Cholesky factors of the current ACM statistics are then computed, yielding

Rxcurrent=chol⁢{Rxcurrent⁢xcurrent},(29)
where Rx=chol{Rxx} is the upper-triangular matrix with real-nonnegative diagonal elements yielding RxHRx=Rxxfor general nonnegative-definite matrix Rxx. The spatially-whitened CCM(131) is then given by

Txprior⁢xcurrent=CxpriorH⁢Rxprior⁢xcurrent⁢Cxcurrent,(30)
where Cx=Rx1is the inverse Cholesky factor of Rxx. The multiplications shown in (30) are performed using back-substitution algorithms, requiring storage of only the diagonal elements of Cx, which are themselves generated as an intermediate product of the Cholesky factorization operation and are equal to the inverse of the diagonal elements of Rx. This reduces the computational density and storage requirements for these operations.

Note that the CCM and ACM statistics given by the processes implementing computation of Equations (22)-(28) are unweighted, that is, the summation does not include a tapering window and is not multiplied by the time-bandwidth product of the input data matrices (the ACM statistics are more precisely referred to as Grammian's in this case). This normalization can be added with no loss of generality (albeit at some potential cost in complexity if NTBPis not a power of two) if computed using a floating point DSP element (31); the unnormalized statistics shown here are the best solution if a fixed or hybrid DSP element (31) is used to compute the statistics, or if the ACM and CCM statistics computation is performed in the FPGA (30) in alternate embodiments. Unweighted statistics are employed here to both reduce operating time of the statistics accumulation, and to avoid roundoff errors for a fixed-point DSP element (31) used in this DICE embodiment. Because the input data has 16-bit precision (and even in systems in which data is transferred at its full 25 bit precision), the entire accumulation can be performed at 64-bit (TI double-double) precision accuracy without incurring roundoff or overflow errors. Moreover, any weighting is automatically removed by the spatial whitening operation shown in the processes implementing computation of Equation (30). However, care must be taken to prevent the calibration statistic adjustment from causing overflow of the 64-bit statistics.

In this embodiment of the DICE system, an additional step is taken immediately before the statistics accumulation, to remove a half-bit bias induced by the FPGA (30). In a 16-bit reducing embodiment, the FPGA (30) truncates the 25-bit precision channelizer data to 16-bit accuracy before transferring it to the DSP element (31), which adds a negative half-bit bias to each data sample passed to the DSP element (31). Because the bias is itself self-coherent across frames, it introduces an additional feature that is detected by the algorithm (in fact, it is routed to the first SCORE port and rejected by the SOI tracker). In order to reduce loading caused by this impairment, the DSP data is adjusted using the, the processes implementing computation of:

Xcurrent(kchn)⁢¬2⁢Xcurrent(kchn)+complex(1,1),(31)
i.e., each rail of Xcurrent(kchn,nframe) is upshifted by one bit and incremented by 1, after conversion to 64-bit precision but before the ACM and CCM operation (128). This impairment can be removed in the FPGA (30) by replacing the truncation operation with a true rounding operation; however, the data is preferentially transferred to the DSP element (31) at full 25-bit precision to eliminate this effect and improve dynamic range of the algorithm's implementation in the presence of narrowband interference.

Also, embodiment preferentially uses a hybrid or floating point DSP element (31), rather than a fixed-point DSP. This enables access to BLAS, LINPACK, and other toolboxes that will be key to alternate system embodiments (e.g., coherence phase tracking algorithms requiring EIG rather than SVD operations).

Assuming the SW-CCM is computed (131) every frame, complexity of the statistic accumulation operation can be substantively reduced by storing the prior-frame ACM statistics and Cholesky factors at the end of each frame, and then reusing those statistics in subsequent frames (134). If the prior-frame ACM statistics do not exist, then the prior-frame ACM statistics are computed using processes implementing computation of:

Xprior(kchn)⁢¬2⁢Xprior(kchn)+complex(1,1)(32)Rxprior⁢xprior(kchn)=XpriorH(kchn)⁢Xprior(kchn)(33)Rxprior⁢xprior(kchn)←Rxprior⁢xprior(kchn)∘(wca⁢l*(kchn)⁢wca⁢lT(kchn))(34)Rxprior⁢xprior=∑kchn∈𝒦subbandRxprior⁢xprior(kchn)(35)Rxprior=chol⁢{Rxprior⁢xprior}.(36)

This condition will occur during the first call of the algorithm; if a pathological data set is encountered; or if for any reason a frame is skipped between algorithm calls.

In an alternate embodiment, the CCM and ACM statistics are additionally exponentially averaged to improve accuracy of the statistics, by using processes implementing computation of

Rxprior⁢xcurrent(kchn)⁢¬Rxprior⁢xcurrent(kchn)+XpriorH(kchn)⁢Xcurrent(kchn)(37)Rxcurrent⁢xcurrent(kchn)⁢¬Rxprior⁢xprior(kchn)+XcurrentH(kchn)⁢Xcurrent(kchn),(38)
rather than the processes implementing computation of Equations (22)-(23) to compute the CCM and ACM statistics inFIG.12, where 0≤μ<1 is an exponential forget factor that reduces to the primary embodiment for μ=0. A slightly less computationally complex operation can be implemented by exponentially averaging the CCM and ACM statistics after the channel combining operation, e.g., by using

Rxprior⁢xcurrent←μ⁢Rxprior⁢xcurrent+∑kchn∈𝒦subbandRxprior⁢xcurrent(kchn)(39)Rxcurrent⁢xcurrent←μ⁢Rxcurrent⁢xcurrent+∑kchn∈𝒦subbandRxcurrent⁢xcurrent(kchn),(40)
to update the subband ACM and CCM statistics inFIG.12, where Rxpriorxcurrent(kchn) and Rxcurrentxcurrent(kchn) are given by processes implementing Equations (24) and (25), respectively. Exponential averaging can increase the effective time-bandwidth product of the CCM and by a factor of 1/(1), e.g., by a factor of four for μ=¾□□□□□□□□□□□ in a 6 dB improvement in feature strength for signals received with a maximum attainable SINR that is greater than 1.

In both cases, the exponential averaging can be performed without overloading fixed averaging operations, if the effective TBP improvement does not overload the dynamic range of the DSP element (31). For the example given above, exponential averaging only loads 2 bits of dynamic range onto the averaging operation.

The forget factor μ can also be dynamically adjusted to react quickly to dynamic changes in the environment, e.g., as interferers enter or leave the channel, or if the cross-frame correlation of the MUOS signal changes abruptly. The ACM statistics can be used to detect these changes with high sensitivity and under strong co-channel interference, e.g., using methods described in [B. Agee, “Fast Acquisition of Burst and Transient Signals Using a Predictive Adaptive Beamformer,” inProc.1989IEEE Military Communications Conference, October1989].

Multiport Self-Coherence Restoral Weight Adaptation Procedure

The baseline multiport self-coherence restoral (SCORE) algorithm used in this DICE embodiment is implemented using the iterative QR method,

{Ucurrent,DSCORE}←QRD⁢{Txprior⁢xcurrentH⁢Uprior}(41){Uprior,DSCORE}⁢¬QRD⁢{Txprior⁢xcurrent⁢Ucurrent},(42)
where Uprioris the spatially-whitened combiner weights from the prior frame, and where {U,D}=QRD{V} is the QR decomposition (QRD) of general complex MfeedLportmatrix V, such that D and U satisfy

D=chol⁢{VH⁢V}(43)DU=V(44)
if V has full rank such that D is invertible. The QRD can be computed using a variety of methods; in the DICE embodiment it is performed using a modified Graham-Schmidt orthogonalization (MGSO) procedure. If Upriordoes not exist (initialization event), then {Ucurrent,DSCORE} is initialized to

{Ucurrent,DSCORE}=QRD⁢{Txprior⁢xcurrentH((Mfeed⁢Lport):Mfeed,:)}(45)where⁢Txprior⁢xcurrent((Lport⁢Mfeed):Mfeed,:)⁢is⁢the⁢lower⁢Lport⁢columns⁢of⁢Txprior⁢xcurrent.

Over multiple iterations of the processes implementing computation of Equations (41)-(42), {Uprior,DSCORE,Ucurrent} converges exponentially to the SVD of Txpriorxcurrent,

{Uprior,DSCORE,Ucurrent}→S⁢V⁢D⁢{Txprior⁢xcurrent}(46)⇔Txprior⁢xcurrent=Uprior⁢DSCORE⁢UcurrentH,{UpriorH⁢Uprior=IMfeedUcurrentH⁢Ucurrent=IMfeedDSCORE=diag⁢{dscore}(47)
where IMfeedis the MfeedMfeedidentity matrix and diag{d} is the Matlab diag operation for vector input d, with exponential convergence based on the ratio between the elements of dSCORE(also referred to as the mode spread of the SVD). It should also be noted that the recursion can be employed for Lport<Mfeedport, in which case the implementation of the algorithm converges to the first Lportstrongest modes of the SVD with exponential convergence (greatly reducing the computational processing load). For the simplest case where Lport=1, the implementation of the algorithm reduces to a power method recursion.

After multiple iterations of the processes implementing computation of Equations (41)-(42), the final SCORE weights and modes are computed from:

{Ucurrent,DSCORE}←QRD⁢{Txprior⁢xcurrentH⁢Uprior}(final⁢QR⁢iteration)(48)dSCORE=diag⁢{DSCORE}(diagonal⁢element⁢selection)(49)Rxcurrent⁢WSCORE=Ucurrent(spatial⁢unwhitening⁢operation),(50)
where diag{D}=[(D)l,l]l=1Lportis the Matlab diag operation for LportLportmatrix input D, and where the process implementing Equation (50) is performed using a back-substitution operation. The unwhitened SCORE combiner weights also orthonormalize the output signal,

WSCOREH⁢Rxcurrent⁢xcurrent⁢WSCORE=UcurrentH⁢Ucurrent=ILport(51)
regardless of how well Ucurrentconverges to the right-singular vectors of Txpriorxcurrent(nframe).

In practice, only the processes implementing Equations (48)-(50) need be computed over each frame, i.e., the processes implementing QR recursion described in Equations (41)-(42) may be skipped, thereby greatly reducing complexity of the processing and computation of this implementation. This results in a stochastic QR method over multiple frames, in which the modes converge to the modes of the underlying asymptotic SVD of the spatially-whitened CCM, with continuous, low-level misadjustment due to random differences between the measured and asymptotic signal statistics. Under normal operating conditions where the MUOS signal is received at a low signal-to-white-noise ratio (SWNR), this misadjustment will be small; however, at higher power levels and especially in dispersive environments, this misadjustment can be significant. In this DICE embodiment, four recursions of the processes implementing Equations (41)-(42) are performed in each frame to minimize this effect.

After they are computed, both Ucurrentand WSCOREare written to L2 cache, where they are used as prior weights in subsequent adaptation frames (123). Under normal operating conditions, Ucurrentfrom the current frame is used as Upriorto initialize in the next frame to initialize the processes implementing either Equation (41) or (48) without change; however, if a skipped frame is detected, Uprioris set from WSCOREusing spatial whitening through the process implementing:

Uprior=Rxprior⁢WSCORE(52)
prior to activating the processes implementing Equation (41) or (48), where Rxprioris also newly computed over that frame.

Alternate embodiments of the processes implementing the methods described by these equations can accelerate convergence of the SVD, for example, using Hessenberg decomposition and shift-and-deflation methods well known to those skilled in the art. However, the benefits of that acceleration are uncertain for the stochastic QR method, especially if only the processes implementing Equations (48)-(50) are computed over each frame. Such SVD-convergence acceleration comes with an initial cost to compute the Hessenberg decomposition at the beginning of the recursion, and to convert the updated weights from the Hessenberg decomposition at the end of the recursion, that may outweigh the performance advantages of the approach.

Similar acceleration methods can be Old to compute the true eigendecomposition of Txpriorxcurrent, which provides a complex eigenvalue related to the cross-frame coherence strength and phase of the MUOS A-CPICH. The cross-coherence phase will differ between different satellites in the field of view of antennas attached to the receiver. Hence, this refinement can greatly enhance ability to detect and separate multiple access interference (MAI) in operational MUOS systems, especially in reception scenarios in which the MUOS emissions have nearly equal observed power levels at antennas attached to the receiver. This approach provides additional protection against EA measures designed to spoof or destabilize the algorithm, by providing an additional feature dimension (coherence phase) that must be duplicated by the spoofer.

The SCORE modes dSCOREare used by the SOI tracker to provide a first level of discrimination between SOI's and signals-not-of-interest (SNOI's). Based on information provided in the public literature, and on statistics gathered during operation of the invention in real representative test environments, the MUOS signal should have a cross-frame coherence strength (correlation coefficient magnitude between adjacent 10 ms MUOS frames) between 0.1 and 0.5. In contrast, a CW tone should have a cross-frame coherence strength of unity, and a non-MUOS interferer should have a cross-frame coherence strength of zero. Accordingly, a minimum coherence of 0.1 (dSCOREdmin=0.1) and maximum coherence threshold of 0.5 (dSCOREdmax=0.5) are used to provide a first level of screening against non-MUOS signals.

Channel Kurtosis Calculation Procedure

The set of processes implementing the channel kurtosis algorithm (135) provides a second level of screening against CW signals as well as any narrowband interferers that may be inadvertently detected by the SCORE algorithm, by computing the kurtosis of the linear combiner output power over the active channels in the MUOS subband (134). The channel kurtosis is given by

κsubband(ℓport)=△Ksubband⁢∑kchn∈𝒦subbandRycurrent⁢ycurrent2(kchn;ℓport)(∑kchn∈𝒦subbandRycurrent⁢ycurrent(kchn;ℓport))2,(53)
where Ksubbandis the number of frequency channels covering the active bandwidth of the MUOS signal (Ksubband=40 for this DICE system embodiment), and where Rycurrentycurrent(kchn;lport) is the unnormalized power (L2 Euclidean norm) of the port lportSCORE output signal on frequency channel kchn,

Rycurrent⁢ycurrent(kc⁢h⁢n;ℓport)=△wSCOREH(ℓport)⁢Rxcurrent⁢xcurrent(kchn)⁢wSCORE(ℓport)=ycurrent(kchn,ℓport)22(54)ycurrent(kchn,ℓport)=△Xcurrent(kchn)⁢(wca⁢l(kchn)∘wSCORE(ℓport)),
and where WSCORE(lport)=WSCORE(:,lport) is column lportof WSCORE. From (51), it can be shown that

∑kchn∈𝒦subbandRycurrent⁢ycurrent(kchn;ℓport)=wSCOREH(ℓport)⁢Rxcurrent⁢xcurrent⁢wSCORE(ℓport)(55)1,ℓport=1,▯,Lport
allowing simplification

κsubband(ℓport)=Ksubband⁢∑kchn∈𝒦subbandRycurrent⁢ycurrent2(kchn;ℓport).(56)

The channel kurtosis is greater than unity, is approximated by unity for a MUOS SOI, and is approximated by KSNOI/Ksubbandfor a SNOI occupying KSNOIfrequency channels. In this DICE embodiment, SCORE ports with kurtosis greater than 8(subband>max=8), corresponding to 924 KHz SOI bandwidth, are identified as SNOI ports, even if their cross-frame coherence strength is within the minimum and maximum threshold set by the SCORE algorithm.

Channel kurtosis is one of many potential metrics of spectral occupancy of the subband. It is chosen here because an implementation of it can be computed at low complexity and with low memory requirement. As a useful byproduct (further enhancing computational efficiency of the invention), this instantiation of the algorithm also computes the spectral content of each SCORE output signal, which can be used in ancillary display applications.

SOI Tracker Procedure

FIG.13shows the flow diagram for a process (or sub-method) implementing the algorithm used to update SOI beamforming weights in the subband-channelized DICE embodiment. This procedure (SOI Tracker) is activated (149) and tests whether any valid SCORE ports are available (150) when either (a) SOI beamforming weights are available for the subband (136), or (b) valid SCORE ports (e.g., SCORE ports that meet the cross-frame coherence and channel kurtosis criteria possessed by valid MUOS signals) are identified by the SCORE processes shown inFIG.12(135). If no SOI beamforming weights (also referred to in this embodiment as “SOI weights” for brevity) are available for the subband, but at least one valid SCORE port has been identified, then the process initializes wSOIto the valid SCORE port with the highest coherence strength, and initializes a heap counter (sets heap count Cheap for the subband to zero) (151). If no valid SCORE ports are found during the current frame, and SOI beamforming weights wSOIare available for the subband (137), the process adjusts the SOI beamforming weights wSOIfor the subband to yield a beamformer output signal with unity norm, by setting

wSOI⁢¬wSOIuSOI2,(57)
where uSOI=RxcurrentwSOIis the Mfeed1 SOI beamformer combiner weights, whitened over the current data frame, and the heap count is incremented by one (cheap¬cheap+1)(152).

If valid SCORE ports have been found, and SOI beamforming weights are available, then a lock metric is computed based on the least-squares (LS) fit between the spatially whitened SOI beamforming weights uSOIand the valid SCORE ports, given by

εSOI(ℒvalid)=ming∈ℂLvaliduSOI-Ucurrent(:,ℒvalid)⁢g22uSOI22,(58)
where Lvalid={lport(1),□,lport(Lvalid)} is the set of LvalidSCORE ports that meet the cross-frame coherence and channel kurtosis thresholds set in the process implementing the multiport SCORE algorithm (seeFIG.14), and Ucurrent(:,Lvalid) is the MfeedLvalidmatrix of spatially whitened SCORE weights computed over the valid SCORE ports,

Ucurrent(:,ℒvalid)=[Ucurrent(:,ℓport(1))⁢…⁢Ucurrent(:,ℓport(Lvalid))],(59)
and where U(:,l), is the lthrightmost column of matrix U. Because the whitened multiport SCORE weights are orthonormal, the LS fit is simply computed using the cross-product

gLS=UcurrentH(:,ℒvalid)⁢uSOI(60)εSOI(ℒvalid)|LS=1-gLS22uSOI22=1lock2,(61)
wherelockis the lock metric, also referred to here as the lock-break statistic,

ρlock=△gLS2/uSOI2.(62)

The lock-break statistic is guaranteed to be between 0 and 1, and is equal to unity if the prior weights lie entirely within the space spanned by the valid SCORE weights (153).

If the lock metric is below a preset lock-fit threshold (lock<min), then the tracker is presumed to be out of lock. In this case, if the heap count has not exceeded a specified maximum heap count threshold (cheapcmax)(154), then the process assumes that an anomalous event has caused lock to break, adjusts the SOI beamforming weights for the subband to unity output norm using the processes implementing Equation (57), i.e., without changing the SOI beamforming weights except for a power adjustment, and increments the heap count by one (cheap¬cheap+1)(152). If the lock metric is below the threshold and the heap count has been exceeded (cheap>cmax)(155), then the process assumes that lock has been lost completely, sets wSOIto the valid SCORE port with the highest coherence strength, and resets cheapfor the subband to zero (151). In an embodiment, the maximum heap count threshold is set to 200 (cmax=200).

If the lock metric is above the lock-fit threshold (lock min)(156), then the process resets (initializes) cheapfor the subband to zero (157), and sets the spatially-whitened SOI beamforming weights to the unit-norm LS fit between the prior weights and the valid multiport SCORE beamforming weights,

uSOI←Ucurrent(:,ℒvalid)⁢gLSgLS2,(63)
where gLSis given by the processes implementing Equation (60). The new unit-norm, spatially-unwhitened SOI tracker weights are then computed using back-substitution (158)

Rxcurrent⁢wSOI=uSOI.(64)

These three paths all end with terminating (159) this SOI Tracker procedure.

For one DICE embodiment, the lock-fit threshold is set to (min=0.25). This tracker algorithm implementation is chosen to minimize effects of hypersensitivity in highly dispersive environments where the MUOS SOI can induce multiple substantive SCORE solutions, and to maintain phase and gain continuity between adaptation frames. In addition, the LS fitting process is easily refined over multiple data frames using statistics and weights computed in prior steps.

FIG.14shows the flow diagram for a SOI tracker algorithm used in an alternate embodiment that can track multiple valid SOI's. This embodiment is particularly useful for applications in which valid signals-of-interest are received from multiple transmitters in the field of view of receive antennas attached to the DICE system, e.g., multiple MUOS SV's in the receiver's field of view. The tracker differs from the single-SOI tracker shown inFIG.13in the following respects:It can create multiple SOI ports, and attempts to match those SOI ports to subsets of valid SCORE ports based on a single-port lock metric.It possesses mechanisms for increasing SOI's tracked (number of SOI ports) over the processing interval, based on failure of a valid SCORE port to match to any SOI port.It possesses mechanisms for decreasing the number of SOI's tracked (number of SOI ports) over the processing interval, based on a heap counter comprising the number of consecutive frames in which a SOI has not been successfully tracked.It provides additional mechanisms for measuring phase as well as strength of cross-frame coherence, in order to exploit differing phase of the cross-frame coherence between SOI's received from different transmitters in the environment, and to refine multiport SCORE weights based on those metrics.

In the embodiment shown inFIG.14, when this procedure (Multi-SOI Tracker) is activated (170) the first step performed by the tracker is to determine if any valid SCORE ports are present (171).

This is accomplished by using the MfeedLvalidmatrix of current whitened valid multiport SCORE weights Ucurrent(:,Lvalid) (13), determined as part of the coherence strength and kurtosis metrics computation procedure described above, to determine a set of MfeedLvalidphase-mapped SCORE weights Vcurrent(174) using the linear transformation

Vcurrent=Ucurrent(:,ℒvalid)⁢Gvalid,(65)
where each column of the LvalidLvalidphase-mapping matrix Gvalidapproximates a solution to the phase-SCORE eigenequation

valid(ℓ)⁢gvalid⁢(ℓ)=Tvalid⁢gvalid⁢(ℓ),ℓ=1,▯,Lvalid.(66)Tvalid=△UcurrentH(:,ℒvalid)⁢Txprior⁢xcurrentH⁢Uprior(:,ℒvalid),(67)
and where Uprior(:,Lvalid) is the matrix of MfeedLvalidwhitened prior multiport SCORE weights computed over the valid SCORE port (133). The process implementing Equation (66) yields a closed form solution if two or less valid SCORE ports are identified, as is typical in MUOS reception environments, namely,

valid=UcurrentH(:,ℓport(1))⁢Txprior⁢xcurrentH⁢Uprior(:,ℓport(1))(68)gvalid=1(69)if⁢Lvalid=1,andλvalid=[s+d2+cs-d2+c],{s=12⁢(t11+t22)d=12⁢(t11-t22)c=t12⁢t21.(70)Gvalid=((d⁢d2+c)t12t21d⁢d2+c)(71)
if Lvalid=2, where

Tvalid=(t11t12t21t22).
The columns of Gvalidare then adjusted to unit norm, such that ∥Gvalid(:,l)∥21 and therefore ∥Vcurrent(:,l)∥21. However, it should be noted that Gvalidis not in general orthonormal, and therefore Vcurrentis not orthonormal.

If no valid SCORE ports exist, then the SOI weights are normalized and the heap counters are incremented (172). If at least one valid SCORE port exists (173), then the process maps valid SCORE weights to phase-sensitive weights and compares these to the SOI port(s) (174).

If no SOI ports exist (175), the MfeedLSOIwhitened SOI beamforming weights USOIare initialized to Vcurrent, the number of SOI ports LSOIis initialized to Lvalid, and the LSOI1 heap counter cheapis set to zero on each element. The MfeedLSOIunwhitened SOI beamformer weights WSOIare then normalized (193) computed by solving back-substitution

Rxcurrent⁢WSOI=USOI,(72)
and this terminates this instantiation of this process (199).

If valid SOI ports do exist (173), then the valid SCORE ports are fit to existing SCORE ports over the SOI ports (178), by first forming spatially-whitened SOI beamforming weights USOI=RxcurrentWSOIfrom the existing SCORE weights WSOI, and then computing the fit-gains {gLS(lvalid,lSOI)} that minimizes the least-squares (LS) fit between each column of USOIand Vcurrent, yielding optimized fit gain

gLS(ℓvalid,ℓSOI)=VcurrentH(:,ℓvalid)⁢USOI(:,ℓSOI)(73)
and least-squares fit-metric

LS(ℓvalid,ℓSOI)=❘"\[LeftBracketingBar]"gLS(ℓvalid,ℓSOI)❘"\[RightBracketingBar]",(74)
which is maximized when the LS fit is close. The fit metric (74) is then used to associated the phase-mapped multiport SCORE ports with the SOI ports, by setting

ℓvalid(ℓSOI)=argmaxℓ=1,▯,LvalidLS(ℓ,ℓSOI).(75)lock(ℓSOI)=LS(ℓvalid(ℓSOI),ℓSOI).(76)

For each SOI port this process initiates (177), if the lock metric is above the lock-fit threshold for SOI port lSOI(lock(lSOI)min) (179), then the spatially-whitened SOI beamforming weights for SOI port lSOIare set equal to

USOI(:,ℓSOI)⁢¬Vcurrent(:,ℓvalid(ℓSOI))⁢sgn⁢{gLS(ℓvalid(ℓSOI))},(77)
and heap counter cheap(lSOI) is reset (initialized) to zero (180). If the lock metric is below the lock-fit threshold for SOI port lSOI(lock(lSOI)<min), and the heap count has not exceeded the maximum value (cheap(lSOI)cmax) (183), then the unwhitened SOI port lSOIbeamforming weights are adjusted to provide unity output norm,

WSOI(:,ℓSOI)⁢¬WSOI(:,ℓSOI)USOI(:,ℓSOI)2,(78)
and the heap count for SOI port lSOIis incremented by one (cheap(lSOI)¬cheap(lSOI)+1) (184). If the lock metric is below the lock-fit threshold and the heap count has exceeded the maximum value (181), then the SOI port and all of its associated parameters are removed from the list of valid SOI ports (182). The implementation then moves onto the next SOI port (190) and to the fitting of valid SCORE ports to the current selection of the SOI port (178) if any remain unfitted.

Once all of the SOI ports have been sorted (191), any valid phase-mapped multiport SCORE ports that have not yet been associated with SOI are assigned to new SOI ports with heap counters initialized to zero (192). This allows new SOI's to detected and captured when they become visible to the DICE system, e.g., as MUOS satellites come into the field of view of the DICE antennas. All as-yet unwhitened SOI beamforming weights are then computed from the whitened SOI beamforming weights (193), and the SOI tracking process is completed, terminating this Multi-SOI Tracking procedure (199).

In another embodiment, the MfeedLvalidvalid multiport SCORE beamforming weights Ucurrent(:,Lvalid) given by the processes implementing Equation (59) can be directly sorted using the procedure shown inFIG.11, without the intermediate phase mapping operation. In this case, the ability to separate SOI's based on phase of the cross-frame coherence is lost; however, in many reception scenarios this can still be sufficient to effectively separate the signals.

In another embodiment, the valid multiport SCORE ports can be partitioned into subsets of valid ports associated with each SOI, e.g., based on common phase of the phase-mapped SCORE eigenvalues, or based on fit metrics given in (74). In this case, the lock metric is given by

lock(ℓSOI)=gLS⁢(ℓSOI)2/USOI(:,ℓSOI)2(79)gLS(ℓSOI)=QcurrentH(ℓSOI)⁢USOI(:,ℓSOI)(80)Qcurrent(ℓSOI)=QRD⁡(Vc⁢u⁢r⁢r⁢e⁢n⁢t(:,ℒv⁢a⁢l⁢i⁢d(ℓSOI)))(81)
where Lvalid(lSOI) is the set of Lvalid(lSOI) valid multiport SCORE ports associated with SOI port lSOIand Vcurrent(:,LValid(lSOI)) is the MfeedLvalid(lSOI) matrix of (phase-mapped) SCORE beamforming weights covering those ports, and where Qcurrent(lSOI) (is the whitened phase-mapped SCORE weight matrix, given in the processes implementing Equations (43)-(44). If the lock metric is above the lock-fit threshold, then the beamforming weights for SOI port lSOIis given by

USOI(:,ℓSOI)⁢¬Qcurrent(:,ℓSOI)⁢gL⁢S(ℓSOI)gL⁢S(ℓSOI)2.(82)

If the phase-mapping is not performed, then the multiport SCORE weights are already orthonormal, and Qcurrent(lSOI)=Vcurrent(:,Lvalid(lSOI)). This embodiment reduces effects of hypersensitivity in highly dispersive environments where the MUOS SOI can induce multiple substantive SCORE solutions.

In another embodiment, the SCORE weights are directly computed from TxpriorxcurrentH, by solving for the eigenvalues and eigenvectors of the phase-SCORE eigenequation,

valid(ℓ)⁢vvalid(ℓ)=Txprior⁢xcurrentH⁢vvalid(ℓ),(83)ℓ=1,,Lport.
using eigenequation computation methods well known to those skilled in the art. These weights can then be directly sorted by strength to determine both the number of valid SCORE ports, and by phase to further separate the valid ports into SOI subsets.
FPGA BFN Weight Computation Procedure

The SOI tracker weights are converted to FPGA weights using a three-step operation:

First, the weights are multiplied by calibration weights on each active subband channel, yielding

wFPGA⁢(kc⁢h⁢n)=wcal(kchn)∘wSOI.(84)

Then, the weights are then scaled to meet an output norm target. Conceptually, this is given by

wFPGA⁢(kc⁢h⁢n)⁢¬gFPGA⁢wFPGA(kc⁢h⁢n).(85)
where gFPGAis a scaling constant, which can be precomputed as {wSOI} is scaled to yield unity output norm under all conditions, since

ySOI(kchn)2=Xcurrent(kchn)⁢wFPGA(kchn)2(86)=gFPGA2⁢Xcurrent(kc⁢h⁢n)⁢(wcal(kc⁢h⁢n)∘wSOI)2(87)=gFPGA2(88)
at the output of the SOI tracker. In the embodiment shown here, gFPGA=230. Lastly, the MSB of the FPGA weights are computed, and used to scale and convert those weights to 16-bit precision, and to derive a shift to be applied to the data after beamforming.

Once the beamforming weights and scaling factor have been computed, a DMA transfer is triggered, to effect transfer of the weights and scaling factor to the FPGA (30) over the EMIF bus (32). A “Weights Ready” semaphore is then set inside the FPGA (30), alerting it to the presence of new weights. The FPGA (30) then applies these weights to its Beamforming Network (34) shown inFIG.4, along with the scaling factor used to maintain continuity of output power between adaptation frames.

In one embodiment, a number of ancillary metrics are also computed by the implementation of the algorithm, which are also transferred over the EMIF to a host computer allowing display for control, monitoring, and diagnostic purposes.

This weight computation procedure extends to multi-SOI tracking embodiments in a straightforward manner, by applying the processes implementing Equations (84)-(85) to each individual SOI beamforming weight vector.

Dispersion Compensation Procedure

The dispersion compensation processing is designed to correct for cross-feed dispersion induced in the DICE front-end due to frequency mismatch between the DICE bandpass filters. Modeling the ideal channelizer output signal by

x⁡(kchn,nchn)❘"\[LeftBracketingBar]"ideal=xs⁢k⁢y(kchn,nc⁢h⁢n)❘"\[RightBracketingBar]"ideal+εR⁢x(kchn,nc⁢h⁢n)(89)xs⁢k⁢y(kchn,nchn)❘"\[LeftBracketingBar]"ideal=εsky(kchn,nc⁢h⁢n)+∑ℓemitaideal⁢(ℓe⁢m⁢i⁢t)⁢semit(kchn,nchn)(90)
where εsky(kchn,nchn) is the Mfeed1 sky noise added to the DICE signal ahead of the BPF's, {aideal(lemit)} are the frequency-independent (nondispersive) spatial signatures for each of the emitters received by the DICE system, and εRx(kchn,nchn) is the receiver noise added after the BPF's, then the true channelizer output response can be modeled by

x⁡(kc⁢h⁢n,nc⁢h⁢n)=(gB⁢P⁢F(kc⁢h⁢n)∘xsky(kc⁢h⁢n,nchn)❘"\[RightBracketingBar]"ideal)+εRx(kchn,nc⁢h⁢n)=ε⁢(kc⁢h⁢n,nc⁢h⁢n)+∑ℓemita⁢(kc⁢h⁢n,ℓemit)⁢semit(kc⁢h⁢n,nc⁢h⁢n)(91)
where {gBPF(kchn)} are the Mfeed1 BPF responses on each frequency channel and ε(kchn,nchn) is the combined nonideal receiver noise,

ε⁢(kc⁢h⁢n,nc⁢h⁢n)=(gB⁢P⁢F(kc⁢h⁢n)∘εs⁢k⁢y(kc⁢h⁢n,nc⁢h⁢n))+εR⁢x(kc⁢h⁢n,nchn)(92)
and where {a(kchn,lemit)} are dispersive spatial signatures given by

a⁢(kc⁢h⁢n,nc⁢h⁢n)=gBPF(kc⁢h⁢n)∘aideal(kchn,nc⁢h⁢n)(93)

Assuming the BPF differences are small and/or the receiver noise is small relative to the sky noise, then the receive signal can be approximated by

xFPGA⁢(kchn,nc⁢h⁢n)≈gB⁢P⁢F(kc⁢h⁢n)∘x⁡(kchn,nc⁢h⁢n)❘ideal(94)
within the FPGA, where

x⁡(kchn,nc⁢h⁢n)❘"\[LeftBracketingBar]"ideal=ε⁢(kc⁢h⁢n,nchn)❘"\[RightBracketingBar]"ideal+∑ℓemitaideal(ℓemit)⁢semit(kchn,nchn)(95)
is an ideal nondispersive response. Further assuming that the BPF differences can be computed to within at least a scalar ambiguity gcal, then the dispersive receive signal can be transformed to a nondispersive signal by setting

xcal(kchn,nc⁢h⁢n)=wcal(kchn)∘xFPGA⁢(kchn,nc⁢h⁢n)(96)gcal⁢x⁡(kc⁢h⁢n,nc⁢h⁢n)❘idealwherewcal(kc⁢h⁢n)⁢gcal·/⁢gBPF(kc⁢h⁢n)(97)
and where “./” denotes the Matlab element-by-element divide operation. Given two M N arrays “X=[X(m,n)]” and “Y=[Y(m,n)]”, Z=X./Y creates an M N matrix with elements Z(m,n)=X(m,n)/Y(m,n), where “/” is a scalar divide operation. This is the mathematical basis for the gain compensation processing implementation.

Assuming conceptually that the cross-feed dispersion has been removed and beamforming weights wDSPhave been computed in the DSP for compensated data set xcal(kchn,nchn), then the beamformer output data can be expressed as

y⁡(kc⁢h⁢n,nc⁢h⁢n)=wD⁢S⁢PT⁢xcal(kc⁢h⁢n,nc⁢h⁢n)=wD⁢S⁢PT(wcal(kchn)∘xFPGA(kchn,nchn))=(wcal(kchn)∘wD⁢S⁢P)T⁢xFPGA(kchn,nchn)(98)=wFPGAT(kc⁢h⁢n)⁢xFPGA(kc⁢h⁢n,nc⁢h⁢n)
where FPGA beamforming weights wFPGA(kchn)=wcal(kchn)∘wDSPare applied directly to the uncompensated FPGA data. Thus there is no need to compensate each FPGA channel directly, as the compensation can be applied to the DSP weights instead, simplifying and speeding this task. Defining (again conceptually) calibrated current data frame: