Patent ID: 12249610

Since the drawings inFIGS.1-23are intended for illustrative purposes, the elements in the drawings are not necessarily drawn to scale. For example, some of the elements may be enlarged or exaggerated for clarity purpose.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings.

FIG.1is a diagram illustrating the layout of an image sensor100according to an example embodiment of the present inventive concept.

Referring toFIG.1, the image sensor100may include an active pixel region APR, a peripheral circuit region PCR, and a pad region PDR, which are formed in a semiconductor substrate110.

The active pixel region APR may be in a central portion of the semiconductor substrate110, and the peripheral circuit region PCR may be on both sides of the active pixel region APR. For example, the peripheral circuit region PCR may be on the right side and the left side of the active pixel region APR. A pad region PDR may be in an edge portion of the semiconductor substrate110. For example, the pad region PDR may be in the top edge portion and at the bottom edge portion in a view from above.

The active pixel region APR may include a plurality of pixels PX, and a plurality of photoelectric conversion regions (refer to PD inFIG.4) may be respectively in the plurality of pixels PX. In the active pixel region APR, the plurality of pixels PX may be arranged in a matrix form of rows and columns in a first direction parallel to a top surface of the semiconductor substrate110and a second direction parallel to the top surface of the semiconductor substrate110. The second direction may be perpendicular to the first direction. However, the present inventive concept is not limited thereto. For example, the plurality of pixels PX may be arranged in a pentile matrix shape, or a diamond shape.

Although the peripheral circuit region PCR is illustrated as being on both sides of the active pixel region APR in a view from above, the present inventive concept is not limited thereto, and the peripheral circuit region PCR may entirely surround the active pixel region APR. Alternatively, the peripheral circuit region PCR may surround three sides of the active pixel region APR. A conductive pad PAD may be in the pad region PDR. The conductive pad PAD may be on the edge portion of the semiconductor substrate110.

FIGS.2and3are diagrams illustrating the layout of an image sensor100according to an example embodiment of the present inventive concept. For example,FIG.2is an enlarged layout diagram of region II ofFIG.1at a first vertical level LV1, andFIG.3is an enlarged layout diagram of region II ofFIG.1at a second vertical level LV2(seeFIG.4).FIG.4is a cross-sectional view taken along line A1-A1′ ofFIGS.2and3.FIG.5is a cross-sectional view taken along line A2-A2′ ofFIGS.2and3.FIG.6is a cross-sectional view taken along line A3-A3′ ofFIGS.2and3.FIG.7is an enlarged view of region CX2ofFIG.4.FIG.8is a circuit diagram of a pixel PX of the image sensor100, according to an example embodiment of the present inventive concept.

Referring toFIGS.2to8, the image sensor100may include an image sensor of a global shutter type. During an operation of the image sensor of the global shutter type, charges may be simultaneously stored in each of pixels PX by simultaneously exposing all the pixels PX, and pixel signals may be sequentially output for each row. For example, because the image sensor of the global shutter type exposes all of the pixels PX at the same time, it may enable the capture of distortion-free images in comparison to a rolling shutter type.

The pixel PX of the image sensor100may include a photoelectric conversion region PD, a transfer transistor TG, a first floating diffusion region FD1, a reset transistor RG, a dual conversion gain (DCG) transistor DCG, a second floating diffusion region FD2, a first source follower transistor SF1, a pre-charge transistor PC, a sample transistor SAM, a first capacitor C1, a second capacitor C2, a calibration transistor CAL, a second source follower transistor SF2, a first selection transistor SEL1, a second selection transistor SEL2, a first node X, and a second node Y.

One pixel PX may be electrically insulated from a pixel PX adjacent thereto by a pixel device isolation film130. For example, each pixel PX may be surrounded by the pixel device isolation film130. First to fourth active regions AC1, AC2, AC3, and AC4may be defined in one pixel PX by a device isolation film STI. The photoelectric conversion region PD, the transfer transistor TG, the first floating diffusion region FD1, the first source follower transistor SF1, the pre-charge transistor PC, the second source follower transistor SF2, and the first selection transistor SEL1may be in the first active region AC1. The reset transistor RG, the DCG transistor DCG, the second floating diffusion region FD2, and the calibration transistor CAL may be in the second active region AC2. The sample transistor SAM may be in the third active region AC3, and the second selection transistor SEL2may be in the fourth active region AC4.

The photoelectric conversion region PD may be in the first active region AC1and include, for example, an N-type impurity region. Electric charge may be generated from the photoelectric conversion region PD by, for example, absorbing light. The first floating diffusion region FD1may be adjacent to the photoelectric conversion region PD in the first active region AC1. A transfer gate electrode140of the transfer transistor TG may be adjacent to the first floating diffusion region FD1. The photoelectric conversion region PD may be coupled with the transfer transistor TG that transfers the accumulated charge to the first floating diffusion region FD1.

A DCG gate electrode151of the DCG transistor DCG and a reset gate electrode152of the reset transistor RG may be on the second active region AC2, and the second floating diffusion region FD2may be in the second active region AC2between the DCG gate electrode151and the reset gate electrode152. The second floating diffusion region FD2may be shared between the reset transistor RG and the DCG transistor DCG. The second floating diffusion region FD2may serve as sources or drains of the reset transistor RG and the DCG transistor DCG. The first and second floating diffusion regions FD1and FD2may be regions which convert charges into voltages, and charges may be accumulatively stored in the first and second floating diffusion regions FD1and FD2.

In an example embodiment of the present inventive concept, the DCG transistor DCG may be connected between the first floating diffusion region FD1and the reset transistor RG. The reset transistor RG may be connected to the first floating diffusion region FD1via the DCG transistor DCG. Alternatively, the reset transistor RG may be connected between the first floating diffusion region FD1and the DCG transistor DCG. The reset transistor RG and the DCG transistor DCG may be connected in series to the first floating diffusion region FD1. Alternatively, the DCG transistor DCG may be omitted.

The pre-charge transistor PC may be connected to the first source follower transistor SF1, and a pre-charge gate electrode153of the pre-charge transistor PC may be on the first active region AC1. The sample transistor SAM may be connected between the first source follower transistor SF1and the pre-charge transistor PC, and a sample gate electrode154of the sample transistor SAM may be on the third active region AC3. The calibration transistor CAL may be connected to a third electrode C22of the second capacitor C2, and a calibration gate electrode155of the calibration transistor CAL may be on the second active region AC2. For example, the second capacitor C2may be between the calibration transistor CAL and the first capacitor C1, and by increasing the capacitance of the second capacitor C2, the noise generated when calibration transistor CAL is turned off may be reduced.

The first selection transistor SEL1may be connected to a second source follower transistor SF2. A first selection gate electrode156of the first selection transistor SEL1and a first source follower gate electrode158of the first source follower transistor SF1may be connected to the first floating diffusion region FD1. A fourth electrode C24of the second capacitor C2may be connected to the sample transistor SAM and a second electrode C14of the first capacitor C1. The second source follower gate electrode159of the second source follower transistor SF2may be connected to the calibration transistor CAL and the third electrode C22of the second capacitor C2. The first selection gate electrode156of the first selection transistor SEL1, the first source follower gate electrode158of the first source follower transistor SF1, the transfer gate electrode140of the transfer transistor TG, and the second source follower gate electrode159of the second source follower transistor SF2may be on the first active region AC1.

One end of each of the reset transistor RG, the first source follower transistor SF1, the second source follower transistor SF2, and the calibration transistor CAL may be connected to a power source Vpix. One end of each of the first source follower transistor SF1and the second source follower transistor SF2may be connected to the first power source Vpix1, and one end of each of the reset transistor RG and the calibration transistor CAL may be connected to a second power source Vpix2. One end of the pre-charge transistor PC may be connected to a pre-charge voltage Vpc. In an example embodiment of the present inventive concept, the pre-charge voltage Vpc may be a ground voltage. A first electrode C12of the first capacitor C1may be connected to the second power source Vpix2. One end of the first selection transistor SEL1and one end of the second selection transistor SEL2may be connected to a power line Vout. The second selection gate electrode157of the second selection transistor SEL2may be on the fourth active region AC4.

One end of the sample transistor SAM may be connected to the second electrode C14of the first capacitor C1and the fourth electrode C24of the second capacitor C2to constitute the first node X. Another end of the sample transistor SAM may be connected to one end of the second selection transistor SEL2and another end of the first source follower transistor SF1. Another end of the calibration transistor CAL may be connected to the third electrode C22of the second capacitor C2and the second source follower gate electrode159of the second source follower transistor SF2to constitute the second node Y.

AlthoughFIG.2illustrates an example layout of the pixel PX, in another case, the second selection transistor SEL2may be omitted, and a first power source Vpix1may be applied to both one end of the calibration transistor CAL and one end of the second source follower transistor SF2.

As exemplarily shown inFIGS.3and4, the semiconductor substrate110may include a first surface110F1and a second surface110F2, which are opposite to each other. In an example embodiment of the present inventive concept, the semiconductor substrate110may include a P-type semiconductor substrate. For example, the semiconductor substrate110may include a P-type silicon (Si) substrate. In an example embodiment of the present inventive concept, the semiconductor substrate110may include a P-type bulk silicon (Si) substrate and a P-type or N-type epitaxial layer grown on the P-type bulk silicon (Si) substrate. In an example embodiment of the present inventive concept, the semiconductor substrate110may include an N-type bulk silicon (Si) substrate and a P-type or N-type epitaxial layer grown thereon. Alternatively, the semiconductor substrate110may include an organic plastic substrate.

A plurality of pixels PX may be arranged in a matrix form in the semiconductor substrate110. A plurality of photoelectric conversion regions PD may be respectively in the plurality of pixels PX. Each of the plurality of photoelectric conversion regions PD may include a photodiode region and a well region.

The pixel device isolation film130may be in the semiconductor substrate110, and the plurality of pixels PX may be defined by the pixel device isolation film130. For example, the pixel device isolation film130may be formed to surround each of the plurality of pixels PX. The pixel device isolation film130may be between one of the plurality of photoelectric conversion regions PD and the photoelectric conversion region PD adjacent thereto. One photoelectric conversion region PD may be physically and electrically isolated from another photoelectric conversion region PD adjacent thereto by the pixel device isolation film130. The pixel device isolation film130may be between the respective ones of the plurality of photoelectric conversion regions PD, which are arranged in a matrix form. The pixel device isolation film130may have a grid or mesh shape in a view from above.

The pixel device isolation film130may be formed inside a pixel trench130T, which passes through the semiconductor substrate110from the first surface110F1of the semiconductor substrate110to the second surface110F2thereof. The pixel device isolation film130may include an insulating layer132conformally formed on a sidewall of the pixel trench130T and a conductive layer134formed on the insulating layer132to fill the inside of the pixel trench130T. In an example embodiment of the present inventive concept, the insulating layer132may include a metal oxide such as, for example, hafnium oxide (HfO2), aluminum oxide (Al2O3), and/or tantalum oxide (Ta2O5). In this case, the insulating layer132may serve as a negative fixed charge layer, but the present inventive concept is not limited thereto. In an example embodiment of the present inventive concept, the insulating layer132may include an insulating material such as, for example, silicon oxide (SiO2), silicon nitride (Si3N4), and/or silicon oxynitride (SiON). The conductive layer134may include at least one of, for example, doped polysilicon (p-Si), a metal, a metal silicide, a metal nitride, or a metal-containing film.

In an example embodiment of the present inventive concept, an upper insulating film136may be in a portion of the pixel trench130T, which is adjacent to the first surface110F1of the semiconductor substrate110. In an example embodiment of the present inventive concept, the formation of the upper insulating film136may include etching back portions of the insulating layer132and the conductive layer134, which are at an entrance of the pixel trench130T, and filling the remaining space of the pixel trench130T with an insulating material. For example, the pixel device isolation film130may have a structure configured to refract incident light obliquely incident on the photoelectric conversion region PD. Also, the pixel device isolation film130may limit or prevent the migration of photocharges generated in one pixel during light exposure to the neighboring pixels to enhance the image quality.

FIG.4illustrates an example in which the pixel device isolation film130extends from the first surface110F1of the semiconductor substrate110to the second surface110F2thereof and passes through the semiconductor substrate110. In another case, however, the pixel device isolation film130may extend from the second surface110F2of the semiconductor substrate110into the semiconductor substrate110and may not be exposed at the first surface110F1of the semiconductor substrate110.

As exemplarily shown inFIG.4, the device isolation film STI defining the first to fourth active regions ACT1to ACT4may be formed in the semiconductor substrate110at the first surface110F1. The device isolation film STI may be in a device isolation trench (refer to110T inFIG.14), which is formed to have a predetermined depth from the first surface110F1of the semiconductor substrate110. For example, a depth at which the device isolation film STI is formed may be shallower than a depth at which the pixel device isolation film130is formed. The device isolation film STI may include an insulating material. The device isolation film STI may surround an upper sidewall of the pixel device isolation film130(e.g., a sidewall of the upper insulating film136).

Transistors constituting pixel circuits may be on the first to fourth active regions ACT1to ACT4. The sources, drains and channels of these transistors may be formed in the first to fourth active regions ACT1to ACT4of the semiconductor substrate110. For example, as exemplarily shown inFIG.2, the transfer gate electrode140, the DCG gate electrode151, the reset gate electrode152, the pre-charge gate electrode153, the sample gate electrode154, the calibration gate electrode155, the first and second selection gate electrodes156and157, and the first and second source follower gate electrodes158and159may be on the first surface110F1of the semiconductor substrate110. For example, the transistors constituting the pixel circuits may be disposed on the first surface110F1of the semiconductor substrate110.

The first floating diffusion region FD1may be in a portion of the first active region ACT1, for example, a portion of the first active region ACT1adjacent to the transfer gate electrode140.

As exemplarily shown inFIG.4, the transfer gate electrode140may be in a transfer gate trench140T, which extends from the first surface110F1of the semiconductor substrate110into the semiconductor substrate110. The DCG gate electrode151, the reset gate electrode152, the pre-charge gate electrode153, the sample gate electrode154, the calibration gate electrode155, the first and second selection gate electrodes156and157, and the first and second source follower gate electrodes158and159may be collectively referred to as a planar gate electrode150. The planar gate electrode150may be on the first surface110F1of the semiconductor substrate110. In an example embodiment of the present inventive concept, the transfer gate electrode140and the planar gate electrode150may include at least one of, for example, doped polysilicon (p-Si), a metal, a metal silicide, a metal nitride, or a metal-containing film.

A transfer gate insulating layer1401may be on an inner wall of the transfer gate trench140T to surround a sidewall and a bottom surface of the transfer gate electrode140. A transfer gate spacer140S may be on a sidewall of the transfer gate electrode140. A gate insulating layer1501may be between the planar gate electrode150and the first surface110F1of the semiconductor substrate110. A gate spacer150S may be on a sidewall of the planar gate electrode150.

A first interlayer insulating film160may be on the first surface110F1of the semiconductor substrate110to cover the transfer gate electrode140and the planar gate electrode150. For example, the first interlayer insulating film160may be formed to cover the transistors constituting the pixel circuits. The first interlayer insulating film160may have a stack structure including a lower insulating layer162and an upper insulating layer164sequentially stacked on the first surface110F1of the semiconductor substrate110. The lower insulating layer162may cover the transfer gate electrode140and the planar gate electrode150on the first surface110F1of the semiconductor substrate110, and the upper insulating layer164may be on the lower insulating layer162. A first wiring layer M1may be on the lower insulating layer162, and the upper insulating layer164may cover the first wiring layer M1. In an example embodiment of the present inventive concept, an etch stop layer may be formed between the lower insulating layer162and the first surface110F1of the semiconductor substrate110. The etch stop layer may include a material having an etch selectivity with respect to that of the lower insulating layer162.

The first capacitor C1and the second capacitor C2may be on the first interlayer insulating film160. An upper pad electrode CUP may be shared by both the first capacitor C1and the second capacitor C2.

As exemplarily shown inFIGS.3and4, a first lower pad electrode LP1and a second lower pad electrode LP2may be spaced apart from each other on the first interlayer insulating film160. The first lower pad electrode LP1and the second lower pad electrode LP2may be in parallel with the first surface110F1of the semiconductor substrate110in a central region of the pixel PX. For example, the first lower pad electrode LP1and the second lower pad electrode LP2may be formed at the same vertical level. The first and second lower pad electrodes LP1and LP2may occupy at least 50% of an area of the pixel PX (seeFIG.3). A mold insulating layer170may be formed on the first interlayer insulating film160to cover the first lower pad electrode LP1and the second lower pad electrode LP2. The mold insulating layer170may include at least one of, for example, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON).

A plurality of first lower electrodes LE1may be respectively inside a plurality of first openings170H1(seeFIGS.7and17), which pass through the mold insulating layer170and expose a top surface of the first lower pad electrode LP1. A plurality of second lower electrodes LE2may be respectively inside a plurality of second openings170H2(seeFIGS.7and17), which pass through the mold insulating layer170and expose a top surface of the second lower pad electrode LP2. As shown inFIG.3, the first and second lower electrodes LE1and LE2may be arranged in a zigzag form along a first direction parallel to a top surface of the semiconductor substrate110and a second direction parallel to the top surface of the semiconductor substrate110. The second direction may be perpendicular to the first direction. However, the present inventive concept is not limited thereto. Each of the first lower electrode LE1and the second lower electrode LE2may have a cylindrical shape.

A dielectric film DL and an upper electrode CUE may be sequentially formed on the first lower electrode LE1and the second lower electrode LE2. The dielectric film DL may be conformally formed on top surfaces and inner walls of the first lower electrode LE1and the second lower electrode LE2, which have cylindrical shapes. The upper electrode CUE may be formed on the dielectric film DL to fill the remaining space of the plurality of first openings170H1and the plurality of second openings170H2. The first and second lower electrodes LE1and LE2and the upper electrode CUE may each include a film including a metal having a high melting point, such as, for example, cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W) or molybdenum (Mo), and/or a metal nitride film, such as, for example, a titanium nitride film (TiN), a titanium silicon nitride film (TiSiN), a titanium aluminum nitride film (TiAlN), a tantalum nitride film (TaN), a tantalum silicon nitride film (TaSiN), a tantalum aluminum nitride film (TaAlN), or a tungsten nitride film (WN). The dielectric film DL may include one or a combination of single films selected from combinations of a metal oxide, such as, for example, hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), or titanium oxide (TiO2), and a dielectric material having a perovskite structure, such as, for example, strontium titanium oxide (SrTiO3, STO), barium strontium titanium oxide ((Ba,Sr)TiO3, BST), barium titanium oxide (BaTiO3), lead zirconate titanate (Pb(Ti,Zr)O3, PZT), or lead lanthanum zirconium titanate ((Pb,La)(Zr,Ti)O3, PLZT).

An upper pad electrode CUP may be on the mold insulating layer170to cover an upper portion of the upper electrode CUE. The upper pad electrode CUP may vertically overlap the first and second lower pad electrodes LP1and LP2. The upper pad electrode CUP may include a conductive material different from that of the upper electrode CUE, or may include a doped semiconductor material. The upper pad electrode CUP may include, for example, doped polysilicon (p-Si), silicon germanium (SiGe), and/or a metal, such as, for example, tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), or tantalum (Ta).

A second wiring layer M2may be spaced apart from the first and second lower pad electrodes LP1and LP2on the upper insulating layer164(seeFIGS.3and6). For example, the second wiring layer M2, the first lower pad electrode LP1and the second lower pad electrode LP2may be formed at the same vertical level. For example, the second wiring layer M2may surround the first and second lower pad electrodes LP1and LP2in a view from above. Because the second wiring layer M2is on an edge of the pixel PX to surround the first and second lower pad electrodes LP1and LP2, the second wiring layer M2may be referred to as an edge wiring layer.

The first capacitor C1may include the first lower pad electrode LP1, the plurality of first lower electrodes LE1, the dielectric film DL, the upper electrode CUE, and the upper pad electrode CUP. The first lower pad electrode LP1and the plurality of first lower electrodes LE1may correspond to the first electrode C12, and the upper electrode CUE and the upper pad electrode CUP may correspond to the second electrode C14. The second capacitor C2may include the second lower pad electrode LP2, the plurality of second lower electrodes LE2, the dielectric film DL, the upper electrode CUE, and the upper pad electrode CUP. The second lower pad electrode LP2and the plurality of second lower electrodes LE2may correspond to the third electrode C22, and the upper electrode CUE and the upper pad electrode CUP may correspond to the fourth electrode C24. For example, the upper electrode CUE and the upper pad electrode CUP may be shared by both the second electrode C14of the first capacitor C1and the fourth electrode C24of the second capacitor C2. Because the first capacitor C1and the second capacitor C2respectively include the first and second lower electrodes LE1and LE2having cylindrical shapes, the capacitances of the first and second capacitors C1and C2may be increased, and the loss of charges and the generation of noise may be reduced during a global shutter operation, thereby enhancing shutter efficiency.

A second interlayer insulating film172may be on the mold insulating layer170, and may have a stack structure including first to fourth insulating layers172A,172B,172C, and172D sequentially stacked on the mold insulating layer170. For example, the first insulating layer172A may be on the mold insulating layer170to cover the upper pad electrode CUP. A third wiring layer M3may be on the first insulating layer172A, and the second insulating layer172B may be on the first insulating layer172A to cover the third wiring layer M3. A fourth wiring layer M4may be on the second insulating layer172B, and the third insulating layer172C may be on the second insulating layer172B to cover the fourth wiring layer M4. A fifth wiring layer M5may be on the third insulating layer172C, and the fourth insulating layer172D may be on the third insulating layer172C to cover the fifth wiring layer M5.

The first to fifth wiring layers M1, M2, M3, M4, and M5may include at least one of, for example, doped or undoped polysilicon (p-Si), a metal, a metal silicide, a metal nitride, or a metal-containing film. For example, the first to fifth wiring layers M1, M2, M3, M4, and M5may each include, for example, tungsten (W), aluminum (Al), copper (Cu), tungsten silicide (WSi2), titanium silicide (TiSi2), tungsten nitride (WN), titanium nitride (TiN), and/or doped polysilicon (p-Si). The first to fourth insulating layers172A,172B,172C, and172D may each include an insulating material, such as, for example, silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON).

A first lower contact plug LCP1may pass through the lower insulating layer162of the first interlayer insulating film160and be connected to the first wiring layer M1. The first lower contact plug LCP1may be electrically connected to the first wiring layer M1and an impurity region (a source/drain region) of a transistor located within one of the first to fourth active regions AC1to AC4. A second lower contact plug LCP2(seeFIG.6) may pass through the upper insulating layer164of the first interlayer insulating film160and be connected to the second wiring layer M2and the first wiring layer M1. A first upper contact plug UCP1may be on the upper pad electrode CUP to pass through the first insulating layer172A, and the first upper contact plug UCP1may be electrically connected to the third wiring layer M3and the upper pad electrode CUP. In addition, a second upper contact plug UCP2may pass through the second insulating layer172B and connect the third wiring layer M3to the fourth wiring layer M4. A third upper contact plug UCP3may pass through the third insulating layer172C and connect the fourth wiring layer M4to the fifth wiring layer M5. A third contact plug CP3(seeFIG.6) may pass through the mold insulating layer170and the first insulating layer172A and electrically connect the second wiring layer M2(or the edge wiring layer) to the third wiring layer M3.

As exemplarily shown inFIG.3, the first lower pad electrode LP1may include a main pad portion MP1and an extension EX1protruding from the main pad portion MP1. The main pad portion MP1may have a rectangular horizontal cross-section. The second lower pad electrode LP2may include a main pad portion MP2and an extension EX2protruding from the main pad portion MP2. The main pad portion MP2may have a rectangular horizontal cross-section.

In an example embodiment of the present inventive concept, a first contact plug CP1may be on a top surface of the extension EX1of the first lower pad electrode LP1(seeFIGS.3and5). The first contact plug CP1may pass through the mold insulating layer170and the second interlayer insulating film172(e.g., the first insulating layer172A of the second interlayer insulating film172) and be connected to the third wiring layer M3. The first contact plug CP1may be electrically connected to the third wiring layer M3and the first lower pad electrode LP1. A bottom surface of the first lower pad electrode LP1may be entirely covered by the first interlayer insulating film160. For example, the bottom surface of the first lower pad electrode LP1may be entirely in contact with the first interlayer insulating film160.

A second contact plug CP2may be on a top surface of the extension EX2of the second lower pad electrode LP2(seeFIGS.3and6). The second contact plug CP2may pass through the mold insulating layer170and the second interlayer insulating film172(e.g., the first insulating layer172A of the second interlayer insulating film172) and be connected to the third wiring layer M3. The second contact plug CP2may be electrically connected to the third wiring layer M3and the second lower pad electrode LP2. A bottom surface of the second lower pad electrode LP2may be entirely covered by the first interlayer insulating film160. For example, the bottom surface of the second lower pad electrode LP2may be entirely in contact with the first interlayer insulating film160. For example, the first wiring layer M1may be located at a vertical level lower than that of the first and second lower pad electrodes LP1and LP2, and the third wiring layer M3may be located at a vertical level higher than that of the first and second lower pad electrodes LP1and LP2. The second lower pad electrode LP2is not directly connected to the first wiring layer M1through the second contact plug CP2or any other contact plug, and the second lower pad electrode LP2is connected to the third wiring layer M3through the second contact plug CP2.

As shown inFIG.6, the second lower pad electrode LP2may be connected to the third wiring layer M3through the second contact plug CP2located on the top surface of the extension EX2and be connected to an impurity region N+ of the calibration transistor CAL through the third contact plug CP3connected to the third wiring layer M3, the second wiring layer M2, the second lower contact plug LCP2, the first wiring layer M1, and the first lower contact plug LCP1. That is, as shown inFIG.6, the second lower pad electrode LP2may be connected to the impurity region N+ of the calibration transistor CAL along a bypass electrical path C2_DP.

Since the second lower pad electrode LP2may be electrically connected to the impurity region N+ of the calibration transistor CAL along the bypass electrical path C2_DP, which is formed by the second contact plug CP2, the third wiring layer M3, the third contact plug CP3, the second wiring layer M2, the second lower contact plug LCP2, the first wiring layer M1, and the first lower contact plug LCP1, damage may be prevented from being built up in the semiconductor substrate110due to plasma used in a process of forming the first capacitor C1and the second capacitor C2. Because the second contact plug CP2is formed after the process of forming the first capacitor C1and the second capacitor C2, the first capacitor C1and the second capacitor C2may not be electrically connected to the impurity region N+ of the calibration transistor CAL during the process of forming the first capacitor C1and the second capacitor C2.

As shown inFIG.4, a rear insulating layer182may be formed on the second surface110F2of the semiconductor substrate110. For example, the rear insulating layer182may be on substantially the entire area of the second surface110F2of the semiconductor substrate110. The rear insulating layer182may be in contact with a top surface of the pixel device isolation film130at a level the same as that of the second surface110F2of the semiconductor substrate110. In an example embodiment of the present inventive concept, the rear insulating layer182may include a metal oxide, such as, for example, hafnium oxide (HfO2), aluminum oxide (Al2O3), and/or tantalum oxide (Ta2O5). In an example embodiment of the present inventive concept, the rear insulating layer182may include an insulating material, such as, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), and/or a low-k dielectric material.

A passivation layer184may be on the rear insulating layer182, and a color filter186and a microlens188may be on the passivation layer184. Light may be incident on the second surface110F2of the semiconductor substrate110through the microlens188, the color filter186, the passivation layer184and the rear insulating layer182. Optionally, a support substrate may be further located on the first surface110F1of the semiconductor substrate110.

According to the above-described example embodiments of the present inventive concept, the image sensor100may be a global-shutter-type image sensor having an increased capacitance, and shutter efficiency may be increased during a global shutter operation. For example, the capacitances of the first and second capacitors C1and C2may be increased when the first capacitor C1and the second capacitor C2respectively include the first and second lower electrodes LE1and LE2having cylindrical shapes. In addition, because the second lower pad electrode LP2is connected to a storage node (e.g., the impurity region N+ of the calibration transistor CAL) along the bypass electrical path C2_DP, plasma damage may be prevented from being built up in the storage node of the semiconductor substrate110during the process of forming the first and second capacitors C1and C2. For example, the bypass electrical path C2_DP may be formed after the process of forming the first and second capacitors C1and C2. Accordingly, white spots may be prevented from occurring due to a junction leakage current, and thus, the image sensor100may be prevented from causing noise.

FIG.9is a cross-sectional view of an image sensor100A according to an example embodiment of the present inventive concept. InFIG.9, the same reference numerals are used to denote the same elements as inFIGS.1to8.

Referring toFIG.9, a second lower pad electrode LP2may be connected to one of third wiring layers M3through a second contact plug CP2located on a top surface of an extension EX2, and may be electrically connected to an impurity region N+ of a calibration transistor CAL through a second upper contact plug UCP2connected to the third wiring layer M3, a fourth wiring layer M4connected to the second upper contact plug UCP2, an other second upper contact plug UCP2connected to the fourth wiring layer M4, an other third wiring layer M3connected to the other second upper contact plug UCP2, a third contact plug CP3connected to the other third wiring layer M3, a second wiring layer M2(or an edge wiring layer) connected to the third contact plug CP3, a second lower contact plug LCP2connected to the second wiring layer M2, and a first wiring layer M1and a first lower contact plug LCP1, which are connected to the second lower contact plug LCP2. That is, as shown inFIG.9, the second lower pad electrode LP2may be connected to the impurity region N+ of the calibration transistor CAL along a bypass electrical path C2_DP. The bypass electrical path C2_DP ofFIG.9adds two second upper contact plugs UCP2and the fourth wiring layer M4to connect two separated third wiring layers in the path in comparison to the bypass electrical path C2_DP ofFIG.6.

Since the second lower pad electrode LP2may be connected to the impurity region N+ of the calibration transistor CAL along the bypass electrical path C2_DP, which is formed by the second contact plug CP2, the third wiring layer M3, the second upper contact plug UCP2, the fourth wiring layer M4, the third contact plug CP3, the second wiring layer M2, the second lower contact plug LCP2, the first wiring layer M1, and the first lower contact plug LCP1, damage may be prevented from being built up in a semiconductor substrate110due to plasma used in a process of forming a first capacitor C1and a second capacitor C2. For example, the bypass electrical path C2_DP ofFIG.9may be formed after the process of forming the first and second capacitors C1and C2. Accordingly, plasma damage may be prevented from being built up in the semiconductor substrate110, especially, in an impurity region N+ of a calibration transistor CAL during the process of forming the first capacitor C1and the second capacitor C2.

FIG.10is a diagram illustrating the layout of an image sensor100B according to an example embodiment of the present inventive concept. InFIG.10, the same reference numerals are used to denote the same elements as inFIGS.1to9.

Referring toFIG.10, a first lower pad electrode LP1may include a main pad portion MP1having a rectangular shape with a long side and a short side and an extension EX1that protrudes outward from the short side of the main pad portion MP1. A second lower pad electrode LP2may include a main pad portion MP2having a rectangular shape with a long side and a short side and an extension EX2that protrudes outward from the short side of the main pad portion MP2. For example, the extension EX1of the first lower pad electrode LP1and the extension EX2of the second lower pad electrode LP2may be at positions vertically overlapping a pixel device isolation film130. The second lower pad electrode LP2described here with reference toFIG.10is different from the second lower pad electrode LP2illustrated inFIG.3. InFIG.3, the extension EX2of the second lower pad electrode LP2protrudes outward from the long side of the main pad portion MP2.

FIG.10illustrates an example in which the extension EX1of the first lower pad electrode LP1and the extension EX2of the second lower pad electrode LP2, which are included in one pixel PX, protrude in the same direction. In another case, however, the extension EX1of the first lower pad electrode LP1may protrude in an upward direction ofFIG.10, and the extension EX2of the second lower pad electrode LP2may protrude in a downward direction ofFIG.10.

FIG.11is a cross-sectional view of an image sensor100C according to an example embodiment of the present inventive concept, andFIG.12is an enlarged view of region CX2ofFIG.11. InFIGS.11and12, the same reference numerals are used to denote the same elements as inFIGS.1to10.

Referring toFIGS.11and12, the first capacitor C1may include a first lower pad electrode LP1, a plurality of first lower electrodes LE1, a first dielectric film DL1, a first upper electrode UE1, and a first upper pad electrode UP1, and the second capacitor C2may include a second lower pad electrode LP2, a plurality of second lower electrodes LE2, a second dielectric film DL2, a second upper electrode UE2, and a second upper pad electrode UP2.

Each of the plurality of first lower electrodes LE1may have a pillar shape and extend in a vertical direction, and the first dielectric film DL1may conformally cover a top surface and a sidewall of each of the plurality of first lower electrodes LE1. The first upper electrode UE1may cover all of the plurality of first lower electrodes LE1on the first dielectric film DL1. The first upper pad electrode UP1may be in a flat plate shape on a top surface of the first upper electrode UE1. The first upper electrode UE1and the first upper pad electrode UP1may correspond to the second electrode C14of the first capacitor C1.

Each of the plurality of second lower electrodes LE2may have a pillar shape and extend in the vertical direction, and the second dielectric film DL2may conformally cover a top surface and a sidewall of each of the second lower electrodes LE2. The second upper electrode UE2may cover all of the plurality of second lower electrodes LE2on the second dielectric film DL2. The second upper pad electrode UP2may be in a flat plate shape on a top surface of the second upper electrode UE2. The second upper electrode UE2and the second upper pad electrode UP2may correspond to the fourth electrode C24of the second capacitor C2. Although the first upper pad electrode UP1and the second upper pad electrode UP2are spaced apart from each other, the first upper pad electrode UP1and the second upper pad electrode UP2may be connected to the same node (e.g., the first node X shown inFIG.8) each by a first upper contact plug UCP1. For example, the second electrode C14of the first capacitor C1and the fourth electrode C24of the second capacitor C2may be connected to the same node (e.g., the first node X shown inFIG.8).

A mold insulating layer (refer to170inFIG.4) may be omitted from the image sensor100C shown inFIGS.11and12. The first capacitor C1and the second capacitor C2may be covered by a first insulating layer172A of a second interlayer insulating film172. A first contact plug (refer to CP1inFIG.5) and a second contact plug CP2may pass through the first insulating layer172A.

FIG.13is a schematic view of an image sensor200according to an example embodiment of the present inventive concept.

Referring toFIG.13, the image sensor200may be a stack-type image sensor including a first chip CHIP1and a second chip CHIP2, in which the first chip CHIP1may be stacked on the second chip CHIP2in a vertical direction. The first chip CHIP1may include an active pixel region APR and a first pad region PDR1, and the second chip CHIP2may include a peripheral circuit region PCR and a second pad region PDR2.

A plurality of first pads PAD1of the first pad region PDR1may transmit and receive electric signals to and from an external device. The peripheral circuit region PCR may include a logic circuit block LC and a plurality of CMOS transistors. The peripheral circuit region PCR may provide a constant signal to each active pixel PX of the active pixel region APR or control an output signal of each active pixel PX. The first pads PAD1of the first pad region PDR1may be electrically connected to second pads PAD2of the second pad region PDR2by a via structure VS.

FIGS.14to22are cross-sectional views of a method of manufacturing an image sensor100, according to an example embodiment of the present inventive concept. InFIGS.14to22, the same reference numerals are used to denote the same elements as inFIGS.1to13.

Referring toFIG.14, a semiconductor substrate110including a first surface110F1and a second surface110F2, which are opposite each other, may be prepared. A photoelectric conversion region PD may be formed by performing an ion implantation process on the first surface110F1of the semiconductor substrate110. Thus, the photoelectric conversion region PD may be formed in the semiconductor substrate110. For example, a photoelectric conversion region PD may include a photodiode region and a well region. The photodiode region may be doped with N-type impurities, and the well region may be doped with P-type impurities.

Next, a first mask pattern may be formed on the first surface110F1of the semiconductor substrate110, and a device isolation trench110T may be formed in the semiconductor substrate110by using the first mask pattern as an etch mask. For example, the device isolation trench110T may be formed by removing a portion of the semiconductor substrate110through an etching process.

Subsequently, the device isolation trench110T may be filled with an insulating material, and thus, a device isolation film STI may be formed inside the device isolation trench110T. The device isolation film STI may be formed to cover the first mask pattern.

Thereafter, a second mask pattern may be formed on the first surface110F1of the semiconductor substrate110, and pixel trenches130T may be formed in the semiconductor substrate110by using the second mask pattern as an etch mask. The pixel trenches130T may have a predetermined depth from the first surface110F1of the semiconductor substrate110and be arranged in a matrix form in a view from above. For example, a depth of the pixel trenches130T may be larger than a depth of the device isolation trench110T.

An insulating layer132may be then conformally formed on the first surface110F1of the semiconductor substrate110and an inner wall of the pixel trench130T by using a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. Thereafter, a conductive layer134may be formed on the insulating layer132to fill an inner wall of the pixel trench130T.

A portion of the insulating layer132and a portion of the conductive layer134may be removed so that the first surface110F1of the semiconductor substrate110may be exposed. Afterwards, a portion of the insulating layer132and a portion of the conductive layer134, which are in an upper portion of the pixel trench130T, may be further removed using an etchback process, and a vacant space of the pixel trench130T may be filled with an insulating material, and thus, an upper insulating film136may be formed on the insulating layer132and the conductive layer134in the upper portion of the pixel trench130T.

Referring toFIG.15, a mask pattern may be formed on the first surface110F1of the semiconductor substrate110, and a portion of the semiconductor substrate110may be removed using the mask pattern as an etch mask, thereby forming a transfer gate trench140T.

A transfer gate electrode140and a planar gate electrode150may be formed on the first surface110F1of the semiconductor substrate110and an inner wall of the transfer gate trench140T. In an example embodiment of the present inventive concept, before the transfer gate electrode140and the planar gate electrode150are formed, a transfer gate insulating layer1401may be formed on the inner wall of the transfer gate trench140T and a gate insulating layer1501may be formed on the first surface110F1under the planar gate electrode150. Next, a transfer gate spacer140S and a gate spacer150S may be further respectively formed on a sidewall of the transfer gate electrode140and a sidewall of the planar gate electrode150.

Afterwards, an ion implantation process may be performed on a partial region of the first surface110F1of the semiconductor substrate110, thereby forming an impurity region in the semiconductor substrate110.

Referring toFIG.16, a lower insulating layer162may be formed on the first surface110F1of the semiconductor substrate110, and a first lower contact hole LCPH may be formed to pass through the lower insulating layer162. Afterwards, the first lower contact hole LCPH may be filled with a conductive material to form a first lower contact plug LCP1. A first wiring layer M1may be formed on the lower insulating layer162, and an upper insulating layer164may be formed on the lower insulating layer162to cover the first wiring layer M1. Thereafter, a second lower contact hole may be formed to pass through the upper insulating layer164. The second lower contact hole may be filled with a conductive material to form a second lower contact plug (refer to LCP2inFIG.6).

Subsequently, a conductive layer may be formed on the upper insulating layer164and patterned to form a first lower pad electrode LP1, a second lower pad electrode LP2, and a second wiring layer M2(seeFIG.6). The first lower pad electrode LP1, the second lower pad electrode LP2, and the second wiring layer M2may be formed using the same material. For example, the second wiring layer M2(or an edge wiring layer) may be disposed on the second lower contact plug (refer to LCP2inFIG.6) and located at a vertical level the same as that of the first and second lower pad electrodes LP1and LP2. The second lower pad electrode LP2may not be in direct contact with the second lower contact plug (refer to LCP2inFIG.6). As shown inFIG.3, in a view from above, the first lower pad electrode LP1may include a main pad portion MP1and an extension EX1, and the second lower pad electrode LP2may include a main pad portion MP2and an extension EX2.

Referring toFIG.17, a mold insulating layer170may be formed on the first interlayer insulating film160. Next, a mask pattern may be formed on the mold insulating layer170, and a plurality of first openings170H1and a plurality of second openings170H2may be formed in the mold insulating layer170using the mask pattern as an etch mask. The first lower pad electrode LP1may be exposed at bottom portions of the plurality of first openings170H1, and the second lower pad electrode LP2may be exposed at bottom portions of the plurality of second openings170H2.

Referring toFIG.18, a preliminary lower electrode layer may be formed on the mold insulating layer170to conformally cover inner walls of the plurality of first openings170H1and inner walls of the plurality of second openings170H2. Portions of the preliminary lower electrode layer covering a top surface of the mold insulating layer170may be removed, and thus, a plurality of first lower electrodes LE1may be formed on the inner walls of the plurality of first openings170H1and a plurality of second lower electrodes LE2may be formed on the inner walls of the plurality of second openings170H2. Each of the first lower electrode LE1and the second lower electrode LE2may have a cylindrical shape.

A dielectric film DL and an upper electrode CUE may be formed on the mold insulating layer170to conformally cover the inner walls of the plurality of first openings170H1and the inner walls of the plurality of second openings170H2. A first capacitor C1and a second capacitor C2may be formed by forming an upper pad electrode CUP on the upper electrode CUE. Since the first capacitor C1and the second capacitor C2respectively include the first and second lower electrodes LE1and LE2having cylindrical shapes, the capacitances of the first and second capacitors C1and C2may be increased. For example, the upper pad electrode CUP may include a semiconductor material (e.g., silicon germanium (SiGe)) doped with impurities. A process of implanting impurity ions into the upper pad electrode CUP may be performed during the process of forming the upper pad electrode CUP.

In an example embodiment of the present inventive concept, a plasma-related process may be used in the process of forming the first capacitor C1and the second capacitor C2. For example, a plasma-based etching process may be used in a process of etching the mold insulating layer170. Even when the plasma-based etching process is performed, because the first and second lower pad electrodes LP1and LP2remain electrically insulated from the semiconductor substrate110, plasma damage may be prevented from being built up in the semiconductor substrate110, especially, in an impurity region N+(refer toFIG.6) of a calibration transistor CAL. For example, the first and second lower pad electrodes LP1and LP2may not be electrically connected to a storage node (or the impurity region N+ of a calibration transistor CAL) during the process of forming the first capacitor C1and the second capacitor C2. Accordingly, plasma damage may be prevented from being built up in the storage node (or the impurity region N+ of the calibration transistor CAL).

Referring toFIG.19, a first insulating layer172A may be formed on the mold insulating layer170and the upper pad electrode CUP. Subsequently, an upper contact hole UCPH passing through the first insulating layer172A and a contact hole CPH passing through the first insulating layer172A and the mold insulating layer170may be formed. For example, the contact hole CPH may expose a top surface of the second lower pad electrode LP2, a top surface of the first lower pad electrode LP1, and a top surface of a second wiring layer (refer to M2inFIG.6).

Referring toFIG.20, the upper contact hole UCPH and the contact hole CPH may be filled with a conductive layer, and an upper portion of the conductive layer may be planarized so that a top surface of the first insulating layer172A may be exposed. Thus, a first upper contact plug UCP1may be formed in the upper contact hole UCPH and first to third contact plugs CP1, CP2, and CP3(seeFIGS.5and6) may be formed in the contact holes CPH.

Referring toFIG.21, a process of forming a conductive layer on the first insulating layer172A, a process of patterning the conductive layer, and a process of forming an insulating layer to cover the patterned conductive layer may be repeatedly performed, thereby forming a second interlayer insulating film172, which includes the first to fourth insulating layers172A,172B,172C, and172D, and third to fifth wiring layers M3, M4, and M5. For example, the third wiring layer M3may be formed on the first insulating layer172A and covered by the second insulating layer172B, the fourth wiring layer M4may be formed on the second insulating layer172B and covered by the third insulating layer172C, and the fifth wiring layer M5may be formed on the third insulating layer172C and covered by the fourth insulating layer172D. A first upper contact plug UCP1may be formed on the upper pad electrode CUP to pass through the first insulating layer172A to electrically connect the upper pad electrode CUP and the third wiring layer M3. A second upper contact plug UCP2may pass through the second insulating layer172B and connect the third wiring layer M3to the fourth wiring layer M4. A third upper contact plug UCP3may pass through the third insulating layer172C and connect the fourth wiring layer M4to the fifth wiring layer M5.

Referring toFIG.22, a support substrate may be adhered to a first surface110F1of the semiconductor substrate110including the above described capacitor structures and wiring layers, and the semiconductor substrate110may be reversed so that a second surface110F2of the semiconductor substrate110may face upward.

Subsequently, a planarization process, such as a chemical mechanical polishing (CMP) process or an etchback process, may be performed so that a top surface of a pixel device isolation film130(e.g., an end portion of the pixel device isolation film130adjacent to the second surface110F2of the semiconductor substrate110) may be exposed, and thus, a portion of the semiconductor substrate110may be removed from the second surface110F2of the semiconductor substrate110.

Afterwards, a rear insulating layer182may be formed on the second surface110F2of the semiconductor substrate110. The rear insulating layer182may be formed over the entire area of the second surface110F2of the semiconductor substrate110to cover the pixel device isolation layer130.

Subsequently, a passivation layer184may be formed on the rear insulating layer182, and a color filter186and a microlens188may be formed on the passivation layer184.

The manufacture of the image sensor100may be completed due to the above-described processes.

According to an example embodiment of the present inventive concept, even when a plasma-related process is used in a process of forming the first capacitor C1and the second capacitor C2, because the first and second lower pad electrodes LP1and LP2remain electrically insulated from the semiconductor substrate110, plasma damage may not be built up in the semiconductor substrate110, especially, in the impurity region N+ of the calibration transistor CAL. Accordingly, white spots may be prevented from occurring due to a junction leakage current, and thus, the image sensor100may be prevented from causing noise.

FIG.23is a block diagram of a configuration of an image sensor1100according to an example embodiment of the present inventive concept.

Referring toFIG.23, the image sensor1100may include a pixel array1110, a controller1130, a row driver1120, and a pixel signal processor1140. The image sensor1100may include at least one of the image sensors100,100A,100B,100C, or200described above with reference toFIGS.1to13.

The pixel array1110may include a plurality of unit pixels arranged two-dimensionally, and each of the unit pixels may include a photoelectric conversion element. The photoelectric conversion element may absorb light, generate charges, and provide an electric signal (or an output voltage) corresponding to the generated charges to the pixel signal processor1140through a vertical signal line. The unit pixels included in the pixel array1110may provide one output voltage at a time in units of rows. Thus, unit pixels in one row of the pixel array1110may be simultaneously activated in response to a selection signal output by the row driver1120. For example, the unit pixels included in the pixel array1110may be driven by a plurality of drive signals such as, for example, selection signals, reset signals, and charge transfer signals from the row driver1120. Unit pixels in a selected row may provide an output voltage corresponding to absorbed light to an output line of a column corresponding thereto.

The controller1130may control the row driver1120such that the pixel array1110absorbs light to accumulate charges or temporarily stores the accumulated charges and outputs an electric signal corresponding to the stored charges to the outside of the pixel array1110. In addition, the controller1130may control the pixel signal processor1140to measure the output voltage provided by the pixel array1110.

The pixel signal processor1140may include a correlated double sampler (CDS)1142, an analog-to-digital converter (ADC)1144, and a buffer1146. The output voltage converted from an optical signal (absorbed light) by the unit pixels included in the pixel array1110may be provided to the CDS1142. The CDS1142may sample and hold the output voltage provided by the pixel array1110. The CDS1142may double sample a specific noise level and a level corresponding to the generated output voltage and output a difference level corresponding to a difference between the noise level and the level corresponding to the generated output voltage. Furthermore, the CDS1142may receive ramp signals generated by a ramp signal generator1148, compare the ramp signals, and output a comparison result.

The ADC1144may convert an analog signal corresponding to a level received from the CDS1142into a digital signal. The buffer1146may latch the digital signal, and latched signals may be sequentially output to the outside of the image sensor1100and transmitted to an image processor.

While the present inventive concept has been particularly shown and described with reference to the example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the present inventive concept as defined by the appended claims.