Patent ID: 12237394

DETAILED DESCRIPTION

Referring toFIGS.1-5,FIGS.1-5illustrate a method for fabricating semiconductor device according to an embodiment of the present invention. As shown inFIG.1, a substrate12such as a silicon substrate or silicon-on-insulator (SOI) substrate is provided, a first region such as a PMOS region14and a second region such as a NMOS region16are defined on the substrate12, and a shallow trench isolation (STI)18is formed in the substrate12to divide the PMOS region14and the NMOS region16. Next, at least a gate structure20is formed on the substrate12and extending across the PMOS region14and the NMOS region16. In this embodiment, the formation of the gate structure20could be accomplished by sequentially forming a gate dielectric layer, a gate material layer, and a selective hard mask on the substrate12, conducting a pattern transfer process by using a patterned resist (not shown) as mask to remove part of the hard mask, part of the gate material layer, and part of the gate dielectric layer through single or multiple etching processes, and then stripping the patterned resist. This forms a gate structure20composed of a patterned gate dielectric layer22, a patterned gate material layer24, and a patterned hard mask (not shown) on the substrate12.

It should be noted that even though the present embodiment pertains to a planar MOS transistor, according to another embodiment of the present invention, the present invention could also be applied to a non-planar MOS transistor such as fin field effect transistor (FinFET) devices, which is also within the scope of the present invention.

Next, at least a spacer26is formed on sidewalls of the gate structure20, source/drain regions28,30and/or epitaxial layer (not shown) are formed in the substrate12adjacent to two sides of the spacer26on the PMOS region14and NMOS region16respectively, and a selective silicide layer (not shown) could be formed on the surface of the source/drain regions28,30. In this embodiment, the spacer26could be a single spacer or a composite spacer, such as a spacer including but not limited to for example an offset spacer and a main spacer. Preferably, the offset spacer and the main spacer could include same material or different material while both the offset spacer and the main spacer could be made of material including but not limited to for example SiO2, SiN, SiON, SiCN, or combination thereof. The source/drain regions28,30could include dopants and epitaxial material of different conductive type depending on the type of device being fabricated. For example, the source/drain region28on the PMOS region14could include p-type dopants and/or silicon germanium (SiGe) while the source/drain region30on the NMOS region16could include n-type dopants, SiC, and/or SiP, but not limited thereto.

Next, referring toFIGS.2-5,FIGS.2-5illustrate follow-up fabrication processes taken along the longer axis of gate structure20or along the sectional line AA′ shown inFIG.1. As shown inFIG.2, a contact etch stop layer (CESL)32is formed on the surface of the substrate12and the gate structure20and an interlayer dielectric (ILD) layer34is formed on the CESL32thereafter. Next, a planarizing process such as chemical mechanical polishing (CMP) process is conducted to remove part of the ILD layer34and part of the CESL32to expose the gate material layer24made of polysilicon and the top surface of the gate material24is even with the top surface of the ILD layer34.

Next, a replacement metal gate (RMG) process is conducted to transform the gate structure20into metal gate. For instance, the RMG process could be accomplished by first performing a selective dry etching or wet etching process using etchants including but not limited to for example ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer24and even gate dielectric layer22of the gate structure20for forming a recess36in the ILD layer34on both PMOS region14and NMOS region16at the same time. Next, a selective interfacial layer38or gate dielectric layer, a high-k dielectric layer40, a bottom barrier metal (BBM) layer42, another BBM layer44, and a work function metal layer46are formed in the recess36.

In this embodiment, the high-k dielectric layer40is preferably selected from dielectric materials having dielectric constant (k value) larger than 4. For instance, the high-k dielectric layer40may be selected from hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalate (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT), barium strontium titanate (BaxSr1-xTiO3, BST) or a combination thereof.

Preferably, the BBM layer42and the BBM layer44could be made of same material or different material depending on the demand of the product while both layers42,44could all be selected from the group consisting of Ti, TiN, Ta, and TaN. The work function metal layer46at this stage is preferably a p-type work function metal layer having a work function ranging between 4.8 eV and 5.2 eV, which may include but not limited to for example titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC).

Next, as shown inFIG.3, a patterned mask such as a patterned resist48is formed to cover the PMOS region14, and an etching process is conducted by using the patterned resist48as mask to remove the work function metal layer46and part of the BBM layer44on the NMOS region16. It should be noted that the etching process conducted as this stage is preferably an over-etching process such that after removing all of work function metal layer46on the NMOS region16some of the BBM layer44on the NMOS region16is removed thereafter. This exposes part of the sidewall of the BBM layer44on the PMOS region and reduces the overall thickness of the BBM layer44on NMOS region16so that the remaining thickness of the BBM layer44on NMOS region16is slightly less than the thickness of the BBM layer44on PMOS region14. The patterned resist48is stripped thereafter.

Next as shown inFIG.4, a diffusion barrier layer50is formed on the surfaces of the work function metal layer46on PMOS region14and the BBM layer44on NMOS region16. It should be noted that since part of the BBM layer44on NMOS region16has been removed by the aforementioned etching process, the diffusion barrier layer50at this stage is preferably formed on the top surface of the work function metal layer46on PMOS region14, a sidewall of the work function metal layer46on PMOS region14, a sidewall of the BBM layer44on PMOS region14, and the top surface of the BBM layer44on NMOS region16. Viewing from another perspective, the diffusion barrier layer50is formed to extend from the PMOS region14to the NMOS region16and covering the work function metal layer46on PMOS region14, the BBM layer44on NMOS region16, and sidewalls of the work function metal layer46and BBM layer44at the intersecting point between PMOS region14and NMOS region16at the same time. Preferably, the BBM layer44and the diffusion barrier layer50are made of same material such as but not limited to for example TaN.

Next, as shown inFIG.5, another work function metal layer52and a low resistance metal layer54are sequentially formed on the surface of the diffusion barrier layer50on both PMOS region14and NMOS region16, and a planarizing process such as CMP is conducted to remove part of the low resistance metal layer54, part of the work function metal layer52, part of the diffusion barrier layer50, part of the BBM layer44, part of the BBM layer42, and part of the high-k dielectric layer40to form metal gate56.

Preferably, the work function metal layer52is a n-type work function metal layer having work function ranging between 3.9 eV and 4.3 eV, which may include titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or titanium aluminum carbide (TiAlC), but not limited thereto. The low-resistance metal layer54could include copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP) or any combination thereof.

Next, a pattern transfer process could be conducted by using patterned mask to remove part of the ILD layer34and part of the CESL32adjacent to the metal gate56to form contact holes (not shown) exposing the source/drain regions28,30underneath. Next, metals such as a barrier layer including Ti, TiN, Ta, TaN, or combination thereof and a metal layer including W, Cu, Al, TiAl, CoWP, or combination thereof could be deposited into the contact holes, and a planarizing process such as CMP is conducted to remove part of the metals to form contact plugs electrically connecting the source/drain regions28,30. This completes the fabrication of a semiconductor device according to an embodiment of the present invention.

Referring again toFIG.5,FIG.5further illustrates a structural view of a semiconductor device according to an embodiment of the present invention. As shown inFIG.5, the semiconductor device preferably includes a gate structure20or metal gate56disposed on the substrate12while the gate structure20extends or laterally crossing the PMOS region14and NMOS region16at the same time. Preferably, the gate structure20includes an interfacial layer38or gate dielectric layer extending from the PMOS region14to the NMOS region16, a high-k dielectric layer40extending from the PMOS region14to the NMOS region16, a BBM layer42extending from the PMOS region14to the NMOS region16, another BBM layer44extending from the PMOS region14to the NMOS region16, a work function metal layer46disposed on the PMOS region14, a diffusion barrier layer50extending from the PMOS region14to the NMOS region16, another work function metal layer52extending from the PMOS region14to the NMOS region16, and a low resistance metal layer54extending from the PMOS region14to the NMOS region16.

Viewing from a more detailed perspective, the high-k dielectric layer40is extended from the PMOS region14to NMOS region16and disposed on the surface of the interfacial layer38, the BBM layer42is extended from the PMOS region14to NMOS region16and directly contacting the surface of the high-k dielectric layer40, the BBM layer44is extended from the PMOS region14to NMOS region16and directly contacting the surface of the BBM layer42, the work function metal layer46is only disposed on the PMOS region14and directly contacting the surface of the BBM layer44on PMOS region14without extending to the NMOS region16, the diffusion barrier layer50is extended from the PMOS region14to NMOS region16and directly contacting the top surface of the work function metal layer46on PMOS region, a sidewall of the work function metal layer46on PMOS region14(or more specifically on the intersecting point between PMOS region14and NMOS region16), a sidewall of the BBM layer44on PMOS region14(or more specifically on the intersecting point between PMOS region14and NMOS region16), and the top surface of BBM layer44on NMOS region16, the work function metal layer52is extended from the PMOS region14to NMOS region16and directly contacting the top surface of the diffusion barrier layer50, and the low resistance metal layer54is extended from the PMOS region14to NMOS region16and directly contacting the surface of the work function metal layer52.

It should be noted that the thickness of the BBM layer44on NMOS region16is preferably less than the thickness of the BBM layer44on PMOS region14or more specifically the thickness of the BBM layer44on NMOS region16is approximately half the thickness of the BBM layer44on PMOS region14, and at the same time the thickness of the diffusion barrier layer50is preferably equal to the thickness of the BBM layer44on NMOS region16or half the thickness of the BBM layer44on PMOS region14. In other word, the total thickness of the BBM layer44and diffusion barrier layer50combined on NMOS region16is preferably equal to the total thickness of a single BBM layer44on PMOS region14.

Referring toFIGS.6-8,FIGS.6-8illustrate a method for fabricating semiconductor device according to an embodiment of the present invention. As shown inFIG.6, it would be desirable to sequentially form an interfacial layer38, a high-k dielectric layer40, a BBM layer42, another BBM layer44, and a work function metal layer46on both PMOS region14and NMOS region16as shown inFIG.2and then directly form a diffusion barrier layer50on the surface of the work function metal layer46on both PMOS region14and NMOS region16.

Next, as shown inFIG.7, a patterned mask such as a patterned resist58is formed to cover the PMOS region14, and an etching process is conducted by using the patterned resist58as mask to remove the diffusion barrier layer50and the work function metal layer46on NMOS region16to expose the surface of the BBM layer44underneath. The patterned resist58is stripped thereafter.

Next, as shown inFIG.8, another work function metal layer52and a low resistance metal layer54are formed on the surface of the diffusion barrier layer50on PMOS region14and the surface of the BBM layer44on NMOS region16, and a planarizing process such as CMP is conducted to remove part of the low resistance metal layer54, part of the work function metal layer52, part of the diffusion barrier layer50, part of the work function metal layer46, part of the BBM layer44, part of the BBM layer42, and part of the high-k dielectric layer40to form metal gate60.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.