Patent ID: 12255660

DETAILED DESCRIPTION

The following description sets forth numerous specific details such as examples of specific systems, components, methods, and so forth, in order to provide a good understanding of various embodiments of a digital phase-locked loop (DPLL) described herein. Such DPLLs may be employed in memory control units in different types of transportation vehicles or in any number of other applications such as home automation and security. It will be apparent to one skilled in the art, however, that at least some embodiments may be practiced without these specific details. In other instances, well-known components, elements, or methods are not described in detail or are presented in a simple block diagram format in order to avoid unnecessarily obscuring the subject matter described herein. Thus, the specific details set forth hereinafter are merely exemplary. Particular implementations may vary from these exemplary details and still be contemplated to be within the spirit and scope of the present embodiments.

Reference in the description to “an embodiment,” “one embodiment,” “an example embodiment,” “some embodiments,” and “various embodiments” means that a particular feature, structure, step, operation, or characteristic described in connection with the embodiment(s) is included in at least one embodiment. Further, the appearances of the phrases “an embodiment,” “one embodiment,” “an example embodiment,” “some embodiments,” and “various embodiments” in various places in the description do not necessarily all refer to the same embodiment(s).

The description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show illustrations in accordance with exemplary embodiments. These embodiments, which may also be referred to herein as “examples,” are described in enough detail to enable those skilled in the art to practice the embodiments of the claimed subject matter described herein. The embodiments may be combined, other embodiments may be utilized, or structural, logical, and electrical changes may be made without departing from the scope and spirit of the claimed subject matter. It should be understood that the embodiments described herein are not intended to limit the scope of the subject matter but rather to enable one skilled in the art to practice, make, and/or use the subject matter.

FIG.1is a simplified block diagram of a digital phase-locked loop (DPLL)100employed in certain electronic devices. In some cases, the DPLL100includes a phase detector (PD) and time-to-digital converter (TDC)110, a clock-to-data synchronizer115, a digital loop filter (DLF)120, a digitally-controlled oscillator (DCO)130, and a frequency divider150, generally coupled together in a loop, as illustrated. In such DPLL100, the PD (of the PD & TDC110) is adapted to detect a phase and frequency of an input reference clock (REFCLCK) and a feedback clock (FBCLK). Further, in the DPLL100, the TDC of the PD & TDC110is configured to determine a time difference (e.g., a phase error) between the reference frequency (Fref) of the input reference clock and the feedback frequency (Fb) of the feedback clock.

The TDC of the PD & TDC110generates a multi-bit code that digitally encodes the time difference (e.g., quantifies the phase error) and is designed to trigger the DCO130to adjust an output frequency (Fout) of an alternating-current (AC) output signal of the DPLL100. The DCO130of DPLLs is generally implemented as a code-to-frequency circuit, where for each input code (e.g., set of digital bits or pulses), there is a unique output frequency if the DCO130. The DLF120, which is coupled between the TDC and the DCO130, is configured to digitally filter the multi-bit code to ensure these bits are accurate and the DCO130can stably, with acceptable noise, modulate the output frequency based on the filtered digital bits or code.

In various applications, the DPLL100may be employed in battery-powered consumer electronics, lower-power wireless sensors, home automation systems, remote controls, and automotive memory control units (MCUs), for example, where low cost, low power, fewer bill of materials (BOM), or smaller size are highly desired. The DLF120is generally implemented as an on-chip integrated loop filter to further keep the design smaller than analog counterparts. The frequency divider150divides the output frequency of the AC output signal by an integer value (N) in order to generate the feedback clock that flows back into the PD & TDC110. The DPLL100is thus designed to operate in a feedback loop in which the time difference between the input reference clock and the feedback clock is minimized until “locking” onto the frequency and phase of the input reference clock.

In certain DPLLs such as the DPLL100, the digits bits that the DLF120receives from TDC are out of synch (e.g., asynchronous) with the input reference clock that the DLF120also receives. Thus, a separate synchronization circuit, such as the clock-to-data synchronizer115, is employed between the TDC and the DLF120in order to synchronize the reference clock to the data being passed as digital bits. This extra synchronization stage adds in another clock cycle, which creates delay in the operation of the DPLL that in turn causes jitter in the output signal. This separate synchronization circuit also adds cost and area to the DPLL design

FIG.2Ais a more-detailed block diagram of a digital PLL (or DPLL200) in accordance with at least some embodiments, which is designed to resolve the deficiencies of certain DPLLs that were discussed with reference toFIG.1. The DPLL200, in various embodiments, may be a DPLL circuit, a DPLL device, or a DPLL apparatus. The DPLL200, for example, may include a phase detector (PD)205, a time-to-digital converter (TDC) circuit210operatively coupled to the PD205, a digital loop filter (DLF)220operatively coupled to the TDC circuit210, a digitally-controlled oscillator (DCO) circuit230coupled to the DLF220, and a frequency divider250coupled between an output of the DCO circuit230and the PD205.

In these embodiments, the PD205is configured to detect a phase and frequency of an input reference clock (REFCLCK) and a feedback clock (FBCLK), e.g., so as to be able to provide the reference frequency (Fret) and phase of the input reference clock and the feedback frequency (Ffb) and phase of the feedback clock to the TDC circuit210. Further, in at least one embodiment, the TDC circuit210includes phase error calculation circuitry212adapted to determine phase error values based on a time difference between the input reference clock and the feedback clock of a DPLL200. The input reference clock and the feedback clock are unsynchronized, as was discussed with reference toFIG.1, so pulses of each of these clocks may include some time difference that may be encoded as phase error values. In this at least one embodiment, the phase error calculation circuitry212further provides the phase error values to the DLF220of the DPLL200.

In some embodiments, the phase error values are a series of digital bits or pulses such as a digital multi-bit code that digitally encodes the time difference (or phase error) and are designed to trigger the DCO circuit230to adjust an output frequency (Fout) of an alternating-current (AC) output signal of the DPLL200. The DCO circuit230thus generates an output signal that is convertible to the feedback clock, e.g., via the frequency divider250. For example, the feedback divider250may generate the feedback clock by reducing a frequency of the output signal of the DCO circuit230by an integer value (e.g., N).

In at least some embodiments, the DLF220digitally filters the multi-bit code (e.g., series of digital bits) received from the TDC circuit210to generate a filtered series of digital bits that are capable of accurately driving the DCO circuit230. The DLF220, for example, may include proportional path logic220A having a first gain and integral path logic220B having a second gain. In some embodiments, the DLF220implements a z-domain transfer function to process a combination of a proportional part of the multi-bit code multiplied by the first gain and an integral part of the multi-bit code multiplied by the second gain. The proportional path logic220A and the integral path logic220B may both be instantiated in an on-chip integrated loop filter of the DPLL200, for example.

In at least some embodiments, and to overcome the deficiencies of previous designs, the TDC circuit210of the DPLL200further includes clock generation circuitry216. In these embodiments, the clock generation circuitry216generates a filter clock that asserts a clock pulse in response to detecting each last-received pulse of the input reference clock and the feedback clock (seeFIGS.3A-3B). In these embodiments, the clock generation circuitry216is further to provide the filter clock to the DLF220concurrently with providing the phase error values (e.g., series of digital bits) to the DLF220that are synchronized to the filter clock. In this way, the clock generation circuitry216synchronizes the phase error values with the clock pulses of the filter clock due to triggering these clock pulses off the last-received pulse of the input reference clock and the feedback clock, e.g., not relying only on the reference clock that is not synchronized to the phase error values. In some embodiments, the phase error values are a series of digital bits or a multi-bit code, as was discussed. The clock generation circuitry216is discussed in more detail with reference toFIG.2B.

Further, in these embodiments, the DCO circuit230includes a current digital-to-analog converter (IDAC)232coupled to a ring oscillator238. For example, the IDAC232may convert the phase error values (e.g., the series of digital bits) to a current that is supplied to the ring oscillator238. The ring oscillator238generates an AC output signal (Fout) of the DPLL200that corresponds to the received current from IDAC232. The output signal is convertible by the frequency divider250in generating the feedback clock (FBCLK) supplied to the PD205.

FIG.2Bis a schematic circuit diagram of the clock generation circuitry216of the TDC210of the DPLL200(FIG.2A) in accordance with at least some embodiments. In these at least some embodiments, the clock generation circuitry216includes a first latch242A that is triggered by the input reference clock (REFCLK), a second latch242B that is triggered by the feedback clock (FBCLK), and an AND gate244that is coupled to outputs of each of the first latch and the second latch and outputs the filter clock. In this way, as illustrated inFIGS.3A-3B, once the last-received pulse between the input reference clock and the feedback clock is received, both the first latch242A and the second latch242B assert outputs and the output of the AND gate244is also asserted, which starts a next pulse of the filter clock.

In some embodiments, each of the first latch242A and the second latch242B are gated D-latches, which prevents application of a restricted input combination. The gated D-latches, also referred to as transparent latches, data latches, or simply gated latches or gated flip-flops, each has a data input (“1” in this embodiment) and an enable signal, which in this embodiment is the input clock, e.g., the input reference clock in the first latch242A and the feedback clock in the second latch242B. Thus, a one value is provided to inputs of the each of the first latch242A and second latch242B and these clock signals act as enables signals for the first latch242A and the second latch242B. In other embodiments, different kinds of latches are employed with optionally different external circuitry to trigger the pulses of the filter clock.

In at least some embodiments, the clock generation circuitry216further includes a pulse width modulation (PWM) circuit260coupled to an output of the AND gate244. In these embodiments, the PWM circuit260sets a pulse width of each clock pulse of the filter clock and resets the first latch and the second latch at an end of each pulse width, completing the controlled formation of the filter clock that is provided to the DLF220. In this way, the TDC210independently generates the filter clock, reducing the number of clock cycles, cost, and chip area needed to generate the filter clock, which in turn reduces the jitter of the output signal generated by the DCO230.

FIGS.3A-3Bare graphs of a filter clock that is output from the clock generation circuitry216in accordance with at least some embodiments. As mentioned, the PWM circuit260generates a filter clock that asserts a clock pulse in response to detecting each last-received pulse of the input reference clock and the feedback clock. The graph ofFIG.3Aillustrates that a pulse from the input reference clock (REFCLK) has arrived first and a pulse from the feedback clock (FBCLK) has arrived last at the clock generation circuitry216of the TDC210. Thus, the clock generation circuitry216asserts a pulse of the filter clock in response to detecting this last-received pulse of the feedback clock. The TDC data (series of digital bits) that is also passing through the TDC210is illustrated below the filter clock waveform, illustrating that the filter clock has been synchronized to the data transition all within the TDC210. Thus, the need for the extra, external clock-to-data synchronizer115(FIG.1) has been eliminated.

Similarly, the graph ofFIG.3Billustrates that a pulse from the feedback clock has arrived first and a pulse from the input reference clock has arrived last at the clock generation circuitry216of the TDC210. Thus, the clock generation circuitry216asserts a pulse of the filter clock in response to detecting this last-received pulse of the feedback clock. The TDC data (series of digital bits) that is also passing through the TDC210is illustrated below the filter clock waveform, illustrating that the filter clock has been synchronized to the data transition all within the TDC210. Thus, the need for the extra, external clock-to-data synchronizer115(FIG.1) has been eliminated.

FIG.4is a flow diagram of method400of operating the DPLL200that employs the clock generation circuitry216in accordance with at least some embodiments. Thus, in these embodiments, the method400is performed by the DPLL200, and particularly the TDC circuit210of the DPLL200illustrated inFIG.2. The operations need not be performed in a specific order, unless explicitly disclosed to be required to be performed in such an order.

At operation410, the method400begin with generating, by the TDC210, phase error values based on a time difference between an input reference clock and a feedback clock of the DPLL circuit200, the input reference clock and the feedback clock being unsynchronized.

At operation420, the method400continues with generating, by the TDC210, a filter clock that asserts a clock pulse in response to detecting each last-received pulse of the input reference clock and the feedback clock.

At operation430, the method continues by providing, by the TDC210to the DLF220, the phase error values concurrently with the clock pulses of the filter clock.

At operation440, the method continues by generating, by the DLF220, filtered phase error values that causes the DCO to generate an output signal that is convertible to the feedback clock.

In at least some embodiments, the method400further includes synchronizing, by the TDC210, the generating the phase error values with the generating the clock pulses, where the phase error values are a series of digital bits. This synchronization may be ensured by the operation420and/or triggering off the phase error values generated by the phase error correction circuitry212, which was discussed with reference toFIG.2A.

Various embodiments of the AC-DC flyback converter described herein may include various operations. These operations may be performed and/or controlled by hardware components, digital hardware and/or firmware, and/or combinations thereof. As used herein, the term “coupled to” may mean connected directly to or connected indirectly through one or more intervening components. Any of the signals provided over various on-die buses may be time multiplexed with other signals and provided over one or more common on-die buses. Additionally, the interconnection between circuit components or blocks may be shown as buses or as single signal lines. Each of the buses may alternatively be one or more single signal lines and each of the single signal lines may alternatively be buses.

Certain embodiments may be implemented by firmware instructions stored on a non-transitory computer-readable medium, e.g., such as volatile memory and/or non-volatile memory. These instructions may be used to program and/or configure one or more devices that include processors (e.g., CPUs) or equivalents thereof (e.g., such as processing cores, processing engines, microcontrollers, and the like), so that when executed by the processor(s) or the equivalents thereof, the instructions cause the device(s) to perform the described operations for USB-C mode-transition architecture described herein. The non-transitory computer-readable storage medium may include, but is not limited to, electromagnetic storage medium, read-only memory (ROM), random-access memory (RAM), erasable programmable memory (e.g., EPROM and EEPROM), flash memory, or another now-known or later-developed non-transitory type of medium that is suitable for storing information.

Although the operations of the circuit(s) and block(s) herein are shown and described in a particular order, in some embodiments the order of the operations of each circuit/block may be altered so that certain operations may be performed in an inverse order or so that certain operation may be performed, at least in part, concurrently and/or in parallel with other operations. In other embodiments, instructions or sub-operations of distinct operations may be performed in an intermittent and/or alternating manner.

In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.