Patent ID: 12237009

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like, are described below to simplify the disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the disclosure may repeat reference numerals and/or letters in the various examples.

This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In addition, terms, such as “first”, “second”, “third”, “fourth” and the like, may be used herein for ease of description to describe similar or different element(s) or feature(s) as illustrated in the figures, and may be used interchangeably depending on the order of the presence or the contexts of the description.

The sense amplifier suffers from slow read speed and large offset voltage due to device mismatch. By minimizing the offset voltage of the sense amplifier, the read developing time of the bit-line can be reduced and the read latency of the bit-line can be reduced as well.

In order to keep the offset of the sense amplifier in the allowable margin, the sense amplifier suffers from the problems with slower read speed and higher read fail probability. On the other hand, the bit-line developing time needs to be long enough to get higher read margin for voltage difference sensing. However, the longer bit-line developing time leads to the increasing of the read time. Thus, an offset of the sense amplifier requires more tolerant margin to detect the voltage difference and then achieves faster read speed. That is, an offset tolerant and latch type sense amplifier is required for sensing a memory with small read margin so as to achieve the faster read speed.

FIG.1Ais a schematic diagram illustrating a memory circuit in accordance with some embodiments of the present disclosure.FIG.1Bis a schematic diagram illustrating a memory cell in the memory circuit as shown inFIG.1Ain accordance with some embodiments.

Referring toFIG.1AandFIG.1B, the memory circuit100includes memory arrays MA, a column decoder101, a word line decoder102, and a sense amplifier SA. The memory arrays MA include memory cells MC, word lines WL, and bit lines BL, BLB. Each memory cells MC includes at least one access transistor (not shown). The word lines WL (i.e., WL0, . . . , WLn−1, WLn) are respectively coupled to a row of the memory cells MC. The bit lines BL, BLB are respectively coupled to a column of the memory cells MC. The sense amplifier SA is coupled to the column decoder101through a first data line DL and a second data line DLB.

Referring toFIG.1AandFIG.1B, the column decoder101is used to select the voltage signals from the bit lines BL, BLB and output the decoded voltage signals to the first data line DL and the second data line DLB. The word line decoder102is used to select the word lines WL. The sense amplifier SA is used to detect a voltage difference between the bit lines BL, BLB. The voltage signals of the bit lines BL, BLB are transmitted to the column decoder101and then the voltage signals of the bit lines BL, BLB are decoded to be data signals. The decoded data signals on the first data line DL and the second data line DLB may lead to a voltage difference between the first data line DL and the second data line DLB, and then the voltage difference between the first data line DL and the second data line DLB will be transmitted to the inputs of the sense amplifier SA. The sense amplifier SA senses the voltage difference between voltage inputs through the first data line DL and the second data line DLB and then outputs a sensing voltage at an output node of the sense amplifier circuit related to the read data.

Referring toFIG.1AandFIG.1B, in the exemplary embodiment, the bit lines BL, BLB are attached (electrically coupled) to the sense amplifier (sense amplifier circuits) SA at the edge of the memory array MA. In some embodiments, the bit lines BL, BLB are attached (electrically coupled) to the column decoder101, and the sense amplifier SA is attached (electrically coupled) to the column decoder101through the data lines, for example, the first data line DL and the second data line DLB. As shown inFIG.1A, the memory cells MC located in the same column may be electrically coupled to the sense amplifier SA using two complementary bit lines BL, BLB.

In some embodiments, the sense amplifier SA is configured to compare voltages on the associated bit lines BL, BLB, and output a read signal indicating the data stored in a selected memory cell MC during a read operation. In addition, the amplification and readout functions are integrated as one circuit in each of the sense amplifier SA. In such embodiment, the memory cells MC in the memory arrays MA are for example, static random access memory (SRAM) type memory cells. In some embodiments, the memory cells MC in the memory arrays MA are a series of 6T-SRAM103. The 6T-SRAM103is the SRAM structure of this embodiment, and those who use this embodiment can adjust the number of transistors in the SRAM according to their needs, so as to realize the function of the SRAM. However, the disclosure is not limited thereto.

Moreover, the memory cells MC may further include an access transistor T1. A gate terminal of the access transistor T1is connected to a word line WL. In addition, a source/drain terminal of the access transistor T1is coupled to a storage node Q1, while the other source/drain terminal of the access transistor T1is connected to bit line BL. When the access transistor T1is enabled, the bit line BL can charge/discharge the storage node Q1, or vice versa. Accordingly, logic data can be programmed to the storage node Q1, or read out from the storage node Q1. On the other hand, when the access transistor T1is in an off state, the storage node Q1is decoupled from the bit line BL, and logic data cannot be written to or read out from the storage node Q1. In other words, the access transistor T1may control access of the storage node Q1.

Similarly, access of the storage node is controlled by an access transistor T2. The word line WL for controlling switching of the access transistor T1may also connect to a gate terminal of the access transistor T2. In this way, the access transistors T1, T2may be switched simultaneously. In addition, a source/drain terminal of the access transistor T2is coupled to a storage node Q2, while the other source/drain terminal of the access transistor T1is connected to a bit line BLB. When the access transistor T2is enabled, the bit line BLB can charge/discharge the storage node Q2, or vice versa. Accordingly, logic data can be programmed to the storage node Q2, or read out from the storage node Q2. On the other hand, when the access transistor T2is in an off state, the storage node Q2is decoupled from the bit line BLB, and logic data cannot be written to or read out from the storage node Q2. During a write operation, the bit lines BL, BLB may receive complementary logic data, in order to overwrite the logic data previously stored at the storage nodes Q1, Q2. In addition, during a read operation using the sense amplifier SA, both of the bit lines BL, BLB are pre-charged, and one of them is slightly pulled down by the corresponding storage node. By comparing voltage difference of the bit lines BL, BLB, the logic data stored at the storage nodes Q1, Q2can be read out easily using the sense amplifier SA.

FIG.2Ais a schematic diagram of a sense amplifier circuit as shown inFIG.1Ain accordance with some embodiments.FIG.2Bis a schematic diagram of a sense amplifier circuit as shown inFIG.1Ain accordance with another embodiments.FIG.2Cis a schematic diagram of a sense amplifier circuit as shown inFIG.1Ain accordance with some embodiments.FIG.2Dis a schematic diagram of a sense amplifier circuit as shown inFIG.1Ain accordance with some embodiments. The sense amplifier circuit illustrated inFIG.2B,FIG.2C, andFIG.2Dis similar to the sense amplifier circuit illustrated inFIG.2A. Therefore, the same reference numerals are used to refer to the same or liked parts, and its detailed description will be omitted herein.

Referring toFIG.2A,FIG.2B,FIG.2C, andFIG.2D, the sense amplifier circuit200is provided. The sense amplifier circuit200includes, a differential amplifier DA, a first switch SW1, and a second switch SW2. The differential amplifier DA includes a first input node N1and a second input node N2. The differential amplifier DA is coupled to the first switch SW1, and the second switch SW2. The first switch SW1is coupled to a control line CL. The first node of the first switch SW1is coupled to the first input node N1, and a second node of the first switch SW1is coupled to the first output node Q. The second switch SW2is coupled to the control line CL. The first node of the second switch SW2is coupled to the second input node N2, and the second node of the second switch SW2is coupled to the second output node QB.

In some embodiments, the sense amplifier circuit200includes a power supply PS, a differential amplifier DA, a pull-down circuit PD, a first switch SW1, and a second switch SW2. The differential amplifier DA is coupled to the power supply PS, the first switch SW1, and the second switch SW2. The pull-down circuit PD is coupled to the differential amplifier DA. In some embodiments, the pull-down circuit PD may be coupled to the first switch SW1and the second switch SW2as well. The first switch SW1is coupled to the first data line DL, a control line CL, and the differential amplifier DA. The second switch SW2is coupled to the second data line DLB, the control line CL, and the differential amplifier DA.

In some embodiments, the differential amplifier DA amplifies a voltage difference of the first output node Q and the second output node QB according to a first input voltage VIN of the first input node N1and a second input voltage VIN′ of the second input node N2. The first switch SW1pre-charges the first input node N1by a first output voltage of the first output node Q while the control line CL is received a select signal SAE where the sense amplifier circuit is enabled by the select signal SAE. The second switch SW2the second input node N2by a second output voltage of the second output node QB while the control line CL is received the select signal SAE where the sense amplifier circuit is enabled by the select signal SAE. In some embodiments, the voltage difference between the first input node N1and the second input node N2may decrease gradually during a sensing period.

In accordance with some embodiments, the power supply PS provides the power voltage. The differential amplifier DA provides the input voltages VIN, VIN′. In accordance with some embodiments of the disclosure, the input voltages VIN, VIN′ are provided by virtue of the column decoder101through the first data line DL and the second data line DLB. The pull-down circuit PD provides a biasing current source. In accordance with some embodiments of the disclosure, the pull-down circuit PD provides a biasing voltage source. The first switch SW1transfers a first bit line voltage to a first input node N1upon receiving a select signal SAE from a controller (not shown). The second switch SW2transfers a second bit line voltage to a second input node N2upon receiving the select signal SAE from the controller. In some embodiments, the voltage level of the first input voltage VIN of the first input node N1and the voltage level of the second input voltage VIN′ of the second input node N2are complement. In some embodiments, the voltage level of the second bit line voltage is complementary to the first bit line voltage.

Referring toFIG.2A,FIG.2B,FIG.2C, andFIG.2D, in accordance with some embodiments of the disclosure, the sense amplifier circuit200includes an inverter pair INVP and a pull-down circuit PD. The inverter pair INVP is coupled to the power supply PS, the first switch SW1, the second switch SW2, and the differential amplifier DA. The pull-down circuit PD is coupled to the differential amplifier, the first switch SW1and the second switch SW1. In some embodiments, the pull-down circuit PD provides a biasing current source to discharge the sense amplifier circuit.

In accordance with some embodiments of the disclosure, the inverter pair INVP is adapted to provide positive feedback for voltage latching behavior. In the exemplary embodiment, the inverter pair INVP is a kind of latch circuit, for example, a cross-coupled inverter. As such, the inverter pair INVP is adapted to retain the stored data of the memory cells MC in the memory arrays MA from the input of the sense amplifier circuit200without being periodically refreshed. In some embodiments, the inverter pair INVP includes two inverters. A first inverter201may include a pull-up transistor and a pull-down transistor (not shown). The pull-up transistor may be a P-type Metal-Oxide-Semiconductor (PMOS) field effect transistor, while the pull-down transistor may be an N-type Metal-Oxide-Semiconductor (NMOS) field effect transistor. The pull-up transistor and the pull-down transistor of the first inverter201share a common source/drain terminal, and such common source/drain terminal may be referred as a first storage node Q of the memory cells MC. In addition, the other source/drain terminal of the pull-up transistor is coupled to a working voltage VDD (not shown) provided from the power supply PS. On the other hand, the other source/drain terminal of the pull-down transistor is coupled to a reference voltage VSS (not shown), such as a ground voltage. In some embodiments, the reference voltage is pre-charged to the first storage node Q. For example, the reference voltage may be the first bit line voltage. Furthermore, gate terminals of the pull-up transistor and the pull-down transistor of the first inverter201are connected with each other. A node coupled to the gate terminals of the pull-up transistor and the pull-down transistor may be an input terminal of the first inverter201, and the first storage node Q may be an output terminal of the first inverter201.

Similarly, a second inverter202in the inverter pair INVP may include a pull-up transistor and a pull-down transistor. The pull-up transistor may be a PMOS field effect transistor, while the pull-down transistor may be an NMOS field effect transistor. The pull-up transistor and the pull-down transistor of the second inverter202share a common source/drain terminal, which may be referred as a second storage node QB of the memory cells MC. The other source/drain terminal of the pull-up transistor is coupled to the working voltage VDD (not shown), while the other source/drain terminal of the pull-down transistor is coupled to the reference voltage VSS (not shown). In addition, gate terminals of the pull-up transistor and the pull-down transistor of the second inverter202are connected with each other. A node coupled to the gate terminals of the pull-up transistor and the pull-down transistor of the second inverter202may be an input terminal of the second inverter, while the second storage node QB may be an output terminal of the second inverter202. On the other hand, the other source/drain terminal of the pull-down transistor is coupled to a reference voltage VSS (not shown), such as a ground voltage. In some embodiments, the reference voltage is pre-charged to the second storage node QB. For example, the reference voltage may be the second bit line voltage. Referring toFIG.2A,FIG.2B,FIG.2C, andFIG.2D, in accordance with some embodiments of the disclosure, the first switch SW1further includes a first pre-charge switch PRE1and a first control switch CSW1. The second switch SW2further includes a second pre-charge switch PRE2and a second control switch CSW2. The first pre-charge switch PRE1may be directly coupled to the first inverter201and the differential amplifier DA. The second pre-charge switch PRE2may be directly coupled to the second inverter202and the differential amplifier DA. The first control switch CSW1is coupled to the first pre-charge switch PRE1and the first data line DL. The second control switch CSW2is coupled to the second pre-charge switch PRE2and the second data line DLB. The first control switch CSW1is coupled to the pull-down circuit PD through the control line CL. The second control switch CSW2is coupled to the pull-down circuit PD through the control line CL. In some embodiments, the first control switch CSW1and the second control switch CSW2may be coupled to the pull-down circuit PD through the same control line CL.

In accordance with some embodiments of the disclosure, the first pre-charge switch PRE1may bring the first data line DL and the second data line DLB to be either the same (for example, VDD and VDD) or the complement voltage (for example, VDD and VSS) before a read cycle. The first pre-charge switch PRE1may consist of a transistor that can be either NMOS or PMOS devices. In some embodiments, the first pre-charge switch PRE1and the first control switch CSW1may be PMOS devices. The first control switch CSW1are used to connect the first data line DL to, for instance, the logic high (i.e., 1 or VCC). The second pre-charge switch PRE2may consist of a transistor that can be either NMOS or PMOS devices. In some embodiments, the second pre-charge switch PRE2and the second control switch CSW2may be PMOS devices. The second control switch CSW2is used to connect the second data line DLB to, for instance, the logic high (i.e., 1 or VCC). The first pre-charge switch PRE1is connected between the first control switch CSW1and the first inverter201, and the second pre-charge switch PRE2is connected between the second control switch CSW2and the second inverter202to ensure that the first storage node Q and the second storage node QB end up being the same voltage.

In yet other embodiments, the first pre-charge switch PRE1and the second pre-charge switch PRE2ensure that the first storage node (i.e., the first output node) Q and the second storage node (i.e., the second output node) QB end up being the complement voltage. As such, the voltage difference (voltage offset) between the first input node N1and the second input node N2is pre-established and then the sense amplifier SA is able to sense the pre-established voltage difference much earlier (i.e., the predetermined bit-line developing time will be decreased) before the sensing period. Therefore, the sensing speed is able to be enhanced after the pull-down circuit PD is enabled during the sensing period. In some embodiments, the bit-line developing time indicates the period of time that the voltage difference (or voltage offset, voltage swing) changes from 0 to relatively larger enough than the voltage offset between the bit-lines BL, BLB so as to be identified by the sense amplifier SA.

To pre-charge the first storage node Q, the select signal SAE is brought to a logic low (i.e., 0 or VSS). That is, the first control switch CSW1is enabled when the sense amplifier SA is enabled at logic low. This enables the first control switch CSW1and the first pre-charge switch PRE1which then charge and equalize the first storage node Q and the second storage node QB to be VCC before a read cycle. Similarly, to pre-charge the second storage node QB, the select signal SAE is brought to a logic low (i.e., 0 or VSS). That is, the second control switch CSW2is enabled when the sense amplifier SA is enabled at logic low. This enables the second control switch CSW2and the second pre-charge switch PRE2which then charge and equalize the second storage node QB and the first storage node Q to be VCC before a read cycle.

In some embodiments, the first storage node Q as the input terminal of the second inverter202is coupled to the second storage node QB as the output terminal of the first inverter201, and the second storage node QB as the input terminal of the first inverter201is coupled to the first storage node Q as the output terminal of the second inverter202. In other words, the first inverter201and the second inverter202are cross-coupled. As a result, the first storage node Q and the second storage node QB are ensured to store complementary logic data. For instance, when a logic data “0” is stored at the first storage node Q, the P-type pull-up transistor of the second inverter202may be enabled as its gate terminal is coupled to the first storage node Q of the first inverter201, and the second storage node QB of the second inverter202as a source/drain terminal of the pull-up transistor is pulled up by the working voltage VDD coupled to the other source/drain terminal of the pull-up transistor. Therefore, a logic data “1” complementary to the logic data “0” is stored at the second storage node QB.

On the other hand, the N-type pull-down transistor of the second inverter202is kept in an off state as its gate terminal is also coupled to the first storage node Q holding at the logic data “0”, thus the second storage node QB as a source/drain terminal of the pull-down transistor of the second inverter202would not be pulled down by the reference voltage (e.g., VSS) coupled to the other source/drain terminal of the pull-down transistor of the second inverter202. In addition, the N-type pull-down transistor of the first inverter201is enabled as its gate terminal is coupled to the second storage node QB holding at the logic data “1”, and the first storage node Q as a source/drain terminal of the pull-down transistor of the first inverter201is kept discharged by the reference voltage (e.g., VSS) coupled to the other source/drain terminal of the pull-down transistor of the first inverter201. In addition, the P-type pull-up transistor of the first inverter201is kept in an off state as its gate terminal is also coupled to the second storage node QB holding at the logic data “1”, thus the first storage node Q as a source/drain terminal of the pull-up transistor of the first inverter201would not be pulled up by the working voltage VDD coupled to the other source/drain terminal of the pull-up transistor of the first inverter201. Therefore, the logic data “0” can be retained at the first storage node Q.

FIG.2Eis a schematic diagram of a sense amplifier circuit as shown inFIG.1Ain accordance with another embodiments.FIG.2Fis a schematic diagram of a sense amplifier circuit as shown inFIG.1Ain accordance with yet another embodiment. The sense amplifier circuit illustrated inFIG.2EandFIG.2Fis similar to the sense amplifier circuit illustrated inFIG.2A-2D. Therefore, the same reference numerals are used to refer to the same or liked parts, and its detailed description will be omitted herein.

Referring toFIG.2AandFIG.2E, the differential amplifier DA may further include a matching capacitor CAP. The matching capacitor CAP is coupled to the first switch SW1and the second switch SW2at the first input node N1and the second input node N2.

In some embodiments, the matching capacitor CAP is adapted to keep a voltage difference between the first input voltage VIN of the first input node N1and the second input voltage VIN′ of the second input node N2during a sensing period. In some embodiments, the voltage difference between the first input node N1and the second input node N2may be equal to the voltage difference between the first bit line voltage and the second bit line voltage transferred from the first bit line BL (or the first data line DL) and the second bit line BLB (or the second data line DL) before the sensing period.

FIG.3Ais a schematic diagram of a sense amplifier circuit as shown inFIG.1Ain accordance with some embodiments.FIG.3Bis a timing diagram of the sense amplifier circuit shown inFIG.3Ain the operation process according to some embodiments of the present disclosure.

Referring toFIG.3A, the sense amplifier circuit includes the differential amplifier, the first switch, the second switch, the first control switch CSW1, and the second control switch CSW2. The differential amplifier includes an inverter pair, a pull-down switch PD, a first input switch M7and a second input switch M8. The inverter pair includes a third switch M3, a fourth switch M4, a fifth switch M5, and a sixth switch M6. The third switch M3are coupled to the first pre-charge switch PRE1, the first control switch, and a first input switch M7. The fifth switch M5are coupled to the first pre-charge switch PRE1, the second pre-charge switch PRE2, a second control switch CSW2, and a second input switch M8. In some embodiments, the fourth switch M4is coupled to the power supply, the third switch M3, and the first pre-charge switch PRE1. In some embodiments, the sixth switch M6is coupled to the power supply, the fifth switch M5, and the second pre-charge switch PRE2. In some embodiments, the first pre-charge switch PRE1is coupled to the first data line DL and the first input switch M7. In some embodiments, the second pre-charge switch PRE2is coupled to the second data line DLB and the second input switch M8. In some embodiments, the drain node (i.e., the first output node) Q of the fourth switch M4(or the drain node Q of the third switch M3) is connected to the gate node of the fifth switch M5and the gate node of the sixth switch M6. Similarly, the drain node (i.e., the second output node) QB of the sixth switch M6(or the drain node Q of the fifth switch M5) is connected to the gate node of the third switch M3and the gate node of the fourth switch M4. In some embodiments, a gate node of the first pre-charge PRE1is coupled to a gate node of the first control switch CSW1. A gate node of the second pre-charge PRE2is coupled to a gate node of the second control switch CSW2. In some embodiments, the source node of the third switch M3is coupled to the first input node N1and the source node of the fifth switch M5is coupled to the second input node N2.

In some embodiments, the controller determines whether the first bit line voltage is transmitted through the control line SAE to the first input node N1by a voltage level of the select signal SAE. In some embodiments, the controller determines whether the second bit line voltage is transmitted through the control line SAE to the second input node N2by the voltage level of the select signal SAE.

In some embodiments, the voltage level of the first input voltage VIN of the first input node N1is complementary to an output voltage of the first output node Q of the third switch M3(and/or the first pre-charge switch PRE1). The voltage level of the second input voltage VIN of the second input node N1is the same as an output voltage of the second output node QB of the fifth switch M5(and/or the second pre-charge switch PRE2). In alternative embodiments, the voltage level of the first input voltage VIN of the first input node N1is the same as an output voltage of the first output node Q of the third switch M3(and/or the first pre-charge switch PRE1). The voltage level of the second input voltage VIN of the second input node N1is complementary to an output voltage of the second output node QB of the fifth switch M5(and/or the second pre-charge switch PRE2).

In some embodiments, the first input switch M7and the second input switch M8respectively receive the first bit line voltage and the second bit line voltage from the plurality of bit lines selected by the column decoder.

In some embodiments, the voltage difference between the first input switch M7and the second input switch M8is detected by the sense amplifier200when the voltage difference reaches a predetermined voltage difference.

In some embodiments, the first control switch CSW1receives the select signal SAE through the gate node of the first control switch CSW1from the controller and receives the first bit line voltage through a drain node of the first control switch CSW1. In some embodiments, the second control switch CSW2receives the select signal SAE through the gate node of the second control switch CSW2from the controller and receives the second bit line voltage through a drain node of the second control switch CSW2. In some embodiments, the pull-down switch PD receives the select signal SAE through the gate node of the pull-down switch PD from the controller.

In some embodiments, the first pre-charge switch PRE1transfers the first bit line voltage to a drain node (or the first output node Q) of the third switch M3. The second pre-charge switch PRE1transfers the second bit line voltage to a drain node (or the second output node QB) of the fifth switch M5.

In accordance with some embodiments of the disclosure, a voltage level of the source node of the third switch M3(or the first input node N1) and a voltage level of the source node of the fifth switch M5(or the second input node N2) are respectively pre-charged to a first voltage level (for example, logic “0”) and a second voltage level (for example, logic “1”). The first voltage level is complementary to the second voltage level. In some embodiments, the voltage level of the source node of the third switch M3and a voltage level of the source node of the fifth switch M5are respectively pre-charged to the first voltage level (for example, logic “1”) and the second voltage level (for example, logic “0”).

Referring toFIG.3AandFIG.3B, the time frame between the time t1and the time t3is the bit-line developing period. The time frame between the time t2and the time t3is the is the offset detecting period. The time frame between the time t3and the time t4is the is the sensing period, and the sense amplifier circuit is enabled by the select signal SAE at this period.

The word line address is selected during the period from the time t1to the time t3. The voltage level of the first data line DL and the voltage level of the second data line DLB is charged at the same logic level (e.g., logic “1”) before the time t1. The voltage level of the first output node Q and the voltage level of the second output node QB is charged at the same logic level (e.g., logic “1”) before the time t1. The voltage level of the first input node N1is the same as the voltage level of second input node N2(e.g., logic “1”) before the time t1.

The voltage level of the first input node N1is pre-charged by a first output voltage of the first output node Q according to the first input voltage VIN of the first input node N1while the control line CL is received the select signal SAE during the early stage of the bit-line developing period. The voltage level of the second input node N2is pre-charged by a first output voltage of the second output node QB according to the second input voltage VIN′ of the second input node N2while the control line CL is received the select signal SAE during the early stage of the bit-line developing period. The voltage level of the first output node Q is the same as the first input voltage VIN of a first input node N1. The voltage level of the second output node QB is the same as the second input voltage VIN of the second input node N2.

The voltage difference (or offset) DV between the first input voltage VIN of the first input node N1and the second input voltage VIN′ of the second input node N2is large enough at a predetermined value to be sensed after the time t2.

After the time t1, the voltage level of the first data line, the voltage level of the first output node Q, and the voltage level of the first input node N1decline gradually following along a first slope.

After the time t3, the voltage level of the first data line rises gradually following along a second slope, however, the voltage level of the first output node Q and the voltage level of the first input node N1declines following along a third slope due to the pull-down circuit PD is enabled. The third slope is larger (or steep) than the first slope.

From the time t3to the time t3′, the voltage level of the first output node Q, the second output node QB, and the voltage level of the first input node N1remain unchanged. However, the voltage level of the second input node N2declines (or decreases) gradually following along a fourth slope. The forth slope is substantially equal to the third slope. In contrast, the voltage level of the second output node QB and the voltage level of the second input node N2remain unchanged from the time t1to the time t3.

The voltage difference (or offset) DV between the first input voltage VIN of the first input node N1and the second input voltage VIN′ of the second input node N2is large enough at a predetermined value to be sensed after the time t2.

The voltage difference DV between the first input node N1and the second input node N2which shows the latching behavior is kept at the fixed value in the early stage of the offset detecting period from the time t2to the time t3and then gradually decreases in the later stage of the offset detecting period. It is noted that the waveform of the voltage difference DV will not crossover from the time t1to the time t3due to the device mismatch. That is, the sense amplifier circuit will not suffer from the influence of the device mismatch and is able to enhance the sensing speed of the sense amplifier circuit300.

FIG.4Ais another schematic diagram of a sense amplifier circuit as shown inFIG.1Ain accordance with some embodiments.FIG.4Bis a timing diagram of the sense amplifier circuit shown inFIG.4Ain the operation process according to some embodiments of the present disclosure.

Referring toFIG.4AandFIG.4B, the memory circuit with the sense amplifier circuit includes the differential amplifier, the first switch, the second switch, the matching capacitor CAP, the first control switch CSW1, and the second control switch CSW2. The differential amplifier includes an inverter pair, a pull-down switch PD, a first input switch M7and a second input switch M8. The inverter pair includes a third switch M3, a fourth switch M4, a fifth switch M5, and a sixth switch M6. The third switch M3are coupled to the first pre-charge switch PRE1, the first control switch, and a first input switch M7. The fifth switch M5are coupled to the first pre-charge switch PRE1, the second pre-charge switch PRE2, a second control switch CSW2, and a second input switch M8. In some embodiments, the fourth switch M4is coupled to the power supply, the third switch M3, and the first pre-charge switch PRE1. In some embodiments, the sixth switch M6is coupled to the power supply, the fifth switch M5, and the second pre-charge switch PRE2. In some embodiments, the first pre-charge switch PRE1is coupled to the first data line DL and the first input switch M7. In some embodiments, the second pre-charge switch PRE2is coupled to the second data line DLB and the second input switch M8. In some embodiments, the drain node (i.e., the first output node) Q of the fourth switch M4(or the drain node Q of the third switch M3) is connected to the gate node of the fifth switch M5and the gate node of the sixth switch M6. Similarly, the drain node (i.e., the second output node) QB of the sixth switch M6(or the drain node Q of the fifth switch M5) is connected to the gate node of the third switch M3and the gate node of the fourth switch M4. In some embodiments, a gate node of the first pre-charge PRE1is coupled to a gate node of the first control switch CSW1. A gate node of the second pre-charge PRE2is coupled to a gate node of the second control switch CSW2. In some embodiments, the source node of the third switch M3is coupled to the first input node N1and the source node of the fifth switch M5is coupled to the second input node N2.

In some embodiments, the matching capacitor CAP is coupled to the drain node of the first input switch M7, the drain node of the first pre-charge switch PRE1, the drain node of the second pre-charge switch PRE2, the second input switch M8, the first input node N1, the second input node N2, the source node of the third switch M3, and the source node of the fifth switch M5. By analogy, the function of the components may also be represented in a manner similar toFIG.3A.

In some embodiments, the matching capacitor CAP is used to keep a voltage difference DV between the first input voltage VIN of the first input node N1and the second input voltage VIN′ of the second input node N2at a fixed value during a sensing period.

In some embodiments, the first switch includes a first pre-charge switch PRE1and a first control switch CSW1. The first control switch CSW1is enabled when the select signal SAE is enabled and a gate node voltage of the first pre-charge switch PRE1is at logic low. In some embodiments, the second switch includes a second pre-charge switch PRE2and a second control switch CSW2. The second control switch CSW2is enabled when the select signal SAE is enabled and a gate node voltage of the second pre-charge switch PRE2is at logic low.

In some embodiments, the voltage difference DV between the first input voltage VIN of the first input node N1and the second input voltage VIN′ of the second input node N2will be kept at a fixed value by the matching capacitor CAP during the positive feedback amplify period (i.e., from the time t1to the time t3), and becomes smaller than the fixed value after the sensing period (i.e., after the time t3).

Referring toFIG.2A,FIG.4AandFIG.4B, the time frame between the time t1and the time t3is the bit-line developing period. The time frame between the time t2and the time t3is the offset detecting period. The time frame between the time t3and the time t4is the sensing period, and the sense amplifier circuit is enabled by the select signal SAE at this period.

The word line address is selected during the period from the time t1to the time t3. The voltage level of the first data line DL and the voltage level of the second data line DLB is charged at the same logic level (e.g., logic “1”) before the time t1. The voltage level of the first output node Q and the voltage level of the second output node QB is charged at the same logic level (e.g., logic “1”) before the time t1. The voltage level of the first input node N1is the same as the voltage level of second input node N2(e.g., logic “1”) before the time t1.

The voltage level of the first input node N1is pre-charged by a first output voltage of the first output node Q according to the first input voltage VIN of the first input node N1while the control line CL is received the select signal SAE during the early stage of the bit-line developing period. The voltage level of the second input node N2is pre-charged by a first output voltage of the second output node QB according to the second input voltage VIN′ of the second input node N2while the control line CL is received the select signal SAE during the early stage of the bit-line developing period. The voltage level of the first output node Q is the same as the first input voltage VIN of a first input node N1. The voltage level of the second output node QB is the same as the second input voltage VIN of the second input node N2.

After the time t1, the voltage level of the first data line, the voltage level of the first output node Q, and the voltage level of the first input node N1decline gradually following along a first slope.

After the time t3, the voltage level of the first data line rises gradually following along a second slope, however, the voltage level of the first output node Q and the voltage level of the first input node N1declines following along a third slope due to the pull-down circuit PD is enabled. The third slope is larger (or steep) than the first slope.

From the time t3to the time t3′, the voltage level of the first output node Q, the second output node QB, and the voltage level of the first input node N1remain unchanged. However, the voltage level of the second input node N2declines (or decreases) gradually following along a fourth slope. The forth slope is substantially equal to the third slope. In contrast, the voltage level of the second output node QB and the voltage level of the second input node N2remain unchanged from the time t1to the time t3.

The voltage difference (or offset) DV between the first input voltage VIN of the first input node N1and the second input voltage VIN′ of the second input node N2is large enough at a predetermined value to be sensed after the time t2.

The voltage difference DV between the first input node N1and the second input node N2which shows the latching behavior is kept at the fixed value from the time t2to the time t3and then gradually declines from the time t3to the time t3′. It is noted that the waveform of the voltage difference DV will not crossover from the time t1to the time t4. That is, the sense amplifier circuit will not suffer from the influence of the device mismatch and is able to enhance the sensing speed of the sense amplifier circuit400. Furthermore, the time that the voltage difference DV is kept with the matching capacitor CAP in the sense amplifier400is longer than the time that the voltage difference DV is kept without the matching capacitor CAP.

In some embodiments, a sensing method of a sense amplifier circuit400includes: receiving a first input voltage VIN of a first input node N1from a first data line and a second input voltage VIN′ of a second input node N2from a second data line DLB; pre-charging the first input node N1by a first output voltage of a first output node Q while a control line CL is received a select signal SAE where the sense amplifier circuit is enabled by the select signal SAE and pre-charging a second input node N2by a second output voltage of the second output node QB while the control line CL is received the select signal SAE where the sense amplifier circuit400is enabled by the select signal SAE, wherein a voltage level of the first output node Q is the same as the first input voltage VIN of a first input node N1; discharging the first input voltage VIN of the first input node N1and the second input voltage VIN′ of the second input node N2by a pull-down circuit PD; keeping a voltage difference DV between the first input voltage VIN of the first input node N1and the second input voltage VIN′ of the second input node N2at a fixed value by a matching capacitor CAP of the sense amplifier circuit400during a sensing period; amplifying a voltage difference DV of the first output node Q and the second output node QB according to the first input voltage VIN of the first input node N1and the second input voltage VIN′ of the second input node N2; and outputting a sensing voltage at an output node of the sense amplifier circuit400.

During a read operation, the access transistor is enabled as well, and the bit line BL being pre-charged may be pulled up or pulled down according to a charge state of the storage capacitor. In specific, a word line WL coupled to the selected memory cell is asserted, then the pre-charged bit lines BL are further pulled up or pulled down by the storage capacitors of the memory cells coupled to the asserted word line WL, respectively. By comparing the voltage variation of the bit line BL coupled to the selected memory cell with a reference voltage, the charge state of the storage capacitor can be sensed, and the logic state of the memory cell can be identified. By virtue of pulling up/down the pre-charged bit lines BL, the charges stored in the storage capacitors of the memory cells coupled to the asserted word line WL are altered. In order to restore logic states of these memory cells, the read operation may be followed by a write operation for programming the previous logic states to these memory cells, and such write operation may also be referred as a refresh operation.

The memory arrays are routed to the memory control circuit or memory controller lying under the memory arrays. Although not shown, the word lines of the memory array may be routed to the underlying memory controller as well. The memory controller is formed on a surface of a semiconductor substrate (e.g., core die), while the memory arrays are embedded in a stack of interlayer dielectric layers lying over the memory controller.

According to different design needs, the memory control circuit and/or a block of the memory controller may be implemented in the form of hardware, firmware, software (i.e., a program), or a combination of the majority of the foregoing three.

In the form of hardware, the memory control circuit and/or the block of the memory controller may be implemented in the form of a logic circuit on an integrated circuit. Related functions of the memory control circuit and/or the memory controller may be implemented as hardware through using hardware description languages (e.g., Verilog HDL or VHDL) or other suitable programming languages. For instance, the related functions of the memory control circuit and/or the memory controller may be implemented in one or a plurality of controllers, a micro controller, a micro-processor, an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), and/or various logic blocks, modules, and circuits in other processing units.

In the form of software and/or firmware, the related functions of the memory control circuit and/or the memory controller may be implemented as programming codes. For instance, the memory control circuit and/or the memory controller may be implemented by using a general programming language (e.g., C, C++, or an assembly language) or other suitable programming languages. The programming code may be recorded/stored in a recording medium. In some embodiments, the recording medium includes, for example, read only memory (ROM), random access memory (RAM), and/or a storage device. The storage device includes a hard disk drive (HDD) a solid-state drive (SSD), or other storage devices. In some other embodiments, the recording medium may include a “non-transitory computer readable medium”. For instance, a tape, a disk, a card, semiconductor memory, a programmable logic circuit, etc. may be used to be implemented as the non-transitory computer readable medium. A computer, a central processing unit (CPU), a controller, a micro controller, or a micro-processor may read and execute the programming code from the recording medium to accomplish the related functions of the memory control circuit and/or the memory controller. Further, the programming code may also be provided to the computer (or CPU) through any transmission medium (a communication network or a broadcast wave, etc.). The communication network includes, for example, Internet, a wired communication network, a wireless communication network, or other communication media.

The memory controller includes sense amplifiers. The sense amplifiers are configured to facilitate read operations. Each sense amplifier may include two inputs. One of the inputs is coupled to a bit line from the memory array, while the other input is coupled to a bit line from the memory array. During a read operation, both bit lines coupled to the inputs of a sense amplifier are pre-charged to a pre-charging voltage, and one of these bit lines would be further pulled up or pulled down by the storage capacitor in a selected memory cell, while the other bit line still holds at the pre-charging voltage. The sense amplifier is configured to output the logic state of the selected memory cell by comparing the voltage on the bit line coupled to the selected memory cell with the pre-charging voltage held by the other bit line. For instance, when a memory cell in the memory array is selected for a read operation, the bit lines from the memory arrays are pre-charged to a pre-charging voltage. Further, the word line coupled to the selected memory cell is asserted, and the bit line coupled to the selected memory cell is further pulled up or pulled down by the storage capacitor in the selected memory cell. The bit line being further pulled up/down is coupled to an input of one of the sense amplifiers, and another input of this sense amplifier is coupled to a bit line from the memory array. During such read operation, none of the word lines in the memory array is asserted, thus the bit line BL from the memory array is prevented from being further pulled up/down, thus still holds at the pre-charging voltage. This sense amplifier compares the voltage at the bit line BL coupled to the selected memory cell with the pre-charging voltage held by the bit line BL, and identify the logic state of the selected memory cell.

As described above, the sense amplifier circuit in the memory circuit is able to achieve faster read speed. Further, the sense amplifier circuit with a matching capacitor is able to keep the voltage difference, thus the waveform of the voltage difference will not crossover during the positive feedback amplify period due to the device mismatch. Consequently, interference between the adjacent voltages across the matching capacitor in the memory circuits with the sense amplifier circuit can be prevented. That is, the sense amplifier circuit will not suffer from the influence of the device mismatch and easily improves the sensing speed of the sense amplifier circuit in the present application.

As compared to the sense amplifier circuit at the same circuit area that does not have a matching capacitor, the small offset voltage is achieved in the present application.

In some embodiments, the sense amplifier circuit includes a differential amplifier, comprising a first input node, a second input node, a first output node and a second output node, wherein the differential amplifier amplifies a voltage difference of the first output node and the second output node according to a first input voltage of the first input node and a second input voltage of the second input node; a first switch, wherein a control node of the first switch is coupled to a control line, a first node of the first switch is coupled to the first input node, and a second node of the first switch is coupled to the first output node, the first switch is configured to pre-charge the first input node by a first output voltage of the first output node while the control line is received a select signal where the sense amplifier circuit is enabled by the select signal; and a second switch, wherein a control node of the second switch is coupled to the control line, a first node of the second switch is coupled to the second input node, and a second node of the second switch is coupled to the second output node, the second switch is configured to pre-charge the second input node by a second output voltage of the second output node while the control line is received the select signal where the sense amplifier circuit is enabled by the select signal.

In some embodiments, a memory circuit includes a first input node, a second input node, a first output node and a second output node, wherein the differential amplifier amplifies a voltage difference of the first output node and the second output node according to a first input voltage of the first input node and a second input voltage of the second input node; a first switch, wherein a control node of the first switch is coupled to a control line, a first node of the first switch is coupled to the first input node, and a second node of the first switch is coupled to the first output node, the first switch is configured to pre-charge the first input node by a first output voltage of the first output node while the control line is received a select signal where the sense amplifier circuit is enabled by the select signal; and a second switch, wherein a control node of the second switch is coupled to a control line, a first node of the second switch is coupled to the second input nod, and a second node of the second switch is coupled to the second output node, the second switch is configured to pre-charge the second input node by a second output voltage of the second output node while the control line is received the select signal where the sense amplifier circuit is enabled by the select signal; and a matching capacitor, coupled to the first switch and the second switch, wherein the matching capacitor is configured to keep a voltage difference between the first input voltage of the first input node and the second input voltage of the second input node at a fixed value during a sensing period.

In some embodiments, In some embodiments, a sensing method of a sense amplifier circuit includes: receiving a first input voltage of a first input node from a first data line and a second input voltage of a second input node from a second data line; pre-charging the first input node by a first output voltage of a first output node while a control line is received a select signal where the sense amplifier circuit is enabled by the select signal and pre-charging a second input node by a second output voltage of the second output node while the control line is received the select signal where the sense amplifier circuit is enabled by the select signal, wherein a voltage level of the first output node is the same as the first input voltage of a first input node; discharging the first input voltage of the first input node and the second input voltage of the second input node by a pull-down circuit; keeping a voltage difference between the first input voltage of the first input node and the second input voltage of the second input node at a fixed value by a matching capacitor of the sense amplifier circuit during a sensing period; amplifying a voltage difference of the first output node and the second output node according to the first input voltage of the first input node and the second input voltage of the second input node; and outputting a sensing voltage at an output node of the sense amplifier circuit.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.