Patent ID: 12207458

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

DETAILED DESCRIPTION

The methods and apparatus enable three-dimensional (3D) dynamic random-access memory (DRAM) cells that use economical materials and process methods to produce memory arrays which can meet a D1d memory density of approximately 1300 um2per Megabit and beyond. Two-dimensional (2D) DRAM scaling is getting very difficult to manufacture and the cost is constantly increasing. Below the D1d DRAM node, the feature size will be so small that even self-aligned quadruple patterning (SAQP) will no longer be a viable option. Even if extreme ultraviolet (EUV) lithography is adopted, the EUV lithography will still need to be at least self-aligned double patterning (SADP), if not SAQP at most levels. Although 3D DRAM is a concept that is has been investigated widely in the DRAM industry for D1d and beyond, proposed solutions with different cell structures cannot be processed with economical materials and processes at the dimensions needed to reach memory density comparable to 2D DRAM.

The methods and apparatus of the present principles provide a 3D DRAM cell interconnection architecture that enables low bitline capacitance, integrated fin field-effect transistor's (FinFET) for sense amplifier circuitry, and hierarchical connections for bitlines to reduce the parasitic capacitance and resistance-capacitance (RC) delay response to surpass 2D DRAM capabilities. The present principles leverage vertical wordlines formed from alternating layers of silicon (Si) and silicon germanium (SiGe) to enable the following architecture features. In some embodiments, the vertical wordline access device structure may be used to create a switch to connect or disconnect a local bitline to a global bitline, and, in some cases, connect or disconnect the global bitline to a sense amplifier. In some embodiments, the vertical wordline access device structure may be used to create a switch to connect or disconnect a local bitline on an opposite end of a global bitline to short all local bitlines in a tier stack together and connect the local bitlines to bitline reference voltages, also known as the bitline EQ or bitline equilibrate.

The techniques of the present principles eliminate the need (and space) for staircase contact points by using an L-pad formation, allowing top level contacts with minimal surface area usage. The L-pad formation begins with a hole in a substrate at least as deep as a memory array and wider on all sides than the memory array by at least the tier stack thickness. The tier stack layers of alternating Si/SiGe are epitaxially grown on the sidewall as well as the bottom of the memory array. After deposition of the Si/SiGe layers, the Si/SiGe layers are planarized back to the original silicon surface. The planarization is performed such that the planarization stops below the original silicon height. Only a small width of the sidewall Si/SiGe stack is used for the interconnect to the memory array and forms the global bitline.

The techniques of the present principles may also be used to form ancillary structures such as FinFET structures in the sidewall portions of the Si/SiGe layers. After planarization, the Si/SiGe layers appear as alternating lines parallel to the array. The SiGe layers are recessed selectively to the Si layers to form Si fins of the FinFET. In some embodiments, some of the fins are removed and other fins are narrowed to a desired thickness. The formation of the FinFET structures allows creation of complementary metal-oxide-semiconductor (CMOS) sense amplifiers inside, for example, a 50 nm pitch staircase compared to conventional methods which require a 400 nm pitch staircase and sense amplifiers to be built outside of the memory array area.

In a top-down view100ofFIG.1, several 3D DRAM cell groups102are depicted. A first 3D DRAM cell group104has been formed in a gap between a first silicon wall106and a second silicon wall108created by a silicon substrate etch for the array Si/SiGe deposition. A plurality of 3D DRAM cells110with vertical wordlines formed from a plurality of crystalline Si and SiGe layers are formed along with a stack of horizontal bitlines112for the 3D DRAM cells110. Adjacent to the plurality of 3D DRAM cells110is a layer access area114used to connect to the plurality of 3D DRAM cells110and to the stack of horizontal bitlines112. In a view200ofFIG.2, a cross-section of the 3D DRAM cell groups102on a substrate202is depicted. Si layers204alternate with SiGe layers206both horizontally (in the areas of the plurality of 3D DRAM cells110) and vertically (in the layer access area114). The L-pad formation, formed by the alternating layers created between the silicon walls, presents a starting structure that can be formed into vertical wordlines, bitlines, contact points, and FinFETs and the like.

In the top-down view300ofFIG.3, a hierarchical bitline architecture is formed using the L-pad formation. A sidewall330of the first silicon wall106is adjacent to the layer access area114. The plurality of 3D DRAM cells110and the stack of horizontal bitlines112are depicted figuratively to better illustrate the switchable connections between the structures. A global bitline access area302has been formed by etching trenches304into the layer access area114to create an electrically isolated area of the layer access area114that runs from the sidewall330of the first silicon wall106to a stack of global bitlines306. The global bitline access area302is further formed by fully etching the SiGe layers from one or both sides in the isolation cuts (trenches304) and replacing the removed SiGe gaps with dielectric material. The dielectric material provides isolation between the bitline metal layers formed next. The global bitline access area302is then further formed by selectively etching the global bitline access area302from one or both sides in the trenches304to replace the Si material with a metal material to form bitline metal layers in the global bitline access area302to provide bitline connectivity to the layers of the 3D DRAM cells. The stack of global bitlines306is formed between the layer access area114and the 3D DRAM cells110. A bitline EQ308is formed adjacent to the 3D DRAM cells110on a side opposite of the stack of global bitlines306. A local bitline switch310may be formed using a vertical wordline gate switch to control the bitline connection to only a single local bitline of 3D DRAM cells314, dramatically reducing the bitline length and the bitline resistance and capacitance.

Each of the stack of 3D DRAM cells314has a wordline switch316to gate the access device of each cell so that one stack of memory locations may be accessed to the stack of horizontal bitlines112. As an example, a local bitline switch310has been activated318allowing a read or write on a stack of 3D DRAM cells314B. A wordline switch316has been activated320, allowing access to the local bitline to read or write the cell bit value as required. Only the stack of local bitlines on an active wordline is activated to connect the activated stack of local bitlines328to the stack of global bitlines306. The bitline tier stack deposited on the sidewall of the silicon forms a planar connection point of the stack of global bitlines306. The bitline tier stack is isolated on either side by a combination of holes, slits, or slot etched features with a lateral recess to form a supported wall of narrow bitline (global bitline access area302). The inventor has found that the estimated total bitline RC and bitline capacitance is comparable to that of 2D DRAM for even higher density of 3D DRAM. The bitline EQ308also has a series of bitline EQ switches322that may be activated individually or all together to equalize the stack of global bitlines306.

As an example, the global bitline access area302may formed with 96 bitline metal layers that may be connected to 96 sense amplifiers. The bitline metal layers run vertically down along the sidewall330of the first silicon wall106and then horizontally towards the stack of global bitlines306. The stack of global bitlines306runs horizontal and consists of the same 96 layers of bitlines in the global bitline access area302where the stack of bitlines run vertically up the first silicon wall106to be individually accessed from the top surface. Each local bitline switch310would control access to an entire tier (96layers) of the stack of local bitlines for each grouping312of 3D DRAM cells314. When a local bitline switch310is activated, only the stack of 96 local bitlines in a grouping312would be accessible by the 96 bitline metal layers. Using the approach, a sense amplifier connected to one of the 96 bitline metal layers can be used to access different cell locations without the substantial additional resistance and capacitance of the local bitlines in the non-accessed cell locations (the non-activated local bitlines). Because only the global bitline access area302is needed to access the 3D DRAM cells, the remaining portions324,326of the layer access area114may be used to form ancillary structures such as FinFETs for sense amplifiers and the like, dramatically reducing the required surface area for the 3D DRAM and supporting circuits. The formation of the L-pad areas, vertical wordline structures, bitline structures, and development of the layer access area114for FinFET structures are discussed in more detail below.

In some embodiments, a method of the present principles uses a stack of alternating crystalline Si/SiGe layers402to form different structures using high aspect ratio (HAR) etching of a pattern of holes as depicted in a top-down view400ofFIG.4. For example, a first hole type404may be used to form a first structure and a second hole type408may be used to form a second structure. A third hole type410in an example is used to construct a switch by using a transistor formed during the creating of a vertical wordline. In a similar fashion, a slit406may be used form a third structure and so forth (e.g., a bitline). In the top-down view500ofFIG.5, a version of a 3D DRAM cell layout uses the vertical wordline access transistor502,504to connect or disconnect a local bitline506,508to the global bitline510. In a similar fashion, other vertical wordline access transistors can be used to connect local bitlines or the global bitlines to the bitline EQ. The bitline slit creates a metal contact to the silicon (metal to source/drain of the vertical wordline transistor). The bitline is placed to coincide with the source/drain region created at the edge of wordline cell to connect the channels.

FIG.6is a method600of L-pad formation for 3D DRAM. References to the cross-sectional views700A-D ofFIG.7will assist in describing the method600. In block602, a substrate702of silicon is formed as depicted in cross-sectional view700A. A thickness704of the silicon may vary based upon a desired height of silicon wall used for the L-pad formation. In block604, the substrate702is etched to form a first silicon wall706and a second silicon wall708as depicted in the cross-sectional view700B. Any number of silicon walls may be formed during the process and the illustration of two silicon walls is for the sake of brevity. A wall height710is selected based on the number of alternating Si/SiGe layers desired for the 3D DRAM cell structures. In some embodiments, a thickness720of a sidewall may be approximately 2 microns to approximately 3 microns. The inventor has found that the thickness should be sufficient such that the silicon wall does not bend or collapse for a given height. In some embodiments, the wall height710is approximately 10 microns. In some embodiments, the wall height710is approximately 2 microns to approximately 20 microns. In some embodiments, a spacing distance722between the first silicon wall706and the second silicon wall708is approximately 60 microns. The spacing is selected to be twice the length of the single local bitline to meet bitline parasitic requirements.

In block606, crystalline Si layers712and crystalline SiGe layers714are alternately epitaxially deposited over the substrate702, including the first silicon wall706and the second silicon wall708as depicted in the cross-sectional view700C. In block608, a chemical mechanical polishing (CMP) stop layer716is deposited on the substrate702as shown in the cross-sectional view700C. In block610, the substrate702is planarized below the wall height710to a second sidewall height718as depicted in the cross-sectional view700D. Because the crystalline Si layers712and the crystalline SiGe layers714run horizontally and then vertically up a first sidewall730of the first silicon wall706and up a second sidewall732of the second silicon wall708, the crystalline Si layers712and the crystalline SiGe layers714form an “L” shape or an “L-pad.” Different portions of the L-pad formation802may be used for different 3D DRAM structures as depicted in a cross-sectional view800ofFIG.8. In some embodiments, a horizontal portion804is used to form 3D DRAM cell structures such as vertical wordline structures and the like (seeFIGS.22and23). In some embodiments, the L-shaped portions806may be used for a global bitline access area and/or for forming fins for FinFETs and the like for sense amplifiers. By using the L-pad formation along with the hole patterning process, 3D DRAM cells and ancillary support structures such as sense amplifiers can be economically produced on the same scale or less than 2D DRAM.

As the formation of the vertical wordline structures are discussed below (FIGS.22and23), the processes for forming the fins for the FinFETs are presently discussed. As an example process, a first portion902of the L-pad to the left of the global bitline access area906and a second portion904of the L-pad to the right of the global bitline access area906may be processed to produce FinFETs for sense amplifiers and the like as depicted in the top-down view900ofFIG.9. In a cross-sectional view1000ofFIG.10, the sideview of the first portion902or the second portion904is depicted. The sidewall330of the first silicon wall106is positioned oriented to the left with the vertical portions of the Si layers1004and the SiGe layers1002oriented to the right. In some embodiments, a first width1006of the SiGe layers1002is approximately 10 nm and a second width1008of the Si layers1004is approximately 30 nm.

FIG.11is a method1100of forming FinFET structures in an L-pad formation. In block1102, the L-pad structure is created as described above. In some embodiments, memory structures such as, for example, the global bitline access area are also formed, leaving portions of the L-pad formation for use by ancillary structures for the memory cells. The method1100forms fins of FinFET structures without requiring self-aligned double patterning (SADP) while providing a well-controlled profile and fin thickness. The method1100allows formation of FinFETs with one, two, three, or four or more fins with isolation between the transistors. In block1104, the SiGe layers1002are selectively etched (over the Si layers1004) to remove a first portion of the SiGe layers1002as depicted in a cross-sectional view1200ofFIG.12. In block1106, the Si layers1004are selective etched (over the SiGe layers1002) to remove a first portion of the Si layers1004which forms narrow fins1302on the Si layers1004as depicted in a cross-sectional view1300ofFIG.13. In some embodiments, the narrow fins1302are approximately 10 nm to approximately 12 nm in width1304. Narrowing of the FinFET before isolation allows for wider silicon to support the narrow fins1302during a subsequent shallow trench isolation (STI) formation.

In some embodiments, the gap1306from the SiGe layers1002starts at approximately 10 nm and after the Si etching, the gap1306increases as the Si layers1004are etched to approximately 12 nm and a gap width of approximately 28 nm. In some embodiments, during subsequent processing, the silicon-based fins will be reduced in width further through oxidative loss in a gate pre-clean process and interlayer treatment to be approximately 10 nm in width1304. In block1108, an oxide liner1402is deposited and densified on the substrate as depicted in a cross-sectional view1400inFIG.14. In some embodiments, the oxide liner1402has a thickness1404of approximately 6 nm. In block1110, STI patterning (not shown) covers the active areas1504and fins, which will become isolation regions, and portions1502of the oxide liner1402are then removed as depicted in a cross-sectional view1500ofFIG.15. In some embodiments, the STI patterning remains in place to protect gaps of the active area fins. In block1112, portions of the Si layers1004and SiGe layers1002exposed after etching the oxide liner1402are etched to form STI areas1602as depicted in a cross-sectional view1600ofFIG.16. In block1114, oxide liner1402to is partially etched to remove vertical oxide liner portions1604as depicted in a cross-sectional view1700ofFIG.17. In some embodiments, the vertical oxide liner portions1604are removed by using a hydrogen fluoride (HF) clean. In block1116, a chemical oxide layer1802is formed on Si and SiGe exposed surfaces within the STI areas1602as depicted in a cross-sectional view1800ofFIG.18. In some embodiments, the chemical oxide layer1802has a thickness1804of approximately 3 nm.

In block1118, oxide is deposited in the STI areas1602to increase a thickness1902of the oxide liner1402as depicted in a cross-sectional view1900ofFIG.19. In some embodiments, approximately 3 nm of oxide is deposited to partially fill the STI areas1602. In some embodiments, the thickness1902may be approximately 6 nm (approximately 3 nm due to chemical oxide formation and approximately 3 nm from oxide deposition). In block1120, nitride is deposited in the unfilled portions1904of the STI areas1602to form nitride plugs2002as depicted in a view2000ofFIG.20. In some embodiments, the nitride plugs2002have a width2004of approximately 10 nm. In some embodiments, the STI patterning (not shown) is then removed. In block1122, the oxide liner1402is etched back, exposing a portion of the nitride plugs2002while leaving portions of the oxide liner1402in the STI areas1602as depicted in a cross-sectional view2100ofFIG.21. In some embodiments, thermal or in-situ steam generated (ISSG) oxidation processes can be used to etch the STI areas1602slower than the deposited liner oxide giving a desired tapered profile for gate etch and electric-field for gate-induced drain leakage (GIDL). The FinFET formation can now be completed using conventional techniques by one skilled in the art which are not described herein for the sake of brevity.

In some embodiments, a portion of the horizontal portion804ofFIG.8is used to form 3D DRAM cell structures such as vertical wordline structures and the like.FIG.22depicts such a vertical wordline structure in an isometric view2200in accordance with some embodiments. A capacitor section2212is connected to a wordline feature section2214which connects with a horizontal bitline feature section2216. The capacitor section2212has lower electrode2250and a top electrode2252. The wordline feature section2214includes two source/drain regions2210. A cut line2202is shown in an isometric view2300ofFIG.23to illustrate the internal structure of the 3D DRAM structure through the wordline feature. The wordline hole2204is central to a channel and forms two gate all around (GAA) channels2302in each intersection of the vertical wordline feature2306and the horizontal bitline feature2208. The vertical wordline features2306are separated by isolation features2304. As the processes described above for formation of the wordline feature are performed, the GAA channels2302are also formed.

In some embodiments, the vertical wordline transistors may be used as switches to enable the hierarchical bitline architecture as described above. The wordline hole2204with the two GAA channels is used for connecting and/or disconnecting the source/drain to source/drain for each 3D DRAM tier for bitline to global bitline, bitline to bitline EQ and/or global bitline to bitline EQ to enable the hierarchical bitline architecture. The vertical wordline structures and connected structures may be formed using the same high aspect ratio etching holes described above forFIG.4and the like. Basically, holes808are patterned into the alternating crystalline Si and crystalline SiGe epitaxially grown layers of the L-pad in the horizontal portion804. The holes808may then be expanded into slots or slits as needed or lateral etching may be used to selectively open up channels in the SiGe layers and the various features of the vertical wordline, capacitor, or bitline may be formed using atomic layer deposition or chemical vapor deposition techniques as shown inFIGS.22and23.

Embodiments in accordance with the present principles may be implemented in hardware, firmware, software, or any combination thereof. Embodiments may also be implemented as instructions stored using one or more computer readable media, which may be read and executed by one or more processors. A computer readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing platform or a “virtual machine” running on one or more computing platforms). For example, a computer readable medium may include any suitable form of volatile or non-volatile memory. In some embodiments, the computer readable media may include a non-transitory computer readable medium.

While the foregoing is directed to embodiments of the present principles, other and further embodiments of the principles may be devised without departing from the basic scope thereof.