Patent ID: 12191409

DESCRIPTION OF EMBODIMENTS

Embodiments described below with reference to the accompanying drawings are illustrative and are only intended to explain the present disclosure and not to be interpreted as a limitation on the present disclosure.

An interdigitated back contact solar cell is also referred to as an IBC solar cell. It is an urgent technical problem to improve the efficiency of the IBC solar cell while effectively separating a boron-doped region and a phosphorus-doped region of the IBC solar cell.

In order to solve the above technical problem, an embodiment of the present disclosure provides a solar cell. The solar cell is an IBC solar cell. As shown inFIG.1-1,FIG.1-2orFIG.1-3, the solar cell at least includes a substrate1, a first conductive layer6, a second conductive layer7, a first electrode8, and a second electrode9.

The substrate1has a front surface2and a back surface3opposite to the front surface2. The front surface2is a light receiving surface facing the direction of sunlight, and the back surface3is a surface opposite to the front surface2.

The substrate1may be, for example, a crystalline semiconductor (e.g., crystalline silicon) including a dopant of a first conductivity type. The crystalline semiconductor may be monocrystalline silicon, and the dopant of the first conductivity type may be an N-type dopant including Group V elements such as phosphorus (P), arsenic (As), bismuth (Bi), and stibnum (Sb), or a P-type dopant including Group III elements such as boron (B), aluminum (Al), gallium (Ga), and indium (In).

The back surface3has first regions101and second regions102staggered and spaced from each other in a first direction D1. Gap regions4recessed toward the interior of the substrate1are provided between adjacent first and second regions101,102. The first conductive layer6is formed over the first region101. The second conductive layer7is formed over the second region102. The second conductive layer7is of a conductivity type opposite to the first conductive layer6. The gap region4is configured to physically separate the first conductive layer6from the second conductive layer7, so that the first conductive layer6is insulated from the second conductive layer7or the first electrode8is insulated from the second electrode9to prevent short circuit of positive and negative electrodes of the solar cell or leakage of the solar cell, thereby improving reliability of the solar cell.

The first electrode8forms electrical contact with the first conductive layer6, and the second electrode9forms electrical contact with the second conductive layer7. In some embodiments, the first electrode8and the second electrode9are made from at least one conductive metal material such as silver, aluminum, copper, and nickel.

Referring toFIG.2andFIG.3, a plurality of first pyramidal texture structure regions10are formed on the back surface3corresponding to the gap regions4. The first pyramidal texture structure regions10may be formed through a texturing (or etching) process. The texturing process may be chemical etching, laser etching, mechanical etching, plasma etching, or the like. The first pyramidal texture structure regions10can bring good light trapping and antireflection effects, so that light incident on the back surface3can also be utilized, which increases an effective contact area of the light, realizes further utilization of light energy, and thus improves power generation efficiency.

In some embodiments, a plurality of first pyramidal texture structure regions10, for example, stepped flat texture structures, are formed on the back surface3corresponding to the first regions101and the second regions102, respectively.

Second pyramidal texture structure regions11are formed on the first conductive layer6. The second pyramidal texture structure regions11may be formed through a texturing (or etching) process. The texturing process may be chemical etching, laser etching, mechanical etching, plasma etching, or the like. The second pyramidal texture structure regions11have good light trapping and antireflection effects, so that light incident on the back surface3can also be utilized, which increases an effective contact area of the light, realizes further utilization of light energy, and thus improves power generation efficiency of the solar cell.

In one or more embodiments, different from the first pyramidal texture structure regions10and the second pyramidal texture structure regions11, a plurality of quadrangular frustum pyramid texture structure regions (not shown) are formed on the back surface2corresponding to the first conductive layer6and/or the second conductive layer7. The quadrangular frustum pyramid texture structure regions may also bring good light trapping and antireflection effects.

Still referring toFIG.2andFIG.3, boundary regions5are formed between adjacent first pyramidal texture structure regions10and adjacent second pyramidal texture structure regions11, and the back surface3is provided with a line-pattern concave and convex texture structure12at the boundary region5. Different light trapping structures are formed between the line-pattern concave and convex texture structure12and a surface of the first pyramidal texture structure region10and/or the second pyramidal texture structure region11, which can reduce interface recombinations, increase reflection of incident light on the back surface3of the substrate1, and increase the amount of light absorbed by the solar cell. As a result, the light has a chance to be reused by the solar cell, thereby improving photoelectric conversion efficiency of the IBC solar cell.

Referring toFIG.3, the line-pattern concave and convex texture structures12are strip or line-patterned texture structures arranged at intervals, and a plurality of strip or line-patterned texture structures are parallel to one another. Two opposite ends of the strip or line-patterned texture structures are in contact with the first pyramidal texture structure regions10and the second pyramidal texture structure regions11, respectively. Reflectivity of incident light on the back of the solar cell can be increased by 2% to 6%, so that more incident light is reflected and absorbed again into the substrate1after reaching the back of the solar cell, thereby further improving the photoelectric conversion efficiency by 0.07% to 0.15%.

As shown inFIG.1-1orFIG.1-2, the solar cell is an N-type solar cell. The substrate1is an N-type crystalline silicon substrate1, the first conductive layer6includes a P-type doped layer (i.e., emitter), and the second conductive layer7includes an N-type doped layer (i.e., base).

In some embodiments, as shown inFIG.1-1, the first conductive layer6is formed inside or over the back surface4of the substrate1. For example, the first conductive layer6is formed by doping a preset region of the back surface4of the substrate1with a P-type dopant by means of such as deposition, diffusion, or printing. In this case, the P-type dopant has any impurity of a conductivity type opposite to the substrate1. That is, a Group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In) may be used. The first conductive layer6has a same crystal structure as the substrate1, for example, monocrystalline silicon. A dielectric layer15is provided between the second conductive layer7and the substrate1. In some embodiments, the dielectric layer15includes one or more of silicon oxide, aluminum oxide, hafnium oxide, silicon nitride, and silicon oxynitride. The second conductive layer7is formed by doping amorphous silicon, microcrystalline silicon, or polycrystalline silicon with an N-type dopant. The N-type dopant may be any dopant having a same conductivity type as the substrate1. That is, a Group V element such as phosphorus (P), arsenic (As), bismuth (Bi), or stibnum (Sb) may be used. In an embodiment, the second conductive layer7is a phosphorus-doped polysilicon layer. The second conductive layer7has a different crystal structure from the substrate1.

In some embodiments, as shown inFIG.1-2, the second conductive layer7is the same as the second conductive layer7inFIG.1-1, which is not described in detail herein. The difference lies in that the dielectric layer15is also arranged between the first conductive layer6and the substrate1. In some embodiments, the dielectric layer15includes one or more of silicon oxide, aluminum oxide, hafnium oxide, silicon nitride, and silicon oxynitride, and the first conductive layer6is generally formed by doping amorphous silicon, microcrystalline silicon, or polycrystalline silicon with a P-type dopant. That is, a P-type dopant of a Group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In) may be used. For example, the first conductive layer6is a boron-doped polysilicon layer. The first conductive layer6has a different crystal structure from the substrate1.

In some embodiments, referring toFIG.1-3, the solar cell is a P-type solar cell. That is, the substrate1is a P-type crystalline silicon substrate, the first conductive layer6includes a P-type doped layer (i.e., base), and the second conductive layer7includes an N-type doped layer (i.e., emitter).

The P-type doped layer may form an opening above the substrate1through a process such as laser etching, dry etching, wet etching, or mechanical etching to expose the P-type crystalline silicon substrate, and then the first electrode8may be directly formed on the back surface4of the P-type crystalline silicon substrate, so that the first electrode8comes into contact with the back surface4to facilitate metal atoms in the first electrode8to be diffused into the back surface3to form a base layer. The P-type doped layer includes an alloy layer (e.g., an Al—Si alloy layer) formed by a metal electrode and the substrate1.

A dielectric layer15is arranged between the second conductive layer7and the substrate1. In some embodiments, the dielectric layer15includes one or more of silicon oxide, aluminum oxide, hafnium oxide, silicon nitride, and silicon oxynitride. The second conductive layer7is formed by doping amorphous silicon, microcrystalline silicon, or polycrystalline silicon with an N-type dopant. The N-type dopant may be any dopant having a same conductivity type as the substrate1. That is, a Group V element such as phosphorus (P), arsenic (As), bismuth (Bi), or stibnum (Sb) may be used.

In some embodiments, the structure of the IBC solar cell according to the present disclosure is described with an example with the substrate1being an N-type crystalline silicon substrate.

Referring toFIG.1-1,FIG.15, andFIG.16, the solar cell further includes a back passivation layer13. The back passivation layer13may perform passivation on the back surface of the solar cell and dangling bonds at the first conductive layer6, the second conductive layer7, and the gap region4, which reduces a carrier recombination speed of the back surface3and thus improves the photoelectric conversion efficiency. The back passivation layer13is located on a surface of the first conductive layer6, a surface of the second conductive layer7, and a surface of the gap region4. The first electrode8penetrates through the back passivation layer13to form electrical contact with the first conductive layer6. The second electrode9penetrates through the back passivation layer13to form electrical contact with the second conductive layer7. In some embodiments, the back passivation layer13may be provided with an opening to allow the first electrode8and the second electrode9to pass therethrough to electrically contact with the first conductive layer6and the second conductive layer7, respectively, so as to reduce the contact area among the metal electrode, the first conductive layer6and the second conductive layer7, which further reduces contact resistance, and thus increases an open-circuit voltage.

For example, the back passivation layer13includes a stack structure of at least one or more of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, or a silicon oxynitride layer.

In some embodiments, the back passivation layer13has a thickness in a range of 10 nm to 120 nm, which may be, for example, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 120 nm, or the like, and may also be other values in the range, which is not limited herein.

In some embodiments, a front passivation layer14is formed on the front surface2of the substrate1. The front passivation layer14may perform passivation on the front surface2of the substrate1, which reduces recombinations of carriers at an interface and improves transport efficiency of the carriers, thereby improving the photoelectric conversion efficiency of the IBC solar cell.

In some embodiments, the front passivation layer14includes a stack structure of at least one or more of a silicon oxide layer, a silicon nitride layer, an aluminum oxide layer, or a silicon oxynitride layer.

In some embodiments, an antireflection layer22is further formed over a surface of the front passivation layer14. The antireflection layer22may reduce reflection of incident light and improve refraction of light, thereby improving the utilization of the light and the photoelectric conversion efficiency. In some embodiments, similar to the antireflection layer22, the front passivation layer14may also reduce the reflection of the incident light.

In some embodiments, an ultra-thin dielectric layer15is formed between at least one of the first conductive layer6and the second conductive layer7and the back surface3of the substrate1. The dielectric layer15is configured to perform passivation on an interface of the back surface3of the substrate1, which reduces recombinations of carriers at the interface and ensures transport efficiency of the carriers. Referring toFIG.9toFIG.16, the dielectric layer15is formed between the second conductive layer7and the back surface3of the substrate1.

In some embodiments, the dielectric layer15includes one or more of silicon oxide, aluminum oxide, hafnium oxide, silicon nitride, or silicon oxynitride.

In some embodiments, the dielectric layer15has a thickness in a range of 0.5 nm to 3 nm. If the thickness of the dielectric layer15is excessively large, the tunneling effect of majority carriers will be affected, and it is difficult to transport the carriers through the dielectric layer15, thereby adversely affecting tunneling and passivation effects of the dielectric layer15and gradually decreasing the photoelectric conversion efficiency of the solar cell. If the thickness of the dielectric layer15is excessively small, it is not conducive to the contact with electrode slurry. In some embodiments, the dielectric layer15has a thickness in a range of 0.5 nm to 3 nm. For example, the thickness of the dielectric layer13may be 0.5 nm, 0.9 nm, 1.0 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 2.0 nm, 2.2 nm, 2.4 nm, 2.6 nm, 2.8 nm, 3 nm, or the like, and may also be other values in the range, which is not limited herein.

In some embodiments, the dielectric layer15does not cover the back surface3of the substrate1corresponding to the gap region4. When the first conductive layer6is a P-type doped layer and the second conductive layer7is an N-type doped layer, the dielectric layer15is, for example, a tunnel oxide layer. The tunnel oxide layer allows majority carriers to tunnel into the first conductive layer6and the second conductive layer7and block the passage of minority carriers, and then the majority carriers are transported transversally within the first conductive layer6and the second conductive layer7and collected by the first electrode8or the second electrode9. The tunnel oxide layer forms a tunnel oxide passivated contact structure with the first conductive layer6and the second conductive layer7, which can achieve excellent interface passivation and selective collection of carriers, reduce the recombinations of the carriers, and thus improve the photoelectric conversion efficiency of the IBC solar cell. It is to be noted that the tunnel oxide layer may not have a perfect tunnel barrier in practice because it may include, for example, defects such as pinholes, which may cause other charge carrier transport mechanisms (such as drift, diffusion) to dominate the tunnel effect.

In some embodiments, a distance between a top surface and a bottom surface of the first pyramidal texture structure regions10ranges from 2 μm to 4 μm. For example, the distance may be 2.0 μm, 2.5 μm, 3.0 μm, 3.5 μm, 4.0 μm, or the like, and may also be other values in the range, which is not limited herein. When the distance between the top surface and the bottom surface of the first pyramidal texture structure regions10is limited to the above range, the first pyramidal texture structure regions10bring good light trapping and antireflection effects, enabling further improvement of the photoelectric conversion efficiency.

In some embodiments, a distance between a top surface and a bottom surface of the second pyramidal texture structure regions11ranges from 1 μm to 3 μm. For example, the distance may be 1 μm, 1.5 μm, 2.0 μm, 2.5 μm, 3.0 μm, or the like, and may also be other values in the range, which is not limited herein. When the distance between the top surface and the bottom surface of the second pyramidal texture structure regions11is limited to the above range, the second pyramidal texture structure regions11bring good light trapping and antireflection effects, thereby enabling further improvement of the photoelectric conversion efficiency.

In some embodiments, a distance of the boundary region5in the first direction D1ranges from 3 μm to 5 μm. For example, the distance may be 3.0 μm, 3.5 μm, 4.0 μm, 4.5 μm, 5.0 μm, or the like, and may also be other values in the range, which is not limited herein. If the boundary region5is excessively wide, an effective area of the back surface3may be wasted, and it is difficult to collect effective carriers, thereby reducing the performance of the solar cell. The boundary region5cannot bring good insulation effect between positive and negative electrodes if being excessively narrow.

In some embodiments, referring toFIG.2andFIG.3, a distance between a top surface and a bottom surface of the line-pattern concave and convex texture structure12ranges from 1 μm to 4 μm. For example, the distance may be 1 μm, 1.5 μm, 2.0 μm, 2.5 μm, 3.0 μm, or the like, and may also be other values in the range, which is not limited herein. When the distance between the top surface and the bottom surface of the line-pattern concave and convex texture structure12is limited to the above range, the line-pattern concave and convex texture structure12can increase reflection of incident light, thereby enabling further improvement of the photoelectric conversion efficiency.

In some embodiments, a distance of the gap region4in the first direction D1ranges from 50 μm to 200 μm. For example, the distance may be 50 μm, 70 μm, 90 μm, 110 μm, 130 μm, 150 μm, 170 μm, 190 μm, 200 μm, or the like, and may also be other values in the range, which is not limited herein. If the gap region4is excessively wide, an effective area of the back surface3may be wasted, and it is difficult to collect effective carriers, thereby reducing the performance of the solar cell. The gap region4cannot bring good positive and negative insulation effect between positive and negative electrodes if being excessively narrow.

In some embodiments, a distance of the gap region4in a normal direction of the back surface3of the substrate ranges from 1 μm to 6 μm. For example, the distance may be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, or the like, and may also be other values in the range, which is not limited herein.

In some embodiments, a ratio of an area of the gap region4to an area of the back surface3of the substrate1ranges from 10% to 35%. For example, the ratio may be 10%, 15%, 20%, 25%, 30%, 35%, or the like, and may also be other values in the range, which is not limited herein. If the area of the gap region4is excessively large, the effective area of the back surface3may be wasted, and it is difficult to collect effective carriers, thereby reducing the performance of the solar cell. The gap region4cannot bring good positive and negative insulation effect between positive and negative electrodes if having an excessively small area.

Based on the above embodiments, the present disclosure further provides a method for manufacturing an N-type solar cell, including the following steps.

Providing a substrate1, the substrate1has a front surface2and a back surface3opposite to the front surface2, the back surface3has first regions101and second regions102staggered and spaced from each other in a first direction D1, and gap regions4between the first regions101and the second regions102adjacent to each other;

Forming a first conductive layer6over the back surface3of the substrate1;

Performing laser ablation over the back surface3of the substrate1to remove the first conductive layer6located in the second region102and the gap region4;

Forming a second conductive layer7over the back surface3of the substrate1;

Forming a first protective layer18over a surface of the second conductive layer7corresponding to the second region102;

Removing the second conductive layer7not covered by the first protective layer18;

Removing the first protective layer18;

Performing texturing to form a plurality of first pyramidal texture structure regions on the back surface3corresponding to the gap regions4and form a plurality of second pyramidal texture structure regions11on the second conductive layer7, boundary regions are formed between adjacent first pyramidal texture structure regions10and adjacent second pyramidal texture structure regions11, and the back surface3is provided with a line-pattern concave and convex texture structure12at the boundary region5; and

Forming a first electrode8on the first conductive layer6, and forming a second electrode9on the second conductive layer7.

By use of the solar cell manufactured with the above method, since the design of a partial structure of the IBC solar cell is optimized, the gap region4effectively separates the first conductive layer6from the second conductive layer7, which reduces interface recombinations. In addition, boundary regions5are formed between adjacent first pyramidal texture structure regions10and adjacent second pyramidal texture structure regions11, and the back surface3is provided with a line-pattern concave and convex texture structure12at the boundary region5, so as to increase reflection of incident light on the back surface3of the substrate1, increase the amount of light absorbed by the solar cell, and thus improve conversion efficiency of the solar cell.

In step S10, referring toFIG.4, in some embodiments, the substrate1is an N-type crystalline silicon substrate1, the front surface2is a light receiving surface facing the direction of sunlight, the back surface3is a surface opposite to the front surface2, the first conductive layer6is formed over the first region101, the second conductive layer7is formed over the second region102, the second conductive layer7is of a conductivity type opposite to the first conductive layer6, and the gap region4is configured to separate the first conductive layer6from the second conductive layer7to improve insulating properties of positive and negative electrodes, prevent leakage of the solar cell, and thus improve reliability of the solar cell.

In step S20, referring toFIG.5andFIG.6, the substrate1is textured, and a first conductive layer6is formed on the back surface3of the substrate1. In some embodiments of the present disclosure, the first conductive layer6includes a P-type doped layer (i.e., emitter). Boron is doped into the substrate1by diffusion for 2 h to 5 h at a temperature of 800° C. to 1200° C., forming the first conductive layer6on the back surface3of the N-type silicon substrate1, with diffusion sheet resistance in a range of 70 ohm/sq to 120 ohm/sq. BSG is also formed by diffusion on the doped layer. A BSG layer16plays a role of isolation to better protect the first conductive layer6. The BSG layer16has a thickness in a range of 100 nm to 200 nm. It may be understood that, in a boron diffusion process, a P-type doped layer and part of the BSG layer16may also be formed on the front surface2of the substrate1, and this part of BSG is required to be removed. In some embodiments, the BSG layer16on the front surface2is removed using chain HF acid with concentration in a range of 2% to 15%.

In step S30, referring toFIG.7andFIG.8, laser ablation is performed on the back surface3of the substrate1to remove the first conductive layer6located in the second region102and the gap region4. For example, laser ablation is performed on the back surface3first, a pattern after laser ablation is interdigitated, and corresponds to a sum of the second region102and the gap region4, the BSG layer16in the corresponding regions is removed, and then laser damages are removed by polishing. In some embodiments, laser power ranges from 8 W to 15 W, an ablation width ranges from 300 μm to 600 μm, a polishing temperature is in a range of 50° C. to 65° C., polishing time ranges from 400 s to 800 s, a polishing solution includes NaOH with a volume fraction in a range of 1% to 5% or KOH with a volume fraction in a range of 1% to 3% and an additive with a volume fraction in a range of 0.5% to 2.5%, and a polishing depth is in a range of 2 μm to 5 μm.

In step S40, referring toFIG.9, a second conductive layer7is formed over the back surface3of the substrate1. The second conductive layer7includes an N-type doped layer (i.e., base). In some embodiments, a dielectric layer15(tunnel oxide layer) is first grown by thermal oxidation. The dielectric layer15has a thickness in a range of 0.1 nm to 1 nm. Intrinsic polysilicon is deposited on the dielectric layer15by low pressure chemical vapor deposition. The polysilicon has a thickness in a range of 100 nm to 200 nm. Phosphorus is doped into the intrinsic polysilicon by diffusion for 1 h to 3 h at a temperature of 700° C. to 1000° C., forming a passivated contact structure at the back of the N-type silicon substrate1. The passivated contact structure is a stacked layer of the dielectric layer15and the second conductive layer7. The second conductive layer7has sheet resistance in a range of 25 ohm/sq to 45 ohm/sq. PSG is also formed on the N-type polysilicon by diffusion. A PSG layer17may serve as a barrier layer, and has a thickness in a range of 20 nm to 100 nm.

In step S50, referring toFIG.10, a first protective layer18is formed on the surface of the second conductive layer7corresponding to the second region102. In some embodiments, the first protective layer18is an INK protective layer. The PSG layer17of the second conductive layer7is coated with an interdigitated INK protective layer by screen printing or ink-jet coating. A pattern of the INK protective layer is an electrode pattern of the IBC solar cell.

In step S60, the second conductive layer7not covered by the first protective layer18is removed, and then the first protective layer18is removed. Then, texturing is performed to form a plurality of first pyramidal texture structure regions10on the back surface3corresponding to the gap region4and form a plurality of second pyramidal texture structure regions11on the first conductive layer6, boundary regions5are formed between adjacent first pyramidal texture structure regions10and adjacent second pyramidal texture structure regions11, and the back surface3is provided with a line-pattern concave and convex texture structure12at the boundary region5.

In S601, referring toFIG.11, the PSG layer17not covered by the first protective layer17is corroded with HF acid with a volume fraction in a range of 1% to 20%, and corrosion time ranges from 5 s to 60 s.

In S602, referring toFIG.12, after the PSG layer17not covered by the first protective layer18is removed, the first protective layer18is washed off with an alkaline solution which is a solution with NaOH concentration in a range of 1% to 10%, to react for 180 s to 300 s.

In S603, referring toFIG.13, texturing or alkaline polishing is performed in an alkaline solution which is a solution with NaOH concentration in a range of 0.5% to 5% at a temperature of 60° C. to 80° C. to react for 240 s to 500 s. The second conductive layer7not protected by the PSG layer17is etched away to form the gap region4.

In S603, referring toFIG.14, RCA cleaning is performed on the textured substrate1, followed by cleaning in an HF solution with concentration in a range of 1% to 10% to clean the surface of the substrate1and remove the dielectric layer15, the BSG layer16, and the PSG layer17on the surface of the substrate1, so as to form different profiles in different regions of the back surface3. First pyramidal texture structure regions10are formed in the gap region4, and a distance (or height) between the top and the bottom of the first pyramidal texture structure regions10ranges from 2 μm to 4 μm. A plurality of second pyramidal texture structure regions11are formed on the second conductive layer7, and a distance (or height) between the top and the bottom of the second pyramidal texture structure regions11ranges from 1 μm to 3 μm. Boundary regions5are formed between adjacent first pyramidal texture structure regions10and adjacent second pyramidal texture structure regions11. The boundary region5has a width in a range of 3 μm to 5 μm. The back surface3is provided with a line-pattern concave and convex texture structure12at the boundary region5.

In step S70, referring toFIG.15andFIG.16, a front passivation layer14and a back passivation layer13are deposited on the front surface2and the back surface3of the substrate1respectively. The front passivation layer14is a stacked layer of aluminum oxide, silicon oxide, and silicon nitride, and the back passivation layer13is aluminum oxide and silicon nitride. Silver aluminum slurry and silver slurry are printed on the back surface3of the substrate1. The silver aluminum slurry is printed and aligned with the first conductive layer6to form the first electrode8, and the silver slurry is aligned with the second conductive layer7to form the second electrode9, which are sintered to complete metallization.

Based on the above embodiment, referring toFIG.17, the present disclosure further provides a photovoltaic module, including: solar cell strings19, each of the solar cell strings19is formed by connecting the solar cells, and adjacent solar cell strings19are connected by a conductive strip such as a solder strip; an encapsulation layer20, the encapsulation layer20is configured to cover surfaces of the solar cell strings19; and a cover plate21, the cover plate21is configured to cover a surface of the encapsulation layer20away from the solar cell strings19.

In some embodiments, at least two solar cell strings19are provided. The solar cell strings19are electrically connected in parallel and/or in series.

In some embodiments, the encapsulation layer20includes encapsulation layers arranged on the front and back of the solar cell strings19. Materials of the encapsulation layer20include, but are not limited to, ethylene vinyl acetate (EVA), polyolefin elastomer (POE), and polyethylene terephthalate (PET) films.

In some embodiments, the cover plate21includes cover plates21arranged on the front and back of the solar cell strings19. Materials with good light transmittance are selected for the cover plate21, including but not limited to glass, plastic, and the like.

Finally, it should be noted that the above embodiments are merely intended to describe the technical solutions of the present disclosure instead of limiting the present disclosure. Although the present disclosure is described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that they can still make modifications to the technical solutions described in the above embodiments, or make equivalent replacements to some or all of the technical features in the technical solutions; and these modifications or replacements do not make the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present disclosure, all of which fall within the scope of the claims and the specification of the present disclosure. In particular, the technical features mentioned in various embodiments can be combined in any manner provided that there is no structural conflict. The present disclosure is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling into the protection scope of the claims.