Patent ID: 12237240

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Hereinafter, example embodiments will be explained in detail with reference to the accompanying drawings.

FIG.1is a plan view illustrating a semiconductor package according to example embodiments.FIG.2is a cross-sectional view taken along the line A-A′ inFIG.1.FIG.3is a cross-sectional view taken along the line B-B′ inFIG.1.FIG.4is an enlarged cross-sectional view illustrating portion ‘C’ inFIG.2.FIG.5is an enlarged cross-sectional view illustrating portion ‘D’ inFIG.3.

Referring toFIGS.1to5, a semiconductor package10may include a package substrate100, an interposer200, first and second semiconductor devices300and400, and a molding layer500. Additionally, the semiconductor package10may further include a first underfill member350, a second underfill member450and a third underfill member270and a stiffener700.

In example embodiments, the semiconductor package10may be a memory device having a stacked chip structure in which a plurality of dies (chips) is stacked. For example, the semiconductor package10may include a semiconductor memory device with a 2.5D chip structure. In this case, a first semiconductor device300may include or may be a logic semiconductor device, and a second semiconductor device400may include or may be a memory device. The logic semiconductor device may include or may be a CPU, a GPU, an ASIC, or an SOC. The memory device may include or may be a high bandwidth memory (HBM) device.

In example embodiments, the package substrate100may be a substrate having an upper surface and a lower surface opposite to each other. For example, the package substrate100may be a printed circuit board (PCB). The PCB may be a multilayered circuit board including vias and various circuits therein.

The interposer200may be disposed on the package substrate100. The interposer200may be mounted on the package substrate100through solder bumps260. A planar area of the interposer200may be less than a planar area of the package substrate100. For example, the planar area of the interposer200may be an area of the interposer200in a plan view. The interposer200may be disposed within the area of the package substrate100in a plan view. For example, the package substrate100may vertically overlap the whole interposer200.

The interposer200may be a silicon interposer including a plurality of wirings therein. First semiconductor devices300and second semiconductor devices400may be electrically connected to each other through the wirings and may be electrically connected to the package substrate100through the solder bumps260. The silicon interposer may provide a high density interconnection between the first and second semiconductor devices300and400. Alternatively, the interposer200may be a redistribution wiring interposer or a semiconductor die in which a logic chip or a memory chip is implemented.

As used herein, components described as being “electrically connected” are configured such that an electrical signal can be transferred from one component to the other (although such electrical signal may be attenuated in strength as it transferred and may be selectively transferred).

In case of the silicon interposer, the interposer200may include a semiconductor substrate210, a wiring layer220disposed on an upper surface of the semiconductor substrate210and including a plurality of wirings222, a plurality of first bonding pads230provided on the wiring layer220and a plurality of second bonding pads240provided on a lower surface of the semiconductor substrate210.

For example, the interposer200may have an area of 20 mm×30 mm or more. For example, the interposer200may have a rectangle shape in a plan view. For example, lengths of shorter sides of the interposer200may be 20 mm or greater and lengths of longer sides of the interposer200may be 30 mm or greater in the plan view. The substrate210may include silicon, germanium, silicon-germanium, or III-V compounds, e.g., GaP, GaAs, GaSb, etc.

The wiring layer220may include a plurality of insulation layers and a plurality of wirings222in the insulation layers. For example, the wirings222may include or be formed of a metal such as copper Cu.

The semiconductor substrate210may include a plurality of through electrodes250penetrating therethrough. The through electrodes250may include a through silicon via (TSV). Each of the through electrodes250may be provided to extend in a thickness direction from a first surface of the semiconductor substrate210to a second surface of the semiconductor substrate210. The first and second surfaces of the semiconductor substrate210may be opposite surfaces. An end portion of the through electrode250may contact the wiring222of the wiring layer220.

It will be understood that when an element is referred to as being “connected” or “coupled” to or “on” another element, it can be directly connected or coupled to or on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as “contacting” or “in contact with” another element, there are no intervening elements present at the point of contact.

The interposer200may be mounted on the package substrate100via the solder bumps260. Each of the solder bumps260may be formed on a corresponding second bonding pad240. For example, the solder bump260may include or may be C4 (controlled collapse chip connection) bump. The second bonding pad240of the interposer200may be electrically connected to a substrate pad of the package substrate100by the solder bump260.

In example embodiments, at least one first semiconductor device300may be arranged on the interposer200. The first semiconductor device300may be mounted on the interposer200in a flip chip bonding manner. In this case, the first semiconductor device300may be mounted such that an active surface of the first semiconductor device300on which chip pads310are formed faces the interposer200. The chip pads310of the first semiconductor device300may be electrically connected to the first bonding pads230of the interposer200by conductive bumps330. For example, the conductive bumps330may include or may be micro bumps (uBump).

The second semiconductor devices400may be arranged on the interposer200to be spaced apart from the first semiconductor device300. The second semiconductor devices400may be arranged on the interposer200to be spaced apart from each other. The second semiconductor devices400may be mounted on the interposer200in a flip chip bonding manner. In this case, each of the second semiconductor devices400may be mounted such that an active surface of the second semiconductor device400on which chip pads410are formed faces the interposer200. The chip pads410of the second semiconductor device400may be electrically connected to the first bonding pads230of the interposer200by conductive bumps430. For example, the conductive bumps430may include or may be micro bumps (uBump).

For example, the second semiconductor device400may include a buffer die and a plurality of memory dies (chips) sequentially stacked on the buffer die. Additionally, the second semiconductor device400may further include a molding member covering at least side surfaces of the buffer die and the memory dies. The buffer die and the memory dies may be electrically connected to each other by through silicon vias (TSVs).

The wirings222may be electrically connected to through electrodes250. The first and second semiconductor devices300,400may be electrically connected to the package substrate100through the wirings222and the through electrodes250. The first semiconductor device300and the second semiconductor device400may be electrically connected to each other by the wirings222.

In example embodiments, the first underfill member350may be filled between the first semiconductor device300and the interposer200and the second underfill member450may be filled between the second semiconductor device400and the interposer200. The third underfill member270may be filled between the interposer200and the package substrate100.

The first underfill member350may extend between the first semiconductor device300and the interposer200to reinforce a gap between the first semiconductor device300and the interposer200. For example, the first underfill member350may reinforce adhesion between the first semiconductor device300and the interposer200. The second underfill member450may extend between the second semiconductor device400and the interposer200to reinforce a gap between the second semiconductor device400and the interposer200. For example, the second underfill member450may reinforce adhesion between the second semiconductor device400and the interposer200. Portions of the first and second underfill members350and450may extend upwardly from the upper surface of the interposer200respectively to cover portions of side surfaces of the first and second semiconductor devices350and450to firmly support the first and second semiconductor devices350and450.

The third underfill member270may extend between the interposer200and the package substrate100to reinforce a gap between the interposer200and the package substrate100. For example, the third underfill member270may reinforce adhesion between the interposer200and the package substrate100. A portion of the third underfill member270may extend upwardly from the upper surface of the package substrate100to cover a portion of a side surface of the interposer200to firmly support the interposer200.

The first, second and third underfill members350,450and270may include or be formed of a material having a relatively high fluidity to effectively fill small spaces between the first and second semiconductor devices300and400and the interposer200and between the interposer200and the package substrate100. For example, the first, second and third underfill members350,450and270may include or be formed of an adhesive including an epoxy material. The first and second semiconductor devices300and400may have a first coefficient of thermal expansion, and the first and second underfill members350and450may have a second coefficient of thermal expansion greater than the first coefficient of thermal expansion. The first coefficient of thermal expansion may be within a range of 1 ppm/° C. to 4 ppm/° C., and the second coefficient of thermal expansion may be within a range of 20 ppm/° C. to 30 ppm/° C.

As illustrated inFIG.1, the interposer200may include first to fourth side surfaces S1, S2, S3and S4. The first to fourth side surfaces S1, S2, S3and S4may be perpendicular to the upper surface of the interposer200. The third side surface S3and the fourth side surface S4may extend in parallel with a first direction (X direction) and may be opposite to each other. The first side surface S1and a second side surface S2may extend in a direction parallel with a second direction (Y direction) and may be opposite to each other. The first direction (X-direction) and the second direction (Y direction) may be perpendicular to each other. The interposer200may have a rectangular plate shape having long sides (e.g., the first and second sides S1and S2) and short sides (e.g., the second and fourth sides S3and S4).

The first and second semiconductor devices300and400may be arranged on the upper surface of the interposer200to be spaced apart from each other. Two first semiconductor devices300may be arranged to be spaced apart from each other in the second direction (Y direction) with a center line ML of the interposer200interposed therebetween, e.g., in a plan view. The center line ML may pass through the midpoints of the long sides. Four second semiconductor devices400may be disposed on the upper surface of the interposer200to be spaced apart from each other in the second direction (Y direction) along the first side surface S1of the interposer200. Four second semiconductor devices400may be disposed on the upper surface of the interposer200to be spaced apart from each other in the second direction (Y direction) along the second side surface S2of the interposer200. Two second semiconductor devices400may be disposed to be spaced apart from each other in the second direction (Y direction) with the center line ML of the interposer200interposed therebetween, e.g., in a plan view.

In a plan view as shown inFIG.1, two second semiconductor devices400may be arranged on the left side of a first semiconductor device300above the center line ML adjacent to the first side surface S1of the interposer200, and two second semiconductor devices400may be arranged on the right side of the first semiconductor device300above the center line ML adjacent to the second side surface S2of the interposer200. Similarly, two second semiconductor devices400may be arranged on the left side of a first semiconductor device300below the center line ML adjacent to the first side surface S1of the interposer200, and two second semiconductor devices400may be arranged on the right side of the first semiconductor device300below the center line ML adjacent to the second side surface S2of the interposer200.

Although only two first semiconductor devices300and eight second semiconductor devices400are illustrated in the figures, the numbers and arrangements thereof are exemplary, and they are not limited thereto.

As illustrated inFIGS.2and4, the second semiconductor devices400may be spaced apart from each other in the second direction (Y direction) to form a first gap G1. For example, the first gap G1may have a spacing distance in a range of 50 μm to 150 μm. A first height H1of the second semiconductor device400, e.g., a vertical distance from a top surface of the interposer200to a top surface of the second semiconductor device400, may be 700 μm or more. For example, the vertical distance may be measured in a direction perpendicular to the top surface of the interposer200. The second semiconductor device400may have an area of 10 mm×10 mm or more, e.g., in a plan view. For example, each side of the second semiconductor device400may have a length of 10 mm or greater in the plan view.

As illustrated inFIGS.3and5, the first semiconductor devices300may be spaced apart from each other in the second direction (Y direction) to form a second gap G2. The second gap G2may have a spacing distance less than the spacing distance of the first gap G1. For example, the second gap G2may have the spacing distance within a range of 20 μm to 100 μm. The first semiconductor device300may have a second height H2less than or the same as the height H1of the second semiconductor device400. The second height H2may be a vertical distance from the top surface of the interposer200to a top surface of the semiconductor device300. The second height H2of the first semiconductor device300may be 500 μm or more. The first semiconductor device300may have an area of 20 mm×20 mm or more, e.g., in a plan view. For example, each side of the first semiconductor device300may have a length of 20 mm or greater in the plan view.

In example embodiments, the molding layer500may be provided on the upper surface of the interposer200to cover the first and second semiconductor devices300and400. The molding layer500may cover the side surfaces of the first and second semiconductor devices300and400.

An upper surface of the molding layer500may be coplanar with upper surfaces of the first semiconductor devices300. The upper surface of the molding layer500may be coplanar with upper surfaces of the second semiconductor devices400. The upper surfaces of the first and second semiconductor devices300and400may be exposed by the molding layer500. A side surface of the molding layer500may be coplanar with the side surface of the interposer200. A portion of the third underfill member270may cover at least a portion of the side surface of the molding layer500.

For example, the molding layer500may include or be formed of a polymer material such as an epoxy molding compound (EMC). The molding layer500may have a coefficient of thermal expansion greater than those of the first and second semiconductor devices. The molding layer500may have a coefficient of thermal expansion within a range of 5 ppm/° C. to 15 ppm/° C. The interposer200may have a coefficient of thermal expansion the same as or similar to those of the first and second semiconductor devices300and400.

In example embodiments, the molding layer500may have at least one groove600extending in one direction between the first and second semiconductor devices300and400. A first groove600amay be provided in the molding layer500between the second semiconductor devices400. A second groove600bmay be provided in the molding layer500between the first semiconductor devices300. In some embodiments, the first groove600aand the second groove600bmay be integrally formed as shown inFIG.1. For example, the first groove600aand the second groove600bmay be connected to each other. For example, the first groove600aand the second groove600bmay be continuously and integrally formed in the molding layer500. In certain embodiments, the first groove600aand the second groove600bmay be spaced apart from each other. The grooves600aand600bmay be recesses formed on a top surface of the molding layer500.

The first groove600amay extend in the first direction (X direction) between the second semiconductor devices400. The first groove600amay extend along the center line ML of the interposer200. The first groove600amay have a first depth D1from the upper surface502of the molding layer500. For example, the first depth D1of the first groove600amay be 30% to 100% of the first height H1of the second semiconductor device400. The first width W1of the first groove600amay be 20% to 100% of the first gap G1.

When the first depth D1of the first groove600ais equal to the first height H1of the second semiconductor device400(100% of the first height H1), the wiring layer220of the interposer200may be exposed on a bottom surface602the first groove600a. When the first width W1of the first groove600ais equal to the spacing distance of the first gap G1(100% of the first gap G1), the side surfaces of the second semiconductor devices400may be exposed on sidewalls604of the first groove600a.

The second groove600bmay extend in the first direction (X direction) between the first semiconductor devices300. The second groove600bmay extend along the center line ML of the interposer200. The first and second grooves600aand600bmay extend along the center line ML of the interposer200to be in communication with each other. The second groove600bmay have a second depth D2from the upper surface502of the molding layer500, e.g., in a vertical direction. For example, the second depth D2of the second groove600bmay be 30% to 100% of the second height H2of the first semiconductor device300. The second width W2of the second groove600bmay be 20% to 100% of the second gap G2. The second width W2of the second groove600bmay be equal to or smaller than the first width W1of the first groove600a.

When the second depth D2of the second groove600bis equal to the second height H2of the first semiconductor device300(100% of the second height H2), the wiring layer220of the interposer200may be exposed on a bottom surface602of the second groove600b. When the second width W2of the second groove600bis equal to the spacing distance of the second gap G2(100% of the second gap G2), the side surfaces of the first semiconductor devices300may be exposed on sidewalls604of the second groove600b.

In example embodiments, a stiffener700may be arranged on the package substrate100to surround the semiconductor devices300and400. The stiffener700may be provided to extend along a peripheral region of the package substrate100to increase overall rigidity of the package substrate100to thereby reduce or prevent warpage. Accordingly, reliability of the 2.5D package may be improved.

Outer connection pads may be formed on the lower surface of the package substrate100, and outer connection members130for an electrical connection with an external device may be disposed on the outer connection pads respectively. The outer connection members130may be, for example, solder balls. The semiconductor package10may be mounted on a module substrate by the solder balls, thus constituting a memory module.

Although only some first bonding pads230and second bonding pads240are illustrated in the figures, it may be understood that the first bonding pads230and the second bonding pads240are exemplary, and thus, numbers and arrangements of the first and second bonding pads230and240are not limited thereto.

As mentioned above, the semiconductor package10may include the package substrate100, the interposer200provided on the package substrate100, the first and second semiconductor devices300and400arranged on the interposer200to be spaced apart from each other, and the molding layer500on the interposer200to cover the side surfaces of the first and second semiconductor devices300and400. The molding layer500may have the at least one groove600extending in one direction between the first and second semiconductor devices300and400. The molding layer500may have the coefficient of thermal expansion greater than those of the first and second semiconductor devices300and400.

Since the groove600is formed in the upper surface of the molding layer500between the first and second semiconductor devices300and400, warpage behavior of the molded interposer in a high temperature region may be minimized and the rigidity of the molded interposer may be reduced. Accordingly, solder wettability in a bonding process of the molded interposer may be improved to enhance the 2.5D package reliability. Further, a thermal disconnection effect between the first and second semiconductor devices300and400may be generated to thereby prevent a thermal-coupling phenomenon.

Hereinafter, a method of manufacturing the semiconductor package inFIG.1will be explained.

FIGS.6to20are views illustrating a method of manufacturing a semiconductor package according to example embodiments.FIGS.7to11,13,15,17,19and20are cross-sectional views taken along the line E-E′ inFIG.6.FIGS.12,14,16and18are cross-sectional views taken along the line F-F′ inFIG.6.

Referring toFIGS.6and7, first, a semiconductor wafer W for a base structure may be prepared.

In example embodiments, the base structure may include or may be a silicon interposer. Alternatively, the base structure may include or may be a redistribution wiring interposer or a semiconductor die in which a logic chip or a memory chip is implemented.

In case of the silicon interposer, the wafer W may include a substrate210and a wiring layer220. The wiring layer220may be provided on a first surface212of the substrate210. The wafer W may include a package region, e.g., a mounting region MR where semiconductor device(s) are mounted and a scribe lane region, e.g., a cutting region CA surrounding the mounting region MR. As described later, the wafer W may be cut along the cutting region CA dividing the mounting regions MR to form an individual interposer. For example, the mounting region MR may have an area of 20 mm×30 mm or more. For example, the mounting region MR may have a rectangle shape in a plan view. For example, shorter sides of the mounting region MR may have a length of 20 mm or greater, and longer sides of the mounting region MR may have a length of 30 mm or greater in the plan view.

For example, the substrate210may include or be formed of silicon, germanium, silicon-germanium, or III-V compounds, e.g., GaP, GaAs, GaSb, etc. In some embodiments, the substrate210may be a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate.

The wiring layer220may be formed on the first surface212of the substrate210. The wiring layer220may be formed by a back process referred to as BEOL (Back End of Line) process. The wiring layer220may include a plurality of insulation layers and a plurality of wirings222in the insulation layers. For example, the wiring may include or be formed of a metal such as copper (Cu).

The substrate210may include a plurality of through electrodes (through silicon vias)250which are formed to penetrate the substrate210, e.g., from a top surface to a bottom surface of the substrate210. The through electrodes250may be electrically connected to the wirings222respectively. The through electrodes250may be formed in the substrate210before grinding a backside (e.g., a second surface214) of the substrate210(e.g., a via first process or a via middle process). Alternatively, the through electrode may be formed in the substrate210after grinding the backside of the substrate210(e.g., a via last process).

A first bonding pad230may be provided in the outermost insulation layer of the wiring layer220. The through electrode250may be electrically connected to the first bonding pad230through the wiring222.

Referring toFIGS.8to10, a second bonding pad240may be formed on the second surface214of the substrate210, and a solder bump260as a conductive connection member may be formed on the second bonding pad240.

As illustrated inFIGS.8and9, the backside of the substrate210, e.g., the second surface214, may be grinded using a substrate support system WSS. The wafer W may be adhered to a carrier substrate C1using a first adhesive film F1, and then, the second surface214of the substrate210may be grinded until a portion of the through electrode250is exposed.

The second surface214of the substrate210may be partially removed by a grinding process such as a chemical mechanical polishing (CMP) process. Thus, a thickness of the substrate210may be reduced to a desired/proper thickness. For example, the substrate210may have a thickness range of about 50 μm to 100 μm. Additionally, the portion of the through electrode250may be exposed from the second surface214of the substrate210.

As illustrated inFIG.10, the second bonding pad240may be formed on the second surface214of the substrate210to be electrically connected to the through electrode250, and the solder bump260may be formed on the second bonding pad240.

The second bonding pad240may be formed by forming a seed layer and a photoresist layer on the second surface214of the substrate210, performing an exposure process on the photoresist layer to form a photoresist pattern having an opening that exposes a portion of the seed layer, and performing a plating process on the exposed portion of the seed layer.

For example, the second bonding pad240may have a diameter of 70 μm to 80 μm. The diameter of the second bonding pad240may be at least three times a diameter of the first bonding pad230.

Then, the solder bump260may be formed on the second bonding pad240.

For example, a seed layer may be formed on the second bonding pad240on the second surface214of the substrate210, and a photoresist pattern having an opening that exposes a portion of the seed layer may be formed on the second surface214of the substrate210.

Then, the opening of the photoresist pattern may be filled with a conductive material, and then, the photoresist pattern may be removed and a reflow process may be performed to form the solder bump260. For example, the conductive material may be formed by a plating process. Alternatively, the solder bump may be formed by a screen printing process, a deposition process, etc.

The carrier substrate C1may be removed from the wafer W.

Referring toFIGS.11and12, the structure inFIG.10may be reversed (flipped over), and a plurality of semiconductor devices300and400may be mounted on the wiring layer220. Then, first and second underfill members350and450may be formed between the semiconductor devices300and400and the wiring layer220.

Firstly, the wafer W may be adhered to a second carrier substrate C2using a second adhesive film F2. The wafer W may be adhered to the second carrier substrate C2such that the second surface214faces toward the second carrier substrate C2and the first bonding pads230are exposed. Then, the first and second semiconductor devices300and400may be arranged on the wiring layer220to be spaced apart from each other.

In example embodiments, the first and second semiconductor devices300and400may be mounted on the wiring layer220in a flip chip bonding manner. Chip pads310of the first semiconductor device300may be electrically connected to the first bonding pads230of the wiring layer220by conductive bumps330. Chip pads410of the second semiconductor device400may be electrically connected to the first bonding pads230of the wiring layer220by conductive bumps430. For example, the conductive bumps330and430may include or may be micro bumps (uBump).

For example, the first semiconductor device300may include or may be a logic semiconductor device, and the second semiconductor device400may include or may be a memory device. The logic semiconductor device may include or may be a CPU, a GPU, an ASIC, or an SOC. The memory device may include or may be a high bandwidth memory (HBM) device. In this case, the second semiconductor device may include a buffer die and a plurality of memory dies (chips) sequentially stacked on the buffer die. The buffer die and the memory dies may be electrically connected to each other by through silicon vias.

As illustrated inFIG.11, the second semiconductor devices400may be spaced apart from each other to form a first gap G1. For example, the first gap G1may have a spacing distance in a range of 50 μm to 150 μm. A first height H1of the second semiconductor device400may be 700 μm or more. The second semiconductor device400may have an area of 10 mm×10 mm or more. For example, each side of the second semiconductor device400may have a length of 10 mm or greater in a plan view.

As illustrated inFIG.12, the first semiconductor devices300may be spaced apart from each other to form a second gap G2. For example, the second gap G2may have a spacing distance within a range of 20 μm to 100 μm. The first semiconductor device300may have a second height H2less than or the same as the height H1of the second semiconductor device400. The second height H2of the first semiconductor device300may be 500 μm or more. The first semiconductor device300may have an area of 20 mm×20 mm or more. For example, each side of the first semiconductor device300may have a length of 20 mm or greater in a plan view.

Then, an underfill solution may be dispensed between the first semiconductor devices300and the wiring layer220and between the second semiconductor devices400and the wiring layer220while moving a dispenser nozzle along edges of the first and second semiconductor devices300and400, and the underfill solution may be cured to form the first and second underfill members350and450. The first underfill member350may extend between the first semiconductor device300and the wiring layer220to reinforce a gap between the first semiconductor device300and the wiring layer220. For example, the first underfill member350may be beneficial for adhesion between the first semiconductor device300and the wiring layer220. The second underfill members450may extend between the second semiconductor device400and the wiring layer220to reinforce a gap between the second semiconductor device400and the wiring layer220. For example, the second underfill member450may be beneficial for adhesion between the second semiconductor device400and the wiring layer220.

The first and second underfill members350and450may include or be formed of a material having a relatively high fluidity so as to effectively fill small spaces between the first and second semiconductor devices300and400and the wiring layer220. For example, the first and second underfill members may include or be formed of an adhesive including an epoxy material. The first and second underfill members350and450may have a coefficient of thermal expansion greater than those of the first and second semiconductor devices300and400. The first and second underfill members350and450may have a coefficient of thermal expansion within a range of 20 ppm/° C. to 30 ppm/° C. The first and second semiconductor devices300and400may have a coefficient of thermal expansion within a range of 1 ppm/° C. to 4 ppm/° C. The wafer W may have a coefficient of thermal expansion the same as or similar to those of the first and second semiconductor devices300and400.

Referring toFIGS.13and14, a molding material50may be formed on the wiring layer220to cover the first and second semiconductor devices300and400.

In example embodiments, the molding material50may be formed to cover side surfaces and upper surfaces of the first and second semiconductor devices300and400. The molding material50may be formed to completely fill the gaps G1and G2between the first and second semiconductor devices300and400. For example, the molding material50may be formed using a polymer material such as an epoxy molding compound (EMC) by a molded underfill (MUF) process. The molding material50may have a coefficient of thermal expansion greater than those of the first and second semiconductor devices300and400. The molding material50may have a coefficient of thermal expansion within a range of 5 ppm/° C. to 15 ppm/° C.

Referring toFIGS.15and16, an upper surface/portion of the molding material50may be partially removed to form a molding layer500that exposes the upper surfaces of the first and second semiconductor devices300and400.

For example, the molding material50may be partially removed by a grinding process such as a chemical mechanical polishing (CMP) process. The upper surfaces of the first and second semiconductor devices300and400may be exposed by the molding layer500. The upper surface of the molding layer500may be coplanar with the upper surface of the first semiconductor device300and/or the upper surface of the second semiconductor device400. The side surfaces of the first and second semiconductor devices300and400may be covered by the molding layer500.

Referring toFIGS.17and18, the molding layer500between the first and second semiconductor devices300and400may be partially removed to form grooves600aand600b. The grooves may be formed by removing a portion of the molding layer500using a blade, laser, plasma, or the like.

As illustrated inFIG.17, the first groove600amay be formed in the molding layer500between the second semiconductor devices400to extend in a direction parallel to side surfaces of the second semiconductor devices400facing each other. The first groove600amay have a first depth D1from an upper surface502of the molding layer500. For example, the first depth D1of the first groove600amay be 30% to 100% of the first height H1of the second semiconductor device400. A first width W1of the first groove600amay be 20% to 100% of the first gap G1.

When the first depth D1of the first groove600ais equal to the first height H1of the second semiconductor device400, the wiring layer220of the interposer200may be exposed on a bottom surface of the first groove600a. When the first width W1of the first groove600ais equal to a spacing distance of the first gap G1, the side surface of the second semiconductor device400may be exposed on a sidewall of the first groove600a.

As illustrated inFIG.18, the second groove600bmay be formed in the molding layer500between the first semiconductor devices300to extend in a direction parallel to side surfaces of the first semiconductor devices300facing each other. The second groove600bmay have a second depth D2from the upper surface502of the molding layer500. For example, the second depth D2of the second groove600bmay be 30% to 100% of the second height H2of the first semiconductor device300. A second width W2of the second groove600bmay be 20% to 100% of the second gap G2. The second width W2of the second groove600bmay be the same as or less than the first width W1of the first groove600a.

When the second depth D2of the second groove600bis equal to the second height H2of the first semiconductor device300, the wiring layer220of the interposer200may be exposed on a bottom surface of the second groove600b. When the second width W2of the second groove600bis equal to a spacing distance of the second gap G2, the side surface of the first semiconductor device300may be exposed on a sidewall of the second groove600b.

Referring toFIGS.19and20, the wafer W may be cut along the cutting region CA to form the individual interposer200, and the interposer200on which the first and second semiconductor devices300and400are mounted may be disposed on a package substrate100. Then, a third underfill member270may be formed between the interposer200and the package substrate100.

In example embodiments, the interposer200may be mounted on the package substrate100through the solder bumps260. The interposer200may be attached on the package substrate100by a mass reflow process. Then, an underfill solution may be dispensed between the interposer200and the package substrate100while moving a dispenser nozzle along edges of the interposer200, and the underfill solution may be cured to form the third underfill member270. For example, the mass reflow process may be a reflow soldering process in which a reflow soldering is performed together with respect to a plurality of package substrate100on which interposers200are respectively mounted.

In the mass reflow process, package substrates100on which interposers200are disposed respectively may be loaded into a reflow oven at once, and then, the reflow process may be performed on the package substrates100within the reflow oven. The mass reflow process may have advantages in mass production compared to a thermo-compression process and a local reflow process.

The mass reflow process may be sensitive to a warpage behavior between the molded interposer and the package substrate depending on a reflow temperature in the reflow oven. For example, when a bending behavior of the molded interposer at a solder melting point and/or its vicinity does not match the package substrate, non-wetting may occur. For example, at the solder melting temperature and/or its vicinity, the interposer200may be bent in the form of a crying warpage. The crying warpage may be a form of warpage in which a center portion of the interposer200may bend upwards and edge portions of the interposer200may bend downwards.

In example embodiments, the first and second grooves600aand600bmay be formed in the molding layer500between the first semiconductor devices300and between the second semiconductor devices400to extend in a direction parallel to adjacent side surfaces of the first and second semiconductor devices300and400. Since the molded interposer includes the first and second grooves, warpage behavior at a high temperature may be minimized, and the rigidity of the molded interposer itself may be reduced to improve solder wettability in the reflow process.

Then, outer connection members such as solder balls may be formed on outer connection pads on a lower surface of the package substrate100respectively to complete the semiconductor package10inFIG.1.

FIG.21is a cross-sectional view illustrating a portion of a semiconductor package according to example embodiments. The semiconductor package may be substantially the same as or similar to the semiconductor package described with reference toFIGS.1to5except for a shape of a groove and a configuration of an additional recess. Thus, same reference numerals will be used to refer to the same or like elements and repetitive explanation concerning the above elements will be omitted.

Referring toFIG.21, a molding layer500may have a first groove600aextending in a direction parallel to adjacent side surfaces of second semiconductor devices400between adjacent second semiconductor devices400. A first depth D1of the first groove600amay be equal to a first height of the second semiconductor device400. An interposer200may be exposed on a bottom surface of the first groove600a.

In example embodiments, the interposer200may have a first recess280connected to the first groove600a. For example, the first recess280and the first groove600amay be continuously and integrally formed as shown inFIG.21. The first recess280may be provided in a wiring layer220of the interposer200. Alternatively, the first recess280may penetrate a portion of the wiring layer220of the interposer200and extend from an upper surface of a semiconductor substrate210to a predetermined depth. For example, the first recess280may extend from a top surface of the interposer200to a portion of the semiconductor substrate210, e.g., below a top surface of the semiconductor substrate210.

The first recess280of the interposer200may be formed together when forming the first groove600a. Processes the same as or similar to the processes described with reference toFIG.17may be performed to remove a portion of the molding layer500and a portion of the interposer200to form the first groove600aand the first recess280. The first groove600aand the first recess280may form one first trench extending between the second semiconductor devices400, e.g., in a direction parallel to adjacent side surfaces of the second semiconductor devices400.

Additionally, the molding layer500may have a second groove600bextending in a direction parallel to adjacent side surfaces of first semiconductor devices300between adjacent first semiconductor devices300. A second depth of the second groove600bmay be equal to a second height of the second semiconductor devices400. The interposer200may be exposed on a bottom surface of the second groove600b. In this case, the interposer200may have a second recess connected to the second groove600b, e.g., similarly to the first groove600aand the first recess280. The second groove600band the second recess may form one second trench extending between the first semiconductor devices. The first and second trenches may extend along a center line of the interposer200, e.g., in a plan view, to communicate with each other.

FIG.22is a cross-sectional view illustrating a portion of a semiconductor package according to example embodiments. The semiconductor package may be substantially the same as or similar to the semiconductor package described with reference toFIGS.1to5except for a shape of a groove and a configuration of an additional recess. Thus, same reference numerals will be used to refer to the same or like elements and repetitive explanation concerning the above elements will be omitted.

Referring toFIG.22, a molding layer500may have a first groove600aextending in one direction between adjacent second semiconductor devices400. A first width W1of the first groove600amay be equal to a first gap between the second semiconductor devices400. A side surface of the second semiconductor device400may be exposed on a sidewall of the first groove600a.

In example embodiments, the second semiconductor device400may have a third recess440connected to the first groove600a. The third recesses440may be provided in the side surfaces of the second semiconductor devices400opposite to each other. A bottom surface of the third recess440may be coplanar with a bottom surface of the first groove600a. For example, second semiconductor devices400may have side surfaces facing the first groove600aformed in the molding layer500, and the side surfaces of the second semiconductor devices400may have step structures as shown inFIG.22.

The third recess440of the second semiconductor device400may be formed together when forming the first groove600a. Processes the same as or similar to the processes described with reference toFIG.17may be performed to remove a portion of the molding layer500and a portion of the second semiconductor device400to form the first groove600aand the third recess440. The first groove600aand the third recess440may form a third trench extending between the second semiconductor devices400.

The molding layer500may have a second groove extending in one direction between adjacent first semiconductor devices300. A second width of the second groove may be equal to a second gap between the first semiconductor devices300. A side surface of the first semiconductor device300may be exposed on a sidewall of the second groove. In this case, the first semiconductor device300may have a fourth recess connected to the second groove. The second groove and the fourth recess may form a fourth trench extending between the first semiconductor devices300. The third and fourth trenches may extend along a center line of the interposer200, e.g., in a plan view, to communicate with each other. For example, the first semiconductor devices300may have side surfaces facing the second groove600bformed in the molding layer500, and the side surfaces of the first semiconductor devices300may have step structures similarly to the side surfaces of the second semiconductor devices400shown inFIG.22.

FIG.23is a plan view illustrating a semiconductor package according to example embodiments. The semiconductor package may be substantially the same as or similar to the semiconductor package described with reference toFIGS.1to5except for an arrangement of grooves. Thus, same reference numerals will be used to refer to the same or like elements and repetitive explanation concerning the above elements will be omitted.

Referring toFIG.23, a molding layer500of a semiconductor package11may have a plurality of grooves600arranged in a lattice form between first and second semiconductor devices300and400.

For example, the molding layer500may include first grooves600aextending in a first direction (X direction) between the second semiconductor devices400, a second groove600bextending in the first direction (X direction) between the first semiconductor devices300, and third grooves600cextending in a second direction (Y direction) between the first semiconductor devices300and the second semiconductor devices400.

In example embodiments, the third grooves600cmay intersect with and/or be connected to the first grooves600a. The third grooves600cmay extend to intersect with and/or be connected to the first grooves600aspaced apart from each other along a first side surface S1. The third grooves600cmay extend to intersect and/or be connected to the first grooves600aspaced apart from each other along a second side surface S2.

The first and second semiconductor devices300and400may have a rectangular plate shape having four side surfaces. At least two grooves may be provided to extend along at least two of the four side surfaces of each semiconductor device respectively, e.g., in a plan view.

FIG.24is a plan view illustrating a semiconductor package according to example embodiments.FIG.25is a cross-sectional view taken along the line G-G′ inFIG.24. The semiconductor package may be substantially the same as or similar to the semiconductor package described with reference toFIGS.1to5except for an additional dummy member. Thus, same reference numerals will be used to refer to the same or like elements and repetitive explanation concerning the above elements will be omitted.

Referring toFIGS.24and25, a semiconductor package12may include a dummy member550arranged between second semiconductor devices400on an interposer200. The semiconductor package12may further include another dummy member arranged between first semiconductor devices300or between a first semiconductor device300and a second semiconductor device400.

In example embodiments, the dummy member550may extend in a first direction (X direction) along a center line ML between the second semiconductor devices400. For example, the dummy member550may vertically overlap the center line ML of the interposer200. The dummy member550may be attached to an upper surface of the interposer200by an adhesive film such as a die attach film (DAF). For example, the dummy member550may include or be formed of a silicon material. For example, the dummy member550may be a semiconductor chip, e.g., a silicon chip, which does not include any circuit and any electronic device in the semiconductor chip.

The dummy member550may have a third height H3smaller than a height H1of the second semiconductor device400. The third height H3of the dummy member550may be 30% to 60% of the height H1of the second semiconductor device400. A third width W3of the dummy member550may be 50% to 90% of the gap between the second semiconductor devices400, e.g., at which the dummy member550is disposed.

The molding layer500may be provided on the upper surface of the interposer200to cover the first and second semiconductor devices300and400and the dummy member550. The molding layer500may cover an upper surface and a side surface of the dummy member550. A first groove600amay be located above the dummy member550. For example, the first groove600amay vertically overlap the dummy member550.

Hereinafter, a method of manufacturing the semiconductor package inFIG.24will be explained.

FIGS.26to29are cross-sectional views illustrating a method of manufacturing a semiconductor package according to example embodiments.

Referring toFIG.26, first, processes the same as or similar to the processes described with reference toFIGS.6to11may be performed to mount a plurality of semiconductor devices300and400on an interposer200. Then, a dummy member550may be arranged on the interposer200between the second semiconductor devices400.

In example embodiments, the dummy member550may be disposed on a wiring layer220to extend in a first direction (X direction) along a center line ML between the second semiconductor devices400. The dummy member550may be attached on the wiring layer220by adhesive films such as a die attach film (DAF). For example, the dummy member550may include or be formed of a silicon material.

The dummy member550may have a height smaller than a height of the second semiconductor device400. The height of the dummy member550may be 30% to 60% of the height of the second semiconductor device400.

Referring toFIGS.27and28, a molding material50may be formed on the wiring layer220to cover the first and second semiconductor devices300and400and the dummy member550, and an upper surface of the molding material50may be partially removed to form a molding layer500that exposes upper surfaces of the first and second semiconductor devices300and400.

Referring toFIG.29, the molding layer500between the first and second semiconductor devices300and400may be partially removed to form grooves600aand600b. The groove may be formed by removing a portion of the molding layer500using a blade, laser, plasma, or the like.

As illustrated inFIG.29, a first groove600amay be formed in the molding layer500to extend in a direction between the second semiconductor devices400. The first groove600amay have a first depth D1from an upper surface502of the molding layer500. The first groove600amay be located above the dummy member550.

Then, processes the same as or similar to the processes described with reference toFIGS.19and20may be performed to complete the semiconductor package12inFIG.24.

FIG.30is a cross-sectional view illustrating a portion of a semiconductor package according to example embodiments. The semiconductor package may be substantially the same as or similar to the semiconductor package described with reference toFIGS.24and25except for a shape of a groove and a configuration of an additional recess. Thus, same reference numerals will be used to refer to the same or like elements and repetitive explanation concerning the above elements will be omitted.

Referring toFIG.30, a molding layer500may have a first groove600aextending in a direction between adjacent second semiconductor devices400. A first depth D1of the first groove600amay be equal to a difference between a first height H1of the second semiconductor device400and a third height H3of a dummy member550. The dummy member550may be exposed on a bottom surface of the first groove600a.

In example embodiments, the dummy member550may have a fifth recess560connected to the first groove600a. The fifth recess560may be provided in an upper surface of the dummy member550.

The fifth recess560of the dummy member550may be formed together when forming the first groove600a. Processes the same as or similar to the processes described with reference toFIG.29may be performed to remove a portion of the molding layer500and a portion of the dummy member550to form the first groove600aand the fifth recess560. The first groove600aand the fifth recess560may form one fifth trench extending between the second semiconductor devices400. For example, the fifth recess560and the first groove600amay be integrally formed, e.g., in the same process and/or as a continuous one pattern.

FIG.31is a cross-sectional view illustrating a portion of a semiconductor package according to example embodiments. The semiconductor package may be substantially the same as or similar to the semiconductor package described with reference toFIGS.24and25except for a shape of a groove and a configuration of an additional recess. Thus, same reference numerals will be used to refer to the same or like elements and repetitive explanation concerning the above elements will be omitted.

Referring toFIG.31, a molding layer500may have a first groove600aextending in a direction between adjacent second semiconductor devices400. The first groove600amay be located above a dummy member550. A first width W1of the first groove600amay be equal to a first gap between the second semiconductor devices400. A side surface of the second semiconductor device400may be exposed on a sidewall of the first groove600a. The dummy member550may be exposed on a bottom surface of the first groove600a.

In example embodiments, the second semiconductor device400may have a third recess440connected to the first groove600a. The third recesses440may be provided in the side surfaces of the second semiconductor devices400opposite to each other. A bottom surface of the third recess440may be coplanar with a bottom surface of the first groove600a.

The third recess440of the second semiconductor device400may be formed together when forming the first groove600a. Processes the same as or similar to the processes described with reference toFIG.29may be performed to remove a portion of the molding layer500and a portion of the second semiconductor device400to form the first groove600aand the third recess440. The first groove600aand the third recess440may form one third trench extending between the second semiconductor devices400. For example, the second semiconductor devices400on which the third recess440is formed may have step structures on the side surfaces. For example, the step structures of the second semiconductor devices400may be integrally formed with the first groove600a.

FIG.32is a plan view illustrating a semiconductor package according to example embodiments. The semiconductor package may be substantially the same as or similar to the semiconductor package described with reference toFIGS.1to5except for a configuration of first semiconductor devices300and grooves600formed between the first semiconductor devices300. Thus, same reference numerals will be used to refer to the same or like elements and repetitive explanation concerning the above elements will be omitted.

Referring toFIG.32, a first semiconductor device300of a semiconductor package13may include a plurality of chiplets300a,300b,300c, and300dspaced apart from each other, e.g., in horizontal directions. Each of the chiplets300a,300b,300cand300dmay be an integrated circuit block designed to work with other similar chiplets to form one larger semiconductor chip.

In example embodiments, the molding layer500may further have a plurality of fourth grooves600dextending between the chiplets300a,300b,300c, and300dof the first semiconductor device300.

The fourth grooves600dmay be arranged in a grid shape to correspond to the arrangement of the chiplets300a,300b,300c, and300d. The fourth grooves600dmay extend to intersect with and/or be connected to each other. The fourth grooves600dmay extend to intersect with and/or be connected to the third grooves600c.

The semiconductor packages described above may include or may be semiconductor devices such as logic devices or memory devices. The semiconductor packages may include or may be logic devices such as central processing units (CPUs), main processing units (MPUs), or application processors (APs), or the like, and volatile memory devices such as DRAM devices, HBM devices, or non-volatile memory devices such as flash memory devices, PRAM devices, MRAM devices, ReRAM devices, or the like.

The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in example embodiments without materially departing from the novel teachings and advantages of the present invention. Accordingly, all such modifications are intended to be included within the scope of example embodiments as defined in the claims.