Patent ID: 12254943

DETAILED DESCRIPTION

How to test whether the duty cycle of a high-speed clock signal meets requirements, how to ensure the accuracy of testing a high-speed clock signal, and how to generate equidistant parallel clock signals based on the high-speed clock signal are urgent problems to be solved at present.

An embodiment of the disclosure provides a signal detection system. Different test paths are selected to test whether duty cycles of a high-speed clock signal in different transmission paths meets requirements, to ensure the stability of data processing in a memory.

A person of ordinary skill in the art may understand that in the embodiments of the disclosure, many technical details are provided for a reader to better understand the disclosure. However, even in the absence of these technical details and various changes and modifications based on the following embodiments, the technical solution that the disclosure seek to protect can be implemented. The divisions in the following embodiments are for ease of description but should not constitute any limitation to specific embodiments of the disclosure. Various embodiments may be combined with each other or used as references for each other without causing any conflict.

The signal detection system provided in this embodiment is further described below in detail with reference to the accompanying drawings. Details are as follows:

A signal detection system1000is applied to a memory, and is configured to perform a duty cycle test on output signals of test paths in the memory according to a test circuit in the memory.

Referring toFIG.1, the signal detection system1000includes:a signal generator100, configured to generate a reference test signal AltWck based on an external parameter, the reference test signal AltWck being a clock signal satisfying a preset duty cycle.

The duty cycle test is performed on the reference test signal AltWck based on a test circuit400, to determine whether a function of the test circuit400is normal. If the function of the test circuit400is normal, different portions under test are sequentially selected based on a test control signal DemCtrl, and the duty cycle test is performed, based on the test circuit400, on a signal outputted by each of the selected portions under test.

The portions under test include a signal conversion circuit1002and a write clock path1003. The signal conversion circuit1002is configured to generate an internal clock signal PWCK according to the reference test signal AltWck. The write clock path1003includes a write frequency divider1013, a write clock tree1023, and a signal loading circuit805. The write frequency divider1013is configured to generate a parallel write clock Clk_W according to the internal clock signal PWCK. The write clock tree1023has an input terminal connected to an output terminal of the write frequency divider1013and is configured to adjust a delay of an input signal and generate a parallel write clock Clk_W. The signal loading circuit805has an input terminal connected to an output terminal of the write clock tree1023and an output terminal connected to the test circuit400, and is configured to sample preset data according to the parallel write clock Clk_W, to generate a first indication signal Pup and a second indication signal Pdn.

The duty cycle test is performed on the reference test signal AltWck based on the test circuit400. A duty cycle of the reference test signal AltWck is known and is used for determining whether a duty cycle test function of the test circuit400is normal. If the duty cycle test function of the test circuit400is normal, different portions under test are selected based on the test control signal DemCtrl, and duty cycles of output signals of the different portions under test are sequentially tested by using the test circuit400, to test whether the duty cycle of the output signal of each of the different portions under test is normal, thereby completing function test for the different portions under test.

Continuing to refer toFIG.1, in some embodiments, the portions under test further include a read clock path1004. The read clock path1004includes a read frequency divider1014and a read clock conversion circuit1024. The read frequency divider1014is configured to generate a parallel read clock Clk_R1according to the internal clock signal PWCK. The read clock conversion circuit1024is configured to generate a serial read clock Clk_R2according to the parallel read clock Clk_R1.

It needs to be noted that in some embodiments, the write frequency divider1013and the read frequency divider1014in the memory may be implemented based on one frequency divider.

For the signal generator100, referring toFIG.2, the signal generator100includes:an oscillation generation circuit101, configured to generate an initial oscillation signal Osc0based on an oscillation control signal OscAdj, the oscillation control signal OscAdj being used for adjusting a frequency of the generated initial oscillation signal Osc0;a duty cycle correction circuit102, connected to an output terminal of the oscillation generation circuit101, the duty cycle correction circuit102being configured to adjust a duty cycle of the initial oscillation signal Osc0based on a duty cycle control signal Duty to generate an intermediate test signal Pretest; andan amplitude adjustment circuit103, connected to an output terminal of the duty cycle correction circuit102, the amplitude adjustment circuit103being configured to adjust an amplitude of the intermediate test signal Pretest based on an amplitude control signal OBControl to generate the reference test signal AltWck.

For the oscillation generation circuit101, referring toFIG.3, in some embodiments, the oscillation generation circuit101includes a ring oscillator. The ring oscillator is configured to generate the initial oscillation signal Osc0based on the oscillation control signal OscAdj. The oscillation control signal OscAdj is used for adjusting a number of inverters connected to the ring oscillator. It may be understood that the number of inverters connected to the ring oscillator is related to an oscillation frequency of the initial oscillation signal Osc0. Specifically, when more inverters are connected to the ring oscillator, the oscillation frequency of the initial oscillation signal Osc0is lower. Referring toFIG.4, in some embodiments, the oscillation generation circuit101includes a tetrahedral oscillator. The tetrahedral oscillator includes inner ring inverters and outer ring inverters. The outer ring inverters have the same driving capability. The inner ring inverters have the same driving capability. The driving capability of the inner ring inverters is 0.3 to 0.8 times the driving capability of the outer ring inverters. For the tetrahedral oscillator, the tetrahedral oscillator is configured to generate the initial oscillation signal Osc0based on the oscillation control signal OscAdj, and the oscillation control signal OscAdj is used for adjusting the driving capability of the inner ring inverters. In an example, the oscillation control signal OscAdj is used for adjusting the driving capability of transistors forming the inner ring inverters to adjust the driving capability of the inner ring inverters. It may be understood that when the driving capability of the inner ring inverters in the tetrahedral oscillator is higher, a delay caused by the inverters is shorter, and the frequency of the initial oscillation signal Osc0generated by the oscillation generation circuit101is higher. During actual application, a ratio of the driving capability of the inner ring inverters to the driving capability of the outer ring inverters may be changed to control the frequency of the initial oscillation signal Osc0generated by the oscillation generation circuit101. In an example, the driving capability of the inner ring inverters may be set to 0.4 times, 0.5 times, 0.6 times or 0.7 times the driving capability of the outer ring inverters. Preferably, the driving capability of the inner ring inverters is set to 0.7 times the driving capability of the outer ring inverters, to increase the frequency of the initial oscillation signal Osc0generated by the oscillation generation circuit101. In a specific example, the outer ring inverters include a first inverter1, a second inverter2, a third inverter3, and a fourth inverter4. The inner ring inverters include a fifth inverter5, a sixth inverter6, a seventh inverter7, and an eighth inverter8. An output terminal of the first inverter1is connected to an input terminal of the second inverter2. An output terminal of the second inverter2is connected to an input terminal of the third inverter3. An output terminal of the third inverter3is connected to an input terminal of the fourth inverter4. An output terminal of the fourth inverter4is connected to an input terminal of the first inverter1. The fifth inverter5has an input terminal connected to the output terminal of the first inverter1and an output terminal connected to the input terminal of the fourth inverter4. The sixth inverter6has an input terminal connected to the output terminal of the second inverter2and an output terminal connected to the input terminal of the first inverter1. The seventh inverter7has an input terminal connected to the output terminal of the third inverter3and an output terminal connected to the input terminal of the second inverter2. The eighth inverter8has an input terminal connected to the output terminal of the fourth inverter4and an output terminal connected to the input terminal of the third inverter3.

For the duty cycle correction circuit102, referring toFIG.5, the duty cycle correction circuit102includes: a first adjustment unit112, connected to the oscillation generation circuit101, the first adjustment unit112being configured to increase the duty cycle of the initial oscillation signal Osc0to generate a first adjustment signal T1; a second adjustment unit122, connected to the oscillation generation circuit101, the second adjustment unit122being configured to decrease the duty cycle of the initial oscillation signal Osc0to generate a second adjustment signal T2; and a calibration unit132, connected to the first adjustment unit112and the second adjustment unit122, the calibration unit132being configured to generate the intermediate test signal Pretest according to the duty cycle control signal Duty, the first adjustment signal T1, and the second adjustment signal T2. The duty cycle control signal Duty is used for adjusting a signal proportion of the first adjustment signal T1and a signal proportion of the second adjustment signal T2in the generated intermediate test signal Pretest.

For the first adjustment unit112and the second adjustment unit122, referring toFIG.6, the first adjustment unit112and the second adjustment unit122delay a rising edge and a falling edge of a signal to different degrees to adjust the duty cycle of the signal. For example, a rising edge of an initial signal is delayed by t1, and a falling edge of the initial signal is delayed by t2. When t1>t2, an interval between the rising edge and the falling edge of the signal after the delays is shortened, and the duty cycle of the signal is reduced. When t1<t2, the interval between the rising edge and the falling edge of the signal after the delays is extended, and the duty cycle of the signal is increased.

In a specific example, referring toFIG.7, the first adjustment unit112includes a first P-type switch transistor <KP1>, a first N-type switch transistor <KN1>, a second P-type switch transistor <KP2>, and a second N-type switch transistor <KN2>. A gate electrode of the first P-type switch transistor <KP1> is connected to a gate electrode of the first N-type switch transistor <KN1>, and is configured to receive the initial oscillation signal Osc0. A source electrode of the first P-type switch transistor <KP1> is connected to a drain electrode of a first pull-up transistor <LP1>. A source electrode of the first pull-up transistor <LP1> is configured to receive a high level. A source electrode of the first N-type switch transistor <KN1> is connected to a drain electrode of a first pull-down transistor <LN1>. A source electrode of the first pull-down transistor <LN1> is configured to receive a low level. A drain electrode of the first P-type switch transistor <KP1> is connected to a drain electrode of the first N-type switch transistor <KN1>, and connects a gate electrode of the second P-type switch transistor <KP2> and a gate electrode of the second N-type switch transistor <KN2>. A source electrode of the second P-type switch transistor <KP2> is connected to a drain electrode of a second pull-up transistor <LP2>. A source electrode of the second pull-up transistor <LP2> is configured to receive a high level. A source electrode of the second N-type switch transistor <KN2> is connected to a drain electrode of a second pull-down transistor <LN2>. A source electrode of the second pull-down transistor <LN2> is configured to receive a low level. The second P-type switch transistor <KP2> is connected to a drain electrode of the second N-type switch transistor <KN2>, and is configured to output the first adjustment signal T1. The first pull-up transistor <LP1> and the first pull-down transistor <LN1> are turned on based on the duty cycle control signal Duty, and the driving capability of the first pull-down transistor <LN1> is greater than the driving capability of the first pull-up transistor <LP1>. The second pull-up transistor <LP2> and the second pull-down transistor <LN2> are turned on based on the duty cycle control signal Duty, and the driving capability of the second pull-down transistor <LN2> is less than the driving capability of the second pull-up transistor <LP2>. The second adjustment unit122includes a third P-type switch transistor <KP3>, a third N-type switch transistor <KN3>, a fourth P-type switch transistor <KP4>, and a fourth N-type switch transistor <KN4>. A gate electrode of the third P-type switch transistor <KP3> is connected to a gate electrode of the third N-type switch transistor <KN3>, and is configured to receive the initial oscillation signal Osc0. A source electrode of the third P-type switch transistor <KP3> is connected to a drain electrode of a third pull-up transistor <LP3>. A source electrode of the third pull-up transistor <LP3> is configured to receive a high level. A source electrode of the third N-type switch transistor <KN3> is connected to a drain electrode of a third pull-down transistor <LN3>. A source electrode of the third pull-down transistor <LN3> is configured to receive a low level. A drain electrode of the third P-type switch transistor <KP3> is connected to a drain electrode of the third N-type switch transistor <KN3>, and connects a gate electrode of the fourth P-type switch transistor <KP4> and a gate electrode of the fourth N-type switch transistor <KN4>. A source electrode of the fourth P-type switch transistor <KP4> is connected to a drain electrode of a fourth pull-up transistor <LP4>. A source electrode of the fourth pull-up transistor <LP4> is configured to receive a high level. A source electrode of the fourth N-type switch transistor <KN4> is connected to a drain electrode of a fourth pull-down transistor <LN4>. A source electrode of the fourth pull-down transistor <LN4> is configured to receive a low level. The fourth P-type switch transistor <KP4> is connected to a drain electrode of the fourth N-type switch transistor <KN4>, and is configured to output the second adjustment signal T2. The third pull-up transistor <LP3> and the third pull-down transistor <LN3> are turned on based on the duty cycle control signal Duty, and the driving capability of the third pull-down transistor <LN3> is greater than the driving capability of the third pull-up transistor <LP3>. The fourth pull-up transistor <LP4> and the fourth pull-down transistor <LN4> are turned on based on the duty cycle control signal Duty, and the driving capability of the fourth pull-down transistor <LN4> is less than the driving capability of the fourth pull-up transistor <LP4>. It needs to be noted that the first pull-up transistor <LP1>, the first pull-down transistor <LN1>, the second pull-up transistor <LP2>, the second pull-down transistor <LN2>, the third pull-up transistor <LP3>, the third pull-down transistor <LN3>, the fourth pull-up transistor <LP4>, and the fourth pull-down transistor <LN4> may be directly turned on according to the duty cycle control signal Duty or may be turned on according to a duty cycle enable signal. The duty cycle enable signal is generated based on the duty cycle control signal Duty. For the first adjustment unit112, because the driving capability of the second pull-up transistor <LP2> is greater than the driving capability of the second pull-down transistor <LN2>, it is easy to pull up but difficult to pull down the first adjustment signal T1. Therefore, compared with the initial oscillation signal Osc0, for the first adjustment signal T1, the delay of the rising edge is small, and the delay of the rising edge is large. For the second adjustment unit122, because the driving capability of the fourth pull-up transistor <LP4> is less than the driving capability of the fourth pull-down transistor <LN4>, it is easy to pull down but difficult to pull up the second adjustment signal T2. Therefore, compared with the initial oscillation signal Osc0, for the second adjustment signal T2, the delay of the rising edge is large, and the delay of the rising edge is small.

In some embodiments, the driving capability of the first pull-up transistor <LP1>, the driving capability of the second pull-down transistor <LN2>, the driving capability of the third pull-down transistor <LN3>, and the driving capability of the fourth pull-up transistor <LP4> are the same. The driving capability of the first pull-down transistor <LN1>, the driving capability of the second pull-up transistor <LP2>, the driving capability of the third pull-up transistor <LP3>, and the driving capability of the fourth pull-down transistor <LN4> are the same. Continuing to refer toFIG.7, specifically, the driving capability of the first pull-up transistor <LP1>, the driving capability of the second pull-down transistor <LN2>, the driving capability of the third pull-down transistor <LN3>, and the driving capability of the fourth pull-up transistor <LP4> are B. The driving capability of the first pull-down transistor <LN1>, the driving capability of the second pull-up transistor <LP2>, the driving capability of the third pull-up transistor <LP3>, and the driving capability of the fourth pull-down transistor <LN4> are A. The driving capability represented by A is greater than the driving capability represented by B. It is set that the driving capability of the first pull-up transistor <LP1>, the driving capability of the second pull-down transistor <LN2>, the driving capability of the third pull-down transistor <LN3>, and the driving capability of the fourth pull-up transistor <LP4> are the same, it is set that the driving capability of the first pull-down transistor <LN1>, the driving capability of the second pull-up transistor <LP2>, the driving capability of the third pull-up transistor <LP3>, and the driving capability of the fourth pull-down transistor <LN4> are the same, the same transistor is used to control an adjustment capability of a rising edge by the first adjustment unit112to be the same as an adjustment capability of a falling edge by the second adjustment unit122, and the same transistor is used to control an adjustment capability of a falling edge by the first adjustment unit112to be the same as an adjustment capability of a rising edge by the second adjustment unit122, so that a total delay of adjustment of a rising edge and a falling edge of the first adjustment unit112is consistent with a total delay of a rising edge and a falling edge of the second adjustment unit122, to ensure that the first adjustment signal T1and the second adjustment signal T2have the same period, making it convenient for the calibration unit132to adjust the duty cycles of the first adjustment signal T1and the second adjustment signal T2.

In this embodiment, the first adjustment unit112and the second adjustment unit122further include a correction transistor group142. The correction transistor group142includes x correction transistors disposed in parallel. In the x correction transistors, the driving capability of an nth correction transistor is twice the driving capability of an (n−1)thcorrection transistor, where x is an integer greater than or equal to 2, and n is any integer less than or equal to x and greater than or equal to 2. Further, the duty cycle control signal Duty is further used for selecting to turn on a correction transistor in the correction transistor group142. In this case, the driving capability of the correction transistor group142is equivalent driving capability of a plurality of correction transistors that are turned on. The correction transistor group142is separately disposed in parallel to the first pull-up transistor <LP1>, the first pull-down transistor <LN1>, the second pull-up transistor <LP2>, the second pull-down transistor <LN2>, the third pull-up transistor <LP3>, the third pull-down transistor <LN3>, the fourth pull-up transistor <LP4>, and the fourth pull-down transistor <LN4>, and the type of a correction transistor in the correction transistor group142is the same as the type of a transistor connected in parallel. In a specific example, continuing to refer toFIG.7, the correction transistor group142includes a first correction transistor, a second correction transistor, a third correction transistor, a fourth correction transistor, and a fifth correction transistor. The driving capability of the first correction transistor is C, the driving capability of the second correction transistor is 2 C, the driving capability of the third correction transistor is 4 C, the driving capability of the fourth correction transistor is 8 C, and the driving capability of the fifth correction transistor is 16 C. A first driving transistor, a second driving transistor, a third driving transistor, a fourth driving transistor, and a fifth driving transistor are selectively turned on based on the duty cycle control signal Duty, to control the first adjustment unit112and the second adjustment unit122to perform a signal delay to different degrees on the initial oscillation signal Osc0. It needs to be noted that the foregoing “C” represents a preset unit value, and may be correspondingly designed according to a circuit design in actual application. The foregoing description is only used for reflecting a multiple relationship of the driving capability between correction transistors. It needs to be noted that the plurality of correction transistors in the correction transistor group142may be disposed in parallel in this embodiment. In other embodiments, the plurality of correction transistors in the correction transistor group may be disposed in series or may be disposed in the form of a series and parallel combination.

For the calibration unit132, referring toFIG.8, the calibration unit132includes: a plurality of first driving subunits that are disposed in parallel to each other, each having an input terminal connected to the first adjustment unit112and further configured to receive the duty cycle control signal Duty; a plurality of second driving subunits that are disposed in parallel to each other, each having an input terminal connected to the second adjustment unit122and further configured to receive the duty cycle control signal Duty, where the duty cycle control signal Duty is used for selectively turning on the plurality of first driving subunits and the plurality of second driving subunits; and a third driving subunit213, having an input terminal connected to an output terminal of each first driving subunit and an output terminal of each second driving subunit and an output terminal configured to output the intermediate test signal Pretest. Specifically, when the driving capability of the plurality of first driving subunits is greater than the driving capability of the plurality of second driving subunits, the duty cycle of the intermediate test signal Pretest outputted by the third driving subunit213is biased toward the first adjustment signal T1. That is, in the intermediate test signal Pretest generated according to the first adjustment signal T1and the second adjustment signal T2, the proportion of the first adjustment signal T1is larger. When the driving capability of the plurality of second driving subunits is greater than the driving capability of the plurality of first driving subunits, the duty cycle of the intermediate test signal Pretest outputted by the third driving subunit213is biased toward the second adjustment signal T2. That is, in the intermediate test signal Pretest generated according to the first adjustment signal T1and the second adjustment signal T2, the proportion of the second adjustment signal T2is larger. It may be understood that the driving capability of the plurality of first driving subunits is an equivalent driving capability of first driving subunits that are turned on in the plurality of first driving subunits. Similarly, the driving capability of the plurality of second driving subunits is an equivalent driving capability of second driving subunits that are turned on in the plurality of second driving subunits.

In this embodiment, continuing to refer toFIG.8, the signal generator100includes a first inverter group211, configured to receive the duty cycle control signal Duty, where the first inverter group211includes a plurality of first adjustment inverters201connected in parallel, each first adjustment inverter201is used as one first driving subunit, and the duty cycle control signal Duty is used for selectively turning on the first adjustment inverters201in the first inverter group211; and a second inverter group212, having an input terminal connected to the second adjustment unit122and further configured to receive the duty cycle control signal Duty, where the second inverter group212includes a plurality of second adjustment inverters202connected in parallel, each second adjustment inverter202is used as one second driving subunit, and the duty cycle control signal Duty is used for selectively turning on the second adjustment inverters202in the second inverter group212. The third driving subunit213includes a third adjustment inverter203, having an input terminal connected to an output terminal of the first inverter group211and an output terminal of the second inverter group212, and an output terminal configured to output the intermediate test signal Pretest. Because the first inverter group211includes the plurality of first adjustment inverters201connected in parallel and the second inverter group212includes the plurality of second adjustment inverters202connected in parallel, when more inverters connected in parallel are turned on, the first adjustment inverters201or the second adjustment inverters202as a whole have a higher driving capability. That is, numbers of the first adjustment inverters201and the second adjustment inverters202that are turned on in the first inverter group211and the second inverter group212are controlled to adjusting the duty cycle of the intermediate test signal Pretest.

In a specific example, referring toFIG.8in combination withFIG.9, it is assumed that the first inverter group211includes three first adjustment inverters201and the second inverter group212includes three second adjustment inverters202. That is, the calibration unit includes three first driving subunits and three second driving subunits. In this case, the conduction of the first driving subunits and the second driving subunits may include the following cases: (1) Three first driving subunits and zero second driving subunits are turned on. In this case, the intermediate test signal Pretest and the first adjustment signal T1have the same duty cycle, and a duration of a high-level signal is tpH3. (2) Two first driving subunits and one second driving subunits are turned on. In this case, the intermediate test signal Pretest is biased toward the first adjustment signal T1, and the duration of the high-level signal is tpH2. (3) One first driving subunit and two second driving subunits are turned on. In this case, the intermediate test signal Pretest is biased toward the second adjustment signal T2, and the duration of the high-level signal is tpH1. (4) Zero first driving subunits and three second driving subunits are turned on. In this case, the intermediate test signal Pretest and the second adjustment signal T2have the same duty cycle, and the duration of the high-level signal is tpH0.

For the amplitude adjustment circuit103, referring toFIG.10, the amplitude adjustment circuit103includes: a first signal generation unit113, configured to pull up an output signal based on the intermediate test signal Pretest and pull down an output signal based on an inverted test signal Pretest− to generate the reference test signal AltWck with the same phase as the intermediate test signal Pretest; and a second signal generation unit123, configured to pull up an output signal based on the inverted test signal Pretest− and pull down an output signal based on the intermediate test signal Pretest to generate an inverted reference test signal AltWck− with the same phase as the inverted test signal Pretest−. The intermediate test signal Pretest and the inverted test signal Pretest− have the same amplitude but opposite phases. Specifically, a first driving transistor <QN1> has a gate electrode configured to receive the intermediate test signal Pretest and a drain electrode configured to receive a high level. A second driving transistor <QN2> has a gate electrode configured to receive the inverted test signal Pretest− and a source electrode configured to receive a low level. A source electrode of the first driving transistor <QN1> is connected to a drain electrode of the second driving transistor <QN2> and is configured to output the reference test signal AltWck. The amplitude control signal OBControl is used for adjusting the driving capability of the first driving transistor <QN1>. It needs to be noted that in this embodiment, the amplitude control signal OBControl adjusts the driving capability of the first driving transistor <QN1> to change the driving capability of the first signal generation unit113. In other embodiments, it may be set that the amplitude control signal adjusts the driving capability of the second driving transistor or jointly adjusts the first driving transistor and the second driving transistor to change the driving capability of the first signal generation unit. The second signal generation unit123includes a third driving transistor and a fourth driving transistor. A third driving transistor <QN3> has a gate electrode configured to receive the intermediate test signal Pretest and a drain electrode configured to receive a high level. A fourth driving transistor <QN4> has a gate electrode configured to receive the inverted test signal Pretest− and a source electrode configured to receive a low level. A source electrode of the third driving transistor <QN3> is connected to a drain electrode of the fourth driving transistor <QN4> and is configured to output the inverted reference test signal AltWck−. The amplitude control signal OBControl is used for adjusting the driving capability of the third driving transistor <QN3>. It needs to be noted that in this embodiment, the amplitude control signal OBControl adjusts the driving capability of the third driving transistor <QN3> to change the driving capability of the second signal generation unit123. In other embodiments, it may be set that the amplitude control signal adjusts the driving capability of the fourth driving transistor or jointly adjusts the third driving transistor and the fourth driving transistor to change the driving capability of the second signal generation unit. In an example, the amplitude control signal OBControl may change aspect ratios or substrate voltages of the first driving transistor <QN1> and the third driving transistor <QN3> to adjust the driving capability of the first driving transistor <QN1> and the third driving transistor <QN3>. Similarly, the driving capability of the second driving transistor and the driving capability of the fourth driving transistor may be adjusted in a similar manner. Further, the first signal generation unit113may include a first switch transistor <B1>, a second switch transistor <B2>, and a first anti-interference transistor <B3>. The first switch transistor <B1> has a source electrode coupled to a power supply node, a drain electrode connected to a drain electrode of the first driving transistor <QN1>, and a gate electrode configured to receive the amplitude control signal OBControl, and the second switch transistor <B2> has a source electrode coupled to a ground wire node, a drain electrode connected to a drain electrode of the second driving transistor <QN2>, and a gate electrode configured to receive the amplitude control signal OBControl, so as to be turned on after the amplitude control signal OBControl is received, thereby reducing the power consumption of the first signal generation unit113during idle time. In addition, the first anti-interference transistor <B3> is connected in parallel to the second driving transistor <QN2> and has a gate electrode configured to receive the amplitude control signal OBControl. The amplitude control signal OBControl is further used for adjusting the driving capability of the first anti-interference transistor <B3>, to adjust the anti-interference capability of the first anti-interference transistor <B3>. Because the driving capability of the first driving transistor <QN1> may be adjusted based on the amplitude control signal OBControl, that is, when the driving capability of the first driving transistor <QN1> is large, the outputted reference test signal AltWck has a large amplitude, and a high anti-interference capability is required. When the driving capability of the first driving transistor <QN1> is small, the outputted reference test signal AltWck has a low amplitude, and a low anti-interference capability is required. Therefore, the amplitude control signal OBControl is used to correspondingly adjust the anti-interference capability of the first anti-interference transistor <B3>, to ensure the accuracy of the reference test signal AltWck generated by the first signal generation unit113and reduce the power consumption of the first anti-interference transistor <B3>. In this embodiment, the amplitude control signal OBControl is further used for enabling the first switch transistor <B1>, the second switch transistor <B2>, and the first anti-interference transistor <B3> and at the same time adjusting the driving capability of the first anti-interference transistor <B3>. In other embodiments, it may be set that the first switch transistor, the second switch transistor, and the first anti-interference transistor are turned on based on an amplitude enable signal. The amplitude enable signal is generated based on the amplitude control signal. The second signal generation unit123may include a third switch transistor <B4>, a fourth switch transistor <B5>, and a second anti-interference transistor <B6>. The third switch transistor <B4> has a source electrode coupled to a power supply node, a drain electrode connected to a drain electrode of the fourth driving transistor <QN4>, and a gate electrode configured to receive the amplitude control signal OBControl, and the fourth switch transistor <B5> has a source electrode coupled to a ground wire node, a drain electrode connected to a drain electrode of a fifth driving transistor <QN5>, and a gate electrode configured to receive the amplitude control signal OBControl, so as to be turned on after the amplitude control signal OBControl is received, thereby reducing the power consumption of the second signal generation unit123during idle time. In addition, the second anti-interference transistor <B6> is connected in parallel to the fifth driving transistor <QN5> and has a gate electrode configured to receive the amplitude control signal OBControl. The amplitude control signal OBControl is further used for adjusting the driving capability of the second anti-interference transistor <B6>, to adjust the anti-interference capability of the second anti-interference transistor <B6>. Because the driving capability of the third driving transistor <QN3> may be adjusted based on the amplitude control signal OBControl. That is, when the driving capability of the third driving transistor <QN3> is large, the outputted inverted reference test signal AltWck− has a large amplitude, and a high anti-interference capability is required. When the driving capability of the third driving transistor <QN3> is small, the outputted inverted reference test signal AltWck− has a low amplitude, and a low anti-interference capability is required. Therefore, the amplitude control signal OBControl is used to correspondingly adjust the anti-interference capability of the second anti-interference transistor <B6>, to ensure the accuracy of the inverted reference test signal AltWck-generated by the second signal generation unit123and reduce the power consumption of the second anti-interference transistor <B6>. In this embodiment, the amplitude control signal OBControl is further used for enabling the third switch transistor <B4>, the fourth switch transistor <B5>, and the second anti-interference transistor <B6> and at the same time adjusting the driving capability of the second anti-interference transistor <B6>. In other embodiments, it may be set that the third switch transistor, the fourth switch transistor, and the second anti-interference transistor are turned on based on an amplitude enable signal. The amplitude enable signal is generated based on the amplitude control signal. It needs to be noted that this embodiment is described in detail by using an example in which the first signal generation unit113generates the reference test signal AltWck and the second signal generation unit123generates the inverted reference test signal AltWck−, which does not constitute a limitation to this embodiment. In other embodiments, it may be set that the first signal generation unit generates an inverted test signal and the second signal generation unit generates a test signal.

Specifically, in this embodiment, the amplitude adjustment circuit103further includes a signal generation unit300, connected to the amplitude adjustment circuit103and the duty cycle correction circuit102, and configured to generate the inverted test signal Pretest-based on the intermediate test signal Pretest. In a specific example, the first signal generation unit113includes the first driving transistor <QN1> and the second driving transistor <QN2>.

In this embodiment, the amplitude control signal OBControl is further used for controlling the input of the intermediate test signal Pretest and the inverted test signal Pretest−. In a specific example, the signal generator100further includes a first driving unit301and a second driving unit302. The first driving unit301is configured to receive the amplitude control signal OBControl and the intermediate test signal Pretest. The first driving unit301is configured to: if the amplitude control signal OBControl and the intermediate test signal Pretest are simultaneously received, output one of the intermediate test signal Pretest and the inverted test signal Pretest−. The second driving unit302is configured to receive the amplitude control signal OBControl and the inverted test signal Pretest−. The second driving unit302is configured to: if the amplitude control signal OBControl and the inverted test signal Pretest− are simultaneously received, output the other of the intermediate test signal Pretest and the inverted test signal Pretest−. Specifically, if the first driving unit301is designed based on a NAND gate, in this case, if the amplitude control signal OBControl and the intermediate test signal Pretest are simultaneously received, the inverted test signal Pretest− is outputted. If the first driving unit301is designed based on an AND gate, in this case, if the amplitude control signal OBControl and the intermediate test signal Pretest are simultaneously received, the intermediate test signal Pretest is outputted. If the second driving unit302is designed based on a NAND gate, in this case, if the amplitude control signal OBControl and the inverted test signal Pretest− are simultaneously received, the intermediate test signal Pretest is outputted. If the second driving unit302is designed based on an AND gate, in this case, if the amplitude control signal OBControl and the inverted test signal Pretest− are simultaneously received, the inverted test signal Pretest− is outputted. It needs to be noted that in this embodiment, the amplitude control signal OBControl is further used for enabling the first driving unit301and the second driving unit302. In other embodiments, it may be set that the first driving unit and the second driving unit are turned on based on an amplitude enable signal. The amplitude enable signal is generated based on the amplitude control signal. Continuing to refer toFIG.10, because the first driving unit301and the second driving unit302have relatively large device distances from the first signal generation unit113and the second signal generation unit123, the outputted intermediate test signal Pretest and inverted test signal Pretest− may encounter a signal attenuation phenomenon. To avoid this phenomenon, in some embodiments, the amplitude adjustment circuit103further includes a first input adjustment unit310, a second input adjustment unit320, a third input adjustment unit330, and a fourth input adjustment unit340. The first input adjustment unit310is connected to the first signal generation unit113, and is configured to perform driving to provide the intermediate test signal Pretest to the first signal generation unit113. The second input adjustment unit320is connected to the second signal generation unit123, and is configured to perform driving to provide the intermediate test signal Pretest to the second signal generation unit123. The third input adjustment unit330is connected to the first signal generation unit113, and is configured to perform driving to provide the inverted test signal Pretest− to the first signal generation unit113. The fourth input adjustment unit340is connected to the second signal generation unit123, and is configured to perform driving to provide the inverted test signal Pretest− to the second signal generation unit123. In an example, each of the first input adjustment unit310, the second input adjustment unit320, the third input adjustment unit330, and the fourth input adjustment unit340includes an even-numbered quantity of inverters. In another example, each of the first input adjustment unit310, the second input adjustment unit320, the third input adjustment unit330, and the fourth input adjustment unit340includes an odd-numbered quantity of inverters. In this case, the first input adjustment unit310is configured to provide the inverted test signal Pretest− to the first signal generation unit113. The second input adjustment unit320is configured to provide the inverted test signal Pretest− to the second signal generation unit123. The third input adjustment unit330is configured to provide the intermediate test signal Pretest to the first signal generation unit113. The fourth input adjustment unit340is configured to provide the intermediate test signal Pretest to the second signal generation unit123.

Referring toFIG.11, the reference test signal AltWck and the inverted reference test signal AltWck-generated after the intermediate test signal Pretest and the inverted test signal Pretest-pass through the amplitude adjustment circuit103have the same phase and amplitude changing from V1to V2, to meet subsequent use requirements.

For the test circuit400, referring toFIG.12, a first integral circuit401is configured to receive a first test signal Test1, and is configured to integrate the first test signal Test1to output a first integral signal FltNdT. A second integral circuit402is configured to receive a second test signal Test2, and is configured to integrate the second test signal Test2to output a second integral signal FltNdC. The first test signal Test1is a to-be-tested signal inputted into the test circuit400. The first test signal Test1and the second test signal Test2are inverted signals of each other. A voltage value of the first integral signal FltNdT is a product of multiplying a duty cycle of the first test signal Test1by a power supply amplitude. A voltage value of the second integral signal FltNdC is a product of multiplying a duty cycle of the second test signal Test2by the power supply amplitude. A comparison circuit403has an input terminal connected to the first integral circuit401and another input terminal connected to the second integral circuit402. The comparison circuit403is configured to compare the first integral signal FltNdT with the second integral signal FltNdC, output a high-level signal when the first integral signal FltNdT is greater than the second integral signal FltNdC, and output a low-level signal when the second integral signal FltNdC is greater than the first integral signal FltNdT.

Specifically, in this embodiment, referring toFIG.13, the first integral circuit401includes a first filter unit501, a first preprocessing unit510, and a second preprocessing unit520. The first filter unit501is configured to integrate a received signal. That is, the first filter unit501is configured to integrate the first test signal Test1. The first preprocessing unit510includes a first conducting transistor <DT1>, a first P-type precharge transistor <YP1>, and a first N-type precharge transistor <YN1>. The first conducting transistor <DT1> has a drain electrode configured to receive the first test signal Test1, a source electrode connected to an input terminal of the first filter unit501, and a gate electrode configured to receive a first switch signal PassA. The first P-type precharge transistor <YP1> has a source electrode configured to receive a high level, a drain electrode connected to the input terminal of the first filter unit501, and a gate electrode configured to receive an integral charge signal ClampF. The first N-type precharge transistor <YN1> has a source electrode configured to receive a low level, a drain electrode connected to the input terminal of the first filter unit501, and a gate electrode configured to receive a first integral discharge signal ClpGnd. Specifically, the first switch signal PassA is used for starting the first preprocessing unit510. When the first switch signal PassA turns on the first conducting transistor <DT1>, the first filter unit501receives the first test signal Test1and starts to integrate the first test signal Test1. The first P-type precharge transistor <YP1> is turned on based on the integral charge signal ClampF, to indirectly connect the input terminal of the first filter unit501to a high level, so as to pull up a potential at the input terminal of the first filter unit501. The first N-type precharge transistor <YN1> is turned on based on the first integral discharge signal ClpGnd, to indirectly connect the input terminal of the first filter unit501to a low level, so as to pull down the potential at the input terminal of the first filter unit501. The second preprocessing unit520includes a second conducting transistor <DT2>, a second P-type precharge transistor <YP2>, and a second N-type precharge transistor <YN2>. The second conducting transistor <DT2> has a drain electrode connected to an output terminal of the first filter unit501, a source electrode configured to output the first integral signal FltNdT, and a gate electrode configured to receive a second switch signal PassB. The second P-type precharge transistor <YP2> has a source electrode configured to receive a high level, a drain electrode connected to the output terminal of the first filter unit501, and a gate electrode configured to receive the integral charge signal ClampF. The second N-type precharge transistor <YN2> has a source electrode configured to receive a low level, a drain electrode connected to the input terminal of the first filter unit501, and a gate electrode configured to receive the first integral discharge signal ClpGnd. Specifically, the second switch signal PassB is configured to start the second preprocessing unit520. When the second switch signal PassB turns on the second conducting transistor <DT2>, the first integral signal FltNdT obtained through integration by the first filter unit501may be outputted to the comparison circuit403. The second P-type precharge transistor <YP2> is turned on based on the integral charge signal ClampF, to indirectly connect the output terminal of the first filter unit501to a high level, so as to pull up a potential at the output terminal of the first filter unit501. The second N-type precharge transistor <YN2> is turned on based on the first integral discharge signal ClpGnd, to indirectly connect the output terminal of the first filter unit501to a low level, so as to pull down the potential at the output terminal of the first filter unit501. The second integral circuit402includes a second filter unit502, a third preprocessing unit530, and a fourth preprocessing unit540. The second filter unit502is configured to integrate a received signal. That is, the second filter unit502is configured to integrate the second test signal Test2. The third preprocessing unit530includes a third conducting transistor <DT3>, a third P-type precharge transistor <YP3>, and a third N-type precharge transistor <YN3>. The third conducting transistor <DT3> has a drain electrode configured to receive the second test signal Test2, a source electrode connected to an input terminal of the second filter unit502, and a gate electrode configured to receive the first switch signal PassA. The third P-type precharge transistor <YP3> has a source electrode connected to a gate electrode and configured to receive a high level and a drain electrode connected to the input terminal of the second filter unit502. The third N-type precharge transistor <YN3> has a source electrode configured to receive a low level, a drain electrode connected to the input terminal of the second filter unit502, and a gate electrode configured to receive a second integral discharge signal Clamp. Specifically, the first switch signal PassA is used for starting the third preprocessing unit530. When the first switch signal PassA turns on the third conducting transistor <DT3>, the second filter unit502receives the second test signal Test2and starts to integrate the second test signal Test2. The source electrode and the gate electrode of the third P-type precharge transistor <YP3> simultaneously receive a high level, to enable the third P-type precharge transistor <YP3> to be in a cut-off state, to prevent the high level from pulling up a potential at the input terminal of the second filter unit502. The third N-type precharge transistor <YN3> is turned on based on the second integral discharge signal Clamp, to indirectly connect the input terminal of the second filter unit502to a low level, so as to pull down the potential at the output terminal of the second filter unit502. The fourth preprocessing unit540includes a fourth conducting transistor <DT3>, a fourth P-type precharge transistor <YP4>, and a fourth N-type precharge transistor <YN4>. The fourth conducting transistor <DT3> has a drain electrode connected to an output terminal of the second filter unit502, a source electrode configured to output the second integral signal FltNdC, and a gate electrode configured to receive the second switch signal PassB. The fourth P-type precharge transistor <YP4> has a source electrode connected to a gate electrode and configured to receive a high level and a drain electrode connected to the output terminal of the second filter unit502. The fourth N-type precharge transistor <YN4> has a source electrode configured to receive a low level, a drain electrode connected to the output terminal of the second filter unit502, and a gate electrode configured to receive the second integral discharge signal Clamp. Specifically, the second switch signal PassB is configured to start the fourth preprocessing unit540. When the second switch signal PassB turns on the fourth conducting transistor <DT3>, the second integral signal FltNdC obtained through integration by the second filter unit502may be outputted to the comparison circuit403. The source electrode and the gate electrode of the fourth P-type precharge transistor <YP4> simultaneously receive a high level, to enable the fourth P-type precharge transistor <YP4> to be in a cut-off state, to prevent the high level from pulling up a potential at the output terminal of the second filter unit502. The fourth N-type precharge transistor <YN4> is turned on based on the second integral discharge signal Clamp, to indirectly connect the output terminal of the second filter unit502to a low level, so as to pull down the potential at the output terminal of the second filter unit502.

In this embodiment, the first filter unit501adopts a second-order RC filter arrangement. Correspondingly, the second filter unit502also adopts a second-order RC filter arrangement. It needs to be noted that, in other embodiments, the first filter unit and the second filter unit may both use a first-order or a higher-order RC filter arrangement. Correspondingly, in some embodiments, different orders may be set for RC filters of the first filter unit and the second filter unit.

Continuing to refer toFIG.13, in this embodiment, the test circuit400further includes a first equalizer circuit521and a second equalizer circuit522. The first equalizer circuit521has one end connected to an input terminal of the first integral circuit401and the other end connected to an input terminal of the second integral circuit402. The first equalizer circuit521is configured to make voltages at the input terminals of the first integral circuit401and the second integral circuit402equal based on a first equalization signal EqA. The second equalizer circuit522has one end connected to an output terminal of the first integral circuit401and the other end connected to an output terminal of the second integral circuit402. The second equalizer circuit522is configured to make initial voltages of the first integral signal FltNdT and the second integral signal FltNdC equal based on a second equalization signal EqB. Specifically, in this embodiment, the first equalizer circuit521includes a first P-type equalization transistor <EP1> and a first N-type equalization transistor <EN1>. A source electrode of the first P-type equalization transistor <EP1> and a drain electrode of the first N-type equalization transistor <EN1> are coupled to the input terminal of the first integral circuit401. A drain electrode of the first P-type equalization transistor <EP1> and a source electrode of the first N-type equalization transistor <EN1> are coupled to the input terminal of the second integral circuit402. A gate electrode of the first P-type equalization transistor <EP1> is connected to a gate electrode of the first N-type equalization transistor <EN1> are configured to receive the first equalization signal EqA. The second equalizer circuit522includes a second P-type equalization transistor <EP2> and a second N-type equalization transistor <EN2>. A source electrode of the second P-type equalization transistor <EP2> and a drain electrode of the second N-type equalization transistor <EN2> are coupled to the output terminal of the first integral circuit401. A drain electrode of the second P-type equalization transistor <EP2> and a source electrode of the second N-type equalization transistor <EN2> are coupled to the output terminal of the second integral circuit402. A gate electrode of the second P-type equalization transistor <EP2> is connected to a gate electrode of the second N-type equalization transistor <EN2> are configured to receive the second equalization signal EqB. The first equalizer circuit521has one end connected to an input terminal of the first filter unit501and the other end connected to an input terminal of the second filter unit502. The first equalizer circuit521is configured to make voltages at the input terminals of the first filter unit501and the second filter unit502equal based on the first equalization signal EqA. The second equalizer circuit522has one end connected to a drain electrode of the second conducting transistor <DT2> and the other end connected to a drain electrode of a fourth conducting transistor <DT4>. The second equalizer circuit522is configured to make initial voltages of the first integral signal FltNdT and the second integral signal FltNdC equal based on the second equalization signal EqB. It needs to be noted that for the first equalizer circuit521and the second equalizer circuit522, equalization transistors that need to be turned on may be disposed according to actual requirements after the test circuit is equalized. For example, if the input terminals of the first filter unit501and the second filter unit502need to be equalized by the first equalizer circuit521to reach an intermediate level, the first P-type equalization transistor <EP1> is used to equalize potentials at the input terminals of the first filter unit501and the second filter unit502. If the input terminals of the first filter unit501and the second filter unit502need to be equalized by the first equalizer circuit521to reach a low level, the first N-type equalization transistor <EN1> is used to equalize potentials at the input terminals of the first filter unit501and the second filter unit502. If the initial voltages of the first integral signal FltNdT and the second integral signal FltNdC need to be equalized by the second equalizer circuit522to reach an intermediate level, the second P-type equalization transistor <EP2> is used to equalize the initial voltages of the first integral signal FltNdT and the second integral signal FltNdC. If the initial voltages of the first integral signal FltNdT and the second integral signal FltNdC need to be equalized by the second equalizer circuit522to reach a low level, the second N-type equalization transistor <EN2> is used to equalize the initial voltages of the first integral signal FltNdT and the second integral signal FltNdC. Input terminal voltages and output terminal voltages of the first integral circuit401and the second integral circuit402are equalized before the first integral circuit401and the second integral circuit402are integrated, to ensure the accuracy of a difference between integral values of the first integral circuit401and the second integral circuit402, thereby further ensuring the accuracy of obtaining the duty cycle of a signal subsequently. In addition, in a subsequent process of outputting the first integral signal FltNdT and the second integral signal FltNdC, the first equalizer circuit521and the second equalizer circuit522are turned on, so that the power consumption of the test circuit can be further reduced.

For the comparison circuit403, referring toFIG.14, in this embodiment, the comparison circuit403includes: a first P-type input transistor <SP1>, having a gate electrode configured to receive the first integral signal FltNdT, a source electrode connected to a drain electrode of a third P-type input transistor <SP3>, and a drain electrode connected to a source electrode of a first P-type comparison transistor <BP1>; a second P-type input transistor <SP2>, having a gate electrode configured to receive the second integral signal FltNdC, a source electrode connected to a drain electrode of the third P-type input transistor <SP3>, and a drain electrode connected to a source electrode of a second P-type comparison transistor <BP2>, where a gate electrode of the third P-type input transistor <SP3> is configured to receive a comparison enable signal CkN and a source electrode configured to receive a high-level signal, that is, the third P-type input transistor <SP3> is used as a high-level protection transistor of the comparison circuit403, and the comparison enable signal CkN is used to provide a high level required for the operation of the comparison circuit403; a first N-type input transistor <SN1>, having a gate electrode configured to receive the comparison enable signal CkN, a source electrode configured to receive a low-level signal, and a drain electrode connected to a source electrode of the first P-type comparison transistor <BP1>; a second N-type input transistor <SN2>, having a gate electrode configured to receive the comparison enable signal CkN, a source electrode configured to receive a low-level signal, and a drain electrode connected to a source electrode of the second P-type comparison transistor <BP2>; a third N-type input transistor <SN3>, having a gate electrode configured to receive the comparison enable signal CkN, a source electrode configured to receive a low-level signal, and a drain electrode connected to a drain electrode of a first N-type comparison transistor <BN1>; a fourth N-type input transistor <SN4>, having a gate electrode configured to receive the comparison enable signal CkN, a source electrode configured to receive a low-level signal, and a drain electrode connected to a drain electrode of a second N-type comparison transistor <BN2>, the first P-type comparison transistor <BP1> has a drain electrode connected to the drain electrode of the first N-type comparison transistor <BN1> and a gate electrode connected to the drain electrode of the second N-type comparison transistor <BN2>, the second P-type comparison transistor <BP2> has a drain electrode connected to the drain electrode of the second N-type comparison transistor <BN2> and a gate electrode connected to the drain electrode of the first N-type comparison transistor <BN1>, the first N-type comparison transistor <BN1> has a source electrode configured to receive a low-level signal, the drain electrode configured to output a first comparison output signal OutP, and a gate electrode connected to the drain electrode of the second N-type comparison transistor <BN2>, and the second N-type comparison transistor <BN2> has a source electrode configured to receive a low-level signal, the drain electrode configured to output a second comparison output signal OutN, and a gate electrode connected to the drain electrode of the first N-type comparison transistor. One of the first comparison output signal OutP and the second comparison output signal OutN is used as an output signal of the comparison circuit403, and the other is used as an inverted signal of the output signal. The gate electrode of the first P-type input transistor <SP1> is configured to receive the first integral signal FltNdT. The gate electrode of the second P-type input transistor <SP2> is configured to receive the second integral signal FltNdC. In this case, after comparing and amplifying the first integral signal FltNdT and the second integral signal FltNdC, the comparison circuit403generates the first comparison output signal OutP and the second comparison output signal OutN. One of the first comparison output signal OutP and the second comparison output signal OutN is used for representing a comparison result between the first integral signal FltNdT and the second integral signal FltNdC, and the other is used as an inverted signal of the signal representing the comparison result. It needs to be noted that this embodiment is described in detail by using an example in which the first comparison output signal OutP is used for representing the comparison result between the first integral signal FltNdT and the second integral signal FltNdC and the second comparison output signal OutN is used as an inverted signal of the first comparison output signal OutP, which does not constitute a limitation to this embodiment. In other embodiments, the second comparison output signal may be used for representing the comparison result between the first integral signal and the second integral signal. More specifically, for the first integral signal FltNdT and the second integral signal FltNdC, if an integral value is greater than ½*power supply amplitude, the correspondingly generated first comparison output signal OutP is at a high level. If the integral value is less than or equal to ½*power supply amplitude, the correspondingly generated first comparison output signal OutP is at a low level.

In this embodiment, referring toFIG.15, the test circuit400further includes: a prestorage circuit600, connected to an output terminal of the comparison circuit403, and receiving a first clock signal Clk and a second clock signal Clklat. The prestorage circuit600is configured to prestore, based on the first clock signal Clk, a level signal outputted by the comparison circuit403or output a prestored level signal based on the second clock signal Clklat. The prestorage circuit600is adopted to ensure that the signal output timing of the test circuit400is kept consistent with the signal output timing of a memory belonging to the test circuit400, thereby ensuring that the test circuit400is applicable to memories of different types. The prestorage circuit600includes: a latch601, having one end connected to an output terminal of the comparison circuit403and the other end configured to receive the first clock signal Clk, the latch601being configured to: when the first clock signal Clk is a valid signal, generate an indication signal Result based on the outputted level of the comparison circuit; and a register602, having an input terminal D connected to an output terminal of the latch601, a clock terminal C configured to receive the second clock signal Clklat, and an enable terminal RN configured to receive an output enable signal ComEn, the register602being configured to: when the second clock signal Clklat and the output enable signal ComEn are valid signals, output the indication signal Result. Specifically, the latch601includes: a first latch NAND gate, having an input terminal configured to receive the first comparison output signal OutP and another input terminal configured to receive the first clock signal Clk; a second latch NAND gate, having an input terminal configured to receive the second comparison output signal OutN and another input terminal configured to receive the first clock signal Clk; a third latch NAND gate, having an input terminal connected to an output terminal of the first latch NAND gate and another input terminal according to an output terminal of a fourth latch NAND gate; and the fourth latch NAND gate, having an input terminal connected to an output terminal of the second latch NAND gate, another input terminal connected to an output terminal of the third latch NAND gate, and an output terminal configured to output the indication signal Result. It needs to be noted that in some embodiments, the register602may use an FF register arrangement.

In this embodiment, referring toFIG.16, the test circuit400further includes a control circuit700. The control circuit700is configured to provide, based on a control enable signal ControlEn, control signals required for duty cycle detections in the first integral circuit401, the second integral circuit402, and the comparison circuit403. Specifically, the control signals required for the duty cycle detections in the first integral circuit401, the second integral circuit402, and the comparison circuit403include: the first equalization signal EqA, the second equalization signal EqB, the integral charge signal ClampF, the first integral discharge signal ClpGnd, the second integral discharge signal Clamp, the first switch signal PassA, the second switch signal PassB, the comparison enable signal CkN, the first clock signal Clk, the second clock signal Clklat, and the output enable signal ComEn.

More specifically, referring toFIG.17, the control circuit700includes: a clock unit710, configured to generate a control clock signal ControlClk based on the control enable signal ControlEn; a timing unit720, connected to an output terminal of the clock unit710, and storing a signal count value B, the timing unit720being configured to control the signal count value B to increase by 1 when the control enable signal ControlEn and the control clock signal ControlClk are valid signals; and a logic unit730, connected to an output terminal of the timing unit720, storing a control signal corresponding to the signal count value B, and configured to provide the control signal corresponding to the signal count value B based on the signal count value B. Specifically, the clock unit710uses a ring oscillator arrangement, and the control enable signal ControlEn is used as an enable signal for a ring oscillator. An example in which the signal count value B is a 7-bit signal formed by 7 bits is used for description, which does not constitute a limitation to this embodiment. In an actual configuration, a quantity of bits of the signal count value may be configured according to an actual requirement. In some embodiments, the timing unit720is further configured to receive a test control signal ProbeMode, and when the test control signal ProbeMode is valid, add a new data bit Bmax of at least one bit to the signal count value B. The new data bit Bmax increases bits of the signal count value B to increase a change period of the control clock signal ControlClk, so as to control a memory in a test mode more accurately.

Continuing to refer toFIG.1, for the signal detection system1000, the test control signal DcmCtrl is set to at least three bits to form a plurality of signal values. The memory further includes a logic control signal circuit1006, configured to recognize the test control signal DcmCtrl and generate a turn-on signal PathEns corresponding to the test control signal DcmCtrl based on the test control signal DemCtrl, the turn-on signal PathEns is used for selecting to turn on a corresponding portion under test to form a different test path, and the different test path outputs a to-be-tested signal to the test circuit400or an external test system10.

Specifically, one value in the test control signal DemCtrl is configured to select the test circuit400to perform the duty cycle test on the reference test signal AltWck. In this case, the turn-on signal PathEns is used for making a data transmission path between the signal generator100and the test circuit400, to use the reference test signal AltWck with a known duty cycle to test whether the test function of the test circuit400is normal.

One value in the test control signal DemCtrl is configured to control the signal conversion circuit1002to receive the reference test signal AltWck and perform, based on the test circuit, the duty cycle test on the internal clock signal PWCK outputted by the signal conversion circuit1002. In this case, the turn-on signal PathEns is used for making a data transmission path between the signal generator100and the signal conversion circuit1002and a data transmission path between the signal conversion circuit1002and the test circuit400, to use the test circuit400to test whether the function of the signal conversion circuit1002is normal.

One value in the test control signal DcmCtrl is configured to select to perform, based on the test circuit400, the duty cycle test on the serial read clock Clk_R2outputted by the read clock path1004. In this case, the turn-on signal PathEns is used for making a data transmission path between the signal generator100and the signal conversion circuit1002, a data transmission path between the signal conversion circuit1002and the read clock path1004, and a data transmission path between the read clock path1004and the test circuit400, to use the test circuit400to test whether the function of the read clock path1004is normal.

One value in the test control signal DemCtrl is configured to select to perform, based on the test circuit400, the duty cycle test on the first indication signal Pup and the second indication signal Pdn outputted by the write clock path1003. In this case, the turn-on signal PathEns is used for making a data transmission path between the signal generator100and the signal conversion circuit1002, a data transmission path between the signal conversion circuit1002and the write clock path1003, and a data transmission path between the write clock path1003and the test circuit400, to repeatedly perform tests and adjustments to generate an equidistant parallel write clock Clk_W.

In some embodiments, the memory further includes: a clock driver1005, having an input terminal connected to an output terminal of the signal conversion circuit1002and an output terminal connected to the test circuit400and configured to drive the internal clock signal PWCK outputted by the signal conversion circuit1002, to avoid great signal attenuation in a transmission process of transmitting the internal clock signal PWCK to the test circuit400for testing, thereby ensuring the accuracy of a test result of the test circuit400.

In some embodiments, the memory further includes: a first output component1100, connected to the output terminal of the duty cycle correction circuit102(referring toFIG.2), and configured to output the intermediate test signal Pretest to the external test system10, the external test system10being configured to test whether the intermediate test signal Pretest satisfies the preset duty cycle. That is, the first output component1100is configured to obtain the intermediate test signal Pretest satisfying the preset duty cycle. It needs to be noted that in some embodiments, in a process of outputting the intermediate test signal Pretest to the external test system, the external test system is further configured to perform frequency division on the intermediate test signal Pretest, to make it convenient for the external test system10to detect the frequency of the intermediate test signal Pretest, thereby reducing a detection accuracy requirement of the external test system10for a signal frequency.

For the test logic of testing the write frequency divider1013by the test circuit400, details are as follows: Referring toFIG.18, the write frequency divider1013includes a four-phase clock generation circuit801, configured to receive the internal clock signal PWCK, and configured to generate the parallel write clock Clk_W based on the internal clock signal PWCK. In this embodiment, the parallel write clock Clk_W is a first clock signal WCK2TF0, a second clock signal WCK2TR0, a third clock signal WCK2TR1, and a fourth clock signal WCK2TF1with the same period. The write clock tree1023includes a signal delay circuit802, configured to receive the first clock signal WCK2TF0, the second clock signal WCK2TR0, the third clock signal WCK2TR1, the fourth clock signal WCK2TF1, and delay commands, and configured to perform a signal delay on the first clock signal WCK2TF0, the second clock signal WCK2TR0, the third clock signal WCK2TR1, and the fourth clock signal WCK2TF1separately based on the delay commands, and delays of the first clock signal WCK2TF0, the second clock signal WCK2TR0, the third clock signal WCK2TR1, and the fourth clock signal WCK2TF1are different.

In an example, a signal delay inside the four-phase clock generation circuit801is relatively large, and a K value corresponding to the four-phase clock generation circuit801is relatively large. In this case, the period of the generated first clock signal WCK2TR0may be five or more times the period of the internal clock signal PWCK. In another example, a signal delay inside the four-phase clock generation circuit801is relatively small, and a K value corresponding to the four-phase clock generation circuit801is relatively small. In this case, the period of the generated first clock signal WCK2TR0may be four or fewer times the period of the internal clock signal PWCK. Referring toFIG.19andFIG.20, it needs to be noted that double-edge sampling is usually used in a memory. That is, data sampling is performed at both a rising edge and a falling edge of a signal. That is, data is transmitted twice within one clock period. During subsequent division into four-phase clocks, if sampling is performed once based on every clock, double-edge sampling corresponds to a quantity of times of sampling of the internal clock signal PWCK of two periods. Therefore, in this embodiment, an example in which the period of the generated first clock signal WCK2TR0is twice the period of the internal clock signal PWCK (that is, K=2) is used for detailed description, which does not constitute a limitation to this embodiment. During specific use, a signal delay of the four-phase clock generation circuit801may be correspondingly set according to a frequency of a clock that needs to be generated and a frequency of the internal clock signal PWCK of the memory. It may be understood that because the first clock signal WCK2TR0, the second clock signal WCK2TF0, the third clock signal WCK2TR1, and the fourth clock signal WCK2TF1have the same period, in this case, the periods of the second clock signal WCK2TF0, the third clock signal WCK2TR1, and the fourth clock signal WCK2TF1are also twice the period of the internal clock signal PWCK.

The signal delay circuit802generates a first delay clock signal WCK2TWRTR0after delaying the first clock signal WCK2TR0, generates a second delay clock signal WCK2TWRTF0after delaying the second clock signal WCK2TF0, generates a third delay clock signal WCK2TWRTR1after delaying the third clock signal WCK2TR1, and generates a fourth delay clock signal WCK2TWRTF1after delaying the fourth clock signal WCK2TF1. Referring toFIG.19andFIG.20, a delay of the second delay clock signal WCK2TWRTF0relative to the first delay clock signal WCK2TWRTR0is Ts1, a delay of the third delay clock signal WCK2TWRTR1relative to the second delay clock signal WCK2TWRTF0is Ts2, a delay of the fourth delay clock signal WCK2TWRTF1relative to the third delay clock signal WCK2TWRTR1is Ts3, and a delay of the first delay clock signal WCK2TWRTR0relative to the fourth delay clock signal WCK2TWRTF1is Ts4.

In this embodiment, the delay commands include a first delay command cmR0, a second delay command cmF0, a third delay command cmR1, and a fourth delay command cmF1. The signal delay circuit802includes a first delay subcircuit901, a second delay subcircuit902, a third delay subcircuit903, and a fourth delay subcircuit904.

The first delay subcircuit901is configured to perform a signal delay on the first clock signal WCK2TF0according to the first delay command cmR0, to generate the first delay clock signal WCK2TWRTR0. The second delay subcircuit902is configured to perform a signal delay on the second clock signal WCK2TF0according to the second delay command cmF0, to generate the second delay clock signal WCK2TWRTF0. The third delay subcircuit903is configured to perform a signal delay on the third clock signal WCK2TR1according to the third delay command cmR1, to generate the third delay clock signal WCK2TWRTR1. The fourth delay subcircuit904is configured to perform a signal delay on the fourth clock signal WCK2TF1according to the fourth delay command cmF1, to generate the fourth delay clock signal WCK2TWRTF1.

In an example, the first delay subcircuit901includes: a first I delay inverter811, having an input terminal configured to receive the first clock signal WCK2TF0; a first II delay inverter812, having an input terminal connected to the first I delay inverter811; a first III delay inverter813, having an input terminal connected to the first II delay inverter812; a first IV delay inverter814, having an input terminal connected to the first III delay inverter813and an output terminal configured to output a delayed first clock signal, that is, the first delay clock signal WCK2TWRTR0; a first charge-discharge circuit851, having one end connected to an output terminal of the first I delay inverter811and the other end coupled to a low-level power supply node, the low-level power supply node being configured to receive a low level; and a fifth charge-discharge circuit855, having one end connected to an output terminal of the first II delay inverter812and the other end coupled to the low-level power supply node, where the charge-discharge capability of the first charge-discharge circuit851and the charge-discharge capability of the fifth charge-discharge circuit855are adjusted according to the first delay command cmR0. It needs to be noted that in other embodiments, the other end of the first charge-discharge circuit851and the other end of the fifth charge-discharge circuit855may be coupled to a high-level power supply node, the high-level power supply node being configured to receive a high level.

In an example, the second delay subcircuit902includes: a second I delay inverter821, having an input terminal configured to receive the second clock signal WCK2TF0; a second II delay inverter822, having an input terminal connected to the second I delay inverter821; a second III delay inverter823, having an input terminal connected to the second II delay inverter822; a second IV delay inverter824, having an input terminal connected to the second III delay inverter823and an output terminal configured to output a delayed second clock signal, that is, the second delay clock signal WCK2TWRTF0; a second charge-discharge circuit852, having one end connected to an output terminal of the second I delay inverter821and the other end coupled to a low-level power supply node, the low-level power supply node being configured to receive a low level; and a sixth charge-discharge circuit856, having one end connected to an output terminal of the second II delay inverter822and the other end coupled to the low-level power supply node, where the charge-discharge capability of the second charge-discharge circuit852and the charge-discharge capability of the sixth charge-discharge circuit856are adjusted according to the second delay command cmF0. It needs to be noted that in other embodiments, the other end of the second charge-discharge circuit852and the other end of the sixth charge-discharge circuit856may be coupled to a high-level power supply node, the high-level power supply node being configured to receive a high level.

In an example, the third delay subcircuit903includes: a third I delay inverter831, having an input terminal configured to receive the third clock signal WCK2TR1; a third II delay inverter832, having an input terminal connected to the third I delay inverter831; a third III delay inverter833, having an input terminal connected to the third II delay inverter832; a third IV delay inverter834, having an input terminal connected to the third III delay inverter833and an output terminal configured to output a delayed third clock signal, that is, the third delay clock signal WCK2TWRTR1; a third charge-discharge circuit853, having one end connected to an output terminal of the third I delay inverter831and the other end coupled to a low-level power supply node, the low-level power supply node being configured to receive a low level; and a seventh charge-discharge circuit857, having one end connected to an output terminal of the third II delay inverter832and the other end coupled to the low-level power supply node, where the charge-discharge capability of the third charge-discharge circuit853and the charge-discharge capability of the seventh charge-discharge circuit857are adjusted according to the third delay command cmR1. It needs to be noted that in other embodiments, the other end of the third charge-discharge circuit853and the other end of the seventh charge-discharge circuit857may be coupled to a high-level power supply node, the high-level power supply node being configured to receive a high level.

In an example, the fourth delay subcircuit904includes: a fourth I delay inverter841, having an input terminal configured to receive the fourth clock signal WCK2TF1; a fourth II delay inverter842, having an input terminal connected to the fourth I delay inverter841; a fourth III delay inverter843, having an input terminal connected to the fourth II delay inverter842; a fourth IV delay inverter844, having an input terminal connected to the fourth III delay inverter843and an output terminal configured to output a delayed fourth clock signal, that is, the fourth delay clock signal WCK2TWRTF1; a fourth charge-discharge circuit854, having one end connected to an output terminal of the fourth I delay inverter841and the other end coupled to a low-level power supply node, the low-level power supply node being configured to receive a low level; and an eighth charge-discharge circuit858, having one end connected to an output terminal of the fourth II delay inverter842and the other end coupled to the low-level power supply node, where the charge-discharge capability of the fourth charge-discharge circuit854and the charge-discharge capability of the eighth charge-discharge circuit858are adjusted according to the fourth delay command cmF1. It needs to be noted that in other embodiments, the other end of the fourth charge-discharge circuit854and the other end of the eighth charge-discharge circuit858may be coupled to a high-level power supply node, the high-level power supply node being configured to receive a high level.

Specifically, for the first charge-discharge circuit851, the second charge-discharge circuit852, the third charge-discharge circuit853, and the fourth charge-discharge circuit854, if more charges can be stored, the discharge speed is higher, and a delay of the rising edge of the signal is longer. For the fifth charge-discharge circuit855, the sixth charge-discharge circuit856, the seventh charge-discharge circuit857, and the eighth charge-discharge circuit858, if more charges can be stored, the charge speed is higher, and a delay of the falling edge of the signal is longer. The charge-discharge capability of the first charge-discharge circuit851, the second charge-discharge circuit852, the third charge-discharge circuit853, the fourth charge-discharge circuit854, the fifth charge-discharge circuit855, the sixth charge-discharge circuit856, the seventh charge-discharge circuit857, and the eighth charge-discharge circuit858is adjusted, so that the first clock signal WCK2TF0, the second clock signal WCK2TR0, the third clock signal WCK2TR1, and the fourth clock signal WCK2TF1have the same period are delayed to different degrees.

Moreover, the first charge-discharge circuit851and the fifth charge-discharge circuit855are controlled based on the same delay command, that is, the rising edge and the falling edge of the first clock signal WCK2TF0are delayed to the same degree, to ensure that the duty cycle of the first clock signal WCK2TF0is not changed. The second charge-discharge circuit852and the sixth charge-discharge circuit856are controlled based on the same delay command, that is, the rising edge and the falling edge of the second clock signal WCK2TR0are delayed to the same degree, to ensure that the duty cycle of the second clock signal WCK2TR0is not changed. The third charge-discharge circuit853and the seventh charge-discharge circuit857are controlled based on the same delay command, that is, the rising edge and the falling edge of the third clock signal WCK2TR1are delayed to the same degree, to ensure that the duty cycle of the third clock signal WCK2TR1is not changed. The fourth charge-discharge circuit854and the eighth charge-discharge circuit858are controlled based on the same delay command, that is, the rising edge and the falling edge of the fourth clock signal WCK2TF1are delayed to the same degree, to ensure that the duty cycle of the fourth clock signal WCK2TF1is not changed.

In this embodiment, the first charge-discharge circuit851, the second charge-discharge circuit852, the third charge-discharge circuit853, the fourth charge-discharge circuit854, the fifth charge-discharge circuit855, the sixth charge-discharge circuit856, the seventh charge-discharge circuit857, and the eighth charge-discharge circuit858are implemented by capacitors. The charge-discharge capability of a capacitor depends on a maximum storage charge amount C and a discharge current I of the capacitor. Specifically, the discharge current I is controlled by one bias transistor. Delay commands cm controls the discharge current I to control the delay performance of the corresponding first charge-discharge circuit851, second charge-discharge circuit852, third charge-discharge circuit853, fourth charge-discharge circuit854, fifth charge-discharge circuit855, sixth charge-discharge circuit856, seventh charge-discharge circuit857, and eighth charge-discharge circuit858.

It needs to be noted that in some embodiments, the low levels received by the low-level power supply nodes coupled to the first delay subcircuit901, the second delay subcircuit902, the third delay subcircuit903, and the fourth delay subcircuit904are adjustable, thereby implementing the overall adjustment of the charge-discharge capability of the first delay subcircuit901, the second delay subcircuit902, the third delay subcircuit903, and the fourth delay subcircuit904.

In an ideal case, the signal delay circuit802may generate an equidistant (Ts1=Ts2=Ts3=Ts4) four-phase clock signals. However, due to reasons such as a deviation in an actual device, corresponding delays of the four-phase clock signals generated by the signal delay circuit802are not equal, that is, it cannot be ensured that Ts1=Ts2=Ts3=Ts4.

The signal loading circuit805generate the first indication signal Pup and the second indication signal Pdn based on the first delay clock signal WCK2TWRTR0, the second delay clock signal WCK2TWRTF0, the third delay clock signal WCK2TWRTR1, and the fourth delay clock signal WCK2TWRTF1. Specifically, referring toFIG.18, the signal loading circuit805includes: a data generation circuit803, configured to generate four-bit first loading data Data1and four-bit second loading data Data2; and a data loading circuit804, configured to sample the first loading data Data1according to the delayed first clock signal, second clock signal, third clock signal, and fourth clock signal to generate the first indication signal Pup, where when first loading data Data1corresponding to a sampling edge of each of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal is at a high level, the generated first indication signal Pup is at a high level; and when the first loading data Data1corresponding to the sampling edge of each of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal is at a low level, the generated first indication signal Pup is at a high level. The data loading circuit804is further configured to sample the second loading data Data2according to the delayed first clock signal, second clock signal, third clock signal, and fourth clock signal to generate the second indication signal Pdn, where when second loading data Data2corresponding to a sampling edge of each of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal is at a high level, the generated second indication signal Pdn is at a high level. For the data generation circuit803, the generated first loading data Data1and four-bit second loading data Data2have a quantity of bits equal to that of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal driving the data loading circuit804. In this embodiment, the data loading circuit804may be driven by four clock signals. Therefore, the first loading data Data1and the second loading data Data2both have four bits. In some embodiments, the data generation circuit803is controlled based on the test control signal to be turned on. It is controlled that the data generation circuit is turned on only during use, thereby reducing the power consumption of the clock generation circuit.

The test circuit400is connected to the signal loading circuit805, and is configured to perform the duty cycle test based on the first indication signal Pup and the second indication signal Pdn. Specifically, an output signal of the test circuit400is used for representing a value relationship between the first indication signal Pup and the second indication signal Pdn. If the output signal of the test circuit is at a high level, the first indication signal Pup is greater than the second indication signal Pdn. If the output signal of the test circuit is at a low level, the second indication signal Pdn is not less than the first indication signal Pup.

Specifically, the first indication signal Pup is generated based on the first delay clock signal WCK2TWRTR0, the second delay clock signal WCK2TWRTF0, and the third delay clock signal WCK2TWRTR1obtained through delaying. The second indication signal Pdn is generated based on the third delay clock signal WCK2TWRTR1, the fourth delay clock signal WCK2TWRTF1, and the first delay clock signal WCK2TWRTR0obtained through delaying. As can be known fromFIG.19andFIG.20, in this case, the duty cycle of the first indication signal Pup is (Ts1+Ts2)/(Ts1+Ts2+Ts3+Ts4), and the duty cycle of the second indication signal Pdn is (Ts3+Ts4)/(Ts1+Ts2+Ts3+Ts4). If the output signal of the test circuit400is at a high level, it is proved that the duty cycle of the first indication signal Pup is greater than the duty cycle of the second indication signal Pdn, that is, (Ts1+Ts2)> (Ts3+Ts4). In this case, the delay of the first clock signal may be increased and at the same time delays of the second clock signal and the third clock signal are reduced, that is, Ts1+Ts2is reduced and Ts3+Ts4is increased, to keep (Ts1+Ts2)=(Ts3+Ts4) and a sum of Ts1+Ts2+Ts3+Ts4unchanged, so that the overall period of the four-phase clock signals is not changed. If the output signal of the test circuit400is at a low level, it is proved that the duty cycle of the first indication signal Pup is less than the duty cycle of the second indication signal Pdn, that is, (Ts1+Ts2)< (Ts3+Ts4). In this case, the delay of the first clock signal may be reduced and at the same time delays of the second clock signal and the third clock signal are increased, that is, Ts1+Ts2is increased and Ts3+Ts4is reduced, to keep (Ts1+Ts2)=(Ts3+Ts4) and a sum of Ts1+Ts2+Ts3+Ts4unchanged, so that the overall period of the four-phase clock signals is not changed. It needs to be noted that the foregoing example does not reflect sampling of a delay clock signal in which the first indication signal Pup and the second indication signal Pdn are not related to a duty cycle result. During actual application, the first indication signal Pup and the second indication signal Pdn are both adopted based on the first delay clock signal WCK2TWRTR0, the second delay clock signal WCK2TWRTF0, the third delay clock signal WCK2TWRTR1, and the fourth delay clock signal WCK2TWRTF1.

A third indication signal Pup is generated based on the delayed the first delay clock signal WCK2TWRTR0and the second delay clock signal WCK2TWRTF0, and a fourth indication signal Pdn is generated based on the delayed second delay clock signal WCK2TWRTF0and the third delay clock signal WCK2TWRTR1. With reference toFIG.19andFIG.20, in this case, the duty cycle of the third indication signal Pup is Ts1/(Ts1+Ts2), and the duty cycle of the fourth indication signal Pdn is Ts2/(Ts1+Ts2). If the output signal of the test circuit400is at a high level, it is proved that the duty cycle of the third indication signal Pup is greater than the duty cycle of the fourth indication signal Pdn, that is, Ts1>Ts2. In this case, the delay of the first clock signal may be increased and the delay of the second clock signal may be reduced, that is, Ts1is reduced and Ts2is increased, to keep Ts1=Ts2and a total delay of the first clock signal and the second clock signal unchanged, that is, a sum of Ts1+Ts2unchanged, to ensure that (Ts1+Ts2)=(Ts3+Ts4). If the output signal of the test circuit400is at a low level, it is proved that the duty cycle of the third indication signal Pup is less than the duty cycle of the fourth indication signal Pdn, that is, Ts1<Ts2. In this case, the delay of the first clock signal may be reduced and the delay of the second clock signal may be increased, that is, Ts1is increased and Ts2is reduced, to keep Ts1=Ts2and a total delay of the first clock signal and the second clock signal unchanged, that is, a sum of Ts1+Ts2unchanged, to ensure that (Ts1+Ts2)=(Ts3+Ts4). It needs to be noted that the foregoing example does not reflect sampling of a delay clock signal in which the third indication signal Pup and the fourth indication signal Pdn are not related to a duty cycle result. During actual application, the first indication signal Pup and the third indication signal Pdn are both adopted based on the first delay clock signal WCK2TWRTR0, the second delay clock signal WCK2TWRTF0, the third delay clock signal WCK2TWRTR1, and the fourth delay clock signal WCK2TWRTF1.

A fifth indication signal Pup is generated based on the delayed the third delay clock signal WCK2TWRTR1and the fourth delay clock signal WCK2TWRTF1, and a sixth indication signal Pdn is generated based on the delayed fourth delay clock signal WCK2TWRTF1and the first delay clock signal WCK2TWRTR0. With reference toFIG.19andFIG.20, in this case, the duty cycle of the fifth indication signal Pup is Ts3/(Ts3+Ts4), and the duty cycle of the sixth indication signal Pdn is Ts4/(Ts3+Ts4). If the output signal of the test circuit400is at a high level, it is proved that the duty cycle of the fifth indication signal Pup is greater than the duty cycle of the sixth indication signal Pdn, that is, Ts3>Ts4. In this case, the delay of the third clock signal may be increased and the delay of the fourth clock signal may be reduced, that is, Ts3is reduced and Ts4is increased, to keep Ts3=Ts4and a total delay of the third clock signal and the fourth clock signal unchanged, that is, a sum of Ts3+Ts4unchanged, to ensure that (Ts1+Ts2)=(Ts3+Ts4). If the output signal of the test circuit400is at a low level, it is proved that the duty cycle of the fifth indication signal Pup is less than the duty cycle of the sixth indication signal Pdn, that is, Ts3<Ts4. In this case, the delay of the third clock signal may be increased and the delay of the fourth clock signal may be reduced, that is, Ts3is increased and Ts4is reduced, to keep Ts3=Ts4and a total delay of the third clock signal and the fourth clock signal unchanged, that is, a sum of Ts3+Ts4unchanged, to ensure that (Ts1+Ts2)=(Ts3+Ts4). It needs to be noted that the foregoing example does not reflect sampling of a delay clock signal in which the fifth indication signal Pup and the sixth indication signal Pdn are not related to a duty cycle result. During actual application, the fifth indication signal Pup and the sixth indication signal Pdn are both adopted based on the first delay clock signal WCK2TWRTR0, the second delay clock signal WCK2TWRTF0, the third delay clock signal WCK2TWRTR1, and the fourth delay clock signal WCK2TWRTF1.

It needs to be noted that the foregoing example describes a case in which the delays of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are all adjustable. During specific implementation, because a rising edge of the first clock signal WCK2TR0needs to be aligned with a rising edge of the internal clock signal PWCK, that is, the delay of the first clock signal WCK2TR0cannot be adjusted. In this case, a change in the delay of the first clock signal WCK2TR0is ignored, and the foregoing example is still applicable.

Continuing to refer toFIG.1, in some embodiments, the memory further includes a second output component1200, connected to an output terminal of the write clock tree1023, and configured to output the parallel write clock Clk_W to the external test system10, the external test system10being configured to test whether the parallel write clock Clk_W is an equidistant clock. That is, after the write clock tree1023, the signal loading circuit805, and the test circuit400are tested and adjusted, it is determined whether the actually obtained parallel write clock Clk_W is an equidistant clock.

In this case, one value in the test control signal is configured to control the memory to output the parallel write clock outputted by the write clock path1003to the external test system10to perform the duty cycle detection. In this case, the turn-on signal PathEns is used for making a data transmission path between the signal generator100and the signal conversion circuit1002, a data transmission path between the signal conversion circuit1002and the write clock path1003, and a data transmission path between the write clock path1003and the external test system, to determine whether the parallel write clock Clk_W is an equidistant clock.

In some embodiments, the signal conversion circuit1002is further configured to receive an external clock signal WCK with the preset duty cycle and generate the internal clock signal PWCK according to the external clock signal WCK. The external clock signal WCK is a clock signal that needs to be received when the memory operates normally.

Correspondingly, referring toFIG.1, the memory further includes: a selection circuit1001, having a first input terminal, a second input terminal, and an output terminal, the first input terminal being configured to receive the reference test signal AltWck, the second input terminal being configured to receive the external clock signal WCK, the output terminal being connected to an input terminal of the signal conversion circuit1002, the control terminal being configured to receive the test control signal DcmCtrl and connect the first input terminal and the output terminal or connect the second input terminal and the output terminal based on the test control signal DemCtrl.

In an example, referring toFIG.21, a first input MOS transistor has a source electrode connected to an output terminal of the amplitude adjustment circuit103and a drain electrode configured to output the reference test signal AltWck. A second input MOS transistor has a source electrode connected to the drain electrode of the first input MOS transistor and a drain electrode connected to the source electrode of the first input MOS transistor. A third input MOS transistor has a source electrode configured to receive the external clock signal WCK and a drain electrode connected to the drain electrode of the first input MOS transistor and configured to output the external clock signal WCK. A gate electrode of the first input MOS transistor, a gate electrode of the second input MOS transistor, and a gate electrode of the third input MOS transistor are configured to receive the test control signal DemCtrl, and signals received by the gate electrode of the first input MOS transistor and the gate electrode of the second input MOS transistor are inverted signals. That is, the gate electrode of one of the first input MOS transistor and the second input MOS transistor is configured to receive the test control signal DcmCtrl, and the gate electrode of the other is configured to receive inverted test control signal DcmCtrl−. In some embodiments, only one of the first input MOS transistor and the third input MOS transistor receives a clock signal. In this case, the two can be turned on simultaneously. In some other embodiments, the first input MOS transistor and the third input MOS transistor are alternately turned on.

Correspondingly, continuing to refer toFIG.1, for the test control signal DcmCtrl, details are as follows:

One value in the test control signal DcmCtrl is configured to control the memory to output the generated intermediate test signal Pretest to the external test system to perform a duty cycle detection. In this case, the turn-on signal PathEns is used for making a data transmission path between the signal generator100and the external test system10, to obtain the reference test signal AltWck with a duty cycle satisfying the preset duty cycle.

One value in the test control signal DcmCtrl is configured to select, based on the test circuit, to perform the duty cycle test on the reference test signal AltWck. In this case, the turn-on signal PathEns is used for making a data transmission path between the signal generator100and the test circuit400, to use the reference test signal AltWck with a known duty cycle to test whether the test function of the test circuit400is normal.

One value in the test control signal DcmCtrl is configured to select to perform, based on the test circuit400, the duty cycle test on the internal clock signal PWCK outputted by the signal conversion circuit1002based on the reference test signal AltWck. In this case, the turn-on signal PathEns is used for making a data transmission path between the signal generator100and the selection circuit1001, a data transmission path between selection circuit1001and the signal conversion circuit1002, and a data transmission path between the signal conversion circuit1002and the test circuit400, to use the test circuit400to test whether the function of the signal conversion circuit1002when operating based on the reference test signal AltWck is normal.

One value in the test control signal DemCtrl is configured to select to perform, based on the test circuit400, the duty cycle test on the internal clock signal PWCK outputted by the signal conversion circuit1002based on the internal clock signal PWCK. In this case, the turn-on signal PathEns is used for making a data transmission path between the selection circuit1001and a data pad (configured to receive the external clock signal WCK), a data transmission path between selection circuit1001and the signal conversion circuit1002, and a data transmission path between the signal conversion circuit1002and the test circuit400, to use the test circuit400to test whether the function of the signal conversion circuit1002when operating based on the external clock signal WCK is normal.

One value in the test control signal DcmCtrl is configured to select to perform, based on the test circuit400, the duty cycle test on the serial read clock Clk_R2outputted by the read clock path1004based on the reference test signal AltWck. In this case, the turn-on signal PathEns is used for making a data transmission path between the signal generator100and the selection circuit1001, a data transmission path between the selection circuit1001and the signal conversion circuit1002, a data transmission path between the signal conversion circuit1002and the read clock path1004, and a data transmission path between the read clock path1004and the test circuit400, to use the test circuit400to test whether the function of the read clock path1004when operating based on the reference test signal AltWck is normal.

One value in the test control signal DemCtrl is configured to select to perform, based on the test circuit400, the duty cycle test on the serial read clock Clk_R2outputted by the read clock path1004based on the external clock signal WCK. In this case, the turn-on signal PathEns is used for making a data transmission path between the selection circuit1001and a data pad (configured to receive the external clock signal WCK), a data transmission path between the selection circuit1001and the signal conversion circuit1002, a data transmission path between the signal conversion circuit1002and the read clock path1004, and a data transmission path between the read clock path1004and the test circuit400, to use the test circuit400to test whether the function of the read clock path1004when operating based on the external clock signal WCK is normal.

One value in the test control signal DemCtrl is configured to select to perform, based on the test circuit400, the duty cycle test on the first indication signal Pup and the second indication signal Pdn outputted by the write clock path1003based on the reference test signal AltWck. In this case, the turn-on signal PathEns is used for making a data transmission path between the signal generator100and the selection circuit1001, a data transmission path between the selection circuit1001and the signal conversion circuit1002, a data transmission path between the signal conversion circuit1002and the write clock path1003, and a data transmission path between the write clock path1003and the test circuit400, to repeatedly perform tests and adjustments to generate an equidistant parallel write clock Clk_W based on the reference test signal AltWck.

One value in the test control signal DemCtrl is configured to select to perform, based on the test circuit400, the duty cycle test on the first indication signal Pup and the second indication signal Pdn outputted by the write clock path1003based on the external clock signal WCK. In this case, the turn-on signal PathEns is used for making a data transmission path between the selection circuit1001and a data pad (configured to receive the external clock signal WCK), a data transmission path between the selection circuit1001and the signal conversion circuit1002, a data transmission path between the signal conversion circuit1002and the write clock path1003, and a data transmission path between the write clock path1003and the test circuit400, to repeatedly perform tests and adjustments to generate an equidistant parallel write clock Clk_W based on the external clock signal WCK.

One value in the test control signal DcmCtrl is configured to control the memory to output the parallel write clock Clk_W generated based on the reference test signal AltWck to the external test system10to perform the duty cycle detection. In this case, the turn-on signal PathEns is used for making a data transmission path between the signal generator100and the selection circuit1001, a data transmission path between the selection circuit1001and the signal conversion circuit1002, a data transmission path between the signal conversion circuit1002and the write clock path1003, and a data transmission path between the write clock path1003and the external test system, to determine whether the parallel write clock Clk_W generated based on the reference test signal AltWck is an equidistant clock.

One value in the test control signal DemCtrl is configured to control the memory to output the parallel write clock Clk_W generated based on the external clock signal WCK to the external test system10to perform the duty cycle detection. In this case, the turn-on signal PathEns is used for making a data transmission path between the selection circuit1001and a data pad (configured to receive the external clock signal WCK), a data transmission path between the selection circuit1001and the signal conversion circuit1002, a data transmission path between the signal conversion circuit1002and the write clock path1003, and a data transmission path between the write clock path1003and the external test system, to determine whether the parallel write clock Clk_W generated based on the external clock signal WCK is an equidistant clock.

It needs to be noted that “the driving capability” in the embodiments of the disclosure is a driving capability of a source-drain current of a transistor when a gate electrode of the transistor is turned on to the same degree.

In this embodiment, the duty cycle test is performed on the reference test signal AltWck based on the test circuit400. A duty cycle of the reference test signal AltWck is known and is used for determining whether a duty cycle test function of the test circuit400is normal. If the duty cycle test function of the test circuit400is normal, different portions under test are selected based on a test control signal DemCtrl, and duty cycles of an output signals of the different portions under test are sequentially tested by using the test circuit400, to test whether the duty cycle of the output signal of each of the different portions under test is normal, thereby completing a function test for the different portions under test.

It needs to be noted that the features disclosed in the signal detection system provided in the foregoing embodiments may be arbitrarily combined with each other without causing any conflict to obtain new embodiments of the signal detection system.

Another embodiment of the disclosure provides a memory detection method, performing a duty cycle test on output signals of test paths in a memory based on the signal detection system provided in the foregoing embodiments. Different test paths are selected to test whether duty cycles of a high-speed clock signal in different transmission paths meets requirements, to ensure the stability of data processing in a memory.

A person of ordinary skill in the art may understand that the foregoing embodiments are specific embodiments for implementing the disclosure, and in actual applications, various changes can be made thereto in forms and details without departing from the spirit and scope of the disclosure.