Patent ID: 12260837

DETAILED DESCRIPTION

The following describes embodiments of the present disclosure with reference to the drawings. What is disclosed herein is merely an example, and the present disclosure naturally encompasses appropriate modifications easily conceivable by those skilled in the art while maintaining the gist of the invention. To further clarify the description, the drawings schematically illustrate, for example, widths, thicknesses, and shapes of various parts as compared with actual aspects thereof, in some cases. However, they are merely examples, and interpretation of the present disclosure is not limited thereto. The same element as that illustrated in a drawing that has already been discussed is denoted by the same reference numeral through the description and the drawings, and detailed description thereof will not be repeated in some cases where appropriate.

In this disclosure, when an element is described as being “on” another element, the element can be directly on the other element, or there can be one or more elements between the element and the other element.

FIG.1is a plan view illustrating an exemplary display device according to a present embodiment.FIG.1does not illustrate a light source device L illustrated inFIG.2.FIG.2is a sectional view illustrating an exemplary section of the display device ofFIG.1.FIG.3is a partial sectional view obtained by enlarging a portion ofFIG.2.FIG.4is a schematic circuit diagram illustrating a main configuration of the display device of the present embodiment.

As illustrated inFIG.1, a display device100includes a display panel P, a circuit substrate91, and a flexible substrate92that couples the display panel P to the circuit substrate91. A first direction X denotes one direction in a plane of the display panel P. A second direction Y denotes a direction orthogonal to the first direction X. A third direction Z denotes a direction orthogonal to the X-Y plane.

The display panel P has a display region7, and a first peripheral region PA1, a second peripheral region PA2, a third peripheral region PA3, and a fourth peripheral region PA4provided around the display region7. The first peripheral region PA1and the second peripheral region PA2interpose the display region7therebetween in the first direction X. The third peripheral region PA3and the fourth peripheral region PA4interpose the display region7therebetween in the second direction Y.

A driver integrated circuit (IC)5, a first scan circuit9A, and a second scan circuit9B are arranged in the third peripheral region PA3. The driver IC5includes a signal output circuit8and a common electrode drive circuit10.

In the first peripheral region PA1, a plurality of first lead lines DW1are provided outside first coupling ends CE1of respective scan lines GL in the first direction X. The first scan circuit9A is electrically coupled to the first coupling ends CE1through the respective first lead lines DW1. In the second peripheral region PA2, a plurality of second lead lines DW2are provided outside second coupling ends CE2of the respective scan lines GL in the first direction X. The second scan circuit9B is electrically coupled to the second coupling ends CE2through the respective second lead lines DW2. The first lead lines DW1and the second lead lines DW2are arranged line-symmetrically to each other with respect to the center line in the second direction Y passing through the center in the first direction X of the display region7.

In the display region7, a plurality of scan lines GL1, GL2, . . . , GLN (where N is an integer equal to or larger than 1) extending in the first direction X are arranged with gaps interposed therebetween in the second direction Y. Hereafter, the scan lines GL1, GL2, . . . , GLN may be collectively referred to as scan lines GLn (where n is an integer from 1 to N). In the display region7, a plurality of signal lines SL1, SL2, . . . , SLM−1, SLM (where M is an integer equal to or larger than 1) extending in the second direction are arranged with gaps interposed therebetween in the first direction X. Hereafter, the signal lines SL1, SL2, . . . , SLM−1, SLM may be collectively referred to as signal lines SLm (where m is an integer from 1 to M).

A plurality of pixels Pix are arranged in a matrix in a row-column configuration in the display region7. In the present disclosure, a row refers to a pixel row including M pixels Pix arranged in one direction. A column refers to a pixel column including N pixels Pix arranged in a direction orthogonal to the direction in which the rows extend. The values of M and N are determined according to a display resolution in the vertical direction and a display resolution in the horizontal direction. The scan lines GLn are provided corresponding to the rows, and the signal lines SLm are provided corresponding to the columns.

A timing controller13and a power supply circuit14are arranged on the circuit substrate91.

The display panel P includes a first substrate30, a second substrate20, a liquid crystal layer3, and the light source device L. The second substrate20faces a surface of the first substrate30in a direction orthogonal thereto (in the third direction Z illustrated inFIG.1). As the liquid crystal layer3, polymer-dispersed liquid crystals LC are sealed between the first substrate30and the second substrate20.

The display panel P of the present embodiment is a display panel where, for example, when a display surface is denoted as a first surface351of the first substrate30, a back surface is denoted as a second surface211of the second substrate20. A background on the back surface can be seen through when viewed from the display surface side, and a background on the display surface can be seen through when viewed from the back surface side. The display surface may be the second surface211and the back surface may be the first surface351.

As illustrated inFIG.2, the light source device L is a sidelight located on a side surface side orthogonal to the first surface351of the first substrate30and second surface211of the second substrate20. The plane of light incidence is not limited to the side surface of the first substrate30, but the light source device L may emit light toward the side surface of the second substrate20, or toward the side surface of the first substrate30and the side surface of the second substrate20.

As illustrated inFIG.3, the first substrate30includes a light-transmitting glass substrate35, pixel electrodes2formed on the second substrate20side of the glass substrate35, and a first orientation film55stacked on the second substrate20side of each pixel electrode2so as to cover the pixel electrodes2. The pixel electrode2is individually provided for each of the pixels Pix. The second substrate20includes a light-transmitting glass substrate21, a common electrode6formed on the first substrate30side of the glass substrate21, and a second orientation film56stacked on the first substrate30side of the common electrode6so as to cover the common electrode6. The common electrode6has a plate-like or film-like shape shared among the pixels Pix. In the first substrate30, although not illustrated inFIG.3, each switching element1coupled to a corresponding one of the pixel electrodes2is formed between the pixel electrode2and the glass substrate35. The first substrate30and the second substrate20may further include protective members formed of, for example, glass, on the display surface side (first surface351side and second surface211side) of the glass substrates35and21. The protective members may be made of a resin, as long as transmitting light.

The liquid crystal layer3of the present embodiment is the polymer-dispersed liquid crystals. Specifically, the polymer-dispersed liquid crystals contain a bulk51and fine particles52. A solution containing the liquid crystals and a monomer is filled between the first substrate30and the second substrate20. In a state where the monomer and the liquid crystals are oriented by the first and the second orientation films55and56, the monomer is polymerized by ultraviolet rays or heat to form the bulk51. This process forms the liquid crystal layer3containing the polymer-dispersed liquid crystals in a reverse mode in which the liquid crystals are dispersed in gaps of a polymer network formed in a mesh shape.

Thus, the polymer-dispersed liquid crystals contain the bulk51formed of the polymer and the fine particles52dispersed in the bulk51. The fine particles52are formed of the liquid crystals. Both the bulk51and the fine particles52are optically anisotropic.

The orientation of the liquid crystals contained in the fine particles52is controlled by a voltage difference between the pixel electrode2and the common electrode6. The orientation of the liquid crystals is changed by the voltage applied to the pixel electrode2. The degree of scattering of light passing through the pixels Pix changes with change in the orientation of the liquid crystals.

Ordinary-ray refractive indices of the bulk51and the fine particles52are equal to each other. When no voltage is applied between the pixel electrode2and the common electrode6, the difference of refractive index between the bulk51and the fine particles52is zero in all directions. The liquid crystal layer3is placed in a non-scattering state of not scattering the light of the light source device L. Light in the display panel P propagates in a direction away from the light source device L (light emitter31) while being reflected by the first surface351of the first substrate30and the second surface211of the second substrate20. When the liquid crystal layer3is in the non-scattering state of not scattering the light, a background on the second surface211side of the second substrate20is visible from the first surface351of the first substrate30, and a background on the first surface351side of the first substrate30is visible from the second surface211of the second substrate20.

In the gap between the pixel electrode2and the common electrode6having a voltage applied thereto, an optical axis of the fine particles52is inclined by an electric field generated between the pixel electrode2and the common electrode6. Since an optical axis of the bulk51is not changed by the electric field, the direction of the optical axis of the bulk51differs from that of the optical axis of the fine particles52. The light is scattered in the pixel Pix including the pixel electrode2having a voltage applied thereto. A viewer views a part of the light that has been scattered as described above and emitted outward from the first surface351of the first substrate30or the second surface211of the second substrate20.

With the pixel Pix including the pixel electrode2having no voltage applied thereto, the background on the second surface211side of the second substrate20is visible from the first surface351of the first substrate30, and the background on the first surface351side of the first substrate30is visible from the second surface211of the second substrate20. In the display device100of the present embodiment, a voltage is applied to the pixel electrode2of the pixel Pix to display an image, and the image is visible together with the background. Thus, the image is displayed in the display region7when the polymer-dispersed liquid crystals are in the scattering state.

The image displayed by the light that has been scattered in the pixel Pix including the pixel electrode2having a voltage applied thereto and has been emitted outward, is displayed so as to be superimposed on the background. In other words, the display device100of the present embodiment displays the image such that the image is superimposed on the background.

As illustrated inFIG.4, the light source device L includes a light source drive circuit12and the light emitter31that includes pluralities of first, second, and third light sources11R,11G, and11B.FIG.4illustrates some of the first, the second, and the third light sources11R,11G, and11B as representatives. As illustrated inFIG.4, the light source drive circuit12is mounted on the light source device L. The light source drive circuit12may be built into the driver IC separately from the light source device L.

Each of the first light sources11R emits red light. Each of the second light sources11G emits green light. Each of the third light sources11B emits blue light. Each of the first, the second, and the third light sources11R,11G, and11B emits the light under the control of the light source drive circuit12. Each of the first, the second, and the third light sources11R,11G, and11B of the present embodiment is a light source using, for example, a light-emitting element such as a light-emitting diode (LED), but is not limited thereto, and only needs to be a light source controllable in light emission timing. The light source drive circuit12controls the light emission timing of the first, the second, and the third light sources11R,11G, and11B under the control of the timing controller13.

As illustrated inFIG.4, the timing controller13receives input signals (such as red-green-blue (RGB) signals) from an image output circuit of an external higher-level controller15through a flexible substrate, for example.

In the display region7, the pixels Pix are arranged in a matrix in a row-column configuration, being arranged in the row and column directions. Each of the pixels Pix includes the switching element1.

As illustrated inFIG.4, the switching element1is a switching element using, for example, a semiconductor, such as a thin-film transistor (TFT). One of the source and the drain of the switching element1is coupled to one of the two electrodes (pixel electrode2). The other of the source and the drain of the switching element1is coupled to a corresponding one of the signal lines SLm. The gate of the switching element1is coupled to a corresponding one of the scan lines GLn. The scan line GLn applies a potential (hereinafter also called “drive potential”) for opening or closing a circuit between the source and the drain of the switching element1under the control of the first and the second scan circuits9A and9B. The first and the second scan circuits9A and9B control the drive potential.

As illustrated inFIG.4, the signal lines SLm are arranged along one of the arrangement directions (row direction) of the pixels Pix. The signal lines SLm extend along the other of the arrangement directions (column direction) of the pixels Pix. Each of the signal lines SLm is shared by the switching elements1of the corresponding pixels Pix arranged in the column direction. The scan lines GLn are arranged along the column direction. The scan lines GLn extend along the row direction. Each of the scan lines GLn is shared by the switching elements1of the corresponding M pixels Pix arranged in the row direction.

The common electrode6is coupled to the common electrode drive circuit10. The common electrode drive circuit10applies a common potential to the common electrode6. When the first and the second scan circuits9A and9B apply drive potentials VGn (VG1, VG2, . . . , VGN (refer toFIG.6)) to the scan lines GLn, the signal output circuit8outputs a pixel signal Sigm (refer toFIG.6) to each of the signal lines SLm to charge a storage capacitor formed between each pixel electrode2and the common electrode6and the liquid crystals (fine particles52) serving as a capacitive load. This operation sets the potential of the pixel electrode2of the pixel Pix to a potential corresponding to the pixel signal Sigm. After the completion of the application of the drive potentials VGn, the storage capacitor and the liquid crystals (fine particles52) serving as the capacitive load hold the potential of the pixel electrode2of the Pixel Pix corresponding to the pixel signal Sigm. The orientation of the liquid crystals (fine particles52) is controlled according to an electric field generated by a difference voltage between the potential of the pixel electrode2of each of the pixels Pix and a common potential Vcom (first common potential VcomL or second common potential VcomH (refer toFIGS.5and6)) of the common electrode6applied by the common electrode drive circuit10.

The timing controller13controls the operation timing of the signal output circuit8, the first and the second scan circuits9A and9B, the common electrode drive circuit10, and the light source drive circuit12. In the present embodiment, the operation control is performed using a field-sequential color (FSC) method.

FIG.5is a timing diagram illustrating an exemplary process of the FSC control of the present embodiment.FIG.5illustrates a schematic timing diagram of two consecutive frame periods F(1) and F(2). The two frame periods F(1) and F(2) illustrated inFIG.5are periodically repeated to perform the operation control using the FSC method according to the present embodiment. That is, in the present embodiment, the two frame periods F(1) and F (2) illustrated inFIG.5are alternately repeated.FIG.5also illustrates the inversion timing of the common potential Vcom applied to the common electrode6by the common electrode drive circuit10and the lighting timing of each of the light sources (first, second, and third light sources11R,11G, and11B) of the light emitter31.

In the FSC control of the present embodiment, each of the frame periods F(1) and F(2) includes a plurality of sub-frame periods. In other words, each of the frame periods F(1) and F(2) is temporally divided into a plurality of sub-frame periods. Specifically, in the example illustrated inFIG.5, each of the frame periods F(1) and F(2) is temporally divided into a first sub-frame period RSF, a second sub-frame period GSF, and a third sub-frame period BSF. The number of the sub-frame periods included in each of the frame periods F(1) and F (2) corresponds to the number of colors of the light sources of the light emitter31. The number and types of colors of the light sources of the light emitter31and the number of the sub-frame periods included in each of the frame periods F(1) and F(2) in the present embodiment are merely exemplary, and are not limited to those cited above, but can be changed as appropriate.

In the FSC control of the present embodiment, the common electrode drive circuit10performs inversion drive to switch the common potential Vcom applied to the common electrode6for each of the sub-frame periods (first sub-frame period RSF, second sub-frame period GSF, and third sub-frame period BSF). Specifically, the common electrode drive circuit10switches the common potential Vcom between the first common potential VcomL, which is relatively low, and the second common potential VcomH, which is relatively high, for each of the sub-frame periods.

The sub-frame periods (first sub-frame period RSF, second sub-frame period GSF, and third sub-frame period BSF) include write periods RW, GW, and BW for writing the pixel signal Sigm and hold periods RH, GH, and BH for holding the pixel signal Sigm by the storage capacitor, respectively, and each include a potential reset period RST of the pixel electrode2and a common potential inversion period RV.

The write periods RW, GW, and BW are periods during which the pixel signals Sigm corresponding to gradation values of different colors are written in the sub-frame periods (first sub-frame period RSF, second sub-frame period GSF, and third sub-frame period BSF), respectively. The hold periods RH, GH, and BH are periods during which the pixel signals Sigm written in the write periods RW, GW, and BW, respectively, of the sub-frame periods are held.

Each of the pixel signals Sigm written in the write periods RW, BW, and GW of the sub-frame periods is set to a potential between a first signal potential VsigL, which is relatively low, and a second signal potential VsigH, which is relatively high, according to the gradation value of each of the pixels Pix. The polarity of the pixel signal Sigm output by the signal output circuit8in each of the write periods RW, BW, and GW varies according to the common potential Vcom applied to the common electrode6by the common electrode drive circuit10.

Specifically, in each of the write periods RW, BW, and GW of the sub-frame periods (first sub-frame period RSF and third sub-frame period BSF of frame period F(1), and second sub-frame period GSF of frame period F(2)) in which the first common potential VcomL is applied to the common electrode6, the signal output circuit8outputs the pixel signal Sigm having a relatively high potential with respect to the first common potential VcomL to the signal line SLm. That is, in each of the write periods RW, BW, and GW of the sub-frame periods in which the first common potential VcomL is applied to the common electrode6, the signal output circuit8outputs the positive-polarity pixel signal Sigm.

In each of the write periods GW, RW, and BW of the sub-frame periods (second sub-frame period GSF of frame period F(1), and first sub-frame period RSF and third sub-frame period BSF of frame period F(2)) in which the second common potential VcomH is applied to the common electrode6, the signal output circuit8outputs the pixel signal Sigm having a relatively low potential with respect to the second common potential VcomH to the signal line SLm. That is, in each of the write periods GW, RW, and BW of the sub-frame periods in which the second common potential VcomH is applied to the common electrode6, the signal output circuit8outputs the negative-polarity pixel signal Sigm.

The light sources of a plurality of colors (such as the first light source11R, the second light source11G, and the third light source11B) included in the light source device L are each controlled to be lit up in a corresponding one of the hold periods RH, GH, and BH of the sub-frame periods (first sub-frame period RSF, second sub-frame period GSF, and third sub-frame period BSF). For example, the first light source11R is a red light source; the second light source11G is a green light source; and the third light source11B is a blue light source.

The first light source11R is lit up during the hold period RH of the first sub-frame period RSF. As a result, red scattered light corresponding to the potential of the pixel signal Sigm corresponding to the gradation value of red (R) written in the write period RW of the first sub-frame period RSF is emitted.

The second light source11G is lit up during the hold period GH of the second sub-frame period GSF. As a result, green scattered light corresponding to the potential of the pixel signal Sigm corresponding to the gradation value of green (G) written in the write period GW of the second sub-frame period GSF is emitted.

The third light source11B is lit up during the hold period BH of the third sub-frame period BSF. As a result, blue scattered light corresponding to the potential of the pixel signal Sigm corresponding to the gradation value of blue (B) written in the write period BW of the third sub-frame period BSF is emitted.

The potential of the pixel electrode2of the pixel Pix held in each of the hold periods RH, GH, and BH of the sub-frame periods (first sub-frame period RSF, second sub-frame period GSF, and third sub-frame period BSF) is reset in a corresponding one of the potential reset periods RST. Specifically, in the potential reset period RST, the signal output circuit8applies the same potential to all the signal lines SLm in the display region7, and the first and the second scan circuits9A and9B collectively apply the drive potential to all the scan lines GLn in the display region7, so as to collectively drive the switching elements1of all the pixel Pix. This operation resets the potential of the pixel electrodes2of all the pixels Pix in the display region7.

After the potential of the pixel electrodes2of all the pixel Pix in the display region7is reset in the potential reset period RST, the common electrode drive circuit10switches the common potential Vcom applied to the common electrode6in the common potential inversion period RV.

Specifically, for example, in the common potential inversion period RV of the first sub-frame period RSF of the frame period F(1), the common electrode drive circuit10switches the common potential Vcom, which is applied to the common electrode6, from the first common potential VcomL to the second common potential VcomH.

For example, in the common potential inversion period RV of the second sub-frame period GSF of the frame period F (1), the common electrode drive circuit10switches the common potential Vcom, which is applied to the common electrode6, from the second common potential VcomH to the first common potential VcomL.

For example, in the common potential inversion period RV of the third sub-frame period BSF of the frame period F(1), the common electrode drive circuit10switches the common potential Vcom, which is applied to the common electrode6, from the first common potential VcomL to the second common potential VcomH.

For example, in the common potential inversion period RV of the first sub-frame period RSF of the frame period F(2), the common electrode drive circuit10switches the common potential Vcom, which is applied to the common electrode6, from the second common potential VcomH to the first common potential VcomL.

For example, in the common potential inversion period RV of the second sub-frame period GSF of the frame period F (2), the common electrode drive circuit10switches the common potential Vcom, which is applied to the common electrode6, from the first common potential VcomL to the second common potential VcomH.

For example, in the common potential inversion period RV of the third sub-frame period BSF of the frame period F (2), the common electrode drive circuit10switches the common potential Vcom, which is applied to the common electrode6, from the second common potential VcomH to the first common potential VcomL.

The FSC control described above periodically repeats the two frame periods F(1) and F(2) so as to control the display of consecutive frame images.

FIG.6is a timing diagram illustrating an example of inversion drive control of the common potential in the FSC control according to a comparative example.FIG.6illustrates a schematic timing diagram for three consecutive sub-frame periods. Specifically, for example, the timing diagram inFIG.5exemplarily illustrates the sub-frame periods (first sub-frame period RSF, second sub-frame period GSF, and third sub-frame period BSF) in the frame period F(1); while the first, the second, and the third sub-frame periods RSF, GSF, and BSF are denoted as sub-frame periods SF(1), SF(2), and SF(3), respectively, in this comparative example. In addition, each of the write periods RW, GW, and BW and each of the hold periods RH, GH, and BH in the sub-frame period SF are denoted as write period W and hold period H, respectively.

In sub-frame periods SF(1) and SF(3), the common electrode drive circuit10supplies the first common potential VcomL to the common electrode6. In the sub-frame period SF(2), the common electrode drive circuit10supplies the second common potential VcomH to the common electrode6.

The write period W of each of the sub-frame periods SF(1), SF(2), and SF(3) includes N row write periods W/N obtained by temporally dividing the write period W by the number N of the scan lines GLn in the display region7. The first and the second scan circuits9A and9B sequentially supply the drive potentials VGn (VG1, VG2, . . . , VGN) to the scan lines GLn (GL1, GL2, . . . , GLN) in each of the row write periods W/N. Each of the drive potentials VGn is, for example, a second gate potential VGH that is relatively high than a first gate potential VGL that is relatively low.

The signal output circuit8outputs positive-polarity pixel signals Sigm+(Sig1m+, Sig2m+, . . . , SigNm+) corresponding to the signal lines SLm (SL1, SL2, . . . , SLM−1, SLM) in each of the row write periods W/N in the write period W of each of the sub-frame periods SF(1) and SF(3). At this time, the drive potentials VGn (VG1, VG2, . . . , VGN) are respectively supplied to the scan lines GLn (GL1, GL2, . . . , GLN) to control to turn on the switching elements1of the respective pixels Pix, and thus, pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) of the respective pixels Pix are set to the potentials of the positive-polarity pixel signals Sigm+(Sig1m+, Sig2m+, . . . , SigNm+).FIG.6illustrates an example in which the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) of the respective pixels Pix in the write period W of each of the sub-frame periods SF(1) and SF(3) are set to the second signal potential VsigH. In this example, the maximum gradation value is written to each of the pixels Pix in the write period W of each of the sub-frame periods SF(1) and SF(3). The potential corresponding to the minimum gradation value that can be written to each of the pixels Pix in the write period W of each of the sub-frame periods SF(1) and SF(3) is the first signal potential VsigL.

The signal output circuit8outputs negative-polarity pixel signals Sigm− (Sig1m−, Sig2m−, . . . , SigNm−) corresponding to the signal lines SLm (SL1, SL2, . . . , SLM−1, SLM) in each of the row write periods W/N in the write period W of the sub-frame period SF(2). At this time, the drive potentials VGn (VG1, VG2, . . . , VGN) are respectively supplied to the scan lines GLn (GL1, GL2, . . . , GLN) to control to turn on the switching elements1of the respective pixels Pix, and thus, the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) of the respective pixels Pix are set to the potentials of the negative-polarity pixel signals Sigm− (Sig1m−, Sig2m−, . . . , SigNm−).FIG.6illustrates an example in which the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) of the respective pixels Pix in the write period W of the sub-frame period SF(2) are set to the first signal potential VsigL. In this example, the maximum gradation value is written to each of the pixels Pix in the write period W of the sub-frame period SF(2). The potential corresponding to the minimum gradation value that can be written to each of the pixels Pix in the write period W of the sub-frame period SF(2) is the second signal potential VsigH.

The pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) written to the respective pixels Pix in the row write periods W/N are maintained after the switching elements1are turned off. In the hold period H after the write period W, the light sources (first light sources11R, second light sources11G, or third light sources11B) corresponding to the sub-frame period SF(1), SF(2), or SF(3) are turned on to display an image in accordance with the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) written to the respective pixels Pix.

In the comparative example illustrated inFIG.6, the potential of each of the signal lines SLm (SL1, SL2, . . . , SLM−1, SLM) after the write period W of each of the sub-frame periods SF(1) and SF(3) is set to the first signal potential VsigL.

In the potential reset period RST of each of the sub-frame periods SF(1) and SF(3), the drive potentials VGn (VG1, VG2, . . . , VGN) are collectively supplied to all the scan lines GLn in the display region7to control to turn on the switching elements1of the respective pixels Pix. As a result, the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) written to the respective pixels Pix in the row write periods W/N of each of the sub-frame periods SF(1) and SF(3) change to the first signal potential VsigL. In the subsequent common potential inversion period RV, after the potential of the common electrode6is switched from the first common potential VcomL to the second common potential VcomH, the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) capacitively coupled to the common electrode6change to the second signal potential VsigH, as indicated by upward arrows inFIG.6.

In the subsequent row write periods W/N of the sub-frame period SF(2), when the first signal potential VsigL (maximum gradation value) is written as the negative-polarity pixel signals Sigm− (Sig1m−, Sig2m−, . . . , SigNm−) to the respective pixels Pix, the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) change from the second signal potential VsigH to the first signal potential VsigL, as indicated by downward arrows inFIG.6.

In the comparative example illustrated inFIG.6, the potential of each of the signal lines SLm (SL1, SL2, . . . , SLM−1, SLM) after the write period W of the sub-frame period SF(2) is set to the second signal potential VsigH. In the potential reset period RST of the sub-frame period SF(2), the drive potentials VGn (VG1, VG2, . . . , VGN) are collectively supplied to all the scan lines GLn in the display region7to control to turn on the switching elements1of the respective pixels Pix.

As a result, the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) written to the respective pixels Pix in the row write periods W/N of the sub-frame period SF(2) change to the second signal potential VsigH. In the subsequent common potential inversion period RV, after the potential of the common electrode6is switched from the second common potential VcomH to the first common potential VcomL, the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) capacitively coupled to the common electrode6change to the first signal potential VsigL, as indicated by downward arrows inFIG.6.

In the subsequent row write periods W/N of each of the sub-frame periods SF(1) and SF(3), when the second signal potential VsigH (maximum gradation value) is written as the positive-polarity pixel signals Sigm+(Sig1m+, Sig2m+, . . . , SigNm+) to the respective pixels Pix, the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) change from the first signal potential VsigL to the second signal potential VsigH, as indicated by upward arrows inFIG.6.

FIG.7Ais a conceptual diagram illustrating a first example of a pixel electrode potential change when the maximum gradation value is written to the pixel in the comparative example illustrated inFIG.6.FIG.7Bis a conceptual diagram illustrating a second example of the pixel electrode potential change when the maximum gradation value is written to the pixel in the comparative example illustrated inFIG.6.FIG.7Aillustrates an example in which the second signal potential VsigH (maximum gradation value) is written as the positive-polarity pixel signals Sigm+ (Sig1m+, Sig2m+, . . . , SigNm+) to the respective pixels Pix in the row write periods W/N of each of the sub-frame periods SF(1) and SF(3).FIG.7Billustrates an example in which the first signal potential VsigL (maximum gradation value) is written as the negative-polarity pixel signals Sigm− (Sig1m−, Sig2m−, . . . , SigNm−) to the respective pixels Pix in the row write periods W/N of the sub-frame period SF(2).

As illustrated inFIG.7A, in the comparative example, in the row write periods W/N of each of the sub-frame periods SF(1) and SF(3), when the second signal potential VsigH (maximum gradation value) is written as the positive-polarity pixel signals Sigm+(Sig1m+, Sig2m+, . . . , SigNm+) to the respective pixels Pix, a longer time is required until each of the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) changes from the first signal potential VsigL corresponding to the minimum gradation value to the second signal potential VsigH corresponding to the maximum gradation value and is stabilized. This phenomenon results in the longer row write periods W/N in each of the sub-frame periods SF(1) and SF(3), which results in the longer write period W in each of the sub-frame periods SF(1) and SF(3).

As illustrated inFIG.7B, in the comparative example, in the row write periods W/N of the sub-frame period SF(2), when the first signal potential VsigL (maximum gradation value) is written as the negative-polarity pixel signals Sigm− (Sig1m−, Sig2m−, . . . , SigNm−) to the respective pixels Pix, a longer time is required until each of the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) changes from the second signal potential VsigH corresponding to the minimum gradation value to the first signal potential VsigL corresponding to the maximum gradation value and is stabilized. This phenomenon results in the longer row write periods W/N in the sub-frame period SF(2), which results in the longer write period W in the sub-frame period SF(2).

First Embodiment

FIG.8is a timing diagram illustrating an example of the inversion drive control of the common potential in the FSC control according to a first embodiment. The following describes differences from the comparative example illustrated inFIG.6, with reference toFIG.8.

In the first embodiment, the potential of each of the signal lines SLm (SL1, SL2, . . . , SLM−1, SLM) after the write period W of each of the sub-frame periods SF(1) and SF(3) is set to an intermediate potential VsigC between the first signal potential VsigL and the second signal potential VsigH.

In the potential reset period RST of each of the sub-frame periods SF(1) and SF(3), when the drive potentials VGn (VG1, VG2, . . . , VGN) are collectively supplied to all the scan lines GLn in the display region7to control to turn on the switching elements1of the respective pixels Pix, the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) written to the respective pixels Pix in the row write periods W/N of each of the sub-frame periods SF(1) and SF(3) change to the intermediate potential VsigC.

In the first embodiment, the on-state of each of the switching elements1of the respective pixels Pix is maintained during the common potential inversion period RV. As a result, the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) are maintained at the intermediate potential VsigC after the potential of the common electrode6is switched from the first common potential VcomL to the second common potential VcomH.

In the subsequent row write periods W/N of the sub-frame period SF(2), when the first signal potential VsigL (maximum gradation value) is written as the negative-polarity pixel signals Sigm− (Sig1m−, Sig2m−, . . . , SigNm−) to the respective pixels Pix, the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) change from the intermediate potential VsigC to the first signal potential VsigL, as indicated by downward arrows inFIG.8.

In the first embodiment, the potential of each of the signal lines SLm (SL1, SL2, . . . , SLM−1, SLM) after the write period W of the sub-frame period SF(2) is set to the intermediate potential VsigC between the second signal potential VsigH and the first signal potential VsigL.

In the potential reset period RST of the sub-frame period SF(2), when the drive potentials VGn (VG1, VG2, . . . , VGN) are collectively supplied to all the scan lines GLn in the display region7to control to turn on the switching elements1of the respective pixels Pix, the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) written to the respective pixels Pix in the row write periods W/N of the sub-frame period SF(2) change to the intermediate potential VsigC.

In the first embodiment, the on-state of each of the switching elements1of the respective pixels Pix is maintained during the common potential inversion period RV. As a result, the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) are maintained at the intermediate potential VsigC after the potential of the common electrode6is switched from the second common potential VcomH to the first common potential VcomL.

In the subsequent row write periods W/N of each of the sub-frame periods SF(1) and SF(3), when the second signal potential VsigH (maximum gradation value) is written as the positive-polarity pixel signals Sigm+(Sig1m+, Sig2m+, . . . , SigNm+) to the respective pixels Pix, the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) change from the intermediate potential VsigC to the second signal potential VsigH, as indicated by upward arrows inFIG.8.

FIG.9Ais a conceptual diagram illustrating a first example of the pixel electrode potential change when the maximum gradation value is written to the pixel in the first embodiment.FIG.9Bis a conceptual diagram illustrating a second example of the pixel electrode potential change when the maximum gradation value is written to the pixel in the first embodiment.FIG.9Aillustrates an example in which the second signal potential VsigH (maximum gradation value) is written as the positive-polarity pixel signals Sigm+ (Sig1m+, Sig2m+, . . . , SigNm+) to the respective pixels Pix in the row write periods W/N of each of the sub-frame periods SF(1) and SF(3).FIG.9Billustrates an example in which the first signal potential VsigL (maximum gradation value) is written as the negative-polarity pixel signals Sigm− (Sig1m−, Sig2m−, . . . , SigNm−) to the respective pixels Pix in the row write periods W/N of the sub-frame period SF(2).

As illustrated inFIG.9A, in the first embodiment, when the second signal potential VsigH (maximum gradation value) is written as the positive-polarity pixel signals Sigm+ (Sig1m+, Sig2m+, . . . , SigNm+) to the respective pixels Pix in the row write periods W/N of each of the sub-frame periods SF(1) and SF(3), the time until the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) are stabilized at the second signal potential VsigH can be made shorter than in the comparative example. Therefore, the row write period W/N in each of the sub-frame periods SF(1) and SF(3) can be reduced to (W/N)/2, which is shorter than in the comparative example, resulting in a shorter write period W of each of the sub-frame periods SF(1) and SF(3).

As illustrated inFIG.9B, in the first embodiment, when the first signal potential VsigL (maximum gradation value) is written as the negative-polarity pixel signals Sigm− (Sig1m−, Sig2m−, . . . , SigNm−) to the respective pixels Pix in the row write periods W/N of the sub-frame period SF(2), the time until the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) are stabilized at the first signal potential VsigL can be made shorter than in the comparative example. Therefore, the row write period W/N in the sub-frame period SF(2) can be reduced to (W/N)/2, which is shorter than in the comparative example, resulting in a shorter write period W of the sub-frame period SF(2).

In the example illustrated inFIG.8, when the potential of the common electrode6is switched from the first common potential VcomL to the second common potential VcomH in the common potential inversion period RV of each of the sub-frame periods SF(1) and SF(3), the potential is switched to an intermediate potential VcomM between the first common potential VcomL and the second common potential VcomH, and then switched to the second common potential VcomH.

In the example illustrated inFIG.8, when the potential of the common electrode6is switched from the second common potential VcomH to the first common potential VcomL in the common potential inversion period RV of the sub-frame periods SF(2), the potential is switched to the intermediate potential VcomM between the second common potential VcomH and the first common potential VcomL, and then switched to the first common potential VcomL.

These operations can reduce transient potential variations of the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) when the potential of the common electrode6changes in the common potential inversion period RV.

Second Embodiment

FIG.10is a timing diagram illustrating an example of the inversion drive control of the common potential in the FSC control according to a second embodiment. The following describes differences from the comparative example illustrated inFIG.6, with reference toFIG.10.

In the second embodiment, a precharge period PCH is provided in which, after the potential of the common electrode6is switched from the first common potential VcomL to the second common potential VcomH, the drive potentials VGn (VG1, VG2, . . . , VGN) are collectively supplied to all the scan lines GLn in the display region7to control to turn on the switching elements1of the respective pixels Pix.

In the second embodiment, the potential of each of the signal lines SLm (SL1, SL2, . . . , SLM−1, SLM) after the write period W of each of the sub-frame periods SF(1) and SF(3) is set to the first signal potential VsigL, in the same manner as in the comparative example, and set to the intermediate potential VsigC between the first signal potential VsigL and the second signal potential VsigH in the common potential inversion period RV of each of the sub-frame periods SF(1) and SF(3).

In the potential reset period RST of each of the sub-frame periods SF(1) and SF(3), when the drive potentials VGn (VG1, VG2, . . . , VGN) are collectively supplied to all the scan lines GLn in the display region7to control to turn on the switching elements1of the respective pixels Pix, the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) written to the respective pixels Pix in the row write periods W/N of each of the sub-frame periods SF(1) and SF(3) change to the first signal potential VsigL.

In the subsequent common potential inversion period RV, after the potential of the common electrode6is switched from the first common potential VcomL to the second common potential VcomH, the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) capacitively coupled to the common electrode6change to the second signal potential VsigH, in the same manner as in the comparative example.

In the state where the potential of each of the signal lines SLm (SL1, SL2, . . . , SLM−1, SLM) is set to the intermediate potential VsigC, the drive potentials VGn (VG1, VG2, . . . , VGN) are collectively supplied to all the scan lines GLn in the display region7to control to turn on the switching elements1of the respective pixels Pix, in the precharge period PCH. Thereby, the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) are changed from the second signal potential VsigH to the intermediate potential VsigC.

In the subsequent row write periods W/N of the sub-frame period SF(2), when the first signal potential VsigL (maximum gradation value) is written as the negative-polarity pixel signals Sigm− (Sig1m−, Sig2m−, . . . , SigNm−) to the respective pixels Pix, the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) change from the intermediate potential VsigC to the first signal potential VsigL, as indicated by downward arrows inFIG.10.

In the second embodiment, the potential of each of the signal lines SLm (SL1, SL2, . . . , SLM−1, SLM) after the write period W of the sub-frame period SF(2) is set to the second signal potential VsigH, in the same manner as in the comparative example, and set to the intermediate potential VsigC between the second signal potential VsigH and the first signal potential VsigL in the common potential inversion period RV of each of the sub-frame period SF(2).

In the potential reset period RST of the sub-frame period SF(2), when the drive potentials VGn (VG1, VG2, . . . , VGN) are collectively supplied to all the scan lines GLn in the display region7to control to turn on the switching elements1of the respective pixels Pix, the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) written to the respective pixels Pix in the row write periods W/N of the sub-frame period SF(2) change to the second signal potential VsigH.

In the subsequent common potential inversion period RV, after the potential of the common electrode6is switched from the second common potential VcomH to the first common potential VcomL, the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) capacitively coupled to the common electrode6change to the first signal potential VsigL, in the same manner as in the comparative example.

In the state where the potential of each of the signal lines SLm (SL1, SL2, . . . , SLM−1, SLM) is set to the intermediate potential VsigC, the drive potentials VGn (VG1, VG2, . . . , VGN) are collectively supplied to all the scan lines GLn in the display region7to control to turn on the switching elements1of the respective pixels Pix, in the precharge period PCH. Thereby, the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) are changed from the first signal potential VsigL to the intermediate potential VsigC.

In the subsequent row write periods W/N of each of the sub-frame periods SF(1) and SF(3), when the second signal potential VsigH (maximum gradation value) is written as the positive-polarity pixel signals Sigm+(Sig1m+, Sig2m+, . . . , SigNm+) to the respective pixels Pix, the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) change from the intermediate potential VsigC to the second signal potential VsigH, as indicated by upward arrows inFIG.10.

In also the second embodiment, in the same manner as in the first embodiment, when the second signal potential VsigH (maximum gradation value) is written as the positive-polarity pixel signals Sigm+(Sig1m+, Sig2m+, . . . , SigNm+) to the respective pixels Pix in the row write periods W/N of each of the sub-frame periods SF(1) and SF(3), the time until the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) are stabilized at the second signal potential VsigH can be made shorter than in the comparative example. Therefore, the row write period W/N in each of the sub-frame periods SF(1) and SF(3) can be reduced to (W/N)/2, which is shorter than in the comparative example, resulting in a shorter write period W of each of the sub-frame periods SF(1) and SF(3).

In addition, when the first signal potential VsigL (maximum gradation value) is written as the negative-polarity pixel signals Sigm− (Sig1m−, Sig2m−, . . . , SigNm−) to the respective pixels Pix in the row write periods W/N of the sub-frame period SF(2), the time until the pixel electrode potentials Vpixnm (Vpix1m, Vpix2m, . . . , VpixNm) are stabilized at the first signal potential VsigL can be made shorter than in the comparative example. Therefore, the row write period W/N in the sub-frame period SF(2) can be reduced to (W/N)/2, which is shorter than in the comparative example, resulting in a shorter write period W of the sub-frame period SF(2).

As described above, the embodiments described above can shorten the write period W in the frame period F. As a result, for example, the frame rate can be improved. The hold period H can be relatively lengthened, allowing the lighting time of each of the light sources (first, second, and third light sources11R,11G, and11B) of the light emitter31to be lengthened. As a result, for example, the emission intensity of each of the light sources (first, second, and third light sources11R,11G, and11B) of the light emitter31can be reduced. Alternatively, the number of the light sources can be reduced, thereby being capable of contributing to power saving and/or cost reduction. Furthermore, since the number of time divisions of the write period W can be increased, the number of pixels on the display panel P can be increased to achieve a higher definition.

While the preferred embodiments of the present disclosure have been described above, the present disclosure is not limited to the embodiments described above. The content disclosed in the embodiments is merely an example, and can be variously modified within the scope not departing from the gist of the present disclosure. For example, any modifications appropriately made within the scope not departing from the gist of the present disclosure also naturally belong to the technical scope of the present disclosure.