Patent ID: 12199066

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, the present embodiment will be described with reference to the accompanying drawings. For easy understanding of the description, components that are the same throughout the drawings are denoted by the same reference signs as much as possible, and repeated description will be omitted.

FIG.1is a cross-sectional view for illustrating the structure of a semiconductor memory device E according to a first embodiment. The semiconductor memory device E includes a base substrate B and chips C1, C2, C3, C4, C5, and C6. The chip C1is joined to the base substrate B. A plurality of metal balls BE are joined to a face of the base substrate B on the side opposite to the face to which the chip C1is joined. The chip C2is joined to a face of the chip C1on the side opposite to the face joined to the base substrate B. The chip C3is joined to a face of the chip C2on the side opposite to the face joined to the chip C1. The chip C4is joined to a face of the chip C3on the side opposite to the face joined to the chip C2. The chip C5is joined to a face of the chip C4on the side opposite to the face joined to the chip C3. The chip C6is joined to a face of the chip C5on the side opposite to the face joined to the chip C4. In this manner, the chips C1, C2, C3, C4, C5, and C6are stacked on the base substrate B.

A protective film P is provided so as to cover the side faces of the chips C1, C2, C3, C4, C5, and C6. The protective film P also at least partially covers the base substrate B. In the present embodiment, as an example, the protective film P is provided such that it is relatively thick on the side of the chip C1and is relatively thin on the side of the chip C6. The thickness of the protective film P is not limited thereto, and for example, the protective film P with a uniform thickness may be provided. The protective film P may also be provided such that it is relatively thick on the side of the chip C6and is relatively thin on the side of the chip C1. The protective film P may also be removed. A molding resin layer M is provided so as to cover the protective film P.

Next, a method for producing the semiconductor memory device E will be described with reference toFIGS.2to11. AlthoughFIGS.2to11illustrate the production of two semiconductor memory devices E, it is also possible to concurrently produce a number of, that is, three or more semiconductor memory devices E.

As illustrated inFIG.2, the base substrate B bonded to a support substrate SB is prepared. It should be noted that the base substrate B may also be obtained by forming wire layers on the support substrate SB. A predetermined number of chips C1obtained through dicing are bonded to the base substrate B at predetermined positions. Silicon C1aon each chip C1is thick. A through-silicon via (TSV) T1extending from each chip C1is buried in the silicon C1a.

Next, as illustrated inFIG.3, a protective film P1is formed so as to cover each chip C1, the silicon C1a, and the base substrate B. The protective film P1is a film with high mechanical strength. For example, a film of SiO2, SiN, SiC, or BN is used as the protective film P1. Besides, a variety of inorganic insulating films, such as DLC (diamond-like carbon), may be used, for example.

Next, as illustrated inFIG.4, the silicon C1ais ground with a backside grinder. The silicon C1aground with the backside grinder has a high surface roughness.

Next, as illustrated inFIG.5, the silicon C1ais made thinner by CMP (Chemical Mechanical Polishing). Through CMP, crystal defects are removed and the surface roughness is improved. The protective film P1is not easily removed through CMP, and thus, the silicon C1ais removed more than the protective film P1.

Next, as illustrated inFIG.6, dry etching is performed on the silicon C1ato expose the top portion of the through-silicon via T1. Next, as illustrated in FIG.7, an oxide film C1bto serve as a bonding face is formed conformally. As the oxide film C1b, a SiO2film is used, for example.

Next, as illustrated inFIG.8, the protective film P1, the oxide film C1b, and the through-silicon via T1are made thinner by CMP so that a flat bonding face is formed. The oxide film C1bformed on each side face of each chip C1at this time is referred to as a first oxide film, and the oxide film C1bformed on the rear face of each chip C1at this time is referred to as a second oxide film. The second oxide film is thinner around the peripheral edge portions of each chip C1than around the central portion of the chip C1. The upper end portion of the protective film P1on each side face of each chip C1is located between the first oxide film and the second oxide film, and further, the upper end portion of the protective film P1is exposed from the first oxide film and the second oxide film.

Next, as illustrated inFIG.9, a next chip C2is bonded to the bonding face of each chip C1.

A process performed on the chip C2is similar to that performed on the chip C1. That is, a protective film P2is formed on the chip C2. The protective film P2is formed on the rear face and the side faces of the chip C2and also on the side faces of the chip C1. If the protective film P1and the oxide film C1bremain on each side face of the chip C1, the protective film P2is formed thereon. Then, the chip C2is made thinner from the side of its rear face so that the top portion of the through-silicon via is exposed.

Then, an oxide film C2bto serve as a bonding face is formed on the rear face of the chip C2. The oxide film C2bis also formed on the side faces of the chip C2and on the side faces of the chip C1. At this time, the oxide film C2bmay also be formed on the protective film P2.

Then, the protective film, the oxide film, and the through-silicon via are made thinner by CMP so that a flat face is formed. Hereinafter, the procedures described with reference toFIGS.3to8are repeated to stack the chips C3, C4, C5, and C6and thus form a chip stack. As illustrated inFIG.10, a protective film is formed each time a chip is stacked. Thus, the resulting protective film P after the chip C6is stacked is thicker on each side face of the chip C1than on each side face of the chip C6.

FIG.11is an enlarged view of an XI portion inFIG.10. As illustrated inFIG.11, the protective film P1, the oxide film C1b, the protective film P2, the oxide film C2b, a protective film P3, an oxide film C3b, a protective film P4, an oxide film C4b, a protective film P5, an oxide film C5b, a protective film P6, and an oxide film C6bare stacked in this order. The protective film P1and the oxide film C1bare a stacked film formed in providing the chip C1as described above. The protective film P2and the oxide film C2bare a stacked film formed in providing the chip C2on the chip C1. The protective film P3and the oxide film C3bare a stacked film formed in providing the chip C3on the chip C2. The protective film P4and the oxide film C4bare a stacked film formed in providing the chip C4on the chip C3. The protective film P5and the oxide film C5bare a stacked film formed in providing the chip C5on the chip C4. The protective film P6and the oxide film C6bare a stacked film formed in providing the chip C6on the chip C5.

Six stacked films each including a stack of a protective film and an oxide film are provided on each side face of the chip C1as illustrated inFIG.11. Likewise, six stacked films each including a stack of a protective film and an oxide film are also provided on the base substrate B.

On each side face of the chip C2, neither the protective film P1nor the oxide film C1bis formed, but the protective film P2and the oxide film C2bare stacked first. Thus, five stacked films each including a stack of a protective film and an oxide film are provided. On each side face of the chip C3, neither the protective film P2nor the oxide film C2bis formed besides the protective film P1and the oxide film C1b, but the protective film P3and the oxide film C3bare stacked first. Thus, four stacked films each including a stack of a protective film and an oxide film are provided.

On each side face of the chip C4, none of the protective films P1, P2, and P3or none of the oxide films C1b, C2b, and C3bis formed, but the protective film P4and the oxide film C4bare stacked first. Thus, three stacked films each including a stack of a protective film and an oxide film are provided. On each side face of the chip C5, none of the protective films P1, P2, P3, and P4or none of the oxide films C1b, C2b, C3b, and C4bis formed, but the protective film P5and the oxide film C5bare stacked first. Thus, two stacked films each including a stack of a protective film and an oxide film are provided. On each side face of the chip C6, none of the protective films P1, P2, P3, P4, and P5or none of the oxide films C1b, C2b, C3b, C4b, and C5bis formed, but the protective film P6and the oxide film C6bare stacked first. Thus, a single stacked film including a stack of a protective film and an oxide film is provided.

At this time, the chip C6, which is the uppermost layer, has nothing to which the through-silicon via T1is connected. Thus, there may be a case where the chip C6need not be made thinner. In such a case, a stacked film is not provided on each side face of the chip C6. Thus, the protective film P6and the oxide film C6billustrated inFIG.11are not formed. That is, on each side face of the chip C1, five stacked films each including a stack of a protective film and an oxide film are provided. In such a case, five stacked films each including a stack of a protective film and an oxide film are provided on the base substrate B.

Next, as illustrated inFIG.12, a molding resin layer M is formed. Then, the support substrate SB is removed and the structure is diced into individual pieces so that the semiconductor memory device E illustrated inFIG.1is obtained. The protective film P is partially exposed from the side faces of the molding resin M. The exposed protective film P is a stacked film of SiN and SiO2alternately repeated a plurality of times along the direction perpendicular to the surface of the base substrate B. The number of the repeated stacks may be the same as the number of the stacked chips or smaller than that by one. The protective film P on the base substrate B may be removed before the molding resin layer M is formed. In such a case, the protective film P is not exposed from the side faces of the molding resin layer M.

Next, the chip C1will be further described with reference toFIG.13.FIG.13is a cross-sectional view of the chip C1, and is a cross-sectional view of the state described with reference toFIG.2. As illustrated inFIG.13, the chip C1is a three-dimensional memory including an array chip1and a circuit chip2bonded together.

The array chip1includes a memory cell array11, an insulating film12, a substrate13, and an insulating film14. The memory cell array11includes a plurality of memory cells. The insulating film12is provided below the memory cell array11. The substrate13is provided below the insulating film12. The insulating film14is provided below the substrate13.

The array chip1further includes an interlayer dielectric15and an insulating film16. The interlayer dielectric15is provided above the memory cell array11. The insulating film16is provided above the interlayer dielectric15. The insulating films12,14, and16are silicon oxide films or silicon nitride films, for example. The substrate13is a semiconductor substrate, such as a silicon substrate, for example.

The circuit chip2is provided above the array chip1. Reference sign S indicates the bonded face of the array chip1and the circuit chip2. The array chip1and the circuit chip2are bonded together after having been formed individually. The circuit chip2includes an insulating film17, an interlayer dielectric18, and a semiconductor19. The interlayer dielectric18is provided above the insulating film17. The semiconductor19is provided above the interlayer dielectric18. The insulating film17is a silicon oxide film or a silicon nitride film, for example.

FIG.13illustrates the X-direction and the Y-direction that are parallel with the surfaces S1and S2of the substrate13, the surface S3of the semiconductor19, and the surface S4of a substrate60, and are perpendicular to each other, and also illustrates the Z-direction perpendicular to the surfaces S1and S2and the surfaces S3and S4. In this specification, the +Z-direction is handled as the upward direction, and the Z-direction is handled as the downward direction. For example, the memory cell array11is located below the substrate60and above the substrate13. The Z-direction may either coincide with or not coincide with the direction of gravity.

The array chip1includes, as electrode layers in the memory cell array11, a plurality of word lines WL, a back gate BG, and a selection gate SG.FIG.13illustrates a stepped structure portion21of the memory cell array11. The array chip1and the circuit chip2are joined.

As illustrated inFIG.13, each word line WL is electrically connected to a word wire layer23via a contact plug22. The back gate BG is electrically connected to a back gate wire layer25via a contact plug24. The selection gate SG is electrically connected to a selection gate wire layer27via a contact plug26. Columnar portions CL are provided so as to penetrate the selection gate SG. The word lines WL, the back gate BG, and the columnar portions CL are electrically connected to bit lines BL via plugs28, and are also electrically connected to the substrate13.

The circuit chip2includes a plurality of transistors31. Each transistor31includes a gate electrode32, a source diffusion layer (not illustrated), and a drain diffusion layer (not illustrated). The gate electrode32is provided on the semiconductor19with a gate insulating film (not illustrated) interposed therebetween. The source diffusion layer and the drain diffusion layer are provided in the semiconductor19.

The circuit chip2further includes plugs33, wire layers34, and wire layers35. The plurality of plugs33are provided on the source diffusion layers or the drain diffusion layers of the respective transistors31. The plurality of the wire layers34are provided on the respective plugs33, and include a plurality of wires. The plurality of wire layers35are provided on the respective wire layers34, and include a plurality of wires.

The circuit chip2further includes via plugs36and metal pads37. The plurality of via plugs36are provided on the respective wire layers35. The plurality of metal pads37are provided in the insulating film17and on the respective via plugs36.

The circuit chip2further includes the substrate60and through-silicon vias61. The substrate60is provided on the surface S4of the semiconductor19. The substrate60is a semiconductor substrate, such as a silicon oxide film or silicon, for example. The through-silicon vias61are provided in the interlayer dielectric18, the semiconductor19, and the substrate60, and are provided on the respective wire layers34. The substrate60corresponds to the silicon C1ainFIG.2, for example. The through-silicon vias61correspond to the through-silicon vias T1inFIG.2, for example. The through-silicon vias61are formed so as to be buried in the substrate60before the wire layers34are formed, for example. The circuit chip2includes a CMOS control circuit (i.e., a logic circuit) for controlling the array chip1.

The array chip1includes metal pads41, via plugs42, and wire layers43. The plurality of metal pads41are provided in the insulating film16and on the respective metal pads37. The plurality of via plugs42are provided on the respective metal pads41. The plurality of wire layers43are provided on the respective via plugs42, and include a plurality of wires. Each word line WL and each bit line BL are electrically connected to the corresponding wire in the wire layer43.

The array chip1further includes a plug44, plugs46, and metal pads47. The plug44is provided in the interlayer dielectric15and the insulating film12, and is provided on the wire layer43. The plug46is provided in the substrate13and the insulating film14with an insulating film45interposed therebetween, and is provided on the plug44. The metal pad47is provided in the insulating film14, and is provided on the plug46. The metal pad47is provided flush with the lower face of the insulating film14. The metal pad47is an external connection pad of the chip C1.

FIG.14is a cross-sectional view illustrating a state in which the chip C1is joined to the base substrate B by bonding. The base substrate B includes external terminals70, wire layers71, plugs72, and metal pads73. The plurality of external terminals70are provided below the base substrate B. The external terminals70are metal terminals for connection to the outside, and serve a similar role to the metal balls BE described with reference toFIG.1.

The wire layers71are provided in the base substrate B, and include a plurality of wires. The plug72is provided in the base substrate B, and is provided on the wire layer71. The metal pad73is provided on the plug72. The metal pad73is provided in the base substrate B, and is provided flush with the upper face of the base substrate B.

The metal pads47of the chip C1and the metal pads73of the base substrate B at corresponding positions are arranged opposite each other, and are joined together by bonding.

A controller may be provided in the base substrate.FIG.15illustrates an example of a base substrate Ba in which a controller74is provided. The controller74is a controller for controlling the chip C1, for example. The controller74and the metal pads73are connected via the plugs72.

FIG.16is a cross-sectional view illustrating a state in which the chip C2is further joined to the chip C1illustrated inFIG.14by bonding. In the state illustrated inFIG.14, the top portions of the through-silicon vias61of the chip C1are exposed using the method described with reference toFIGS.3to9, and then, the chip C2is put on the chip C1. The through-silicon vias61of the chip C1and the metal pads47of the chip C2at corresponding positions are arranged opposite each other, and are joined by bonding. A face of the chip C2on the side of the chip C1is formed of an insulating film, such as a silicon oxide film, for example, and may be formed flush with the pads47. A face of the chip C1on the side of the chip C2is formed of an insulating film, such as a silicon oxide film, for example, and may be formed flush with the through-silicon vias61.

As illustrated inFIG.17, an example in which the through-silicon vias61of the chip C1and the metal pads47of the chip C2are arranged will be described. FIG.17illustrates the upper face of the chip C1and the lower face of the chip C2. In the example illustrated inFIG.17, through-silicon vias61acorrespond to metal pads47a, and through-silicon vias61bcorrespond to metal pads47b. The chip C2is put on the chip C1and is bonded thereto so that corresponding vias and pads are arranged opposite each other.

InFIG.18, a case where the chip C1is joined to the base substrate B will be described.FIG.18illustrates the upper face of the base substrate B and the lower face of the chip C1. In the example illustrated inFIG.18, metal pads73acorrespond to metal pads47a, and metal pads73bcorrespond to metal pads47b. The chip C1is put on the base substrate B and is bonded thereto so that corresponding pads are arranged opposite each other.

AlthoughFIG.18illustrates an example in which the metal pads73are arranged linearly along the short side of the base substrate B and the metal pads47are also arranged linearly along the short side of the chip C1, the arrangement patterns of the metal pads73and the metal pads47are not limited thereto.

As illustrated inFIG.19, the metal pads may be arranged in an irregular pattern.FIG.19illustrates the upper face of a base substrate BD and the lower face of a chip CID. In the example illustrated inFIG.19, a metal pad73Dacorresponds to a metal pad47Da, and a metal pad73Dbcorresponds to a metal pad47Db. The chip C1D is put on the base substrate BD and is bonded thereto so that corresponding pads are arranged opposite each other. It should be noted that as illustrated in the example ofFIG.19, the arrangement pattern of the metal pads in the chip CID may be changed according to the arrangement pattern of the metal pads in the base substrate BD, or it is also possible to perform rewiring while using the arrangement pattern of the metal pads in the chip C1illustrated in the example ofFIG.18.

FIG.20is a view for illustrating a semiconductor memory device E1for which the base substrate Ba described with reference toFIG.15is used. As illustrated inFIG.20, the base substrate Ba includes the controller74. The wire layers71are provided in the base substrate Ba. Chips C are stacked on the base substrate Ba. Each chip C is not limited to the one obtained by joining a memory board and a CMOS (Complementary Metal-oxide Semiconductor) like the chip C1described with reference toFIG.13and the like, and may include only a memory board, for example. A protective film P is provided on the outer periphery of the plurality of stacked chips C. A molding resin layer M is provided around the protective film P.

FIG.21is a cross-sectional view for illustrating the structure of a semiconductor memory device E2according to a second embodiment. The semiconductor memory device E2includes a base substrate B and a plurality of chips C. The chips C are held on the base substrate B while being supported by bonding portions81. The base substrate B and the chips C are electrically connected via connection electrodes82. A plurality of metal balls BE are joined to a face of the base substrate B on the side opposite to a face to which the chips C are joined.

Each of the plurality of chips C is provided with through-silicon vias T. A protective film P is provided so as to cover the side faces of the plurality of chips C. The protective film P may also be removed. A molding resin layer M is provided so as to cover the protective film P.

Next, a method for producing the semiconductor memory device E2will be described with reference toFIGS.22to31.FIGS.22to31illustrate an example in which two chips C are mounted.

As illustrated inFIG.22, a support substrate SB is prepared. The support substrate SB is a substrate to be removed during the production process.

Next, as illustrated inFIG.23, a chip C is joined to the support substrate SB using an adhesive, for example. Through-silicon vias T are provided in the chip C.

Next, as illustrated inFIG.24, a protective film P is provided on the chip C joined to the support substrate SB, and the top portions of the through-silicon vias T are exposed so that a next chip C is joined thereto. The through-silicon vias T of the two chips C, which are joined, are joined. The two chips C are joined by bonding.

Next, as illustrated inFIG.25, a protective film P is provided on the upper chip C, and the top portions of the through-silicon vias T are exposed.

Next, as illustrated inFIG.26, a control chip CT is connected to the upper chip C. The control chip CT is joined to the through-silicon vias T of the upper chip C.

Next, as illustrated inFIG.27, a base substrate B is prepared. The base substrate B includes wire layers (not illustrated). The base substrate B has metal pads83on its upper face. The support substrate SB and the chips C illustrated inFIG.26are flipped upside down, and are bonded to the base substrate B. The bonding is performed with bonding portions81. The bonding portions81also serve as supports for holding the chips C on the base substrate B at predetermined intervals. The chips C and the base substrate B are electrically connected via electrodes82. The electrodes82are connected to the through-silicon vias T and the metal pads83.

Next, as illustrated inFIG.28, the support substrate SB is removed. Next, as illustrated inFIG.29, molding resin is provided so as to cover the chips C on the base substrate B so that a molding resin layer M is formed.

Next, as illustrated inFIG.30, metal balls BE are joined to the lower face of the base substrate B. The metal balls BE are joined to the metal pads83provided on the lower face of the base substrate B. Next, as illustrated inFIG.31, the structure is diced into individual pieces along cut lines L so that the semiconductor memory device E2is obtained. At this time, the protective film P may be partially exposed from the side faces of the molding resin layer M. Unlike in the semiconductor device E ofFIG.1, the protective film P is exposed around the end portions of the chip C that is most distant from the base substrate B. The protective film P may be removed before the molding resin layer M is formed. In such a case, the protective film P is not exposed from the molding resin layer M.

The semiconductor device E, E1, or E2of each of the aforementioned embodiments includes the base substrate B or Ba including wire layers, and the chips C or the chips C1, C2, C3, C4, C5, and C6provided on the base substrate B or Ba, and also includes the protective film P provided on the side faces of the chips C or the chips C1, C2, C3, C4, C5, and C6. In a CMP step for making the chips C or the chips C1, C2, C3, C4, C5, and C6, which have been obtained through dicing, thinner and forming junction electrodes, even when the processing pressure of CMP concentrates on the chips, local polishing does not proceed because the protective film P of a SiN film, for example, remains on each of the side faces of the chips C or the chips C1, C2, C3, C4, C5, and C6. Thus, it is possible to suppress a roll-off phenomenon in which the ends of the chips C or the chips C1, C2, C3, C4, C5, and C6become thin. This can improve the joining failures of the ends of the chips C or the chips C1, C2, C3, C4, C5, and C6.

The protective film P contains at least one of SiO2, SiN, SiC, and BN. The thickness of the protective film P on the side of the base substrate B or Ba differs from that on the side of the upper end of the chips C or the chips C1, C2, C3, C4, C5, and C6.

The method for producing the semiconductor device E or E1according to each of the aforementioned embodiments includes preparing the base substrate B or Ba including wire layers, joining the chips C or the chips C1, C2, C3, C4, C5, and C6including electrodes to the base substrate B or Ba, forming the protective film P on the chips C or the chips C1, C2, C3, C4, C5, and C6, and exposing the top portions of the electrodes in the chips C or the chips C1, C2, C3, C4, C5, and C6. In a CMP step for making the chips C or the chips C1, C2, C3, C4, C5, and C6, which have been obtained through dicing, thinner and forming junction electrodes, even when the processing pressure of CMP concentrates on the chips, local polishing does not proceed because the protective film P of a SiN film, for example, remains on each of the side faces of the chips C or the chips C1, C2, C3, C4, C5, and C6. Thus, it is possible to suppress a roll-off phenomenon in which the ends of the chips C or the chips C1, C2, C3, C4, C5, and C6become thin. This can improve the joining failures of the ends of the chips C or the chips C1, C2, C3, C4, C5, and C6.

The method for producing the semiconductor device E2according to the aforementioned embodiment includes preparing the support substrate SB, bonding the chips C including electrodes to the support substrate SB, forming the protective film P on the chips C, exposing the top portions of the electrodes in the chips C, joining the base substrate B including wire layers to the side of the chips C opposite to the side bonded to the support substrate SB, and removing the support substrate SB. In a CMP step for making the chips C, which have been obtained through dicing, thinner and forming junction electrodes, even when the processing pressure of CMP concentrates on the chips, local polishing does not proceed because the protective film P of a SiN film, for example, remains on each of the side faces of the chips C. Thus, it is possible to suppress a roll-off phenomenon in which the ends of the chips C become thin. This can improve the joining failures of the ends of the chips C.

In the production method of each of the aforementioned embodiments, it is possible to, after forming the protective film P on the chips C or the chips C1, C2, C3, C4, C5, C6, make the chips C or the chips C1, C2, C3, C4, C5, and C6thinner and expose the top portions of the electrodes in the chips C or the chips C1, C2, C3, C4, C5, and C6.

In the production method of each of the aforementioned embodiments, the protective film P can be formed to a thickness of 20 nm to 3000 nm. In the production method of each of the aforementioned embodiments, the protective film P contains at least one of SiN, SiC, and BN. The protective film P may also be a stacked film of at least one of SiN, SiC, and BN, and SiO2.

OTHER EMBODIMENTS

When the protective film P is a stacked film, a stacked structure of SiN and SiO2may be repeated more than once, for example. In such a case, the number of repeated stacked structures on each side face of each of the chips C1, C2, C3, C4, C5, and C6may be different.

In each of the semiconductor devices E and E1, the number of repeated stacked structures is the largest on each side face of the chip C1, and becomes sequentially smaller by one on each of the side faces of the chips C2to C6. In the semiconductor device E2, the number of repeated stacked structures is the largest on each side face of the chip that is most distant from the base substrate B, and becomes sequentially smaller by one on each of the side faces of the chips closer to the base substrate B.

InFIG.7, the oxide film C1bis formed on the side faces and the rear face of each chip C1and on the base substrate B. However, at this time, the oxide film C1bmay be formed only on the rear face of each chip C1, that is, on the silicon C1a. In such a case, since the oxide film C1bis not formed on the side faces of each chip C1or the base substrate B, the protective film P does not have the aforementioned repeated structures of stacked films, and is formed only of SiN, for example. However, more specifically, a plurality of SiN layers are formed.

InFIG.28, the support substrate SB is removed, but the support substrate SB need not be removed. In such a case, the support substrate SB on the upper face of the semiconductor device E2may be used as is. Alternatively, when the entire support substrate SB is buried in the molding resin layer M, cross-sections of the support substrate SB are exposed from the side faces of the molding resin layer M.

Although the present embodiment has been described with reference to specific examples, the present disclosure is not limited thereto. Such specific examples are, even when some design changes are appropriately made thereto by one of ordinary skill in the art, also included in the scope of the present disclosure as long as the resulting design includes the features of the present disclosure. The components, their arrangement, conditions, shapes, and the like of each of the aforementioned specific examples are not limited to those exemplarily illustrated above, and can be changed as appropriate. A combination of the components of each of the aforementioned specific examples can be changed as appropriate unless any technical contradiction occurs.