Patent ID: 12237395

DETAILED DESCRIPTION

To provide a better understanding of the present invention to those of ordinary skill in the art, several exemplary embodiments of the present invention will be detailed as follows, with reference to the accompanying drawings using numbered elements to elaborate the contents and effects to be achieved. The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute a part of this specification. Relative dimensions and proportions of parts of the drawings have been shown exaggerated or reduced in size, for the sake of clarity and convenience in the drawings. The same reference signs are generally used to refer to corresponding or similar features in modified and different embodiments. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention.

The high electron mobility transistor provided by the present invention may be depletion mode (normally-on) high electron mobility transistors or enhancement mode (normally-off) high electron mobility transistors. The high electron mobility transistors provided by the present invention may be used in power converters, low noise amplifiers, radio frequency (RF) or millimeter wave (MMW) and other technical fields.

The types and shapes of the gate structures, the drain structures, and the source structures of the high electron mobility transistors described in the embodiments of the present invention are only examples for the purpose of convenience of drawing and description, and are not used to limit the scope of the present invention. Moreover, in the following embodiments, high electron mobility transistors including metal-semiconductor gate structures are taken as examples to illustrate the principle of the present invention. It should be understood that the present invention may also be applied to high electron mobility transistors including metal gate structures.

FIG.1toFIG.4are schematic cross-sectional views illustrating a method for forming a high electron mobility transistor according to an embodiment of the present invention. Please refer toFIG.1. First, a substrate10is provided. A stack structure is formed on the substrate10. The stack structure may include, in a sequence from bottom to top, a buffer layer12, a channel layer14, a barrier layer16, a gate structure18, and a passivation layer20. According to an embodiment of the present invention, the gate structure18may be a metal-semiconductor gate structure that includes a semiconductor gate layer18aand a metal gate layer18b. The method for forming the stack structure may include performing a series of deposition processes to form the buffer layer12, the channel layer14, the barrier layer16, the semiconductor gate layer18aand the metal gate layer18bon the substrate10. Subsequently, a patterning process may be performed to etch and remove unnecessary portions of the semiconductor gate layer18aand the metal gate layer18bto form the gate structure18. After that, another deposition process may be performed to form the passivation layer20on the barrier layer16and the gate structure18, so that the stack shown inFIG.1may be obtained. According to an embodiment of the present invention, the deposition processes used to form the layers of the stack structure shown inFIG.1may include molecule beam epitaxy (MBE) process, hydride vapor phase deposition (HVPE) process, metal-organic chemical vapor deposition (MOCVD) process, chemical vapor deposition (CVD) process, atomic layer deposition (ALD) process, physical vapor deposition (PVD) process, molecular beam deposition (MBD) process, plasma-enhanced chemical vapor deposition (PECVD) process, but are not limited thereto.

The substrate10may be a silicon substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a gallium nitride (GaN) substrate, an aluminum nitride (AlN) substrate, or a substrate made of other suitable materials, but is not limited thereto. The buffer layer12, the channel layer14, and the barrier layer16may respectively include a single layer or a multilayer structure. The buffer layer12, the channel layer14, and the barrier layer16may respectively include a III-V compound semiconductor material, such as gallium nitride (GaN), aluminum gallium nitride (AlGaN), graded aluminum gallium nitride (graded AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), doped gallium nitride (doped GaN), aluminum nitride (AlN), or a combination thereof, but is not limited thereto. According to an embodiment of the present invention, the buffer layer12includes aluminum gallium nitride (AlGaN), the channel layer14includes allium nitride (GaN), and the barrier layer16includes aluminum gallium nitride (AlGaN). A two-dimensional electron gas (2 DEG) layer may be formed at the junction between the barrier layer16and the channel layer14and be utilized as a planar current channel of the high electron mobility transistor.

The gate structure18controls the conducting or cut-off of the two-dimensional electron gas layer. The semiconductor gate layer18aof the gate structure18may include an n-type doped III-V compound semiconductor material, an n-type doped II-VI compound semiconductor material, an undoped III-V compound semiconductor material, an undoped II-VI compound semiconductor material, a p-type doped III-V compound semiconductor material, or a p-type doped II-VI compound semiconductor material, but is not limited thereto. According to an embodiment of the present invention, the semiconductor gate layer18aof the gate structure18includes p-type gallium nitride (p-GaN) that includes dopants such as magnesium (Mg), iron (Fe), or other suitable p-type dopants. The metal gate layer18bof the gate structure18may include a metal material, such as gold (Au), tungsten (W), cobalt (Co), nickel (Ni), titanium (Ti), molybdenum (Mo), copper (Cu), aluminum (Al), tantalum (Ta), palladium (Pd), platinum (Pt), compounds (such as nitrides, silicides or oxides) of the above materials, a composite layer of the above materials, or an alloy of the above materials, but is not limited thereto. According to an embodiment of the present invention, the metal gate layer18bof the gate structure18includes titanium nitride (TiN). The metal-semiconductor interface between the semiconductor gate layer18aand the metal gate layer18bis preferably a Schottky contact which may enable a rectification function for the gate structure18.

The passivation layer20covers the stack structure and may serve as an isolation and passivation layer for the stack structure. The passivation layer20may include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (Al2O3), aluminum nitride (AlN), boron nitride (BN), zirconia (ZrO2), hafnium oxide (HfO2), lanthanum oxide (La2O3), lutetium oxide (Lu2O3), lanthanum oxide (LaLuO3), high-k dielectric materials, organic polymers such as polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), or a combination thereof, but is not limited thereto. According to an embodiment of the present invention, the passivation layer20includes silicon nitride (SiN).

Please refer toFIG.2. Subsequently, an etching process may be performed to etch the stack structure to form the openings OP1at two sides of the gate structure18and the opening OP2directly on the gate structure18. The openings OP1respectively extend through the passivation layer20and the barrier layer16to expose a portion of the channel layer14. The opening OP2extends through the passivation layer20directly on the gate structure18to expose a portion of the metal gate layer18b. After that, a series of deposition processes or suitable film forming processes may be performed to sequentially form a liner32, a metal layer34and a cap layer36on the passivation layer20of the stack structure and filling the openings OP1and OP2. As shown inFIG.2, the liner32conformally covers the surface of the passivation layer20and the sidewalls and bottom surfaces of the openings OP1and OP2. The portions of the liner32in the bottom portions of the openings OP1are in direct contact with the barrier layer16and the channel layer14. The portion of the liner32in the bottom portion of the opening OP2is in direct contact with the metal gate layer18bof the gate structure18. The liner32, the metal layer34and the cap layer36may respectively include a metal material, such as gold (Au), tungsten (W), cobalt (Co), nickel (Ni), titanium (Ti), molybdenum (Mo), copper (Cu), aluminum (Al), tantalum (Ta), palladium (Pd), platinum (Pt), compounds of the above materials, a composite layer of the above materials, or an alloy of the above materials, but is not limited thereto. The thicknesses of the liner32, the metal layer34, and the cap layer36may be adjusted according to device needs. According to an embodiment of the present invention, the thickness of the liner32may be between 10 and 200 angstroms, the thickness of the metal layer34may be between 1000 and 3000 angstroms, and the thickness of the cap layer36may be 250 and 350 angstroms, but is not limited thereto.

The materials of the liner32and the metal layer34are selected based on the material of the channel layer14, and are able to form an ohmic contact with the channel layer14after a thermal process (for example, after the anneal process P1shown inFIG.3). Furthermore, the metal layer34may include at least an additive additionally added to the metal material of the metal layer34to improve the quality of the ohmic contact and also improve the conductivity and reliability of the metal layer34. According to an embodiment of the present invention, for a channel layer14made of gallium nitride (GaN), the liner layer32may preferably include titanium (Ti) and the metal layer34may preferably include aluminum (Al) doped with at least an additive selected from silicon (Si), germanium (Ge), carbon (C), and copper (Cu). According to an embodiment of the present invention, the metal layer34may include AlSiCu, AlGeCu, and/or AlCCu, wherein the metal material34athat constructs the majority of the metal layer34is aluminum (Al), the first additive34bdoped in the metal material34amay include at least one of silicon (Si), germanium (Ge) and carbon (C), and the second additive34cdoped in the metal material34amay include copper (Cu). According to an embodiment of the present invention, a weight percentage of the first additive34b(such as Si, Ge, and/or C) in the metal layer34may be between 0% and 2%. A weight percentage of the second additive34c(such as Cu) in the metal layer34may be between 0% and 1%. According to an embodiment of the present invention, the weight percentage of the first additive34bmay be equal to or larger than the weight percentage of the second additive34c. The metal layer34may be formed by any suitable film forming process, such as electron beam evaporation process or sputtering process. In some embodiments, the metal layer34may be formed by using a target of the metal material34athat is already doped with the first additive34band the second additive34cin appropriate concentrations (such as an Al target that is doped with suitable amounts of Si, Ge and/or Ge, and Cu). In other embodiments, other suitable methods may be used to add the first additive34band the second additive34cinto the metal material34aof the metal layer34, such as multi-target sputtering, but is not limited thereto. The cap layer36may provide protection to the metal layer34and prevent the surface of the metal layer34from oxidation or reaction with other layers. According to an embodiment of the present invention, the cap layer36may include titanium nitride (TiN), but is not limited thereto.

Please refer toFIG.3. Subsequently, an anneal process P1is performed to react the material of the channel layer14with the material of the liner32, thereby forming an ohmic contact between the channel layer14and the metal layer34at the bottom portion of each of the openings OP1, and concurrently converting the liner32into a metal compound layer32′ by reacting the liner32with the first additive34bof the metal layer34. According to an embodiment of the present invention, the anneal process P1may be performed at a temperature between 450° C. and 900° C. and a process time between 5 and 60 minutes, but is not limited thereto. The metal compound layer32′ may include at least the material of the liner32and the first additive34bof the metal layer34.

Please refer toFIG.4. After the anneal process P1, a patterning process may be performed to remove the unnecessary portions of the cap layer36, the metal layer34, and the metal compound layer32′, thereby forming contact structures42corresponding to the openings OP1and a contact structure43corresponding to the opening OP2. The contact structures42(source/drain contacts) are located at two sides of the gate structure18and respectively extend through the passivation layer20and the barrier layer16to directly contact a portion of the channel layer14. The contact structure43(gate contact) is located on the gate structure18and extends through the passivation layer20directly on the gate structure18to directly contact a portion of the metal gate layer18bof the gate structure18.

As previously illustrated, when the channel layer14is made of gallium nitride (GaN), selecting the liner layer32including titanium (Ti) and the metal layer34including aluminum (Al) with at least an additive of silicon (Si), germanium (Ge), carbon (C), and/or copper (Cu) may produce an ohmic contact with improved quality and lower contact resistance between the contact structure42and the channel layer14. It is because that, during the anneal process P1the titanium (Ti) of the liner32may capture and react with the nitrogen (N) of the channel layer14to form titanium nitride (TiN) and therefore produce a plenty of nitrogen vacancies (N-vacancies) in the channel layer14. The low work function (3.7 eV) of titanium nitride (TiN) and the heavy n-type doping effect produced by the plenty of nitrogen vacancies in the channel layer14are both advantageous to form an ohmic contact with a lower contact resistance. Furthermore, during the anneal process P1the first additive34b(such as Si, Ge and/or C) of the metal layer34may diffuse toward the interface between the metal layer34and the liner32and react with the titanium (Ti) of the liner32, so that titanium aluminide (TiAl3) formed by reaction of the aluminum (Al) of the metal layer34and the titanium (Ti) of the liner32may be suppressed, and the high resistance problems caused by titanium aluminide (TiAl3) may be prevented. Additionally, the metal compound layer32′ (formed from the liner32and the first additive34b) may include titanium silicide (TiSi), titanium germanium (TiGe), and/or titanium carbide (TiC), which are also low work function materials and are beneficial for the formation of a low resistance ohmic contact. Benefiting from the above factors, the contact resistance of the contact structures42provided by the present invention may be reduced. It is noteworthy that the portion of the metal compound layer32′ at the bottom of the openings OP1may further include titanium nitride (TiN) formed by the reaction of the titanium of the liner layer32and the nitrogen of the channel layer14.

It is one feature of the present invention that by using a metal layer34made of AlSiCu, AlGeCu, and/or AlCCu to form the contact structures42and the contact structure43, the titanium aluminide (TiAl3) formed by reaction of the aluminum (Al) of the metal layer34and the titanium (Ti) of the liner32may be suppressed, and the high contact resistance problems caused by titanium aluminide (TiAl3) may be resolved. Furthermore, the metal compound layer32′ may serve as a diffusion barrier to prevent diffusion of the gallium (Ga) of the channel layer14into the metal layer34which may result in gallium vacancies (Ga-vacancies) in the gallium nitride (GaN) of the channel layer14. Overall, the present invention may effectively reduce the contact resistances of the contact structures42and the contact structure43and achieve a better contact quality.

The following description will detail the different embodiments of the present invention. To simplify the description, identical components in each of the following embodiments are marked with identical symbols. For making it easier to understand the differences between the embodiments, the following description will detail the dissimilarities among different embodiments and the identical features will not be redundantly described.

FIG.5toFIG.8are schematic cross-sectional views illustrating a method for forming a high electron mobility transistor according to another embodiment of the present invention. A difference between this embodiment and the embodiment shown inFIG.1toFIG.4is that the source/drain contacts and the gate contact of this embodiment are formed at different steps wherein the gate contact is formed after forming the source/drain contacts. In detail, as shown inFIG.5, after forming the stack structure on the substrate10, an etching process may be performed to etch the stack structure to form the openings OP1in the stack structure at two si des of the gate structure18while no opening is formed and expose any portion of the gate structure18. Following, a series of deposition processes or suitable film forming processes may be performed to sequentially form the liner32, the metal layer34and the cap layer36on the stack structure and filling the openings OP1. Subsequently, as shown inFIG.6, an anneal process P1is performed to react the material of the channel layer14with the material of the liner32, thereby forming an ohmic contact between the metal layer34and the channel layer14at the bottom portion of each of the openings OP1, and converting the liner32into a metal compound layer32′. After that, as shown inFIG.7, a patterning process may be performed to remove the unnecessary portions of the cap layer36, the metal layer34, and the metal compound layer32′, thereby forming contact structures42(source/drain contacts) respectively at two sides of the gate structure18and directly contacting the channel layer14. Afterward, as shown inFIG.8, a deposition may be performed to form another passivation layer22on the passivation layer20and covering the contact structures42. The passivation layer22may include a dielectric material that may be referred to the materials suitable for the passivation layer20. According to an embodiment of the present, the passivation layer22and the passivation layer20may include a same dielectric material, such as silicon nitride (SiN). An etching process may be performed to each the passivation layer22to form the openings OP3and OP4in the passivation layer22, wherein the openings OP3penetrate through the passivation layer22directly on the contact structures42and expose portions of the contact structures42, and the opening OP4penetrates through the passivation layer22and the passivation layer20directly on the gate structure18and exposes a portion of the metal gate layer18bof the gate structure18. Following, a deposition process or any suitable film forming process may be performed to form a metal layer (not shown) on the passivation layer22and filling the openings OP3and OP4, and a patterning process may be performed to remove the unnecessary portions of the metal layer thereby forming contact structures44on the contact structures42and in direct contact with the contact structures42and a contact structure46(gate contact) on the gate structure18and in direct contact with the metal gate layer18bof the gate structure18. The contact structures44and the contact structure46may include a metal material, such as gold (Au), tungsten (W), cobalt (Co), nickel (Ni), titanium (Ti), molybdenum (Mo), copper (Cu), aluminum (Al), tantalum (Ta), palladium (Pd), platinum (Pt), compounds of the above materials, a composite layer of the above materials, or an alloy of the above materials, but is not limited thereto.

FIG.9toFIG.12are schematic cross-sectional views illustrating a method for forming a high electron mobility transistor according to still another embodiment of the present invention. A difference between this embodiment and the embodiment shown inFIG.1toFIG.4is that the source/drain contacts and the gate contact of this embodiment are formed at different steps, wherein the gate contact is formed before forming the source/drain contacts. In detail, as shown inFIG.9, after forming the stack structure on the substrate10, an etching process may be performed to etch the passivation layer20of the stack structure to form an opening OP5that is directly on the gate structure18and exposing a portion of the metal gate layer18bof the gate structure18. Following, a deposition process or any suitable film forming process may be performed to form a metal layer (not shown) on the passivation layer20and filling the opening OP5, and a patterning process may be performed to remove the unnecessary portions of the metal layer thereby forming a contact structure46on the gate structure18and in in direct contact with the metal gate layer18bof the gate structure18. Subsequently, as shown inFIG.10, a deposition may be performed to form another passivation layer21on the passivation layer20and covering the contact structure46. The passivation layer21may include a dielectric material that may be referred to the materials suitable for the passivation layer20. According to an embodiment of the present, the passivation layer21and the passivation layer20may include a same dielectric material, such as silicon nitride (SiN). Following, an etching process may be performed to each the passivation layer21and the passivation layer20, thereby forming openings OP6at two sides of the gate structure18and the opening OP7directly on the contact structure46. The openings OP6respectively extend through the passivation layer21, the passivation layer20and the barrier layer16to expose a portion of the channel layer14. The opening OP7extends through the passivation layer21directly on the contact structure46and exposes a portion of the contact structure46. Subsequently, a series of deposition processes or suitable film forming processes may be performed to sequentially form the liner32, the metal layer34and the cap layer36on the passivation layer21and filling the openings OP6and OP7. Following, as shown inFIG.11, an anneal process P1is performed to react the material of the channel layer14with the material of the liner32, thereby forming an ohmic contact between the metal layer34and the channel layer14at the bottom portion of each of the openings OP6, and converting the liner32into a metal compound layer32′. Afterward, as shown inFIG.12, a patterning process may be performed to remove the unnecessary portions of the cap layer36, the metal layer34, and the metal compound layer32′, thereby forming contact structures42(source/drain contacts) respectively at two sides of the gate structure18and directly contacting the channel layer14and a contact structure48directly on the contact structure46.

In summary, the high electron mobility transistor provided by the present invention may achieve a lower source/drain contact resistance by forming the source/drain contact structure with a liner and a metal layer including at least a kind of additive. During the anneal process, the additive may diffuse to the interface between the metal layer and the liner and reduce the reaction of the metal layer and the liner, so that an ohmic contact with a lower resistance may be formed between the contact structure and the channel layer. Furthermore, the metal compound layer formed from reaction of the liner and the additive may serve as a diffusion barrier to prevent the gallium (Ga) of the channel layer from diffusing into the channel layer, and defects caused by the Ga-vacancies in the channel layer may be reduced.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.