Patent ID: 12255198

DETAILED DESCRIPTION

Some devices and/or systems, e.g., memory devices and/or memory systems, may include two or more stacked dies (also commonly referred to as “dice”). A device may provide one or more independent communication channels for each of the dies. For example, a memory device may include two or more dies with one or more memory arrays on each of the dies. To enable the various memory arrays to be used independently (e.g., to enable each of the memory arrays to store and retrieve data independent of the other memory arrays), the memory device may include one or more independent data channels for each of the memory arrays. The data channels may allow data to be written to and to be read from the memory arrays. Data channels may traverse, among other things, inter-layer connections, data pads, and dummy data pads. In the present disclosure the terms “data pad” and “dummy data pad” each refer to a node for electrical connection that is present on both a front side and a back side of a die. Data pads and dummy data pads may include upper metal-layer pads, silicon-bulk-side pads, and through-silicon vias.

Some embodiments of the present disclosure include a layout (e.g., an arrangement) of data pads and dummy data pads for a die that allow substantially identical copies of the die to be stacked while providing independent data channels for memory arrays on the dies. For example, a first die may include a first data pad in its top left corner and a first dummy data pad in its bottom right corner. The first data pad may be electrically coupled to a first circuit of the first die and the first dummy data pad may not be electrically coupled to the first circuit (in some embodiments, the first dummy data pad may be electrically isolated). A second die, which is a substantially identical copy of the first die, may include a second data pad in its top left corner and a second dummy data pad in its bottom right corner. The second data pad may be electrically coupled to a second circuit of the second die and the second dummy data pad may not be electrically coupled to the second circuit (in some embodiments, the second dummy data pad may be electrically isolated). The second die may be rotated substantially 180° around an axis normal to the first die and stacked above the first die such that the second dummy data pad of the second die is above the first data pad of the first die and the second data pad of the second die is above the first dummy data pad of the first die. A first inter-layer connection may electrically couple a first input/output of the stack of dies to the second dummy data pad of the second die and to the first data pad of the first die. A second inter-layer connection may electrically couple a second input/output of the stack of dies to the first dummy data pad of the first die and to the second data pad of the second die. Because the second dummy data pad is not electrically coupled to the second circuit (and/or is electrically isolated relative to the second die), the first input/output may provide a first independent data channel for the first circuit (e.g., of a first memory array) of the first die. Further, because the first dummy data pad is not electrically coupled to the first circuit (and/or is electrically isolated relative to the first die), the second input/output may provide a second independent data channel for the second circuit (e.g., of a second memory array) of the second die.

The example layout described above may be expanded to include several data pads and several corresponding dummy data pads allowing for several dies to be stacked and providing an independent data channel for each memory array of each of the several dies. In some embodiments, an inter-layer connection may be electrically coupled to multiple data pads of multiple dies. In such cases, addressing may be applied to individually access circuits (e.g., circuits of memory arrays) of the multiple dies. For example, four dies may be stacked in two different orientations (e.g., one of the orientations rotated substantially 180° relative to the other). Each of the four dies may include two data pads and two dummy data pads. Four inter-layer connections may be electrically coupled to the data pads of the four dies. For example, at a first die (e.g., a bottom die) the inter-layer connections may be electrically coupled to each of the two data pads and to the two dummy data pads. At a second die, above the first die, the inter-layer connections electrically coupled to the data pads of the first die may be electrically coupled to dummy data pads of the second die and the inter-layer connections electrically coupled to the dummy data pads of the first die may be electrically coupled to data pads of the second die. At a third die, above the second die, the inter-layer connections electrically coupled to the data pads of the second die may be electrically coupled to dummy data pads of the third die and the inter-layer connections electrically coupled to the dummy data pads of the second die may be electrically coupled to data pads of the third die. At a fourth die, above the third die, the inter-layer connections electrically coupled to the data pads of the third die may be electrically coupled to dummy data pads of the fourth die and the inter-layer connections electrically coupled to the dummy data pads of the third die may be electrically coupled to data pads of the fourth die. A device (e.g., an “accessing device”), such as a controller and/or a host, may be configured to provide inputs to and/or to receive outputs from one or more memory arrays of one or more of the four dies through unique inter-layer connections as part of a data channel for each of the dies. For example, the accessing device may use a first inter-layer connection electrically coupled to a data pad of the first die, a dummy data pad of the second die, a data pad of the third die, and a dummy data pad of the fourth die to provide inputs to and/or to receive outputs from a memory array of the first die. In addition, the accessing device may use a second inter-layer connection that is also electrically coupled to a data pad of the first die, a dummy data pad of the second die, a data pad of the third die, and a dummy data pad of the fourth die to provide inputs to and/or to receive outputs from a memory array of the third die.

As another example, a first die may include a first data pad in its top left corner, a first dummy data pad in its top right corner, a second dummy data pad in its bottom right corner, and a third dummy data pad in its bottom left corner. In this example, three additional die, each identical to the first, may be stacked above the first die, each rotated substantially 90° relative to the die beneath it. This may allow four identical die to be stacked while providing four independent data channels through four inter-layer connections. The example layout suitable for substantially 90° rotations may be expanded using more than one data pad and more than three dummy data pads per die to allow more than four dies to be stacked while providing individual data channels in similar fashion to what was described in the previous example.

Additionally or alternatively, a device may use additional data channels to provide data to all dies of a stack of dies. In the present disclosure, data channels to provide data to all dies of a stack are referred to as “common data channels.” Examples of common data channels include data channels for communicating test-mode signals and reset signals. Additionally or alternatively, power and ground may be provided through common data channels. Likewise, inter-layer connections configured to communicate common data channels may be referred to herein as “common inter-layer connections” and data pads intended to be electrically coupled to common inter-layer connections may be referred to as “common data pads.” A device may use several different categories of common data channels (e.g., for carrying different categories of signals) and dies of the device may include several corresponding categories of common data pads, e.g., a first category of common data pad configured for a first category of common data channel and a second common data pad configured for a second category of common data channel.

Some embodiments of the present disclosure may include a layout of categories of common data pads for a die that allow substantially identical copies of the die to be rotated relative to one another and stacked. For example, a die may include a first common data pad of a first category proximate to a top left corner of the die and a second common data pad of a second category proximate to the first common data pad. The die may further include a third common data pad of the first category proximate to a bottom right corner of the die and a fourth common data pad of the second category proximate to the third common data pad. The position of the first common data pad relative to the top left corner may be the reverse as the position of the third common data pad relative to the bottom right corner and the position of the second common data pad relative to the top left corner may be the reverse as the position of the fourth common data pad relative to the bottom right corner. The relative positions of the die may be such that if a substantially identical copy of the die is placed above the die, the first common data pad of the die will align with the third common data pad of the copy of the die and the second common data pad of the die will align with the fourth common data pad of the copy of the die.

Such a layout (i.e., a layout that allows for alignment of data pads and dummy data pads and/or the alignment of categories of common data pads) may allow inter-layer connections to be straight (e.g., vertical through the stack) and without any lateral-connection portions. Straight inter-layer connections without lateral-connection portions may decrease parasitic capacitance compared with other stacks of dies including lateral-connection portions. Further, a layout decreasing the number of, or not including, lateral-connection portions, may have other advantages when compared with layouts including lateral-connection portions including decreased complexity and/or decreased manufacturing time and/or cost.

Further, such a layout (i.e., a layout that allows for alignment of data pads and dummy data pads and/or of categories of common data pads) may allow multiple instances of similar or identical dies to be stacked. This may allow for producing a stack of dies more simply and/or economically.

A data pad may be configured for a particular data channel or common data channel based on which circuits of the die the data pad is electrically coupled to on the die. For example, a data pad electrically coupled to an input/output circuit of a memory array may be a data pad for a data channel. Another data pad electrically coupled to an address input circuit of a memory array may be a data pad for receiving address information.

On the other hand, a dummy data pad may be defined by its lack of electrical coupling to circuits on the die. For example, in some embodiments, dummy data pads of a die may be electrically isolated from everything on the die. Thus, an inter-layer connection may electrically couple to a dummy data pad of a first die and to a data pad of a second die without electrical signaling on the first die interfering with a signal carried to, or from, the data pad of the second die.

Although various embodiments are described herein with reference to memory devices, the disclosure is not so limited, and the embodiments may be generally applicable to microelectronic systems and/or semiconductor devices that may or may not include memory devices. Embodiments of the disclosure will now be explained with reference to the accompanying drawings.

FIG.1is a functional block diagram illustrating an example memory device100, in accordance with at least one embodiment of the disclosure. Memory device100may include, for example, a DRAM (dynamic random-access memory), a SRAM (static random-access memory), a SDRAM (synchronous dynamic random-access memory), a DDR SDRAM (double-data-rate SDRAM, such as a DDR4 SDRAM and the like), a SGRAM (synchronous graphics random access memory) or a three-dimensional (3D) DRAM. Memory device100, which may be integrated on a semiconductor chip, may include a memory array102.

In the embodiment ofFIG.1, memory array102is shown as including eight memory banks BANK0-7. More or fewer banks may be included in memory array102of other embodiments. Each memory bank includes a number of access lines (word lines WL), a number of data lines (bit lines BL and/BL), and a number of memory cells MC arranged at intersections of the number of word lines WL and the number of bit lines BL and/BL. The selection of a word line WL may be performed by a row decoder104and the selection of the bit lines BL and/BL may be performed by a column decoder106. In the embodiment ofFIG.1, row decoder104may include a respective row decoder for each memory bank BANK0-7, and column decoder106may include a respective column decoder for each memory bank BANK0-7.

Bit lines BL and/BL are coupled to a respective sense amplifier SAMP. Read data from bit line BL or/BL may be amplified by sense amplifier SAMP, and transferred to read/write amplifiers160over complementary local data lines (LIOT/B), a transfer gate (TG), and complementary main data lines (MIOT/B). Conversely, write data outputted from read/write amplifiers160may be transferred to sense amplifier SAMP over the complementary main data lines MIOT/B, transfer gate TG, and complementary local data lines LIOT/B, and written in the memory cell MC coupled to bit line BL or/BL.

Memory device100may be generally configured to be receive various inputs (e.g., from an external controller or host) via various terminals, such as address terminals110, command terminals112, clock terminals114, data terminals116, and data mask terminals118. Memory device100may include additional terminals such as a power supply terminal120and a power supply terminal122.

During a contemplated operation, one or more command signals COM, received via command terminals112, may be conveyed to a command decoder150via a command input circuit152. Command decoder150may include a circuit configured to generate various internal commands via decoding the one or more command signals COM. Examples of the internal commands include an active command ACT and a read/write signal R/W.

Further, one or more address signals ADD, received via address terminals110, may be conveyed to an address decoder130via an address input circuit132. Address decoder130may be configured to supply a row address XADD to row decoder104and a column address YADD to column decoder106. Although command input circuit152and address input circuit132are illustrated as separate circuits, in some embodiments, address signals and command signals may be received via a common circuit.

An active command ACT may include a pulse signal that is activated in response to a command signal COM indicating row access (e.g., an active command). In response to active signal ACT, row decoder104of a specified bank address may be activated. As a result, the word line WL specified by row address XADD may be selected and activated.

Read/write signal R/W may include a pulse signal that is activated in response to a command signal COM indicating column access (e.g., a read command or a write command). In response to read/write signal R/W, column decoder106may be activated, and bit line BL specified by the column address YADD may be selected.

In response to active command ACT, a read signal, a row address XADD, and a column address YADD, data may be read from the memory cell MC specified by row address XADD and column address YADD. The read data may be output via sense amplifier SAMP, transfer gate TG, read/write amplifiers160, an input/output circuit162, and data terminals116. Further, in response active command ACT, a write signal, a row address XADD, and a column address YADD, write data may be supplied to memory array102via data terminals116, input/output circuit162, read/write amplifiers160, transfer gate TG, and sense amplifier SAMP. The write data may be written to the memory cell MC specified by row address XADD and column address YADD.

Clock signals CK and/CK may be received via clock terminals114. A CLK Input circuit170may generate internal clock signals ICLK based on the clock signals CK and/CK. Internal clock signals ICLK may be conveyed to various components of memory device100, such as command decoder150and an internal clock generator172. Internal clock generator172may generate internal clock signals LCLK, which may be conveyed to input/output circuit162(e.g., for controlling the operation timing of input/output circuit162). Further, data mask terminals118may receive one or more data mask signals DM. When the data mask signal DM is activated, overwrite of corresponding data may be prohibited.

FIG.2Ais a functional block diagram illustrating an example layout200aof a die274in accordance with at least one embodiment of the disclosure. Layout200aincludes an array area264a, array area264b, and through-silicon via (TSV) and peripheral circuit area266close to a center line276of die274.

Additionally, layout200aincludes designations of areas of the die for specific channels (“channel areas”), e.g., Channel A (“ChA”), Channel B (“ChB”), Channel C (“ChC”), Channel D (“ChD”), Channel I (“ChI”), Channel J (“ChJ”), Channel K (“ChK”), and Channel L (“ChL”). Including multiple channels on a die may, among other things, increase the granularity with which memory cells can be accessed. Including multiple channels may improve random-access operations. Each of the channel areas may include a portion of an array area264aor array area264band a portion of TSV and peripheral circuit area266. As an example, ChA area278is illustrated inFIG.2A. The TSV and peripheral circuit area266of a channel area may be for servicing the memory in the memory array area of the channel area. For example, each channel area may include one “AW” region (or “AWord” region) that may include data pads for receiving address/command data (or a “command block”) and two “DW” regions (or “DWord” regions) that may include data pads for providing and/or receiving data (or a “data I/O block”).

FIG.2Bis a functional block diagram illustrating an example layout200bof pads of an example DW area of the die ofFIG.2Ain accordance with at least one embodiment of the disclosure. In particular, layout200billustrates an arrangement of power/ground pads268(which may be used to transfer power to dies), data pads270(which may be used to provide data to and/or receive data from dies and, more specifically, from memory arrays of dies), and clock/command pads272(which may be used to provide clock signals and/or command signals to dies). Each of the pads of a die may be electrically coupled to inter-layer connections that may couple the pads to other dies and/or to inputs/outputs of the dies. For example, in some embodiments, each of the pads may be, or may include, a TSV.

FIG.2Cis a functional block diagram illustrating an example layout200cof data pads, dummy data pads, and common data pads on an example die202in accordance with at least one embodiment of the disclosure. Layout200cmay allow for multiple instances of die202to be rotated relative to one another and to be stacked. A stack of instances of die202(e.g., with alternative dies rotated substantially 180° relative one another) may allow for alignment of data pads and dummy data pads and alignment of categories of common data pads which may allow for straight inter-layer connections, e.g., without lateral-connection portions.

Die202is illustrated inFIG.2without memory arrays and with eight data pads and sixteen common data pads for descriptive purposes. In particular, die202and the description of layout200crelative to die202is meant to describe principles and patterns that can be applied to data pads, dummy data pads, and common data pads of any die including any number of data pads, dummy data pads, and common data pads arranged anywhere on the die. For example, the TSV and peripheral circuit area266ofFIG.2Aas a whole may be arranged according to layout200c. Further, because the patterns and principles described with regard to layout200capply to TSV and peripheral circuit area266as a whole, the patterns and principles described with regard to layout200cmay apply within each DW region and/or AW region of TSV and peripheral circuit area266.

Die202may include one or more memory arrays (e.g., memory array102ofFIG.1; not illustrated inFIG.2C) arranged in one or more memory array areas (e.g., array area264aofFIG.2Aand array area264bofFIG.2A; not illustrated inFIG.2C). The data pads, dummy data pads, and common data pads of layout200cmay be arranged close to a center line of die202, e.g., close to center line276ofFIG.2Awith array areas on either side as illustrated inFIG.2Aor, the data pads, dummy data pads, and common data pads of layout200cmay be arranged close to edges of die202with one or more memory array areas between them.

The data pads of die202may provide for data channels for the memory arrays. For example, the various data pads of die202may be variously electrically coupled to various circuits (e.g., input/output circuits) of die202. For example, data pads may be for electrical coupling to circuits such as, for example, address input circuit132, command input circuit152, input/output circuit162, and/or CLK input circuit170. Additionally or alternatively, the data pads may be for electrical coupling to terminals such as address terminals110, command terminals112, clock terminals114, data terminals116, and data mask terminals118ofFIG.1. In some embodiments, data channels including data pads may be serialized and/or de-serialized to allow for a reduction in a number of data pads per die and/or to allow for a relaxed data rate.

Die202includes a first edge228, a second edge230, a third edge232, and a fourth edge234. An axis244and an axis246are illustrated on die202for descriptive purpose. Axis244may be between first edge228and third edge232e.g., axis244may be substantially the same distance from first edge228and third edge232. Axis246may be between second edge230and fourth edge234e.g., axis246may be substantially the same distance from second edge230and fourth edge234.

Die202includes data pad204a, data pad204b, data pad204c, and data pad204d(collectively referred to as “data pads204”) arranged proximate to first edge228. In the present disclosure, the term “proximate” may mean that a thing (e.g., a data pad, a dummy data pad, or a common data pad) is closer to one location than to the opposite of the location. For example, data pads204being proximate to first edge228means that data pads204are closer to first edge228than to third edge232. In other words, data pads204being proximate to first edge228may mean that data pads204are on the first edge228side of axis244. As an example, a data pad close to a center line of a die (e.g., a data pad close to center line276ofFIG.2A) may yet be proximate to a first edge because the data pad is closer to the first edge than to a third edge opposite the first edge. Data pads204are illustrated inFIG.2Cas including four data pads for descriptive purposes; any number of data pads204may be included in other embodiments. Data pads204may be variously electrically coupled to one or more respective circuits of die202. For example, each of data pads204may be electrically coupled to a respective circuit to allow an accessing device to electrical couple (e.g., through an inter-layer connection) to the one or more respective circuits of a memory array.

Die202includes dummy data pad208a, dummy data pad208b, dummy data pad208c, and dummy data pad208d(collectively referred to as “dummy data pads208”) arranged proximate to first edge228. Dummy data pads208may not be electrically coupled to one or more circuits of die202. In some embodiments, dummy data pads208may be electrically isolated from all circuits of die202. Dummy data pads208are illustrated inFIG.2Cas including four dummy data pads for descriptive purposes; any number of dummy data pads208may be included in other embodiments. Dummy data pads208may be arranged alternatingly with data pads204. For example, from left to right, data pads204and dummy data pads208include data pad204a, dummy data pad208a, data pad204b, dummy data pad208b, data pad204c, dummy data pad208c, data pad204d, and dummy data pad208d. As another example (not illustrated), groups of data pads204may be arranged alternatingly with groups of dummy data pads208, for example, from left to right, data pads204and dummy data pads208may include data pad204a, data pad204b, dummy data pad208a, dummy data pad208b, data pad204c, data pad204d, dummy data pad208c, and dummy data pad208d. Because of the alternating arrangement of data pads204and dummy data pads208, one of data pads204(e.g., data pad204a) may be proximate to an edge (e.g., fourth edge234) and one of dummy data pads208(e.g., dummy data pad208d) may be proximate to the opposite edge (e.g., second edge230).

Die202includes data pad206a, data pad206b, data pad206c, and data pad206d(collectively referred to as “data pads206”) arranged proximate to third edge232; data pads206are illustrated inFIG.2Cas including four data pads for descriptive purposes; any number of data pads206may be included in other embodiments. Data pads206may be variously electrically coupled to a respective circuit to allow an accessing device to electrical couple (e.g., through an inter-layer connection) to the one or more respective circuits of a memory array.

Die202includes dummy data pad210a, dummy data pad210b, dummy data pad210c, and dummy data pad210d(collectively referred to as “dummy data pads210”) arranged proximate to third edge232. Dummy data pads210may be not electrically coupled to one or more circuits of die202. In some embodiments, dummy data pads210may be electrically isolated from all circuits of die202. Dummy data pads210are illustrated inFIG.2Cas including four dummy data pads for descriptive purposes; any number of dummy data pads210may be included in other embodiments. Dummy data pads210may be arranged alternatingly with data pads206. For example, from left to right, data pads206and dummy data pads210include data pad206d, dummy data pad210d, data pad206c, dummy data pad210c, data pad206b, dummy data pad210b, data pad206a, and dummy data pad210a. As another example (not illustrated), groups of data pads206may be arranged alternatingly with groups of dummy data pads210, for example, from left to right, data pad206d, data pad206c, dummy data pad210d, dummy data pad210c, data pad206b, data pad206a, dummy data pad210b, and dummy data pad210a. Because of the alternating arrangement of data pads206and dummy data pads210, one of data pads206(e.g., data pad206d) may be proximate to an edge (e.g., fourth edge234) and one of dummy data pads210(e.g., dummy data pad210a) may be proximate to the opposite edge (e.g., second edge230).

In some embodiments, the arrangement of data pads204and dummy data pads208may be symmetrical to the arrangement of data pads206and dummy data pads210about axis244. For example, each of data pads204may be substantially the same distance from first edge228as a corresponding one of data pads206is from third edge232. Likewise, each of dummy data pads208may be substantially the same distance from first edge228as a corresponding one of dummy data pads210is from third edge232. In some embodiments, all of data pads204may be substantially the same distance from first edge228and all of data pads206may be substantially the same distance from third edge232. In other embodiments, one or more of data pads204may be a first distance from first edge228and others of data pads204may be a second distance from first edge228. In such embodiments, a corresponding one or more of data pads206may be substantially the first distance from third edge232and corresponding others of data pads206may be substantially the second distance from third edge232. Additionally, each of data pads204may be substantially the same distance from fourth edge234as a corresponding one of data pads206is from fourth edge234. For example, data pad204amay be the substantially same distance from fourth edge234as data pad206dis from fourth edge234. Likewise, each of dummy data pads208may be substantially the same distance from fourth edge234as a corresponding one of dummy data pads210. For example, dummy data pad208amay be substantially the same distance from fourth edge234as dummy data pad210dis from fourth edge234.

Additionally or alternatively, in some embodiments, the arrangement of data pads204relative to a top left corner (e.g., where first edge228meets fourth edge234) may be the reverse of the arrangement of dummy data pads210relative to a bottom right corner (e.g., where second edge230meets third edge232). For example, data pad204amay be distance236from first edge228and distance240from the fourth edge234and dummy data pad210amay be distance238(which may be substantially the same as distance236) from third edge232and the second distance242(which may be substantially the same as distance240) from second edge230.

Similarly, the arrangement of dummy data pads208relative to a top left corner may be the reverse of the arrangement of data pads206relative to a bottom right corner. For example, dummy data pad208amay be substantially the same distance from first edge228as data pad206ais from third edge232and dummy data pad208amay be substantially the same distance from fourth edge234as data pad206ais from second edge230.

In some embodiments, all of data pads204may be substantially the same distance from first edge228. In such embodiments, all of dummy data pads208may be substantially the same distance from third edge232. In other embodiments, one or more of data pads204may be a first distance from first edge228and others of data pads204may be a second distance from first edge228. In such embodiments, a corresponding one or more of dummy data pads208may be the first distance from third edge232and corresponding others of dummy data pads208may be the second distance from third edge232.

Such an arrangement of data pads204, data pads206, dummy data pads208, and dummy data pads210may allow for data pads of a first die to be aligned with dummy data pads of a second die when substantially identical copies of die202are rotated and stacked. For example, data pads204, dummy data pads208, data pads206, and dummy data pads210may be arranged such that if die202were rotated substantially 180° around an axis between first edge228, second edge230, third edge232, and fourth edge234, data pads204would be in positions formerly occupied by the dummy data pads210, dummy data pads208would be in positions formerly occupied by the data pads206, the data pads206would be in positions formerly occupied by the dummy data pads208, and dummy data pads210would be in positions formerly occupied by the data pads204.

Die202includes data pads212-218including: data pad212aand data pad212bwhich may be common data pads of a first category, data pad214aand data pad214bwhich may be common data pads of a second category, data pad216aand data pad216bwhich may be common data pads of a third category, and data pad218aand data pad218bwhich may be common data pads of a fourth category. Data pads212-218include four categories of common data pads for descriptive purposes. Any number of common data pads and any number of categories of common data pads may be included in other embodiments. Data pads212a,214a,216a, and218amay be proximate to first edge228and data pads212b,214b,216b, and218bmay be proximate to third edge232. In contrast to data pads204and data pads206, data pads212-218may be common data pads for common data channels.

Die202includes data pads220-226including: data pad220aand data pad220bwhich may be common data pads of a first category, data pad222aand data pad222bwhich may be common data pads of a second category, data pad224aand data pad224bwhich may be common data pads of a third category, and data pad226aand data pad226bwhich may be common data pads of a fourth category. Data pads220-226include four categories of common data pads for descriptive purposes. Any number of common data pads and any number of categories of common data pads may be included in other embodiments. Data pads220a,222a,224a, and226amay be proximate to first edge228and data pads220b,222b,224b, and226bmay be proximate to third edge232. In contrast to data pads204and data pads206, data pads220-226may be common data pads for common data channels.

In some embodiments, the arrangement of data pads212a,214a,216a, and218amay be symmetrical to the arrangement of data pads220b,222b,224b, and226babout axis244. For example, each of data pads212a,214a,216a, and218amay be substantially the same distance from first edge228as a corresponding one of data pads220b,222b,224b, and226bis from third edge232. In some embodiments, all of data pads212a,214a,216a, and218amay be substantially the same distance from first edge228and all of data pads220b,222b,224b, and226bmay be substantially the same distance from third edge232. In other embodiments, one or more of data pads212a,214a,216a, and218amay be a first distance from first edge228and others of data pads212a,214a,216a, and218amay be a second distance from first edge228. In such embodiments, a corresponding one or more of data pads220b,222b,224b, and226bmay be substantially the first distance from third edge232and corresponding others of data pads220b,222b,224b, and226bmay be substantially the second distance from third edge232. Additionally, each of data pads212a,214a,216a, and218amay be substantially the same distance from fourth edge234as a corresponding one of data pads220b,222b,224b, and226bis from fourth edge234. For example, data pad212amay be substantially the same distance from fourth edge234as data pad220bis from fourth edge234. Further, each of data pads212a,214a,216a, and218amay be substantially the same distance from axis246as a corresponding one of data pads220b,222b,224b, and226bis from axis246. For example, data pad218amay be substantially the same distance from axis246as data pad226bis from axis246.

In some embodiments, according to layout200c, the arrangement of data pads212a,214a,216a, and218amay be symmetrical to the arrangement of data pads220a,222a,224a, and226aabout axis246. For example, each of data pads212a,214a,216a, and218amay be substantially the same distance from first edge228as a corresponding one of data pads220a,222a,224a, and226ais from first edge228. In some embodiments, all of data pads212a,214a,216a, and218aand data pads220a,222a,224a, and226amay be substantially the same distance from first edge228. In other embodiments, one or more of data pads212a,214a,216a, and218amay be a first distance from first edge228and others of data pads212a,214a,216a, and218amay be a second distance from first edge228. In such embodiments, a corresponding one or more of data pads220a,222a,224a, and226amay be substantially the first distance from first edge228and corresponding others of data pads220a,222a,224a, and226amay be substantially the second distance from first edge228. Additionally, each of data pads212a,214a,216a, and218amay be substantially the same distance from fourth edge234as a corresponding one of data pads220a,222a,224a, and226ais from second edge230. For example, data pad212amay be substantially the same distance from fourth edge234as data pad220ais from second edge230. Further, each of data pads212a,214a,216a, and218amay be substantially the same distance from axis246as a corresponding one of data pads220a,222a,224a, and226ais from axis246. For example, data pad218amay be substantially the same distance from axis246as data pad226ais from axis246.

In some embodiments, the arrangement of categories of data pads212a,214a,216a, and218arelative to a top left corner may be the reverse of the arrangement of the categories of data pads212b,214b,216b, and218brelative to a bottom right corner. For example, data pad212a(of the first category) may be distance248from first edge228and data pad212b(of the first category) may be distance250(which may be substantially the same as distance248) from third edge232and data pad212amay be distance252from fourth edge234and data pad212bmay be distance254(which may be substantially the same as distance252) from third edge232. Likewise, data pad214a(of the second category) may be substantially the same distance from first edge228as data pad214b(of the second category) is from third edge232and data pad214amay be substantially the same distance from fourth edge234as data pad214bis from second edge230. Further, data pad218a(of a fourth category) may be distance256from first edge228and data pad218bmay be distance258(which may be substantially the same as distance256) from third edge232and data pad218amay be distance260from axis246and data pad218bmay be distance262(which may be substantially the same as distance260) from axis246.

In some embodiments, all of data pads212a,214a,216a, and218amay be substantially the same distance from first edge228. In such embodiments, all of data pads212b,214b,216b, and218bmay be substantially the same distance from third edge232. In other embodiments, one or more of data pads212a,214a,216a, and218amay be a first distance from first edge228and others of data pads212a,214a,216a, and218amay be a second distance from first edge228. In such embodiments, a corresponding one or more of data pads212b,214b,216b, and218bmay be substantially the first distance from third edge232and corresponding others of data pads212b,214b,216b, and218bmay be substantially the second distance from third edge232.

Such an arrangement of data pads212-218may allow for common data pads of the same category to be aligned when substantially identical copies of die202are rotated and stacked.

RelatingFIG.2AtoFIG.2C, according to the principles and patterns of layout200c, the layout of data pads of a DW0region of ChA ofFIG.2Arelative to a top left corner of die274ofFIG.2Amay be the reverse of the layout of dummy data pads of a DW1region of ChL relative to a bottom right corner of die274. The result of this layout of data pads and dummy data pads is that when a copy of die274is rotated and stacked above die274, the data pads of DW0of ChA of die274align with the dummy data pads of DW1of ChL of the copy of die274. Further, according to the principles and patterns of layout200c, the dummy data pads of DW0of ChA of die274will align with the data pads of DW1of ChL of the copy of die274. The same holds true for DW1of ChA and DW0of ChL, DW0of ChB and DW1of ChK, etc.

In some embodiments, the layout of data pads and dummy data pads of each DW0may correspond to the layout of dummy data pads of each DW1and the layout of dummy data pads of each DW0may correspond to the layout of data pads of each DW1. Thus, the layout of data pads and dummy data pads within each DW may follow the principles and patterns of layout200crelative to the DW. For example, each DW may be viewed as a die202and may follow the follow the principles and patterns of layout200c. Similarly, the layout of data pads and dummy data pads within each AW may follow the principles and patterns of layout200crelative to the AW.

Similarly, according to the principles and patterns of layout200c, the layout of categories of common data pads of a DW0region of ChA ofFIG.2Arelative to a top left corner of die274ofFIG.2Amay be the same of the layout of categories of common data pads of a DW1region of ChL relative to a bottom right corner of die274. The result of this layout of categories of common data pads is that when a copy of die274is rotated and stacked above die274, the categories of common data pads of DW0of ChA of die274align with the same categories of common data pads of DW1of ChL of the copy of die274. The same holds true for DW1of ChA and DW0of ChL, DW0of ChB and DW1of ChK, etc.

In some embodiments, the layout of categories of common data pads of each DW0may correspond to the layout of categories of common data pads of each DW1. Thus, the layout of categories of common data pads within each DW may follow the principles and patterns of layout200crelative to the DW. For example, each DW may be viewed as a die202and may follow the follow the principles and patterns of layout200c. Similarly, the layout of categories of common data pads within each AW may follow the principles and patterns of layout200crelative to the AW.

FIG.3is a functional block diagram illustrating an example stack of dies300in accordance with at least one embodiment of the disclosure. For example, stack of dies300may be referred to as a “memory device” or a “memory system.” Each die of stack of dies300may be an example of die202ofFIG.2C. Stack of dies300includes three instances of die202rotated relative to one another and stacked. Three dies are illustrated for descriptive purposes. Any number of dies may be included in other embodiments. Stack of dies300(with alternative dies rotated 180° relative one another) may allow for data pads of certain dies to align with dummy data pads of alternating dies and/or for alignment of categories of common data pads which may allow for straight inter-layer connections e.g., without lateral-connection portions.

Stack of dies300includes die302(e.g., a bottom die), die304above die302, and die306above die304. Each die of stack of dies300may be substantially identical to each of the others of stack of dies300. Each die of the stack of dies300may be rotated substantially 180° around an axis normal to the bottom die relative to a respective die immediately beneath it. For example, die304may be rotated substantially 180° relative to die302and die306may be rotated substantially 180° relative to die304.

Each die of stack of dies300may include a number of data pads308, each electrically coupled to a respective circuit (not illustrated) of a respective die on which data pads308are located. Data pads308may be examples of data pads204and data pads206ofFIG.2C.

Each die of stack of dies300may also include a number of dummy data pads310each not electrically coupled to a circuit of the respective die on which dummy data pads310are located. In some embodiments, dummy data pads310may be electrically isolated with respect to the die on which the dummy data pads are located. For example, dummy data pads310on die302may be electrically isolated with respect to die302. The number of dummy data pads310may be arranged relative to the number of data pads308such that each of the number of dummy data pads310of each die of the stack of dies300may align with a respective data pad of the number of data pads308. Dummy data pads310may be examples of dummy data pads208and dummy data pads210ofFIG.2C.

For example, die302may include one or more first data pads proximate to a top left corner of the die, one or more first dummy data pads proximate to the top left corner, one or more second data pads proximate to a bottom right corner of the die, and one or more second dummy data pads proximate to the bottom right corner. First positions of the first data pads relative to the top left corner may correspond to second positions of the second dummy data pads relative to the bottom right corner and third positions of the first dummy data pads relative to the top left corner may correspond to fourth positions of the second data pads relative to the bottom right corner.

Because data pads308of a die of stack of dies300align with dummy data pads310of adjacent dies of stack of dies300, straight inter-layer connections may electrically couple dummy data pads310and data pads308of adjacent dies of stack of dies300. For example, inter-layer connection316may electrically couple a dummy data pad310of die302to a data pad308of die304and to a dummy data pad310of die306.

Data pads and inter-layer connections may be implemented such that each die of stack of dies300is associated with one or more inter-layer connections to provide one or more independent data channel for each die of stack of dies300. For example, inter-layer connections may electrically couple all of data pads308of die302with all of data pads308of die306. An accessing device may be configured to access die302through certain inter-layer connections and to access die306through other inter-layer connections.

Additionally or alternatively, each die of stack of dies300may include data pads312. Data pads312may be common data pads of various categories. Data pads312may be arranged such that each of data pads312of each die of stack of dies300aligns with a respective one of the data pads312of the respective die immediately beneath the die. For example, each of data pads312of die302align with each of data pads312of die304which also align with each of data pads312of die306.

The arrangement of categories of data pads312may be such that each of data pads312of a first category of each die of stack of dies300aligns with a respective one of the data pads312of the first category of the respective die immediately beneath the die. Further, each of data pads312of a second category of each die of stack of dies300aligns with a respective one of the number of data pads312of the second category of the respective die immediately beneath the die. For example, of data pads312of each die of stack of dies300, a top-left-most data pad may be of a first category. Further, of data pads312of each die of stack of dies300, a second-to-left-most data pad may be of a second category. Thus, inter-layer connection318may electrically couple to data pads312of a first category of all dies of stack of dies300and another inter-layer connection (not illustrated) may electrically couple to all data pads312of a second category.

FIG.4is a functional block diagram illustrating an example layout400of data pads and dummy data pads on a die402in accordance with at least one embodiment of the disclosure. Layout400may allow for multiple instances of die402to be rotated relative to one another and to be stacked. A stack of instances of die402(with alternative dies rotated 90° relative one another) may allow for alignment of data pads and dummy data pads and/or alignment of categories of common data pads which may allow for straight inter-layer connections e.g., without lateral-connection portions.

Die402may include one or more memory arrays (e.g., memory array102ofFIG.1; not illustrated inFIG.4). The data pads of die402may provide for data channels for the memory arrays. For example, the data pads may be electrically coupled to various inputs and/or outputs of the memory arrays.

Die402includes a first edge410, a second edge412, a third edge414, and a fourth edge416.

Die402includes a number of data pads404each of which may be electrically coupled to a respective circuit of die402. Data pads404may be arranged proximate to first edge410. InFIG.4, seven data pads404are illustrated for descriptive purposes. Other numbers of data pads404may be included in other embodiments.

Die402includes dummy data pads406not electrically coupled to a circuit of die402. In some embodiments, dummy data pads406may be electrically isolated. Dummy data pads406includes a first number of dummy data pads406arranged proximate to second edge412, a second number of dummy data pads406arranged proximate to third edge414, and a third number of dummy data pads406arranged proximate to fourth edge416. InFIG.4, twenty-one dummy data pads406are illustrated for descriptive purposes. Other numbers of dummy data pads406may be included in other embodiments.

The arrangement of the dummy data pads406relative to each of second edge412, third edge414, and fourth edge416may be symmetrical to the arrangement of data pads404relative to first edge410. For example, a first data pad may be a first distance from first edge410and a second distance from fourth edge416. A corresponding dummy data pad may be substantially the first distance from second edge412and substantially the second distance from first edge410. Another corresponding dummy data pad may be substantially the first distance from third edge414and substantially the second distance from second edge412. And another corresponding dummy data pad may be substantially the first distance from fourth edge416and substantially the second distance from third edge414.

Such an arrangement of data pads404and dummy data pads406may allow for data pads of a first die to be aligned with dummy data pads of a second die, a third die, and a fourth die when substantially identical copies of die402are rotated and stacked.

Die402further includes data pads408. Data pads408may be common data pads, e.g., of different categories. For example, of data pads408proximate to first edge410, the data pad on left may be of a first category and the data pad on the right may be of a second category. Further, of data pads408proximate to second edge412, the top data pad may be of the first category and the bottom data pad may be of the second category. Further, of data pads408proximate to third edge414, the data on the right may be of the first category and the data pad on the left may be of the second category. Further, of data pads408proximate to fourth edge416, the bottom data pad may be of the first category and the top data pad may be of the second category.

Such an arrangement of data pads408may allow for the same categories of data pads408to be aligned when multiple substantially identical copies of die402are rotated and stacked.

FIG.5is a functional block diagram illustrating an example stack of dies500in accordance with at least one embodiment of the disclosure. For example, stack of dies500may be referred to as a “memory device” or a “memory system.” Each die of stack of dies500may be an example of die402ofFIG.4. Stack of dies500includes five instances of die402rotated relative to one another and stacked. Five dies are illustrated for descriptive purposes. Any number of dies may be included in other embodiments. Stack of dies500(with alternative dies rotated 90° relative one another) may allow for data pads of certain dies to align with dummy data pads of other dies and/or for alignment of categories of common data pads which may allow for straight inter-layer connections e.g., without lateral-connection portions.

Stack of dies500includes a die502, a die504, a die506, a die508, and a die510. Each die of stack of dies500may be substantially identical to each of the other dies of stack of dies500. Each die of the stack of dies500may be rotated substantially 90° around an axis normal to the bottom die relative to a respective die immediately beneath the die. For example, die504may be rotated substantially 90° relative to die502and die506may be rotated substantially 90° relative to die504.

Each die of stack of dies500may include a number of data pads512each of which may be electrically coupled to a respective circuit of the respective die on which data pads512are located. Data pads512may be examples of data pads404ofFIG.4.

Each die of stack of dies500may also include a number of dummy data pads514not electrically coupled to a circuit of the die on which dummy data pads514are located. The number of dummy data pads514may be arranged relative to the number of data pads512such that each of the number of dummy data pads514of each die of the stack of dies500may align with a respective data pad of the number of data pads512. Dummy data pads514may be examples of dummy data pads406FIG.4.

For example, die502may include one or more first data pads proximate to a first edge, one or more first dummy data pads proximate to a second edge, one or more second dummy data pads proximate to a third edge, and one or more third dummy data pads proximate to a fourth edge. First positions of the first data pads relative to the first edge may correspond to: second positions of the first dummy data pads relative to the second edge, third positions of the second dummy data pads relative to the third edge, and fourth positions of the third dummy data pads relative to the fourth edge.

Because data pads512of a die of stack of dies500align with dummy data pads514of at least some other dies of stack of dies500, straight inter-layer connections may electrically couple dummy data pads514and data pads512. For example, inter-layer connection528may electrically couple a dummy data pad of die510, a data pad of die508, a dummy data pad of die506, a dummy data pad of die504, and a dummy data pad of die502.

Data pads and inter-layer connections may be implemented such that each die of stack of dies500is associated with a one or more inter-layer connections to provide one or more independent data channels for each die of stack of dies500. For example, inter-layer connections may electrically couple all of data pads512of die502with all of data pads512of die510. An accessing device may be configured to access die502through certain inter-layer connections and to access die510through other inter-layer connections. For example, all of inter-layer connection518, inter-layer connection520, and inter-layer connection526may electrically couple to data pads of die502and die510. An accessing device may determine to access a memory array of die502through inter-layer connection518and to access a memory array of die510through inter-layer connection520.

Additionally or alternatively, each die of stack of dies500may include data pads516. Data pads516may be common data pads of various categories. Data pads516may be arranged such that each of data pads516of each die of stack of dies500aligns with a respective one of the data pads516of the respective die immediately beneath the die. For example, each of data pads516of die502align with each of data pads516of die504, which also align with each of data pads516of die506, which also align with each of data pads516of die508, which also align with each of data pads516of die510.

The arrangement of categories of data pads516may be such that each of data pads516of a first category of each die of stack of dies500aligns with a respective one of the data pads516of the first category of the respective die immediately beneath the die. Further, each of data pads516of a second category of each die of stack of dies500aligns with a respective one of the number of data pads516of the second category of the respective die immediately beneath the die. For example, of data pads516of each die of stack of dies500: of data pads516proximate to a first edge, a left data pad may be of a first category and a right data pad may be of a second category, of data pads proximate to a second edge, the top data pad may be of the first category and the bottom data pad may be of the second category, of data pads408proximate to a third edge, the right data pad may be of the first category and the left data pad may be of the second category, and of data pads408proximate to a fourth edge, the bottom data pad may be of the first category and the top data pad may be of the second category. Thus, inter-layer connection522may electrically couple to data pads516of a first category of all dies of stack of dies500and inter-layer connection524may electrically couple to all data pads516of a second category.

FIG.6is a flowchart illustrating an example method600in accordance with at least one embodiment of the disclosure. Method600may be arranged in accordance with at least one embodiment described in the disclosure. Method600may be performed, in some embodiments, in forming at least a portion of memory device100ofFIG.1, stack of dies300ofFIG.3, stack of dies500ofFIG.5, memory system700ofFIG.7, electronic system800ofFIG.8, or another device or system. Although illustrated as discrete blocks, various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

At block602, a number of dies may be obtained. Each die of the number of dies may be substantially identical to each of the other dies of the number of dies. Each of the dies may include a number of data pads electrically coupled to a respective circuit of the die and a number of dummy data pads not electrically coupled to a circuit of the die. Die202(including data pads204, data pads206, dummy data pads208, and dummy data pads210) ofFIG.2Cmay be a first example of a die of the number of dies obtained at block602. Die402(including data pads404and dummy data pads406) ofFIG.4may be a second example of a die of the number of dies obtained at block602.

At block604, the number of dies may be rotated and stacked, one above another, such that data pads of one of the number of dies align with dummy data pads of dies above and beneath the one of the number of dies. Stack of dies300ofFIG.3may be a first example of how the dies are rotated and stacked at block604. For example, rotating and stacking each of the number of dies may include rotating each of the stack of dies (except a bottom die) by substantially 180° relative to a die beneath it. Stack of dies500ofFIG.5may be a second example of how the dies are rotated and stacked at block604. For example, rotating and stacking each of the number of dies may include rotating each of the stack of dies (except a bottom die) by substantially 90° relative to a die beneath it.

At block606, data pads of some of the number of dies may be electrically coupled with dummy data pads of others of the number of dies. Further, the dummy data pads of the others of the number of dies may be electrically coupled with data pads of the some of the number of dies. Inter-layer connection314, inter-layer connection316, and inter-layer connection318ofFIG.3may be first examples of the inter-layer connections electrically coupling data pads of some of the number of dies and dummy data pads of others of the numbers of dies at block606. Inter-layer connection518, inter-layer connection520, inter-layer connection522, inter-layer connection524, inter-layer connection526, and inter-layer connection528ofFIG.5may be second examples of the inter-layer connections electrically coupling data pads of some of the number of dies and dummy data pads of others of the numbers of dies at block606.

Modifications, additions, or omissions may be made to method600without departing from the scope of the disclosure. For example, the operations of method600may be implemented in differing order. Furthermore, the outlined operations and actions are only provided as examples, and some of the operations and actions may be optional, combined into fewer operations and actions, or expanded into additional operations and actions without detracting from the essence of the disclosed embodiment.

FIG.7is a simplified block diagram illustrating an example memory system700implemented in accordance with at least one embodiment of the disclosure. Memory system700, which may include, for example, a semiconductor device, includes a number of memory devices702and a controller704. Controller704may be operatively coupled with memory devices702so as to convey command/address signals (e.g., command/address signals received by command terminals112and/or address terminals110ofFIG.1) to memory devices702.

At least one of memory devices702(e.g., memory device100ofFIG.1) and/or controller704of memory system700may include one or more dies arranged according to layout200cofFIG.2Cor layout400ofFIG.4, according to one or more embodiments disclosed herein.

An electronic system is also disclosed. According to various embodiments, the electronic system may include a memory device including a number of memory dies, each memory die having an array of memory cells. Each memory cell may include an access transistor and a storage element operably coupled with the access transistor.

FIG.8is a simplified block diagram illustrating an electronic system800implemented in accordance with at least one embodiment of the disclosure. Electronic system800includes at least one input device802, which may include, for example, a keyboard, a mouse, or a touch screen. Electronic system800further includes at least one output device804, such as a monitor, a touch screen, or a speaker. Input device802and output device804are not necessarily separable from one another. Electronic system800further includes a storage device806. Input device802, output device804, and storage device806may be coupled to a processor808. Electronic system800further includes a memory device810coupled to processor808. Memory device810may include at least a portion of memory system700ofFIG.7. Electronic system800may include, for example, a computing, processing, industrial, or consumer product. For example, without limitation, electronic system800may include a personal computer or computer hardware component, a server or other networking hardware component, a database engine, an intrusion prevention system, a handheld device, a tablet computer, an electronic notebook, a camera, a phone, a music player, a wireless device, a display, a chip set, a game, a vehicle, or other known systems.

Various embodiments may include a die including: a number of circuits, a first edge, a second edge perpendicular to the first edge, a third edge opposite the first edge, and a fourth edge opposite the second edge. The die may also include a first number of data pads variously electrically coupled to the number of circuits. The first number of data pads may be arranged proximate to the first edge. The die may also include a first number of dummy data pads, not electrically coupled to the number of circuits, alternatingly arranged with the first number of data pads, proximate to the first edge, with a first data pad of the first number of data pads proximate to the fourth edge and a first dummy data pad of the first number of dummy data pads proximate to the second edge. The die may also include a second number of data pads variously electrically coupled to the number of circuits. The second number of data pads may be arranged proximate to the third edge. The die may also include a second number of dummy data pads, not electrically coupled to the number of circuits, alternatingly arranged with the second number of data pads, proximate to the third edge, with a second data pad of the second number of data pads proximate to the fourth edge and a second dummy data pad of the second number of dummy data pads proximate to the second edge.

Various embodiments may include a device including dies comprising a bottom die and a number of dies arranged above the bottom die. Each of the dies may be substantially identical to each of the other dies. Each of the number of dies may be rotated substantially 180° around an axis normal to the bottom die relative to a respective die immediately beneath the die. Each of the dies may include a number of circuits, a number of data pads variously electrically coupled to the number of circuits, and a number of dummy data pads not electrically coupled to the number of circuits. The number of dummy data pads may be arranged relative to the number of data pads such that each of the number of dummy data pads of each of the number of dies aligns with a respective data pad of the number of data pads.

Various embodiments may include a device including dies comprising a bottom die and a number of dies arranged above the bottom die. Each of the dies may be substantially identical to each of the other dies. Each of the number of dies may be rotated substantially 90° around an axis normal to the bottom die relative to a respective die immediately beneath the die. Each of the dies may include a number of circuits, a number of data pads variously electrically coupled to the number of circuits, and a number of dummy data pads not electrically coupled to the number of circuits. The number of dummy data pads may be arranged relative to the number of data pads such that each of the number of dummy data pads of each of the number of dies aligns with a respective data pad of the number of data pads.

Various embodiments may include a die including: a number of circuits, a first edge, a second edge perpendicular to the first edge, a third edge opposite the first edge, and a fourth edge opposite the second edge. The die may also include a number of data pads variously electrically coupled to the number of circuits. The number of data pads may be arranged proximate to the first edge. The die may also include: a first number of dummy data pads, not electrically coupled to the number of circuits, arranged proximate to the second edge, a second number of dummy data pads, not electrically coupled to the number of circuits, arranged proximate to the third edge, and a third number of dummy data pads, not electrically coupled to the number of circuits, arranged proximate to the fourth edge. In such embodiments, the number of data pads may include a first data pad a first distance from the first edge and a second distance from the fourth edge, the first number of dummy data pads may include a first dummy data pad substantially the first distance from the second edge and substantially the second distance from the first edge, the second number of dummy data pads may include a second dummy data pad substantially the first distance from the third edge and substantially the second distance from the second edge, and the third number of dummy data pads may include a third dummy data pad substantially the first distance from the fourth edge and substantially the second distance from the third edge.

Various embodiments may include A method including stacking a number of dies such that data pads of one of the number of dies align with dummy data pads of dies above and beneath the one of the number of dies. Each of the number of dies may be substantially identical to each of the other dies. The method may also include electrically coupling data pads of some of the number of dies with dummy data pads of others of the number of dies. Such embodiments may also include rotating, prior to stacking the number of dies, all but a bottom of the number of dies substantially 90° or 180° relative to a die beneath it.

In accordance with common practice, the various features illustrated in the drawings may not be drawn to scale. The illustrations presented in the disclosure are not meant to be actual views of any particular apparatus (e.g., device, system, etc.) or method, but are merely idealized representations that are employed to describe various embodiments of the disclosure. Accordingly, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. In addition, some of the drawings may be simplified for clarity. Thus, the drawings may not depict all of the components of a given apparatus (e.g., device) or all operations of a particular method.

As used herein, the term “device” or “memory device” may include a device with memory, but is not limited to a device with only memory. For example, a device or a memory device may include memory, a processor, and/or other components or functions. For example, a device or memory device may include a system on a chip (SOC).

As used herein, the term “semiconductor” should be broadly construed, unless otherwise specified, to include microelectronic and MEMS devices that may or may not employ semiconductor functions for operation (e.g., magnetic memory, optical devices, etc.).

Terms used herein and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as “open” terms (e.g., the term “including” should be interpreted as “including, but not limited to,” the term “having” should be interpreted as “having at least,” the term “includes” should be interpreted as “includes, but is not limited to,” etc.).

Additionally, if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases “at least one” and “one or more” to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim recitation to embodiments containing only one such recitation, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and/or “an” should be interpreted to mean “at least one” or “one or more”); the same holds true for the use of definite articles used to introduce claim recitations. As used herein, “and/or” includes any and all combinations of one or more of the associated listed items.

In addition, even if a specific number of an introduced claim recitation is explicitly recited, it is understood that such recitation should be interpreted to mean at least the recited number (e.g., the bare recitation of “two recitations,” without other modifiers, means at least two recitations, or two or more recitations). Furthermore, in those instances where a convention analogous to “at least one of A, B, and C, etc.” or “one or more of A, B, and C, etc.” is used, in general such a construction is intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, etc. For example, the use of the term “and/or” is intended to be construed in this manner.

Further, any disjunctive word or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms. For example, the phrase “A or B” should be understood to include the possibilities of “A” or “B” or “A and B.”

Additionally, the use of the terms “first,” “second,” “third,” etc., are not necessarily used herein to connote a specific order or number of elements. Generally, the terms “first,” “second,” “third,” etc., are used to distinguish between different elements as generic identifiers. Absence a showing that the terms “first,” “second,” “third,” etc., connote a specific order, these terms should not be understood to connote a specific order. Furthermore, absence a showing that the terms “first,” “second,” “third,” etc., connote a specific number of elements, these terms should not be understood to connote a specific number of elements.

The embodiments of the disclosure described above and illustrated in the accompanying drawings do not limit the scope of the disclosure, which is encompassed by the scope of the appended claims and their legal equivalents. Any equivalent embodiments are within the scope of this disclosure. Indeed, various modifications of the disclosure, in addition to those shown and described herein, such as alternative useful combinations of the elements described, will become apparent to those skilled in the art from the description. Such modifications and embodiments also fall within the scope of the appended claims and equivalents.