Patent ID: 12211570

DETAILED DESCRIPTION

FIG.1illustrates an exemplary debug flow according to an embodiment of the invention. Generally, in the testing stage of a chip, when an error or an unexpected exception has occurred during the operation of a processor (e.g., a central processing unit) configured inside of the chip, a debug operation is required and the debug flow may comprise the following processing steps:

Step S100: The occurrence of an error or an unexpected exception is detected. For example, the processor or the chip under test itself, or another host device coupled to the chip under test or coupled to a development board having the chip under test installed therein, may perform the detection by monitoring one or more debug ports.

Step S102: The processor clock is stopped or turned off and it is switched to a scan dump mode. At this time, another scan clock with a lower frequency is turned on to assist subsequent dump operations.

Step S104: The content stored in all registers (or the statuses of all registers) of the chip is read and provided to the host device.

Step S106: It is switched to the memory dump mode.

Step S108: The content stored in all memories of the chip is read and provided to the host device.

Step S110: The dumped content is compared with the result obtained by software simulation (e.g., the golden pattern generated by the simulator under the same conditions) performed on the host device to determine the cause of the error or exception.

In the process similar to the memory read operation involved in step S108, the processor of the conventional design (e.g., the processor configured inside of the chip) must issue a dedicated read command for each memory address, and then sequentially provide the read data corresponding to each memory address to the host device through a test interface, such as IEEE1149.1 Joint Test Action Group (JTAG).

However, for each read command issued by the processor, it usually takes several (e.g., 3-5) clock cycles of the processor clock to complete the corresponding read operation. The reason is that the commands issued by the processor must undergo decoding and some other processes. As the number of memories configured in the chip increases, the time required for performing the memory dump operation will increase significantly, causing the problem that the memory dump operation is excessively time-consuming.

To solve this problem, a circuit and a corresponding method for efficiently performing memory dump are proposed. In one embodiment of the invention, a test circuit is utilized to perform memory dump related operations (e.g., the operations in the aforementioned step S108), and the proposed test circuit may be a Memory Built-in Self Test (MBIST) circuit. In the embodiments of the invention, the test circuit or the MBIST circuit may be configured with a corresponding test algorithm to complete the required memory read operations in the memory dump mode, and different from the conventional design, in the embodiments of the invention, it only takes one processor clock cycle to complete the read operation of a memory address. That is, in the embodiments of the invention, it is not necessary for the processor to sequentially issue the dedicated read command for each memory address, but the test circuit or MBIST circuit automatically performs and completes the read operations of all memory addresses, and the read operation of one memory address can be completed within one clock cycle of the processor. In this manner, compared with the conventional design that requires multiple clock cycles to complete the read operation of one memory address, the execution time of memory dump is greatly shortened by applying the proposed circuit and the corresponding method.

FIG.2illustrates an exemplary block diagram of a system according to an embodiment of the invention. The system mentioned here may comprise a development board200and a host device250, wherein the development board200may also be a system-on-chip (SoC) platform. The processor (not shown inFIG.2) of the host device250may realize a circuit simulator255by executing corresponding software. The development board200may be installed with a chip210under test, and the chip210may comprise a memory device220, a test circuit230and a register module240. The processor of the host device250may transmit the command CMD to the test interface260, such as the aforementioned JTEG, through the corresponding bus and receive the read data through the test interface260and the corresponding bus, such as the value Value_From_Memory read from the memory device shown inFIG.2. It is to be noted that, in order to clarify the concept of the invention,FIG.2presents a simplified block diagram in which only the components relevant to the invention are shown. Those skilled in the art can understand that the host device and the chip may further comprise many components or devices not shown inFIG.2to implement corresponding signal processing functions. In addition, in an embodiment of the invention, the test circuit230may be an MBIST circuit dedicatedly configured for the memory device220.

In an embodiment of the invention, when the processor of the host device250issues a command to switch an operation mode to the memory dump mode for performing memory dump, the chip210under test performs the read operations on different memory addresses to sequentially read the values stored therein through the test circuit230installed therein, and stores the values read from the memory device in the register module240. When the data stored in the register module240reaches a certain level, the data stored in the register module240are read and output to the bus connected between the development board200and the host device250, so as to be transmitted to the host device250. It is to be noted that the embodiments of the invention are not limited to configure the register module240outside the testing circuit230. In some embodiments of the invention, the register module240may also be configured inside the testing circuit230.

FIG.3illustrates an exemplary block diagram of a test circuit according to an embodiment of the invention. The test circuit300is coupled to the memory device320for reading data stored in the memory device320in the memory dump operation. It is to be noted that, to illustrate the operation of the test circuit300, the memory device320is also shown inFIG.3. However, in actual implementation, the test circuit300may not comprise the memory device320.

The test circuit300may comprise a control module310, a multiplexer330and a register module340. The control module310may comprise a pattern generator311and a dump controller312. The dump controller312may be configured to trigger the pattern generator311to start a corresponding pattern generating operation in response to a setting of a memory dump mode performed by a processor (e.g., a processor configured in the chip comprising the test circuit300). The multiplexer330may receive signals from a plurality of input sources and a selection signal, and select the signal(s) of one of the input sources to be output according to the setting of the selection signal. The plurality of input sources may comprise a pattern generated by the pattern generator311and a function input signal Function_Input generated by a processor (for example, the aforementioned processor configured in the chip, or a memory controller corresponding to the memory device320).

In one embodiment of the invention, the test circuit300may be an MBIST circuit dedicatedly configured for the memory device320. The selection signal received by the multiplexer330may be the setting signal BIST_Mode of the built-in self-test (BIST) mode or the setting signal Memory_Dump_Mode of the memory dump mode. For example, besides the communication port configured to receive the setting signal BIST_Mode, the test circuit300may comprise an additional communication port to receive the setting signal Memory_Dump_Mode.

When the test circuit300performs the BIST on the memory device320, the processor of the chip may program the value of the register corresponding to the setting signal BIST_Mode (for example, set to 1) to control the multiplexer330to select the pattern generated by the pattern generator311as the output, and now the pattern is generated for the BIST. Similarly, when the test circuit300performs the memory dump operation on the memory device320, the processor may program the value of the register corresponding to the setting signal Memory_Dump_Mode (for example, set to 1) to control the multiplexer330to select the pattern generated by the pattern generator311as the output, and now the pattern is generated for memory dump. When the test circuit300is neither performing BIST operation nor performing memory dump operation on the memory device320, the processor may control the multiplexer330to select and output the function input signal Function_Input by setting the value of the register corresponding to the setting signal BIST_Mode to other values (e.g., set to 0).

According to an embodiment of the invention, in response to the issuing of the command by the host device to request the chip to switch to the memory dump mode, the processor of the chip may set the value of the register corresponding to the setting signal Memory_Dump_Mode to a predetermined value, e.g., set to 1 as mentioned above, to notify the test circuit300to switch the operation mode to the memory dump mode. The control module310may also receive this setting signal Memory_Dump_Mode, and the dump controller312may trigger the pattern generator311to start generating the patterns of the control signals required in the memory dump mode in response to the setting of the memory dump mode (e.g. the aforementioned predetermined value), and provide the control signals to the memory device320.

In an embodiment of the invention, in the memory dump mode, the control signals generated by the pattern generator311may at least comprise an address signal ADDR, a memory enable signal ME and a read enable signal WE, wherein the read enable signal WE may also be regarded as a write enable signal. For example, one signal level of the read enable signal WE may be defined as the level to enable the write operation of the memory device, while another signal level of the read enable signal WE may be defined as the level to enable the read operation of the memory device. In the BIST mode, the control signal generated by the pattern generator311may further comprise the data signal D. In the memory dump mode, the pattern generator311may provide the control signals to the memory device320to control the memory device320to sequentially read the data stored in the corresponding memory address according to the content indicated by the address signal ADDR, and sequentially provide the read data to the register module340through the output communication port Q. The register module340may comprise one or more registers for sequentially receiving and storing the data. In an embodiment of the invention, the patterns of the control signals generated by the pattern generator311may be a sequence of patterns comprising only memory read operations.

FIG.4is a diagram showing the exemplary waveforms of the control signals according to an embodiment of the invention. In response to the setting of the memory dump mode, the pattern generator311may set the level of the memory enable signal ME to 1 (high level) to enable the memory device320, and set the level of the read enable signal WE to 0 (low level) to enable the read operation of the memory device320. In addition,FIG.4also shows the waveform of the clock signal CLK of the processor. The address signal ADDR generated by the pattern generator311in the memory dump mode may comprise a plurality of memory addresses, such as the memory addresses A_0˜A_5shown inFIG.4, arranged in a plurality of consecutive clock cycles of the processor.

In an embodiment of the invention, by setting the pattern of the address signal ADDR, the pattern generator311may arrange the read operation of one memory address within one clock cycle of the processor, and in the pattern of the address signal ADDR, the pattern generator311may arrange a plurality of memory addresses, such as a plurality of consecutive memory addresses, in a plurality of consecutive clock cycles for sequentially reading data stored in these memory addresses one by one in consecutive clock cycles. As illustrated by the operation waveform OP inFIG.4, a plurality of read operations Read will be performed continuously within a plurality of clock cycles. By arranging the memory addresses and the setting the corresponding patterns of other control signals, the test circuit300may complete a predetermined number of data read operations to read data from the memory device320within the predetermined number of clock cycles of the processor. Assuming that the memory space of the memory device320addressed by one memory address is able to store 128 bits of data, the test circuit230/300may complete the read operation of 128-bit data within one clock cycle of the processor, and the read operations corresponding to a predetermined number of memory addresses can be completed within the equal number of (i.e. the aforementioned predetermined number of) clock cycles of the processor in response to the aforementioned control signals, wherein the read data size in each read operation is 128 bits in this example, but the invention is not limited thereto.

An exemplary script that uses the test circuit or the MBIST circuit to automatically complete the memory dump is provided. In this example, the memory dump script includes P steps to read N memory addresses, and the corresponding descriptions are shown as the following steps:Step 0: A memory dump command is sent by the host device.Step 1: Memory dump is performed by the chip.Step 2: (Internal operation of the test circuit) The first memory address of the memory device is read and the corresponding data is stored in the register by the test circuit.Step 3: The read operation is performed on the register.Step 4: The read data is transmitted to the host device.

( . . . omitted)Step (P-3): (Internal operation of the test circuit) The (N−1) memory address of the memory device is read and the corresponding data is stored in the register by the test circuit.Step (P-2): The read operation is performed on the register.Step (P-1): The read data is transmitted to the host device.

Since, in the embodiments of the invention, the processor does not sequentially issue the read commands which are respectively for each memory address, but triggers the test circuit to enter and operate in the memory dump mode by setting the signal Memory_Dump_Mode and generate the corresponding patterns of control signals to perform the corresponding read operations. Therefore, in the embodiments of the invention, the operations of reading N memory addresses can be completed in a shorter time than the conventional design. As an example, the Step 1, Step 2 and Step 3 shown above all do not involve the operation of the processor.

FIG.5shows an exemplary flow chart of a method for reading data stored in a memory device in a memory dump operation according to an embodiment of the invention. The method comprises the following steps:Step S502: A plurality of control signals are generated in response to a setting of a memory dump mode performed by a processor.Step S504: The plurality of control signals are provided to the memory device.Step S506: The data stored in a plurality of memory addresses is sequentially read in a plurality of consecutive clock cycles in response to the plurality of control signals.

In Step S506, within a predetermined number of clock cycles of the processor, the memory device sequentially outputs the data stored in the same number of (i.e., the predetermined number of) memory addresses.

According to an alternative embodiment of the invention, in addition to one or more registers, the register module may further comprise a scheduler for scheduling the receptions of data, and the scheduler may perform handshake with the control module to complete the serial output of the data (i.e., each piece of data being sequentially output) or parallel output of the data (i.e. multiple pieces of data being output at the same time).

FIG.6illustrates an exemplary block diagram of a test circuit according to an alternative embodiment of the invention. The test circuit600is coupled to the memory device620for reading data stored in the memory device620in the memory dump operation. It is to be noted that, to illustrate the operation of the test circuit600, the memory device620is also shown inFIG.6. However, in actual implementation, the test circuit600may not comprise the memory device620.

The test circuit600may comprise a control module610, a multiplexer630and a register module640. The control module610may comprise a pattern generator611and a dump controller612. The dump controller612may be configured to generate a start signal Start (e.g., by generating a corresponding pulse) in response to a setting of a memory dump mode performed by a processor (e.g., a processor configured in the chip comprising the test circuit600) and trigger the pattern generator611to start a corresponding pattern generating operation.

In one embodiment of the invention, the test circuit600may be an MBIST circuit dedicatedly configured for the memory device620. The basic operations of the control module610, the memory device620, the multiplexer630, the pattern generator611and the dump controller612are the same as those of the control module310, the memory device320, the multiplexer330, the pattern generator311and the dump controller312as illustrated inFIG.3, and the descriptions are omitted here for brevity.

According to an embodiment of the invention, the register module640may comprise a plurality of registers, such as the register REG_0, the register REG_1and the register REG_2and the scheduler642configured to schedule the receptions of data. It is to be noted that the number of registers shown inFIG.6is not a limit to the invention.

The control module610receives the setting signal Memory_Dump_Mode, and in response to the setting of the memory dump mode (e.g. the aforementioned predetermined value), the dump controller612generates the start signal Start and triggers the pattern generator611to start generating the patterns of the control signals required in the memory dump mode. The start signal Start is provided to the scheduler642to notify the start of the read operation, and the control signals are provided to the memory device620to control the read operations of the memory device620. The memory device620sequentially reads the data stored in the corresponding memory addresses according to the content indicated by the address signal ADDR in response to the control signals, and provides the read data to the register module640through the output communication port Q. The register module640may comprise one or more registers to sequentially receive data and store the data. The scheduler642may sequentially arrange one of the registers to receive the data from the memory device620and store the received data in response to the start signal Start.

When the data stored in the register module640reaches a certain level, the data stored in the register module640are read and output by the scheduler642in a serial manner or in a parallel manner, and the read data is output to the bus connected to the host device to provide the data to the host device. In addition, the scheduler642may send a notification signal Next (e.g., by generating a corresponding pulse) to the dump controller612to notify the dump controller612to continue the subsequent read operation.

The dump controller612may regenerate the start signal Start (e.g., by generating a corresponding pulse) in response to the reception of the notification signal Next, and trigger pattern generator611to continue to arrange a plurality of memory addresses that have not been read in the address signal ADD in response to the start signal Start (which is equivalent to in response to the notification signal Next) and generate the corresponding address signal ADDR, the memory enable signal ME and the read enable signal WE.

According to an embodiment of the invention, the scheduler642may also count a predetermined time, for example, count a specific number of clock cycles, and when the predetermined time expires, the data stored in the register module640are read and output by the scheduler642in a serial manner or in a parallel manner, and the read data is output to the bus connected to the host device to provide the data to the host device. In addition, the scheduler642may send a notification signal Next (e.g., by generating a corresponding pulse) to the dump controller612to notify the dump controller612to continue the subsequent read operation.

According to an embodiment of the invention, the predetermined time or the specific number may be related to the number of registers configured in the register module640. For example, if there are three registers comprised in the register module640, in response to the reception of the start signal Start, the scheduler642may repeatedly count for 3 clock cycles, and every time when 3 clock cycles have been counted, the scheduler642reads out the data stored in the three registers and generate a pulse of the corresponding notification signal Next to notify the dump controller612to continue the subsequent read operation.

It should be noted that the register module640may also be implemented by a first-in-first-out (FIFO) circuit, and in such implementation, the start signal Start and the notification signal Next may be respectively provided as indicators, to respectively indicate the operations of writing data into the FIFO circuit and outputting data from the FIFO circuit.

FIG.7shows exemplary waveforms of the serial output of multiple pieces of data of the memory device under the control of the test circuit according to an embodiment of the invention. InFIG.7, not only the waveforms of the clock signal CLK of the processor, the address signal ADDR, the memory enable signal ME, the read enable signal WE, the start signal Start, and the notification signal Next are shown, but also the waveforms of signals at the output communication port Q of the memory device such as the signal Value, the data signal REG* written in the registers, and the signal OUT transmitted on the bus connected between the register module and the host device are shown.

As shown inFIG.7, in response to the pulse of the start signal Start, the pattern generator generates the corresponding control signals, and the memory device sequentially outputs the pieces of data D0-D8read from the addresses A_0-A_8based on the settings of the control signals, wherein each output is performed in one clock cycle of the clock signal CLK. Assuming that there are three registers comprised in the register module, which are respectively numbered by REG_0, REG_1and REG_2, and the waveform of the data signal REG* of the registers is represented by simplified register numbers R_0-R_2with the data D0-D8marked in brackets to indicate the data written into each register in different clock cycles. In this embodiment, the register module sequentially outputs the received data to the bus. Therefore, the signal OUT transmitted on the bus has valid data in the corresponding clock cycle, which is filled with slashes inFIG.7to represent valid data on the bus. In this embodiment, the data D0-D8corresponding to memory addresses A_0-A_8will be sequentially read in 9 consecutive clock cycles, and will be sequentially output to the bus in 9 consecutive clock cycles, and the scheduler generates a pulse in the corresponding notification signal Next every time when it finishes counting one clock cycle, so as to notify the dump controller to continue the subsequent read operation. Therefore, in the embodiment of serial output, because the test circuit completes the read operation of one piece of data within one clock cycle of the processor, N pieces of data are continuously output in adjacent N clock cycles, wherein N is a positive integer.

FIG.8shows exemplary waveforms of the parallel output of multiple pieces of data of the memory device under the control of the test circuit according to an alternative embodiment of the invention. In this embodiment, the pieces of data that have been written in the registers REG_0-REG_2in different clock cycles, such as the data grouped in each of the following brackets: {R_0(D0), R_1(D1) and R_2(D2)}, {R_0(D3), R_1(D4) and R_2(D5)}, {R_0(D6), R_1(D7) and R_2(D8)}, etc. will be output to the bus in parallel at the same time. Therefore, the signal OUT transmitted on the bus only has valid data in the clock cycle when the data is output. In this embodiment, in response to the pulse of the start signal Start, the pattern generator generates the corresponding control signals, and the scheduler generates the pulse of the corresponding notification signal Next after the reading of data stored in the registers is completed or after counting at least 3 clock cycles, to notify the dump controller to continue the subsequent read operation. In the embodiment of parallel output, since the test circuit completes the read operation of one piece of data within one clock cycle of the processor, the memory device may continuously output M pieces of data in adjacent M clock cycles, wherein M is a positive integer, and the scheduler may output data to the bus in parallel after the M pieces of data have been written into the register, for example, after counting M clock cycles, so that the M pieces of data are output to the bus at the same time in a parallel manner.

In the embodiments of the invention, the host device only needs to send the signal to switch operation modes, and when it is switched to the memory dump mode to perform memory dump, the test circuit configured in the chip under test sequentially performs the read operations on different memory addresses to read the corresponding values, without the need of issuing the corresponding read command for each memory address by the processor. That is, upon receiving the signal to switch the operation mode, the processor comprised in the chip under test only needs to perform the operations of setting the value of the setting signal Memory_Dump_Mode, and does not have to participate in the data read operation of the memory. In response to the setting of the memory dump mode (for example, setting the value of the setting signal Memory_Dump_Mode to a predetermined value), the test circuit automatically generates corresponding control signals, comprising the address signal ADDR with a plurality of memory addresses arranged in a plurality of consecutive clock cycles of the processor, and controls the memory device to only perform the corresponding read operations in the memory dump mode. In this manner, the execution time of memory dump can be greatly shortened by applying the proposed circuit and the corresponding method as compared with the conventional design. In addition, the MBIST circuit which is generally configured for memory devices may be directly applied as the proposed test circuit without adding an additional memory dump circuit or a circuit dedicated for memory dump operation. Therefore, although the memory dump operation is performed by hardware circuits in the embodiments of the invention, no additional circuit area is actually required, which shows that the proposed solution is also a low circuit area solution.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.