Patent ID: 12224256

DETAILED DESCRIPTION OF EMBODIMENTS

In this description, like reference numerals may indicate like components. The following will now describe wafer structures, semiconductor devices, semiconductor packages, and their fabricating methods.

FIG.1Aillustrates a plan view showing a wafer structure according to some embodiments.FIG.1Billustrates an enlarged view showing section I ofFIG.1A.FIG.1Cillustrates a cross-sectional view taken along line II-II′ ofFIG.1B.FIG.1Dillustrates an enlarged view showing section III ofFIG.1C.

Referring toFIGS.1A to1D, a wafer structure1000may include a semiconductor substrate100, lower conductive pads130, a circuit layer110, through vias200, conductive pads300, a first dielectric layer410, a second dielectric layer420, a third dielectric layer430, and dielectric patterns500.

As shown inFIGS.1A and1B, when viewed in plan, the semiconductor substrate100may have chip regions CR and a scribe lane region SLR. Each of the chip regions CR may be an area that is used as a substrate for a semiconductor device (see10ofFIG.3A) which will be discussed below. Chip regions CR of the semiconductor substrate100may be separated from each other by the scribe lane region SLR. The chip regions CR may be spaced apart from each other in a first direction D1or in a second direction D2. For example, the chip regions CR may be arranged along rows parallel to the first direction D1and along columns parallel to the second direction D2.

The first direction D1may be parallel to a first surface100aof the semiconductor substrate100. The first direction D1may be parallel to a major axis of the semiconductor substrate100. The second direction D2may be parallel to the first surface100aof the semiconductor substrate100and substantially perpendicular to the first direction D1. A third direction D3may be substantially perpendicular to the first surface100aof the semiconductor substrate100and may intersect the first direction D1and the second direction D2. A fourth direction D4may be parallel to the first surface100aof the semiconductor substrate100and may intersect the first direction D1and the second direction D2. The fourth direction D4may be a diagonal direction. The fourth direction D4may be substantially orthogonal to the third direction D3.

The scribe lane region SLR may be disposed between the chip regions CR of the semiconductor substrate100. The scribe lane region SLR may surround each of the chip regions CR. The scribe lane region SLR may be an imaginary area. The scribe lane region SLR may include a dicing region R1and a dummy region R2. The dicing region R1of the scribe lane region SLR may be an area that is removed in a dicing process which will be discussed inFIGS.3A and3B. A range of about 80 μm to about 150 μm may be given to a width W10in the first direction D1of the dicing region R1. A range of about 80 μm to about 150 μm may be given to a width W20in the second direction D2of the dicing region R1.

The dummy region R2may be provided between the dicing region R1and the chip regions CR. The presence of the dummy region R2may prevent or mitigate damage to components of the chip region CR in a dicing process.

The scribe lane region SLR may include first regions, second regions, and intersection regions. Each of the first regions of the scribe lane region SLR may extend in a direction parallel to the first direction D1, and each of the second regions of the scribe lane region SLR may extend in a direction parallel to the second direction D2. The interconnection regions may be areas where the first regions meet the second regions.

The dielectric patterns500may include etch stop patterns510and alignment key patterns520. The etch stop patterns510may be provided on the chip regions CR. The alignment key patterns520may be spaced apart from the etch stop patterns510. When viewed in plan, the alignment key patterns520may be correspondingly provided on the intersection regions of the scribe lane region SLR. A width W1in the first direction D1of the alignment key pattern520may be greater than the width W10of the dicing region R1. For example, a range of about 30 μm to about 180 μm may be given to the width W1in the first direction D1of the alignment key pattern520. For more detail, a range of about 140 μm to about 180 μm may be given to the width W1in the first direction D1of the alignment key pattern520. A range of about 30 μm to about 180 μm may be given to a width W2in the second direction D2of the alignment key pattern520.

Differently from that shown, the width W2in the second direction D2of the alignment key pattern520may be greater than the width W20of the dicing region R1, and the width W1in the first direction D1of the alignment key pattern520may be less than the width W10of the dicing region R1. Alternatively, the width W1in the first direction D1and the width W2in the second direction D2of the alignment key pattern520may be respectively greater than the width W10in the first direction D1and the width W20in the second direction D2of the dicing region R1. When a value of equal to or less than about 30 μm is given to the width W1in the first direction D or the width W2in the second direction D2of the alignment key pattern520, it may be difficult to recognize the alignment key patterns520in a following process for forming the wafer structure1000. When a value of equal to or greater than about 180 μm is given to the width W1in the first direction D or the width W2in the second direction D2of the alignment key pattern520, the alignment key patterns520may extend onto the chip regions CR. This case may impose a limitation on arrangement of the conductive pads300which will be discussed below inFIGS.1C and1D.

Referring toFIG.1C, the circuit layer110may be provided on the second surface100bof the semiconductor substrate100. The through vias200may be provided on the chip regions CR of the semiconductor substrate100. The through vias200may penetrate the semiconductor substrate100and may further penetrate at least a portion of the circuit layer110. The circuit layer110may be provided with solder balls150on a bottom surface thereof. The through vias200may be electrically connected to the solder balls150. The solder balls150may overlap the chip regions CR of the semiconductor substrate100. The solder balls150may include a solder material, such as tin, lead, silver, or an alloy thereof.

The first dielectric layer410may be provided on the first surface100aof the chip regions CR and the scribe lane region SLR of the semiconductor substrate100. The second dielectric layer420may be provided on the first dielectric layer410. The second dielectric layer420may overlap the first surface100aof the chip regions CR and the scribe lane region SLR of the semiconductor substrate100. The dielectric patterns500may be provided between the first dielectric layer410and the second dielectric layer420. The dielectric patterns500may include the alignment key patterns520and the etch stop patterns510. The alignment key patterns520may be provided on the scribe lane region SLR. The first dielectric layer410and the second dielectric layer420may be provided therebetween with the third dielectric layer430interposed between the dielectric patterns500.

The conductive pads300may be provided in the second dielectric layer420and on the through vias200. The conductive pads300may be coupled to the through vias200. The conductive pads300may overlap the chip regions CR.

A wafer structure will be described in detail with reference toFIG.1D. A single alignment key pattern520will be discussed in the interest of brevity of description.

Referring toFIGS.1C and1D, the wafer structure1000may further include integrated circuits125. The integrated circuits125may be provided on the second surface100bof the chip regions CR of the semiconductor substrate100. The integrated circuits125may not be provided on the scribe lane region SLR of the semiconductor substrate100. The integrated circuits125may include transistors.

The circuit layer110may be provided on the second surface100bof the semiconductor substrate100. The circuit layer110may include dielectric layers111and wiring structures113. The dielectric layers111may be stacked on the second surface100bof the scribe lane region SLR and the chip regions CR of the semiconductor substrate100. An uppermost one of the dielectric layers111may cover the integrated circuits125. The dielectric layers111may include a silicon-based dielectric material, such as one or more of silicon oxide, silicon oxide, silicon oxynitride, and silicon carbonitride. Alternatively, at least one of the dielectric layers111may include an organic material such as a dielectric polymer, but the present inventive concepts are not limited thereto.

The wiring structures113may be provided on the second surface100bof the chip regions of the semiconductor substrate100. The wiring structures113may include a contact plug, a wiring pattern, and a via. The wiring structures113may include metal, such as copper or tungsten. A contact plug may penetrate an uppermost dielectric layer111and may be coupled to at least one of the integrated circuits125. The wiring patterns may be provided between the dielectric layers111. The vias may penetrate the dielectric layers111and may be coupled to the wiring patterns. The wiring structures113may not be provided on the scribe lane region SLR.

The lower conductive pads130may be provided on the bottom surface of the circuit layer110. For example, the lower conductive pads130may be provided in a lowermost one of the dielectric layers111. The solder balls150may be provided on bottom surfaces of the lower conductive pads130. The solder balls150may be electrically connected through the wiring structures113to the integrated circuits125. The lower conductive pads130may include metal, such as copper or aluminum. Neither the lower conductive pads130nor the solder balls150may be provided on the scribe lane region SLR of the semiconductor substrate100.

The through vias200may be provided on the chip regions CR of the semiconductor substrate100and may penetrate the first and second surfaces100aand100bof the semiconductor substrate100. The through vias200may further penetrate at least one of the dielectric layers111. The through vias200may be coupled to the wiring structures113. Therefore, the through vias200may be coupled to the solder balls150or the integrated circuits125. The through vias200may not be provided on the scribe lane region SLR of the semiconductor substrate100. Upper portions of the through vias200may be provided in the first dielectric layer410.

Each of the through vias200may include a barrier pattern210and a conductive via250. The conductive via250may be disposed on the barrier pattern210. The conductive via250may include metal, such as copper and tungsten. The barrier pattern210may be provided along a sidewall of the conductive via250. For example, the barrier pattern210may be provided between the conductive via250and the semiconductor substrate100, between the conductive via250and one of the dielectric layers111, and between the conductive via250and the first dielectric layer410. The barrier pattern210may not cover a top or bottom surface of the conductive via250. The barrier pattern210may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The barrier pattern210may prevent or reduce diffusion of materials included in the conductive via250. The barrier pattern210may be a seed pattern.

The first dielectric layer410may cover the first surface100aof the semiconductor substrate100. The first dielectric layer410may include extension portions413. The extension portions413of the first dielectric layer410may be provided along and may cover sidewalls of the through vias200. The extension portions413of the first dielectric layer410may have their top surfaces coplanar with those of the through vias200. Although not shown, each of the extension portions413of the first dielectric layer410may have a closed loop shape when viewed in plan. The first dielectric layer410may include silicon-based dielectric material. For example, the first dielectric layer410may include silicon oxide. The first dielectric layer410may serve as an adhesion layer.

The dielectric patterns500may be provided on the first dielectric layer410. The dielectric patterns500may include a different material from that of the first dielectric layer410and that of the second dielectric layer420. For example, the dielectric patterns500may include silicon-based dielectric material, such as silicon nitride.

As discussed above, the dielectric patterns500may include the alignment key patterns520and the etch stop patterns510. The etch stop patterns510may be laterally spaced apart from the sidewalls of the through vias200. The first dielectric layer410may be provided between the etch stop patterns510and the sidewalls of the through vias200. For example, the extension portions413of the first dielectric layer410may be interposed between the etch stop patterns510and the sidewalls of the through vias200. There may be a relatively small adhesion force between dielectric patterns500and the semiconductor substrate100and between the dielectric patterns500and the through vias200(or the barrier patterns210). According to some embodiments, because the first dielectric layer410is provided between the dielectric patterns500and the semiconductor substrate100and between the dielectric patterns500and the through vias200, the etch stop patterns510may be stably fixed through the first dielectric layer410to the semiconductor substrate100and the through vias200. The dielectric patterns500may have their top surfaces located at substantially the same level as that of top surfaces of the through vias200and that of top surfaces of the extension portions413of the first dielectric layer410. The phrase “certain components are the same in terms of width, height, and level” may include an allowable tolerance possibly occurring during fabrication process.

The alignment key pattern520may be provided on the scribe lane region SLR of the semiconductor substrate100. For example, the alignment key pattern520may be provided on the dicing region R1of the semiconductor substrate100. The alignment key pattern520may further extend onto the dummy region R2of the semiconductor substrate100. A width in the fourth direction D4of the alignment key pattern520may be greater than a width in the fourth direction D4of the dicing region R1.

The alignment key pattern520may be laterally spaced apart from the etch stop patterns510. The phrase “two components are laterally spaced apart from each other” may mean that “two components are horizontally spaced apart from each other.” The language “horizontal” may mean that parallel to the first surface100aof the semiconductor substrate100. The alignment key pattern520may have a hole590that penetrates therethrough. The hole590may further penetrate the first dielectric layer410. The hole590may have a bottom surface that is provided in the first dielectric layer410. The alignment key pattern520may have a shape that is variously changed without being limited to the shape illustrated in the figures. For example, the alignment key pattern520may be formed without the hole590.

The third dielectric layer430may be provided between the alignment key pattern520and the etch stop patterns510. The third dielectric layer430may further be provided in the hole590of the alignment key pattern520. The third dielectric layer430may further penetrate an upper portion of the first dielectric layer410. The third dielectric layer430may have a bottom surface located at a level that is lower than that of bottom surfaces of the dielectric patterns500and higher than that of the first surface100aof the semiconductor substrate100. A level of a certain component may indicate a vertical level, and a level difference between two components may be measured in the third direction D3. The third dielectric layer430may include a different material from that of the dielectric patterns500. For example, the third dielectric layer430may include the same material as that of the first dielectric layer410. In this case, an indistinct interface may be provided between the first dielectric layer410and the third dielectric layer430, but the present inventive concepts are not limited thereto. The third dielectric layer430may include a silicon-based dielectric material, such as silicon oxide.

The second dielectric layer420may be provided on the dielectric patterns500and the third dielectric layer430. The second dielectric layer420may have a first top surface420aand a second top surface420aa. The first top surface420aof the second dielectric layer420may be provided on the chip regions CR, and the second top surface420aaof the second dielectric layer420may be provided on the scribe lane region SLR. The first top surface420aof the second dielectric layer420may be located at a lower level than that of the second top surface420aaof the second dielectric layer420. The second dielectric layer420may include a silicon-based dielectric material, such as silicon oxide or silicon carbonitride.

The conductive pads300may be provided in the second dielectric layer420and on the through vias200. The second dielectric layer420may surround sidewalls of the conductive pads300. The conductive pads300may have their top surfaces300athat are exposed by the second dielectric layer420. The second top surface420aaof the second dielectric layer420may be located at a lower level than that of the top surfaces300aof the conductive pads300. For example, there may be a level difference A ranging from about 0.01 μm to about 0.1 μm may be provided between the second top surface420aaof the second dielectric layer420and the top surfaces300aof the conductive pads300. In this case, the top surfaces300aof the conductive pads300may be top surfaces at edge regions of the conductive pads300. The level difference A may be a maximum level difference.

The conductive pads300may be provided on and electrically connected to the through vias200. For example, the conductive pads300may be electrically connected through the through vias200to the integrated circuits125or to the solder balls150. The conductive pads300may further be provided on the extension portions413of the first dielectric layer410and on the etch stop patterns510. For example, the conductive pads300may have their bottom surfaces in physical contact with top surfaces510aof the etch stop patterns510.

Each of the conductive pads300may include a barrier pad310and a metal pad350. The barrier pad310may cover a bottom surface and a sidewall of the metal pad350, but may expose a top surface of the metal pad350. The barrier pad310may include at least one selected from titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). The metal pad350may include, for example, copper.

According to some embodiments, the alignment key pattern520may have a size greater than those of the conductive pads300. For example, a width W4in the fourth direction D4of the alignment key pattern520may be greater than widths W3in the fourth direction D4of the conductive pads300. When the alignment key pattern520is provided on the chip regions CR of the semiconductor substrate100, the alignment key pattern520may impose a limitation on arrangement of the conductive pads300and the through vias200. According to some embodiments, because the alignment key pattern520is provided on the scribe lane region SLR of the semiconductor substrate100, it may be possible to freely design an arrangement of the conductive pads300and the through vias200. For example, the conductive pads300may have a fine pitch.

According to some embodiments, no conductive component may be provided on the scribe lane region SLR of the semiconductor substrate100.

FIG.1Eillustrates an enlarged view of section III depicted inFIG.1C, showing conductive pads and through vias according to some embodiments.

Referring toFIG.1E, the conductive pads300may have protrusions303. For example, the protrusions303may be provided on the bottom surfaces of the conductive pads300, while protruding into the first dielectric layer410. For example, the protrusions303may protrude into the extension portions413of the first dielectric layer410. The protrusions303may be interposed between the conductive pads300and the etch stop patterns510. The protrusions303may not be provided on the etch stop patterns510. The extension portions413of the first dielectric layer410may have their top surfaces located at a lower level than that of the top surfaces510aof the etch stop patterns510and that of the top surfaces of the through vias200.

The through vias200may penetrate the first and second surfaces100aand100bof the semiconductor substrate100, but may not penetrate the dielectric layer111. For example, the through vias200may be formed in a via-first process. Alternatively, as discussed in the embodiment ofFIG.1D, the through vias200may further penetrate at least one of the dielectric layers111.

FIG.1Fillustrates an enlarged view of section I depicted inFIG.1B, showing an alignment key according to some embodiments.

Referring toFIG.1F, the alignment key pattern520may have a cross shape. The alignment key pattern520may be provided on the dicing region R1of the scribe lane region SLR. The alignment key pattern520may further extend onto the dummy region R2. The width W1in the first direction D1and the width W2in the second direction D2of the alignment key pattern520may satisfy a condition discussed in the embodiment ofFIG.1D.

The following will describe a method of fabricating a wafer structure according to some embodiments.

FIGS.2A to2Lillustrate enlarged views of section III depicted inFIG.1C, showing a method of fabricating a wafer structure according to some embodiments of the present inventive concepts. A description duplicate with the aforementioned will be omitted hereinafter.

Referring toFIG.2A, a semiconductor substrate100may be prepared. Integrated circuits125and a circuit layer110may be formed on a second surface100bof the semiconductor substrate100, and through vias200may be formed in the semiconductor substrate100. The through vias200may be formed in a via-middle process. Alternatively, the through vias200may be formed in a via-first process. In this case, the through vias200may not penetrate a dielectric layer111.

According to some embodiments, a through hole209may be formed to penetrate the second surface100bof the semiconductor substrate100. The through hole209may further penetrate the dielectric layer111. The through hole209may have a bottom surface that is provided in the semiconductor substrate100. A barrier pattern210may be formed in the through hole209to conformally cover a sidewall and the bottom surface of the through hole209. The barrier pattern210may serve as a seed pattern. For example, an electroplating process may be performed in which the barrier pattern210is used as an electrode. The electroplating process may fill the through hole209with a conductive material to form a conductive via250.

Referring toFIG.2B, an upper portion of the semiconductor substrate100may be removed to thin the semiconductor substrate100. The thinning of the semiconductor substrate100may include performing a planarization process or an etch-back process on the second surface100bof the semiconductor substrate100. The planarization process may be a chemical mechanical polishing process. While the semiconductor substrate100is thinned, the through vias200may not be removed. The semiconductor substrate100may be thinned such that upper portions of the through vias200may protrude onto a first surface100aof the semiconductor substrate100.

Referring toFIG.2C, a first dielectric layer410may be formed on the first surface100aof the semiconductor substrate100and on the upper portions of the through vias200. The first dielectric layer410may conformally cover the first surface100aof the semiconductor substrate100, and may also conformally cover sidewalls and top surfaces of the upper portions of the through vias200. The first dielectric layer410may be formed by, for example, a deposition process.

A preliminary dielectric pattern500Z may be formed on the first surface100aof the semiconductor substrate100and on the sidewalls and the top surfaces of the upper portions of the through vias200, thereby covering the first dielectric layer410. The preliminary dielectric pattern500Z may be formed by a deposition process.

Referring toFIG.2D, a first resist pattern810may be formed on the preliminary dielectric pattern500Z. The first resist pattern810may include an organic material. A photolithography process may be performed such that the first resist pattern810may be patterned to form first guide holes819. The first guide holes819may penetrate the first resist pattern810to expose the preliminary dielectric pattern500Z.

Referring toFIG.2E, the preliminary dielectric pattern500Z exposed to the first guide holes819may be removed to form a hole590and a trench519. The removal of the preliminary dielectric pattern500Z may be achieved by an etching process, such as a dry etching process. The etching process may be performed using, for example, nitrogen and oxygen. The etching process may also remove a portion of the first resist pattern810.

The hole590and the trench519may be spaced apart from each other. The hole590and the trench519may penetrate the preliminary dielectric pattern500Z and extend into an upper portion of the first dielectric layer410. For example, the hole590and the trench519may have their bottom surfaces provided in the first dielectric layer410.

Referring toFIG.2F, a remaining first resist pattern810may be removed to expose the preliminary dielectric pattern500Z. An ashing or strip process may be performed to remove the first resist pattern810.

Referring toFIG.2G, a preliminary dielectric layer430Z may be formed on the preliminary dielectric pattern500Z to fill the hole590and the trench519. The preliminary dielectric layer430Z may include a different material from that of the preliminary dielectric pattern500Z. The preliminary dielectric layer430Z in the hole590and the trench519may have a top surface located at a level the same as or higher than that of top surfaces of the through vias200. The preliminary dielectric layer430Z may be formed by a deposition process.

Referring toFIG.2H, the preliminary dielectric layer430Z may be performed to form dielectric patterns500and a third dielectric layer430. The planarization process may include a chemical mechanical polishing (CMP) process. The planarization process may remove the preliminary dielectric layer430Z from a top surface of the preliminary dielectric pattern500Z. The preliminary dielectric layer430Z may be localized in the hole590and the trench519.

The planarization process may remove upper portions of the through vias200, a portion of the first dielectric layer410, and a portion of the preliminary dielectric pattern500Z. For example, the planarization process may partially remove the first dielectric layer410and the preliminary dielectric pattern500Z on the upper portion of the through vias200. The portion of the preliminary dielectric pattern500Z may be removed to form the dielectric patterns500. The dielectric patterns500may include an alignment key pattern520and etch stop patterns510. The alignment key pattern520and the etch stop patterns510510and520may be separated from each other. As a result of the planarization process, there may be exposed the conductive via250, the barrier pattern210, the extension portions413of the first dielectric layer410, the dielectric patterns500, and the third dielectric layer430. The dielectric patterns500may have their top surfaces located at substantially the same level as that of a top surface of the conductive via250, that of a top surface of the barrier pattern, that of top surfaces of the extension portions413of the first dielectric layer410, and that of a top surface of the third dielectric layer430. The top surfaces of the dielectric patterns500may include a top surface520aaof the alignment key pattern520and top surfaces510aof the etch stop patterns510.

According to some embodiments, as shown inFIG.2G, the top surface of the preliminary dielectric layer430Z in the hole590and the trench519is located at a level the same as or higher than that of the top surfaces of the through vias200.

Referring toFIG.2I, a second dielectric layer420may be formed to cover the top surfaces of the through vias200, the top surfaces of the extension portions413of the first dielectric layer410, the top surfaces of the dielectric patterns500, and the top surface of the third dielectric layer430. The second dielectric layer420may have a flat top surface. The second dielectric layer420may be formed by a deposition process.

A second resist pattern820may be formed on the second dielectric layer420. A photolithography process may be performed such that the second resist pattern820may be patterned to form second guide holes829. The second guide holes829may penetrate the second resist pattern820and expose the second dielectric layer420.

Before the second guide holes829are formed, a position of the alignment key pattern520may be recognized. According to some embodiments, because the alignment key pattern520includes the first, second, and third dielectric layers410,420, and430, there may be a visible interface between the alignment key pattern520and the first, second, and third dielectric layers410,420, and430. Light (e.g., infrared light) may be used to recognize the alignment key pattern520. The light may pass through the second resist pattern820and the second dielectric layer420. The recognized position of the alignment key pattern520may be used to calculate positions of the through vias200. The recognized and calculated results may be used to decide formation positions of the second guide holes829. The second guide holes829may vertically overlap the through vias200.

Referring toFIG.2J, the second dielectric layer420exposed to the second guide holes829may be etched to form pad trenches429in the second dielectric layer420. A dry etching process may be performed to etch the second dielectric layer420. For example, oxygen may be used to perform the dry etching process. In the etching process, an upper portion of the second resist pattern820may be removed.

In the etching process, the etch stop patterns510and the through vias200may have their etch selectivity. For example, the etch stop patterns510may not be etched or may have an extremely low etch rate. After the etching process is completed, the pad trenches429may expose the top surfaces510aof the etch stop patterns510and the top surfaces of the through vias200. In addition, the pad trenches429may expose the extension portions413of the first dielectric layer410. When the etch stop patterns510are omitted, the pad trenches429may have step differences on bottom surfaces thereof. According to some embodiments, the etch stop patterns510may be provided to satisfactorily form the pad trenches429.

Alternatively, in the etching process, the extension portions413of the first dielectric layer410may further be etched. In this case, the top surfaces of the extension portions413of the first dielectric layer410may be located at a lower level than that of the top surfaces510aof the etch stop patterns510.

Referring toFIG.2K, the second resist pattern820may be removed to expose a top surface of the second dielectric layer420. An ashing or strip process may be performed to remove the second resist pattern820.

Referring toFIG.2L, a barrier layer310Z may be formed in the pad trenches429and on the second dielectric layer420. A deposition process may be performed to form the barrier layer310Z. The barrier layer310Z may conformally cover the bottom surfaces and sidewalls of the pad trenches429and the top surface of the second dielectric layer420.

An electroplating process may be performed in which the barrier layer310Z is used as an electrode. The electroplating process may fill the pad trenches429with metal to form a metal layer350Z. The metal layer350Z may extend onto the top surface of the second dielectric layer420.

Referring back toFIG.1D, the metal layer350Z and the barrier layer310Z may undergo a polishing process to form a metal pad350and a barrier pad310. The polishing process may include a chemical mechanical polishing (CMP) process. The polishing process may partially remove the barrier layer310Z and the metal layer350Z that are provided on the top surface of the second dielectric layer420. As a result of the polishing process, conductive pads300may be formed which are separated from each other. The conductive pads300may be localized in the pad trenches429. Each of the conductive pads300may include a metal pad350and a barrier pad310. The conductive pads300may have their top surfaces300acoplanar with a first top surface420aof the second dielectric layer420.

The second dielectric layer420on the scribe lane region SLR may be relatively widely spaced apart from the conductive pads300. In the polishing process, the second dielectric layer420on the scribe lane region SLR may further be partially removed. Therefore, the second dielectric layer420may have a second top surface420aaon the scribe lane region SLR. The second top surface420aamay be located at a lower level than that of top surfaces300aof the conductive pads300.

The processes mentioned above may eventually fabricate a wafer structure1000discussed in the embodiments ofFIGS.1A to1D.

The following will describe a semiconductor device and a dicing process that is performed on a wafer structure according to some embodiments.

FIG.3Aillustrates a cross-sectional view taken along line II-II′ ofFIG.1B, showing a dicing process performed on a wafer structure according to some embodiments.FIG.3Billustrates an enlarged view showing section III ofFIG.3A.FIG.3Cillustrates a cross-sectional view showing a semiconductor device fabricated according to some embodiments.

Referring back toFIG.1C, a wafer structure1000may be prepared. As discussed above, the wafer structure1000may include the semiconductor substrate100, the solder balls150, the circuit layer110, the through vias200, the conductive pads300, the first, second, and third dielectric layers410,420, and430, the etch stop patterns510, and the alignment key pattern520.

Referring toFIGS.3A to3C, a dicing process may be performed such that the semiconductor substrate100, the circuit layer110, the first dielectric layer410, the second dielectric layer420, and the alignment key pattern520may be diced along the dicing region R1of the scribe lane region SLR. The dicing process may be executed by using a mechanical tool, such as a blade. Therefore, the dicing process may remove the semiconductor substrate100, the circuit layer110, the first dielectric layer410, the second dielectric layer420, and the alignment key pattern520that are formed on the dicing region R1. The presence of the dummy region R2may prevent or mitigate damage to components of the chip region CR in the dicing process. For example, it may be possible to prevent or mitigate damage to the integrated circuits125, the through vias200, the conductive pads300, the wiring structures113, and the lower conductive pads130.

As a result of the dicing process, semiconductor devices10may be formed which are separated from each other. As shown inFIG.1C, each of the semiconductor devices10may include one of the chip regions CR of the semiconductor substrate100. Each of the semiconductor devices10may include the circuit layer110, the solder balls150, the through vias200, the conductive pads300, the first, second, and third dielectric layers410,420, and430, and the etch stop pattern510that correspond to the chip region CR. In addition, each of the semiconductor devices10may include a corresponding dummy region R2, and may also include the circuit layer110and the first, second, and third dielectric layers410,420, and430on the dummy region R2. After the dicing process, a portion of the alignment key pattern520may remain on the dummy region R2to form a dummy dielectric pattern521. The dummy dielectric pattern521may be a dummy alignment key pattern. A portion of the dummy dielectric pattern521may be exposed, or not covered by the dielectric layers410,420, and430, on a sidewall of the semiconductor device10. The sidewall of the semiconductor device10may be a cutting surface. The first and second dielectric layers410and420may have their sidewalls that expose a sidewall of the alignment key pattern520. When viewed in plan, the dummy region R2of the semiconductor substrate100may correspond to an edge region of the semiconductor device10. The chip region CR may surround the dummy region R2of the semiconductor substrate100.

At least a portion of the second top surface420aaof the second dielectric layer420may remain on the dummy region R2. A level difference between the top surfaces300aof the conductive pads300and the second top surface420aaof the second dielectric layer420on the dummy region R2may be less than the level difference A between the top surfaces300aof the conductive pads300and the second surface100bof the second dielectric layer420discussed inFIG.1C.

When the alignment key pattern520includes metal, a metal residue may be formed after the dicing process. It may be difficult to remove the metal residue. According to some embodiments, because the alignment key pattern520includes a silicon-based dielectric material, and because no conductive component is provided on the scribe lane region SLR, there may be no occurrence of metal residue. Therefore, the semiconductor devices10may be fabricated in high yield and may have increased reliability.

When the alignment key pattern520includes metal, a dicing tool may be damaged. According to some embodiments, the alignment key pattern520may have strength less than that of metal. Therefore, the dicing tool may be prevented or reduced from damage.

Through the processes mentioned above, the semiconductor device10may be eventually fabricated. The semiconductor device10may be a semiconductor chip.

The following will describe a bonding process and a semiconductor package fabrication method according to some embodiments.

FIGS.4A,4B,4D,4F, and4Gillustrate cross-sectional views showing a method of fabricating a semiconductor device according to some embodiments.FIG.4Billustrates an enlarged view showing section IV ofFIG.4A.FIG.4Eillustrates an enlarged view showing section V ofFIG.4D.

Referring toFIGS.4A to4C, semiconductor chips10X may be bonded to a top surface of the wafer structure1000. The wafer structure1000may be first prepared. The wafer structure1000may be substantially the same as that discussed with reference toFIGS.1A to1D. For example, the wafer structure1000may include a substrate, the circuit layer110, the lower conductive pads130, the through vias200, the conductive pads300, the first, second, and third dielectric layers410,420, and430, and the dielectric patterns500. The dielectric patterns500may include the alignment key pattern520and the etch stop patterns510.

As discussed in the embodiments ofFIGS.3A and3B, the semiconductor chips10X may be the semiconductor devices10formed by dicing the wafer structure1000. Each of the semiconductor chips10X may include a first semiconductor substrate100X, a first circuit layer110X, first lower conductive pads130X, first through vias200X, first conductive pads300X, a first upper dielectric layer410X, a second upper dielectric layer420X, a third upper dielectric layer430X, and first dielectric patterns500X. The first semiconductor substrate100X, the first circuit layer110X, the first lower conductive pads130X, the first through vias200X, the first conductive pads300X, the first upper dielectric layer410X, the second upper dielectric layer420X, the third upper dielectric layer430X, and the first dielectric patterns500X may be correspondingly substantially the same as the semiconductor substrate100, the circuit layer110, the lower conductive pads130, the through vias200, the conductive pads300, the first dielectric layer410, the second dielectric layer420, the third dielectric layer430, and the dielectric patterns500discussed in the embodiments ofFIGS.3B and3C. The first dielectric patterns500X may include a first dummy dielectric pattern521X and a first etch stop pattern510X. The first dummy dielectric pattern521X and the first etch stop pattern510X may be respectively the same as the dummy dielectric pattern521and the etch stop pattern510discussed in the embodiments ofFIGS.3B and3C. The semiconductor chips10X may not include the solder balls150. The semiconductor chips10X may be first semiconductor chips11X.

The first semiconductor chips11X may be disposed and bonded. According to some embodiments, the first semiconductor chips11X may be directly disposed on corresponding chip regions CR at the top surface of the wafer structure1000. The first semiconductor chips11X and the wafer structure1000may be provided with heat or pressure to perform a bonding process of the first semiconductor chips11X. Therefore, the first semiconductor chips11X and the wafer structure1000may be connected in a direct bonding mode. For example, the conductive pads300of the wafer structure1000may be directly bonded to the first lower conductive pads130X of the first semiconductor chips11X. The first lower conductive pads130X may be vertically aligned with the conductive pads300. The heat or pressure may induce diffusion of metal elements between the conductive pads300and the first lower conductive pads130X such that indistinct interfaces may be provided between the conductive pads300and the first lower conductive pads130X, but the present inventive concepts are not limited thereto. The first circuit layer110X of each of the first semiconductor chips11X may be directly bonded to the second dielectric layer420of the wafer structure1000. For example, the first circuit layer110X may include first dielectric layers111X and first wiring structures113X. The first dielectric layers111X and the first wiring structures113X may be substantially the same as the dielectric layers111and the wiring structures113discussed inFIG.1C. A lowermost first dielectric layer111X may be directly bonded to the second dielectric layer420. A chemical bond may be formed between a bottom surface of the lowermost first dielectric layer111X and the first top surface420aof the second dielectric layer420. The chemical bond may include a covalent bond. The second top surface420aaof the second dielectric layer420may be located at a lower level than that of the first top surface420aof the second dielectric layer420, and may be spaced apart from the semiconductor chips10X.

FIG.4Cillustrates an enlarged cross-sectional view of section IV depicted inFIG.4A, showing a direct bonding between a semiconductor chip and a wafer structure according to some embodiments. The following description ofFIG.4Cwill focus on a single semiconductor chip, a single conductive pad, and a single first lower conductive pad.

Referring toFIG.4C, the first semiconductor chip11X and the wafer structure1000may be directly bonded to each other. The first lower conductive pad130X may not be vertically aligned with the conductive pad300. For example, the first lower conductive pad130X may be offset in a horizontal direction from the conductive pad300. The first lower conductive pad130X may have an edge region whose bottom surface is in direct contact with the second dielectric layer420.

Referring back toFIG.4A, when the first semiconductor chips11X include metal residues, a poor bonding may be provided between the first semiconductor chips11X and the wafer structure1000. For example, the metal residues may cause the occurrence of voids between the first semiconductor chips11X and the wafer structure1000or the first semiconductor chips11X may be delaminated from the wafer structure1000. According to some embodiments, as discussed inFIGS.3A and3B, because the dummy dielectric pattern521includes a silicon-based dielectric material, and because no conductive component is provided on the scribe lane region SLR, there may be no occurrence of metal residue. Therefore, the first semiconductor chips11X may be satisfactorily bonded to the wafer structure1000.

Referring toFIGS.4D and4E, the placement and bonding of the semiconductor chips10X may be repeatedly performed. The placement and bonding of the semiconductor chips10X may be performed by substantially the same method as that discussed in the embodiments ofFIGS.4A and4B.

According to some embodiments, the semiconductor chips10X may include first semiconductor chips11X and second semiconductor chips12X. The second semiconductor chips12X may have their components substantially the same as those of the first semiconductor chips11X. Each of the second semiconductor chips12X may include the first semiconductor substrate100X, the first circuit layer110X, the first lower conductive pads130X, the first through vias200X, the first conductive pads300X, the first upper dielectric layer410X, the second upper dielectric layer420X, the third upper dielectric layer430X, and the first dielectric patterns500X.

The second semiconductor chips12X may be directly disposed on the first semiconductor chips11X. The first semiconductor chips11X and the second semiconductor chips12X may be provided with heat or pressure to perform a bonding process of the second semiconductor chips12X. Therefore, the first semiconductor chips11X and the second semiconductor chips12X may be connected in a direct bonding mode. For example, as shown inFIG.4E, the first conductive pads300X of the first semiconductor chips11X may be directly bonded to the first lower conductive pads130X of the second semiconductor chips12X. The first conductive pads300X of the first semiconductor chips11X may be vertically aligned with the first lower conductive pads130X of the second semiconductor chips12X. Alternatively, the first conductive pads300X of the first semiconductor chips11X may be offset in a horizontal direction from the first lower conductive pads130X of the second semiconductor chips12X.

The first circuit layer110X of the second semiconductor chip12X may be directly bonded to the first dielectric layer410of the first semiconductor chip11X. For example, a lowermost first dielectric layer111X of the second semiconductor chip12X may be directly bonded to the second upper dielectric layer420X of the first semiconductor chip11X. A chemical bond may be formed between the lowermost first dielectric layer111X and the second upper dielectric layer420X.

Before the bonding process ofFIGS.4D and4Eand the dicing process ofFIGS.3A and3B, as discussed in the examples of the second dielectric layer420and the conductive pads300inFIG.1C, a level difference (see A ofFIG.1C) may be provided between the second top surface420aaof the second upper dielectric layer420X and the top surfaces300aof the conductive pads300. When the level difference A is greater than about 0.1 μm, after the bonding process, the second top surface420aaof the second upper dielectric layer420X in each of the first semiconductor chips11X may not be in contact with the lowermost first dielectric layer111X of the second semiconductor chip12X that corresponds to the first semiconductor chip11X. According to some embodiments, because before the bonding process the level difference A of less than about 0.1 μm is provided between the second top surface420aaof the second upper dielectric layer420X and the top surfaces300aof the conductive pads300, the second top surface420aaof the second upper dielectric layer420X in each of the first semiconductor chips11X may be, after the bonding process, in contact with the lowermost first dielectric layer111X of the second semiconductor chip12X that corresponds to the first semiconductor chip11X. Therefore, the first top surface420aand the second top surface420aaof the second upper dielectric layer420X in each of the first semiconductor chips11X may be satisfactorily directly bonded to the lowermost first dielectric layer111X of the second semiconductor chip12X.

Referring back toFIG.4D, the semiconductor chips10X may further include third semiconductor chips13X. The third semiconductor chips13X may have their components substantially the same as those of the first semiconductor chips11X. For example, each of the third semiconductor chips13X may include the first semiconductor substrate100X, the first circuit layer110X, the first lower conductive pads130X, the first through vias200X, the first conductive pads300X, the first upper dielectric layer410X, the second upper dielectric layer420X, the third upper dielectric layer430X, and the first dielectric patterns500X.

The third semiconductor chips13X may be directly disposed on the second semiconductor chips12X. The second semiconductor chips12X and the third semiconductor chips13X may be connected in a direct bonding mode. For example, the first conductive pads300X of the second semiconductor chips12X may be directly bonded to the first lower conductive pads130X of the third semiconductor chips13X. The first circuit layer110X of each of the third semiconductor chips13X may be directly bonded to the second upper dielectric layer420X of the second semiconductor chip12X. A chemical bond may be formed between a dielectric layer (not shown) of the first circuit layer110X in each of the third semiconductor chips13X and the second upper dielectric layer420X of the second semiconductor chip12X that corresponds to the third semiconductor chip13X.

The number of stacked semiconductor chips10X may be variously changed.

Upper semiconductor chips10Y may be stacked on the semiconductor chips10X. Each of the upper semiconductor chips10Y may include a second semiconductor substrate100Y and a second circuit layer110Y. The second semiconductor substrate100Y, the second circuit layer110Y, and the second lower conductive pads130Y may be correspondingly similar to the semiconductor substrate100, the circuit layer110, and the lower conductive pads130ofFIG.3C. The upper semiconductor chips10Y may include none of the conductive pads300, the through vias200, the first, second, and third dielectric layers410,420, and430, and the dielectric patterns500that are discussed in the examples of the semiconductor device10inFIG.3C.

The upper semiconductor chips10Y may be directly disposed on the third semiconductor chips13X. The upper semiconductor chips10Y and the third semiconductor chips13X may be connected in a direct bonding mode. For example, the first conductive pads300X of the third semiconductor chips13X may be directly bonded to the second lower conductive pads130Y of the upper semiconductor chips10Y. A dielectric layer (not shown) included in the second circuit layer110Y of the upper semiconductor chip10Y may be directly bonded to the second upper dielectric layer420X of the third semiconductor chip13X.

Referring toFIG.4F, a first molding layer30may be formed on the wafer structure1000to cover sidewalls of the first, second, and third semiconductor chips11X,12X, and13X and also to cover sidewalls of the upper semiconductor chips10Y. The first molding layer30may expose top surfaces of the upper semiconductor chips10Y. The first molding layer30may be formed in a wafer level. The first molding layer30may include a dielectric polymer, such as an epoxy-based molding compound.

Referring toFIG.4G, a dicing process may be performed such that the wafer structure1000and the first molding layer30may be diced along the dicing region R1of the wafer structure1000. For example, the dicing process may dice the semiconductor substrate100, the circuit layer110, the first dielectric layer410, the second dielectric layer420, and the alignment key pattern520of the wafer structure1000. The dicing process may be executed by a method substantially the same as that discussed above in the embodiments ofFIGS.3A and3B.

As a result of the dicing process, there may be formed a plurality of separated chip stacks1and a plurality of separated semiconductor devices10. Each of the chip stacks1may include the semiconductor device10, the first, second, and third semiconductor chips11X,12X, and13X, the upper semiconductor chip10Y, and the diced first molding layer30. The semiconductor devices10may be substantially the same as that discussed in the embodiment ofFIG.1C. For example, each of the semiconductor devices10may include one of the chip regions CR of the semiconductor substrate100, the circuit layer110, the solder balls150, the through vias200, the conductive pads300, the first, second, and third dielectric layers410,420, and430, and the etch stop pattern510. In addition, each of the semiconductor devices10may include the dummy region R2of the semiconductor substrate100, the circuit layer110on the dummy region R2, and the first, second, and third dielectric layers410,420, and430. After the dicing process, a portion of the alignment key pattern520may remain on the dummy region R2to form a dummy dielectric pattern521. Therefore, the semiconductor devices10may be fabricated. The semiconductor devices10may be semiconductor chips, such as logic chips or buffer chips. For example, the semiconductor devices10may control its corresponding first, second, and third semiconductor chips11X,12X, and13X and its corresponding upper semiconductor chips10Y.

FIG.5Aillustrates a cross-sectional view showing a semiconductor package according to some embodiments.

Referring toFIG.5A, a semiconductor package may include a substrate40, solder terminals50, and a chip stack1.

The substrate40may be, for example, an interposer substrate. The substrate40may include an interposer die41, via structures45, a wiring layer42, and substrate pads43. The substrate40may not include an integrated circuit such as transistors. The interposer die41may include a semiconductor die, such as a silicon die, a germanium die, or a silicon-germanium die. The via structures45may be provided in the interposer die41. The via structures45may include a conductive material, such as metal. The via structures45may be laterally spaced apart from each other. The via structures45may penetrate top and bottom surfaces of the interposer die41.

The wiring layer42may be provided on the top surface of the interposer die41. The wiring layer42may include an interposer dielectric layer42X and metal patterns42Y. The interposer dielectric layer42X may include a plurality of layers. The interposer dielectric layer42X may include a silicon-based dielectric material. The metal patterns42Y may be provided in the interposer dielectric layer42X. The metal patterns42Y may include metal lines and metal vias. The metal vias may be connected to the metal patterns. The metal patterns42Y may include metal, such as one or more of copper, tungsten, titanium, and any alloy thereof.

The substrate pads43may be provided on a top surface of the substrate40. For example, the substrate pads43may be provided on and coupled to the metal patterns42Y. Two of the substrate pads43may be electrically connected to each other through their corresponding metal patterns42Y. Others of the substrate pads43may be electrically connected through corresponding metal patterns42Y to the via structures45. The phrase “electrically connected to the substrate40” may mean that “electrically connected to at least one of the metal patterns42Y.”

The substrate40may be provided on its bottom surface with the solder terminals50coupled to the via structures45. The solder terminals50may include solder balls. The solder balls may include a solder material, for example, one or more of tin (Sn), silver (Ag), zinc (Zn), and any alloy thereof. The substrate40may further include solder pads47. The solder pads47may be interposed between the solder terminals50and the via structures45. The solder pads47may include metal different from that of the solder terminals50.

The chip stack1may be fabricated by a method discussed in the embodiments ofFIGS.4A to4G. The chip stack1may include the semiconductor device10, the solder balls150, the first, second, and third semiconductor chips11X,12X, and13X, the upper semiconductor chip10Y, and the first molding layer30. The chip stack1may be mounted on the top surface of the substrate40. The solder balls150may be bonded to the substrate pad43, and thus the chip stack1may be electrically connected to the substrate40.

The semiconductor package may further include a fourth semiconductor chip20. The fourth semiconductor chip20may be of a different type from the semiconductor device10, the first, second, and third semiconductor chips11X,12X, and13X, and the upper semiconductor chip10Y. The fourth semiconductor chip20may include a logic chip, a buffer chip, or a system-on-chip (SOC). For example, the fourth semiconductor chip20may be a logic chip whose function is different from that of the semiconductor device10. The fourth semiconductor chip20may be an application specific integrated circuit (ASIC) chip or an application processor (AP) chip. The fourth semiconductor chip20may include a central processing unit (CPU) or a graphic processing unit (GPU). The fourth semiconductor chip20may include chip pads21on a bottom surface thereof.

The substrate40and the fourth semiconductor chip20may be provided therebetween with connection solders152coupled to their corresponding substrate pads43and their corresponding chip pads21. The connection solders152may include a solder material.

The semiconductor package may further include a second molding layer33. The substrate40may be provided thereon with the second molding layer33that covers sidewalls of the chip stack1and sidewalls of the fourth semiconductor chip20. The second molding layer33may expose a top surface of the chip stack1and a top surface of the fourth semiconductor chip20. The second molding layer33may include a dielectric polymer, such as an epoxy-based molding compound.

FIG.5Billustrates a cross-sectional view showing a semiconductor package according to some embodiments. A duplicate description will be omitted below.

Referring toFIG.5B, a semiconductor package may include a substrate40, solder terminals50, a chip stack1, a fourth semiconductor chip20, and a second molding layer33.

The chip stack1may include the semiconductor device10, the first, second, and third semiconductor chips11X,12X, and13X, the upper semiconductor chip10Y, and the first molding layer30. The chip stack1may not include the solder balls150discussed inFIG.4G. The chip stack1and the substrate40may be connected in a direct bonding mode. For example, the lower conductive pads130of the semiconductor device10may be directly bonded to corresponding substrate pads43. The circuit layer110of the semiconductor device10may be in direct contact with and directly bonded to the interposer dielectric layer42X. A chemical bond may be provided between the interposer dielectric layer42X and the lowermost dielectric layer (see111ofFIG.1C) of the circuit layer110in the semiconductor device10. The interposer dielectric layer42X may include silicon oxide or silicon carbonitride.

The fourth semiconductor chip20may further include a lower dielectric layer22on the bottom surface thereof. The lower dielectric layer22may include a silicon-based dielectric material, such as silicon oxide or silicon carbonitride. The fourth semiconductor chip20and the substrate40may be connected in a direct bonding mode. For example, the chip pads21of the fourth semiconductor chip20may be directly bonded to corresponding substrate pads43. The lower dielectric layer22may be directly bonded to the interposer dielectric layer42X. A chemical bond may be provided between the lower dielectric layer22and the interposer dielectric layer42X.

FIGS.6A and6Billustrate cross-sectional views showing a method of bonding a wafer structure and a method of fabricating a semiconductor device according to some embodiments.

Referring toFIG.6A, a wafer structure1000and a first wafer structure1000X may be prepared. The wafer structure1000may be substantially the same as that discussed in the embodiments ofFIGS.1A to1D.

The first wafer structure1000X may be substantially the same as the wafer structure1000discussed inFIGS.1A to1D. For example, the first wafer structure1000X may include a first semiconductor substrate100X, a first circuit layer110X, first lower conductive pads130X, first through vias200X, first conductive pads300X, a first upper dielectric layer410X, a second upper dielectric layer420X, a third upper dielectric layer430X, and first dielectric patterns500X. The first dielectric patterns500X may include a first etch stop pattern510X and a first alignment key pattern520X. The first wafer structure1000X may not include the solder balls150.

The first wafer structure1000X and the wafer structure1000may be connected in a direct bonding mode. The direct bonding between the first wafer structure1000X and the wafer structure1000may be performed by a method substantially the same as that discussed in the examples of the direct bonding between the first semiconductor chips11X and the wafer structure1000ofFIGS.4A to4C. For example, the first lower conductive pads130X of the first wafer structure1000X may be directly bonded to the conductive pads300of the wafer structure1000. The first circuit layer110X may be directly bonded to the second dielectric layer420. For example, a chemical bond may be formed between the second dielectric layer420and the lowermost dielectric layer111included in the first circuit layer110X.

Referring toFIG.6B, a dicing process may be performed such that the wafer structure1000and the first wafer structure1000X may be diced along the dicing region R1of the wafer structure1000. The dicing process may be executed by a method substantially the same as that discussed above in the embodiments ofFIGS.3A and3B.

The wafer structure1000may be diced to form semiconductor devices10that are separated from each other. A portion of the alignment key pattern520may remain on the dummy region R2to form a dummy dielectric pattern521. Each of the semiconductor devices10may be substantially the same as the semiconductor device10ofFIG.1C. For example, each of the semiconductor devices10may include the semiconductor substrate100, the solder balls150, the circuit layer110, the lower conductive pads130, the through vias200, the conductive pads300, the first, second, and third dielectric layers410,420, and430, the etch stop pattern510, and the dummy dielectric pattern521.

The first wafer structure1000X may be diced to form semiconductor chips10X that are separated from each other. After the dicing process, a portion of the first alignment key pattern520X may remain on the dummy region R2to form a dummy dielectric pattern521X. Each of the semiconductor chips10X may include the first semiconductor substrate100X, the first circuit layer110X, the first lower conductive pads130X, the first through vias200X, the first conductive pads300X, the first, second, and third upper dielectric layers410X,420X, and430X, the first etch stop pattern510X, and the first dummy dielectric pattern521X.

The semiconductor chips10X may be directly bonded to the semiconductor devices10.

According to some embodiments of the present inventive concepts, a wafer structure may include a dielectric pattern. The dielectric pattern may include an alignment key pattern and an etch stop pattern. Therefore, metal residues may be prevented or reduced from being generated in a dicing process performed on the wafer structure. A semiconductor device may be fabricated in high yield and may have increased reliability.

A dicing tool may be prevented or reduced from damage during the dicing process.

When the terms “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value include a tolerance of ±10% around the stated numerical value. When ranges are specified, the range includes all values therebetween such as increments of 0.1%.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it may be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. It will further be understood that when an element is referred to as being “on” another element, it may be above or beneath or adjacent (e.g., horizontally adjacent) to the other element.

It will be understood that elements and/or properties thereof (e.g., structures, surfaces, directions, or the like), which may be referred to as being “perpendicular,” “parallel,” “coplanar,” or the like with regard to other elements and/or properties thereof (e.g., structures, surfaces, directions, or the like) may be “perpendicular,” “parallel,” “coplanar,” or the like or may be “substantially perpendicular,” “substantially parallel,” “substantially coplanar,” respectively, with regard to the other elements and/or properties thereof.

Elements and/or properties thereof (e.g., structures, surfaces, directions, or the like) that are “substantially perpendicular” with regard to other elements and/or properties thereof will be understood to be “perpendicular” with regard to the other elements and/or properties thereof within manufacturing tolerances and/or material tolerances and/or have a deviation in magnitude and/or angle from “perpendicular,” or the like with regard to the other elements and/or properties thereof that is equal to or less than 10% (e.g., a. tolerance of ±10%).

Elements and/or properties thereof (e.g., structures, surfaces, directions, or the like) that are “substantially parallel” with regard to other elements and/or properties thereof will be understood to be “parallel” with regard to the other elements and/or properties thereof within manufacturing tolerances and/or material tolerances and/or have a deviation in magnitude and/or angle from “parallel,” or the like with regard to the other elements and/or properties thereof that is equal to or less than 10% (e.g., a. tolerance of ±10%)

This detailed description of the present inventive concepts should not be construed as limited to the embodiments set forth herein, and it is intended that the present inventive concepts cover the various combinations, the modifications and variations of the inventive concepts without departing from the spirit and scope of the present inventive concepts.