Patent ID: 12250002

In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing.

DESCRIPTION OF THE EMBODIMENTS

Technical terms of the disclosure are based on general definition in the technical field of the disclosure. If the disclosure describes or explains one or some terms, definition of the terms is based on the description or explanation of the disclosure. Each of the disclosed embodiments has one or more technical features. In possible implementation, one skilled person in the art would selectively implement part or all technical features of any embodiment of the disclosure or selectively combine part or all technical features of the embodiments of the disclosure.

FIG.1shows a functional block diagram of a successive-approximation register (SAR) analog-digital converter (ADC) according to one embodiment of the application. As shown inFIG.1, the SAR ADC100according to one embodiment of the application includes a sample-hold circuit110, a DAC (digital-to-analog converter)120, a comparator130, a SAR combinational digital circuit group140, a multiplexer circuit150and a plurality of registers160. The registers160are for example but not limited by, D-type flip-flops.

The sample-hold circuit110samples an input voltage VI based on a system clock CLK to generate a sample-hold output signal vsh and sends to the comparator130.

The DAC120receives a reference voltage REF. The DAC120generates a DAC output signal vdac under control of the multiplexer output signals b[N:1] of the multiplexer circuit150and sends to the comparator130. The reference voltage REF input to the DAC120defines a Least Significant Bit (LSB) of a voltage. For example but not limited by, when the DAC120is a N-bit binary DAC, then LSB=REF/(2{circumflex over ( )}N).

The comparator130is coupled to the sample-hold circuit110and the DAC120. The comparator130compares the sample-hold output signal vsh with the DAC output signal vdac to generate a comparing output signal dcomp. The comparing output signal dcomp of the comparator130is registered in the registers160to output as register output signals d[i], i=N˜1.

The SAR combinational digital circuit group140is coupled to the registers160. The SAR combinational digital circuit group140generates a plurality of first SAR output signals x[N:1] and a plurality of second SAR output signals y[N:1] based on the register output signals d[i:1] from the registers160. The SAR combinational digital circuit group140includes a first SAR combinational digital circuit140-1and a second SAR combinational digital circuit140-2. The first SAR combinational digital circuit140-1and the second SAR combinational digital circuit140-2are coupled to the registers160. The first SAR combinational digital circuit140-1generates the first SAR output signals x[N:1] based on the register output signals d[i−1:1] from the registers160; and the second SAR combinational digital circuit140-2generates the second SAR output signals y[N:1] based on the register output signals d[i−1:1] from the registers160.

The multiplexer circuit150is coupled to the DAC120, the SAR combinational digital circuit group140and the registers160. The multiplexer circuit150outputs a plurality of multiplexer output signals b[N:1] to the DAC120based on the first SAR output signals x[N:1], the second SAR output signals y[N:1] and the register output signals d[i] from the registers160. A capacitor coupling relationship of the DAC120is controlled by the multiplexer output signals b[N:1].

The registers160output the register output signals d[N:1] as an output signal ADC_OUT of the SAR ADC100, wherein ADC_OUT=d[N:1].

FIG.2shows detailed function block diagram of the SAR combinational digital circuit group of the SAR ADC according to one embodiment of the application. The first SAR combinational digital circuit140-1includes a plurality of SAR units140-1-1˜140-1-4and a plurality of switches SW1˜SW8. The second SAR combinational digital circuit140-2includes a plurality of SAR units140-2-1˜140-2-4and a plurality of switches SW9˜SW16. The SAR units140-1-1˜140-1-4and140-2-1˜140-2-4are for example but not limited by XOR logic gates.

The SAR units140-1-1˜140-1-4generate a plurality of SAR intermediate output signals based on the register output signal d[i] from the registers160and a first reference value (for example but not limited by logic 0). The switches SW1˜SW8are controlled by the SAR intermediate output signals from the SAR unit140-1-1˜140-1-4to conduct the comparing output signals or the first reference value as the first SAR output signals, or pulls high or low the first SAR output signals. When the switches SW1and SW3are conducted, x[1]=d[1]; and when the switches SW5and SW7are conducted, x[1]=0. When the switches SW2and SW4are conducted, x[1]=L (pulling low); and when the switches SW6and SW8are conducted, x[1]=H (pulling high). For example but not limited by, when the SAR intermediate output signal from the SAR unit140-1-1is logic 1, the switch SW1is disconnected while the switch SW2is conducted. When the SAR intermediate output signal of the SAR unit140-1-1is logic 0, the switch SW1is conducted while the switch SW2is disconnected. Operations of the switches SW3˜SW8are similar.

The SAR units140-2-1˜140-2-4generate the SAR intermediate output signals based on the register output signals d[i] from the registers160and a second reference value (for example but not limited by logic 1). The switches SW9˜SW16are controlled by the SAR intermediate output signals from the SAR units140-2-1˜140-2-4, to conduct the comparing output signals or the second reference value as the second SAR output signals, or pull high or low the second SAR output signals. For example but not limited by, when the SAR intermediate output signal from the SAR unit140-2-1is logic 1, the switch SW9is disconnected while the switch SW10is conducted. When the SAR intermediate output signal from the SAR unit140-2-1is logic 0, the switch SW9is conducted while the switch SW10is disconnected. Operations of the switches SW11˜SW16are similar.

When the switch SW1is conducted and the switch SW2is disconnected, the first SAR output signal x[1] is the register output signal d[1] from the registers160. When the switch SW1is disconnected and the switch SW2is conducted, the first SAR output signal x[1] is logic 0. Generation of the first SAR output signals x[N:1] and the second SAR output signals y[N:1] are similar.

FIG.3shows operations of the SAR ADC according to one embodiment of the application. The multiplexer circuit150includes a plurality of switches SW17˜SW24, wherein the switches SW17˜SW24are controlled by the register output signal d[2] or d[3] of the registers160. Taking the switches SW17and SW18as an example, when the register output signal d[2] is logic 1, the switch SW17is conducted and the switch SW18is disconnected. When the register output signal d[2] is logic 0, the switch SW17is disconnected and the switch SW18is conducted. Operations of the switches SW19-SW24are similar. When the switch SW17is conducted and the switch SW18is disconnected, the multiplexer circuit150selects the first SAR output signal x[1] as the multiplexer output signal b[1]. When the switch SW17is disconnected and the switch SW18is conducted, the multiplexer circuit150selects the second SAR output signal y[1] as the multiplexer output signal b[1].

Further, in one embodiment of the application, the SAR ADC100further includes a switch SW25coupled to the DAC120. The switch SW25resets the DAC output signal vdac to a common voltage VCM based on a control signal rst. For example but not limited by, when the control signal rst is logic high, the switch SW25is conducted to reset the DAC output signal vdac to the common voltage VCM. When the control signal rst is logic low, the switch SW25is disconnected.

The DAC120includes a plurality of capacitors c[1]˜c[4]. Coupling relationship of the capacitors c[1]˜c[4] are controlled by the multiplexer output signals b[1]˜b[4]. For example but not limited by, when the multiplexer output signal b[1] is logic high, the capacitor c[1] is coupled to a reference voltage (not shown); and when the multiplexer output signal b[1] is logic low, the capacitor c[1] is coupled to a ground terminal.

Further, the registers160receive clock signals clk1˜clk4. The registers160are further controlled by the control signal rst. For example but not limited by, a first register160among the registers160receives the clock signal clk1, and when the control signal rst is logic low, the first register160among the registers160outputs the register output signal d[1] to the SAR units140-1-1˜140-1-4and the SAR units140-2-1˜140-2-4. A second register160among the registers160receives the clock signal clk2, and when the control signal rst is logic high, the second register160among the registers160outputs the register output signal d[2] to the SAR units140-1-1˜140-1-4and the SAR units140-2-1˜140-2-4. A third register160among the registers160receives the clock signal clk3, and when the control signal rst is logic high, the third register160among the registers160outputs the register output signal d[3] to the SAR units140-1-1˜140-1-4and the SAR units140-2-1˜140-2-4. A fourth register160among the registers160receives the clock signal clk4, and when the control signal rst is logic high, the fourth register160among the registers160outputs the register output signal d[4] to the SAR units140-1-1˜140-1-4and the SAR units140-2-1˜140-2-4.

FIG.4shows a signal timing diagram of the SAR ADC according to one embodiment of the application. Referring toFIG.3andFIG.4to show operations of the SAR ADC according to one embodiment of the application.

Here, the SAR ADC100is a 4-bit ADC (N=4), which is an example but not to limit the application.

At the timing T1, the system clock CLK is CLK=H and the control signal rst is rst=H. When system clock CLK=H, the sample-hold circuit110samples the input voltage VI; and in response to rst=H, the registers160are reset and thus the registers160generate d[4:1]=[1,1,0,0]. Therefore, x[4:1]=[0,0,0,0], y[4:1]=[1,1,0,0], b[4:1]=[1,1,0,0]. When the control signal rst is logic high, the switch SW25is conducted to reset the DAC output signal dac to the common voltage VCM.

At the timing T2, the system clock CLK is CLK=L and the control signal rst is rst=L. The sample-hold circuit110stops sampling and generates the sample-hold output signal vsh to the comparator130. The comparator clock signal CLK_comp transits to logic low, and the comparator130performs a first comparison and updates the comparing output signal dcomp to decide the multiplexer output signal b[2,1]. The comparing output signal dcomp output at the first comparison is dcomp=d[1].

In one embodiment of the application, another inputs of the SAR units140-1-1˜140-1-4are fixed as logic 0; and another inputs of the SAR units140-2-1˜140-2-4are fixed as logic 1. At the timing T2, when d[1]=L, because another inputs of the SAR units140-1-1˜140-1-4and140-2-1˜140-2-4are fixed as logic 0 and logic 1, thus x[4:1]=[0,0,0,0], y[4:1]-[1,1,0,0]. Because at the timing T2, d[2:3] is still the reset value (i.e. logic 1), b[4:1]=y[4:1]=[1,1,0,0].

At timing T2, when d[1]=H, another inputs of the SAR units140-1-1˜140-1-4are fixed as logic 0 and thus x[4:1]=[1,1,0,0]; and another inputs of the SAR units140-2-1˜140-2-4are fixed as logic 1, and thus y[4:1]=[1, 1, 1, 1]. Because at the timing T2, d[2:3] is still the reset value (i.e. logic 1), b[4:1]=y[4:1]=[1,1,1,1].

After comparison, the comparator clock signal CLK_comp is transited to logic H.

At timing T3, the comparator clock signal CLK_comp transits to logic low again, and the comparator130performs second comparison and updates the comparing output signal dcomp to decide the output signal b[3,1]. The comparing output signal dcomp output at the second comparison is dcomp=d[2].

At timing T3, when d[2]=L and d[1]=L, because another inputs of the SAR unit140-1-1˜140-1-4and the SAR units140-2-1˜140-2-4are fixed, b[3,1]=x[3,1]=[0,0].

At timing T3, when d[2]=L and d[1]=H, because another inputs of the SAR unit140-1-1˜140-1-4and the SAR units140-2-1˜140-2-4are fixed, b[3,1]=x[3,1]=[1,0].

At timing T3, when d[2]=H and d[1]=L, because another inputs of the SAR unit140-1-1˜140-1-4and the SAR units140-2-1˜140-2-4are fixed, b[3,1]=y[3,1]=[1,0].

At timing T3, when d[2]=H and d[1]=H, because another inputs of the SAR unit140-1-1˜140-1-4and the SAR units140-2-1˜140-2-4are fixed, b[3,1]=y[3,1]=[1,1].

At timing T3, because d[2] is valid, the valid comparing output signal d[2] controls the switches SW17, SW18, SW21and SW22of the multiplexer circuit150to generate the updated signals b[1] and b[3], for deciding whether to change the coupling relationship of the capacitors c[1] and c[3].

After the second comparison, the comparator clock signal CLK_comp is transited to H.

At timing T4, the comparator clock signal CLK_comp is transited to logic low, the comparator130performs third comparison, and updates the comparing output signal dcomp to decide the multiplexer output signal b[4,2]. The comparing output signal dcomp at third comparison is dcomp=d[3].

At timing T4, when d[3]=L and d[1]=L, because another inputs of the SAR unit140-1-1˜140-1-4and the SAR units140-2-1˜140-2-4are fixed b[4,2]=x[4,2]=[0,0].

At timing T4, when d[3]=L and d[1]=H, because another inputs of the SAR unit140-1-1˜140-1-4and the SAR units140-2-1˜140-2-4are fixed b[4,2]=x[4,2]=[1,0].

At timing T4, when d[3]=H and d[1]=L, because another inputs of the SAR unit140-1-1˜140-1-4and the SAR units140-2-1˜140-2-4are fixed b[4,2]=y[4,2]=[1,0].

At timing T4, when d[3]=H and d[1]=H, because another inputs of the SAR unit140-1-1˜140-1-4and the SAR units140-2-1˜140-2-4are fixed b[4,2]=y[4,2]=[1,1].

After the third comparison, the comparator clock signal CLK_comp is transited to H.

At timing T4, because the signal d[3] is valid, the valid comparing output signal d[3] controls the switches SW19, SW20, SW23and SW24of the multiplexer circuit150to generate the updated signals b[2] and b[4], to decide whether to change the coupling relationship of the capacitors c[2] and c[4].

At timing T5, the comparator clock signal CLK_comp is transited to logic low, the comparator130performs fourth comparison, and generates the comparing output signal dcomp (logic low or logic high). The comparing output signal dcomp at the fourth comparison is dcomp=d[4].

After comparing 4 bits, the registers160output ADC_OUT=d[4:1].

In prior art, limited by transmission delay of logic operations of SAR digital circuit, the prior SAR ADC has low operation speed.

In one embodiment of the application, via logic design of the SAR combinational digital circuit group140, the SAR ADC100has high operation speed.

FIG.5shows waveforms comparing the prior DAC and the DAC according to one embodiment of the application. As shown inFIG.5, when conversion is triggered, the DAC120according to one embodiment of the application is already converting while the prior DAC just begins to convert. Therefore, as shown inFIG.5, one embodiment of the application has fast operation speed.

While this document may describe many specifics, these should not be construed as limitations on the scope of an invention that is claimed or of what may be claimed, but rather as descriptions of features specific to particular embodiments. Certain features that are described in this document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable sub-combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination in some cases can be excised from the combination, and the claimed combination may be directed to a sub-combination or a variation of a sub-combination. Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results.

Only a few examples and implementations are disclosed. Variations, modifications, and enhancements to the described examples and implementations and other implementations can be made based on what is disclosed.