Patent ID: 12211800

DETAILED DESCRIPTION

Various package manufacturing flaws can impact performance and cause finished packages to fail inspection. For example, when devices such as dies and other devices are coupled to leadframes, viscous materials—particularly solder—are often used to establish the connection. The solder, however, can undesirably flow into certain areas of the package or leadframe, resulting in functional or cosmetic defects.

As another example, stamped leadframe substrates may be imprecisely planar, which can affect connections to package components with planar surfaces, such as semiconductor dies and shunts. Moreover, such leadframes are generally interference fit with a package molding die, which may result in residual stresses within finished packages which can contribute to solder cracks during reliability testing and operation of the packages.

The techniques disclosed herein, including with respect to semiconductor package100, may improve package reliability compared to prior designs by reducing or eliminating wire bond and solder connections between the die, the shunt, and the electrical contact pads and/or by replacement of a stamped leadframe with a metal trace.

FIGS.1A and1Billustrate semiconductor package100. Specifically,FIG.1Aillustrates a perspective view of semiconductor package100, andFIG.1Billustrates a cross-sectional view of semiconductor package100. Semiconductor package100includes a first layer104with a semiconductor die130and a shunt140embedded in a dielectric substrate layer128, and a second layer106stacked on first layer104. Second layer106includes metal trace sections150A-150C, representing a first metal trace150, patterned on first dielectric substrate layer128, and a second dielectric substrate layer158over first metal trace150.

Semiconductor package100also includes a base layer102opposite second layer106relative first layer104. Base layer102includes a second metal trace120patterned on first dielectric substrate layer128. Second metal trace120is opposite first metal trace150relative to semiconductor die130and shunt140. Base layer102further includes a third dielectric substrate layer118over second metal trace120. Second metal trace120electrically connects electrical contact pads112A-112E (collectively, “pads112”) to shunt140, metal pillars122A-122C (collectively, “pillars122”), and semiconductor die130. Base layer102forms exposed electrical contact pads112. Electrical contact pads112provide electrical connections to shunt140and semiconductor die130via metal traces120,150and metal pillars122.

Metal traces120,150are metal plating layers patterned on opposing sides of dielectric substrate layer128. Both of metal traces120,150are generally planar with the addition of vias that extend through dielectric substrate layer128to form electrical connections with various elements of package100. Metal pillars122extend through dielectric substrate layer128to provide electrical connections between metal traces120,150. Metal pillars, as referred to herein, may also be referred to as metal bridges in they provide electrical connections that bridge between the distinct conductive layers (metal traces120,150) of semiconductor package100.

Metal trace150includes a first section150A that electrically connects a first portion141A of surface141of shunt140to metal pillar122A, and a second section150B that electrically connects a second portion141B of surface141to a second metal pillar122B. In some examples, metal trace sections150A,150B may be used for current sensing of a load current through shunt140.

Semiconductor die130includes bond pads131providing electrical connections to its functional circuitry. Bond pads131are electrically coupled to metal trace150patterned on dielectric substrate layer128. Specifically, dielectric substrate layer128forms vias151C, which are filled with the conductive material of metal trace section150C over the bond pads, electrically connecting the functional circuitry of semiconductor die130to metal trace150. Similarly, dielectric substrate layer128forms vias151A,151B over first and second portions141A,141B of surface141of shunt140. Vias151A,151B are filled with the conductive material of metal trace sections150A,150B respectively, electrically connecting portions141A,141B of surface141of shunt140to metal trace150. Metal trace section150C connects each bond pad131to one of metal pillars122C, and to one of electrical contact pads112C via sections of metal trace120.

Metal pillars122and metal traces120,150may include any suitable pure metal or alloy such as, but not limited to, copper, copper alloys, gold, gold alloys or other metals. Electrical contact pads112may include a solderable metal and/a corrosion-resistant metal plated over a base metal layer of metal traces120.

An inactive surface of semiconductor die130is bonded to metal trace120. A dielectric film136separates inactive surface of semiconductor die130from metal trace120. Semiconductor die130comprises a substrate (e.g., silicon or silicon/germanium) having an active surface and an inactive surface. Bond pads131are exposed in bond pad openings in a dielectric layer of semiconductor die130on its active surface. Bond pads131are bonded to a metallization layer including functional circuitry (not shown) in a semiconductor substrate. The functional circuitry of semiconductor die130is formed on a semiconductor wafer prior to singulation of semiconductor die130and includes circuit elements such as transistors, diodes, capacitors, and resistors, as well as signal lines and other electrical conductors that interconnect the various circuit elements. As nonlimiting examples, such functional circuitry may include an application specific integrated circuit (ASIC), a digital signal processor, a radio frequency chip, a memory, a microcontroller and a system-on-a-chip or a combination thereof. The functional circuitry is generally integrated circuitry that realizes and carries out desired functionality of the package, such as that of a digital IC (e.g., digital signal processor) or analog IC (e.g., amplifier or power converter), such as a BiMOS IC. The capability of functional circuitry may vary, ranging from a simple device to a complex device.

Shunt140is physically and electrically connected to metal trace120. In the specific example of semiconductor package100, a thin dielectric film146separates shunt from metal trace120; however, dielectric film146includes vias121adjacent surface143of shunt140, which are filled with the conductive material of metal trace120, electrically connecting metal trace120to shunt140.

As best seen inFIG.1B, the load current path through package100includes, in order, a first electrical contact pad112D, a first section of metal trace120, shunt140, a second section of metal trace120, and a second electrical contact pad112E. Electrical contact pads112A and112B facilitate current sensing by way of their electrical connections to surface141of shunt140. For example, current sensing may include measuring a voltage drop between portions141A,141B of surface141of shunt140via electrical contact pads112A and112B.

The electrical connection between electrical contact pad112A and portion141A of surface141includes, in order, a section of metal trace120, metal pillar122A, and metal trace section150A. Likewise, the electrical connection between electrical contact pad112B and portion141B of surface141includes, in order, a section of metal trace120, metal pillar122B, and metal trace section150B. In this manner, metal pillars122and metal traces120,150provide routable three-dimensional electrical connections between semiconductor die130, shunt140and electrical contact pads112of semiconductor package100.

Each of metal trace sections150A,150B includes five connections to surface141shunt140, providing significant redundancy which improves accuracy of sensed current in case of any defects in the load current path through package100. In other examples, metal trace sections150A,150B may each provide more or less than five connections to surface141shunt140.

Dielectric substrate layers118,128,158provide protective layers covering electronics of semiconductor package100, including semiconductor die130, shunt140, and metal pillars122. Dielectric substrate layers118,128,158may be formed from a nonconductive plastic or resin material. One or more of dielectric substrate layers118,128,158may be molded components. Mold compounds suitable for use as dielectric substrate layers118,128,158include, for example, thermoset compounds that include an epoxy novolac resin or similar material combined with a filler, such as alumina, and other materials to make the compound suitable for molding, such as accelerators, curing agents, filters, and mold release agents.

FIGS.2A-2Hillustrate conceptual process steps for manufacturing semiconductor package100.FIG.3is flowchart of a method of manufacturing a multilayer package with an embedded semiconductor die additional package layers including passive components. For clarity, the techniques ofFIG.3are described with respect to semiconductor package100andFIGS.2A-2H; however, the described techniques may also be readily adapted to alternative package configurations, including packages300,400, as described with respect toFIGS.4-5B.

As represented byFIG.2A, semiconductor die130and shunt140are mounted on a carrier10, such as a metal carrier or glass carrier (FIG.3, step202). Carrier10provides support for unfinished layers of semiconductor package100during manufacturing. Adhesives, such as thermal or UV-sensitive adhesives, are used to hold semiconductor die130and shunt140to carrier10. In this example, dielectric film136secures inactive surface of semiconductor die130to carrier10and dielectric film146secures shunt140to carrier10.

As represented byFIG.2B, metal pillars122are patterned on carrier10to a height extending beyond semiconductor die130and shunt140(FIG.3, step204). In some examples, patterning metal pillars122may include plating multiple layers of metal carrier to build-up metal pillars122to the desired height.

As represented byFIG.2C, the partially assembled device ofFIG.2Bis molded, thereby covering semiconductor die130, shunt140, and metal pillars122with a dielectric substrate layer128(FIG.3, step206). Dielectric substrate layer128may encapsulate the components of first layer104, although distal ends of metal pillars122may remain exposed following molding. After molding, the process includes grinding a layer of dielectric substrate layer128to expose distal ends of metal pillars122adjacent a surface of dielectric substrate layer128(FIG.3, step208). Grinding also provide a flat surface for dielectric substrate layer128in a common plane with the exposed distal ends of metal pillars122.

As represented byFIG.2D, metal trace150is patterned over dielectric substrate layer128with metal pillars122electrically connected to metal trace150(FIG.3, step210). Vias151A,151B are drilled, chemically etched, or plasma-etched into dielectric substrate layer128to expose portions141A,141B of surface141of shunt140prior to plating metal trace150. Likewise, vias151C are drilled, chemically etched, or plasma-etched into dielectric substrate layer128to expose the bond pads on the active side of semiconductor die130prior to plating metal trace150. Drilling may include laser drilling. While laser drilling forms round depressions in dielectric substrate layer128, drilling is repeated to form any desired shape, such as trenches351A,351B, as described with respect to package300. The plating layer of metal trace150fills vias151A,151B,151C, electrically connecting portions141A,141B of surface141of shunt140and the functional circuitry of semiconductor die130to metal trace150.

As represented byFIG.2E, the partially assembled device is molded, thereby covering metal trace150with a dielectric substrate layer158(FIG.3, step212).

As represented byFIG.2F, after applying dielectric substrate layer158over metal trace150and dielectric substrate layer128, a subassembly including semiconductor die130, shunt140, metal pillars122, dielectric substrate layer128, and metal trace150is removed from carrier10(FIG.3, step214). Removing the partially assembled semiconductor package100from carrier10may include deactivating any adhesive securing semiconductor package100to carrier10, including dielectric films136,146, such as by applying UV light or heat.

As represented byFIG.2G, metal trace120is patterned over dielectric substrate layer128with metal pillars122electrically connected to metal trace120(FIG.3, step216). Vias121are drilled, chemically etched, or plasma-etched into dielectric film146to expose portions of shunt140prior to plating metal trace120. The plating layer of metal trace120fills vias121electrically connecting shunt140to metal trace120. While dielectric substrate layer128provides a planar surface conforming to carrier10, grinding may occur prior to patterning metal trace120to ensure the planarity of dielectric substrate layer128and/or to expose distal ends of metal pillars122.

As represented byFIG.2H, an additional metal layer, such as a solderable metal and/or corrosion-resistant metal is plated over metal trace120to form electrical contact pads112(FIG.3, step218). As further represented byFIG.2H, the partially assembled device is molded, thereby covering metal trace120with a dielectric substrate layer158, while leaving electrical contact pads112exposed on an outer surface of semiconductor package100(FIG.3, step220).

In some alternative examples, step212may be formed in conjunction with or after step220such that metal trace150remains exposed during patterning of metal trace120. In the same or different examples, metal trace120may be patterned before patterning metal trace150.

In some examples, semiconductor package100may be one of an array of packages manufactured on a common carrier10using common molds for one or more of dielectric substrate layers118,128,158. In such examples, the method further includes singulating the array of molded packages to form individual semiconductor packages100. Singulation may include cutting through any dielectric material linking the interconnected packages with a saw or other cutting implement.

FIG.4illustrates semiconductor package300. Semiconductor package300is substantially similar to semiconductor package100except that metal trace150has been replaced by metal trace sections350A-350C, representing a first metal trace350. Metal trace350is substantially similar to metal trace150except that metal trace sections350A,350B includes trenches351A,351B rather than vias151A,151B of metal trace sections150A,150B. Metal trace section350C is substantially similar to metal trace section150C. Metal trace section350A fills a trench351A that electrically connects a first portion141A of surface141of shunt140to metal pillar122A, and metal trace section350B fills a trench351B that electrically connects a second portion141B of surface141to a second metal pillar122B. Trenches351A,351B represent elongated vias. Trenches351A,351B may be formed by repeated laser drilling through dielectric substrate layer128to expose elongated cavities adjacent portions141A,141B of surface141in dielectric substrate layer128before plating metal trace350over dielectric substrate layer128, filling the elongated cavities with the metal of metal trace350.

Use of trenches351A,351B rather than vias151A,151B increases the contact area between metal trace sections350A,350B and shunt140. In some examples, trenches351A,351B may each extend at least half of a width of surface141. Such a design may improve sensing accuracy in the event of a defect or crack between elements of the load current path through package300. For this reason, package300may provide further resilience and redundancy for current sensing a load current through shunt140as compared to package100.

Elements of semiconductor package300with the same numbers as semiconductor package100are the same or substantially similar to those elements in semiconductor package100. For brevity, such elements are described in limited or no detail with respect to semiconductor package300.

Like semiconductor package100, semiconductor package300includes a first layer including semiconductor die130and shunt140embedded in a dielectric substrate layer128, and a second layer stacked on first layer. The second layer includes metal trace350, patterned on first dielectric substrate layer128, and a second dielectric substrate layer158over first metal trace350.

Semiconductor package300also includes a base layer with metal trace120patterned on first dielectric substrate layer128opposite first metal trace350relative to semiconductor die130and shunt140, and a third dielectric substrate layer118over second metal trace120. Second metal trace120electrically connects electrical contact pads112to shunt140, metal pillars122, and semiconductor die130. Electrical contact pads112provide electrical connections to shunt140and semiconductor die130via metal traces120,350and metal pillars122.

In this manner, metal pillars122and metal traces120,350provide routable three-dimensional electrical connections between semiconductor die130, shunt140and electrical contact pads112of semiconductor package300.

FIG.5Ashows an exploded perspective view of semiconductor package400, andFIG.5Billustrates a cross-sectional view of package400. Semiconductor package400is substantially similar to semiconductor package100with the addition of metal pillars422A,422B, to provide a redundant current path for load current through shunt140. In addition, metal trace150is replaced by metal trace sections450A-450E, representing a metal trace450. Metal trace450is substantially similar to metal trace150with the addition of metal trace sections450D,450E. Metal trace sections450A-450C are substantially similar to metal trace sections150A-150C.

Metal trace sections450D,450E include trenches453A,453B in contact with portions of surface141of shunt140outside the contact areas for vias451A,451B. Metal pillars422extend between of metal trace sections450D,450E in direct contact with surface141of shunt140and portions of second metal trace120in direct contact with a second surface143of shunt140.

As best shown inFIG.5B, metal pillars422A,422B and metal trace sections450D,450E provide a redundant load current path from electrical contact pads112D,112E through shunt140. As described with respect to package100, vias121of metal trace120provide the primary load current path from electrical contact pads112D,112E through shunt140. The redundant load current path of package400may improve sensing accuracy in the event of a defect or crack between elements of the primary load current path, including the connections between shunt140and vias121of metal trace120. For this reason, package400may provide further resilience and redundancy for current sensing a load current through shunt140as compared to package100.

In alternative examples, vias451A,451B of package400may be replaced with trenches351A,351B as described with respect to package300to provide further resilience and redundancy for current sensing a load current through shunt140.

Elements of semiconductor package400with the same numbers as semiconductor package100are the same or substantially similar to those elements in semiconductor package100. For brevity, such elements are described in limited or no detail with respect to semiconductor package400.

Like semiconductor package100, semiconductor package400includes a first layer including semiconductor die130and shunt140embedded in a dielectric substrate layer128, and a second layer stacked on first layer. The second layer includes metal trace450, patterned on first dielectric substrate layer128, and a second dielectric substrate layer158over first metal trace450.

Semiconductor package400also includes a base layer with metal trace120patterned on first dielectric substrate layer128opposite first metal trace450relative to semiconductor die130and shunt140, and a third dielectric substrate layer118over second metal trace120. Second metal trace120electrically connects electrical contact pads112to shunt140, metal pillars122,422, and semiconductor die130. Base layer102also forms exposed electrical contact pads112. Electrical contact pads112provide electrical connections to shunt140and semiconductor die130via metal traces120,450and metal pillars122,422.

In this manner, metal pillars122,422and metal traces120,450provide routable three-dimensional electrical connections between semiconductor die130, shunt140and electrical contact pads112of semiconductor package400.

The specific techniques for multilayer packages with an embedded semiconductor die and shunt with a patterned metal trace, including techniques described with respect to packages100,300,400, are merely illustrative of the general inventive concepts included in this disclosure as defined by the following claims.