Patent ID: 12230194

DETAILED DESCRIPTION

The technical schemes in embodiments of the present disclosure are described clearly and completely in conjunction with drawings in the embodiments of the present disclosure from which the schemes are better understood by those skilled in the art. Apparently, the embodiments described below are part, not all, of the embodiments of the present disclosure. Based on the embodiments described herein, all other embodiments obtained by those skilled in the art on the premise that no creative work is done are within the scope of the present disclosure.

It is to be noted that terms such as “first” and “second” in the description, claims, and drawings of the present disclosure are used to distinguish between similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that data used in this manner are interchangeable where appropriate so that the embodiments of the present disclosure described herein may also be implemented in a sequence not illustrated or described herein. In addition, terms “comprising”, “including”, and any other variations thereof are intended to encompass a non-exclusive inclusion. For example, a system, product, or device that includes a series of units not only includes expressly listed steps or units, but may also include other units that are not expressly listed or are inherent to such a product or device.

FIG.1is a schematic diagram illustrating the structure of a display panel according to an embodiment of the present disclosure.FIG.2is a section view taken along section line A-A′ ofFIG.1. Referring toFIGS.1and2, this embodiment of the present disclosure provides a display panel10. The display panel10includes a substrate100and a drive circuit200located on one side of the substrate100. The drive circuit200includes a first transistor210. The first transistor210includes a first active layer211. The first active layer211includes an oxide semiconductor. The drive circuit200also includes a first capacitor220. One capacitor plate221of the first capacitor220is disposed in the same layer as the first active layer211.

The display panel10includes a substrate100, multiple insulation layers and multiple metal layers, and the multiple insulation layers and metal layers are alternately arranged on one side of the substrate100. The drive circuit200is included in the multiple insulation layers and the multiple metal layers. Illustratively, the multiple insulation layers on the one side of the substrate100may include a buffer layer110, a first gate insulation layer120, a first interlayer insulation layer130, a second gate insulation layer140, a second interlayer insulation layer150, a third interlayer insulation layer160, and a planarization layer170. Based on the number and types of insulation layers, an adaptive adjustment may be made according to the practical display panel10. Multiple transistors and capacitor structures may be included in the drive circuit200. The number of transistors and capacitor structures is not limited in this embodiment of the present disclosure. In other words, the drive circuit200may be a pixel circuit or a shift register circuit. The type of the drive circuit200is not limited herein, and based on an adjustment on the type of the drive circuit200, the numbers and the configuration positions of transistors and capacitor structures in the drive circuit200may be adaptively adjusted.

Further, as shown inFIG.2, the drive circuit200includes the first transistor210, the first transistor210includes the first active layer211, and the first active layer211includes the oxide semiconductor. That is, the first transistor210is an oxide (indium gallium zinc oxide, IGZO) transistor, which has such advantages as low production cost and low power consumption. Additionally, the first transistor210may also include other structures such as a first gate212, a second gate213, a source214of the first transistor, and a drain215of the first transistor.

Further, the drive circuit200also includes a first capacitor220. One capacitor plate221of the first capacitor220is disposed in the same layer as the first active layer211. Disposing in the same layer herein may indicate that the first active layer211and one capacitor plate221of the first capacitor220are manufactured in the same patterning process using the same mask process. For example, a semiconductor layer is manufactured and patterned. The semiconductor layer structure retained in the configuration region of the first transistor210is the first active layer211. The structure obtained after the semiconductor layer structure retained in the configuration region of the first capacitor220is conducted by ion doping is one capacitor plate221of the first capacitor220. Although having different degrees of conductivity, the first active layer211and one capacitor plate221of the first capacitor220are both in contact with the first insulation layer130in a film structure, that is, the first active layer211and one capacitor plate221of the first capacitor220are located on the side of the first insulation layer130away from the substrate100. Disposing in the same layer can reduce a manufacturing procedure of the first capacitor220in a manufacturing process of the display panel10, and the manufacturing cost can be effectively saved. Moreover, reducing a film manufacturing procedure is conducive to achieving a thinning design of the display panel10.

Alternatively, the drive circuit200may also include a second transistor230, and the second transistor230may include a second active layer231, a third gate232, a source233of the second transistor, and a drain234of the second transistor. The second active layer231may include silicon, that is, the second transistor230is a low temperature poly silicon (LTPS) transistor, which has such advantages as high switch speed, high carrier mobility, and low power. Further, the drive circuit200provided by this embodiment of the present disclosure may combine the preceding two types of transistors, that is, the first transistor210and the second transistor230. In other words, the LTPS is combined with the IGZO to obtain the display panel technology of LTPO (low-temperature polycrystalline oxide). The LTPO display panel not only has the advantages of the LTPS display panel, such as the high resolution, high reaction speed, high brightness, and high aperture ratio, but also has the advantages of the IGZO, such as the low production cost and low power consumption.

In summary, the drive circuit of the display panel provided by this embodiment of the present disclosure includes a first transistor. A first active layer of the first transistor includes an oxide semiconductor. One capacitor plate of a first capacitor in the drive circuit may be disposed in the same layer as the first active layer. In this manner, the process for manufacturing the display panel can be reduced, the manufacturing cost of the display panel can be saved, and a thinning design of the display panel as a whole can be better achieved.

FIG.3is a schematic diagram of circuit elements in a pixel circuit according to an embodiment of the present disclosure.FIG.4is a schematic diagram illustrating the structure of another display panel according to an embodiment of the present disclosure.FIG.5is a schematic diagram of a part of the structure of the display panel ofFIG.4.FIG.6is a schematic diagram of another part of the structure of the display panel ofFIG.4.FIG.7is a schematic diagram of another part of the structure of the display panel ofFIG.4.FIG.8is a schematic diagram of another part of the structure of the display panel ofFIG.4.FIG.9is a schematic diagram of another part of the structure of the display panel ofFIG.4.FIG.10is a schematic diagram of another part of the structure of the display panel ofFIG.4. Referring toFIGS.1to10, the drive circuit200includes a pixel circuit200A, the pixel circuit200A includes a storage capacitor Cst, and one capacitor plate Cst1 of the storage capacitor Cst is electrically connected to a power signal terminal PVDD. The first capacitor220includes the storage capacitor Cst.

The drive circuit200may include the pixel circuit200A electrically connected to a light-emitting element600in the display panel10. That is, the display panel10drives the light-emitting element600to display and emit light via the pixel circuit200A to achieve a display function of the display panel10.

The pixel circuit200A includes the storage capacitor Cst electrically connected to the power supply signal terminal PVDD, as shown inFIG.3. The storage capacitor Cst is the first capacitor220, that is, a capacitor plate of the storage capacitor Cst is disposed in the same layer as the first active layer211. In this manner, the manufacturing procedure of the display panel10is reduced, the manufacturing cost of the display panel10is saved, and the thinning design of the display panel10as a whole is better achieved.

Illustratively, referring toFIG.3, a pixel circuit200A including “7T1C” is used as an example in this embodiment of the present disclosure, where “T” denotes a transistor, and “C” denotes a capacitor. “C” is the storage capacitor Cst in this embodiment of the present disclosure, that is, “C” is the first capacitor220. Alternatively, the description is made in conjunction with a structural schematic diagram and a structural circuit diagram of the pixel circuit200A. The pixel circuit200A includes a light-emitting control transistor M1, a data writing transistor M2, a drive transistor M3, a threshold compensation transistor M4, an initialization transistor M5, a second light-emitting control transistor M6, a reset transistor M7, and the storage capacitor Cst. A first scan signal line SN-1 controls the initialization transistor M5 of the drive circuit to be turned on and off. When the initialization transistor M5 is turned on, the gate potential of the drive transistor M3 is reset, that is, a first reset signal Vref1 is transmitted to the initialization transistor M5, and a connection node (a first node N1) of the drive transistor M3, the initialization transistor M5, the threshold compensation transistor M4, and the storage capacitor Cst is reset. A second scan signal line SP-1 controls the data writing transistor M2 of the drive circuit to be turned on and off. When the data writing transistor M2 is turned on, a data signal Vdata on the data signal line is written into the gate of the drive transistor M3. A third scan signal line SN-2 controls the threshold compensation transistor M4 to be turned on and off. When the threshold compensation transistor M4 is turned on, the threshold voltage of the drive transistor M3 is compensated. At the same time, a fourth scan signal line SP-2 controls the reset transistor M7 to be turned on and off. When the reset transistor M7 is turned on, the anode of the light-emitting element600connected to the pixel circuit200is reset, that is, a second reset signal Vref2 is transmitted to the anode of the light-emitting element600. A light-emitting control signal Emit controls the light-emitting control transistor M1 and the second light-emitting control transistor M6 to be turned on and off. When the light-emitting control transistor M1 and the second light-emitting control transistor M6 are controlled to be turned on, a power signal PVDD is transmitted to the light-emitting element600, thereby achieving display and light-emission of the light-emitting element600. Illustratively, the light-emitting element600may be an organic light-emitting diode (OLED), a mini light-emitting diode (LED), a micro LED, or a quantum-dot light-emitting diode (QLED). The type of light-emitting element is not limited in this embodiment of the present disclosure. Further, the light-emitting element may include a red light-emitting element, a green light-emitting element, and a blue light-emitting element. Light-emitting elements of different colors may be arranged in many different manners, such as a diamond pixel arrangement, a standard red-green-blue (RGB) arrangement, a delta pixel arrangement, a pearl pixel arrangement, or a 2-in-1 pixel arrangement. The arrangement of light-emitting elements of different colors is not limited in this embodiment of the present disclosure.

Further,FIG.4is a schematic diagram illustrating the structure of the display panel10as a whole. The display panel10is arranged with overlapping layers of films so that it is convenient to clearly understand the configuration positions of the films. Referring toFIGS.5to10, different films in the display panel10are illustrated one by one from the bottom to the top. That is, a film310where the second active layer231is disposed, a metal film320where the third gate232and the second gate213are disposed, a film330where the first active layer211is disposed, a metal film340where the first gate212is disposed, a metal film360where the source and drain are disposed, and a metal film350located between the metal film340and the metal film360for connecting the two are sequentially included. Referring toFIG.7, region A shown in the figure is a capacitor plate Cst1 of the storage capacitor Cst, and the film where the capacitor plate Cst1 is disposed is the same film layer as the film330where the first active layer211is disposed. Illustratively, the film where the other capacitor plate Cst2 of the storage capacitor Cst is disposed may be the same layer as the metal film320where the third gate232and the second gate213are disposed, as shown inFIG.6. The film position of the other capacitor plate Cst2 of the storage capacitor Cst is not limited in this embodiment of the present disclosure.

FIG.11is a schematic diagram of circuit elements in another pixel circuit according to an embodiment of the present disclosure.FIG.12is a schematic diagram of a part of the structure of a display panel according to an embodiment of the present disclosure.FIG.13is a schematic diagram of circuit elements in another pixel circuit according to an embodiment of the present disclosure. Referring toFIGS.11to13, a drive circuit200includes a pixel circuit200A, the pixel circuit200A includes a data writing transistor M2, a drive transistor M3, and a node potential adjustment capacitor C1 disposed in series between the gate of the data writing transistor M2 and the gate of the drive transistor M3. The first capacitor220includes the node potential adjustment capacitor C1.

In an embodiment, referring toFIG.11, the node potential adjustment capacitor C1 included in the pixel circuit200A is located between the data writing transistor M2 and the drive transistor M3. That is, one of the two capacitor plates of the node potential adjustment capacitor C1 is electrically connected to the gate of the data writing transistor M2, and the other capacitor plate of the node potential adjustment capacitor C1 is electrically connected to the gate of the drive transistor M3. Configuration of the node potential adjustment capacitor C1 may adjust the gate potential of the drive transistor M3 and ensure the operation stability of the entire pixel circuit200A.

Further, the configuration position of the node potential adjustment capacitor C1 is flexible, which is not limited to being only between the gate of the data writing transistor M2 and the gate of the drive transistor M3. As shown inFIG.13, the node potential adjustment capacitor C1 may also be disposed in series between the gate of the threshold compensation transistor M4 and the gate of the drive transistor M3.

In an embodiment, referring toFIG.12, region B shown in the figure is a capacitor plate C11 of the node potential adjustment capacitor C1, and the film where the capacitor plate C11 is disposed is the same film layer as the film330where the first active layer211is disposed. The film position of the other capacitor plate of the node potential adjustment capacitor C1 is not limited in this embodiment of the present disclosure. Disposing in the same layer can reduce the manufacturing procedure of the display panel10and help achieve a thinning design of the display panel10as a whole.

FIG.14is a schematic diagram illustrating the structure of another display panel according to an embodiment of the present disclosure. Referring toFIGS.11and14, the drive circuit200includes the pixel circuit200A, and the pixel circuit200A includes the data writing transistor M2, the drive transistor M3, the storage capacitor Cst, and the node potential adjustment capacitor C1. One capacitor plate of the storage capacitor Cst is electrically connected to the power signal terminal PVDD, the node potential adjustment capacitor C1 is disposed in series between the gate of the data writing transistor M2 and the gate of the drive transistor M3, the first capacitor220includes the storage capacitor Cst. the first transistor210also includes a first gate212located on the side of the first active layer211away from the substrate100, and one capacitor plate C11 of the node potential adjustment capacitor C1 is disposed in the same layer as the first gate212.

Illustratively, with continued reference toFIG.11, a pixel circuit200A including “7T2C” is used as an example in this embodiment of the present disclosure, where “T” denotes a transistor, and “C” denotes a capacitor. The two capacitors are the storage capacitor Cst and the node potential adjustment capacitor C1. The storage capacitor Cst is electrically connected to the power signal terminal PVDD. The node potential adjustment capacitor C1 is disposed in series between the gate of the data writing transistor M2 and the gate of the drive transistor M3. It should be noted that the configuration position of the node potential adjustment capacitor C1 is flexible, which is not limited to being only between the data writing transistor M2 and the drive transistor M3.

Further, referring toFIG.14, the storage capacitor Cst is used as the first capacitor220, and one capacitor plate221of the storage capacitor Cst is disposed in the same layer as the first active layer211. One capacitor plate C11 of the node potential adjustment capacitor C1 is disposed in the same layer as the first gate212of the first transistor210, that is, disposed in the same layer as the top gate of the first transistor210. The two capacitor structures are disposed in the same layer as other structures, further reducing the manufacturing procedure of the display panel10and helping achieve the thinning design of the display panel10as a whole. Furthermore, one capacitor plate221of the storage capacitor Cst and the capacitor plate C11 of the node potential adjustment capacitor C1 are disposed in different layers so that it is also ensured that the capacitor plate221and the capacitor plate C11 each have sufficient configuration space. Since the storage capacitor Cst has higher requirements on the capacitance value. That is, under the premise of ensuring that both the storage capacitor Cst and the node potential adjustment capacitor C1 have sufficient configuration space, the capacitor plate221is disposed in the same layer as the first active layer211so that the distance between the two plates of the storage capacitor Cst is relatively small, and the capacitance value of the storage capacitor Cst is further ensured.

FIG.15is a schematic diagram of circuit elements in a shift register circuit according to an embodiment of the present disclosure.FIG.16is a schematic diagram illustrating the structure of another display panel according to an embodiment of the present disclosure. Referring toFIGS.15and16, the drive circuit200includes a shift register circuit200B, and the shift register circuit200B includes a bootstrap capacitor C2 and an output transistor T1. One terminal of the bootstrap capacitor C2 is electrically connected to the output terminal GOUT of the shift register circuit, and the other terminal of the bootstrap capacitor C2 is electrically connected to the gate of the output transistor T1. The first transistor210also includes a first gate212disposed on the side of the first active layer211away from the substrate100. The first capacitor220includes the bootstrap capacitor C2, one capacitor plate C2b of the bootstrap capacitor C2 is disposed in the same layer as the first active layer211, and the other capacitor plate C2a of the bootstrap capacitor C2 is disposed in the same layer as the first gate212.

In an embodiment, the drive circuit200may include a shift register circuit200B, and the shift register circuit200B includes the output transistor T1 and the bootstrap capacitor C2, as shown inFIG.15. Further, one terminal of the bootstrap capacitor C2 is electrically connected to the output terminal GOUT of the shift register circuit, and the other terminal of the bootstrap capacitor C2 is electrically connected to the gate of the output transistor T1, that is, the configuration position of the bootstrap capacitor C2 may be determined by the output terminal GOUT of the shift register circuit200B and the output transistor T1. As shown inFIG.15, the shift register circuit200B also includes other transistors, capacitor structures, and the like, that is, the shift register circuit200B also includes conventional configurations in the shift register circuit200B, and details are not described herein. In the shift register circuit200B, one plate of the bootstrap capacitor C2 is electrically connected to the gate of the output transistor T1 so that the potential of the gate of the output transistor T1 can be adjusted. The other terminal of the bootstrap capacitor C2 is electrically connected to the output terminal GOUT. Since the output transistor T1 is turned on by the low level, that is, the potential at one capacitor plate of the bootstrap capacitor C2 may become low according to an output low-level signal, and then the potential at the gate of the output transistor T1 is reduced via the bootstrap capacitor C2, thereby better ensuring the conduction degree of the output transistor T1.

In an embodiment, as shown inFIG.16, the film where one capacitor plate C2b of the bootstrap capacitor C2 is disposed is the same as the film330where the first active layer211of the first transistor210is disposed. The other plate C2a of the bootstrap capacitor C2 may be disposed in the same layer as the first gate212. Disposing in the same layer can reduce the manufacturing procedure of the display panel10and help achieve a thinning design of the display panel10as a whole. Further, the shift register circuit200B does not have a first transistor210, that is, the configuration space of the film where the first active layer211is disposed in the shift register circuit200B is relatively large. In other words, the configuration space for the capacitor plate C2b of the bootstrap capacitor C2 on the same layer as the first active layer211is relatively large so that the storage performance of the bootstrap capacitor C2 and the stability of the capacitor can be ensured.

FIG.17is a schematic diagram of circuit elements in a pixel circuit according to an embodiment of the present disclosure.FIG.18is a schematic diagram illustrating the structure of another display panel according to an embodiment of the present disclosure.FIG.19is a schematic diagram of a part of the structure of the display panel ofFIG.18.FIG.20is a schematic diagram illustrating the structure of another display panel according to an embodiment of the present disclosure.FIG.21is a schematic diagram of a part of the structure of the display panel ofFIG.20. Referring toFIG.3andFIGS.17to21, the drive circuit200includes a pixel circuit200A, and the pixel circuit includes a light-emitting control transistor M1, an initialization transistor M5, and a bias adjustment transistor M8, and the display panel10also includes a light-emitting control signal line Emit, an initialization signal line Vref1, and a bias adjustment signal line DVH. The light-emitting control signal line Emit is electrically connected to the gate of the light-emitting control transistor M1, the initialization signal line Vref1 is electrically connected to the input terminal of the initialization transistor M5, and the bias adjustment signal line DVH is electrically connected to the input terminal of the bias adjustment transistor M8. At least one of the light-emitting control signal line Emit, the initialization signal line Vref1, or the bias adjustment signal line DVH is disposed in the same layer as the first active layer211.

In an embodiment, referring toFIG.17, the pixel circuit200A includes the light-emitting control transistor M1, the initialization transistor M5, and the bias adjustment transistor M8. The control terminal of the light-emitting control transistor M1 is electrically connected to the light-emitting control signal line Emit, that is, the gate of the light-emitting control transistor M1 is electrically connected to the light-emitting control signal line Emit, the input terminal of the initialization transistor M5 is electrically connected to the initialization signal line Vref1, and the input terminal of the bias adjustment transistor M8 is electrically connected to the bias adjustment signal line DVH, thereby achieving light-emitting control, initialization adjustment, bias adjustment, and the like of the pixel circuit200A.

Further, the film corresponding to the first active layer211where the light-emitting control signal line Emit, the initialization signal line Vref1, and the bias adjustment signal line DVH are disposed may be arranged in a conductive manner so that the corresponding film may have the metal characteristic for performing signal transmission.

In an embodiment, as shown inFIG.18andFIG.19, the light-emitting control signal line Emit is disposed in the same layer as the first active layer211, that is, the light-emitting control signal line Emit reuses the corresponding region where the first active layer211is disposed in the film330. Referring to the light-emitting control signal line Emit inFIG.19, when the light-emitting control signal line Emit is manufactured in the display panel10, one manufacturing procedure can be reduced, and the manufacturing cost of the display panel10can be saved. As shown inFIG.20andFIG.21, the initialization signal line Vref1 is disposed in the same layer as the first active layer211, that is, the initialization signal line Vref1 reuses the corresponding region of the film330where the first active layer211is disposed. Referring to the initialization signal line Vref1 inFIG.21, when the initialization signal line Vref1 is manufactured in the display panel10, one manufacturing procedure can be reduced, and the manufacturing cost of the display panel10can be saved. Meanwhile, referring to region E inFIG.21, the initializing signal line Vref1 and the film330originally in this region need to be electrically connected across layers. The initializing signal line Vref1 is disposed at the film330so that a perforation process can be reduced, and the manufacturing procedure of the display panel10can also be reduced.

Similarly, the bias adjustment signal line DVH is disposed in the same layer as the first active layer211so that a manufacturing procedure can also be reduced, and the manufacturing cost of the display panel10can be saved. Further, the light-emitting control signal line Emit, the initialization signal line Vref1, and the bias adjustment signal line DVH may be all disposed in the same layer as the first active layer211to more effectively control the manufacturing cost of the display panel10.

FIG.22is a schematic diagram illustrating the structure of another display panel according to an embodiment of the present disclosure.FIG.23is a section view taken along section line C-C′ ofFIG.22. Referring toFIGS.2,22, and23, the display panel10also includes a fan-out wire region12and fan-out wires400disposed in the fan-out wire region12. The fan-out wires400include at least one layer of wire structures, and at least a portion of the fan-out wires400are disposed in the same layer as the first active layer211.

In an embodiment, the display panel100includes a display region11and a fan-out wire region12. The display region11is provided with a light-emitting element600and a data line430connected to the light-emitting element600. The data line430is configured to provide a data signal for the light-emitting element600so that the light-emitting element600emits light and displays according to the data signal.

Additionally, the display panel10also includes a non-display region located on at least one side of the display region11. For example,FIG.22is used as an example where the non-display region is located on the lower side of the display region11. The non-display region may include a fan-out wire region12and a binding region13. The fan-out wire region12is provided with fan-out wires400. The binding region13is provided with a drive chip131. The fan-out wire region410is electrically connected to the data line430and the drive chip131separately for transmitting a data signal output from the drive chip to the data line430.

In this embodiment of the present disclosure, adjacent fan-out wires400may be disposed in different layers. That is, referring toFIG.23, a fan-out wire410and a fan-out wire420are disposed in different layers so that parasitic capacitance between adjacent signal wires can be avoided, influence and interference of signal transmission can be avoided, and display effect of the display panel10can be ensured. Thus, the area of the lower bezel occupied by the fan-out wires can be reduced, the area of the lower bezel is reduced, and the screen ratio of the display panel is increased. Comparing and referring toFIG.2andFIG.23, a portion of the fan-out wires410are disposed in the same layer as the first active layer211so that the manufacturing procedure of the fan-out wires410can be reduced, thus reducing the cost of the overall manufacturing of the display panel10. Moreover, the fan-out wires410do not need to occupy one more film, thus facilitating a thinning design of the display panel10as a whole.

FIG.24is a schematic diagram illustrating the structure of another display panel according to an embodiment of the present disclosure.FIG.25is a schematic diagram of a part of the structure of the display panel ofFIG.24. Referring toFIGS.3,24, and25, the drive circuit200includes a pixel circuit200A, the pixel circuit200A includes a drive transistor M3 and a threshold compensation transistor M4, and the output terminal of the threshold compensation transistor M4 is electrically connected to the gate of the drive transistor M3 via a first connection structure510. The first connection structure510is disposed in the same layer as the first active layer211.

In an embodiment, as shown inFIG.3, the drive transistor M3 and the threshold compensation transistor M4 in the pixel circuit200A are connected to each other, that is, the output terminal of the threshold compensation transistor M4 is electrically connected to the gate of the drive transistor M3. As shown inFIG.24, the drive transistor M3 and the threshold compensation transistor M4 are electrically connected by configuration of the first connection structure510.

Further, as shown inFIG.25, the first connection structure510for connecting the drive transistor M3 and the threshold compensation transistor M4 is disposed in the same layer as the first active layer211, that is, the first connection structure510and the first active layer211are both disposed in the film330. The first connection structure510is disposed on the existing film330so that an individual manufacturing procedure of the first connection structure510can be reduced, and the manufacturing cost of the display panel10is saved. Moreover, the manner of sharing a film is also beneficial to achieve a thinning design of the display panel10. Further, the first connection structure510is disposed at the film330so that the process of perforating the first connection structure510across layers to electrically connect to the film330can be avoided, that is, the perforation process and the manufacturing procedure of the display panel10can be reduced.

FIG.26is a schematic diagram illustrating the structure of another display panel according to an embodiment of the present disclosure. Referring toFIG.26, the drive circuit200also includes second transistors230, the second transistor230includes a second active layer231, and the second active layer231includes silicon. The display panel10also includes a second connection structure520, the sources233and the drains234of at least a portion of the second transistors230are electrically connected to the second active layer231via the second connection structure520; and the second connection structure520is disposed in the same layer as the first active layer211.

The drive circuit200of the display panel10also includes a second transistor230, and the second active layer231of the second transistor230includes silicon, that is, the second transistor230is an LTPS transistor, which has the advantages of high switch speed, high carrier mobility, and low power.

Further, the display panel10also includes a second connection structure520. In the second transistor230, the source233and the drain234are electrically connected to the second active layer231via the second connection structure520, that is, signal transmission of the second transistor230is achieved. The second connection structure520is configured so that the perforation depth of the source233and the drain234can be reduced, thereby reducing the difficulty in manufacturing the display panel10and ensuring the stability of signal transmission in the second transistor230. In this manner, the overall lap signal is better.

Further, in the second transistor230, the second connection structure520for connecting the source233and the second active layer231may be disposed in the same layer as the first active layer211. By disposing in the same layer, the second connection structure520and the first active layer211may be manufactured in the same procedure, and the entire manufacturing cost of the display panel10is reduced. Moreover, a film used by the second connection structure520does not need to be provided, that is, the film structure separately provided for the second connection structure520can be reduced, thus facilitating a thinning design of the display panel10as a whole.

FIG.27is a schematic diagram illustrating the structure of another display panel according to an embodiment of the present disclosure. Referring toFIGS.3and27, the drive circuit200includes a pixel circuit200A, and the second transistor230includes a switch transistor Ms and a drive transistor M3. At least the source233and the drain234of the switch transistor Ms are electrically connected to the second active layer231via the second connection structure520.

In an embodiment, the pixel circuit200A includes a drive transistor M3 and a switch transistor Ms. The switch transistor Ms may refer to the light-emitting control transistor M1, the data writing transistor M2, the threshold compensation transistor M4, the initialization transistor M5, the second light-emitting control transistor M6, the reset transistor M7, and so on, which is not limited in this embodiment of the present disclosure.

Further, as shown inFIG.27, the switch transistor Ms and the drive transistor M3 may both be the second transistor230. Further, in a portion of switch transistors Ms, the source233and the drain234may be electrically connected to the second active layer231via the second connection structure520. In this manner, it is ensured that the electrical connection of the source233and the drain234of the switch transistor Ms to the second active layer231can be more stable, the operation is more stable, and the current is better prevented from leaking.

With continued reference toFIGS.15and27, the drive circuit200includes a shift register circuit200C, and the source233and the drain234of the second transistor230in the shift register circuit200C are electrically connected to the second active layer231via the second connection structure520.

Further, a second transistor230is also included in the shift register circuit200C, that is, an LTPS transistor is included. As for the second transistor230in the shift register circuit200C, the current may be prevented from leaking via the second connection structure. In this manner, it is ensured that the operation of the second transistor230in the shift register circuit200C is more stable, the current is better prevented from leaking, and the transistor is better controlled.

FIG.28is a schematic diagram illustrating the structure of another display panel according to an embodiment of the present disclosure. Referring toFIGS.2and28, the drive circuit200also includes a second transistor230, and the second transistor230includes a second active layer231, a source233, and a drain234. The second active layer231includes silicon, and both the source233and the drain234are electrically connected to the second active layer231. The source233includes a first source portion233aand a second source portion233b, and the first source portion233ais located on the side of the second source portion233badjacent to the second active layer231. The first source portion233aincludes a first source surface233a1adjacent to the side of the second source portion233b, and the second source portion233bincludes a second source surface233b1adjacent to the side of the first source portion233a, The drain234includes a first drain portion234aand a second drain portion234b, and the first drain portion234ais disposed on the side of the second drain portion234badjacent to the second active layer231, the first drain portion234aincludes a first drain surface234a1adjacent to the side of the second drain portion234b, and the second drain portion234bincludes a second drain surface234b1adjacent to the side of the first drain portion234a. The display panel also includes a source connection portion521and/or a drain connection portion522. The source connection portion521is located between a film in which the first source portion233ais disposed and a film in which the second source portion233bis disposed and is electrically connected to the first source portion233aand the second source portion233bseparately, and the area of the source connection portion521is larger than both the area of the first source surface233a1and the area of the second source surface233b1. The drain connection portion522is located between a film in which the first drain portion234ais disposed and a film in which the second drain portion234bis disposed and is electrically connected to the first drain portion234aand the second drain portion234bseparately, and the area of the drain connection portion522is larger than both the area of the first drain surface234a1and the area of the second drain surface234b1.

In an embodiment, as shown inFIGS.2and28, both the source233and the drain234of the second transistor230are electrically connected to the second active layer231to ensure the normal operation of the second transistor230. As shown inFIG.2, the source233and the drain234need to be electrically connected to the second active layer231by penetrating the multiple insulation layers, that is, deep perforation needs to be performed in manufacturing the source233and the drain234to ensure the electrical connection to the second active layer231. In the manufacturing process of the display panel10, when it is ensured that the overall structure of the display panel10is stable, the process difficulty in accurately etching the source233and the drain234is relatively large. Further, as shown inFIG.28, the source233includes the first source portion233aand the second source portion233b, and the drain234includes the first drain portion234aand the second drain portion234b. That is, the source233and the drain234, which were manufactured by one deep perforation process, are manufactured by two or more perforations in a stepwise manner. In this manner, adverse effects of the deep perforation on the display panel10can be reduced.

The first source portion233ais adjacent to the second active layer231, and the second source portion233bis away from the second active layer231compared with the first source portion233a. The first source surface233a1of the first source portion233ais adjacent to one side of the second source portion233b, and the second source surface233b1of the second source portion233bis adjacent to one side of the first source portion233a. Similarly, the first drain portion234ais adjacent to the second active layer231, and the second drain portion234bis away from the second active layer231compared with the first drain portion234a. Further, the first drain surface234a1of the first drain portion234ais adjacent to one side of the second drain portion234b, and the second drain surface234b1of the second drain portion234bis adjacent to one side of the first source portion234a. Further, the source connection portion521is disposed between the first source surface233a1and the second source surface233b1so that the electrical connection between the first source portion233aand the second source portion233bis achieved, and the electrical connection between the source233and the second active layer231is ensured. The drain connection portion522is disposed between the first drain surface234a1and the second drain surface234b1so that the electrical connection between the first drain portion234aand the second drain portion234bis achieved, and the electrical connection between the drain234and the second active layer231is ensured. It should be noted that the source connection portion521and the drain connection portion522may be disposed at the same time in the display panel10, or only one of the source connection portion521or the drain connection portion522is provided according to process requirements, which is not limited in this embodiments of the present disclosure.

Further, the area of the source connection portion521is larger than both the area of the first source surface233a1and the area of the second source surface233b1. That is, when the electrical connection between the first source portion233aand the second source portion233bis ensured, configuring the source connection portion521with a larger area can reduce the alignment accuracy requirement for the first source portion233aand the second source portion233band thus reduce the difficulty in manufacturing the display panel10. Similarly, the area of the drain connection portion522is larger than both the area of the first drain surface234a1and the area of the second drain surface234b1. That is, when the electrical connection between the first drain portion234aand the second drain portion234bis ensured, configuring the drain connection portion522with a larger area can reduce the alignment accuracy requirement for the first drain portion234aand the second drain portion234band thus reduce the difficulty in manufacturing the display panel10.

With continued reference toFIG.28, both the source connection portion521and the drain connection portion522are disposed in the same layer as the first active layer211.

Further, the source connection portion521and the drain connection portion522are disposed in the same layer so that the normalized design of the display panel10can be ensured. Moreover, the source connection portion521and the drain connection portion522are disposed in the same layer as the first active layer211, that is, the source connection portion521, the drain connection portion522, and the first active layer211may be manufactured in one step, reducing the entire manufacturing cost of the display panel10. In addition, a film used by the source connection portion521and the drain connection portion522does not need to be provided, that is, the film structure provided separately for the source connection portion521and the drain connection portion522can be reduced, thus facilitating a thinning design of the display panel10as a whole.

FIG.29is a schematic diagram illustrating the structure of another display panel according to an embodiment of the present disclosure.FIG.30is a section view taken along section line D-D′ ofFIG.29. Referring toFIGS.29and30, the display panel10includes a first display region11aand a second display region11b, and the second display region11bat least partially surrounds the first display region11a. The first display region11aincludes a first light-emitting element610, and the second display region11bincludes a second light-emitting element620. The drive circuit200includes a first pixel circuit240and a second pixel circuit250located in the second display region11b, the first pixel circuit240is electrically connected to the first light-emitting element610via a third connection structure530, and the second pixel circuit250is electrically connected to the second light-emitting element620. The third connection structure530is disposed in the same layer as the first active layer211.

The display panel10includes a first display region11aand a second display region11b. The second display region11bat least partially surrounds the first display region11a. The first display region11amay be a light-transmitting region in which an optical device is arranged below the display panel10for acquiring external light. Illustratively, the optical device20may be a camera under the screen or a fingerprint recognition module. The second display region11bmay be a normal display region of the display panel10.

Further, the first display region11aincludes a first light-emitting element610, and the second display region11bincludes a second light-emitting element620. A comprehensive display effect of the display panel10is achieved by configuration of the first light-emitting element610and the second light-emitting element620.

Further, referring toFIG.30, a pixel circuit200A for driving the first light-emitting element610is the first pixel circuit240, and a pixel circuit200A for driving the second light-emitting element620is the second pixel circuit250. To ensure the light-transmitting effect of the first display region11a, both the first pixel circuit240and the second pixel circuit250are disposed in the second display region11b. Further, the first pixel circuit240disposed in the second display region11bmay be electrically connected to the first light-emitting element610via the third connection structure530.

Further, referring toFIG.30, the third connection structure530is disposed in the same layer as the first active layer211in the first transistor210, that is, the third connection structure530and the first active layer211may be manufactured in one procedure, reducing the entire manufacturing cost of the display panel10. In addition, a film used by the third connection structure530does not need to be provided, that is, the film structure provided separately for the third connection structure530can be reduced, thus facilitating a thinning design of the display panel10as a whole. It should be noted that the first transistor210shown inFIG.30is used for indicating that the third connection structure530is disposed in the same layer as first active layer211, and the first transistor210is not in the section view taken along section line D-D′.

FIG.31is a schematic diagram illustrating the structure of another display panel according to an embodiment of the present disclosure. As shown inFIG.31, the first transistor210also includes a second gate213located on the side of the first active layer211adjacent to the substrate100. The first active layer211includes a source region211a, a drain region211b, and a channel region211clocated between the source region211aand the drain region211b. The display panel10also includes a hydrogen barrier layer700located between a film in which the first active layer211is disposed and a film in which the second gate213is disposed, the hydrogen barrier layer700includes a metal layer and is in contact with the second gate213, and the hydrogen barrier layer700overlaps at least the channel region211cin the thickness direction of the display panel10.

Referring toFIG.31, the first transistor210may include a first gate212and a second gate213, that is, the first transistor210is a double-gate transistor, and the first gate212is the top gate of the first transistor210and the second gate213is the bottom gate of the first transistor210. Further, the first active layer211includes a source region211a, a drain region211b, and a channel region211clocated between the source region211aand the drain region211b. The source region211ais a position at which the source214is electrically connected to the first active layer211. The drain region211bis a position at which the drain215is electrically connected to the first active layer211. The channel region211cis a region in which the first gate212and the second gate213overlap at the first active layer211in the thickness direction of the display panel10.

Further, the display panel10also includes a hydrogen barrier layer700disposed in contact with the second gate213. The provided hydrogen barrier layer700may prevent hydrogen from transmitting to the channel region211c, thus avoiding a threshold drift of the first transistor210and ensuring the operational stability of the first transistor210. In an embodiment, the hydrogen barrier layer700includes a metal layer. Illustratively, the material of the hydrogen barrier layer700may be titanium metal. In terms of the hydrogen barrier layer of silicon nitride, although silicon nitride does not contain hydrogen, hydrogen is also generated in the manufacturing process of the silicon nitride. That is, if the hydrogen barrier layer of silicon nitride is used, a certain impact is imposed on the threshold stability of the first transistor210. Thus, the hydrogen barrier layer700of metal has a more stable structure and better ensures the threshold stability of the first transistor210.

Alternatively, the enthalpy value of the hydrogen barrier layer700is negative.

In an embodiment, the enthalpy value of the hydrogen barrier layer700is adjusted to a negative value. In this manner, it is ensured that the hydrogen barrier layer700has a stable structure, the hydrogen barrier function is stable, and the overall display panel10is stable.

With continued reference toFIG.31, the display panel10also includes an isolation layer800disposed between the film in which the first active layer211is disposed and a film in which the hydrogen barrier layer700is disposed, the isolation layer800is in contact with the hydrogen barrier layer700and the first active layer211separately, and the isolation layer800includes silicon oxide.

Further, the display panel10is provided with an isolation layer800disposed between the first active layer21and the hydrogen barrier layer700, through which the effect of hydrogen on the threshold of the first transistor210can be more effectively prevented. Thus, the threshold stability of the first transistor210can be further ensured.

Referring toFIG.31, the drive circuit200also includes a second transistor230, the second transistor230includes a second active layer231and a third gate232, the second active layer231includes silicon, and the third gate232is located on the side of the second active layer231away from the substrate100. The display panel10also includes a hydrogen injection layer900located between a film in which the second active layer231is disposed and a film in which the third gate232is disposed.

In an embodiment, the second active layer231of the second transistor230includes silicon, that is, a hydrogenation process exists in manufacturing the second active layer231. To ensure the hydrogenation process of the second transistor230, the hydrogen injection layer900is disposed on the side of the third gate232of the second transistor230adjacent to the second active layer231. Further, the configuration position of the hydrogen injection layer900ensures the hydrogenation process of the second transistor230without transmitting hydrogen to the first active layer211of the first transistor210, that is, the threshold stability of the first transistor210is also ensured.

Based on the same inventive concept, an embodiment of the present disclosure also provides a display device.FIG.32is a schematic diagram illustrating the structure of a display device according to an embodiment of the present disclosure. The display device includes any one of the display panels provided in the preceding embodiments. Illustratively, referring toFIG.32, the display device1includes the display panel10. Therefore, the display device also has the beneficial effects of the display panel described in the preceding embodiments. The same content may be understood by reference to the preceding description of the display panel, and repetition is not made below.

The display device1provided in this embodiment of the present disclosure may be a phone shown inFIG.32, or may be any electronic product with a display function, including but not limited to a television, a laptop, a desktop display, a tablet computer, a digital camera, a smart bracelet, smart glasses, an in-vehicle display, industry-controlling equipment, a medical display, a touch interactive terminal, and the like, which is not limited in embodiments of the present disclosure.

It is to be noted that the preceding are only alternative embodiments of the present disclosure and the technical principles used therein. It is to be understood by those skilled in the art that the present disclosure is not limited to the embodiments described herein. For those skilled in the art, various apparent modifications, adaptations, and substitutions may be made without departing from the scope of the present disclosure. Therefore, while the present disclosure is described in detail via the preceding embodiments, the present disclosure is not limited to the preceding embodiments and may include more equivalent embodiments without departing from the concept of the present disclosure. The scope of the present disclosure is determined by the scope of the appended claims.