Patent ID: 12205928

In operation, electrical power is provided to the SSL device10via the contacts17,19, causing the active region14to emit light. Higher light output can be achieved at the assembly level by mounting several high voltage SSL devices onto a single circuit board, e.g., an LED package array to deliver higher flux. Typical arrays include many LED packages which can be coupled in series, in parallel or in a combination of series and parallel coupled packages. For example, high voltage can be achieved by wiring several conventional high voltage SSL devices10in parallel configuration. Arrays of high voltage SSL devices can be advantageous in that the number of LED packages included in the array is independent of the total package voltage (U.S. Patent Publication No. 2012/0161161, incorporated herein by reference in its entirety). However, despite improved light output and higher flux delivery, arrays incorporating the SSL device10ofFIGS.1A and1Bare subject to junction failure which can cause problems with chip usability, deterioration, and create high variation in bias across individual coupled SSL devices in the array. For example, an individual LED structure11acan fail, become an open circuit, or become a short circuit, causing the remaining LED structure11bas well as other serially or parallel coupled dies to fail, reduce performance or lose stability. Accordingly, there remains a need for high voltage LEDs, high voltage LED arrays and other solid-state devices that facilitate packaging and have improved performance and reliability.

BRIEF DESCRIPTION OF THE DRAWINGS

Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale. Instead, emphasis is placed on illustrating clearly the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.

FIGS.1A and1Bare schematic cross-sectional and top plan diagrams of a high voltage LED device configured in accordance with the prior art.

FIG.2Ais a schematic top plan view of a solid-state transducer (SST) array configured in accordance with an embodiment of the present technology.

FIGS.2B-2Care cross-sectional views of a multi-junction SST die shown inFIG.2Aand in accordance with an embodiment of the present technology.

FIG.3is a flowchart of a method of forming an SST die having a plurality of junctions coupled in series in accordance with embodiments of the present technology.

FIG.4is a schematic block diagram of an array assembly of SST dies having electrical cross-connections in accordance with embodiments of the present technology.

FIG.5is a flowchart of a method of forming an array of high voltage light-emitting diodes (HVLEDs) in accordance with embodiments of the present technology.

DETAILED DESCRIPTION

Specific details of several embodiments of solid-state transducers (“SSTs”) and associated systems and methods are described below. The term “SST” generally refers to solid-state devices that include a semiconductor material as the active medium to convert electrical energy into electromagnetic radiation in the visible, ultraviolet, infrared, and/or other spectra. For example, SSTs include solid-state light emitters (e.g., LEDs, laser diodes, etc.) and/or other sources of emission other than electrical filaments, plasmas, or gases. SSTs can alternately include solid-state devices that convert electromagnetic radiation into electricity. Additionally, depending upon the context in which it is used, the term “substrate” can refer to a wafer-level substrate or to a singulated device-level substrate. A person skilled in the relevant art will also understand that the technology may have additional embodiments, and that the technology may be practiced without several of the details of the embodiments described below with reference toFIGS.2A-5.

FIG.2Ais a schematic top plan view of a solid-state transducer (SST) array100configured in accordance with an embodiment of the present technology. As shown inFIG.2A, the SST array100includes two SST dies110(identified individually as first and second SST dies110a,110b) which can be coupled in parallel. Only two SST dies110are illustrated inFIG.2Afor simplicity; however, one of ordinary skill in the art will recognize that the SST array100can include additional SST dies110arranged in a variety of configurations (e.g., in series, in parallel, or a combination of serially and parallel aligned dies110).

FIGS.2B and2Care cross-sectional views of the multi-junction SST die110aofFIG.2Ain accordance with an embodiment of the present technology. Referring toFIGS.2A-2Ctogether, the SST die110can include a substrate120carrying a plurality of LED structures111(identified individually as first and second LED structures111aand111b, respectively) that are electrically isolated from one another by an insulating material112. For the purposes of illustration, only two LED structures111aand111bare shown in each of the individual die110a,110b; however, it will be understood that in other embodiments, the SST die110can include three, four, five, and/or other suitable numbers of LED structures111. In further embodiments, the SST die110can also include a lens, a mirror, and/or other suitable optical and/or electrical components (not shown).

In one embodiment, the substrate120can include a metal, a metal alloy, a doped silicon, and/or other electrically conductive substrate materials. For example, in one embodiment, the substrate120can include copper, aluminum, and/or other suitable metals. In other embodiments, the substrate120can also include a ceramic material, a silicon, a polysilicon, and/or other generally nonconductive substrate materials.

In certain embodiments, the insulating material112can include silicon oxide (SiO2), silicon nitride (Si3N4), and/or other suitable nonconductive materials formed on the substrate120via thermal oxidation, chemical vapor deposition (“CVD”), atomic layer deposition (“ALD”), and/or other suitable techniques. In other embodiments, the insulting material112can include a polymer (e.g., polytetrafluoroethylene and/or other fluoropolymer to tetrafluoroethylene), an epoxy, and/or other polymeric materials.

The LED structures111a,111bare configured to emit light and/or other types of electromagnetic radiation in response to an applied electrical voltage. In the embodiment illustrated inFIGS.2B and2C, the LED structures111a,111beach have a first side132an d a second side134opposite the first side132. The LED structures111a,111bindividually include a first semiconductor material115at the first side132, a second semiconductor material116at the second side134, and an active region114located between the first and second semiconductor materials115,116. In other embodiments, the LED structures111can also include silicon nitride, aluminum nitride (AlN), and/or other suitable intermediate materials.

The first and second semiconductor materials115,116can be doped semiconductor materials. In certain embodiments, the first semiconductor material115can include P-type GaN (e.g., doped with magnesium (Mg)), and the second semiconductor material116can include N-type GaN (e.g., doped with silicon (Si)). In other embodiments, the first semiconductor material115can include N-type GaN, and the second semiconductor material116can include P-type GaN. In further embodiments, the first and second semiconductor materials115and116can individually include at least one of gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), gallium arsenide phosphide (GaAsP), gallium(III) phosphide (GaP), zinc selenide (ZnSe), boron nitride (BN), aluminum gallium nitride (AlGaN), and/or other suitable semiconductor materials.

The active region114can include a single quantum well (“SQW”), multiple quantum wells (MQWs), and/or a single grain semiconductor material (e.g., InGaN), such as a single grain semiconductor material (e.g., InGaN) with a thickness greater than about 10 nanometers and up to about 500 nanometers. In certain embodiments, the active region114can include an InGaN SQW, GaN/InGaN MQWs, and/or an InGaN bulk material. In other embodiments, the active region114can include aluminum gallium indium phosphide (AlGaInP), aluminum gallium indium nitride (AlGaInN), and/or other suitable materials or arrangements.

In certain embodiments, at least one of the first semiconductor material115, the active region114, and the second semiconductor material116can be formed on the substrate material120via metal organic chemical vapor deposition (“MOCVD”), molecular beam epitaxy (“MBE”), liquid phase epitaxy (“LPE”), and hydride vapor phase epitaxy (“HVPE”). In other embodiments, at least one of the foregoing components and/or other suitable components (not shown) of the LED structure111may be formed using other suitable epitaxial growth techniques.

The individual LED structures111a,111balso each include a first electrode or contact117(identified individually as117aand117b) and a second electrode or contact119(identified individually as119aand119b). The first contacts117a,117bare electrically coupled to the first semiconductor material115of the first and second LED structures111a,111b, respectively. The second contacts119a,119bare electrically coupled to the second semiconductor material116of the first and second LED structures111a,111b, respectively. As shown inFIG.2C, the first LED structure111aincludes a first contact117alocated on the first semiconductor material115and the second LED structure111bincludes a second contact119blocated on the second semiconductor material116through a gap130in the active region114and the first semiconductor material115. First contact117aand second contact119bprovide external electrical contact points for coupling the SST die110with external contacts and/or devices for receiving or applying electrical power.

FIGS.2A and2Cshow the first contact117aaccessible at the first side132of the LED structure111a. As illustrated, the first contact117acan be formed over a smaller portion of the first semiconductor material115. In other embodiments, not shown, the first contact117acan extend over a larger portion of the underlying first semiconductor material115. The first contact117acan be formed using chemical vapor deposition (“CVD”), physical vapor deposition (“PVD”), atomic layer deposition (“ALD”), spin coating, patterning, and/or other suitable techniques known in the art. In some embodiments, the first contact117acan be formed of non-reflective materials. In other embodiments, reflective contact materials, including nickel (Ni), silver (Ag), copper (Cu), aluminum (Al), tungsten (W), and/or other reflective materials can be used to form the first contact117a.

Likewise, the second contact119bis accessible through the gap130at the first side132of the LED structure111b. Suitable second contact materials can include titanium (Ti), aluminum (Al), nickel (Ni), silver (Ag), and/or other suitable conductive materials. The second contact119bcan also be formed using CVD, PVD, ALD or other suitable techniques known in the semiconductor fabrication arts. As described, the gap130can be formed, for example, by etching a portion of the LED structure111bextending from the first side132of the SST die110to or into the second semiconductor material116. In the embodiment illustrated inFIGS.2A and2C, the second contact119bcan be positioned near or at the edge of the LED structure111bsuch that no dielectric material is necessary for electrical insulation of the second contact119bfrom the first semiconductor material115or active region114. However, in other embodiments, second contacts119can be buried contact elements within the LED structure111, such as those described in the vertically arranged solid-state transducers described in U.S. patent application Ser. No. 13/346,495, which is incorporated herein by reference in its entirety. In such embodiments, a dielectric coating of etched walls in the LED structure111can electrically isolate the second contacts119from the first semiconductor material115and the active region114.

As shown inFIGS.2A-2C, the LED structures111a,111bare arranged in a lateral array with a channel126(FIGS.2A and2C) separating the adjacent LED structures111a,111b. The individual LED structures111a,111balso include a notch122through which a portion of the second semiconductor material116is exposed. An interconnect124electrically connects the two adjacent LED structures111a,111bthrough the corresponding notch122. As such, the first and second LED structures111a,111bare serially coupled to one another. In one embodiment, the interconnect124can bean interconnection point between the second contact119aon the first LED structure111aand the first contact117bon the second LED structure111b. The contacts117b,119acan be deposited or otherwise formed in the notch122by similar techniques as those described for first and second contacts117a,119b(e.g., CVD, PVD, ALD or other suitable techniques).

The channel126divides the SST device110such that the LED structures111a,111bof the SST die110are isolated from each other. For example, the channel126can be formed before the contacts117b,119aand the interconnect124are formed in the notch122and can extend to the second side134of the LED structures111a,111b(as shown inFIGS.2B and2C). In one embodiment, all or portions of the sidewalls of the channel126and/or the notch122can be coated with a dielectric material138(FIG.2C). In some arrangements, the dielectric material138can electrically insulate the second contact119(not shown) along a path extending through the first semiconductor material115, and the active region114. The dielectric material138can include silicon dioxide (SiO2), silicon nitride (SiN), and/or other suitable dielectric materials, and can be deposited using CVD, PVD, ALD, patterning, and/or other suitable techniques known in the art.

The SST die110can also include a third contact140coupled to the interconnect124and in accordance with an embodiment of the present technology. As illustrated inFIG.2A, the SST die110can have one or more third contacts140positioned in the channel126and electrically coupled to the interconnect124via one or more conductive lines142. In one embodiment, the third contact140is externally accessible through the channel126between the first and second LED structures111a,111b. In other embodiments, the third contact140can be positioned at the first side132of the LED structure111aor111bwith suitable insulating or dielectric materials intervening between the third contact140and the underlying first semiconductor material115. Suitable third contact materials140can include titanium (Ti), aluminum (Al), nickel (Ni), silver (Ag), and/or other suitable conductive materials. The third contact140can also be formed using CVD, PVD, ALD or other suitable techniques known in the semiconductor fabrication arts.

In the illustrated embodiment, the dielectric material138is positioned to insulate the exposed third contacts140laterally apart from the first semiconductor material115, the second semiconductor material116and the active region114, and therefore reduces the likelihood of shorting the contacts to each other during subsequent processing or in operation. In other embodiments, the SST dies110can include larger or smaller coatings or portions of the dielectric material138.

As shown inFIG.2C, the dielectric material138can coat the inner walls of the channel126but does not cover the third contacts140. In a particular embodiment, the conductive lines142can be formed over the dielectric material138between the interconnect124and the third contacts140. The conductive lines142can be made from a suitable electrically conductive material, such as nickel (Ni), silver (Ag), copper (Cu), aluminum (Al), tungsten (W) and/or other suitable conductive materials. The dielectric material138underlying the conductive lines142electrically isolates the third contact140from the first contact117a. The conductive lines142can be formed using deposition, patterning, and/or other suitable methods known in the art, and can be made from electrically conductive materials similar to those used for the second contact material119and or the third contact material140.

The SST dies110a,110bcan undergo further processing to add elements for attachment to additional substrates and/or devices. For example, bond pads (not shown) c an b e electrically coupled to the first, second and third contacts117a,119band140, respectively. The bond pads can be metal or metal alloy structures (e.g., Ni, Ag, Cu, Sn Al, W, etc.). In some arrangements, wire bonds146(FIG.2C) can be used to electrically couple external devices, additional dies, and/or other power sources to the first and second contacts117a,119bof the SST dies110. In other embodiments, the resulting SST dies110can include first and second contacts117aand119bthat can be mounted on a board, a package or another component without requiring wire bonds, e.g., using a solder reflow process.

In one embodiment, the third contact140can provide a provision for forming a cross-connection144(FIG.2A) between an adjacent SST die110bcoupled in the SST array100. The cross-connection144can provide an electrical connection to at least one intermediate point located between the multiple LED structures111a,111bof the SST dies110a,110bwithin the SST array100. In operation, the cross-connection144can provide a reduced variation in bias across individual SST dies110(e.g., dies110a,110b). Referring toFIG.2A, with the cross-connection between the third contact140on SST die110aand the corresponding third contact140on SST die110b, the first LED structures111aand the second LED structures111bcan have identical voltage applied. Additionally, the cross-connection144can provide protection against SST die110or SST array100failures. For example, if one LED structure fails and becomes either an open circuit or a short circuit, additional LED structures remain operational with the cross-connection144.

In a particular example, if LED structure111aof SST die110abecomes short circuited (e.g., having low resistance), voltage applied to both SST dies110in parallel will preferentially flow through LED structure111aof SST die110a, and SST die110bwill not operate or operate with diminished capacity. The forward voltage will flow to LED structure111bof SST die110a; however, the cross-connection144provides forward voltage evenly to both LED structure111bof SST die110aas well as LED structure111bof SST die110b. As such more die remain in operation despite the faulty LED structure111a. Accordingly, the third contact140electrically coupled to the interconnects124between LED structures111aand111bprovide the accessible electrical connection within high voltage (e.g., multiple junction) SST dies110. In additional embodiments, the SST die110can include more than two LED structures111and, accordingly, can include multiple interconnects124with corresponding third contacts140provided for additional cross-connections144between, for example, parallel-coupled SST dies110.

FIG.3is a flowchart of a method300of forming an SST die having a plurality of junctions coupled in series in accordance with embodiments of the present technology. As shown inFIG.3, an initial stage (block302) of the method300can include forming a light-emitting diode (LED) structure having a first semiconductor material at a first side, a second semiconductor material at a second side opposite the first side, and a light-emitting active region between the first semiconductor material and the second semiconductor material. Another stage (block304) of the method300includes forming a first contact on a first junction, wherein the first contact is electrically coupled to the first semiconductor material. In a further stage (block306), the method300includes forming a second contact on a second junction, wherein the second contact is electrically coupled to the second semiconductor material.

The method300can include yet another stage (block308) of forming an interconnect between the first junction and the second junction, wherein the interconnect is electrically coupled to the first semiconductor material and the second semiconductor material. In some arrangements, the first, second and cross-connection contacts are accessible from the first side of the LED structure. In yet a further stage (block310), the method300includes forming a cross-connection contact electrically coupled to the interconnect. The cross-connection contacts can be used to electrically couple the SST die to another die in an array at an intermediate point located between the first and second junctions.

FIG.4is a schematic block diagram of an array assembly200of SST dies210having electrical cross-connections in accordance with embodiments of the present technology. As shown inFIG.4, the array assembly200includes a first terminal202, a second terminal204, and a plurality of SST dies210coupled in parallel between the first and second terminals202and204. The first and second terminals202and204are configured to receive an input voltage from an external power supply (not shown).

In the illustrated embodiment, the SST dies210are arranged as separate strings individually identified as206a-dcoupled in parallel with each other. The strings206a-dare each shown to have a single SST die210each having multiple LED junctions211(e.g., LED structures individually identified as111aand111b); however, in other embodiments, the SST dies210may be arranged into a single string and/or have other suitable arrangements. In further embodiments, at least one of the strings206a-dmay carry more than one SST dies210in series.

In certain embodiments, the individual SST dies210have two LED junctions211a,211belectrically coupled in series by an interconnect224. In other embodiments, the individual dies210may include more than two LED junctions211(e.g., three, four, five, etc.) electrically coupled in series by interconnects. The array assembly200also includes a plurality of cross-connections244electrically coupling interconnects224of SST dies110between the strings206a-d. As such, input voltage provided through terminals202,204may flow through the strings106a-dand between the strings to provide alternative electrical paths for improving light output and higher flux delivery. Accordingly, array assemblies, such as assembly200, which incorporate the SST dies210or dies110(illustrated inFIGS.2A-2C), have provisions to overcome junction failure, providing reduced variation in bias across individual coupled SST dies in the array. Moreover, the array assemblies200can remain in use even after a junction failure, providing improved chip performance and reliability, thereby reducing manufacturing costs.

FIG.5is a flowchart of a method400of forming an array of high voltage light-emitting diodes (HVLEDs) in accordance with embodiments of the present technology. As shown inFIG.5, an initial stage (block402) of the method400can include providing a first terminal and a second terminal, e.g., for receiving an input voltage from an external power supply. Another stage (block404) of the method400includes coupling a plurality of HVLEDs between the first and second terminals. In some embodiments, at least a pair of HVLEDs can be coupled in parallel. The plurality of HVLEDs can individually include a plurality of junctions coupled in series with an interconnection between each individual junction. In some arrangements, the individual HVLED have a cross-connection contact coupled to the interconnection.

A further stage (block406) of the method400can include forming a cross-connection between the cross-connection contacts on at least the pair of the HVLEDs. In some arrangements, a bond pad can be coupled to the cross-connection contacts and forming a cross-connection between the contacts can include wire bonding between the bond pads. Additional stages (not shown) may include electrically coupling the first terminal and the second terminal to an AC power source or other power source.

From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. The SST dies110,210and the array assemblies100,200can include additional components, and/or different combinations of the components described herein. For example, the SST dies110can include more than two junctions and/or be provided with more than one interconnect124. In such arrangements, additional third contacts140can be formed providing for additional intermediate electrical access points between the multiple junctions or LED structures. Furthermore, the array100includes a 1×1 array of SST dies110, and the array assembly200includes a 1×4 array of SST dies210. In other embodiments, assemblies and arrays can include different numbers of SST dies and/or have different shapes (e.g., rectangular, circular, etc.). Additionally, certain aspects of the present technology described in the context of particular embodiments maybe eliminated in other embodiments. For example, the configuration of the dielectric material138can be altered to expose or cover differing combinations of semiconductor materials, contacts or conductive lines. Additionally, while advantages associated with certain embodiments of the present technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments need necessarily exhibit such advantages to fall within the scope of the technology. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described herein.