Patent ID: 12255139

DETAILED DESCRIPTION

Hereinafter, some example embodiments of the present inventive concepts will be described with reference to the accompanying drawings.

As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. Thus, for example, “at least one of A, B, or C,” “at least one of A, B, and C,” and “A, B, and/or C” mean either A, B, C or any combination thereof. In other words, an expression such as “at least one of,” when preceding a list of elements, modifies the entire list of elements and does not modify the individual elements of the list.

FIG.1is a plan view illustrating a semiconductor device according to an example embodiment.

FIGS.2A and2Bare cross-sectional views illustrating semiconductor devices according to an example embodiment.FIGS.2A and2Billustrate cross-sections of the semiconductor device ofFIG.1taken along lines I-I′ and respectively.

Referring toFIGS.1to2B, a semiconductor device100may include a substrate101, a first insulating structure IL1on the substrate101, contacts130penetrating through the first insulating structure ILL a second insulating structure IL2on the first insulating structure ILL and a conductive line170penetrating through the second insulating structure IL2. The conductive line170may include a power line for supplying power to standard cells of the semiconductor device100. The conductive line170may be disposed side by side in a pair on one standard cell to supply different power sources to the standard cell. The semiconductor device100may further include signal lines170S disposed in parallel with the conductive line170.

The substrate101may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon (Si), germanium (Ge), or silicon germanium (SiGe). The substrate101may be provided as a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor on insulator (SeOI) layer, or the like.

A device layer105may be disposed between the substrate101and the first insulating layer201and may include transistors constituting an integrated circuit. The transistors constituting an integrated circuit may be disposed on the substrate101, and the transistors may be disposed in an region between the substrate101and the first insulating layer201. The transistors constituting the integrated circuit may include a planar Metal Oxide Semiconductor FET (MOSFET), a FinFET in which an active region has a fin structure, and a Multi-Bridge Channel FET (MBCFET™) or a Gate-All-Around transistor including a plurality of channels vertically stacked on the active region, or a vertical FET (VFET), but example embodiments are not limited thereto. The integrated circuit may include a volatile memory device such as DRAM, static RAM (SRAM), or the like, and a non-volatile memory device such as PRAM, MRAM, ReRAM, a flash memory device, or the like.

The first insulating structure IL1may be disposed on the substrate101. The first insulating structure IL1may include a first etch stop layer110and a first interlayer insulating layer120disposed on the first etch stop layer110.

The first etch stop layer110may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), and silicon oxycarbide (SiOC). The first etch stop layer110may include, for example, a metal oxide and/or a metal nitride, the metal including at least one of aluminum (Al), zirconium (Zr), hafnium (Hf), titanium (Ti), ruthenium (Ru), molybdenum (Mo), tungsten (W), copper (Cu), and cobalt (Co). The first etch stop layer110may include a plurality of layers, for example, a first layer111, a second layer113, and a third layer115, which are sequentially stacked. In an example embodiment, the first layer111may include an aluminum oxide (AlO), the second layer113may include a silicon oxycarbide (SiOC), and the third layer115may include a silicon nitride (SiN). However, example embodiments of the present inventive concepts are not limited thereto, and the first etch stop layer110may be formed of a single layer.

The first interlayer insulating layer120may be formed of silicon oxide (SiO) or a low-k insulating material layer having a dielectric constant smaller than that of silicon oxide. For example, the first interlayer insulating layer120may include a low-k insulating material such as SiOC or SiOCH. For example, the first interlayer insulating layer120may include a material such as phosphor silicate glass (PSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), tetra ethyl ortho silicate (TEOS), plasma enhanced PE-TEOS (PE-TEOS), high density plasma-chemical vapor deposition (HDP-CVD) oxide, and the like.

The first interlayer insulating layer120may include a recess portion RC exposing an upper surface of the first etch stop layer110. The recess portion RC may penetrate through the first interlayer insulating layer120in a Z direction. A protrusion170P, which is a portion of the conductive line170, may extend into the recess portion RC. The recess portion RC may be a region in which the first interlayer insulating layer120is patterned to have a desired (or alternatively, predetermined) pattern in a plan view and partially removed. The recess portion RC may include regions having different widths in a Y direction in a plan view.

Contacts130may penetrate through the first insulating structure IL1to be connected to a lower wiring or a contact in a device layer105below the first insulating structure ILE The contacts130may be in contact with and connected to the conductive line170from an upper portion thereof through an upper surface thereof. A level of a lower surface of the contacts130may be lower than a level of a lower surface of the protrusion170P of the conductive line170. A level of an upper surface of the contacts130may be higher than a level of the lower surface of the protrusion170P of the conductive line170. The contacts130may have any one of a polygonal shape, a square shape, a rectangular shape, a rounded square shape, a circle, and an ellipse in plan view, parallel to the upper surface of the substrate101.

The contacts130may include a contact barrier layer131, a contact liner layer133on the contact barrier layer131, and a contact metal layer135on the contact liner layer133. The contact liner layer133may cover a side surface and a bottom surface of the contact metal layer135. The contact barrier layer131may cover a side surface and a bottom surface of the contact liner layer133. The contact barrier layer131may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), and tungsten carbon nitride (WCN). The contact liner layer133may include, for example, at least one of ruthenium (Ru), molybdenum (Mo), tungsten (W), and cobalt (Co). The contact metal layer135may include, for example, at least one of ruthenium (Ru), molybdenum (Mo), tungsten (W), copper (Cu), aluminum (Al), and cobalt (Co). In an example embodiment, in the contacts130, at least one of the contact barrier layer131and the contact liner layer133may be omitted.

The contacts130may include first contacts130_1and second contacts130_2. For example, the first contacts130_1may be spaced apart from the recess portion RC or the protrusion170P of the conductive line170. The first contacts130_1may be disposed adjacent to any one of a first side surface S1of the conductive line170and a second side surface S2of the conductive line170, which is opposite to the first side surface S1. However, example embodiments are not limited thereto. In some example embodiments, the first contacts130_1may also be disposed on a center line of the conductive line170in the X direction. For example, the second contacts130_2may at least partially overlap the recess portion RC or the protrusion170P of the conductive line170in the Z direction. The second contacts130_2may extend longer in the Y direction than the first contacts130_1. For example, the first contacts130_1may have a first length in the Y direction, and the second contacts130_2may have a second length longer than the first length in the Y direction.

The second insulating structure IL2may be disposed on the first insulating structure ILL The second insulating structure IL2may include a second etch stop layer150and a second interlayer insulating layer160on the second etch stop layer150.

The second etch stop layer150may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), and silicon oxycarbide (SiOC). The second etch stop layer150may include, for example, a metal oxide and/or a metal nitride, the metal being including at least one of aluminum (Al), zirconium (Zr), hafnium (Hf), titanium (Ti), ruthenium (Ru), molybdenum (Mo), tungsten (W), copper (Cu), and cobalt (Co). The second etch stop layer150may include a plurality of layers, for example, a first layer151, a second layer153, and a third layer155, which are sequentially stacked. In an example embodiment, the first layer151may include an aluminum oxide (AlO), the second layer153may include a silicon oxycarbide (SiOC), and the third layer155may include a silicon nitride (SiN). However, example embodiments of the present inventive concepts are not limited thereto, and the second etch stop layer150may be formed of a single layer.

The second interlayer insulating layer160may be formed of silicon oxide (SiO) or a low-k insulating material layer having a dielectric constant smaller than that of silicon oxide. For example, the second interlayer insulating layer160may include a low-k insulating material such as SiOC or SiOCH. For example, the second interlayer insulating layer160may include a material such as phosphor silicate glass (PSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), tetra ethyl ortho silicate (TEOS), plasma enhanced PE-TEOS (PE-TEOS), high density plasma-chemical vapor deposition (HDP-CVD) oxide, and the like.

The conductive line170may be disposed on the first insulating structure IL1and the contacts130. The conductive line170may have a line shape extending in the X direction in a plan view. The conductive line170may be formed by a damascene process in which an insulating layer is formed, patterned, and then a metal material layer is filled.

The conductive line170may include a barrier layer171, a liner layer173on the barrier layer171, and a metal layer175on the liner layer173. The liner layer173may cover a side surface and a bottom surface of the metal layer175. The barrier layer171may cover a side surface and a bottom surface of the liner layer173. The barrier layer171may include, for example, at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), and tungsten carbon nitride (WCN). The liner layer173may include, for example, at least one of ruthenium (Ru), molybdenum (Mo), tungsten (W), and cobalt (Co). The metal layer175may include, for example, at least one of ruthenium (Ru), molybdenum (Mo), tungsten (W), copper (Cu), aluminum (Al), and cobalt (Co).

The conductive line170may include a first portion P1on the first interlayer insulating layer120and a second portion P2on the first etch stop layer110. The second portion P2may include a protrusion170P provided to reduce electrical resistance of the conductive line170, and the second portion P2may be a portion having a thickness greater than that of the first portion P1. For example, the first portion P1may have a first thickness T1on an upper surface of the first interlayer insulating layer120, and the second portion P2may have a second thickness T2, which is greater than the first thickness T1, on an upper surface of the first etch stop layer110. The second thickness T2may correspond to a thickness between a lower surface of the protrusion170P and an upper surface of the conductive line170. In an example embodiment, the second thickness T2may be thicker than the first thickness T1by about 15 nm to about 20 nm. The protrusion170P may extend further downwardly than the second insulating structure IL2and may be disposed in the recess portion RC of the first interlayer insulating layer120. The protrusion170P may be in contact with the first etch stop layer110. The protrusion170P may be disposed between the first contacts130_1in the X direction in which one conductive line170extends.

The first portion P1may overlap at least one of the contacts130in the Z direction. Because the conductive line170includes the second portion P2including the protrusion170P, electrical resistance may be reduced by securing a large space filled with metal in the conductive line170.

A planar shape of the protrusion170P needs to be designed in consideration of the disposition and shape of the contacts130disposed immediately below the conductive line170. According to an example embodiment of the present inventive concepts, the space capable of increasing the thickness of the conductive line170may be sufficiently secured, but a separate layer may be added to a layout of the semiconductor device to reduce or minimize damages applied to the contacts130when the recess portion RC or the protrusion170P is formed. The layer may have a pattern satisfying a design rule considered when designing a semiconductor device. Accordingly, the layer may be designed so that there is no problem in the patterning of the corresponding layer in the photolithography process step.

As an example embodiment of the present inventive concepts, a layer of a region indicated by a dotted line inFIG.1may be added to the layout of the semiconductor device. The layer may be provided to form the recess portion RC or the protrusion170P. When the thickness of the conductive line170increases, the electrical resistance may decrease, but an etching process of the first interlayer insulating layer120performed to increase the thickness of the conductive line170may damage the contacts130. That is, if an area in which the protrusion170P of the conductive line170is disposed is secured as much as possible to reduce electrical resistance, an area of the contact130disposed below the conductive line170and overlapping the protrusion170P may increase, thereby increasing a risk of damages to the contacts130by the etching process. Accordingly, a pattern of the layer needs to be properly designed so that the reduction in electrical resistance of the conductive line170can be secured as much as possible, while reducing or minimizing damage to the contacts130.

In an example embodiment of manufacturing the semiconductor device100using a layout including the layer having the optimal design, a protrusion170P of the conductive line170may be spaced apart from the first contacts130_1, may have a desired (or alternatively, predetermined) pattern in a plan view such that at least a portion of the conductive line170overlaps the second contacts130_2in the Z direction. For example, as shown inFIG.1, the protrusion170P of the conductive line170may include a first region R1having a first width W1in the Y direction and a second region having a second width W2, narrower than the first width W1, in the Y direction. One of side surfaces of the first region R1, extending in the X direction, and one of side surfaces of the second region R2, extending in the X direction, may be shifted from each other. A side portion SP which is bent due to a difference in width may be formed between the first region R1and the second region R2of the conductive line170. The side surface SP may face a side surface of the first contacts130_1that overlaps the conductive line170in the Z direction. However, a planar shape of the protrusion170P of the conductive line170is not limited to the illustrated one, and may be variously changed according to the disposition and shape of the contacts130.

FIG.3is a cross-sectional view illustrating a semiconductor device according to an example embodiment.FIG.3illustrates a region corresponding toFIG.2A.

Referring toFIG.3, in another region of the semiconductor device100, second contacts130_2may overlap a protrusion170P of the conductive line170in a Z direction. In this case, a second portion P2of the conductive line170may include a portion surrounding upper surfaces and upper regions of side surfaces of the second contacts130_2. The second contacts130_2may have a shape in which a length in the Y direction is longer than a length in the X direction in a plan view, and may extend longer in the Y direction than the first contacts130_1. The conductive line170may have a first thickness at the second portion P2, and a second thickness smaller than the first thickness on the second contacts130_2.

FIGS.4to17Bare diagrams illustrating a method of manufacturing a semiconductor device according to a process sequence according to an example embodiment.FIGS.4,6, and8are plan views according to the process sequence of the region corresponding toFIG.1, respectively, andFIGS.5A,5B,7A,7B, andFIGS.9A to17Bare cross-sectional views according to the process sequence according to a region corresponding toFIGS.2A and2B, respectively.

Referring toFIGS.4,5A, and5B, a first insulating structure IL1and contacts130may be formed on a substrate101, a second insulating structure IL2may be formed on the first insulating structure ILL a hard mask pattern185may be formed on the second insulating structure IL2, and a trench T opening a portion of the hard mask pattern185may be formed.

Before forming the first insulating structure ILL an integrated circuit including transistors may be formed on the substrate101through a front end of line (FEOL) process. The integrated circuit including the transistors may be formed in a region between the substrate101and the first insulating structure IL1.

Forming the first insulating structure IL1may include sequentially forming a first etch stop layer110and a first interlayer insulating layer120. Forming the first etch stop layer110may include forming a plurality of layers, for example, a first layer111, a second layer113, and a third layer115.

After the first insulating structure IL1is patterned and filled with a conductive material, a planarization process may be performed to form contacts130. Forming the contacts130may include forming a contact barrier layer131, a contact liner layer133, and a contact metal layer135. A chemical vapor deposition process or an atomic layer deposition process may be performed to form a contact barrier layer131and a contact liner layer133. The contacts130may be formed by performing a chemical vapor deposition process or an atomic layer deposition process.

Forming the second insulating structure IL2may include sequentially forming a second etch stop layer150and a second interlayer insulating layer160. Forming the second etch stop layer150may include forming a plurality of layers, for example, a first layer151, a second layer153, and a third layer155.

A hard mask pattern185including a first mask pattern181and a second mask pattern183may be formed on the second insulating structure IL2, and a trench T exposing a portion of the second insulating structure IL2may be formed by performing a separate lithography process and an etching process and patterning the hard mask pattern185. The first mask pattern181may include titanium nitride (TiN), and the second mask pattern183may include silicon oxycarbide (SiOC). The trench T may have a line shape extending in an X direction.

Referring toFIGS.6,7A, and7B, a photoresist187may be formed on a hard mask pattern185.

The photoresist187may partially cover a second insulating structure IL2exposed by the trench T, and may be formed to cover an upper surface of the hard mask pattern185.

Referring toFIGS.8,9A and9B, an opening OP may be formed by performing exposure and development processes on a photoresist187. The opening OP may be formed by partially removing the photoresist187on a region corresponding to the protrusion170P of the conductive line170ofFIG.1. The opening OP may be formed to have a desired (or alternatively, predetermined) pattern in the trench T, as shown inFIG.8.

A pattern of the opening OP may be selected as a design capable of securing a reduction in electrical resistance of the conductive line170to be formed in a subsequent process as much as possible while reducing or minimizing damage to contacts130. Hereinafter, a region overlapping the region in which the opening OP is formed in the photoresist187will be referred to as a recess region A, and the region overlapping the region in which the opening OP is not formed in the photoresist187will be referred to as a normal region B.

Referring toFIGS.10A and10B, a portion of a second interlayer insulating layer160may be etched using a photoresist187as an etching mask in a recess region A. The second interlayer insulating layer160may be partially removed under an opening OP. By etching a portion of the second interlayer insulating layer160, a third layer155of a second etch stop layer150may be exposed in the recess region A.

Referring toFIGS.11A and11B, a photoresist187may be removed. The photoresist187may be removed by performing a stripping or ashing process. The photoresist187may be removed using, for example, a solution containing, H2O2, H2SO4or the like, or may be removed using a gas such as O2, N2, H2.

Referring toFIGS.12A and12B, a portion of a third layer155of a second etch stop layer150may be etched using the second interlayer insulating layer160as an etching mask in the recess region A. In the recess region A, a portion of a second layer153of the second etch stop layer150may be exposed.

Referring toFIGS.13A and13B, a portion of a second layer153of a second etch stop layer150may be etched using a second interlayer insulating layer160as an etching mask in the recess region A, and a portion of the second interlayer insulating layer160may be etched using a hard mask pattern185as an etching mask in a normal region B. The hard mask pattern185in the recess region A may be removed during or after an etching process in the present step.

Referring toFIGS.14A and14B, a portion of a first layer151of a second etch stop layer150may be etched using a second layer153of the second etch stop layer150as an etch mask in the recess region A, and a portion of a third layer155of the second etch stop layer150may be etched using a second interlayer insulating layer160as an etching mask in the normal region B.

Referring toFIGS.15A and15B, a portion of a first interlayer insulating layer120may be etched using a second layer153of a second etch stop layer150as an etching mask in the recess region A, and a portion of a first layer151of a first etch stop layer110may be etched using a second interlayer insulating layer160as an etching mask in the normal region B. A recess portion RC may be formed in the first interlayer insulating layer120, and the recess portion RC may expose the first etch stop layer110in the recess region A. The recess portion RC may be formed in the first interlayer insulating layer120in a planar shape corresponding to the opening OP ofFIG.8. Because first contacts130_1are spaced apart from the recess portion RC, the first contacts may not be exposed to an etching process. Also, the first contacts130_1may be protected from an etching process by the first layer151of the second etch stop layer150. However, in some example embodiments, second contacts130_2may be partially exposed to the recess portion RC.

Referring toFIGS.16A and16B, a portion of a first layer151of a second etch stop layer150may be etched using a second interlayer insulating layer160as an etching mask in the normal region B. Accordingly, upper surfaces of contacts130may be exposed.

Referring toFIGS.17A and17B, a conductive line170may be formed by forming material layers constituting the conductive line and performing a planarization process. A protrusion170P may be formed in the recess portion RC, and a second portion P2of the conductive line170may have a thickness greater than a thickness of a first portion P1of the conductive line170. The planarization process may be performed up to, for example, a portion indicated by a dotted line in the drawing, so that an upper surface of the second interlayer insulating layer160may be exposed and the conductive line170may be formed in a line-shaped pattern. Accordingly, the semiconductor device100ofFIG.1may be manufactured.

As set forth above, according to the above example embodiments of the present inventive concepts, by optimizing or appropriately designing a planar shape of the protrusion of the conductive line, a semiconductor device having improved electrical characteristics and reliability may be provided. In other words, according to the above example embodiments, a semiconductor device having improved electrical characteristics and reliability may be implemented by reducing the electrical resistance of the conductive line, while reducing or minimizing etch damage of contacts, which are disposed below the conductive line.

Some advantages and effects of the present inventive concepts may be easily understood in view of the above specific example embodiments of the present inventive concepts. However, various and advantageous advantages and effects of the present inventive concepts are not limited to the advantages and effects of the above example embodiments.

While some example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present inventive concepts as defined by the appended claims.