Patent ID: 12218051

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Exemplary embodiments for redistribution layers formed on integrated circuit components are disclosed. The redistribution layers on the integrated circuit components of the present disclosure include one or more arrays of conductive contacts that are configured and arranged to allow a bonding wave to displace air between the redistribution layers during bonding. This configuration and arrangement of the one or more arrays minimize discontinuities, such as pockets of air (i.e. voids) to provide an example, between the redistribution layers during the bonding.

FIG.1AandFIG.1Brespectively illustrate exemplary integrated circuit component and semiconductor device including bonded integrated circuit components according to exemplary embodiments of the present disclosure. As illustrated inFIG.1A, an exemplary integrated circuit component100includes a semiconductor substrate101having electronic circuitry formed therein, and an interconnection structure102disposed on the semiconductor substrate101. In some embodiments, the integrated circuit component100includes an active region100A in which the electronic circuitry is formed and a periphery region100B surrounding the active region100A. A redistribution layer104is fabricated on the interconnection structure102of the integrated circuit component100in a back-end-of-line (BEOL) process. The redistribution layer104formed on the interconnection structure102of the integrated circuit component100may serve as a bonding layer when the integrated circuit component100is bonded with other components. In the exemplary embodiment illustrated inFIG.1A, the electronic circuitry formed in the semiconductor substrate101includes analog and/or digital circuitry situated within a semiconductor stack having one or more conductive layers, also referred to as metal layers, interdigitated with one or more non-conductive layers, also referred to as insulation layers. However, one skilled in the relevant art(s) will recognize the electronic circuitry may include one or more mechanical and/or electromechanical devices without departing from the spirit and scope of the present disclosure.

The semiconductor substrate101may be made of silicon or other semiconductor materials. Alternatively, the semiconductor substrate101may include other elementary semiconductor materials such as germanium. In some embodiments, the semiconductor substrate101is made of a compound semiconductor such as sapphire, silicon carbide, gallium arsenic, indium arsenide, or indium phosphide. In some embodiments, the semiconductor substrate101is made of an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, the semiconductor substrate101includes an epitaxial layer. For example, the semiconductor substrate101has an epitaxial layer overlying a bulk semiconductor.

The semiconductor substrate101may further include isolation features (not shown), such as shallow trench isolation (STI) features or local oxidation of silicon (LOCOS) features. Isolation features may define and isolate various semiconductor elements. The semiconductor substrate101may further include doped regions (not shown). The doped regions may be doped with p-type dopants, such as boron or BF2, and/or n-type dopants, such as phosphorus (P) or arsenic (As). The doped regions may be formed directly on the semiconductor substrate101, in a P-well structure, in an N-well structure, or in a dual-well structure.

The electronic circuitry including the above-mentioned isolation features and semiconductor elements (e.g., transistors (e.g., metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high-voltage transistors, high-frequency transistors, p-channel and/or n channel field effect transistors (PFETs/NFETs), etc.), diodes, and/or other applicable elements) may be formed over the semiconductor substrate101. Various processes may be performed to form the isolation features and semiconductor elements, such as deposition, etching, implantation, photolithography, annealing, and/or other applicable processes. In some embodiments, the electronic circuitry including the isolation features and semiconductor elements are formed in the semiconductor substrate101in a front-end-of-line (FEOL) process.

In some embodiments, the interconnection structure102includes dielectric layers, conductive vias embedded in the dielectric layers, and conductive wirings formed between the dielectric layers, wherein different layers of the conductive wirings are electrically connected to one another through the conductive vias. Furthermore, the interconnection structure102is electrically connected to the electronic circuitry formed in the semiconductor substrate101. In some embodiments, at least one seal ring105and at least one alignment mark are formed in the interconnection structure102, wherein the seal ring105and the alignment mark are formed within the periphery region100B of the integrated circuit component100, the seal ring105surrounds the active region100A of the integrated circuit component100, and the alignment mark is formed within a region out of the seal ring105. In some embodiments, pluralities of alignment marks are formed around corners of the integrated circuit component100. The number of the above-mentioned seal ring105and alignment mark(s) is not limited in this disclosure.

In the exemplary embodiment illustrated inFIG.1A, the redistribution layer104represents a conductive layer (e.g., a metal layer) from among the one or more conductive layers of the semiconductor stack which is utilized for electrically coupling the electronic circuitry to other electrical, mechanical, and/or electromechanical devices. For example, the redistribution layer104may be used to electrically couple the electronic circuitry to an integrated circuit package, such as a through-hole package, a surface mount package, a pin grid array package, a flat package, a small outline package, a chip-scale package, and/or a ball grid array to provide some examples.

As another example and as illustrated inFIG.1B, a semiconductor device includes a first integrated circuit component100.1, a first redistribution layer104.1, a second integrated circuit component100.2and a second redistribution layer104.2, wherein the first redistribution layer104.1and the second redistribution layer104.2are between the first integrated circuit component100.1and the second integrated circuit component100.2. An exemplary first integrated circuit component100.1includes a first semiconductor substrate101.1having first electronic circuitry formed therein, and a first interconnection structure102.1disposed on the first semiconductor substrate101.1. An exemplary second integrated circuit component100.2includes a second semiconductor substrate101.2having second electronic circuitry formed therein, and a second interconnection structure102.2disposed on the semiconductor substrate101.2. The first redistribution layer104.1from among a first semiconductor stack associated with first electronic circuitry may be electrically and/or mechanically coupled to the second redistribution layer104.2from among a second semiconductor stack associated with second electronic circuitry to electrically couple the first electronic circuitry and the second electronic circuitry. In this exemplary embodiment, the first redistribution layer104.1is configured and arranged to be electrically and/or mechanically coupled to the second redistribution layer104.2. In an exemplary embodiment, the first redistribution layer104.1is bonded to the second redistribution layer104.2using hybrid bonding, direct bonding, surface activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, thermo-compression bonding, reactive bonding, transient liquid phase diffusion bonding and/or any other well-known bonding technique which is apparent to those skilled in the relevant art(s) without departing from the spirit and scope of the present disclosure. In this exemplary embodiment, these afore-mentioned bonding techniques utilize a bonding wave to electrically and/or mechanically couple the first redistribution layer104.1and the second redistribution layer104.2. As to be described in further detail below, the first redistribution layer104.1and the second redistribution layer104.2are configured and arranged to minimize discontinuities, such as pockets of air to provide an example, between the first redistribution layer104.1and the second redistribution layer104.2during the bonding of the first redistribution layer104.1and the second redistribution layer104.2.

FIG.2A,FIG.2BandFIG.2Cillustrate exemplary semiconductor wafers including the exemplary integrated circuit components according to exemplary embodiments of the present disclosure. Referring toFIG.2A, a semiconductor device fabrication operation is utilized to manufacture multiple integrated circuit components100.1through100.nin a semiconductor wafer200. The semiconductor wafer200includes multiple integrated circuit components100.1through100.narranged in array. In some embodiments, the semiconductor wafer200includes a semiconductor substrate202having electronic circuitry formed therein and an interconnection structure203disposed on the semiconductor substrate202. In some embodiments, each one of the integrated circuit component100.1through100.nincluded in the semiconductor wafer200includes an active region100A having electronic circuitry formed therein and a periphery region100B surrounding the active region100A. The semiconductor device fabrication operation uses a predetermined sequence of photographic and/or chemical processing operations to form the multiple integrated circuit components100.1through100.nin the first semiconductor wafer200. The predetermined sequence of photographic and/or chemical processing operations may include deposition, removal, patterning, and modification. The deposition is an operation used to grow, coat, or otherwise transfer a material onto the semiconductor substrate and may include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), and/or molecular beam epitaxy (MBE) to provide some examples. The removal is an operation to remove material from the semiconductor substrate and may include wet etching, dry etching, and/or chemical-mechanical planarization (CMP) to provide some examples. The patterning, often referred to as lithography, is an operation to shape or alter material of the semiconductor substrate to form various geometric shapes of the analog and/or digital circuitry for the electronic device. The modification of electrical properties is an operation to alter physical, electrical, and/or chemical properties of material of the semiconductor substrate, typically, by ion implantation. In an exemplary embodiment, a semiconductor foundry may utilize this fabrication flow to fabricate the analog and/or digital circuitry for the electronic device on the semiconductor substrate.

In the exemplary embodiment illustrated inFIG.2A, the integrated circuit components100.1through100.nare formed in and/or on the semiconductor substrate202using a first series of fabrication operations, referred to as front-end-of-line processing, and a second series of fabrication operations, referred to as back-end-of-line processing. The front-end-of-line processing represents a first series of photographic and/or chemical processing operations to form corresponding electronic circuitry of the multiple integrated circuit components100.1through100.nin and/or on the semiconductor substrate202. The back-end-of-line processing represents a second series of photographic and/or chemical processing operations to form corresponding interconnection structure203of the multiple integrated circuit components100.1through100.non the semiconductor substrate202to form the semiconductor wafer200. In an exemplary embodiment, the integrated circuit components100.1through100.nincluded in the semiconductor wafer200may be similar and/or dissimilar to one other.

As shown inFIG.2A, the semiconductor substrate202is a portion of the semiconductor wafer200. The semiconductor substrate202may be made of silicon or other semiconductor materials. Additionally, the semiconductor substrate202may include other elementary semiconductor materials such as germanium. In some embodiments, the semiconductor substrate202is made of a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, or indium phosphide. In some embodiments, the semiconductor substrate202is made of an alloy semiconductor such as sapphire, silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, the semiconductor substrate202includes an epitaxial layer. For example, the semiconductor substrate202has an epitaxial layer overlying a bulk semiconductor.

The semiconductor substrate202may further include isolation features (not shown), such as shallow trench isolation (STI) features or local oxidation of silicon (LOCOS) features. Isolation features may define and isolate various semiconductor elements. The semiconductor substrate202may further include doped regions (not shown). The doped regions may be doped with p-type dopants, such as boron or BF2, and/or n-type dopants, such as phosphorus (P) or arsenic (As). The doped regions may be formed directly on the semiconductor substrate202, in a P-well structure, in an N-well structure, or in a dual-well structure.

In some embodiments, the interconnection structure203includes dielectric layers, conductive vias embedded in the dielectric layers, and conductive wirings between the dielectric layers, wherein different layers of the conductive wirings are electrically connected to one another through the conductive vias.

A redistribution layer204is formed over the semiconductor wafer200. In some embodiments, the process for fabricating the redistribution layer204over the semiconductor wafer200includes: forming a dielectric layer over the semiconductor wafer200; patterning the dielectric layer to form a plurality of openings in the dielectric layer to expose conductive pads of the semiconductor wafer200; depositing a conductive material over the semiconductor wafer200such that the dielectric layer and the conductive pads exposed by the openings in the dielectric layer are covered by the conductive material, wherein the conductive material not only covers the dielectric layer and the conductive pads, but also covers sidewall surfaces of the openings and completely fill the openings; performing a grinding process (e.g., CMP process) to partially remove an excess portion of conductive material until the top surface of the dielectric layer206is exposed so as to form arrays of conductive contacts208(e.g., metal vias and/or metal pads) in the dielectric layer206. The redistribution layer204including the dielectric layer206and the arrays of conductive contacts208may serve as a bonding layer when a wafer level bonding process is performed to bond the semiconductor wafer200with another wafer.

As illustrated inFIG.2B, a first semiconductor wafer200.1and a second semiconductor wafer200.2to be bonded with each other are provided. In some embodiments, two different types of wafers200.1and200.2are provided. In other words, the integrated circuit components100.1through100.nincluded in first semiconductor wafer200.1and the integrated circuit components100.1through100.nincluded in second semiconductor wafer200.2may have different architectures and perform different functions. For example, the first semiconductor wafer200.1is a sensor wafer including a plurality of image sensor chips (e.g., CMOS image sensor chips) and the second semiconductor wafer200.2is an application-specific integrated circuit (ASIC) wafer including a plurality of ASIC units corresponding to the image sensor chips. The image sensor chips included in the sensor wafer may be back-side illuminated CMOS image sensors (BSI-CIS) capable of sensing light from the back-surface of the CMOS image sensors, and the redistribution layer204may be formed over active surfaces (e.g., surfaces opposite to the back-surface of the CMOS image sensors) of the CMOS image sensors. In some alternative embodiments, two similar or same wafers200.1and200.2are provided. In other words, the integrated circuit components100.1through100.nincluded in first semiconductor wafer200.1and the integrated circuit components100.1through100.nincluded in second semiconductor wafer200.2may have the same or similar architecture and perform the same or similar function.

Before bonding the first semiconductor wafer200.1and the second semiconductor wafer200.2, a first redistribution layer204.1and a second redistribution layer204.2are formed over the first semiconductor wafer200.1and the second semiconductor wafer200.2respectively. The process for forming the first redistribution layer204.1and the second redistribution layer204.2may be similar with the process for forming the redistribution layer204illustrated inFIG.2A.

In some embodiments, the process for fabricating the first redistribution layer204.1over the first semiconductor wafer200.1includes: forming a first dielectric layer over the first semiconductor wafer200.1; patterning the first dielectric layer to form a plurality of first openings in the first dielectric layer206.1to expose first conductive pads of the first semiconductor wafer200.1; depositing a first conductive material over the first semiconductor wafer200.1such that the first dielectric layer206.1and the first conductive pads exposed by the first openings in the first dielectric layer206.1are covered by the first conductive material, wherein the first conductive material not only covers the first dielectric layer206.1and the first conductive pads, but also covers sidewall surfaces of the first openings and completely fill the first openings; performing a first grinding process (e.g., CMP process) to partially remove an excess portion of first conductive material until the top surface of the first dielectric layer206.1is exposed so as to form multiple arrays of conductive contacts208.1(e.g., metal vias and/or metal pads) in the first dielectric layer206.1. In some embodiments, the process for fabricating the second redistribution layer204.2over the second semiconductor wafer200.1includes: forming a second dielectric layer206.2over the second semiconductor wafer200.2; patterning the second dielectric layer206.2to form a plurality of second openings in the second dielectric layer206.2to expose second conductive pads of the second semiconductor wafer200.2; depositing a second conductive material over the second semiconductor wafer200.2such that the second dielectric layer206.2and the second conductive pads exposed by the second openings are covered by the second conductive material, wherein the second conductive material not only covers the second dielectric layer206.2and the second conductive pads, but also covers sidewall surfaces of the second openings and completely fill the second openings; performing a second grinding process (e.g., CMP process) to partially remove an excess portion of second conductive material until the top surface of the second dielectric layer206.2is exposed so as to form multiple arrays of conductive contacts208.2(e.g., metal vias and/or metal pads) in the second dielectric layer206.2.

In some embodiments, the arrays of conductive contacts208.1slightly protrude from the top surface of the first dielectric layer206.1and the arrays of conductive contacts208.2slightly protrude from the top surface of the second dielectric layer206.2because the first and dielectric layers206.1and206.2are polished at a relatively higher polishing rate while the conductive material is polished at a relatively lower polishing rate during the CMP processes.

As illustrated inFIG.2BandFIG.2C, after the first and second redistribution layers204.1and204.2are formed over the first and second semiconductor wafers200.1and200.2, the first semiconductor wafer200.1having the first redistribution layer204.1formed thereon is flipped onto the second redistribution layer204.2formed on the second semiconductor wafer200.2such that the multiple arrays of conductive contacts208.1of the first redistribution layer204.1are substantially aligned with the multiple arrays of conductive contacts208.2of the second redistribution layer204.2. Then, the first semiconductor wafer200.1is bonded to the second semiconductor wafer200.2through the first and second redistribution layers204.1and204.2to form a semiconductor device210. In some embodiments, the bonding interface between the first redistribution layer204.1and the second redistribution layer204.2in the bonded structure (e.g., the semiconductor device)210is void free after performing the bonding process. This bonding may include hybrid bonding, direct bonding, surface activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, thermo-compression bonding, reactive bonding, transient liquid phase diffusion bonding and/or any other well-known bonding technique which is apparent to those skilled in the relevant art(s) without departing from the spirit and scope of the present disclosure. As to be described in further detail below, the first redistribution layer204.1formed over the first semiconductor wafer200.1and the second redistribution layer204.2formed over the second semiconductor wafer200.2are configured and arranged to minimize discontinuities, such as pockets of air to provide an example, between the first redistribution layer204.1and the second redistribution layer204.2.

Since the arrays of conductive contacts208.1slightly protrude from the top surface of the first dielectric layer206.1and the arrays of conductive contacts208.2slightly protrude from the top surface of the second dielectric layer206.2, an air gap may be generated between the first and second redistribution layers204.1and204.2of the first and second semiconductor wafers200.1and200.2. After aligning the multiple arrays of conductive contacts208.1and208.2on the first and second semiconductor wafers200.1and200.2, a wafer-to-wafer hybrid bonding process may be performed such that the first and second semiconductor wafer200.1and200.2are physically and electrically bonded with each other. During the hybrid bonding process of the first and second semiconductor wafer200.1and200.2, a bonding wave is applied to the first and second semiconductor wafer200.1and200.2to drive away air between the first and second redistribution layers204.1and204.2.

It is noted that air may be trapped between the first and second redistribution layers204.1and204.2during the hybrid bonding process if the layout of the arrays of conductive contacts is not well configured and arranged. For example, when two most adjacent arrays of conductive contacts which extend parallel with each other are arranged too close, it is difficult to displace the air trapped between the two most adjacent arrays of conductive contacts, and accordingly, voids may be generated between the two most adjacent arrays of conductive contacts. In other words, voids may generate at the bonding interface between the first and second redistribution layers204.1and204.2and deteriorate device performance. In an exemplary embodiment, the arrays of conductive contacts are properly configured and arranged as illustrated inFIG.4AthroughFIG.4Ito prevent voids from trapping at the bonding interface between the first and second redistribution layers204.1and204.2.

In some embodiments, the above-mentioned hybrid bonding process of the first semiconductor wafer200.1and the second semiconductor wafer200.2includes simultaneously performed metal-to-metal bonding between conductive contacts208.1and208.2as well as dielectric-to-dielectric bonding between the first and second dielectric layers206.1and206.2. For example, the metal-to-metal bonding between conductive contacts208.1and208.2includes via-to-via bonding, pad-to-pad bonding or via-to-pad bonding.

FIG.3AthroughFIG.3Jillustrate exemplary redistribution layers of the exemplary integrated circuit components according to exemplary embodiments of the present disclosure. A redistribution layer300as illustrated inFIG.3A, a redistribution layer310as illustrated inFIG.3B, a redistribution layer318as illustrated inFIG.3C, a redistribution layer320as illustrated inFIG.3D, a redistribution layer322as illustrated inFIG.3E, a redistribution layer332as illustrated inFIG.3F, a redistribution layer334as illustrated inFIG.3G, a redistribution layer336as illustrated inFIG.3H, a redistribution layer338as illustrated inFIG.3I, and a redistribution layer340as illustrated inFIG.3Jeach represents a conductive layer from among one or more conductive layers of a semiconductor stack of an integrated circuit, such as the integrated circuit component100to provide an example. The redistribution layer300, the redistribution layer310, the redistribution layer318, the redistribution layer320, the redistribution layer322, the redistribution layer332, the redistribution layer334, the redistribution layer336, the redistribution layer338, and/or the redistribution layer340may be utilized for electrically coupling the integrated circuit to other electrical, mechanical, and/or electromechanical devices. In the exemplary embodiment illustrated inFIG.3A, the redistribution layer300includes an array of first conductive contacts302. As illustrated inFIG.3A, the array of first conductive contacts302extends along a first direction D1, such as an x-axis of a Cartesian coordinate system to provide an example, along a first side of the integrated circuit component. Those skilled in the relevant art(s) will recognize the array of first conductive contacts302may alternatively extend along a second direction D2, such as a y-axis of a Cartesian coordinate system to provide an example, along a second side of the redistribution layer300without departing from the spirit and scope of the present disclosure. In an exemplary embodiment, the array of first conductive contacts302includes conductive contacts304.1.1through304.i.karranged in a series of i rows and k columns to form an array. In some embodiments, the arrangement pitch of the conductive contacts304.1.1through304.i.kranges from about 3 micrometers to about 5 micrometers. The conductive contacts304.1.1through304.i.kmay include one or more conductive materials such as tungsten (W), aluminum (Al), copper (Cu), gold (Au), silver (Ag), or platinum (Pt) to provide some examples. However, the conductive contacts304.1.1through304.i.kmay alternatively, or additionally, include other materials, such as silicide, for example, nickel silicide (NiSi), sodium silicide (Na2Si), magnesium silicide (Mg2Si), platinum silicide (PtSi), titanium silicide (TiSi2), tungsten silicide (WSi2), or molybdenum disilicide (MoSi2) to provide some examples, as will be recognize by those skilled in the relevant art(s) without departing from the spirit and scope of the present disclosure.

In the exemplary embodiment illustrated inFIG.3A, the redistribution layer300may be bonded to other redistribution layers of other electrical, mechanical, and/or electromechanical devices using hybrid bonding, direct bonding, surface activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, thermocompression bonding, reactive bonding, transient liquid phase diffusion bonding and/or any other well-known bonding technique which is apparent to those skilled in the relevant art(s) without departing from the spirit and scope of the present disclosure. In this exemplary embodiment, these bonding techniques listed above utilize a bonding wave to electrically and/or mechanically couple the redistribution layer300to other redistribution layers of other electrical, mechanical, and/or electromechanical devices. The configuration and arrangement of the array of conductive contacts302minimizes discontinuities, such as pockets of air to provide an example, between these redistribution layers. For example, the array of first conductive contacts302within the redistribution layer300allows the bonding wave to displace air between the redistribution layer300to other redistribution layers of other electrical, mechanical, and/or electromechanical devices during the bonding of these redistribution layers.

In the exemplary embodiment illustrated inFIG.3B, the redistribution layer310includes an array of first conductive contacts312and an array of second conductive contacts314. As illustrated inFIG.3B, the array of first conductive contacts312extends along the first direction D1, such as the x-axis of the Cartesian coordinate system to provide an example, along a first side of the integrated circuit component and the array of second conductive contacts314extends along the second direction D2, such as a y-axis of the Cartesian coordinate system to provide an example, along a second side of the integrated circuit component. In an exemplary embodiment, the array of first conductive contacts312and the array of second conductive contacts314include conductive contacts that are configured and arranged in a substantially similar manner as the array of first conductive contacts302as described above inFIG.3A. Those skilled in the relevant art(s) will recognize that other configurations and arrangements are possible for the array of first conductive contacts312and the array of second conductive contacts314without departing from the spirit and scope of the present disclosure. For example, the array of first conductive contacts312and the array of second conductive contacts314may extend along the first direction D1along a first side and a third side, respectively, of the integrated circuit component as illustrated inFIG.3C. As another example, the array of first conductive contacts312and the array of second conductive contacts314may extend along the second direction D2along the second side and a fourth side, respectively, of the integrated circuit component as illustrated inFIG.3D.

In the exemplary embodiment illustrated inFIG.3B, the redistribution layer310may be bonded to other redistribution layers of other electrical, mechanical, and/or electromechanical devices in a substantially similar manner as the redistribution layer300as described above inFIG.3B. In this exemplary embodiment, these bonding techniques listed above utilize a bonding wave to electrically and/or mechanically couple the redistribution layer310to other redistribution layers of other electrical, mechanical, and/or electromechanical devices. The configuration and arrangement of the array of first conductive contacts312and the array of second conductive contacts314minimize discontinuities, such as pockets of air to provide an example, between these redistribution layers. For example, the configuration and arrangement of the array of first conductive contacts312and the array of second conductive contacts314allows the bonding wave to displace air between the redistribution layer310and the other redistribution layers of other electrical, mechanical, and/or electromechanical devices during the bonding of these redistribution layers.

Additionally, in the exemplary embodiment illustrated inFIG.3B, the redistribution layer310includes a separation, or exhaust pathway316, between the array of first conductive contacts312and the array of second conductive contacts314to allow the air to be displaced during the bonding of the redistribution layer310and the other redistribution layers of other electrical, mechanical, and/or electromechanical devices during the bonding of these redistribution layers. In some situations, if the exhaust pathway316were not present, namely, the array of first conductive contacts312intersects or overlaps the array of second conductive contacts314, one or more discontinuities may form approximate to an area within the redistribution layer310where the array of first conductive contacts312intersects the array of second conductive contacts314. This intersection traps the air during the bonding of the redistribution layer310and the other redistribution layers of other electrical, mechanical, and/or electromechanical devices during the bonding of these redistribution layers forming the one or more discontinuities.

In the exemplary embodiment illustrated inFIG.3E, the redistribution layer322includes an array of first conductive contacts324, an array of second conductive contacts326, an array of third conductive contacts328, and an array of fourth conductive contacts330. As illustrated inFIG.3E, the array of first conductive contacts324and the array of third conductive contacts328extend along the first direction D1, such as the x-axis of the Cartesian coordinate system to provide an example, along a first side and a third side, respectively, of the integrated circuit component. The array of second conductive contacts326and the array of fourth conductive contacts330extend along the second direction D2, such as the y-axis of the Cartesian coordinate system to provide an example, along a second side and a fourth side, respectively, of the integrated circuit component. In an exemplary embodiment, lengths of the array of first conductive contacts324and the array of third conductive contacts328in the first direction D1are less than one-half a length of the redistribution layer322in the first direction D1. Similarly, in this exemplary embodiment, lengths of the array of second conductive contacts326and the array of fourth conductive contacts330in the second direction D2are less than one-half a length of the redistribution layer322in the second direction D2. In another exemplary embodiment, the array of first conductive contacts324, the array of second conductive contacts326, the array of third conductive contacts328, and the array of fourth conductive contacts330include conductive contacts that are configured and arranged in a substantially similar manner as the array of first conductive contacts302as described above inFIG.3A. Those skilled in the relevant art(s) will recognize that other configurations and arrangements are possible for the array of first conductive contacts324, the array of second conductive contacts326, the array of third conductive contacts328, and the array of fourth conductive contacts330without departing from the spirit and scope of the present disclosure. For example, the array of first conductive contacts324and the array of third conductive contacts328may be mirrored along an axis of the second direction D2, namely the y-axis of the Cartesian coordinate system to provide an example, as illustrated inFIG.3F. Moreover, those skilled in the relevant art(s) will recognize the redistribution layer322need not include all of the array of first conductive contacts324, the array of second conductive contacts326, the array of third conductive contacts328, and the array of fourth conductive contacts330without departing from the spirit and scope of the present disclosure. For example, the redistribution layer334includes the array of second conductive contacts and the array of fourth conductive contacts330as illustrated inFIG.3G. As another example, the redistribution layer336includes the array of first conductive contacts324extending along the first direction D1and the array of second conductive contacts326extending along the second direction D2as illustrated inFIG.3H. As yet another example, the redistribution layer338includes the array of first conductive contacts324extending along the first direction D1and the array of third conductive contacts328extending along the first direction D1as illustrated inFIG.3I. As yet another example, the redistribution layer340includes the array of first conductive contacts324extending along the first direction D1and the array of fourth conductive contacts330extending along the second direction D2as illustrated inFIG.3J.

Furthermore, those skilled in the relevant arts will further recognize the redistribution layer300as illustrated inFIG.3A, the redistribution layer310as illustrated inFIG.3B, the redistribution layer322as illustrated inFIG.3E, the redistribution layer332as illustrated inFIG.3F, the redistribution layer334as illustrated inFIG.3G, the redistribution layer336as illustrated inFIG.3H, the redistribution layer338as illustrated inFIG.3I, and/or the redistribution layer340as illustrated inFIG.3Jmay be rotated, for example, by 90 degrees, 180 degrees, and/or 270 degrees, in a clockwise or counter-clockwise manner to form additional exemplary redistribution layers without departing from the spirit and scope of the present disclosure.

FIG.4AthroughFIG.4Iillustrate exemplary semiconductor wafers having the exemplary redistribution layers according to exemplary embodiments of the present disclosure. A semiconductor wafer400as illustrated inFIG.4A, a semiconductor wafer410as illustrated inFIG.4B, a semiconductor wafer420as illustrated inFIG.4C, a semiconductor wafer430as illustrated inFIG.4D, a semiconductor wafer440as illustrated inFIG.4E, a semiconductor wafer450as illustrated inFIG.4F, a semiconductor wafer460as illustrated inFIG.4G, a semiconductor wafer470as illustrated inFIG.4H, and a semiconductor wafer480as illustrated inFIG.4Ieach includes multiple integrated circuit components, such as the integrated circuit components100.1through100.nas described above inFIG.2A. The multiple integrated circuit components100.1through100.nare covered by a redistribution layer including a plurality of redistribution patterns300.1through300.rand the plurality of redistribution patterns300.1through300.rare identical in layout. Each redistribution pattern300.1,300.2, . . . or300.rmay has the same layout as the redistribution layer300as illustrated inFIG.3A, the redistribution layer310as illustrated inFIG.3B, the redistribution layer322as illustrated inFIG.3E, the redistribution layer332as illustrated inFIG.3F, the redistribution layer334as illustrated inFIG.3G, the redistribution layer336as illustrated inFIG.3H, the redistribution layer338as illustrated inFIG.3Ior the redistribution layer340as illustrated inFIG.3J.

In the exemplary embodiment illustrated inFIG.4A, the semiconductor wafer400includes integrated circuit components402.1through402.r. As illustrated inFIG.4A, the integrated circuit components402.1through402.rare respectively covered by the redistribution patterns300.1through300.rof the redistribution layer, each of the redistribution patterns300.1through300.ris identical with the redistribution layer300as described above inFIG.3A. In the exemplary embodiment illustrated inFIG.4A, the array of first conductive contacts302is separated or spaced apart from the active region100A by a distance a. For example, the distance a ranges from about 60 micrometers to about 70 micrometers, such as approximately 65 micrometers. Similarly, the array of first conductive contacts302is separated or spaced apart from peripheries, or edges, of their corresponding redistribution patterns310.1through310.rby a distance b. For example, the distance b ranges from about 60 micrometers to about 70 micrometers, such as approximately 65 micrometers (μm). In an exemplary embodiment, the semiconductor wafer400includes scribe lines404.1through404.yand scribe lines406.1through406.xintersected with the scribe lines404.1through404.y. In this exemplary embodiment, the semiconductor wafer400may be cut along the scribe lines404.1through404.yand the scribe lines406.1through406.xto singulate the semiconductor wafer400into a plurality of singulated integrated circuit components402.1through402.r. In the exemplary embodiment illustrated inFIG.4A, at most one of the array of first conductive contacts302corresponding to one of the redistribution patterns300.1through300.ris adjacent to the scribe lines404.1through404.yat any location within the semiconductor wafer400. For example, as illustrated inFIG.4A, the array of first conductive contacts302corresponding to the redistribution pattern300.2disposed over the integrated circuit component402.2is along the scribe line404.1between the integrated circuit component402.1and the integrated circuit component402.2. This configuration and arrangement of the redistribution patterns300.1through300.rfacilitates displacement of air during bonding of the semiconductor wafer400and other redistribution layers of other electrical, mechanical, and/or electromechanical devices during the bonding of these redistribution layers.

As illustrated inFIG.4A, any two most adjacent arrays of first conductive contacts302(e.g., a first array of first conductive contacts302.1and a second array of first conductive contacts302.2) which are aligned with each other in the second direction D2and respectively disposed over two adjacent first integrated circuit components (e.g., the integrated circuit components402.1and402.2) are apart from each other by a first distance DS1, the first distance DS1is greater than a first dimension DM1of the active region100A in the second direction D2.

As shown inFIG.4A, the first integrated circuit component402.1is most adjacent to the second integrated circuit component402.2in the second direction D2substantially perpendicular with the first direction D1. The first array of first conductive contacts302.1are disposed on the periphery region100B of the first integrated circuit component402.1while the second array of first conductive contacts302.2are disposed on the periphery region100B of the second integrated circuit component402.2. The first and second arrays of first conductive contacts302.1and302.2extend along the first direction D1and are substantially aligned with each other in the second direction D2. Furthermore, the first and second arrays of first conductive contacts302.1and302.2are apart from each other by a first distance DS1in the second direction D2.

As shown inFIG.4A, in some embodiments, the first array of first conductive contacts302.1and the second array of first conductive contacts302.2are substantially aligned with each other in the second direction D2and no other array of conductive contacts is arranged between the first array of first conductive contacts302.1and the second array of first conductive contacts302.2.

In some alternative embodiments, each of the redistribution patterns300.1through300.rfurther includes a dummy pattern DP (e.g., dummy metal pattern) embedded in the dielectric layer, wherein the dummy pattern DP is electrically floating and are arranged between any two most adjacent arrays of first conductive contacts302. For example, the dummy pattern DP includes at least one dummy metal pad or a plurality of dummy metal vias arranged in an array. The dummy pattern DP is apart from the arrays of first conductive contacts302to make sure that air is not trapped between the dummy pattern DP and the arrays of first conductive contacts302. For example, the dummy pattern DP is embedded in the dielectric layer of the redistribution patterns300.1through300.rand located above the active regions100A and/or the periphery regions100B of the integrated circuit components402.1through402.r. It is noted that a metal ratio of the redistribution patterns300.1through300.rmay affect the process window and yields of the CMP process for fabricating the arrays of first conductive contacts302because of loading effect. Thickness uniformity of the arrays of first conductive contacts302may be affected by loading effect when the metal ratio of the redistribution patterns300.1through300.ris low. Accordingly, the dummy pattern DP may improve the process window and yields of the CMP process for fabricating the arrays of first conductive contacts302.

In the exemplary embodiment illustrated inFIG.4B, the semiconductor wafer410includes integrated circuit components412.1through412.r. As illustrated inFIG.4B, the integrated circuit components402.1through412.rare respectively covered by the redistribution patterns310.1through310.rof the redistribution layer, each of the redistribution patterns310.1through310.ris identical with the redistribution layer310as described above inFIG.3B. In the exemplary embodiment illustrated inFIG.4B, the array of first conductive contacts312and the array of second conductive contacts314are separated or spaced apart from the active region100A by a distance a. For example, the distance a ranges from about 60 micrometers to about 70 micrometers, such as approximately 65 micrometers. Similarly, the array of first conductive contacts312and the array of second conductive contacts314are separated or spaced apart from peripheries, or edges, of their corresponding redistribution patterns310.1through310.rby a distance b. For example, the distance b ranges from about 60 micrometers to about 70 micrometers, such as approximately 65 micrometers (μm). In an exemplary embodiment, the semiconductor wafer410includes the horizontal rows of scribe lines404.1through404.yand the vertical columns of scribe lines406.1through406.xas described above inFIG.4A. In the exemplary embodiment illustrated inFIG.4B, at most one of the array of first conductive contacts312corresponding to one of the redistribution patterns310.1through310.ris adjacent to the horizontal rows of scribe lines404.1through404.yat any location within the semiconductor wafer410and at most one of the array of second conductive contacts314corresponding to one of the redistribution patterns310.1through310.ris adjacent to the vertical columns of scribe lines406.1through406.xat any location within the semiconductor wafer410. For example, as illustrated inFIG.4B, the array of first conductive contacts312corresponding to the redistribution pattern310.2disposed over the integrated circuit component412.2is along the horizontal row of scribe line404.1between the integrated circuit component412.1and the integrated circuit component412.2. As another example, as illustrated inFIG.4B, the array of second conductive contacts314corresponding to the redistribution pattern310.1disposed over the integrated circuit component412.1is along the vertical row of scribe lines406.1between the integrated circuit component412.1and the integrated circuit component412.3. This configuration and arrangement of the redistribution patterns310.1through310.rfacilitates displacement of air during bonding of the semiconductor wafer410and other redistribution layers of other electrical, mechanical, and/or electromechanical devices during the bonding of these redistribution layers.

As illustrated inFIG.4B, any two most adjacent arrays of first conductive contacts312(e.g., a first array of first conductive contacts312.1and a second array of first conductive contacts312.2) which are aligned with each other in the second direction D2and respectively disposed over two adjacent integrated circuit components (e.g., the integrated circuit components412.1and412.2) are apart from each other by a first distance DS1, and the first distance DS1is greater than a first dimension DM1of the active region100A in the second direction D2. In addition, any two most adjacent arrays of second conductive contacts314(e.g., a first array of second conductive contacts314.1and a second array of second conductive contacts314.2) which are aligned with each other in the first direction D1and respectively disposed over two adjacent integrated circuit components (e.g., the integrated circuit components412.1and412.3) are apart from each other by a second distance DS2, and the second distance DS2is greater than a second dimension DM2of the active region100A in the first direction D1.

As shown inFIG.4B, the first integrated circuit component412.1is most adjacent to the second integrated circuit component412.2in the second direction D2. The first array of first conductive contacts312.1are disposed on the periphery region100B of the first integrated circuit component412.1while the second array of first conductive contacts312.2are disposed on the periphery region100B of the second integrated circuit component412.2. The first and second arrays of first conductive contacts312.1and312.2extend along the first direction D1and are substantially aligned with each other in the second direction D2. Furthermore, the first and second arrays of first conductive contacts312.1and312.2are apart from each other by the second distance DS1in the second direction D2.

In some embodiments, the first array of first conductive contacts312.1and the second array of first conductive contacts312.2are substantially aligned with each other in the second direction D2and no other array of conductive contacts is arranged between the first array of first conductive contacts312.1and the second array of first conductive contacts312.2.

As shown inFIG.4B, the first integrated circuit component412.1is most adjacent to the third integrated circuit component412.3in the first direction D1. The first array of second conductive contacts314.1are disposed on the periphery region100B of the first integrated circuit component412.1while the second array of second conductive contacts314.2are disposed on the periphery region100B of the third integrated circuit component412.3. The first and second arrays of second conductive contacts314.1and314.2extend along the second direction D2and are substantially aligned with each other in the first direction D1. Furthermore, the first and second arrays of second conductive contacts314.1and314.2are apart from each other by the second distance DS2in the first direction D1.

In some embodiments, the first array of second conductive contacts314.1and the second array of second conductive contacts314.2are substantially aligned with each other in the first direction D1and no other array of conductive contacts is arranged between the first array of second conductive contacts314.1and the second array of second conductive contacts314.2.

In some alternative embodiments, each of the redistribution patterns310.1through310.rfurther includes a dummy pattern (e.g., dummy metal pattern as shown inFIG.4A) embedded in the dielectric layer, wherein the dummy pattern is electrically floating and are arranged between the arrays of first conductive contacts312and/or314. For example, the dummy pattern includes at least one dummy metal pad or a plurality of dummy metal vias arranged in an array. The dummy pattern is apart from the arrays of first conductive contacts312and/or314to make sure that air is not trapped between the dummy pattern and the arrays of first conductive contacts312and/or314. For example, the dummy pattern is embedded in the dielectric layer of the redistribution patterns310.1through310.rand located above the active regions100A and/or the periphery regions100B of the integrated circuit components412.1through412.r. It is noted that metal ratio of the redistribution patterns310.1through310.rmay affect the process window and yields of the CMP process for fabricating the arrays of first conductive contacts312and314because of loading effect. Thickness uniformity of the arrays of first conductive contacts312and314may be affected by loading effect when the metal ratio of the redistribution patterns310.1through310.ris low. Accordingly, the dummy pattern may improve the process window and yields of the CMP process for fabricating the arrays of first conductive contacts312and314.

In the exemplary embodiment illustrated inFIG.4C, the semiconductor wafer420includes integrated circuit components422.1through422.rinterdigitated with integrated circuit components424.1through424.s. As illustrated inFIG.4C, the integrated circuit components422.1through422.rare respectively covered by the redistribution patterns318.1through318.r, each of the redistribution patterns318.1through318.ris identical with the redistribution layer318as described above inFIG.3C. The integrated circuit components424.1through424.sare respectively covered by the redistribution patterns320.1through320.s, each of the redistribution patterns320.1through320.sis identical with the redistribution layer320as described above inFIG.3D. As illustrated inFIG.4C, the redistribution patterns318.1through318.rand the redistribution patterns320.1through320.sare configured and arranged to optimize displacement of air during bonding of the semiconductor wafer420and other redistribution layers of other electrical, mechanical, and/or electromechanical devices. In the exemplary embodiment illustrated inFIG.4C, the first array of conductive contacts312of the redistribution patterns318.1through318.rare situated along first sides, for example top sides, of the redistribution patterns318.1through318.rand the second array of conductive contacts314of the redistribution patterns318.1through318.rare situated along third sides, for example bottom sides, of the redistribution patterns318.1through318.r. Also in the exemplary embodiment illustrated inFIG.4C, the first array of conductive contacts312of the redistribution patterns320.1through320.sare situated along second sides, for example right sides, of the redistribution patterns320.1through320.sand the second array of conductive contacts314of the redistribution patterns320.1through320.sare situated along fourth sides, for example left sides, of the redistribution patterns320.1through320.s.

In an exemplary embodiment, the semiconductor wafer420includes the horizontal rows of scribe lines404.1through404.yand/or the vertical columns of scribe lines406.1through406.xas described above inFIG.4A. In the exemplary embodiment illustrated inFIG.4C, at most one of the first array of conductive contacts312and/or the second array of conductive contacts314corresponding to one of the redistribution patterns318.1through318.ris adjacent to the horizontal rows of scribe lines404.1through404.yat any location within the semiconductor wafer410and at most one of the first array of conductive contacts312and/or the second array of conductive contacts314corresponding to one of the redistribution patterns320.1through320.sis adjacent to the vertical columns of scribe lines406.1through406.xat any location within the semiconductor wafer410. For example, as illustrated inFIG.4C, the second array of conductive contacts314corresponding to the redistribution pattern318.1on the integrated circuit component422.1is along the horizontal row of scribe line404.1between the integrated circuit component422.1and the integrated circuit component424.1. As another example, as illustrated inFIG.4C, the first array of conductive contacts312corresponding to the redistribution pattern320.1on the integrated circuit component424.2is along the vertical row of scribe lines406.1between the integrated circuit component422.1and the integrated circuit component424.2. This configuration and arrangement of the redistribution patterns320.1through320.rfacilitates displacement of air during bonding of the semiconductor wafer410and other redistribution layers of other electrical, mechanical, and/or electromechanical devices during the bonding of these redistribution layers. Furthermore, the above-mentioned dummy pattern (e.g., dummy metal pattern as shown inFIG.4A) may be applied in the embodiment as illustratedFIG.4C.

As illustrated inFIG.4D, the semiconductor wafer430includes redistribution patterns322.1through322.r, each of the redistribution patterns322.1through322.ris identical with the redistribution layer322as described above inFIG.3E. In the exemplary embodiment illustrated inFIG.4D, the array of first conductive contacts324, the array of second conductive contacts326, the array of third conductive contacts328, and the array of fourth conductive contacts330are separated or spaced apart from the active region100A by a distance a. For example, the distance a ranges from about 60 micrometers to about 70 micrometers, such as approximately 65 micrometers. Similarly, the array of first conductive contacts324, the array of second conductive contacts326, the array of third conductive contacts328, and the array of fourth conductive contacts330are separated or spaced apart from peripheries, or edges, of their corresponding redistribution patterns322.1through322.rby a distance b. For example, the distance b ranges from about 60 micrometers to about 70 micrometers, such as approximately 65 micrometers (μm).

In an exemplary embodiment, the semiconductor wafer430includes the horizontal rows of scribe lines404.1through404.yand/or the vertical columns of scribe lines406.1through406.xas described above inFIG.4A. In the exemplary embodiment illustrated inFIG.4D, at most one of the array of first conductive contacts324and the array of third conductive contacts328corresponding to one of the redistribution patterns322.1through322.ris adjacent to the horizontal rows of scribe lines404.1through404.yat any location within the semiconductor wafer430and at most one of the array of second conductive contacts326and the array of fourth conductive contacts330corresponding to one of the redistribution patterns322.1through322.ris adjacent to the vertical columns of scribe lines406.1through406.xat any location within the semiconductor wafer430. For example, as illustrated inFIG.4D, the third array of conductive contacts328corresponding to the redistribution pattern322.1of the integrated circuit component432.1is along a first portion of the horizontal row of scribe line404.1between the integrated circuit component432.1and the integrated circuit component432.2and the array of first conductive contacts324corresponding to the redistribution pattern322.2of the integrated circuit component432.2is along a second portion of the horizontal row of scribe line404.1between the integrated circuit component432.1and the integrated circuit component432.2. As another example, as illustrated inFIG.4D, the array of second conductive contacts326corresponding to the redistribution pattern322.1of the integrated circuit component432.1is along a first portion of the vertical column of scribe line406.1between the integrated circuit component432.1and the integrated circuit component432.3and the array of fourth conductive contacts330corresponding to the redistribution pattern322.3of the integrated circuit component432.3is along a second portion of the vertical column of scribe line406.1between the integrated circuit component432.1and the integrated circuit component432.3. This configuration and arrangement of the redistribution patterns322.1through322.rfacilitates displacement of air during bonding of the semiconductor wafer430and other redistribution layers of other electrical, mechanical, and/or electromechanical devices during the bonding of these redistribution layers.

As illustrated inFIG.4D, any two most adjacent arrays of first conductive contacts324(e.g., a first array of first conductive contacts324.1and a second array of first conductive contacts324.2) which are aligned with each other in the second direction D2and respectively disposed over two adjacent integrated circuit components (e.g., the integrated circuit components432.1and432.2) are apart from each other by a first distance DS1, and the first distance DS1is greater than a first dimension DM1of the active region100A in the second direction D2. Any two most adjacent arrays of second conductive contacts326(e.g., a first array of second conductive contacts326.1and a second array of second conductive contacts326.2) which are aligned with each other in the first direction D1and respectively disposed over two adjacent integrated circuit components (e.g., the integrated circuit components432.1and432.3) are apart from each other by a second distance DS2, and the second distance DS2is greater than a second dimension DM2of the active region100A in the first direction D1. Any two most adjacent arrays of third conductive contacts328(e.g., a first array of third conductive contacts328.1and a second array of third conductive contacts328.2) which are aligned with each other in the second direction D2and respectively disposed over two adjacent integrated circuit components (e.g., the integrated circuit components432.1and432.2) are apart from each other by the first distance DS1, and the first distance DS1is greater than the first dimension DM1of the active region100A in the second direction D2. In addition, any two most adjacent arrays of fourth conductive contacts330(e.g., a first array of fourth conductive contacts330.1and a second array of fourth conductive contacts330.2) which are aligned with each other in the first direction D1and respectively disposed over two adjacent integrated circuit components (e.g., the integrated circuit components432.1and432.3) are apart from each other by the second distance DS2, and the second distance DS2is greater than the second dimension DM2of the active region100A in the first direction D1.

As shown inFIG.4D, the first integrated circuit component432.1is most adjacent to the second integrated circuit component432.2in the second direction D2. The first array of first conductive contacts324.1are disposed on the periphery region100B of the first integrated circuit component432.1while the second array of first conductive contacts324.2are disposed on the periphery region100B of the second integrated circuit component432.2. The first and second arrays of first conductive contacts324.1and324.2extend along the first direction D1and are substantially aligned with each other in the second direction D2. The first and second arrays of first conductive contacts324.1and324.2are apart from each other by the second distance DS1in the second direction D2. Similarly, the first array of third conductive contacts328.1are disposed on the periphery region100B of the first integrated circuit component432.1while the second array of third conductive contacts328.2are disposed on the periphery region100B of the second integrated circuit component432.2. The first and second arrays of third conductive contacts328.1and328.2extend along the first direction D1and are substantially aligned with each other in the second direction D2. The first and second arrays of third conductive contacts328.1and328.2are apart from each other by the second distance DS1in the second direction D2. Furthermore, the first and second arrays of first conductive contacts324.1and324.2are not aligned with the first and second arrays of third conductive contacts328.1and328.2in the second direction D2.

As shown inFIG.4D, the first integrated circuit component432.1is most adjacent to the third integrated circuit component432.3in the first direction D1. The first array of second conductive contacts326.1are disposed on the periphery region100B of the first integrated circuit component432.1while the second array of second conductive contacts326.2are disposed on the periphery region100B of the third integrated circuit component432.3. The first and second arrays of second conductive contacts326.1and326.2extend along the second direction D2and are substantially aligned with each other in the first direction D1. Furthermore, the first and second arrays of second conductive contacts326.1and326.2are apart from each other by the second distance DS2in the first direction D1. Similarly, the first array of fourth conductive contacts330.1are disposed on the periphery region100B of the first integrated circuit component432.1while the second array of fourth conductive contacts330.2are disposed on the periphery region100B of the third integrated circuit component432.3. The first and second arrays of fourth conductive contacts330.1and330.2extend along the second direction D2and are substantially aligned with each other in the first direction D1. The first and second arrays of fourth conductive contacts330.1and330.2are apart from each other by the second distance DS2in the first direction D1. Furthermore, the first and second arrays of second conductive contacts326.1and326.2are not aligned with the first and second arrays of fourth conductive contacts330.1and330.2in the first direction D1.

In some embodiments, the first array of first conductive contacts324.1and the second array of first conductive contacts324.2are substantially aligned with each other in the second direction D2and no other array of conductive contacts is arranged between the first array of first conductive contacts324.1and the second array of first conductive contacts324.2. In some embodiments, the first array of second conductive contacts326.1and the second array of second conductive contacts326.2are substantially aligned with each other in the first direction D1and no other array of conductive contacts is arranged between the first array of second conductive contacts326.1and the second array of second conductive contacts326.2. In some embodiments, the first array of third conductive contacts328.1and the second array of third conductive contacts328.2are substantially aligned with each other in the second direction D2and no other array of conductive contacts is arranged between the first array of third conductive contacts328.1and the second array of third conductive contacts328.2. Similarly, the first array of fourth conductive contacts330.1and the second array of fourth conductive contacts330.2are substantially aligned with each other in the first direction D1and no other array of conductive contacts is arranged between the first array of fourth conductive contacts330.1and the second array of fourth conductive contacts330.2.

In some alternative embodiments, each of the redistribution patterns322.1through322.rfurther includes a dummy pattern (e.g., dummy metal pattern as shown inFIG.4A) embedded in the dielectric layer, wherein the dummy pattern is electrically floating and are arranged between the arrays of first conductive contacts324,326,328and/or330. The dummy pattern is apart from the arrays of first conductive contacts324,326,328and/or330to make sure that air is not trapped between the dummy pattern and the arrays of first conductive contacts324,326,328and/or330. For example, the dummy pattern is embedded in the dielectric layer of the redistribution patterns322.1through322.rand located above the active regions100A and/or the periphery regions100B of the integrated circuit components432.1through432.r. It is noted that a metal ratio of the redistribution patterns322.1through322.rmay affect the process window and yields of the CMP process for fabricating the arrays of first conductive contacts324,326,328and330because of loading effect. Thickness uniformity of the arrays of first conductive contacts324,326,328and330may be affected by loading effect when the metal ratio of the redistribution patterns322.1through322.ris low. Accordingly, the dummy pattern may improve the process window and yields of the CMP process for fabricating the arrays of first conductive contacts324,326,328and330.

As illustrated inFIG.4E, the semiconductor wafer440includes redistribution patterns332.1through332.r, wherein each of the redistribution patterns332.1through332.ris identical with the redistribution layer332as described above inFIG.3F. In the exemplary embodiment illustrated inFIG.4E, the array of first conductive contacts324, the array of second conductive contacts326, the array of third conductive contacts328, and the array of fourth conductive contacts330are separated or spaced apart from the active region100A within the semiconductor stack by a distance a. For example, the distance a ranges from about 60 micrometers to about 70 micrometers, such as approximately 65 micrometers. Similarly, the array of first conductive contacts324, the array of second conductive contacts326, the array of third conductive contacts328, and the array of fourth conductive contacts330are separated or spaced apart from peripheries, or edges, of their corresponding redistribution patterns332.1through332.rby a distance b. For example, the distance b ranges from about 60 micrometers to about 70 micrometers, such as approximately 65 micrometers (μm). The arrangement of the array of first conductive contacts324, the array of second conductive contacts326, the array of third conductive contacts328, and the array of fourth conductive contacts330in the semiconductor wafer440is similar with that in the semiconductor wafer430except for the locations of the array of first conductive contacts324and the array of third conductive contacts328.

In an exemplary embodiment, the semiconductor wafer440includes the horizontal rows of scribe lines404.1through404.yand/or the vertical columns of scribe lines406.1through406.xas described above inFIG.4A. In the exemplary embodiment illustrated inFIG.4E, at most one of the array of first conductive contacts324and the array of third conductive contacts328corresponding to one of the redistribution patterns332.1through332.ris adjacent to the horizontal rows of scribe lines404.1through404.yat any location within the semiconductor wafer440and at most one of the array of second conductive contacts326and the array of fourth conductive contacts330corresponding to one of the redistribution patterns332.1through332.ris adjacent to the vertical columns of scribe lines406.1through406.xat any location within the semiconductor wafer440. For example, as illustrated inFIG.4E, the array of third conductive contacts328corresponding to the redistribution pattern332.1of the integrated circuit component442.1is along a first portion of the horizontal row of scribe line404.1between the integrated circuit component442.1and the integrated circuit component442.2and the array of first conductive contacts324corresponding to the redistribution pattern332.2of the integrated circuit component442.2is along a second portion of the horizontal row of scribe line404.1between the integrated circuit component442.1and the integrated circuit component442.2. As another example, as illustrated inFIG.4E, the array of second conductive contacts326corresponding to the redistribution pattern332.1of the integrated circuit component442.1is along a first portion of the vertical column of scribe line406.1between the integrated circuit component442.1and the integrated circuit component442.3and the array of fourth conductive contacts330corresponding to the redistribution pattern332.3of the integrated circuit component442.3is along a second portion of the vertical column of scribe line406.1between the integrated circuit component442.1and the integrated circuit component442.3. This configuration and arrangement of the redistribution patterns332.1through332.rfacilitates displacement of air during bonding of the semiconductor wafer440and other redistribution layers of other electrical, mechanical, and/or electromechanical devices during the bonding of these redistribution layers.

As illustrated inFIG.4F, the semiconductor wafer450includes redistribution patterns334.1through334.r, each of the redistribution patterns334.1through334.ris identical with the redistribution layer334as described above inFIG.3G. In the exemplary embodiment illustrated inFIG.4F, the array of second conductive contacts326and the array of fourth conductive contacts330are separated or spaced apart from the active region100A within the semiconductor stack by a distance a. For example, the distance a ranges from about 60 micrometers to about 70 micrometers, such as approximately 65 micrometers. Similarly, the array of second conductive contacts326and the array of fourth conductive contacts330are separated or spaced apart from peripheries, or edges, of their corresponding redistribution patterns334.1through334.rby a distance b. For example, the distance b ranges from about 60 micrometers to about 70 micrometers, such as approximately 65 micrometers (μm). The arrangement of the array of second conductive contacts326and the array of fourth conductive contacts330in the semiconductor wafer450may be the same as that in the semiconductor wafer430and the detail descriptions of the array of second conductive contacts326and the array of fourth conductive contacts330in the semiconductor wafer450are thus omitted.

In an exemplary embodiment, the semiconductor wafer450includes the horizontal rows of scribe lines404.1through404.yand/or the vertical columns of scribe lines406.1through406.xas described above inFIG.4A. In the exemplary embodiment illustrated inFIG.4F, at most one of the array of second conductive contacts326and the array of fourth conductive contacts330corresponding to one of the redistribution patterns334.1through334.ris adjacent to the vertical columns of scribe lines406.1through406.xat any location within the semiconductor wafer450. For example, as illustrated inFIG.4F, the array of second conductive contacts326corresponding to the redistribution pattern334.1of the integrated circuit component452.1is along a first portion of the vertical column of scribe line406.1between the integrated circuit component452.1and the integrated circuit component452.2and the array of fourth conductive contacts330corresponding to the redistribution pattern334.3of the integrated circuit component452.2is along a second portion of the vertical column of scribe line406.1between the integrated circuit component452.1and the integrated circuit component452.2. This configuration and arrangement of the redistribution patterns334.1through334.rfacilitates displacement of air during bonding of the semiconductor wafer450and other redistribution layers of other electrical, mechanical, and/or electromechanical devices during the bonding of these redistribution layers.

As illustrated inFIG.4G, the semiconductor wafer460includes redistribution patterns336.1through336.r. In the exemplary embodiment illustrated inFIG.4G, the arrays of first conductive contacts324and the arrays of second conductive contacts326are separated or spaced apart from the active region100A within the semiconductor stack by a distance a. For example, the distance a ranges from about 60 micrometers to about 70 micrometers, such as approximately 65 micrometers. Similarly, the arrays of first conductive contacts324and the arrays of second conductive contacts326are separated or spaced apart from peripheries, or edges, of their corresponding redistribution patterns336.1through336.rby a distance b. For example, the distance b ranges from about 60 micrometers to about 70 micrometers, such as approximately 65 micrometers (μm). The arrangement of the arrays of first conductive contacts324and the arrays of second conductive contacts326in the semiconductor wafer450may be the same as that in the semiconductor wafer430and the detailed descriptions of the arrays of first conductive contacts324and the arrays of second conductive contacts326in the semiconductor wafer450are thus omitted.

As illustrated inFIG.4H, the semiconductor wafer470includes redistribution patterns338.1through338.r. In the exemplary embodiment illustrated inFIG.4H, the arrays of first conductive contacts324and the arrays of third conductive contacts328are separated or spaced apart from the active region100A within the semiconductor stack by a distance a. For example, the distance a ranges from about 60 micrometers to about 70 micrometers, such as approximately 65 micrometers. Similarly, the arrays of first conductive contacts324and the arrays of third conductive contacts328are separated or spaced apart from peripheries, or edges, of their corresponding redistribution patterns338.1through338.rby a distance b. For example, the distance b ranges from about 60 micrometers to about 70 micrometers, such as approximately 65 micrometers (μm). The arrangement of the arrays of first conductive contacts324and the arrays of third conductive contacts328in the semiconductor wafer450may be the same as that in the semiconductor wafer430and the detailed descriptions of the arrays of first conductive contacts324and the arrays of third conductive contacts328in the semiconductor wafer450are thus omitted.

As illustrated inFIG.4I, the semiconductor wafer480includes redistribution patterns340.1through340.r. In the exemplary embodiment illustrated inFIG.4I, the arrays of first conductive contacts324and the arrays of fourth conductive contacts340are separated or spaced apart from the active region100A within the semiconductor stack by a distance a. For example, the distance a ranges from about 60 micrometers to about 70 micrometers, such as approximately 65 micrometers. Similarly, the arrays of first conductive contacts324and the arrays of fourth conductive contacts330are separated or spaced apart from peripheries, or edges, of their corresponding redistribution patterns340.1through340.rby a distance b. For example, the distance b ranges from about 60 micrometers to about 70 micrometers, such as approximately 65 micrometers (μm). The arrangement of the arrays of first conductive contacts324and the arrays of fourth conductive contacts340in the semiconductor wafer450may be the same as that in the semiconductor wafer430and the detailed descriptions of the arrays of first conductive contacts324and the arrays of fourth conductive contacts340in the semiconductor wafer450are thus omitted.

Furthermore, the above-mentioned dummy pattern (e.g., dummy metal pattern as shown inFIG.4A) may be applied in the embodiments as illustratedFIG.4E,FIG.4F,FIG.4G,FIG.4H,FIG.4IandFIG.4J.

FIG.5illustrates a flowchart of exemplary operation for fabricating the exemplary semiconductor wafers including the exemplary integrated circuit components according to an exemplary embodiment of the present disclosure. The disclosure is not limited to this operational description. Rather, it will be apparent to ordinary persons skilled in the relevant art(s) that other operational control flows are within the scope and spirit of the present disclosure. The following discussion describes an exemplary operational control flow500for fabricating a semiconductor wafer, such as the semiconductor wafer200to provide an example.

At operation502, the exemplary operational control flow500fabricates a first semiconductor wafer. The exemplary operational control flow500uses a first predetermined sequence of photographic and/or chemical processing operations to form multiple integrated circuit components, such as the integrated circuit components100.1through100.nto provide an example, onto a semiconductor substrate, such as the semiconductor substrate202to provide an example, to form the first semiconductor wafer. The first predetermined sequence of photographic and/or chemical processing operations may include deposition, removal, patterning, and modification. The deposition is an operation used to grow, coat, or otherwise transfer a material onto the semiconductor substrate and may include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), and/or molecular beam epitaxy (MBE) to provide some examples. The removal is an operation to remove material from the semiconductor substrate and may include wet etching, dry etching, and/or chemical-mechanical planarization (CMP) to provide some examples. The patterning, often referred to as lithography, is an operation to shape or alter material of the semiconductor substrate to form various geometric shapes of the analog and/or digital circuitry for the electronic device. The modification of electrical properties is an operation to alter physical, electrical, and/or chemical properties of material of the semiconductor substrate, typically, by ion implantation.

At operation504, the exemplary operational control flow500fabricates a second semiconductor wafer. The exemplary operational control flow500uses a second predetermined sequence of photographic and/or chemical processing operations to form multiple integrated circuit components, such as the integrated circuit components100.1through100.nto provide an example, onto a semiconductor substrate, such as the semiconductor substrate202to provide an example, to form the second semiconductor wafer. The second predetermined sequence of photographic and/or chemical processing operations may include the deposition, the removal, the patterning, and the modification as described above in operation502.

At operation506, the exemplary operational control flow500cleans the first semiconductor wafer from operation502and the second semiconductor wafer from operation504. The exemplary operational control flow500removes impurities from a first redistribution layer of the first semiconductor wafer from operation502and a second redistribution layer of the second semiconductor wafer from operation504. The exemplary operational control flow500may utilize a dry cleaning, for example, plasma treatments, ultra-violet cleaning, and/or ozone cleaning to provide some examples, and/or a wet chemical cleaning procedure to remove the impurities.

At operation508, the exemplary operational control flow500aligns the first semiconductor wafer from operation502and the second semiconductor wafer from operation504. The exemplary operational control flow500aligns the first redistribution layer of the first semiconductor wafer from operation502and the second redistribution layer of the second semiconductor wafer from operation504for bonding. In an exemplary embodiment, the first redistribution layer of the first semiconductor wafer from operation502is a mirror, or substantial mirror, image of the second redistribution layer of the first semiconductor wafer from operation502to allow for bonding.

At operation510, the exemplary operational control flow500bonds the first semiconductor wafer from operation502and the second semiconductor wafer from operation504. The exemplary operational control flow500using hybrid bonding, direct bonding, surface activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, thermocompression bonding, reactive bonding, transient liquid phase diffusion bonding and/or any other well-known bonding technique which is apparent to those skilled in the relevant art(s) without departing from the spirit and scope of the present disclosure to bond the first semiconductor wafer from operation502and the second semiconductor wafer from operation504.

At operation512, after performing the bonding process (i.e. the operation510), the exemplary operational control flow500performs a dicing process on the bonded first and second semiconductor wafers (i.e. the bonded structure210as illustrated inFIG.2C) to form singulated semiconductor devices.

The foregoing Detailed Description discloses an integrated circuit. The integrated circuit includes electronic circuitry and a redistribution layer. The electronic circuitry is situated within a semiconductor stack having conductive layers interdigitated with a non-conductive layer situated on a semiconductor substrate. The redistribution layer is situated within a conductive layer from among the conductive layers of the semiconductor stack, the redistribution layer including a first array of conductive contacts extending along a first direction of the redistribution layer. The integrated circuit has been separated from integrated circuit components situated on a semiconductor substrate along scribe lines. A second integrated circuit, including second electronic circuitry, is arranged on the semiconductor substrate to be adjacent to the integrated circuit along a first scribe line, the second integrated circuit including a second array of conductive contacts extending along the first direction. At most of one the first array of conductive contacts and the second array of conductive contacts is situated between the electronic circuitry and the second electronic circuitry along the first scribe line.

The foregoing Detailed Description also discloses a semiconductor wafer. The semiconductor wafer includes a semiconductor substrate and integrated circuit components. The integrated circuit components are situated on the semiconductor substrate, the integrated circuit components including redistribution layers having first arrays of conductive contacts and second arrays of conductive contacts. The first arrays of conductive contacts extend in a first direction along first sides their corresponding integrated circuit components. The second arrays of conductive contacts extend in a second direction along second sides their corresponding integrated circuit components.

The foregoing Detailed Description further discloses a method for fabricating an integrated circuit. The method includes fabricating a first semiconductor wafer, the first semiconductor wafer including first integrated circuit components formed within a first semiconductor stack having first conductive layers interdigitated with first non-conductive layers situated on a semiconductor substrate, fabricating a second semiconductor wafer, the second semiconductor wafer including second integrated circuit components and second redistribution layers situated on a semiconductor substrate, and bonding the first redistribution layers and the second redistribution layers to form the integrated circuit. The first integrated circuit components include first redistribution layers situated within the first conductive layers of the semiconductor stack, each redistribution layer from among the first retribution layers including a corresponding first array of conductive contacts from among first arrays of conductive contacts and a corresponding second array of conductive contacts from among second arrays of conductive contacts. The first arrays of conductive contacts extend in a first direction along first sides of their corresponding integrated circuit components. The second arrays of conductive contacts extend in a second direction along a second sides their corresponding integrated circuit components.