Patent ID: 12224176

DETAILED DESCRIPTION OF THE APPLICATION

Referring toFIG.7, the present application provides a method for forming a fin structure in a fin field effect transistor process, which includes:step S1: growing a core layer thin film on a substrate;step S2: performing photolithography and etching for a first time to form a first core layer pattern and a second core layer pattern, the first core layer pattern being used to form fins, the second core layer pattern being used to form a reference layer overlay mark, the number of the first core layer pattern being at least one, and the number of the second core layer pattern being at least one;step S3: depositing an etching mask layer, the etching mask layer covering tops and side surfaces of the first core layer pattern and the second core layer pattern, and a surface of the substrate;step S4: etching back the etching mask layer to form sidewalls of the first core layer pattern and sidewalls of the second core layer pattern, and expose the tops of the first core layer pattern and the second core layer pattern, and the surface of the substrate;step S5: performing photolithography for a second time to form a first photoresist pattern and a second photoresist pattern, the first photoresist pattern being used to form a planar active area and the second photoresist pattern covering the second core layer pattern;step S6: removing the first core layer pattern, reserving the sidewalls of the first core layer pattern, and reserving the second photoresist pattern and the first photoresist pattern;step S7: etching the substrate for a first time to form the fins and the planar active area consisting of a substrate material;step S8: removing the sidewalls of the first photoresist pattern, the second photoresist pattern and the second core layer pattern, and reserving the second core layer pattern;step S9: performing photolithography for a third time to form a third photoresist pattern which covers all the planar active area and fins outside a fin cut area, and expose the second core layer pattern and the fins inside the fin cut area;step S10: etching the substrate for a second time to form at least one reference layer overlay mark and fin cut area consisting of the substrate material.

The method for forming the fin structure is further described in detail below in combination with the specific structure of the fin field effect transistor in the steps of the method.

In step S1, referring toFIG.8, a core layer thin film200is grown on a substrate100. The substrate100is used to form a final fin structure. Exemplarily, the substrate100is a silicon wafer. The substrate100may also include an elemental semiconductor (such as silicon or germanium in a crystal structure), a compound semiconductor (such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide or indium antimonide).

The core layer thin film200may be a single-layer dielectric film layer or a single-layer metal film layer or a single-layer metal compound film layer, or a multilayer film layer consisting of a dielectric film layer and/or a metal film layer and/or a metal compound film layer. Exemplarily, the core layer thin film200is amorphous silicon. Exemplarily, one or more hard mask layers may be grown before and after the core layer thin film200is grown according to process requirements to improve the etching selection ratio of subsequent etching processes.

In step S2, referring toFIG.9, photolithography and etching are performed for a first time to form a first core layer pattern201and a second core layer pattern202. The first core layer pattern201is used to form fins. The second core layer pattern202is used to form a reference layer overlay mark. The number of the first core layer pattern201is at least one. Exemplarily, the number of the first core layer pattern201is two in this embodiment. The number of the second core layer pattern202is at least one. Exemplarily, the number of the second core layer pattern202is two in this embodiment.

The width a of the second core layer pattern202depends on the width (not shown in the figure) of the corresponding reference layer overlay mark on the used mask. The photolithography for the first time is used as a reference layer for alignment and overlay of subsequent photolithography layers. Therefore, the quality of the reference layer alignment and overlay mark formed through the photolithography and etching processes for the first time will directly affect the alignment and overlay accuracy of subsequent photolithography layers. One or more reference layer overlay mark patterns with different widths or types may be designed on the mask used in the photolithography for the first time according to process requirements.

That is, in the case of multiple second core layer patterns202, the width and type of the multiple second core layer patterns202may be different.

The photolithography mentioned in this step and other steps may include photoresist coating, soft baking, mask alignment, exposure, baking after exposure, photoresist development, washing, drying, and etching with exposed and developed photoresist. Exemplarily, the photolithography process may be implemented, supplemented, or replaced by other methods, such as maskless photolithography, electron beam writing, and ion beam writing.

The etching process mentioned in this and other steps includes dry etching, wet etching, and/or other etching methods, such as reactive ion etching.

In step S3, referring toFIG.10, an etching mask layer300is deposited. The etching mask layer300covers tops and side surfaces of the first core layer pattern201and the second core layer pattern202, and a surface of the substrate100. The etching selection ratio of the material of the etching mask layer300to the material of the core layer thin film200and the material of the substrate100is certain (more than 3:1, for example).

The deposition in this step and other steps may be implemented by adopting any suitable technology such as Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), High-Density Plasma CVD (HDP-CVD) or Atomic Layer Deposition (ALD).

In step S4, referring toFIG.11, the etching mask layer300is etched back to form sidewalls301of the first core layer pattern and sidewalls302of the second core layer pattern.

After the etching mask layer300is etched back, the tops of the first core layer pattern201and the second core layer pattern202and the surface of the substrate100are exposed.

The sidewalls301of the first core layer pattern are formed on side surfaces of the first core layer pattern201. The sidewalls302of the second core layer pattern are formed on side surfaces of the second core layer pattern202.

In step S5, referring toFIG.12, photolithography is performed for a second time to form a first photoresist pattern403and a second photoresist pattern402. The first photoresist pattern403is used to form a planar active area. The second photoresist pattern402covers the second core layer pattern202.

In step S6, referring toFIG.13, the first core layer pattern201is removed, the sidewalls of the first core layer pattern301are reserved, and the second photoresist pattern402and the first photoresist pattern403are reserved. The etching selection ratio of the material of the first core layer pattern201to the material of the sidewalls301of the first core layer pattern and the material of the second photoresist pattern402and the first photoresist pattern403is certain (more than 3:1, for example).

In step S7, referring toFIG.14, the substrate100is etched for a first time to form the fins101and the planar active area103consisting of a substrate material. The substrate is etched for the first time by using the sidewalls301of the second photoresist pattern402, the first photoresist pattern403and the first core layer pattern as an etching mask.

In step S8, referring toFIG.15, the sidewalls302of the first photoresist pattern403, the second photoresist pattern402and the second core layer pattern are removed, and the second core layer pattern202is reserved.

In step S9, referring toFIG.16, photolithography is performed for a third time to form a third photoresist pattern500which covers all the planar active area103and fins101required to be reserved, i.e., fins outside a fin cut area, and expose the second core layer pattern202and the fins101required to be cut, i.e., fins inside the fin cut area, and the exposed fins will be used as the fin cut area.

In step S10, referring toFIG.17, the substrate100is etched for a second time to form at least one reference layer overlay mark102and the fin cut area104consisting of the substrate material. In this embodiment, the number of the reference layer overlay marks102is two. The substrate100is etched for the second time by using the third photoresist pattern500and the second core layer pattern202as an etching mask. Therefore, the width b of the reference layer overlay mark102is determined by the width a of the second core layer pattern202. Further, the width b of the reference layer overlay mark102depends on the width (not shown) of the corresponding reference layer overlay mark pattern on the mask used in the first photolithography process described in step S2, In the traditional process, the width of the reference layer overlay mark is equal to the width of the fin.

Accordingly, it can be seen that the method for forming the fin structure in the fin field effect transistor process provided by the present application mainly achieves the following technical effects: by respectively forming multiple core layer patterns (first core layer pattern, second core layer pattern, and third core layer pattern) in the three photolithography processes, combined with the innovative process, on the basis of forming the fins, planar active area, and fin cut area of the traditional fin field effect transistor, a reference layer overlay mark is formed at the same time, the width of the reference layer overlay mark can be freely adjusted according to the process requirements, and the type of the reference layer overlay mark can also be designed freely according to the process requirements (while in the traditional process, the width of the reference layer overlay mark is equal to the width of the fin, the size is small and cannot be adjusted, and the type of the overlay mark cannot be designed freely), thus solving the problem that the reference layer overlay mark in the traditional fin field effect transistor process is easily destroyed by subsequent multiple processes, and thus solving the problem of inaccurate measurement of subsequent photolithography layer overlay accuracy.

The embodiment of the present application further provides a fin structure of a fin field effect transistor, which is fabricated by adopting the method for forming the fin structure in the fin field effect transistor process in the above embodiment. The fin structure comprises fins, a planar active area, a fin cut area and a reference layer overlay mark consisting of a substrate material. The width of the reference layer overlay mark is greater than the width of the fin. The width of the reference layer overlay mark is greater than the minimum width capable of being recognized by an overlay accuracy measuring machine.