Patent ID: 12236115

DETAILED DESCRIPTION

Reference will now be made in detail to embodiments of the invention, which are illustrated in the accompanying drawings.

The same reference numbers may be used throughout the drawings to refer to the same or like parts or components/operations. Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, a component may be referred by different names. This document does not intend to distinguish between components that differ in name but not in function. In the following description and in the claims, the term “comprise” is used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the phrase “coupled with” is intended to compass any indirect or direct connection. Accordingly, if this document mentioned that a first device is coupled with a second device, it means that the first device may be directly or indirectly connected to the second device through electrical connections, wireless communications, optical communications, or other signal connections with/without other intermediate devices or connection means.

FIG.1is a simplified functional block diagram of a data storage system100in accordance with an example embodiment. The data storage system100comprises a host device110, a flash memory controller120, and a flash memory module130. The host device110accesses the flash memory module130through the flash memory controller120. The host device110may be a computer, a card reader, a digital camera, a digital video recorder, a mobile phone, a GPS device, or any other electronic device capable of using the flash memory module130as a storage medium. The flash memory controller120comprises a recording medium122, a processing circuit124, and a communication interface126. The communication interface126is utilized for coupling with the host device110, so that data can be communicated between the processing circuit124and the host device110via the communication interface126.

The flash memory module130comprises a read and write circuit132and a plurality of data blocks134. In one embodiment, these data blocks134are realized by one or more TLC (triple-level cells) chips to provide high storage capacity with lower cost. The flash memory controller120and the flash memory module130may be integrated into a single memory device, such as a solid-state disk (SSD) or a memory card. The operations of writing data into the flash memory module130will be further described with reference toFIG.2andFIG.3.

FIG.2is a simplified flowchart200illustrating a method for writing data into flash memory in accordance with a first example embodiment.FIG.3is a simplified schematic diagram300of program threshold voltages of cells in the data block134ofFIG.1according to an example embodiment.

In operation210, the flash memory controller120receives data to be written transmitted from the host device110via the communication interface126.

Then, the processing circuit124of the flash memory controller120decides a range of program threshold voltages for cells in a target data block for use to store the data according to an amount of stored data in the flash memory module130.

For example, in the embodiment ofFIG.2, the processing circuit124performs operation220to determine whether the amount of stored data in the flash memory module130is higher than a first threshold TH1. If the amount of stored data in the flash memory module130is less than the first threshold TH1, the processing circuit124proceeds to operation230. Otherwise, the processing circuit124proceeds to operation240.

In operation240, the processing circuit124further determines whether the amount of stored data in the flash memory module130is higher than a second threshold TH2, wherein TH2is greater than TH1. If the amount of stored data in the flash memory module130is between the first threshold TH1and the second threshold TH2, the processing circuit124proceeds to operation250. If the amount of stored data in the flash memory module130is higher than the second threshold TH2, the processing circuit124proceeds to operation260.

In implementations, the afore-mentioned first threshold TH1and second threshold TH2may be represented in the form of data amount, such as a certain number of MBs or GBs. Alternatively, the first threshold TH1and the second threshold TH2may be represented in the form of percentage values. For example, assuming that the nominal storage capacity of the flash memory module130is X GBs, the first threshold TH1and the second threshold TH2may be respectively set to be 0.3X GBs and 0.6X GBs, or may be respectively set to be 30% and 60% of the nominal storage capacity of the flash memory module130.

As shown inFIG.2, in the operation230the processing circuit124selects a first voltage range to be the voltage range of program threshold voltages for the target data block, in the operation250the processing circuit124selects a third voltage range to be the voltage range of program threshold voltages for the target data block, and in the operation260the processing circuit124selects a second voltage range to be the voltage range of program threshold voltages for the target data block.

The above first voltage range is less than 50% of the second voltage range, and the third voltage range is less than 60% of the second voltage range. The upper limit of the first voltage range may be less than 80% of the upper limit of the second voltage range. For example, the upper limit of the first voltage range may be less than 60% of the upper limit of the second voltage range, or even less than 30% of the upper limit of the second voltage range. The required power consumption for writing data into the cells of the data block can be reduced if the upper limit of the first voltage range is set to be lower. The upper limit of the third voltage range may be less than 80% of the upper limit of the second voltage range, or even less than 60% of the upper limit of the second voltage range. Similarly, the required power consumption for writing data into the cells of the data block can be reduced if the upper limit of the third voltage range is set to be lower.

In operation270, the processing circuit124controls the read and write circuit132to program cells in a target data block134using program threshold voltages within the selected voltage range so as to write data into the target data block134.

In the embodiment shown inFIG.3, each cell of the data block134has an erase threshold voltage interval EV and a plurality of program threshold voltage intervals V0˜V7. In implementations, the processing circuit124may select the first voltage range VR1to be the voltage range of program threshold voltages for the target data block in the operation230. The processing circuit124may select the third voltage range VR3to be the voltage range of program threshold voltages for the target data block in the operation250. The processing circuit124may select the second voltage range VR2to be the voltage range of program threshold voltages for the target data block in the operation260. In this embodiment, the upper limit of the first voltage range VR1is less than 30% of the upper limit of the second voltage range VR2and the first voltage range VR1comprises the lowest two program threshold voltage intervals V0and V1within the second voltage range VR2. In addition, the upper limit of the third voltage range VR3is less than 60% of the upper limit of the second voltage range VR2and the third voltage range VR3comprises the lowest four program threshold voltage intervals V0, V1, V2, and V3within the second voltage range VR2.

For example, when the communication interface126receives a first data D1to be written transmitted from the host device110, if the amount of stored data in the flash memory module130at that time is less than the first threshold TH1, the processing circuit124may select the first voltage range VR1to be the voltage range of program threshold voltage for a target data block, such as a first data block134A, and control the read and write circuit132to program cells in the first data block134A using program threshold voltages within the first voltage range VR1so as to write the first data D1into the first data block134A under an one-bit-per-cell mode, a.k.a. 1bpc mode hereinafter.

Afterward, when the communication interface126receives a second data D2to be written transmitted from the host device110, if the amount of stored data in the flash memory module130at that time is between the first threshold TH1and the second threshold TH2, the processing circuit124may select the third voltage range VR3to be the voltage range of program threshold voltage for a target data block, such as a second data block134G, and control the read and write circuit132to program cells in the second data block134G using program threshold voltages within the third voltage range VR3so as to write the second data D2into the second data block134G under a two-bit-per-cell mode, a.k.a. 2bpc mode hereinafter.

Afterward, when the communication interface126receives a third data D3to be written transmitted from the host device110, if the amount of stored data in the flash memory module130at that time is higher than the second threshold TH2, the processing circuit124may select the first voltage range VR2to be the voltage range of program threshold voltage for a target data block, such as a third data block134P, and control the read and write circuit132to program cells in the third data block134P using program threshold voltages within the second voltage range VR2so as to write the third data D3into the third data block134P under a three-bit-per-cell mode, a.k.a. 3bpc mode hereinafter.

In other words, different data blocks134of the flash memory module130may have different data storage modes at the same time. For example, in the previous embodiment, when the read and write circuit132just finished writing the third data D3into the third data block134P, the data storage mode of the third data block134P is the 3bpc mode. At the same time, the data storage mode of the first data block134A is the 1bpc mode and the data storage mode of the second data block134G is the 2bpc mode.

In addition, when deciding the voltage range of program threshold voltages for a target data block, the processing circuit124may also take the property of the data to be written into consideration. For example,FIG.4shows a simplified flowchart400illustrating a method for writing data into flash memory in accordance with a second example embodiment, andFIG.5shows a simplified flowchart500illustrating a method for writing data into flash memory in accordance with a third example embodiment.

In the embodiment shown inFIG.4, when the communication interface126receives a fourth data D4to be written transmitted from the host device110, the processing circuit124firstly performs operation415to determine whether the fourth data D4is cold data. The term “cold data” as used herein refers to a type of data that is expected will not be frequently accessed. The processing circuit124may determine whether the fourth data D4is cold data or not according to the file type, file extension, logical address of the fourth data D4, or other criteria. If the processing circuit124determines that the fourth data D4is cold data, the processing circuit124proceeds to the operation260. Otherwise, the processing circuit124proceeds to the operation220.

In the embodiment shown inFIG.5, when the communication interface126receives a fifth data D5to be written transmitted from the host device110, the processing circuit124firstly performs operation515to determine whether the fifth data D5is hot data. The term “hot data” as used herein refers to a type of data that is expected will be frequently accessed. The processing circuit124may determine whether the fifth data D5is hot data or not according to the file type, file extension, logical address of the fifth data D5, or other criteria. If the processing circuit124determines that the fifth data D5is hot data, the processing circuit124proceeds to the operation230. Otherwise, the processing circuit124proceeds to the operation220.

In another embodiment, the processing circuit124may determine whether the fifth data D5is cold data or hot data first. If the processing circuit124determines that the fifth data D5is hot data, it proceeds to the operation230; if the processing circuit124determines that the fifth data D5is cold data, it proceeds to the operation260; and if the processing circuit124determines that the fifth data D5is not hot data nor cold data, it proceeds to the operation220.

In operations, the processing circuit124may also record a number of times each data block134was written under the 1bpc mode, a number of times each data block134was written under the 2bpc mode, and/or a number of times each data block134was written under the 3bpc mode in the recording medium122. For facilitating or simplifying the recording operation, the processing circuit124may record a number of times the data block134was erased under a particular mode, such as the 1bpc mode, the 2bpc mode, or the 3bpc mode, to be a representative value of the number of times the data block134was written under the particular mode. In the operation270described previously, the processing circuit124may select an appropriate data block134to be the target data block according to the information recorded in the recording medium122, so that different data blocks can be evenly written under a particular mode to avoid overutilization of particular data blocks.

In addition, the processing circuit124may also record the usage situation of data blocks134of the flash memory module130in the recording medium122, and decide whether to combine contents stored in some data blocks into a data block with sufficient storage capacity to release more data blocks for later usage.

For example, the processing circuit124may record an amount of data blocks in use within the flash memory module130in the recording medium122, and combine contents stored in some data blocks into a data block having sufficient storage capacity when the amount of data blocks in use is higher than a third threshold TH3. Alternatively, the processing circuit124may record an amount of empty data blocks within the flash memory module130in the recording medium122, and combine contents stored in some data blocks into a data block having sufficient storage capacity when the amount of empty data blocks is lower than a fourth threshold TH4.

When combining contents stored in different data blocks, the processing circuit124may control the read and write circuit132to write valid data stored in one or more candidate data blocks containing data written under the 1bpc mode, such as the data blocks134A and134B, into a target data block, such as the data block134H or134Q, under the 2bpc mode or 3bpc mode, and to erase the candidate data blocks. The processing circuit124may control the read and write circuit132to write valid data stored in one or more candidate data blocks containing data written under the 2bpc mode, such as the data blocks134G and134H, into a target data block, such as the data block134P or134Q, under the 3bpc mode, and to erase the candidate data blocks. The processing circuit124may control the read and write circuit132to write valid data stored in a first candidate data block containing data written under the 1bpc mode, such as the data block134A or134B, into a target data block, such as the data block134P or134Q, under the 3bpc mode, to write valid data stored in a second candidate data block containing data written under the 2bpc mode, such as the data block134G or134H, into the target data block, such as the data block134P or134Q, under the 3bpc mode, and to erase the first and second candidate data blocks.

Since the processing circuit124dynamically adjusts the voltage range of program threshold voltages for the target data block134to be written according to the amount of stored data in the flash memory module130, the same data block134may be configured to have different program threshold voltage ranges at different points of time. For example, when the amount of stored data in the flash memory module130is less than the first threshold TH1, if the data block134Q is selected as the target data block, then the processing circuit124may control the read and write circuit132to program cells in the target data block134Q using program threshold voltages within the first voltage range VR1so as to write data into the target data block134Q under the 1bpc mode.

The data block134Q may be erased due to various causes in the later operations. When the amount of stored data in the flash memory module130is increased to a level between the first threshold TH1and the second threshold TH2, if the data block134Q is again selected to be a target data block, the processing circuit124may control the read and write circuit132to program the cells in the target data block134Q using program threshold voltages within the third voltage range VR3so as to write new data into the target data block134Q under the 2bpc mode.

Afterward, the data block134Q may be again erased due to various causes in the later operations. When the amount of stored data in the flash memory module130is increased to a level higher than the second threshold TH2, if the data block134Q is again selected to be a target data block, the processing circuit124may control the read and write circuit132to program the cells in the target data block134Q using program threshold voltages within the second voltage range VR2so as to write new data into the target data block134Q under the 3bpc mode.

As described previously, the processing circuit124dynamically adjusts the voltage range of program threshold voltages for the target data block134to be written according to the amount of stored data in the flash memory module130, or even directly assigns program threshold voltages to be used by the read and write circuit132when writing data into the target data block134. When the amount of stored data in the flash memory module130reaches a lower level, the processing circuit124controls the read and write circuit132of the flash memory module130to program the data block134using lower program threshold voltages, such as threshold voltages within the voltage interval V0or threshold voltages within the voltage interval V1ofFIG.3. This not only reduces required power consumption for writing data into the data block, but also effectively improves the wear capacity of the cells of the flash memory module130, thereby increasing the reliability of data stored in the flash memory module130.

In addition, since the program threshold voltages of the data block134can be assigned by the processing circuit124, the processing circuit124may also directly assign the read threshold voltage to be used by the read and write circuit132when reading data from the target data block134, thereby increasing data reading speed of the flash memory module130.

Thus, by using the above control method of the flash memory controller120, the flash memory module130is allowed to provide high storage capacity with low cost when realized by the MLC chips, TLC chips, or even higher-level chips, and the endurance, wear capacity, and data reliability of the flash memory module130can also be effectively improved. Such architecture is beneficial not only for saving power consumption, but also for expediting the promotion and applications of solid-state disks.

Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.