Patent ID: 12210460

DETAILED DESCRIPTION

Aspects of the present disclosure are directed to memory sub-systems, in particular to memory sub-systems that include a translation lookaside buffer (TLB) access monitor component. A memory sub-system can be a storage system, storage device, a memory module, or a combination of such. An example of a memory sub-system is a storage system such as a solid-state drive (SSD). Examples of storage devices and memory modules are described below in conjunction withFIG.1, et alibi. In general, a host system can utilize a memory sub-system that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

A memory device can be a non-volatile memory device. One example of a non-volatile memory device is a three-dimensional cross-point memory device that includes a cross-point array of non-volatile memory cells. Other examples of non-volatile memory devices are described below in conjunction withFIG.1. A non-volatile memory device, such as a three-dimensional cross-point memory device, can be a package of one or more memory components (e.g., memory dice). Each die can consist of one or more planes. Planes can be grouped into logic units. For example, a non-volatile memory device can be assembled from multiple memory dice, which can each form a constituent portion of the memory device.

A non-volatile memory device is a package of one or more dies. Each die can consist of one or more planes. Planes can be groups into logic units (LUN). Each plane can consist of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. A block hereinafter refers to a unit of the memory device used to store data and can include a group of memory cells, a word line group, a word line, or individual memory cells. For some memory devices, blocks (also hereinafter referred to as “memory blocks”) are the smallest area than can be erased. Pages cannot be erased individually, and only whole blocks can be erased.

Each of the memory devices can include one or more arrays of memory cells. Depending on the cell type, a cell can store one or more bits of binary information, and has various logic states that correlate to the number of bits being stored. The logic states can be represented by binary values, such as “0” and “1”, or combinations of such values. There are various types of cells, such as single level cells (SLCs), multi-level cells (MLCs), triple level cells (TLCs), and quad-level cells (QLCs). For example, a SLC can store one bit of information and has two logic states.

Memory technology is moving away from storage and towards a processing device, such as a central processing unit (CPU), within a memory hierarchy. This may cause system-level performance challenges for memory technologies having higher access latencies, such as DRAM. Some previous approaches to mitigating (e.g., reducing, hiding) access latencies may include caching and/or prefetching.

Memory technologies having memory access characteristics similar to those of DRAM, for example, can be positioned close to a processing device within a memory hierarchy. As a result, it can be beneficial to make such memory technologies operate in a manner similar to DRAM. Some previous approaches include prefetching and caching data to bridge the access time gap between DRAM and other types of memory. Such previous approaches may include keeping a recent history of access requests and/or accesses of data and using this history as an input signal to a prefetcher or cache. Effective caching and prefetching hardware can utilize many input signals to determine usage patterns and/or data temperatures. As used herein “data temperature” of metadata, corresponding to data value, is indicative of a likelihood of the data values being accessed (e.g., read, written, erased) in the near future. Data values that have not been accessed recently (e.g., not within a threshold amount of time) have decreased or lower data temperatures whereas data values that have been accessed recently (e.g., within a threshold amount of time) have increased or higher data temperatures.

Aspects of the present disclosure address deficiencies of previous approaches by monitoring a TLB, of a CPU, for instance, to drive decisions whether to prefetch and/or cache data on a memory device. TLB fill requests and/or TLB flush requests can be used as input signals to caching and/or prefetching to improve access latency of a memory device. As a non-limiting example of operation of a TLB, a CPU may issue a TLB fill request in response to software being executed by the CPU requesting to access a page of data of a memory device that does not have a corresponding page table entry (PTE) (e.g., an address of the memory device) stored in the TLB. Such a situation can be referred to as a TLB miss. In response to a TLB miss, hardware, of a host system, for instance, may perform a page table walk to retrieve the physical address mapping for the desired page of data. By detecting a TLB fill request, the physical address mapping of the desired page of data can be identified and extracted from the TLB fill request. Extracting the physical address mapping of the desired page of data can enable migration of the desired page of data to a faster tier of memory (e.g., DRAM) to occur at least partially concurrently with return of the TLB data to the CPU and a subsequent request for the page of data.

While a TLB fill request is indicative of a prefetch opportunity, a TLB flush request is indicative of a page of data having a decreased data temperature. Data values that are frequently accessed can be “hotter” than other data values that are not accessed as frequently. Data values having lower data temperatures can be candidates for removal (eviction) from a faster tier of memory (e.g., DRAM). For instance, a mapping of a virtual address of cooler data values to a physical address of a memory device may not be cached in a TLB. As a result, an access request for cooler data values will be preceded by a TLB fill request. A TLB fill request can be indicative of increases of data temperatures of cooler data values (the cooler data values are “warming up”).

Embodiments of the present disclosure include forward-looking approaches where operation of a TLB is indicative of future states of a system including the TLB. In contrast to previous approaches to access latency mitigation that rely on historical data, embodiments of the present disclosure do not store any history. Rather, a TLB operation can be detected and used to directly predict whether data is likely to be accessed and/or likely not to be accessed. Predictions made by embodiments described herein to drive caching and/or prefetching are accurate because they are based on data temperatures, data from an operation system (OS) (e.g., page table mappings), and/or hardware capable of detecting memory accesses. Benefits of embodiments described herein include, but are not limited to, improved performance of a memory sub-system via hiding access latency and increased efficiency via less read/write amplification resulting from incorrect predictions of previous approaches. Embodiments of the present disclosure do not require changes to an existing processing device of a system and may require, if any, minor software changes at the OS level.

FIG.1illustrates an example computing system100that includes a memory sub-system110in accordance with some embodiments of the present disclosure. The memory sub-system110can include media, such as one or more non-volatile memory devices (e.g., memory device130).

A memory sub-system110can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of a storage device include a solid-state drive (SSD), a flash drive, a universal serial bus (USB) flash drive, an embedded Multi-Media Controller (eMMC) drive, a Universal Flash Storage (UFS) drive, a secure digital (SD) card, and a hard disk drive (HDD). Examples of memory modules include a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), and various types of non-volatile dual in-line memory modules (NVDIMMs).

The computing system100can be a computing device such as a desktop computer, laptop computer, server, network server, mobile device, a vehicle (e.g., airplane, drone, train, automobile, or other conveyance), Internet of Things (IoT) enabled device, embedded computer (e.g., one included in a vehicle, industrial equipment, or a networked commercial device), or such computing device that includes memory and a processing device.

The computing system100can include a host system120that is coupled to one or more memory sub-systems110. In some embodiments, the host system120is coupled to different types of memory sub-system110.FIG.1illustrates one example of a host system120coupled to one memory sub-system110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, and the like.

The host system120can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., an SSD controller), and a storage protocol controller (e.g., PCIe controller, SATA controller). The host system120uses the memory sub-system110, for example, to write data to the memory sub-system110and read data from the memory sub-system110.

The host system120can be coupled to the memory sub-system110via a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), a double data rate (DDR) memory bus, a dual in-line memory module (DIMM) interface (e.g., DIMM socket interface) that supports DDR), Open NAND Flash Interface (ONFI), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transmit data between the host system120and the memory sub-system110. The host system120can further utilize an NVM Express (NVMe) interface to access components (e.g., memory devices130) when the memory sub-system110is coupled with the host system120by the PCIe interface. The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system110and the host system120.FIG.1illustrates a memory sub-system110as an example. In general, the host system120can access multiple memory sub-systems via a same communication connection, multiple separate communication connections, and/or a combination of communication connections.

Some examples of non-volatile memory devices (e.g., the memory device130) include negative-and (NAND) type flash memory and write-in-place memory, such as three-dimensional cross-point (“3D cross-point”) memory device, which is a cross-point array of non-volatile memory cells. A cross-point array of non-volatile memory can perform bit storage based on a change of bulk resistance, in conjunction with a stackable cross-gridded data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform a write in-place operation, where a non-volatile memory cell can be programmed without the non-volatile memory cell being previously erased. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

The memory device130can include one or more arrays of memory cells. One type of memory cell, for example, single level cells (SLC) can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple level cells (TLCs), quad-level cells (QLCs), and penta-level cells (PLC) can store multiple bits per cell. In some embodiments, the memory device130can include one or more arrays of memory cells such as SLCs, MLCs, TLCs, QLCs, or any combination of such. In some embodiments, a particular memory device can include an SLC portion, and an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory device130can be grouped as pages that can refer to a logical unit of the respective memory devices used to store data. With some types of memory (e.g., NAND), pages can be grouped to form blocks.

Although non-volatile memory components such as three-dimensional cross-point arrays of non-volatile memory cells and NAND type memory (e.g., 2D NAND, 3D NAND) are described, the memory device130can be based on any other type of non-volatile memory or storage device, such as such as, read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide based memories, ferroelectric transistor random-access memory (FeTRAM), ferroelectric random access memory (FeRAM), magneto random access memory (MRAM), Spin Transfer Torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide based RRAM (OxRAM), negative-or (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

Memory sub-system controller115can communicate with the memory device130to perform operations, such as reading data, writing data, and/or erasing data stored on the memory device130, and other such operations. The memory sub-system controller115can include hardware such as one or more integrated circuits and/or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller115can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

The memory sub-system controller115can include a processor117(e.g., a processing device) configured to execute instructions stored in a local memory119. In the illustrated example, the local memory119of the memory sub-system controller115includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory sub-system110, including handling communications between the memory sub-system110and the host system120.

In some embodiments, the local memory119can include memory registers storing memory pointers, fetched data, etc. The local memory119can also include read-only memory (ROM) for storing micro-code. While the example memory sub-system110inFIG.1has been illustrated as including the memory sub-system controller115, in another embodiment of the present disclosure, a memory sub-system110does not include a memory sub-system controller115, and can instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory sub-system).

In general, the memory sub-system controller115can receive commands or operations from the host system120and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device130. The memory sub-system controller115can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a virtual address (e.g., logical block address (LBA), namespace) and a physical address (e.g., physical block address, physical media locations, etc.) that are associated with the memory device130. The memory sub-system controller115can further include host interface circuitry to communicate with the host system120via the physical host interface. The host interface circuitry can convert the commands received from the host system120into command instructions to access the memory device130as well as convert responses associated with the memory device130into information for the host system120.

The memory sub-system110can also include additional circuitry or components that are not illustrated. In some embodiments, the memory sub-system110can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., a row decoder and a column decoder) that can receive an address from the memory sub-system controller115and decode the address to access the memory device130.

In some embodiments, the memory device130includes local media controller135that operates in conjunction with memory sub-system controller115to execute operations on one or more memory cells of the memory device130. An external controller (e.g., the memory sub-system controller115) can externally manage the memory device130(e.g., perform media management operations on the memory device130). In some embodiments, the memory device130can be a managed memory device. A managed memory device is a raw memory device combined with a local controller (e.g., the local controller135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

The memory sub-system110can include a TLB access monitor component113. Although not shown inFIG.1so as to not obfuscate the drawings, the TLB access monitor component113can include special purpose circuitry in the form of an ASIC, FPGA, state machine, and/or other logic circuitry that can enable the TLB access monitor component113to predict access requests from the host system120to the memory device130based on TLB fill requests and/or TLB flush requests.

In some embodiments, the memory sub-system controller115includes at least a portion of the TLB access monitor component113. For example, the memory sub-system controller115can include the processor117(e.g., processing device) configured to execute instructions stored in the local memory119for performing the operations described herein. In some embodiments, the TLB access monitor component113can be part of the host system120, an application, or an OS.

In a non-limiting example, an apparatus (e.g., the computing system100) can include the TLB access monitor component113. The TLB access monitor component113can be resident on the memory sub-system110. As used herein, the term “resident on” refers to something that is physically located on a particular component. For example, the TLB access monitor component113being “resident on” the memory sub-system110refers to a condition in which the hardware circuitry that comprises the TLB access monitor component113is physically located on the memory sub-system110. The term “resident on” can be used interchangeably with other terms such as “deployed on” or “located on,” herein. The TLB access monitor component113can be on die with the memory device130.

The TLB access monitor component113can maintain a page table (not illustrated byFIG.1). As used herein, the page table maintained by the TLB access monitor component113refers to one or more local page tables associated with respective memory devices130. The TLB access monitor component113can be configured to receive signaling, from the host system120, indicative of addresses associated with page table allocations and maintain the addresses in the page table. The TLB access monitor component113can be configured to prefetch data at a target address (e.g., a target physical address) of the memory device130associated with a TLB fill request in response to the page table including the target address. The TLB access monitor component113can initiate the prefetch for data at the target address in advance of receipt of the command (e.g., from the host system120) to access the memory device130at the target address. As such, the TLB access monitor component113can be configured to, in response to the page table including the target address, issue, or cause to be issued, a prefetch command (e.g., via the memory sub-system controller115) to the memory device130to retrieve data at the target address. The TLB access monitor component113can intercept (in some instances, concurrently with prefetching data at the target address) an access command from the host system120for data at the target address. In some embodiments, in response to issuing a prefetch command for data at the target address, signaling can be provided to the host system120to prevent the host system120from generating access commands for data at the target address during the prefetch. The TLB access monitor component113and/or the memory sub-system controller115can include logic to provide such signaling to the host system120.

In some embodiments, the TLB access monitor component113can be configured to, in response to the page table maintained by the TLB access monitor component113not including a target address associated with a TLB fill request, provide an access command (e.g., an access request) for data at the address (e.g., received from the host system120) to the memory device130. Because the page table did not include the target address, a prefetch command is not issued. The memory device130can communicate the accessed data to the host system120directly, bypassing the TLB access monitor circuitry113.

In some embodiments, the TLB access monitor component113can be configured to responsive to the page table including the address, provide, to the host system120, signaling indicative of an increased data temperature of the data associated with the address in response to prefetching the data. The TLB access monitor component113can be configured to provide, to the memory device130, signaling indicative of a decreased data temperature of a page of data associated with an address associated with a TLB flush request.

The TLB access monitor component113can determine whether a page table maintained on the circuitry includes a physical address of the memory device130corresponding to a virtual address of a TLB fill request from the host system120. Responsive to determining that the page table includes the physical address, signaling indicative of a completion of the TLB fill request can be provided from the TLB access monitor component113to the host system120. The TLB access monitor component113can prefetch, from the memory device130, a page of data at the physical address. The TLB access monitor component113can provide, to the host system120, signaling indicative of the page of data. Responsive to determining that the page table does not include the physical address, the TLB access monitor component113can forward, to the memory device130, signaling from the host system120indicative of a command to access to the page of data at the physical address. The TLB access monitor component113can receive, from the memory device130, signaling indicative of a PTE associated with the TLB fill request and decode the PTE to obtain the physical address corresponding to the virtual address of the TLB fill request.

FIG.2is a block diagram representation of TLB access monitoring in accordance with some embodiments of the present disclosure. The dashed line represents the TLB access monitor component213and functionality thereof. The TLB access monitor component213can be analogous to the TLB access monitor component113described in association withFIG.1. The region ofFIG.2illustrated above the dashed line includes representations of components and functionalities of a processing device250. The processing device250can be a CPU, for example, of a host system, such as the host system120. The region ofFIG.2illustrated below the dashed line includes representations of components and functionalities of the memory device230. The memory device230can be analogous to the memory device130described in association withFIG.1.

Prior to accessing data stored on the memory device230at a virtual address245, the processing device250can translate the virtual address245to a physical address of the memory device230. To translate the virtual address245, the processing device250can determine whether the TLB241includes the corresponding physical address. If the TLB241does not store the corresponding physical address, a TLB miss, then a page table walker242performs a TLB fill operation243by walking a page table247of the memory device230to retrieve a PTE249, which includes the corresponding physical address, from the page table247. The corresponding physical address is then stored (cached) in the TLB241. By storing the corresponding physical address in the TLB241, subsequent accesses for data at the virtual address245can retrieve the PTE249from the TLB241rather than the page table walker242accessing the page table247to retrieve the PTE249. A PTE, such as the PTE249, stored in the TLB241can be removed from the TLB241via a TLB flush operation244. The TLB access monitor component213uses the TLB fill operation243and/or the TLB flush operation244as indications of future requests of data. Predictions made by the TLB access monitor component213are described further in association withFIGS.3-4.

FIG.3is a block diagram representation of prefetching data based on a TLB fill request in accordance with some embodiments of the present disclosure. The processing device (e.g., CPU)350, the page table walker342, the TLB access monitor component313, the PTE349, and the memory device330can be analogous to the processing device250, the page table walker242, the TLB access monitor component213, the PTE249, and the memory device230described in association withFIG.2.

The page table walker342can issue a TLB fill request348. Although the page table walker342is illustrated as a component of the CPU350, embodiments are not so limited. For example, the page table walker342can be coupled to the CPU350. As illustrated at363, the TLB access monitor component313can detect the TLB fill request348and determine whether a PTE (e.g., the PTE349) associated with the TLB fill request348is stored in a page table361of the TLB access monitor component313. As illustrated at360, the OS356, which is executed by the CPU350, can report page table allocations to the page table361. The OS356is illustrated as two separated boxes for ease of illustration only and not intended to imply any differences.

The TLB access monitor component313can initiate a prefetch operation without an access request from the CPU350because the TLB access monitor component313uses the TLB fill request348as an indicator of the access request, at370, that follows the TLB fill request348. As illustrated at352, the TLB access monitor component313can issue a prefetch request to the memory device330. The prefetch request is for data stored at a physical address associated with the PTE. As illustrated at367, in response to the prefetch request, the memory device330can read a page of data associated with the physical address. As illustrated at371, the TLB access monitor component313can provide the prefetched page of data.

Access latency associated with reading the page of data from the memory device330is mitigated by the TLB access monitor component313initiating the prefetch operation, at367, for the page of data before the OS356requests the page of data, at370. The prefetch operation, at367, for the page of data may take a similar amount of time to complete and provide the page of data, at371, to the CPU350as completing a read operation associated with an access command issued by the CPU350, at370, and providing, at372, the page of data to the CPU350. However, because the prefetch operation, at367, is initiated prior to receiving an access command, at370, and a resulting read operation, the page of data is provided, at371, to the CPU350, by the TLB access monitor component313, sooner than by a read operation resulting from the access request, at372. As such, access latency of the memory device330is mitigated (e.g., at least partially hidden) because the page of data is provided to the CPU350earlier.

If the page table361does not include a target PTE of a PTE request, then the TLB access monitor component313does not initiate a prefetch operation. As illustrated at365, the memory device330loads (reads) the target PTE in response to the TLB access monitor component313forwarding the request for the target PTE. As illustrated at368, in response to receiving the target PTE loaded (read) from the memory device330, the TLB access monitor component313provides a response, to the CPU350, that completes the TLB fill operation (or is indicative of completion of the TLB fill operation). Then, as illustrated at370, the OS356can issue an access command for the page of data associated with the physical address of the TLB fill request348in response to the completion of the TLB fill operation, to the CPU350, that completes the TLB fill operation (or is indicative of completion of the TLB fill operation). Because a prefetch operation was not initiated, as determined by the TLB access monitor component313at369, the TLB access monitor component313provides the access command to the memory device330as illustrated at368. As illustrated at367, the memory device330reads the page of data as part of a read operation in association with the access command. As illustrated at372, the memory device330can provide the page of data directly to the CPU350, bypassing the TLB access monitor component313.

FIG.4is a block diagram representation of indicating data temperature based on a TLB flush request in accordance with some embodiments of the present disclosure. The processing device (e.g., CPU)450, the TLB access monitor component413, the page table walker442, and the memory device430can be analogous to the processing device350, the TLB access monitor component313, the page table walker342, and the memory device330described in association withFIG.3.

The TLB442can issue a TLB flush request451. As illustrated at481, the TLB access monitor component413can detect the TLB flush request451. As illustrated at482, the TLB access monitor component413can provide a memory request to the memory device430. As illustrated at483, the memory device430can write a PTE in association with the memory request. As illustrated at484, the TLB access monitor component413can provide an indication of a cool or cold data temperature of a page of data at a physical address associated with the TLB flush request451. The memory device430can use the indication of the cool or cold data temperature of the page of data that a TLB fill request will precede a subsequent access request for that page of data.

FIG.5is flow diagram corresponding to a method596for TLB access monitoring in accordance with some embodiments of the present disclosure. The method596can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method596is performed by the TLB access monitor component113described in association withFIG.1. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

At operation597, whether a page table maintained on circuitry of a memory device includes a virtual address associated with a TLB flush request can be determined by the circuitry.

At operation598, responsive to determining that the page table includes a physical address of the memory device corresponding to the virtual address, signaling indicative of a data temperature of a page of data corresponding to the physical address can be provided by the circuitry to the memory device. The signaling indicative of the data temperature of the page of data can include an indication that the data temperature of the page of data is cool. The signaling indicative of the data temperature of the page of data can include an indication that the page of data has not been accessed within a threshold amount of time.

Although not specifically illustrated byFIG.5, in some embodiments, the method596can include providing, by the circuitry to the memory device, different signaling indicative of the TLB flush request.

FIG.6is a block diagram of an example computer system698in which embodiments of the present disclosure may operate. For example,FIG.6illustrates an example machine of a computer system698within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, can be executed. In some embodiments, the computer system698can correspond to a host system (e.g., the host system120described in association withFIG.1) that includes, is coupled to, or utilizes a memory sub-system (e.g., the memory sub-system110) or can be used to perform the operations of a controller (e.g., to execute an operating system to perform operations corresponding to the TLB access monitor component113). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

The example computer system698includes a processing device650(e.g., the processing device350described in association withFIG.3), a main memory630(e.g., ROM, flash memory, DRAM such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory606(e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system618, which communicate with each other via a bus630.

The processing device650represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. The processing device650can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device698is configured to execute instructions626for performing the operations and steps discussed herein. The computer system698can further include a network interface device608to communicate over the network611.

The data storage system618can include a machine-readable storage medium624(also referred to as a computer-readable medium) on which one or more sets of instructions626or software embodying any one or more of the methodologies or functions described herein is stored. The instructions626can also reside, completely or at least partially, within the main memory604and/or within the processing device650during execution thereof by the computer system698, the main memory630, and the processing device698also constituting machine-readable storage media. The machine-readable storage medium624, data storage system618, and/or main memory630can correspond to the memory sub-system110.

In some embodiments, the instructions626can include instructions to implement functionality corresponding to a TLB access monitor component (e.g., the TLB access monitor component113). For instance, the instructions626can include instructions to maintain a page table including a plurality of addresses of a memory device associated with a plurality of page table allocations by an operating system. The instructions626can include instructions to determine whether the page table includes a physical address associated with a TLB fill request. The instructions626can include instructions to, responsive to determining that the page table includes the physical address associated with the TLB fill request, initiate a prefetch operation for a page of data stored on the memory device at the physical address. The instructions626can include instructions to intercept, from the operating system, signaling indicative of a command to access a page of data stored on the memory device at the physical address. The instructions626can include instructions to, responsive to determining that the page table includes the physical address associated with the TLB fill request, prevent communication of the command to the memory device. The instructions626can include instructions to intercept the command concurrently with execution of the prefetch operation. The instructions626can include instructions to responsive to determining that the page table does not include the physical address associated with the TLB fill request, provide the command to the memory device.

While the machine-readable storage medium624is shown in an example embodiment to be a single medium, the term “machine-readable storage medium” should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term “machine-readable storage medium” shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term “machine-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the ways used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions, which can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as a read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.

In the foregoing specification, embodiments of the disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications can be made thereto without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.