Patent ID: 12261084

In the drawings, which are not necessarily drawn to scale, like reference symbols may indicate like and/or similar components (elements, structures, etc.) in different views. The drawings illustrate generally, by way of example, but not by way of limitation, various implementations discussed in the present disclosure. Reference symbols shown in one drawing may not be repeated for the same, and/or similar elements in related views. Reference symbols that are repeated in multiple drawings may not be specifically discussed with respect to each of those drawings, but are provided for context between related views. Also, not all like elements in the drawings are specifically referenced with a reference symbol when multiple instances of an element are illustrated.

DETAILED DESCRIPTION

This disclosure relates to packaged semiconductor device apparatus and associated methods of manufacturing packaged semiconductor devices. More specifically, this disclosure relates to fan-out wafer level packages (FOWLPs) for packaging semiconductor devices (semiconductor die), and associated manufacturing processes. The FOWLPs and manufacturing approaches disclosed herein can have reduced manufacturing cost and improved reliability over current FOWLP implementations.

For instance, using the approaches described herein, FOWLPs including semiconductor die that are encapsulated, at least partially, on all sides (e.g., six-sided encapsulation) can be produced using a single molding operation, as compared to current approaches, which can include multiple molding operations and/or molding compound grinding operations. For example, in some implementations, such as those described herein, FOWLPs can include semiconductor die that are fully encapsulated in molding compound on five sides (e.g., a back side surface and four side surfaces), and partially encapsulated on a front side surface (e.g., an active surface) using a single molding operation, which can reduce manufacturing costs.

In such approaches, semiconductor die included in a FOWLP can be mold-locked, as a result of such six-sided encapsulation. Such mold locking can improve structural stability of a resulting FOWLP, as compared to FOWLPs produced using current approaches. This improved structural stability can prevent stresses at edges of the semiconductor die that can cause damage, such as cracking of the semiconductor die. Such stresses, in current FOWLPs, can occur as a result of inadequate material coverage (e.g., voids due to insufficient step coverage) and/or mismatches in thermal characteristics (e.g., expansion and contraction) of materials included in a FOWLP, such as semiconductor materials, molding compound materials, dielectric (insulating) materials, and/or conductive materials (e.g., metal layers).

FIGS.1A and1Bare diagrams illustrating a FOWLP100.FIG.1Ais a diagram illustrating a plan (top side) view of the FOWLP100.FIG.1Bis a diagram illustrating a cross-sectional view of the FOWLP100ofFIG.1Aalong the section line1B-1B shown inFIG.1A. Accordingly, the following discussion of the FOWLP100is made with respect to bothFIGS.1A and1B. InFIG.1A, the plan view of the FOWLP100is illustrated such that internal elements of the FOWLP100are shown, so as to illustrate relationships of the various elements of the FOWLP100to one another. In some implementations, these internal elements may, or may not be visible in such a plan view. That is, the FOWLP100is, inFIG.1A, shown as a partial x-ray, or ghost view, to illustrate arrangement of the various elements of the FOWLP100. Further, inFIG.1B, the FOWLP100is illustrated prior to being separated (e.g., singulated) from a plurality of FOWLPs (including other semiconductor die), such as can be concurrently formed from a plurality of semiconductor die that are produced on a semiconductor wafer.

As shown inFIGS.1A and1B, the FOWLP100can include a semiconductor die105, an insulating layer115, a molding compound125, and a signal distribution (e.g., fan-out) structure135. InFIG.1A, perimeter edges (e.g. four perimeter edges) of the semiconductor die are indicated with the reference number105. As shown inFIGS.1A and1B, the semiconductor die105can include conductive bumps107, edge surfaces109, a backside surface111, and an active surface113. In some implementations, the conductive bumps107can be disposed on the active surface113of the semiconductor die105, and can provide electrical connections to a circuit and/or electrical device (e.g., a power semiconductor device) that is implemented (as an integrated circuit) on the active surface113of the semiconductor die105. The conductive bumps107can include metal, solder, solder flux, and/or any suitable electrically conductive material or combination of materials.

As shown inFIGS.1A and1B, the edge surfaces109and the backside surface111of the semiconductor die105can be fully encapsulated in the molding compound125. As also shown in inFIGS.1A and1B, the molding compound125can wrap around, e.g., from the side surfaces109onto a portion of the active surface113of the semiconductor die105, partially encapsulating the active surface113and locking (securing, mold locking, etc.) the semiconductor die105in the molding compound125. As noted above, such mold locking can prevent reliability issues in the FOWLP100, such as cracking of the semiconductor die105. In the FOWLP100ofFIGS.1A and1B, the molding compound125can also be disposed under (e.g., extend under, etc.) the signal distribution structure135.

As illustrated inFIGS.1A and1B, the insulating (e.g., dielectric) layer115, which can be a polyimide layer, a glass layer, or any other appropriate insulating material can be disposed on the active surface113and between the conductive bumps107of the semiconductor die105. In the FOWLP100, the portion of the active surface113of the semiconductor die105between the conductive bumps and the outer edges of the semiconductor die105can be devoid of the insulating layer115. Accordingly, during a molding operation for the FOWLP100, the molding compound can encapsulate the portion of the active surface113that is devoid of the insulating layer115, while the insulating layer115can prevent (block, etc.) the molding compound125from flowing between the conductive bumps107during the molding process.

In the FOWLP100ofFIGS.1A and1B, the signal distribution structure135can include a first dielectric layer137a(which can be referred to an inter-layer dielectric layer), a second dielectric layer137b, electrical connections139and conductive bumps143. The first dielectric layer137aand the second dielectric layer137b(which can also be referred to as insulating layers137aand137b) can include glass, polyimide, oxide, and/or any other appropriate dielectric materials or combination of dielectric materials.

The first dielectric layer137acan have via openings141formed therein, where a respective via opening141can be formed over each of the conductive bumps107of the semiconductor die105. The first dielectric layer137acan be disposed on the conductive bumps107, disposed on the insulating layer115, and on the molding compound125. The first dielectric layer137acan have a planar (upper) surface, which can be planarized using an appropriate process for the particular dielectric material used. The electrical connections139of the signal distribution structure135can be disposed on the planar surface of the first dielectric layer137aand disposed in (and extend through) respective via openings141to electrically couple the electrical connections139with the conductive bumps107. In some implementations, the electrical connections139can be formed by patterning a deposited conductive (metal) layer, e.g., using photolithography techniques.

In the FOWLP100, the second dielectric layer137bcan be disposed on the first dielectric layer137aand the electrical connections139. As with the first dielectric layer137a, the second dielectric layer137acan have a planar (upper) surface. The second dielectric layer137bcan have via openings145defined therein, where the conductive bumps143can each be disposed in a respective via opening145, providing electrical connections from the conductive bumps143to the conductive bumps107of the semiconductor die105(e.g., through the electrical connections139).

As noted above, inFIG.1B, the FOWLP100is illustrated prior to being separated (e.g., singulated) from a plurality of FOWLPs, such as can be concurrently formed from a plurality of semiconductor die, including semiconductor die105aand105b, in addition to the semiconductor die105. InFIG.1B, only portions (part) of the semiconductor die and FOWLPs on either side of the FOWLP100are illustrated. In some implementations, the semiconductor die105,105aand105bcan be produced on a semiconductor wafer and can implement a same, or a different circuit or device, depending on the particular implementation. As shown inFIG.1B, saw streets can be defined by spaces150between signal distribution structures135of the FOWLP. The molding compound125can be cut (e.g., using a saw, a laser, plasma, etc.) to separate (singulate) the FOWLP100from other concurrently produced FOWLPs, such as respective FOWLPs including the semiconductor die105aand150b.

FIGS.2A through2Nare diagrams illustrating a process for producing a FOWLP, such as the FOWLP100ofFIGS.1A and1B. In some implementations, the process ofFIGS.2A-2Ncan be implemented to produce FOWLPs other than the FOWLP100. For instance, the process ofFIGS.2A-2N(or a similar process) can be use to produce a FOWLP including multiple semiconductor die. In such a multiple semiconductor die FOWLP, an associated signal distribution layer can, in addition to providing external electrical connections (e.g., via conductive bumps143), include electrical connections between the multiple semiconductor die included in such a FOWLP. In some implementations, other manufacturing processes can be used to produce a FOWLP, such as the FOWLPs described herein. However, for purposes of this disclosure and illustration, the process ofFIGS.2A-2Nwill be described with reference to the FOWLP100ofFIGS.1A and1B.

Referring toFIG.2A, a portion of a semiconductor substrate200that includes the semiconductor die105(as well as portions of adjacent semiconductor die105aand105b) is illustrated. As shown inFIG.2A, the electrically conductive bumps107can be disposed (formed, produced, etc.) on the active surface113of the semiconductor die105. For instance, the conductive bumps107can be disposed on a passivation (e.g., glass, dielectric, etc.) layer114. The conductive bumps107can be electrically connected with a circuit and/or semiconductor device that is defined on the active surface113of the semiconductor die105using electrical (e.g., Ohmic) contacts210that extend through the passivation layer114(e.g., through contact openings). For purposes of clarity, such circuitry and/or semiconductor devices on the active surface113of the semiconductor die105is/are not shown inFIGS.2A-2N.

In some implementations, the conductive bumps107can include an underlying (first) conductive material107a, and a second conductive material107bthat is disposed on the underlying conductive material107a. The second conductive material107bcan be formed using evaporation, electrolytic plating, electroless plating, ball drop, and/or screen printing processes. In some implementations, the second conductive material107bcan be aluminum (Al), tin (Sn), nickel (Ni), gold (Au), silver (Ag), lead (Pb), bismuth (Bi), copper (Cu), solder, and/or combinations thereof, and can further include a solder flux. In some implementations, the second conductive material107bcan be eutectic Sn/Pb, high-lead solder, or lead-free solder.

In some implementations, the second conductive material107bcan be bonded to the underlying conductive material107ausing an attachment or bonding process. For instance, the second conductive material107bcan be reflowed by heating the second conductive material107babove its melting point to form balls or bumps. In some implementations, the second conductive material107bcan be reflowed a second time, which can improve electrical contact (e.g., reduce resistance) to the underlying conductive material107a. Conductive bumps107, as described herein, are disclosed, by way of example, as one possible electrical interconnect that can be configured to provide electrical connections to circuitry formed on the active surface113of the semiconductor die105. In some implementations, other approaches for providing such electrical connections can be used, such as conductive paste, stud bumps, micro bumps, conductive pillars, or other electrical connections.

As further shown inFIG.2A, openings between the passivation layers114of the semiconductor die105,105aand105bcan define scribe (saw) streets220(indicated by dashed lines) between the semiconductor die. As described in further detail below with respect toFIG.2D, the semiconductor die105,105aand105bcan be singulated (separated along the scribe streets220) as part of the FOWLP manufacturing process ofFIGS.2A-2N.

As shown inFIG.2B, the insulating layer115can be formed on the active surface113of the semiconductor die105between the conductive bumps107. The insulating layer115can be formed using vapor deposition, printing, lamination, spin coating, spray coating, sintering, and/or other processes. The insulating layer115can include one or more layers of insulating material, such as silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), hafnium oxide (HfO2), benzocyclobutene (BCB), polyimide (PI), polybenzoxazoles (PBO), mold compound, polymer, and/or other dielectric material having appropriate structural and insulating properties.

As shown inFIG.2B(as well as inFIG.1A), the insulating layer115can substantially fill spaces between conductive bumps107on the active surface113, though some gaps between the conductive bumps107and the insulating layer115may be present. Further, as is shown inFIG.2B(andFIG.1A), in this example implementation, the insulating layer115can be formed between the conductive bumps107, where the insulating layer115contacts, at most, two sides of each conductive bump107. In other words, in this example implementation, the area of the active surface113between the conductive bumps107and the side surfaces109of the semiconductor die105can be devoid of the insulating layer115. Depending on the particular implementation, the insulating layer115can be formed as part of a wafer manufacturing process, or as part of a FOWLP manufacturing process. In some implementations, the insulating layer115can be formed prior to forming conductive bumps107, and via openings can be formed in the insulating layer115. In this example, the conductive bumps107can electrically contact the active surface113of the semiconductor die105through the openings that are formed in the insulating layer115. As also shown inFIG.2B, the semiconductor substrate200(and the semiconductor die105) can have a thickness (e.g., an initial or starting thickness) of T1.

Referring toFIG.2C, the semiconductor substrate200, including the semiconductor die105, can be inverted from the orientation shown inFIG.2Band mounted on a back-grinding tape (e.g., a stiff polyester tape)230using an adhesive layer235. As shown inFIG.2C, the adhesive layer235can be in contact with (disposed on) the conductive bumps107and the insulating layer115, which can secure the semiconductor substrate200to the back-grinding tape. A portion of the semiconductor substrate200(and the semiconductor die105) can be removed from the back side surface111using a grinding process. As shown inFIG.2C, the grinding process can reduce a thickness of the substrate200from the thickness T1ofFIG.2B, to a thickness T2, where T2<T1. As further shown inFIG.2, in some implementations, a back side metal layer106can be formed (e.g., using vapor deposition, sputtering, etc.) on the back side surface111of the semiconductor die105(e.g., the substrate200). While not specifically shown inFIGS.2D-2N, in some implementations, such a back side metal layer106can be included on the semiconductor die105of the example FOWLP100.

The process can then continue toFIG.2D, where the semiconductor substrate200, while still coupled with the back-grinding tape230via the adhesive layer235, can be inverted and the back side surface111of the substrate200can be coupled to an expandable dicing tape240and an adhesive layer245. The back-grinding tape230and the adhesive layer235can then be removed from the substrate200.

As shown inFIG.2D, after the back-grinding tape230and the adhesive layer235have been removed, the semiconductor die105can be singulated, e.g., from at least the semiconductor die105aand105b, by creating cut openings225through the semiconductor substrate200along the scribe streets220. In some implementations, the cut openings225can be formed using plasma etching, which can have certain advantages, such as forming precision side surfaces109along the saw streets220and, allowing for forming cut openings225of different widths on a same semiconductor wafer. In some implementations, the semiconductor die105can be singulated from the semiconductor substrate200using a saw blade or laser cutting tool. Semiconductor die105,105aand105bcan remain affixed to dicing tape240, and the FOWLP manufacturing process can move to the operations illustrated byFIGS.2E and2F. In some implementations, the singulated semiconductor die can be picked, inverted, and placed onto a separate carrier or tape, with spacings such as those shown inFIG.2G.

As shown inFIGS.2E and2F, the dicing tape240(and the adhesive layer245) between the die can be expanded in the x-direction and the y-direction (as shown by the axes inFIG.2F) to increase spacing (from a width of the cut openings225to the spacing S1) between the semiconductor die105and adjacent semiconductor die (e.g., the semiconductor die105aand105b). In some implementations, the dicing tape240and the associated adhesive layer245between the die can be differentially expanded in the x-direction and the y-direction using an expansion table that moves independently in the x-direction and the y-direction and stretches the dicing tape240(and the adhesive layer245). In some implementations, the semiconductor die can have different spacings in the x-direction than in the y-direction.

In some implementations, because the dicing tape240may not uniformly expand in both the x-direction and the y-direction, widths of the cut opening225for the saw streets220can differ between those that are aligned in the x-direction and those that are aligned it the y-direction, which can compensate for different amounts of expansion of the dicing tape240in the x-direction and the y-direction.

The process can then continue toFIG.2G, where the singulated semiconductor die105,105aand105b, while still coupled with the stretched dicing tape240via the adhesive layer245, can be inverted and coupled to another expandable (a second expandable) carrier or tape250(e.g., a polymer material) using an expandable adhesive layer255. The dicing tape240and the adhesive layer245can then be removed from the singulated semiconductor die.

As shown inFIG.2G, the expandable carrier or tape250(and the adhesive layer255) can be expanded (e.g., in both the x-direction and the y-direction) to further increase spacing between the semiconductor die105and adjacent semiconductor die (e.g., the semiconductor die105aand105b), such as from the spacing S1ofFIG.2Eto the spacing S2ofFIG.2G, where S2>S1. In some implementations, the carrier or tape250and the associated adhesive layer255can be differentially expanded in the x-direction and the y-direction using an expansion table that moves independently in the x-direction and the y-direction and stretches the carrier or tape250(e.g., to appropriately space the singulated semiconductor die for further processing to produce FOWLPs, such as the FOWLP100). In some implementations, the singulated semiconductor die can be picked and placed on a carrier or tape, such as the carrier or tape as described below with respect toFIG.2H, with spacings such as those shown inFIG.2G. In other embodiments, two or more semiconductor die can be placed such that they will be contained together into a single FOWLP.

As shown inFIG.2H, the singulated and spaced semiconductor die ofFIG.2Gcan be transferred (e.g., using one or more carrier to carrier or tape to tape transfers, such as those described above) to a carrier or tape260using an (adhesive) interface layer265. The carrier260can be formed from an overmold tape, a polymer, beryllium oxide, silicon, glass, or other suitable material for structural support. The interface layer265can be formed over (disposed on, etc.) a surface of the carrier260as a temporary adhesive bonding film, etch-stop layer, and/or thermal release layer. The carrier260and the associated interface layer265can then be disposed on the conductive bumps107and the insulating layer115for structural support, where spaces127can remain between the interface layer265and the active surface113of the semiconductor die105(e.g., to allow for mold locking the semiconductor die105in the molding compound125).

As also shown inFIG.2H, after coupling the singulated and spaced semiconductor die (e.g., with spacings S2) to the carrier260with the interface layer265, the molding compound (encapsulant)125can be disposed (e.g., deposited, flowed, etc.) over and between the semiconductor die105,105aand105b, as well as into the space(s)127, to achieve a six-sided (mold locked) encapsulation of the semiconductor die105(e.g. after curing of the molding compound125). Depending on the particular implementation, the molding compound125can be formed (applied, etc.) using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, film-assisted molding, spin coating, and/or any other suitable application process. The molding compound125can be a polymer, a polymer composite material, such as an epoxy resin with filler, an epoxy acrylate with filler, or a polymer with filler. The molding compound125can (should) be non-conductive, and provide physical support, and environmentally protect the semiconductor die105from external elements and contaminants.

FIG.2Iillustrates a portion of the molded structure ofFIG.2Hincluding the semiconductor die105, e.g., from the bottom side of the molded structure, as shown inFIG.2H, after removal of the carrier260and the interface layer265.FIG.2Iillustrates, in a plan view, an arrangement of the semiconductor die105, the conductive bumps107of the semiconductor die105, the insulating layer115, the molding compound125and the location of the space127, which is disposed around the conductive bumps107on a perimeter of the semiconductor die105. As shown inFIG.2I, a portion of the molding compound125is disposed in the space127, but does not extend into area of the insulation layer115.

FIGS.2J-2Lillustrate formation of the signal distribution structure135of the FOWLP100. As shown inFIG.2J, after removal of the carrier260and the interface layer265, the dielectric layer137acan be formed on the conductive bumps107, the insulating layer115and the molding compound125. The insulating layer137a, can be planarized using an appropriate process, such as a reflow process, a polishing process, etc. Via openings141can be formed in, and extend through the dielectric layer137ato the conductive bumps107. The electrical connections139can then be formed (e.g., by patterning a metal layer that is disposed, or formed on the dielectric layer137aand disposed in the via opening141). As noted above, the electrical connections139can be electrically coupled with respective conductive bumps107of the semiconductor die105.

FIG.2Killustrates a portion of the cross-sectional view ofFIG.2Jthat is indicated by the inset2K. As shown inFIG.2K, the electrical connection(s)139can be disposed on the planar upper surface of the dielectric layer137a, and also be disposed in (e.g., fill) the via opening(s)141to create electrical contact(s) with the conductive bump(s)107. As also shown inFIG.2K, the molding compound125can fill the space127between the semiconductor die105and the dielectric layer137a. As indicated inFIG.2K, the molding compound can have a thickness of T3between the semiconductor die105and the dielectric layer137a, and a width W1between the conductive bump and edge (edge surface109) of the semiconductor die. In some implementations, T3can be greater than or equal to 5 micrometers (μm), and W1can also be greater than or equal to 5 μm.

As shown inFIG.2L, after the operations illustrated inFIG.2J, the dielectric layer137bof the signal distribution structure135can be formed on the conductive layer137aand the electrical connections139. As with the insulating layer137a, the insulating layer137bcan be planarized using an appropriate process, such as a reflow process, a polishing process, etc. Via openings145can be formed in, and extend through the dielectric layer137bto the electrical connections139. The conductive bumps143of the signal distribution structure135can then be disposed (formed, etc.) in the via openings143(e.g., on respective electrical connections139).FIG.2Lcorresponds withFIG.1B.

As shown inFIG.2M, after completion of the signal distribution structure135, the structure (assembly) shown inFIG.2Lcan be coupled with a dicing tape270(e.g., a polymer base material) using an adhesive layer275. Channels155can be formed along the saw streets150shown in, for example,FIG.2L. As shown inFIG.2Mthe channels155can be formed completely through the molding compound125and into the adhesive layer275to singulate the FOWLP100, as shown inFIG.2N, from other concurrently formed FOWLPs. For instance, the channel155can be formed around each semiconductor die105,105aand105busing, e.g., a saw blade or laser cutting tool. In some embodiments, more than one semiconductor die105or different sizes and types of semiconductor die can be combined into each singulated FOWLP100.FIG.2Ncorresponds withFIG.1A. Accordingly, for the purpose of brevity, the details of the FOWLP100discussed with respect toFIGS.1A and1B, are not repeated again here.

FIG.3is a schematic diagram illustrating semiconductor die105,105aand105bdisposed on a carrier360for fan-out wafer level packaging. The carrier360can, for example, be the carrier260ofFIG.2H(e.g., after the two carrier stretching processes ofFIGS.2E and2G, and transfer of the semiconductor die105,105aand105bto the carrier260). Accordingly, the spacing of the semiconductor die105inFIG.3could be, with reference toFIG.2G, the spacing S2, as is indicated inFIG.3. In some implementations, other spacings, such as larger or smaller spacings can be used, where the particular spacing between semiconductor die can depend on the particular FOWLP being produced. Using the process ofFIGS.2A-2N, FOWLPs including the semiconductor die105shown inFIG.3can be concurrently produced, where each FOWLP can include one or more of the semiconductor die105.

It will be understood that, in the foregoing description, when an element, such as a layer, a region, or a substrate, is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it may be directly on, connected or coupled to the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to or directly coupled to another element or layer, there are no intervening elements or layers present. Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements that are shown as being directly on, directly connected or directly coupled can be referred to as such. The claims of the application may be amended to recite exemplary relationships described in the specification or shown in the figures.

As used in this specification, a singular form may, unless definitely indicating a particular case in terms of the context, include a plural form. Spatially relative terms (e.g., over, above, upper, under, beneath, below, lower, and so forth) are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. In some implementations, the relative terms above and below can, respectively, include vertically above and vertically below. In some implementations, the term adjacent can include laterally adjacent to or horizontally adjacent to.

Some implementations may be implemented using various semiconductor processing and/or packaging techniques. Some implementations may be implemented using various types of semiconductor device processing techniques associated with semiconductor substrates including, but not limited to, for example, Silicon (Si), Gallium Arsenide (GaAs), Gallium Nitride (GaN), and/or so forth.

While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the implementations. It should be understood that they have been presented by way of example only, not limitation, and various changes in form and details may be made. Any portion of the apparatus and/or methods described herein may be combined in any combination, except mutually exclusive combinations. The implementations described herein can include various combinations and/or sub-combinations of the functions, components and/or features of the different implementations described.