Patent ID: 12229563

Throughout the drawings, identical reference characters and descriptions indicate similar, but not necessarily identical, elements. While the exemplary implementations described herein are susceptible to various modifications and alternative forms, specific implementations have been shown by way of example in the drawings and will be described in detail herein. However, the exemplary implementations described herein are not intended to be limited to the particular forms disclosed. Rather, the present disclosure covers all modifications, equivalents, and alternatives falling within the scope of the appended claims.

DETAILED DESCRIPTION

As will be described in greater detail below, the instant disclosure describes various systems and methods for managing split registers in a split register list for renaming. To simplify management of registers, a processor may manage physical registers based on a largest supported architectural register size. However, such a scheme may result in physical registers being unused, for instance when supporting instructions of smaller sizes. Thus, in one example, a method for managing split registers for renaming may include detecting that a data unit size for an instruction is smaller than a register and allocating a first portion of the register to the instruction in a manner that leaves a second portion of the register available for allocating to an additional instruction. The method may also include tracking the register as a split register.

In some examples, tracking the register may include marking the register in a split register list. The split register list may track a split register based on one of even or odd address value such that the corresponding second portion has the other of even or odd address value. In some examples, the method may further include unmarking, in the split register list, the register when the first portion and the second portion are free.

In some examples, the method may include selecting the register from a free register list. Free registers may each be tracked in the free register list as a pair of register portions. In addition, the method may include tracking, in a free register portion list, the second portion of the register.

In some examples, the method may include marking the first portion as free when the instruction completes. In some examples, the method may also include allocating the second portion to a second instruction. In some examples, the data unit size may correspond to an instruction width of the instruction. In some examples, a size of the register may correspond to a wide instruction width.

In one example, a method for managing split registers for renaming may include detecting that a data unit size for an instruction is smaller than a register size and selecting, for the instruction from a free register list, a free register having the register size. The method may also include allocating a first portion of the selected register to the instruction in a manner that leaves a second portion of the selected register available for allocating to an additional instruction and tracking the selected register as a split register in a split register list.

In one implementation, a system for managing split registers for renaming may include a physical memory, and at least one physical processor including a plurality of registers and a control circuit for managing allocation of registers for instructions. The control circuit configured to select, for an instruction having a data unit size smaller than a register, a free register of the plurality of registers from a free register list. The control circuit may be further configured to allocate a first portion of the selected register to the instruction in a manner that leaves a second portion of the selected register available for allocating to an additional instruction and track the selected register as a split register in a split register list.

Features from any of the above-mentioned implementations may be used in combination with one another in accordance with the general principles described herein. These and other implementations, features, and advantages will be more fully understood upon reading the following detailed description in conjunction with the accompanying drawings and claims.

The present disclosure is generally directed to splitting registers during a rename phase of a processor's instruction pipeline. As will be explained in greater detail below, the present disclosure provides systems and methods for splitting and tracking registers that may be combinations of physical registers. Rather than tracking individual physical registers, a processor may track the combinations of physical registers (as registers) and split a combination when an instruction does not require combined registers. The processor may track whether a register is a split register using a bit vector to avoid requiring significant changes to the processor's renaming scheme.

For example, implementations of the present disclosure may detect that a data unit size for an instruction is smaller than a register. In response, implementations of the present disclosure may allocate a first portion of the register to the instruction in a manner that leaves a second portion of the register available for allocating to an additional instruction. The register may be tracked as a split register.

Features from any of the implementations described herein may be used in combination with one another in accordance with the general principles described herein. These and other implementations, features, and advantages will be more fully understood upon reading the following detailed description in conjunction with the accompanying drawings and claims.

The following will provide, with reference toFIGS.1-6, detailed descriptions of various implementations of split register renaming. Detailed descriptions of an example system for managing split registers are provided in connection withFIG.1. Detailed descriptions of an example renaming workflow are provided in connection withFIG.2. Detailed descriptions of registers and a split register list are provided in connection withFIGS.3and4. Detailed descriptions of an example method for managing split registers for renaming are provided in connection withFIG.6.

FIG.1is a block diagram of an example system100for managing split registers for renaming. System100may correspond to a computing device, such as a desktop computer, a laptop computer, a server, a tablet device, a mobile device, a smartphone, a wearable device, an augmented reality device, a virtual reality device, a network device, and/or an electronic device. As illustrated inFIG.1, system100may include one or more memory devices, such as memory120. Memory120generally represents any type or form of volatile or non-volatile storage device or medium capable of storing data and/or computer-readable instructions. Examples of memory120include, without limitation, Random Access Memory (RAM), Read Only Memory (ROM), flash memory, Hard Disk Drives (HDDs), Solid-State Drives (SSDs), optical disk drives, caches, variations or combinations of one or more of the same, and/or any other suitable storage memory.

As illustrated inFIG.1, example system100may include one or more physical processors, such as processor110. Processor110generally represents any type or form of hardware-implemented processing unit capable of interpreting and/or executing computer-readable instructions. In some examples, processor110may access and/or modify data and/or instructions stored in memory120. Examples of processor110include, without limitation, microprocessors, microcontrollers, Central Processing Units (CPUs), graphics processing units (GPUs), Field-Programmable Gate Arrays (FPGAs) that implement softcore processors, Application-Specific Integrated Circuits (ASICs), systems on chip (SoCs), portions of one or more of the same, variations or combinations of one or more of the same, and/or any other suitable physical processor.

In some implementations, the term “instruction” may refer to computer code that may be read and executed by a processor. Examples of instructions may include, without limitation, macro-instructions (e.g., program code that may require a processor to decode into processor instructions that the processor may directly execute) and micro-operations (e.g., low-level processor instructions that may be decoded from a macro-instruction and that form parts of the macro-instruction).

As further illustrated inFIG.1, processor110may include a control circuit112, registers130, a register list140, and a split register list150. Control circuit112may correspond to a rename unit or other similar control unit and may include circuitry and/or instructions for allocating and/or assigning registers for instructions. Registers130may correspond to one or more registers of processor110. Register list140may correspond to a free list that may track which of registers130are free (e.g., not in use) and/or which of registers130are not available. Split register list150may correspond to one or more lists that may track which of registers130have been split into register portions.

In some implementations, the term “register” may refer to a fast local storage of a processor that may be used to hold data for operations. Examples of registers may include, without limitation, physical registers (e.g., physical storage units in a processor), logical registers (e.g., registers that may be referenced by instructions and are dynamically mapped to physical registers), and architectural registers (e.g., registers defined by an architecture that may be visible to software and are dynamically mapped to physical registers). In some examples, a register (e.g., a pair register) may refer to more than one physical register. In some examples, a size or number of bits of a physical register may be defined by a processor's hardware architecture.

FIG.2illustrates an exemplary pipeline200for a processor, such as processor110(and/or a functional unit thereof), for executing instructions. During a fetch stage202, processor110may read program instructions from memory120. Processor110may fetch based on an active thread or other criteria. At decode stage204, processor110may decode the read program instructions into micro-operations. Processor110(and/or a functional unit thereof) may forward the newly decoded micro-operations to a scheduler that may queue micro-operations until they are ready for dispatch. At dispatch stage206, the scheduler may dispatch one or more micro-operations that are ready for dispatch. A micro-operation may be ready for dispatch when its dependencies (e.g., resources that may rely on other instructions to finish execution) have been resolved. In some examples, the scheduler may select a ready micro-operation in response to an execution unit of processor110becoming available.

At rename stage208, control circuit112may allocate registers to the dispatched micro-operation as needed. Control circuit112may access one or more of a register file230(which may correspond to and/or represent registers130) a free list240(which may correspond to register list140), and a split register list250(which may correspond to split register list150). Register file230may correspond to an array of registers of processor110.FIG.3illustrates a register file330(which may correspond to register file230).

As illustrated inFIG.3, register file330can include a pair register332, a pair register334, and a pair register336. In some examples, processor110implements an architecture that may support wide instructions that may operate with data unit sizes greater than a register size of a physical register. For instance, a wide instruction or special instruction may operate with a data unit size that is twice the physical register size. The data unit size may correspond to a bit size of data units operated on by the instruction. In some examples, the data unit size also corresponds to an instruction width (e.g., a bit size of an instruction). To support wide instructions, processor110manages registers and physical register pairs such that a pair register size may be twice the physical register size. Thus, as shown inFIG.3, pair register332includes a physical register333A (having an address of “00”) and a physical register333B (having an address of “01”), pair register334includes a physical register335A (having an address of “02”) and a physical register335B (having an address of “03”), and pair register336includes a physical register337A (having an address of “04”) and a physical register337B (having an address of “05”). Although pair registers described herein include a pair of physical registers, in other implementations pair registers may include different numbers of physical registers, such as three, four, etc.

The physical registers for each register may be consecutive such that the register may include two contiguous physical registers, although in other examples the physical registers may not be consecutive. As seen inFIG.3, because each pair register includes a pair of consecutive physical registers, each pair register is associated with an even address value. For example, pair register332has an address of 00 (as address 01 is considered a part of pair register332). Similarly, pair register334has an address of 02 and pair register336has an address of 04. In other implementations, registers may have an odd address value, with the associated second physical register having an even address value.

During rename stage208, processor110may allocate one of pair register332, pair register334, or pair register336based on availability. In other words, processor110may allocate two physical registers to an instruction. However, in some examples, an instruction may have a data unit size and/or instruction width that may be smaller than the pair register size. The instruction may not require two physical registers. The systems and methods described herein allow splitting a pair register into portions that may correspond to physical registers.

FIG.4illustrates a register list440, a split register list450(which may correspond to split register list150and/or split register list250), a derived pair register list460and a derived single register list461(which may correspond to free list240and/or register list140). In some examples, register list440includes a register list442A and a register list442B. Register list442A tracks availability of physical registers corresponding to a first portion of a pair register and register list442B tracks availability of physical registers corresponding to a second portion of the pair register. In some examples, register list442A may track even physical registers (e.g., physical registers having even addresses) and register list442B may track odd physical registers (e.g., physical registers having odd addresses). To avoid using a rename table or other complicated structure, the availabilities of pair registers and single registers are tracked with vectors, including derived pair register list460and derived single register list461.

A size of the various register lists shown inFIG.4can be N/L, where N is maximum or total number of single physical registers available in a processor. In the examples described herein, N is 384 (e.g., 384 physical registers). L corresponds to a number of physical registers that may be combined, such as 2 physical registers combined into a pair register as described herein. L also corresponds to a number of lists and N is a multiple of L. In the examples described herein, L is 2, corresponding to 2 register lists (e.g., register list442A and register list442B), and further corresponding to pair registers including 2 physical registers (e.g., even and odd registers). Each of the lists (e.g., register list442A, register list442B, split register list450, derived pair register list460, and/or derived single register list461) are indexed from [0 . . . N/L−1] and each hold data corresponding to different aspects of the registers. For example, register list442A is implemented as a 192-bit vector (e.g., 384/2) that holds information on even addressable registers, whereas register list442B is implemented as a 192-bit vector that holds information on odd addressable registers. In other examples, L may be a different value. In one particular example, if the physical registers are 128-bit sized registers, it may be desirable to be able to allocate one physical register to a 128-bit uop, two physical registers to a 256-bit uop, and four physical registers to a 512-bit uop, such that L may be 4 in this particular example.

Because pair registers are managed as pairs of physical registers (e.g., L=2), each pair register has an address (e.g., corresponding to a physical register number or PRN) with an even value, as further illustrated inFIG.3. Derived pair register list460corresponds to a free pair list (indicating which pair registers are free) and derived single register list461corresponds to a free single register list (indicating which single registers are free). Derived pair register list460(which is also stored in registers) is a list derived from an AND combination of register list442A and register list442B. Derived single register list461(which is also stored in registers) is a list derived from an XOR combination of register list442A and register list442B.FIG.5illustrates an example simplified circuit500for deriving pair register and single register lists.

FIG.5includes an even list542A, which may correspond to register list442A, an odd list542B, which may correspond to register list442B, a split vector550, which may correspond to split register list150, an AND gate544, an XOR gate546, a pair list560, which may correspond to derived pair register list460, a single list561, which may correspond to derived single register list461, and a rename block582, which may correspond to rename stage208. Each of split vector550, even list542A, and odd list542B has the same size of N/2 (e.g., 384/2=192-bit vector). As each marked bit in even list542A and odd list542B indicates a free portion of a pair register (e.g., a physical register), both the even and odd portions being free indicates a free pair register, whereas only one of the even and odd portions being free indicates a free single register. Thus, pair list560is derived using AND gate544and single list561is derived using XOR gate546. For each index value, AND gate544marks the corresponding bit in pair list560if both even list542A and odd list542B have marked bits. In addition, for each index value, XOR gate546marks the corresponding bit in single list561if a bit in even list542A or odd list542B, but not both bits, are marked.

Returning toFIG.4, derived pair register list460and derived single register list461comprise, in some examples, 192-bit vectors. In the example shown inFIG.4, pair registers (e.g., pairs of portions) are identified by even address values such that derived pair register list460tracks even address values. Thus, a pair register from derived pair register list460has an even address value and includes 2 continuous free portions (e.g., the even address PRN and the following odd address PRN). Derived single register list461also tracks even address values, but may not have Least Significant Bit (LSB) information of the address values. To specifically identify the even or odd portion of a pair register is free, the LSB data can be queried against one of register list442A and/or register list442B to determine the LSB data. For example, register list442B (e.g., odd addresses) is queried to determine the LSB status. For an index marked free in derived single register list461, if the corresponding index in register list442B is free, the LSB data indicates that the odd portion is free. Otherwise, if the corresponding index in register list442B is not free, the LSB data indicates that the even portion is free. As described herein, derived single register list461is derived from an XOR operation. A marked bit also indicates that one portion of the corresponding pair register is not free in register list442A or register list442B.

When new pair registers are being formed (e.g., both portions of a pair register being freed), the corresponding address/bits in register list442A and register list442B are marked and propagated to derived pair register list460. When only one of the address/bits in register list442A and register list442B is set (e.g., only one portion of a pair register is free), the corresponding even address value is set in derived single register list461. Optionally in some examples, to reduce power consumption, new pairs may not be tracked (e.g., updating/deriving derived pair register list460) unless a number of free pairs in derived pair register list460runs low, such as below a threshold number of free pair registers needed for an iteration of rename.

In some examples, split register list450tracks which registers have been split. Split register list450is implemented with a 192-bit vector. For example, as shown inFIG.4, split register list450can track even address physical registers. A marked bit in split register list450for a register (which is indexed based on even address values) indicates that the corresponding pair register is split.

Turning back toFIG.2, in some examples, during rename stage208, control circuit112selects a free pair register (e.g., a physical register pair) for an instruction from derived pair register list460. If the instruction has a data unit width matching the pair register size or instruction has other architectural signals (such as whether the instruction is a special instruction, type of operation, etc.), control circuit112allocates all of the selected pair register (e.g., both portions) to the instruction and indicates that the corresponding entry is not free in derived pair register list460(e.g., by unmarking the corresponding bits in register list442A and register list442B and updating derived pair register list460as described herein).

If the instruction has the data unit width less than the register size and there are no other architectural signals (such as whether the instruction is a special instruction, type of operation, etc.), control circuit112proceeds with allocating only a free portion (e.g., a free single physical register) of the selected pair register to the instruction. If the selected pair register has not already been split, control circuit112allocates the even portion of the selected pair register to the instruction and unmarks the corresponding bit in register list442A. Control circuit112splits the selected pair register (making the odd portion available) by marking the appropriate bit in split register list450(e.g., marking the even address entry as split), and unmarking the appropriate bit in derived pair register list460(e.g., by updating/deriving derived register list460as described herein). Thus, the even portion of the selected pair register is allocated to the instruction and the odd portion is available to be allocated later. In addition, in some examples control circuit112may actively mark the appropriate bit of single free register portions (e.g., in register list442B and updating derived single register list461) as free if the instruction was previously allocated earlier due to architectural signal overrides (such as a register allocated in earlier stages of pipeline) in register list442A and/or register list442B.

If the selected pair register has been previously split (e.g., derived single register list461is providing a free register and/or derived pair register list460was not updated/derived), control circuit112allocates the even address value to the instruction if free, or the corresponding odd address value if free, and accordingly update the entry as not free in register list440(e.g., either register list442A or register list442B as well as in derived single register list461). In some examples, if the instruction has the data unit width less than the register size, control circuit112may first check derived single register list461for a free register portion before selecting and splitting another free pair register.

In some examples, rename stage208may only get certain (e.g., P=6, S=6) selected register lists of either pair registers or single registers. In some examples, rename stage208may pre-emptively update entries in register list440and/or derived pair register list460as not free when a selected register list is transferred to rename stage208, rather than marking entries as free or un-free afterwards. These selected register lists may be designated as not free when given to rename stage208from a free list block. A pair-selected register list of #P may be designated as not free from derived pair register list460. A single selected register list of #S may be designated as not free from derived single register list461, as well as in register list442A or register list442B depending on selected LSB data.

When a physical register is retired or otherwise returned after an instruction completes or due to any other cases (e.g., flushes and more), control circuit112updates the relevant lists (e.g., one or more of register list140, split register list150, free list240, split register list250, split register list450, etc.) accordingly. For example, if the returned physical register has an even address value, control circuit112identifies whether it is a split register (by checking split register list450). If the returned even physical register corresponds to a split register, control circuit112marks the corresponding entry in register list442A as free. If the control circuit112determines that returned even physical register is not a split register marked in split register list450, then control circuit112marks the appropriate entry as free in both register list442A and register list442B for the appropriate address. If the returned physical register has an odd address value, control circuit112marks the corresponding entry as free in register list442B.

In some examples, control circuit112creates/derives a new pair register list and/or a new single register list (e.g., by updating/deriving as described herein) and writes to derived pair register list460and derived single register list461. Control circuit112un-marks the appropriate bits of the newly created pair register in split register list450. In some examples, control circuit112can complement derived pair register list460with a new pair list whereas control circuit112can write all the bits in the bit vector for derived single register list461.

Returning toFIG.2, at issue/execute stage210, processor110and/or an execution unit thereof executes the dispatched micro-operations. AlthoughFIG.2illustrates a basic example pipeline200, in other examples processor110may perform the stages in various orders, repeat iterations, and/or perform stages in parallel.

FIG.6is a flow diagram of an exemplary computer-implemented method600for managing split registers for renaming. The steps shown inFIG.6may be performed by any suitable computer-executable code and/or computing system, including the system illustrated inFIG.1. In one example, each of the steps shown inFIG.6may represent an algorithm whose structure includes and/or is represented by multiple sub-steps, examples of which will be provided in greater detail below.

As illustrated inFIG.6, at step602one or more of the systems described herein may detect that a data unit size for an instruction is smaller than a pair register. For example, control circuit112detects that a data unit size for an instruction is smaller than a pair register that control circuit112has selected.

The systems described herein may perform step602in a variety of ways. As described herein, the data unit size corresponds to an instruction width of the instruction and the size of the pair register may correspond to a wide instruction width (e.g., a physical register pair). In some examples, control circuit112may detect the data unit size from the instruction width or other architectural signals (such as whether the instruction is a special instruction, type of operation, etc.) of the instruction.

As further described herein, free registers are each tracked in the free register list as a pair of register portions or as a single portion free list. For example, register list140tracks free registers as a pair of physical registers. In some examples, derived pair register list460tracks available pair registers and derived single register list461tracks available single registers. In some examples, control circuit112selects a pair register from a free register list (e.g., from register list140, derived pair register list460and/or derived single register list461). Once the selected register is given to a rename block, the corresponding bit of the selected register is marked un-free from derived pair register list460or derived single register list461.

At step604one or more of the systems described herein may allocate a first portion of the pair register to the instruction in a manner that leaves a second portion of the pair register available for allocating to an additional instruction. For example, control circuit112splits, after selecting a free register for the instruction, the selected pair register as described herein to allocate the first portion of the pair register to the instruction in a manner that leaves the second portion of the pair register available for allocating to an additional instruction.

The systems described herein may perform step604in a variety of ways. In one example, control circuit112splits the selected pair register (which has an even address value although in other implementations may have an odd address value) by marking the corresponding entry as split in split register list450. Control circuit112allocates the second portion of the split register to another instruction in this cycle. If it cannot allocate the second portion to another instruction, control circuit112holds the second portion in a register in the rename block. This held register keeps the second portion from returning back to a free list. Control circuit112can also decide, before breaking a pair register, to allocate a previously-held second portion register (e.g., from previous cycles) to an appropriate new instruction (e.g., an instruction which has satisfied the condition that it is not a wide instruction and there are no other architectural signals to override) in this cycle. Control circuit112may proceed to clear the hold register in rename block.

As described above, if the selected register has already been split, control circuit112can allocate the first portion to the instruction. In another iteration, control circuit112can then allocate the second portion to a second instruction as needed.

Returning to method600, at step606one or more of the systems described herein may track the pair register as a split register. For example, control circuit112tracks the pair register as a split register by updating relevant lists (e.g., one or more of register list140, split register list150, free list240, split register list250, split register list450, etc.).

The systems described herein may perform step606in a variety of ways. In one example, tracking the register includes marking the register in a split register list (e.g., split register list250and/or split register list450). The split register list tracks a split register based on one of even or odd address value such that the corresponding second portion has the other of even or odd address value. In some examples, control circuit112further tracks, in a free register portion list (e.g., register list442B and/or derived register list461), the second portion of the register.

In some examples, control circuit112marks the first portion as free (e.g., by updating register list442A) when the instruction completes. In some examples, control circuit112marks the second portion as free (e.g., by updating register list442B) when the corresponding instruction completes. In some examples, control circuit112marks the first and second portion as free (e.g., by updating register list442A and442B which may in some examples further update/derive derived pair register list460and/or derived single register list461) when the corresponding instruction completes. Control circuit112may also unmark, in the split register list (e.g., split register list450), the register when the first portion and the second portion are free to signify that the first and second portions have reformed a pair register.

FIG.7illustrates a simplified top-level view of split register renaming process700as described herein. A flush block772, a rename block774, and a retire block776returns physical register numbers at778for updating free list741(which may correspond to register list440), which may include updating one or more of free register list742A (which may correspond to register list442A), free register list742B (which may correspond to register list442B), split register list750(which may correspond to split register list450), pair list760(which may correspond to derived pair register list460), and single list761(which may correspond to derived single register list461). From updated free list741, additional PRNs (e.g., 6, although in other examples other amounts of PRNs may be used) are read at780for rename block782.

FIG.8illustrates a simplified flow diagram of a return process800, with reference toFIG.7, for example as performed at778. At802, the free list (e.g., free list741) receives the PRNs returned, for instance the addresses returned to be freed. At804, a given address of each PRN is evaluated as even or odd. If odd, which in some examples indicates a single PRN being freed, at808the corresponding bit in free register list742B is marked as free.

If at804the address is even, which in some examples indicates a pair of registers being freed, at806the corresponding bit in free register list742A is marked. At810, the bit in the split vector (e.g., split register list750) is checked whether it was marked as a pair register. If the bit was not marked as a pair register, then at814the process completes the current iteration. If the bit was marked as a pair register, then at812the corresponding bit in free register list742B is marked as free, to indicate that both the even and odd portions of the pair register are free.

In one example of returning a PRN, for instance address 04 corresponding to index 2 as shown inFIG.4with respect to register list442A, register list442A is updated at index 2 to mark PRN 04 as free. Split register list450is checked to determine whether index 2 is split or is a pair register. If split register list450indicates a pair register, register list442B is also updated at index 2 as free, to indicate that the pair register (e.g., both portions) are free. Register list442B may not require updating if the returned PRN was not a pair register. In another example, for instance an odd address such as 01, register list442B is updated at index 0.

FIG.9illustrates a simplified flow diagram of a list updating process900with reference toFIG.7, for example after returning PRNs and in some examples after process800. At902, pair list760is evaluated to determine whether a number of available pair registers is low (e.g., below a threshold number of pair registers for a current iteration), which indicates that pair list760requires updating. If the number of available pair registers is not low, process900completes the current iteration at904.

If the number of pair registers is low at902, process900proceeds to906for updating pair list760and single list761. Free register list742A is combined with free register list742B using an AND operation (see alsoFIG.5) to derive a next pair list. Free register list742A is combined with free register list742B using an XOR operation (see alsoFIG.5) to derive a next XOR list.

At908, the next pair list is written to pair list760for updating, and the next XOR list is written to single list761for updating. In addition, at910, the next pair list is unmarked in split register list750to indicate that the newly derived pairs are not split. Similarly, at912, the next pair list is unmarked in free register list742A and free register list742B.

The bit set in single list761is derived from free register list742A or free register list742B (as a single register) via an XOR operation, in which a resulting bit is marked if the corresponding bit was marked in free register list742A (e.g., even address) or free register list742B (e.g., odd address), but not both. Therefore, the next XOR list (and single list761) is agnostic or otherwise unaware whether it contains even or odd PRN address values. The bits read out from single list761is used to determine all bits of the PRN address value except for LSBs but can further be queried or referenced against free register list742B to determine if the single PRN is odd (indicated by a corresponding marked bit in free register list742B) or even.

In one example of making a pair register, with reference toFIG.4, PRN 04 and PRN 05 are free (in register list442A and register list442B, respectively). If a number of free pairs (e.g., pair free list counter) does not satisfy a threshold number of free pairs, (e.g., is less than or equal to the threshold number of free pairs, such as 24), a new pair is created from available free portions. PRN 04 is free, such that derived pair register list460is accordingly updated (e.g., index 2 may be marked as free). PRN 04 is marked as not free in register list442A (e.g., at index 2), and PRN 05 is marked as not free in register list442B (e.g., at index 2). Split register list450is marked (e.g., at index 2) as a pair, or not-split.

In one example of making a single register available, PRN 04 is free, and PRN 05 is not free. If the pair free list counter does not satisfy the threshold number of free pairs (e.g., is less than or equal to the threshold number of free pairs, which may be 24 for example), a new pair is needed. An XOR operation for PRN 04 and PRN 05 can determine if index 2 corresponds to a single register. Derived single register list461is accordingly updated at index 2 to mark as free. In some examples, if the pair free list counter satisfies the threshold number of free pairs (e.g., the number of free pairs is greater than the threshold number of free pairs), a new pair is not needed.

FIGS.10A-Billustrate simplified flow diagrams of various picking processes with reference toFIG.7.FIG.10Aillustrates a process1000for picking a single PRN. At1002, single list761is provided and/or updated. At1004, single list761is viewed to determine whether single list761has 6 PRNs available (although in other examples, other amounts of PRNs may be requested), and if Stage P0 (e.g., PRN 0) is invalid (e.g., a floating point register is needed). If neither condition is met, at1006the current iteration of process1000ends. Otherwise, at10086 PRNs are read, and at1010written to Stage P0 flops. Using an appropriate scheme or method, Stage P0 is invalidated on Rename Read, and at the same time written to Stage P1 (e.g., PRN 1) flops.

Continuing to1012, free register list742B (e.g., odd address PRNs) is checked to determine if the Stage P0 address is marked. If it is not marked in free register list742B, at1014it is determined that the LSB is 0. Otherwise, at1016, it is determined that the LSB is 1. In addition, at1020the address or PRNs are written to Stage P1 flops on Rename read (e.g., new uops are in the pipeline, rename read is asserted to indicate that PRNs are required for the operation), and given to the rename block.

In one example of selecting a single PRN, with further reference toFIG.4, after picking a single PRN (using, for example a find first N logic), the corresponding entry in derived single register list461is marked as un-free. The address of the picked PRN is checked against register list442B to determine if the address is odd. If the picked PRN is found in register list442B, it is marked as un-free in register list442B and confirmed as odd. If the picked PRN is not found in register list442B, then it is marked as un-free in register list442A and confirmed as even.

For example, for PRN 04 (having index 2 in register list442A), index 2 of derived single register list461may be marked as un-free. If index 2 of register list442B is marked free, then PRN={2, 1′b1}=PRN 05. Otherwise, PRN={2, 1′b0}=PRN 04. For PRN 05, index 2 of register list442B is marked as un-free. For PRN 04, index 2 of register list442A is marked as un-free.

FIG.10Billustrates a process1001for picking a pair register. At1030, pair list760is provided and/or updated. At1032, pair list760is viewed to determine whether pair list760has 6 PRNs available (although in other examples, other amounts of PRNs may be requested) and whether Stage P0 is invalid (e.g., needing a floating point register). If these conditions are not met, at1034the current iteration of process1001ends. Otherwise, continuing to1036, 6 PRNs are read from pair list760for rename. At1038, the addresses are written to Stage P0 flops. Using a scheme or method, Stage P0 is invalidated on Rename Read, at the same time as being written to Stage P1 flops.

Process1001continues to1048to write the addresses or PRNs to Stage P1 flops on Rename Read. Process1001ends its current iteration by giving PRNs to the rename block at1050.

In one example of selecting a pair PRN, with further reference toFIG.4, after picking a pair PRN (using for example, a find first N logic), such as PRN 04 (having index 2 in register list442A), this PRN is marked in derived pair register list460as un-free. The rename stage can then use and/or allocate this pair PRN to a uop.

FIGS.11A-Bis a simplified flow diagram of an example renaming process1100in conjunction with the systems and methods described herein. At1102, two conditions are evaluated: (1) whether the current uop size is less than 512 (e.g., whether the current instruction is less than a wide instruction size), and (2) whether there is no SSE merge (e.g., a merge-type operation for Streaming Single Instruction Multiple Data (SIMD) Extension (SSE), which in some examples correspond to an architectural signal of the instruction that requires a wide instruction-sized register). If any condition evaluates to false, then at1104a pair PRN is allocated. If the uop is determined to be 512 or SSE merge is set, then it will be allocated a pair PRN.

If both conditions are true (which indicates that a wide instruction-sized register is not required), then at1104, the last stored odd single PRN may be evaluated as valid. If the last stored odd single PRN is valid (which indicates that the single PRN is free), then at1106the odd single PRN is allocated, and at1108the stored odd single PRN is marked as invalid (e.g., not free or un-free).

If at1104the last stored odd single PRN is not valid, then at1110, it may be determined whether there is a valid second portion of a pair PRN. If there is a valid second portion of a pair PRN, at1112this second portion is allocated to the current uop.

If at1110there is no valid second portion, then at1114a pair PRN is split to allocate the first portion to the current uop. At1118, it may be determined whether the second portion of the pair PRN (split at1114) will be used by another uop in the current cycle. If the second portion will not be used by another uop this cycle, at1120the second portion is stored in the odd single PRN for a uop in the next cycle (e.g., at the next cycle's iteration of1104). If the second portion will be used by another uop this cycle, at1122this second portion is allocated to the other uop this cycle rather than storing the second portion and avoiding a split of a new pair PRN in the current iteration of process1100.

In addition, after splitting the pair PRN at1114, at1116an update to the split vector (e.g., split register list150, split register list450, split register list750, etc.) is sent to indicate that this pair PRN has been split. Process1100continues with process1101illustrated inFIG.11B. At1124, architecture overrides are checked, such that the uop may already have a PRN and may not need a PRN from the free list (e.g., a PRN allocated to the uop from Load/Store (LS)/Executing (EX) PRN first-in-first-out queue (FIFO) in earlier pipe stages). If there is no architecture override, at1126the PRN allocated by the rename process are used. Otherwise, at1128the PRN allocated by the rename process is returned to the free list and the PRN allocated by the LS or EX FIFO is used instead.

In one example of allocating a PRN during rename, with further reference toFIG.4, PRN 04 may be a pair PRN. For a current uop read from dispatch, if the uop size is less than 512 and there is no SSE merge, then the availability of a stored split PRN is checked during rename. If there is a stored split PRN available and not yet allocated, this stored split PRN is allocated to the current uop. If the stored split PRN is available but allocated to another uop, then the availability of the corresponding second portion (which may have been split this cycle) is checked. If the second portion is available, it is allocated to the current uop. Otherwise, PRN 04 is split, and a first portion thereof allocated to the current uop. After splitting PRN 04, PRN 05 may be allocated to another uop in this cycle or stored to be used at the next cycle. If there is an SSE merge, then the current uop may be an SSE merge operation or otherwise be a 512-sized instruction such that a pair PRN may be allocated. Alternatively, if PRN 04 is a single PRN, and the current uop is not an SSE merge operation (or 512-bit instruction), PRN 04 may be allocated to the current uop.

The systems and methods described herein provide for flexibility in allocating free registers during a rename stage of a processor's instruction pipeline. In one example, a processor architecture may support 512-bit instructions which require 512-bit registers. The processor may have 384 physical registers that are each 256 bits, organized into 192 pairs of physical registers, such that each pair of physical registers satisfies the 512-bit size. To simplify management of registers, the processor may track 512-bit registers as a 256-bit physical register paired with a 256-bit shadow (physical) register for rename and 384-single physical registers to maintain complete list for returned physical register number.

The processor may further support smaller instructions, such as 256-bit instructions, 128-bit instructions, etc. Although 512-bit registers may be used for the smaller instructions, the shadow registers may be unused for the smaller instructions. Making the shadow registers available for use may increase an instructions per cycle performance of the processor. The shadow registers may be used by modifying the renaming scheme to map each physical register in a pair as a high or low logical register number. For example, one 512 uop requiring one 512-bit physical register, may be converted to two 256 uops requiring two 256-bit physical registers. However, such mapping may prohibitively add complexity and overhead to the renaming stage. Such modifications may require effectively doubling queue sizes. For example, the two uops may require tracking Hi and Lo logical register numbers mapped to two physical registers. Thus, rather than one instruction holding in the retire queue, scheduler queue and other queues, two or more instructions may need to be held, effectively reducing processor performance.

The systems and methods described herein may advantageously mitigate the overhead for managing the shadow registers. Rather than managing each physical register individually, the systems and methods described herein may manage physical register pairs (e.g., managing pairs using derived pair register list460and managing 192 single registers using derived single register list461). For example, the processor may manage 192 register pairs. Because a register may be split as needed, normal renaming queues may not require doubling. A split register may be tracked based on its original register pair, with a bit vector for indicating whether a register was split, and another bit vector for indicating whether the split portion is free. In some examples, control circuit112may also allocate free single registers for uops. Thus, the systems and methods described herein may allow using shadow registers and/or all registers efficiently. This scheme can be expanded to allow only allocate appropriate physical registers to appropriate instruction widths without need to double queues, double rename and efficiently use all registers and support wide instructions in a processor.

As detailed above, the computing devices and systems described and/or illustrated herein broadly represent any type or form of computing device or system capable of executing computer-readable instructions, such as those contained within the modules described herein. In their most basic configuration, these computing device(s) may each include at least one memory device and at least one physical processor.

In some examples, the term “memory device” generally refers to any type or form of volatile or non-volatile storage device or medium capable of storing data and/or computer-readable instructions. In one example, a memory device may store, load, and/or maintain one or more of the modules described herein. Examples of memory devices include, without limitation, Random Access Memory (RAM), Read Only Memory (ROM), flash memory, Hard Disk Drives (HDDs), Solid-State Drives (SSDs), optical disk drives, caches, variations or combinations of one or more of the same, or any other suitable storage memory.

In some examples, the term “physical processor” generally refers to any type or form of hardware-implemented processing unit capable of interpreting and/or executing computer-readable instructions. In one example, a physical processor may access and/or modify one or more modules stored in the above-described memory device. Examples of physical processors include, without limitation, microprocessors, microcontrollers, Central Processing Units (CPUs), Field-Programmable Gate Arrays (FPGAs) that implement softcore processors, Application-Specific Integrated Circuits (ASICs), systems on a chip (SOCs), portions of one or more of the same, variations or combinations of one or more of the same, or any other suitable physical processor.

Although illustrated as separate elements, the modules described and/or illustrated herein may represent portions of a single module or application. In addition, in certain implementations one or more of these modules may represent one or more software applications or programs that, when executed by a computing device, may cause the computing device to perform one or more tasks. For example, one or more of the modules described and/or illustrated herein may represent modules stored and configured to run on one or more of the computing devices or systems described and/or illustrated herein. One or more of these modules may also represent all or portions of one or more special-purpose computers configured to perform one or more tasks.

In addition, one or more of the modules described herein may transform data, physical devices, and/or representations of physical devices from one form to another. For example, one or more of the units recited herein may receive instruction data to be transformed, transform the instruction data, output a result of the transformation to determine whether to split a register, use the result of the transformation to split the register, and store the result of the transformation to manage the split register. Additionally or alternatively, one or more of the modules recited herein may transform a processor, volatile memory, non-volatile memory, and/or any other portion of a physical computing device from one form to another by executing on the computing device, storing data on the computing device, and/or otherwise interacting with the computing device.

In some implementations, the term “computer-readable medium” generally refers to any form of device, carrier, or medium capable of storing or carrying computer-readable instructions. Examples of computer-readable media include, without limitation, transmission-type media, such as carrier waves, and non-transitory-type media, such as magnetic-storage media (e.g., hard disk drives, tape drives, and floppy disks), optical-storage media (e.g., Compact Disks (CDs), Digital Video Disks (DVDs), and BLU-RAY disks), electronic-storage media (e.g., solid-state drives and flash media), and other distribution systems.

The process parameters and sequence of the steps described and/or illustrated herein are given by way of example only and can be varied as desired. For example, while the steps illustrated and/or described herein may be shown or discussed in a particular order, these steps do not necessarily need to be performed in the order illustrated or discussed. The various exemplary methods described and/or illustrated herein may also omit one or more of the steps described or illustrated herein or include additional steps in addition to those disclosed.

The preceding description has been provided to enable others skilled in the art to best utilize various aspects of the exemplary implementations disclosed herein. This exemplary description is not intended to be exhaustive or to be limited to any precise form disclosed. Many modifications and variations are possible without departing from the spirit and scope of the present disclosure. The implementations disclosed herein should be considered in all respects illustrative and not restrictive. Reference should be made to the appended claims and their equivalents in determining the scope of the present disclosure.

Unless otherwise noted, the terms “connected to” and “coupled to” (and their derivatives), as used in the specification and claims, are to be construed as permitting both direct and indirect (i.e., via other elements or components) connection. In addition, the terms “a” or “an,” as used in the specification and claims, are to be construed as meaning “at least one of.” Finally, for ease of use, the terms “including” and “having” (and their derivatives), as used in the specification and claims, are interchangeable with and have the same meaning as the word “comprising.”