Patent ID: 12249516

DETAILED DESCRIPTION

The specific structural or functional description disclosed herein is merely illustrative for the purpose of describing embodiments according to the concept of the present disclosure. The embodiments according to the concept of the present disclosure can be implemented in various forms, and cannot be construed as limited to the embodiments set forth herein.

Embodiments provide a manufacturing method of a memory device, which can prevent occurrence of a bridge between adjacent elements.

FIGS.1A to1Care views illustrating a defect which may occur in a manufacturing process of a memory device.

Referring toFIG.1A, a mask pattern110may be formed on the top of an etching target layer100. Although not shown in the drawing, a lower structure, such as a substrate or a peripheral circuit, may be formed below the etching target layer100. The etching target layer100may be an interlayer insulating layer. For example, the etching target layer100may be formed of silicon oxide. In order to form a trench TC or a contact hole in the etching target layer100, the mask pattern110in which an opening is formed in an etching target region may be formed on the top of the etching target layer100. The mask pattern110may be formed of carbon. For example, the mask pattern110may be formed of amorphous carbon. The mask pattern110may include openings that expose portions of the etching target layer100. Although the mask pattern110in which an opening with a line shape is formed has been illustrated inFIG.1A, the opening may be implemented in various shapes, such as a circular shape and a polygonal shape.

When an etching process that uses the mask pattern110as an etching mask is performed, the trench TC may be formed as the etching target layer100that is exposed through the openings of the mask pattern110is etched. The etching process may be performed through a dry etching process by using plasma. The etching process may be performed by using, as an etching gas ETC, a gas with a high etching selectivity with respect to the etching target layer100. For example, when the etching target layer100that is formed of silicon oxide is etched by using the mask pattern110that contains carbon as an etching mask, the etching process may be performed by using the etching gas ETC that contains fluorine. For example, CF4or CHF3gas may be used as the etching gas ETC.

When the etching process, using the etching gas ETC that contains fluorine, is performed, the fluorine that is contained in the etching gas ETC may be ionized by plasma, and fluorine (F) ions may be introduced into the etching target layer100through the mask pattern110. Since the fluorine has a high etching selectivity with respect to the etching target layer100, a defect DF that is caused by the fluorine may occur outside of a region in which the trench TC is formed. For example, when a defect DF occurs in a region in which etching of the etching target layer100is inhibited, a portion of the etching target layer100may be etched due to the defect DF.

Referring toFIG.1B, the defect DF that occurs in the etching target layer100may occur in the etching process that uses the etching gas ETC and may remain after the mask pattern110is removed. A region in which the defect DF occurs may be further removed even in a cleaning process performed after the etching process is performed.

Referring toFIG.1C, when the trench TC is filled with a conductive layer120in a state in which a defect DF occurs in the etching target layer100, the conductive layer120may spill into a region in which the defect DF occurs. Therefore, although a polishing process that allows the conductive layer120to remain only in the trench TC is performed, the conductive layer120, which spills into the region in which the defect DF occurs, may remain and hence a bridge BG may be formed. For example, a bridge BG may be formed between a line that is formed in the trench TC and adjacent lines to be electrically blocked from the line. When the bridge BG is formed between the lines to be electrically blocked from each other, a malfunction may occur in an operation of the memory device, and therefore, the reliability of the memory device may deteriorate.

FIGS.2A to2Dare views illustrating a method of forming a mask in accordance with an embodiment of the present disclosure.

Referring toFIG.2A, a first mask layer210aand a compensation layer220may be formed on the top of an etching target layer200. Although not shown in the drawing, a lower structure such as a substrate or a peripheral circuit may be formed on the bottom of the etching target layer200.

The etching target layer200may be formed of an insulating material. For example, the etching target layer200may be formed of oxide or silicon oxide. The first mask layer210amay be formed on the top of the etching target layer200, and the compensation layer220may be formed on the top of the first mask layer210a. The first mask layer210amay be used as a mask pattern in an etching process of the etching target layer200and may be formed of carbon. For example, the first mask layer210amay be formed of amorphous carbon.

The compensation layer220may be formed to prevent a defect that occurs in the etching target layer200during the etching process. For example, the compensation layer220may be formed to prevent a bridge from forming, which may occur in the etching target layer200due to the first mask layer210a. To this end, the compensation layer220may be formed of a material that is easily chemically bonded to the first mask layer210a. When the first mask layer210ais formed of a material that contains carbon (C), the compensation layer220may be formed of a material that includes hydrogen (H), which is easily ion-bonded to carbon (C). For example, the compensation layer220may be formed to be a layer with a high density of hydrogen (H).

Referring toFIG.2B, a second mask layer210b, a barrier layer240, and a photoresist pattern250may be sequentially formed on the top of the compensation layer220. The barrier layer240may be formed of silicon oxide. The second mask layer210bmay be formed on the top of the compensation layer220, the barrier layer240may be formed on the top of the second mask layer210b, and the photoresist pattern250may be formed on the top of the barrier layer240. The first mask layer210a, the compensation layer220, and the second mask layer210bmay be used as a mask pattern MP.

The photoresist pattern250and the barrier layer240may be used as a pattern used in a process of patterning the second mask layer210b, the compensation layer220, and the first mask layer210a, and the first mask layer210a, the compensation layer220, and the second mask layer210bmay be used as the mask pattern MP used in a process of etching the etching target layer. Therefore, a layers or a pattern, which may be formed on the top of the mask pattern MP, is not limited to the barrier layer240and the photoresist pattern250, and various layers or patterns may be formed.

The first mask layer210a, the compensation layer220, and the second mask layer210b, which are included in the mask pattern MP, may be formed by using an in-situ method of changing a gas in the same chamber or be formed by using an ex-situ method that uses different gases in different chambers.

Referring toFIG.2C, the barrier layer240, the second mask layer210b, the compensation layer220, and the first mask layer210a, which are exposed through an opening of the photoresist pattern250, are sequentially etched through an etching process, and therefore, openings OP that expose portions of the etching target layer200may be formed.

Referring toFIG.2D, an etching process for etching a portion of the etching target layer200exposed through the opening of the mask pattern MP may be performed. The etching process may be performed through a dry etching process by using plasma.

The etching process may be performed by using an etching gas ETC with an etching selectivity with respect to the etching target layer200, which is higher than that of the mask pattern MP. For example, the etching process may be performed by using, as the etching gas ETC, a fluorine gas or a gas that contains fluorine. For example, CF4or CHF3gas may be used as the etching gas ETC.

Both the photoresist pattern (250shown inFIG.2C) and the barrier layer (240shown inFIG.2C), which are formed on the top of the mask pattern MP, may be removed while the etching process is performed. Therefore, a top surface of the mask pattern MP may be exposed by the etching process that uses the etching gas ETC. Although an etching speed of the etching target layer200is faster than that of the mask pattern MP, the mask pattern MP may also be etched little by little while the etching process is performed.

When the etching process is performed, the fluorine that is contained in the etching gas ETC may be ionized into fluorine (F) ions due to the plasma, and the fluorine (F) ions may infiltrate into the second mask layer210bincluded in the mask pattern MP.

In this embodiment, since the compensation layer220is located between the first and second mask layers210aand210b, chemical bonding of impurities may occur between the compensation layer220and the first and second mask layers210aand210b. For example, covalent bonding in which a hydrogen (H) atom and a carbon (C) atom share an electron pair with each other may occur between the compensation layer220and the first and second mask layers210aand210b, and ionic bonding in which fluorine (F) ions and hydrogen (H) ions are bonded to each other may occur between the compensation layer220and the first and second mask layers210aand210b. Due to the covalent bonding of hydrogen (H) and carbon (C), a compensation crystal structure300may be formed in a boundary region between the compensation layer220and the first and second mask layers210aand210bor in a first mask layer210a. The compensation crystal structure300is a crystal structure formed due to the covalent bonding of hydrogen (H) and carbon (C), and may function to increase densities of the compensation layer220and the first mask layer210a. Thus, although fluorine ions F infiltrate into the mask pattern MP in the etching process, the infiltration can be suppressed by the compensation crystal structure300. Accordingly, the number of fluorine ions F infiltrating into the first mask layer210acan be decreased, and a defect which may occur in the etching target layer200due to the etching gas ETC can be reduced.

Also, in order to further suppress the infiltration of the fluorine ions F, the first and second mask layers210aand210bmay be formed at a temperature higher than a normal temperature. When assuming that the normal temperature at which the first and second mask layers210aand210bare formed is a reference temperature, the densities of the first and second mask layers210aand210bmay be increased when the first and second mask layers210aand210bare formed under the condition of a temperature higher than the reference temperature. When the densities of the first and second mask layers210aand210bare increased, the number and infiltration speed of the fluorine ions F can be further decreased, and thus the probability that a defect will occur in an etching process for forming a trench TR can be lowered.

FIG.3is a view illustrating a structural formula in which ions of a mask and a compensation layer are bonded to each other.

Referring toFIGS.3and2D, carbon (C) ions of the first mask layer210aand hydrogen (H) ions of the compensation layer220may be bonded to each other in various structures. For example, the compensation crystal structure300of carbon (C) and hydrogen (H) may be generated as a structure of at least one of CH, CH2, HC, and H2C.

FIG.4is a view illustrating a method of forming a mask in accordance with another embodiment of the present disclosure.

Referring toFIG.4, a plurality of mask layers210ato210gand a plurality of compensation layers220ato220fmay be alternately stacked on the top of an etching target layer200. For example, after a first mask layer210ais formed on the top of the etching target layer200, a first compensation layer220amay be formed on the top of the first mask layer210a. A second mask layer210bmay be formed on the top of the first compensation layer220a, and a second compensation layer220bmay be formed on the top of the second mask layer210b. In this manner, the plurality of compensation layers220ato220fmay be alternately disposed between the plurality of mask layers210ato210g. The number of first to seventh mask layers210ato210gand first to sixth compensation layers220ato220f, which are alternately stacked, is not limited to what is shown in the drawing.

When the plurality of mask layers210ato210gand the plurality of compensation layers220ato220fare included in a mask pattern MP, the number of fluorine ions F that infiltrate downwardly can be decreased by the compensation crystal structure (300shown inFIG.3), even when the fluorine ions F infiltrate downwardly while piercing the compensation crystal structure300from the top of the mask pattern MP. Accordingly, a phenomenon can be prevented, the phenomenon being a defect that occurs as the fluorine ions F infiltrate even into the etching target layer200.

The above-described embodiment may be used in various etching processes for forming trenches or contact holes, which are adjacent to each other, during a manufacturing process of the memory device. In an example, a manufacturing process of forming contact plugs in a memory cell array will be described as follows.

FIGS.5A to5Fare views illustrating a manufacturing method of a memory device in accordance with an embodiment of the present disclosure.

Referring toFIG.5A, first to third mask layers520ato520cand first and second compensation layers530aand530b, which are used as a mask pattern MP, may be alternately stacked on the top of a first interlayer insulating layer500. A barrier layer540and a photoresist pattern550may be sequentially stacked on the top of the mask pattern MP. Although not shown in the drawing, a lower structure, such as a substrate or a peripheral circuit, may be formed below the first insulating layer500as an etching target layer.

The first interlayer insulating layer500may be formed of silicon oxide. A plurality of gate lines510that are used as word lines may be formed in the first interlayer insulating layer500. The gate lines510may be stacked to be spaced apart from each other in a vertical direction from the substrate and may be formed in a stepped shape. The gate lines510may be formed of a conductive material and may be formed of, for example, tungsten.

The first to third mask layers520ato520cmay be formed of carbon. For example, the first to third mask layers520ato520cmay be formed of amorphous carbon.

The first and second compensation layers530aand530bthat prevent the formation of a bridge in the first interlayer insulating layer500in a subsequent etching process may be formed between the first to third mask layers520ato520c. The first and second compensation layers530aand530bmay be formed of a material that contains hydrogen (H) that is easily chemically bonded to carbon (C) that is contained in the first to third mask layers520ato520c. For example, the first and second compensation layers530aand530bmay be a hard mask layer with a high density of the hydrogen (H).

The photoresist pattern550and the barrier layer540may be used as an etching mask pattern in a process of patterning the first to third mask layers520ato520cand the first and second compensation layers530aand530b. The barrier layer540may be formed of silicon oxide. The photoresist pattern550may include openings OP that expose portions of the barrier layer540.

Referring toFIG.5B, a first etching process for forming openings OP in the barrier layer540, the first to third mask layers520ato520c, and the first and second compensation layers530aand530bmay be performed. The first etching process may be a dry etching process and may be performed by using a first etching gas 1ETC. For example, the first etching gas 1ETC may include a gas with an etching selectivity with respect to the barrier layer540, the first to third mask layers520ato520c, and the first and second compensation layers530aand530b, which is higher than that of the photoresist pattern550. The first etching process may be performed until the first interlayer insulating layer500is exposed through the openings OP of the mask pattern MP.

Referring toFIG.5C, when the first interlayer insulating layer500is exposed through the openings OP of the mask pattern MP, a second etching process for forming contact holes Hc in the first interlayer insulating layer500that are exposed through the openings OP may be performed. The second etching process may be performed through a dry etching process. For example, the second etching process may be performed by using a second etching gas 2ETC with an etching selectivity with respect to the first interlayer insulating layer500, which is higher than that of the mask pattern MP. The second etching gas 2ETC may include a gas that contains fluorine. For example, CF4or CHF3gas may be used as the second etching gas 2ETC.

Since plasma is used in the dry etching process, fluorine ions that are ionized by the plasma in the second etching gas 2ETC may be introduced into the mask pattern MP. Atoms of the first to third mask layers520ato520cand the first and second compensation layers530aand530b, which are included in the mask pattern MP, may be chemically bonded to each other, thereby generating a compensation crystal structure. The fluorine ions might not infiltrate into the first interlayer insulating layer500due to the compensation crystal structure. Thus, a defect that is caused by the fluorine ions in a boundary region BR in which the first interlayer insulating layer500and the first mask layer520aare in contact with each other can be prevented. The second etching process may be performed until the gate lines510are exposed through the contact holes Hc.

Referring toFIG.5D, a cleaning process for removing the mask pattern (MP shown inFIG.5C) may be performed. The cleaning process may be performed as a wet etching process and may be performed by using an etchant with an etching selectivity with respect to the mask pattern MP, which is higher than those of the first interlayer insulating layer500and the gate lines510.

Referring toFIG.5E, a conductive layer560may be formed on the entire structure to fill the contact holes Hc. The conductive layer560may be formed of poly-silicon or tungsten. In order to completely fill the contact holes Hc, the conductive layer560may be formed such that the top of the first interlayer insulating layer500is entirely covered by the conductive layer560.

Referring toFIG.5F, a polishing process may be performed to allow the conductive layers560that fill the contact holes Hc to be electrically isolated from each other. The polishing process may be a chemical mechanical polishing process and may be performed until the top of the first interlayer insulating layer500is exposed. Since a bridge is not formed in the first interlayer insulating layer500, exposed in the boundary region BR, contact plugs CP that are formed in different contact holes Hc may be electrically isolated from each other.

In the drawings described with reference toFIGS.5A to5F, the manufacturing method of the contact plugs CP that are formed in a memory cell array has been illustrated as an embodiment. However, a manufacturing method of a hard mask that uses a compensation layer may be applied in manufacturing processes of forming trenches or channels, which are adjacent to each other, in addition to the contact plugs CP.

FIGS.6A to6Fare views illustrating a manufacturing method of a memory device in accordance with another embodiment of the present disclosure.

Referring toFIG.6A, vertical channel layers VCH may be formed in a stack structure in which a first interlayer insulating layer500and gate lines510are alternately stacked. The gate lines510may be formed of a conductive material. For example, the gate lines510may be formed of, for example, tungsten. Although not shown in the drawing, a lower structure, such as a substrate or a peripheral circuit, may be formed below the vertical channel layers VCH. The vertical channel layers VCH may include memory layers, constituting a memory cell. A second interlayer insulating layer611and bit lines612may be formed on the entire structure that includes the vertical channel layers VCH. The second interlayer insulating layer611may be formed of oxide or silicon oxide, and the bit lines612may be formed of a conductive material. The bit lines612may be formed on the top of the vertical channel layers VCH. A third interlayer insulating layer613may be formed on the top of the second interlayer insulating layer611and the bit lines612. The third interlayer insulating layer613may be formed of silicon oxide.

First to third mask layers620ato620cand first and second compensation layers630aand630b, which are used as a mask pattern MP, may be alternately stacked on the top of the third interlayer insulating layer613. A barrier layer640and a photoresist pattern650may be sequentially stacked on the top of the mask pattern MR The mask pattern MP may be formed of the same material as the mask pattern MP shown inFIG.5A. For example, the first to third mask layers620ato620cmay be formed of amorphous carbon.

The first and second compensation layers630aand630bthat prevent the formation of a bridge in the third interlayer insulating layer613in a subsequent etching process may be formed between the first to third mask layers620ato620c. The first and second compensation layers630aand630bmay be formed of a material that contains hydrogen (H) that is easily chemically boded to carbon (C) that is contained in the first to third mask layers620ato620c. For example, the first and second compensation layers630aand630bmay be a hard mask layer with a high density of the hydrogen (H).

The photoresist pattern650and the barrier layer640may be used as an etching mask pattern in a process of patterning the first to third mask layers620ato620cand the first and second compensation layers630aand630b. The barrier layer640may be formed of a silicon oxide. The photoresist pattern650may include openings OP that expose portions of the barrier layer640.

Referring toFIG.6B, a first etching process for forming openings OP in the barrier layer640, the first to third mask layers620ato620c, and the first and second compensation layers630aand630bmay be performed. The first etching process may be a dry etching process, and may be performed by using a first etching gas 1ETC. For example, the first etching gas 1ETC may include a gas with an etching selectivity with respect to in the barrier layer640, the first to third mask layers620ato620c, and the first and second compensation layers630aand630b, which is higher than that of the photoresist pattern650. The first etching process may be performed until the third interlayer insulating layer613is exposed through the openings OP of the mask pattern MP.

Referring toFIG.6C, when the third interlayer insulating layer613is exposed through the openings OP of the mask pattern MP, a second etching process for forming via holes Hv in the third interlayer insulating layer613that is exposed through the openings OP may be performed. The second etching process may be performed through a dry etching process. For example, the second etching process may be performed by using a second etching gas 2ETC with an etching selectivity with respect to the third interlayer insulating layer613, which is higher than that of the mask pattern MP. The second etching gas 2ETC may include a gas that contains fluorine. For example, CF4or CHF3gas may be used as the second etching gas 2ETC.

Since plasma is used in the dry etching process, fluorine ions that are ionized by the plasma in the second etching gas 2ETC may be introduced into the mask pattern MR Atoms of the first to third mask layers620ato620cand the first and second compensation layers630aand630b, which are included in the mask pattern MP, may be chemically bonded to each other, thereby generating a compensation crystal structure. The fluorine ions might not infiltrate into the third interlayer insulating layer613due to the compensation crystal structure. Thus, a defect that is caused by the fluorine ions in a boundary region BR in which the third interlayer insulating layer613and the first mask layer620aare in contact with each other can be prevented. The second etching process may be performed until the bit lines612are exposed through the via holes Hv.

Referring toFIG.6D, a cleaning process for removing the mask pattern (MP shown inFIG.6C) may be performed. The cleaning process may be performed as a wet etching process and may be performed by using an etchant with an etching selectivity with respect to the mask pattern MP, which is higher than those of the third interlayer insulating layer613and the bit lines612.

Referring toFIG.6E, a conductive layer660may be formed on the entire structure to fill the via holes Hv. The conductive layer660may be formed of poly-silicon or tungsten. In order to completely fill the via holes Hv, the conductive layer660may be formed such that the top of the third interlayer insulating layer613is entirely covered by the conductive layer660.

Referring toFIG.6F, a polishing process may be performed to allow the conductive layers660that fill the via holes Hv to be electrically isolated from each other. The polishing process may be a chemical mechanical polishing process and may be performed until the top of the third interlayer insulating layer613is exposed. Since a bridge is not formed in the third interlayer insulating layer613, exposed in the boundary region BR, contact plugs660cthat are formed in different via holes Hv may be electrically isolated from each other.

FIG.7is a block diagram illustrating a memory card system to which the manufactured memory device is applied in accordance with an embodiment of the present disclosure.

Referring toFIG.7, the memory card system3000may include a controller3100, a memory device3200, and a connector3300.

The controller3100may be connected to the memory device3200. The controller3100may access the memory device3200. For example, the controller3100may control a program, read, or erase operation, or may control a background operation of the memory device3200. The controller3100may provide an interface between the memory device3200and a host. The controller3100may drive firmware for controlling the memory device3200. To this end, the controller3100may include components, such as a Random Access Memory (RAM), a processing unit, a host interface, a memory interface, and an error corrector.

The controller3100may communicate with an external device through the connector3300. The controller3100may communicate with the external device (e.g., the host) according to a specific communication protocol. Exemplarily, the controller3100may communicate with the external device through at least one of various communication protocols, such as a Universal Serial Bus (USB), a Multi-Media Card (MMC), an embedded MMC (eMMC), a Peripheral Component Interconnection (PCI), a PCI express (PCIe), an Advanced Technology Attachment (ATA), a Serial-ATA (SATA), a Parallel-ATA (PATA), a Small Computer System Interface (SCSI), an Enhanced Small Disk Interface (ESDI), an Integrated Drive Electronics (IDE), firewire, a Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector3300may be defined by at least one of the above-described various communication protocols.

The memory device3200may be manufactured in accordance with the above-described embodiment of the present disclosure, and be implemented with various nonvolatile memory devices, such as an Electrically Erasable and Programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a Phase-change RAM (PRAM), a Resistive RAM (ReRAM), a Ferroelectric RAM (FRAM), and a Spin Torque Transfer magnetic RAM (STT-MRAM).

The controller3100and the memory device3200may be integrated into a single semiconductor device, to constitute a memory card. For example, the controller3100and the memory device3200may constitute a memory card, such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash (CF) card, a Smart Media Card (SM and SMC), a memory stick, a Multi-Media Card (MMC, RS-MMC, MMCmicro and eMMC), an SD card (SD, miniSD, microSD and SDHC), and a Universal Flash Storage (UFS).

FIG.8is a block diagram illustrating a Solid State Drive (SDD) to which the manufactured memory device is applied in accordance with an embodiment of the present disclosure.

Referring toFIG.8, the SSD system4000may include a host4100and an SSD4200. The SSD4200may exchange a signal SIG with the host4100through a signal connector4001, and receives power PWR through a power connector4002. The SSD4200may include a controller4210, a plurality of flash memories4221to422n, an auxiliary power supply4230, and a buffer memory4240.

The controller4210may control the plurality of flash memories4221to422nin response to a signal that is received from the host4100. Exemplarily, the signal may be a signal based on an interface between the host4100and the SSD4200. For example, the signal may be a signal that is defined by at least one of interfaces, such as a Universal Serial Bus (USB), a Multi-Media Card (MMC), an embedded MMC (eMMC), a Peripheral Component Interconnection (PCI), a PCI express (PCIe), an Advanced Technology Attachment (ATA), a Serial-ATA (SATA), a Parallel-ATA (PATA), a Small Computer System Interface (SCSI), an Enhanced Small Disk Interface (ESDI), an Integrated Drive Electronics (IDE), a firewire, a Universal Flash Storage (UFS), a WI-FI, a Bluetooth, and an NVMe.

The auxiliary power supply4230may be connected to the host4100through the power connector4002. The auxiliary power supply4230may receive power PWR that is input from the host4100and charge the power PWR. When the supply of power from the host4100is not smooth, the auxiliary power supply4230may provide power for the SSD4200. Exemplarily, the auxiliary power supply4230may be located in the SSD4200or located outside of the SSD4200. For example, the auxiliary power supply4230may be located on a main board and may provide auxiliary power to the SSD4200.

The buffer memory4240may operate as a buffer memory of the SSD4200. For example, the buffer memory4240may temporarily store data that is received from the host4100or data that is received from the plurality of flash memories4221to422n, or temporarily store meta data (e.g., a mapping table) of the flash memories4221to422n. The buffer memory4240may include volatile memories, such as a DRAM, an SDRAM, a DDR SDRAM, an LPDDR SDRAM, and a GRAM or nonvolatile memories such as a FRAM, a ReRAM, an STT-MRAM, and a PRAM.

The mask pattern, in accordance with the above-described embodiment of the present disclosure, may be used in processes of manufacturing the buffer memory4240and the plurality of flash memories4221to422n.

In accordance with the present disclosure, a defect which may occur in a hole or a trench in an etching process that uses a mask pattern can be reduced and prevented. Accordingly, occurrence of a bridge between adjacent elements can be prevented.

While the present disclosure has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-described exemplary embodiments but should be determined by not only the appended claims but also the equivalents thereof.

In the above-described embodiments, all steps may be selectively performed or part of the steps and may be omitted. In each embodiment, the steps are not necessarily performed in accordance with the described order and may be rearranged. The embodiments disclosed in this specification and drawings are only examples to facilitate an understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it should be apparent to those skilled in the art that various modifications can be made on the basis of the technological scope of the present disclosure.

Meanwhile, the exemplary embodiments of the present disclosure have been described in the drawings and specification. Although specific terminologies are used here, those are only to explain the embodiments of the present disclosure. Therefore, the present disclosure is not restricted to the above-described embodiments and many variations are possible within the spirit and scope of the present disclosure. It should be apparent to those skilled in the art that various modifications can be made on the basis of the technological scope of the present disclosure in addition to the embodiments disclosed herein.