Patent ID: 12219702

DETAILED DESCRIPTION

Exemplary aspects (embodiments) to embody the present disclosure are described below in greater detail with reference to the accompanying drawings. The contents described in the embodiments below are not intended to limit the present disclosure. Components described below include components easily conceivable by those skilled in the art and components substantially identical therewith. Furthermore, the components described below may be appropriately combined. What is disclosed herein is given by way of example only, and appropriate modifications made without departing from the spirit of the present disclosure and easily conceivable by those skilled in the art naturally fall within the scope of the present disclosure. To simplify the explanation, the drawings may possibly illustrate the width, the thickness, the shape, and other elements of each unit more schematically than the actual aspect. These elements, however, are given by way of example only and are not intended to limit interpretation of the present disclosure. In the present specification and the drawings, components similar to those previously described with reference to previous drawings are denoted by like reference numerals, and detailed explanation thereof may be appropriately omitted.

First Embodiment

FIG.1is a plan view schematically illustrating a display device according to a first embodiment. As illustrated inFIG.1, a display device1includes an array substrate2, a plurality of pixels Pix, drive circuits12, a drive integrated circuit (IC)200, and cathode wiring26. The array substrate2is a wiring substrate for driving the pixels Pix. The array substrate2is also called a backplane or an active matrix substrate. The wiring substrate according to the present disclosure is not limited to the array substrate2. The array substrate2includes a substrate21, first transistors Tr1, second transistors Tr2, transistors TrG (refer toFIG.4), and various kinds of wiring, for example. The first transistor Tr1, the second transistor Tr2, and the like are switching elements provided to each pixel Pix. The transistor TrG is a switching element included in the drive circuits12.

As illustrated inFIG.1, the display device1has a display region AA and a peripheral region GA. The display region AA is positioned overlapping the pixels Pix and displays an image. The peripheral region GA does not overlap the pixels Pix and is positioned outside the display region AA.

The pixels Pix are arrayed in a first direction Dx and a second direction Dy in the display region AA of the substrate21. The first direction Dx and the second direction Dy are parallel to the surface of the substrate21. The direction parallel to the plane including the first direction Dx and the second direction Dy may be referred to as a planar direction. The first direction Dx is orthogonal to the second direction Dy. Therefore, the second direction Dy may be referred to as an orthogonal direction. The first direction Dx may intersect the second direction Dy without being orthogonal thereto. A third direction Dz is orthogonal to the first direction Dx and the second direction Dy and may be referred to as a stacking direction.

The drive circuit12is a circuit that drives a plurality of gate lines based on various control signals from the drive IC200. The gate lines include a first gate line GCL1and a second gate line GCL2illustrated inFIG.2. The drive circuits12sequentially or simultaneously select a plurality of gate lines and supply gate drive signals to the selected gate lines. Thus, the drive circuits12select the pixels Pix coupled to the gate lines.

The drive IC200is a circuit that controls display on the display device1. The drive IC200is mounted on the peripheral region GA of the substrate21as chip on glass (COG). The configuration is not limited thereto, and the drive IC200may be mounted on a flexible printed circuit board or a rigid circuit board coupled to the peripheral region GA of the substrate21as chip on film (COF).

The cathode wiring26is provided in the peripheral region GA of the substrate21. The cathode wiring26is provided surrounding the pixels Pix in the display region AA and the drive circuits12in the peripheral region GA. Cathodes of a plurality of light-emitting elements3are coupled to the common cathode wiring26and are supplied with a ground potential, for example.

Each pixel Pix includes a light-emitting element3. The light-emitting elements3are provided corresponding to the respective pixels Pix and include a first light-emitting element3R, a second light-emitting element3G, and a third light-emitting element3B that output light in different colors. The first light-emitting element3R outputs red light. The second light-emitting element3G outputs green light. The third light-emitting element3B outputs blue light. In the following explanation, the first light-emitting element3R, the second light-emitting element3G, and the third light-emitting element3B are simply referred to as the light-emitting elements3when they need not be distinguished from one another. The pixels Pix may include four or more light-emitting elements3and output different light in four or more colors.

In the array of the pixels Pix, the pixel Pix including the first light-emitting element3R, the pixel Pix including the second light-emitting element3G, and the pixel Pix including the third light-emitting element3B are repeatedly arrayed in this order in the first direction Dx. In other words, the first light-emitting element3R, the second light-emitting element3G, and the third light-emitting element3B are repeatedly arrayed in this order in the first direction Dx. The first light-emitting elements3R, the second light-emitting elements3G, and the third light-emitting elements3B are each arrayed in the second direction Dy.

The light-emitting element3is an inorganic light-emitting diode (LED) chip having a size of approximately 3 μm to 300 μm in planar view and is called a micro-LED. A display device including micro-LEDs in the respective pixels is also called a micro-LED display device. The term “micro” of the micro-LED is not intended to limit the size of the inorganic light-emitting diode. The light-emitting element3may be a mini-LED.

FIG.2is a circuit diagram of a pixel circuit of the display device. A pixel circuit28is a drive circuit that drives the light-emitting element3. As illustrated inFIG.2, the pixel circuit28includes a plurality of switching elements (the first transistor Tr1, the second transistor Tr2, a third transistor Tr3, and a fourth transistor Tr4), the first gate line GCL1, the second gate line GCL2, a signal line SGL, and a power supply line LVdd. Each transistor is a thin-film transistor (TFT).

The first transistor Tr1is a TFT for driving. The second transistor Tr2is a TFT for switching between an emitting period and a non-emitting period. The third transistor Tr3and the fourth transistor Tr4are TFTs for switching an electric current. The signal line SGL is coupled to a constant current source. The power supply line LVdd is coupled to a constant voltage source.

Holding capacitance CS1is formed between the drain of the second transistor Tr2and the anode of the light-emitting element3. Holding capacitance CS2is formed between the anode of the light-emitting element3and the power supply line LVdd. With the holding capacitance CS1and the holding capacitance CS2, the pixel circuit28suppresses fluctuations in the gate voltage due to parasitic capacitance and leakage current in the second transistor Tr2.

In the non-emitting period, the drive circuits12(refer toFIG.1) set the electric potential of the first gate line GCL1at a high level and set the electric potential of the second gate line GCL2at a low level. As a result, the second transistor Tr2and the third transistor Tr3are turned on, and the fourth transistor Tr4is turned off. The anode of the light-emitting element3is supplied with an electric current Idata from the signal line SGL.

In the emitting period, the drive circuits12(refer toFIG.1) set the electric potential of the first gate line GCL1at a low level and set the electric potential of the second gate line GCL2at a high level. As a result, the second transistor Tr2and the third transistor Tr3are turned off, and the fourth transistor Tr4is turned on. The anode of the light-emitting element3is supplied with an electric current Id from the constant power supply line LVdd. The configuration illustrated inFIG.2is given by way of example only, and the configuration of the pixel circuit28and the operation of the display device1can be appropriately modified.

FIG.3is a sectional view along line III-III′ ofFIG.1. As illustrated inFIG.3, the light-emitting element3is provided on the array substrate2. The array substrate2includes the substrate21, switching elements, such as the first transistor Tr1and the second transistor Tr2, various kinds of wiring, and various kinds of insulating films. In the peripheral region GA of the substrate21, the transistor TrG included in the drive circuits12is provided as a plurality of transistors. The substrate21is an insulating substrate and is a glass substrate, a resin substrate, or a resin film, for example.

In the present specification, a direction from the substrate21toward an upper surface27aof a planarization film27in a direction perpendicular to the surface of the substrate21is referred to as an “upper side”. A direction from the upper surface27aof the planarization film27toward the substrate21is referred to as a “lower side”. The term “plan view” indicates a view seen from a direction perpendicular to the surface of the substrate21.

The first transistor Tr1, the second transistor Tr2, and the transistor TrG are provided on one surface of the substrate21. The first transistor Tr1includes a semiconductor61, a source electrode62, a drain electrode63, a first gate electrode64A, and a second gate electrode64B. The first gate electrode64A is provided on the substrate21with a first insulating film91interposed therebetween. Insulating films, such as the first insulating film91, are made of inorganic insulating material, such as a silicon oxide film (SiO), a silicon nitride film (SiN), and a silicon oxynitride film (SiON). Each inorganic insulating film is not limited to a single layer and may be a multilayered film.

A second insulating film92is provided on the first insulating film91to cover the first gate electrode64A. The semiconductor61is provided on the second insulating film92. A third insulating film93is provided on the second insulating film92to cover the semiconductor61. The second gate electrode64B is provided on the third insulating film93. The semiconductor61is provided between the first gate electrode64A and the second gate electrode64B in the third direction Dz. In the semiconductor61, a channel region is formed at a part sandwiched between the first gate electrode64A and the second gate electrode64B.

In the example illustrated inFIG.3, the first transistor Tr1has what is called a dual-gate structure. The first transistor Tr1, however, may have a bottom-gate structure provided not with the second gate electrode64B but with the first gate electrode64A alone or a top-gate structure provided not with the first gate electrode64A but with the second gate electrode64B alone.

The semiconductor61is made of amorphous silicon, microcrystalline oxide semiconductor, amorphous oxide semiconductor, polycrystalline silicon, low-temperature polycrystalline silicon (LTPS), or gallium nitride (GaN), for example. Examples of the oxide semiconductor include, but are not limited to, IGZO, zinc oxide (ZnO), ITZO, etc. IGZO is indium gallium zinc oxide. ITZO is indium tin zinc oxide.

A fourth insulating film94is provided on the third insulating film93to cover the second gate electrode64B. The source electrode62and the drain electrode63are provided on the fourth insulating film94. In the configuration according to the present embodiment, the source electrode62is electrically coupled to the semiconductor61through a contact hole H5. The drain electrode63is electrically coupled to the semiconductor61through a contact hole H3.

A fifth insulating film95is provided on the fourth insulating film94to cover the source electrode62and the drain electrode63. The fifth insulating film95is a planarization film that planarizes recesses and protrusions formed by the first transistor Tr1and various kinds of wiring.

The second transistor Tr2includes a semiconductor65, a source electrode66, a drain electrode67, a first gate electrode68A, and a second gate electrode68B. The second transistor Tr2has a layer structure similar to that of the first transistor Tr1, and detailed description thereof is omitted. The drain electrode67of the second transistor Tr2is electrically coupled to coupling wiring69through a contact hole H8. The coupling wiring69is coupled to the first gate electrode64A and the second gate electrode64B of the first transistor Tr1.

While the semiconductor65, the source electrode66, the drain electrode67, the first gate electrode68A, and the second gate electrode68B are provided in the same layers as those of the semiconductor61, the source electrode62, the drain electrode63, the first gate electrode64A, and the second gate electrode64B of the first transistor Tr1, respectively, they may be provided in different layers.

The transistor TrG includes a semiconductor71, a source electrode72, a drain electrode73, a first gate electrode74A, and a second gate electrode74B. The transistor TrG is a switching element included in the drive circuits12. The transistor TrG also has a layer structure similar to that of the first transistor Tr1, and a detailed description thereof is omitted. The third transistor Tr3and the fourth transistor Tr4(refer toFIG.2) also have a layer structure similar to that of the first transistor Tr1.

FIG.4is an enlarged view of a coupling part between the array substrate and the light-emitting element. The light-emitting element3includes a light-emitting layer composed of an n-type cladding layer, an active layer, and a p-type cladding layer stacked in order and is made of compound semiconductor, such as gallium nitride (GaN) and aluminum indium phosphorus (AlInP). As illustrated inFIG.4, the light-emitting element3has what is called a face-down structure in which a cathode3acoupled to the n-type cladding layer and an anode3bcoupled to the p-type cladding layer are provided at the lower part. The light-emitting element3may be made of a known LED chip.

As illustrated inFIG.3, the array substrate2includes a first electrode22, a second electrode23, a third electrode24, a fourth electrode25, and a plurality of auxiliary pads30.

The first electrode22and the second electrode23are provided between the substrate21and the light-emitting element3. The first electrode22is provided on a first surface96aof a sixth insulating film96and is electrically coupled to the cathode wiring26(refer toFIG.1) provided in the peripheral region GA. As illustrated inFIG.4, the first electrode22is coupled to the cathode3aof the light-emitting element3. The first electrode22includes a first pad22aas an electrode bonded to the cathode3aof the light-emitting element3. The first pad22ais bonded to the cathode3aof the light-emitting element3by welding. In other words, the first pad22ais heated and melted by a laser device or the like in bonding. Subsequently, the end of the cathode3aof the light-emitting element3is thrust into and bonded to the melted first pad22a. The first pad22amay be referred to as a cathode pad.

The second electrode23is coupled to the anode3bof the light-emitting element3. The second electrode23includes a second pad23aas an electrode bonded to the anode3bof the light-emitting element3. Similarly to the cathode3a, the second pad23ais bonded to the anode3bof the light-emitting element3by welding. The second pad23amay be referred to as an anode pad. The second electrode23is provided on the first surface96aof the sixth insulating film96. As illustrated inFIG.3, the second electrode23is coupled to the third electrode24through a contact hole H7.

The third electrode24is provided on the fifth insulating film95and is electrically coupled to the drain electrode63through a contact hole H2. Thus, the second electrode23and the third electrode24couples the anode of the light-emitting element3to the drain electrode63of the first transistor Tr1. The fourth electrode25is provided in the same layer as that of the third electrode24and is electrically coupled to the source electrode62through a contact hole H4.

The fourth electrode25extends on the fifth insulating film95and faces the first electrode22with the sixth insulating film96interposed therebetween in the third direction Dz. As a result, capacitance is formed between the first electrode22and the fourth electrode25. The capacitance formed between the first electrode22and the fourth electrode25is used as the holding capacitance CS in the pixel circuit28.

A seventh insulating film97is provided on the first electrode22, the second electrode23, and the sixth insulating film96. The seventh insulating film97has an opening97athrough which the first electrode22and the second electrodes23can be coupled to the light-emitting element3.

The planarization film27is provided on the seventh insulating film97. The planarization film27is provided from the display region AA to the peripheral region GA. The planarization film27is a translucent organic insulating film and is made of resin material, such as silicone resin, epoxy resin, acrylic resin, and polyimide resin. A cover5made of a light-transmitting member, such as glass, is provided on the planarization film27.

As illustrated inFIG.4, the auxiliary pads30are made of conductive material and have electrical conductivity. The auxiliary pads30according to the present embodiment are made of metal material that melts by being heated by a laser device or the like. The auxiliary pads30are provided on the first surface96aof the sixth insulating film96. The auxiliary pads30are disposed between the first pad22aand the second pad23aand near the ends of the first pad22aand the second pad23a. Being disposed near the ends of the first pad22aand the second pad23ameans being disposed in the range exposed from the opening97aof the seventh insulating film97and being separated from the ends of the first pad22aand the second pad23ato such an extent that electrical insulation from the first pad22aand the second pad23acan be secured. If the auxiliary pads30are not exposed from the opening97aof the seventh insulating film97, the anode3band other components fail to be electrically coupled to the auxiliary pads30when the light-emitting element3is mounted on the array substrate2.

FIG.5is a plan view ofFIG.4. As illustrated inFIG.5, a distance W1between the first pad22aand the second pad23ais larger than a width W2of the cathode3aand the anode3bof the light-emitting element3in the first direction Dx. This configuration can prevent the cathode3aor the anode3bfrom being coupled to both the first pad22aand the second pad23aacross them if the mounting position of the light-emitting element3is misaligned in the first direction Dx.

Five auxiliary pads30are provided. Each auxiliary pad30has a rectangular shape longer in the second direction Dy than in the first direction Dx when viewed from the third direction Dz. Each auxiliary pad30has an island shape and is electrically floating in the process before the light-emitting element3is mounted. The five auxiliary pads30are arrayed in the first direction Dx with a space W3interposed therebetween. In the following description, the five auxiliary pads30may be referred to as a first auxiliary pad31, a second auxiliary pad32, a third auxiliary pad33, a fourth auxiliary pad34, and a fifth auxiliary pad35in order from the first pad22ato the second pad23aas necessary. To describe properties common to the first auxiliary pad31, the second auxiliary pad32, the third auxiliary pad33, the fourth auxiliary pad34, and the fifth auxiliary pad35, they are collectively referred to as the auxiliary pads30.

The first pad22aand the first auxiliary pad31are separated in the first direction Dx. The space between the first pad22aand the first auxiliary pad31is W3, which is equal to the space between the five auxiliary pads30. Similarly, the second pad23aand the fifth auxiliary pad35are separated in the first direction Dx. The space between the second pad23aand the fifth auxiliary pad35is W3. Thus, all the spaces between the first pad22a, the first auxiliary pad31, the second auxiliary pad32, the third auxiliary pad33, the fourth auxiliary pad34, the fifth auxiliary pad35, and the second pad23ain the first direction Dx are W3and equal to one another.

FIG.6is a view of a state where the fifth auxiliary pad according to the first embodiment is crushed by the anode3b. To mount the light-emitting element3on the array substrate2, the auxiliary pads30are heated and melted by a laser device or the like. If the mounting position of the light-emitting element3is misaligned in the first direction Dx as illustrated inFIG.6, the auxiliary pad30(refer to the fifth auxiliary pad35inFIG.6) may possibly be crushed by the cathode3aor the anode3b. The light-emitting element3illustrated inFIGS.4and5is not misaligned. When crushed by the cathode3aor the anode3b, the auxiliary pads30expand in the first direction Dx because there are gaps therebetween in the first direction Dx. Therefore, the auxiliary pad30has a bulge30a(refer to a bulge35ainFIG.6) that expands in the first direction Dx due to misalignment of the light-emitting element3.

A first expansion amount of the bulge30a(refer to the bulge35ainFIG.6) in the first direction Dx is W4. The expansion amount indicates the amount of expansion in one direction of the first direction Dx with respect to the auxiliary pad30before being crushed. By contrast, the space W3between the first pad22a, the second pad23a, and the five auxiliary pads30is smaller than the first expansion amount W4. If the bulge30ais formed on the auxiliary pad30, the auxiliary pad30comes into contact with the first pad22a, the second pad23a, or another auxiliary pad30disposed adjacently thereto in the first direction Dx.

In the display device1described above, the array substrate2includes the substrate21to the seventh insulating film97covering the first electrode22and the second electrode23. The array substrate2does not include the planarization film27, the light-emitting element3, or the cover5.

FIG.7is a view of a case where the light-emitting element is mounted with its center in the first direction misaligned closer to the first pad.FIG.8is a view of a case where the light-emitting element is mounted with its center in the first direction misaligned closer to the second pad. The following describes a case where the light-emitting element3mounted on the array substrate2is misaligned. As illustrated inFIG.7, if a center O of the light-emitting element3in the first direction Dx comes closer to the first pad22a, the anode3bof the light-emitting element3crushes the fourth auxiliary pad34and the fifth auxiliary pad35, for example. As a result, the bulge (refer to the bulge30ainFIG.6) of the fourth auxiliary pad34comes into contact with the third auxiliary pad33and the fifth auxiliary pad35disposed adjacently thereto. The bulge (refer toFIG.6)35aformed on the fifth auxiliary pad35comes into contact with the second pad23adisposed adjacently thereto in the first direction Dx. In addition, the second pad23ais also crushed by the anode3bas illustrated inFIG.7. As a result, the second pad23ahas a bulge23bthat expands toward the fifth auxiliary pad35and surely comes into contact with the fifth auxiliary pad35. Therefore, the part of the anode3bnot in contact with the second pad23ais electrically coupled to the second pad23avia the fourth auxiliary pad34and the fifth auxiliary pad35.

By contrast, if the center O of the light-emitting element3in the first direction Dx comes closer to the second pad23a, the cathode3aof the light-emitting element crushes the first auxiliary pad31and the second auxiliary pad32, for example, as illustrated inFIG.8. As a result, the bulge (refer to the bulge30ainFIG.6) of the second auxiliary pad32comes into contact with the first auxiliary pad31and the third auxiliary pad33disposed adjacently thereto in the first direction Dx. The bulge (refer to the bulge30ainFIG.6) of the first auxiliary pad31comes into contact with the first pad22adisposed adjacently thereto in the first direction Dx. In addition, the first pad22ais also crushed by the cathode3aas illustrated inFIG.8. As a result, the first pad22ahas a bulge22bthat expands toward the first auxiliary pad31and surely comes into contact with the first auxiliary pad31. Therefore, the part of the cathode3anot in contact with the first pad22ais electrically coupled to the first pad22avia the first auxiliary pad31and the second auxiliary pad32.

As described above, the display device1and the array substrate (wiring substrate)2according to the first embodiment suppress an increase in electrical resistance of the coupling part composed of the cathode3aand the first pad22aif the mounting position of the light-emitting element3is misaligned. The display device1and the array substrate2also suppress an increase in electrical resistance of the coupling part composed of the anode3band the second pad23a.

While the anode3band the cathode3aaccording to the first embodiment are bonded to the pads (the first pad22aand the second pad23a) by welding, the wiring substrate and the display device according to the present disclosure are not limited thereto. A second embodiment below describes an example where they are bonded using an anisotropic conductive film (ACF). In the following description, the same components as those described in the embodiment above are denoted by like reference numerals, and overlapping explanation thereof is omitted.

Second Embodiment

FIG.9is an enlarged view of the coupling part between the array substrate and the light-emitting element in the display device according to the second embodiment. As illustrated inFIG.9, a display device1A is different from the display device1according to the first embodiment in that it includes an anisotropic conductive film40. The anisotropic conductive film40is disposed over the first pad22a, the auxiliary pads30, and the second pad23a. The spaces between the first pad22a, the auxiliary pads30, and the second pad23ain the first direction Dx according to the second embodiment are W5and equal to one another.

The anisotropic conductive film40includes a plurality of metal particles42in a sheet-like thermosetting resin41and has electrical conductivity in the third direction Dz. The anisotropic conductive film40is placed over the first pad22a, the auxiliary pads30, and the second pad23abefore being cured and is welded to the first pad22a, the auxiliary pads30, and the second pad23a. The anode3band the cathode3aof the light-emitting element3are thrust into the anisotropic conductive film40before it is cured, and the anisotropic conductive film40is welded to the anode3band the cathode3a. Some of the metal particles42are pressed toward the first pad22aand the second pad23adue to the thrusting the anode3band the cathode3a. For clear understanding, dots are marked inside the metal particles42pressed by the anode3bor the cathode3ainFIG.9. Therefore, in the display device1A according to the second embodiment, the parts of the anode3band the cathode3aoverlapping the first pad22aand the second pad23awhen viewed from the third direction Dz are electrically coupled to the first pad22aand the second pad23avia the metal particles42.

In the configuration according to the second embodiment, the space W5between the first pad22a, the auxiliary pads30, and the second pad23ain the first direction Dx is smaller than the particle diameter of the metal particles42. If the center of the light-emitting element3in the first direction Dx is misaligned closer to the first pad22a, the metal particles42are pressed by the anode3band are interposed between the anode3band the fourth auxiliary pad34and between the anode3band the fifth auxiliary pad35as illustrated inFIG.9. In addition, the metal particles42are interposed between the fourth auxiliary pad34and the fifth auxiliary pad35and between the fifth auxiliary pad35and the second pad23a. Therefore, the part of the anode3bnot overlapping the second pad23awhen viewed from the third direction Dz is electrically coupled to the fourth auxiliary pad34and the fifth auxiliary pad35via the metal particles42and is electrically coupled to the second pad23a. As described above, the second embodiment also suppresses an increase in electrical resistance of the coupling part.

Third Embodiment

FIG.10is an enlarged view of a state where the light-emitting element is yet to be bonded to the array substrate in the display device according to a third embodiment.FIG.11is an enlarged view of a state where the light-emitting element is bonded to the array substrate in the display device according to the third embodiment. As illustrated inFIGS.16and17, a display device1B according to the third embodiment is different from the display device1according to the first embodiment and the display device1B according to the second embodiment in that it includes a conductive material50. The conductive material50is solder material, such as Sn. The conductive material50is welded to the end surfaces of the anode3band the cathode3aof the light-emitting element3. To mount the light-emitting element3, the conductive material50is heated and melted and adheres to the end surfaces of the anode3band the cathode3a. The anode3band the cathode3aare pressed against the first pad22aand the second pad23awhile maintaining the melted state of the conductive material50. When the conductive material50hardens, the anode3band the cathode3aare bonded to the first pad22aand the second pad23a.

With this configuration, if the center of the light-emitting element3in the first direction Dx is misaligned closer to the first pad22aas illustrated inFIG.17, the conductive material50on the end surface of the anode3benters and hardens between the second pad23aand the fifth auxiliary pad35, between the fifth auxiliary pad35and the fourth auxiliary pad34, and between the fourth auxiliary pad34and the third auxiliary pad33. Therefore, the part of the anode3bnot overlapping the second pad23awhen viewed from the third direction Dz is electrically coupled to the fourth auxiliary pad34and the fifth auxiliary pad35via the conductive material50and is electrically coupled to the second pad23a. As described above, the third embodiment also suppresses an increase in electrical resistance of the coupling part.

While the first embodiment, the second embodiment, and the third embodiment have described a plurality of auxiliary pads disposed at equal intervals, for example, the auxiliary pads according to the present disclosure are not limited thereto. The following describes arrangement examples of the auxiliary pads.

First Modification

FIG.12is a plan view of the auxiliary pads according to a first modification. The array substrate2according to the first modification includes four auxiliary pads30A. In other words, the auxiliary pads30A are different from the auxiliary pads30according to the first embodiment in that they do not include the third auxiliary pad33(refer toFIG.5).

A space W6between the second auxiliary pad32and the fourth auxiliary pad34has such a length that the second auxiliary pad32and the fourth auxiliary pad34do not come into contact with each other if they are both crushed by the anode3bor the cathode3aacross them. In other words, the space W6is such a distance that the bulge30a(refer toFIG.6) formed on the second auxiliary pad32and the bulge30a(refer toFIG.6) formed on the fourth auxiliary pad34do not come into contact with each other. Specifically, the space W6is longer than twice the first expansion amount W4of the bulge30a. This configuration prevents the second auxiliary pad32from being electrically coupled to the fourth auxiliary pad34and can reliably prevent a short circuit between the first pad22aand the second pad23a. If the anode3band the second pad23a, for example, are bonded not by welding but by the anisotropic conductive film40(refer toFIG.9), electrical insulation is secured if the space W6is larger than the particle diameter of the metal particles42.

Second Modification

FIG.13is a plan view of the auxiliary pads according to a second modification. Similarly to the first embodiment, the array substrate2according to the second modification includes five auxiliary pads30B. Both the space between the first pad22aand the first auxiliary pad31and the space between the second pad23aand the fifth auxiliary pad35are W11. Both the space between the first auxiliary pad31and the second auxiliary pad32and the space between the fourth auxiliary pad34and the fifth auxiliary pad35are W12. Both the space between the second auxiliary pad32and the third auxiliary pad33and the space between the third auxiliary pad33and the fourth auxiliary pad34are W13. The distance increases in the order of the spaces W11, W12, and W13. Thus, the space increases toward the center in the first direction Dx in which the auxiliary pads30B are arrayed. In other words, the auxiliary pads according to the present disclosure need not have a constant distance from the auxiliary pads30or the like disposed adjacently thereto.

Third Modification

FIG.14is a plan view of the auxiliary pads according to a third modification. The array substrate2according to the third modification includes five auxiliary pads30C. A first auxiliary pad31C, a second auxiliary pad32C, a third auxiliary pad33C, a fourth auxiliary pad34C, and a fifth auxiliary pad35C each have a wavy shape alternately protruding toward one side and the other side in the first direction Dx from one end to the other end in the second direction Dy. Thus, the auxiliary pads according to the present disclosure are not limited to rectangular pads and may have a shape corresponding to the shape of the ends of the first pad22aand the second pad23a.

Fourth Modification

FIG.15is a plan view of the auxiliary pads according to a fourth modification. An auxiliary pad30D of the array substrate2according to the fourth modification is a square auxiliary pad36that has a square shape in plan view. A plurality of the square auxiliary pads36are provided and are equally spaced in the first direction Dx and the second direction Dy. When crushed by the anode3bor the cathode3a, the square auxiliary pad36expands in the first direction Dx and the second direction Dy.

Fifth Modification

FIG.16is a plan view of the auxiliary pads according to a fifth modification. Auxiliary pads30E of the array substrate2according to the fifth modification are composed of peripheral auxiliary pads37a,37b,37c, and37dsurrounding the first pad22a, and peripheral auxiliary pads38a,38b,38c, and38dsurrounding the second pad23a. The peripheral auxiliary pads37aand37care separated from the first pad22aand sandwich the first pad22ain the first direction Dx. The peripheral auxiliary pads37band37dare separated from the first pad22aand sandwich the first pad22ain the second direction Dy. The peripheral auxiliary pads38aand38care separated from the second pad23aand sandwich the second pad23ain the first direction Dx. The peripheral auxiliary pads38band38dare separated from the second pad23aand sandwich the second pad23ain the second direction Dy. The anode3band the cathode3aaccording to the embodiments and the other modifications described above come into contact with the auxiliary pads if they are misaligned between the first pad22aand the second pad23a. By contrast, the anode3band the cathode3aaccording to the fifth modification can be electrically coupled to the first pad22aand the second pad23aif they are misaligned at a position other than between the first pad22aand the second pad23a.

Sixth Modification

FIG.17is a plan view of the auxiliary pads according to a sixth modification. Auxiliary pads30F of the array substrate2according to the sixth modification are rectangular frame-shaped auxiliary pads39surrounding the first pad22aand the second pad23a. The frame-shaped auxiliary pads39can also achieve the same advantageous effects as those according to the fifth modification.

While the wiring substrate and the display device according to the embodiments and the modifications have been described above, an increase in electrical resistance of the coupling part can be suppressed by at least one auxiliary pad according to the present disclosure. Therefore, a wiring board and a display device provided with one auxiliary pad near the end of the first pad22a(cathode pad) or the second pad23a(anode pad) is also included in the wiring substrate and the display device according to the present disclosure.