Patent ID: 12218587

5. DETAILED DESCRIPTION OF THE INVENTION

Certain embodiments of the present invention are directed to circuits. More particularly, some embodiments of the invention provide systems and methods for controlling operation modes of DC-to-DC voltage converters. Merely by way of example, some embodiments of the invention have been applied to buck-boost converters. But it would be recognized that the invention has a much broader range of applicability.

FIG.6is a simplified diagram showing a power transmitter of a wireless charging system according to certain embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The power transmitter600includes a DC-to-DC voltage converter610, a wireless power controller620, and a full-bridge LC resonant circuit630, and the DC-to-DC voltage converter610includes components as shown inFIG.9. As an example, the full-bridge LC resonant circuit630includes a coil640, a capacitor680, and switches690,692,694and696. Although the above has been shown using a selected group of components for the power transmitter600, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. Further details of these components are found throughout the present specification.

In some examples, the wireless power controller620generates control signals622and624. For example, the control signal622is received by the DC-to-DC voltage converter610. As an example, the control signal624is received by the full-bridge LC resonant circuit630. In certain examples, the DC-to-DC voltage converter610receives an input voltage612(e.g., VIN). For example, in response to the control signal622, the DC-to-DC voltage converter610uses the input voltage612(e.g., VIN) to generate an output voltage614(e.g., VOUT). As an example, the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) both are DC voltages, whose magnitudes satisfy a predetermined matching relationship. In certain examples, the output voltage614(e.g., VOUT) is received by the full-bridge LC resonant circuit630. For example, the full-bridge LC resonant circuit630includes the coil640that is coupled to another coil of a power receiver as part of the wireless charging system. As an example, the input voltage612(e.g., VIN) is provided through a USB port from a power adapter, a 12-volt power source on an automobile, and/or a portable power bank. In some examples, the output voltage614(e.g., VOUT) is higher than, equal to, or lower than the input voltage612(e.g., VIN).

As shown inFIG.6, the DC-to-DC voltage converter610operates in a boost mode and/or in a buck mode according to some embodiments. In certain examples, the DC-to-DC voltage converter610operates in the boost mode. For example, in the boost mode, the DC-to-DC voltage converter610functions as a step-up converter. As an example, in the boost mode, the output voltage614(e.g., VOUT) is larger than the input voltage612(e.g., VIN). In some examples, the DC-to-DC voltage converter610operates in the buck mode. For example, in the buck mode, the DC-to-DC voltage converter610functions as a step-down converter. As an example, in the buck mode, the output voltage614(e.g., VOUT) is smaller than the input voltage612(e.g., VIN).

FIG.7is a simplified diagram showing the DC-to-DC voltage converter610according to certain embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The DC-to-DC voltage converter610includes a capacitor722(e.g., CIN), a capacitor724(e.g., COUT), a coil730, a switch network750, a current detector760, and a voltage controller770, and the voltage controller770includes components as shown inFIG.9. Additionally, the DC-to-DC voltage converter610also includes an input terminal740and an output terminal742. Although the above has been shown using a selected group of components for the DC-to-DC voltage converter610, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. Further details of these components are found throughout the present specification.

As shown inFIG.7, the voltage controller770includes input terminals744and746and output terminals772,774,776and778, and the switch network750includes input terminals752,754,756and758according to some embodiments. For example, the switch network750includes multiple switches. As an example, the multiple switches of the switch network750include one or more switches that are connected to the coil730. For example, the switch network750also includes an input terminal792and the output terminal794, where the input terminal792is connected to the input terminal740and the output terminal794is connected to the output terminal742. In certain examples, the coil730and the coil640are two separate coils. In some examples, the input terminal740receives the input voltage612(e.g., VIN), and the output terminal742outputs the output voltage614(e.g., VOUT). For example, one terminal of the capacitor722(e.g., CIN) is connected to the input terminal740, and another terminal of the capacitor722(e.g., CIN) is biased to a ground voltage. As an example, one terminal of the capacitor724(e.g., COUT) is connected to the output terminal742, and another terminal of the capacitor724(e.g., COUT) is biased to the ground voltage.

In certain embodiments, the current detector760is used to detect a coil current that flows through the coil730and generates a detection signal762. For example, the current detector760includes a current sensing resistor, where the voltage drop across the current sensing resistor depends on the current that flow through the coil730. As an example, the voltage drop across the current sensing resistor is used to generate the detection signal762(e.g., VSNS).

In some embodiments, the voltage controller770receives the detection signal762(e.g., VSNS) at the input terminal748, receives the input voltage612(e.g., VIN) at the input terminal744, and receives the output voltage614(e.g., VOUT) at the input terminal746. As an example, based at least in part on the input voltage612(e.g., VIN), the output voltage614(e.g., VOUT), and the detection signal762(e.g., VSNS), the voltage controller770generates control signals782,784,786and788.

According to certain embodiments, the voltage controller770outputs the control signals782,784,786and788at the output terminals772,774,776and778respectively, and the switch network750receives the control signals782,784,786and788at the input terminals752,754,756and758respectively. For example, the switch network750uses the control signals782,784,786and788to close or open the multiple switches (e.g., four switches) of the switch network750in order to control the increase or the decrease of the output voltage614(e.g., VOUT). As an example, the output voltage614(e.g., VOUT) is controlled to be equal to, smaller than, or larger than the input voltage612(e.g., VIN).

As shown inFIG.7, the DC-to-DC voltage converter610operates in a boost mode and/or in a buck mode according to some embodiments. In certain examples, the DC-to-DC voltage converter610operates in the boost mode. For example, in the boost mode, the DC-to-DC voltage converter610functions as a step-up converter. As an example, in the boost mode, the output voltage614(e.g., VOUT) is larger than the input voltage612(e.g., VIN). In some examples, the DC-to-DC voltage converter610operates in the buck mode. For example, in the buck mode, the DC-to-DC voltage converter610functions as a step-down converter. As an example, in the buck mode, the output voltage614(e.g., VOUT) is smaller than the input voltage612(e.g., VIN).

As discussed above and further emphasized here,FIG.7is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. In some examples, the coil730is part of the switch network750, which also includes the multiple switches. In certain examples, the DC-to-DC voltage converter610is not a part of the power transmitter600as shown inFIG.6. For example, the DC-to-DC voltage converter610is in compliance with USB Power Delivery (USB PD). As an example, the DC-to-DC voltage converter610is used for power supply in an automobile.

FIG.8is a simplified diagram showing certain components of the DC-to-DC voltage converter610as shown inFIG.7according to some embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As an example, the switch network750includes the input terminal792and the output terminal794, and also includes a switch852, a switch854, a switch856, and a switch858. For example, the current detector760includes a current sensing resistor860and a current sampling amplifier870. Although the above has been shown using a selected group of components for the DC-to-DC voltage converter610, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. Further details of these components are found throughout the present specification.

According to certain embodiments, the switch852(e.g., SA), the coil730, the current sensing resistor860, and the switch858(e.g., SD) are connected in series. In some examples, one terminal of the switch852(e.g., SA) is connected to the input terminal792that receives the input voltage612(e.g., VIN), and another terminal of the switch852(e.g., SA) is connected to one terminal of the coil730and one terminal of the switch854(e.g., SB) through a node832(e.g., SW1). For example, another terminal of the switch854(e.g., SB) is biased to the ground voltage. In certain examples, one terminal of the switch858(e.g., SD) is connected to the output terminal794that outputs the output voltage614(e.g., VOUT), and another terminal of the switch858(e.g., SD) is connected to the current sensing resistor860and one terminal of the switch856(e.g., SC) through a node834(e.g., SW2). As an example, another terminal of the switch856(e.g., SC) is biased to the ground voltage. For example, another terminal of the current sensing resistor860is connected to another terminal of the coil730. In some examples, a coil current836(e.g., IL) flows through the coil730as shown inFIG.13. For example, the current sensing resistor860allows the coil current836(e.g., IL) to flow through the current sensing resistor860.

According to some embodiments, the control signal782is used to close or open the switch852(e.g., SA), the control signal784is used to close or open the switch854(e.g., SB), the control signal786is used to close or open the switch856(e.g., SC), and the control signal788is used to close or open the switch858(e.g., SD). For example, under certain condition, both the switch852(e.g., SA) and the switch858(e.g., SD) are closed, so that a current flows from the input terminal792to the output terminal794through the switch852(e.g., SA), the coil730, the current sensing resistor860, and the switch858(e.g., SD). As an example, allowing both the switch852(e.g., SA) and the switch858(e.g., SD) to be closed at the same time reduces the average magnitude of the coil current836(e.g., IL) that flows through the coil730and also lowers the conduction loss.

In some embodiments, the current sampling amplifier870(e.g., ACS) includes an input terminal872, an input terminal874, and an output terminal876. For example, the input terminal872(e.g., SNSP) is connected to one terminal of the current sensing resistor860, and the input terminal874(e.g., SNSN) is connected to another terminal of the current sensing resistor860. As an example, the output terminal876outputs the detection signal762.

In certain embodiments, the current sensing resistor860converts the coil current836, which flows through the coil730, to a voltage difference across the current sensing resistor860. For example, the voltage difference across the current sensing resistor860is equal to a voltage difference between the input terminal872(e.g., SNSP) and the input terminal874(e.g., SNSN). As an example, the voltage difference between the input terminal872(e.g., SNSP) and the input terminal874(e.g., SNSN) is used by the current sampling amplifier870(e.g., ACS) to generate the detection signal762at the output terminal876.

According to some embodiments, the detection signal762represents an amplified magnitude of the coil current836during multiple switching cycles. For example, the detection signal762(e.g., VSNS) represents the amplified magnitude of the coil current836during one switching cycle, and then the detection signal762(e.g., VSNS) represents the amplified magnitude of the coil current836during another switching cycle. As an example, each switching cycle includes one half switching cycle during which both the switch852(e.g., SA) and the switch856(e.g., SC) are closed and both the switch854(e.g., SB) and the switch858(e.g., SD) are open, and also includes another half switching cycle during which both the switch852(e.g., SA) and the switch856(e.g., SC) are open and both the switch854(e.g., SB) and the switch858(e.g., SD) are closed.

FIG.9is a simplified diagram showing certain components of the voltage controller770of the DC-to-DC voltage converter610as shown inFIG.7according to certain embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As an example, the voltage controller770includes a modulation signal generator910, an operation mode controller920, and a control signal generator930. Although the above has been shown using a selected group of components for the voltage controller770, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. Further details of these components are found throughout the present specification.

According to some embodiments, the modulation signal generator910receives the output voltage614(e.g., VOUT) and the detection signal762(e.g., VSNS) and generates a pulse-width-modulation signal912for the boost mode (e.g., PWM_BST) and a pulse-width-modulation signal914for the buck mode (e.g., PWM_BUK). For example, the pulse-width-modulation signal912for the boost mode (e.g., PWM_BST) and the pulse-width-modulation signal914for the buck mode (e.g., PWM_BUK) are received by the operation mode controller920, which also receives the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) and generates a logic signal922(e.g., BST), a logic signal924(e.g., BUK), a logic signal926(e.g., BST_ON), and a logic signal928(e.g., BUK_ON). As an example, the logic signal922(e.g., BST), the logic signal924(e.g., BUK), the logic signal926(e.g., BST_ON), and the logic signal928(e.g., BUK_ON) are received by the control signal generator930, which generates the control signals782,784,786and788.

In certain embodiments, the modulation signal generator910includes a voltage divider940, an error amplifier970, a resistor972, a capacitor974, a pulse-width-modulation signal generator950, a pulse-width-modulation signal generator960, a voltage adder980, and a voltage subtractor982. In some examples, the voltage divider940includes a resistor942(e.g., RFB1) and a resistor944(e.g., RFB2). For example, one terminal of the resistor942(e.g., RFB1) receives the output voltage614(e.g., VOUT), and another terminal of the resistor942(e.g., RFB1) is connected to one terminal of the resistor944(e.g., RFB2) and used to generate a voltage943(e.g., VFB). As an example, another terminal of the resistor944(e.g., RFB2) is biased to the ground voltage. In certain examples, the error amplifier970includes an inverting input terminal (e.g., the “−” input terminal), a non-inverting input terminal (e.g., the “+” input terminal), and an output terminal. For example, the inverting input terminal (e.g., the “−” input terminal) is used to receive the voltage943(e.g., VFB), and the non-inverting input terminal (e.g., the “+” input terminal) is used to receive a reference voltage945(e.g., VREF). As an example, the output terminal of the error amplifier970is connected to a terminal of the resistor972(e.g., RCOMP). In some examples, the resistor972(e.g., RCOMP) also includes another terminal that is connected to a terminal of the capacitor974(e.g., CCOMP). For example, the capacitor974(e.g., CCOMP) also includes another terminal that is biased to the ground voltage.

In some embodiments, the error amplifier970operates together with the resistor972(e.g., RCOMP) and the capacitor974(e.g., CCOMP) and generates a compensation voltage971(e.g., VCOMP). For example, the compensation voltage971(e.g., VCOMP) is received by the pulse-width-modulation signal generator950, which also receives a voltage951(e.g., VSUM_BST) from the voltage adder980and generates the pulse-width-modulation signal912for the boost mode (e.g., PWM_BST). As an example, the compensation voltage971(e.g., VCOMP) is also received by the pulse-width-modulation signal generator960, which also receives a voltage961(e.g., VSUM_BUK) from the voltage subtractor982and generates the pulse-width-modulation signal914for the buck mode (e.g., PWM_BUK).

According to certain embodiments, the pulse-width-modulation signal generator950includes a comparator952, a NAND gate954, a NAND gate956, and a flip-flop958. In some examples, the comparator952includes an inverting input terminal (e.g., the “−” input terminal), a non-inverting input terminal (e.g., the “+” input terminal), and an output terminal. For example, the inverting input terminal (e.g., the “−” input terminal) of the comparator952receives the compensation voltage971(e.g., VCOMP), and the non-inverting input terminal (e.g., the “+” input terminal) of the comparator952receives the voltage951(e.g., VSUM_BST) from the voltage adder980. As an example, the output terminal of the comparator952outputs a comparison signal953(e.g., PWM1). In certain examples, the NAND gate954receives the comparison signal953(e.g., PWM1) and a signal955(e.g., MINON_BST), and generates a logic signal957. For example, the signal955(e.g., MINON_BST) represents a predetermined minimum duration for the switch856(e.g., SC) to be closed in the boost mode. In some examples, the NAND gate956receives the logic signal957and a signal959(e.g., MAXON_BST) and generates a logic signal990. For example, the signal959(e.g., MAXON_BST) represents a predetermined maximum duration for the switch856(e.g., SC) to be closed in the boost mode. In certain examples, the logic signal990is received by an input terminal (e.g., the “R” input terminal) of the flip-flop958, which includes another input terminal (e.g., the “S” input terminal) that receives a clock signal992(e.g., CLK_BST). For example, the flip-flop958generates the pulse-width-modulation signal912for the boost mode (e.g., PWM_BST) at an output terminal (e.g., the “Q” output terminal).

According to some embodiments, the pulse-width-modulation signal generator960includes a comparator962, a NAND gate964, a NAND gate966, and a flip-flop968. In some examples, the comparator962includes an inverting input terminal (e.g., the “−” input terminal), a non-inverting input terminal (e.g., the “+” input terminal), and an output terminal. For example, the inverting input terminal (e.g., the “−” input terminal) of the comparator962receives the compensation voltage971(e.g., VCOMP), and the non-inverting input terminal (e.g., the “+” input terminal) of the comparator962receives the voltage961(e.g., VSUM_BUK) from the voltage subtractor982. As an example, the output terminal of the comparator962outputs a comparison signal963(e.g., PWM2). In certain examples, the NAND gate964receives the comparison signal963(e.g., PWM2) and a signal965(e.g., MINON_BUK), and generates a logic signal967. For example, the signal965(e.g., MINON_BUK) represents a predetermined minimum duration for the switch854(e.g., SB) to be closed in the buck mode. In some examples, the NAND gate966receives the logic signal967and a signal969(e.g., MAXON_BUK) and generates a logic signal996. For example, the signal969(e.g., MAXON_BUK) represents a predetermined maximum duration for the switch854(e.g., SB) to be closed in the buck mode. In certain examples, the logic signal996is received by an input terminal (e.g., the “R” input terminal) of the flip-flop968, which includes another input terminal (e.g., the “S” input terminal) that receives a clock signal998(e.g., CLK_BUK). For example, the flip-flop968generates the pulse-width-modulation signal914for the buck mode (e.g., PWM_BUK) at an output terminal (e.g., the “Q” output terminal).

In certain embodiments, the voltage adder980receives the detection signal762(e.g., VSNS) and a signal981(e.g., SLOPE_BST) and generates the voltage951(e.g., VSUM_BST) by adding the detection signal762(e.g., VSNS) and the signal981(e.g., SLOPE_BST). For example, the signal981(e.g., SLOPE_BST) is a ramp voltage for the boost mode. As an example, the signal981(e.g., SLOPE_BST) is used to prevent sub-harmonic oscillation of the power transmitter600in the boost mode. In some embodiments, the voltage subtractor982receives the detection signal762(e.g., VSNS) and a signal983(e.g., SLOPE_BUK) and generates the voltage961(e.g., VSUM_BUK) by subtracting the signal983(e.g., SLOPE_BUK) from the detection signal762(e.g., VSNS). For example, the signal983(e.g., SLOPE_BUK) is a ramp voltage for the buck mode. As an example, the signal983(e.g., SLOPE_BUK) is used to prevent sub-harmonic oscillation of the power transmitter600in the buck mode.

According to some embodiments, the operation mode controller920receives the input voltage612(e.g., VIN), the output voltage614(e.g., VOUT), the pulse-width-modulation signal914for the buck mode (e.g., PWM_BUK), and the pulse-width-modulation signal912for the boost mode (e.g., PWM_BST), and generates the logic signal922(e.g., BST), the logic signal924(e.g., BUK), the logic signal926(e.g., BST_ON), and the logic signal928(e.g., BUK_ON). In certain examples, the control signal generator930receives the logic signal922(e.g., BST), the logic signal924(e.g., BUK), the logic signal926(e.g., BST_ON), and the logic signal928(e.g., BUK_ON), and generates the control signals782,784,786and788.

FIG.10A,FIG.10B, andFIG.10Care simplified diagrams showing certain operations of the operation mode controller920of the voltage controller770as part of the DC-to-DC voltage converter610as shown inFIG.9according to certain embodiments of the present invention. These diagrams are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As shown inFIG.9, the operation mode controller920receives the input voltage612(e.g., VIN), the output voltage614(e.g., VOUT), the pulse-width-modulation signal914for the buck mode (e.g., PWM_BUK), and the pulse-width-modulation signal912for the boost mode (e.g., PWM_BST), and generates the logic signal922(e.g., BST), the logic signal924(e.g., BUK), the logic signal926(e.g., BST_ON), and the logic signal928(e.g., BUK_ON), according to some embodiments.

As shown inFIG.10A, in certain embodiments, the operation mode controller920uses the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) to generate the logic signal922(e.g., BST) and the logic signal924(e.g., BUK). As an example, the operation mode controller920determines a ratio of the input voltage612(e.g., VIN) to the output voltage614(e.g., VOUT) and generates the logic signal922(e.g., BST) and the logic signal924(e.g., BUK) based at least in part upon the ratio. For example, the logic signal922(e.g., BST) and the logic signal924(e.g., BUK) are determined by at least the ratio of the input voltage612(e.g., VIN) to the output voltage614(e.g., VOUT) as follows:

K=VINVOUT(Equation⁢⁢1)
where K represents the ratio of the input voltage612(e.g., VIN) to the output voltage614(e.g., VOUT). Additionally, VINrepresents the input voltage612, and VOUTrepresents the output voltage614.

In some examples, when the ratio K increases from a value that is smaller than 0.98 until the ratio K reaches 1.02, the logic signal922(e.g., BST) remains at a logic high level (e.g., BST=1), and the logic signal924(e.g., BUK) remains at a logic low level (e.g., BUK=0). For example, when the ratio K increases to 1.02, the logic signal922(e.g., BST) changes from the logic high level to the logic low level, and the logic signal924(e.g., BUK) changes from the logic low level to the logic high level. As an example, when the ratio K increases from 1.02, the logic signal922(e.g., BST) remains at the logic low level (e.g., BST=0), and the logic signal924(e.g., BUK) remains at the logic high level (e.g., BUK=1).

In certain examples, when the ratio K decreases from a value that is larger than 1.02 until the ratio K reaches 0.98, the logic signal922(e.g., BST) remains at the logic low level (e.g., BST=0), and the logic signal924(e.g., BUK) remains at the logic high level (e.g., BUK=1). For example, when the ratio K decreases to 0.98, the logic signal922(e.g., BST) changes from the logic low level to the logic high level, and the logic signal924(e.g., BUK) changes from the logic high level to the logic low level. As an example, when the ratio K decreases from 0.98, the logic signal922(e.g., BST) remains at the logic high level (e.g., BST=1), and the logic signal924(e.g., BUK) remains at the logic low level (e.g., BUK=0).

As shown inFIG.10B, in some embodiments, the operation mode controller920uses the pulse-width-modulation signal914for the buck mode (e.g., PWM_BUK) to generate the logic signal926(e.g., BST_ON). For example, the logic signal926(e.g., BST_ON) is determined by at least a duty cycle DAof the pulse-width-modulation signal914(e.g., PWM_BUK). In certain examples, when the duty cycle DAof the pulse-width-modulation signal914increases from a value that is smaller than 5% until the duty cycle DAreaches 15%, the logic signal926(e.g., BST_ON) remains at a logic high level (e.g., BST_ON=1). For example, when the duty cycle DAincreases to 15%, the logic signal926(e.g., BST_ON) changes from the logic high level to a logic low level. As an example, when the duty cycle DAincreases from 15%, the logic signal926(e.g., BST_ON) remains at the logic low level (e.g., BST_ON=0). In some examples, when the duty cycle DAof the pulse-width-modulation signal914decreases from a value that is larger than 15% until the duty cycle DAreaches 5%, the logic signal926(e.g., BST_ON) remains at the logic low level (e.g., BST_ON=0). For example, when the duty cycle DAdecreases to 5%, the logic signal926(e.g., BST_ON) changes from the logic low level to the logic high level. As an example, when the duty cycle DAdecreases from 5%, the logic signal926(e.g., BST_ON) remains at the logic high level (e.g., BST_ON=1).

As shown inFIG.10C, in certain embodiments, the operation mode controller920uses the pulse-width-modulation signal912for the boost mode (e.g., PWM_BST) to generate the logic signal928(e.g., BUK_ON). For example, the logic signal928(e.g., BUK_ON) is determined by at least a duty cycle DBof the pulse-width-modulation signal912(e.g., PWM_BST). In certain examples, when the duty cycle DBof the pulse-width-modulation signal912increases from a value that is smaller than 5% until the duty cycle DBreaches 15%, the logic signal928(e.g., BUK_ON) remains at a logic high level (e.g., BUK_ON=1). For example, when the duty cycle DBincreases to 15%, the logic signal928(e.g., BUK_ON) changes from the logic high level to a logic low level. As an example, when the duty cycle DBincreases from 15%, the logic signal928(e.g., BUK_ON) remains at the logic low level (e.g., BUK_ON=0). In some examples, when the duty cycle DBof the pulse-width-modulation signal912decreases from a value that is larger than 15% until the duty cycle DBreaches 5%, the logic signal928(e.g., BUK_ON) remains at the logic low level (e.g., BUK_ON=0). For example, when the duty cycle DBdecreases to 5%, the logic signal928(e.g., BUK_ON) changes from the logic low level to the logic high level. As an example, when the duty cycle DBdecreases from 5%, the logic signal928(e.g., BUK_ON) remains at the logic high level (e.g., BUK_ON=1).

FIG.11is a simplified diagram showing certain components of the control signal generator930of the voltage controller770as part of the DC-to-DC voltage converter610as shown inFIG.9according to some embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The control signal generator930includes NOT gates1102and1108, a NOR gate1104, OR gates1106and1110, an AND gate1112, and drivers1140and1142. Additionally, the control signal generator930also includes NOT gates1122and1128, OR gates1124and1132, a NOR gate1126, an AND gate1130, and drivers1144and1148. Although the above has been shown using a selected group of components for the control signal generator930, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. Further details of these components are found throughout the present specification.

According to certain embodiments, the NOT gate1102receives the logic signal922(e.g., BST) and generates a signal1101. In some examples, the signal1101is received by the NOR gate1104and the OR gate1106, both of which also receive the logic signal928(e.g., BUK_ON). For example, the NOR gate1104uses the signal1101and the logic signal928(e.g., BUK_ON) to generate a signal1103. As an example, the OR gate1106uses the signal1101and the logic signal928(e.g., BUK_ON) to generate a signal1105. In certain examples, the pulse-width-modulation signal914for the buck mode (e.g., PWM_BUK) is received by the AND gate1112and the NOT gate1108. For example, the NOT gate1108uses the pulse-width-modulation signal914to generate a logic signal1107. As an example, the OR gate1110receives the signals1103and1107and generate a signal1109. For example, the AND gate1112receives the pulse-width-modulation signal914and the signal1105and generates a signal1111. In some examples, the driver1140receives the signal1109and generates the control signal782, and the driver1142receives the signal1111and generates the control signal784.

According to some embodiments, the NOT gate1122receives the logic signal924(e.g., BUK) and generates a signal1121. In some examples, the signal1121is received by the OR gate1124and the NOR gate1126, both of which also receive the logic signal926(e.g., BST_ON). For example, the OR gate1124uses the signal1121and the logic signal926(e.g., BST_ON) to generate a signal1123. As an example, the NOR gate1126uses the signal1121and the logic signal926(e.g., BST_ON) to generate a signal1125. In certain examples, the pulse-width-modulation signal912for the boost mode (e.g., PWM_BST) is received by the AND gate1130and the NOT gate1128. For example, the NOT gate1128uses the pulse-width-modulation signal912to generate a logic signal1127. As an example, the OR gate1132receives the signals1125and1127and generate a signal1131. For example, the AND gate1130receives the pulse-width-modulation signal912and the signal1123and generates a signal1129. In some examples, the driver1144receives the signal1129and generates the control signal786, and the driver1146receives the signal1131and generates the control signal788.

In certain embodiments, as shown inFIG.7, the switch network750receives the control signals782,784,786and788and uses the control signals782,784,786and788to close or open the multiple switches (e.g., four switches) of the switch network750. In some embodiments, as shown inFIG.8, the control signal782is used to close or open the switch852(e.g., SA), the control signal784is used to close or open the switch854(e.g., SB), the control signal786is used to close or open the switch856(e.g., SC), and the control signal788is used to close or open the switch858(e.g., SD).

As shown inFIG.7,FIG.8,FIG.9andFIG.11, the DC-to-DC voltage converter610is an in-phase buck-boost converter that includes the switches852,854,856, and858according to some embodiments. For example, the relationship between the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) is obtained based on the volt-second balance principle. As an example, the output voltage614is determined as follows:

VOUT=tAC+tADtBD+tAD×VIN(Equation⁢⁢2)
wherein VOUTrepresents the output voltage614, and VINrepresents the input voltage612. Additionally, tACrepresents, within one switching cycle, the time duration during which both the switch852(e.g., SA) and the switch856(e.g., SC) are closed. Moreover, tADrepresents, within one switching cycle, the time duration during which both the switch852(e.g., SA) and the switch858(e.g., SD) are closed. Also, tBDrepresents, within one switching cycle, the time duration during which both the switch854(e.g., SB) and the switch858(e.g., SD) are closed.

In certain embodiments, if the logic signal922(e.g., BST) is at the logic high level, the logic signal924(e.g., BUK) is at the logic low level, and the logic signal928(e.g., BUK_ON) is at the logic low level, regardless of whether the logic signal926(e.g., BST_ON) is at the logic high level or at the logic low level, the DC-to-DC voltage converter610works in the boost mode. For example, in the boost mode, throughout an entire switching cycle, the control signal782is used to keep the switch852(e.g., SA) closed, the control signal784is used to keep the switch854(e.g., SB) open, and the switch856(e.g., SC) and the switch858(e.g., SD) are sometimes closed and sometimes open, but the switch856(e.g., SC) and the switch858(e.g., SD) are not allowed to be closed at the same time. As an example, in the boost mode, the output voltage614is larger than the input voltage612and is determined as follows:

VOUT=tAC+tADtAD×VIN(Equation⁢⁢3)
wherein VOUTrepresents the output voltage614, and VINrepresents the input voltage612. Additionally, tACrepresents, within one switching cycle, the time duration during which both the switch852(e.g., SA) and the switch856(e.g., SC) are closed. Moreover, tADrepresents, within one switching cycle, the time duration during which both the switch852(e.g., SA) and the switch858(e.g., SD) are closed.

In some embodiments, if the logic signal922(e.g., BST) is at the logic low level, the logic signal924(e.g., BUK) is at the logic high level, and the logic signal926(e.g., BST_ON) is at the logic low level, regardless of whether the logic signal928(e.g., BUK_ON) is at the logic high level or at the logic low level, the DC-to-DC voltage converter610works in the buck mode. For example, in the buck mode, throughout an entire switching cycle, the control signal788is used to keep the switch858(e.g., SD) closed, the control signal786is used to keep the switch856(e.g., SC) open, and the switch852(e.g., SA) and the switch854(e.g., SB) are sometimes closed and sometimes open, but the switch852(e.g., SA) and the switch854(e.g., SB) are not allowed to be closed at the same time. As an example, in the buck mode, the output voltage614is smaller than the input voltage612and is determined as follows:

VOUT=tADtBD+tAD×VIN(Equation⁢⁢4)
wherein VOUTrepresents the output voltage614, and VINrepresents the input voltage612. Moreover, tADrepresents, within one switching cycle, the time duration during which both the switch852(e.g., SA) and the switch858(e.g., SD) are closed. Also, tBDrepresents, within one switching cycle, the time duration during which both the switch854(e.g., SB) and the switch858(e.g., SD) are closed.

According to certain embodiments, the operation modes of the DC-to-DC voltage converter610include the boost mode, the buck mode, and a mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal. As an example, in the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal, the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) are equal. For example, in the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal, the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) are approximately equal within ±10%. As an example, in the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal, the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) are approximately equal within ±20%. In some examples, in the boost mode, the output voltage614(e.g., VOUT) is larger than the input voltage612(e.g., VIN). In certain examples, in the buck mode, the output voltage614(e.g., VOUT) is smaller than the input voltage612(e.g., VIN)

According to some embodiments, whether the DC-to-DC voltage converter610operates in the boost mode, in the buck mode, or in the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal is represented by the logic level of the logic signal922(e.g., BST), the logic level of the logic signal924(e.g., BUK), the logic level of the logic signal926(e.g., BST_ON), and/or the logic level of the logic signal928(e.g., BUK_ON).

In some examples, if the logic signal922(e.g., BST) is at the logic high level, the logic signal924(e.g., BUK) is at the logic low level, and the logic signal928(e.g., BUK_ON) is at the logic high level, regardless of whether the logic signal926(e.g., BST_ON) is at the logic high level or at the logic low level, the DC-to-DC voltage converter610works in the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal. For example, in the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal, during an entire switching cycle, the control signal784is used to make the switch854(e.g., SB) closed for only a predetermined minimum duration. As an example, in the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal, the output voltage614is determined as follows:

VOUT=tAC+tADtBD⁡(min)+tAD×VIN(Equation⁢⁢5)
wherein VOUTrepresents the output voltage614, and VINrepresents the input voltage612. Additionally, tACrepresents, within one switching cycle, the time duration during which both the switch852(e.g., SA) and the switch856(e.g., SC) are closed. Moreover, tADrepresents, within one switching cycle, the time duration during which both the switch852(e.g., SA) and the switch858(e.g., SD) are closed. Also, tBD(min)represents, within one switching cycle, the time duration during which both the switch854(e.g., SB) and the switch858(e.g., SD) are closed, given that the switch854(e.g., SB) is closed for only the predetermined minimum duration during the switching cycle.

In certain examples, if the logic signal926(e.g., BST_ON) is at the logic high level and the logic signal928(e.g., BUK_ON) is also at the logic high level, regardless of whether the logic signal922(e.g., BST) is at the logic high level or at the logic low level and regardless of whether the logic signal924(e.g., BUK) is at the logic high level or at the logic low level, the DC-to-DC voltage converter610works in the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal. For example, in the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal, during an entire switching cycle, the control signal784is used to make the switch854(e.g., SB) closed for only a predetermined minimum duration and make the switch856(e.g., SC) closed for only a predetermined minimum duration. For example, if the logic signal922(e.g., BST) is at the logic high level, the logic signal924(e.g., BUK) is at the logic low level, and if the logic signal922(e.g., BST) is at the logic low level, the logic signal924(e.g., BUK) is at the logic high level. As an example, in the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal, the output voltage614is determined as follows:

VOUT=tAC⁡(min)+tADtBD⁡(min)+tAD×VIN(Equation⁢⁢6)
wherein VOUTrepresents the output voltage614, and VINrepresents the input voltage612. Additionally, tAC(min)represents, within one switching cycle, the time duration during which both the switch852(e.g., SA) and the switch856(e.g., SC) are closed, given that the switch856(e.g., SC) is closed for only the predetermined minimum duration for the switch856(e.g., SC) during the switching cycle. Moreover, tADrepresents, within one switching cycle, the time duration during which both the switch852(e.g., SA) and the switch858(e.g., SD) are closed. Also, tBD(min)represents, within one switching cycle, the time duration during which both the switch854(e.g., SB) and the switch858(e.g., SD) are closed, given that the switch854(e.g., SB) is closed for only the predetermined minimum duration for the switch854(e.g., SB) during the switching cycle. As an example, tAC(min)and tBD(min)are equal.

In certain examples, if the logic signal926(e.g., BST_ON) is at the logic high level, the logic signal924(e.g., BUK) is at the logic high level, and the logic signal922(e.g., BST) is at the logic low level, regardless of whether the logic signal928(e.g., BUK_ON) is at the logic high level or at the logic low level, the DC-to-DC voltage converter610works in the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal. For example, in the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal, during an entire switching cycle, the control signal784is used to make the switch856(e.g., SC) closed for only a predetermined minimum duration. As an example, in the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal, the output voltage614is determined as follows:

VOUT=tAC⁡(min)+tADtBD+tAD×VIN(Equation⁢⁢7)
wherein VOUTrepresents the output voltage614, and VINrepresents the input voltage612. Additionally, tAC(min)represents, within one switching cycle, the time duration during which both the switch852(e.g., SA) and the switch856(e.g., SC) are closed, given that the switch856(e.g., SC) is closed for only the predetermined minimum duration during the switching cycle. Moreover, tADrepresents, within one switching cycle, the time duration during which both the switch852(e.g., SA) and the switch858(e.g., SD) are closed. Also, tBDrepresents, within one switching cycle, the time duration during which both the switch854(e.g., SB) and the switch858(e.g., SD) are closed.

FIG.12is a simplified timing diagram showing the DC-to-DC voltage converter610as shown inFIG.7,FIG.8,FIG.9andFIG.11according to some embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The waveform1292represents the clock signal992(e.g., CLK_BST) as a function of time, the waveform1298represents the clock signal998(e.g., CLK_BUK) as a function of time, the waveform1214represents the output voltage614(e.g., VOUT) as a function of time, and the waveform1212represents the input voltage612(e.g., VIN) as a function of time. Additionally, the waveform1262represents the detection signal762(e.g., VSNS) as a function of time, the waveform1271represents the compensation voltage971(e.g., VCOMP) as a function of time, the waveform1251represents the voltage951(e.g., VSUM_BST) as a function of time, and the waveform1261represents the voltage961(e.g., VSUM_BUK) as a function of time. Moreover, the waveform1282represents the control signal782as a function of time, the waveform1284represents the control signal784as a function of time, the waveform1286represents the control signal786as a function of time, and the waveform1288represents the control signal788as a function of time. In certain embodiments, as shown by the waveforms1292and1298, the clock signal992(e.g., CLK_BST) and the clock signal998(e.g., CLK_BUK) have the same frequency but with a phase shift. For example, the phase shift is equal to a value that is larger than or equal to 120° but smaller than or equal to 240°.

According to some embodiments, from time t1to time t3, the logic signal922(e.g., BST) is at the logic high level, the logic signal924(e.g., BUK) is at the logic low level, and the logic signal928(e.g., BUK_ON) is at the logic low level, indicating that the DC-to-DC voltage converter610works in the boost mode. For example, as shown inFIG.12, mode A represents the boost mode. As an example, from time t1to time t3, the output voltage614(e.g., VOUT) is larger than the input voltage612(e.g., VIN) as shown by the waveforms1212and1214. In certain examples, at time t1, which corresponds to a rising edge of the clock signal992(e.g., CLK_BST) as shown by the waveform1292, the switch856(e.g., SC) is closed by the control signal786as shown by the waveform1286. In some examples, at time t2, the voltage951(e.g., VSUM_BST) becomes larger than the compensation voltage971(e.g., VCOMP) as shown by the waveforms1251and1271. For example, at time t2, the switch856(e.g., SC) becomes open by the control signal786as shown by the waveform1286, and also at time t2, the switch858(e.g., SD) becomes closed by the control signal788as shown by the waveform1288. As an example, from time t3to time t4, the switch858(e.g., SD) remains closed, and at time t4, the switch858(e.g., SD) becomes open by the control signal788as shown by the waveform1288.

According to certain embodiments, from time t3to time t13, the DC-to-DC voltage converter610works in the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal. For example, as shown inFIG.12, mode B represents the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal. As an example, from time t3to time t13, the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) are approximately equal (e.g., being equal, being approximately equal within ±10%, or being approximately equal within ±20%).

In some examples, at time t3, the duty cycle of the pulse-width-modulation signal912(e.g., PWM_BST) becomes smaller than 5%, the logic signal928(e.g., BUK_ON) changes from the logic low level to the logic high level, and the DC-to-DC voltage converter610enters the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal. For example, at time t3, the switch856(e.g., SC) becomes closed, and after time t3, the switch856(e.g., SC) remains closed until at least the voltage951(e.g., VSUM_BST) becomes larger than the compensation voltage971(e.g., VCOMP). As an example, if the voltage951(e.g., VSUM_BST) becomes larger than the compensation voltage971(e.g., VCOMP) when the switch856(e.g., SC) has remained closed for at least a predetermined minimum duration (e.g., tAC(min)), the switch856(e.g., SC) becomes open. For example, if the voltage951(e.g., VSUM_BST) becomes larger than the compensation voltage971(e.g., VCOMP) before the switch856(e.g., SC) has remained closed for at least the predetermined minimum duration (e.g., tAC(min)), the switch856(e.g., SC) remains closed and then becomes open when the predetermined minimum duration (e.g., tAC(min)) has been reached (e.g., at time t4). In certain examples, at time t4, the switch856(e.g., SC) is opened by the control signal786and the switch858(e.g., SD) is closed by the control signal788as shown by the waveforms1286and1288respectively.

In some examples, at time t5, which corresponds to a rising edge of the clock signal998(e.g., CLK_BUK) as shown by the waveform1298, the switch854(e.g., SB) is closed by the control signal784as shown by the waveform1284. As an example, from time t5to time t6, the switch854(e.g., SB) remines closed for a predetermined minimum duration (e.g., tBD(min)). In certain examples, at time t6, the switch854(e.g., SB) becomes open by the control signal784as shown by the waveform1284, and the switch852(e.g., SA) becomes closed by the control signal782as shown by the waveform1282.

In some examples, at time t7, which corresponds to a rising edge of the clock signal992(e.g., CLK_BST) as shown by the waveform1292, the switch856(e.g., SC) is closed by the control signal786as shown by the waveform1286. As an example, from time t7to time t8, the switch856(e.g., SC) remines closed for a predetermined minimum duration (e.g., tAC(min)). In certain examples, at time t8, the switch856(e.g., SC) becomes open by the control signal786as shown by the waveform1286, and the switch858(e.g., SD) becomes closed by the control signal788as shown by the waveform1288.

In some examples, at time t9, which corresponds to a rising edge of the clock signal998(e.g., CLK_BUK) as shown by the waveform1298, the switch854(e.g., SB) is closed by the control signal784as shown by the waveform1284. As an example, from time t9to time t10, the switch854(e.g., SB) remines closed for a predetermined minimum duration (e.g., tBD(min)). In certain examples, at time t10, the switch854(e.g., SB) becomes open by the control signal784as shown by the waveform1284, and the switch852(e.g., SA) becomes closed by the control signal782as shown by the waveform1282.

In some examples, at time t11, which corresponds to a rising edge of the clock signal992(e.g., CLK_BST) as shown by the waveform1292, the switch856(e.g., SC) is closed by the control signal786as shown by the waveform1286. As an example, from time t11to time t12, the switch856(e.g., SC) remines closed for a predetermined minimum duration (e.g., tAC(min)). In certain examples, at time t12, the switch856(e.g., SC) becomes open by the control signal786as shown by the waveform1286, and the switch858(e.g., SD) becomes closed by the control signal788as shown by the waveform1288.

According to some embodiments, from time t13to time t15, the logic signal922(e.g., BST) is at the logic low level, the logic signal924(e.g., BUK) is at the logic high level, and the logic signal926(e.g., BST_ON) is at the logic low level, indicating that the DC-to-DC voltage converter610works in the buck mode. For example, as shown inFIG.12, mode C represents the boost mode. As an example, from time t13to time t15, the output voltage614(e.g., VOUT) is larger than the input voltage612(e.g., VIN) as shown by the waveforms1212and1214. In certain examples, at time t13, which corresponds to a rising edge of the clock signal998(e.g., CLK_BUK) as shown by the waveform1298, the switch854(e.g., SB) is closed by the control signal784as shown by the waveform1284. For example, at time t13, the duty cycle of the pulse-width-modulation signal914(e.g., PWM_BUK) becomes larger than 5%, the logic signal926(e.g., BST_ON) changes from the logic high level to the logic low level, and the DC-to-DC voltage converter610enters the buck mode. In some examples, at time t14, the voltage961(e.g., VSUM_BUK) becomes smaller than the compensation voltage971(e.g., VCOMP) as shown by the waveforms1261and1271. For example, at time t14, the switch854(e.g., SB) becomes open by the control signal784as shown by the waveform1284, and also at time t14, the switch852(e.g., SA) becomes closed by the control signal782as shown by the waveform1282. As an example, from time t14to time t15, the switch852(e.g., SA) remains closed. In certain examples, at time t15, which corresponds to a rising edge of the clock signal998(e.g., CLK_BUK) as shown by the waveform1298, the switch852(e.g., SA) becomes open by the control signal782.

As discussed above and further emphasized here,FIG.12is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the timing diagram shows that the DC-to-DC voltage converter610changes from the boost made to the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal and then changes to the buck mode. As an example, the timing diagram shows that the DC-to-DC voltage converter610changes from the buck made to the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal and then changes to the boost mode.

FIG.13is a simplified timing diagram showing the DC-to-DC voltage converter610as shown inFIG.7,FIG.8,FIG.9andFIG.11according to certain embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The waveform1312represents the input voltage612(e.g., VIN) as a function of time, and the waveform1314represents the output voltage614(e.g., VOUT) as a function of time. Additionally, the waveform1332represents a voltage at the node832(e.g., SW1) as a function of time, and the waveform1334represents a voltage at the node834(e.g., SW2) as a function of time. Moreover, the waveform1336represents the coil current836(e.g., IL) as a function of time.

In some embodiments, as shown inFIG.14, mode X represents the buck mode, mode Y represents the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal, and mode Z represents the boost mode. For example, the DC-to-DC voltage converter610changes from the buck mode to the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal, changes from the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal to the boost mode, changes from the boost mode to the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal, changes from the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal to the buck mode. In certain embodiments, the DC-to-DC voltage converter610is in compliance with USB Power Delivery (USB PD) according to some embodiments. For example, the input voltage612(e.g., VIN) remains at 12 volts as shown by the waveform1312. As an example, the output voltage614(e.g., VOUT) is equal to 5 volts, 9 volts, 15 volts, or 20 volts as shown by the waveform1314, with a load current of 5 amps.

FIG.14is a simplified timing diagram showing the DC-to-DC voltage converter610as shown inFIG.7,FIG.8,FIG.9andFIG.11according to some embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The waveform1412represents the input voltage612(e.g., VIN) as a function of time, and the waveform1414represents the output voltage614(e.g., VOUT) as a function of time. Additionally, the waveform1432represents a voltage at the node832(e.g., SW1) as a function of time, and the waveform1434represents a voltage at the node834(e.g., SW2) as a function of time. Moreover, the waveform1436represents the coil current836(e.g., IL) as a function of time.

In some embodiments, as shown inFIG.15, mode J represents the boost mode, mode K represents the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal, and mode L represents the buck mode. For example, the DC-to-DC voltage converter610changes from the boost mode to the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal, changes from the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal to the buck mode, changes from the buck mode to the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal, changes from the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal to the boost mode. In certain embodiments, the DC-to-DC voltage converter610is used for power supply in an automobile according to some embodiments. For example, the input voltage612(e.g., VIN) changes between 4 volts and 36 volts as shown by the waveform1412. As an example, the output voltage614(e.g., VOUT) remains at 12 volts as shown by the waveform1414, with a load current of 5 amps. In certain embodiments, the DC-to-DC voltage converter610changes from the boost mode to the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal, changes from the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal to the buck mode, changes from the buck mode to the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal, changes from the mode for the input voltage612(e.g., VIN) and the output voltage614(e.g., VOUT) being approximately equal to the boost mode.

FIG.15is a simplified diagram showing certain components of the DC-to-DC voltage converter610as shown inFIG.7according to some embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As an example, the switch network750includes the input terminal792and the output terminal794, and also includes a switch1552, a switch1554, a switch1556, and a switch1558. For example, the current detector760includes a current sensing resistor1560and a current sampling amplifier1570. Although the above has been shown using a selected group of components for the DC-to-DC voltage converter610, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. Further details of these components are found throughout the present specification.

According to certain embodiments, the switch1552(e.g., SA), the current sensing resistor1560, the coil730, and the switch1558(e.g., SD) are connected in series. In some examples, one terminal of the switch1552(e.g., SA) is connected to the input terminal792that receives the input voltage612(e.g., VIN), and another terminal of the switch1552(e.g., SA) is connected to one terminal of the current sensing resistor1560and one terminal of the switch1554(e.g., SB) through a node1532(e.g., SW1). For example, another terminal of the switch1554(e.g., SB) is biased to the ground voltage. In certain examples, one terminal of the switch1558(e.g., SD) is connected to the output terminal794that outputs the output voltage614(e.g., VOUT), and another terminal of the switch1558(e.g., SD) is connected to one terminal of the coil730and one terminal of the switch1556(e.g., SC) through a node1534(e.g., SW2). As an example, another terminal of the switch1556(e.g., SC) is biased to the ground voltage. For example, another terminal of the coil730is connected to another terminal of the current sensing resistor1560. In some examples, a coil current1536(e.g., IL) flows through the coil730as shown inFIG.15. For example, the current sensing resistor1560allows the coil current1536(e.g., IL) to flow through the current sensing resistor1560.

According to some embodiments, the control signal782is used to close or open the switch1552(e.g., SA), the control signal784is used to close or open the switch1554(e.g., SB), the control signal786is used to close or open the switch1556(e.g., SC), and the control signal788is used to close or open the switch1558(e.g., SD). For example, under certain condition, both the switch1552(e.g., SA) and the switch1558(e.g., SD) are closed, so that a current flows from the input terminal792to the output terminal794through the switch1552(e.g., SA), the current sensing resistor1560, the coil730, and the switch1558(e.g., SD). As an example, allowing both the switch1552(e.g., SA) and the switch1558(e.g., SD) to be closed at the same time reduces the average magnitude of the coil current1536(e.g., IL) that flows through the coil730and also lowers the conduction loss.

In some embodiments, the current sampling amplifier1570(e.g., ACS) includes an input terminal1572, an input terminal1574, and an output terminal1576. For example, the input terminal1572is connected to one terminal of the current sensing resistor1560, and the input terminal1574is connected to another terminal of the current sensing resistor1560. As an example, the output terminal1576outputs the detection signal762.

In certain embodiments, the current sensing resistor1560converts the coil current1536(e.g., IL), which flows through the coil730, to a voltage difference across the current sensing resistor1560. For example, the voltage difference across the current sensing resistor1560is equal to a voltage difference between the input terminal1572and the input terminal1574. As an example, the voltage difference between the input terminal1572and the input terminal1574is used by the current sampling amplifier1570(e.g., ACS) to generate the detection signal762at the output terminal1576.

According to some embodiments, the detection signal762represents an amplified magnitude of the coil current1536during multiple switching cycles. For example, the detection signal762(e.g., VSNS) represents the amplified magnitude of the coil current1536during one switching cycle, and then the detection signal762(e.g., VSNS) represents the amplified magnitude of the coil current1536during another entire switching cycle. As an example, each switching cycle includes one half switching cycle during which both the switch1552(e.g., SA) and the switch1556(e.g., SC) are closed and both the switch1554(e.g., SB) and the switch1558(e.g., SD) are open, and also includes another half switching cycle during which both the switch1552(e.g., SA) and the switch1556(e.g., SC) are open and both the switch1554(e.g., SB) and the switch1558(e.g., SD) are closed.

As discussed above,FIG.15is a simplified diagram showing certain components of the DC-to-DC voltage converter610as shown inFIG.7according to some embodiments of the present invention. For example, the DC-to-DC voltage converter610as shown inFIG.7includes certain components as shown inFIG.15and also certain components of the voltage controller770as shown inFIG.9and/orFIG.11.

FIG.16is a simplified diagram showing certain components of the DC-to-DC voltage converter610as shown inFIG.7according to certain embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As an example, the switch network750includes the input terminal792and the output terminal794, and also includes a switch1652, a switch1654, a switch1656, and a switch1658. For example, the current detector760includes a current sensing resistor1660and a current sampling amplifier1670. Although the above has been shown using a selected group of components for the DC-to-DC voltage converter610, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. Further details of these components are found throughout the present specification.

According to some embodiments, the switch1652(e.g., SA), the coil730, and the switch1658(e.g., SD) are connected in series. In some examples, one terminal of the switch1652(e.g., SA) is connected to the input terminal792that receives the input voltage612(e.g., VIN), and another terminal of the switch1652(e.g., SA) is connected to one terminal of the coil730and one terminal of the switch1654(e.g., SB) through a node1632(e.g., SW1). In certain examples, one terminal of the switch1658(e.g., SD) is connected to the output terminal794that outputs the output voltage614(e.g., VOUT), and another terminal of the switch1658(e.g., SD) is connected to another terminal of the coil730and one terminal of the switch1656(e.g., SC) through a node1634(e.g., SW2). In some examples, a coil current1636(e.g., IL) flows through the coil730as shown inFIG.16. For example, the current sensing resistor1660allows the coil current1636(e.g., IL) to flow through the current sensing resistor1660.

In certain embodiments, the current sampling amplifier1670(e.g., ACS) includes an input terminal1672, an input terminal1674, and an output terminal1676. For example, another terminal of the switch1654(e.g., SB) and another terminal of the switch1656(e.g., SC) are connected to the input terminal1672of the current sampling amplifier1670(e.g., ACS) and one terminal of the current sensing resistor1660. As an example, another terminal of the current sensing resistor1660is connected to the input terminal1674of the current sampling amplifier1670(e.g., ACS) and is biased to the ground voltage. In certain examples, the output terminal1676of the current sampling amplifier1670(e.g., ACS) outputs the detection signal762.

In some embodiments, the control signal782is used to close or open the switch1652(e.g., SA), the control signal784is used to close or open the switch1654(e.g., SB), the control signal786is used to close or open the switch1656(e.g., SC), and the control signal788is used to close or open the switch1658(e.g., SD). For example, both the switch1652(e.g., SA) and the switch1656(e.g., SC) are closed and both the switch1654(e.g., SB) and the switch1658(e.g., SD) are open. As an example, both the switch1652(e.g., SA) and the switch1656(e.g., SC) are open and both the switch1654(e.g., SB) and the switch1658(e.g., SD) are closed.

According to certain embodiments, the detection signal762represents an amplified magnitude of the coil current1636during multiple half switching cycles. For example, the detection signal762(e.g., VSNS_BST) represents the amplified magnitude of the coil current1636during one half switching cycle, and then the detection signal762(e.g., VSNS_BUK) represents the amplified magnitude of the coil current1636during another half switching cycle. As an example, the one half switching cycle corresponds to a time duration during which both the switch1652(e.g., SA) and the switch1656(e.g., SC) are closed and both the switch1654(e.g., SB) and the switch1658(e.g., SD) are open, and the another half switching cycle corresponds to a time duration during which both the switch1652(e.g., SA) and the switch1656(e.g., SC) are open and both the switch1654(e.g., SB) and the switch1658(e.g., SD) are closed.

As discussed above,FIG.16is a simplified diagram showing certain components of the DC-to-DC voltage converter610as shown inFIG.7according to some embodiments of the present invention. For example, the DC-to-DC voltage converter610as shown inFIG.7includes certain components as shown inFIG.16and also certain components of the voltage controller770as shown inFIG.9and/orFIG.11.

FIG.17is a simplified diagram showing certain components of the DC-to-DC voltage converter610as shown inFIG.7according to some embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. As an example, the switch network750includes the input terminal792and the output terminal794, and also includes a switch1752, a switch1754, a switch1756, and a switch1758. For example, the current detector760includes current sensing resistors1760and1762and current sampling amplifiers1770and1780. Although the above has been shown using a selected group of components for the DC-to-DC voltage converter610, there can be many alternatives, modifications, and variations. For example, some of the components may be expanded and/or combined. Other components may be inserted to those noted above. Depending upon the embodiment, the arrangement of components may be interchanged with others replaced. Further details of these components are found throughout the present specification.

According to certain embodiments, the current sampling amplifier1770includes an input terminal1772, an input terminal1774, and an output terminal1776, and the current sampling amplifier1780includes an input terminal1782, an input terminal1784, and an output terminal1786. For example, the output terminal1776outputs a detection signal1790(e.g., VSNS1), and the output terminal1786outputs a detection signal1792(e.g., VSNS2). As an example, the detection signal762includes the detection signal1790(e.g., VSNS1) and the detection signal1792(e.g., VSNS2).

According to some embodiments, the current sensing resistor1760, the switch1752(e.g., SA), the coil730, the switch1758(e.g., SD), and the current sensing resistor1762are connected in series. In some examples, one terminal of the current sensing resistor1760is connected to the input terminal1772of the current sampling amplifier1770and the input terminal792that receives the input voltage612(e.g., VIN), and another terminal of the current sensing resistor1760is connected to the input terminal1774of the current sampling amplifier1770and one terminal of the switch1752(e.g., SA). For example, another terminal of the switch1752(e.g., SA) is connected to one terminal of the coil730and one terminal of the switch1754(e.g., SB) through a node1732(e.g., SW1). As an example, another terminal of the switch1754(e.g., SB) is biased to the ground voltage. In certain examples, one terminal of the current sensing resistor1762is connected to the input terminal1784of the current sampling amplifier1780and the output terminal794that outputs the output voltage614(e.g., VOUT), and another terminal of the current sensing resistor1762is connected to the input terminal1782of the current sampling amplifier1780and one terminal of the switch1758(e.g., SD). For example, another terminal of the switch1758(e.g., SD) is connected to another terminal of the coil730and one terminal of the switch1756(e.g., SC) through a node1734(e.g., SW2). As an example, another terminal of the switch1756(e.g., SC) is biased to the ground voltage. In some examples, a coil current1736(e.g., IL) flows through the coil730as shown inFIG.17. For example, the current sensing resistor1760and/or the current sensing resistor1762allow the coil current1736(e.g., IL) to flow through the current sensing resistor1760and/or the current sensing resistor1762.

In certain embodiments, the control signal782is used to close or open the switch1752(e.g., SA), the control signal784is used to close or open the switch1754(e.g., SB), the control signal786is used to close or open the switch1756(e.g., SC), and the control signal788is used to close or open the switch1758(e.g., SD). For example, under certain condition, both the switch1752(e.g., SA) and the switch1758(e.g., SD) are closed, so that a current flows from the input terminal792to the output terminal794through the current sensing resistor1760, the switch1752(e.g., SA), the coil730, the switch1758(e.g., SD), and the current sensing resistor1762. As an example, allowing both the switch1752(e.g., SA) and the switch1758(e.g., SD) to be closed at the same time reduces the average magnitude of the coil current1736(e.g., IL) that flows through the coil730and also lowers the conduction loss.

As discussed above and further emphasized here,FIG.9is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. In certain examples, the modulation signal generator910receives the output voltage614(e.g., VOUT) and the detection signal762, which includes the detection signal1790(e.g., VSNS1) and the detection signal1792(e.g., VSNS2), and the modulation signal generator910generates the pulse-width-modulation signal912for the boost mode (e.g., PWM_BST) and the pulse-width-modulation signal914for the buck mode (e.g., PWM_BUK). For example, the voltage adder980receives the detection signal1790(e.g., VSNS1) and the signal981(e.g., SLOPE_BST) and generates the voltage951(e.g., VSUM_BST) by adding the detection signal1790(e.g., VSNS1) and the signal981(e.g., SLOPE_BST). As an example, the voltage subtractor982receives the detection signal1792(e.g., VSNS2) and the signal983(e.g., SLOPE_BUK) and generates the voltage961(e.g., VSUM_BUK) by subtracting the signal983(e.g., SLOPE_BUK) from the detection signal1792(e.g., VSNS2).

As discussed above,FIG.17is a simplified diagram showing certain components of the DC-to-DC voltage converter610as shown inFIG.7according to some embodiments of the present invention. For example, the DC-to-DC voltage converter610as shown inFIG.7includes certain components as shown inFIG.17and also certain components of the voltage controller770as shown inFIG.9and/orFIG.11.

According to some embodiments, a voltage converter for converting an input voltage to an output voltage includes: a coil; multiple switches including one or more switches connected to the coil; a modulation signal generator configured to: receive the output voltage and one or more detection signals indicating a magnitude of a coil current flowing through the coil; and generate a first signal and a second signal based at least in part upon the output voltage and the one or more detection signals; and an operation mode controller configured to: receive the input voltage, the output voltage, the first signal, and the second signal; and generate one or more mode signals based at least in part upon the input voltage, the output voltage, the first signal, and the second signal; wherein the one or more mode signals indicate that the voltage converter operates in an operation mode selected from multiple operation modes. For example, the voltage converter is implemented according to at leastFIG.7and/orFIG.9.

As an example, the voltage converter further includes: a control signal generator configured to: receive the one or more mode signals; and generate multiple control signals based at least in part on the one or more mode signals; wherein the multiple control signals correspond to the operation mode selected from the multiple operation modes. For example, the multiple switches are configured to receive the multiple control signals to open or close each switch of the multiple switches. As an example, the input voltage is a first DC voltage; and the output voltage is a second DC voltage; wherein the first DC voltage and the second DC voltage are equal or not equal. For example, the voltage converter further includes: a current detector including one or more resistors and one or more amplifiers; wherein: the one or more resistors are configured to allow the coil current to flow through the one or more resistors; and the one or more amplifiers are coupled to the one or more resistors and configured to generate the one or more detection signals indicating the magnitude of the coil current.

As an example, The voltage converter of claim1wherein the multiple operation modes includes a first operation mode, a second operation mode, and a third operation mode. For example, the first operation mode is a boost mode; wherein in the boost mode, the output voltage is larger than the input voltage. As an example, the second operation mode is a buck mode; wherein in the buck mode, the output voltage is smaller than the input voltage. For example, in the third operation mode, the input voltage and the output voltage are approximately equal. As an example, in the third operation mode, the input voltage and the output voltage are equal.

For example, the modulation signal generator includes: a voltage adder configured to receive a first detection signal of the one or more detection signals and generate a first processed signal; and a voltage subtractor configured to receive a second detection signal of the one or more detection signals and generate a second processed signal. As an example, the one or more detection signals consist of one detection signal; and the first detection signal and the second detection signal are the same signal. For example, the one or more detection signals include two detection signals; and the first detection signal and the second detection signal are different signals. As an example, the modulation signal generator is further configured to generate the first signal and the second signal based at least in part upon the first processed signal and the second processed signal. For example, each signal of the first signal and the second signal is a pulse-width-modulation signal.

As an example, the one or more mode signals include a first mode signal, a second mode signal, a third mode signal, and a fourth mode signal; wherein each mode signal of the first mode signal, the second mode signal, the third mode signal, and the fourth mode signal is at a logic high level or a logic low level. For example, if the first mode signal is at the logic high level, the second mode signal is at the logic low level; and if the first mode signal is at the logic low level, the second mode signal is at the logic high level. As an example, the voltage converter of claim16wherein the operation mode controller is further configured to: determine a voltage ratio of the input voltage to the output voltage; and generate the first mode signal and the second mode signal based at least in part upon the voltage ratio. For example, the first signal is associated with a first duty cycle; and the operation mode controller is further configured to generate the third mode signal based at least in part upon the first duty cycle of the first signal. As an example, the second signal is associated with a second duty cycle; and the operation mode controller is further configured to generate the fourth mode signal based at least in part upon the second duty cycle of the second signal.

According to certain embodiments, a method for converting an input voltage to an output voltage, the method comprising: receiving the output voltage and one or more detection signals indicating a magnitude of a coil current flowing through a coil connected to one or more switches of multiple switches; generating a first signal and a second signal based at least in part upon the output voltage and the one or more detection signals; receiving the input voltage, the output voltage, the first signal, and the second signal; and generating one or more mode signals based at least in part upon the input voltage, the output voltage, the first signal, and the second signal; wherein the one or more mode signals indicate that the voltage converter operates in an operation mode selected from multiple operation modes. For example, the method is implemented according to at leastFIG.7and/orFIG.9.

As an example, the method further includes: receiving the one or more mode signals; and generating multiple control signals based at least in part on the one or more mode signals; wherein the multiple control signals correspond to the operation mode selected from the multiple operation modes. For example, the method further includes receiving the multiple control signals by the multiple switches to open or close each switch of the multiple switches.

As an example, the multiple operation modes includes a first operation mode, a second operation mode, and a third operation mode. For example, the first operation mode is a boost mode; wherein in the boost mode, the output voltage is larger than the input voltage. As an example, the second operation mode is a buck mode; wherein in the buck mode, the output voltage is smaller than the input voltage. For example, in the third operation mode, the input voltage and the output voltage are approximately equal. As an example, in the third operation mode, the input voltage and the output voltage are equal.

For example, the one or more mode signals include a first mode signal, a second mode signal, a third mode signal, and a fourth mode signal; wherein each mode signal of the first mode signal, the second mode signal, the third mode signal, and the fourth mode signal is at a logic high level or a logic low level. As an example, if the first mode signal is at the logic high level, the second mode signal is at the logic low level; and if the first mode signal is at the logic low level, the second mode signal is at the logic high level. For example, the generating one or more mode signals based at least in part upon the input voltage, the output voltage, the first signal, and the second signal includes: determining a voltage ratio of the input voltage to the output voltage; and generating the first mode signal and the second mode signal based at least in part upon the voltage ratio. As an example, the first signal is associated with a first duty cycle; and the generating one or more mode signals based at least in part upon the input voltage, the output voltage, the first signal, and the second signal includes generating the third mode signal based at least in part upon the first duty cycle of the first signal. For example, the second signal is associated with a second duty cycle; and the generating one or more mode signals based at least in part upon the input voltage, the output voltage, the first signal, and the second signal further includes generating the fourth mode signal based at least in part upon the second duty cycle of the second signal.

For example, some or all components of various embodiments of the present invention each are, individually and/or in combination with at least another component, implemented using one or more software components, one or more hardware components, and/or one or more combinations of software and hardware components. As an example, some or all components of various embodiments of the present invention each are, individually and/or in combination with at least another component, implemented in one or more circuits, such as one or more analog circuits and/or one or more digital circuits. For example, various embodiments and/or examples of the present invention can be combined.

Although specific embodiments of the present invention have been described, it will be understood by those of skill in the art that there are other embodiments that are equivalent to the described embodiments. Accordingly, it is to be understood that the invention is not to be limited by the specific illustrated embodiments.