Patent ID: 12249642

Elements that are the same or equivalent in the various figures may be labeled with the same numeral.

DETAILED DESCRIPTION

Although the techniques of the present invention can be used for various applications, a few examples will be given with reference to the type of device shown inFIG.1. The invention also applies to IGBTs, where the trenches (and gates) extend below the p-well so there is a conductive inversion path between the top n+ source regions and the n-epi region when the gates are biased on. Silicon is assumed as the semiconductor material, but other semiconductor materials may be used.

FIG.4is a top down view of a small area of a vertical power device, such as a device similar toFIG.1or an IGBT, where the opening40in the dielectric26(FIG.1) to expose a p-type contact region42(p or p+ type) for the p-well14(FIG.1) and an opening44to expose the n+ source region46, for an emitter-to-base short, does not result in the p-type contact region42abutting the n+ source region46. The p-type contact region42may also be referred to as a well contact region. The source region46is also considered a source region layer since it is an implanted layer across the device. The openings in the dielectric26are made using a patterned etch step.

FIG.5is taken across line5-5inFIG.4and shows a cross-section of cells where the dielectric26in area48(between two closely-spaced gates12) is opened, and the dielectric26in area50is opened so that the cathode electrode20directly contacts the p-type contact region42and the n+ source region46to form distributed weak emitter-to-base shorts across the cellular array. Importantly, the exposed p-type contact region42does not abut the n+ source region46so is electrically isolated prior to the formation of the cathode electrode20. The two gates12sandwiching the p-type contact region42are close together, resulting in a fairly insignificant reduction in the n+ source region area. Therefore, current density is not significantly affected by the distributed emitter-to-base shorting.

FIG.6illustrates a deep p+ area52under each gate12, such as by using ion implantation prior to the trenches being filled with polysilicon. This deep p+ area52decreases the series resistance between the top surface of the p-type contact region42and the p-well14areas directly below the n+ source regions46, for a more uniform emitter-to-base short across the cellular array and to reduce the effects of lateral current flow.

FIG.7is similar toFIG.6but illustrates how the p-type contact regions42can be p+, such as by ion implantation through the opening in the dielectric26.FIG.7also illustrates a deeper p+ area54below the p-type contact region42.

The deep p+ areas52and54, in addition to the benefit described with respect toFIG.6, provide a uniform implanted p-type charge between the trench bottoms and the p-n junction. Without the extra implant, the p-type charge between the bottom of the trenches and the n-epi layer32is highly dependent on the depth of the trenches and the exact depth of the p-n junction. The trench depth and the depth of the p-n junction vary from lot to lot, but the implant used to form the deep p+ areas52and54is highly repeatable. This feature results in more consistent performance of the devices from lot to lot.

The deep p+ areas52and54also prevent the depletion region (when the device is off) from spreading as great a distance, compared to the distance had the p+ areas52and54not been present.

InFIGS.4-7, the p-type contact region42is surrounded by the polysilicon gate12, reducing lateral current effects.

FIG.8is a top down view of a vertical power device where the n+ source regions46(implanted regions) are formed as strips, and the small p-type contact regions42(for emitter-to-base shorting) are distributed between the strips for a fairly uniform emitter-to-base short across the cellular array. The strips are connected in parallel by the top cathode electrode. The openings in the dielectric, within the dashed outlines inFIG.8, preferably expose a vast majority of the areas of the n+ source regions46for the best device performance.

FIG.9is taken along line9-9inFIG.8and shows how the exposed p-type contact regions42are very small compared to the exposed n+ source regions46. This results in very little area of the n+ source being sacrificed for the p-type contact regions42, maximizing the current density when the device is turned on.

FIG.10is similar toFIG.9but the p-type contact region42is p+ and deeper, as inFIG.7.

FIG.11is a top down view of a vertical power device where the p-type contact regions42are formed as strips perpendicular to the n+ source region46strips for relatively uniform shorting across the cellular array. The p-type contact region strips can be made much narrower than the n+ source region strips.

FIG.12is taken across line12-12inFIG.11, where no p-type contact regions42are located.

FIG.13is taken across line13-13inFIG.11, where only the p-type contact regions42and gates12are located.

FIG.14is also taken across line13-13inFIG.11but shows deep p+ contact regions42.

FIG.15is taken across line15-15inFIG.11, where p-type contact regions42and n+ source regions46are located.

FIG.16is also taken across line15-15inFIG.11but shows deep p+ contact regions42.

The various regions may be formed as strips, squares, hexagons, or other shapes. The conductivities of all layers and regions may be reversed.

Various features disclosed may be combined to achieve a desired result.

While particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from this invention in its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications as fall within the true spirit and scope of this invention.