Patent ID: 12211848

While the embodiments described herein are amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the particular embodiments described are not to be taken in a limiting sense. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

DETAILED DESCRIPTION

Embodiments of the present invention are generally directed to gate-all-around field effect transistors (GAAFETs) co-integrating a matrix of nanowires or nanosheet channels with bottom dielectric isolation and self-aligned gate cut and methods of fabricating the same. While the present disclosure is not necessarily limited to such applications, various aspects of the disclosure may be appreciated through a discussion of various examples using this context.

Various embodiments of the present disclosure are described herein with reference to the related drawings, where like numbers refer to the same component. Alternative embodiments can be devised without departing from the scope of the present disclosure. It is noted that various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings. These connections and/or positional relationships, unless specified otherwise, can be direct or indirect, and the present disclosure is not intended to be limiting in this respect. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, references in the present description to forming layer “A” over layer “B” include situations in which one or more intermediate layers (e.g., layer “C”) is between layer “A” and layer “B” as long as the relevant characteristics and functionalities of layer “A” and layer “B” are not substantially changed by the intermediate layer(s).

The following definitions and abbreviations are to be used for the interpretation of the claims and the specification. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains” or “containing,” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

For purposes of the description hereinafter, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and derivatives thereof shall relate to the described structures and methods, as oriented in the drawing figures. The terms “overlying,” “atop,” “on top,” “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements such as an interface structure can be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements. It should be noted, the term “selective to,” such as, for example, “a first element selective to a second element,” means that a first element can be etched, and the second element can act as an etch stop.

As used herein, the articles “a” and “an” preceding an element or component are intended to be nonrestrictive regarding the number of instances (i.e. occurrences) of the element or component. Therefore, “a” or “an” should be read to include one or at least one, and the singular word form of the element or component also includes the plural unless the number is obviously meant to be singular.

As used herein, the terms “invention” or “present invention” are non-limiting terms and not intended to refer to any single aspect of the particular invention but encompass all possible aspects as described in the specification and the claims.

The terms “about,” “substantially,” “approximately,” “slightly less than,” and variations thereof, are intended to include the degree of error associated with measurement of the particular quantity based upon the equipment available at the time of filing the application. For example, “about” can include a range of ±8% or 5%, or 2% of a given value.

For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details.

It should also be understood that material compounds will be described in terms of listed elements, e.g., SiN, or SiGe. These compounds include different proportions of the elements within the compound, e.g., SiGe includes SixGe(1-x)where x is less than or equal to 1, and the like. In addition, other elements can be included in the compound and still function in accordance with the present principles. The compounds with additional elements will be referred to herein as alloys.

It should be noted that not all masking, patterning, and lithography processes are shown because a person of ordinary skill in the art would recognize where masking and patterning processes are utilized to form the identified layers and openings, and to perform the identified selective etching processes, as described herein.

In general, the various processes used to form a micro-chip that will be packaged into an IC fall into four general categories, namely, film deposition, removal/etching, semiconductor doping and patterning/lithography.

Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others. Another deposition technology is plasma enhanced chemical vapor deposition (PECVD), which is a process which uses the energy within the plasma to induce reactions at the wafer surface that would otherwise require higher temperatures associated with conventional CVD. Energetic ion bombardment during PECVD deposition can also improve the film's electrical and mechanical properties.

Removal/etching is any process that removes material from the wafer. Examples include etch processes (either wet or dry), chemical-mechanical planarization (CMP), and the like. One example of a removal process is ion beam etching (IBE). In general, IBE (or milling) refers to a dry plasma etch method which utilizes a remote broad beam ion/plasma source to remove substrate material by physical inert gas and/or chemical reactive gas means. Like other dry plasma etch techniques, IBE has benefits such as etch rate, anisotropy, selectivity, uniformity, aspect ratio, and minimization of substrate damage. Another example of a dry removal process is reactive ion etching (RIE). In general, RIE uses chemically reactive plasma to remove material deposited on wafers. With RIE the plasma is generated under low pressure (vacuum) by an electromagnetic field. High-energy ions from the RIE plasma attack the wafer surface and react with it to remove material.

Semiconductor doping is the modification of electrical properties by doping, for example, transistor sources and drains, generally by diffusion and/or by ion implantation. These doping processes are followed by furnace annealing or by rapid thermal annealing (“RTA”). Annealing serves to activate the implanted dopants. Films of both conductors (e.g., poly-silicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various regions of the semiconductor substrate allows the conductivity of the substrate to be changed with the application of voltage. By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuitry of a modern microelectronic device.

Semiconductor lithography is the formation of three-dimensional relief images or patterns on the semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the patterns are formed by a light sensitive polymer called a photo-resist. To build the complex structures that make up a transistor and the many wires that connect the millions of transistors of a circuit, lithography and etch pattern transfer steps are repeated multiple times. Each pattern being printed on the wafer is aligned to the previously formed patterns and gradually the conductors, insulators and selectively doped regions are built up to form the final device.

Turning now to an overview of technologies that are more specifically relevant to aspects of the present disclosure, in general, a gate-all-around (GAA) FET, abbreviated GAAFET, and also known as a surrounding-gate transistor (SGT), is similar in concept to a FinFET except that the gate material surrounds the channel region on all sides. GAAFETs may, in some circumstances, include a nanowire/nanosheet structure. Some GAAFETs are vertically aligned, with a bottom source/drain disposed below the nanowire and/or nanosheets (e.g., between the nanowires and the substrate) and a top source/drain disposed on the top of the nanowires (opposite the bottom source/drain). Other GAAFETs may be horizontally aligned (e.g., a horizontal-transport GAAFET), where the current travels from the source to the drain in a horizontal direction.

GAAFETs can be used in high performance applications in complementary metal-oxide-semiconductor (CMOS) technology. Metal gates for the GAAFETs may be disposed on the sides of the nanowires, with a thin insulating dielectric material sitting between the gate and the nanowires. The thin insulating dielectric layer is typically made from silicon oxide, silicon nitride, or high K dielectric materials, such as Al2O3, HfO2, ZrO2or a combination of these, deposited by chemical vapor deposition (CVD), for example.

There are several power performance area (PPA) requirements for nanosheet technology that currently limit usefulness of nanosheets. For example, bottom dielectric isolation (BDI) of the source and drain epitaxy from the substrate is required for optimal electrical performances at 12 nm effective gate lengths (Lmetal). Additionally, N-P boundary scaling for current and future nodes is needed. Work function metal (WFM) patterning is encountering limitation in sub-50 nm N-P space due to patterning edge placement error (EPE) and work function metal recess between N and P devices. Further scaling will require a self-align gate cut process (SAGC) with a self-aligned dielectric layer formed at the N-P boundary. Furthermore, optimal channel electrostatic for 12 nm Lmetal is accessible for sheet width (Wsheet)<25 nm (nanoellipses). Above 25 nm nanosheet width, the channels transition from a true GAA electrostatic regime into a dual-gate regime where the electrostatic control can be degraded. However limiting the width of the sheets to 25 nm also limits the drive current capability of the device, requiring more nanosheets to compensate. Hence, there is a need for a GAAFET device structure delivering: (1) optimal electrostatic control over the channel (sheet width≤25 nm); (2) large effective width for maximum effective width per foot print; (3) Bottom Dielectric Isolation to enable aggressively scaled effective gate length (Lmetal=12 nm) and (iv) self-aligned gate cut to enable aggressive N-P boundary scaling.

Embodiments of the present disclosure may address the PPA requirement above for current and future GAA nodes. This is accomplished through a new type of GAAFET using a matrix of nanowires or nanosheet as the channel region. In some embodiments, individual devices of P and N polarities are formed by a nanosheet matrix of at least 2×1 channels for each polarity sitting above a shared dielectric isolation region. Horizontal and vertical spaces between consecutive nanowires are similar (e.g., within 1-2 nm variation). A vertical dielectric pillar is formed in-between the P and N devices in both the gate regions and source-drain regions. The vertical dielectric pillar is formed at approximately equidistance from the P and N channels and is in contact with the pWFM, the nWFM, and the bottom dielectric isolation of both P and N devices. In some embodiments, the final structure can have an uneven bottom dielectric isolation layer from fin formation.

Some embodiments of the present disclosure include a method of forming the GAAFET with a matrix of nanowires or nanosheet as the channel region. The method may comprise forming nanosheet (NS) stack epitaxy with additional sacrificial high-Ge % SiGe layer. The method may further comprise patterning fins with fin-fin space approximately identical to NS-NS vertical space along with larger spaced regions between N and P devices. The method may further comprise etching fins and stop etching in sacrificial high-Ge % SiGe layer. The method may further comprise forming a sacrificial low-Ge % SiGe layer epitaxy between the fins.

After forming the sacrificial low-Ge % SiGe layer, the method may comprise etching vertically into the substrate in regions where the low-Ge % SiGe layer is unmerged. The method may further comprise forming a dielectric pillar in the N-P space. The method may further comprise forming STI on the substrate at the edges of the N and P regions. The method may further comprise forming dummy gates and hard masks above the Si nanowires made from the nanosheets.

After forming the dummy gates, the method may comprise removing selectively high-Ge % SiGe layer between the dummy gates and forming simultaneously a gate spacer and bottom dielectric isolation layer. Inner spaces may also be formed. Fins may be recessed and self-aligned to the gates. The method may further comprise forming p-type doped field effect transistor (pFET) and n-type doped field effect transistor (nFET) epitaxy contacts sequentially. Inter-layer dielectric may be deposited and planarized. The dummy gates and low-Ge % SiGe layers may then be removed. pFET and nFET WFM (also referred to herein as pWFM and nWFM) may be formed in the nanosheet matrix, a tungsten layer may be deposited around the pFET and nFET WFM, and a self-aligned contact cap may be formed on top of the tungsten layer. Finally, a metallic trench contact may be formed.

Advantageously, some embodiments of the present disclosure may address the PPA requirement above for current and future GAA nodes. The BDI may neutralize leakage and enable Lmetal=12 nm devices. The SAGC may allow for ultimate scaling for N-P space, including at sizes <15 nm. The matrix of n*m nanosheet channels (which may have a width of, e.g., <25 nm) preserve optimal electrostatics while maintaining drive current capability and performance. Additionally, all the processes in the fabrication flow are known processes, with most of them have already been on previous or current technology nodes, which means that the devices can be created using existing system with minimal modification.

Turning now to the figures,FIG.1is a plan view depicting a semiconductor structure, in accordance with embodiments of the present disclosure. In particular,FIG.1shows a plan view of a GAA nanosheet matrix-FET100. The GAA nanosheet matrix-FET100contain an nFET region and a pFET region separated by a N-P dielectric20. Gates18run the length of the GAA nanosheet matrix-FET100, crossing on top of a nanosheet matrix that comprises WFM regions14and nanowire regions16. A shallow trench isolation (STI) layer12surrounds the nanosheet matrix.

FIGS.2A-16Cdepict a fabrication process for forming a GAA nanosheet matrix-FET (e.g., the GAA nanosheet matrix-FET100shown inFIG.1), in accordance with embodiments of the present disclosure. In particular, the figures that have a figure number ending in ‘A’ (e.g.,FIG.2A,FIG.3A,FIG.4A, etc.) show the GAA nanosheet matrix-FET when viewed along the X-X cut shown inFIG.1. Likewise, the figures that have a figure number ending in ‘B’ (e.g.,FIG.2B,FIG.3B,FIG.4B, etc.) show the GAA nanosheet matrix-FET100when viewed along the Y1-Y1cut shown inFIG.1, and the figures that have a figure number ending in ‘C’ (e.g.,FIG.2C,FIG.3C,FIG.4C, etc.) show the GAA nanosheet matrix-FET100when viewed along the Y2-Y2cut shown inFIG.1.

Referring toFIGS.2A-2C, shown are cross-sectional views depicting the GAA nanosheet matrix-FET100ofFIG.1at an intermediate stage of the manufacturing process, in accordance with embodiments of the present disclosure. In particular,FIGS.2A-2Cshow a nanosheet stack epitaxy from which the GAA nanosheet matrix-FET100is fabricated. The nanosheet stack epitaxy includes a high-Ge % SiGe layer104on top of a substrate102. The substrate102may be, for example, a Si substrate. The high-Ge % SiGe layer104may be, for example, SiGe60%. The high-Ge % SiGe layer104may act as a sacrificial layer that is replaced in subsequent fabrication operations. Alternating a lower-Ge % SiGe layers106and Si layers108are formed on top of the high-Ge % SiGe layer104. The lower-Ge % SiGe layers106may comprises, for example, SiGe25%.

Although three Si layers108are depicted in the stack, corresponding to three nanosheet in the GAA nanosheet matrix-FET100, this is done for illustrative purposes only. As would be recognized by a person of ordinary skill, fewer than or greater than the three nanosheets can be present as can be desired for different nFET and pFET nanosheet structures.

FIGS.3A-3Cdepict the GAA nanosheet matrix-FET100after stack patterning and partial fin RIE operations. A hard mask110is deposited over portions of the top layer of Si. An extreme ultraviolet lithography (EUV) stack patterning and/or ME operation is then used to create a plurality of fins in the GAA nanosheet matrix-FET100. As shown inFIG.3B, the fins may have a width of W and the channels between fins may go through all of the Si layers108and lower-Ge % SiGe layers106. The high-Ge % SiGe layer104may act as an etch stop such that it is only partially etched into.

The fin-fin spacing, represented by ‘b’ inFIG.3B, may be substantially similar to the spacing between Si nanosheets (NS)108. In other words, the gap between the individual fins in the same region (e.g., in the nFET region or the pFET region) may be approximately the same size as the thickness of the lower-Ge % SiGe layers106, which is represented by distance ‘a’ inFIG.3B. A larger gap, represented by ‘d’ inFIG.3B, may be etched between the pFET and nFET regions.

In some embodiments, the width of the fins is approximately 10 nm to 25 nm, the thickness of the lower-Ge % SiGe layers106is approximately 11 nm, the gap between fins in the same region is also approximately 11 nm, and the distance between the pFET and nFET regions may be approximately 15 nm+twice the gap between the fins, which in this example is approximately 37 nm. While shown as roughly the same size as the lower-Ge % SiGe layers106, the Si layers108may actually be roughly half the size of the lower-Ge % SiGe layers106. For example, in some embodiments, the thickness of the Si layers108is approximately 6 nm.

It is to be understood that these values are all approximate values of some embodiments of the present disclosure. Except where inconsistent or infeasible, other embodiments may have different dimensions (including different relative dimensions between components) without departing from the spirit of scope of the invention, as would be understood by a person of ordinary skill in the art.

FIGS.4A-4Cdepict the GAA nanosheet matrix-FET100after forming lower-Ge % SiGe material106between the fins. The lower-Ge % SiGe material106may be grown to substantially fill in gaps between fins. Alternatively, conformal CVD/PECVD deposition of amorphous SiGe may be used to fill in the gaps with the lower-Ge % SiGe material106. A CMP operation may then be performed to remove excess lower-Ge % SiGe material106from the top of the structure100. Because the epitaxial growth (or conformal CVD/PECVD deposition) of the lower-Ge % SiGe material106is done to a thickness necessary to fill in the gaps between the fins (‘b’ in the figures), and the gap between the pFET and nFET regions (‘d’ in the figures) is larger than twice the size of the gap between fins in the same region, the formation of the lower-Ge % SiGe material106leaves a gap between the nFET and pFET regions. This gap can be seen inFIGS.4B and4C.

FIGS.5A-5Cdepict the GAA nanosheet matrix-FET100after performing a vertical etch operation. The vertical etch operation may be an anisotropic SiGe/Si etch. The etch may remove a portion of the lower-Ge % SiGe material106from the top of the structure100, exposing part of the sides of the hard mask110. In addition, the etch process extends vertically into the substrate102in regions where the lower-Ge % SiGe material106is unmerged, as shown inFIGS.5A-5C. This effectively separates the lower-Ge % SiGe material106and the high-Ge % SiGe material104in the pFET region from the same material in the nFET region.

FIGS.6A-6Cdepict the GAA nanosheet matrix-FET100after forming a dielectric pillar112in the etched space between the nFET region and the pFET region. The dielectric pillar may be formed by conformal low-k material deposition followed by an isotropic etch back, which removes excess low-k material and the hard mask110. In some embodiments, the dielectric pillar112is SiOCN.

FIGS.7A-7Cdepict the GAA nanosheet matrix-FET100after STI114formation. The STI114is formed in areas of the substrate102that were etched during the anisotropic etch operation. In particular, the STI114is formed along the sides of the nFET and pFET regions to prevent electric current leakage between the GAA nanosheet matrix-FET100and adjacent semiconductor devices. In some embodiments, the STI may be an oxide.

FIGS.8A-8Cdepict the GAA nanosheet matrix-FET100after the formation of dummy gates116. The dummy gates116may be formed on top of portions of the STI layers114, the previously exposed Si layers108, the lower-Ge % SiGe layers106, and the dielectric pillar112. The dummy gates116may be made of amorphous silicon (a-Si). A hard mask118may also be formed on top of the dummy gates116.

FIGS.9A-9Cdepict the GAA nanosheet matrix-FET100after additional fabrication processes are performed. After forming the dummy gates116and hard mask118, the high-Ge % SiGe layer104is removed and replaced with a BDI material120. The BDI material120may be, for example, SiO2, SiOCN, SiOC, SiBCN. The BDI120may be deposited on the substrate102after removal of the high-Ge % SiGe layer104. Furthermore, the BDI material120may be deposited on the sides of the dummy gates116and the hard mask118, as shown inFIG.9A.

In addition to depositing replacing the high-Ge % SiGe layer104with the BDI material120, a fin recess process may be performed that selectively removes parts of the Si layers108and the low-Ge % SiGe layers106. The recessed fins are self-aligned to the gates. This can be seen inFIG.9A, where the fins are separated all the way down to the BDI layer120, andFIG.9C, where the Si layers108and the low-Ge % SiGe layers106have been completely removed.

FIGS.10A-10Cdepict the GAA nanosheet matrix-FET100after inner spacers122are formed. The inner spacers122may be formed on the remaining low-Ge % SiGe layers106. As illustrated inFIG.10A, the inner spacers122may be formed along the edges of the low-Ge % SiGe layers106(i.e., at the edges of the gates). This may be done by selectively indenting the low-Ge % SiGe layers106, depositing the inner spacers122in the indents, and then etching back to re-expose the Si layers108. The inner spacers122may be an isolating material, such as SiO2, SiN, SiBCN, SiOCN, SiOC.

FIGS.11A-11Cdepict the GAA nanosheet matrix-FET100after formation of the nFET source/drain epitaxy124and pFET source/drain epitaxy126. The nFET and pFET source/drain epitaxy materials124,126may be grown in a sequential operation (i.e., one after the other), and they may be formed such that they do not reach the top of the dielectric pillar112, as shown inFIG.11C.

FIGS.12A-12Cdepict the GAA nanosheet matrix-FET100after formation of the interlayer dielectric (ILD) layer128. The ILD layer128may be, in some embodiments, SiO2. The ILD layer128lay may be deposited such that it fills the area between the gates (as shown inFIG.12A) and sits on top of the nFET and pFET source/drain epitaxy materials124,126(as shown inFIG.12C). The ILD layer128may also sit on top of portions of the STI114. A CMP operation may then be performed to remove the hard mask118, thereby exposing the top of the dummy gates116and planarizing the top of the ILD material128, the dummy gates116, and the BDI material120, as shown inFIG.12A.

FIGS.13A-13Cdepict the GAA nanosheet matrix-FET100after removal of the dummy gates116and the remaining low-Ge % SiGe layers106. The dummy gates116and the remaining low-Ge % SiGe layers106may be removed by any suitable fabrication process, as would be known to a person of ordinary skill.

FIGS.14A-14Cdepict the GAA nanosheet matrix-FET100after formation of the nFET WFM132, the pFET WFM140, a metal gate layer134, and a self-aligned contact (SAC) cap136. In particular, the nFET WFM132and pFET WFM140are formed in the gaps where the low-Ge % SiGe layers106previously were (i.e., between the Si layers108and between the bottom Si layer108and the BDI120), as well as on top of the top Si Layer108. This is shown inFIGS.14A and14B. Additionally, the nFET WFM132and pFET WFM140are formed in the gate channels in their respective regions, as shown inFIG.14A. The nFET WFM132and pFET WFM140may be the same or different WFMs, as would be apparent to one of ordinary skill in the art.

The metal gate layer134is formed on top of and around the nFET WFM132and pFET WFM140in the gate areas, as shown inFIGS.14A and14B. The metal gate layer134may be any suitable gate material, including, for example, tungsten. A SAC cap136is formed on top of the metal gate layer134. The SAC cap136is a dielectric layer that helps self-align the trench metal contact in-between the gates during the RIE process, and it may prevent the gates from contacting other components and contact-to-gate shorting. While embodiments of the present disclosure are described as including a SAC cap, some embodiments may not have a SAC cap. Instead, embodiments of the present disclosure may involve a non-SAC fabrication process.

FIGS.15A-15Cdepict the GAA nanosheet matrix-FET100after trench contact formation. In particular,FIGS.15A-15Cdepict trench contact formation in the case of a shared gate device (i.e., one where the pFET and nFET regions share a gate). As shown inFIGS.15A-15C, portions of the ILD material128are replaced with trench contacts138, which are made of a conductive material such as a metal. The trench contacts138extend from the top of the GAA nanosheet matrix-FET100down to the nFET source/drain epitaxy124and pFET source/drain epitaxy126. The trench contacts138are isolated from the gates by the SAC cap136and the gate spacers on the sidewalls of the gates. As shown inFIG.15A, the gate spaces may be made out of the same material as the BDI layer120, but this is not a requirement.

FIGS.16A-16Cdepict the GAA nanosheet matrix-FET100after trench contact formation. In particular,FIGS.16A-16Cdepict trench contact formation in the case of an isolated gate device (i.e., one where the pFET and nFET regions do not share a gate). The GAA nanosheet matrix-FET100is substantially similar to the one shown inFIGS.15A-15Cexcept that the metal gate layer134is broken up by the dielectric pillar112, as can be seen inFIG.16B. This can be done by forming a dielectric extension up from the original dielectric pillar112to disconnect the p-gates from the n-gates.

The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments described. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments described herein.