Patent ID: 12225705

MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments will be described with reference to the drawings. Note that the embodiments can be implemented with various modes, and it will be readily appreciated by those skilled in the art that modes and details thereof can be changed in various ways without departing from the spirit and scope thereof. Thus, the present invention should not be construed as being limited to the following description of the embodiments.

A plurality of embodiments described below can be combined as appropriate. In addition, in the case where a plurality of structure examples are described in one embodiment, the structure examples can be combined as appropriate.

Note that in the drawings attached to this specification, the block diagram in which components are classified according to their functions and shown as independent blocks is illustrated; however, it is difficult to separate actual components completely according to their functions, and it is possible for one component to relate to a plurality of functions.

In the drawings and the like, the size, the layer thickness, the region, or the like is exaggerated for clarity in some cases. Therefore, they are not limited to the illustrated scale. The drawings schematically show ideal examples, and shapes, values, or the like are not limited to shapes, values, or the like shown in the drawings.

In the drawings and the like, the same elements, elements having similar functions, elements formed of the same material, elements formed at the same time, or the like are sometimes denoted by the same reference numerals, and description thereof is not repeated in some cases.

Moreover, in this specification and the like, the term “film” and the term “layer” can be interchanged with each other. For example, the term “conductive layer” can be changed into the term “conductive film” in some cases. As another example, the term “insulating film” can be changed into the term “insulating layer” in some cases.

In this specification and the like, the terms for describing arrangement such as “over” and “below” do not necessarily mean “directly over” and “directly below”, respectively, in the positional relationship between components. For example, the expression “a gate electrode over a gate insulating layer” does not exclude the case where there is an additional component between the gate insulating layer and the gate electrode.

In this specification and the like, ordinal numbers such as “first”, “second”, and “third” are used in order to avoid confusion among components, and the terms do not limit the components numerically.

In this specification and the like, when a plurality of components are denoted by the same reference signs, and in particular need to be distinguished from each other, an identification numeral such as “_1”, “_2”, “[n]”, or “[m,n]” is sometimes added to the reference signs. For example, the second wiring GL is referred to as a wiring GL[2].

In this specification and the like, “electrically connected” includes the case where connection is made through an “object having any electric function”. There is no particular limitation on the “object having any electric function” as long as electric signals can be transmitted and received between components that are connected through the object. Examples of the “object having any electric function” include a switching element such as a transistor, a resistor, an inductor, a capacitor, and other elements with a variety of functions as well as an electrode and a wiring. Furthermore, even when the expression “being electrically connected” is used, there is a case in which no physical connection portion is made and a wiring is just extended in an actual circuit.

In addition, in this specification and the like, the term “electrode” or “wiring” does not functionally limit these components. For example, an “electrode” is used as part of a “wiring” in some cases, and vice versa.

In this specification and the like, a “terminal” in an electric circuit refers to a portion where a current or a potential is input (or output) or a signal is received (or transmitted). Accordingly, part of a wiring or an electrode functions as a terminal in some cases.

In general, a “capacitor” has a structure in which two electrodes face each other with an insulator (dielectric) therebetween. This specification and the like include a case where a “capacitor element” is the above-described “capacitor”. That is, this specification and the like include cases where a “capacitor element” is one having a structure in which two electrodes face each other with an insulator therebetween, one having a structure in which two wirings face each other with an insulator therebetween, or one in which two wirings are positioned with an insulator therebetween.

In this specification and the like, a “voltage” often refers to a potential difference between a given potential and a reference potential (e.g., a ground potential). Thus, a voltage and a potential difference can be interchanged with each other.

In this specification and the like, a transistor is an element having at least three terminals of a gate, a drain, and a source. In addition, a channel formation region is included between the drain (a drain terminal, a drain region, or a drain electrode) and the source (a source terminal, a source region, or a source electrode), and a current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, a channel formation region refers to a region through which a current mainly flows.

Furthermore, functions of a source and a drain might be switched when a transistor of opposite polarity is employed or a direction of current flow is changed in circuit operation, for example. Thus, the terms of a source and a drain are interchangeable for use in this specification and the like.

Furthermore, unless otherwise specified, an off-state current in this specification and the like refers to a drain current of a transistor in an off state (also referred to as a non-conduction state or a cutoff state). Unless otherwise specified, the off state of an n-channel transistor refers to a state where the gate voltage Vgswith respect to a source is lower than a threshold voltage Vth, and the off state of a p-channel transistor refers to a state where the gate voltage Vgswith respect to a source is higher than the threshold voltage Vth. That is, the off-state current of an n-channel transistor sometimes refers to drain current at the time when the voltage Vgsof a gate with respect to a source is lower than the threshold voltage Vth.

In the above description of the off-state current, the drain may be replaced with the source. That is, the off-state current sometimes refers to a source current when a transistor is in an off state. In addition, a leakage current sometimes expresses the same meaning as the off-state current. Furthermore, in this specification and the like, the off-state current sometimes refers to a current that flows between a source and a drain when a transistor is in an off state.

Furthermore, in this specification and the like, an on-state current sometimes refers to a current that flows between a source and a drain when a transistor is in an on state (also referred to as a conduction state).

In this specification and the like, a metal oxide means an oxide of metal in a broad sense. Metal oxides are classified into an oxide insulator, an oxide conductor (including a transparent oxide conductor), an oxide semiconductor, and the like.

For example, in the case where a metal oxide is used in a channel formation region of a transistor, the metal oxide is referred to as an oxide semiconductor in some cases. That is to say, in the case where a metal oxide has at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can also be called a metal oxide semiconductor. In other words, a transistor containing a metal oxide in a channel formation region can be referred to as an “oxide semiconductor transistor” or an “OS transistor”.

Furthermore, in this specification and the like, a metal oxide containing nitrogen is also referred to as a metal oxide in some cases. A metal oxide containing nitrogen may be referred to as a metal oxynitride. The details of a metal oxide will be described later.

Embodiment 1

Structure examples of memory devices of one embodiment of the present invention will be described with reference toFIG.1toFIG.11. The memory devices of one embodiment of the present invention are each a memory device that can function by utilizing semiconductor characteristics, and is also called a memory.

The memory devices of one embodiment of the present invention each have a structure in which a plurality of layers including OS transistors are stacked over a layer including a transistor formed using a semiconductor substrate. The OS transistor has a characteristic of an extremely low off-state current.

<Block Diagram of Memory Device>

FIG.1Ais a block diagram illustrating a structure example of a memory device10A that is one embodiment of the present invention. Note that in the drawings described in this specification and the like, the flow of main signals is indicated by an arrow or a line, and a power supply line and the like are omitted in some cases.

The memory device10A includes a peripheral circuit20and a memory cell array30. The peripheral circuit20includes, in addition to a row driver21and a column driver22, an element layer26including a precharge circuit24, a sense amplifier25, a check bit generation circuit54, an error detection circuit55, and a switch circuit23(seeFIG.3).

The row driver21has a function of outputting a signal for driving the memory cell array30to a word line WL. Specifically, the row driver21has a function of outputting a word signal to the word line WL (WL_1and WL_N are illustrated inFIG.1A, and N is a natural number greater than or equal to 2). The row driver21is referred to as a word line driver circuit in some cases. Note that the row driver21includes a decoder circuit for selecting the word line WL corresponding to the specified address, a buffer circuit, or the like. The word line WL is simply referred to as a wiring in some cases.

The column driver22has a function of outputting a signal for driving the memory cell array30to a bit line BL. Specifically, the column driver22has a function of outputting a data signal to the bit line BL (BL_1and BL_2are illustrated inFIG.1A). The column driver22is referred to as a bit line driver circuit in some cases. Note that the column driver22includes a decoder circuit for selecting a bit line corresponding to a specified address, or the like. The bit line BL is simply referred to as a wiring in some cases. In the drawings, the bit line BL is represented by a bold line or a bold dotted line in some cases for increasing visibility.

The data signal supplied to the bit line BL corresponds to a signal written to a memory cell or a signal read out from the memory cell. The data signal is described as a binary signal having a high-level or a low-level potential corresponding to data 1 or data 0 (also referred to as data High or data Low, or data H or data L). The high-level potential is a potential VDD, and the low-level potential is a potential VS S or a ground potential (GND). Note that a level of the data signal may be multilevel higher than or equal to ternary.

Other signals supplied to the bit line BL include a precharge potential for reading out data. The precharge potential can be VDD/2, for example.

The memory cell array30includes, for example, N (N is a natural number greater than or equal to 2) element layers34_1to34_N. The element layer34_1includes one or more memory cells31_1. The memory cell31_1includes a transistor32_1and a capacitor33_1. The element layer34_N includes one or more memory cells31_N. The memory cell31_N includes a transistor32_N and a capacitor33_N.

Note that the capacitor is referred to as a capacitor element in some cases. The element layer indicates a layer in which elements such as a capacitor and a transistor are provided and a layer including components such as a conductor, a semiconductor, and an insulator.

The transistors32_1to32_N function as switches whose conduction states (also referred to as on or on state) and non-conduction states (also referred to as off or off state) are controlled in accordance with word signals supplied to the word lines WL_1to WL_N. In addition, one of a source and a drain of each of the transistors32_1to32_N is connected to any one of the bit lines BL.

Each of the transistors32_1to32_N is preferably a transistor including a metal oxide in a channel formation region (hereinafter referred to as OS transistor). In the structure of one embodiment of the present invention, an OS transistor is used in the memory cell, so that electric charge corresponding to a predetermined potential can be retained in the capacitors33_1to33_N which are electrically connected to the other of the sources and the drains of the transistors32_1to32_N with use of a characteristic of extremely low leakage current flowing between the source and the drain when the transistor is in an off state (the leakage current is hereinafter referred to as off-state current).

In other words, data once written to the memory cells31_1to31_N can be retained for a long time. Thus, the memory device10A enables the frequency of data refresh to be reduced, and low power consumption can be achieved.

In addition, the memory cells31_1to31_N each using an OS transistor can rewrite and read data by charging or discharging of electric charge; thus, a substantially unlimited number of times of data writing and data reading is possible.

Unlike a magnetic memory or a resistive random-access memory, the memory cells31_1to31_N each using an OS transistor do not undergo an atomic-level structure change and thus are superior in rewrite endurance. In addition, unlike a flash memory, the memory cells31_1to31_N each using an OS transistor do not exhibit instability in characteristics due to an increase in electron trap centers caused by repeated rewrite operations.

The memory cells31_1to31_N each using an OS transistor can be provided over a silicon substrate provided with a transistor including silicon in its channel formation region (hereinafter referred to as Si transistor) or the like. Thus, integration can be facilitated. Furthermore, an OS transistor can be manufactured with a manufacturing apparatus similar to that for a Si transistor and thus can be manufactured at low cost.

An OS transistor can be a four-terminal semiconductor element including a back gate electrode in addition to a gate electrode, a source electrode, and a drain electrode. The OS transistor can be formed with an electric circuit network that can independently control input and output of signals flowing between a source and a drain depending on a potential supplied to the gate electrode or the back gate electrode. Therefore, the circuit design can be made on the same concept as that for LSI (Large Scale Integration).

Furthermore, electrical characteristics of the OS transistor are better than those of a Si transistor in a high-temperature environment. Specifically, the ratio between an on-state current and an off-state current is large even at a high temperature higher than or equal to 125° C. and lower than or equal to 150° C.; thus, favorable switching operation can be performed.

Note that the memory device10A illustrated inFIG.1Acan be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory) using an OS transistor in a memory cell. Since one memory cell can be composed of one transistor and one capacitor, a high-density memory that can store a large amount of data can be achieved. In addition, using an OS transistor enables data retention time to be prolonged.

The capacitors33_1to33_N each have a structure in which an insulator is sandwiched between conductors to be electrodes. Note that as a conductor included in the electrode, a semiconductor to which a conductivity is imparted, or the like can be used. Although the details of the arrangement of the capacitors33_1to33_N are described later, the following arrangement is possible: the capacitors33_1to33_N are positioned over or below the transistors32_1to32_N to overlap with the transistors32_1to32_N; or parts of semiconductor layers, electrodes, or the like included in the transistors32_1to32_N are used as one of electrodes of the capacitors33_1to33_N.

The element layer26including the precharge circuit24, the sense amplifier25, the check bit generation circuit54, the error detection circuit55, and the switch circuit23has a function of generating a check bit when data is written to the memory cell, a function of precharging the bit line BL when data is read out from the memory cell, a function of amplifying a potential of the bit line BL, and a function of detecting whether or not the data read out from the memory cell has an error occurs with use of the check bit.

Each of the circuits (the precharge circuit24, the sense amplifier25, the check bit generation circuit54, the error detection circuit55, and the switch circuit23) included in the element layer26is preferably formed using an OS transistor. When each circuit included in the element layer26is formed using an OS transistor, the element layer26can be provided over a silicon substrate or the like where a Si transistor is formed. Thus, the integration can be facilitated. Furthermore, the OS transistor can be manufactured with a manufacturing apparatus similar to that for a Si transistor and thus can be manufactured at low cost.

<Schematic Diagram of Memory Device>

FIG.1Bis a schematic diagram illustrating a structure example of the memory device10A for describing the element layers34_1to34_N and the element layer26as the structures described with reference toFIG.1A. The schematic diagram inFIG.1Bis a perspective view in which directions of an x-axis, a y-axis, and a z-axis are defined for describing the arrangement of each structure described inFIG.1A.

As illustrated inFIG.1B, the element layer26and the element layer34_1to the element layer34_N, that is, (1+N) layers in total each including an OS transistor, are stacked over a semiconductor substrate11in the memory device10A. Each of the element layer26and the memory cells31_1to31_N included in the element layer34_1to the element layer34_N has a region overlapping with the column driver22formed using the semiconductor substrate11. The element layer26is provided between the semiconductor substrate11and the element layer34_1.

There is no particular limitation on the semiconductor substrate11as long as a channel region of a transistor can be formed therein. For example, a single crystal silicon substrate, a single crystal germanium substrate, a compound semiconductor substrate (such as a SiC substrate or a GaN substrate), an SOI (Silicon on Insulator) substrate, or the like can be used.

The transistor in the memory cell31_1included in the element layer34_1and the transistor in the memory cell31_N included in the element layer34_N are electrically connected via the bit line BL provided in the vertical direction. The bit line BL is electrically connected to the element layer26, and the element layer26is electrically connected to the column driver22formed using the semiconductor substrate11.

For example, a bit line BL_1is provided in contact with a semiconductor layer of the transistor included in the memory cell31_1. Alternatively, the bit line BL_1is provided in contact with a region functioning as a source or a drain in the semiconductor layer of the transistor included in the memory cell31_1. Alternatively, the bit line BL_1is provided in contact with a conductor provided in contact with the region functioning as the source or the drain in the semiconductor layer of the transistor included in the memory cell31_1.

In other words, the bit line BL can be regarded as a wiring that electrically connects one of the source and the drain of the transistor included in the memory cell31_1, one of the source and the drain of the transistor included in the memory cell31_N, and the element layer26.

The bit line BL can be regarded to be provided to extend in the direction vertical to or substantially vertical to a plane of the semiconductor substrate11where the column driver22is provided. In other words, as illustrated inFIG.1B, the bit line BL is provided to be connected to the transistor included in the memory cell31_1and the transistor included in the memory cell31_N and to be in the direction vertical (z direction) or substantially vertical to the surface (xy plane) of the semiconductor substrate. Note that the term “substantially vertical” means a state where the angle is greater than or equal to 85° and less than or equal to 95°.

In the memory device10A that is one embodiment of the present invention, an OS transistor with an extremely low off-state current is used as the transistor provided in each element layer. Accordingly, the frequency of refreshing data retained in the memory cell can be reduced, and power consumption of the memory device can be reduced.

OS transistors can be stacked and manufactured in the vertical direction using the same manufacturing process repeatedly; thus, the manufacturing cost can be reduced. In addition, in the memory device10A, the transistors included in the memory cells can be arranged not in the plane direction but in the vertical direction, so that the memory density can be improved. Consequently, the memory device10A can be downsized.

In addition, the OS transistor has a smaller fluctuation in electrical characteristics than a Si transistor even in a high-temperature environment; when the OS transistors are stacked and integrated, a fluctuation in electric characteristics of the transistors is small. Thus, the memory device10A can function as a memory device with high reliability.

Since the memory cells can be arranged over the column driver and the like in the memory device10A, the memory device10A can be a small-sized high-density memory device that can store a large amount of data. Furthermore, the memory device10A can operate even when capacitance of the capacitors in the memory cells is reduced.

In the memory device10A, the bit line extended from the memory cell array is provided in the direction substantially vertical to the surface of the semiconductor substrate11, whereby the length of the bit line between the memory cell array and the element layer26can be reduced. Thus, parasitic capacitance of the bit line can be reduced, and a potential of a data signal retained in the memory cell can be read out even when the data signal is a multilevel signal.

<Cross-Sectional View of Memory Device>

FIG.2shows a schematic view of a cross section parallel to the vertical direction (z-axis direction) of the memory device10A described with reference toFIG.1AandFIG.1B.

As illustrated inFIG.2, in the memory device10A, the memory cells31_1to31_N provided in the element layers, the element layer26, and the column driver22formed using the semiconductor substrate11can be connected via the bit line BL provided in the vertical direction. When the bit line BL is provided in the vertical direction, the length of the bit line BL can be reduced, so that the load of the bit line BL can be reduced.

FIG.3illustrates the element layers34_1to34_N as the memory cell array30, the element layer26including the precharge circuit24, the sense amplifier25, the check bit generation circuit54, the error detection circuit55, and the switch circuit23, and a write/read circuit29included in the column driver22.

FIG.3also illustrates a bit line BL_A or BL_B, transistors28_aand28_bcontrolling conduction of the precharge circuit24and the sense amplifier25, and a switch23_A to a switch23_C in the switch circuit23. The bit line BLA is connected to one of a source and a drain of the transistor28_a, and the bit line BLB is connected to one of a source and a drain of the transistor28_b.

Over the element layer26illustrated inFIG.3, the element layer34_1to34_N are provided, and the bit line BL_A and the bit line BL_B are provided in the vertical direction. In other words, the element layer26constituting part of the peripheral circuit can be stacked in a manner similar to the arrangement of the element layers34_1to34_N. The bit line BL_A and the bit line BL_B are connected to the transistors included in the precharge circuit24and the sense amplifier25via the transistor28_aand the transistor28_b.

The precharge circuit24includes n-channel transistors24_1to24_3. The precharge circuit24is a circuit for precharging the bit line BL_A and the bit line BL_B to have an intermediate potential VPC corresponding to a potential VDD/2 that is between the potential VDD and the potential VSS, for example, in accordance with a precharge signal supplied to a precharge line PCL.

The sense amplifier25includes n-channel transistors25_1to25_4. The transistor25_1and the transistor25_2are connected to a wiring VHH, and the transistor25_3and the transistor25_4are connected to a wiring VLL. The wiring VHH has a function of suppling a potential VDD, and the wiring VLL has a function of supplying a potential VSS. The transistors25_1to25_4are transistors forming an inverter loop.

When the data is read out from the memory cell, the precharge circuit24precharges the bit line, and the row driver21sets the word line of the selected memory cell to a high level, whereby the potential of the precharged bit line is changed. Depending on the change, the sense amplifier25sets the potentials of a pair of wirings connected to the sense amplifier25to the potential VDD or the potential VSS and outputs the potentials to the write/read circuit29through the switch circuit23.

The check bit generation circuit54has a function of generating a check bit based on a data signal output from the write/read circuit29when data is written to the memory cell. The error detection circuit55has a function of detecting whether data read out from the memory cell has an error or not with use of the check bit when the data is read out from the memory cell and a function of outputting the detection result to the write/read circuit29. Details of the check bit generation circuit54and the error detection circuit55are described later.

Note that in the case where the element layers34_1to34_N and the element layer26in the memory device10A illustrated inFIG.2are collectively referred to as a unit39, the unit39may be stacked in the vertical direction.FIG.4illustrates a memory device10B in which M units39(a unit39_1to a unit39_M; M is a natural number greater than or equal to 2) are stacked with use of the unit39described with reference toFIG.2.FIG.4shows a schematic view of a cross section parallel to the vertical direction (z-axis direction) of the memory device10B.

As illustrated inFIG.4, in the memory device10B, each of the unit39_1to the unit39_M includes the element layers34_1to34_N and the element layer26. One of the unit39_1to the unit39_M is selected by a selection signal MUX, and the selected unit39inputs or outputs a signal through a wiring BL_U and the element layer26. The wiring BL_U is selected by a switch circuit41that can be switched by a selection signal SEL and is connected to the column driver22through the wiring GBL. Note that the switch circuit41may be formed using the OS transistor included in the element layer26.

With the structure of the memory device10B, the number of stacked element layers34_1to34_N in each of the unit391to the unit39_M can be reduced. When the number of stacked element layers34_1to34_N is reduced, the length of the bit line BL can be reduced, and accordingly the load on the bit line BL can be reduced. In the drawings, the wiring GBL in some cases are represented by a bold line or a bold dotted line for increasing visibility. The wiring GBL is referred to as a global bit line in some cases.

The wiring GBL illustrated inFIG.4can be provided after the element layer including the OS transistor is formed. For example, as illustrated in a schematic cross-sectional view inFIG.5A, the wiring GBL can be provided in openings provided on an outer periphery of sealing layers40A surrounding respective element layers after the element layers including OS transistors are formed. Alternatively, as illustrated in a schematic cross-sectional view inFIG.5B, the wiring GBL can be provided in openings provided on an outer periphery of a sealing layer40B surrounding all element layers after the element layers including OS transistors are formed. Note that inFIG.5AandFIG.5B, the switch circuit41and the like are omitted, and details of each element layer provided with the wiring GBL will be described in Embodiment 3.

<Check Bit Generation Circuit and Error Detection Circuit>

FIG.6Ais a circuit diagram illustrating a structure example of the check bit generation circuit54. The check bit generation circuit54includes an XOR circuit53_1to an XOR circuit53_3. A structure example of the XOR circuit53is described later.

Note that for easy understanding, the description of the memory device10A is made on the assumption that N=5 regarding the element layers34_1to34_N included in the memory cell array30. One of the element layers34_1to34_5is used for retaining a check bit, and the other four layers are used for retaining data. In other words, the check bit generation circuit54described in this embodiment is a circuit for handling 4-bit data and a check bit that is 1 bit.

The check bit generation circuit54includes an input terminal T_A0to an input terminal T_A3, and 4-bit data represented as a bit A0to a bit A3is input thereto. In addition, the check bit generation circuit54includes an input terminal T_CK1to an input terminal T_CK4, and a clock signal CK1to a clock signal CK4, which are control signals, are input thereto. Moreover, the check bit generation circuit54outputs a check bit from an output terminal OUT.

FIG.6Bis a timing chart showing a relation between the clock signal CK1to the clock signal CK4input to the check bit generation circuit54, an input period PDI of the 4-bit data, and an output period PDO of the check bit. Since the high levels and the low levels of the clock signal CK1to the clock signal CK4and the 4-bit data are represented by the potential VDD and the potential VSS, they are expressed as Vdd (H) and Vss (L) inFIG.6B.

FIG.6Cis a truth table where outputs with respect to the 4-bit data input to the check bit generation circuit54are expressed as high levels (H) or low levels (L). The truth table inFIG.6Cindicates that the check bit generation circuit54outputs a high level (H) when the number of high levels (H) of the bit A0to the bit A3is odd, and that the check bit generation circuit54outputs a low level (L) when the number of high levels (H) is even or 0.

Next,FIG.7Ais a circuit diagram illustrating a structure example of the error detection circuit55. The error detection circuit55includes an XOR circuit53_4to an XOR circuit53_7and a delay circuit52_1to a delay circuit52_4. Note that a structure example of the delay circuit52is described later.

Like the check bit generation circuit54, the error detection circuit55described in this embodiment is a circuit for handling 4-bit data and the check bit that is 1 bit.

The error detection circuit55includes an input terminal T_A0to an input terminal T_A3, and 4-bit data represented as the bit A0to the bit A3is input thereto. The error detection circuit55includes an input terminal T_CK1to an input terminal T_CK4, and the clock signal CK1to the clock signal CK4, which are control signals, are input thereto. In addition, the error detection circuit55includes an input terminal T_B0, and a check bit B0is input thereto. When an error is not found in a relation between the check bit B0and the bit A0to the bit A3, the error detection circuit55outputs a low level (L) from an output terminal OUT. When an error is found, the error detection circuit55outputs a high level (H).

FIG.7Bis a timing chart showing a relation between the clock signal CK1to the clock signal CK4input to the error detection circuit55, an input period PDI of the 4-bit data and the check bit, and an output period PDO of the error detection circuit55. Since the high levels and the low levels of the clock signal CK1to the clock signal CK4, the 4-bit data, and the check bit are represented by the potential VDD and the potential VSS, they are expressed as Vdd (H) and Vss (L) inFIG.7B.

FIG.8is a truth table where outputs with respect to the 4-bit data and the check bit input to the error detection circuit55are expressed as high levels (H) or low levels (L). The truth table inFIG.8indicates that the error detection circuit55outputs a high level (H) when the check bit B0is at a low level (L) and the number of high levels (H) of the bit A0to the bit A3is odd. This means that the check bit generation circuit54outputs a high level (H) as a check bit when the number of high levels (H) of the bit A0to the bit A3is odd, in which case an error is found in the relation between the check bit B0and the bit A0to the bit A3.

Furthermore, the truth table inFIG.8indicates that the error detection circuit55outputs a high level (H) when the check bit B0is at a high level (H) and the number of high levels (H) of the bit A0to the bit A3is even or 0. This means that the check bit generation circuit54outputs a low level (L) as a check bit when the number of high levels (H) of the bit A0to the bit A3is even or 0, in which case an error is found in the relation between the check bit B0and the bit A0to the bit A3.

Thus, with the check bit generation circuit54, the check bit B0, and the error detection circuit55, the memory device10A can conduct a parity check as well as data writing and reading inside the memory device. An output signal of the error detection circuit55is output to the column driver22through a switch23_C.

<XOR Circuit, NAND Circuit, and Delay Circuit>

FIG.9Ashows a symbol representing the XOR circuit53, andFIG.9Bis a circuit diagram illustrating a structure example of the XOR circuit53. As illustrated inFIG.9B, the XOR circuit53includes a NAND circuit51_1to a NAND circuit51_4, the delay circuit52_1, and the delay circuit52_2. The XOR circuit53also includes an input terminal D, an input terminal E, and an input terminal C5to an input terminal C8to which a control signal S_C5to a control signal S_C8are input, and outputs a signal from an output terminal Z.

FIG.9Cis a timing chart showing a relation between the control signal S_C5to the control signal S_C8input to the XOR circuit53, an input period PDI of signals input to the input terminal D and the input terminal E, and an output period PDO of the XOR circuit53. Since the high levels and the low levels of the control signal S_C5to the control signal S_C8and an input signal are represented by the potential VDD and the potential VSS, they are expressed as Vdd (H) and Vss (L).

FIG.9Dis a truth table where outputs with respect to the signal input to the XOR circuit53are expressed as high levels (H) and low levels (L). The truth table inFIG.9Dshows the relation between the signals input to the input terminal D and the input terminal E and the signals output from the output terminal Z.

FIG.10Ashows a symbol representing the NAND circuit51, andFIG.10Bis a circuit diagram illustrating a structure example of the NAND circuit51. As illustrated inFIG.10B, the NAND circuit51includes a transistor61to a transistor64and a capacitor C61. The transistor61to the transistor64are n-channel transistors. Furthermore, the NAND circuit51includes an input terminal A, an input terminal B, and an input terminal C1and an input terminal C2to which a control signal S_C1and a control signal S_C2are input, and outputs a signal from an output terminal X.

FIG.10Cis a timing chart showing a relation between the control signal S_C1and the control signal S_C2input to the NAND circuit51, an input period PDI of signals input to the input terminal A and the input terminal B, and an output period PDO of the NAND circuit51. Since the high levels and the low levels of the control signal S_C1, the control signal S_C2, and the input signals are represented by the potential VDD and the potential VSS, they are expressed as Vdd (H) and Vss (L) inFIG.10C.

FIG.10Dis a truth table where outputs with respect to the signals input to the NAND circuit51are expressed as high levels (H) and low levels (L). The truth table inFIG.10Dshows the relation between the signals input to the input terminal A and the input terminal B and the signals output to the output terminal X.

FIG.11Ashows a symbol representing the delay circuit52, andFIG.11Bis a circuit diagram illustrating a structure example of the delay circuit52. As illustrated inFIG.11B, the delay circuit52includes a transistor71, a transistor72, and a capacitor C71. The transistor71and the transistor72are n-channel transistors. Furthermore, the delay circuit52includes an input terminal C and an input terminal C3and an input terminal C4to which a control signal S_C3and a control signal S_C4are input, and outputs a signal from an output terminal Y.

FIG.11Cis a timing chart showing a relation between the control signal S_C3and the control signal S_C4input to the delay circuit52, an input period PDI of signals input to the input terminal C, and an output terminal PDO of the delay circuit52. Since the high levels and the low levels of the control signal S_C3, the control signal S_C4, and the input signals are represented by the potential VDD and the potential VSS, they are expressed as Vdd (H) and Vss (L) inFIG.11C.

FIG.11Dis a truth table where outputs with respect to the signals input to the delay circuit52are expressed as high levels (H) and low levels (L). The truth table inFIG.11Dshows the relation between the signals input to the input terminal C and the signals output from the output terminal Y.

<Memory Device>

In the memory device of one embodiment of the present invention, an OS transistor with an extremely low off-state current is used as a transistor provided in each element layer. Since the OS transistor can be stacked over a silicon substrate where a Si transistor is provided, for example, and accordingly can be manufactured in the vertical direction with the same manufacture process repeatedly, resulting in a reduction in the manufacturing cost. In the memory device of one embodiment of the present invention, the transistors included in the memory cells can be arranged not in the plane direction but in the vertical direction, so that the memory density can be improved. Consequently, the memory device can be downsized.

In addition, the memory device of one embodiment of the present invention includes the check bit generation circuit, a check bit, and an error detection circuit. Thus, the memory device of one embodiment of the present invention can conduct a parity check as well as data writing and reading inside the memory device. The check bit generation circuit and the error detection circuit can also be formed using OS transistors; thus, the circuits can be arranged in the vertical direction, so that the memory device can be downsized.

Note that this embodiment can be implemented in combination with the other embodiments described in this specification as appropriate.

Embodiment 2

In this embodiment, a modification example of a circuit applicable to the memory device10A described in Embodiment 1 will be described with reference toFIG.12.

InFIG.2and the like, the transistor with a top gate structure or a bottom gate structure without a back gate electrode is shown as the transistors included in the memory cell31_1to the memory cell31_N and the element layer26. For example, as in a memory device10C illustrated inFIG.12, a transistor with a back gate electrode connected to a back gate electrode line BGL may be used. With the structure illustrated inFIG.12, the threshold voltage of the transistor can be controlled from the outside.

Note that this embodiment can be implemented in combination with the other embodiments described in this specification as appropriate.

Embodiment 3

An example of a memory device of one embodiment of the present invention will be described below.

FIG.13illustrates an example of a memory device in which memory units470(a memory unit470_1to a memory unit470_m: m is a natural number greater than or equal to 1) are stacked over an element layer411including a circuit provided using a semiconductor substrate311.FIG.13shows an example in which the element layer411and a plurality of memory units470over the element layer411are stacked, and each of the memory units470is provided with one transistor layer413(any one of a transistor layer413_1to a transistor layer413_m) and a plurality of memory device layers415(a memory device layer415_1to a memory device layer415n: n is a natural number greater than or equal to 2) over the transistor layer413. Although the example in which the memory device layers415are provided over the transistor layer413in each of the memory units470is shown, this embodiment is not limited thereto. The transistor layer413may be provided over the plurality of memory device layers415, or the memory device layers415may be provided over and below the transistor layer413.

The element layer411includes a transistor300provided on the semiconductor substrate311and can function as a peripheral circuit of the memory device. Examples of the peripheral circuit include a column driver, a row driver, a column decoder, a row decoder, an amplifier circuit, an input/output circuit, and a control logic circuit.

Each transistor layer413includes a transistor200T and can function as a circuit for controlling each of the memory units470. Each memory device layer415includes a memory device420. The memory device420shown in this embodiment includes a transistor200M and a capacitor292.

Although there is no particular limitation on a value of the above m, m is greater than or equal to 1 and less than or equal to 100, preferably greater than or equal to 1 and less than or equal to 50, further preferably greater than or equal to 1 and less than or equal to 10. Although there is no particular limitation on a value of the above n, n is greater than or equal to 2 and less than or equal to 100, preferably greater than or equal to 2 and less than or equal to 50, further preferably greater than or equal to 2 and less than or equal to 100. The product of m and n is greater than or equal to 2 and less than or equal to 256, preferably greater than or equal to 2 and less than or equal to 128, further preferably greater than or equal to 2 and less than or equal to 64.

FIG.13is a cross-sectional view in the channel length direction of the transistor200T and the transistor200M in the memory unit470.

As illustrated inFIG.13, the transistor300is provided on the semiconductor substrate311, the transistor layer413and the memory device layer415included in the memory unit470are provided over the transistor300, and in one memory unit470, the transistor200T included in the transistor layer413and the memory device420included in the memory device layer415are electrically connected via a plurality of conductors424. The transistor300and the transistor200T included in the transistor layer413in each memory unit470are electrically connected via a conductor426. It is preferable that the conductor426be electrically connected to the transistor200T via a conductor428electrically connected to any one of a source, a drain, and a gate of the transistor200T. It is preferable that the conductor424be provided in each memory device layer415. Furthermore, it is preferable that the conductor426be provided in each transistor layer413and each memory device layer415.

Although details are described later, it is preferable to provide an insulator that inhibits the passage of oxygen or impurities such as water or hydrogen on side surfaces of the conductor424and the conductor426. As such insulators, silicon nitride, aluminum oxide, or silicon nitride oxide may be used.

The memory device420includes the transistor200M and the capacitor292, and the transistor200M can have a structure similar to that of the transistor200T included in the transistor layer413. The transistor200T and the transistor200M are collectively referred to as the transistor200, in some cases.

Here, in the transistor200, a semiconductor which includes a region where a channel is formed is preferably formed using a metal oxide functioning as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor).

As the oxide semiconductor, for example, a metal oxide such as an In-M-Zn oxide (the element M is one or more of aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like) is preferably used. As the oxide semiconductor, an indium oxide, an In—Ga oxide or an In—Zn oxide may be used. Note that when an oxide semiconductor having high proportion of indium is used, the on-state current, the field-effect mobility, or the like of the transistor can be increased.

The transistor200using an oxide semiconductor in its channel formation region has an extremely low leakage current in an off state; thus, a memory device with low power consumption can be provided. An oxide semiconductor can be deposited by a sputtering method or the like, and thus can be used for the transistor200included in a highly integrated memory device.

In contrast, a transistor including an oxide semiconductor easily has normally-on characteristics (characteristics such that a channel exists without voltage application to a gate electrode and a current flows in a transistor) owing to an impurity and an oxygen vacancy in the oxide semiconductor that affect the electrical characteristics.

In view of this, an oxide semiconductor with a reduced impurity concentration and a reduced density of defect states is preferably used. Note that in this specification and the like, a state with a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic state.

Accordingly, the impurity concentration in the oxide semiconductor is preferably reduced as much as possible. Examples of impurities contained in the oxide semiconductor include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, and silicon.

Specifically, hydrogen as an impurity which is contained in the oxide semiconductor might form an oxygen vacancy (also referred to as Vo) in the oxide semiconductor. In some cases, a defect that is an oxygen vacancy into which hydrogen enters (hereinafter sometimes referred to as VoH) generates an electron serving as a carrier. In other cases, reaction between part of hydrogen and oxygen bonded to a metal atom generates an electron serving as a carrier.

Thus, a transistor including an oxide semiconductor with a high hydrogen content is likely to be normally on. Hydrogen in the oxide semiconductor is easily transferred by a stress such as heat or an electric field; thus, a high hydrogen content in the oxide semiconductor might reduce the reliability of the transistor.

Therefore, the transistor200preferably uses a highly purified intrinsic oxide semiconductor in which oxygen vacancies and impurities such as hydrogen are reduced.

<Sealing Structure>

In view of the above, the transistor200is preferably sealed using a material that inhibits diffusion of impurities (hereinafter also referred to as an impurity barrier material) in order to inhibit entry of impurities from the outside.

Note that in this specification and the like, a barrier property means a function of inhibiting diffusion of a targeted substance (or low permeability). Alternatively, a barrier property means a function of trapping and fixing (or gettering) a targeted substance.

Examples of a material that has a function of inhibiting diffusion of hydrogen and oxygen include aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide. It is particularly preferable to use silicon nitride or silicon nitride oxide as a sealing material because of their high barrier properties against hydrogen.

Examples of a material having a function of trapping and fixing hydrogen include metal oxides such as aluminum oxide, hafnium oxide, gallium oxide, and indium gallium zinc oxide.

As layers having a barrier property, an insulator211, an insulator212, and an insulator214are preferably provided between the transistor300and the transistor200. A material that inhibits the diffusion or passage of impurities such as hydrogen is used for at least one of the insulator211, the insulator212, and the insulator214, whereby impurities such as hydrogen or water included in the semiconductor substrate311, the transistor300, or the like can be inhibited from being diffused into the transistor200. Furthermore, a material that inhibits the passage of oxygen is used for at least one of the insulator211, the insulator212, and the insulator214, whereby oxygen included in the channel of the transistor200or the transistor layer413can be inhibited from being diffused into the element layer411. For example, it is preferable to use a material that inhibits the passage of impurities such as hydrogen or water for the insulator211and the insulator212and to use a material that inhibits the passage of oxygen for the insulator214. Furthermore, it is further preferable to use a material having a property of extracting and occluding hydrogen for the insulator214. As the insulator211and the insulator212, a nitride such as silicon nitride or silicon nitride oxide can be used, for example. As the insulator214, a metal oxide such as aluminum oxide, hafnium oxide, gallium oxide, or indium gallium zinc oxide can be used, for example. In particular, aluminum oxide is preferably used for the insulator214.

In addition, an insulator287is preferably provided on a side surface of each transistor layer413and a side surface of each memory device layer415, that is, a side surface of each memory unit470, and an insulator282is preferably provided on an top surface of the memory unit470. In this structure, the insulator282is preferably in contact with the insulator287, and the insulator287is preferably in contact with at least one of the insulator211, the insulator212, and the insulator214. For the insulator287and the insulator282, a material that can be used for the insulator214is preferably used.

An insulator283and an insulator284are preferably provided to cover the insulator282and the insulator287, and the insulator283is preferably in contact with at least one of the insulator211, the insulator212, and the insulator214.FIG.13shows an example in which the insulator287is in contact with a side surface of the insulator214, a side surface of the insulator212, and a top surface and a side surface of the insulator211and in which the insulator283is in contact with a side surface of the insulator287and the top surface of the insulator211; however, this embodiment is not limited to this structure. The insulator287may be in contact with the side surface of the insulator214and a top surface and the side surface of the insulator212, and the insulator283may be in contact with the side surface of the insulator287and the top surface of the insulator212. For the insulator282and the insulator287, a material that can be used for the insulator211and the insulator212is preferably used.

In the above structure, a material that can inhibit the passage of oxygen is preferably used for the insulator287and the insulator282. For the insulator287and the insulator282, it is further preferable to use a material having a property of trapping and fixing hydrogen. When a material having a function of trapping and fixing hydrogen is used on a side closer to the transistor200, hydrogen in the transistor200or the memory unit470is trapped and fixed by the insulator214, the insulator287, and the insulator282, whereby the hydrogen concentration in the transistor200can be reduced. Furthermore, for the insulator283and the insulator284, a material that inhibits the passage of impurities such as hydrogen or water is preferably used.

With the above structure, the memory unit470is surrounded by the insulator211, the insulator212, the insulator214, the insulator287, the insulator282, the insulator283, and the insulator284. Specifically, the memory unit470is surrounded by the insulator214, the insulator287, and the insulator282(denoted by a first structure body in some cases), the memory unit470and the first structure body are surrounded by the insulator211, the insulator212, the insulator283, and the insulator284(denoted by a second structure body in some cases). Such a structure in which the memory unit470is surrounded by two or more structure bodies is referred to as a nested structure in some cases. Here, a state where the memory unit470is surrounded by a plurality of structure bodies is denoted by a state where the memory unit470is sealed by a plurality of insulators, in some cases.

The second structure body seals the transistor200with the first structure body therebetween. Thus, the second structure body inhibits hydrogen existing outward the second structure body from being diffused into an inside of the second structure body (to the transistor200side). That is, the first structure body can efficiently trap and fix hydrogen existing in an internal structure of the second structure body.

In the above structure, specifically, a metal oxide such as aluminum oxide can be used for the first structure body and a nitride such as silicon nitride can be used for the second structure body. More specifically, an aluminum oxide film is preferably provided between the transistor200and a silicon nitride film.

Furthermore, by appropriately setting deposition conditions for the material used for the structure bodies, their hydrogen concentrations can be reduced.

In general, a film deposited by a CVD method has more favorable coverage than a film deposited by a sputtering method. On the other hand, many compound gases used for a CVD method contain hydrogen and a film deposited by a CVD method has higher hydrogen content than a film formed by a sputtering method.

Accordingly, it is preferable to use a film with a reduced hydrogen concentration (specifically, a film formed by a sputtering method) as a film which is close to the transistor200, for example. Meanwhile, in the case where a film that has favorable coverage as well as a relatively high hydrogen concentration (specifically, a film deposited by a CVD method) is used as a film for inhibiting impurity diffusion, it is preferable that a film having a function of trapping and fixing hydrogen and a reduced hydrogen concentration be provided between the transistor200and the film that has favorable coverage as well as a relatively high hydrogen concentration.

In other words, a film with a relatively low hydrogen concentration is preferably used as the film which is close to the transistor200. In contrast, a film with a relatively high hydrogen concentration is preferably provided apart from the transistor200.

When the above structure is employed and specifically, the transistor200is sealed with a silicon nitride film deposited by a CVD method, an aluminum oxide film deposited by a sputtering method is preferably provided between the transistor200and the silicon nitride film deposited by a CVD method. It is further preferable that a silicon nitride film deposited by a sputtering method be provided between the silicon nitride film deposited by a CVD method and the aluminum oxide film deposited by a sputtering method.

Note that in the case where a CVD method is employed for deposition, a compound gas containing no hydrogen atom or having a low hydrogen atom content may be used for the deposition to reduce the hydrogen concentration of the deposited film.

Furthermore, the insulator282and the insulator214are preferably provided also between each transistor layer413and the memory device layer415or between the memory device layers415. Moreover, an insulator296is preferably provided between the insulator282and the insulator214. A material similar to that for the insulator283and the insulator284can be used for the insulator296. Alternatively, silicon oxide or silicon oxynitride can be used. Alternatively, a known insulating material may be used. Here, the insulator282, the insulator296, and the insulator214may be elements included in the transistor200. The insulator282, the insulator296, and the insulator214preferably serve as component elements of the transistor200because the number of steps needed to manufacture the memory device can be reduced.

It is preferable that the insulator287be in contact with the side surfaces of the insulator282, the insulator296, and the insulator214provided between each transistor layer413and the memory device layer415or between the memory device layers415. With such a structure, each transistor layer413and each memory device layer415are surrounded and sealed by the insulator282, the insulator296, the insulator214, the insulator287, the insulator283, and the insulator284.

Furthermore, an insulator274may be provided around the insulator284. Moreover, a conductor430may be provided to be embedded in the insulator274, the insulator284, the insulator283, and the insulator211. The conductor430is electrically connected to the transistor300, that is, the circuit included in the element layer411.

In each memory device layer415, the capacitor292is formed in the layer where the transistor200M is provided, and accordingly, the height of the memory device420can be almost the same as that of the transistor200M, which enables each memory device layer415to be prevented from having excessively large height. Thus, the number of memory device layers415can be increased relatively easily. For example, the number of stacked structures each including the transistor layer413and the memory device layers415can be approximately 100.

<Transistor200>

With reference toFIG.14A, will be described the transistor200that can be used for the transistor200T included in the transistor layer413and the transistor200M included in the memory device420.

As illustrated inFIG.14A, the transistor200includes an insulator216, a conductor205(a conductor205aand a conductor205b), an insulator222, an insulator224, an oxide230(an oxide230a, an oxide230b, and an oxide230c), a conductor242(a conductor242aand a conductor242b), an oxide243(an oxide243aand an oxide243b), an insulator272, an insulator273, an insulator250, and a conductor260(a conductor260aand a conductor260b).

The insulator216and the conductor205are provided over the insulator214, and an insulator280and the insulator282are provided over the insulator273. The insulator214, the insulator280, and the insulator282can be regarded as part of the transistor200.

The memory device of one embodiment of the present invention also includes a conductor240(a conductor240aand a conductor240b) electrically connected to the transistor200and functioning as a plug. Note that an insulator241(an insulator241aand an insulator241b) is provided in contact with a side surface of the conductor240functioning as a plug. A conductor246(a conductor246aand a conductor246b) electrically connected to the conductor240and functioning as a wiring is provided over the insulator282and the conductor240.

The conductor240aand the conductor240bare each preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. The conductor240aand the conductor240bmay have a stacked-layer structure.

When the conductor240has a stacked-layer structure, it is preferable to use a conductive material having a function of inhibiting penetration of oxygen and impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used. The conductive material having a function of inhibiting penetration of oxygen and impurities such as water and hydrogen may have a single-layer structure or a stacked-layer structure. With use of the conductive material, entry of impurities such as water and hydrogen diffused from the insulator280or the like into the oxide230through the conductor240aand the conductor240bcan be further reduced. Furthermore, oxygen added to the insulator280can be prevented from being absorbed by the conductor240aand the conductor240b.

For the insulator241provided in contact with the conductor240, for example, silicon nitride, aluminum oxide, silicon nitride oxide, or the like can be used. Since the insulator241is provided in contact with the insulator272and the insulator273, the insulator280, and the insulator282, impurities such as water or hydrogen can be inhibited from being mixed into the oxide230through the conductor240aand the conductor240bfrom the insulator280or the like. In particular, silicon nitride is suitable because of its high hydrogen blocking property. Furthermore, oxygen contained in the insulator280can be prevented from being absorbed by the conductor240aand the conductor240b.

The conductor246is preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. Furthermore, the conductor may have a stacked-layer structure and may be a stack of titanium or titanium nitride and any of the above conductive materials, for example. Note that the conductor may be embedded in an opening provided in an insulator.

In the transistor200, the conductor260functions as a first gate of the transistor and the conductor205functions as a second gate of the transistor. The conductor242aand the conductor242bserve as a source electrode and a drain electrode.

The oxide230functions as a semiconductor including a channel formation region.

The insulator250function as a first gate insulator, and the insulator222and the insulator224function as a second gate insulator.

Here, in the transistor200illustrated inFIG.14A, the conductor260is formed in a self-aligned manner in an opening provided in the insulator280, the insulator273, the insulator272, the conductor242, and the like, with the oxide230cand the insulator250positioned therebetween.

In other words, the conductor260is formed to fill the opening provided in the insulator280and the like, with the oxide230cand the insulator250positioned therebetween; therefore, alignment of the conductor260in the region between the conductor242aand the conductor242bis not needed.

The oxide230cis preferably provided in the opening that is provided in the insulator280and the like. Thus, the insulator250and the conductor260include a region that overlaps with a stacked-layer structure of the oxide230band the oxide230awith the oxide230ctherebetween. When this structure is employed, the oxide230cand the insulator250can be sequentially formed and thus, the interface between the oxide230and the insulator250can be kept clean. Accordingly, the influence of interface scattering on carrier conduction is small, and the transistor200can have a high on-state current and high frequency characteristics.

In the transistor200illustrated inFIG.14A, a bottom surface and a side surface of the conductor260are in contact with the insulator250. Furthermore, a bottom surface and a side surface of the insulator250are in contact with the oxide230c.

In addition, the insulator282and the oxide230care in direct contact with each other in the transistor200as illustrated inFIG.14A. Owing to this structure, diffusion of oxygen contained in the insulator280to the conductor260can be inhibited.

Therefore, oxygen contained in the insulator280can be efficiently supplied to the oxide230aand the oxide230bthrough the oxide230c, which can reduce oxygen vacancies in the oxide230aand the oxide230band improve the electrical characteristics and reliability of the transistor200.

The structure of the memory device including the transistor200of one embodiment of the present invention is described in detail below.

In the transistor200, an oxide semiconductor is preferably used as the oxide230(the oxide230a, the oxide230b, and the oxide230c) including a channel formation region.

For example, the metal oxide functioning as an oxide semiconductor preferably has an energy gap of 2 eV or more, further preferably 2.5 eV or more. With use of a metal oxide having a wide energy gap, leakage current in a non-conduction state (off-state current) of the transistor200can be extremely small. The use of such a transistor can provide a memory device with low power consumption.

Specifically, as the oxide230, a metal oxide such as an In-M-Zn oxide (the element M is one or more of aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like) is preferably used. In particular, aluminum, gallium, yttrium, or tin is preferably used as the element M. Alternatively, an In-M oxide, an In—Zn oxide, or an M-Zn oxide may be used as the oxide230.

As illustrated inFIG.14A, the oxide230preferably includes the oxide230aover the insulator224, the oxide230bover the oxide230a, and the oxide230cthat is over the oxide230band at least part of which is in contact with the top surface of the oxide230b. Note that the side surface of the oxide230cis preferably in contact with the oxide243a, the oxide243b, the conductor242a, the conductor242b, the insulator272, the insulator273, and the insulator280.

That is, the oxide230includes the oxide230a, the oxide230bover the oxide230a, and the oxide230cover the oxide230b. When the oxide230ais provided below the oxide230b, impurities can be inhibited from diffusing into the oxide230bfrom the components formed below the oxide230a. When the oxide230cis provided over the oxide230b, impurities can be inhibited from diffusing into the oxide230bfrom the components formed above the oxide230c.

The transistor200has a structure in which the three layers of the oxide230a, the oxide230b, and the oxide230care stacked in a channel formation region and its vicinity; however, the present invention is not limited to this structure. For example, the transistor200may include a single layer of the oxide230b, a two-layer stack of the oxide230band the oxide230a, a two-layer stack of the oxide230band the oxide230c, or a four or more-layer stack. For example, the transistor200may include a four-layer stack including the oxide230cwith a two-layer structure.

The oxide230preferably has a stacked-layer structure of oxide layers which differ in the atomic ratio of metal atoms. Specifically, the atomic ratio of the element M to constituent elements in the metal oxide used as the oxide230ais preferably greater than that in the metal oxide used as the oxide230b. Moreover, the atomic ratio of the element M to In in the metal oxide used as the oxide230ais preferably greater than that in the metal oxide used as the oxide230b. Moreover, the atomic ratio of In to the element M in the metal oxide used as the oxide230bis preferably greater than that in the metal oxide used as the oxide230a. The oxide230ccan be formed using a metal oxide which can be used as the oxide230aor the oxide230b.

Specifically, for the oxide230a, a metal oxide having In:Ga:Zn=1:3:4 [atomic ratio] or a composition in the vicinity thereof, or 1:1:0.5 [atomic ratio] or a composition in the vicinity thereof is used. As the oxide230b, a metal oxide with In:Ga:Zn=4:2:3 [atomic ratio] or a composition in the vicinity thereof or 1:1:1 [atomic ratio] or a composition in the vicinity thereof is used. As the oxide230c, a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 [atomic ratio] or in the vicinity thereof, In:Ga:Zn=4:2:3 [atomic ratio] or in the vicinity thereof, In:Ga:Zn=5:1:3 [atomic ratio] or in the vicinity thereof, In:Ga:Zn=10:1:3 [atomic ratio] or in the vicinity thereof, Ga:Zn=2:1 [atomic ratio] or in the vicinity thereof, or Ga:Zn=2:5 [atomic ratio] or in the vicinity thereof can be used. When the oxide230chas a stacked-layer structure, a stacked layer structure of a metal oxide having an atomic ratio of In:Ga:Zn=4:2:3 [atomic ratio] or in the vicinity thereof and a metal oxide having an atomic ratio of In:Ga:Zn=1:3:4 [atomic ratio] or in the vicinity thereof, a stacked-layer structure of a metal oxide having an atomic ratio of In:Ga:Zn=4:2:3 [atomic ratio] or in the vicinity thereof and a metal oxide having an atomic ratio of In:Ga:Zn=5:1:3 [atomic ratio] or in the vicinity thereof, a stacked-layer structure of a metal oxide having an atomic ratio of Ga:Zn=2:1 [atomic ratio] or in the vicinity thereof and a metal oxide having an atomic ratio of In:Ga:Zn=4:2:3 [atomic ratio] or in the vicinity thereof, a stacked-layer structure of a metal oxide having an atomic ratio of Ga:Zn=2:5 [atomic ratio] or in the vicinity thereof and a metal oxide having an atomic ratio of In:Ga:Zn=4:2:3 [atomic ratio] or in the vicinity thereof, or a stacked-layer structure of gallium oxide and a metal oxide having an atomic ratio of In:Ga:Zn=4:2:3 [atomic ratio] or in the vicinity thereof can be given as specific examples. Note that a composition in the vicinity includes±30% of an intended atomic ratio.

The oxide230bmay have crystallinity. For example, it is preferable to use a CAAC-OS (c-axis-aligned crystalline oxide semiconductor) described later. An oxide having crystallinity, such as a CAAC-OS, has a dense structure with small amounts of impurities and defects (e.g., oxygen vacancies) and high crystallinity. Accordingly, extraction of oxygen from the oxide230bby the source electrode or the drain electrode can be suppressed. This inhibits extraction of oxygen from the oxide230beven when heat treatment is performed; hence, the transistor200is stable with respect to high temperatures in the manufacturing process (i.e., thermal budget).

The conductor205is positioned to overlap with the oxide230and the conductor260. The conductor205is preferably provided to be embedded in the insulator216.

In the case where the conductor205functions as a gate electrode, by changing a potential applied to the conductor205independently of a potential applied to the conductor260, the threshold voltage (Vth) of the transistor200can be controlled. In particular, by applying a negative potential to the conductor205, Vth of the transistor200can be higher, and its off-state current can be reduced. Thus, a drain current at the time when a potential applied to the conductor260is 0 V can be smaller in the case where a negative potential is applied to the conductor205than in the case where the negative potential is not applied to the conductor205.

As illustrated inFIG.14A, the conductor205is preferably provided to be larger than a region of the oxide230that does not overlap with the conductor242aor the conductor242b. Although not illustrated, the conductor205preferably extends to a region beyond the oxide230aand the oxide230bin the channel width direction of the oxide230. That is, the conductor205and the conductor260preferably overlap with each other with the insulator therebetween, in a region beyond the side surface of the oxide230in the channel width direction. Forming the conductor205with a large area can reduce local charging (charge up) in a treatment using plasma of a manufacturing step after forming the conductor205in some cases. However, one embodiment of the present invention is not limited thereto. The conductor205overlaps with at least the oxide230positioned between the conductor242aand the conductor242b.

When the bottom surface of the insulator224is used as a benchmark, the bottom surface of the conductor260in a region not overlapping with the oxide230aor the oxide230bis preferably positioned below the bottom surface of the oxide230b.

As not illustrated, in the channel width direction, when the conductor260functioning as a gate covers a side surface and a top surface of the oxide230bin the channel formation region with the oxide230cand the insulator250therebetween, the electric field generated from the conductor260is likely to affect the entire channel formation region formed in the oxide230b. Accordingly, the transistor200can have a higher on-state current and higher frequency characteristics. In this specification, such a transistor structure in which the channel formation region is electrically surrounded by the electric fields of conductor260and the conductor205is referred to as surrounded channel (S-channel) structure.

The conductor205apreferably inhibits penetration of oxygen and impurities such as water or hydrogen. For example, the conductor205acan be formed using titanium, titanium nitride, tantalum, or tantalum nitride. The conductor205bis preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. The conductor205has a two-layer structure in the drawing but may have a multilayer structure of three or more layers.

Note that the oxide semiconductor, the insulator or conductor positioned below the oxide semiconductor, and the insulator or conductor positioned over the oxide semiconductor are preferably successively formed without exposure to the air, in which case a substantially highly purified intrinsic oxide semiconductor film with a reduced concentration of impurities (in particular, hydrogen and water) can be formed.

At least one of the insulator222, the insulator272, and the insulator273preferably functions as a barrier insulating film that inhibits entry of impurities such as water or hydrogen into the transistor200from the substrate side or from above the transistor200. Therefore, at least one of the insulator222, the insulator272, and the insulator273is preferably formed using an insulating material having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (e.g., N2O, NO, and NO2), and a copper atom, that is, an insulating material through which the above impurities are less likely to pass. Alternatively, it is preferable to use an insulating material that has a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like) (through which the above oxygen is less likely to pass).

For example, it is preferable that silicon nitride, silicon nitride oxide, or the like be used for the insulator273and that aluminum oxide, hafnium oxide, or the like be used for the insulator222and the insulator272.

Accordingly, it is possible to inhibit diffusion of impurities such as water or hydrogen to the transistor200side from the substrate side through the insulator222. It is also possible to inhibit diffusion of oxygen contained in the insulator224and the like to the substrate side through the insulator222.

Impurities such as water or hydrogen can be inhibited from diffusing to the transistor200side from the insulator280and the like, which are positioned with the insulator272and the insulator273therebetween. In this manner, the transistor200is preferably surrounded by the insulator272and the insulator273that have a function of inhibiting diffusion of oxygen and impurities such as water or hydrogen.

Here, it is preferable that the insulator224in contact with the oxide230release oxygen by heating. In this specification and the like, oxygen that is released by heating is referred to as excess oxygen in some cases. For example, silicon oxide, silicon oxynitride, or the like may be used for the insulator224as appropriate. When such an insulator containing oxygen is provided in contact with the oxide230, oxygen vacancies in the oxide230can be reduced, leading to an improvement in reliability of the transistor200.

Specifically, the insulator224is preferably formed using an oxide material that releases part of oxygen by heating. An oxide that releases oxygen by heating is an oxide film in which the number of released oxygen molecules is greater than or equal to 1.0×1018molecules/cm3, preferably greater than or equal to 1.0×1019molecules/cm3, further preferably greater than or equal to 2.0×1019molecules/cm3or greater than or equal to 3.0×1020molecules/cm3in thermal desorption spectroscopy analysis (TDS analysis). Note that the temperature of the film surface in the TDS analysis is preferably higher than or equal to 100° C. and lower than or equal to 700° C., or higher than or equal to 100° C. and lower than or equal to 400° C.

The insulator222preferably functions as a barrier insulating film that inhibits entry of impurities such as water or hydrogen into the transistor200from the substrate side. For example, the insulator222preferably has a lower hydrogen permeability than the insulator224. When the insulator224, the oxide230, and the like are surrounded by the insulator222and the insulator273, entry of impurities such as water or hydrogen into the transistor200from the outside can be inhibited.

Furthermore, the insulator222preferably has a function of inhibiting diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like); that is, it is preferable that oxygen is less likely to pass through the insulator222. For example, the insulator222preferably has a lower oxygen permeability than the insulator224. The insulator222preferably has a function of inhibiting diffusion of oxygen or impurities, in which case diffusion of oxygen contained in the oxide230into a layer under the insulator222can be reduced. Furthermore, the conductor205can be inhibited from reacting with oxygen in the insulator224or the oxide230.

As the insulator222, an insulator containing an oxide of one or both of aluminum and hafnium that is an insulating material is preferably used. For the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. The insulator222formed of such a material functions as a layer that inhibits release of oxygen from the oxide230and entry of impurities such as hydrogen from the periphery of the transistor200into the oxide230.

Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator, for example. Alternatively, the insulator may be subjected to nitriding treatment. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the insulator.

The insulator222may have a single-layer structure or a stacked-layer structure using an insulator containing what is called a high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3(BST). With miniaturization and high integration of a transistor, a problem such as generation of leakage current may arise because of a thin gate insulator. When a high-k material is used for an insulator functioning as the gate insulator, a gate potential at the time of operating the transistor can be reduced while the physical thickness of the gate insulator is kept.

Note that the insulator222and the insulator224may each have a stacked-layer structure of two or more layers. In that case, the stacked layers are not necessarily formed of the same material and may be formed of different materials.

The oxide243(the oxide243aand the oxide243b) may be positioned between the oxide230band the conductor242(the conductor242aand the conductor242b) which functions as the source electrode or the drain electrode. This structure in which the conductor242and the oxide230bare not in contact with each other can prevent the conductor242from absorbing oxygen in the oxide230b. That is, preventing the oxidation of the conductor242can inhibit a decrease in the conductivity of the conductor242. Accordingly, the oxide243preferably has a function of inhibiting the oxidation of the conductor242.

The oxide243having a function of inhibiting penetration of oxygen is preferably provided between the oxide230band the conductor242functioning as the source electrode and the drain electrode, in which case the electric resistance between the conductor242and the oxide230bcan be reduced. Such a structure improves the electrical characteristics of the transistor200and reliability of the transistor200.

As the oxide243, for example, a metal oxide including an element M that is one or more kinds selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like is preferably used. In particular, aluminum, gallium, yttrium, or tin is preferably used as the element M. The concentration of the element M in the oxide243is preferably higher than that in the oxide230b. Alternatively, gallium oxide may be used for the oxide243. Further alternatively, a metal oxide such as an In-M-Zn oxide may be used for the oxide243. Specifically, the atomic ratio of the element M to In in the metal oxide used for the oxide243is preferably higher than that in the metal oxide used for the oxide230b. The thickness of the oxide243is preferably greater than or equal to 0.5 nm and less than or equal to 5 nm, further preferably greater than or equal to 1 nm and less than or equal to 3 nm. The oxide243preferably has crystallinity. With the oxide243having crystallinity, release of oxygen in the oxide230can be favorably inhibited. When the oxide243has a hexagonal crystal structure, for example, release of oxygen in the oxide230can sometimes be inhibited.

Note that the oxide243is not necessarily provided. In that case, contact between the conductor242(the conductor242aand the conductor242b) and the oxide230may make oxygen in the oxide230diffuse into the conductor242, resulting in oxidation of the conductor242. It is highly probable that oxidation of the conductor242lowers the conductivity of the conductor242. Note that the expression “oxygen in the oxide230diffuses into the conductor242” can be replaced with the expression “the conductor242absorbs oxygen in the oxide230”.

When oxygen in the oxide230is diffused into the conductor242(the conductor242aand the conductor242b), another layer is sometimes formed between the conductor242aand the oxide230b, and between the conductor242band the oxide230b. The another layer contains a larger amount of oxygen than the conductor242and thus presumably has an insulating property. In that case, a three-layer structure of the conductor242, the another layer, and the oxide230bcan be regarded as a three-layer structure of a metal, an insulator, and a semiconductor and is sometimes referred to as an MIS (Metal-Insulator-Semiconductor) structure or a diode-connected structure mainly with an MIS structure.

The another layer is not necessarily formed between the conductor242and the oxide230b; for example, the another layer may be formed between the conductor242and the oxide230cor formed between the conductor242and the oxide230band between the conductor242and the oxide230c.

The conductor242(the conductor242aand the conductor242b) functioning as the source electrode and the drain electrode is provided over the oxide243. The thickness of the conductor242is greater than or equal to 1 nm and less than or equal to 50 nm, preferably greater than or equal to 2 nm and less than or equal to 25 nm, for example.

For the conductor242, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum; an alloy containing any of the above metal elements; an alloy containing a combination of the above metal elements; or the like. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like is preferably used. Tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are preferable because they are oxidation-resistant conductive materials or materials that retain their conductivity even after absorbing oxygen.

It is preferable that the insulator272be provided in contact with the top surface of the conductor242and function as a barrier layer. Such a structure can inhibit the conductor242from absorbing excess oxygen contained in the insulator280. Furthermore, inhibiting the oxidation of the conductor242can suppress an increase in the contact resistance between the transistor200and the wiring. Accordingly, the transistor200can have excellent electrical characteristics and reliability.

Thus, the insulator272preferably has a function of inhibiting oxygen diffusion. For example, the insulator272preferably has a function of further inhibiting diffusion of oxygen as compared to the insulator280. For example, an insulator containing an oxide of one or both of aluminum and hafnium is preferably formed as the insulator272. For another example, an insulator containing aluminum nitride may be used as the insulator272.

As illustrated inFIG.14A, the insulator272is in contact with part of the top surface of the conductor242band the side surface of the conductor242b. In addition, although not illustrated, the insulator272is in contact with part of the top surface of the conductor242aand the side surface the conductor242a. The insulator273is provided over the insulator272. Such a structure can inhibit the conductor242from absorbing oxygen added to the insulator280, for example.

The insulator250functions as a gate insulator. The insulator250is preferably in contact with a top surface of the oxide230c. The insulator250can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or porous silicon oxide. In particular, silicon oxide and silicon oxynitride, which have thermal stability, are preferable.

Like the insulator224, the insulator250is preferably formed using an insulator from which oxygen is released by heating. When the insulator from which oxygen is released by heating is provided as the insulator250to be in contact with the top surface of the oxide230c, oxygen can be effectively supplied to the channel formation region of the oxide230b. Furthermore, as in the insulator224, the concentration of impurities such as water or hydrogen in the insulator250is preferably lowered. The thickness of the insulator250is preferably greater than or equal to 1 nm and less than or equal to 20 nm.

A metal oxide may be provided between the insulator250and the conductor260. The metal oxide preferably prevents oxygen diffusion from the insulator250into the conductor260. Providing the metal oxide that inhibits oxygen diffusion inhibits diffusion of oxygen from the insulator250to the conductor260. That is, the reduction in the amount of oxygen supplied to the oxide230can be inhibited. Moreover, oxidation of the conductor260due to oxygen in the insulator250can be inhibited.

The metal oxide functions as part of the gate insulator in some cases. For that reason, when silicon oxide, silicon oxynitride, or the like is used for the insulator250, the metal oxide is preferably a high-k material with a high dielectric constant. The gate insulator having a stacked-layer structure of the insulator250and the metal oxide can be thermally stable and have a high dielectric constant. Accordingly, a gate potential that is applied during operation of the transistor can be reduced while the physical thickness of the gate insulator is kept. In addition, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced.

Specifically, a metal oxide containing one or more of hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like can be used. It is particularly preferable to use an insulator containing an oxide of one or both of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate).

The metal oxide functions as part of the gate in some cases. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. When the conductive material containing oxygen is provided on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

It is particularly preferable to use, for the conductor functioning as the gate, a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed. A conductive material containing any of the above metal elements and nitrogen may also be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon is added may be used. Indium gallium zinc oxide containing nitrogen may also be used. With use of such a material, hydrogen contained in the metal oxide in which a channel is formed can be captured in some cases. Alternatively, hydrogen entering from an external insulator or the like can be captured in some cases.

Although the conductor260has a two-layer structure inFIG.14A, a single-layer structure or a stacked-layer structure of three or more layers may be employed.

The conductor260ais preferably formed using a conductive material having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (e.g., N2O, NO, and NO2), and a copper atom. Alternatively, it is preferable to use a conductive material having a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like).

When the conductor260ahas a function of inhibiting diffusion of oxygen, the conductivity can be prevented from being lowered because of oxidization of the conductor260bdue to oxygen in the insulator250. As a conductive material having a function of inhibiting oxygen diffusion, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used, for example.

Furthermore, the conductor260bis preferably formed using a conductive material including tungsten, copper, or aluminum as its main component. The conductor260also functions as a wiring, and thus a conductor having high conductivity is preferably used for the conductor260b. For example, a conductive material containing tungsten, copper, or aluminum as its main component can be used. The conductor260bmay have a stacked-layer structure, for example, a stacked-layer structure of titanium or titanium nitride and the above conductive material.

<Metal Oxide>

As the oxide230, a metal oxide functioning as an oxide semiconductor is preferably used. A metal oxide that can be used as the oxide230according to the present invention is described below.

The metal oxide contains preferably at least indium or zinc and particularly preferably indium and zinc. Moreover, gallium, yttrium, tin, or the like is preferably contained in addition to them. Furthermore, one or more kinds selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like may be contained.

Here the case where the metal oxide is an In-M-Zn oxide containing indium, an element M, and zinc (the element M is one or more kinds selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like) is considered. In particular, aluminum, gallium, yttrium, or tin is preferably used as the element M.

Note that in this specification and the like, a metal oxide containing nitrogen is also collectively referred to as a metal oxide in some cases. A metal oxide containing nitrogen may be referred to as a metal oxynitride.

<Transistor300>

The transistor300will be described with reference toFIG.14B. The transistor300is provided on the semiconductor substrate311and includes a conductor316functioning as a gate, an insulator315functioning as a gate insulator, a semiconductor region313that is a part of the semiconductor substrate311, and a low-resistance region314aand a low-resistance region314bfunctioning as a source region and a drain region. The transistor300may be a p-channel transistor or an n-channel transistor.

Here, in the transistor300illustrated inFIG.14B, the semiconductor region313(part of the semiconductor substrate311) in which a channel is formed has a convex shape. Furthermore, the conductor316is provided to cover the top and side surfaces of the semiconductor region313with the insulator315therebetween (not shown). Note that the conductor316may be formed using a material for adjusting the work function. The transistor300having such a structure is also referred to as a FIN transistor because the projecting portion of the semiconductor substrate311is utilized. An insulator functioning as a mask for forming the projecting portion may be provided in contact with the top surface of the projecting portion. Although the case where the projecting portion is formed by processing part of the semiconductor substrate311is described here, a semiconductor film having a projecting shape may be formed by processing an SOI substrate.

Note that the transistor300illustrated inFIG.14Bis an example and the structure is not limited thereto; an appropriate transistor may be used in accordance with a circuit configuration or a driving method.

<Memory Device420>

Next, the memory device420illustrated inFIG.13will be described with reference toFIG.15A. Note that as for the description of the transistor200M included in the memory device420, the same description as that for the transistor200is omitted here.

In the memory device420, the conductor242aof the transistor200M functions as one of electrodes of the capacitor292, and the insulator272and the insulator273function as a dielectric. A conductor290is provided to overlap with the conductor242awith the insulator272and the insulator273positioned therebetween and functions as the other electrode of the capacitor292. The conductor290may be used as the other electrode of the capacitor292in the adjacent memory device420. Alternatively, the conductor290may be electrically connected to the conductor290included in the adjacent memory device420.

The conductor290is provided not only over the top surface of the conductor242abut also on the side surface side of the conductor242aso that the insulator272and the insulator273are positioned therebetween. This structure is preferable because the capacitor292can obtain capacitance higher than that obtained depending on an area where the conductor242aand the conductor290overlap with each other.

The conductor424is electrically connected to the conductor242band is also electrically connected to another conductor424positioned in a lower layer with the conductor205positioned therebetween.

As a dielectric of the capacitor292, silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, or the like can be used. Alternatively, a stack of these materials can be used. In the case where a dielectric of the capacitor292has a stacked-layer structure, a stack of aluminum oxide and silicon nitride or a stack of hafnium oxide and silicon oxide can be used. The stacking order is not limited. For example, silicon nitride may be stacked over aluminum oxide, or aluminum oxide may be stacked over silicon nitride.

Alternatively, as a dielectric of the capacitor292, zirconium oxide having a higher dielectric constant than the above material may be used. As a dielectric of the capacitor292, zirconium oxide may be used as a single layer or part of a stacked layer. For example, a stacked layer of zirconium oxide and aluminum oxide can be used. The capacitor292may have a stacked layer including three layers, in which zirconium oxide is used for the first layer and the third layer, and aluminum oxide is used for the second layer between the first layer and the third layer.

When zirconium oxide having a high dielectric constant is used as a dielectric of the capacitor292, the area occupied by the capacitor292in the memory device420can be reduced. Thus, the area necessary for the memory device420can be reduced, which is preferable because the bit cost can be improved.

For the conductor290, a material that can be used for the conductor205, the conductor242, the conductor260, the conductor424, or the like can be used.

In this embodiment, an example in which the transistors200M and the capacitors292are arranged symmetrically with the conductor424positioned therebetween is shown. When a pair of the transistors200M and a pair of the capacitors292are arranged in this manner, the number of conductors424electrically connected to the transistor200M can be reduced. Thus, the area necessary for the memory device420can be downsized, which is preferable because the bit cost can be improved.

In the case where the insulator241is provided on the side surface of the conductor424, the conductor424is connected to at least part of a top surface of the conductor242b.

With use of the conductor424and the conductor205, the transistor200T and the memory device420in the memory unit470can be electrically connected to each other.

<Modification Example 1 of Memory Device420>

Next, as a modification example of the memory device420, a memory device420A will be described with reference toFIG.15B. The memory device420A includes the transistor200M and a capacitor292A electrically connected to the transistor200M. The capacitor292A is provided below the transistor200M.

In the memory device420A, the conductor242ais positioned in an opening provided in the oxide243a, the oxide230b, the oxide230a, the insulator224, and the insulator222and is electrically connected to the conductor205at a bottom surface of the opening. The conductor205is electrically connected to the capacitor292A.

The capacitor292A includes a conductor294functioning as one of electrodes, an insulator295functioning as a dielectric, and a conductor297functioning as the other electrode. The conductor297overlaps with the conductor294with the insulator295positioned therebetween. The conductor297is electrically connected to the conductor205.

The conductor294is provided on a bottom surface and a side surface of an opening formed in an insulator298over the insulator296, and the insulator295is provided to cover the insulator298and the conductor294. The conductor297is provided to be embedded in a depression portion in the insulator295.

In addition, a conductor299is provided to be embedded in the insulator296, and the conductor299is electrically connected to the conductor294. The conductor299may be electrically connected to the conductor294in the adjacent memory device420A.

The conductor297is provided not only over a top surface of the conductor294but also on a side surface side of the conductor294so that the insulator295is positioned therebetween. This structure is preferable because the capacitor292A can obtain capacitance higher than that obtained depending on an area where conductor294and the conductor297overlap with each other.

As the insulator295functioning as a dielectric of the capacitor292A, silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, or the like can be used. Alternatively, a stack of these materials can be used. In the case where the insulator295has a stacked-layer structure, a stack of aluminum oxide and silicon nitride, or a stack of hafnium oxide and silicon oxide can be used. The stacking order is not limited. For example, silicon nitride may be stacked over aluminum oxide, or aluminum oxide may be stacked over silicon nitride.

Alternatively, as the insulator295, zirconium oxide having a higher dielectric constant than the above material may be used. As the insulator295, zirconium oxide may be used as a single layer or part of a stacked layer. For example, a stacked layer of zirconium oxide and aluminum oxide can be used. The insulator295may have a stacked layer including three layers, in which zirconium oxide is used for the first layer and the third layer, and aluminum oxide is used for the second layer between the first layer and the third layer.

When zirconium oxide having a high dielectric constant is used as the insulator295, the area occupied by the capacitor292A in the memory device420A can be reduced. Thus, the area necessary for the memory device420A can be downsized, which is preferable because the bit cost can be improved.

For the conductor297, the conductor294, and the conductor299, a material that can be used for the conductor205, the conductor242, the conductor260, the conductor424, and the like can be used.

For the insulator298, a material that can be used for the insulator214, the insulator216, the insulator224, the insulator280, and the like can be used.

<Modification Example 2 of Memory Device420>

Next, as a modification example of the memory device420, a memory device420B will be described with reference toFIG.15C. The memory device420B includes the transistor200M and a capacitor292B that is electrically connected to the transistor200M. The capacitor292B is provided above the transistor200M.

The capacitor292B includes a conductor276functioning as one of electrodes, an insulator277functioning as a dielectric, and a conductor278functioning as the other electrode. The conductor278overlaps with the conductor276with the insulator277positioned therebetween.

An insulator275is provided over the insulator282, and the conductor276is provided on a bottom surface and a side surface of an opening formed in the insulator275, the insulator282, the insulator280, the insulator273, and the insulator272. The insulator277is provided to cover the insulator282and the conductor276. The conductor278is provided to overlap with the conductor276in a depression portion in the insulator277, and at least part thereof is provided over the insulator275with the insulator277positioned therebetween. The conductor278may be used as the other electrode of the capacitor292B included in the adjacent memory device420B. Alternatively, the conductor278may be electrically connected to the conductor278included in the adjacent memory device420B.

The conductor278is provided not only over a top surface of the conductor276but also on a side surface side of the conductor276so that the insulator277is positioned therebetween. This structure is preferable because the capacitor292B can obtain capacitance higher than that obtained depending on an area where the conductor276and the conductor278overlap with each other.

In addition, an insulator279may be provided to embed a depression portion in the conductor278.

As the insulator277functioning as a dielectric of the capacitor292B, silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, or the like can be used. Alternatively, a stack of these materials can be used. In the case where the insulator277has a stacked-layer structure, a stack of aluminum oxide and silicon nitride or a stack of hafnium oxide and silicon oxide can be used. The stacking order is not limited. For example, silicon nitride may be stacked over aluminum oxide, or aluminum oxide may be stacked over silicon nitride.

Alternatively, as the insulator277, zirconium oxide having a higher dielectric constant than the above material may be used. As the insulator277, zirconium oxide may be used as a single layer or part of a stacked layer. For example, a stacked layer of zirconium oxide and aluminum oxide can be used. Alternatively, the insulator277may have a stacked layer including three layers, in which zirconium oxide is used for the first layer and the third layer, and aluminum oxide is used for the second layer between the first layer and the third layer.

When zirconium oxide having a high dielectric constant is used for the insulator277, the area occupied by the capacitor292B in the memory device420B can be reduced. Thus, the area necessary for the memory device420B can be reduced, which is preferable because the bit cost can be improved.

For the conductor276and the conductor278, a material that can be used for the conductor205, the conductor242, the conductor260, the conductor424, or the like can be used.

For the insulator275and the insulator279, a material that can be used for the insulator214, the insulator216, the insulator224, the insulator280, and the like can be used.

<Connection of Memory Device420and Transistor200T>

In a region422surrounded by a dashed-dotted line inFIG.13, the memory device420is electrically connected to a gate of the transistor200T via the conductor424and the conductor205; however, this embodiment is not limited thereto.

FIG.16shows an example in which the memory device420is electrically connected to the conductor242bfunctioning as one of a source and a drain of the transistor200T via the conductor424, the conductor205, the conductor246b, and the conductor240b.

As described above, a method for connecting the memory device420and the transistor200T can be determined depending on the function of a circuit included in the transistor layer413.

FIG.17shows an example in which the memory unit470includes the transistor layer413including the transistor200T and four memory devices layer415(the memory device layer415_1to the memory device layer415_4).

Each of the memory device layer415_1to the memory device layer415_4includes a plurality of the memory devices420.

The memory device420is electrically connected to the memory device420included in another memory device layer415and the transistor200T included in the transistor layer413, via the conductor424and the conductor205.

The memory unit470is sealed with the insulator211, the insulator212, the insulator214, the insulator287, the insulator282, the insulator283, and the insulator284. The insulator274is provided around the insulator284. The conductor430is provided in the insulator274, the insulator284, the insulator283, and the insulator211and be electrically connected to the element layer411.

The insulator280is provided in the sealing structure. The insulator280has a function of releasing oxygen by heating. The insulator280includes an excess oxygen region.

For the insulator211, the insulator283, and the insulator284, a material having a high blocking property against hydrogen is preferably used. Furthermore, the insulator214, the insulator282, and the insulator287are preferably formed using a material having a function of trapping or fixing hydrogen.

Examples of the material having a high blocking property against hydrogen include silicon nitride and silicon nitride oxide. Examples of the material having a function of trapping or fixing hydrogen include aluminum oxide, hafnium oxide, and an oxide containing aluminum and hafnium (hafnium aluminate).

Note that in this specification and the like, a barrier property means a function of inhibiting diffusion of a targeted substance (or low permeability). Alternatively, a barrier property means a function of trapping and fixing (or gettering) a targeted substance.

Materials for the insulator211, the insulator212, the insulator214, the insulator287, the insulator282, the insulator283, and the insulator284may have an amorphous or crystal structure, although the crystallinity of the materials is not limited thereto. For example, an amorphous aluminum oxide film is suitably used for the material having a function of trapping or fixing hydrogen. Amorphous aluminum oxide may trap or fix hydrogen more than aluminum oxide with high crystallinity.

The following model can be given for excess oxygen in the insulator280with respect to hydrogen diffusion in an oxide semiconductor in contact with the insulator280.

Hydrogen in the oxide semiconductor diffuses into another structure body through the insulator280in contact with the oxide semiconductor. As the hydrogen diffusion, the hydrogen in the oxide semiconductor reacts with the excess oxygen in the insulator280to be OH bonding and diffuses in the insulator280. The hydrogen atom having the OH bonding reacts with the oxygen atom bonded to an atom (such as a metal atom) in the insulator282in reaching a material which has a function of trapping or fixing hydrogen (typically the insulator282), and is trapped or fixed in the insulator282. The oxygen atom which had the OH bonding of the excess oxygen may remain as an excess oxygen in the insulator280. That is, the excess oxygen in the insulator280highly probably acts as a bridge in the hydrogen diffusion.

A manufacturing process of the memory device is one of important factors for the model.

For example, the insulator280containing excess oxygen is formed above the oxide semiconductor, and then the insulator282is formed. After that heat treatment is preferably performed. The heat treatment is performed at a temperature higher than or equal to 350° C., preferably higher than or equal to 400° C. in an atmosphere containing oxygen, an atmosphere containing nitrogen, or an atmosphere of a mixture of oxygen and nitrogen. The heat treatment is performed for one hour or more, preferably four hours or more, further preferably eight hours or more.

The heat treatment enables diffusion of hydrogen from the oxide semiconductor to the outside through the insulator280, the insulator282, and the insulator287. This reduces the absolute amount of hydrogen in and near the oxide semiconductor.

The insulator283and the insulator284are formed after the heat treatment. The insulator283and the insulator284have a high blocking property against hydrogen and accordingly can inhibit the entry of hydrogen outside or the hydrogen which has been diffused to the outside into the inside, specifically, the oxide semiconductor or insulator280side.

The heat treatment is performed after the insulator282is formed in the above example; however, one embodiment of the present invention is not limited thereto. For example the heat treatment may be performed after the transistor element layer413is formed or after the memory device layer415_1to the memory device layer415_4are formed. When hydrogen diffuses outward by the heat treatment, hydrogen diffuses in the upward direction or in the lateral direction of the transistor layer413. When the heat treatment is performed after the memory device layer415_1to the memory device layer415_4are formed, hydrogen similarly diffuses in the upward direction or in the lateral direction.

The above manufacturing process yields the sealing structure by bonding the insulator211and the insulator283.

The above-described structure and manufacturing process enable a memory device using an oxide semiconductor with reduced hydrogen concentration. Thus, a highly reliable memory device can be provided. One embodiment of the present invention can provide a memory device with favorable electrical characteristics.

FIG.18AtoFIG.18Cshow an example of a different arrangement of the conductor424.FIG.18Ais a layout diagram of the memory device420seen from the top,FIG.18Bis a cross-sectional view of a portion taken along dashed-dotted line A1-A2inFIG.18A, andFIG.18Cis a cross-sectional view of a portion taken along dashed-dotted line B1-B2inFIG.18A. Note that inFIG.18A, the conductor205is not illustrated for easy understanding. In the case where the conductor205is provided, the conductor205has a region overlapping with the conductor424.

As illustrated inFIG.18A, the conductor424is provided not only in the region overlapping with the oxide230aand the oxide230bbut also outside the oxide230aand the oxide230b. Although in the example shown inFIG.18A, the conductor424is provided to protrude from the oxide230aand the oxide230bon B2side, this embodiment is not limited thereto. The conductor424may be provided to protrude from the oxide230aand the oxide230bon B1side or may be provided to protrude from both B1and B2sides.

FIG.18BandFIG.18Cshow an example in which the memory device layer415_p(p is a natural number greater than or equal to 2 and less than or equal to n) is stacked over the memory device layer415_p-1. The memory device420included in the memory device layer415_p-1is electrically connected to the memory device420included in the memory device layer415_pvia the conductor424and the conductor205.

FIG.18Bshows a state where the conductor424in the memory device layer415_p-1is connected to the conductor242in the memory device layer415_p-1and the conductor205in the memory device layer415_p. Here, the conductor424is also connected to the conductor205in the memory device layer415_p-1on an outer side that is on B2side of the conductor242, the oxide243, the oxide230b, and the oxide230a.

According toFIG.18C, the conductor424is formed along side surfaces of the conductor242, the oxide243, the oxide230b, and the oxide230aon B2side, and is electrically connected to the conductor205through an opening formed in the insulator280, the insulator273, the insulator272, the insulator224, and the insulator222. InFIG.18B, the state where the conductor424is provided along the side surfaces of the conductor242, the oxide243, the oxide230b, and the oxide230aon B2side is shown by a dotted line. Moreover, the insulator241is formed, in some cases, between the conductor424and the side surfaces of the conductor242, the oxide243, the oxide230b, the oxide230a, the insulator224, and the insulator222on B2side.

The conductor424is provided also in a region not overlapping with the conductor242or the like, whereby the memory device420can be electrically connected to another memory device420provided in a different memory device layer415. In addition, the memory device420can be electrically connected to the transistor200T provided in the transistor layer413.

When the conductor424serves as a bit line, the conductor424is provided in a region not overlapping with the conductor242or the like, so that the length of the bit line between the memory devices420adjacent to each other in B1-B2direction can be increased. As illustrated inFIG.18, the distance between the conductors424over the conductor242is d1, and the distance between the conductors424positioned below the oxide230a, that is, in the opening formed in the insulator224and the insulator222is d2; d2is larger than d1. Whereas the distance between the conductors424adjacent to each other in B1-B2direction is d1, part of the distance is set to d2, so that the parasitic capacitance of the conductor424can be reduced. A reduction in parasitic capacitance of the conductor424is preferable because the capacitance necessary for the capacitor292can be reduced.

Note that this embodiment can be implemented in combination with the other embodiments described in this specification as appropriate.

Embodiment 4

In this embodiment, the compositions of a CAC-OS (Cloud-Aligned Composite oxide semiconductor) and a CAAC-OS (c-axis aligned crystalline oxide semiconductor) which are metal oxides that can be used in the OS transistor described in the above embodiment will be described.

<Composition of Metal Oxide>

A CAC-OS or a CAC-metal oxide has a conducting function in part of the material and has an insulating function in another part of the material; as a whole, the CAC-OS or the CAC-metal oxide has a function of a semiconductor. Note that in the case where the CAC-OS or the CAC-metal oxide is used in a channel formation region of a transistor, the conducting function is a function that allows electrons (or holes) serving as carriers to flow, and the insulating function is a function that does not allow electrons serving as carriers to flow. By the complementary action of the conducting function and the insulating function, a switching function (On/Off function) can be given to the CAC-OS or the CAC-metal oxide. In the CAC-OS or the CAC-metal oxide, separation of the functions can maximize each function.

In addition, the CAC-OS or the CAC-metal oxide includes conductive regions and insulating regions. The conductive regions have the above-described conducting function, and the insulating regions have the above-described insulating function. Furthermore, in some cases, the conductive regions and the insulating regions in the material are separated at the nanoparticle level. Furthermore, in some cases, the conductive regions and the insulating regions are unevenly distributed in the material. Furthermore, in some cases, the conductive regions are observed to be coupled in a cloud-like manner with their boundaries blurred.

Furthermore, in the CAC-OS or the CAC-metal oxide, the conductive regions and the insulating regions each have a size greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 0.5 nm and less than or equal to 3 nm, and are dispersed in the material, in some cases.

Furthermore, the CAC-OS or the CAC-metal oxide includes components having different bandgaps. For example, the CAC-OS or the CAC-metal oxide includes a component having a wide gap due to the insulating region and a component having a narrow gap due to the conductive region. In the case of the structure, when carriers flow, carriers mainly flow in the component having a narrow gap. Furthermore, the component having a narrow gap complements the component having a wide gap, and carriers also flow in the component having a wide gap in conjunction with the component having a narrow gap. Therefore, in the case where the above-described CAC-OS or CAC-metal oxide is used for a channel formation region of a transistor, the transistor in the on state can achieve high current driving capability, that is, a high on-state current and high field-effect mobility.

In other words, the CAC-OS or the CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

<Structure of Metal Oxide>

Oxide semiconductors can be classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of the non-single-crystal oxide semiconductors include a CAAC-OS (c-axis aligned crystalline oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor.

Oxide semiconductors might be classified in a manner different from the above-described one when classified in terms of the crystal structure. The classification of the crystal structures of oxide semiconductor will be explained withFIG.19A.FIG.19Ais a diagram showing the classification of crystal structures of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn).

As shown inFIG.19A, IGZO is roughly classified into Amorphous, Crystalline, and Crystal. Amorphous includes completely amorphous structure. Crystalline includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (Cloud-Aligned Composite). Crystal includes single crystal and poly crystal.

Note that the structure shown in the thick frame inFIG.19Ais a structure that belongs to new crystalline phase. This structure is positioned in a boundary region between Amorphous and Crystal. In other words, Amorphous, which is energetically unstable, and Crystalline are completely different structures.

A crystal structure of a film or a substrate can be analyzed with X-ray diffraction (XRD) images. Here, XRD spectra of quartz glass and IGZO, which has a crystal structure classified into Crystalline (also referred to as crystalline IGZO), are shown inFIG.19BandFIG.19C.FIG.19Bshows an XRD spectrum of quartz glass andFIG.19Cshows an XRD spectrum of crystalline IGZO. Note that the crystalline IGZO shown inFIG.19Chas a composition of In:Ga:Zn=4:2:3 [atomic ratio]. Furthermore, the crystalline IGZO shown inFIG.19Chas a thickness of 500 nm.

As indicated by arrows inFIG.19B, the XRD spectrum of the quartz glass shows a substantially symmetrical peak. In contrast, as indicated by arrows inFIG.19C, the XRD spectrum of the crystalline IGZO shows an asymmetrical peak. The asymmetrical peak of the XRD spectrum clearly shows the existence of crystal. In other words, the structure cannot be regarded as Amorphous unless it has a bilaterally symmetrical peak in the XRD spectrum.

The CAAC-OS has c-axis alignment, a plurality of nanocrystals are connected in the a-b plane direction, and its crystal structure has distortion. Note that the distortion refers to a portion where the direction of a lattice arrangement changes between a region with a regular lattice arrangement and another region with a regular lattice arrangement in a region where the plurality of nanocrystals are connected.

The nanocrystal is basically a hexagon but is not always a regular hexagon and is a non-regular hexagon in some cases. Furthermore, a pentagonal or heptagonal lattice arrangement, for example, is included in the distortion in some cases. Note that a clear crystal grain boundary (also referred to as grain boundary) cannot be observed even in the vicinity of distortion in the CAAC-OS. That is, formation of a crystal grain boundary is inhibited by the distortion of lattice arrangement. This is probably because the CAAC-OS can tolerate distortion owing to a low density of arrangement of oxygen atoms in the a-b plane direction, an interatomic bond length changed by substitution of a metal element, and the like. A crystal structure in which a clear grain boundary is observed is what is called a polycrystal structure. It is highly probable that the grain boundary becomes a recombination center and traps carriers and thus decreases the on-state current or field-effect mobility of a transistor, for example. Thus, the CAAC-OS in which no clear grain boundary is observed is one of crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. Note that Zn is preferably contained to form the CAAC-OS. For example, an In—Zn oxide and an In—Ga—Zn oxide are suitable because they can inhibit generation of a grain boundary as compared with an In oxide.

The CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter, an In layer) and a layer containing the element M, zinc, and oxygen (hereinafter, an (M,Zn) layer) are stacked. Note that indium and the element M can be replaced with each other, and when the element M in the (M,Zn) layer is replaced with indium, the layer can also be referred to as an (In,M,Zn) layer. Furthermore, when indium in the In layer is replaced with the element M, the layer can be referred to as an (In,M) layer.

The CAAC-OS is an oxide semiconductor with high crystallinity. Meanwhile, in the CAAC-OS, a reduction in electron mobility due to a crystal grain boundary is less likely to occur because a clear crystal grain boundary cannot be observed. Moreover, since the crystallinity of an oxide semiconductor might be decreased by entry of impurities, formation of defects, or the like, the CAAC-OS can be regarded as an oxide semiconductor that has small amounts of impurities and defects (e.g., oxygen vacancies). Thus, an oxide semiconductor including the CAAC-OS is physically stable. Therefore, the oxide semiconductor including the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable with respect to high temperature in the manufacturing process (what is called thermal budget). Accordingly, the use of the CAAC-OS for the OS transistor can extend the degree of freedom of the manufacturing process.

In the nc-OS, a microscopic region (e.g., a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. Furthermore, there is no regularity of crystal orientation between different nanocrystals in the nc-OS. Thus, the orientation in the whole film is not observed. Accordingly, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor by some analysis methods.

The a-like OS is an oxide semiconductor having a structure between those of the nc-OS and the amorphous oxide semiconductor. The a-like OS includes a void or a low-density region. That is, the a-like OS has low crystallinity as compared with the nc-OS and the CAAC-OS.

An oxide semiconductor has various structures with different properties. An oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, the a-like OS, the nc-OS, and the CAAC-OS.

<Transistor Including Oxide Semiconductor>

Next, the case where the above oxide semiconductor is used for a transistor is described.

When the above oxide semiconductor is used for a transistor, a transistor with high field-effect mobility can be achieved. In addition, a transistor having high reliability can be achieved.

An oxide semiconductor with a low carrier density is preferably used for the transistor. To reduce the carrier density of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film is lowered so that the density of defect states can be reduced. In this specification and the like, a state with a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic state.

Moreover, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states and accordingly may have a low density of trap states.

Electric charge trapped by the trap states in the oxide semiconductor takes a long time to disappear and might behave like fixed electric charge. Thus, a transistor whose channel formation region is formed in an oxide semiconductor with a high density of trap states has unstable electrical characteristics in some cases.

Accordingly, in order to obtain stable electrical characteristics of a transistor, reducing the concentration in an oxide semiconductor is effective. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable that the impurity concentration in an adjacent film be also reduced. Examples of impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, and silicon.

<Impurity>

Here, the influence of each impurity in the oxide semiconductor is described.

When silicon or carbon, which is one of Group14elements, is contained in the oxide semiconductor, defect states are formed in the oxide semiconductor. Thus, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon in the vicinity of an interface with the oxide semiconductor (the concentration obtained by secondary ion mass spectrometry (SIMS)) are each set lower than or equal to 2×1018atoms/cm3, preferably lower than or equal to 2×1017atoms/cm3.

When the oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states are formed and carriers are generated in some cases. Thus, a transistor using an oxide semiconductor that contains an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. Therefore, it is preferable to reduce the concentration of an alkali metal or an alkaline earth metal in the oxide semiconductor. Specifically, the concentration of an alkali metal or an alkaline earth metal in the oxide semiconductor obtained by SIMS is lower than or equal to 1×1018atoms/cm3, preferably lower than or equal to 2×1016atoms/cm3.

When containing nitrogen, the oxide semiconductor easily becomes n-type by generation of electrons serving as carriers and an increase in carrier density. As a result, a transistor using an oxide semiconductor containing nitrogen for its channel formation region is likely to have normally-on characteristics. For this reason, nitrogen in the oxide semiconductor is preferably reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor is lower than 5×1019atoms/cm3, preferably lower than or equal to 5×1018atoms/cm3, further preferably lower than or equal to 1×1018atoms/cm3, still further preferably lower than or equal to 5×1017atoms/cm3in SIMS.

Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to be water, and thus forms an oxygen vacancy in some cases. Entry of hydrogen into the oxygen vacancy generates an electron serving as a carrier in some cases. Furthermore, bonding of part of hydrogen to oxygen bonded to a metal atom causes generation of an electron serving as a carrier in some cases. Thus, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Accordingly, hydrogen in the oxide semiconductor is preferably reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor that is obtained by SIMS is set lower than 1×1020atoms/cm3, preferably lower than 1×1019atoms/cm3, further preferably lower than 5×1018atoms/cm3, still further preferably lower than 1×1018atoms/cm3.

When an oxide semiconductor with sufficiently reduced impurities is used for the channel formation region of the transistor, stable electrical characteristics can be given.

Note that this embodiment can be implemented in combination with the other embodiments described in this specification as appropriate.

Embodiment 5

In this embodiment, examples of electronic components and electronic devices in which the memory device or the like described in the above embodiment is incorporated will be described.

<Electronic Component>

First, examples of electronic components in which the memory device10A and the like is incorporated will be described with reference toFIG.20AandFIG.20B.

FIG.20Ais a perspective view of an electronic component700and a substrate (a mounting board704) on which the electronic component700is mounted. In the electronic component700illustrated inFIG.20A, the memory device10A where the element layers34are stacked over the semiconductor substrate11is included in a mold711.FIG.20Aomits part of the electronic component700to show the inside of the electronic component700. The electronic component700includes a land712outside the mold711. The land712is electrically connected to an electrode pad713, and the electrode pad713is electrically connected to the memory device10A via a wire714. The electronic component700is mounted on a printed circuit board702, for example. A plurality of such electronic components are combined and electrically connected to each other on the printed circuit board702, whereby the mounting board704is completed.

FIG.20Bis a perspective view of an electronic component730. The electronic component730is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component730, an interposer731is provided on a package substrate732(a printed circuit board), and a semiconductor device735and a plurality of memory devices10A are provided on the interposer731.

The electronic component730using the memory devices10A as high bandwidth memory (HBM) is shown as an example. An integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA can be used as the semiconductor device735.

As the package substrate732, a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used. As the interposer731, a silicon interposer, a resin interposer, or the like can be used.

The interposer731includes a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits with different terminal pitches. The plurality of wirings are provided in a single layer or multiple layers. Moreover, the interposer731has a function of electrically connecting an integrated circuit provided on the interposer731to an electrode provided on the package substrate732. Accordingly, the interposer is sometimes referred to as a “redistribution substrate” or an “intermediate substrate”. A through electrode may be provided in the interposer731and used for electrically connecting an integrated circuit and the package substrate732. For a silicon interposer, a TSV (Through Silicon Via) can also be used as the through electrode.

A silicon interposer is preferably used as the interposer731. A silicon interposer can be manufactured at lower cost than an integrated circuit because it is not necessary to provide an active element. Meanwhile, since wirings of a silicon interposer can be formed through a semiconductor process, formation of minute wirings, which is difficult for a resin interposer, is easy.

In order to achieve a wide memory bandwidth, many wirings need to be connected to HBM. Therefore, formation of minute and high-density wirings is required for an interposer on which HBM is mounted. For this reason, a silicon interposer is preferably used as the interposer on which HBM is implanted.

In a SiP, an MCM, or the like using a silicon interposer, the decrease in reliability due to a difference in expansion coefficient between an integrated circuit and the interposer is less likely to occur. Furthermore, the surface of a silicon interposer has high planarity, so that a poor connection between the silicon interposer and an integrated circuit provided on the silicon interposer is less likely to occur. It is particularly preferable to use a silicon interposer for a 2.5D package (2.5-dimensional mounting) in which a plurality of integrated circuits are arranged side by side on an interposer.

A heat sink (a radiator plate) may be provided to overlap the electronic component730. In the case of providing a heat sink, the heights of integrated circuits provided on the interposer731are preferably equal to each other. For example, in the electronic component730described in this embodiment, the heights of the memory device10A and the semiconductor device735are preferably equal to each other.

To implant the electronic component730on another substrate, an electrode733may be provided on the bottom portion of the package substrate732.FIG.20Billustrates an example in which the electrode733is formed of a solder ball. When solder balls are provided in a matrix on the bottom portion of the package substrate732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrode733may be formed of a conductive pin. When conductive pins are provided in a matrix on the bottom portion of the package substrate732, PGA (Pin Grid Array) mounting can be achieved.

The electronic component730can be mounted on another substrate by various mounting methods not limited to BGA and PGA. For example, a mounting method such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be employed.

<Electronic Device>

Next, examples of electronic devices including the above electronic component will be described with reference toFIG.21.

A robot7100includes an illuminance sensor, a microphone, a camera, a speaker, a display, various kinds of sensors (e.g., an infrared ray sensor, an ultrasonic wave sensor, an acceleration sensor, a piezoelectric sensor, an optical sensor, and a gyro sensor), a moving mechanism, and the like. The electronic component730includes a processor or the like and has a function of controlling these peripheral devices. For example, the electronic component700has a function of storing data obtained by the sensors.

The microphone has a function of detecting acoustic signals of a speaking voice of a user, an environmental sound, and the like. The speaker has a function of outputting audio signals such as a voice and a warning beep. The robot7100can analyze an audio signal input via the microphone and can output a necessary audio signal from the speaker. The robot7100can communicate with the user with use of the microphone and the speaker.

The camera has a function of taking images of the surroundings of the robot7100. The robot7100has a function of moving with use of the moving mechanism. The robot7100can take images of the surroundings with use of the camera and analyze the images to sense whether there is an obstacle in the way of the movement.

A flying object7120includes propellers, a camera, a battery, and the like and has a function of flying autonomously. The electronic component730has a function of controlling these peripheral devices.

For example, image data taken by the camera is stored in the electronic component700. The electronic component730can analyze the image data to sense whether there is an obstacle in the way of the movement. Moreover, the electronic component730can estimate the remaining battery level from a change in the power storage capacity of the battery.

A cleaning robot7140includes a display provided on the top surface, a plurality of cameras provided on the side surface, a brush, an operation button, various kinds of sensors, and the like. Although not illustrated, the cleaning robot7140is provided with a tire, an inlet, and the like. The cleaning robot7140can run autonomously, detect dust, and vacuum the dust through the inlet provided on the bottom surface.

For example, the electronic component730can analyze images taken by the cameras to judge whether there is an obstacle such as a wall, furniture, or a step. In the case where an object that is likely to be caught in the brush, such as a wire, is detected by image analysis, the rotation of the brush can be stopped.

An automobile7160includes an engine, tires, a brake, a steering gear, a camera, and the like. For example, the electronic component730performs control for optimizing the running state of the automobile7160on the basis of navigation information, the speed, the state of the engine, the gearshift state, the use frequency of the brake, and other data. For example, image data taken by the camera is stored in the electronic component700.

The electronic component700and/or the electronic component730can be incorporated in a TV device7200(a television receiver), a smartphone7210, PCs (personal computers)7220and7230, a game machine7240, a game machine7260, and the like.

For example, the electronic component730incorporated in the TV device7200can function as an image processing engine. The electronic component730performs, for example, image processing such as noise removal and resolution up-conversion.

The smartphone7210is an example of a portable information terminal. The smartphone7210includes a microphone, a camera, a speaker, various kinds of sensors, and a display portion. These peripheral devices are controlled by the electronic component730.

The PC7220and the PC7230are examples of a laptop PC and a desktop PC. To the PC7230, a keyboard7232and a monitor device7233can be connected with or without a wire. The game machine7240is an example of a portable game machine. The game machine7260is an example of a stationary game machine. To the game machine7260, a controller7262is connected with or without a wire. The electronic component700and/or the electronic component730can be incorporated in the controller7262.

<Various Kinds of Memory Device>

In general, a variety of memory devices (memory) are used as semiconductor devices such as a computer in accordance with the intended use.FIG.22is a hierarchy diagram showing various memory devices with different levels. The memory devices at the upper levels of the diagram require high access speeds, and the memory devices at the lower levels require large memory capacity and high record density. InFIG.22, sequentially from the top level, a memory combined as a register in an arithmetic processing device such as a CPU, a static random access memory (SRAM), a dynamic random access memory (DRAM), and a 3D NAND memory are shown.

A memory included as a register in an arithmetic processing device such as a CPU is used for temporary storage of arithmetic operation results, for example, and thus is very frequently accessed by the arithmetic processing device. Accordingly, rapid operation is more important than the memory capacity of the memory. The register also has a function of retaining settings of the arithmetic processing device, for example.

An SRAM is used for a cache, for example. The cache has a function of holding a copy of part of data held in a main memory. Copying data which is frequently used and holding the copy of the data in the cache facilitates rapid data access.

A DRAM is used for the main memory, for example. The main memory has a function of holding a program or data which are read from the storage space. The record density of a DRAM is approximately 0.1 to 0.3 Gbit/mm2.

A 3D NAND memory is used for the storage, for example. The storage has a function of holding data that needs to be stored for a long time and programs used in an arithmetic processing device, for example. Therefore, the storage needs to have a high memory capacity and a high memory density rather than operating speed. The memory density for a storage space is approximately 0.6 to 6.0 Gbit/mm2.

The memory device relating to one embodiment of the present invention operates fast and can hold data for a long time. The memory device relating to one embodiment of the present invention can be favorably used as a memory device in a boundary region901that includes both the level including the cache and the level including the main memory. The memory device relating to one embodiment of the present invention can be favorably used as a memory device in a boundary region902that includes both the level including the main memory and the level including the storage.

Note that this embodiment can be implemented in combination with the other embodiments described in this specification as appropriate.

REFERENCE NUMERALS

A0: bit, A3: bit, B0: check bit, BL_1: bit line, C1: input terminal, C2: input terminal, C3: input terminal, C4: input terminal, C5: input terminal, C8: input terminal, C61: capacitor, C71: capacitor, CK1: clock signal, CK4: clock signal, S_C1: control signal, S_C2: control signal, S_C3: control signal, S_C4: control signal, S_C5: control signal, S_C8: control signal, T_A0: input terminal, T_A3: input terminal, T_B0: input terminal, T_CK1: input terminal, T_CK4: input terminal, WL_N: word line, WL_1: word line,10A: memory device,10B: memory device,10C: memory device,11: semiconductor substrate,20: peripheral circuit,21: row driver,22: column driver,23: switch circuit,23_A: switch,23_C: switch,24: precharge circuit,24_1: transistor,24_3: transistor,25: sense amplifier,25_1: transistor,25_2: transistor,25_3: transistor,25_4: transistor,26: element layer,28_a: transistor,28_b: transistor,29: circuit,30: memory cell array,31_N: memory cell,31_1: memory cell,32_N: transistor,32_1: transistor,33_N: capacitor,33_1: capacitor,34: element layer,34_N: element layer,34_1: element layer,34_5: element layer,39: unit,39_M: unit,39_1: unit,40A: sealing layer,40B: sealing layer,41: switch circuit,51: NAND circuit,51_1: NAND circuit,51_4: NAND circuit,52: delay circuit,52_1: delay circuit,52_2: delay circuit,52_4: delay circuit,53: XOR circuit,53_1: XOR circuit,53_3: XOR circuit,53_4: XOR circuit,53_7: XOR circuit,54: check bit generation circuit,55: error detection circuit,61: transistor,64: transistor,71: transistor,72: transistor,200: transistor,200M: transistor,200T: transistor,205: conductor,205a: conductor,205b: conductor,211: insulator,212: insulator,214: insulator,216: insulator,222: insulator,224: insulator,230: oxide,230a: oxide,230b: oxide,230c: oxide,240: conductor,240a: conductor,240b: conductor,241: insulator,241a: insulator,241b: insulator,242: conductor,242a: conductor,242b: conductor,243: oxide,243a: oxide,243b: oxide,246: conductor,246a: conductor,246b: conductor,250: insulator,260: conductor,260a: conductor,260b: conductor,272: insulator,273: insulator,274: insulator,275: insulator,276: conductor,277: insulator,278: conductor,279: insulator,280: insulator,282: insulator,283: insulator,284: insulator,287: insulator,290: conductor,292: capacitor,292A: capacitor,292B: capacitor,294: conductor,295: insulator,296: insulator,297: conductor,298: insulator,299: conductor,300: transistor,311: semiconductor substrate,313: semiconductor region,314a: low-resistance region,314b: low-resistance region,315: insulator,316: conductor,411: element layer,413: transistor layer,413_m: transistor layer,413_1: transistor layer,415: memory device layer,415_n: memory device layer,415_p: memory device layer,415_p-1: memory device layer,415_1: memory device layer,415_4: memory device layer,420: memory device,420A: memory device,420B: memory device,422: region,424: conductor,426: conductor,428: conductor,430: conductor,470: memory unit,470_m: memory unit,470_1: memory unit,700: electronic component,702: printed circuit board,704: mounting board,711: mold,712: land,713: electrode pad,714: wire,730: electronic component,731: interposer,732: package substrate,733: electrode,735: semiconductor device,901: boundary region,902: boundary region,7100: robot,7120: flying object,7140: cleaning robot,7160: automobile,7200: TV device,7210: smartphone,7220: PC,7230: PC,7232: keyboard,7233: monitor device,7240: game machine,7260: game machine,7262: controller