Patent ID: 12261198

DETAILED DESCRIPTION

Various embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art to which the present invention pertains. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.

The drawings are not necessarily to scale and, in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being “on” a second layer or “on” a substrate, it not only refers to a case where the first layer is formed directly on the second layer or the substrate but also a case where a third layer exists between the first layer and the second layer or the substrate.

It should be understood that the drawings are simplified schematic illustrations of the described devices and may not include well known details for avoiding obscuring the features of the invention.

It should also be noted that features present in one embodiment may be used with one or more features of another embodiment without departing from the scope of the invention.

FIG.1Ais a cross-sectional view illustrating a semiconductor device100in accordance with an embodiment of the present invention.FIG.1Bis a plan view taken along a line A1-A1′ ofFIG.1A.FIG.1Cis a plan view taken along a line A2-A2′ ofFIG.1A.FIG.1Dis a plan view taken along a line A3-A3′ ofFIG.1A.

Referring toFIGS.1A to1D, the semiconductor device100may include a lower structure101and a capacitor structure100C disposed over the lower structure101. The capacitor structure100C may be electrically connected to the lower structure101through a plurality of contact plugs103. The contact plugs103may penetrate an inter-layer dielectric layer102over the lower structure101to be coupled to the lower structure101. The contact plugs103may be referred to as storage node contact plugs.

Although not illustrated, the lower structure101may include a semiconductor substrate, a buried word line formed in the semiconductor substrate, and a bit line over the buried word line.

The lower structure101may include a material appropriate for semiconductor processing. For example, the lower structure101may include a semiconductor substrate, and the semiconductor substrate may be formed of a silicon-containing material. The semiconductor substrate may include silicon, monocrystalline silicon, polysilicon, amorphous silicon, silicon germanium, monocrystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multi-layer thereof. The semiconductor substrate may include other semiconductor materials such as germanium. The semiconductor substrate may include a group-III/V semiconductor substrate, such as a compound semiconductor substrate such as GaAs. The semiconductor substrate may include a Silicon-On-Insulator (SOI) substrate.

The capacitor structure100C may include an etch stop layer104, lower electrodes105, a dielectric layer108, and upper electrodes109. The bottom portion of each of the lower electrodes105may penetrate the etch stop layer104to be coupled to a corresponding contact plug103. The lower electrode105may be of a hybrid type, and it may include a cylinder electrode106and a pillar electrode107filling the cylindrical inside of the cylinder electrode106. The lower electrode105may be referred to as a storage node. The lower electrode105may be positioned over the semiconductor substrate of the lower structure101. The contact plugs103may be positioned between the semiconductor substrate and corresponding lower electrodes105.

The outer wall of the lower electrodes105may be supported by a supporter MLDS. The supporter MLDS may include a plate-like structure which laterally extends to simultaneously support a plurality of neighboring lower electrodes105. The supporter MLDS may include at least one supporter. For example, the supporter MLDS may include a multi-level dielectric supporter. The supporter MLDS may include an upper-level supporter111and a lower-level supporter110. The upper-level supporter111may support the upper outer wall of the lower electrodes105, and the lower-level supporter110may be vertically spaced apart from the upper-level supporter111to support the outer wall of the lower electrodes105. The upper-level supporter111may be thicker than the lower-level supporter110. The distance between the upper-level supporter111and the lower-level supporter110may be smaller than the distance between the lower-level supporter111and the etch stop layer104. From the perspective of a top view, each of the upper-level supporter111and the lower-level supporter110may have a plate-like structure. The upper-level supporter111and the lower-level supporter110may be formed of the same material or different materials. The upper-level supporter111and the lower-level supporter110may include silicon, nitrogen, oxygen, carbon, or a combination thereof. The upper level supporter111and the lower level supporter110may be made of the same material or different materials. For example, the upper level supporter111and the lower level supporter110may be formed of silicon nitride, silicon carbon nitride, or silicon boron nitride.

A protective structure MLCS may be positioned between the lower electrode105and the supporter MLDS. The protective structure MLCS may serve as a discrete supporter that independently supports each lower electrode105. The laterally neighboring protective structures MLCS may be separated from each other. The protective structure MLCS may include at least one protective layer pattern. For example, the protective structure MLCS may include a multi-level protective layer pattern. The supporter MLDS and the protective structure MLCS may be formed of different materials. The supporter MLDS may include a dielectric material, and the protective structure MLCS may include a conductive material.

The protective structure MLCS may include an upper-level protective layer pattern114, a middle-level protective layer pattern113, and a lower-level protective layer pattern112. The upper-level protective layer pattern114may be positioned between the lower electrode105and the upper-level supporter111to support the upper outer wall of the lower electrode105. The upper-level protective layer pattern114and the upper-level supporter111may be positioned at the same level. The middle-level protective layer pattern113may be positioned between the lower electrode105and the lower-level supporter110, and the middle-level protective layer pattern113may be spaced apart from the upper-level protective layer pattern114to support the outer wall of the lower electrode105. The middle-level protective layer pattern113and the lower-level supporter110may be positioned at the same level. The lower-level protective layer pattern112may be vertically spaced apart from the middle-level protective layer pattern113to surround and support the bottom surface and the bottom sidewall of the lower electrode105. The height of the upper-level protective layer pattern114may be greater than the height of the middle-level protective layer pattern113. The lower-level protective layer pattern112may be positioned between the lower structure101and the lower electrode105. The lower-level protective layer pattern112may directly contact the etch stop layer104and the corresponding contact plug103. The distance between the upper-level protective layer pattern114and the middle-level protective layer pattern113may be smaller than the distance between the middle-level protective layer pattern113and the lower-level protective layer pattern112. From the perspective of a top view, the upper-level protective layer pattern114, the middle-level protective layer pattern113, and the lower-level protective layer pattern112may fully surround or partially surround a portion of the outer wall of the lower electrode105. A plurality of the upper-level protective layer patterns114may be positioned at the same level, while being spaced apart from each other. A plurality of the middle-level protective layer patterns113may be positioned at the same level, while being spaced apart from each other. A plurality of the lower-level protective layer patterns112may be positioned at the same level, while being spaced apart from each other.

The upper-level protective layer pattern114, the middle-level protective layer pattern113, and the lower-level protective layer pattern112may include titanium nitride, niobium, or a combination thereof. The upper-level protective layer pattern114, the middle-level protective layer pattern113, and the lower-level protective layer pattern112may be made of the same material or different materials. For example, the upper-level protective layer pattern114, the middle-level protective layer pattern113, and the lower-level protective layer pattern112may be formed of niobium (Nb). Since the upper-level protective layer pattern114, the middle-level protective layer pattern113, and the lower-level protective layer pattern112include a conductive material, they may serve as a portion of the lower electrode105.

According to some embodiments of the present invention, the cylindrical electrode106of the lower electrode105may include a crystalline conductive material, and the upper-level protective layer pattern114, the middle-level protective layer pattern113, and the lower-level protective layer pattern112may include an amorphous conductive material. For example, the cylindrical electrode106may include crystalline titanium nitride, and the upper-level protective layer pattern114, the middle-level protective layer pattern113, and the lower-level protective layer pattern112may include amorphous titanium nitride.

According to another embodiment of the present invention, the cylindrical electrode106may include crystalline titanium nitride, and the upper-level protective layer pattern114, the middle-level protective layer pattern113, and the lower-level protective layer pattern112may include amorphous niobium. According to another embodiment of the present invention, the cylindrical electrode106may include crystalline niobium, and the upper-level protective layer pattern114, the middle-level protective layer pattern113, and the lower-level protective layer pattern112may include amorphous niobium.

According to another embodiment of the present invention, the cylindrical electrode106may include crystalline niobium, and the upper-level protective layer pattern114, the middle-level protective layer pattern113, and the lower-level protective layer pattern112may include amorphous titanium nitride.

As will be described later, the amorphous conductive material as the protective structure MLCS may serve to suppress deterioration in the roughness of the cylindrical electrode106during a wet dip-out process of a mold layer which is to be formed subsequently.

As described above, since the lower electrodes105are supported by the hybrid supporters, that is, the upper-level supporter111, the lower-level supporter110, the upper-level protective layer pattern114, the middle-level protective layer pattern113, and the lower-level protective layer pattern112, the structural stability of lower electrodes105may be increased.

Referring back toFIG.1B, upper portions of the neighboring lower electrodes105A,105B,105C,105D, and105E may be supported by the plate-shaped upper-level supporter111and the discrete upper-level protective layer patterns114. The upper-level protective layer pattern114may include broken loop-shaped protective layer patterns114BL and closed loop-shaped protective layer patterns114CL. From the perspective of a top view, the closed loop-shaped protective layer patterns114CL may have a continuous ring shape, and the broken loop-shaped protective layer patterns114BL may have a discontinuous ring shape, for example, a ‘C’ shape. Some of the lower electrodes105A,105B, and105C may be supported by the plate-shaped upper-level supporter111and the broken loop-shaped protective layer patterns114BL. Some of the lower electrodes105D and105E may be supported by the plate-shaped upper-level supporter111and the closed loop-shaped protective layer patterns114CL.

Referring back toFIG.1C, the middle portions of the neighboring lower electrodes105A,105B,105C,105D and105E may be supported by the plate-shaped lower-level supporter110and the middle-level protective layer patterns113. The middle-level protective layer patterns113may include broken loop-shaped protective layer patterns113BL and the closed loop-shaped protective layer patterns113CL. From the perspective of a top view, the closed loop-shaped protective layer patterns113CL may have a continuous ring shape, and the broken loop-shaped protective layer patterns113BL may have a discontinuous ring shape, for example, a ‘C’ shape. The outer wall of some lower electrodes105A,105B and105C may be supported by the plate-shaped lower-level supporter110and the broken loop-shaped protective layer patterns113BL. Some lower electrodes105D and105E may be supported by the plate-shaped lower-level supporter110and the closed loop-shaped protective layer patterns113CL.

Referring back toFIG.1D, the bottom portions of the neighboring lower electrodes105A,105B,105C,105D and105E may be supported by the plate-shaped etch stop layer104and the lower-level protective layer patterns112. The lower-level protective layer patterns112may include closed loop-shaped protective layer patterns112CL. From the perspective of a top view, the closed loop-shaped protective layer patterns112CL may have a continuous ring shape. The bottom portions of the lower electrodes105A,105B,105C,105D and105E may be supported by the closed loop-shaped protective layer patterns112CL.

FIGS.2A to2Iare cross-sectional views illustrating an example of a method for fabricating a semiconductor device in accordance with an embodiment of the present invention.

Referring toFIG.2A, an inter-layer dielectric layer12may be formed over the lower structure11. A plurality of contact plugs13may be formed to penetrate the inter-layer dielectric layer12. The contact plugs13may penetrate the inter-layer dielectric layer12to be coupled to the lower structure11. Although not illustrated, the lower structure11may include a semiconductor substrate, a buried word line formed in the semiconductor substrate, and a bit line over the buried word line.

The lower structure11may include a material appropriate for semiconductor processing. For example, the lower structure11may include a semiconductor substrate, and the semiconductor substrate may be formed of a silicon-containing material. The semiconductor substrate may include silicon, monocrystalline silicon, polysilicon, amorphous silicon, silicon germanium, monocrystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multi-layer thereof. The semiconductor substrate may include other semiconductor materials, such as germanium. The semiconductor substrate may include a group-III/V semiconductor substrate, such as a compound semiconductor substrate such as GaAs. The semiconductor substrate may include a Silicon-On-Insulator (SOI) substrate. According to another embodiment of the present invention, when the lower structure11includes a semiconductor substrate, a mold structure20may be formed over the semiconductor substrate, and the contact plugs13and the inter-layer dielectric layer12may be positioned between the semiconductor substrate and the mold structure20.

The inter-layer dielectric layer12may include silicon oxide. The inter-layer dielectric layer12may include high-density plasma oxide (HDP oxide), TEOS (TetraEthylOrthoSilicate), PE-TEOS (Plasma Enhanced TetraEthylOrthoSilicate), O3-TEOS (O3-Tetra Ethyl Ortho Silicate), USG (Undoped Silicate Glass), PSG (PhosphoSilicate Glass), BSG (Borosilicate Glass), BPSG (BoroPhosphoSilicate Glass), FSG (Fluoride Silicate Glass), SOG (Spin On Glass), TOSZ (Tonen SilaZene), or a combination thereof. Furthermore, the inter-layer dielectric layer12may be formed of silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

The contact plugs13may include a silicon plug, a metal plug, or a combination thereof. The contact plugs13may be referred to as storage node contact plugs.

A mold structure20may be formed over the contact plugs13and the inter-layer dielectric layer12. The mold structure20may include the etch stop layer14and an alternating stack over the etch stop layer14. In the alternating stack, a plurality of mold layers and a plurality of supporter layers may be alternately stacked. For example, the mold structure20may include a stack structure of the etch stop layer14, the first mold layer15, the first supporter layer16, the second mold layer17, and the second supporter layer18. The etch stop layer14may be formed of a material having an etch selectivity with respect to the inter-layer dielectric layer12and the first mold layer15. The etch stop layer14may include silicon nitride or silicon oxynitride. According to another embodiment of the present invention, the mold structure20may be formed by sequentially stacking the etch stop layer14, one mold layer, and one supporter layer. According to another embodiment of the present invention, the mold structure20may be formed by alternately stacking at least three mold layers and at least three supporter layers over the etch stop layer14.

The first mold layer15may include a dielectric material. The first mold layer15may be silicon oxide (SiO2). The first mold layer15may be formed thicker than the first support layer16. The first mold layer15may be formed by a deposition process, such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD) or Physical Vapor Deposition (PVD). The first mold layer15may include silicon oxide doped with phosphorus or silicon oxide doped with boron. The first mold layer15may include USG, PSG, BSG, BPSG, FSG, or a combination thereof. Phosphorus-doped silicon oxide and boron-doped silicon oxide may be easily removed in the subsequent process because they have high etching rates with respect to the etching solution.

The first supporter layer16may be formed of a material having an etch selectivity with respect to the first mold layer15and the second mold layer17. The first supporter layer16may include silicon nitride or silicon carbon nitride (SiCN).

The second mold layer17may include a dielectric material. The second mold layer17may be silicon oxide (SiO2). The second mold layer17may be formed thicker than the first support layer16. The second mold layer17may be formed by a deposition process such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD) or Physical Vapor Deposition (PVD). The second mold layer17may include phosphorus-doped silicon oxide or boron-doped silicon oxide. The second mold layer17may include USG, PSG, BSG, BPSG, FSG, or a combination thereof. The first mold layer15and the second mold layer17may be made of the same material or different materials.

According to another embodiment of the present invention, the first mold layer15and the second mold layer17may be made of silicon materials, such as amorphous silicon and polysilicon.

The second supporter layer18may be formed of a material having an etch selectivity with respect to the second mold layer17. The second supporter layer18may include silicon nitride or silicon carbon nitride (SiCN).

The first supporter layer16and the second supporter layer18may be made of the same material or different materials. Both the first supporter layer16and the second supporter layer18may be formed of silicon nitride. According to another embodiment of the present invention, the first supporter layer16may be formed of silicon nitride, and the second supporter layer18may be formed of silicon carbon nitride. The second supporter layer18may be thicker than the first supporter layer16.

According to another embodiment of the present invention, another supporter layer may be further formed. For example, the supporter structure may be a multi-level supporter layer structure.

Subsequently, an opening21may be formed. The opening21may be formed by using the mask layer19and etching the mold structure20. In order to form the opening21, the second supporter layer18, the second mold layer17, the first supporter layer16and the first mold layer15may be sequentially etched by using the mask layer19as an etch barrier. The etching process for forming the opening21may stop at the etch stop layer14. To form the opening21, a dry etching process, a wet etching process, or a combination thereof may be used. The opening21may be referred to as a hole in which a lower electrode (or a storage node) is to be formed. The opening21may have a high aspect ratio. The opening21may have a high aspect ratio in which the height to width t ratio is approximately 10:1 or more.

Subsequently, the etch stop layer14may be etched to expose the upper surface of the contact plugs13below the opening21.

The mask layer19for forming the opening21may include a hard mask material, a photoresist, or a combination thereof. For example, the hard mask material may include boron-doped polysilicon, amorphous silicon, an oxide, amorphous carbon, silicon oxynitride, or a combination thereof. The photoresist may include ArF photoresist or EUV photoresist.

The opening21may be formed by a double patterning process. For example, the mask layer19for forming the opening21may be a mesh type formed by combining two spacer patterning techniques.

A mold structure20including a plurality of openings21may be formed by a series of etching processes as described above. The mold structure20may be a structure in which the etch stop layer14, the first mold layer15, the first supporter layer16, the second mold layer17, and the second supporter layer18are stacked in the mentioned order.

Referring toFIG.2B, after the mask layer19is removed, a protective layer22may be formed over the opening21and the mold structure20. The protective layer22may not fill the opening21. The protective layer22may conformally cover the sidewalls and the bottom surface of the opening21. The protective layer22may cover the upper surface of the mold structure20. The protective layer22may include a material which is different from that of the mold structure20. The protective layer22may include a material having an etch selectivity with respect to the first mold layer15and the second mold layer17. The protective layer22may be in direct contact with the contact plugs13.

The protective layer22may include a non-polycrystalline material. The protective layer22may include an amorphous material. The protective layer22may include a conductive material. The protective layer22may be formed of an amorphous conductive material. According to the embodiment of the present invention, the protective layer22may include niobium or titanium nitride. The protective layer22may include amorphous niobium or amorphous titanium nitride. Amorphous niobium or amorphous titanium nitride may be a conductive material.

Referring toFIG.2C, the lower electrode BE may be formed in the opening21. The lower electrode BE may fill the inside of the opening21over the protective layer22. The lower electrode BE may be a hybrid type. In order to form the hybrid-type lower electrode BE, a conductive material may be deposited over the protective layer22to gap-fill the opening21and then planarization may be performed. The lower electrode BE may include polysilicon, a metal, a metal nitride, a conductive metal oxide, a metal silicide, a noble metal, or a combination thereof. The lower electrode BE may include at least one among titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), titanium aluminum nitride (TiAlN), tungsten (W) or tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), and a combination thereof. The lower electrode BE may include titanium nitride (TiN). The lower electrode BE may include titanium nitride (ALD-TiN) formed by Atomic Layer Deposition (ALD). According to the embodiment of the present invention, the lower electrode BE may include a stack of the cylindrical electrode23and the pillar-shaped electrode24. The cylindrical electrode23may be titanium nitride, and the pillar-shaped electrode24may be polysilicon. The cylindrical electrode23may include polycrystalline titanium nitride, and the polycrystalline titanium nitride may include a plurality of grain boundaries. Polycrystalline titanium nitride may have a lower resistance than amorphous titanium nitride and amorphous niobium. Also, polycrystalline titanium nitride may have a greater effect of suppressing bending than amorphous titanium nitride and amorphous niobium. The cylindrical electrode23may not include amorphous titanium nitride and amorphous niobium.

While the lower electrode BE is formed, a portion of the protective layer22may be removed. In other words, a portion of the protective layer22may be removed from the uppermost surface of the mold structure20. Therefore, the protective layer22may remain only inside the opening21. The protective layer22may cover the outer wall and the bottom surface of the lower electrode BE. The protective layer22may directly contact the outer wall and the bottom surface of the cylindrical electrode23. The pillar-shaped electrode24may not contact the protective layer22. The protective layer22may have a cylindrical shape which is similar to the cylindrical electrode23.

The protective layer22may be positioned between the outer wall of the lower electrode BE and the first supporter layer16. The protective layer22may be positioned between the outer wall of the lower electrode BE and the second supporter layer18. The protective layer22may be positioned between the outer wall of the lower electrode BE and the first mold layer15. The protective layer22may be positioned between the outer wall of the lower electrode BE and the second mold layer17. As described above, the protective layer22may have a continuous shape covering the outer wall and the bottom surface of the lower electrode BE, and it may conformally cover the bottom surface and the side walls of the opening21. The protective layer22and the cylindrical electrode23may have the same thickness. According to another embodiment of the present invention, the protective layer22may be thinner than the cylindrical electrode23.

Referring toFIG.2D, a supporter mask layer25M may be formed. The supporter mask layer25M may include a photoresist or amorphous carbon.

Subsequently, a portion of the second supporter layer18may be etched by using the supporter mask layer25M. An upper-level supporter opening25and an upper-level supporter18S may be formed by etching the second supporter layer18.

The upper-level supporter18S may be a plate-shaped supporter. The upper-level supporter18S may contact the upper outer wall of the lower electrode BE. Some surfaces of the second mold layer17may be exposed by the upper-level supporter18S. The upper-level supporter18S may be shaped to partially surround the upper outer wall of the lower electrode BE. The upper-level supporter18S may prevent the lower electrodes BE from collapsing in the subsequent process of removing the second mold layer17.

From the perspective of a top view, the upper-level supporter opening25may be shaped to partially expose the upper outer walls of the neighboring three lower electrodes BE. According to another embodiment of the present invention, the upper-level supporter opening25may be shaped to partially expose the upper outer walls of at least four lower electrodes BE. The upper-level supporter opening25may have a cross section of a triangle, a square, a parallelogram, a pentagon, a hexagon or a honeycomb.

The upper outer walls of all the lower electrodes BE may be partially exposed by the upper-level supporter opening25. This may be referred to as an ‘all-open lower electrode array’.

According to another embodiment of the present invention, the upper outer wall of at least one lower electrode BE may not be exposed by the upper-level supporter opening25. For example, among the lower electrodes BE, there may be at least one lower electrode BE that is not exposed by the upper-level supporter opening25but is fully covered by the upper-level supporter18S. This may be referred to as a 1-span lower electrode array.

During the etching process for forming the upper-level supporter18S, the protective layer22is not etched.

Referring toFIG.2E, the second mold layer17below the upper-level supporter opening25may be removed. The second mold layer17may be removed by a wet dip-out process. The second mold layer17may be selectively removed, and as a result, the surface of the first supporter layer16may be exposed. The wet dip-out process for removing the second mold layer17may be performed by using an etching solution capable of selectively removing the second mold layer17. When the second mold layer17includes silicon oxide, the second mold layer17may be removed by a wet etching process using hydrofluoric acid (HF).

During the wet dip-out process for removing the second mold layer17, the protective layer22is not etched. After the second mold layer17is removed, an upper-level air gap17G may be formed between the upper-level supporter18S and the first supporter layer16. The upper-level air gap17G may be defined by the process of removing the second mold layer17and it may refer to the space from which the second mold layer17is removed. As the second mold layer17is removed, a portion of the outer wall of the protective layer22(hereinafter, which will be referred to as ‘upper-level outer wall’) may be simultaneously exposed. The upper-level outer wall of the protective layer22may be positioned at a level lower than the uppermost surface of the protective layer22. The upper-level outer wall of the protective layer22does not refer to the uppermost outer wall of the protective layer22. The upper outer wall of the protective layer22may not be exposed by the upper-level supporter18S. The upper-level outer wall of the protective layer22may be lower than the upper outer wall of the protective layer22. The upper-level outer wall of the protective layer22may be lower than the upper-level supporter18S. The height of the upper-level outer wall of the protective layer22may correspond to the distance between the upper-level supporter18S and the first supporter layer16.

The uppermost surface of the lower electrode BE, the upper surface of the upper-level supporter18S, and the uppermost surface of the protective layer22may be positioned at the same level.

Referring toFIG.2F, the first supporter layer16may be etched by using the supporter mask layer25M. The etching process of the first supporter layer16may be performed by self-aligned etching using the supporter mask layer25M. A lower-level supporter16S may be formed by the etching process of the first supporter layer16. The lower-level supporter16S may include a lower-level supporter opening26. The lower-level dielectric supporter opening26may overlap with the upper-level supporter opening (‘25’ inFIG.2E). From the perspective of a top view, the upper-level supporter opening25and the lower-level dielectric supporter opening26may be of the same shape.

During the etching process for forming the lower-level supporter16S, the protective layer22are not etched.

Referring toFIG.2G, the first mold layer15below the lower-level supporter opening26may be removed. The first mold layer15may be removed by a wet dip-out process. The first mold layer15may be selectively removed to expose the surface of the etch stop layer14. The wet dip-out process for removing the first mold layer15may be performed by using an etching solution capable of selectively removing the first mold layer15. When the first mold layer15includes silicon oxide, the first mold layer15may be removed by a wet etching process using hydrofluoric acid (HF).

During the wet dip-out process for removing the second mold layer15, the protective layer22is not etched. After the first mold layer15is removed, a lower-level air gap15G may be formed between the lower-level supporter16S and the etch stop layer14. The lower-level air gap15G may be defined by the removal process of the first mold layer15. The lower-level air gap15G may refer to the space from which the first mold layer15is removed.

As the first mold layer15is removed, a portion of the outer wall of the protective layer22(hereinafter, which will be referred to as a ‘lower-level outer wall’) may be simultaneously exposed. The lower-level outer wall of the protective layer22may be positioned at a level lower than the uppermost surface of the protective layer22. The lower-level outer wall of the protective layer22may not refer to the lowermost level outer wall of the protective layer22. The lowermost level outer wall of the protective layer22may not be exposed by the etch stop layer14. The lower-level outer wall of the protective layer22may be lower than the upper-level outer wall of the protective layer22. The lower-level outer wall of the protective layer22may be a lower level than the lower-level supporter16S. The height of the lower-level outer wall of the protective layer22may correspond to the distance between the lower-level supporter16S and the etch stop layer14.

As described above, during the wet dip-out process for removing the first mold layer15and the second mold layer17, the protective layer22may serve to protect surface of the lower electrode BE from being attacked. For example, as the protective layer22suppresses the penetration of a chemical during the wet dip-out process, the phenomenon that the cylindrical electrode23is etched may be prevented.

Referring toFIG.2H, a trimming process T may be performed. The trimming process T may remove impurities such as metal groups which remains after the first and second mold layers15and17are removed. The lateral spacing distance between the neighboring lower electrodes BE may be increased by the trimming process T. A portion of the protective layer22may be removed by the trimming process T.

The trimming process T may include a partial etching process of the protective layer22. The trimming process T may include a wet etching process of the protective layer22. The trimming process T may include a cleaning process, and the cleaning process may be performed by using a mixture of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and water (H2O). The trimming process T may be a process of cutting portions of the protective layer22exposed by the upper-level air gap17G and the lower-level air gap15G. Here, portions of the protective layer22to be cut may include the upper-level outer wall and the lower-level outer wall of the protective layer22. Since the protective layer22is first exposed to the trimming process T, the surface roughness of the cylindrical electrode23of the lower electrode BE may not be deteriorated. The protective layer22may be a sacrificial material for preventing the loss of the lower electrode BE, and it may be a material that is etched before the lower electrode BE during the trimming process T. Since the protective layer22is an amorphous material, the trimming process T may etch the protective layer22at a uniform etching rate. Accordingly, even though the outer wall of the lower electrode BE is exposed after the protective layer22is etched, the surface roughness of the cylindrical electrode23may not be deteriorated.

As a comparative example, when the protective layer22is omitted, during the trimming process T, the polycrystalline cylindrical electrode23may be etched with a non-uniform surface along a grain boundary having a relatively high surface energy. Accordingly, since the surface of the cylindrical electrode23becomes non-uniform (that is, the surface roughness is poor), the thickness distribution of the dielectric layer27may be deteriorated upon deposition of a dielectric layer27, which is to be formed subsequently. When the thickness distribution of the dielectric layer27is deteriorated, an electric field applied to the dielectric layer27may be increased at a local position where the thickness is thin, which may be a factor that deteriorates the operation failure due to leakage current of the dielectric layer27.

As a comparative example, when the protective layer22is omitted and the cylindrical electrode23includes amorphous titanium nitride or amorphous niobium, the surface roughness of the cylindrical electrode23may be prevented from being deteriorated. However, the amorphous titanium nitride and the amorphous niobium that are used as the cylindrical electrode23have a problem of high resistance and bending.

According to the embodiment of the present invention, since the outer wall of the lower electrode BE is protected by the protective layer22, it is possible to improve the surface roughness of the cylindrical electrode23during the trimming process T. Accordingly, leakage current may be suppressed by making the thickness distribution of the subsequent dielectric layer27uniform. Also, according to the embodiment of the present invention, since the cylindrical electrode23includes a polycrystalline material, it is possible to lower the resistance of the cylindrical electrode23and suppress bending.

As a comparative example, when the protective layer22includes a polycrystalline material, the surface of the protective layer22may be unevenly etched along a grain boundary having a relatively high surface energy during the trimming process T. Due to the un-uniform etching of the protective layer22, the surface of the cylindrical electrode23may be partially exposed before the trimming process T is completed. Accordingly, when the trimming process T is completed, the surface of the cylindrical electrode23may be etched un-uniformly, resulting in a poor surface roughness of the cylindrical electrode23.

According to the embodiment of the present invention, as the protective layer22is formed of an amorphous material, the trimming process T may be performed at a uniform etching rate, thereby preventing deterioration of the surface roughness of the cylindrical electrode23.

As portions of the protective layer22are cut by the trimming process T, the upper-level protective layer pattern22U, the middle-level protective layer pattern22M, and the lower-level protective layer pattern22L may be formed.

The upper-level protective layer pattern22U may directly contact the upper-level supporter18S, and the upper-level protective layer pattern22U may be positioned between the upper outer wall of the lower electrode BE and the upper-level supporter18S. The upper-level protective layer pattern22U may be positioned between the cylindrical electrode23of the lower electrode BE and the upper-level supporter18S.

The middle-level protective layer pattern22M may directly contact the lower-level supporter16S, and the middle-level protective layer pattern22M may be positioned between the middle outer wall of the lower electrode BE and the lower-level supporter16S. The middle-level protective layer pattern22M may be positioned between the cylindrical electrode23of the lower electrode BE and the lower-level supporter16S.

The lower-level protective layer pattern22L may contact the bottom surface of the lower electrode BE and the lowermost sidewalls continuous from the bottom surface. The lower-level protective layer pattern22L may directly contact the etch stop layer14.

By the trimming process T, as portions of the protective layer22are removed, the lateral distances D1and D2between the neighboring lower electrodes BE may be widened. By the trimming process T, the outer wall surface23S of the cylindrical electrode23of the lower electrode BE may be exposed.

The outer wall surface23S of the cylindrical electrode23may include an upper-level outer wall and a lower-level outer wall. The upper-level outer wall of the cylindrical electrode23may be lower than the upper-level protective layer pattern22U and the upper-level supporter18S. The height of the upper-level outer wall of the cylindrical electrode23may correspond to the distance between the upper-level supporter18S and the etch stop layer14. The lower-level outer wall of the cylindrical electrode23may be lower than the middle-level protective layer pattern22M and the lower-level supporter16S. The height of the lower-level outer wall of the cylindrical electrode23may correspond to the distance between the lower-level supporter16S and the etch stop layer14.

The middle-level protective layer pattern22M may be vertically spaced apart from the upper-level protective layer pattern22U. The lower-level protective layer pattern22L may be vertically spaced apart from the middle-level protective layer pattern22M. The upper-level protective layer pattern22U may have a shape surrounding a portion of the upper outer wall of the cylindrical electrode23. The middle-level protective layer pattern22M may be positioned at a lower level than the upper-level protective layer pattern22U, but it may have a shape surrounding a portion of the middle outer wall of the cylindrical electrode23. The lower-level protective layer pattern22L may be positioned at a lower level than the middle-level protective layer pattern22M, but it may have a shape surrounding the bottom surface of the cylindrical electrode23and the lowermost sidewalls continuous from the bottom surface. The distance between the upper-level protective layer pattern22U and the middle-level protective layer pattern22M may be shorter than the distance between the middle-level protective layer pattern22M and the lower-level protective layer pattern22L.

Since the protective layer22includes a conductive material, the lower-level protective layer pattern22L may be electrically connected to the lower electrode BE and the contact plugs13. The lower-level protective layer pattern22L, the upper-level protective layer pattern22U, and the middle-level protective layer pattern22M may include amorphous titanium nitride or amorphous niobium.

The lower-level protective layer pattern22L may include amorphous conductive niobium nitride. Amorphous conductive niobium nitride may be formed by combining amorphous niobium which is used as the protective layer22with nitrogen of titanium nitride which is used as the cylindrical electrode23. The upper-level protective layer pattern22U and the middle-level protective layer pattern22M may also include amorphous conductive niobium nitride.

As a comparative example, when the protective layer22is a dielectric metal oxide such as niobium oxide, titanium oxide, or titanium oxynitride, the protective layer22may have to be removed from the bottom portion of the lower electrode BE to secure a current path between the lower electrode BE and the contact plugs13. Therefore, the comparative example not only requires an etching process for removing the protective layer22from the bottom portion of the lower electrode BE, but also has a high difficulty in the etching process.

According to the embodiment of the present invention, since the protective layer22is a conductive material, the protective layer22may not have to be removed from the bottom portion of the lower electrode BE.

The upper surface of the middle-level protective layer pattern22M and the upper surface of the lower-level supporter16S may be positioned at the same level.

Since the bottom surface of the lower electrode BE is embedded in the lower-level protective layer pattern22L, structural stability of the lower electrode BE may be increased from the subsequent process.

The trimming process T may be performed in a state that a supporter mask layer25M remains. According to another embodiment of the present invention, the trimming process T2may be performed after the supporter mask layer25M is removed.

By the series of processes described above, a multi-level supporter MLDS supporting the outer wall of the lower electrode BE and a multi-level protective structure MLCS may be formed. The multi-level supporter MLDS may include an upper-level supporter18S and a lower-level supporter16S, and the multi-level protective structure MLCS may include the upper-level protective layer pattern22U, the middle-level protective layer pattern22M, and the lower-level protective layer pattern22L.

Referring toFIG.2I, after the supporter mask layer25M is removed, a dielectric layer27may be formed over the lower electrode BE. The dielectric layer27may include a high-k material having a higher dielectric constant than silicon oxide. High-k materials include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). According to another embodiment of the present invention, the dielectric layer27may be formed of a composite layer including two or more layers of the high-k material mentioned above. According to the embodiment of the present invention, the dielectric layer27may be formed of a zirconium oxide-based material having good leakage current characteristics while sufficiently lowering the equivalent oxide film thickness (EOT). For example, it may include a ZAZ (ZrO2/Al2O3/ZrO2) stack. According to yet another embodiment of the present invention, the dielectric layer27may include a TiO2/ZrO2/Al2O3/ZrO2stack, a TiO2/HfO2/Al2O3/HfO2stack, a Ta2O5/ZrO2/Al2O3/ZrO2stack, or a Ta2O5/HfO2/Al2O3/HfO2stack.

The dielectric layer27may cover portions of the multi-level supporter MLDS and portions of the multi-level protective structure MLCS.

Since the surface on which the dielectric layer27is to be formed, that is, the surface roughness of the cylindrical electrode23is improved, it is possible to suppress the leakage current by making the thickness distribution of the dielectric layer27uniform when the dielectric layer27is formed.

Next, an upper electrode28may be formed over the dielectric layer27. The upper electrode28may fill the space between the neighboring lower electrodes BE. The upper electrode28may extend to cover the upper portions of the lower electrodes BE. The upper electrode28may include a conductive material. The upper electrode28may be formed by stacking a liner electrode, a gap-fill electrode, and a low-resistance electrode (not shown) in the mentioned order. The liner electrode of the upper electrode28may include titanium nitride, and the gap-fill electrode of the upper electrode28may include silicon germanium. The low-resistance electrode of the upper electrode28may include tungsten or tungsten nitride.

FIGS.3A to3Dare cross-sectional views illustrating an example of a method for fabricating a semiconductor device in accordance with an embodiment of the present invention.FIGS.3A to3Dmay be similar to the fabrication method shown inFIGS.2A to2I. Hereinafter, a detailed description on the same components may be omitted.

An upper-level supporter opening25and an upper-level supporter18S may be formed by a series of the processes illustrated inFIGS.2A to2E. Subsequently, the second mold layer17below the upper-level supporter opening25may be removed. As the second mold layer17is removed, an upper-level air gap17G may be formed between the first supporter layer16and the upper-level supporter18S. A portion of the protective layer22may be exposed by the upper-level air gap17G.

Subsequently, as illustrated inFIG.3A, a primary trimming process T1may be performed. The primary trimming process T1may remove impurities such as metal groups that remain after the second mold layer17is removed. The distance between the neighboring lower electrodes BE may be increased by the primary trimming process T1. A portion of the protective layer22may be removed by the primary trimming process T1.

The primary trimming process T1may include a partial etching process of the protective layer22. The primary trimming process T1may include a wet etching process of the protective layer22. The primary trimming process T1may include a cleaning process, and the cleaning process may be performed by using a mixture of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and water (H2O). The primary trimming process T1may be a process of partially etching portions (the upper-level outer wall) of the protective layer22exposed by the upper-level air gap17G. Since the protective layer22is first exposed to the primary trimming process T1, the surface roughness of the cylindrical electrode23of the lower electrode BE may not be deteriorated.

As a portion of the protective layer22is removed, the upper-level air gap17G may be laterally expanded. After the primary trimming process T1, a non-trimmed protective layer22N and a partially trimmed protective layer22T may be formed. The non-trimmed protective layer22N may refer to a protective layer that is not exposed to the primary trimming process T1, and the partially trimmed protective layer22T may refer to a protective layer whose thickness becomes thinner by the primary trimming process T1. The non-trimmed protective layer22N and the partially trimmed protective layer22T may be formed to be continuous with each other to cover the cylindrical electrode23of the lower electrode BE.

The non-trimmed protective layer22N may include an upper-level non-trimmed protective layer22N disposed between the upper-level supporter18S and the cylindrical electrode23. The non-trimmed protective layer22N may include a lower-level non-trimmed protective layer22N disposed between the first mold layer15and the cylindrical electrode23.

The first trimming process T1may be performed while the supporter mask layer25M remains. According to another embodiment of the present invention, the first trimming process T1may be performed after the supporter mask layer25M is removed.

Referring toFIG.3B, the first supporter layer16may be etched by using the supporter mask layer25M. The etching process of the first supporter layer16may be performed by a self-aligned etching process using the supporter mask layer25M. A lower-level supporter16S may be formed by the etching process of the first supporter layer16. The lower-level supporter16S may include a plurality of lower-level supporter openings26. The lower-level supporter openings26may overlap with the upper-level supporter openings25. From the perspective of a top view, the upper-level supporter openings25and the lower-level supporter openings26may have the same shape.

During the etching process for forming the lower-level supporter16S, the non-trimmed protective layer22N and the partially trimmed protective layer22T are not etched.

Referring toFIG.3C, the first mold layer15below the lower-level supporter openings26may be removed. The first mold layer15may be removed by a wet dip-out process. The first mold layer15may be selectively removed to expose the surface of the etch stop layer14. The wet dip-out process for removing the first mold layer15may be performed by using an etching solution capable of selectively removing the first mold layer15. When the first mold layer15includes silicon oxide, the first mold layer15may be removed by a wet etching process using hydrofluoric acid (HF).

During the wet dip-out process for removing the second mold layer15, the non-trimmed protective layer22N and the partially trimmed protective layer22T are not etched. After the first mold layer15is removed, a lower-level air gap15G may be formed between the lower-level supporter16S and the etch stop layer14. The lower-level air gap15G may be defined by the removal process of the first mold layer15. The non-trimmed protective layer22N may be exposed by the lower-level air gap15G. The partially trimmed protective layer22T may be exposed by the upper-level air gap17G.

Referring toFIG.3D, a secondary trimming process T2may be performed. The secondary trimming process T2may increase the spacing distance between the neighboring lower electrodes BE. The second trimming process T2may remove impurities such as metal groups remaining after the first mold layer15is removed. The spacing distance between the neighboring lower electrodes BE may be increased by the secondary trimming process T2. A portion of the non-trimmed protective layer22N and the partially trimmed protective layer22T may be removed by the secondary trimming process T2. Here, the portion of the non-trimmed protective layer22N which is removed herein may be a lower-level non-trimmed protective layer22N exposed by the lower-level air gap15G. The upper-level non-trimmed protective layer22N between the upper-level supporter18S and the cylindrical electrode23may not be removed.

The secondary trimming process T2may include an etching process of the non-trimmed protective layer22N and the partially trimmed protective layer22T. The secondary trimming process T2may include a wet etching process of the non-trimmed protective layer22N and the partially trimmed protective layer22T. The secondary trimming process T2may include a cleaning process, and the cleaning process may be performed by using a mixture of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and water (H2O). The secondary trimming process T2may be a process of cutting the partially trimmed protective layer22T which is exposed by the upper-level air gap17G and the lower-level non-trimmed protective layer22N which is exposed by the lower-level air gap15G. Since the partially trimmed protective layer22T and the lower-level non-trimmed protective layer22N are first exposed to the secondary trimming process T2, the surface roughness of the cylindrical electrode23of the lower electrode BE may not be deteriorated.

As a result of the second trimming process T2, the upper-level protective layer pattern22U, the middle-level protective layer pattern22M, and the lower-level protective layer pattern22L may be formed. The upper-level protective layer pattern22U, the middle-level protective layer pattern22M, and the lower-level protective layer pattern22L may be formed by cutting the partially trimmed protective layer22T and the non-trimmed protective layer22N. The upper-level protective layer pattern22U may refer to the upper-level non-trimmed protective layer22N remaining by fully cutting the partially trimmed protective layer22T. The middle-level protective layer pattern22M and the lower-level protective layer pattern22L may refer to a portion remaining by partially cutting the lower-level non-trimmed protective layer22N.

The upper-level protective layer pattern22U may directly contact the upper-level supporter18S, and it may be positioned between the upper outer wall of the lower electrode BE and the upper-level supporter18S.

The middle-level protective layer pattern22M may directly contact the lower-level supporter16S, and it may be positioned between the middle outer wall of the lower electrode BE and the lower-level supporter16S.

The lower-level protective layer pattern22L may contact the bottom of the lower electrode BE and the sidewalls of the lowermost portion which is continuous from the bottom surface of the lower electrode BE. The lower-level protective layer pattern22L may directly contact the etch stop layer14.

The distance D1and D2between the neighboring lower electrodes BE may be widened as the partially trimmed protective layer22T and a portion of the lower-level non-trimmed protective layer22N are cut by the secondary trimming process T2. A portion23S of the surface of the cylindrical electrode23of the lower electrode BE may be exposed by the secondary trimming process T2.

The outer wall surface23S of the cylindrical electrode23may include the upper-level outer wall and the lower-level outer wall. The upper-level outer wall of the cylindrical electrode23may be lower than the upper-level protective layer pattern22U and the upper-level supporter18S. The height of the upper-level outer wall of the cylindrical electrode23may correspond to the distance between the upper-level supporter18S and the etch stop layer14. The lower-level outer wall of the cylindrical electrode23may be lower than the middle-level protective layer pattern22M and the lower-level supporter16S. The height of the lower-level outer wall of the cylindrical electrode23may correspond to the distance between the lower-level supporter16S and the etch stop layer14.

The middle-level protective layer pattern22M may be vertically spaced apart from the upper-level protective layer pattern22U. The lower-level protective layer pattern22L may be vertically spaced apart from the middle-level protective layer pattern22M. The upper-level protective layer pattern22U may have a shape surrounding a portion of the upper outer wall of the cylindrical electrode23. The middle-level protective layer pattern22M may be positioned at a lower level than the upper-level protective layer pattern22U while surrounding a portion of the middle outer wall of the cylindrical electrode23. The lower-level protective layer pattern22L may be positioned at a lower level than the middle-level protective layer pattern22M, while having a shape surrounding the bottom surface of the cylindrical electrode23and the sidewalls of the lowermost portion which is continuous from the bottom surface of the cylindrical electrode23. The distance between the upper-level protective layer pattern22U and the middle-level protective layer pattern22M may be shorter than the distance between the middle-level protective layer pattern22M and the lower-level protective layer pattern22L.

The lower-level protective layer pattern22L may be electrically connected to the lower electrode BE and the contact plugs13. The lower-level protective layer pattern22L, the upper-level protective layer pattern22U, and the middle-level protective layer pattern22M may include amorphous titanium nitride or amorphous niobium.

The lower-level protective layer pattern22L may include amorphous conductive niobium nitride. Amorphous conductive niobium nitride may be formed by combining amorphous niobium which is used as the protective layer22with nitrogen of titanium nitride which is used as the cylindrical electrode23. The upper-level protective layer pattern22U and the middle-level protective layer pattern22M may also include amorphous conductive niobium nitride.

Since the bottom surface of the lower electrode BE is embedded in the lower-level protective layer pattern22L, structural stability of the lower electrode BE may be increased from the subsequent process.

The second trimming process T2may be performed while the supporter mask layer25M remains. According to another embodiment of the present invention, the secondary trimming process T2may be performed after the supporter mask layer25M is removed.

By a series of the processes as described above, a multi-level supporter MLDS supporting the outer wall of the lower electrode BE and a multi-level protective structure MLCS may be formed. The multi-level supporter MLDS may include an upper-level supporter18S and a lower-level supporter16S, and the multi-level protective structure MLCS may include an upper-level protective layer pattern22U, the middle-level protective layer pattern22M, and the lower-level protective layer pattern22L.

Subsequently, as illustrated inFIG.2I, after the supporter mask layer25M is removed, the dielectric layer27and the upper electrode28may be sequentially formed over the lower electrode BE.

FIGS.4A to4Care cross-sectional views illustrating an example of a method for fabricating a semiconductor device in accordance with an embodiment of the present invention.FIGS.4A to4Cmay be similar to the fabrication method illustrated inFIGS.2A to2I. Also,FIGS.4A to4Cmay be similar to the fabrication method illustrated inFIGS.3A to3D. Hereinafter, a detailed description on the same constituent elements may be omitted.

An upper-level supporter18S and a lower-level supporter16S may be formed by the processes illustrated inFIGS.2A to2G. The second mold layer17may be removed from the space between the lower-level supporter16S and the upper-level supporter18S to form an upper-level air gap17G. Also, the first mold layer15may be removed from the space between the lower-level supporter16S and the etch stop layer14to form a lower-level air gap15G. The upper-level outer wall of the protective layer22may be exposed by the upper-level air gap17G. Also, the lower-level outer wall of the protective layer22may be exposed by the lower-level air gap15G.

As described above, according to the embodiment of the present invention, after the first and second mold layers15and17are removed by a wet dip-out process, a trimming process T3may be performed as illustrated inFIG.4A. After the first and second mold layers15and17are removed, the protective layer22may include an exposed portion and a non-exposed portion. The exposed portion of the protective layer22may refer to the outer wall that is exposed as the first and second mold layers15and17are removed, and the non-exposed portion of the protective layer22may refer to a portion contacting the upper-level supporter18S and the lower-level supporter16S. Also, the non-exposed portion of the protective layer22may include a portion in contact with the etch stop layer14.

The trimming process T3may increase the spacing distance between the neighboring lower electrodes BE. The trimming process T3may remove impurities such as metal groups remaining after the first and second mold layers15and17are removed. A portion of the protective layer22may be removed by the trimming process T3.

The trimming process T3may include a partial etching process on the exposed portion of the protective layer22. The trimming process T3may include a wet etching process of the protective layer22. The trimming process T3may include a cleaning process, and the cleaning process may be performed by using a mixture of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O). The trimming process T3may be a process of partially etching portions of the protective layer22exposed by the upper-level air gap17G and the lower-level air gap15G. The trimming process T3may include a process of thinning the portions of the protective layer22exposed by the upper-level air gap17G and the lower-level air gap15G. Since the protective layer22is first exposed to the trimming process T3, the surface roughness of the cylindrical electrode23of the lower electrode BE may not be deteriorated.

After the trimming process T3, non-trimmed protective layers22N and partially trimmed protective layers22T may be formed. The non-trimmed protective layers22N may refer to a protective layer which is not exposed to the trimming process T3, and the partially trimmed protective layers22T may refer to a portion whose thickness becomes thin by the trimming process T3. The partially trimmed protective layers22T may be thinner than the non-trimmed protective layers22N. The non-trimmed protective layers22N and the partially trimmed protective layers22T may be continuous to have a shape covering the cylindrical electrode23of the lower electrode BE. The partially trimmed protective layers22T may be an exposed portion of the protective layer and may be referred to as thinned exposed portions. The non-trimmed protective layers22N may be a non-exposed portion of the protective layer22.

The trimming process T3may be performed while the supporter mask layer25M remains. According to another embodiment of the present invention, the trimming process T3may be performed after the supporter mask layer25M is removed.

By the trimming process T3, as the thin partially trimmed protective layers22T are formed, the distance between the neighboring lower electrodes BE may be widened.

Referring toFIG.4B, after the supporter mask layer25M is removed, a dielectric layer27may be formed. The dielectric layer27may be formed over the partially trimmed protective layers22T.

The partially trimmed protective layers22T may be oxidized by their exposure to an oxygen atmosphere while the dielectric layer27is formed or before the dielectric layer27is formed. As a result, a booster layer22B may be formed between the dielectric layer27and the lower electrode BE. The booster layer22B may serve to amplify the dielectric constant of the dielectric layer27.

The non-trimmed protective layers22N may not be oxidized while the dielectric layer27is formed. Accordingly, an upper-level protective layer pattern22U, a middle-level protective layer pattern22M, and a lower-level protective layer pattern22L may be formed.

A booster layer22B may be positioned between the middle-level protective layer pattern22M and the upper-level protective layer pattern22U. A booster layer22B may be positioned between the lower-level protective layer pattern22L and the middle-level protective layer pattern22M. The upper-level protective layer pattern22U, the middle-level protective layer pattern22M, the lower-level protective layer pattern22L, and the booster layer22B may be continuous.

Referring toFIG.4C, the upper electrode28may be formed over the dielectric layer27.

As described above, the semiconductor device in accordance with the embodiment of the present invention may include contact plugs13formed over a substrate11, lower electrodes BE over the contact plugs13, multi-level supporters18S and16S supporting an outer wall of the lower electrodes BE, upper-level and middle-level protective layer patterns22U and22M between the multi-level supporters18S and16S and the lower electrodes BE, and lower-level protective layer patterns22L positioned between the lower electrodes BE and the contact plugs13.

FIG.5is an enlarged view of a portion22A shown inFIG.4C.

Referring toFIG.5, a booster layer22B may be positioned between the dielectric layer27and the cylindrical electrode23. The booster layer22B may be an oxide of the partially trimmed protective layer22T. For example, when the partially trimmed protective layer22T includes niobium, the booster layer22B may include niobium oxide.

According to the embodiment of the present invention described above, since the protective layer22is first exposed during the trimming process T3, it is possible to prevent deterioration in the surface roughness which may be caused by the grain boundary of the grains23G of the cylindrical electrode23.

Also, it is possible to amplify the dielectric constant of the dielectric layer27by forming the booster layer22B.

According to another embodiment of the present invention, even when a single supporter is applied, that is, even when only one supporter among the upper-level supporter18S and the lower-level supporters16S is applied, the surface roughness of the dielectric layer27may be improved by applying the protective layer22.

According to another embodiment of the present invention, even when a supporter of at least three or more layers is applied, the surface roughness of the dielectric layer27may be improved by applying the protective layer22.

According to the embodiment of the present invention, the surface roughness of a lower electrode may be improved by forming a protective layer on the outer wall of the lower electrode. This makes the thickness distribution of a dielectric layer uniform and suppresses the leakage current.

According to the embodiment of the present invention, structural stability of the lower electrode may be increased by forming a hybrid supporter including a supporter and a protective layer pattern.

According to the embodiment of the present invention, the capacitance of the capacitor may be further increased as the dielectric constant of the dielectric layer is amplified by a booster layer.

While the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.