Patent ID: 12198974

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Embodiments will be described with respect to a specific context, namely, a dielectric gap-filling process for a semiconductor device. In some embodiments, the dielectric gap-filling process may be used to form isolation regions of a semiconductor device. In other embodiments, the dielectric gap-filling process may be used to form an interlayer dielectric layer over a semiconductor device. In some embodiments, the dielectric gap-filling process includes forming a precursor soak layer in a trench or a recess before filing the trench or the recess with a dielectric material. In other embodiments, the dielectric gap-filling process further includes performing an ultraviolet/oxygen treatment followed by a thermal treatment. Various embodiments presented herein allow for forming dielectric layers having improved film quality near seam regions of the dielectric layers and allow for reducing or avoiding oxidation of a substrate. Various embodiments further allow for avoiding high temperature and lengthy anneal process and, consequently, improving a wafer-per-hour (WPH) yield and reducing production cost. Various embodiments presented herein are discussed in the context of a FinFET device formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar transistor devices, multiple-gate transistor devices, 2D transistor devices, gate-all-around transistor devices, nanowire transistor devices, or the like.

FIG.1illustrates an example of a fin field-effect transistor (FinFET) device100in a three-dimensional view. The FinFET device100comprises a fin105on a substrate101. The substrate101includes isolation regions103, and the fin105protrudes above and from between neighboring isolation regions103. A gate dielectric107is along sidewalls and over a top surface of the fin105, and a gate electrode109is over the gate dielectric107. Source/drain regions111and113are disposed in opposite sides of the fin105with respect to the gate dielectric107and gate electrode109. The FinFET device100illustrated inFIG.1is provided for illustrative purposes only and is not meant to limit the scope of the present disclosure. As such, many variations are possible, such as epitaxial source/drain regions, multiple fins, multilayer fins, etc.

FIGS.2A-6A,12A-19A,21A-25A,14B-19B,21B-25B, and15C-25Care cross-sectional views of intermediate stages in the manufacturing of a FinFET device200in accordance with some embodiments. InFIGS.2A-6A,12A-19A,21A-25A,14B-19B,21B-25B, and15C-25C, figures ending with an “A” designation are illustrated along the reference cross-section A-A shown inFIG.1, except for multiple FinFETs and multiple fins per FinFET; figures ending with a “B” designation are illustrated along the reference cross-section B-B shown inFIG.1; and figures ending with a “C” designation are illustrated along the cross-section C-C shown inFIG.1.

FIG.2Aillustrates a substrate201. The substrate201may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate201may be a wafer, such as a silicon wafer. Generally, an SOI substrate comprises a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate201may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; combinations thereof; or the like.

The substrate201may further include integrated circuit devices (not shown). As one of ordinary skill in the art will recognize, a wide variety of integrated circuit devices such as transistors, diodes, capacitors, resistors, the like, or combinations thereof may be formed in and/or on the substrate201to generate the structural and functional requirements of the design for the FinFET device200. The integrated circuit devices may be formed using any suitable methods.

In some embodiments, appropriate wells (not shown) may be formed in the substrate201. In some embodiments where the FinFET device200is an n-type device, the wells are p-wells. In some embodiments where the FinFET device200is a p-type device, the wells are n-wells. In other embodiments, both p-wells and n-wells are formed in the substrate201. In some embodiments, p-type impurities are implanted into the substrate201to form the p-wells. The p-type impurities may be boron, BF2, or the like, and may be implanted to a concentration in a range from about 1017cm−3to about 1022cm−3. In some embodiments, n-type impurities are implanted into the substrate201to form the n-wells. The n-type impurities may be phosphorus, arsenic, or the like, and may be implanted to a concentration in a range from about 1017cm−3to about 1018cm−3. After implanting the appropriate impurities, an annealing process may be performed on the substrate to activate the p-type and n-type impurities that were implanted.

FIG.2Afurther illustrates the formation of a mask203over the substrate201. In some embodiments, the mask203may be used in a subsequent etching step to pattern the substrate201(seeFIG.3A). In some embodiments, the mask203may comprise one or more mask layers. As shown inFIG.2A, in some embodiments, the mask203may include a first mask layer203A and a second mask layer203B over the first mask layer203A. The first mask layer203A may be a hard mask layer, may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, a combination thereof, or the like, and may be formed using any suitable process, such as thermal oxidation, thermal nitridation, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), a combination thereof, or the like. The first mask layer203A may be used to prevent or minimize etching of the substrate201underlying the first mask layer203A in the subsequent etching step (seeFIG.3A). The second mask layer203B may comprise a photoresist, and in some embodiments, may be used to pattern the first mask layer203A for use in the subsequent etching step. The second mask layer203B may be formed using a spin-on technique and may be patterned using acceptable photolithography techniques. In some embodiments, the mask203may comprise three or more mask layers.

FIG.3Aillustrates the formation of semiconductor strips303in the substrate201. First, the mask layers203A and203B are patterned, where openings in mask layers203A and203B expose areas of the substrate201where trenches301will be formed. Next, an etching process is performed, where the etching process creates the trenches301in the substrate201through the openings in the mask203. The remaining portions of the substrate201underlying a patterned mask203form a plurality of semiconductor strips303. The etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), a combination thereof, or the like. The etch process may be anisotropic. In some embodiments, after forming the semiconductor strips303, any remaining portions of the mask203may be removed by any suitable process. In other embodiments, portions of the mask203, such as the first mask layer203A, may remain over the semiconductor strips303. In some embodiments, the semiconductor strips303may have a height H1between about 45 nm and about 55 nm. In some embodiments, the semiconductor strips303may have a width W, between about 5 nm and about 10 nm.

FIGS.4A-6Aillustrate a dielectric gap-filling process for forming one or more dialectic materials in the trenches301.FIG.4Aillustrates the formation of a conformal liner layer401on sidewalls and bottom surfaces of the trenches301.FIG.5Aillustrates the formation of a precursor soak layer501over the liner layer401.FIG.6Aillustrated the formation of a dielectric layer601in the trenches301. The details of the dielectric gap-filling process are provided below with reference toFIGS.7-11.

FIG.7is a flow diagram illustrating a dielectric gap-filling process700in accordance with some embodiments. Referring toFIGS.4A and7, in step701, the liner layer401is formed on the sidewalls and the bottom surfaces of the trenches301. In some embodiments, the liner layer401may comprise a semiconductor (e.g., silicon) nitride, a semiconductor (e.g., silicon) oxide, a thermal semiconductor (e.g., silicon) oxide, a semiconductor (e.g., silicon) oxynitride, a polymer, combinations thereof, or the like. The formation of the liner layer401may include any suitable method, such as ALD, CVD, high density plasma chemical vapor deposition (HDP-CVD), PVD, a combination thereof, or the like. In an embodiment where the liner layer401comprises silicon nitride, the liner layer401is formed by an ALD process using a precursor such as DCS (SiCl2H2), a silicon tetrachloride, a combination thereof, or the like. In an embodiment where the liner layer401comprises silicon oxide, the liner layer401is formed by an ALD process using a precursor such as LTO520, SAM24, 3DMAS, a combination thereof, or the like. In some embodiments, the liner layer401has a thickness between about 20 Å and about 40 Å, such as about 20 Å.

Referring toFIGS.5A and7, in step703, the precursor soak layer501is formed over the liner layer401. In some embodiments, the precursor soak layer501may comprise an oxide, such as silicon oxide, or the like. The formation of the precursor soak layer501may include any suitable method, such as ALD, CVD, HDP-CVD, a combination thereof, or the like. In some embodiments wherein the precursor soak layer501comprises silicon oxide formed using ALD, the formation of the precursor soak layer501may comprise steps707and709. In some embodiments, the substrate201comprising the structure ofFIG.4Ais placed on a support structure (such as, for example, a chuck) within a process chamber. The support structure may be configured to rotate the substrate201during the formation of the precursor soak layer501, where one full rotation of the substrate201is one cycle of the deposition process. In some embodiments, each cycle has a duration between about 6 sec and about 60 sec.

In step707, after placing the substrate201within the process chamber, a first silicon precursor is flown into the process chamber. The first silicon precursor may include LTO520, SAM24, 3DMAS, a combination thereof, or the like.FIG.11illustrates a structural formula1101of LTO520, where R may comprise C1-C5alkyl, C2-C5alkenyl, C2-C20alkynyl, or the like.FIG.11further illustrates a structural formula1103of 3DMAS and a structural formula1105of SAM24. In some embodiments, the first silicon precursor is flown into the process chamber for N1 cycles. In some embodiments, the first silicon precursor has a flow rate between about 50 sccm and about 100 sccm. In some embodiments, the first silicon precursor is flown into the process chamber for a duration between about 60 sec and about 90 sec. In some embodiments, N1 is between 1 and 5, such as 5.

In step709, a second silicon precursor and a first oxygen precursor may be flown into the process chamber for N2 cycles. The second silicon precursor may be chosen from same candidate chemicals as the first silicon precursor described above with respect to step707, and the description is not repeated herein. In some embodiments, the first silicon precursor and the second silicon precursor may comprise a same chemical. In other embodiments, the first silicon precursor and the second silicon precursor may comprise different chemicals. In some embodiments, the first oxygen precursor may include O2, O3, a combination thereof, or the like. In some embodiments where the first oxygen precursor is O3, the first oxygen precursor may have a density between about 50 g/m3and about 400 g/m3, such as about 300 g/m3. In some embodiments, the second silicon precursor has a flow rate between about 10 sccm and about 300 sccm. In some embodiments, the first oxygen precursor has a flow rate between about 10 sccm and about 100 sccm. In some embodiments, the second silicon precursor and the first oxygen precursor are flown into the process chamber for a duration between about 6 sec and about 120 sec. In some embodiments, N2 is between 1 and 20, such as 5. In some embodiments, N2 may be different from N1.

In some embodiments, the cycle numbers N1 and N2 may be varied to adjust silicon content in the precursor soak layer501. In some embodiments, the precursor soak layer501is a silicon-rich layer having silicon content of between about 30 atomic % and about 40 atomic %. In some embodiments, the cycle numbers N1 and N2 may be further varied to adjust a thickness of the precursor soak layer501. In some embodiments, the precursor soak layer501may have a thickness between about 3 Å and about 5 Å.

Referring toFIGS.6A and7, in step705, after forming the precursor soak layer501, the dielectric layer601is formed in the trenches301(seeFIG.5A). The dielectric layer601may comprise an oxide, such as silicon oxide, a nitride, such as silicon nitride, a combination thereof, or the like, and may be formed by ALD, CVD, HDP-CVD, flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), a combination thereof, or the like. Other insulation materials formed by any acceptable processes may be also used. In some embodiments where the dielectric layer601comprises silicon oxide formed using ALD, a third silicon precursor and a second oxygen precursor is flown into the process chamber for Nd cycles. The third silicon precursor may be chosen from same candidate chemicals as the first silicon precursor described above with respect to step707, and the description is not repeated herein. In some embodiments, the first silicon precursor, the second silicon precursor and the third silicon precursor may comprise a same chemical. In other embodiments, the third silicon precursor and at least one of the first silicon precursor and the second silicon precursor may comprise different chemicals. The second oxygen precursor may be chosen from same candidate chemicals as the first oxygen precursor described above with respect to step709, and the description is not repeated herein. In some embodiments, the first oxygen precursor and the second oxygen precursor may comprise a same chemical. In other embodiments, the first oxygen precursor and the second oxygen precursor may comprise different chemicals.

In some embodiments, the deposition process for forming the dielectric layer601may be a plasma-assisted process or a plasma-enhanced process. In such embodiments, an oxygen-containing plasma, such as an O2plasma, is flown into the process chamber in addition to the third silicon precursor and the second oxygen precursor. Radio frequency (RF) power for generating the oxygen-containing plasma may be between about 2 KW and about 3 KW. In some embodiments, the third silicon precursor has a flow rate between about 10 sccm and about 300 sccm. In some embodiments, the second oxygen precursor has a flow rate between about 10 sccm and about 100 sccm. In some embodiments, the oxygen-containing plasma has a flow rate between about 10 sccm and about 100 sccm. In some embodiments, the third silicon precursor and the second oxygen precursor are flown into the process chamber for a duration between about 6 sec and about 120 sec. In some embodiments, Nd is between 1 and 20, such as 5.

Referring further toFIG.6A, the dielectric layer601may comprise a seam603within each of the trenches301(seeFIG.5A) due to the deposition process properties. In some embodiments, regions of the dielectric layer601near the seams603may be weaker than the rest of the dielectric layer601. For example, the regions of the dielectric layer601near the seams603may have a higher etch rate than the rest of the dielectric layer601and voids may be formed near the seams603during and/or after preforming subsequent processes on the dielectric layer601, such as a polishing process, an etching process, or the like. By forming the precursor soak layer501before forming the dielectric layer601, the regions of the dielectric layer601near the seams603may be strengthened and formation of voids in the dielectric layer601may be reduced or avoided. In some embodiments where the precursor soak layer501and the dielectric layer601comprise a same material, an interface between the precursor soak layer501and the dielectric layer601may not be detectable.

FIG.8is a flow diagram illustrating a dielectric gap-filling process800in accordance with some embodiments. Referring toFIGS.4A and8, in step801, the liner layer401is formed on the sidewalls and the bottom surfaces of the trenches301. In some embodiments, step801is similar to step701described above with reference toFIG.7and the description is not repeated herein.

Referring toFIGS.5A and8, in step803, the precursor soak layer501is formed over the liner layer401. In some embodiments wherein the precursor soak layer501comprises silicon oxide formed using ALD, the formation of the precursor soak layer501may comprise one or more deposition loops, where each deposition loop comprises steps807,809,811and813. In some embodiments, step803may comprise N7 deposition loops. In some embodiments, N7 is between about 1 and about 5. In some embodiments, the substrate201comprising the structure ofFIG.4Ais placed on a support structure (such as, for example, a chuck) within a process chamber.

In step807, after placing the substrate201within the process chamber, a first silicon precursor is flown into the process chamber. The first silicon precursor may include LTO520, SAM24, 3DMAS, a combination thereof, or the like. In some embodiments, the first silicon precursor is flown into the process chamber for N3 cycles. In some embodiments, the first silicon precursor has a flow rate between about 50 sccm and about 100 sccm. In some embodiments, the first silicon precursor is flown into the process chamber for a duration between about 60 sec and about 90 sec. In some embodiments, N3 is between 1 and 20, such as 5.

In step809, a second silicon precursor and a first oxygen precursor may be flown into the process chamber for N4 cycles. The second silicon precursor may be chosen from same candidate chemicals as the first silicon precursor described above with respect to step807, and the description is not repeated herein. In some embodiments, the first silicon precursor and the second silicon precursor may comprise a same chemical. In other embodiments, the first silicon precursor and the second silicon precursor may comprise different chemicals. In some embodiments, the first oxygen precursor may include O2, O3, a combination thereof, or the like. In some embodiments where the first oxygen precursor is O3, the first oxygen precursor may have a density between about 100 g/m3and about 300 g/m3, such as about 300 g/m3. In some embodiments, the second silicon precursor has a flow rate between about 50 sccm and about 300 sccm. In some embodiments, the first oxygen precursor has a flow rate between about 10 sccm and about 100 sccm. In some embodiments, the second silicon precursor and the first oxygen precursor are flown into the process chamber for a duration between about 6 sec and about 60 sec. In some embodiments, N4 is between 1 and 20, such as 5. In some embodiments, N4 may be different from N3.

In step811, a third silicon precursor is flown into the process chamber for N5 cycles. The third silicon precursor may be chosen from same candidate chemicals as the first silicon precursor described above with respect to step807, and the description is not repeated herein. In some embodiments, the first silicon precursor, the second silicon precursor and the third silicon precursor may comprise a same chemical. In other embodiments, the third silicon precursor and at least one of the first silicon precursor and the second silicon precursor may comprise different chemicals. In some embodiments, the third silicon precursor has a flow rate between about 50 sccm and about 100 sccm. In some embodiments, the third silicon precursor is flown into the process chamber for a duration between about 12 sec and about 24 sec. In some embodiments, N5 is between 1 and 5, such as 2. In some embodiments, N5 may be different from at least one of N3 and N4.

In step813, a fourth silicon precursor and a second oxygen precursor may be flown into the process chamber for N6 cycles. The fourth silicon precursor may be chosen from same candidate chemicals as the first silicon precursor described above with respect to step807, and the description is not repeated herein. In some embodiments, the first silicon precursor, the second silicon precursor, the third silicon precursor and the fourth silicon precursor may comprise a same chemical. In other embodiments, the fourth silicon precursor and at least one of the first silicon precursor, the second silicon precursor and the third silicon precursor may comprise different chemicals. The second oxygen precursor may be chosen from same candidate chemicals as the first oxygen precursor described above with respect to step809, and the description is not repeated herein. In some embodiments, the first oxygen precursor and the second oxygen precursor may comprise a same chemical. In other embodiments, the first oxygen precursor and the second oxygen precursor may comprise different chemicals. In some embodiments where the second oxygen precursor is O3, the second oxygen precursor may have a density between about 100 g/m3and about 300 g/m3, such as about 300 g/m3. In some embodiments, the fourth silicon precursor has a flow rate between about 10 sccm and about 300 sccm. In some embodiments, the second oxygen precursor has a flow rate between about 10 sccm and about 100 sccm. In some embodiments, the fourth silicon precursor and the second oxygen precursor are flown into the process chamber for a duration between about 6 sec and about 120 sec. In some embodiments, N6 is between 1 and 5, such as 3. In some embodiments, N6 may be different from at least one of N3, N4 and N5.

In some embodiments, the cycle numbers N3, N4, N5, N6 and N7 may be varied to adjust silicon content in the precursor soak layer501. In some embodiments, the precursor soak layer501is silicon-rich layer having silicon content of between about 30 atomic % and about 40 atomic %. In some embodiments, the cycle numbers N3, N4, N5, N6 and N7 may be further varied to adjust a thickness of the precursor soak layer501. In some embodiments, the precursor soak layer501may have a thickness between about 8 Å and about 12 Å. In some embodiments, the precursor soak layer501formed in step803of the dielectric gap-filling process800may be thicker than the precursor soak layer501formed in step703of the dielectric gap-filling process700(seeFIG.7). By increasing the thickness of the precursor soak layer501, oxidation of the substrate201may be prevented or reduced.

Referring toFIGS.6A and8, in step805, after forming the precursor soak layer501, the dielectric layer601is formed in the trenches301(seeFIG.5A). In some embodiments, step805may be similar to step705of the dielectric gap-filling process700described above with reference toFIG.7and the description is not repeated herein.

FIG.9is a flow diagram illustrating a dielectric gap-filling process900in accordance with some embodiments. Referring toFIGS.9and6A, after performing the dielectric gap-filling process700illustrated above with reference toFIG.7, the dielectric gap-filling process900continues to step901, where an ultraviolet/oxygen treatment is performed on the dielectric layer601. In some embodiments, the ultraviolet/oxygen treatment comprises subjecting the dielectric layer601to ultraviolet (UV) radiation in an oxygen ambient. In some embodiment, an intensity of the UV radiation is between about 15 mW/cm2and about 25 mW/cm2. In some embodiments, the oxygen ambient may comprise a molecular oxygen gas (O2), or the like. In some embodiments, the UV radiation breaks weak bonds (such as, for example, Si—H bonds) and precursor byproducts near the seams603of the dielectric layer601, while the oxygen ambient provides the oxygen source to form stronger bonds (such as, for example, Si—O bonds) near the seams603of the dielectric layer601.

In step903, after performing the ultraviolet/oxygen treatment, a thermal treatment is performed on the dielectric layer601. In some embodiments, the thermal treatment may be a dry thermal treatment, a wet thermal treatment, a combination thereof, or the like. In some embodiments where the thermal treatment is a dry thermal treatment, the thermal treatment may be performed at a temperature between about 400° C. and about 700° C. for a duration between about 1 hr and about 2 hr. In some embodiments where the thermal treatment is a wet thermal treatment, the thermal treatment may be performed at a temperature between about 400° C. and about 700° C. for a duration between about 1 hr and about 2 hr. Furthermore, in some embodiments where the thermal treatment is a wet thermal treatment, the thermal treatment is performed in an ambient comprising water (H2O) vapor. In some embodiments, the water vapor may have a pressure between about 600 mmHg and about 1200 mmHg. In some embodiments, the thermal treatment densifies the dielectric layer601and facilitates strong bond (such as, for example, Si—O bonds) formation at the seams603of the dielectric layer601.

FIG.10is a flow diagram illustrating a dielectric gap-filling process1000in accordance with some embodiments. Referring toFIGS.10and6A, after performing the dielectric gap-filling process800illustrated above with reference toFIG.8, the dielectric gap-filling process1000continues to step1001, where an ultraviolet/oxygen treatment is performed on the dielectric layer601. In some embodiments, step1001is similar to step901of the dielectric gap-filling process900described above with reference toFIG.9and the description is not repeated herein. In step1003, after performing the ultraviolet/oxygen treatment, a thermal treatment is performed on the dielectric layer601. In some embodiments, step1003is similar to step903of the dielectric gap-filling process900described above with reference toFIG.9and the description is not repeated herein.

Referring toFIG.12A, a planarization process, such as a chemical mechanical polishing (CMP), may remove any excess portions of the dielectric layer601, the precursor soak layer501and the liner layer401, such that top surfaces of the dielectric layer601and top surfaces of the semiconductor strips303are coplanar. In some embodiments where portions of the mask203(seeFIG.6A) remain over the semiconductor strips303after forming the semiconductor strips303, the planarization process may also remove the remaining portions of the mask203.

FIG.13Aillustrates the recessing of the dielectric layer601, the precursor soak layer501and the liner layer401, such that remaining portions of the dielectric layer601, the precursor soak layer501and the liner layer401form isolation regions1301. The isolation regions1301may be also referred to as shallow trench isolation (STI) regions. The dielectric layer601, the precursor soak layer501and the liner layer401are recessed such that fins1303protrude from between neighboring isolation regions1301. Further, the top surfaces of the isolation regions1301may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the isolation regions1301may be formed flat, convex, and/or concave by an appropriate etch. The dielectric layer601, the precursor soak layer501and the liner layer401may be recessed using one or more acceptable etching processes.

A person having ordinary skill in the art will readily understand that the process described with respect toFIGS.2A-6A,12A and13Ais just one example of how the fins1303may be formed. In other embodiments, a dielectric layer can be formed over a top surface of the substrate201; trenches can be etched through the dielectric layer; homoepitaxial structures can be epitaxially grown in the trenches; and the dielectric layer can be recessed such that the homoepitaxial structures protrude from the dielectric layer to form fins. In yet other embodiments, heteroepitaxial structures can be used for the fins. For example, the semiconductor strips303inFIG.12Acan be recessed, and one or more materials different from the semiconductor strips303may be epitaxially grown in their place. In even further embodiments, a dielectric layer can be formed over a top surface of the substrate201; trenches can be etched through the dielectric layer; heteroepitaxial structures can be epitaxially grown in the trenches using one or more materials different from the substrate201; and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form fins1303.

In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the grown materials may be in situ doped during growth. In other embodiments, homoepitaxial or heteroepitaxial structures may be doped using, for example, ion implantation after homoepitaxial or heteroepitaxial structures are epitaxially grown. In various embodiments, the fins1303may comprise silicon germanium (SixGe1−x, where x can be between approximately 0 and 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming III-V compound semiconductor include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like.

Referring toFIGS.14A and14B, a dielectric layer1401is formed on sidewalls and top surfaces of the fins1303. In some embodiments, the dielectric layer1401may be also formed over the isolation regions1301. In other embodiments, top surfaces of the isolation regions1301may be free from the dielectric layer1401. The dielectric layer1401may comprise an oxide, such as silicon oxide, or the like, and may be deposited (using, for example, ALD, CVD, PVD, a combination thereof, or the like) or thermally grown (for example, using thermal oxidation, or the like) according to acceptable techniques. A gate electrode layer1403is formed over the dielectric layer1401, and a mask1405is formed over the gate electrode layer1403. In some embodiments, the gate electrode layer1403may be deposited over the dielectric layer1401and then planarized using, for example, a CMP process. The mask1405may be deposited over the gate electrode layer1403. The gate electrode layer1403may be made of, for example, polysilicon, although other materials that have a high etching selectivity with respect to the material of the isolation regions1301may also be used. The mask1405may include one or more layers of, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, a combination thereof, or the like, and may be formed using any suitable process, such as thermal oxidation, thermal nitridation, ALD, PVD, CVD, a combination thereof, or the like.

Referring toFIGS.15A,15B, and15C, the mask1405(seeFIGS.14A and14B) may be patterned using acceptable photolithography and etching techniques to form a patterned mask1501. The pattern of the patterned mask1501is transferred to the gate electrode layer1403by an acceptable etching technique to form gates1503. The gates1503cover respective channel regions of the fins1303(seeFIG.15B) while exposing source/drain regions of the fins1303(seeFIGS.15B and15C). The gates1503may also have a lengthwise direction substantially perpendicular to the lengthwise direction of respective fins1303, within process variations (seeFIG.15A). A size of the gates1503, and a pitch between the gates1503, may depend on a region of a die in which the gates1503are formed. In some embodiments, the gates1503may have a larger size and a larger pitch when located in, for example, an input/output region of a die (e.g., where input/output circuitry is disposed) than when located in, for example, a logic region of a die (e.g., where logic circuitry is disposed). As described below in greater detail, the gates1503are sacrificial gates and are subsequently replaced by replacement gates. Accordingly, the gates1503may also be referred to as sacrificial gates.

Referring further toFIGS.15A,15B, and15C, lightly doped source/drain (LDD) regions1505may be formed in the substrate201. Similar to the implantation process discussed above with reference toFIG.2A, appropriate impurities are implanted into the fins1303to form the LDD regions1505. In some embodiments where the FinFET device200is a p-type device, p-type impurities are implanted into the fins1303to form p-type LDD regions1505. In some embodiments where the FinFET device200is an n-type device, n-type impurities are implanted into the fins1303to form n-type LDD regions1505. During the implantation of the LDD regions1505, the gates1503and the patterned mask1501may act as a mask to prevent (or at least reduce) dopants from implanting into channel regions of the fins1303. Thus, the LDD regions1505may be formed substantially in source/drain regions of the fins1303. The n-type impurities may be any of the n-type impurities previously discussed, and the p-type impurities may be any of the p-type impurities previously discussed. The LDD regions1505may have a concentration of impurities between about 1020cm−3to about 1021cm−3. After the implantation process, an annealing process may be performed to activate the implanted impurities.

FIGS.16A-16C and17A-17Cillustrate the formation of spacers1701on sidewalls of the gates1503and sidewalls of the fins1303in accordance with some embodiments. Referring first toFIGS.16A,16B, and16C, a dielectric layer1601is blanket formed on exposed surfaces of the gates1503, the patterned mask1501, and the dielectric layer1401. In some embodiments, the dielectric layer1601may comprise silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon carboxynitride (SiOCN), a combination thereof, or the like, and may be formed using CVD, ALD, a combination thereof, or the like.

Referring next toFIGS.17A,17B, and17C, horizontal portions of the dielectric layer1601are removed, such that remaining vertical portions of the dielectric layer1601form spacers1701on the sidewalls of the gates1503and the sidewalls of the fins1303. In some embodiments, the horizontal portions of the dielectric layer1601may be removed using a suitable etching process, such as an anisotropic dry etching process.

Referring toFIGS.18A,18B, and18C, after forming the spacers1701, a patterning process is performed on the fins1303to form recesses1801in the source/drain regions of the fins1303. In some embodiments, the patterning process may include a suitable anisotropic dry etching process, while using the patterned mask1501, the gates1503, the spacers1701, and/or isolation regions1301as a combined mask. The suitable anisotropic dry etching process may include a reactive ion etch (RIE), a neutral beam etch (NBE), a combination thereof, or the like. In some embodiments, portions of the dielectric layer1401may be removed over the isolation regions1301during the patterning process.

Referring toFIGS.19A,19B, and19C, epitaxial source/drain regions1901are formed in the recesses1801(seeFIGS.18B and18C). In some embodiments, the epitaxial source/drain regions1901are epitaxially grown in the recesses1801using metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), a combination thereof, or the like. In some embodiments where the FinFET device200is an n-type device and the fins1303are formed of silicon, the epitaxial source/drain regions1901may include silicon, SiC, SiCP, SiP, or the like. In some embodiments where the FinFET device200is a p-type device and the fins1303are formed of silicon, the epitaxial source/drain regions1901may include SiGe, SiGeB, Ge, GeSn, or the like. The epitaxial source/drain regions1901may have surfaces raised from respective surfaces of the fins1303and may have facets. In some embodiments, the epitaxial source/drain regions1901may extend past the fins1303and into the semiconductor strips303. In some embodiments, the material of the epitaxial source/drain regions1901may be implanted with suitable dopants. In some embodiments, the implantation process is similar to the process used for forming the LLD regions1505as described above with reference toFIGS.15A,15B, and15C, and the description is not repeated herein. In other embodiments, the material of the epitaxial source/drain regions1901may be in situ doped during growth.

Referring further toFIGS.19A,19B, and19C, in the illustrated embodiment, each of the epitaxial source/drain regions1901are physically separated from other epitaxial source/drain regions1901. In other embodiments, adjacent epitaxial source/drain regions1901may be merged. Such an embodiment is depicted inFIG.20C, where adjacent epitaxial source/drain regions1901are merged to form a common epitaxial source/drain region1901.

Referring toFIGS.21A,21B and21C, a dielectric gap-filling process is performed to fill gaps between adjacent gates1503and gaps between adjacent epitaxial source/drain regions1901with one or more dielectric materials. The dielectric gap-filling process includes forming a conformal liner layer2101over the gates1503and the epitaxial source/drain regions1901, forming a precursor soak layer2103over the liner layer2101, and forming a dielectric layer2105over the precursor soak layer2103. In some embodiments, the liner layer2101may be formed using similar materials and methods as the liner layer401described above with reference toFIG.4Aand the description is repeated herein. In some embodiments, the precursor soak layer2103may be formed using similar materials and methods as the precursor soak layer501described above with reference toFIG.5Aand the description is repeated herein. In some embodiments, the dielectric layer2105is formed of a dielectric material such as silicon oxide, SiOC, ZrO2, HfO2, Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), undoped Silicate Glass (USG), low-k dielectric materials, extremely low-k dielectric materials, high-k dielectric materials, a combination thereof, or the like, and may be deposited by any suitable method, such as ALD, CVD, PECVD, a spin-on-glass process, a combination thereof, or the like. The dielectric layer2105may also be referred to as an interlayer dielectric (ILD) layer. In some embodiments, the liner layer2101is used as an etch stop layer while patterning the dielectric layer2105to form openings for subsequently formed contact plugs. Accordingly, a material for the liner layer2101may be chosen such that the material of the liner layer2101has a lower etch rate than the material of the dielectric layer2105.

In some embodiments, the dielectric gap-filling process for forming the liner layer2101, the precursor soak layer2103, and the dielectric layer2105may comprise the dielectric gap-filling process700described above with reference toFIG.7and the description is not repeated herein. In other embodiments, the dielectric gap-filling process for forming the liner layer2101, the precursor soak layer2103, and the dielectric layer2105may comprise the dielectric gap-filling process800described above with reference toFIG.8and the description is not repeated herein. In yet other embodiments, the dielectric gap-filling process for forming the liner layer2101, the precursor soak layer2103, and the dielectric layer2105may comprise the dielectric gap-filling process900described above with reference toFIG.9and the description is not repeated herein. In yet other embodiments, the dielectric gap-filling process for forming the liner layer2101, the precursor soak layer2103, and the dielectric layer2105may comprise the dielectric gap-filling process1000described above with reference toFIG.10and the description is not repeated herein. In some embodiments, a planarization process, such as a CMP process, may be performed to level the top surface of the dielectric layer2105with the top surfaces of the patterned mask1501.

Referring toFIGS.22A,22B and22C, the gates1503(seeFIGS.21A and21B) are removed to form recesses2201. In some embodiments, the gates1503may be removed using one or more suitable etching processes. Each of the recesses2201exposes a channel region of a respective fin1303. In some embodiments, the dielectric layer1401may be used as an etch stop layer when the gates1503are etched. In some embodiments, after removing the gate electrode layers1403of the gates1503, exposed portions of the dielectric layer1401may be also removed. In some embodiments, the exposed portions of the dielectric layer1401may remain in the recesses2201.

Referring toFIGS.23A,23B and23C, a gate dielectric layer2301and a gate electrode layer2303are formed in the recesses2201(seeFIGS.22A and22B). In some embodiments, the gate dielectric layer2301is conformally deposited in the recesses2201. In some embodiments, the gate dielectric layer2301comprises silicon oxide, silicon nitride, or multilayers thereof. In other embodiments, the gate dielectric layer2301includes a high-k dielectric material, and in these embodiments, the gate dielectric layer2301may have a k value greater than about 7.0, and may include a metal oxide or a silicate of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. The formation methods of the gate dielectric layer2301may include Molecular-Beam Deposition (MBD), ALD, PECVD, a combination thereof, or the like.

Referring further to23A,23B and23C, in some embodiments where the portions of the dielectric layer1401are not removed over the channel regions of the fins1303while forming the recesses2201(seeFIGS.22A and22B), the portions of the dielectric layer1401over the channel regions of the fins1303may act as interfacial layers between the gate dielectric layer2301and the channel regions of the fins1303. In some embodiments where the portions of the dielectric layer1401are removed over the channel regions of the fins1303while forming the recesses2201, one or more interfacial layers may be formed over the channel regions of the fins1303prior to forming the gate dielectric layer2301, and the gate dielectric layer2301is formed over the one or more interfacial layers. The interfacial layers help to buffer the subsequently formed high-k dielectric layer from the underlying semiconductor material. In some embodiments, the interfacial layers comprise a chemical silicon oxide, which may be formed of chemical reactions. For example, a chemical oxide may be formed using deionized water+ozone (O3), NH4OH+H2O2+H2O (APM), or other methods. Other embodiments may utilize a different material or processes (e.g., a thermal oxidation or a deposition process) for forming the interfacial layers.

Next, the gate electrode layer2303is deposited over the gate dielectric layer2301and fills the remaining portions of the recesses2201(seeFIGS.22A and22B). In some embodiments, the gate electrode layer2303may comprise one or more layers of suitable conductive materials. The gate electrode layer2303may comprise a metal selected from a group of W, Cu, Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, Co, Pd, Ni, Re, Ir, Ru, Pt, Zr, and combinations thereof. In some embodiments, the gate electrode layer2303may comprise a material selected from a group of TiN, WN, TaN, Ru, and combinations thereof. Metal alloys such as Ti—Al, Ru—Ta, Ru—Zr, Pt—Ti, Co—Ni and Ni—Ta may be used and/or metal nitrides such as WNx, TiNx, MONx, TaNx, and TaSixNymay be used. The gate electrode layer2303may be formed using a suitable process such as ALD, CVD, PVD, plating, combinations thereof, or the like. After filling the recesses2201with the gate electrode layer2303, a planarization process, such as a CMP process, may be performed to remove the excess portions of the gate dielectric layer2301and the gate electrode layer2303, which excess portions are over the top surface of the dielectric layer2105. The remaining portions of the gate electrode layer2303and the gate dielectric layer2301thus form replacement gates2305of the FinFET device200. In other embodiments, the gates1503(seeFIGS.21A and21B) may remain rather than being replaced by the replacement gates2305.

Referring toFIGS.24A,24B and24C, a dielectric layer2401is formed over the dielectric layer2105and the replacement gates2305. The dielectric layer2401may also be referred to as an interlayer dielectric (ILD) layer. In some embodiments, the dielectric layer2401may be formed using similar materials and methods as the dielectric layer2105described above with reference toFIGS.21A,21B and21C, and the description is not repeated herein. In some embodiments, the dielectric layer2105and the dielectric layer2401are formed of a same material. In other embodiments, the dielectric layer2105and the dielectric layer2401are formed of different materials. The liner layer2101, the precursor soak layer2103, and the dielectric layers2105and2401are patterned to form openings2403and2405. In some embodiments, the liner layer2101, the precursor soak layer2103, and the dielectric layers2105and2401may be patterned using one or more suitable etching processes, such as anisotropic dry etching process, or the like. The openings2403expose the respective replacement gates2305. The openings2405expose portions of the respective epitaxial source/drain regions1901.

Referring further toFIGS.24A,24B and24C, self-aligned silicide (salicide) layers2407are formed through the openings2405. In some embodiments, a metallic material is deposited in the openings2405. The metallic material may comprise Ti, Co, Ni, NiCo, Pt, NiPt, Ir, PtIr, Er, Yb, Pd, Rh, Nb, a combination thereof, or the like, and may be formed using PVD, sputtering, or the like. Subsequently, an annealing process is performed to form the salicide layers2407. In some embodiments where the epitaxial source/drain regions1901comprise silicon, the annealing process causes the metallic material to react with silicon to form a silicide of the metallic material.

Referring toFIGS.25A,25B and25C, contact plugs2501are formed in the openings2403(seeFIGS.24A and24B) and contact plug2503are formed in the opening2405(seeFIGS.24B and24C). In some embodiments, a liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are deposited in the openings2403and2405. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, a combination thereof, or the like. Subsequently, the openings2403and2405are filled with the conductive material. The conductive material may be copper, a copper alloy, silver, gold, tungsten, aluminum, nickel, a combination thereof, or the like. A planarization process, such as a CMP process, may be performed to remove excess materials from a top surface of the dielectric layer2401. The remaining portions of the liner and the conductive material form the contact plugs2501and2503. The contact plugs2501are physically and electrically coupled to the replacement gates2305. The contact plugs2503are physically and electrically coupled to the epitaxial source/drain regions1901through the salicide layers2407.

FIGS.26A,26B and26Care cross-sectional views of a FinFET device2600in accordance with some embodiments. To highlight differences between the FinFET device2600and the FinFET device200illustrated inFIGS.25A,25B and25C, the common features of these FinFET devices are labeled by same numerical references and their description is not repeated herein. In some embodiments, the FinFET device2600may be formed using a similar method as the FinFET device200, and the description is not repeated herein. In the illustrated embodiment, the formation of the precursor soak layer2103(seeFIGS.21A,21B, and21C) is omitted and the dielectric layer2105is formed directly on the liner layer2101.

FIGS.27A,27B and27Care cross-sectional views of a FinFET device2700in accordance with some embodiments. To highlight differences between the FinFET device2700and the FinFET device200illustrated inFIGS.25A,25B and25C, the common features of these FinFET devices are labeled by same numerical references and their description is not repeated herein. In some embodiments, the FinFET device2700may be formed using a similar method as the FinFET device200, and the description is not repeated herein. In the illustrated embodiment, the formation of the precursor soak layer501(seeFIG.5A) is omitted and the dielectric layer601is formed directly on the liner layer401.

FIG.28is a flow diagram illustrating a method2800of forming a FinFET device in accordance with some embodiments. The method2800starts with step2801, where trenches (such as, for example, the trenches301illustrated inFIG.3A) are formed in a substrate (such as, for example, the substrate201illustrated inFIG.3A) such that portions of the substrate between adjacent trenches form semiconductor strips (such as, for example, the semiconductor strips303illustrated inFIG.3A) as described above with reference toFIGS.2A and3A. In step2803, isolation regions (such as, for example, the isolation regions1301illustrated inFIG.13A) are formed in the trenches such that portions of the semiconductor strips extending above the isolation regions form the fins (such as, for example, the fins1303illustrated inFIG.13A) as described above with reference toFIGS.4A-6A,12A and13. In some embodiments, step2803may comprise performing the dielectric gap-filling process700described above with reference toFIG.7. In other embodiments, step2803may comprise performing the dielectric gap-filling process800described above with reference toFIG.8. In yet other embodiments, step2803may comprise performing the dielectric gap-filling process900described above with reference toFIG.9. In yet other embodiments, step2803may comprise performing the dielectric gap-filling process1000described above with reference toFIG.10. In step2805, sacrificial gates (such as, for example, the gates1503illustrated inFIGS.15A and15B) are formed along sidewalls and top surfaces of the fins as described above with reference toFIGS.14A,14B and15A-15C. In step2807, epitaxial source/drain regions (such as, for example, the epitaxial source/drain regions1901illustrated inFIGS.19B and19C) are formed in the fins as described above with reference toFIGS.18A-18C and19A-19C. In step2809, a first dielectric layer (such as, for example, the dielectric layer2105illustrated inFIGS.21B and21C) is formed between adjacent sacrificial gate structures as described above with reference toFIGS.21A-21C. In some embodiments, step2809may comprise performing the dielectric gap-filling process700described above with reference toFIG.7. In other embodiments, step2809may comprise performing the dielectric gap-filling process800described above with reference toFIG.8. In yet other embodiments, step2809may comprise performing the dielectric gap-filling process900described above with reference toFIG.9. In yet other embodiments, step2809may comprise performing the dielectric gap-filling process1000described above with reference toFIG.10. In step2811, the sacrificial gates are replaced with replacement gates (such as, for example, the replacement gates2305illustrated inFIGS.23A and23B) as described above with reference toFIGS.22A-22C and23A-23C. In step2813, a second dielectric layer (such as, for example, the dielectric layer2401illustrated inFIGS.24A-24C) is formed over the first dielectric layer and the replacement gates as described above with reference toFIGS.24A-24C. In step2815, gate contact plugs (such as, for example, the contact plugs2501illustrated inFIGS.25A-25C) and source/gate contact plugs (such as, for example, the contact plugs2503illustrated inFIGS.25A-25C) are formed as described above with reference toFIGS.24A-24C and25A-25C.

According to an embodiment, a method includes: forming a trench in a substrate; forming a liner layer along sidewalls and a bottom of the trench; forming a silicon-rich layer over the liner layer, where forming the silicon-rich layer includes: flowing a first silicon precursor into a process chamber for a first time interval; and flowing a second silicon precursor and a first oxygen precursor into the process chamber for a second time interval, the second time interval being different from the first time interval; and forming a dielectric layer over the silicon-rich layer. In an embodiment, forming the silicon-rich layer further includes: flowing a third silicon precursor into the process chamber for a third time interval; and flowing a fourth silicon precursor and a second oxygen precursor into the process chamber for a fourth time interval, the fourth time interval being different from the third time interval. In an embodiment, the first silicon precursor and the second silicon precursor includes a same chemical. In an embodiment, the method further includes performing an ultraviolet/oxygen treatment on the dielectric layer. In an embodiment, performing the ultraviolet/oxygen treatment on the dielectric layer includes subjecting the dielectric layer to an ultraviolet radiation in an oxygen ambient. In an embodiment, the method further includes, after preforming the ultraviolet/oxygen treatment, performing a thermal treatment on the dielectric layer.

According to another embodiment, a method includes: patterning a substrate to form trenches therein, portions of the substrate between adjacent trenches forming semiconductor strips; and forming isolation regions in the trenches, portions of the semiconductor strips extending above the isolation regions forming fins, wherein forming the isolation regions includes: conformally forming a first liner layer in the trenches; forming a first silicon-rich layer over the first liner layer, where forming the first silicon-rich layer includes: flowing a first silicon precursor into a process chamber for a first number of cycles; and flowing a second silicon precursor and a first oxygen precursor into the process chamber for a second number of cycles, the second number of cycles being different from the first number of cycles; and forming a first dielectric layer over the first silicon-rich layer. In an embodiment, forming the first silicon-rich layer further includes: flowing a third silicon precursor into the process chamber for a third number of cycles; and flowing a fourth silicon precursor and a second oxygen precursor into the process chamber for a fourth number of cycles, the fourth number of cycles being different from the third number of cycles. In an embodiment, conformally forming the first liner layer in the trenches includes depositing a dielectric material along sidewalls and bottoms of the trenches using an atomic layer deposition (ALD) process. In an embodiment, forming the first dielectric layer includes flowing a third silicon precursor, a second oxygen precursor, and an oxygen-containing plasma into the process chamber for a third number of cycles. In an embodiment, the method further includes: forming sacrificial gates along sidewalls and top surfaces of the fins; conformally forming a second liner layer over the sacrificial gates; forming a second silicon-rich layer over the second liner layer, where forming the second silicon-rich layer includes: flowing a third silicon precursor into the process chamber for a third number of cycles; and flowing a fourth silicon precursor and a second oxygen precursor into the process chamber for a fourth number of cycles, the fourth number of cycles being different from the third number of cycles; and forming a second dielectric layer over the second silicon-rich layer. In an embodiment, the method further includes: performing an ultraviolet/oxygen treatment on the first dielectric layer; and after preforming the ultraviolet/oxygen treatment, performing a thermal treatment on the first dielectric layer. In an embodiment, performing the ultraviolet/oxygen treatment on the first dielectric layer includes subjecting the first dielectric layer to an ultraviolet radiation in an oxygen ambient.

According to yet another embodiment, a method includes: forming isolation regions in a substrate, portion of the substrate extending between and over adjacent isolation regions forming fins; forming sacrificial gates along sidewalls and top surfaces of the fins; forming a first liner layer along sidewalls and over top surfaces of the sacrificial gates; forming a first silicon-rich layer over the first liner layer, where forming the first silicon-rich layer includes: flowing a first silicon precursor into a process chamber for a first number of cycles; and flowing a second silicon precursor and a first oxygen precursor into the process chamber for a second number of cycles, the second number of cycles being different from the first number of cycles; and forming a first dielectric layer over the first silicon-rich layer. In an embodiment, forming the first silicon-rich layer further includes: flowing a third silicon precursor into the process chamber for a third number of cycles; and flowing a fourth silicon precursor and a second oxygen precursor into the process chamber for a fourth number of cycles, the fourth number of cycles being different from the third number of cycles. In an embodiment, forming the isolation regions includes: patterning the substrate to form trenches in the substrate; conformally forming a second liner layer in the trenches; forming a second silicon-rich layer over the second liner layer, where forming the second silicon-rich layer includes: flowing a third silicon precursor into the process chamber for a third number of cycles; and flowing a fourth silicon precursor and a second oxygen precursor into the process chamber for a fourth number of cycles, the fourth number of cycles being different from the third number of cycles; and forming a second dielectric layer over the second silicon-rich layer. In an embodiment, forming the first dielectric layer includes flowing a third silicon precursor, a second oxygen precursor, and an oxygen-containing plasma into the process chamber for a third number of cycles. In an embodiment, the method further includes performing an ultraviolet/oxygen treatment on the first dielectric layer. In an embodiment, the method further includes, after preforming the ultraviolet/oxygen treatment, performing a thermal treatment on the first dielectric layer. In an embodiment, the first silicon precursor and the second silicon precursor include a same chemical.

According to yet another embodiment, A device includes: a semiconductor strip supported by a substrate; a gate structure along sidewalls and a top surface of the semiconductor strip; a source/drain region adjacent the gate structure and extending into the semiconductor strip; a first liner extending along a sidewall of the gate structure and a top surface of the source/drain region; a first silicon-rich layer over the first liner; and a first dielectric layer over the first silicon-rich layer.

According to yet another embodiment, a device includes: a substrate; a semiconductor strip extending from the substrate; an isolation region over the substrate and adjacent the semiconductor strip; a gate structure over the semiconductor strip; a first liner extending along a sidewall of the gate structure and a top surface of the isolation region; a first silicon-rich layer over the first liner; and a first dielectric layer over the first silicon-rich layer.

According to yet another embodiment, a device includes: a substrate; a semiconductor strip extending away from a first surface of the substrate; an isolation region over the substrate and adjacent the semiconductor strip, the isolation region includes: a first liner extending along a sidewall of the semiconductor strip and the first surface of the substrate; a first silicon-rich layer over the first liner; and a first dielectric layer over the first silicon-rich layer; a gate structure over the semiconductor strip; a second liner extending along a sidewall of the gate structure and a top surface of the isolation region; a second silicon-rich layer over the second liner; and a second dielectric layer over the second silicon-rich layer.

The fins may be formed by any suitable method. For example, the fins may be formed using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.