Patent ID: 12238929

DETAILED DESCRIPTION

In general, according to one embodiment, a memory device includes a first conductor and a charge storage film extending along a first direction crossing a surface of a substrate; a first semiconductor of a first conductive type; a second semiconductor and a third semiconductor each of a second conductive type; and a first stack comprising a second conductor, a first insulator, and a third conductor sequentially stacked along the first direction and each extending along a second direction in a first plane parallel to the surface of the substrate. The first conductor, the charge storage film, the first semiconductor, and the first stack are above the substrate and arranged in this order along a third direction crossing the second direction in the first plane. The second semiconductor is in contact with the first semiconductor and the second conductor, between the second conductor or the first insulator and the charge storage film. The third semiconductor is in contact with the first semiconductor and the third conductor, between the third conductor or the first insulator and the charge storage film.

The embodiments will now be described with reference to the drawings. Each embodiment will exemplify devices and methods for embodying the technical idea of the invention. The drawings are schematic or conceptual, and it is not a requisite that the dimensions, scales, etc., read from each drawing conform to actual products. The technical idea of the invention is not bound by particular component shapes, structures, arrangements, etc.

The description will use the same reference signs for the features or components having the same or substantially the same functions and/or configurations. Numerals may be added after reference sign-constituting characters in order to differentiate between elements that are denoted by a reference sign of the same characters and that have substantially the same configurations. When it is not required to differentiate between elements denoted by a reference sign of the same characters, the description will basically refer to each of such elements using only the reference sign of the same characters.

Also, the description may occasionally assume a size or a diameter of a layer, which may be taken as an average outer size or an average outer diameter of cross-sections of the layer that are parallel to the plane of lamination of the layer. When the description assumes a center of a cross-section of a layer, such a center may be taken as a gravity center of the cross-section.

1. First Embodiment

A memory device according to the first embodiment will be described.

1.1. Configuration

First, a description will be given of a configuration of the memory device according to the first embodiment.

1.1.1 Memory Device

FIG.1is a block diagram for explaining a configuration of a memory system that embraces the memory device according to the first embodiment.

As shown inFIG.1, a memory system1includes a memory device100as the memory device according to the embodiment, and a memory controller200adapted to control the memory device100. The memory device100includes a NOR flash memory which is capable of storing data in a non-volatile manner. The memory system1is connected to, for example, a host device (not illustrated) such as a processor.

The memory controller200directs the memory device100for operations such as write, read, and erase of data. At the time of performing such operations, the memory controller200generates a command CMD corresponding to the respective operation and sends the command CMD to the memory device100together with an address ADD of a target of the operation. For example, in a write operation, the memory controller200sends a command CMD for the write operation, an address ADD of the write target, and also data DT to be written (write data DT), to the memory device100. In a read operation, the memory controller200sends a command CMD for the read operation and an address ADD of the read target to the memory device100, and receives from the memory device100data DT that has been read (read data DT) there. The memory controller200also communicates control signals CNT with the memory device100.

The memory device100includes, for example, a memory cell array10, an input/output circuit (I/O circuit)11, a row control circuit12, a column control circuit13, a sense amplifier circuit14, a voltage generation circuit15, and a sequencer16.

The memory cell array10includes multiple memory cell transistors MT each uniquely associated with a set of a row and a column. More specifically, the memory cell transistors MT in the same row are coupled to the same (global) word line WL, and the memory cell transistors MT in the same column are coupled to the same (global) bit line BL and source line SL which form a pair. The memory cell array10has a three-dimensional structure in which the multiple memory cell transistors MT are stacked in a direction perpendicular to the surface of a substrate.

The input/output circuit11receives a command CMD, an address ADD, data DT, and a control signal CNT from the memory controller200, and transfers them to the sequencer16. Also, the input/output circuit11receives data DT and a control signal NCT from the sequencer16, and sends them to the memory controller200.

The row control circuit12includes, for example, a row decoder (not illustrated), word line drivers121, etc., and controls voltage application to the word lines WL based on the result of decoding the address ADD (row address). In an exemplary configuration, the word line drivers121are provided individually for the respective word lines WL.

The column control circuit13includes, for example, bit line drivers131, source line drivers (not illustrated), a column decoder (not illustrated), etc., and controls voltage application to the bit lines BL and the source lines SL based on the result of decoding the address ADD (column address). In an exemplary configuration, the bit line drivers131and the source line drivers are provided individually for the respective bit lines BL and the respective source lines SL. The source line drivers may be omitted when a configuration is adopted where the intended operations are performed with the source lines SL placed in a floating state.

The sense amplifier circuit14, in read operations, senses a threshold voltage of the memory cell transistor MT to read data from the memory cell transistor MT based on the result of this sensing. The sense amplifier circuit14is also adapted so that it can supply given voltages to the bit lines BL and the source lines SL in the course of, for example, a write operation and an erase operation.

The voltage generation circuit15generates voltages of various values according to operations to be performed, and feeds them to the row control circuit12, the column control circuit13, and the sense amplifier circuit14.

The sequencer16performs total control over the operations of the memory device100. In an exemplary configuration, the sequencer16includes a command decoder and a register circuit (both unillustrated), and controls each of the applicable circuits11to15based on the result of decoding a command CMD so that an operation according to the command CMD is performed. The sequencer16also controls, based on a control signal CNT, the operational timing for each of the circuits11to15and the timing to transfer the signals between the memory device100and the memory controller200.

1.1.2 Circuit Configuration of Memory Cell Array

FIG.2is a circuit diagram, which is used as one example for explaining a configuration of the memory cell array of the memory device according to the first embodiment.

In the memory cell array10as shown inFIG.2, multiple memory cell transistors MT are provided as well as multiple word lines WL (which may be called “global word lines GWL” below), multiple bit lines BL, and multiple source lines SL. The multiple global word lines GWL are each connected with multiple local word lines LWL. The multiple global word lines GWL each receive a voltage supply from the corresponding word line driver121, and the multiple bit lines BL each receive a voltage supply from the corresponding bit line driver131. One memory cell transistor MT is uniquely specified by a set that is constituted by a column-associated bit line BL and source line SL pair and a row-associated global word line GWL.

More specifically, multiple memory cell transistors MT associated with the same column are connected in parallel with each other between a given bit line BL and a given source line SL. These memory cell transistors MT associated with the same column are associated with different rows, respectively. In other words, the multiple memory cell transistors MT connected in parallel with each other between the pair of a bit line BL and a source line SL have their gates connected to different global word lines GWL via different local word lines LWL, respectively.

Each of the multiple global word lines GWL has common connections to the gates of the respective memory cell transistors MT associated with the same row. These memory cell transistors MT associated with the same row are associated with different columns, respectively. In other words, the multiple memory cell transistors MT having their respective gates connected to one common global word line GWL are each connected between the respective pair of a bit line BL and a source line SL that differ from the pairs of bit lines and source lines for the other memory cell transistors MT.

Note that, as mentioned above, the memory cell array10according to the embodiment has a three-dimensional stacking structure in which the memory cell transistors MT are provided in different layers along the direction crossing the surface of the substrate (Z direction).FIG.2shows an exemplary instance where n layers (n being a natural number) for the memory cell transistors MT are stacked in the Z direction as a partial circuit configuration of the memory cell array10.

In this instance, one local word line LWL has common connections to, in each layer, the gates of two respective memory cell transistors MT among the multiple memory cell transistors MT associated with the same row, and thus, to the gates of 2n respective memory cell transistors MT in total among the multiple memory cell transistors MT associated with the same row. For the sake of explanation, the description herein refers to the two memory cell transistors MT having their gates connected to a common local word line LWL in the same layer as “MTa” and “MTb”, on an as-needed basis for differentiation. According to the instance shown inFIG.2, the multiple memory cell transistors MT connected between a given pair of a bit line BL and a source line SL are provided in such a manner that the memory cell transistors MTa and MTb are alternately arranged along the sequence of rows. Also, the description will refer to, among the2nmemory cell transistors MT having their gates connected to a common local word line LWL, the group of n memory cell transistors MTa as a “string NSa” and the group of n memory cell transistors MTb as a “string NSb”.

The above configuration allows for the selection of a single memory cell transistor MT through the selection of one global word line GWL and one pair of a bit line BL and a source line SL.

1.1.3 Structure of Memory Cell Array

An exemplary structure of the memory cell array of the memory device according to the first embodiment will be described.

Note that, in the drawings which will be referred to below, the plane along the surface of a semiconductor substrate is assumed to be an X-Y plane, and the direction crossing the X-Y plane conforms to the Z direction. It is also assumed that the directions crossing each other in the X-Y plane conform to the X direction and the Y direction. The plan views use hatching as appropriate for better viewability. Hatching in the plan views is not necessarily related to materials or properties of the hatched subjects or components. The sectional views omit components such as insulators (interlayer insulating films), interconnects, contacts, etc., as appropriate for easier understanding.

FIG.3is a plan view for explaining a planar layout of the memory cell array of the memory device according to the first embodiment.FIG.3schematically shows, as one example, a region of the memory cell array10viewed from above, where the memory cell transistors MT are formed beneath (i.e., a cell region).

As shown inFIG.3, the memory cell array10includes, for example, multiple stacks STK, multiple structures MP, multiple contacts CP, and multiple global word lines GWL.

The multiple stacks STK extend along the Y direction and are arranged along the X direction.

The multiple structures MP, each having a rectangular profile when viewed from above, are arranged along the Y direction between two stacks STK next to each other. The structure MP includes a local word line LWL (not illustrated) and is electrically connected to the corresponding global word line GWL via the respective contact CP. The multiple global word lines GWL each extend along the X direction and have a common connection to the multiple local word lines LWL corresponding to the respective structures MP arranged along the X direction. The multiple structures MP, arranged between two stacks STK, are mutually separated from one another by intervening insulating structures INS. A region of contact between the structure MP and the stack STK is a portion functioning as a string NS. Note that the example shown inFIG.3assumes the contacting portion between one structure MP and its left-sided stack STK to be the string NSa, and the contacting portion between one structure MP and its right-sided stack STK to be the string NSb.

WhileFIG.3illustrates an exemplary staggered arrangement pattern for the structures MP, the arrangement of the structures MP is not limited to this, and may adopt a matrix pattern, etc.

FIG.4shows an exemplary sectional structure of the memory cell array10shown inFIG.3, assuming that the array is cut along the line IV-IV. That is,FIG.4illustrates, in section, four stacks STK arranged along the X direction, two structures INS and one structure MP each provided between applicable ones of these stacks STK, and the contact CP and the global word line GWL connected to the local word line LWL in the structure MP. By way of example,FIG.4shows the memory cell array10of a case where four layers each as a structural portion for the memory cell transistors MT are stacked along the Z direction.

As shown inFIG.4, the memory cell array10is provided above a semiconductor substrate20via an insulator (not illustrated). There are, for example, the row control circuit12, the column control circuit13, and the sense amplifier circuit14disposed within the insulator between the semiconductor substrate20and the memory cell array10.

Concretely, in the memory cell array10shown inFIG.4, the stack STK, the structure INS, the stack STK, the structure MP, the stack STK, the structure INS, and the stack STK are arranged in this order along the X direction. The multiple stacks STK arranged along the X direction have equivalent structures.

The stack STK includes a stacking structure constituted by conductors21and22alternately stacked with an intervening insulator (not illustrated) as many times as the number of memory cell transistors MT stacked in the Z direction (4 times in the example shown inFIG.4). As discussed above, the multiple stacks STK arranged along the X direction are separated from each other by the structure INS or MP. As such, the multiple sets of conductors21and22arranged along the X direction in the same layer, as well as the multiple sets of conductors21and22arranged along the Z direction in different layers, can each be subjected to individual control for electrical potential, independent of other sets, and each correspond to one of the multiple bit line BL and source line SL pairs associated with different columns. The conductors21and22may contain, for example, a metal such as tungsten (W), molybdenum (Mo), or the like, and may be covered by a barrier metal such as titanium nitride (TiN), tungsten nitride (WN), or the like.

The structure MP extends along the Z direction from the height (level) comparable with the lower end of the stack STK to the height comparable with the upper end of the stack STK. Specifically, the structure MP includes a conductor30which serves as the local word line LWL, and a tunnel insulating film33, a charge storage film32, and a block insulating film31which together serve as a lamination film TCB.

The conductor30is provided at the substantial center of the structure MP and includes, for example, a portion of a rectangular prism shape that extends along the Z direction. The upper end of the conductor30reaches the upper end of the structure MP, and the lower end of the conductor30is below the upper surface of the lowermost conductor21. The conductor30may contain, for example, a metal such as tungsten, molybdenum, or the like, and may be covered by a barrier metal such as titanium nitride, tungsten nitride, or the like.

The four side surfaces and lower surface of the conductor30are wholly covered by the block insulating film31, the charge storage film32, and the tunnel insulating film33disposed in this order. Accordingly, the lamination film TCB has four side surfaces extending along the Z direction. Also, the lamination film TCB for the multiple memory cell transistors MTa formed in different layers within one structure MP, and the lamination film TCB for the multiple memory cell transistors MTb formed similarly within the same structure MP are constituted by one continuous film. The tunnel insulating film33contains, for example, silicon oxide (SiO2), and the charge storage film32contains, for example, silicon nitride (SiN). The block insulating film31includes a film of a high dielectric (high-k) substance such as silicon oxide, alumina, etc., or may be a lamination of such films.

The conductor30, on its upper surface, is provided with a conductor23which serves as the contact CP. There is a conductor24serving as the global word line GWL on an upper surface of the conductor23.

The structure INS includes an insulator25. The insulator25contains, for example, silicon oxide and extends along the Z direction from the height comparable with the lower end of the stack STK to the height comparable with the upper end of the stack STK.

There are semiconductors34and35extending along the Y direction and arranged along the X direction with an intervening insulator (not illustrated), between the conductors21and22in each layer within the stack STK. The semiconductors34and35each contact the multiple structures MP which are arranged along the Y direction and the multiple structures INS which are arranged along the Y direction as well.

The semiconductors34and35include, for example, polysilicon containing a p-type impurity (dopant) such as boron (B). The semiconductor34has a portion34ain contact with the left portion of the structure MP (according to the illustration), and this portion34afunctions as a channel of the memory cell transistor MTa. The semiconductor35has a portion35bin contact with the right portion of the structure MP (according to the illustration), and this portion35bfunctions as a channel of the memory cell transistor MTb. For the sake of explanation, the description will refer to one of the semiconductors34and35that is in contact with the left portion of the structure MP or the structure INS (according to the illustration) as the “semiconductor34”, and the one that is in contact with the right portion of the structure MP or the structure INS (according to the illustration) as the “semiconductor35”.

In each layer within the stack STK, a semiconductor36contacting the semiconductor34and the conductor21, and a semiconductor37contacting the semiconductor35and the conductor21are provided between the structure MP or the structure INS and the conductor21. Also, a semiconductor38contacting the semiconductor34and the conductor22, and a semiconductor39contacting the semiconductor35and the conductor22are provided between the structure MP or the structure INS and the conductor22. The semiconductors36to39extend along the Y direction and include, for example, polysilicon containing an n-type impurity such as phosphorus (P), arsenic (As), etc. The semiconductor36has a portion36ain contact with the semiconductor34a, and the semiconductor38has a portion38ain contact with the semiconductor34a. These portions36aand38aeach function as a source or a drain of the memory cell transistor MTa. The semiconductor37has a portion37bin contact with the semiconductor35b, and the semiconductor39has a portion39bin contact with the semiconductor35b. These portions37band39beach function as a source or a drain of the memory cell transistor MTb.

According to such constitution, the semiconductors34a,36a, and38a, the portion of the lamination film TCB that is proximate to the semiconductor34a, and the conductors21,22, and30together form one memory cell transistor MTa. Also, the semiconductors35b,37b, and39b, the portion of the lamination film TCB that is proximate to the semiconductor35b, and the conductors21,22, and30together form one memory cell transistor MTb. Here, the memory cell transistors MTa and MTb, formed in the four respective layers for one structure MP as described above (in the example shown inFIG.4, four memory cell transistors MTa and four memory cell transistors MTb), constitute one string NSa and one string NSb as the respective groups.

1.2 Method for Producing Memory Device

An example of a process for producing the memory cell array of the memory device according to the first embodiment will be described.FIGS.5to16each show an example of a sectional structure that includes a structural part corresponding to the memory cell array and that is formed in the course of the process for producing the memory device according to the first embodiment. Note that the sectional views which will be referred to for the production process include a cross-section vertical to the surface of the semiconductor substrate20. Also, regions indicated in each sectional view for the production process step correspond to the regions indicated inFIGS.3and4.

First, as shown inFIG.5, a structure that will become the multiple stacks STK is formed.

More specifically, the process begins with forming an insulator40on the semiconductor substrate20, and thereafter stacking on this insulator40an insulator41, a sacrificial member42, an insulator43, and a sacrificial member44in this order. Stacking this set of the insulator41, the sacrificial member42, the insulator43, and the sacrificial member44is repeated as many times as the number of layers (in this example, 4 times). The insulator41contains, for example, silicon oxide added with carbon (C), and the insulator43contains, for example, silicon oxide. With the carbon additive, the insulator41can have a smaller etching rate than the insulator43without a carbon additive, in the selective etching operations for oxides. The sacrificial members42and44contain, for example, silicon nitride. The insulator41, the sacrificial member42, the insulator43, and the sacrificial member44may each have a thickness of, for example, 10 to 100 nanometers (nm). The film formation in this process step may use, for example, plasma chemical vapor deposition (PCVD).

Next, as shown inFIG.6, each region intended for forming the structure MP or INS is removed from the structure that has been formed on the insulator40, so as to form multiple slits SLT. More specifically, a lithography operation is performed first to form a mask with open regions each corresponding to the structure MP or INS. Anisotropic etching is performed using the formed mask so that the multiple slits SLT are formed. The lower end of each slit SLT reaches, for example, the insulator40. The anisotropic etching in this process step may be, for example, reactive ion etching (RIE).

FIG.7is a sectional view of the memory cell array10, taken along the line VII-VII indicated inFIG.6. As shown inFIG.7, the process step has formed a line-and-space shape in which the portion corresponding to the stack STK and including the insulator43, and the slit SLT are alternately arranged along the X direction. Thus, the structure formed in the process step ofFIG.5is divided into multiple separate portions along the X direction.

Next, as shown inFIG.8, semiconductors34and35are formed for each layer in each slit SLT.

More specifically, portions of the insulator43that are exposed in the slit SLT are selectively removed by wet etching. Since the insulator41has a smaller etching rate than the insulator43as discussed above, the etching in this process step forms recesses at the heights of the insulators43in the slit SLT, such that in each recess, the upper surface of the sacrificial member42and the lower surface of the sacrificial member44are exposed along the X direction. The recesses each have a depth of, for example, about 10 nanometers (nm).

Subsequently, a semiconductor film (amorphous silicon or polysilicon) containing a p-type impurity is formed over the entire surface to fill the recesses. The film formation in this process step may use, for example, low-pressure (LP) CVD. This semiconductor film is then dry-etched in an anisotropic manner until the stacked members other than the insulator43are exposed in the slit SLT. The semiconductors34and35are thus formed in the recesses formed for each layer in the multiple slits SLT. Note that if the semiconductor film adopts amorphous silicon, the semiconductors34and35may be turned to polysilicon as their final form by a later heat treatment step.

FIG.9is a sectional view of the memory cell array10, taken along the line IX-IX indicated inFIG.8. As shown inFIG.9, the process step has formed the semiconductors34and35extending along the Y direction in each slit SLT and covering the insulator43.

Next, as shown inFIG.10, multiple structures INS are formed in the respective slits SLT. More specifically, an insulating film is provided over the entire surface to fill the multiple slits SLT. The film formation in this process step may use, for example, PCVD or LPCVD. Chemical mechanical polishing (CMP) is then performed for overall flatness, and an operation thereafter (for example, a combination of lithography and anisotropic etching) removes the portions corresponding to the regions for forming the structures MP from the insulating film. The insulators25corresponding to the structures INS are thus formed.

FIG.11is a sectional view of the memory cell array10, taken along the line XI-XI indicated inFIG.10. As shown inFIG.11, the process step has formed multiple holes STH along the Y direction and separated from one another by the applicable insulators25, between the stack structures each including the insulator43.

Next, as shown inFIG.12, a structure MP is formed in each of the holes STH. More specifically, a tunnel insulating film33, a charge storage film32, and a block insulating film31are formed in this order in each hole STH. The film formation in this process step may use, for example, LPCVD, and the films31to33each have a thickness of about several nanometers (nm). A conductor30is subsequently formed in each hole STH. The film formation in this process step may use, for example, LPCVD or PCVD.

FIG.13is a sectional view of the memory cell array10, taken along the line XIII-XIII indicated inFIG.12. As shown inFIG.13, the process step has formed one structure MP in each hole STH. One semiconductor34extending along the Y direction contacts each of the multiple structures MP arranged along the Y direction via the respective portion34a, and one semiconductor35extending along the Y direction contacts each of the multiple structures MP arranged along the Y direction via the respective portion35b.

Next, as can be seen fromFIG.14, one or more holes (not illustrated) penetrating through all the sacrificial members42and44stacked along the Z direction are formed to expose the sacrificial members42and44. The sacrificial members42and44are then selectively removed by wet etching or dry etching via the holes. This exposes both ends of the semiconductors34and35in the Z direction.

Next, as shown inFIG.15, the exposed portions of the semiconductors34and35are subjected to selective growth of n-type impurity-containing polysilicon. This forms semiconductors36(36a) and38(38a) covering the respective lower and upper ends of the semiconductor34(34a) in the Z direction, and semiconductors37(37b) and39(39b) covering the respective lower and upper ends of the semiconductor35(35b) in the Z direction. The selective growth in this process step may use, for example, LPCVD.

The semiconductors36to39contain, for example, an n-type impurity at a high concentration of 1E20/cm3or more, and each have a thickness of several nanometers to several tens of nanometers. Since the semiconductors36and38selectively grow on the semiconductor34, and the semiconductors37and39selectively grow on the semiconductor35as described above, they can be formed so that the semiconductors36and38are separate from each other and the semiconductors37and39are separate from each other.

Next, as shown inFIG.16, the conductors21are formed in the spaces created by the removal of the sacrificial members42, and the conductors22are formed in the spaces created by the removal of the sacrificial members44. The film formation in this process step may use, for example, LPCVD or PCVD.

By the process steps described above, the multiple, three-dimensionally stacked memory cell transistors MTa and MTb are formed. Thereafter, a step of forming conductors23and24, a step of forming contacts to the conductors21and22and to various circuitry components formed in the insulator40, a heat treatment step, etc. are performed so that the memory cell array10is formed.

Note that the production process described above is only an example. It is possible to adopt modifications such as inserting other processes between the process steps and changing the order of the steps as long as a problem does not occur.

1.3 Effects of Embodiment

According to the configuration of the first embodiment, effects including suppression of increase in size of the memory cell array can be obtained. These effects will be described.

For a stack STK to be formed, four members, i.e., the insulator41, the sacrificial member42corresponding to the conductor21, the insulator43, and the sacrificial member44corresponding to the conductor22, are stacked along the Z direction for each layer. The semiconductors34and35each functioning as a channel of a memory cell transistor MT are formed by removing portions of the insulator43along the X direction. The semiconductors36and37, and also the semiconductors38and39, each functioning as a source or a drain of a memory cell transistor MT are formed by the selective growth that is caused through the spaces created by the removal of the sacrificial members42and44and from the respective semiconductors34and35exposed in these spaces.

Accordingly, when the insulator41, the sacrificial member42, the insulator43, and the sacrificial member44are stacked, it is not necessary to dispose film members corresponding to the semiconductors36and37between the sacrificial member42and the insulator43, and it is not necessary to dispose film members corresponding to the semiconductors38and39between the sacrificial member44and the insulator43, either. This allows the number of different-material members stacked for each layer to be reduced from 6 to 4, and the increase in load of the production process steps can be suppressed. Together, more layers can be provided in the memory cell array with a reduced processing-conversion difference for the production process steps, and therefore, increase in size of the memory cell array can be suppressed.

1.4 Modifications

The foregoing first embodiment tolerates various modifications. The description will basically concentrate on aspects of the configuration and the production process that differ from the first embodiment.

1.4.1 First Modification

The first embodiment has assumed the instances where the semiconductors36to39are formed by causing n-type impurity-containing semiconductor films to selectively grow on the semiconductors34and35, but this is not a limitation. For example, each n-type impurity-containing semiconductor film may be formed as a continuous film on the inner walls that define the space after the removal of the sacrificial member42or44.

FIG.17is one example of a sectional structure that includes a structural part corresponding to the memory cell array and that is formed in the course of the process for producing the memory device according to the first modification of the first embodiment.FIG.17corresponds to the first embodiment shown inFIG.15.

As shown inFIG.17, a semiconductor36′ is formed on the inner walls that define the space after the removal of the sacrificial member42, and a semiconductor38′ is formed on the inner walls that define the space after the removal of the sacrificial member44. The film formation in this process step may use, for example, LPCVD.

The semiconductors36′ and38′ contain, for example, amorphous silicon or polysilicon that contains an n-type impurity at a high concentration of 1E20/cm3or more, and each have a thickness of several nanometers to several tens of nanometers. Since the semiconductors36′ and38′ are each formed as a continuous film on the inner walls that surround the space after the removal of the sacrificial member42or44as described above, the formed semiconductors36′ and38′ each have a tubular profile when viewed in the Y direction. The semiconductor36′ contacts the lower ends of the corresponding semiconductors34and35, and the semiconductor38′ contacts the upper ends of the corresponding semiconductors34and35. The semiconductors36′ and38′ contact the side surfaces of the corresponding conductors21and22, respectively.

Accordingly, a portion36a′ of the semiconductor36′, which is in contact with the semiconductor34a, and a portion38a′ of the semiconductor38′, which is in contact with the semiconductor34a, each function as a source or a drain of the memory cell transistor MTa. A portion36b′ of the semiconductor36′, which is in contact with the semiconductor35b, and a portion38b′ of the semiconductor38′, which is in contact with the semiconductor35b, each function as a source or a drain of the memory cell transistor MTb.

According to the first modification of the first embodiment, the semiconductors36′ and38′ are formed on the inner walls surrounding the spaces created by the removal of the respective sacrificial members42and44, and such film formation is uniformly done by, for example, LPCVD. Subsequently, the spaces inside the semiconductors36′ and38′ are filled with the conductors21and22, respectively.

Therefore, as in the first embodiment, when the insulator41, the sacrificial member42, the insulator43, and the sacrificial member44are stacked, it is not necessary to dispose film members corresponding to the semiconductor36′ between the sacrificial member42and the insulator43, and it is not necessary to dispose film members corresponding to the semiconductor38′ between the sacrificial member44and the insulator43, either. This allows the number of different-material members stacked for each layer to be reduced from 6 to 4, and the increase in load of the production process steps can be suppressed. Together, more layers can be provided in the memory cell array with a reduced processing-conversion difference for the production process steps, and therefore, increase in size of the memory cell array can be suppressed.

1.4.2 Second Modification

The foregoing first embodiment and its first modification have assumed the instances where n-type impurity-containing semiconductor films are formed in the spaces created by the removal of the sacrificial members42and44, but this is not a limitation. For example, n-type impurity-containing semiconductor films may be formed by doping portions of the semiconductors34and35with n-type impurities.

FIG.18is one example of a sectional structure that includes a structural part corresponding to the memory cell array and that is formed in the course of the process for producing the memory device according to the second modification of the first embodiment.FIG.18corresponds to the first embodiment shown inFIG.15.

In the example shown inFIG.18, vapor-phase diffusion is conducted to cause n-type impurities to diffuse into the lower end regions of the semiconductors34and35which are exposed in the spaces created by the removal of the sacrificial member42, and into the upper end regions of the semiconductors34and35which are exposed in the spaces created by the removal of the sacrificial member44. The diffusion of the n-type impurities takes place in the range of, for example, several nanometers (nm) to 20 nanometers (nm) from the upper and lower ends of each of the semiconductors34and35. Consequently, a lower portion36a″ of the semiconductor34, which is in contact with the semiconductor34aand the conductor21, and an upper portion38a″ of the semiconductor34, which is in contact with the semiconductor34aand the conductor22, are provided between the insulator43and the lamination film TCB. These portions36a″ and38a″ contain more n-type impurities than p-type impurities, and each function as a source or a drain of the memory cell transistor MTa. Similarly, a lower portion37b″ of the semiconductor35, which is in contact with the semiconductor35band the conductor21, and an upper portion39b″ of the semiconductor35, which is in contact with the semiconductor35band the conductor22, are provided between the insulator43and the lamination film TCB. These portions37b″ and39b″ contain more n-type impurities than p-type impurities, and each function as a source or a drain of the memory cell transistor MTb.

According to the second modification of the first embodiment, the semiconductors36″ and37″ are formed by the vapor-phase diffusion of n-type impurities into the semiconductors34and35exposed in the spaces after the removal of the sacrificial member42, and the semiconductors38″ and39″ are formed by the vapor-phase diffusion of n-type impurities into the semiconductors34and35exposed in the spaces after the removal of the sacrificial member44. Subsequently, the spaces after the removal of the sacrificial members42and44are filled with the conductors21and22, respectively.

Therefore, as in the first embodiment, when the insulator41, the sacrificial member42, the insulator43, and the sacrificial member44are stacked, it is not necessary to dispose film members corresponding to the semiconductors36″ and37″ between the sacrificial member42and the insulator43, and it is not necessary to dispose film members corresponding to the semiconductors38″ and39″ between the sacrificial member44and the insulator43, either. This allows the number of different-material members stacked for each layer to be reduced from 6 to 4, and the increase in load of the production process steps can be suppressed. Together, more layers can be provided in the memory cell array with a reduced processing-conversion difference for the production process steps, and therefore, increase in size of the memory cell array can be suppressed.

2. Second Embodiment

Next, a memory device according to the second embodiment will be described. The first embodiment has assumed the instances where the p-type impurity-containing semiconductors34and35are formed separately from each other between the two structures (MP or INS). The second embodiment differs from the first embodiment in that a p-type impurity-containing semiconductor provided between the two structures (MP or INS) is formed as a continuous film. The description will basically omit the configuration and production process substantially the same as those of the first embodiment, and concentrate on the configuration and production process that differ from those of the first embodiment.

2.1 Structure of Memory Cell Array

FIG.19is a sectional view for explaining a structure of the memory cell array of the memory device according to the second embodiment, and corresponds to the first embodiment shown inFIG.4.

As shown inFIG.19, there are semiconductors47each extending along the Y direction and having a tubular profile surrounding an insulator (not illustrated) when viewed in the Y direction, between the conductors21and22in each layer within the stack STK. One semiconductor47contacts the structures MP and INS that sandwich the semiconductor47along the X direction.

The semiconductors47include, for example, polysilicon containing a p-type impurity. The semiconductor47has a portion47ain contact with the left portion of the structure MP (according to the illustration), and this portion47afunctions as a channel of the memory cell transistor MTa. The semiconductor47has a portion47bin contact with the right portion of the structure MP (according to the illustration), and this portion47bfunctions as a channel of the memory cell transistor MTb.

In each layer within the stack STK, a semiconductor48is provided in contact with the lower portion of the semiconductor47(that is, the lower side of the tubular profile of the semiconductor47as viewed in the Y direction) and the conductor21. Also, a semiconductor49is provided in contact with the upper portion of the semiconductor47(that is, the upper side of the tubular profile of the semiconductor47as viewed in the Y direction) and the conductor22. The semiconductors48and49extend along the Y direction and include, for example, polysilicon containing an n-type impurity. The semiconductor48has a portion48ain contact with the semiconductor47a, and the semiconductor49has a portion49ain contact with the semiconductor47a. These portions48aand49aeach function as a source or a drain of the memory cell transistor MTa. The semiconductor48has a portion48bin contact with the semiconductor47b, and the semiconductor49has a portion49bin contact with the semiconductor47b. These portions48band49beach function as a source or a drain of the memory cell transistor MTb. According to such constitution, the semiconductors47a,48a, and49a, the portion of the lamination film TCB that is proximate to the semiconductor47a, and the conductors21,22, and30together form one memory cell transistor MTa. Also, the semiconductors47b,48b, and49b, the portion of the lamination film TCB that is proximate to the semiconductor47b, and the conductors21,22, and30together form one memory cell transistor MTb.

2.2 Method for Producing Memory Device

An example of a process for producing the memory cell array of the memory device according to the second embodiment will be described.FIGS.20to33each show an example of a sectional structure that includes a structural part corresponding to the memory cell array and that is formed in the course of the process for producing the memory device according to the second embodiment. Note that the sectional views which will be referred to for the production process include a cross-section vertical to the surface of the semiconductor substrate20. Also, regions indicated in each sectional view for the production process step correspond to the regions indicated inFIG.19.

First, as shown inFIG.20, a structure that will become the multiple stacks STK is formed.

More specifically, the process begins with forming an insulator40on the semiconductor substrate20, and thereafter stacking on this insulator40an insulator41A, a sacrificial member42, a sacrificial member46, and a sacrificial member44in this order. Stacking this set of the insulator41A, the sacrificial member42, the sacrificial member46, and the sacrificial member44is repeated as many times as the number of layers (in this exemplary production process, 4 times). The insulator41A contains, for example, silicon oxide, and the sacrificial member46contains, for example, polysilicon. The insulator41A, the sacrificial member42, the sacrificial member46, and the sacrificial member44may each have a thickness of, for example, 10 to 100 nanometers (nm). The film formation in this process step may use, for example, PCVD.

Next, as shown inFIG.21, lithography and anisotropic etching are conducted to remove each region intended for forming the structure MP or INS from the structure that has been formed on the insulator40, so that multiple slits SLT are formed.

FIG.22is a sectional view of the memory cell array10, taken along the line XXII-XXII indicated inFIG.21. As shown inFIG.22, this process step has formed a line-and-space shape in which the portion corresponding to the stack STK and including the sacrificial member46, and the slit SLT are alternately arranged along the X direction. Thus, the structure formed in the process step ofFIG.20is divided into multiple separate portions along the X direction.

Next, as shown inFIG.23, multiple structures INS are formed in the respective slits SLT. More specifically, an insulating film is provided over the entire surface to fill the multiple slits SLT. The film formation in this process step may use, for example, PCVD or LPCVD. Subsequently, CMP is performed for overall flatness, and an operation thereafter (for example, a combination of lithography and anisotropic etching) removes the portions corresponding to the regions for forming the structures MP from the insulating film. The insulators25corresponding to the structures INS are thus formed.

FIG.24is a sectional view of the memory cell array10, taken along the line XXIV-XXIV indicated inFIG.23. As shown inFIG.24, the process step has formed multiple holes STH along the Y direction and separated from one another by the applicable insulators25, between two stack structures each including the sacrificial member46.

Next, as shown inFIG.25, a structure MP is formed in each of the holes STH. More specifically, a tunnel insulating film33, a charge storage film32, and a block insulating film31are formed in this order in each hole STH. The film formation in this process step may use, for example, LPCVD, and the films31to33each have a thickness of about several nanometers (nm). A conductor30is subsequently formed in each hole STH. The film formation in this process step may use, for example, LPCVD or PCVD.FIG.26is a sectional view of the memory cell array10, taken along the line XXVI-XXVI indicated inFIG.25. As shown inFIG.26, the process step has formed one structure MP in each hole STH. One sacrificial member46extending along the Y direction contacts, on both of its sides in the X direction, each of the multiple structures MP arranged along the Y direction.

Next, as can be seen fromFIG.27, one or more holes (not illustrated) penetrating through all the sacrificial members46stacked along the Z direction are formed to expose the sacrificial members46. The sacrificial members46are then selectively removed by wet etching or dry etching via the holes. This exposes each upper surface of the sacrificial members42, each lower surface of the sacrificial members44, and each portion of the structures MP and INS that is located between the applicable sacrificial members42and44.

FIG.28is a sectional view of the memory cell array10, taken along the line XXVIII-XXVIII indicated inFIG.27. As shown inFIG.28, the process step has exposed the left portion and the right portion (according to the illustration) of each of the multiple structures MP.

Next, as shown inFIG.29, the p-type impurity-containing semiconductor47is formed on the inner walls surrounding the respective space created by the removal of the sacrificial member46, such that the semiconductor47has a tubular profile. Each semiconductor47contains, for example, polysilicon or amorphous silicon. If the semiconductors47adopt amorphous silicon, the semiconductors47may be turned to polysilicon as their final form by a later heat treatment step. The film formation in this process step may use, for example, LPCVD or PCVD. Subsequently, an insulator43A is formed on the inner walls of the respective semiconductor47to fill the space created by the removal of the sacrificial member46. Each insulator43A contains, for example, silicon oxide.

FIG.30is a sectional view of the memory cell array10, taken along the line XXX-XXX indicated inFIG.29. As shown inFIG.30, the process step has formed the semiconductors47such that the multiple structures MP arranged along the Y direction each have a left portion (according to the illustration) contacting the respective one of the portions47aof one semiconductor47extending along the Y direction on their left side (according to the illustration). Also, the multiple structures MP arranged along the Y direction each have a right portion (according to the illustration) contacting the respective one of the portions47bof one semiconductor47extending along the Y direction on their right side (according to the illustration).

Next, as can be seen fromFIG.31, one or more holes (not illustrated) penetrating through all the sacrificial members42and44stacked along the Z direction are formed to expose the sacrificial members42and44. The sacrificial members42and44are then selectively removed by wet etching or dry etching via the holes. This exposes the lower and upper surfaces of the semiconductors47.

Next, as shown inFIG.32, the exposed portions of the semiconductors47are subjected to selective growth of n-type impurity-containing polysilicon. This forms semiconductors48(48aand48b) and semiconductors49(49aand49b) to cover the respective lower and upper surfaces of the semiconductors47(47aand47b). The selective growth in this process step may use, for example, LPCVD.

Next, as shown inFIG.33, the conductors21are formed in the spaces created by the removal of the sacrificial members42, and the conductors22are formed in the spaces created by the removal of the sacrificial members44. The film formation in this process step may use, for example, LPCVD or PCVD.

By the process steps described above, the multiple, three-dimensionally stacked memory cell transistors MTa and MTb are formed. Thereafter, a step of forming conductors23and24, a step of forming contacts to the conductors21and22and to various circuitry components formed in the insulator40, a heat treatment step, etc. are performed so that the memory cell array10is formed.

Note that the production process described above is only an example. It is possible to adopt modifications such as inserting other processes between the process steps and changing the order of the steps as long as a problem does not occur.

2.3 Effects of Embodiment

For a stack STK to be formed according to the second embodiment, four members, i.e., the insulator41A, the sacrificial member42, the sacrificial member46, and the sacrificial member44, are stacked along the Z direction for each layer. The semiconductor47functioning as a channel of a memory cell transistor MT is formed on the inner walls surrounding the respective space created by the removal of the sacrificial member46. Subsequently, the spaces inside the semiconductors47are filled with the insulators43A. The semiconductors48and49, each functioning as a source or a drain of a memory cell transistor MT, are formed by the selective growth that is caused through the spaces created by the removal of the sacrificial members42and44and from the semiconductors47exposed in these spaces.

Accordingly, when the insulator41A, the sacrificial member42, the sacrificial member46, and the sacrificial member44are stacked, it is not necessary to dispose a film member corresponding to the semiconductor48between the sacrificial member42and the sacrificial member46, and it is not necessary to dispose a film member corresponding to the semiconductor49between the sacrificial member44and the sacrificial member46, either. This allows the number of different-material members stacked for each layer to be reduced from 6 to 4, and the increase in load of the production process steps can be suppressed as in the first embodiment. Together, as in the first embodiment, more layers can be provided in the memory cell array with a reduced processing-conversion difference for the production process steps, and therefore, increase in size of the memory cell array can be suppressed.

Additionally, the semiconductors47are formed after the structures MP are formed. Accordingly, the embodiment can reduce the risk of the semiconductors47being damaged by the etching step for forming the holes STH.

2.4 Modifications

The foregoing second embodiment tolerates various modifications. The description will basically concentrate on aspects of the configuration and the production process that differ from the second embodiment.

2.4.1 First Modification

The second embodiment has assumed the instances where the semiconductors48and49are formed by causing n-type impurity-containing semiconductor films to selectively grow on the semiconductors47, but this is not a limitation. For example, each n-type impurity-containing semiconductor film may be formed as a continuous film on the inner walls that define the space after the removal of the sacrificial member42or44.

FIG.34is one example of a sectional structure that includes a structural part corresponding to the memory cell array and that is formed in the course of the process for producing the memory device according to the first modification of the second embodiment.FIG.34corresponds to the second embodiment shown inFIG.32.

As shown inFIG.34, a semiconductor48′ is formed on the inner walls that define the space after the removal of the sacrificial member42, and a semiconductor49′ is formed on the inner walls that define the space after the removal of the sacrificial member44. The film formation in this process step may use, for example, LPCVD.

The semiconductors48′ and49′ contain, for example, amorphous silicon or polysilicon that contains an n-type impurity at a high concentration of 1E20/cm3or more, and each have a thickness of several nanometers to several tens of nanometers. Since the semiconductors48′ and49′ are each formed as a continuous film on the inner walls that surround the space after the removal of the sacrificial member42or44as described above, the formed semiconductors48′ and49′ each have a tubular profile when viewed in the Y direction. The semiconductor48′ contacts the lower surface of the corresponding semiconductors47, and the semiconductor49′ contacts the upper surface of the corresponding semiconductors47.

Accordingly, a portion48a′ of the semiconductor48′, which is in contact with the semiconductor47a, and a portion49a′ of the semiconductor49′, which is in contact with the semiconductor47a, each function as a source or a drain of the memory cell transistor MTa. A portion48b′ of the semiconductor48′, which is in contact with the semiconductor47b, and a portion49b′ of the semiconductor49′, which is in contact with the semiconductor47b, each function as a source or a drain of the memory cell transistor MTb.

According to the first modification of the second embodiment, the semiconductors48′ and49′ are formed on the inner walls surrounding the spaces created by the removal of the respective sacrificial members42and44, and such film formation is uniformly done by, for example, LPCVD. Subsequently, the spaces inside the semiconductors48′ and49′ are filled with the conductors21and22, respectively.

Therefore, as in the second embodiment, when the insulator41A, the sacrificial member42, the sacrificial member46, and the sacrificial member44are stacked, it is not necessary to dispose a film member corresponding to the semiconductor48′ between the sacrificial member42and the sacrificial member46, and it is not necessary to dispose a film member corresponding to the semiconductor49′ between the sacrificial member44and the sacrificial member46, either. This allows the number of different-material members stacked for each layer to be reduced from 6 to 4, and the increase in load of the production process steps can be suppressed. Together, more layers can be provided in the memory cell array with a reduced processing-conversion difference for the production process steps, and therefore, increase in size of the memory cell array can be suppressed.

2.4.2 Second Modification

The foregoing second embodiment and its first modification have assumed the instances where n-type impurity-containing semiconductor films are formed in the spaces created by the removal of the sacrificial members42and44, but this is not a limitation. For example, n-type impurity-containing semiconductor films may be formed by doping portions of the semiconductors47with n-type impurities.

FIG.35is one example of a sectional structure that includes a structural part corresponding to the memory cell array and that is formed in the course of the process for producing the memory device according to the second modification of the second embodiment.FIG.35corresponds to the second embodiment shown inFIG.32.

In the example shown inFIG.35, vapor-phase diffusion is conducted to cause n-type impurities to diffuse into the lower surface regions of the semiconductors47which are exposed in the spaces created by the removal of the sacrificial member42, and into the upper surface regions of the semiconductors47which are exposed in the spaces created by the removal of the sacrificial member44. The diffusion of the n-type impurities takes place in the range of, for example, several nanometers (nm) to 20 nanometers (nm) from the upper and lower surfaces of each semiconductor47. Consequently, a lower portion48a″ and an upper portion49a″ of the semiconductor47acontain more n-type impurities than p-type impurities, and each function as a source or a drain of the memory cell transistor MTa. Similarly, a lower portion48b″ and an upper portion49b″ of the semiconductor47bcontain more n-type impurities than p-type impurities, and each function as a source or a drain of the memory cell transistor MTb.

According to the second modification of the second embodiment, the semiconductors48″ are formed by the vapor-phase diffusion of n-type impurities into the semiconductors47exposed in the spaces after the removal of the sacrificial member42, and the semiconductors49″ are formed by the vapor-phase diffusion of n-type impurities into the semiconductors47exposed in the spaces after the removal of the sacrificial member44. Subsequently, the spaces after the removal of the sacrificial members42and44are filled with the conductors21and22, respectively.

Therefore, as in the second embodiment, when the insulator41A, the sacrificial member42, the sacrificial member46, and the sacrificial member44are stacked, it is not necessary to dispose a film member corresponding to the semiconductor48″ between the sacrificial member42and the sacrificial member46, and it is not necessary to dispose a film member corresponding to the semiconductor49″ between the sacrificial member44and the sacrificial member46, either. This allows the number of different-material members stacked for each layer to be reduced from 6 to 4, and the increase in load of the production process steps can be suppressed. Together, more layers can be provided in the memory cell array with a reduced processing-conversion difference for the production process steps, and therefore, increase in size of the memory cell array can be suppressed.

3. Third Embodiment

Next, a memory device according to the third embodiment will be described. The first embodiment and the second embodiment have assumed the instances where the channels of memory cell transistors MT are each formed to have a height corresponding to the length between the upper end of the applicable bit line BL and the lower end of the applicable source line SL along the Z direction. The third embodiment differs from the first embodiment and the second embodiment in that the channels of memory cell transistors MT are each formed to bridge between the lower end of the bit line BL and the upper end of the source line SL along the Z direction (in other words, have a length along the Z direction longer than the length between the upper end of the bit line BL and the lower end of the source line SL). The description will basically omit the configuration and production process substantially the same as those of the first embodiment, and concentrate on the configuration and production process that differ from those of the first embodiment.

3.1 Structure of Memory Cell Array

FIG.36is a sectional view for explaining a structure of the memory cell array of the memory device according to the third embodiment, and corresponds to the first embodiment shown inFIG.4.

As shown inFIG.36, each structure MP includes: a conductor30; a set of a tunnel insulating film33′, a charge storage film32′, and a block insulating film31′ serving as a lamination film TCB; and semiconductors52a,52b,55a,55b,56a, and56b. The semiconductors52aand52bfunction as channels of the memory cell transistors MTa and MTb, respectively. The semiconductors55aand56aeach function as a source or a drain of the memory cell transistor MTa, and the semiconductors55band56beach function as a source or a drain of the memory cell transistor MTb. Note that, in the structure MP, the conductor30is of a similar structure to the first embodiment.

Among the four side surfaces and the lower surface of the conductor30, two opposing side surfaces (in the example shown inFIG.36, the two surfaces along the Y-Z plane) and the lower surface are wholly covered by the block insulating film31′, the charge storage film32′, and the tunnel insulating film33′ disposed in this order. Accordingly, the lamination film TCB has two side surfaces along the Y-Z plane. Also, the lamination film TCB for the multiple memory cell transistors MTa formed in different layers within one structure MP, and the lamination film TCB for the multiple memory cell transistors MTb formed similarly within the same structure MP are constituted by one continuous film. The tunnel insulating film33′, the charge storage film32′, and the block insulating film31′ may contain the same materials as the tunnel insulating film33, the charge storage film32, and the block insulating film31of the first embodiment, respectively.

The lamination film TCB has, for each layer, portions corresponding to the height from the lower end of the conductor21to the upper end of the conductor22. The lamination film TCB has two side surfaces for these portions, where the semiconductor52ais provided on one side surface (in the example shown inFIG.36, the left surface) and the semiconductor52bis provided on the other side surface (in the example shown inFIG.36, the right surface).

For each layer, the semiconductor55ais provided on the side surface of the semiconductor52afor a portion corresponding to the height from the lower end to the upper end of the conductor21, and the semiconductor56ais provided on the side surface of the semiconductor52afor a portion corresponding to the height from the lower end to the upper end of the conductor22. Also, for each layer, the semiconductor55bis provided on the side surface of the semiconductor52bfor a portion corresponding to the height from the lower end to the upper end of the conductor21, and the semiconductor56bis provided on the side surface of the semiconductor52bfor a portion corresponding to the height from the lower end to the upper end of the conductor22.

The structure INS includes an insulator54. The insulator54contains, for example, silicon oxide and has a portion extending along the Z direction from the position (height) comparable with the lower end of the stack STK to the position comparable with the upper end of the stack STK. The insulator54also has portions extending along the XY plane in film regions within each stack STK, including a film region below the lowermost conductor21, film regions between the applicable conductors21and22, and a film region above the uppermost conductor22.

According to such constitution, the semiconductors52a,55a, and56a, the portion of the lamination film TCB that is proximate to the semiconductor52a, and the conductors21,22, and30together form one memory cell transistor MTa. Also, the semiconductors52b,55b, and56b, the portion of the lamination film TCB that is proximate to the semiconductor52b, and the conductors21,22, and30together form one memory cell transistor MTb.

3.2 Method for Producing Memory Device

An example of a process for producing the memory cell array of the memory device according to the third embodiment will be described.FIGS.37to55each show an example of a sectional structure that includes a structural part corresponding to the memory cell array and that is formed in the course of the process for producing the memory device according to the third embodiment. Note that the sectional views which will be referred to for the production process include a cross-section vertical to the surface of the semiconductor substrate20. Also, regions indicated in each sectional view for the production process step correspond to the regions indicated inFIG.36.

First, as shown inFIG.37, a structure that will become the multiple stacks STK is formed.

More specifically, the process begins with forming an insulator40on the semiconductor substrate20, and thereafter stacking on this insulator40an insulator41B, a sacrificial member42, an insulator43B, and a sacrificial member44in this order. Stacking this set of the insulator41B, the sacrificial member42, the insulator43B, and the sacrificial member44is repeated as many times as the number of layers (in this exemplary production process, 4 times). The insulator41B contains, for example, silicon oxide added with boron, phosphorus, or both boron and phosphorus, and the insulator43B contains, for example, silicon oxide. With the boron additive or the phosphorus additive, or both, the insulator41B can have a greater etching rate than the insulator43B without such an additive, at the selective etching operations for oxides. The insulator41B, the sacrificial member42, the insulator43B, and the sacrificial member44may each have a thickness of, for example, 10 to 100 nanometers (nm). The film formation in this process step may use, for example, PCVD.

Next, as shown inFIG.38, lithography and anisotropic etching are conducted to remove each region intended for forming the structure MP or INS from the structure that has been formed on the insulator40, so that multiple slits SLT are formed.

FIG.39is a sectional view of the memory cell array10, taken along the line XXXIX-XXXIX indicated inFIG.38. As shown inFIG.39, the process step has formed a line-and-space shape in which the portion corresponding to the stack STK and including the insulator43B, and the slit SLT are alternately arranged along the X direction. Thus, the structure formed in the process step ofFIG.37is divided into multiple separate portions along the X direction.

Next, as shown inFIG.40, a structure that can constitute the structure MP is formed in each slit SLT. More specifically, an insulator53, a semiconductor52, a tunnel insulating film33′, a charge storage film32′, a block insulating film31′, and a sacrificial member51are formed in this order over the entire surface to fill the multiple slits SLT. Subsequently, CMP is performed for overall flatness and the surfaces of the stacks STK are exposed, so that the material portions filling the respective slits SLT are separate from each other. Each insulator53contains, for example, silicon oxide. Each semiconductor52contains, for example, polysilicon or amorphous silicon containing a p-type impurity. If the semiconductors52adopt amorphous silicon, the semiconductors52may be turned to polysilicon as their final form by a later heat treatment step. The sacrificial member51contains, for example, polysilicon. The film formation in this process step may use, for example, PCVD or LPCVD.

FIG.41is a sectional view of the memory cell array10, taken along the line XLI-XLI indicated inFIG.40. As shown inFIG.41, the process step has filled each slit SLT with the insulator53, the semiconductor52, the tunnel insulating film33′, the charge storage film32′, the block insulating film31′, and the sacrificial member51, which each extend along the Y direction.

Next, as shown inFIG.42, lithography and anisotropic etching are conducted so that, among the material portions filling the respective slits SLT, the portions that will become the structures MP are maintained while the remaining portions are removed. Accordingly, multiple holes STH are created at the positions where the material portions have been removed, and the insulators41B are exposed.

FIG.43is a sectional view of the memory cell array10, taken along the line XLIII-XLIII indicated inFIG.42. As shown inFIG.43, the process step has turned the state where each slit SLT is filled with the material portion, into the state where the material portions as the later structures MP are retained in an arrangement along the Y direction with the intervening holes STH. In each of the portions that will become the structure MP, a set of the lamination film TCB, the semiconductor52, and the insulator53has two side surfaces sandwiching the sacrificial member51along the X direction, but does not have side surfaces sandwiching the sacrificial member51along the Y direction.

Next, as shown inFIG.44, the insulators41B are selectively removed by wet etching via the holes STH. Since each insulator41B has a greater etching rate than the insulators43B (and the insulator53) as discussed above, the etching in this process step can remove the insulators41B until the associated portions of the insulator53are exposed, without substantively damaging the insulators43B.

FIG.45is a sectional view of the memory cell array10, taken along the line XLV-XLV indicated inFIG.44. As shown inFIG.45, the process step has connected together the multiple holes STH via the spaces created by the removal of the insulators41B, so that one hole STHa results.

Next, as shown inFIG.46, the portions of the insulator53are selectively removed by wet etching or dry etching via the hole STHa until the associated portions of the semiconductor52are exposed (that is, for as much as the thickness of the insulator53). Accordingly, the insulator53is, for each layer, divided into two parts that sandwich the lamination film TCB and the sacrificial member51. Such two parts of the insulator53are portions53aand53bof one layer, respectively. That is, the portions53aand53bfor each layer extend along the Z direction from the lower end of the sacrificial member42to the upper end of the sacrificial member44.

Subsequently, the portions of the semiconductor52are selectively removed by further wet etching or dry etching via the hole STHa until the tunnel insulating film33′ is exposed (that is, for as much as the thickness of the semiconductor52). Accordingly, the semiconductor52is, for each layer, divided into two parts that sandwich the lamination film TCB and the sacrificial member51. Such two parts of the semiconductor52are portions52aand52bof one layer, respectively. That is, the portions52aand52bfor each layer extend along the Z direction from the lower end of the sacrificial member42to the upper end of the sacrificial member44.

FIGS.47and48are sectional views of the memory cell array10, taken along the line XLVII-XLVII and the line XLVIII-XLVIII indicated inFIG.46, respectively. As shown inFIG.47, the process step has completely removed the portions of the semiconductor52and the insulator53that are at the same height as the respective associated insulators41B. On the other hand, as shown inFIG.48, the process step has partially removed the portions of the semiconductor52and the insulator53(as well as the sacrificial member51), which are at the same height as the respective associated insulators43B, along the Y direction and from the part exposed along the X-Z plane. That is, the semiconductors52aand52bare each shorter in the Y direction than the lamination film TCB.

Next, as shown inFIG.49, a structure INS is formed in the hole STHa. More specifically, an insulating film is provided over the entire surface to fill the hole STHa. The film formation in this process step may use, for example, PCVD or LPCVD. Subsequently, CMP is performed for overall flatness so that the insulator54corresponding to the structure INS is formed.

FIGS.50and51are sectional views of the memory cell array10, taken along the line L-L and the line LI-LI indicated inFIG.49, respectively. As shown inFIGS.50and51, the process step has filled all the spaces between the structures MP and between the sacrificial members42and44, with the insulator54.

Next, as can be seen fromFIG.52, one or more holes (not illustrated) penetrating through all the sacrificial members42and44stacked along the Z direction are formed to expose the sacrificial members42and44. The sacrificial members42and44are then selectively removed by wet etching or dry etching via the holes. This exposes the side surfaces of each of the semiconductors52aand52b, for a portion from the lower end to the upper end of the sacrificial member42and a portion from the lower end to the upper end of the sacrificial member44.

Next, as shown inFIG.53, the exposed portions of the semiconductors52aand52bare subjected to selective growth of n-type impurity-containing polysilicon. Accordingly, a semiconductor55ais formed to cover, among the exposed portions of each semiconductor52a, the portion (side surface) exposed in the space after the removal of the sacrificial member42, and a semiconductor56ais formed to cover the portion (side surface) exposed in the space after the removal of the sacrificial member44. Also, a semiconductor55bis formed to cover, among the exposed portions of each semiconductor52b, the portion (side surface) exposed in the space after the removal of the sacrificial member42, and a semiconductor56bis formed to cover the portion (side surface) exposed in the space after the removal of the sacrificial member44. The selective growth in this process step may use, for example, LPCVD.

Next, as shown inFIG.54, the conductors21are formed in the spaces created by the removal of the sacrificial members42, and the conductors22are formed in the spaces created by the removal of the sacrificial members44. The film formation in this process step may use, for example, LPCVD or PCVD.

Accordingly, between one conductor21and the lamination film TCB, the semiconductor55acontacts the side surface of each of the semiconductor52aand the conductor21along the Y direction, and the semiconductor55bcontacts the side surface of each of the semiconductor52band the conductor21along the Y direction. Between one conductor22and the lamination film TCB, the semiconductor56acontacts the side surface of each of the semiconductor52aand the conductor22along the Y direction, and the semiconductor56bcontacts the side surface of each of the semiconductor52band the conductor22along the Y direction. Also, the upper surface of each semiconductor55is higher than or flush with the upper surface of the associated conductor21, and the lower surface of each semiconductor56is lower than or flush with the lower surface of the associated conductor22.

Next, as shown inFIG.55, the sacrificial member51is removed by wet etching, and the space after the removal of the sacrificial member51is filled with a conductor30. The film formation in this process step may use, for example, LPCVD or PCVD.

By the process steps described above, the multiple, three-dimensionally stacked memory cell transistors MTa and MTb are formed. Thereafter, a step of forming conductors23and24, a step of forming contacts to the conductors21and22and to various circuitry components formed in the insulator40, a heat treatment step, etc. are performed so that the memory cell array10is formed.

Note that the production process described above is only an example. It is possible to adopt modifications such as inserting other processes between the process steps and changing the order of the steps as long as a problem does not occur.

3.3 Effects of Embodiment

For a stack STK to be formed according to the third embodiment, four members, i.e., the insulator41B, the sacrificial member42, the insulator43B, and the sacrificial member44, are stacked along the Z direction for each layer. The semiconductor52functioning as a channel of a memory cell transistor MT, and the insulator53covering the side surface of the semiconductor52are formed on the side surface of the lamination film TCB as a part of the structure MP. Portions of the semiconductor52and the insulator53, at the height where the associated insulator41B was present, are removed via the space created by the removal of this insulator41B. The semiconductor52is thus divided to correspond to the respective layers. Subsequently, portions of the semiconductor52, at the respective heights where the associated sacrificial members42and44were present, are exposed to the spaces created by the removal of these sacrificial members42and44, upon removal of the associated portions of the insulator53. The semiconductors55and56, each functioning as a source or a drain of a memory cell transistor MT, are formed by the selective growth caused from the portions of the semiconductor52exposed in the spaces created by the removal of the sacrificial members42and44, respectively.

Accordingly, when the insulator41B, the sacrificial member42, the insulator43B, and the sacrificial member44are stacked, it is not necessary to dispose a film member corresponding to the semiconductor55between the sacrificial member42and the insulator43B, and it is not necessary to dispose a film member corresponding to the semiconductor56between the sacrificial member44and the insulator43B, either. This allows the number of different-material members stacked for each layer to be reduced from 6 to 4, and the increase in load of the production process steps can be suppressed as in the first and second embodiments. Together, as in the first and second embodiments, more layers can be provided in the memory cell array with a reduced processing-conversion difference for the production process steps, and therefore, increase in size of the memory cell array can be suppressed.

Also, the semiconductor52is formed by the step of filling the slit SLT, and as such, the area for film formation is relatively reduced. This facilitates the film formation with a uniform thickness.

Moreover, the surface of the semiconductor52along the Y-Z plane is not exposed during the later step of forming the hole STH. Accordingly, as in the second embodiment, the embodiment can reduce the risk of the semiconductors52being damaged during the step after the formation of the semiconductor52.

3.4 Modifications

The foregoing third embodiment tolerates various modifications. The description will basically concentrate on aspects of the configuration and the production process that differ from the third embodiment.

3.4.1 First Modification

The third embodiment has assumed the instances where the semiconductors55aand55b, and the semiconductors56aand56bare formed by causing n-type impurity-containing semiconductor films to selectively grow on the semiconductors52aand52b, but this is not a limitation. For example, each n-type impurity-containing semiconductor film may be formed as a continuous film on the inner walls that define the space after the removal of the sacrificial member42or44.

FIG.56is one example of a sectional structure that includes a structural part corresponding to the memory cell array and that is formed in the course of the process for producing the memory device according to the first modification of the third embodiment.FIG.56corresponds to the third embodiment shown inFIG.53.

As shown inFIG.56, a semiconductor55′ is formed on the inner walls that define the space after the removal of the sacrificial member42, and a semiconductor56′ is formed on the inner walls that define the space after the removal of the sacrificial member44. The film formation in this process step may use, for example, LPCVD.

The semiconductors55′ and56′ contain, for example, amorphous silicon or polysilicon that contains an n-type impurity at a high concentration of 1E20/cm3or more, and each have a thickness of several nanometers to several tens of nanometers. Since the semiconductors55′ and56′ are each formed as a continuous film on the inner walls that surround the space after the removal of the sacrificial member42or44as described above, the formed semiconductors55′ and56′ each have a tubular profile when viewed in the Y direction. Also, the semiconductor55′ contacts the lower side surface of the semiconductor52aor52b, and the semiconductor56′ contacts the upper side surface of the semiconductor52aor52b. Also, the region of contact between the semiconductor52aor52band the semiconductor55′ has an upper end higher than the upper surface of the conductor21when formed, and the region of contact between the semiconductor52aor52band the semiconductor56′ has a lower end lower than the lower surface of the conductor22when formed.

Accordingly, a portion55a′ of the semiconductor55′, which is in contact with the semiconductor52a, and a portion56a′ of the semiconductor56′, which is in contact with the semiconductor52a, each function as a source or a drain of the memory cell transistor MTa. A portion55b′ of the semiconductor55′, which is in contact with the semiconductor52b, and a portion56b′ of the semiconductor56′, which is in contact with the semiconductor52b, each function as a source or a drain of the memory cell transistor MTb.

According to the first modification of the third embodiment, the semiconductors55′ and56′ are formed on the inner walls surrounding the spaces created by the removal of the respective sacrificial members42and44, and such film formation is uniformly done by, for example, LPCVD. Subsequently, the spaces inside the semiconductors55′ and56′ are filled with the conductors21and22, respectively.

Therefore, as in the third embodiment, when the insulator41B, the sacrificial member42, the insulator43B, and the sacrificial member44are stacked, it is not necessary to dispose a film member corresponding to the semiconductor55′ between the sacrificial member42and the insulator43B, and it is not necessary to dispose a film member corresponding to the semiconductor56′ between the sacrificial member44and the insulator43B, either. This allows the number of different-material members stacked for each layer to be reduced from 6 to 4, and the increase in load of the production process steps can be suppressed. Together, more layers can be provided in the memory cell array with a reduced processing-conversion difference for the production process steps, and therefore, increase in size of the memory cell array can be suppressed.

3.4.2 Second Modification

The foregoing third embodiment and its first modification have assumed the instances where n-type impurity-containing semiconductor films are formed in the spaces created by the removal of the sacrificial members42and44, but this is not a limitation. For example, n-type impurity-containing semiconductor films may be formed by doping portions of the semiconductors52aand52bwith n-type impurities.

FIG.57is one example of a sectional structure that includes a structural part corresponding to the memory cell array and that is formed in the course of the process for producing the memory device according to the second modification of the third embodiment.FIG.57corresponds to the third embodiment shown inFIG.53.

In the example shown inFIG.57, vapor-phase diffusion is conducted to cause n-type impurities to diffuse into the lower side surface regions of the semiconductors52aand52bwhich are exposed in the spaces created by the removal of the sacrificial member42, and into the upper side surface regions of the semiconductors52aand52bwhich are exposed in the spaces created by the removal of the sacrificial member44. The diffusion of the n-type impurities takes place in the range of, for example, several nanometers (nm) to 20 nanometers (nm) from each of the upper and lower side surfaces of the semiconductor52a.

Consequently, a lower portion55a″ and an upper portion56a″ of the semiconductor52acontain more n-type impurities than p-type impurities, and each function as a source or a drain of the memory cell transistor MTa. Similarly, a lower portion55b″ and an upper portion56b″ of the semiconductor52bcontain more n-type impurities than p-type impurities, and each function as a source or a drain of the memory cell transistor MTb.

Note that the resultant boundary between each semiconductor52and its lower portion55″ may be at the height higher than or comparable with the lower surface of the associated insulator43B, and the resultant boundary between each semiconductor52and its upper portion56″ may be at the height lower than or comparable with the upper surface of the associated insulator43B.

According to the second modification of the third embodiment, the semiconductors55″ are formed by the vapor-phase diffusion of n-type impurities into the semiconductors52exposed in the spaces after the removal of the sacrificial member42, and the semiconductors56″ are formed by the vapor-phase diffusion of n-type impurities into the semiconductors52exposed in the spaces after the removal of the sacrificial member44. Subsequently, the spaces after the removal of the sacrificial members42and44are filled with the conductors21and22, respectively.

Therefore, as in the third embodiment, when the insulator41B, the sacrificial member42, the insulator43B, and the sacrificial member44are stacked, it is not necessary to dispose a film member corresponding to the semiconductor55″ between the sacrificial member42and the insulator43B, and it is not necessary to dispose a film member corresponding to the semiconductor56″ between the sacrificial member44and the insulator43B, either. This allows the number of different-material members stacked for each layer to be reduced from 6 to 4, and the increase in load of the production process steps can be suppressed. Together, more layers can be provided in the memory cell array with a reduced processing-conversion difference for the production process steps, and therefore, increase in size of the memory cell array can be suppressed.

4. Fourth Embodiment

Next, a memory device according to the fourth embodiment will be described. The third embodiment has assumed the instances where the entire side surfaces of the conductors21and22contact the source or the drain of a memory cell transistor MT. The fourth embodiment differs from the third embodiment in that the lower side surfaces of the conductors21and22contact the source or the drain of a memory cell transistor MT. The description will basically omit the configuration and production process substantially the same as those of the third embodiment, and concentrate on the configuration and production process that differ from those of the third embodiment.

4.1 Structure of Memory Cell Array

FIG.58is a sectional view for explaining a structure of the memory cell array of the memory device according to the fourth embodiment, and corresponds to the third embodiment shown inFIG.36.

As shown inFIG.58, for each layer, a semiconductor57ais provided on the side surface of the semiconductor52afor a portion proximate to the lower end of the conductor21, and a semiconductor58ais provided on the side surface of the semiconductor52afor a portion proximate to the upper end of the conductor22. The semiconductors57aand58aeach have a portion adjacent to the semiconductor52aand a portion distant from the semiconductor52ain the X direction, and the latter portion is longer in the Z direction than the former portion.

Also, for each layer, a semiconductor57bis provided on the side surface of the semiconductor52bfor a portion proximate to the lower end of the conductor21, and a semiconductor58bis provided on the side surface of the semiconductor52bfor a portion proximate to the upper end of the conductor22. The semiconductors57band58beach have a portion adjacent to the semiconductor52band a portion distant from the semiconductor52bin the X direction, and the latter portion is longer in the Z direction than the former portion.

The region of contact between the semiconductor57aand the semiconductor52a, and the region of contact between the semiconductor57band the semiconductor52beach have an upper end lower than the upper end of the conductor21. The region of contact between the semiconductor58aand the semiconductor52a, and the region of contact between the semiconductor58band the semiconductor52beach have a lower end higher than the lower end of the conductor22.

According to such constitution, the semiconductors52a,57a, and58a, the portion of the lamination film TCB that is proximate to the semiconductor52a, and the conductors21,22, and30together form one memory cell transistor MTa. Also, the semiconductors52b,57b, and58b, the portion of the lamination film TCB that is proximate to the semiconductor52b, and the conductors21,22, and30together form one memory cell transistor MTb.

4.2 Method for Producing Memory Device

An example of a process for producing the memory cell array of the memory device according to the fourth embodiment will be described.FIGS.59to65each show an example of a sectional structure that includes a structural part corresponding to the memory cell array and that is formed in the course of the process for producing the memory device according to the fourth embodiment. Note that the sectional views which will be referred to for the production process include a cross-section vertical to the surface of the semiconductor substrate20. Also, regions indicated in each sectional view for the production process step correspond to the regions indicated inFIG.58.

First, the process steps similar to the steps described with reference toFIGS.37to46for the third embodiment are performed so that the hole STHa is formed and the insulator53and the semiconductor52are divided to correspond to the respective layers.

Next, as shown inFIG.59, portions of the insulator53are further selectively removed by wet etching or dry etching via the hole STHa. Accordingly, the insulators53aand53b, having been etched along the Z direction, are turned into the insulators53a′ and53b′ shorter in the Z direction than the associated semiconductor52. That is, in each layer, the insulators53a′ and53b′ each have a lower end higher than the lower end of the sacrificial member42, and an upper end lower than the upper end of the sacrificial member44.

FIG.60is a sectional view of the memory cell array10, taken along the line LX-LX indicated inFIG.59. As shown inFIG.60, the process step has partially removed the portions of the semiconductor52and the insulator53(as well as the sacrificial member51), which are at the same height as the respective associated insulators43B, along the Y direction and from the part exposed along the X-Z plane, so that the insulator53becomes shorter in the Y direction than the semiconductor52.

Next, as shown inFIG.61, a structure INS is formed in the hole STHa. More specifically, an insulating film is provided over the entire surface to fill the hole STHa. The film formation in this process step may use, for example, PCVD or LPCVD. Subsequently, CMP is performed for overall flatness so that the insulator54corresponding to the structure INS is formed. Note that the insulator54here is preferably a silicon oxide having a lower density than the insulators53a′ and53b′. The insulator54can accordingly have a greater etching rate than the insulators53a′ and53b′ at the selective etching operations for oxides.

FIG.62is a sectional view of the memory cell array10, taken along the line LXII-LXII indicated inFIG.61. As shown inFIGS.62, the process step has filled all the spaces between the structures MP and between the sacrificial members42and44, with the insulator54.

Next, as can be seen fromFIG.63, one or more holes (not illustrated) penetrating through all the sacrificial members42and44stacked along the Z direction are formed to expose the sacrificial members42and44. The sacrificial members42and44are then selectively removed by wet etching or dry etching via the holes. This exposes the insulator54and the insulator53a′ or53b′, arranged along the Z direction.

Subsequently, further wet etching or dry etching is performed to selectively remove portions of the insulator54. As described above, the insulator54has been formed at a lower density than the insulator53a′ or53b′ so that it has a greater etching rate. Accordingly, when the insulator54is removed in the X direction until the semiconductors52aand52bare exposed, the insulator53a′ can be retained on the semiconductor52aand the insulator53b′ can be retained on the semiconductor52b.

Next, as shown inFIG.64, the exposed portions of the semiconductors52aand52bare subjected to selective growth of n-type impurity-containing polysilicon. This forms a semiconductor57acovering the lower exposed portion of the semiconductor52athat constitutes one Z-direction excess-length portion thereof as compared to the insulator53a′, and also covering the lower region of the insulator53a′. Also, a semiconductor58ais formed, covering the upper exposed portion of the semiconductor52athat constitutes another Z-direction excess-length portion as compared to the insulator53a′, and also covering the upper region of the insulator53a′. Meanwhile, a semiconductor57bis formed, covering the lower exposed portion of the semiconductor52bthat constitutes one Z-direction excess-length portion thereof as compared to the insulator53b′, and also covering the lower region of the insulator53b′. Also, a semiconductor58bis formed, covering the upper exposed portion of the semiconductor52bthat constitutes another Z-direction excess-length portion as compared to the insulator53b′, and also covering the upper region of the insulator53b′. The selective growth in this process step may use, for example, LPCVD.

Next, as shown inFIG.65, the conductors21are formed in the spaces created by the removal of the sacrificial members42, and the conductors22are formed in the spaces created by the removal of the sacrificial members44. The film formation in this process step may use, for example, LPCVD or PCVD. Subsequently, the sacrificial member51is removed by wet etching, and the space after the removal of the sacrificial member51is filled with a conductor30. The film formation in this process step may use, for example, LPCVD or PCVD.

By the process steps described above, the multiple, three-dimensionally stacked memory cell transistors MTa and MTb are formed. Thereafter, a step of forming conductors23and24, a step of forming contacts to the conductors21and22and to various circuitry components formed in the insulator40, a heat treatment step, etc. are performed so that the memory cell array10is formed.

Note that the production process described above is only an example. It is possible to adopt modifications such as inserting other processes between the process steps and changing the order of the steps as long as a problem does not occur.

4.3 Effects of Embodiment

According to the fourth embodiment, portions of the semiconductor52and the insulator53, at the height where the associated insulator41B was present, are removed via the space created by the removal of this insulator41B. The semiconductor52is thus divided to correspond to the respective layers. Also, the insulator53are further partially removed along the Z direction via the same space, and the portion subjected to this further removal is substituted by the insulator54. Thereafter, the portions substituted by the insulator54are selectively removed via the respective spaces created by the removal of the sacrificial members42and44, so that the associated portions of the semiconductor52are exposed in the spaces. The semiconductors57and58, each functioning as a source or a drain of a memory cell transistor MT, are formed by the selective growth caused from the portions of the semiconductor52exposed in the spaces created by the removal of the sacrificial members42and44, respectively.

Thus, this allows the number of different-material members stacked for each layer to be reduced from 6 to 4, and the increase in load of the production process steps can be suppressed as in the third embodiment. Together, as in the third embodiment, more layers can be provided in the memory cell array with a reduced processing-conversion difference for the production process steps, and therefore, increase in size of the memory cell array can be suppressed.

Moreover, since the length of the channels can be increased, the embodiment realizes improved properties of the memory cell transistors MT.

4.4 Modifications

The foregoing fourth embodiment tolerates various modifications. The description will basically concentrate on aspects of the configuration and the production process that differ from the fourth embodiment.

4.4.1 First Modification

The foregoing fourth embodiment has assumed the instances where the semiconductors57aand57b, and the semiconductors58aand58bare formed by causing n-type impurity-containing semiconductor films to selectively grow on the semiconductors52aand52b, but this is not a limitation. For example, each n-type impurity-containing semiconductor film may be formed as a continuous film on the inner walls that define the space after the removal of the sacrificial member42or44.

FIG.66is one example of a sectional structure that includes a structural part corresponding to the memory cell array and that is formed in the course of the process for producing the memory device according to the first modification of the fourth embodiment.FIG.66corresponds to the fourth embodiment shown inFIG.64.

As shown inFIG.66, a semiconductor57′ is formed on the inner walls that define the space after the removal of the sacrificial member42, and a semiconductor58′ is formed on the inner walls that define the space after the removal of the sacrificial member44. The film formation in this process step may use, for example, LPCVD.

The semiconductors57′ and58′ contain, for example, amorphous silicon or polysilicon that contains an n-type impurity at a high concentration of 1E20/cm3or more, and each have a thickness of several nanometers to several tens of nanometers. Since the semiconductors57′ and58′ are each formed as a continuous film on the inner walls that surround the space after the removal of the sacrificial member42or44as described above, the formed semiconductors57′ and58′ each have a tubular profile when viewed in the Y direction. Also, the semiconductor57′ contacts the lower side surface of the semiconductor52aor52b, and the semiconductor58′ contacts the upper side surface of the semiconductor52aor52b.

Here, the region of contact between the semiconductor57′ and the semiconductor52has an upper end lower than the upper surface of the conductor21when formed, and the region of contact between the semiconductor58′ and the semiconductor52has a lower end higher than the lower surface of the conductor22when formed.

Accordingly, a portion57a′ of the semiconductor57′, which is in contact with the semiconductor52a, and a portion58a′ of the semiconductor58′, which is in contact with the semiconductor52a, each function as a source or a drain of the memory cell transistor MTa. A portion57b′ of the semiconductor57′, which is in contact with the semiconductor52b, and a portion58b′ of the semiconductor58′, which is in contact with the semiconductor52b, each function as a source or a drain of the memory cell transistor MTb.

According to the first modification of the fourth embodiment, the semiconductors57′ and58′ are formed on the inner walls surrounding the spaces created by the removal of the respective sacrificial members42and44, and such film formation is uniformly done by, for example, LPCVD. Subsequently, the spaces inside the semiconductors57′ and58′ are filled with the conductors21and22, respectively.

Thus, this allows the number of different-material members stacked for each layer to be reduced from 6 to 4, and the increase in load of the production process steps can be suppressed as in the fourth embodiment. Together, as in the fourth embodiment, more layers can be provided in the memory cell array with a reduced processing-conversion difference for the production process steps, and therefore, increase in size of the memory cell array can be suppressed.

4.4.2 Second Modification

The foregoing fourth embodiment and its first modification have assumed the instances where n-type impurity-containing semiconductor films are formed in the spaces created by the removal of the sacrificial members42and44, but this is not a limitation. For example, n-type impurity-containing semiconductor films may be formed by doping portions of the semiconductors52aand52bwith n-type impurities.

FIG.67is one example of a sectional structure that includes a structural part corresponding to the memory cell array and that is formed in the course of the process for producing the memory device according to the second modification of the fourth embodiment.FIG.67corresponds to the fourth embodiment shown inFIG.64.

In the example shown inFIG.67, vapor-phase diffusion is conducted to cause n-type impurities to diffuse into the lower side surface regions of the semiconductors52aand52bwhich are exposed in the spaces created by the removal of the sacrificial member42, and into the upper side surface regions of the semiconductors52aand52bwhich are exposed in the spaces created by the removal of the sacrificial member44. The diffusion of the n-type impurities takes place in the range of, for example, several nanometers (nm) to 20 nanometers (nm) from each of the upper and lower side surfaces of the semiconductor52a.

Consequently, a lower portion57a″ and an upper portion58a″ of the semiconductor52acontain more n-type impurities than p-type impurities, and each function as a source or a drain of the memory cell transistor MTa. Similarly, a lower portion57b″ and an upper portion58b″ of the semiconductor52bcontain more n-type impurities than p-type impurities, and each function as a source or a drain of the memory cell transistor MTb.

According to the second modification of the fourth embodiment, the semiconductors57″ are formed by the vapor-phase diffusion of n-type impurities into the semiconductors52exposed in the spaces after the removal of the sacrificial member42, and the semiconductors58″ are formed by the vapor-phase diffusion of n-type impurities into the semiconductors52exposed in the spaces after the removal of the sacrificial member44. Subsequently, the spaces after the removal of the sacrificial members42and44are filled with the conductors21and22, respectively.

This allows the number of different-material members stacked for each layer to be reduced from 6 to 4, and the increase in load of the production process steps can be suppressed as in the fourth embodiment. Together, as in the fourth embodiment, increase in size of the memory cell array can be suppressed.

5. Fifth Embodiment

Next, a memory device according to the fifth embodiment will be described. The first to fourth embodiments have assumed the instances where each of the multiple bit lines BL has a first end connected to the corresponding memory cell transistor MT and a second end connected to the corresponding bit line driver131. The description will be given, as the fifth embodiment, of a detailed bit line configuration between the bit line drivers131and the memory cell transistors MT. The description will basically omit the configuration and production process substantially the same as those of the first embodiment, and concentrate on the configuration and production process that differ from those of the first embodiment.

5.1 Circuit Configuration of Memory Cell Array

FIG.68is one example of a circuit diagram for explaining a structure of the memory cell array of the memory device according to the fifth embodiment, and corresponds to the first embodiment shown inFIG.2.

As shown inFIG.68, multiple bit lines include multiple global bit lines GBL, and multiple local bit lines LBL connected to the respective global bit lines GBL. The local bit lines LBL shown inFIG.68correspond to the bit lines BL which have been illustrated for the first to fourth embodiments. That is, multiple memory cell transistors MT associated with the same column are connected in parallel with each other between a given local bit line LBL and a given source line SL among the multiple pairs of the local bit lines LBL and the source lines SL.

The multiple local bit lines LBL are each connected to a first end of a corresponding select transistor ST. Multiple select transistors ST in one layer have their gates connected to one common select gate line SGL. In other words, gates of multiple select transistors ST in the k-th layer have common connections to the same select gate line SGLk (1≤k≤n). Multiple select transistors ST connected to the respective memory cell transistors MTa (or MTb) in one string NSa (or NSb) have their second ends connected to one common global bit line GBL.

In the disclosure herein, a term “string STS” will be used to refer to a unit constituted by multiple select transistors ST having common connections to the same global bit line GBL, for the sake of explanation.

The above configuration allows for the selection of a single local bit line LBL through the selection of a set of one global bit line GBL and one select gate line SGL.

5.2 Structure of Memory Cell Array

An exemplary structure of the memory cell array of the memory device according to the fifth embodiment will be described.

FIG.69is a plan view for explaining a planar layout of the memory cell array of the memory device according to the fifth embodiment.FIG.69schematically shows, as one example, a cell region in the memory cell array10and hookup regions for pulling out various interconnects to be higher than the memory cell array10, which are viewed from above. The cell region here is of a similar structure to the first embodiment shown inFIG.3, so the substantial description thereof will be basically omitted.

Note that, for the sake of explanation, the description will assume the instances where there are two memory cell transistors MT stacked along the Z direction (that is, where two layers, i.e., a first layer and a second layer, are provided).

As shown inFIG.69, the hookup regions include a bit line hookup region for pulling out the global bit lines GBL to be higher than the memory cell array10, and a select gate line hookup region for pulling out the select gate lines SGL to be higher than the memory cell array10. The cell region, the bit line hookup region, and the select gate line hookup region are sequentially arranged along the Y direction in this order.

The bit line hookup region is provided with multiple strings STS arranged along the X direction. The multiple strings STS are each disposed between two consecutive structures INS while contacting these two structures INS, so that the strings STS are separate from one another. The multiple strings STS arranged along the X direction each have a first end in the Y direction that contacts the corresponding stack STK extending along the Y direction from the side of the cell region. This stack STK includes a stack of multiple local bit lines LBL. Also, the multiple strings STS arranged along the X direction have respective second ends in the Y direction that have common connections to multiple select gate lines SGL (SGL1and SGL2) provided for the respective layers and extending along the Y direction in the select gate line hookup region. Further, each of the multiple strings STS is connected to the global bit line GBL extending therethrough along the Z direction.

With the above constitution, the global bit lines GBL are pulled out in the bit line hookup region so that they are higher than the memory cell array10.

In the select gate line hookup region, the select gate lines SGL corresponding to the respective layers together form a staircase profile along the Y direction in order for them to be pulled out higher than the memory cell array10. In other words, the Y-direction extension of the select gate line SGL for the lower layer (e.g., select gate line SGL1) is, starting from the region of contact with the strings STS, longer than that of the select gate line SGL for the upper layer (e.g., select gate line SGL2). The select gate line SGL for the lower layer is connected with a contact CV which extends along the Z direction where the select gate line SGL for the upper layer is absent. As such, contacts CV1and CV2in this example are disposed such that the former is more distant from the string STS in the Y direction than the latter.

With the above constitution, the select gate lines SGL are pulled out in the select gate line hookup region so that they are higher than the memory cell array10.

FIG.70shows an exemplary sectional structure of the memory cell array10shown inFIG.69, assuming that the array is cut along the line LXX-LXX. Thus,FIG.70is mainly composed of the cross-sections of the bit line hookup region and the select gate line hookup region.

As shown inFIG.70, the structural part to form the string STS in the bit line hookup region includes a conductor65, insulators61and67, and semiconductors62,64,66, and68. This structural part is connected to each of the multiple conductors21in the corresponding stack STK on the cell region side, and to multiple conductors69corresponding to the respective conductors21in the select gate line hookup region.

The conductor21in each layer is formed below the associated conductor22and thicker in the Z direction than the conductor22.

The multiple conductors69are disposed at the same height as the respective, corresponding conductors21. The conductors69may contain, for example, a metal such as tungsten, molybdenum, or the like, and may be covered by a barrier metal such as titanium nitride, tungsten nitride, or the like.

The conductor65is provided at the center portion of the structural part forming the string STS and includes, for example, a portion of a cylindrical shape that extends along the Z direction. The conductor65has a lower end that is lower than the lower surface of the conductor21in the lowermost layer (the first layer), and an upper end that is higher than the upper surface of the conductor22in the uppermost layer. The conductor65may contain, for example, a metal such as tungsten, molybdenum, or the like, and may be covered by a barrier metal such as titanium nitride, tungsten nitride, or the like.

The semiconductor64surrounds the side surface and the lower surface of the conductor65and is electrically connected to the conductor65. The semiconductor64contains, for example, polysilicon containing an n-type impurity, and functions as a first end (a source or a drain) of each of the multiple select transistors ST in the string STS.

The semiconductor66is provided for each layer and disposed between the conductor21in the corresponding layer and the semiconductor64, so as to be electrically connected to the conductor21. The semiconductor66contains, for example, polysilicon containing an n-type impurity, and functions as a source or a drain of the select transistor ST in the corresponding layer.

The semiconductor62contains, for example, polysilicon containing a p-type impurity. The semiconductor62has first portions provided at the same heights as the respective members of the stack STK except the conductors21, and second portions provided at the same heights as the conductors21of the respective layers. The first and second portions of the semiconductor62are formed as a continuous film.

The first portions of the semiconductor62surround the side surface and the lower surface of the semiconductor64. The second portions of the semiconductor62each have portions62pprovided between the semiconductors66and64and physically connecting together the semiconductor66and the semiconductor64. The portions62pfunction as a channel of the select transistor ST in the corresponding layer. Note that there is no second portion of the semiconductor62between the conductor69and the semiconductor64in the corresponding layer (that is, the semiconductor62has openings such that the semiconductor62does not interrupt between each conductor69and the semiconductor64).

The insulator67is provided for each layer and covers the surfaces of the semiconductor64and the second portion of the semiconductor62at the same height as the conductor21in the corresponding layer. The insulator67contains, for example, silicon oxide and its portion provided along the portions62pof the semiconductor62functions as a gate insulating film for the select transistor ST in the corresponding layer.

The semiconductor68is provided for each layer and disposed between the insulator67and the conductor69in the corresponding layer, so as to cover the entire surface of each of the insulator67and the conductor69. The semiconductor68contains, for example, polysilicon containing an n-type impurity. The portion of the semiconductor68, provided along the respective portion62pof the semiconductor62via the insulator67, functions as a source or a drain of the select transistor ST in the corresponding layer.

As such, the insulator67is provided between [the semiconductor68and the conductor69] and [the semiconductors62,64, and66, and the conductors21and65].

The insulator61is provided for each layer and disposed on the side surface of the first portion of the semiconductor62at the same height as the conductor22in the corresponding layer. Each insulator61contains, for example, silicon oxide and electrically separates the associated conductor22and the semiconductor64from each other.

The conductor70is provided for each layer and extends along the Z direction from the upper portion of the conductor69of the corresponding layer. The conductor70thus serves as a contact CV for pulling out the respective select gate line SGL to be higher than the memory cell array10.

As in the above constitution, the multiple select transistors ST corresponding to the respective layers are formed within one string STS.

5.3 Method for Producing Memory Device

An example of a process for producing the memory cell array of the memory device according to the fifth embodiment will be described.FIGS.71to97each show an example of a sectional structure that includes a structural part corresponding particularly to the hookup regions for the memory cell array and that is formed in the course of the process for producing the memory device according to the fifth embodiment. Note that the sectional views which will be referred to for the production process include a cross-section vertical to the surface of the semiconductor substrate20. Also, regions indicated in each sectional view for the production process step correspond to the regions indicated inFIG.70.

First, a structure similar to that shown inFIG.5for the first embodiment, i.e., a structure that has been described as becoming the multiple stacks STK, is formed. Here, the sacrificial member42is formed with a thickness in the2direction greater than that of the sacrificial member44.

Subsequently, process steps similar to those explained with reference toFIGS.6to13for the first embodiment are performed.

As shown inFIG.71, in the select gate line hookup region, the insulator43and the sacrificial member44in the first layer and the insulator41and the sacrificial member42in the second layer are each formed to be shorter in the Y direction than the insulator41and the sacrificial member42in the first layer. Also, the insulator43and the sacrificial member44in the second layer and the uppermost insulator41are each formed to be shorter in the Y direction than the insulator43and the sacrificial member44in the first layer and the insulator41and the sacrificial member42in the second layer. Accordingly, a staircase-profile portion is formed in the select gate line hookup region. Note that the space above the staircase-profile portion is, for example, subjected to formation of an interlayer insulating film80.

FIG.72is a sectional view of the memory cell array10, taken along the line LXXII-LXXII indicated inFIG.71. As shown inFIG.72, the process steps have formed multiple structures MP in the cell region. The process steps have also formed multiple semiconductors34and35(not shown) in the cell region. Note that, as can be understood from the foregoing description, the structures INS extend along the Y direction up to the boundary between the bit line hookup region and the select gate line hookup region.

Next, as shown inFIG.73, a step of, for example, lithography and anisotropic etching is conducted to remove each region intended for forming the string STS from the stacked structure shown inFIG.71, so that holes CH are formed. Each hole CH penetrates through the lowermost insulator41and reaches the upper surface of the insulator40. The anisotropic etching in this process step may be, for example, RIE.

FIG.74is a sectional view of the memory cell array10, taken along the line LXXIV-LXXIV indicated inFIG.73. As shown inFIG.74, the process step has formed multiple holes CH each having, for example, a circular opening. One hole CH is provided at every interval between multiple structures INS arranged along the X direction.

Next, as shown inFIG.75, portions of the sacrificial members42and44, exposed via each hole CH formed as shown inFIG.73, are selectively removed by, for example, wet etching or dry etching. This forms, within the hole CH, recesses that expose the upper and lower surfaces of the insulators41and43at the heights corresponding to the sacrificial members42and44.

FIG.76is a sectional view of the memory cell array10, taken along the line LXXVI-LXXVI indicated inFIG.75. In this figure, as well as the remaining figures, a circle indicated by dashed-dotted lines within the hole CH represents the diameter of the opening in the insulator41or43. As shown inFIG.76, the recesses formed by this process step each have a diameter larger than the width between two consecutive structures INS arranged along the X direction. As such, the recesses formed in the respective holes CH by the process step separate the sacrificial members42and44into the portions42pand44pon the side of the cell region and the portions42qand44gon the side of the select gate line hookup region, with respect to the holes CH.

Next, as shown inFIG.77, an insulator61is formed in each hole CH having the recesses. This makes the insulator61fill the recesses at the heights corresponding to the sacrificial members44pand44q. On the other hand, since the sacrificial members42pand42qare thicker in the Z direction than the sacrificial members44pand44qas explained above, the recesses at the heights corresponding to the sacrificial members42pand42qeach have an opening size in the Z direction larger than that of the recesses at the heights corresponding to the sacrificial members44pand44q. Accordingly, the insulator61formed in the recesses at the heights corresponding to the sacrificial members42pand42qdoes not fill these recesses.

FIG.78is a sectional view of the memory cell array10, taken along the line LXXVIII-LXXVIII indicated inFIG.77. As shown inFIG.78, the insulator61does not fill each recess at the height corresponding to the associated sacrificial members42pand42q, even for the relatively shallow portions (that is, X-direction portions of the recess).

Next, as shown inFIG.79, portions of the insulator61formed in each hole CH are removed by, for example, wet etching or dry etching. More specifically, the insulator61is subjected to isotropic etching to the extent that its portions formed on the insulators41and43are removed. As explained above, the insulator61does not fill the recesses at the heights corresponding to the sacrificial members42pand42q, and the portions of the insulator61formed on the sacrificial members42pand42qeach have a thickness comparable with the thickness of the portions formed on the insulators41and43. Accordingly, the portions of the insulator61formed on the sacrificial members42pand42qare likewise removed. On the other hand, since the insulator61has filled the recesses at the heights corresponding to the sacrificial members44pand44q, portions of the insulator61formed on the sacrificial members44pand44qare not removed but remain there.

Next, as shown inFIG.80, a semiconductor62and a sacrificial member63are formed in this order within each hole CH. Similar to the insulator61formed as shown inFIG.77, the semiconductor62is formed in such a manner that it does not fill the recesses at the heights corresponding to the sacrificial members42pand42q. The sacrificial member63, however, is formed on the semiconductor62in such a manner as to fill these recesses. The sacrificial member63contains, for example, silicon nitride. The film formation in this process step may use, for example, LPCVD.

Note that portions62pof the semiconductor62in each layer, including a portion extending along the Y direction over the upper surface of the insulator41to reach the sacrificial member42pand a portion extending along the Y direction over the lower surface of the insulator43to reach the sacrificial member42p, will, in the final form, function as a channel of the select transistor ST.

FIG.81is a sectional view of the memory cell array10, taken along the line LXXXI-LXXXI indicated inFIG.80. In the example shown inFIG.81, each hole CH has substantially the same diameter at any of the heights of the insulators41and43and also the sacrificial members42p,42q,44p, and44q.

Next, as shown inFIG.82, a portion of the sacrificial member63in each hole CH is subjected to an etch-back step. This process step exposes the semiconductor62except for the portions at the heights corresponding to the sacrificial members42pand42q. The recesses at the heights corresponding to the sacrificial members42pand42qare still filled with the semiconductor62and the sacrificial member63.

FIG.83is a sectional view of the memory cell array10, taken along the line LXXXIII-LXXXIII indicated inFIG.82. In the example shown inFIG.83, each hole CH has substantially the same diameter at any of the heights of the insulators41and43and also the sacrificial members42p,42q,44p, and44q, as in the case shown inFIG.81.

Next, as shown inFIG.84, a semiconductor64and a conductors65are formed in this order within each hole CH, and the hole CH is thus filled. The film formation in this process step may use, for example, LPCVD or PCVD. Note that the portion of the semiconductor64in each layer, which is in contact with the respective portion62pof the semiconductor62, will, in the final form, function as a source or a drain of the select transistor ST.

FIG.85is a sectional view of the memory cell array10, taken along the line LXXXV-LXXXV indicated inFIG.84. As understood fromFIG.85, the semiconductor64includes, on its side surface, the part covered by the sacrificial member63in addition to the part where the portions62pof the semiconductor62are formed.

Next, as shown inFIG.86, and also inFIG.87which is a sectional view of the memory cell array10taken along the line LXXXVII-LXXVII indicated inFIG.86, the process step as in the first embodiment shown inFIG.14is performed. This removes the sacrificial members42pand44pfrom the cell region and the bit line hookup region, so that the surface of the semiconductor62on the side of the cell region is exposed in the space created by the removal of the respective sacrificial member42p, and the surface of the insulator61on the side of the cell region is exposed in the space created by the removal of the respective sacrificial member44p. Note that the sacrificial members42qand44qare each separate from the sacrificial members42pand44pas described above, the sacrificial members42qand44qremain unremoved by this process step.

Subsequently, the process step as in the first embodiment shown inFIG.15is performed. This forms a semiconductor66on the semiconductor62exposed in the space created by the removal of the respective sacrificial member42pin the bit line hookup region, while the semiconductors36to39are formed on the semiconductors34and35exposed in the spaces created by the removal of the sacrificial members42pand44pin the cell region.

Thereafter, as shown inFIG.88, and also inFIG.89which is a sectional view of the memory cell array10taken along the line LXXXIX-LXXXIX indicated inFIG.88, the process step as in the first embodiment shown inFIG.16is performed. This fills the spaces created by the removal of the sacrificial members42pand44pwith the conductors21and22, respectively. Accordingly, the conductor21and the conductor65are connected via the n-type impurity-containing semiconductor64, the p-type impurity-containing semiconductor62(portions62p), and the n-type impurity-containing semiconductor66.

Next, as can be seen fromFIG.90, one or more holes (not illustrated) penetrating through all the sacrificial members42qand44qstacked along the Z direction are formed to expose the sacrificial members42qand44q. The sacrificial members42qand44qare then selectively removed by wet etching or dry etching via the holes. Accordingly, the surface of the semiconductor62on the side of the gate line hookup region is exposed in the space created by the removal of the respective sacrificial member42q, and the surface of the insulator61on the side of the gate line hookup region is exposed in the space created by the removal of the respective sacrificial member44q.

Subsequently, further wet etching or dry etching is performed via said one or more holes (not illustrated) so that the surface portions of the semiconductor62that are exposed to the one or more holes are selectively removed. Accordingly, the associated sacrificial members63each covering the semiconductor64are exposed.

Then, the further wet etching or dry etching is carried on via said one or more holes so that the sacrificial members63are selectively removed. This exposes, in each layer, the two portions62pof the semiconductor62, i.e., the portion provided on the upper surface of the insulator41and the portion provided on the lower surface of the insulator43, and also the portion of the semiconductor62that is provided on the semiconductor66and connects these two portions62ptogether.

FIG.91is a sectional view of the memory cell array10, taken along the line XCI-XCI indicated inFIG.90. As shown inFIG.91, upon removal of the associated sacrificial member63, a space is created between the semiconductor64and the portion of the semiconductor62that is formed on the semiconductor66, and this space is continuous with the space created by the removal of the sacrificial member42g.

Next, as shown inFIG.92, insulators67are formed on the inner walls defining the spaces created by the removal of the sacrificial members42qand44q, the portions of the semiconductor62, and the sacrificial members63, via the one or more holes (not illustrated) used for creating these spaces. Accordingly, the insulators67cover the surfaces of the semiconductors62and64, the insulators41and43, and the interlayer insulating film80, which are exposed at the height corresponding to the respective conductor21, as well as the surfaces of the insulators41,43, and61, and the interlayer insulating film80, which are exposed at the height corresponding to the respective conductor22. The film formation in this process step may use, for example, LPCVD. Note that the portion of the semiconductors67, which is in contact with the portions62pof the semiconductor62, will, in the final form, function as a gate insulating film for the corresponding select transistor ST.

FIG.93is a sectional view of the memory cell array10, taken along the line XCIII-XCIII indicated inFIG.92. As shown inFIG.93, the insulators67are also formed on the end portions of the multiple structures INS arranged along the X direction, at the height corresponding to the conductor21. As such, for the multiple select transistors ST arranged along the X direction, the insulators67are formed as a continuous film.

Next, as shown inFIG.94, semiconductors68are formed on the entire surfaces of the exposed insulators67via the one or more holes (not illustrated) used for forming the insulators67. Accordingly, at least the portions of the insulators67which are formed on the portions62pof the semiconductor62are covered by the semiconductor68. The film formation in this process step may use, for example, LPCVD.

Subsequently, conductors69are formed on the exposed semiconductors68, at least for the portions on the side of the select gate line hookup region, via the one or more holes (not illustrated) used for forming the semiconductors68so that the spaces after the removal of the sacrificial members42qare filled. The film formation in this process step may use, for example, LPCVD or PCVD.

FIG.95is a sectional view of the memory cell array10, taken along the line XCV-XCV indicated inFIG.94. As shown inFIG.95, the semiconductors68are formed as a continuous film for the multiple select transistors ST arranged along the X direction, similar to the insulators67. Note that the example shown inFIG.95assumes a constitution where the semiconductor68formed on the insulator67on one side of the associated structure INS and the semiconductor68formed on the insulator67on the side of the conductor65join together, which has consequently closed the part of the space after the removal of the sacrificial member63on the side of the cell region with respect to the conductor65. Here, the conductor69is not formed in the closed spaces. However, the portion of the semiconductor68that sandwiches the insulator67with the respective portion62pof the semiconductor62is electrically connected to the conductor69, and therefore, can function as a gate of the select transistor ST.

Next, as shown inFIG.96, a hole is formed for each layer such that the hole penetrates through the interlayer insulating film80, the insulator67, and the semiconductor68to reach the corresponding conductor69, and the holes are each filled with a conductor70.

FIG.97is a sectional view of the memory cell array10, taken along the line XCVII-XCVII indicated inFIG.96. As shown inFIG.97, the conductor70extends along the Z direction within the interlayer insulating film80without interfering the conductor69of the upper layer, and thus, the select gate line SGL can be pulled out higher than the memory cell array10. Note that, since the conductor69has common connections to all the select transistors ST in one layer, providing one conductor70for each layer suffices.

The bit line hookup region and the select gate line hookup region are therefore formed. Thereafter, a step of forming conductors23and24in the cell region, a step of forming contacts to the conductors21and22and to various circuitry components formed in the insulator40, a heat treatment step, etc. are performed so that the memory cell array10is formed.

Note that the production process described above is only an example. It is possible to adopt modifications such as inserting other processes between the process steps and changing the order of the steps as long as a problem does not occur.

5.5 Effects of Embodiment

According to the fifth embodiment, a string STS includes one select transistor ST for each layer, and each of the select transistors ST is selected by a select gate line SGL provided for shared use in the respective layer. This can reduce the number of the bit line drivers131to the number equal to the number of memory cells arranged along the X direction. The number of memory cells arranged along the X direction does not depend on the number of memory cell transistors MT stacked in the Z direction (that is, the number of layers). Accordingly, the number of layers can be increased while suppressing the upsizing of the regions occupied by the bit line drivers131.

Together, the area occupied by the bit line drivers131, which is arranged below the memory cell array10, can be kept from exceeding the area occupied by the memory cell array10when viewed from above. Accordingly, increase in the area of the memory cell array10for preventing such an excess area can be avoided, and it is possible to obviate an unintended increase in the length of interconnects. This contributes to the prevention against increased resistance and capacitance, and consequently, the memory cell array10can be prevented from deteriorating its performance.

6. Others

The foregoing first to fifth embodiments tolerate various modifications.

For example, while the first to fifth embodiments have assumed the instances where the global word lines GWL are formed above the memory cell array10, this is not a limitation. As another example, the global word lines GWL may be formed in advance between the insulator40in which various circuitry components are formed and the memory cell array10, and then pulled upward using contacts. For such cases, each structure MP may be subjected to an etching step after the formation of the lamination film TCB and before the formation of the local word line LWL, so that the lower portion of the lamination film TCB is opened to expose the global word line GWL. The local word line LWL is then formed. Accordingly, the local word line LWL and the global word line GWL can be electrically connected together at the position below the structure MP.

Also, while the fifth embodiment has assumed the instances where the cell-region side part of the space created by the removal of the sacrificial member63is closed by the formation of the semiconductor68, this is not a limitation. This part of the space may be, for example, continuous with the space in the select gate line hookup region after the semiconductor68is formed. Also, the part may be filled with the conductor69by the subsequent step of forming the conductor69.

Moreover, while the fifth embodiment has assumed the instances where the structure to become the stack STK adopts a constitution similar to that described for the first embodiment, this is not a limitation. For example, the structure to become the stack STK may adopt a constitution similar to any of the second to fourth embodiments. Here, adopting the constitution of, in particular, the second embodiment involves sacrificial members46contained in the structure to become the stack STK, which is not preferable. To cope with this, one or more holes penetrating through all the sacrificial members46stacked in the bit line hookup region may be formed after providing the structure to become the stack STK and before starting the formation of the string STS. Then, the sacrificial members46are substituted by, for example, insulators containing silicon oxide, to the extent not affecting the cell region. Upon this processing, the process steps similar to those in the fifth embodiment can be conducted thereafter.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit.