Patent ID: 12259604

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “upper,” “on,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, although the terms such as “first,” “second” and “third” describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as “first,” “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the deviation normally found in the respective testing measurements. Also, as used herein, the terms “about,” “substantial” or “substantially” generally mean within 10%, 5%, 1% or 0.5% of a given value or range. Alternatively, the terms “about,” “substantial” or “substantially” mean within an acceptable standard error of the mean when considered by one of ordinary skill in the art. Other than in the operating/working examples, or unless otherwise expressly specified, all of the numerical ranges, amounts, values and percentages such as those for quantities of materials, durations of times, temperatures, operating conditions, ratios of amounts, and the likes thereof disclosed herein should be understood as modified in all instances by the terms “about,” “substantial” or “substantially.” Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and attached claims are approximations that can vary as desired. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges can be expressed herein as being from one endpoint to another endpoint or between two endpoints. All ranges disclosed herein are inclusive of the endpoints, unless specified otherwise.

According to embodiments of the present disclosure, an optical device and a method of fabricating an optical device are provided. Specifically, the optical device includes an optical modulator and a thermal tuning member in the vicinity of the optical modulator to manipulate optical properties of an optical signal within the optical modulator by way of a thermo-optical effect on refractive index. The optical device may be implemented with a silicon-based material due to the material's low transmission loss and compatibility with existing semiconductor fabrication operations.

FIG.1is a top view of a silicon-based optical device10in accordance with some embodiments of the present disclosure, andFIG.2is a cross-sectional view taken along a line A-A′ inFIG.1. In some embodiments, the silicon-based optical device10is part of an optical link used to transmit high-speed data with a modulated light beam, wherein the optical link is configured to transmit an electrically-modulated optical signal between two or more electrical devices. In some embodiments, the optical link including the silicon-based optical device10is incorporated into a semiconductor package and configured to convert electrical signals to optical signals, and vice versa, between interconnected electrical devices. The silicon-based optical device10includes a modulator100, an input waveguide110, an output waveguide120, and a thermal tuning member200used to adjust a temperature of the modulator100, thereby changing a wavelength of an optical signal within the modulator100.

In some embodiments, the modulator100is a ring modulator that includes a ring waveguide102. The input waveguide110and the output waveguide120are positioned on either side of the ring waveguide102. It should be noted that the ring modulator is described herein merely by way for example, and any other suitable type of modulator may alternatively be used. The modulator100has a resonant wavelength. For example, a value of the resonant wavelength of the ring modulator depends, among other parameters, on a length of a perimeter of the ring modulator. The resonant wavelength is given approximately by:

λi=2⁢π⁢rni
where r is a radius of the ring modulator, n is the optical waveguide's effective index, and i is an integer.

In addition, an effective refractive index may be approximated by:

n=n0+(dndT)⁢Δ⁢T
where n0is an effective index at an initial temperature T0, dn/dT is a rate of change of a refractive index at temperature T0, and ΔT is a net change in temperature T−T0.

The resonant wavelength of the modulator100may be changed by raising or lowering a temperature of the ring waveguide102. More particularly, the thermal tuning member200generates heat when a current is supplied. Therefore, when the current is supplied to the thermal tuning member200, the ring waveguide102of the modulator100is heated so that a refractive index of the ring waveguide102can be changed. Consequently, the resonant wavelength of the modulator100can be adjusted.

FIG.3is a top view of the thermal tuning member200, in accordance with some embodiments of the present disclosure. Referring toFIG.3, the thermal tuning member200, configured to generate heat sufficient to increase a temperature of the modulator100, includes a core202, a pair of grids204spaced apart from the core202, and a pair of neck portions206connecting the grids204to the core202. In some embodiments, the pair of grids204and the pair of neck portions206are arranged symmetrically, such that a symmetrical thermal distribution is obtained when a current is applied to the thermal tuning member200. The current supplied to the thermal tuning member200is conducted from one of the grids204to another of the grids204through the connected core202and neck portions206. In some embodiments, the core202, the pair of grids204, and the pair of neck portions206are integrally formed and have substantially a same thickness. In some embodiments, the thermal tuning member200comprises tungsten.

In some embodiments, each grid204includes a plurality of strips2042ato2042g, wherein the strips2042ato2042gare equally spaced and parallel to one another, and a connecting portion2044connecting the strips2042ato2042gto one of the neck portions206. In some embodiments, the pair of grids204are arranged on either side of the core202, and the strips2042ato2042gextend parallel to the neck portions206. Referring toFIGS.1to3, the strips2042ato2042gof each grid204are physically connected to a metal line300formed of a metal, e.g., copper, which has a melting temperature less than that of the thermal tuning member200, which may be formed of tungsten, for example.

Referring back toFIG.3, the core202may have a shape that follows a shape of the modulator100, and the core202is arranged to overlap the modulator100from a view above the thermal tuning member200. Therefore, there is a need for the core202to generate more heat and the strips2042to generate less heat when the current is supplied to the thermal tuning member200to accurately control the temperature and optimize a heating energy required for bringing the modulator100to a desired temperature.

Generally, a higher electrical resistance of a conductor correlates to more heat being generated as a current passes through the conductor. In addition, a cross-sectional area of the conductor is inversely proportional to its resistance. As described above, the core202, the grids204and the neck portions206have substantially the same thickness, so that the cross-sectional area of the core202, the strips2042ato2042gand the neck portions206are determined by their widths. In some embodiments, a ring of the core202has a first width W1, the neck portion206has a second width W2greater than the first width W1, and each of the strips2042ato2042ghas a third width W3greater than the second width W2to provide more efficient thermal tuning, as well as electrical stability (e.g., improve electromigration (EM) reliability). For example, the first width W1is between about 0.2 μm and about 0.7 μm, and the second width W2is between about 1 μm and about 2 μm.

In some embodiments, the strips2042ato2042gin each grid204have decreasing lengths from a center toward two sides. For example, when each grid204includes an odd number of the strips2042ato2042g, the central strip2042dhas a greatest length, and the strips2042aand2042gfarthest away from the central strip2042dhave a shortest length. The strips2042ato2042ghave a length ranging from about 10 μm to about 20 μm. The connecting portion2044includes a first segment2046and a second segment2048connected to one other. The central strip2042dand the strips2042a,2042band2042cdisposed at an upper side of the central strip2042dare connected to the first segment2046, and the central strip2042dand the strips2042e,2042fand2042gdisposed at a lower side of the central strip2042dare connected to the second segment2048.FIG.4is an enlarged view of an area A ofFIG.3. Referring toFIG.4, in some embodiments, an angle α between the first segment2046and the second segment2048may be an acute angle, an obtuse angle or a right angle. In some embodiments, an angle β between the first segment2046and the respective neck portion206is an obtuse angle, and an angle γ between the second segment2048and the respective neck portion206is also an obtuse angle.

As described above, the core202generates more heat and the strips2042ato2042ggenerate less heat, so that the heat in the core202may radiate to the strips2042ato2042gor conduct to the strips2042ato2042gthrough the neck portions206. Generally, radiation intensity is inversely proportional to a square of a distance, so that the heat radiated to the strips2042a,2042b,2042c,2042c,2042fand2042gdisposed at two sides of the central strip2042dis less than a heat radiated to the central strip2042d. As such, a heat conducted to the central strip2042dfrom the core202and through the respective neck portion206may be rapidly dissipated for preventing the metal lines300connecting the strips2042ato2042g(as shown inFIGS.1and2) from incurring electromigration. In some embodiments, each of the metal lines300is arranged perpendicular to the strips2042ato2042gbeing connected. In some embodiments, the core202of the thermal tuning member200is arranged directly over the ring waveguide102of the modulator100to achieve a desirable heating performance on the modulator100with uniform heat distribution while conducting as little heat as possible to other parts of the optical link or to metals in the semiconductor device10. In some embodiments, the core202of the thermal tuning member200substantially overlaps the ring waveguide102of the modulator100.

Referring toFIG.5, the thermal tuning member200aincludes a core202, a plurality of grids204spaced apart from the core202, and a pair of neck portions206connecting the plurality of grids204to the core202. The thermal tuning member200aincludes four grids204, and each neck portion206is configured to connect a pair of grids204to the core202. The grids204and the pair of neck portions206are arranged symmetrically, such that a symmetrical thermal distribution is obtained when a current is supplied to the thermal tuning member200a. In some embodiments, the current supplied to the thermal tuning member200ais conducted from an upper pair of the grids204to the neck portion206connected to the upper pair of the grids204, then to the core202, and finally to a lower pair of the grids204through another neck portion206. In some embodiments, the core202has a ring shape, and the neck portions206are disposed on either side of the core202.

Each grid204includes a plurality of strips2042ato2042gand a connecting portion2044connecting the strips2042ato2042gto the respective neck portion206. The strips2042ato2042gmay have decreasing lengths from a center toward two sides, so that when the grid204includes an odd number of the strips2042ato2042g, a central strip2042dcan have a greatest length. The connecting portion2044may include a first segment2046and a second segment2048; the first segment2046connects the central strip2042dand some of the strips2042a,2042band2042cdisposed at one side of the central strip2042d, and the second segment2048connects the central strip2042dand the strips2042e,2042f, and2042gdisposed at another side of the central strip2042d. One of the first and second segments2046and2048is arranged parallel to the neck portions206, and another of the first and second segments2046and2048is arranged perpendicular to the neck portions206.

Referring toFIG.6, a thermal tuning member200bincludes a core202, a pair of grids204spaced apart from the core202, and a pair of neck portions206connecting the pair of grids204to the core202. In some embodiments, the pair of grids204and the pair of neck portions206are arranged symmetrically, such that a symmetrical thermal distribution is obtained when a current is applied to the thermal tuning member200b. The current supplied to the thermal tuning member200bis conducted from one of the grids204(e.g., the left grid204) to the one of the neck portions206connected to the left grid204, then to the core202, and finally to the right grid204through another of the neck portions206. In some embodiments, the core202has a C shape, and the pair of neck portions206are connected to open ends of the C-shaped core202. In other words, the pair of grids204are arranged side-by-side.

In some embodiments, each grid204includes a plurality of strips2042ato2042gand a connecting portion2044connecting the strips2042ato2042gto the respective neck portion206. The strips2042ato2042gmay have decreasing lengths from a center toward two sides, so that when the grid204includes an odd number of the strips2042ato2042g, a central strip2042dcan have a greatest length. The connecting portion2044may include a first segment2046and a second segment2048; the first segment2046connects the central strip2042dand some of the strips2042a,2042band2042cdisposed at one side of the central strip2042, and the second segment2048connects the central strip2042dand the strips2042e,2042fand2042gdisposed at another side of the central strip2042d. One of the first and second segments2046and2048is arranged parallel to the neck portions206, and another of the first and second segments2046and2048is arranged perpendicular to the neck portions206.

FIG.7is a flow diagram illustrating a method500of fabricating a silicon-based optical device in accordance with some embodiments of the present disclosure, andFIGS.8to26illustrate intermediate stages in the formation of the silicon-based optical device in accordance with some embodiments of the present disclosure. The stages shown inFIGS.8to26are also illustrated schematically in the flow diagram inFIG.7. In the subsequent discussion, the fabrication stages shown inFIGS.8to26are discussed in reference to operation steps shown inFIG.7. Additional steps can be provided before, during, and after the stages shown inFIGS.8to26, and some steps described below can be replaced or eliminated in other embodiments of the method500. An order of the steps may be interchangeable. Some of the steps may be performed concurrently or independently.

Referring toFIG.8, a substrate210is received or provided according to a step S502inFIG.7. The substrate210includes silicon. In some embodiments, the substrate210is a silicon-on-insulator (SOI) substrate in which a silicon wafer212, an insulating layer214and a silicon layer216are formed. The insulating layer214, for example, includes silicon oxide, silicon nitride or other suitable dielectric materials. In some embodiments, the insulating layer214may have a first thickness T1of about 2 μm, and the silicon layer216may have a second thickness T2of about 220 nm.

Referring toFIGS.9and10, the silicon layer216is etched to form one or more optical components218according to a step S504inFIG.7. In some embodiments, at least one photolithography operation is used to earmark regions where the optical components218are to be formed, and one or more etching operations are applied to remove portions of the silicon layer216, leaving the earmarked regions in place to thereby form the optical components218. For the etching of the silicon layer216, a reactive ion etching operation may, for example, be applied. The optical components218may include, from left to right, a strip waveguide, a rib waveguide, and a ring waveguide for formation of a modulator, as described below.

Referring toFIG.11, according to a step S506inFIG.7, a protection layer230is formed over the substrate210to surround the optical components218. The protection layer230, including oxide, may be formed by any acceptable deposition operation, such as a chemical vapor deposition (CVD) operation or a high-density plasma (HDP) CVD operation. After the deposition operation is performed, the protection layer230may cover the insulating layer214and the optical components218. Accordingly, an additional planarization operation, such as a chemical mechanical polishing (CMP) operation or a grind operation, may be performed, so as to obtain the structure shown inFIG.11, in which a top surface of the protection layer230is planarized and top surfaces220S of the optical components218are exposed through the protection layer230.

Referring toFIG.12, according to a step S508inFIG.7, implantation operations are performed to introduce impurities into the optical components218, as part of formation of the modulator222. The modulator222may include a first region224ahaving a first conductivity type (e.g., n-type) and a second region224babutting the respective first region224aand having a second conductivity type (e.g., p-type) different from the first conductivity type. In some embodiments, the modulator222is formed in separate processing sequences that include, for example, masking the second region224band the other optical components218when implanting n-type impurities into the first region224aand masking the first region224aand the other optical components218when implanting p-type impurities into the second region224b. A PN junction may thus be formed within the modulator222. N-type impurity concentrations of the first region224aandp-type impurity concentrations of second region224bmay be set at substantially same levels. In some embodiments, an anneal operation (such as a rapid thermal annealing (RTA) operation) may be performed to repair implantation damage and to activate the p-type and n-type impurities that were implanted.

In order to form a low-resistance contact with the first region224aand the second region224bof the modulator222, an n+ region226aand a p+ region226bare formed in the first region224aand the second region224b, respectively. It can be seen that the n+ region226ais formed on a top part of the first region224aexcept for a region where the PN junction is located, and the p+ region226bis formed on a top part of the second region224bexcept for the region where the PN junction is located. The n+ region226ahas an impurity concentration greater than that of the first region224aand the p+ region226bhas an impurity concentration greater than that of the second region224b. In some embodiments, the n+ region226aand the p+ region226bare formed in separate processing sequences that include, for example, masking the optical components218while excluding a portion of the n+ region226aspaced apart from the PN junction when implanting n-type impurities into the portion of the first region224a, and masking the optical components218while excluding a portion of the second region224bspaced apart from the PN junction when implanting p-type impurities into the second region224b. In some embodiments, an anneal operation may be performed to activate the p-type and n-type impurities that were implanted in the n+ region226aand the p+ region226b.

Referring toFIG.13, a dielectric film240is formed on the protection layer230and the optical components218including the modulator222according to a step S510inFIG.7. The dielectric film240, including oxide, may be formed by a CVD operation or other suitable methods. After the formation of the dielectric film240, the dielectric film240may be planarized, using, for example, a CMP operation, to yield an acceptably flat topology.

After the formation of the dielectric film240, a first patterned mask410is provided on the dielectric film240. In some embodiments, photosensitive material is applied to fully cover the dielectric film240by a spin-coating operation and then dried using a soft-baking operation, and the first patterned mask410is formed by performing an exposure operation and a develop operation on the photosensitive material. It can be seen inFIG.13that a plurality of first openings412are provided in the first patterned mask410above the n+ region226aand the p+ region226b.

Following the formation of the first patterned mask410, an etching operation is conducted to remove portions of the dielectric film240exposed through the first patterned mask410, as shown inFIG.14. Accordingly, a plurality of through holes242for exposing the n+ region226aand the p+ region226bare formed. In some embodiments, an anisotropic etching operation can be performed to etch portions of the dielectric film240that are not masked by the first patterned mask410. The first patterned mask410is then removed using, for example, an ashing operation or a wet strip operation.

Referring toFIGS.15and16, a plurality of electrodes252are formed at top portions of the n+ region226aand the p+ region226baccording to a step S512inFIG.7. As shown inFIG.15, a metal layer250is formed at least on the n+ region226aand the p+ region226b. In some embodiments, the metal layer250is deposited across the dielectric film240conforming to a surface topography of the etched dielectric film240and the n+ region226aand the p+ region226bexposed through the openings242in the dielectric film240(as shown inFIG.14). The metal layer250can include, and/or can consist essentially of, at least one metal that can form a metal silicide material. For example, the metal layer250can include nickel.

In some embodiments, a thermal anneal operation can be performed at an elevated temperature to cause a reaction between the metal layer250and a semiconductor material of the modulator222. After the anneal operation, a plurality of metal-semiconductor alloy portions are formed. The metal-semiconductor alloy portions act as electrodes of the modulator222. The reacted portions of the metal layer250and a silicon material of the modulator222form the electrodes252, as shown inFIG.16. Unreacted portions of the metal layer250can be subsequently removed. For example, the unreacted portion of the metal layer250can be etched selectively to metal-semiconductor alloy portions using a wet etching operation.

Referring toFIG.17, a contact etch stop layer (CESL)260and an interlayer dielectric (ILD) layer270are successively formed over the dielectric film240and the electrodes252of the modulator222according to a step S514inFIG.7. The CESL260may comprise one or more layers of silicon oxide or silicon nitride-based materials such as SiN, SiCN, SiON or SiOCN. The CESL260may be formed by a CVD operation, a physical vapor deposition (PVD) operation, an atomic layer deposition (ALD) operation and/or other suitable methods. The ILD layer270, disposed on the CESL260, may include SiO2, SiN, SiON, SiOCN, fluorine-doped silicate glass (FSG), or a low-K dielectric material, and may be formed by CVD or other suitable operations. A CMP operation may follow the forming of the ILD layer270to remove excessive dielectric material, and thereby provide a substantially planar top surface.

FIG.17further illustrates an anti-reflective coating (ARC) layer280and a second patterned mask420over the ILD layer270. The ARC layer280is disposed on the ILD layer270. Anti-reflective coating may improve photo resolution by reducing optical distortions associated with specular reflections, thin-film interference, and/or standing waves that may inhibit sharp feature definition during imaging of the photoresist material. In the illustrated example, the ARC layer280may include SiON. The ARC layer280may be formed by any suitable deposition technique, e.g., CVD, PECVD, ALD, PEALD. PVD, spin-coating or the like, or a combination thereof. The second patterned mask420includes a second opening422above the modulator222. The second patterned mask420may be formed by steps including: conformally coating a photosensitive material on the ARC layer280, exposing portions of the photosensitive material to radiation (not shown), and developing the photosensitive material, thereby forming the second opening422defining a pattern for etching of the ARC layer280and the ILD layer270.

Referring toFIG.18, one or more etching operations are performed to form a trench272in the ILD layer270according to a step S516inFIG.7. The one or more etching operations are performed in order to remove portions of the ARC layer280not masked by the second patterned mask420, and portions of the ILD layer270exposed after removing the unmasked portions of the ARC layer280, thus forming the trench272above the modulator222for formation of a thermal tuning member, as described below. Portions of the ARC layer280and the ILD layer270are removed using one etching operation. The etching operation utilizes multiple etchants, selected based on materials of the ARC layer280and the ILD layer270, to sequentially etch the ARC layer280and the ILD layer270. The etching operation is conducted until the ILD layer270is etched to a selected depth D. In some embodiments, the selected depth D is between about 1000 Å and about 4000 Å. After the formation of the trench272, the second patterned mask420is removed by an acceptable ashing or stripping operation.

Subsequently, a blanket layer of photosensitive material is formed on the ARC layer280and etched portions of the ILD layer270and the ARC layer280. The blanket layer of the photosensitive material is then patterned to provide a third patterned mask430(as shown inFIG.19) having a plurality of third openings432utilizing a lithographic operation that may include exposing the photosensitive material to a pattern of radiation and developing the exposed photosensitive material utilizing a developer. The third openings432are disposed above the electrodes252of the modulator222.

Still referring toFIG.19, at least one etching operation is performed to remove portions of the ARC layer280, the ILD layer270and the CESL260not protected by the third patterned mask430according to step S518inFIG.7. Consequently, a plurality of contact holes274are formed, and portions of the electrodes252are exposed. The contact holes274, penetrating through the ARC layer280, the ILD layer270and the CESL260, can be formed using an etching operation utilizing multiple etchants, selected based on materials of the CESL260, the ILD layer270, and the ARC layer280, to sequentially etch the ARC layer280, the ILD layer270and the CESL260until the electrodes252are exposed. After the contact holes274are formed, the third patterned mask430is removed using, for example, an ashing operation or a wet strip operation.

Referring toFIG.20, a first metallic material290is deposited in the trench272and the contact holes274, according to a step S520inFIG.7. The first metallic material290is uniformly deposited on the electrodes252of the modulator222and the ARC layer280until the trench272and the contact holes274are entirely filled. The first metallic material290may comprise tungsten. The first metallic material290may be deposited using a CVD operation.

Next, a planarizing operation is performed to remove the first metallic material290and the ARC layer280. Consequently, the thermal tuning member292and a plurality of metal plugs294, as shown inFIG.21, are formed. After the removal of the superfluous first metallic material290and the ARC layer280, the ILD layer270is exposed. The thermal tuning member292in the ILD layer270may have a structure as shown inFIGS.3,5and6.

Referring toFIG.22toFIG.26, a back-end-line (BEOL) layer300is formed over the ILD layer270, the thermal tuning member292and the conductive plugs294according to a step S522inFIG.7. The BEOL layer300includes a plurality of layers comprising an insulative layer310and a plurality of metallization layers320stacked within the insulative layer310. The BEOL layer300is formed utilizing a cyclic operation comprising a sequence of depositing a dielectric layer and forming metallization lines penetrating through the dielectric layer.

Referring toFIG.22, a first dielectric layer310a, including oxide, is formed using a CVD operation. After the formation of the first dielectric layer310a, a planarization operation may be performed to provide the first dielectric layer310awith a substantially planar top surface. Next, a fourth patterned mask440, including a plurality of fourth openings442, is provided on the first dielectric layer310a. The openings442may be formed in the fourth patterned mask440using lithography operations.

Next, an etching operation is performed to remove portions of the first dielectric layer310anot protected by the fourth patterned mask440. After the etching operation, a plurality of holes penetrating through the first dielectric layer310aare formed, and portions of the thermal tuning member292and the plugs294are exposed through the holes312a, as shown inFIG.23.

Subsequently, a second metallic material314a(as shown inFIG.24) is formed over the first dielectric layer310a, the thermal tuning member292and the plugs294. In some embodiments, the formation of the second metallic material314aincludes filling the holes312awith the second metallic material314a, and the filling of the holes312amay include a plating operation. In some embodiments, after the plating operation is performed, the second metallic material314amay overflow the holes312aand cover a top surface of the first dielectric layer310a; accordingly, an additional planarization may be performed to remove an overflow portion of the second metallic material314a. As shown inFIG.25, first metallization lines320aare thus formed to couple to the thermal tuning member292and the conductive plugs294. In some embodiments, after the formation of the first metallization lines320a, a series of metal damascene processes used to form other metallization lines coupled to the first metallization lines320aare performed until the BEOL layer300are completely formed.

In accordance with some embodiments of the present disclosure, a method of fabricating an optical device comprises steps of: receiving a substrate; forming a silicon-based optical component in the substrate; depositing an interlayer dielectric (ILD) layer on the substrate and the silicon-based optical component; forming a thermal tuning member comprising a first metallic material in the ILD layer, wherein the thermal tuning member comprises a core above the silicon-based optical component, a plurality of grids spaced apart from the core, and a pair of neck portions connecting the plurality of grids to the core, wherein a width of a strip in each of the plurality of grids is greater than a width of the core; forming at least one conductive plug comprising the first metallic material penetrating through the ILD layer and coupled to the silicon-based optical component; forming a dielectric layer over the thermal tuning member and the conductive plug; and forming a plurality of conductive lines comprising a second metallic material coupled to the thermal tuning member.

In accordance with some embodiments of the present disclosure, a method of fabricating a thermal tuning member for a silicon-based optical component is provided. The method comprises steps of: forming a core above the silicon-based optical component; forming a pair of neck portions connected to the core; forming a plurality of strips adjacent to the pair of neck portions, the plurality of strips being equally spaced and parallel to one another; and forming a plurality of connecting portions to connect the strips to the pair of neck portions.

In accordance with some embodiments of the present disclosure, a silicon-based optical device includes: a silicon-on-insulator (SOI) substrate; at least one optical component formed within the SOI substrate; a thermal tuning member disposed over the optical components and comprising a core, a pair of neck portions connected to the core, and a plurality of grids connected to the pair of neck portions, wherein the plurality of grids each comprises a plurality of strips equally spaced and parallel to one another; and a connecting portion connecting the plurality of strips to the pair of neck portions.

The foregoing outlines structures of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.