Patent ID: 12189830

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG.1is a block diagram illustrating an integrated circuit10according to an exemplary embodiment of the inventive concept. The integrated circuit10for security of a physically unclonable function (PUF) may generate a security key KEY requested to be secured as illustrated inFIG.1. As illustrated inFIG.1, the integrated circuit10may include a plurality of PUF blocks11_1,11_2, . . . , and11_n, a multiplexer (MUX)12, a selection signal generator13, and a key generator14. In some embodiments of the inventive concept, the integrated circuit10may be manufactured through a semiconductor process and components of the integrated circuit10may be packaged in a single package or two or more packages.

Referring toFIG.1, the plurality of PUF blocks11_1,11_2, . . . , and11_nmay generate a plurality of output signals OUT1, OUT2, . . . , and OUTn, respectively, (n is an integer greater than 1). In some embodiments of the inventive concept, the plurality of PUF blocks11_1,11_2, . . . , and11_nmay be designed by logic synthesis and may be implemented as digital logics. For example, the plurality of PUF blocks11_1,11_2, . . . , and11_nmay be designed with reference to a standard cell library that defines various logic gates and may respectively include instances of the same logic gate to have the same structure.

Each of the plurality of PUF blocks11_1,11_2, . . . , and11_nmay include a plurality of PUF cells. For example, as illustrated inFIG.1, the PUF block11_1may include the plurality of PUF cells C1, . . . , and Ck (k is an integer greater than 1) and accordingly, the integrated circuit10may include n*k PUF cells. The plurality of PUF cells C1, . . . , and Ck may generate a plurality of cell signals CS1, . . . , and CSk having unique values, respectively. As described later with reference toFIGS.2A and2B, the PUF cell (for example, C1) may include a plurality of PUF units for respectively outputting signals having unique levels. Accordingly, the cell signal (for example, CS1) output by the PUF cell (for example, C1) may have a unique value due to various variations that occur in a process of manufacturing the integrated circuit10. For example, elements (for example, transistors) and/or patterns included in the plurality of PUF cells C1, . . . , and Ck may have unique characteristics different from those of a plurality of PUF cells of another integrated circuit manufactured by the same semiconductor process due to variations such as a height, a width, a length, and a doping concentration. Therefore, the plurality of cell signals CS1, . . . , and CSk may have unique values, respectively, and may be used for generating the security key KEY.

Security of an operation of obtaining the plurality of cell signals CS1, . . . , and CSk from the plurality of PUF cells C1, . . . , and Ck, in other words, an operation of reading each of the unique values of the plurality of cell signals CS1, . . . , and CSk (also referred to as an operation of reading the plurality of PUF cells C1, . . . , and Ck) may be needed. For example, in a side-channel attack (SCA), there may be an attempt to obtain the plurality of cell signals CS1, . . . , and CSk and/or the security key KEY by using a response to power consumption that occurs in the integrated circuit10, an electromagnetic field, or an intentionally applied fault or by using machine learning based on various parameters measured by the integrated circuit10. Therefore, the plurality of cell signals CS1, . . . , and CSk having high entropy and low predictability and which are an effective countermeasure against the SCA (also referred to as an attack) may be requested in a process of reading the plurality of PUF cells C1, . . . , and Ck. As described hereinafter, the integrated circuit according to exemplary embodiments of the inventive concept may increase the security of the PUF by reducing the predictability of the operation of reading the plurality of PUF cells C1, . . . , and Ck.

As illustrated inFIG.1, the plurality of PUF blocks11_1,11_2, . . . , and11_nmay commonly receive a first selection signal SEL1from the selection signal generator13and one of the plurality of PUF cells may be selected in response to the first selection signal SEL1. For example, one of the plurality of PUF cells C1, . . . , and Ck of the PUF block11_1may be selected in response to the first selection signal SEL1and a first output signal OUT1corresponding to a cell signal output by the selected PUF cell may be generated. Therefore, the plurality of PUF blocks11_1,11_2, . . . , and11_nmay simultaneously generate a plurality of output signals OUT1, OUT2, . . . , and OUTn, respectively, and power consumptions of the plurality of PUF blocks11_1,11_2, . . . , and11_nmay be equal regardless of the first selection signal SEL1. As a result, predictability of the power consumptions of the plurality of PUF blocks11_1,11_2, . . . , and11_nmay be reduced. An example of a PUF block will be described later with reference toFIGS.3and4.

In some embodiments of inventive concept, the plurality of PUF blocks11_1,11_2, . . . , and11_nmay be divided into two or more groups, and each of the two or more groups has the same number of PUF blocks. The selection signal generator13may provide the two or more groups with additional selection signals respectively to enable one of the two or more groups, and PUF blocks included in an enabled group may generate output signals. For example, when the integrated circuit10may include four PUF blocks, i.e., n=4, the four PUF blocks may be divided into a first group including two PUF blocks11_1and11_2and a second group including another two PUF blocks. The second selection signal SEL2may select each of the two PUF blocks11_1and11_2sequentially when the first group is enabled by the selection signal generator13. Similarly, the second selection signal SEL2may select each of the another two PUF blocks sequentially when the second group is enabled by the selection signal generator13. Therefore, two PUF blocks among the four PUF blocks may generate output signals and power is always consumed by two PUF blocks. As a result, predictability of the power consumptions of the plurality of PUF blocks11_1,11_2, . . . , and11_nmay be reduced.

The multiplexer12may receive the plurality of output signals OUT1, OUT2, . . . , and OUTn from the plurality of PUF blocks11_1,11_2, . . . , and11_n, respectively, and may provide a PUF signal PUF corresponding to one of the plurality of output signals OUT1, OUT2, . . . , and OUTn to the key generator14in accordance with a second selection signal SEL2received from the selection signal generator13. The multiplexer12may have an arbitrary structure for selecting one of the plurality of output signals OUT1, OUT2, . . . , and OUTn in response to the second selection signal SEL2. The inventive concept is not limited thereto.

The selection signal generator13may generate the first selection signal SEL1and the second selection signal SEL2. In some embodiments of the inventive concept, the selection signal generator13may generate the first selection signal SEL1and the second selection signal SEL2to select all of the n*k PUF cells included in the plurality of PUF blocks11_1,11_2, . . . , and11_n. The selection signal generator13may generate the first selection signal SEL1so that the plurality of PUF cells C1, . . . , and Ck included in the PUF block (for example,11_1) are selected one by one with nothing omitted. For example, the selection signal generator13may generate the first selection signal SEL1so that the plurality of PUF cells C1, . . . , and Ck are sequentially selected. In addition, the selection signal generator13may generate the second selection signal SEL2so that the plurality of PUF blocks11_1,11_2, . . . , and11_nare selected one by one with nothing omitted.

In some embodiments of the inventive concept, the selection signal generator13may generate the first selection signal SEL1and/or the second selection signal SEL2to reduce the predictability of an operation of reading a PUF cell. For example, the selection signal generator13may select the plurality of PUF cells C1, . . . , and Ck with nothing omitted at differently delayed points in time. Therefore, the predictability of the operation of reading the PUF cell may be reduced. An example of the selection signal generator13will be described later with reference toFIG.10.

The key generator14may receive the PUF signal PUF from the multiplexer12and may generate the security key KEY based on the PUF signal PUF. In some embodiments of the inventive concept, the key generator14may repeatedly receive the PUF signal PUF and may collect values of the PUF signal PUF corresponding to different PUF cells. The key generator14may generate the security key KEY by performing an arbitrary method, for example, modular arithmetic on the collected values of the PUF signal PUF.

FIGS.2A and2Bare block diagrams illustrating physical unclonable function (PUF) cells20aand20b, respectively, according to exemplary embodiments of the inventive concept. As described above with reference toFIG.1, each of the PUF cells20aand20bofFIGS.2A and2Bmay include a PUF unit for generating a signal at a unique level. Hereinafter,FIGS.2A and2Bwill be described with reference toFIG.1and descriptions of the same components as those inFIG.1will not be given.

Referring toFIG.2A, the PUF cell20amay include a plurality of PUF units20a_1, and20a_wand each of the plurality of PUF units20a_1, . . . , and20a_wmay generate a bit of a cell signal CS. In some embodiments of the inventive concept, the PUF unit may include two or more logic gates and may generate a signal at a unique level based on a difference between threshold levels of the two or more logic gates. For example, as illustrated inFIG.2A, the PUF unit20a_1may include a first inverter G21aand a second inverter G22aof the same structure and the first inverter G21amay have its input connected to its output. Therefore, a voltage of a node N20amay have a first threshold level of the first inverter G21a, in other words, a voltage level corresponding to a boundary at which the first inverter G21adistinguishes a low level (e.g., “0”) from a high level (e.g., “1”). The second inverter G22amay output a first bit CS[1] of the cell signal CS, which has a level dependent on a second threshold level of the second inverter G22aand the first threshold level of the first inverter G21a. A value, in other words, a voltage level of the first bit CS[1] of the cell signal CS, may be dependent on a difference between the first threshold level and the second threshold level. InFIG.2A, it is illustrated that the PUF unit20a_1includes the first inverter G21aand the second inverter G22a. However, in some embodiments of the inventive concept, the PUF unit may further include additional inverters subsequent to the second inverter G22aand the additional inverters may amplify a voltage level of the node N20ato a low level or a high level by propagating the voltage level of the node N20a.

In addition, the first inverter G21amay consume power caused by the first threshold level, and the second inverter G22amay consume power caused by the difference between the first threshold level and the second threshold level. For example, when the difference between the first threshold level and the second threshold level is small, the second inverter G22amay consume power close to that of the first inverter G21adue to a high current that passes through an electrical path formed between a positive supply voltage and a negative supply voltage (or a ground voltage). On the other hand, when the difference between the first threshold level and the second threshold level is large, the second inverter G22amay consume low power due to a low current that passes through the electrical path formed between the positive supply voltage and the negative supply voltage. For example, the second inverter G22amay consume power dependent on an absolute value of the difference between the first threshold level and the second threshold level.

As described above, since the power consumed by the second inverter G22adepends on an absolute value of the difference between the threshold levels of the logic gates, resistivity against the SCA may be enhanced. For example, when a threshold level of the PUF unit20a_1is higher than the first threshold level of the first inverter G21aand the second threshold level of the second inverter G22a, the second inverter G22amay recognize the voltage of the node N20aas having a high level. Accordingly, the first bit CS[1] of the cell signal CS may have a low level. On the other hand, when the first threshold level is lower than the second threshold level, the second inverter G22amay recognize the voltage of the node N20aas having a low level. Accordingly, the first bit CS[1] of the cell signal CS may have a high level. In the two cases just described, when the absolute values of the differences between the first threshold level and the second threshold level are equal, powers consumed by the second inverter G22amay be the same. Therefore, the same power consumption may be measured in the both cases. However, in the both cases, the cell signal CS may have different values. As a result, resistivity against the SCA may be enhanced.

Referring toFIG.2B, the PUF cell20bmay include a plurality of PUF units20b_1,20b_2, . . . , and20b_wand each of the plurality of PUF units20b_1,20b_2, . . . , and20b_wmay include two NAND gates. For example, as illustrated inFIG.2B, the PUF unit20b_l may include a first NAND gate G21band a second NAND gate G22bhaving the same structure. The first NAND gate G21bmay have its input A connected to its output.

In comparison with the PUF cell20aofFIG.2A, the PUF cell20bofFIG.2Bmay receive one bit SEL1[x] of the first selection signal SEL1. For example, as illustrated inFIG.2B, each of the first NAND gate G21band the second NAND gate G22bmay have an input B that receives the bit SEL1[x] of the first selection signal SEL1. Therefore, when the bit SEL1[x] of the first selection signal SEL1has a low level, in other words, when the PUF cell20bis not selected, the first bit CS[1] of the cell signal CS may have a high level. On the other hand, when the bit SEL1[x] of the first selection signal SEL1has a high level, in other words, when the PUF cell20bis selected, the node N20bmay have the first threshold level of the first NAND gate G21band the first bit CS[1] of the cell signal CS may have a level dependent on a difference between the first threshold level and a second threshold level of the second NAND gate G22b.

When the PUF block (for example,11_1ofFIG.1) includes the PUF cell20aofFIG.2A, the PUF block may include a circuit (for example, a multiplexer) for selecting one of the plurality of cell signals CS1, . . . , and CSk in response to the first selection signal SEL1. On the other hand, when the PUF block includes the PUF cell20bofFIG.2B, a non-selected PUF cell, in other words, a PUF cell that receives one bit of the first selection signal SEL1having a low level, may output a cell signal having a certain level, and thus, the PUF block may include a logic circuit (for example,321ofFIG.3) independent from the first selection signal SEL1. Hereinafter, exemplary embodiments of the inventive concept will be described with reference to the PUF cell that receives one bit of the first selection signal SEL1as illustrated inFIG.2B. However, the inventive concept is not limited thereto. In addition, hereinafter, it is assumed that the cell signal output by the PUF cell has the number w of bits (w is an integer greater than 1) as illustrated inFIGS.2A and2B.

FIG.3is a block diagram illustrating the PUF block ofFIG.1according to an exemplary embodiment of the inventive concept. As described above with reference toFIG.1, a PUF block300ofFIG.3may receive the first selection signal SEL1and may generate an output signal OUT corresponding to the cell signal of the PUF cell selected, in response to the first selection signal SEL1, from among the plurality of PUF cells C1, C2, . . . , and Ck. As illustrated inFIG.3, the PUF block300may include the plurality of PUF cells C1, C2, . . . , and Ck and a selector320. Hereinafter,FIG.3will be described with reference toFIG.1.

The selector320may receive the plurality of cell signals CS1, CS2, . . . , and CSk from the plurality of PUF cells C1, C2, . . . , and Ck, respectively, and may generate a sampled non-inverted cell signal pCSS and a sampled inverted cell signal nCSS as output signals OUT. In other words, the output signals OUT may include the sampled non-inverted cell signal pCSS and the sampled inverted cell signal nCSS. As illustrated inFIG.3, the selector320may include a combination circuit321, a first converting circuit322, a second converting circuit323, and a sampling circuit324.

The combination circuit321may receive the plurality of cell signals CS1, CS2, . . . , and CSk and may output the selected cell signal CS0. As described above with reference toFIG.2B, since the PUF cell that is not selected by the first selection signal SEL1may generate a cell signal having a previously defined level, the combination circuit321may generate the cell signal CS0selected as a signal dependent on the cell signal output by the PUF cell selected by the first selection signal SEL1. For example, when each of the plurality of PUF cells C1, C2, . . . , and Ck includes the PUF unit20b_1ofFIG.2B, non-selected PUF cells may generate high level cell signals. In this case, the combination circuit321may perform an AND operation or a NAND operation on the plurality of cell signals CS1, CS2, . . . , and CSk and may generate the selected cell signal CS0dependent on the cell signal of the selected PUF cell.

The first converting circuit322and the second converting circuit323may have the same structure and may both receive the selected cell signal CS0. The first converting circuit322may generate a non-inverted cell signal pCS by not inverting the selected cell signal CS0and the second converting circuit323may generate an inverted cell signal nCS by inverting the selected cell signal CS0. Therefore, power consumed by a subsequent sampling circuit324as well as by the first converting circuit322and the second converting circuit323may be uniformly maintained and independent from a value of the selected cell signal CS0.

The first converting circuit322and the second converting circuit323may also make hamming weight uniform. The hamming weight may refer to the number of different symbols from a zero symbol and may refer to the number of ‘1’s in a multi-bit signal. The SCA may use the hamming weight as well as the power consumption and the total hamming weight of the non-inverted cell signal pCS and the inverted cell signal nCS may be uniformly maintained as the number w of bits of the cell signal. An example of the first converting circuit322and the second converting circuit323will be described in detail with reference toFIG.4.

The sampling circuit324may generate the sampled non-inverted cell signal pCSS and the sampled inverted cell signal nCSS by sampling the non-inverted cell signal pCS and the inverted cell signal nCS in response to a sampling signal SAM. In some embodiments of the inventive concept, the sampling signal SAM may be provided from the selection signal generator13ofFIG.1. In some embodiments of the inventive concept, the sampling circuit324may include at least one flip-flop for receiving the sampling signal SAM as a clock signal and receiving the non-inverted cell signal pCS or the inverted cell signal nCS as a data input. In addition, in some embodiments of the inventive concept, the sampling circuit324may be omitted and the non-inverted cell signal pCS and the inverted cell signal nCS may be used as the output signals OUT.

FIG.4is a block diagram illustrating the first converting circuit322and the second converting circuit323ofFIG.3according to an exemplary embodiment of the inventive concept. As described above with reference toFIG.3, a first converting circuit322′ ofFIG.4may generate the non-inverted cell signal pCS by not inverting the selected cell signal CS0and a second converting circuit323′ may generate the inverted cell signal nCS by inverting the selected cell signal CS0. Hereinafter,FIG.4will be described with reference toFIG.3.

In some embodiments of the inventive concept, the first converting circuit322and the second converting circuit323ofFIG.3may include XOR gates, respectively. For example, as illustrated inFIG.4, the first converting circuit322′ may include a first XOR gate G41having an input A that receives “0” (e.g., a low level) and an input B that receives the selected cell signal CS0, the second converting circuit323′ may include a second XOR gate G42having an input A that receives “1” (e.g., a high level) and an input B that receives the selected cell signal CS0, and the first XOR gate G41and the second XOR gate G42may process multi-bit signals, respectively. Therefore, the non-inverted cell signal pCS may have the same value as the selected cell signal CS0and the inverted cell signal nCS may have a value obtained by inverting the value of the selected cell signal CS0.FIG.4illustrates only an example of the first converting circuit322and the second converting circuit323ofFIG.3. In some embodiments of the inventive concept, the first converting circuit322and the second converting circuit323ofFIG.3may have the same structure in which the selected cell signal CS0is not inverted and inverted.

FIG.5is a block diagram illustrating an integrated circuit50according to an exemplary embodiment of the inventive concept. Like the integrated circuit10ofFIG.1, the integrated circuit50ofFIG.5may include a plurality of PUF blocks51_1,51_2, . . . , and51_n, a multiplexer (MUX)52, a selection signal generator53, and a key generator54. The integrated circuit50ofFIG.5may further include an attack detector55. Hereinafter, it is assumed that each of the plurality of PUF blocks51_1,51_2, . . . , and51_nhas the same structure as that of the PUF block300ofFIG.3. Therefore,FIG.5will be described with reference toFIG.3. In addition, descriptions of the same components as those inFIG.3will not be given.

The plurality of PUF blocks51_1,51_2, . . . , and51_nmay generate the plurality of output signals OUT1, OUT2, . . . , and OUTn, respectively, and each of the plurality of PUF blocks51_1,51_2, . . . , and51_nmay include the plurality of PUF cells C1, C2, . . . , and Ck. As described above with reference toFIG.3, the first output signal OUT1output by one PUF block, for example, the PUF block51_1, may include the sampled non-inverted cell signal pCSS and the sampled inverted cell signal nCSS. The selection signal generator53may generate the first selection signal SEL1and the second selection signal SEL2. The multiplexer52may output a non-inverted PUF signal pPUF and an inverted PUF signal nPUF as PUF signals by selecting one of the plurality of output signals OUT1, OUT2, . . . , and OUTn in response to the second selection signal SEL2.

The attack detector55may detect an attack from the outside, for example, a fault insertion attack, based on a comparison between the non-inverted PUF signal pPUF and the inverted PUF signal nPUF. For example, when the non-inverted PUF signal pPUF and the inverted PUF signal nPUF include bits having the same value, the attack detector55may determine that the attack occurs. In other words, as described with reference toFIG.3, due to the first converting circuit322and the second converting circuit323included in the PUF block300, in a normal case, the non-inverted PUF signal pPUF and the inverted PUF signal nPUF may have inverted values from each other. However, when the attack is attempted, a value of at least one bit may change until the non-inverted PUF signal pPUF and the inverted PUF signal nPUF are generated. The attack detector55may detect the attack by detecting a change in bit value. When the attack is detected, the attack detector55may generate an activated error signal ERR and may provide the error signal ERR to the key generator54. As a result, the first converting circuit322and the second converting circuit323may both be used to enhance resistivity against the attack as well as detect the attack.

The key generator54may receive the non-inverted PUF signal pPUF and may generate the security key KEY based on the non-inverted PUF signal pPUF. In some embodiments of the inventive concept, unlike inFIG.5, the key generator54may receive the inverted PUF signal nPUF and may generate the security key KEY based on the inverted PUF signal nPUF. The key generator54may receive the error signal ERR from the attack detector55and, when the activated error signal ERR is received, in other words, when the attack against the integrated circuit50is detected, the key generator54may not generate the security key KEY or may generate a void security key KEY to provide an error in response to the attack.

FIG.6is a flowchart illustrating a method of detecting an attack against a PUF, according to an exemplary embodiment of the inventive concept. In some embodiments of the inventive concept, the method ofFIG.6may be performed by the attack detector55ofFIG.5. Hereinafter,FIG.6will be described with reference toFIG.5.

In operation S62, an operation of obtaining a first signal and a second signal may be performed. The first signal and the second signal may have inverted values from each other in a normal case, for example, when an attack does not occur. In other words, the first signal and the second signal may have different values from each other in the normal case. For example, the first signal may correspond to the non-inverted PUF signal pPUF ofFIG.5and the second signal may correspond to the inverted PUF signal nPUF ofFIG.5. The attack detector55may receive the non-inverted PUF signal pPUF and the inverted PUF signal nPUF from the multiplexer52.

In operation. S64, an operation of comparing the first signal to the second signal may be performed. In some embodiments of the inventive concept, an operation of determining whether a signal obtained by inverting the first signal coincides with the second signal may be performed. For example, the attack detector55may perform an XOR operation on corresponding bits of the non-inverted PUF signal pPUF and the inverted PUF signal nPUF and may determine whether a bit having a low level (e.g., “0”) exists in a result of the XOR operation. As illustrated inFIG.6, when the signal obtained by inverting the first signal coincides with the second signal (YES), the method ofFIG.6may be terminated and the error signal ERR may be maintained to be in an inactive state. On the other hand, when the signal obtained by inverting the first signal is different from the second signal (NO), operation S66may be subsequently performed.

In operation S66, an operation of determining that the attack occurs may be performed. Since a value of at least one bit is changed due to the attack, the occurrence of the attack may be detected. For example, the attack detector55may provide the activated error signal ERR to the key generator54in response to the occurrence of the attack.

FIG.7is a block diagram illustrating an integrated circuit70according to an exemplary embodiment of the inventive concept.FIGS.8A and8Bare views illustrating the validity table76ofFIG.7according to exemplary embodiments of the inventive concept. Like the integrated circuit50ofFIG.5, the integrated circuit70ofFIG.7may include a plurality of PUF blocks71_1,71_2, . . . , and71_n, a multiplexer (MUX)72, a selection signal generator73, a key generator74, and an attack detector75. The integrated circuit70may further include a validity table76. Hereinafter, descriptions of the same components as those inFIG.1or5will not be given.

Referring toFIG.7, the plurality of PUF blocks71_1,71_2, . . . , and71_nmay generate the plurality of output signals OUT1, OUT2, . . . , and OUTn, respectively, and each of the plurality of PUF blocks71_1,71_2, . . . , and71_nmay include the plurality of PUP cells C1, C2, . . . , and Ck. The selection signal generator73may generate the first selection signal SEL1and the second selection signal SEL2. The multiplexer72may output the PUF signals including the non-inverted PUF signal pPUF and the inverted PUF signal nPUF by selecting one of the plurality of output signals OUT1, OUT2, . . . , and OUTn in response to the second selection signal SEL2.

The validity table76may include information that represents whether the PUF cells included in the integrated circuit70are stable PUF cells or unstable PUF cells, in other words, stability information. For example, when each of the plurality of PUF cells C1, C2, . . . , and Ck included in the PUF block71_1has the same structure as the PUF cell20aofFIG.2A, a PUF unit including the first inverter G21aand the second inverter G22awith a large difference between threshold levels may always generate a signal having a fixed (or stable) level, and a PUF unit including the first inverter G21aand the second inverter G22awith a difference approximately 0 between threshold levels may generate a signal having a varying (or unstable) level. In the current specification, among the PUF cells, a cell that always generates a cell signal having a fixed value may be referred to as a stable PUF cell and a cell that generates a cell signal having a varying value may be referred to as an unstable PUF cell.

Referring toFIG.8A, in some embodiments of the inventive concept, a validity table80amay include information that represents whether the PUF cell is the stable PUF cell or the unstable PUF cell. For example, while the first PUF cell C1of the first PUF block1is the stable PUF cell as indicated by “1” in the validity table80a, the kth PUF cell Ck of the second PUF block2may be the unstable PUF cell as indicated by “0” in the validity table80a. InFIG.8A, the kth PUF cell Ck of the second PUF block2as the unstable PUF cell may include at least one PUF unit for outputting a signal having an unstable level.

Referring toFIG.8B, in some embodiments of the inventive concept, a validity table80bmay include information that represents whether a PUF unit included in the PUF cell is a stable PUF unit or an unstable PUF unit. For example, while a first PUF unit U1included in the first PUF cell C1of the first PUF block1is a stable PUF unit as indicated by “1” in the validity table80b, the first PUF unit U1included in the kth PUF cell Ck of the second PUF block2may be an unstable PUF unit as indicated by “0” in the validity table80b. In the current specification, in exemplary embodiments of the inventive concept, the validity table80aofFIG.8Aincluding the stability information that represents whether the PUF cell is the stable PUF cell or the unstable PUF cell will be mainly described. However, the inventive concept is not limited thereto.

Referring toFIG.7again, in some embodiments of the inventive concept, the stability information may be stored in the validity table76in a process of manufacturing the integrated circuit70. For example, the process of manufacturing the integrated circuit70may include an enrolment process. In the enrolment process, each of the cell signals of the plurality of PUF cells included in the integrated circuit70may be tested. In accordance with the test result, it may be determined whether each of the plurality of PUF cells is the stable PUF cell or the unstable PUF cell. In accordance with the determination result, the stability information may be stored in the validity table80a. In some embodiments of the inventive concept, as a non-limiting example, the validity table76may include a non-volatile memory such as an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistance random access memory (RRAM), a nano-floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), or a ferroelectric random access memory (FRAM). In addition, in some embodiments of the inventive concept, the validity table76may include an irreversibly programmable memory.

The attack detector75may receive the non-inverted PUF signal pPUF and the inverted PUF signal nPUF and may refer to the validity table76to detect the attack. For example, as illustrated inFIG.7, the validity table76may receive the first selection signal SEL1and the second selection signal SEL2and may provide the stability information INFO of the PUF cells corresponding to the first selection signal SEL1and the second selection signal SEL2to the attack detector75. When the occurrence of the attack is detected, the attack detector75may provide the activated error signal ERR to the key generator74. An example of the operation of the attack detector75will be described later with reference toFIG.9.

FIG.9is a flowchart illustrating a method of detecting an attack against a PUF according to an exemplary embodiment of the inventive concept. In some embodiments of the inventive concept, the method ofFIG.9may be performed by the attack detector75ofFIG.7. Hereinafter,FIG.9will be described with reference toFIG.7. Descriptions of the same steps as those inFIG.6will not be given.

In operation S91, an operation of obtaining the first signal and the second signal may be performed. As described above with reference toFIG.6, the first signal may correspond to the non-inverted PUF signal pPUF ofFIG.7and the second signal may correspond to the inverted PUF signal nPUF ofFIG.7. The attack detector75may receive the non-inverted PUF signal pPUF and the inverted PUF signal nPUF from the multiplexer72.

In operation S93, an operation of comparing the first signal with the second signal may be performed. In some embodiments of the inventive concept, an operation of determining whether the signal obtained by inverting the first signal coincides with the second signal may be performed. As illustrated inFIG.9, when the signal obtained by inverting the first signal coincides with the second signal (YES), the method ofFIG.9may be terminated and the error signal ERR may be maintained to be in the inactive state. On the other hand, when the signal obtained by inverting the first signal is different from the second signal (NO), operation S95may be subsequently performed.

In operation S95, an operation of obtaining the stability information of the PUF cells may be performed. For example, the validity table76may include the stability information of the PUF cells included in the integrated circuit70and may provide the stability information INFO of the PUF cells corresponding to the non-inverted PUF signal pPUF and the inverted PUF signal nPUF to the attack detector75in response to the first selection signal SEL1and the second selection signal SEL2.

In operation S97, an operation of determining whether the PUF cells are the unstable PUF cells may be performed. For example, since the PUF cells correspond to the non-inverted PUF signal pPUF and the inverted PUF signal nPUF, the attack detector75may determine whether the PUF cells are the unstable PUF cells based on the stability information obtained in operation S95. As illustrated inFIG.9, when the PUF cells are the unstable PUF cells (YES), the method ofFIG.9may be terminated. In other words, it may be determined that in operation S93the signal obtained by inverting the first signal is different from the second signal due to instability of the PUF cells. Therefore, the method ofFIG.9may be terminated and the error signal ERR may be kept in the inactive state. On the other hand, when the PUF cells are not the unstable PUF cells (NO), in other words, when the PUF cells are the stable PUF cells, operation S99may be subsequently performed.

In operation S99, an operation of determining that the attack occurs may be performed. When it is determined in operation S93that at least one bit value changes and it is determined in operation S97that the PUF cells are the stable PUF cells, it may be interpreted that the at least one bit value changes due to the attack. Therefore, it may be determined in operation S99that the attack occurs and the attack detector75may provide the activated error signal ERR to the key generator74in response to the occurrence of the attack.

FIG.10is a block diagram illustrating a selection signal generator100according to an exemplary embodiment of the inventive concept.FIG.11is a timing diagram illustrating an operation of the selection signal generator100ofFIG.10according to an exemplary embodiment of the inventive concept. For example,FIG.10illustrates an example in which the selection signal generator100generates the first selection signal SEL1for selecting one of the plurality of PUF cells from each of the plurality of PUF blocks. The selection signal generator100ofFIG.10may be an example of the above-described selection signal generators. In addition,FIG.11illustrates an example in which a PUF block includes four PUF cells (e.g., k=4) and the first selection signal SEL1is generated to select one of the four PUF cells. Hereinafter,FIGS.10and11will be described with reference toFIG.1.

Referring toFIG.10, the selection signal generator100may receive a seed SED and may generate the first selection signal SEL1. The selection signal generator100may include a sequence generator101, an encoder102, a counter103, and a comparator104.

The sequence generator101may receive the seed SED and may generate a sequence SEQ that changes in accordance with the seed SED. For example, as illustrated inFIG.11, the sequence generator101may repeatedly generate a sequence SEQ of “5-2-1-4-3”. In some embodiments of the inventive concept, the sequence generator101may generate a sequence SEQ that starts from a value determined based on the seed SED among values “5-2-1-4-3”. In addition, in some embodiments of the inventive concept, the sequence generator101may generate a sequence SEQ in which the order of the values changes based on the seed SED. The seed SED may have low predictability like a random number and may be generated by a varying method. Examples of generating the seed SED will be described later with reference toFIGS.13A and13B.

The encoder102may receive the sequence SEQ from the sequence generator101and may generate the first selection signal SEL1by encoding the sequence SEQ. In some embodiments of the inventive concept, the encoder102may generate the first selection signal SEL1by one-hot encoding or one-cold encoding the value of the sequence SEQ. For example, as illustrated inFIG.11, the encoder102may one-hot encode the value of the sequence SEQ and may generate the first selection signal SEL1of 5 bits. Therefore, a PUF cell corresponding to the bit having a value “1” among the bits of the first selection signal SEL1may be selected. For example, at time t11to t12, the second PUF cell C2may be selected from each of the plurality of PUF blocks11_1,11_2, . . . , and11_nin accordance with the first selection signal SEL1of “00010” and accordingly, the plurality of PUF blocks11_1,11_2, . . . , and11_nmay output the plurality of output signals OUT1, OUT2, . . . , and OUTn having values “CS12, CS22, . . . , and CSn2”, respectively, corresponding to cell signals generated by the second PUF cell C2. In addition, at time t15to t16, none of the four PUF cells may be selected in accordance with the first selection signal SEL1of “10000” and the plurality of output signals OUT1, OUT2, . . . , and OUTn may have void values N/A. The void values N/A of the plurality of output signals OUT1, OUT2, . . . , and OUTn may enhance resistivity against the attack and accordingly, in some embodiments of the inventive concept, a period of the sequence SEQ may be determined to be greater than the number of PUF cells.

The counter103may output a count signal CNT counted in accordance with a comparison signal CMP provided by the comparator104. The comparator104may compare the sequence SEQ provided by the sequence generator101with the count signal CNT provided by the counter103and, when the value of the sequence SEQ coincides with the value of the count signal CNT, may generate the activated comparison signal CMP. For example, as illustrated inFIG.11, at time t11to t13, while the counter103outputs a count signal CNT having a value “1”, the sequence generator101may output a sequence SEQ sequentially having values “5-2-1”. Therefore, at time t12, the value of the sequence SEQ may coincide with the value of the count signal CNT and the comparison signal CMP may be activated, for example, the comparison signal CMP may be transited to a high level. In response to the activated comparison signal CMP, the counter103may increase the count signal CNT and accordingly, from the time t13, the count signal CNT may have a value “2”.

The comparison signal CMP may determine a point in time at which a PUF cell is selected, in other words, a point in time at which a cell signal output by the PUF cell is selected. For example, as illustrated inFIG.11, in the time t12to the time t13, the plurality of output signals OUT1, OUT2, . . . , and OUTn having the values “CS11, CS21, . . . , and CSn1” corresponding to the cell signals generated by the plurality of first PUF cells may be output in accordance with the activated comparison signal CMP and, due to the second selection signal SEL2having a value “1”, “CS11”, which is the value of the first output signal OUT1output by the PUF block11_1, may be output as a PUF signal PUF. Similarly, at time t16to t17, the PUF signal PUF may have the value “CS12” corresponding to the cell signal generated by the second PUF cell of the PUF block11_1. As the second selection signal SEL2sequentially increases from 1 to n, the PUF signal PUF may have a value “CSn3” corresponding to the cell signal generated by the third PUF cell of the nth PUF block11_nat time t21to t22and may have a value “CSn4” corresponding to the cell signal generated by the fourth PUF cell of the nth PUF block11_nat time t25. Therefore, the PUF cells included in the integrated circuit10may be sequentially read. In some embodiments of the inventive concept, the comparison signal CMP may be provided to the key generator14.

In some embodiments of the inventive concept, the second selection signal SEL2may be generated based on the count signal CNT. For example, inFIG.11, when the count signal CNT has a value 4, which is the number of PUF cells included in one PUF block, and the comparison signal CMP is activated, the second selection signal SEL2may increase and n, which is the number of PUF blocks11_1,11_2, . . . , and11_n, may also increase.

As described above, the comparison signal CMP may be non-periodically (or randomly) activated due to the values of the sequence SEQ and, when the seed SED changes, points in time at which the comparison signal CMP is activated may change. Therefore, it is possible to prevent the value of the PUF signal PUF used for generating the security key KEY from being exposed and to enhance resistivity against the attack.

FIG.12is a flowchart illustrating a method of reading PUF cells according to an exemplary embodiment of the inventive concept. In some embodiments of the inventive concept, the method ofFIG.12may be performed by the selection signal generator13ofFIG.1. Hereinafter,FIG.12will be described with reference toFIG.1.

Referring toFIG.12, in operation S121, an operation of setting a variable i as 1 may be performed. The variable i may correspond to an index that indicates one of the plurality of PUF blocks11_1,11_2, . . . , and11_n(1≤i≤n). Next, in operation S122, an operation of setting a variable j as 1 may be performed. The variable j may correspond to an index that indicates one of the plurality of PUF cells C1, . . . , and Ck included in each of the plurality of PUF blocks11_1,11_2, . . . , and11_n(1≤j≤k).

In operation S123, an operation of selecting an ith PUF block11_imay be performed. For example, the selection signal generator13may generate the second selection signal SEL2and accordingly, an output signal OUT1is output by the ith PUF block11_ias the PUF signal PUF. Next, in operation S124, an operation of selecting a jth PUF cell Cj at a point in time randomly delayed may be performed. For example, the selection signal generator13may generate the first selection signal SEL1for selecting the jth PUF cell Cj at the randomly delayed point in time.

In operation S125, an operation of comparing the variable j with the number k of PUF cells included in one PUF block may be performed. When the variable j does not coincide with k, in other words, when a PUF cell that is not selected exists in the ith PUF block11_i, in operation S126, an operation of increasing the variable j may be performed and then, operation S124may be performed. On the other hand, when the variable j coincides with k, in other words, when there is no PUF cell that is not selected in the ith PUF block11_i, operation S127may be subsequently performed.

In operation S127, an operation of comparing the variable i with the number n of PUF blocks included in the integrated circuit10may be performed. When the variable i does not coincide with n, in other words, when a non-selected PUF block exists, in operation S128, an operation of increasing the variable i may be performed and then, operation S122may be performed. On the other hand, when the variable i coincides with n, in other words, when there is no PUF block that is not selected, the method ofFIG.12may be terminated.

FIGS.13A and13Bare block diagrams illustrating examples in which seeds are generated according to exemplary embodiments of the inventive concept. As described above with reference toFIG.10, the seed SED may change a method, performed by selection signal generators131aand131bofFIGS.13A and13B, of generating the first selection signal SEL1and/or the second selection signal SEL2. As a result, the plurality of PUF cells may be differently (for example, at changed points in time) selected in accordance with the seed SED. Hereinafter, descriptions of the same components as those inFIG.10will not be given.

Referring toFIG.13A, the seed SED may be generated by a random number generator132a. The random number generator132amay generate a random number and may provide the seed SED having a value of the random number or a value obtained by processing the random number to the selection signal generator131a. The random number generator132amay generate the random number by a varying method. In some embodiments of the inventive concept, the random number generator132amay include a true random number generator (TRNG) and/or a pseudo random number generator (PRNG).

Referring toFIG.13B, the seed SED may be generated based on cell signals CSs generated by the PUF cells. As described above with reference toFIGS.7,8A, and8B, a plurality of PUF blocks132bmay include unstable PUF cells as well as stable PUF cells and accordingly, values of the cell signals CSs may be unstable. As illustrated inFIG.13B, the cell signals CSs generated by at least parts of the PUF cells included in the plurality of PUF blocks132bmay be provided to a compress circuit133b.

The compress circuit133bmay generate the seed SED based on the cell signals CSs. To increase entropy of the seed SED, the number of PUF cells that provide the cell signals CSs may be large. Therefore, the compress circuit133bmay generate the seed SED dependent on the cell signals CSs by compressing the cell signals CSs. In some embodiments of the inventive concept, the compress circuit133bmay generate the seed SED by performing an XOR operation on the cell signals CSs and may provide the generated seed SED to the selection signal generator131b. Since the seed SED is generated based on instability of the PUF cells, the PUF cells may be used for increasing resistivity against the attack as well as performing a PUF.

FIG.14is a block diagram illustrating an integrated circuit140according to an exemplary embodiment of the inventive concept. Like the integrated circuit10ofFIG.1, the integrated circuit140ofFIG.14may include a plurality of PUF blocks141_1,141_2, . . . , and141_n, a multiplexer (MUX)142, a selection signal generator143, and a key generator144. Descriptions of the same components as those inFIG.1will not be given.

Referring toFIG.14, the plurality of PUF blocks141_1,141_2, . . . , and141_nmay generate the plurality of output signals OUT1, OUT2, . . . , and OUTn, respectively, and each of the plurality of PUF blocks141_1,141_2, . . . , and141_nmay include the plurality of PUF cells C1, C2, . . . , and Ck. The selection signal generator143may generate the first selection signal SEL1and the second selection signal SEL2. The multiplexer142may output the PUF signals PUF by selecting one of the plurality of output signals OUT1, OUT2, . . . , and OUTn in response to the second selection signal SEL2.

In some embodiments of the inventive concept, the selection signal generator143may generate a permutation signal PER and may provide the generated permutation signal PER to the key generator144. As described above, the selection signal generator143may generate the first selection signal SEL1and the second selection signal SEL2so that the n*k PUF cells included in the plurality of PUF blocks141_1,141_2, . . . , and141_nare selected one by one with nothing omitted. In the example ofFIG.14, the selection signal generator143may change the order in which the n*k PUF cells are selected. In other words, the selection signal generator143may generate a permutation of the n*k PUF cells and may generate the first selection signal SEL1and the second selection signal SEL2so that the n*k PUF cells are selected in accordance with the permutation. The key generator144may receive the permutation signal PER that represents the permutation generated by the selection signal generator143to recognize the PUF cells corresponding to the PUF signals PUF. In some embodiments of the inventive concept, as illustrated inFIG.14, the selection signal generator143may generate the permutation based on the seed SED. An example of the operation of the selection signal generator143will be described later with reference toFIG.15.

FIG.15is a flowchart illustrating a method of reading PUF cells, according to an exemplary embodiment of the inventive concept. In some embodiments of the inventive concept, the method ofFIG.15may be performed by the selection signal generator143ofFIG.14. Hereinafter,FIG.15will be described with reference toFIG.14.

Referring toFIG.15, in operation S152, an operation of generating the permutation of the plurality of PUF cells based on the seed SED may be performed. For example, the selection signal generator143may generate the permutation to select the n*k PUF cells one by one with nothing omitted and to change the order in which the n*k PUF cells are selected. The permutation may be generated based on the seed SED and the order in which the n*k PUF cells are selected may change due to the permutation that changes in accordance with the seed SED. In addition, the selection signal generator143may provide the permutation signal PER that represents the generated permutation to the key generator144. In some embodiments of the inventive concept, the selection signal generator143may generate the permutation for some of the n*k PUF cells. For example, the selection signal generator143may generate the permutation for the k PUF cells included in one PUF block and may generate the permutation for the n PUF blocks.

In operation S154, an operation of sequentially selecting the plurality of PUF cells in accordance with the permutation may be performed. For example, the selection signal generator143may generate the first selection signal SEL1and the second selection signal SEL2to sequentially select the plurality of PUF cells in accordance with the permutation. In some embodiments of the inventive concept, when the selection signal generator143generates the permutation for the k PUF cells included in one PUF block, the selection signal generator143may generate the first selection signal SEL1in accordance with the generated permutation. In addition, in some embodiments of the inventive concept, when the selection signal generator143generates the permutation for the n PUF blocks, the second selection signal SEL2may be generated in accordance with the generated permutation.

FIGS.16A to16Care block diagrams of a device including an integrated circuit for security of a PUF according to an exemplary embodiment of the inventive concept. As described above, the integrated circuit may include the PUF cells that increase resistivity against the attack and may have a structure in which the predictability of the operation of reading the PUF cells deteriorates. In identification devices160a,160b, and160cofFIGS.16A to16C, the integrated circuits according to the exemplary embodiments of the inventive concept may be included as PUF integrated circuits (IC)161a,161b, and161c, respectively. In addition, components included in the identification devices160a,160b, and160cmay be implemented as independent integrated circuits, respectively. At least two of the components included in each of the identification devices160a,160b, and160cmay be implemented as one integrated circuit.

Referring toFIG.16A, the identification device160amay include the PUF IC161aand a communication interface162a. The identification device160amay transmit a response RES including identification information of the identification device160ato the outside in response to a request REQ received from the outside. For example, the identification device160amay be a radio frequency identification (RFID) device and the identification information included in the response RES may be used to identify a user of the identification device160a. The identification information included in the response RES may be generated based on the security key KEY generated by the PUF IC161a.

Referring toFIG.16B, the identification device160bmay include the PUF IC161b, an encryption engine162b, and a memory163b. The identification device160bmay store data DATA received from the outside or may transmit the stored data DATA to the outside. The encryption engine162bmay encrypt the data DATA received from the outside by using the security key KEY, generated by the PUF IC161bfor security of the stored data and may store encrypted data ENC in the memory163b. In addition, the encryption engine162bmay decode the encrypted data ENC read from the memory163bby using the security key KEY and may transmit the decoded data DATA to the outside. InFIG.16B, the decoded data read from the memory163bis represented as DEC. For example, the identification device160bmay be a portable storage device or a storage device of a storage server.

Referring toFIG.16C, the identification device160cmay include the PUF IC161c, a public key generator162c, and a modem163c. The identification device160cmay communicate with another communication device by receiving a signal RX from the another communication device or transmitting a signal TX to the another communication device. The public key generator162cmay generate a public key P_KEY based on the security key KEY generated by the PUF IC161c. The modem163cmay transmit the encrypted signal TX or may decrypt the signal RX based on the public key P_KEY. In other words, the identification device160cmay perform a secure communication with another communication device based on the security key KEY. For example, the identification device160cmay be a portable wireless communication device.

Exemplary embodiments of the inventive concept provide an integrated circuit for security of a PUF and a device including the same. More particularly exemplary embodiments of the inventive concept provide an integrated circuit for providing an effective countermeasure against various SCAs against the PUF and a device including the same.

While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made thereto without departing from the spirit and scope of the inventive concept as defined by the following claims.