Patent ID: 12255100

DETAILED DESCRIPTION

In the following description, many thicknesses and materials are described for various layers and structures within an integrated circuit die. Specific dimensions and materials are given by way of example for various embodiments. Those of skill in the art will recognize, in light of the present disclosure, that other dimensions and materials can be used in many cases without departing from the scope of the present disclosure.

The following disclosure provides many different embodiments, or examples, for implementing different features of the described subject matter. Specific examples of components and arrangements are described below to simplify the present description. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In the following description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the disclosure. However, one skilled in the art will understand that the disclosure may be practiced without these specific details. In other instances, well-known structures associated with electronic components and fabrication techniques have not been described in detail to avoid unnecessarily obscuring the descriptions of the embodiments of the present disclosure.

Unless the context requires otherwise, throughout the specification and claims that follow, the word “comprise” and variations thereof, such as “comprises” and “comprising,” are to be construed in an open, inclusive sense, that is, as “including, but not limited to.”

The use of ordinals such as first, second and third does not necessarily imply a ranked sense of order, but rather may only distinguish between multiple instances of an act or structure.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least some embodiments. Thus, the appearances of the phrases “in one embodiment”, “in an embodiment”, or “in some embodiments” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the content clearly dictates otherwise. It should also be noted that the term “or” is generally employed in its sense including “and/or” unless the content clearly dictates otherwise.

Embodiments of the present disclosure provide an integrated circuit including nanostructure transistors each having a plurality of semiconductor nanostructures corresponding to channel regions of the transistor. Embodiments of the present disclosure provide improved gate metal layer formation for transistors having different threshold voltages. In particular, an inter-sheet filler layer is formed between the semiconductor nanostructures of two transistors. The inter-sheet filler layer is completely removed from between the semiconductor nanostructures of the first transistor prior to deposition of a first gate metal. The inter-sheet filler layer is removed from the sides, but not from between the semiconductor nanostructures of the second type of transistor. The first gate metal layer is then deposited. The first gate metal layer fills the gaps between the semiconductor nanostructures of the first type of transistor. The first gate metal layer is prevented by the inter-sheet filler layer from filling the gaps between the semiconductor nanostructures of the second type of transistor. Because the first gate metal layer never enters the gaps between semiconductor nanostructures of the second transistor, the semiconductor nanostructures of the second transistor are not exposed to a prolonged etching process to entirely remove the first gate metal from between the semiconductor nanostructures. The result is that gate dielectric materials of the second transistor are not eroded by the etching process. Furthermore, the first and second transistors have more distinct threshold voltages. The performance of the transistors and overall wafer yields are improved.

FIGS.1A-1Lare perspective views of an integrated circuit100at successive intermediate stages of processing, according to some embodiments.FIGS.1A-1Lillustrate an exemplary process for producing an integrated circuit that includes nanostructure transistors.FIGS.1A-1Lillustrate how these transistors can be formed in a simple and effective process in accordance with principles of the present disclosure. Other process steps and combinations of process steps can be utilized without departing from the scope of the present disclosure. The nanostructure transistors can include gate all around transistors, multi-bridge transistors, nanosheet transistors, nanowire transistors, or other types of nanostructure transistors.

The nanostructure transistor structures may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the nanostructure transistor structure.

InFIG.1Athe integrated circuit100includes a semiconductor substrate102. In some embodiments, the substrate102includes a single crystalline semiconductor layer on at least a surface portion. The substrate102may include a single crystalline semiconductor material such as, but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb and InP. In the example process described herein, the substrate102includes Si, though other semiconductor materials can be utilized without departing from the scope of the present disclosure.

The substrate102may include in its surface region, one or more buffer layers (not shown). The buffer layers can serve to gradually change the lattice constant from that of the substrate to that of the source/drain regions. The buffer layers may be formed from epitaxially grown single crystalline semiconductor materials such as, but not limited to Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. The substrate102may include various regions that have been suitably doped with impurities (e.g., p-type or n-type conductivity). The dopants are, for example boron (BF2) for an n-type transistor and phosphorus for a p-type transistor.

The integrated circuit100includes a plurality of semiconductor nanostructures104. The semiconductor nanostructures104are layers of semiconductor material. The semiconductor nanostructures104correspond to the channel regions of the nanostructure transistors that will result from the process described. The semiconductor nanostructures104are formed over the substrate102. The semiconductor nanostructures104may include one or more layers of Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb or InP. In some embodiments, the semiconductor nanostructures104are the same semiconductor material as the substrate102. Other semiconductor materials can be utilized for the semiconductor nanostructures104without departing from the scope of the present disclosure. In a non-limiting example described herein, the semiconductor nanostructures104and the substrate102are silicon. The nanostructures104can include nanosheets, nanowires, or other types of suitable structures or shapes for acting as channel regions of a nanostructure transistor.

The integrated circuit100includes a plurality of sacrificial semiconductor nanostructures106positioned between the semiconductor nanostructures104. The sacrificial semiconductor nanostructures106include a different semiconductor material than the semiconductor nanostructures104. In an example in which the semiconductor nanostructures104include silicon, the sacrificial semiconductor nanostructures106may include SiGe.

In some embodiments, the semiconductor nanostructures104and the sacrificial semiconductor nanostructures106are formed by alternating epitaxial growth processes from the semiconductor substrate102. Alternating epitaxial growth processes are performed until a selected number of semiconductor nanostructures104and sacrificial semiconductor nanostructures106have been formed.

InFIG.1A, there are three semiconductor nanostructures104. However, in practice, there may be many more semiconductor nanostructures104than three. For example, each gate all around transistor may include between 3 and 10 semiconductor nanostructures104. Other numbers of semiconductor nanostructures104can be utilized without departing from the scope of the present disclosure.

The vertical thickness of the semiconductor nanostructures104can be between 2 nm and 15 nm. The thickness of the sacrificial semiconductor nanostructures106can be between 5 nm and 15 nm. Other thicknesses and materials can be utilized for the semiconductor nanostructures104and the sacrificial semiconductor nanostructures106without departing from the scope of the present disclosure.

In some embodiments, the sacrificial semiconductor nanostructures106correspond to a first sacrificial epitaxial semiconductor region having a first semiconductor composition. In subsequent steps, the sacrificial semiconductor nanostructures106will be removed and replaced with other materials and structures. For this reason, the semiconductor nanostructures106are described as sacrificial.

InFIG.1B, a trench108has been formed in the sacrificial semiconductor nanostructures106, the semiconductor nanostructures104, and in the substrate102. The trench108can be formed by depositing a hard mask layer110on the top sacrificial semiconductor nanostructure106. The hard mask layer110is patterned and etched using standard photolithography processes. After the hard mask layer110has been patterned and etched, the sacrificial semiconductor nanostructures106, the semiconductor nanostructures104, and the substrate102are etched at the locations that are not covered by the hard mask layer110. The etching process results in formation of the trenches108. The etching process can include multiple etching steps. For example, a first etching step can etch the top sacrificial semiconductor nanostructure. A second etching step can etch the top semiconductor nanostructure104. These alternating etching steps can repeat until all of the sacrificial semiconductor nanostructures106and semiconductor nanostructures104are etched at the exposed regions. The final etching step may etch the substrate102. In other embodiments, the trench108may be formed in a single etching process.

The trench108defines three columns or stacks semiconductor nanostructures104and sacrificial semiconductor nanostructures106. Each of these columns or stacks corresponds to a separate gate all around transistor that will eventually result from further processing steps described herein. In particular, the semiconductor nanostructures104in each column or stack will correspond to the channel regions of a particular gate all around nanostructure transistor.

The hard mask layer110can include one or more of aluminum, AlO, SiN, or other suitable materials. The hard mask layer110can have a thickness between 5 nm and 50 nm. The hard mask layer110can be deposited by a PVD process, an ALD process, a CVD process, or other suitable deposition processes. The hard mask layer110can have other thicknesses, materials, and deposition processes without departing from the scope of the present disclosure.

InFIG.1C, shallow trench isolation regions112have been formed in the trenches108. The shallow trench isolation regions112can be formed by depositing a dielectric material in the trenches108and by recessing the deposited dielectric material so that a top surface of the dielectric material is lower than the lowest sacrificial semiconductor nanostructure106.

The shallow trench isolation regions112can be utilized to separate individual transistors or groups of transistors formed in conjunction with the semiconductor substrate102. The dielectric material for the shallow trench isolation regions112may include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-K dielectric material, formed by LPCVD (low pressure chemical vapor deposition), plasma enhanced-CVD or flowable CVD. Other materials and structures can be utilized for the shallow trench isolation regions112without departing from the scope of the present disclosure. InFIG.1D, the material of the shallow trench isolation has been etched back via one or more wet or dry etching processes.

InFIG.1E, a cladding layer114has been deposited on the sides of the semiconductor nanostructures104and the sacrificial semiconductor nanostructures106and on the hard mask layer110. The cladding layer114defines gaps116between claddings114of adjacent columns of semiconductor nanostructures. The cladding layer114can be formed by an epitaxial growth from the semiconductor nanostructures104, the sacrificial semiconductor nanostructures106, and the hard mask layer110. Alternatively, the cladding layer114can be deposited by a chemical vapor deposition (CVD) process. Other processes can be utilized for depositing the cladding layer114without departing from the scope of the present disclosure.

InFIG.1Fa layer of polysilicon126has been deposited on the top surfaces of the cladding layer114, the top semiconductor nanostructure104, and on the high-K dielectric layer124. The layer of polysilicon126can have a thickness between 20 nm and 100 nm. The layer of polysilicon126can be deposited by an epitaxial growth, a CVD process, a physical vapor deposition (PVD) process, or an ALD process. Other thicknesses and deposition processes can be used for depositing the layer polysilicon126without departing from the scope of the present disclosure.

InFIG.1Fa dielectric layer128has been deposited on the layer of polysilicon126. A dielectric layer130has been formed on the dielectric layer128. In one example, the dielectric layer128includes silicon nitride. In one example, the dielectric layer130includes silicon oxide. The dielectric layers128and130can be deposited by CVD. The dielectric layer128can have a thickness between 5 nm and 15 nm. The dielectric layer130can have a thickness between 15 nm and 50 nm. Other thicknesses, materials, and deposition processes can be utilized for the dielectric layers128and130without departing from the scope of the present disclosure.

The dielectric layers128and130have been patterned and etched to form a hard mask for the layer of polysilicon126. The dielectric layers128and130can be patterned and etched using standard photolithography processes. After the dielectric layers128and130have been patterned and etched to form the hard mask, the layer of polysilicon126is etched so that only the polysilicon directly below the dielectric layers128and130remains. The result is a polysilicon fin. Additionally, the cladding layer114is removed at all locations except directly under the remaining portion of the layer of polysilicon126. The cladding layer114can be removed in a same etch process that patterns the layer of polysilicon. Alternatively, the cladding layer114can be removed in a separate etching process after etching the layer of polysilicon126.

InFIG.1G, the sacrificial semiconductor nanostructures106are removed from the areas not below the layer of polysilicon126. The sacrificial semiconductor nanostructures106can be removed using an etchant that selectively etches the sacrificial semiconductor nanostructures106with respect to the semiconductor nanostructures104. In some embodiments, the sacrificial semiconductor nanostructures106may also be recessed below the dummy gate structure formed by the layer polysilicon126, and the dielectric layers128and130. This may facilitate forming inner spacers into the recessed regions.

InFIG.1H, a gate spacer layer132has been deposited on the exposed top surfaces of the semiconductor nanostructures104, as well as on the sidewalls of the layer of polysilicon126and the dielectric layers128and130. In one example, the gate spacer layer132includes SiCON. The gate spacer layer132can be deposited by CVD, PVD, or ALD. Other materials and deposition processes can be utilized for the gate spacer layer132without departing from the scope of the present disclosure.

InFIG.1I, and etching processes been performed to remove portions of the gate spacer layer132. The etching process selectively etches in the downward direction. The result is that the gate spacer layer132is removed from on top of the dielectric layer130and from the top of the semiconductor nanostructures104in the areas not covered by the polysilicon layer126. InFIG.1I, a spacer layer133has been deposited between the exposed portions of the semiconductor nanostructures104. The spacer layer133can be deposited by an ALD process, a CVD process, or other suitable processes. In one example, the spacer layer133includes silicon nitride. The spacer layer133may be formed simultaneously with or separately from the gate spacer layer132. Other processes, structures, and materials can be utilized for forming the gate spacer layer132and the spacer layer133without departing from the scope of the present disclosure.

As described previously, when the sacrificial semiconductor nanostructures106are removed outside the dummy gate structure, the sacrificial semiconductor nanostructures106may be recessed below the dummy gate structure. When the spacer layer133is formed, a portion of the spacer layer133is formed in the recesses left by the sacrificial semiconductor nanostructures106beneath the dummy gate structure. The spacer layer133and a recess can help ensure that source and drain regions will not directly contact gate metals that will be formed subsequently. In this sense, a portion of the spacer layer133may also act as an inner spacer layer.

InFIG.1Jsource and drain regions138have been formed. The source and drain regions138include a semiconductor material. The source and drain regions138can be grown epitaxially from the semiconductor nanostructures104. The source and drain regions138can be epitaxially grown from the semiconductor nanostructures104or from the substrate102. The source and drain regions138can be doped with N-type dopants species in the case of N-type transistors. The source and drain regions138can be doped with P-type dopant species in the case of P-type transistors. The doping can be performed in-situ during the epitaxial growth.

The source and drain regions138can have different structures and can be formed with different process than described above. For example, the spacer layer133may be removed between the exposed portions of the nanostructures104, while leaving the portion of the spacer layer133described as the inner spacer layer below the dummy gate structure to prevent the source and drain regions138from directly contacting subsequently formed gate electrodes. An epitaxial growth may then be performed to grow source and drain regions138from the exposed portions of the nanostructures104. In this case, the source and drain material will fill the spaces between the exposed portions of the nanostructures104. In another example, the exposed portions of the nanostructures104may be entirely removed. The source and drain regions138can then be epitaxially grown from the substrate102or otherwise deposited or formed.

InFIG.1Kan etching process has been performed to remove the dielectric layers128and130from above the layer of polysilicon126. The etching process also removes a portion of the gate spacer layer132. Multiple etching steps can be utilized to remove the dielectric layers128and130and the portion of the gate spacer layer132.

After removal of the dielectric layers128and130, an interlevel dielectric layer142has been deposited. The interlevel dielectric layer142can include silicon oxide. The interlevel dielectric layer142can be deposited by CVD, ALD, or other suitable processes. Other materials and processes can be utilized for the interlevel dielectric layer142without departing from the scope of the present disclosure. A CMP process may be performed to make the top surface of the interlevel dielectric layer142planar with the top surface of the polysilicon layer126.

After formation of the interlevel dielectric layer142, an etching process has been performed to remove the polysilicon layer126. The removal of the polysilicon layer126forms a gate trench144. The gate trench144exposes the semiconductor nanostructures104and the portions of the sacrificial semiconductor nanostructures106that were not removed.

InFIG.1L, the remaining portions of the sacrificial semiconductor nanostructures106have been removed from between the semiconductor nanostructures104by selectively etching the sacrificial semiconductor nanostructures106with respect to the semiconductor nanostructures104.

FIGS.1M-1Yare cross-sectional views of the integrated circuit100at intermediate stages of processing, according to some embodiments. The cross-sectional views ofFIGS.1M-1Ytaken along cut lines M shown inFIG.1L. The cross-sectional views show the semiconductor nanostructures104a,104b, and104c, of three different gate all around transistors150a,150b, and150c. WhileFIG.1Lshows the formation of two transistors,FIGS.1M-1Yshow three transistors150a,150b, and150cbecause some embodiments provide three types of transistors each having a different threshold voltage.

InFIG.1M, interfacial dielectric layer152a,152b, and152care formed on the semiconductor nanostructures104a,104b, and104c. The interfacial dielectric layer152ais formed on the semiconductor nanostructures104a. The interfacial dielectric layer152bis formed on the semiconductor nanostructures104b. The interfacial dielectric layer152cis deposited on the semiconductor nanostructures104c. The interfacial dielectric layers152a-care in direct contact with the semiconductor nanostructures104a-c.

The interfacial dielectric layers152a-ccan include a dielectric material such as silicon oxide, silicon nitride, or other suitable dielectric materials. The interfacial dielectric layers152a-ccan include a comparatively low-K dielectric with respect to high-K dielectric materials such as hafnium oxide or other high-K dielectric materials that may be used in gate dielectrics of transistors.

The interfacial dielectric layers152a-152ccan be formed by a thermal oxidation process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. The interfacial dielectric layer can have a thickness between 0.5 nm and 2 nm. One consideration in selecting a thickness for the interfacial dielectric layer is to leave sufficient space between the semiconductor nanostructures104a-cfor gate metals, as will be explained in more detail below. Other materials, deposition processes, and thicknesses can be utilized for the interfacial dielectric layer without departing from the scope of the present disclosure. In some embodiments, the interfacial dielectric layers152a-care formed simultaneously in a same deposition process.

InFIG.1N, high-K dielectric layers154a,154b, and154chave been formed on the semiconductor nanostructures104a,104b, and104cof the transistors150a,150b, and150c. In particular, the high-K gate dielectric layer154ais formed on the interfacial dielectric layer152aon the semiconductor nanostructures104aof the transistor150a. The high-K gate dielectric layer154bis formed on the interfacial dielectric layer152bon the semiconductor nanostructures104bof the transistor150b. The high-K gate dielectric layer154cis formed on the interfacial dielectric layer152con the semiconductor nanostructures104cof the transistor150c. In some embodiments, the high-K gate dielectric layers154a-154care formed simultaneously in a same deposition process.

The high-K gate dielectric layers154a-cand the interfacial dielectric layers152a-cphysically separate the semiconductor nanostructures104from the gate metals that will be deposited in subsequent steps. The high-K gate dielectric layers154a-cand the interfacial dielectric layers152a-152cisolate the gate metals from the semiconductor nanostructures104a-cthat correspond to the channel regions of the transistors150a-c.

The high-K gate dielectric layers154a-cincludes one or more layers of a dielectric material, such as HfO2, HfSiO, HfSiON, HfTaO, HfSiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, other suitable high-k dielectric materials, and/or combinations thereof. The high-K gate dielectric layers154a-cmay be formed by CVD, ALD, or any suitable method. In some embodiments, the high-K gate dielectric layers154a-care formed using a highly conformal deposition process such as ALD in order to ensure the formation of a gate dielectric layer having a uniform thickness around each semiconductor nanostructure104. In some embodiments, the thickness of the high-k dielectric is in a range from about 1 nm to about 3 nm. Other thicknesses, deposition processes, and materials can be utilized for the high-K gate dielectric layers154a-cwithout departing from the scope of the present disclosure. The high-K gate dielectric layers154a-154cmay include a first layer that includes HfO2with dipole doping including La and Mg, and a second layer including a higher-K ZrO layer with crystallization.

The interfacial dielectric layer152aand the high K gate dielectric layer154acollectively form a gate dielectric of the transistor150a. The interfacial dielectric layer152band the high K gate dielectric layer154bcollectively form a gate dielectric of the transistor150b. The interfacial dielectric layer152cand the high K gate dielectric layer154ccollectively form a gate dielectric of the transistor150c.

Prior to proceeding with further discussion regarding the formation of the transistors150a,150b, and150c, it is beneficial to discuss some aspects that can affect the work function of the transistors150a-c. There may be various reasons that it is beneficial to have multiple types of transistors with different threshold voltages. For example, transistors with higher threshold voltages can typically withstand higher voltages across their terminals. Such high threshold voltage transistors may be utilized as I/O transistors coupled to the terminals of the integrated circuit100. These I/O transistors may be subject to particularly high voltages from circuits external to the integrated circuit, or due to the buildup of electrostatic charges. Lower threshold voltage transistors may be utilized as core transistors of the integrated circuit100. The core transistors may be utilized as the logic and computation centers of the integrated circuit100. To reduce power consumption, the core transistors may receive relatively small supply voltages and, thus, may benefit from lower threshold voltages. There may be three or more different types of transistors having different threshold voltages in the integrated circuit100.

The work function associated with the gate electrodes of the transistors strongly affects the threshold voltages of the transistors. The work function of the transistor can be selectively increased or decreased based on the material or combinations of materials acting as the gate electrode. The gate electrode of a first type of transistor may include only a first gate metal and thus may have a first work function. The gate electrode of the second type of transistor may include both the first gate metal and a second gate metal and, thus, may have a second work function different than the first work function. The gate electrode of a third type of transistor may include both the first gate metal, the second gate metal, and a third gate metal and, thus, may have a third work function different than the first and second work functions.

If the various gate metals are deposited in blanket deposition on the gate dielectrics of each of the types of transistors, then some of the gate metals will be removed from between the semiconductor nanostructures of some of the types of transistors in order to produce the differing work functions. However, removing a gate metal from between the semiconductor nanostructures of a transistor that is not intended to include that gate metal can result in some drawbacks. For example, it can be very difficult to entirely remove the gate metal from between the semiconductor nanostructures of the transistor. Particularly long and potent etching processes may be utilized to remove the gate metal from between the semiconductor nanostructures of a particular type of transistor. Not only may removal be incomplete, but the thickness of the high K gate dielectric at the sides of the semiconductor nanostructures may be significantly reduced as a result of the etching processes. The reduction in the thickness of the high K gate dielectric can seriously impact the performance of the transistor. The presence of a gate metal remaining between the semiconductor nanostructures of a transistor for which the gate metal is not intended to be part of the gate electrode can result in the work function not being as distinct as desired compared to other types of transistors. In short, the deposition of a gate metal between the semiconductor nanostructures of a transistor for which the gate metal is intended to be removed can result in serious drawbacks in terms of work function distinction and overall transistor function.

Some embodiments of the present disclosure overcome the drawbacks described above by utilizing an easily removable inter-sheet filler layer to block the deposition of gate metals between the semiconductor nanostructures of transistors for which the gate metals not intended to remain part of the gate electrode. The inter-sheet filler layer can be deposited between the semiconductor nanostructures104a-cof each of the transistors150a-cafter deposition of the high K gate dielectric layers154a-c. The inter-sheet filler layer can then be selectively and successively removed from between each type of transistor between gate metal deposition processes so that gate metals are never deposited between the semiconductor nanostructures of transistors for which the gate metal is not intended to be part of the gate electrode. This is described in more detail with respect to subsequent figures. The result is multiple types of transistors with distinct threshold voltages and robust gate dielectrics. Wafer yields and device performance significantly increased

InFIG.1O, inter-sheet filler layers156a-156chave been deposited on the semiconductor nanostructures104a-c. The inter-sheet filler layer156ais deposited on the high K dielectric layer154aon the semiconductor nanostructures104aof the transistor150a. The inter-sheet filler layer156afills the spaces between the semiconductor nanostructures104a. The inter-sheet filler layer156bis deposited on the high K dielectric layer154bon the semiconductor nanostructures104bof the transistor150b. The inter-sheet filler layer156bfills the spaces between the semiconductor nanostructures104b. The inter-sheet filler layer156cis deposited on the high K dielectric layer154con the semiconductor nanostructures104cof the transistor150c. The inter-sheet filler layer156cfills the spaces between the semiconductor nanostructures104c.

The inter-sheet filler layers156a-ccan include materials with a high etch selectivity relative to the material of the high K-gate dielectric layers154a-c. In some embodiments, the inter-sheet filler layers156a-ccan include Si, AlTiCN, TiC, AlC, TiN, AlN, Al2O3, or SiO2. The inter-sheet filler layers may be deposited by an ALD process. Alternatively, the inter-sheet filler layers156a-cmay be deposited by a CVD process, a PVD process, or other suitable deposition processes. The thickness of the inter-sheet filler layers156a-cis selected to ensure that the inter-sheet filler layers156a-centirely fill the gaps between adjacent semiconductor nanostructures104a-cof each of the transistors150a-c. In one example, after deposition of the high K gate dielectric layer154aon the semiconductor nanostructures104a, the vertical gap between the high K gate dielectric layer154aof adjacent nanostructures104amay be between 20 Å and 50 Å, in some examples. Accordingly, in some embodiments, the inter-sheet filler layers156a-cmay have a thickness between 20 Å and 15 Å. Other materials, deposition processes, and thicknesses can be utilized for the inter-sheet filler layers156a-cwithout departing from the scope of the present disclosure. In some embodiments, the inter-sheet filler layers156a-cmay be deposited simultaneously in a single deposition process. InFIG.1P, an anisotropic etching process has been performed on the inter-sheet filler layers156a-c. The etching process selectively etches in the vertical direction. The result is that the inter-sheet filler layers156a-care removed from the sides of the semiconductor nanostructures104a-cand from the top surface of the top nanostructure104a-cin each transistor150a-c. The inter-sheet filler layers156a-cremain between the semiconductor nanostructures104a-c. The etching process can include a wet etch, a dry etch, or combination of wet and dry etches. In some embodiments, the etching process includes a sidewall conversion treatment including low-temperature O2exposure, or H2O2deionized water wet chemical oxidation. The wet etch further includes a selected wet etch with MR, MR3, or MR1. A subsequent dry etching process can include etching with WCl5 or TACl5 based selected oxide etch with CF4or C2F6plasma. The dry etch can further include an anisotropic atomic radical treatment including H2, F2, or other suitable etches. Other etching processes or combinations of etching processes can be utilized to remove the side portions of the inter-sheet filler layers156a-cwithout departing from the scope of the present disclosure.

InFIG.1Q, a mask158has been formed and patterned. The mask158covers the semiconductor nanostructures104band104cof the transistors150band150c. The mask exposes the semiconductor nanostructures104aof the transistor150a. The mask can include photo resist or hard mask materials patterned using photolithography processes.

An etching process is performed in the presence of the mask158. The etching process entirely removes the inter-sheet filler layer156afrom between the semiconductor nanostructures104a. The etching process can include a wet etch, a dry etch, or a combination of wet and dry etching processes.

InFIG.1R, the mask158has been removed. The mask158can be removed by any suitable process for moving a photoresist or hard mask layer depending on the type of the mask158. After removal of the mask158, first gate metal layers160a-160care deposited on the semiconductor nanostructures104a-c. In particular, the first gate metal layer160ais deposited directly on the high K gate dielectric154aof the transistor150a. The first gate metal layer160aentirely fills the gaps between the semiconductor nanostructures104a. The first gate metal layer160bis deposited directly on the high K gate dielectric154bof the transistor150b. However, the first gate metal layer160bis not deposited entirely between the semiconductor nanostructures104bbecause of the presence of the inter-sheet filler layer156bbetween the semiconductor nanostructures104b. The presence of the inter-sheet filler layer156bprevents or blocks deposition of the first gate metal layer160bbetween the semiconductor nanostructures104b. The first gate metal layer160cis deposited directly on the high K gate dielectric154cof the transistor150c. However, the first gate metal layer160cis not deposited entirely between the semiconductor nanostructures104cbecause of the presence of the inter-sheet filler layer156cbetween the semiconductor nanostructures104c. The presence of the inter-sheet filler layer156cprevents or blocks deposition of the first gate metal layer160cbetween the semiconductor nanostructures104c.

In some embodiments, the first gate metal layers160a-cincludes titanium nitride. In some embodiments, the first gate metal layers160a-cinclude Ru, TiAl, WCN, tantalum, or other suitable materials. The first gate metal layers160a-ccan be deposited by ALD, PVD, CVD, or other suitable deposition processes. The first gate metal layers160a-ccan have thicknesses between 20 Å and 50 Å. Other materials, deposition processes, and thicknesses can be utilized for the first gate metal layers160a-cwithout departing from the scope of the present disclosure.

In Figure is, a mask162has been formed and patterned. The mask162covers the transistors150aand150c. The mask exposes the transistor150b. The mask162can include photo resist or hard mask materials patterned using photolithography processes.

An etching process is performed in the presence of the mask162. The etching process entirely removes the first gate metal160band the inter-sheet filler layer156bfrom between the semiconductor nanostructures104b. The etching process can include a wet etch, a dry etch, or a combination of wet and dry etching processes.

InFIG.1T, the mask162has been removed. The mask162can be removed by any suitable process for moving a photoresist or hard mask layer depending on the type of the mask162. After removal of the mask162, second gate metal layers164a-care deposited on the semiconductor nanostructures104a-c. In particular, the second gate metal layer164ais deposited directly on the first gate metal layer160aof the transistor150a. The second gate metal layer164bis deposited directly on the high K gate dielectric154bof the transistor150b. The second gate metal layer164bentirely fills the gaps between the semiconductor nanostructures104bof the transistor150b. The second gate metal layer164cis deposited directly on the first gate metal layer160cof the transistor150c.

In some embodiments, the second gate metal layers164a-cincludes titanium nitride. In some embodiments, the second gate metal layers164a-cinclude Ru, TiAl, WCN, tantalum, or other suitable materials. In some embodiments, the second gate metal layers164a-cinclude a different material than the first gate metal layers160a-c. The second gate metal layers164a-ccan be deposited by ALD, PVD, CVD, or other suitable deposition processes. The second gate metal layers164a-ccan have thicknesses between 20 Å and 50 Å. Other materials, deposition processes, and thicknesses can be utilized for the second gate metal layers164a-cwithout departing from the scope of the present disclosure.

InFIG.1U, a mask166has been formed and patterned. The mask166covers the transistors150aand150b. The mask166exposes the transistor150c. The mask166can include photo resist or hard mask materials patterned using photolithography processes.

An etching process is performed in the presence of the mask166. The etching process entirely removes the second gate metal layer164c, the first gate metal layer160c, and the inter-sheet filler layer156cfrom between the semiconductor nanostructures104c. The etching process can include a wet etch, a dry etch, or a combination of wet and dry etching processes.

InFIG.1V, the mask166has been removed. The mask166can be removed by any suitable process for moving a photoresist or hard mask layer depending on the type of the mask166. After removal of the mask166, third gate metal layers168a-care deposited on the semiconductor nanostructures104a-c. In particular, the third gate metal layer168ais deposited directly on the second gate metal layer164aof the transistor150a. The third gate metal layer168bis deposited directly on second gate metal layer164bof the transistor150b. The third gate metal layer168cis deposited directly on the high-K gate dielectric layer154cof the transistor150c. The third gate metal layer168centirely fills the gaps between the semiconductor nanostructures104cof the transistor150c.

In some embodiments, the second gate metal layers164a-cincludes TiAl. In some embodiments, the second gate metal layers164a-cinclude Ru, WCN, tantalum, titanium nitride, or other suitable materials. In some embodiments, the third gate metal layers168a-cinclude a different material than the one or both of the second gate metal layers164a-cand the first gate metal layers160a-c. The third gate metal layers168a-ccan be deposited by ALD, PVD, CVD, or other suitable deposition processes. In some embodiments, the third gate metal layers168a-care deposited simultaneously in a single deposition process. The third gate metal layers168a-ccan have thicknesses between 20 Å and 50 Å. Other materials, deposition processes, and thicknesses can be utilized for the third gate metal layers168a-cwithout departing from the scope of the present disclosure.

InFIG.1W, glue layers170a-chave been deposited on the third gate metal layers168a-cof the transistors150a-c. A gate fill material172has been deposited covering the glue layers170a-c. The glue layers170a-cbind the gate fill material172to the third gate metal layers168a-c.

The glue layers170a-ccan include titanium nitride, tantalum nitride, or other suitable materials. The glue layers170a-ccan be deposited by an ALD process, a PVD process, a CVD process, or other suitable deposition processes. The glue layers170a-ccan have a thickness between 5 Å and 20 Å. Other materials, deposition processes, and thicknesses can be utilized for the glue layers170a-cwithout departing from the scope of the present disclosure.

The gate fill material172can include tungsten, cobalt, copper, ruthenium, aluminum, titanium, or other suitable materials. The gate fill material172is a highly conductive metal that covers the other gate metal layers of the transistors150a-c. The gate fill material172completely fills the remaining space in the gate trenches144around and above the semiconductor nanostructures104a-cof the transistors150a-c. The gate fill material172can be deposited by PVD, ALD, CVD, or other suitable deposition processes. Other materials and deposition processes can be utilized for the gate fill material172without departing from the scope of the present disclosure.

InFIG.1W, formation of the transistors150a-cis complete. The transistor150aincludes a gate electrode174a. The gate electrode174aincludes the gate fill material172, the glue layer170a, first gate metal layer160a, the second gate metal layer164a, and the third gate metal layer168a. The transistor150bincludes a gate electrode174b. The gate electrode174bincludes the gate fill material172, the glue layer170b, the second gate metal layer164band the third gate metal layer168b, but does not include the first gate metal layer160b. The transistor150cincludes a gate electrode174c. The gate electrode174cincludes the gate fill material172, the glue layer170c, and the third gate metal layer168c, but does not include the second gate metal layer164cor the first gate metal layer160c.

Because the gate electrodes174a-cinclude different combinations of gate metal layers, each of the transistors150a-chave different work functions. Furthermore, the distinctness of the work functions is improved based on the utilization of the inter-sheet filler layers156a-c. For example, because the inter-sheet filler layers156b-cwere present during deposition of the first gate metal layers160a-c, the first gate metal layers160band160cwere not deposited between the semiconductor nanostructures104b-c. Accordingly, there are no unwanted remnants of the first gate metal layers160band160cbetween the semiconductor nanostructures104band104c. The edges of the high K gate dielectric layers154b-care not diminished from an etching process that might otherwise be utilized to remove the first gate metal layers160band160cif the inter-sheet filler layers were not utilized. The same benefits are achieved in relation to preventing deposition of the second gate metal layer164cbetween the semiconductor nanostructures104cof the transistor150c.

Some further benefits of the process shown in relation toFIGS.1A-1Winclude complete filling of the gaps between the semiconductor nanostructures104a-c. The spaces between the semiconductor nanostructures104a-care entirely filled with either the first gate metal layer160a, the second gate metal layer164b, or the third gate metal layer168csuch that there are no pores between the semiconductor nanostructures104a-c. Furthermore, though not shown inFIGS.1A-1Wa small intermixing layer may remain all around the high K gate dielectric layers154a-c. The small intermixing layer can include a mixture of the material of the high K gate dielectric layers154a-cand the inter-sheet filler layers156a-c.

In some embodiments, after removal of the inter-sheet filler layers156a-c, the remaining amounts of inter-sheet filler material directly below the centers of the semiconductor nanostructures104a-cmay be less than 1.8% and less than 1.2 Å.

FIG.1Xis a cross-sectional view of some of the semiconductor nanostructures104bof the transistor150bin an alternative process that does not utilized the inter-sheet filler layer156b. In this alternative process, the first gate metal layer160bhas been deposited between the semiconductor nanostructures104bbecause the inter-sheet filler layer156bwas not present during the deposition process. An etching process has been utilized to remove the first gate metal layer160bfrom between the semiconductor nanostructures104b. However, the etching process is not able to completely remove the first gate metal layer160bfrom between the semiconductor nanostructures104b. Furthermore, this etching process has greatly reduced the thickness of the high K gate dielectric layer154bon the sides or lateral portions176of the semiconductor nanostructures104b. The result is a less distinct work function for the transistor150band a more poorly functioning transistor150bdue to the degradation of the high K gate dielectric154b.

FIG.1Yis an enlarged cross-sectional view of some of the semiconductor nanostructures104B of the transistor150bin accordance with the process described in relation toFIGS.1O-1W. The view ofFIG.1Ycorresponds to a portion of the process between theFIGS.1S and1Tafter removal of the first gate metal layer160band the inter-sheet filler layer156bprior to deposition of the second gate metal layer164b. As can be seen inFIG.1Y, there are no remnants of the first gate metal layer160bbetween the semiconductor nanostructures104b. This is because the inter-sheet filler layer156bwas present during deposition of the first gate metal layer160b. Furthermore, because a lengthy etching process is not utilized to remove the first gate metal layer160bfrom between the semiconductor nanostructures104b, the high K gate dielectric layer154bis not degraded at the lateral portions176of the semiconductor nanostructures104b. Similar results and benefits are obtained in relation to the transistor150cwith respect to the inter-sheet filler layer156cpreventing deposition of the first gate metal layer160cand the second gate metal layer164cbetween the semiconductor nanostructures104c.

In some embodiments, the high K gate dielectric layer154bhas nearly uniform thickness around the perimeter of the semiconductor nanostructures104b. The variations in thickness may be less than 2 Å. Furthermore, the high K gate dielectric layer154bhas very low surface roughness.

FIGS.2A-2Dare cross-sectional views of an integrated circuit200at various stages of processing, according to some embodiments. InFIG.2A, the integrated circuit200is at a stage of processing corresponding to the integrated circuit one hundred ofFIG.1R. InFIG.2B, a mask162is deposited and patterned on the integrated circuit200. The mask162covers the transistor150aand the transistor150b. The mask162exposes the transistor150c. An etching process has been performed to remove the first gate metal layer160C and the inter-sheet filler layer156cfrom the transistor150c. Accordingly, the high K gate dielectric154cis exposed.

InFIG.2C, the second gate metal layers164a-care deposited. The second gate metal layer164ais deposited on the first gate metal layer160a. The second gate metal layer164bis deposited on the first gate metal layer160b. The second gate metal layer164cis deposited on the high K gate dielectric layer154c. The second gate metal layer164cfills the gaps between the semiconductor nanostructures104cof the transistor150c. The second gate metal layers164a-ccan include the same materials, thicknesses, and deposition processes as described previously for the second gate metal layers164a-cdescribed in relation toFIG.1T. Alternatively, the second gate metal layers164a-ccan include the same materials, thicknesses, and deposition processes as described previously for the third gate metal layers168a-cin relation toFIG.1V.

InFIG.2D, the glue layers170a-chave been deposited on the second gate metal layers164a-c. The glue layers170a-ccan have the same materials, thicknesses, and deposition processes described for the glue layers170a-cofFIG.1W. InFIG.2D, the gate fill material172has been deposited on the glue layers170a-c. The gate fill material172can have the same materials, thicknesses, and deposition processes as described for the gate fill material172ofFIG.1W.

The integrated circuit200ofFIG.2Ddiffers from the integrated circuit100ofFIG.1Win that the third gate metal layers168a-care not deposited. The integrated circuit200ofFIG.2Dalso differs from the integrated circuit100ofFIG.1Win that the inter-sheet filler layer156bremains between the semiconductor nanostructures104bof the transistor150b. The transistors150a-150call have different work functions and different threshold voltages from each other.

FIGS.3A-3Dare cross-sectional views of an integrated circuit300at various stages of processing, according to some embodiments. The integrated circuit300ofFIG.3Acorresponds to the stage of processing of the integrated circuit100ofFIG.1O. In particular, the inter-sheet filler layers156a-chave been deposited on the between the semiconductor nanostructures104a-cof the transistors150a-c.

InFIG.3Ban annealing process is performed in the presence of low amounts of O2. Alternatively, and oxidation treatment is performed including passing H2O2and O3into the environment of the integrated circuit300. The result of either of these processes is a change in the structure or strength of the portions of the inter-sheet filler layers156a-cthat are not directly between the semiconductor nanostructures104a-c.

InFIG.3C, a selected sidewall etch is performed. The selected sidewall etch etches the altered portions of the inter-sheet filler layers156a-cselectively with respect to the portions of the inter-sheet filler layers156a-cthat are positioned directly between the semiconductor nanostructures104a-cand that were not affected by the processes described in relation toFIG.3B. The selected sidewall etch can include a wet etch or dry etch. In one example, the sidewall etch includes etching with CF4. The result of the etching process is that the inter-sheet filler layers156a-cremain only directly between the semiconductor nanostructures104a-c. This process can be utilized to form the inter-sheet filler layers156a-cof the integrated circuits100and200described previously.

FIG.4Ais a cross-sectional view of an integrated circuit400, according to some embodiments. InFIG.4A, the integrated circuit400is at the stage of processing corresponding to the integrated circuit100ofFIG.1O. In particular, the inter-sheet filler layers156a-chave been formed on the semiconductor nanostructures104a-cthe same manner as described in relation toFIG.1O. InFIG.4B, an anisotropic etch is performed to remove the portions of the inter-sheet filler layers156a-cthat are not directly between the semiconductor nanostructures104a-c. The anisotropic etch can include a plasma etch that etches selectively in the downward direction. The plasma etch can include bombarding the integrated circuit400with plasmatized ions in the downward direction. The result of the anisotropic etch is that the inter-sheet filler layers156a-cremain only directly between the semiconductor nanostructures104a-c.

FIG.5is a flow diagram of a method500for forming an integrated circuit, according to some embodiments. The method500can utilize structures and processes described in relation toFIGS.1A-4B. At502, the method500includes forming an inter-sheet filler layer between first semiconductor nanostructures of a first gate all around transistor and between second semiconductor nanostructures of a second gate all around transistor. One example of a first gate all around transistor is the first gate all around transistor150aofFIG.1O. One example of a second gate all around transistor is the second gate all around transistor150bofFIG.1O. One example of first semiconductor nanostructures are the semiconductor nanostructures104aofFIG.1O. One example of second semiconductor nanostructures are the semiconductor nanostructures104bofFIG.1O. One example of an inter-sheet filler layer is the inter-sheet filler layer156a-bofFIG.1O. At504, the method500includes removing the inter-sheet filler layer from between the first semiconductor nanostructures. At506, the method500includes forming a first gate metal layer between the first semiconductor nanostructures and on the second semiconductor nanostructures while the inter-sheet filler layer is between the second semiconductor nanostructures. One example of a first gate metal layer is the first gate metal layer160a-bofFIG.1R. At508, the method500includes removing the first gate metal layer and the inter-sheet filler layer from the second semiconductor nanostructures. At510, the method500includes forming a second gate metal layer between the second semiconductor nanostructures and on the first gate metal layer over the first semiconductor nanostructures. One example of a second gate metal layer is the second gate metal layer164a-bofFIG.1T.

FIGS.6A-6Fare perspective views of an integrated circuit100at successive intermediate stages of processing, according to some embodiments.FIGS.6G-6Lare cross-sectional views of the integrated circuit100at successive intermediate stages of processing, according to some embodiments.FIGS.6A-6Lillustrate an exemplary process for producing an integrated circuit that includes nanostructure transistors.FIGS.6A-6Lillustrate how these transistors can be formed in a simple and effective process in accordance with principles of the present disclosure.FIG.6A-6Lmay utilize processes, techniques, structures, and materials described in relation toFIGS.1A-5. Other process steps and combinations of process steps can be utilized without departing from the scope of the present disclosure.

FIG.6Aillustrates a substrate102.FIG.6Aalso illustrates a stack of semiconductor nanostructures104and sacrificial semiconductor nanostructures106. The substrate102, the semiconductor nanostructures104, and the sacrificial semiconductor nanostructures106can be substantially as described in relation toFIGS.1A and1B, though other structures, materials, and processes can be utilized without departing from the scope of the present disclosure.

InFIG.6Ba hard mask110has been formed on the stack of semiconductor nanostructures104and sacrificial semiconductor nanostructures106. The hard mask110has been patterned and trenches108have been etched in the stack of semiconductor nanostructures104and sacrificial semiconductor nanostructures106and in the substrate102. The hard mask110and the trenches108can be formed substantially as described in relation toFIGS.1A and1B, though other structures, materials, and processes can be utilized without departing from the scope of the present disclosure.

InFIG.6C, shallow trench isolation regions112have been formed in the trenches108. The shallow trench isolation regions112can be formed substantially as described in relation toFIGS.1C and1D, though other structures, materials, and processes can be utilized without departing from the scope of the present disclosure.

InFIG.6D, a dummy gate structure180has been formed. The dummy gate structure180includes a cladding layer114formed on the stack of semiconductor nanostructures104and sacrificial semiconductor nanostructures106, and on the shallow trench isolation regions112. The dummy gate180includes a layer of polysilicon126on the cladding layer114. The dummy gate180includes a dielectric layer130on the layer polysilicon126. The dummy gate has been patterned to expose portions of the stack of semiconductor nanostructures104and sacrificial semiconductor nanostructures106. The cladding layer114, the layer polysilicon126, and the dielectric layer130can be formed substantially as described in relation toFIGS.1E and1F, though other structures, materials, and processes can be utilized without departing from the scope of the present disclosure.

InFIG.6E, a spacer layer132has been formed on the dummy gate180and on the exposed portions of the stack of semiconductor nanostructures104and sacrificial semiconductor nanostructures106. The spacer layer can be formed substantially as described in relation toFIG.1H, though the spacer layer132will not be positioned between the semiconductor nanosheets104because the sacrificial semiconductor nanosheets106about been etched back. Other processes, structures, and materials can be utilized for the spacer layer132without departing from the scope of the present disclosure.

InFIG.6F, a substantially anisotropic etching process has been performed. The etching process etches in the downward direction. A first etching step removes the spacer layer132from the top of the dielectric layer130and from the top of the uppermost semiconductor nanostructures104. The portions of the spacer layer132with larger vertical thicknesses are not removed. A second etching step removes the portions of the stack of semiconductor nanostructures104and sacrificial semiconductor nanostructures106that are not covered by the dummy gate180. The first and second etching steps can utilize one or more of dry etches, wet etches, or other types of etches. The etching process corresponds to forming a recess for source and drain regions that will be subsequently produced.FIG.6Falso illustrates cut lines G for the cross-sectional views ofFIGS.6G-6L.

FIG.6Gis a cross-sectional view of the integrated circuit100at the same processing stage shown inFIG.6E, in accordance with some embodiments. The cross-sectional view ofFIG.6Gillustrates the remaining portions of the semiconductor nanostructures104and sacrificial semiconductor nanostructures106on the substrate102.FIG.6Galso illustrates the dummy gate180including the cladding layer114the layer polysilicon126and the spacer layer132. The dielectric layer130is not shown inFIG.6Gbecause the view ofFIG.6Gdoes not extend vertically high enough to show the dielectric layer130.

InFIG.6H, an etching processes been performed to recess the sacrificial semiconductor nanostructures106relative to the semiconductor nanostructures104. This can be accomplished by performing a selective timed etch. The etching process selectively etches the sacrificial semiconductor nanostructures106with respect to the semiconductor nanostructures104. The etching process is timed to form recesses in the sacrificial semiconductor nanostructures106rather than to entirely remove the sacrificial semiconductor nanostructures106. The etching process can include one or more of a dry etch, wet etch, or other type of etching process.

InFIG.6I, an inner spacer layer182has been formed in the recesses adjacent to the remaining portions of the sacrificial semiconductor nanostructures106. The inner spacer layer182can be formed by an ALD process, a CVD process, an epitaxial growth, or other suitable processes. The inner spacer layer182may include silicon nitride or another suitable dielectric material. Other processes, structures, and materials can be utilized for the inner spacer layer182without departing from the scope of the present disclosure.

InFIG.6J, source and drain regions138have been formed. The source and drain regions138include a semiconductor material. The source and drain regions138can be grown epitaxially from one or more of the semiconductor nanostructures104, the substrate102, and the inner spacer layer182. The source and drain regions138can include silicon or other semiconductor materials. The source and drain regions138may be doped in situ during formation of the source and drain regions138. Other structures, materials, and processes can be utilized for the source and drain regions138without departing from the scope of the present disclosure.

InFIG.6J, a dielectric layer183has been formed on the source and drain regions138and on sidewalls of the dummy gate180. The dielectric layer183can include silicon nitride or another suitable dielectric material. The dielectric layer183can be deposited by CVD, ALD, or other suitable deposition processes. An interlevel dielectric layer184has been deposited on the dielectric layer183. The interlevel dielectric layer184can be deposited by ALD, CVD, or other suitable deposition processes. The interlevel dielectric layer184can include silicon oxide, a porous dielectric material, a low K dielectric material, an ultra-low K dielectric material, or other suitable dielectric materials. Other materials and processes can be utilized for the dielectric layer183in the interlevel dielectric layer184without departing from the scope of the present disclosure.

InFIG.6K, the sacrificial semiconductor nanostructures106have been entirely removed. The sacrificial semiconductor nanostructures106may be entirely removed by an etching process that selectively etches the sacrificial semiconductor nanostructures106with respect to the semiconductor nanostructures104. The etching process can include a wet etch, dry etch or other types of etches.

After removal of the sacrificial semiconductor nanostructures106, a gate dielectric185is formed on the semiconductor nanostructures104. The gate dielectric185surrounds the semiconductor nanostructures104. Formation of the gate dielectric185utilizes the processes and structures described in relation toFIGS.1M-1N. Accordingly, the gate dielectric185includes the interfacial gate dielectric layer152and the high K gate dielectric layer154described in relation toFIGS.1M-1N, though the gate dielectric185is illustrated as a single layer inFIG.6K.

After formation of the gate dielectric185, a gate electrode186is formed on the gate dielectric185. The gate electrode186can include one or more of the first gate metal layer160a-c, the second gate metal layer164a-c, the third gate metal layer168a-c, the glue layer170a-c, and the gate fill material172, and the inter-sheet filler layer156a-cas described in relation toFIGS.1A-4B. Accordingly, the gate electrode186can be formed utilizing the processes, structures, and materials described in relation toFIGS.10-4B.

InFIG.6L, source and drain contacts190have been formed in the interlevel dielectric layer184. The source and drain contacts190can include a silicide in direct contact with the source and drain regions138. The source and drain contacts190can include a conductive via or plug made of a conductive material such as aluminum, titanium, tungsten, copper, gold, tantalum, or other conductive materials. The source and drain contacts190may be formed by first etching trenches in the interlevel dielectric layer184. Other processes and materials can be utilized to form the source and drain contacts190without departing from the scope of the present disclosure.

FIG.6Lcorresponds to completion of a nanostructure transistor150. The nanostructures transistor150may correspond to one of the transistors150a-cdescribed previously in relation toFIGS.1A-4B. The nanostructure transistor150may have other structures, materials, components, and may utilize other processes without departing from the scope of the present disclosure.

In some embodiments, a method includes forming an inter-sheet filler layer between first semiconductor nanostructures of a first gate all around transistor and between second semiconductor nanostructures of a second gate all around transistor, removing the inter-sheet filler layer from between the first semiconductor nanostructures, and forming a first gate metal layer between the first semiconductor nanostructures and on the second semiconductor nanostructures while the inter-sheet filler layer is between the second semiconductor nanostructures. The method includes removing the first gate metal layer and the inter-sheet filler layer from the second semiconductor nanostructures and forming a second gate metal layer between the second semiconductor nanostructures and on the first gate metal layer over the first semiconductor nanostructures.

In some embodiments, an integrated circuit includes a first gate all around transistor including a plurality of first semiconductor nanostructures and a second gate all around transistor including a plurality of second semiconductor nanostructures. The integrated circuit includes an inter sheet filler layer between the second semiconductor nanostructures and a first gate metal layer between the first semiconductor nanostructures and on sides of the second semiconductor nanostructures.

In some embodiments, an integrated circuit includes a first gate all around transistor including a plurality of first semiconductor nanostructures and a second gate all around transistor including a plurality of second semiconductor nanostructures. The integrated circuit includes a gate dielectric layer surrounding the first and second semiconductor nanostructures, a first gate metal layer substantially filling a space between the first semiconductor nanostructures, and a second gate metal layer substantially filling a space between the second semiconductor nanostructures. The first gate metal layer has a thickness less than 0.2 nm between the second semiconductor nanostructures.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.