Patent ID: 12225834

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper”, “on” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the terms such as “first”, “second” and “third” describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as “first”, “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context.

As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation of less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, two numerical values can be deemed to be “substantially” the same or equal if a difference between the values is less than or equal to ±10% of an average of the values, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, “substantially” parallel can refer to a range of angular variation relative to 0° that is less than or equal to ±100, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°. For example, “substantially” perpendicular can refer to a range of angular variation relative to 90° that is less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1°, or less than or equal to ±0.05°.

A phase change memory (PCM) cell includes a phase change material arranged over a heating element and a dielectric element surrounded by and abutting the heating element. Further, a top electrode is arranged over the phase change element, and a bottom electrode is arranged below the heating elements. In some embodiments, the phase change memory cell is integrated in an interconnect structure, and thus a metal layer or a via may serve as the bottom electrode of the phase change memory cell. The data state of the phase change memory cell is switched between “1” and “0” by heating the phase change material to cause reversible switches between crystalline and amorphous state of the phase change material. However, it is found that the heat also causes metal diffusion from the metal layer that is serving as the bottom electrode. Consequently, metal loss is caused due to the high temperature required to cause the state switch. The metal loss issue adversely impacts the reliability of the interconnect structure. Further, the metal loss issue can even form an open circuit in the interconnect structure as a size of the heating element is reduced to less than 65 nanometers (nm).

The present disclosure therefore provides a semiconductor structure including a memory device and a method for forming the same. In the semiconductor structure, a heat-buffering layer is introduced between the heating element of the memory device and the metal layer of the interconnect structure, and thus heat required to cause the state change for the phase change material is buffered from the metal layer in the interconnect structure. Consequently, metal diffusion and metal loss issue are both mitigated by the heat-buffering layer, and thus reliability of the phase change memory cell and the interconnect structure are both improved.

FIG.1shows a flow chart representing a method for forming a semiconductor structure10according to aspects of the present disclosure. In some embodiments, the method10includes an operation100: forming a first conductive layer. The method10further includes an operation102: forming a first dielectric layer over the first conductive layer, the first dielectric layer including at least one trench exposing the first conductive layer. The method10further includes an operation104: forming a second conductive layer in the trench. The method10further includes an operation106: forming a third conductive layer in the trench, wherein a resistivity of the third conductive layer is greater than a resistivity of the second conductive layer. The method10further includes an operation108: forming a second dielectric layer over the third conductive layer. The method10further includes an operation110: forming a phase change material over the first dielectric layer. The method10will be further described according to one or more embodiments. It should be noted that the operations of the method for forming the semiconductor structure10may be rearranged or otherwise modified within the scope of the various aspects. It is further noted that additional operations may be provided before, during, and after the method10, and that some other operations may only be briefly described herein. Thus other implementations are possible within the scope of the various aspects described herein.

FIGS.2A-2Iare schematic drawings illustrating a semiconductor structure including a memory device at various fabrication stages constructed according to aspects of the present disclosure in one or more embodiments. Further,FIGS.2A-2Hare enlarged views of a portion of the semiconductor structure including the memory device at various fabrication stages constructed according to aspects of the present disclosure in one or more embodiments. Referring toFIG.2A, a substrate can be received. The substrate may be a semiconductor substrate formed of commonly used semiconductor materials such as silicon (Si), silicon germanium (SiGe), gallium arsenide (GaAs), and the like, and may be a bulk substrate or a semiconductor-on-insulator (SOI) substrate. In some embodiments, the substrate can include a plurality of functional regions. The plurality of functional regions can be defined and electrically isolated from each other by isolation structures, such as shallow trench isolations (STIs), but the not limited thereto. For example but not limited to, the substrate can include a logic region200L and a memory region200M that are defined and electrically isolated from other functional regions by the STIs. The logic region200L may include circuitry, such as the exemplary transistor202, for processing information received from memory cells and for controlling reading and writing functions of the memory cells. In some embodiments, access transistors204are disposed in the memory region200M. The transistor202in the logic region200L can include a gate dielectric layer2061, a gate conductive layer206G, source/drain regions206S/206D, and silicides206L, but the disclosure is not limited to this. The access transistors204in the memory region200M can include a gate dielectric layer2081, a gate conductive layer208G, source/drain regions208S/208D, and silicides208L, but the disclosure is not limited to this. For simplicity, components such as spacers and contact etch stop layer (CESL) that are commonly formed in integrated circuits are not illustrated and/or detailed.

Still referring toFIG.2A, an inter-layer dielectric layer ILD is formed over the transistor202and the access transistors204, and contact plugs CO are formed in the inter-layer dielectric layer ILD for providing electrical connections between other circuitry/elements and the source/drain regions206S/206D of the transistor204, and between other circuitry/elements and the source/drain regions208S/208D of the access transistors204. The formation operations of the contact plugs CO can include forming openings in the inter-layer dielectric layer ILD, filling the openings and performing a planarization such as chemical mechanical polish (CMP). For simplicity, the gate contact plug is not shown, although it is also formed simultaneously with the contact plugs CO shown inFIG.2A. In some embodiments, the contact plugs CO can include tungsten (W), but other suitable conductive material such as silver (Ag), aluminum (Al), copper (Cu), AlCu, and the like may also be used or added.

Still referring toFIG.2A, an interconnect structure210is disposed over the inter-layer dielectric layer ILD and the contact plugs CO. In some embodiments, the interconnect structure210includes a plurality of conductive layers. For example, the interconnect structure210includes a plurality of metal layers labeled as M1through M4and a plurality of conductors labeled as V1through V3. Further, the metal layers M1through M4and the conductors V1through V4are disposed in a plurality of inter-metal dielectric layers labeled as IMD1through IMD4. The inter-metal dielectric layers IMD1through IMD4may provide electrical insulating as well as structural support for the various features during many fabrication operations. In some embodiments, the inter-metal dielectric layer IMD1through IMD4may be formed of low-k dielectric material, for example, with k value lower than about 3.0, and even lower than about 2.5, but the disclosures is not limited to this. In some embodiments, a memory device can be integrated in the interconnect structure210. For example, the memory device can be integrated over the metal layer M4and the inter-metal dielectric layer IMD4, but the disclosure is not limited to this. In other words, the memory device can be integrated over any of the metal layers Mn and the inter-metal dielectric layer IMDn, and n is a positive integer. In some embodiments, the formation operations of the metal layers Mn and the conductors Vn can include forming openings in the inter-metal dielectric layer IMDn, filling the openings and performing a planarization such as chemical mechanical polish (CMP). In some embodiments, the metal layers M1through M4and the conductor V1through V4can include W, Al, Cu, AlCu, and the like. Additionally, a barrier layer (not shown) can be disposed between at least the metal layers M1through M4and the inter-metal layers IMD1through IMD4.

Please refer toFIG.2B, in some embodiments, a conductive layer212such as the metal layer M4is provided according to operation100. However in some embodiments, the conductive layer212can be any of the metal layers Mn, and n is a positive integer, as mentioned above. In some embodiments, a trench may be formed in the inter-metal dielectric layer (IMD), a barrier layer212-1may formed to line a bottom and sidewalls of the trench, and a conductor layer212-2may be formed to fill the trench. In some embodiments, a planarization may be performed to remove superfluous conductor layer212-2and/or barrier layer212-1. It should be understood that to mitigate metal diffusion, which may adversely affect electrical isolation of the surrounding IMD layers, the barrier layer212-1may be required. Therefore, the conductor layer212-2may be enclosed or encapsulated by the barrier layer212-1. Next, a first dielectric layer214, such as an inter-metal dielectric layer IMD5, is formed over the conductive layer212. At least one trench216is formed in the first dielectric layer214, and the conductive layer212is exposed from the trench216, as shown inFIG.2B. In some embodiments, a depth D of the trench216can be between approximately 250 angstroms (Å) and approximately 500 Å, but the disclosure is not limited to this.

A second conductive layer220is formed in the trench216according to operation104. In some embodiments, the formation of the second conductive layer220in the trench216further includes forming the conductive layer220over the first dielectric layer214to fill the trench216as shown inFIG.2C. In some embodiments, the conductive layer212includes Cu, and the conductive layer220can include conductive materials that are able to be a Cu diffusion barrier. For example but not limited to, the conductive layer220can include tantalum nitride (TaN), tantalum (Ta), titanium nitride (TiN), tungsten nitride (WN), W, palladium (Pd), nickel (Ni), nickel chromium (NiCr), zirconium (Zr), and niobium (Nb).

Referring toFIG.2D, the conductive layer220is then etched back by any suitable etchant. Accordingly, a top surface of the conductive layer220is lower than an opening of the trench216. In some embodiments, a thickness T1of the conductive layer220in the trench216can be equal to or greater than 50 Å, but the disclosure is not limited to this. However, the thickness T1of the conductive layer220can be limited by, for example but not limited to, an aspect ratio of the trench216, as long as the thickness T1is less than the depth D of the trench216.

Referring toFIG.2E, a conductive layer222is formed in the trench216according to operation106. The conductive layer222is conformally formed in the trench216, and thus the conductive layer222is in contact with a top surface of the conductive layer220and a portion of sidewalls of the trench216, as shown inFIG.2E. Accordingly, the conductive layer222is spaced apart from the conductive layer212by the conductive layer220. More importantly, a resistivity of the conductive layer222is greater than a resistivity of the conductive layer220. Further, a thermal conductivity of the conductive layer222is less than a thermal conductivity of the conductive layer220. In some embodiments, a thickness T2of the conductive layer222can be equal to or greater than 30 Å, but the disclosure is not limited to this. In some embodiments, the thickness T2of the conductive layer222can be between about 30 Å and about 200 Å, but the disclosure is not limited to this. However, it should be easily realized that the thickness T2of the conductive layer222can be limited by, for example but not limited to, an aspect ratio of the trench216. In some embodiments, the conductive layer222includes TiN, but other suitable conductive material such as TaN or TaAlN may be used. Further, the conductive layer222can be formed by atomic layer deposition (ALD), but the disclosure is not limited to this. In some embodiments, the conductive layer220and the conductive layer222can include the same material. In other embodiments, the conductive layer220and the conductive layer222can include different materials.

Referring toFIG.2F, a second dielectric layer224is formed over the conductive layer222according to operation108. The second dielectric layer224can include silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON), but the disclosure is not limited to this. In some embodiments, the second dielectric layer224and the first dielectric layer214can include the same material, but the disclosure is not limited to this. Further, the second dielectric layer224is formed to fill the trench216, as shown inFIG.2F. Subsequently, a planarization such as CMP operation is performed to remove a portion of the second dielectric layer224and a portion of the conductive layer222, such that the first dielectric layer214, the second dielectric layer224and the conductive layer222are all exposed as shown inFIG.2G.

Referring toFIG.2H, a phase change material226is then formed over the first dielectric layer214, the second dielectric layer224and the conductive layer222according to operation110. In some embodiments, a thickness T3of the phase change material226can be between about 300 Å and about 400 Å, but the disclosure is not limited to this. In some embodiments, the phase change material226can include chalcogenide materials including one or more of germanium (Ge), tellurium (Te) and antimony (Sb) or stoichiometric materials. In some embodiments, the phase change material226can include a Ge)Sb—Te (GST) compound such as Ge2Sb2Te5(also referred to as GST225), but the disclosure is not limited to this. In some embodiments, the phase change material226can include Si—Sb—Te compounds, Ga—Sb—Te compounds, As—Sb—Te compounds, Ag—In—Sb—Te compounds, Ge—In—Sb—Te compounds, Ge—Sb compounds, Sb—Te compounds, Si—Sb compounds, and combinations thereof. The phase change material226is chosen to be a material that will undergo a phase change such as from amorphous to crystalline or vice-versa when heated by the conductive layer222.

Still referring toFIG.2H, subsequently a conductive layer228is formed over the phase change material226, and thus a memory device230is obtained. In some embodiments, a thickness T4of the conductive layer228is about 400 Å, but the disclosure is not limited to this. In the memory device230, the conductive layer228serves as a top electrode232while the conductive layer220, the conductive layer222and the second dielectric layer224serve as a bottom electrode234. Accordingly, the memory device230includes the top electrode232, the bottom electrode234adjacent to the conductive layer212, and the phase change material226between the top electrode232and the bottom electrode234. Further, the bottom electrode234includes a first portion234aand a second portion234bbetween the first portion234aand the conductive layer212. The first portion234aand the second portion234bcan include different materials. As shown inFIG.2H, the conductive layer222and the second dielectric layer224form the first portion234a, and the conductive layer220forms the second portion234b. Since the resistivity of the conductive layer222is greater than the resistivity of the conductive layer220, more heat will be generated by the conductive layer222. Accordingly, the conductive layer222serves as a heat-spreading layer while the conductive layer220serves as a heat-buffering layer. In some embodiments, the thickness T1of the heat-buffering layer220is greater than the thickness T2of the heat-spreading layer222, as shown inFIG.2E. However, a height h1of the first portion234a(including the conductive layer222and the second dielectric layer224) and a height h2of the second portion234b(including the conductive layer220) include a ratio, and the ratio is between about 4 and about 9, but the disclosure is not limited to this. More importantly, the heat-buffering layer220is disposed between the heat-spreading layer222and the conductive layer212. Further, the heat-spreading layer222is in a ring shape from a top plan view, and the bottom and the sidewall of the second dielectric layer224are in contact with the heat-spreading layer222. And the heat-buffering layer220is in contact with an entire bottom surface of the heat-spreading layer222. Further, an outer surface of the ring-shaped heat-spreading layer222is aligned with and coupled to a sidewall surface of the heat-buffer layering220.

Referring toFIG.2I, in some embodiments, another conductive layer240can be formed over the memory device230, and a top conductor242can be disposed between the conductive layer240and the memory device230for providing electrical connection. The top conductor242is disposed between the top electrode232of the memory device230and the conductive layer240. As mentioned above, the memory device230can be integrated in the interconnect structure210, therefore in some embodiments, the first dielectric layer214can be formed simultaneously with an inter-metal dielectric layer IMD5. Similarly, the top conductor242can be formed simultaneously with the conductor V5, and the conductive layer240can be formed simultaneously with other conductive layer in the inter-metal layer IMD5, such as the metal layer M5, as shown inFIG.2I.

Accordingly, a semiconductor structure20is therefore obtained. The semiconductor structure20can include the conductive layer212(or the metal layer M4), the conductive layer240(or the metal layer M5), and the memory device230disposed between the conductive layer212and the conductive layer240. As mentioned above, the memory device230includes the top electrode232, the bottom electrode234adjacent to the conductive layer212, and the phase change material226between the top electrode232and the bottom electrode234. In some embodiments, the semiconductor structure20includes the inter-metal dielectric layer IMD4, and the conductive layer212and other conductive layer such as the metal layer M4are disposed in inter-metal dielectric layer IMD4. As shown inFIGS.2H and2I, the semiconductor structure20includes the dielectric layer214serving as a portion of the inter-metal dielectric layer IMD5, and the conductive layer240and other conductive layer such as the metal layer M5are disposed in the inter-metal dielectric layer IMD5. Further, the semiconductor structure20further includes the conductors V5disposed in the inter-metal dielectric layer IMD5to electrically connect the metal layer M5in the inter-metal dielectric layer IMD5and the metal layer M4in the inter-metal dielectric layer IMD4. In some embodiments, a height h3of the memory cell230is less than a height h4of the conductors V5. In some embodiments, a sum of the height h3and a height of the top conductor242is substantially equal to the height h4of the conductors V5, but the disclosure is not limited to this.

Referring toFIGS.2H and2I, the memory device230is electrically connected to the access transistor204through the interconnect structure210and the contact plug CO in the memory region200M. Further, the memory device230is electrically connected to a word line or a source line244through the interconnect structure210, the contact plug CO and the access transistor204, as shown inFIG.2I. Further, other operations such as providing other electrical connection between the memory device230and a bit line (not shown) through the conductive layer240(M5of the interconnect structure210) can be performed. Additionally, the transistor202in the logic region200L can be electrically connected to other circuitry or element through the interconnect structure210located in the logic region200L.

Referring toFIG.3, which is a schematic drawing illustrating a semiconductor memory structure20′ according to aspects of the present disclosure in one or more embodiments. It should be noted that elements same inFIGS.2A-2IandFIG.3are designated by the same numerals. Further, those elements can include the same materials and be formed by the same operations, therefore those details are omitted in the interest of brevity and only differences are discussed. In some embodiments, the method for forming the semiconductor structure including the memory device10can be performed to form the semiconductor structure20′ and the memory device230is integrated in the interconnect structure210. However, a height h3′ of the memory cell230can be equal to the height h4of the conductor V5. Accordingly, the top electrode232of the memory device203is in contact with the conductive layer240, such as the metal layer M5of the interconnect structure210, as shown inFIG.3.

Referring toFIG.4, which is a schematic drawing illustrating the memory device in a reset state according to aspects of the present disclosure in one or more embodiments, since the resistivity of the conductive layer222is greater than the resistivity of the conductivity layer220, heat is generated in and spread from the conductive layer222when sufficient currents is applied to the conductive layer222. Accordingly, the conductive layer222serves as the heat-spreading layer of the bottom electrode234, as mentioned above. The phase change material226is heated up to a temperature higher than a melting temperature by the heat-spreading layer222. The temperature can be quickly dropped below the crystallization temperature, which is referred as “quench”, and thus a portion of the phase change material226is changed to an amorphous state with a high resistivity as schematically shown in region250A inFIG.4. Accordingly, the memory device230is in a high-resistance state and stores a data value of “0” in a reset state. Additionally, since the thermal conductivity of the conductive layer220is greater than the thermal conductivity of the conductive layer222, heat can be quenched faster due to the conductive layer220. In other words, the quench operation is shortened. Additionally, it should be noted that the heat-spreading layer222is in a ring shape from a top plan view. Therefore, the region250A is in a ring shape inherited from the heat-spreading layer222.

Referring toFIG.5, which is a schematic drawing illustrating the memory device in a set state according to aspects of the present disclosure in one or more embodiments, the region250A can be set back to the crystalline state by heating up the phase change material226to a temperature higher than the crystalline temperature but below the melting temperature by the heat-spreading layer222, for a period time. Thus, the portion of the phase change material226is changed to a crystalline state with a low resistivity as schematically shown in region250C inFIG.5. Accordingly, the memory device230is in a low-resistance state and stores a data value of “1” in a set state. Additionally, it should be noted that the heat-spreading layer222is in a ring shape from a top plan view. Therefore, the region250C is in a ring shape inherited from the heat-spreading layer222.

Still referring toFIGS.4and5, the conductive layer220, which includes resistivity lower than the conductive layer222, serves as the heat-buffering layer of the bottom electrode234, as mentioned above. It should be noted that since the heat-spreading layer222is spaced apart from the conductive layer212by the heat-buffering layer220, heats are buffered by the heat-buffering layer220. In other words, the conductive layer212is in contact with the heat-buffering layer220which has the temperature lower than the heat-spreading layer220, consequently the metal diffusion is reduced due to the lower temperature. Additionally, since the heat-buffering layer220includes the conductive material having diffusion barrier ability, the conductive layer212can be enclosed by the diffusion barrier layers (i.e. the barrier layer212-1and the heat-buffer layer220) and thus the metal diffusion issue of the conductive layer212is further mitigated. Accordingly, not only the performance and reliability of the memory device230is improved, but also the reliability of the interconnect structure210is improved.

Accordingly, the present disclosure therefore provides a semiconductor structure including a memory device and a method for forming the same. In some embodiments, a heat-buffering layer is introduced between the heat-spreading layer and the conductive layer of the interconnect structure, and thus heat required to cause the state change for the phase change material is buffered from the conductive layer in the interconnect structure. Consequently, metal diffusion and metal loss issue are both mitigated by the heat-buffering layer, and thus reliability of the phase change memory device and interconnect structure are both improved.

In some embodiments, a method for forming a semiconductor structure is provided. The method includes following operations. A first conductive layer is formed. A first dielectric layer is formed over the first conductive layer, and the first dielectric layer includes at least one trench exposing the first conductive layer. A second conductive layer is formed in the trench. A third conductive layer is formed in the trench, and a resistivity of the third conductive layer is greater than a resistivity of the second conductive layer. A second dielectric layer is formed over the third conductive layer. A phase change material is formed over the first dielectric layer.

In some embodiments, a method for forming a semiconductor structure is provided. The method includes following operations. A first dielectric layer is formed over a first conductive layer. The first conductive layer is exposed through a bottom of a trench in the first dielectric layer. A second conductive layer is formed in the trench and covering a top surface of the first dielectric layer. A portion of the second conductive layer is removed such that a top surface of the second conductive layer is lower than the top surface of the first dielectric layer. A third conductive layer is formed in the trench and covering the first dielectric layer. A second dielectric layer is formed over the third conductive layer and the first dielectric layer. A portion of the third conductive layer and a portion of the second dielectric layer are removed to expose the top surface of the first dielectric layer.

In some embodiments, a method for forming a semiconductor structure is provided. The method includes following operations. A first dielectric layer is formed over a lower conductive layer. The first dielectric layer includes at least one trench exposing the first conductive layer. A heat-butting layer is formed in the trench. A heat-spreading layer is stacked over the heat-spreading layer in the trench. The trench is filled with a second dielectric layer. A phase change material is disposed over the first dielectric layer. A top electrode is formed over the phase change material. The second dielectric layer, the heat-spreading layer and the heat-buffering layer form a bottom electrode. A resistivity of the heat-buffering layer is less than a resistivity of the heat-spreading layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein.