Patent ID: 12249978

DETAILED DESCRIPTION

In some approaches, isolated bootstrapped switch circuits use capacitor charge pumps and digital level shifters for controlling the state of the switch. A charge pump is connected to the source of the switch and a latch biased from the charge pump generates switch control signals between source and gate. The present inventors have recognized that a problem with such a configuration is that the switch cannot be turned off when the drain potential is below the source potential.

Using various techniques of this disclosure, a charge pump is connected between the source and the body of the switch. Such a configuration avoids a condition in which the body diode opens for negative drain-to-source voltage (Vds) across the switch. Such a configuration also avoids a condition in which the switch control circuit generates control signals referenced to a body potential rather than a source potential, thereby allowing the switch to reliably turn off even for negative Vds. An additional gain stage ensures that the switch can be properly turned on. The techniques of this disclosure can be used to generate switches that enable highly linear processing of bipolar differential signals even far outside of the supply range.

The charge pump capacitors are usually significantly larger than the level shift capacitors. The size of the charge pump capacitors determines the driving strength of the charge pump. For minimizing total capacitance area, the charge pumps can be clocked at a higher rate than the switch itself.

The isolated bootstrapped switches of this disclosure can be used in, for example, input stages of switched capacitor analog-to-digital converters (ADCs), continuous time ADCs, chopped low offset amplifiers, etc. The ability to sample bipolar input signals at several megahertz even in the presence of fast common mode variations makes such switches the perfect choice for ADC input stages of battery management ICs.

FIG.1is a block diagram of an example of a bootstrapped switch circuit that can implement various techniques of this disclosure. The bootstrapped switch circuit100has an input terminal IN and an output terminal OUT and is coupled to a timing circuit102that provides one or more clock signals, such as the clock signals Phi1and Phi2, and their complements Phi1C and Phi2C. The timing circuit102is configured to receive a supply voltage VDD.

The bootstrapped switch circuit100includes a switch104, e.g., a field-effect transistor (FET), having a first terminal T1, e.g., a drain terminal, coupled to the input terminal IN, a second terminal T2, e.g., a source terminal, coupled to the output terminal OUT, and a control terminal T3, e.g., a gate terminal. The switch104includes a body diode106coupled between a fourth terminal T4, e.g., the body or substrate, of the switch104and the second terminal T2of the switch104.

The bootstrapped switch circuit100includes a charge pump108coupled to the timing circuit102, such as using capacitors C1and C2, and configured to receive the clock signals Phi1and Phi2. The charge pump108generates a charge pump voltage Vcp and is coupled to the fourth terminal T4of the switch104.

The bootstrapped switch circuit100includes a logic circuit110coupled to the timing circuit102, such as using capacitors C3and C4, and is configured to receive the clock signals Phi1cand Phi2c. The bootstrapped switch circuit100includes a gain stage112, e.g., a2X gain stage, coupled between an output114of the logic circuit110and the control terminal T3of the switch104. In some examples, the gain stage includes an amplifier circuit. The logic circuit110is configured to provide a control signal ON to the control terminal T3of the switch104.

As seen inFIG.1, the charge pump voltage Vcp is not connected to the source terminal T2of the switch104. Instead, the charge pump voltage Vcp is connected between the source terminal T2and the body terminal T4. The charge pump voltage Vcp is below the source potential and, as such, the body diode106sees different voltages.

In other approaches, the body diode106is coupled to terminal T1and if the voltage at the input terminal IN is greater than the voltage at the output terminal OUT, then the body diode106conducts and the switch104will not operate. However, using the techniques of this disclosure, and as shown inFIG.1, the body diode106only conducts when the voltage at the output terminal OUT is less than the voltage at the body connection. The body diode106will not immediately conduct, such as when the voltage at the input terminal IN is greater than the voltage at the output terminal OUT.

The charge pump108generates a voltage rail that is below the voltage at the input terminal IN. In order to turn the switch104ON, a voltage at the control terminal T3must be greater than the voltage at the input terminal IN. The gain stage112is used to ensure such a voltage is applied to the control terminal T3.

The charge pump108and the logic circuit110are controlled by the timing circuit102. The timing circuit102applies the clock signals Phi1and Phi2to the charge pump108and applies complementary clock signal Phi1cand Phi2cto the logic circuit110to control the switch104.

The bootstrapped switch circuit100ofFIG.1can be used as input stage of switched capacitor ADCs, continuous time ADCs, chopped low offset amplifiers, etc. For example, the output terminal OUT can be coupled to an ADC, such as shown inFIG.3.

FIG.2is a block diagram of another example of a bootstrapped switch circuit200that can implement various techniques of this disclosure. Some of the components inFIG.2are similar to components inFIG.1and use similar reference numbers. For purposes of conciseness, similar components will not be described in detail again.

InFIG.2, the logic circuit110is configured to receive the charge pump voltage Vcp and control the fourth terminal T4of the switch104. The charge pump108of the bootstrapped switch circuit200is configured to provide the charge pump voltage Vcp, developed across the charge pump capacitor Ccp, to the logic circuit110. The logic circuit110includes a first output204A configured to supply a first control signal ON to the control terminal T3of the switch104, e.g., gate terminal, via the gain stage112. In the configuration inFIG.2, the logic circuit110includes a second output204B configured to supply a second control signal ON_body to the fourth terminal T4of the switch104, e.g., the body terminal. In some examples, the first control signal ON and the second control signal ON_body are supplied concurrently. The control signal ON_body can be supplied by the charge pump voltage Vcp or the input voltage VIN.

When the logic circuit110applies a voltage to the gate of the switch104, the logic circuit110also applies a voltage to connect the body of the switch104to the source of the switch104. This is in contrast to the configuration shown inFIG.1in which the charge pump108is directly coupled to the fourth terminal T4and the voltages to the gate and body are not necessarily applied at the same time.

The larger the voltage between the source terminal and the body terminal, the lower the on resistance of the switch104. By using the techniques ofFIG.2, the body voltage is controlled together with the gate voltage to minimize the impact of the body-effect on the switch104on resistance.

The bootstrapped switch circuit200ofFIG.2can be used as an input stage of switched capacitor ADCs, continuous time ADCs, chopped low offset amplifiers, etc. For example, the output terminal OUT can be coupled to an ADC, such as shown inFIG.3.

FIG.3is a block diagram of an example of a single-ended implementation of an ADC input stage using the bootstrapped switch circuit techniques of this disclosure. Some of the components inFIG.3are similar to components inFIG.1and use similar reference numbers. For purposes of conciseness, similar components will not be described in detail again.

The circuit300includes a first bootstrapped switch circuit302P configured to receive a positive input voltage VINP at the positive input terminal INP, and a second bootstrapped switch circuit302M configured to receive a negative input voltage VINM at the negative input terminal INM. Each of the first bootstrapped switch circuit302P and the second bootstrapped switch circuit302M can be similar to the bootstrapped switch circuit200ofFIG.2. In some examples, the switch104P of the first bootstrapped switch circuit302P can be a P-type FET and the switch104M of the second bootstrapped switch circuit302M can be an N-type FET.

The first bootstrapped switch circuit302P is coupled to and controlled by a first timing circuit102P and the second bootstrapped switch circuit302M is coupled to and is controlled by a second timing circuit102M. In some examples, the timing circuit102P and the second timing circuit102M are the same timing circuit. In other examples, the timing circuit102and the second timing circuit102M are separate timing circuits.

InFIG.3, the first logic circuit110P is configured to receive the first charge pump voltage Vcpp and provide the first charge pump voltage Vcpp to the fourth terminal T4of the first switch104P. Similarly, the second logic circuit110M is configured to receive the second charge pump voltage Vcpn and provide the second charge pump voltage Vcpn to the fourth terminal T4of the second switch104M.

In the single-ended implementation shown inFIG.3, the circuit300operates by alternatingly connecting the first bootstrapped switch circuit302P and the second bootstrapped switch circuit302M to an ADC circuit304, such as using an input capacitor306coupled to the output terminal OUT of the first bootstrapped switch circuit302P and an input terminal308of the ADC circuit304. The output terminal OUT represents the output terminals of each of the first bootstrapped switch circuit302P and the second bootstrapped switch circuit302M electrically coupled together. In the example shown, the first timing circuit102P connects the input capacitor306first to the positive input voltage VINP by closing the switch104P. Then, the first timing circuit102P opens the switch104P and then closes the switch104M to connect the input capacitor306to the negative input voltage VINM. This process repeats.

Due to the charge pump108P and the charge pump108M, the body diode106P and the body diode106M, respectively, will not conductive if there is a negative input voltage. For example, if the negative input voltage VINM is greater than the positive input voltage VINP, the diodes will not conduct because the charge pumps provide additional room.

The configuration shown inFIG.3can sample negative differential voltages. The body diodes of the switch104P and the switch104M conduct when VINP-VINM <Vcp+0.6V.

FIG.4is a block diagram of an example of a fully differential techniques of this disclosure. Some of the components inFIG.4are similar to components inFIG.1and use similar reference numbers. For purposes of conciseness, similar components will not be described in detail again.

The circuit400includes a first bootstrapped switch circuit402P configured to receive a positive input voltage VINP at the positive input terminal INP, and a second bootstrapped switch circuit402M configured to receive a negative input voltage VINP at the negative input terminal INM. Each of the first bootstrapped switch circuit402P and the second bootstrapped switch circuit402M can be similar to the bootstrapped switch circuit200ofFIG.2. The switch104P of the first bootstrapped switch circuit402P, the switch104M of the second bootstrapped switch circuit402M, and the switches104A,104B of the third bootstrapped switch circuit402CM can be N-type FETs, for example.

The first bootstrapped switch circuit402P includes a charge pump and a logic circuit, shown as a combined charge pump and logic circuit404P for conciseness, coupled to a gain stage406P. Via the gain stage406P, the logic circuit404P supplies a control signal to the third terminal T3of the switch104P, e.g., the gate terminal. In some examples, the logic circuit404P includes a second output configured to supply a second control signal to the fourth terminal T4of the switch104P, e.g., the body terminal, like inFIG.2. In some examples, the first control signal and the second control signal are supplied concurrently.

The second bootstrapped switch circuit402M includes a charge pump and a logic circuit, shown as a combined charge pump and logic circuit404M for conciseness, coupled to a gain stage406M. Via the gain stage406M, the logic circuit404M supplies a control signal to the third terminal T3of the switch104M, e.g., the gate terminal. In some examples, the logic circuit404M includes a second output configured to supply a second control signal to the fourth terminal T4of the switch104M, e.g., the body terminal, like inFIG.2. In some examples, the first control signal and the second control signal are supplied concurrently.

The third bootstrapped switch circuit402CM includes an input terminal IN1. Unlike the first bootstrapped switch circuit402P and the second bootstrapped switch circuit402M, the third bootstrapped switch circuit402CM includes two switches104A,104B that are each electrically coupled to the input terminal IN1. The third bootstrapped switch circuit402CM includes a charge pump and a logic circuit, shown as a combined charge pump and logic circuit404CM for conciseness, coupled to a gain stage406CM. Via the gain stage406CM, the logic circuit404CM supplies a control signal to the third terminal T3of the switch104A, e.g., the gate terminal, and to the third terminal T3of the switch104B, e.g., the gate terminal. In some examples, the logic circuit404CM includes a second output configured to supply a second control signal to the fourth terminal T4of the switch104A, e.g., the body terminal, like inFIG.2, and to the fourth terminal T4of the switch104B, e.g., the body terminal. In some examples, the first control signal and the second control signal are supplied concurrently.

A first capacitor C3A is coupled between the positive input terminal INP of the first bootstrapped switch circuit402P and the input terminal IN1of the third bootstrapped switch circuit402CM. A second capacitor C3B is coupled between the negative input terminal INM of the second bootstrapped switch circuit402M and the input terminal IN1of the third bootstrapped switch circuit402CM. The input terminal IN1of the third bootstrapped switch402CM is configured to receive a common mode voltage VCM generated using the positive input voltage VINP and the negative input voltage VINM.

A timing circuit102is coupled to the charge pump and logic circuit404P, the charge pump and logic circuit404CM, and the charge pump and logic circuit404M, such as via capacitors C1P, C1CM, and C1M.

The third bootstrapped switch circuit402CM includes two output terminals. The output terminal OUT1inFIG.4represents the output terminal of the first bootstrapped switch circuit402P and a first one of the outputs of the third bootstrapped switch circuit402CM tied together. The output terminal OUT2inFIG.4represents the output terminal of the second bootstrapped switch circuit402M and a second one of the outputs of the third bootstrapped switch circuit402CM tied together.

In the fully differential implementation shown inFIG.4, the circuit400operates by only sampling two times half the input signal vs. a common mode voltage. First, the timing circuit102can control the first bootstrapped switch circuit402P to close the switch104P and control the second bootstrapped switch circuit402M to close the switch104M. After opening switches104P and402M, the timing circuit102can control the third bootstrapped switch circuit402CM to couple the voltage at OUT1to node IN1(the common mode voltage VCM) by closing the switch104A and couple the voltage at OUT2to node IN1(the common mode voltage VCM) by closing the switch104B. In this manner, the circuit400can sample half the signal onto capacitors C2A, C2B, which are coupled to the corresponding inputs of an ADC circuit408.

The configuration shown inFIG.4permits negative voltages that are even larger than those permitted by the circuit300ofFIG.3. The circuit400can sample negative differential voltages and the body diodes conduct when VINP-VINM<2x(Vcp+0.6V).

In some examples, the switches104P,104M,104A, and104B are N-type FETs. In other examples, the switches104P,104M,104A, and104B are P-type FETs.

FIG.5is an example of a timing diagram of various clock signals generated by a timing circuit. Clock signals PHI1and PHI2are shown at500and502, respectively. Clock signals PHI1and PHI2drive the charge pump, e.g., the charge pump108ofFIG.2. Clock signals PHI1cand PHI2care shown at504and506, respectively. Clock signals PHI1cand PHI2care applied to the logic circuit, e.g., the logic circuit110ofFIG.2, which drives the switches. A charge pump can be stronger the faster it is clocked. As such, the clock signals PHI1and PHI2are clocked at a faster rate than the clock signals PHI1cand PHI2c. In other words, the clock signals PHI1and PHI2have shorter pulse widths than those of the clock signals PHI1cand PHI2c.

FIG.6is a block diagram of another example of a fully differential techniques of this disclosure. Some of the components inFIG.6are similar to components inFIGS.1-3and use similar reference numbers. For purposes of conciseness, similar components will not be described in detail again.

The circuit600is a fully differential implementation of the circuit300ofFIG.3. The circuit600includes a first bootstrapped switch circuit602P configured to receive a positive input voltage VINP at the positive input terminal INP, and a second bootstrapped switch circuit602M configured to receive a negative input voltage VINP at the negative input terminal INM. The first bootstrapped switch circuit602P includes two gain stages112P1,112P2coupled to corresponding gate terminals of switches104P1,104P2, respectively. In the example shown, the switches104P1,104P2are P-type FETs.

The second bootstrapped switch circuit602M includes two gain stages112M1,112M2coupled to corresponding gate terminals of switches104M1,104M2, respectively. In the example shown, the switches104M1,104M2are N-type FETs.

The first bootstrapped switch circuit602P includes two output terminals and the second bootstrapped switch circuit602M includes two output terminals. The output terminal OUT1inFIG.6represents a first output terminal of the first bootstrapped switch circuit602P and a first output terminal of the second bootstrapped switch circuit602M electrically coupled together. The output terminal OUT2inFIG.6represents a second output terminal of the first bootstrapped switch circuit602P and a second output terminal of the second bootstrapped switch circuit602M electrically coupled together.

The circuit600can sample the differential input voltage between VINP and VINM onto capacitor C2A and C3B, which are coupled to the outputs OUT1and OUT2and corresponding inputs of an ADC circuit604.

VARIOUS NOTES

Each of the non-limiting aspects or examples described herein may stand on its own, or may be combined in various permutations or combinations with one or more of the other examples.

The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as “examples.” Such examples may include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

In the event of inconsistent usages between this document and any documents so incorporated by reference, the usage in this document controls.

In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.” In this document, the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated. In this document, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.” Also, in the following claims, the terms “including” and “comprising” are open-ended, that is, a system, device, article, composition, formulation, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

Method examples described herein may be machine or computer-implemented at least in part. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. An implementation of such methods may include code, such as microcode, assembly language code, a higher-level language code, or the like. Such code may include computer readable instructions for performing various methods. The code may form portions of computer program products. Further, in an example, the code may be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact discs and digital video discs), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), and the like.

The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. § 1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description as examples or embodiments, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments may be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.