Patent ID: 12199626

DETAILED DESCRIPTION

Hereinafter, examples will be described in detail with reference to the accompanying drawings. The scope of the right, however, should not be construed as limited to the example embodiments set forth herein. In the drawings, like reference numerals are used for like elements.

Various modifications may be made to the examples. Here, the examples are not construed as limited to the disclosure and should be understood to include all changes, equivalents, and replacements within the idea and the technical scope of the disclosure.

Although terms of “first” or “second” are used to explain various components, the components are not limited to the terms. These terms should be used only to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly the second component may also be referred to as the first component.

The terminology used herein is for the purpose of describing particular examples only and is not to be limiting of the examples. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, “A or B”, “at least one of A and B”, “at least one of A or B”, “A, B or C”, “at least one of A, B and C”, and “at least one of A, B, or C,” each of which may include any one of the items listed together in the corresponding one of the phrases, or all possible combinations thereof. It will be further understood that the terms “comprises/comprising” and/or “includes/including” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

Unless otherwise defined, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, such as those defined in commonly-used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

When describing the examples with reference to the accompanying drawings, like reference numerals refer to like constituent elements and a repeated description related thereto will be omitted. In the description of example embodiments, detailed description of well-known related structures or functions will be omitted when it is deemed that such description will cause ambiguous interpretation of the present disclosure.

Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings.

FIG.1illustrates a digital sensor according to an example embodiment.

Referring toFIG.1, a dynamic high-resolution analog to digital converter (ADC)101and a transducer102are shown. The dynamic high-resolution ADC101and the transducer102may be included in a digital sensor.

The transducer102may measure a physical quantity. The transducer102may measure a physical quantity, such as a temperature, a pressure, and a voltage. The physical quantity measured by the transducer102may be an analog signal that is a continuous signal. In order for the analog signal measured by the transducer102to be processed and stored in an electronic device, an ADC may convert the analog signal into a digital signal or digital data that is a discrete signal.

The dynamic high-resolution ADC101may receive the analog signal measured by the transducer102. The dynamic high-resolution ADC101may convert an analog signal, which is a continuous signal, into a digital signal, which is a discrete signal. A dynamic range or a full scale indicating a range of signals that may be normally converted and resolution indicating the accuracy of a measured value may matter to the dynamic high-resolution ADC101.

The resolution may include a temporal resolution and a size resolution. The temporal resolution may be related to a sample per second (SPS) indicating a speed at which an analog signal is converted into a digital signal. Herein, the resolution may refer to the size resolution. The ADC may be required to increase a signal to noise ratio (SNR) to improve the dynamic range and the resolution. The SNR of the ADC may be proportional to the effective number of bits (ENOB) representing a digital value. The number of ENOB in the ADC may need to be great enough to increase the SNR. Accordingly, an input signal of the ADC may need to be dynamically matched with the size of a full scale range (FSR) of the ADC.

The ADC may include a flash ADC, a successive approximation register (SAR) ADC, a pipeline ADC, and a sigma delta ADC. The flash ADC may include a comparator, which samples an input voltage and compares the input voltage to a reference voltage, and a decoder, which converts a digital signal to digital data. The flash ADC may improve the dynamic range and the resolution according to an increase in the number of bits but may increase complexity as the number of comparators increases proportionally to the power of two. The SAR ADC, the pipeline ADC, and the sigma delta ADC may be used to improve the complexity of the flash ADC in implementation.

The SAR ADC may repeat one unit ADC as many as the number of bits according to a clock and decode the one unit ADC. The unit ADC may include a sampling and hold amplifier (SHA), a comparator, a digital to analog converter, a subtractor, and an amplifier. The SAR ADC may repeat one unit ADC from a most significant bit (MSB) by as many as the number of bits.

The pipeline ADC may increase the number of bits and reduce ADC complexity by serially connecting a plurality of sub-range ADCs. For example, the pipeline ADC may use an 8-bit subrange ADC and a 4-bit subrange ADC to provide a 12-bit ADC. The sigma delta ADC may convert an analog signal to a digital signal in a delta manner.

Since the transducer102needs to measure a physical quantity in a measurement unit, the transmitter102may not use an automatic gain control (AGC) that greatly amplifies a small signal and amplifies a large signal to be small in order to improve resolution.

Described hereinafter in detail is a dynamic high-resolution ADC for a high-resolution digital sensor that may increase a dynamic range and resolution of a digital sensor.

FIG.2is a block diagram illustrating a digital sensor according to an example embodiment.

Referring toFIG.2, a transducer102and a dynamic high-resolution ADC101are shown. A digital sensor may include the transducer102and the dynamic high-resolution ADC101.

The transducer102may convert a physical quantity into an electrical signal. The transducer102may convert a physical quantity, such as temperature, solar radiation, and a voltage, into an electrical signal. The electrical signal converted by the transducer102may be an analog signal. In order for an electronic device to process and store an analog signal, the analog signal may need to be converted into a digital signal or digital data. The dynamic high-resolution ADC101may convert the analog signal received from the transducer102into digital data.

The dynamic high-resolution ADC101may include a sample and hold circuit201, a dynamic amplifier202, a residue signal amplifier203, and an ADC204, a digital to analog converter (DAC)205, and a decoder206.

The sample and hold circuit201may sample the analog signal received from the transducer102in units of time. The sample and hold circuit201may hold the magnitude of the analog signal sampled in units of time during a sampling period.

The dynamic amplifier202may be connected to the sample and hold circuit201. The dynamic amplifier202may amplify, by as much as Ad, the sampled-and-held analog signal, received from the sample and hold circuit. Admay be a gain of the dynamic amplifier202. Admay be a first gain of the dynamic high-resolution ADC101. Where an output signal received by the ADC204exceeds a range of an input signal that the ADC204may receive, the gain Adof the dynamic amplifier202may reduce by a factor of ½. The gain Adof the dynamic amplifier202may reduce by a factor of ½ until the output signal received by the ADC204is within the range of an input signal that the ADC204may receive. That is, where the output signal received by the ADC204exceeds the range of an input signal that the ADC204may receive so clipping occurs in which a part of the output of the ADC204is cut off, the gain Adof the dynamic amplifier202may reduce by a factor of ½ until the clipping does not occur. Admay be initialized to an initial value for each sampling period. Such a process may increase the ENOB by dynamically matching the input signal of the ADC204to the FSR of the ADC204to improve a noise figure.

The residue signal amplifier203may be connected to the dynamic amplifier202and the DAC205. The residue signal amplifier203may calculate a difference between an output signal of the dynamic amplifier202and an output signal of the DAC205. The residue signal amplifier203may amplify, by as much as Ar, the difference between the output signal of the dynamic amplifier202and the output signal of the DAC205. Armay be a gain of the residue signal amplifier203. Armay be a second gain of the dynamic high-resolution ADC101. An initial value of Armay be set to 1. Where the output signal received by the ADC204does not exceed a range of an input signal that the ADC204may receive, the gain Arof the residue signal amplifier203may be set to be equal to the output of the ADC204. Armay be initialized to the initial value of 1 for each sampling period.

The ADC204may be connected to the residue signal amplifier203. The ADC204may convert an analog signal into a digital signal. The ADC204may convert the output signal received from the residue signal amplifier203into a digital signal. Where the output signal received by the ADC204exceeds a range of an input signal that the ADC204may receive, the gain Adof the dynamic amplifier202may reduce by a factor of ½. The gain Adof the dynamic amplifier202may reduce by a factor of ½ until the output signal received by the ADC204is within the range of an input signal that the ADC204may receive. That is, where the output signal received by the ADC204exceeds the range of an input signal that the ADC204may receive so clipping occurs in which a part of the output of the ADC204is cut off, the gain Adof the dynamic amplifier202may reduce by a factor of ½ until the clipping does not occur. The ADC204may not be limited to a cyclic ADC, a pipeline ADC, and the like, and various structures of the ADC204may be used.

The DAC205may be connected to the decoder206. The DAC205may convert a digital signal into an analog signal. The DAC205may convert the digital signal received from the decoder206into an analog signal. An output initial value of the DAC205may be 0 and may be initialized to 0 for every sampling period.

The decoder206may be connected to the ADC204. The decoder206may decode, into digital data, the output signal received from the ADC204as an input. The decoder206may control the dynamic amplifier202and the residue signal amplifier203. Specifically, the decoder206may control the gains of the dynamic amplifier202and the residue signal amplifier203. The decoder206may control the gain Adof the dynamic amplifier202to be reduced by a factor of ½ until the input signal of the ADC204is within the range of an input signal that the ADC204may receive so that clipping does not occur where a part of the output signal of the ADC204is cut off.

The decoder206may set, to the gain Arof the residue signal amplifier203, the output of the ADC204when the clipping, in which a part of the output signal of the ADC204is cut off, does not occur since the input signal of the ADC204is within the range of an input signal that the ADC204may receive. As a result, the decoder206may control the output of the ADC204and the input of the DAC205.

Described hereinafter is a method of converting analog to digital by a dynamic high-resolution ADC.

FIG.3is a flowchart of converting an analog signal into digital data, according to an example embodiment.

In operation301, a dynamic high-resolution ADC101may sample and hold a sensor signal received from a sensor. Specifically, a sample and hold circuit201included in the dynamic high-resolution ADC101may sample the sensor signal received from the sensor in units of time to hold the size of the sensor signal during a sampling period. The sensor signal may be an analog signal.

In operation302, the dynamic high-resolution ADC101may scale the analog signal to an appropriate size and convert the scaled and sampled-and-held analog signal to a first digital signal. Specifically, a dynamic amplifier202may scale the analog signal to an appropriate size and an ADC204may convert the scaled and sampled-and-held analog signal into the first digital signal. The scaled and sampled—and held analog signal may be within a range of an input signal that the ADC204may receive. Clipping may not occur where a part of the signal is cut off for the digital signal, into which the ADC204converts the scaled and sampled—and held signal as an input.

In operation303, the dynamic high-resolution ADC101may amplify a micro signal not converted into a first digital signal and convert the micro signal into a second digital signal. Specifically, a residue signal amplifier203may amplify a difference between an output signal of the dynamic amplifier202and an output signal of the DAC205. The difference between the output signal of the dynamic amplifier202and the output signal of the DAC205may be the micro signal of the analog signal not converted into the first digital signal. The ADC204may convert, into the second digital signal, the amplified difference between the output signal of the dynamic amplifier202and the output signal of the DAC205.

In operation304, the dynamic high-resolution ADC101may convert a sensor signal into digital data, based on the first digital signal and the second digital signal. Specifically, a decoder206may convert the sensor signal, which is an analog signal, into digital data, based on the first digital signal of operation302and the second digital signal of operation303.

Hereinafter, a dynamic ADC (DADC) corresponding to operation302is described.

FIG.4is a flowchart illustrating a DADC operation according to an example embodiment.

In operation401, where clipping occurs in an ADC204, a decoder206may control a gain Adof a dynamic amplifier202to be repeatedly reduced by a factor of ½ until the clipping does not occur. In this case, where the number of repetition is i, i may refer to the number of loops. For example, where the clipping occurs in the ADC204and the gain Adreduces by 3 times to ⅛ until the clipping does not occur, i may be 3. The initial value of i may be 0. Admay be a gain of the dynamic amplifier202. The initial value of Admay be Ad,0. Armay be a gain of a residue signal amplifier203. The initial value of Armay be 1 as Ar,0. i, Ad, and Armay be initialized to initial values for each sampling period.

In operation402, the dynamic high-resolution ADC101may determine whether da(k), which is an output of the ADC204, is a maximum. Whether da(k) is a maximum may be determined by whether all output bits of the ADC204are used. For example, where the output bits of the ADC204are 8 bits and da(k) is “11111111”, the output bits of da(k) may be all used and thus be a maximum. Where the da(k) is a maximum, a signal input to the ADC204exceeds a range of an input signal that the ADC204may receive and there may be clipping in which a part of the output is cut off. Thus, where da(k) is a maximum, the dynamic high-resolution ADC101may perform operation403for controlling the gain Adof the dynamic amplifier202. Where da(k) is not a maximum, no clipping has occurred, so the dynamic high-resolution ADC101may perform operation406.

In operation403, the dynamic high-resolution ADC101may control the gain Adof the dynamic amplifier202to be (½)itimes an initial value. The decoder206of the dynamic high-resolution ADC101may control the gain Adof the dynamic amplifier202to be (½)itimes the initial value. That is, whenever clipping occurs, the decoder206may control the gain Adby ½ times the initial value. When the gain Adreduces, the signal input to the ADC204may be controlled to be within the range of an input signal that the ADC204may receive.

In operation404, the dynamic high-resolution ADC101may determine whether i is less than EMAX. EMAXmay refer to the maximum number of extension bits. Where i is greater than or equal to EMAX, operation406may be performed. Where i is less than EMAX, operation405may be performed.

In operation405, the dynamic high-resolution ADC101may repeat operations402to404by adding 1 to the current i. Specifically, the decoder206may add 1 to i and perform operations402and403to control the first gain Ad.

In operation406, the dynamic high-resolution ADC101may determine the number of extension bits E to be i, which is the number of loops. Since da(k) is not a maximum, the dynamic high-resolution ADC101may determine a first digital signal dd(k), into which the ADC101converts a sampled-and-held analog signal, to be da(k), which is the output of the ADC204. In the DADC operation, since the second gain Aris maintained at 1, the first digital signal may be the output signal of the ADC204when the second gain is 1.

In operation407, the dynamic high-resolution ADC101may determine Ar, which is a gain of the residue signal amplifier203, to be equal to Ar,0*dd(k). Since Ar,0is 1, Armay be determined by dd(k), which is the first digital signal. Armay be controlled to become dd(k), which is the first digital signal. The decoder206may control Arto become dd(k), which is the first digital signal.

Hereinafter, a residue ADC (RADC) operation corresponding to operation303ofFIG.3is described.

FIG.5is a flowchart illustrating an RADC operation according to an example embodiment.

In operation501, a dynamic high-resolution ADC101may convert a second digital signal that is an output of the RADC operation. The second digital signal may be dr(k). The second digital signal dr(k) may be determined by da(k) that is an output of the ADC204. da(k) ofFIG.5may be a signal obtained by amplifying a difference between an output signal of a dynamic amplifier202and an output signal of a DAC205by as much as a gain Arof a residue signal amplifier203determined in the DADC operation ofFIG.4and by the ADC204converting the signal into a digital signal. Since Ar, which is a second gain, is controlled to be dd(k) in the DADC operation, the second digital signal dr(k) may be an output signal of the ADC204when the second gain is not 1.

In this case, the difference between the output signal of the dynamic amplifier202and the output signal of the DAC205may be an analog signal not converted into a digital signal in the DADC operation. The difference between the output signal of the dynamic amplifier203and the output signal of the DAC205may be a micro signal not converted into a digital signal in the DADC operation. Accordingly, the second digital signal dr(k) may be a signal obtained by converting, into a digital signal, a sampled-and-held analog signal not converted into the first digital signal in the DADC operation.

Described hereinafter in detail is a method of converting, into digital data, an analog signal received from a sensor based on the first digital signal dd(k), which is the output of the DADC operation, and the second digital signal dr(k), which is the output of the RADC operation.

FIG.6is a flowchart illustrating a method in which a decoder decodes a digital signal according to an example embodiment.

In operation601, a dynamic high-resolution ADC101may read E, dd(k), and dr(k) determined in the previous DADC operation and RADC operation. Specifically, a decoder206may read E, dd(k), and dr(k) determined in the previous DADC and RADC operations. The decoder206may decode a digital signal into digital data based on E, dd(k), and dr(k).

In operation602, the dynamic high-resolution ADC101may determine ER, which is the number of residual extension bits, to be ER=EMAX−E. Specifically, the decoder206may determine ER, which is the number of residual extension bits, by a difference between EMAX, which is the maximum number of extension bits, and E. The decoder206may determine do,0:MSB(k) to be 0. do,0:MSB(k) may be an initial digital data output for a kth sampling value of the decoder206and be determined to be 0 for bits from the least significant bit (LSB) to the most significant bit (MSB) of the initial digital data output. That is, do,0:MSB(k) may be determined to be 0 since it is before decoding of the decoder206. In operation603, the output of the decoder206may be determined as follows.
do,(N-ER):(MSB-ER)(k)dd,0:MSB(k)(1)
do,0:(N-ER-1)(k)=dr,ER:MSB(k)  (2)

That is, MSB-ERto N-ERamong the output bits of the decoder206may be decoded values of the first digital signal dd(k). Also, N-ER−1 to LSB do,0among the output bits of the decoder206may be decoded values from the MSB to ER of the second digital signal dr(k). In this case, N may be the number of bits of the ADC204. N may be the number of output bits of the ADC204. That is, the ADC204may be the number of bits of the first digital signal and the second digital signal. According to an example embodiment, N may be 8 since the number of output bits of the first digital signal and the second digital signal, which are the outputs of the ADC204, is 8.

Accordingly, referring toFIG.6, the input signal of the amplifier may be controlled to an appropriate level in the DADC operation by using the number of extension bits E. In this case, the ENOB may be increased to improve a dynamic range and resolution. For example, when the ADC204is 8 bits and the number of maximum extension bits is 4 bits, the output bits of the dynamic high-resolution ADC101may be up to 16. Accordingly, the dynamic high-resolution ADC101may measure a physical quantity up to 216(65,536) level.

Hereinafter, a method in which a decoder decodes a digital signal is described with an example.

FIG.7A to7Care examples illustrating a method in which a decoder decodes a digital signal, according to an example embodiment.

Hereinafter, it is assumed that EMAX=4 and the number of bits of the ADC204is 8 bits. Accordingly, the first digital signal dd(k) and the second digital signal dr(k) may be 8 bits. However, the foregoing is only an example and may not be limited thereto. do,n, which is a bit of output digital data of a decoder206, is denoted as do inFIG.7A to7Cfor convenience. For example, do,15, which is the MSB among bits of the output digital data of the decoder206, may be referred to as d15for convenience.

FIG.7Ais a diagram illustrating a method in which the decoder206decodes dd(k) and dr(k) and converts the dd(k) and dr(k) into digital data where E=0.FIG.7Bis a diagram illustrating a method in which the decoder206decodes dd(k) and dr(k) and converts the dd(k) and dr(k) into digital data where E=4.FIG.7Cis a diagram illustrating a method in which the decoder206decodes dd(k) and dr(k) and converts the dd(k) and dr(k) into digital data where E=0 in a sub-LSB extension type.

Where the number of bits of an ADC204is N and the maximum number of extension bits is EMAX, L, which is the number of bits of the decoded output digital data, may be N+EMAX.

InFIG.7A, it may be determined that ER=4 since EMAX=4 and E=0, according to operation602ofFIG.6. Since the number of bits of the ADC204is 8 bits, the decoder206may output up to 16 bits. Accordingly, the MSB of the output digital data of the decoder206may be determined to be d15and the LSB may be determined to be d0. The MSBs of the first digital signal dd(k) and the second digital signal dr(k) may be determined to be dd7and dr7, respectively.

Accordingly, referring to operation603ofFIG.6, d11, which is d15-4 of do(k), to d4, which is d8-4, may be decoded as dd7to dd0of the first digital signal. Also, d3, which is d8-4-1of do(k), to d0may be decoded as dr7to dr4of the second digital signals. In this case, d13, which exceeds d12, to d15, which is the MSB of do(k), may be decoded as 0.

InFIG.7B, it may be determined that ER=0 since EMAX=4 and E=4, according to operation602ofFIG.6. Since the number of bits of the ADC204is 8 bits, the decoder206may output up to 16 bits. Accordingly, the MSB of the output digital data of the decoder206may be determined to be d15and the LSB may be determined to be do. The MSBs of the first digital signal dd(k) and the second digital signal dr(k) may be determined to be dd7and dr7, respectively.

Accordingly, referring to operation603ofFIG.6, d15, which is d15-0of do(k), to d8, which is d8-0, may be decoded as dd7to dd0of the first digital signals. Also, d7, which is d8-0-1of do(k), to d0may be decoded as dr7to dr0of the second digital signals.

FIG.7Cmay be a sub-LSB extension type. Since E=0 in inFIG.7C, the decoder206may decode a digital signal as shown inFIG.7A. However, the decoder206may add a sub LSB for extension to the LSB of do.

FIG.8is a diagram illustrating analog-to-digital conversion according to an example embodiment.

According to an example embodiment, in operation801, a sample and hold circuit201may receive an analog signal from a sensor, sample the received analog signal, and hold a size of the analog signal during a sampling period.

According to an example embodiment, in operation802, a dynamic amplifier202receiving the sampled-and-held analog signal from the sample and hold circuit201may amplify the size of the sampled-and-held analog signal. A residue signal amplifier203, which is connected to the dynamic amplifier202and a DAC205and amplifies a difference between two signals input by the dynamic amplifier202and the DAC205, and an ADC204, which is connected to the residue signal amplifier203, may convert the amplified size of the sampled-and-held analog signal into a first digital signal.

According to an example embodiment, the first digital signal may refer to the sampled-and-held analog signal converted into a digital signal, wherein the sampled-and-held analog signal is controlled to be within the range of an input signal that the ADC204may receive and the controlled sampled-and-held signal is converted into the digital signal.

According to an example embodiment, operation802may further include operation A that determines whether the output signal of the ADC204, to which the sampled-and-held analog signal is input, is the maximum output signal of the ADC204, based on the first gain of the dynamic amplifier202and the second gain of the residual amplifier203.

According to an example embodiment, where the output signal of the ADC204, to which the sample-and-hold analog signal is input, is the maximum output signal of the ADC204, operation802may further include B operation that controls the first gain to be ½ times the current first gain.

According to an example embodiment, operation802may further include operation C determining whether the number of loops is the maximum number of extension bits.

According to an example embodiment, where the number of loops is the maximum number of extension bits, operation802may further include operation D, in which the ADC204converts the sampled-and-held analog signal into the first digital signal, based on the controlled first gain, the maximum number of extension bits, and the second gain.

According to an example embodiment, in operation802, the dynamic high-resolution ADC101may determine the number of extension bits to be the number of loops and further include operation E controlling the second gain with the first digital signal where the output signal of the ADC, to which the sampled-and-held analog signal is input, is less than the maximum output signal of the ADC.

According to an example embodiment, where the number of loops is less than the maximum number of extension bits, operation802may increase the number of loops by 1 and further include operation F repeating operations A to D.

According to an example embodiment, the first gain may be initialized to an initial value for every sampling period.

According to an example embodiment, the second gain may have an initial value of 1 and may be initialized to the initial value for every sampling period.

According to an example embodiment, in operation803, the ADC204may convert, into the second digital signal, a signal not converted into the first digital signal among sampled-and-held analog signals.

According to an example embodiment, operation803may further include an operation amplifying, by as much as the second gain, a difference between the sampled-and-held analog signal amplified by the dynamic amplifier202and the first digital signal converted into the analog signal by the DAC205.

According to an example embodiment, operation803may include an operation converting the signal amplified by the ADC204into the second digital signal.

According to an example embodiment, in operation804, the decoder206may be connected to the ADC204. The decoder206may decode the analog signal into digital data based on the first digital signal and the second digital signal.

The components described in the example embodiments may be implemented by hardware components including, for example, at least one digital signal processor (DSP), a processor, a controller, an application-specific integrated circuit (ASIC), a programmable logic element, such as a field programmable gate array (FPGA), other electronic devices, or combinations thereof. At least some of the functions or the processes described in the example embodiments may be implemented by software, and the software may be recorded on a recording medium. The components, the functions, and the processes described in the example embodiments may be implemented by a combination of hardware and software.

The method according to example embodiments may be written in a computer-executable program and may be implemented as various recording media such as magnetic storage media, optical reading media, or digital storage media.

Various techniques described herein may be implemented in digital electronic circuitry, computer hardware, firmware, software, or combinations thereof. The implementations may be achieved as a computer program product, i.e., a computer program tangibly embodied in an information carrier, e.g., in a machine-readable storage device (for example, a computer-readable medium) or in a propagated signal, for processing by, or to control an operation of, a data processing apparatus, e.g., a programmable processor, a computer, or multiple computers. A computer program, such as the computer program(s) described above, may be written in any form of a programming language, including compiled or interpreted languages, and may be deployed in any form, including as a stand-alone program or as a module, a component, a subroutine, or other units suitable for use in a computing environment. A computer program may be deployed to be processed on one computer or multiple computers at one site or distributed across multiple sites and interconnected by a communication network.

Processors suitable for processing of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read-only memory or a random-access memory, or both. Elements of a computer may include at least one processor for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer also may include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks. Examples of information carriers suitable for embodying computer program instructions and data include semiconductive wire memory devices, e.g., magnetic media such as hard disks, floppy disks, and magnetic tape, optical media such as compact disk read only memory (CD-ROM) or digital video disks (DVDs), magneto-optical media such as floptical disks, read-only memory (ROM), random-access memory (RAM), flash memory, erasable programmable ROM (EPROM), or electrically erasable programmable ROM (EEPROM). The processor and the memory may be supplemented by, or incorporated in special purpose logic circuitry.

In addition, non-transitory computer-readable media may be any available media that may be accessed by a computer and may include both computer storage media and transmission media.

Although the present specification includes details of a plurality of specific example embodiments, the details should not be construed as limiting any invention or a scope that can be claimed, but rather should be construed as being descriptions of features that may be peculiar to specific example embodiments of specific inventions. Specific features described in the present specification in the context of individual example embodiments may be combined and implemented in a single example embodiment. On the contrary, various features described in the context of a single example embodiment may be implemented in a plurality of example embodiments individually or in any appropriate sub-combination. Furthermore, although features may operate in a specific combination and may be initially depicted as being claimed, one or more features of a claimed combination may be excluded from the combination in some cases, and the claimed combination may be changed into a sub-combination or a modification of the sub-combination.

Likewise, although operations are depicted in a specific order in the drawings, it should not be understood that the operations must be performed in the depicted specific order or sequential order or all the shown operations must be performed in order to obtain a preferred result. In specific cases, multitasking and parallel processing may be advantageous. In addition, it should not be understood that the separation of various device components of the aforementioned example embodiments is required for all the example embodiments, and it should be understood that the aforementioned program components and apparatuses may be integrated into a single software product or packaged into multiple software products.

The example embodiments disclosed in the present specification and the drawings are intended merely to present specific examples in order to aid in understanding of the present disclosure, but are not intended to limit the scope of the present disclosure. It will be apparent to those skilled in the art that various modifications based on the technical spirit to of the present disclosure, as well as the disclosed example embodiments, can be made.