Patent ID: 12224018

DETAILED DESCRIPTION

A semiconductor storage device of the present embodiment includes: a first block including a first memory cell; a second block including a second memory cell; a first local word line connected to a gate of the first memory cell; a second local word line connected to a gate of the second memory cell; a bit line electrically connected to one end of the first memory cell; and a global word line. The semiconductor storage device also includes: a voltage generation circuit configured to generate and supply a read voltage to the global word line; a first transfer transistor connected between the global word line and the first local word line; a second transfer transistor connected between the global word line and the second local word line; a first block decoder configured to supply either one of a first selection signal or a first non-selection signal to a gate of the first transfer transistor in response to a block address input thereto; a second block decoder configured to supply either one of a second selection signal or a second non-selection signal to a gate of the second transfer transistor in response to the block address input thereto; and a control unit configured to perform a read operation to either one of the first memory cell or the second memory cell in response to a read command accompanied with the block address. The voltage generation circuit is further configured to generate and supply a first power voltage and a second power voltage to each of the first block decoder ant the second block decoder. During the read operation, a value of the first power voltage is changed between a first set value and a second set value lower than the first set value, and a value of the second power voltage is changed between a third set value lower than the first set value and a fourth set value lower than both of the second set value and the third set value, the first set value being larger than zero volt, the fourth set value being lower than zero volt.

An embodiment will be described below with reference to the accompanying drawings.

First Embodiment

(1. Configuration)

(1-1. Configuration of Memory System)

FIG.1is a block diagram illustrating an exemplary configuration of a memory system according to an embodiment. The memory system of the embodiment includes a memory controller1and a non-volatile memory2as a semiconductor storage device. The memory system is connectable to a host. The host is an electronic device such as a personal computer or a portable terminal.

The non-volatile memory2is a memory configured to store data in a non-volatile manner and includes, for example, a NAND memory (NAND flash memory). The non-volatile memory2is, for example, a NAND memory including a memory cell capable of storing three bits, that is, a 3 bit/Cell (triple level cell (TLC)) NAND memory. The non-volatile memory2may be a 1 bit/Cell NAND memory or a NAND memory capable of performing storage in a plurality of bits, such as a 2 bit/Cell, 4 bit/Cell or greater NAND memory. Typically, the non-volatile memory2is constituted by a plurality of memory chips.

The memory controller1controls data writing to the non-volatile memory2in accordance with a writing request from the host. The memory controller1also controls data reading from the non-volatile memory2in accordance with a read request from the host. A chip enable signal/CE, a ready/busy signal/RB, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal/WE, read enable signals RE and/RE, a write protect signal/WP, signals DQ <7:0> as data, and data strobe signals DQS and/DQS are transmitted and received between the memory controller1and the non-volatile memory2. Note that a symbol “/” added to a signal name indicates active low.

For example, the non-volatile memory2and the memory controller1are each formed as a semiconductor chip (hereinafter also simply referred to as “chip”).

The chip enable signal/CE is a signal for selecting and enabling a particular memory chip of the non-volatile memory2. The ready/busy signal/RB is a signal for indicating whether the non-volatile memory2is in a ready state (state in which a command from outside can be received) or a busy state (state in which a command from outside cannot be received). The memory controller1can know a state of the non-volatile memory2by receiving a signal RB. The command latch enable signal CLE is a signal indicating that the signals DQ <7:0> are commands. The command latch enable signal CLE enables latch of a command transmitted as a signal DQ at a command register in a selected memory chip in the non-volatile memory2. The address latch enable signal ALE is a signal indicating that the signals DQ <7:0> are addresses. The address latch enable signal ALE enables latch of an address transmitted as a signal DQ at an address register in a selected memory chip in the non-volatile memory2. The write enable signal/WE is a signal for taking a received signal into the non-volatile memory2and is asserted each time a command, an address, or data is received by the memory controller1. The non-volatile memory2is instructed to take in the signals DQ <7:0> when the signal/WE is at “Low (L)” level.

The read enable signals RE and/RE are signals for the memory controller1to read data from the non-volatile memory2. For example, the read enable signals RE and/RE are used to control an operation timing of the non-volatile memory2when the signals DQ <7:0> are output. The write protect signal/WP is a signal for instructing the non-volatile memory2to inhibit data writing and erasure. The signals DQ <7:0> are main bodies of data transmitted and received between the non-volatile memory2and the memory controller1and include commands, addresses, and data. The data strobe signals DQS and/DQS are signals for controlling input-output timings of the signals DQ <7:0>.

The memory controller1includes a random access memory (RAM)11, a processor12, a host interface13, an error check and correct (ECC) circuit14, and a memory interface15. The RAM11, the processor12, the host interface13, the ECC circuit14, and the memory interface15are connected to one another through an internal bus16.

The host interface13outputs, to the internal bus16, for example, a request and user data (write data) received from the host. In addition, the host interface13transmits, to the host, for example, user data read from the non-volatile memory2and a response from the processor12.

The memory interface15controls, based on an instruction from the processor12, processing of writing user data or the like to the non-volatile memory2and processing of reading user data or the like from the non-volatile memory2.

The processor12collectively controls the memory controller1. The processor12is, for example, a central processing unit (CPU) or a micro processing unit (MPU). When having received a request from the host through the host interface13, the processor12performs control in accordance with the request. For example, in accordance with a request from the host, the processor12instructs the memory interface15to write user data and parity to the non-volatile memory2. In addition, in accordance with a request from the host, the processor12instructs the memory interface15to read user data and parity from the non-volatile memory2.

The processor12determines, for user data accumulated in the RAM11, a storage region (memory region) in the non-volatile memory2. The user data is stored in the RAM11through the internal bus16. The processor12performs the memory region determination for data (page data) per page as a unit of writing. In the present specification, unit data is defined to be user data stored in a page of the non-volatile memory2. The unit data is typically encoded by the ECC circuit14and stored in the non-volatile memory2as a code word. In the present embodiment, encoding is not essential. The memory controller1may store the unit data in the non-volatile memory2without encoding, butFIG.1illustrates an exemplary configuration in which encoding is performed. When the memory controller1does not perform encoding, the page data is same as the unit data. One code word may be generated based on one unit data or based on division data into which the unit data is divided. Alternatively, one code word may be generated by using a plurality of pieces of unit data.

The processor12determines, for each unit data, a memory region in the non-volatile memory2at a writing destination. A physical address is allocated to each memory region in the non-volatile memory2. The processor12manages a memory region at the writing destination of each unit data by using the physical address. The processor12designates the determined memory region (physical address) and instructs the memory interface15to write user data to the non-volatile memory2. The processor12manages correspondence between a logical address (logical address managed by the host) and a physical address of user data. When having received a read request including a logical address from the host, the processor12specifies a physical address corresponding to the logical address and instructs, with designation of the physical address, the memory interface15to read user data.

The ECC circuit14generates a code word by encoding user data stored in the RAM11. In addition, the ECC circuit14decodes a code word read from the non-volatile memory2.

The RAM11temporarily stores user data received from the host until the user data is stored in the non-volatile memory2, and temporarily stores data read from the non-volatile memory2until the data is transmitted to the host. The RAM11is a general-purpose memory such as a static random access memory (SRAM) or a dynamic random access memory (DRAM).

In the exemplary configuration illustrated inFIG.1, the memory controller1includes the ECC circuit14and the memory interface15. However, the ECC circuit14may be built in the memory interface15. Alternatively, the ECC circuit14may be built in the non-volatile memory2.

When having received a writing request from the host, the memory system operates as follows. The processor12temporarily stores data as a writing target in the RAM11. The processor12reads data stored in the RAM11and inputs the data to the ECC circuit14. The ECC circuit14encodes the input data and inputs a resulting code word to the memory interface15. The memory interface15writes the input code word to the non-volatile memory2.

When having received a read request from the host, the memory system operates as follows. The memory interface15inputs a code word read from the non-volatile memory2to the ECC circuit14. The ECC circuit14decodes the input code word and stores resulting decoded data in the RAM11. The processor12transmits the data stored in the RAM11to the host through the host interface13.

(1-2. Configuration of Non-Volatile Memory)

FIG.2is a block diagram illustrating an exemplary configuration of the non-volatile memory of the present embodiment. The non-volatile memory2includes a logic control circuit21, an input-output circuit22, a memory cell array23, a sense amplifier24, a row decoder25, a register26, a sequencer27, a voltage supply circuit28, an input-output pad group32, a logic control pad group34, and a power source inputting terminal group35.

The memory cell array23includes a plurality of blocks. Each of these plurality of blocks BLK includes a plurality of memory cell transistors (memory cells). A plurality of bit lines, a plurality of word lines, a source line, and the like are disposed in the memory cell array23to control voltage applied to the memory cell transistors. A specific configuration of each block BLK will be described later.

The input-output pad group32includes a plurality of terminals (pads) corresponding to the signals DQ <7:0> and the data strobe signals DQS and/DQS to transmit and receive signals including data to and from the memory controller1.

The logic control pad group34includes a plurality of terminals (pads) corresponding to the chip enable signal/CE, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal/WE, the read enable signals RE and/RE, and the write protect signal/WP to transmit and receive signals to and from the memory controller1.

The signal/CE enables selection of the non-volatile memory2. The signal CLE enables latch of a command transmitted as a signal DQ at a command register. The signal ALE enables latch of an address transmitted as a signal DQ at an address register. The signal WE enables writing. The signal RE enables reading. The signal WP inhibits writing and erasure. The signal R/B indicates whether the non-volatile memory2is in the ready state (state in which a command from outside can be received) or the busy state (state in which a command from outside cannot be received). The memory controller1can know the state of the non-volatile memory2by receiving the signal R/B.

The power source inputting terminal group35includes a plurality of terminals through which power voltage Vcc, VccQ, and Vpp and ground voltage Vss are input to supply various kinds of operation power sources from outside to the non-volatile memory2. The power voltage Vcc is circuit power voltage provided typically from outside as an operation power source and is input as voltage of, for example, 3.3 V approximately. The power voltage VccQ is input as voltage of, for example, 1.2 V. The power voltage VccQ is used to transmit and receive signals between the memory controller1and the non-volatile memory2.

The power voltage Vpp is power voltage higher than the power voltage Vcc and is input as voltage of, for example, 12 V. High voltage of 20 V approximately is needed to write data to the memory cell array23or erase data. In this case, desired voltage can be generated faster with less electric power consumption by stepping up the power voltage Vpp of 12 V approximately than by stepping up the power voltage Vcc of 3.3 V approximately at a step-up circuit of the voltage supply circuit28. The power voltage Vcc is a power source normally supplied to the non-volatile memory2, and the power voltage Vpp is a power source additionally and optionally supplied in accordance with, for example, use environment.

The logic control circuit21and the input-output circuit22are connected to the memory controller1through a NAND bus. The input-output circuit22transmits and receives a signal DQ (for example, DQ0to DQ7) through the NAND bus to and from the memory controller1.

The logic control circuit21receives external control signals (for example, the chip enable signal/CE, the command latch enable signal CLE, the address latch enable signal ALE, the write enable signal/WE, the read enable signals RE and/RE, and the write protect signal/WP) from the memory controller1through the NAND bus. In addition, the logic control circuit21transmits the ready/busy signal/RB to the memory controller1through the NAND bus.

The input-output circuit22transmits and receives the signals DQ <7:0> and the data strobe signals DQS and/DQS to and from the memory controller1. The input-output circuit22forwards commands and addresses in the signals DQ <7:0> to the register26. The input-output circuit22also transmits and receives write data and read data to and from the sense amplifier24.

The register26includes a command register, an address register, and a status register. The command register temporarily stores a command. The address register temporarily stores an address. The status register temporarily stores data necessary for operation of the non-volatile memory2. The register26is configured as, for example, an SRAM.

The sequencer27as a control unit receives a command from the register26and controls the non-volatile memory2in accordance with a sequence based on the command.

The voltage supply circuit28receives power voltage from outside of the non-volatile memory2and generates a plurality of voltages necessary for write operation, read operation, and erasure operation by using the power voltage. The voltage supply circuit28supplies the generated voltages to the memory cell array23, the sense amplifier24, the row decoder25, and the like.

The row decoder25receives a row address from the register26and decodes the row address. The row decoder25performs selection operation of a word line based on the decoded row address. Then, the row decoder25forwards a plurality of voltages necessary for write operation, read operation, and erasure operation to a selected block.

The sense amplifier24receives a column address from the register26and decodes the column address. The sense amplifier24includes a sense amplifier unit group24A and a data register24B. The sense amplifier unit group24A is connected to the bit lines and selects either bit line based on a decoded column address. At data reading, the sense amplifier unit group24A senses and amplifies data read from a memory cell transistor onto a bit line. At data writing, the sense amplifier unit group24A forwards write data to a bit line.

At data reading, the data register24B temporarily stores data detected by the sense amplifier unit group24A and serially forwards the data to the input-output circuit22. At data writing, the data register24B temporarily stores data serially forwarded from the input-output circuit22and forwards the data to the sense amplifier unit group24A. The data register24B is configured as, for example, an SRAM.

(1-3. Block Configuration of Memory Cell Array)

FIG.3is a diagram illustrating an exemplary configuration of a block of the memory cell array23having a three-dimensional structure.FIG.3illustrates one block BLK among the plurality of blocks included in the memory cell array23. Any other block of the memory cell array has a configuration same as the configuration inFIG.3. Note that the present embodiment is also applicable to a memory cell array having a two-dimensional structure.

As illustrated, the block BLK includes, for example, four string units (SU0to SU3). Each string unit SU includes a plurality of NAND strings NS. In this example, each NAND string NS includes eight memory cell transistors MT (MT0to MT7) and select gate transistors ST1and ST2. Each memory cell transistor MT includes a gate and an electric charge accumulation layer and stores data in a non-volatile manner. Note that, for sake of simplicity, the number of memory cell transistors MT included in each NAND string NS is eight but may be larger.

The select gate transistors ST1and ST2are each indicated as one transistor in terms of electric circuit but may be each integrated with a memory cell transistor in terms of structure. For example, to improve a cutoff characteristic, the select gate transistors ST1and ST2may each include a plurality of select gate transistors. In addition, a dummy cell transistor may be provided between a memory cell transistor MT and each of the select gate transistors ST1and ST2.

The memory cell transistors MT are connected in series to each other and disposed between the select gate transistors ST1and ST2. The memory cell transistor MT7on one end side is connected to the select gate transistor ST1, and the memory cell transistor MT0on the other end side is connected to the select gate transistor ST2.

Gates of the select gate transistors ST1of the respective string units SU0to SU3are connected to select gate lines SGD0to SGD3(hereinafter referred to as select gate lines SGD when not needed to be distinguished from one another), respectively. Gates of the select gate transistors ST2are connected to a select gate line SGS that is common to the plurality of string units SU in the same block BLK. Gates of the memory cell transistors MT0to MT7in the same block BLK are connected to word lines WL0to WL7, respectively. In other words, the word lines WL0to WL7and the select gate line SGS are connected in common to the plurality of string units SU0to SU3in the same block BLK, but the select gate lines SGD are independently connected to the string units SU0to SU3, respectively, in the same block BLK.

The gates of the memory cell transistors MT0to MT7included in each NAND string NS are connected to the word lines WL0to WL7, respectively. The gates of memory cell transistors MTi on the same row in the block BLK are connected to the same word line WLi. Note that, in the following description, each NAND string NS is simply referred to as “string” in some cases.

Each NAND string NS is connected to a corresponding bit line. Thus, each memory cell transistor MT is connected to a bit line through the select gate transistors ST and the other memory cell transistors MT included in a corresponding NAND string NS. As described above, data at the memory cell transistors MT in the same block BLK is erased all at once. However, data reading and writing are performed per memory cell group MG (or per page). In the present specification, a memory cell group MG is defined to be a plurality of memory cell transistors MT connected to one word line WLi and belonging to one string unit SU. In read operation and write operation, one word line WLi and one select gate line SGD are selected in accordance with a physical address, and accordingly, a memory cell group MG is selected.

(1-4. Sectional Structure of Non-Volatile Memory)

FIG.4is a cross-sectional view of a partial region of the semiconductor storage device according to the embodiment.FIG.4illustrates an example in which a peripheral circuit region corresponding to peripheral circuits such as the sense amplifier24and the row decoder25is provided on a semiconductor substrate71and a memory region is provided above the peripheral circuit region. Note that, in the following description, an x direction and a y direction are defined to be two directions horizontal to a surface of the semiconductor substrate71and orthogonal to each other, and a z direction is defined to be a direction perpendicular to the surface of the semiconductor substrate71.

As illustrated inFIG.4, the non-volatile memory includes the semiconductor substrate71, electric conductors641to657, a memory pillar634, and contact plugs C0, C1, C2, and CP in a memory region MR. Note that the drawing to be described below omits illustrations of p-type or n-type well regions formed at an upper surface part of the semiconductor substrate71, an impurity diffusion region formed in each well region, and gate insulating films and element separation regions each insulating the well regions from each other.

In the memory region MR, an electric conductor GC is provided on the semiconductor substrate71through a gate insulating film (not illustrated). In addition, for example, a plurality of contacts C0are provided in a plurality of impurity diffusion regions (not illustrated), respectively, provided on the semiconductor substrate71to sandwich the electric conductor GC. The memory cell array23is disposed on the semiconductor substrate71through a wiring layer region WR.

The electric conductor641, which forms a wiring pattern, is provided on each contact C0. For example, the electric conductor GC functions as a gate electrode of a transistor, and the electric conductor641functions as a source electrode or drain electrode of the transistor.

For example, the contact C1is provided on each electric conductor641. For example, the electric conductor642is provided on the contact C1. For example, the contact C2is provided on the electric conductor642. For example, the electric conductor643is provided on the contact C2.

Wiring patterns of the electric conductors641,642, and643are disposed in the wiring layer region WR between a sense amplifier circuit and the memory cell array, both not illustrated. Hereinafter, wiring layers in which the electric conductors641,642, and643are provided are referred to as wiring layers D0, D1, and D2, respectively. The wiring layers D0, D1, and D2are provided at a lower layer part of the non-volatile memory2. Note that, in this example, three wiring layers are provided in the wiring layer region WR, but two wiring layers or less, or four wiring layers or more may be provided in the wiring layer region WR.

The electric conductor644is provided above the electric conductor643through, for example, an interlayer insulating film. The electric conductor644is formed in, for example, a plate shape parallel to an xy plane and functions as a source line SL. For example, the electric conductors645to654corresponding to each NAND string NS are sequentially stacked above the electric conductor644. A non-illustrated interlayer insulating film is provided between each pair of adjacent electric conductors in the z direction among these electric conductors.

The electric conductors645to654are each formed in, for example, a plate shape parallel to the xy plane. For example, the electric conductor645functions as the select gate line SGS, the electric conductors646to653function as the word lines WL0to WL7, respectively, and the electric conductor654functions as the select gate line SGD.

Each memory pillar634has a column shape, penetrates through each of the electric conductors645to654, and contacts the electric conductor644. The memory pillar634includes, for example, an electric conductor column638on a center side, a tunnel insulating film637formed on an outer side of the electric conductor column638, an electric charge accumulation film636formed on the outer side of the tunnel insulating film637, and a block insulating film635formed on the outer side of the electric charge accumulation film636.

For example, a part at which the memory pillar634intersects the electric conductor645functions as the select gate transistor ST2. A part at which the memory pillar634intersects each of the electric conductors646to653functions as a memory cell transistor (memory cell) MT. A part at which the memory pillar634intersects the electric conductor654functions as the select gate transistor ST1.

The electric conductor655is provided in a layer above an upper surface of the memory pillar634through an interlayer insulating film. The electric conductor655is formed in a line shape extending in the x direction and corresponds to a bit line BL. A plurality of electric conductors655are arrayed at intervals in the y direction (not illustrated). The electric conductor655is electrically connected, for each string unit SU, to the electric conductor column638in the corresponding one memory pillar634.

Specifically, in each string unit SU, for example, the contact plug CP is provided on the electric conductor column638in each memory pillar634, and one electric conductor645is provided on the contact plug CP. Note that the present embodiment is not limited to such a configuration, but the electric conductor column638and the electric conductor655in the memory pillar634may be connected to each other through a plurality of contacts and wires or the like.

The electric conductor656is provided, through an interlayer insulating film, in a layer above the layer in which the electric conductor655is provided. The electric conductor657is provided, through an interlayer insulating film, in a layer above the layer in which the electric conductor656is provided.

The electric conductors656and657correspond to, for example, a wire provided in the memory cell array and a wire for connecting the peripheral circuits provided below the memory cell array. The electric conductors656and657may be connected to each other through a non-illustrated column-shaped contact. In this example, the layer in which the electric conductor655is provided is referred to as a wiring layer M0, the layer in which the electric conductor656is provided is referred to as a wiring layer M1, and the layer in which the electric conductor657is provided is referred to as a wiring layer M2.

As illustrated inFIG.4, in the semiconductor storage device of the embodiment, the wiring layers D0, D1, and D2are formed below each string unit SU. The wiring layers M0, M1, and M2are formed above each string unit SU. The wiring layers D0, D1, and D2are tungsten wires formed by, for example, a damascene method.

The wiring layer M2is, for example, an aluminum wire formed by anisotropic etching such as reactive ion etching (RIE). The wiring layer M2has a large film thickness and a low resistance, and thus key power source wires (Vcc, Vss) are allocated to the wiring layer M2. The wiring layer M1is, for example, a copper (Cu) wire formed by the damascene method. The Cu wire has high wiring reliability in, for example, electro migration (EM) resistance, and a signal line through which data needs to be reliably transferred is allocated to the wiring layer M1. The wiring layer M0is, for example, a Cu wire formed by the damascene method. The wiring layer M0is used as the bit line BL, and part of the key power source wires is allocated to the wiring layer M0for power source reinforcement. Note that a wire such as a signal line other than the key power source wires preferably has a resistance as low as possible and thus is formed by using an upper wiring layer (for example, the wiring layer M2) when possible.

(1-5. Threshold Voltage Distributions of Memory Cell Transistor)

FIG.5is a diagram illustrating an example of threshold voltage distributions of the non-volatile memory.FIG.5illustrates a threshold voltage distribution example of the 3 bit/Cell non-volatile memory2. The non-volatile memory2stores information as an amount of electric charge stored in the electric charge accumulation layer of each memory cell. The memory cell has a threshold voltage in accordance with the amount of electric charge. A plurality of data values stored in the memory cell are associated with a plurality of respective regions (threshold voltage distribution regions) of the threshold voltage.

InFIG.5, eight distributions (lobes) denoted by Er, A, B, C, D, E, F, and G correspond to eight threshold voltage distribution regions. In this manner, each memory cell has threshold voltage distributions divided by seven boundaries. InFIG.5, a horizontal axis represents the threshold voltage, and a vertical axis represents distribution of the number of memory cells (the number of cells).

In the present embodiment, the region Er is defined to be a region in which the threshold voltage is equal to or lower than VrA, the region A is defined to be a region in which the threshold voltage is higher than VrA and equal to or lower than VrB, the region B is defined to be a region in which the threshold voltage is higher than VrB and equal to or lower than VrC, and the region C is defined to be a region in which the threshold voltage is higher than VrC and equal to or lower than VrD. In addition, in the present embodiment, the region D is defined to be a region in which the threshold voltage is higher than VrD and equal to or lower than VrE, the region E is defined to be a region in which the threshold voltage is higher than VrE and equal to or lower than VrF, the region F is defined to be a region in which the threshold voltage is higher than VrF and equal to or lower than VrG, and the region G is defined to be a region in which the threshold voltage is higher than VrG.

The threshold voltage distributions corresponding to the regions Er, A, B, C, D, E, F, and G are referred to as distributions Er, A, B, C, D, E, F, and G (first to eighth distribution), respectively. The voltages VrA to VrG are threshold voltages as the boundaries of the regions.

In the non-volatile memory2, a plurality of data values are associated with the plurality of respective threshold voltage distribution regions of each memory cell. This association is referred to as data coding. The data coding is determined in advance, and at data writing (programming), electric charge is injected into the memory cell based on the data coding so that the threshold voltage is in a threshold voltage distribution region in accordance with a data value to be stored. At reading, read voltage is applied to the memory cell, and data is determined based on whether the threshold voltage of the memory cell is lower or higher than the read voltage.

FIG.6is a diagram illustrating the data coding of the embodiment. In the present embodiment, the eight threshold voltage distribution regions illustrated inFIG.5are associated with eight three-bit data values, respectively. The threshold voltage and data values of bits corresponding to Upper, Middle, and Lower pages have a relation as described below.The memory cell stores “111” when the threshold voltage is in the region Er.The memory cell stores “101” when the threshold voltage is in the region A.The memory cell stores “001” when the threshold voltage is in the region B.the memory cell stores “011” when the threshold voltage is in the region C.The memory cell stores “010” when the threshold voltage is in the region D.The memory cell stores “110” when the threshold voltage is in the region E.The memory cell stores “100” when the threshold voltage is in the region F.The memory cell stores “000” when the threshold voltage is in the region G.

In this manner, the regions of the threshold voltage can indicate the states of three-bit data in each memory cell. Note that the threshold voltage of the memory cell is in the region Er in a state in which the memory cell is not written (state of “erased”). In the above-described code, only one bit of data changes between any two adjacent states, for example, as data “111” is stored in the state Er (erasure) and data “101” is stored in the state A. In this manner, the coding illustrated inFIG.6is gray code that only one bit of data changes between any two adjacent regions.

Note that the example in which the eight states are discretely distributed is described with reference toFIG.5, but this is, for example, an ideal state right after data writing. Thus, in reality, adjacent states potentially overlap each other. For example, after data writing, an upper end of the distribution Er and a lower end of the distribution A overlap each other due to disturbance or the like in some cases. In such a case, data is corrected by using, for example, an ECC technology.

(2. Operation)

Subsequently, data write operation and read operation in the present embodiment will be described below.

(2-1. Concept of Write Operation)

First, the write operation according to the present embodiment will be briefly described. The write operation roughly includes program operation and verify operation. When multiple-value data is to be written to a memory cell transistor MT, the threshold voltage of the memory cell transistor MT is set to be a value in accordance with a value of the data. When program voltage VPGM and bit line voltage Vb1are applied to the memory cell transistor MT, electrons are injected into the electric charge accumulation film of the memory cell transistor MT and the threshold voltage increases. When the program voltage VPGM is increased to increase an amount of injected electrons, the threshold voltage of the memory cell transistor MT can be increased. However, an amount of injected electrons is different among memory cell transistors MT due to variance among the memory cell transistors MT even when the same program voltage VPGM is applied. Once injected, electrons are held until erasure operation is performed. Thus, the program operation and the verify operation (loop) are performed a plurality of times along with gradual increase of the program voltage VPGM so that the threshold voltage set to each memory cell transistor MT is in an allowable range of the threshold voltage.

The program operation is operation that increases the threshold voltage by injecting electrons into the electric charge accumulation layer (or maintains the threshold voltage by inhibiting the injection). Hereinafter, the operation that increases the threshold voltage is referred to as ““0” programming” or ““0” writing”, and data “0” is provided to a bit line BL as a “0” programming target. The operation that maintains the threshold voltage is referred to as “1” “programming”, “1” “writing”, or “writing inhibition”, and data “1” is provided to a bit line BL as a “1” programming target.

The verify operation is read operation performed as part of the write operation. The verify operation is operation that determines whether the threshold voltage of a memory cell transistor MT has reached a target level by reading data after the program operation. A memory cell transistor MT, the threshold voltage of which has reached the target level is then set to writing inhibition. Combination of the program operation and the verify operation described above is repeated to increase the threshold voltage of the memory cell transistor MT to the target level.

(2-2. Program Operation)

FIG.7Ais a diagram illustrating voltage change at each wire in the write operation (program operation). Note that each voltage illustrated inFIG.7Ais generated by the voltage supply circuit28under control of the sequencer27.

The program operation is performed in accordance with the program voltage and the bit line voltage applied to a word line and a bit line. For a writing target string unit SU (selected SU) of a writing target block BLK (selected BLK), a select gate line SGD (SGD_sel) is set to, for example, 5 V to conduct electricity through the select gate transistor ST1before application of the program voltage VPGM. In the program operation, the select gate line SGS is at, for example, 0 V. Thus, the select gate transistor ST2is off. Thereafter, the select gate line SGD (SGD_sel) is set to, for example, 2.5 V at application of the program voltage VPGM. Accordingly, a state of conduction through the select gate transistor ST1is determined by the bit line voltage of the bit line BL connected to the select gate transistor ST1.

For a non-writing target string unit SU (non-selected SU) of a writing target block BLK (selected BLK), a select gate line SGD (SGD_usel) is set to, for example, 5 V to conduct electricity through the select gate transistor ST1before application of the program voltage VPGM. Thereafter, the select gate line SGD (SGD_usel) is set to, for example, 0 V at application of the program voltage VPGM. Accordingly, the select gate transistor ST1conducts no electricity and is electrically disconnected from the bit line BL.

Note that, in a non-writing target block BLK (non-selected BLK), “0” is applied to each select gate line SGD and the select gate line SGS. Accordingly, each select gate transistor ST1and each select gate transistor ST2are turned off.

As described above, the sense amplifier24forwards data to each bit line BL. The ground voltage Vss of, for example, 0 V is applied as bit line voltage Vbl_L to a bit line BL provided with data “0”. Writing inhibition voltage Vinhibit (for example, 2.5 V) is applied as a bit line voltage Vbl_H to a bit line BL provided with data “1”. Thus, at application of the program voltage VPGM, each select gate transistor ST1connected to the bit line BL provided with data “0” conducts electricity, and each select gate transistor ST1connected to the bit line BL provided with data “1” is cut off. The memory cell transistor MT connected to each select gate transistor ST1being cut off is set to writing inhibition.

In the memory cell transistor MT connected to each select gate transistor ST1set to a conducting state, electrons are injected into the electric charge accumulation film in accordance with voltage applied to the corresponding word line WL. Each memory cell transistor MT connected to a word line WL provided with voltage VPASS as word line voltage becomes a conducting state irrespective of the threshold voltage, but no electrons are injected into the electric charge accumulation film. In each memory cell transistor MT connected to a word line WL provided with the program voltage VPGM as word line voltage, electrons are injected into the electric charge accumulation film in accordance with the program voltage VPGM.

Specifically, the row decoder25selects either word line WL in a selected BLK, applies the program voltage VPGM to the select word line, and applies the voltage VPASS to any other word line (non-select word line) WL. The program voltage VPGM is high voltage for injecting electrons into the electric charge accumulation film by a tunneling phenomenon, and VPGM>VPASS holds.FIG.8illustrates a status of a string unit SU in this case.

FIG.8is a circuit diagram illustrating a status of strings in the program operation.FIG.8illustrates two NAND strings corresponding to a “0” writing target bit line BL and a “1” writing target bit line BL. The illustrated diagram corresponds to a status when the word line WL3is selected.

As illustrated, the voltage VPGM is applied to the select word line WL3, and the voltage VPASS is applied to the non-select word lines WL0to WL2and WL4to WL7.

Accordingly, in the NAND string corresponding to the “0” writing target bit line BL, the select gate transistor ST1is turned on. Thus, channel voltage Vch of the memory cell transistor MT3connected to the select word line WL3becomes 0 V. In other words, voltage difference between a control gate and a channel increases, and as a result, electrons are injected into the electric charge accumulation layer and the threshold voltage of the memory cell transistor MT3is increased.

In the NAND string corresponding to the “1” writing target bit line BL, the select gate transistor ST1is cut off. Thus, the channel of the memory cell transistor MT3connected to the select word line WL3becomes electrically floating, and the channel voltage Vch is increased close to the voltage VPGM due to capacitive coupling with the word line WL and the like. In other words, the voltage difference between the control gate and the channel decreases, and as a result, no electrons are injected into the electric charge accumulation layer and the threshold voltage of the memory cell transistor MT3is maintained (the threshold voltage does not vary enough to cause transition of a threshold voltage distribution level to a higher distribution).

In this manner, the write operation (program operation) is performed on each memory cell transistor MT in the memory cell array23as voltage of the corresponding word line WL is controlled by the row decoder25and data is supplied to the corresponding bit line BL by the sense amplifier24.

(2-3. Read Operation (Verify Operation))

FIG.7Bis a diagram illustrating voltage change at each wire in the read operation (verify operation). Note that each voltage illustrated inFIG.7Bis generated by the voltage supply circuit28under control of the sequencer27. The read operation, that is, data reading from a multivalued memory cell transistor is performed as the row decoder25applies read voltage Vr to a select word line WL (hereinafter also referred to as WL_sel) of a selected block and the sense amplifier24senses data read onto a bit line BL and determines whether the read data is “0” or

The read operation has a disturbance prevention duration (time point t1to time point t2; hereinafter referred to as an USTRDIS duration) and an actual reading duration (time point t2to time point t3; hereinafter referred to as an actual reading duration). In the USTRDIS duration, all-channel conduction is performed at start of actual read operation to prevent disturbance (unintended increase of the threshold voltage). Specifically, when a cell belonging to the select word line WL_sel is not turned on in a non-selected string unit of the selected block, voltage on a drain side is boosted and voltage on a source side becomes equal to VCELSRC, and accordingly, a large voltage difference occurs. In this case, such a phenomenon occurs that hot carrier injection (HCI) occurs and a threshold value of a nearby cell changes. As a countermeasure for this, the select gate line SGD_usel on the drain side in the non-selected string unit is turned on to remove the boosted voltage, thereby preventing voltage difference between the drain side and the source side. Accordingly, unintended increase of the threshold voltage is prevented.

The row decoder25applies voltage VSG (for example, 5 V) for turning on the select gate transistors ST1and ST2to the select gate line SGD_sel, SGD_usel, and SGS of the selected block. The row decoder25also applies sufficiently high voltage VREAD (for example, 8 V) necessary for turning on each memory cell transistor to the select word line WL_sel of the selected block and the other non-select word lines WL_usel of the selected block. Note that voltage VREADK slightly higher than the voltage VREAD may be applied to a word line (adjacent word line) adjacent to the select word line WL_sel to facilitate conduction of each memory cell transistor connected to the adjacent word line.

In the actual reading duration, the select gate lines SGD_sel and SGS of a selected string unit of the selected block are maintained at the voltage VSG (for example, 5 V). The select gate line SGD_usel of a non-selected string unit of the selected block decreases to the voltage Vss (for example, 0 V) for turning off the select gate transistor ST1. In the actual reading duration, the row decoder25applies the read voltage Vr to the select word line WL_sel of the selected block and applies the voltage VREAD or VREADK to the other non-select word lines WL_usel of the selected block. In the read operation, the sense amplifier24fixes a bit line BL to constant voltage (for example, 1 V) and charges a non-illustrated sense node SEN inside the sense amplifier unit group24A to predetermined precharge voltage Vpre higher than the voltage of the bit line BL. In this state, the logic control circuit21connects the sense node SEN to the bit line BL. Accordingly, current flows from the sense node SEN to the bit line BL, and the voltage of the sense node SEN gradually decreases.

The voltage of the sense node SEN changes in accordance with a state of the threshold voltage of each memory cell transistor connected to the corresponding bit line BL. Specifically, when the threshold voltage of the memory cell transistor is lower than the read voltage, the memory cell transistor is on, large cell current flows through the memory cell transistor, and the voltage of the sense node SEN decreases at higher speed. When the threshold voltage of the memory cell transistor is higher than the read voltage, the memory cell transistor is off, small or no cell current flows through the memory cell transistor, and the voltage of the sense node SEN decreases at slower speed.

Such difference in the decrease speed of the voltage of the sense node SEN is used to determine a writing state of the memory cell transistor, and a result of the determination is stored in a data latch circuit. For example, whether the voltage of the sense node SEN is at a low level (hereinafter also referred to as “L”) or a high level (hereinafter also referred to as “H”) is determined at a first time point when a predetermined first duration has elapsed since discharging start at which electric charge at the sense node SEN starts discharging. For example, when the threshold voltage of the memory cell transistor is lower than the read voltage, the memory cell transistor is completely on and large cell current flows through the memory cell transistor. Accordingly, the voltage of the sense node SEN rapidly decreases, a voltage decrease amount is relatively large, and the sense node SEN becomes “L” at the first time point.

When the threshold voltage of the memory cell transistor is higher than the read voltage, the memory cell transistor is off and extremely small or no cell current flows through the memory cell transistor. Accordingly, the voltage of the sense node SEN extremely gradually decreases, the voltage decrease amount is relatively small, and the sense node SEN remains at “H” at the first time point.

In this manner, whether the threshold voltage of a memory cell transistor is higher or lower than the read voltage Vr is determined as the row decoder25applies the read voltage to the select word line WL_sel of a selected block and the sense amplifier circuit monitors a state of the sense node SEN. Thus, when voltage between states is applied as the read voltage to the select word line WL_sel, a state of each memory cell transistor can be determined and data allocated to the state can be read.

For example, 3 bits of data per memory cell transistor can be stored in a TLC by allocating data to each of the threshold voltage distributions of eight lobes of the TLC. Writing is performed at each memory cell transistor in any of states Er, A, B, . . . , and G corresponding to the eight threshold voltage distributions, respectively. At reading, the value of data in each memory cell transistor can be determined by applying the voltages VrA to VrG. Note that, in the following description, the read voltage applied to the select word line WL_sel in the verify operation is referred to as voltages VfyA to VfyG.

Note that, in an entire duration (t1to t3) of the read operation, the row decoder25applies the voltage Vss (for example, 0 V) to the word lines WL and the select gate lines SGD and SGS of each non-selected block.

(2-4. Specific Example of Write Operation)

A standard writing sequence will be more specifically described below with reference toFIG.9.FIG.9illustrates an example in which data is written as combination of the program operation and the verify operation is repeated 19 times. This repetition operation is referred to as “loop”.

FIG.9lists target states of the verify operation performed in each loop. As illustrated, the verify operation is performed only for the state “A” in the first and second loops. Specifically, in the verify operation, the voltage VfyA is applied to the select word line WL_sel, but the voltages VfyB to VfyG are not applied. In the subsequent third and fourth loops, the verify operation is performed for the state “A” and the state “B”. Specifically, in the verify operation, the voltages VfyA and VfyB are sequentially applied to the select word line WL_sel, but the voltages VfyC to VfyG are not applied.

In the fifth and sixth loops, the verify operation is performed for the state “A”, the state “B”, and the state “C”. Specifically, in the verify operation, the voltages VfyA, VfyB, and VfyC are sequentially applied to the select word line WL_sel, but the voltages VfyD to VfyG are not applied. The verify operation for the state “A” is completed on the sixth loop. This is because it is empirically known that, for example, programming to the state “A” is substantially completed in six loops.

In the seventh and eighth loops, the verify operation is performed for the state “B”, the state “C”, and the state “D”. Specifically, in the verify operation, the voltages VfyB, VfyC, and VfyD are sequentially applied to the select word line WL_sel. The verify operation for the state “B” is completed on the eighth write operation. Further, in the ninth and tenth loops, the verify operation is performed for the state “C”, the state “D”, and the state “E”. Specifically, in the verify operation, the voltages VfyC, VfyD, and VfyE are sequentially applied to the select word line WL_sel. The verify operation for the state “C” is completed on the tenth loop. Subsequently, writing is similarly performed up to the state “G”, and the loop is repeated 19 times at maximum.

FIG.10is a diagram illustrating timings of the program operation and the verify operation in the write operation based on the above-described standard writing sequence. As illustrated inFIG.10, in the first and second loops, the verify operation is performed only for the state “A”. Specifically, the verify operation is performed once for each program operation. In the third and fourth loops, the verify operation is performed for the state “A” and the state “B”. Specifically, the verify operation is performed twice for each program operation. In the fifth loop to the twelfth loop in which the verify operation for the state “D” is completed, the verify operation is performed three times for each program operation. Subsequently, the verify operation for a set predetermined state is performed for each program operation. Eventually in the 19 loops, the program operation is performed 19 times and the verify operation is performed 42 times.

Note that the above description assumes that the verify operation is performed up to an upper limit number of times. As illustrated inFIG.9, the verify operation for the state “A” is performed six times at maximum through the first to sixth loops. The verify operation for the state “B” is performed six times at maximum through the third to eighth loops. This is same for the other states. For example, there are a plurality of memory cell transistors MT written at the state “A”, and there are also a plurality of bit lines BL (“A”) connected to the memory cell transistors MT. Thus, in a precise sense, for example, when all memory cell transistors MT written at the state “A” have passed the verify operation for the state “A” in the fifth loop, the verify operation may not be performed for each bit line BL (“A”) in the sixth loop. This is also true for description below.

The voltage VPGM applied to the select word line WL_sel through the program operation for the first time, an increased amount of the voltage VPGM in the program operation for the second time or later, and a loop at which the verify operation for each state starts are set based on an assumption of a worst case of fast writing, and sufficient margins are allocated to prevent writing beyond a target level.

The number of loops in the write operation, the voltage (voltage VPGM) of the select word line WL_sel in each loop, and a verify operation target state in each loop, which are described above, are stored as the standard writing sequence in the sequencer27. When the write operation is to be performed on the memory cell array23based on the standard writing sequence, the sequencer27outputs a control signal based on the standard writing sequence to the sense amplifier24and the row decoder25.

(2-5. Voltage Control of Each Wire in Read Operation)

Subsequently, generation and control of voltage applied to each wire in the read operation will be described below with reference toFIG.11.FIG.11is a block diagram illustrating an example of configurations of the voltage supply circuit28and the row decoder25. Note thatFIG.11illustrates only a configuration of part of the voltage supply circuit28.

InFIG.11, the voltage supply circuit28is controlled by the sequencer27and generates various voltages including voltage necessary for, for example, the program operation and the read operation on memory cell transistors MT. The voltage supply circuit28includes a voltage generation circuit281and a voltage adjustment circuit282. The voltage generation circuit281generates internal voltage necessary for operation of the non-volatile memory2. The voltage generation circuit281includes a BDH power voltage generation circuit281A and a BDL power voltage generation circuit281B. The BDH power voltage generation circuit281A generates high-level power voltage (VRD) used at a block decoder25B of the row decoder25. The BDL power voltage generation circuit281B generates low-level power voltage (VBB) used at the block decoder25B. Note that the power voltage VBB is negative voltage.

The voltage adjustment circuit282generates various voltages necessary for operation of components of the non-volatile memory2by using voltage input through the power source inputting terminal group35and voltage generated by the voltage generation circuit281. Then, the voltage adjustment circuit282selects appropriate voltage from among the generated voltages and supplies the voltage to signal lines SG0to SG4and signal lines CG0to CG7. The voltage adjustment circuit282includes an SG driver282A configured to supply voltage to the signal lines SG0to SG4, and a plurality of CG drivers282B configured to supply voltage to the signal lines CG0to CG7, respectively. The signal lines SG0to SG4and CG0to CG7are branched through the row decoder25and connected to wires of each block BLK. Specifically, the signal lines SG0to SG3function as global drain side select gate lines and are connected to the select gate lines SGD0to SGD3as local select gate lines in each block BLK through the row decoder25. The signal lines CG0to CG7function as global word lines and are connected to the word lines WL0to WL7as local word lines in each block BLK through the row decoder25. The signal line SG4functions as a global source side select gate line and is connected to the select gate line SGS as a local select gate line in each block BLK through the row decoder25.

The row decoder25includes a plurality of switch circuit groups25A corresponding to respective blocks, and a plurality of block decoders25B corresponding to the plurality of switch circuit groups25A, respectively. Each switch circuit group25A includes a plurality of transistors TR_SG0to TR_SG4connecting the signal lines SG0to SG4and the select gate lines SGD0to SGD4, respectively, and a plurality of transistors TR_CG0to TR_CG7connecting the signal lines CG0to CG7and the word lines WL0to WL7, respectively. The transistors TR_SG0to TR_SG4and the transistors TR_CG0to TR_CG7are high breakdown voltage transistors.

When designated by a row address, each block decoder25B supplies a high-level block selection signal BLKSEL to gates of the transistors TR_SG0to TR_SG4and the transistors TR_CG0to TR_CG7. Accordingly, in a switch circuit group25A to which the high-level block selection signal BLKSEL is supplied from the block decoder25B designated by the row address, the transistors TR_SG0to TR_SG4and the transistors TR_CG0to TR_CG7are turned on and conduct electricity. As a result, voltage supplied from the voltage supply circuit28to the signal lines SG0to SG4and the signal lines CG0to CG7is supplied to the select gate lines SGD0to SGD3and SGS and the word lines WL0to WL7included in a block BLK as an operation target.

When not designated by a row address, each block decoder25B supplies a low-level block selection signal BLKSEL to the gates of the transistors TR_SG0to TR_SG4and the transistors TR_CG0to TR_CG7. Accordingly, in a switch circuit group25A to which the low-level block selection signal BLKSEL is supplied from a block decoder25B designated by the row address, the transistors TR_SG0to TR_SG4and the transistors TR_CG0to TR_CG7are turned off and conduct no electricity. As a result, voltage supplied from the voltage supply circuit28to the signal lines SG0to SG4and the signal lines CG0to CG7is not supplied to the select gate lines SGD0to SGD3and SGS and the word lines WL0to WL7included in a block BLK as a non-operation target.

In other words, the voltage supply circuit28and the row decoder25supply the voltage VREAD, the voltage Vr, and the like to a select word line WL_sel of a selected block and supply the voltage \TREAD, VREADK, or the like to a non-select word lines WL_usel. For example, the voltage VSG is supplied to a select gate line SGD_sel connected to a select gate transistor ST1belonging to a string unit SU as an operation target, and the voltage Vss such as 0 V is supplied to a select gate line SGD_usel connected to a select gate transistor ST1not belonging to the string unit SU as an operation target. The voltage Vss such as 0 V is supplied to the word lines WL and the select gate lines SGD and SGS of a non-selected block.

FIG.12is a block diagram illustrating an example of a configuration of a block decoder in a comparative example. The block decoders25B includes, for example, a logical circuit LC, a logical multiplication circuit AND, an inverter NV1, and a level conversion circuit30.

The logical circuit LC outputs an output signal based on a block address signal BLKADD input from the register26. All output signals from the logical circuit LC are at “H” level (high level) in a block decoder25B that the block address signal BLKADD hits, and either output signal from the logical circuit LC is at “L” level (low level) in a block decoder25B that the block address signal BLKADD does not hit. The logical multiplication circuit AND outputs, as a signal RDECAD to the inverter NV1and the level conversion circuit30, a logical multiplication result of the output signals from the logical circuit LC. Specifically, the signal RDECAD at “H” level is output from a block decoder25B that the block address signal BLKADD hits and for which a corresponding block BLK is determined to be normal. The signal RDECAD at “L” level is output from a block decoder25B that the block address signal BLKADD does not hit or for which a corresponding block BLK is determined to be anomalous. Note that voltage of the signal RDECAD at “H” level is the power voltage VRD output from the BDH power voltage generation circuit281A, and voltage of the signal RDECAD at “L” level is the ground voltage Vss (0 V). For example, VRD is 2.5 V. The inverter NV1inverts the signal RDECAD output from the logical multiplication circuit AND. The inverter NV1outputs a signal RDECADn as a result of the inversion.

The level conversion circuit30converts the signal RDECAD in accordance with the power voltage VRD into a signal BLKSEL in accordance with high power voltage (VGBST). Specifically, when the signal RDECAD at “H” level and the signal RDECADn at “L” level in accordance with the power voltage VRD are input, the level conversion circuit30converts the signals into the signal BLKSEL at “H” level in accordance with the power voltage VGBST and outputs the signal BLKSEL. When the signal RDECAD at “L” level and the signal RDECADn at “H” level are input, the level conversion circuit30outputs the signal RDECAD at “L” level as the signal BLKSEL at “L” level. Note that the power voltage VGBST is set to be voltage that turns on all transistors TR_SG0to TR_SG4and transistors TR_CG0to TR_CG7in the switch circuit group25A corresponding to a selected block. In the read operation, the power voltage VGBST is set to be voltage (for example, 15 V) higher than the voltage VREAD.

FIG.13is a block diagram illustrating an example of a configuration of the level conversion circuit. The level conversion circuit30includes a depletion-type NMOS transistor NM1and a high breakdown voltage PMOS transistor PM1. The power voltage VGBST is input to one end of the NMOS transistor NM1. The other end of the NMOS transistor NM1is connected to one end of the PMOS transistor PM1. The signal RDECAD is input to the other end of the PMOS transistor PM1. The signal RDECAD is also input to a gate of the NMOS transistor NM1. The signal RDECADn is input to a gate of the PMOS transistor PM1. The signal BLKSEL is output from the other end of the PMOS transistor PM1. A backflow prevention circuit301is provided between an input terminal for the signal RDECAD and a connection point n1among the other end of the PMOS transistor PM1, the input terminal for the signal RDECAD, and an output terminal for the signal BLKSEL.

The NMOS transistor NM1and the PMOS transistor PM1are both turned on when the signal RDECAD is at “H” level, that is, the voltage VRD, and the signal RDECADn is at “L” level, that is, the voltage Vss. Accordingly, the power voltage VGBST input to the one end of the NMOS transistor NM1is output as the signal BLKSEL. Note that the power voltage VGBST is higher than the voltage Vss, but outflow toward the input terminal for the signal RDECAD is prevented since the backflow prevention circuit301is provided. Therefore, an output level of the signal BLKSEL remains at the power voltage VGBST.

Because the NMOS transistor NM1is of the depletion type, it is not completely turned off when the signal RDECAD is at “L” level, that is, the voltage Vss, and the signal RDECADn is at “H” level, that is, the voltage VRD. Accordingly, current I1flows through the NMOS transistor NM1, and voltage at a connection point n2between the NMOS transistor NM1and the PMOS transistor PM1is stepped up to, for example, 1.8 V approximately. The voltage VRD is applied to the gate of the PMOS transistor PM1. The voltage VRD is, for example, 2.5 V and thus, the voltage applied to the gate is higher than the voltage at the connection point n2. Therefore, the PMOS transistor PM1is turned off. Accordingly, the voltage Vss is output as the signal BLKSEL.

It has been increasingly requested to decrease operation voltage of the semiconductor storage device, and it has been desired to decrease applied voltage at reading. At the same time, to maintain reading accuracy, it has been requested not to reduce a width of each threshold voltage distribution region. Thus, there has been proposed a semiconductor storage device having threshold voltage distributions shifted to a negative voltage side with the width of each threshold voltage distribution region being maintained.FIG.14is a diagram illustrating an example of threshold voltage distributions of the embodiment. An upper part ofFIG.14illustrates threshold voltage distributions in the comparative example, and a lower part illustrates the threshold voltage distributions in the embodiment. In the comparative example, the lowest voltage VrA among threshold voltages Vr that determine boundaries of regions is higher than 0 V. On the other hand, in the threshold voltage distributions of the embodiment, the threshold voltages Vr decrease in accordance with a decrease amount of the voltage \TREAD. Accordingly, the lowest voltage VrA is lower than 0 V (for example, −2 V approximately). The read operation of the non-volatile memory having such threshold voltage distributions will be described below with reference toFIG.15.

FIG.15is a diagram illustrating voltage change at each wire in the read operation (verify operation) of the embodiment. Voltage change at each wire in the USTRDIS duration (time point t1to time point t2) is same as the voltage change in the comparative example illustrated inFIG.7B. In addition, for wires other than a select word line WL_sel of a selected block, voltage distribution of each wire in the actual reading duration (time point t2to time point t3) is same as the voltage change in the comparative example illustrated inFIG.7B. In the actual reading duration (time point t2to time point t3), the read voltage Vr applied to the select word line WL_sel of the selected block is negative voltage (for example, −2 V), which is different from the voltage change in the comparative example illustrated inFIG.7B.

For example, when the select word line WL_sel is the word line WL0, the voltage VrA applied from the voltage supply circuit28to the signal line CG0is negative voltage in the actual read operation. The low-level block selection signal BLKSEL (voltage VBB) supplied from TR_CG0to TR_CG7, that is, a block decoder25B needs to reliably turn off the transistor TR_CG0, to one end of which negative voltage (voltage VrA) is input. Therefore, the voltage VBB needs to be set to negative voltage lower than the voltage VrA. In the actual reading duration, the BDL power voltage generation circuit281B of the present embodiment generates, as the power voltage VBB, negative voltage (for example, −4 V) lower than the voltage VrA. The power voltage VBB generated by the BDL power voltage generation circuit281B is supplied to the voltage adjustment circuit282and can be also used to generate negative threshold voltage such as the voltage VrA.

FIG.16is a block diagram illustrating an example of a configuration of a block decoder in the embodiment. The block decoder25B includes, for example, the logical circuit LC, the logical multiplication circuit AND, the inverter NV1, the level conversion circuit30, and a negative voltage conversion circuit31.

The logical circuit LC outputs an output signal based on a block address signal BLKADD input from the register26. All output signals from the logical circuit LC are at “H” level (high level) in a block decoder25B that the block address signal BLKADD hits, and either output signal from the logical circuit LC is at “L” level (low level) in a block decoder25B that the block address signal BLKADD does not hit. The logical multiplication circuit AND outputs, as a signal SEL to the inverter NV1and the level conversion circuit30, a logical multiplication result of the output signals from the logical circuit LC. Specifically, the signal SEL at “H” level is output from a block decoder25B that the block address signal BLKADD hits and for which a corresponding block BLK is determined to be normal. The signal SEL at “L” level is output from a block decoder25B that the block address signal BLKADD does not hit or for which a corresponding block BLK is determined to be anomalous. Note that voltage of the signal RDECAD at “H” level is the power voltage VRD output from the BDH power voltage generation circuit281A, and voltage of the signal RDECAD at “L” level is the ground voltage Vss (=0 V). The inverter NV1inverts the signal SEL output from the logical multiplication circuit AND. The inverter NV1outputs a signal SELn as a result of the inversion.

The negative voltage conversion circuit31converts the input signal SEL or the ground voltage Vss input as the signal SELn into the power voltage VBB that is negative voltage.FIG.17is a circuit diagram illustrating an example of a configuration of the negative voltage conversion circuit31in the embodiment. The negative voltage conversion circuit31includes two PMOS transistors PM11and PM12and four NMOS transistors NM11, NM12, NM13, and NM14. The PMOS transistor PM11and the NMOS transistors NM11and NM13are connected in series between an input terminal for the signal SELn and an input terminal for the power voltage VBB. The PMOS transistor PM12and the NMOS transistors NM12and NM14are connected in series between an input terminal for the signal SEL and the input terminal for the power voltage VBB.

The ground voltage Vss is input to gates of the PMOS transistors PM11and PM12. The signal SEL is input to a gate of the NMOS transistor NM11. The signal SELn is input to a gate of the NMOS transistor NM12. Voltage at a connection point between the PMOS transistor PM12and the NMOS transistor NM12is input to a gate of the NMOS transistor NM13. Voltage at a connection point between the PMOS transistor PM11and the NMOS transistor NM11is input to a gate of the NMOS transistor NM14. The power voltage VRD as well voltage is supplied to the PMOS transistors PM11and PM12. The NMOS transistors NM11to NM14have a triple-well structure.

FIG.18is a cross-sectional view for description of an NMOS transistor structure in the negative voltage conversion circuit.FIG.18illustrates a structure of the NMOS transistor NM13, but the other NMOS transistors NM11, NM12, and NM14have the same structure. In the NMOS transistor NM13, an N well711formed through injection and diffusion of n-type impurities (for example, arsenic (As)) is provided in a predetermined region of the p-type semiconductor substrate71. A P well712formed through injection and diffusion of p-type impurities (for example, boron (B)) is provided in the N well711. A source region713and a drain region714formed through injection and diffusion of n-type impurities (for example, phosphorus (P)) are provided in the P well712. A gate electrode715made of a conductive material is provided on the semiconductor substrate between the source region713and the drain region714through a gate insulating film. In other words, the NMOS transistor NM13is formed of the source region713, the drain region714, and the gate electrode715. The negative power voltage VBB is supplied to the source region713and the P well712. Voltage VDNW BD (>0 V) is supplied to the N well711. In a case of an NMOS transistor having a structure in which the N well711is not provided, when negative voltage is applied to the n-type source region713, forward bias is formed between the n-type source region713and the p-type semiconductor substrate71, which is fixed at the ground voltage Vss (0 V), and large leakage current flows from the NMOS transistor NM13to the semiconductor substrate71. In the present embodiment, since the NMOS transistor NM13has such a triple-well structure, a leakage path can be cut off by the N well711, which is formed between the P well712and the semiconductor substrate71, when negative voltage is applied to the source region713.

The voltage at the connection point between the PMOS transistor PM12and the NMOS transistor NM12is output as the signal RDECAD. The voltage at the connection point between the PMOS transistor PM11and the NMOS transistor NM11is output as the signal RDECADn.

When the signal SEL is at “H” level, the power voltage VRD is input to one end of the PMOS transistor PM12. Since the signal SELn is at “L” level, the ground voltage Vss is input to one end of the PMOS transistor PM11. In this case, the PMOS transistor PM12is turned on and the PMOS transistor PM11is turned off. The NMOS transistors NM11and NM13are turned on since the voltage VRD is applied to the gates of NMOS transistors NM11and NM13. The NMOS transistor NM12is turned off since the voltage Vss is applied to the gate of the NMOS transistor NM12. The NMOS transistor NM14is turned off since the voltage VBB is applied to the gate of the NMOS transistor NM14. In this manner, the transistors PM11, NM12, and NM14are switched off, and the transistors PM12, NM11, and NM13are switched on, and accordingly, the voltage VRD is output as the signal RDECAD, and the voltage VBB is output as the signal RDECADn.

When the signal SEL is at “L” level, the power voltage Vss is input to the one end of the PMOS transistor PM12. Since the signal SELn is at “H” level, the power voltage VRD is input to the one end of the PMOS transistor PM11. In this case, the PMOS transistor PM11is turned on and the PMOS transistor PM12is turned off. The NMOS transistors NM12and NM14are turned on since the voltage VRD is applied to the gates of the NMOS transistors NM12and NM14. The NMOS transistor NM11is turned off since the voltage Vss is applied to the gate of the NMOS transistor NM11. The NMOS transistor NM13is turned off since the voltage VBB is applied to the gate of the NMOS transistor NM13. In this manner, the transistors PM11, NM12, and NM14are switched on, and the transistors PM12, NM11, and NM13are switched on, and accordingly, the voltage VBB is output as the signal RDECAD, and the voltage VRD is output as the signal RDECADn. The signals RDECAD and RDECADn output from the negative voltage conversion circuit31are input to the level conversion circuit30.

In the level conversion circuit30, the NMOS transistor NM1and the PMOS transistor PM1are both turned on when the signal RDECAD is at “H” level, that is, the voltage VRD, and the signal RDECADn is at “L” level, that is, the voltage VBB. Thus, the power voltage VGBST input to the one end of the NMOS transistor NM1is output as the signal BLKSEL.

Because the NMOS transistor NM1is of the depletion type, it is not completely turned off when the signal RDECAD is at “L” level, that is, the voltage VBB, and the signal RDECADn is at “H” level, that is, the voltage VRD. Accordingly, the current I1flows through the NMOS transistor NM1, and the voltage at the connection point n2between the NMOS transistor NM1and the PMOS transistor PM1is stepped up to, for example, 2 V approximately. The voltage VRD is applied to the gate of the PMOS transistor PM1. The voltage VRD is, for example, 2.5 V, and thus the voltage applied to the gate is higher than the voltage at the connection point n2. Therefore, the PMOS transistor PM1is turned off. Thus, the voltage VBB is output as the signal BLKSEL.

In the comparative example, “H” voltage level of the signals RDECAD and RDECADn generated at the block decoder25B is the power voltage VRD and is a fixed value (for example, 2.5 V) during the read operation. An “L” voltage level of the signals RDECAD and RDECADn is the ground voltage Vss and is a fixed value (for example, 0 V) during the read operation. On the other hand, in the embodiment, the “H” voltage level of the signals RDECAD and RDECADn generated at the block decoder25B is the power voltage VRD, and a value of the power voltage VRD changes during the read operation. The “L” voltage level of the signals RDECAD and RDECADn is the power voltage VBB, and a value of the power voltage VBB changes during the read operation.

FIG.19is a diagram illustrating voltage change of the power voltage in the read operation (verify operation) of the embodiment. As illustrated inFIG.19, the power voltage VBB is at the ground voltage of 0 V (the ground voltage Vss, voltage Vhb) before read-operation start time t1. The power voltage VBB starts decreasing at read-operation start time t1and decreases to voltage Vlb, that is, voltage value (for example, −4 V) lower than the voltage VrA, which can reliably turn off a transistor TR_CG, to one end of which negative voltage (the voltage VrA) is input, in the USTRDIS duration. The power voltage VBB is maintained at the voltage Vlb in the actual reading duration. The power voltage VBB starts increasing at actual-reading-duration end time t3and continues increasing until the voltage Vhb is reached. Note that the power voltage VBB may start decreasing from the ground voltage of 0 V at slight delay from read-operation start time t1.

Before read-operation start time t1, the power voltage VRD is at voltage (voltage Vhr; for example, 2.5 V) same as in the comparative example. In the USTRDIS duration, the power voltage VBB starts decreasing after reaching predetermined threshold voltage Vo1(for example, −1 V). The power voltage VRD decreases to voltage Vlr (for example, 2 V) in the USTRDIS duration. The power voltage VRD is maintained at the voltage Vlr in the actual reading duration. After actual-reading-duration end time t3, the power voltage VRD starts increasing once the power voltage VBB reaches predetermined threshold voltage Vo2(for example, −3 V), and continues increasing until the voltage Vhr is reached.

Reasons for the change of the power voltage VRD and VBB are as follows. First, the reason for the change of the power voltage VBB will be described below. The power voltage VBB as negative voltage is generated through electrical discharging of the ground voltage Vss. Since a consumption amount of current increases in an electrical discharging duration, it is required to shorten a generation time of negative voltage as much as possible. Thus, the power voltage VBB is desirably maintained at the voltage Vlb from time point t2to time point t3in the actual reading duration and changed to the ground voltage Vss (voltage Vhb) in the other duration. Accordingly, the power voltage VBB starts decreasing from the voltage Vhb at read-operation start time t1, remains at the voltage Vlb between time points t2and t3, and starts increasing again at time point t3until the voltage Vhb is reached.

Subsequently, the reason for the change of the power voltage VRD will be described below. As illustrated inFIG.21, when the power voltage VRD is fixed at the voltage Vhr (for example, 2.5 V) through the entire duration of the read operation, difference between the power voltage VRD and the power voltage VBB is 6.5 V in the actual reading duration. When the NMOS transistors NM11and NM13between the PMOS transistor PM11and the input terminal for the power voltage VBB are turned on, source voltage and well voltage of the PMOS transistor PM11become equal to the power voltage VBB and the power voltage VRD, respectively. The PMOS transistor PM11of the negative voltage conversion circuit31is a low breakdown voltage transistor, and thus difference between the voltage Vhr and the voltage Vlb potentially exceeds junction breakdown voltage (for example, 6 V). Similarly, the PMOS transistor PM12is a low breakdown voltage transistor, and thus difference between source voltage and well voltage of the PMOS transistor PM12potentially exceeds junction breakdown voltage when the NMOS transistors NM12and NM14are turned on. To avoid this problem, the power voltage VRD is preferably decreased to the voltage Vlr (for example, 2 V) in the actual reading duration so that difference between source voltage and well voltage does not exceed junction breakdown voltage.

As illustrated inFIG.22, when the value of the power voltage VRD is fixed at the voltage Vlr (for example, 2 V) through the entire duration of the read operation, a voltage value applied to the gate of the PMOS transistor PM1in the level conversion circuit30is the voltage Vlr. Near time point t1, the signal RDECAD is at “L” level, that is, voltage Vlh (0 V), and because the NMOS transistor NM1is of the depletion type, it is not completely turned off when the signal RDECADn is at “H” level, that is, the voltage Vlr (for example, 2 V). Accordingly, the current I1flows through the NMOS transistor NM1, and the voltage at the connection point n2between the NMOS transistor NM1and the PMOS transistor PM1is stepped up to, for example, 1.8 V approximately. Since the voltage Vlr (for example, 2 V) is applied to the gate of the PMOS transistor PM1, the voltage applied to the gate is equivalent to the voltage at the connection point n2. In this case, the PMOS transistor PM1is not completely turned off, and leakage current12potentially increases. Thus, the voltage applied to the gate of the PMOS transistor PM1is preferably increased to prevent leakage current when the value of the power voltage VBB is high and the NMOS transistor NM1is not completely turned off. For the above-described two reasons, the power voltage VRD is changed in accordance with the value of the power voltage VBB in the embodiment.

The value of the power voltage VBB and the value of the power voltage VRD are controlled by the sequencer27. The sequencer27controls the value of the power voltage VBB in accordance with a sequence implemented in advance. The sequencer27monitors the value of the power voltage VBB and controls the value of the power voltage VRD based on the two threshold voltages Vo1and Vo2set in advance as triggers.

Note that the sequencer27may control the value of the power voltage VRD, as well, in accordance with a sequence implemented in advance.FIG.20is a diagram illustrating other voltage change of the power voltage in the read operation (verify operation) of the embodiment. In an example illustrated inFIG.19, the power voltage VBB is discharged through one step from the voltage Vhb to the voltage Vlb and charged through one step from the voltage Vlb to the voltage Vhb, but in an example illustrated inFIG.20, the power voltage VBB is discharged through two steps from the voltage Vhb to the voltage Vo1and then from the voltage Vo1to the voltage Vlb and charged through two steps from the voltage Vlb to the voltage Vo2and then from the voltage Vo2to the voltage Vhb. When a duration in which the power voltage VBB is maintained at the threshold voltage Vo1is provided between the two steps in discharging and a duration in which the power voltage VBB is maintained at the threshold voltage Vo2is provided between the two steps in charging, the sequencer27may implement a sequence in advance so that the power voltage VRD starts discharging in the duration (time point t11to time point t12) in which the power voltage VBB is maintained at the threshold voltage Vo1and the power voltage VRD starts charging in the duration (time point t31to time point t32) in which the power voltage VBB is maintained at the threshold voltage Vo2, thereby controlling a voltage value of the power voltage VRD without monitoring voltage of the power voltage VBB.

In the example illustrated inFIG.20, the power voltage VBB starts decreasing from the ground voltage of 0 V at read-operation start time t1, but may start decreasing from the ground voltage of 0 V at slight delay from read-operation start time t1.

In this manner, the semiconductor storage device of the embodiment controls the voltage values of the power voltage VRD and VBB supplied to each block decoder25B in the read operation, and thus can improve reliability of the block decoder25B and reliably turn off any switch circuit group25A corresponding to a non-selected block.

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel devices and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the devices and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.