Patent ID: 12211886

DETAILED DESCRIPTION

With reference toFIGS.1,2,2Aand in accordance with embodiments of the invention, a structure10includes a semiconductor substrate12and a dielectric layer14on the semiconductor substrate12. In an embodiment, the semiconductor substrate12may be comprised of a semiconductor material, such as single-crystal silicon, and the dielectric layer14may be comprised of a dielectric material, such as silicon dioxide. The dielectric layer14adjoins the semiconductor substrate12along a horizontal interface15. The semiconductor substrate12and the dielectric layer14may be included as a handle substrate and a buried oxide layer of a silicon-on-insulator substrate.

Pilot openings16,17may be formed that extend fully through the dielectric layer14and then penetrate past the horizontal interface15to a depth into the semiconductor substrate12. The pilot openings16,17may be formed by an anisotropic etching process. In an embodiment, the pilot openings16,17may be arranged in adjacent spaced-apart pairs.

Cavities18,20,22,24,26may be formed in the semiconductor substrate12as undercuts beneath the dielectric layer14. Specifically, the cavities18,20,22,24,26may be formed in the semiconductor substrate12by an isotropic etching process that relies on the pilot openings16,17for ingress and egress of an etchant to remove portions of the semiconductor substrate12. Each of the cavities18,20,22,24,26is associated with at least a pair of the pilot openings16,17and, in an embodiment, each of the cavities18,20,22,24,26is associated with multiple pairs of the pilot openings16,17. The isotropic etching process includes a vertical etching component and a lateral etching component that result in each of the cavities18,20,22,24,26being deepened and widened relative to the initial depth and width of the portion of the pilot openings16,17in the semiconductor substrate12. In an embodiment, the isotropic etching process may be a dry etching process. The cavities18,20,22,24,26may have different widths that progressively narrow in a prescribed manner, as subsequently discussed. In an embodiment, cavities18,20,22,24,26may have equal lengths. In an alternative embodiment, two or more of the cavities18,20,22,24,26may have unequal lengths.

In an embodiment, the cavity18may include adjacent chambers30,31having upper portions that that merge together during the isotropic etching process. The adjacent chambers30,31of the cavity18are respectively associated with the overlying pair of pilot openings16,17, the formation of the chamber30initiates at the pilot opening16in the overlying pair, and the formation of the chamber31initiates at the adjacent pilot opening17in the overlying pair. The merged upper portions of the chambers30,31result because of the lateral advance of the etch fronts in the semiconductor substrate12from the pair of pilot openings16,17. The cavity18and, more specifically, the upper portions of the chambers30,31of the cavity18may be coextensive with (i.e., share a boundary with) the horizontal interface15between the semiconductor substrate12and the dielectric layer14.

The cavity18has a maximum width W1, which may occur adjacent to the horizontal interface15between the semiconductor substrate12and the dielectric layer14. In an embodiment, the maximum width W1may coincide with the horizontal interface15between the semiconductor substrate12and the dielectric layer14. The width W1of the cavity18may narrow with increasing depth from the horizontal interface15. The cavity18has a maximum depth that may be measured relative to the horizontal interface15. The lower portions of the chambers30,31may be curved and may have a “W” shape with a cusped portion of the semiconductor substrate12separating the lower portions of the chambers30,31.

In an embodiment, the cavity20may include adjacent chambers32,33having upper portions that that merge during the isotropic etching process. The adjacent chambers32,33of the cavity20are respectively associated with the overlying pair of pilot openings16,17, and the formation of the chamber32initiating at the pilot opening16in the overlying pair and the formation of the chamber32initiates at the pilot opening17in the overlying pair. The merged upper portions of the chambers32,33result because of the lateral advance of the etch fronts from the pair of pilot openings16,17. The cavity20and, more specifically, the upper portions of the chambers32,33may be coextensive with (i.e., share a boundary with) the horizontal interface15between the semiconductor substrate12and the dielectric layer14.

The cavity20has a maximum width W2, which may occur adjacent to the horizontal interface15between the semiconductor substrate12and the dielectric layer14. In an embodiment, the maximum width W2may coincide with the horizontal interface15between the semiconductor substrate12and the dielectric layer14. The maximum width W2of the cavity20may be less than the maximum width W1of the cavity18. The width difference may result from the pilot openings16,17used to form the cavity20having a smaller spacing than the pilot openings16,17used to form the cavity18. The width W2of the cavity20may narrow with increasing depth from the horizontal interface15. The cavity20has a maximum depth that may be measured relative to the horizontal interface15. The lower portions of the chambers32,33may be curved and may have a “W” shape with a cusped portion of the semiconductor substrate12separating the lower portions of the chambers32,33.

In an embodiment, the cavity22may include adjacent chambers34,35having upper portions that that merge during the isotropic etching process. The adjacent chambers34,35of the cavity22are associated with the overlying pair of pilot openings16,17with the formation of the chamber34initiating at the pilot opening16in the overlying pair and the formation of the chamber34initiating at the pilot opening17in the overlying pair. The merged upper portions of the chambers34,35result because of the lateral advance in the semiconductor substrate12of the etch fronts from the pair of pilot openings16,17. The cavity22and, more specifically, the upper portions of the chambers34,35may be coextensive with (i.e., share a boundary with) the horizontal interface15between the semiconductor substrate12and the dielectric layer14.

The cavity22has a maximum width W3, which may occur adjacent to the horizontal interface15between the semiconductor substrate12and the dielectric layer14. In an embodiment, the maximum width W3may coincide with the horizontal interface15between the semiconductor substrate12and the dielectric layer14. The maximum width W3of the cavity22may be less than the maximum width W2of the cavity20. The width difference may result from the pilot openings16,17used to form the cavity22having a smaller spacing than the pilot openings16,17used to form the cavity20. The width W3of the cavity22may narrow with increasing depth from the horizontal interface15. The cavity22has a maximum depth that may be measured relative to the horizontal interface15. The lower portions of the chambers34,35may be curved and may have a “W” shape with a cusped portion of the semiconductor substrate12separating the lower portions of the chambers34,35.

In an embodiment, the cavity24may include adjacent chambers36,37having upper portions that that merge during the isotropic etching process. The adjacent chambers36,37of the cavity24are associated with the overlying pair of pilot openings16,17with the formation of the chamber36initiating at the pilot opening17in the overlying pair and the formation of the chamber36initiating at the pilot opening17in the overlying pair. The merged upper portions of the chambers36,37result because of the lateral advance in the semiconductor substrate12of the etch fronts from the pair of pilot openings16,17. The cavity24and, more specifically, the upper portions of the chambers36,37may be coextensive with (i.e., share a boundary with) the horizontal interface15between the semiconductor substrate12and the dielectric layer14.

The cavity24has a maximum width W4, which may occur adjacent to the horizontal interface15between the semiconductor substrate12and the dielectric layer14. In an embodiment, the maximum width W4may coincide with the horizontal interface15between the semiconductor substrate12and the dielectric layer14. The maximum width W4of the cavity24may be less than the maximum width W3of the cavity22. The width difference may result from the pilot openings16,17used to form the cavity24having a smaller spacing than the pilot openings16,17used to form the cavity22. The width W4of the cavity24may narrow with increasing depth from the horizontal interface15. The cavity24has a maximum depth that may be measured relative to the horizontal interface15. The lower portions of the chambers36,37may be curved and may have a “W” shape with a cusped portion of the semiconductor substrate12separating the lower portions of the chambers36,37.

In an embodiment, the cavity26may include adjacent chambers38,39having upper portions that that merge during the isotropic etching process. The adjacent chambers38,39of the cavity26are associated with the overlying pair of pilot openings16,17with the formation of the chamber38initiating at the pilot opening16in the overlying pair and the formation of the chamber38initiating at the pilot opening17in the overlying pair. The merged upper portions of the chambers38,39result because of the lateral advance in the semiconductor substrate12of the etch fronts from the pair of pilot openings16,17. The cavity26and, more specifically, the upper portions of the chambers38,39may be coextensive with (i.e., share a boundary with) the horizontal interface15between the semiconductor substrate12and the dielectric layer14.

The cavity26has a maximum width W5, which may occur adjacent to the horizontal interface15between the semiconductor substrate12and the dielectric layer14. In an embodiment, the maximum width W5may coincide with the horizontal interface15between the semiconductor substrate12and the dielectric layer14. The maximum width W5of the cavity26may be less than the maximum width W4of the cavity24. The width difference may result from the pilot openings16,17used to form the cavity26having a smaller spacing than the pilot openings16,17used to form the cavity24. The width W3of the cavity26may narrow with increasing depth from the horizontal interface15. The cavity26has a maximum depth that may be measured relative to the horizontal interface15. The lower portions of the chambers38,39may be curved and may have a “W” shape with a cusped portion of the semiconductor substrate12separating the lower portions of the chambers39,39.

A dielectric layer42is formed on, and over, the dielectric layer14. The dielectric layer42extends over, and closes, the entrance to the open distal end of each of the pilot openings16,17. The closure of the pilot openings16,17seals the cavities in the semiconductor substrate12of which the cavities18,20,22,24,26are representative. The dielectric layer42may be comprised of a dielectric material, such as silicon dioxide, that is an electrical insulator.

The cavities18,20,22,24,26, after being sealed by the formation of the dielectric layer42, include respective airgaps that are unfilled by solid dielectric material and are instead filled by a gas, such as air. The airgap inside each of the scaled cavities18,20,22,24,26may be characterized by a permittivity or dielectric constant of near unity (i.e., vacuum permittivity), which is less than the permittivity of solid dielectric material. The airgap inside each of the sealed cavities18,20,22,24,26may be filled by atmospheric air at or near atmospheric pressure, may be filled by another gas at or near atmospheric pressure, or may contain atmospheric air or another gas at a sub-atmospheric pressure (e.g., a partial vacuum).

Additional cavities like the cavities18,20,22,24,26may be formed in the semiconductor substrate12, as shown inFIG.1, and then sealed by the formation of the dielectric layer42. The cavities, of which the cavities18,20,22,24,26are representative, are distributed in a pattern with prescribed density and width, as subsequently described. The cavities may be discrete and disconnected from each other.

A back-end-of-line stack45may be formed that includes an inductor44in at least one of its metallization levels. The inductor44includes turns or windings46,48,50that are arranged in a single spiral with the winding46being the outermost turn in the coiled arrangement and the winding50being the innermost turn in the coiled arrangement. The inductor44includes a terminal52and a terminal54that may be used to establish electrical connections used to power the inductor44during operation. The width W and cross-sectional area of the inductor44progressively narrow between the connection of the outer winding46to the terminal52and the connection of the inner winding50to the terminal54with the largest width W and cross-sectional area occurring adjacent to the connection of the outer winding46to the terminal52and the smallest width W and cross-sectional area occurring adjacent to the connection of the inner winding50to the terminal54. The inductor44has an outer perimeter41established by the outer winding46and an inner perimeter43established by the inner winding50.

The inductor44has a length between an end at the connection of the outer winding46to the terminal52and an opposite end at the connection of the inner winding50to the terminal54. The length of the inductor44is a measurement from one end to the opposite end and is the largest of the three dimensions (e.g., length, width, and thickness) of the inductor44. The inductor44spirals along its length between the opposite ends as the windings46,48,50progressively tighten with shrinking radius. In an embodiment, the width W of the windings46,48,50may be greater than the respective widths of the overlapped sealed cavities at any position along the length of the inductor44.

The back-end-of-line stack45includes interlayer dielectric layers comprised of dielectric materials, such as silicon dioxide or silicon nitride, that electrically insulating and that are disposed in a layer stack. The windings46,48,50may be formed by a damascene process in which trenches are formed by lithography and etching processes in one of the interlayer dielectric layers and those trenches and via openings are filled with one or more conductors (e.g., one or more metals) that are deposited and planarized. The primary conductor of the windings46,48,50may be comprised of a metal, such as copper or aluminum. The back-end-of-line stack45, which may include metallization levels formed over the metallization level including the inductor44, has a height H. In an embodiment, the depths of the cavities18,20,22,24,26relative to the horizontal interface15may be substantially equal to the height H. In an alternative embodiment, the depths of the cavities18,20,22,24,26relative to the horizontal interface15may be less than the height H.

The windings46,48,50of the inductor44are disposed over, and overlap with, the sealed cavities, of which the cavities18,20,22,24,26are representative, in the semiconductor substrate12. The cavity18and the cavity26are positioned beneath portions of the winding46, the cavity20and the cavity24are positioned beneath portions of the winding48, and the cavity26is positioned beneath a portion of the winding46. In an embodiment, portions of the winding46respectively overlap with the cavity18and the cavity26, portions of the winding48respectively overlap with the cavity20and the cavity24, and a portion of the winding50overlaps with the cavity26. In an embodiment, the respective portions of winding46may fully overlap with the cavity18and the cavity26, the respectively portions of the winding48may fully overlap with the cavity20and the cavity24, and the portion of the winding50may fully overlap with the cavity22.

The sealed cavities are arranged in a single spiral that is overlapped by the single spiral including the windings46,48,50. The footprint represented by the outer perimeter41and the inner perimeter43of the inductor44may be projected in a vertical direction relative to the horizontal interface15between the semiconductor substrate12and the dielectric layer14. The inner perimeter43may circumscribe and surround a core region of the inductor44that lacks windings and, when projected downwardly to the semiconductor substrate12, the inner perimeter43of the inductor44coincides with a region of the semiconductor substrate12that lacks cavities and that is interior to the region of the semiconductor substrate12that includes the cavities18,20,22,24,26.

The sealed cavities, of which the cavities18,20,22,24,26are representative, have a non-uniform width dimension over the length of the inductor44. For example, the width dimension of the sealed cavities may decrease with increasing distance along the length of the inductor44from the terminal52. For example, the width W1of the cavity18beneath the winding46may be greater than the width W5of the cavity26also beneath the winding46, the width W2of the cavity20beneath the winding48may be greater than the width W4of the cavity24also beneath the winding48, the width W1of the cavity18and the width W5of the cavity26beneath the winding46may be greater than the width W2of the cavity20beneath the winding48and the width W4of the cavity24beneath the winding48, and the cavity22beneath the winding50may have a width W3that is less than the widths W1, W2and that is less than the widths W4, W5. The decrease in the width dimension along the length of the inductor44may be correlated with the terminal52being biased at a larger potential, during operation, than the terminal54. In an embodiment, the rate of decrease of the width dimension of the sealed cavities may be described by a linear function. In an alternative embodiment, the rate of decrease of the width dimension of the sealed cavities may be described by a non-linear function, such as a linear function, a quadratic function, an exponential function, etc.

The density of the sealed cavities, which may be represented by the inter-cavity spacing, may decrease along the length of the inductor44between the end at the connection of the outer winding46to the terminal52and the opposite end at the connection of the inner winding50to the terminal54. In that regard, the density of the sealed cavities beneath the winding46may be greater than the density of the sealed cavities beneath the winding48, and the density of the sealed cavities beneath the winding48may be greater than the density of the sealed cavities beneath the winding50.

The inductor44may be deployed as a peaking inductor in a silicon photonics trans-impedance amplifier. The sealed cavities, of which the cavities18,20,22,24,26are representative, are non-uniformly placed in the semiconductor substrate12beneath the windings46,48,50of the inductor44. The sealed cavities include air gaps characterized by a low permittivity. The non-uniform distribution of the sealed cavities beneath the windings46,48,50of the inductor44may optimize the inductor performance benefit without violating design rule checks. For example, the airgaps included in the cavities18,20,22,24,26may function to increase the quality factor for the inductor44by reducing energy losses to the semiconductor substrate12.

The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. The chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product. The end product can be any product that includes integrated circuit chips, such as computer products having a central processor or smartphones.

References herein to terms modified by language of approximation, such as “about”, “approximately”, and “substantially”, are not to be limited to the precise value or precise condition as specified. In embodiments, language of approximation may indicate a range of +/−10% of the stated value(s) or the stated condition(s).

References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to a direction in the frame of reference perpendicular to the horizontal plane, as just defined. The term “lateral” refers to a direction in the frame of reference within the horizontal plane.

A feature “connected” or “coupled” to or with another feature may be directly connected or coupled to or with the other feature or, instead, one or more intervening features may be present. A feature may be “directly connected” or “directly coupled” to or with another feature if intervening features are absent. A feature may be “indirectly connected” or “indirectly coupled” to or with another feature if at least one intervening feature is present. A feature “on” or “contacting” another feature may be directly on or in direct contact with the other feature or, instead, one or more intervening features may be present. A feature may be “directly on” or in “direct contact” with another feature if intervening features are absent. A feature may be “indirectly on” or in “indirect contact” with another feature if at least one intervening feature is present. Different features may “overlap” if a feature extends over, and covers a part of, another feature.

The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.