Patent ID: 12191635

DETAILED DESCRIPTION

Two-dimensional arrays of VCSELs are capable of providing the higher output power needed for many applications and are separately capable of allowing specific elements or groups of elements of the array to be addressed for applications such as printing or producing directional or variable illumination patterns. Traditional approaches to fabricating arrays of VCSELs have often required at least one contact pad that must be connected by wire bonds. The wire bonds add packaging complexity and are a source of parasitic inductance that limits the bandwidth of the laser array when high current pulses are used.

U.S. Pat. No. 7,949,024 B2 describes the fabrication of etched mesas that are interconnected by flip-chip bonding to a separate submount with a metal interconnect pattern. The etched mesas are covered by an additional, conformal metal coating that provides for additional heat dissipation, environmental protection and for a larger contact area for the later flip-chip bonded assembly. Some of the mesas have a contact that allows current flow through the VCSEL device to produce light and others are electrically shorted so that current flows through metal that has been deposited on the outside of the mesas without going through the VCSEL device itself. An intra-cavity contact with a metal layer on the surface allows for lateral flow of current from the active (light-emitting) mesas to the shorted mesas. This architecture allows for both the anode and cathode contacts to be made on the same side of the laser die and for a single flip-chip assembly step to make all the contacts to a patterned sub-mount that provides the electrical contact to the mesas. This approach works very well for minimizing electrical parasitic inductance and capacitance or overall parasitic impedances for the array. However, the sub-mount is a high precision part that needs to have high thermal conductivity. This adds expense and the sub-mount still needs to be soldered to a PCB or put into a conventional sealed package that will in turn be soldered to a PCB assembly. The additional packaging is a source of further parasitic impedance.

An alternative approach is to build a VCSEL array that can be directly soldered to the PCB without an additional sub-mount or package. As described herein a VCSEL array design and fabrication process allows direct soldering of the VCSEL array to a PCB using conventional solder pad dimensions on the PCB and well-known surface-mount PCB assembly tools and processes, including tape and reel dispensing.

FIG.2shows a simplified cross-section of VCSEL array device100in accordance with the embodiment. The illustration shows a semiconductor device that is an array of surface-emitting lasers and solder bump contacts that are on a simple geometric pattern with a size and pitch large enough for mounting directly to printed circuit boards by conventional assembly processes known to those of ordinary skill in the art. The figure depicts the VCSEL array soldered to a simplified printed circuit board200.

The methods described herein may be used to fabricate arrays of other semiconductor devices, including external cavity versions of VCSELs, light emitting diodes, photodetectors, photomodulators and transistors. The illustration of the VCSEL device100is for illustration purposes and is not intended to limit the scope of the invention to any specific type of semiconductor device.

FIG.3is an inverted more detailed illustration of the selected part101ofFIG.2. In the embodiment, VCSEL array device100may include a substrate102which includes Gallium Arsenide (GaAs) or other semiconductor materials, such as Indium Phosphide (InP), Gallium Nitride (GaN) or Silicon (Si). The substrate may be doped as n or p-type or may be undoped depending on the design requirements, wavelength of operation and placement of the contact layer. The substrate may also be a material, such as Aluminum Oxide (Al2O3) that can be used as a substrate for the growth of semiconductor materials on the surface. Subsequent layers of semiconductor material may be deposited on the surface of the substrate102by epitaxial growth processes, such as Molecular Beam Epitaxy (MBE) or Metal-Organo-Chemical Vapor Deposition (MOCVD).

In an embodiment, a starting wafer with epitaxially grown layers is shown inFIG.4. A lattice-matched lower Distributed Bragg Reflector (DBR)104may be epitaxially deposited on substrate102(as shown inFIG.5) or above the substrate102(as shown inFIG.4) to form the first of the layers of the active VCSEL mesas103and the short-circuited or grounded mesas105(shown inFIG.3). The lower DBR may be formed from multiple layers of alternating semiconductor alloys that have different indices of refraction. Each layer boundary causes a partial reflection of an optical wave with the combination of layers acting as a high-quality reflector at a desired wavelength of operation. While the lower DBR104and upper DBR108are composed of many layers of material, in order to simplify the illustration, inFIG.4they are depicted as a single material. A portion, or all, of the lower DBR104may also be conductive to allow current to flow through the VCSEL device. An intracavity contact layer107may be located either at the interface of the lower DBR104and the substrate102as shown inFIG.4or as a layer inside the lower DBR as shown inFIG.5. The intracavity contact layer107may be a heavily doped semiconductor material to provide a conductive path connecting the mesas so as to allow lateral current flow through the device.

In an embodiment, an active region106may be epitaxially deposited on the lower DBR104. Region106is again shown as a single material, but is actually composed of multiple layered materials to provide correct spacing for the desired resonance wavelength and conductivity for the current flow in the device. Region106may also have the gain medium that emits light with electrical current flow. The choice of material used for the gain medium and the dimensions of the other layers may serve to select a working wavelength, which may range from 620 nm to 1600 nm for a GaAs substrate. Other material choices may extend that wavelength range in either or both directions.

As is understood by those skilled in the art, the emission wavelength of the VCSEL is determined by the choices of materials and layer thicknesses of the materials in the lower DBR104and upper DBR108, as well as the active region106. The gain material may be quantum wells, quantum dots or other semiconductor structures.

In the embodiment, upper DBR108may be positioned on the active region106and may also be electrically conductive. In some embodiments, lower DBR104may be p-doped and upper DBR108maybe n-doped, but some embodiments may reverse that order. The upper DBR108may also be partly or completely composed of a non-conducting dielectric layer stack that is not epitaxially grown semiconductor material, but rather thin-film layers deposited by evaporation or sputtering with electrical contact made to an intracavity contact layer within or below the upper DBR. As depicted inFIGS.4and5, all of these layers are typically in a single epitaxial structure grown on the substrate102which constitutes a starting point for subsequent processing steps. InFIG.4, the lower DBR104is positioned above the intracavity contact layer107and inFIG.5, the lower DBR104is positioned below the intracavity contact layer107, in each case with the active region106between the lower DBR and upper DBR (forming the distributed DBR).

The upper DBR108may terminate in a heavily-doped contact layer to facilitate an ohmic contact to a metal contact layer,120.FIG.6shows the initial deposition and patterning of the contact metal120to the upper DBR108surface, and the patterned dielectric layer114on top of the metal contact layer120using lithographic processes well known to those skilled in the art. If an ion-implanted confinement is part of the final structure, that implantation step may be performed prior to the contact. In that case, a prior metal deposition and patterning step may be performed to provide alignment features for the ion-implantation and subsequent steps.

The next step is illustrated inFIG.7and involves creation of the mesa structures103and105. A robust photolithographically defined mask is needed for etching of the mesas into the epitaxial layer structure. This may use the patterned dielectric layer114(shown inFIG.6), such as SiN or a combination of the dielectric material with a photoresist layer. The contact metal120patterned (as shown inFIG.6) is also protected by this layer. The exposed sides of the mesas103and105shown inFIG.7allow for lateral oxidation of one or more high aluminum content AlGaAs layers110as one approach to charge carrier and light confinement in the mesa. Note that the contact metal on top of the mesas may still be covered by the dielectric etch mask at this stage. Photoresist layers that may be part of the etch mask can be removed at this point.

The mesa etch may be a controlled etch process using dry (plasma) or wet etch processes that stops at the intracavity contact layer107, that is in the lower (n-type) DBR104, or just under the DBR at the interface of the lower DBR104and the substrate102. Selective etch stop layers may be part of the intracavity contact layer to produce a more uniform etch depth.

Another contact metal layer122, as shown inFIG.8, may be deposited and patterned at this point on the exposed surface of the intracavity contact layer107. This may typically be a metal layer structure optimized for making an ohmic contact to the contact layer. This may also be the point at which thermal annealing may be used to interdiffuse the contact metal into the semiconductor material surface. The active light-emitting mesas are mesas103and the shorted mesas are mesas105.

As shown inFIG.9, a second dielectric layer116may then be deposited on the wafer surface that covers all the features. This layer may allow for isolation of the shorted mesas from the active, light-emitting mesas. Another photolithography step may be used to define the regions of the dielectric layer116that need to be exposed by etching to allow electrical contact to the active mesas103where current will flow through the mesa structure to cause the laser to emit light. This step is also shown inFIG.9. Note that the dielectric layer116may only be removed from selected areas of the n-contact metal122.

The next step is illustrated inFIG.10, where a thick metal cap124is shown formed over the mesas124to protect the mesas, to make an electrical connection to the n-contact metal for the shorted mesas, to act as the p-contact for the active mesas, and to provide additional heat transfer. If this metal cap124may be deposited by electroplating, a thin “seed” metal layer123may be deposited first across the entire wafer to provide electrical continuity. A thick photoresist mask may then be applied and photolithographically patterned for a thick metal deposition. Removal of the photoresist may then be followed by a selective etch of the exposed seed metal layer.

As noted, the thick metal cap124on the mesas may be in electrical contact to the n-contact metal on the active laser mesas103while being separated from the mesa surface and the p-contact metal on the shorted mesas105by the remaining dielectric layer116. The thick metal cap124on the shorted mesas105overlap exposed area of the n-contact metal. This allows the return current from the VCSEL mesas to flow through the n-contact metal where it is in contact with the intracavity contact layer in or near the lower DBR108to the metal cap on the shorted mesas. Then the current flow does not go through the shorted mesa, but flows through the thick metal heat sink cap,124. The resulting structure is shown isFIG.10.

The metal mesa caps124may necessarily be on the same pitch as the mesas and may only be several microns larger than the original mesas depending on the thickness of the additional metal. An efficient VCSEL array may have the mesas located on a fine pitch and the mesas may usually be limited in size. The mesa caps124do not provide a compatible interface to solder pads on conventional PCBs.

The next steps are shown inFIG.11. A planarizing layer of nonconductive material128may be applied to the wafer in order to fill all the gaps between the mesas and provide a surface level with the tops of the metal caps124on the mesas. This may typically be done with spin deposition of a polymer like polyimide or bisbenzocyclobutene (BCB) or with a spin-on glass (sol-gel) formulation. Careful control of the parameters allows for the applied layer to match the height of the mesas. Additional solvent removal or mechanical polishing may be used to exactly match the height of the mesas. Other deposition processes may also be used to create the planar surface.

The two types of mesa,103and105, may be slightly different heights, due to the removal of layers114and116from the active mesas103. The height difference may be small enough that the planarization step can provide a sufficiently uniform contact pad surface130for soldering purposes.

Once the planarizing material is hardened or cured, a photolithographic pattern process may be completed to pattern interposer metal pads130that contact the metal caps. These pads can be much larger than the mesas and separately provide electrical contact to groups of active mesas or individual active mesas to form the anode pads and to groups of shorted mesas or individual shorted mesas to form cathode pads. The pad shapes and spacing may provide great flexibility in how the mesas are interconnected. The pad metal may be gold or a layered structure optimized for heat dissipation and high electrical conductivity. An example is a thin gold layer to contact the tops of the metal caps (also gold in this example) and then a thick layer of plated copper to provide high lateral conductivity and heat transfer. The effect of the pads130is to provide an interposer layer to allow the final solder bumps to be on a significantly different pitch and size than the mesas. The additional surface area and thermal mass can greatly increase the thermal dissipation of the VCSEL array compared to the metal heatsink caps124by themselves.

The pattern of the pad metal130may not be the best layout for compatibility with surface mount processes and may therefore be somewhat arbitrary in size and shape, in order to accommodate the patterns of mesas that need to be connected together, due to the functional, optical and electrical requirements for the VCSEL array. In order to provide a uniform array of contact pads ideally configured for soldering to PCB solder pads with automated assembly and solder reflow methods an additional metal structure of metal pads, posts, pillars or bumps132may be fabricated on the interposer pads130. InFIG.12, the metal pads, posts, pillars or bumps132are depicted as much thicker and larger than the VCSEL mesas, but may be smaller and may be patterned more densely, depending on the manufacturing processes available. The key point is that they provide for good mechanical and metallurgical bonding to the PCB solder pads and can be located on the underlying pad metal130so that they match up to the PCB solder pad dimensions and spacing. This allows separate optimization of the VCSEL array dimensions and spacing from the electrical contact functions of the device.

FIG.12illustrates the resulting metal structures according to a first embodiment, a combination of posts132and solder metal layer136that may provide the actual solder bonding surfaces for the VCSEL array. Copper electroplating of the posts132provides a thick structure that can carry large amounts of current with very low loss and low parasitic inductance. The copper posts may be terminated with a metal layer structure optimized for good adhesion and compatibility with common solders used for surface mount assembly. An example is a layer of gold on the surface of the copper posts132with a diffusion barrier of nickel followed by a thin corrosion barrier of gold. There are many variations of commonly used under bump metallization (UBM) known to those skilled in the art. The fabrication of the copper posts may require another application of a continuous thin metal seed layer, a thick photoresist layer photolithographically patterned to create the desired size and pitch of copper posts. After electroplating, and possibly replanarizing by chemo-mechanical polishing methods, the photoresist may be stripped, and any seed metal layer stripped away.FIG.12shows an optional additional solder metal layer136on the top of the metal posts. This layer136may be deposited electrochemically after the other metals in the post structure, or may be applied afterwards by other deposition methods, including evaporation, electroplating, jet deposition or mechanical application of discrete solder balls.

A second embodiment is shown inFIG.13in which an additional planarization layer134of polymer or other dielectric material is applied after the completion of the interposer metal pads130. This layer can also be patterned and used to define the shapes of the metal posts132, but may be left in place to insulate the interposer pads from the deposition of the solder136and from the soldering reflow process itself. The additional planarization dielectric134can also be left higher than the metal posts132to facilitate the assembly of discrete solder balls onto the metal post132surfaces.

Another embodiment, shown inFIG.14, does not use the plated copper posts, but uses a solder wetting barrier138directly on the anode and cathode pad metal130so that specific areas of the pad can have solder deposited or can be bonded with solder paste applied to the PCB. The solder wetting barriers can be dielectric material or metals known to those skilled in the art to not allow wetting by solders used for attachment to the PCB.

As embodiments of the VCSEL array design disclosed herein is for devices that will emit light through the surface of the substrate102, additional process steps may typically be needed for the other side of the wafer. At this point the side of the wafer with the mesas (the “active side”) may need to be protected while processing is performed on the other side (the “back side”) of the substrate wafer. One approach illustrated inFIG.15may be to encapsulate the exposed metal posts and the gaps between the posts in a removable resin140, such as photoresist or a wax or resin that can be applied uniformly and easily removed by solvents. A mechanical “handle” wafer (not shown), such as a silicon or quartz wafer may then be bonded to the surface of the resin140for additional mechanical support during the processing of the back side of the wafer.FIG.15shows the device structure with the resin encapsulation140in place and the substrate thinned by mechanical and chemo-mechanical means. The back side of the substrate is also polished for low scattering loss. An anti-reflection (AR) coating142can also be applied to reduce Fresnel reflection losses from the substrate surface. The AR coating can also be photolithographically patterned by an etch or liftoff process to provide labeling information as the light emission surface will be the surface visible after assembly.

A standoff structure in metal or a durable heat-resistant polymer material144can be applied to the back side of the wafer to provide protection of the AR coated surfaces during handling and assembly. The completed device, after removal of the any handle wafer and the encapsulating resin140is as shown inFIG.16. The resulting finished wafer can then be diced, and each individual die can be a completely packaged part with solder pads large enough in size and pitch to be soldered directly to a PCB by standard assembly techniques.

The backside or emission side of the wafer can also be used to fabricate optical structures, including microlenses, for control of beam direction and beam properties of the lasers.FIG.16further illustrates an example of a microlens146etched into the substrate for this purpose. This step can be done right after the wafer thinning step so that an AR coating142can then be applied to the lens surface. There are numerous processes for fabricating microlenses on the surface of the array that are known to those skilled in the art, including reflow of polymers, transfer etching of a resist profile formed by grayscale lithography or reflow of a resist. Diffractive structures including gratings, Fresnel lenses, kinoforms and computer-generated phase relief holograms may also be fabricated on the back side of the wafer for control and manipulation of the output beams of the VCSELs.

In some cases, the wavelength of the VCSELs will be designed to be short enough that the semiconductor substrate102is absorbing at the operating wavelength, resulting in unacceptable light emission losses even when the substrate is thinned.FIG.17shows a variation of the VCSEL array ofFIG.16in which the processing on the back (or emission) side of the wafer includes etching of vias148, in place of microlens146, so as to remove all substrate material in the beam path. This process may be enabled by including a suitable selective etch stop layer, known to those skilled in the art, in the epitaxial growth structure149at the interface of the lower DBR104and the substrate102. The via may then be patterned in photoresist on the backside of the wafer and a selective wet or dry etch may be used that will stop at the layer that greatly slows the etch process. An AR coating142may be applied to the exposed epitaxial layers149as well as the remaining substrate.

In other cases, it may be desirable to remove the substrate entirely from the wafer while it is still attached to a handle wafer, as discussed in reference toFIG.15. When that is done, the extremely thin epitaxial layers149that make up the VCSEL array and the added metal and planarization layers would be all that was left, as shown inFIG.18. A new support wafer150that is transparent to the laser wavelength may then be bonded to the exposed surface149as shown inFIG.19. The exposed semiconductor surface149or the surface of the transparent wafer can have an antireflection matching coating to minimize reflections between the two material that are likely to have a large index mismatch and high reflection losses. The emission side of the transparent wafer150can also have an AR coating142, as well as microlenses, other micro-optical devices, and protective standoff frames similar to those described above.

The transparent wafer150may have a high reflectivity coating on the surface so that it forms an extended cavity of the lasers for larger mode volume devices with higher power and improved brightness. This type of device is commonly referred to as a VECSEL. The transparent wafer150may also be a doped glass or crystalline laser gain medium with appropriate coating to make a diode-pumped solid-state laser array where the VCSEL laser elements are the pump lasers.

Another alternative embodiment is shown inFIG.20. In this embodiment, device160includes a second intracavity contact layer162that may be grown in the upper DBR structure. The upper DBR structure may be many fewer layers than in other embodiments or omitted completely, depending on the detailed laser design and replaced by a spacer layer and a doped contact layer configured to support the growth of a sequence of dielectric layers on top. The second intracavity contact layer162may be a heavily doped semiconductor layer that facilitates high lateral conductivity and provides a good ohmic metallic contact. Instead of a full upper DBR fabricated of epitaxial semiconductor alloys, as used in other embodiments, a separate mirror165may be deposited after the formation of a metal contact, such as an annular ohmic contact170, on the upper intracavity contact layer162. The annular ohmic contact170(shown inFIG.22) has an opening large enough for the planned laser aperture or a resonant LED if used for that purpose. The mirror165may be a dielectric stack of contrasting index of refraction materials commonly used by those skilled in the art of making high reflectivity, low loss laser mirrors. The dielectric mirror165may be designed for phase matching to the partial upper DBR layers168if they are used. The mirror165does not conduct current. The upper intracavity contact layer162conducts the current from the annular ohmic contact170. One advantage of this type of device is that the semiconductor-based DBR layers can be inefficient for longer wavelength lasers designs. This design approach also reduces ohmic losses as the current does not have to go through the full thickness of semiconductor DBR layers.

FIG.21shows in greater detail the epitaxial wafer structure ofFIG.20having the second intracavity contact layer162as well as the lower intracavity contact layer107and a reduced thickness top DBR layer structure168.FIG.22shows the same device structure after deposition and patterning of the annular metal layer170, which makes an ohmic contact to the top intracavity contact layer162. As shown inFIG.23, the laser mesa103in this case has the contact metal170patterned with an opening in the center of the mesa103. The mirror layers165are deposited over the ohmic contact170so that the opening is filled with the dielectric layers to create a high reflectivity laser cavity. The size of the final mirror, which may be a hybrid mirror combining the dielectric mirror layers with a partial upper DBR, needs to be large enough relative to the laser aperture formed by the oxidation of the high aluminum content layers110(shown inFIG.7) or by ion implant. InFIG.23the laser mesa103and the shorted or grounded mesa105are formed as described earlier. At this stage, fabrication of the completed device may be substantially the same as described above, provided care is taken to protect the mirror layers165during the process steps.

In accordance with an embodiment,FIGS.24-26illustrate top views of two exemplary layouts for a VCSEL array following the processes illustrated inFIGS.10-12. Active laser mesas103are grouped in the middle area, surrounded by n-contact metal122, which is ringed by shorted mesas105.FIG.24illustrates the sequence of capped mesas124formed by completion of the process illustrated inFIG.10.FIG.25illustrates the interposer pad metal130added as a result of the process illustrated inFIG.11.FIG.26illustrates the solder bumps136added to the tops of the metal posts132inFIG.12. As illustrated inFIG.25, for both layouts, interposer pad metal pattern130aconnects all of the active laser mesas103in parallel while the other interposer pad metal pattern130bconnects all the shorted mesas105together. In this embodiment, the metal posts132for pad metal pattern130aare the anode contacts of the device and the metal posts132for pad metal pattern130bare the cathode contacts of the device. Note: as illustrated in the left layout ofFIG.26, the metal posts132do not have to be cylindrical structures as in the example inFIGS.12-20. The shape of the metal contact posts may be designed for optimum solder contact area for ease of assembly, high thermal conduction into the PCB metal, strong mechanical solder bond strength and high conductivity and low inductance.

FIG.27illustrates another exemplary layout for a VCSEL array. As shown inFIG.27, the capped mesas124are configured similarly to the configurations ofFIG.24, but the active laser mesas103may be separated into two groups by a gap175. Likewise, the interposer pad metal130amay be separated into two areas for the VCSELs (active mesas)103, as shown inFIG.28. In this case the shorted mesas105are still all contacted in parallel for a low impedance current return path and because the VCSELs all share common ground connection through the intracavity contact layer in the lower DBR108. The metal contact posts132illustrated inFIG.29are also now separately connected into contact pads for soldering the device to a PCB, each connecting to a group of VCSELs (active mesas),103.

Separation of the active mesas (VCSELs) in this manner makes it possible to independently turn on and off the groups of VCSELs and allows for the groups of VCSELs to be independently modulated, such as by connecting the separate contacts through separate pads on the PCB. This is a very flexible embodiment for configuring a VCSEL array for specific applications through the final fabrication steps. The layout of the mesas103and105can be on a fixed pitch that is optimized for efficient current spreading through the array and for balanced heat load across the array and the final electrical configuration decided by the design of the interposer pad metal130pattern and the metal contact post132pattern.

Flexibility in the design of the contact pad layout130is limited by the fact that in the fabrication sequence depicted thus far the VCSELs are all connected in common through the intracavity contact layer. This contact layer, however, can be altered in the fabrication sequence by an additional trench etch or isolation implant so that groups of VCSELs (active mesas)103are isolated from each other. In such an embodiment, it is desirable to have an undoped semiconductor substrate102so that only the intracavity contact layer and any doped layers in the lower DBR104need to be made nonconducting in regions to separate the groups of VCSELs electrically. This may be accomplished by ion implantation into areas of the conductive layers so that the disordering of the implant renders those area nonconducting. Another approach is to do a second etch step after the mesa etch to physically isolate the regions from each other by etching through the intracavity contact layer and a remaining doped lower DBR layers.

FIG.30shows a top view of a VCSEL array in which an additional ion implant is used after the mesa etch step to render non-conducting regions138of the intracavity contact layer, and to make the lower DBR104nonconducting. The groups of VCSEL mesas and shorted mesas shown are now electrically isolated from each other. As shown inFIG.31, the interposer pad metal140aand140bare also electrically separated.FIG.32shows the metal contact post and solder areas142a,142b,142cand142dthat may make contact to separate PCB solder pads so that the cathode contacts of one part, for example anode contact142a, can be connected to the current supply through the PCB board. The cathode contacts142bthen are connected to the anode contacts142cof the second group. The current flow then returns to ground through cathode contacts142d. The result is to connect the two groups of lasers in series through the PCB connections.

It is possible to connect the cathode contacts142bto the anode contacts142con the die itself, so that only contacts142aand142dneed to be connected to the power and ground contacts on the PCB and the two regions of the die are connected in series. However, in the preferred embodiment as shown inFIG.32, the contact pads142a, and142bare isolated from contact pads142cand142dby the non-conducting region138so that the PCB designer can connect the two laser regions (142aand142c) in parallel or in series as preferred by the designer.

The embodiments of the present disclosure, while illustrated and described in terms of various embodiments, are not limited to the particular descriptions contained in the specification. Different materials and different combinations of elements may be used in a manner consistent with the present disclosure to develop additional embodiments. Additional alternative or equivalent components and elements may also be readily used to practice the present disclosure.