Patent ID: 12255584

DETAILED DESCRIPTION

FIG.1is a circuit diagram of an electronic device102including a typical amplitude regulator108for use with a Pierce oscillator104.

The device102comprises an oscillator circuit portion which in this example is a Pierce oscillator104. The Pierce oscillator104includes a Pierce inverter106having an input terminal XC1 and an output terminal XC2, where a crystal oscillator would be connected between the input terminal XC1 and output terminal XC2 of the inverter106. The crystal oscillator and any other circuitry relating to the Pierce oscillator104are not shown inFIG.1, however there are many suitable topologies known in the art per se.

The device102also includes an amplitude regulator circuit portion108which is arranged to supply a current IPIERCE to the inverter106within the Pierce oscillator104. The amplitude regulator108is arranged to monitor the voltage at the input terminal of the inverter106and to vary the current IPIERCE supplied to the inverter106in response to that monitored voltage.

The amplitude regulator108comprises first, second, and third PMOS transistors P1-3, and first and second NMOS transistors N1, N2. It will be appreciated that these transistors are conventional metal-oxide-semiconductor (MOS) field-effect-transistors (FETs) or ‘MOSFETs’. Each transistor has a respective gate, drain, and source terminal as is typical for such devices, and their respective connections are outlined below.

The respective source terminal of each of the first, second, and third PMOS transistors is connected to a positive supply rail AVDD, while the respective source terminal of each of the first and second NMOS transistors N1, N2 is connected to ground. In particular, the source terminal of the second NMOS transistor N2 is connected to ground via a fixed resistor R1.

An input node110of the amplitude regulator108is connected to the input terminal XC1 of the inverter106, the respective gate terminal of each of the first and second NMOS transistors N1, N2, and the respective drain terminal of each of the first NMOS transistor N1 and first PMOS transistor P1. An ‘AC coupling’ capacitor C1 is connected between the input node110and the gate terminal of N1, such that the first terminal of C1 is connected to the input node110and the second terminal of C1 is connected to the gate of N1.

A further resistor R2 is connected between the gate and drain terminals of the first NMOS transistor N1, where this resistor R2 sets the DC condition for the first NMOS transistor, i.e. sets N2 to its operating point.

The respective gate terminals of each of the first, second, and third PMOS transistors P1-3 are connected together and to the respective drain terminals of the second PMOS transistor P2 and second NMOS transistor N2. As a result, the second PMOS transistor P2 is ‘diode connected’ (i.e. due to the connection between its drain and gate terminals).

The drain terminal of the third PMOS transistor P3 is connected to a current input of the inverter106of the oscillator circuit portion104, and the gate terminal of P3 is connected to the gate terminal of P2 (and also the gate terminal of P1). Due to this arrangement, the second and third PMOS transistors P2, P3 form a current mirror, such that the current through the second PMOS transistor P2 is ‘reflected’ as the Pierce current IPIERCE supplied to the Pierce inverter106. These two currents may be equal, or may be scaled in accordance with a ratio of the W/L values of P2 and P3, as per a technique for current mirror design known in the art per se.

The amplitude regulator108operates to monitor the voltage at the input terminal XC1 of the inverter106, i.e. the voltage at the input of the crystal connected between XC1 and XC2 within the Pierce oscillator104.

A low pass filter, constructed from a filter resistor R3 and a filter capacitor C3, is connected between the input terminal110of the amplitude regulator108and the gate terminal of the second NMOS transistor N2.

Thus the voltage VGN2 applied to the gate terminal of N2 is a low pass filtered version of the voltage VGN1 applied to the gate terminal of N1, where the low pass filter function is provided by the first low pass filter R3, C3. This causes the conductance of the second NMOS transistor N2 to be dependent on the time-average amplitude of the voltage Vamp_XC1 at the input of the crystal in the crystal oscillator104, where the time-averaging is provided by the low pass filtering. This low pass filter also prevents high frequency fluctuations (e.g. due to noise) being applied to the gate terminal of N2.

Thus while the amplitude of the voltage Vamp_XC1 at the input of the crystal in the crystal oscillator104remains below a certain value, which is set through the choice of component values of the resistors R1-3, N2 is relatively conductive, which causes a current to pass through the diode-connected second PMOS transistor P2. Due to the current mirror formed by P2 and P3, this current is then reflected through P3 as the Pierce current IPIERCE that is provided to the inverter106as outlined above. Thus when Vamp_XC1 is low, IPIERCE is brought high so as to help set up oscillations, and to reduce start-up time of the oscillator.

As the amplitude of the voltage Vamp_XC1 at the input of the crystal in the crystal oscillator104ramps up, it will eventually reach approximately the desired cut-off level and the conductance of N2 is reduced, thereby reducing the Pierce current IPIERCE. Thus once Vamp_XC1 grows sufficiently large, the current IPIERCE decreases to a level just enough to maintain oscillation.

FIG.2is a graph showing a typical plot of IPIERCE vs Vamp_XC1 for the amplitude regulator108ofFIG.1. In particular, the graph shows three plots for this relationship, including a plot for a typical case30, a plot for a slow corner32, and a plot for a fast corner34.

As can be seen fromFIG.2, the value of Vamp_XC1 at which the supply current IPIERCE reaches the threshold current I_threshold is highly dependent on the process corner of the device. In particular, at fast corners (as shown in plot34), IPIERCE drops to I_threshold at a higher voltage amplitude at the input of the crystal Vamp_XC1 than in the typical case. Conversely, at slow corners (as shown in plot32), IPIERCE drops to I_threshold at a lower value of Vamp_XC1.

Due to this, the performance of the conventional amplitude regulator108can be unpredictable, and thus it can be difficult to optimise the phase noise and power consumption of the amplitude regulator108and associated oscillator circuit104.

FIG.3is a circuit diagram of an electronic device202including an amplitude regulator208for use with a Pierce oscillator204in accordance with an embodiment of the present invention. Portions of the circuit having a reference number starting with a ‘2’ correspond in form and function to the portions having corresponding numbers starting with a ‘1’ as outlined above in respect ofFIG.1, except where specified otherwise below.

The structure of the amplitude regulator208corresponds to the amplitude regulator108ofFIG.1, however the amplitude regulator208in accordance with an embodiment of the present invention has some additional features that, as is outlined below, advantageously allow the IPIERCE vs Vamp_XC1 curves for different corners to be brought closer together around a chosen operating point.

Firstly, in the amplitude regulator208ofFIG.3, the fixed resistor R1 used in the amplitude regulator108ofFIG.1is replaced with a variable resistor R1′ in the amplitude regulator208ofFIG.3. This ‘trimmable’ resistor R1′ is arranged such that its resistance can be varied. In this particular example, the variable resistor R1′ is constructed from a switched array of resistors, such that a suitable selection of the resistors in the array can be ‘switched in’ to set the overall resistance of the variable resistor R1′ to a desired value suitable for a particular crystal being used in the crystal oscillator204.

Additionally, the device202further comprises a current monitor210, which includes a number ‘m’ of current comparators212[0]-212[m], referred to collectively as current comparators212. Each current comparator212receives a respective reference current IREF at a respective reference input of that comparator212. While two comparators are shown inFIG.3, it will be appreciated that this is for ease of illustration, and any suitable number may be selected, as depicted by the dashed lines between the comparators212[0],212[m] inFIG.3.

The current monitor210receives a copy of the Pierce current IPIERCE supplied to the inverter206, where the copied current IP_COPY is generated via an additional current mirror formed by a fourth PMOS transistor P4. P4 is arranged such that its source terminal is connected to the positive supply rail AVDD and its drain terminal is connected to a respective current input of each of the current comparators212.

If the copy current IP_COPY (which is representative of the supply current (PIERCE) exceeds the respective current threshold of a given current comparator212, that current comparator212raises a respective comparator flag COMP_OUT which indicates that the supply current IPIERCE exceeds its respective threshold. Different thresholds may be set by selecting an appropriate reference current IREF for each comparator212and/or by scaling the copy current IP_COPY by different factors for each comparator212.

In a simple case, two comparators212may be used to check the supply current IPIERCE against upper and lower bounds. However, in practice, a more accurate determination of the value of IPIERCE may be made by having more comparators212(e.g. five comparators) to detect a narrower band in which the value of the current IPIERCE is at any given time, and thus a more accurate determination of the value of Vamp_XC1 can be made.

If either comparator212,214raises its respective output COMP_H, COMP_L indicating that the supply current IPIECE is out-of-bounds (i.e. outside its predetermined range as set by the reference currents IREF_H, IREF_L), an auto-calibration process may be carried out in a manner known in the art per se.

FIG.4is a graph showing a plot of IPIERCE vs Vamp_XC1 for the amplitude regulator208ofFIG.3at different process corners. Specifically,FIG.4shows: a plot for a typical case40; a slow corner plot42and fast corner plot44for the case where the amplitude regulator208is trimmed for when Vamp_XC1=0; and a slow corner plot46and fast corner plot48for the case where the amplitude regulator208is trimmed for a non-zero operating point.

The objective is to determine the value of Vamp_XC1 at I_threshold. InFIG.4, the y-axis is the IPIERCE current supplied from the circuit when Vamp_XC1=0, i.e. the start-up condition. As outlined previously, in the start-up process, a larger supply current IPIERCE is usually provided to start oscillation. Once the oscillation is established and stable (i.e. under steady state conditions), it is generally desirable to keep the supply current IPIERCE just enough to maintain the oscillation only without exceeding this value. Having just enough supply IPIERCE is also good for the phase noise performance of the oscillator.

Additionally,FIG.4also shows the slow and fast plots32,34associated with the conventional amplitude regulator108, as discussed previously with respect toFIG.2for ease of comparison.

As can be seen inFIG.4, by applying the trimming to R1′ in the amplitude regulator208ofFIG.3, the respective plots for the slow and fast corners42,44in the zero operating point and the respective plots for the slow and fast corners46,48in the non-zero operating point are ‘squeezed’ closer together compared to the respective plots for the slow and fast corners32,34associated with the conventional amplitude regulator108ofFIG.1. This indicates that there is less variation in the curves across the different corners for the amplitude regulator208ofFIG.3when compared to the amplitude regulator108ofFIG.1.

In the first trimming case, R1′ is trimmed such that the resistance of R1′ is set to force IPIERCE=I_threshold when the voltage Vamp_XC1 is set to zero, i.e. at the DC typical condition. This results in the respective slow and fast plots42,44being ‘pinched’ together, where the closest point between these plots is at the value of IPIERCE corresponding to when Vamp_XC1=0.

The respective points C and D where the respective slow and fast plots42,44cross the I_threshold line are closer together than they are for the corresponding plots32,34associated with the conventional amplitude regulator108.

As determinations of the value of the voltage Vamp_XC1 are made based on the current IPIERCE being supplied, these points C, D being closer together are illustrative of an improvement in the predictability of the Vamp_XC1 value, i.e. estimates of Vamp_XC1 made from the known current IPIERCE being supplied by the amplitude regulator208ofFIG.3are more accurate than with the conventional amplitude regulator108ofFIG.1.

In this first case where R1′ is trimmed for Vamp_XC1=0, the slow and fast plots42,44are closest together where Vamp_XC1=0. Thus while the threshold-crossing points C and D are closer together than in the conventional case, it is further advantageous to have the slow and faster corner plots closest together at the operating point, i.e. to minimise the variation in the possible IPIERCE vs Vamp_XC1 curves around the desired operating point, i.e. the value of Vamp_XC1 that is to be used during operation, rather than zero.

Thus in the second trimming case where R1′ is trimmed to the resistance value that sets IPIERCE=I_threshold at a non-zero operational value of Vamp_XC1, this results in the respective slow and fast plots46,48being pinched closest together at the operating point, i.e. where IPIERCE=I_threshold.

This results in the threshold-crossing points A, B (i.e. where plots46,48cross I_threshold) corresponding to the points at which the slow and fast plots46,48are closest, i.e. the predictability of Vamp_XC1 from supplied current IPIERCE is maximised at the operating point itself.

Thus, as outlined above, the trimming range is better for the second trimming case because it is narrower (i.e. the distance between point A and point B) at I_threshold than in the first trimming case (i.e. the distance between point C and point D).

It can be seen, therefore, that embodiments of the present invention provide an improved arrangement wherein the amplitude regulator that supplies the current to the oscillator circuit (which may be a Pierce oscillator) is arranged such that the trimmable resistor can be used to set the voltage at the input to the inverter (and thus the crystal) to a known value at the point at which the supply current is equal to the threshold current (i.e. the value at which the amplitude regulator is switched off). This may advantageously improve the predictability of the voltage at the input of the inverter (which is unknown at run time) from the current supplied to the inverter (which is known to the amplitude regulator) around that operating point.

Those skilled in the art will appreciate that the specific embodiments described herein are merely exemplary and that many variants within the scope of the invention are envisaged.