Patent ID: 12238937

DETAILED DESCRIPTION

In the SOT-MRAM system design, it is preferred that a lower switching current flows through the SOT channel layer, which switches the magnetization state of the perpendicular MTJ (“pMTJ”) with a higher spin HALL efficiency. The disclosed techniques are directed to a new structure of the SOT channel that has one or more magnetic insertion layers superposed or stacked with one or more heavy metal layer(s). Through proximity to a magnetic insertion layer, a surface portion of a heavy metal layer is magnetized to include a magnetization. The magnetization within the heavy metal layer enhances spin-dependent scattering, which leads to increased transverse spin imbalance. Resultantly, more spins are accumulated at the boundaries of the heavy metal layer, which generates stronger magnetic torques in the free layer of the pMTJ. In other words, the magnetic insertion layer improves the conversion rate from an in-plane current flowing through the SOT channel to a magnetic torque on the magnetization of the free layer of the pMTJ.

The magnetic insertion layer may have in-plane magnetic anisotropy or perpendicular magnetic anisotropy. The material of the magnetic insertion layer is selected such that the crystalline lattice of the magnetic insertion layer will not impact the adjacent heavy metal layer or the free layer of the pMTJ, and vice versa. The lattice matching or mismatching between the magnetic insertion layer and one or more of the heavy metal layer or the free layer of the pMTJ are determined based on the size and shape of the crystalline lattices thereof. The choice of the magnetic insertion layer material also depends on the magnetic anisotropy of the magnetic insertion layer. For example cobalt/platinum Co/Pt multilayer or cobalt/nickel Co/Ni multilayer may be used as perpendicular magnetic anisotropy (“PMA”) insertion layer(s). CoFeB magnetic alloy or permalloy (nickel-iron magnetic alloy) may be used as in-plane magnetic anisotropy (“IMA”) insertion layers.

With respect to a magnetic insertion layer of PMA, the overall thickness of the magnetic insertion layer or layers is controlled to be relatively thin, as compared to the free layer of the pMTJ, such that the magnetization of the free layer will not be pinned by the magnetic insertion layer(s). In an embodiment, the overall thickness of the magnetic insertion layer(s) is no more than about 30% of the thickness of the free layer. With respect to a magnetic insertion layer of IMA, the in-plane magnetization actually pulls the perpendicular magnetization of the free layer to an angle off the perpendicular orientation. This angled magnetization of the free layer tends to promote an easier switching between AP and P states of the pMTJ, while the angled magnetization is also less stable and sometimes blurs the distinction between the AP and the P states. The magnetization strength, e.g., the thickness, of the IMA insertion layer is optimized based on circuitry or device design with compromises between switching efficiency and MTJ state reading accuracy.

The SOT channel layer includes one or more magnetic insertion layers and one or more heavy metal layers stacked in an alternating manner. A magnetic insertion layer is adjacent to at least one heavy metal layer. A heavy metal layer is adjacent to at least one magnetic insertion layer. In an embodiment, the total number of the heavy metal layers is at least one more than the total number of the magnetic insertion layers such that the SOT channel layer includes a heavy metal layer on the top surface thereof and a heavy metal layer on the bottom surface thereof. In another embodiment, the total number of the magnetic insertion layers is at least one more than the total number of the heavy metal layers such that the SOT channel layer includes a magnetic insertion layer on the top surface thereof and a magnetic insertion layer on the bottom surface thereof. In a further embodiment, the total number of the magnetic insertion layers is the same as the total number of the heavy metal layers such that the SOT channel layer includes a magnetic insertion layer on a first surface thereof and a heavy metal layer on a second surface thereof that is opposite to the first surface.

The following disclosure provides many different embodiments, or examples, for implementing different features of the described subject matter. Specific examples of components and arrangements are described below to simplify the present description. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In the following description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the disclosure. However, one skilled in the art will understand that the disclosure may be practiced without these specific details. In other instances, well-known structures associated with electronic components and fabrication techniques have not been described in detail to avoid unnecessarily obscuring the descriptions of the embodiments of the present disclosure.

Unless the context requires otherwise, throughout the specification and claims that follow, the word “comprise” and variations thereof, such as “comprises” and “comprising,” are to be construed in an open, inclusive sense, that is, as “including, but not limited to.”

The use of ordinals such as first, second and third does not necessarily imply a ranked sense of order, but rather may only distinguish between multiple instances of an act or structure.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the content clearly dictates otherwise. It should also be noted that the term “or” is generally employed in its sense including “and/or” unless the content clearly dictates otherwise.

FIG.1shows an example 2T1MTJ bit cell100of a SOT-MRAM device. The bit cell100includes a SOT-MTJ device102that includes a MTJ structure110. The MTJ structure110includes a dielectric layer114sandwiched between a first ferromagnetic layer112and a second ferromagnetic layer116. The first ferromagnetic layer112and the second ferromagnetic layer116include a same magnetic anisotropy. Specifically, the first ferromagnetic layer112and the second ferromagnetic layer116either both have in-plane magnetic anisotropy or both have perpendicular magnetic anisotropy. In the description herein, for an illustrative example, the first ferromagnetic layer112and the second ferromagnetic layer116include perpendicular magnetic anisotropy. The magnetization or magnetic moment of the first ferromagnetic layer112maintains a fixed orientation or polarity, e.g., in the down direction as shown by a unidirectional arrow120, perpendicular to a substrate plane (not shown for simplicity) or a plane which the MTJ110sits on. The magnetization orientation of the second ferromagnetic layer116is switchable in the perpendicular axis, as shown by a bi-directional arrow122. The switchable magnetization orientation of the second ferromagnetic layer116represents two states thereof with respect to the magnetization orientation of the first ferromagnetic layer112, a parallel state “P” or an antiparallel state “AP”. In the “P” state, the magnetization orientation of the second ferromagnetic layer116is in the same direction as that of the first ferromagnetic layer112, here in the down direction. In the “AP” state, the magnetization orientation of the second ferromagnetic layer116is in a different direction from that of the first ferromagnetic layer112, here in the up direction. In the description herein, the first ferromagnetic layer112is referred to as a “reference layer” and the second ferromagnetic layer116is referred to as a “free layer.” The dielectric layer114is a tunnel barrier layer that acts as a barrier to the tunneling of charge carriers between the reference layer112and the free layer116.

A SOT channel layer130is positioned adjacent to and in electric coupling with the free layer116. In an embodiment, the SOT channel layer130is in direct contact with the free layer116. For example, an upper surface130U of the SOT channel layer130is in direct contact with a lower surface116L of the free layer116. In some embodiments, to maximize the spin Hall effect (“SHE”) between the SOT channel layer130and the free layer116, an interface area132between the SOT channel layer130and the free layer116substantially fully overlaps the lower surface116L of the free layer116. That is, the upper surface130U of the SOT channel layer130substantially fully overlaps the lower surface116L of the free layer116. In an embodiment, the upper surface130U is larger than the lower surface116L in at least some directions.

Due to the tunnel magnetoresistance effect, the resistance value between the reference layer and the free layer changes with the magnetization polarity switch in the free layer116. The parallel magnetizations (P state) lead to a lower electric resistance across MTJ110, whereas the antiparallel magnetizations (AP state) lead to a higher electric resistance across MTJ110. The two states of the resistance values are considered as two logic states “1” or “0” that are stored in the MRAM bit cell100.

The bit cell100includes three terminals R, W and S. In a read operation, a signal from a read control line, e.g., a read Word line140, turns on a read transistor142to enable a read current to flow between a Bit line and a source line through the MTJ structure110. A value of the read current indicates the resistance value of the MTJ, i.e., the logic state stored in the MRAM cell100. In a write operation, a signal from a write control line, e.g., a write Word line150, turns on a write transistor152to enable a write current to pass through the SOT channel130to generate a spin-orbit torque that changes the magnetization orientation of the free layer116. The mechanisms of the spin-orbit torque include one or more of spin Hall effect (“SHE”) or a Rashba effect. The relative ratios between the SHE and the Rashba effect depend on the device structure, fabrication processes and/or material choices. However, the current disclosure is applicable to and is not limited by all these factors and any resultant ratios between the SHE and Rashba effect. In the description herein, it is assumed that SHE dominates the spin-orbit torque (“SOT”). The terms “SHE” or “SOT” may be used interchangeably in referring to the spin-orbit torque.

As the MTJ110includes perpendicular anisotropy, some additional mechanisms may be used to deterministically switch the magnetization orientation of the free layer116. For example, an additional in-plane magnetic field may be applied. In another example, a shape anisotropy, e.g., the long axis, of the MTJ structure100may be position with a canting angle with a current flow direction of the SOT channel130. All such additional features are possible with the disclosed techniques included in the disclosure.

In some embodiments, the write operation may be implemented with a bidirectional current through the SOT channel130to set up the two magnetization orientations, e.g., up or down, in the free layer116. In other embodiments, the different magnetization orientations in the free layer116may be achieved through different switching mechanisms. For example, the AP state writing may be achieved through the SOT effect by an in-plane current passing through the SOT channel130, while the P state writing may be achieved through the STT effect via a current passing through the MTJ structure110in an opposite direction to the read operation. Other approaches of writing to the SOT-MRAM cell100are also possible and included in the disclosure.

In the example MRAM cell100, however, the SOT channel130includes a multilayer structure that includes one or more (two shown for illustration) heavy metal layers130HM of heavy metal materials and one or more (one shown for illustration) magnetic insertion layers130MI of magnetic material/magnetic properties. The heavy metal layers130HM and the magnetic insertion layers130MI are positioned adjacent to one another in an alternating manner. Each heavy metal layer130HM is adjacent to at least one magnetic insertion layer130MI. Each magnetic insertion layer130MI is adjacent to at least one heavy metal layer130HM.

Through proximity to a magnetic insertion layer130MI, a surface portion of a heavy metal layer130HM is magnetized to include a magnetization. The magnetization within the heavy metal layer130HM enhances spin-dependent scattering, which leads to increased transverse spin imbalance. Resultantly, more spins are accumulated at the boundaries of the heavy metal layer130HM, which generate stronger magnetic torques in the free layer116of the pMTJ110. In other words, the magnetic insertion layer130MI improves the conversion rate from an in-plane current flowing through the SOT channel130to a magnetic torque on the magnetic polarity of the free layer116of the pMTJ110.

FIGS.2,3and4show example embodiments of the SOT channel130. Referring toFIG.2, the SOT channel layer230includes three heavy metal layers230HM and two magnetic insertion layers230MI. The total number of the heavy metal layers230HM is more than the total number of the magnetic insertion layer230MI. As the heavy metal layers230HM and the magnetic insertion layers230MI are arranged in an alternating manner, the extra heavy metal layer230HM leads to the SOT channel layer230including a heavy metal layer230HM on both the top surface230U and the bottom surface230L of the SOT channel layer230.

As shown inFIG.2, a heavy metal layer230HM is on the top surface230U of the SOT channel230. An upper surface234HM of the heavy metal layer230HM interfaces with the free layer116of the MTJ structure110. A lower surface236HM of the heavy metal layer230HM interfaces with an upper surface234MI of an underlying magnetic insertion layer230MI. A lower surface236MI of the underlying magnetic insertion layer230MI interfaces with another heavy metal layer230HM. The identified upper surface and lower surface of a respective heavy metal layer230HM or a magnetic insertion layer230MI are opposite to one another.

In an embodiment, the two magnetic insertion layers230MI both have PMA in a same magnetic polarity, e.g., both pointing perpendicularly upward. In the case that the magnetic insertion layers230MI have perpendicular magnetic anisotropy “PMA”, the magnetization strength of the magnetic insertion layers230MI are controlled to be relatively low compared to that of the free layer116. In an embodiment, in a case that the magnetic insertion layers230MI are in the same perpendicular magnetic polarity orientation, the overall thickness of the two magnetic insertion layers230MI, i.e., T1+T2, is no more than ⅓ of the thickness T3 of the free layer116. In an alternative embodiment, the multiple magnetic insertion layers230MI are of different perpendicular magnetic polarity orientations. The magnetization strength of the most adjacent magnetic insertion layer230MI is relevant to the free layer116and the thickness T1 of the most adjacent magnetic insertion layer230MI is controlled to be no more than ⅓ of the thickness T3 of the free layer116.

In another embodiment, the magnetic insertion layers230MI have in-plane magnetic anisotropy “IMA.” The in-plane magnetization of the magnetic insertion layers230MI will pull the magnetization of the free layer116off the perpendicular direction with an angle. Because the magnetization of the free layer116is pulled off from the perpendicular direction, it is easier to switch the magnetization of the free layer116between the P state direction and the AP state direction. On the other hand, when the magnetization of the free layer is pulled off from the perpendicular orientation, the AP or P state of pMTJ structure110is less stable and it is more difficult to read the magnetoresistance state of the pMTJ structure110because the angled magnetization orientation of the free layer116tends to blur the distinction between the P and the AP states. As such, the magnetization strength of the magnetic insertion layers230MI are optimized based on the circuit design and/or the device designs. The magnetization strength of the IMA magnetic insertion layers230MI are related to the thickness T1, T2 of the respective IMA magnetic insertion layers230MI. Therefore, the thickness T1, T2 of the IMA magnetic insertion layers230MI is controlled based on the circuit designs and the device designs of the pMTJ structure110.

The heavy metal layers230HM are one or more of tungsten W, platinum Pt, tantalum Ta, or other suitable heavy metal materials. The material of the magnetic insertion layers230MI is selected such that the crystalline lattice of the magnetic insertion layer230MI and the crystalline lattice of the adjacent heavy metal layer230HM do not impact or mismatch one another. The lattice matching or mismatching between the magnetic insertion layer230MI and the adjacent heavy metal layer230HM is determined based on the size and the shape of the crystalline lattices thereof. For example, Fe, FeB, CoFeB, Fe3O4, or other magnetic materials have a lattice mismatch <5%. The choice of the magnetic insertion layer230MI material also depends on the magnetic anisotropy of the magnetic insertion layer. For example, in the case that the heavy metal layers230HM are one or more of W, Pt or Ta, the cobalt/platinum Co/Pt multilayer (or alloy) or cobalt/nickel Co/Ni multilayer (or alloy) may be used as perpendicular magnetic anisotropy PMA magnetic insertion layer(s)230MI. CoFeB magnetic alloy (“CFB”) or permalloy (nickel-iron magnetic alloy) may be used as in-plane magnetic anisotropy IMA insertion layers.

In some embodiments, for the PMA Co/Pt or Co/Ni multilayers, each of the Co, Pt, Ni layers may be about 2 Å to about 6 Å in thickness. As such, the magnetic insertion layers230MI may be about 4 Å to about 12 Å in thickness, T1, T2. For the magnetic insertion layer230MI of IMA, the CFB material may be deposited with a thickness of larger than 15 Å. A relatively thinner CFB layer, e.g., thickness smaller than 12 Å, generally exhibits a PMA property. A thicker CFB layer, e.g., thickness larger than 15 Å, generally exhibits an IMA property. The permalloy may be deposited with a thickness ranging from about 5 Å to about 20 Å.

In some embodiments, in the case that one or more of the heavy metal layers230HM is Pt, layers of cobalt Co may be used as the magnetic insertion layer. A cobalt layer itself may not have required magnetic anisotropy, while the interfacing between the Co and the Pt creates magnetic anisotropy and magnetization suitable for increasing the spin scattering within the Pt layers230HM.

FIG.3shows another embodiment of the SOT channel. In SOT channel330, the total number of magnetic insertion layers330MI, here two330MI layers, is more than the total number of heavy metal layer330HM, here one330HM layer. The magnetic insertion layers330MI and the heavy metal layer330HM are arranged adjacent to one another in an alternating manner. The top surface330U and the bottom surface330L of the SOT channel layer330are both magnetic insertion layers330MI. As the magnetic insertion layer330MI at the top surface330U interfaces with the free layer116, the material of the magnetic insertion layer330MI is selected such that the surface lattice of the magnetic insertion layer330MI and the surface lattice of the free layer116do not impact each other. The “impact” is determined based on whether the desired magnetic properties of either layers are substantially changed through the interfacing. The spin orientation of the free layer should not be substantially affected by the insertion layer, which could cause a tilting angle larger than 18 degrees or effectively cause a reduction in TMR more than 10%. Other than the above identified differences, the descriptions of the SOT channel layers130,230similarly apply to the SOT channel layer330, which is omitted for simplicity purposes.

FIG.4shows another example SOT channel430. The SOT channel430includes a same number of magnetic insertion layers430MI and heavy metal layers430HM arranged adjacent to one another in an alternating manner. One of the top surface430U or the bottom surface430L of the SOT channel layer430is magnetic insertion layers430MI and the other one of the top surface430U or the bottom surface430L of the SOT channel layer430is a heavy metal layer430HM.

As shown inFIGS.1,2,3,4, the magnetic insertion layers and the heavy metal layers in the SOT channels130,230,330,430are stacked vertically in an alternating manner. These examples do not limit the scope of the disclosure.FIG.5shows a top view of another example SOT channel530. As shown inFIG.5, the SOT channel530includes heavy metal layers530HM and magnetic insertion layers530MI arranged laterally adjacent to one another in an alternating manner. Other descriptions of the SOT channel530are similar to that of the other SOT channels130,230,330,430and are omitted for simplicity.

As shown inFIGS.1-5, the magnetic insertion layers in a SOT channel are separated from one another and the heavy metal layers in a SOT channel are separated from one another. These example embodiments do not limit the scope of the disclosure. In other embodiment, one or more of the magnetic insertion layers or the heavy metal layers in a SOT channel may be coupled to one another in various manners.

For example,FIG.6shows an example SOT channel630that includes a comb-shaped magnetic insertion layer630MI and a comb-shaped heavy metal layer630HM. The comb-shaped magnetic insertion layer630MI includes tooth elements632MI. The comb-shaped heavy metal layer630HM includes tooth elements632HM. The tooth elements632MI and the tooth elements632HM are arranged adjacent to one another in an alternating manner.

Other variants of the arrangements among the heavy metal layers and the magnetic insertion layers are also possible and included in the disclosure. The disclosed embodiments of the heavy metal layers and the magnetic insertion layers can be combined in various ways, which are also included in the disclosure.

FIG.7shows an example process700which may be used to make the MRAM100including the SOT-MTJ structure102or other semiconductor structures.FIGS.8A to8Eshow a wafer800in various stage of the process ofFIG.7.

Referring toFIG.7, in example operation710, a wafer800is received. The wafer800includes a substrate810and a transistor820formed over the substrate810. The transistor820includes a gate822, a first source/drain structure824and a second source/drain structure826. The wafer800also includes a first back-end-of-line (“BEOL”) level830that is formed over the transistor820and a first inter-level dielectric (“ILD”) layer832. For example, a Bit line834is on the first BEOL level830.FIG.8Ashows, as an illustrative example, that the first BEOL level830is one level, e.g., one layer of ILD832, over the transistor820, which is not limiting. The first BEOL level830may be formed on more than one level over the transistor820. All are included in the disclosure. The Bit line834is electrically coupled to the first source/drain structure824through interconnect structures836, e.g., a contact plug or via.

The substrate810may be a semiconductor substrate or a silicon-on-insulator substrate suitable for a front-end-of-line (“FEOL”) process. The substrate810may also be a back-end-of-line (“BEOL”) substrate having a dielectric surface layer and FEOL devices under the dielectric surface. As such, the transistor820may be FEOL transistor or a thin-film transistor formed over dielectric layers in a BEOL process.

The wafer800also includes a second BEOL level840formed at a different level from the first BEOL level830over the transistor820.FIG.8Ashows, as an illustrative example, that the second BEOL level840is formed over the first BEOL level830, which is not limiting. It is possible that the second BEOL level840is formed below the first BEOL level830while the Bit line834on the first BEOL level830is formed after structures on the second BEOL level840have been formed. The second BEOL level840is formed over the second ILD layer842. Interconnect structures846are already formed in the wafer800for coupling features on the second BEOL level840. In an example, the second interconnect structure846is electrically coupled to the second source/drain structure826of the transistor820.

In example operation720, with reference also toFIG.8B, a SOT channel850is formed on the second BEOL level840. Specifically, the SOT channel850is formed over the second ILD layer842. A first end850E1is coupled to the second interconnect structure846, which is coupled to the second source/drain structure826.

The formation of the SOT channel850, as an overall structure, may be implemented through any suitable approaches and all are included in the disclosure. For example, the SOT channel850materials may be initially formed as a layer(s) over the wafer800surface and later patterned to form the SOT channel850. For another example, a lift-off or a damascene process is used to form the SOT channel850. For example, a dielectric layer (not shown for simplicity) is formed over the second ILD layer842and is patterned to open an aperture exposing the second interconnect structure846. The SOT channel850is formed within the aperture. The excessive deposition material may be removed together with the dielectric material in a lift-off process or be removed through a CMP process in a damascene process. The dielectric layer may be further patterned to form other structures, e.g., a spacer structure adjacent to the SOT channel layer850. Optionally, an etch stop layer (not shown for simplicity), e.g., of silicon nitride is formed between the dielectric layer and the second ILD842. The specific examples of forming the SOT channel850are further described herein.

Optionally, an electrode layer (not shown for simplicity purposes), referred to as bottom electrode for descriptive purposes, is formed between the SOT channel layer850, e.g., the first end850E1thereof, and the second interconnect structure846.

In example operation730, with reference also toFIG.8C, a MTJ structure860is formed adjacent to, e.g., over, the SOT channel850. The MTJ structure860includes a first ferromagnetic layer862and a second ferromagnetic layer864, which are separated by a tunneling barrier layer866. As an illustrative example, the first ferromagnetic layer862has a fixed or “pinned” magnetization orientation and the second ferromagnetic layer864has a switchable or free magnetization orientation. The first ferromagnetic layer862is referred to as the “reference layer”862and the second ferromagnetic layer864is referred to as the “free layer”864. In an embodiment, the free layer864is one or more of Fe, Co, Ni, FeCo, CoNi, CoFeB, FeB, FePt, FePd or other suitable ferromagnetic material. The reference layer862is one or more of Fe, Co, Ni, FeCo, CoNi, CoFeB, FeB, FePt, FePd or other suitable ferromagnetic material. In an embodiment, the reference layer862is a synthetic anti-ferromagnetic structure that includes one or more non-magnetic (“NM”) metal layers each sandwiched between two pinned ferromagnetic (“FM”) layers. In an embodiment, the free layer864is a synthetic anti-ferromagnetic structure that includes a non-magnetic metal layer sandwiched between two free ferromagnetic layers. For example, the free layer864may include a Ta layer sandwiched between two CoFeB layers.

In some embodiments, a capping layer868, e.g., of WO2, NiO, MgO, Al2O3, Ta2O8, MoO2, TiO, GdO, Al, Mg, Ta, Ru or other suitable materials are formed over the reference layer862.

The layers of the MTJ860may be deposited over the surface of the wafer800and patterned to form the MTJ860structure. Other approaches, like the lift-off process or the damascene process, are also available to form the MTJ structure860. A shape anisotropy of the MTJ860may have a canting angle with a current flow direction of the SOT channel850.

In example operation740, with reference also toFIG.8D, optionally, a spacer870is formed adjacent to the MTJ structure860and the SOT channel850. The spacer870may be formed using any suitable deposition techniques and is typically formed conformally. The spacer870is one or more of SiN, SiC, Si3N4, SiON or other suitable dielectric materials that is different from the dielectric material of the first ILD layer832and/or the second ILD layer842, which is silicon oxide or low-K dielectric materials.

The example structure ofFIG.8Dis provided as an illustrative example of a SOT-MRAM cell and the silicon implementation. Alternative or additional MTJ structures and silicon implementations are also possible and included in the disclosure. For example the SOT-MRAM cell may also include an AP-coupling layer and a hard layer (not shown for simplicity) adjacent to the reference layer862to pin the magnetization orientation of the reference layer862. The SOT-MRAM cell may also include an antiferromagnetic layer and/or a ferromagnetic biasing layer adjacent to the free layer864, which functions to facilitate the SOT effect in switching the magnetization orientation of the free layer864. A bottom electrode may be formed adjacent to the SOT channel850and a top electrode may be formed adjacent to the reference layer862. These additional or alterative features are all possible and included in the disclosure.

FIG.8Dshows that in the MTJ structure860, the free layer864is stacked below the reference layer862for illustrative purposes. In other embodiment, the free layer864is stacked over the reference layer and the SOT channel layer850is position adjacent to the free layer over the reference layer.

In an embodiment, the reference layer862or the respective electrode thereof is electrically coupled to the Bit line834through interconnect structures and another transistor, which are not shown for simplicity.

FIG.8Dshows that the SOT channel850connects directly to the interconnect structure846, which is not limiting. The SOT channel850may be electrically coupled to the second source/drain structure826through an electrode and interconnect structures coupled to the electrode.

The ILD layers832,842are each silicon oxide or suitable low-K dielectric materials.

In example operation750, with reference also toFIG.8E, a source line882is formed over a third BEOL level880. The source line882is coupled, through interconnect structures886, to a second end850E2of the SOT channel850. In an embodiment, an in-plane write current is configured to flow from the first end850E1to the second end850E2.

FIG.9shows an example process900of forming an example SOT channel850, which is similar to the example SOT channel130ofFIG.1.FIGS.10A to10Cshow various stages of a wafer800in the example process900.

Referring toFIG.9, in example operation910, with reference also toFIG.10A, a first layer1020of a heavy metal material, e.g., tungsten, is formed over a substrate, e.g., the substrate810having the second ILD layer832. The first tungsten layer1020is deposited as a thin film using pulsed laser deposition, chemical vapor deposition, atomic layer deposition, physical vapor deposition or other suitable deposition techniques. In an embodiment, a physical vapor deposition process, e.g., sputtering, is used to form the first tungsten layer1020. In an embodiment, the first tungsten layer1020is formed through a lift-off process such that the first tungsten layer1020is patterned upon deposition.

The thickness of the first tungsten layer1020is controlled to be in a range of about 5 Å to about 15 Å. In an embodiment, the thickness of the first tungsten layer1020is controlled to be in a range of about 5 Å to about 10 Å. The controlled thickness ranges facilitate the SOT effects in that electrons bunce between/among the dielectric molecules deposited on upper surface1020U and/or lower surface1020L of the first tungsten layer1020.

In example operation920, a magnetic insertion layer1040of Co/Pt multilayer is formed over the first tungsten layer1020. The Co/Pt layer1040is formed through physical vapor deposition, e.g., sputtering, at room temperature such that the surface lattice structure of the Co/Pt multilayer is maximally maintained. The Co/Pt layer1040is formed through the lift-off process.

In example operation930, a second tungsten W layer1060is formed over the Co/Pt multilayer1040using similar processes as those for forming the first Co/Pt multilayer1020.

It should be appreciated that the SOT channel850may include more or less heavy metal layers1020,1060and more magnetic insertion layers1040.

The layers1020,1040or1060of the SOT channel layer850may be annealed with a relatively low temperature, e.g., around 400° C., for reflow control purposes. The annealing preferably does not change or modify the crystalline lattice structure of the heavy metal layers1020,1060or the magnetic insertion layer1040.

In the description herein, the read and write lines of the MRAM cells are illustrated as implemented through Word lines, which is not limiting. It is also possible, depending on MRAM circuitry design, that the read and write lines are implemented through Bit lines. For example,FIG.11illustrates an example MRAM architecture1100. In the example architecture1100, the write Bit line and the read Bit line are controlled by an example write enable signal which, for example, turns on/off the transistors to enable the write or read function of each MRAM cell in the architecture1100. Other SOT-MRAM architectures are also possible and included in the disclosure.

In the description herein, the SOT channel850is formed before and below the MTJ structure860, which is not limiting. In other embodiments, the SOT channel is formed over the MTJ structure, with the free layer of the MTJ structure stacked over the reference layer. The SOT channel being formed subsequent to the MTJ structure is advantageous in some scenarios because the SOT channel will not be impacted by the annealing process of modifying the lattice structures of the ferromagnetic layers of the MTJ structure.

The source/drain regions824,826includes one or more of Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, silicon-carbon-phosphide (“SiCP”), silicon-germanium-boron (“SiGeB”) or other suitable semiconductor materials and may be doped in-situ during the epitaxy process by the supply of impurity sources or may be doped through post implantation process. The possible dopants include boron for SiGe, carbon for Si, phosphorous for Si or SiCP.

The gate electrode822of the transistor820includes a conductive material, e.g., a metal or a metal compound. Suitable metal materials for the gate electrode include ruthenium, palladium, platinum, cobalt, nickel, and/or conductive metal oxides and other suitable P type metal materials and may include hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), aluminides and/or conductive metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), and other suitable materials for N type metal materials. In some examples, the gate electrode822includes a work function layer tuned to have a proper work function for enhanced performance of the field effect transistor devices. For example, suitable N type work function metals include Ta, TiAl, TiAlN, TaCN, other N type work function metal, or a combination thereof, and suitable P type work function metal materials include TiN, TaN, other p-type work function metal, or a combination thereof. In some examples, a conductive layer, such as an aluminum layer, is formed over the work function layer such that the gate electrode includes a work function layer disposed over the gate dielectric and a conductive layer disposed over the work function layer and below the gate cap. In an example, the gate electrode has a thickness ranging from about 8 nm to about 40 nm depending on design requirements.

The gate dielectric layer includes a high dielectric constant (high K) dielectric material selected from one or more of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), combinations thereof, and/or other suitable materials. A high K dielectric material, in some applications, may include a dielectric constant (K) value larger than 6. Depending on design requirements, a dielectric material of a dielectric contact (K) value of 9 or higher may be used. The high K dielectric layer may be formed by atomic layer deposition (ALD) or other suitable technique. In accordance with embodiments described herein, the high K dielectric layer includes a thickness ranging from about 10 to about 30 angstrom (Å) or other suitable thickness.

The substrate810may include a silicon substrate in crystalline structure and/or other elementary semiconductors like germanium. Alternatively or additionally, the substrate may include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, and/or indium phosphide. Further, the substrate may also include a silicon-on-insulator (SOI) structure. The substrate may include an epitaxial layer and/or may be strained for performance enhancement. The substrate may also include various doping configurations depending on design requirements as is known in the art such as p-type substrate and/or n-type substrate and various doped regions such as p-wells and/or n-wells.

The semiconductor structure/transistor device820is a lateral or a vertical transistor or other semiconductor devices, like bipolar devices. The transistor is finFET, tunnel FET (“TFET”), gate-all-around (“GAA”) or other devices depending MRAM circuitry design.

FIG.8Eshows that the SOT-MTJ structure850,860is formed subsequent to the transistor820of the MRAM circuit. This example does not limit the scope of the disclosure. In other embodiments, the SOT-MTJ structure may be formed before or at a same layer level as the respective transistors, which are all included in the disclosure.

The present disclosure may be further appreciated with the description of the following embodiments:

In a method embodiment, a first heavy metal layer is formed over a substrate. A first magnetic layer is formed adjacent to the first heavy metal layer. A first surface of the first magnetic layer interfaces a first surface of the first heavy metal layer. A magnetic tunnel junction structure is formed vertically adjacent to one or more of the first heavy metal layer or the first magnetic layer. The magnetic tunnel junction includes a reference layer, a tunneling barrier layer and a free layer.

In a structure embodiment, a structure includes a magnetic tunnel junction structure that includes a reference layer, a free layer and a tunneling barrier layer sandwiched between the reference layer and the free layer. A spin-orbit torque layer is vertically adjacent to the free layer of the magnetic tunnel junction structure. The spin-orbit torque layer includes a vertical stack of a first heavy metal layer and a first magnetic layer

In a memory device embodiment, a memory device includes a substrate, a transistor over the substrate, and a magnetoresistive random access memory cell over the transistor. The transistor has a first source/drain terminal, a second source/drain terminal and a gate terminal. The magnetoresistive random access memory cell includes a magnetic tunnel junction structure and a spin-orbit torque structure vertically adjacent to the magnetic tunnel junction structure and coupled to a first source/drain terminal of the transistor. The spin-orbit torque structure includes a first heavy metal layer, and a first magnetic insertion layer interfacing with the first heavy metal layer.