Patent ID: 12199178

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

A semiconductor device according to an embodiment of the present invention includes: a semiconductor layer of a first conductivity type made of SiC having an Si surface; a gate trench dug down from the surface of the semiconductor layer; a gate insulating film formed on a bottom surface and a side surface of the gate trench so that the ratio of the thickness of a portion located on the bottom surface to the thickness of a portion located on the side surface is 0.3 to 1.0; and a gate electrode embedded in the gate trench through the gate insulating film.

According to the structure, the gate trench is dug down from the surface of the semiconductor layer of the first conductivity type made of SiC having the Si surface. The gate insulating film is formed on the bottom surface and the side surface of the gate trench. The gate electrode is embedded in the gate trench through the gate insulating film.

Thus, a trench gate MOSFET having such a MOS (Metal Oxide Semiconductor) structure that the gate electrode (Metal) is opposed to the semiconductor layer (Semiconductor) through the portion (Oxide) of the gate insulating film located on the side surface of the gate trench is formed in the semiconductor device.

In the MOSFET, the ratio of the thickness of the portion of the gate insulating film located on the bottom surface to the thickness of the portion located on the side surface is 0.3 to 1.0. Even if the thickness of the portion located on the bottom surface is increased so that dielectric breakdown can be suppressed, excessive increase in the thickness of the portion located on the side surface can be suppressed due to the lower limit of 0.3 of the ratio (thickness of portion located on bottom surface/thickness of portion located on side surface). When the thickness of the portion located on the bottom surface is designed to a proper value, on the other hand, the thickness of the portion located on the side surface is not excessively reduced, due to the upper limit of 1.0. Consequently, dielectric breakdown of the portion located on the bottom surface can be suppressed while suppressing increase in the thickness of the portion located on the side surface by properly designing the thickness of the portion located on the bottom surface.

Preferably, the semiconductor device further includes a body region of a second conductivity type formed in the semiconductor layer on a side portion of the gate trench and in contact with the gate insulating film on the side surface of the gate trench and a source region of a first conductivity type formed on a surface layer portion of the body region adjacently to the gate trench, and the gate insulating film contains nitrogen.

According to the structure, the body region of the second conductivity type in contact with the gate insulating film on the side surface of the gate trench is formed in the semiconductor layer on the side portion of the gate trench. On the surface layer portion of the body region, the source region of the first conductivity type is formed adjacently to the gate trench. In the trench gate MOSFET in the semiconductor device, therefore, a portion in the vicinity of the interface between the body region and the gate insulating film is a channel portion in which a channel is formed due to an electric field from the gate electrode. In the semiconductor device, the gate insulating film contains nitrogen, whereby channel mobility of the MOSFET can be improved.

Preferably in the semiconductor device, the concentration of an impurity of the second conductivity type in the body region is not more than 1019cm−3.

If the impurity concentration in the body region on the side portion of the gate trench is in excess of 1019cm−3, the side surface of the trench is oxidized at a relatively extremely high oxidation rate with respect to the bottom surface of the trench when the bottom surface and the side surface of the gate trench are oxidized, and the portion of the gate insulating film located on the side surface is remarkably thickened.

When the impurity concentration in the body region is not more than 1019cm−3, on the other hand, the ratio of the oxidation rate for the side surface of the trench to the oxidation rate for the bottom surface of the trench can be maintained at a proper value when the bottom surface and the side surface of the gate trench are oxidized. Consequently, increase in the thickness of the portion of the gate insulating film located on the side surface can be suppressed.

Preferably, the semiconductor device further includes an implantation layer formed by implantation of an impurity in a portion of the semiconductor layer reaching an intermediate portion of the semiconductor layer in the thickness direction from the bottom surface of the gate trench.

The implantation layer is so formed immediately under the bottom surface of the gate trench that the ratio of the thickness of the portion of the gate insulating film located on the bottom surface to the thickness of the portion located on the side surface can be set to 0.3 to 1.0 by oxidizing the bottom surface of the trench at a relatively high oxidation rate with respect to the side surface of the trench when the bottom surface and the side surface of the gate trench are oxidized after the formation of the implantation layer.

Preferably, the implantation layer is formed by implantation of an impurity of the second conductivity type.

When the implantation layer is formed by implantation of the impurity of the second conductivity type different from the conductivity type of the semiconductor layer, an energy barrier formed between the implantation layer and the semiconductor layer can be enlarged. Therefore, a current can be rendered hardly flowable to the implantation layer. Consequently, the electric field concentration on the bottom surface of the gate trench can be suppressed.

Preferably in the semiconductor device, the thickness of the portion of the gate insulating film located on the side surface of the gate trench is not more than 2000 Å.

If the thickness of the portion located on the side surface of the gate trench is in excess of 2000 Å, the semiconductor device must be operated with a high gate-on voltage (about 20 V, for example), and an efficient transistor operation may not be executable.

When the thickness of the portion located on the side surface of the gate trench is not more than 2000 Å, on the other hand, the semiconductor device can be operated with a proper gate-on voltage, and an efficient transistor operation can be achieved.

Preferably, an end portion of the bottom portion of the gate trench in a direction orthogonal to the gate width is bent outward.

According to the structure, the end portion of the bottom portion of the gate trench on which an electric field easily concentrates at a turn-off time is so bent that the electric field applied to the end portion can be dispersed to portions other than the end portion. Consequently, dielectric breakdown of the portion of the gate insulating film located on the bottom surface can be suppressed.

Preferably, the semiconductor device further includes a source wire formed on the semiconductor layer and in contact with the source region, and the source wire has a polysilicon layer in the portion in contact with the source region, and has a metal layer on the polysilicon layer.

In order to form the source wire212in the semiconductor device201shown inFIG.11, for example, Ni is first deposited by sputtering on the surfaces (the surfaces of the source regions209and the body contact regions210) of regions (impurity regions) of the epitaxial layer203doped with impurities. Then, Ni is silicified by reacting with Si contained in SiC through a heat treatment at a high temperature (about 1000° C., for example), to be brought into ohmic contact with the impurity regions. Thus, the nickel silicide layer218is formed. Thereafter Al is deposited on the nickel silicide layer218by sputtering. Thus, the aluminum layer219is formed, to form the source wire212.

When the nickel silicide layer218is formed, however, carbon (C) remaining in SiC is deposited on the surface of the nickel silicide layer218and in the vicinity of the interface between the nickel silicide layer218and the impurity regions, to form a carbon layer containing a large quantity of C. The carbon layer is so poor in adhesiveness to a metal or SiC that the nickel silicide layer218is easily peeled from the aluminum layer219or the impurity regions.

Preferably in the semiconductor device, therefore, the source wire brought into contact with the source region has the polysilicon layer in the portion in contact with the source region, and has the metal layer on the polysilicon layer.

Polysilicon can form excellent ohmic contact with the region (the impurity region) of SiC doped with the impurity. Therefore, silicification indispensable for a structure having a metal layer directly in contact with a source region can be omitted. Thus, formation of a carbon layer can be prevented on the surface of the polysilicon layer and in the vicinity of the interface between the polysilicon layer and the source region. Consequently, layer peeling can be suppressed between the polysilicon layer and the metal layer as well as between the polysilicon layer and the source region. Thus, connection reliability of the source wire can be improved.

Preferably in the semiconductor device, an intermediate layer containing Ti is interposed between the polysilicon layer and the metal layer.

A material containing titanium has excellent adhesiveness with respect to both of a polysilicon material and a metal material. In the semiconductor device having the layer containing titanium interposed between the polysilicon layer and the metal layer, therefore, adhesiveness between the polysilicon layer and the metal layer can be improved. Consequently, the connection reliability of the contact wire can be further improved.

Preferably in the semiconductor device, the metal layer has a layer containing Al, and the intermediate layer has a structure obtained by laminating a Ti layer and a TiN layer in this order from the side of the polysilicon layer.

While Al can be utilized as an impurity for providing the polysilicon layer with conductivity, the resistance of the polysilicon layer utilized as the source wire may be unstabilized unless Al is mixed into the polysilicon layer in a proper quantity.

In the structure of the semiconductor device, therefore, the TiN layer is interposed between the layer containing Al and the polysilicon layer, as a barrier layer for preventing diffusion of Al into the polysilicon layer. Thus, no excessive Al diffuses into the polysilicon layer, whereby the impurity concentration in the polysilicon layer can be stabilized. Consequently, the resistance of the polysilicon layer can be stabilized.

A method of manufacturing a semiconductor device according to the embodiment of the present invention includes the steps of: forming a gate trench on a surface layer portion of a semiconductor layer of a first conductivity type made of SiC having an Si surface to be dug down from the surface; forming a gate insulating film on a bottom surface and a side surface of the gate trench by oxidizing the bottom surface and the side surface of the gate trench in gas containing nitrogen and oxygen at a heat treatment temperature of not less than 1200° C.; and forming a gate electrode on the gate insulating film to fill up the gate trench.

When the bottom surface and the side surface of the gate trench are oxidized under the conditions (the atmosphere gas and the heat treatment temperature) in the method, the ratio of the thickness of a portion of the gate insulating film located on the bottom surface to the thickness of a portion located on the side surface can be set to 0.3 to 1.0.

Preferably, the bottom surface and the side surface of the gate trench are oxidized in gas containing at least N2O in the step of forming the gate insulating film, and N2O gas is fed at a flow rate of not more than 30% with respect to the total flow rate of fed gas in the step of forming the gate insulating film.

The step of forming the gate insulating film may include the steps of charging the semiconductor layer into a resistance heating furnace, producing a nitrogen-and-oxygen-containing gas atmosphere by introducing gas containing nitrogen and oxygen into the resistance heating furnace, and controlling the heating temperature in the resistance heating furnace to not less than 1200° C. while maintaining the gas atmosphere.

The following is known as the background technique related to heating of a semiconductor layer made of SiC, for example:

More specifically, a MOSFET having a MOS (Metal Oxide Semiconductor) structure formed by an SiC layer having an activated ion region on a surface layer portion thereof, a gate oxide film formed on the surface of the SiC layer and a gate electrode formed on the gate oxide film and opposed to the ion region through the gate oxide film, for example, is known as a semiconductor device employing SiC.

In order to prepare such a MOS structure, impurity ions are first implanted into the surface layer portion of the SiC layer, for example. Then, the SiC layer is heated in a resistance heating furnace, whereby the implanted ions are activated. After the activation of the ions, the gate oxide film is formed on the surface of the SiC layer by feeding oxygen-containing gas in a CVD (Chemical Vapor Deposition) apparatus. Then, the gate electrode is formed on the gate oxide film by sputtering. Thus, a layered structure (the MOS structure) of the gate electrode (Metal), the gate oxide film (Oxide) and the SiC layer (Semiconductor) is produced.

In order to activate the ions in the SiC layer, the SiC layer must be annealed at a temperature of 1600 to 1700° C., for example. In the resistance heating furnace, it takes a long time to heat the SiC layer up to a high temperature range, and hence Si sublimates from the surface of the SiC layer by the so-called Si escape, to roughen the surface of the SiC layer. Consequently, the interface between the SiC layer and the gate oxide film is irregularized, to reduce channel mobility of the MOSFET.

Therefore, a technique of suppressing surface roughening of the SiC layer by utilizing a high-frequency induction heater for reducing the time for heating the SiC layer up to the high temperature range and thereafter forming the gate oxide film through a gate oxidation furnace is employed.

However, such a technique separately requires two apparatuses, i.e., the high-frequency induction heater and the gate oxidation furnace, and hence the device cost is disadvantageously increased.

Another technique of forming a carbon film on the surface of the SiC layer in advance of the activation of the ions and preventing the Si escape with the carbon film thereby maintaining planarity on the surface of the SiC layer is proposed.

The carbon film is prepared by forming a film containing carbon on the surface of the SiC layer and heating the film containing carbon in the high-frequency induction heater thereby evaporating elements other than carbon from the film, for example.

According to studies made by the inventors, however, a heating temperature for forming the carbon film may be about 1000° C., which is lower than the temperature (1600 to 1700° C.) for activating the ions. Therefore, the heating temperature must be controlled in two stages, while it has been recognized difficult to precisely temperature-control the high-frequency induction heater.

After the activation of the ions, the carbon film is no longer required. The unrequited carbon film is oxidized and removed with oxidizing gas in an apparatus different from the high-frequency induction heater. While the oxidizing gas may be introduced into the high-frequency induction heater to remove the carbon film subsequently to the activation of the ions, a carbon material is used for a heating element of the high-frequency induction heater and hence the carbon material is oxidized when fed with the oxidizing gas. Therefore, a carbon film removing apparatus is inevitably additionally required, to unavoidably increase the device cost.

In order to attain an object of providing a method of manufacturing a semiconductor device capable of suppressing roughening on the surface of an SiC layer through simple temperature control without increasing the device cost, the inventors have provided the following invention:

More specifically, the method of manufacturing a semiconductor device according to the invention includes the steps of forming an organic material film on the surface of an SiC layer having a surface layer portion into which ions have been implanted, altering the organic material film into a carbon film by heating the organic material in a resistance heating furnace after the formation of the organic material film, activating the ions in the SiC layer by heating the SiC layer provided with the carbon film in the resistance heating furnace, oxidizing and removing the carbon film by introducing oxygen-containing gas into the resistance heating furnace, and forming an oxide film by oxidizing the surface of the SiC layer with the oxygen-containing gas in the resistance heating furnace continuously after the removal of the carbon film.

According to the method, the organic material film is heated in the resistance heating furnace after the formation of the organic material film, whereby the organic material film is altered into the carbon film, and the carbon film is formed on the surface of the SiC layer. After the formation of the carbon film, the SiC layer is heated in order to activate the ions in the SiC layer. Thereafter the carbon film is oxidized and removed by introducing the oxygen-containing gas into the resistance heating furnace. After the removal of the carbon film, the surface of the SiC layer is oxidized with the oxygen-containing gas continuously in the resistance heating furnace, so that the surface of the SiC layer is oxidized with the oxygen-containing gas and the oxide film is formed.

The carbon film is formed on the surface of the SiC layer in advance of the heating for activating the ions, whereby Si escape from the surface of the SiC layer can be prevented when the SiC layer is heated. Therefore, roughening on the surface of the SiC layer can be suppressed, and planarity on the surface of the SiC layer can be maintained. Consequently, the interface between the SiC layer and the oxide film can be smoothed, whereby channel mobility of the semiconductor device can be improved.

Further, the four steps of altering the organic material film into the carbon film by heating the same, activating the ions by heating the SiC layer, oxidizing and removing the carbon film with the oxygen-containing gas, and forming the oxide film by oxidizing the surface of the SiC layer can be continuously carried out in a single resistance heating furnace. No apparatus for removing the carbon film or the like is additionally required, whereby increase in the device cost can also be suppressed. Further, the resistance heating furnace is so employed that the heating temperature for forming the carbon film and that for activating the ions can be precisely and simply controlled.

The oxygen-containing gas may be gas containing oxygen and nitrogen. When the oxygen-containing gas for forming the oxide film contains oxygen and nitrogen, the channel mobility of the semiconductor device can be further improved.

Gas containing NO (nitrogen monoxide), N2O (dinitrogen oxide) or the like, for example, can be employed as the gas containing oxygen and nitrogen.

Preferably, the surface of the SiC layer is defined by a (0001) plane, i.e., an Si surface.

As hereinabove described, the inventors have provided the invention utilizing the resistance heating furnace as the invention related to heating of the semiconductor layer made of SiC.

When the step of forming the gate insulating film includes the steps of charging the semiconductor layer into a resistance heating furnace, producing a nitrogen-and-oxygen-containing gas atmosphere by introducing gas containing nitrogen and oxygen into the resistance heating furnace, and controlling the heating temperature in the resistance heating furnace to not less than 1200° C. while maintaining the gas atmosphere, therefore, functions/effects of the aforementioned invention utilizing the resistance heating furnace can be attained in addition to those of the present invention.

Embodiments of the present invention are now described in detail with reference to the attached drawings.

FIG.1is a schematic sectional view of a semiconductor device according to a first embodiment of the present invention.

A semiconductor device1has a structure obtained by arranging a plurality of unit cells of a trench gate VDMOSFET in the form of a matrix.FIG.1shows only part of the plurality of unit cells.

The semiconductor device1includes an SiC substrate2forming the base thereof. The SiC substrate2is doped with an N-type impurity in a high concentration (1018to 1021cm−3, for example). The SiC substrate2has a surface21(an upper surface) formed by an Si surface and a rear surface (a lower surface)22formed by a C surface.

An N−-type epitaxial layer3made of SiC (silicon carbide) doped with an N-type impurity in a lower concentration than the SiC substrate2is laminated on the surface21of the SiC substrate2. The epitaxial layer3as a semiconductor layer is formed on the SiC substrate2by the so-called epitaxy. The epitaxial layer3formed on the surface21, i.e., the Si surface, is grown on a major growth surface formed by an Si surface. Therefore, a surface31of the epitaxial layer3formed by the growth is an Si surface, similarly to the surface21of the SiC substrate2.

A portion (a base layer portion) on the side of the C surface of the epitaxial layer3opposite to a portion (a surface layer portion) on the side of the Si surface forms an N−-type drain region4entirely maintaining the state after the epitaxy. The drain region4has an N-type impurity concentration of 1015to 1017cm−3, for example.

On the other hand, a P-type body region5is formed on the surface layer portion of the epitaxial layer3. The body region5is in contact with the drain region4from the side (the Si surface side) of the surface31of the epitaxial layer3. The body region5has a P-type impurity concentration of 1016to 1019cm−3, for example.

A gate trench6is dug down in the epitaxial layer3from the surface31thereof. A plurality of such gate trenches6(not shown inFIG.1) are formed at regular intervals to parallelly extend in the same direction (a direction orthogonal to the plane ofFIG.1: the direction may hereinafter be referred to as a “direction along the gate width”), thereby forming a striped structure, for example.

Each gate trench6has a pair of planar side surfaces7opposed to each other at an interval and orthogonal to the surface31respectively and a bottom surface8having a portion parallel to the surface31. The gate trench6passes through the body region5in the thickness direction, and the deepest portion (the bottom surface8) thereof reaches the drain region4.

A gate insulating film9is formed on the inner surfaces of the gate trench6and the surface31of the epitaxial layer3, to cover the overall regions of the inner surfaces (the side surfaces7and the bottom surface8) of the gate trench6. The gate insulating film9consists of an oxide film containing nitrogen, such as a silicon oxynitride film formed by thermal oxidation with nitrogen-containing gas, for example. The nitrogen content (the nitrogen concentration) in the gate insulating film9is 0.1 to 10%, for example.

In the gate insulating film9, the thickness T2of a portion (an insulating film bottom portion11) located on the bottom surface8is smaller than the thickness T1of portions (insulating film side portions10) located on the side surfaces7. More specifically, the ratio (thickness T2of insulating film bottom portion11/thickness T1of insulating film side portion10) of the thickness T2of the insulating film bottom portion11to the thickness T1of the insulating film side portions10is 0.3 to 1.0, preferably 0.5 to 1.0. Further specifically, the thickness T1of the insulating film side portions10is 300 to 1000 Å, and the thickness T2of the insulating film bottom portion11is 150 to 500 Å, for example.

Agate electrode12is embedded in the gate trench6by filling up the inner side of the gate insulating film9with a polysilicon material doped with an N-type impurity in a high concentration.

On a surface layer portion of the body region5, N+-type source regions13are formed on both sides of the gate trench6in a direction (the right-and-left direction inFIG.1) orthogonal to the gate width. The source regions13are doped with an N-type impurity in a higher concentration than the drain region4. The source regions13have an N-type impurity concentration of 1018to 1021cm−3, for example. The source regions13extend in the direction along the gate width on positions adjacent to the gate trench6.

The epitaxial layer3is provided with P+-type body contact regions14passing through central portions of the source regions13in the direction orthogonal to the gate width from the surface31thereof to be connected to the body region5. The body contact regions14are doped with a P-type impurity in a higher concentration than the body region5. The body contact regions14have a P-type impurity concentration of 1018to 1021cm−3, for example.

In other words, the gate trench6and the source regions13are alternately provided in the direction orthogonal to the gate width, and extend in the direction along the gate width respectively. Boundaries between the unit cells adjacent to one another in the direction orthogonal to the gate width are set on the source regions13along the source regions13. At least one or more body contact regions14are provided over two unit cells adjacent to each other in the direction orthogonal to the gate width. The boundaries between the unit cells adjacent to one another in the direction along the gate width are so set that the gate electrode12included in each unit cell has a constant gate width.

An interlayer dielectric film15made of SiO2is laminated on the epitaxial layer3. A contact hole16exposing the surfaces of the source regions13and the body contact regions14is formed in the interlayer dielectric film15and the gate insulating film9.

A source wire17is formed on the interlayer dielectric film15. The source wire17is in contact (electrically connected) with the source regions13and the body contact regions14through the contact hole16. The source wire17has a polysilicon layer18in the portion in contact with the source regions13and the body contact regions14, and has a metal layer20on the polysilicon layer18.

The polysilicon layer18is a doped layer made of doped polysilicon doped with an impurity, and preferably a high-concentration doped layer doped with the impurity in a high concentration of 1019to 1021cm−3, for example. The impurity for forming the polysilicon layer18as the doped layer (including the high-concentration doped layer) can be prepared from an N-type impurity such as P (phosphorus) or As (arsenic) or a P-type impurity such as B (boron). The polysilicon layer18fills up the contact hole16. The thickness of the polysilicon layer18is 5000 to 10000 Å, for example, depending on the depth of the contact hole16.

The metal layer20is made of aluminum (Al), gold (Au), silver (Ag) or copper (Cu), an alloy thereof, or a metal material containing the same, for example. The metal layer20forms the outermost layer of the source wire17, and a metal wire or the like, for example, is connected (bonded) thereto. The thickness of the metal layer20is 1 to 5 μm, for example.

In the source wire17, an intermediate layer19containing titanium is interposed between the polysilicon layer18and the metal layer20. The intermediate layer19is formed by a single layer containing titanium (Ti) or a plurality of layers including the layer. The layer containing titanium can be prepared from titanium, titanium nitride or the like. The thickness of the intermediate layer19is 200 to 500 nm, for example.

The aforementioned source wire17having the polysilicon layer18, the intermediate layer19and the metal layer20preferably has a multilayer structure (Poly-Si/Ti/TiN/Al) obtained by successively laminating polysilicon (the polysilicon layer18), titanium (the intermediate layer19), titanium nitride (the intermediate layer19) and aluminum (the metal layer20).

A drain wire23is formed on the rear surface22of the SiC substrate2. The drain wire23is in contact (electrically connected) with the SiC substrate2. The drain wire23has a polysilicon layer24in the portion in contact with the SiC substrate2, and has a metal layer26on the polysilicon layer24.

The polysilicon layer24can be made of a material similar to that constituting the aforementioned polysilicon layer18. The thickness of the polysilicon layer24is 1000 to 2000 Å, for example.

The metal layer26can be made of a material similar to that constituting the aforementioned metal layer20. The metal layer26forms the outermost layer of the drain wire23, and is bonded to a die pad of a lead frame when the SiC substrate2is bonded to the die pad, for example. The thickness of the metal layer26is 0.5 to 1 μm, for example.

In the drain wire23, an intermediate layer25containing titanium is interposed between the polysilicon layer24and the metal layer26. The intermediate layer25can be made of a material similar to that constituting the aforementioned intermediate layer19.

A gate wire27is in contact (electrically connected) with the gate electrode12through a contact hole (not shown) formed in the interlayer dielectric film15.

A prescribed voltage (a voltage of not less than a gate threshold voltage) is applied to the gate wire27while a prescribed potential difference is caused between the source wire17and the drain wire23(between a source and a drain), whereby a channel is formed in the vicinity of the interface between the body region5and the gate insulating film9due to an electric field from the gate electrode12. Thus, a current flows between the source wire17and the drain wire23, and the VDMOSFET is turned on.

FIGS.2A to2Nare schematic sectional views for illustrating a method of manufacturing the semiconductor device1shown inFIG.1in step order.

First, an SiC crystal is grown on the surface21(the Si surface) of the SiC substrate2by epitaxy such as CVD (Chemical Vapor Deposition), LPE (Liquid Phase Epitaxy) or MBE (Molecular Beam Epitaxy) while doping the same with an impurity, as shown inFIG.2A. Thus, the N−-type epitaxial layer3is formed on the SiC substrate2. Then, a P-type impurity is implanted into the epitaxial layer3from the surface31thereof. While the implantation conditions vary with the type of the P-type impurity, acceleration energy is 200 to 400 keV, for example.

Thus, a region (a P-type implantation region28) into which the P-type impurity has been implanted is formed on the surface layer portion of the epitaxial layer3, as shown inFIG.2B. Due to the formation of the P-type implantation region28, the drain region4isolated from the P-type implantation region28while maintaining the state after the epitaxy is formed on the base layer portion of the epitaxial layer3.

Then, a mask29made of SiO2is formed on the epitaxial layer3by CVD, as shown inFIG.2C. Then, the mask29is etched through a photoresist film (not shown) into a pattern having openings30in regions for forming the body contact regions14. After the formation of the openings30, a P-type impurity is implanted into the epitaxial layer3from the surface31thereof. While the implantation conditions vary with the type of the P-type impurity, acceleration energy is 30 to 200 keV, for example. Thus, regions (P+-type implantation regions32) into which the P-type impurity has been implanted in a high concentration are formed on a surface layer portion of the P-type implantation region28. After the implantation of the P-type impurity, the mask29is removed.

Then, a mask33made of SiO2is formed on the epitaxial layer3by CVD (Chemical Vapor Deposition), as shown inFIG.2D. Then, the mask33is etched through a photoresist film (not shown) into a pattern having openings34in regions for forming the source regions13. After the formation of the openings34, an N-type impurity is implanted into the epitaxial layer3from the surface31thereof. While the implantation conditions vary with the type of the N-type impurity, acceleration energy is 30 to 200 keV, for example. After the implantation of the N-type impurity, the mask33is removed. Thus, a region (an N+-type implantation region35) into which the N-type impurity has been implanted in a high concentration is formed on the surface layer portion of the P-type implantation region28.

Then, the epitaxial layer3is heat-treated at a temperature of 1400 to 2000° C., for example, as shown inFIG.2E. Thus, the implanted N- and P-type impurities are activated, whereby the body region5is formed on the surface layer portion3of the epitaxial layer3, while the source regions13and the body contact regions14are formed on the surface layer portion of the body region5.

Then, a mask36made of SiO2is formed on the overall region of the surface31of the epitaxial layer3by CVD or thermal oxidation, as shown inFIG.2F. The mask36may alternatively be made of SiN or the like through CVD.

Then, the mask36is etched through a photoresist film (not shown) into a pattern having an opening37in a region for forming the gate trench6, as shown inFIG.2G.

Then, mixed gas (SF6/O2gas) containing SF6(sulfur hexafluoride) and O2(oxygen) is introduced into the surface31of the epitaxial layer3through the opening37, as shown inFIG.2H. Thus, the epitaxial layer3is dry-etched from the surface31(the Si surface), and the gate trench6having the bottom surface8having the portion (the Si surface) parallel to the surface31and the side surfaces7orthogonal to the Si surface is formed. After the formation of the gate trench6, the mask36is removed.

Then, the SiC substrate2is introduced into a diffusion furnace, and the inner surfaces (the side surfaces7and the bottom surface8) of the gate trench6and the surface31of the epitaxial layer3are thermally oxidized by feeding nitrogen-containing gas while heating the diffusion furnace, as shown inFIG.2I. N2O gas or NO gas, for example, can be employed as the nitrogen-containing gas. A heater temperature (a heating temperature) in the diffusion furnace is 1200 to 1350° C., for example, and a feeding time (an oxidation time) for the nitrogen-containing gas is 3 to 5 hours, for example. The gate trench6is formed in the epitaxial layer3made of SiC, and hence the oxidation of the inner surfaces of the gate trench6progresses under the condition that the oxidation rate for the bottom surface8having the Si surface and that for the side surfaces7orthogonal to the Si surface satisfy the following relational expression:
Oxidation rate for bottom surface 8/oxidation rate for side surface 7<0
Thus, the gate insulating film9is formed so that the thickness of the portion (the insulating film bottom portion11) located on the bottom surface8is smaller than that of the portions (the insulating film side portions10) located on the side surfaces7.

Then, a doped polysilicon material is deposited on the epitaxial layer3by CVD, as shown inFIG.2J. The deposited polysilicon material is etched back until the etched-back surface is flush with the surface31of the epitaxial layer3. Thus, portions of the polysilicon layer located outside the gate trench6are removed, and the gate electrode12is formed by the polysilicon material remaining in the gate trench6.

Then, the interlayer dielectric film15made of SiO2is laminated on the epitaxial layer3by CVD, as shown inFIG.2K. Then, the interlayer dielectric film15and the gate insulating film9are so patterned that the contact hole16exposing the source regions13and the body contact regions14is formed in the interlayer dielectric film15and the gate insulating film9.

Then, a polysilicon material38is laminated by CVD to fill up the contact hole16, as shown inFIG.2L.

Then, an N- or P-type impurity is implanted into the deposited polysilicon material, as shown inFIG.2M. While the implantation conditions vary with the type of the N- or P-type impurity, acceleration energy is 10 to 100 keV, for example. Thus, the polysilicon layer18doped with the impurity in a high concentration is formed.

Then, titanium and titanium nitride are deposited in this order on the surface of the polysilicon layer18by a method such as sputtering or vapor deposition to form the intermediate layer19, as shown inFIG.2N. Then, aluminum is deposited on the surface of the intermediate layer19by a method such as sputtering or vapor deposition, to form the metal layer20. Then, the metal layer20, the intermediate layer19and the polysilicon layer18are worked into a prescribed pattern, to form the source wire17. Then, the gate wire27connected to the gate electrode12is formed. Thereafter the drain wire23having the polysilicon layer24, the intermediate layer25and the metal layer26is formed on the rear surface22of the SiC substrate2by a method similar to that for the source wire17.

The semiconductor device1shown inFIG.1is obtained through the aforementioned steps.

In the semiconductor device1, as hereinabove described, the gate trench6is dug down from the surface31(the Si surface) of the epitaxial layer3made of SiC. Therefore, oxidation of the inner surfaces of the gate trench6progresses under the condition that the oxidation rate for the bottom surface8having the Si surface and that for the side surfaces7orthogonal to the Si surface satisfy the following relational expression:
Oxidation rate for bottom surface 8/oxidation rate for side surface 7<0

In the aforementioned method, the inner surfaces of the gate trench6are thermally oxidized with the nitrogen-containing gas, dissimilarly to thermal oxidation (dry oxidation) employing oxygen gas or thermal oxidation (wet oxidation) employing water vapor (H2O) gas. Therefore, the ratio (oxidation rate for bottom surface8/oxidation rate for side surface7) of the oxidation rate for the bottom surface8to that for the side surfaces7can be increased as compared with a case where the gate insulating film9is formed by dry oxidation or wet oxidation.

In the gate insulating film9formed in the aforementioned manner, the ratio (thickness T2of insulating film bottom portion11/thickness T1of insulating film side portion10) of the thickness T2of the insulating film bottom portion11to the thickness T1of the insulating film side portions10is in the range of 0.3 to 1.0.

Even if the thickness T2of the insulating film bottom portion11is increased so that dielectric breakdown can be suppressed, excessive increase in the thickness T1of the insulating film side portions10can be suppressed due to the lower limit of 0.3 of the ratio (thickness T2of insulating film bottom portion11/thickness T1of insulating film side portion10). When the thickness T2of the insulating film bottom portion11is designed to a proper value, on the other hand, the thickness T1of the insulating film side portions10is not excessively reduced, due to the upper limit of 1.0. Consequently, dielectric breakdown of the insulating film bottom portion11can be suppressed while suppressing increase in the thickness T1of the insulating film side portions10by properly designing the thickness T2of the insulating film bottom portion11.

Further, the gate insulating film9consists of the silicon oxynitride film formed by thermal oxidation employing the nitrogen-containing gas, whereby channel mobility of the VDMOSFET can be improved.

FIGS.3A and3Bare schematic plan views of a semiconductor device according to a second embodiment of the present invention, withFIG.3Ashowing the overall semiconductor device andFIG.3Bshowing an inner portion thereof in an enlarged manner.

A semiconductor device41according to the second embodiment of the present invention is a trench gate power VDMOSFET (an individual device) employing SiC, in the form of a chip square in plan view, for example. The chip-like semiconductor device41has a length of about several mm in the right-and-left (vertical) direction in the plane ofFIG.3A.

The semiconductor device41has an SiC substrate42and a large number of unit cells44formed on the SiC substrate42and partitioned by a gate trench43latticed in plan view. In other words, the unit cells44in the form of rectangular parallelepipeds arranged in window portions of the latticed gate trench43respectively are aligned on the SiC substrate42in the form of a matrix. Each unit cell44has a length of not more than 10 μm in the right-and-left (vertical) direction in the plane ofFIG.3B, for example, and a source trench45, square in plan view, dug down from the surface side toward the side of the SiC substrate42is formed at the center thereof.

A source pad46is formed on the surface of the semiconductor device41. The source pad46is generally in the form of a square having outwardly bent four corners in plan view, and formed to generally cover the overall region of the surface of the semiconductor device41. A removed region47is formed in the source pad46by partially removing the same in a generally square manner in plan view, on a position slightly leftward in the right-and-left direction in the plane ofFIG.3A.

Agate pad48is arranged on the removed region47. An interval is provided between the gate pad48and the source pad46, which are insulated from each other.

FIG.4is a schematic sectional view of the semiconductor device41according to the second embodiment of the preset invention, taken along a line IV-IV inFIG.3B.

The sectional structure of the semiconductor device41is described with reference toFIG.4. The semiconductor device4includes the SiC substrate41of an N+-type (having a concentration of 1018to 1021cm−3, for example). The SiC substrate42has a surface49(an upper surface) formed by an Si surface and a rear surface50(a lower surface) formed by a C surface.

An N−-type epitaxial layer51made of SiC having a lower concentration (1015to 1017cm−3, for example) than the SiC substrate42is laminated on the SiC substrate42. The epitaxial layer51as a semiconductor layer is formed on the SiC substrate42by the so-called epitaxy. The epitaxial layer51formed on the surface49, i.e., the Si surface, is grown on a major growth surface formed by an Si surface. Therefore, a surface52of the epitaxial layer51formed by the growth is an Si surface, similarly to the surface49of the SiC substrate42.

On the side of the epitaxial layer51closer to the surface52(the Si surface), a P-type body region53is provided in the form of a well over a wide range, with a concentration of 1016to 1019cm−3, for example. A region of the epitaxial layer51closer to the SiC substrate42(the C surface) than the body region53forms an N−-type drain region54(a drift region) maintaining the state after the epitaxy.

In the body region53, an N+-type source region55(having a concentration of 1018to 1021cm−3, for example) is formed generally on the overall region of the side closer to the surface52, while a P+-type body contact region56(having a concentration of 1018to 1021cm−3, for example) is formed on a side (the lower side) closer to the SiC substrate42than the source region55. A large number of such body contact regions56are provided in the form of a matrix.

Source trenches45are formed in the same number as the body contact regions56so that each source trench45passes through each body contact region56, and the latticed gate trench43is formed to surround each body contact region56provided with the source trench45. Thus, the large number of unit cells44functioning as field-effect transistors respectively are formed on the epitaxial layer51. In other words, the body contact region56is formed to surround the corresponding source trench45and the body region53is formed to surround the body contact region56in each unit cell44. A side of the body region53opposite to the side closer to the body contact region56is exposed on the side surfaces of the gate trench43. In the unit cell44, the depth direction of the gate trench43corresponds to a gate length direction, and the peripheral direction of each unit cell44orthogonal to the gate length direction corresponds to a gate width direction.

Both of the source trench45and the gate trench43pass through the body region53from the surface52of the epitaxial layer51to reach the drain region54, and the depths thereof are identical to each other in the second embodiment. The distance D1between side surfaces59and57of the source trench45and the gate trench43is 0.5 to 3 μm, for example. When the distance D1is in this range, increase in resistance (on-resistance) can be suppressed when each unit cell44is turned on, and an electric field applied to the bottom portion of the gate trench43can be relaxed.

The gate trench43is U-shaped in section, such that both end corner portions61of the bottom portion thereof in a direction (a direction opposed to the adjacent unit cell44) orthogonal to the gate width are bent toward the side of the drain region54and the side surfaces57opposed to each other and a bottom surface58are continuous through bent surfaces. The source trench45is also U-shaped in section, such that the side surfaces59opposed to each other and a bottom surface60are continuous through bent surfaces. When the unit cell44is turned off, therefore, the electric field applied to both end corner portions61of the bottom portion of the gate trench43can be dispersed to portions other than both end corner portions61, whereby a portion (an insulating film bottom portion64), described later, of the gate insulating film63located on the bottom surface58can be prevented from dielectric breakdown.

In the drain region54, an implantation active layer62as an implantation layer formed by implantation of a P-type impurity (B (boron), Al (aluminum) or the like, for example) is formed in a portion reaching an intermediate portion of the gate trench43in the thickness direction from the bottom surface58thereof. The implantation active layer62is in the form of a lattice overlapping with the gate trench43in plan view, with a width smaller than the distance between the unit cells44adjacent to each other. According to the second embodiment, the depth of the implantation active layer62is 0.1 to 0.5 μm, for example.

The implantation active layer62is a high-resistance layer having higher resistance than the peripheral regions (the drain region54, for example), and the resistance thereof is several 10 to several 100 kΩ/□, for example. The implantation active layer62has a P-type impurity concentration of 1016to 1021cm−3, for example.

Agate insulating film63is formed on the inner surfaces of the gate trench43, to cover the overall regions thereof. The gate insulating film63consists of an oxide film containing nitrogen, such as a silicon oxynitride film formed by thermal oxidation with gas containing nitride and oxygen, for example. The nitrogen content (the nitrogen concentration) in the gate insulating film63is 0.1 to 10%, for example.

In the gate insulating film63, the thickness T4of the portion (the insulating bottom portion64) located on the bottom surface58of the gate trench43is smaller than the thickness T3of portions (insulating film side portions65) located on the side surfaces57of the gate trench43, and the ratio (thickness T4/thickness T3) of the thickness T4to the thickness T3is 0.3 to 1.0, preferably 0.5 to 1.0. More specifically, the thickness T3is 300 to 1000 Å, and the thickness T4is 150 to 500 Å, for example. If the thickness T3of the insulating film side portions65is in the aforementioned range, the semiconductor device41can be operated with a proper gate-on voltage, and an efficient transistor operation can be achieved.

A gate electrode66is embedded in the gate trench43by filling up the inner side of the gate insulating film63with a polysilicon material doped with an N-type impurity in a high concentration.

An interlayer dielectric film67made of SiO2is laminated on the epitaxial layer51. A contact hole68exposing the surfaces of the source trench45and the source region55of each unit cell44is formed in the interlayer dielectric film67and the gate insulating film63.

A source wire69is formed on the interlayer dielectric film67. The source wire69collectively enters the source trench45of every unit cell44through each contact hole68, and is in contact with the drain region54, the body contact region56and the source region55successively from the bottom side of the source trench45in each unit cell44. In other words, the source wire69is common to all unit cells44. An interlayer dielectric film (not shown) is formed on the source wire69, which in turn is electrically connected to the source pad46(seeFIG.3A) through the interlayer dielectric film (not shown). On the other hand, the gate pad48(seeFIG.3A) is electrically connected to the gate electrode66through a gate wire (not shown) drawn onto the interlayer dielectric film (not shown).

The source wire69has a polysilicon layer70, an intermediate layer71and a metal layer72successively from the side in contact with the epitaxial layer51.

The polysilicon layer70is a doped layer made of doped polysilicon doped with an impurity, such as a high-concentration doped layer doped with the impurity in a high concentration of 1019to 1021cm−3, for example. The impurity for forming the polysilicon layer70as the doped layer (including the high-concentration doped layer) can be prepared from an N-type impurity such as N (nitrogen), P (phosphorus) or As (arsenic) or a P-type impurity such as Al (aluminum) or B (boron). The thickness of the polysilicon layer70is 5000 to 10000 Å, for example.

According to the second embodiment, the polysilicon layer70is formed to cover the overall region of the surface of the unit cell44exposed in the contact hole68, and in contact with the drain region54, the body contact region56and the source region55in the source trench45.

The layer of the source wire69in contact with the drain region54, the body contact region56and the source region55is made of polysilicon, whereby the source wire69can be brought into ohmic contact with both of the body contact region56and the source region55, which are high-concentration impurity regions. On the other hand, a heterojunction having a smaller junction barrier than the diffusion potential of a body diode73(a PN diode formed by junction between the body region53and the drain region54) intrinsic in the semiconductor device41can be formed with respect to the low-concentration drain region54.

When a current flows to the body diode73intrinsic in the semiconductor device41, positive holes (holes) moving from the body region53to the drain region54recombine with electrons in the drain region54, and a defect of an SiC crystal in the epitaxial layer51may spread in the plane due to the resulting recombination energy. The resistance of the crystal defect is so high that the crystal defect may hinder an ordinary transistor operation to increase on-resistance when spreading toward the side of the gate trench43.

When the heterojunction is formed due to the contact between the polysilicon layer70and the drain region54as in the second embodiment, on the other hand, a current can be fed to the side of the heterojunction in preference to the side of the body diode73, even if a reverse voltage is applied between the source and the drain and the current flows to the aforementioned body diode73. Consequently, the crystal defect of SiC can be prevented from spreading, and increase in the on-resistance can be suppressed.

The intermediate layer71, laminated on the polysilicon layer70, is formed by a single layer containing Ti (titanium) or a plurality of layers including the layer. The layer containing Ti can be prepared from Ti, TiN (titanium nitride) or the like. The thickness of the intermediate layer71is 200 to 500 nm, for example.

The metal layer72, laminated on the intermediate layer71, is made of Al (aluminum), Au (gold), Ag (silver), Cu (copper) or Mo (molybdenum), an alloy thereof, or a metal material containing the same, for example. The metal layer72forms the outermost layer of the source wire69. The thickness of the metal layer72is 1 to 5 μm, for example.

More specifically, the polysilicon layer70, the intermediate layer71and the metal layer72may be combined in a multilayer structure (Poly-Si/Ti/TiN/Al) obtained by successively laminating Poly-Si (the polysilicon layer70), Ti (the intermediate layer71), TiN (the intermediate layer71) and Al (the metal layer72).

A drain electrode74is formed on the rear surface50of the SiC substrate42, to cover the overall region thereof. The drain electrode74is common to all unit cells44. The drain electrode74has a multilayer structure (Ti/Al) obtained by laminating Ti and Al successively from the side of the SiC substrate42, for example.

A prescribed voltage (a voltage of not less than a gate threshold voltage) is applied to the gate pad48while a prescribed potential difference is caused between the source pad46(the source wire69) and the drain electrode74(between a source and a drain), whereby a channel is formed in the vicinity of the interface between the body region53and the gate insulating film63due to an electric field from the gate electrode66. Thus, a current flows between the source wire69and the drain wire74, and the VDMOSFET is turned on.

FIGS.5A to5Uare schematic sectional views for illustrating a method of manufacturing the semiconductor device41shown inFIG.4in step order.

First, an SiC crystal is grown on the surface49(the Si surface) of the SiC substrate42by epitaxy such as CVD (Chemical Vapor Deposition), LPE (Liquid Phase Epitaxy) or MBE (Molecular Beam Epitaxy) while doping the same with an impurity, as shown inFIG.5A. Thus, the N−-type epitaxial layer51is formed on the SiC substrate42.

Then, a P-type impurity is implanted into the epitaxial layer51from the surface52thereof, as shown inFIG.5B. While the implantation conditions vary with the type of the P-type impurity, acceleration energy is 200 to 3000 keV, for example.

Then, a mask75made of SiO2is formed on the epitaxial layer51by CVD, as shown inFIG.5C. Then, the mask75is etched through a photoresist film (not shown) into a pattern having an opening76in a region for forming the body contact region56. After the formation of the opening76, a P-type impurity is implanted into the epitaxial layer51from the surface52thereof. While the implantation conditions vary with the type of the P-type impurity, acceleration energy is 30 to 400 keV, for example. After the implantation of the P-type impurity, the mask75is removed.

Then, an N-type impurity is implanted into the epitaxial layer51from the surface52thereof, as shown inFIG.5D. While the implantation conditions vary with the type of the N-type impurity, acceleration energy is 30 to 400 keV, for example.

Then, a mask77made of SiO2is formed on the overall region of the surface52of the epitaxial layer51by CVD or thermal oxidation, as shown inFIG.5E. The mask77may alternatively be made of SiN or the like through CVD. Then, the mask77is etched through a photoresist film (not shown) into a pattern having openings78in regions for forming the gate trench43and the source trench45. After the formation of the openings78, mixed gas (SF6/O2gas) containing SF6(sulfur hexafluoride) and O2(oxygen) or mixed gas (SF6/O2/HBr gas) containing SF6, O2and HBr (hydrogen bromide), for example, is introduced into the surface52of the epitaxial layer51through the openings78. Thus, the epitaxial layer51is dry-etched from the surface52(the Si surface), and the gate trench43and the source trench45are formed at the same time. Further, the large number of unit cells44are formed on the epitaxial layer51.

Then, the inner surfaces of the gate trench43and the source trench45are oxidized by thermal oxidation (dry oxidation) employing O2gas, as shown inFIG.5F. Thus, a stopper film79is formed. While the thickness of the stopper film79may not be entirely uniform,FIGS.5F to5Iillustrate the stopper film79having a uniform thickness, for the purpose of convenience.

Then, a polysilicon material, different from the material (SiO2) for the mask77for forming the gate trench43and the source trench45, is deposited on the epitaxial layer51by CVD to completely fill up the overall regions of the surfaces of the stopper film79and the mask77, as shown inFIG.5G. Thus, a protective mask80is formed on the stopper film79and the mask77. The thickness of the protective mask80is controlled to be 0.1 to 0.5 μm, for example.

Then, the protective mask80is etched back from above the epitaxial layer51, as shown inFIG.5H. The protective mask80is etched back while a portion of the protective mask80located on the bottom surface60of the source trench45is masked, until the etching is stopped by the stopper film79and the mask77. Thus, only a portion of the protective mask80located on the bottom surface58of the gate trench43is removed, while those covering the side surfaces57of the gate trench43and the bottom surface60and the side surfaces59of the source trench45remain.

Then, a P-type impurity is implanted into the epitaxial layer51from the bottom surface58of the gate trench43through the stopper film79, as shown inFIG.5I. While the implantation conditions vary with the type of the P-type impurity, acceleration energy is 30 to 400 keV, for example.

Then, the protective mask80is removed and the mask77as well as the stopper film79are subsequently removed by wet etching, as shown inFIG.5J.

Thereafter an organic material film81is formed on the overall region of the surface52of the epitaxial layer51, as shown inFIG.5K. The organic material film81is made of a material containing carbon, to which an organic material (polyimide or the like, for example) employed as a photoresist material or the like can be applied, for example. The organic material film81is formed with a spin coater or the like, for example.

After the formation of the organic material film81, the SiC substrate42is charged into a resistance heating furnace82. The resistance heating furnace82is not particularly restricted, so far as airtightness in the resistance heating furnace82in which a heated object is set can be ensured and gas can be introduced thereinto. Further, the heating system of the resistance heating furnace82may be either direct heating or indirect heating.

When the SiC substrate42is set in the resistance heating furnace82, inert gas (N2, Ar or the like, for example) is introduced into the resistance heating furnace82, which in turn is subjected to temperature-rise control (first temperature-rise control).

In the first temperature-rise control, the heating temperature is controlled to rise from 100° C. to 1000° C. over 35 to 45 minutes, for example, and thereafter held at 1000° C. (first temperature holding) for 5 to 10 minutes, for example, as shown inFIG.6. Due to the temperature rise and the temperature holding, elements other than carbon evaporate from the organic material film81, which in turn is altered into a carbon film83, as shown inFIG.5L. Therefore, the overall region of the surface52of the epitaxial layer51is covered with the carbon film83.

Then, the resistance heating furnace82is subjected to further temperature-rise control (second temperature-rise control) while the inner portion thereof is kept in the inert atmosphere.

In the second temperature-rise control, the heating temperature is controlled to rise from 1000° C. to 1600° C. over 30 to 60 minutes, for example, as shown inFIG.6. After the temperature rise, the heating temperature is held at 1600° C. (second temperature holding) for 5 to 10 minutes, for example. Due to the temperature rise and the temperature holding, ions of the individual N- and P-type impurities implanted into a surface layer portion of the epitaxial layer51are activated, and the body region53, the source region55and the body contact region56are formed in response to the implanted portions respectively, as shown inFIG.5M. Further, the drain region54maintaining the state after the epitaxy is formed on a base layer portion of the epitaxial layer51.

Then, the resistance heating furnace82is subjected to temperature-drop control while the inner portion thereof is kept in the inert atmosphere.

In the temperature-drop control, the heating temperature is controlled (temperature-drop-controlled) to drop from 1600° C. to 1300° C. over 15 to 30 minutes, for example, as shown inFIG.6. After the temperature drop, nitrogen/oxygen-containing gas is introduced into the resistance heating furnace82for 5 to 10 minutes, for example, while the heating temperature is held at 1300° C. (third temperature holding). Due to the introduction of the nitrogen/oxygen-containing gas, the carbon film83is oxidized and removed by reacting with oxygen contained in the gas, as shown inFIG.5N. The introduced nitrogen/oxygen-containing gas can be prepared from gas containing at least N2O (dinitrogen oxide), and may contain NO (nitrogen monoxide). The N2O gas is fed at a flow rate of not more than 30%, preferably 1 to 30% with respect to the total flow rate of the introduced gas.

Thereafter the heating temperature is further held at 1300° C. (fourth temperature holding) for 200 to 240 minutes, for example, while the nitrogen/oxygen-containing gas is introduced into the resistance heating furnace82at the same flow rate. Thus, the surface52of the epitaxial layer51is oxidized, and a silicon oxynitride film (the gate insulating film63) covering the overall region of the surface52is formed, as shown inFIG.5O.

After the formation of the gate insulating film63, the inert gas (N2, Ar or the like, for example) is reintroduced into the resistance heating furnace82, while the heating temperature is controlled to drop from 1300° C. to 300° C. After the temperature drop, the SiC substrate42is taken out from the resistance heating furnace82.

Then, a doped polysilicon material84is deposited from above the epitaxial layer51by CVD, as shown inFIG.5P. The polysilicon material84is continuously deposited until at least the gate trench43and the source trench45are filled up therewith.

Thereafter the deposited polysilicon material84is etched back until the etched-back surface is flush with the surface52of the epitaxial layer51, as shown inFIG.5Q.

Then, only the portion of the polysilicon material84remaining in the source trench45is removed by dry etching, as shown inFIG.5R. Thus, the gate electrode66is formed by the polysilicon material84remaining in the gate trench43.

Then, the interlayer dielectric film67made of SiO2is laminated on the epitaxial layer51by CVD, as shown inFIG.5S.

Then, the interlayer dielectric film67and the gate insulating film63are continuously patterned, whereby the contact hole68is formed in the interlayer dielectric film67and the gate insulating film63, as shown inFIG.5T.

Then, a polysilicon material is deposited by CVD to fill up the contact hole68, as shown inFIG.5U. Thereafter an N- or P-type impurity is implanted into the deposited polysilicon material. While the implantation conditions vary with the type of the N- or P-type impurity, acceleration energy is 10 to 100 keV, for example. Thereafter the impurity is diffused at a temperature of 900° C. for 20 minutes, for example. Thus, the polysilicon layer70doped with the impurity in a high concentration is formed. Then, Ti and TiN are deposited in this order on the surface of the polysilicon layer70by a method such as sputtering or vapor deposition, and the intermediate layer71is formed. Then, a metal such as Al is deposited on the surface of the intermediate layer71by a method such as sputtering or vapor deposition, and the metal layer72is formed. Thus, the source wire69is formed. Then, the drain electrode74is formed on the rear surface50of the SiC substrate42.

Thereafter the semiconductor device41shown inFIG.4is obtained by forming the interlayer dielectric film (not shown), the source pad46and the gate pad48.

In the semiconductor device41, as hereinabove described, the gate trench43is dug from the surface52(the Si surface) of the epitaxial layer51made of SiC, similarly to the semiconductor device1according to the first embodiment. Therefore, oxidation of the inner surfaces of the gate trench43(seeFIG.5O) progresses under the condition that the oxidation rate for the bottom surface58having the Si surface and that for the side surfaces57orthogonal to the Si surface satisfy the following relational expression:
Oxidation rate for bottom surface 58/oxidation rate for side surface 57<0

In the aforementioned method, the inner surfaces of the gate trench43are oxidized not by thermal oxidation (dry oxidation) employing O2gas or thermal oxidation (wet oxidation) employing H2O (water vapor) gas, but by thermal oxidation employing nitrogen/oxygen-containing gas. Further, the implantation active layer62into which the P-type impurity has been implanted is formed immediately under the bottom surface58of the gate trench43. Therefore, the ratio (oxidation rate for bottom surface58/oxidation rate for side surface57) of the oxidation rate for the bottom surface58to that for the side surfaces57can be increased as compared with a case where the gate insulating film63is formed by dry oxidation or wet oxidation.

In the gate insulating film63formed in the aforementioned manner, the ratio (thickness T4/thickness T3) of the thickness T4of the insulating film bottom portion64to the thickness T3of the insulating film side portions65is in the range of 0.3 to 1.0.

In other words, even if the thickness T4of the insulating film bottom portion64is increased so that dielectric breakdown can be suppressed, excessive increase in the thickness T3of the insulating film side portions65can be suppressed due to the lower limit of 0.3 of the ratio (thickness T4/thickness T3). When the thickness T4of the insulating film bottom portion64is designed to a proper value, on the other hand, the thickness T3of the insulating film side portions65is not excessively reduced, due to the upper limit of 1.0. Consequently, dielectric breakdown of the insulating film bottom portion64can be suppressed while suppressing increase in the thickness T3of the insulating film side portions65by properly designing the thickness T4of the insulating film bottom portion64.

The gate insulating film63consists of the silicon oxynitride film formed by thermal oxidation employing nitrogen-containing gas, whereby channel mobility of the VDMOSFET can be improved.

The implantation active layer62is formed immediately under the gate trench43, whereby an energy barrier formed between the implantation active layer62and the epitaxial layer51can be enlarged. Therefore, a current can be rendered hardly flowable to the implantation active layer62. Consequently, the electric field concentration on the bottom surface58of the gate trench43can be suppressed.

The source trench45is formed at the center of each unit cell44surrounded by the gate trench43, whereby congestion of equipotential lines can be suppressed in the vicinity of both end corner portions61of the gate trench43. Consequently, the electric field applied to both end corner portions61on the bottom portion of the gate trench43can be relaxed, whereby the insulating film bottom portion64can be prevented from dielectric breakdown.

The source trench45may be deeper than the gate trench43, as in a semiconductor device85shown inFIG.7. Thus, the electric field applied to both end corner portions61on the bottom portion of the gate trench43can be further relaxed.

In the semiconductor device41, the source wire69has the polysilicon layer70in the portion in contact with the source region55and the body contact region56, whereby the same can be brought into ohmic contact with both of the body contact region56and the source region55, which are high-concentration impurity regions.

When the semiconductor device41is manufactured, therefore, a step of forming an Ni layer on the surface52of the epitaxial layer51can be omitted dissimilarly to a case where a layer made of only a metal such as Al is directly brought into contact with the impurity regions, and a step of silicifying such an Ni layer can also be omitted. Thus, the surface52of the epitaxial layer51can be prevented from formation of a carbon layer.

Consequently, layer peeling can be suppressed between the source wire69and the epitaxial layer51. Thus, connection reliability of the source wire69can be improved.

Further, the layer (the polysilicon layer70) entering the source trench45to come into contact with the drain region54, the body contact region56and the source region55is made of polysilicon excellent in coverage, whereby coverage of the source wire69can be improved. Consequently, the connection reliability of the source wire69can be further improved.

In addition, the intermediate layer71having the multilayer structure of the Ti layer and the TiN layer is interposed between the polysilicon layer70and the metal layer72. A material containing Ti has excellent adhesiveness with respect to both of a polysilicon material and a metal material. Therefore, adhesiveness between the polysilicon layer70and the metal layer72can be improved. Consequently, the connection reliability of the source wire69can be further improved.

When the metal layer72contains Al, the TiN layer can be utilized as a barrier layer for preventing diffusion of Al from the metal layer72into the silicon layer70, whereby excessive Al can be prevented from diffusing into the polysilicon layer70. Consequently, the impurity concentration in the polysilicon layer70can be stabilized, whereby the resistance of the polysilicon layer70can also be stabilized.

An embodiment related to the invention of a method of manufacturing an SiC semiconductor device through a resistance heating furnace is now described.

FIG.8is a schematic sectional view of a planar gate semiconductor device.

A semiconductor device101has a structure obtained by arranging a plurality of unit cells of a planar gate VDMOSFET in the form of a matrix.FIG.8shows only part of the plurality of unit cells.

The semiconductor device101includes an N+-type SiC substrate102forming the base of the semiconductor device101. An N−-type epitaxial layer103made of SiC (silicon carbide) doped with an N-type impurity in a lower concentration than the SiC substrate102is laminated on a surface121of the SiC substrate102. A surface131of the epitaxial layer103is constituted of a (0001) plane of SiC, for example.

An N−-type drain region104maintaining a state after epitaxy is formed on the epitaxial layer103.

A P-type body region105is formed on a surface layer portion of the epitaxial layer103. A plurality of such body regions105(not shown inFIG.8) are formed at regular intervals to parallelly extend in the same direction (a direction perpendicular to the plane ofFIG.8), and arranged in a striped manner or in the form of a matrix, for example. The drain region104is exposed between two body regions105adjacent to each other.

On a surface layer portion of the body region105, an N+-type source region106is formed at an interval from the peripheral edge thereof.

A gate insulating film107extending over the drain region104, the body region105and the source region106is formed on the surface131of the epitaxial layer103. The gate insulating film107is made of SiO2.

A gate electrode108made of polysilicon doped with an N-type impurity in a high concentration is formed on the gate insulating film107. The gate electrode108is opposed to the drain region104, the body region105and the source region106through the gate insulating film107.

An interlayer dielectric film109made of SiO2is laminated on the epitaxial layer103. A source wire111is formed on the interlayer dielectric film109. The source wire111is electrically connected to the body region105and the source region106through a contact hole110formed in the interlayer dielectric film109.

A gate wire112is electrically connected to the gate electrode108through a contact hole (not shown) formed in the interlayer dielectric film109.

A drain electrode113is formed on the rear surface of the SiC substrate102.

When the source wire111is grounded and the potential of the gate electrode108is controlled while applying a positive voltage of a proper level to the drain electrode113, a channel can be formed in the vicinity of the interface between the body region105and the gate insulating film107due to an electric field from the gate electrode108. Thus, a current can be fed between the source wire111and the drain electrode113.

FIGS.9A to9Lare schematic sectional views for illustrating a method of manufacturing the semiconductor device101shown inFIG.8in step order.

First, the epitaxial layer103is formed on the surface121of the SiC substrate102by epitaxy, as shown inFIG.9A. At this time, a major growth surface (the surface121) of the SiC substrate102is defined by a (0001) plane. Due to the surface121of the SiC substrate102defined by the (0001) plane, the epitaxial layer103formed on the SiC substrate102by epitaxy is grown also with a major surface defined by a (0001) plane. Therefore, the surface131of the epitaxial layer103parallel to the surface121of the SiC substrate102is defined by the (0001) plane.

Then, a photoresist film114having an opening115in a portion opposed to a region for forming the body region105is formed on the surface131of the epitaxial layer103by well-known photolithography. Then, ions (boron ions, for example) of a P-type impurity are introduced into the surface131of the epitaxial layer103from above the photoresist film114. Thus, the P-type impurity is implanted into surface layer portions of portions of the epitaxial layer103exposed from the opening115, as shown inFIG.9B.

Then, a photoresist film116having an opening117in a portion opposed to a region for forming the source region106is formed on the surface131of the epitaxial layer103by well-known photolithography. Then, ions (arsenic ions, for example) of an N-type impurity are introduced into the surface131of the epitaxial layer103from above the photoresist film116. Thus, the N-type impurity is implanted into a surface layer portion (closer to the surface131than the portions into which the P-type impurity has been implanted) of a portion of the epitaxial layer103exposed from the opening117, as shown inFIG.9C.

After the implantation of the impurity ions into the surface layer portion of the epitaxial layer103, an organic material film118is formed on the overall region of the surface131of the epitaxial layer103, as shown inFIG.9D. The organic material film118is made of a material containing carbon, to which an organic material (polyimide or the like, for example) employed as a photoresist material or the like can be applied, for example. The organic material film118is formed with a spin coater or the like, for example.

After the formation of the organic material film118, the SiC substrate102is charged into a resistance heating furnace122. The resistance heating furnace122is not particularly restricted, so far as airtightness in the resistance heating furnace122in which a heated object is set can be ensured and gas can be introduced thereinto. Further, the heating system of the resistance heating furnace122may be either direct heating or indirect heating.

When the SiC substrate102is set in the resistance heating furnace122, inert gas (N2, Ar or the like, for example) is introduced into the resistance heating furnace122, which in turn is subjected to temperature-rise control (first temperature-rise control).

In the first temperature-rise control, the heating temperature is controlled to rise from 100° C. to 1000° C. over 35 to 45 minutes, for example, and thereafter held at 1000° C. (first temperature holding) for 5 to 10 minutes, for example, as shown inFIG.6. Due to the temperature rise and the temperature holding, elements other than carbon evaporate from the organic material film118, which in turn is altered into a carbon film119, as shown inFIG.9E. Therefore, the overall region of the surface131of the epitaxial layer103is covered with the carbon film119.

Then, the resistance heating furnace122is subjected to further temperature-rise control (second temperature-rise control) while the inner portion thereof is kept in the inert atmosphere.

In the second temperature-rise control, the heating temperature is controlled to rise from 1000° C. to 1600° C. over 30 to 60 minutes, for example, as shown inFIG.6. After the temperature rise, the heating temperature is held at 1600° C. (second temperature holding) for 5 to 10 minutes, for example. Due to the temperature rise and the temperature holding, ions of the N- and P-type impurities implanted into the surface layer portion of the epitaxial layer103are activated, and the body region105and the source region106are formed on the surface layer portion of the epitaxial layer103, as shown inFIG.9F. Further, the drain region104isolated from the body region105while maintaining the state after the epitaxy is formed on a base layer portion of the epitaxial layer103.

Then, the resistance heating furnace122is subjected to temperature-drop control while the inner portion thereof is kept in the inert atmosphere.

In the temperature-drop control, the heating temperature is controlled (temperature-drop-controlled) to drop from 1600° C. to 1300° C. over 15 to 30 minutes, for example, as shown inFIG.6. After the temperature drop, oxygen-containing gas is introduced into the resistance heating furnace122for 5 to 10 minutes, for example, while holding the heating temperature at 1300° C. (third temperature holding). Due to the introduction of the oxygen-containing gas, the carbon film119is oxidized and removed by reacting with oxygen contained in the oxygen-containing gas, as shown inFIG.9G. The oxygen-containing gas introduced into the resistance heating furnace122is preferably prepared from gas containing oxygen and nitrogen. More specifically, gas containing NO (nitrogen monoxide) or N2O (dinitrogen oxide) can be employed.

Thereafter the heating temperature is further held at 1300° C. (fourth temperature holding) for 200 to 240 minutes, for example, while the oxygen-containing gas is introduced into the resistance heating furnace122. Thus, the surface131of the epitaxial layer103is oxidized, and an oxide film120covering the overall region of the surface131is formed, as shown inFIG.9H.

After the formation of the oxide film120, the inert gas (N2, Ar or the like, for example) is reintroduced into the resistance heating furnace122, while the heating temperature is controlled to drop from 1300° C. to 300° C. After the temperature drop, the SiC substrate102is taken out from the resistance heating furnace122.

Then, a conductive material film is formed by sputtering. Then, the conductive material film is patterned by well-known photolithography and etching, and the gate electrode108is formed on the oxide film120, as shown inFIG.9I.

Thereafter the interlayer dielectric film109is laminated on the epitaxial layer103by CVD (Chemical Vapor Deposition), as shown inFIG.9J.

Then, the contact hole110is formed in the interlayer dielectric film109and the oxide film120by well-known photolithography and etching, as shown inFIG.9K. The remaining portion of the oxide film120forms the gate insulating film107.

Then, a film of a conductive material is formed on the epitaxial layer103by sputtering. The conductive material is bonded (deposited) to fill up the contact hole110and form a thin film on the interlayer dielectric film109. Then, the conductive material film formed on the interlayer dielectric film109is patterned by well-known photolithography and etching. Thus, the source wire111is formed, as shown inFIG.9L. Further, the gate wire112electrically connected with the gate electrode108is formed. In addition, the drain electrode113is formed on the rear surface of the SiC substrate102.

The semiconductor device101shown inFIG.8is obtained through the aforementioned steps.

According to the aforementioned method, the organic material film118is heated in the resistance heating furnace122by the first temperature-rise control after the formation of the organic material film118to be altered into the carbon film119, which is formed on the surface131of the epitaxial layer103.

After the formation of the carbon film119, the epitaxial layer103is heated due to the second temperature-rise control in the resistance heating furnace122while the inner portion thereof is kept in the inert atmosphere, thereby activating the ions of the N- and P-type impurities in the epitaxial layer103.

Then, the temperature-drop control (temperature drop from 1600° C. to 1300° C., for example) is executed while maintaining the resistance heating furnace122in the inert state. Thereafter the oxygen-containing gas is introduced for 5 to 10 minutes, for example, while the heating temperature is held at 1300° C. (the third temperature holding). Thus, the carbon film119is oxidized and removed, and the surface131of the epitaxial layer103is exposed.

After the removal of the carbon film119, the resistance heating furnace122is subjected to the temperature holding (the fourth temperature holding) while the oxygen-containing gas is continuously introduced thereinto, whereby the exposed surface131is oxidized and the oxide film120is formed.

The carbon film119is formed on the surface131of the epitaxial layer103in advance of the heating (the second temperature-rise control) for activating the ions, whereby Si escape from the surface131can be prevented when the epitaxial layer103is heated. Therefore, roughening of the surface131of the epitaxial layer103can be suppressed, and planarity of the surface131can be maintained. Consequently, the interface between the epitaxial layer103and the gate insulating film107can be smoothed, whereby channel mobility of the semiconductor device101can be improved.

Further, the four steps of altering the organic material film118into the carbon film119by heating the same (the first temperature-rise control), activating the ions by heating the epitaxial layer103(the second temperature-rise control), oxidizing and removing the carbon film119with the oxygen-containing gas (the temperature-drop control and the third temperature holding) and forming the oxide film120by oxidizing the surface131of the epitaxial layer103(the fourth temperature holding) can be continuously carried out in the single resistance heating furnace122. No apparatus for removing the carbon film119or the like is additionally required, whereby increase in the device cost can also be suppressed. Further, the resistance heating furnace122is so employed that the first temperature-rise control, the second temperature-rise control, the temperature-drop control as well as the third temperature holding, and the fourth temperature holding can be precisely and simply executed.

In addition, the surface131of the epitaxial layer103on which the oxide film120is formed is defined by the (0001) plane, and the oxygen-containing gas introduced into the resistance heating furnace122is prepared from the gas containing oxygen and nitrogen.

When oxide films are formed by oxidizing (0001) planes of SiC layers with O2gas, H2O gas (water vapor) and N2O gas respectively, for example, MOSFETS including the SiC layers exhibit channel mobility values of 1 to 5 cm2/V·s, 5 to 15 cm2/V·s and 15 to 25 cm2/V·s respectively, for example. In other words, the MOSFET including the SiC layer having the oxide film formed with the N2O gas is most excellent in channel mobility.

In the semiconductor device101according to the embodiment, the oxide film120is formed by oxidizing the (0001) plane (the surface131) of the epitaxial layer103with NO gas or N2O gas, whereby the channel mobility of the semiconductor device101can be further improved.

EXAMPLES

While the present invention is now described with reference to Example and comparative examples, the present invention is not restricted by the following Examples.

Example 1 (N2O Oxidation)

First, an epitaxial layer made of SiC was formed by growing an SiC crystal on an Si surface of a wafer-shaped SiC substrate (by Cree Inc.) while doping the same with an N-type impurity. Then, a trench was formed by forming an SiO2mask of a prescribed pattern on the surface (an Si surface) of the epitaxial layer and introducing SF6/O2gas into the surface of the epitaxial layer through the SiO2mask.

Then, the SiC substrate was introduced into a diffusion furnace, and N2O gas was fed for 3 hours while heating the diffusion furnace to 1275° C. Thus, an oxide film was formed by oxidizing the inner surface of the trench.

Other oxide films were formed similarly to the above, by setting the times (oxidation times) for feeding N2O gas to 8 hours and 12 hours respectively.

Comparative Example 1 (Dry Oxidation)

Steps similar to those in Example 1 were carried out up to a step of forming a trench. After the formation of the trench, an SiC substrate was introduced into a diffusion furnace, and O2gas was fed for 4 hours while heating the diffusion furnace to 1150° C. Thus, an oxide film was formed by oxidizing the inner surface of the trench.

Other oxide films were formed similarly to the above, by setting the times (oxidation times) for feeding O2gas to 6 hours and 8 hours respectively.

Comparative Example 2 (Wet Oxidation)

Steps similar to those in Example 1 were carried out up to a step of forming a trench. After the formation of the trench, an SiC substrate was introduced into a diffusion furnace, and water vapor (H2O gas) was fed for 15 minutes while heating the diffusion furnace to 1275° C. Thus, an oxide film was formed by oxidizing the inner surface of the trench.

Other oxide films were formed similarly to the above, by setting the times (oxidation times) for feeding H2O gas to 25 minutes and 35 minutes respectively.

1) Measurement of Thickness of Oxide Film

The thicknesses of the oxide films formed according to Example 1 and comparative examples 1 and 2 were measured on portions located on the side surfaces of the trenches and those located on the bottom surfaces of the trenches.FIGS.10A,10B and10Cshow the results of Example 1 and comparative examples 1 and 2 respectively.

2) Thickness Ratio of Oxide Film

The ratios (bottom surface/side surface) of the thicknesses of the portions of the oxide films located on the bottom surfaces to those of the portions located on the side surfaces were calculated through the thicknesses of the oxide films shown inFIGS.10A to10Crespectively.FIGS.10A to10Calso show the results.

Referring toFIG.10A, it has been confirmed that the ratios (bottom surface/side surface) of the thicknesses of the portions of the oxide films located on the bottom surfaces to those of the portions located on the side surfaces were about 0.54 (feeding time: 3 hours), 0.46 (feeding time: 8 hours) and 0.48 (feeding time: 12 hours) respectively.

Referring toFIG.10B, it has been confirmed that the ratios (bottom surface/side surface) of the thicknesses of the portions of the oxide films located on the bottom surfaces to those of the portions located on the side surfaces were about 0.20 (feeding time: 4 hours), 0.20 (feeding time: 6 hours) and 0.19 (feeding time: 8 hours) respectively.

Referring toFIG.10C, it has been confirmed that the ratios (bottom surface/side surface) of the thicknesses of the portions of the oxide films located on the bottom surfaces to those of the portions located on the side surfaces were about 0.23 (feeding time: 15 minutes), 0.21 (feeding time: 25 minutes) and 0.22 (feeding time: 35 minutes) respectively.

While the embodiments of the present invention have been described, the present invention may be embodied in other ways.

For example, the conductivity types of the semiconductor portions of the semiconductor device1,41or85may be reversed. In other words, the P-type portions may be replaced with N-type portions and vice versa in the semiconductor device1,41or85.

Each of the source wire17or69and the drain wire23(the drain electrode74) may have a multilayer structure formed by a layer prepared by silicifying nickel (Ni) or titanium (Ti) and the aforementioned metal layer.

While the present invention has been described in detail by way of the embodiments thereof, it should be understood that these embodiments are merely illustrative of the technical principles of the present invention but not limitative of the invention. The spirit and scope of the present invention are to be limited only by the appended claims.