Patent ID: 12190943

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

A mixed transistor type SRAM bit cell having a reduced coupling capacitance is provided. In a vertical direction, a wordline “WL” and a bitline “BL” of the SRAM cell are stacked further away from one another to reduce the coupling capacitance between the WL and the BL. In an embodiment, one of the BL or the WL, e.g., the WL, is vertically spaced apart from the other one of the BL or the WL, e.g., the BL, with one or more metallization level that none of the WL or the BL is formed from. That is, the metallization level of the WL, referred to as “WL metal level” for descriptive purposes, and the metallization level of the BL, referred to as “BL metal level” for descriptive purposes, are vertically spaced apart from one another by at least one additional metallization level in-between. In an embodiment, one or more metal island structures, referred to as “jumper structures,” are formed within the additional metallization level and are connected to the upper one of the WL or the BL. The jumper structures each do not overlap with the lower one of the WL or the BL, such that the coupling capacitance between a jumper structure and the lower one of the WL or the BL is minimized, if any. The distance between the WL and the BL is substantially increased so that the coupling capacitance between the WL and the BL is substantially reduced. To this extent, the width of the WL may be increased to lower the resistance. The size of the jumper structures are optimally configured to maintain a determined balance between minimizing coupling capacitance and minimizing resistance in the connection path between the WL and the gates of the transistors that is connected to the WL.

FIG.1is an example SRAM bit cell100in a six transistor (“6T”) arrangement. InFIG.1, a pair of MOS pass gates PG1and PG2are each coupled to one of a pair of data lines referred to as “bitlines” BL1, BL2to inversely related storage nodes SN1and SN2, respectively. In an embodiment, the pass gate transistors PG1and PG2are formed of NMOS transistors. A first voltage node Vddmay provide a voltage ranging from about 0.6 Volts to about 3.0 Volts, depending on the technology node. Pull up transistors PU1, PU2are each formed of PMOS transistors and coupled between the first supply node Vddand one of the storage nodes SN1, SN2, depending on the state of the SRAM cell100.

A second voltage Vssmay provide a voltage potential lower than the first voltage node Vdd, e.g., set as a ground. Two pull down transistors PD1, PD2are each formed of NMOS transistors, and are coupled between the second voltage node Vssand one of the storage nodes SN1, SN2, depending on the state of the SRAM cell100. The 6T SRAM bit cell100is a latch that will retain its data state indefinitely so long as the supplied power Vddis sufficient to operate the circuit correctly. Two CMOS inverters formed of PU1, PD1and PU2, PD2are “cross coupled” and they operate to reinforce the stored charge on the storage nodes SN1, SN2continuously. The two storage nodes SN1, SN2are inverted from one another, as shown inFIG.1. When the SN1is at a high voltage level, e.g., logical “1”, the SN2is at a low voltage level, e.g., logical “0”, and vice versa.

When the SRAM bit cell100is written to, complementary write data signals are placed on the bitline pair BL1and BL2. A positive control signal on a wordline WL is coupled to the gate of the pass gates PG1, PG2. The transistors PU1, PD1and PU2, PD2are sized in a manner that the data on the bitlines BL1, BL2may overwrite the stored data and thus write, or program, the SRAM bit cell100.

When the SRAM bit cell100is read from, a positive voltage is placed on the wordline WL, and the pass gates PG1and PG2allow the bitlines BL1and BL2to be coupled to receive the data from the storage nodes SN1and SN2, respectively. Unlike a dynamic memory cell, the SRAM bit cell100does not lose its stored state during a read operation if the power supply Vddis maintained at a sufficiently high level.

FIG.2is an example bit cell layout, in an X-Y plane, of the single port, 6T bit cell100. InFIG.2, the dashed areas depict the gate structures. The gate structures are positioned over semiconductor areas/structures210. The transistors PG-1, PG-2, PU-1, PU-2, PD-1, and PD-2are labeled at their respective gate structures. The cell100has a pitch labeled Y1-pitch in the Y direction and a pitch labeled X1-pitch in the X direction. Example contacts are shown with “X” for illustration purposes and are labeled with the appropriate signal. Wordline WL contacts are formed to the gates of the PG-1, PG-2transistors. Bitline contacts are formed to the source/drain terminals of the PG-1, PG-2transistors. Power Vdd, Vsscontacts are formed to the source/drain terminals of the PU-1, PU-2, PD-1, PD-2transistors. Storage node contacts are formed to the storage nodes SN1and SN2, respectively. The pull-up transistors PU-1, PU-2are different types of transistors than the pull-down transistors PD-1, PD-2. In an example embodiment, as shown inFIG.2, the pull-up transistors PU-1, PU-2are formed in a doped region, e.g., an N type well220, within a P type substrate230, where the pull-down transistors are formed in. Other example embodiments, e.g., a dual-well configuration, are also possible and within the scope of the disclosure.

In an embodiment, the semiconductor structures210are fin-shaped semiconductor structures and gate structures each wrap around the respective fin-shaped semiconductor structures210.

FIG.3A-3Cshow a structure300including the example bit cell100and metal lines of the wordline WL and the bitlines BL1, BL2, the first power supply Vdd, and the second power supply Vss.FIG.3Ais a layout view in the X-Y plane.FIG.3Bis a cross-sectional view of the metallization levels of the structure300from cutting line BB.FIG.3Cis a cross-sectional view of the metallization levels of the structure300from cutting line CC.

As shown inFIGS.3A-3C, the bitlines BL1, BL2are metal lines formed as a part of a lower level metallization, referred to as “M0” for descriptive purposes, within a lower level inter-layer dielectric “ILD” layer ILD0. The BL1, BL2metal lines may be longitudinal and are oriented along the y-axis direction in the X-Y plane.

The wordline WL is a metal line formed as a part of an upper level metallization M3, within an upper level ILD, ILD3. The WL metal line may be longitudinal and is oriented along the x-axis direction that is orthogonal to the y-axis direction.

There are at least one inter-layer dielectric layers, shown as two ILD1, ILD2, positioned vertically between the ILD0and the ILD3. The ILD0is also referred to as BL level for descriptive purposes, and the ILD3is also referred to as WL level for descriptive purposes. The ILD2, ILD1that are positioned vertically between the BL level ILD0and the WL level ILD3are also referred to as “jumper ILD” for descriptive purposes. In some embodiments, the jumper ILD layers are added to increase the distance between the wordline WL and the bitlines BL1, BL2. The numerals “0” is used as an example to indicate a lower level of ILD and a lower level of metallization, with respect to ILD3or metallization level M3. That is, the ILD0is two levels below the ILD3. “ILD0” does not necessarily indicate that the ILD is the first ILD level formed in the BEOL process or that the ILD is any specific ILD level formed in the BEOL process. Similarly, “M0” does not necessarily indicate that the metallization level is the first metallization level formed in the BEOL process or that the metallization is any specific metallization level formed in the BEOL process.

The gates of the transistors PG-1, PG-2(not shown inFIG.3B) are each connected to the WL through a series of interconnection features (referred to as ‘interconnection assembly”)310-1,310-2, respectively. The interconnection assembly310-1includes one or more jumper structures322, shown as322(1),322(2) formed in jumper ILD layers ILD1, ILD2, respectively. The interconnection assembly310-2includes one or more jumper structures320, shown as jumper structures320(1),320(2) formed in jumper ILD layers ILD1, ILD2, respectively. In an embodiment, each of the jumper structures320,322does not vertically overlap with the adjacent bitlines BL1, BL2. Specifically, for example, the jumper structures320(1),320(2) each is spaced away from the BL2, in the x-axis, by a gap space324(1),324(2). The gap spaces324(1),324(2) ensure that the coupling capacitance, if any, between the jumper structures320(1),320(2) to the bitline BL2is minimized or reduced.

As such, in an embodiment, the dimensions of each jumper structures320,322in the x-axis direction are minimized subject to the minimum area rule defined by the process design. For example, the minimum area rule provides that the x-axis dimension of a jumper structure320,322be sufficiently large to ensure contact or connection with a respective connection via. In an embodiment, the x-axis dimension of a jumper structure320,322may be designed based on a vertical distance between the jumper structure320,322and the adjacent bitline BL1, BL2. Specifically, a jumper structure320,322that is positioned vertically further away from the bitline BL1, BL2, may include a larger x-axis dimension than a jumper structure320,322that is positioned vertically closer to the bitline BL1, BL2. For example, the jumper structure320(2) formed as part of the M2metallization in the ILD2layer may include a larger x-axis dimension than the jumper structure320(1) formed as part of the M1metallization in the ILD1layer, because the jumper structure320(2) is vertically further away from the adjacent bitline BL2. The longer distance may compensate, at least to some extent, for the increased x-axis dimension of the jumper structure320(2), as compared to the jumper structure320(1).

In an embodiment, the dimensions of each jumper structures320,322in the y-axis direction are minimized subject to the minimum area rule defined by the process design. For example, the minimum area rule provides that the y-axis dimension of a jumper structure320,322be sufficiently large to ensure contact or connection with a respective connection via. In an embodiment, the y-axis dimension of a jumper structure320,322may be designed based on a vertical distance between the jumper structure320,322and the adjacent bitline BL1, BL2. Specifically, a jumper structure320,322that is positioned vertically further away from the bitline BL1, BL2, may include a larger y-axis dimension than a jumper structure320,322that is positioned vertically closer to the bitline BL1, BL2. For example, the jumper structure320(2) formed as part of the M2metallization in the ILD2layer may include a larger y-axis dimension than the jumper structure320(1) formed as part of the M1metallization in the ILD1layer, because the jumper structure320(2) is vertically further away from the adjacent bitline BL2. The longer distance may compensate, at least to some extent, for the increased y-axis dimension of the jumper structure320(2), as compared to the jumper structure320(1).

In the example embodiment, the bitlines BL1, BL2are longitudinal and oriented along the y-axis direction. That is, the increase in the y-axis dimension will not affect whether a jumper structure320,322vertically overlaps with the adjacent bitline BL1, BL2. As such, in some embodiment, the y-axis dimension of a jumper structure320,322is more flexibly designed as compared to the x-axis dimension thereof.

It should be noted that the surface area of a jumper structure320,322may not be a rectangular shape, and may include a circular shape, an oval shape, another polygonal shape or an irregular shape. The above description of the x-axis dimension and/or the y-axis dimension of a jumper structure320,322may also be similarly applied to such non-rectangular shapes.

Further, the description herein about the x-axis or y-axis dimensions of a jumper structure320,322may similarly apply to a size of a surface area of a jumper structure320,322. For example, a size of a surface area of a jumper structure320,322, in the X-Y plane, may be designed based on a vertical distance between the jumper structure320,322and the adjacent bitline BL1, BL2. A jumper structure320,322that is positioned further away from a bitline BL1, BL2may include a larger surface area than a jumper structure320,322that is positioned closer to the bitline BL1, BL2. For example, the jumper structure320(2) may include a larger surface area than the jumper structure320(1) because the jumper structure320(2) is positioned vertically further away from the adjacent bitline BL2.

The WL is connected to a connection island structure330as part of the M0metallization in the ILD0layer through the jumper structures320,322and via structures340, here340(1),340(2),340(3) formed in dielectric layers ILD1, ILD2, ILD3, respectively. The descriptions about the dimension sizes and/or surface area sizes of the jumper structures320,322also apply similarly to the connection via structures340.FIG.3shows that the jumper structures are larger in the x-axis and y-axis dimensions than the adjacent connection via structures, which does not limit the scope of the disclosure. In some embodiment, a connection via340may include one of more of a larger x-axis dimension, a larger y-axis dimension or a larger X-Y plane surface area than an adjacent jumper structure320,322.

FIGS.4A-4Bshow an alternative embodiment.FIG.4Ais an X-Y plane view.FIG.4Bis an Y-Z sectional view. As shown inFIGS.4A and4B, a wide W2of the WL is larger than the W1of the WL ofFIGS.3A-3C. The larger width W2of the embodiment shown inFIGS.4A and4Bis enabled by the reduced coupling capacitance between the wordline WL and the bitlines BL1, BL2. The X-Y plane surface areas of the jumper structures420(2),420(1) and the island structure430increase along the upward direction of the z-axis. Specifically, the X-Y plane surface area of the jumper structure420(2) is larger than the X-Y plane surface area of the jumper structure420(1). The X-Y plane surface area of the jumper structure420(1) is larger than the X-Y plane surface area of the island structure430. In an embodiment, the surface area ratios among the island structure430, the jumper structure420(1), and the jumper structure420(2) are between about 1:1.1:1.15 to about 1:1.3:1.4. In an embodiment, the jumper structures420(1),420(2) include substantially a same dimension in the x-axis to avoid overlapping with the adjacent bitline BL2, while the jumper structure420(2) includes a larger dimension in the y-axis than the jumper structure420(1). That is, the surface area ratios between or among the island structure430, the jumper structure420(1), and the jumper structure420(2) mainly attribute to the variations in the y-axis dimensions thereof.

In an embodiment, none of the jumper structure420(420(1),420(2) shown),422(422(1),422(2) shown) ofFIGS.4A,4Boverlaps vertically with the adjacent bitline BL2, BL1, respectively. The surface e area of the jumper structure420(1) that is positioned in the ILD1immediately over the M1metallization of the bitlines BL1, BL2is designed to have minimized X-Y plane surface area subject to minimum area design rules like the via enclosure rule and the minimum area rule for the jumper structure.

Similar to the surface areas, the x-axis or y-axis dimensions of the of the island structure430, the jumper structure420(1), and the jumper structure420(2) may also increase along upward direction of the z-axis. Specifically, the x-axis dimension of the jumper structure420(2) is larger than the x-axis dimension of the jumper structure420(1). The x-axis dimension of the jumper structure420(1) is larger than the x-axis dimension of the island structure430. Specifically, the y-axis dimension of the jumper structure420(2) is larger than the y-axis dimension of the jumper structure420(1). The y-axis dimension of the jumper structure420(1) is larger than the y-axis dimension of the island structure430.

The metallization levels M0, M1, M2, M3may be one or more of copper, gold, silver, aluminum, cobalt, tungsten or other suitable conductive materials. The ILD layers ILD0, ILD1, ILD2, ILD3are silicon oxide, silicon nitride, low-k dielectric materials, or other suitable dielectric materials.

The wordline WL is vertically spaced away from the bitlines BL1, BL2by at least one jumper ILD layer that none of the WL or the BL1, BL2are formed within. As such the coupling capacitances between the WL and the BL1, BL2are reduced. The width or the surface area of wordline WL may be increased to reduce signal line resistance. The surface areas of the jumper structures may be balanced between reducing coupling capacitance between the jumper structures and the adjacent bitline and reducing interconnection line resistance. A jumper structure positioned vertically closer to the adjacent bitline may include a minimized dimension and surface area while a jumper structure positioned vertically further away from the adjacent bitline may include a larger dimension and/or surface area. As such, the coupling capacitance and the signal line resistance may be optimized in a balancing manner. The signal transmittal delay time could be reduced substantially.

In the description herein, for simplicity purposes, the dielectric layer surrounding each metallization levels M1, M2, M3and the dielectric layer surrounding the respective interconnect structures340(1),340(2),340(3) formed immediately below the respective metallization levels M1, M2, M3are described as one ILD layer. Specifically, for example, ILD1surrounds both the M1level including the jumper structure320(1) and the via structure340(1); ILD2surrounds both the M2level including the jumper structure320(2) and the via structure340(2); and ILD3surrounds both the M3level including the wordline WL and the via structure340(3). It should be appreciated that depending on the specific process of forming the via structures340(1),340(2),340(3), the dielectric layer surrounding a via structure340(1),340(2),340(3) may be separate from a dielectric layer surrounding the metallization level M1, M2, M3that is formed immediately above the respective via structures340(1),340(2),340(3). That is, each of the ILD1, ILD2, ILD3in the description herein may include two or more dielectric layers.

In the description ofFIGS.1-4B, a 6T SRAM cell is used as an illustrative example. The disclosed techniques are not limited to 6T SRAM and may include other SRAM cell design and/or other types of memory cells. For example,FIG.5is an example 8T SRAM design. Referring toFIG.5, an 8T SRAM cell500includes a first pull-up transistor PU1and a first pull-down transistor PD1forming a first inverter INV1, a second pull-up transistor PU2and a second pull-down transistor PD2forming a second inverter INV2. The first inverter INV1and the second inverter INV2are cross-coupled to one another and are coupled to write bitlines WBL, WBLB, through first and second pass-gate transistors PG1and PG2, configured to write data to be stored by the cross-coupled first and second inverters INV1and INV2, respectively. A read pull-down transistor RPD and a read pass-gate transistor RPG forms a read port RP to access data stored by the cross-coupled first and second inverters INV1and INV2.

Specifically, drain electrodes of the first pull-up transistor PU1, the first pull-down transistor PD1, and the first pass-gate transistor PG1are electrically connected at a first data storage node ND11. Drain electrodes of the second pull-up transistor PU2, the second pull-down transistor PD2, and the second pass-gate transistor PG2are electrically connected at a second data storage node ND12.

Gate electrodes of the second pull-up transistor PU2and the second pull-down transistor PD2are electrically connected to the drain electrodes of the first pull-down transistor PD1, the first pass-gate transistor PG1, and the first pull-up transistor PU1through the first data storage node ND11, while gate electrodes of the first pull-up transistor PU1and the first pull-down transistor PD1are electrically connected to the drain electrodes of the second pull-down transistor PD2, the second pass-gate transistor PG2, and the second pull-up transistor PU2through the second data storage node ND12.

Source electrodes of the first and second pull-down transistors PD1and PD2are connected to a first power supply node Vss, while source electrodes of the first and second pull-up transistors PU1and PU2are connected to a second power supply node Vdd. According to one embodiment, the first power supply node Vss is electrically connected to a ground, and the second power supply node Vdd is electrically connected to a positive electrical potential, supplied from a power supply circuit (not shown) of the SRAM.

Gate electrodes of the first and second pass-gate transistors PG1and PG2are connected to a write wordline WWL. Source electrodes of the first and second pass-gate transistors PG1and PG2are connected to first and second write bitlines WBL and WBLB, respectively.

The read pass-gate transistor RPG and the read pull-down transistor RPD are connected in series between a read bitline RBL and the first power supply node Vss. The read pull-down transistor RPD has a gate electrode electrically connected to the second data storage node ND12. A gate electrode of the read pass-gate transistor RPG is connected to a read wordline RWL configured to control reading of the data stored by the cross-coupled first and second inverters INV1and INV2by way of the conduction state of the read pull-down transistor RPD to the read bitline RBL.

The wordlines WL and the paired bitlines BL1, BL2are vertically spaced apart by at least one jumper ILD layer other than the ILD layer ILD3of the wordline or ILD layer ILD0of the paired bitline. For example, the write wordline WWL may be formed on metallization level M3ofFIG.3while the first and second write bitlines WBL, WBLB are formed on the metallization level M0that is separated from the metallization level M3by two metallization levels M1, M2. The read wordline RWL is also formed in a metallization level at least two levels away from a metallization level of the read bitline RBL. That is, there is at least one additional metallization level vertically positioned between the metallization level of the RWL and the metallization level of RBL.

FIG.6is an example process of making among others.FIGS.7-11show a wafer700in various stages of fabrication under the example process ofFIG.6.

Referring toFIG.6, with reference also toFIG.7, in example operation610, a wafer700is received. The wafer700includes a substrate702and an FEOL layer704formed over the substrate702. In some embodiments, the FEOL layer704includes the transistors of an SRAM cell, e.g., the 6T SRAM cell ofFIG.1or the 8T SRAM cell ofFIG.5. In an embodiment, the wafer700has completed the front-end-of-line device fabrication process which forms transistors over the substrate702.

The wafer700may also have completed the middle-end-of-line process, which forms the pre-metal dielectric layer (“PMD”) and the contact structures, e.g., vias, that directly contacts the terminals of transistors, e.g., the gates and the source/drain structures of FET transistors.

In example operation620, with reference also toFIG.8, a lower level metallization820is formed over the wafer700. The lower level metallization820may include a bit line structure822and a connection island structure824. The bit line structure822and the island824may each connect to a respective interconnect structure, e.g., a via, to connect to respective terminals of the transistors in the IC block704, which are omitted for simplicity purposes. For example, the bitline structure822is ultimately connected to a source/drain terminal of a transistor and the island824is ultimately connected to a gate of the same transistor. The lower level metallization820may be the first metallization level formed over the pre-metal dielectric layer “PMD” or may be any metallization level over the first metallization level. The metallization level820is formed in a dielectric layer826.

In example operation630, with reference also toFIG.9, a first intermediate metallization level930is formed over the dielectric layer826and the metallization level820. The metallization level930includes a jumper structure932. The jumper structure932is connected to the island structure824through an interconnect structure934. The jumper structure932and the interconnect structure934are formed in a dielectric layer936. The jumper structure932and the interconnect structure934each do not overlap with the bitline structure822in the vertical direction, here the z-axis direction. The dielectric layer936may be formed by a thin film process, e.g., a CVD or a PVD process or other suitable thin film process. The metallization level930may be blankly formed over a wafer surface and then patterned to obtain the jumper structure932. The jumper structure932may also be formed using other metal deposition and patterning processes like a damascene process or a lift-off process. The interconnect structure934is a metal structure formed using a damascene process or a lift-off process.

In example operation640, with reference also toFIG.10, a second intermediate metallization level1040is formed over the dielectric layer936and the metallization level930. The metallization level1040includes a jumper structure1042. The jumper structure1042is connected to the jumper structure932through an interconnect structure1044. The jumper structure1042and the interconnect structure1044are formed in a dielectric layer1046. The jumper structure1042and the interconnect structure1044each do not overlap with the bitline structure822in the vertical direction, here the z-axis direction.

In example operation650, with reference also toFIG.11, an upper metallization level1150is formed over the dielectric layer1046and the metallization level1040. The metallization level1150includes a wordline structure1152. The wordline structure1152is connected to the jumper structure1042through an interconnect structure1154. The wordline structure1152and the interconnect structure1154are formed in a dielectric layer1156. The interconnect structure1154does not overlap with the bitline structure822in the vertical direction, here the z-axis direction. Through the jumper structures1042,932and the island824, the wordline structure1152is ultimately connected to the gate of the transistor. The wordline structure1152, although overlapping with the bitline structure822, is vertically spaced apart from the bitline structure822by at least one metallization level that none of the wordline structure1152or the bitline structure822is formed from. The increased vertical distance between the wordline structure1152and the bitline structure822reduces coupling capacitance between the wordline structure1152and the bitline structure822when both are supplied with electrical signals.

In some embodiments, the method600may be used to fabricate the SRAM cells100,500or other SRAM cells. For example, the wordline structure1152ofFIG.11may be configured as the wordline WL ofFIG.3. The jumper structures932,1042may be configured as the jumper structures320(1),320(2) ofFIG.3. The island structure824may be configured as the connection island structure330ofFIG.3. The bit line structure822may be configured as the second bitline BL2ofFIG.3.

In the description herein, a FET transistor is used as an illustrative example to describe the example SRAM memory cells, e.g., the 6T SRAM cell ofFIG.1and the 8T SRAM cell ofFIG.5. It should be noted that other type of transistors, e.g., a bipolar transistor, may also be used to form a SRAM cell, which are all included in the disclosure.

In the description herein, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the disclosure. However, one skilled in the art will understand that the disclosure may be practiced without these specific details. In other instances, well-known structures associated with electronic components and fabrication techniques have not been described in detail to avoid unnecessarily obscuring the descriptions of the embodiments of the present disclosure.

Unless the context requires otherwise, throughout the specification and claims herein, the word “comprise” and variations thereof, such as “comprises” and “comprising,” are to be construed in an open, inclusive sense, that is, as “including, but not limited to.”

The use of ordinals such as first, second and third does not necessarily imply a ranked sense of order, but rather may only distinguish between multiple instances of an act or structure.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the content clearly dictates otherwise. It should also be noted that the term “or” is generally employed in its sense including “and/or” unless the content clearly dictates otherwise.

A finFET or gate all around (GAA) structures may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the finFET or GAA structure.

The present disclosure may be further appreciated with the description of the following embodiments:

In a structure embodiment, a structure includes a substrate and a first transistor of a memory cell formed over the substrate. The first transistor includes a first terminal and a second terminal. A first metallization level is formed over the first transistor. The first metallization level includes a first metal line structure and a metal island structure separated from the first metal line structure. The first metal line structure is longitudinal oriented along a first lateral direction and is connected to the first terminal of the first transistor. The metal island structure is connected to the second terminal of the first transistor. A second metallization level is formed over the first metallization level. The second metallization level includes a first metal jumper structure. The first metal jumper structure is connected to the metal island structure and is positioned non-overlapping with the first metal line structure. A third metallization level is formed over the second metallization level. The third metallization level includes a second metal line structure. The second metal line structure is longitudinal oriented along a second lateral direction that is different from the first lateral direction. The second metal line structure is connected to the first metal jumper structure.

In another embodiment, a memory device includes a substrate and a pass gate transistor over the substrate. The pass gate transistor includes a first terminal and a second terminal. A first signal line is positioned in a first metallization level over the first transistor. The first signal line is connected to the first terminal of the pass gate transistor. A metal island structure is positioned in the first metallization level. The metal island structure is laterally separated from the first signal line. A second signal line is positioned in a second metallization level vertically separated from the first metallization level by at least a third metallization level vertically positioned between the first metallization level and the second metallization level. A first metal jumper structure is positioned in the third metallization level. The first metal jumper structure is connected to both the second signal line and the metal island structure.

In a method embodiment, a method includes forming a first metallization level over a wafer. The wafer includes a first transistor of a memory cell over a substrate. The first transistor includes a first terminal and a second terminal. The first metallization level includes a first metal line structure and a metal island structure laterally separated from the first metal line structure. The first metal line structure is longitudinal oriented along a first lateral direction and is connected to the first terminal of the first transistor. The metal island structure is connected to the second terminal of the first transistor. A second metallization level is formed over the first metallization level. The second metallization level includes a first metal jumper structure. The first metal jumper structure is connected to the metal island structure and is positioned non-overlapping with the first metal line structure. A third metallization level is formed over the second metallization level. The third metallization level includes a second metal line structure. The second metal line structure is longitudinal oriented along a second lateral direction that is different from the first lateral direction. The second metal line structure is connected to the first metal jumper structure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.