Patent ID: 12249566

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

A method of forming a package with the gap-fill regions having improved heat-dissipation ability and the resulting structures are provided. The heat generated by device dies may dissipate through the gap-fill regions. The stress and the warpage in the resulting package may also be reduced. Embodiments discussed herein are to provide examples to enable making or using the subject matter of this disclosure, and a person having ordinary skill in the art will readily understand modifications that can be made while remaining within contemplated scopes of different embodiments. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

FIGS.1through12illustrate the cross-sectional views of intermediate stages in the formation of a package in accordance with some embodiments of the present disclosure. The corresponding processes are also reflected schematically in the process flow shown inFIG.15.

FIG.1illustrates a cross-sectional view in the formation of package component20. The respective process is illustrated as process202in the process flow200as shown inFIG.15. In accordance with some embodiments, package component20is a device wafer, which includes device dies20′ therein. Device dies20′ may include active devices and possibly passive devices, which are represented as integrated circuit devices24. In accordance with alternative embodiments, package component20is an interposer die, which is free from active devices, and may or may not include passive devices. In accordance with yet alternative embodiments, package component20is or comprises a package such as an Integrated Fan-Out (InFO) Package, a redistribution structure including redistribution lines therein, or the like.

In accordance with some embodiments, package component20includes semiconductor substrate22and the features formed over semiconductor substrate22. Semiconductor substrate22may be formed of or comprise crystalline silicon, crystalline germanium, crystalline silicon germanium, carbon-doped silicon, a III-V compound semiconductor, or the like. Semiconductor substrate22may also be a bulk semiconductor substrate or a Semiconductor-On-Insulator (SOI) substrate.

In accordance with some embodiments, package component20includes integrated circuit devices24, which are formed at the top surface of semiconductor substrate. Integrated circuit devices24may include Complementary Metal-Oxide Semiconductor (CMOS) transistors, resistors, capacitors, diodes, and/or the like in accordance with some embodiments. The details of integrated circuit devices24are not illustrated herein.

Inter-Layer Dielectric (ILD)28is formed over semiconductor substrate22and fills the spaces between the gate stacks of transistors (not shown) in integrated circuit devices24. In accordance with some embodiments, ILD28is formed of silicon oxide, Phospho Silicate Glass (PSG), Boro Silicate Glass (BSG), Boron-doped Phospho Silicate Glass (BPSG), Fluorine-doped Silicate Glass (FSG), or the like. ILD28may be formed using spin-on coating, Flowable Chemical Vapor Deposition (FCVD), or the like. In accordance with some embodiments, ILD28may also be formed using a deposition method such as Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), or the like.

Contact plugs30are formed in ILD28, and are used to electrically connect integrated circuit devices24to overlying metal lines and vias. In accordance with some embodiments of the present disclosure, contact plugs30are formed of or comprise a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys therefore, and/or multi-layers thereof. The formation of contact plugs30may include forming contact openings in ILD28, filling a conductive material(s) into the contact openings, and performing a planarization process (such as a Chemical Mechanical Polish (CMP) process or a mechanical grinding process) to level the top surfaces of contact plugs30with the top surface of ILD28.

Interconnect structure32is formed over semiconductor substrate22. In accordance with some embodiments, interconnect structure32includes a plurality of dielectric layers34, and a plurality of conductive features such as metal lines/pads36and vias38in the dielectric layers34.

Dielectric layers34may include low-k dielectric layers (also referred to as Inter-metal Dielectrics (IMDs)) in accordance with some embodiments. The dielectric constants (k values) of the low-k dielectric layers may be lower than about 3.5 or 3.0, for example. The low-k dielectric layers may comprise a carbon-containing low-k dielectric material, Hydrogen SilsesQuioxane (HSQ), MethylSilsesQuioxane (MSQ), or the like.

The formation of metal lines36and vias38in dielectric layers34may include single damascene processes and/or dual damascene processes. In a single damascene process for forming a metal line or a via, a trench or a via opening is first formed in one of dielectric layers34, followed by filling the trench or the via opening with a conductive material. A planarization process such as a CMP process is then performed to remove the excess portions of the conductive material higher than the top surface of the dielectric layer, leaving a metal line or a via in the corresponding trench or via opening. In a dual damascene process, both of a trench and a via opening are formed in a dielectric layer, with the via opening underlying and connected to the trench. Conductive materials are then filled into the trench and the via opening to form a metal line and a via, respectively. The conductive materials may include a diffusion barrier layer and a copper-containing metallic material over the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like.

Metal lines36include top conductive (metal) features (denoted as36T) such as metal lines, metal pads, or vias in a top dielectric layer (denoted as dielectric layer34T), which is the top layer of dielectric layers34. In accordance with some embodiments, dielectric layer34T is formed of a low-k dielectric material similar to the material of lower ones of dielectric layers34. The metal features36T in the top dielectric layer34T may also be formed of copper or a copper alloy, and may have a dual damascene structure or a single damascene structure.

Interconnect structure32may also include a passivation layer (not shown), which is over, and may be in contact with, an underlying dielectric layer34. The passivation layer may be formed of a non-low-k dielectric material, which may comprise silicon and another element(s) including oxygen, nitrogen, carbon, and/or the like. The material of the passivation layer may be expressed as SiOxNyCz, with x being in the range between about 0 and about 2, y being in the range between about 0 and about 1.33, and z being in the range between about 0 and about 1, and x, y, and z will not be all equal to zero. For example, the passivation layer may be formed of or comprises SiON, SiN, SiOCN, SiCN, SiOC, SiC, or the like.

Bond layer41and bond pads40are formed as a top portion of interconnect structure32. Bond layer41may be formed of a silicon-containing dielectric material selected from SiO, SiC, SiN, SION, SiOC, SiCN, SiOCN, or the like, or combinations thereof. Bond pads40may comprise copper, and may be formed through a damascene process. The bond layer41and bond pads40are planarized so that their top surfaces are coplanar, which may be resulted due to a Chemical Mechanical Polish (CMP) process performed in the formation of bond pads40.

Referring toFIG.2, device dies42(also referred to as top dies) are bonded to the device dies20′ (also referred to as bottom dies) in package component20. The respective process is illustrated as process204in the process flow200as shown inFIG.15. In accordance with some embodiments, each of device dies42may be a logic die, which may be a Central Processing Unit (CPU) die, a microcontroller (MCU) die, an input-output (IO) die, a BaseBand die, or the like. Device dies42may also include memory dies.

Device dies42may include semiconductor substrates44. Through-Silicon Vias (TSVs)46, sometimes referred to as through-semiconductor vias or through-vias, are formed to extend into semiconductor substrates44. TSVs46are used to connect the integrated circuit devices and metal lines formed on the front side (the illustrated bottom side) of semiconductor substrates44to the backside, and connect device die20′ to a subsequently formed redistribution structure. Also, device dies42include interconnect structures48for connecting to the active devices and passive devices in device dies42. Interconnect structures48include metal lines and vias.

Each of device dies42includes bond pads51and bond layer52(also referred to as a bond film) at the illustrated bottom surface of device die42. The bottom surfaces of bond pads51may be coplanar with the bottom surface of bond layer52. In accordance with some embodiments, Bond layer52may be formed of a silicon-containing dielectric material, which may be selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, or the like, or combinations thereof. Bond pads51may comprise copper, and may be formed through a damascene process. The bond layer52and bond pads51are planarized so that their surfaces are coplanar, which may be resulted due to the CMP in the formation of bond pads51.

The bonding may be achieved through hybrid bonding. For example, bond pads51are bonded to bond pads40through metal-to-metal direct bonding. In accordance with some embodiments, the metal-to-metal direct bonding is copper-to-copper direct bonding. Furthermore, bond layers52are bonded to bond layer41through fusion bonding, for example, with Si—O—Si bonds being generated. The structure illustrated inFIG.2is referred to as reconstructed wafer50hereinafter, and more features are subsequently formed to further expand the reconstructed wafer50in subsequent processes.

In accordance with some embodiments, a backside grinding process may be performed to thin device dies42. Through the thinning of device dies42, the aspect ratio of the gaps between neighboring device dies42is reduced in order to perform gap filling. Otherwise, the gap filling may be difficult due to the otherwise high aspect ratio of the gaps. After the backside grinding process, TSVs46may be revealed. Alternatively, TSVs46are not revealed at this time, and the backside grinding is stopped when there is a thin layer of substrate covering TSVs46. In accordance with these embodiments, TSVs46may be revealed in the step shown inFIG.5.

FIGS.3and4illustrate the formation of a plurality of gap-fill layers. In accordance with some embodiments, the gap-fill layers include dielectric liner54, and gap-fill layer56over and contacting dielectric liner54.

Referring toFIG.3, dielectric liner54is deposited. The respective process is illustrated as process206in the process flow200as shown inFIG.15. Dielectric liner54may be deposited using a conformal deposition method such as Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD). Dielectric liner54is formed of a dielectric material that has good adhesion to the sidewalls of device dies42and the top surfaces of bond layer41and bond pads40. In accordance with some embodiments, dielectric liner54is formed of a nitride-containing material such as silicon nitride, SiON, SiCN, or the like. Dielectric liner54extends on, and contacts, the sidewalls of device dies42.

FIG.4illustrates the formation of gap-fill layer56over and contacting dielectric liner54. The respective process is illustrated as process208in the process flow200as shown inFIG.15. The thermal conductivity of gap-fill layer56is higher than the thermal conductivity of silicon oxide. For example, the thermal conductivity of silicon oxide may be in the range between about 1.1 watt/m-k and about 1.3 watt/m-k. Accordingly, the thermal conductivity of gap-fill layer56may be equal to or higher than about 1.5 watt/m-k, and may be in the range between about 1.5 watt/m-k and about 500 watt/m-k.

In accordance with some embodiments, gap-fill layer56is a single layer, with an entirety of the gap-fill layer56being formed of a homogeneous material. The material of gap-fill layer56is different from the material of dielectric liner54. In accordance with some embodiments, gap-fill layer56is formed of a semiconductor material such as silicon, III-V semiconductor, or the like. When silicon is used, gap-fill layer56is formed of amorphous silicon, which may be undoped with any of the p-type and n-type impurity, and thus is intrinsic. Accordingly, gap-fill layer56is intrinsic. This will keep the electrical conductivity value of gap-fill layer56low, and hence the leakage current through gap-fill layer56to be low.

The amorphous silicon may have a thermal conductivity of about 1.8 watt/m-k, which is significantly greater than the thermal conductivity of silicon oxide. In accordance with alternatively embodiments, gap-fill layer56comprises mainly amorphous silicon, with a small percentage, for example, less than 10 percent polysilicon therein. Since crystalline silicon has a thermal conductivity much higher than, for example, about 100 times higher than, the thermal conductivity of amorphous silicon, incorporating even a small amount of polysilicon in the amorphous silicon of gap-fill layer56may significantly improve the thermal conductivity of gap-fill layer56, for example, to be greater than about 5 watt/m-k or higher.

In accordance with some embodiments in which gap-fill layer56comprises polycrystalline silicon, the polycrystalline silicon may be polycrystalline islands (particles) fully enclosed in, and separated by, the amorphous silicon. The generation of small amount of polysilicon may be achieved, for example, by slightly increasing the deposition temperature of gap-fill layer56, reducing the deposition rate, and/or the like. The generation of small amount of polysilicon may also be achieved by annealing gap-fill layer56after deposition, for example, after the process shown inFIG.4orFIG.5.

In accordance with some embodiments, gap-fill layer56is deposited using Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), and/or the like.

Using amorphous silicon to form gap-fill layer56has some advantageous features. The thermal conductivity is relatively high, and hence heat may dissipate more efficiently through gap-fill layer56to other features such as a heat sink. Also, the coefficient of thermal expansion (CTE) of amorphous silicon is closer to that of semiconductor substrate22than other materials. Accordingly, the stress and the warpage in the resulting package is reduced.

In accordance with alternative embodiments in which gap-fill layer56comprises a semiconductor material, gap-fill layer56may be formed of or comprises a III-V semiconductor, which may be formed or comprises GaAs, InP, GaN, InN, and/or the like, or combinations thereof. The III-V semiconductors may have high thermal conductivity values. For example, GaAs may have a thermal conductivity equal to about 52 watt/m-k, InP may have a thermal conductivity equal to about 68 watt/m-k, GaN may have a thermal conductivity equal to about 130 watt/m-k, GaP may have a thermal conductivity equal to about 110 watt/m-k, and InN may have a thermal conductivity in the range between about 45 watt/m-k and about 175 watt/m-k. Accordingly, III-V compound semiconductors may have very high thermal conductivity values compared to that of silicon oxide.

In accordance with some embodiments, the III-V compound semiconductor that forms gap-fill layer56may be undoped with the impurities that cause it to be n-type and/or p-type. Accordingly, gap-fill layer56may be intrinsic or unintentionally doped. This will keep the electrical conductivity value, and hence the leakage current through it, if any, to be low.In accordance with alternative embodiments, gap-fill layer56is formed of or comprises a dielectric material, which also has a higher thermal conductivity than silicon oxide. For example, gap-fill layer56may be formed of silicon-based dielectrics such as silicon carbide, silicon oxynitride, silicon oxy-carbo-nitride, or the like. The thermal conductivity value of the dielectric material may be greater than about 1.5 watt/m-k, and may be in the range between about 1.5 watt/m-k and about 10 watt/m-k. The corresponding gap-fill layer56may also have an amorphous structure.

In accordance with alternative embodiments, gap-fill layer56has a multi-layer structure including a plurality of layers. For example,FIG.4illustrates that an example gap-fill layer56may include sub layers56A,56B,56C, and56D, which are also collectively referred to as sub layers56. In accordance with various embodiments, gap-fill layer56may include two sub layers, three sub layers, four sub layers, five sub layers, or more. In accordance with some embodiments, neighboring sub layers56are formed of different materials. The sub layers that are not in contact with each other may be formed of a same material or different materials. In accordance with some embodiments, sub layers56A and56C are formed of a same material, and/or sub layers56B and56D are formed of a same material. In accordance with alternative embodiments, sub layers56A and56C are formed of different materials, and/or sub layers56B and56D are formed of different materials.

In accordance with some embodiments in which gap-fill layer56has a multi-layer structure, the dielectric sub layers (if any) in gap-fill layer56may include silicon oxide, silicon nitride, silicon oxynitride, amorphous silicon carbide, silicon oxycarbide, and/or the like. The semiconductor sub layers (if any) in gap-fill layer56may include amorphous silicon (with or without small polycrystalline islands therein), or may include a III-V semiconductor material such as GaAs, InP, GaN, GaP, InN, or the like, or combinations thereof.

Also, the sub layers may have mixed structure including a semiconductor layer(s) and a dielectric layer(s). For example, sub layer56A or56B may be a dielectric layer (and having low leakage), while sub layer56B or56C may be a semiconductor layer that has a high thermal conductivity.

In accordance with some embodiments, as shown inFIG.4, lower sub layers56A,56B, and56C are conformal layers, which may be formed through ALD, CVD, or the like. The top sub layer such as sub layer56D may be conformal or non-conformal. In accordance with alternative embodiments, some or all of the sub layers in gap-fill layer are non-conformal. This may be achieved through bottom-up deposition such as Flowable Chemical Vapor Deposition (FCVD), spin-on coating, or the like.

Forming gap-fill layer56as having a multi-layer structure have some advantageous features. For example, the requirement of having low leakage current and high thermal conductivity can both be met by adopting sub layers. In an example embodiment, some sub layers such as56A and/or56C are formed of dielectric materials having low leakage currents, and hence act as leakage barriers. Other sub layers such as56B and/or56D may be formed of a material(s) with high thermal conductivities. The dielectric materials may have small thicknesses so that its effect to the thermal conductivity is small. The high-thermal-conductivity layer(s) may have greater thicknesses greater than the thickness of the leakage barriers, so that the resulting gap-fill layer56has an overall higher thermal resistance.

The materials and the thicknesses of the sub layers may be adjusted, so that the stress in the resulting gap-fill layer56is reduced. In accordance with some embodiments, sub layer56A is a dielectric layer formed of a silicon-containing dielectric material, the bottom horizontal portion of sub layer56A may have a top surface56A-T, which is level with or substantially level with (for example, with a variation smaller than about 0.1 μm) the bottom surface44-B of substrate44. The overlying sub layers56B,56C, and56D, instead of being multiple layers, may be formed as a single layer instead. The single layer may be formed of amorphous silicon. Accordingly, the gap-fill layer56may have a similar structure as device die42, with a silicon region and a dielectric region underlying the silicon region. This structure will have significantly reduced stress and warpage.

Referring toFIG.5, a planarization process such as a CMP process or a mechanical grinding process is performed to remove excess portions of gap-fill layer56and dielectric liner54, so that semiconductors44of device dies42are exposed. The respective process is illustrated as process210in the process flow200as shown inFIG.15. Also, the top surfaces of through-vias46are exposed. The remaining portions of dielectric liner54and gap-fill layer56are collectively referred to as gap-fill regions62or isolation regions62.

FIG.6through9illustrate the formation of through-via72, which penetrates through gap-fill region62. Referring toFIG.6, Bottom Anti-Reflective Coating (BARC)64and photoresist66are formed. In accordance with some embodiments, BARC64may be formed of a cross-linked photoresist, an SiON layer, or the like. Photoresist66is patterned, and is used to etch BARC64, followed by the etching of gap-fill region62.

In accordance with some embodiments, the etching of gap-fill region62is performed through a Bosch process. The Bosch process may include etching a top portion of the gap-fill region62to form an opening68, forming a first protection layer on the sidewall of the opening68, further etching the gap-fill region62to extend opening68down, forming a second protection layer on the sidewall of the opening68, and etching the gap-fill region62to extend opening68down. The protection layers may be formed of polymers, an inorganic dielectric material, or the like. The process is repeated until opening68extends to dielectric liner54. The protection layers are then removed, resulting in the structure shown inFIG.6. Dielectric liner54is thus exposed. Opening68is thus formed. The respective process is illustrated as process212in the process flow200as shown inFIG.15.

In the etching process, dielectric liner54may act as an etch stop layer. Another etching process is then performed to etch-through dielectric liner54, exposing the underlying bond pad40.

In accordance with some embodiments, by using the Bosch process, the etching rate is increased, for example, to a range between about 3 μm and about 100 μm. This improves the throughput. When the Bosch process is used, the resulting opening68may have a plurality of lateral protrusions between the vertical-and-straight portions of the sidewalls. In accordance with alternative embodiments, the etching is performed without using Bosch process (without forming protection layers in opening68and lining sidewalls of gap-fill region62). The sidewalls of gap-fill region62facing opening68may thus be straight. Photoresist66is removed after the etching process.

In accordance with alternative embodiments in which gap-fill regions62comprise a plurality of sub layers56, the lower sub layers may be used as the etch stop layers of the respective overlying sub layer(s). For example, sub layer56A may be used as the etch stop layer for the etching of sub layer56B, or the etch stop layer for etching sub layers56B,56C, and56D. Sub layer56B may be used as the etch stop layer for the etching of sub layer56C, or the etch stop layer for etching sub layers56C and56D.

Next, as shown inFIG.7, a dielectric liner71is formed lining opening68. The respective process is illustrated as process214in the process flow200as shown inFIG.15. Dielectric liner71may be formed of silicon nitride, silicon oxide, silicon oxynitride, silicon oxycarbide, or the like. Dielectric liner71may be formed as a conformal layer, which may be formed through ALD, CVD, or the like.

FIG.8illustrates the removal of the horizontal portions of dielectric liner71, for example, through an anisotropic etching process. The respective process is illustrated as process216in the process flow200as shown inFIG.15.

In a subsequent process, as shown inFIG.9, a conductive material is filled into opening68, followed by a planarization process to remove excess portions of the conductive material, forming through-via72. The respective process is illustrated as process218in the process flow200as shown inFIG.15. In accordance with alternative embodiments, no through-via is formed in gap-fill regions62.

Referring toFIG.10, a (backside) interconnect structure74is formed on the backside of device dies42. The respective process is illustrated as process220in the process flow200as shown inFIG.15. Interconnect structure74includes redistribution lines (RDLs)76(which also include metal pads) and dielectric layers78. In accordance with some embodiments, dielectric layer78is formed of an oxide such as silicon oxide, a nitride such as silicon nitride, or the like. RDLs76may be formed using damascene processes, which includes etching dielectric layer78to form openings, depositing a conductive barrier layer into the openings, plating a metallic material such as copper or a copper alloy, and performing a planarization process to remove excess portions of RDLs76. Alternatively, RDLs76may be formed through plating processes.

Electrical connectors82are formed on interconnect structure74, and are electrically connected to device dies42and possibly through-vias72through RDLs76. In accordance with some embodiments, electrical connectors82comprise solder regions, metal bumps, and/or the like. Reconstructed wafer50is thus formed.

In subsequent processes, as shown inFIG.11, reconstructed wafer50is singulated in a sawing process, so that discrete packages50′ are formed. The respective process is illustrated as process222in the process flow200as shown inFIG.15. The discrete packages50′ may include device dies20′ and42.

FIG.12illustrates the bonding of package50′ to package component84in accordance with some embodiments. The respective process is illustrated as process224in the process flow200as shown inFIG.15. Package component84may be an interposer, a package substrate, a package including device dies therein, or the like. Underfill86may be dispensed in the gap between package50′ and package component84. Package88is thus formed.

In the structure as shown inFIG.12, through-via72may have a plurality of lateral protrusion portions protruding laterally beyond the vertical-and-straight sidewalls of the overlying portions of through-via72. The protrusion portions are caused due to the formation of the protection layers in the Bosch process. In accordance with some embodiments, the positions of the protrusion portions may be at any height of the through-via72, depending on the positions of stop etching in order to form protection layers.

In the structure shown inFIG.12, the heat generated in device die20′ may pass through device dies42and gap-fill regions62, and dissipate to package component84. With the gap-fill layer56having a high thermal conductivity, more heat can be dissipated through gap-fill regions62.

In accordance with alternative embodiments, a heat sink may be under and attached to device die20′. Accordingly, with gap-fill regions62having a high thermal conductivity value, the heat generated in device dies42may dissipate to gap-fill regions62, and from gap-fill regions62into device die20′ and to the heat sink. Due to the high thermal conductivity value of gap-fill layer56, the thermal resistance in this heat dissipation path is reduced. Accordingly, in addition to the heat path from device dies42directly into device die20′ and to the heat sink, another heat dissipation path through gap-fill regions62also has reduced thermal resistance.

FIG.13illustrates package88formed in accordance with alternative embodiments. In accordance with these embodiments, gap-fill regions62may have a multi-layer structure, in which some sub layers are used as etch stop layers for etching the overlying sub layer(s). For example, sub layer56C may be used as an etch stop layer, which may be etched through an isotropic etch process (which may be a dry etch process or a wet etch process). There may be undercuts formed in the etch stop layer, and accordingly, through-via72has protrusion portions laterally extending into the etch stop layer, while the portions in the overlying and underlying layers do not have lateral protrusion portions. The materials and the structures of the sub layers have been discussed referring to preceding embodiments.

FIG.14illustrates package88formed in accordance with yet alternative embodiments. In accordance with these embodiments, through-via72may have straight edges. In the formation of the respective opening68(FIG.6), a same etching gas that is configured to etch all sub layers56may be used, and no Bosch process is used. Accordingly, the sidewalls of gap-fill regions62facing opening68may be straight. The resulting through-via72also has straight edges, as shown inFIG.14.

In above-illustrated embodiments, some processes and features are discussed in accordance with some embodiments of the present disclosure to form a three-dimensional (3D) package. Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.

The embodiments of the present disclosure have some advantageous features. By forming isolation regions with high thermal conductivity values, the heat dissipation through the isolation regions is improved. The materials and the structure of the isolation regions are selected, so that the stress and the warpage of the resulting packages are also reduced.

In accordance with some embodiments of the present disclosure, a method comprises bonding a top die to a bottom die; depositing a first dielectric liner on the top die; depositing a gap-fill layer on the first dielectric liner, wherein the gap-fill layer has a first thermal conductivity value higher than a second thermal conductivity value of silicon oxide; etching the gap-fill layer and the first dielectric liner to form a through-opening, wherein a metal pad in the bottom die is exposed to the through-opening; depositing a second dielectric liner lining the through-opening; filling the through-opening with a conductive material to form a through-via connecting to the metal pad; and forming a redistribution structure over and electrically connecting to the top die and the through-via.

In an embodiment, the depositing the gap-fill layer comprises depositing a first sub layer comprising a first material; and depositing a second sub layer over the first sub layer, wherein the second sub layer comprises a second material different from the first material. In an embodiment, a first one of the first sub layer and the second sub layer comprises amorphous silicon, and a second one of the first sub layer and the second sub layer comprises a dielectric material. In an embodiment, the gap-fill layer comprises a first plurality of sub layers and a second plurality of sub layers stacked alternatingly, wherein the first plurality of sub layers comprise the first material, and the second plurality of sub layers comprise the second material.

In an embodiment, the etching the gap-fill layer comprises etching the second sub layer, with the first sub layer being used as an etch stop layer. In an embodiment, the etching the gap-fill layer is performed through a Bosch process. In an embodiment, the etching the gap-fill layer is performed without stopping until the first dielectric liner is exposed. In an embodiment, the depositing the gap-fill layer comprises depositing an amorphous silicon layer. In an embodiment, the depositing the gap-fill layer comprises depositing an amorphous silicon-based dielectric layer. In an embodiment, the depositing the gap-fill layer comprises depositing a III-V compound semiconductor layer.

In accordance with some embodiments of the present disclosure, a structure comprises a bottom die; a top die over and bonding to the bottom die, wherein the top die comprises a top metal pad; a dielectric liner comprising a vertical portion on sidewalls of the top die, and a horizontal portion on the bottom die; a gap-fill layer overlapping the horizontal portion of the dielectric liner, wherein the gap-fill layer has a first thermal conductivity value higher than a second thermal conductivity value of silicon dioxide; a through-via penetrating through the dielectric liner and the gap-fill layer, wherein the through-via contacts the top metal pad; and a redistribution structure over and electrically coupling to the top die and the through-via.

In an embodiment, the gap-fill layer comprises an amorphous silicon-based dielectric material. In an embodiment, the gap-fill layer comprises a semiconductor material. In an embodiment, the gap-fill layer comprises a first sub layer comprising a first material; and a second sub layer over the first sub layer, wherein the second sub layer comprises a second material different from the first material. In an embodiment, a first one of the first sub layer and the second sub layer comprises a semiconductor, and a second one of the first sub layer and the second sub layer comprises a dielectric material. In an embodiment, the through-via comprises a plurality of lateral protrusions.

In accordance with some embodiments of the present disclosure, a structure comprises a bottom die; a top die over and bonding to the bottom die; a first dielectric liner comprising a first portion on sidewalls of the top die, and a second portion on a top surface of the bottom die; a gap-fill layer contacting the first dielectric liner, wherein the gap-fill layer comprises a first sub layer comprising a semiconductor material; a through-via penetrating through the first dielectric liner and the gap-fill layer; and a second dielectric liner encircling the through-via, wherein the second dielectric liner electrically insulates the through-via from the gap-fill layer. In an embodiment, the semiconductor material of the gap-fill layer comprises a III-V compound semiconductor material. In an embodiment, the semiconductor material of the gap-fill layer comprises amorphous silicon. In an embodiment, the gap-fill layer further comprises a second sub layer contacting the first sub layer, and wherein the second sub layer is formed of a different material than the first sub layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.