Patent ID: 12193227

DETAILED DESCRIPTION

The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

A memory device may, for example, comprise a plurality of device lines. The plurality of device lines comprises a select gate (SG) line, a control gate (CG) line, an erase gate (EG) line, and a source line that are elongated in parallel. The CG line is between the EG and SG lines, and the source line underlies the EG line in a substrate. The plurality of device lines defines a plurality of memory cells and a plurality of strap cells spaced along lengths of the device lines. The strap cells electrically couple the device lines to metal lines with lower resistances than the device lines repeatedly along the device lines to reduce resistances and hence voltage drops along the device lines. At a strap cell for the source line (e.g., a source strap cell), the EG line has a break to allow access to the source line. At a strap cell for the CG line (e.g., a CG strap cell), the CG line has a pad protruding laterally. Further, the SG line has a break to prevent a risk of a contact via electrically shorting the CG and SG lines together and/or to prevent the SG line from electrically shorting with a neighboring SG line.

In some embodiments, while forming the source and CG strap cells, a first etch is performed into the EG line and the SG line with a first mask in place. The first etch stops on a source dielectric layer and a substrate portion respectively underlying the EG and SG lines. Further, the first etch simultaneously forms a first opening and a second opening respectively extending through the EG and SG lines respectively at the source and CG strap cells. Thereafter, a second etch is performed into the source dielectric layer, but not the substrate portion, with a second mask in place. The second etch removes a portion of the source dielectric layer in the first opening to expose the source line at the source strap cell. A resist protection oxide (RPO) layer is deposited lining the first opening, and a third etch is performed into the RPO layer with a third mask in place to extend the first opening through the RPO layer to the source line. A silicide layer is formed on the source line with the RPO layer in place, and a contact via is formed on the silicide layer. A challenge is that formation of the second mask may result in photoresist scum on the source line that persists even after removal of the second mask. The scum may prevent the silicide layer from properly forming on the source line and may hence lead to a high resistance connection between the contact via and the source line. The high resistance connection may lead to device failure and/or shift operating parameters (e.g., power consumption) out of specification, whereby bulk manufacturing yields may be low.

Various embodiments of the present disclosure are directed towards an enhanced etch method for opening the source line in the memory device, as well as the memory device itself. It has been appreciated that the second mask may be omitted and the second etch may instead be performed with the first mask in place to thin the source dielectric layer but not expose the source line. Further, the third etch may be extended (e.g., increased in duration) to extend the first opening through the source dielectric layer and to expose the source line. Hence, the enhanced etch method may use at least one less photomask. Because photomasks are costly to form and photolithography process tools are costly to use, one less photomask is a substantial cost savings. Additionally, because the second mask may be omitted, the risk of scum the source line in the first opening is reduced. This enlarges the process window (e.g., makes the process more resilient) for forming the silicide layer and the contact via.

With reference toFIGS.1A-1C, various views100A-100C of some embodiments of a memory device comprising a source strap cell102is provided.FIG.1Acorresponds to a cross-sectional view100A of the source strap cell102in a first direction (e.g., an Y direction), whereasFIG.1Bcorresponds to a cross-sectional view100B of the source strap cell102in a second direction (e.g., a X direction) orthogonal to the first direction.FIG.1Ccorresponds to a top layout of the source strap cell102.FIGS.1A and1Bmay, for example, be taken respectively along line A inFIG.1Cand line B inFIG.1C. The memory device may, for example, be or be part of an integrated circuit (IC) chip or some other suitable semiconductor structure. Further, the memory device may, for example, be a third generation SUPERFLASH (ESF3) memory device or some other suitable split gate flash memory device.

The source strap cell102overlies an active region104aof a substrate104and is defined in part by a source line106, an EG line108, and CG lines110that are elongated in parallel. For example, the various lines may be elongated in parallel along a column of a memory array. The active region104aof the substrate104is a top region of the substrate104that is surrounded and demarcated by a trench isolation structure112. The trench isolation structure112may be or comprise, for example, silicon oxide and/or some other suitable dielectric(s). Further, the trench isolation structure112may be or comprise, for example, a shallow trench isolation (STI) structure or some other suitable trench isolation structure. The substrate104may be, for example, a bulk monocrystalline silicon substrate, a silicon-on-insulator (SOI) substrate, or some other suitable semiconductor substrate.

The source line106and the EG line108are between the CG lines110, and the EG line108overlies the source line106while remaining spaced from the source line106by a source dielectric layer114. Further, the CG lines110respectively overlie floating gates116and are separated from a break118in the EG line108and the source dielectric layer114by main sidewall spacers120. The break118separates (or breaks) the EG line108into separate EG segments along a length of the EG line108. Silicide layers122are respectively on the EG line108and the source line106, and contact vias124extend respectively to the silicide layers122. The silicide layers122provide low resistance electrical coupling from the contact vias124respectively to the EG line108and the source line106.

As seen hereafter, the source strap cell102may, for example, be formed using an enhanced method for opening the source line106(e.g., for forming the break118in the EG line108and the source dielectric layer114). Instead of using a photolithography/etching process specifically for clearing the source dielectric layer114at the break118, the enhanced method thins the source dielectric layer114while clearing the EG line108at the break118and etches through the source dielectric layer114while patterning a resist protect dielectric (RPD) layer (not shown) used during formation of a source silicide layer122a. As such, the enhanced method may use one less photomask. Because photomasks are costly to form and photolithography process tools are costly to use, one less photomask is a substantial cost savings. Additionally, because one less photomask may be used, the risk of photoresist scum on the source line106may be reduced. The reduced scum risk may enlarge the process window (e.g., make the process more resilient) for forming the source silicide layer122aand a source contact via124aon the source silicide layer122a. Hence, the reduced scum risk may reduce the likelihood of the source contact via124afailing to properly electrically couple to the source silicide layer122a. Too much scum on the source silicide layer122amay prevent the source silicide layer122afrom fully forming on the source line106, such that the source silicide layer122amay be small and/or nonexistent. Hence, the source contact via124amay fail to fully land on the source silicide layer122aand resistance from the source contact via124ato the source line106may be high. This high resistance may, in turn, shift operating parameters of the memory device out of specification and/or lead to low yields.

By opening the source line106according to the enhanced method, the main sidewall spacers120overlie a thinned portion of the source dielectric layer114inFIG.1A. As such, a height Hsof the main sidewall spacers120is greater than it would otherwise be inFIG.1A. In some embodiments, the height Hsof the main sidewall spacers120is about 400-800 angstroms, about 400-600 angstroms, about 600-800 angstroms, or some other suitable value. Further, by opening the source line106according to the enhanced method, a width Wsof the source silicide layer122amay be larger than it would otherwise be inFIG.1B. Further, a ratio of the width Wsto a separation S between EG segments of the EG line108may be larger than it would otherwise be inFIG.1B. As such, the likelihood of the source contact via124aproperly landing on the source silicide layer122ais increased. This enlarges the process window for forming the source contact via124aand reduces the likelihood of source contact via124afailing to properly electrically couple to the source contact via124a.

In some embodiments, the width Wsof the source silicide layer122ais about 800-1100 angstroms, about 800-950 angstroms, about 950-1100 angstroms, or some other suitable value. If the width Wsis too small (e.g., less than about 800 angstroms or some other suitable value), the likelihood of the source contact via124aproperly landing on the source silicide layer122amay be low. As such, the process window for forming the source contact via124amay be small and the likelihood of high resistance, or no, electrically coupling between the source contact via124aand the source line106may be high. If the width Wsis too large (e.g., greater than about 1100 or some other suitable value), scaling down of the memory device may be hindered for little to no gain in the process window for the source contact via124a.

In some embodiments, a ratio of the width Wsto the separation S is greater than about 0.4:1.0, about 0.5:1.0, about 0.6:1.0, or some other suitable ratio. In some embodiments, a ratio of the width Wsto the separation S is about 0.4:1.0 to about 0.6:1.0, about 0.6:1.0 to 0.8:1.0, or some other suitable ratio. If the ratio is too low (e.g., less than about 0.4:1.0 or some other suitable ratio), the source silicide layer122amay be small and the likelihood of the source contact via124aproperly landing on the source silicide layer122amay be low.

With continued reference toFIGS.1A-1C, the source line106may, for example, be or comprise a doped portion of the substrate104and/or some other suitable semiconductor region. The EG line108, the CG lines110, and the floating gates116may, for example, be or comprise doped polysilicon and/or some other suitable conductive material(s). The silicide layers122may, for example, be or comprise metal silicide and/or some other suitable silicide(s). The contact vias124may be or comprise, for example, metal and/or some other suitable conductive material(s). The source dielectric layer114may, for example, be or comprise silicon oxide and/or some other suitable dielectric(s).

The CG lines110are separated from the floating gates116by corresponding CG dielectric layers126, and the floating gates116are separated from the substrate104by corresponding floating gate dielectric layers128. Further, the CG lines110are separated from the main sidewall spacers120by corresponding CG sidewall spacers130, and the floating gates116are separated from the main sidewall spacers120by corresponding EG tunnel dielectric layers132. In some embodiments, the EG tunnel dielectric layers132and the source dielectric layer114are defined by a common layer. The CG dielectric layers126and the CG sidewall spacers130may be or comprise, for example, silicon oxide, silicon nitride, some other suitable dielectric(s), or any combination of the foregoing. In some embodiments, as illustrated, the CG dielectric layers126and the CG sidewall spacers130are oxide-nitride-oxide (ONO) films. The floating gate dielectric layers128and the EG tunnel dielectric layers132may be or comprise, for example, silicon oxide and/or some other suitable dielectric(s).

An interconnect dielectric layer134covers the source strap cell102and fills the break118in the EG line108and the source dielectric layer114. Further, the interconnect dielectric layer134surrounds the contact vias124. The interconnect dielectric layer134may, for example, be or comprise silicon oxide and/or some other suitable dielectric(s).

WhileFIGS.1A-1Care described together with regard to the same memory device, each ofFIGS.1A-1Cmay stand alone independent of each other one ofFIGS.1A-1C. For example, a memory device may have the cross-sectional view100A ofFIG.1Abut may not have the cross-sectional view100B ofFIG.1Band/or the top layout100C ofFIG.1C. As another example, a memory device may have the cross-sectional view100B ofFIG.1Bbut may not have the cross-sectional view100A ofFIG.1Aand/or the top layout100C ofFIG.1C.

With reference toFIG.2A, an expanded cross-sectional view200A of some embodiments of the source strap cell102ofFIG.1Ais provided in which the source strap cell102is further defined in part by SG lines202. The SG lines202are elongated in parallel (not visible in the cross-sectional view200A) with the CG lines110, and the CG lines110are between and respectively border the SG lines202. Further, the SG lines202partially overlie the trench isolation structure112and are separated from the substrate104by corresponding SG dielectric layers204. The SG lines202may, for example, be or comprise doped polysilicon and/or some other suitable conductive material(s). The SG dielectric layers204may, for example, be or comprise silicon oxide and/or some other suitable dielectric(s).

The CG sidewall spacers130and SG sidewall spacers206separate the CG lines110respectively from the SG lines202. The CG sidewall spacers130are on sidewalls of the CG lines110, whereas the SG sidewall spacers206are on sidewalls of the SG lines202that face the CG lines110. Further, the main sidewall spacers120are on sidewalls of the SG lines202that face away from the CG lines110. The SG sidewall spacers206may be or comprise, for example, silicon oxide and/or some other suitable dielectric(s). In some embodiments, the CG sidewall spacers130are or comprise ONO films, the SG sidewall spacers206are or comprise silicon oxide, and the main sidewall spacers120are or comprise silicon nitride. Other materials are, however, amenable for one or any combination of the aforementioned spacers.

The silicide layers122are on the SG lines202to provide low resistance electrically coupling from the SG lines202to SG contact vias (not shown). Further, a contact etch stop layer (CESL)208is on the main sidewall spacers120and the source silicide layer122a, and the source contact via124aextends through the CESL208from a source line wire210ato the source silicide layer122a. The source line wire210ais in the interconnect dielectric layer134and may be or comprise, for example, metal and/or some other suitable conductive material(s). The CESL208may be or comprise, for example, silicon oxide, silicon nitride, some other suitable dielectric(s), or any combination of the foregoing.

With reference toFIG.2B, a cross-sectional view200B of some alternative embodiments of the source strap cell102ofFIG.2Ais provided in which main sidewall spacers120between the CG lines110have bottommost points at a same level as the floating gates116and/or the floating gate dielectric layers128.

With reference toFIG.2C, a cross-sectional view200C of some alternative embodiments of the source strap cell102ofFIG.2Ais provided in which the SG lines202are to sides of the trench isolation structure112. In other words, the SG lines202do not overlie the trench isolations structure112.

With reference toFIG.2D, a cross-sectional view200D of some alternative embodiments of the source strap cell102ofFIG.2Cis provided in which a common dielectric structure212surrounds and separates constituents of the source strap cell102. Among other things, the common dielectric structure212surrounds and separates the floating gates116, the CG lines110, the silicide layers122, the CESL208, sidewall spacers214, and gate dielectric layers216. Further, the common dielectric structure212defines constituents of the source strap cell102. Among other things, the common dielectric structure212defines the trench isolation structure112and the floating gate dielectric layers128. The common dielectric structure212may, for example, be or comprise silicon oxide and/or some other suitable dielectric(s). The sidewall spacers214and/or the gate dielectric layers216may, for example, be or comprise silicon nitride and/or some other suitable dielectric(s).

While not labeled to simplifyFIG.2D, it is to be appreciated that the common dielectric structure212and the sidewall spacers214may, for example, collectively define the CG sidewall spacers130ofFIG.2C. For example, the common dielectric structure212and the sidewall spacers214may collectively define ONO films corresponding to the CG sidewall spacers130ofFIG.2C. Further, the common dielectric structure212and the gate dielectric layers216may, for example, collectively define the CG dielectric layers126ofFIG.2C. For example, the common dielectric structure212and the gate dielectric layers216may collectively define ONO films corresponding to the CG dielectric layers126ofFIG.2C.

With reference toFIG.3A, an expanded cross-sectional view300A of some embodiments of the source strap cell102ofFIG.1Bis provided in which the contact vias124extend respectively to the silicide layers122respectively from wires210. Further, the CESL208is on the main sidewall spacers120, and the source contact via124aextends through the CESL208. The wires210are in the interconnect dielectric layer134and may be or comprise, for example, metal and/or some other suitable conductive material(s).

With reference toFIG.3B, a cross-sectional view300B of some alternative embodiments of the source strap cell102ofFIG.3Ais provided in which the common dielectric structure212surrounds and separates constituents of the source strap cell102. Among other things, the common dielectric structure212surrounds and separates the EG line108, the silicide layers122, the main sidewall spacers120, and the CESL208. Further, the common dielectric structure212defines constituents of the source strap cell102. Among other things, the common dielectric structure212defines the source dielectric layer114.

With reference toFIG.4, an expanded top layout400of some embodiments of the source strap cell102ofFIG.1Cis provided in which the SG lines202are laterally elongated in parallel with the CG lines110and the EG line108. Further, the SG lines202, the CG lines110, and the EG line108overlap with the trench isolation structure112and the active region104a, and the trench isolation structure112surrounds and demarcates the active region104a. Any one of the cross-sectional views100A,200A-200D ofFIGS.1A and2A-2Dmay, for example, be taken along line A and/or any one of the cross-sectional views100B,300A,300B ofFIGS.1B,3A, and3Bmay, for example, be taken along line B.

With reference toFIG.5, a cross-sectional view500of some embodiments of a memory device comprising a source strap cell102and CG strap cells502is provided. The memory device may, for example, be or be part of an IC chip or some other suitable semiconductor structure. Further, the memory device may, for example, be an ESF3 memory device or some other suitable split gate flash memory device.

The source strap cell102and the CG strap cells502overlie a trench isolation structure112and an active region104aof a substrate104. Further, the source strap cell102and the CG strap cells502are defined in part by source lines106, EG lines108, CG lines110, and SG lines202that are elongated in parallel (not visible in the cross-sectional view500ofFIG.5). The source strap cell102is as illustrated and described inFIG.2A, but may, for example, alternatively be as illustrated and described in any one or combination ofFIGS.1A-1C,2B-2D,3A,3B, and4or alternatively be as any other suitable source strap cell.

The source lines106respectively border the CG lines110on first sides of the CG lines110, and the EG lines108respectively overlie the source lines106while remaining spaced from the source line106by source dielectric layers114. Note that the source dielectric layer114of the source strap cell102is partially removed, whereas the source dielectric layers114of the CG strap cells502are complete. Further, the SG lines202respectively border the CG lines110on second sides of the CG lines110, and the CG lines110respectively overlie the floating gates116. The EG line of the source strap cell102(not visible) and the source dielectric layer114of the source strap cell102have a first break118at the source strap cell102, and the SG lines (not visible) of the CG strap cell502have a second break504at the CG strap cells502.

As seen hereafter, the source strap cell102may, for example, be formed by an enhanced method for opening the source line106. During the enhanced method, a first photolithography/etching process clears the EG line of the source strap cell102at the first break118while simultaneously clearing the SG lines of the CG strap cells502at the second break504. Further, instead of using a second photolithography/etching process specifically for clearing the source dielectric layer114at the first break118, the enhanced method thins the source dielectric layer114of the source strap cell102during the first photolithography/etching process and etches through a remainder of the source dielectric layer while patterning a RPD layer (not shown) used during formation of the silicide layer122at the first break118. As such, the first photolithography/etching process is extended.

Because the first photolithography/etching process is extended, and the first photolithography/etching process is performed on the SG lines202of the CG strap cells502, the first photolithography/etching process extends into the substrate104and the trench isolation structure112at the CG strap cell502. This, in turn, forms a recess506that has a depth D, which is measured from a top surface of the substrate104. In some embodiments, the depth D is greater than about 50 angstroms or greater than about 100 angstroms and/or is less than about 200 angstroms, less than about 250 angstroms, or less than about 300 angstroms. Other suitable values are, however, amenable. If the depth D is too large (e.g., greater than about 300 angstroms or some other suitable value), metal may become trapped in the recess506. Such trapped metal may cause contamination of process tools, undesired electrical shorting, or other suitable challenges. If the depth D is too small (e.g., less than about 50 angstroms or some other suitable value), the source dielectric layer114of the source strap cell102may be insufficiently thinned and the patterning of the RPD layer may be unable to etch through the remainder of the source dielectric layer. As such, the contact via124of the source strap cell102may fail to electrically couple to the source line106of the source strap cell102.

With continued reference toFIG.5, the CG lines110are separated respectively from the trench isolation structure112and the floating gates116by corresponding CG dielectric layers126. Further, the floating gates116are separated from the substrate104by corresponding floating gate dielectric layers128, and the SG lines202are separated from the substrate104by corresponding SG dielectric layers204. The CG lines110are separated from the EG lines108and the SG lines202by corresponding CG sidewall spacers130. The CG lines110are further separated from the EG lines108by corresponding EG tunnel dielectric layers132and are further separated from the SG lines202by corresponding SG sidewall spacers206. The CG sidewall spacers130are on sidewalls of the CG lines110, the EG tunnel dielectric layers132are on sidewalls of the floating gates116and sidewalls of the EG lines108, and the SG sidewall spacers206are on sidewalls of the SG lines202.

A CESL208lines outer sidewalls of the source strap cell102and the CG strap cells502, and main sidewall spacers120separate the CESL208respectively from the outer sidewalls. Silicide layers122are respectively on the SG lines202, the EG lines108, and the source line106of the source strap cell102. A source line wire210aand a source contact via124aoverlie the silicide layer122of the source strap cell102, and the source contact via124aextends from the source line wire210ato the silicide layer122of the source strap cell102. An interconnect dielectric layer134covers the source strap cell102and the CG strap cells502. Further, the interconnect dielectric layer134fills the first and second breaks118,504and surrounds the source line wire210aand the source contact via124a.

With reference toFIGS.6A and6B, various cross-sectional views600A,600B of some alternative embodiments of the GC strap cells502ofFIG.5are provided in which the recess506is substantially defined by the substrate104and the trench isolation structure112is substantially localized under the CG lines110. InFIG.6A, the trench isolation structure112neighbors the second break504and the recess506. InFIG.6B, the trench isolation structure112neighbors the EG lines108.

With reference toFIG.7, a top layout700of some embodiments of the GC strap cells502ofFIG.5is provided. The GC strap cell502ofFIG.5may, for example, be taken along line C but other suitable locations are, however, amenable. In alternative embodiments, the GC strap cells502in any one ofFIGS.6A and6Bmay, for example, be taken along line C by modifying the top layout of the trench isolation structure112and the top layout of the active region104a. The CG lines110, the EG lines108, and the SG lines202are laterally elongated in parallel and overlap with the trench isolation structure112and the active region104a. Further, one of the CG lines110has a pad110pat the break504, the recess506wraps around the pad110p, and a contact via124extends from the pad110pto electrically couple the pad110pto a metal line (not shown). In some embodiments, the recess506is U or C shaped. In alternative embodiments, the recess506has some other suitable shape.

With reference toFIG.8, a schematic top diagram800of some embodiments of a memory device comprising a memory array is provided in which the source strap cell102ofFIG.5and the GC strap cell502ofFIG.5are arranged. The memory array comprises a plurality of cells in a plurality of rows and a plurality of columns. The rows are respectively labeled Rxthrough Rx+7and the columns are respectively labeled Cmthrough Cm+2, Cnthrough Cn+2, Cothrough Co+2, and Cpthrough Cp+2. The subscripts of the row and column labels identify corresponding row and column numbers. Further, x is an integer variable representing a row number whereas m, n, o, and p are integer variables representing column numbers.

The plurality of cells comprises a plurality of source strap cells102, a plurality of CG strap cells502, and a plurality of memory cells802repeating along each of the rows. In some embodiments, the plurality of cells further comprises SG strap cells and/or other types of strap cells that are not shown. The source strap cells102electrically couple source lines (not shown) and EG lines (not shown) to a corresponding source strap line804and a corresponding EG strap line806. As such, the source strap cells102may, for example, also be known as source/erase gate (SEG) strap cells. The CG strap cells502electrically couple CG lines (not shown) to corresponding CG strap lines808. The CG lines, the EG lines, and the source lines extend along the rows and partially define the plurality of cells. The memory cells802store individual bits of data and may, for example, be ESF3 memory cells, split gate flash memory cells, or some other suitable memory cells. The source strap cells102may, for example, be as in any one or combination ofFIGS.1A-1C,2A-2D,3A,3B,4, and5and/or the GC strap cells502may, for example, be as in any one or combination of theFIGS.5,6A,6B, and7.

An interconnect structure interconnects the plurality of cells and comprises a plurality of wires210and a plurality of vias810. Note that the wires210and the vias810are only labeled in the legend below the memory array. The wires210are grouped into a plurality of wire levels and the vias810are grouped into a plurality of via levels. A level corresponds to an elevation above the memory array when the memory device is viewed in cross section. The plurality of wire levels comprises a first wire level M1, a second wire level M2, a third wire level M3, and a fourth wire level M4. The wire levels are schematically illustrated by thicknesses of the wires210and elevation above the memory array increases with wire thickness. The plurality of via levels comprises a contact via level CO (e.g., a zero via level), a first via level V1, a second via level V2, and a third via level V3. The via levels are schematically illustrated by shape and/or color. For example, a black circle corresponds to contact vias124in the contact via level CO, whereas a white square corresponds to vias in the second via level V2.

Vias in the contact via level CO extend from the cells to wires in the first wire level M1, and vias in the first via level V1extend from wires in the first wire level M1to wires in the second wire level M2. Further, vias in the second via level V2extend from wires in the second wire level M2to wires in the third wire level M3, and vias in the third via level V3extend from wires in the third wire level M3to wires in the fourth wire level M4. Note that where vias at different levels directly overlap, the intervening wires are not shown.

The plurality of wires210comprises a plurality of bit lines812, a plurality of source shunt wires814, and a plurality of EG shunt wire816in the first wire level M1. The bit lines812extend along columns (e.g., columns Cm, Cm+2, Cn+2, Co, etc.) at which the memory cells802are located and electrically couple to memory cells in corresponding columns through vias in the contact via level CO. The source and EG shunt wires814,816extend along the column (e.g., columns Cm+1and Co+1) at which the source strap cells102are located and electrically couple respectively to source lines (not shown) and EGs (not shown) at the source strap cells102through contact vias in the contact via level CO.

Additionally, the plurality of wires210comprises the source strap line804, the EG strap line806, and the CG strap lines808. The source and EG strap lines804,806are in the fourth wire level M4and electrically couple respectively to the source and EG shunt wires814,816through vias in the first, second, and third via levels V1, V2, and V3. The CG strap lines808are in the third wire level M3and electrically couple to CG lines (not shown) in corresponding rows at the CG strap cells502through contact vias in the contact via level CO and the first and second via levels V1, V2.

WhileFIG.8illustrates the various strap lines and the various shunt wires as being in certain wire levels, some or all of the strap lines and/or some or all of the shunt wires may be in different wire levels in alternative embodiments. For example, the CG strap lines808may be in the second wire level M2in alternative embodiments. As another example, the EG strap line806may be in the fourth wire level M4and the source strap line804may be in a fifth wire level (not shown), or vice versa, in alternative embodiments.

With reference toFIG.9, a top layout900of some embodiments of a portion of the memory array ofFIG.8is provided. The top layout900may, for example, be taken within box E inFIG.8, but other suitable locations are amenable. A plurality of EG lines108, a plurality of CG lines110, and a plurality of SG lines202are laterally elongated in parallel and partially define a plurality of cells in a plurality of rows and a plurality of columns. The rows are respectively labeled Rythrough Ry+3and the columns are respectively labeled Cqthrough Cq+7. The subscripts of the row and column labels identify corresponding row and column numbers. Further, y is an integer variable representing a row number whereas q is an integer variable representing a column number.

The plurality of cells comprises a plurality of source strap cells102, a plurality of CG strap cells502, and a plurality of memory cells802. The plurality of cells overlap an active region104aand a trench isolation structure112surrounding and demarcating the active region104a. Further, the plurality of cells is electrically coupled to corresponding wires (not shown; see, e.g.,FIG.8) through corresponding contact vias124. The source strap cells102may, for example, be as in any one or combination ofFIGS.1A-1C,2A-2D,3A,3B,4, and5. Any one ofFIGS.1A and2A-2Dmay, for example, be taken along line A and/or any one ofFIGS.1B,3A, and3B may, for example, be taken along line B. Further, the source strap cell102ofFIG.5may, for example, be taken along line A. The CG strap cells502may, for example, be as in any one or combination ofFIGS.5,6A,6B, and7and/or any one ofFIGS.6A and6Bmay, for example, be taken along line C. Further, the CG strap cells502ofFIG.5may, for example, be taken along line C.

With reference toFIGS.10-13and16-24, a series of cross-sectional views1000-1300,1600-2400of some embodiments of a method for forming a memory device comprising a source strap cell and CG strap cells according to aspects of the present disclosure is provided. The method is employed to form the memory device ofFIG.5but may, for example, alternatively be employed to form the memory device in any one or combination ofFIGS.1A-1C,2A-2D,3A,3B,4,6A,6B, and7-9or to form some other suitable memory device.

As illustrated by the cross-sectional view1000ofFIG.10, a source strap cell102and CG strap cells502are partially formed on a trench isolation structure112and an active region104aof a substrate104. The trench isolation structure112surrounds and demarcates the active region104a. The source strap cell102and the CG strap cells502are defined in part by source lines106, EG lines108, CG lines110, and SG lines202that are elongated in parallel (not visible in the cross-sectional view1000). In some embodiments, the source strap cell102has the top layout atFIG.4, less the contact vias124and the break118, such that the EG line108of the source strap cell102is continuous. In some embodiments, the CG strap cells502have the top layout atFIG.7, less the contact via124and the break504, such that the SG lines202of the CG strap cells502are continuous. Other suitable top layouts are, however, amenable for the source strap cell102and/or the CG strap cells502.

The SG lines202respectively border the CG lines110on first sides of the CG lines110, and the CG lines110respectively overlie floating gates116. Further, the source lines106respectively border the CG lines110on second sides of the CG lines110, and the EG lines108respectively overlie the source lines106while remaining spaced from the source lines106by source dielectric layers114. The source dielectric layers114have a ball or oval shaped cross-sectional profile, but other profiles are amenable. In some embodiments, an individual height Hdof the source dielectric layers114is about 300-500 angstroms, about 300-400 angstroms, about 400-500 angstroms, or some other suitable values. In some embodiments, an individual width Wdof the source dielectric layers114is about 500-800 angstroms, about 500-650 angstroms, about 650-800 angstroms, or some other suitable values.

The CG lines110are separated from the trench isolation structure112and the floating gates116by corresponding CG dielectric layers126, and the floating gates116are separated from the substrate104by corresponding floating gate dielectric layers128. Further, the SG lines202are separated from the substrate104by corresponding SG dielectric layers204. The CG lines110are separated from the EG lines108and the SG lines202by corresponding CG sidewall spacers130. The CG lines110are further separated from the EG lines108by corresponding EG tunnel dielectric layers132and are further separated from the SG lines202by corresponding SG sidewall spacers206.

CG hard masks1002respectively cover the CG lines110, and SG hard masks1004respectively cover the SG lines202. Further, EG hard masks1006respectively cover the EG lines108. The EG hard masks1006and/or the SG hard masks1004may, for example, be or comprise silicon nitride and/or some other suitable dielectric(s). The CG hard masks1002may, for example, be or comprise silicon oxide, silicon nitride, some other suitable dielectric(s), or any combination of the foregoing. In some embodiments, as illustrated, the CG hard masks1002are or comprise nitride-oxide-nitride (NON) films.

As illustrated by the cross-sectional view1100ofFIG.11, a first mask1102is formed partially covering the source strap cell102and the CG strap cells502. In some embodiments, the first mask1102is or comprises photoresist and/or some other suitable mask material(s). Further, in some embodiments, the first mask1102is formed by photolithography and/or some other suitable process(es) for forming the first mask1102.

Also illustrated by the cross-sectional view1100ofFIG.11, a sacrificial layer1104is formed filling a gap (see, e.g.,FIG.10) between the CG strap cells502. The sacrificial layer1104may, for example, be or comprise bottom antireflective coating (BARC) and/or some other suitable sacrificial material(s). In some embodiments, the sacrificial layer1104is formed of a material that is flowable and self-levels under the force of gravity so a top surface of the sacrificial layer1104is flat or substantially flat. A process for forming the sacrificial layer1104may, for example, comprise depositing the sacrificial layer1104by spin on coating and subsequently etching back the sacrificial layer1104until a top surface of the sacrificial layer1104is about even with top surfaces of the CG hard masks1002. Other suitable processes are, however, amenable for forming the sacrificial layer1104.

As illustrated by the cross-sectional view1200ofFIG.12, a first etch is performed into the source and CG strap cells102,502with the first mask1102in place. The first etch may, for example, comprise or be performed by an anisotropic etch, a dry etch, some other suitable type of etch, or any combination of the foregoing.

The first etch stops on the source dielectric layer114of the source strap cell102and further stops on a portion of the substrate104between the CG strap cells502. Further, in some embodiments, the first etch stops on a portion of the trench isolation structure112between the CG strap cells502. In some embodiments, the source dielectric layers114and the trench isolation structure112are or comprise silicon oxide and/or are or comprise the same material. In some embodiments, an etchant employed by the first etch has high selectivity (e.g., a high etch rate) for material of the EG and SG lines108,202relative to material of the source dielectric layers114and/or material of the substrate104.

The first etch forms: 1) a first opening1202through the EG line108of the source strap cell102(see, e.g.,FIG.11); and 2) a second opening1204through the SG lines202of the CG strap cells502(see, e.g.,FIG.11). Further, the first etch fully or substantially removes the sacrificial layer1104(see, e.g.,FIG.11) and partially removes some of the dielectric layers in the first and second openings1202,1204. For example, the SG sidewall spacers206of the CG strap cells502are thinned or partially removed.

The sacrificial layer1104protects the substrate104between the CG strap cells502so the substrate104is not exposed to etchants for an entire duration of the first etch. If the substrate104was exposed to the etchants, a deep recess may form which could trap metal. Such trapped metal is difficult to remove and may hence cause contamination of process tools, undesired electrical shorting, or other suitable challenges.

As illustrated by the cross-sectional view1300ofFIG.13, a second etch is performed with the first mask1102in place. The second etch is performed into the source dielectric layer114of the source strap cell102and an exposed portion of the substrate104between the CG strap cells502. In some embodiments, the second etch is also performed into an exposed portion of the trench isolation structure112between the CG strap cells502. In some embodiments, an etchant employed by the second etch is different than that employed by the first etch and/or has high selectivity (e.g., a high etch rate) for material of the source dielectric layers114and/or material of the substrate104relative to surrounding structure. As with the first etch, the second etch may, for example, comprise or be performed by an anisotropic etch, a dry etch, some other suitable type of etch, or any combination of the foregoing.

In some embodiments, the first and second etches are performed in situ. In other words, the first and second etches are performed within a common process chamber, such that the substrate104is within the common process chamber continuously from a beginning of the first etch to an end of the second etch. In alternative embodiments, the first and second embodiments are performed in different process chambers.

The second etch thins exposed portions of the CG hard masks1002. In some embodiments in which the CG hard masks1002are or comprise NON films, the second etch stops on oxide layers of the NON films before reaching bottom nitride layers of the NON films. The second etch thins the source dielectric layer114of the source strap cell102. Hence, the source dielectric layer114of the source strap cell102has a height Hdthat is less than before the thinning. Further, the second etch flattens the source dielectric layer114of the source strap cell102so a top surface of the source dielectric layer is flatter than before the second etch. For example, a difference between a highest point on the top surface and a lowest point on the top surface may be less than before the second etch. The second etch extends into the substrate104and the trench isolation structure112to form a recess506between the CG strap cells502. The recess506has a depth D, which is measured from a top surface of the substrate104, and may, for example, have the top layout inFIG.7. For example, the recess506may have a C- or U-shaped top layout. Other suitable top layouts are, however, amenable.

In some embodiments, the height Hdis about 300-500 angstroms, about 300-400 angstroms, about 400-500 angstroms, or some other suitable values before the second etch and/or is about 100-200 angstroms, about 100-150 angstroms, about 150-200 angstroms, or some other suitable values after the etch. If the height Hdafter the second etch is too small (e.g., less than about 100 angstroms or some other suitable value), the depth D may be too large. As discussed below, this may lead to trapped metal. If the height Hdafter the second etch is too large (e.g., greater than about 200 angstroms or some other suitable value), a subsequently described RPD etch may be unable to extend the first opening1202through the source dielectric layer114of the source strap cell102. This may, in turn, degrade a process window for forming silicide and/or a contact via on the source dielectric layer114of the source strap cell102.

In some embodiments, the depth D is greater than about 50 angstroms or greater than about 100 angstroms and/or is less than about 200 angstroms, less than about 250 angstroms, or less than about 300 angstroms. Other suitable values are, however, amenable. If the depth D is too large (e.g., greater than about 300 angstroms or some other suitable value), metal may become trapped in the recess506. Such trapped metal may cause contamination of process tools, undesired electrical shorting, or other suitable challenges. If the depth D is too small (e.g., less than about 50 angstroms or some other suitable value), the source dielectric layer114of the source strap cell102may be insufficiently thinned at the first opening1202and the height Hdmay be too large (see above).

With reference toFIGS.14A and14B, cross-sectional views1400A,1400B of some alternative embodiments of the source strap cell102ofFIG.13are provided. InFIG.14A, the active region104aof the substrate104and the trench isolation structure112have different layouts, such that the SG lines202are substantially to sides of the trench isolation structure112. InFIG.14B, a common dielectric structure212surrounds and separates constituents of the source strap cell102. Among other things, the common dielectric structure212surrounds and separates the floating gates116, the CG lines110, sidewall spacers214, gate dielectric layers216, and hard masks1402. Further, the common dielectric structure212defines constituents of the source strap cell102. Among other things, the common dielectric structure212defines the source dielectric layer114and the trench isolation structure112. The hard masks1402may, for example, be or comprise silicon nitride and/or some other suitable dielectric(s).

With reference toFIGS.15A and15B, cross-sectional views1500A,1500B of some embodiments of the source strap cell102ofFIG.13are provided in a direction orthogonal to that of the cross-sectional view1300ofFIG.13. For example,FIGS.15A and15Bmay, for example, be in a X direction andFIG.13may be in Y direction. InFIG.15A, the EG line108is recessed relative to the EG hard mask1006and the source dielectric layer114is indented where uncovered by the EG hard mask1006and the first mask1102. InFIG.15B, corners are more rounded and surfaces are less rectilinear.

In some embodiments, the source strap cell102ofFIGS.15A and15Bare taken along line B in any one or combination ofFIGS.1C,4, and9, whereas the source strap cell102ofFIG.13is taken along line A in any one or combination ofFIGS.1C,4, and9. Further, in some embodiments, the cross-sectional views1500A,1500B ofFIGS.15A and15Balternatively correspond toFIG.14Aand/orFIG.14Binstead ofFIG.13.

Referring back toFIGS.10-13and16-24and the series of cross-sectional views1000-1300,1600-2400illustrated thereby, the first mask1102(see, e.g.,FIG.13) is removed at the cross-sectional view1600ofFIG.16. The removal may, for example, be performed by plasma ashing and/or some other suitable removal process.

Also illustrated by the cross-sectional view1600ofFIG.16, the source and CG strap cells102,502are thinned and top surfaces thereof are flattened until about even. This includes thinning the SG hard masks1004, the CG hard masks1002, and the EG hard mask1006and flatting top surfaces of the hard masks. In some embodiments, a process for performing the thinning and the flattening comprises: 1) depositing a sacrificial layer covering the source and CG strap cells102,502; 2) etching back the sacrificial layer in parallel with the source and CG strap cells102,502; and 3) removing the sacrificial layer. Other processes are, however, amenable. The sacrificial layer has a top surface that is flat or substantially flat and may, for example, be or comprise BARC and/or some other suitable sacrificial material(s). In some embodiments, the sacrificial layer is formed of a flowable material that self-levels under the force of gravity so the top surface of the sacrificial layer is flat or substantially flat. A process for forming the sacrificial layer may, for example, comprise depositing the sacrificial layer by spin on coating. Other processes are, however, amenable.

As illustrated by the cross-sectional view1700ofFIG.17, main sidewall spacers120are formed on outer sidewalls of the source and CG strap cells102,502and lining sidewalls of the source and CG strap cells102,502at the first and second openings1202,1204. In some embodiments, a process for forming the main sidewall spacers120comprises: 1) depositing a spacer layer covering the source and CG strap cells102,502and lining the sidewalls of the source and CG strap cells; and 2) performing an etch back into the spacer layer to remove horizontal, but not vertical, segments. Other processes are, however, amenable.

Because the source dielectric layer114of the source strap cell102is only thinned at the first opening1202, the main sidewall spacers120in the first opening1202overlie the source dielectric layer. In some embodiments, the main sidewall spacers120in the first opening1202have bottom surfaces elevated above a topmost point of the substrate104. Further, in some embodiments, the main sidewall spacers120in the first opening1202have bottom surfaces elevated above bottom surfaces respectively of the floating gates116and/or recessed relative to top surfaces respectively of the floating gates116. Because the main sidewall spacers120in the first opening1202overlie the source dielectric layer114of the source strap cell102, the main sidewall spacers have a height Hs1that is smaller than it would otherwise be if the first opening1202extended through the source dielectric layer before formation.

Because the recess506extends into the substrate104and the trench isolation structure112between the CG strap cells502, the main sidewall spacers120between the CG strap cells502also extend into the substrate104and the trench isolation structure112. Because the main sidewall spacers120between the CG strap cells502extend into the substrate104and the trench isolation structure112, the main sidewall spacers have a height Hs2that is larger than it would otherwise be if the recess506did not exist. As noted above, the recess506occurs because the second etch uses the first mask1102(see, e.g.,FIG.13).

As illustrated by the cross-sectional view1800ofFIG.18, a resist protect dielectric (RPD) layer1802is deposited covering the source and CG strap cells102,502and further lining sidewalls of the main sidewall spacers120. The RPD layer1802may, for example, be or comprise silicon oxide and may, for example, therefore also be a RPO layer. Alternatively, the RPD layer1802may, for example, be or comprise some other suitable dielectric(s).

As illustrated by the cross-sectional view1900ofFIG.19, a second mask1902is formed on the RPD layer1802. The second mask1902is formed with an opening overlying the source line106of the source strap cell102. While not visible, the second mask1902may, for example, also include additional openings. The openings of the second mask1902may, for example, define a silicide pattern for subsequently formed silicide. In some embodiments, the second mask1902is or comprises photoresist and/or some other suitable mask material(s). Further, in some embodiments, the second mask1902is formed by photolithography and/or some other suitable process(es) for forming the second mask1902.

Also illustrated by the cross-sectional view1900ofFIG.19, a third etch is performed into the RPD layer1802and the source dielectric layer114of the source strap cell102with the second mask1902in place. The third etch extends the first opening1202through the source dielectric layer114of the source strap cell102to expose the source line106of the source strap cell102. The third etch may, for example, comprise or be performed by an anisotropic etch, a dry etch, some other suitable type of etch, or any combination of the foregoing. In some embodiments, the RPD layer1802and the source dielectric layer114of the source strap cell102are or comprise the same dielectric material, such that the third etch employs a single etchant.

As seen above, the second etch (see, e.g.,FIG.13) thins the source dielectric layer114of the source strap cell102in the first opening1202, and then the third etch etches through the source dielectric layer, to extend the first opening1202to the source line106of the source strap cell102. The second etch uses the first mask1102(see, e.g.,FIG.13) of the first etch (see, e.g.,FIG.12), and the third etch uses the second mask1902(see, e.g.,FIG.19). This two-step process for exposing the source line106of the source strap cell102is to be contrasted with a single-step process that exposes the source line by a single photolithography/etching process with a third mask different than the first and second masks1102,1902.

Because the present disclosure uses the two-step process, instead of the single-step process, the method may use one less photomask than it would otherwise use. Because photomasks are costly to form and photolithography process tools are costly to use, one less photomask is a substantial cost savings. Additionally, because one less photomask may be used, the risk of errant photoresist on the source line106of the source strap cell102is reduced. This enlarges the process window (e.g., makes the process more resilient) for forming silicide and/or a contact via on the source line106of the source strap cell102. Too much scum on the source line106of the source strap cell102may prevent a silicide layer from fully forming on the source line, such that the silicide layer may be small. The small silicide layer may reduce the likelihood of the contact via fully landing on the silicide layer and may hence lead to a high resistance from the contact via to the source line. This high resistance may, in turn, shift operating parameters of the memory device out of specification and/or lead to low yields.

As noted above, the second etch thins the source dielectric layer114of the source strap cell102so the height Hd(see, e.g.,FIG.13) is about 100-200 angstroms, about 100-150 angstroms, about 150-200 angstroms, or some other suitable values after the etch. If the height Hdis too large (e.g., greater than about 200 angstroms or some other suitable value), the third etch may be unable to extend the first opening1202through the source dielectric layer114of the source strap cell102without damage to structure (not shown) elsewhere on the substrate104. For example, the third etch may also be employed to expose source/drain regions (not shown) elsewhere on the substrate104. The source/drain regions may not be covered by source/drain dielectric layers and may, instead, only be covered by the RPD layer1802. As such, extending the third etch through the source dielectric layer114of the source strap cell102may increase exposure of the source/drain regions to etchants during the third etch. This increased exposure may, in turn, damage the source/drain regions. If the height Hdis too large, the damage may be high and may hence shift operating parameters out of specification.

As illustrated by the cross-sectional view2000ofFIG.20, the second mask1902(see, e.g.,FIG.19) is removed and a source silicide layer122ais formed on the source line106of the source strap cell102. The removal may, for example, be performed by plasma ashing and/or some other suitable removal process. The source silicide layer122ais formed by a process that forms silicide on silicon semiconductor regions uncovered by the RPD layer1802, but not on silicon semiconductor regions covered by the RPD layer1802. The process may, for example, be a salicide process or some other suitable process for forming silicide.

As illustrated by the cross-sectional view2100ofFIG.21, the RPD layer1802(see, e.g.,FIG.20) is removed. The removal may, for example, be performed by an etching process or some other suitable etching process.

Also illustrated by the cross-sectional view2100ofFIG.21, the CG hard mask1002, the SG hard masks1004, and the EG hard masks1006are removed. In some embodiments, a process for performing the removal comprises: 1) depositing a sacrificial layer covering the source and CG strap cells102,502; 2) etching back the sacrificial layer in parallel with the source and CG strap cells102,502; and 3) removing the sacrificial layer. Other processes are, however, amenable. The sacrificial layer may, for example, be or comprise BARC and/or some other suitable sacrificial material(s). In some embodiments, the sacrificial layer is formed of a flowable material that self-levels under the force of gravity so the top surface of the sacrificial layer is flat or substantially flat. A process for forming the sacrificial layer may, for example, comprise depositing the sacrificial layer by spin on coating or some other suitable process.

As illustrated by the cross-sectional view2200ofFIG.22, a CESL208and a first interconnect dielectric layer134aare deposited covering the source and CG strap cells102,502and further filling the first and second openings1202,1204(see, e.g.,FIG.21). The first interconnect dielectric layer134amay be or comprise, for example, silicon oxide and/or some other suitable dielectric(s).

As illustrated by the cross-sectional view2300ofFIG.23, a planarization is performed into the CESL208and the first interconnect dielectric layer134a. The planarization persists until top surfaces respectively of the CESL208and the first interconnect dielectric layer134aare about even with top surfaces respectively of the SG lines202, the CG lines110, and the EG lines108. The planarization may, for example, be performed by a chemical mechanical polish or some other suitable planarization process.

Also illustrated by the cross-sectional view2300ofFIG.23, CG/EG silicide layers122bare formed on the CG lines110and the EG lines108. The CG/EG silicide layers122bmay, for example, be formed by a salicide process or some other suitable process.

As illustrated by the cross-sectional view2400ofFIG.24, a second interconnect dielectric layer134bis formed over the source and CG strap cells102,502and the first interconnect dielectric layer134a. The second interconnect dielectric layer134bmay be or comprise, for example, silicon oxide and/or some other suitable dielectric(s).

Also illustrated by the cross-sectional view2400ofFIG.24, a source line wire210aand a contact via124aare formed in the first and second interconnect dielectric layers134a,134b. The contact via124aextends from the source line wire210a, through the first and second interconnect dielectric layers134a,134band the CESL208, to the source silicide layer122a. The CESL208may, for example, serve as an etch stop while forming the contact via124a.

WhileFIGS.10-13and16-24are described with reference to various embodiments of a method, it will be appreciated that the structures shown inFIGS.10-13and16-24are not limited to the method but rather may stand alone separate of the method. WhileFIGS.10-13and16-24are described as a series of acts, it will be appreciated that the order of the acts may be altered in other embodiments. WhileFIGS.10-13and16-24illustrate and describe as a specific set of acts, some acts that are illustrated and/or described may be omitted in other embodiments. Further, acts that are not illustrated and/or described may be included in other embodiments.

With reference toFIG.25, a block diagram2500of some embodiments of the method ofFIGS.10-13and16-24is provided.

At2502, a source strap cell is partially formed, wherein the source strap cell is defined by a source line and an EG line overlying the source line. See, for example,FIG.10.

At2504, a pair of CG strap cells are partially formed, wherein the CG strap cells are respectively defined by CG lines and SG lines, and wherein the SG lines are between and respectively border the CG lines. See, for example,FIG.10.

At2506, a first etch is performed into the EG and SG lines with a first mask in place, wherein the first etch forms a first opening through the EG line at the source strap cell and forms a second opening through the SG lines at the CG strap cells, and wherein the first etch stops on a source dielectric layer underlying the EG line. See, for example,FIG.12.

At2508, a second etch is performed into the source dielectric layer with the first mask in place to thin the source dielectric layer at the first opening. See, for example,FIG.13.

At2510, main sidewall spacers are formed on sidewalls of the source and CG strap cells. See, for example,FIG.17.

At2512, an RPD layer is deposited covering the source and CG strap cells. See, for example,FIG.18.

At2514, a third etch is performed into the RPD layer with a second mask in place to pattern the RPD layer with a silicide pattern and to extend the first opening through the source dielectric layer to the source line. See, for example,FIG.19. Therefore, the source line is opened by a two-step process made up of the second and third etches. The two-step process is to be contrasted with a single-step process for opening the source line that uses a single photolithography/etching process with a mask different than the first and second masks.

At2516, a silicide layer is formed in the first opening and on the source line according to the silicide pattern.

At2518, a wire and a contact via are formed on the silicide layer. See, for example,FIG.24.

Because the method uses the two-step process, instead of the single-step process, to open the source line the method may use one less photomask than it would otherwise use. This may reduce costs. Additionally, because one less photomask may be used, the risk of errant photoresist on the source line may be reduced. This may enlarge the process window for forming the silicide layer and/or the contact via on the source line.

While the block diagram2500ofFIG.25is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

With reference toFIGS.26-32, a series of cross-sectional views2600-3200of some alternative embodiments of the method ofFIGS.10-13and16-24is provided in which the active region104aand the trench isolation structure112have different layouts. Further, the hard masks are fully removed before depositing the RPD layer.

As illustrated by the cross-sectional view2600ofFIG.26, a source strap cell102and CG strap cells502are partially formed on a trench isolation structure112and an active region104aof a substrate104. The trench isolation structure112and the active region104aare as described with regard toFIG.10, except that the trench isolation structure112and the active region104ahave different layouts than inFIG.10.

As illustrated by the cross-sectional view2700ofFIG.27, the acts illustrated and described with regard toFIGS.11and12are performed. The first mask1102is formed partially covering the source strap cell102and the CG strap cells502, and the sacrificial layer (not shown; see, e.g.,1104inFIG.11) is formed filling a gap (see, e.g.,FIG.26) between the CG strap cells502. Further, the first etch is performed into the source and CG strap cells102,502with the first mask1102in place to form the first and second openings1202,1204.

As illustrated by the cross-sectional view2800ofFIG.28, the second etch is performed into the source dielectric layer114of the source strap cell102and the exposed portion of the substrate104between the CG strap cells502. The second etch is as described with regard toFIG.13.

As illustrated by the cross-sectional view2900ofFIG.29, the acts illustrated and described with regard toFIGS.17and21are performed. The CG hard mask1002, the SG hard masks1004, and the EG hard masks1006are removed. Further, the main sidewall spacers120are formed on outer sidewalls of the source and CG strap cells102,502and lining sidewalls of the source and CG strap cells102,502in the first and second openings1202,1204.

As illustrated by the cross-sectional view3000ofFIG.30, the RPD layer1802is formed covering the source and CG strap cells102,502and further lining sidewalls of the main sidewall spacers120. The RPD layer1802is formed as described with regard toFIG.18.

As illustrated by the cross-sectional view3100ofFIG.31, the acts illustrated and described with regard toFIG.19are performed. The second mask1902is formed on the RPD layer1802. Further, the third etch is performed into the RPD layer1802and is extended into the source dielectric layer114of the source strap cell102to expose the source line106of the source strap cell102at the first opening1202.

As illustrated by the cross-sectional view3200ofFIG.32, the acts illustrated and described with regard toFIGS.20and22-24are performed. The second mask1902is removed and the source silicide layer122ais formed on the source line106of the source strap cell102. The CESL208and the first interconnect dielectric layer134aare deposited covering the source and CG strap cells102,502and further filling the first and second openings1202,1204(see, e.g.,FIG.13). The planarization is performed into the CESL208and the first interconnect dielectric layer134a, and the CG/EG silicide layers122bare formed on the CG lines110and the EG lines108. The second interconnect dielectric layer134bis formed over the source and CG strap cells102,502and the first interconnect dielectric layer134a. The source line wire210aand the contact via124aare formed.

WhileFIGS.26-32are described with reference to various embodiments of a method, it will be appreciated that the structures shown inFIGS.26-32are not limited to the method but rather may stand alone separate of the method. WhileFIGS.26-32are described as a series of acts, it will be appreciated that the order of the acts may be altered in other embodiments. WhileFIGS.26-32illustrate and describe as a specific set of acts, some acts that are illustrated and/or described may be omitted in other embodiments. Further, acts that are not illustrated and/or described may be included in other embodiments.

In some embodiments, the present disclosure provides an IC comprising: a memory device including: a substrate; an erase gate line, a control gate line, and a source line that are elongated in parallel in a first direction, wherein the erase gate line has a break separating the erase gate line into a pair of erase gate segments in the first direction, wherein the control gate line borders the erase gate line, and wherein the source line underlies the erase gate line in the substrate; a source dielectric layer between the erase gate line and the source line; a main sidewall spacer overlying the source dielectric layer and the source line at a center between the erase gate segments; and a contact via extending through the erase gate line and the source dielectric layer at the break and electrically coupling with the source line. In some embodiments, the contact via is spaced from the main sidewall spacer and the source dielectric layer. In some embodiments, the main sidewall spacer has a bottom surface at least partially elevated above a topmost point of the substrate. In some embodiments, the main sidewall spacer and the source dielectric layer define a common sidewall facing the contact via. In some embodiments, the memory device further includes an etch stop layer (ESL) having a U-shaped profile at the center between the erase gate segments, wherein the U-shaped profile laterally contacts the main sidewall spacer. In some embodiments, the memory device further includes: a floating gate underlying the control gate line; and a control gate sidewall spacer overlying the floating gate and separating the control gate line from the main sidewall spacer. In some embodiments, the memory device further includes a silicide layer between and directly contacting the contact via and the source line. In some embodiments, a width of the silicide layer is about 800-1100 angstroms.

In some embodiments, the present disclosure provides: a substrate; a memory array including a plurality of cells, wherein the plurality of cells includes a source strap cell and a pair of control gate strap cells; an erase gate line and a source line partially defining the source strap cell and elongated in parallel in a first direction, wherein the source line underlies the erase gate line, and wherein the erase gate line has a first break in the first direction; a first control gate line, a second control gate line, and a pair of select gate lines partially defining the control gate strap cells and elongated in parallel in the first direction, wherein the select gate lines are between and respectively border the first and second control gate lines and have a second break in the first direction, and wherein the first control gate line has a pad protruding towards the second control gate line at the second break; and a trench isolation structure underlying the first and second control gate lines; wherein a top surface of the substrate and has a recess with a U-shaped top layout that wraps around the pad at the second break. In some embodiments, the recess extends into the top surface of the substrate to a depth of about 100-300 angstroms. In some embodiments, contact vias extending respectively to the source line, the first control gate line, and the second control gate line respectively at the source strap cell and the control gate strap cells. In some embodiments, the first break separates the erase gate line into a pair of erase gate segments in the first direction, wherein the IC further includes: a source dielectric layer between the erase gate line and the source line; and a main sidewall spacer vertically separated from the substrate by the source dielectric layer proximate the first break and at a location spaced from and between the erase gate segments. In some embodiments, the location is equidistant from the erase gate segments.

In some embodiments, the present disclosure provides a method for forming a memory device, the method including: forming an erase gate line and a source line that are elongated in parallel, wherein the source line underlies the erase gate line in a substrate and is separated from the erase gate line by a source dielectric layer; performing a first etch into the erase gate line to form a first opening extending through the erase gate line, wherein the first etch is performed with a first mask in place and stops on the source dielectric layer; performing a second etch into the source dielectric layer through the first opening, and with the first mask in place, to thin the source dielectric layer at the first opening; performing a silicide process to form a silicide layer on the source line at the first opening, wherein the silicide process includes a third etch that extends the first opening through the source dielectric layer and exposes the source line; and forming a contact via extending through the erase gate line to the silicide layer. In some embodiments, the silicide process includes a RPO etch, wherein the RPO etch removes the source dielectric layer at the first opening. In some embodiments, a portion of the source dielectric layer at the first opening has an oval shaped profile before the second etch, wherein a top surface of the portion has a W shaped profile after the second etch. In some embodiments, the method further includes forming a pair of control gate lines and a pair of select gate lines that overlie the substrate and that are elongated in parallel with the erase gate line, wherein the select gate lines are between and respectively border the control gate lines, wherein one of the control gate lines has a pad protruding towards another one of the control gate lines, and wherein the first etch forms a second opening extending through the select gate lines at the pad. In some embodiments, the control gate lines are formed partially overlying a trench isolation structure extending into a top surface of the substrate, wherein the second etch forms a recess in the top surface of the substrate through the second opening, and wherein the recess wraps around the pad. In some embodiments, the method further includes: forming a pair of control gate lines overlying the substrate and elongated in parallel with the erase gate line, wherein the erase gate line is between and borders the control gate lines; and forming a main sidewall spacer between the control gate lines on sidewalls of the first opening, wherein the main sidewall spacer overlies the source dielectric layer at a center between discrete segments of the erase gate line that are separated by the first opening. In some embodiments, the silicide process includes: depositing a RPD layer covering the erase gate line and lining the first opening; performing a third etch into the RPD layer and the source dielectric layer with a second mask in place to extend the first opening through the RPD layer and the source dielectric layer; forming the silicide layer on the source line and with the RPD layer in place; and removing the RPD layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.