Patent ID: 12218043

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Like components in the drawings will be referred to as like reference numerals, and will not be repeatedly described.

FIG.1is a perspective view of an interposer100according to an embodiment of the inventive concept.FIG.2is a side cross-sectional view showing a cross section along a line II-II′ in the interposer100ofFIG.1.

Referring toFIGS.1and2, the interposer100may include an interposer substrate110having a first main surface110A and a second main surface110B that is an opposite surface of the first main surface110A.

The interposer substrate110may include a semiconductor material or an insulating material. In some embodiments of the inventive concept, the interposer substrate110may include silicon, germanium, silicon-germanium, gallium arsenide (GaAs), glass, ceramic, etc. The first main surface110A and the second main surface110B may be parallel to each other. The first main surface110A and the second main surface110B may be two opposing main surfaces of the interposer substrate110.

The interposer100may include first and second through-electrode structures131and133passing through the interposer substrate110. A pair of through-electrode structures, such as the first through-electrode structure131and the second through-electrode structure133may be connected to one common connection terminal structure140. In some embodiments of the inventive concept, the first through-electrode structure131and the second through-electrode structure133may form redundancy vias, and even when a defect occurs in any one of the first through-electrode structure131and the second through-electrode structure133, the other may operate, thereby preventing a defect in all of the interposer100. The present inventive concept is not limited thereto. In some embodiment, the number of through-electrode structures connected to a common connection terminal structure140may be three or more.

The connection terminal structure140may be provided for electrical connection with an external device, e.g., a printed circuit board, and may be provided on the first main surface110A. The connection terminal structure140may include a solder ball.

Each of the through-electrode structures131and133may be electrically connected with a connection pad120on the second main surface110B such that another semiconductor device may be mounted on the second main surface110B. A first region R1on which a first semiconductor device is to be mounted and a second region R2on which a second semiconductor device is to be mounted are indicated as virtual lines inFIG.1. For the simplicity of drawings, the interposer100has two mounting regions R1and R2with the same area. The present inventive concept, however, is not limited thereto. In some embodiments, the interposer100may include three or more mounting regions. Those mounting regions may have various areas and be arranged in various manners.

FIG.3is a partial enlarged view of a portion indicated by III inFIG.2.

Referring toFIGS.2and3, each of the first through-electrode structure131and the second through-electrode structure133may protrude from the first main surface110A through the first main surface110A of each interposer substrate110. For convenience of illustration, inFIG.2, protrusion of the first through-electrode structure131and the second through-electrode structure133from the first main surface110A is not illustrated in detail.

The first through-electrode structure131may be arranged in a first via hole131h, and may include a first core conductor131a, a first barrier film131b, and a first via dielectric film131d. The second through-electrode structure133may be arranged in a second via hole133h, and may include a second core conductor133a, a second barrier film133b, and a second via dielectric film133d.

Each of the first core conductor131aand the second core conductor133amay include one or more selected from, for example, aluminum (Al), gold (Au), beryllium (Be), bismuth (Bi), cobalt (Co), copper (Cu), hafnium (Hf), indium (In), magnesium (Mg), manganese (Mn), molybdenum (Mo), nickel (Ni), lead (Pb), palladium (Pd), white gold (Pt), rhodium (Rh), rhenium (Re), ruthenium (Ru), tin (Sn), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), zinc (Zn), and zirconium (Zr).

The first barrier film131band the second barrier film133bmay contact sidewalls of the first core conductor131aand the second core conductor133a, and surround the first core conductor131aand the second core conductor133ain a side direction. For example, the first barrier film131band the second barrier film133bmay contact sidewalls of the first core conductor131aand the second core conductor133arespectively, and surround the sidewalls of the first core conductor131aand the second core conductor133arespectively. In some embodiment, the first barrier film131band the first core conductor131amay be concentric in a top down view. In some embodiment, the second barrier film133band the second core conductor133amay be concentric in the top down view. The first barrier film131band the second barrier film133bmay be conductor films having a relatively low wiring resistance. For example, the first barrier film131band the second barrier film133beach may be a single film or a multi-layered film including at least one selected from among W, WN, WC, Ti, TiN, Ta, TaN, Ru, Co, Mn, WN, Ni, or NiB. For example, the first barrier film131band the second barrier film133beach may be a multi-layered film including TaN/W, TiN/W, or WN/W. In some embodiments of the inventive concept, each of the first barrier film131band the second barrier film133bmay have a thickness between about 50 Å and about 1000 Å. Terms such as “about” or “approximately” may reflect amounts, sizes, orientations, or layouts that vary, due to a process variation, only in a small relative manner, and/or in a way that does not significantly alter the operation, functionality, or structure of certain elements. For example, a range from “about 0.1 to about 1” may encompass a range such as a 0%-5% deviation around 0.1 and a 0% to 5% deviation around1, especially if such deviation maintains the same effect as the listed range. The term “contact,” as used herein, refers to a direct connection (i.e., touching) unless the context indicates otherwise.

In some embodiments of the inventive concept, the first barrier film131band the second barrier film133bmay have an approximately constant thickness in a longitudinal direction of the first through-electrode structure131and in a longitudinal direction of the second through-electrode structure133, respectively. In some embodiments of the inventive concept, the first barrier film131band the second barrier film133bmay be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

The first via dielectric film131dand the second via dielectric film133delectrically insulate the first core conductor131aand the second core conductor133afrom the interposer substrate110. The first via dielectric film131dand the second via dielectric film133dmay include an oxide film, a nitride film, a carbide film, a polymer, or a combination thereof. In some embodiments of the inventive concept, the first via dielectric film131dand the second via dielectric film133dmay be formed by CVD. In some embodiments of the inventive concept, each of the first via dielectric film131dand the second via dielectric film133dmay have a thickness between about 500 Å and about 2500 Å.

The first through-electrode structure131and the second through-electrode structure133may extend by a certain distance beyond the first main surface110A. The first through-electrode structure131and the second through-electrode structure133may protrude by a predetermined distance between several μm and several tens of μm, e.g., between about 3 μm and about 20 μm, beyond the first main surface110A.

A passivation layer150may cover the first main surface110A. The passivation layer150may surround protruding portions of the first through-electrode structure131and the second through-electrode structure133, which protrude beyond the first main surface110A, in a side direction. For example, the passivation layer150may surround sidewalls of the protruding portions of the first through-electrode structure131and the second through-electrode structure133.

The passivation layer150may include a first passivation layer (i.e., a lower passivation layer)151and a second passivation layer (i.e., an upper passivation layer)153. Each of the first passivation layer151and the second passivation layer153may be formed of an insulating film, for example, a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. In some embodiments, the first passivation layer151and the second passivation layer153may be formed of different kinds of insulating films or have the same kind of an insulating film. In some embodiments of the inventive concept, the first passivation layer151may be a silicon oxide film, and the second passivation layer153may be a silicon nitride film or a silicon oxynitride film. In some embodiments, the first passivation layer151may be a tetraethyl orthosilicate (TEOS) film, a high density plasma (HDP) oxide film, a boro-phospho-silicate glass (BPSG) oxide film, or a flowable chemical vapor deposition (FCVD) oxide film, and the second passivation layer153may be a silicon nitride or a silicon oxynitride.

The first passivation layer151may have a thickness between about 1.0 μm and about 3.0 μm, between about 1.2 μm and about 2.5 μm, between about 1.4 μm and about 2.2 μm, between about 1.5 μm and about 2.1 μm, or between about 1.6 μm and about 2.0 μm. The first passivation layer151may also have a Young's modulus between about 60 GPa and about 80 GPa, between about 65 GPa and about 75 GPa, or between about 68 GPa and about 72 GPa.

The second passivation layer153may have a thickness between about 0.35 μm and about 0.75 μm, between about 0.40 μm and about 0.70 μm, between about 0.45 μm and about 0.65 μm, between about 0.48 μm and about 0.62 μm, or between about 0.50 μm and about 0.60 μm. The second passivation layer153may also have a Young's modulus between about 100 GPa and about 160 GPa, between about 120 GPa and about 140 GPa, or between about 125 GPa and about 135 GPa.

The first passivation layer151may be formed to contact the first main surface110A. The first passivation layer151may cover a sidewall of the first through-electrode structure131and may be in contact with the sidewall. For example, the first passivation layer151may cover a sidewall of the protruding portion of the first through-electrode structure131and may be in contact with the sidewall of the protruding portion. The second passivation layer153may extend horizontally along the first main surface110A, with the first passivation layer151between the second passivation layer153and the first main surface110A. The second passivation layer153may extend vertically along the protruding portion of the first through-electrode structure131, with the first passivation layer151between the second passivation layer153and the protruding portion of the first through-electrode structure131. For the brevity of description, the first passivation layer151is described above with reference to the first through-electrode structure131. The same description of the first passivation layer151may apply to the second through-electrode structure133.

Top ends of the first passivation layer151and the second passivation layer153, which surround the sidewall of the first through-electrode structure131, may form a first top surface156p_1. Top ends of the first passivation layer151and the second passivation layer153, which surround a sidewall of the second through-electrode structure133, may form a second top surface156p_2. In some embodiments of the inventive concept, a top surface of the first through-electrode structure131may be substantially coplanar with the first top surface156p_1. In some embodiments of the inventive concept, a top surface of the second through-electrode structure133may be substantially coplanar with the second top surface156p_2.

A photosensitive polymer layer160may be provided on the passivation layer150. The photosensitive polymer layer160may include a material to which a photolithography process is applicable, for example, a photoimageable dielectric (PID) material. The PID material may include, for example, a polyimide-based photosensitive polymer, a novolac-based photosensitive polymer, polybenzoxazole, silicone-based polymer, acrylate-based polymer, or epoxy-based polymer.

The photosensitive polymer layer160may fill a space between the two passivation layers151and153that respectively surround, in a side direction, the first through-electrode structure131and the second through-electrode structure133that protrude from and extend upward from the first main surface110A. For example, the photosensitive polymer layer160may be arranged between the passivation layer surrounding the first through-electrode structure131in the side direction and the passivation layer surrounding the second through-electrode structure133in the side direction.

In some embodiments of the inventive concept, a top surface of the photosensitive polymer layer160may be arranged substantially coplanar with top surfaces of the first through-electrode structure131and the second through-electrode structure133. In some embodiments of the inventive concept, a top surface of the photosensitive polymer layer160may be arranged substantially coplanar with top surfaces of the first top surface156_1and the second top surface156_2.

The connection terminal structure140may be electrically connected to and in contact with the first through-electrode structure131and the second through-electrode structure133. The connection terminal structure140may include a seed metal layer145that contacts both the first through-electrode structure131and the second through-electrode structure133, a first conductor layer141formed on the seed metal layer145, and a solder metal layer143provided on the first conductor layer141. In some embodiments, the solder metal layer143may be referred to as a solder ball.

The seed metal layer145may include, for example, titanium (Ti), copper (Cu), chromium (Cr), tungsten (W), nickel (Ni), aluminum (Al), palladium (Pd), gold (Au), or an alloy thereof. The seed metal layer145may be formed by, for example, PVD such as sputtering. The seed metal layer145may have a thickness between about 1 μm and about 20 μm, between about 3 μm and about 15 μm, or between about 4 μm and about 10 μm.

The first conductor layer141formed on the seed metal layer145may be, but not limited to, metals such as copper (Cu), tungsten (W), titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), chromium (Cr), aluminum (Al), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), etc., alloys thereof, or metal nitrides. The first conductor layer141may have a thickness between about 10 μm and about 100 μm, between about 15 μm and about 80 μm, or between about 20 μm and about 60 μm.

A solder metal layer143may be provided on the first conductor layer141. The solder metal layer143may be an alloy including silver (Ag), copper (Cu), palladium (Pd), aluminum (Al), and silicon (Si) with tin (Sn) as a main component. Herein, the ‘main component’ may refer to a component of which a weight percentage exceeds 50% of a total weight of the alloy.

A bottom surface of the seed metal layer145may contact the top surface of the photosensitive polymer layer160. For example, the seed metal layer145may contact a portion of the photosensitive polymer layer160between the first through-electrode structure131and the second through-electrode structure133that contact the seed metal layer145. For example, the bottom surface of the seed metal layer145may be substantially coplanar with a top surface of the portion of the photosensitive polymer layer160arranged under the seed metal layer145.

In some embodiments of the inventive concept, an alignment key170may be further provided adjacent to the first through-electrode structure131. The alignment key170may have a shape of a recess passing through the photosensitive polymer layer160. In some embodiments of the inventive concept, the alignment key170may have a shape of a groove that passes through the photosensitive polymer layer160and extends by a certain length in a direction parallel to the first main surface110A.

In some embodiments of the inventive concept, the alignment key170may pass through the photosensitive polymer layer160and at least partially pass through the passivation layer150. In some embodiments of the inventive concept, the alignment key170may completely pass through the passivation layer150such that the first main surface110A is exposed.

FIG.4is a partial detailed view of a portion indicated by IV inFIG.3.

Referring toFIG.4, a sidewall170SW of the alignment key170may be inclined at an acute angle with respect to the first main surface110A. An angle α of the sidewall170SW with respect to the first main surface110A may be an angle between about 80 degrees and about 88 degrees or between about 83 degrees and about 87 degrees. In some embodiments of the inventive concept, the sidewall170SW may be formed by anisotropic etching as will be described below. Since a traveling direction of some ions or plasma used in anisotropic etching may have a distribution around a perpendicular direction with respect to the first main surface110A, the inclination of the sidewall170SW may not be a completely right angle with respect to the first main surface110A.

In some embodiments, the sidewall170SW may partially have a curved surface. For example, the sidewall170SW may be largely a plane in a portion corresponding to the photosensitive polymer layer160, but may be a different plane or a curved surface in a portion corresponding to the passivation layer150. In this case, the angle may be defined as an angle between an extending line of the portion corresponding to the photosensitive polymer layer160and the first main surface110A.

A top surface160uof the photosensitive polymer layer160may not be completely parallel with the first main surface110A. In some embodiments of the inventive concept, a vertical thickness t of the photosensitive polymer layer160between the connection terminal structure140and the alignment key170may decrease in a direction toward the alignment key170. For example, the photosensitive polymer layer160may have a decreasing thickness toward the alignment key170with a thickness change between about 0.01 μm and about 0.5 μm.

Referring back toFIG.3, connection pads120may be provided in end portions of the first through-electrode structure131and the second through-electrode structure133near the second main surface110B. The connection pad120may include aluminum (Al), copper (Cu), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), cobalt (Co), tungsten (W), zinc (Zn), or an alloy thereof.

Although the planar shape of the connection pad120is illustrated as a circle inFIG.1, the planar shape of the connection pad120may be, but not limited to, an arbitrary polygon such as a square, a rectangle, etc., an oval, etc.

FIGS.5and6are partial enlarged views of a portion indicated by III inFIG.2of an interposer according to other embodiments of the inventive concept.

An embodiment ofFIG.5is the same as the embodiment ofFIG.3except that a first conductor layer141ais of a pillar type. Thus, hereinbelow, the embodiment ofFIG.5will be described based on such a difference.

Referring toFIG.5, vertical dimensions of the first conductor layer141aof the pillar type may be greater than those of the first conductor layer141shown inFIG.3. The first conductor layer141amay include, for example, copper (Cu), aluminum (Al), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), cobalt (Co), tungsten (W), zinc (Zn), or an alloy thereof, and especially, copper (Cu).

An embodiment ofFIG.6is the same as the embodiment ofFIG.3except that the passivation layer150is omitted. Thus, hereinbelow, the embodiment ofFIG.6will be described based on such a difference.

Referring toFIG.6, the passivation layer150is omitted, such that the photosensitive polymer layer160may contact the first main surface110A of the interposer substrate110. The photosensitive polymer layer160may contact the sidewalls of the first through-electrode structure131and the second through-electrode structure133that protrude from the first main surface110A. For example, the photosensitive polymer layer160may contact the sidewall of the protruding portion of each of the first through-electrode structure131and the second through-electrode structure133.

The alignment key170may be formed in the photosensitive polymer layer160. The alignment key170may be adjacent to the first through-electrode structure131and/or the second through-electrode structure133. The alignment key170may not pass through the photosensitive polymer layer160. In some embodiments of the inventive concept, the alignment key170may pass through the photosensitive polymer layer160, and a portion of the first main surface110A may be exposed by the alignment key170.

In some embodiments of the inventive concept, the top surface of the first through-electrode structure131may be substantially coplanar with the top surface of the photosensitive polymer layer160. The top surface of the second through-electrode structure133may be substantially coplanar with the top surface of the photosensitive polymer layer160.

FIG.7is a partial enlarged view of a portion indicated by III inFIG.2of an interposer according to another embodiment of the inventive concept.

An embodiment ofFIG.7is the same as the embodiment ofFIG.3except that a redistribution layer120RDL is further provided. Thus, hereinbelow, the embodiment ofFIG.7will be described based on such a difference.

Referring toFIG.7, the redistribution layer120RDL may be further provided on the connection pad120. The redistribution layer120RDL may include contact plugs122_V1and122_V2and metal horizontal wires122_L1and122_L2. The contact plugs122_V1and122_V2may electrically connect the metal horizontal wires122_L1and122_L2to each other, which are formed in multi-levels, and/or the connection pad120at each level. The redistribution layer120RDL may further include an interlayer insulating film128to electrically insulate several components. The interlayer insulating film128may include silicon oxide, silicon nitride, silicon oxynitride, polymer, or a combination thereof.

FIG.8is a side cross-sectional view of a semiconductor package10including the interposer100, according to an embodiment of the inventive concept.

Referring toFIG.8, the semiconductor package10may include a package substrate200, the interposer100arranged on the package substrate200, and a first semiconductor device310and a second semiconductor device320that are mounted on the interposer100.

The package substrate200may include a base board layer210, and a top pad222and a bottom pad224which are arranged on a top surface and a bottom surface of the base board layer210, respectively.

In some embodiments of the inventive concept, the package substrate200may be a printed circuit board (PCB). For example, the package substrate200may be a multi-layered PCB. The base board layer210may include at least one material selected from phenol resin, epoxy resin, and polyimide. The base board layer210may include at least one material selected from, for example, flame retardant4, tetrafunctional epoxy, polyphenylene ether, epoxy/polyphenylene oxide, bismaleimide triazine (BT), Thermount, cyanate ester, polyimide, and liquid crystal polymer.

On the top surface and the bottom surface of the base board layer210may be a top solder resist layer232and a bottom solder resist layer234that expose the top pad222and the bottom pad224, respectively. The connection terminal structure140may be connected to the top pad222, and an external connection terminal250may be connected to the bottom pad224.

The package substrate200may include interconnection patterns that electrically connect the top pad222with the bottom pad224and conductive vias that electrically connect the interconnection patterns to each other. The interconnection patterns may be located on the top surface, the bottom surface, and/or the inside of the base board layer210. The interconnection patterns may include, for example, an electrolytically deposited (ED) copper foil, a rolled-annealed (RA) copper foil, a stainless-steel foil, an aluminum foil, ultra-thin copper foils, sputtered copper, copper alloys, etc.

The conductive vias may be formed to pass through at least a part of the base board layer210. In some embodiments of the inventive concept, the conductive vias may include copper, nickel, stainless steel, or beryllium copper.

In some embodiments of the inventive concept, when the semiconductor package10does not include the package substrate200, the connection terminal structure140may function as an external connection terminal.

The interposer100has been described in detail with reference toFIGS.1through7, and thus will not be described in detail at this time.

The first semiconductor device310may be mounted on a first region R1(seeFIG.1) on the interposer100. The first semiconductor device310may be connected to the redistribution layer120RDL of the interposer100through a connection member314. The connection member314may include, for example, a bump, a solder ball, or a conductive pillar.

The first semiconductor device310may be, for example, a central processing unit (CPU), a graphic processing unit (GPU), or an application processor (AP). In some embodiments of the inventive concept, the first semiconductor device310may further include, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, an electrically erasable and programmable read-only memory (EEPROM), a phase-change random access memory (PRAM), a magnetic random access memory (MRAM), or a resistive random access memory (RRAM). As used herein, a semiconductor device may refer, for example, to a device such as a semiconductor chip (e.g., memory chip and/or logic chip formed on a die), a stack of semiconductor chips, a semiconductor package including one or more semiconductor chips stacked on a package substrate, or a package-on-package device including a plurality of packages. These devices may be formed using ball grid arrays, wire bonding, through substrate vias, or other electrical connection elements, and may include memory devices such as volatile or non-volatile memory devices. Semiconductor packages may include a package substrate, one or more semiconductor chips, and an encapsulant formed on the package substrate and covering the semiconductor chips.

The second semiconductor device320may be mounted on a second region R2(seeFIG.2) on the interposer100.

The second semiconductor device320may be, for example, a high bandwidth memory (HBM) DRAM. The second semiconductor device320may include a semiconductor chip or a stack of a plurality of memory semiconductor chips. Herein, the ‘stack’ may be defined as any memory chips included together in one assembly based on definitions of the Joint Electron Device Engineering Council (JEDEC).

The second semiconductor device320may include a plurality of memory chips323a,323b,323c, and323d. The plurality of memory chips323a,323b,323c, and323dmay be electrically connected with one another by connection terminals336. The connection terminals336may be bumps or solder balls.

Each of the plurality of memory chips323a,323b,323c, and323dmay include a through silicon via (TSV)338that electrically connects a chip pad arranged on an inactive surface with a chip pad arranged on an active surface.

The plurality of memory chips323a,323b,323c, and323dmay be attached to one another by adhesive layers382. In some embodiments of the inventive concept, the adhesive layer382may include a non-conductive film (NCF).

The second semiconductor device320may further include a logic chip325. The plurality of memory chips323a,323b,323c, and323dmay be stacked on the logic chip325that may be mounted on the interposer100.

The logic chip325may serve to control the operation of the plurality of memory chips323a,323b,323c, and323d. The logic chip325may be a semiconductor chip and may be described as a control chip. In some embodiments, the logic chip325may include, but is not limited to, for example, logic circuits such as a serializer (SER)/deserializer (DES) circuits. The logic chip325may be connected to the redistribution layer120RDL of the interposer100through a connection member324. The connection member324may include, for example, a bump, a solder ball, or a conductive pillar.

In some embodiments of the inventive concept, the interposer100, the first semiconductor device310, and the second semiconductor device320may be sealed by an encapsulant, but the encapsulant is not shown for identification of other components inFIG.8.

The semiconductor package10may further include a heat dissipation member such as a heat slug or a heat sink. The heat dissipation member may be configured to contact the first semiconductor device310, the second semiconductor device320, and/or the encapsulant.

FIG.9is a side cross-sectional view of a semiconductor package10A including an interposer100A, according to an embodiment of the inventive concept.

Referring toFIG.9, the semiconductor package10A may include a package substrate200A having a recess portion SR, the interposer100A which is accommodated in the recess portion SR and electrically connected with the package substrate200A, and the first semiconductor device310and the second semiconductor device320which are mounted on both the interposer100A and the package substrate200A. In some embodiments, the first semiconductor device310may partially overlap the interposer100A, and the second semiconductor device320may partially overlap the interposer100A.

The package substrate200A may include the recess portion SR. A depth of the recess portion SR may be determined based on a level that a top surface of the interposer100A needs to have when the interposer100A is accommodated in the recess portion SR. In some embodiments of the inventive concept, the top surface of the package substrate200A may be arranged substantially coplanar with the top surface of the interposer100A accommodated in the recess portion SR.

The interposer100A may include a third region R3that partially overlaps the first semiconductor device310and a fourth region R4that partially overlaps the second semiconductor device320. In some embodiments of the inventive concept, the interposer100A may completely overlap any one of the first semiconductor device310and the second semiconductor device320and partially overlap the other.

The first semiconductor device310and the second semiconductor device320may be electrically connected with the interposer100A through the connection members314and324. The first semiconductor device310and the second semiconductor device320may be electrically connected with the package substrate200A through connection members314aand324a.

While the redistribution layer120RDL is aligned to face the package substrate200A inFIG.9, the redistribution layer120RDL may be aligned to face the first semiconductor device310and the second semiconductor device320in another embodiment of the inventive concept.

The first semiconductor device310and the second semiconductor device320have been described in detail with reference toFIG.8, and thus will not be described repeatedly.

FIG.10is a side cross-sectional view of a semiconductor package10B including an interposer100B, according to another embodiment of the inventive concept.

Referring toFIG.10, the semiconductor package10B may include an interposer100B, the first semiconductor device310and a second semiconductor device320amounted on different surfaces of the interposer100B, and a package substrate200B on which the interposer100B is mounted.

The first semiconductor device310may be mounted on a first main surface110A of the interposer100B, and the second semiconductor device320amay be mounted on a second main surface110B of the interposer100B, more specifically, on the redistribution layer120RDL. While the first semiconductor device310and the second semiconductor device320aare illustrated as a single semiconductor chip inFIG.10, each of the first semiconductor device310and the second semiconductor device320amay include a plurality of semiconductor chips.

The interposer100B may be mounted on the package substrate200B by the connection terminal structure140. The first semiconductor device310may also be mounted on the interposer100B by the connection terminal structure140. The second semiconductor device320amay be electrically connected with the redistribution layer120RDL through the connection member324.

The package substrate200B may include the recess portion SR that at least partially accommodates the first semiconductor device310.

FIGS.11A through11Rare side cross-sectional views illustrating a method of fabricating the interposer100, according to an embodiment of the inventive concept.

Referring toFIG.11A, an etching mask101may be formed on the interposer substrate110to define positions in which a first through-electrode structure and a second through-electrode structure are to be formed. The etching mask101may be a hard mask and/or a photoresist mask, and may be formed by a photolithography process. The hard mask may include, for example, a material such as silicon nitride, a spin-on hard mask (SOH), and an amorphous carbon layer (ACL). The photoresist mask may include a photosensitive polymer. The specific kind of the photosensitive polymer may be determined depending on a wavelength range of exposed light.

Referring toFIG.11B, by performing anisotropic etching with respect to an exposed portion using the etching mask101, a first via hole131hand a second via hole133hmay be formed. CFx-based gas such as C4F8, etc., as etching gas and additive gas such as Ar, N2, O2, H2, etc., may be used.

In some embodiments of the inventive concept, the first via hole131hand the second via hole133hmay be performed by deep reactive-ion etching (DRIE) also known as a Bosch process. In some embodiments, a scallop may be formed at least partially on sidewalls of the first via hole131hand the second via hole133h.

In some embodiments of the inventive concept, a laser drilling technique may apply to form the first via hole131hand the second via hole133h.

Referring toFIG.11C, a via dielectric material film131dmand a barrier material film131bmmay be sequentially formed to coat inner sidewalls of the first via hole131hand the second via hole133hand bottom surfaces thereof, and the top surface of the interposer substrate110. The via dielectric material film131dmmay be formed by CVD or PVD. The barrier material film131bmmay be formed by CVD, PVD, or ALD.

Thereafter, a core conductor material film131ammay be formed in a space defined by the barrier material film131bm. The core conductor material film131ammay be formed by electroplating. For example, the core conductor material film131ammay be formed by forming a metal seed layer on the surface of the barrier material film131bm, and a conductor film may grow from the metal seed layer by electroplating. The metal seed layer may include Cu, a Cu alloy, Co, Ni, Ru, Co/Cu, or Ru/Cu. The metal seed layer may be formed by PVD. The core conductor material film131ammay include Cu or W. In some embodiments, most of the core conductor material film131ammay be formed of Cu or W.

In some embodiments of the inventive concept, the core conductor material film131ammay include, but not limited to, Cu, CuSn, CuMg, CuNi, CuZn, CuPd, CuAu, CuW, W, or a W alloy. The electroplating process may be performed at a temperature between about 10° C. and about 65° C. In some embodiments of the inventive concept, the electroplating process may be performed at a room temperature. After the core conductor material film131amis formed, a resultant where the core conductor material film131amis formed may be annealed at a temperature between about 150° C. and about 450° C.

Referring toFIG.11D, the core conductor material film131am, the barrier material film131bm, and the via dielectric material film131dmoutside the first via hole131hand the second via hole133hmay be removed by chemical mechanical polishing (CMP). As a result, the first through-electrode structure131and the second through-electrode structure133defined inside the first via hole131hand the second via hole133hmay be formed. The first through-electrode structure131may be arranged in the first via hole131h, and may include a first core conductor131a, a first barrier film131b, and a first via dielectric film131d. The second through-electrode structure133may be arranged in the second via hole133h, and may include a second core conductor133a, a second barrier film133b, and a second via dielectric film133d.

Thereafter, the first through-electrode structure131and the second through-electrode structure133may be thermally treated to reduce roughness on an exposed surface. In some embodiments of the inventive concept, thermal treatment may be performed at a temperature between about 400° C. and about 500° C.

Referring toFIG.11E, the connection pad120may be formed on the exposed surfaces of the first through-electrode structure131and the second through-electrode structure133. For example, the connection pad120may be formed on a first end of each of the first through-electrode structure131and the second through-electrode structure133.

The connection pad120may include Al, Cu, Au, Ag, Pt, Pd, Ni, Co, W, Zn, or an alloy thereof. In some embodiments of the inventive concept, the connection pad120may include copper and may be formed by using a damascene method. For example, after a sacrificial film corresponding to the shape of the connection pad120is formed, a copper material film is formed by plating and then is planarized to form the connection pad120in a sacrificial film pattern which is then removed, thus forming the connection pad120as illustrated inFIG.11E.

Referring toFIG.11F, the interposer substrate110may be partially removed from the bottom surface such that the first through-electrode structure131and the second through-electrode structure133protrude from the first main surface110A of the interposer substrate110. The interposer substrate110may be partially removed from the bottom surface by etchback. For example, the etchback is performed on the bottom surface of the interposer substrate110such that the bottom surface is recessed to form the first main surface110A and to expose a second end.

FIG.11Fillustrates a state where an interposer ofFIG.11Eis turned upside down. Thus, while the connection pads120are located on the first through-electrode structure131and the second through-electrode structure133inFIG.11E, the connection pads120may be located under the first through-electrode structure131and the second through-electrode structure133inFIG.11F.

Referring toFIG.11G, a passivation layer150may be formed on the first main surface110A of the interposer substrate110and the exposed surfaces of the first through-electrode structure131and the second through-electrode structure133. The passivation layer150may include a first passivation layer151and a second passivation layer153that may be sequentially formed. The first passivation layer151and the second passivation layer153each may be independently formed by PVD, CVD, or ALD.

The materials of the first passivation layer151and the second passivation layer153have been described in detail with reference toFIG.3, and thus will not be described repeatedly.

Referring toFIG.11H, a photosensitive polymer material film160mmay be formed on the passivation layer150. The photosensitive polymer material film160mmay have fast-curing property as well as photosensitivity to which the photolithography process is applicable. The photosensitive polymer material film160mmay include, for example, a photoimageable dielectric (PID) material. In some embodiments, the PID material may include, for example, a polyimide-based photosensitive polymer, a novolac-based photosensitive polymer, polybenzoxazole, silicone-based polymer, acrylate-based polymer, or epoxy-based polymer.

The photosensitive polymer material film160mmay be formed by spin coating. The photosensitive polymer material film160mhas high viscosity, such that the top surface of the photosensitive polymer material film160mmay have a higher level than the first through-electrode structure131and the second through-electrode structure133. In some embodiments, a top surface of the photosensitive polymer material film160mmay be uneven. For example, the photosensitive polymer material film160mmay include a first portion on each of the first through-electrode structure131and the second through-electrode structure133and a second portion on a region therebetween. A top surface of the first portion may be higher than a top surface of the second portion.

Referring toFIG.11I, an alignment key pattern170pmay be formed in the photosensitive polymer material film160m. Formation of the alignment key pattern170pmay be performed by selectively exposing the photosensitive polymer material film160mand developing the same.

In some embodiments of the inventive concept, the alignment key pattern170pmay be formed to pass through the photosensitive polymer material film160m. In some embodiments of the inventive concept, sidewalls of the alignment key pattern170pmay not be completely perpendicular to the first main surface110A. This is because a time and an environment in which the photosensitive polymer material film160mis exposed to an etchant for pattern formation may vary with positions of the sidewalls of the alignment key pattern170pin the vertical direction. As a result, as shown inFIG.4, the sidewall170SW may be formed which is inclined at a certain angle α (e.g., an angle between about 80 degrees and about 88 degrees) with respect to the first main surface110A.

Thereafter, the photosensitive polymer material film160mmay be cured by being annealed at a temperature between about 80° C. and about 200° C. for a curing time between about 5 seconds and about 5 minutes.

Referring toFIG.11J, anisotropic etching may be performed using the alignment key pattern170pas an etching mask, thus partially removing a portion, exposed the alignment key pattern170p, of the passivation layer150or completely removing the portion of the passivation layer150. Herein, the passivation layer150is illustrated as being partially removed.

In some embodiments of the inventive concept, an operation of partially removing the passivation layer150by using the alignment key pattern170pas an etching mask may be omitted.

Although the photosensitive polymer material film160mabove the first through-electrode structure131and the second through-electrode structure133is illustrated as being removed by anisotropic etching inFIG.11J, the photosensitive polymer material film160mmay partially remain on the first through-electrode structure131and the second through-electrode structure133according to circumstances.

Referring toFIG.11K, end portions (i.e., the second ends) of the first through-electrode structure131and the second through-electrode structure133may be partially removed and may be partially exposed from the passivation layer150.

Removal of the end portions may be performed by CMP. The passivation layer150on the first through-electrode structure131and the second through-electrode structure133may be removed by CMP. In some embodiments, the via dielectric films131dand133dand the barrier films131band133bon the top ends of the first through-electrode structure131and the second through-electrode structure133may also be partially removed by CMP.

In some embodiments of the inventive concept, CMP may be performed until the top surface of the photosensitive polymer layer160, the top surfaces of the first through-electrode structure131and the second through-electrode structure133, and the top surface of the passivation layer150surrounding side surfaces of the first through-electrode structure131and the second through-electrode structure133may become coplanar or on substantially the same plane. Terms such as “same,” “equal,” “planar,” or “coplanar,” as used herein encompass near identicality including variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise.

The alignment key170may also be formed by CMP.

Referring toFIG.11L, a seed metal layer145mmay be formed on the exposed surface. The seed metal layer145mmay be formed by, for example, CVD, ALD, or PVD. The seed metal layer145mmay include, for example, Cu, a Cu alloy, Co, Ni, Ru, Co/Cu, or Ru/Cu.

Referring toFIG.11M, a photoresist material film180mmay be formed on the seed metal layer145m. The photoresist material film180mmay be, for example, a photoresist material used in a photolithography process, and may be formed to a proper thickness by spin coating.

Referring toFIG.11N, the photoresist material film180mmay be patterned to expose the seed metal layer145mat a position where a connection terminal structure is to be formed, thus forming a photoresist pattern180. Patterning of the photoresist material film180mmay be performed by exposure and development using a photomask having a pattern.

Referring toFIG.11O, the first conductor layer141and a preliminary solder metal layer143amay then be formed by plating. Plating may be, but not limited to, electroplating. In some embodiments, the first conductor layer141and the preliminary solder metal layer143amay be formed by electroless plating. As shown inFIG.5, for the first conductor layer141aof a pillar type, a plating time may be adjusted such that the first conductor layer141ahas sufficiently large vertical dimensions.

Referring toFIG.11P, the photoresist pattern180may be removed. Removal of the photoresist pattern180may be performed by, but not limited to, ashing.

Referring toFIG.11Q, the exposed portion of the seed metal layer145mmay be removed by using the first conductor layer141and the preliminary solder metal layer143aas an etching mask. Removal of the exposed portion of the seed metal layer145mmay be performed by anisotropic etching or wet etching using selective etching liquid.

The exposed surface of the photosensitive polymer layer160may be partially removed while the exposed portion of the seed metal layer145mis removed. In some embodiments of the inventive concept, the top surface of the photosensitive polymer layer160may be partially removed while the exposed portion of the seed metal layer145mis removed, and material delivery of an etching gas or an etchant is more active in a portion away from the first conductor layer141than in a portion close to the first conductor layer141, such that the photosensitive polymer layer160may be removed faster. Consequently, as shown inFIG.4, the thickness of the photosensitive polymer layer160may decrease in a direction toward the alignment key pattern170p, and the top surface160uof the photosensitive polymer layer160may be inclined with respect to the first main surface110A.

Referring toFIG.11R, by reflowing the preliminary solder metal layer143a, the connection terminal structure140may be formed. The reflow may be performed at a temperature between about 200° C. and about 280° C. for a reflow time between about 30 seconds and about 10 minutes.

FIGS.12A through12Jare side cross-sectional views illustrating a method of fabricating an interposer, according to an embodiment described with reference toFIG.6.

Operations prior to an operation shown inFIG.12Aare common with the operations shown inFIGS.11A through11F, and thus will not be described for brevity. The operation shown inFIG.12Afollows the operation shown inFIG.11F.

Referring toFIG.12A, the photosensitive polymer material film160mmay be formed on the first main surface110A, the exposed first through-electrode structure131, and the second through-electrode structure133. The photosensitive polymer material film160mmay have fast-curing property as well as photosensitivity to which the photolithography process is applicable, and this matter has already been described with reference toFIG.11Hand thus will not be described in detail at this time.

Referring toFIG.12B, an alignment key pattern170pmay be formed in the photosensitive polymer material film160m. Formation of the alignment key pattern170pmay be performed by selectively exposing the photosensitive polymer material film160mand developing the same.

In some embodiments of the inventive concept, the alignment key pattern170pmay be formed to pass through the photosensitive polymer material film160m.

Thereafter, the photosensitive polymer material film160mmay be cured by being annealed at a temperature between about 80° C. and about 200° C. for a curing time between about 5 seconds and about 5 minutes.

Referring toFIG.12C, end portions of the first through-electrode structure131and the second through-electrode structure133, and the photosensitive polymer material film160mmay be partially removed to expose the first through-electrode structure131and the second through-electrode structure133and to form a photosensitive polymer layer160from the photosensitive polymer material film160m.

Removal of the end portions may be performed by CMP. Upper portions of the first through-electrode structure131and the second through-electrode structure133may be removed by CMP. Moreover, the via dielectric films131dand133dand the barrier films131band133bon the top ends of the first through-electrode structure131and the second through-electrode structure133may also be removed by CMP. The alignment key170may also be formed by CMP.

Referring toFIG.12D, a seed metal layer145mmay be formed on the exposed surface. The seed metal layer145mmay be formed by, for example, CVD, ALD, or PVD. The seed metal layer145mmay include, for example, Cu, a Cu alloy, Co, Ni, Ru, Co/Cu, or Ru/Cu.

Referring toFIG.12E, a photoresist material film180mmay be formed on the seed metal layer145m. The photoresist material film180mmay be, for example, a photoresist material that is used for a photolithography process, and may be formed to a proper thickness by spin coating.

Referring toFIG.12F, the photoresist material film180mmay be patterned to expose the seed metal layer145mat a position where a connection terminal structure is to be formed, thus forming the photoresist pattern180. Patterning of the photoresist material film180mmay be performed by exposure and development using a photomask having a pattern.

Referring toFIG.12G, the first conductor layer141and the preliminary solder metal layer143amay then be formed by plating. Plating may be, but not limited to, electroplating. In some embodiments, the first conductor layer141and the preliminary solder metal layer143amay then be formed by electroless plating.

Referring toFIG.12H, the photoresist pattern180may be removed. Removal of the photoresist pattern180may be performed by, but not limited to, ashing.

Referring toFIG.12I, the exposed portion of the seed metal layer145mmay be removed by using the first conductor layer141and the preliminary solder metal layer143aas an etching mask. Removal of the exposed portion of the seed metal layer145mmay be performed by anisotropic etching or wet etching using selective etching liquid.

Referring toFIG.12J, by reflowing the preliminary solder metal layer143a, the connection terminal structure140may be formed. The reflow may be performed at a temperature between about 200° C. and about 280° C. for a reflow time between about 30 seconds and about 10 minutes.

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.