Patent ID: 12193160

DETAILED DESCRIPTION

Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

In the present disclosure, the expression “side portion”, “side surface”, or the like refers to a direction toward a first direction or a second direction or a surface in that direction for convenience, the expression “upper side”, “upper portion”, “upper surface”, or the like refers to a direction toward a third direction or a surface in that direction for convenience, and the expression “lower side”, “lower portion”, “upper surface”, or the like refers to a direction toward an opposite direction to the third direction or a surface in that direction for convenience. In addition, the expression “positioned on the side portion, the upper side, the upper portion, the lower side, or the lower portion” conceptually includes a case in which a target component is positioned in a corresponding direction but is not in direct contact with a reference component, as well as a case in which the target component is in direct contact with the reference component in the corresponding direction. However, these directions are defined for convenience of explanation, and the claims are not particularly limited by the definition described above, and the concepts of the upper and lower portions, sides and surfaces may be changed.

Electronic Device

FIG.1is a block diagram schematically illustrating an example of an electronic device system.

Referring toFIG.1, an electronic device1000may accommodate a main board1010therein. Chip-related components1020, network-related components1030, and other components1040may be physically and/or electrically connected to the main board1010. These components may also be coupled to other electronic components, which will be described later, to form various signal lines1090.

The chip-related components1020may include: a memory chip such as a volatile memory (e.g. a dynamic random access memory (DRAM)), a non-volatile memory (e.g. a read only memory (ROM)), or a flash memory; an application processor chip such as a central processor (e.g. a central processing unit (CPU)), a graphics processor (e.g. a graphics processing unit (GPU)), a digital signal processor, a cryptography processor, a microprocessor, or a microcontroller; and a logic chip such as an analog-to-digital converter or an application-specific integrated circuit (ASIC). However, the chip-related components1020are not limited thereto, and may include any other types of chip-related electronic components. Also, these electronic components1020may also be combined with each other. The chip-related component1020may be in the form of a package including the above-described chip or electronic component.

The network-related components1030may include wireless fidelity (Wi-Fi) (Institute of Electrical And Electronics Engineers (IEEE) 802.11 family, or the like), worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family, or the like), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high speed packet access+ (HSPA+), high speed downlink packet access+ (HSDPA+), high speed uplink packet access+ (HSUPA+), enhanced data GSM environment (EDGE), global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS), code division multiple access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G, 4G, and 5G, and any other wireless and wired protocols designated thereafter. However, the network-related components1030are not limited thereto, and may include any other wireless or wired standards or protocols. Also, the network-related components1030may be combined with each other, together with the chip-related components1020.

The other components1040may include a high-frequency inductor, a ferrite inductor, a power inductor, ferrite beads, low-temperature co-firing ceramics (LTCC), an electro-magnetic interference (EMI) filter, a multi-layer ceramic condenser (MLCC), and the like. However, the other components1040are not limited thereto, and may include passive elements in the form of chip components used for various other purposes. Also, the other components1040may be combined with each other, together with the chip-related components1020and/or the network-related components1030.

The electronic device1000may include any other electronic components that may be or may not be physically and/or electrically connected to the main board1010according to the type of the electronic device1000. Examples of the other electronic components may include a camera1050, an antenna1060, a display1070, and a battery1080. However, the other electronic components are not limited thereto, and may be an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g. a hard disk drive), a compact disc (CD), and a digital versatile disc (DVD). Also, the electronic device1000may include any other electronic components used for various purposes according to the type of the electronic device1000.

The electronic device1000may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game machine, a smart watch, or an automotive component. However, the electronic device1000is not limited thereto, and may be any other electronic device processing data.

FIG.2is a perspective view schematically illustrating an example of an electronic device.

Referring toFIG.2, the electronic device may be, for example, a smartphone1100. A main board1110may be accommodated in the smartphone1100, and various electronic components1120may be physically and/or electrically connected to the main board1110. Also, other electronic components that may be or may not be physically and/or electrically connected to the main board1110, such as a camera1130and/or a speaker1140, may be accommodated in the smartphone1100. Some of the electronic components1120may be the above-described chip-related components, for example, semiconductor packages1121, but are not limited thereto. The semiconductor package1121may be a type in which a semiconductor chip or a passive component is surface-mounted on a package substrate in the form of a multilayer printed circuit board, but is not limited thereto. Meanwhile, the electronic device is not necessarily limited to the smartphone1100, and may be another electronic device as described above.

Printed Circuit Board

FIG.3is a cross-sectional view schematically illustrating a printed circuit board according to a first exemplary embodiment in the present disclosure, andFIG.5is a plan view schematically illustrating an example of a coil pattern applied to the printed circuit boards ofFIG.3andFIG.4to be described later.

Referring toFIG.3, the printed circuit board100A according to the first exemplary embodiment may include magnetic members210,220,230, and240embedded in core layers111and112, and a first coil pattern310and a second coil pattern320disposed on and under the core layers111and112respectively. In this case, the first and second coil patterns310and320may have a spiral thin-film coil pattern structure. Hereinafter, specific components that may be provided in the printed circuit board100A will be described in detail.

The printed circuit board100A may include a plurality of insulating layers111to119, a plurality of wiring layers121to126, and a plurality of via layers131to135. In this case, the magnetic members210,220,230, and240may be embedded in at least some of the plurality of insulating layers.

For example, in the printed circuit board100A according to the first exemplary embodiment in the present disclosure, a core substrate110may include a plurality of first and second core layers111and112and a plurality of first to third core insulating layers113ato113c. The plurality of first and second core layers111and112may be first and second insulating layers111and112, respectively, and the plurality of core insulating layers113ato113cmay be collectively referred to as third insulating layers.

In addition, the core substrate110may include fourth and fifth insulating layers114and115disposed between the plurality of first and second core layers111and112and the plurality of first to third core insulating layers113ato113c, and a through via131penetrating through the core substrate110.

In addition, the printed circuit board100A according to the first exemplary embodiment in the present disclosure may include first and second build-up layers110A and110B covering both surfaces of the core substrate110.

The first build-up layer110A, a build-up layer disposed on an upper surface of the core substrate110, may include a first wiring layer121and a sixth insulating layer116disposed on the core insulating layer113b, a third wiring layer123and an eighth insulating layer118disposed on the sixth insulating layer116, and a fifth wiring layer125disposed on the eighth insulating layer118.

On the other hand, the second build-up layer110B, a build-up layer disposed on a lower surface of the core substrate110, may include a second wiring layer122and a seventh insulating layer117disposed on the core insulating layer113c, a fourth wiring layer124and a ninth insulating layer119disposed on the seventh insulating layer117, and a sixth wiring layer126disposed on the ninth insulating layer119.

The first and second build-up layers110A and110B described above may be collectively referred to as build-up layers. Although the two build-up layers are illustrated, the number of build-up layers may be more than or less than two.

Meanwhile, the printed circuit board100A according to the first exemplary embodiment may further include a first passivation layer141disposed on the first build-up layer110A and having a plurality of first openings141heach exposing at least a portion of the fifth wiring layer125, a second passivation layer142disposed on the second build-up layer110B and having a plurality of second openings142heach exposing at least a portion of the sixth wiring layer126, a plurality of first electrical connection metals151disposed on the plurality of first openings141h, respectively, and electrically connected to the exposed portions of the fifth wiring layer125, respectively, and a plurality of second electrical connection metals152disposed on the plurality of second openings142h, respectively, and electrically connected to the exposed portions of the sixth wiring layer126, respectively.

As described above, central processing units (CPUs), application specific integrated circuits (ASICs), application processors (APs), and the like have recently been supplied with power from power management integrated circuits (PMICs). In order to improve power efficiency, there has recently been an increase in power supply switching frequency of the PMIC. In this regard, it may be considered to dispose an inductor on the main board, separately from the package substrate on which an integrated circuit (IC) is surface-mounted. However, in this case, a high-capacity inductor is required. In particular, an electrical path between the inductor and the integrated circuit (IC) mounted on the package substrate may be long, resulting in an increase in resistance and a decrease in power efficiency. Alternatively, it may be considered to simply form a coil in a pattern in the package substrate. In this case, however, the coil is formed in air rather than on a magnetic material, and thus, there may be difficulty in implementing capacitance, and the overall size of the package substrate may increase because it is required to use a large area of the package substrate in forming the pattern coil therein. Alternatively, it may be considered to surface-mount a die-type inductor on a bottom surface of the package substrate. In this case, however, the cost of the die-type inductor may be significant.

In contrast, the printed circuit board100A according to the first exemplary embodiment may include a plurality of first to fourth magnetic members210,220,230, and240. The plurality of first to fourth magnetic members210,220,230, and240may be collectively referred to as magnetic members200.

In the printed circuit board100A according to the first exemplary embodiment, the first core layer111may have a plurality of first cavities111H, and the first and second magnetic members210and220may be disposed in the respective first cavities111H. The first and second magnetic members210and220may be embedded, for example, to be at least partially covered by the fourth insulating layer114, while being disposed inside the first cavities111H.

The second core layer112may also have a plurality of second cavities112H, and the third and fourth magnetic members230and240may be disposed in the respective second cavities112H. The third and fourth magnetic members230and240may be embedded, for example, to be at least partially covered by the fifth insulating layer115, while being disposed inside the second cavities112H.

In addition, in the printed circuit board100A according to the first exemplary embodiment, each of the first to fourth magnetic members210,220,230, and240may be disposed on at least one of the first to third core insulating layers113ato113c. For example, the first and second magnetic members210and220may be disposed on the second core insulating layer113bto contact the second core insulating layer113b, and the third and fourth magnetic members230and240may be disposed on the third core insulating layer113cto contact the third core insulating layer113c.

In addition, the first coil pattern310may be disposed on the core substrate110, and the second coil pattern320may be disposed below the core substrate110. As described above, since the magnetic members200are in an embedded type, high capacitance can be implemented in the printed circuit board100A according to the present disclosure. For example, the second and fourth magnetic members220and240may be laminates including magnetic layers222and242, respectively, for maintaining a high magnetic permeability at a high frequency, as will be described later. Furthermore, since the coil patterns310and320are disposed adjacent to the plurality of magnetic members200, inductance performance may be improved.

Hereinafter, each component of the printed circuit board100A according to the present disclosure will be described in more detail.

The core layers111and112may include a plurality of first and second core layers111and112, and the first and second core layers111and112may be a core substrate that is the center of the printed circuit board100A. As a material of the first and second core layers111and112, an insulating material may be used. Here, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material including a reinforcing material such as a glass fiber, glass cloth, or glass fabric and/or an inorganic filler together with the aforementioned resin, e.g. a copper clad laminate (CCL) or an unclad CCL. However, the insulating material is not limited thereto. As the first and second core layers111and112, metal plates or glass plates may be used, or ceramic plates may be used. If necessary, a liquid crystal polymer (LCP) may be used as a material of the first and second core layers111and112. The first and second core layers111and112may have cavities111H and112H, respectively, and the magnetic members200may be disposed in the respective cavities111H and112H.

The core insulating layers113may include a plurality of first to third core insulating layers113ato113c. The first core insulating layer113amay be located in the center portion of the core substrate110, and the second and third core insulating layers113band113cmay be disposed on the first and second core layers111and112, respectively. The second core insulating layer113bmay be disposed between the first core layer111and the first coil pattern310, and the third core insulating layer113cmay be disposed between the second core layer112and the second coil pattern320. In other words, each of the second and third core insulating layers113band113cmay be disposed on an outer layer of the core substrate110. The first to third core insulating layers113ato113cmay also include the same material as the first and second core layers111and112as described above. However, the material of the first to third core insulating layers113ato113cis not limited thereto, and the first to third core insulating layers113ato113cmay include a different material from the first and second core layers111and112among the above-described materials that may be used for the first and second core layers111and112.

InFIG.3, the first to third core insulating layers113ato113care disposed. However, boundaries between the first to third core insulating layers113ato113cand the fourth and fifth insulating layers114and115and the core layers111and112may be clear or unclear. If the boundaries are unclear or if necessary, the first to third core insulating layers113ato113cmay be omitted.

The magnetic members200may be a magnetic element type, each including a magnetic material having a magnetic permeability, or in a laminate type, each including a base layer and a magnetic layer disposed on the base layer. In the printed circuit board100A according to the present disclosure, the first and third magnetic members210and230may be the magnetic element type, and the second and fourth magnetic members220and240may be the laminate type, including base layers221and241and magnetic layers222and242disposed on the base layers221and241, respectively.

The magnetic members200may have, but not limited to, a square column shape or a cylindrical shape in accordance with the inductor characteristics regardless of whether the magnetic members200are in the magnetic element type or in the laminate type.

For the first and third magnetic members210and230that are in the magnetic element type, a material having a high magnetic permeability is used to constitute an entire magnetic block, resulting in an advantageous effect in terms of productivity and cost.

In the second and fourth magnetic members220and240that are in the laminate type, each including a base layer and a magnetic layer disposed on the base layer, the base layers221and241may serve as substrates when forming the magnetic layers222and242. For example, the magnetic layers222and242may be attached to the base layers221and241, respectively, by sputtering or evaporation. Atoms or molecules ejected from a target material are collected on surfaces of the base layers221and241, such that the magnetic layers222and242are formed. The base layers221and241may include an insulating material. For example, the base layers221and241may include glass or an organic material, or may be prepreg or an Ajinomoto build-up film (ABF). Alternatively, the base layers221and241may be silicon wafers formed of single crystal silicon (Si).

The magnetic layers222and242may include a ferromagnetic material to increase magnetic fields, which are induced by the first and second coil patterns310and320. For example, the magnetic layers222and242may contain a cobalt-tantalum-zirconium alloy, a cobalt-niobium-zirconium alloy, a nickel-iron (Ni—Fe) alloy, a cobalt-zirconium oxide alloy, or the like, but the material of the magnetic layers222and242is not limited thereto as long as it is a magnetic material having a high magnetic permeability. The magnetic layers222and242may be formed by sputtering, and thus may be formed to have a thin film-level thickness, that is, a thickness of several micrometers. The magnetic layers222and242may be each formed of a single layer or multiple layers. When the magnetic layers222and242are each formed of multiple layers, each layer may have a thickness of about 0.1 to 3 μm, but the thickness of each layer is not limited thereto. Meanwhile, since the magnetic layers222and242are not directly formed on the printed circuit board, the magnetic layers222and242can be embedded at a thin film level. For example, after the base layers221and241are put into thin film formation equipment and the magnetic layers222and242are formed, the second and fourth magnetic members220and240may be cut to required sizes and then disposed into the cavities111H and112H of the first and second core layers111and112, respectively. Therefore, the second and fourth magnetic members220and240can be embedded into the printed circuit board in any size without being limited on the basis of a work size. In this way, a higher magnetic permeability can be implemented when the magnetic member has a structure in which the magnetic layer is disposed on the base layer than when the magnetic member is entirely formed of a magnetic material in the magnetic element type.

Meanwhile, the first and third magnetic members210and230may be the magnetic element type, and may contain a cobalt-tantalum-zirconium alloy, a cobalt-niobium-zirconium alloy, a nickel-iron (Ni—Fe) alloy, a cobalt-zirconium oxide alloy, or the like, like the magnetic layers222and242of the second and fourth magnetic members220and240, but the material of the first and third magnetic members210and230is not limited thereto as long as it is a magnetic material having a high magnetic permeability. The first and third magnetic members210and230may also be cut to required sizes and disposed into the first and second cavities111H and112H of the first and second core layers111and112, respectively. Therefore, the first and third magnetic members210and230can be embedded into the printed circuit board in any size without being limited on the basis of a work size.

Although not illustrated, the magnetic members200according to the present disclosure are not necessarily required to have a double-layer structure in a vertical direction, and the plurality of magnetic members200may be disposed in a horizontal direction in the single core layer111. In this case, each of the first magnetic member210and the second magnetic member220may be embedded in the core layer111, and the first magnetic member210may be the magnetic element type and the second magnetic member220may be the laminate type in which the magnetic layer222is disposed on the base layer221as described above.

Since the first and second magnetic members210and220are disposed in different forms, they can accordingly be different from each other in inductance increase effect and magnetic permeability. Based thereon, it is possible to secure a degree of freedom in designing the first and second coil patterns310and320disposed on and under each of the first and second magnetic members210and220. If necessary, both the first and second magnetic members210and220may be the magnetic element type or in the laminate type.

The first and second magnetic members210and220disposed in the first cavities111H may be at least partially covered by the fourth insulating layer114, and the third and fourth magnetic members230and240disposed in the second cavities112H may be at least partially covered by the fifth insulating layer115. Accordingly, the fourth insulating layer114may fill empty spaces of the first cavities111H, and the fifth insulating layer115may fill empty spaces of the second cavities112H. Meanwhile, an insulating material may be used as a material of the fourth and fifth insulating layers114and115, and the fourth and fifth insulating layers114and115may include the same material as the first and second core layers111and112as described above. In particular, the fourth and fifth insulating layers114and115may include an ABF or the like to fill the first and second cavities111H and112H. Boundaries between the fourth and fifth insulating layers114and115and the core insulating layers113may be clear or unclear.

As a material of the first and second wiring layers121and122, a metal material may be used. Here, the metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The first and second wiring layers121and122may be formed by plating such as an additive process (AP), a semi additive process (SAP), a modified semi additive process (MSAP), or tenting (TT). As a result, each of the first and second wiring layers121and122may include a seed layer, an electroless plating layer, and an electrolytic plating layer, formed on the basis of the seed layer. The first and second wiring layers121and122may perform various functions according to the designs of the layers. For example, the first and second wiring layers121and122may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signals, e.g. data signals, excluding the ground (GND) pattern, the power (PWR) pattern, and the like. If necessary, the ground (GND) pattern and the power (PWR) pattern may be the same pattern. Each of these patterns may include a line pattern, a plane pattern, and/or a pad pattern.

The first and second coil patterns310and320may be disposed on and under the core substrate110, respectively, and may have a planar spiral structure as illustrated inFIG.5. In addition, each of the first and second coil patterns310and320, which may correspond to a coil pattern311shown inFIG.5as an example, may include two connection pads, which may correspond to connection pads311P shown inFIG.5as an example, connected to both ends of the planar spiral structure, respectively. This means that each of the first and second coil patterns310and320includes an independent coil layer at the same level. In other words, each of the first and second coil patterns310and320may be a coil having a plurality of turns on the same plane. In this form, a high inductance can be implemented while the first and second coil patterns310and320are thin. Here, althoughFIG.5illustrates the first coil pattern310, the second coil pattern320may also have an identical or similar shape thereto. As described above, the first and second coil patterns310and320include independent spiral coil structures from each other and are not required to be directly connected to each other. Even though the first and second coil patterns310and320are not directly connected to each other, each may independently perform a function as an inductor.

The first and second coil patterns310and320may be formed simultaneously with the formation of the first and second wiring layers121and122, respectively. As a material of the first and second coil patterns310and320, a metal material may be used. Here, the metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The first and second coil patterns310and320may be formed by plating such as an additive process (AP), a semi additive process (SAP), a modified semi additive process (MSAP), or tenting (TT). As a result, each of the first and second coil patterns310and320may include a seed layer, an electroless plating layer, and an electrolytic plating layer, formed on the basis of the seed layer.

Meanwhile, the first coil pattern310may include a 1-1st coil pattern311disposed on the first magnetic member210and a 1-2nd coil pattern312disposed on the second magnetic member220. In addition, the second coil pattern320may include a 2-1st coil pattern321disposed on the third magnetic member230and a 2-2nd coil pattern322disposed on the fourth magnetic member240. Thus, the 1-1st, 1-2nd, 2-1st, and 2-2nd coil patterns311,312,321, and322may include 1-1st, 1-2nd, 2-1st, and 2-2nd connection pads311P,312P,321P,322P, respectively.

Meanwhile, although not illustrated, each of the first and second coil patterns310and320may include a plurality of planar spiral structures, and the plurality of planar spiral structures may be stacked in a thickness direction of the printed circuit board.

As illustrated inFIG.3, the first coil pattern310may be disposed on the core substrate110to be close to the first and second magnetic members210and220, and the second coil pattern320may be disposed below the core substrate110to be close to the third and fourth magnetic members230and240. To this end, the first and second coil patterns310and320may be disposed to be aligned in the thickness direction. In addition, the first and second coil patterns310and320may have the same or substantially the same width. Here, the width of the coil pattern may refer to a length from the center of the pattern to the outermost side of the pattern. Furthermore, the first and second coil patterns310and320may have the same or substantially the same width as the magnetic members200. Since the first and second coil patterns310and320are disposed above and below the magnetic members200and adjacent to the magnetic members200, a high inductance can be implemented within a limited space of the printed circuit board100A.

In the printed circuit board100A according to the first exemplary embodiment as illustrated inFIG.3, the magnetic members200including the first to fourth magnetic members210,220,230, and240are arranged in two layers. However, the magnetic members200may be arranged in more than two layers. In this case, additional build-up layers may be disposed above the first and second build-up layers110A and110B together to cover the magnetic members200.

As a material of the first and second coil patterns310and320, a metal material may be used. Here, the metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. In this case, the first and second coil patterns310and320may be formed, simultaneously with the formation of the first wiring layer121and the second wiring layer122, respectively, by the above-described plating. As a result, each of the first and second coil patterns310and320may include a seed layer, an electroless plating layer, and an electrolytic plating layer, formed on the basis of the seed layer.

The through via131may be a first via layer131. Meanwhile, as a material of the through via131as well, a metal material may be used. Here, the metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The through via131may also be formed by plating such as AP, SAP, MSAP, or TT. As a result, the through via131may include a seed layer, an electroless plating layer, and an electrolytic plating layer, formed on the basis of the seed layer. Wiring vias of the through via131may be each completely filled with the metal material, or the metal material may be formed along wall surfaces of via holes. In addition, any known shape, such as an hourglass shape or a cylindrical shape, may be applied to the through via131. The through via131may also perform various functions according to the design of the layer. For example, the through via131may include a wiring via for signal connection, a wiring via for ground connection, a wiring via for power connection, and the like. The wiring via for ground connection and the wiring via for power connection may be the same wiring via.

The sixth to ninth insulating layers116to119may provide insulating areas for forming multi-layered wirings on both sides of the core substrate110. As a material of the sixth to ninth insulating layers116to119, an insulating material may be used. Here, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material including a reinforcing material such as a glass fiber and/or an inorganic filler together with the aforementioned resin, e.g. prepreg or ABF. If necessary, a photo image-able dielectric (PID) may be used as a material of the sixth to ninth insulating layers116to119. Meanwhile, the sixth to ninth insulating layers116to119may include the same material or different materials. Boundaries between the sixth to ninth insulating layers116to119may be clear or unclear.

As a material of the first to sixth wiring layers121to126, a metal material may be used. Here, the metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Each of the first to sixth wiring layers121to126may be formed by plating such as AP, SAP, MSAP, or TT. As a result, each of the first to sixth wiring layers121to126may include a seed layer, an electroless plating layer, and an electrolytic plating layer, formed on the basis of the seed layer. The first to sixth wiring layers121to126may perform various functions according to the designs of the layers. For example, the first to sixth wiring layers121to126may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. Here, the signal (S) pattern may include various signals, e.g. data signals, excluding the ground (GND) pattern, the power (PWR) pattern, and the like. If necessary, the ground (GND) pattern and the power (PWR) pattern may be the same pattern. Each of these patterns may include a line pattern, a plane pattern, and/or a pad pattern.

As a material of the second to fifth via layers132to135as well, a metal material may be used. Here, the metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Each of the second to fifth via layers132to135may also be formed by plating such as AP, SAP, MSAP, or TT. As a result, each of the second to fifth via layers132to135may include a seed layer, an electroless plating layer, and an electrolytic plating layer, formed on the basis of the seed layer. Wiring vias of the second to fifth via layers132to135may be each completely filled with the metal material, or the metal material may be formed along wall surfaces of via holes. In addition, any known shape, such as a tapered shape, may be applied to the second to fifth via layers132to135. As an example, the wiring vias of the third and fifth via layers133and135and the wiring vias of the second and fourth via layers132and134may have tapered shapes in opposite directions to each other. The second to fifth via layers132to135may also perform various functions according to the designs of the layers. For example, the second to fifth via layers132to135may include a wiring via for signal connection, a wiring via for ground connection, a wiring via for power connection, and the like. The wiring via for ground connection and the wiring via for power connection may be the same wiring via.

The first and second passivation layers141and142may protect the internal components of the printed circuit board100A according to the first exemplary embodiment from external physical and chemical damage. The first and second passivation layers141and142may include a thermosetting resin. For example, the first and second passivation layers141and142may be ABFs. However, the material of the first and second passivation layers141and142is not limited thereto, and each of the first and second passivation layers141and142may be a known solder resist (SR) layer. If necessary, the first and second passivation layers141and142may also include a PID. The first and second passivation layers141and142may have a plurality of openings141hand142h, respectively. The plurality of openings141hand142hmay expose at least a portion the fifth and sixth wiring layers125and126, which are the uppermost and lowermost wiring layers of the printed circuit board100A according to the first exemplary embodiment, respectively. Meanwhile, surface treatment layers may be formed on the exposed surfaces of the fifth and sixth wiring layers125and126. The surface treatment layer may be formed by, for example, electrolytic gold plating, electroless gold plating, organic solderability preservative (OSP) or electroless tin plating, electroless silver plating, electroless nickel plating/substituted gold plating, direct immersion gold (DIG) plating, hot air solder leveling (HASL), or the like. If necessary, each of the openings141hand142hmay include a plurality of via holes. If necessary, an under-bump metallurgy (UBM) bump may be disposed on each of the openings141hand142hto improve reliability.

The first and second electrical connection metals151and152are components for physically and/or electrically connecting the printed circuit board100A according to the first exemplary embodiment to the outside. For example, an electronic component400may be mounted on the printed circuit board100A according to the first exemplary embodiment through the first electrical connection metal151. In addition, the printed circuit board100A according to the first exemplary embodiment may be mounted on the main board of the electronic device through the second electrical connection metal152. For example, the printed circuit board100A according to the first exemplary embodiment may be a ball grid array (BGA)-type package substrate. The electrical connection metals151and152may be disposed on the plurality of openings141hand142hof the first and second passivation layers141and142, respectively. Each of the first and second electrical connection metals151and152may be made of a low melting point metal having a lower melting point than copper (Cu), e.g. tin (Sn) or an alloy containing tin (Sn). For example, the electrical connection metals151and152may be formed of solder, but this is only an example, and the material is not particularly limited thereto.

The first and second electrical connection metals151and152may be lands, balls, pins, or the like. The first and second electrical connection metals151and152may be formed in multiple layers or in a single layer. The first and second electrical connection metals151and152may include copper pillars and solder when formed in multiple layers, and may include tin-silver solder when formed in a single layer. However, this is also only an example, and the material is not limited thereto. The number, distance, arrangement form, etc. of the first and second electrical connection metals151and152are not particularly limited, and may be sufficiently modified by those skilled in the art according to details of designs. Since the second electrical connection metal152is for mounting the printed circuit board on the main board, the number and size of second electrical connection metals152may be larger than those of the first electrical connection metals151. From this point of view, the number and size of the plurality of second openings142hmay be larger than those of the plurality of first openings141h.

The electronic component400may be a known active or passive component. For example, the electronic component400may be a semiconductor chip or a semiconductor package including a semiconductor chip. However, the electronic component400is not limited thereto, and may be another known surface-mounted component.

FIG.4is a cross-sectional view schematically illustrating a printed circuit board according to a second exemplary embodiment in the present disclosure.

The printed circuit board100B according to the second exemplary embodiment in the present disclosure ofFIG.4may be different, in the positions of the magnetic members200, as compared with the printed circuit board100A according to the first exemplary embodiment in the present disclosure. Therefore, for the configuration overlapping with that of the printed circuit board100A according to the first exemplary embodiment in the present disclosure, the above description of the printed circuit board100A according to the first exemplary embodiment in the present disclosure may be identically applicable. The printed circuit board100B according to the second exemplary embodiment in the present disclosure will be described focusing on components modified from those in the previous exemplary embodiment.

The printed circuit board100B according to the second exemplary embodiment in the present disclosure ofFIG.4is different, in the respective positions of the magnetic members200, as compared with the printed circuit board100A according to the first exemplary embodiment. For example, the first to fourth magnetic members210,220,230, and240may be disposed on the first core insulating layer113a. Specifically, the first and second magnetic members210and220may be disposed on one surface of the first core insulating layer113awhile being disposed inside the first cavities111h, and the third and fourth magnetic members230and240may be disposed on the other surface of the first core insulating layer113awhile being disposed inside the second cavities112h. In this way, a distance between the magnetic members200embedded in the core substrate110having a multilayer structure can be reduced, thereby achieving a magnetic flux increasing effect.

The above description of the first and second coil patterns310and320illustrated inFIG.5may also be identically applied to the printed circuit board100B according to the second exemplary embodiment ofFIG.4.

FIG.6is a cross-sectional view schematically illustrating a printed circuit board according to a third exemplary embodiment in the present disclosure, andFIG.9is a plan view schematically illustrating a partial cross-sectional view of a magnetic member in the printed circuit boards ofFIG.6andFIG.7to be described later.

The printed circuit board100C according toFIG.6is different, in that connection vias331and332are further included, as compared with the printed circuit board100A according to the first exemplary embodiment ofFIG.3. Therefore, for the configuration overlapping with that of the printed circuit board100A, the above description of the printed circuit board100A according to the first exemplary embodiment may be identically applicable. The printed circuit board100C according to the third exemplary embodiment in the present disclosure will be described focusing on components modified from those in the previous exemplary embodiment.

Although not illustrated, each of the first and second coil patterns310and320may have a plurality of planar spiral structures, and the plurality of planar spiral structures may be implemented to be stacked in a thickness direction of the printed circuit board. That is, for the first coil pattern310, multiple coil layers may be connected to each other to form a single coil structure. This is the same for the second coil pattern320. To this end, in each of the first and second coil patterns310and320, the plurality of planar spiral structures may be connected to each other by a connection via (not illustrated). When each of the first and second coil patterns310and320includes multiple coil layers as in the present embodiment, the number of turns of the coil can be increased, thereby further improving inductance characteristics.

Meanwhile, the printed circuit board100C according to the third exemplary embodiment ofFIG.6may further include a plurality of connection vias331and332. The connection vias331and332may include first and second connection vias331and332, and the first and second coil patterns310and320may be connected to each other by the connection vias331and332. The first and second the connection vias331and332may penetrate through the core substrate110to electrically connect the first and second coil patterns310and320to each other. Meanwhile, as in the first exemplary embodiment, the first coil pattern310may include a 1-1st coil pattern311disposed on the first magnetic member210and a 1-2nd coil pattern312disposed on the second magnetic member220. The second coil pattern320may also include a 2-1st coil pattern321disposed on the third magnetic member230and a 2-2nd coil pattern322disposed on the fourth magnetic member240.

Thus, the 1-1st coil pattern311and the 2-1st coil pattern321may form a single coil structure as a whole, and the 1-2nd coil pattern312and the 2-2nd coil pattern322may form another single coil structure as a whole.

As a material of the first and second connection vias331and332as well, a metal material may be used. Here, the metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The first and second connection vias331and332may also be formed by plating such as AP, SAP, MSAP, or TT. As a result, each of the first and second connection vias331and332may include a seed layer, an electroless plating layer, and an electrolytic plating layer, formed on the basis of the seed layer. Wiring vias of the first and second connection vias331and332may be each completely filled with the metal material, or the metal material may be formed along wall surfaces of via holes. In addition, any known shape, such as an hourglass shape or a cylindrical shape, may be applied to the first and second connection vias331and332. The first and second connection vias331and332may also perform various functions according to the designs of the layers. For example, the first and second connection vias331and332may include a wiring via for signal connection, a wiring via for ground connection, a wiring via for power connection, and the like. The wiring via for ground connection and the wiring via for power connection may be the same wiring via.

In this case, as illustrated, the connection vias331and332may be implemented to penetrate through the magnetic members200. Specifically, the first connection via331may penetrate through each of the first and third magnetic members210and230to connect the 1-1st coil pattern311and the 2-1st coil pattern321. The second connection via332may also penetrate through each of the second and fourth magnetic members220and240to connect the 1-2nd coil pattern312and the 2-2nd coil pattern322. When the connection vias331and332penetrate the magnetic members200to connect the first and second coil patterns310and320, as illustrated inFIG.8, the connection vias331and332may connect the respective innermost ends of the first and second coil patterns310and320(corresponding to pad areas connected by331inFIG.8).

The connection pad310P disposed at the other end of the first coil pattern310may be connected to another circuit pattern on the same layer, for example, the first wiring layer121, and the connection pad310P and the first wiring layer121may be disposed on the same plane. The connection pad320P disposed at the other end of the second coil pattern320may be connected to another circuit pattern on the same layer, for example, the second wiring layer122, and the connection pad320P and the second wiring layer122may be disposed on the same plane.

Meanwhile, although not illustrated, the connection vias331and332may be disposed adjacent to side surfaces of the magnetic members200. In this case, the connection vias331and332are not required to penetrate through the magnetic members200.

FIG.7is a cross-sectional view schematically illustrating a printed circuit board according to a fourth exemplary embodiment in the present disclosure.

The printed circuit board100D according to the fourth exemplary embodiment in the present disclosure ofFIG.7may be different, in the positions of the magnetic members200, as compared with the printed circuit board100C according to the third exemplary embodiment in the present disclosure. Therefore, for the configuration overlapping with that of the printed circuit board100C according to the third exemplary embodiment in the present disclosure, the above description of the printed circuit board100C according to the third exemplary embodiment in the present disclosure may be identically applicable. The printed circuit board100D according to the fourth exemplary embodiment in the present disclosure ofFIG.7will be described focusing on components modified from those in the previous exemplary embodiment.

The printed circuit board100D according to the fourth exemplary embodiment in the present disclosure ofFIG.7is different, in the respective positions of the magnetic members200, as compared with the printed circuit board100C according to the third exemplary embodiment. For example, the first to fourth magnetic members210to240may be disposed on the first core insulating layer113a. Specifically, the first and second magnetic members210and220may be disposed on one surface of the first core insulating layer113awhile being disposed inside the first cavities111h, and the third and fourth magnetic members230and240may be disposed on the other surface of the first core insulating layer113awhile being disposed inside the second cavities112h. In this way, a distance between the magnetic members200embedded in the core substrate110having a multilayer structure can be reduced, thereby achieving a magnetic flux increasing effect.

The above description of the first and second coil patterns310and320illustrated inFIG.6may also be identically applied to the printed circuit board100D according to the fourth exemplary embodiment ofFIG.7.

FIG.9is a plan view schematically illustrating a partial cross-sectional view of the magnetic member in the printed circuit boards ofFIGS.6and7.

As illustrated inFIG.9, a through hole H may be formed in the first magnetic member210, and the first connection via331may penetrate through the through hole H to electrically connect the 1-1st coil pattern311and the 2-1st coil pattern321to each other. Although not illustrated, the first connection via331may additionally penetrate through the third magnetic member230. InFIG.9, only the first connection via331penetrating through the first and third magnetic members210and230is illustrated. However, this structure may also be applied identically to the second connection via332penetrating through the second and fourth magnetic members220and240.

FIG.10is a cross-sectional view schematically illustrating a printed circuit board according to a fifth exemplary embodiment in the present disclosure, andFIG.12is a plan view schematically illustrating an example of a coil pattern applied to the printed circuit boards ofFIG.10andFIG.11to be described later.

The printed circuit board100E according to the fifth exemplary embodiment ofFIG.10is different, in that each of the first and second coil patterns310and320further includes a pad connection via131′ connecting the connection pads310P and320P to each other without having a planar spiral structure, as compared with the printed circuit board100A according to the first exemplary embodiment ofFIG.3. Therefore, for the configuration overlapping with that of the printed circuit board100A, the above description of the printed circuit board100A according to the first exemplary embodiment may be identically applicable. The printed circuit board100E according to the fifth exemplary embodiment in the present disclosure will be described focusing on components modified from those in the previous exemplary embodiment.

In the printed circuit board100E according to the fifth exemplary embodiment, the first and second coil patterns310and320may include a plurality of first and second connection parts310′ and320′ spaced apart from each other, respectively. Specifically, the first connection part310′ may include 1-1st connection parts311′ and 1-2nd connection parts312′, and the second connection part320′ may include 2-1st connection parts321′ and 2-2nd connection parts322′.

For example, the 1-1st coil pattern311may include a plurality of 1-1st connection parts311′ spaced apart from each other, and the 1-2nd coil pattern312may include a plurality of 1-2nd connection parts312′ spaced apart from each other. Also, the 2-1st coil pattern321may include a plurality of 2-1st connection parts321′ spaced apart from each other, and the 2-2nd coil pattern322may include a plurality of 2-2nd connection parts322′ spaced apart from each other.

The above-described first and second connection parts310′ and320′ may be electrically connected to each other by a plurality of connection vias333. In this case, the connection vias333may be disposed to penetrate through the core substrate110to electrically connect the first coil pattern310provided on the core substrate110and the second coil pattern320provided below the core substrate110to each other.

In the printed circuit board according to the fifth exemplary embodiment, the first and second connection pads310P and320P may be electrically connected to each other by a plurality of pad connection vias131′. The plurality of pad connection vias131′ may be disposed adjacent to side surfaces of the magnetic member200.

As a material of the first and second connection parts310′ and320′ as well, a metal material may be used. Here, the metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The first and second connection parts310′ and320′ may be formed by plating such as AP, SAP, MSAP, or TT. As a result, each of the first and second connection parts310′ and320′ may include a seed layer, an electroless plating layer, and an electrolytic plating layer, formed on the basis of the seed layer.

As a material of the connection vias333and the pad connection vias131′ as well, a metal material may be used. Here, the metal material may be copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The connection vias333and the pad connection vias131′ may also be formed by plating such as AP, SAP, MSAP, or TT. As a result, each of the connection vias333and the pad connection vias131′ may include a seed layer, an electroless plating layer, and an electrolytic plating layer, formed on the basis of the seed layer. Wiring vias of the connection vias333and the pad connection vias131′ may be each completely filled with the metal material, or the metal material may be formed along wall surfaces of via holes. In addition, any known shape, such as an hourglass shape or a cylindrical shape, may be applied to the connection vias333and the pad connection vias131′. The connection vias333and the pad connection vias131′ may also perform various functions according to the designs of the layers. For example, the connection vias333and the pad connection vias131′ may include a wiring via for signal connection, a wiring via for ground connection, a wiring via for power connection, and the like. The wiring via for ground connection and the wiring via for power connection may be the same wiring via.

FIG.12illustrates a configuration of the connection vias333connecting the 1-1st coil pattern311and the 2-1st coil pattern321in the printed circuit board100E according to the fifth exemplary embodiment. As described above, the 1-1st coil pattern311may include a plurality of 1-1st connection parts311′ spaced apart from each other, and the 2-1st coil pattern321may include a plurality of 2-1st connection parts321′ spaced apart from each other.

In addition, the 1-1st connection pads311P may be disposed at one ends of two outermost 1-1st connection parts311′ among the plurality of 1-1st connection parts311′ of the 1-1st coil pattern311. That is, the 1-1st connection pads311P may be disposed at both ends of the 1-1st coil pattern311. In addition, the 2-1st connection pads321P may be disposed at positions adjacent to the plurality of the 2-1st connection parts321′ of the 2-1st coil pattern321, and the 2-1st connection pads321P are not required to be directly connected to the 2-1st connection parts321′.

Meanwhile, the 1-1st connection pad311P and the 2-1st connection pad321P may be electrically connected to each other through the pad connection via131′.

Accordingly, in the printed circuit board100E according to the fifth exemplary embodiment, the first and third magnetic members210and230may be surrounded by the 1-1st and 2-1st coil patterns311and321, the connection vias333, and the pad connection vias131′ illustrated inFIG.12.

The 1-1st coil pattern311, the 2-1st coil pattern321, and the pad connection vias131′ may form a structure surrounding a magnetic member, similar to a wound-type inductor structure. For example, the first and third magnetic members210and230may be disposed in a space S ofFIG.12. By disposing the magnetic members, it is possible to improve an inductance L of the above-described wound-type inductor structure.

InFIG.12, the 1-1st coil pattern311and the 2-1st coil pattern321are illustrated, but the same structure may be applied to the 1-2nd coil pattern312and the 2-2nd coil pattern322. In this case, the second and fourth magnetic members220and240may be surrounded by the 1-2nd and 2-2nd coil patterns312and322, the connection vias333, and the pad connection vias131′.

FIG.11is a cross-sectional view schematically illustrating a printed circuit board according to a sixth exemplary embodiment in the present disclosure.

The printed circuit board100F according to the sixth exemplary embodiment in the present disclosure ofFIG.11may be different, in the positions of the magnetic members200, as compared with the printed circuit board100E according to the fifth exemplary embodiment in the present disclosure. Therefore, for the configuration overlapping with that of the printed circuit board100E according to the fifth exemplary embodiment in the present disclosure, the above description of the printed circuit board100E according to the fifth exemplary embodiment in the present disclosure may be identically applicable. The printed circuit board100F according to the sixth exemplary embodiment ofFIG.11will be described focusing on components modified from those in the previous exemplary embodiment.

The printed circuit board100F according to the sixth exemplary embodiment in the present disclosure ofFIG.11is different, in the respective positions of the magnetic members200, as compared with the printed circuit board100E according to the fifth exemplary embodiment. For example, the first to fourth magnetic members210,220,230, and240may be disposed on the first core insulating layer113a. Specifically, the first and second magnetic members210and220may be disposed on one surface of the first core insulating layer113awhile being disposed inside the first cavities111h, and the third and fourth magnetic members230and240may be disposed on the other surface of the first core insulating layer113awhile being disposed inside the second cavities112h. In this way, a distance between the magnetic members200embedded in the core substrate110in the multilayer structure can be reduced, thereby achieving a magnetic flux increasing effect.

The above description of the first and second coil patterns310and320of the printed circuit board100E according to the fifth exemplary embodiment may also be identically applied to the printed circuit board100F according to the sixth exemplary embodiment ofFIG.11.

As set forth above, according to the exemplary embodiment in the present disclosure, it is possible to provide a printed circuit board having an inductor function capable of maintaining a high magnetic permeability even at a high frequency.

In addition, it is possible to provide a printed circuit board whose core can be manufactured thickly, with a magnetic material embedded in the thick core so that the board can be thin.

While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present invention as defined by the appended claims.