Patent ID: 12205553

DETAILED DESCRIPTION

Hereinafter, a backlight device and a liquid crystal display apparatus according to an embodiment of the present invention will be described with reference to the drawings. The backlight device and the liquid crystal display apparatus according to the embodiment of the present invention are not limited to those exemplified below.

FIG.1is a schematic perspective view of the liquid crystal display apparatus300according to the embodiment of the present invention. The liquid crystal display apparatus300includes a liquid crystal display panel200and the backlight device100disposed on the back surface side of liquid crystal display panel200.

The backlight device100exemplified here has nine regions BA11, BA12, BA13, BA21, BA22, BA23, BA31, BA32, and BA33arrayed in three rows and three columns, and each region has a plurality of LED elements10. The nine regions BA11, BA12, BA13, BA21, BA22, BA23, BA31, BA32, and BA33(sometimes collectively called BA) irradiate nine regions DA11, DA12, DA13, DA21, DA22, DA23, DA31, DA32, and DA33in a display region of the liquid crystal display panel200with light. Luminances of the regions BA11, BA12, BA13, BA21, BA22, BA23, BA31, BA32, and BA33of the backlight device100can be controlled in accordance with images displayed in the regions DA11, DA12, DA13, DA21, DA22, DA23, DA31, DA32, and DA33in the display region of the liquid crystal display panel200. That is, the liquid crystal display apparatus300is a liquid crystal display apparatus that can perform local dimming.

FIG.2is a schematic block diagram of the liquid crystal display apparatus300according to the embodiment of the present invention.

The liquid crystal display apparatus300includes the backlight device100, the liquid crystal display panel200, and an LCD control circuit (timing controller)220that drives the liquid crystal display panel200. The backlight device100includes a power supply circuit110, a control circuit (image processing IC)120, a plurality of LED drive circuits130that generate LED drive signals configured to drive the LED elements10in each region BA, and the time constant circuit140arranged between the control circuit120and each of the LED drive circuits130and connected to the corresponding LED drive circuit130.

The control circuit120receives an image signal Video from the outside, and outputs the vertical synchronization signal Vsync and current setting data Vdata for setting the luminance of the LED elements10in each region BA in accordance with a luminance signal of the image signal Video. Each time constant circuit140delays the vertical synchronization signal Vsync by a predetermined time. The delay time varies depending on the time constant circuit140, and the time constant circuit140outputs the delayed vertical synchronization signal Vsync_d to the corresponding LED drive circuit130.

The LED drive circuit130receives the current setting data Vdata from the control circuit120and receives the delayed vertical synchronization signal Vsync_d from the corresponding time constant circuit140. The current setting data Vdata can be transmitted by using, for example, SPI. The control circuit120supplies a signal Vsig for driving the liquid crystal display panel200to an LCD control circuit220as, for example, a V by one (registered trademark) signal.

After receiving a vertical synchronization signal indicating the start of a current vertical scanning period (current frame) and before receiving a vertical synchronization signal indicating the start of a next vertical scanning period (next frame), the LED drive circuit130controls the current to be supplied to the LED element10based on the current setting data regarding the current vertical scanning period. The current setting data regarding the current vertical scanning period is received, for example, during the immediately preceding vertical scanning period (immediately preceding frame). In this example, the LED drive circuit130determines a duty ratio of the waveform of the voltage to be applied to the gate of the LED FET12based on the current setting data, and the LED drive current in accordance with the duty ratio flows through the LED element10.

The LED element10is connected to the power supply circuit110, and the luminance of the LED element10is adjusted at a desired luminance by the LED FET12controlling the drive current. By inputting the drive current of each of the LED elements10to IDs1,2, and3as voltage using the resistive element14, the drive current of each of the LED elements10can be detected by the LED drive circuit130. The power supply circuit110is a DCDC power supply circuit, and can raise and lower an output voltage of the DCDC power supply by a feedback (FB) output voltage from the LED drive circuit130. Therefore, the current detection circuit that detects the current of the LED element can control the output voltage of the DCDC power supply while monitoring the drive current.

Next, the configuration and the operation of the time constant circuit140included in the backlight device100will be described with reference toFIG.3.

Drive of the LED elements10in three different regions (a first region, a second region, and a third region) will be described as an example. LED elements10_1,10_2, and10_3, the LED FETs12_1,12_2, and12_3, and resistive elements14_1,14_2, and14_3respectively represent the plurality of LED elements10, the plurality of LED FETs12, and the plurality of resistive elements14in the first region, the second region, and the third region.

The vertical synchronization signal Vsync output from the control circuit120is input to a time constant circuit140_1connected to an LED drive circuit130_1for driving the LED element10_1in the first region. The time constant circuit140_1includes a resistive element142_1and a capacitance element144_1. The resistive element142_1and the capacitance element144_1are connected in series. The vertical synchronization signal Vsync becomes the vertical synchronization signal Vsync_d1delayed by a predetermined time by the time constant circuit140_1, and is input to the LED drive circuit130_1.

Similarly, the vertical synchronization signal Vsync is input to a time constant circuit140_2connected to an LED drive circuit130_2for driving the LED element10_2in the second region. The time constant circuit140_2includes a resistive element142_2and a capacitance element144_2. The resistive element142_2and the capacitance element144_2are connected in series. The vertical synchronization signal Vsync becomes the vertical synchronization signal Vsync_d2delayed by a predetermined time by the time constant circuit140_2, and is input to the LED drive circuit130_2.

Similarly, the vertical synchronization signal Vsync is input to a time constant circuit140_3connected to an LED drive circuit130_3for driving the LED elements10_3in the third region. The time constant circuit140_3includes a resistive element142_3and a capacitance element144_3. The resistive element142_3and the capacitance element144_3are connected in series. The vertical synchronization signal Vsync becomes the vertical synchronization signal Vsync_d3delayed by a predetermined time by the time constant circuit140_3, and is input to the LED drive circuit130_3.

For example, delay time of each of the delayed vertical synchronization signals Vsync_d1, Vsync_d2, and Vsync_d3can be adjusted as follows. For example, the output voltage of the DCDC power supply110is set to 6 V.

When the resistance values of the resistive elements142_1,142_2, and142_3are each 100Ω, and the capacitance values of the capacitance elements144_1,144_2, and144_3are 0.1 μF, 0.2 μF, and 0.3 μF, respectively, the delay times td become 50 μs, 100 μs, and 150 μs, respectively.

As described above, since the timing at which the LED drive circuits130_1,130_2, and130_3provided for the respective regions change the LED drive current is shifted from the vertical synchronization signal Vsync, the timing at which the rush current is generated in drive of the LED FETs12_1,12_2, and12_3is shifted. Then, the drop of the power supply voltage of the LED is reduced. Therefore, it is no longer necessary to set the power supply voltage of the LED higher than the Vf voltage of the LED. Since the heat generation of the LED FETs12_1,12_2, and12_3is reduced and the operation is stabilized, there is no need to design the DCDC circuit with good transient response characteristics, and the circuit scale can be reduced.

According to the embodiment of the present invention, simply by adding a time constant circuit using the existing controller (image processing IC)120, a problem caused by a plurality of LED drive circuits simultaneously changing the LED drive current can be avoided.

Note that the liquid crystal display apparatus according to the embodiment of the present invention includes at least two regions in the display region of the liquid crystal display panel, the backlight device is only required to include at least two regions, and the liquid crystal display apparatus is only required to include at least one time constant circuit140.

Next, the configuration and the operation of another time constant circuit that can be included in the backlight device100according to the embodiment of the present invention will be described with reference toFIGS.4and5. Time constant circuits150_1,150_2, and150_3are each configured to be given two time constants. That is, the time constant circuits150_1,150_2, and150_3are each configured to change time during which the vertical synchronization signal Vsync is caused to be delayed (in this case, to select two different delay times).

As illustrated inFIG.4, the time constant circuit150_1includes a resistive element152_1, two capacitance elements154_1aand154_1b, and two FETs156_1aand156_1brespectively connected to the two capacitance elements154_1aand154_1b. In order to give more than two time constants, it is only required to provide three or more sets of capacitance elements and FETs.

Similarly, the time constant circuit150_2includes a resistive element152_2, two capacitance elements154_2aand154_2b, and two FETs156_2aand156_2brespectively connected to the two capacitance elements154_2aand154_2b. The time constant circuit150_3includes a resistive element152_3, two capacitance elements154_3aand154_3b, and two FETs156_3aand156_3brespectively connected to the two capacitance elements154_3aand154_3b. The capacitance elements154_1a,2a, and3aare sometimes referred to as first capacitance elements, and the capacitance elements154_1b,2b, and3bare sometimes referred to as second capacitance elements. The FETs156_1a,2a, and3aare sometimes referred to as first FETs, and the FETs156_1b,2b, and3bare sometimes referred to as second FETs.

The LED drive circuit130_1outputs a gate signal G_1afor turning on/off the gate of the FET156_1afrom a terminal C_1a, and outputs a gate signal G_1bfor turning on/off the gate of the FET156_1bfrom a terminal C_1b. By changing the combined capacitance value of the two capacitance elements154_1aand154_1bby controlling the gate signals G_1aand G_1b, two different time constants can be given in a driving state (lighting state) of the LED element10.

FIG.5illustrates delayed vertical synchronization signals Vsync_d1, Vsync_d2, and Vsync_d3and waveforms of voltages to be applied to gates of LED FETs12_1,12_2, and12_3, respectively. The left side in each waveform drawing illustrates waveforms in a state where only the FET156_1a, the FET156_2a, and the FET156_3aare turned on, and the right side illustrates waveforms in a state where both the FETs156_1aand1b, both the FETs156_2aand2b, and both the FETs156_3aand3bare turned on. When the capacitance values of the two capacitance elements154_1aand154_1b, the two capacitance elements154_2aand154_2b, and the two capacitance elements154_3aand154_3bare all equal, the delay time td illustrated on the right side inFIG.5(the delay time td when both the first FET and the second FET are turned on) is twice the delay time td illustrated on the left side inFIG.5(the delay time td when only the first FET is turned on). Of course, the capacitance value of each of the capacitance elements can be set independently.

For example, when the power supply voltage of the LED drops due to the rush current of the LED element, the drive current of the LED element decreases. When the current detection circuit that detects the current of the LED element detects that the drive current has fallen below a set value, the second FET is turned on to increase the capacitance value of the time constant circuit (combined capacitance of the first capacitance element and the second capacitance element). Then, the rush current is dispersed, and the drop of the power supply voltage of the LED does not occur (becomes higher than Vf). When the current detection circuit detects that the drive current has become the set value, the second FET is turned off to decrease the capacitance value of the time constant circuit (only the capacitance value of the first capacitance element).

Since the direct-current resistance of the LED element10is less at the time of the first activation, the rush current may be great. Therefore, the second FET may be set to be turned on at the time of the first activation.

With reference toFIG.6, the configuration and the operation of still another time constant circuit that can be included in the backlight device100according to the embodiment of the present invention will be described. Time constant circuits160_1,160_2, and160_3are each configured to be given two or more time constants. That is, the time constant circuits160_1,160_2, and160_3are each configured to change time during which the vertical synchronization signal Vsync is caused to be delayed.

As illustrated inFIG.6, the time constant circuit160_1includes an FET162_1and a capacitance element164_1. An output RC1of the LED drive circuit130_1is connected to the gate of the FET162_1. As the FET162_1, an FET (for example, a P-channel FET) whose on-resistance changes depending on the gate voltage is used, and the time constant of the time constant circuit160_1can be changed by the voltage of the output RC1.

The time constant circuit160_2includes an FET162_2and a capacitance element164_2. An output RC2of the LED drive circuit130_2is connected to the gate of the FET162_2, and the time constant of the time constant circuit160_2can be changed by the voltage of the output RC2. Similarly, the time constant circuit160_3includes an FET162_3and a capacitance element164_3. An output RC3of the LED drive circuit130_3is connected to the gate of the FET162_3, and the time constant of the time constant circuit160_3can be changed by the voltage of the output RC3.

For example, with the capacitance values of the capacitance elements164_1,164_2, and164_3being all the same, by using the same P-channel FETs as the FETs162_1,162_2, and162_3, and lowering the gate voltages to be output from the outputs RC1, RC2, and RC3, for example, changing the on-resistance of the P-channel FET from 4Ω to 8Ω, the delay time can be doubled as illustrated inFIG.5.

Next, an example of setting of the delay time and arrangement of the time constant circuit in a case where the backlight device has12regions arrayed in a matrix shape having four rows and three columns will be described with reference toFIGS.7to9.

The time constant of the above-described time constant circuit can be variously set using a resistive element, a capacitance element, and an FET. The circuit design can be simplified by setting the delay time of each region in accordance with a law when the region is divided into a greater number of regions.

FIG.7is a schematic view illustrating an example of the arrangement of a plurality of regions in the backlight device. In the example illustrated inFIG.7, the regions of the first column, the second column, and the third column of the first row are regions BA11, BA12, and BA13, respectively, the regions of the first column, the second column, and the third column of the second row are regions BA21, BA22, and BA23, respectively, the regions of the first column, the second column, and the third column of the third row are regions BA31, BA32, and BA33, respectively, and the regions of the first column, the second column, and the third column of the fourth row are regions BA41, BA42, and BA43, respectively. In the lower part of each region inFIG.7, delay times d11, d21, . . . , and d43of the delayed vertical synchronization signal to be supplied to the regions BA11, BA21, . . . , and BA43are indicated. Here, for each of the regions BA11, BA21, . . . , and BA43, it is preferable that the delayed vertical synchronization signals (Vsync_d11, Vsync_d21, . . . , and Vsync_d43inFIG.9) have different timings. It is more preferable to prevent a plurality of delayed vertical synchronization signals from being continuous at equal intervals. That is, it is preferable to set the delay time so as to satisfy the relationship of (Da2−Da1)≠(Da3−Da2) and Db1≠(Db2−Db1)≠(Db3−Db2). For example, the setting is as follows.

Delay times Da1, Da2, and Da3different from one another are set for the regions BA11, BA12, and BA13, respectively, included in the first row. For example, Da1<Da2<Da3, (Da2−Da1)<(Da3−Da2).

Assume that the delay times of the regions BA21, BA22, and BA23included in the second row are obtained by adding a certain delay time Db1to the delay times of the regions BA11, BA12, and BA13, respectively. That is, the delay times Da1+Db1, Da2+Db1, and Da3+Db1are set for the regions BA21, BA22, and BA23. For example, Db1<Da1and Db1<(Da2−Da1).

Assume that the delay times of the regions BA31, BA32, and BA33included in the third row are obtained by adding a certain delay time Db2to the delay times of the regions BA11, BA12, and BA13, respectively. That is, the delay times Da1+Db2, Da2+Db2, and Da3+Db2are set for the regions BA31, BA32, and BA33. For example, Db2>Db1. Also, Db2<(Da2−Da1).

Assume that the delay times of the regions BA41, BA42, and BA43included in the fourth row are obtained by adding a certain delay time Db3to the delay times of the regions BA11, BA12, and BA13, respectively. That is, the delay times Da1+Db3, Da2+Db3, and Da3+Db3are set for the regions BA41, BA42, and BA43. For example, Db3>Db2. Also, Db3<(Da2−Da1).

A difference (Da2−Da1, Da3−Da2) between the delay times of the vertical synchronization signals received by the two LED drive circuits corresponding to the two regions adjacent in the row direction is made greater than a difference (Db1, Db2−Db1, Db3−Db2) between the delay times of the vertical synchronization signals received by the two LED drive circuits corresponding to the two regions adjacent in the column direction.

In the example illustrated inFIG.7, the difference between the delay times of the two vertical synchronization signals received by LED drive circuits corresponding to the two regions adjacent in the row direction is constant regardless of the row. The difference between the delay times of the vertical synchronization signals received by the two LED drive circuits corresponding to the two regions adjacent in the column direction is constant regardless of the column.

FIG.8illustrates a schematic view of an arrangement example of the time constant circuit in the backlight device having the plurality of regions of the arrangement illustrated inFIG.7. The setting of the delay time illustrated inFIG.7can be achieved, for example, by setting the capacitance value of the time constant circuit140illustrated inFIG.8to become the delay time of each region.

That is, the time constant circuit140corresponding to the region BA11is set to be given the delay time Da1, the time constant circuit140corresponding to the region BA12is set to be given the delay time Da2, and the time constant circuit140corresponding to the region BA13is set to be given the delay time Da3.

For the time constant circuits140corresponding to the regions BA21, BA22, and BA23, the capacitance values of the time constant circuits140corresponding to the regions BA11, BA12, and BA13are increased so as to lengthen the delay time by Db1.

Similarly, the capacitance values of the time constant circuits140corresponding to the region BA31, the region BA32, and the region BA33, and the capacitance values of the time constant circuits140corresponding to the region BA41, the region BA42, and the region BA43are increased.

FIG.9illustrates delayed vertical synchronization signals Vsync_d11, Vsync_d21, . . . , and Vsync_d43and waveforms of voltages to be applied to the gates of the LED FETs12for the respective regions illustrated inFIG.7.

The value of the delay time can be appropriately set in accordance with a falling time constant of the rush current, for example. For example, Da1=0 μs, Da2=260 μs, Db3=300 μs, Db1=50 μs, Db2=110 μs, and Db3=180 μs are set.

By setting the delay time as described above, a great rush current can be dispersed in the horizontal direction (in a region included in the same row) and a less rush current in the vertical direction (in a region included in the same column). By making the timings of the delayed vertical synchronization signals different for each of the divided regions, electro magnetic interference (EMI) caused by the power supply can be reduced. By preventing continuation of a plurality of delayed vertical synchronization signals at equal intervals, for example, the sounding can be suppressed. For example, when a plurality of delayed vertical synchronization signals are continuous at equal intervals, sound on the order of KHz caused by power supply ripple from a circuit substrate may enter a human audible range (20 to 20 KHz).

FIG.10is a schematic view illustrating an example of the arrangement of a plurality of regions in the backlight device that can perform backlight scan according to the embodiment of the present invention.

In the backlight device illustrated inFIG.10, the control circuit120outputs a plurality of vertical synchronization signals Vsync1, Vsync2, Vsync3, and Vsync4having phases different from one another. The plurality of vertical synchronization signals Vsync1, Vsync2, Vsync3, and Vsync4are used for sequentially driving the LED elements in synchronization with line sequential driving of the liquid crystal display panel. This backlight device includes a plurality of time constant circuits that delay each of the plurality of vertical synchronization signals Vsync1, Vsync2, Vsync3, and Vsync4by a predetermined time. For example, the delay time is controlled for each region where each scan unit of backlight scan (a region of a row (may be a plurality of rows) having the same vertical synchronization signal before delay) is divided into a plurality of columns. For example, each of Vsync1, Vsync2, Vsync3, and Vsync4is supplied to a region (scan unit) including m rows (m: positive integer) of LED elements, each scan unit is divided into a region including n columns of LED elements, and a delay time is controlled for each segmented region (including m rows and n columns of LED elements). Of course, the number of vertical synchronization signals generated by the control circuit120and the number of segmented regions can be appropriately adjusted in accordance with the size of the liquid crystal display panel, the number of pixels, and the like.

Another transistor can be used instead of the FET included in the backlight device of the above embodiment. The time constant circuit140can be mounted on, for example, a back surface (a surface opposite to the surface on which the LED element10is arranged) or a front surface of a LED substrate on which the LED element10is arranged. The FET12and the resistive element14can be formed on a back surface or a front surface of the LED substrate.

The backlight device according to the embodiment of the present invention is suitably used for a large or high-definition liquid crystal display apparatus.

While there have been described what are at present considered to be certain embodiments of the application, it will be understood that various modifications may be made thereto, and it is intended that the appended claim cover all such modifications as fall within the true spirit and scope of the application.