Patent ID: 12261164

DETAILED DESCRIPTION OF EMBODIMENTS

Semiconductor packages according to example embodiments will be described hereinafter with reference to the accompanying drawings.

FIG.1is a cross-sectional view illustrating a semiconductor package according to some example embodiments.FIG.2is an enlarged view of a region ‘A’ ofFIG.1.FIGS.3and4are cross-sectional views illustrating semiconductor packages according to some example embodiments.

Referring toFIGS.1and2, a package substrate100may be provided. The package substrate100may include a printed circuit board (PCB) having signal patterns on its top surface. Alternatively, the package substrate100may have a structure in which insulating layers and interconnection layers are alternately stacked. The package substrate100may have pads disposed on its top surface.

External terminals102may be disposed under the package substrate100. For example, the external terminals102may be disposed on terminal pads disposed on a bottom surface of the package substrate100. The external terminals102may include solder balls or solder bumps. The semiconductor package may be provided in the form of a ball grid array (BGA), a fine ball-grid array (FBGA) or a land grid array (LGA), depending on a kind and arrangement of the external terminals102.

An interposer substrate200may be provided on the package substrate100. The interposer substrate200may be mounted on the top surface of the package substrate100. The interposer substrate200may include first substrate pads210exposed at a top surface of the interposer substrate200, and second substrate pads220exposed at a bottom surface of the interposer substrate200. Here, top surfaces of the first substrate pads210may be coplanar with the top surface of the interposer substrate200. The interposer substrate200may redistribute a first chip stack CS1and a second chip stack CS2, which will be described later. For example, the first substrate pads210and the second substrate pads220may be electrically connected to each other through circuit interconnection lines in the interposer substrate200and may constitute a redistribution circuit along with the circuit interconnection lines. The first substrate pads210and the second substrate pads220may include a conductive material such as a metal. For example, the first substrate pads210and the second substrate pads220may include copper (Cu). The interposer substrate200may be formed of an insulating material or silicon (Si). When the interposer substrate200includes silicon (Si), the interposer substrate200may be a silicon interposer substrate having a through-electrode vertically penetrating the silicon interposer substrate.

Substrate terminals230may be disposed on the bottom surface of the interposer substrate200. The substrate terminals230may be provided between the pads of the package substrate100and the second substrate pads220of the interposer substrate200. The substrate terminals230may electrically connect the interposer substrate200to the package substrate100. For example, the interposer substrate200may be mounted on the package substrate100by a flip chip method. The substrate terminals230may include solder balls or solder bumps.

A first underfill layer240may be provided between the package substrate100and the interposer substrate200. The first underfill layer240may fill a space between the package substrate100and the interposer substrate200and may surround the substrate terminals230.

A first chip stack CS1may be disposed on the interposer substrate200. The first chip stack CS1may include a plurality of memory chips and may provide a memory of the semiconductor package. For example, the first chip stack CS1may include a base substrate, first semiconductor chips320corresponding to memory chips stacked on the base substrate, and a first molding layer330surrounding the first semiconductor chips320. Hereinafter, the components of the first chip stack CS1will be described in detail.

The base substrate may be a base semiconductor chip310. For example, the base substrate may be a wafer-level semiconductor substrate formed of a semiconductor material such as silicon. Hereinafter, the base semiconductor chip310and the base substrate may refer to the same component, and the base semiconductor chip and the base substrate may be indicated by the same reference numeral. A thickness of the base semiconductor chip310may range from 40 μm to 100 μm.

The base semiconductor chip310may include a base circuit layer312and a base through-electrode314. The base circuit layer312may be provided on a bottom surface of the base semiconductor chip310. The base circuit layer312may include an integrated circuit. For example, the base circuit layer312may include a memory circuit. In other words, the base semiconductor chip310may be a memory chip such as a dynamic random-access memory (DRAM) chip, a static random-access memory (SRAM) chip, a magnetoresistive random-access memory (MRAM) chip, or a flash memory chip. The base through-electrode314may penetrate the base semiconductor chip310in a direction perpendicular to the top surface of the interposer substrate200. The base through-electrode314and the base circuit layer312may be electrically connected to each other. The bottom surface of the base semiconductor chip310may be an active surface. The base substrate includes the base semiconductor chip310inFIG.1. However, embodiments of the disclosure are not limited thereto. In certain embodiments, the base substrate may not include the base semiconductor chip310.

The base semiconductor chip310may further include a protective layer and first connection terminals316. The protective layer may be disposed on the bottom surface of the base semiconductor chip310to cover the base circuit layer312. The protective layer may include silicon nitride (SiN). The first connection terminals316may be provided on the bottom surface of the base semiconductor chip310. The first connection terminals316may be electrically connected to the base circuit layer312. The first connection terminals316may be exposed from the protective layer.

A first semiconductor chip320may be mounted on the base semiconductor chip310. A thickness of the first semiconductor chip320may range from 40 μm to 100 μm. A width of the first semiconductor chip320may be less than a width of the base semiconductor chip310.

The first semiconductor chip320may include a circuit layer322and a through-electrode324. The circuit layer322may include a memory circuit. In other words, the first semiconductor chip320may be a memory chip such as a DRAM chip, a SRAM chip, a MRAM chip, or a flash memory chip. The circuit layer322may include the same circuit as the base circuit layer312. However, embodiments of the disclosure are not limited thereto. The through-electrode324may penetrate the first semiconductor chip320in the direction perpendicular to the top surface of the interposer substrate200. The through-electrode324may be electrically connected to the circuit layer322. A bottom surface of the first semiconductor chip320may be an active surface. First bumps326may be provided on the bottom surface of the first semiconductor chip320. The first bumps326may be provided between the base semiconductor chip310and the first semiconductor chip320to electrically connect the base semiconductor chip310and the first semiconductor chip320to each other.

The first semiconductor chip320may be provided in plurality. For example, the plurality of first semiconductor chips320may be stacked on the base semiconductor chip310. The number of the stacked first semiconductor chips320may range from 8 to 32. In this case, the first bumps326may also be formed between the stacked semiconductor chips320. Here, an uppermost one of the first semiconductor chips320may not include the through-electrode324. In addition, a thickness of the uppermost first semiconductor chip320may be greater than thicknesses of the first semiconductor chips320disposed thereunder.

An adhesive layer may be provided between the semiconductor chips320. The adhesive layer may include a non-conductive film (NCF). The adhesive layer may be disposed between the first bumps326provided between the first semiconductor chips320to prevent occurrence of an electrical short between the first bumps326.

The first molding layer330may be disposed on the top surface of the base semiconductor chip310. The first molding layer330may at least partially cover the base semiconductor chip310and may surround the first semiconductor chips320. A top surface of the first molding layer330may be coplanar with a top surface of the uppermost first semiconductor chip320, and the uppermost first semiconductor chip320may be exposed from the first molding layer330. The first molding layer330may include an insulating polymer material. For example, the first molding layer330may include an epoxy molding compound (EMC).

The first chip stack CS1may be provided as described above. The first chip stack CS1may be mounted on the interposer substrate200. For example, the first chip stack CS1may be connected to the first substrate pads210of the interposer substrate200through the first connection terminals316of the base semiconductor chip310.

A second underfill layer318may be provided between the interposer substrate200and the first chip stack CS1. The second underfill layer318may fill a space between the interposer substrate200and the base semiconductor chip310and may surround the first connection terminals316.

A second chip stack CS2may be disposed on the interposer substrate200. The second chip stack CS2may include a logic chip and at least one memory chip and may be a chip stack for driving the semiconductor package. For example, the second chip stack CS2may include a redistribution substrate400, a second semiconductor chip500(e.g., a memory chip) disposed on the redistribution substrate400, and a third semiconductor chip600(e.g., a logic chip) disposed on the second semiconductor chip500. For example, as illustrated inFIG.1, the second chip stack CS2including the second semiconductor chip500corresponding to a single memory chip will be described. Hereinafter, the components of the second chip stack CS2will be described in detail.

The redistribution substrate400may include a plurality of redistribution layers sequentially stacked.

Each of the redistribution layers may include an insulating pattern410and a conductive pattern420provided in the insulating pattern410. The conductive pattern420of one redistribution layer may be electrically connected to the conductive pattern420of another redistribution layer adjacent thereto. Hereinafter, the components of one redistribution layer will be described.

The insulating pattern410may include an insulating polymer or a photo-imageable dielectric (PID). For example, the photo-imageable dielectric (PID) may include at least one of photosensitive polyimide, polybenzoxazole (PBO), a phenol-based polymer, or a benzocyclobutene-based polymer. The insulating pattern410may have a single-layered structure or a multi-layered structure. When the insulating pattern410has the multi-layered structure, layers of the insulating pattern410may be formed of the same material or may be formed of different materials.

The conductive pattern420may be provided in the insulating pattern410. The conductive pattern420may have a damascene structure. The conductive pattern420may have an inverted T-shaped cross section. For example, the conductive pattern420may have a head portion422and a tail portion424, which are integrally connected to each other (i.e., may constitute a single body). The head portion422may correspond to an interconnection pattern horizontally redistributing electrical connection of the second semiconductor chip500to be described later, and the tail portion424may correspond to a via pattern vertically connecting the conductive patterns420of the redistribution layers. The head portion422and the tail portion424may vertically overlap with each other, and the tail portion424may extend from the head portion422toward a top surface of the insulating pattern410. An interface may not exist between the head portion422and the tail portion424. A bottom surface of the conductive pattern420may be disposed at the same level as a bottom surface of the corresponding insulating pattern410. The head portion422of the conductive pattern420of a lowermost redistribution layer may be exposed at a bottom surface of the redistribution substrate400. The head portion422of the conductive pattern420of the lowermost redistribution layer may be a pad to which a second connection terminal430to be described later is connected. The tail portion424of the conductive pattern420of an uppermost redistribution layer may be exposed at a top surface of the redistribution substrate400. The tail portion424of the conductive pattern420of the uppermost redistribution layer may be a portion on which the second semiconductor chip500is mounted. A top surface of the tail portion424may be disposed at the same level as a top surface of the corresponding insulating pattern410. The conductive pattern420may include a conductive material. For example, the conductive pattern420may include copper (Cu).

A barrier layer may be disposed between the insulating pattern410and the conductive pattern420. The barrier layer may surround the head portion422and the tail portion424of the conductive pattern420. A gap between the conductive pattern420and the insulating pattern410(i.e., a thickness of the barrier layer) may range from 50 Å to 1000 Å. The barrier layer may include titanium (Ti), tantalum (Ta), titanium nitride (TiN), and/or tantalum nitride (TaN).

Second connection terminals430may be provided under the redistribution substrate400. Each of the second connection terminals430may be connected to a conductive pattern420of the lowermost redistribution layer. The second connection terminals430may include solder balls or solder bumps.

The second semiconductor chip500may be disposed on the redistribution substrate400. The second semiconductor chip500may be disposed face-up on the redistribution substrate400. In other words, the top surface of the second semiconductor chip500may include an active surface.

The second semiconductor chip500may be disposed on the top surface of the redistribution substrate400. The second semiconductor chip500may be a memory chip such as a DRAM chip, an SRAM chip, an MRAM chip, or a flash memory chip. The second semiconductor chip500may have a front surface500aand a back surface500b. For example, the front surface may be a surface adjacent to an active surface of an integrated device in a semiconductor chip and may be defined as a surface on which pads of the semiconductor chip are formed. The back surface may be defined as another surface opposite to the front surface. The back surface500bof the second semiconductor chip500may face the redistribution substrate400. A width of the second semiconductor chip500may be less than a width of the redistribution substrate400. The second semiconductor chip500may include a first base layer510, a first circuit layer520provided on one surface of the first base layer510, and at least one first via530penetrating the first base layer510.

The first base layer510may include silicon (Si). An integrated device or integrated circuits may be formed in an upper portion of the first base layer510. The integrated device or integrated circuits may include a memory circuit.

The first circuit layer520may be provided on a top surface of the first base layer510. The first circuit layer520may be electrically connected to the integrated device or integrated circuits formed in the first base layer510. For example, the first circuit layer520may include a first circuit pattern524provided in a first insulating pattern522, and the first circuit pattern524may be connected to the integrated device or integrated circuits formed in the first base layer510. A portion of the first circuit pattern524may be exposed at a top surface of the first circuit layer520, and the exposed portion of the first circuit pattern524may correspond to a pad of the second semiconductor chip500. A top surface (i.e., the front surface)500aof the second semiconductor chip500, at which the first circuit layer520is provided, may be an active surface of the second semiconductor chip500.

The first via530may vertically penetrate the first base layer510. One end of the first via530may be exposed at a bottom surface of the first base layer510. A bottom surface of the first via530may be coplanar with the bottom surface of the first base layer510(i.e., the back surface500bof the second semiconductor chip500). The bottom surface of the first via530and the bottom surface of the first base layer510may be substantially flat. Another end of the first via530may extend toward the front surface500aof the second semiconductor chip500so as to be connected to the first circuit layer520. The first via530may be connected to the first circuit pattern524of the first circuit layer520.

A passivation layer may be provided on the bottom surface of the first base layer510. The passivation layer may cover the bottom surface of the first base layer510, and the first via530may penetrate the passivation layer so as to be exposed at a bottom surface of the passivation layer. The passivation layer may include an insulating material. For example, the passivation layer may include silicon nitride (SiN), silicon oxide (SiO), or silicon oxynitride (SiON).

The second semiconductor chip500may be mounted on the redistribution substrate400. For example, the first base layer510of the second semiconductor chip500may be in contact with the top surface of the redistribution substrate400. Here, the first via530of the second semiconductor chip500may be connected to the tail portion424of the conductive pattern420of the uppermost layer of the redistribution substrate410.

A second molding layer710may be disposed on the top surface of the redistribution substrate400. The second molding layer710may at least partially cover the top surface of the redistribution substrate400. The second molding layer710may be disposed adjacent to a side surface of the second semiconductor chip500. In detail, the second molding layer710may be disposed adjacent to both side surfaces of the second semiconductor chip500. For example, the second molding layer710may surround the second semiconductor chip500in a plan view. The second molding layer710may cover the side surfaces of the second semiconductor chip500. The second molding layer710may protect the second semiconductor chip500. Here, the second molding layer710may not cover or contact the front surface500aof the second semiconductor chip500. In other words, the second molding layer710may expose the front surface500aof the second semiconductor chip500. A top surface of the second molding layer710may be coplanar with the front surface500aof the second semiconductor chip500, and the top surface of the second molding layer710and the front surface500aof the second semiconductor chip500may be substantially flat. The side surface of the second molding layer710may be vertically aligned with a side surface of the redistribution substrate400. For example, the side surface of the second molding layer710and the side surface of the redistribution substrate400may be located in the same plane. The second molding layer710may include an insulating material. For example, the second molding layer710may include an insulating material having high machinability, such as polyimide.

UnlikeFIG.1, a width502of the second semiconductor chip500may be equal to a width402of the redistribution substrate400, and the side surface of the second semiconductor chip500may be vertically aligned with the side surface of the redistribution substrate400. As illustrated inFIG.3, the second molding layer710may surround the second semiconductor chip500. The second molding layer710may be in contact with a bottom surface600aof the third semiconductor chip600to be described later. A bottom surface of the second molding layer710may be located at the same level as the bottom surface of the second semiconductor chip500. Thus, the side surface of the redistribution substrate400may be exposed. In other words, the second molding layer710may not cover or contact the side surface of the redistribution substrate400. Alternatively, as illustrated inFIG.4, the second molding layer710may extend onto the side surface of the redistribution substrate400. Thus, the second molding layer710may protect the second semiconductor chip500and the redistribution substrate400. In this case, the bottom surface of the second molding layer710may be located at the same level as the bottom surface of the redistribution substrate400.

Referring again toFIGS.1and2, the third semiconductor chip600may be disposed on the second semiconductor chip500. The third semiconductor chip600may be disposed face-down on the second semiconductor chip500. In other words, the bottom surface of the third semiconductor chip600may include an active surface. The third semiconductor chip600may be a logic chip. The third semiconductor chip600may have a front surface600aand a back surface. The front surface600aof the third semiconductor chip600may face the second semiconductor chip500. A width of the third semiconductor chip600may be equal to the width of the redistribution substrate400. A side surface of the third semiconductor chip600may be vertically aligned with the side surface of the redistribution substrate400and an outer side surface of the second molding layer710. For example, the side surface of the second semiconductor chip500may have a shape recessed from the side surface of the third semiconductor chip600and the side surface of the redistribution substrate400. The second molding layer710may be in contact with the front surface600aof the third semiconductor chip600and the top surface of the redistribution substrate400. The third semiconductor chip600may include a second base layer610and a second circuit layer620provided on one surface of the second base layer610.

The second base layer610may include silicon (Si). An integrated device or integrated circuits may be formed in a lower portion of the second base layer610. The integrated device or integrated circuits may include a logic circuit.

The second circuit layer620may be provided on a bottom surface of the second base layer610. The second circuit layer620may be electrically connected to the integrated device or integrated circuits formed in the second base layer610. For example, the second circuit layer620may include a second circuit pattern624provided in a second insulating pattern622, and the second circuit pattern624may be connected to the integrated device or integrated circuits formed in the second base layer610. A portion of the second circuit pattern624may be exposed at a bottom surface of the second circuit layer620, and the exposed portion of the second circuit pattern624may correspond to a pad of the third semiconductor chip600. The bottom surface (i.e., the front surface)600aof the third semiconductor chip600, at which the second circuit layer620is provided, may be an active surface of the third semiconductor chip600.

The third semiconductor chip600may form a chip-on-wafer (COW) structure with the second semiconductor chip500. The width of the second semiconductor chip500may be less than the width of the third semiconductor chip600. For example, the width of the second semiconductor chip500may be greater than 60% of the width of the third semiconductor chip600and less than 100% of the width of the third semiconductor chip600. The second semiconductor chip500may be in direct contact with the third semiconductor chip600. In other words, a top surface of the first circuit layer520of the second semiconductor chip500may be in contact with a bottom surface of the second circuit layer620of the third semiconductor chip600at a boundary of the second semiconductor chip500and the third semiconductor chip600. The first circuit layer520may be hybrid-bonded to the second circuit layer620. For example, the hybrid bonding may mean that two components including the same kind of a material are fused together at their interface. For example, the first circuit pattern524of the first circuit layer520and the second circuit pattern624of the second circuit layer620may constitute a continuous component, and an interface IF between the first and second circuit patterns524and624may not be visible. For example, the first and second circuit patterns524and624which are in contact with each other at a boundary of the first and second insulating patterns522and622may be formed of the same material, and thus the interface IF of the first and second circuit patterns524and624may not exist. In other words, the first and second circuit patterns524and624may be provided as a single component. Thus, the first circuit pattern524and the second circuit pattern624may constitute the continuous component. The second semiconductor chip500and the third semiconductor chip600may be electrically connected to each other through the first circuit pattern524and the second circuit pattern624.

According to the embodiments of the disclosure, the first circuit pattern524and the second circuit pattern624may be formed in one body, and thus the second and third semiconductor chips500and600may be firmly bonded to each other. As a result, electrical characteristics and structural stability of the semiconductor package may be improved.

Since the second and third semiconductor chips500and600are bonded directly to each other, an additional connection terminal between the second and third semiconductor chips500and600and a protective material for protecting the additional connection terminal may not be required. Thus, a height of the second chip stack CS2may be reduced to provide a small semiconductor package. In addition, heat generated from the second and third semiconductor chips500and600may be easily released or dissipated by way of the third semiconductor chip600. Furthermore, the second molding layer710may expose (i.e., may not cover or contact) the side surface of the third semiconductor chip600. Thus, heat generated from the third semiconductor chip600which may generate a lot of heat may be easily released or dissipated.

The second chip stack CS2may be provided as described above. The second chip stack CS2may be mounted on the interposer substrate200. For example, the second chip stack CS2may be connected to the first substrate pads210of the interposer substrate200through the second connection terminals430of the redistribution substrate400. A top surface of the second chip stack CS2(i.e., a top surface of the third semiconductor chip600) may be disposed at the same level as a top surface of the first chip stack CS1.

A third underfill layer432may be provided between the interposer substrate200and the second chip stack CS2. The third underfill layer432may fill a space between the interposer substrate200and the redistribution substrate400and may surround the second connection terminals430.

The first chip stack CS1and the second chip stack CS2may be electrically connected to each other through a circuit interconnection line212provided in the interposer substrate200.

A third molding layer800may be provided on the interposer substrate200. The third molding layer800may cover the top surface of the interposer substrate200. The third molding layer800may surround the first chip stack CS1and the second chip stack CS2. The third molding layer800may include an insulating material. For example, the third molding layer800may include an epoxy molding compound (EMC). InFIG.1, the third molding layer800covers the first chip stack CS1and the second chip stack CS2. Alternatively, the top surface of the first chip stack CS1and the top surface of the second chip stack CS2may be exposed from the third molding layer800.

The semiconductor package may be provided as described above.

FIG.5is a cross-sectional view illustrating a semiconductor package according to some example embodiments. In the following example embodiments, the same components as in the example embodiments ofFIGS.1to4will be indicated by the same reference numerals or designators, and the descriptions thereto will be omitted or mentioned briefly for the purpose of ease and convenience in explanation. In other words, differences between the following embodiments and the embodiments ofFIGS.1to4will be mainly described.

Referring toFIG.5, the second chip stack CS2may include a plurality of memory chips. For example, a fourth semiconductor chip550may further be provided between the second semiconductor chip500and the third semiconductor chip600.

The fourth semiconductor chip550may be disposed on the top surface of the second semiconductor chip500. The fourth semiconductor chip550may include substantially the same semiconductor chip as the second semiconductor chip500. The fourth semiconductor chip550may be a memory chip such as a DRAM chip, a SRAM chip, a MRAM chip, or a flash memory chip. The fourth semiconductor chip550may have a front surface and a back surface. The back surface of the fourth semiconductor chip550may face the second semiconductor chip500. A width of the fourth semiconductor chip550may be equal to the width of the second semiconductor chip500. A side surface of the fourth semiconductor chip550may be vertically aligned with the side surface of the second semiconductor chip500. The fourth semiconductor chip550may include a third base layer560, a third circuit layer570provided on one surface of the third base layer560, and at least one third via580penetrating the third base layer560.

The third base layer560may include silicon (Si). An integrated device or integrated circuits may be formed in an upper portion of the third base layer560. The integrated device or integrated circuits may include a memory circuit.

The third circuit layer570may be provided on a top surface of the third base layer560. The third circuit layer570may be electrically connected to the integrated device or integrated circuits formed in the third base layer560. For example, the third circuit layer570may include a third circuit pattern574provided in a third insulating pattern572, and the third circuit pattern574may be connected to the integrated device or integrated circuits formed in the third base layer560. A portion of the third circuit pattern574may be exposed at a top surface of the third circuit layer570, and the exposed portion of the third circuit pattern574may correspond to a pad of the fourth semiconductor chip550. A top surface (i.e., the front surface) of the fourth semiconductor chip550, at which the third circuit layer570is provided, may be an active surface of the fourth semiconductor chip550.

A third via of the at least one third via580may vertically penetrate the third base layer560. One end of the third via580may be exposed at a bottom surface of the third base layer560. A bottom surface of the third via580may be coplanar with the bottom surface of the third base layer560(i.e., the back surface of the fourth semiconductor chip550). The bottom surface of the third via580and the bottom surface of the third base layer560may be substantially flat. Another end of the third via580may extend toward the front surface of the fourth semiconductor chip550so as to be connected to the third circuit layer570. The third via580may be connected to the third circuit pattern574of the third circuit layer570.

A passivation layer may be provided on the bottom surface of the third base layer560. The passivation layer may cover the bottom surface of the third base layer560, and the third via580may penetrate the passivation layer so as to be exposed at a bottom surface of the passivation layer. The passivation layer may include an insulating material.

The fourth semiconductor chip550may be bonded to the second semiconductor chip500. For example, the third base layer560of the fourth semiconductor chip550may be in contact with the top surface of the first circuit layer520of the second semiconductor chip500. Here, the third via580of the fourth semiconductor chip550may be connected to the first circuit pattern522of the first circuit layer520of the second semiconductor chip500. In more detail, the top surface of the first circuit layer520of the second semiconductor chip500may be in contact with the bottom surface of the third via580of the fourth semiconductor chip550at a boundary of the second semiconductor chip500and the fourth semiconductor chip550. The first circuit layer520may be hybrid-bonded to the third via580. For example, the first circuit layer520and the third via580may constitute a continuous component, and an interface between the first circuit layer520and the third via580may not be visible. Thus, the first circuit layer520and the third via580may have the continuous component. The second semiconductor chip500and the fourth semiconductor chip550may be electrically connected to each other through the first circuit layer520and the third via580.

A fourth molding layer720may be disposed on the second molding layer710. The fourth molding layer720may cover the top surface of the second molding layer710. The fourth molding layer720may be disposed adjacent to a side surface of the fourth semiconductor chip550. In detail, the fourth molding layer720may be disposed adjacent to both side surfaces of the fourth semiconductor chip550. For example, the fourth molding layer720may surround the fourth semiconductor chip550in a plan view. The fourth molding layer720may cover the side surfaces of the fourth semiconductor chip550. The fourth molding layer720may protect the fourth semiconductor chip550. Here, the fourth molding layer720may expose the front (i.e., top) surface of the fourth semiconductor chip550. A top surface of the fourth molding layer720may be coplanar with the front surface of the fourth semiconductor chip550, and the top surface of the fourth molding layer720and the front surface of the fourth semiconductor chip550may be substantially flat. An interface of the fourth molding layer720and the second molding layer710may be provided in the same plane as an interface of the second semiconductor chip500and the fourth semiconductor chip550. A side surface of the fourth molding layer720may be vertically aligned with the side surface of the second molding layer710and the side surface of the redistribution substrate400. For example, the side surface of the fourth molding layer720, the side surface of the second molding layer710and the side surface of the redistribution substrate400may be located in the same plane. The fourth molding layer720may include an insulating material.

The third semiconductor chip600may form a chip-on-wafer (COW) structure with the fourth semiconductor chip550. The width of the fourth semiconductor chip550may be less than the width of the third semiconductor chip600. The fourth semiconductor chip550may be in direct contact with the third semiconductor chip600. In other words, a top surface of the third circuit layer570of the fourth semiconductor chip550may be in contact with the bottom surface of the second circuit layer620of the third semiconductor chip600at a boundary of the fourth semiconductor chip550and the third semiconductor chip600. The third circuit layer570may be hybrid-bonded to the second circuit layer620. For example, the third circuit pattern574of the third circuit layer570and the second circuit pattern624of the second circuit layer620may constitute a continuous component, and an interface between the third and second circuit patterns574and624may not be visible. In other words, the third and second circuit patterns574and624may be provided as a single component. The fourth semiconductor chip550and the third semiconductor chip600may be electrically connected to each other through the third circuit pattern574and the second circuit pattern624.

FIG.6is a cross-sectional view illustrating a semiconductor package according to some example embodiments.FIG.7is an enlarged view of a region ‘B’ ofFIG.6.

Referring toFIGS.6and7, a width of the second semiconductor chip500may be equal to the width of the redistribution substrate400. A side surface of the second semiconductor chip500may be vertically aligned with the side surface of the redistribution substrate400. In the embodiments ofFIGS.6and7, in contrast to an embodiment shown inFIG.1, the second molding layer710(seeFIG.1) surrounding the second semiconductor chip500may not be provided.

The third semiconductor chip600may be disposed on the second semiconductor chip500. A width of the third semiconductor chip600may be less than the width of the redistribution substrate400and less than the width of the second semiconductor chip500. For example, a side surface of the third semiconductor chip600may have a shape recessed from the side surface of the second semiconductor chip500. The third semiconductor chip600may be bonded onto the second semiconductor chip500. Like the description inFIG.2, the third semiconductor chip600may form a chip-on-wafer (COW) structure with the second semiconductor chip500. The width of the second semiconductor chip500may be greater than the width of the third semiconductor chip600. The second semiconductor chip500may be in direct contact with the third semiconductor chip600. The first circuit layer520may be hybrid-bonded to the second circuit layer620.

A fifth molding layer730may be disposed on the top surface of the second semiconductor chip500. The fifth molding layer730may at least partially cover the top surface of the second semiconductor chip500. The fifth molding layer730may be disposed adjacent to a side surface of the third semiconductor chip600. In detail, the fifth molding layer730may be disposed adjacent to both side surfaces of the third semiconductor chip600. For example, the fifth molding layer730may surround the third semiconductor chip600in a plan view. The fifth molding layer730may cover the side surfaces of the third semiconductor chip600. The fifth molding layer730may protect the third semiconductor chip600. Here, the fifth molding layer730may expose the back (i.e., top) surface of the third semiconductor chip600. In other words, the fifth molding layer730may not cover or contact the back surface of the third semiconductor chip600. A bottom surface of the fifth molding layer730may be coplanar with the front (i.e., bottom) surface of the third semiconductor chip600, and the bottom surface of the fifth molding layer730and the front surface of the third semiconductor chip600may be substantially flat. A side surface of the fifth molding layer730may be vertically aligned with the side surface of the second semiconductor chip500. For example, the side surface of the fifth molding layer730, the side surface of the second semiconductor chip500and the side surface of the redistribution substrate400may be located in the same plane. The fifth molding layer730may include an insulating material.

FIG.8is a cross-sectional view illustrating a semiconductor package according to some example embodiments.

Referring toFIG.8, a first chip stack CS1may be provided in plurality. The first chip stacks CS1may be spaced apart from each other. The second chip stack CS2may be disposed between the first chip stacks CS1. Each of the first chip stacks CS1may be the same as or similar to the first chip stack CS1described with reference toFIG.1. For example, each of the first chip stacks CS1may include the base semiconductor chip310, the first semiconductor chips320stacked on the base semiconductor chip310, and the first molding layer330surrounding the first semiconductor chips320. The first chip stacks CS1and the second chip stack CS2may be electrically connected to each other through circuit interconnection lines212provided in the interposer substrate200.

FIGS.9to19are cross-sectional views illustrating a method for manufacturing a semiconductor package according to some example embodiments.

Referring toFIG.9, a first wafer WF1may be provided. The first wafer WF1may be a semiconductor wafer. For example, the first wafer WF1may be a silicon wafer, a germanium wafer, or a silicon-germanium wafer. The first wafer WF1may include first device regions DR1spaced apart from each other in one direction, and a first scribe region SR1defining the first device regions DR1. The first device regions DR1of the first wafer WF1may be regions in which third semiconductor chips600are formed. The first scribe region SR1of the first wafer WF1may be a region on which a sawing process for singulation of the third semiconductor chips600will be performed later.

The third semiconductor chips600may be formed on the first device regions DR1of the first wafer WF1, respectively. The third semiconductor chips600may be formed on a top surface of the first wafer WF1. Integrated circuits of the third semiconductor chips600may be formed on the top surface of the first wafer WF1. The integrated circuits of the third semiconductor chips600may be logic circuits.

Second circuit layers620of the third semiconductor chips600may be formed on the top surface of the first wafer WF1. For example, an insulating layer (e.g., silicon oxide (SiO)) may be formed on the top surface of the first wafer WF1, and then, the insulating layer may be patterned to form a portion of a second insulating pattern622. A conductive layer may be formed on a top surface of the second insulating pattern622, and then, the conductive layer may be patterned to form a second circuit pattern624. The second circuit pattern624may be electrically connected to the integrated circuit of the third semiconductor chip600. The processes of forming and patterning the insulating layer and the processes of forming and patterning the conductive layer may be repeated to form the second circuit layer620.

Referring toFIG.10, a second wafer WF2may be provided. The second wafer WF2may be a semiconductor wafer. For example, the second wafer WF2may be a silicon wafer, a germanium wafer, or a silicon-germanium wafer. The second wafer WF2may include second device regions DR2spaced apart from each other in one direction, and a second scribe region SR2defining the second device regions DR2. The second device regions DR2of the second wafer WF2may be regions in which second semiconductor chips500are formed. The second scribe region SR2of the second wafer WF2may be a region on which a sawing process for singulation of the second semiconductor chips500will be performed later.

The second semiconductor chips500may be formed on the second device regions DR2of the second wafer WF2, respectively. The second semiconductor chips500may be formed on a top surface of the second wafer WF2. Integrated circuits of the second semiconductor chips500may be formed on the top surface of the second wafer WF2. The integrated circuit of the second semiconductor chip500may be a memory circuit.

Holes may be formed in the second wafer WF2. The holes may be formed by performing a laser drilling process on the top surface of the second wafer WF2. Alternatively, a mask pattern may be formed on the top surface of the second wafer WF2, and then, an anisotropic etching process may be performed on the second wafer WF2by using the mask pattern as an etch mask, thereby forming the holes. The holes may not completely penetrate the second wafer WF2in a vertical direction. In other words, bottoms of the holes may not reach a bottom surface of the second wafer WF2.

First vias530may be formed in the second wafer WF2. For example, a conductive material may be coated or deposited on the top surface of the second wafer WF2. At this time, the conductive material may fill the holes of the second wafer WF2. Thereafter, a portion of the conductive material on the top surface of the second wafer WF2may be removed, and thus the conductive material may remain only in the holes.

First circuit layers520of the second semiconductor chips500may be formed on the top surface of the second wafer WF2. For example, an insulating layer (e.g., silicon oxide (SiO)) may be formed on the top surface of the second wafer WF2, and then, the insulating layer may be patterned to form a portion of a first insulating pattern522. A conductive layer may be formed on a top surface of the first insulating pattern522, and then, the conductive layer may be patterned to form a first circuit pattern524. The first circuit pattern524may be electrically connected to the integrated circuit of the second semiconductor chip500and the first vias530. The processes of forming and patterning the insulating layer and the processes of forming and patterning the conductive layer may be repeated to form the first circuit layer520.

Referring toFIG.11, a singulation process may be performed on the resultant structure ofFIG.10. For example, a sawing process may be performed along the second scribe region SR2(seeFIG.10) of the second wafer WF2. The second scribe region SR2of the second wafer WF2may be sawed. Thus, a plurality of the second semiconductor chips500may be separated from each other. Widths of the second semiconductor chips500may be less than widths of the third semiconductor chips600.

The second semiconductor chips500may be bonded onto the first wafer WF1. The second semiconductor chips500may be bonded onto the first wafer WF1by a chip-on-wafer (COW) method. For example, the second semiconductor chips500may be aligned on the third semiconductor chips600of the first wafer WF1, respectively. At this time, side surfaces of the second semiconductor chips500may be spaced apart from the first scribe region SR1. The first circuit layers520of the second semiconductor chips500may face the second circuit layers620of the third semiconductor chips600. The second semiconductor chips500may be in contact with the third semiconductor chips600. At this time, an exposed portion of the first circuit pattern524of the first circuit layer520may be in contact with an exposed portion of the second circuit pattern624of the second circuit layer620. The exposed portion of the first circuit pattern524of the first circuit layer520may be bonded to the exposed portion of the second circuit pattern624of the second circuit layer620. For example, the first circuit pattern524and the second circuit pattern624may be bonded to each other to form one body. The bonding of the first circuit pattern524and the second circuit pattern624may be naturally performed. In more detail, the first circuit pattern524and the second circuit pattern624may be formed of the same material (e.g., copper (Cu)), and the first circuit pattern524and the second circuit pattern624may be bonded to each other by a hybrid-bonding process (e.g., a copper (Cu)-copper (Cu) hybrid-bonding process) performed by surface activation at an interface of the first and second circuit patterns524and624being in contact with each other. The first circuit pattern524and the second circuit pattern624may be bonded to each other, and thus the interface between the first circuit pattern524and the second circuit pattern624may disappear.

In some embodiments, to easily bond the first and second circuit patterns524and624, a surface activation process may be performed on surfaces of the first and second circuit patterns524and624. The surface activation process may include a plasma process. In addition, pressure and heat may be applied to the first wafer WF1to easily bond the first and second circuit patterns524and624. The applied pressure may be less than, for example, about 30 MPa. The applied heat may be provided by an annealing process performed at a temperature of about 100 degrees Celsius to about 500 degrees Celsius. In certain embodiments, different pressure and/or a different temperature of heat may be used in the hybrid-bonding process.

The first circuit pattern524and the second circuit pattern624may be bonded to each other to constitute one body, and thus the second semiconductor chips500may be firmly bonded to the respective third semiconductor chips600of the first wafer WF1. As a result, a semiconductor package with improved structural stability may be manufactured.

Referring toFIG.12, a second molding layer710may be formed on the first wafer WF1. For example, a molding material may be applied onto the top surface of the first wafer WF1to cover the second semiconductor chips500, and the molding material may be hardened to form the second molding layer710. The second molding layer710may at least partially cover the top surface of the first wafer WF1, side surfaces of the second semiconductor chips500, and back surfaces of the second semiconductor chips500. The molding material may include an insulating material.

Referring toFIG.13, a portion of the second molding layer710and portions of the second semiconductor chips500may be removed. In other words, the second semiconductor chips500may be thinned in a vertical direction. For example, a grinding process or a chemical mechanical polishing (CMP) process may be performed on a top surface of the second molding layer710. Thus, the back (i.e., top) surfaces of the second semiconductor chips500and the top surface of the second molding layer710may be planarized. By the thinning process, an upper portion of the second molding layer710may be removed and upper portions of the second semiconductor chips500may also be removed.

After the thinning process is performed, the back surfaces500bof the second semiconductor chips500may be exposed from the top surface of the second molding layer710. The back surfaces500bof the second semiconductor chips500and the top surface of the second molding layer710may be substantially flat and may be coplanar with each other. At this time, the first vias530of the second semiconductor chips500may be exposed at the back surfaces500bof the second semiconductor chips500. Exposed top surfaces of the first vias530may be flat.

According to the example embodiments of the disclosure, the second semiconductor chips500may first be bonded to the third semiconductor chips600by using the metal-to-metal bonding process having strong bonding strength, and then, the thinning process may be performed on the second semiconductor chips500. Thus, the possibility of detachment and breakage of the second semiconductor chips500may be reduced or minimized, and the second semiconductor chips500having thin thicknesses may be formed. As a result, a size of the semiconductor package may be reduced.

In the example embodiments ofFIGS.11to13, the second molding layer710may be formed after the second semiconductor chips500are bonded to the third semiconductor chips600. However, embodiments of the disclosure are not limited thereto.

In certain example embodiments, a singulation process may be performed on the resultant structure ofFIG.10. For example, the second scribe region SR2of the second wafer WF2may be sawed. Thus, a plurality of the second semiconductor chips500may be separated from each other.

Referring toFIG.14, a first carrier substrate910may be provided. The first carrier substrate910may be an insulating substrate including a glass or a polymer or may be a conductive substrate including a metal. An adhesive member may be provided on a top surface of the first carrier substrate910. For example, the adhesive member may include an adhesive tape.

The second semiconductor chips500may be adhered onto the first carrier substrate910. For example, a surface of the first circuit layer520may be adhered to the adhesive member of the first carrier substrate910.

A second molding layer710may be formed on the first carrier substrate910. For example, a molding material may be applied onto the top surface of the first carrier substrate910to cover the second semiconductor chips500, and the molding material may be hardened to form the second molding layer710. The second molding layer710may cover side surfaces and top surfaces of the second semiconductor chips500.

Referring toFIG.15, a portion of the second molding layer710may be removed. In other words, the second molding layer710may be thinned. For example, a grinding process or a chemical mechanical polishing (CMP) process may be performed on a top surface of the second molding layer710. Thus, the top surface of the second molding layer710may be planarized. The thinning process may be performed until the second semiconductor chips500are exposed from the second molding layer710. Upper portions of the second semiconductor chips500may also be removed by the thinning process.

After the thinning process is performed, the first vias530of the second semiconductor chips500may be exposed from the top surface of the second molding layer710. Back (i.e., top) surfaces of the second semiconductor chips500, top surfaces of the first vias530and the top surface of the second molding layer710may be substantially flat and may be substantially coplanar with each other.

After the thinning process, the first carrier substrate910may be removed. For example, the first carrier substrate910may be detached by melting the adhesive member, or the first carrier substrate910may be physically removed.

Referring again toFIG.13, the second semiconductor chips500may be bonded onto the first wafer WF1manufactured through the processes ofFIG.9. The second semiconductor chips500may be aligned on the third semiconductor chips600of the first wafer WF1, respectively. The first circuit layers520of the second semiconductor chips500may face the second circuit layers620of the third semiconductor chips600. The second semiconductor chips500and the second molding layer710may be in contact with the third semiconductor chips600. The exposed portion of the first circuit pattern524of the first circuit layer520may be bonded to the exposed portion of the second circuit pattern624of the second circuit layer620. The bonding of the first circuit pattern524and the second circuit pattern624may be naturally performed. In more detail, the first circuit pattern524and the second circuit pattern624may be bonded to each other by the hybrid-bonding process performed by the surface activation at the interface of the first and second circuit patterns524and624being in contact with each other. The first circuit pattern524and the second circuit pattern624may be bonded to each other, and thus the interface between the first circuit pattern524and the second circuit pattern624may disappear.

Referring toFIG.16, a redistribution substrate400may be formed on the resultant structure ofFIG.13. For example, an insulating pattern410may be formed on the second semiconductor chips500and the second molding layer710. The insulating pattern410may include an insulating polymer or a photo-imageable dielectric (PID). A conductive pattern420may be formed in the insulating pattern410. For example, the insulating pattern410may be patterned to form openings for forming the conductive pattern420, a seed layer may be conformally formed in the openings, and a plating process may be performed using the seed layer as a seed to form the conductive pattern420filling the openings. One redistribution layer may be formed as described above.

Another insulating pattern410may be formed on the one redistribution layer. The insulating pattern410may be formed by a coating process such as a spin coating process or a slit coating process. The insulating pattern410may include a photo-imageable dielectric (PID). The insulating pattern410may have a first opening exposing the conductive pattern420of the redistribution layer provided thereunder, and a second opening provided on the first opening and having a width greater than that of the first opening. A seed layer may be conformally formed in the first opening and the second opening, and a plating process may be performed using the seed layer as a seed to form a conductive pattern420filling the first and second openings. Other redistribution layer(s) may be formed on the one redistribution layer as described above. The conductive pattern420of an uppermost redistribution layer may be exposed at a top surface of the corresponding insulating pattern410.

However, embodiments of the disclosure are not limited to the above example of forming the redistribution substrate400.

InFIG.16, the redistribution substrate400is formed on the second semiconductor chips500and the second molding layer710. However, embodiments of the disclosure are not limited thereto. As illustrated inFIG.17, the redistribution substrate400may be formed in plurality, and the redistribution substrates400may be formed on the second semiconductor chips500, respectively. For example, in the patterning process of the insulating pattern410, an insulating material located on the second molding layer710may be removed.

Referring again toFIG.16, second connection terminals430may be formed on the redistribution substrate400. For example, solder balls or solder bumps may be provided on the exposed conductive patterns420of the uppermost redistribution layer.

Referring toFIG.18, a singulation process may be performed on the resultant structure ofFIG.16. For example, a sawing process may be performed along the first scribe region SR1(seeFIG.16) of the first wafer WF1. The redistribution substrate400and the second molding layer710on the first scribe region SR1and the first wafer WF1may be sequentially sawed. Thus, a plurality of second chip stacks CS2may be separated from each other.

Referring toFIG.19, a first chip stack CS1may be formed. For example, base semiconductor chips310may be formed on a wafer-level semiconductor substrate formed of a semiconductor material (e.g., silicon). Each of the base semiconductor chips310may include a base circuit layer312and a base through-electrode314. The base circuit layer312may be provided on a bottom surface of the base semiconductor chip310. The bottom surface of the base semiconductor chip310may be an active surface.

First semiconductor chips320may be mounted on the base semiconductor chip310. Each of the first semiconductor chips320may include a circuit layer322and a through-electrode324. A bottom surface of each of the first semiconductor chips320may be an active surface. First bumps326may be provided on the bottom surface of each of the first semiconductor chips320. The first bumps326may be provided between the base semiconductor chip310and the first semiconductor chips320to electrically connect the base semiconductor chip310and the first semiconductor chips320to each other. Other first semiconductor chips320may be stacked on the first semiconductor chips320. For example, the plurality of first semiconductor chips320may be stacked on the base semiconductor chip310. At this time, the first bumps326may also be formed between adjacent first semiconductor chips320in a vertical direction.

A first molding layer330may be formed on top surfaces of the base semiconductor chips310to cover the first semiconductor chips320. A top surface of the first molding layer330may be higher than a top surface of an uppermost first semiconductor chip320. The first molding layer330may surround the first semiconductor chips320when viewed in a plan view. The first molding layer330may include an insulating polymer material. For example, the first molding layer330may include an epoxy molding compound (EMC).

A portion of the first molding layer330and a portion of the uppermost first semiconductor chip320may be removed. For example, a grinding process may be performed on the top surface of the first molding layer330. An upper portion of the first molding layer330may be removed. Thus, the top surface of the first molding layer330may be coplanar with the top surface of the uppermost first semiconductor chip320as shown inFIG.19.

Referring again toFIG.1, a singulation process may be performed on the resultant structure ofFIG.19. For example, the first molding layer330and the base semiconductor chip310may be sawed to separate the first chip stacks CS1from each other. In other words, the first molding layer330and the base semiconductor chip310may be sawed along a sawing line SL located between the first semiconductor chips320, and thus the first semiconductor chips320may be separated from each other and the base semiconductor chips310may be separated from each other.

An interposer substrate200may be provided as shown, for example, inFIGS.1,3-6, and8. The interposer substrate200may include first substrate pads210exposed at a top surface of the interposer substrate200, and second substrate pads220exposed at a bottom surface of the interposer substrate200.

The first chip stack CS1and the second chip stack CS2may be mounted on the interposer substrate200. The first chip stack CS1and the second chip stack CS2may be mounted on the interposer substrate200by a flip chip method. The first connection terminals316may be provided on a bottom surface of the first chip stack CS1, and the second connection terminals430may be provided on a bottom surface of the second chip stack CS2. The first and second connection terminals316and430may include solder balls or solder bumps. A second underfill layer318may be provided on the bottom surface of the first chip stack CS1to surround the first connection terminals316, and a third underfill layer432may be provided on the bottom surface of the second chip stack CS2to surround the second connection terminals430. For example, each of the second and third underfill layers318and432may be a non-conductive adhesive or a non-conductive film. When each of the second and third underfill layers318and432is the non-conductive adhesive, the second and third underfill layers318and432may be formed by applying a liquid non-conductive adhesive to the bottom surfaces of the first and second chip stacks CS1and CS2through a dispensing process. When each of the second and third underfill layers318and432is the non-conductive film, the second and third underfill layers318and432may be formed by attaching the non-conductive films onto the bottom surfaces of the first and second chip stacks CS1and CS2. The first connection terminals316and the second connection terminals430may be connected to the first substrate pads210of the interposer substrate200.

A third molding layer800may be formed as shown, for example, inFIGS.1,3-6, and8. For example, an insulating material may be applied onto the interposer substrate200to form the third molding layer800. The third molding layer800may cover the first chip stack CS1and the second chip stack CS2. In certain embodiments, a grinding process may be performed on the third molding layer800. An upper portion of the third molding layer800may be removed. In this case, a top surface of the third molding layer800may be coplanar with a top surface of the first chip stack CS1and a top surface of the second chip stack CS2.

The interposer substrate200may be mounted on a package substrate100. The interposer substrate200may be mounted on the package substrate100by a flip chip method. For example, substrate terminals230may be provided on a bottom surface of the interposer substrate200. The substrate terminals230may be provided on the second substrate pads220of the interposer substrate200. The substrate terminals230may be connected to pads of the package substrate100. A first underfill layer240may be formed between the interposer substrate200and the package substrate100. For example, the first underfill layer240may be provided on the bottom surface of the interposer substrate200to surround the substrate terminals230, and then, the interposer substrate200may be mounted on the package substrate100.

External terminals102may be provided on a bottom surface of the package substrate100. For example, the external terminals102may be disposed on terminal pads disposed on the bottom surface of the package substrate100. The external terminals102may include solder balls or solder bumps.

The semiconductor package ofFIG.1may be manufactured by the processes described above.

FIGS.20to22are cross-sectional views illustrating a method for manufacturing a semiconductor package according to some example embodiments.

Referring toFIG.20, fourth semiconductor chips550may be provided on the resultant structure ofFIG.13. A process of forming the fourth semiconductor chips550may be the same as or similar to the process of forming the second semiconductor chips500described with reference toFIG.10. Each of the fourth semiconductor chips550may include a third base layer560, a third circuit layer570provided on a front surface of the third base layer560, and at least one third via580penetrating the third base layer560.

InFIG.20, widths of the fourth semiconductor chips550are equal to widths of the second semiconductor chips500. However, embodiments of the disclosure are not limited thereto. According to the example embodiments of the disclosure, the grinding or polishing process may be performed such that the top surfaces of the second semiconductor chips500and the top surface of the second molding layer710are flat, and then, the fourth semiconductor chips550may be mounted on the flat top surfaces. Thus, even though the widths of the fourth semiconductor chips550are greater or less than the widths of the second semiconductor chips500, the fourth semiconductor chips550may be easily aligned.

The fourth semiconductor chips550may be in contact with the second semiconductor chips500. For example, the third circuit patterns574of the third circuit layers570of the fourth semiconductor chips550may be in contact with the first vias530of the second semiconductor chips500. The third circuit patterns574may be bonded to the first vias530. For example, the third circuit patterns574and the first vias530may be formed of the same material, and the third circuit patterns574may be bonded to the first vias530by a metal-to-metal hybrid-bonding process performed by surface activation at interfaces of the third circuit patterns574and the first vias530which are in contact with each other.

Referring toFIG.21, a fourth molding layer720may be formed on the second molding layer710. For example, a molding material may be applied onto the top surface of the second molding layer710to cover the fourth semiconductor chips550, and the molding material may be hardened to form the fourth molding layer720. The fourth molding layer720may cover the top surface of the second molding layer710, side surfaces of the fourth semiconductor chips550, and back (i.e., top) surfaces of the fourth semiconductor chips550. The molding material may include an insulating material.

Referring toFIG.22, a portion of the fourth molding layer720and portions of the fourth semiconductor chips550may be removed. In other words, the fourth semiconductor chips550may be thinned in a vertical direction. For example, a grinding process or a chemical mechanical polishing (CMP) process may be performed on a top surface of the fourth molding layer720. Thus, the back surfaces of the fourth semiconductor chips550and the top surface of the fourth molding layer720may be planarized. By the thinning process, an upper portion of the fourth molding layer720may be removed and upper portions of the fourth semiconductor chips550may also be removed. After the thinning process is performed, the back surfaces of the fourth semiconductor chips550may be exposed from the top surface of the fourth molding layer720. The back surfaces of the fourth semiconductor chips550and the top surface of the fourth molding layer720may be substantially flat and may be substantially coplanar with each other.

The processes described with reference toFIGS.16to18may be performed on the resultant structure ofFIG.22. For example, the redistribution substrate400may be formed on the fourth semiconductor chips550, and the second connection terminals430may be formed on the redistribution substrate400. Thereafter, a singulation process may be performed to separate a plurality of second chip stacks CS2from each other.

Referring again toFIG.5, the first chip stack CS1and the second chip stack CS2may be mounted on the interposer substrate200. The first chip stack CS1and the second chip stack CS2may be mounted on the interposer substrate200by a flip chip method. An insulating material may be applied onto the interposer substrate200to form a third molding layer800. The third molding layer800may cover the first chip stack CS1and the second chip stack CS2. The interposer substrate200may be mounted on the package substrate100. The interposer substrate200may be mounted on the package substrate100by a flip chip method. External terminals102may be provided on a bottom surface of the package substrate100.

The semiconductor package ofFIG.5may be manufactured by the processes described above.

FIGS.23to27are cross-sectional views illustrating a method for manufacturing a semiconductor package according to some example embodiments.

Referring toFIG.23, a first wafer WF1may be provided. The first wafer WF1may be a semiconductor wafer. The first wafer WF1may include third device regions DR3spaced apart from each other in one direction, and a third scribe region SR3defining the third device regions DR3.

Third semiconductor chips600may be formed on the third device regions DR3of the first wafer WF1, respectively. Integrated circuits of the third semiconductor chips600may be formed on the top surface of the first wafer WF1. The integrated circuits of the third semiconductor chips600may be logic circuits.

Second circuit layers620of the third semiconductor chips600may be formed on the top surface of the first wafer WF1. For example, processes of forming and patterning an insulating layer and processes of forming and patterning a conductive layer may be repeated to form the second circuit layer620including a second insulating pattern622and a second circuit pattern624. The second circuit pattern624may be electrically connected to the integrated circuit of the third semiconductor chip600.

A singulation process may be performed on the resultant structure ofFIG.23. For example, the third scribe region SR3of the first wafer WF1may be sawed. Thus, a plurality of the third semiconductor chips600may be separated from each other.

Referring toFIG.24, a second wafer WF2may be provided. The second wafer WF2may be a semiconductor wafer. The second wafer WF2may include fourth device regions DR4spaced apart from each other in one direction, and a fourth scribe region SR4defining the fourth device regions DR4.

Second semiconductor chips500may be formed on the fourth device regions DR4of the second wafer WF2, respectively. Integrated circuits of the second semiconductor chips500may be formed on the top surface of the second wafer WF2. The integrated circuit of the second semiconductor chip500may be a memory circuit.

First vias530may be formed in the second wafer WF2. For example, holes may be formed in the second wafer WF2, and then, the first vias530may be formed by filling the holes with a conductive material. The first vias530may not completely penetrate the second wafer WF2in a vertical direction. In other words, bottom surfaces of the first vias530may not reach a bottom surface of the second wafer WF2. InFIG.24, the second wafer WF2is shown in a flipped position such that the bottom surface thereof appears at a top position of the drawing.

First circuit layers520of the second semiconductor chips500may be formed on the top surface of the second wafer WF2. For example, processes of forming and patterning an insulating layer and processes of forming and patterning a conductive layer may be repeated to form the first circuit layer520including a first insulating pattern522and a first circuit pattern524. The first circuit pattern524may be electrically connected to the integrated circuit of the second semiconductor chip500.

A second carrier substrate920may be provided. The second carrier substrate920may have an adhesive member provided on a top surface of the second carrier substrate920.

The second wafer WF2may be adhered onto the second carrier substrate920. For example, a surface of the first circuit layer520may be adhered to the adhesive member of the second carrier substrate920.

Referring toFIG.25, a grinding or polishing process may be performed on a back (i.e., bottom) surface of the second wafer WF2to expose the first vias530. A redistribution substrate400may be formed on the second wafer WF2. For example, an insulating pattern410may be formed on the second wafer WF2. A conductive pattern420may be formed in the insulating pattern410. One redistribution layer may be formed as described above. The process of forming the redistribution layer may be repeatedly performed to form the redistribution substrate400. Second connection terminals430may be formed on the redistribution substrate400.

Thereafter, the second carrier substrate920may be removed. For example, the second carrier substrate920may be detached by melting the adhesive member, or the second carrier substrate920may be physically removed.

Referring toFIG.26, a third carrier substrate940may be provided. An adhesive member945may be provided on a top surface of the third carrier substrate940. The second wafer WF2may be adhered onto the third carrier substrate940. For example, a surface of the redistribution substrate400may be adhered to the adhesive member945of the third carrier substrate940. At this time, the second connection terminals430may be inserted into the adhesive member945.

The third semiconductor chips600may be bonded onto the second wafer WF2. The third semiconductor chips600may be aligned on the second semiconductor chips500of the second wafer WF2, respectively. The second circuit layers620of the third semiconductor chips600may face the first circuit layers520of the second semiconductor chips500. The third semiconductor chips600may be in contact with the second semiconductor chips500. An exposed portion of the second circuit pattern624of the second circuit layer620may be bonded to an exposed portion of the first circuit pattern524of the first circuit layer520. The first circuit pattern524and the second circuit pattern624may be bonded to each other by the hybrid-bonding process performed by the surface activation at the interface of the first and second circuit patterns524and624being in contact with each other. The first circuit pattern524and the second circuit pattern624may be bonded to each other, and thus the interface between the first circuit pattern524and the second circuit pattern624may disappear.

A fifth molding layer730may be formed on the second wafer WF2. For example, a molding material may be applied onto the top surface of the second wafer WF2to cover the third semiconductor chips600, and the molding material may be hardened to form the fifth molding layer730. The fifth molding layer730may at least partially cover the top surface of the second wafer WF2, side surfaces of the third semiconductor chips600, and back surfaces of the third semiconductor chips600. The molding material may include an insulating material.

A portion of the fifth molding layer730and portions of the third semiconductor chips600may be removed. In other words, the third semiconductor chips600may be thinned. For example, a grinding process or a chemical mechanical polishing (CMP) process may be performed on a top surface of the fifth molding layer730. Thus, the back (i.e., top) surfaces of the third semiconductor chips600and the top surface of the fifth molding layer730may be planarized.

Referring toFIG.27, a singulation process may be performed on the resultant structure ofFIG.26. For example, a sawing process may be performed along the fourth scribe region SR4(seeFIG.26) of the second wafer WF2. The redistribution substrate400and the fifth molding layer730on the fourth scribe region SR4and the second wafer WF2may be sequentially sawed. Thus, a plurality of second chip stacks CS2may be separated from each other.

Thereafter, the third carrier substrate940may be removed. For example, the third carrier substrate940may be detached by melting the adhesive member945, or the third carrier substrate940may be physically removed.

Referring again toFIG.6, the first chip stack CS1and the second chip stack CS2may be mounted on the interposer substrate200. The first chip stack CS1and the second chip stack CS2may be mounted on the interposer substrate200by a flip chip method. An insulating material may be applied onto the interposer substrate200to form the third molding layer800. The third molding layer800may cover the first chip stack CS1and the second chip stack CS2. The interposer substrate200may be mounted on a package substrate100. The interposer substrate200may be mounted on the package substrate100by a flip chip method. External terminals102may be provided on a bottom surface of the package substrate100.

The semiconductor package ofFIG.6may be manufactured by the processes described above.

In the semiconductor package according to the example embodiments of the disclosure, the first and second circuit patterns may constitute one (i.e., a single) body, and thus the second and third semiconductor chips may be firmly bonded to each other. As a result, electrical characteristics and structural stability of the semiconductor package may be improved.

In addition, since the second and third semiconductor chips are bonded directly to each other, the semiconductor package may not require an additional connection terminal between the second and third semiconductor chips and a protective material for protecting the additional connection terminal. Thus, a height of the second chip stack may be reduced to provide a small semiconductor package. Moreover, heat generated from the second and third semiconductor chips may be easily released or dissipated by way of the third semiconductor chip. Furthermore, the second molding layer may expose the side surface of the third semiconductor chip. Thus, heat generated from the third semiconductor chip which may generate a lot of heat may be easily released or dissipated.

While example embodiments have been described, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure. Therefore, it should be understood that the above example embodiments are not limiting, but illustrative. Thus, the scope of the disclosure is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing description.