Patent ID: 12224313

DETAILED DESCRIPTION

According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the first conductivity type, a gate electrode, and a second electrode. The first semiconductor region is provided on the first electrode, and electrically connected to the first electrode. The second semiconductor region is provided on a part of the first semiconductor region. The third semiconductor region is provided on another part of the first semiconductor region. The third semiconductor region includes a first region separated from the second semiconductor region in a second direction perpendicular to a first direction directed from the first electrode to the first semiconductor region, and a second region provided between the first region and the second semiconductor region. An impurity concentration of the first conductivity type in the second region is higher than an impurity concentration of the first conductivity type in the first region. The fourth semiconductor region is provided on the second semiconductor region. An impurity concentration of the second conductivity type in the fourth semiconductor region is higher than an impurity concentration of the second conductivity type in the second semiconductor region. The fifth semiconductor region is provided on a part of the fourth semiconductor region. The gate electrode faces the fourth semiconductor region with a gate insulating layer interposed between the gate electrode and the fourth semiconductor region. The second electrode is provided on the fourth semiconductor region and the fifth semiconductor region. The second electrode is electrically connected to the fourth semiconductor region and the fifth semiconductor region.

Various embodiments are described below with reference to the accompanying drawings.

The drawings are schematic and conceptual; and the relationships between the thickness and width of portions, the proportions of sizes among portions, etc., are not necessarily the same as the actual values. The dimensions and proportions may be illustrated differently among drawings, even for identical portions.

In the specification and drawings, components similar to those described previously or illustrated in an antecedent drawing are marked with like reference numerals, and a detailed description is omitted as appropriate.

In the following description and drawings, the notations of n+, n−and p+, p represent relative high and low concentration of impurities. That is, the notation with “+” shows that the impurity concentration is relatively higher than the concentration of the notation without any of “+” and “−”, and the notation with “−” shows that the impurity concentration is relatively lower than the concentration of the notation without any of them. These notations represent relative high and low concentration of net impurities after compensation of the impurities, when both of p-type impurity and n-type impurity are included in respective regions.

In the embodiments described later, the embodiments may be executed by inverting the p-type and the n-type in respective semiconductor regions.

First Embodiment

FIG.1is a cross-sectional view illustrating a semiconductor device according to the first embodiment.

A semiconductor device100according to the first embodiment is a MOSFET. As illustrated inFIG.1, the semiconductor device100includes an n+-type (first conductivity type) drain region1(first conductivity region), a p−-type (second conductivity type) pillar region2(second conductivity region), an n−-type pillar region3(third semiconductor region), a p-type base region4(fourth semiconductor region), an n+-type source region5(fifth semiconductor region), an n−-type buffer region6(intermediate region), a gate electrode10, a drain electrode21(first electrode), a source electrode22(second electrode), and an insulating part30.

An XYZ coordinate system is employed in the description of the embodiment. A direction directed from the drain electrode21to the n+-type drain region1is Z-direction (first direction). A direction that is perpendicular to Z-direction is X-direction (second direction). A direction that is perpendicular to Z-direction and intersects X-direction is Y-direction (third direction). Further, for description, a direction directed from the drain electrode21to the n+-type drain region1is referred to as “upper” and an opposite direction thereof is referred to as “lower”. These directions are based on the relative positional relationship between the drain electrode21and the n+-type drain region1, and thus have no relationship with the direction of gravity.

The drain electrode21is provided on the lower surface of the semiconductor device100. The n+-type drain region1is provided on the drain electrode21and is electrically connected to the drain electrode21. The p−-type pillar region2is provided on a part of the n+-type drain region1. The n−-type pillar region3is provided on another part of the n+-type drain region1. The n−-type pillar region3is arranged in X-direction with the p−-type pillar region2. The n-type impurity concentration in the n−-type pillar region3is lower than the n-type impurity concentration in the n−-type drain region1.

The n−-type pillar region3includes a first region3aand a second region3b. The first region3ais separated from the p−-type pillar region2in X-direction. The second region3bis provided between the p−-type pillar region2and the first region3a. The n-type impurity concentration in the second region3bis higher than the n-type impurity concentration in the first region3a.

The p-type base region4is provided on at least a part of the p−-type pillar region2and the second region3b. The p-type impurity concentration in the p-type base region4is higher than the p-type impurity concentration in the p−-type pillar region2. The n+-type source region5is provided in an upper part of the p-type base region4. The gate electrode10faces the p-type base region4with the gate insulating layer11interposed therebetween. In the semiconductor device100, the gate electrode10is provided on the n−-type pillar region3, the p-type base region4, and the n+-type source region5with the gate insulating layer11interposed therebetween.

The source electrode22is provided on the p-type base region4, the n+-type source region5, and the gate electrode10, and is electrically connected to the p-type base region4and the n+-type source region5. The insulating layer12is provided between the gate electrode10and the source electrode22. The source electrode22is electrically separated from the gate electrode10by the insulating layer12.

The n−-type buffer region6is provided between the n+-type drain region1and the p−-type pillar region2, and between the n−-type drain region1and the n−-type pillar region3. The n-type impurity concentration in the n−-type buffer region6is lower than the n-type impurity concentration in the n+-type drain region1. The n−-type buffer region6includes a first portion6aand a second portion6b. The first portion6ais provided between the n+-type drain region1and the p−-type pillar region2, and between the n−-type drain region1and the second region3b. The second portion6bis provided between the n+-type drain region1and the first region3a.

The insulating part30is provided on the n+-type drain region1. The p−-type pillar region2is provided around the insulating part30in X-direction and under the insulating part30. For example, an upper portion of the insulating part30is arranged in X-direction with the p-type base region4and in contact with the source electrode22. As illustrated inFIG.1, the insulating part30may include a gap31.

FIG.2is a plan view illustrating a semiconductor device according to the first embodiment.

FIG.3is a cross-sectional view illustrating a semiconductor device according to the first embodiment.

FIG.1is a cross-sectional view taken along the line I-I inFIGS.2and3.FIG.3is a cross-sectional view taken along the line III-III inFIG.1. InFIG.2, the insulating layer12and the source electrode22are omitted.

For example, as illustrated inFIGS.1to3, a plurality of p−-type pillar regions2, n−-type pillar regions3, p-type base regions4, n+-type source regions5, gate electrodes10, and insulating parts30are provided in X-direction. A plurality of p−-type pillar regions2and a plurality of n−-type pillar regions3are alternately provided in X-direction. One n−-type pillar region3includes one first region3aand two second regions3b. The two second regions3bare respectively provided between the first region3aand two p−-type pillar regions2which are adjacent to each other in X direction. The first region3aincludes an intermediate portion between the p−-type pillar regions2which are adjacent to each other in X-direction.

Two p-type base regions4are provided on one p−-type pillar region2. The upper portion of the insulating part30is provided between two p-type base regions4in X-direction. The n+-type source region5is provided on each p-type base region4. Two p-type base regions4and two n+-type source regions5are provided between two insulating parts30which are adjacent to each other in X direction X. The gate electrode10is provided on the n−-type pillar region3, two p-type base regions4, and two n−-type source regions5with the gate insulating layer11interposed therebetween. The p−-type pillar regions2, the n−-type pillar regions3, the p-type base regions4, the n+-type source regions5, the gate electrodes10, and the insulating parts30extend along Y-direction. In examples illustrated inFIGS.1to3, Y direction is perpendicular to X direction.

Operations of the semiconductor device100will be described.

A voltage higher than a threshold is applied to the gate electrode10in a state in which a voltage positive with respect to the source electrode22is applied to the drain electrode21. A channel (inversion layer) is formed in the p-type base region4. This brings the semiconductor device100into an on-state. In an on-state, electrons flow into the drain electrode21via the channel and the n−-type pillar region3. Thereafter, when the voltage applied to the gate electrode10becomes lower than the threshold, the channel in the p-type base region4disappears, so that the semiconductor device100is brought into an off-state. When the semiconductor device100is in an off-state, a depletion layer extends from the p-n junction surface between the n−-type pillar region3and the p-type base region4along Z direction, and a depletion layer extends from the p-n junction surface between the n−-type pillar region3and the p−-type pillar region2along X direction.

An example of the material of each constituent element of the semiconductor device100will be described.

The n+-type drain region1, the p−-type pillar region2, the n−-type pillar region3, the p-type base region4, the n+-type source region5, and the n−-type buffer region6contain, as a semiconductor material, silicon, silicon carbide, gallium nitride, or gallium arsenide. In a case where silicon is used as a semiconductor material, arsenic, phosphorus, or antimony can be used as the n-type impurity. Boron can be used as the p-type impurity. The gate electrode10contains a conductive material such as polysilicon. The gate insulating layer11and the insulating part30contain an insulating material such as silicon oxide. The drain electrode21and the source electrode22contain a metal such as titanium, tungsten, or aluminum.

FIGS.4A to6Bare cross-sectional views illustrating a manufacturing process of a semiconductor device according to the first embodiment.

First, a semiconductor substrate80including an n+-type semiconductor layer81(first semiconductor layer) and an n−-type semiconductor layer82(second semiconductor layer) is prepared. The n−-type semiconductor layer82is provided on the n+-type semiconductor layer81. An insulating layer91is formed on the n−-type semiconductor layer82by chemical vapor deposition (CVD). The insulating layer91is patterned by photolithography and reactive ion etching (RIE). An opening OP1is formed in the upper surface of the n−-type semiconductor layer82by RIE using the insulating layer91as a mask. As illustrated inFIG.4A, a plurality of openings OP1are formed in X-direction. Each opening OP1extends along Y-direction.

In the structural body illustrated inFIG.4A, an inner surface S of the opening OP1is doped with an n-type impurity by an isotropic doping method. The inner surface S is a part of the surface of the n−-type semiconductor layer82. As the isotropic doping method, plasma doping or solid phase diffusion is employed. The semiconductor substrate80is heat-treated to activate the n-type impurity. Thereby, the n−-type diffusion region83(first diffusion region) is formed in the n−-type semiconductor layer82as illustrated inFIG.4B. An insulating layer92may be formed along the inner surface of the opening OP1by thermal oxidation before the heat treatment of the semiconductor substrate80. The insulating layer92can suppress vaporization of the semiconductor material of the n−-type semiconductor layer82during heat treatment for activation.

The n-type impurity is diffused from the inner surface S of the opening OP1to X-direction and Y-direction during the heat treatment for activation. A concentration gradient is formed in the n−-type diffusion region83. As a result, the n−-type diffusion region83includes a first region83a, a second region83b, and a third region83c. The first region83ais separated from the inner surface S in X-direction. The second region83bis positioned between the inner surface S and the first region83a. The third region83cis positioned between the n+-type semiconductor layer81and the inner surface S, and between the n+-type semiconductor layer81and the second region83bin Z-direction. The n-type impurity concentration in each of the second region83band the third region83cis higher than the n-type impurity concentration in the first region83a.

Also, the n−-type semiconductor layer82remains under the lower portion of the first region83a, for example. The n-type impurity concentration in the n−-type semiconductor layer82is lower than the n-type impurity concentration in the first region83a. Alternatively, the n-type impurity may be diffused in the entire n−-type semiconductor layer82during the heat treatment for activation. In this case, a fourth region having a concentration of a first conductivity type impurity lower than that of the first region83ais formed under the first region83a. In any case, after formation of the n−-type diffusion region83, a region of a first conductivity type having a concentration of the first conductivity type impurity lower than that of the first region83aexists under the first region83a.

The insulating layer92is removed. The inner surface S is doped with a p-type impurity by plasma doping or solid phase diffusion. The semiconductor substrate80is heat-treated to activate the p-type impurity. As illustrated inFIG.5A, a p−-type diffusion region84(second diffusion region) along the inner surface S is formed so as to be stacked on a part of the n−-type diffusion region83.

An insulating layer93filling the opening OP1is formed by CVD. A part of the insulating layer93and the insulating layer91are removed such that the upper surface of the n−-type diffusion region83is exposed. A gap93amay exist in the remaining insulating layer93. An insulating layer94is formed on the upper surface of the n−-type diffusion region83and the upper surface of the p-type diffusion region85by thermal oxidation. As illustrated inFIG.5B, a p-type impurity is ion-implanted on an upper portion of the p−-type diffusion region84to form the p-type diffusion region85.

A conductive layer is formed on the insulating layer94and this conductive layer is patterned by photolithography and RIE. As a result, the gate electrode10is formed. An insulating layer95covering the insulating layer94and the gate electrode10is formed. A part of the insulating layer94and a part of the insulating layer95are removed by photolithography and RIE to form an opening OP2between the gate electrodes10. The remaining insulating layer94and the remaining insulating layer95respectively correspond to the gate insulating layer11and the insulating layer12. A part of the p-type base region4and the insulating layer93are exposed through the opening OP2. An n-type impurity is selectively ion-implanted on an upper portion of the p-type diffusion region85through the opening OP2. Thereby, an n+-type diffusion region86is formed as illustrated inFIG.6A.

A source electrode22filling the opening OP2is formed on the insulating layer95. The back surface of the n+-type semiconductor layer81is abraded until the thickness of the n−-type semiconductor layer81reaches a predetermined thickness. As illustrated inFIG.6B, the drain electrode21is formed on the back surface of the n+-type semiconductor layer81. Thus, the semiconductor device100according to the first embodiment is manufactured.

In the semiconductor device illustrated inFIG.6B, the n−-type semiconductor layer81corresponds to the n+-type drain region1in the semiconductor device100. A part of the n−-type diffusion region83between the p−-type diffusion regions84which are adjacent to each other in X-direction corresponds to the n−-type pillar region3. The first region83aof the n−-type diffusion region83corresponds to the first region3aof the n−-type pillar region3. The second region83bof the n−-type diffusion region83corresponds to the second region3bof the n−-type pillar region3. A region of a first conductivity type between the n+-type semiconductor layer81and the p−-type diffusion region84, between the n+-type semiconductor layer81and the first region83a, and between the n+-type semiconductor layer81and the second region83bcorresponds to the n−-type buffer region6. The third region83cof the n−-type diffusion region83corresponds to the first portion6aof the n−-type buffer region6. The n−-type semiconductor layer82corresponds to the second portion6bof the n−-type buffer region6. The p−-type diffusion region84corresponds to the p−-type pillar region2. The p-type diffusion region85corresponds to the p-type base region4. The n+-type diffusion region86corresponds to the n+-type source region5.

The effects of the first embodiment will be described.

To improve the breakdown voltage of the semiconductor device100, the difference between the amount of the p-type impurity contained in the p−-type pillar region2and the amount of the n-type impurity contained in the n−-type pillar region3is preferably small. A small difference between amounts of the impurities allows the p−-type pillar region2and the n−-type pillar region3to be completely depleted when the semiconductor device100is in an off-state.

In addition to the breakdown voltage, reduction in the on-resistance is desired for the semiconductor device100. The n-type impurity concentration in the n−-type pillar region3is preferably high in order to reduce the on-resistance of the semiconductor device100. However, as the n-type impurity concentration in the n−-type pillar region3becomes high, the n−-type pillar region3becomes difficult to be depleted. For this reason, the width of the n−-type pillar region3(length in X-direction) needs to be reduced as the n-type impurity concentration in the n−-type pillar region3becomes high. By setting the n-type impurity concentration in the n−-type pillar region3to be high and reducing the width of the n−-type pillar region3, the on-resistance of the semiconductor device100can be reduced while the breakdown voltage of the semiconductor device100is maintained.

Meanwhile, with a high n-type impurity concentration in the n−-type pillar region3, when the width of the n−-type pillar region3varies, variation in the amount of the n-type impurity contained in the n−-type pillar region3becomes large. As a result, variation in the breakdown voltage of the semiconductor device100becomes large, thus reducing the reliability of the semiconductor device100.

For this problem, in the semiconductor device100according to the first embodiment, the n−-type pillar region3includes the first region3aand the second region3b. For example, the width of the n−-type semiconductor layer82between the openings OP1which are adjacent to each other in X-direction, illustrated inFIG.4Aaffects the width of the n−-type pillar region3. As illustrated inFIG.4B, the first region3aand the second region3bare formed by doping the inner surface S of the opening OP1with an n-type impurity. The second region3bis formed along the inner surface S, and the width of the second region3bis substantially constant regardless of variation in the width of the n−-type pillar region3. For this reason, when the width of the n−-type pillar region3varies, the width of the first region3avaries according to the variation.

The n-type impurity concentration in the first region3ais lower than the n-type impurity concentration in the second region3b. Thus, even when the width of the first region3avaries, variation in the amount of the n-type impurity contained in the n−-type pillar region3is smaller than a case where the width of the second region3bvaries. According to the first embodiment, variation in the amount of the n-type impurity in the n−-type pillar region3caused by variation in the width of the n−-type pillar region3can be reduced. As a result, variation in the breakdown voltage of the semiconductor device100can be reduced, thus improving the reliability of the semiconductor device100.

A preferred example of the first embodiment will be described.

FIG.7Ais a cross-sectional view illustrating a part of a semiconductor device according to the first embodiment.

FIG.7Bis a graph showing the impurity concentration in the A1-A2line inFIG.7A.

InFIG.7B, the horizontal axis represents the position P in X-direction. The vertical axis represents the impurity concentration C. The solid line represents the n-type impurity concentration. The dashed line represents the p-type impurity concentration.

As illustrated inFIG.7A, the length L1of the n−-type pillar region3in X-direction is longer than the length L2of the p−-type pillar region2in X-direction. As illustrated inFIG.7B, the p-type impurity concentration in the p−-type pillar region2is higher than the n-type impurity concentration in the n−-type pillar region3. When the semiconductor device100is in an on-state, electrons flow into the drain electrode21via the n−-type pillar region3. The length L1being longer than the length L2allows the width of the path of electrons to be increased when the semiconductor device100is in an on-state. Thereby, the on-resistance of the semiconductor device100can be further reduced.

As the n-type impurity concentration in the first region3ais low, variation in the amount of the n-type impurity of the n−-type pillar region3caused by variation in the width of the n−-type pillar region3is small. Therefore, the n-type impurity concentration C1in the first region3ais preferably less than 0.5 times the n-type impurity concentration C2in the second region3b.

The p−-type pillar region2is formed by doping the p-type impurity along the inner surface S of the opening OP1as illustrated inFIG.5A. The insulating part30is provided inside the p−-type pillar region2. As a result, variation in the amount of the p-type impurity contained in the p−-type pillar region2can be reduced regardless of variation in the width of the opening OP1compared to a case of filling the opening OP1with a p-type semiconductor layer.

The p−-type pillar region2may be provided around a semiconductor part not substantially containing impurities instead of the insulating part30. Note that, for reducing leak current in the semiconductor device100, it is preferable to provide the p−-type pillar region2around the insulating part30.

Preferably, the insulating part30includes the gap31. In a case where the insulating part30is provided, a stress is applied from the insulating part30to the p−-type pillar region2and the n−-type pillar region3. Such a stress may cause cracks in the p−-type pillar region2or the n−-type pillar region3. In a case where the insulating part30includes the gap31, deformation of the gap31causes uneven distribution of the stress applied from the insulating part30to the p−-type pillar region2and the n−-type pillar region3. This enables to reduce a possibility that cracks are generated in the p−-type pillar region2or the n−-type pillar region3.

The semiconductor device100preferably includes the n−-type buffer region6. By providing the n−-type buffer region6, a depletion layer extends between the n+-type drain region1and the p−-type pillar region2, and between the n+-type drain region1and the n−-type pillar region3, so that the breakdown voltage of the semiconductor device100can be improved.

Further, as illustrated inFIG.1, the n−-type buffer region6includes the first portion6aand the second portion6b. The second portion6bis positioned between the n+-type drain region1and the first region3ain Z-direction. In other words, the second portion6bis separated from the p−-type pillar region2in X-direction and Z-direction. For this reason, when the semiconductor device100is in an off-state, the second portion6bis difficult to deplete compared to the first portion6apositioned under the p−-type pillar region2. For this problem, the n-type impurity concentration in the second portion6bis preferably lower than the n-type impurity concentration in the first portion6a. In this case, the second portion6bis easily depleted compared to a case where the n-type impurity concentrations in the first portion6aand the second portion6bare the same. As a result, the breakdown voltage of the semiconductor device100can be improved.

First Modification

FIG.8is a cross-sectional view illustrating a semiconductor device according to the first modification of the first embodiment.

A semiconductor device110illustrated inFIG.8is different from the semiconductor device100in that the semiconductor device110does not include the n−-type buffer region6. In the semiconductor device110, as in the semiconductor device100, the n−-type pillar region3includes the first region3aand the second region3b. Even in a case where the n−-type buffer region6is not provided, variation in the amount of the n-type impurity of the n−-type pillar region3caused by variation in the width of the n−-type pillar region3can be reduced compared to a case where the n-type impurity concentration in the n−-type pillar region3is uniform, by providing the first region3aand the second region3b.

Second Modification

FIG.9is a cross-sectional view illustrating a semiconductor device according to the second modification of the first embodiment.

In a semiconductor device120illustrated inFIG.9, variation in the n-type impurity concentration of the n−-type pillar region3in X-direction is smaller than that of the semiconductor device100. In the semiconductor device120, the n-type impurity concentration in the n−-type pillar region3may be uniform. In the semiconductor device120, as in the semiconductor device100, the n−-type buffer region6includes the first portion6aand the second portion6b. Even in a case where variation in the n-type impurity concentration of the n−-type pillar region3in X-direction is small, the breakdown voltage of the semiconductor device120can be improved compared to a case where the n-type impurity concentration in the n−-type buffer region6is uniform, by providing the first portion6aand the second portion6b.

Third Modification

FIG.10is a cross-sectional view illustrating a semiconductor device according to the third modification of the first embodiment.

As a semiconductor device130illustrated inFIG.10, the gate electrode10may face the p-type base region4in X-direction with the gate insulating layer11interposed therebetween. The gate electrode10is positioned on the first region3a. In the semiconductor device130, as in the semiconductor device100, the n−-type pillar region3includes the first region3aand the second region3b. Thereby, variation in the breakdown voltage of the semiconductor device130can be reduced, thus improving the reliability of the semiconductor device130. Further, the n−-type buffer region6includes the first portion6aand the second portion6b. Thereby, the breakdown voltage of the semiconductor device130can be improved.

Second Embodiment

FIGS.11and13are cross-sectional views illustrating a semiconductor device according to the second embodiment.

FIG.12is a plan view illustrating a semiconductor device according to the second embodiment.

FIG.11is a cross-sectional view taken along the line XI-XI inFIGS.12and13.FIG.13is a cross-sectional view taken along the line XIII-XIII inFIG.11. InFIG.12, the insulating layer12and the source electrode22are omitted.

In a semiconductor device200according to the second embodiment, a plurality of p−-type pillar regions2are provided in X-direction and Y-direction as illustrated inFIG.13. For example, Y-direction is not perpendicular to X-direction, and inclined with respect to X-direction.

As illustrated inFIGS.11and13, the n−-type pillar region3is provided around a plurality of p−-type pillar regions2in X-Y plane. The n−-type pillar region3includes the first region3aand a plurality of the second regions3b. The plurality of second regions3bare respectively provided between the plurality of p−-type pillar regions2and the first region3a. The plurality of second regions3bare respectively provided around the plurality of p−-type pillar regions2in X-Y plane.

As illustrated inFIGS.11and12, the p-type base region4is provided on each p−-type pillar region2. One p-type base region4is provided around the upper portion of the insulating part in the X-Y plane. The n+-type source region5is provided on each p-type base region4. The gate electrode10is provided on the n−-type pillar region3and the plurality of p-type base regions4with the gate insulating layer11interposed therebetween such that the plurality of p-type base regions4and the plurality of n−-type source regions5are exposed to the source electrode22.

According to the second embodiment, the area of the n−-type pillar region3in X-Y plane can be increased compared to the first embodiment. The width of the path of electrons can be increased when the semiconductor device200is in an on-state. Thereby, the on-resistance of the semiconductor device200can be reduced.

Further, in the semiconductor device200, as in the semiconductor device100, the n−-type pillar region3includes the first region3aand the second region3b. Thereby, variation in the breakdown voltage of the semiconductor device200can be reduced, thus improving the reliability of the semiconductor device200. Further, the n−-type buffer region6includes the first portion6aand the second portion6b. Thereby, the breakdown voltage of the semiconductor device200can be improved.

The configuration of the n−-type pillar region3is particularly suitable for the semiconductor device200according to the second embodiment. In a case where a plurality of p−-type pillar regions2are provided in two directions, a portion which is far from any of the p−-type pillar regions2and which is difficult to deplete is generated in the n−-type pillar region3. In a case where the n−-type pillar region3includes the first region3a, the portion which is difficult to deplete is positioned in the first region3a. Therefore, the portion is easily depleted compared to a case where the n-type impurity concentration in the n−-type pillar region3is uniform.

More specifically, description will be given with reference toFIG.14.

FIG.14is a cross-sectional view enlarging a portion ofFIG.13.

For example, a plurality of p−-type pillar regions2include a first p−-type pillar region2a, a second p−-type pillar region2b, and a third p−-type pillar region2c. The second p−-type pillar region2bis adjacent to the first p−-type pillar region2ain X-direction. The third p−-type pillar region2cis adjacent to the first p−-type pillar region2ain Y-direction.

An imaginary circle IC passing through the center Cel of the first p−-type pillar region2ain X-direction and Y-direction, the center Cel of the second p−-type pillar region2bin X-direction and Y-direction, and the center Ce3of the third p−-type pillar region2cin X-direction and Y-direction is assumed. At this time, the center Ce of the imaginary circle IC is positioned separated from any of the first p−-type pillar region2a, the second p−-type pillar region2b, and the third p−-type pillar region2c. A depletion layer extending from each p−-type pillar region2is less likely to reach the n−-type pillar region3around the center Ce.

As a method for depleting a portion around the center Ce, there is a method of reducing the interval between the p−-type pillar regions2. In this case, the area of the n−-type pillar region3in X-Y plane is small. As a result, the on-resistance of the semiconductor device200increases. As another method, there is a method of reducing the n-type impurity concentration in the n−-type pillar region3. Also in this case, the electrical resistance in the n−-type pillar region3increases, as a result of which the on-resistance of the semiconductor device200increases.

By reducing the n-type impurity concentration of the first region3aincluding a portion around the center Ce relative to the second region3b, the portion around the center Ce is easily depleted. Thus, according to the second embodiment, the breakdown voltage of the semiconductor device200can be improved while increase in the on-resistance of the semiconductor device200is suppressed.

Examples in which Y-direction is inclined with respect to X-direction have been described herein, but Y-direction may be perpendicular to X-direction. Further, in the examples illustrated, the shape of the p−-type pillar region2viewed from Z-direction is a circular shape. The shape of the p−-type pillar region2viewed from Z-direction may be a polygonal shape (for example, a regularly hexagonal shape).

While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the invention. The above embodiments can be practiced in combination with each other.