Patent ID: 12254805

DETAILED DESCRIPTION OF ILLUSTRATED EMBODIMENTS

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of the present disclosure. In addition, it should be understood that the specific embodiments described here are only used to illustrate and explain the present disclosure, and are not intended to limit the present disclosure. In the present disclosure, unless otherwise stated, directional terms, such as “upper” and “lower”, usually refer to upper and lower positions of a device in actual use or working conditions, and specifically refer to drawing directions in the drawings, while “inner” and “outer” refer to the outline of the device.

Referring toFIG.1, a pixel driving circuit of the present disclosure includes a light-emitting module1, an external detection module3, and an internal compensation module4. The light-emitting module1is electrically connected to the external detection module3and the internal compensation module4. The light-emitting module1includes a second transistor and a light-emitting unit. A first electrode of the second transistor is electrically connected to a high-electric potential power supply signal. A second electrode of the second transistor is electrically connected to the light-emitting unit. The external detection module is configured to acquire a threshold voltage of the second transistor when the display panel is turned on, and determine a shift direction of the threshold voltage. The internal compensation module is configured to use a first timing sequence to compensate the threshold voltage when the shift direction of the threshold voltage is a positive shift. The internal compensation module is configured to use a second timing sequence to compensate the threshold voltage when the shift direction of the threshold voltage is a negative shift.

It is understandable that by detecting the shift direction of the threshold voltage at startup through the external detection module3, the shift direction of the threshold voltage during a period from startup to shutdown can be determined. That is, depending on whether the shift direction of the threshold voltage at startup is the positive shift or the negative shift, one of the first timing sequence and the second timing sequence is selected to compensate the threshold voltage, thereby achieving internal real-time compensation, which is more accurate and has a larger compensation range.

In this embodiment, the pixel driving circuit including the external detection module and the internal compensation module is provided. The external detection module detects the shift direction of the threshold voltage at startup. When the shift direction of the threshold voltage is the positive shift, the internal compensation module is configured to use the first timing sequence to compensate the threshold voltage. When the shift direction of the threshold voltage is the negative shift, the internal compensation module is configured to use the second timing sequence to compensate the threshold voltage. Through internal compensation at different timings, internal real-time compensation that is more accurate and has a larger compensation range is achieved, which solves the technical problem of the existing pixel driving circuit being unable to take into account both real-time compensation and a larger compensation range.

The technical solutions of the present disclosure will now be described with reference to specific embodiments.

It should be noted that first electrodes and second electrodes of a first transistor to a ninth transistor in the present disclosure are only for illustration. The present disclosure is explained by taking the following explanation as an example. A side of a certain transistor with a gate is a “downward direction”, an electrode of the transistor located in a “left direction” of the gate is the first electrode, and an electrode of the transistor located in a “right direction” of the gate is the second electrode.

It should be noted that inFIG.1of the present disclosure, Scan1is a first scan signal, Scan2is a second scan signal, Scan3is a third scan signal, Scan4is a fourth scan signal, and Scan5is a fifth scan signal, Data1is a first data signal, Data2is a second data signal, EM1is a first light-emitting signal, EM2is a second light-emitting signal, VSS is a low-electric potential power supply signal, VDD is a high-electric potential power supply signal, Vi is a reset signal, and ADC is a digital-to-analog conversion signal. Regarding connection relationships or positions of signal input terminals that are not described in the following content, a simple inference can be made with reference toFIG.1.

Alternatively, in a specific embodiment, when the first electrode is a source, the second electrode is a drain. Alternatively, when the first electrode is a drain, the second electrode is a source.

In some embodiments, when the threshold voltage is greater than or equal to 0, the pixel driving circuit uses the first timing sequence to compensate the threshold voltage. A compensation range of the threshold voltage is a first range. When the threshold voltage is less than 0, the pixel driving circuit uses the second timing sequence to compensate the threshold voltage. A compensation range of the threshold voltage is a second range. The first range is different from the second range.

It can be understood that when the shift direction of the threshold voltage is the positive shift, it means that the threshold voltage is greater than or equal to 0. The shift direction of the threshold voltage is the negative shift, which means that the threshold voltage is less than 0.

In some embodiments, the first range ranges from 0 to 4V, and the second range ranges from −3V to 2V.

It can be understood that, refer toFIG.1, an addition of the first range and the second range is the compensation range of the pixel driving circuit provided by the present disclosure. The compensation range of the pixel driving circuit to the shift of the threshold voltage ranges from −3V to 4V. Compared with a single internal compensation circuit in the prior art, the compensation range of the pixel driving circuit of the present disclosure is the addition of two timing compensation ranges. Therefore, a larger compensation range is achieved.

In some embodiments, refer toFIG.1, the pixel driving circuit is a 9T3C circuit. The pixel driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitor, a second capacitor, and a third capacitor.

In some embodiments, the light-emitting module1also includes the first transistor, the third transistor, and the first capacitor. A gate of the first transistor is input with a first light-emitting signal. A first electrode of the first transistor is input with a high-electric potential power supply signal. A second electrode of the first transistor is connected to the first electrode of the second transistor. The second electrode of the second transistor is connected to a second electrode of the third transistor. A first electrode of the third transistor is connected to an anode of the light-emitting unit. A gate of the third transistor is input with a second light-emitting signal. A cathode of the light-emitting unit is input with a low-electric potential power supply signal. One terminal of the first capacitor is connected to the first electrode of the first transistor, and another terminal of the first capacitor is connected to the second electrode of the second transistor.

The external detection module3includes a first switch, a second switch, a chip, and the fourth transistor. A gate of the fourth transistor is input with a first scan signal. A second electrode of the fourth transistor is electrically connected to the second electrode of the second transistor. A first electrode of the fourth transistor is connected to the chip through a first branch and a second branch arranged in parallel, the first branch includes the first switch, and the second branch includes the second switch.

The internal compensation module4includes the third capacitor, the fifth transistor, the seventh transistor, the eighth transistor, and the ninth transistor. One terminal of the third capacitor is connected to a gate of the second transistor, and another terminal of the third capacitor is connected to the second electrode of the second transistor. A gate of the fifth transistor is input with the first scan signal. A second electrode of the fifth transistor is electrically connected to a second electrode of the ninth transistor. A first electrode of the fifth transistor is connected to the second electrode of the first transistor. A first electrode of the ninth transistor is connected to the first electrode of the first transistor. A gate of the ninth transistor is input with a third scan signal. A second electrode of the seventh transistor is connected to the second electrode of the ninth transistor. A first electrode of the seventh transistor is electrically connected to the gate of the second transistor. A gate of the seventh transistor is input with a fourth scan signal. A gate of the eighth transistor is input with a fifth scan signal. A first electrode of the eighth transistor is input with a second data signal. A second electrode of the eighth transistor is connected to the gate of the second transistor.

In some embodiments, refer toFIG.1, the pixel driving circuit further includes a reset module2, the reset module2includes the sixth transistor and the second capacitor. A gate of the sixth transistor is input with a second scan signal. A second electrode of the sixth transistor is connected to the anode of the light-emitting unit and the second capacitor. A first electrode of the sixth transistor is input with a reset signal.

In some embodiments, refer toFIG.2, working stages of the external detection module3includes an initialization stage10, a storage stage20, and a detection stage30. In the initialization stage10, the external detection module3resets a potential of a G-point at the gate and a potential of an S-point at the second electrode of the second transistor. In the storage stage20, the external detection module charges the second electrode of the second transistor to turn off the second transistor. In the detection stage30, the external detection module reads the threshold voltage of the second transistor.

In the initialization stage10, the first scan signal and the fifth scan signal are at a high potential, the fourth transistor is turned on, the eighth transistor is turned on, the second data signal is at a low potential, the low potential VdataLof the second data signal is written to the G-point at the gate of the second transistor, a constant reference voltage Vrefis written to the S-point at the second electrode of the second transistor. At this time, the potential Vgof the G-point and the potential Vsof the S-point are initialized, where Vs=Vrefand Vg=VdataL.

In the storage stage20, the fifth scan signal is at the high potential, the eighth transistor is turned on, the second data signal is at the high potential. At this time, the high potential VdataHof the second data signal is written to the G-point, the second transistor is turned on, and the S-point starts to be charged. When Vs=VdataH−Vth, the second transistor is turned off, where the threshold voltage of the second transistor is Vth, and the potential of the S-point is charged to Vs=VdataH−Vth.

In the detection stage30, the first scan signal is at the high potential, the fourth transistor is turned on, the first switch is turned off, the first data signal is not input, and the second switch is turned on, so that the chip reads the potential of the S-point and acquires the threshold voltage Vthof the second transistor.

In some embodiments, refer toFIG.3, when the Vth>0, the internal compensation module4uses the first timing sequence to compensate the threshold voltage, and working stages of the first timing sequence includes a first reset stage40, a writing and compensation stage50, and a first light-emitting stage60.

In the first reset stage40, the third scan signal and the fourth scan signal are at the high potential, the seventh transistor and the ninth transistor are turned on, the high-electric potential power supply signal VDDis written to the G-point, the second scan signal is at the high potential, the sixth transistor is turned on, the reset signal Viis written to an A-point connecting the second capacitor and the first electrode of the sixth transistor. At this time, the potential of the G-point is Vg=VDD, and the potential Vaof the A-point is equal to the Vi.

In the writing and compensation stage50, the first light-emitting signal, the first scan signal, the second scan signal, the fourth scan signal, and the fifth scan signal are at the high potential, the first switch, the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are all turned on, the high potential VDataH′ of the first data signal is written to the S-point. At this time, the potential of the G-point is a sum of the potential of the S-point and the threshold voltage of the second transistor, i.e., Vg=VDataH′+Vth, and the potential of the A-point maintains at the Vi.

In the first light-emitting stage60, the first light-emitting signal, the second light-emitting signal, the second data signal, and the fifth scan signal are at the high potential, the first transistor, the second transistor, and the third transistor are turned on, the potential Vaof the A-point is equal to a sum of a voltage VF,LEDof the light-emitting unit, the low-electric potential power supply signal VSS, and a voltage VIR(VSS)of a wiring connecting the A-point and the light-emitting unit, that is, Va=VF,LED+VSS+VIR(VSS). The fourth scan signal is at the high potential, the seventh transistor is turned on, the potential of the G-point is increased by the potential of the A-point through the second capacitor. At this time, the potential of the G-point is Vg=VDataH′+Vth−Vinit+VF,LED+VSS+VIR(VSS), and the potential Vsof the S-Point is equal to a sum of the voltage VF,LEDof the light-emitting unit, a divided voltage VT3of the third transistor, the voltage VSSof the low-electric potential power supply signal, and a voltage VIR(VSS)′ of a wiring connecting the S-point and the light-emitting unit, that is Vs=VF,LED+VT3+VSS+VIR(VSS)′.

It can be understood that in the first reset stage40, VDDis written to the gate of the second transistor. In writing and compensation stage50, after VdataHis written to the A-point, Vthis detected. Therefore, a maximum value of Vththat can be detected before and after drift is VDD−VdataH. Vthneeds to be ensured to be greater than 0 so that Vthcan be correctly stored into the gate. That is, the compensation range of the threshold voltage of the first timing sequence is: 0<Vth<VDD−VdataH−Vth.

In some embodiments, refer toFIG.4, when Vth<0, the internal compensation module4uses the second timing sequence to compensate the threshold voltage, working stages of the second timing sequence includes a second reset stage70, an acquisition and storage stage80, a data writing stage90, and a second light-emitting stage100.

In the second reset stage70, the first scan signal and the fifth scan signal are at the high potential, the first switch is turned on, the fourth transistor is turned on, a Vnegsignal carried by the first data signal is written into the potential of the S-point, the eighth transistor is turned on, a Vpresignal carried by the second data signal is written into the potential of the G-point to initialize the potentials of the G-point and the S-point, where Vg=Vpreand Vs−Vneg.

In the acquisition and storage stage80, the first scan signal, the fourth scan signal, the fifth scan signal, and the second data signal are at the high potential, the second transistor, the fifth transistor, and the seventh transistor are turned on. After the potential of the S-point is charged to Vs=Vpre−Vth, the second transistor is turned off, the S-point stops being charged, and the potential of the S-point maintains at Vs=Vpre−Vth.

In the data writing stage90, the second data signal carries the high potential Vdata2, the fifth scan signal is at the high potential, the eighth transistor is turned on, the potential of the G-point is Vdata2, the second transistor is turned on, a coupling of the G-point through the third capacitor increases the potential of the S-point. At this time, the potential of the S-point is Vs=(Vpre−Vth)+(Vdata2−Vpre)*C3/(C1+C3), a potential difference between the G-point and the S-point is Vgs=(Vdata2−Vpre)*C1/(C1+C3)+Vth, where C1is a capacitance value of the first capacitor and C3is a capacitance value of the third capacitor.

In the second light-emitting stage100, the potentials of the G-point and the S-point are maintained, the first light-emitting signal, the second light-emitting signal, the second data signal, and the fifth scan signal are at the high potential, and the first transistor, the second transistor, and the third transistor are turned on to cause the light-emitting unit to emit light.

In some embodiments, a purpose of the second light-emitting stage100is to maintain the voltage difference between G and S-points so that the light-emitting unit emits light.
Vs=VLED+VSS, Vg=Vdata2+VLED+VSS−(Vpre−Vth)−(Vdata2−Vpre)*C2/(C1+C2),Vgs−Vth=Vdata2−Vpre−(Vdata2−Vpre)*C2/(C1+C2).

It can be understood that the second timing sequence is used to compensate the threshold voltage. When the second transistor is turned on, at this time, Vpre−Vref>Vth. When the second transistor works in a saturation zone, Vds>Vgs−Vth. When the light-emitting unit is turned off, Vpre−Vth−VSS<VLED. The compensation range of the threshold voltage is: Vpre−VSS−VLED<Vth<VDataL−Vref.

The present disclosure also proposes a display panel, a display module, and a display device. The display panel, the display module, and the display device all include the above-mentioned pixel driving circuit, which will not be described again here.

The pixel driving circuit provided by the embodiments of the present disclosure includes the light-emitting module, the external detection module, and the internal compensation module. The light-emitting module is electrically connected to the reset module, the external detection module, and the internal compensation module. The external detection module is configured to acquire the threshold voltage of the second transistor when the display panel is started, and determine the shift direction of the threshold voltage. The internal compensation module is configured to use the first timing sequence to compensate the threshold voltage when the shift direction of the threshold voltage is the positive shift. The internal compensation module is configured to use the second timing sequence to compensate the threshold voltage when the shift direction of the threshold voltage is the negative shift. Through internal compensation in different timing sequences, internal real-time compensation with more accuracy and larger compensation range is achieved.

In the foregoing embodiments, the description of each embodiment has its own emphasis. For the parts not described in detail in one embodiment, reference may be made to related descriptions in other embodiments.

The pixel driving circuit of the embodiments of the present disclosure have been described in detail above. Specific examples have been used in the specification to explain the principles and implementation manners of the present disclosure. The descriptions of the above embodiments are only used to facilitate understanding of the methods and core ideas of the present disclosure. Persons of ordinary skill in the art may change the implementation and application scope according to the ideas of the present application. In summary, the content of this specification should not be construed as a limitation on the present disclosure.