Patent ID: 12193142

DETAILED DESCRIPTION

FIG.1is an electronic schematic of a quantum mechanical circuit100, according to an embodiment of the present invention. The quantum mechanical circuit100includes a substrate102. The quantum mechanical circuit100also includes a first electrical conductor104, and a second electrical conductor106provided on the substrate102. The quantum mechanical circuit100further includes a third electrical conductor108(shown inFIG.2) to electrically connect the first electrical conductor104and the second electrical conductor106. The third electrical conductor108is a poor thermal conductor. The term “poor thermal conductor” is used herein broadly to mean the third electrical conductor108has a thermal conductivity substantially lower than a thermal conductivity of the first electrical conductor104and the thermal conductivity of the second electrical conductor106. In an embodiment, the material of the third electrical conductor108(poor thermal conductor) can be selected to have a sufficiently low thermal conductivity such that the cooling apparatus (e.g., cooling vessel) in which the circuit100is used can sufficiently cool the circuit100to desired temperatures (e.g., temperatures of operation of the circuit). Selecting a material with a certain thermal conductivity is dependent on a system in which the circuit100is used. For example, if the cooling apparatus (e.g., cooling vessel) has enough cooling power, a material with a higher thermal conductivity can be acceptable.

FIG.2is a three-dimensional perspective view of electrical coupling between the first electrical conductor104, the second electrical conductor106, and the third electrical conductor108, according to an embodiment of the present invention. As shown inFIG.2, the third electrical conductor108is configured to electrically connect the first electrical conductor104and the second electrical conductor106. In an embodiment, the third electrical conductor108includes at least one of Copper-Nickel (CuNi) or stainless steel. In an embodiment, CuNi has an electrical resistivity that is approximately 3.8×10−8 Ωm at ambient temperature and a thermal conductivity that is between about 25 W/m° K and 40 W/m° K. However, as it must be appreciated other materials having poor thermal conductivity can also be used for the third electrical conductor108.

In an embodiment, the first electrical conductor104and the second electrical conductor106include copper (Cu). A material of the third electrical conductor108is different from a material of the first electrical conductor104and a material of the second electrical conductor106. In an embodiment, the material of the first electrical conductor104and the material of the second electrical conductor106can be substantially the same. For example, both the material of the first electrical conductor104and the material of the second electrical conductor106can be essentially copper (Cu) while the material of the third electrical conductor108is essentially CuNi and/or stainless steel. In an embodiment, the substrate102is an electrically non-conductive (electrically insulating) material such as silicon (Si), sapphire (Al2O3), printed circuit board material (e.g., FR-4 (woven glass and epoxy) or other laminate board, fiberglass), or a polymer (e.g., a polyimide), for example.

In an embodiment, the third electrical conductor108is coupled to the substrate102using fasteners110. In an embodiment, the fasteners110include brass fasteners, for example. However, other types of fasteners can also be used. In addition, in another embodiment, the third electrical conductor108can also be coupled to the substrate102using other means, such as by using an adhesive.

In an embodiment, the first electrical conductor104, the second electrical conductor106and the third electrical conductor108are configured to transmit a radiofrequency (RF) electrical current. In an embodiment, the first electrical conductor104and the second electrical conductor106are connected to electrical ground potential.

In an embodiment, the first electrical conductor104and the second electrical conductor106are electrically decoupled by providing a discontinuity, a gap or a channel112between the first electrical conductor104and the second electrical conductor106within the substrate102. The first electrical conductor104and the second electrical conductor106are spaced apart to provide the gap112therebetween.

FIG.3is a three-dimensional perspective view of a configuration of the first electrical conductor104and the second electrical conductor106, according to an embodiment of the present invention. As shown inFIG.3, a discontinuity, a gap or channel112is provided between the first electrical conductor104and the second electrical conductor106. In embodiment, as shown inFIG.3, two layers116A and116B can be used for signal transmission. For example, the discontinuity, channel or gap112in layers116A and116B provides improved thermal isolation and helps steer return current. This dual sided configuration provides an increase in density. In addition, in an embodiment, the top and bottom split locations112are offset by removing internal ground planes from the internal layers of the substrate102(not shown) and by providing blind vias (i.e., vias on layers116A and11B that are not aligned with each other) to reduce electrical coupling.

Furthermore, as shown inFIG.3, attenuator chips114can be provided on top and bottom sides of layers116A and116B to increase electrical signal isolation. The attenuator chips114are electrically coupled (e.g., wire-bonded or soldered, etc.) to the first and second electrical conductors104and106. In an embodiment, the attenuator chips114can be wire-bonded or soldered (for example, either surface mount soldered or ball grid array soldered) across the ground split112. In addition, in other embodiments, other types of components, such as a filter for example, can also be used in addition or alternatively to the attenuator chips114. In an embodiment, as shown inFIG.3, removing ground planes internal to the substrate102(not shown) by providing the discontinuity or gap112in both layers116A and116B allows to reduce coupling to increase thermal isolation. Furthermore, vias118can be arranged within the substrate102(not shown) to allow electrical signals to have proper electromagnetic mode conversion to reduce coupling. In this way, electromagnetic (EM) fields can use the electrical ground potential more efficiently for return current path across the discontinuity112in the ground planes (i.e., the discontinuity or gap or channel112between the first electrical conductor104and the second electrical conductor in both layer116A and layer116B). The electrical ground potential is thus provided by the first electrical conductor104, the second electrical conductor106and the third electrical conductor108connected to each other and to ground.

Therefore, as it can be appreciated from the above paragraphs, in some embodiments of the present invention, the problem of thermal isolation can be addressed by splitting the ground plane. The ground plane corresponds to the first electrical conductor104and the second electrical conductor106both connected to electrical ground potential. The splitting in the ground plane thus corresponds to the gap or discontinuity or channel112provided between the first electrical conductor104ad the second electrical conductor106. While the gap or channel112provides good thermal isolation, this may cause many issues with the return current path. As a result, the third electrical conductor108is provided to electrically connect the first electrical conductor104and the second electrical conductor106. However, to provide thermal isolation between the first electrical conductor104and the second electrical conductor106(in the ground plane in this example), the third electrical conductor108is selected as being a poor thermal conductor such as CuNi alloy or Stainless steel, for example. CuNi is relatively a good electrical conductor but a poor thermal conductor.

FIG.4is a schematic diagram showing a superconducting quantum mechanical computer200, according to an embodiment of the present invention. The superconducting quantum mechanical computer200includes a refrigeration system comprising a temperature-controlled vessel202. The superconducting quantum computer includes a quantum processor204disposed within the temperature-controlled vessel202, the quantum processor including a plurality of qubits206. The superconducting quantum mechanical computer200further includes the quantum mechanical circuit100disposed inside the temperature-controlled vessel202. As shown inFIG.1, the circuit100includes the substrate102, the first electrical conductor104and the second electrical conductor106provided on the substrate102. The circuit100also includes the third electrical conductor108for electrically connecting the first electrical conductor104and the second electrical conductor106, the third electrical conductor108being a poor thermal conductor. Each of the plurality of qubits206is provided on the substrate102and is at least electrically connected to ground via at least one of the first or second electrical conductors104and106.

FIG.5is a flow chart of a method of manufacturing the quantum mechanical circuit, according to an embodiment of the present invention. The method includes:

1. providing the substrate102(e.g., silicon, polymer, laminate board, fiberglass, etc.) having a top face and a bottom face, at S100;

2. forming a conductive layer (e.g., copper layer) on at least one of the top face and bottom face of the substrate, at S102;

3. forming conductor lines in a selected pattern on the substrate102by removing portions of the conductive layer, the conductor lines including first electrical conductor104and second electrical conductor106on the substrate102, the first electrical104and second electrical conductor106being spaced apart and separated by a gap therebetween, at S104; and
4. electrically connecting the first electrical conductor104and the second electrical conductor106using a third electrical conductor108(shown inFIG.2), the third electrical conductor108is a poor thermal conductor (e.g., CuNi or stainless steel), at S106. In an embodiment, the first and second electrical conductors104and106can be connected to electrical ground.

The method further includes, before forming the conductor lines in the selected pattern on the substrate102:5. applying a photoresist layer on the conductive layer;6. applying a light absorbing material on the photoresist layer in the selected pattern so as to cover portions of the photoresist layer corresponding to the selected pattern;7. irradiating the photoresist layer with electromagnetic radiation (e.g., ultraviolet radiation) to harden areas of the photoresist layer that are not covered by the light absorbing material;8. removing areas of the photoresist layer corresponding to the covered portions of the photoresist layer that are not hardened by the electromagnetic radiation to expose portions of the conductive layer;9. etching away the exposed portions of the conductive layer while not etching portions of the conductive layer under the hardened areas of the photoresist;10. removing the hardened areas of the photoresist layer to expose portions of the conductive layer that are not etched, the portions of the conductive layer not etched corresponding to the selected pattern to form the conductor lines; and11. forming vias within the substrate at selected locations within the substrate.

The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.