Patent ID: 12211807

DETAILED DESCRIPTION

The present disclosure is described with reference to the attached figures. The figures are not drawn to scale and they are provided merely to illustrate the disclosure. Several aspects of the disclosure are described below with reference to example applications for illustration. It should be understood that numerous specific details, relationships, and methods are set forth to provide an understanding of the disclosure. The present disclosure is not limited by the illustrated ordering of acts or events, as some acts may occur in different orders and/or concurrently with other acts or events. Furthermore, not all illustrated acts or events are required to implement a methodology in accordance with the present disclosure.

A microelectronic device includes a substrate having a semiconductor material extending to a top surface of the substrate. The microelectronic device includes an active component having a doped region in the semiconductor material. The active component may be manifested as a metal oxide semiconductor (MOS) transistor, a junction field effect transistor (JFET), a bipolar junction transistor, an insulated gate bipolar transistor (IGBT), a bipolar junction diode, and a Schottky diode, by way of example. The microelectronic device is configured to provide a first operational potential at a first region of the semiconductor material and to provide a second operational potential at a second region of the semiconductor material, during operation of the microelectronic device. The doped region is between the first region and the second region. The first region and the second region are approximately perpendicular to current flow through the doped region during operation of the microelectronic device. The first operational potential is generally different from the second operational potential. During operation of the microelectronic device, the first operational potential changes as the active component is switched from an on state to an off state, and vice versa. Current flows through the doped region parallel to a current flow direction, from the first region to the second region, or vice versa, during operation of the microelectronic device.

The microelectronic device includes field plate segments in trenches extending into the doped region from the top surface of the substrate. Each field plate segment is separated from the semiconductor material by a trench liner of dielectric material. The field plate segments include at least a first field plate segment nearest the first region of the doped region, a second field plate segment nearest the second region of the doped region, and a third field plate segment between the first field plate segment and the second field plate segment. The field plate segments may be arranged in rows and columns in the doped region, the rows being perpendicular to the current flow direction and the columns being parallel to the current flow direction.

The microelectronic device further includes circuitry electrically connected to each of the field plate segments. The circuit is configured to apply bias potentials to the field plate segments. All the bias potentials are between the first operational potential and the second operational potential. The bias potentials are monotonic with respect to distances of the field plate segments from the first region of the doped region. That is, the first field plate segment, being closer to the first region than the third field plate segment, will have a bias potential closer to the first operational potential, and thus further from the second operational potential, than the third field plate segment. The second field plate segment, being further from the first region than the third field plate segment, will have a bias potential further from the first operational potential, and thus closer to the second operational potential, than the third field plate segment.

The circuitry is configured to adjust the bias potentials to track changes in the first operational potential, as the active component is switched from the off state to the on state, and back to the off state. Applying the bias potentials as disclosed may reduce an electric field in the doped region, which may advantageously enable the active component to operate at a higher value of the first operational potential, with respect to the second operational potential, in an off state, than a similar active component without the field plate segments. Furthermore, applying the bias potentials as disclosed may enable the doped region to have a higher dopant concentration than the similar active component without the field plate segments, in an on state, advantageously reducing an ohmic resistance of the doped region compared to the similar active component.

In the off state, a magnitude of the difference between the first operational potential and the second operational potential may be more than 10 times the magnitude of the difference between the first operational potential and the second operational potential in the on state. Having the bias potentials track the changes in the first operational potential and the second operational potential, as the active component is switched, may maintain a maximum potential difference across the trench liners to less than 5 percent of a maximum difference between the first operational potential and the second operational potential, which enable thinner trench liners compared to similar active components without the circuitry. The thinner trench liners in turn enable more complete charge balance to be attained in the off state, and thus higher operating potentials for the active component.

It is noted that terms such as top, bottom, over, under, and below may be used in this disclosure. These terms should not be construed as limiting the position or orientation of a structure or element, but should be used to provide spatial relationship between structures or elements. For the purposes of this disclosure, the term “lateral” refers to directions parallel to a plane of the top surface of the substrate. The term “vertical” refers to a direction perpendicular to the plane of the top surface of the substrate. For the purposes of this disclosure, it will be understood that, if an element is referred to as being “directly coupled” or “directly connected” to another element, it is understood there are no other intentionally disposed intervening elements present.

It is to be noted that in the text as well as in all of the Figures, the respective structures will be termed the “microelectronic device” and labeled with corresponding reference numbers, even though the device is not yet completed until some of the last stages of manufacturing described herein. This is done primarily for the convenience of the reader.

FIG.1AthroughFIG.1Lare alternating top views and cross sections of an example microelectronic device having a doped region, depicted in stages of an example method of formation. Referring toFIG.1AandFIG.1B, the microelectronic device100is formed in and on a substrate102. The substrate102may be, for example, part of a bulk semiconductor wafer, part of a semiconductor wafer with an epitaxial layer, part of a silicon-on-insulator (SOI) wafer, or other structure suitable for forming the microelectronic device100. The substrate102may include other microelectronic devices, not shown. The substrate102includes a semiconductor material104which extends to a top surface106of the substrate102. In this example, the semiconductor material104may be p-type to start with.

The microelectronic device100includes an active component108. In this example, the active component108may be manifested as an n-channel extended drain MOS transistor108, and will be referred to as the MOS transistor108in the disclosure of this example. A doped region110is formed in the semiconductor material104, leaving a p-type portion104aof the semiconductor material104under the doped region110. The doped region110of this example is n-type, and may be formed by implanting n-type dopants, such as phosphorus, into the semiconductor material104, followed by annealing the substrate102to diffuse and activate the n-type dopants. The doped region110may have an average dopant concentration of the n-type dopants of 1×1016cm−2to 1×1017cm−2, by way of example. The doped region110may be part of an n-type well in the semiconductor material104. The doped region110of this example may provide a drift region of the MOS transistor108.

A dielectric layer112is formed on the substrate102, at the top surface106. The dielectric layer112of this example extends over the doped region110. The dielectric layer112may be implemented as field oxide112, with a thickness of 200 nanometers to 400 nanometers. In one version of this example, the dielectric layer112may be formed by a local oxidation of silicon (LOCOS) process, which includes forming a layer of thermal oxide at the top surface106, and forming a patterned layer of silicon nitride on the thermal oxide. The dielectric layer112is formed by thermal oxidation in areas exposed by the patterned layer of silicon nitride. The patterned layer of silicon nitride is subsequently removed. The dielectric layer112formed by the LOCOS process has tapered edges, as depicted inFIG.1B, referred to as bird's beaks. In another version of this example, the dielectric layer112may be formed by a shallow trench isolation (STI) process. Alternatively, the dielectric layer112may be implemented as a field plate isolation layer, with a thickness of 100 nanometers to 250 nanometers. The dielectric layer112implemented as the field plate isolation layer may be formed by forming a layer of thermal oxide at the top surface106, and forming a layer of silicon dioxide by a low pressure chemical vapor deposition (LPCVD) process using dichlorosilane and oxygen on the thermal oxide. The layer of silicon dioxide is subsequently patterned by etching to provide the dielectric layer112. Other methods of forming the dielectric layer112are within the scope of this example.

A drain well114of the MOS transistor108is formed in the semiconductor material104at a first region116of the semiconductor material104. The drain well114of this example is n-type, and has a higher average concentration of n-type dopants than the doped region110. The term “well” as used in this disclosure is intended to mean either an n-type well or a p-type well, and includes the case in which the well that has the same conductivity type as the semiconductor material surrounding the well. N-type dopants in the drain well114may include phosphorus and arsenic, for example. The drain well114may be formed by implanting the n-type dopants into the semiconductor material104, and subsequently annealing the substrate102to activate and diffuse the n-type dopants.

A body region118of the MOS transistor108is formed in the semiconductor material104proximate to a second region120of the semiconductor material104. The doped region110is between the first region116and the second region120. The body region118of this example is p-type, and may have an average concentration of p-type dopants, such as boron, of 1×1017cm−2to 1×1018cm−2, by way of example. The body region118may be formed by implanting the p-type dopants into the semiconductor material104, and subsequently annealing the substrate102to activate and diffuse the p-type dopants. In one version of this example, the n-type dopants may be implanted into the semiconductor material104for the drain well114and the p-type dopants may be implanted into the semiconductor material104for the body region118, and the substrate102may be subsequently annealed to concurrently activate and diffuse the p-type dopants in the body region118and the n-type dopants in the drain well114.

During operation of the MOS transistor108, current may flow from the first region116to the second region120. The current flows parallel to a current flow direction122which extends from the first region116to the second region120.

Referring toFIG.1CandFIG.1D, trenches124are formed through the dielectric layer112and in the semiconductor material104from the top surface106, extending into the doped region110. In this example, the trenches124may extend through the doped region110into the p-type portion104aof the semiconductor material104under the doped region110, as depicted inFIG.1D. The trenches124may have lateral dimensions of 1 micron to 10 microns, by way of example.

The trenches124of this example may be arranged in seriate alternating rows126. Each row126is perpendicular to the current flow direction122, as depicted inFIG.1C. Instances of the trenches124in a same row126are equidistant from the first region116of the semiconductor material104, within fabrication tolerances encountered in forming the microelectronic device100. Other arrangements of the trenches124are within the scope of this example.

The trenches124may be formed by etching, such as by a reactive ion etch (RIE) process. A hard mask, not shown, of silicon nitride or sublayers of silicon nitride and silicon dioxide may be formed over the dielectric layer112, exposing areas for the trenches124, and the RIE process may then remove material from the dielectric layer112and the semiconductor material104to form the trenches124. The hard mask may subsequently be removed. Other methods of forming the trenches124are within the scope of this example. The trenches124may have equal lateral dimensions, with rounded rectangular shapes, as depicted inFIG.1C. Other shapes for the trenches124are within the scope of this example.

Referring toFIG.1EandFIG.1F, trench liners128are formed in the trenches124, contacting the semiconductor material104. The trench liners128may include primarily silicon dioxide formed by thermal oxidation of silicon, referred to as thermal oxide, in the semiconductor material104abutting the trenches124. Thermal oxide may be characterized by having a stoichiometry of SiO2with less than 0.1 atomic percent of hydrogen. Thermal oxide may advantageously provide a higher dielectric strength and uniform thickness in the trenches124compared to other materials for the trench liners128. The trench liners128may have a thickness of 5 nanometers to 50 nanometers, which may advantageously enable more complete charge balance in the doped region110during operation of the MOS transistor108compared to thicker trench liners128.

In this example, a gate dielectric layer130of the MOS transistor108may be formed concurrently with the trench liners128. The gate dielectric layer130is formed at the top surface106, extending to the dielectric layer112, over the body region118and over the doped region110exposed by the dielectric layer112at the second region120of the semiconductor material104. A layer of pad oxide132may be concurrently formed at the top surface106, over the drain well114and the first region116. Forming the gate dielectric layer130concurrently with the trench liners128may advantageously reduce fabrication cost and complexity of the microelectronic device100.

Referring toFIG.1GandFIG.1H, a conductive layer134is formed over the microelectronic device100, on the trench liners128, the dielectric layer112, and the gate dielectric layer130. The conductive layer134may include polycrystalline silicon, commonly referred to as polysilicon, and may include n-type dopants such as phosphorus or arsenic. The conductive layer134may be formed by thermal decomposition of silane or disilane, by way of example. In alternate versions of this example, the conductive layer134may include another electrically conductive material, such as titanium nitride or tantalum nitride.

A gate mask136is formed over the conductive layer134, on an area for a gate138, shown inFIG.1IandFIG.1J, of the MOS transistor108. The area for the gate138extends partway over the body region118, partway over the doped region110, and partway onto the dielectric layer112. The gate mask136may include photoresist, formed by a photolithographic process, and organic anti-reflection material, or may include hard mask material such as silicon dioxide or silicon nitride, and inorganic anti-reflection material. In an alternate version of this example, the gate mask136may extend over the dielectric layer112partway to the first region116, with openings for the trenches124.

Referring toFIG.1IandFIG.1J, a portion of the conductive layer134ofFIG.1GandFIG.1His removed by an etch process, leaving the conductive layer134under the gate mask136to form the gate138of the MOS transistor108. The gate138extends partway over the body region118proximate to the second region120of the semiconductor material104and partway over the doped region110exposed by the dielectric layer112, and partway onto the dielectric layer112. The conductive layer134is left in the trenches124to form field plate segments140on the trench liners128. The field plate segments140are separated from the semiconductor material104by the trench liners128. In versions of this example in which the gate mask136extends over the dielectric layer112partway to the first region116, the conductive layer134is left over the doped region110, between the trenches124, to provide a horizontal field plate, not shown.

The etch process to remove the portion of the conductive layer134may include an RIE step, for example. After the etch process is completed, the gate mask136is removed. Organic material in the gate mask136may be removed by oxygen radicals in an asher process, followed by a wet clean process using an aqueous mixture of sulfuric acid and hydrogen peroxide. Inorganic material in the gate mask136may be removed by a plasma etch using fluorine that has selectivity with respect to the gate138. Forming the gate138concurrently with the field plate segments140may further advantageously reduce fabrication cost and complexity of the microelectronic device100.

Referring toFIG.1KandFIG.1L, sidewall spacers142may be formed on vertical surfaces of the gate138. The sidewall spacers142may include one or more layers of silicon dioxide and silicon nitride, formed by one or more LPCVD or plasma enhanced chemical vapor deposition (PECVD) processes, followed by an anisotropic plasma etch to remove the layers of silicon dioxide and silicon nitride from horizontal surfaces of the microelectronic device100.

A body contact region144of the MOS transistor108is formed in the semiconductor material104, contacting the body region118. The body contact region144is p-type, and has a higher average concentration of p-type dopants than the body region118. The body contact region144may be formed by implanting p-type dopants into the semiconductor material104, or diffusing p-type dopants into the semiconductor material104from a solid source, such as a doped oxide, by way of example.

A source region146of the MOS transistor108is formed in the semiconductor material104at the second region120, adjacent to the gate138and extending partway under the gate138, contacting the body region118. A drain contact region148of the MOS transistor108is formed in the semiconductor material104at the first region116, contacting the drain well114. The source region146and the drain contact region148are n-type, and each has a higher average concentration of n-type dopants than the drain well114. The source region146and the drain contact region148may be formed concurrently by implanting or diffusing n-type dopants into the semiconductor material104.

Metal silicide150is formed on exposed silicon, including polysilicon, on the microelectronic device100, including on the gate138, the body contact region144, the source region146, the drain contact region148, and the field plate segments140. The metal silicide150may include titanium silicide, cobalt silicide, or nickel silicide, by way of example. The metal silicide150may be formed by forming a layer of metal on the microelectronic device100, contacting the exposed silicon. Subsequently, the microelectronic device100is heated to react the layer of metal with the exposed silicon to form the metal silicide150. Unreacted metal is removed from the microelectronic device100, leaving the metal silicide150in place. The unreacted metal may be removed by a wet etch process using an aqueous mixture of sulfuric acid and hydrogen peroxide, or an aqueous mixture of nitric acid and hydrochloric acid, by way of example. The metal silicide150may provide electrical connections to the gate138, the body contact region144, the source region146, the drain contact region148, and the field plate segments140with lower resistance compared to a similar microelectronic device without metal silicide.

A pre-metal dielectric (PMD) layer152of the microelectronic device100is formed over the substrate102, the dielectric layer112and the metal silicide150. The PMD layer152is electrically non-conductive, and may include one or more sublayers of dielectric material. By way of example, the PMD layer152may include a PMD liner, not shown, of silicon nitride, formed by an LPCVD process or a PECVD process, contacting the substrate102, the dielectric layer112and the metal silicide150. The PMD layer152may also include a planarized layer, not shown, of silicon dioxide, phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG), formed by a PECVD process using tetraethyl orthosilicate (TEOS), formally named tetraethoxysilane, a high density plasma (HDP) process, or a high aspect ratio process (HARP) using TEOS and ozone, on the PMD liner. The PMD layer152may further include a PMD cap layer, not shown, of silicon nitride, silicon carbide, or silicon carbonitride, suitable for an etch-stop layer of a chemical-mechanical polish (CMP) stop layer, formed by a PECVD process using TEOS and bis(tertiary-butyl-amino)silane (BTBAS), on the planarized layer. Other layer structures and compositions for the PMD layer152are within the scope of this example. The PMD layer152is not shown inFIG.1K, to depict the remaining elements of the microelectronic device100more clearly.

Contacts154are formed through the PMD layer152, making electrical connections to the metal silicide150on the gate138, the body contact region144, the source region146, the drain contact region148, and the field plate segments140. Each of the field plate segments140is electrically coupled through the metal silicide150to at least one corresponding contact154The contacts154are electrically conductive, and may include a contact liner, not shown, of titanium and titanium nitride contacting the PMD layer152and the metal silicide150, with a tungsten core, not shown, on the liner. The contacts154may be formed by etching contact holes through the PMD layer152to expose the metal silicide150. The contact liner may be formed by sputtering titanium followed by forming titanium nitride using an atomic layer deposition (ALD) process. The tungsten core may be formed by a metalorganic chemical vapor deposition (MOCVD) process using tungsten hexafluoride (WF6) reduced by silane initially and hydrogen after a layer of tungsten is formed on the contact liner. The tungsten, titanium nitride, and titanium is subsequently removed from a top surface of the PMD layer152by an etch process, a tungsten CMP process, or a combination of both, leaving the contacts154extending to the top surface of the PMD layer152. Other structures and compositions for the contacts154are within the scope of this example.

Interconnects156are formed on the PMD layer152, making electrical connections to the contacts154. The interconnects156are electrically conductive. In one version of this example, the interconnects156may have an etched aluminum structure, and may include an adhesion layer, not shown, of titanium nitride or titanium tungsten, on the PMD layer152, an aluminum layer, not shown, with a few atomic percent of silicon, titanium, or copper, on the adhesion layer, and an anti-reflection layer, not shown, of titanium nitride on the aluminum layer. The etched aluminum interconnects may be formed by depositing the adhesion layer, the aluminum layer, and the anti-reflection layer, and forming an etch mask, not shown, followed by an RIE process to etch the anti-reflection layer, the aluminum layer, and the adhesion layer where exposed by the etch mask, and subsequently removing the etch mask. In another version of this example, the interconnects156may have a damascene structure, and may include a barrier liner of tantalum and tantalum nitride in an interconnect trench in an intra-metal dielectric (IMD) layer, not shown, on the PMD layer152, with a copper fill metal in the interconnect trench on the barrier liner. The damascene interconnects may be formed by depositing the IMD layer on the PMD layer152, and etching the interconnect trenches through the IMD layer to expose the contacts154. The barrier liner may be formed by sputtering tantalum onto the IMD layer and exposed PMD layer152and contacts154, and forming tantalum nitride on the sputtered tantalum by an ALD process. The copper fill metal may be formed by sputtering a seed layer, not shown, of copper on the barrier liner, and electroplating copper on the seed layer to fill the interconnect trenches. Copper and barrier liner metal is subsequently removed from a top surface of the IMD layer by a copper CMP process. In further version of this example, the interconnects156may have a plated structure, and may include an adhesion layer, not shown, on the PMD layer152and the contacts154, with copper interconnects on the adhesion layer. The plated interconnects may be formed by sputtering the adhesion layer, containing titanium, on the PMD layer152and contacts154, followed by sputtering a seed layer, not shown, of copper on the adhesion layer. A plating mask is formed on the adhesion layer that exposes areas for the interconnects156. The copper interconnects are formed by electroplating copper on the seed layer where exposed by the plating mask. The plating mask is removed, and the seed layer and the adhesion layer are removed by wet etching between the interconnects.

In this example, instances of the field plate segments140that are in a same row126are directly electrically coupled to one of the interconnects156through the metal silicide150and the contacts154. Instances of the field plate segments140that are not in a same row126are not directly electrically coupled to the same interconnect156. Thus, the field plate segments140in one of the rows126may be biased independently of the field plate segments140in another of the rows126.

During operation of the microelectronic device100, a first operational potential is provided to the first region116of the semiconductor material104. In this example, the first operational potential may be implemented by a drain potential applied to the drain contact region148. In one version of this example, the drain potential may be generated by an external potential source that is external to the microelectronic device100, and the microelectronic device100may be configured to provide the first potential to the first region116by the microelectronic device100having instances of the metal silicide150, the contacts154, and the interconnects156directly electrically coupled in series to the external potential source, for example, through an input/output (I/O) pad such as a bond pad or solder bump. In one version of this example, the drain potential may be generated by an internal potential source that is internal to the microelectronic device100, and the microelectronic device100may be configured to provide the first potential to the first region116by the microelectronic device100having instances of the metal silicide150, the contacts154, and the interconnects156directly electrically coupled in series to the internal potential source.

Also during operation of the microelectronic device100, a second operational potential is provided to the second region120of the semiconductor material104. In this example, the second operational potential may be implemented by a source potential applied to the source region146. In one version of this example, the source potential may be generated by an external potential source that is external to the microelectronic device100; in another version, the source potential may be generated by an internal potential source that is internal to the microelectronic device100. The microelectronic device100may be configured to provide the second potential to the second region120by the microelectronic device100having instances of the metal silicide150, the contacts154, and the interconnects156directly electrically coupled in series to the external potential source or the internal potential source, as appropriate.

When the MOS transistor108is in an off state, the first operational potential may be significantly higher, for example, 30 volts to 1000 volts higher, than the second operational potential. When the MOS transistor108is in an on state, the first operational potential may be a few volts higher than the second operational potential. In an alternate version of this example, in which the MOS transistor108is manifested as a p-channel MOS transistor, the first operational potential may be significantly lower than the second operational potential in the off state, and may be a few volts lower than the second operational potential in the on state.

Circuitry158is formed in the microelectronic device100. The circuitry158is electrically connected to each of the field plate segments140through the interconnects156, the contacts154, and the metal silicide150. The circuitry158is configured to apply bias potentials to the field plate segments140. All the bias potentials are between the first operational potential and the second operational potential. The bias potentials are monotonic with respect to distances of the field plate segments140from the first region116of the semiconductor material104. That is, the circuitry158is configured to provide bias potentials that are closer to the first operational potential for instances of the field plate segments140that are closer to the first region116than other instances of the field plate segments140that are farther from the first region116. In this example, all the field plate segments140in one row126are a same distance from the first region116, and are provided a same bias potential, as a result of being electrically coupled to a same interconnect156through electrically conductive elements of the microelectronic device100. The circuitry158may include a resistor ladder160with internal nodes162electrically coupled through buffers164to the interconnects156in the rows126, and end terminals of the resistor ladder160connected to the drain contact region148and the source region146. The buffers164may be implemented as source follower buffers164, as indicated schematically inFIG.1KandFIG.1L. Having the buffers164coupled between the internal nodes162and the interconnects156may enable the resistor ladder160to have a high impedance, advantageously reducing power consumption by the circuitry158.

The monotonic relationship between the bias potentials and distances from the first region116is discussed in reference toFIG.4AandFIG.4B. To illustrate the monotonic relationship with respect to this example, the field plate segments140include a first field plate segment140anearest the first region116, a second field plate segment140bnearest the second region120, and a third field plate segment140cbetween the first field plate segment140aand the second field plate segment140b. The circuitry158is configured to apply a first bias potential to the first field plate segment140a, apply a second bias potential to the second field plate segment140b, and apply a third bias potential to the third field plate segment140c. The first bias potential, the second bias potential, and the third bias potential are all between the first operational potential and the second operational potential. The first bias potential is between the first operational potential and the third bias potential. The second bias potential is between the third bias potential and the second operational potential. The third bias potential is between the first bias potential and the second bias potential.

Having the circuitry158configured to provide the bias potentials in the monotonic relationship with respect to distances of the field plate segments140from the first region116may reduce an electric field in the doped region110, which may advantageously enable the MOS transistor108to operate at a higher drain bias with respect to the source bias, that is, higher value of the first operational potential, with respect to the second operational potential, in the off state, than a similar MOS transistor without field plate segments. Furthermore, having the circuitry158configured to provide the bias potentials as disclosed in this example may enable the doped region110to have a higher dopant concentration than the similar MOS transistor without field plate segments, in the on state, advantageously reducing an ohmic resistance of the doped region110compared to the similar MOS transistor. Having the field plate segments140arranged in seriate alternating rows126may provide a desired balance between uniformity of the electric field in the doped region110in the off state and ohmic resistance of the doped region110in the on state. The circuitry158is configured to adjust the bias potentials applied to the field plate segments140as the first operational potential and the second operational potential change during switching the MOS transistor108from the off state to the on state, and back to the off state, accruing the advantage of lower potential difference across the trench liners128, and hence higher operating potential, as explained above.

FIG.2AthroughFIG.2Fare alternating top views and cross sections of another example microelectronic device having a doped region, depicted in stages of an example method of formation. Referring toFIG.2AandFIG.2B, the microelectronic device200is formed in and on a substrate202. The substrate202of this example is part of an SOI wafer having a substrate dielectric layer266and a semiconductor material204which extends from the substrate dielectric layer266to a top surface206of the substrate202. In alternate versions of this example, the substrate202may be implemented as a bulk semiconductor wafer, a wafer having an epitaxial semiconductor layer, or other structure suitable for forming the microelectronic device200. The substrate202may include other microelectronic devices, not shown.

The microelectronic device200includes an active component208. In this example, the active component208may be manifested as an NPN IGBT208, and will be referred to as the IGBT208in the disclosure of this example. A doped region210is formed in the semiconductor material204. The doped region210of this example is n-type, and may be formed by implanting n-type dopants, such as phosphorus, into the semiconductor material204, followed by annealing the substrate202to diffuse and activate the n-type dopants. The doped region210may have an average dopant concentration of the n-type dopants of 1×1016cm−2to 1×1017cm−2, by way of example. The doped region210is between a first region216in the semiconductor material204and a second region220in the semiconductor material204. The doped region210of this example may provide a drift region210of the IGBT208. The first region216may be implemented, in this example, as a collector contact region, and the second region220may be implemented, in this example, as an emitter contact region. In this example, an n-type buried layer268may be formed in the semiconductor material204below the doped region210. The n-type buried layer268may extend across the semiconductor device200. The n-type buried layer268may be formed before the doped region210is formed. The n-type buried layer268has a higher average dopant concentration of the n-type dopants than the doped region210. By way of example, the n-type buried layer268may have an average dopant concentration of n-type dopants of 1×1017cm−2to 1×1018cm−2.

A p-type buried layer270may be formed in the semiconductor material204, under the second region220of the semiconductor material204. The p-type buried layer270may be localized, or patterned, to extend only partway under the doped region210from the second region220. The p-type buried layer270may be formed so that the semiconductor material204extends under the p-type buried layer270, as depicted inFIG.2B. Alternatively, the p-type buried layer270may be formed so as to extend to the substrate dielectric layer266. The p-type buried layer270may be formed before the doped region210is formed.

A dielectric layer212is formed on the substrate202, at the top surface206. The dielectric layer212of this example extends over the doped region210. The dielectric layer212may be implemented as field oxide212, with a thickness of 250 nanometers to 500 nanometers. In one version of this example, the dielectric layer212may be formed by an STI process, which includes etching isolation trenches in the semiconductor material204. The isolation trenches are with silicon dioxide by one or more deposition processes, including thermal oxidation, atmospheric pressure chemical vapor deposition (APCVD), HDP, or HARP. The deposition processes may be alternated with etchback processes, to reduce a thickness of the silicon dioxide over the top surface206of the substrate202. The silicon dioxide over the top surface206by an oxide CMP process or an etchback process, or a combination of both. In another version of this example, the dielectric layer212may be formed by a LOCOS process. Alternatively, the dielectric layer212may be implemented as a field plate isolation layer. Other methods of forming the dielectric layer212are within the scope of this example.

A collector well214of the IGBT208is formed in the semiconductor material204under the first region216of the semiconductor material204. The collector well214of this example is n-type, and has a higher average concentration of n-type dopants than the doped region210. N-type dopants in the collector well214may include phosphorus and arsenic, for example. The collector well214may be formed by implanting the n-type dopants into the semiconductor material204, and subsequently annealing the substrate202to activate and diffuse the n-type dopants.

A base region218of the IGBT208is formed in the semiconductor material204under the second region220of the semiconductor material204. The base region218of this example is p-type, and may have an average concentration of p-type dopants, such as boron, of 1×1017cm−2to 1×1018cm−2, by way of example. The base region218may be formed by implanting the p-type dopants into the semiconductor material204, and subsequently annealing the substrate202to activate and diffuse the p-type dopants. In one version of this example, the n-type dopants may be implanted into the semiconductor material204for the drain well214and the p-type dopants may be implanted into the semiconductor material204for the base region218, and the substrate202may be subsequently annealed to concurrently activate and diffuse thep-type dopants in the base region218and the n-type dopants in the drain well214.

A gate dielectric layer230of the IGBT208is formed at the top surface206of the substrate202, at the second region220of the semiconductor material204. The gate dielectric layer230extends partway over the doped region210to the dielectric layer212, and partway over the base region218adjacent to the doped region210. The gate dielectric layer230of this example may include silicon dioxide, hafnium oxide, zirconium oxide, tantalum oxide, or other dielectric material, optionally with nitrogen added to improve reliability. The gate dielectric layer230of this example may have a thickness of 2 nanometers to 50 nanometers, by way of example.

A gate238of the IGBT208is formed on the gate dielectric layer230and extending partway onto the dielectric layer212. The gate238may include polysilicon, metal silicide, as in a fully silicided (FUSI) gate, or one or more metals, such as titanium, titanium nitride, tantalum, or tantalum nitride, as in a metal replacement gate. Sidewall spacers242may be formed on vertical surfaces of the gate238. The sidewall spacers242may have structures and compositions as disclosed in reference to the sidewall spacers142ofFIG.1KandFIG.1L. In an alternate version of this example, the gate238may extend further on the dielectric layer212to provide a horizontal field plate, not shown, as disclosed in reference toFIG.1IandFIG.1J.

An emitter region246of the IGBT208is formed in the semiconductor material204at the second region220, contacting the base region218. The emitter region246is n-type, and has an average dopant concentration higher than the collector well214, for example, above 1×1018cm−2. The emitter region246may be formed by implanting or diffusing n-type dopants into the semiconductor material204, followed by annealing the semiconductor material204.

A collector injection region248of the IGBT208is formed in the semiconductor material204at the first region216, contacting the collector well214. The collector injection region248is p-type, and has an average concentration of p-type dopants above 1×1018cm−2, by way of example. The collector injection region248may be formed by implanting or diffusing the p-type dopants into the semiconductor material204, followed by annealing the semiconductor material204.

Annealing the semiconductor material204for the emitter region246and the collector injection region248may be implemented as a rapid thermal anneal, a spike anneal, or a flash anneal, by way of example. A rapid thermal anneal may heat the substrate202to 1000° C. to 1150° C. for 5 seconds to 60 seconds, and may be implemented in a rapid thermal processor using an incandescent lamp. A spike anneal may heat the substrate202to 1100° C. to 1250° C. for 100 milliseconds seconds to 5 seconds, and may be implemented an arc flash lamp. A flash anneal may heat the substrate202to 1200° C. to 1350° C. for 50 microseconds to 1 millisecond, and may be implemented by a flash lamp or scanned laser. The annealing process may be selected to balance activating as many of the n-type dopants and p-type dopants as possible while controlling diffusion of the n-type dopants and p-type dopants.

During operation of the IGBT208, current may flow from the first region216of the semiconductor material204to the second region220, parallel to a current flow direction222which extends from the first region216to the second region220.

Referring toFIG.2CandFIG.2D, trenches224are formed through the dielectric layer212and in the semiconductor material204from the top surface206, extending into the doped region210. In this example, the trenches224may terminate in the doped region210, so that the doped region210extends under the trenches224, as depicted inFIG.2D. The trenches224may have lateral dimensions similar to the trenches124ofFIG.1CandFIG.1D. The trenches224may have rounded rectangular shapes with unequal lateral dimensions, in which the larger lateral dimension is oriented perpendicular to the current flow direction222, as depicted inFIG.2C. Other shapes and orientations for the trenches224are within the scope of this example.

The trenches224may be arranged in rows226and columns272. Each row226is perpendicular to the current flow direction222, and each column272is parallel to the current flow direction222, as depicted inFIG.2C. Instances of the trenches224in a same row226are equidistant from the first region216of the semiconductor material204, within fabrication tolerances encountered in forming the microelectronic device200. Other arrangements of the trenches224are within the scope of this example. The trenches224may be formed as disclosed for the trenches124ofFIG.1CandFIG.1D.

Trench liners228are formed in the trenches224, contacting the semiconductor material204. The trench liners228may include primarily thermal oxide, or may include thermal oxide and one or more layers of deposited dielectric material such as silicon nitride or silicon oxynitride, formed by a PECVD process. The trench liners228may have a thickness of 5 nanometers to 50 nanometers, which may advantageously enable more complete charge balance in the doped region210during operation of the MOS transistor208compared to thicker trench liners228. Forming the trench liners228separately from the gate dielectric layer230may advantageously enable the thicknesses and compositions of the trench liners228and the gate dielectric layer230to be independently optimized.

Referring toFIG.2EandFIG.2F, field plate segments240are formed in the trenches224on the trench liners228. The field plate segments240are electrically conductive, and may include polysilicon, aluminum, copper, titanium, titanium nitride, tantalum, tantalum nitride, by way of example. The field plate segments240may be formed using a sputter process, an electroplating process, an ALD process, or any combination thereof. Other processes for forming the field plate segments240are within the scope of this example.

A PMD layer252of the microelectronic device200is formed over the substrate202, the dielectric layer212the gate238, and the field plate segments240. The PMD layer252may have a similar layer structure and composition as disclosed for the PMD layer152ofFIG.1KandFIG.1L. Contacts254are formed through the PMD layer252, making electrical connections to the field plate segments240, the gate238, the emitter region246, and the collector injection region248. Each of the field plate segments240is electrically coupled through electrically conductive elements or directly electrically connected to at least one corresponding contact254The contacts254are electrically conductive. The contacts254may have a structure and composition, and may be formed, as disclosed for the contacts154ofFIG.1KandFIG.1L. Interconnects256are formed on the PMD layer252, making electrical connections to the contacts254. The interconnects256are electrically conductive. The interconnects256may have a structure and composition, and may be formed, as disclosed for the interconnects156ofFIG.1KandFIG.1L. In this example, instances of the field plate segments240that are in a same row226are directly electrically coupled to one of the interconnects256through the contacts254. Instances of the field plate segments240that are not in a same row226are not directly electrically coupled to the same interconnect256. Thus, the field plate segments240in one of the rows226may be biased independently of the field plate segments240in another of the rows226. The PMD layer252is not shown inFIG.2E, to depict the remaining elements of the microelectronic device200more clearly.

During operation of the microelectronic device200, a first operational potential is provided to the first region216of the semiconductor material204. In this example, the first operational potential may be implemented as a collector potential applied to the collector injection region248. Also during operation of the microelectronic device200, a second operational potential is provided to the second region220of the semiconductor material204. In this example, the second operational potential may be implemented as an emitter potential applied to the emitter region246. When the IGBT208is in an off state, the first operational potential may be significantly higher, for example, 30 volts to 1000 volts higher, than the second operational potential. When the IGBT208is in an on state, the first operational potential may be a few volts higher than the second operational potential. In an alternate version of this example, in which the IGBT208is manifested as a PNP IGBT, the first operational potential may be significantly lower than the second operational potential in the off state, and may be a few volts lower than the second operational potential in the on state.

Circuitry258is formed in the microelectronic device200. The circuitry258is configured to apply bias potentials to each of the field plate segments240through the interconnects256and the contacts254. All the bias potentials are between the first operational potential and the second operational potential. The circuitry258may include a resistor ladder260with internal nodes262electrically coupled to the interconnects256in the rows226. End terminals of the resistor ladder260may be connected to the collector injection region248and the emitter region246. The internal nodes262may be directly electrically coupled to the interconnects256, as indicated schematically inFIG.2EandFIG.2F. Having the internal nodes262of the resistor ladder260directly electrically coupled to the interconnects256may reduce complexity and area of the circuitry258, and thus advantageously reduce fabrication cost and complexity of the microelectronic device200.

The bias potentials are monotonic with respect to distances of the field plate segments240from the first region216of the semiconductor material204, as explained in reference toFIG.1KandFIG.1L. To illustrate the monotonic relationship with respect to this example, the field plate segments240include a first field plate segment240anearest the first region216, a second field plate segment240bnearest the second region220, and a third field plate segment240cbetween the first field plate segment240aand the second field plate segment240b. The circuitry258is configured to apply a first bias potential to the first field plate segment240a, apply a second bias potential to the second field plate segment240b, and apply a third bias potential to the third field plate segment240c. The first bias potential, the second bias potential, and the third bias potential are all between the first operational potential and the second operational potential. The first bias potential is between the first operational potential and the third bias potential. The second bias potential is between the third bias potential and the second operational potential. The third bias potential is between the first bias potential and the second bias potential.

Having the circuitry258configured to provide the bias potentials in the monotonic relationship with respect to distances of the field plate segments240from the first region216may accrue the advantages disclosed in reference to the MOS transistor108ofFIG.1KandFIG.1L. Having the field plate segments240arranged in rows226and columns272may provide a desired low ohmic resistance of the doped region210in the on state. The circuitry258is configured to adjust the bias potentials applied to the field plate segments240as the first operational potential and the second operational potential change during switching the MOS transistor208from the off state to the on state, and back to the off state, accruing the advantage of lower potential difference across the trench liners228, and hence higher operating potential, as explained above. Forming the field plate segments240to include aluminum or copper may reduce a resistance of the field plate segments240compared to polysilicon, and so reduce a resistor-capacitor (RC) time constant of the field plate segments240combined with the trench liners228, advantageously enabling the field plate segments240to follow changes in the first operational potential and the second operational potential.

FIG.3AthroughFIG.3Jare alternating top views and cross sections of a further example microelectronic device having a doped region, depicted in stages of an example method of formation. Referring toFIG.3AandFIG.3B, the microelectronic device300is formed in and on a substrate302. The substrate302of this example may be part of a semiconductor wafer. The substrate302has a semiconductor material304which includes a base semiconductor material374. In this example, the base semiconductor material374may be n-type, as indicated inFIG.3B. The substrate302may include other microelectronic devices, not shown. The microelectronic device300includes an active component308. In this example, the active component308may be manifested as Schottky diode308.

Epitaxial-blocking pillars376are formed on the base semiconductor material374to define regions for subsequently-formed trenches324, shown inFIG.3EandFIG.3F. The epitaxial-blocking pillars376include material such as silicon dioxide, silicon nitride, or silicon-doped boron nitride or other epitaxial-blocking material which blocks formation of epitaxial silicon. The epitaxial-blocking pillars376may be formed by forming a layer of the epitaxial-blocking material on the base semiconductor material374, and forming an etch mask, not shown, over the layer of the epitaxial-blocking material to define areas for the epitaxial-blocking pillars376. The layer of the epitaxial-blocking material is removed where exposed by the etch mask, leaving the epitaxial-blocking material under the etch mask to form the epitaxial-blocking pillars376. The epitaxial-blocking pillars376may have lateral dimensions similar to the lateral dimensions disclosed for the trenches124ofFIG.1CandFIG.1D. The epitaxial-blocking pillars376have vertical dimensions greater than a thickness of a subsequently-formed doped region310, shown inFIG.3CandFIG.3D.

During operation of the Schottky diode308, current may flow in the subsequently-formed doped region310, shown inFIG.3CandFIG.3D, parallel to a current flow direction322. The epitaxial-blocking pillars376may be arranged in alternating rows326, so that each epitaxial-blocking pillar376is equidistant from neighboring epitaxial-blocking pillars376.

Referring toFIG.3CandFIG.3D, a semiconductor layer304aof the semiconductor material304is formed on the base semiconductor material374where exposed by the epitaxial-blocking pillars376. The semiconductor layer304amay be formed by an epitaxial process. The semiconductor layer304aincludes a doped region310. The epitaxial process may include thermal decomposition of silane (SiH4) or disilane (Si2H6) to form silicon in the doped region310. Other processes to form the doped region310are within the scope of this example. The semiconductor layer304aformed by the epitaxial process may extend past the doped region310, as depicted inFIG.3D. The doped region310extends to a top surface306of the substrate302. The top surface306of this example may extend proximate to tops of the epitaxial-blocking pillars376, so that a thickness of the doped region310is less than a vertical dimension of the epitaxial-blocking pillars376.

Referring toFIG.3EandFIG.3F, the epitaxial-blocking pillars376ofFIG.3CandFIG.3Dare removed, leaving trenches324in the doped region310. The epitaxial-blocking pillars376may be removed by a wet etch process which has high selectivity to the doped region310. For example, the wet etch process may use a dilute aqueous buffered solution of hydrofluoric acid. Other processes for removing the epitaxial-blocking pillars376are within the scope of this example. The trenches324may have lateral dimensions similar to the lateral dimensions disclosed for the trenches124ofFIG.1CandFIG.1D. Each trench324of this example is equidistant from neighboring trenches324.

A trench liner layer378is formed on the doped region310, extending into the trenches324and onto the base semiconductor material374. The trench liner layer378may be formed by a thermal oxidation process, or a combination of a thermal oxidation process followed by a dielectric deposition process, such as a PECVD process.

Referring toFIG.3GandFIG.3H, an anode well314of the Schottky diode308is formed in the semiconductor material304. The anode well314contacts the doped region310. An anode contact region348is formed in the semiconductor material304at a first region316of the semiconductor material304, contacting the anode well314. Both the anode well314and the anode contact region348are p-type. The anode well314has a higher average concentration of p-type dopants than the doped region310, and the anode contact region348has a higher average concentration of p-type dopants than the anode well314.

Electrically conductive material is formed on the trench liner layer378ofFIG.3EandFIG.3F, extending into the trenches324. The electrically conductive material is removed from over the top surface306of the substrate302, leaving the electrically conductive material in the trenches324to form field plate segments340. The field plate segments340may include polysilicon, one or more metals, carbon-based material such as graphene, or an electrically conductive polymer, by way of example.

The trench liner layer378in the trenches324forms trench liners328, which separate the field plate segments340from the semiconductor material304. The trench liner layer378over the top surface306may optionally be removed, as depicted inFIG.3H. Alternatively, a portion, or all, of the trench liner layer378may be left in place over the top surface306.

A dielectric layer312is formed over the top surface306of the substrate302. The dielectric layer312may include silicon dioxide, silicon nitride, silicon oxynitride, boron nitride, aluminum oxide, polyimide, or other dielectric material. The dielectric layer312may be formed by forming a layer of dielectric material, not shown, over the top surface306, followed by patterning the layer of dielectric material to expose the field plate segments340and areas for a cathode380of the Schottky diode308.

The cathode380of the Schottky diode308is formed at the top surface306over a second region320of the semiconductor material304, proximate to the doped region310. The doped region310is between the first region316and the second region320. The cathode380may include one or more metals, such as molybdenum, platinum, chromium, or tungsten, or may include metal silicide, such as platinum silicide, or palladium silicide. Metal in the cathode380may be formed by sputtering a layer of the metal on the microelectronic device300or forming the layer of the metal by an MOCVD process, followed by patterning the layer of the metal by an etch process. Metal silicide in the cathode380may be formed by a method similar to the method disclosed for forming the metal silicide150ofFIG.1KandFIG.1L.

Referring toFIG.3IandFIG.3J, during operation of the microelectronic device300, a first operational potential is provided to the first region316. In this example, the first operational potential may be implemented as an anode bias applied to the anode contact region348. Also during operation of the microelectronic device300, a second operational potential is provided to the second region320. In this example, the second operational potential may be implemented as a cathode bias applied to the cathode380. When the Schottky diode308is in an off state, the first operational potential may be significantly lower, for example, 30 volts to 500 volts lower, than the second operational potential. When the Schottky diode308is in an on state, the first operational potential may be a few volts higher than the second operational potential.

Circuitry358is formed in the microelectronic device300. The circuitry358is configured to apply bias potentials to each of the field plate segments340. All the bias potentials are between the first operational potential and the second operational potential. The circuitry358may include an impedance ladder360with internal nodes362electrically coupled through buffers364to the field plate segments340, as indicated schematically inFIG.3IandFIG.3J. The impedance ladder360may have impedances including resistors, capacitor, inductors, or diodes between the internal nodes362. Each internal node362may be coupled to all the field plate segments340in a corresponding row326, as indicated inFIG.3I. End terminals of the impedance ladder360may be connected to the anode contact region348and the cathode380.

The bias potentials are monotonic with respect to distances of the field plate segments340from the first region316of the doped region310, as explained in reference toFIG.1KandFIG.1L. To illustrate the monotonic relationship with respect to this example, the field plate segments340include a first field plate segment340anearest the first region316, a second field plate segment340bnearest the second region320, and a third field plate segment340cbetween the first field plate segment340aand the second field plate segment340b. The circuitry358is configured to apply a first bias potential to the first field plate segment340a, apply a second bias potential to the second field plate segment340b, and apply a third bias potential to the third field plate segment340c. The first bias potential, the second bias potential, and the third bias potential are all between the first operational potential and the second operational potential. The first bias potential is between the first operational potential and the third bias potential. The second bias potential is between the third bias potential and the second operational potential. The third bias potential is between the first bias potential and the second bias potential.

Having the circuitry358configured to provide the bias potentials in the monotonic relationship with respect to distances of the field plate segments340from the first region316may accrue the advantages disclosed in reference to the MOS transistor108ofFIG.1KandFIG.1L. Having the trenches324arranged to be equidistant from neighboring trenches324may provide a more uniform electric field in the doped region310in the off state. The circuitry358is configured to adjust the bias potentials applied to the field plate segments340as the first operational potential or the second operational potential changes during operation of the Schottky diode308from the off state to the on state, and back to the off state, accruing the advantage of lower potential difference across the trench liners328, and hence higher operating potential, as explained above.

FIG.4AandFIG.4Bare charts depicting example monotonic relationships between bias potentials and distances from a first region of a doped region of an active component of a microelectronic device, as disclosed in the examples herein. The bias potentials are applied by circuitry of the microelectronic device. The first chart400ofFIG.4Aillustrates a first case in which the first operational potential is higher than the second operational potential. The first case may be encountered during operation of the MOS transistor108or the IGBT208, as disclosed herein. The vertical direction of the first chart400spans values of the bias potentials applied to field plate segments in the doped region, as disclosed in the examples herein. The bias potentials are between the first operational potential and the second operational potential.

The horizontal direction of the first chart400spans values of the distances of the field plate segments from the first region of the doped region. The distances are between zero and a length of the doped region. The length of the doped region is less than, or equal to, to a lateral distance between the first region and the second region.

Points402in the first chart400represent distances of the field plate segments from the first region and their corresponding bias potentials. The first chart400shows seven points402; other semiconductor devices may have more or fewer separate distances. Moreover, the semiconductor devices may have multiple instances of the field plate segments at each distance; each of the field plate segments at the same distance may have the same applied bias.

The bias potentials applied to the field plate segments have a monotonic relationship to the corresponding distances, that is, in the first case depicted in the first chart400, field plate segments nearer to the first region have higher bias potentials than field plate segments farther from the first region. The following relationships apply to any three field plate segments having different distances from the first region. A first point402arepresents a first field plate segment having a first distance from the first region, the first field plate segment having a first bias potential applied to it by the circuitry. A second point402brepresents a second field plate segment having a second distance from the first region that is greater than the first distance, the second field plate segment having a second bias potential applied to it by the circuitry. A third point402crepresents a third field plate segment having a third distance from the first region that is between the first distance and the second distance, the third field plate segment having a third bias potential applied to it by the circuitry. That is, the third distance is greater than the first distance and less than the second distance. In this first case, the first bias is higher than the second bias and the third bias, and the second bias is higher than the third bias. As the first operational potential or the second operational potential, or both, change during operation of the semiconductor device, the circuitry adjusts the bias potentials to maintain the monotonic relationship between the distances from the first region and the corresponding bias potentials.

The second chart404ofFIG.4Billustrates a second case in which the first operational potential is lower than the second operational potential. The second case may be encountered during operation of the Schottky diode308in an off state, as disclosed herein. The vertical direction of the second chart404spans values of the bias potentials, and the horizontal direction spans values of the distances. The bias potentials are between the first operational potential and the second operational potential. The distances are between zero and a length of the doped region. Points406in the second chart404represent distances of the field plate segments from the first region and their corresponding bias potentials.

The bias potentials applied to the field plate segments in this second case also have a monotonic relationship to the corresponding distances. In this second case, depicted in the second chart404, field plate segments nearer to the first region have lower bias potentials than field plate segments farther from the first region. The following relationships apply to any three field plate segments having different distances from the first region. A first point406arepresents a first field plate segment having a first distance from the first region, the first field plate segment having a first bias potential applied to it by the circuitry. A second point406brepresents a second field plate segment having a second distance from the first region that is greater than the first distance, the second field plate segment having a second bias potential applied to it by the circuitry. A third point406crepresents a third field plate segment having a third distance from the first region that is between the first distance and the second distance, the third field plate segment having a third bias potential applied to it by the circuitry. That is, the third distance is greater than the first distance and less than the second distance. In this second case, the first bias is lower than the second bias and the third bias, and the second bias is lower than the third bias. As the first operational potential or the second operational potential, or both, change during operation of the semiconductor device, the circuitry adjusts the bias potentials to maintain the monotonic relationship between the distances from the first region and the corresponding bias potentials.

Various features of the examples disclosed herein may be combined in other manifestations of example microelectronic devices. For example, any of the doped regions110,210, or310may be n-type or p-type. Any of the active components108,208, or308may be implemented as MOS transistors, bipolar transistors, or diodes. Any of the circuitry158,258, or358may include a resistor ladder or an impedance ladder to provide the bias potentials at the internal nodes. Any of the circuitry158,258, or358may include buffers to couple the internal nodes to the field plate segments.

While various embodiments of the present disclosure have been described above, it should be understood that they have been presented by way of example only and not limitation. Numerous changes to the disclosed embodiments can be made in accordance with the disclosure herein without departing from the spirit or scope of the disclosure. Thus, the breadth and scope of the present invention should not be limited by any of the above described embodiments. Rather, the scope of the disclosure should be defined in accordance with the following claims and their equivalents.