Patent ID: 12259353

To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized in other embodiments without specific recitation. Moreover, the description of an element in the context of one drawing is applicable to other drawings illustrating that element.

DETAILED DESCRIPTION

Disclosed herein are amplifiers suitable for biological sensing applications, such as those using nanopores. The disclosed amplifier circuits can substantially reduce amplifier input current noise. Also disclosed herein are devices, and systems, and methods of using the amplifier circuits, e.g., in biological sensing applications.

FIG.1illustrates a nanopore15with a molecule20(e.g., a single-stranded DNA (ssDNA) molecule), passing through it. Two electrodes, which are referred to herein as the sense electrode18A and the counter electrode18B, are situated near the nanopore15to, in cooperation, sense the ionic or tunnel current through (or associated with) the nanopore15. The sense electrode18A and/or counter electrode18B are typically connected to a voltage source (not illustrated), which creates a potential between the sense electrode18A and counter electrode18B.

FIG.2is a diagram of a system100for detecting molecules in accordance with some embodiments. The system100includes a nanopore unit50, a detection device120, and a processing device180. The illustrated nanopore unit50has a fluid chamber52that can be filled with an electrolyte solution containing molecules to be detected (e.g., molecule20fromFIG.1). The nanopore unit50includes a nanopore15with a hole16. The sense electrode18A and counter electrode18B are situated on either side of the nanopore15, as illustrated. As explained further below, the sense electrode18A and/or counter electrode18B may be in contact with the nanopore15or they may be separated from it.

In the diagram ofFIG.2, the detection device120comprises an amplifier130, an analog-to-digital converter140(or, more generally, a digitizer), and a voltage source150. The amplifier130may be, for example, a transimpedance amplifier that is configured to convert the detected current, Is, to a voltage, Vs. The analog-to-digital converter140is configured to digitize the output voltage, Vs, of the amplifier130and provide it to the processing device180(e.g., via an interface). The voltage source150is configured to generate a voltage of sufficient magnitude across the sense electrode18A and counter electrode18B to drive molecules within the fluid chamber52into the hole16and to allow the effect of the molecules on the current to be detected by the amplifier130. The voltage source150may be capable of providing a variable voltage level Vb across the sense electrode18A and counter electrode18B. The amplifier130may operate by, for example, detecting the resistance between the sense electrode18A and the counter electrode18B when the voltage is applied by the voltage source150.

In operation, the voltage source150generates a voltage across the sense electrode18A and counter electrode18B, which causes an ionic or tunnel current, Is, to flow between the sense electrode18A and counter electrode18B and also causes molecules in the fluid chamber52to be drawn into the hole16of the nanopore15. If the voltage across the sense electrode18A and counter electrode18B is Vb, the current Is is given by Ohm's law: Is=Vb/Rp, where Rp is the resistance through the nanopore15encountered by a molecule20as it passes through the hole16. The amplifier130converts the current Is to a voltage, Vs, which it passes to the analog-to-digital converter140. The voltage Vs is dependent on the gain of the amplifier130. The analog-to-digital converter140converts the voltage signal Vs into digital data Ds, which it passes to the processing device180, which may be situated in a different (external) physical device than the nanopore unit50and/or detection device120(e.g., the nanopore unit50and/or detection device120may be situated on/in a single integrated circuit device, and the processing device180may be in a computer or other device external to the integrated circuit device). The analog-to-digital converter140may provide the sampled signal Ds to the processing device180using any available communication path (e.g., wired or wireless) and in accordance with any suitable protocol (e.g., IEEE 802.11, Ethernet, USB, etc.).

As described further below, multiple instantiations of the nanopore unit50, the detection device120, and/or the processing device180may be included in a single physical device, or they may be separate. For example, the nanopore unit50and the detection device120may be included in a single device that is connected to the processing device180(e.g., a computer or other processor). In addition, a system may include multiple nanopores15connected to sense electrodes18A and counter electrodes18B (which may be dedicated or shared), in turn coupled to detection devices120(which may be dedicated or shared) that measure the respective currents (Is).

FIG.3Aillustrates a cross-section of an example configuration of a nanopore15and the sense electrode18A and counter electrode18B in accordance with some embodiments. The cross-section is in the x-z plane, as indicated by the axes. As illustrated in the example ofFIG.3A, the nanopore15can comprise a thin dielectric layer17with a hole16and two electrodes, namely, the sense electrode18A and counter electrode18B, attached to the sides of the nanopore15. The sense electrode18A and counter electrode18B may have thicknesses in the z-direction of, for example, around 10 nm.

FIG.3Billustrates a cross-section of an alternative example configuration of a nanopore15and the sense electrode18A and counter electrode18B in accordance with some embodiments. As illustrated inFIG.3B, the sense electrode18A and counter electrode18B can be electrochemical electrodes, e.g. silver/silver-chloride pairs.

With either of the sense electrode18A and counter electrode18B embodiments illustrated inFIGS.3A and3B, the thin dielectric layer17of the nanopore15is very thin (e.g., in the nm range) to create a nanopore15with a suitable aspect ratio so that molecules passing through the hole16will cause measurable disturbances in the current. As a result, the capacitance between the sense electrode18A and counter electrode18B, which is inversely proportional to the thickness of the thin dielectric layer17, is naturally very large. This capacitance can amplify the noise of the applied voltage Vb by forming a pole with the output impedance of the amplifier130. It can also cause the detection device120to have an unstable dynamic response at higher frequencies. This instability can reduce the usefulness of the system100by preventing it from being able to detect rapid changes in the current as molecules pass through the nanopore15at the applied voltage Vb. Specifically, the capacitance amplifies the noise voltage, particularly at higher frequencies. The amplified noise limits the frequency at which the nanopore15can read or detect molecules passing through its hole16.

The capacitance of the nanopore15can be modeled as the parallel-plate capacitance of the constituent elements of the nanopore unit50.FIG.4is a conceptual illustration of the system100ofFIG.2representing the capacitance between the sense electrode18A and the counter electrode18B as a capacitor. As illustrated inFIG.4, the capacitance can be considered as a parasitic capacitance19between the sense electrode18A and counter electrode18B. The parasitic capacitance19acts as a charge sink for the sense electrode18A and can create a peak in the noise spectrum. For example, if a potential difference ΔU is created between the sense electrode18A and counter electrode18B, a charge Q=ΔU*C flows into the parasitic capacitance19, which reduces the signal (e.g., the current Is) that is sensed by the amplifier130and, correspondingly, reduces the SNR of the measurement.

Prior approaches to improving the SNR have included reducing the capacitance of the nanopore15by modifying its physical layout, reducing the bandwidth of the amplifier130, and reducing the translocation speed of the molecules passing through the nanopore15. All of these approaches have drawbacks. For example, changes to the physical layout are limited by manufacturability, and reduced amplifier130bandwidth and/or translocation speed of molecules through the nanopore15reduces the rate at which molecules can be read. Therefore, there remains a need for additional solutions.

Disclosed herein are devices, systems, and methods that can improve the SNR of nanopore15measurements by mitigating the effect of the parasitic capacitance19. In some embodiments, an amplifier circuit that comprises a three-terminal device (e.g., at least one transistor) is situated in a configuration that allows the circuit to read the nanopore15(e.g., detect the current Is) while providing feedback to the sense electrode18A to reduce the parasitic capacitance19between the sense electrode18A and the counter electrode18B. The amplifier circuit may include, for example, a bi-polar junction transistor (BJT) situated in a common-base amplifier configuration. In some embodiments, the amplifier circuit includes a voltage-controlled current source or an integrated amplifier that uses the so-called “diamond” topology. The disclosed amplifier circuits both amplify the current from the sense electrode18A and inject a charge into the sense electrode18A to cancel at least part of the parasitic capacitance19to mitigate charge being diverted to the parasitic capacitance19.

Referring again toFIG.4, if the amplifier130is an inverting amplifier, the parasitic capacitance between the input and output of the amplifier130will appear to be multiplied by the gain of the amplifier. The additional amount of capacitance is known as Miller capacitance, and the apparent increase in input capacitance is known as the Miller effect. The Miller effect limits the bandwidth of the amplifier130. Furthermore, the parasitic capacitance19between the sense electrode18A and the counter electrode18B will reduce the phase margin for stability of the detection device120and introduce noise gain at frequencies interfering with the response of the nanopore15to molecules. Both of these phenomena can limit the capabilities and/or effectiveness of the detection device120.

The inventor of the techniques disclosed herein had the insight that the input noise effect can be avoided by an amplifier circuit that uses a three-terminal device, such as a BJT, a diamond transistor, or a similar device in a common-base configuration to provide wide bandwidth with reduced noise gain while reducing the parasitic capacitance19at the input. A common-base configuration is not subject to the Miller effect.

FIG.5Ais a diagram illustrating an example system200in accordance with some embodiments. As shown inFIG.5A, the current detected by the sense electrode18A is measured by the amplifier circuit160. The amplifier circuit160is coupled to and provides an output to the analog-to-digital converter140. The analog-to-digital converter140is coupled to a processing device180and provides a digitized version of the read signal to the processing device180.

One objective of the amplifier circuit160is to suppress the effects of the parasitic capacitance19. Generally speaking, the amplifier circuit160includes a three-terminal device, examples of which are described further below in the context ofFIGS.5B,5C, and5D. A first terminal of the three-terminal device is a low-impedance terminal that is coupled to the sense electrode18A, a second terminal of the three-terminal device is a high-impedance terminal that is coupled to a bias voltage source, and a third terminal of the three-terminal device is a high-impedance terminal that provides the output of the amplifier circuit160. As used herein, the term “low-impedance” is used relative to and in contradistinction to the term “high-impedance.” The impedance of a low-impedance terminal of a three-terminal device is lower than the impedance of a high-impedance terminal of a three-terminal device. Depending on the three-terminal device, the impedance of a low-impedance terminal may be, for example, on the order of a few Ohms to about 1 kΩ, and the impedance of a high-impedance terminal may be, for example, on the order of a few kΩ to GΩ. The sense electrode18A detects a current of the nanopore15and provides it to the first terminal of the three-terminal device. The third terminal of the three-terminal device provides an amplified signal that represents the detected current to a downstream component (e.g., a digitizer (e.g., an analog-to-digital converter), a processor, etc.).

FIG.5Bis an example of a circuit161that can be used as the amplifier circuit160inFIG.5A. The circuit161includes a BJT170A with its emitter coupled to a current source155and the sense electrode18A, its base coupled to a bias voltage, Vbias, and its collector coupled to Vcc through a resistor Rc and providing the output of the circuit161. The circuit161is in a common-base (CB) amplifier configuration that provides a high-bandwidth current buffer with a low input impedance and a small feedback capacitance that does not suffer from the Miller effect.

A significant aspect of the circuit161is that the base is not grounded, but rather is connected to a bias voltage. With the circuit161as illustrated, the bias voltage biases the nanopore15. Because the base of the BJT170A is held at a constant bias voltage, Vbias, it shields the collector signal from being fed back to the emitter input. Thus, the circuit161provides a better high frequency response than other types of amplifier circuits that could be used in nanopore15applications.

In operation, whenever the current Is from the nanopore15is less than the current Ibias, the emitter current is positive, and the BJT170A is in forward-active mode. As long as a sufficient bias voltage Vbias is applied (e.g., around 0.7 V for common types of BJTs), the voltage on the sense electrode18A will be held close to 0 V as a result of the high forward transconductance of the BJT170A. As a result, for both positive or negative voltages applied to the sense electrode18A, the circuit161effectively presents a low impedance to ground as long as the sensed current Is is less than the bias current Ibias. The parasitic capacitance19is then divided by the transconductance of the circuit161, thereby reducing the noise in reading the current Is from the nanopore15.

In some embodiments, the bias voltage Vbias is selected so that the current Is is close to zero for an input voltage of close to zero. Using an approximate Ebers-Moll model of the BJT170A, the bias voltage is

-n⁢VT⁢log⁢(I⁢biasI⁢sat+1),
where Isat is the saturation current of the base-emitter junction, VT, which is approximately 26 mV, is the thermal voltage, and n is the diode ideality factor. The output of the circuit161then provides an amplified voltage signal Vs that is linearly related to the input current Is:

Is=I⁢bias-(1+ββ)⁢(V⁢cc-V⁢sRC)
where β is the forward common-emitter current gain of the BJT170A.

As will be appreciated by those having ordinary skill in the art, packaged discrete BJTs for radio-frequency applications are available with very low parasitic capacitance, making them a good choice for the BJT170A of the circuit161.

In some embodiments, however, the BJT170A is directly integrated onto the nanopore15substrate to mitigate the need for wiring and thereby reduce the input capacitance. As will be appreciated by those having ordinary skill in the art, BJTs are available in integrated processes, such as BiCMOS processes.

It is to be appreciated that the circuit161can alternatively be implemented using a common gate amplifier in pure CMOS. Such an implementation might have inferior input capacitance suppression, however, because a MOSFET generally has inferior transconductance.

In some embodiments, the amplifier circuit160uses a voltage-controlled current source or an integrated amplifier that uses a diamond topology. For example, the amplifier circuit160can include a diamond transistor, which may also be referred to as an operational transconductance amplifier, a voltage-controlled current source, a transconductor, a macro transistor, or a second-generation current conveyor (CCII+). The diamond transistor is a DC-coupled structure that acts as an ideal transistor and does not require biasing circuits or an external offset voltage compensation network. A diamond transistor, which provides high gain, can be used similarly to a CB amplifier.

FIG.5Cillustrates an example of a diamond transistor170B that can be used in accordance with some embodiments. As shown inFIG.5C, the diamond transistor170B has three terminals, labeled as B, E, and C. The B terminal is a high-impedance terminal, the E terminal is a low-impedance terminal, and the C terminal is a high-impedance output current source terminal. One difference between the diamond transistor170B and other transistors (e.g., the BJT170A) is that the current flows out of the C terminal when the B-to-E input voltage is positive, and into the C terminal when the B-to-E input voltage is negative. The diamond transistor170B is self-biased and, because the transconductance is constant over a wide range of collector currents, more linear than an ordinary transistor.

FIG.5Dillustrates an example of a circuit162that includes a diamond transistor170B in accordance with some embodiments. The circuit162can be used as the amplifier circuit160in the configuration shown inFIG.5A. InFIG.5D, the diamond transistor170B is used similarly to a CB amplifier. The E terminal of the diamond transistor170B is coupled to the sense electrode18A and to a current source155, the B terminal is coupled to the bias voltage Vbias, and the C terminal is coupled to Vcc. Although not illustrated, the circuit162can include a resistance between the E terminal of the diamond transistor170B and the nanopore15.

A significant aspect of the circuit162is that the B terminal of the diamond transistor170B is not grounded, but rather is connected to a bias voltage. With the circuit162as illustrated, the bias voltage biases the nanopore15. (It is to be appreciated that the bias voltage Vbias can be any value, including zero.)

One benefit of the circuit162is that it is truly bipolar, which can be especially advantageous if the translocation of a molecule being sensed by the nanopore15is to be reversed. For example, if the nanopore15is included in a data storage device, and data is stored in molecules, those molecules can be read whether they pass through the nanopore15in the forward or reverse direction.

In some embodiments, the diamond transistor170B is directly integrated onto the nanopore15substrate to mitigate the need for wiring and thereby reduce the input capacitance. In some embodiments, the diamond transistor170B is provided as a separate component that is coupled to the nanopore15(e.g., via wiring).

Both of the circuit161and circuit162provide advantages as the amplifier circuit160. Both the circuit161and circuit162allow the nanopore15to be read while reducing the effect of the parasitic capacitance19between the sense electrode18A and counter electrode18B. In essence, the circuit161and circuit162provide amplification while providing feedback on the sense electrode18A to at least partially cancel the parasitic capacitance19.

Those having ordinary skill in the art will appreciate that the circuit161and circuit162can include components that are not specifically illustrated (e.g., resistors, etc.). As will be appreciated, these components can be added to improve stability.

It will be appreciated that the bias voltage, Vbias, for the three-terminal device of the amplifier circuit160(e.g., the BJT170A or the diamond transistor170B) is separate from the voltage source150that biases the nanopore15. One or both of Vbias and the voltage applied by the voltage source150may be adjustable.

It will also be appreciated that the nanopore15likely produces too little current (i.e., the amplitude of Is is too low) to cause the BJT170A or diamond transistor170B in the circuit161and circuit162to operate in a region in which they have high gain. Accordingly, it will be appreciated that the BJT170A, diamond transistor170B may be biased (e.g., by the current source155providing, e.g., 50-100 μA) so that they operate in a region in which they have sufficiently high gain.

In the example system200shown inFIG.5A, the amplifier circuit160is connected to a single nanopore units50. In some embodiments, the amplifier circuit160is used to read multiple nanopores15.FIG.6illustrates an example of a system201that includes an amplifier circuit160that can read multiple nanopore15in accordance with some embodiments. The amplifier circuit160may be, for example, the circuit161or the circuit162described above. In the illustrated example, the system201comprises an array110of nanopore units50. InFIG.6, the array110is shown as including at least the nanopore unit50A, the nanopore unit50B, the nanopore unit50C, the nanopore unit50D, the nanopore unit50E, the nanopore unit50F, and the nanopore unit50N, but it is to be appreciated that the array110can include fewer or more nanopore units50than shown. Moreover, the use of the letter “N” in the last illustrated nanopore unit50is not intended to suggest that the array110of the system201includes any particular number of nanopore units50. In general, the array110can include any number of nanopore units50(e.g., one or more).

In some embodiments, some or all of the nanopore units50of the array110share a counter electrode18B but each nanopore15has its own sense electrode18A with an individualize voltage. Such a configuration may be particularly advantageous from a manufacturing standpoint. For example, a continuous metal electrode on the back of a wafer could serve as a common counter electrode18B for some or all of the nanopore units50. This type of implementation would not require the back side of the wafer to be patterned, nor would it require a large number of wires to be brought from the back side of the wafer to the front side, which can be complicated.

The array110is coupled to a multiplexer220. As shown inFIG.6, the multiplexer220has a plurality of inputs, each corresponding to a respective one of the nanopore units50in the array110, and a single output. The multiplexer220may be, for example, configured to cycle through individual nanopore units50of the array110to read the nanopores15in a systematic way (e.g., periodically, in accordance with a clock signal, in response to an instruction from the control logic230discussed below, etc.). Alternatively or in addition, the multiplexer220may be configured to select any one nanopore unit50in the array110at any time (e.g., when desirable or necessary) and to read its nanopore15(e.g., provide a signal representing its current to the amplifier circuit160). Accordingly, as illustrated inFIG.6, in the system201, a plurality (some or all) of the nanopore units50in the array110are coupled to the multiplexer220and are selectable by the multiplexer220.

As shown in the example ofFIG.6, the multiplexer220is coupled to and provides a signal corresponding to a selected nanopore unit50to the amplifier circuit160. Referring back toFIG.5A, the multiplexer220may provide the current Is corresponding to the selected nanopore15to the amplifier circuit160. As explained above in the discussion ofFIGS.5A-5D, the amplifier circuit160comprises a three-terminal device. In the system201shown inFIG.6, the first terminal of the three-terminal device is coupled to the multiplexer220output, the second terminal of the three-terminal device is coupled to a bias voltage source (to produce Vbias), and the third terminal of the three-terminal device is the output of the amplifier circuit160.

As illustrated inFIG.6, the amplifier circuit160of the system201provides an output signal (e.g., Vs ofFIG.5A) to the analog-to-digital converter140(or, generally, a digitizer). The analog-to-digital converter140is coupled to, and can provide signals to and receive signals from, control logic230. As will be appreciated by those having ordinary skill in the art, the control logic230may be implemented in any suitable way (e.g., a processor, an application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), etc.). In the example system201, the control logic230is coupled to memory250and to an interface240. The memory may be on-board (e.g., on an integrated circuit chip that includes some or all components of the system201, etc.), or it may be external memory. The interface240may couple the system201to a processing device (e.g., the processing device180shown inFIG.5A).

As shown inFIG.6, the control logic230is coupled to memory250, which may be on-chip or off-chip memory. Memory250may store information (e.g., computer-readable instructions) that can be used to read the nanopores15and/or to store read results.

The control logic230is also coupled to and configured to provide signals/instructions to the drive circuitry270. The drive circuitry270is coupled to the array110and, as its name suggests, is the driver for at least one nanopore unit50of the array110. For example, the drive circuitry270may include the voltage source150illustrated inFIG.5A. The drive circuitry270is the power supply that biases the array110, and it includes at least one drive circuit coupled to at least one nanopore unit50.

The control logic230is also coupled to and configured to provide signals/instructions to the multiplexer220. For example, the control logic230can provide a signal to cause the multiplexer220to cycle through the connected nanopore units50to allow the nanopore15currents to be read/measured. Alternatively or in addition, the control logic230can select a particular nanopore unit50connected to the multiplexer220by providing a signal to the multiplexer220.

It is to be appreciated that the control logic230, memory250, and interface240are illustrated inFIG.6as external to the system201, but this demarcation is solely for convenience of description. For example,FIG.7, described below, includes multiple instantiations of the components of the system201shown inFIG.6, as well as control logic and an interface. It is to be appreciated that the system201can include components or elements not illustrated inFIG.6as being part of the system201. For example, the system201can include control logic230, an interface240, and/or memory250.

FIG.7illustrates another example of a system202in accordance with some embodiments. As illustrated, the system202includes one or more of the system201described above, thereby making the systems201subsystems of the system202. In the example shown inFIG.7, the system202includes a plurality of systems201as subsystems.FIG.7illustrates and labels the subsystem201A, the subsystem201B, the subsystem201C, and the subsystem201M, but it is to be appreciated that the system202can include any number of systems201as subsystems. Moreover, the use of the letter “M” in the last illustrated system201is not intended to suggest that the system202includes any particular number of instances of systems201as subsystems.

As described in the context ofFIG.6, multiple nanopore units50of each of the system201can share a counter electrode18B. Furthermore, multiple systems201can share a counter electrode18B. Thus, for example, some or all of the nanopore units50in subsystem201A can share a counter electrode18B with some or all of the nanopore units50in one or more of subsystem201B, subsystem201C, subsystem201M, and/or any other subsystem in the system202.

The subsystem201A, subsystem201B, subsystem201C, . . . , subsystem201M (collectively referred to as the “subsystems201x”) ofFIG.7are coupled to a bus215. The bus215may be any suitable wired or wireless communication channel that allows the subsystems201xin the system202to communicate with the control logic280. The control logic280is configured to provide instructions/commands to and receive information/data from the subsystems201x. The control logic280may be configured to perform the functions of the control logic230shown inFIG.6, but for all of the subsystems201xof the system202. The control logic280is also coupled to an interface290, which is configured to provide information to and obtain information from the control logic280. The interface290may be any suitable interface and may communicate, wirelessly and/or via a wired communication path, with downstream components (e.g., processor, memory) using any suitable protocol. For example, it may provide communication via Wi-Fi, Ethernet, USB, etc. The interface290may be configured to perform the functions of the interface240shown inFIG.6. The system202may also include memory (not illustrated), which may serve the same purpose(s) as described above for the memory250ofFIG.6.

FIG.8illustrates an example of a system203in accordance with some embodiments. The system203may be an implementation of the system202shown inFIG.7. The system203may be, for example, implemented as an integrated circuit chip that allows molecules to be detected.FIG.8is a diagram showing a plan view (e.g., in an x-y plane perpendicular to the x-z plane shown inFIG.1and others herein) of the system203. As shown, the system203includes a plurality of nanopore units50. To avoid obscuring the drawing, only four nanopore units50are labeled: nanopore unit50A, nanopore unit50B, nanopore unit50C, and nanopore unit50D.

As explained in the discussion ofFIG.6, the nanopore units50are coupled to multiplexers220. InFIG.8, respective pluralities (subsets) of the nanopore units50are coupled to the multiplexer220A, multiplexer220B, and multiplexer220C. Coupled to each of the multiplexers220(e.g., as illustrated inFIG.6) is a respective a respective amplifier circuit160and a respective analog-to-digital converter140. Specifically, multiplexer220A is coupled to amplifier circuit160A and analog-to-digital converter140A; multiplexer220B is coupled to amplifier circuit160B and analog-to-digital converter140B; and multiplexer220C is coupled to amplifier circuit160C and analog-to-digital converter140C. The system203also includes drive circuitry270, an interface290, control logic280, and memory250. These components were described above in the discussion ofFIGS.7and/or8. That discussion applies here and is not repeated.

As described above in the context ofFIG.6andFIG.7, some or all of the nanopore units50can share a counter electrode18B. In the plan view ofFIG.8, a common counter electrode18B may be situated, for example, on the bottom of a wafer so that the back side of the wafer does not need to be patterned.

In the foregoing description and in the accompanying drawings, specific terminology has been set forth to provide a thorough understanding of the disclosed embodiments. In some instances, the terminology or drawings may imply specific details that are not required to practice the invention.

The term “diamond transistor” is used herein to describe a device that approximates ideal transistor behavior, at least under some conditions. As explained above, other names for the diamond transistor include operational transconductance amplifier, voltage-controlled current source, transconductor, macro transistor, and second-generation current conveyor (CCII+). The use of a diamond transistor in the examples is not meant to be limiting. Other structures that perform similarly or identically to a diamond transistor are also suitable, regardless of what they are called.

To avoid obscuring the present disclosure unnecessarily, well-known components are shown in block diagram form and/or are not discussed in detail or, in some cases, at all.

Unless otherwise specifically defined herein, all terms are to be given their broadest possible interpretation, including meanings implied from the specification and drawings and meanings understood by those skilled in the art and/or as defined in dictionaries, treatises, etc. As set forth explicitly herein, some terms may not comport with their ordinary or customary meanings.

As used in the specification and the appended claims, the singular forms “a,” “an” and “the” do not exclude plural referents unless otherwise specified. The word “or” is to be interpreted as inclusive unless otherwise specified. Thus, the phrase “A or B” is to be interpreted as meaning all of the following: “both A and B,” “A but not B,” and “B but not A.” Any use of “and/or” herein does not mean that the word “or” alone connotes exclusivity.

As used in the specification and the appended claims, phrases of the form “at least one of A, B, and C,” “at least one of A, B, or C,” “one or more of A, B, or C,” and “one or more of A, B, and C” are interchangeable, and each encompasses all of the following meanings: “A only,” “B only,” “C only,” “A and B but not C,” “A and C but not B,” “B and C but not A,” and “all of A, B, and C.”

To the extent that the terms “include(s),” “having,” “has,” “with,” and variants thereof are used in the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term “comprising,” i.e., meaning “including but not limited to.”

The terms “exemplary” and “embodiment” are used to express examples, not preferences or requirements.

The term “coupled” is used herein to express a direct connection/attachment as well as a connection/attachment through one or more intervening elements or structures.

The terms “over,” “under,” “between,” and “on” are used herein refer to a relative position of one feature with respect to other features. For example, one feature disposed “over” or “under” another feature may be directly in contact with the other feature or may have intervening material. Moreover, one feature disposed “between” two features may be directly in contact with the two features or may have one or more intervening features or materials. In contrast, a first feature “on” a second feature is in contact with that second feature.

The term “substantially” is used to describe a structure, configuration, dimension, etc. that is largely or nearly as stated, but, due to manufacturing tolerances and the like, may in practice result in a situation in which the structure, configuration, dimension, etc. is not always or necessarily precisely as stated. For example, describing two lengths as “substantially equal” means that the two lengths are the same for all practical purposes, but they may not (and need not) be precisely equal at sufficiently small scales. As an example, a structure that is “substantially vertical” would be considered to be vertical for all practical purposes, even if it is not precisely at 90 degrees relative to horizontal.

The drawings are not necessarily to scale, and the dimensions, shapes, and sizes of the features may differ substantially from how they are depicted in the drawings.

Although specific embodiments have been disclosed, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the disclosure. For example, features or aspects of any of the embodiments may be applied, at least where practicable, in combination with any other of the embodiments or in place of counterpart features or aspects thereof. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.