Patent ID: 12199048

EMBODIMENTS OF THE PRESENT DISCLOSURE

Described herein are multi-chip packaging architectures with a heterogeneous nested interposer package and methods of forming such electronic packages, in accordance with various embodiments. In the following description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present invention, however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

As noted above, current packaging solutions are beginning to use multi-die architectures. However, the inclusion of multiple dies in a single package is not without issue. In addition to the larger footprint of existing multi-die architectures, such systems also suffer from poor yield and reliability. Particularly, the interconnections between dies is difficult due to warpage and other alignment issues when using traditional packaging substrates. Accordingly, embodiments disclosed herein include electronic packages that utilize heterogeneous nested interposers.

Heterogeneous nested interposers, such as those described herein, include an interposer with one or more cavities. Nested components may be positioned in the cavities. One or more dies may be connected to the interposer and the nested components with interconnects. In an embodiment, the interconnects include a bump pad that interfaces with bumps (e.g., solder bumps) above and below. The use of a bump pad allows for self-aligning between the interposer or nested components and the die. Accordingly, embodiments allow for high yields and reliability, even when fine pitched interconnects are used (e.g., when the nested component is a bridge between two dies).

Referring now toFIG.1A, a cross-sectional illustration of an electronic package100is shown, in accordance with an embodiment. In an embodiment, the electronic package100may comprise an interposer130and a nested component140. The nested component140is positioned within a cavity135that passes through the interposer130. The nested component140is referred to as being “nested” because the component140is placed into the cavity135. That is, the nested component140is surrounded by portions of the interposer130. In the illustrated embodiment, a single cavity135is shown in the interposer130. However, it is to be appreciated that any number of cavities135may be used, depending on the device. Examples of multiple cavities135are provided below in greater detail. In the illustrated embodiment, a single nested component140in the cavity135is shown. However, it is to be appreciated that any number of nested components140may be positioned in a single cavity135. Examples of multiple nested components140in a single cavity135is provided below in greater detail.

In an embodiment, the interposer130may be any suitable substrate material. For example, the interposer130may comprise glass, ceramic, semiconductor materials (e.g., high or low resistivity silicon, III-V semiconductors, or the like), organic substrates (high density interconnect (HDI) substrates, embedded trace substrates (ETS), high density package (HDP) substrates, molded substrates, or the like). In some embodiments, the interposer130is a passive device. That is, the interposer130may include only passive components (e.g., traces, vias, etc.). For example, the interposer130may comprise vias134that provide connections between pads133below the interposer130and pads136above the interposer130. In other embodiments, the interposer130may be an active interposer. That is, the interposer130may comprise active devices (e.g., transistors etc.).

In an embodiment, the nested component140may be an active or passive component. For example, an active nested component140may comprise logic devices, analog/RF devices, I/O circuits, memory devices, voltage regulators, sensors, or the like. Passive nested components140may comprise high density multi-die interconnect bridge dies, capacitors, inductors, resistors, thermo-electric coolers, high speed connectors, or the like. In the illustrated embodiment, the nested component140comprises an active surface141. While referred to as an “active” surface141, it is to be appreciated that the active surface141may comprise entirely passive features. In an embodiment, the nested component140may comprise through component vias (TCVs)144. The TCVs144may electrically couple the active surface141to pads143on the backside of the nested component140.

In an embodiment, the interposer130and the nested component140may be embedded by an underfill material131and/or a mold layer132. In an embodiment, pads133of the interposer130and pads143of the nested component140may be contacted by bumps137positioned in openings through a portion of the mold layer132. In an embodiment, the bumps137may be referred to as “package side bumps” (PSBs). The PSBs may interface with a package substrate (not shown).

In an embodiment, the electronic package100may further comprise one or more dies120embedded in a mold layer122. In an embodiment, the active surfaces121of the dies120may be electrically coupled to the interposer130and the nested component140. For example, interconnects181provide electrical connections between the die120and the interposer130, and interconnects182provide electrical connections between the die120and the nested component140. In an embodiment, the interconnects181may have a different pitch than the interconnects182. For example, the interconnects182may have a smaller pitch than the interconnects181. In the illustrated embodiment, the nested component140is a bridge that provides an electrical connection between the two dies120.

Referring now toFIG.1B, a zoomed in portion180of the electronic package100is shown, in accordance with an embodiment. Portion180illustrates more clearly the architecture of the interconnects181and182. As shown, the interconnects181and182are substantially similar to each other, with the exception that the widths of the interconnects182are smaller than the width of interconnects181. In an embodiment, the interconnects comprise a bump pad184. The bump pad184may be a conductive material, such as copper. Bumps183may be positioned over the bump pad184, and bumps185may be positioned below the bump pad184. The bumps183,185may be solder bumps or the like. In an embodiment, the bumps183may interface with pads123of the die120. The bumps185may interface with pads136of the interposer130or with pads146of the nested component140.

The use of a bump pad184improves alignment between the dies120and the interposer130and between the dies120and the nested component140. This is because the die120is self-aligned to the bump pads184by solder bumps183, and the interposer130and the nested component140are self-aligned to the bump pads184by solder bumps185. That is, the bump pads184provide locations to which all of the components are self-aligned. Since the dies120, the interposer130, and the nested component140are self-aligned to the same features, the dies120are precisely aligned to the interposer130and the nested component140.

Referring now toFIG.2A, a cross-sectional illustration of an electronic package200is shown, in accordance with an additional embodiment. In an embodiment, the electronic package200may be substantially similar to the electronic package100inFIG.1A, with the exception that a plurality of nested components240are provided in the interposer230. As shown, a first nested component240Ais positioned in a first cavity235Ain the interposer230and a second nested component240Bis positioned in a second cavity235B. In an embodiment, the first cavity235Amay span between two dies220. That is, the first cavity may be partially within a footprint of both dies220. Accordingly, the first nested component240Amay be accessible by both dies220. For example, the first nested component240Amay be a bridge that electrically couples the dies220together. In an embodiment, the second cavity235Bmay be entirely within a footprint of one of the dies220. In such embodiments, the second nested component240Bmay be accessible to only one of the dies220.

Referring now toFIG.2B, a cross-sectional illustration of an electronic package200is shown, in accordance with an additional embodiment. In an embodiment, the electronic package200inFIG.2Bmay be substantially similar to the electronic package200inFIG.2A, with the exception that the first nested component240Adoes not include TCVs244. In some embodiments, the first nested component240Amay comprise dummy balls237′. That is, in some embodiments the dummy balls237′ may not be electrically connected to circuitry of the package200and serve as mechanical supports only, whereas balls237provide mechanical support and are electrically connected to circuitry of the package200. In such an embodiment, the nested component240Amay source power or signals from the package substrate (not shown) indirectly through the dies220via the top-side of the nested component240A.

Referring now toFIG.2C, a cross-sectional illustration of an electronic package200is shown, in accordance with an embodiment. In an embodiment, the electronic package200inFIG.2Cmay be substantially similar to the electronic package200inFIG.2A, with the exception that the second nested component240Bis facing a different direction. For example, the second nested component240Bmay have an active surface241that is facing away from the die220.

Referring now toFIG.2D, a cross-sectional illustration of an electronic package200is shown, in accordance with an additional embodiment. In an embodiment, the electronic package200inFIG.2Cmay be substantially similar to the electronic package200inFIG.2A, with the exception that a stack of second nested components240Bis positioned in the second cavity235B. In an embodiment, the stack of second nested components240Bmay comprise a stack of memory dies or any other stackable components.

Referring now toFIG.2E, a cross-sectional illustration of an electronic package200is shown, in accordance with an embodiment. In an embodiment, the electronic package200may comprise an interposer230, a nested component240in a cavity235in the interposer230, and one or more dies220attached to the nested component240and the interposer230. In an embodiment, the nested component240and/or the interposer230may comprise one or more redistribution layers251,252. For example, a redistribution layer251may be above the nested component240and the interposer230(i.e., facing the dies220) and a redistribution layer252may be below the nested component240and the interposer230. While the redistribution layers251,252are shown on both the nested component240and the interposer230, it is to be appreciated that in some embodiments, the redistribution layers251,252may only be on one of the nested component240and the interposer230. Additionally, while the redistribution layers251,252are shown on both the top and bottom surfaces of the nested component240and the interposer230, it is to be appreciated that in some embodiments, the redistribution layer251or252may be only on one surface of the nested component240and/or the interposer230.

Referring now toFIG.2F, a cross-sectional illustration of an electronic package200is shown, in accordance with an additional embodiment. In an embodiment, the electronic package200may be substantially similar to the electronic package200inFIG.2E, with the exception that the redistribution layers253and254are positioned in different locations. For example, a redistribution layer253may be located between the bumps285and the bumps283and/or a redistribution layer254may be located below the pads233of the interposer230and the pads243of the nested component240. In the case where a redistribution layer253is located between bumps285and283, it is to be appreciated that the bump pad may be integrated into the redistribution layer254. While a redistribution layer253and254is shown in both locations inFIG.2F, it is to be appreciated that only one redistribution layer253or254may be used in some embodiments. InFIGS.2E and2F, various redistribution layers251-254are shown. However, it is to be appreciated that embodiments may include any number or combination of redistribution layers251-254or redistribution layers in other locations not illustrated inFIG.2E or2F.

Referring now toFIG.3A, a plan view illustration of an electronic package300is shown, in accordance with an embodiment. In an embodiment, the electronic package300comprises an interposer330with a plurality of cavities335A-E. In an embodiment, a plurality of nested components340are positioned in the cavities335. In some embodiments, at least one of the cavities335comprises a plurality of nested components340. For example, two nested components340are positioned in cavity335B. In an embodiment, the cavities335may be entirely within a footprint of a die320(indicated by dashed lines), within the footprint of more than one die320, and/or partially within the footprint of a single die320. For example, cavities335Aand335Bare entirely within a footprint of die320A, cavity335Cis within the footprint of die320Aand320B, cavity335Eis within the footprint of die320Aand320C, and cavity335Dis partially within the footprint of die320B.

Referring now toFIG.3B, a cross-sectional schematic illustration of the electronic package300inFIG.3Aalong line B-B′ is shown, in accordance with an embodiment. In the illustrated embodiment, the interposer330is shown with nested components340within cavities335A,335C, and335D. The interposer330and the nested components340may be electrically coupled to the dies320Aand320Bby interconnects that comprise a layer of bump pads384. The bump pads384are shown schematically between the dies320A,320Band the interposer330and the nested components340for simplicity. However, it is to be appreciated that the bump pads384may be part of an interconnect substantially similar to the interconnects181and182described above with respect toFIG.1B. In an embodiment, the bottom surfaces of the interposer330and the nested components340may be electrically coupled to package side bumps337.

Referring now toFIG.3C, a cross-sectional schematic illustration of the electronic package300inFIG.3Aalong line C-C′ is shown, in accordance with an embodiment. In the illustrated embodiment, the interposer330is shown with nested components340within cavities335Band335E. The interposer330and the nested components340may be electrically coupled to the dies320Aand320Bby interconnects that comprise a layer of bump pads384. The bump pads384are shown schematically between the dies320A,320Band the interposer330and the nested components340for simplicity. However, it is to be appreciated that the bump pads384may be part of an interconnect substantially similar to the interconnects181and182described above with respect toFIG.1B. In an embodiment, the bottom surfaces of the interposer330and the nested components340may be electrically coupled to package side bumps337.

Referring now toFIG.4, a plan view illustration of an electronic package400is shown, in accordance with an embodiment. In an embodiment, the electronic package400may comprise a plurality of interposers430A-D. Each interposer430may be any shape. For example, the interposers430are illustrated as being rectilinear. The interposers430may be arranged so that sidewalls of the interposers430define a cavity435. In an embodiment, one or more nested components440may be positioned in the cavity435. In an embodiment, one or more dies420(indicated with dashed lines) may be provided above the interposers430and the nested components440. Each of the dies420may extend over one or more of interposers430.

In an embodiment, each of the interposers430may be substantially similar to each other. For example, each of the interposers430may be passive interposers430or active interposers430. In other embodiments, the interposers430may not all be the same. For example, one or more of the interposers430may be an active interposer430and one or more of the interposers430may be passive interposers.

Referring now toFIGS.5A-5M, a series of cross-sectional illustrations depicting a process for forming an electronic package with a heterogeneous nested interposer is shown, in accordance with an embodiment.

Referring now toFIG.5A, a cross-sectional illustration of a first carrier591with bumps585is shown, in accordance with an embodiment. In an embodiment, the first carrier591may be any suitable carrier substrate, such as glass or the like. In an embodiment, a conductive layer512may be adhered to the first carrier591with an adhesive511. A plurality of bump pads584may be formed over the conductive layer512. For example, the bump pads584may be formed with a lithographically defined resist layer (not shown) and a plating process (e.g., electroplating). Accordingly, the alignment of bump pads584relative to each other will be excellent since they are formed with a single patterning process. In an embodiment, the bump pads584may include bump pads584of different sizes in order to accommodate different features. For example, larger bump pads584may accommodate the interposer and smaller bump pads584may accommodate the nested components. In an embodiment, a bump585may be disposed over the top surfaces of each of the bump pads584. For example, the bumps585may be solder bumps or the like.

Referring now toFIG.5B, a cross-sectional illustration after the interposer530and the nested component540is attached to the bump pads584is shown, in accordance with an embodiment. In an embodiment, the interposer530may comprise vias534that connect pads533on a first surface of the interposer530to pads536on a second surface of the interposer530. In an embodiment, the nested component540may be positioned within a cavity535of the interposer. In an embodiment, the nested component540may have an active surface541and through component vias544. In the illustrated embodiment, the active surface541is facing the first carrier591. However, it is to be appreciate that in other embodiments, the active surface541may be facing away from the first carrier591. In other embodiments, the nested component540may not have through component vias544. The nested component may have pads543on a first surface and pads546on a second surface.

In an embodiment, the pads546of the nested component540and the pads536of the interposer530may be electrically coupled to the bump pads584. Since the pads546and536are coupled to the bump pads584by bumps585, they are self-aligned to the bump pads584. Accordingly, the alignment between the nested component540and the interposer530have excellent alignment with each other. In an embodiment, the nested component540may be attached first followed by attaching the interposer530, or the interposer530may be attached first followed by attaching the nested component540.

In the illustrated embodiment, a single interposer530and nested component540are shown on the first carrier591. However, it is to be appreciated that the first carrier591may be a panel level, sub-panel level, wafer-level, etc. carrier on which a plurality of electronic packages are fabricated substantially in parallel.

Referring now toFIG.5C, a cross-sectional illustration after an underfill material531is dispensed around the interposer530and the nested component540is shown, in accordance with an embodiment. The underfill material531may be dispensed with any suitable process.

Referring now toFIG.5D, a cross-sectional illustration after a mold layer532is applied over the nested component540and the interposer530is shown, in accordance with an embodiment. Accordingly, the nested component540and the interposer530may be substantially embedded by the combination of the underfill material531and the mold layer532. The mold layer532may be a build-up film, a solder resist laminated layer, or a molding compound. In some embodiments, the mold layer532may be planarized (e.g., with a chemical mechanical polishing (CMP) process). In an embodiment, the mold layer532may be a different material than the underfill material531. Accordingly, in some embodiments, a seam between the underfill material531and the mold layer532may be visible.

Referring now toFIG.5E, a cross-sectional illustration after a second carrier592is attached to the mold layer532is shown, in accordance with an embodiment. In an embodiment, the second carrier592may be attached to the mold layer532with an adhesive513or the like. The second carrier592may be a glass carrier or any other suitable carrier substrate.

Referring now toFIG.5F, a cross-sectional illustration after the first carrier591is removed is shown, in accordance with an embodiment. As shown, the removal of the first carrier591and the adhesive511results in the conductive layer512being exposed.

Referring now toFIG.5G, a cross-sectional illustration after the conductive layer512is removed is shown, in accordance with an embodiment. In an embodiment, the conductive layer512may be removed with grinding process, an etching process, or any other suitable process. Removal of the conductive layer512exposes surfaces of the bump pads584.

Referring now toFIG.5H, a cross-sectional illustration after the assembly is flipped over is shown, in accordance with an embodiment. At this point, the bump pads584are oriented so that the exposed surfaces are facing upwards.

Referring now toFIG.5I, a cross-sectional illustration after dies520are attached to the interposer530and the nested component540is shown, in accordance with an embodiment. In an embodiment, the dies520comprise an active surface521that faces towards the bump pads584. In an embodiment, the nested component540may be a bridge that electrically couples the dies520together.

In an embodiment, the dies520may be electrically coupled to the bump pads584by bumps583. For example, the bumps583may be solder bumps. As shown, opposing surfaces of the bump pads584are covered by bumps583,585. This provides an interconnects between the die520and the interposer530that comprise a pad523, a bump583, a bump pad584, a bump585, and a pad536, and provides interconnects between the die520and the nested component540that comprise a pad523, a bump583, a bump pad584, a bump585, and a pad546. Since solder bumps are used, the dies520are self-aligned to the bump pads584. Accordingly, the dies520, the interposer530, and the nested component540are all self-aligned to a single feature (i.e., the bump pads584). This provides excellent alignment between the dies520and the interposer530and the nested component540.

Referring now toFIG.5J, a cross-sectional illustration after a mold layer522is disposed over the dies520is shown, in accordance with an embodiment. In an embodiment, the mold layer522may be also comprise an underfill material (not shown). In an embodiment, the mold layer522may be recessed (e.g., with a CMP process or the like) to expose backside surfaces of the dies520.

Referring now toFIG.5K, a cross-sectional illustration after the second carrier592is removed is shown, in accordance with an embodiment. In an embodiment, removal of the second carrier592exposes portions of the mold layer532on the package side of the assembly.

Referring now toFIG.5L, a cross-sectional illustration after openings596are formed into the mold layer532to expose package side pads533and543of the interposer530and the nested component540, respectively, is shown, in accordance with an embodiment. In an embodiment, the openings596may be formed with a laser drilling process or a lithography process.

Referring now toFIG.5M, a cross-sectional illustration after bumps537are disposed in the openings596is shown, in accordance with an embodiment. The bumps537may be referred to as package side bumps (PSBs) since they will interface with a package substrate (not shown). However, it is to be appreciated that other interconnect architectures (e.g., LGA, PGA, PoINT, eWLB, or the like) may be used instead of the bumps537in the BGA architecture shown. In an embodiment, the individual electronic packages may be singulated from the panel-level assembly after (or before) the formation of the PSBs537.

Referring now toFIG.6, a cross-sectional illustration of an electronic system670is shown, in accordance with an embodiment. In an embodiment, the electronic system670may comprise a board671(e.g. a printed circuit board (PCB)) that is coupled to a package substrate673by interconnects672. The interconnects672are shown as being solder bumps. However, it is to be appreciated that any interconnect architecture may be used. In an embodiment, the electronic system670may comprise an electronic package600that is coupled to the package substrate673with package side bumps637.

The electronic package600may be substantially similar to the electronic packages described above. For example, the electronic package may comprise an interposer630and one or more nested components640. One or more dies620may be electrically coupled to the interposer630and the nested component640by interconnects that comprise a bump pad684with bumps683,685on opposing surfaces. In an embodiment, an underfill material674may surround the package side bumps637.

FIG.7illustrates a computing device700in accordance with one implementation of the invention. The computing device700houses a board702. The board702may include a number of components, including but not limited to a processor704and at least one communication chip706. The processor704is physically and electrically coupled to the board702. In some implementations the at least one communication chip706is also physically and electrically coupled to the board702. In further implementations, the communication chip706is part of the processor704.

These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip706enables wireless communications for the transfer of data to and from the computing device700. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip706may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device700may include a plurality of communication chips706. For instance, a first communication chip706may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip706may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor704of the computing device700includes an integrated circuit die packaged within the processor704. In some implementations of the invention, the integrated circuit die of the processor may be packaged in an electronic system that comprises a multi-chip package with an interposer and a nested component that are coupled to one or more dies by interconnects that comprises a bump pad with bumps on opposing surfaces of the bump pad, in accordance with embodiments described herein. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip706also includes an integrated circuit die packaged within the communication chip706. In accordance with another implementation of the invention, the integrated circuit die of the communication chip may be packaged in an electronic system that comprises a multi-chip package with an interposer and a nested component that are coupled to one or more dies by interconnects that comprises a bump pad with bumps on opposing surfaces of the bump pad, in accordance with embodiments described herein.

The above description of illustrated implementations of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications may be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Example 1: an electronic package, comprising: an interposer, wherein a cavity passes through the interposer; a nested component in the cavity; and a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect, wherein the first and second interconnects comprise: a first bump; a bump pad over the first bump; and a second bump over the bump pad.

Example 2: the electronic package of Example 1, wherein the bump pad of the first interconnect is substantially coplanar to the bump pad of the second interconnect.

Example 3: the electronic package of Example 1 or Example 2, wherein the nested component and the interposer are embedded in an underfill layer and a first mold layer.

Example 4: the electronic package of Example 3, wherein the die is embedded in a second mold layer.

Example 5: the electronic package of Examples 1-4, wherein the cavity is entirely within a footprint of the die.

Example 6: the electronic package of Examples 1-4, wherein a first portion of the cavity is within a footprint of the die, and wherein a second portion of the cavity is outside of the footprint of the die.

Example 7: the electronic package of Examples 1-6, wherein through component vias extend through the nested component.

Example 8: the electronic package of Examples 1-7, wherein the nested component is a passive component.

Example 9: the electronic package of Examples 1-7, wherein the nested component is an active component.

Example 10: the electronic package of Examples 1-9, further comprising: a second die, wherein the second die is coupled to the nested component by a third interconnect comprising: a first bump; a bump pad over the first bump; and a second bump over the bump pad.

Example 11: the electronic package of Example 10, wherein the nested component electrically couples the first die to the second die.

Example 12: the electronic package of Examples 1-11, further comprising: a second nested component in the cavity.

Example 13: the electronic package of Examples 1-12, wherein an active surface of the nested component faces away from the die.

Example 14: the electronic package of Examples 1-13, wherein the nested component comprises a plurality of stacked dies.

Example 15: the electronic package of Examples 1-14, wherein the interposer comprises a plurality of discrete interposer substrates, wherein edges of the plurality of discrete interposer substrates define the cavity.

Example 16: the electronic package of Examples 1-15, wherein the interposer comprises glass, ceramic, silicon, or organic materials.

Example 17: the electronic package of Examples 1-16, further comprising one or more redistribution layers, wherein the one or more redistribution layers are located over a top surface of the interposer, over a bottom surface of the interposer, over a top surface of the nested component, over a bottom surface of the nested component, over a mold layer that embeds the interposer and the nested component, and/or between the first bumps and the second bumps.

Example 18: an electronic system, comprising: a board; a package substrate electrically coupled to the board; an interposer electrically coupled to the package substrate, wherein the interposer comprises a cavity; a nested component in the cavity, wherein the nested component is electrically coupled to the package substrate; a first die electrically coupled to the interposer and the nested component by interconnects; and a second die electrically coupled to the interposer and the nested component by interconnects, wherein the interconnects comprise: a first bump; a bump pad over the first bump; and a second bump over the bump pad.

Example 19: the electronic system of Example 18, wherein the nested component electrically couples the first die to the second die.

Example 20: the electronic system of Example 18 or 19, wherein the nested component is a passive component.

Example 21: the electronic system of Example 18 or 19, wherein the nested component is an active component.

Example 22: the electronic system of Examples 18-21, wherein the nested component comprises a plurality of stacked dies.

Example 23: a method of forming an electronic package, comprising: forming first bump pads and second bump pads on a first carrier, wherein first bumps are disposed over the first bump pads and the second bump pads; attaching an interposer to the first bump pads, wherein the interposer comprises a cavity; attaching a nested component to the second bump pads, wherein the nested component is within the cavity of the interposer; applying a mold layer over the interposer and the nested component; attaching a second carrier to the mold layer; removing the first carrier; exposing surfaces of the first bump pads and the second bump pads opposite from the first bumps; and attaching a die to the first bump pads and the second bump pads with second bumps.

Example 24: the method of Example 23, further comprising: applying a second mold layer over the die; and removing the second carrier.

Example 25: the method of Example 24, further comprising: attaching interconnects to the interposer and the nested component.