Patent ID: 12230667

DETAILED DESCRIPTION

FIG.1is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the present inventive concepts. In an example embodiment, the semiconductor device may include a dynamic random access memory (DRAM).

Referring toFIG.1, the semiconductor device may include a substrate21, an active region23, an isolation layer25, gate dielectric layers27, gate electrodes28, a gate capping layers29, source/drain regions31, an interlayer insulating layer33, a bit contact plug34, a bit line35, buried contact plugs37, a pad isolation layer50, a plurality of conductive pads51and52, an insulating pattern61, seed layers63, a plurality of lower electrodes71and72, a capacitor dielectric layer81, an upper electrode91, an additional electrode96, an upper insulating layer97, an upper contact plug98, and an upper interconnection99.

The plurality of conductive pads51and52may include a first conductive pad51and a second conductive pad52. The plurality of lower electrodes71and72may include a first lower electrode71and a second lower electrode72. Each of the plurality of lower electrodes71and72may include a monocrystalline perovskite lower conductive layer SLC and a polycrystalline perovskite lower conductive layer PLC. The capacitor dielectric layer81may include monocrystalline perovskite dielectric layers SD and polycrystalline perovskite dielectric layers PD. The upper electrode91may include monocrystalline perovskite upper conductive layers SUC and polycrystalline perovskite upper conductive layers PUC.

The substrate21may include a semiconductor substrate, for example, a silicon wafer or a silicon on insulator (SOI) wafer. The isolation layer25for limiting the active region23may be formed on the substrate21. The isolation layer25may include an insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride (SiOCN), low-K dielectric, high-K dielectric, or a combination thereof.

In the active region23, the gate dielectric layers27, the gate electrodes28, and the gate capping layers29may be stacked in sequence. The source/drain regions31may be formed in the active region23adjacent to both sides of the gate electrodes28. The gate dielectric layers27may be interposed between the active region23and the gate electrodes28. The gate dielectric layers27may include an insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, high-K dielectric, or a combination thereof. The gate electrodes28may be formed at a lower level than an upper end of the active region23. The gate electrodes28may include a conductive material, for example, metal, metal nitride, metal oxide, metal silicide, polysilicon, conductive carbon, or a combination thereof. Each of the gate electrodes28may correspond to a word line. The gate capping layers29may cover upper surfaces of the gate electrodes28. The gate capping layers29may include an insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, low-K dielectric, high-K dielectric, or a combination thereof. The source/drain regions31may include conductive impurities different from those of the active region23. For example, the active region23may include P-type impurities, and the source/drain regions31may include N-type impurities.

The interlayer insulating layer33may cover the active region23, the isolation layer25, the gate dielectric layers27, the gate electrodes28, the gate capping layers29, and the source/drain regions31. The interlayer insulating layer33may include an insulating layer, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, low-K dielectric, high-K dielectric, or a combination thereof.

The bit contact plug34and the bit line35may be formed in the interlayer insulating layer33. The bit line35may be connected to a selected one of the source/drain regions31via the bit contact plug34. The buried contact plugs37may be formed in the interlayer insulating layer33. Each of the buried contact plugs37may pass through the interlayer insulating layer33, and may be connected to a selected one of the source/drain regions31. The bit contact plug34, the bit line35, and the buried contact plugs37may include a conductive material, for example, metal, metal nitride, metal oxide, metal silicide, polysilicon, conductive carbon, or a combination thereof.

The pad isolation layer50and the plurality of conductive pads51and52may be formed on the interlayer insulating layer33. Each of the plurality of conductive pads51and52may pass through the pad isolation layer50and may be connected to a selected one of the buried contact plugs37. The pad isolation layer50may be disposed between the plurality of conductive pads51and52.

The active region23, the gate dielectric layers27, the gate electrodes28, and the source/drain regions31may constitute a plurality of transistors. In an example embodiment, each of the plurality of transistors may serve as a switching element. In an example embodiment, the switching elements may be configured as other active/passive elements, for example, diodes. The plurality of conductive pads51and52may be connected to the source/drain regions31via the buried contact plugs37. Each of the plurality of conductive pads51and52may be construed as being connected to a switching element via a selected one of the buried contact plugs37.

Each of the plurality of conductive pads51and52may be surrounded by the pad isolation layer50. The insulating pattern61may be formed on the pad isolation layer50between the first conductive pad51and the second conductive pad52. The insulating pattern61may have a height greater than a horizontal width thereof. The insulating pattern61may include a first side surface S1and a second side surface S2opposite to the first side surface S1. The first side surface S1may be adjacent to the first conductive pad51, and the second side surface S2may be adjacent to the second conductive pad52. The seed layers63may be formed next to the side surfaces S1and S2of the insulating pattern61.

The plurality of lower electrodes71and72may be formed on the outer sides of the seed layers63. The first lower electrode71may be adjacent to the first side surface S1, and may be in contact with one seed layer63and the first conductive pad51. The second lower electrode72may be adjacent to the second side surface S2and may be in contact with the other seed layer63and the second conductive pad52. The seed layers63may be interposed between the first lower electrode71and the first side surface S1and between the second lower electrode72and the second side surface S2.

Compared to the polycrystalline perovskite lower conductive layers PLC, the monocrystalline perovskite lower conductive layers SLC may be formed relatively close to the seed layers63. The monocrystalline perovskite lower conductive layers SLC may come in direct contact with the seed layers63and the plurality of conductive pads51and52. The polycrystalline perovskite lower conductive layers PLC may come in direct contact with the plurality of conductive pads51and52. In an example embodiment, the plurality of lower electrodes71and72may be entirely formed of the monocrystalline perovskite lower conductive layers SLC.

The capacitor dielectric layer81may cover the plurality of lower electrodes71and72, and cover an upper surface of the insulating pattern61, upper surfaces of the seed layers63, and the pad isolation layer50. Compared to the polycrystalline perovskite dielectric layers PD, the monocrystalline perovskite dielectric layers SD may be formed relatively close to the side surfaces S1and S2of the insulating pattern61and the seed layers63. Compared to the polycrystalline perovskite dielectric layers PD, the monocrystalline perovskite dielectric layers SD may be formed relatively close to the monocrystalline perovskite lower conductive layers SLC. The monocrystalline perovskite dielectric layers SD may come in direct contact with the monocrystalline perovskite lower conductive layers SLC. The polycrystalline perovskite dielectric layers PD may come in direct contact with the polycrystalline perovskite lower conductive layers PLC, the upper surface of the insulating pattern61, and the pad isolation layer50. In an example embodiment, the capacitor dielectric layer81may be formed entirely of the monocrystalline perovskite dielectric layers SD.

The upper electrode91may cover the capacitor dielectric layer81. Compared to the polycrystalline perovskite upper conductive layers PUC, the monocrystalline perovskite upper conductive layers SUC may be formed relatively close to the monocrystalline perovskite dielectric layers SD. The monocrystalline perovskite upper conductive layers SUC may come in direct contact with the monocrystalline perovskite dielectric layers SD. The polycrystalline perovskite upper conductive layers PUC may come in direct contact with the polycrystalline perovskite dielectric layers PD. In an example embodiment, the upper electrode91may be formed entirely of the monocrystalline perovskite upper conductive layers SUC.

The plurality of lower electrodes71and72, the capacitor dielectric layer81, and the upper electrode91may constitute capacitors. Due to the configuration of the insulating pattern61, the seed layers63, the plurality of lower electrodes71and72, the capacitor dielectric layer81, and the upper electrode91, capacitors having increased capacitance may be implemented to have reduced leakage current.

The additional electrode96may be formed on the upper electrode91. The additional electrode96may include a conductive material, for example, metal, metal nitride, metal oxide, metal silicide, polysilicon, conductive carbon, or a combination thereof. The upper insulating layer97may be formed on the additional electrode96. The upper insulating layer97may include an insulating material, for example silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, low-K dielectric, high-K dielectric, or a combination thereof. The upper contact plug98may be formed to pass through the upper insulating layer97and to be in contact with the additional electrode96. The upper interconnection99may be formed on the upper insulating layer97to be in contact with the upper contact plug98. The upper contact plug98and the upper interconnection99may include a conductive material, for example, metal, metal nitride, metal oxide, metal silicide, polysilicon, conductive carbon, or a combination thereof.

In an example embodiment, the first conductive pad51and the second conductive pad52may constitute one pair of conductive pads. Each of the plurality of lower electrodes71and72may have an L shape. The first lower electrode71and the second lower electrode72may be disposed in a mirror-inverted manner with the insulating pattern61interposed therebetween. The seed layers63may be interposed between the first lower electrode71and the insulating pattern61and between the second lower electrode72and the insulating pattern61. A lower surface of the insulating pattern61may be in contact with an upper surface of the pad isolation layer50. The first lower electrode71and the second lower electrode72may constitute one pair of lower electrodes. The first lower electrode71may be in contact with an upper surface of the first conductive pad51, and the second lower electrode72may be in contact with an upper surface of the second conductive pad52. The first lower electrode71may be connected to a corresponding one of the plurality of transistors via the first conductive pad51and a selected one of the buried contact plugs37. The second lower electrode72may be connected to a corresponding one of the plurality of transistors via the second conductive pad52and a selected one of the buried contact plugs37. Each of the capacitors may be connected to a corresponding one of the plurality of transistors and may constitute a unit cell. The unit cell may include a selected one of the first lower electrode71and the second lower electrode72.

In an example embodiment, the monocrystalline perovskite lower conductive layers SLC, the polycrystalline perovskite lower conductive layers PLC, the monocrystalline perovskite dielectric layers SD, the polycrystalline perovskite dielectric layers PD, the monocrystalline perovskite upper conductive layers SUC, and the polycrystalline perovskite upper conductive layers PUC may be construed as monocrystalline lower conductive layers, polycrystalline conductive layers, monocrystalline dielectric layers, polycrystalline dielectric layers, monocrystalline upper conductive layers, and polycrystalline upper conductive layers, respectively.

Referring toFIG.2, the first lower electrode71may be divided into a monocrystalline perovskite lower conductive layer SLC and a polycrystalline perovskite lower conductive layer PLC in terms of material. A side surface of the monocrystalline perovskite lower conductive layer SLC may come in direct contact with a side surface of a seed layer63. A lower end of the monocrystalline perovskite lower conductive layer SLC may come in direct contact with the upper surface of the first conductive pad51. The polycrystalline perovskite lower conductive layer PLC may be in continuity with or may be connected to the monocrystalline perovskite lower conductive layer SLC. The polycrystalline perovskite lower conductive layer PLC may be relatively apart from the seed layer63, compared to the monocrystalline perovskite lower conductive layer SLC. A lower surface of the polycrystalline perovskite lower conductive layer PLC may come in direct contact with the upper surface of the first conductive pad51.

Referring toFIG.3, the first lower electrode71may be divided into a lower region LP and an upper region UP in terms of geometry. The lower region LP may have a horizontal width greater than a height thereof. The lower region LP may come in direct contact with the upper surface of the first conductive pad51. The upper region UP may be in continuity with or may be connected to the lower region LP. The upper region UP may have a height greater than a horizontal width thereof. A side surface of the upper region UP may come in direct contact with the side surface of the seed layer63. The first lower electrode71may have an L shape.

FIGS.4and5are perspective views showing parts of a semiconductor device according to example embodiments of the present inventive concepts, andFIG.6is a layout showing a part of the semiconductor device.FIG.5is a perspective view showing a partial configuration ofFIG.4,FIG.6is a layout showing some components ofFIG.4disposed on a substrate21, andFIG.1may correspond to a part of a cross-sectional view taken along line I-I′ ofFIGS.4and6.

Referring toFIG.4, the semiconductor device may include a pad isolation layer50, a plurality of conductive pads51and52, insulating patterns61, seed layers63, a plurality of lower electrodes71and72, a capacitor dielectric layer81, and an upper electrode91.

Referring toFIG.5, the semiconductor device may include the pad isolation layer50, the plurality of conductive pads51and52, the insulating patterns61, the seed layers63, and the plurality of lower electrodes71and72. Each of the plurality of lower electrodes71and72may include a lower region LP having a horizontal width greater than a height thereof and an upper region UP having a height greater than a horizontal width thereof. The upper region UP may include a monocrystalline perovskite lower conductive layer SLC. The lower region LP may include a polycrystalline perovskite lower conductive layer PLC and the monocrystalline perovskite lower conductive layer SLC. Each of the insulating patterns61may include a first side surface S1and a second side surface S2opposite to the first side surface S1. The first side surface S1may be adjacent to a first conductive pad51, and the second side surface S2may be adjacent to a second conductive pad52. The seed layers63may be formed next to the side surfaces S1and S2of the insulating patterns61. The plurality of lower electrodes71and72may be formed on the outer sides of the seed layers63. The first lower electrodes71may be adjacent to the first side surfaces S1and may be in contact with the seed layers63and the first conductive pads51. The second lower electrodes72may be adjacent to the second side surfaces S2and may be in contact with the seed layers63and the second conductive pads52.

Referring toFIG.6, the insulating patterns61, the seed layers63, and the plurality of lower electrodes71and72may be disposed on the substrate21. The insulating patterns61may be repeatedly arranged in a row direction and a column direction.

Referring back toFIGS.5and6, one pair of lower electrodes71and72may be aligned on one pair of conductive pads51and52. In an example embodiment, the pair of conductive pads51and52may be repeatedly disposed on the substrate21in the row direction and the column direction. The pair of lower electrodes71and72may be repeatedly disposed on the substrate21in the row direction and the column direction along with the repeated arrangement of the pair of conductive pads51and52. The repeated arrangement of the pair of conductive pads51and52may be separated from each other by the pad isolation layer50.

FIG.7is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the present inventive concepts.

Referring toFIG.7, the semiconductor device may include a substrate21, a pad isolation layer50, a plurality of conductive pads51and52, an insulating pattern61, a plurality of lower electrodes71and72, a capacitor dielectric layer81, and an upper electrode91.

The insulating pattern61may include a first side surface S1and a second side surface S2opposite to the first side surface S1. The first lower electrode71may come in direct contact with the first side surface S1and the first conductive pad51. The second lower electrode72may come in direct contact with the second side surface S2and the second conductive pad52. Monocrystalline perovskite lower conductive layers SLC may be formed relatively close to the side surfaces S1and S2of the insulating pattern61, compared to polycrystalline perovskite lower conductive layers PLC. The monocrystalline perovskite lower conductive layers SLC may come in direct contact with the first side surface S1and the second side surface S2.

The capacitor dielectric layer81may cover the plurality of lower electrodes71and72, and cover an upper surface of the insulating pattern61and the pad isolation layer50. Monocrystalline perovskite dielectric layers SD may be formed relatively close to the side surfaces S1and S2of the insulating pattern61, compared to polycrystalline perovskite dielectric layers PD. The monocrystalline perovskite dielectric layers SD may be formed relatively close to the monocrystalline perovskite lower conductive layers SLC, compared to the polycrystalline perovskite dielectric layers PD.

Due to the configuration of the insulating pattern61, the plurality of lower electrodes71and72, the capacitor dielectric layer81, and the upper electrode91, capacitors having increased capacitance may be implemented to have reduced leakage current. In an example embodiment, the semiconductor device described with reference toFIG.7may be the same as or substantially similar to the semiconductor device ofFIG.1, except for an omission of the seed layers63.

FIGS.8and9are perspective views showing parts of a semiconductor device according to example embodiments of the present inventive concepts, andFIG.10is a layout showing a part of the semiconductor device.FIG.9is a perspective view showing a partial configuration ofFIG.8,FIG.10is a layout showing some components ofFIG.8disposed on a substrate21, andFIG.7may correspond to a cross-sectional view of a part ofFIGS.8and10.

Referring toFIG.8, monocrystalline perovskite lower conductive layers SLC may come in direct contact with insulating patterns61.

Referring toFIG.9, the monocrystalline perovskite lower conductive layers SLC may come in direct contact with first and second side surfaces S1and S2of the insulating patterns61.

Referring toFIG.10, the insulating patterns61and the plurality of lower electrodes71and72may be disposed on the substrate21.

FIGS.11,13,15,17,19,21,23,25,26,27,29,31,33,35,37,39, and41are cross-sectional views taken along lines I-I′, and ofFIGS.4and6to illustrate a method of fabricating a semiconductor device according to example embodiments of the present inventive concepts.FIGS.12,14,16,18,20,22,24,28,30,32,34,36,38, and40are perspective views of the semiconductor device according to the process operations ofFIGS.11,13,15,17,19,21,23,25,26,27,29,31,33,35,37,39, and41, andFIGS.42and43are partial diagrams showing parts ofFIG.41.

Referring toFIGS.11and12, the pad isolation layer50and the plurality of conductive pads51and52may be formed. The plurality of conductive pads51and52may include the first conductive pads51and the second conductive pads52.

The pad isolation layer50may include an insulating material, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride (SiOCN), or a combination thereof. The pad isolation layer50may include a single-layer or multi-layer structure, and include a single-pattern structure or a structure in which a plurality of insulating patterns are combined. In an example embodiment, the pad isolation layer50may include silicon nitride.

The plurality of conductive pads51and52may include conductive patterns formed of for example, metal, a metal nitride, metal oxide, a metal silicide, polysilicon, conductive carbon, or a combination thereof. Formation of the pad isolation layer50and the plurality of conductive pads51and52may involve a thin film formation process, a patterning process, and a planarization process. The planarization process may include a chemical mechanical polishing (CMP) process, an etch-back process, or a combination thereof. Upper surfaces of the pad isolation layer50and the plurality of conductive pads51and52may be substantially coplanar. Each of the plurality of conductive pads51and52may be surrounded by the pad isolation layer50. The plurality of conductive pads51and52may be regularly arranged in a two-dimensional array of the row direction and the column direction.

In an example embodiment, the pad isolation layer50may include a plurality of insulating patterns. The pad isolation layer50may be interposed among the plurality of conductive pads51and52.

In an example embodiment, the pad isolation layer50and the plurality of conductive pads51and52may be formed on a substrate21which is the same as or substantially similar to that described above with reference toFIG.1. Each of the plurality of conductive pads51and52may pass through the pad isolation layer50and may be connected to a switching element which is the same as or substantially similar to that described above with reference toFIG.1.

Referring toFIGS.13and14, a sacrificial seed layer55may be formed on the pad isolation layer50and the plurality of conductive pads51and52. The sacrificial seed layer55may include Ni, Cu, Al, Pd, or a combination thereof.

Referring toFIGS.15and16, a sacrificial layer56may be formed on the sacrificial seed layer55. The sacrificial layer56may include a monocrystalline Ge layer, a monocrystalline S1layer, a monocrystalline SiC layer, a monocrystalline SiGe layer, or a combination thereof. For example, the sacrificial layer56may include a monocrystalline Ge layer. The sacrificial layer56may have a greater thickness than that of the sacrificial seed layer55. In an example embodiment, formation of the sacrificial layer56may include a process of forming a Ge layer on the sacrificial seed layer55and a process of crystallizing the Ge layer by applying laser annealing thereto. In an example embodiment, the sacrificial layer56may be formed by using an epitaxial growth technique.

In an example embodiment, the sacrificial seed layer55may be formed on the sacrificial layer56. In an example embodiment, the sacrificial seed layer55may be formed on and under the sacrificial layer56. In an example embodiment, the sacrificial seed layer55and the sacrificial layer56may be stacked alternately and repeatedly.

Referring toFIGS.17and18, sacrificial patterns57may be formed by patterning the sacrificial layer56and the sacrificial seed layer55. The respective sacrificial patterns57may be formed on the pad isolation layer50between the plurality of conductive pads51and52. Each of the sacrificial patterns57may have a height greater than a horizontal width thereof. Upper surfaces of the plurality of conductive pads51and52may be exposed. The upper surface of the pad isolation layer50may be at least partially covered by the sacrificial patterns57.

In an example embodiment, the sacrificial patterns57may be disposed on the pad isolation layer50in parallel with each other in the row direction. The sacrificial patterns57and pairs of conductive pads51and52may be alternately disposed.

Referring toFIGS.19and20, the seed layers63may be formed to cover side surfaces and upper surfaces of the sacrificial patterns57and cover the plurality of conductive pads51and52and the pad isolation layer50. The seed layers63may include a monocrystalline material. For example, the seed layers63may include a monocrystalline perovskite material. In an example embodiment, the seed layers63may include a monocrystalline perovskite dielectric material, a monocrystalline perovskite conductive material, or a combination thereof. The monocrystalline perovskite dielectric material may include SrTiO3, BaTiO3, (Ba, Sr)TiO3, CaTiO3, PbTiO3, KTaO3, NaNbO3, HfPbO3, KNbO3, BaTiO3, or a combination thereof. The monocrystalline perovskite conductive material may include SrRuO3, BaSnO3, (La, Sr)CoO3, (La, Sr)CuO3, (La, Sr)MnO3, LaNiO3, SrSnO3, SrMoO3, or a combination thereof. For example, the seed layers63may include SrTiO3 layers.

In an example embodiment, formation of the seed layers63may include a process of depositing a thin film and a process of crystallizing the thin film by applying laser annealing thereto. In an example embodiment, the seed layers63may be formed by using an epitaxial growth technique.

Referring toFIGS.21and22, the plurality of conductive pads51and52may be exposed by partially removing the seed layers63. Due to the process of exposing the plurality of conductive pads51and52, some of the pad isolation layers50and the upper surfaces of the sacrificial patterns57may also be exposed. The seed layers63may be retained next to the side surfaces of the sacrificial patterns57. The seed layers63may be partially removed by using an anisotropic etching process. In an example embodiment, due to the etching process, the seed layers63may remain only on both sidewalls of the sacrificial patterns57in the row direction.

Referring toFIGS.23and24, the monocrystalline perovskite lower conductive layers SLC and the polycrystalline perovskite lower conductive layers PLC may be formed to cover outer sides of the seed layers63, the plurality of conductive pads51and52, the upper surfaces of the sacrificial patterns57, and the pad isolation layer50. The monocrystalline perovskite lower conductive layers SLC may be formed relatively close to the seed layers63, compared to the polycrystalline perovskite lower conductive layers PLC. The polycrystalline perovskite lower conductive layers PLC may be in continuity with or may be connected to the monocrystalline perovskite lower conductive layers SLC. The monocrystalline perovskite lower conductive layers SLC and the polycrystalline perovskite lower conductive layers PLC may include SrRuO3, BaSnO3, (La, Sr)CoO3, (La, Sr)CuO3, (La, Sr)MnO3, LaNiO3, SrSnO3, SrMoO3, or a combination thereof. For example, the monocrystalline perovskite lower conductive layers SLC and the polycrystalline perovskite lower conductive layers PLC may include SrRuO3 layers.

In an example embodiment, formation of the monocrystalline perovskite lower conductive layers SLC and the polycrystalline perovskite lower conductive layers PLC may include a process of depositing a thin film and a process of crystallizing the thin film by applying laser annealing thereto. In an example embodiment, the monocrystalline perovskite lower conductive layers SLC and the polycrystalline perovskite lower conductive layer PLC may be formed by using an epitaxial growth technique.

In an example embodiment, during the process of forming the monocrystalline perovskite lower conductive layers SLC and the polycrystalline perovskite lower conductive layers PLC, the seed layers63may serve to induce crystallization of the monocrystalline perovskite lower conductive layers SLC. The monocrystalline perovskite lower conductive layers SLC may grow in crystal directions of the seed layers63and also in a lateral direction to the crystal directions. The monocrystalline perovskite lower conductive layers SLC may slightly extend outward from the seed layers63. The monocrystalline perovskite lower conductive layers SLC may have a greater width than the seed layers63. Boundaries between the monocrystalline perovskite lower conductive layers SLC and the polycrystalline perovskite lower conductive layers PLC may be formed on the plurality of conductive pads51and52. Lower ends of the monocrystalline perovskite lower conductive layers SLC and lower surfaces of the polycrystalline perovskite lower conductive layers PLC may come in direct contact with upper surfaces of the plurality of conductive pads51and52.

Referring toFIG.25, a spacer layer65may be formed to conformally cover upper surfaces of the monocrystalline perovskite lower conductive layers SLC and the polycrystalline perovskite lower conductive layers PLC. The spacer layer65may include polysilicon.

Referring toFIG.26, the spacer layer65, the monocrystalline perovskite lower conductive layers SLC, and the polycrystalline perovskite lower conductive layers PLC may be anisotropically etched such that spacers65S may be formed. The spacers65S may be retained on the side surfaces of the sacrificial patterns57and the upper surfaces of the plurality of conductive pads51and52. The upper surfaces of the sacrificial patterns57, upper surfaces of the seed layers63, and upper ends of the monocrystalline perovskite lower conductive layers SLC may be exposed. The pad isolation layers50between the spacers65S may be exposed. The monocrystalline perovskite lower conductive layers SLC may be retained between the spacers65S and the seed layers63. The polycrystalline perovskite lower conductive layers PLC may be retained between the spacers65S and the plurality of conductive pads51and52.

Referring toFIGS.27and28, the spacers65S may be completely removed such that the monocrystalline perovskite lower conductive layers SLC and the polycrystalline perovskite lower conductive layers PLC may be exposed.

Referring toFIGS.29and30, a mold layer67may be formed to fill gaps between the sacrificial patterns57. A thin film formation process and a planarization process may be used to form the mold layer67. The planarization process may include a CMP process, an etch-back process, or a combination thereof. The upper surfaces of the sacrificial patterns57, the upper surfaces of the seed layers63, the upper ends of the monocrystalline perovskite lower conductive layers SLC, and an upper surface of the mold layer67may be exposed. The mold layer67may include a polysilicon.

Referring toFIGS.31and32, the sacrificial patterns57may be completely removed such that trenches57T may be formed. The pad isolation layer50may be exposed on bottoms of the trenches57T. The seed layers63may be exposed on sidewalls of the trenches57T.

Referring toFIGS.33and34, the insulating patterns61may be formed in the trenches57T. A thin film formation process and a planarization process may be used to form the insulating patterns61. The planarization process may include a CMP process, an etch-back process, or a combination thereof. Upper surfaces of the insulating patterns61, the upper surfaces of the seed layers63, the upper ends of the monocrystalline perovskite lower conductive layers SLC, and the upper surface of the mold layer67may be exposed. The insulating patterns61may include a silicon oxide, a silicon nitride, a silicon oxynitride, a silicon oxycarbonitride, a low-K dielectric, or a combination thereof. In an example embodiment, the insulating patterns61may be a silicon oxide.

Each of the insulating patterns61may have a single-layer structure. Each of the insulating patterns61may have a physically continuous integrated structure including a plurality of layers. Each of the insulating patterns61may come in direct contact with the pad isolation layer50.

Referring toFIGS.35and36, the mold layer67may be completely removed such that the monocrystalline perovskite lower conductive layers SLC and the polycrystalline perovskite lower conductive layers PLC may be exposed.

Referring toFIGS.37and38, a node separation process may be used to form the plurality of lower electrodes71and72. The plurality of lower electrodes71and72may include the first lower electrodes71and the second lower electrodes72. The respective insulating patterns61may be retained between the plurality of lower electrodes71and72. The seed layers63may be retained between the plurality of lower electrodes71and72and the insulating patterns61. Each of the plurality of lower electrodes71and72may include a monocrystalline perovskite lower conductive layer SLC and a polycrystalline perovskite lower conductive layer PLC which is in continuity with or is connected to the monocrystalline perovskite lower conductive layer SLC.

Referring toFIGS.39and40, the capacitor dielectric layer81may be formed to cover upper surfaces of the plurality of lower electrodes71and72, the seed layers63, the insulating patterns61, and the pad isolation layer50. The capacitor dielectric layer81may include a monocrystalline perovskite dielectric layer SD and a polycrystalline perovskite dielectric layer PD.

The monocrystalline perovskite dielectric layers SD and the polycrystalline perovskite dielectric layer PD may include SrTiO3, BaTiO3, (Ba, Sr)TiO3, CaTiO3, PbTiO3, KTaO3, NaNbO3, HfPbO3, KNbO3, BaTiO3, or a combination thereof. In an example embodiment, the monocrystalline perovskite dielectric layers SD and the polycrystalline perovskite dielectric layer PD may include superlattice structures formed by alternately depositing at least two materials selected from among SrTiO3, BaTiO3, (Ba, Sr)TiO3, CaTiO3, PbTiO3, KTaO3, NaNbO3, HfPbO3, KNbO3, and BaTiO3. For example, the monocrystalline perovskite dielectric layers SD and the polycrystalline perovskite dielectric layer PD may include superlattice structures formed by alternately depositing BaTiO3 and SrTiO3.

In an example embodiment, formation of the capacitor dielectric layer81may include a process of depositing a thin film and a process of crystallizing the thin film by applying laser annealing thereto. In an example embodiment, the capacitor dielectric layer81may be formed by using an epitaxial growth technique.

In an example embodiment, during the process of forming the capacitor dielectric layer81, the monocrystalline perovskite lower conductive layers SLC may serve to induce crystallization of the monocrystalline perovskite dielectric layers SD. The monocrystalline perovskite dielectric layers SD may grow in crystal directions of the monocrystalline perovskite lower conductive layers SLC and also in a lateral direction to the crystal directions. The monocrystalline perovskite dielectric layers SD may slightly extend outward from the monocrystalline perovskite lower conductive layers SLC. The monocrystalline perovskite dielectric layers SD may have a greater width than the monocrystalline perovskite lower conductive layers SLC. The monocrystalline perovskite dielectric layers SD may have a greater width than the seed layers63. Boundaries between the monocrystalline perovskite dielectric layers SD and the polycrystalline perovskite dielectric layer PD may be formed on the outside of the monocrystalline perovskite lower conductive layers SLC.

Referring toFIGS.4and41, the upper electrode91may be formed on the capacitor dielectric layer81. The upper electrode91may include monocrystalline perovskite upper conductive layers SUC and a polycrystalline perovskite upper conductive layer PUC.

The monocrystalline perovskite upper conductive layers SUC may be formed relatively close to the monocrystalline perovskite dielectric layers SD compared to the polycrystalline perovskite upper conductive layer PUC. The polycrystalline perovskite upper conductive layer PUC may be in continuity with or may be connected to the monocrystalline perovskite upper conductive layers SUC. The monocrystalline perovskite upper conductive layers SUC and the polycrystalline perovskite upper conductive layer PUC may include SrRuO3, BaSnO3, (La, Sr)CoO3, (La, Sr)CuO3, (La, Sr)MnO3, LaNiO3, SrSnO3, SrMoO3, or a combination thereof. For example, the upper electrode91may include an SrRuO3 layer.

In an example embodiment, formation of the upper electrode91may include a process of depositing a thin film and a process of crystallizing the thin film by applying laser annealing thereto. In an example embodiment, the upper electrode91may be formed by using an epitaxial growth technique.

In an example embodiment, during the process of forming the upper electrode91, the monocrystalline perovskite dielectric layers SD may serve to induce crystallization of the monocrystalline perovskite upper conductive layers SUC. The monocrystalline perovskite upper conductive layers SUC may grow in crystal directions of the monocrystalline perovskite dielectric layers SD and also in a lateral direction to the crystal directions. The monocrystalline perovskite upper conductive layers SUC may slightly extend outward from the monocrystalline perovskite dielectric layers SD. The monocrystalline perovskite upper conductive layers SUC may have a greater width than the monocrystalline perovskite dielectric layers SD. The monocrystalline perovskite upper conductive layers SUC may have a greater width than the seed layers63. Boundaries between the monocrystalline perovskite upper conductive layers SUC and the polycrystalline perovskite upper conductive layer PUC may be formed on the outside of the monocrystalline perovskite dielectric layers SD.

FIGS.42and43are partial diagrams showing parts ofFIG.41.

Referring toFIGS.4,5,41, and42, the insulating patterns61may be spaced apart from each other in the row direction and the column direction. In the column direction, the polycrystalline perovskite dielectric layer PD may completely fill gaps between the insulating patterns61. Profiles of the polycrystalline perovskite dielectric layer PD and the polycrystalline perovskite upper conductive layer PUC may be controlled by adjusting a column-direction interval between the insulating patterns61and a thickness of the polycrystalline perovskite dielectric layer PD. Parts of the polycrystalline perovskite upper conductive layer PUC may be formed at a higher level than the upper surfaces of the insulating patterns61.

Referring toFIGS.4,5,41, and43, in the column direction, the polycrystalline perovskite dielectric layer PD may conformally cover side surfaces of the insulating patterns61. Profiles of the polycrystalline perovskite dielectric layer PD and the polycrystalline perovskite upper conductive layer PUC may be controlled by adjusting a column-direction interval between the insulating patterns61and a thickness of the polycrystalline perovskite dielectric layer PD. Between the insulating patterns61, parts of the polycrystalline perovskite upper conductive layer PUC may conformally cover the upper surface of the polycrystalline perovskite dielectric layer PD.

Referring back toFIG.1, additional electrodes96, an upper insulating layer97, upper contact plugs98, and an upper interconnection99may be formed on the upper electrode91.

FIGS.44,46, and48are cross-sectional views illustrating a method of fabricating a semiconductor device according to some example embodiments of the present inventive concepts, andFIGS.45and47are perspective views according to the process operations ofFIGS.44,46, and48.

Referring toFIGS.44and45, monocrystalline perovskite lower conductive layers SLC and polycrystalline perovskite lower conductive layers PLC may be formed to cover side surfaces and upper surfaces of the sacrificial patterns57and cover the plurality of conductive pads51and52and the pad isolation layer50. The monocrystalline perovskite lower conductive layers SLC may be formed relatively close to the sacrificial patterns57, compared to the polycrystalline perovskite lower conductive layers PLC. The monocrystalline perovskite lower conductive layers SLC may come in direct contact with the sacrificial patterns57.

In an example embodiment, during the process of forming the monocrystalline perovskite lower conductive layers SLC and the polycrystalline perovskite lower conductive layers PLC, the sacrificial patterns57may serve to induce crystallization of the monocrystalline perovskite lower conductive layers SLC. The monocrystalline perovskite lower conductive layers SLC may grow in crystal directions of the sacrificial patterns57and also in a lateral direction to the crystal directions. The monocrystalline perovskite lower conductive layers SLC may slightly extend outward from the sacrificial patterns57. The monocrystalline perovskite lower conductive layers SLC may have a greater width than the sacrificial patterns57. Boundaries between the monocrystalline perovskite lower conductive layers SLC and the polycrystalline perovskite lower conductive layers PLC may be formed on the plurality of conductive pads51and52. Lower end portions of the monocrystalline perovskite lower conductive layers SLC and lower surfaces of the polycrystalline perovskite lower conductive layers PLC may come in direct contact with upper surfaces of the plurality of conductive pads51and52.

Referring toFIGS.46and47, the upper surfaces of the sacrificial patterns57and some of the pad isolation layer50may be exposed by partially removing the monocrystalline perovskite lower conductive layers SLC and the polycrystalline perovskite lower conductive layers PLC.

Referring toFIGS.8,9, and48, the capacitor dielectric layer81may be formed to cover upper surfaces of the plurality of lower electrodes71and72, the insulating patterns61, and the pad isolation layer50. The process of forming the plurality of lower electrodes71and72and the insulating patterns61may include the same or substantially similar process operations to the operations described above with reference toFIGS.29to43. The capacitor dielectric layer81may include the monocrystalline perovskite dielectric layers SD and the polycrystalline perovskite dielectric layer PD. The upper electrode91may be formed on the capacitor dielectric layer81. The upper electrode91may include the monocrystalline perovskite upper conductive layers SUC and the polycrystalline perovskite upper conductive layer PUC.

According to the example embodiments of the present inventive concepts, a capacitor in which a monocrystalline perovskite dielectric layer is interposed between monocrystalline perovskite electrode layers is provided. Application of the monocrystalline perovskite dielectric layer may remarkably increase capacitance of the capacitor. A semiconductor device including a capacitor having increased capacitance and reduced leakage current may be implemented.

Although the example embodiments of the present inventive concepts have been described with reference to the accompanying drawings, those of ordinary skill in the art to which the present inventive concepts pertain would appreciate that the present inventive concepts may be implemented in other example embodiments without departing from the technical spirit and essential features thereof. Thus, the above-described example embodiments are intended to show at least some aspects of the present inventive concepts.