Patent ID: 12216159

DETAILED DESCRIPTION

The inventors recognized several drawbacks of previous techniques for measuring propagation delays of an integrated circuit. One such drawback is that propagation delay test structures have not been implemented on-chip in a cost-effective way. For instance, previous test structures rely on using a multitude of different structures on the integrated circuit to produce enough delay data to conduct accurate measurements. For example, in some applications, measuring a mean propagation delay of an integrated circuit can require delay measurements from hundreds of different logic gate configurations, which, according to previous techniques, could require hundreds of differently configured test structures to generate the requisite number of measurements. Similarly, measuring a variance in propagation delay of an integrated circuit could require even more test structures than for mean measurements. The inventors recognized that variance measurements are particularly useful to incorporate during simulation for estimating post-fabrication performance, as the variance in propagation delay in integrated circuits is increasing as integrated circuits are made to include denser logic gate configurations.

In some applications, even more dedicated test structures may be required to measure different types of propagation delay in the integrated circuit, such as cell delay due to propagation via logic gates, wire delay due to propagation via wires between logic gates, and delays due to voltage thresholds of the transistors. By relying on a multitude of different structures to obtain useful propagation delay measurements, test structures according to previous techniques take up a large amount of space on-chip, making them expensive to implement and unsuitable for obtaining various different types of propagation delay measurements.

Another drawback is that measurement circuits for measuring propagation delays from on-chip test structures are implemented outside of the integrated circuit, which increases the complexity of transmitting signals off of the chip for measurement. As discussed above, test structures can be large and take up expensive space on-chip, which precludes inclusion of measurement circuits on-chip to measure propagation delays generated by the test structures. Since the measurement circuits are implemented off-chip, signals generated by the test structures have to be extracted for off-chip measurement, which can require large test pads to be placed on the integrated circuit for reading off the generated signals via bond wires. For instance, since propagation delays on an integrated circuit are typically on the order of picoseconds or shorter, the signals generated by the integrated circuit are unsuitable for use with standard input/output (I/O) interface standards such as Joint Test Action Group (JTAG) interface standards. The large test pads used to read signals off of the integrated circuit for measurement also increase the cost of implementation due to taking up a large amount of space on-chip.

To overcome the above drawbacks of previous techniques, the inventors developed improved techniques for measuring propagation delay of an integrated circuit that facilitate performing propagation delay measurements on-chip. In some embodiments, an integrated circuit described herein may include programmable circuitry and a controller configured to provide control signals to the programmable circuitry to generate signals for measuring propagation delays of the integrated circuit. For example, in some embodiments, the programmable circuitry may include a programmable oscillator with a plurality of oscillator stages that are switchable into and out of a delay path based on control signals from the controller. In this example, switching oscillator stages in and out of the delay path using control signals from the controller can allow the same programmable oscillator to generate many different oscillator signals, (e.g., using different combinations of oscillator stages), according to the received control signals. In some embodiments, the controller may be configured to determine a central tendency and/or variance of propagation delay of the integrated circuit, such as using signals generated using different combinations of oscillator stages of a programmable oscillator. Moreover, in some embodiments, programmable circuitry described herein can include a plurality of oscillators, each having transistors with different voltage thresholds, facilitating measurements of propagation delay for the different voltage thresholds.

In some embodiments, programmable circuitry of an integrated circuit can include a plurality of programmable delay paths, which can be configured to provide an amount of cell delay and an amount of wire delay based on control signals from a controller. For example, each programmable delay path can include path tuners configured to add different amounts of cell and wire delay to the delay path based on the control signals. In this example, adding cell and wire delays based on the control signals can allow the same programmable delay path to generate signals for measuring delays due to cell and wire delays of the integrated circuit (e.g., using different tuner configurations). In some embodiments, each programmable delay path can have transistors with different channel widths, facilitating measurements of propagation delay for the different channel widths.

Accordingly, programmable circuitry and controllers described herein can generate a large enough amount of propagation delay measurements, and/or measurements taking into account various different types of propagation delays, using programmable structures that take up less space on-chip than previously employed fixed test structures. By consuming less space on-chip, programmable circuitry described herein is cost-effective to implement in an integrated circuit. In addition, by including the controller in the integrated circuit, the controller can be configured to perform measurements on the integrated circuit and offload data from the chip using a standard interface.

It should be appreciated that techniques described herein can be used alone or in combination.

FIG.1is a block diagram illustrating an exemplary integrated circuit100athat includes programmable ring oscillator (ROSC) circuitry200aand programmable delay path circuitry300a, in accordance with some embodiments. As shown inFIG.1, integrated circuit100aalso includes a test access port (TAP)110configured to receive input parameters112afrom outside of the integrated circuit100aand transmit one or more outputs112boutside the integrated circuit100a. Also shown inFIG.1, integrated circuit100amay be configured to receive a clock (CLK) signal and provide the CLK signal to programmable ROSC circuitry200aand/or programmable delay path circuitry300a. In some embodiments, integrated circuit100amay include an array of digital logic gates. For example, integrated circuit100amay be a field programmable gate array (FPGA). Alternatively, integrated circuit100amay be an application-specific integrated circuit (ASIC).

In some embodiments, programmable ROSC circuitry200aand/or programmable delay path circuitry300amay include groups of logic gates formed on integrated circuit100a. In some embodiments, programmable ROSC circuitry200amay be configured to measure propagation delays in the integrated circuit100a. For example, in some embodiments, programmable ROSC circuitry200amay be configured to generate and measure oscillator signals that indicate propagation delays of programmable ROSC circuitry200a. In some embodiments, programmable ROSC circuitry200amay be configured to determine a central tendency and/or variance of propagation delay of programmable ROSC circuitry200a. In some embodiments, programmable delay path circuitry300amay be configured to measure and compare propagation delays of various types in the integrated circuit100ato a threshold delay amount. For example, in some embodiments, programmable delay path circuitry300amay be configured to propagate signals along a programmable delay path having configurable amounts of cell delay and/or wire delay and compare the propagated signals to reference signals to determine whether delays in the programmable delay path exceed a threshold delay amount. In some embodiments, programmable delay path circuitry300amay be configured to control an amount of cell delay and/or an amount of wire delay of the programmable delay path.

As described further herein, in some embodiments, programmable ROSC circuitry200aand/or programmable delay path circuitry300amay be programmed to operate according to control signals received via TAP110. In some embodiments, TAP110may be configured to transmit to programmable ROSC circuitry200aones of the input parameters112athat are configured to control operation of programmable ROSC circuitry200aand transmit to programmable delay path circuitry300aones of the input parameters112athat are configured to control operation of programmable delay path circuitry300a. For example, input parameters112aconfigured to control operation of programmable ROSC circuitry200amay include parameters that control generation of oscillator signals and/or measurement of the oscillator signals, and input parameters112aconfigured to control operation of programmable delay path circuitry300amay include parameters that control delays in the programmable delay path. In some embodiments, TAP100may be configured to receive output signals112bfrom programmable ROSC circuitry200aand programmable delay path circuitry300afor transmission outside of integrated circuit100a. For example, output signals112bmay indicate propagation delays measured by programmable ROSC circuitry200aand/or whether delay in signals propagated by programmable delay path circuitry exceed a threshold delay amount.

In some embodiments, TAP110may be configured as a parallel and/or serial port interface controller configured to transmit and/or receive encoded signals over a parallel and/or serial communication medium, such as one or more cables and one or more electrical connectors, to another circuit outside of the integrated circuit100a. For example, in some embodiments, TAP110may be compatible with a JTAG interface standard.

It should be appreciated that integrated circuit100amay include any combination of field-programmable and pre-programmed digital logic circuitry. It should also be appreciated that, according to various embodiments, only programmable ROSC circuitry200a(e.g., with or without TAP110) may be included, or only programmable delay path circuitry300a(e.g., with or without TAP110) may be included.

FIG.2is a block diagram illustrating an alternative exemplary integrated circuit100bincluding programmable ROSC circuitry200band programmable delay path circuitry300b, in accordance with some embodiments. In some embodiments, integrated circuit100bmay be configured in the manner described herein for integrated circuit100ain connection withFIG.1. For example, in some embodiments, programmable ROSC circuitry200band programmable delay path circuitry300bmay be configured in the manner described herein for programmable ROSC circuitry200aand programmable delay path circuitry300ain connection withFIG.1.

As shown inFIG.2, TAP110may be configured to receive input parameters112cfrom outside of integrated circuit100b, transmit ROSC parameter signals114ato programmable ROSC circuitry200band path parameters116ato programmable delay path circuitry300b, and transmit outputs112boutside of integrated circuit100b. For example, inFIG.2, input parameters112cinclude test reset (trst), test mode select (tms), test clock (tck), and test data in (tdi), and outputs112binclude test data out (tdo). For example, each of parameters trst, tms, tck, tdi, and tdo may have its own dedicated input/output (I/O) pin of integrated circuit100b. In some embodiments, test data in tdi may include serial data transmitted according to test clock tck and including control parameters for programmable ROSC circuitry200band/or programmable delay path circuitry300b. For example, the control parameters may be transmitted to programmable ROSC circuitry200bas ROSC parameter signals114aand/or to programmable delay path circuitry300bas path parameters116a. In some embodiments, test data out tdo may include serial data including outputs from programmable ROSC circuitry200band/or programmable delay path circuitry300bthat may be transmitted according to test clock tck. For example, the outputs may be received from programmable ROSC circuitry as output(s)114band/or from programmable delay path circuitry300bas output(s)116b.

As shown inFIG.2, in some embodiments, programmable ROSC circuitry200bmay include a ROSC controller210and one or more ROSCs230. In some embodiments, ROSC controller210may be configured to control operation of ROSC(s)230to generate output signals (e.g., oscillator signals), and ROSC controller210may be configured to measure propagation delays of ROSC(s)230based on the generated output signals. For example, as shown inFIG.2, ROSC controller210may be configured to transmit one or more ROSC control signals202and one or more ROSC select signals204to ROSC(s)230. In some embodiments, ROSC controller210may be configured to generate ROSC control signals202and ROSC select signals204based on ROSC parameter signals114areceived via TAP110. In the illustrated example, ROSC(s)230may be configured to generate, select, and transmit one or more ROSC output signals206to ROSC controller210based on ROSC control signals202and ROSC select signals204. In some embodiments, ROSC controller210may be configured to measure propagation delays of ROSC(s)230based on ROSC output signals206. In some embodiments, ROSC controller210may be configured to determine a central tendency and/or variance of propagation delays of ROSC(s)230. In some embodiments, ROSC controller210may be configured to transmit output(s)114bto TAP110, with output(s)114bindicating propagation delays (e.g., central tendency and/or variance of propagation delays) of ROSC(s)230.

As shown inFIG.2, in some embodiments, programmable delay path circuitry300bmay include a delay path controller310and one or more delay paths330. In some embodiments, delay path controller310may be configured to control operation of delay path(s)330to generate output signals, and delay path controller310may be configured to compare the received output signals to reference signals to determine whether propagation delays of the delay path(s)330exceed a threshold delay amount. For example, as shown inFIG.2, delay path controller310may be configured to transmit one or more path and/or clock control signals301and one or more path select signals306to delay path(s)330. In some embodiments, delay path controller310may be configured to generate path and/or clock control signals301and path select signals306based on path parameter signals116areceived via TAP110. In some embodiments, delay path(s)330may be configured to generate, select, and transmit path output signals308to delay path controller310based on path and/or clock control signals301and path select signals306. For example, in some embodiments, delay path(s)330may be configured to modify an amount of cell delay and/or wire delay based on path and/or clock control signals301. In some embodiments, delay path controller310may be configured to compare the received output signals308to one or more reference signals to determine whether delays in the output signals308exceed a threshold delay amount. In some embodiments, delay path controller310may be configured to transmit output(s)116bto TAP110, with output(s)116bindicating whether delays in output signals308exceed a threshold delay amount.

It should be appreciated that TAP110may be configured to transmit and/or receive different signals and/or a different number than shown inFIG.2, as embodiments described herein are not so limited.

FIG.3is a block diagram illustrating an exemplary ROSC controller210that may be included in integrated circuit100aor100b, in accordance with some embodiments. As shown inFIG.3, ROSC controller210may include a state machine212, a thermometer encoding circuit214, fast clock counter216, a ROSC counter218, a hit counter220, and a central tendency calculator222. In some embodiments, ROSC controller210may be configured to transmit ROSC control signals202and ROSC select signals204to ROSC(s)230, receive ROSC output206(e.g., one or more oscillator signals) from ROSC(s)230, and determine a central tendency and/or variance of propagation delay of ROSC(s)230using ROSC output206.

In some embodiments, state machine212may be configured to generate and transmit ROSC control signals202to ROSC(s)230using thermometer encoding circuit214. For example, in some embodiments, state machine212may be configured to transmit signals of ROSC parameter signals114athat are configured to control values of control signals202to thermometer encoding circuit214. In some embodiments, thermometer encoding circuit214may be configured to convert the received signals to parallel, thermometer encoded bits suitable for use by ROSC(s)230. For example, as described further herein, ROSC(s)230may have a plurality of ROSC stages each configured to receive a thermometer encoded bit to control a number of ROSC stages that are active during a delay measurement. In some embodiments, state machine212may be configured to receive ROSC select signals204among ROSC parameter signals114afrom TAP110and transmit ROSC select signals204to ROSC(s)230. In some embodiments, ROSC(s)230may generate and provide ROSC output206to ROSC controller210in response to receiving ROSC control signals202.

In some embodiments, state machine212may be configured to determine propagation delays of ROSC output206by using fast clock counter216and ROSC counter218to determine a pulse width of ROSC output206. For example, in some embodiments, fast clock counter216may be configured to receive, and increment according to pulses of, a fast clock signal (e.g., included in ROSC parameter signals114areceived from TAP110). In this example, ROSC counter218may be configured to receive, and increment according to pulses of, ROSC output206. Also in this example, state machine212may be configured to determine the pulse width of ROSC output206by dividing a count of fast clock pulses from fast clock counter216by a count of ROSC output206pulses from ROSC counter218.

In some embodiments, state machine212may be further configured to determine sampling parameters for determining propagation delays of ROSC output206using hit counter220. In some embodiments, state machine212may be configured to determine pre-scaler values for fast clock counter216and/or ROSC counter218based on a count of pulses of ROSC output206stored in hit counter220. For example, the count stored in hit counter220may indicate a number of pulses of ROSC output206counted during a measurement cycle, and state machine212may be configured to adjust pre-scaler values of fast clock counter216and/or ROSC counter218if less than a threshold number of pulses are stored in hit counter220. As described further herein, in some embodiments, fast clock counter216and/or ROSC counter218may be configured to increment at configurable frequencies with respect to pulses of the fast clock and/or ROSC output206, where the frequencies can be configured based on pre-scalar values. For example, in some embodiments, if less than a threshold number of pulses are stored in hit counter220after a measurement cycle, ROSC controller210may be configured to adjust the pre-scalar values to increase the number of counted pulses of ROSC output206during the next measurement cycle.

In some embodiments, state machine212may be configured to determine a central tendency and/or variance of propagation delay of ROSC(s)230using central tendency calculator222. For example, in some embodiments, state machine212may be configured to generate propagation delay measurements for a plurality of stages of ROSC(s)230and provide the propagation delay measurements to central tendency calculator222to calculate a central tendency of the propagation delay measurements of the plurality of stages, such as a mean, median, or mode of the propagation delay measurements. In some embodiments, state machine212may be further configured to provide to central tendency calculator222a second set of propagation delay measurements for the plurality of stages, and central tendency calculator222may be further configured to calculate a variance of the propagation delay measurements. For example, central delay calculator222may be further configured to determine a deviation of each propagation delay measurement from the mean (and/or other central tendency of) propagation delay, and calculate the variance using the mean and deviations. In some embodiments, central tendency calculator222may be alternatively or additionally configured to calculate a standard deviation of propagation delay.

FIG.4is a block diagram illustrating a plurality of exemplary programmable ROSCs230that may be included in integrated circuit100aor100b, in accordance with some embodiments. As shown inFIG.4, each of ROSCs230may be coupled to inputs of a multiplexer (MUX)240and configured to receive ROSC control signals202from ROSC controller210. MUX240may be configured to receive ROSC outputs206a-mfrom ROSCs230and ROSC select signals204from ROSC controller210and select among ROSC outputs206a-mto output as ROSC output206to ROSC controller210. In some embodiments, each ROSC230may be configured to generate a ROSC output206a-m, which may include oscillator signals generated in response to ROSC control signals202. In some embodiments, each ROSC230may be configured with different physical parameters. For example, in some embodiments, transistors of each ROSC230may be configured with different gate voltage thresholds.

FIG.5is a block diagram illustrating programmable ROSC230aofFIG.4, including a plurality of ROSC stages232a-n, in accordance with some embodiments. In some embodiments, each ROSC230of ROSCs230shown inFIG.4may be configured in the manner described herein for ROSC230a. In some embodiments, ROSC stages232a-nare each coupled to at least one other ROSC stage, and each may be configured to receive a respective control signal of ROSC control signals202from controller210. For example, inFIG.5, first ROSC stage232amay be configured to receive the Nth control signal (e.g., the Nth bit or group of bits) of ROSC control signals202, second ROSC stage232bmay be configured to receive the N−1th control signal (e.g., the N−1th bit or group of bits) of ROSC control signals202, and so on. Also shown inFIG.5, first ROSC stage232amay be configured to generate ROSC output206a, and the last ROSC stage232nmay be configured to receive a fixed control signal value, which is a zero value in the example ofFIG.5.

In some embodiments, ROSC stages232a-nmay be configured as a programmable delay path, and ROSC230amay be configured to propagate a signal (e.g., an oscillator signal) along the delay path. For example, as shown inFIG.5, each ROSC stage232a-nmay be programmable to transmit and/or receive signals to and/or from at least one other ROSC stage. In some embodiments, ROSC stages232a-nmay be switchable into and out of the delay path based on ROSC control signals202. For example, in some embodiments, when a ROSC stage is switched into the delay path, the ROSC stage may be configured to propagate signals received from at least one ROSC stage to at least one other ROSC stage, and when the ROSC stage is switched out of the delay path, the ROSC stage may be configured to block signals from at least one ROSC stage from reaching at least one other ROSC stage. In this example, switching ROSC stages of ROSC stages232a-ninto and out of the delay path may change an amount of propagation delay in signals propagated along the programmable delay path, which may be indicated in ROSC output206agenerated at first ROSC stage232a.

In some embodiments, subsequent ones of ROSC stages232a-n(e.g., ROSC stages232c-d) may be programmable into and out of communication with previous ROSC stages (e.g., ROSC stages232a-b). For example, in some embodiments, ROSC control signals202may be thermometer encoded. In this example, in some embodiments, a first state of ROSC control signals202may include an Nth control signal having a one bit and the remaining ROSC control signals202may have zero bits, and a second state of ROSC control signals202may include the Nth control signal having a one bit, the N−1th control signal having a one bit, and the remaining ROSC control signals202may have zero bits. In the example ofFIG.5, the first state of ROSC control signals202may be configured to switch ROSC stage232ainto the delay path and all other ROSC stages out of the delay path, and the second state of ROSC control signals202may be configured to switch ROSC stages232aand232binto the delay path and all other ROSC stages out of the delay path.

It should be appreciated that a different and/or multiple ROSC stage232may be configured to provide ROSC output206ato MUX240. It should also be appreciated that, in some embodiments, the fixed bit received at ROSC stage232nmay include a one, and/or may include a group of bits.

FIG.6is a circuit diagram illustrating a programmable ROSC230xthat may be included in ROSCs230ofFIG.4, in accordance with some embodiments. In some embodiments, ROSC230xmay be configured in the manner described herein for ROSC230aincluding in connection withFIG.5. For example, as shown inFIG.6, ROSC230xmay include ROSC stages232a′-n′, with each ROSC stage232a′-n′ being coupled to at least one other ROSC stage and configured to receive a respective control signal of ROSC control signals202. Also shown inFIG.6, ROSC stage232a′ is configured to generate ROSC output206a′ (e.g., for transmitting to MUX240), and ROSC stage232n′ is configured to receive a fixed control signal of zero value.

In some embodiments, ROSC stages232a′-n′ may be configured as a programmable delay path, and ROSC230xmay be configured to propagate an oscillator signal along the delay path. For example, inFIG.6, ROSC stage232a′ includes AND gates234aand234b, with a plurality of logic gates positioned in between, configured to propagate an oscillator signal. In this example, when the Nth control signal of ROSC control signal202is a one bit, AND gate234amay be configured to propagate a zero value through the plurality of logic gates to generate one bits at the inputs of AND gate234b, which may then generate a one bit at ROSC output206a′ as a rising edge of an oscillator signal at ROSC output206a′. Also in this example, when a one bit appears at ROSC output206a′, the one bits of ROSC output206a′ and the Nth control signal may cause AND gate234ato propagate a one value through the plurality of logic gates to generate a zero bit at one of the inputs of AND gate234b, which may then generate a zero bit at ROSC output206a′ as a falling edge of the oscillator signal at ROSC output206a′. In some embodiments, ROSC stage232a′ may be configured to continue generating rising and falling edges at ROSC output206a′ to generate pulses of the oscillator signal.

In some embodiments, ROSC stages232a′-n′ may be switchable into and out of the delay path based on ROSC control signals202. For example, inFIG.6, ROSC stage232b′ includes AND gate234cand a plurality of logic gates that are programmable based to transmit and receive an oscillator signal to and from ROSC stage232a′. For example, inFIG.6, when the N-lth control signal of ROSC control signals202is a zero bit, ROSC stage232b′ may be configured to provide the zero bit to ROSC stage232a′, which may block signals propagated by the plurality of logic gates of ROSC stage232b′ from reaching ROSC stage232a′. For example, the zero bit may keep a one bit as one of the inputs to AND gate234b, preventing the input of AND gate234bfrom changing when signals are propagated by the plurality of logic gates. In this example, ROSC stage232b′ may be switched out of the delay path. Alternatively, when the N−1th control signal of ROSC control signals202is a one bit, ROSC stage232b′ may be configured to provide the one bit to ROSC stage232a′, which may allow oscillator signals propagated through AND gate234cand the plurality of logic gates of ROSC stage232b′ to reach AND gate234bof ROSC stage232a′, thereby switching ROSC stage232b′ into the delay path. As shown inFIG.6, subsequent ROSC stages of ROSC230xmay be switchable into and out of the delay path in the manner described herein for ROSC stage232b′. It should be appreciated that, inFIG.6, ROSC stage232a′ may also be switchable into and out of the delay path at least in that ROSC stage232a′ may be configured not to produce a falling edge at ROSC output206a′ when the Nth control signal of ROSC control signals202is a zero bit.

In the example ofFIG.6, switching ROSC stages of ROSC stages232a′-n′ into and out of the delay path may change an amount of propagation delay in oscillator signals propagated along the programmable delay path, which may be indicated in ROSC output206a′ generated at first ROSC stage232a′. For example, as described above, when the Nth and N−1th control signals of ROSC control signal202are one and zero bits, respectively, rising and falling edges of the oscillator signal may be generated at ROSC output206a′ based on when the oscillator signal propagates through AND gates234aand234band other logic gates of ROSC stage232a′. Accordingly, propagation delays of AND gates234aand234band other logic gates of ROSC stage232a′ contribute to the time elapsed between the rising and falling edges of the oscillator signal. Also described above, when the Nth and N−1th control signal of ROSC control signals202are both one bits, rising and falling edges of the oscillator signal may be generated at ROSC output206a′ based on when the oscillator signal propagates through the AND gates234a,234b, and234cand other logic gates of ROSC stages232a′ and232b′. Accordingly, propagation delays of AND gates234a,234b, and234cand other logic gates of ROSC stages232a′ and232b′ contribute to the time elapsed between the rising and falling edges of the oscillator signal.

FIG.7is a flow diagram illustrating an exemplary method700of determining propagation delay of an integrated circuit, in accordance with some embodiments. In some embodiments, method700may be performed using programmable ROSC circuitry200aand/or200bas described herein including in connection withFIGS.1-5. For example, in some embodiments, method700may be performed using a ROSC controller coupled to one or more programmable ROSCs. As shown inFIG.7, method700may include determining delay sample parameters for measuring ROSC pulses at step720, determining propagation delay of a ROSC stage of one or more ROSCs at step740, and determining a central tendency and/or variance of propagation delay of the ROSC(s) at step760.

In some embodiments, determining delay sample parameters at720may include determining whether at least a threshold number of ROSC output pulses has been received during a first measurement cycle. For example, in some embodiments, a ROSC controller may transmit ROSC control signals to one or more ROSCs, receive an output from the ROSC(s), and count the number of pulses of the ROSC output over the course of a measurement cycle (e.g., until a fast clock counter of the ROSC controller reaches a predetermined limit. In some embodiments, upon determining that less than the threshold number of ROSC output pulses were counted during the first measurement cycle, method700may include adjusting the sample parameters. For example, in some embodiments, the ROSC controller may adjust pre-scalar values of the fast clock counter and/or a ROSC output counter that counts pulses of the ROSC output and run a second measurement cycle. In this example, step720of determining delay sample parameters may be repeated for the second measurement cycle. It should be appreciated that some embodiments omit step720and proceed to step740.

In some embodiments, determining propagation delay of a ROSC stage of one or more programmable ROSCs at step740may include receiving a ROSC output from the ROSC stage, counting a number of pulses of the ROSC output over a measurement cycle, and counting a number of pulses of a fast clock over the measurement cycle. For example, in some embodiments, a ROSC controller may divide the number of fast clock pulses counted during the measurement cycle by ROSC output pulses counted during the measurement cycle to determine the pulse width of the ROSC output in fast clock pulses. In this example, the frequency of the fast clock may be known, such that the pulse width of the ROSC output in fast clock pulses can be converted to a time in seconds, such as by the ROSC controller and/or by another device communicatively coupled to the ROSC controller. In some embodiments, step740may be repeated for multiple ROSC stages or each ROSC stage of a ROSC. In some embodiments, step720may be performed for some or each of the ROSC stages before step740is performed for the ROSC stage. In some embodiments, the propagation delay determined for a previous ROSC stage may be used to determine the propagation delay of a subsequent ROSC stage. For example, a ROSC having ROSC stages A and B that are switchable into and out of a delay path and configured to receive thermometer encoded control signals, the propagation delay of the delay path including ROSC stage A may be determined first, followed by determining the propagation delay of a delay path including ROSC stages A and B, and subtracting the first propagation delay from the second to obtain the propagation delay of ROSC stage B.

In some embodiments, determining the central tendency and/or variance of propagation delay of the ROSC(s) at step760may include calculating the central tendency and/or variance using propagation delays determined at step740. In some embodiments, step760may be performed once step740has been performed for multiple ROSC stages of a ROSC. For example, in some embodiments, determining the central tendency of propagation delay of the ROSC(s) may include determining a mean propagation delay of the stages for which step740was performed. In some embodiments, step740may be performed once (e.g., for each ROSC stage) prior to determining the central tendency of propagation delay and again (e.g., for each ROSC stage) after determining the central tendency of propagation delay. For example, in some embodiments, step760may include determining a variance of propagation delay using deviations of propagation delays of each ROSC stage from the central tendency (e.g., mean).

FIG.8is a flow diagram illustrating an alternative exemplary method800of determining propagation delay of an integrated circuit, in accordance with some embodiments. As shown inFIG.8, method800may include determining delay sample parameters for measuring ROSC pulses at step820, determining propagation delay of a ROSC stage of one or more ROSCs at step840, and determining a central tendency and/or variance of propagation delay of the ROSC(s) at step860, which may be performed in the manner described herein for steps720,740, and760of method700in connection withFIG.7, and as described further below.

As shown inFIG.8, determining delay sample parameters for measuring ROSC pulses at step820may include initializing the delay sample parameters at step822. In some embodiments, initializing the delay sample parameters at step822may include initializing pre-scaler values of a fast clock counter and/or ROSC counter of the ROSC controller. For example, in some embodiments, the pre-scaler values may determine how many pulses of the fast clock pass per increment of the fast clock counter and/or how many pulses of the ROSC output pass per increment of the ROSC counter. In some embodiments, the pre-scaler values may be set such that, initially, a small number of pulses of the fast clock pass per increment of the fast clock counter and a large number of pulses of the ROSC output pass per increment of the ROSC counter. In some embodiments, the pre-scaler values may be set based on input parameters received through a TAP (e.g., TAP110).

In some embodiments, step820may also include sampling the ROSC output from the ROSC(s) at step824. For example, in some embodiments, sampling the ROSC output may include incrementing the ROSC counter according to pulses of the ROSC output using delay sample parameters (e.g., parameters initialized at step822and/or adjusted at step828). In this example, sampling the ROSC output may be performed for one measurement cycle, such as until the fast clock counter reaches a predetermined count limit and/or the ROSC counter reaches a predetermined count limit.

In some embodiments, step820may also include determining whether a count of ROSC output pulses sampled during a measurement cycle is at least equal to a count threshold at step826. In some embodiments, step826may include comparing a value stored in a hit counter of the ROSC controller following a measurement cycle to a count threshold. For example, in some embodiments, the count threshold may be received through a TAP. In some embodiments, in response to determining that the count of ROSC output pulses is not at least equal to the count threshold, step820may also include adjusting the delay sample parameters at step828. For example, in some embodiments, the ROSC controller may change pre-scaler values of the fast clock counter and/or ROSC counter, such as by increasing the number of pulses of the fast clock that pass per increment of the fast clock counter and/or decreasing the number of pulses of the ROSC output that pass per increment of the ROSC counter. The inventors recognized that having at least a threshold count of ROSC output pulses per measurement cycle (e.g., over 1000 pulses in some applications) can ensure that propagation delay calculations rely on a large enough set of delay measurements to yield accurate results. In some embodiments, the ROSC counter pre-scaler values may be adjusted until they reach a minimum before adjusting the fast clock counter pre-scaler values, which may increase the number of ROSC counter pulses counted during a measurement cycle without increasing the duration of the measurement cycle.

In some embodiments, after adjusting the delay sample parameters at step828, method800may return to sampling the ROSC output at step824using the adjusted sample delay parameters. In some embodiments, if the count of ROSC output pulses is greater than or equal to the count threshold, method800may proceed to determining propagation delay of a ROSC stage at step840.

As shown inFIG.8, determining propagation delay of a ROSC stage of one or more ROSCs at step840may include sampling the ROSC output at step842. In some embodiments, sampling the ROSC output at step842may include incrementing the ROSC counter according to pulses of the ROSC output using delay sample parameters initialized and/or adjusted during step820. In this example, sampling the ROSC output may be performed for one measurement cycle, such as until the fast clock counter reaches a predetermined count limit and/or the ROSC counter reaches a predetermined count limit.

In some embodiments, step840may also include determining the propagation delay of the ROSC stage at step844, which may be performed in the manner described herein for step740including in connection withFIG.7. In some embodiments, step840may also include determining whether the central tendency of propagation delay of the ROSC(s) has been previously determined at step846. For example, in some embodiments, step840may be performed multiple times for the same or multiple ROSC stages, with a first iteration of step840resulting in calculating a central tendency of propagation delay (e.g., at step864), and a with the second iteration of step840resulting in calculating a variance of the propagation delay (e.g., at step866). In some embodiments, in response to determining that the central tendency of propagation delay has been previously determined, method800may proceed to determining the difference between the central tendency of propagation delay and the propagation delay determined for the ROSC stage at step848. For example, in some embodiments, the difference between the central tendency of propagation delay and the propagation delay determined at step844may be used to determine a variance of propagation delay (e.g., at step866).

In some embodiments, in response to determining that the central tendency of propagation delay has not been previously determined, and/or following step848, method800may proceed to determining whether there are additional ROSC stages for determining propagation delay at step850. In some embodiments, determining whether there are additional ROSC stages may include determining whether all ROSC stages have been sampled. For example, in some embodiments, in response to determining that one or more ROSC stages have not been sampled, method800may return to and/or repeat step820and/or step840for the ROSC stage(s) that have not been sampled. In this example, steps820and/or840may be performed for a single ROSC stage at a time. In some embodiments, the determination at step850may take into account input parameters received from the TAP indicating which ROSC stages should be sampled. For example, in some embodiments, input parameters received from the TAP may indicate that only one or a subset of ROSC stages should be sampled during performance of method800. In some embodiments, upon determining that there are no remaining ROSC stages to sample, method800may proceed to determining a central tendency and/or variance of propagation delay at step860.

As shown inFIG.8, determining a central tendency and/or variance of propagation delay of the ROSC(s) at step860may include determining whether the central tendency of propagation delay has been previously determined at step862. For example, in some embodiments, in response to determining that the central tendency of propagation delay was not previously determined, method800may proceed to determining the central tendency of propagation delay at step864. Alternatively, in some embodiments, in response to determining that the central tendency of propagation delay was previously determined, method800may proceed to determining the variance of propagation delay at step866. In some embodiments, determining the central tendency and/or variance of propagation delay may be performed in the manner described herein for step760including in connection withFIG.7. In some embodiments, after determining the central tendency of delay at step864, method800may return to and/or repeat steps820,840, and/or860. For example, in some embodiments, steps820and860may be performed (e.g., repeated) for each ROSC stage to be sampled (e.g., sampled in the previous iteration of steps820,840, and860). In some embodiments, method800may further include outputting a central tendency and/or variance of propagation delay to the TAP.

FIG.9is a block diagram illustrating an exemplary delay path controller310that may be included in integrated circuit100aor100b, in accordance with some embodiments. As shown inFIG.9, delay path controller310includes a state machine312, a clock divider314, a clock controller316, a comparator318, and a hit counter320. In some embodiments, delay path controller310may be configured to generate and/or transmit path and/or clock control signals301and path select signals306to delay paths330based on path parameters116areceived from TAP110. For example, as shown inFIG.9, path and/or clock control signals301can include path clock control signals302, path delay control signals304, and path shift control signals305. In some embodiments, delay path controller310may be configured to receive path output308from the delay paths330, compare path output308to one or more reference signals, and output results of the comparison(s) to TAP110as output(s)116b.

In some embodiments state machine312may be configured to transmit path delay control signals304, path shift control signals305, and path select control signals306to delay paths330based on path parameters116areceived from TAP110. For example, in some embodiments, state machine312may be configured to transmit path delay control signals304, path shift control signals305, and path select control signals306to delay paths330in the manner the signals are received from TAP110in input parameters116a. In some embodiments, state machine312may be further configured to generate one or more reference signals for comparator318to compare with path output308. For example, in some embodiments, the reference signal(s) may include delayed clock signals received from clock divider314and/or clock controller316, and/or path shift signals received from TAP110.

In some embodiments, clock divider314and clock controller316may be configured to generate and transmit path clock control signals302to delay paths330based on control signals of path parameters116areceived from TAP110. For example, in some embodiments, clock divider314may receive a clock divider control signal among path parameters116aand divide a clock signal based on the clock divider control signal. In some embodiments, clock divider314may be configured to provide the divided clock signal to state machine312for use in generating reference signals. In some embodiments, clock controller316may be configured to output control signals for controlling clock delay tuners of delay paths330based on clock delay control signals received among input parameters116a.

In some embodiments, comparator318may be configured to receive path output308from delay paths330and generate an output indicating a comparison between path output308and one or more reference signals. For example, in some embodiments, comparator318may be further configured to receive the reference signal(s) from state machine312. In some embodiments, comparator318may be configured to determine whether a delay amount of and/or indicated by path output308is greater than a threshold delay amount. For example, in some embodiments, comparator318may be configured to generate a first output when the delay amount of and/or indicated by path output308is greater than the delay amount of and/or indicated by the reference signal(s) and a second output when the delay amount of and/or indicated by path output308is less than or equal to the delay amount of and/or indicated by the reference signal(s).

In some embodiments, hit counter320may be configured to count a number of measurement cycles during which a delay amount of and/or indicated by path output308is less than or equal to (or, alternatively, greater than) a threshold delay amount. For example, in some embodiments, comparator318may be configured to output an indication of whether the delay amount of and/or indicated by path output308is less than or equal to and/or or greater than the threshold delay amount to hit counter320, which may be configured to increment for each indication that the threshold delay amount is not (or, alternatively is) exceeded. In some embodiments, hit counter320may be configured to output its count to TAP110among output(s)116b).

It should be appreciated that, in some embodiments, state machine312may be alternatively or additionally configured to provide outputs among output(s)116b.

FIG.10is a block diagram illustrating a plurality of exemplary programmable delay paths330that may be included in integrated circuit100aor100b, in accordance with some embodiments. As shown inFIG.10, each programmable delay path330may be configured to receive path clock control signals302, path delay control signals304, and path shift control signals305from delay path controller310, and each may be coupled to a MUX340to provide path outputs308a-mas inputs to MUX340. In some embodiments, MUX340may be configured to receive path select signals306from delay path controller310and select from among path outputs308a-mto provide to delay path controller310as path output308. In some embodiments, each programmable delay path330may be configured to generate path outputs308a-308mbased on path clock control signals302, path delay control signals304, and path shift control signals305. For example, in some embodiments, programmable delay paths330may be configured to propagate shift control signals using a clock delay based on path clock control signals302and cell and/or wire delays based on path delay control signals304. In some embodiments, each programmable delay path330may have transistors with channel widths that are different from channel widths of transistors of the other programmable delay paths330.

FIG.11is a block diagram illustrating programmable delay path330aofFIG.10, including input clock delay tuners332a-p, output clock delay tuners334a-qand path tuners338a-n, in accordance with some embodiments. As shown inFIG.11, delay path330amay also include input flip flops336a-band output flip flop336c. In some embodiments, input flip flops336a-bmay be configured to receive clock signals from input clock delay tuners332a-pand path shift control signals305aand305bfrom delay path controller310and provide the path shift control signals305aand305bto path tuners338a-nand output flip flop336cbased on the clock signals. In some embodiments, output flip flop336cmay be further configured to receive clock signals from output clock delay tuners334a-q.

In some embodiments, delay path330amay be configured to generate path output308abased on clock control signals302aand clock control signals302b. For example, in some embodiments, input clock delay tuners332a-332pmay be configured to receive respective control signals (e.g., bits or groups of bits) of clock control signals302aand control a delay between when path shift control signals305aare received at input flip flops336a-band when path shift control signals305areach output flip flop336cvia path tuners338a-nbased on clock control signals302a. In this example, input clock delay tuners332a-332pmay be configured to add a delay to clock signals (e.g., received from path delay controller310) provided to input flip flops336a-b. Alternatively or additionally, in some embodiments, output clock delay tuners334a-qmay be configured to receive respective control signals (e.g., bits or groups of bits) of clock control signals302band control a delay between when path shift control signals305aare received at output flip flop336cand when output flip flop336cgenerates path output308a. For example, in some embodiments, output clock delay tuners334a-qmay be configured to add a delay to clock signals (e.g., the same clock signals provided to input clock delay tuners332a-p) provided to output flip flop336c.

In some embodiments, delay path330amay be further configured to generate path output308abased on the received path shift signals and path delay control signals304. For example, in some embodiments, path tuners338a-nmay be configured to receive respective control signals (e.g., bits or groups of bits) of path delay control signals304and add an amount of cell delay and/or wire delay based on path delay control signals304. In some embodiments, path tuners338a-nmay be configured to add programmable proportions of cell delay and/or wire delay to the path shift signals. Alternatively or additionally, in some embodiments, path tuners338a-nmay be configured to output versions of the path shift signals propagated using transistors having different voltage thresholds based on path delay control signals304. In some embodiments, each path tuner338a-nmay be individually programmable (e.g., via respective control signals of path delay control signals304) to provide add different amounts of cell delay and/or wire delay and/or to output path shift signals propagated using transistors having different voltage thresholds.

FIG.12is a block diagram illustrating input clock delay tuner332aofFIG.11, in accordance with some embodiments. In some embodiments, each input clock delay tuner332a-pand/or output clock delay tuner334a-qmay be configured in the manner described herein for input clock delay tuner332a.

In some embodiments, input clock delay tuner332amay be configured to propagate a path clock signal (e.g., from delay path controller310) along one or more sub-paths to add delay to the path clock signal. As shown inFIG.12, clock delay tuner332amay include a plurality of sub-paths350, including sub-paths350a-b, each sub-path350including one or more logic gates352, and each sub-path350configured to receive the path clock signal. In some embodiments, each sub-path350may be configured to add a different amount of cell delay to the path clock signal than the other sub-paths350. For example, in some embodiments, each sub-path350may have a different number of logic gates352than the other sub-paths350.

In some embodiments, clock delay tuner332amay be further configured to output a version of the path clock signal having an amount of delay based on clock control signals302. As shown inFIG.12, clock delay tuner332amay include a MUX354configured to receive signals from each sub-path350and a respective control signal of path clock control signals302(e.g., the Pth group of bits of path clock control signal302a). For example, in some embodiments, MUX354may be configured to output one of the signals received from sub-paths350based on the respective path clock control signal received from delay path controller310.

FIG.13is a block diagram illustrating path tuner338aofFIG.11, in accordance with some embodiments. In some embodiments, each path tuner338a-nmay be configured in the manner described herein for path tuner338a. In some embodiments, path tuner338amay be configured to propagate a path shift signal from input flip flop336aand/or336balong one or more sub-paths, adding programmable amounts of cell and/or wire delay to the path shift signal and using logic gates having transistors with a selected voltage threshold. As shown inFIG.13, path tuner338amay include cell and/or wire delay tuner360and voltage threshold tuner370. In some embodiments, cell and/or wire delay tuner360may be configured to receive a first portion and voltage threshold tuner370may be configured to receive a second portion of the respective (e.g., Nth) control signal of path delay control signals304.

Cell and/or wire delay tuner360may be configured to add programmable amounts of cell and/or wire delay to the received path shift signal based on path delay control signals304. As shown inFIG.13, cell and/or wire delay tuner360may include a plurality of sub-paths362, including sub-paths362a-d, each sub-path362including one or more logic gates364(e.g., inverters), and each sub-path362configured to receive the path shift signal. In some embodiments, some sub-paths362may be configured to add different amounts of cell and/or wire delays to the path shift signal than other sub-paths362. For example, as shown inFIG.13, sub-paths362aand362bmay have different numbers of logic gates362. In this example, a sub-path with fewer logic gates may add more wire delay than cell delay to the path shift signal, and a sub-path with more logic gates may add more cell delay than wire delay to the path shift signal. Also shown inFIG.13, cell and/or wire delay tuner360may include multiplexers (MUXes)366a-d, which may be each configured to receive path shift signals from respective pairs of the sub-paths362and output one of the path shift signals based on path delay control signals304.

In some embodiments, voltage threshold tuner370may be configured to selectively output path shift signals from cell and/or wire delay tuner360propagated by logic gates having transistors with different voltage thresholds based on path delay control signals304. For example, in some embodiments, logic gates364of sub-paths362a-bmay have transistors with a first voltage threshold and logic gates364of sub-paths362c-dmay have transistors with a second voltage threshold different from the first voltage threshold.

FIG.14is a flow diagram of an exemplary method1400of determining path delay of an integrated circuit, in accordance with some embodiments. In some embodiments, method1400may be performed using programmable delay path circuitry300aand/or300bas described herein including in connection withFIGS.1-2and9-13. For example, in some embodiments, method1400may be performed using a path delay controller coupled to one or more programmable delay paths. As shown inFIG.14, method1400may include configuring cell delay and wire delay of one or more programmable delay paths at step1402and comparing one or more delay path signals to one or more reference signals at step1404.

In some embodiments, configuring cell delay and wire delay of the programmable delay path(s) at step1402may include a delay path controller transmitting a plurality of control signals to the programmable delay path(s). For example, in some embodiments, the plurality of control signals may include clock delay control signals, path delay control signals, and/or path shift control signals. In some embodiments, the delay path controller may receive and/or generate the control signals in response to path parameters received via a TAP. In some embodiments, the programmable delay path may generate the delay path signal(s) based on the received control signals. For example, in some embodiments, the programmable delay path may add an amount of cell delay and/or an amount of wire delay to the path based on the received control signals. In some embodiments, the plurality of control signals may include path select signals for selecting a delay path signal from among a plurality of delay path outputs from a plurality of programmable delay paths. In some embodiments, the delay path controller may receive the delay path signal(s) from the programmable delay paths for comparison to the reference signal(s) at step1404.

In some embodiments, comparing the delay path signal(s) to the reference signal(s) may include the delay path controller generating a reference clock signal and/or a reference path shift signal and comparing the delay path signal(s) to the reference clock and/or path shift signal. For example, in some embodiments, comparing the delay path signal(s) to the reference clock and/or path shift signal may generate an output indicating an amount of delay in the delay path signal(s). In this example, the output may indicate whether the amount of delay in the delay path signal(s) is less than or equal to (or, alternatively, greater than) a threshold delay amount. In some embodiments, steps1702and1704may be repeated for a plurality of measurement cycles and a hit counter of the delay path controller may count a number of measurement cycles in which the amount of delay in the delay path was less than or equal to (or, alternatively, greater than) the threshold delay amount. In some embodiments, the delay path controller may output the number from the hit counter via a TAP.

Various aspects of the apparatus and techniques described herein may be used alone, in combination, or in a variety of arrangements not specifically discussed in the embodiments described in the foregoing description and is therefore not limited in its application to the details and arrangement of components set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments.

Use of ordinal terms such as “first”, “second”, “third”, etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having a same name (but for use of the ordinal term) to distinguish the claim elements.

Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including”, “comprising”, “having”, “containing” or “involving” and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.

The use of “coupled” or “connected” is meant to refer to circuit elements, or signals, that are either directly linked to one another or through intermediate components.

The terms “approximately”, “substantially,” and “about” may be used to mean within ±20% of a target value in some embodiments, within ±10% of a target value in some embodiments, within ±5% of a target value in some embodiments, and within ±2% of a target value in some embodiments. The terms “approximately” and “about” may include the target value.