Patent ID: 12237029

DETAILED DESCRIPTION

Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

FIG.1depicts a schematic diagram of a testing system100according to one embodiment of the present disclosure. In some embodiments, please refer toFIG.1, the testing system100includes a memory chip110and a test equipment120. In some embodiments, the test equipment120is coupled to the memory chip110.

In some embodiments, the test equipment120is configured to generate a first signal and an active command. The test equipment120is configured to input the first signal to a memory chip. The test equipment120is configured to put the memory chip110into a self-refresh mode according to the first signal. The test equipment120is configured to input the active command to test the memory chip110so as to generate a first testing result according to the first signal.

Then, the test equipment120is configured to adjust a bandwidth of the first signal to generate a second signal so as to input to the memory chip110. The test equipment120is configured to put the memory chip110into the self-refresh mode according to the second signal. The test equipment120is configured to input the active command to test the memory chip110so as to generate a second testing result according to the second signal. The test equipment120is configured to calculate a self-refresh rate of the memory chip110according to the first testing result and the second testing result.

In some embodiments, the memory chip110includes a double data rate (DDR) synchronous dynamic random access memory (SDRAM).

In some embodiments, each of the first signal and the second signal includes a clock enable signal (CKE signal).

In some embodiments, the memory chip110includes an oscillator111. The oscillator111is configured to observe a data state of data stored in the memory chip110when the memory chip110receives the active command.

In some embodiments, in order to facilitate the understanding of a testing system100shown inFIG.1. Please refer toFIG.1toFIG.4B.FIG.2depicts a flow chart of a testing method200according to one embodiment of the present disclosure.FIG.3depicts a schematic diagram of signal adjustment of signals of a testing system100according to one embodiment of the present disclosure. In some embodiments, the testing method200for includes step210to step270, which will be described as shown below.

In step210, a first signal is input to a memory chip. In some embodiments, please refer toFIG.1toFIG.3, a first signal CKE1is input to a memory chip110by the test equipment120of the testing system100.

In step220, the memory chip is put into a self-refresh mode according to the first signal. In some embodiments, please refer toFIG.1toFIG.3, the memory chip110is put into a self-refresh mode according to the first signal CKE1.

In some embodiments, the memory chip110is configured to generate a first self-refresh command SF1to enter a first self-refresh procedure under the self-refresh mode when a first voltage level of the first signal CKE1is at a low electrical potential.

In step230, an active command is input to test the memory chip so as to generate a first testing result according to the first signal. In some embodiments, please refer toFIG.1toFIG.3, an active command A1is input to test the memory chip110so as to generate a first testing result according to the first signal CKE1. It should be noted that a time of the active command A1must be when the first signal CKE1is at a high electrical potential.

In some embodiments, a first time difference T1is formed between the first self-refresh command SF1and the active command A1.

Then, if the first time difference T1is less than a refresh cycle time (tRFC) of the memory chip110, the first testing result is that the memory chip110is in a data failure state. In some embodiments, the first time difference T1also needed to be greater than a minimum time (tXPmin) to leave a power down mode of the of the memory chip110.

Furthermore, if the first time difference T1is greater than the refresh cycle time (tRFC) of the memory chip110, the first testing result is that the memory chip110is in a data pass state.

In step240, a bandwidth of the first signal is adjusted to generate a second signal so as to input to the memory chip. In some embodiments, please refer toFIG.1toFIG.3, a bandwidth of the first signal CKE1is adjusted to generate a second signal (e.g. a first clock enable signal CKE(n) or a second clock enable signal CKE(m)) so as to input to the memory chip110by the test equipment120of the testing system100. It should be noted that each of n and m is a positive integer and m is greater than n.

In some embodiments, the bandwidth of the first signal CKE1is adjusted to generate the second signals (e.g. the first clock enable signal CKE(n) and the second clock enable signal CKE(m)) one thousand times. In other words, step240is repeated one thousand times. It should be noted that each of adjusted bandwidths of the second signals (e.g. the first clock enable signal CKE(n) and the second clock enable signal CKE(m)) is different each time.

In step250, the memory chip is put into the self-refresh mode according to the second signal. In some embodiments, please refer toFIG.1toFIG.3, the memory chip110is put into the self-refresh mode according to the second signal (e.g. the first clock enable signal CKE(n) and the second clock enable signal CKE(m)) by the test equipment120of the testing system100. In some embodiments, following the aforementioned step240, step250can be repeated one thousand times.

In some embodiments, a time difference T(n) is formed between the first self-refresh command SF1and the active command A(n). It should be noted that a time of the active command A(n) must be when the first clock enable signal CKE(n) is at a high electrical potential.

In some embodiments, please refer toFIG.1toFIG.3, the time difference T(n) is greater than the refresh cycle time (tRFC) of the memory chip110, the testing result is that the memory chip110is in the data pass state.

In step260, the active command is input to test the memory chip so as to generate a second testing result according to the second signal. In some embodiments, the active command T(n) is input to test the memory chip110so as to generate a second testing result according to the second signal (e.g. the second clock enable signal CKE(m)). In some embodiments, following the aforementioned step240and step250, step260can be repeated one thousand times.

In some embodiments, when the bandwidth of the first signal CKE(1) is adjusted to second clock enable signal CKE(m) the test equipment120of the testing system100, the memory chip110is configured to generate a second self-refresh command SF2to enter a second self-refresh procedure under the self-refresh mode when a second voltage level of the second signal (e.g. the second clock enable signal CKE(m)) is at a low electrical potential.

In some embodiments, please refer toFIG.1toFIG.3, a second time difference T(m) is formed between the second self-refresh command SF2and the active command A(m).

Then, if the second time difference T(m) is less than the refresh cycle time of the memory chip110, the second testing result is that the memory chip110is in the data failure state.

Furthermore, if the second time difference T(m) is greater than the refresh cycle time (tRFC) of the memory chip110, the second testing result is that the memory chip110is in the data pass state.

In step270, a self-refresh rate of the memory chip is calculated according to the first testing result and the second testing result. In some embodiments, please refer toFIG.1toFIG.2, a self-refresh rate of the memory chip110is calculated according to the first testing result and the second testing result by the test equipment120of the testing system100.

In some embodiments, please refer toFIG.1,FIG.2, andFIG.4A.FIG.4Adepicts a schematic diagram of testing results timing in a high temperature range according to one embodiment of the present disclosure.

In some embodiments, a self-refresh period I1is formed between the first self-refresh command SF1and the second self-refresh command SF2. The self-refresh period I1includes a first time interval I11and a second time interval I12. The first time interval I11is that the memory chip110is in the data failure state “F” in a high temperature range. The second time interval I12is that the memory chip110is in the data pass state “P” in a high temperature range. In some embodiments, the high temperature range is between 70° C. and 80° C., or above 80° C.

In some embodiments, number of testing results is one thousand times. It should be noted that number of testing results is not limited to embodiment of figure.

In some embodiments, the test equipment120is further configured to calculate the self-refresh rate of the memory chip110according to the first time interval I11and the second time interval I12of the self-refresh period I1in a low temperature range.

In some embodiments, please refer toFIG.1,FIG.2, andFIG.4B.FIG.4Bdepicts a schematic diagram of testing results timing in a low temperature range according to one embodiment of the present disclosure.

In some embodiments, a self-refresh period I1is formed between the first self-refresh command SF1and the second self-refresh command SF2. The self-refresh period I1includes a third time interval I13and a fourth time interval I14. The third time interval I13is that the memory chip110is in the data failure state “F” in a low temperature range. The fourth time interval I14is that the memory chip110is in the data pass state “P” in a low temperature range. In some embodiments, the lower temperature range is about −20° C., or a temperature that the memory chip110can withstand.

In some embodiments, number of testing results is one thousand times. It should be noted that number of testing results is not limited to embodiment of figure.

In some embodiments, the test equipment120is further configured to calculate the self-refresh rate of the memory chip110according to the third time interval I13and the fourth time interval I14of the self-refresh period I1in a low temperature range.

Based on the above embodiments, the present disclosure provides a testing system and a testing method to calculate a self-refresh rate of a memory chip at any temperature range so as to reduce time cost.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims.