Patent ID: 12218145

DETAILED DESCRIPTION

Various embodiments of the present disclosure are described in detail with reference to the drawings. It should be noted that the relative arrangement of components and steps, numerical expressions, and numerical values set forth in the embodiments may not limit the scope of the present disclosure unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative, which may not limit the present disclosure and its application or use.

Techniques, methods and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, the techniques, methods and equipment should be considered as a part of the specification.

In all exemplary embodiments shown and discussed herein, any specific values should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

It should be noted that similar reference numerals and letters indicate similar items in the following drawings. Therefore, once an item is defined in one drawing, there is no need to discuss it further in subsequent drawings.

Referring toFIGS.1-3,FIG.1illustrates a planar structural schematic of a display panel according to various embodiments of the present disclosure;FIG.2illustrates a local film-layer cross-sectional structural schematic at a region A inFIG.1; andFIG.3illustrates a local film-layer cross-sectional structural schematic at a region B inFIG.1. It should be understood thatFIGS.2-3may each exemplarily illustrate a local film-layer schematic of a first transistor and a second transistor. The first transistor and the second transistor may be illustrated together for description to clearly illustrate the technical features of the first transistor and the second transistor, which may not indicate the actual disposing positions of the first transistor and the second transistor in the display panel. During an implementation, the disposing positions and the connection relationship of the first transistor and the second transistor may be determined by the layout of the drive circuit and the pixel circuit. A display panel000provided in one embodiment may include a base substrate10, first transistors20, and second transistors30. The first transistors20and the second transistors30may be formed on the base substrate10. The first transistor20may include a first active layer201, a first gate electrode20G, and a first source electrode20S, and a first drain electrode20D, where the first active layer201may include silicon. The second transistor30may include a second active layer301, a second gate electrode30G, a second source electrode30S, and a second drain electrode30D, where the second active layer301may include an oxide semiconductor. Optionally, in one embodiment, the first transistor20and the second transistor30may both be top gate transistors as an example for description. In an implementation, the first transistor20and the second transistor30may also be other bottom gate transistors.

The length of the channel region of the first transistor20is L1. Along a direction Z perpendicular to the base substrate10, the distance between the first gate electrode20G and the first active layer201is D1, and the first area S1=L1×D1.

The length of the channel region of the second transistor30is L2. Along the direction Z perpendicular to the base substrate10, the distance between the second gate electrode30G and the second active layer301is D2, and the second area S2=L2×D2; where S1<S2.

The display panel000may include pixel circuits40and a drive circuit50which provides drive signals for the pixel circuits40. The first transistor20and the second transistor30may be transistors in the drive circuit, that is, the drive circuit50may include the first transistor20or the second transistor30. Furthermore, the first transistor20and the second transistor30may also be transistors in the pixel circuit, that is, the pixel circuit may include the first transistor20or the second transistor30. If the second transistor30is in the pixel circuit, the second transistor may be a drive transistor or a switch transistor.

In some optional embodiments, the drive circuit50may include the second transistor30, the pixel circuit40may include the first transistor20, or the drive circuit50may include the first transistor20.

For example, the display panel000of one embodiment may include the pixel circuits40and the drive circuit50which provides drive signals for the pixel circuits40. Optionally, the drive circuit50may be a gate drive circuit for providing scan drive signals for the scan lines G of the display panel000. The gate drive circuit may be formed on the base substrate10, for example, disposed at the left edge of the display panel100(it should be understood thatFIG.1of one embodiment only exemplarily illustrates a structure of the drive circuit50on the display panel as a block diagram which may not be limited according to various embodiments of the present disclosure, and the connection structure of the drive circuit50may not be limited in one embodiment), the right edge, only on a single edge of the display panel, or other position of the display panel. The drive circuit50may also be a demultiplexer circuit (not shown inFIGS.1-3, the demultiplexer circuit may be located between a bonding region and the display region of the display panel000), which is configured to demultiplex data signals from the drive chip at the bonding region or a flexible circuit board to a plurality of corresponding data lines S. The display panel000may include a plurality of display pixels400, and each display pixel400may include a pixel circuit40. The scan lines G and data lines S of the display panel000may be crossed and insulated to define the regions of the display pixels400. It should be understood thatFIG.1in one embodiment may not illustrate the connection structure of the pixel circuit40, which is only represented by a block diagram. The pixel circuit40may be a circuit structure including a plurality of transistors and storage capacitors, which may not be limited according to various embodiments of the present disclosure, and the pixel circuit40may only need to provide the display drive signals for the display pixels400. In one embodiment,FIG.2exemplarily illustrates that the drive circuit50includes the second transistor30, and the pixel circuit40includes the first transistor20; andFIG.2exemplarily illustrates that the drive circuit50includes the second transistor30and the first transistor20, which may not limit the structures of the pixel circuit40and the drive circuit50during an implementation. In one embodiment, the circuit structures of the pixel circuit40and the drive circuit50which provides the drive signal for the pixel circuit40may not be limited according to various embodiments of the present disclosure, and it may only need to satisfy that the drive circuit50includes the second transistor30, and the pixel circuit40includes the first transistor20or the drive circuit50includes the first transistor20, such that at least two types of transistors are provided on the base substrate10of the display panel000. In an implementation, the circuit structure may be understood according to the structures of the pixel circuit and the drive circuit designed for the display panel000to realize the display function in the existing technology.

In one embodiment, the first transistor20and the second transistor30may be formed on the base substrate10. The first transistor20may include the first active layer201, the first gate electrode20G, the first source electrode20S, and the first drain electrode20D. The first active layer201may include silicon. That is, the first transistor20may be a silicon transistor. The silicon may be polysilicon, that is, LTPS (low temperature poly silicon) or low temperature polysilicon, deposited by a low-temperature method. The length of the channel region of the first transistor20is L1. The channel region of the first transistor20is the region where the first active layer201of the first transistor20overlaps the first gate electrode20G. The length of the channel region of the first transistor20is the length of the channel region of the first transistor20along the current transmission direction between the first source electrode20S and the first drain electrode20D. The second transistor30may include the second active layer301, the second gate electrode30G, the second source electrode30S, and the second drain electrode30D. The second active layer301may include an oxide semiconductor, that is, the second transistor30is an oxide semiconductor transistor. The oxide semiconductor material may be an amorphous indium gallium zinc oxide (IGZO). The length of the channel region of the second transistor30is L2. The channel region of the second transistor30is the region where the second active layer301of the second transistor30overlaps the second gate electrode30G. The length of the channel region of the second transistor30is the length of the channel region of the second transistor30along the current transmission direction between the second source electrode30S and the second drain electrode30D.

In the display panel000provided in one embodiment, along the direction Z perpendicular to the base substrate10, the distance between the first gate electrode20G and the first active layer201is D1, and the first area S1=L1×D1; and the distance between the second gate electrode30G and the second active layer301is D2, the second area S2=L2×D2; where S1<S2. Optionally, the distance D1 between the first gate electrode20G and the first active layer201may be configured to be less than the distance D2 between the second gate electrode30G and the second active layer301; or the length L1 of the channel region of the first transistor20may be also configured to be less than the length L2 of the channel region of the second transistor30; or the distance D1 between the first gate electrode20G and the first active layer201may be also configured to be less than the distance D2 between the second gate electrode30G and the second active layer301, and the length L1 of the channel region of the first transistor20may be also configured to be less than the length L2 of the channel region of the second transistor30, thereby implementing that the first area S1 is less than the second area S2. In one embodiment, the first transistor20is a silicon transistor, the second transistor30is an oxide semiconductor transistor, and the first transistor20(e.g., a silicon transistor) has a faster carrier mobility compared with the second transistor30(e.g., an oxide semiconductor transistor); the first active layer201of the first transistor20includes silicon, the second active layer301of the second transistor30includes an oxide semiconductor, and the silicon transistor may not be sensitive to hydrogen, water and oxygen in the external environment than the oxide semiconductor transistor. Therefore, the distance D1 between the first gate electrode20G of the first transistor20and the first active layer201may be configured to be less than the distance D2 between the second gate electrode30G of the second transistor30and the second active layer301(as shown inFIGS.2-3). The first transistor20(e.g., a silicon transistor) has desirable responsiveness. Therefore, in order to fully increase the PPI of the display panel000, in one embodiment, the lengths (L1 and L2) of the channel regions of the two types of transistors may also be designed to be as small as possible by utilizing the advantages of silicon transistors and oxide semiconductor transistors, which is beneficial for saving circuit space and further increasing the PPI (pixels per inch) (pixel density, representing the number of pixels per inch) of the display panel000. In one embodiment, along the direction Z perpendicular to the base substrate10of the display panel000, the first area S1<the second area S2, where the first area S1=L1×D1, and the second area S2=L2×D2; and the distance between the first gate electrode20G of the first transistor20(e.g., a silicon transistor) and the first active layer201is D1, and the distance between the second gate electrode30G of the second transistor30(e.g., an oxide semiconductor transistor) and the second active layer301is D2. Therefore, the features and advantages of silicon transistors and oxide semiconductor transistors may be fully utilized, and while ensuring the stability and normal operation of the transistors, the space of the display panel may be saved and the PPI of the display panel may be improved, which is further beneficial for improving the display quality of the display panel000and improving the display effect and the product competitiveness.

It should be noted that for the width and length of the channel region described above and below, the length of the channel region refers to a dimension between the source and the drain along the migration direction of the carriers; if such direction is defined as the second direction, the width of the channel region refers to the dimension of the channel region along the third direction, where the second direction may be perpendicular to the third direction.

Furthermore, it should be noted thatFIGS.1-3in one embodiment may only exemplarily illustrate the planar structure of the display panel000and the cross-sectional structure of the local film-layer, which may not limit the structures included in the display panel000according to various embodiments of the present disclosure. The structures included in the display panel000may further include other film-layer structures which may implement the related functions of the display panel, such as various insulation layers, light-emitting layers, electrode layers (organic light-emitting display panels), and the like, which may not be limited according to various embodiments of the present disclosure. During an implementation, the structures of the display panel may be understood by referring to the existing technology.

In some optional embodiments, referring toFIGS.1-3and4,FIG.4illustrates a circuit connection block diagram of a drive circuit according to various embodiments of the present disclosure. In one embodiment, the drive circuit50may include an input module501, a logic transmission module502, and an output module503. The input module501may be connected between an input terminal in and the logic transmission module502, and the output module503may be connected between the logic transmission module502and an output terminal out. The logic transmission module502may be connected to a high-level signal terminal VGH or a low-level signal terminal VGL, and the output terminal may be connected to the pixel circuit40.

The logic transmission module502may include the second transistor30or the input module501may include the second transistor30and the output module503may include the first transistor20.

In one embodiment, it may describe that the drive circuit50may be a gate drive circuit, which is configured to connect with the pixel circuit40through the scan line G to provide a scan drive signal for the pixel circuit40. The drive circuit50may include the input module501, the logic transmission module502, and the output module503. One terminal of the input module501may be connected to the input terminal in of the drive circuit50, and the other terminal may be connected to the logic transmission module502. The input terminal in may provide an input signal for the input module501through a connected driver chip or flexible circuit board. The logic transmission module502may be connected to the high-level signal terminal VGH or the low-level signal terminal VGL, and may include a NAND gate, a NOR circuit, or the like which may be a switch circuit of the high-level signal terminal VGH and the low-level signal terminal VGL. The other terminal of the logic transmission module502may be connected to the output module503, the output module503may be connected to the output terminal out of the drive circuit50, and the output terminal out may be connected to the pixel circuit40, such that it may implement that the scan drive signal is provided for the pixel circuit40through the drive circuit50. In one embodiment, the logic transmission module502of the drive circuit50may include the second transistor30, or the input module501of the drive circuit50may include the second transistor30, and the output module503may include the first transistor20. The first area S1 of the first transistor20is smaller than the second area S2 of the second transistor30, such that the length L1 of the channel region of the first transistor20may be configured to be smaller, or along the direction Z perpendicular to the base substrate10, the distance D1 between the first gate electrode20G and the first active layer201may be smaller, which may both make the first area S1 of the first transistor20smaller, thereby making the response speed of the first transistor20faster. In the drive circuit50provided in one embodiment, the input module501and the logic transmission module502, especially the NAND circuit and NOR circuit of the logic transmission module502, may be switch circuits of the high-level signal terminal VGH and the low-level signal terminal VGL. The switch circuits of the high-level signal terminal VGH and the low-level signal terminal VGL may require the transistor to have a relatively low leakage current in the cutoff state, such that the leakage current of the transistor may be avoided to affect the high-level signal and low-level signal after the logic signal is transmitted, thereby affecting the normal signal transmission of a next node. Therefore, in one embodiment, the logic transmission module502may be configured to include the second transistor30(e.g., an oxide semiconductor transistor), and the input module501may be configured to include the second transistor30(e.g., an oxide semiconductor transistor); the oxide semiconductor transistor may have a lower leakage current in the cutoff state, such that the leakage currents of other disposed transistors may be avoided to affect the switch of the high-level signal and the low-level signal after the logic signal of the input module501and the logic transmission module502is transmitted, thereby affecting the normal signal transmission of a next node. The output module503of the drive circuit50may require a relatively fast response speed and drive capability. Therefore, in one embodiment, the output module503may be configured to include the first transistor20(e.g., a silicon transistor), the first area S1 of the first transistor20may be relatively small, and the response speed may be faster, thereby ensuring the response and drive capability of the drive circuit50and avoiding problems such as signal delay and the like caused by the drive circuit50of the display panel000.

It should be noted that, in one embodiment, the block diagram illustrates the connection structures of each module in the drive circuit50. During an implementation, the circuit connection structures inside each module of the drive circuit50may be designed according to actual requirements, which may not be limited according to various embodiments of the present disclosure.

In some optional embodiments, referring toFIGS.1-4,5, and6,FIG.5illustrates a top structural view of the first transistor and the second transistor inFIG.2; andFIG.6illustrates a top structural view of the first transistor and the second transistor inFIG.3. In one embodiment, the width of the channel region of the first transistor20is W1, the width of the channel region of the second transistor30is W2, the first volume V1=S1×W1, and the second volume V2=S2×W2, where V1>V2. The channel region of the first transistor20may be the region where the first active layer201of the first transistor20overlaps the first gate electrode20G. The length L1 of the channel region of the first transistor20may be the length of the channel region of the first transistor20along the current transmission direction between the first source electrode20S and the first drain electrode20D. The width W1 of the channel region of the first transistor20may be the length of the channel region of the first transistor20along a direction perpendicular to the length direction of the channel region of the first transistor20. That is, the length direction of the channel region of the first transistor20may be perpendicular to the width direction of the channel region of the first transistor20. The channel region of the second transistor30may be region where the second active layer301of the second transistor30overlaps the second gate electrode30G. The length of the channel region of the second transistor30may be the length of the channel region of the second transistor30along the current transmission direction between the second source electrode30S and the second drain electrode30D. The width W2 of the channel region of the second transistor30may be the length of the channel region of the second transistor30along the direction perpendicular to the length direction of the channel region of the second transistor30. That is, the length direction of the channel region of the second transistor30may be perpendicular to the width direction of the channel region of the second transistor30.

In one embodiment, it may describe that the width of the channel region of the first transistor20(e.g., a silicon transistor) is W1, the first volume V1=S1×W1, the width of the channel region of the second transistor30(e.g., an oxide semiconductor transistor) is W2, and the second volume V2=S2×W2. Although the first area S1<the second area S2, the first volume V1 is configured to be greater than the second volume V2. Therefore, the first volume V1 is greater than the second volume V2 by sufficiently increasing the width W1 of the channel region of the first transistor20(e.g., a silicon transistor), that is, W1/W2>S2/S1, the ratio of the width W1 of the channel region of the first transistor20to the width W2 of the channel region of the second transistor30is greater than the ratio of the second area S2 to the first area S1. In such way, the transistor responsiveness of the output module503of the drive circuit50using the first transistor20may be further ensured, thereby further ensuring the output performance of the drive circuit50, which is beneficial for improving the output effect.

In some optional embodiments, referring toFIGS.1,7and8,FIG.7illustrates another local film-layer cross-sectional structural schematic at the region A inFIG.1; andFIG.8illustrates a structural schematic of the pixel circuit40according to various embodiments of the present disclosure. In one embodiment, the pixel circuit40may include the first transistor20which is the drive transistor of the pixel circuit40, where D1/D2<L1/L2.

In one embodiment, it may describe that the pixel circuit40of the display pixel400may include the first transistor20(e.g., a silicon transistor), and the first transistor20may be the drive transistor of the pixel circuit40. In the organic light-emitting display panel, the first transistor20used as the drive transistor may be electrically connected to a light-emitting unit to provide an anode voltage signal for the anode of each light-emitting unit. In such way, a certain drive electric field may be formed between the anode and the cathode of the light-emitting unit, thereby implementing the light emission of the light-emitting layer and further implementing the display function. Since the drive transistor of the pixel circuit40is used to perform the data write work of the pixel circuit40, the accuracy of the threshold voltage of the drive transistor and the stability of the gate electrode potential may be extremely high. Therefore, there is a need to appropriately increase the distance between the gate electrode and the active layer of the transistor or the length of the channel region of the transistor, thereby obtaining a relatively accurate threshold voltage and ensuring the stability of the gate electrode potential of the drive transistor. Therefore, in one embodiment, the drive transistor of the pixel circuit40may be configured as the first transistor20(e.g., a silicon transistor), and the carrier mobility rate of the silicon transistor may be relatively high; when it is ensured that the first area S1 is smaller than the second area S2 and the increase of the length L1 of the channel region of the disposed first transistor20is relatively large, the response rate of the first transistor20may not be greatly affected. Therefore, in one embodiment, the drive transistor of the pixel circuit40may be configured as the first transistor20(e.g., a silicon transistor), and the ratio of the distance D1 between the first gate electrode20G of the first transistor20and the first active layer201to the distance D2 between the second gate electrode30G of the second transistor30and the second active layer301may be less than the ratio of the length L1 of the channel region of the first transistor20to the length L2 of the channel region of the second transistor30. That is, the length L1 of the channel region of the first transistor20may be greater than or equal to the length L2 of the channel region of the second transistor30. In such way, a relatively accurate threshold voltage of the drive transistor may be obtained, the stability of the gate electrode potential of the drive transistor may be ensured, and the significant influence on the response rate of the first transistor20may be avoided, which is beneficial for ensuring the response capability of the pixel circuit40.

Optionally, as shown inFIGS.8-9,FIG.9illustrates a working sequence diagram of the pixel circuit inFIG.8. The pixel circuit40may include a plurality of switch transistors and drive transistors (M1-M7), a storage capacitor Cst, and a light-emitting diode OLED, where the transistor M3 is a drive transistor, and remaining transistors are switch transistors. Taking the structure of the pixel circuit40as an example, the working principle of the pixel circuit40may be described as follows. In an initial reset stage T1, the transistors M5 and M7 may be in conduction, the other transistors may be in cutoff, the potential of a node N1 may be a reference voltage Vref, the potential of a node N4 may be a reference voltage Vref, and the anode of the light-emitting diode OLED may be reset; in a data write and threshold fetch stage T2, the transistor M2, the transistor M3 and the transistor M4 may be in conduction, the other transistors may be in cutoff, the potential of a node N2 may be a data voltage Vdata, the potential of the node N1 and a node N3 may be Vdata−|Vth|, where Vth is the threshold voltage of the transistor M3; and in a light-emitting stage T3, the transistor M1, the transistor M3, and the transistor M6 may be conduction, the other transistors may be in cutoff, a signal of a positive power supply voltage PVDD may be transmitted to the transistor M3, the transistor M3 may generate a drive current to drive the light-emitting diode OLED to emit light, the potential of the node N2 may be the positive power supply voltage PVDD, the potential of the node N1 may be Vdata-|Vth|, the potential of the node N3 may be PVEE+Voled, PVEE may be a negative power supply voltage, Voled may be a corresponding voltage on the light-emitting diode OLED, and a light-emitting current may be Id=k(Vsg−|Vth|)2=k(PVDD−Vdata−|Vth|)2. Optionally, in one embodiment, the structure of the pixel circuit40may be taken as an example, and the first transistor20(e.g., a silicon transistor) may be the drive transistor M3 in the pixel circuit40.

It should be noted that an implementable circuit structure of the pixel circuit40may be exemplarily described in one embodiment, which may not be limited according to various embodiments of the present disclosure. The structure of the pixel circuit40may be other structure, which may not be limited according to various embodiments of the present disclosure.

In some optional embodiments, referring toFIGS.1,10, and11,FIG.10illustrates another local film-layer cross-sectional structural schematic at the region A inFIG.1; andFIG.11illustrates another local film-layer cross-sectional structural schematic at the region B inFIG.1. In one embodiment, the second transistor30may further include a fourth gate electrode30G2, and along the direction Z perpendicular to the base substrate10, the distance between the fourth gate electrode30G2and the second active layer301is D4, where D2<D4. The channel region of the second transistor30defined by the second gate electrode30G may be a second channel region, and the length of the second channel region may be L2. The second channel region may be the region where the second active layer301of the second transistor30overlaps the second gate electrode30G, and the length of the second channel region may be the length of the second channel region of the second transistor30along the current transmission direction between the second source electrode30S and the second drain electrode30D. The channel region of the second transistor30defined by the fourth gate electrode30G2may be a fourth channel region, and the length of the fourth channel region may be L4. The fourth channel region may be the region where the second active layer301of the second transistor30overlaps the fourth gate electrode30G2, and the length of the fourth channel region may be the length of the fourth channel region of the second transistor30along the current transmission direction between the second source electrode30S and the second drain electrode30D; where the fourth area S4=L4×D4, and S2<S4.

In one embodiment, it may describe that the second transistor30(e.g., an oxide semiconductor transistor) may be a double gate transistor. The second transistor30may include the second gate electrode30G and the fourth gate electrode30G2, and along the direction Z perpendicular to the base substrate10, the distance D4 between the fourth gate electrode30G2and the second active layer301may be greater than the distance D2 between the second gate electrode30G and the second active layer301. That is, the second transistor30of the double gate structure may include two control gate electrodes, the second gate electrode30G may be the main gate electrode, and the fourth gate electrode30G2may be an auxiliary gate electrode. From the structural point of view, it can be considered that two single gate transistors may be connected in series. The added fourth gate electrode30G2may have a certain shielding effect, which may make the feedback capacitance between the drain electrode and the second gate electrode30G become extremely small, thereby being beneficial for improving the display quality of the display panel. Furthermore, in one embodiment, along the direction Z perpendicular to the base substrate10, the distance D4 between the fourth gate electrode30G2and the second active layer301may be configured to be greater than the distance D2 between the second gate electrode30G and the second active layer301, that is, the insulation layer between the fourth gate electrode30G2and the second active layer301may be configured to be relatively thick, which may protect the second active layer301.

In some optional embodiments, referring toFIGS.1,10, and11, the product of the length L4 of the fourth channel region of the second transistor30defined by the fourth gate electrode30G2of the second transistor30and the distance D4 between the fourth gate electrode30G2and the second active layer301is the fourth area S4; the product of the length L1 of the channel region of the first transistor20and the distance D1 between the first gate electrode20G and the first active layer201is the first area S1; and the product of the length L2 of the channel region of the second transistor30and the distance D2 between the second gate electrode30G and the second active layer301is the second area S2, where S4+S1>2S2, that is, the sum of the fourth area S4 and the first area S1 is greater than two times of the second area S2.

In one embodiment, it may describe that the difference between the fourth area S4 defined by the fourth gate electrode30G2of the second transistor30(e.g., an oxide semiconductor transistor) of the double gate structure and the second area S2 defined by the second gate electrode30G of the second transistor30is greater than the difference between the second area S2 defined by the second gate electrode30G of the second transistor30and the first area S1 defined by the first gate electrode20G of the first transistor20, that is, S4−S2>S2−S1, S4+S1>2S2. In one embodiment, along the direction Z perpendicular to the base substrate10, the distance D4 between the fourth gate electrode30G2and the second active layer301may be configured to be greater than the distance D2 between the second gate electrode30G and the second active layer301, that is, the insulation layer between the fourth gate electrode30G2and the second active layer301may be configured to be relatively thick, which may protect the second active layer301. Moreover, the fourth area S4 defined by the fourth gate electrode30G2may be configured to be relatively large to make the fourth area S4 greater than the second area S2, and the first area S1 and the second area S2 may both be areas defined by the main gates of the transistors. In addition, when the first transistor20and the second transistor30are used as switch transistors, although there is an area difference between the first transistor20and the second transistor30, the difference may not be configured to be extremely large, that is, S4−S2>S2−S1. In one embodiment, the second transistor30may be an oxide semiconductor transistor with a double gate structure. The fourth gate electrode30G2may be the auxiliary gate electrode which is located at the bottom of the second active layer301. The auxiliary gate electrode may improve the stability of the oxide semiconductor transistor and also protect the second active layer301.

In some optional embodiments, referring toFIGS.1,12, and13.FIG.12illustrates another local film-layer cross-sectional structural schematic at the region A inFIG.1; andFIG.13illustrates another local film-layer cross-sectional structural schematic at the region B inFIG.1. In one embodiment, the first transistor20may further include a third gate electrode20G2; along the direction Z perpendicular to the base substrate10, the distance between the third gate electrode20G2and the first active layer201is D3, where D1<D3; the channel region of the first transistor20defined by the first gate electrode20G is a first channel region, and the length of the first channel region is L1; the first channel region is a region where the first active layer201of the first transistor20overlaps the first gate electrode20G, and the length of the first channel region is the length of the first channel region of the first transistor20along the current transmission direction between the first source electrode20S and the first drain electrode20D. The channel region of the first transistor20defined by the third gate electrode20G2is a third channel region, and the length of the third channel region is L3; the third channel region is the region where the first active layer201of the first transistor20overlaps the third gate electrode20G2, and the length of the third channel region is the length of the third channel region of the first transistor20along the current transmission direction between the first source electrode20S and the first drain electrode20D, where the third area S3=L3×D3, and S1<S3.

In one embodiment, it may describe that the first transistor20(e.g., a silicon transistor) may be a double gate transistor and include the first gate electrode20G and the third gate electrode20G2. Along the direction Z perpendicular to the base substrate10, the distance D3 between the third gate electrode20G2and the first active layer201may be greater than the distance D1 between the first gate electrode20G and the first active layer201. That is, the first transistor20of the double gate structure may include two control gate electrodes, the first gate electrode20G may be the main gate electrode, and the third gate electrode20G2may be an auxiliary gate electrode. From the structural point of view, it can be considered that two single gate transistors may be connected in series. The added third gate electrode20G2may have a certain shielding effect, which may make the feedback capacitance between the drain electrode and the first gate electrode20G become extremely small, thereby being beneficial for improving the display quality of the display panel. Furthermore, in one embodiment, the third area S3 defined by the third gate electrode20G2may be configured to be relatively large, and the third area S3 may be greater than the first area S1. That is, the first area S1 defined by the main gate electrode may be less than the third area S3 defined by the auxiliary gate electrode. Along the direction Z perpendicular to the base substrate10, the distance D3 between the third gate electrode20G2and the first active layer201may be greater than the distance D1 between the first gate electrode20G and the first active layer201, that is, the insulation layer between the third gate electrode20G2and the first active layer201may be configured to be relatively thick, which may protect the first active layer201.

In some optional embodiments, referring toFIGS.1,12and13, the third gate electrode20G2of the first transistor20may include hydrogen-containing amorphous silicon.

In one embodiment, it may describe that the material of the third gate electrode20G2of the first transistor20may be amorphous silicon (a-Si:H) containing hydrogen, such that the hydrogen element may be provided to the first active layer201of the first transistor20(e.g., a silicon transistor) to repair defects in the first active layer201.

In some optional embodiments, referring toFIGS.1,8,12, and13, the first transistor20may be the drive transistor of the pixel circuit40, where S3−S1<S4−S2.

In one embodiment, it may describe that the pixel circuit40of the display pixel400may include the first transistor20(e.g., a silicon transistor), and the first transistor20may be the drive transistor of the pixel circuit40. In the organic light-emitting display panel, the first transistor20as the drive transistor may be electrically connected to a light-emitting unit, thereby providing an anode voltage signal for the anode of each light-emitting unit. In such way, a certain drive electric field may be formed between the anode and the cathode of the light-emitting unit, thereby implementing the light emission of the light-emitting layer and further implementing the display function.

In one embodiment, the difference between the third area S3 and the first area51may be configured to be less than the difference between the fourth area S4 and the second area S2. That is, the first transistor20and the second transistor30may both be double gate structures; the difference between the third area S3 defined by the bottom gate electrode (the third gate electrode20G2) of the first transistor20and the first area51defined by the top gate electrode (the first gate electrode20G) is S3−S1; and the difference between the fourth area S4 defined by the bottom gate electrode (the fourth gate electrode30G2) of the second transistor30and the second area S2 defined by the top gate electrode (the second gate electrode30G) is S4−S2. The material of the bottom gate electrode (the third gate electrode20G2) of the first transistor20may include hydrogen-containing amorphous silicon, which may provide the hydrogen element to the first active layer201to repair defects in the first active layer201and also play a shielding role to prevent the first transistor20from being interfered by other elements in the display device. Therefore, compared with the first area S1 defined by the top gate electrode (the first gate electrode20G), there is no need to configure the third area S3, defined by the bottom gate (the third gate electrode20G2) of the first transistor20, to be relatively large, that is, the difference between S3−S1 may be relatively small. Moreover, the material of the second active layer301of the second transistor30may be an oxide semiconductor material, which is more sensitive than silicon material. Especially, when both the oxide semiconductor transistor and the silicon transistor are disposed in the display panel000, the silicon transistor may be in an environment with a relatively high hydrogen content, in order to fully protect the oxide semiconductor transistor, the fourth area S4 defined by the bottom gate electrode (an auxiliary gate electrode, i.e., the fourth gate electrode30G2) may be configured to be relatively large after the second transistor30has configured with the double gate structure. Therefore, while the stability of the second transistor30is improved, the second active layer301of the second transistor30may be protected from the influence of hydrogen through the fourth gate electrode30G2with a relatively large area, such that S3−S1 may be configured to be less than S4−S2 in one embodiment.

In addition, since the third gate electrode20G2of the first transistor20in one embodiment is mainly used to supplement hydrogen and perform a shielding function for the first active layer201of the first transistor20, the distance D3 between the third gate electrode20G2and the first active layer201does not need to be configured to be relatively large along the direction Z perpendicular to the base substrate10. However, for the second transistor30, in order to fully protect the oxide semiconductor transistor, the distance D2 between the second gate electrode30G and the second active layer301and the distance D4 between the fourth gate electrode30G2and the second active layer301may be configured to be larger (that is, the thickness of the insulation layer between the second gate electrode30G and the second active layer301and the thickness of the insulation layer between the fourth gate electrode30G2and the second active layer301may both be larger), thereby protecting the second transistor30, which is beneficial for improving the display quality.

Optionally, referring toFIG.8,FIG.8illustrates a structural schematic of the pixel circuit40according to various embodiments of the present disclosure. The pixel circuit40may include a plurality of switch transistors and drive transistors, a storage capacitor, a light-emitting diode OLED (7T1C). Taking the structure of the pixel circuit40as an example, the first transistor20(e.g., a silicon transistor) may be the drive transistor M3 in the pixel circuit40.

In some optional embodiments, referring toFIGS.14and15,FIG.14illustrates another planar structural schematic of the display panel according to various embodiments of the present disclosure; andFIG.15illustrates a local film-layer cross-sectional structural schematic at a region C inFIG.14. It should be understood that the local film-layer schematic of a first transistor, a second transistor, and a third transistor may be exemplarily illustrated inFIG.15. In order to clearly illustrate the technical solution of one embodiment, the first transistor, the second transistor, and the third transistor may be illustrated together for description, which may not indicate the actual positions of the first transistor, the second transistor, and the third transistor in the display panel. During an implementation, the positions and connection relationships of the first transistor, the second transistor, and the third transistor may be determined according to the layout of the drive circuit and the pixel circuit. In one embodiment, the pixel circuit40may include a third transistor60; and the third transistor60may include a fifth gate electrode60G, a third active layer601, a third source electrode60S, and a third drain electrode60D; and the third active layer601may include an oxide semiconductor. Along the direction Z perpendicular to the base substrate10, the distance between the fifth gate electrode60G and the third active layer601is D5, the channel region of the third transistor60defined by the fifth gate electrode60G is a fifth channel region, the length of the fifth channel region is L5, and the fifth area S5=L5×D5; where S1<S5.

In one embodiment, it may describe that the pixel circuit40of the display panel000may further include the third transistor60. The third transistor60may include the fifth gate electrode60G, the third active layer601, the third source electrode60S, and the third drain electrode60D. The third active layer601may include an oxide semiconductor, that is, the third transistor60may be also an oxide semiconductor transistor. The oxide semiconductor material may be amorphous indium gallium zinc oxide (IGZO). The drive circuit50may include the second transistor30(e.g., an oxide semiconductor transistor), and the pixel circuit40may include the third transistor60(e.g., also an oxide semiconductor transistor). The length of the channel region of the third transistor60is L5, where the channel region of the third transistor60may be the region where the third active layer601of the third transistor60overlaps with the fifth gate electrode60G, and the length of the channel region of the third transistor60may be the length of the channel region of the third transistor60along the current transmission direction between the third source electrode60S and the third drain electrode60D.

In the display panel000provided in one embodiment, along the direction Z perpendicular to the base substrate10, the distance between the fifth gate electrode60G and the third active layer601is D5, the length of the fifth channel region of the third transistor60defined by the fifth gate electrode60G is L5, the fifth area S5=L5×D5, and S1<S5. Optionally, the distance D1 between the first gate electrode20G and the first active layer201may be configured to be less than the distance D5 between the fifth gate electrode60G and the third active layer601; the length L1 of the channel region of the first transistor20may be also configured to be less than the length L5 of the channel region of the third transistor60; and the distance D1 between the first gate electrode20G and the first active layer201may be configured to be less than the distance D5 between the fifth gate electrode60G and the third active layer601, and the length L1 of the channel region of the first transistor20may be also configured to be less than the length L5 of the channel region of the third transistor60, thereby realizing that the first area S1 is less than the fifth area S5. In one embodiment, the first transistor20may be a silicon transistor, and the third transistor60may be an oxide semiconductor transistor; compared with the third transistor60(an oxide semiconductor transistor), the first transistor20(a silicon transistor) may have a relatively fast carrier mobility rate; the first active layer201of the first transistor20may include silicon; the third active layer601in the third transistor60may include an oxide semiconductor; and the silicon transistor may not be sensitive to hydrogen, water and oxygen in the external environment than the oxide semiconductor transistor. Therefore, the distance D1 between the first gate electrode20G of the first transistor20and the first active layer201may be configured to be less than the distance D5 between the fifth gate electrode60G of the third transistor60and the third active layer601(as shown inFIG.15). Since the first transistor20(e.g., a silicon transistor) has better responsiveness, in order to fully improve the PPI of the display panel000, the lengths (L1 and L5) of the channel regions of such two types of transistors may be designed to be as small as possible by utilizing the advantages of silicon transistors and oxide semiconductor transistors, which is beneficial for saving circuit space and further beneficial for increasing the PPI of the display panel000. In one embodiment, along the direction Z perpendicular to the base substrate10of the display panel000, the first area S1 may be configured to be less than the fifth area S5, where the first area S1=L1×D1, the fifth area S5=L5×D5, the distance between the first gate electrode20G of the first transistor20(e.g., a silicon transistor) and the first active layer201is D1, and the distance between the fifth gate electrode60G of the third transistor60(e.g., an oxide semiconductor transistor) and the third active layer601is D5. Therefore, the features and advantages of silicon transistors and oxide semiconductor transistors may be fully utilized, and while ensuring the stability and normal operation of the transistors, the space of the display panel may be saved and the PPI of the display panel may be improved, which is further beneficial for improving the display quality of the display panel000and improving the display effect and the product competitiveness.

In some optional embodiments, referring toFIGS.8,14, and16,FIG.16illustrates another local film-layer cross-sectional structural schematic at the region C inFIG.14. It should be understood that the local film-layer schematic of a first transistor, a second transistor, and a third transistor may be exemplarily illustrated inFIG.16. In order to clearly illustrate the technical solution of one embodiment, the first transistor, the second transistor, and the third transistor may be illustrated together for description, which may not indicate the actual positions of the first transistor, the second transistor, and the third transistor in the display panel. During an implementation, the positions and connection relationships of the first transistor, the second transistor, and the third transistor may be determined according to the layout of the drive circuit and the pixel circuit. In one embodiment, the third transistor60may be a switch transistor of the pixel circuit40, where S2>S5.

In one embodiment, it may describe that the second area S2 defined by the second gate electrode30G of the second transistor30in the drive circuit50may be greater than the fifth area S5 defined by the fifth gate electrode60G of the third transistor60in the pixel circuit40. When the third transistor60(e.g., an oxide semiconductor transistor) is the switch transistor of the pixel circuit40, the third transistor60may only functions as a switch. Therefore, the fifth area S5 defined by the fifth gate electrode60G of the third transistor60may not need to be excessively large and may be configured to be less than the second area S2 defined by the second gate electrode30G of the second transistor30in the drive circuit50, which may save the space of the display panel and be beneficial for further improving the PPI of the display panel000. The drive circuits50may be disposed on the left and right edges of the display panel000, or only on a single edge of the display panel000, or at other positions in the display panel000, which may have a relatively large arrangement space. Moreover, the drive circuit50may be configured to provide signals for the pixel circuit40. Properly lengthening the length L2 of the channel region of the second transistor30(e.g., an oxide semiconductor transistor) (as shown inFIG.16) may make the second area S2 defined by the second gate electrode30G of the second transistor30relatively large, thereby avoiding problems such as signal delay, distortion and the like of the drive circuit50, which may be beneficial for improving the reliability of the drive circuit50.

Optionally, referring toFIG.8,FIG.8illustrates a structural schematic of the pixel circuit40according to various embodiments of the present disclosure. The pixel circuit40may include a plurality of switch transistors and drive transistors, a storage capacitor, a light-emitting diode OLED (7T1C). Taking the structure of the pixel circuit40as an example, any one or more of the switch transistors M1, M2, M4, M5, M6, and M7 in the pixel circuit40may be the third transistor60(e.g., an oxide semiconductor transistor).

In some optional embodiments, referring toFIGS.8,14, and17,FIG.17illustrates another local film-layer cross-sectional structural schematic at the region C inFIG.14. It should be understood that the local film-layer schematic of a first transistor, a second transistor, and a third transistor may be exemplarily illustrated inFIG.17. In order to clearly illustrate the technical solution of one embodiment, the first transistor, the second transistor, and the third transistor may be illustrated together for description, which may not indicate the actual positions of the first transistor, the second transistor, and the third transistor in the display panel. During an implementation, the positions and connection relationships of the first transistor, the second transistor, and the third transistor may be determined according to the layout of the drive circuit and the pixel circuit. In one embodiment, the third transistor60may be a drive transistor of the pixel circuit40, where S2<S5.

In one embodiment, it may describe that the second area S2 defined by the second gate electrode30G of the second transistor30in the drive circuit50may be less than the fifth area S5 defined by the fifth gate electrode60G of the third transistor60in the pixel circuit40. When the third transistor60(e.g., an oxide semiconductor transistor) is the drive transistor of the pixel circuit40, the drive transistor is the core element of the pixel circuit40to provide a drive current for the pixel circuit40, and before providing the drive current for the display pixel400of the pixel circuit40, there is a need to store the data voltage signal through the gate electrode of the drive transistor in the data write stage. Therefore, in one embodiment, the fifth area S5 defined by the fifth gate electrode60G of the third transistor60used as the drive transistor may be configured to be relatively large, and the length L5 of the channel region of the third transistor60(e.g., an oxide semiconductor transistor) may be appropriately lengthened (e.g., shown inFIG.17), which may make the third transistor60used as the drive transistor have a relatively stable threshold voltage and improve the stability of the gate electrode potential, thereby being beneficial for better realizing the storage of the data voltage signal by the gate electrode of the drive transistor.

Optionally, referring toFIG.8,FIG.8illustrates a structural schematic of the pixel circuit40according to various embodiments of the present disclosure. The pixel circuit40may include a plurality of switch transistors and drive transistors, a storage capacitor, and a light-emitting diode OLED (7T1C). Taking the structure of the pixel circuit40as an example, the third transistor60(e.g., an oxide semiconductor transistor) may be the drive transistor M3 in the pixel circuit40.

In some optional embodiments, referring toFIGS.14and18,FIG.18illustrates another local film-layer cross-sectional structural schematic at the region C inFIG.14. In one embodiment, the third transistor60may further include a sixth gate electrode60G2. Along the direction Z perpendicular to the base substrate10, the distance between the fifth gate electrode60G and the third active layer601is D5, the channel region of the third transistor60defined by the fifth gate electrode60G is the fifth channel region, the length of the fifth channel region is L5, and the fifth area S5=L5×D5. Along the direction Z perpendicular to the base substrate10, the distance between the sixth gate electrode60G2and the third active layer601is D6, where D5<D6. The channel region of the third transistor60defined by the sixth gate electrode60G2is a sixth channel region, the length of the sixth channel region is L6, the sixth channel region is the region where the third active layer601of the third transistor60overlaps the sixth gate electrode60G2, and the length of the sixth channel region is the length of the sixth channel region of the third transistor60along the current transmission direction between the third source electrode60S and the third drain electrode60D. The channel region of the third transistor60defined by the sixth gate electrode60G2is the sixth channel region, the length of the sixth channel region is L6, and the sixth area S6=L6×D6; where S5<S6.

In one embodiment, it may describe that the third transistor30(e.g., an oxide semiconductor transistor) in the pixel circuit40may be a double gate transistor. The third transistor60may include the fifth gate electrode60G and the sixth gate electrode60G2, and along the direction Z perpendicular to the base substrate10, the distance D6 between the sixth gate electrode60G2and the third active layer601may be greater than the distance D5 between the fifth gate electrode60G and the third active layer601. That is, the third transistor60of the double gate structure may include two control gate electrodes, the fifth gate electrode60G may be the main gate electrode, and the sixth gate electrode60G2may be an auxiliary gate electrode. From the structural point of view, it can be considered that two single gate transistors may be connected in series. The added sixth gate electrode60G2may have a certain shielding effect, which may make the feedback capacitance between the drain electrode and the fifth gate electrode60G become extremely small, thereby being beneficial for improving the display quality of the display panel. Furthermore, in one embodiment, along the direction Z perpendicular to the base substrate10, the distance D6 between the sixth gate electrode60G2and the third active layer601may be configured to be greater than the distance D5 between the fifth gate electrode60G and the third active layer601, that is, the insulation layer between the sixth gate electrode60G2and the third active layer601may be configured to be relatively thick, which may protect the third active layer601.

In some optional embodiments, refer toFIGS.8,14, and18, the third transistor60may be a switch transistor of the pixel circuit40, where S6<S4.

In one embodiment, it may describe that when the third transistor60in the pixel circuit40is used as a switch transistor, compared with the second transistor30in the drive circuit50, the sixth area S6 defined by the sixth gate electrode60G2of the third transistor60of the double gate structure may be less than the fourth area S4 defined by the fourth gate electrode30G2of the second transistor30of the double gate structure. Since various structures in the pixel circuits in the display region of the display panel000are relatively complicated, in one embodiment, when the third transistor60is used as a switch transistor, the sixth area S6 defined by the sixth gate electrode60G2of the third transistor60in the pixel circuit40may be relatively small, which may reduce the load caused by the parasitic capacitance of the pixel circuit4and be beneficial for improving the response speed of the pixel circuit40and reducing the hysteresis problem. Moreover, the drive circuits50may be disposed on the left and right edges of the display panel000, or only on a single edge of the display panel000, or at other positions in the display panel000, which may have a relatively large arrangement space. Therefore, in one embodiment, the fourth area S4 defined by the fourth gate electrode30G2of the second transistor30may be configured to be relatively large, that is, S6<S4, which may be beneficial for improving the reliability of the drive circuit50.

Optionally, referring toFIG.8,FIG.8illustrates a structural schematic of the pixel circuit40according to various embodiments of the present disclosure. The pixel circuit40may include a plurality of switch transistors and drive transistors, a storage capacitor, a light-emitting diode OLED (7T1C). Taking the structure of the pixel circuit40as an example, any one or more of the switch transistors M1, M2, M4, M5, M6, and M7 in the pixel circuit40may be the third transistor60(e.g., an oxide semiconductor transistor).

In some optional embodiments, referring toFIGS.8,14, and18, the third transistor60may be a switch transistor of the pixel circuit40, where S4−S2>S6−S5.

In one embodiment, it may describe that when the third transistor60in the pixel circuit40is used as a switch transistor, compared with the second transistor30in the drive circuit50, the difference between the sixth area S6 defined by the sixth gate electrode60G2of the third transistor60(e.g., an oxide semiconductor transistor) of the double gate structure and the fifth area S5 defined by the fifth gate electrode60G of the third transistor60may be less than the difference between the fourth area S4 defined by the fourth gate electrode30G2of the second transistor30and the second area S2 defined by the second gate electrode30G of the second transistor30(e.g., an oxide semiconductor transistor) of the double gate structure. Since various structures in the pixel circuits in the display region of the display panel000are relatively complicated, in one embodiment, when the third transistor60is used as a switch transistor, the sixth area S6 defined by the sixth gate electrode60G2of the third transistor60and the fifth area S5 defined by the fifth gate electrode60G may both be relatively small, that is, the difference between S6−S5 may also be relatively small, which may reduce the load caused by the parasitic capacitance of the pixel circuit4and be beneficial for improving the response speed of the pixel circuit40and reducing the hysteresis problem. Moreover, the drive circuits50may be disposed on the left and right edges of the display panel000, or only on a single edge of the display panel000, or at other positions in the display panel000, which may have a relatively large arrangement space. Therefore, in one embodiment, the fourth area S4 defined by the fourth gate electrode30G2of the second transistor30and the second area S2 defined by the second gate electrode30G may be both configured to be relatively large, that is, the difference between S4−S2 may also be relatively large to make S4−S2>S6−S5, which may be beneficial for improving the reliability of the drive circuit50.

Optionally, referring toFIG.8,FIG.8illustrates a structural schematic of the pixel circuit40according to various embodiments of the present disclosure. The pixel circuit40may include a plurality of switch transistors and drive transistors, a storage capacitor, a light-emitting diode OLED (7T1C). Taking the structure of the pixel circuit40as an example, the third transistor60(e.g., an oxide semiconductor transistor) may be any one or more of the switch transistors M1, M2, M4, M5, M6, and M7 in the pixel circuit40.

In some optional embodiments, referring toFIGS.8,14and19,FIG.19illustrates another local film-layer cross-sectional structural schematic at the region C inFIG.14. In one embodiment, the third transistor60may be the drive transistor of the pixel circuit40, where S6>S4.

In one embodiment, it may further describe that when the third transistor60in the pixel circuit40is used as a drive transistor, the fourth area S4 defined by the fourth gate electrode30G2(the auxiliary gate electrode) of the second transistor30in the drive circuit50may be less than the sixth area S6 defined by the sixth gate electrode60G2(the auxiliary gate electrode) of the third transistor60in the pixel circuit40. When the third transistor60(e.g., an oxide semiconductor transistor) is the drive transistor of the pixel circuit40, the drive transistor is the core element of the pixel circuit40to provide a drive current for the pixel circuit40, and before providing the drive current for the display pixel400of the pixel circuit40, there is a need to store the data voltage signal through the gate electrode of the drive transistor in the data write stage. Therefore, in one embodiment, the sixth area S6 defined by the sixth gate electrode60G2(the auxiliary gate electrode) of the third transistor60used as the drive transistor may be configured to be relatively large, and the length L5 of the channel region of the third transistor60(e.g., an oxide semiconductor transistor) may be appropriately lengthened (e.g., shown inFIG.19), which may make the third transistor60used as the drive transistor have a relatively stable threshold voltage and improve the stability of the gate electrode potential, thereby being beneficial for better realizing the storage of the data voltage signal by the gate electrode of the drive transistor.

Optionally, referring toFIG.8,FIG.8illustrates a structural schematic of the pixel circuit40according to various embodiments of the present disclosure. The pixel circuit40may include a plurality of switch transistors and drive transistors, a storage capacitor, and a light-emitting diode OLED (7T1C). Taking the structure of the pixel circuit40as an example, the third transistor60(e.g., an oxide semiconductor transistor) may be the drive transistor M3 in the pixel circuit40.

In some optional embodiments, referring toFIGS.8,14, and20,FIG.20illustrates another local film-layer cross-sectional structural schematic at the region C inFIG.14. In one embodiment, the pixel circuit40may further include a first capacitor C1; and the first capacitor C1 may be configured to store the data voltage transmitted to the gate electrode of the third transistor60. The sixth gate electrode60G2(the auxiliary gate electrode) of the third transistor60may be multiplexed as a plate of the first capacitor C1. Optionally, the other plate of the first capacitor C1 may be disposed at a same layer as other metal conductive film-layers and arranged opposite to the sixth gate electrode60G2. As shown inFIG.20, the other plate of the first capacitor C1 may be disposed at a same layer as the first gate electrode20G of the first transistor20

In one embodiment, it may describe that the pixel circuit40may further include the first capacitor C1 used as the storage capacitor for storing the data voltage transmitted to the gate of the third transistor60, and the sixth gate electrode60G2(the auxiliary gate electrode) of the third transistor60may be multiplexed as a plate of the first capacitor C1. The sixth area S6 defined by the sixth gate electrode60G2(the auxiliary gate electrode) of the third transistor60in the pixel circuit40is greater than the fourth area S4 defined by the fourth gate electrode30G2(the auxiliary gate electrode) of the second transistor30in the drive circuit50, such that the relative area of two plates of the first capacitor C1 may be relatively large, which may be beneficial for improving the storage capacity of the first capacitor C1 to make the storage capacitor have better storage capacity, thereby improving the drive effect of the pixel circuit40.

Optionally, referring toFIG.8,FIG.8illustrates a structural schematic of the pixel circuit40according to various embodiments of the present disclosure. The pixel circuit40may include a plurality of switch transistors and drive transistors, a storage capacitor, and a light-emitting diode OLED (7T1C). Taking the structure of the pixel circuit40as an example, the first capacitor may be the storage capacitor Cst in the pixel circuit40.

In some optional embodiments, referring toFIGS.14and21,FIG.21illustrates another local film-layer cross-sectional structural schematic at the region C inFIG.14. In on embodiment, the drive circuit50may further include a second capacitor C2, where the fourth gate electrode30G2may be multiplexed as a plate of the second capacitor C2. Optionally, the other plate of the second capacitor C2 may be disposed at a same layer as other metal conductive film-layers and arranged opposite to the fourth gate electrode30G2. As shown inFIG.21, the other plate of the second capacitor C2 may be disposed at a same layer as the first gate electrode20G of the first transistor20, and the capacitance value of the first capacitor C1 may be greater than the capacitance value of the second capacitor C2.

In one embodiment, it may describe that the drive circuit50may further include the second capacitor C2; the second transistor30in the drive circuit50may be electrically connected to the second capacitor C2; and the fourth gate electrode30G2of the second transistor30may be multiplexed as a plate of the second capacitor C2. In one embodiment, the capacitance value of the first capacitor C1 may be configured to be greater than the capacitance value of the second capacitor C2. The first capacitor C1 is a storage capacitor in the pixel circuit40for storing the data voltage signals, and the capability to store the data voltage signals may directly determine the drive current of the light-emitting element in the display pixel400. Therefore, the first capacitor C1 used as the storage capacitor in the pixel circuit40may need a relatively large capacitance value, which may then enable the first capacitor C1 to have a relatively high storage capacity. However, the second capacitor C2 in the drive circuit50may be configured for stabilizing a node potential, and the storage capacity requirement of the second capacitor C2 may be lower than the first capacitor C1 used as the storage capacitor in the pixel circuit40. Thus, in one embodiment, the capacitance value of the first capacitor C1 may be configured to be greater than the capacitance value of the second capacitor C2, which may satisfy the relatively high storage capacity of the first capacitor C1 and the requirement of stabilizing the node potential in the drive circuit50.

In some optional embodiments, referring toFIGS.8,14and21, the third transistor60may be the drive transistor of the pixel circuit40, where S4−S2<S6−S5.

In one embodiment, it may describe that when the third transistor60in the pixel circuit40is used as the drive transistor, compared with the second transistor30in the drive circuit50, the difference between the sixth area S6 defined by the sixth gate electrode60G2of the third transistor60(e.g., an oxide semiconductor transistor) of the double gate structure and the fifth area S5 defined by the fifth gate electrode60G of the third transistor60may be greater than the difference between the fourth area S4 defined by the fourth gate electrode30G2of the second transistor30(e.g., an oxide semiconductor transistor) of the double gate structure and the second area S2 defined by the second gate electrode30G of the second transistor30. When the third transistor60(e.g., an oxide semiconductor transistor) is the drive transistor of the pixel circuit40, the drive transistor is the core element of the pixel circuit40to provide a drive current for the pixel circuit40, and before providing the drive current for the display pixel400of the pixel circuit40, there is a need to store the data voltage signal through the gate electrode of the drive transistor in the data write stage. Therefore, in one embodiment, the sixth area S6 defined by the sixth gate electrode60G2(the auxiliary gate electrode) of the third transistor60used as the drive transistor and the fifth area S5 defined by the fifth gate electrode60G may both be configured to be relatively large, and the lengths L5 and L6 of the channel regions of the third transistor60(e.g., an oxide semiconductor transistor) may be appropriately lengthened (e.g., shown inFIG.21) to make S6−S5>S4−S2, which may make the third transistor60used as the drive transistor have a relatively stable threshold voltage, improve the stability of the gate electrode potential, thereby being beneficial for better realizing the storage of the data voltage signal by the gate electrode of the drive transistor.

Optionally, referring toFIG.8,FIG.8illustrates a structural schematic of the pixel circuit40according to various embodiments of the present disclosure. The pixel circuit40may include a plurality of switch transistors and drive transistors, a storage capacitor, and a light-emitting diode OLED (7T1C). Taking the structure of the pixel circuit40as an example, the third transistor60(e.g., an oxide semiconductor transistor) may be the drive transistor M3 in the pixel circuit40.

In some optional embodiments, referring toFIGS.22and23,FIG.22illustrates another planar structural schematic of the display panel according to various embodiments of the present disclosure; andFIG.23illustrates a local film-layer cross-sectional structural schematic at a region D inFIG.22. It should be understood that the local film-layer schematic of a first transistor, a second transistor, a third transistor, and a fourth transistor may be exemplarily illustrated inFIG.23. In order to clearly illustrate the technical solution of one embodiment, the first transistor, the second transistor, the third transistor, and the fourth transistor may be illustrated together for description, which may not indicate the actual positions of the first transistor, the second transistor, the third transistor, and the fourth transistor in the display panel. During an implementation, the positions and connection relationships of the first transistor, the second transistor, the third transistor, and the fourth transistor may be determined according to the layout of the drive circuit and the pixel circuit. In the display panel000provided in one embodiment, the pixel circuit40may further include a fourth transistor70.

The fourth transistor70may include a seventh gate electrode70G, a fourth active layer701, a fourth source electrode70S, and a fourth drain electrode70D; and the fourth active layer701may include an oxide semiconductor.

Along the direction Z perpendicular to the base substrate10, the distance between the seventh gate electrode70G and the fourth active layer701is D7, the channel region of the fourth transistor70defined by the seventh gate electrode70G is a seventh channel region, the length of the seventh channel region is L7, and the seventh area S7=L7×D7.

The fourth transistor70may further include an eighth gate electrode70G2. Along the direction Z perpendicular to the base substrate10, the distance between the eighth gate electrode70G2and the fourth active layer701is D8, the channel region of the fourth transistor70defined by the eighth gate electrode70G2is an eighth channel region, the length of the eighth channel region is L8, and the eighth area S8=L8×D8, where D7<D8, and S7<S8.

In one embodiment, it may describe that the pixel circuit40may further include the fourth transistor70; and the fourth transistor70may include the seventh gate electrode70G, the fourth active layer701, the fourth source electrode70S, and the fourth drain electrode70D. The fourth active layer701may include an oxide semiconductor, that is, the fourth transistor70may be an oxide semiconductor transistor, and the oxide semiconductor material may be an amorphous indium gallium zinc oxide (IGZO). The channel region of the fourth transistor70defined by the seventh gate electrode70G of the fourth transistor70is the seventh channel region, and the length of the seventh channel region is L7. The seventh channel region of the fourth transistor70is a region where the fourth active layer701of the fourth transistor70overlaps with the seventh gate electrode70G; and the length of the seventh channel region of the fourth transistor70is the length of the seventh channel region of the fourth transistor70along the current transmission direction between the fourth source electrode70S and the fourth drain electrode70D. The fourth transistor70may be a transistor with a double gate structure, and the fourth transistor70may further include the eighth gate electrode70G2. Along the direction Z perpendicular to the base substrate10, the distance between the eighth gate electrode70G2and the fourth active layer701is D8, the channel region of the fourth transistor70defined by the eighth gate electrode70G2is the eighth channel region, and the length of the eighth channel region is L8. The eighth channel region of the fourth transistor70is a region where the fourth active layer701of the fourth transistor70overlaps the eighth gate electrode70G2; and the length of the eighth channel region of the fourth transistor70is the length of the eighth channel region of the fourth transistor70along the current transmission direction between the fourth source electrode70S and the fourth drain electrode70D. In one embodiment, the pixel circuit40may include the first transistor20(e.g., a silicon transistor) of the double gate structure, the third transistor60(e.g., an oxide semiconductor transistor), and the fourth transistor70(e.g., an oxide semiconductor transistor). That is, the fourth transistor70of the double gate structure may include two control gate electrodes, the seventh gate electrode70G may be the main gate electrode, and the eighth gate electrode70G2may be an auxiliary gate electrode. From the structural point of view, it can be considered that two single gate transistors may be connected in series. The added eighth gate electrode70G2may have a certain shielding effect, which may make the feedback capacitance between the drain electrode and the seventh gate electrode70G become extremely small, thereby being beneficial for improving the display quality of the display panel.

In one embodiment, along the direction Z perpendicular to the base substrate10, the distance D7 between the seventh gate electrode70G (the main gate electrode) and the fourth active layer701may be less than the distance D8 between the eighth gate electrode70G2(the auxiliary gate electrode) and the fourth active layer701; and the seventh area S7 defined by the seventh gate electrode70G may be less than the eighth area S8 defined by the eighth gate electrode70G2. In such way, the insulation layer between the eighth gate electrode70G2and the fourth active layer701may be configured to be relatively thick, which may protect the fourth active layer701.

In some optional embodiments, referring toFIGS.8,22, and23, the third transistor60may be a drive transistor, and the fourth transistor70may be a switch transistor, where S6>S8.

In one embodiment, it may describe that when the third transistor60in the pixel circuit40is used as a drive transistor and the fourth transistor70is used as a switch transistor, the eighth area S8 defined by the eighth gate electrode70G2(the auxiliary gate electrode) of the fourth transistor70may be less than the sixth area S6 defined by the sixth gate electrode60G2(the auxiliary gate electrode) of the third transistor60. When the third transistor60(e.g., an oxide semiconductor transistor) is the drive transistor of the pixel circuit40, the drive transistor is the core element of the pixel circuit40to provide a drive current for the pixel circuit40, and before providing the drive current for the display pixel400of the pixel circuit40, there is a need to store the data voltage signal through the gate electrode of the drive transistor in the data write stage. Therefore, in one embodiment, the sixth area S6 defined by the sixth gate electrode60G2(the auxiliary gate electrode) of the third transistor60used as the drive transistor may be configured to be relatively large, and the length L6 of the channel region of the third transistor60(e.g., an oxide semiconductor transistor) may be appropriately lengthened (e.g., shown inFIG.23), which may make the third transistor60used as the drive transistor have a relatively stable threshold voltage and improve the stability of the gate electrode potential, thereby being beneficial for better realizing the storage of the data voltage signal by the gate electrode of the drive transistor. However, when the fourth transistor70of the oxide semiconductor transistor is used as the switch transistor of the pixel circuit40, the fourth transistor70may only function as a switch, such that the eighth area S8 defined by the eighth gate electrode70G2(the auxiliary gate electrode) of the fourth transistor70may not need to be excessively large, which may save the space of the display panel and be beneficial for improving the PPI of the display panel000.

Optionally, referring toFIG.8,FIG.8illustrates a structural schematic of the pixel circuit40according to various embodiments of the present disclosure. The pixel circuit40may include a plurality of switch transistors and drive transistors, a storage capacitor, and a light-emitting diode OLED (7T1C). Taking the structure of the pixel circuit40as an example, the third transistor60(e.g., an oxide semiconductor transistor) may be the drive transistor M3 in the pixel circuit40; and the fourth transistor70(e.g., an oxide semiconductor transistor) may be any one or more of the switch transistors M1, M2, M4, M5, M6, and M7 in the pixel circuit40.

In some optional embodiments, referring toFIGS.8,22, and23, the third transistor60may be a drive transistor, and the fourth transistor70may be a switch transistor, where S6−S5>S8−S7.

In one embodiment, it may describe that when the third transistor60in the pixel circuit40is used as a drive transistor and the fourth transistor70is used as a switch transistor, the difference between the sixth area S6 defined by the sixth gate electrode60G2of the third transistor60(e.g., an oxide semiconductor transistor) of the double gate structure and the fifth area S5 defined by the fifth gate electrode60G of the third transistor60may be greater than the difference between the eighth area S8 defined by the eighth gate electrode70G2(the auxiliary gate electrode) of the fourth transistor70(e.g., an oxide semiconductor transistor) of the double gate structure and the seventh area S7 defined by the seventh gate electrode70G of the fourth transistor70. When the third transistor60(e.g., an oxide semiconductor transistor) is the drive transistor of the pixel circuit40, the drive transistor is the core element of the pixel circuit40to provide a drive current for the pixel circuit40, and before providing the drive current for the display pixel400of the pixel circuit40, there is a need to store the data voltage signal through the gate electrode of the drive transistor in the data write stage. Therefore, in one embodiment, the sixth area S6 defined by the sixth gate electrode60G2(the auxiliary gate electrode) of the third transistor60used as the drive transistor and the fifth area S5 defined by the fifth gate electrode60G may both be configured to be relatively large, and the lengths L5 and L6 of the channel regions of the third transistor60(e.g., an oxide semiconductor transistor) may be appropriately lengthened (e.g., shown inFIG.23) to make S6−S5>S8−S7, which may make the third transistor60used as the drive transistor have a relatively stable threshold voltage and improve the stability of the gate electrode potential, thereby being beneficial for better realizing the storage of the data voltage signal by the gate electrode of the drive transistor. However, when the fourth transistor70of the oxide semiconductor transistor is used as the switch transistor of the pixel circuit40, the fourth transistor70may only function as a switch. Therefore, the seventh area S7 defined by the seventh gate electrode70G of the fourth transistor70and the eighth area S8 defined by the eighth gate electrode70G2(the auxiliary gate electrode) may not need to be excessively large, which may save the space of the display panel, thereby being beneficial for improving the PPI of the display panel000.

Optionally, referring toFIG.8,FIG.8illustrates a structural schematic of the pixel circuit40according to various embodiments of the present disclosure. The pixel circuit40may include a plurality of switch transistors and drive transistors, a storage capacitor, and a light-emitting diode OLED (7T1C). Taking the structure of the pixel circuit40as an example, the third transistor60(e.g., an oxide semiconductor transistor) may be the drive transistor M3 in the pixel circuit40; and the fourth transistor70(e.g., an oxide semiconductor transistor) may be any one or more of the switch transistors M1, M2, M4, M5, M6, and M7 in the pixel circuit40.

In some optional embodiments, referring toFIGS.22and23, in the pixel circuit40, the difference between the sixth area S6 defined by the sixth gate electrode60G2of the third transistor60(e.g., an oxide semiconductor transistor) of the double gate structure and the fifth area S5 defined by the fifth gate electrode60G of the third transistor60is S6−S5; in the drive circuit50, the difference between the fourth area S4 defined by the fourth gate electrode30G2of the second transistor30(e.g., an oxide semiconductor transistor) of the double gate structure and the second area S2 defined by the second gate electrode30G of the second transistor30is S4−S2; and in the pixel circuit40, the difference between the eighth area S8 defined by the eighth gate electrode70G2(the auxiliary gate electrode) of the fourth transistor70(e.g., an oxide semiconductor transistor) of the double gate structure and the seventh area S7 defined by the seventh gate electrode70G of the fourth transistor70is S8−S7, and (S6−S5)−(S8−S7)>(S8−S7)−(S4−S2), that is, (S6−S5)+(S4−S2)>2(S8−S7).

In one embodiment, it may describe that when the third transistor60in the pixel circuit40is used as the drive transistor, compared with the fourth transistor70used as the switch transistor in the pixel circuit40, the difference between the sixth area S6 defined by the sixth gate electrode60G2of the third transistor60(e.g., an oxide semiconductor transistor) of the double gate structure and the fifth area S5 defined by the fifth gate electrode60G of the third transistor60may be greater than the difference between the eighth area S8 defined by the eighth gate electrode70G2of the fourth transistor70(e.g., an oxide semiconductor transistor) of the double gate structure and the seventh area S7 defined by the seventh gate electrode70G of the fourth transistor70. Since various structures in the pixel circuits in the display region of the display panel000are relatively complicated, in one embodiment, when the fourth transistor70is used as the switch transistor, the eighth area S8 defined by the eighth gate electrode70G2of the fourth transistor70in the pixel circuit40and the seventh area S7 defined by the seventh gate electrode70G of the fourth transistor70may both be configured to be relatively small, that is, the difference between S8 and S7 may also be relatively small, which may reduce the load caused by the parasitic capacitance of the pixel circuit40, thereby being beneficial for improving the response speed of the pixel circuit40and reducing the problem of hysteresis. The eighth area S8 defined by the eighth gate electrode70G2of the fourth transistor70and the seventh area S7 defined by the seventh gate electrode70G of the fourth transistor70are both relatively small. Therefore, the difference between the eighth area S8 defined by the eighth gate electrode70G2of the fourth transistor70(e.g., an oxide semiconductor transistor) of the double gate structure and the seventh area S7 defined by the seventh gate electrode70G of the fourth transistor70may be greater than the difference between the fourth area S4 defined by the fourth gate electrode30G2of the second transistor30(e.g., an oxide semiconductor transistor) of the double gate structure and the second area S2 defined by the second gate electrode30G of the second transistor30; and the difference between (S8−S7) and (S4−S2) may not be configured to be excessively large, that is, the difference between (S6−S5) and (S8−S7) may be greater than the difference between (S8−S7) and (S4−S2), which may be beneficial for improving the PPI of the display panel while also improving the reliability of the pixel circuit40.

In some optional embodiments, referring toFIGS.24and25,FIG.24illustrates another planar structural schematic of the display panel according to various embodiments of the present disclosure; andFIG.25illustrates a local enlarged schematic at a region E inFIG.24. It should be understood thatFIG.25may exemplarily illustrate a local top view of a first transistor and a second transistor. The first transistor and the second transistor may be illustrated together for description to clearly illustrate the technical features of the first transistor and the second transistor, which may not indicate the actual disposing positions of the first transistor and the second transistor in the display panel. During an implementation, the disposing positions and the connection relationship of the first transistor and the second transistor may be determined by the layout of the drive circuit and the pixel circuit. In one embodiment, the display panel000may be a foldable display panel, and the display panel000may include a bending axis80extending along a first direction Y. The angle α2 between the length L2 direction of the channel region of the second transistor30and the first direction Y may be greater than 45 degrees, and the angle α1 between the length L1 direction of the channel region of the first transistor20and the first direction Y may be less than 45 degrees.

In one embodiment, it may describe that the first transistor20and the second transistor30of the display panel000may be formed on the base substrate10; the first transistor20may include the first active layer201, the first gate electrode20G, the first source electrode20S, and the first drain electrode20D; and the first active layer201may include silicon, that is, the first transistor20may be a silicon transistor. The silicon may be polysilicon, that is, LTPS (low temperature polysilicon), deposited by a low-temperature method. The length of the channel region of the first transistor20is L1. The channel region of the first transistor20is the region where the first active layer201of the first transistor20overlaps the first gate electrode20G. The length L1 of the channel region of the first transistor20is the length of the channel region of the first transistor20along the current transmission direction between the first source electrode20S and the first drain electrode20D (a direction X1 inFIG.25). The second transistor30may include the second active layer301, the second gate electrode30G, the second source electrode30S, and the second drain electrode30D. The second active layer301may include an oxide semiconductor, that is, the second transistor30may be an oxide semiconductor transistor, and the oxide semiconductor material may be an amorphous indium gallium zinc oxide (IGZO). The length of the channel region of the second transistor30is L2. The channel region of the second transistor30is the region where the second active layer301of the second transistor30overlaps the second gate electrode30G. The length of the channel region of the second transistor30is the length of the channel region of the second transistor30along the current transmission direction between the second source30S and the second drain30D (a direction X2 inFIG.25). The display panel000in one embodiment may be a foldable display panel, and the foldable display panel may include the bending axis80extending along the first direction Y. The angle α2 between the length direction X2 of the channel region of the second transistor30and the first direction Y may be greater than 45 degrees; and the angle α1 between the length direction X1 of the channel region of the first transistor20and the first direction Y may be less than 45 degrees. The second transistor30(e.g., an oxide semiconductor transistor) may have desirable bending performance. Therefore, in one embodiment, the angle α2 between the length direction X2 of the channel region of the second transistor30and the first direction Y may be configured to be greater than 45 degrees, that is, the angle α2 may be more inclined to 90 degrees; and the angle α1 between the length direction X1 of the channel region of the first transistor20and the first direction Y may be configured to be less than 45 degrees, that is, the angle α1 may be more inclined to 0 degree. In such way, the second transistor30with better bending performance may pass through the region where the bending axis80is located as much as possible to bear a greater bending pressure; and the first transistor20with poor bending performance may avoid passing through the region where the bending axis80is located as much as possible, which may avoid the failure of the first transistor20due to bending, thereby being beneficial for improving the product yield.

In some optional embodiments, referring toFIGS.24and26,FIG.26illustrates another local enlarged schematic at the region E inFIG.24. It should be understood thatFIG.26may exemplarily illustrate a local top view of a first transistor and a second transistor. The first transistor and the second transistor may be illustrated together for description to clearly illustrate the technical features of the first transistor and the second transistor, which may not indicate the actual disposing positions of the first transistor and the second transistor in the display panel. During an implementation, the disposing positions and the connection relationship of the first transistor and the second transistor may be determined by the layout of the drive circuit and the pixel circuit. In one embodiment, the length direction X2 of the channel region of the second transistor30may be perpendicular to the first direction Y; and the length direction X1 of the channel region of the first transistor20may be in parallel with the first direction Y.

In one embodiment, it may describe that the first transistor20and the second transistor30of the display panel000may be formed on the base substrate10; the first transistor20may include the first active layer201, the first gate electrode20G, the first source electrode20S, and the first drain electrode20D; and the first active layer201may include silicon, that is, the first transistor20may be a silicon transistor. The silicon may be polysilicon, that is, LTPS (low temperature polysilicon), deposited by a low-temperature method. The length of the channel region of the first transistor20is L1. The channel region of the first transistor20is the region where the first active layer201of the first transistor20overlaps the first gate electrode20G. The length L1 of the channel region of the first transistor20is the length of the channel region of the first transistor20along the current transmission direction between the first source electrode20S and the first drain electrode20D (a direction X1 inFIG.26). The second transistor30may include the second active layer301, the second gate electrode30G, the second source electrode30S, and the second drain electrode30D. The second active layer301may include an oxide semiconductor, that is, the second transistor30may be an oxide semiconductor transistor, and the oxide semiconductor material may be an amorphous indium gallium zinc oxide (IGZO). The length of the channel region of the second transistor30is L2. The channel region of the second transistor30is the region where the second active layer301of the second transistor30overlaps the second gate electrode30G. The length of the channel region of the second transistor30may be the length of the channel region of the second transistor30along the current transmission direction between the second source30S and the second drain30D (a direction X2 inFIG.26). The display panel000in one embodiment may be a foldable display panel, and the foldable display panel may include the bending axis80extending along the first direction Y. The length direction X2 of the channel region of the second transistor30may be perpendicular to the first direction, and the length direction X1 of the channel region of the first transistor20may be in parallel with the first direction Y. The second transistor30(e.g., an oxide semiconductor transistor) may have desirable bending performance. Therefore, in one embodiment, the angle between the length direction X2 of the channel region of the second transistor30and the first direction Y may be configured to be 90 degrees, and the angle between the length direction X1 of the channel region of the first transistor20and the first direction Y may be configured to be 0 degree. Furthermore, the second transistor30with better bending performance may pass through the region where the bending axis80is located as much as possible to bear a greater bending pressure; and the first transistor20with poor bending performance may avoid passing through the region where the bending axis80is located as much as possible, which may avoid the failure of the first transistor20due to bending, thereby being beneficial for improving the product yield.

In some alternative embodiments, referring toFIG.27,FIG.27illustrates a planar structural schematic of a display device according to various embodiments of the present disclosure. A display device111, provided in one embodiment, may include the display panel000provided in the above-mentioned embodiments of the present disclosure. A mobile phone may be taken as an example to illustrate the display device111inFIG.27. It should be understood that the display device111provided in the embodiments of the present disclosure may be a computer, a television, a vehicle-mounted display device, or other display device having a display function, which may not be limited according to various embodiments of the present disclosure. The display device111provided by the embodiments of the present disclosure may have the beneficial effects of the display panel000provided by the embodiments of the present disclosure, which may refer to the description of the display panel000in the above-mentioned embodiments and may not be described in detail herein.

From the above-mentioned embodiments, it can be seen that the display panel and the display device provided by the present disclosure may achieve at least the following beneficial effects.

In the display panel provided in the present disclosure, along the direction perpendicular to the base substrate, the distance between the first gate electrode and the first active layer is D1, and the first area S1=L1×D1; and the distance between the second gate electrode and the second active layer is D2, the second area S2=L2×D2, and S1<S2. The first transistor (the silicon transistor) has desirable responsiveness. Therefore, in order to fully increase the PPI of the display panel, the lengths of the channel regions of such two types of transistors may also be designed to be as small as possible by utilizing the advantages of silicon transistors and oxide semiconductor transistors in the present disclosure, which is beneficial for saving circuit space and further increasing the PPI of the display panel. In the present disclosure, along the direction perpendicular to the base substrate of the display panel, the first area S1 may be less than the second area S2, where the first area S1=L1×D1, and the second area S2=L2×D2; and the distance between the first gate electrode of the first transistor (the silicon transistor) and the first active layer is D1, and the distance between the second gate electrode of the second transistor (the oxide semiconductor transistor) and the second active layer is D2. Therefore, the features and advantages of silicon transistors and oxide semiconductor transistors may be fully utilized, and while ensuring the stability and normal operation of the transistors, the space of the display panel may be saved, and the PPI of the display panel may be improved, thereby being further beneficial for improving the display quality of the display panel000and improving the display effect and the product competitiveness.

Although certain embodiments of the present disclosure have been described in detail through examples, those skilled in the art should understand that the above-mentioned examples are merely for illustration and not for limiting the scope of the present disclosure. Those skilled in the art should understand that the above-mentioned embodiments may be modified without departing from the scope and spirit of the present disclosure, and the scope of the present disclosure is defined by the appended claims.