Patent ID: 12237280

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In overview, various embodiments directed to semiconductor devices are disclosed. Specifically, embodiments directed to radio-frequency (RF) resonator semiconductor structures including two or more resonator trenches and methods of forming the same. Various embodiment structures and methods may be used to reduce or eliminate adverse impacts of long manufacturing times. The various embodiment structures and methods may also be used to reduce and/or eliminate corrosion that occurs during these long etching processes, the various aspects of which are described herebelow.

Etching processes may be simultaneously time-sensitive and time-consuming. In particular, in semiconductor dies that include a large array of devices such as RF resonators and resonating circuits for detecting, measuring, and/or emitting RF signals, the etching processes used to form such array of devices may be time-sensitive and time-consuming. Etching processes may be time sensitive such that the formation of all required RF-related semiconductor structures within a single die may require multiple deposition and etching steps, during which conductive metals may be exposed to remnant etching gases. Such long exposures to etchant gases may result in corrosion of layers and materials. Long manufacturing times may cause F-pad buildup, or buildup of trench etching remnant gases (e.g., fluorine). Remnant etching gases exposed to oxygen during the time-consuming etching processes may react to create moisture, which may create a metal surface crystal defect (i.e., corrosion). Moisture caused by remnant etching gases may also be trapped under additional deposited layers, causing further defects to the semiconductor die. Such defects may lead to reduction in resonator function, such as altering the resonant frequencies of a resonator or leaving the fabricated resonator inoperable altogether.

A semiconductor die is disclosed within the present disclosure to reduce and/or eliminate RF resonator defects such as corrosion caused by remnant etching gases. The disclosed embodiment semiconductor dies may also be improved by standardizing and reducing manufacturing times. A semiconductor die may include a graduated, “step-like” structure including two or more resonator trenches having various depths within a dielectric layer, or substrate, in relation to a shared capping plate within the semiconductor die. The resonator trenches may be positioned within the semiconductor die such that the varying depths of each resonator trench in relation to the shared capping plate may create distinct resonator trenches (cavities) having different resonant frequencies. In addition, the embodiment methods may implement reduced steps to simultaneously layout each resonator trench. This reduction in the steps to fabricate the device may decrease manufacturing times. By reducing the manufacturing times and more specifically, the amount of time the device may be exposed to etchant gases, a reduction in the total amount of corrosion experienced during the manufacturing process may be achieved.

Various embodiment semiconductor dies and manufacturing methods are disclosed that may create semiconductor devices with multiple resonator trenches having different resonant frequencies. Such embodiment devices may be used in a variety of application and system requirements, such as RF applications. The graduated semiconductor die may allow the for customization of resonant frequencies specific to resonator trenches by varying the depths of the resonator trenches embedded within the substrate dielectric, adjusting the thicknesses of the capping plate and a dielectric layer between the capping plate and the resonator trenches, and by controlling the dielectric constants of the dielectric material layer(s) within each resonator trench (i.e., dielectric constants among the at least two resonator trenches is the same or different), among other structural design factors. Additionally, by embedding the resonator trenches within the substrate dielectric material there may be a reduction of the risk that the resonator structure may experience physical damage during the manufacturing process and during field operation. Consequently, the risk of RF degradation and/or a resulting inoperable semiconductor die structure may be reduced.

FIG.1Ais a vertical cross-sectional view of the exemplary structure100after deposition of a base dielectric layer102according to an embodiment of the present disclosure. Referring toFIG.1A, the base dielectric layer102may be deposited within a semiconductor structure (not shown). The base dielectric layer102may include silicon oxide-based dielectric materials such as undoped silicate glass, doped silicate glass, or organosilicate glass. In one embodiment, the base dielectric layer102may include undoped silicon glass, silicon nitride, phosphosilicate glass, fluorosilicate glass, low-k material, extreme low-k material, and black diamond, and/or a layer stack thereof. Other suitable dielectric materials are within the contemplated scope of disclosure.

FIG.1Bis a vertical cross-sectional view of the exemplary structure100after deposition of a first mask layer104according to an embodiment of the present disclosure. Referring toFIG.1B, the first mask layer104may be deposited over the base dielectric layer102. The first mask layer104may include a metallic material that may function as an etch mask in subsequent anisotropic etch processes. For example, the first mask layer104may include a conductive metallic nitride material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), or tungsten nitride (WN), or a conductive metallic carbide material, such as titanium carbide (TiC), tantalum carbide (TaC), or tungsten carbide (WC). Other suitable mask materials are within the contemplated scope of disclosure. The first mask layer104may be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition, or the like. The first mask layer104may have a thickness suitable for use in etching deep vias.

FIG.1Cis a vertical cross-sectional view of the exemplary structure100after the deposition and patterning of a first photoresist layer106according to an embodiment of the present disclosure. Referring toFIG.1C, the first photoresist layer106may be applied over the first mask layer104, and may be lithographically patterned to form an array of openings in areas that overlie the base dielectric layer102. The area of each opening in the first photoresist layer106may be greater than, less than, or the same as, a desired area of the top of vias that are to be formed in subsequent processes.

An etch process may be performed to transfer the pattern in the first photoresist layer106through the first mask layer104. The etch process may include an anisotropic etch process or an isotropic etch process. In one embodiment, an anisotropic etch process such as a reactive ion etch process may be performed to transfer the pattern in the first photoresist layer106through the first mask layer104. The first photoresist layer106may be subsequently removed, for example, by ashing.

FIG.1Dis a vertical cross-sectional view of the exemplary structure100after formation of an array of via cavities108a,108b,108caccording to an embodiment of the present disclosure. Referring toFIG.1D, an anisotropic etch process may be performed using the first mask layer104as an etch mask. The anisotropic etch process may comprise a reactive ion etch process that etches the base dielectric layer102selective to the materials of the first mask layer104. In one embodiment, the base dielectric layer102may include one or more dielectric materials such as undoped silicon glass, doped silicate glass, organosilicate glass, silicon nitride, phosphosilicate glass, fluorosilicate glass, low-k material, extreme low-k material, black diamond, and/or a layer stack thereof, and the anisotropic etch process may include a reactive ion etch process that etches the base dielectric layer102dielectric material(s) selective to the dielectric materials of the first mask layer104. The etch process may form deep via cavities108a,108b,108cunderneath the openings through the first mask layer104.

FIG.1Eis a vertical cross-sectional view of the exemplary structure after removing the first mask layer104according to an embodiment of the present disclosure. An anisotropic etch process may be performed to remove portions of the first mask layer104that may remain after performing the etch process as described with reference toFIG.1D. Referring toFIG.1E, the chemistry of the anisotropic etch process may be selective to the materials of the base dielectric layer102. For example, the first mask layer104may include materials TiN, TaN, W, WN, TiC, TaC, or WC, and the anisotropic etch process may include a reactive ion etch process that etches the first mask layer104selective to the dielectric materials of the base dielectric layer102. In an illustrative example, the anisotropic etch process may include a reactive ion etch process using HBr, CH2H2, CHF3, CF4, O2, N2, CHxFy, Ar, He, Cl2and/or other fluorinated gas(es) or halogen gas(es) as process gases.

FIG.1Fis a vertical cross-sectional view of the exemplary structure100after deposition of a metallic fill material layer in the via cavities108a,108b,108caccording to an embodiment of the present disclosure. Referring toFIG.1F, a metallic fill material layer may be sequentially deposited in, and over, each of the via cavities108a,108b,108cto form metallic fill material portions. A metallic fill material layer (not shown) may include a metallic material that provides high electrical conductivity. For example, the metallic fill material layer may include an elemental metal or an intermetallic alloy of at least two elemental metals. In one embodiment, the metallic fill material layer may include copper (Cu), W, ruthenium (Ru), molybdenum (Mo), aluminum (Al), aluminum copper (AlCu), aluminum silicon copper (AlSiCu), alloys thereof, and/or a layer stack thereof. Other suitable metallic fill materials within the contemplated scope of disclosure may also be used. The metallic fill material layer may be deposited by any physical vapor deposition, chemical vapor deposition, electroplating, or electroless plating.

A chemical mechanical polishing/planarization (CMP) process may be performed to remove portions of the metallic fill material layer that overlie a horizontal plane including the top surface of the base dielectric layer102. Each remaining portion of the metallic fill material layer that fills a via cavity may form contact vias110a,110b,110c. The top surfaces of the contact vias110a,110b,110cmay be within the same horizontal plane as the top surface of the base dielectric layer102.

In some embodiments, the metallic fill material layer used to form the contact vias110a,110b,110cmay be deposited/disposed over a previously deposited via barrier layer (not shown). Each via barrier layer may be a patterned portion of the metallic barrier layer as deposited in a manner similar to the metallic fill material layer according to the processing steps ofFIG.1F. A via barrier layer may include an elemental metal or an intermetallic alloy of at least two elemental metals. In one embodiment, the via barrier layer may include Ti, Ta, TiN, TaN, W, alloys thereof, and/or a layer stack thereof. Other suitable barrier layer materials within the contemplated scope of disclosure may also be used. The via barrier layer may be deposited by any physical vapor deposition, chemical vapor deposition, electroplating, or electroless plating.

Generally, the contact vias110a,110b,110cmay be formed by depositing at least one conductive material in the via cavities108a,108b,108c. Each of the contact vias110a,110b,110cmay be formed directly on a top surface of any respective semiconductor structure, such as a metal interconnect structure or a logic device structure or peripheral connection to a logic device structure used in logic devices, light emitting diode (LED) or liquid crystal display (LCD) devices, random access memory (RAM) devices, CMOS Image Sensor (CIS) devices, and any other device in which RF resonators may be used to implement said device.

In some embodiments, the contact vias110a,110b,110cmay be deep vias formed using techniques suitable for developing deep vias within a dielectric material. For example, the via cavities108a,108b,108cand contact vias110a,110b,110cmay be formed piecewise, such that portions of the base dielectric layer102and portions of the contact vias110a,110b,110cmay be formed in a sequence. For example, a lower, or first portion of the base dielectric layer102may be formed, first portions of the via cavities108a,108b,108cmay be etched, and first portions of the contact vias110a,110b,110cmay be formed within the first portions of the via cavities108a,108b,108c. A second portion of the base dielectric layer102may be deposited over the first portion of the base dielectric layer102and top surfaces of the lower portions of the contact vias110a,110b,110c. Second portions of the via cavities108a,108b,108cmay be etched within the second portion of the base dielectric layer102, and second portions of the contact vias110a,110b,110cmay be formed within the second portions of the via cavities108a,108b,108c. Additional portions of the base dielectric layer102and contact vias110a,110b,110cmay be formed to achieve a desired depth of the contact vias110a,110b,110c.

In one embodiment, portions of the via cavities108a,108b,108cmay be formed within portions of the base dielectric layer102as previously described, such that sidewalls of the various portions of the via cavities108a,108b,108cmay be tapered and in alignment with adjacent vertical portions of the via cavities108a,108b,108c. Subsequently, the contact vias110a,110b,110cmay be formed in their entirety by depositing a metallic material layer within the finished via cavities108a,108b,108c.

FIG.1Gis a vertical cross-sectional view of the exemplary structure100after deposition of a second mask layer112and a second photoresist layer114according to an embodiment of the present disclosure. The second mask layer112and the second photoresist layer114may be deposited and patterned in a similar manner as the first mask layer104and the first photoresist layer106as described with reference toFIGS.1B and1C. Referring toFIG.1G, the second mask layer112may be deposited over the base dielectric layer102and top surfaces of the contact vias110a,110b,110c. The second mask layer112may include a metallic material that may function as an etch mask in subsequent anisotropic etch processes. For example, the second mask layer112may include a conductive metallic nitride material, such as TiN, TaN, W, or WN, or a conductive metallic carbide material, such as TiC, TaC, or WC. The second mask layer112may be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition, or the like. The second mask layer112may have a thickness range from 2 nm to 20 nm, such as from 3 nm to 10 nm, although lesser and greater thicknesses may also be used.

The second photoresist layer114may be applied over the second mask layer112, and may be lithographically patterned to form an opening in areas that overlie a width of the base dielectric layer102between the contact vias110band110c. The area of the opening in the second photoresist layer114may be greater than, less than, or the same as, a desired area of a cavity in which an RF resonator may be formed in subsequent processes.

An etch process may be performed to transfer the pattern in the second photoresist layer114through the second mask layer112. The etch process may include an anisotropic etch process or an isotropic etch process. In one embodiment, an anisotropic etch process such as a reactive ion etch process may be performed to transfer the pattern in the second photoresist layer114through the second mask layer112. The second photoresist layer114may be subsequently removed, for example, by ashing.

FIG.1His a vertical cross-sectional view of the exemplary structure100after formation of a resonator trench (cavity)124caccording to an embodiment of the present disclosure. Referring toFIG.1H, an anisotropic etch process may be performed using the second mask layer112as an etch mask. The anisotropic etch process may comprise a reactive ion etch process that etches the base dielectric layer102selective to the materials of the second mask layer112. In one embodiment, the base dielectric layer102may include one or more dielectric materials such as undoped silicon glass, doped silicate glass, organosilicate glass, silicon nitride, phosphosilicate glass, fluorosilicate glass, low-k material, extreme low-k material, black diamond, and/or a layer stack thereof, and the anisotropic etch process may include a reactive ion etch process that etches the base dielectric layer102dielectric material(s) selective to the dielectric materials of the second mask layer112. The etch process may form the resonator cavity124cunderneath the openings through the second mask layer112.

An anisotropic etch process may be performed to remove portions of the second mask layer112that may remain after etching the base dielectric layer102to form the resonator cavity124c. The chemistry of the anisotropic etch process may be selective to the materials of the base dielectric layer102and the contact vias110a,110b,110c. For example, the second mask layer112may include materials TiN, TaN, W, WN, TiC, TaC, or WC, and the anisotropic etch process may include a reactive ion etch process that etches the second mask layer112selective to the dielectric materials of the base dielectric layer102and the contact vias110a,110b,110c. In an illustrative example, the anisotropic etch process may include a reactive ion etch process using HBr, CH2H2, CHF3, CF4, O2, N2, CHxFy, Ar, He, Cl2and/or other fluorinated gas(es) or halogen gas(es) as process gases.

FIG.1Iis a vertical cross-sectional view of the exemplary structure100after deposition of a third mask layer116and a third photoresist layer118according to an embodiment of the present disclosure. The third mask layer116and the third photoresist layer118may be deposited and patterned in a similar manner as the first mask layer104and the first photoresist layer106as described with reference toFIGS.1B and1C. Referring toFIG.1I, the third mask layer116may be deposited over the base dielectric layer102, including top surfaces of the base dielectric layer102inside the resonator cavity124c, and top surfaces of the contact vias110a,110b,110c. The third mask layer116may include a metallic material that may function as an etch mask in subsequent anisotropic etch processes. For example, the third mask layer116may include a conductive metallic nitride material, such as TiN, TaN, W, or WN, or a conductive metallic carbide material, such as TiC, TaC, or WC. The third mask layer116may be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition, or the like. The third mask layer116may have a thickness range from 2 nm to 20 nm, such as from 3 nm to 10 nm, although lesser and greater thicknesses may also be used.

The third photoresist layer118may be applied over the third mask layer116, and may be lithographically patterned to form an opening in areas that overlie a width of the base dielectric layer102between the contact vias110aand110b. The area of the opening in the third photoresist layer118may be greater than, less than, or the same as, a desired area of a cavity in which an RF resonator may be formed in subsequent processes.

An etch process may be performed to transfer the pattern in the third photoresist layer118through the third mask layer116. The etch process may include an anisotropic etch process or an isotropic etch process. In one embodiment, an anisotropic etch process such as a reactive ion etch process may be performed to transfer the pattern in the third photoresist layer118through the third mask layer116. The third photoresist layer118may be subsequently removed, for example, by ashing.

FIG.1Jis a vertical cross-sectional view of the exemplary structure100after formation of a resonator cavity124baccording to an embodiment of the present disclosure. Referring toFIG.1J, an anisotropic etch process may be performed using the third mask layer116as an etch mask. The anisotropic etch process may comprise a reactive ion etch process that etches the base dielectric layer102selective to the materials of the third mask layer116. In one embodiment, the base dielectric layer102may include one or more dielectric materials such as undoped silicon glass, doped silicate glass, organosilicate glass, silicon nitride, phosphosilicate glass, fluorosilicate glass, low-k material, extreme low-k material, black diamond, and/or a layer stack thereof, and the anisotropic etch process may include a reactive ion etch process that etches the base dielectric layer102dielectric material(s) selective to the dielectric materials of the third mask layer116. The etch process may form the resonator cavity124bunderneath the openings through the third mask layer116.

An anisotropic etch process may be performed to remove portions of the third mask layer116that may remain after etching the base dielectric layer102to form the resonator cavity124b. The chemistry of the anisotropic etch process may be selective to the materials of the base dielectric layer102and the contact vias110a,110b,110c. For example, the third mask layer116may include materials TiN, TaN, W, WN, TiC, TaC, or WC, and the anisotropic etch process may include a reactive ion etch process that etches the third mask layer116selective to the dielectric materials of the base dielectric layer102and the contact vias110a,110b,110c. In an illustrative example, the anisotropic etch process may include a reactive ion etch process using HBr, CH2H2, CHF3, CF4, O2, N2, CHxFy, Ar, He, Cl2and/or other fluorinated gas(es) or halogen gas(es) as process gases.

FIG.1Kis a vertical cross-sectional view of the exemplary structure100after deposition of a fourth mask layer120and a fourth photoresist layer122according to an embodiment of the present disclosure. The fourth mask layer120and the fourth photoresist layer122may be deposited and patterned in a similar manner as the first mask layer104and the first photoresist layer106as described with reference toFIGS.1B and1C. Referring toFIG.1K, the fourth mask layer120may be deposited over the base dielectric layer102, including top surfaces of the base dielectric layer102inside the resonator cavity124band resonator cavity124c, and top surfaces of the contact vias110a,110b,110c. The fourth mask layer120may include a metallic material that may function as an etch mask in subsequent anisotropic etch processes. For example, the fourth mask layer120may include a conductive metallic nitride material, such as TiN, TaN, W, or WN, or a conductive metallic carbide material, such as TiC, TaC, or WC. The fourth mask layer120may be formed by chemical vapor deposition, atomic layer deposition, physical vapor deposition, or the like. The fourth mask layer120may have a thickness range from 2 nm to 20 nm, such as from 3 nm to 10 nm, although lesser and greater thicknesses may also be used.

The fourth photoresist layer122may be applied over the fourth mask layer120, and may be lithographically patterned to form an opening in areas that overlie a width of the base dielectric layer102adjacent to the contact via110a(e.g., to the left of the contact via110aas illustrated). The area of the opening in the fourth photoresist layer122may be greater than, less than, or the same as, a desired area of a cavity in which an RF resonator may be formed in subsequent processes.

An etch process may be performed to transfer the pattern in the fourth photoresist layer122through the fourth mask layer120. The etch process may include an anisotropic etch process or an isotropic etch process. In one embodiment, an anisotropic etch process such as a reactive ion etch process may be performed to transfer the pattern in the fourth photoresist layer122through the fourth mask layer120. The fourth photoresist layer122may be subsequently removed, for example, by ashing.

FIG.1Lis a vertical cross-sectional view of the exemplary structure100after formation of a resonator cavity124aaccording to an embodiment of the present disclosure. Referring toFIG.1L, an anisotropic etch process may be performed using the fourth mask layer120as an etch mask. The anisotropic etch process may comprise a reactive ion etch process that etches the base dielectric layer102selective to the materials of the fourth mask layer120. In one embodiment, the base dielectric layer102may include one or more dielectric materials such as undoped silicon glass, doped silicate glass, organosilicate glass, silicon nitride, phosphosilicate glass, fluorosilicate glass, low-k material, extreme low-k material, black diamond, and/or a layer stack thereof, and the anisotropic etch process may include a reactive ion etch process that etches the base dielectric layer102dielectric material(s) selective to the dielectric materials of the fourth mask layer120. The etch process may form the resonator cavity124aunderneath the openings through the fourth mask layer120.

An anisotropic etch process may be performed to remove portions of the fourth mask layer120that may remain after etching the base dielectric layer102to form the resonator cavity124a. The chemistry of the anisotropic etch process may be selective to the materials of the base dielectric layer102and the contact vias110a,110b,110c. For example, the fourth mask layer120may include materials TiN, TaN, W, WN, TiC, TaC, or WC, and the anisotropic etch process may include a reactive ion etch process that etches the fourth mask layer120selective to the dielectric materials of the base dielectric layer102and the contact vias110a,110b,110c. In an illustrative example, the anisotropic etch process may include a reactive ion etch process using HBr, CH2H2, CHF3, CF4, O2, N2, CHxFy, Ar, He, Cl2and/or other fluorinated gas(es) or halogen gas(es) as process gases.

The etching processes used to form the resonator cavities124a,124b,124c, also referred to as resonator shallow trenches, as described with reference toFIGS.1G-1Lare performed in order from right to left, forming the resonator cavity124cfirst, followed by the resonator cavity124b, and subsequently the resonator cavity124a. The order of etching of the resonator cavities124a,124b,124cas described is merely illustrative and each of the resonator cavities124a,124b,124cmay be etched in any order with respect to other resonator cavities124a,124b,124c. For example, the resonator cavity124amay be etched first, followed by the resonator cavity124band then the resonator cavity124c. As another example, the resonator cavity124bmay be etched first, then resonator cavity124amay be etched followed by the resonator cavity124c.

In some embodiments, alternatively to the processes as described with reference toFIGS.1G-1L, one or more etch processes may be performed to shape the base dielectric layer102having resonator cavities124a,124b,124c. For example, the resonator cavities124a,124b,124cmay be formed in a single etch process, such as through ion-beam etching. The etch process(es) may form the graduated, step-like, shape of the base dielectric layer102as shown using any various deposition and etching techniques. The etch(es) process may be performed to create a graduated trench shape, in which varying depths of the resonator cavities124a,124b,124cmay be formed adjacent to and in between contact vias110a,110b,110c. The horizontal planes within the trench shape may be formed at heights less than the height of the top surface of the sidewalls.

For ease of illustration, three graduated “steps” are shown as three depths of the resonator cavities124a,124b,124c. However, the structure100may include only two resonator cavities of varying depths, or may include any number of resonator cavities greater than two in which each resonator cavity is adjacent to at least one corresponding contact via within the base dielectric layer102. In some embodiments, the structure100may include multiple resonator cavities, in which each resonator cavity of the multiple resonator cavities is a depth that is a different depth from at least one other resonator cavity. For example, the resonator cavity124bmay be of a certain depth, and the resonator cavities124a,124cmay have a same depth that is different than the depth of the resonator cavity124b. As another example, the structure100may include ten resonator cavities, with each resonator cavity having a depth alternating between a first depth and a different second depth. As a further example, the structure100may include five resonator cavities each having a different unique depth, similar to what is illustrated inFIG.1L.

FIG.1Mis a vertical cross-sectional view of a region of the exemplary structure100after deposition of a metallic barrier layer126according to an embodiment of the present disclosure. Referring toFIG.1M, the metallic barrier layer126may be sequentially deposited over each top surface of the contact vias110a,110b,110cand the exposed top surfaces of the base dielectric layer102. The metallic barrier layer126may include an elemental metal or an intermetallic alloy of at least two elemental metals. In one embodiment, the metallic barrier layer126may include Ti, Ta, TiN, TaN, W, alloys thereof, and/or a layer stack thereof. Other suitable metallic barrier layer materials may be within the contemplated scope of disclosure. The metallic barrier layer126may be deposited by any physical vapor deposition, chemical vapor deposition, electroplating, or electroless plating.

FIG.1Nis a vertical cross-sectional view of a region of the exemplary structure100after deposition of a metallic resonance layer128according to an embodiment of the present disclosure. Referring toFIG.1N, the metallic resonance layer128may be sequentially deposited over the top surface of metallic barrier layer126. The metallic resonance layer128may include an elemental metal or an intermetallic alloy of at least two elemental metals. In one embodiment, metallic resonance layer128may include at least one of tungsten (W), copper (Cu), ruthenium (Ru), molybdenum (Mo), aluminum (Al), aluminum copper (AlCu), or aluminum silicon copper (AlSiCu), alloys thereof, and/or a layer stack thereof. Other suitable elemental metals or intermetallic alloys of at least two elemental metals within the contemplated scope of disclosure may be used. The metallic resonance layer128may be deposited by any physical vapor deposition, chemical vapor deposition, electroplating, or electroless plating. In one embodiment, the metallic resonance layer128may have a range of thicknesses, such as a thickness that is greater than or equal to 50 angstroms (A), although thicker or thinner metallic resonance layer128may be used.

FIG.1Ois a vertical cross-sectional view of the exemplary structure100after deposition of a resonator trench dielectric layer130according to an embodiment of the present disclosure. Referring toFIG.1O, the resonator trench dielectric layer130may be sequentially deposited over the top surface of metallic resonance layer128. The resonator trench dielectric layer130may fill in trenches formed after depositing the metallic resonance layer128as described with reference toFIG.1N, such that the resonator trench dielectric layer130may be in contact with top surfaces and/or sidewalls of the metallic resonance layer128within the areas previously defined by the resonator cavities124a,124b,124c. The resonator trench dielectric layer130may be deposited by a conformal deposition process (such as a chemical vapor deposition process) or a self-planarizing deposition process (such as spin coating).

In one embodiment, the resonator trench dielectric layer130may include undoped silicon glass, doped silicate glass, organosilicate glass, silicon nitride, phosphosilicate glass, fluorosilicate glass, low-k material, extreme low-k material, and black diamond, and/or a layer stack thereof. Other suitable dielectric materials are within the contemplated scope of disclosure. The resonator trench dielectric layer130may be implemented as an isolation layer between a capping plate (not shown) and at least a portion of the metallic resonance layer128(i.e., any portion of the metallic resonance layer128vertically below the resonator trench dielectric layer130).

FIG.1Pis a vertical cross-sectional view of the exemplary structure100after performing CMP according to an embodiment of the present disclosure. Referring toFIG.1P, a CMP process may remove portions of the metallic barrier layer126, metallic resonance layer128, and resonator trench dielectric layer130. The CMP process may be performed to create a single horizontal plane in which top surfaces of the metallic barrier layer126, metallic resonance layer128, resonator trench dielectric layer130, and base dielectric layer102may be exposed.

The CMP process may separate portions of the metallic barrier layer126, metallic resonance layer128, and resonator trench dielectric layer130to form resonator trenches132a,132b,132c. For example, the CMP process may remove topmost portions of the metallic barrier layer126, metallic resonance layer128, and resonator trench dielectric layer130to form electrically-separated resonator trenches132a,132b,132c. A first resonator trench132amay include a metallic barrier layer126a, a metallic resonance layer128a, and a first resonator trench dielectric layer130a. A second resonator trench132bmay include a metallic barrier layer126b, a metallic resonance layer128b, and a second resonator trench dielectric layer130b. A third resonator trench132cmay include a metallic barrier layer126c, a metallic resonance layer128c, and a third resonator trench dielectric layer130c. The metallic barrier layers126a,126b,126cmay be electrically isolated from each other, the metallic resonance layers128a,128b,128cmay be electrically isolated from each other, and the resonator trench dielectric layers130a,130b,130cmay be isolated from each other.

In one embodiment, the CMP process may be performed until a specific layer or semiconductor structure is detected by one or more sensors. For example, the CMP process may be performed, removing topmost portions of the metallic barrier layer126, metallic resonance layer128, and resonator trench dielectric layer130, until a topmost surface of the contact vias110a,110b,110care exposed and detected. Thus, portions of the metallic barrier layers126a,126b,126c, metallic resonance layers128a,128b,128c, resonator trench dielectric layers130a,130b,130c, and base dielectric layer102may be planarized on a same horizontal plane as top surfaces of the contact vias110a,110b,110c.

In one embodiment, the CMP process may be performed until a designated depth is reached, in which the designated depth is based on known depths of resonator trenches132a,132b,132c(i.e., the depths of the metallic barrier layer126within the base dielectric layer102) and depths of the resonator trench dielectric layer130. For example, a CMP process may stop at a specific known depth to ensure the remaining resonator trench dielectric layers130a,130b,130chave certain thicknesses between exposed, polished top surfaces and bottom surfaces contacting the metallic resonance layers128a,128b,128crespectively.

FIG.1Qis a vertical cross-sectional view of the exemplary structure100after deposition of a dielectric isolation layer134according to an embodiment of the present disclosure. Referring toFIG.1Q, the dielectric isolation layer134may be sequentially deposited over top surface of contact vias110a,110b,110c, and exposed surfaces of resonator trenches132a,132b,132cand the base dielectric layer102. The dielectric isolation layer134may be deposited by a conformal deposition process (such as a chemical vapor deposition process) or a self-planarizing deposition process (such as spin coating).

In one embodiment, the dielectric isolation layer134may include undoped silicon glass, doped silicate glass, organosilicate glass, silicon nitride, phosphosilicate glass, fluorosilicate glass, low-k material, extreme low-k material, and black diamond, and/or a layer stack thereof. Other suitable dielectric materials are within the contemplated scope of disclosure. The dielectric isolation layer134may be implemented as an isolation layer between a capping plate (not shown) and each of the resonator trenches132a,132b,132c. In some embodiments, the thickness of the metallic resonance layer128combined and the resonator trench dielectric layer130may be greater than 100 Å. For example, the combined thickness of the metallic resonance layer128cand the third resonator trench dielectric layer130cof the resonator trench132cmay be greater than 100 Å, although lesser or equivalent thicknesses may also be used. The thickness of the metallic resonance layer128and the resonator trench dielectric layer130may be measured as the distance between a bottom surface of the dielectric isolation layer134and a top surface of the metallic barrier layer126for each resonator trench132a,132b,132c. As illustrated inFIG.1Q, the metallic resonance layer128and the resonator trench dielectric layer130may have different combined thicknesses indicated by labels T1, T2, and T3for each of the resonator trenches132a,132b,132c, in which each thickness T1, T2, and T3may be greater than 100 Å.

FIG.1Ris a vertical cross-sectional view of the exemplary structure100after deposition of a capping plate136according to an embodiment of the present disclosure. Referring toFIG.1R, a capping plate136may be deposited over the dielectric isolation layer134. The capping plate136may include an elemental metal or an intermetallic alloy of at least two elemental metals. In one embodiment, the capping plate136may include W, Cu, Ru, Mo, Al, AlCu, AlSiCu, alloys thereof, and/or a layer stack thereof. Other suitable elemental metal or an intermetallic alloy of at least two elemental metals are within the contemplated scope of disclosure. The capping plate136may be deposited by any one of physical vapor deposition, chemical vapor deposition, electroplating, or electroless plating.

In one embodiment, the dielectric constants of the base dielectric layer102and the dielectric isolation layer134may be the same. In one embodiment, the dielectric constants of the base dielectric layer102and the dielectric isolation layer134may be different. In one embodiment, the dielectric constants of the base dielectric layer102, the resonator trench dielectric layers130a,130b,130c, and the dielectric isolation layer134may be the same. In some embodiments, the dielectric constants of the resonator trench dielectric layers130a,130b,130cin each resonator trench132a,132b,132cmay be the same dielectric constant value. In some embodiments, the resonator trench dielectric layers130a,130b,130cin each resonator trench132a,132b,132cmay have different dielectric constant values and/or may be comprised of different dielectric materials. For example, the resonator trench dielectric layer130a, may have a different dielectric constant than resonator trench dielectric layers130b,130c, and the resonator trench dielectric layer130bmay have a different dielectric constant than the resonator trench dielectric layer130c.

In some embodiments, the resonator trench dielectric layers130a,130b,130cin each resonator trench132a,132b,132cmay be formed using one or more dielectric material layers, such as in a dielectric material stackup deposited sequentially over the metallic resonance layers128a,128b,128c. For example, the resonator trench dielectric layers130a,130b,130cmay consist of a series of deposited layers having varying dielectric constants. As another example, the resonator trench dielectric layer130amay consist of a single dielectric layer, the resonator trench dielectric layer130bmay consist of a two-dielectric layer stackup in which the dielectric constant of the resonator trench dielectric layer130bis based on the dielectric constants of both layers, and the resonator trench dielectric layer130cmay consist of a three-dielectric layer stackup in which the dielectric constant of the resonator trench dielectric layer130cis based on the dielectric constants of all three layers.

The resulting structure100may operate as a RF resonator, in which the resonator trenches132a,132b,132chave various resonant frequencies that may be fine-tuned during the manufacturing process based on, but not limited by, the following parameters: (i) the size and shape of the resonator trenches132a,132b,132cincluding (a) depth of the trench (i.e., distance from a bottom surface of the dielectric isolation layer134to a distal end of the metallic barrier layers126a,126b,126c), (b) taper angle of sidewalls of the resonator trenches132a,132b,132c, (c) taper angle of sidewalls of each material layer (e.g., metallic barrier layers126a,126b,126c; metallic resonance layers128a,128b,128c; resonator trench dielectric layers130a,130b,130c), (d) thickness of each material layer, and (e) width of the resonator trenches132a,132b,132c; (ii) dielectric constant and conductivity of the metallic barrier layers126a,126b,126c; (iii) dielectric constant and conductivity of the metallic resonance layers128a,128b,128c; and (iv) dielectric constant of the resonator trench dielectric layers130a,130b,130c.

The structure100operating as an RF resonator may function additionally based on, but not limited by, the following parameters: (i) the thickness and conductivity of the capping plate136; (ii) the thickness and dielectric constant of the dielectric isolation layer134; (iii) the distances between each pair of resonator trench132a,132b,132cand contact vias110a,110b,110c(e.g., distance between contact via110aand resonator trench132b, distance between contact via110band resonator trench132c); (iv) the size and shape of the contact vias110a,110b,110c; (v) the total number of resonator trenches within a single resonator structure in general; and (vi) the resonant frequencies of each resonator trench compared to the resonant frequencies of other resonator trenches within a single resonator structure.

In one embodiment, the resonator trenches132a,132b,132cmay have a same depth within the base dielectric layer102, but may exhibit different resonant frequencies as determined by one or more of the aforementioned parameters (e.g., dielectric constant of resonator trench dielectric layers130a,130b,130c). In one embodiment, the resonator trenches132a,132b,132cmay have a same shape (e.g., size, sidewall taper angles, depth) but may exhibit different resonant frequencies as determined by one or more of the aforementioned parameters.

The structure100may operate as an RF resonator by absorbing, or otherwise receiving RF signals at the capping plate136from an external RF source. The capping plate136may relay the received RF signals through the dielectric isolation layer134towards the resonator trenches132a,132b,132c. The RF signals may continuously propagate throughout the resonator trench dielectric layers130a,130b,130c, which may cause the metallic resonance layers128a,128b,128cto generate electromagnetic fields (EMF) if the frequency of the RF signals is equal to or substantially close to the one or more resonant frequencies of the resonator trenches132a,132b,132c. For example, if an RF signal received at the capping plate136has a frequency that is equivalent to or nearly equivalent to one or more resonant frequencies of the resonator trench132b, but the same RF signal frequency is not equivalent to or close to one or more resonant frequencies of the resonator trenches132a,132c, then the resonator trench132bmay generate a large EMF as compared to the EMFs generated by the resonator trenches132a,132c. The EMF generated by a propagated RF signal within each resonator trench132a,132b,132cmay be converted into voltages in the metallic resonance layers128a,128b,128c. The voltages within the metallic resonance layers128a,128b,128cmay be conducted through the metallic barrier layers126a,126b,126cto respective contact vias110a,110b,110c. The contact vias110a,110b,110cmay then communicate any voltage to logic device or circuitry within a semiconductor die (e.g., BEOL/FEOL) to process the voltage parameters measured as a result of the received RF signal.

In some examples, the RF resonator structure100may operate in reverse of the aforementioned RF measurement process, such that the RF resonator structure may be configured to alternatively or additionally function as an RF emitter. For example, a semiconductor logic device may provide a voltage to one or more contact vias110a,110b,110c. The contact vias110a,110b,110cmay transmit the voltage through the metallic barrier layers126a,126b,126cto the metallic resonance layers128a,128b,128c. The metallic resonance layers128a,128b,128cmay generate EMFs based on the applied voltage. The EMFs may generate a wave signal that may be directed through the dielectric isolation layer134to the capping plate136. The capping plate136may then transmit the RF signal outward and externally from the semiconductor die.

FIG.2is a vertical cross-sectional view of a first alternative embodiment of the exemplary structure200after formation of multiple capping plates according to an embodiment of the present disclosure. Referring toFIG.2, a capping plate material layer, or electrode material layer, layer may be deposited over the dielectric isolation layer134. The capping plate may be patterned to form a first capping plate136a, a second capping plate136b, and a third capping plate136c. The sidewalls of each of the first capping plate136a, the second capping plate136b, and the third capping plate136cmay be at least respectively aligned with or extend past the outer periphery of the resonator trenches132a,132b,132crespectively. For example, the first capping plate136amay be vertically positioned above the resonator trench132a, the second capping plate136bmay be vertically positioned above the resonator trench132b, and the third capping plate136cmay be vertically positioned above the resonator trench132c.

The first capping plate136a, the second capping plate136b, and the third capping plate136cmay include an elemental metal or an intermetallic alloy of at least two elemental metals. In one embodiment, the first capping plate136a, the second capping plate136b, and the third capping plate136cmay include W, Cu, Ru, Mo, Al, AlCu, AlSiCu, alloys thereof, and/or a layer stack thereof. Other suitable metal materials are within the contemplated scope of disclosure. The capping plate material layer may be deposited by any one of physical vapor deposition, chemical vapor deposition, electroplating, or electroless plating. The first capping plate136a, the second capping plate136b, and the third capping plate136cmay be formed within a dielectric layer138. In one embodiment, the first capping plate136a, the second capping plate136b, and the third capping plate136cmay be formed, and then the dielectric layer138may be sequentially deposited around the first capping plate136a, the second capping plate136b, and the third capping plate136c. In an alternative embodiment, the dielectric layer138may be deposited, and then the first capping plate136a, the second capping plate136b, and the third capping plate136cmay be sequentially formed within the dielectric layer138using a pattern and etching process implementing photoresist layers and mask layers.

The first capping plate136a, the second capping plate136b, and the third capping plate136cmay create three distinct resonator circuits respectively with the resonator trenches132a,132b,132c. A first resonator may be defined by the first capping plate136aand the resonator trench132a, in which resonant frequencies of the first resonator are determined at least by the distance between a bottom surface of the first capping plate136aand a distal bottom surface of the metallic barrier layer126a. A second resonator may be defined by the second capping plate136band the resonator trench132b, in which resonant frequencies of the second resonator are determined at least by the distance between a bottom surface of the second capping plate136band a distal bottom surface of the metallic barrier layer126b. A third resonator may be defined by the third capping plate136cand the resonator trench132c, in which resonant frequencies of the third resonator are determined at least by the distance between a bottom surface of the third capping plate136cand a distal bottom surface of the metallic barrier layer126c. Thus, the first resonator, second resonator, and third resonator may each exhibit different resonant frequencies depending on depths of the resonator trenches in relation to the capping plates136a,136b,136crespectively.

FIG.3is a vertical cross-sectional view of a second alternative embodiment of the exemplary structure300after formation of multiple capping plates according to an embodiment of the present disclosure. A capping plate material layer, or electrode material layer, layer may be deposited directly over the resonator trenches132a,132b,132cafter performing the CMP process as described with reference toFIG.1P. Referring toFIG.3, the capping plate may be patterned to form a first capping plate142a, a second capping plate142b, and a third capping plate142c. The first capping plate142a, the second capping plate142b, and the third capping plate142cmay be in direct electrical connection with the metallic barrier layers126a,126b,126c, metallic resonance layers128a,128b,128c, and contact vias110a,110b,110cof the resonator trenches132a,132b,132crespectively. The first capping plate142a, the second capping plate142b, and the third capping plate142cmay therefore enclose the resonator trench dielectric layers130a,130b,130crespectively. For example, the first capping plate142amay be deposited directly on top of both ends of the metallic barrier layer126a, both ends of the metallic resonance layer128a, and at least a portion of the contact via110ato isolate the resonator trench dielectric layer130aand to form an electrical pathway between the first capping plate142a, the resonator trench132a, and the contact via110a. The sidewalls of each of the first capping plate142a, the second capping plate142b, and the third capping plate142cmay be at least respectively aligned with or extend past the outer periphery of the resonator trenches132a,132b,132cand contact vias110a,110b,110crespectively.

The first capping plate142a, the second capping plate142b, and the third capping plate142cmay include an elemental metal or an intermetallic alloy of at least two elemental metals. In one embodiment, the first capping plate142a, the second capping plate142b, and the third capping plate142cmay include W, Cu, Ru, Mo, Al, AlCu, AlSiCu, alloys thereof, and/or a layer stack thereof. Other suitable metal materials are within the contemplated scope of disclosure. The capping plate material layer may be deposited by any one of physical vapor deposition, chemical vapor deposition, electroplating, or electroless plating. The first capping plate142a, the second capping plate142b, and the third capping plate142cmay be formed within a dielectric layer140. In one embodiment, the first capping plate142a, the second capping plate142b, and the third capping plate142cmay be formed, and then the dielectric layer140may be sequentially deposited around the first capping plate142a, the second capping plate142b, and the third capping plate142c. In an alternative embodiment, the dielectric layer140may be deposited, and then the first capping plate142a, the second capping plate142b, and the third capping plate142cmay be sequentially formed within the dielectric layer140using a pattern and etching process implementing photoresist layers and mask layers.

The first capping plate142a, the second capping plate142b, and the third capping plate142cmay create three distinct resonator circuits respectively with the resonator trenches132a,132b,132c. A first resonator may be defined by the first capping plate142aand the resonator trench132a, in which resonant frequencies of the first resonator are determined at least by the distance between a bottom surface of the first capping plate142aand a distal bottom surface of the metallic barrier layer126a. A second resonator may be defined by the second capping plate142band the resonator trench132b, in which resonant frequencies of the second resonator are determined at least by the distance between a bottom surface of the second capping plate142band a distal bottom surface of the metallic barrier layer126b. A third resonator may be defined by the third capping plate142cand the resonator trench132c, in which resonant frequencies of the third resonator are determined at least by the distance between a bottom surface of the third capping plate142cand a distal bottom surface of the metallic barrier layer126c. Thus, the first resonator, second resonator, and third resonator may each exhibit different resonant frequencies depending on depths of the resonator trenches in relation to the capping plates142a,142b,142crespectively.

Referring toFIG.4, an exemplary structure according to an embodiment of the present disclosure is illustrated.FIG.4is a vertical cross-sectional view of an exemplary structure after formation of complementary metal-oxide-semiconductor (CMOS) transistors and metal interconnect structures formed in dielectric material layers during a front-end-of-line (FEOL) process according to an embodiment of the present disclosure. The exemplary structure includes a substrate9, which may be a semiconductor substrate such as a commercially available silicon substrate. Shallow trench isolation structures720including a dielectric material such as silicon oxide may be formed in an upper portion of the substrate9. Suitable doped semiconductor wells, such as p-type wells and n-type wells, may be formed within each area that is laterally enclosed by a portion of the shallow trench isolation structures720. Field effect transistors may be formed over the top surface of the substrate9. For example, each field effect transistor may include a source region732, a drain region738, a semiconductor channel735that includes a surface portion of the substrate9extending between the source region732and the drain region738, and a gate structure750. Each gate structure750may include a gate dielectric752, a gate electrode754, a gate cap dielectric758, and a dielectric gate spacer756. A source-side metal-semiconductor alloy region742may be formed on each source region732, and a drain-side metal-semiconductor alloy region748may be formed on each drain region738.

The exemplary structure may include a resonator trench region101in which an array of resonator trenches may be subsequently formed, and a logic region201in which logic devices that support operation of the array of resonator elements may be formed. In one embodiment, devices (such as RF resonators) in the resonator trench region101may include resonator trenches (e.g., resonator trenches132a,132b,132c) that communicate voltages converted from EMFs generated by received RF signals to transistor structures electrically connected to the contact vias110a,110b,110c. Supporting structures such as logic or memory devices may be formed in the logic region201. Devices (such as field effect transistors) in the logic region201may provide functions that are needed to operate the array of resonator trenches to be subsequently formed. Specifically, devices in the logic region201may be configured to control the operation of the array of resonator trenches. The devices formed on the top surface of the substrate9may include complementary metal-oxide-semiconductor (CMOS) transistors and optionally additional semiconductor devices (such as resistors, diodes, capacitors, etc.), and are collectively referred to as CMOS circuitry700.

Various metal interconnect structures formed in dielectric material layers may be subsequently formed over the substrate9and the devices (such as field effect transistors). The dielectric material layers may include, for example, a contact-level dielectric material layer601, a first interconnect-level dielectric material layer610, a second interconnect-level dielectric material layer620, a third interconnect-level dielectric material layer630, and a fourth interconnect-level dielectric material layer640. The metal interconnect structures may include device contact via structures612formed in the contact-level dielectric material layer601and contact a respective component of the CMOS circuitry700, first line structures618formed in the first interconnect-level dielectric material layer610, first via structures622formed in a lower portion of the second interconnect-level dielectric material layer620, second line structures628formed in an upper portion of the second interconnect-level dielectric material layer620, second via structures632formed in a lower portion of the third interconnect-level dielectric material layer630, third line structures638formed in an upper portion of the third interconnect-level dielectric material layer630, third via structures642formed in a lower portion of the fourth interconnect-level dielectric material layer640, and fourth line structures648formed in an upper portion of the fourth interconnect-level dielectric material layer640. In one embodiment, the second line structures628may include source lines that are connected a source-side power supply for an array of resonator elements. The voltage provided by the source lines may be applied to the electrodes (e.g., contact vias110a,110b,110c) through the access transistors provided in the resonator trench region101.

Each of the contact-level and interconnect-level dielectric layers (601,610,620,630,640) may include a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the interconnect structures (612,618,622,628,632,638,642,648) may include at least one conductive material, which may be a combination of a metallic liner layer (such as a metallic nitride or a metallic carbide) and a metallic fill material. Each metallic liner layer may include TiN, TaN, WN, TiC, TaC, and WC, and each metallic fill material portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and/or combinations thereof. Other suitable materials within the contemplated scope of disclosure may also be used. In one embodiment, the first via structures622and the second line structures628may be formed as integrated line and via structures by a dual damascene process, the second via structures632and the third line structures638may be formed as integrated line and via structures, and/or the third via structures642and the fourth line structures648may be formed as integrated line and via structures. While the present disclosure is described using an embodiment in which an array of resonator trenches formed over the fourth interconnect-level dielectric material layer640, embodiments are expressly contemplated herein in which the array of resonator trenches may be formed at a different interconnect level.

A cap layer103may be formed over the metal interconnect structures and the interconnect dielectric material layers. For example, the cap layer103may be formed on the top surfaces of the fourth line structures648and on the top surface of the fourth interconnect-level dielectric material layer640. The cap layer103may include a dielectric capping material that may protect underlying metal interconnect structures such as the fourth line structures648. In one embodiment, the cap layer103may include a material that may provide high etch resistance, i.e., a dielectric material, and also may function as an etch stop material during a subsequent anisotropic etch process that etches the base dielectric layer102. For example, the cap layer103may include silicon carbide or silicon nitride, and may have a thickness in a range from 5 nm to 30 nm, although lesser and greater thicknesses may also be used.

The cap layer103and the base dielectric layer102may be formed as planar blanket (unpatterned) layers having a respective planar top surface and a respective planar bottom surface that extends throughout the resonator trench region101and the logic region201. The cap layer103and the base dielectric layer102may be etched to form contact via cavities in which contact vias110a,110b,110cmay be formed. The resonator trenches132a,132b,132c, dielectric isolation layer134, and capping plate136of the structure100may be formed according to various embodiments as described with reference toFIGS.1A-3.

FIG.5is a flowchart that illustrates the general processing steps for forming a semiconductor structure100according to an embodiment of the present disclosure. Referring to step501andFIGS.1A-1F, a first contact via110aand a second contact via110bmay be formed within a base dielectric layer102. Referring to step502andFIGS.1G-1L, a first resonator cavity124amay be etched adjacent to the first contact via110a. Referring to step503andFIG.1G-1L, a second resonator cavity124bmay be etched adjacent to the second contact via110b, in which the second resonator cavity124bmay have a different depth than the first resonator cavity124a. Referring to step504andFIG.1M, a metallic barrier layer126may be deposited over top surfaces of the first contact via110aand the second contact via110band exposed surfaces of the base dielectric layer102. Referring to step505andFIG.1N, a metallic resonance layer128may be deposited over the metallic barrier layer126. Referring to step506andFIG.1O, a resonator trench dielectric layer130may be deposited over the metallic resonance layer128. Referring to step507andFIG.1P, a CMP process may be performed until top surfaces of the first contact via110aand the second contact via110bare exposed, in which the CMP process may physically separate portions of the metallic barrier layer126and the metallic resonance layer128to form a first resonator trench132aincluding a first metallic barrier layer126a, a first metallic resonance layer128a, and a first resonator trench dielectric layer130a, and a second resonator trench132bincluding a second metallic barrier layer126b, a second metallic resonance layer128b, and a second resonator trench dielectric layer130b. Referring to step508andFIGS.1R,2, and3, a capping plate material layer136may be deposited above exposed surfaces of the base dielectric layer102, the first contact via110a, the second contact via110b, the first resonator trench132a, and the second resonator trench132b.

In one embodiment, referring toFIG.1Qa dielectric isolation layer134may be deposited on top of exposed surfaces of the base dielectric layer102, the first contact via110a, the second contact via110b, the first resonator trench132a, and the second resonator trench132b, in which the dielectric isolation layer134may be positioned beneath the capping plate material layer.

In one embodiment, referring toFIGS.2and3, the capping plate material layer may be patterned to form a first capping plate (e.g.,136a,142a) and a second capping plate (e.g.,136b,142b), in which the first capping plate (e.g.,136a,142a) may be positioned above the first resonator trench132a, and in which the second capping plate (e.g.,136b,142b) may be positioned above the second resonator trench132b.

In one embodiment, referring toFIGS.1A-1La third contact via110cmay be formed within the base dielectric layer102, and a third resonator cavity124cmay be etched adjacent to the third contact via110c, in which the third resonator cavity124cmay have a different depth than the second resonator cavity124b.

In one embodiment, a first distance between a bottom surface of the capping plate material layer and a distal end of the first metallic resonance layer128amay be greater than 100 Å, and a second distance between the bottom surface of the capping plate material layer and a distal end of the second metallic resonance layer128bmay be greater than 100 Å.

Referring to all drawings and according to various embodiments of the present disclosure, a semiconductor structure is provided. The semiconductor structure may include a first resonator comprising a first metallic resonance layer128aand a capping plate136having a bottom surface that is a first distance from a distal end of the first metallic resonance layer128a. The semiconductor structure may further include a second resonator including a second metallic resonance layer128b, and the capping plate136, in which the bottom surface is a second distance from a from a distal end of the second metallic resonance layer128b, and in which the first distance is different from the second distance.

In one embodiment, the first metallic resonance layer128amay be in a first trench shape having first sidewalls, and the second metallic resonance layer128bmay be in a second trench shape having second sidewalls. The first resonator may further include a first resonator trench dielectric layer (e.g., resonator trench dielectric layer130a) embedded between the first sidewalls of the first metallic resonance layer128a, and the second resonator may further include a second resonator trench dielectric layer (e.g., resonator trench dielectric layer130b) embedded between the second sidewalls of the second metallic resonance layer128b.

In one embodiment, the first resonator trench dielectric layer (e.g., resonator trench dielectric layer130a) and the second resonator trench dielectric layer (e.g., resonator trench dielectric layer130b) may have different dielectric constants. In one embodiment, the first resonator trench dielectric layer (e.g., resonator trench dielectric layer130a) and the second resonator trench dielectric layer (e.g., resonator trench dielectric layer130b) may have the same dielectric constant. In one embodiment, the first resonator trench dielectric layer (e.g., resonator trench dielectric layer130a) and the second resonator trench dielectric layer (e.g., resonator trench dielectric layer130b) may include at least one of undoped silicon glass, silicon nitride, phosphosilicate glass, fluorosilicate glass, low-k material, extreme low-k material, or black diamond.

In one embodiment, the semiconductor structure may further include a base dielectric layer102in which the first metallic resonance layer128aand the second metallic resonance layer128bare embedded, in which a top surface of the base dielectric layer102may be on a same horizontal plane as top surfaces of the first metallic resonance layer128aand the second metallic resonance layer128b. In one embodiment, the first resonator may further include a dielectric isolation layer134positioned between the capping plate136and the first metallic resonance layer128a, and the second resonator may further include the dielectric isolation layer134positioned between the capping plate136and the second metallic resonance layer128b.

In one embodiment, the semiconductor structure may further include a third resonator including a third metallic resonance layer128cand the capping plate136, in which the bottom surface is a third distance from a from a distal end of the third metallic resonance layer128c, and in which the third distance is different from the first distance and the second distance.

In one embodiment the semiconductor structure may further include a first contact via110a, a first metallic barrier layer126aelectrically connecting the first contact via110aand the first metallic resonance layer128a, a second contact via110b, and a second metallic barrier layer126belectrically connecting the second contact via110band the second metallic resonance layer128b.

Referring to all drawings and according to various embodiments of the present disclosure, a semiconductor structure is provided, which may include a first resonator and a second resonator. The first resonator may include a first metallic resonance layer128aand a first capping plate (e.g.,136a,142a) having a bottom surface that is a first distance from a distal end of the first metallic resonance layer128a. The second resonator may include a second metallic resonance layer128band a second capping plate (e.g.,136b,142b) having a bottom surface that is a second distance from a distal end of the second metallic resonance layer128b, in which the first distance is different from the second distance.

In one embodiment, the first capping plate (e.g.,136a,142a) may be positioned vertically above the first metallic resonance layer128a, the second capping plate (e.g.,136b,142b) may be positioned vertically above the second metallic resonance layer128b, the first capping plate (e.g.,136a,142a) may be on a same horizontal plane as the second capping plate (e.g.,136b,142b). In one embodiment, the first capping plate (e.g.,136a,142a) may be positioned directly on top of the first metallic resonance layer128aand may be electrically connected to the first metallic resonance layer128a, and the second capping plate (e.g.,136b,142b) may be positioned directly on top of the second metallic resonance layer128band may be electrically connected to the second metallic resonance layer128b.

In one embodiment, the first resonator may further include a dielectric isolation layer134positioned between the first capping plate (e.g.,136a) and the first metallic resonance layer128a, and the second resonator may further include the dielectric isolation layer134positioned between the second capping plate (e.g.,136b) and the second metallic resonance layer128b. In one embodiment, the semiconductor structure may further include a third resonator including a third metallic resonance layer128cand a third capping plate (e.g.,136c,142c) having a bottom surface that is a third distance from a distal end of the third metallic resonance layer128c, in which the third distance is different from the first distance and the second distance. In one embodiment, the first metallic resonance layer128aand the second metallic resonance layer128beach may include at least one of W, Cu, Ru, Mo, Al, AlCu, or AlSiCu.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.