Patent ID: 12245439

It should be understood the reference number for any illustrated element that appears in multiple different figures has the same meaning across the multiple figures, and the mention or discussion herein of any illustrated element in the context of any particular figure also applies to each other figure, if any, in which that same illustrated element is shown.

DETAILED DESCRIPTION

FIG.1is a side cross-sectional view showing an example IC structure100including a MIM capacitor module102and an interconnect structure104formed concurrently, according to one example. As discussed below, the MIM capacitor module102may be constructed without adding any photomask operations to the background integrated circuit fabrication process (e.g., the background integrated circuit fabrication process for forming the interconnect structure104and/or other IC elements). In other examples, the interconnect structure104may be optional, such that MIM capacitor module102described herein may be formed alone, i.e., not concurrently with an interconnect structure.

As shown inFIG.1, the interconnect structure104may include a lower interconnect element110formed in a lower metal layer Mxand an upper interconnect element112formed in an upper metal layer Mx+1and connected to the lower interconnect element110by at least one interconnect via114formed in a via layer Vxby depositing a conformal via material, e.g., tungsten, into respective via openings.

Each of the lower interconnect element110and upper interconnect element112may comprise a wire or other laterally elongated structure, or a discrete pad (e.g., having a square or substantially square shape from a top view), or any other suitable shape and structure.

As used herein, a “metal layer,” for example in the context of a lower metal layer Mxor upper metal layer Mx+1, may comprise any metal or metalized layer or layers, including (a) a metal interconnect layer, e.g., comprising copper, aluminum or other metal deposited by a subtractive patterning process (e.g., deposition, patterning, and etching of a metal layer) or using a damascene process, or (b) a silicided polysilicon layer including a number of polysilicon regions each having a layer or region of metal silicide formed thereon, for example. For example, in some examples the lower metal layer Mxmay be a silicided polysilicon layer and the upper metal layer Mx+1may comprise a first metal interconnect layer, often referred to as metal-1. In such examples, x=0 such that the lower metal layer Mx=M0and the upper metal layer Mx+1=M1(i.e., metal-1). Further, as used herein, an “interconnect structure,” e.g., in the context of the interconnect structure104discussed below, may include any type or types of metal layers as defined above.

The MIM capacitor module102includes a bottom electrode120, a top electrode122, and an insulator124formed between the bottom electrode120and the top electrode122. The MIM bottom electrode120includes (a) a bottom electrode base134formed in the lower metal layer Mxand (b) a bottom electrode cup136formed on the bottom electrode base134. The bottom electrode base134is formed in the lower metal layer Mx, e.g., as discussed below in more detail. The bottom electrode cup136is formed on the bottom electrode base134and includes (a) a laterally-extending bottom electrode cup base140and (b) a bottom electrode cup sidewall142extending upwardly from the laterally-extending bottom electrode cup base140. In some examples, the bottom electrode cup136, a bottom electrode contact164, and the interconnect vias114may formed concurrently in the via layer Vx, e.g., by depositing a conformal via material, e.g., tungsten, into respective openings formed in a dielectric region170. In some examples, e.g., as discussed below with reference toFIG.2B, the bottom electrode cup136, bottom electrode contact164, and interconnect vias114are formed over a liner166, e.g., comprising TiN.

As shown, the insulator124includes an insulator cup144an insulator flange146extending laterally outwardly from the insulator cup144. The insulator cup144is formed in an opening defined by the bottom electrode cup136, and includes (a) a laterally-extending insulator cup base148and (b) an insulator cup sidewall150extending upwardly from the laterally-extending insulator cup base148.

The insulator flange146extends laterally outwardly from an upper edge152of the insulator cup sidewall150, and extends laterally over an upper surface143of the bottom electrode cup sidewall142. In some examples, the bottom electrode cup sidewall142has a closed-loop perimeter in a horizontal (x-y) plane, the insulator cup sidewall150has a closed-loop perimeter in a horizontal (x-y) plane, a sidewall upper edge152extends around the closed-loop perimeter of the insulator cup sidewall150, and the insulator flange146extends radially outwardly from the closed-loop sidewall upper edge152and extends around the closed-loop perimeter of the insulator cup sidewall142. The sidewall upper edge152may extend fully around the closed-loop perimeter of the insulator cup sidewall150. The insulator flange146may extend fully around the closed-loop perimeter of the insulator cup sidewall142.

In the illustrated example:(a) the bottom electrode cup base140has a rectangular shape (in a horizontal plane) defining four lateral sides, and the bottom electrode cup sidewall142includes four bottom electrode cup sidewall sections142a-142d(sidewall sections142aand142care visible inFIG.1) collectively defining a closed-loop rectangular perimeter, each bottom electrode cup sidewall section142a-142dextending upwardly from a respective lateral side of the rectangular bottom electrode cup base140; and(b) the insulator cup base148similarly has a rectangular shape (in a horizontal plane) defining four lateral sides, and the insulator cup sidewall150includes four insulator cup sidewall sections150a-150d(sidewall sections150aand150care visible inFIG.1) collectively defining a closed-loop rectangular perimeter, each insulator cup sidewall section150a-150dextending upwardly from a respective lateral side of the rectangular insulator cup base148.

The cross-sectional view shown inFIG.1shows bottom electrode cup sidewall sections142aand142cand insulator cup sidewall sections150aand150c. For a more complete view, the top view ofFIG.2Hdiscussed below shows all four bottom electrode cup sidewall sections142a-142dand insulator cup sidewall sections150a-150d.

In other examples, the bottom electrode cup base140and insulator cup base148may have any other shape, e.g., circular or N-sided polygon, and the bottom electrode cup sidewall142and insulator cup sidewall150may each include any suitable number of sidewall sections.

As discussed below in more detail, a vertical height of the bottom electrode cup sidewall142may be shortened prior to forming the insulator124, by removing an upper portion or “lip” of the bottom electrode cup sidewall142(e.g., using a sputter etch process), thus allowing the formation of the insulator flange146extending laterally over the upper surface143of the shortened bottom electrode cup sidewall142. The insulator flange146insulates the top electrode122from the upper surface143of the bottom electrode cup sidewall142, to prevent shorting between the top electrode122and bottom electrode120.

In some examples, insulator124may comprise silicon nitride (SiN) with a thickness in the range of 250-750 Å. Alternatively, insulator124may comprise Al2O3, ZrO2, HfO2, ZrSiOx, HfSiOx, HfAlOx, or Ta2O5, or other suitable capacitor insulator material.

The top electrode122fills an interior opening defined by the insulator cup144, and may include a top electrode cap region158extending laterally over the insulator flange146, such that the insulator flange146is arranged between the top electrode cap region158and the upper surface143of the bottom electrode cup sidewall142. The top electrode122may comprise Al, Ti, TiN, W, TiW, Co, Ta, TaN, Cu, or any combination thereof, for example, TiN plus Al, TiN plus W, or a Ta/TaN bilayer plus Cu.

The MIM capacitor102also includes a top electrode connection pad160and a bottom electrode connection pad162formed in the upper metal layer Mx+1concurrently with the upper interconnect element112, e.g., as discussed below with reference toFIG.2J. The top electrode connection pad160may be formed directly on the top electrode122. The bottom electrode connection pad162may be connected to the bottom electrode base134by the bottom electrode contact164. The bottom electrode contact164may be formed laterally spaced apart from the bottom electrode cup136and laterally spaced apart from interconnect vias114, and may have a shape and size similar to interconnect vias114. In some examples, MIM capacitor102may have multiple bottom electrode contacts164. In another example, the bottom electrode contact164may be formed as a lateral extension of the bottom electrode cup136, which configuration may provide a reduced electrical resistance between the bottom electrode cup136and the bottom electrode connection pad162.

Each of the top electrode connection pad160and bottom electrode connection pad162may have any suitable shape and size. For example, each of the top electrode connection pad160and bottom electrode connection pad162may have a square or rectangular shape in the x-y plane, e.g., as shown inFIG.2Hdiscussed below. In another example (not shown) each of the top electrode connection pad160and bottom electrode connection pad162may have a generally circular shape in the x-y plane. As another example, the top electrode connection pad160and/or bottom electrode connection pad162may be substantially elongated, e.g., running laterally across the wafer in the x-direction and/or the y-direction.

The top electrode122is capacitively coupled to both the bottom electrode cup base140and the bottom electrode cup sidewalls142of the bottom electrode cup136(which bottom electrode cup136is conductively coupled to the bottom electrode base134), which defines a substantially larger area of capacitive coupling between the top electrode122and bottom electrode120, as compared with conventional designs. In particular, MIM capacitor module102defines the following capacitive couplings between the top electrode122and bottom electrode120:(a) capacitive coupling between the top electrode122and bottom electrode120by a displacement current path through the insulator cup base148and through the bottom electrode cup base140; and(b) capacitive coupling between the top electrode122and bottom electrode120by a displacement current path through each vertically-extending insulator cup sidewall150and through the corresponding vertically-extending bottom electrode cup sidewall142.

The laterally-extending insulator cup base148effectively defines a plate capacitor, with the top and bottom plates extending horizontally (x-y plane), and each of the four insulator cup sidewall sections150a-150deffectively defines an additional plate capacitor, with the top and bottom plates extending vertically (x-z plane or y-z plane). Thus, MIM capacitor module102may be referred to as a “three-dimensional” or “3D” MIM capacitor. Due to the capacitive coupling area between the top electrode122and bottom electrode120(e.g., as compared with conventional designs), the MIM capacitor module102may be formed in a smaller footprint on the respective chip, thus allowing an increased density of capacitors and/or other structures on the chip.

As mentioned above, a vertical height of the bottom electrode cup sidewall142may be shortened (e.g., using a sputter etch process) to allow the formation of the insulator flange146extending laterally over the bottom electrode cup sidewall upper surface143. The insulator flange146prevents or reduces shorting between the top electrode122and bottom electrode120. In the illustrated example, insulator flange146is arranged between the bottom electrode cup sidewall upper surface143and the top electrode cap region158, to thereby insulate the bottom electrode cup sidewall upper surface143from the top electrode122.

In another example, e.g., as shown inFIG.3discussed below, the top electrode cap region158over the insulator flange146is excluded (e.g., removed by a deeper or more aggressive planarization at the step shown inFIG.2Idiscussed below), insulator flange146is arranged between the bottom electrode cup sidewall upper surface143and the top electrode connection pad160, to thereby insulate the bottom electrode cup sidewall upper surface143from the top electrode connection pad160, and thereby insulate the bottom electrode cup sidewall upper surface143from an indirect connection to the top electrode122via the top electrode connection pad160.

Based on the above, the lower interconnect element110of interconnect structure104and the bottom electrode base134of the MIM capacitor module102may each comprise a metal structure formed concurrently in the lower metal layer Mx. Similarly, the upper interconnect element112of interconnect structure104, and the top electrode connection pad160and bottom electrode connection pad162of the MIM capacitor module102, may each comprise a metal structure formed concurrently in the upper metal layer Mx+1.

Each of the lower metal layer Mxand upper metal layer Mx+1may comprise any metal or metalized layer or layers. For example, each of the lower metal layer Mxand upper metal layer Mx+1may comprise a copper or aluminum interconnect layer, bond pad layer, or other metal layer. As another example, the lower metal layer Mxmay be a silicided polysilicon layer (e.g., where Mxis M0), as discussed below.

Metal structures may be formed in the lower metal layer Mxand upper metal layer Mx+1, respectively, in any suitable manner, for example using a subtractive patterning process (e.g., deposition, patterning, and etching of a metal layer), or using a damascene process, or by forming a metal silicide region on patterned polysilicon regions, or any other suitable process.

In the example shown inFIG.1, lower interconnect element110and bottom electrode base134comprise aluminum structures formed in lower metal layer Mx(using a subtractive patterning process); top electrode122comprises an aluminum structure formed in via layer Vx(using a damascene process); and upper interconnect element112, top electrode connection pad160, and bottom electrode connection pad162comprise aluminum structures formed in upper metal layer Mx+1(using a subtractive patterning process).

In another example, lower interconnect element110and bottom electrode base134are formed in a silicided polysilicon layer Mx, e.g., wherein Mx=M0. In such example, lower interconnect element110and bottom electrode base134respectively comprise a metal silicide region formed on a respective polysilicon region.

Thus, the bottom electrode cup136, insulator124, top electrode122, and bottom electrode contact164may be formed concurrently with the interconnect vias114in the via layer Vxbetween the lower metal layer Mxand upper metal layer Mx+1, e.g., using a damascene process as discussed below, and without adding any additional photomasks to the background IC fabrication process.

FIGS.2A-2Jshow an example method of forming the example IC structure100shown inFIG.1, including MIM capacitor module102and interconnect structure104. As noted above, in other examples, the interconnect structure104may be optional, such that MIM capacitor module102may be formed by the process described below but with the elements of interconnect structure104.

As shown inFIG.2A, the lower interconnect element110and the bottom electrode base134are formed in the lower metal layer Mx. In this example, the lower metal layer Mxmay comprise a metal interconnect layer, wherein the lower interconnect element110and bottom electrode base134are respectively formed as metal elements (e.g., aluminum elements). In another example, e.g., as shown inFIG.4discussed below, the lower metal layer Mxmay comprise a silicided polysilicon layer, wherein the lower interconnect element and bottom electrode base respectively comprise a silicide region formed on a respective polysilicon structure.

Dielectric region170(e.g., an Inter Metal Dielectrics (IMD) region or Poly Metal Dielectrics (PMD) region) is formed over the lower interconnect element110and bottom electrode base134formed in lower metal layer Mx. Dielectric region170may include one or more dielectric materials, e.g., silicon oxide, PSG (phosphosilicate glass), or FSG (fluorine doped glass), or a combination thereof.

Via layer openings200, including interconnect via openings202, a tub opening204, and a bottom electrode contact opening206, may be patterned (using a photomask) and etched in the dielectric region170. Via layer openings200may be formed using a plasma etch or other suitable etch, followed by a resist strip or other suitable process to remove remaining portions of photoresist material.

The interconnect via openings202may be via openings having a width (or diameter or Critical Dimension (CD)) Wviain both the x-direction and y-direction in the range of 0.1-0.5 μm, for example. The interconnect via openings width Wviamay significantly affect the performance of the IC device being formed.

The bottom electrode contact opening206may be formed as a via opening with a width (or diameter or Critical Dimension (CD)) Wcontact. In some examples, the bottom electrode contact opening206is formed the same as each of the interconnect via openings202, thus Wvia=Wcontact, and may have similar dimensions in both the x-direction and y-direction.

In contrast, tub opening204may have a substantially larger width in the x-direction (Wtub_x) and/or y-direction (Wtub_y) than interconnect via openings202and the bottom electrode contact opening206. The shape and dimensions of the tub opening204may be selected based on various parameters, e.g., for effective manufacturing of the MIM capacitor module102(e.g., effective deposition of the top electrode material (e.g., aluminum) into the tub opening204) and/or for desired performance characteristics of the resulting MIM capacitor module102. In one example, the tub opening204may have a square or rectangular shape from the top view. In other examples, tub opening204may have a circular or oval shape from the top view.

As noted above, a width of tub opening204in the x-direction (Wtub_x) y-direction (Wtub_y), or both the x-direction and y-direction (Wtub_xand Wtub_y) may be substantially larger than the width Wviaof interconnect via openings202in the x-direction, y-direction, or both the x-direction and y-direction. For example, in some examples, each width Wtub_xand Wtub_yof tub opening204is at least twice as large as the width Wviaof interconnect via openings202. In particular examples, each width Wtub_xand Wtub_yof tub opening204is at least five time as large or at least 10 times as large as the width Wviaof interconnect via openings202. In some examples, Wtub_xand Wtub_yare each in the range of 1-100 μm.

Further, tub opening204may be formed with a height-to-width aspect ratio of less than or equal to 1.0 in both the x-direction and y-direction, e.g., to allow effective filling of the tub opening204by conformal materials. For example, tub opening204may be formed with aspect ratios Htub/Wtub_xand Htub/Wtub_yrespectively in the range of 0.01-1.0, for example in the range of 0.1-1.0. In some examples, aspect ratios Htub/Wtub_xand Htub/Wtub_yare respectively less than or equal to 1.0, e.g., for effective filling of tub opening204by conformal materials, e.g., tungsten or silicon nitride. For example, tub opening204may be formed with aspect ratios Htub/Wtub_xand Htub/Wtub_yrespectively in the range of 0.1-1.0, or more particularly in the range of 0.5-1.0.

Next, as shown inFIG.2B, a liner (or “glue layer”)166, e.g., comprising TiN, is deposited over the structure and extending into respective via layer openings200. A conformal metal layer210is deposited over the liner166and extending into respective via layer openings200, filling respectively interconnect via opening202, filling the bottom electrode contact opening206, and forming a cup-shaped conformal metal layer region212in the tub opening, extending down from a lateral conformal metal layer region214, the lateral conformal metal layer region214extending laterally outwardly from a top of the cup-shaped conformal metal region212. In one example, the conformal metal layer210comprises tungsten deposited with a thickness in the range of 1000 Å-5000 Å. In other examples, the conformal metal layer210may comprise Co, TiN, or other conformal metal. The conformal metal layer210may be deposited by a conformal chemical vapor deposition (CVD) process or other suitable deposition process.

Next, a vertical height of the cup-shaped conformal metal layer region212may be shortened by removing a corner region220of the conformal metal layer210at a corner defined between the cup-shaped conformal metal layer region212and the lateral conformal metal layer region214.

FIGS.2C-2Eshow one example process for removing the corner region220of the conformal metal layer210. As shown inFIG.2C, a High Density Plasma Chemical Vapor Deposition (HDP CVD) oxide deposition process is performed with an enhanced sputter etch to form an oxide layer224covering the conformal metal layer210except over the corner region220of the conformal metal layer210, thus defining a corner opening226over the corner region220.

A particular characteristic of an HDP CVD deposition process is enhanced sputter etch at external corners, typically for the purpose of achieving a desired gap fill (while avoiding bread loading that may result in a sealed keyhole). The present process may utilize this enhanced sputter etch characteristic of HDP CVD deposition. In some examples, by selecting or setting an effective ratio between oxide deposition and sputter etch components of an HDP CVD process, a desired corner oxide removal can be achieved, to provide a corner opening226exposing the corner region220of the conformal metal layer210.

Next, as shown inFIG.2D, the corner region220of the conformal metal layer210(e.g., tungsten), along with the underlying liner166(e.g., TiN) is etched through the corner opening226in the overlying oxide layer224. In some examples, a dry etch (plasma etch) is performed, for example (in the case where the conformal metal layer210comprises tungsten) an SF6 based W Etch Back (WEB) process with high selectivity to oxide. In other examples, a wet etch is performed, e.g., a hydrogen peroxide (H2O2) etch at an elevated temperature, e.g., 50° C. with very high selectivity to oxide.

A remaining portion of the cup-shaped conformal metal layer region212defines the bottom electrode cup136including the laterally-extending bottom electrode cup base140and the bottom electrode cup sidewall142extending upwardly from the laterally-extending bottom electrode cup base140, wherein the upper surface143of the bottom electrode cup sidewall142is exposed. As shown, the bottom electrode cup sidewall142is vertically shortened by the removal (etch) of the conformal metal layer corner region220.

Next, as shown inFIG.2E, the remaining oxide layer224is removed, for example by a wet strip (e.g., a very short diluted hydrofluoric acid (HF) dip) or a dry etch (e.g., an isotropic fluorine-based oxide etch).

As an alternative to the process shown inFIGS.2C-2E, the corner region220of the conformal metal layer210(e.g., comprising tungsten) may be removed by a direct sputter etch in an HDP chamber. Such direct sputter etch may be particularly effective for a relatively thin conformal metal layer210, e.g., having a thickness in the range of 1000 Å-2000 Å.

Next, as shown inFIG.2F, an insulator layer230is deposited over remaining portions of the conformal metal layer210. The deposited insulator layer230defines (a) the insulator cup144in an opening137defined by the bottom electrode cup136and (b) the insulator flange146extending laterally outwardly from the insulator cup144and extending laterally over the upper surface143of the bottom electrode cup sidewall142. In some examples, insulator layer230may comprise silicon nitride (SiN) deposited with a thickness in the range of 250-750 Å by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. Alternatively, insulator layer230may comprise Al2O3, ZrO2, HfO2, ZrSiOx, HfSiOx, HfAlOx, or Ta2O5, or other suitable capacitor insulator material deposited using an Atomic Layer Deposition (ALD) process.

Next, as shown inFIG.2G, a top electrode layer240is deposited over the insulator layer230and extends into and fills an interior opening145defined by the insulator cup144. In some examples, top electrode layer240may comprise Al, Ti, TiN, W, or a combination thereof, for example TiN and Al, and may be deposited by a physical vapor deposition (PVD) process. The top electrode layer240includes the top electrode cap region158extending over the insulator flange146, such that the insulator flange146is arranged between the top electrode cap region158and the upper surface143of the bottom electrode cup sidewall142.

Next, as shown inFIGS.2H and2I, a chemical mechanical planarization (CMP) process is performed to remove upper portions of the top electrode layer240, insulator layer230, and conformal metal layer210.FIG.2Hshows a top view of the resulting structure after the CMP process, andFIG.2Ishows a side cross-sectional view taking through line2I-2I shown in FIG.2H. The CMP process defines a planarized top surface172including a planarized top surface250of the top electrode layer122. After the CMP process, a remaining portion of the top electrode layer240defines the final form of the top electrode122, and a remaining portion of the insulator layer230defines the final form of the insulator124including the insulator cup144and insulator flange146.

As shown inFIGS.2H and2Iviewed together, the bottom electrode cup136includes a bottom electrode cup base140having a rectangular shape, and the bottom electrode cup sidewall142includes four bottom electrode cup sidewall sections142a-142dextending upwardly (in the z-direction) from the rectangular bottom electrode cup base140and defining a closed-loop rectangular shape (in an x-y plane) of the bottom electrode cup sidewall142. Similarly, the insulator cup144includes a laterally-extending insulator cup base148having a rectangular shape, and the insulator cup sidewall150includes four insulator cup sidewall sections150a-150dextending upwardly (in the z-direction) from the rectangular laterally-extending insulator cup base148and defining a closed-loop rectangular shape (in an x-y plane). The insulator flange146extends laterally outwardly (in the x-direction) from an upper edge152of the insulator cup sidewall150, around the rectangular perimeter (in the x-y plane) of the insulator cup sidewall150, such that the insulator flange146covers the upper surface143of the bottom electrode cup sidewall142around the rectangular perimeter (in an x-y plane) of the bottom electrode cup sidewall142. The insulator flange146may extend laterally outwardly (in the x-direction) from an upper edge152of the insulator cup sidewall150, around the full rectangular perimeter (in the x-y plane) of the insulator cup sidewall150, such that the insulator flange146covers the upper surface143of the bottom electrode cup sidewall142around the full rectangular perimeter (in an x-y plane) of the bottom electrode cup sidewall142.

By reducing the height of the bottom electrode cup sidewall142and forming an insulator124having an insulator flange146extending over the upper surface143of the bottom electrode cup sidewall142, a top electrode connection pad may be formed directly on the planarized top surface250of the top electrode122without creating a short with the bottom electrode120.

Thus, as shown inFIG.2J, an upper metal layer (Mx+1layer) may be formed on the planarized upper surface172of the via layer Vx. Various metal elements are formed in the upper metal layer Mx+1(e.g., by a metal deposition, pattern, and etch process) including (a) the upper interconnect element112connected to interconnect vias114, (b) the top electrode connection pad160connected to the top electrode122, and (c) the bottom electrode connection pad162connected to the bottom electrode contact164. The upper metal layer Mx+1may comprise aluminum or other suitable metal. As shown, the top electrode connection pad160may be formed directly on the planarized top surface250of the top electrode122, and may be insulated from the bottom electrode cup136by the insulator flange146, to thereby prevent electrical shorts between the top connection pad160(and thus the top electrode122) and the bottom electrode120.

As shown inFIG.2H, interconnect vias114and bottom electrode contact164may have a circular shape in the top view. In other examples, interconnect vias114and/or bottom electrode contact164may have any other shape in the top view, e.g., a square or rectangular shape.

FIG.3is a side cross-sectional view showing an example IC structure300including a MIM capacitor module302and interconnect structure104formed concurrently, according to one example. As shown, MIM capacitor module302is similar to MIM capacitor module102shown inFIG.1and discussed above, with similar parts. However, the top electrode322of IC structure300omits the top electrode cap region158of the top electrode322(extending over insulator flange146) of IC structure100discussed above. For example, the top electrode cap region158may be removed by a deeper or more aggressive planarization at the step shown inFIG.2Idiscussed above. Thus, in IC structure300, insulator flange146is arranged between the bottom electrode cup sidewall upper surface143and the top electrode connection pad160, to thereby insulate the bottom electrode cup sidewall upper surface143from the top electrode connection pad160. Thus, the bottom electrode cup sidewall upper surface143is electrically insulated from the top electrode122through the top electrode connection pad160.

FIG.4is a side cross-sectional view showing an example IC structure400including an MIM capacitor module402and an interconnect structure404formed on a lower metal layer Mxcomprising a silicided polysilicon layer. In this example, a lower interconnect element410of interconnect structure404and the bottom electrode base434of the MIM capacitor module402may each comprises a metal silicide region formed on a respective polysilicon region. In particular, lower interconnect element410comprises a first metal silicide region422aformed on a first polysilicon region420a, and bottom electrode base434comprises a second metal silicide region422bformed on a second polysilicon region420b.