Patent ID: 12248021

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

One or more specific embodiments of the present disclosure will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure. The techniques presented and claimed herein are referenced and applied to material objects and concrete examples of a practical nature that demonstrably improve the present technical field and, as such, are not abstract, intangible or purely theoretical.

When introducing elements of various embodiments of the present disclosure, the articles “a,” “an,” and “the” are intended to mean that there are one or more of the elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that references to “one embodiment” or “an embodiment” of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features. Furthermore, the phrase A “based on” B is intended to mean that A is at least partially based on B. Moreover, unless expressly stated otherwise, the term “or” is intended to be inclusive (e.g., logical OR) and not exclusive (e.g., logical exclusive-OR (XOR)). In other words, the phrase A “or” B is intended to mean A, B, or both A and B.

Programmable logic devices are increasingly permeating markets and are increasingly enabling customers to implement circuit designs in logic fabric (e.g., programmable logic). Due to the highly customizable nature of programmable logic devices, the logic fabric is to be configured with a circuit design prior to use of the circuit corresponding to the circuit design. When implementing designs in the logic fabric, sectors may be used to allocate portions of the logic fabric to implement the circuit. However, a sector may be a relatively imprecise and/or large allocation of total logic fabric area due at least in part to data registers and physical arrangements of interconnections of the programmable logic device.

By rearranging some of the interconnections of the programmable logic device and/or by shrinking a data width of the data registers, systems and processes for implementing a circuit design in logic fabric may improve. For example, by making some of these changes, a size of the sector may be reduced and form a microsector, permitting a relatively finer granularity of assignment to be used to allocate the logic fabric to the circuit design. This may, for example, permit a more efficient allocation of resources to respective circuit designs, and thus enable circuit designs to use less resources in implementation.

Since a circuit design for a programmable logic device may be customized by a user for a particular application, the ability to partition and control the configuration of the device at a fine grain and/or in parallel (as may be afforded by rearrangement of the interconnections and/or shrinking of a data width of data registers) enables a number of advantages particular to devices with programmable logic. Some of the advantages may be in the construction of the device and some advantages are in the use models for the device that are enabled (e.g., enabled or permitted use cases). For construction of the device, fine-grained configurable regions may be a mechanism to enable building a device with a suitable or tailored amount of resources for implementation of that device. Some of the new use models are enabled by faster configuration, faster partial reconfiguration, and faster single-event update (SEU) detection for smaller regions of the device when compared to other systems and methods for programmable logic device programming.

These changes in system implementation may also improve (e.g., reduce) overall configuration times, including reducing configuration times used when performing partial reconfigurations, and may also enable faster single-event upset (SEU) detection. For example, the proposed structural changes described herein may enable partial reconfiguration to occur in similar amounts of time as a normal configuration.

The microsector infrastructure may use a smaller number of columns (e.g., 8 columns vs 50 columns) in a single fabric row (row region). The row region may receive data from a smaller data register (e.g., 1-bit data register as opposed to a 32-bit data register). Since a microsector may represent a relatively small percentage of area of a programmable logic device (e.g., less than 1% of total fabric area), it may be feasible to have the microsector become the partial reconfiguration quanta. This may enable the partial reconfiguration to be a write-only operation that avoids performing a read-modify-write each time partial reconfiguration is to occur for the microsector, thereby saving time and resources for the partial reconfiguration. In some cases, the partial reconfiguration time may be reduced by a factor of five or six, a relatively high amount of performance improvement. Furthermore, since the number of columns is reduced, the amount of time spent waiting for a data transmission to complete (either to the row region or from the row region) may reduce, thereby improving operation of the programmable logic device.

A microsector architecture may be combined with network-on-chip (NOC) data transmission methods. Standard NOC implementations are sometimes inefficiently applied field programmable gate arrays (FPGAs) or other programmable logic devices. For example, these implementations do not account for repetitive nature of the FPGA programmable logic, nor account for aspect ratio differences and data density implications of connecting to FPGA programmable logic with a standard NOC. Thus, merely using programmable logic with a standard NOC may limit usability, may reduce available transaction bandwidths, and may increase latencies.

This disclosure describes an interface that enables communication between programmable logic having a microsector architecture and a NOC, while avoiding adverse effects from interfacing the two. In particular, this disclosure describes data transactions associated with a microsector architecture that may use one or more micro-network-on-chips (microNOCs) disposed within unused wire tracks of the microsector architecture to form a columnar-oriented networked structure that uses extensible data handling processes. The columnar-oriented networked structure is a repetitive structure used to interface between programmable logic and one or more NOCs, which fits within programmable logic memory columns (e.g., FPGA fabric memory columns). The extensible columnar-oriented networked structure may permit high bandwidth and relatively complex data transactions similar to transactions performed using a network-on-chip (NOC) but without burdening the device with a large footprint or a performance penalty. These benefits may be provided natively with the architecture and independent of any further performance optimizations made by a complier or during a programmable logic design process.

Indeed, described herein are structures that provide one or more microNOCs as well as methods that may be used to address specific microNOCs or specific devices of a microNOC (i.e., specific microsectors). These systems and methods may provide a control mechanism to request loading and unloading of specific memories associated with specific microNOCs (e.g., specific memories of specific row controllers) to or from on-chip memories or off-chip memories. Furthermore, these system and methods may dramatically reduce the complexity of routing of high-bandwidth data buses between memory and into programmable logic (e.g., deeply located configuration memory) while increasing ease of use for customers and control systems implementing the transactions. Reducing system complexity may cause reduced power consumption and more efficient resource consumption within an integrated circuit performing these memory transactions. Indeed, these systems and methods may reduce power consumption amounts associated with moving data from off-chip memory interfaces to programmable logic by using dedicated bussed routing to portions of the microNOCs, as opposed to soft logic routing. It is noted that soft logic routing uses relatively large quantities of flip-flops and/or latches to exchange data, which may increase latencies with data transmissions and may depend on a distributed clocking signal network propagating clocks with aligned timings. By reducing an amount soft logic-based routing used to transmit data, data transmissions may happen faster with less of a reliance on precise clocking alignments and with the additional benefit of freeing up soft logic for other uses.

A microNOC may include a column of row controllers each connected to a shared data path (e.g., a shared vertical data path) and a respective microsector. The data path and the row controllers of the microNOC may include hardened logic. The row controller may include hardened logic, which interfaces with the hardened logic and the soft logic of the microsector. The row controller may communicate with controllers disposed outside of a programmable logic by way of messages transmitted via the shared data path. These messages may include transaction-related data, headers, command indications, slots for data to be stored in, or the like, to communicate between the row controllers and other devices, such as devices external to the microsector, other row controllers, or even portions of programmable logic programmed to perform a logic function.

Data may be transmitted to one or more microsectors using data streaming protocols and using bi-directional movements. In this way, one or more row controllers may inspect a header of a packet before accessing a payload of the packet to determine which of the row controller the packet is to be delivered. When a row controller finds a packet has a header matching its own identifier, the row controller may receive the packet and process any data and/or command included in the packet. This structure may help improve transaction speeds since multiple concurrent traffic flows in one or two data movement directions may occur even within a same column of microsectors. For example, the microNOC includes a shared data path that uses data streaming processes to deliver different commands to different row controllers at a same time by segregating command delivery in different packets with different headers.

A microNOC, a column manager, and/or a row controller may each be individually addressed using a logical address described herein. This may enable direct access to a location in programmable memory by direct addressing to its corresponding row controller. A logical address space is discussed herein. Using the logical address space to address a packet to a specific row controller in combination with routing circuitry between column managers and paths to microNOCs may enable any peripheral device in communication with a NOC and/or any column manager to communicate with the specific row controller.

Indeed, as discussed herein, data transactions may occur between a row controller and any suitable data source and/or end point using direct addressing. This may let, for example, a logic design implemented in a portion of programmable logic generate an instruction to cause a reading or writing of data to another portion of programmable logic. Each column manager may help perform several types of transactions, and each type of transaction may use the direct addressing process. These transactions may include a directly addressed read, a directly addressed write, a first-in, first-out (FIFO) read (e.g., streaming read), a FIFO write (e.g., streaming write), a load (e.g., plural write, batch write), and an unload (e.g., plural read, batch read).

Transactions involving directly addressed reads or writes may use addresses from a global address space that reference specific row controllers (or groups of row controllers) to access data stored in microsectors. These transactions may read or write any suitable number of words from any location in any enabled row controller (e.g., a row controller having an address assigned). Transactions involving FIFO reads or writes may continuously stream data to or from one or more row controllers and to or from another device (e.g., an on-chip memory, an off-chip memory, one or more processors). Moreover, transactions involving loads or unloads may perform a block movement between one or more row controllers and another device (e.g., an on-chip memory, an off-chip memory, one or more processors).

Direct addressing methods and data streaming methods may permit a relatively large amount data to transmit between programmable logic and a data source (or data end point). For example, a column manager directly addressing one or more row controllers and/or one or more microNOCs for a transaction may improve processing speeds associated with moving data for machine learning uses, signal processing uses, graphic processing unit (GPU) calculations, and/or other data intensive uses by simplifying these otherwise complex transactions.

Another benefit from using addressing methods and the microNOCs described herein includes the ability to store data in a different order than a logical read and/or write order. Data may be read from a register of a column manager in a logical order. But, the data may be read from the programmable logic in a different order than the logical order. The feature of being able to read and write data into the different row controllers in an order differing from this logical order represents a dramatic improvement in memory access, and more particularly, programmable logic access methods. This is an improvement beyond typical processes than involve reading and writing data into programmable logic according to the logical order. Being able to store data in any order may permit column managers to store the data in a convenient order for the operation rather than being restricted to the logical order. Thus, the column managers may have the capability to pack data in a single microNOC column or according to data striping processes across multiple microNOC columns, in whichever order is deemed more convenient (e.g., of lower cost, of lower memory usage overall, of lesser footprint) by the column manger and/or system overall.

With the foregoing in mind,FIG.1illustrates a block diagram of a system10that may implement arithmetic operations. A designer may desire to implement functionality, such as the arithmetic operations of this disclosure, on an integrated circuit12(e.g., a programmable logic device such as a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC)). In some cases, the designer may specify a high-level program to be implemented, such as an OPENCL® program, which may enable the designer to more efficiently and easily provide programming instructions to configure a set of programmable logic cells for the integrated circuit12without specific knowledge of low-level hardware description languages (e.g., Verilog or VHDL). For example, since OPENCL® is quite similar to other high-level programming languages, such as C++, designers of programmable logic familiar with such programming languages may have a reduced learning curve than designers that are required to learn unfamiliar low-level hardware description languages to implement new functionalities in the integrated circuit12.

The designer may implement high-level designs using design software14, such as a version of INTEL® QUARTUS® by INTEL CORPORATION. The design software14may use a compiler16to convert the high-level program into a lower-level description. The compiler16may provide machine-readable instructions representative of the high-level program to a host18and the integrated circuit12. The host18may receive a host program22which may be implemented by the kernel programs20. To implement the host program22, the host18may communicate instructions from the host program22to the integrated circuit12via a communications link24, which may be, for example, direct memory access (DMA) communications or peripheral component interconnect express (PCIe) communications. In some embodiments, the kernel programs20and the host18may enable configuration of a logic block26on the integrated circuit12. The logic block26may include circuitry and/or other logic elements and may be configured to implement arithmetic operations, such as addition and multiplication.

The designer may use the design software14to generate and/or to specify a low-level program, such as the low-level hardware description languages described above. Further, in some embodiments, the system10may be implemented without a separate host program22. Moreover, in some embodiments, the techniques described herein may be implemented in circuitry as a non-programmable circuit design. Thus, embodiments described herein are intended to be illustrative and not limiting.

Turning now to a more detailed discussion of the integrated circuit12,FIG.2is a block diagram of an example of the integrated circuit12as a programmable logic device, such as a field-programmable gate array (FPGA). Further, it should be understood that the integrated circuit12may be any other suitable type of programmable logic device (e.g., an ASIC and/or application-specific standard product). The integrated circuit12may have input/output circuitry42for driving signals off device and for receiving signals from other devices via input/output pins44. Interconnection resources46, such as global and local vertical and horizontal conductive lines and buses, and/or configuration resources (e.g., hardwired couplings, logical couplings not implemented by user logic), may be used to route signals on integrated circuit12. Additionally, interconnection resources46may include fixed interconnects (conductive lines) and programmable interconnects (i.e., programmable connections between respective fixed interconnects). Programmable logic48may include combinational and sequential logic circuitry. For example, programmable logic48may include look-up tables, registers, and multiplexers. In various embodiments, the programmable logic48may be configured to perform a custom logic function. The programmable interconnects associated with interconnection resources may be considered to be a part of programmable logic48.

Programmable logic devices, such as the integrated circuit12, may include programmable elements50with the programmable logic48. For example, as discussed above, a designer (e.g., a customer) may (re)program (e.g., (re)configure) the programmable logic48to perform one or more desired functions. By way of example, some programmable logic devices may be programmed or reprogrammed by configuring programmable elements50using mask programming arrangements, which is performed during semiconductor manufacturing. Other programmable logic devices are configured after semiconductor fabrication operations have been completed, such as by using electrical programming or laser programming to program programmable elements50. In general, programmable elements50may be based on any suitable programmable technology, such as fuses, antifuses, electrically-programmable read-only-memory technology, random-access memory cells, mask-programmed elements, and so forth.

Many programmable logic devices are electrically programmed. With electrical programming arrangements, the programmable elements50may be formed from one or more memory cells. For example, during programming, configuration data is loaded into the memory cells using input/output pins44and input/output circuitry42. In one embodiment, the memory cells may be implemented as random-access-memory (RAM) cells. The use of memory cells based on RAM technology is described herein is intended to be only one example. Further, since these RAM cells are loaded with configuration data during programming, they are sometimes referred to as configuration RAM cells (CRAM). These memory cells may each provide a corresponding static control output signal that controls the state of an associated logic component in programmable logic48. For instance, in some embodiments, the output signals may be applied to the gates of metal-oxide-semiconductor (MOS) transistors within the programmable logic48.

Keeping the discussion ofFIG.1andFIG.2in mind, a user (e.g., designer) may utilize the design software14to implement the logic block26on the programmable logic48of the integrated circuit12. In particular, the designer may specify in a high-level program that mathematical operations such as addition and multiplication be performed. The compiler16may convert the high-level program into a lower-level description that is used to program the programmable logic48to perform addition.

Once programmed, the integrated circuit12may process a dataset60, as is shown inFIG.3.FIG.3is a block diagram of an application system62that includes the integrated circuit12and memory64. The application system62may represent a device that uses the integrated circuit12to perform operations based on computational results from the integrated circuit12, or the like. The integrated circuit12may directly receive the dataset60. The dataset60may be stored into the memory64before, during, or concurrent to transmission to the integrated circuit12.

As bandwidths and processing expectations increase, such as in response to the advent of fifth generation (5G) and higher communication techniques and/or widespread use of neural networks (e.g., machine learning (ML) and/or artificial intelligence (AI) computations) to perform computations, the integrated circuit12may be expected to handle subsequent increases in size of the dataset60over time. The integrated circuit12may also be expected to perform digital signal processing operations of signals transmitted using 5G or higher techniques (e.g., signals of higher throughput and/or high data transmission bandwidths) and ML operations. These desired applications may also be implemented dynamically, during runtime, such as during a partial reconfiguration that causes configuration of a portion of the integrated circuit12without causing configuration of another portion of the integrated circuit12during runtime operations of the integrated circuit. For at least these reasons, it may be desired to improve configuration methods to meet complexity and timing specifications of technical computations. To do so, programmable logic66that includes at least the programmable logic48, the input/output pins44, and interconnection resources46, may leverage a1-bit data register to (re)configure the programmable logic48using microsectors. Using microsectors to program circuitry functions in the programmable logic48may provide the advantages of enabling write-only reconfiguration, relatively smaller region SEU detection (e.g., 1-bit region of detection), relatively smaller granularities for reconfiguration regions, and relatively larger parallel configuration (e.g., parallel configuration of data channels of 1-bit width) operations. As used herein, the term microsector refers to a sector of programmable logic that has a data register that is comparatively small. In one example, a microsector has a 1-bit data register. In some embodiments, a microsector may have a larger data register, but still may be smaller than what is ordinarily found in a sector (e.g., may be less than 32 bits, less than 16 bits, less than 8 bits).

To elaborate regarding the smaller granularities for reconfiguration regions,FIG.4Ais a block diagram of example programmable logic66. The programmable logic66may include a controller76to program the programmable logic66. When programmed, the circuitry of the programmable logic66may be used to perform digital signal processing, machine learning processing, computations, logic functions, or the like (e.g., represented by portion78). However, the programmable logic66may be divided in relatively large logical sectors, and thus a portion80may be allocated to the circuitry as opposed to a region of circuitry corresponding to the portion78. This overallocation of resources may waste circuitry since size differences between the portion80and the portion78represent underutilized programmable logic66. It is noted that when partially reconfiguring programmable logic66, certain speed metrics may be desired to be met (e.g., partial reconfiguration may be desired to be completed in a relatively fast amount of time). In these cases, for example, overallocation of resources may occur since slower configuration speeds may be undesired that may improve allocation of resources.

Indeed, if a device is built in the programmable logic of a multiple of sectors, the device may likely have more or less logic (e.g., logic arithmetic blocks (LABs), digital signal processing (DSP) blocks) than is desired to be allocated to building the device. This overallocation may occur since a rectangular number of sectors is used to implement the example device. By rearranging the interconnections and/or shrinking a data width of data registers to form microsectors, a relatively more exact amount of logic (e.g., more accurate number of LABs or DSP blocks) may be allocated to implementation of the device.

When implementing circuitry represented by the portion78in programmable logic66that uses microsector logical divisions, as shown inFIG.4B, less programmable logic66may be wasted when implementing the circuitry.FIG.4Bis a block diagram of the programmable logic66implemented using microsectors. Indeed, microsectors may permit the circuitry corresponding to the portion78to be implemented in a region represented by portion82. Although not drawn to scale, the portion82implementing circuitry corresponding to the portion78efficiently utilizing the programmable logic66where the portion80implementing the portion78may otherwise inefficiently utilize the programmable logic66.

To elaborate further on a microsector architecture,FIG.5is a block diagram of the programmable logic66. The programmable logic66may couple between microsectors92using the interconnection resources46. Indeed, the interconnection resources46may include any suitable combination of data shifting registers, registers, logical gates, direct couplings, reprogrammable circuitry, or the like able to be used to move data from a first location to a second location within the programmable logic66and/or within the integrated circuit12. One or more microsectors92may be programmed by the controller76with information to perform functions of circuitry, such as the circuitry corresponding to portion78. However, since the controller76may transmit configuration data (or any suitable data), the granularity of regions used to program functions into the programmable logic66may reduce. When these granularities reduce or become more precise (e.g., smaller), programming of the programmable logic66may improve since circuit designs may be more efficiently configured in the programmable logic66. It is noted that the programmable logic66and/or the integrated circuit12may be any suitable type of software or hardware, or a combination of the two. The integrated circuit12and/or the programmable logic66may be or include programmable logic48, programmable elements50, or the like, to enable one or more portions to be reprogrammable (e.g., reconfigurable). The controller76may interface with the microsectors92using the interconnection resources46that may include interface buses, such as an advanced interface bus (AIB) and/or an embedded multi-die interconnect bridge (EMIB). As described above, the programmable logic66may be a reprogrammable circuit capable of performing a multitude of tasks.

FIG.6is a block diagram of two example microsectors92(e.g., microsector92A, microsector92B). This application describes a particular architecture of microsectors92; however, it should be understood that any suitable architecture may be used. Indeed, each microsector92may include one or more logic access blocks (LAB)104(e.g., eight LABs) able to interface with the interconnection resources46(shown here to communicate with the microsectors92via an address register106(AR)). Indeed, the interconnection resources46may include one or more ARs106to transmit and/or receive signals from the microsectors92, as well as or in alternative of other control circuitry, logic circuitry (e.g., AND gates, OR gates, not-OR gates, exclusive-OR gates, flip-flops, switch-reset latches), or the like. It should also be understood that same or similar circuitry may be included in each microsector92.

The LABs104may receive data from the AR106through an address line buffer (ALB)108. The ALBs108may each include digital signal processing (DSP) circuitry and/or control circuitry that converts data from a suitable format for transmission to the microsector92A to a suitable format for use by circuitry of the LAB104.

Each LAB104may include some number of arithmetic logic element circuitry (ALE)110circuits (e.g., ten ALEs110). A micro-data register (μDR)112may be disposed on at least some of the ALEs110, such as in another layer of silicon, or other material, used to physically form the integrated circuit. The μDR112communicatively couples each LAB104to the ALB108. Each ALE110of the LAB104may share and/or couple to the LAB-wide Control Block (LCB)114. The LABs104are separated from each other by routing fabric116(e.g., configuration random access memory (CRAM), configuration memory). In this example, the μDR112runs through the LCB114via a center of a row of circuitry corresponding to the microsector92A.

To elaborate further on interconnections between the AR106and the microsectors92,FIG.7is a block diagram of rows regions (row regions)124and row controllers126implemented in the AR106illustrating communicative couplings between the row controllers126and the microsectors92fromFIG.6. It is noted that microsectors92may sometimes be referred to in terms of row regions124since designs like manufacturer designs (e.g., manufacturer IP) or user designs (e.g., user IP) may be loaded into the microsectors92for implementation. The AR106may include any suitable control system circuitry and/or logic circuitry. Indeed, the AR106may be an address register from INTEL® STRATIX10® or INTEL® AGILEX® by INTEL CORPORATION. Furthermore, the AR106shown is disposed between at least two microsectors92. There are some instances where the AR106may be disposed by just one column region128of microsectors92(e.g., orientated on the right side of the AR106or on the left side of the AR106) to accommodate physical boundaries of the programmable logic66or the integrated circuit12or to avoid supporting left and right data movement patterns. The various row regions124and column regions128are arranged as a grid on a same physical board.

Each row controller126may control a row region124of microsectors, and thus be associated with or be the ALB108described earlier. For the microsector implementation, the AR106may be repeated and shared between column region128(e.g., column region128A, column region128B, column region128C, column region128D) of microsectors92. For example, column region128A shares an AR106A with the column region128B, and is disposed adjacent to a column region128C. The microsectors92of the column region128C may share the AR106B with microsectors92of the column region128D. Thus, the microsectors92of column region128C may be controlled using signals generated and/or transmitted by the row controllers126of the AR106B independent of at least some signals transmitted via the AR106A. Although part of a same row region124, the microsector92C may be controlled differently from the microsector92B since the microsectors92being associated with different column region128. Furthermore, although part of a same column region (e.g., column region128C), the microsector92C may be controlled differently from the microsector92D since the microsectors92receive control signals from separate row controllers126(e.g., row controller126A, row controller126B). Microsectors92may be formed to divide the row region124into smaller portions, and thus provide the smaller granularity.

The row controllers126may use any suitable communication protocol to transmit and/or receive signals from respective microsectors92. For example, the row controllers126may use a streaming protocol, such as Advanced eXtensible Interface (AXI) 4 Streaming, to receive an address and data corresponding to the address in a same symbol (e.g., same packet transmission) at internal write registers (e.g., internal to a respective row controller126).

Each AR106may include a local sector manager (LSM)130(e.g., LSM130A, LSM130B) at the bottom or top of the AR106column region to interface with its corresponding CM132. For example, the LSM130A is shown at the top of and communicatively coupled to the AR106A column region and the CM132A. The LSM130A is also disposed outside of the programmable logic66. One LSM130may be included per AR106, however it should be understood that LSMs130may be shared by two or more AR106, such that one LSM130controls two or more AR106.

Sometimes, the LSMs130may be integrated with an AR column manager (CM)132(e.g., CM132A, CM132B) to form respective sector column managers (SCM). Although depicted as separate blocks, CMs132may be included in a same column manager. An example layout of a CM132with associated AR106is described below with reference toFIG.8.

Each CM132may be responsible for managing transactions between device of its corresponding AR106and the interconnection resources46. For example, the CM132A may coordinate with the LSM130A to transmit a command to the microsector92A and the microsector92B. The CM132and LSMs130may be involved with routing commands, such as configuration instructions, to certain microsectors92from other portions of the integrated circuit12or from other microsectors92. In cases where the interconnection resources46involve use of a network-on-chip, the CMs132may manage transactions between the network-on-chip and the corresponding AR106. This arrangement may permit relatively high bandwidth data movement between master and slave bridges implemented via the interconnection resources46since, for example, the CMs132may help coordinate transmission between multiple microsectors and/or multiple ARs106, such that the transmissions may be paralleled, or at least partially coordinated in time and/or in sequence.

A controller, such as the controller76, may transmit packets to each of the LSMs130and/or CMs132that include data and commands to perform a configuration and a test of the configuration. To implement the configuration, one or more LSMs130may generate respective commands interpretable by respective row controllers126, where the respective commands may be used to control configuration of one or more microsectors92. The data and commands transmitted to a LSM130from the controller76may correspond to a portion of a circuit design represented by the configuration to be implemented in the subset of microsectors92managed (e.g., communicatively coupled) to the respective LSM130. Once the configuration is implemented in the programmable logic66(or at least partially implemented), the one or more LSMs130may test the implemented configuration to verify that the configuration operates as expected. The test may be performed using a portion of the data and commands received by the LSM130from the controller76. The LSMs130may test the respective portion of the circuit design corresponding to its respective intersections of column regions128and row regions124at least partially overlapping in time to the programming (e.g., configuration) of additional portions of the programmable logic66, such as while one or more other row regions124, column regions128, or microsectors92, continue to be programmed (e.g., configured). Once each portion of the programmable logic66is programmed, the LSMs130may coordinate in operation and perform a system-wide test of one or more circuit designs implemented in one or more microsectors92. Testing performed may include aggregation operations that verify operations of portions of circuitry, in addition to verifying whole circuit operation. Each LSM130may operate as a management engine for its local set of the microsectors92.

Indeed, each row controller126may receive a command from its corresponding LSM130and may decode the command to generate control signals. The control signals may control operation of the corresponding row region124of microsectors92. For example, the row controller126A, coupled between the microsector92C and the microsector92E, may generate control signals used for controlling operation of the microsector92C and the microsector92E disposed in a same row region124. Furthermore, as opposed to the LSM130controlling multiple column regions128, each LSM130may control two column regions128.

For example, the LSM130may generate commands associated with read and write operations. In some cases, the LSM130may also command the row controller126to decompress (e.g., decode) data associated with the command before transmitting data to a respective microsector92. The row controller126may be considered a configuration endpoint that may be read from and/or written to by the LSM130and/or the controller76via the interconnection resources46to read or write data (e.g., configuration data, test data) to the microsector92. It is noted that although shown as including43row regions124, and43row controllers126, any suitable number of row regions124, column regions128, and the like may be used in the integrated circuit12to implement systems and methods described herein.

Continuing now to discuss an example chip layout and an example of the AR106(i.e., a micro-network-on-chip),FIG.8is a block diagram of a micro-network-on-chip (microNOCs)142that includes a bi-directional data path144and multiple row controllers126. This extensible columnar-oriented network structure fits within fabric memory columns of the programmable logic66, and permits data transaction operations like dynamic and/or static bandwidth allocations, virtual channels, and the like. Each microNOC142is formed from the bi-directional data path144interconnecting a column of row controllers126to a respective CM132and, if used, a respective LSM130. A subset of microNOCs142may share the respective CM132.

Each CM132may couple to a network-on-chip (NOC)146. In some cases, the interconnection resources46may include and/or form the network-on-chip (NOC)146. When used in an FPGA, the fabric of the FGPA die may integrate the NOC146. The NOC146may communicate with the individual row controllers126, and thus the programmable logic66, using commands sent through the microNOCs142. In some cases, the NOC146may include horizontal NOC circuitry and vertical NOC circuitry, such that the NOC146as a whole is not contiguous. Even in these cases, however, the NOC146intersects horizontally with each microNOC142, and thus intersects horizontally with each microsector92corresponding to the programmable logic66. The programmable logic66may be accessed by using row controllers126to interface with corresponding microsectors92. Furthermore, each row controller126may include memory (e.g., random-access memory (RAM), cache memory) that may be accessed before, after, or in conjunction with access to associated programmable logic66. The row controllers126ofFIG.8may include the row controller126A. It is noted that one or more of the microNOCs142may include additional circuitry not depicted or described herein.

A CM132may span multiple microNOC142columns (e.g., one, two, three, ten, any suitable number). In this example, one CM132may control five microNOC142columns. Each CM132may communicate with the row controllers126associated with the subset of microNOC142coupled to the CM132. When transmitting a command, the CM132may receive the command, determine which portion of programmable logic66to communicate with based on the command, and determine which microNOC142to transmit the command based on the portion of programmable logic66. Since the data path144is bi-directional, the CM132may transmit and receive messages simultaneously on a same microNOC142.

To receive and/or transmit commands, the CM132may include a master interface148and a slave interface150. In some cases, commands and/or data may be communicated from external software or a peripheral component using an advanced interface bus (AIB)140to a respective row controller126of a respective microNOC142.

A trace buffer trigger250may provide buffer memory for collecting register state traces collected from microsectors using highly pipelined (HIPI) debug trace capabilities described below. For example, if a user wants to capture a lot of trace data over a short period of time, external memory and transceiver may not have enough bandwidth to send all the data to off-chip locations at once. When on-chip buffer memory has much higher bandwidth than off-chip interfaces, it can accept a short burst of high-bandwidth data which can be later sent through a narrow off-chip communication link to the off-chip destination.

The trace trigger buffer250may also detect specific conditions in register traces to aid user-level debug operations. For example, a user may want to know on what clock cycle a specific multi-bit variable reached a value of zero. The trace trigger buffer250may process traces from multiple microNOCs to collect all bits belonging to this variable, may align all those bits to specific cycles, and may generate a signal when all bits are equal to zero on a specific cycle.

Debug and Real Time Trace of Registers

To elaborate on data handling operations,FIG.9is block diagram of a microsector including logic element input mux (LEIM) HIPI registers154and driver input mux (DIM) HIPI registers158. Routing fabric116may include any suitable number of LEIM HIPI registers154and any suitable number of DIM HIPI registers158. LEIM HIPI registers154may be grouped into a LEIM HIPI register chain152. Data in the LEIM HIPI register chain152may be shifted up from one LEIM HIPI register154to a subsequent LEIM HIPI register154in the LEIM HIPI register chain152. At the end of the LEIM HIPI register chain152, a final LEIM HIPI register154may shift data to a shift register166in a HIPI QDI Shift In path164. Data may be shifted out from a shift register162in a HIPI QDI Shift Out path160to a first LEIM HIPI register154in the LEIM HIPI register chain152. The data from shift register162may then be shifted up to a subsequent LEIM HIPI register154in the LEIM HIPI register chain152.

DIM HIPI registers158may be grouped into a DIM HIPI register chain156. Data in the DIM HIPI register chain156may be shifted down from one DIM HIPI register158to a subsequent DIM HIPI register158in the DIM HIPI register chain156. At the end of the DIM HIPI register chain156, a final DIM HIPI register158may shift data to a shift register166in the HIPI QDI Shift In path164. Data may be shifted out from the shift register162in the HIPI QDI Shift Out path160to a first DIM HIPI register158in the DIM HIPI register chain156. The data from shift register162may then be shifted down to a subsequent DIM HIPI register158.

The row controller126A may include an interface168and the interface168may receive data from the HIPI QDI Shift In path164and may transmit data to the HIPI QDI Shift Out path160. In some embodiments, the interface168may convert data to be transmitted into a suitable number of data frames to be transmitted to the HIPI QDI Shift Out path160. For example, the number of data frames may be based on the number of LEIM HIPI register chains152being written to and/or the number of DIM HIPI register chains156being written to.

To elaborate on the LEIM HIPI register chain152,FIG.10is a block diagram of a respective LEIM HIPI register154. The LEIM HIPI register154A may include any suitable combination of logic gate circuitry and/or serially shifting circuitry. For example, the LEIM HIPI register154A may include one or more flip-flops, switch-reset latches, multiplexing circuitry or the like to enable the LEIM HIPI register154A to shift data up to a subsequent LEIM HIPI register154in the LEIM HIPI register chain152associated with the microsector92A or to a shift register166in the LCB114. A LEIM shift enable signal170may be received at multiplexer172and may enable a shift mode of the LEIM HIPI register154A. In the shift mode, a shift in data signal174A may be received at the LEIM HIPI register154A from a previous LEIM HIPI register154in the LEIM HIPI register chain152or a shift register166. A shift out data signal174B may be shifted out of LEIM HIPI register154A to a subsequent LEIM HIPI register154or to a shift register166. In some embodiments, the LEIM shift enable signal170may enable a shift mode in any suitable number of LEIM HIPI registers154in any suitable number of LEIM HIPI register chains152. As such, data may be shifted up the LEIM HIPI register chain152until reaching a shift register166in the LCB114.

To elaborate on the DIM HIPI register chain156,FIG.11is a block diagram of a respective DIM HIPI register158. The DIM HIPI register158A may include any suitable combination of logic gate circuitry and/or serially shifting circuitry. For example, the DIM HIPI register158A may include one or more flip-flops, switch-reset latches, multiplexing circuitry or the like to enable the DIM HIPI register158A to shift data down to a subsequent DIM HIPI register158in the DIM HIPI register chain156associated with the microsector92A or to a shift register166in the LCB114. A DIM shift enable signal178may be received at multiplexer180and may enable a shift mode of the DIM HIPI register158A. In the shift mode, a shift in data signal182may be received at the DIM HIPI register158A from a previous DIM HIPI register158in the DIM HIPI register chain156or a shift register166. A shift out data signal184may be shifted out of DIM HIPI register158A to a subsequent DIM HIPI register158or to a shift register166. In some embodiments, the DIM shift enable signal178may enable a shift mode in any suitable number of DIM HIPI registers158in any suitable number of DIM HIPI register chains156. As such, data may be shifted down the DIM HIPI register chain156until reaching a shift register166in the LCB114.

To elaborate further on accessing the microsector92,FIG.12is a block diagram of a respective row controller126and of a respective microsector92. For ease of explanation, row controller126A and microsector92A are referenced. However, it should be understood that these descriptions are applicable to each row controller126and/or microsector92.

The row controller126may receive the command from the LSM130via data path144. Indeed, the LSM130may transmit commands as one or more packets (e.g., data packets) using the data path144. It is noted that the command received via the data path144may be of any suitable format or length. An identifier decoder (ID Decode) block186may decode an identifier (ID) of the packet. By reading the ID of the packet and comparing to a stored ID indication, the ID Decode block186may identify whether the packet is relevant to the row controller126A and/or whether the packet is intended to be received by the row controller126A. The ID Decode block186may use one or more look-up tables, register values, and/or stored indications of its identifier. The data path144may be shared by each row controller126of a respective AR106. As such, the data path144may also continue on to a subsequent row controller126of the AR106A.

When the ID Decode block186identifies that a packet is for the row controller126A, a finite state machine (FSM)188may perform logical sequencing to move the packet off of the data path144. Register values received from the packet may be stored in configuration random access memory (CRAM) registers192. It is noted that the CRAM registers192may be alternatively implemented in flip-flop circuitry or other logic circuitry, however CRAM-based registers may provide suitable memory storage capabilities to flip-lop circuitry or other logic circuitry while using a smaller footprint.

Register values may be referenced by other components throughout the row controller126A. For example, from the packet, the FSM188and/or the ID Decode block186may receive signals indicative of register values (R). In response to the register values, the FSM188may generate a signal indicative of a state machine state (S). The state machine state may be maintained by the FSM188, where a state of the FSM188may change in response to the register values (R) received from the CRAM registers192and/or in response to an output from the ID Decode block186. The FSM188may output the state machine state (S) to the CRAM registers192. The switching circuitry may change state to change a data path internal to the row controller126A in response to the state machine state (S) output from the FSM188.

Some of the CRAM registers192may not change in response to the packet being received by the row controller126A. For example, identifier data stored in a controller identifier (ID) register194may be set at a time of initial configuration of the row controller126A. However, if the row controller126A is not preset with the identifier data stored in the ID register194, the row controller126A may set a value of the ID register194(e.g., the stored identifier) to an identifier included in the packet.

The CRAM registers192may include a control (CNTL) register196that stores control bits. The control bits may define how the row controller126A interacts with the data path144, such as how the row controller126A is to receive and/or access a packet from the data path144. For example, the control bits may indicate to the ID Decode block186which subset of packets are relevant to the row controller126A and thus should be taken off of the data path144. The CRAM registers192may also include a configuration (CNFG) register198used to store configuration bits. The configuration bits may transmit to the FSM188to change an operation of the row controller126, such as an operation performed based on a state of the FSM188. A mode register200may store configuration bits, for example, to define an operation for one or more of the row controllers126. In some embodiments, the configuration bits may transmit to the Quasi Delay Insensitive (QDI) FIFO Out block210to change an operation of the row controller126, such as indicating to the QDI FIFO Out block210an output frame size for converted data. For example, the output frame size may be based on the number of HIPI register columns written to. In certain embodiments, the configuration bits may transmit to the QDI FIFO In block212to change an operation of the row controller126, such as indicating to the QDI FIFO In block212an input frame size for converted data. For example, the input frame size may be based on the number of HIPI register columns read from.

In some cases, a random-access memory (RAM)202of the row controller126A may also receive the state machine state (S) generated by the FSM188. The RAM202may be used as storage for the configuration operations. Since the RAM202includes volatile memory, the storage provided via the RAM202may be temporary storage. Packets from the data path144and/or packets to be transmitted to the data path144may be stored temporarily in the RAM202before and/or after transmission via the data path144. Operations used to read from the RAM202may be based on data indicated by a Read Pointer (RPTR) block204. Operations used to write to the RAM202may be based on data indicated by a Write Pointer (WPTR) block206. The pointer indicated by the data of the RPTR block204may be used to advance an address provided to the RAM202as data is read from the RAM202, thereby providing real-time adjustment of pointers used to access data stored by the RAM202. It is noted that in cases when the RAM202is not included in the row controller126A, supporting circuitry may also be omitted. For example, without the RAM202, some switching circuitry (e.g.,190B,190C) may be omitted as well as some or all of the FPGA fabric interface control signals since the data loading may be performed via transmit through the μDR112. In some cases, the FSM188may control the addresses indicated by the RPTR block204and/or the WPTR206when moving data to or from the data path144and/or the FSM188may control the address indicated by the RPTR block204and/or the WPTR206when moving data to or from microsector92A.

The row controller126A may convert the address indicated by the WPTR block206to a one hot-decoded value (e.g., thermometer encoded value, 10000000, 00000001) by using a decoder block186(1 hot decode). The one-hot encoded value may be used to select a CRAM to be written or read. It is noted that with one-hot encoded values, an integer value, such as an address or another integer encoded variable, may be replaced (e.g., translated) into a new binary variable, where a binary value (e.g., logical low bit, “0” or a logical high bit, “1” as is in the case of 111110 encoding) may added for each unique integer value. In this way, an address of ten may be represented by “0000000001” or “1111111110,” while an address of four may be represented by “0001” or “1110,” based on whether the encoding is using a “1” or a “0” to represent the various integer values. Other formats may be used based on the particular system implementation.

The row controller126A may also include a Quasi Delay Insensitive (QDI) FIFO Out block210(QDI FIFO OUT). The QDI FIFO Out block210may convert data received over the data path144into any suitable number of data frames, such that the data frames may be serially shifted to the HIPI QDI Shift Out path160that may include individual shift registers162(e.g., shift register162A, shift register162B, shift register162C, shift register162N) serially coupled.

Each shift register162may include any suitable combination of logic gate circuitry and/or serially shifting circuitry. For example, the shift register162may include one or more flip-flops, switch-reset latches, multiplexing circuitry or the like to enable the row controller126A to shift data into the respective programmable logic66(e.g., disposed in region176) associated with the microsector92A. Indeed, the region176of the programmable logic66corresponding to the microsector92A may include the LABs104, the ALEs110, the LCBs114, and/or the routing fabric116described above with regards to at leastFIG.6.

The row controller126A may also include a QDI FIFO In block212(QDI FIFO IN). The QDI FIFO in block212may convert data frames received from the HIPI QDI Shift In path164into data portions matching a width of the data path144, such that the data frames may be serially shifted from the HIPI QDI Shift In path164that may include individual shift registers166(e.g., shift register166A, shift register166B, shift register166C, shift register166N) serially coupled.

Each shift register166may include any suitable combination of logic gate circuitry and/or serially shifting circuitry. For example, the shift register166may include one or more flip-flops, switch-reset latches, multiplexing circuitry or the like to enable the row controller126A to shift data out of the respective programmable logic66(e.g., disposed in region176) associated with the microsector92A.

In certain embodiments, the FSM188may receive signals indicative of a command to read and/or write the QDI FIFO Out block210and/or the QDI FIFO In block212. The row controller126A may also include a timer block208. The timer block208may be synchronized. The timer block208may include a suitable number of bits to count a maximum variation in latency of data arriving at the trace trigger buffer250. The timer block208may generate and may transmit a timer value to that is sent with each trace data packet in the data path144. The trace trigger buffer250may receive the timer value and may determine a time an associated trace data packet was generated.

Referring now to more details regarding the HIPI QDI Shift In path164,FIG.13is a block diagram of a portion of the microsector92A ofFIG.9. Microsector92A may include any suitable number of LABs104. Each LAB104may include one or more user registers214(e.g., user register214A, user register214B, user register214C, user register214D, user register214E, user register214F). While six user registers214are shown inFIG.13, any suitable number of user registers214may be present in microsector92A. The microsector92A may also include any suitable number of DIM HIPI register chains156(e.g.,156A,156B,156C,156D,156E,156F,156G156H,156J). Each user register214may be communicatively coupled to an associated DIM HIPI register chain156.

The microsector92A may also include any suitable number of shift registers166(e.g.,166A,166B,166C,166D,166E,166F,166G,166H,166J) in the HIPI QDI Shift In path164. For example, the microsector92A may have an equal or greater number of shift registers166as the number of DIM HIPI register chains156. Each DIM HIPI register chain156may be communicatively coupled to an associated shift register166in the HIPI QDI Shift In path164. The HIPI QDI Shift In path164may shift data from the DIM HIPI register chains156to the interface168. The shift registers166of the HIPI QDI Shift In path164may operate at a frequency greater than a frequency at which the user registers214operate. As such, the HIPI QDI Shift In path164may shift a number of bits from the shift registers166based on a ratio of the frequency of the shift registers166and the frequency of the user registers214. For example, if the shift registers166operate at 5 GHz and the user registers214operate at 1 GHz, the HIPI QDI Shift In path164may shift five bits to the interface168during every clock cycle. As such, only five shift registers (166B,166C,166E,166F,166G) may be active and may shift out bits to the interface168.

Column226shows clock cycles 0, 1, 2, 3, 4, 5, 6, and 7. Bit columns216,218,220,222, and224show bits associated with corresponding clock cycles for each of the active shift registers166. On every clock cycle, data shifts from one DIM HIPI register156in DIM HIPI register chains156B,156C,156E,156F,156G to an associated active shift register166in the HIPI QDI Shift In path164. For example, during clock cycle 0, shift register166B receives data BO from DIM HIPI register chain156B, shift registers166C,166E,166F, and166G receive a bit value of zero from DIM HIPI register chains156C,156E,156F, and156G, respectively.

WhileFIG.13is described in relation to DIM HIPI register chains156, shift registers166, and HIPI QDI Shift In path164, LEIM HIPI register chains152may function with HIPI QDI Shift In path164in a similar manner. Additionally, shift registers162and HIPI QDI Shift Out path160may function in a similar manner with LEIM HIPI register chains152and DIM HIPI register chains156with bits being shifted from HIPI QDI Shift Out path160to the register chains152,156.

FIG.14is an illustration of data received at the QDI FIFO In block210ofFIG.12via the interface168. Bit columns216,218,220,222,224show bits shifted out from associated active shift registers166B,166C,166E,166F, and166G, respectively, inFIG.13.FIG.15is an illustration of a MNOC message228generated by converting the bits received at the QDI FIFO In block210. MNOC message228may include a Traffic Identifier (TID)230used to identify a respective microNOC142. The TID230may correspond to a logical address of the respective microNOC142(e.g., to guide a routing network as to where to direct a message). In certain embodiments, the TID230may indicate a respective microNOC responsible for generating the MNOC message228. A time stamp232may indicate when the MNOC message228was created and/or generated. The interface168and/or QDI FIFO In block210may also arrange the bits according to how the interface168and/or QDI FIFO In block210received the data from the active shift registers166B,166C,166E,166F, and166G. For example, the interface168and/or QDI FIFO In block210may arrange the bits according to the clock cycle during which the interface168received the bits. As such, bit group234,236,238,240,242,244,246,248may correspond to clock cycles 0, 1, 2, 3, 4, 5, 6, 7, respectively.

Referring now toFIG.16, the trace buffer trigger250may receive any suitable number of MNOC messages228. The trace buffer trigger250may store MNOC messages228in temporary message buffer266. The trace buffer trigger250may send MNOC messages228out as trace268. The trace buffer trigger250may include a message ID compare block252, time align block254, lookup256, bit align block258, lookup260, trigger262, conditions264, and message buffer266. The purpose of all these blocks is to reconstruct cycle-by-cycle view of multiple bits received in MNOC message228. Time align block254may align a local time stamp embedded in a received MNOC message228to a global timing view. Bit align block258may unpack bits from the received MNOC message228and may align bits from different registers to the same timeline and may further re-order bits from a least significant bit (LSB) to a most significant bit (MSB) order. Finally, trigger block262may align values to the trigger condition (e.g., conditions264) and may generate appropriate trigger signals.

Microregion Dynamic Voltage Frequency Scaling (DVFS) and Security Techniques

To incorporate dynamic voltage and frequency scaling techniques in programmable integrated circuits, the critical paths of each region of the integrated circuit may be identified based on an analysis of a user's design of each region of the integrated circuit. After identifying the critical paths of an integrated circuit based on the user design, the embodiments described herein may include creating synthetic tunable replica circuits (STRCs) that mimic the identified critical paths. The created STRCs may be programmed into unused FPGA logic and circuit components of the integrated circuit based on the user's design. In some embodiments, the insertion of the STRCs into the integrated circuit may involve simultaneously inserting the STRCs with the user's circuit design if there is not enough unused logic to create them.

After an STRC is stored in a region of the integrated circuit, a control circuit within the respective region of the integrated circuit may tune or calibrate the STRC to represent the critical paths of the respective region. In some embodiments, a calibration design may be created to calibrate the STRCs with respect to the real critical paths of the actual circuit paths of the user's circuit design. The calibration design may include heater circuits, such that the STRCs may be swept across various voltages, frequencies, and temperature values. After tuning the STRC, the control circuit may monitor the performance of the STRC over a frequency sweep and record the behavior of the critical path over frequency. As a result, the control circuit may generate a table that quantifies the behavior of the critical path over frequency without knowledge of the voltage and temperature characteristics of the region of the integrated circuit.

With the foregoing in mind, while the region of the integrated circuit is performing a respective operation via its critical path, the control circuit may determine whether the clocking frequency or voltage provided to the region may be reduced without compromising the region's performance based on the recorded behavior. Based on the recorded behavior, the control circuit may adjust the clocking frequency of the region to reduce the overall power consumed by the integrated circuit. In addition to reducing the power consumption of the integrated circuit, the control circuit may employ STRCs to detect anomalies that may occur within the integrated circuit, detect attacks from perpetrators outside of the integrated circuit, improve end-of-life parameters for the integrated circuit, and the like.

FIG.17illustrates a block diagram of a system270for sensitizing a logic cone288. To sensitive the logic cone288, an activating source274causes an input logic to transition and travels along critical path278to cause destination flop282to transition. Input bit sequence272may be shifted into the DIM HIPI register158. The input bit sequence272may include bit values that are shifted at a slow clock frequency and bit values that are shifted at a maximum clock frequency (FMAX). The DIM HIPI register158may transmit the input bit sequence272to the activating source274. The activating bit sequence276may include bit values that are shifted at the slow clock frequency and bit values that are shifted at the maximum clock frequency. In certain embodiments, the activating bit sequence may include bit values which are unknown (e.g., X). In response, the activating source274may initialize a bit sequence284of the destination flop282to a bit value opposite of the desired transition. The activating source274may initialize the activating bit sequence276to a bit value opposite of the desired source transition. The activating source274may also create the desired transition at an output of the activating source274. The activating source274may also create the transition to be measured at the destination flop282at the desired maximum frequency. The LEIM HIPI register154may shift out data (e.g., bit sequence286). The bit sequence286may include unknown bit values and a transition bit value being tested for (e.g., T). In certain embodiments, the activating signal may be a vector instead of a bit sequence.

Referring now to more details regarding critical paths,FIG.18is a block diagram of a clock control circuit290for a clock network. The clock control circuit290may select either a fast clock (FCLK) signal296(e.g., the FMAX clock signal) or a slow clock (SCLK) signal298as the clock source for sensitizing and activating the critical path. The clock control circuit290may include a phase-locked loop block294that receives input clock frequency signal292and that generates the fast clock signal296and the slow clock signal298, based on the input clock frequency signal292. The clock gate block300may select the fast clock signal296or the slow clock signal298as output clock signal302to the clock network.

To elaborate further on DFVS techniques on the microsector92,FIG.19is a block diagram of a respective row controller126and of a respective microsector92. The microsector92A may also include a delay chain326that may provide a bit value (e.g., 0-16 bits) that represents the current delay of the identified critical path. The delay chain326may be used as a reference to determine whether the identified critical path delay is increasing or decreasing over time. The QDI FIFO In block212may generate a delay meter signal338based on data received from the HIPI QDI Shift In path164(e.g., the delay meter). For example, the QDI FIFO In block212may receive meter data indicative of the behavior (e.g., delay time) of the critical path of the STRC via the HIPI QDI Shift In path164. The FSM188may receive the delay meter signal338from the QDI FIFO In block212

The CRAM registers192may include a mode register320that stores configuration bits. For example, the configuration bits may define an operation for one or more of the row controllers126. In some embodiments, the configuration bits may transmit to the local source block322to change an operation of the row controller126, such as indicating a local source block322to be used for a measured signal and the clock the local source is launched on. In certain embodiments, the configuration bits may transmit to the delay adjust block324to change an operation of the row controller126, such as monitoring and centering a delay edge in the delay meter (e.g., HIPI QDI Shift In path164).

To elaborate further on security techniques on the microsector92,FIG.20is a block diagram of a respective row controller126and of a respective microsector92. A less than circuit block330may compare the delay meter signal338from the QDI FIFO In block212to a first threshold delay value (e.g., a lower threshold delay value). For example, the less than circuit block330may determine the delay meter signal338falls below the first threshold delay value. As such, the less than circuit block330may generate a low alarm signal332based on the comparison and may transmit the low alarm signal332to the FSM188. A greater than circuit block334may compare the delay meter signal338to a second threshold delay value (e.g., a greater threshold delay value). For example, the greater than circuit block334may determine the delay meter signal338is greater than the second threshold delay value. As such, the greater than circuit block334may generate a high alarm signal336based on the comparison and may transmit the high alarm signal336to the FSM188.

In some embodiments, the FSM188may perform an operation in response to receiving an alarm signal (e.g., low alarm signal332, high alarm signal336). For example, the FSM188may generate and may transmit the alarm signal to a secure device manager for the integrated circuit12. The alarm signal may include an indication of a microsector92associated with the alarm signal, the first threshold delay value, the second threshold delay value, and/or the delay meter signal338. In certain embodiments, the secure device manager may perform an operation in response to receiving the indication from the FSM. For example, the secure device manager may shut down the integrated circuit12, shut down the corresponding microsector92A based on the indication in the alarm signal, remove power from the corresponding microsector92A, gate the I/O of the corresponding microsector92A based on the indication in the alarm signal, or the like.

The CRAM registers192may include a low comparison register326that stores configuration bits. For example, the configuration bits may transmit to the FSM188to change an operation of the row controller126, such as an operation performed based on a state of the FSM188. The configuration bits may transmit to the less than circuit block330to change an operation of the row controller126, such as generating a lower threshold delay value and comparing the lower threshold delay value to the delay meter signal338from the HIPI QDI Shift In path164.

A high comparison register328in the CRAM registers192may store configuration bits. For example, the configuration bits may transmit to the FSM188to change an operation of the row controller126, such as an operation performed based on a state of the FSM188. The configuration bits may transmit to the greater than circuit block334to change an operation of the row controller126, such as generating the greater threshold delay value and comparing the greater threshold delay value to the delay meter signal338from the HIPI QDI Shift In path164.

Referring briefly to design and compilation operations, a compiler16, host18, and/or design software14may know which register-transfer level (RTL) soft logic is used to implement circuitry applications in the programmable logic66. The compiler16, the host18, and/or the design software14may use this information to configure a master bridge of the NOC146with identifiers for used row controllers126and/or microNOCs142. The compiler16, the host18, and/or the design software14may also use this information to generate a name to use to address the include file. At the time the RTL is written, the design software14, for example, may use placeholder blocks with defined data sources and data end points but without defined memories and logic placement. During compilation, an “include file” may be generated that includes memories and logic placement to implement the operations to be performed by the placeholder blocks. An include file may include one or more named associations between logical memory inferenced (or instantiated in RTL) and addresses. The compiler16, the host18, and/or the design software14may generate the include file in an RTL analyze phase of compilation operations. For example, the include file may be generated when defining a memory map to guide future memory transactions with the programmable logic66. The master bridge of the NOC146supporting the command interface may provide translation to the physical CM132. The include file may provide the logical address of the CM132. The compiler16, the host18, and/or the design software14may generate a NOC logical-to-physical address translation table after design fitting operations, and may store the translation table in the master bridge as part of device configurations.

During a design phase, a visualization tool associated with the design software14may show physical placement of the row controllers126in a design. The visualization tool may also show an impact on timing that the row controller placement has on the design, as well as an expected bandwidth or latency. The timing, bandwidth, and/or latency metrics may be shown for the design as a whole, for portions of the design in comparison to each other, or the like. With the visualization tool, a user may perform manual placement of row controllers126to determine an impact of the placement. The impact of the placement may not be reflected in the presented metrics until after a re-compilation of the design.

While the embodiments set forth in the present disclosure may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. For example, any suitable combination of the embodiments and/or techniques described herein may be implemented. Moreover, any suitable combination of number formats (e.g., single-precision floating-point, half-precision floating-point, bfloat16, extended precision and/or the like) may be used. Further, each DSP circuitry and/or DSP architecture may include any suitable number of elements (e.g., adders, multipliers 64, routing, and/or the like). Accordingly, it should be understood that the disclosure is not intended to be limited to the particular forms disclosed. The disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure as defined by the following appended claims.

Technical effects of the present disclosure include system and methods that provide a microsector architecture. The microsector architecture described herein may benefit operations of programmable logic devices, such as field programmable gate arrays and/or other configurable devices, by permitting programming of programmable fabric to occur over smaller regions of fabric. The systems and methods described herein may enable a 1-bit wide data register (e.g., a micro-data register (μDR)) to transmit data to or from the smaller regions of programmable fabric. Benefits afforded from the microsector architecture may be further improved from using a micro-network-on-chip (microNOC) in conjunctions with the microsector. Each microsector corresponds to a row controller, and row controllers communicate with a control system via a shared data path. The control system may improve data transactions within the microsector architecture by coordinating data read and write operations across one or more microNOCs and across one or more row controllers. Coordinating operations spanning the microsector architecture enables large-scale data movements between the memory within the microsector architecture components and external memory. Furthermore, an addressing process is described herein that enables each row controller and/or each microNOC to be respectively addressed. These system and methods that enable individualized addressing of microNOCs may improve data handling operations since data may be stored out of logical order within the microsector architecture.

EXAMPLE EMBODIMENTS

EXAMPLE EMBODIMENT 1. An integrated circuit, comprising:

a first network-on-chip disposed around at least a partial perimeter of a plurality of microsectors arranged in a row and column grid; and

a first microsector of the plurality of microsectors, wherein the first microsector is coupled to a first row controller, the first microsector comprising:a plurality of logic access blocks, each logic access block coupled to a data register;a plurality of routing blocks, each routing block comprising a first HIPI register chain and a second HIPI register chain, wherein at least one data register is coupled to at least one of the first HIPI register chain and the second HIPI register chain; anda control block comprising a first shift register chain configurable to shift data out of the first microsector to the first row controller and a second shift register chain configurable to shift data in to the first microsector from the first row controller.

EXAMPLE EMBODIMENT 2. The integrated circuit of example embodiment 1, wherein the first shift register chain comprises a plurality of shift registers.

EXAMPLE EMBODIMENT 3. The integrated circuit of example embodiment 2, wherein a portion of the plurality of shift registers are inactive shift registers.

EXAMPLE EMBODIMENT 4. The integrated circuit of example embodiment 1, the first row controller comprising a first control circuit configurable to receive data from the first shift register chain.

EXAMPLE EMBODIMENT 5. The integrated circuit of example embodiment 4, the first row controller comprising a second control circuit configurable to shift data to the second shift register chain.

EXAMPLE EMBODIMENT 6. The integrated circuit of example embodiment 4, wherein the first control circuit is configurable to convert data received from the first shift register chain from a number of data frames to a data format associated with the first row controller.

EXAMPLE EMBODIMENT 7. The integrated circuit of example embodiment 5, wherein the second control circuit is configurable to convert data into a number of data frames.

EXAMPLE EMBODIMENT 8. The integrated circuit of example embodiment 1, wherein a number of bits shifted out from the first shift register chain is based on a frequency of the data register and a frequency of a shift register of the first shift register chain.

EXAMPLE EMBODIMENT 9. A method, comprising:

monitoring, via a first control circuit, a propagation delay associated with a delay chain disposed in programmable logic circuitry of an integrated circuit, wherein the first control circuit is disposed outside programmable logic circuitry of the integrated circuit;

comparing, via the first control circuit, the propagation delay to a first threshold delay;

determining, based on the comparison, that at least one alarm signal criteria is met; and

in response to determining at least one alarm signal criteria is met, generating an alarm signal based on the comparison.

EXAMPLE EMBODIMENT 10. The method of example embodiment 9, comprising:

receiving, at a second control circuit disposed outside the programmable logic circuitry, the alarm signal; and

generating, based on the alarm signal, a message comprising an identifier of a microsector of the programmable logic circuitry.

EXAMPLE EMBODIMENT 11. The method of example embodiment 10, comprising performing an operation based on the message.

EXAMPLE EMBODIMENT 12. The method of example embodiment 11, wherein the operation comprises turning off power to the microsector.

EXAMPLE EMBODIMENT 13. The method of example embodiment 9, wherein:

the first threshold delay is a minimum threshold delay; and

comparing the propagation delay to the first threshold delay comprises determining that the propagation delay falls below the minimum threshold delay.

EXAMPLE EMBODIMENT 14. The method of example embodiment 9, comprising:

comparing, via the first control circuit, the propagation delay to a second threshold delay;

determining, based on the comparison to the second threshold delay, that at least one alarm signal criteria is met; and

in response to determining at least one alarm signal criteria is met, generating a second alarm signal based on the comparison to the second threshold delay.

EXAMPLE EMBODIMENT 15. The method of example embodiment 14, wherein:

the second threshold delay is a maximum threshold delay; and

comparing the propagation delay to the second threshold delay comprises determining that the propagation delay exceeds the maximum threshold delay.

EXAMPLE EMBODIMENT 16. A system, comprising:

programmable logic circuitry comprising a plurality of configuration memory, the programmable logic circuitry comprising:

a first microsector, wherein the first microsector is coupled to a first row controller, the first microsector comprising:

a plurality of logic access blocks, each logic access block coupled to a data register;

a plurality of routing blocks, each routing block comprising a first HIPI register chain and a second HIPI register chain, wherein at least one data register is coupled to at least one of the first HIPI register chain and the second HIPI register chain; and

a control block comprising a first shift register chain configurable to shift data out of the first microsector to the first row controller; and

a first control circuitry, wherein the first control circuitry is configured to receive data from the first shift register chain.

EXAMPLE EMBODIMENT 17. The system of example embodiment 16, the control block comprising second shift register chain configurable to shift data in to the first microsector from the first row controller.

EXAMPLE EMBODIMENT 18. The system of example embodiment 17, comprising a second control circuitry, wherein the second control circuitry is configured to shift data to the second shift register chain.

EXAMPLE EMBODIMENT 19. The system of example embodiment 18, wherein the first control circuitry and the second control circuitry are disposed in the first row controller.

EXAMPLE EMBODIMENT 20. The system of example embodiment 18, wherein the second control circuitry is configured to convert data into a number of data frames.

The techniques presented and claimed herein are referenced and applied to material objects and concrete examples of a practical nature that demonstrably improve the present technical field and, as such, are not abstract, intangible or purely theoretical. Further, if any claims appended to the end of this specification contain one or more elements designated as “means for [perform]ing [a function]. . . ” or “step for [perform]ing [a function]. . . ” it is intended that such elements are to be interpreted under 35 U.S.C. 112(f). However, for any claims containing elements designated in any other manner, it is intended that such elements are not to be interpreted under 35 U.S.C. 112(f).