Patent ID: 12218219

Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, like reference numerals generally indicate identical, functionally similar, and/or structurally similar elements.

DETAILED DESCRIPTION

It is noted that references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” “exemplary,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of one skilled in the art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.

It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by those skilled in relevant art(s) in light of the teachings herein.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In some embodiments, the terms “about” and “substantially” can indicate a value of a given quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values are merely examples and are not intended to be limiting. The terms “about” and “substantially” can refer to a percentage of the values as interpreted by those skilled in relevant art(s) in light of the teachings herein.

Fins associated with fin field effect transistors (finFETs) or gate-all-around (GAA) FETs can be patterned by any suitable method. For example, the fins can be patterned using one or more photolithography processes, including a double-patterning process or a multi-patterning process. Double-patterning and multi-patterning processes can combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins.

Technology advances in the semiconductor industry drive the pursuit of integrated circuits (ICs) having higher device density, higher performance, and lower cost. In the course of the IC evolution, nano-sheet transistors can replace planar FETs and finFETs to achieve ICs with higher device densities. Nano-sheet transistors can use a GAA gate structure to surround each nano-sheet channel layer to mitigate short channel effects. To further boost nano-sheet transistor performance, the nano-sheet transistor can incorporate a buried dielectric layer to physically separate the nano-sheet channel layers from the substrate to further suppress substrate leakage current. The process of forming the buried dielectric layer can include (i) performing an inner spacer formation process to form inner spacers to cover a top sacrificial layer (e.g., a silicon germanium layer with germanium atomic ratio about 30%), and (ii) replacing, via a lateral etching process and a deposition process, a bottom sacrificial layer (e.g., a silicon germanium layer with germanium atomic ratio about 15%) with the buried dielectric layer. The inner spacers can protect the top sacrificial layer when replacing the bottom sacrificial layer with the buried dielectric layer during the lateral etching process. However, the inner spacer formation can include an etching process with an insufficient etching selectivity to etch the top sacrificial layer over the bottom sacrificial layer. Accordingly, the inner spacer formation process may unintentionally form inner spacers to cover the bottom sacrificial layer and block the formation of the buried dielectric layer, thus degrading the IC's reliability and performance.

To address the aforementioned challenges, the present disclosure is directed to a fabrication method of an inner spacer for a gate-all-around field effect transistor (GAA FET). The process of forming the inner spacer can include epitaxially growing a bottom sacrificial layer over a substrate and epitaxially growing a top sacrificial layer over the bottom sacrificial layer. The top sacrificial layer and the bottom sacrificial layer can be silicon germanium layers. Further, the top sacrificial layer can have a greater germanium atomic concentration than the bottom sacrificial layer. The process of forming the inner spacer can further include forming a recess structure to expose side surfaces of the top sacrificial layer and the bottom sacrificial layer. The process of forming the inner spacer can further include performing a radical etching process to selectively etch the top sacrificial layer over the bottom sacrificial layer with an etching selectivity greater than about 5, such as from about 5 to about 100. The radical etching process can be performed with a fluorine-containing etchant, such as fluorine-containing radicals. Further, the radical etching process can be a hydrogen-free radical etching process to ensure a sufficient activation energy difference (e.g., greater than about 0.39 eV) of the etching reaction between on the top sacrificial layer and on the bottom sacrificial layer. With a sufficient etching selectivity provided by the radical etching process, the process of forming the inner spacer can selectively form inner spacer on the top sacrificial layer. The bottom sacrificial layer can be exposed after the process of forming the inner spacer, thus enabling the subsequent replacement process (e.g., etching process and deposition process) to replace the bottom sacrificial layer with the buried dielectric layer. A benefit of the present disclosure, among others, is to increase the yield of patterning the buried dielectric layer for the GAA FET, thus improving the IC's reliability and performance.

A semiconductor device100having multiple FETs101formed over a substrate102is described with reference toFIGS.1and2, according to some embodiments.FIG.1illustrates an isometric view of semiconductor device100, according to some embodiments.FIG.2illustrates a cross-sectional (e.g., along the x-z plane) view of semiconductor device100along line B-B ofFIG.1, according to some embodiments. The discussion of elements inFIGS.1and2with the same annotations applies to each other, unless mentioned otherwise. Semiconductor device100can be included in a microprocessor, memory cell, or other integrated circuit (IC). Also, each FET101shown inFIGS.1and2can be a GAA FET, according to some embodiments.

Referring toFIGS.1and2, substrate102can be a semiconductor material, such as silicon. In some embodiments, substrate102can include a crystalline silicon substrate (e.g., wafer). In some embodiments, substrate102can include (i) an elementary semiconductor, such as silicon (Si) or germanium (Ge); (ii) a compound semiconductor including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb); (iii) an alloy semiconductor including silicon germanium carbide (SiGeC), silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), gallium indium phosphide (InGaP), gallium indium arsenide (InGaAs), gallium indium arsenic phosphide (InGaAsP), aluminum indium arsenide (InAlAs), and/or aluminum gallium arsenide (AlGaAs); or (iv) a combination thereof. Further, substrate102can be doped depending on design requirements (e.g., p-type substrate or n-type substrate). In some embodiments, substrate102can be doped with p-type dopants (e.g., boron (B), indium (In), aluminum (Al), or gallium (Ga)) or n-type dopants (e.g., phosphorus (P) or arsenic (As)).

FET101can include a fin structure108extending along an x-direction, a gate structure110traversing through fin structure108along a y-direction, and source/drain (S/D) regions124formed over portions of fin structure108. AlthoughFIG.1shows fin structure108accommodating two FETs101, any number of FETs101can be disposed along fin structure108. In some embodiments, FET101can include multiple fin structures108extending along a first horizontal direction (e.g., in the x-direction) and gate structure110traversing through the multiple fin structures108along a second horizontal direction (e.g., in the y-direction).

Fin structure108can include a buffer region120formed over substrate102. Buffer region120can be made of materials similar to (e.g., lattice mismatch within 5%) substrate102. In some embodiments, buffer region120can be made of identical materials as substrate102. In some embodiments, buffer region120can be made of Si or SiGe. Buffer region120can be un-doped, doped with p-type dopants, doped with n-type dopants, or doped with intrinsic dopants.

Fin structure108can further include a buried dielectric layer140formed over substrate102. In some embodiments, buried dielectric layer140can be formed over and in contact with substrate102(this embodiment is not shown inFIG.2). In some embodiments, as shown inFIG.2, buried dielectric layer140can be formed over buffer region120. With buried dielectric layer140being formed over substrate102and/or over buffer region120, FET101's substrate leakage current that flows through buffer region120and/or substrate102can be reduced. Buried dielectric layer140can be made of any suitable electrically insulating material. In some embodiments, buried dielectric layer140can be made of silicon oxide, silicon nitride, or a low-k dielectric material with a dielectric constant less than about 3.9. Buried dielectric layer140can have a suitable thickness t140(shown inFIG.2), such as about 10 nm. In some embodiments, buried dielectric layer140's central portion (e.g., under gate structure110) and edge portion (e.g., proximate to S/D region124) can have substantially identical thicknesses t140to each other. Based on the disclosure herein, other materials and thicknesses for buried dielectric layer140are within the spirit and scope of this disclosure.

Fin structure108can further include one or more channel regions122formed over buried dielectric layer140. Channel region120can be made of materials similar to (e.g., lattice mismatch within 5%) substrate102. In some embodiments, channel region122can be made of Si or SiGe. In some embodiments, buffer region120and channel regions122can be both doped with p-type dopants or doped with n-type dopants. In some embodiments, channel region122can be wrapped by gate structure110to function as FET101's channel. For example, a top surface, side surfaces, and a bottom surface of channel region122can be surrounded and in physical contact with gate structure110. In some embodiments, channel region122(e.g., the bottommost channel region122shown inFIGS.1and2) can be wrapped by gate structure110and buried dielectric layer140Channel region122can have a thickness t122A(e.g., from about 8 nm to about 13 nm) proximate to the adjacent S/D regions124and a thickness t122B(e.g., from about 10 nm to about 15 nm) away from the adjacent S/D regions124. In some embodiments, thickness t122Bcan be greater than or substantially equal to thickness t122Adue to the etching selectivity between channel region122and first sacrificial layers422of the radical etching process performed at operation315(discussed below). In some embodiments, as shown inFIG.2, a horizontal (e.g., in the x-direction) dimension of channel region122's bottom surface can be greater than that of channel region122's top surface. In some embodiments, as shown inFIG.2, a horizontal (e.g., in the x-direction) dimension of the bottommost channel region122's bottom surface can be greater than that of another (e.g., another channel region122that is formed over the bottommost channel region122) channel regions122's bottom surface. In some embodiments, as shown inFIG.2, a horizontal (e.g., in the x-direction) dimension of buried dielectric layer140's bottom surface can be greater than that of channel region122's bottom surface. Based on the disclosure herein, other materials and thicknesses for channel region122are within the spirit and scope of this di

Gate structure110can be a multilayered structure (not shown inFIGS.1and2) that wraps around channel region122and buried dielectric layer140to modulate FET101. Gate structure110can have a suitable length L110, such as from about 15 nm to about 50 nm, representing FET101's channel length. Gate structure110can include a gate dielectric layer (not shown inFIGS.1and2) and a gate electrode (not shown inFIGS.1and2) disposed on the gate dielectric layer. The gate dielectric layer can include any suitable dielectric material with any suitable thickness that can provide channel modulation for FET101. In some embodiments, the gate dielectric layer can be made of silicon oxide or a high-k dielectric material (e.g., hafnium oxide or aluminum oxide). In some embodiments, the gate dielectric layer can have a thickness ranging from about 1 nm to about 5 nm. Based on the disclosure herein, other materials and thicknesses for the gate dielectric layer are within the spirit and scope of this disclosure. The gate electrode can function as a gate terminal for FET101. The gate electrode can include any suitable conductive material that provides a suitable work function to modulate FET101. In some embodiments, the gate electrode can be made of titanium nitride, tantalum nitride, tungsten nitride, titanium, aluminum, copper, tungsten, tantalum, copper, or nickel. Based on the disclosure herein, other materials for the gate electrode are within the spirit and scope of this disclosure.

S/D regions124can be formed over opposite sides (e.g., along x-direction) of channel region122, opposite sides of gate structure110, and opposite sides of buried dielectric layer140. S/D regions124can be physically contact with channel region122and buried dielectric layer140. S/D regions124can be made of an epitaxially-grown semiconductor material similar to (e.g., lattice mismatch within 5%) channel region122. In some embodiments, S/D regions124can be made of Si, Ge, SiGe, InGaAs, or GaAs. S/D regions124can be doped with p-type dopants, n-type dopants, or intrinsic dopants. In some embodiments, S/D region124can have a different doping type from channel region122.

Semiconductor device100can further include a gate spacer104formed between gate structure110and S/D region124. In some embodiments, gate spacer104can be further formed over fin structure108's side surface. Gate spacer104can be made of any suitable dielectric material. In some embodiments, gate spacer104can be made of silicon oxide, silicon nitride, or a low-k material with a dielectric constant less than about 3.9. In some embodiments, gate spacer104can have a suitable thickness t104, such as from about 5 nm to about 15 nm. Based on the disclosure herein, other materials and thicknesses for gate spacer104are within the spirit and scope of this disclosure.

Semiconductor device100can further include shallow trench isolation (STI) regions138to provide electrical isolation between fin structures108. Also, STI regions138can provide electrical isolation between FET101and neighboring active and passive elements (not shown inFIGS.1and2) integrated with or deposited on substrate102. STI regions138can include one or more layers of dielectric material, such as a nitride layer, an oxide layer disposed on the nitride layer, and an insulating layer disposed on the nitride layer. In some embodiments, the insulating layer can include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric material, and/or other suitable insulating materials. Based on the disclosure herein, other dielectric materials for STI region138are within the spirit and scope of this disclosure.

Semiconductor device100can further include an interlayer dielectric (ILD) layer130to provide electrical isolation to structural elements it surrounds or covers, such as gate structure110and S/D regions124. In some embodiments, gate spacer104can be formed between gate structure110and ILD layer130. ILD layer130can include any suitable dielectric material to provide electrical insulation, such as silicon oxide, silicon dioxide, silicon oxycarbide, silicon oxynitride, silicon oxy-carbon nitride, and silicon carbonitride. ILD layer130can have any suitable thickness, such as from about 50 nm to about 200 nm, to provide electrical insulation. Based on the disclosure herein, other insulating materials and thicknesses for ILD layer130are within the spirit and scope of this disclosure.

Semiconductor device100can further include an inner spacer160formed protruding into fin structure108. Inner spacer160can separate gate structure110from S/D region124. For example, inner spacer160can be formed at gate structure110's opposite sides along FET101's channel direction (e.g., along the x-direction) to separate gate structure110from S/D region124. In some embodiments, inner spacer160can be formed between two vertically (e.g., in the z-direction) adjacent channel regions122. Inner spacer160can further have a front surface160F proximate to gate structure110. In some embodiments, the term “vertical” or “vertically” can mean nominally perpendicular to the surface of a substrate. In some embodiments, front surface160F can be substantially coplanar with gate structure110. In some embodiments, front surface160F can be a substantially planar surface or a curved surface. Inner spacer160can further have a back surface160B proximate to S/D region124. In some embodiments, back surface160B can be substantially coplanar with S/D region124. In some embodiments, back surface160B can be a substantially planar surface or a curved surface. In some embodiments, back surface160B can be an indented surface with respect to inner spacer160's vertical (e.g., in the z-direction) adjacent channel region122's side surface122S. Inner spacer160can be made of any suitable insulating material, such as a low-k dielectric material, to electrically separate gate structure110from S/D region124. In some embodiments, inner spacer160can be made of silicon nitride, silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon oxynitridecarbide (SiONC). Based on the disclosure herein, other materials for inner spacer160are within the spirit and scope of this disclosure.

FIG.3is a flow diagram of a method300for fabricating semiconductor device100, according to some embodiments. For illustrative purposes, the operations illustrated inFIG.3will be described with reference to the example fabrication process for fabricating semiconductor device100as illustrated inFIGS.1and2.FIGS.4and5illustrates isometric views of semiconductor device100at various stages of its fabrication, according to some embodiments.FIGS.6-17illustrate cross-sectional views along line B-B of structure ofFIG.5at various stages of its fabrication, according to some embodiments. Operations can be performed in a different order or not performed depending on specific applications. Method300may not produce a complete semiconductor device100. Accordingly, it is understood that additional processes can be provided before, during, and/or after method300, and that some other processes may be briefly described herein. Further, the discussion of elements inFIGS.1,2, and4-17with the same annotations applies to each other, unless mentioned otherwise.

Referring toFIG.3, in operation305, a fin structure with first and second sacrificial layers is formed over a substrate. For example, as shown inFIG.4, fin structure108with a first sacrificial layer422and a second sacrificial layer440can be formed over substrate102. The process of forming fin structures108can include (i) providing substrate102; (ii) epitaxially growing second sacrificial layer440with thickness t140over substrate102, (iii) epitaxially growing alternative stacks of channel regions122with thickness t122Band sacrificial layers422with a suitable thickness t422, such as from about 5 nm to about 10 nm, over second sacrificial layer440; and (iv) etching channel regions122, first sacrificial layers422, second sacrificial layer440, and substrate102through a patterned mask layer (not shown inFIG.4) using an etching process. In some embodiments, thickness t422can be substantially equal to thickness t140.

First sacrificial layer422and second sacrificial layer440can be made of materials different from channel region122and similar to (e.g., lattice mismatch within 5%) substrate102. In some embodiments, first sacrificial layer422and second sacrificial layer440can be made of SiGe, and channel region122can be made of Si. In some embodiments, first sacrificial layer422and second sacrificial layer444can have greater atomic percentage of Ge than channel region122's atomic percentage of Ge. Further, first sacrificial layer422and channel region122can be made of SiGe with different atomic percentages of Ge from each other. Accordingly, first sacrificial layer422can have different etching selectivity from second sacrificial layer440during the process of forming inner spacer (discuss at operation320). In some embodiments, first sacrificial layer422(e.g., Si0.7Ge0.3) can have a greater atomic percentage of Ge than second sacrificial layer440(e.g., Si0.8sGe0.15), such that first sacrificial layer422can be selectively etched over the second sacrificial layer440during the process of forming inner spacer (discuss at operation320). In some embodiments, first sacrificial layer422can have a greater atomic percentage of Ge than second sacrificial layer440by from about 5% to about 25%, from about 10% to about 25%, from about 10% to about 20%, or from about 10% to about 15%. If the difference of Ge atomic percentages between first sacrificial layer422and second sacrificial layer440is below the above-noted lower limits, the etching selectivity between first sacrificial layer422and second sacrificial layer440may be insufficient to form buried dielectric layer140(discussed at operation320and325). If the difference of Ge atomic percentages between first sacrificial layer422and second sacrificial layer440is beyond the above-noted upper limits, the lattice mismatch between first sacrificial layer440and second sacrificial layer440may be cause crystalline defects in channel regions122, thus causing device failure for semiconductor device100.

Channel region122, first sacrificial layer422, and second sacrificial layer440can be epitaxially grown using any suitable epitaxial growth process, such as a chemical vapor deposition (CVD) process, a low pressure CVD (LPCVD) process, a rapid thermal CVD (RTCVD) process, a metal-organic CVD (MOCVD) process, an atomic layer CVD (ALCVD) process, an ultrahigh vacuum CVD (UHVCVD) process, a reduced pressure CVD (RPCVD) process, a molecular beam epitaxy (MBE) process, a cyclic deposition-etch (CDE) process, and a selective epitaxial growth (SEG) process. Based on the disclosure herein, other materials, thicknesses, and epitaxial growth processes for channel region122, first sacrificial layer422, and second sacrificial layer440are within the spirit and scope of this disclosure.

The etching process for removing channel region122, first sacrificial layer422, second sacrificial layer440, and substrate102can include a dry etching process or a wet etching process to define fin structure108and buffer region120with a suitable width W108, such as from about 5 nm to about 50 nm. In some embodiments, the dry etching process can include using any suitable etchant, such as an oxygen-containing gas, a fluorine-containing gas, a chlorine-containing gas, and a bromine-containing gas, and the wet etching process can include etching in any suitable wet etchant, such as diluted hydrofluoric acid, potassium hydroxide solution, ammonia, and nitric acid. Based on the disclosure herein, other widths and etching processes for fin structure108are within the spirit and scope of this disclosure.

Referring toFIG.3, in operation310, a recess structure is formed in the fin structure to expose side surfaces of the first and second sacrificial layers. For example, a recess structure636(shown inFIG.6) can be formed in fin structure108to expose channel region122's side surface122S, first sacrificial layer422's side surface422S, and second sacrificial layer440's side surface440S with reference toFIGS.5and6. The process of forming recess structure636can include (i) forming STI region138(shown inFIG.5) over the etched substrate102using a deposition process and an etch back process; (ii) forming sacrificial gate structures510(shown inFIG.5) with length L110over fin structures108; and (iii) removing fin structures108through sacrificial gate structures510to form recess structure636.

The deposition process for forming STI region138can include any suitable growth process, such as a physical vapor deposition (PVD) process, a CVD process, a high-density-plasma (HDP) CVD process, a flowable CVD (FCVD) process, and an atomic layer deposition (ALD) process. The etch back process for forming STI region138can include a dry etching process, a wet etching process, or a polishing process, such as chemical vapor deposition (CMP) process. Based on the disclosure herein, other processes for forming STI region138are within the spirit and scope of this disclosure.

The process of forming sacrificial gate structure510can include (i) blanket depositing a dielectric layer506with a suitable thickness, such as from about 1 nm to about 5 nm, over fin structures108using a suitable deposition process, such as a CVD process, a PVD process, and an ALD process; (ii) blanket depositing a polysilicon layer (not shown inFIG.5) and a hard mask layer (not shown inFIG.4) over dielectric layer506using a suitable deposition process, such as a CVD process, a PVD process, and an ALD process; (iii) removing dielectric layer506, the polysilicon layer and the hard mask layer through a patterned mask layer (not shown inFIG.5) using an etching process; and (iv) forming gate spacers104with a suitable thickness t104, such as from about 5 nm to about 15 nm, over the polysilicon layer's side surfaces and/or over fin structure108's side surfaces using a suitable deposition process and an etching process. Based on the disclosure herein, other processes for forming gate structures510are within the spirit and scope of this disclosure.

Referring toFIG.6, after forming sacrificial gate structure410, recess structure636can be formed by removing channel regions122, first sacrificial layers422, second sacrificial layer440, and substrate102through sacrificial gate structures510and gate spacers104using an etching process. The etching process can include a dry etching process or a wet etching process. In some embodiments, the etching process can be a time-etching process. In some embodiments, the dry etching process can include using any suitable etchant, such as an oxygen-containing gas, a fluorine-containing gas, a chlorine-containing gas, and a bromine-containing gas, and the wet etching process can include etching in any suitable wet etchant, such as diluted hydrofluoric acid, potassium hydroxide solution, ammonia, and nitric acid. As shown inFIG.6, the resulting recess structure636can expose fin structure108's side surface, such as exposing first sacrificial layers422's side surfaces422S, exposing second sacrificial layer440's side surface440S, and exposing channel region122's side surface122S. Further, the resulting recess structure636can expose gate spacers104's side surfaces. In some embodiments, the resulting recess structure636can expose buffer region120's side surface. In some embodiments, side surfaces422S,440S and122S formed by operation310can be substantially coplanar with one another.

Referring toFIG.3, in operation315, the first sacrificial layer exposed by the recess structure is selectively etched over the second sacrificial layer exposed by the recess structure. For example, as shown inFIG.7, first sacrificial layers422exposed by recess structure636can be selectively etched over second sacrificial layer440exposed by recess structure636by performing a radical etching process on the structure ofFIG.6. The radical etching process can etch first sacrificial layer422with a lateral (e.g., along the x-direction) etching depth S422. In some embodiments, lateral etching depth S422can be substantially equal to spacer104's thickness t104, such that gate structure110formed over channel regions122and gate structure110formed between channel regions122can have substantially identical length L110to each other after method300. The radical etching process may minimally etch second sacrificial layer422with a lateral etching depth S440. In some embodiments, lateral etching depth S440can be less than about 1.5 nm. If etching depth S440is beyond the above-noted upper limit, inner spacer160(formed at operation320) may be formed over second sacrificial layer422's side surface422S, thus inhibiting forming buried dielectric layer at operation325.

In some embodiments, a ratio of lateral etching depth S422to lateral etching depth S440can be from about 10 to about 100. If the ratio of lateral etching depth S422to lateral etching depth S440is below the above-noted lower limit, inner spacer160(formed at operation320) may be formed over second sacrificial layer422's side surface422S, thus inhibiting forming buried dielectric layer at operation325. If the ratio of lateral etching depth S422to lateral etching depth S440is beyond the above-noted upper limits, the radical etching process may result in an increased etching depth S422, thus causing gate structure110formed between channel regions122having an insufficient gate length to control FET101's channel regions122. In some embodiments, the ratio of lateral etching depth S422to lateral etching depth S440can be substantially equal to the ratio of the etching rate of etching first sacrificial layer422by the radical etching process to the etching rate of etching second sacrificial layer440by the radical etching process. In some embodiments, the ratio of the etching rate of etching first sacrificial layer422by the radical etching process to the etching rate of etching second sacrificial layer440can be referred to the etching selectivity of first sacrificial layer422over second sacrificial layer440in the radical etching process.

In some embodiments, the radical etching process performed at operation315can selectively etch first sacrificial layer422over channel region122, thus causing thickness t122Bgreater than or substantially equal to thickness t122Aafter operation315. In some embodiments, the difference between thickness t122Band thickness t122Acan be substantially equal to lateral etching depth S440.

The process of performing the radical etching process to selectively etch first sacrificial layer422over second sacrificial layer440can include (i) providing a processing gas that contains a halogen element, such as containing fluorine, (ii) providing a noble gas, such as argon (Ar), to mix with the processing gas; and (iii) performing, via a remote plasma source, an excitation process, a disassociation process, and/or an ionization process on the mixed processing gas and the noble gas to generate radicals that contain the halogen element. In some embodiments, the generated radicals can be ion-free radicals (e.g., charge neutral radicals). The generated radicals can react with side surfaces (e.g., side surface422S) ofFIG.6's fin structure108exposed by recess structures636to selectively etch first sacrificial layer422over second sacrificial layer440and selectively etch first sacrificial layer422over channel regions122. In some embodiments, the processing gas can include nitrogen trifluoride (NF3), fluorine gas (F2), carbon tetrafluoride (CF4), or sulfur hexafluoride (SF6), where the respective halogen element contained in the processing gas can be a fluorine element (F). Accordingly, respective generated radicals can be fluorine-based radicals, such as NF3*, NF2*, NF*, F*, and F2*. As previously discussed, first sacrificial layer422and channel region122can be made of SiGe with different atomic percentages of Ge from each other. For example, first sacrificial layer422(e.g., Si0.7Ge0.3) can have a greater atomic percentage of Ge than second sacrificial layer440(e.g., Si0.8sGe0.15). The generated radicals (e.g., the above-noted fluorine-containing radicals) can react with a germanium-rich (e.g., germanium's atomic concentration greater than about 20%) surface (e.g., reacting with first sacrificial layer422's side surface422S) to form a volatile byproduct (e.g., germanium fluoride) at the activation energy (e.g., about 0 eV) lower than the activation energy (e.g., about 3.9 eV) of reacting with a germanium-poor (e.g., germanium's atomic concentration less than about 20%) surface (e.g., reacting with second sacrificial layer440's side surface440S) to form the volatile byproduct (e.g., germanium fluoride). The volatile byproduct (e.g., germanium fluoride) can then be evaporated from sacrificial layer422, thus reducing first sacrificial layer422's volume. The above-noted activation energy difference (e.g., about 3.9 eV) can ensure a greater etching rate of etching the germanium-rich surface (e.g., etching first sacrificial layer422) than etching the germanium-poor surface (e.g., etching first sacrificial layer422and/or etching channel regions122).

In some embodiments, the radical etching process can be an etching process that only adopts a single species of halogen to selectively etch first sacrificial layer422over second sacrificial layer440. For example, the radical etching process can include providing one or more processing gases, each of the one or more processing gases (e.g., NF3and F2) only including F element. If the one or more processing gases contain another halogen species, such as chlorine (Cl), the radical etching process may additionally include the other halogen-based radicals (e.g., Cl-based radicals) that may reduce the above-noted activation energy differences, thus degrading the etching selectivity between first sacrificial layer422and second sacrificial layer440in the radical etching process.

In some embodiments, the radical etching process can be a hydrogen-free etching process to selectively etch first sacrificial layer422over second sacrificial layer440. Namely, the radical etching does not apply a hydrogen-containing processing gas, such as Trifluoromethane (CHF3) which chemical formula includes hydrogen, to etch first sacrificial layer422. If the processing gas of the radical etching process contains hydrogen, the radical etching process may additionally include the hydrogen-based radicals (e.g., H or H2radicals) that may reduce the above-noted activation energy differences, thus degrading the etching selectivity between first sacrificial layer422and second sacrificial layer440in the radical etching process.

In some embodiments, a ratio of the processing gas's flow rate (e.g., NF3's flow rate) and the noble gas's flow rate (e.g., Ar's flow rate) during the radical etching process can be from about 0.05 to about 1. If the ratio of the processing gas's flow rate (e.g., NF3's flow rate) and the noble gas's flow rate (e.g., Ar's flow rate) during the radical etching process is above these upper limit, the radical etching process may have insufficient noble gas to dissociate the processing gas's molecules to form the halogen-containing radicals (e.g., F-based radicals), thus degrading the overall etching rate of the radical etching process. If the ratio of the processing gas's flow rate (e.g., NF3's flow rate) and the noble gas's flow rate (e.g., Ar's flow rate) during the radical etching process is below these lower limits, the etching selectivity of the radical etching process may degrade due to insufficient halogen-containing radicals.

In some embodiments, the radical etching process can be performed at an operating temperature (e.g., the temperature ofFIG.6's semiconductor device100) from about −90° C. to about 30° C. or from about −90° C. to about 15° C. If the operating temperature of performing the radical etching process is below the above-noted lower limits, the radical etching process's etching rate of etching first sacrificial layer422may be degraded. If the operating temperature of performing the radical etching process is beyond the above-noted upper limits, the radicals in the radical etching process may acquire sufficient thermal energy from the operating temperature to overcome the above-noted activation energy difference (e.g., about 0.39 eV) to greatly react with second sacrificial layer440, thus degrading the etching selectivity between the first sacrificial layer422and second sacrificial layer440in the radical etching process.

Referring toFIG.3, in operation320, an inner spacer is formed over the etched first sacrificial layers. For example, inner spacer160(shown inFIG.9) can be formed over first sacrificial layer422's side surfaces422S with second sacrificial layer440's side surface440S being exposed. As shown inFIG.8, the process of forming inner spacers160can include blanket depositing a dielectric layer760over first sacrificial layer422's side surfaces422S, over second sacrificial layer440's side surface440S, and over channel region122's side surface122S in recess structure636using a deposition process, such as a CVD process, a PVD process, and an ALD process. Dielectric layer760can have a suitable thickness, such as from 1 nm to about 5 nm, to conform to dielectricFIG.7's fin structure108's top and side surfaces. In some embodiments, the deposited dielectric layer760can have two opposite side surfaces horizontally (e.g., in the x-direction) separated from one another in recess structure636.

As shown inFIG.9, the process of forming inner spacer160can further include performing a dry etching process to etch dielectric layer760to define inner spacer160over first sacrificial layer422's side surfaces422S with second sacrificial layer440's side surface440S and channel region122's side surface122S being exposed to recess structures636. In some embodiments, the dry etching process for etching dielectric layer760can be a plasma-free dry etching process (e.g., providing the dry etchant gases to chemically react with dielectric layer760without applying a radio-frequency power to generate ions). In some embodiments, the dry etching process can be a radical etching process. Further, since the radical etching process performed at operation315can cause a negligible lateral etching depth S440(e.g., less than about 3 nm as previously discussed), the dry etching process for forming inner spacer160can completely remove dielectric layer760from second sacrificial layer440's side surface440S with first sacrificial layer422's side surfaces422S being capped by inner spacer160. Therefore, side surface440S can be exposed after forming inner spacer160at operation320. In some embodiments, inner spacer160's lateral (e.g., along x-direction) thickness can be substantially equal to the lateral etching depth S422defined by the radical etching process at operation315. In some embodiments, the dry etching process for etching dielectric layer760can selectively etch dielectric layer760over channel region122with an etching selectivity from about 5 to about 50, from about 5 to about 30, or from about 5 to about 20. If the above-noted etching selectivity is below the above-noted lower limits, channel region122's side surface122S may be damaged by the dry/wet etching process, thus causing FET101's leakage current. If the above-noted etching selectivity is beyond the above-noted upper limits, the resulting inner spacer160may have an insufficient thickness to avoid leakage current between FET101's gate and source/drain terminals.

Referring toFIG.3, in operation325, the second sacrificial layer is replaced with a buried dielectric layer. For example, second dielectric layer440ofFIG.9can be replaced with buried dielectric layer140ofFIG.12with references toFIGS.10-12. As shown inFIG.10, the process of replacing second sacrificial layer440with buried dielectric layer140can include forming a cavity structure1040between the bottommost channel region122and buffer region120by performing an etching process to selectively remove second sacrificial layer440over channel regions122. Cavity structure1040can connect recess structures636at opposite (e.g., in the x-direction) sides of channel regions122with channel regions122and first sacrificial layers422being anchored by sacrificial gate structures510in the y-direction (not shown inFIG.10). As previously discussed, second sacrificial layer440(e.g., a SiGe layer, such as Si0.85Ge0.15) can have a greater germanium concentration than channel region122(e.g. a Si layer). The etching process for forming cavity structure1040can include a dry etching process or a wet etching that selectively etches SiGe over Si. The dry etching process or the wet etching process for forming cavity structure1040does not remove first sacrificial layers422because first sacrificial layer422are protected by inner spacer160. In some embodiments, the dry etching process for forming cavity structure1040can include applying a mixture of gases of HF/F2, or a mixture of NF3and hydrogen radical (H*). In some embodiments, the wet etching process for forming cavity structure1040can include applying a mixture of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) (SPM), or a mixture of ammonia hydroxide with H2O2and water (APM).

As shown inFIG.11, the process of replacing second sacrificial layer440with buried dielectric layer140can further include blanket depositing a dielectric layer1140to fill cavity structure1040, over inner spacers160, and over channel region122's side surface122S of the structure ofFIG.10using a deposition process, such as a CVD process, a PVD process, and an ALD process. In some embodiments, the deposited dielectric layer1140can have two opposite side surfaces horizontally (e.g., in the x-direction) separated from one another in recess structure636.

As shown inFIG.12, the process of replacing second sacrificial layer440with buried dielectric layer140can further include performing a dry etching process to etch portions dielectric layer1140in recess structure636to expose inner spacers160and channel region122's side surface122S, with another portion of dielectric layer1140that occupies cavity structure1040being defined as buried dielectric layer140. In some embodiments, the dry etching process for etching dielectric layer1140can be a plasma-free dry etching process (e.g., providing the dry etchant gases to chemically react with dielectric layer1140without applying a radio-frequency power to generate ions). In some embodiments, the dry etching process can be a radical etching process. In some embodiments, the dry etching process for etching dielectric layer1140can selectively etch dielectric layer1140over channel region122with an etching selectivity from about 5 to about 50, from about 5 to about 30, or from about 5 to about 20. If the above-noted etching selectivity is below the above-noted lower limits, channel region122's side surface122S may be damaged by the dry/wet etching process, thus causing FET101's leakage current. If the above-noted etching selectivity is beyond the above-noted upper limits, the resulting dielectric buried layer140may have an insufficient horizontal (e.g., in the x-direction) dimension to avoid leakage current between FET101's source and drain terminals.

Referring toFIG.3, in operation330, a source/drain (S/D) region and a metal gate structure is formed. For example, as shown inFIGS.1and2, S/D region124can be formed over inner spacers160and channel regions122, and gate structure110can be formed over fin structure108with references toFIGS.13-17. As shown inFIG.13, the process of forming S/D region124can include epitaxially growing S/D region124in the structure ofFIG.12using an epitaxial growth process, such as a CVD process, a LPCVD process, a RTCVD process, a MOCVD process, an ALCVD process, a UHVCVD process, a RPCVD process, an MBE process, a CDE process, and an SEG process. The epitaxial growth process can be performed using suitable precursors, such as silane (SiH4), disilane (Si2H6), dichlorosilane (DCS), and germane (GeH4). The epitaxial growth process can further include doping S/D region124using suitable dopant precursors, such as diborane (B2H6), boron trifluoride (BF3), phosphine (PH3), and arsine (AsH3). Accordingly, the resulting S/D region124can be grown over and in contact with channel regions122under sacrificial gate structure510and gate spacers104. The resulting S/D region124can be further grown over and in contact with inner spacers160that are vertically (e.g., in the z-direction) sandwiched by two vertical (e.g., in the z-direction) channel regions122. The resulting S/D region124can be further grown over and in contact with buried dielectric layer140that are vertically (e.g., in the z-direction) sandwiched by the bottommost channel region122and buffer region120. Based on the disclosure herein, other epitaxial growth processes for forming S/D region124are within the spirit and scope of this disclosure.

Referring toFIGS.14-17, the process of forming gate structure110can include (i) forming ILD layer130(shown inFIG.14) coplanarized with sacrificial gate structures510ofFIG.13using a suitable deposition process, such as a PVD process and a CVD process, and a suitable etch back process, such as a chemical mechanical polishing (CMP) process; (ii) removing sacrificial gate structure510to form recess structures1536(shown inFIG.15) to expose dielectric layer506using an etching process; and (iii) removing dielectric layer506to expose sacrificial layers422using an etching process. In some embodiments, the etching process for forming recess structure1536can include a dry etching process that uses chlorine, fluorine or bromine as gas etchants. In some embodiments, the etching process for forming recess structure1536can include a wet etching process that uses an ammonium hydroxide (NH4OH), sodium hydroxide (NaOH), or potassium hydroxide (KOH) as wet etchants. In some embodiments, the etching process for removing dielectric layer506can include a dry etching process that uses chlorine, fluorine or bromine as gas etchants. In some embodiments, the etching process for removing dielectric layer506can include a wet etching process that uses a hydrogen fluoride (HF) as wet etchants.

The process of forming gate structure110can further include (i) removing sacrificial layers422ofFIG.15to form recess structures1601(shown inFIG.16) using a plasma etching process or a radical etching process; (ii) filling gate structure110(shown inFIG.17), such as a gate dielectric layer (not shown inFIG.17) and a gate electrode (not shown inFIG.17) in the recess structures1536and1601ofFIG.16using a suitable deposition process, such as an ALD process and a CVD process; and (iii) coplanarizing the filled gate structure110ofFIG.17with ILD layer130using a suitable etch back process, such as a CMP process, to define gate structure110ofFIG.2. Based on the disclosure herein, other processes for forming gate structure110are within the spirit and scope of this disclosure.

The present disclosure provides an exemplary transistor inner spacer and a method for forming the same. The method of forming the inner spacer can include forming a fin structure that includes a top sacrificial layer and a bottom sacrificial layer. The top sacrificial layer can have a greater germanium concentration than the bottom sacrificial layer. The method of forming the inner spacer can further include performing a radical etching process to selectively etch the top sacrificial layer over the bottom sacrificial layer at the fin structure. The radical etching process can be a hydrogen-free radical etching process. Further, the radical etching process can apply a fluorine-containing radical, such as a F radical, to react with the top sacrificial layer with an activation energy less than reacting with the bottom sacrificial layer. Accordingly, the radical etching process can selective etch the top sacrificial layer over the bottom sacrificial layer with an etching selectivity greater than about 5, such as from about 5 to about 100. The above-noted enhanced etching selectivity allows the radical etching process to selectively recess the top sacrificial layer's side surface without damaging the bottom side surface's side surface. Hence, the method of forming the inner spacer can selectively pattern the inner spacer over the top sacrificial layer with the bottom sacrificial layer being exposed. After the process of forming the inner spacer, the exposed bottom sacrificial layer can react with etchants of subsequent etching processes to be replaced with a buried dielectric layer. A benefit of the present disclosure, among others, is to provide a hydrogen-free radical etching method to selectively form the inner spacer on the top sacrificial layer to enhance the yield and reliability of patterning the buried dielectric layer, thus improving the semiconductor device's reliability and performance.

In some embodiments, a method can include forming a fin structure over a substrate. The fin structure can include first and second sacrificial layers. The method can further include forming a recess structure in a first portion of the fin structure, selectively etching the first sacrificial layer of a second portion of the fin structure over the second sacrificial layer of the second portion of the fin structure, and forming an inner spacer layer over the etched first sacrificial layer with the second sacrificial layer of the second portion of the fin structure being exposed.

In some embodiments, a method can include forming first and second sacrificial layers over a substrate, forming a recess structure to expose the first and second sacrificial layers, selectively etching the exposed first sacrificial layer over the exposed second sacrificial layer, and forming an inner spacer layer to cap the etched first sacrificial layer over the exposed second sacrificial layer.

In some embodiments, a semiconductor structure can include a substrate and a fin structure formed over the substrate. The fin structure can include a channel region and a buried dielectric layer formed under the channel region. The semiconductor structure can further include a gate structure formed over the channel region, and first and second source/drain (S/D) regions formed in the fin structure and separated from the gate structure. The buried dielectric layer can be in contact with the first and second S/D regions.

The foregoing disclosure outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.