Patent ID: 12218671

DETAILED DESCRIPTION

The detailed description set forth below in connection with the appended drawings, where like numerals reference like elements, is intended as a description of various embodiments of the disclosed subject matter and is not intended to represent the only embodiments. Each embodiment described in this disclosure is provided merely as an example or illustration and should not be construed as preferred or advantageous over other embodiments. The illustrative examples provided herein are not intended to be exhaustive or to limit the claimed subject matter to the precise forms disclosed.

In some embodiments described below, the term “module,” “unit” or “stage,” etc., refers to or includes, inter alia, a combination of hardware (e.g. a processor such as an integrated circuit or other circuitry) and software (e.g. machine- or processor-executable instructions, commands, or code such as firmware, programming, or object code). Furthermore, a combination of hardware and software may include hardware only (i.e. a hardware element with no software elements), software hosted at hardware (e.g. software that is stored at a memory and executed or interpreted at a processor), or hardware with the software hosted thereon. In some embodiments, the hardware may, inter alia, comprise a CPU, a GPU, an FPGA, an ASIC, or other types of electronic circuitry.

The FIGURE shows an example of a phase coherent synthesizer10that has good phase noise and spurious performance The phase coherent synthesizer10comprises a digital direct synthesizer (DDS) module12that has a control interface14via which control signals from a separately formed processing module16are received. Of course, the digital direct synthesizer (DDS) module12and the processing module16may include circuitry for carrying out their respective functions.

The DDS module12also comprises an input18via which a signal is received, e.g. a reference signal, which is processed internally by the DDS module12in order generate analog output signals. Moreover, digital instructions may be received that are processed by the DDS module12in order to generate the output signals. For this purpose, the DDS module12comprises at least one internal digital-to-analog converter in an integrated manner, for example two digital-to-analog converters.

The DDS module12has a first output20as well as a second output22that are independent of each other, but phase stable with respect to each other. Hence, the output signals provided at the respective outputs20,22, namely the first output signal and the second output signal, are phase coherent with respect to each other.

In the shown embodiment, the second output22is associated with a step synthesis, e.g. a step/coarse synthesis provided by the phase coherent synthesizer10. In some embodiments, a second output signal provided via the second output22is associated with a frequency range from, for example, 1.5 to 3 GHz.

In contrast, the first output20is associated with a fine resolution synthesis, also called interpolation synthesis, e.g. a fine synthesis provided by the phase coherent synthesizer10. A first output signal provided via the first output20is associated with a frequency range from, for example, 50 to 300 MHz. Accordingly, the second output signal has a higher frequency compared to the first output signal.

Put differently, the second output signal is used for setting the synthesized frequency of the phase coherent synthesizer10in a coarse manner, whereas the first output signal is used for setting accurate steps between, for example, 50 and 300 MHz. Accordingly, the second output signal is used for a coarse setting, whereas the first output signal is used for fine setting.

Generally, the second output signal only has discrete frequencies, thereby ensuring spurious free signals or rather low phase noise.

In addition, the phase coherent synthesizer10comprises a frequency multiplier24that is associated with the second output22such that the second output signal is multiplied with regard to its frequency, thereby generating a multiplied output signal that is processed by an optional band-pass filter26subsequently.

The multiplied output signal, for example the band-pass filtered one, is forwarded to a mixing stage28that is also associated with an output30of an oscillator32of the phase coherent synthesizer10. In the shown embodiment, the oscillator32is established by an Yttrium-Iron Garnet (YIG) oscillator.

The oscillator32is inter alia controlled by tuning signals or rather control signals, which are derived from the output signals provided at the outputs20,22, thereby generating a magnetic field, e.g. a direct current (DC) magnetic field. The magnetic field is used for setting the oscillator32with regard to its resonance properties such that the frequency of the oscillator output signal is set. In some embodiments, the output signals are used to obtain an intended synthesized frequency of the oscillator output signal.

The oscillator32outputs the oscillator output signal with a respective frequency via an amplifier33towards a main output34. The oscillator output signal provided at the main output34may be used in different technical areas depending on the application of the phase coherent synthesizer10itself.

For instance, the phase coherent synthesizer10is associated with a signal generator such that the oscillator output signal provided at the main output34corresponds to the generated output signal of the signal generator. Alternatively, the phase coherent synthesizer10is associated with a signal analyzer, wherein the oscillator output signal is used as an internal local oscillator signal.

In an output line35provided between the oscillator32, for example its output30, and the main output34. a coupler36is provided. The coupler36is used for providing the oscillator output signal, which is forwarded to the mixing stage28. Previously, the oscillator output signal obtained via the coupler36is amplified by an isolated amplifier37. Accordingly, the mixing stage28has two input ports38,40via which the multiplied output signal and the oscillator output signal from the oscillator32are received respectively.

The mixing stage28down-converts the oscillator output signal by the multiplied output signal to a (low) intermediate frequency signal (IF signal). Thus, the mixing stage28generates the IF signal that is used for further processing. The IF signal is filtered by a low-pass filter41associated with an output of the mixing stage28.

Generally, the intermediate frequency signal provided by the mixing stage28and the first output signal provided by the first output20are synchronized with each other as will be explained in more detail hereinafter.

The phase coherent synthesizer10further comprises a phase detector module42, for example a digital phase detector. The phase detector module42may include circuitry for carrying out its respective function(s).

The phase detector module42is associated with the first output20and the mixing stage28such that the respective signals received, namely the first output signal from the first output20as well as the intermediate frequency signal from the mixing stage28, are compared with each other with respect to their phase. Accordingly, a phase difference may be detected by the phase detector module42.

The phase detector module42outputs, depending on the phase difference detected, a voltage signal, namely a direct voltage signal. The direct voltage signal outputted by the phase detector module42is forwarded to a loop filter44that processes the respective voltage signal that is used for controlling a main coil46of the oscillator32. Previously, the respective voltage signal processed by the loop filter44is amplifier by an amplifier47. In the shown embodiment, the phase detector module42is a digital phase detector.

In some embodiments, the phase coherent synthesizer10comprises a second mixing stage48that is associated with the first output20and the mixing stage28, namely the first mixing stage28. The second mixing stage48is established as, for example, an analog phase detector that provides an output signal indicative of the phase difference between the signals received, namely the IF signal and a signal derived from the first output signal.

The signal derived from the first output signal is obtained via a hybrid coupler50that is located between the first output20and the second mixing stage48.

Hence, the second mixing stage48receives a phase shifted signal that is derived from the first output signal. The phase shifted signal is phase-shifted by 90° with respect to the first output signal.

Depending on the phase difference detected by the analog phase detector, namely the second mixing stage48, between the IF signal provided by the mixing stage28and the phase shifted signal derived from the first output signal, the second mixing stage48outputs a voltage signal that is used for controlling the oscillator32. In the shown embodiment, a FM coil52of the YIG oscillator is controlled by the voltage signal of the second mixing stage48, namely the analog phase detector. Previously, the voltage signal of the second mixing stage48is amplified by an amplifier54.

Accordingly, the phase coherent synthesizer10comprises a phase-locked loop56that comprises the analog phase detector, namely the second mixing stage48, as well as the digital phase detector, namely the phase detector module42.

The respective phase shift between the analog phase detector and the digital phase detector is compensated by the phase shift introduced due to the hybrid coupler50.

Alternatively, the oscillator42may be established as a voltage controlled oscillator that receives the respective voltage signals from the different phase detectors42,48for controlling the oscillator output signal.

Furthermore, the phase-locked loop26, which is established in a frequency divided free manner due to the frequency multiplier24, ensures phase coherence of the signals used for controlling the oscillator32, for example the main coil46and the FM coil52.

In some embodiments, the digital direct synthesizer (DDS) module12is set such that the first output signal and the second output signal together control the oscillator32to generate the oscillator output signal with an intended synthesized frequency. In some embodiments, the digital direct synthesizer (DDS) module12is set such that the second output signal has low spurs, whereas the first output signal is used for fine adjustment of the intended synthesized frequency.

Generally, it is ensured, e.g. by the phase-locked loop56and the associated components, that the first output signal and the intermediate frequency signal are synchronized with each other. Therefore, the phase coherent synthesizer10has a good phase noise and spurious performance while ensuring high tuning speed simultaneously.

Certain embodiments disclosed herein, for example the respective module(s), stage(s), etc., utilize circuitry (e.g., one or more circuits) in order to implement standards, protocols, methodologies or technologies disclosed herein, operably couple two or more components, generate information, process information, analyze information, generate signals, encode/decode signals, convert signals, transmit and/or receive signals, control other devices, etc. Circuitry of any type can be used. It will be appreciated that the term “information” can be use synonymously with the term “signals” in this paragraph. It will be further appreciated that the terms “circuitry,” “circuit,” “one or more circuits,” etc., can be used synonymously herein.

In an embodiment, circuitry includes, among other things, one or more computing devices such as a processor (e.g., a microprocessor), a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a system on a chip (SoC), or the like, or any combinations thereof, and can include discrete digital or analog circuit elements or electronics, or combinations thereof. In an embodiment, circuitry includes hardware circuit implementations (e.g., implementations in analog circuitry, implementations in digital circuitry, and the like, and combinations thereof).

In an embodiment, circuitry includes combinations of circuits and computer program products having software or firmware instructions stored on one or more computer readable memories that work together to cause a device to perform one or more protocols, methodologies or technologies described herein. In an embodiment, circuitry includes circuits, such as, for example, microprocessors or portions of microprocessor, that require software, firmware, and the like for operation. In an embodiment, circuitry includes one or more processors or portions thereof and accompanying software, firmware, hardware, and the like.

In some examples, the functionality described herein can be implemented by special purpose hardware-based computer systems or circuits, etc., or combinations of special purpose hardware and computer instructions.

Of course, in some embodiments, two or more of the components described above, or parts thereof, can be integrated or share hardware and/or software, circuitry, etc. In some embodiments, these components, or parts thereof, may be grouped in a single location or distributed over a wide area. In circumstances were the components are distributed, the components are accessible to each other via communication links.

The present application may reference quantities and numbers. Unless specifically stated, such quantities and numbers are not to be considered restrictive, but exemplary of the possible quantities or numbers associated with the present application. Also in this regard, the present application may use the term “plurality” to reference a quantity or number. In this regard, the term “plurality” is meant to be any number that is more than one, for example, two, three, four, five, etc. The terms “about”, “approximately”, “near” etc., mean plus or minus 5% of the stated value.

The principles, representative embodiments, and modes of operation of the present disclosure have been described in the foregoing description. However, aspects of the present disclosure which are intended to be protected are not to be construed as limited to the particular embodiments disclosed. Further, the embodiments described herein are to be regarded as illustrative rather than restrictive. It will be appreciated that variations and changes may be made by others, and equivalents employed, without departing from the spirit of the present disclosure. Accordingly, it is expressly intended that all such variations, changes, and equivalents fall within the spirit and scope of the present disclosure, as claimed.