Patent ID: 12237648

DETAILED DESCRIPTION

The following detailed description of example implementations refers to the accompanying drawings. The same reference numbers in different drawings may identify the same or similar elements.

A vertical cavity surface emitting laser (VCSEL) and an edge-emitting laser (EEL) emit light in different directions, which may be particularly relevant in applications requiring a small form factor. A VCSEL emits vertically in a direction perpendicular to a wafer surface. As such, a thickness of the VCSEL may be dictated by a quantity of layers of the VCSEL that are grown and an amount by which a substrate for the VCSEL is thinned during fabrication. An EEL emits from an edge of a device, parallel to a wafer surface. Moreover, a VCSEL may interface with external optics placed directly above the surface of the VCSEL. An EEL requires additional optics to change the direction of emitted light by 90 degrees if emission is to be in the same direction as the wafer surface.

Additionally, a VCSEL may emit light out of the top of a chip in a growth direction of the VCSEL (e.g., a top-emitting VCSEL) or down through a substrate through the back of the VCSEL (e.g., a bottom-emitting VCSEL). Each type of VCSEL may utilize a different epitaxial design and a different fabrication process. A top-emitting VCSEL may be easier to fabricate than a bottom-emitting VCSEL, but the top-emitting VCSEL may need to be used in combination with external optical components. A bottom-emitting VCSEL may integrate optical components onto the back of the substrate of the bottom-emitting VCSEL to reduce complexity, but a fabrication process of the bottom-emitting VCSEL may be more complex than a top-emitting VCSEL. A top-emitting VCSEL and/or a bottom-emitting VCSEL may be used in applications relating to dot projectors, indirect time of flight (iToF), direct time of flight (dToF), and/or light detection and ranging (LIDAR), among other examples.

In some cases, multiple VCSEL chips may be integrated into a device, such as a smartphone. For example, a first VCSEL chip, integrated into the device, may be configured to face a user (e.g., emit light in a direction of emission of a display of the device), which may be referred to as “front-facing.” Continuing with the example, a second VCSEL chip, integrated into the device, may be configured to face the world (e.g., emit light opposite to a direction of emission of a display of the device), which may be referred to as “world-facing.” Typically, both VCSEL chips that are used in such configurations may be top-emitting. Moreover, each VCSEL chip may be integrated into a separate module, thereby increasing overall device size and thickness.

Some implementations described herein provide a VCSEL device that emits light in opposite directions (e.g., bi-directionally). In some implementations, VCSELs of different types (e.g., top-emitting and bottom-emitting) may be integrated on a single chip. For example, both a top-emitting VCSEL and a bottom-emitting VCSEL (e.g., independent VCSELs with different active layers and mirrors) may be integrated into the same chip in a configuration that provides emission in opposite directions. In some implementations, a first set of epitaxial layers for one or more bottom-emitting VCSELs may be disposed on a substrate layer (e.g., a wafer), and a second set of epitaxial layers for one or more top-emitting VCSELs may be disposed on the first set of epitaxial layers. For example, multiple full VCSEL epitaxial stacks may be grown on the same substrate layer, and a lower VCSEL stack may be exposed during fabrication to produce multiple VCSELs that emit light in opposite light emission directions.

In this way, a single VCSEL module may include top-emitting and bottom-emitting VCSELs with a reduced form factor. Moreover, the VCSELs (e.g., which may be independently controlled) enable bi-directional emission of light to facilitate front-facing and world-facing operation. Thus, the front-facing and world-facing operation may be achieved without the need for separate VCSEL chips and modules, thereby reducing complexity, thickness, and overall form factor.

FIGS.1A and1Bare diagrams depicting a top-view of an example emitter100and a cross-sectional view150of example emitter100along the line X-X, respectively. As shown inFIG.1A, emitter100may include a set of emitter layers constructed in an emitter architecture. In some implementations, emitter100may correspond to one or more vertical-emitting devices described herein.

As shown inFIG.1A, emitter100may include an implant protection layer102that is circular in shape in this example. In some implementations, implant protection layer102may have another shape, such as an elliptical shape, a polygonal shape, or the like. Implant protection layer102is defined based on a space between sections of implant material (not shown) included in emitter100.

As shown by the medium gray and dark gray areas inFIG.1A, emitter100includes an ohmic metal layer104(e.g., a P-Ohmic metal layer or an N-Ohmic metal layer) that is constructed in a partial ring-shape (e.g., with an inner radius and an outer radius). The medium gray area shows an area of ohmic metal layer104covered by a protective layer (e.g., a dielectric layer or a passivation layer) of emitter100and the dark gray area shows an area of ohmic metal layer104exposed by via106, described below. As shown, ohmic metal layer104overlaps with implant protection layer102. Such a configuration may be used, for example, in the case of a P-up/top-emitting emitter100. In the case of a bottom-emitting emitter100, the configuration may be adjusted as needed.

Not shown inFIG.1A, emitter100includes a protective layer in which via106is formed (e.g., etched). The dark gray area shows an area of ohmic metal layer104that is exposed by via106(e.g., the shape of the dark gray area may be a result of the shape of via106) while the medium grey area shows an area of ohmic metal layer104that is covered by some protective layer. The protective layer may cover all of the emitter other than the vias. As shown, via106is formed in a partial ring-shape (e.g., similar to ohmic metal layer104) and is formed over ohmic metal layer104such that metallization on the protection layer contacts ohmic metal layer104. In some implementations, via106and/or ohmic metal layer104may be formed in another shape, such as a full ring-shape or a split ring-shape.

As further shown, emitter100includes an optical aperture108in a portion of emitter100within the inner radius of the partial ring-shape of ohmic metal layer104. Emitter100emits a laser beam via optical aperture108. As further shown, emitter100also includes a current confinement aperture110(e.g., an oxide aperture formed by an oxidation layer of emitter100(not shown)). Current confinement aperture110is formed below optical aperture108.

As further shown inFIG.1A, emitter100includes a set of trenches112(e.g., oxidation trenches) that are spaced (e.g., equally, unequally) around a circumference of implant protection layer102. How closely trenches112can be positioned relative to the optical aperture108is dependent on the application, and is typically limited by implant protection layer102, ohmic metal layer104, via106, and manufacturing tolerances.

The number and arrangement of layers shown inFIG.1Aare provided as an example. In practice, emitter100may include additional layers, fewer layers, different layers, or differently arranged layers than those shown inFIG.1A. For example, while emitter100includes a set of six trenches112, in practice, other configurations are possible, such as a compact emitter that includes five trenches112, seven trenches112, or another quantity of trenches. In some implementations, trench112may encircle emitter100to form a mesa structure associated with a distance dt. As another example, while emitter100is a circular emitter design, in practice, other designs may be used, such as a rectangular emitter, a hexagonal emitter, an elliptical emitter, or the like. Additionally, or alternatively, a set of layers (e.g., one or more layers) of emitter100may perform one or more functions described as being performed by another set of layers of emitter100, respectively.

Notably, while the design of emitter100is described as including a VCSEL, other implementations are possible. For example, the design of emitter100may apply in the context of another type of optical device, such as a light emitting diode (LED), or another type of vertical emitting (e.g., top emitting or bottom emitting) optical device. Additionally, the design of emitter100may apply to emitters of any wavelength, power level, and/or emission profile. In other words, emitter100is not particular to an emitter with a given performance characteristic.

As shown inFIG.1B, the example cross-sectional view may represent a cross-section of emitter100that passes through, or between, a pair of trenches112(e.g., as shown by the line labeled “X-X” inFIG.1A). As shown, emitter100may include a backside cathode layer128, a substrate layer126, a bottom mirror124, an active region122, an oxidation layer120, a top mirror118, an implant isolation material116, a protective layer114(e.g. a dielectric passivation/mirror layer), and an ohmic metal layer104. As shown, emitter100may have, for example, a total height that is approximately 10 micrometers (lam).

Backside cathode layer128may include a layer that makes electrical contact with substrate layer126. For example, backside cathode layer128may include an annealed metallization layer, such as an AuGeNi layer, a PdGeAu layer, or the like.

Substrate layer126may include a base substrate layer upon which epitaxial layers are grown. For example, substrate layer126may include a semiconductor layer, such as a GaAs layer, an InP layer, and/or another type of semiconductor layer.

Bottom mirror124may include a bottom reflector layer of emitter100. For example, bottom mirror124may include a distributed Bragg reflector (DBR).

Active region122may include a layer that confines electrons and defines an emission wavelength of emitter100. For example, active region122may be a quantum well.

Oxidation layer120may include an oxide layer that provides optical and electrical confinement of emitter100. In some implementations, oxidation layer120may be formed as a result of wet oxidation of an epitaxial layer. For example, oxidation layer120may be an Al2O3layer formed as a result of oxidation of an AlAs or AlGaAs layer. Trenches112may include openings that allow oxygen (e.g., dry oxygen, wet oxygen) to access the epitaxial layer from which oxidation layer120is formed.

Current confinement aperture110may include an optically active aperture defined by oxidation layer120. A size of current confinement aperture110may range, for example, from approximately 4 μm to approximately 20 μm. In some implementations, a size of current confinement aperture110may depend on a distance between trenches112that surround emitter100. For example, trenches112may be etched to expose the epitaxial layer from which oxidation layer120is formed. Here, before protective layer114is formed (e.g., deposited), oxidation of the epitaxial layer may occur for a particular distance (e.g., identified as doinFIG.1B) toward a center of emitter100, thereby forming oxidation layer120and current confinement aperture110. In some implementations, current confinement aperture110may include an oxide aperture. Additionally, or alternatively, current confinement aperture110may include an aperture associated with another type of current confinement technique, such as an etched mesa, a region without ion implantation, lithographically defined intra-cavity mesa and regrowth, or the like.

Top mirror118may include a top reflector layer of emitter100. For example, top mirror118may include a DBR.

Implant isolation material116may include a material that provides electrical isolation. For example, implant isolation material116may include an ion implanted material, such as a hydrogen/proton implanted material or a similar implanted element to reduce conductivity. In some implementations, implant isolation material116may define implant protection layer102.

Protective layer114may include a layer that acts as a protective passivation layer and which may act as an additional DBR. For example, protective layer114may include one or more sub-layers (e.g., a dielectric passivation layer and/or a mirror layer, a SiO2layer, a Si3N4layer, an Al2O3layer, or other layers) deposited (e.g., by chemical vapor deposition, atomic layer deposition, or other techniques) on one or more other layers of emitter100.

As shown, protective layer114may include one or more vias106that provide electrical access to ohmic metal layer104. For example, via106may be formed as an etched portion of protective layer114or a lifted-off section of protective layer114. Optical aperture108may include a portion of protective layer114over current confinement aperture110through which light may be emitted.

Ohmic metal layer104may include a layer that makes electrical contact through which electrical current may flow. For example, ohmic metal layer104may include a Ti and Au layer, a Ti and Pt layer and/or an Au layer, or the like, through which electrical current may flow (e.g., through a bondpad (not shown) that contacts ohmic metal layer104through via106). Ohmic metal layer104may be P-ohmic, N-ohmic, or other forms known in the art. Selection of a particular type of ohmic metal layer104may depend on the architecture of the emitters and is within the knowledge of a person skilled in the art. Ohmic metal layer104may provide ohmic contact between a metal and a semiconductor and/or may provide a non-rectifying electrical junction and/or may provide a low-resistance contact. In some implementations, emitter100may be manufactured using a series of steps. For example, bottom mirror124, active region122, oxidation layer120, and top mirror118may be epitaxially grown on substrate layer126, after which ohmic metal layer104may be deposited on top mirror118. Next, trenches112may be etched to expose oxidation layer120for oxidation. Implant isolation material116may be created via ion implantation, after which protective layer114may be deposited. Via106may be etched in protective layer114(e.g., to expose ohmic metal layer104for contact). Plating, seeding, and etching may be performed, after which substrate layer126may be thinned and/or lapped to a target thickness. Finally, backside cathode layer128may be deposited on a bottom side of substrate layer126.

The number, arrangement, thicknesses, order, symmetry, or the like, of layers shown inFIG.1Bis provided as an example. In practice, emitter100may include additional layers, fewer layers, different layers, differently constructed layers, or differently arranged layers than those shown inFIG.1B. Additionally, or alternatively, a set of layers (e.g., one or more layers) of emitter100may perform one or more functions described as being performed by another set of layers of emitter100and any layer may comprise more than one layer.

FIG.2is a diagram of an example VCSEL device200. As shown inFIG.2, the VCSEL device200may include a substrate layer202, similarly as described above. In addition, the VCSEL device200may include a first set of epitaxial layers204for a bottom-emitting VCSEL206(e.g., one or more bottom-emitting VCSELs206, such as a plurality of bottom-emitting VCSELs206) disposed on the substrate layer202, and the VCSEL device200may include a second set of epitaxial layers208for a top-emitting VCSEL210(e.g., one or more top-emitting VCSELs210, such as a plurality of top-emitting VCSELs210) disposed on the first set of epitaxial layers204. The first set of epitaxial layers204and the second set of epitaxial layers may be independent, and thus the bottom-emitting VCSEL206and the top-emitting VCSEL210may be independent (e.g., electrically and optically). The first set of epitaxial layers204and/or the second set of epitaxial layers208may correspond to the emitter layers described in connection withFIGS.1A-1B.

The VCSEL device200may include a bulk material layer212between the first set of epitaxial layers204and the second set of epitaxial layers208. For example, the bulk material layer212may include a bulk semiconductor layer (e.g., GaAs), which may be lattice matched to the substrate layer202(e.g., the GaAs bulk semiconductor layer may be lattice matched to the GaAs substrate layer202). In some implementations, the VCSEL device200may include an electrical isolation layer214(e.g., a semiconductor layer) between the first set of epitaxial layers204and the second set of epitaxial layers208(e.g., between the bulk material layer212and the first set of epitaxial layers204). The electrical isolation layer214may include a material that provides electrical isolation. In some implementations, the VCSEL device200may include a contact layer216(e.g., a semiconductor layer) between the first set of epitaxial layers204and the second set of epitaxial layers208(e.g., between the bulk material layer212and the first set of epitaxial layers204). The contact layer216may include a highly doped semiconductor material (e.g., an n++ material or a p++ material). The contact layer216may be disposed on the electrical isolation layer214. In some implementations, the VCSEL device200may include a tunnel junction218between the first set of epitaxial layers204and one or more active layers, as described below, of the second set of epitaxial layers208(e.g., within the bulk material layer212, within a bottom mirror of the second set of epitaxial layers208, or the like, outside of the active regions of the bottom-emitting VCSEL206and the top-emitting VCSEL210).

The tunnel junction218may flip a carrier type (e.g., from electrons (n-type) to holes (p-type)) between the first set of epitaxial layers204and the second set of epitaxial layers208. In this way, the first set of epitaxial layers204and the second set of epitaxial layers208may both utilize a p-i-n structure and electrical driving scheme (e.g., to simplify manufacture of the VCSEL device200). However, the first set of epitaxial layers204and the second set of epitaxial layers208are not limited to any particular structure. For example, the first set of epitaxial layers204and the second set of epitaxial layers208may include the same structure or different structures that may be any combination of p-i-n, n-i-p, n-p-i-n, or the like.

The first set of epitaxial layers204may include a first set of mirrors, shown as a first mirror220aand a second mirror220b. The first set of epitaxial layers204may include at least one first active layer222(e.g., a gain region) between the first mirror220aand the second mirror220b. The second set of epitaxial layers208may include a second set of mirrors, shown as a third mirror224aand a fourth mirror224b. The second set of epitaxial layers208may include at least one second active layer226(e.g., a gain region) between the third mirror224aand the fourth mirror224b. An active layer may include an active region where electrons and holes recombine to emit light. For example, an active region may include one or more quantum wells. An active layer may be located at a semiconductor junction of a set of epitaxial layers. A semiconductor junction may be a region at which oppositely-doped semiconductor material meets. For example, a first active layer and a second active layer of a set of epitaxial layers may be at a first p-n junction and a second p-n junction respectively. The bottom-emitting VCSEL206and/or the top-emitting VCSEL210may include two or more semiconductor junctions/active layers (e.g., the bottom-emitting VCSEL206and/or the top-emitting VCSEL210may be a multi-junction VCSEL). Here, a tunnel junction may be between consecutive active layers. In some implementations, the first set of mirrors and the second set of mirrors may be configured to prevent optical crosstalk between the bottom-emitting VCSEL206and the top-emitting VCSEL210.

In some implementations, the first set of mirrors may include the first mirror220a(e.g., a bottom mirror) and the second mirror220b(e.g., a top mirror), and the second set of mirrors may include the third mirror224a(e.g., a bottom mirror) and the fourth mirror224b(e.g., a top mirror). In some implementations, the first set of mirrors may include a first mirror (e.g., the first mirror220a) and a second mirror (e.g., a combination of the second mirror220band the third mirror224a), and the second set of mirrors may include the second mirror and a third mirror (e.g., the fourth mirror224b). For example, the bulk material layer212may be omitted, and the top mirror (or one or more layers thereof) of the first set of epitaxial layers204may be combined with the bottom mirror (or one or more layers thereof) of the second set of epitaxial layers208to form a shared mirror for the first set of epitaxial layers204and the second set of epitaxial layers208. The shared mirror may have increased reflectivity, thereby reducing optical leakage between the bottom-emitting VCSEL206and the top-emitting VCSEL210. Moreover, use of the shared mirror may reduce a time and complexity of manufacturing the VCSEL device200. The first mirror220a, the second mirror220b, the third mirror224a, or the fourth mirror224bmay be DBRs, as described herein.

In some implementations, a first bottom mirror (e.g., the first mirror220a) of the first set of mirrors and a second bottom mirror (e.g., the third mirror224a) of the second set of mirrors may be one of n-type or p-type, and a first top mirror (e.g., the second mirror220b) of the first set of mirrors and a second top mirror (e.g., the fourth mirror224b) of the second set of mirrors may be the other of n-type or p-type. For example, the first bottom mirror and the second bottom mirror may be n-type, and the first top mirror and the second top mirror may be p-type. Here, as described above, the VCSEL device200may include the tunnel junction218between the first set of epitaxial layers204and the second set of epitaxial layers208. Thus, the first set of epitaxial layers204and the second set of epitaxial layers208may both utilize the same p-i-n structure, the same n-i-p structure, or the like. In some implementations, the first set of epitaxial layers204and the second set of epitaxial layers208may utilize different structures, and the tunnel junction218may be omitted.

The at least one first active layer222may include one or more active layers, and the at least one second active layer226may include one or more active layers. In some implementations, a first quantity of active layers of the first active layer(s)222is the same as a second quantity of active layers of the second active layer(s)226, as shown. In some implementations, the first quantity of active layers of the first active layer(s)222is different from the second quantity of active layers of the second active layer(s)226. In this way, an optical power of the bottom-emitting VCSEL206may be the same as or different from an optical power of the top-emitting VCSEL210. In implementations where the first active layer(s)222or the second active layer(s)226include multiple active layers (e.g., two active layers), the first set of epitaxial layers204or the second set of epitaxial layers208, respectively, may include a tunnel junction (not shown) between the multiple active layers.

In an example, the bottom-emitting VCSEL206(or the top-emitting VCSEL210) may have two active layers222(e.g., for higher slope efficiency) and may be suitable for applications that use higher power or longer distance light emission, while the top-emitting VCSEL210(or the bottom-emitting VCSEL) may have a single active layer226(e.g., for lower slope efficiency and/or for lower driver voltage and/or current operation) and may be suitable for applications that use lower power or shorter distance light emission. Thus, the VCSEL device200may be used for multi-power applications, such as indoor/outdoor applications, short range/long range applications, or the like. For example, if a world-facing application uses higher optical power, the world-facing VCSEL may include three active layers or five active layers, while the front-facing VCSEL may include a single active layer (e.g., because front-facing applications typically use lower optical power).

In some implementations, the bottom-emitting VCSEL206(e.g., the lower VCSEL) may have a greater quantity of active layers than the top-emitting VCSEL210(e.g., the upper VCSEL). Alternatively, the top-emitting VCSEL210may have a greater quantity of active layers than the bottom-emitting VCSEL206. The VCSEL with the greatest quantity of active layers (e.g., and therefore the largest heat load) may be positioned nearest to the substrate layer202, and thus nearest to a heat sink (not shown). The quantity of active layers that may be utilized in the bottom-emitting VCSEL206and the top-emitting VCSEL210is not limited to one or two active layers. For example, the bottom-emitting VCSEL206and/or the top-emitting VCSEL210may include three active layers, four active layers, five active layers, and/or six active layers, etc. Moreover, any combination of quantities of active layers may be used for the bottom-emitting VCSEL206and the top-emitting VCSEL210(e.g., because the first set of epitaxial layers204is independent of the second set of epitaxial layers208).

The bottom-emitting VCSEL206and the top-emitting VCSEL210may be configured with an emission wavelength of 850 nanometers (nm), 905 nm, 940 nm, or greater than 1300 nm. In some implementations, an emission wavelength of the bottom-emitting VCSEL206may be the same as an emission wavelength of the top-emitting VCSEL210. In some implementations, the emission wavelength of the bottom-emitting VCSEL206may be different from the emission wavelength of the top-emitting VCSEL210. Here, the VCSEL device200may be used for multi-wavelength applications. For example, the VCSEL device200may provide shorter wavelength emission (e.g., 940 nm) and longer wavelength emission (e.g., greater than 1300 nm). In this way, the VCSEL device200may be used (e.g., simultaneously) for entirely different applications.

The VCSEL device200may include a first set of electrical contacts electrically connected to the first set of epitaxial layers204. The first set of electrical contacts may include a bottom contact228a(e.g., a cathode contact) and a top contact228b(e.g., an anode contact). The bottom contact228amay be disposed on a surface of the substrate layer202opposite the first set of epitaxial layers204. The top contact228bmay be formed in one or more trenches that extend from a surface of the first set of epitaxial layers204to the first mirror220a. The configuration for the first set of electrical contacts shown inFIG.2and described herein is provided as an example and other configurations are possible.

The VCSEL device200may include a second set of electrical contacts electrically connected to the second set of epitaxial layers208. The second set of electrical contacts may include a bottom contact230a(e.g., a cathode contact) and a top contact230b(e.g., an anode contact). The bottom contact230amay be disposed on the first set of epitaxial layers204. For example, the bottom contact230amay be disposed on the contact layer216or the electrical isolation layer214. The top contact230bmay be disposed on a surface of the second set of epitaxial layers208(e.g., on the fourth mirror224b) or may be formed in one or more trenches that extend from a surface of the second set of epitaxial layers208to the third mirror224a. The configuration for the second set of electrical contacts shown inFIG.2and described herein is provided as an example and other configurations are possible.

The first set of electrical contacts and the second set of electrical contacts may be independent or connected together (e.g., depending on a driving scheme for the VCSEL device200that is employed). That is, the bottom-emitting VCSEL206and the top-emitting VCSEL210may be operated simultaneously or independently (e.g., based on a driving scheme that is employed and/or based on a manner in which the VCSELs are fabricated). For example, each VCSEL may be controlled independently by separate sets of contact layers that are deposited during fabrication of the VCSEL device200.

In some implementations, the first set of epitaxial layers204may include an oxide layer232(e.g., between the first active layer(s)222and the second mirror220b) that includes an oxide aperture, and the second set of epitaxial layers208may include an oxide layer234(e.g., between the second active layer(s)226and the fourth mirror224b) that includes an oxide aperture, similarly as described above. In some implementations, an electrical isolation layer236may be disposed along a surface of the first set of epitaxial layers204(e.g., and line the one or more trenches for the top contact230b), and an electrical isolation layer238may be disposed along a surface of the second set of epitaxial layers208(e.g., and line the one or more trenches, if present, for the top contact232b). The electrical isolation layers236,238may include portions of electrical isolation removal (shown by dashed ovals) to facilitate electrical connection of the top contacts228b,230bto the first set of epitaxial layers204and the second set of epitaxial layers208, respectively.

In some implementations, a surface of the substrate layer202, opposite the first set of epitaxial layers204, may include an optical element240(e.g., a lens). That is, the optical element240may be integrated into the substrate layer202. Here, the substrate layer202may have a thickness of greater than or equal to 50 μm (e.g., based on a configuration of the optical elements240). As shown, the optical element240may be for the bottom-emitting VCSEL206(e.g., a light emission from the bottom-emitting VCSEL206may be directed at the optical element240).

The bottom-emitting VCSEL206and the top-emitting VCSEL210may be configured to emit light in opposite light emission directions242a,242b(e.g., the light emission direction242ais rotated 180 degrees relative to the light emission direction242b). For example, as described herein, the bottom-emitting VCSEL206may be configured for bottom emission (e.g., through the substrate layer202) and the top-emitting VCSEL210may be configured for top emission (e.g., away from the substrate layer202). Moreover, the bottom-emitting VCSEL206and the top-emitting VCSEL210may be offset (e.g., vertically offset) in the opposite light emission directions242a,242b. For example, the second set of epitaxial layers208for the top-emitting VCSEL210may be stacked on the first set of epitaxial layers204for the bottom-emitting VCSEL206.

In some implementations, the emission area of the bottom-emitting VCSEL206and the emission area of the top-emitting VCSEL210are aligned in a direction orthogonal to the opposite light emission directions242a,242b, as shown inFIG.2. In some implementations, the emission area of the bottom-emitting VCSEL206and the emission area of the top-emitting VCSEL210are offset in the direction orthogonal to the opposite light emission directions242a,242b, as described below. That is, the emission area of the bottom-emitting VCSEL206and the emission area of the top-emitting VCSEL210may be horizontally offset.

In the VCSEL device200, the bottom-emitting VCSEL206and the top-emitting VCSEL210are optically independent. In other words, there may be complete optical separation between an optical cavity of the bottom-emitting VCSEL206and an optical cavity of the top-emitting VCSEL210, as optical leakage between the bottom-emitting VCSEL206and the top-emitting VCSEL210may affect the performance of the top-emitting VCSEL210(e.g., the VCSEL that is stacked on top of another VCSEL).

The VCSEL device200may be implemented as a single chip that includes the bi-directional VCSELs206,210. That is, the bi-directional VCSELs206,210may share a single, common substrate layer202(e.g., a single, common wafer). Thus, the VCSEL device200provides integration of front-facing and world-facing VCSELs, which may be different optical powers (e.g., different quantities of active layers) and/or different emission wavelengths, in a single chip.

As indicated above,FIG.2is provided as an example. Other examples may differ from what is described with regard toFIG.2.

FIG.3is a diagram of an example VCSEL device300. The VCSEL device300may include a substrate layer302, similarly as described above. In addition, the VCSEL device300may include a first set of epitaxial layers304for a bottom-emitting VCSEL306(e.g., one or more bottom-emitting VCSELs306, such as a plurality of bottom-emitting VCSELs306) disposed on the substrate layer302, and the VCSEL device300may include a second set of epitaxial layers308for a top-emitting VCSEL310(e.g., one or more top-emitting VCSELs310, such as a plurality of top-emitting VCSELs310) disposed on the first set of epitaxial layers304. The VCSEL device300, including the first set of epitaxial layers304and the second set of epitaxial layers308, may be configured in a similar manner as described in connection with the VCSEL device200. The bottom-emitting VCSEL306and the top-emitting VCSEL310may be configured to emit light in opposite light emission directions342a,342b, in a similar manner as described above.

As shown inFIG.3, an emission area of the bottom-emitting VCSEL306and an emission area of the top-emitting VCSEL310may be offset in the direction orthogonal to the opposite light emission directions342a,342b(e.g., the emission area of the bottom-emitting VCSEL306and the emission area of the top-emitting VCSEL310may be horizontally offset), as described herein. The horizontal offset may be useful for satisfying module constraints or for producing particular VCSEL array patterns (as described in connection withFIG.4). For example, the VCSEL used for a front-facing application may require a dot projector with a randomized emitter layout, while the VCSEL used for a world-facing application, that is iToF-based, may require a uniform emitter array. The horizontal offset of the bottom-emitting VCSEL306and the top-emitting VCSEL310may also simplify fabrication of the VCSEL device300.

As indicated above,FIG.3is provided as an example. Other examples may differ from what is described with regard toFIG.3.

FIG.4is a diagram of example VCSEL arrays400,410, and420. The VCSEL arrays400,410, and420may include the VCSEL device300, or another VCSEL device described herein. For example, the VCSEL arrays400,410, and420may include the first set of epitaxial layers304for a plurality of bottom-emitting VCSELs306and the second set of epitaxial layers308for a plurality of the top-emitting VCSELs310. As shown, the VCSEL arrays400,410, and420may be arranged into various patterns for the plurality of bottom-emitting VCSELs306and the plurality of top-emitting VCSELs310(some of which could not be achieved using separate VCSEL chips). The patterns shown inFIG.4are provided as examples, and in some implementations, a VCSEL array may utilize a pattern different from that shown inFIG.4.

In the VCSEL array400, the plurality of bottom-emitting VCSELs306and the plurality of top-emitting VCSELs310may be separated onto different sections of a chip (e.g., left and right sections, top and bottom sections, or the like). For example, the plurality of bottom-emitting VCSELs306may be positioned to a first side of a line that sections the VCSEL array400(e.g., into equal sections, or into unequal sections), and the plurality of top-emitting VCSELs310may be positioned to a second side of the line, in a direction orthogonal to the opposite light emission directions342a,342b. The line may represent a starting position of an etch of the second set of epitaxial layers308that exposes a surface of the first set of epitaxial layers304.

In the VCSEL array410and in the VCSEL array420, the plurality of bottom-emitting VCSELs306and the plurality of top-emitting VCSELs310are intermixed. For example, the plurality of bottom-emitting VCSELs306may be arranged in a first pattern, and the plurality of top-emitting VCSELs310may be arranged in a second pattern. In the VCSEL array410, the plurality of bottom-emitting VCSELs306may be interleaved with the plurality of top-emitting VCSELs310in a uniform pattern (e.g., each row and each column of the VCSEL array410alternates between the plurality of bottom-emitting VCSELs306and the plurality of top-emitting VCSELs310). However, in some implementations, the plurality of bottom-emitting VCSELs306are interleaved with the plurality of top-emitting VCSELs310in a random pattern or in a quasi-random pattern. In other words, the first pattern of the plurality of bottom-emitting VCSELs306is interleaved with the second pattern of the plurality of top-emitting VCSELs310in the direction orthogonal to the opposite light emission directions242a,242b. In the VCSEL array410, etches of the second set of epitaxial layers308may expose (e.g., surround) individual VCSELs in the first set of epitaxial layers304. In some implementations, the etches of the second set of epitaxial layers308may expose multiple VCSELs in the first set of epitaxial layers304(e.g., the etches expose particular sections of a surface of the first set of epitaxial layers304).

In the VCSEL array420, the plurality of bottom-emitting VCSELs306surround (e.g., centrally, as shown, or offset from center) the plurality of top-emitting VCSELs310. In other words, the first pattern of the plurality of bottom-emitting VCSELs306surrounds the second pattern of the plurality of top-emitting VCSELs310in the direction orthogonal to the opposite light emission directions342a,342b. Here, an etch of the second set of epitaxial layers308may expose the plurality of bottom-emitting VCSELs306in the first set of epitaxial layers304. In some implementations, the plurality of bottom-emitting VCSELs306may surround multiple groups of the plurality of top-emitting VCSELs310. In some implementations, the plurality of top-emitting VCSELs310may surround the plurality of bottom-emitting VCSELs306in a similar manner.

In this way, a single optical component (e.g., that includes the VCSEL array400,410, or420) may provide front-facing and world-facing light emission with reduced module size and module complexity.

As indicated above,FIG.4is provided as an example. Other examples may differ from what is described with regard toFIG.4.

FIG.5is a diagram of an example module500. As shown inFIG.5, the module may include a VCSEL device501. The VCSEL device501may include a substrate layer502, similarly as described above. In addition, the VCSEL device501may include a first set of epitaxial layers504for a bottom-emitting VCSEL506(e.g., one or more bottom-emitting VCSELs506, such as a plurality of bottom-emitting VCSELs506) disposed on the substrate layer502, and the VCSEL device501may include a second set of epitaxial layers508for a top-emitting VCSEL510(e.g., one or more top-emitting VCSELs510, such as a plurality of top-emitting VCSELs510) disposed on the first set of epitaxial layers504. The VCSEL device501, including the first set of epitaxial layers504and the second set of epitaxial layers508, may be configured in a similar manner as described in connection with the VCSEL device200.

In addition, the module500may include a housing550. The VCSEL device501may be attached to the housing550. For example, the housing550may include a substrate to which the VCSEL device501is attached (e.g., at edges of the VCSEL device501) by bonding, or the like. As an example, the housing550may include a box (e.g., where a base of the box is the substrate), a tray (e.g., where a base of the tray is the substrate), or a plate (e.g., where the plate is the substrate).

In some implementations, the housing550may include an aperture552. That is, the substrate of the housing550may include the aperture552. An emission area of the bottom-emitting VCSEL506or an emission area of the top-emitting VCSEL510may be aligned with the aperture552of the housing550(e.g., such that light emitted from the bottom-emitting VCSEL506or the top-emitting VCSEL510passes through the aperture552). For example, the emission area of the bottom-emitting VCSEL506may be aligned with the aperture552of the housing550(e.g., such that the aperture surrounds the emission area of the bottom-emitting VCSEL506, and light emitted from the bottom-emitting VCSEL506passes through the aperture552), as shown.

In some implementations, the module500may include one or more optical elements (not shown) attached to the housing550. For example, an optical element for the bottom-emitting VCSEL506may be attached to the substrate at a surface of the substrate opposite the VCSEL device501. Here, the optical element may be attached to, or otherwise aligned with, the aperture552. As another example, an optical element for the top-emitting VCSEL510may be attached to the housing above the VCSEL device501.

As indicated above,FIG.5is provided as an example. Other examples may differ from what is described with regard toFIG.5.

In some implementations, the VCSEL device200, the VCSEL device300, and/or the VCSEL device501may employ a type of vertically-emitting device other than a VCSEL, as described herein. In some implementations, a module may include the VCSEL device200, the VCSEL device300, and/or the VCSEL device501. For example, the VCSEL device200, the VCSEL device300, and/or the VCSEL device501may be disposed in a housing with one or more additional electrical components (e.g., circuitry for driving the VCSEL device200, the VCSEL device300, and/or the VCSEL device501) and/or optical components (e.g., optical elements, such as lenses, diffusers, diffractive optical elements, or the like). In some implementations, an optical source (e.g., for three-dimensional sensing (3DS) or LIDAR) may include the VCSEL device200, the VCSEL device300, and/or the VCSEL device501. In some implementations, an optical system may include the VCSEL device200, the VCSEL device300, and/or the VCSEL device501. Moreover, the optical system may include one or more lenses, one or more optical elements (e.g., diffractive optical elements, refractive optical elements, or the like), one or more reflector elements, and/or one or more optical sensors, among other examples.

In some implementations, a VCSEL may achieve bi-directional light emission, as described herein, from the same active region. For example, reflectivities of the top mirror and the bottom mirror of the VCSEL may be configured such that light is emitted from both sides (e.g., the top and the bottom) of the VCSEL.

FIG.6is a flowchart of an example process600for forming bi-directional VCSELs, as described herein.

As shown inFIG.6, process600may include growing, on a substrate layer, a first set of epitaxial layers for a bottom-emitting VCSEL (e.g., a lower VCSEL) (block610). The substrate layer may correspond to the substrate layer202,302, or502. The first set of epitaxial layers may correspond to the first set of epitaxial layers204,304, or504. As further shown inFIG.6, process600may include growing, on the first set of epitaxial layers, a second set of epitaxial layers for a top-emitting VCSEL (e.g., an upper VCSEL) (block620). The second set of epitaxial layers may correspond to the second set of epitaxial layers208,308, or508. During growth in between respective sets of mirrors of the first set of epitaxial layers and the second set of epitaxial layers, limiting the epitaxial quality and thickness by the introduction of epitaxial dislocations or other strain effects should be avoided.

The first set of epitaxial layers and the second set of epitaxial layers may be grown during the same growth process on the same substrate layer. Moreover, the first set of epitaxial layers and the second set of epitaxial layers may be grown with different quantities of active layers and/or to emit light at different emission wavelengths. In some implementations, to configure different emission wavelengths for the first set of epitaxial layers and the second set of epitaxial layers, different growth processes may be used for the first set of epitaxial layers and the second set of epitaxial layers. For example, metal organic vapor phase epitaxy (MOVPE) and/or metal organic chemical vapor deposition (MOCVD) may be used to produce shorter wavelengths (e.g., 850 nm, 905 nm, and/or 940 nm), and molecular-beam epitaxy (MBE) may be used to produce longer wavelengths (e.g., greater than 1300 nm).

As further shown inFIG.6, process600may include etching a portion of the second set of epitaxial layers until a surface of the first set of epitaxial layers is exposed (block630). For example, to etch the portion of the second set of epitaxial layers, process600may include masking regions of the second set of epitaxial layers where operation (e.g., light emission) of the top-emitting VCSEL is desired and performing an etching process (e.g., wet etching, dry etching, or a combination thereof) to remove the second set of epitaxial layers in regions where operation (e.g., light emission) of the bottom-emitting VCSEL is desired. In some implementations, the second set of epitaxial layers may be etched to produce the pattern of VCSEL array400, the pattern of VCSEL array410, and/or the pattern of VCSEL array420, among other examples.

As further shown inFIG.6, process600may include forming at least one of the bottom-emitting VCSEL in the first set of epitaxial layers or the top-emitting VCSEL in the second set of epitaxial layers (block640). Forming the bottom-emitting VCSEL and/or the top-emitting VCSEL may include depositing metal contacts for the bottom-emitting VCSEL and/or the top-emitting VCSEL, exposing an oxidation layer of the bottom-emitting VCSEL and/or the top-emitting VCSEL, or the like. In some implementations, the bottom-emitting VCSEL and the top-emitting VCSEL both may be formed after the etching described in connection with block630. In some implementations, the top-emitting VCSEL may be formed prior to the etching described in connection with block630, and the bottom-emitting VCSEL may be formed after the etching described in connection with block630.

In some implementations, the bottom-emitting VCSEL and the top-emitting VCSEL may be formed independently. For example, the bottom-emitting VCSEL may be formed by masking regions of the VCSEL device other than a region for the bottom-emitting VCSEL, and the top-emitting VCSEL may be formed by masking regions of the VCSEL device other than a region for the top-emitting VCSEL. In some implementations, the bottom-emitting VCSEL and the top-emitting VCSEL may be formed simultaneously, for example, by simultaneously depositing respective metal contacts for each VCSEL and/or by simultaneously exposing respective oxidation layers of each VCSEL.

In this way, process600improves tolerances of the VCSEL device and eliminates the need for multiple wafers and/or multiple growth runs to produce a VCSEL device that is suitable for bi-directional light emission.

Process600may include additional implementations, such as any single implementation or any combination of implementations described below and/or in connection with one or more other processes described elsewhere herein.

AlthoughFIG.6shows example blocks of process600, in some implementations, process600includes additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted inFIG.6. Additionally, or alternatively, two or more of the blocks of process600may be performed in parallel.

The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the implementations to the precise forms disclosed. Modifications and variations may be made in light of the above disclosure or may be acquired from practice of the implementations. Furthermore, any of the implementations described herein may be combined unless the foregoing disclosure expressly provides a reason that one or more implementations may not be combined.

Even though particular combinations of features are recited in the claims and/or disclosed in the specification, these combinations are not intended to limit the disclosure of various implementations. In fact, many of these features may be combined in ways not specifically recited in the claims and/or disclosed in the specification. Although each dependent claim listed below may directly depend on only one claim, the disclosure of various implementations includes each dependent claim in combination with every other claim in the claim set. As used herein, a phrase referring to “at least one of” a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover a, b, c, a-b, a-c, b-c, and a-b-c, as well as any combination with multiple of the same item.

No element, act, or instruction used herein should be construed as critical or essential unless explicitly described as such. Also, as used herein, the articles “a” and “an” are intended to include one or more items, and may be used interchangeably with “one or more.” Further, as used herein, the article “the” is intended to include one or more items referenced in connection with the article “the” and may be used interchangeably with “the one or more.” Furthermore, as used herein, the term “set” is intended to include one or more items (e.g., related items, unrelated items, or a combination of related and unrelated items), and may be used interchangeably with “one or more.” Where only one item is intended, the phrase “only one” or similar language is used. Also, as used herein, the terms “has,” “have,” “having,” or the like are intended to be open-ended terms. Further, the phrase “based on” is intended to mean “based, at least in part, on” unless explicitly stated otherwise. Also, as used herein, the term “or” is intended to be inclusive when used in a series and may be used interchangeably with “and/or,” unless explicitly stated otherwise (e.g., if used in combination with “either” or “only one of”). Further, spatially relative terms, such as “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the apparatus, device, and/or element in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.