Patent ID: 12211559

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG.1is a block diagram showing the memory device10according to an embodiment. Referring toFIG.1, the memory device10may include a memory cell array100and a peripheral circuit200, and the peripheral circuit200may include a page buffer circuit210, a control circuit220, a voltage generator230, a row decoder240, a page buffer decoder (PBDEC)213, a mass bit counter (MBC)214, and a pass/fail checking unit215.

The memory cell array100may be connected to the page buffer circuit210through bit lines BL and may be connected to the row decoder240through word lines WL, string select lines SSL, and ground select lines GSL. The memory cell array100may include a plurality of memory cells. For example, the memory cells may be flash memory cells. Hereinafter, embodiments of the inventive concept will be described in detail based on an example case where the memory cells are nonvolatile memory cells such as NAND flash memory cells. However, the inventive concept is not limited thereto, and the memory cells may be resistive memory cells like resistive RAM (ReRAM) cells, phase change RAM (PRAM) cells, or magnetic RAM (MRAM) cells.

In an embodiment, the memory cell array100may include a 3-dimensional memory cell array. The 3-dimensional memory cell array may include a plurality of NAND strings, and each NAND string may include memory cells respectively connected to word lines vertically stacked on a substrate. Detailed descriptions thereof will be given later with reference toFIGS.3,4A, and4B. U.S. Pat. Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and U.S. Patent Application No. 2011/0233648 disclose detailed suitable configurations for a 3-dimensional memory array including multiple levels and in which word lines and/or bit lines are shared between the levels, and are incorporated herein by reference in their entirety.

The control circuit220may output various control signals, e.g., a voltage control signal CTRL_vol, a row address X_ADDR, and a column address Y_ADDR, for programming data to the memory cell array100, reading data from the memory cell array100, or erasing data stored in the memory cell array100, based on a command CMD, an address ADDR, and a control signal CTRL. Therefore, the control circuit220may overall control various operations within the memory device10.

The voltage generator230may generate various types of voltages for performing a program operation, a read operation, and an erase operation on the memory cell array100based on the voltage control signal CTRL_Vol. In detail, the voltage generator230may generate a word line voltage VWL, e.g., a program voltage, a read voltage, a pass voltage, an erase verify voltage, or a program verify voltage. The row decoder240may select one of a plurality of memory blocks in response to the row address X_ADDR, may select one of the word lines WL of a selected memory block, and may select one of the string select lines SSL. The page buffer circuit230may select at least some bit lines from among the bit lines BL in response to the column address Y_ADDR. In detail, the page buffer circuit210operates as a write driver or a sense amplifier depending on an operation mode.

The page buffer circuit210may include a plurality of page buffers PB respectively connected to a plurality of bit lines BL. Page buffer units (e.g., PBU0to PBUn ofFIG.5) respectively included in the page buffers PB and cache latches (e.g., CL0to CLn ofFIG.5) respectively included in the page buffers PB may be spaced apart from each other and have separate structures. Therefore, the degree of freedom for the wires arranged above the page buffer units may be improved and the complexity of the layout may be reduced. Also, since the cache latches are arranged adjacent to data input/output lines, a distance between the cache latches and the data input/output lines may be reduced, thereby improving a data input/output speed. Also, the page buffer units may be divided into two groups each including upper page buffer units, upper page buffer units and lower page buffer units, or lower page buffer units, and cache latches may be arranged between the upper page buffer units and the lower page buffer units.

According to an embodiment, each page buffer unit may include a pair of pass transistors (e.g., TR0and TR0′ ofFIG.11) and a sensing node line (e.g., MT0aofFIG.11) for electrically connecting the pair of pass transistors to each other. Here, the sensing node line may be implemented as one track of a lower metal layer (e.g., LM0ofFIG.11) and may correspond to a sensing node. A “track” as described herein, refers to a straight segment of material extending lengthwise in only one horizontal direction. An item, layer, or portion of an item or layer described as extending “lengthwise” in a particular direction has a length in the particular direction and a width perpendicular to that direction, where the length is greater than the width. During a data sensing period, pass transistors respectively included in the page buffer units may not be electrically connected to each other, and thus sensing node lines respectively included in the page buffer units may not be electrically connected to each other. Meanwhile, during a data transmission period, the pass transistors respectively included in the page buffer units may be connected to each other in series, and thus the sensing node lines respectively included in the page buffer units may be electrically connected to each other and used as data transmission lines. Therefore, since the page buffer circuit210does not need to separately provide a plurality of data transmission lines for respectively connecting the page buffer units and the cache latches, the area occupied by the page buffer circuit210may be reduced.

The PBDEC213may generate a decoder output signal DS corresponding to the number of fail bits from a page buffer signal PBS received from the page buffer circuit210. For example, when the page buffer signal PBS is logic low, it may be determined that programming to a corresponding memory cell has failed, and data of the corresponding memory cell may be determined as a fail bit. In detail, the PBDEC213may receive a reference current from a current generator (not shown) and generate the decoder output signal DS based on the received reference current.

The MBC214may receive the decoder output signal DS from the PBDEC213and generate a count result CNT from the decoder output signal DS. For example, the MBC214may be an analog-to-digital converter that converts the decoder output signal DS that is an analog signal into a count result CNT that is a digital signal. In detail, the MBC214may receive a reference current from the current generator (not shown) and generate the count result CNT based on the received reference current.

The pass/fail checking unit215, which may be a circuit, may receive the count result CNT from the MBC214, generate a pass signal PASS or a fail signal FAIL based on the count result CNT, and provide the pass signal PASS or the fail signal FAIL to the control circuit220. For example, when the count result CNT is less than or equal to a reference number, the pass/fail checking unit215may generate the pass signal PASS. When the count result CNT is greater than the reference number, the pass/fail checking unit215may generate the fail signal FAIL.

FIG.2is a diagram schematically showing the structure of the memory device10ofFIG.1, according to an embodiment. Referring toFIG.2, the memory device10may include a first semiconductor layer L1and a second semiconductor layer L2, and the first semiconductor layer L1may be stacked in a vertical direction VD with respect to the second semiconductor layer L2. In detail, the second semiconductor layer L2may be disposed below the first semiconductor layer L1in the vertical direction VD. According to an embodiment, the memory cell array100ofFIG.1may be formed in the first semiconductor layer L1, and the peripheral circuit200ofFIG.1may be formed in the second semiconductor layer L2. Therefore, the memory device10may have a structure in which the memory cell array100is disposed above the peripheral circuit200, that is, a cell-over-periphery (COP) structure. The COP structure may reduce a horizontal area and improve the degree of integration of the memory device10.

In an embodiment, the second semiconductor layer L2may include a substrate, and the peripheral circuit200may be formed in the second semiconductor layer L2by forming transistors and metal patterns (e.g., first and third lower metal layers LM0and LM2ofFIG.11) for wiring the transistors on the substrate. After the peripheral circuit200is formed on the second semiconductor layer L2, the first semiconductor layer L1including the memory cell array100may be formed, and metal patterns for electrically connecting the word lines WL and the bit lines BL of the memory cell array100to the peripheral circuit200formed in the second semiconductor layer L2may be formed. For example, the bit lines BL may extend in a first horizontal direction or a first direction HD1, and the word lines WL may extend in a second horizontal direction or a second direction HD2.

As the number of stacks of memory cells arranged in the memory cell array100increases (i.e., as the number of stacks of the word lines WL increases) with the development of semiconductor processing technology, the area of the memory cell array100is reduced, and thus the area of the peripheral circuit200is also reduced. According to the present embodiment, the page buffer circuit210has a structure in which page buffer units and cache latches are separated from each other, and, by connecting sensing nodes included in the respective page buffer units in common to a combined sensing node, the area occupied by the page buffer circuit210may be reduced. Detailed descriptions thereof will be given later with reference toFIG.11.

FIG.3is a diagram showing an example of the memory cell array100ofFIG.1, according to an embodiment. Referring toFIG.3, the memory cell array100may include a plurality of memory blocks BLK0to BLKi, and i may be a positive integer. The memory blocks BLK1to BLKi may each have a 3-dimensional structure (or a vertical structure). The memory blocks BLK0to BLKi may each include a plurality of NAND strings extending in the vertical direction VD. Here, the NAND strings may be provided to be a particular distance spaced apart from one another in the first direction HD1and the second direction HD2.

FIG.4Ais a perspective view of a memory block BLKa according to an embodiment. Referring toFIG.4A, the memory block BLKa may correspond to one of the memory blocks BLK1to BLKi ofFIG.3. The memory block BLKa is formed in the vertical direction VD with respect to a substrate SUB having a first conductivity type (e.g., p-type). According to an embodiment, the common source line CSL doped with impurities of a second conductivity type (e.g., n-type) may be provided on the substrate SUB. According to an embodiment, the substrate SUB may be implemented by using polysilicon, and a plate-type common source line CSL may be disposed on the substrate SUB. On the substrate SUB, a plurality of insulation layers IL extending in the second direction HD2are sequentially provided in the vertical direction VD, and the insulation layers IL are spaced apart from one another by a certain distance in the vertical direction VD. For example, the insulation layers IL may include or may be formed of an insulating material like silicon oxide.

A plurality of pillars P connected to each bit line, which pillars are sequentially arranged in the first direction HD1and penetrate through the insulation layers IL in the vertical direction VD, are provided on the substrate SUB. For example, the pillars P will contact the substrate SUB by penetrating through the insulation layers IL. In detail, a surface layer S of each pillar P may include or be formed of a silicon-based material doped with impurities of the first conductivity type and function as a channel region. Therefore, the pillars P may be referred to as a vertical channel structure. An internal layer I of each pillar P may include an insulating material like silicon oxide or an air gap.

A charge storage layer CS is provided along exposed surfaces of the insulation layers IL, the pillars P, and the substrate SUB. The charge storage layer CS may include a gate insulation layer, a charge trapping layer, and a blocking insulation layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. Also, on an exposed surface of the charge storage layer CS, gate electrodes GE such as a ground select line GSL, a string select line SSL, and word lines WL1to WL8are provided. Drains DR are provided on the pillars P, respectively. For example, the drains DR may include or be formed of a silicon-based material doped with impurities of the second conductivity type. Bit lines BL1to BL3extending in a first direction HD1and being a certain distance apart from one another in the second direction HD2may be provided on the drains DR.

FIG.4Bis a perspective view of a memory block BLKb according to an embodiment. Referring toFIG.4B, the memory block BLKb may correspond to one of the memory blocks BLK1to BLKi ofFIG.3. Also, the memory block BLKb corresponds to a modified example of the memory block BLKa ofFIG.4A, and the descriptions given above with reference toFIG.4Amay also be applied to the present embodiment. The memory block BLKb may include a first memory stack ST1and a second memory stack ST2stacked in the vertical direction VD. However, the inventive concept is not limited thereto, and the memory block BLKb may include three or more memory stacks.

FIG.5is a diagram showing an example of the connection between the memory cell array100and the page buffer circuit210according to an embodiment.

Referring toFIG.5, the memory cell array100may include first to n+1-th NAND strings NS0to NSn, the first to n+1-th NAND strings NS0to NSn may each include a ground select transistor GST connected to a ground select line GSL, a plurality of memory cells MC respectively connected to a plurality of word lines WL0to WLm, and a string select transistor SST connected to a string select line SSL, and the ground select transistor GST, the memory cells MC, and the string select transistor SST may be connected to one another in series and may be arranged in a vertical direction. Here, m is a positive integer.

The page buffer circuit210may include first to n+1-th page buffer units PBU0to PBUn. A first page buffer unit PBU0is connected to a first NAND string NS0through a first bit line BL0, and an n+1-th page buffer unit PBUn may be connected to an n+1-th NAND string NSn through an n+1th bit line BLn. Here, n is a positive integer. For example, n may be 7, and the first to n+1-th page buffer units PBU0to PBUn of the page buffer circuit210may be divided into an upper page buffer group and a lower page buffer group, wherein page buffer units included in the upper page buffer group may be arranged along a line, and page buffer units included in the lower page buffer group may be arranged along a line. Each page buffer unit may be described as a page buffer segment, since it is part of the page buffer circuit as a whole. Each page buffer unit may include a circuit that outputs a data bit corresponding to data being written to or read from a memory cell.

The page buffer circuit210may further include first to n+1-th cache latches CL0to CLn respectively corresponding to the first to n+1-th page buffer units PBU0to PBUn. For example, n may be 7, and the page buffer circuit210may have a structure in which eight cache latches CL0to CLn are arranged along a line. For example, the first to n+1-th cache latches CL0to CLn may be arranged along a line in a direction in which first to n+1-th bit lines BL0to BLn extend between the upper page buffer group and the lower page buffer group.

Sensing nodes of the first to n+1-th page buffer units PBU0to PBUn may be commonly connected to a combined sensing node SOC, and the first to n+1-th cache latches CL0to CLn may also be commonly connected to the SOC. Therefore, the first to n+1-th page buffer units PBU0to PBUn may be connected to the first to n+1-th cache latches CL0to CLn through the combined sensing node SOC.

FIG.6is a diagram showing a page buffer PB according to an embodiment.

Referring toFIG.6, the page buffer PB may correspond to an example of the page buffer PB ofFIG.1. The page buffer PB may include a page buffer unit PBU and a cache unit CU. Since the cache unit CU includes a cache latch CL (C-LATCH), and the cache latch CL is connected to a data input/output line, the cache unit CU may be disposed adjacent to the data input/output line. Therefore, the page buffer unit PBU and the cache unit CU may be disposed to be spaced apart from each other, and thus the page buffer PB may have a structure in which the page buffer unit PBU and the cache unit CU are separated from each other.

The page buffer unit PBU may include a main unit MU, and the main unit MU may include major transistors in the page buffer PB. The page buffer unit PBU may further include a bit line select transistor TR_hv connected to a bit line BL and driven by a bit line select signal BLSLT. The bit line selection transistor TR_hv may be implemented as a high-voltage transistor and may be disposed in a well region different from the main unit MU, that is, in a high-voltage unit HVU.

The main unit MU may include a sensing latch SL (S-LATCH), a force latch FL (F-LATCH), an upper bit latch or most-significant-bit latch ML (M-LATCH), and a lower bit latch or a least-significant-bit latch LL (L-LATCH). According to some embodiments, the sensing latch SL, the force latch FL, the more-significant-bit latch ML, or the less-significant-bit latch LL may be referred to as a “main latch”. The main unit MU may further include a pre-charge circuit PC capable of controlling a pre-charge operation for the bit line BL or a sensing node SO based on a bit line clamping control signal BLCLAMP and may further include a transistor PM′ driven by a bit line setup signal BLSETUP.

The sensing latch SL may store data stored in a memory cell or a result of sensing a threshold voltage of a memory cell during a read operation or a program verification operation. Also, the sensing latch SL may be used to apply a program bit line voltage or a program inhibit voltage to the bit line BL during a program operation. The force latch FL may be used to store force data and improve threshold voltage distribution during a program operation. The force data may be initially set to ‘1’ and then inverted to ‘0’ when the threshold voltage of a memory cell enters a forcing region that is less than a target region. The more-significant-bit latch ML, the less-significant-bit latch LL, and the cache latch CL may be used to store data input from the outside during a program operation. The cache latch CL may receive data read from a memory cell during a read operation from the sensing latch SL and output the data to the outside through a data input/output line.

The main unit MU may further include first to fourth transistors NM1to NM4. A first transistor NM1may be connected between the sensing node SO and the sensing latch SL and may be driven by a ground control signal SOGND. A second transistor NM2may be connected between the sensing node SO and the force latch FL and may be driven by a forcing monitoring signal MON_F. A third transistor NM3may be connected between the sensing node SO and the more-significant-bit latch ML and may be driven by a more-significant-bit monitoring signal MON_M. A fourth transistor NM4may be connected between the sensing node SO and the less-significant-bit latch LL and may be driven by a less-significant-bit monitoring signal MON_L.

The main unit MU may further include a fifth transistor NM5and a sixth transistor NM6connected in series between the bit line select transistor TR_hv and the sensing node SO. A fifth transistor NM5may be driven by a bit line shut-off signal BLSHF, and a sixth transistor NM6may be driven by a bit line connection control signal CLBLK. Also, the main unit MU may further include a pre-charge transistor PM. The pre-charge transistor PM is connected to the sensing node SO, is driven by a load signal LOAD, and pre-charges the sensing node SO to a pre-charge level during a pre-charge period.

The main unit MU may further include a pair of pass transistors connected to the sensing node SO, that is, a first pass transistor TR and a second pass transistor TR′. According to some embodiments, the first pass transistor TR and the second pass transistors TR′ may be referred to as “a first sensing node connecting transistor and a second sensing node connecting transistor”, respectively. The first pass transistor TR and the second pass transistors TR′ may be driven according to a pass control signal SO_PASS. According to some embodiments, the pass control signal SO_PASS may be referred to as a “sensing node connection control signal”. A first pass transistor TR may be connected between a first terminal SOC_U and the sensing node SO, and a second pass transistor TR′ may be connected between the sensing node SO and a second terminal SOC_D.

For example, when the page buffer unit PBU is a second page buffer unit PBU1ofFIG.5, the first terminal SOC_U may be connected to one end of a pass transistor included in the first page buffer unit PBU0, and the second terminal SOC_D may be connected to one end of a pass transistor included in a third page buffer unit PBU2. Therefore, the sensing node SO may be electrically connected to the combined sensing node SOC through pass transistors respectively included in third to n+1-th page buffer units PBU2to PBUn.

FIG.7is a timing diagram showing an example of voltage levels of a pass control signal according to a core operation sequence, according to an embodiment. Referring toFIGS.6and7together, the core operation sequence represents the operation of the page buffer PB. For example, the core operation sequence may include a data sensing period71in which a data sensing operation is performed and a data dumping period or a data transmission period72in which a data dumping operation or a data transmission operation is performed.

In the data sensing period71, the pass control signal SO_PASS may be deactivated, and the first pass transistor TR and the second pass transistors TR′ may be turned off. Therefore, the page buffer unit PBU may not be electrically connected to the combined sensing node SOC, and the page buffer unit PBU may not be electrically connected to the cache unit CU. Also, the page buffer unit PBU may not be electrically connected to an adjacent page buffer unit PBU. For example, the data sensing period71may include a pre-charge period for pre-charging the voltage of the bit line BL or the sensing node SO to a pre-charge level, a develop period for electrically connecting the bit line BL to the sensing node SO to develop the voltage of the sensing node SO, and a sensing period for sensing the voltage of the sensing node SO.

In the data transmission period72, the pass control signal SO_PASS may be activated, and the first pass transistor TR and the second pass transistors TR′ may be turned on. Therefore, the page buffer unit PBU may be electrically connected to the combined sensing node SOC, and the page buffer unit PBU may be electrically connected to the cache unit CU. Also, the page buffer unit PBU may be electrically connected to an adjacent page buffer unit PBU. For example, the data transmission period72may include a period in which an operation of dumping read data stored in the sensing latch SL to the cache latch CL is performed, a period in which an operation of dumping program data stored in the cache latch CL to the sensing latch SL is performed, or a period in which data stored in the cache latch CL is transmitted to a data input/output circuit.

FIG.8is a timing diagram showing another example of voltage levels of a pass control signal according to a core operation sequence, according to an embodiment. Referring toFIGS.6and8together, the core operation sequence represents the operation of the page buffer PB. For example, the core operation sequence may include a bit line setup period81, a forcing dumping period82, a bit line forcing period83, a data dumping period or a data transmission period84, and an MBC period85.

In the bit line setup period81, the pass control signal SO_PASS may be activated, and the first pass transistor TR and the second pass transistors TR′ may be turned on. At this time, as the sensing node SO and the combined sensing node SOC are electrically connected, data may be dumped from the main latch (e.g., the sensing latch SL, the force latch FL, the more-significant-bit latch ML, or the less-significant-bit latch LL) included in the page buffer unit PBU to the cache latch CL.

In the forcing dumping period82and the bit line forcing period83, the pass control signal SO_PASS may be deactivated, and the first pass transistor TR and the second pass transistors TR′ may be turned off. Therefore, the page buffer unit PBU may not be electrically connected to the cache unit CU and may not be electrically connected to an adjacent page buffer unit PBU. In the forcing dumping period82, a dumping operation may be performed to select a bit line to be forced to a bias lower than a power voltage level when a program operation is performed. For example, data may be dumped from the force latch FL to the sensing latch SL. In the bit line forcing period83, a voltage applied to the bit line BL may be changed according to a value stored in the force latch FL during a program operation.

In the data transmission period84, the pass control signal SO_PASS may be activated, and the first pass transistor TR and the second pass transistors TR′ may be turned on. For example, in the data transmission period84, a dumping operation of marking data stored in the sensing latch SL connected to memory cells, which failed as a result of a program verification, from among memory cells, which are to be programmed to a target program state when a program operation is performed, as logic low may be performed. Here, as the sensing node SO and the combined sensing node SOC are electrically connected, data may be dumped from the cache latch CL to the main latch (e.g., the sensing latch SL).

In the MBC period85, the pass control signal SO_PASS may be deactivated, and the first pass transistor TR and the second pass transistors TR′ may be turned off. Therefore, the page buffer unit PBU may not be electrically connected to the cache unit CU and may not be electrically connected to an adjacent page buffer unit PBU. In the MBC period85, the number of sensing latches marked as logic low in the previous data transmission period84may be counted.

FIG.9is a diagram showing the page buffer circuit210and the PBDEC213according to an embodiment. Referring toFIG.9, the page buffer circuit210may have a structure having multiple stages in the first direction HD1, e.g., 8-stages STAGE0to STAGE7. The page buffer circuit210includes first to fourth page buffer circuits PGBUFa to PGBUFd arranged along the second direction HD2, and the first to fourth page buffer circuits PGBUFa to PGBUFd may be referred to as “first to fourth page buffer columns”. The first to fourth page buffer circuits PGBUFa to PGBUFd may each include first to eighth page buffer units PBU0to PBU7and first to eighth cache units CU0to CU7arranged in the first direction HD1. Here, the number of page buffer columns included in the page buffer circuit210and the number of page buffer units and the number of cache units included in each page buffer column may be variously changed according to embodiments. It should be noted that the first direction HD1and second direction HD2refer to horizontal directions, in relation to the vertical direction VD described, for example, in connection withFIGS.2,3,4A, and4B.

Since the size of the first to eighth page buffer units PBU0to PBU7in the second direction HD2decreases as the width of a transistor decreases, more page buffer units can be included in the same row in the page buffer circuit210(e.g., a row extends in the HD2direction). Therefore, the page buffer circuit210may be implemented as a page buffer array including the first to fourth page buffer circuits PGBUFa to PGBUFd. Hereinafter, the configuration of a first page buffer circuit PGBUFa will be described. Descriptions of the first page buffer circuit PGBUFa may also be applied to second to fourth page buffer circuits PGBUFb to PGBUFd.

The first to eighth page buffer units PBU0to PBU7may be separated into two groups. First to fourth page buffer units PBU0to PBU3corresponding to first to fourth stages STAGE0to STAGE3may be referred to as upper page buffer units PBU0to PBU3, or a first set of page buffer units, and fifth to eighth page buffer units PBU4to PBU7corresponding to fifth to eighth stages STAGE4to STAGE7may be referred to as lower page buffer units PBU4to PBU7, or a second set of page buffer units. Each set of page buffer units may include a plurality of page buffer units directly and consecutively adjacent to each other in a particular direction (e.g., the HD1direction).

The first to eighth cache units CU0to CU7may be arranged between the upper page buffer units, e.g., the first to fourth page buffer units PBU0to PBU3, and the lower page buffer units, e.g., the fifth to eighth page buffer units PBU4to PBU7. For example, along the direction that the page buffer units are consecutively arranged (e.g., the HD1direction), the first to eighth cache units CU0to CU7may be arranged also along the same direction, and all of the first to eighth cache units CU0to CU7may be positioned between a first set of page buffer units and a second set of page buffer units. Here, the first to eighth cache units CU0to CU7may be separated into two groups, or sets. First to fourth cache units CU0to CU3may be arranged adjacent to the first to fourth page buffer units PBU0to PBU3in correspondence to the first to fourth page buffer units PBU0to PBU3, respectively, and may be referred to as upper cache units CU0to CU3, or a first set of cache units. Meanwhile, fifth to eighth cache units CU4to CU7may be arranged adjacent to the fifth to eighth page buffer units PBU4to PBU7in correspondence to the fifth to eighth page buffer units PBU4to PBU7, respectively, and may be referred to as or lower cache units CU4to CU7, or a second set of cache units. Ordinal numbers such as “first,” “second,” “third,” etc. may be used simply as labels of certain elements, steps, etc., to distinguish such elements, steps, etc. from one another. Terms that are not described using “first,” “second,” etc., in the specification, may still be referred to as “first” or “second” in a claim. In addition, a term that is referenced with a particular ordinal number (e.g., “first” in a particular claim) may be described elsewhere with a different ordinal number (e.g., “second” in the specification or another claim). Also, the terms “upper” and “lower” in the context of page buffer units and cache units and their related components as discussed in connection withFIGS.5-12for example, may be used as a naming convention to refer to a set of units that are all at a particular location in relation to a second set of units.

In the first page buffer circuit PGBUFa, sensing nodes of the first to fourth page buffer units PBU0to PBU3may be commonly connected to a first combined sensing node SOC1, the first to fourth cache units CU0to CU3may be commonly connected to the first combined sensing node SOC1, sensing nodes of the fifth to eighth page buffer units PBU4to PBU7may be commonly connected to a second combined sensing node SOC1′, and the fifth to eighth cache units CU4to CU7may be commonly connected to the second combined sensing node SOC1′. Similarly, a second page buffer circuit PGBUFb may include a first combined sensing node SOC2and a second combined sensing node SOC2′, a third page buffer circuit PGBUFc may include a first combined sensing node SOC3and a second combined sensing node SOC3′, and a fourth page buffer circuit PGBUFd may include a first combined sensing node SOC4and a second combined sensing node SOC4′.

The PBDEC213may be disposed between the first to fourth cache units CU0to CU3and the fifth to eighth cache units CU4to CU7. The PBDEC213may include first to fourth PBDECs PBDECa to PBDECd arranged in the second direction HD2, and the first to fourth PBDECs PBDECa to PBDECd may be connected to the first to fourth page buffer circuits PGBUFa to PGBUFd, respectively. A first PBDEC PBDECa may be connected to the first to fourth page buffer units PBU0to PBU3and the first to fourth cache units CU0to CU3and may also be connected to the fifth to eighth page buffer units PBU4to PBU7and the fifth to eighth cache units CU4to CU7.

FIG.10is a diagram showing the page buffer circuit210and the PBDEC213according to an embodiment in more detail. Referring toFIG.10, the page buffer circuit210may include first to fourth areas AR1to AR4arranged in the first direction HD1. The first to fourth page buffer units PBU0to PBU3may be arranged in a first area AR1, the first to fourth cache units CU0to CU3may be arranged in a second area AR2, the fifth to eighth cache units CU4to CU7may be arranged in a third area AR3, and the fifth to eighth page buffer units PBU4to PBU7may be arranged in a fourth area AR4. The PBDEC213may be disposed between the second area AR2and the third area AR3.

As described above with reference toFIG.6, each page buffer unit PBU may include the main unit MU and the high-voltage unit HVU, and redundant descriptions thereof will be omitted. The first page buffer unit PBU0may include a main unit MU0and a high-voltage unit HVU0, the second page buffer unit PBU1may include a main unit MU1and a high-voltage unit HVU1, and a contact area THVa may be disposed between the first page buffer unit PBU0and the second page buffer unit PBU1. Similarly, a fifth page buffer unit PBU4may include a main unit MU4and a high-voltage unit HVU4, a sixth page buffer unit PBU5may include a main unit MU5and a high-voltage unit HVU5, and a contact area THVc may be disposed between the fifth page buffer unit PBU4and the sixth page buffer unit PBU5.

Main units MU0to MU7may each include a sensing node, and the sensing node is indicated by a dot inFIG.10. The PBDEC213may be connected to sensing nodes included in main units MU0to MU3through an upper node and may be connected to sensing nodes included in main units MU4to MU7through a lower node.

FIG.11is a plan view of a partial area of a page buffer circuit PGBUF according to an embodiment.FIG.12is a circuit diagram showing the partial area of a page buffer circuit PGBUF according to an embodiment.

Referring toFIGS.11and12together, the page buffer circuit PGBUF may correspond to one of the first to fourth page buffer circuits PGBUFa to PGBUFd ofFIG.9. The page buffer circuit PGBUF may include the first to fourth page buffer units PBU0to PBU3arranged in the first area AR1and the first to fourth cache units CU0to CU3arranged in the second area AR2. AlthoughFIGS.11and12show only portions corresponding to the first area AR1and the second area AR2for convenience of illustration, the fifth to eighth cache units CU4to CU7and the fifth to eighth page buffer units PBU4to PBU7arranged in the third area AR3and the fourth area AR4may also be implemented similarly.

The first to fourth page buffer units PBU0to PBU3may each include two pass transistors, and thus the first to fourth page buffer units PBU0to PBU3may include total eight pass transistors TR0, TR0′ to TR3, and TR3′, wherein the eight pass transistors TR0, TR0′ to TR3, and TR3′ may be connected in series. For example, the first page buffer unit PBU0may include a first pass transistor TR0and a second pass transistor TR0′ connected in series. For example, the first pass transistor TR0may be disposed adjacent to a first boundary of the first page buffer unit PBU0, the second pass transistor TR0′ may be disposed adjacent to a second boundary of the first page buffer unit PBU0, and the first boundary and the second boundary may be opposite each other. For example, the first pass transistor TR0and the second pass transistor TR0′ may be implemented as NMOS transistors, and thus the first pass transistor TR0and the second pass transistor TR0′ may be arranged at opposite ends of a P well of the first page buffer unit PBU0. However, the inventive concept is not limited thereto. Meanwhile, another semiconductor device, e.g., a PMOS transistor or an NMOS transistor, may be further disposed between the first boundary of the first page buffer unit PBU0and the first pass transistor TR0. Similarly, another semiconductor device, e.g., a PMOS transistor or an NMOS transistor, may be further disposed between the second boundary of the first page buffer unit PBU0and the second pass transistor TR0′.

For example, the first page buffer unit PBU0may further include a plurality of transistors (e.g., transistors included in the sensing latch SL, the force latch FL, the more-significant-bit latch ML, and the less-significant-bit latch LL ofFIG.6, first to sixth transistors NM1to NM6, etc.) arranged in the first direction HD1between the first pass transistor TR0and the second pass transistor TR0′. Descriptions below will focus on the configuration of the first page buffer unit PBU0, and second to fourth page buffer units PBU1to PBU3may have substantially the same configuration as that of the first page buffer unit PBU0.

The first pass transistor TR0may include a source S0, a drain D0, and a gate G0, the source S0may be connected to a first terminal (e.g., SOC_U ofFIG.6), the drain D0may be connected to a first sensing node SO0, and a first pass control signal SO_PASS0may be applied to the gate G0. The second pass transistor TR0′ may include a source S0′, a drain D0′, and a gate G0′, the source S0′ may be connected to the first sensing node SO0, the drain D0′ may be connected to a second terminal (e.g., SOC_D ofFIG.6), and the first pass control signal SO_PASS0may be applied to the gate G0′.

Similarly, the second page buffer unit PBU1may include a first pass transistor TR1and a second pass transistor TR1′ connected in series. The first pass transistor TR1may include a source S1, a drain D1, and a gate G1, the second pass transistor TR1′ may include a source S1′, a drain D1′, and a gate G1′, and a second pass control signal SO_PASS1may be applied to gates G1and G1′. The third page buffer unit PBU2may include a first pass transistor TR2and a second pass transistor TR2′ connected in series. The first pass transistor TR2may include a source S2, a drain D2, and a gate G2, the second pass transistor TR2′ may include a source S2′, a drain D2′, and a gate G2′, and a third pass control signal SO_PASS2may be applied to gates G2and G2′. The fourth page buffer unit PBU3may include a first pass transistor TR3and a second pass transistor TR3′ connected in series. The first pass transistor TR3may include a source S3, a drain D3, and a gate G3, the second pass transistor TR3′ may include a source S3′, a drain D3′, and a gate G3′, and a fourth pass control signal SO_PASS3may be applied to gates G3and G3′. However, the inventive concept is not limited thereto, and, according to some embodiments, a combined sensing node pass control signal SOC_PASS may be applied to the gate G3′.

A first cache unit CU0may include a monitor transistor NM7a, the monitor transistor NM7amay include a source S, a drain D, and a gate G, the source S may be connected to the first combined sensing node SOC1, and a cache monitoring signal MON_C0may be applied to the gate G. For example, the monitor transistor NM7amay correspond to a transistor NM7ofFIG.6. The first cache unit CU0may further include a plurality of transistors arranged in the first direction HD1(e.g., a plurality of transistors included in the cache latch CL ofFIG.6). Second to fourth cache units CU1to CU3may each have substantially the same configuration as that of the first cache unit CU0. Monitor transistors NM7ato NM7drespectively included in the first to fourth cache units CU0to CU3may be commonly connected in parallel to the first combined sensing node SOC1. In detail, sources of the monitor transistors NM7ato NM7dmay be commonly connected to the first combined sensing node SOC1.

In the first page buffer unit PBU0, the drain D0of the first pass transistor TR0and the source S0′ of the second pass transistor TR0′ may be connected to each other through a first conductive line or a first metal pattern MT0a. Since the first metal pattern MT0amay correspond to the first sensing node SO0, the first metal pattern MT0amay be referred to as a “first sensing node line”. In the second page buffer unit PBU1, the drain D1of the first pass transistor TR1and the source S1′ of the second pass transistor TR1′ may be connected to each other through a first metal pattern MT0b. Since the first metal pattern MT0bmay correspond to a second sensing node SO1, the first metal pattern MT0bmay be referred to as a “second sensing node line”. In the third page buffer unit PBU2, the drain D2of the first pass transistor TR2and the source S2′ of the second pass transistor TR2′ may be connected to each other through a first metal pattern MT0c. Since the first metal pattern MT0cmay correspond to a third sensing node SO2, the first metal pattern MT0cmay be referred to as a “third sensing node line”. In the fourth page buffer unit PBU3, the drain D3of the first pass transistor TR3and the source S3′ of the second pass transistor TR3′ may be connected to each other through a first metal pattern MT0d. Since the first metal pattern MT0dmay correspond to a fourth sensing node SO3, the first metal pattern MT0dmay be referred to as a “fourth sensing node line”. Here, first to fourth sensing node lines may be arranged in a line in the first direction HD1.

The drain D3′ of the second pass transistor TR3′ of the fourth page buffer unit PBU3and the source S of the monitor transistor NM7aof the first cache unit CU0may be connected to each other through a first metal pattern MT0e. Here, the first metal pattern MT0emay also be connected to a pre-charge circuit SOC_PRE. The first metal pattern MT0emay correspond to the first combined sensing node SOC1, and thus the first metal pattern MT0emay be referred to as a “first combined sensing node line”. Here, the first to fourth sensing node lines and the first combined sensing node line may be arranged in a line in the first direction HD1. According to an embodiment, first metal patterns MT0a, MT0b, MT0c, MT0d, and MT0emay be implemented as a first lower metal layer LM0and each occupy one track (e.g., along a straight line) of the first lower metal layer LM0. Each metal pattern and metal layer may be formed, for example, by an electroplating process, or other metal deposition process.

The drain D0′ of the second pass transistor TR0′ of the first page buffer unit PBU0and the source S1of the first pass transistor TR1of the second page buffer unit PBU1may be connected to each other through a second conductive line or a second metal pattern MT1a, and the second metal pattern MT1amay be referred to as a “first node connecting line”. The drain D1′ of the second pass transistor TR1′ of the second page buffer unit PBU1and the source S2of the first pass transistor TR2of the third page buffer unit PBU2may be connected to each other through a second metal pattern MT1b, and the second metal pattern MT1bmay be referred to as a “second node connecting line”. The drain D2′ of the second pass transistor TR2′ of the third page buffer unit PBU2and the source S3of the first pass transistor TR3of the fourth page buffer unit PBU3may be connected to each other through a second metal pattern MT1c, and the second metal pattern MT2cmay be referred to as a “third node connecting line”. For example, second metal patterns MT1a, MT1b, and MT1cmay be implemented as a third lower metal layer LM2and each occupy one track (e.g., along a straight line) of the third lower metal layer LM2. However, the inventive concept is not limited thereto, and the second metal pattern MT1amay be implemented as a second lower metal layer. Also, according to some embodiments, the second metal patterns MT1a, MT1b, and MT1cmay be implemented as the first lower metal layer LM0and may occupy one track of the first lower metal layer LM0. As discussed herein, a “track” refers to an area formed along a straight line.

According to the present embodiment, when the pass control signal SO_PASS is activated, first pass transistors TR0to TR3and second pass transistors TR0′ to TR3′ are turned on, and thus first and second pass transistors TR0to TR3′ included in the first to fourth page buffer units PBU0to PBU3may be connected to each other in series, and first to fourth sensing nodes SO0to SO3may be connected to the first combined sensing node SOC1. In detail, first and second sensing nodes SO0and SO1may be connected to each other through first metal patterns MT0aand MT0band the second metal pattern MT1a, second and third sensing nodes SO1and SO2may be connected to each other through first metal patterns MT0band MT0cand a second metal pattern MT1b, third and fourth sensing nodes SO2and SO3may be connected to each other through first metal patterns MT0cand MT0dand a second metal pattern MT1c, and the fourth sensing node SO3and the first combined sensing node SOC1may be connected to each other through first metal patterns MT0dand MT0e.

First metal patterns MT0a, MT0b, MT0c, and MT0dcorresponding to the first to fourth sensing node lines, the second metal patterns MT1a, MT1b, and MT1ccorresponding to node connecting lines, and the first metal pattern MT0ecorresponding to the combined sensing node line may constitute “data transmission lines”. As described above, according to the present embodiment, it is not necessary to separately provide four data transmission lines for connecting the first to fourth page buffer units PBU0to PBU3and the first to fourth cache units CU0to CU3, and sensing node lines included in the first to fourth page buffer units PBU0to PBU3may be used as data transmission lines. Therefore, since the number of metal lines needed for wiring of the page buffer circuit PGBUF may be reduced, the complexity of a layout may be reduced and the size of the page buffer circuit PGBUF may be reduced.

The first to fourth page buffer units PBU0to PBU3may further include pre-charge transistors PM0to PM3, respectively. In the first page buffer unit PBU0, a pre-charge transistor PM0is connected between the first sensing node SO0and a voltage terminal to which a pre-charge voltage is applied and may include a gate to which a load signal LOAD0is applied. The pre-charge transistor PM0may pre-charge the first sensing node SO0to the pre-charge level corresponding to the pre-charge voltage in response to the load signal LOAD0.

The page buffer circuit PGBUF may include contact areas THVa and THVb. The contact area THVa may be disposed between the first page buffer unit PBU0and the second page buffer unit PBU1, and a contact area THVb may be disposed between the third page buffer unit PBU2and the fourth page buffer unit PBU3. First and second bit line contacts CT0and CT1respectively connected to first and second bit lines may be arranged in the contact area THVa. A first bit line contact CT0may be connected to the first page buffer unit PBU0, and a second bit line contact CT1may be connected to the second page buffer unit PBU1. For example, the first bit line contact CT0may be connected to a high-voltage transistor (e.g., TR_hv ofFIG.6) included in a high-voltage unit (e.g., HVU0ofFIG.10), and the second bit line contact CT1may be connected to a high-voltage transistor included in a high-voltage unit (e.g., HVU1ofFIG.10). Third and fourth bit line contacts CT2and CT3respectively connected to third and fourth bit lines may be arranged in the contact area THVb. A third bit line contact CT2may be connected to the third page buffer unit PBU2, and a fourth bit line contact CT3may be connected to the fourth page buffer unit PBU3. For example, the third bit line contact CT2may be connected to a high-voltage transistor included in a high-voltage unit (e.g., HVU2ofFIG.10), and the fourth bit line contact CT3may be connected to a high-voltage transistor included in a high-voltage unit (e.g., HVU3ofFIG.10). The bit line contacts and other conductive contacts described herein may be formed, for example, of conductive material such as metal, extending vertically between a device (e.g., transistor) to which it is connected, and a conductive pattern at a different vertical level from the device. As can be seen inFIG.11, the second metal patterns MT1a, MT1b, MT1c, and MT1dmay be at a particular level and may connect to devices at a different level through conductive contacts.

The page buffer circuit PGBUF may further include a pre-charge circuit SOC_PRE between the fourth page buffer unit PBU3and the first cache unit CU0. The pre-charge circuit SOC_PRE may include a pre-charge transistor PMa for pre-charging the first combined sensing node SOC1and a shielding transistor NMa. The pre-charge transistor PMa is driven by a combined sensing node load signal SOC_LOAD, and, when the pre-charge transistor PMa is turned on, the first combined sensing node SOC1may be pre-charged to a pre-charge level. The shielding transistor NMa is driven by a combined sensing node shielding signal SOC_SHLD, and, when the shielding transistor NMa is turned on, the first combined sensing node SOC1may be discharged to a ground level.

As a transistor width WD decreases according to the process miniaturization, the area occupied by the page buffer circuit PGBUF may decrease. For example, the transistor width WD may correspond to the size of the gate G0of the first pass transistor TR0in the second direction HD2. In detail, as the transistor width WD decreases, the size of the first page buffer unit PBU0in the second direction HD2may decrease. However, despite the decrease in the transistor width WD, the pitch of the first lower metal layer LM0may not decrease. Therefore, the number of wires (i.e., the number of metal patterns) of the first lower metal layer LM0disposed on the first page buffer unit PBU0having a reduced size in the second direction HD2is also reduced. For example, the number of metal patterns of the first lower metal layer LM0corresponding to the first page buffer unit PBU0may be reduced from 6 to 4.

As described above, when the number of metal patterns of the first lower metal layer LM0corresponding to the first page buffer unit PBU0is reduced, the sensing reliability of the first page buffer unit PBU0may be deteriorated. For example, during a sensing operation, to prevent coupling between the first sensing node S00and an adjacent node, a metal pattern adjacent to the first sensing node SO0may be used as a shielding line to which a fixed bias is applied. However, when a metal pattern corresponding to a shielding line is removed due to the reduction of metal patterns, the voltage variation at the first sensing node SO0may increase due to the coupling between the first sensing node SO0and an adjacent node, and thus the sensing reliability of the first page buffer unit PBU0may be deteriorated.

However, according to the present embodiment, by arranging the first page buffer unit PBU0and the first cache unit CU0separately, the degree of freedom regarding first and third lower metal layers LM0and LM2arranged above the first page buffer unit PBU0increases, and at least one of metal patterns included in the first and third lower metal layers LM0and LM2may be used as a shielding line for the first sensing node SO0. Therefore, it is possible to prevent an increase in the voltage variation at the first sensing node SO0, thereby preventing deterioration of the sensing reliability of the first page buffer unit PBU0.

Meanwhile, in a structure in which the first to fourth page buffer units PBU0to PBU3and the first to fourth cache units CU0to CU3are separated, when eight signal lines are arranged to respectively connect the first to fourth page buffer units PBU0to PBU3and the first to fourth cache units CU0to CU3, the size of the page buffer circuit PGBUF in the second direction HD2may increase again. However, according to the present embodiment, the first to fourth sensing nodes SO0to SO3may be connected to one another by using the first pass transistors TR0to TR3and the second pass transistors TR0′ to TR3′ included in the first to fourth page buffer units PBU0to PBU3, and the first to fourth sensing nodes SO0to SO3may be connected to the first to fourth cache units CU0to CU3through the first combined sensing node SOC1. Here, since sensing node lines for connecting first and second pass transistors included in page buffer units to each other are implemented by using metal patterns (e.g., MT0a, MT0b, MT0c, and MT0d) of one track of the first lower metal layer LM0, the increase in the size of the page buffer circuit PGBUF in the second direction HD2may be prevented.

A PBDEC PBDECa may include a first inverter IVT0, a second inverter IVT1, and transistors N0, N0′, N0″, and N1. The first inverter IVT0may receive a first page buffer signal PBS0from the first to fourth page buffer units PBU0to PBU3, and an output of the first inverter IVT0may be provided to a gate of a transistor N0. The second inverter IVT1may receive a second page buffer signal PBS1from the fifth to eighth page buffer units PBU4to PBU7, and an output of the second inverter IVT1may be provided to a gate of a transistor N1. Sources of transistors N0and N1may be connected to a ground terminal, and drains of the transistors N0and N1may be commonly connected to a transistor N0′. The transistors N0′ and N0″ are connected in series, a reference current signal REF_CUR is applied to a gate of the transistor N0″, and a control signal nCR is applied to a gate of the transistor N0′.

For example, when a program operation with respect to a memory cell connected to the first page buffer unit PBU0has failed, a logic low level may be stored in a sensing latch of the first page buffer unit PBU0, and, in this case, the voltage level of the first page buffer signal PBS0may be logic low corresponding to the voltage level of the first sensing node SO0, and the voltage level of the first combined sensing node SOC1may also be logic low. In this case, the first inverter IVT0may output a logic high signal, and thus the transistor N0may be turned on and the PBDEC PBDECa may operate as a current sink. The transistor N0″ may output a first signal, that is, a reference current, to a wired OR terminal WOR_OUT based on the reference current signal REF_CUR. Here, the reference current may correspond to a current flowing through the transistor N0″ when the transistor N0″ is turned on according to the reference current signal REF_CUR.

For example, the PBDEC213may include an input/output driver, a WOR latch, and an MBC current branch. The input/output driver may control input/output signals for cache latches respectively included in the first to eighth cache units CU0to CU7. The WOR latch may store column repair information. For example, the column repair information may be column repair information corresponding to the first page buffer circuit PGBUFa. The MBC current branch may provide a value corresponding to the number of pieces of latch data (logic high or logic low) of each page buffer unit to an MBC (e.g.,214ofFIG.1), and thus the MBC214may perform digital-to-analog conversion.

FIG.13is a circuit diagram showing the page buffer circuit PGBUF according to an embodiment. Referring toFIG.13, the page buffer circuit PGBUF may correspond to one of the first to fourth page buffer circuits PGBUFa to PGBUFd ofFIG.9. The page buffer circuit PGBUF may include the first to eighth page buffer units PBU0to PBU7and the first to eighth cache units CU0to CU7. The fifth to eighth cache units CU4to CU7may be disposed in the third area AR3ofFIG.10, and the fifth to eighth page buffer units PBU4to PBU7may be disposed in the fourth area AR4ofFIG.10. The descriptions of the first to fourth page buffer units PBU0to PBU3and the first to fourth cache units CU0to CU3given above with reference toFIGS.11and12may also be applied to the fifth to eighth page buffer units PBU4to PBU7and the fifth to eighth cache units CU4to CU7, and thus redundant descriptions will be omitted.

The fifth page buffer unit PBU4may include a fifth sensing node SO4and first and second pass transistors TR4and TR4′ connected in series, the sixth page buffer unit PBU5may include a sixth sensing node SO5and first and second pass transistors TR5and TR5′ connected in series, a seventh page buffer unit PBU6may include a seventh sensing node SO6and first and second pass transistors TR6and TR6′ connected in series, an eighth page buffer unit PBU7may include an eighth sensing node SO7and first and second pass transistors TR7and TR7′ connected in series, and a pass control signal SO_PASS[7:4] may be applied to gates of first pass transistors TR4to TR7and second pass transistors TR4′ to TR7′.

A fifth cache unit CU4may include a monitor transistor NM7e, a sixth cache unit CU5may include a monitor transistor NM7f, a seventh cache unit CU6may include a monitor transistor NM7g, and an eighth cache unit CU7may include a monitor transistor NM7h. Sources of monitor transistors NM7eto NM7hmay be connected to the second combined sensing node SOC1′, and a cache monitoring signal MON_C[7:4] may be applied to gates of the monitor transistors NM7eto NM7h.

FIG.14is a circuit diagram showing the cache unit CU according to an embodiment.

Referring toFIGS.6and14together, the cache unit CU may include a monitor transistor NM7and the cache latch CL, and the cache latch CL may include a dump transistor132, transistors131and133to135, a first inverter136, and a second inverter137. The monitor transistor NM7is driven according to a cache monitoring signal MON_C and may control the connection between the combined sensing node SOC and the cache latch CL. The cache unit CU may correspond to one of the first to eighth cache units CU0to CU7ofFIG.9.

The first inverter136is connected between a first node ND1and a second node ND2, the second inverter137is connected between the second node ND2and the first node ND1, and the first inverter136and the second inverter137may constitute a latch. A transistor131includes a gate connected to the combined sensing node SOC. The dump transistor132may be driven by a dump signal DUMP_C and may transmit data stored in the cache latch CL to a main latch in the page buffer unit PBU, e.g., the sensing latch SL. A transistor133may be driven by a data signal DI, a transistor134may be driven by a data inversion signal nDI, and a transistor135may be driven by a write control signal DIO_W. When the write control signal DIO_W is activated, voltage levels of the first node ND1and the second node ND2may be determined according to the data signal DI and the data inversion signal nDI, respectively.

The cache unit CU may be connected to an input/output terminal RDi through transistors138and139. A transistor138includes a gate connected to the second node ND2and may be turned on or turned off according to a voltage level of the second node ND2. A transistor139may be driven by a read control signal DIO_R. When the control signal DIO_R is activated and the transistor139is turned on, the voltage level of the input/output terminal RDi may be determined as ‘1’ or ‘0’ according to the state of the cache latch CL.

FIG.15is a timing diagram showing an example of a data transmission operation according to an embodiment. Referring toFIGS.12,13, and15together, pass control signals SO_PASS0to SO_PASS3(i.e., SO_PASS[3:0]) may be applied to pass transistors TR0to TR3and TR0′ to TR3′ included in the first to fourth page buffer units PBU0to PBU3, respectively, and pass control signals SO_PASS4to SO_PASS7(i.e., SO_PASS[7:4]) may be applied to pass transistors TR4to TR7and TR4′ to TR7′ included in the fifth to eighth page buffer units PBU4to PBU7, respectively.

The core operation sequence may include a data transmission period161in which a data dumping operation is performed. When the page buffer circuit PGBUF has a multi-stage structure, the data transmission period161may be divided into the number of data transmission periods corresponding to half of the total number of stages. For example, when the page buffer circuit PGBUF has an 8-stage structure, the data transmission period161may be divided into four data transmission periods, e.g., first to fourth data transmission periods1611to1614. First data transmission operations between upper page buffer units and upper cache units and second data transmission operations between lower page buffer units and lower cache units may be simultaneously performed. Here, the first data transmission operations may be sequentially performed, and the second data transmission operations may also be sequentially performed. Specifically, in each of the first to fourth data transmission periods1611to1614, a data transmission operation between an upper page buffer unit and a upper cache unit corresponding thereto and a data transmission between a lower page buffer unit and a lower cache unit corresponding thereto may be performed simultaneously.

In a data transmission section161, the first pass transistors TR0to TR3and the second pass transistors TR0′ to TR3′ respectively included in the first to fourth page buffer units PBU0to PBU3may be selectively turned on to individually control connections between the first to fourth page buffer units PBU0to PBU3and the first to fourth cache units CU0to CU3. Also, in the data transmission section161, the first pass transistors TR4to TR7and the second pass transistors TR4′ to TR7′ respectively included in the fifth to eighth page buffer units PBU4to PBU7may be selectively turned on to individually control connections between the fifth to eighth page buffer units PBU4to PBU7and the fifth to eighth cache units CU4to CU7. Therefore, an amount of a current consumed in for a data dumping operation may be reduced.

In detail, in the first data transmission period1611, all of first to eighth pass control signals SO_PASS0to SO_PASS7may be activated, and thus all of the first pass transistors TR0to TR3and the second pass transistors TR0′ to TR3′ respectively included in the first to fourth page buffer units PBU0to PBU3may be turned on and connected in series, and all of the first pass transistors TR4to TR7and the second pass transistors TR4′ to TR7′ respectively included in the fifth to eighth page buffer units PBU4to PBU7may be turned on and connected in series. Here, the first sensing node SO0may be connected to the first combined sensing node SOC1through second to fourth sensing nodes SO1to SO3, and the eighth sensing node SO7may be connected to the second combined sensing node SOC1′ through fifth to seventh sensing nodes SO4to SO6.

At the start of the first data transmission period1611, load signals LOAD0to LOAD7may transition to logic low, which is an enable level, all of pre-charge transistors PM0to PM7respectively included in the first to eighth page buffer units PBU0to PBU7may be turned on, and first to eighth sensing nodes SO0to SO7may be pre-charged to a pre-charge level. Also, at the start of the first data transmission period1611, the combined sensing node load signal SOC_LOAD may transition to logic low, which is an enable level, the pre-charge transistor PMa included in a pre-charge circuit SOC_PRE1may be turned on, and the first combined sensing node SOC1may be pre-charged to a pre-charge level. Similarly, the second combined sensing node SOC1′ may also be pre-charged to a pre-charge level.

Subsequently, the load signals LOAD0to LOAD7and the combined sensing node load signal SOC_LOAD transition to logic high, and ground control signals SOGND0and SOGND7, which are respectively applied to first and eighth page buffer units PBU0and PBU7, may transition to logic high, which is an enable level. Here, the first sensing node SO0and a sensing latch included in the first page buffer unit PBU0may be electrically connected, and the eighth sensing node SO7and a sensing latch included in the eighth page buffer unit PBU7may be electrically connected.

Subsequently, the ground control signals SOGND0and SOGND7respectively applied to the first page buffer unit PBU0and the eighth page buffer unit PBU7transition to logic low, and dump signals DUMP_C0and DUMP_C7respective applied to the first cache unit CU0and the eighth cache unit CU7may transition to logic high, which is an enable level. Here, data may be dumped between the sensing latch included in the first page buffer unit PBU0and the first cache unit CU0, and at the same time, data may be dumped between the sensing latch included in the eighth page buffer unit PBU7and the eighth cache unit CU7. The above descriptions of the first data transmission period1611may also be applied to second to fourth data transmission periods1612to1614.

In a second data transmission section1612, the first pass control signal SO_PASS0and an eighth pass control signal SO_PASS7may be deactivated and second to seventh pass control signals SO_PASS1to SO_PASS6may be activated, and thus all of first pass transistors TR1to TR3and second pass transistors TR1to TR3′ included in second to fourth page buffer units PBU1to PBU3may be turned on and connected in series, and all of first pass transistors TR4to TR6and second pass transistors TR4′ to TR6′ included in fifth to seventh page buffer units PBU4to PBU6may be turned on and connected in series. Here, the second sensing node SO1may be connected to the first combined sensing node SOC1through the third sensing node SO2and the fourth sensing node SO3, and data dumping may be performed between the main latch in the second page buffer unit PBU1and a cache latch in a second cache unit CU1. Here, the seventh sensing node SO6may be connected to the second combined sensing node SOC1′ through the fifth sensing node SO4and the sixth sensing node SO5, and data dumping may be performed between the main latch in the seventh page buffer unit PBU6and a cache latch in the seventh cache unit CU6. Here, since first and second pass transistors TR0, TR0′, TR7, and TR7′ included in the first page buffer unit PBU0and the eighth page buffer unit PBU7are turned off, current consumption may be reduced.

In a third data transmission section1613, first, second, seventh, and eighth pass control signals SO_PASS0, SO_PASS1, SO_PASS6, and SO_PASS7may be deactivated and third to sixth pass control signals SO_PASS2to SO_PASS5may be activated, and thus all of first and second pass transistors TR2, TR3, TR2′, and TR3′ included in the third page buffer unit PBU2and the fourth page buffer unit PBU3may be turned on and connected in series, and all of first and second pass transistors TR4, TR5, TR4′, and TR5′ included in the fifth page buffer unit PBU4and the sixth page buffer unit PBU5may be turned on and connected in series. Here, the third sensing node SO2may be connected to the first combined sensing node SOC1through the fourth sensing node SO3, and data dumping may be performed between the main latch in the third page buffer unit PBU2and a cache latch in a third cache unit CU2. Also, the sixth sensing node SO5may be connected to the second combined sensing node SOC1′ through the fifth sensing node SO4, and data dumping may be performed between the main latch in the sixth page buffer unit PBU5and a cache latch in a sixth cache unit CU5. Here, since first and second pass transistors TR0, TR0′, TR1, TR1′, TR6, TR6′, TR7, and TR7′ included in first, second, seventh, and eighth page buffer units PBU0, PBU1, PBU6, and PBU7are turned off, current consumption may be reduced.

In a fourth data transmission section1614, first to third and sixth to eighth pass control signals SO_PASS0to SO_PASS2and SO_PASS5to SO_PASS7may be deactivated and fourth and fifth pass control signals SO_PASS3, SO_PASS4may be activated, and thus the first pass transistor TR3and the second pass transistor TR3′ included in the fourth page buffer unit PBU3may be turned on and connected in series, and a first pass transistor TR4and a second pass transistor TR4′ included in the fifth page buffer unit PBU4may be turned on and connected in series. In this case, the fourth sensing node SO3is connected to the first combined sensing node SOC1, and data dumping may be performed between the main latch in the fourth page buffer unit PBU3and the cache latch in a fourth cache unit CU3. Also, the fifth sensing node SO4is connected to the second combined sensing node SOC1′, and data dumping may be performed between the main latch in the fifth page buffer unit PBU4and the cache latch in the fifth cache unit CU4. Here, since first and second pass transistors TR0to TR2, TR5to TR7, TR0′ to TR2′, and TR5′ to TR7′ included in first to third and sixth to eighth page buffer units PBU0to PBU2and PBU5to PBU7are turned off, current consumption may be reduced.

Meanwhile, in a data sensing period in which a data sensing operation is performed in the core operation sequence, all of the first to eighth pass control signals SO_PASS0to SO_PASS7may be deactivated, and all the pass transistors TR0to TR7and TR0′ to TR7′ included in the first to eighth page buffer units PBU0to PBU7may be turned off. Therefore, the first to eighth page buffer units PBU0to PBU7may not be electrically connected to one another, and the first to eighth sensing nodes SO0to SO7may be insulated from one another. Here, the first to fourth sensing nodes SO0to SO3may not be electrically connected to the first combined sensing node SOC1, and the first to fourth page buffer units PBU0to PBU3may not be connected to the first to fourth cache units CU0to CU3. Here, fifth to eighth sensing nodes SO4to SO7may not be electrically connected to the second combined sensing node SOC1′, and the fifth to eighth page buffer units PBU4to PBU7may not be electrically connected to the fifth to eighth cache units CU4to CU7.

FIG.16is a timing diagram showing an example of a pass/fail determination operation according to an embodiment.

Referring toFIGS.13and16together, the core operation sequence may include a pass/fail determination period171in which a pass/fail determination operation is performed on data. For example, the pass/fail determination period171may be performed after the data transmission period161ofFIG.15. When the page buffer circuit PGBUF has a multi-stage structure, the pass/fail determination period171may be divided into pass/fail determination periods corresponding to respective stages. For example, when the page buffer circuit PGBUF has an 8-stage structure, the pass/fail determination period171may be divided into eight pass/fail determination periods, e.g., first to eighth pass/fail determination periods1711to1718.

According to an embodiment, first pass/fail determination operations respectively corresponding to upper page buffer units may be sequentially performed, and then second pass/fail determination operations respectively corresponding to lower page buffer units may be sequentially performed. For example, first to fourth pass/fail determination periods1711to1714may correspond to a first period, and in the first period, first pass/fail determination operations for upper page buffer units may be sequentially performed. For example, fifth to eighth pass/fail determination periods1715to1718may correspond to a second period, and in the second period, second pass/fail determination operations for lower page buffer units may be sequentially performed.

In detail, in a first pass/fail determination section1711, first to fourth pass control signals SO_PASS0to SO_PASS3may be activated, and fifth to eighth pass control signals SO_PASS4to SO_PASS7may be deactivated, and thus the first pass transistors TR0to TR3and the second pass transistors TR0′ to TR3′ included in the first to fourth page buffer units PBU0to PBU3may be turned on and connected in series, and the first pass transistors TR4to TR7and the second pass transistors TR4′ to TR7′ included in the fifth to eighth page buffer units PBU4to PBU7may be turned off. Here, the first sensing node SO0is connected to the first combined sensing node SOC1through the second to fourth sensing nodes SO1to SO3, and a pass/fail determination operation regarding data stored in the sensing latch in the first page buffer unit PBU0may be performed.

At the start of the first pass/fail determination period1711, load signals LOAD0to LOAD3may transition to logic low, which is an enable level, all of pre-charge transistors PM0to PM3respectively included in the first to fourth page buffer units PBU0to PBU3may be turned on, and the first to fourth sensing nodes SO0to SO3may be pre-charged to a pre-charge level. Also, at the start of the first pass/fail determination period1711, the combined sensing node load signal SOC_LOAD may transition to logic low, which is an enable level, the pre-charge transistor PMa included in the pre-charge circuit SOC_PRE1may be turned on, and the first combined sensing node SOC1may be pre-charged to a pre-charge level. Subsequently, the load signals LOAD0to LOAD3and the combined sensing node load signal SOC_LOAD transition to logic high, and a ground control signal SOGND0, which is applied to the first page buffer unit PBU0, may transition to logic high, which is an enable level. At this time, the first sensing node SO0and the sensing latch included in the first page buffer unit PBU0may be electrically connected. The above descriptions of the first pass/fail determination period1711may also be applied to second to eighth pass/fail determination periods1712to1718.

In a second pass/fail determination section1712, second to fourth pass control signals SO_PASS1to SO_PASS3may be activated, and first and fifth to eighth pass control signals SO_PASS0and SO_PASS4to SO_PASS7may be deactivated, and thus first pass transistors TR1to TR3and the second pass transistors TR1′ to TR3′ included in the second to fourth page buffer units PBU1to PBU3may be turned on and connected in series, and the first pass transistors TR0and TR4to TR7and the second pass transistors TR0′ and TR4′ to TR7′ included in the first and fifth to eighth page buffer units PBU0and PBU4to PBU7may be turned off. Here, the second sensing node SO1is connected to the first combined sensing node SOC1through the third and fourth sensing nodes SO2and SO3, and a pass/fail determination operation regarding data stored in the sensing latch in the second page buffer unit PBU1may be performed.

In a third pass/fail determination section1713, third and fourth pass control signals SO_PASS2and SO_PASS3may be activated, and first, second, and fifth to eighth pass control signals SO_PASS0, SO_PASS1, and SO_PASS4to SO_PASS7may be deactivated, and thus first pass transistors TR2and TR3and the second pass transistors TR2′ and TR3′ included in the third and fourth page buffer units PBU2to PBU3may be turned on and connected in series, and the first pass transistors TR0, TR1, and TR4to TR7and the second pass transistors TR0′, TR1′, and TR4′ to TR7′ included in the first, second, and fifth to eighth page buffer units PBU0, PBU1, and PBU4to PBU7may be turned off. Here, the third sensing node SO2is connected to the first combined sensing node SOC1through the fourth sensing node SO3, and a pass/fail determination operation regarding data stored in the sensing latch in the third page buffer unit PBU2may be performed.

In a fourth pass/fail determination section1714, a fourth pass control signal SO_PASS3may be activated, and first to third and fifth to eighth pass control signals SO_PASS0to SO_PASS2and SO_PASS4to SO_PASS7may be deactivated, and thus the first pass transistor TR3and the second pass transistor TR3′ included in the fourth page buffer unit PBU3may be turned on and connected in series, and first pass transistors TR0to TR2and TR4to TR7and second pass transistors TR0′ to TR2′ and TR4′ to TR7′ included in the first to third and fifth to eighth page buffer units PBU0to PBU2and PBU4to PBU7may be turned off. Here, the fourth sensing node SO3is connected to the first combined sensing node SOC1, and a pass/fail determination operation regarding data stored in the sensing latch in the fourth page buffer unit PBU3may be performed.

In a fifth pass/fail determination period1715, the first to fourth pass control signals SO_PASS0to SO_PASS3may be deactivated and the fifth to eighth pass control signals SO_PASS4to SO_PASS7may be activated, and thus a pass/fail determination operation regarding data stored in the sensing latch in the eighth page buffer unit PBU7may be performed. In a sixth pass/fail determination period1716, first to fourth and eighth pass control signals SO_PASS0to SO_PASS4and SO_PASS7may be deactivated and fifth to seventh pass control signals SO_PASS4to SO_PASS6may be activated, and thus a pass/fail determination operation regarding data stored in the sensing latch in the seventh page buffer unit PBU6may be performed.

In a seventh pass/fail determination period1717, first to fourth, seventh, and eighth pass control signals SO_PASS0to SO_PASS3, SO_PASS6, and SO_PASS7may be deactivated and fifth and sixth pass control signals SO_PASS4and SO_PASS5may be activated, and thus a pass/fail determination operation regarding data stored in the sensing latch in the sixth page buffer unit PBU5may be performed. In an eighth pass/fail determination period1718, first to fourth and sixth to eighth pass control signals SO_PASS0to SO_PASS3and SO_PASS5to SO_PASS7may be deactivated and a fifth pass control signal SO_PASS4may be activated, and thus a pass/fail determination operation regarding data stored in the sensing latch in the fifth page buffer unit PBU4may be performed.

FIG.17is a diagram showing a page buffer circuit210aand a PBDEC213aaccording to an embodiment. The present embodiment corresponds to an modified example ofFIG.10, and the descriptions given above with reference toFIG.10may also be applied to the present embodiment.

Referring toFIG.17, the PBDEC213amay include first to fourth PBDECs PBDECa′ to PBDECd′, and the first to fourth PBDECs PBDECa′ to PBDECd′ may be arranged to correspond to first page buffer units PBU0of first to fourth page buffer circuits PGBUFa′ to PGBUFd′, respectively. An input/output driver213bmay be disposed at the center of the page buffer circuit210a, and more particularly, between the fourth cache unit CU3and the fifth cache unit CU4of each of the first to fourth page buffer circuits PGBUFa′ to PGBUFd′. The input/output driver213bmay control input/output signals for cache latches included in the first to eighth cache units CU0to CU7.

For example, the input/output driver213bmay include transistors NM_DIVa to NM_DIVd driven by a segmentation control signal or a division control signal DIV_SOC. When the division control signal DIV_SOC is at a logic high level, the transistors NM_DIVa to NM_DIVd may be turned on, and thus the fifth to eighth cache units CU4to CU7and the fifth to eighth page buffer units PBU4to PBU7may be connected to the PBDEC213atogether with the first to fourth page buffer units PBU0to PBU3and the first to fourth cache units CU0to CU3. Meanwhile, when the division control signal DIV_SOC is at a logic low level, the transistors NM_DIVa to NM_DIVd may be turned off, and thus the fifth to eighth cache units CU4to CU7and the fifth to eighth page buffer units PBU4to PBU7may not be connected to the PBDEC213a.

A first PBDEC PBDECa′ may be connected to the first combined sensing node SOC1and/or the second combined sensing node SOC1′ through an upper combined sensing node SOC_T1. A second PBDEC PBDECb′ may be connected to the first combined sensing node SOC2and/or the second combined sensing node SOC2′ through an upper combined sensing node SOC_T2. A third PBDEC PBDECc′ may be connected to the first combined sensing node SOC3and/or the second combined sensing node SOC3′ through an upper combined sensing node SOC_T3. A fourth PBDEC PBDECd′ may be connected to the first combined sensing node SOC4and/or the second combined sensing node SOC4′ through an upper combined sensing node SOC_T4.

FIG.18is a diagram showing the page buffer circuit210aand the PBDEC213aaccording to an embodiment in more details. The present embodiment corresponds to a modified example ofFIGS.11and17, and redundant descriptions will be omitted. Referring toFIG.18, transistors PM_WORa to PM_WORd driven by a load WOR control signal LOAD_WOR may be arranged between the PBDEC213aand the page buffer circuit210a. When the load WOR control signal LOAD_WOR is at a logic low level, the transistors PM_WORa to PM_WORd may be turned on, and the page buffer circuit210aand the PBDEC213amay be connected. On the other hand, when the load WOR control signal LOAD_WOR is at a logic high level, the transistors PM_WORa to PM_WORd may be turned off, and the page buffer circuit210aand the PBDEC213amay not be connected.

FIG.19is a circuit diagram showing a partial region of the page buffer circuit PGBUFa′ and the PBDEC PBDECa′ according to an embodiment.

Referring toFIG.19, the PBDEC PBDECa′ may include an MBC current branch191and a WOR latch192. The WOR latch192may store column repair information. Here, the column repair information may be column repair information corresponding to the first page buffer circuit PGBUFa′. The MBC current branch191may provide a value corresponding to the number of pieces of latch data (logic high or logic low) of each page buffer unit to the MBC214, and thus the MBC214may perform digital-to-analog conversion.

The MBC current branch191may include transistors TR1, TR2, and TR3connected in series and an inverter IV0, and an input terminal of the inverter IV0may be connected to the upper combined sensing node SOC_T1. The WOR latch192may include inverters IV1and IV2and transistors TR4, TR5and TR6, wherein the inverters IV1and IV2may constitute a latch. A gate of a transistor TR1may be connected to the MBC214and may receive a control signal from the MBC214. A gate of the transistor TR2may be connected to an input terminal of the inverter IV1and an output terminal of the inverter IV2. Gates of transistors TR4and TR5may be connected to a Y driver216and each receive a control signal from the Y driver216. A gate of a transistor TR6may be connected to the upper combined sensing node SOC_T1.

FIG.20is a circuit diagram showing a partial region of the page buffer circuit210aand the PBDEC213aaccording to an embodiment. Referring toFIG.20, the MBC current branch191may include current branches CB0to CB3, and the current branches CB0to CB3may be connected to the MBC214. The WOR latch192may include latches LAT0to LAT3, and the latches LAT0to LAT3may transmit latch information W_LAT0to W_LAT3to the current branches CB0to CB3, respectively. WOR latch information may be updated in one (e.g., CU3) of the first to fourth cache units CU0to CU3through the input/output driver213b, and WOR latch information may be transmitted to a WOR latch (e.g., LAT0) through the first combined sensing node SOC1.

FIG.21is a timing diagram showing an example of a data transmission operation according to an embodiment. The present embodiment corresponds to a modified example ofFIG.15, and redundant descriptions will be omitted. Referring toFIGS.17to21, the core operation sequence may include a data transmission period211in which a data dumping operation is performed. The data transmission period211may include first to fourth data transmission periods2111to2114. The first to fourth data transmission periods2111to2114may correspond to the first to fourth data transmission periods1611to1614ofFIG.15, respectively. In the first to fourth data transmission periods2111to2114, the division control signal DIV_SOC may maintain a logic low level, and thus all of the transistors NM_DIVa to NM_DIVd may be turned off. In the first to fourth data transmission periods2111to2114, a WOR control signal LOAD_WOR may maintain a logic high level, and thus all of transistors NM_WORa to NM_WORd may be turned off.

FIG.22is a timing diagram showing an example of a pass/fail determination operation according to an embodiment. The present embodiment corresponds to a modified example ofFIG.16, and redundant descriptions will be omitted. Referring toFIGS.17to20and22together, the core operation sequence may include a pass/fail determination period221in which a pass/fail determination operation is performed on data. For example, the pass/fail determination period2211may be performed after the data transmission period211ofFIG.21. The pass/fail determination period221may include first to eighth pass/fail determination periods2211to2218. The first to eighth pass/fail determination periods2211to2218may correspond to the first to eighth pass/fail determination periods1711to1718ofFIG.16, respectively.

In the first to fourth pass/fail determination periods2211to2214, the division control signal DIV_SOC may maintain a logic low level, and thus all of the transistors NM_DIVa to NM_DIVd may be turned off. Meanwhile, in each of fifth to eighth pass/fail determination periods2215to2218, the division control signal DIV_SOC may be activated. For example, in a fifth pass/fail determination section2215, the division control signal DIV_SOC may transition to a logic high level when pass control signals SO_PASS<4> to SO_PASS<7> transition from a logic low level to a logic high level and may transition to the logic high level when a ground control signal SOGND<7> transitions from the logic high level to the logic low level. The transistors NM_DIVa to NM_DIVd are turned on while the division control signal DIV_SOC is maintaining the logic high level, and thus the fifth to eighth page buffer units PBU4to PBU7may be connected to the PBDEC213a, and a pass/fail determination operation corresponding to the eighth page buffer unit PBU7may be performed.

At the start of a first pass/fail determination period2211, the WOR control signal LOAD_WOR may transition to a logic low level, which is an enable level, and the transistors PM_WORa to PM_WORd may be turned on. At this time, the first combined sensing node SOC1and the upper combined sensing node SOC_T1may be electrically connected. Subsequently, the WOR control signal LOAD_WOR may transition to a logic high level, which is a disable level, and the transistors PM_WORa to PM_WORd may be turned off.

FIG.23is a circuit diagram showing a page buffer PB′ according to an embodiment. Referring toFIG.23, the page buffer PB′ may include a page buffer unit PBU′ and the cache unit CU, and the page buffer unit PBU′ may include a main unit MU′ and the high-voltage unit HVU. The page buffer PB′ may correspond to a modified example of the page buffer PB ofFIG.6. The page buffer unit PBU ofFIG.6includes first and second pass transistors TR and TR′, whereas the page buffer unit PBU′ according to the present embodiment may include one pass transistor TR″. The pass transistor TR″ may be driven according to the pass control signal SO_PASS and may be connected between the first terminal SOC_U and the second terminal SOC_D.

For example, a source of the pass transistor TR″ may be connected to the first terminal SOC_U, and a drain of the pass transistor TR″ may be connected to the sensing node SO and the second terminal SOC_D. However, the inventive concept is not limited thereto, and the source of the pass transistor TR″ may be connected to the first terminal SOC_U and the sensing node SO, and the drain of the pass transistor TR″ may be connected to the second terminal SOC_D. According to an embodiment, a pass transistor included in one of two page buffer units adjacent to each other in the first direction HD1may be connected between the first terminal SOC_U and the sensing node SO, and a pass transistor included in the other one page buffer unit may be connected between the sensing node SO and the second terminal SOC_D.

FIG.24is a diagram showing the PBDEC213and the MBC214according to an embodiment. Referring toFIGS.1,9, and24together, the PBDEC213may include N PBDECs. Here, N is a positive integer and may correspond to the number of page buffer columns included in a page buffer circuit. Each PBDEC may include inverters IVT0and IVT1and transistors N0, N0′, N0″, and N1, and the transistor N0′ may be referred to as a column enable transistor. Descriptions given above with reference toFIGS.12and13may be applied to the present embodiment. The MBC214may be connected to the wired OR terminal WOR_OUT connected to the N PBDECs.

The MBC214may generate count results CNT (i.e., OUT<0> to OUT<9>), which are digital values corresponding to the number of fail bits, from the analog level decoder output signal DS, that is, a current signal IWOR. In detail, the MBC214may include a plurality of transistors P11, P12, P21, P22, P31, P32, N11, N12, N21, N22, and N23, a resistor R, and a differential amplifier2141constituting a reference current generator. Also, the MBC214may further include a plurality of transistors P1, P1a, P2, P2a, P9, P9a, N1, N1a, N2, N2a, N2b, N2c, N9, N9a, N9b, and N9cconstituting a counter and a plurality of comparators2142and2143. In a period in which the operation of the MBC214is enabled, the transistors P11, P21, P31, N12, N23, P1a, P2a, P9a, N1a, N2a, N2c, N9a, and N9cmay be turned on. On the other hand, in a period in which the operation of the MBC214is disabled, the transistors P11, P21, P31, N12, N23, P1a, P2a, P9a, N1a, N2a, N2c, N9a, and N9cmay be turned off.

A reference voltage Vref may be input to a first input terminal of the differential amplifier2141, and a voltage across the resistor R may be input to a second input terminal of the differential amplifier2141. Transistors P11and P12and the resistor R may constitute a feedback variable resistor, and a bias current Ibias may flow through the resistor R. Transistors P21, P22, N12, and N21may constitute a first reference current generator generating a first reference current Iref1, and transistors P31, P32, N21, N22, and N23may constitute a second reference current generator generating a second reference current Iref2. A node voltage between transistors P32and N21may be provided from the second reference current generator to the PBDEC213as the reference current signal REF_CUR.

FIG.25is a cross-sectional view of a memory device500having a bonding vertical NAND (B-VNAND) structure, according to an embodiment. When a non-volatile memory included in a memory device is implemented as a bonding vertical NAND (B-VNAND) type flash memory, the non-volatile memory may have the structure shown inFIG.25.

Referring toFIG.25, a cell region CELL of a memory device500may correspond to a first semiconductor layer L1, and a peripheral circuit region PERI may correspond to a second semiconductor layer L2. The peripheral circuit region PERI and the cell region CELL of the memory device500may each include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA. For example, the word lines WL, the string select lines SSL, the ground select lines GSL, and the memory cell array110ofFIG.2may be formed on the first semiconductor layer L1, whereas the control logic circuit120, the page buffer circuit130, the voltage generator140, and the row decoder150may be formed on the second semiconductor layer L2.

The peripheral circuit region PERI may include a first substrate610, an interlayer insulating layer615, a plurality of circuit elements620a,620b, and620cformed on the first substrate610, first metal layers630a,630b, and630crespectively connected to the plurality of circuit elements620a,620b, and620c, and second metal layers640a,640b, and640cformed on the first metal layers630a,630b, and630c. In an embodiment, the first metal layers630a,630b, and630cmay be formed of tungsten having relatively high resistivity, and the second metal layers640a,640b, and640cmay be formed of copper having relatively low resistivity.

In an embodiment, although only the first metal layers630a,630b, and630cand the second metal layers640a,640b, and640care shown and described, the embodiment is not limited thereto, and one or more additional metal layers may be further formed on the second metal layers640a,640b, and640c. At least a portion of the one or more additional metal layers formed on the second metal layers640a,640b, and640cmay be formed of aluminum or the like having a lower resistivity than those of copper forming the second metal layers640a,640b, and640c.

The interlayer insulating layer615may be disposed on the first substrate610and cover the plurality of circuit elements620a,620b, and620c, the first metal layers630a,630b, and630c, and the second metal layers640a,640b, and640c. The interlayer insulating layer615may include or be formed of an insulating material such as silicon oxide, silicon nitride, or the like.

Lower bonding metals671band672bmay be formed on the second metal layer640bin the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals671band672bin the peripheral circuit region PERI may be electrically bonded to upper bonding metals571band572bof the cell region CELL. The lower bonding metals671band672band the upper bonding metals571band572bmay be formed of aluminum, copper, tungsten, or the like. Further, the upper bonding metals571band572bin the cell region CELL may be referred as first metal pads and the lower bonding metals671band672bin the peripheral circuit region PERI may be referred as second metal pads.

The cell region CELL may include at least one memory block. The cell region CELL may include a second substrate510and a common source line520. On the second substrate510, a plurality of word lines531to538(i.e.,530) may be stacked in a vertical direction VD, perpendicular to an upper surface of the second substrate510. At least one string select line and at least one ground select line may be arranged on and below the plurality of word lines530, respectively, and the plurality of word lines530may be disposed between the at least one string select line and the at least one ground select line.

In the bit line bonding area BLBA, a channel structure CH may extend in the vertical direction VD, perpendicular to the upper surface of the second substrate510, and pass through the plurality of word lines530, the at least one string select line, and the at least one ground select line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, and the like, and the channel layer may be electrically connected to a first metal layer550cand a second metal layer560c. For example, the first metal layer550cmay be a bit line contact, and the second metal layer560cmay be a bit line. In an embodiment, the bit line560cmay extend in a second horizontal direction HD2, parallel to the upper surface of the second substrate510.

In an embodiment, an area in which the channel structure CH, the bit line560c, and the like are disposed may be defined as the bit line bonding area BLBA. In the bit line bonding area BLBA, the bit line560cmay be electrically connected to the circuit elements620cproviding a page buffer593in the peripheral circuit region PERI. The bit line560cmay be connected to upper bonding metals571cand572cin the cell region CELL, and the upper bonding metals571cand572cmay be connected to lower bonding metals671cand672cconnected to the circuit elements620cof the page buffer593.

In the word line bonding area WLBA, the plurality of word lines530may extend in a first horizontal direction HD1, parallel to the upper surface of the second substrate510, and may be connected to a plurality of cell contact plugs541to547(i.e.,540). The plurality of word lines530and the plurality of cell contact plugs540may be connected to each other in pads provided by at least a portion of the plurality of word lines530extending in different lengths in the second horizontal direction HD2. A first metal layer550band a second metal layer560bmay be connected to an upper portion of the plurality of cell contact plugs540connected to the plurality of word lines530, sequentially. The plurality of cell contact plugs540may be connected to the peripheral circuit region PERI by the upper bonding metals571band572bof the cell region CELL and the lower bonding metals671band672bof the peripheral circuit region PERI in the word line bonding area WLBA.

The plurality of cell contact plugs540may be electrically connected to the circuit elements620bproviding a row decoder594in the peripheral circuit region PERI. In an embodiment, operating voltages of the circuit elements620bof the row decoder594may be different from operating voltages of the circuit elements620cproviding the page buffer593. For example, operating voltages of the circuit elements620cproviding the page buffer593may be greater than operating voltages of the circuit elements620bproviding the row decoder594.

A common source line contact plug580may be disposed in the external pad bonding area PA. The common source line contact plug580may be formed of a conductive material such as a metal, a metal compound, polysilicon, or the like, and may be electrically connected to the common source line520. A first metal layer550aand a second metal layer560amay be stacked on an upper portion of the common source line contact plug580, sequentially. For example, an area in which the common source line contact plug580, the first metal layer550a, and the second metal layer560aare disposed may be defined as the external pad bonding area PA.

Input-output pads605and505may be disposed in the external pad bonding area PA. A lower insulating film601covering a lower surface of the first substrate610may be formed below the first substrate610, and a first input-output pad605may be formed on the lower insulating film601. The first input-output pad605may be connected to at least one of the plurality of circuit elements620a,620b, and620cdisposed in the peripheral circuit region PERI through a first input-output contact plug603, and may be separated from the first substrate610by the lower insulating film601. In addition, a side insulating film may be disposed between the first input-output contact plug603and the first substrate610to electrically separate the first input-output contact plug603and the first substrate610.

An upper insulating film501covering the upper surface of the second substrate510may be formed on the second substrate510, and a second input-output pad505may be disposed on the upper insulating layer501. The second input-output pad505may be connected to at least one of the plurality of circuit elements620a,620b, and620cdisposed in the peripheral circuit region PERI through a second input-output contact plug503.

According to embodiments, the second substrate510and the common source line520may not be disposed in an area in which the second input-output contact plug503is disposed. Also, the second input-output pad505may not overlap the word lines530in the vertical direction VD. The second input-output contact plug503may be separated from the second substrate510in a direction, parallel to the upper surface of the second substrate510, and may pass through an interlayer insulating layer of the cell region CELL to be connected to the second input-output pad505.

According to embodiments, the first input-output pad605and the second input-output pad505may be selectively formed. For example, the memory device400may include only the first input-output pad605disposed on the first substrate610or the second input-output pad505disposed on the second substrate510. Alternatively, the memory device400may include both the first input-output pad605and the second input-output pad505.

A metal pattern provided on an uppermost metal layer may be provided as a dummy pattern or the uppermost metal layer may be absent, in each of the external pad bonding area PA and the bit line bonding area BLBA, respectively included in the cell region CELL and the peripheral circuit region PERI.

In the external pad bonding area PA, the memory device500may include a lower metal pattern673a, corresponding to an upper metal pattern572aformed in an uppermost metal layer of the cell region CELL, and having the same cross-sectional shape as the upper metal pattern572aof the cell region CELL so as to be connected to each other, in an uppermost metal layer of the peripheral circuit region PERI. In the peripheral circuit region PERI, the lower metal pattern673aformed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a contact. Similarly, in the external pad bonding area PA, an upper metal pattern, corresponding to the lower metal pattern formed in an uppermost metal layer of the peripheral circuit region PERI, and having the same shape as a lower metal pattern of the peripheral circuit region PERI, may be formed in an uppermost metal layer of the cell region CELL.

The lower bonding metals671band672bmay be formed on the second metal layer640bin the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals671band672bof the peripheral circuit region PERI may be electrically connected to the upper bonding metals571band572bof the cell region CELL by a Cu-to-Cu bonding.

Further, in the bit line bonding area BLBA, an upper metal pattern592, corresponding to a lower metal pattern652formed in the uppermost metal layer of the peripheral circuit region PERI, and having the same cross-sectional shape as the lower metal pattern652, may be formed in an uppermost metal layer of the cell region CELL. A contact may not be formed on the upper metal pattern592formed in the uppermost metal layer of the cell region CELL.

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.