Patent ID: 12249649

DETAILED DESCRIPTION

Referring toFIG.1-2,FIG.1illustrate a top-view of a semiconductor device according to an embodiment of the present invention andFIG.2illustrates a cross-sectional view ofFIG.1along the sectional line AA′. As shown inFIGS.1-2, a substrate12, such as a silicon substrate or silicon-on-insulator (SOI) substrate is provided, and at least a fin-shaped structure, such as fin-shaped structures14,16are formed on the substrate12, in which the bottom portion of the fin-shaped structures14,16are surrounded by an insulation material to form isolation structures20,22.

According to an embodiment of the present invention, the fin-shaped structures14,16are preferably fabricated by a sidewall pattern transfer (SIT) technique, the procedures of which generally include first inputting a layout pattern into a computer system and modifying the layout pattern through suitable calculations. The modified layout is then defined in a mask and further transferred to a layer of sacrificial layer on a substrate through a photolithographic and an etching process. In this way, several sacrificial layers distributed with a same spacing and of a same width are formed on a substrate. Each of the sacrificial layers may be stripe-shaped. Subsequently, a deposition process and an etching process are carried out such that spacers are formed on the sidewalls of the patterned sacrificial layers. Next, sacrificial layers can be removed completely by performing an etching process. Through the etching process, the pattern defined by the spacers can be transferred into the substrate underneath, and through additional fin cut processes, desirable pattern structures such as stripe patterned fin-shaped structures could be obtained.

Alternatively, the fin-shaped structures14,16could also obtained by first forming a patterned mask (not shown) on the substrate12, and through an etching process, the pattern of the patterned mask is transferred to the substrate12to form the fin-shaped structures. Moreover, the formation of the fin-shaped structures14could also be accomplished by first forming a patterned hard mask (not shown) on the substrate12and a semiconductor layer composed of silicon germanium is grown from the substrate12through exposed patterned hard mask via selective epitaxial growth process to form the corresponding fin-shaped structures14. These approaches for forming the fin-shaped structures14are all within the scope of the present invention.

Next, at least a MOS transistor24is formed on the fin structures14,16and gate structures26,28are formed on two sides of the MOS transistor24, in which the gate structure30of the MOS transistor24is preferably an active gate structure while the gate structure26,28disposed on two sides of the MOS transistor24are dummy gates. In this embodiment, the gate structures26,28and30could be fabricated by a gate first process, a high-k first approach from gate last process, or a high-k last approach from gate last process, in which each of the gate structures26,28and30could be a polysilicon gate or a metal gate depending on the demand of the process.

For instance, the gate structures are fabricated by a high-k last approach and a replacement metal gate (RMG) process in this embodiment, in which each of the gate structures26,28and30is preferably composed of an interfacial layer or a gate dielectric layer32, a U-shaped high-k dielectric layer34, a U-shaped work function metal layer36, and a low-resistance metal layer38. Preferably, a hard mask40made of silicon nitride is disposed atop each of the gate structures26,28,30. Since the process of using high-k last approach and RMG process to transform dummy gate into metal gate is well known to those skilled in the art, the details of which are not explained herein for the sake of brevity.

In this embodiment, the high-k dielectric layer34is preferably selected from dielectric materials having dielectric constant (k value) larger than4. For instance, the high-k dielectric layer48may be selected from hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalate (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT), barium strontium titanate (BaxSr1-xTiO3, BST) or a combination thereof.

In this embodiment, the work function metal layer36is formed for tuning the work function of the later formed metal gates to be appropriate in an NMOS or a PMOS. For an NMOS transistor, the work function metal layer36having a work function ranging between 3.9 eV and 4.3 eV may include titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or titanium aluminum carbide (TiAlC), but it is not limited thereto. For a PMOS transistor, the work function metal layer36having a work function ranging between 4.8 eV and 5.2 eV may include titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), but it is not limited thereto. An optional barrier layer (not shown) could be formed between the work function metal layer36and the low resistance metal layer38, in which the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN). Furthermore, the material of the low-resistance metal layer38may include copper (Cu), aluminum (Al), titanium aluminum (TiAl), tungsten (W), cobalt tungsten phosphide (CoWP) or any combination thereof.

It should be noted that as shown in the top view ofFIG.1, the fin-shaped structures14,16are preferably disposed extending along a first direction (such as X-direction), the gate structures26,28and30are preferably disposed extending along a second direction (such as Y-direction) that is orthogonal to the first direction, the isolation structure20directly under the gate structure28is also disposed extending along the second direction as the gate structure28, and the isolation structure22on the end portion of the fin-shaped structure14,16are disposed to surround the entire fin-shaped structures14,16

In this embodiment, the isolation structure20and the isolation structure22are preferably formed from different isolation fabrication processes. The formation of the isolation structure20could be accomplished by first forming a fin-shaped structure on the substrate12, conducting an etching process to divide the fin-shaped structure into two portions (such as the fin-shaped structures14and16), and then filling a dielectric material between the divided fin-shaped structures14,16to form a single diffusion break (SDB) structure42. The isolation structure22is essentially a shallow trench isolation (STI)44surrounding the fin-shaped structures14,16after the fin-shaped structures14,16are being divided.

It should be noted that the isolation structures20,22adjacent to two sides of the MOS transistor24could be fabricated from same material and/or different processes. For instance, the isolation structures20,22adjacent to two sides of MOS transistor24could include a combination of different materials and different depths or a combination of same material and different depths depending on the demand of the product to improve the flow of electric current when the device is turned on. As illustrated by the MOS transistor shown inFIG.2, the isolation structure20on the right side of the gate structure30and the isolation structure22on the left side of the gate structure30are preferably composed of different dielectric material, in which the isolation structure20is preferably composed of a dielectric material or even a material carrying tensile stress such as silicon nitride and the isolation structure22is preferably composed of silicon oxide.

Viewing from a more detailed perspective, a top surface of the SDB structure42composed of silicon nitride having tensile stress is preferably lower than the top surface of the fin-shaped structures14,16, and a top surface of the STI44composed of silicon oxide is preferably even with a top surface of the fin-shaped structures14,16. It is to be noted that even though a bottom surface of the SDB structure42is even with a bottom surface of the STI44in this embodiment, according to another embodiment of the present invention not only a top surface of the SDB structure42can be lower than a top surface of the STI44but also a bottom surface of the SDB structure42is lower than a bottom surface of the STI44. These variations are all within the scope of the present invention.

Moreover, the gate structure28disposed directly on top of the SDB structure42preferably spans over to stand on the two adjacent fin-shaped structures14,16at the same time while overlapping the SDB structure42entirely. The gate structure26on the left side on the other hand overlaps or stands on the STI44and the fin-shaped structure14at the same time, in which the bottom surface of the gate structure28on the SDB structure42is preferably extended into part of the fin-shaped structures14,16and lower than a top surface of the fin-shaped structures14,16while the bottom surface of the gate structure26on the left side is even with the top surface of the fin-shaped structures14,16.

As shown inFIG.2, at least one spacer46is disposed on the sidewalls of each of the gate structures26,28,30or gate electrodes and a source/drain region48is formed in the substructure12adjacent to two sides of the gate structure30. Preferably, silicides (not shown) could be formed on the surface of the source/drain region48, an interlayer dielectric (ILD) layer52is formed on the gate structures26,28,30, and multiple contact plugs54are formed in the ILD layer52to electrically connect the source/drain regions48.

In this embodiment, the spacer46can be a single spacer or a composite spacer, such as a spacer including but not limited to for example an offset spacer and a main spacer. Preferably, the offset spacer and the main spacer could include same material or different material while both the offset spacer and the main spacer can be made of material including but not limited to for example SiO2, SiN, SiON, SiCN, or combination thereof. The interlayer dielectric (ILD) layer52preferably includes silicon oxide and the contact plugs54can include a barrier layer including titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN) and a metal layer including tungsten (W), copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP) or any combination thereof.

Viewing from a more detailed perspective, the source/drain region48on the left side of the gate structure30includes an epitaxial layer56and the source/drain region48on the right side of the gate structure30includes another epitaxial layer58, in which the epitaxial layers56,58could include n-type or p-type dopants while the epitaxial layers56,58could also include different epitaxial materials. For instance, if the transistor being fabricated were to be a PMOS transistor, the epitaxial layers56,58preferably include silicon germanium (SiGe), but not limited thereto. If the transistor being fabricated were to be a NMOS transistor the epitaxial layers56,58preferably include silicon phosphorus (SiP), but not limited thereto.

It should be noted that the epitaxial layer56and the epitaxial layer58preferably include different sizes, in which the definition of “different sizes” could be interpreted by having different shapes, different diameters, or any other features or parameters that could be used to clearly distinguish between the epitaxial layers56,58visually. Preferably, the epitaxial layer56on the left side of the gate structure30or between the gate structures26,30include a circle or circular profile while the epitaxial layer58on the right side of the gate structure30or between the gate structures28,30includes an ellipse or elliptical profile, in which the diameter R1of the ellipse, or more specifically, the short axis through the center of the ellipse is preferably less than the diameter R2of the circle.

Since the diameter R1or the short axis of the elliptical epitaxial layer58on the right side of the gate structure30is preferably less than the diameter R2of the epitaxial layer56on the left side of the gate structure30, the distance between the gate structure28and the gate structure30, or more specifically, the distance D1measuring from the left sidewall of the gate electrode of the gate structure28to the right sidewall of the gate electrode of the gate structure30is preferably less than the distance between the gate structure26and the gate structure30or more specifically the distance D2measuring from the left sidewall of the gate electrode of the gate structure30to the right sidewall of the gate electrode of the gate structure26.

In addition, the three gate structure26,28,30in this embodiment could also include different combinations of the same widths and/or different widths depending on the demand of the product. For instance, as shown inFIG.2, the width W1of the middle gate structure30or gate electrode is preferably less than the width W2of the gate structure26on the left side while the width W2of the gate structure26is further less than the width W3of the gate structure28on the right side. Nevertheless, according to an embodiment of the present invention, the width W1of the middle gate structure30could be equal to the width W2of the gate structure26on the left while the width W2of the gate structure26is less than the width W3of the gate structure28on the right. In other words, the gate structure26and the gate structure30could be having same widths W1and W2while each of the widths W1and W2is less than the width W3of the gate structure28directly on the SDB structure42. These variations are all within the scope of the present invention.

Referring toFIG.3,FIG.3illustrates a structural view of a semiconductor device according to an embodiment of the present invention. As shown inFIG.3, in contrast to epitaxial layers56,58having different sizes therebetween or the gate structures26,28,30having different gaps therebetween as disclosed in the embodiment shown inFIG.2, according to an embodiment of the present invention, it would be desirable to adjust the position of each of the gate structures26,28,30so that each of the gate structures26,28,30could have different widths while having same spacing therebetween, and at the same time the epitaxial layers56,58disposed adjacent to two sides of the gate structure30also include same size and/or the same diameter thereby improving the leakage performance of the transistor device.

Specifically, each of the epitaxial layers56,58adjacent to two sides of the gate structure30could include a circular or substantially circular profile, in which the diameter R2of the epitaxial layers56on the left side of the gate structure30or between the gate structures26,30is preferably equal to the diameter R1of the epitaxial layer58on the right side of the gate structure30or between the gate structures28,30.

Since the diameter R2of the epitaxial layer56on the left side of the gate structure30is preferably equal to the diameter R1of the epitaxial layer58on the right side of the gate structure30, the distance D1between the gate structures28,30or more specifically the distance D1measuring from the left sidewall of the gate structure28to the right sidewall of the gate structure30is preferably equal to the distance D2between the gate structures26,30or more specifically the distance D2measuring from the left sidewall of the gate structure30to the right sidewall of the gate structure26.

Similar to the aforementioned embodiment, the three gate structure26,28,30in this embodiment could also include different combinations of the same widths and/or different widths depending on the demand of the product. For instance, as shown inFIG.3, the width W1of the middle gate structure30or gate electrode is preferably less than the width W2of the gate structure26on the left side while the width W2of the gate structure26is further less than the width W3of the gate structure28on the right side. Nevertheless, according to an embodiment of the present invention, the width W1of the middle gate structure30could be equal to the width W2of the gate structure26on the left while the width W2of the gate structure26is less than the width W3of the gate structure28on the right. In other words, the gate structure26and the gate structure30could be having same widths W1and W2while each of the widths W1and W2is less than the width W3of the gate structure28directly on the SDB structure42. These variations are all within the scope of the present invention.

Referring toFIG.4,FIG.4illustrates a structural view of a semiconductor device according to an embodiment of the present invention. As shown inFIG.4, in contrast to the epitaxial layers56,58having different sizes as shown inFIG.2, the present invention may additionally perform an extra photo-etching process to remove or thin a portion of the spacer46on the right sidewall of the gate structure30and a portion of the spacer46on the left sidewall of the gate structure28during formation of the spacers46. By doing so, the epitaxial layer56disposed on the left side of the gate structure30and the epitaxial layer58on the right side of the gate structure30could thereby having same size, shape, and diameter after forming recess in the fin-shaped structure14and filling the epitaxial layer58in the recess. In other words, asymmetrical spacers46are formed on left and right sidewalls of the gate structure28,30, in which the thickness of the spacer46on left sidewall of the gate structure28is preferably less than the spacer46on right sidewall of the gate structure28and the thickness of the spacer46on right sidewall of the gate structure30is less than the spacer46on left sidewall of the gate structure30. In addition, even though the diameter R1of the substantially circular epitaxial layer58on right side of the gate structure30is preferably equal to the diameter R2of the substantially circular epitaxial layer56on the left side, the distance D1between the gate structure28and the gate structure30is still less than the distance D2between the gate structures26,30as disclosed in the embodiment ofFIG.2.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.