Patent ID: 12255836

DETAILED DESCRIPTION

Pursuant to embodiments of the present invention, main and secondary processors are provided that may be used, for example, in active antenna modules for cellular communications systems. A single processor chip/device may not be able to perform all of the functions that are demanded by a massive MIMO (e.g., 32T32R) array. Accordingly, by splitting processing functions between main and secondary processors, the demands of a massive MIMO array can be better addressed.

An issue then arises as to how to split the processing functions between the main and secondary processors. For example, the size and processing requirements of the main processor may be reduced by using the secondary processors to convert between frequency and time domains. Such a reduction in size and processing requirements for the main processor may improve heat dissipation and reduce the overall cost of an active antenna module having the main and secondary processors.

Moreover, control-plane information of a downlink protocol can be communicated from the main processor to the secondary processors during a frequency guard band. Because the guard band will not be fully used, it can provide room for both the control-plane information and relaxed timing requirements. For example, user-plane data in the frequency domain may require less bandwidth with respect to the final conversion in the time domain. On the other hand, some real time control-plane information may still be necessary to allow the full conversion. Also, by splitting the processing functions relatively evenly, requirements for system throughput may be decreased, thus allowing for a lower-speed link (or for a smaller number of links) between the main and secondary processors.

As discussed above, the main and secondary processors according to embodiments of the present invention may be part of an active antenna module that provides 5G communications capability. Before discussing the main and secondary processors according to embodiments of the present invention, an example active antenna module in which these processors may be used will be discussed in greater detail.

FIGS.1A and1Bare perspective front and back views, respectively, of an active antenna module100that may include processors according to embodiments of the present invention. As shown inFIGS.1A and1B, the active antenna module100includes a housing110and an outer radome192. The housing110may include heat fins112that are used to dissipate heat generated by active circuit components that are mounted within the housing110. The housing110with heat fins112forms the rear side of the active antenna module100. The radome192may be formed of a dielectric material that is substantially transparent to RF radiation in the operating frequency band of the active antenna module100. The radome192may be mounted forwardly of the housing110and may cover and protect a multi-column array of radiating elements that is included in the active module100.

The active antenna module100may be used as a standalone antenna. When used in this fashion, the active antenna module100may be mounted on a raised structure with the radiating elements thereof pointing outwardly so that they can form antenna beams in the direction of the intended coverage area for the active antenna module100. A pair of fiber optic cables may extend between the active antenna module100and a baseband unit (not shown).

The active antenna module may alternatively be integrated into a larger “passive” base station antenna. A passive base station antenna refers to a base station antenna that includes one or more arrays of radiating elements that generate relatively static antenna beams. Passive base station antennas include RF connectors or “ports” that are connected to external radios.

FIGS.2A and2Bare perspective front and back views, respectively, of the active antenna module100ofFIGS.1A-1Bpartially slid into place within a larger passive base station antenna10. The passive base station antenna10may comprise an elongated structure that extends along a longitudinal axis L. The passive base station antenna10includes a radome12and a first top end cap14. The passive base station antenna10also includes a bottom end cap16which includes a plurality of RF ports18(FIGS.3A-3B) mounted therein. The RF ports18are connected to external radios (not shown) that are connected to the arrays of radiating elements of the passive base station antenna10. The passive base station antenna10is typically mounted in a vertical configuration (i.e., the longitudinal axis L may be generally perpendicular to a plane defined by the horizon when the passive base station antenna10is mounted for normal operation).

The depth of the upper portion22of the passive base station antenna10is less than the lower portion20of the passive base station antenna10. The rear side of the upper portion22of the passive base station antenna10is recessed. This allows the active antenna module100to be pushed or slid into place and secured to the upper rear side of the passive base station antenna10. The lower portion20of the passive base station antenna10includes a second top end cap24.

FIG.3Ais a rear perspective view of the passive base station antenna10with the active antenna module100fully integrated therein.FIG.3Bis a shadow perspective front view of the passive base station antenna10with the active antenna module100integrated therein that schematically illustrates the linear arrays of radiating elements included in the passive base station antenna10. As shown inFIG.3B, the passive base station antenna10includes one or more reflectors26. Various components of the passive antenna10may be mounted behind the lower portion of the reflector26, such as remote electronic tilt units, phase shifters, diplexers, controllers and the like (not shown). A pair of linear arrays30-1,30-2of low-band radiating elements32,34and four linear arrays40-1through40-4of mid-band radiating elements42,44are mounted to extend forwardly from the reflector26. The low-band radiating elements32,34may comprise slant −45°/+45° cross dipole radiating elements that are configured to transmit and receive RF signals in all or part of the 617-960 MHz frequency range. The low-band radiating elements34differ from the low-band radiating elements32in that they have slanted feed stalks so that the active antenna module100can fit in between the two low-band linear arrays30-1,30-2.

The mid-band radiating elements42,44may also comprise slant −45°/+45° cross dipole radiating elements that are configured to transmit and receive RF signals in all or part of the 1427-2690 MHz frequency range. In the depicted embodiment, the outer mid-band linear arrays40-1and40-4include mid-band radiating elements42that are configured to transmit and receive RF signals in the 1695-2690 MHz frequency range (or alternatively the 1427-2690 MHz frequency range), while the inner mid-band linear arrays40-2and40-3include mid-band radiating elements44that are configured to transmit and receive RF signals in the full 1427-2690 MHz frequency range. The radiating elements of the active antenna module100are not shown inFIG.3Bto simplify the drawing.

Passive base station antennas that are designed for use with integrated active antenna modules are discussed in detail in U.S. patent application Ser. No. 17/209,562 (“the '562 application”), the entire content of which is incorporated herein by reference. The passive base station antenna10and the active antenna module100may have the mechanical designs of any of the passive base station antennas and active antenna modules disclosed in the above-referenced '562 application.

FIG.4is an exploded schematic perspective view of the active antenna module100. As shown inFIG.4, the rearmost portion of the active antenna module100is the housing110having heat fins112. The housing110may comprise a metal frame and the heat fins112may be formed integrally with the housing110. The bottom surface of the housing110and the heat fins act as a heat sink. Heat spreading structures (not shown) such as vapor chambers, heat pipes or any other high thermal conductivity material, structure or assembly may also be mounted in the housing110adjacent regions where high heat density occurs during device operation. The heat spreading structures may facilitate spreading heat from a small area (e.g., the area behind active circuits in the active circuit layer120) to a much larger area so that the heat may be vented from the active antenna module100through the heat fins112.

An “active circuit layer”120is mounted forwardly of the heat spreading structures. The active circuit layer120may comprise a printed circuit board structure122(not visible inFIG.4, but shown inFIGS.5and6-7) and an EMI shield124that covers and protects the printed circuit board structure122. The printed circuit board structure122may include multiple printed circuit boards that have processors as well as baseband and RF circuit components mounted thereon such as field programmable gate arrays, amplifiers, oscillators, switches, circulators, up-converters, down-converters and the like. The EMI shield124may comprise a metal (e.g., aluminum) structure that may be formed by, for example, die casting. The EMI shield124shields the circuits and transmission lines in the active circuit layer120from RF radiation from external sources, and prevents RF energy radiated from the active circuit layer120from impacting other circuits/elements in the active antenna module100or the passive antenna10. Electrical connections may extend through the EMI shield124to facilitate connecting circuit elements in the active circuit layer120to the filter layer170. The active circuit layer120will be described in greater detail below with reference toFIGS.5and6-7. Various of the processors and baseband/RF circuit components may generate significant amounts of heat. By providing vapor chambers or other heat spreading structures directly behind the highest heat generating circuits of the active circuit layer120, the heat generated by such circuits may be more efficiently vented from the active antenna module100.

A filter layer170is mounted forwardly of the active circuit layer120. The filter layer170includes a plurality of RF filters174. The RF filters174may be formed as filter banks172that each include a plurality of RF filters174that share a common housing. In the depicted embodiment, a total of four filter banks172are provided that each include eight RF filters174that are formed in a common housing. Each RF filter174may comprise a resonant cavity bandpass filter that is configured to pass RF signals in the operating frequency band of the active antenna module100. The filters174are mounted directly on the EMI shield124.

An antenna layer180is provided forwardly of the filter layer170. The antenna layer180may include a reflector182and a plurality of radiating elements184. The reflector182may comprise, for example, a metallic sheet or a frequency selective surface that is designed to reflect RF energy in the operating frequency range of the radiating elements184of the active antenna module100. The radiating elements184may comprise, for example, slant −45°/+45° cross dipole radiating elements that are configured to transmit and receive RF signals in the operating frequency range of the active antenna module100. This operating frequency range may, for example, comprise all or a portion of the 3.1-4.2 GHz frequency range or all or a portion of the 5.1-5.8 GHz frequency range. In an example embodiment, the operating frequency range may be the 3.4-3.8 GHz frequency band. The radiating elements184may be arranged in a plurality of rows and columns. In the depicted embodiment, a total of eight columns having twelve radiating elements184each are provided. As will be explained below, the upper and lower half of each column are fed by different transceivers so that the active antenna module100operates as two separate eight column arrays186-1,186-2of radiating elements184that are stacked along the longitudinal axis of the active antenna module100. As a result, the active antenna module100effectively includes sixteen columns of radiating elements184(namely two arrays186with eight columns each, where each column includes six radiating elements184). Since the radiating elements184are dual-polarized radiating elements, this means that the active antenna module100effectively has thirty-two columns of radiators that can simultaneously transmit or receive RF signals.

An inner radome190covers and protects the antenna layer180. An outer radome192covers the inner radome190. The function and operation of the inner and outer radomes190,192are described in more detail in the above-referenced '562 application.

FIG.5is a schematic diagram of the printed circuit board structure122of the active circuit layer120, the filter layer170and the antenna layer180. As shown inFIG.5, the printed circuit board structure122includes an optical interface printed circuit board (“PCB”)130, a digital front haul printed circuit board132, a pair of RF front end printed circuit boards134-1,134-2, and a pair of power supply printed circuit boards138-1,138-2. Each RF front end printed circuit board134may have a plurality of RF power amplifier (“PA”) printed circuit boards136mounted thereon. Each RF PA printed circuit board136supports four RF channels, and hence a total of eight RF printed circuit boards136are provided to support thirty-two channels that are coupled to the respective thirty-two columns of radiators discussed above. The active circuit layer120may further include a power bar or other power bus126. The power bus may connect to each of the power supply printed circuit boards138and to the digital front haul printed circuit board132.

The digital front haul printed circuit board132may be mounted in the middle of the heat sink, and may be placed directly on a first of the vapor chambers. The first and second RF front end printed circuit boards134-1,134-2may be mounted on either side of the digital front haul printed circuit board132, and may likewise be mounted directly on respective second and third vapor chambers. Four RF PA printed circuit boards136are mounted on each RF front end printed circuit board134, and may be soldered onto or press fit on the front surfaces of the RF front end printed circuit boards134. The digital front haul printed circuit board132and the first and second RF front end printed circuit boards134may be formed using conventional low cost printed circuit boards formed using FR4 or the like. The RF PA printed circuit boards136may be formed using dielectric materials that have low insertion losses for RF signals.

The filter layer170includes the above-described banks172of resonant cavity filters174. A total of thirty-two resonant cavity filters174are provided, with each resonant cavity filter174coupled to a respective one of the transmit/receive chains on the RF PA printed circuit boards136. As noted above, the filters174may be mounted directly on the EMI shield124that covers and protects the printed circuit boards of the active circuit layer120.

First and second resonant cavity filters174are coupled to each of the sixteen columns of radiating elements184, where the first resonant cavity filter174is coupled to the slant −45° radiators of the radiating elements184in the column, and the second resonant cavity filter174is coupled to the slant +45° radiators of the radiating elements184in the column.

FIGS.6and7are schematic front and side views, respectively, of the printed circuit board structure122of the active circuit layer120. As shown inFIG.6, a pair of optical connector modules140-1,140-2are provided on the optical interface printed circuit board130. Each optical connector module140may have the same design, with two optical connector modules140provided to double the throughput and/or to provide redundancy. Each optical connector module140is a bidirectional device that includes a fiber optic connector, an integrated optical-to-electrical converter that converts optical digital baseband data received at the connector modules140into an electrical baseband data stream and an integrated electrical-to-optical converter that converts an electrical baseband data stream that is received from the digital front haul printed circuit board132into digital optical signals.

A high-speed cable assembly142connects the first and second optical connectors140to a main FPGA144that is mounted on the digital front haul printed circuit board132. The main FPGA144may perform various functions including O-RAN processing and digital beamforming. The main FPGA144is connected to four secondary FPGAs146that are mounted on the RF front end printed circuit boards134(two secondary FPGAs146are provided per RF front end printed circuit board134). High-speed board-to-board connectors148are used to connect the main FPGA144to each of the secondary FPGAs146. Each secondary FPGA146may perform additional processing.

Each secondary FPGA146is connected to a pair of RF transceivers150. Four RF transceivers150are located on each of the RF front end printed circuit boards134, with each RF transceiver150being associated with a respective one of the RF PA printed circuit boards136. Each secondary FPGA is146coupled to its associated two RF transceivers150by a pair of JESD transmission paths152.

Each RF transceiver150includes a digital-to-analog converter, an I/Q modulator (including a local oscillator) that, for downlink signals, converts an input digital data stream into four RF signals. The RF transceivers150likewise include an analog-to-digital converter and an I/Q demodulator that demodulate four RF uplink signals and convert the demodulated data into a digital data stream. Thus, each RF transceiver150comprises the front end of four transmit/receive chains. Each RF PA printed circuit board136includes the back end of four transmit/receive chains, including filters, high power amplifiers, low noise amplifiers, amplifier predistortion circuitry and transmit/receive path switching. Thus, the eight RF transceivers150and the eight RF PA printed circuit boards136together form thirty-two transmit/receive chains. The output of each transmit/receive chain may be coupled to a respective one of the filters174in the filter layer170.

FIG.7is a schematic side view of the printed circuit board structure122of the active circuit layer120. As shown inFIG.7, the digital front haul printed circuit board132may be offset rearwardly from the two RF front end printed circuit boards134so that high-speed board-to-board connectors148may be used to connect each RF front end printed circuit board134to the digital front haul printed circuit board132.FIG.7also illustrates the high-speed cable assembly142that connects the optical connectors140-1,140-2to the digital front haul printed circuit board132.

FIG.8is a schematic block diagram of modules of the main FPGA144, and modules of a first FPGA146-1of the secondary FPGAs146, ofFIG.6, according to embodiments of the present invention. The present invention is not limited, however, to FPGAs. Rather, FPGAs are one example of processors that can include the modules shown inFIG.8. In some embodiments, Application Specific Integrated Circuits (“ASICs”) or other processors may include the modules that are shown inFIG.8. The modules shown inFIG.8may thus be included in either FPGA processors or non-FPGA processors.

As shown inFIG.8, the main FPGA144includes an Ethernet-plus-1588 module810and an O-RAN module820that are each used for both downlink and uplink communications. Specifically, the O-RAN module820controls both downlink and uplink data flows. Likewise, the main FPGA144includes a synchronization module830that is coupled to the Ethernet-plus-1588 module810and that can serve the entire system, in both downlink and uplink directions. The main FPGA144also has downlink-only modules, including a beamforming module851, an I/Q compression module852, and a framer module853. Moreover, the main FPGA144has uplink-only modules, including a de-framer module881, an I/Q decompression module882, a beamforming module883, a PRACH module884, and a sounding reference signal (“SRS”) module885.

As the O-RAN module820may be an O-RAN front-haul interface of the main FPGA144, each of the downlink-only modules of the main FPGA144may be referred to herein as being part of a “post-O-RAN interface” of the main FPGA144. The post-O-RAN interface is configured to parse packets, including (i) user-plane packets and (ii) control-plane packets, that are received from the O-RAN front-haul interface to provide a plurality of output data streams in a frequency domain. The control-plane packets that are received from the O-RAN front-haul interface may be based on control-plane information that is generated by a base station (operating in the frequency domain) of the active antenna module100. Also, each of the uplink-only modules of the main FPGA144may be referred to herein as being part of a “pre-O-RAN interface” of the main FPGA144. The pre-O-RAN interface is configured to generate packets, including user-plane packets, using data received through an uplink protocol from secondary FPGAs146to provide uplink user-plane data to the O-RAN front-haul interface.

The main FPGA144may always receive all symbols from the secondary FPGAs146, including those where no mobile users are scheduled. Though the main FPGA144may not discard any data, it may transmit back to the baseband unit only the symbols/data that are explicitly requested by the baseband unit through control-plane messages.

The Ethernet-plus-1588 module810is coupled to a bidirectional Ethernet link842, which may be implemented, for example, as a high-speed cable assembly142(FIG.6). The main FPGA144is configured to receive an input data stream via the Ethernet link842. For example, the input data stream may be an electrical baseband data stream that was converted from optical digital baseband data received at optical connector module(s)140(FIG.6) from a baseband unit that is at the bottom of a tower that supports an active antenna module100(FIG.4). The input data stream may include (i) user-plane data, (ii) control-plane data (e.g., scheduling information, beamforming information), and (iii) synchronization-plane data (for the synchronization module830).

Based on the input data stream, the Ethernet-plus-1588 module810(a) recognizes packets having an O-RAN protocol, (b) separates the synchronization-plane data from the control-plane data and the user-plane data, (c) reformats the user-plane packets and the control-plane packets for delivery to the O-RAN module820, and (d) outputs downlink data packets (e.g., the reformatted user-plane packets and control-plane packets) to the O-RAN module820. Moreover, the “1588” portion of the Ethernet-plus-1588 module810outputs clock timing/synchronization information (e.g., of/based on the synchronization-plane data) to the synchronization module830. The synchronization module830outputs timing information that ensures that data streams output by the main FPGA144arrive at respective secondary FPGAs146at the same time. In some embodiments, the synchronization module830may provide synchronization for the entire system, including the main FPGA144and the secondary FPGA146, in both downlink and uplink directions.

The O-RAN module820provides data extracted from downlink data (e.g., user-plane) packets to the beamforming module851. This data that is input to the beamforming module851comprise frequency-domain I/Q data. The beamforming module851also receives downlink beamforming weights from the O-RAN module820. For example, the O-RAN module820can send a different beamforming weight for each RF channel (e.g., different weight vectors for each possible stream of data scheduled on the same time slot and frequency resource). The beamforming module851then applies, in the frequency domain, the downlink beamforming weights to different RF channels of the active antenna module100(e.g., the frequency-domain data is divided into thirty-two sub-components that correspond to thirty-two transmit/receive chains, and the beamforming weights generated by the O-RAN module820are applied to the thirty-two sub-components). Different mobile users may be served by the active antenna module100at the same time (e.g., by reusing time-frequency resources) or in different respective time slots, and different respective downlink beamforming weights may be applied for the different users.

The beamforming module851outputs data to the I/Q compression module852, which compresses the data in the frequency domain. For example, the beamforming module851may output data to which it has applied the downlink beamforming weights, and the I/Q compression module852can compress such beamforming-weighted data. The I/Q compression module852outputs the compressed data to the framer module853.

The framer module853, which may comprise a transport layer and a physical layer, sends respective data streams to the secondary FPGAs146. Accordingly, the framer module853outputs a first data stream to the first secondary FPGA146-1, a second data stream to a second secondary FPGA146-2, and an Nth data stream to an Nth secondary FPGA146-N. In some embodiments, the framer module853may comprise, for example, an Ethernet layer or a custom point-to-point high-speed physical layer.

Each secondary FPGA146includes downlink modules and uplink modules. The downlink modules include a de-framer module861, an I/Q decompression module862, a calibration module863, a low physical-layer (“PHY”) module864, a digital upconverter/digital front end (“DUC/DFE”) module865, and a real-time (“RT”) control module866.

The de-framer module861de-frames data packets that are received in the data stream from the main FPGA144. For example, the de-framer module861can separate (i) I/Q data of the data stream from (ii) control-plane information of the data stream. The de-framer module861outputs the I/Q data and the control-plane information to the I/Q decompression module862and RT control module866, respectively.

The RT control module866can understand from the control-plane information that PRACH processing will be needed for a PRACH transmission that will arrive. The control-plane information may be part of the overhead of the data stream.

The I/Q decompression module862decompresses the I/Q data that it receives from the de-framer module861. The I/Q decompression module862then sends the decompressed I/Q data to the calibration module863, which applies antenna calibration parameters to the I/Q data in the frequency domain. Such parameters may compensate for amplitude and phase-delay differences among different RF transmission paths.

The low-PHY module864receives the calibrated frequency-domain I/Q data from the calibration module863and transforms the calibrated data from the frequency domain into the time domain. For example, the low-PHY module864may be configured to perform an inverse fast Fourier transform (“IFFT”) on the calibrated I/Q data. Moreover, the low-PHY module864adds a cyclic prefix (“CP”), which can save bandwidth due to being added by the secondary FPGA146in the time domain rather than transmitted in the frequency domain from the main FPGA144to the secondary FPGA146.

The DUC/DFE module865receives time-domain data from the low-PHY module864. For example, the DFE portion of the DUC/DFE module865may include one or more interpolators that increase the data rate of the time-domain data. In some embodiments, the DFE portion, which can be either inside or outside the secondary FPGA146, can include a digital-to-analog converter (“DAC”) and can perform (i) digital pre-distortion (“DPD”) and/or (ii) crest factor reduction (“CFR”) to ensure that power levels are appropriate for a desired level of efficiency.

Moreover, the DUC portion of the DUC/DFE module865may include a channel filter and may increase the sample rate of the time-domain data. As an example, the presence of multiple carriers (e.g., due to multiple cells) may necessitate an increased sample rate. In some embodiments, the same DUC/DFE module865can receive outputs from multiple low-PHY modules864of respective downlink data flows. The DUC/DFE module865outputs its converted data to a plurality of RF channels of the active antenna module100, where the channels are coupled to respective columns of radiators of the active antenna module100. Moreover, in some embodiments, the low-PHY module864can consume any remaining control-plane data of the downlink protocol between the main FPGA144and the secondary FPGA146, and thus no control-plane data of the downlink protocol may be transmitted from the low-PHY module864to the DUC/DFE module865.

The uplink modules of the secondary FPGAs146include a DFE/digital downconverter (“DDC”) module871, a low-PHY module872, a calibration module873, an I/Q compression module874, a PRACH processing module875, and a framer module876. Some of these uplink modules may perform inverse functions relative to corresponding downlink modules of the secondary FPGAs146.

For example, the DFE/DDC module871can reduce the sample rate and the data rate of data received via radiating elements184(FIG.4) of the active antenna module100and may apply required channel filtering. The low-PHY module872may be configured to perform CP removal and an FFT to transform time-domain data from the DFE/DDC module871into frequency-domain data. Moreover, the I/Q compression module874can compress frequency-domain data, and the framer module876can combine compressed I/Q data from the I/Q compression module874with an output of the PRACH processing module875.

The DUC/DFE module865and the DFE/DDC module871are not limited to a particular upconverter/downconverter architecture. Rather, these modules may be configured to perform, for example, direct RF conversion, zero intermediate frequency (“IF”), or IF output from a DAC and upconversion of IF to RF. Moreover, these modules may be implemented with external transceivers having a JESD interface or with any other radio architecture.

The de-framer module881of the main FPGA144comprises a transport layer and a physical layer and is configured to receive uplink data from the framer module876. In some embodiments, the de-framer module881may comprise, for example, an Ethernet layer or a custom point-to-point high-speed physical layer. The de-framer module881outputs the uplink data to the I/Q decompression module882, which decompresses the uplink data and outputs decompressed I/Q data to the beamforming module883. The beamforming module883can apply uplink beamforming weights that are received from the O-RAN module820to the decompressed I/Q data in the frequency domain.

In some embodiments, the PRACH module884may identify beamforming and I/Q data of a PRACH channel from the decompression module882. Moreover, the SRS module885may extract SRS information from the I/Q decompression module882.

The beamforming module883, the PRACH module884, and the SRS module885each provide their outputs to the O-RAN module820. The O-RAN module820then provides its output to the Ethernet-plus-1588 module810, which provides its output to the bidirectional Ethernet link842. This output may comprise an electrical baseband data stream that is then converted into digital optical signals by one or more optical connector modules140coupled to the Ethernet link842. The O-RAN module820can perform processing of all RT information, such as user-plane data and control-plane data. For example, control-plane information may include time/frequency-domain scheduling, beam forming, TDD, PRACH configuration, and/or data-compression parameters that can be processed by the O-RAN module820.

Accordingly, processing functions can be split among the main FPGA144and the secondary FPGAs146. InFIG.8, this split in processing functionality is indicated by an imaginary line855that extends between the main FPGA144and the secondary FPGAs146. According to other embodiments, however, the line855may be moved to the right to incorporate more modules into the main FPGA144. For example, in the embodiment shown inFIG.11, which will be described in detail below, the line855is to the right of the low-PHY modules864,872.

In still further embodiments, individual modules may be incorporated into the main FPGA144without also incorporating intervening modules that are shown inFIG.8. As an example, the calibration modules863,873may be incorporated into the main FPGA144, while maintaining the de-framer module861, the I/Q decompression module862, the RT control module866, the I/Q compression module874, the PRACH module875, and the framer module876in the secondary FPGAs146.

FIG.9Ais a flowchart of operations corresponding to downlink modules ofFIG.8. The operations include providing (Block910) a plurality of downlink data streams in the frequency domain. For example, the framer module853of the main FPGA144may provide the downlink data streams to the secondary FPGAs146, respectively, after the main FPGA144uses its beamforming module851to apply downlink beamforming weights.

Data of the downlink data streams may be transformed (Block920) from the frequency domain into the time domain. As an example, the low-PHY modules864of the secondary FPGAs146may perform IFFTs on the respective downlink data streams. In other embodiments, such as the embodiment shown inFIG.11, the transformation (Block920) from the frequency domain into the time domain may be performed by the main FPGA144rather than the secondary FPGAs146.

Moreover, the secondary FPGAs146may process (Block930) the time-domain data, such as by using the DUC/DFE module865to increase the data rate and/or the sample rate of the time-domain data. Accordingly, the operations shown inFIG.9Acorrespond to at least one module of the main FPGA144and at least one module of the secondary FPGAs146.

FIG.9Bis a flowchart of operations corresponding to uplink modules ofFIG.8. The operations include providing (Block940) uplink data streams in the time domain. For example, the secondary FPGAs146may receive uplink data streams via radiating elements184(FIG.4) of the active antenna module100.

The operations also include transforming (Block950) data of the uplink data streams from the time domain into the frequency domain. As an example, the low-PHY module872of each secondary FPGA146may perform an FFT on a respective uplink data stream. In other embodiments, such as the embodiment shown inFIG.11, the transformation (Block950) from the time domain into the frequency domain may be performed by the main FPGA144rather than the secondary FPGAs146.

Moreover, the main FPGA144may process (Block960) the time-domain data, such as by using the beamforming module883to apply, in the frequency domain, uplink beamforming weights to I/Q data of the uplink data streams. In some embodiments, processing the frequency-domain data may further include using the I/Q decompression module882, the PRACH module884, and/or the SRS module885of the main FPGA144.

FIG.10Ais a schematic block diagram of a header H-D of a downlink data stream that is output from the main FPGA144ofFIG.8to the first FPGA146-1of the secondary FPGAs146ofFIG.8. Each downlink data stream that the main FPGA144outputs may have a respective header H-D, which may include control-plane information that is sent to a respective secondary FPGA146. For example, the control-plane information may comprise timing information, such as symbol information1001, slot information1002, a frame number1004of a radio frame, and/or a sub-frame number1003of the radio frame.

In some embodiments, the control-plane information may comprise information regarding a PRACH occasion, such as slot information1005, a sub-frame number1006, and/or a frame number1007for the PRACH occasion. Moreover, the control-plane information may comprise PRACH time-offset information1008, PRACH CP length information1010, PRACH physical resource block (“PRB”) information1011, PRACH frequency-offset information1012, and/or PRACH occasion-valid information1013. Other control-plane information in the header H-D may include data-compression information1014, RT spare information1015, and/or calibration information1016.

The header H-D may, in some embodiments, be word #0 of a downlink transmission having a 30 kHz sub-carrier spacing (“SCS”) configuration. For example, in a transmission having frequency points 0 through 4,096, frequency points 0 through 3,275 may comprise data, and a guard section (e.g., guard band) comprising a gap between frequency points 3,275 and 4,096 may provide space for the header H-D and space for relaxed timing requirements.

FIG.10Bis a schematic block diagram of user (e.g., user-plane) data of the downlink data stream ofFIG.10A, whereFIGS.10A and10Bcollectively illustrate a protocol for downlink communications from the main FPGA144to the secondary FPGAs146. In particular,FIG.10Billustrates a specific example use case in which the downlink data stream comprises (i) the specific 5G numerology 1 (SCS of 30 kHz), (ii) a carrier bandwidth of 100 MHZ, (iii) two different component carriers (C0, C1), and (iv) eight data streams for eight different antenna paths handled by the first FPGA146-1of the secondary FPGAs146.

The user data may include I/Q data for each of the frequency points 0 through 3,275. Moreover, each frequency point may comprise two words of the downlink transmission. For example, the frequency point 0 may include word #1 and word #2 of the transmission. Each word may comprise 256 bits. Word #1 may include data C0Q, C0I for each of eight RF channels of the active antenna module100. Similarly, word #2 may include data C1Q, C1I for each of the eight channels. In the use case of the present example, two words for each frequency point are used because two different component carriers C0, C1are being transferred for eight different antenna paths. This pattern may be continued through the frequency point 3,275, which may include word #6,551 having data C0Q, C0I for each of the eight channels and word #6,552 having data C1Q, C1I for each of the eight channels. Referring again toFIG.8, upon receiving the downlink data stream from the main FPGA144, the low-PHY864of the secondary FPGA146may convert each of the frequency points 0 through 3,275 to the time domain.

FIG.10Billustrates an example that is based on the specific 5G numerology 1 and a carrier bandwidth of 100 MHz. The present invention, however, is not limited to either a 100 MHz carrier bandwidth or to a 30 kHz SCS. Accordingly, the active antenna module100may use a downlink protocol between the main FPGA144and the secondary FPGAs146that has a carrier bandwidth other than 100 MHz and/or an SCS other than 30 kHz. A downlink protocol comprising both control-plane information and user-plane data for transmission to the secondary FPGAs146may thus be used for any numerology defined by 5G.

If the carrier bandwidth (e.g., 100 MHz), which is proportional to the number of words in a transmission, changes, then the number of sub-carriers will also change. Moreover, a change in SCS will result in a timing (e.g., symbol spacing) change.

FIG.10Cis a schematic block diagram of a header H-U of an uplink data stream that is input from the first FPGA146-1of the secondary FPGAs146ofFIG.8to the main FPGA144ofFIG.8. As with the downlink data streams, each uplink data stream may, in some embodiments, be a transmission having a 30 kHz SCS configuration. Each of the secondary FPGAs146may provide a respective uplink data stream having a respective header H-U to the main FPGA144.

For example, each uplink data stream may include word #0 through word #6,830, where the header H-U may be word #0. The header H-U may comprise timing information, such as symbol information1021, slot information1022, a frame number1024of a radio frame, and/or a sub-frame number1023of the radio frame. Moreover, the header H-U may comprise PRACH information, such as PRACH symbol information1025, PRACH slot information1026, a PRACH sub-frame number1027, a PRACH frame number1028, and/or PRACH occasional valid information1029.

In some embodiments, the header H-U may comprise further information1030-1032. Moreover, the header H-U may, in some embodiments, include data-compression information that is not shown inFIG.10C.

Though the headers H-U, H-D are part of a packet-based protocol, the protocol can generate a simple, almost-continuous and almost-synchronous, data flow. For example, the post-O-RAN interface of the main processor144may always send data streams to the secondary processors146, even if no data is available from the O-RAN front-haul interface of the main processor144. In this case, dummy “zero” values are sent to the secondary processors146for processing (e.g., for performance of an IFFT on the values) by the low-PHY864. Accordingly, by sending the dummy values, the main processor144can continue to send the data streams when the O-RAN front-haul interface does not output data to the post-O-RAN interface. As an example, the framer853of the post-O-RAN interface can generate and transmit the dummy values when the O-RAN front-haul interface has no data to transmit, such that the framer853provides an almost-continuous data stream to the de-framer861of a secondary FPGA146.

Moreover, as scheduling information may be processed in the main FPGA144, links between the main FPGA144and the secondary FPGAs146may be almost synchronous. Also, the headers H-U, H-D may be implemented in a time and frequency guard of an orthogonal frequency-division multiplexing (“OFDM”) system to send RT control information (i.e., control-plane information).

Using the present invention's internal split (between the main FPGA144and the secondary FPGAs146) of processing along with the protocol of the present invention, the active antenna module100can take advantage of unused frequency points in an OFDM modulation (e.g., in a frequency guard thereof) and avoid the transmission of zeros corresponding to the unused frequency points. For example, as idle time/frequency resources in the guard section (e.g., guard band) of a transmission may not be scheduled, implementation of the protocol may be simplified and overhead of the protocol may be reduced. Moreover, a cyclic prefix can be added in the time domain, thus giving an additional time gap between consecutive symbols. The difference between the throughput required in the time domain as compared with the frequency domain may be the maximum bandwidth available for control-data overhead.

FIG.10Dis a schematic block diagram of user (e.g., user-plane) data of the uplink data stream ofFIG.10C. In particular,FIG.10Dillustrates a specific example use case in which the uplink data stream comprises (i) the specific 5G numerology 1 (SCS of 30 kHz), (ii) a carrier bandwidth of 100 MHz, (iii) two different component carriers (C0, C1), and (iv) eight data streams for eight different antenna paths handled by the first FPGA146-1of the secondary FPGAs146.

For example, each uplink data stream includes physical uplink shared channel (“PUSCH”) data having frequency points 0 through 3,275. The frequency point 0 may include word #1 and word #2 of the uplink transmission, where word #1 may include data C0Q, C0I for each of eight RF channels of the active antenna module100and word #2 may include data C1Q, C1I (where C0and C1refer to two different component carriers) for each of the eight channels. This pattern may be continued through the frequency point 3,275, which may include word #6,551 having data C0Q, C0I for each of the eight channels and word #6,552 having data C1Q, C1I for each of the eight channels.

ThoughFIG.10Dillustrates an example that is based on the specific 5G numerology 1 and a carrier bandwidth of 100 MHz, the present invention is not limited to either a 100 MHz carrier bandwidth or to a 30 kHz SCS. Accordingly, the active antenna module100may use an uplink protocol between the secondary FPGAs146and the main FPGA144that has a carrier bandwidth other than 100 MHz and/or an SCS other than 30 kHz. An uplink protocol comprising both control-plane information and user-plane data for transmission from the secondary FPGAs146to the main FPGA144may thus be used for any numerology defined by 5G.

FIG.10Eis a schematic block diagram of PRACH data (e.g., for short preamble random access) of the uplink data stream ofFIG.10C, whereFIGS.10C-10Ecollectively illustrate a protocol for uplink communications from the secondary FPGAs146to the main FPGA144. For example, the PRACH data may include 139 PRACH frequency points, which may comprise word #6,553 through word #6,830 of the uplink transmission. As an example, the PRACH frequency point 0 may comprise word #6,553 and word #6,554, where word #6,553 may include data C0Q, C0I for each of eight RF channels of the active antenna module100and word #6,554 may include data C1Q, C1I for each of the eight channels. This pattern may be continued through the PRACH frequency point 138, which may include word #6,829 having data C0Q, C0I for each of the eight channels and word #6,830 having data C1Q, C1I for each of the eight channels.

In some embodiments, a user plane and a control plane of the downlink and uplink protocols for transmissions between the main FPGA144and the secondary FPGAs146may be different from a user plane and a control plane of the O-RAN module820. For example, user-plane data and control-plane information of the downlink/uplink protocol may differ from that of the O-RAN module820.

FIG.11is a schematic block diagram of modules of the main FPGA144, and modules of a first of the secondary FPGAs146, ofFIG.6, according to other embodiments of the present invention. For simplicity of illustration, only one secondary FPGA146is shown inFIG.11. Others of the secondary FPGAs146, however, can have the same arrangement of modules therein.

As shown inFIG.11, the main FPGA144may include the low-PHY module864in its downlink path and the low-PHY module872in its uplink path. For example, the main FPGA144may use the low-PHY864to transform data from the frequency domain into the time domain. Conversely, the main FPGA144may use the low-PHY872to transform data from the time domain into the frequency domain. Moreover, the framer module853of the main FPGA144may send time-domain data that is output by the low-PHY864to the DUC/DFE module865of the secondary FPGA146for further processing. The de-framer module881of the main FPGA144may likewise receive an uplink data stream in the time domain from the DFE/DDC871of the secondary FPGA146, and may output time-domain data to the low-PHY872.

The transformation into the time domain by the main FPGA144for a downlink data stream follows processing that the main FPGA144performs (e.g., using its beamforming module851(FIG.8)) on an input data stream to provide a plurality of data streams in the frequency domain. Accordingly, the main FPGA144can transform the frequency-domain data streams into respective time-domain data streams that the main FPGA144outputs via its framer module853to a plurality of secondary FPGAs146, respectively. The secondary FPGAs146can then use their DUC/DFE modules865to perform further processing on the respective data streams in the time domain.

The transformation into the frequency domain by the main FPGA144for an uplink data stream follows processing that the secondary FPGA146performs using its DFE/DDC module871in the time domain. Moreover, the main FPGA144can perform further processing (e.g., using its beamforming module883(FIG.8)) in the frequency domain before outputting the data stream to a baseband unit via an Ethernet link842(FIG.8). Specifically, the main FPGA144can transform and further process each of a plurality of data streams that it receives via its de-framer module881from a plurality of secondary FPGAs146, respectively.

In some embodiments, an active antenna module100that splits processing functionality between the main FPGA144and the secondary FPGAs146as indicated by the position of the imaginary line855that is shown inFIG.11may not require a header H (FIGS.10A and10C) for transmissions between the main FPGA144and the secondary FPGAs146. Specifically, the amount of control-plane information used when the line855is at the position shown inFIG.11may be reduced relative to when the line855is at the position shown inFIG.8. For example, when the main FPGA144ofFIG.11includes the I/Q decompression module862(FIG.8), the I/Q compression module874(FIG.8), the calibration modules863,873, and the low-PHY modules864,872, communication of calibration information1016(FIG.10A), compression information1014(FIG.10A), and timing information between the main FPGA144and the secondary FPGAs146may no longer be required.

Antennas according to embodiments of the present invention may provide a number of advantages. For example, referring toFIG.8, splitting processing functions/resources between the main FPGA144and the secondary FPGAs146reduces processing requirements for the main FPGA144, thus allowing the main FPGA144to be smaller, which can reduce cost and enable better heat dissipation. This split may also relax timing requirements. Accordingly, control-plane information may be communicated between the main FPGA144and the secondary FPGAs146in gaps that are provided by guard sections (in frequency and time) in downlink and uplink transmissions.

Embodiments of the present invention have been described above with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (i.e., “between” versus “directly between”, “adjacent” versus “directly adjacent”, etc.).

Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer or region to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” “comprising,” “includes” and/or “including” when used herein, specify the presence of stated features, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, operations, elements, components, and/or groups thereof.

Aspects and elements of all of the embodiments disclosed above can be combined in any way and/or combination with aspects or elements of other embodiments to provide a plurality of additional embodiments.