Patent ID: 12211897

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

FIG.1shows a perspective view of a GAA FET semiconductor device showing one of the stages of a manufacturing process according to an embodiment of the present disclosure. One or more gate structures120extending in the X-direction are disposed over one or more fin structures FS extending in the Y-direction. The X-direction is substantially perpendicular to the Y-direction. The fin structures FS are formed over a semiconductor substrate100. A lower portion of the fin structure FS is embedded in an isolation insulating layer111, and the gate structure120wraps around semiconductor nanosheets102,104,106and108that are vertically arranged above the fin structure FS. Source/drain stressors117are formed on opposite sides of the gate structure120. Each of the source/drain stressors117includes two or more regrown source/drain layers (e.g., layers113,114,115and116as illustrated inFIG.1). The regrown source/drain layers each have a first chemical element (e.g., silicon) and a second chemical element (e.g., germanium), but have different atomic ratios of the second chemical element to the first chemical element. In this way, the atomic ratio (e.g., germanium-to-silicon atomic ratio) difference among the regrown source/drain layers can be tuned to reduce the strain mismatch among the semiconductor nanosheets102,104,106and108, which will be explained in greater detail below.

FIGS.2A-13Bshow exemplary sequential processes for manufacturing a GAA FET according to some embodiments of the present disclosure. It is understood that additional operations can be provided before, during, and after processes shown byFIGS.2A-13B, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable. InFIGS.2A-11B,12A,13A and13B, the “A” figures (e.g.,FIG.2A) illustrate a cross-sectional view along Y-direction corresponding to the line A-A illustrated inFIG.1,FIGS.2B,3B,4B,5B,6B,11B and13Billustrate a cross-sectional view along the X-direction corresponding to the line B-B illustrated inFIG.1,FIGS.7B,8B,9B, and10Billustrate a cross-sectional view along the X-direction corresponding to the line C-C illustrated inFIG.1.FIG.12Billustrates a perspective view at the intermediate stage corresponding to the cross-sectional view ofFIG.12A.

As shown inFIGS.2A and2B, a semiconductor substrate100is provided. In some embodiments, the substrate100may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multi-layered or gradient substrate, or the like. The substrate100may include a semiconductor material, such as an elemental semiconductor including Si and Ge; a compound or alloy semiconductor including SiC, SiGe, GeSn, GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb, GaInAsP; a combination thereof, or the like. The substrate100may be doped or substantially un-doped. In a specific example, the substrate100is a bulk silicon substrate, which may be a wafer.

The substrate100may include in its surface region, one or more buffer layers (not shown). The buffer layers can serve to gradually change the lattice constant from that of the substrate to that of the source/drain regions. The buffer layers may be formed from epitaxially grown single crystalline semiconductor materials such as, but not limited to Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP.

Impurity ions (interchangeably referred to as dopants) are implanted into the silicon substrate100to form a well region (not shown). The ion implantation is performed to prevent a punch-through effect. The substrate100may include various regions that have been suitably doped with impurities (e.g., p-type or n-type conductivity). The dopants are, for example, boron (BF2) for an n-type GAA FET and phosphorus for a p-type GAA FET.

In some embodiments of the present disclosure a layer stack is prepared, as shown inFIGS.2A and2B. A first semiconductor layer (first buffer layer)101is formed over the substrate100. A second semiconductor layer (first channel layer)102is formed over the first semiconductor layer101. Another first semiconductor layer (second buffer layer)103is formed over the second semiconductor layer102. Another second semiconductor layer (second channel layer)104is formed over the another first semiconductor layer103. Another first semiconductor layer (third buffer layer)105is formed over the second semiconductor layer104. Another second semiconductor layer (third channel layer)106is formed over the first semiconductor layer105. Another first semiconductor layer (fourth buffer layer)107is formed over the second semiconductor layer106. Another second semiconductor layer (fourth channel layer)108is formed over the first semiconductor layer107. Another first semiconductor layer (fifth buffer layer)109is formed over the second semiconductor layer108.

In some embodiments, the first and second semiconductor layers are alternately stacked such that there are more than two layers each of the first and second semiconductor layers. In some embodiments, each of the second semiconductor layers, which become the nanosheets or channel layers, can be formed of different materials. The nanosheets can be interchangeably referred to as nano wires, nanoslabs and nanorings, depending on their geometry. In some embodiments, the lattice constant of the second semiconductor layers is greater than the lattice constant of the first semiconductor layers. In other embodiments, the lattice constant of the second semiconductor layers is smaller than the lattice constant of the first semiconductor layers.

In some embodiments, the first and second semiconductor layers are made of different materials selected from the group consisting of Si, Ge, SiGe, GeSn, Si/SiGe/Ge/GeSn, SiGeSn, and combinations thereof. In some embodiments, the first and second semiconductor layers are formed by epitaxy. In some embodiments, the SiGe is Si1-xGex, where 0.1≤x≤0.9.

In some embodiments, the first semiconductor layers101,103,105,107and109are formed of a first semiconductor material. In some embodiments, the first semiconductor material includes a first Group IV element and a second Group IV element. The Group IV elements are selected from the group consisting of C, Si, Ge, Sn, and Pb. In some embodiments, the first Group IV element is Si and the second Group IV element is Ge. In certain embodiments, the first semiconductor material is Si1-xGex, wherein 0.2≤x≤0.9. For example, the first semiconductor material is Si0.8Ge0.2. In some embodiments, the first semiconductor layers101,103,105,107and109have substantially the same atomic ratio of silicon to germanium (e.g., Si0.8Ge0.2).

In some embodiments, the second semiconductor layers102,104,106and108are formed of a second semiconductor material. In some embodiments, the second semiconductor material includes a first Group IV element and a second Group IV element. In some embodiments, the first Group IV element is Si and the second Group IV element is Ge. In some embodiments, the amounts of the first Group IV element and second Group IV element are different in the second semiconductor material than in the first semiconductor material. In some embodiments, the amount of Ge in the first semiconductor material is greater than the amount of Ge in the second semiconductor material. For example, the second semiconductor material is Si1-yGey, wherein 0.1≤y≤0.8, and x>y. In some embodiments, the second semiconductor material includes a Group III element and a Group V element. In certain embodiments, the second semiconductor material is silicon. Stated another way, the second semiconductor material is substantially free of germanium.

The first semiconductor layers101,103,105,107,109and second semiconductor layers102,104,106and108may be formed by one or more epitaxy or epitaxial (epi) processes. The epitaxy processes include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy (MBE), and/or other suitable processes.

In some embodiments, the thickness t2 of the second semiconductor layers (e.g., channel layers)102,104,106and108measured in the Z-direction is a range from about 5 nm to about 10 nm. The first semiconductor layers101,103,105,107and109are not thinner than the second semiconductor layers102,104,106and108. For example, the thickness t1 of the first semiconductor layers and the thickness t2 of the second semiconductor layers are related as t1/t2=1 to 8. In some embodiments, the thickness t1 of the first semiconductor layers measured in the Z-direction is in a range from about 10 nm to about 40 nm.

After the epitaxial growth process of the layer stack is complete, a patterned mask110is formed over the topmost first semiconductor layer109. The patterned mask110may be formed using depositing a mask layer over the topmost first semiconductor layer109, followed by patterning the mask layer into the patterned mask110using suitable photolithography and etching techniques. The patterned mask110includes silicon nitride (Si3N4), silicon oxide, the like, or combinations thereof.

After forming the patterned mask110, a patterning process is performed on the layer stack to form a fin structure FS, as illustrated inFIGS.3A and3B. In some embodiments, the patterning process comprises one or more etching processes, where the patterned mask layer110is used as an etch mask. The one or more etching processes may include wet etching processes, anisotropic dry etching processes, or combinations thereof, and may use one or more etchants that etch the first and second semiconductor layers101-109at a faster etch rate than it etches the patterned mask layer110. Although the fin structure FS illustrated inFIG.3Bhas vertical sidewalls, the etching process may lead to tapered sidewalls, as indicated by dash line DL1, in some other embodiments.

Once the fin structure FS has been formed, shallow trench isolation (STI) regions111(interchangeably referred to as isolation insulation layer) are formed around a lower portion of the fin structure FS are illustrated inFIGS.4A and4B. STI regions111may be formed by depositing one or more dielectric materials (e.g., silicon oxide) to completely fill the trenches around the fin structures FS and then recessing the top surface of the dielectric materials. The dielectric materials of the STI regions111may be deposited using a high density plasma chemical vapor deposition (HDP-CVD), a low-pressure CVD (LPCVD), sub-atmospheric CVD (SACVD), a flowable CVD (FCVD), spin-on coating, and/or the like, or a combination thereof. After the deposition, an anneal process or a curing process may be performed. In some cases, the STI regions111may include a liner such as, for example, a thermal oxide liner grown by oxidizing the silicon surface or silicon germanium surface of the fin structure FS and the substrate100. The recess process may use, for example, a planarization process (e.g., a chemical mechanical polish (CMP)) followed by a selective etch process (e.g., a wet etch, or dry etch, or a combination thereof) that may recess the top surface of the dielectric materials in the STI regions111such that an upper portion of the fin structure FS protrudes from surrounding insulating STI regions111.

Once the STI regions111have been formed, a dummy gate structure112is formed over the fin structure FS, as illustrated inFIGS.5A and5B. The dummy gate structure112has a lengthwise direction perpendicular to the lengthwise direction of the fin structure FS. The dummy gate structure112includes a dummy gate dielectric layer112d, a dummy gate electrode layer112gover the dummy gate dielectric layer112dand a hard mask layer112m. The dummy gate dielectric layer112dmay be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. The dummy gate layer112gcan be deposited over the dummy dielectric layer112dand then planarized, such as by a CMP process. The hard mask layer112mmay be deposited over the dummy gate layer112g. The dummy gate electrode layer112gmay be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon), polycrystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate electrode layer112gmay be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or the like. The hard mask layer112mmay include, for example, silicon nitride, silicon oxynitride, or the like.

Once the dummy gate dielectric layer112d, the dummy gate electrode layer112gand the hard mask layer112mhave been deposited, the hard mask layer112mis patterned using acceptable photolithography and etching techniques to form a hard mask. The pattern of the hard mask is then transferred to the underlying dummy gate electrode layer112gand dummy gate dielectric layer112dby an acceptable etching technique to form the dummy gate structure112having a longitudinal axis extending in X-direction perpendicular to the longitudinal axis of the fin structure FS that extends in Y-direction.

In a subsequent step, the exposed fin mask110and underlying fin structure FS that extend laterally beyond the dummy gate structure112along Y-direction are removed, for example, in an anisotropic etch step until the substrate100is exposed. The resulting structure is illustrated inFIGS.6A and6B. The etching is performed using an etchant that attacks the mask110and fin structure FS, and hardly attacks the gate hard mask112m. Stated differently, the gate hard mask112mhas higher etch resistance to the etching process than that of the fin mask110and fin structure FS. Accordingly, in the etching step, the height of gate structure112is substantially not reduced. Although the resulting fin structure FS illustrated inFIG.6Ahas vertical sidewalls, the etching process may lead to tapered sidewalls, as indicated by dash line DL2, in some other embodiments.

In some embodiments, the fin structure FS may be etched by a dry chemical etch with a plasma source and an etchant gas. The plasma source may be inductively coupled plasma (ICR) etch, transformer coupled plasma (TCP) etch, electron cyclotron resonance (ECR) etch, reactive ion etch (RIE), or the like and the etchant gas may be fluorine, chlorine, bromine, combinations thereof, or the like, which etches the fin structure FS at a faster etch rate than it etches the gate hard mask112m. After etching the fin structure FS is complete, a cleaning process is optionally performed on the exposed substrate100to remove any possible oxide formation on the silicon surface by using, for example, a diluted hydrofluoric acid (HF) solution.

In a subsequent step, a silicon germanium epitaxial process is performed to epitaxially grow source/drain stressors117having a plurality of epitaxial silicon germanium layers, such as layers113,114,115and116, on the exposed substrate100, as illustrated inFIGS.7A-10B. Formation of the silicon germanium layers (interchangeably referred to as regrown source/drain layers)113,114,115and116is performed “in-situ” without interrupting an epitaxial process. The silicon germanium layers113-116have different atomic ratios of germanium to silicon (i.e., different germanium atomic concentration), which in turn reduces the strain mismatch among the semiconductor nanosheets.

The Ge-to-Si atomic ratio difference among the layers113-116can be achieved by modifying a flow rate ratio between the germanium precursor gas and the silicon precursor during a continuous epitaxial growth. For example, at an initial stage of the continuous epitaxial growth, the silicon germanium layer113is formed at a first process condition, as illustrated inFIGS.7A and7B. The in-situ epitaxial process then continues at a second process condition and the next silicon germanium layer114is formed over the silicon germanium layer113, as illustrated inFIGS.8A and8B. The in-situ epitaxial process then continues at a third process condition and the next silicon germanium layer115is formed over the silicon germanium layer114, as illustrated inFIGS.9A and9B. The in-situ epitaxial process then continues at a fourth process condition and the next silicon germanium layer116is formed over the silicon germanium layer115, as illustrated inFIGS.10A-10B. The first, second, third and fourth process conditions are different at least in the flow rate ratio of a Ge precursor gas to a Si precursor gas, so that the layers113-116have different Ge-to-Si atomic ratios.

These silicon germanium layers113-116are grown in a bottom-up fashion. For example, silicon germanium layers113-116can be grown by an epitaxial deposition/partial etch process, which repeats the epitaxial deposition/partial etch process at least once. Such repeated deposition/partial etch process is also called a cyclic deposition-etch (CDE) process. In some embodiments, these silicon germanium layers113-116are grown by selective epitaxial growth (SEG), where an etching gas is added to promote the selective growth of silicon germanium from the exposed top surface of the substrate100that is parallel with the (100) crystal plane, but not from the sidewalls of the fin structure FS that are parallel with the (110) crystal plane. For example, the silicon germanium layers113-116are epitaxially grown using reaction gases such as HCl as an etching gas, GeH4as a Ge precursor gas, DCS and/or SiH4as a Si precursor gas, B2H6as B dopant (i.e., p-type dopant) precursor, H2, and/or N2. In some embodiments, the etching gas may be other chlorine-containing gases or bromine-containing gases such as Cl2, BCl3, BiCl3, BiBr3or the like.

The growth rate on the horizontal surface of the substrate100is different from the growth rate on the vertical sidewalls of the fin structure FS due to the different crystal plane orientations. For example, silicon germanium growth on the (100) crystal plane (e.g., horizontal surface of the substrate100) is at least about three times (3×) faster than the silicon germanium growth on the (110) crystal plane (e.g., sidewalls of the fin structure FS). Accordingly, the bottom-up growth process incorporates the etching gas to promote bottom-up silicon germanium growth by preventing silicon germanium from growing on the sidewalls of the fin structure FS. For example, silicon germanium is grown from the horizontal surface of the substrate100at a higher rate than that of silicon germanium grown from the sidewalls of the fin structure FS. The etching gas removes the silicon germanium grown from the sidewalls of the fin structure FS as well as some silicon germanium grown from the horizontal surface of the substrate100at comparable etch rates. However, since the silicon germanium growth rate from the horizontal surface of the substrate100is faster than from the sidewalls of the fin structure FS, the net effect is that silicon germanium will substantially grow from the bottom-up. By way of example and not limitation, in each deposition-etch cycle of the CDE process, the etching step stops once the sidewalls of the fin structure FS are exposed, and the silicon germanium grown from the horizontal surface of the substrate100remains on the substrate100because it is thicker than the silicon germanium grown from sidewalls of the fin structure FS. In this way, the bottom-up growth can be realized.

To achieve different atomic ratios of germanium to silicon in these layers113-116, a ratio of a flow rate of the Ge precursor gas (e.g., GeH4) to a flow rate of the Si precursor gas (e.g., SiH4) is varied for their respective growth processes. For example, a Ge-to-Si precursor flow rate ratio during the epitaxial growth of the layer114is greater than that of the layer113, a Ge-to-Si precursor flow rate ratio during the epitaxial growth of the layer115is greater than that of the layer114, and a Ge-to-Si precursor flow rate ratio during the epitaxial growth of the layer116is greater than that of the layer115. In this way, the Ge-to-Si atomic ratio of the layer116is greater than that of the layer115, the Ge-to-Si atomic ratio of the layer115is greater than that of the layer114, and the Ge-to-Si atomic ratio of the layer114is greater than that of the layer113. By way of example and not limitation, the layer113is Si0.45Ge0.55, the layer114is Si0.44Ge0.56, the layer115is Si0.43Ge0.57, and the layer116is Si0.40Ge0.60.

The channel layer102(e.g., silicon layer) is in contact with the silicon germanium layer113and thus the silicon germanium layer113can induce a compressive strain in the channel layer102. This is because the intrinsic lattice constant of germanium is larger than that of silicon. For similar reasons, the channel layer104in contact with the silicon germanium layer114, the channel layer106in contact with the silicon germanium layer115, and the channel layer108in contact with the silicon germanium layer116experience compressive strains.

In some embodiments, the channel layer102is spaced from the silicon germanium layers114,115and116, so that the silicon germanium layer113dominates the compressive strain in the channel layer102. Similarly, the channel layer104is spaced from the silicon germanium layer113,115and116, and thus the silicon germanium layer114dominates the compressive strain in the channel layer104. The channel layer106is spaced from the silicon germanium layer113,114and116and thus experiences a compressive strain dominated by the silicon germanium layer115. The channel layer108is spaced from the silicon germanium layer113,114and115and thus experiences a compressive strain dominated by the silicon germanium layer116.

It is observed that if the channel layers of a GAA FET are disposed between SiGe stressors with a uniform Ge-to-Si atomic ratio, the higher channel layer would experience the lower compressive strain, thus leading to compressive strain mismatch among the channel layers. However, because the layer116has a greater Ge-to-Si atomic ratio than the underlying layer115, the layer115has a greater Ge-to-Si atomic ratio than the underlying layer114, and the layer114has a greater Ge-to-Si atomic ratio than the underlying layer113, the compressive strain mismatch among the channel layers102,104,106and108can be alleviated, which in turn improves uniformity of the carrier mobility among the channel layers102,104,106and108.

In some embodiments, the alloy composition in each silicon germanium layer is substantially uniform. For example, the layer113is Si0.45Ge0.55in each position in the layer113, the layer114is Si0.44Ge0.56in each position in the layer114, the layer115is Si0.43Ge0.57in each position in the layer115, and the layer116is Si0.40Ge0.60in each position in the layer116. In some other embodiments, the alloy composition in each silicon germanium layer is graded. In some embodiments, at least one silicon germanium layer can be undoped, or doped with p-type dopant (e.g., boron or gallium) by in-situ doping simultaneously with epitaxial growth, ion implantation after epitaxial growth, or both. In some embodiments, the dopant profile (e.g., boron concentration profile) in each silicon germanium can be a box profile, Gaussian profile, erf profile, or the like. In some embodiments, each silicon germanium layer can be strained or partially relaxed.

In some embodiments, thicknesses of the silicon germanium layers113-116each are in a range from about 5 nm to about 500 nm. In some embodiments, the thicknesses of the silicon germanium layers113-116are the same or different. In some embodiments, when viewed in a cross section taken along a direction perpendicular to a longitudinal axis of the fin structure FS (e.g., the cross sectional view as shown inFIG.10B), the geometry of the bottom silicon germanium layer113can be a diamond shape, a circular shape, a polygonal shape, or the like. In some embodiments, when viewed in the cross section taken along the direction perpendicular to the longitudinal axis of the fin structure FS, the upper silicon germanium layers114,115and116can be a A-shape, a rounded shape, a polygonal shape, or the like.

Due to different growth rates on different surface planes, facets may be formed. For example, the growth rate on surfaces having (111) surface orientations is lower than that of other planes such as (110) and (100) planes. Accordingly, when viewed in a cross section as shown inFIG.10B, the resultant source/drain stressors117have facets117uand117d, which have the (111) surface orientations (in other word, on (111) planes). Throughout the description, the facets117u, which face away from the substrate100, are referred to as up-slant facets, while the facets117d, which face toward the substrate100, are referred to as down-slant facets. The down-slant facets117dand the respective top surfaces of STI regions111may have an angle α, which may be from about 50 degrees to about 60 degrees. Although the depicted source/drain stressors have facets with (111) surface orientations, the facets of the source/drain stressors may have {311}, {100}, {911} facets or rounded surface in some other embodiments, depending on process conditions of the epitaxial growth.

In some embodiments where the channel layers102,104,106and108are made of silicon, the regrown source/drain layer113is Si1-aGea, the regrown source/drain layer114is Si1-bGeb, the regrown source/drain layer115is Si1-cGec, and the regrown source/drain layer116is Si1-dGed, where 0.3≤a<b<c<d≤0.8.

In some embodiments where the channel layers102,104,106and108are made of silicon germanium, the channel layers102,104,106and108may have lower germanium atomic concentration (or lower germanium-to-silicon atomic ratio) than that of the regrown source/drain layers113-116, so that the regrown source/drain layers113-116can induce compressive strain in the respective channel layers102,104,106and108, which in turn will increase hole mobility in the channel layers102,104,106and108, thus improving the device performance of a resultant p-type GAA FET. By way of example and not limitation, the channel layers102,104,106and108are Si1-xGex, where 0<x<1, and the regrown source/drain layers113/114/115/116are respectively Si1-aGea/Si1-bGeb/Si1-cGec/Si1-dGed, where 0.3≤a<b<c<d≤1, and x<a<b<c<d.

Although the source/drain layers113-116discussed above are silicon germanium, the source/drain layers113-116may be other materials in some other embodiments. For example, in some embodiments where the channel layers102,104,106and108are made of germanium tin (GeSn), the regrown source/drain layers113-116are made of germanium tin as well, but have a higher tin atomic concentration (or higher tin-to-germanium atomic ratio) than that of the channel layers102,104,106and106, so as to induce compressive strain to the respective channel layers102,104,106and108, thus improving the hole mobility of a resultant p-type GAA FET. By way of example and not limitation, the channel layers102,104,106and108are Ge1-xSnx, where 0<x<0.3, and the regrown source/drain layers113/114/115/116are respectively Ge1-aSna/Ge1-bSnb/Ge1-cSnc/Ge1-dSnd, where 0<a<b<c<d≤0.3, and x<a<b<c<d. In such embodiments, the source/drain layer113is epitaxially grown at a first flow rate ratio of a tin precursor gas (e.g., SnCl4) to a germanium precursor gas (e.g., GeH4), the source/drain layer114is epitaxially grown at a second Sn-to-Ge precursor flow rate ratio greater than the first Sn-to-Ge precursor flow rate ratio, the source/drain layer115is epitaxially grown at a third Sn-to-Ge precursor flow rate ratio greater than the second Sn-to-Ge precursor flow rate ratio, and the source/drain layer116is epitaxially grown at a fourth Sn-to-Ge precursor flow rate ratio greater than the third Sn-to-Ge precursor flow rate ratio.

In some other embodiments, the channel layers102,104,106and108are made of silicon, and the source/drain layers113-116are made of silicon phosphorous. Therefore, the regrown source/drain layers113-116can induce tensile strain in the respective channel layers102,104,106and108, which in turn will increase electron mobility in the channel layers102,104,106and108, thus improving the device performance of a resultant n-type GAA FET. By way of example and not limitation, the channel layers102,104,106and108are silicon, and the regrown source/drain layers113/114/115/116are respectively Si1-aPa/Si1-bPb/Si1-cPc/Si1-dPd, where 0.002≤a<b<c<d≤0.2. In such embodiments, the source/drain layer113is epitaxially grown at a first flow rate ratio of a phosphorous precursor gas (e.g., PH3) to a silicon precursor gas (e.g., SiH4), the source/drain layer114is epitaxially grown at a second P-to-Si precursor flow rate ratio greater than the first P-to-Si precursor flow rate ratio, the source/drain layer115is epitaxially grown at a third P-to-Si precursor flow rate ratio greater than the second P-to-Si precursor flow rate ratio, and the source/drain layer116is epitaxially grown at a fourth P-to-Si precursor flow rate ratio greater than the third P-to-Si precursor flow rate ratio. In some other embodiments of an n-type GAA FET, the source/drain layers113-116may be made of arsenic doped silicon.

Once the source/drain stressors117have been formed, the dummy gate structure112and the mask110are removed to expose the fin structure FS. The resulting structure is shown inFIGS.11A and11B. The dummy gate structure112may be removed, for example, using a selective etching process that etches the dummy gate structure112at a faster etch rate than it etches other materials on the substrate100. After the dummy gate structure112is removed to expose the mask110, the mask110is removed, for example, using another selective etching process that etches the mask110at a faster etch rate than it etches other materials on the substrate100.

In some embodiments, another mask118can be optionally formed over the source/drain stressors117before etching the dummy gate structure112. In this way, the source/drain stressors117can be protected against the etchants used in removal of the dummy gate structure112and the mask110. The mask118may be formed using depositing a mask layer over the substrate100, followed by patterning the mask layer into the patterned mask118using suitable photolithography and etching techniques. The patterned mask118includes silicon nitride (Si3N4), silicon oxide, the like, or combinations thereof.

Afterwards, the buffer layers101,103,105,107and109are removed by a selective etching process, using the mask118as an etching mask, thus forming openings119between neighboring channel layers102,104,106and108. The resultant structure is illustrated inFIGS.12A and12B. In this way, the channel layers102,104,106and108become suspended over the substrate100and between the source/drain stressors117. This step can be interchangeably referred to as a channel release process. At this interim processing step, the openings119may be filled with ambient environment conditions (e.g., air, nitrogen, etc). The selective etching process removes the material of the buffer layers101,103,105,107and109(e.g., Si0.8Ge0.2) at a faster rate than or without removing the material of the channel layers102(e.g., silicon). By way of example and not limitation, the etch process may include a wet etch process using an etchant such as hydrogen peroxide (H2O2), ammonium hydroxide (NH4OH), tetramethyalammonium hydroxide (TMAH), or another etchant. In some embodiments, the etch process may include a chemical vapor etch process using high-temperature HCl gas. In still further embodiments, the etch process may include an RIE process using a plasma produced from CF4gas. After the channel release process is complete, the patterned mask118may be removed using a selective etching process, such as a wet etching process using hot H3PO4if the mask118is made of silicon nitride.

Afterwards, a gate structure is formed, as illustrated inFIGS.13A and13B. The gate structure may be the final gate of a GAA FET. The final gate structure may be a high-k/metal gate stack, however other compositions are possible. In some embodiments, the gate structure forms the gate associated with the multi-channels provided by the plurality of nanosheets (now having openings therebetween) in the channel region. For example, a high-k/metal gate structure120is formed within the openings119provided by the release of nanosheets102,104,106and108. In various embodiments, the high-k/metal gate structure120includes a gate dielectric layer121formed around the nanosheets102,104,106and108, a work function metal layer122formed over the gate dielectric layer121, and a fill metal123formed over the work function metal layer122. The gate dielectric layer121includes an interfacial layer (e.g., silicon oxide layer) and a high-k gate dielectric layer over the interfacial layer. High-k gate dielectrics, as used and described herein, include dielectric materials having a high dielectric constant, for example, greater than that of thermal silicon oxide (˜3.9). The work function metal layer and/or fill metal layer used within high-k/metal gate stack may include a metal, metal alloy, or metal silicide. Additionally, the formation of the high-k/metal gate stack may include depositions to form various gate materials, one or more liner layers, and one or more CMP processes to remove excessive gate materials. As illustrated inFIG.13B, the resultant high-k/metal gate stack120surrounds each nanosheets102,104,106and108, and thus is referred to as a GAA FET.

In some embodiments, the interfacial layer of the gate dielectric layer121may include a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). The interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable method. The high-k dielectric layer of the gate dielectric layer121may include hafnium oxide (HfO2). Alternatively, the gate dielectric layer121of the gate stack120may include other high-k dielectrics, such as hafnium silicon oxide (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (La2O3), zirconium oxide (ZrO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanium oxide (SrTiO3, STO), barium titanium oxide (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), oxynitrides (SiON), and combinations thereof.

The work function metal layer122may include work function metals to provide a suitable work function for the high-k/metal gate stack120. For an n-type GAA FET, the work function metal layer122may include one or more n-type work function metals (N-metal). The n-type work function metals may exemplarily include, but are not limited to, titanium aluminide (TiAl), titanium aluminium nitride (TiAlN), carbo-nitride tantalum (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC), tungsten carbide (WC)), aluminides, and/or other suitable materials. On the other hand, for a p-type GAA FET, the work function metal layer122may include one or more p-type work function metals (P-metal). The p-type work function metals may exemplarily include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and/or other suitable materials.

The fill metal123may exemplarily include, but are not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, tungsten nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials.

Although the source/drain stressors in the embodiments discussed above include four epitaxial source/drain layers, the source/drain stressor in some other embodiments can include more than four or less than four epitaxial source/drain layers. For example,FIG.14shows a perspective view of a GAA FET according to some other embodiments of the present disclosure.FIG.14shows substantially the same structure asFIG.1, except that the source/drain stressors117′ include two regrown source/drain layers113′ and114′, rather than four source/drain layers as illustrated inFIG.1. The regrown source/drain layers113′ and114′ are silicon germanium but have different germanium-to-silicon atomic ratios. For example, the regrown source/drain layer113′ is Si0.45Ge0.55, and the regrown source/drain layer114′ is Si0.40Ge0.60. Because the upper regrown layer114′ has a greater germanium-to-silicon atomic ratio than the lower regrown layer113′, the compressive strain mismatch among the nanosheets102,104,106and108can be reduced.

FIG.15illustrates simulation results showing compressive strains in different nanosheets of a p-type GAA FET, wherein the compressive strain is shown on the vertical axis inFIG.15, and the vertical distance from the substrate is shown on the horizontal axis inFIG.15. In Condition #1, the vertically arranged nanosheets102a,104a,106aand108aare laterally disposed between two source/drain stressors, where the source/drain stressors each consisting of substantially uniform Si0.45Ge0.55. In Condition #2, the vertically nanosheets102b,104b,106band108bare laterally disposed between two source/drain stressors each consisting of a regrown Si0.45Ge0.55layer and a regrown Si0.40Ge0.60layer over the Si0.45Ge0.55layer, such as the source/drain stressors117′ as illustrated inFIG.14. In Condition #3, the vertically arranged nanosheets102c,104c,106cand108care laterally disposed between two source/drain stressors each consisting of a regrown Si0.45Ge0.55layer, a regrown Si0.44Ge0.56layer over the Si0.45Ge0.55layer, a regrown Si0.43Ge0.57layer over the Si0.44Ge0.56layer, and a regrown Si0.40Ge0.60layer over the Si0.43Ge0.57layer, such as the source/drain stressors117illustrated inFIG.1.

In Condition #1, the compressive strain of the nanosheet104ais lower than that of the nanosheet102a, the compressive strain of the nanosheet106ais lower than that of the nanosheet104a, and the compressive strain of the nanosheet108ais lower than that of the nanosheet106a. This proves that the higher nanosheet (i.e., farther from the substrate) experiences the lower compressive strain, if the source/drain stressors are made of uniform Si0.45Ge0.55.

Comparing Condition #2 with Condition #1, the top nanosheet108bin Condition #2 has a greater compressive strain than that of the top nanosheet108ain Condition #1. This proves that the source/drain stressor consisting of a regrown Si0.45Ge0.55layer and a regrown Si0.40Ge0.60layer over the Si0.45Ge0.55layer induces an increased compressive strain in the top nanosheet, as compared with the source/drain stressors each consisting of uniform Si0.45Ge0.55. Moreover, a maximum compressive strain difference among the nanosheets102b,104b,106band108b(e.g., compressive strain difference between the nanosheet108band104b) in Condition #2 is lower than a maximum compressive strain difference among the nanosheets102a,104a,106aand108a(e.g., compressive strain difference between the nanosheet108aand102a) in Condition #1. This proves that the compressive strain mismatch among the nanosheets in a GAA FET is reduced by the source/drain stressor consisting of a regrown Si0.45Ge0.55layer and a regrown Si0.40Ge0.60layer over the Si0.45Ge0.55layer.

Comparing with Condition #3 with Condition #1, the nanosheet104cin Condition #3 has a greater compressive strain than that of the nanosheet104ain Condition #1, the nanosheet106cin Condition #3 has a greater compressive strain than that of the nanosheet106ain Condition #1, and the nanosheet108cin Condition #3 has a greater compressive strain than that of the nanosheet108ain Condition #1. This proves that the source/drain stressor consisting of a regrown Si0.45Ge0.55layer, a regrown Si0.44Ge0.56layer over the Si0.45Ge0.55layer, a regrown Si0.43Ge0.57layer over the Si0.44Ge0.56layer, and a regrown Si0.40Ge0.60layer over the Si0.43Ge0.57layer induces an increased compressive strain in the nanosheets104,106and108, as compared with the source/drain stressors each consisting of uniform Si0.45Ge0.55. Moreover, a maximum compressive strain difference among the nanosheets102c,104c,106cand108c(e.g., compressive strain difference between the nanosheet108cand102c) in Condition #3 is lower than a maximum compressive strain difference among the nanosheets102a,104a,106aand108a(e.g., compressive strain difference between the nanosheet108aand102a) in Condition #1. This proves that the compressive strain mismatch among the nanosheets in a GAA FET is reduced by the source/drain stressor consisting of a regrown Si0.45Ge0.55layer, a regrown Si0.44Ge0.56layer over the Si0.45Ge0.55layer, a regrown Si0.43Ge0.57layer over the Si0.44Ge0.56layer, and a regrown Si0.40Ge0.60layer over the Si0.43Ge0.57layer.

The simulation results as illustrated inFIG.15is obtained by performing a simulation where the nanosheet length (measured in Y-direction as illustrated inFIG.1) is set from about 25 nm to about 30 nm (e.g., about 28 nm), the nanosheet width (measured in X-direction as illustrated inFIG.1) is set from about 23 nm to about 27 nm (e.g., about 25 nm), the nanosheet thickness (measured in Z-direction as illustrated inFIG.1) is set from about 3 nm to about 7 nm (e.g., about 5 nm), and the nanosheet pitch (i.e., Z-directional distance between neighboring nanosheets as illustrated inFIG.1) is set from about 20 nm to about 24 nm (e.g., about 22 nm). However, these dimensions are only intended to be illustrate and not intended to limit embodiments of the present disclosure. Rather, nanosheets having any other suitable dimension and/or any number of nanosheets can experience similar strain mismatch improvement. For example, the nanosheet pitch can be less than about 22 nm, such as about 11 nm or 16 nm, or be in a range from about 10 nm to about 40 nm. The nanosheet thickness can be greater than about 5 nm, such as about 10 nm, or be in a range from about 5 nm to about 10 nm. The nanosheet width can be in a range from about 5 nm to about 100 nm. The number of nanosheets can be in a range from about 2 to about 10.

FIG.16illustrates a method M1of forming a GAA FET in accordance with some embodiments. Although the method M1is illustrated and/or described as a series of acts or events, it will be appreciated that the method is not limited to the illustrated ordering or acts. Thus, in some embodiments, the acts may be carried out in different orders than illustrated, and/or may be carried out concurrently. Further, in some embodiments, the illustrated acts or events may be subdivided into multiple acts or events, which may be carried out at separate times or concurrently with other acts or sub-acts. In some embodiments, some illustrated acts or events may be omitted, and other un-illustrated acts or events may be included.

At block S101, a fin structure is formed on a substrate. The fin structure has a stack of alternating first semiconductor layers and second semiconductor layers.FIGS.2A-2B and3A-3Billustrate cross-sectional views of some embodiments corresponding to act in block S101.

At block S102, an STI region is formed around a lower portion of the fin structure.FIGS.4A-4Billustrate cross-sectional views of some embodiments corresponding to act in block S102.

At block S103, a dummy gate structure is formed extending across the fin structure.FIGS.5A-5Billustrate cross-sectional views of some embodiments corresponding to act in block S103.

At block S104, portions of the fin structure that extend laterally beyond the dummy gate structure is etched until the substrate is exposed.FIGS.6A-6Billustrate cross-sectional views of some embodiments corresponding to act in block S104.

At block S105, a first source/drain layer is epitaxially grown at a first Ge-to-Si precursor flow rate ratio.FIGS.7A-7Billustrate cross-sectional views of some embodiments corresponding to act in block S105.

At block S106, a second source/drain layer is epitaxially grown at a second Ge-to-Si precursor flow rate ratio higher than the first Ge-to-Si precursor flow rate ratio.FIGS.8A-8Billustrate cross-sectional views of some embodiments corresponding to act in block S106.

At block S107, a third source/drain layer is epitaxially grown at a third Ge-to-Si precursor flow rate ratio higher than the second Ge-to-Si precursor flow rate ratio.FIGS.9A-9Billustrate cross-sectional views of some embodiments corresponding to act in block S107.

At block S108, a fourth source/drain layer is epitaxially grown at a fourth Ge-to-Si precursor flow rate ratio higher than the third Ge-to-Si precursor flow rate ratio.FIGS.10A-10Billustrate cross-sectional views of some embodiments corresponding to act in block S108.

At block S109, the dummy gate structure is removed to expose the fin structure.FIGS.11A-11Billustrate cross-sectional views of some embodiments corresponding to act in block S109.

At block S110, the remaining first semiconductor layers are removed to release the nanosheets formed from the remaining second semiconductor layers.FIGS.12A and12Billustrate a cross-sectional view and a perspective view of some embodiments corresponding to act in block S110.

At block S111, a high-k/metal gate stack is formed around nanosheets formed from the remaining second semiconductor layers.FIGS.13A and13Billustrate cross-sectional views of some embodiments corresponding to act in block S111.

FIGS.17-30show exemplary sequential processes for manufacturing a GAA FET according to some embodiments of the present disclosure. It is understood that additional operations can be provided before, during, and after processes shown byFIGS.17-30, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable.FIGS.17-30illustrate a cross-sectional view along Y-direction corresponding to the line A-A illustrated inFIG.1.

As illustrated inFIG.17, a semiconductor substrate300is provided. In some embodiments, the substrate300may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multi-layered or gradient substrate, or the like. The substrate300may include a semiconductor material, such as an elemental semiconductor including Si and Ge; a compound or alloy semiconductor including SiC, SiGe, GeSn, GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb, GaInAsP; a combination thereof, or the like. The substrate300may be doped or substantially un-doped. In a specific example, the substrate300is an SOI substrate having a buried oxide layer302over a bulk silicon substrate301, and a doped semiconductor (e.g., silicon) layer303over the buried oxide layer302. The doped silicon layer303is thinner than the buried oxide layer302. For example, the doped silicon layer303has a thickness in a range from about 5 nm to about 15 nm (e.g., about 10 nm), and the buried oxide layer302has a thickness in a range from about 130 nm to about 160 nm (e.g., about 145 nm). The doped silicon layer303may be doped with an n-type dopant (e.g., phosphorous) or a p-type dopant (e.g., boron). The substrate300includes first and second device regions310and320. The first device region310is an n-type transistor region, in which one or more n-type transistors such as one or more n-type GAA FETs are to be formed. The second device region320is a p-type transistor region, in which one or more p-type transistors such as one or more p-type GAA FETs are to be formed. As a result, the device region310can be referred to as an NFET region, and the device region320can be referred to as a PFET region.

In some embodiments where the substrate300is an SOI substrate, the silicon layer303in the NFET region310can be optionally doped with a p-type impurity (e.g., boron), and the silicon layer303in the PFET320region can be optionally doped with an n-type impurity (e.g., phosphorous or arsenic). The doped surface layer of the SOI substrate300is helpful to electrically isolate different transistors and/or different device regions, because the doped surface layer is doped with an impurity of a conductivity type opposite a conductivity type of subsequently formed source/drain regions. In some embodiments, the silicon layer303in the NFET region310has a p-type impurity concentration (e.g., boron concentration) in a range from about 1×1014cm−3to about 1×1020cm−3(e.g., about 1×1015cm−3), and the silicon layer303in the PFET region320has an n-type impurity concentration (e.g., phosphorous concentration) in a range from about 1×1014cm−3to about 1×1020cm−3(e.g., about 1×1015cm−3). In some embodiments, the NFET region310and the PFET region320are doped by using different ion implantation processes, wherein the NFET region310is covered by a mask (e.g., photoresist mask) during implanting an n-type impurity into the PFET region, and the PFET region320is covered by a mask (e.g., photoresist mask) during implanting a n-type impurity into the PFET region320.

A strain-relaxed buffer layer400is formed on the semiconductor substrate300by using one or more epitaxy processes. The epitaxy processes include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy (MBE), and/or other suitable processes. The epitaxy duration time of forming the strain-relaxed buffer layer400is long enough such that the strain-relaxed buffer layer400has a minimum thickness (e.g., in a range from about 2 nm to about 500 nm) sufficient to form a relaxed layer having substantially zero value of strain. The strain-relaxed buffer layer400may be a Group IV material, such as Si, Ge, SiGe, SiGeSn, Sn or the like; a Group III-Group V compound material, such as GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb, GaInAsP or the like; SiP, combinations thereof, or the like. The strain-relaxed buffer layer400can be doped or substantially un-doped. In specific embodiments, the strain-relaxed buffer layer400may be formed of doped or substantially un-doped germanium.

In some embodiments, the strain-relaxed buffer layer400in the NFET region310can be doped with a p-type impurity (e.g., boron), and the strain-relaxed buffer layer400in the PFET320region can be doped with an n-type impurity (e.g., phosphorous or arsenic). The doped strain-relaxed buffer layer is helpful to electrically isolate different transistors and/or different device regions, because the doped strain-relaxed buffer layer is doped with an impurity of a conductivity type opposite a conductivity type of subsequently formed source/drain regions.

Once the strained-relaxed buffer layer400has been formed, an annealing process AL1is performed on the strain-relaxed buffer layer400at a temperature from about 600 degrees Centigrade to about 1000 degrees Centigrade (e.g., about 800 degrees Centigrade), as illustrated inFIG.18. The annealing process AL1is helpful to confine crystallographic defects (e.g., threading dislocation defects, point defects, antiphase boundaries or the like) in the interface between the resultant buffer layer401and the substrate300. After the annealing process AL1is complete, the buffer layer401cools down to a predetermined temperature (e.g., room temperature such as about 25 degrees Centigrade). In some embodiments where the buffer layer401is made of a material (e.g., germanium) different from a material of the topmost layer303of the substrate300(e.g., silicon), the buffer layer401may obtain a tensile strain (e.g., about 0.05%-0.30% tensile strain) after the cooling down is complete. This is because of the mismatch among the thermal expansion coefficient of silicon and the thermal expansion coefficient of germanium.

Afterwards, a patterned mask ML1is formed over the NFET region310while leaving the PFET region320exposed. The patterned mask ML1may be formed using depositing a mask layer blanket over the substrate300, followed by patterning the mask layer into the patterned mask ML1using suitable photolithography and etching techniques. The patterned mask ML1includes silicon oxide, silicon nitride (Si3N4), the like, or combinations thereof.

After the NFET region310is covered by the patterned mask ML1, a layer stack is formed over the PFET region320, as illustrated inFIG.19. A first semiconductor layer (first sacrificial layer)422is epitaxially grown on the PFET region320, a second semiconductor layer (first channel layer)423is epitaxially grown on the first semiconductor layer422, another first semiconductor layer (second sacrificial layer)424is epitaxially grown on the second semiconductor layer423, another second semiconductor layer (second channel layer)425is epitaxially grown on the first semiconductor layer424, and another first semiconductor layer (third sacrificial layer)426is epitaxially grown on the second semiconductor layer425. The epitaxy processes include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy (MBE), and/or other suitable processes.

In some embodiments, the first and second semiconductor layers are alternately stacked such that there are more than two layers each of the first and second semiconductor layers. In some embodiments, each of the second semiconductor layers, which become the nanosheets or channel layers, can be formed of a same material or different materials. The nanosheets can be interchangeably referred to as nanowires, nanoslabs and nanorings, depending on their geometry. In some embodiments, the first and second semiconductor layers are made of different materials selected from the group consisting of Si, Ge, SiGe, GeSn, Si/SiGe/Ge/GeSn, SiGeSn, and combinations thereof.

The lattice constant of the channel layers423and425is greater than the lattice constant of the sacrificial layers422,424and426, so that the channel layers423and425are under compressive strains once the epitaxy growth is complete, which in turn will increase hole mobility in the channel layers423and425, thus improving the device performance of p-type GAA FETs formed in the PFET region320. In this way, the compressive-strained channels can be realized without forming regrown source/drain stressors. Moreover, the strain in channels induced from the buffer layer401is retained after the whole device fabrication process (e.g., including a whole front-end-of-line (FEOL) process and a whole back-end-of-line (BEOL) process).

At this intermediate stage as illustrated inFIG.19, the channel layers423and425are substantially un-doped to reduce impurity scattering and random dopant fluctuation, and the sacrificial layers422,424and426are heavily doped with a p-type impurity (e.g., boron) that will be diffused into source/drain regions in the channel layers423and425in a subsequent step. The sacrificial layers422,424and426are in-situ doped during epitaxially growth thereof.

In some specific embodiments for the p-type GAA FET, the sacrificial layers422,424and426are heavily p-doped silicon layers (i.e., p+Si), and the channel layers423and425are substantially un-doped silicon germanium layer (i.e., un-doped SiGe). The heavily p-doped silicon sacrificial layers422,424and426may have a p-type impurity concentration 4 orders, 5 orders, or even 9 orders higher than an n-type impurity concentration in the PFET region320in the topmost layer303of the SOI substrate300. By way of example and not limitation, the boron concentration of the silicon sacrificial layers422,424and426may be in a range from about 1×1019cm−3to about 1×1023cm−3(e.g., 2.7×1020cm−3), the phosphorous concentration in the PFET region320of the substrate300may be in a range from about 1×1014cm−3to about 1×1020cm (e.g., 1×1015cm−3). In some other specific embodiments for the p-type GAA FET, the sacrificial layers422,424and426are heavily p-doped germanium layers (i.e., p+Ge), and the channel layers423and425are substantially un-doped germanium tin layer (i.e., un-doped GeSn).

Once the epitaxial layer stack has been formed over the PFET region320, the mask ML1is removed. An epitaxial layer stack is then formed over the NFET region310. The resultant structure is illustrated inFIG.20. In some specific embodiments, a third semiconductor layer (first sacrificial layer)412is epitaxially grown on the strain-relaxed buffer layer401in the NFET region310, a fourth semiconductor layer (first channel layer)413is epitaxially grown on the third semiconductor layer412, another third semiconductor layer (second sacrificial layer)414is epitaxially grown on the fourth semiconductor layer413, another fourth semiconductor layer (second channel layer)415is epitaxially grown on the third semiconductor layer414, and another third semiconductor layer (third sacrificial layer)416is epitaxially grown on the fourth semiconductor layer415. The epitaxy processes include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and/or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy (MBE), and/or other suitable processes.

In some embodiments, the third and fourth semiconductor layers are alternately stacked such that there are more than two layers each of the third and fourth semiconductor layers. In some embodiments, each of the fourth semiconductor layers, which become the nanosheets or channel layers, can be formed of a same material or different materials.

In some embodiments, the third and fourth semiconductor layers are made of different materials selected from the group consisting of Si, Ge, SiGe, GeSn, Si/SiGe/Ge/GeSn, SiGeSn, and combinations thereof. In some embodiments, the SiGe is Si1-xGex, where 0.02≤x≤0.98.

The lattice constant of the channel layers413and415is smaller than the lattice constant of the sacrificial layers412,414and416, so that the channel layers413and415are under tensile strains once the epitaxy growth is complete, which in turn will increase electron mobility in the channel layers413and415, thus improving the device performance of n-type GAA FETs formed in the NFET region310. In this way, the tensile-strained channels can be realized without forming regrown source/drain stressors. Moreover, the strain in channels induced from the buffer layer401is retained after the whole device fabrication process (e.g., including a whole FEOL process and a whole BEOL process).

At this intermediate stage as illustrated inFIG.20, the channel layers413and415are substantially un-doped to reduce impurity scattering and random dopant fluctuation, and the sacrificial layers412,414and416are heavily doped with a n-type impurity (e.g., phosphorous) that will be diffused into source/drain regions in the channel layers413and415in a subsequent step. The sacrificial layers412,414and416are in-situ doped during epitaxially growth thereof.

In some specific embodiments for the n-type GAA FET, the sacrificial layers412,414and416are heavily n-doped germanium layers (e.g., n+Ge), and the channel layers413and415are substantially un-doped silicon germanium layer (e.g., un-doped Si0.02Ge0.98). In such embodiments, the channel layers413and415have a greater silicon atomic concentration than that of the sacrificial layers412,414and416. Therefore, the channel layers413and415have a greater tensile strain than that in the sacrificial layers412,414and416and the buffer layer401. For example, the germanium buffer layer401, and the germanium sacrificial layers412,414and416have a tensile strain value of about 0.10% to about 0.14% (e.g., about 0.12%) resulting from the annealing process AL1as discussed previously with respect toFIG.18, and the channel layers413and415have a greater tensile strain value of about 0.18% to about 0.22% (e.g. about 0.20%). The improved tensile strain in channel layers413and415result from the sacrificial layers412,414and414as well as the buffer layer401. In some other embodiments for the n-type GAA FET, the sacrificial layers412,414and416are heavily n-doped silicon germanium layers (i.e., n+SiGe), and the channel layers413and415are substantially un-doped silicon layer (i.e., un-doped Si).

The heavily n-doped sacrificial layers (e.g., n+Ge layers)412,414and416may have an n-type impurity concentration 4 orders, 5 orders, or even 9 orders higher than a p-type impurity concentration in the NFET region310in the SOI substrate's topmost layer303. By way of example and not limitation, the phosphorous concentration of the sacrificial layers412,414and416may be in a range from about 1×1019cm−3to about 1×1023cm−3(e.g., 2.7×1020cm−3), and the boron concentration in the NFET region310in the SOI substrate's topmost layer303may be in a range from about 1×1014cm−3to about 1×1020cm (e.g., 1×1015cm−3).

FIG.36is a graph illustrating an experimental result showing atomic concentrations of various chemical elements in the NFET region310that is observed by Secondary Ion Mass Spectroscopy (SIMS) measurement after the layer stack is formed on the NFET region310, wherein atomic concentration is shown on the vertical axis inFIG.36, and the vertical distance from a top surface of the layer stack (i.e., top surface of the topmost sacrificial layer416) is shown on the horizontal axis inFIG.36. In this experiment, the sacrificial layers412,414and416are germanium layers doped with phosphorous, and the channel layers413and415are substantially un-doped silicon germanium (Si0.02Ge0.98) layer. InFIG.36, the curve C1represents a germanium atomic concentration along a vertical distance from a top surface of the layer stack, the curve C2represents a silicon atomic concentration along a vertical distance from a top surface of the layer stack, the curve C3represents a phosphorous atomic concentration along a vertical distance from a top surface of the layer stack, and the curve C4represents an oxygen atomic concentration along a vertical distance from a top surface of the layer stack.

As illustrated in the curve C3inFIG.36, the sacrificial layers412,414and416have a greater phosphorous atomic concentration than that of the channel layer413and415. This proves that the sacrificial layers412,414and416are doped with phosphorous, and the channel layers413and415are substantially un-doped with phosphorous. It is noted that the channel layers413and415may still have non-zero values of phosphorous concentration due to unintentional phosphorous diffusion from the sacrificial layers412,414and416. Comparing the curve C3with the curve C1, the phosphorous atomic concentration in the sacrificial layers412,414and416is greater than the germanium atomic concentration in the sacrificial layers412,414and416. This proves that the sacrificial layers412,414and416are heavily doped with phosphorous.

As illustrated in the curve C2ofFIG.36, the channel layers413and415have a greater silicon atomic concentration than that of the sacrificial layers412,414and416. Moreover, the buffer layer401has gradient silicon germanium that increases as a distance from the substrate300decreases, because of unintentional silicon diffusion from the substrate300.

Reference is made back toFIG.21. Once the layer stack on the NFET region310has been formed, a patterning process is performed on the layer stacks on the NFET region310and the PFET region320to form a fin structure FS1on the NFET region310and a fin structure FS2on the PFET region320by using suitable photolithography and etching techniques, as discussed previously with respect toFIGS.3A and3B. Once the fin structures FS1and FS2have been formed, a dielectric layer (e.g., silicon oxide (SiO2) layer)430is conformally formed over the substrate300using suitable deposition techniques, such as CVD, ALD, thermal oxidation, the like or combinations thereof. The resultant structure is illustrated inFIG.21.

Once the dielectric layer430has been formed, dummy gate electrodes441and442are respectively formed across the fin structures FS1and FS2, as illustrated inFIG.22. The dummy gate electrodes441and442have a lengthwise direction perpendicular to the lengthwise direction of the fin structures FS1and FS2. The dummy gate electrodes441and442may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon), polycrystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate electrodes441and442may be formed by, for example, depositing a polysilicon layer over the substrate300, planarizing the deposited polysilicon layer by CMP, and then patterning the planarized polysilicon layer into the dummy gate electrodes441and442using suitable photolithography and etching techniques.

Once the dummy gate electrodes441and442have been formed, a spacer layer450is conformally formed over the substrate300using suitable deposition techniques, such as CVD, ALD, the like or combinations thereof. The resultant structure is illustrated inFIG.23. The spacer layer450includes silicon nitride (Si3N4), although other materials, such as silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, porous dielectric materials, hydrogen doped silicon oxycarbide (SiOC:H), low-k dielectric materials, or other suitable dielectric materials, may be used.

Next, an anisotropic etching process is performed to etch on the spacer layer450, so that horizontal portions of the spacer layer450are removed while leaving portions451and452of the spacer layer450on sidewalls of the dummy gate electrode441and442. The resulting structure is illustrated inFIG.24. The remaining spacer portions451on sidewalls of the dummy gate electrode441can be interchangeably referred to gate spacers451, and remaining spacer portions452on sidewalls of the dummy gate electrode442can be interchangeably referred to gate spacers452. In some specific embodiments, the anisotropic etching is an RIE process using a plasma produced from CHF3gas and/or Cl2gas.

Once the spacers451and452have been formed, as illustrated inFIG.25, a patterned mask ML2is formed over the PFET region320while leaving the NFET region310exposed. The patterned mask ML2may be formed using depositing a mask layer blanket over the substrate300, followed by patterning the mask layer into the patterned mask ML2using suitable photolithography and etching techniques. The patterned mask ML2includes silicon nitride (Si3N4), silicon oxynitride, the like, or combinations thereof.

Once the patterned mask ML2has been formed, the dummy gate electrode441in the NFET region310is removed to form a gate trench GT between the gate spacers451, by using a selective etching process that etches the dummy gate structure441at a faster etch rate than it etches other materials on the substrate300. For example, the selective etching is an isotropic wet etching process using potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH) as an etchant. Afterwards, a portion of the dielectric layer430in the gate trench GT is removed using a selective etching process that etches the material of the dielectric layer430(e.g., silicon oxide) faster than other materials on the substrate300. In some embodiments, other portions of the dielectric layer430in the NFET region310except for the gate trench GT between the gate spacers451are covered by a photoresist mask (not shown) formed using suitable photolithography techniques, so that the dielectric layer430can remain on the NFET region310except for the region between the gate spacers451. Once the portion of the dielectric layer430between the gate spacers451have been removed, the photoresist mask can be removed, for example, in an ashing step, such as using oxygen plasma.

Thereafter, the n-doped sacrificial layers412,414and416and the buffer layer401in the gate trench GT are removed by a selective etching process, thus forming openings among the channel layers413,415and the substrate300. In this way, channel regions413CH, and415CHof the channel layers413and415become suspended over the substrate300. Details of the selective etching process (interchangeably referred to as channel release process) have been discussed previously with respect toFIGS.12A and12Band are thus not repeated for the sake of brevity.

Once the channel release process is complete, a high-k/metal gate structure460is formed within the openings provided by the release of nanosheets413and415. The resulting structure is illustrated inFIG.25. In various embodiments, the high-k/metal gate structure460includes a gate dielectric layer461formed around the nanosheets413and415, an n-type work function metal (also referred to as N-metal) layer462formed over the gate dielectric layer461, and a fill metal463formed over the work function metal layer461. The gate dielectric layer461includes an interfacial layer and a high-k dielectric layer formed over the interfacial layer. Detailed materials and fabrication of the interfacial layer, the high-k dielectric layer and the fill metal463have been discussed previously with respect toFIGS.13A and13Band are thus not repeated for the sake of brevity. The n-type work function metal layer462may exemplarily include, but are not limited to, titanium aluminide (TiAl), titanium aluminium nitride (TiAlN), carbo-nitride tantalum (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and/or other suitable materials.

Next, a top portion of the fill metal463over the fin structure FS1is patterned into a metal pad463P by using a selective etching process that etches the fill metal463at a faster rate than etching the n-type work function metal layer462. The resulting structure is illustrated inFIG.26. In some embodiments, the metal pad463P has a sidewall aligned with a vertical interface between the gate dielectric layer461and the sacrificial layer416.

Afterwards, the mask layer ML2is removed from the PFET region320, and then the process steps similar to that illustrated inFIGS.25and26are performed on the PFET region320to form a high-k/metal gate structure470wrapping around each nanosheets423and425. The resulting structure is illustrated inFIG.27. For example, the process steps include, removing the dummy gate electrode442to form a gate trench between the gate spacers, removing a portion of the dielectric layer430in the gate trench, releasing the channel regions423CHand425CHof the nanosheets423and425by selective etching the sacrificial layers422,424and426, and the buffer layer401that are exposed by the gate trench, forming a high-k/metal gate structure470including a gate dielectric layer471, a p-type work function metal layer472and a fill metal473in the openings provided by the release of nanosheets413and415, and then patterning a top portion of the fill metal473into a metal pad473P.

The gate dielectric layer471includes an interfacial layer and a high-k dielectric layer formed over the interfacial layer. Detailed materials and fabrication of the interfacial layer, the high-k dielectric layer and the fill metal473have been discussed previously with respect toFIGS.13A and13Band are thus not repeated for the sake of brevity. The p-type work function metal layer472may exemplarily include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and/or other suitable materials.

Next, an annealing process AL2is performed to diffuse the n-type impurity (e.g., phosphorous) from the heavily doped sacrificial layers412,414,416into source/drain regions413SDand415SDof the nanosheets413and415, and to diffuse the p-type impurity (e.g., boron) from the heavily doped sacrificial layers422,424,426into source/drain regions423SDand425SDof the nanosheets423and425. The annealing process AL2may be, for example, a rapid thermal anneal (RTA) or the like. The sacrificial layers412′,414′, and416′ after the annealing process AL2have a lower n-type impurity concentration that the sacrificial layers412,414, and416before the annealing process AL2. Similarly, the sacrificial layers422′,424′, and426′ after the annealing process AL2have a lower p-type impurity concentration that the sacrificial layers412,414, and416before the annealing process AL2.

Because the sacrificial layers412′,414′, and416′ and the source/drain regions413SDand415SDof the resulting nanosheets413′ and415′ are n-doped, they can be in combination referred to as source/drain regions of an n-type GAA FET. As a result, the sacrificial layers412′,414′, and416′ can be referred to as n-type source/drain layers. Similarly, because the sacrificial layers422′,424′, and426′ and the source/drain regions423SDand425SDof the resulting nanosheets423′ and425′ are p-doped, they can be in combination referred to as source/drain regions of an p-type GAA FET. As a result, the sacrificial layers422′,424′, and426′ can be referred to as p-type source/drain layers.

Because the channel regions413CHand415CHof the nanosheets413and415are surrounded by the gate structure460and thus spaced apart from the heavily doped layers412,414and416, and the channel regions423CHand425CHof the nanosheets423and425are surrounded by the gate structure470and thus spaced from the heavily doped layers422,424and426, the source/drain regions413SDand415SDof the nanosheets413′ and415′ have a greater n-type impurity concentration than that of the channel regions413CHand415CHof the nanosheets413′ and415′, and the source/drain regions423SDand425SDof the resulting nanosheets423′ and425′ have a greater p-type impurity concentration than that of the channel regions423CHand425CHof the nanosheets423′ and425′.

Next, as illustrated inFIG.29, source/drain contact openings OP1are formed through the n-type work function metal layer462, the gate dielectric layer461, and the dielectric layer430to the source/drain regions of the n-type GAA FET (e.g., to the n-type source/drain layer416′), and source/drain contact openings OP2are formed through the p-type work function metal layer472, the gate dielectric layer471, and the dielectric layer430to the source/drain regions of the p-type GAA FET (e.g., to the p-type source/drain layer426′). The source/drain contact openings OP1and OP2are formed using suitable photolithography and etching techniques.

Afterwards, an annealing process AL3is performed to activate the n-type impurities in the sacrificial layers412′,414′, and416′ and the source/drain regions413SDand415SDof the resulting nanosheets413′ and415′, and to activate the p-type impurities in the sacrificial layers422′,424′, and426′ and the source/drain regions423SDand425SDof the resulting nanosheets423′ and425′. In some specific embodiments, the annealing process AL3includes irradiating the source/drain regions of the n-type GAA FET and p-type GAA FET with radiation from a radiation source. In some embodiments, the radiation source is a laser or a flash lamp, including argon and xenon flash lamps. The layer stacks are exposed to the radiation for a period of time ranging from greater than 0 s to about 90 ms. In particular, regions of the layer stacks exposed by the source/drain contact openings OP1and OP2are exposed for a period of time ranging from greater than 0 s to about 90 ms, such as about 2 ns to about 0.8 ms. During the exposure to radiation, the exposed portions of the layer stacks undergo ultra-rapid heating and reach temperatures of up to 1800° C. In some other embodiments, the exposed portions of the layer stacks reach temperatures up to 1050° C. Channel regions413CHand415CHcovered by the gate structure460and channel regions423CHand425CHcovered by the gate structure470are not substantially heated because the metal pads463P and the metal pads473P reflects the radiation.

In some embodiments, the power density of the radiation is about 2 mJ/cm2to about 850 mJ/cm2. In some embodiments, the radiation is laser radiation from a laser. In some embodiments, the wavelength of the laser radiation ranges from about 170 nm to about 2200 nm. In other embodiments, the wavelength used in the irradiation by the laser is about 198 nm to about 1880 nm (λ=1878 nm is equivalent to the bandgap of Ge). In certain embodiments, a laser beam having a wavelength of about 532 nm is used. In some embodiments, the power density used in laser annealing is about 2 mJ/cm2to about 850 mJ/cm2. In certain embodiments, the power density of the radiation ranges from about 260 mJ/cm2to about 290 mJ/cm2. In certain embodiments, dynamic surface annealing occurs during the exposure to radiation. In dynamic surface annealing, the activation of the doped source/drain regions occurs without diffusion of the dopants. Therefore, the channel regions413CHand415CHof the nanosheets413and415, and the channel regions423CHand425CHof the nanosheets423and425remain substantially un-doped after the annealing process AL3. In some embodiments, the full-width-at-half-maximum (FWHM) of the laser pulse is about 2 ns to about 0.5 ms. A particular spot on the layer stacks is exposed to the laser beam from about 15 ns to about 95 μs in some embodiments. The shape of laser beam can be any shape including linear, elliptical, circular, etc.

In certain embodiments, the laser radiation has a wavelength in a range from about 530 nm to about 550 nm, and the fluence of the laser radiation ranges from about 15 to about 75 mJ/cm2. Because the metal pads463P and473P blocks and/or reflects the laser radiation, the source/drain regions of the layer stack are selectively irradiated with the laser radiation. The irradiation can be performed in ambient air, clean dry air, N2, N2+H2, H2, or inert gas (e.g. —He, Ne, and Ar).

Afterwards, source/drain contacts481and482are formed in the openings OP1and OP2respectively by using, for example, a lift-off process. The resulting structure is illustrated inFIG.30. By way of example and not limitation, the lift-off process includes coating photoresist on the substrate300, patterning the photoresist to expose the openings OP1and OP2, sputtering metal materials (e.g., copper, tungsten, nickel, cobalt, gold or other suitable metals) of the contacts481and482onto bottom surfaces of the openings OP1and OP2, and then removing the photoresist by an ashing process.

FIG.31is a graph illustrating a simulation result showing uniaxial tensile strain in the nanosheets413and415in the NFET region310after the channel release process is performed, wherein the uniaxial tensile strain is shown on the vertical axis inFIG.31, and the lateral distance from centers of channel regions (e.g., center of channel region415CHor413CH) is shown on the horizontal axis inFIG.31. InFIG.31, the curve C5represents uniaxial tensile strain in the upper nanosheet415, and the curve C6represents uniaxial tensile strain in the lower nanosheet413. The curve C5shows that the channel region415CHof the nanosheet415has a greater tensile strain than the source/drain region415SDof the nanosheet415, and curve C6shows that the channel region413CHof the nanosheet413has a greater tensile strain than the source/drain region413SDof the nanosheet413. Moreover, comparing the curve C5with the curve C6, the channel region415CHof the upper nanosheet415has a greater tensile strain than the channel region413CHof the lower nanosheet413. In some embodiments, the channel region415CHof the nanosheet415and channel region413CHof the nanosheet413have a tensile strain in a range from about 0.24% to about 0.65% (e.g., about 0.27%).

FIGS.32-34show exemplary sequential processes for manufacturing a GAA FET according to some embodiments of the present disclosure. It is understood that additional operations can be provided before, during, and after processes shown byFIGS.32-34, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable.FIGS.32-34illustrate a cross-sectional view along Y-direction corresponding to the line A-A illustrated inFIG.1.

FIG.32illustrates a patterning process performed on the gate structures460,470and the dielectric layer430, after the annealing process AL2as shown inFIG.28is performed. The patterning process is performed using suitable photolithography and etching techniques. The patterned gate structure460′, including the patterned gate dielectric layer461′, the patterned n-type work function metal layer462′ and the patterned fill metal463′, non-overlaps with the top surface of the n-type source/drain layer416′. The resulting gate structure470′, including the patterned gate dielectric layer471′, the patterned p-type work function metal layer472′ and the patterned fill metal473′, non-overlaps with the top surface of the p-type source/drain layer426′.

Next, as illustrated inFIG.33, the annealing process AL3is performed to activate the activate the n-type impurities in the sacrificial layers412′,414′, and416′ and the source/drain regions413SDand415SDof the resulting nanosheets413′ and415′, and to activate the p-type impurities in the sacrificial layers422′,424′, and426′ and the source/drain regions423SDand425SDof the resulting nanosheets423′ and425′, as discussed previously with respect toFIG.29.

Afterwards, as illustrated inFIG.34, source/drain contacts481and482are respectively formed on the n-type source/drain layer416′ and the p-type source/drain layer426′ by using, for example, a lift-off process as discussed previously with respect toFIG.30.

FIG.35illustrates a method M2of forming a GAA FET in accordance with some embodiments. Although the method M1is illustrated and/or described as a series of acts or events, it will be appreciated that the method is not limited to the illustrated ordering or acts. Thus, in some embodiments, the acts may be carried out in different orders than illustrated, and/or may be carried out concurrently. Further, in some embodiments, the illustrated acts or events may be subdivided into multiple acts or events, which may be carried out at separate times or concurrently with other acts or sub-acts. In some embodiments, some illustrated acts or events may be omitted, and other un-illustrated acts or events may be included.

At block S201, a buffer layer is formed on an NFET region and a PFET region.FIGS.17and18illustrate a cross-sectional view of some embodiments corresponding to acts in block S201.

At block S202, a first layer stack of alternating n-doped sacrificial layers and NFET channel layers is formed on the NFET region, and a second layer stack of alternating p-doped sacrificial layers and PFET channel layers is formed on the PFET region.FIGS.19and20illustrate a cross-sectional view of some embodiments corresponding to acts in block S202.

At block S203, the first layer stack is patterned into a first fin structure and the second layer stack is patterned into a second fin structure. At block S204, a dielectric layer is formed over the first and second fin structure.FIG.21illustrates a cross-sectional view of some embodiments corresponding to acts in blocks S203and S204.

At block S205, first and second dummy gate electrodes are formed over the first and second fin structures respectively.FIG.22illustrates a cross-sectional view of some embodiments corresponding to act in block S205.

At block S206, gate spacers are formed on sidewalls of the first and second dummy gate electrodes.FIGS.23and24illustrate a cross-sectional view of some embodiments corresponding to act in block S206.

At block S207, the first dummy gate electrode is removed, channel regions of the NFET channel layers are released, and a high-k/metal gate stack is formed around the released channel regions.FIGS.25and26illustrate a cross-sectional view of some embodiments corresponding to act in block S207.

At block S208, the second dummy gate electrode is removed, channel regions of the PFET channel layers are released, and a high-k/metal gate stack is formed around the released channel regions.FIG.27illustrates a cross-sectional view of some embodiments corresponding to act in block S208.

At block S209, n-type impurity is diffused from n-doped sacrificial layers into source/drain regions of the NFET channel layers and p-type impurity is diffused from p-doped sacrificial layers into source/drain regions of the PFET channel layers to form source/drain regions of n-type GAA FET and p-type GAA FET.FIG.28illustrates a cross-sectional view of some embodiments corresponding to act in block S209.

At block S210, source/drain regions of the n-type GAA FET and the p-type GAA FET are irradiated by laser.FIG.29illustrates a cross-sectional view of some embodiments corresponding to act in block S210.

Based on the above discussions, it can be seen that the present disclosure offers advantages. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. One advantage of some embodiments is that atomic ratio (e.g., germanium-to-silicon atomic ratio) difference among the regrown source/drain layers in source/drain stressors can be tuned to reduce the strain mismatch among the semiconductor nanosheets. Another advantage of some embodiments is that the strained channels can be realized by a layer stack of alternating semiconductor layers having different lattice constants, and thus the regrown source/drain stressors can be omitted in such embodiments.

In some embodiments, a method includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate; forming a dummy gate structure across the fin structure; etching portions of the fin structure that extend laterally beyond the dummy gate structure to expose portions of the substrate; forming source/drain stressors over the exposed portions of the substrate; after forming the source/drain stressors, removing the dummy gate structure; after removing the dummy gate structure, removing the first semiconductor layers such that the second semiconductor layers are suspended between the source/drain stressors; and forming a gate structure to surround each of the suspended second semiconductor layers. Forming the source/drain stressors comprises forming a first source/drain layer over the exposed portions of the substrate, and forming a second source/drain layer over the first source/drain layer. An atomic concentration of a Group IV element or a Group V element in the second source/drain layer is greater than that in the first source/drain layer.

In some embodiments, a semiconductor device includes a plurality of nanosheets, source/drain stressors, and a gate structure. The nanosheets extend in a first direction above the semiconductor substrate and are arranged in a second direction substantially perpendicular to the first direction. The source/drain stressors are on either side of the nanosheets. Each of the source/drain stressors includes a first epitaxial layer and a second epitaxial layer over the first epitaxial layer. The first and second epitaxial layers are made of an alloy semiconductor of a first Group IV element and a second Group IV element having a lattice constant greater than that of the first group IV element, and an atomic ratio of the second Group IV element to the first Group IV element in the second epitaxial layer is greater than that in the first epitaxial layer. The gate structure wraps around each of the nanosheets.

A method includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, wherein a concentration of an impurity of a first conductivity type in the first semiconductor layers is greater than that in the second semiconductor layers, and the second semiconductor layers are made of a material having a lattice constant different than that of the first semiconductor layers; forming a dummy gate structure across the fin structure; forming gate spacers on opposite sidewalls of the dummy gate structure, respectively; removing the dummy gate structure to form a gate trench between the gate spacers; removing portions of the first semiconductor layers in the gate trench, such that channel regions of the second semiconductor layers are suspended above the substrate; forming a gate structure to surround each of the suspended channel regions; and after forming the gate structure, performing a first annealing process to diffuse the impurity of the first conductivity type from the first semiconductor layers into source/drain regions of the second semiconductor layers.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.