Patent ID: 12255166

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method.

Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.

Herein, the terms “around,” “about,” “substantial” usually mean within 20% of a given value or range, and better within 10%, 5%, or 3%, or 2%, or 1%, or 0.5%. It should be noted that the quantity herein is a substantial quantity, which means that the meaning of “around,” “about,” “substantial” are still implied even without specific mention of the terms “around,” “about,” “substantial.”

Embodiments for forming a semiconductor package structure are provided. The method for forming the semiconductor package structure may include forming a ductile via structure with lower hardness in an encapsulating material. During subsequent planarization process, a lateral extending portion of the ductile via structure is formed near the top surface of the via structure. Since the top surface of the via structure is enlarged, the landing area of redistribution layer structure may be increased. With ductile via structure, the via structure profile may be well controlled and electrical bridge defect and fail issue may be avoided.

FIGS.1A-1Oare cross-sectional representations of various stages of forming a semiconductor package structure10a, in accordance with some embodiments of the disclosure. A carrier substrate102is provided as shown inFIG.1Ain accordance with some embodiments. The carrier substrate102may provide temporary mechanical and structural support during subsequent processing steps. The carrier substrate102may include glass, silicon, silicon oxide, aluminum oxide, metal, the like, or a combination thereof. The carrier substrate102may include a metal frame.

Next, an adhesive layer104is formed over the carrier substrate102as shown inFIG.1Ain accordance with some embodiments. The adhesive layer104may made of glue or foil. The adhesive layer104may be made of a photosensitive material which is easily detached from the carrier substrate102by light irradiation. The adhesive layer104may be made of a heat-sensitive material.

Afterwards, a buffer layer106is formed over the adhesive layer104as shown inFIG.1Ain accordance with some embodiments. The buffer layer106may be a polymer-based layer. The buffer layer106may be made of a poly-p-phenylenebenzobisthiazole (PBO) layer, a polyimide (PI) layer, a solder resist (SR) layer, an Ajinomoto buildup film (ABF), a die attach film (DAF), other applicable materials, or combinations thereof. The adhesive layer104and the buffer layer106may be deposited or laminated over the carrier substrate102.

Afterwards, a seed layer108is formed over the buffer layer106as shown inFIG.1B, in accordance with some embodiments. The seed layer108may be made of metal, such as copper (Cu), titanium (Ti), copper alloy, titanium alloy, or combinations thereof. The seed layer108may be formed by a deposition process, such as chemical vapor deposition process (CVD), physical vapor deposition process (PVD), other applicable processes, or a combination thereof.

After the seed layer108is formed over the buffer layer106, a mask layer110is formed on the seed layer108, as shown inFIG.1Cin accordance with some embodiments. Openings112are formed in the mask layer110. As shown inFIG.1C, the seed layer108is exposed from the openings112. The openings112may define the position of the subsequently formed via structures. The mask layer110may be made of a photoresist material. The openings112may be formed by a patterning process. The patterning process may include a photolithography process and an etching process. The photolithography process may be soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing and drying (e.g., hard baking). The etching process may be a dry etching or a wet etching process.

Afterwards, the via structure114is formed in the mask layer110, as shown inFIG.1D, in accordance with some embodiments. The via structure114is filled into the opening112. The via structure114may be made of metal, such as copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), alloy thereof, or a combination thereof. The top-view shape of the via structure114may be rectangle, square, circle, or the like. The height of the via structure114may be determined by the thickness of the mask layer110. The via structure114may be formed by a plating process. In some embodiments, the plating chemicals of the via structure114include copper sulfate. In some embodiments, the via structure114is formed under a surface current density of about 0.5 ASD (amps/square decimeter) to about 20 ASD.

Afterwards, the mask layer110is removed, as shown inFIG.1Ein accordance with some embodiments. After the mask layer110is removed, the sidewalls and the top surface of the via structure114may be exposed. The seed layer108may be exposed from the via structure114. The mask layer110may be removed by an ashing process, other applicable processes, or a combination thereof.

Next, and an etching process is performed to remove a portion of seed layer108, as shown inFIG.1Fin accordance with some embodiments. During the etching process, the via structure114is used as a mask. As a result, the via structure114and the remaining seed layer108are referred to as through InFO vias (TIV). The via structure114and the seed layer108may be made of the same material, and therefore there may be no distinguishable interface between them.

Next, a chip116is disposed over the buffer layer106between the via structures114, as shown inFIG.1Gin accordance with some embodiments. The chip116may be formed beside the via structures114. As shown inFIG.1G, the chip116is formed over the buffer layer106by an adhesive layer118. The adhesive layer118may be a die attach film (DAF). The height of the via structure114may be higher than the height of the chip116.

Other device elements may be formed in the chip116. The device elements may include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high-voltage transistors, high-frequency transistors, p-channel and/or n channel field effect transistors (PFETs/NFETs), etc.), diodes, and/or other applicable elements. Various processes may be performed to form device elements, such as deposition, etching, implantation, photolithography, annealing, and/or other applicable processes.

FIGS.2-1and2-2are enlarged cross-sectional views of the chip116, in accordance with some embodiments. As shown inFIGS.2-1and2-2, the chip116includes a substrate120, a conductive pad122, a passivation layer124, a via structure126, and a first encapsulating material128.

As shown inFIGS.1G,2-1, and2-2, a conductive layer122is formed over the substrate120. The conductive layer122may be made of metal material such as aluminum (Al), copper (Cu), tungsten (W), gold (Au), other suitable materials, or a combination thereof. The conductive layer122may be deposited by an electroplating process, a sputtering process, another applicable process, or a combination thereof. Afterwards, multiple etching processes may be used to pattern the conductive layers122to form conductive pads122, as shown inFIGS.2-1and2-2.

Next, a passivation layer124may be conformally formed over the conductive pad122and the substrate120. The passivation layer124may be made of polymer material such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), silicone, acrylates, siloxane, other suitable materials, or a combination thereof. The passivation layer124may also include non-organic materials such as silicon oxide, un-doped silicate glass, silicon oxynitride, solder resist (SR), silicon nitride, silicon carbide, hexamethyldisilazane (HMDS), other suitable materials, or a combination thereof. The passivation layer124may be deposited by a chemical vapor deposition (CVD) process or a spin-on coating process.

Next, the passivation layer124may be patterned to form openings exposing the conductive pads122(not shown). The openings may be formed by photolithography and etching process. The photolithography process may include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, pattern exposure, post-exposure baking, photoresist development, and rinsing and drying (e.g., hard baking), etc. The etching process may include a dry etching process (e.g., reactive ion etching (RIE), anisotropic plasma etching method), a wet etching process, or a combination thereof.

Afterwards, the via structure126is formed in the opening over the conductive pads122, as shown inFIGS.2-1and2-2in accordance with some embodiments. The via structure126may be formed by a patterning process and a plating process.

The patterning processes for forming the via structure126may be the same as, or similar to, those used when forming the via structure114. For the purpose of brevity, the descriptions of these processes are not repeated herein. The via structure126may include copper, aluminum, electroless nickel immersion gold (ENIG), electroless nickel electroless palladium immersion gold (ENEPIG), other suitable materials, or a combination thereof. In some embodiments, the via structure126is made of copper.

In some embodiments, the plating chemical of the via structure126may include copper sulfate. The hardness of the via structure126may be controlled by the surface current density during the plating process. In some embodiments, the via structure126is formed under a surface current density of about 2 ASD to about 10 ASD. In this condition, the via structure126may be made of ductile copper, which has a hardness of about 0.5 Gpa to about 1.8 Gpa. If the surface current density is too great, the hardness of the via structure126may be too great, and there may be voids formed in the via structure126. If the surface current density is too less, the hardness of the via structure126may be too less, and the process time may be also too long.

In some embodiments, the via structure126is formed under a surface current density lower than the surface current density used when forming the via structure114. Therefore, the hardness of the via structure126may be lower than the hardness of the via structure114. In addition, the deposition rate of the via structure126may be lower than the deposition rate of the via structure114. Moreover, the sidewall of the top portion of the via structure114may be straight and there may be no lateral protruding portion of the via structure114.

Next, the first encapsulating material128is filled surrounding the via structure126, as shown inFIGS.2-1and2-2in accordance with some embodiments. The first encapsulating material128may include a molding compound, such as liquid epoxy, deformable gel, silicon rubber, or the like. The first encapsulating material128may provide mechanical support and electrical isolation to the via structure126, and protection to the active circuitry from the environment. The first encapsulating material128may be dispensed over the via structure126by a capillary flow process. Next, the first encapsulating material128may be cured by a thermal curing process, an infrared (IR) energy curing process, a UV curing process, or a combination thereof.

Afterwards, a second encapsulating material130is formed over the chip116and the via structures114and126, as shown inFIG.1Hin accordance with some embodiments. The second encapsulating material130covers the chip116and fills up the space between via structures114and the space between via structure114and the chip116. As shown inFIG.1H, the top surface of the second encapsulating material130is higher than the top surface of the via structure114and the top surface of the chip116.

The forming processes and material for forming the second encapsulating material130may be the same as, or similar to, those used when forming the first encapsulating material128. For the purpose of brevity, the descriptions of these processes are not repeated herein. The material of the first encapsulating material128and the second encapsulating material130may be the same.

After the second encapsulating material130is deposited, a planarization process is performed to expose the chip116and the via structure114, as shown inFIG.1I, in accordance with some embodiments of the disclosure. After the planarization process, the top surface of the chip116is substantially level with the top surface of the via structure114. As shown inFIG.1I, the first encapsulating material128is surrounded by the second encapsulating material130. The planarization process may include grinding process, a chemical mechanical polishing (CMP) process, an etching process, other applicable processes or combinations thereof.

Since the via structure126in the chip116is formed under a certain plating surface current density range, the via structure126may be made of ductile conductive material. In addition, the first encapsulating material128may also be malleable. Therefore, the shape of the via structure126in a cross-sectional view may be changed by the force of the planarization process. In some embodiments, the top surface of the via structure126is enlarged by the planarization process. In some embodiments as shown inFIGS.2-1and2-2, the via structure126has a lateral extending portion126enear the top surface of the via structure126embedded in the first encapsulating material128. As shown inFIGS.2-1and2-2, the lateral extending portion126eis at the top portion of the via structure126. With greater top surface area, it may be easier for landing the subsequently formed redistribution layer structure.

In some embodiments as shown inFIG.2-1, the lateral extending portion126ehas a curved sidewall. In some embodiments as shown inFIG.2-2, the lateral extending portion126ehas an inclined sidewall. In addition, the slope of the sidewall of the lateral extending portion126eand the slope of the sidewall of the bottom portion of the via structure126are different. In some embodiments, the slope of the sidewall of the lateral extending portion126eis less than the slope of the sidewall of the bottom portion of the via structure126.

As shown inFIGS.2-1and2-2, the first encapsulating material128surrounds the top portion of the via structure126after the planarization process. Therefore, adjacent via structures126are separated by the first encapsulating material128, providing electronic isolation between adjacent via structures126.

In some embodiments as shown inFIGS.2-1and2-2, since the top surface of the via structures126is enlarged by the planarization process, the width W1of the top surface of the via structure126is greater than the width W2of the bottom surface of the via structure126. Therefore, there is larger landing area of subsequently formed redistribution layer structure. In some embodiment, the width W1of the top surface of the via structure126is greater than the width W2of the bottom surface of the via structure126by less than 12 μm. If the difference of the width W1and the width W2is too great, the distance W3between adjacent via structures126at the top surface of the first encapsulating material128may not be enough, and it may cause a short-circuit.

In some embodiments as shown inFIGS.2-1and2-2, the ratio of the width W1of the top surface of the via structures126to the width W2of the bottom surface of the via structures126is in a range of about 1.1 to about 1.5. If the ratio of width W1to width W2is too great, the distance W3between adjacent via structures126at the top surface of the first encapsulating material128may not be enough, and it may cause a short-circuit. If ratio of the width W1and the width W2is too less, the landing area of subsequently formed redistribution layer structure may be not enough.

In some embodiments as shown inFIGS.2-1and2-2, the distance W3between adjacent via structures126at the top surface of the first encapsulating material128is in a range of about 4 μm to about 6 μm. If the distance W3is too great, the landing area of subsequently formed redistribution layer structure may be not enough. If the distance W3is too less, it may cause a short-circuit.

In some embodiments, the sum of the width W1of the top surface of the via structures126and the distance W3between adjacent via structures126at the top surface of the first encapsulating material128is less than 40 μm. If the sum of widths W1and W3is too great, it may not be necessary to control the shape of the lateral extending portion126eof the via structure126. In some embodiments, the sum of the width W2of the bottom surface of the via structure126and the distance W4between adjacent via structures126at the bottom surface of the first encapsulating material128is less than 40 μm. If the sum of widths W2and W4is too great, it may not be necessary to control the shape of the lateral extending portion126eof the via structure126.

In some embodiments as shown inFIGS.2-1and2-2, the ratio of the height of the lateral extending portion126eof the via structures126to the height of the bottom portion of the via structures126is in a range of about 0.1 to about 0.5. If the height ratio is too great, adjacent via structures126may merge and there may be an electrical failure. If the height ratio is too low, the landing area of the subsequently formed redistribution layer structure may be not large enough, and the process window for forming the redistribution layer structure may be not enough.

In some embodiments as shown inFIG.1I, the distance W3between adjacent via structures126at the top surface of the first encapsulating material128is less than the distance W5between adjacent via structures114. Therefore, the ductile conductive material may be only used for the via structures126, not for the via structures114. In this way, the profile of the via structures126may be well-controlled, and the process time may be saved.

Next, a redistribution layer (RDL) structure132is formed over the via structures126and114, and a polymer layer134is formed over the redistribution layer structure132as shown inFIG.1Jin accordance with some embodiments. The redistribution layer structure132may be electrically connected to the via structures126and114.

The redistribution layer structure132may be made of metal such as copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy, titanium (Ti), titanium alloy, tantalum (Ta), or tantalum alloy. The redistribution layer structure132may be formed by plating, electroless plating, sputtering or chemical vapor deposition (CVD). In some embodiments, the redistribution layer structure132and the via structure126are formed by the same material. In some embodiments, the redistribution layer structure132is made of copper.

In some embodiments, the redistribution layer structure132and the via structure126may be formed under different surface current densities. Therefore, the hardness of the redistribution layer structure132and the via structure126may be different. In some embodiments, the surface current density of forming the via structure126is lower than the surface current density of forming the redistribution layer structure132. Therefore, the hardness of the redistribution layer structure132is greater than the hardness of the via structure126. In some embodiments, the redistribution layer structure132has a hardness of about 1.8 Gpa to about 4 Gpa. With greater hardness of the redistribution layer structure132, the process time may be saved.

The polymer layer134may be made of polybenzoxazole (PBO), benzocyclobutene (BCB), silicone, acrylates, siloxane, or combinations thereof. The polymer layer134may be made of non-organic materials, such as silicon oxide, un-doped silicate glass, silicon oxynitride, solder resist (SR), silicon nitride, HMDS (hexamethyldisilazane).

As shown inFIGS.2-1and2-2, a polymer layer134ais formed between the via structure126and the redistribution layer structure132. Since the adjacent via structures126are separated by the first encapsulating layer128and the first encapsulating layer128is surrounding the via structures126, the polymer layer134ais in contact with the first encapsulating layer128.

The polymer layer134amay be formed first, and openings are formed in the polymer layer134aexposing the via structures126(not shown). Afterwards, the redistribution layer structure132may be conformally formed over the polymer layer134aand the sidewalls and the bottom surface of the opening in the polymer layer134a. Therefore, the redistribution layer structure132may be in contact with the via structures126and is electrically connected to the via structures126. Later, the polymer layer134may be formed in the opening and over the redistribution layer structure132.

The forming processes and material for forming the polymer layer134amay be the same as, or similar to, those used when forming the polymer layer134. For the purpose of brevity, the descriptions of these processes are not repeated herein. In some embodiments, the polymer layer134and the polymer layer134aare made of the same material.

Afterwards, openings may be formed in the polymer layer134, and the redistribution layer structure132may be exposed (not shown). The under bump metallurgy (UBM) layer135may be conformally formed in the openings, and electrical connector136is formed over the UBM layer135, as shown inFIG.1Kin accordance with some embodiments. The electrical connector136may include solder ball, metal pillar, other applicable connectors, or a combination thereof. The UBM layer135may have a solderable metal surface to serve as an interface between the electrical connector136and the redistribution layer structure132. The UBM layer135may be made of metal such as copper, nickel, titanium, tungsten, aluminum, other suitable conductive materials, or a combination thereof. The UBM layer135may be formed by plating, such as electroplating or electroless plating, other suitable process, or a combination thereof.

Afterwards, the carrier substrate102and the adhesive layer104are removed, and the structure ofFIG.1Kis flipped and attached to a carrier140, as shown inFIG.1L, in accordance with some embodiments of the disclosure. As a result, the buffer layer106may face up and be exposed. The carrier140may include a tape which is photosensitive or heat-sensitive and is easily detached from the electrical connector136.

Afterwards, a portion of the buffer layer106is removed to form opening142, as shown inFIG.1M, in accordance with some embodiments of the disclosure. A portion of the seed layer108may be removed, and the seed layer108may be exposed. The opening142may be formed by a laser drilling process, an etching process, or other applicable processes, or a combination thereof.

Afterwards, the semiconductor package structure as shown inFIG.1Mis detached from the carrier140, and a dicing process is performed to separate the semiconductor package structure into chip packages as shown inFIG.1N, in accordance with some embodiments of the disclosure.

Next, an electrical connector144is filled into the opening142, as shown inFIG.1O, in accordance with some embodiments of the disclosure. Afterwards, the top package146may be bonded to the electrical connector144. The top package146may include a package substrate148and semiconductor dies150. The semiconductor dies150may include memory dies, such as Static Random Access Memory (SRAM) die, Dynamic Random Access Memory (DRAM) die or the like.

By forming the via structure126with a ductile conductive material, the top surface of the via structure126may be enlarged by the planarization process. Therefore, a lateral extending portion126emay be formed near the top surface of the via structure126, and the landing area of the redistribution layer structure132may be enlarged. In addition, the profile of the via structure126may be well-controlled, and the bridge defect may be reduced and the electrical fail issue may be prevented.

Many variations and/or modifications may be made to the embodiments of the disclosure.FIGS.3A-3Care cross-sectional representations of various stages of forming a modified semiconductor package structure10b, in accordance with some embodiments of the disclosure. Some processes or devices are the same as, or similar to, those described in the embodiments above, and therefore the descriptions of these processes and devices are not repeated herein. The difference from the embodiments described above is that, as shown inFIG.3Ain accordance with some embodiments, the via structure114is formed under the same or similar surface current density as forming the via structure126.

In some embodiments as shown inFIG.3A, the via structure114is formed under a surface current density of about 2 ASD to about 10 ASD. In this condition, the via structure114may be made of ductile copper, which has a hardness of about 0.5 Gpa to about 1.8 Gpa. If the surface current density is too great, the hardness of the via structure114may be too great, and there may be a void forming in the via structure114. If the surface current density is too less, the hardness of the via structure114may be too less, and the process time may be too long.

In some embodiments, the via structure126and the via structure114are formed under the same or similar surface current density. Therefore, the hardness of the via structure126and the via structure114may be similar or the same.

Next, as shown inFIG.3B, after forming the second encapsulating material130over the via structures114and126, the planarization process is performed and the top surface of the via structures114and126are exposed. Since the via structure114is made of ductile conductive material, a lateral extending portion114eis formed after the planarization process. In some embodiments, the top surface of the via structure114is enlarged by the planarization process.

In some embodiments as shown inFIG.3B, the lateral extending portion114eis embedded in the second encapsulating material130. In some embodiments, adjacent via structures114are separated by the second encapsulating material130, preventing electrical fail issue.

Next, a redistribution layer structure132is formed over the via structures114and126, and the redistribution layer structure132is electrically connected to the via structures114and126, as shown inFIG.3C, in accordance with some embodiments of the disclosure. Since the top surface of the via structure114is enlarged, the landing area of the redistribution layer structure132may be enlarged. It may be easier to form redistribution layer structure132over the via structure114.

By forming the via structures114and126with a ductile conductive material, the top surface of the via structures114and126may be enlarged by the planarization process. Therefore, a lateral extending portions114eand126emay be formed near the top surface of the via structures114and126respectively, and the landing area of the redistribution layer structure132may be enlarged. In addition, the profile of the via structures114and126may be well-controlled, and the bridge defect may be reduced and the electrical fail issue may be prevented.

Many variations and/or modifications may be made to the embodiments of the disclosure.FIGS.4A-4Care cross-sectional representations of various stages of forming a modified semiconductor package structure10c, in accordance with some embodiments of the disclosure. Some processes or devices are the same as, or similar to, those described in the embodiments above, and therefore the descriptions of these processes and devices are not repeated herein. The difference from the embodiments described above is that, as shown inFIG.4Ain accordance with some embodiments, the via structure126is formed in two steps.

As shown inFIG.4A, the bottom portion126B and the top portion126T are formed under different surface current densities. In some embodiments, the bottom portion126B of the via structure126is formed under a surface current density of about 0.5 ASD to about 20 ASD. In some embodiments, the top portion126T of the via structure126is formed under a surface current density of about 2 ASD to about 10 ASD. In some embodiments, the surface current density of forming the bottom portion126B of the via structure126is greater than the surface current density forming the top portion126T of the via structure126. In some embodiments, the bottom portion126B and the top portion126T are formed at a different deposition rate. In some embodiments, the bottom portion126B is formed at a higher deposition rate than the top portion126T. In some embodiments, the hardness of the bottom portion126B and the top portion126T of the via structure126are different. In some embodiments, the hardness of the bottom portion126B is greater than the hardness of the top portion126T.

Next, after the second encapsulating material130is deposited, a planarization process is performed to expose the chip116and the via structure114, as shown inFIG.4B, in accordance with some embodiments of the disclosure. Since the top portion126T of the via structure126is made of ductile conductive material, a lateral extending portion126eof the top portion126T is formed after the planarization process. In some embodiments, the top surface of the top portion126T of the via structure126is enlarged by the planarization process.

Next, a redistribution layer structure132is formed over the via structures126, and the redistribution layer structure132is electrically connected to the via structure126, as shown inFIG.4C, in accordance with some embodiments of the disclosure. Since the top surface of the top portion126T of the via structure126is enlarged, the landing area of the redistribution layer structure132may be enlarged. It may be easier to form the redistribution layer structure132over the via structure126. In addition, the bottom portion126B may be formed with a faster deposition rate to save production time.

By forming the via structure126with a ductile conductive material, the top surface of the via structure126may be enlarged by the planarization process. Therefore, a lateral extending portion126emay be formed near the top surface of the via structure126, and the landing area of the redistribution layer structure132may be enlarged. In addition, the profile of the via structure126may be well-controlled, and the bridge defect may be reduced and the electrical fail issue may be prevented. The bottom portion126B and the top portion126T of the via structure126may be formed under different surface current densities. Therefore, the production time may be saved, and the landing area of the redistribution layer structure132may be enlarged at the same time.

Many variations and/or modifications may be made to the embodiments of the disclosure.FIGS.5A-5Bare cross-sectional representations of various stages of forming a modified semiconductor package structure10d, in accordance with some embodiments of the disclosure. Some processes or devices are the same as, or similar to, those described in the embodiments above, and therefore the descriptions of these processes and devices are not repeated herein. The difference from the embodiments described above is that, as shown inFIG.5Ain accordance with some embodiments, the redistribution layer structure132is formed under the same or similar surface current density as forming the via structure126.

In some embodiments as shown inFIG.5A, the redistribution layer structure132is formed under a surface current density of about 2 ASD to about 10 ASD. In this condition, the redistribution layer structure132may be made of ductile copper, which has a hardness of about 0.5 Gpa to about 1.8 Gpa. If the surface current density is too great, the hardness of the redistribution layer structure132may be too great, and there may be a void forming in redistribution layer structure132. If the surface current density is too less, the hardness of redistribution layer structure132may be too less, and the process time may be too long.

In some embodiments, the via structure126and the redistribution layer structure132are formed under the same or similar surface current density. Therefore, the hardness of the via structure126and the redistribution layer structure132may be similar or the same. In this way, the redistribution layer structure132may be made of ductile conductive material.

Since the planarization of the second encapsulating layer130is performed before the planarization redistribution layer structure132, the top surface area of the redistribution layer structure132may remain the same in the following process. With ductile redistribution layer structure132, the landing process window may be improved, and the resistance may be reduced.

By forming the via structure126with a ductile conductive material, the top surface of the via structure126may be enlarged by the planarization process. Therefore, a lateral extending portion126emay be formed near the top surface of the via structure126, and the landing area of the redistribution layer structure132may be enlarged. In addition, the profile of the via structure126may be well-controlled, and the bridge defect may be reduced and the electrical fail issue may be prevented. By forming the redistribution layer structure132by the ductile conductive material, the landing process window may be improved, and the resistance may be reduced.

As described previously, forming the via structures126by a ductile conductive material may enlarge the top surface of the via structures126after the planarization process. It may be easier to land the redistribution layer structure132. The profile of the via structure126may be well-controlled by the ductile conductive material, and the bridge defect may be reduced and the electrical fail issue may be prevented when the distance between the via structures is small. In the embodiments as shown inFIGS.3A-3C, the via structures114beside the chip116are also made of ductile conductive material, and the top surface of the via structures114beside the chip116are also enlarged after the planarization process. It may be easier to land the redistribution layer structure132over the via structures114beside the chip116. In the embodiments as shown inFIGS.4A-4C, the top portion of the via structures126is made of ductile conductive material and the hardness of the top portion of the via structures126is lower than the bottom portion of the via structures126. It may be easier to land the redistribution layer structure132and save production time. In the embodiments as shown inFIGS.5A-5B, the redistribution layer structure132is made of ductile conductive material with lower hardness. The landing process window may be improved, and the resistance may be reduced.

Embodiments of a semiconductor package structure and a method for forming the same are provided. The semiconductor package structure may include via structures made of conductive material with lower hardness. It may be easier to land the redistribution layer structure over the via structure, and the via structure profile may be well-controlled. Furthermore, the bridge defect may be reduced and the electrical fail issue may be prevented.

In some embodiments, a semiconductor package structure is provided. The semiconductor package structure includes a conductive pad formed over a substrate. The semiconductor package structure also includes a passivation layer formed over the conductive pad. The semiconductor package structure also includes a first via structure formed through the passivation layer and in contact with the conductive pad. The semiconductor package structure also includes a first encapsulating material surrounding the first via structure. The semiconductor package structure also includes a redistribution layer structure formed over the first via structure. The first via structure has a lateral extending portion embedded in the first encapsulating material near the top surface of the first via structure.

In some embodiments, a semiconductor package structure is provided. The semiconductor package structure includes a chip including first via structures over a substrate. The semiconductor package structure also includes second via structures formed beside the chip. The semiconductor package structure also includes a redistribution layer structure formed over the first via structures and the second via structures. The first via structures comprise a top portion and a bottom portion. The slope of the sidewall of the top portion of the first via structures is different than the slope of the sidewall of the bottom portion of the first via structures.

In some embodiments, a method for forming a semiconductor package structure is provided. The method for forming a semiconductor package structure includes forming a conductive pad over a substrate. The method for forming a semiconductor package structure also includes conformally depositing a passivation layer over the conductive pad. The method for forming a semiconductor package structure also includes patterning the passivation layer to form an opening exposing the conductive pad. The method for forming a semiconductor package structure also includes forming a first via structure in the opening over the conductive pad. The method for forming a semiconductor package structure also includes depositing a first encapsulating material surrounding the first via structure. The method for forming a semiconductor package structure also includes planarizing the first encapsulating material to expose the top surface of the first via structure. The top surface of the first via structure is enlarged by planarizing the first encapsulating material. The method for forming a semiconductor package structure also includes forming a redistribution layer structure electrically connected to the first via structure.

In some embodiments, a semiconductor package structure is provided. The semiconductor package structure includes a conductive pad formed over a substrate. The semiconductor package structure also includes a passivation layer formed over the conductive pad. The semiconductor package structure further includes a first via structure formed through the passivation layer and in contact with the conductive pad. The semiconductor package structure also includes a first encapsulating material surrounding the first via structure. The semiconductor package structure further includes a redistribution layer structure formed over the first via structure. The first via structure has a lateral extending portion embedded in the first encapsulating material near a top surface of the first via structure, and the lateral extending portion has a width increasing in a direction toward the redistribution layer structure.

In some embodiments, a semiconductor package structure is provided. The semiconductor package structure includes a chip including first via structures over a substrate. The semiconductor package structure also includes second via structures formed beside the chip. The semiconductor package structure further includes a redistribution layer structure formed over the first via structures and the second via structures. Each of the first via structures includes a top portion and a bottom portion, and a slope of a sidewall of the top portion of the first via structures and a slope of a sidewall of the bottom portion of the first via structures are different.

In some embodiments, a semiconductor package structure is provided. The semiconductor package structure includes a conductive pad formed over a substrate. The semiconductor package structure also includes an electrical connector formed below the substrate. The semiconductor package structure further includes a first via structure electrically connected to the conductive pad. The semiconductor package structure also includes a first encapsulating material surrounding the first via structure. A top portion of the first encapsulating material is partially covered by the first via structure. The semiconductor package structure further includes a second via structure adjacent to the substrate and electrically connected to the electrical connector. The semiconductor package structure also includes a redistribution layer structure electrically connected to the first via structure and the second via structure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.