Patent ID: 12193343

DETAILED DESCRIPTION

Hereinafter in the specifications (and not in the claims necessarily), a direction substantially perpendicular to an upper surface of a substrate may be defined as a first direction D1, and two directions substantially parallel to the upper surface of the substrate and crossing each other may be defined as second and third directions D2and D3, respectively. In example embodiments, the second and third directions D2and D3may be substantially perpendicular to each other.

It will be understood that, although the terms “first,” “second,” and/or “third” may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section, and do not imply or require sequential inclusion.

FIGS.1to3are a plan view and cross-sectional views of a vertical variable resistance memory device in accordance with example embodiments.FIG.4illustrates graphs of a resistance of a gate electrode in accordance with a Comparative Example and a resistance of a gate electrode in accordance with an Example.FIG.1is the plan view,FIG.2is a cross-sectional view taken along a line A-A′ ofFIG.1, andFIG.3is a cross-sectional view taken along a line B-B′ ofFIG.1.

Referring toFIGS.1to3, the vertical variable resistance memory device may include a gate electrode125, first and second insulation patterns115and195, and a pillar structure170on a substrate100. In an implementation, the vertical variable resistance memory device may include first and second contact plugs200and205, first and second wirings220and225, and first to third insulating interlayers130,180and210.

The substrate100may include silicon, germanium, silicon-germanium or a III-V compound such as GaP, GaAs, GaSb, or the like. In an implementation, the substrate100may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate. As used herein, the term “or” is not an exclusive term, e.g., “A or B” would include A, B, or A and B.

In an implementation, the substrate100may include a first region I and a second region II at least partially surrounding the first region I. The first region I may be a cell region on which memory cells may be formed, and the second region II may be an extension region or a pad region on which contact plugs for transferring electrical signals to the memory cells may be formed.

In an implementation, a plurality of gate electrodes125may be spaced apart from each other in the first direction D1on the first and second regions I and II of the substrate100to form a gate electrode structure, and each of the gate electrodes125may extend (e.g., lengthwise) in the second direction D2. The gate electrodes125may be stacked in a staircase shape in which extension lengths of the gate electrodes125decrease from a lowermost level toward an uppermost level (e.g., a length of a gate electrode125proximate to the substrate100may be greater than a length of a gate electrode distal to the substrate100).

Hereinafter, a portion of each of the gate electrodes125not overlapped with an upper gate electrode125, e.g., each of opposite end portions in the second direction D2of each of the gate electrodes125, may be referred to as a pad.

In an implementation, a plurality of gate electrode structures may be spaced apart from each other in the third direction.

In an implementation, each of the gate electrodes125in each of the gate electrode structures may serve as one of a ground selection line (GSL), a word line, and a string selection line (SSL). In an implementation, a lowermost one of the gate electrodes125may serve as the GSL, an uppermost one and a second one from above of the gate electrodes125may serve as the SSL, and other ones of the gate electrodes125may serve as the word line.

In an implementation, each of the gate electrodes125may include graphene.

The first insulation patterns115may be between the gate electrodes125(spaced apart from each other in the first direction D1) in each gate electrode structure, and may contact (e.g., directly contact) the gate electrodes125. Each of the first insulation patterns115and one of the gate electrodes125directly thereon may form a “step layer,” and extension lengths in the second direction D2of the first insulation patterns115, which may correspond to the extension lengths of the gate electrodes125, respectively, may decrease in a stepwise manner from a lowermost level toward an uppermost level.

In an implementation, the first insulation pattern115and the gate electrode125stacked in the first direction D1may form a “step layer,” a plurality of step layers may be stacked in the first direction D1to form a mold having a staircase shape, and a plurality of molds may be spaced apart from each other in the third direction D3on the substrate100. A portion of each step layer in each mold not overlapped with upper step layers, e.g., each opposite end portions in the second direction D2of each step layer may be referred to as a “step.” In an implementation, the steps of each mold may be on the second region II of the substrate100.

In an implementation, the second insulation patterns195may be between the molds, and may contact (e.g., directly contact) opposite sidewalls in the third direction D3of the molds. In an implementation, the second insulation pattern195may contact opposite sidewalls in the third direction D3of the gate electrodes125and the first insulation patterns115in each mold.

In an implementation, the second insulation pattern195may extend (e.g., lengthwise) in the second direction D2on the first and second regions I and II of the substrate100, and may separate the molds disposed in the third direction D3from each other. Thus, an extension length in the second direction D2of the second insulation pattern195may be greater than or equal to an extension length in the second direction D2of a step layer having a maximum length among the step layers in each mold.

In an implementation, the extension length in the second direction D2of the second insulation pattern195may be greater than or equal to an extension length in the second direction D2of a lowermost one of the gate electrodes125. In an implementation, the second insulation pattern195may be between the molds, and may protrude from the molds in the second direction D2at an upper level where an extension length in the second direction D2of the step layer is relatively small.

In an implementation, an upper surface (e.g., surface facing away from the substrate100in the first direction D1) of the second insulation pattern195may be higher than upper surfaces of the molds, e.g., upper surfaces of the gate electrode structures included in the molds.

In an implementation, a lower surface and sidewalls in the third direction D3of the gate electrodes125(except for an uppermost one thereof included in each mold) may be covered by the first and second insulation patterns115and195.

In an implementation, each of the first and second insulation patterns115and195may include boron nitride BN. In an implementation, each of the first and second insulation patterns115and195may include hexagonal boron nitride (h-BN), which is a two-dimensional material. In an implementation, each of the first and second insulation patterns115and195may include amorphous boron nitride (a-BN).

The first and second insulation patterns115and195may include substantially the same material, and may be merged with each other.

The pillar structure170may extend (e.g., lengthwise) in the first direction D1on the first region I of the substrate100through the mold, e.g., the gate electrodes125and the first insulation patterns115. In an implementation, a plurality of pillar structures170may be spaced apart from each other in each of the second and third directions D2and D3. In an implementation, the pillar structures170extending through each mold may be spaced apart in the second direction D2, the molds may be formed in the third direction D3, and the pillar structures170may be also spaced apart in the third direction D3correspondingly. In an implementation, the pillar structure170may have a circular shape in a plan view.

The pillar structure170may include a vertical electrode160extending in the first direction D1and a variable resistance pattern150covering a sidewall and a lower surface of the vertical electrode160.

In an implementation, the vertical electrode160may include graphene.

In an implementation, the variable resistance pattern150may include a material in which an electrical path, e.g., a filament may be generated by a difference between voltages applied to respective opposite ends of the variable resistance pattern150. In an implementation, the filament may be generated by oxygen vacancy due to the movement of oxygen included in the variable resistance pattern150. In an implementation, the variable resistance pattern150may include a perovskite material or a transition metal oxide (TMO).

The perovskite material may include, e.g., STO (SrTiO3), BTO (BaTiO3), PCMO (Pri1-xCaxMnO3), or the like. The TMO may include, e.g., titanium oxide (TiOx), zirconium oxide (ZrOx), aluminum oxide (AlOx), hafnium oxide (HfOx), tantalum oxide (TaOx), niobium oxide (NbOx), cobalt oxide (CoOx), tungsten oxide (WOO, lanthanum oxide (LaOx), zinc oxide (ZnOx), or the like. These may be used alone or in a combination thereof.

In an implementation, the variable resistance pattern150may include a single layer or a composite layer having a plurality of single layers sequentially stacked.

The first contact plug200may extend in the first direction D1on the second region II of the substrate100to contact a pad of each of the gate electrodes125, and the second contact plug205may extend in the first direction D1on the first region I of the substrate100to contact an upper surface of each of the vertical electrodes160.

The first wiring220may extend in the second direction D2on the second region II of the substrate100to contact upper surfaces of the first contact plugs200, and the second wiring225may extend in the third direction D3on the first region I of the substrate100to contact upper surfaces of the second contact plugs205.

In an implementation, a plurality of first wirings220corresponding to the gate electrode structures may be spaced apart in the third direction D3, and a plurality of second wirings225corresponding to the vertical electrodes160may be spaced apart in the second direction D2. The first wiring220may apply electrical signals to the gate electrodes125serving as the word line, the GSL and the SSL, respectively, and the second wiring225may serve as a bit line.

The first and second contact plugs200and205and the first and second wirings220and225may include, e.g., a metal, a metal nitride, a metal silicide, doped polysilicon, or the like.

The first to third insulating interlayers130,180and210may be sequentially stacked in the first direction D1on the substrate100. The first insulating interlayer130may cover sidewalls and upper surfaces of the molds. The first contact plug200may extend through the first and second insulating interlayers130and180, and the second contact plug205may extend through the second insulating interlayer180. The first and second wirings220and225may extend through the third insulating interlayer210. The first to third insulating interlayers130,180and210may include an oxide, e.g., silicon oxide.

In the vertical variable resistance memory device, each of the gate electrode125and the vertical electrode160may include graphene instead of a metal, and thus may have thicknesses and widths that may be much smaller than those of other gate electrodes and vertical electrodes.

The gate electrode125may have a small thickness, e.g., in a range of about 0.3 nm to about 10 nm, an upper surface of the gate electrode structure including the gate electrodes125may be lowered, and forming a hole140for forming the pillar structure170extending through the gate electrode structure may be facilitated.

The first insulation pattern115between the gate electrodes125including graphene may include, e.g., boron nitride such as h-BN instead of silicon oxide, and a surface roughness between the gate electrodes125and the first insulation pattern115may decrease, which may cause enhancement of electrons in the gate electrodes125.

Referring toFIG.4, a resistance of each of the gate electrodes including graphene when the insulation pattern between the gate electrodes includes h-BN may be much smaller than a resistance of each of the gate electrodes including graphene when the insulation pattern between the gate electrodes includes h-BN includes silicon oxide, which means that the mobility of electrons in each gate electrode may be remarkably enhanced.

In an implementation, the first insulation pattern115may have a small thickness, e.g., in a range of about 0.3 nm to about 10 nm, which may be distinguished from an insulation pattern including silicon oxide and having a much larger thickness, in order to prevent the leakage current. Not only the gate electrodes125but also the first insulation patterns115may have the small thickness, and the formation of the hole140for forming the pillar structure170may be facilitated.

The vertical electrode160may have a width, e.g., in a range of about 0.3 nm to about 10 nm, and the pillar structure170including the vertical electrode160may have a small width. As a result, the vertical variable resistance memory device including a plurality of pillar structures170may have an enhanced integration degree.

FIGS.5to14are plan views and cross-sectional views of stages in a method of manufacturing a vertical variable resistance memory device in accordance with example embodiments.FIGS.5,7,9and12are the plan views, andFIGS.6,8,10and13are cross-sectional views taken along lines A-A′ of corresponding plan views, respectively, andFIGS.11and14are cross-sectional views taken along lines B-B′ of corresponding plan views, respectively.

Referring toFIGS.5and6, a first insulation layer110and a gate electrode layer120may be alternately and repeatedly stacked on a substrate100including first and second regions I and II to form a mold layer.

A photoresist pattern partially covering an uppermost one of the gate electrode layers120may be formed on the uppermost one of the gate electrode layers120, and the uppermost one of the gate electrode layers120and an uppermost one of the first insulation layers110may be etched using the photoresist pattern as an etching mask. Thus, one of the gate electrode layers120under the uppermost one of the first insulation layers110may be partially exposed. A trimming process for reducing an area of the photoresist pattern may be performed, and the uppermost one of the gate electrode layers120, the uppermost one of the first insulation layers110, the exposed one of the gate electrode layers120, and one of the first insulation layers110thereunder may be etched again using the reduced photoresist pattern as an etching mask.

The etching process and the trimming process may be alternately and repeatedly performed to form a mold having a plurality of step layers each including the first insulation layer110and the gate electrode layer120sequentially stacked on the substrate100. A portion of each of the step layers not overlapped with upper step layers in the first direction D1, e.g., each of opposite end portions in the second direction D2of each of the step layers may be referred to as a “step.” In an implementation, a plurality of steps may be formed on the second region II of the substrate100.

Referring toFIGS.7and8, a first insulating interlayer130may be formed on the substrate100to cover the mold, and the first insulating interlayer130and the mold may be etched to form a hole140exposing an upper surface of the substrate100.

In example embodiments, a plurality of holes140may be formed in each of the second and third directions D2and D3on the first region I of the substrate100.

A variable resistance layer may be formed on a sidewall of the hole140, the exposed upper surface of the substrate100, and an upper surface of the first insulating interlayer130, and a vertical electrode layer may be formed on the variable resistance layer to fill the hole140.

The vertical electrode layer and the variable resistance layer may be planarized until an upper surface of the first insulating interlayer130is exposed, and may form a vertical electrode160and a variable resistance pattern150, respectively. The vertical electrode160extending in the first direction D1and the variable resistance pattern150covering a sidewall and a lower surface of the vertical electrode160may form a pillar structure170. In an implementation, a plurality of pillar structures170may be formed to be spaced apart in each of the second and third directions D2and D3on the first region I of the substrate100.

In an implementation, the planarization process may include a chemical mechanical polishing (CMP) process and/or an etch back process.

Referring toFIGS.9to11, a second insulating interlayer180may be formed on the first insulating interlayer130and the pillar structure170, and an opening190may be formed through the first and second insulating interlayers130and180and the mold to expose an upper surface of the substrate100by an etching process.

In an implementation, the opening190may extend in the second direction D2on the first and second regions I and II of the substrate100, and a plurality of openings190may be formed to be spaced apart in the third direction D3. In an implementation, the opening190may extend to each of opposite ends in the second direction D2of the mold, and the mold may be divided into a plurality of pieces in the third direction D3. The mold may have a staircase shape having an extension length in the second direction D2decreasing in a stepwise manner from a lowermost level toward an uppermost level, and an extension length in the second direction D2of the opening190may be equal to or greater than an extension length in the second direction D2of a lowermost one of the step layers in the mold.

As the opening190is formed, the first insulation layer110may be divided into first insulation patterns115each of which may extend in the second direction D2, and the gate electrode layer120may be divided into a plurality of gate electrodes125each of which may extend in the second direction D2.

A second insulation layer may be formed on the exposed upper surface of the substrate100and an upper surface of the second insulating interlayer180to fill the opening190, and may be planarized until the upper surface of the second insulating interlayer180is exposed to form a second insulation pattern195in the opening190.

In an implementation, the second insulation pattern195may include a material substantially the same as that of the first insulation pattern115. In an implementation, the second insulation pattern195may be merged with the first insulation pattern115.

Referring toFIGS.12to14, a first contact plug200(extending through the first and second insulating interlayers130and180to contact the gate electrode125), and a second contact plug205(extending through the second insulating interlayer180to contact the vertical electrode160) may be formed.

In an implementation, the first contact plug200may contact a pad of each of the gate electrodes125on the second region II of the substrate100, and thus a plurality of first contact plug200may be formed to be spaced apart from each other in each of the second and third directions D2and D3on the second region II of the substrate100.

In an implementation, the second contact plug205may contact the vertical electrode160of the pillar structure170on the first region I of the substrate100, and according to the arrangement of the pillar structure170, a plurality of second contact plugs205may be spaced apart from each other in each of the second and third directions D2and D3on the first region I of the substrate100.

Referring toFIGS.1to3again, a third insulating interlayer210may be formed on the second insulating interlayer180, and first and second wirings220and225extending through the third insulating interlayer210to contact upper surfaces of the first and second contact plugs200and205, respectively, may be formed. Thus, the fabrication of the vertical variable resistance memory device may be completed.

In an implementation, the first wiring220may extend in the second direction D2on the second region II of the substrate100, and a plurality of first wirings220may be spaced apart from each other in the third direction D3.

In an implementation, the second wiring225may extend in the third direction D3on the first region I of the substrate100, and a plurality of second wirings225may be spaced apart from each other in the second direction D2.

By way of summation and review, the mobility of electrons in gate electrodes deteriorated due to the surface roughness of insulation patterns between the gate electrodes. Additionally, insulation patterns may have a large thickness in order to prevent the leakage current, and the formation of holes for forming vertical electrodes penetrating through the gate electrodes and the insulation patterns may be difficult.

One or more embodiments may provide a vertical variable resistance memory device having improved characteristics.

In the vertical variable resistance memory device in accordance with example embodiments, the gate electrodes and the insulation patterns therebetween may include graphene and h-BN, respectively, and may have a relatively small thickness. Thus, process difficulty of formation of the vertical electrode extending through the gate electrodes and the insulation patterns may be reduced. Additionally, the gate electrode between the insulation patterns including h-BN may have a reduced resistance, and thus the mobility of electrons therein may be enhanced. Furthermore, the vertical electrode may include graphene, and it may have a small width, and thus the vertical variable resistance memory device may have an enhanced integration degree.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.