Patent ID: 12191881

DETAILED DESCRIPTION OF SOME EXAMPLE EMBODIMENTS

Hereinafter, some example embodiments according to the inventive concepts will be described with reference to the accompanying drawings.

FIG.1is a block diagram of a semiconductor device according to some example embodiments.

Referring toFIG.1, a semiconductor device10may include a sample circuit100, a comparator200, a control logic300, and a reference signal adjusting circuit400.

In some example embodiments, the semiconductor device10may be, for example, an analog-to-digital converter (ADC) that converts an analog input signal IS into a digital signal corresponding thereto. Specifically, the semiconductor device10may be, for example, a successive-approximation register (SAR) ADC that converts an analog input signal IS provided through a successive approximation method into a q-bit digital output signal (here, q is a natural number).

Hereinafter, some example embodiments will be described by taking an example of the case in which the semiconductor device10is an SAR ADC, but example embodiments are not limited thereto. In some other example embodiments, the semiconductor device10may be implemented as a type of ADC other than an SAR ADC, may be implemented as a type of semiconductor device10other than an ADC, etc.

Referring toFIG.1, the sample circuit100may receive the input signal IS and sample and hold the received input signal IS. Specifically, the sample circuit100may store the input signal IS using a predetermined storage device to provide the input signal IS to the comparator200.

The comparator200may compare the input signal IS with a reference signal RS and output a comparison signal CS on the basis of a result of the comparison. Specifically, the comparator200may compare a voltage level of the input signal IS with a voltage level of the reference signal RS and output the comparison signal CS on the basis of a result of the comparison.

When the voltage level of the input signal IS is higher than the voltage level of the reference signal RS, the comparator200may output a comparison signal CS having a first level, and when the voltage level of the input signal IS is lower than the voltage level of the reference signal RS, the comparator200may output a comparison signal CS having a second level different from the first level. The detailed configuration of the comparator200will be described below in more detail.

The control logic300may receive the comparison signal CS from the comparator200and determine a bit value of the digital signal corresponding to the input signal IS on the basis of the received comparison signal CS. Further, the control logic300may receive the comparison signal CS from the comparator200and output a first control signal RCON to the reference signal adjusting circuit400on the basis of the received comparison signal CS.

The reference signal adjusting circuit400may adjust the reference signal RS provided to the comparator200according to the first control signal RCON received from the control logic300. Specifically, the reference signal adjusting circuit400may adjust the voltage level of the reference signal RS provided to the comparator200according to the first control signal RCON received from the control logic300.

In some example embodiments, when the semiconductor device10is the SAR ADC, the reference signal adjusting circuit400may include a digital-to-analog converter (DAC) that adjusts the voltage level of the reference signal RS according to the first control signal RCON, which is a digital signal. Specifically, when the semiconductor device10is the SAR ADC, the reference signal adjusting circuit400may include a DAC that adjusts a reference voltage RV received from the outside according to the first control signal RCON, which is a digital signal, and outputs the adjusted reference voltage RV as a reference signal RS. More specifically, when the semiconductor device10is the SAR ADC, the reference signal adjusting circuit400may include a DAC that controls a plurality of capacitors and a plurality of switches disposed therein according to the first control signal RCON, which is a digital signal, to generate a reference signal RS from the reference voltage RV and output the generated reference signal RS to the comparator200.

Meanwhile, the control logic300may provide a second control signal PCON for controlling the operation of the comparator200to the comparator200.

In some example embodiments, the control logic300may include an SAR logic, and the reference signal adjusting circuit400may include a DAC that generates a reference voltage according to a first control signal RCON received from the SAR logic, but example embodiments are not limited thereto.

FIG.2is a diagram for describing an ADC according to some example embodiments.FIG.3is a diagram for describing the operation of the ADC ofFIG.2.FIG.4is a schematic diagram illustrating a first comparator included in the ADC ofFIG.1.FIG.5is a schematic diagram illustrating a second comparator included in the ADC ofFIG.1.

Referring toFIG.2, a semiconductor device10may further include first and second asynchronous clock generators510and520. The first asynchronous clock generator510may receive a sampling clock signal Sampling CLK and generate a first asynchronous clock signal CLK_M from the received sampling clock signal Sampling CLK. The second asynchronous clock generator520may generate a second asynchronous clock signal CLK_L from a first comparison operation completion signal MSB_Done.

The comparator200may include first and second comparators210and220that compare an input signal VINwith first and second reference signals to generate first and second comparison signals CS_1and CS_2, respectively. The first comparator210may be a coarse comparator, and the second comparator220may be a fine comparator. A coarse ADC may include the coarse comparator210, a first control logic310, and the first asynchronous clock generator510, and a fine ADC may include the fine comparator220, a second control logic320, and the second asynchronous clock generator520.

Referring toFIGS.2and3, the first comparator210may generate a first comparison signal CS_1on the basis of the first asynchronous clock signal CLK_M generated from the sampling clock signal Sampling CLK. The second comparator220may generate a second comparison signal CS_2on the basis of the second asynchronous clock signal CLK_L generated by the first comparison operation completion signal MSB_Done. That is, the first asynchronous clock generator510may receive the sampling clock signal Sampling CLK to start generating the first asynchronous clock signal CLK_M, and may stop generating the first asynchronous clock signal CLK_M in response to the first comparison operation completion signal MSB_Done provided by the first control logic310. Thereafter, the second asynchronous clock generator520may start generating the second asynchronous clock signal CLK_L.

The first comparison signal CS_1may include first up/down signals DP_M and DM_M for performing a first comparison operation, and the second comparison signal CS_2may include second up/down signals DP_L and DM_L for performing a second comparison operation. The first comparator210may provide a first ready signal RDY_M for confirming that the first up/down signals DP_M and DM_M have been transmitted, and the second comparator220may provide a second ready signal RDY_L for confirming that the second up/down signals DP_L and DM_L have been transmitted.

In this case, the first comparison signal CS_1may be synchronized or substantially synchronized with the first asynchronous clock signal CLK_M, and the second comparison signal CS_2may be synchronized or substantially synchronized with the second asynchronous clock signal CLK_L. The first and second comparison signals CS_1and CS_2may not be synchronized with the sampling clock signal Sampling CLK.

A control logic300may include the first control logic310and the second control logic320.

The first and second control logics310and320may respectively output first and second control signals RCON_1and RCON_2on the basis of the first and second comparison signals CS_1and CS_2. Each of the first and second control logics310and320may determine bits of a digital output signal corresponding to an analog input signal from a corresponding one of the first and second comparators210and220.

The first and second control logics310and320may respectively output first and second comparison operation completion signals MSB_Done and LSB_Done on the basis of the first and second comparison signals CS_1and CS_2. The first control logic310may generate the first comparison operation completion signal MSB_Done on the basis of the first comparison signal CS_1. The second control logic320may generate the second comparison operation completion signal LSB_Done on the basis of the second comparison signal CS_2.

The first control logic310may provide the first comparison operation completion signal MSB_Done to the first asynchronous clock generator510. The second control logic320may provide the second comparison operation completion signal LSB_Done to the second asynchronous clock generator520.

A conversion logic330may convert first data output by the first control logic310and second data output by the second control logic320into digital signals. Digital processing may be performed on both of the first data and the second data, and each of the first data and the second data may be converted into a digital output signal DOUT.

A reference signal adjusting circuit400may include first and second reference signal adjusting circuits400A and400B that adjust voltage levels of the first and second reference signals according to the first and second control signals RCON_1and RCON_2. The first and second reference signal adjusting circuits400A and400B may include first and second capacitor arrays410and420and a plurality of switches S1and S2, respectively.

Although not specifically illustrated, each of the first and second capacitor arrays410and420may include a plurality of binary-weighted capacitors. The first reference signal adjusting circuit400A may include the first capacitor array410used to determine N upper bits of the digital output signal corresponding to the analog input signal. The second reference signal adjusting circuit400B may include the second capacitor array420used to determine N-n lower bits remaining after the digital output signal is generated.

Each of the plurality of capacitors may have the capacitance of 2ntimes the capacitance of a unit capacitor (or any other suitable capacitance value). For example, each of the capacitors included in the second capacitor array420may have the capacitance of 20times, 21times, 22times, 23times, 24times, 25times the capacitance of the unit capacitor, etc. Further, for example, each of the capacitors included in the first capacitor array410may have the capacitance of 26times, 27times, 28times, 29times, 210times the capacitance of the unit capacitor, etc.

The capacitors included in the first capacitor array410may be used to receive a first reference voltage VREFPand a second reference voltage VREFNand determine upper bits of the digital output signal DOUT. The capacitors included in the second capacitor array420may be used to receive the first reference voltage VREFPand the second reference voltage VREFNand determine lower bits of the digital output signal DOUT.

First terminals of the capacitors included in the first capacitor array410may be connected to a first node of the first comparator210. First terminals of the capacitors included in the second capacitor array420may be connected to a first node of the second comparator220.

Second terminals of the capacitors included in the first capacitor array410may be connected to any one of the first reference voltage VREFPand the second reference voltage VREFNby the plurality of switches S1. Second terminals of the capacitors included in the second capacitor array420may be connected to any one of the first reference voltage VREFPand the second reference voltage VREFNby the plurality of switches S2.

For example, the first terminal may be a top plate of the capacitor, and the second terminal may be a bottom plate of the capacitor.

The first and second switches S1and S2may be controlled according to the first control signal RCON_1and the second control signal RCON_2which are respectively output from the first control logic310and the second control logic320.

A third switch S3may function as a bootstrap switch. In this case, the ON-resistance of a sampling switch that is changed dependently on the input signal VINmay be constantly changed.

An offset calibration logic600may calibrate the bits determined by the first control logic310and the bits determined by the second control logic320.

Referring toFIGS.4and5, the first comparator210may include a first preamplifier215that primarily amplifies a difference between the input signal VINand the first reference signal, and a first latch211that generates a first comparison signal CS_1using an output of the first preamplifier215.

The first comparator210may further include a first preamplifier reset switch circuit216, a first latch reset switch circuit212, a1_1capacitor C1_M connected to a node that provides first up/down signals DP_M and DM_M, a1_2capacitor C2_M connected to a node that provides a first ready signal RDY_M, and a1_3capacitor C3_M connected to a node connected to the first asynchronous clock generator510.

The first control logic310may provide start and end signals of the operation of the first preamplifier215to control the start of the operation of the first preamplifier215.

The second comparator220may include a second preamplifier225that secondarily amplifies a difference between the input signal VINand the second reference signal, and a second latch221that generates a second comparison signal CS_2using an output of the second preamplifier225.

The second comparator220may further include a second preamplifier reset switch circuit226, a second latch reset switch circuit222, a2_1capacitor C1_L connected to a node that provides second up/down signals DP_L and DM_L, a2_2capacitor C2_L connected to a node that provides a second ready signal RDY_L, and a2_3capacitor C3_L connected to a node connected to the second asynchronous clock generator520.

The second control logic320may provide start and end signals of the operation of the second preamplifier225to control the start of the operation of the second preamplifier225.

A first comparison operation corresponding to upper bits may be performed by the first comparator210, and after the first comparison operation is performed, a second comparison operation corresponding to lower bits may be performed by the second comparator220.

Since the first comparison operation is performed by the coarse comparator210and the second comparison operation is performed by the fine comparator220, an operation speed of the first comparison operation may be greater than an operation speed of the second comparison operation, and the first comparison operation may be performed with less power consumption than the second comparison operation.

Further, an amount of power consumed when the first comparison operation is performed may be smaller than that of power consumed when the second comparison operation is performed. As a result, the sizes of a first tail switch circuit213, a first asynchronous clock generator214, the first preamplifier215, and the first control logic310may be reduced compared to prior art. In this case, the size of the first preamplifier215may be smaller than the size of the second preamplifier225, and the size of the first control logic310may be smaller than the size of the second control logic320.

Accordingly, the loading of unwanted parasitic capacitors may also be reduced. As a result, the sizes of the first latch211, the first latch reset switch circuit212, and the first asynchronous clock generator214may be reduced compared to prior art.

Meanwhile, in this case, the accuracy of the first comparison operation of the first comparator210may be lower than the accuracy of the second comparison operation of the second comparator220. Although not specifically illustrated, errors related to the comparison operations may be removed using, for example, a redundancy circuit of the second reference signal adjusting circuit400B.

The first comparator210may perform the first comparison operation at a fast operation speed with reduced power consumption, and the second comparator220may perform the second comparison operation with improved accuracy. That is, the power consumption may be reduced even when the accuracy of the comparison operation is the same or improved compared to prior art. As a result, the sizes of a second tail switch circuit223and a second asynchronous clock generator224may be reduced.

Accordingly, the loading of the unwanted capacitors may also be reduced. As a result, the sizes of the second latch221and the second latch reset switch circuit222may be reduced compared to the related art.

FIG.6is a flowchart illustrating an analog-to-digital conversion method according to some example embodiments.

First, a first asynchronous clock signal CLK_M may be generated from a sampling clock signal Sampling CLK by a first asynchronous clock generator510(S100).

Thereafter, a first comparison signal CS_1may be generated based on the first asynchronous clock signal CLK_M by a first comparator210(S200).

Thereafter, a first comparison operation completion signal MSB_Done may be generated based on the first comparison signal CS_1by a first control logic310(S300).

Thereafter, a second asynchronous clock signal CLK_L may be generated from the first comparison operation completion signal MSB_Done by a second asynchronous clock generator520(S400).

Thereafter, a second comparison signal CS_2may be generated based on the second asynchronous clock signal CLK_L by a second comparator220(S500). Thereafter, a second comparison operation completion signal LSB_Done may be generated based on the second comparison signal CS_2by a second control logic320.

The first comparison signal CS_1may include first up/down signals DP_M and DM_M for performing a first comparison operation, and the second comparison signal CS_2may include second up/down signals DP_L and DM_L for performing a second comparison operation. The first comparator210may provide a first ready signal RDY_M for confirming that the first up/down signals DP_M and DM_M have been transmitted, and the second comparator220may provide a second ready signal RDY_L for confirming that the second up/down signals DP_L and DM_L have been transmitted.

The first comparison signal CS_1may be generated according to the first asynchronous clock signal CLK_M, and the second comparison signal CS_2may be generated according to the second asynchronous clock signal CLK_L. The first and second comparison signals CS_1and CS_2may not be synchronized with the sampling clock signal Sampling CLK.

It will be understood that elements and/or properties thereof described herein as being “substantially” the same and/or identical encompasses elements and/or properties thereof that have a relative difference in magnitude that is equal to or less than 10%. Further, regardless of whether elements and/or properties thereof are modified as “substantially,” it will be understood that these elements and/or properties thereof should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated elements and/or properties thereof.

One or more of the elements disclosed above may include or be implemented in one or more processing circuitries such as hardware including logic circuits; a hardware/software combination such sa a processor executing software; or a combination thereof. For example, the processing circuitries more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FGPA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc.

While some example embodiments have been described with reference to the accompanying drawings, the inventive concepts are not limited to the example embodiments disclosed but may be implemented in various different forms. It will be understood that various modifications can be made without departing from the scope of the inventive concepts. Therefore, the above-described example embodiments should be considered in a descriptive sense only and not for purposes of limitation.