Patent ID: 12198652

DETAILED DESCRIPTION

FIG.1is a block diagram illustrating a display system100according to an embodiment of the present invention. As shown inFIG.1, the display system100may include a timing controller circuit10and a display panel12, wherein the display panel12may include a gate in panel (GIP) circuit14, a plurality of gates16_1-16_N (e.g. gates of a plurality of thin-film transistors (TFT)), and a source driver circuit18. The GIP circuit14acts as a gate driver circuit, and may be arranged to control opening/closing of the gates on a plurality of gate lines GL_1-GL_N, and may include a plurality of shift registers20_1-20_N, wherein the shift registers20_1-20_N correspond to the gate lines GL_1-GL_N, respectively, and the gate lines GL_1-GL_N are coupled to the gates16_1-16_N, respectively. For convenience of description, only one gate on each gate line is illustrated inFIG.1. In practice, each gate line is connected to the gates of the plurality of TFTs in the horizontal direction. In addition, the display panel12has a plurality of data lines, and each data line is connected to the sources of the plurality of TFTs in the vertical direction. The source driver circuit18may be arranged to control the driving voltage applied to each data line according to an image data IDATA. The number of gate lines GL_1-G1_N and the number of data lines (not shown) may be determined according to the resolution W×H of the display panel12, wherein each pixel of the display panel12is composed of three sub-pixels: a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. As a result, the horizontal resolution W of the display panel12determines the number of data lines in the horizontal direction as W*3, and the vertical resolution H of the display panel12determines the number of gate lines GL_1-GL_N in the vertical direction as H (i.e. N=H). For example, under the condition that the resolution of the display panel12is 8K×4K, the vertical direction of the display panel12may include 4320 gates16_1-16_4320(i.e. N=4320) that are located on 4320 gate lines GL_1-GL_4320, respectively, and the source of the corresponding 4320 TFTs that have the gates16_1-16_4320, respectively, will be connected to the same data line. In addition, the GIP circuit14may include 4320 shift registers20_1-20_4320, wherein the 4320 shift registers20_1-20_4320correspond to the 4320 gate lines GL-1-GL_4320, respectively.

The timing controller circuit10may be arranged to receive the image data IDATA, and detect an input timing IN_TIMING of the image data IDATA. In addition, the timing controller circuit10may perform data masking on the image data IDATA according to the input timing IN_TIMING of the image data IDATA to generate a data masking signal DATA_MASK, and determine a GIP timing GIP_TIMING of the GIP circuit14according to the input timing IN_TIMING of the image data IDATA, wherein the timing controller circuit10may generate a timing control output TIMING_OUTPUT to the GIP circuit14according to the GIP timing GIP_TIMING. It should be noted that, in some embodiments, in response to different input timings IN_TIMING of the image data IDATA, the timing controller circuit10will perform switching selection between different GIP timings GIP_TIMING of the GIP circuit14. In addition, in some embodiments, the timing controller circuit10will not perform data masking on the image data IDATA according to the input timing IN_TIMING of the image data IDATA (i.e. the data masking signal DATA_MASK will not be generated), but instead will directly transmit the image data IDATA to the display panel12(e.g. the source driver circuit18of the display panel12). Then, the timing controller circuit10may transmit the timing control output TIMING_OUTPUT and the image data IDATA (or the timing control output TIMING_OUTPUT, the image data IDATA, and the data masking signal DATA_MASK) to the display panel12, wherein the timing control output TIMING_OUTPUT is transmitted to the GIP circuit14, and the image data IDATA (or the image data IDATA and the data masking signal DATA_MASK) is transmitted to the source driver circuit18.

In this embodiment, the timing control output TIMING_OUTPUT may include a first starting pulse signal STVA, a second starting pulse signal STVB, and a plurality of clock signals CLK1-CLKM. The first starting pulse signal STVA may be arranged to pre-charge the shift register20_1in the shift registers20_1-20_N, to sequentially turn on a plurality of odd shift registers (i.e. the shift register20_1, the shift register20_3, the shift register20_5, and so on) corresponding to a plurality of odd gate lines (i.e. GL_1, GL_3, GL_5, and so on) in the GIP circuit14. The second starting pulse signal STVB may be arranged to pre-charge the shift register20_2in the shift registers20_1-20_N, to sequentially turn on a plurality of even shift registers (i.e. the shift register20_2, the shift register20_4, the shift register20_6, and so on) corresponding to a plurality of even gate lines (i.e. GL_2, GL_4, GL_6, and so on) in the GIP circuit14. The clock signals CLK1-CLKM may be arranged to drive the odd gate lines and the even gate lines through the odd shift registers and the even shift registers, respectively, to turn on the gates connected to each gate line (e.g. the gates16_1-16_N in the vertical direction will be turned on one by one according to the driving timing of the gate lines GL_1-GL_N). For example, under the condition that the resolution of the display panel12is 8K×4K (i.e. the display panel12may include the gates16_1-16_4320, which are the gates of 4320 TFTs on the same data line, respectively), the timing control output TIMING_OUTPUT may include the clock signals CLK1-CLK10(i.e. M=10), wherein each of the clock signals CLK1-CLK10has 432 pulses to turn on 432 gate lines in the 4320 gate lines GL_1-GL_4320, respectively. For the gates16_1-16_4320of 4320 TFTs on the same data line, the 432 pulses of each clock signal of the clock signals CLK1-CLK10will turn on 432 gates in the gates16_1-16_4320(e.g. the 432 pulses in the clock signal CLK1will turn on the gates16_1,16_11,16_21, . . . ,16_4311, respectively).

FIG.2is a diagram illustrating a timing controller circuit200according to an embodiment of the present invention. The timing controller circuit10shown inFIG.1may be implemented by the timing controller circuit200shown inFIG.2. It should be noted that, in this embodiment, the resolution and the frame rate of the display panel12are 8K×4K and 60 Hz, respectively, and the timing controller circuit200will not perform data masking on the image data IDATA according to the input timing IN_TIMING of the image data IDATA (i.e. the data masking signal DATA_MASK will not be generated), but instead will directly transmit the image data IDATA to the display panel12(e.g. the source driver circuit18of the display panel12). In addition, the timing controller circuit200has only one timing controller201, and the timing controller201may be arranged to control the gate driving and the data driving (i.e. the source driving) of all sub-pixels of the display panel12.

As shown inFIG.2, the timing controller circuit200(more particularly, the timing controller201) may include a data receiving circuit202, a timing detection circuit204, a control circuit206, and a data transmitting circuit208. The data receiving circuit202may be arranged to receive the image data IDATA, wherein the input timing IN_TIMING of the image data IDATA may be 8K×4K @ 60 Hz (i.e. the resolution and the frame rate of the image data IDATA are 8K×4K and 60 Hz, respectively) or 8K×2K @ 120 Hz (i.e. the resolution and the frame rate of the image data IDATA are 8K×2K and 120 Hz, respectively). The timing detection circuit204may be coupled to the data receiving circuit202, and may be arranged to detect the input timing IN_TIMING of the image data IDATA. The control circuit206may be coupled to the timing detection circuit204, and may be arranged to determine the GIP timing GIP_TIMING of the GIP circuit14according to the detected input timing IN_TIMING of the image data IDATA, and generate the timing control output TIMING_OUTPUT (which includes the first starting pulse signal STVA, the second starting pulse signal STVB, and the clock signals CLK1-CLK10according to the GIP timing GIP_TIMING, wherein in response to different input timings IN_TIMING of the image data IDATA, the control circuit206will perform switching selection on different GIP timings GIP_TIMING of the GIP circuit14. The data transmitting circuit208may be coupled to the control circuit206, and may be arranged to transmit the timing control output TIMING_OUTPUT to the GIP circuit14, and output the image data IDATA to the source driver circuit18.

For example, when the input timing IN_TIMING of the image data IDATA is 8K×4K @ 60 Hz, the timing control output TIMING_OUTPUT will control the GIP circuit14to sequentially turn on each gate line in the gate lines GL_1-GL_4320of the display panel12(i.e. sequentially turn on each gate in the gates16_1-16_4320in the vertical direction that are connected to the same data line in the display panel12), to illuminate the display panel12. In another example, when the input timing IN_TIMING of the image data IDATA is 8K×2K @ 120 Hz, the timing control output TIMING_OUTPUT will control the GIP circuit14to sequentially turn on two gate lines in the gate lines GL_1-GL_4320of the display panel12at the same time (i.e. sequentially turn on two gates in the gates16_1-16_4320in the vertical direction that are connected to the same data line in the display panel12at the same time), wherein the sub-pixels corresponding to the two gates, respectively, will display the same sub-pixel data transmitted by the data transmitting circuit208in the image data IDATA at the same time. In this way, the frame rate of the display panel12is increased from the original 60 Hz to 120 Hz (i.e. doubled). In addition, the horizontal resolution of the display panel is maintained at 8K, and the vertical resolution of the display panel is reduced from 4K to 2K. The resolution of the display panel, however, is still maintained at true 8K. As a result, under the condition that the timing controller circuit200has only one timing controller201, the frame rate of the display panel12is increased, and the dynamic visuals of the display panel12will be improved. In addition, the charge time of each data line of the display panel12is maintained at 3.74 microseconds (μs).

FIG.3is a timing diagram of a timing control output generated by the timing controller circuit200shown inFIG.2according to an embodiment of the present invention. In this embodiment, the input timing IN_TIMING of the image data IDATA is 8K×4K @ 60 Hz. The first starting pulse signal STVA may include a plurality of odd pulse signals STV0_A and STV1_A, wherein a pulse signal width of the odd pulse signal STV0_A is 1.5*3.7 μs, and a pulse signal width of the odd pulse signal STV1_A is 3*3.7 μs. The second starting pulse signal STVB may include a plurality of even pulse signals STV0_B and STV1_B, wherein a pulse signal width of the even pulse signal STV0_B is 1.5*3.7 μs, and a pulse signal width of the even pulse signal STV1_B is 3*3.7 μs. Since the input timing IN_TIMING of the image data IDATA is 8K×4K @ 60 Hz, the timing control output TIMING_OUTPUT will control the GIP circuit14to sequentially turn on each of the gates16_1-16_4320of the display panel12, to illuminate the display panel12. As shown inFIG.3, each of the clock signals CLK1-CLK10has 432 pulses to turn on 432 gates in the gates16_1-16_4320, respectively (e.g. the 432 pulses in the clock signal CLK1turn on the gates16_1,16_11,16_21, . . . ,16_4311, respectively), wherein a pulse signal width of each pulse is 2*3.7 μs. For brevity, only the pulses that correspond to the first 20 gates (i.e. the gates16_1-16_20) of the gates16_1to16_4320, respectively, are illustrated inFIG.3.

FIG.4is a timing diagram of a timing control output generated by the timing controller circuit200shown inFIG.2according to another embodiment of the present invention. In this embodiment, the input timing IN_TIMING of the image data IDATA is 8K×2K @ 120 Hz. The first starting pulse signal STVA may include a plurality of odd pulse signals STV0_A and STV1_A, wherein a pulse signal width of the odd pulse signal STV0_A is 1.5*3.7 μs, and a pulse signal width of the odd pulse signal STV1_A is 3*3.7 μs. The second starting pulse signal STVB may include a plurality of even pulse signals STV0_B and STV1_B, wherein a pulse signal width of the even pulse signal STV0_B is 1.5*3.7 μs, and a pulse signal width of the even pulse signal STV1_B is 3*3.7 μs. Since the input timing IN_TIMING of the image data IDATA is 8K×2K @ 120 Hz, the timing control output TIMING_OUTPUT will control the GIP circuit14to sequentially turn on two gates in the gates16_1-16_4320of the display panel12at the same time (e.g. sequentially turn on the gates16_1and16_2, the gates16_3and16_4, the gates16_5and16_6, . . . , and the gates16_4319and16_4320at the same time). As shown inFIG.4, each of the clock signals CLK1-CLK10has 432 pulses to turn on 432 gates in the gates16_1-16_4320, respectively (e.g. the 432 pulses in the clock signal CLK1turn on the gates16_1,16_11,16_21, . . . ,16_4311, respectively), wherein a pulse signal width of each pulse is 2*3.7 μs. For brevity, only the pulses that correspond to the first 20 gates (i.e. the gates16_1-16_20) of the gates16_1to16_4320, respectively, are illustrated inFIG.4.

FIG.5is a diagram illustrating a timing controller circuit500according to another embodiment of the present invention. The timing controller circuit10shown inFIG.1may be implemented by the timing controller circuit500shown inFIG.5. It should be noted that, in this embodiment, the resolution and the frame rate of the display panel12are 8K×4K and 120 Hz, respectively, and the timing controller circuit500may include a master timing controller50and a slave timing controller51, wherein the master timing controller50may be arranged to control gate driving of all sub pixels of the display panel12, and control data driving (source driving) of a part of sub-pixels in all sub-pixels of the display panel12, and the slave timing controller51may be arranged to control data driving (source driving) of another part of sub-pixels in all sub-pixels of the display panel12. For example, under the condition that the data output of the master timing controller50and the data output of the slave timing controller51are coupled to the left side and the right side of the display panel12, respectively, the master timing controller50may be arranged to control the data driving of the left side of the display panel12, and the slave timing controller51may be arranged to control the data driving of the right side of the display panel12.

As shown inFIG.5, the master timing controller50included in the timing controller circuit500may include a data receiving circuit502, a timing detection circuit504, a data processing circuit506, a control circuit508, and a data transmitting circuit510. The data receiving circuit502may be arranged to receive an image data IDATA, wherein an input timing IN_TIMING of the image data IDATA may be 8K×4K @ 120 Hz (i.e. the resolution and the frame rate of the image data IDATA are 8K×4K and 120 Hz, respectively). The timing detection circuit504may be coupled to the data receiving circuit502, and may be arranged to detect the input timing IN_TIMING of the image data IDATA. The data processing circuit506may be coupled to the timing detection circuit504, and may be arranged to perform data masking upon the image data IDATA according to the input timing IN_TIMING of the image data IDATA, to generate a data masking signal DATA_MASK. The control circuit508may be coupled to the timing detection circuit504, and may be arranged to determine the GIP timing GIP_TIMING of the GIP circuit14according to the input timing IN_TIMING of the image data IDATA, and generate a timing control output TIMING_OUTPUT (which includes a first starting pulse signal STVA, a second starting pulse signal STVB, and a plurality of clock signals CLK1-CLK10) according to the GIP timing GIP_TIMING. The data transmitting circuit510may be coupled to the data processing circuit506and the control circuit508, and may be arranged to transmit the timing control output TIMING_OUTPUT, the image data IDATA, and the data masking signal DATA_MASK to the display panel12, wherein the timing control output TIMING_OUTPUT is output to the GIP circuit14, and the image data IDATA and the data masking signal DATA_MASK are output to the source driver circuit18.

In this embodiment, the data masking signal DATA_MASK may be arranged to control the source driver circuit18to mask odd line data and only drive even line data in each even frame of the image data IDATA, and control the source driver circuit17to mask the even line data and only drive the odd line data in each odd frame of the image data IDATA. In this way, each frame of the display panel12will only display the data whose input timing IN_TIMING is 8K×2K @ 120 Hz. As a result, the timing controller circuit500may utilize the interlaced scanning structure to double the charging time of each data line of the display panel12from the original 1.87 μs to 3.74 μs, to improve the problem of insufficient charging time.

FIG.6is a timing diagram of a timing control output generated by the timing controller circuit500shown inFIG.5according to an embodiment of the present invention. As shown inFIG.6, the first starting pulse signal STVA may include a plurality of odd pulse signals STV0_A and STV1_A, wherein a pulse signal width of the odd pulse signal STV0_A is 3*1.85 μs, and a pulse signal width of the odd pulse signal STV1_A is 6*1.85 μs. The second starting pulse signal STVB may include a plurality of even pulse signals STV0_B and STV1_B, wherein a pulse signal width of the even pulse signal STV0_B is 3*1.85 μs, and a pulse signal width of the even pulse signal STV1_B is 6*1.85 μs. The timing control output TIMING_OUTPUT will control the GIP circuit14to sequentially turn on each gate in the gates16_1-16_4320of the display panel12, to light up the display panel12. Each of the clock signals CLK1-CLK10has 432 pulses to turn on 432 gates in the gates16_1-16_4320, respectively (e.g. the 432 pulses in the clock signal CLK1turn on the gates16_1,16_11,16_21, . . . ,16_4311, respectively), wherein a pulse signal width of each pulse is 4*1.85 μs. For brevity, only the pulses that correspond to the first 20 gates (i.e. the gates16_1-16_20) of the gates16_1to16_4320, respectively, are illustrated inFIG.6.

It is assumed that the image data IDATA has a plurality of odd line data D1, D3, D5, . . . , D4319(where each odd line data includes sub-pixel data that are arranged to drive a plurality of TFTs on a same odd scanning line) and a plurality of even line data (where each even line data includes sub-pixel data that are arranged to drive a plurality of TFTs on a same even scanning line). Under the condition that the data masking signal DATA_MASK controls the source driver circuit18, a plurality of odd gates corresponding to a plurality of odd gate lines will only display the odd line data (e.g. the gate16_1will only display the odd line data D1, and the gate16_3will only display the odd line data D3), and a plurality of even gates corresponding to a plurality of even gate lines will only display the even line data (e.g. the gate16_2will only display the even line data D2, and the gate16_4will only display the even line data D4). For brevity, only the pulses that correspond to the first 20 gates (i.e. the gates16_1-16_20) of the gates16_1to16_4320, respectively, are illustrated inFIG.6.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.