Patent ID: 12213388

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

FIG.1is a schematic cross-sectional view of an integrated circuit IC in accordance with some embodiments of the disclosure. In some embodiments, the integrated circuit IC includes a substrate20, an interconnect structure30, a passivation layer40, a post-passivation layer50, a plurality of conductive pads60, and a plurality of conductive terminals70. In some embodiments, the substrate20is made of elemental semiconductor materials, such as crystalline silicon, diamond, or germanium; compound semiconductor materials, such as silicon carbide, gallium arsenic, indium arsenide, or indium phosphide; or alloy semiconductor materials, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. The substrate20may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate.

In some embodiments, the substrate20includes various doped regions depending on circuit requirements (e.g., p-type semiconductor substrate or n-type semiconductor substrate). In some embodiments, the doped regions are doped with p-type or n-type dopants. For example, the doped regions may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and/or combinations thereof. In some embodiments, these doped regions serve as source/drain regions of a first transistor T1, which is over the substrate20. Depending on the types of the dopants in the doped regions, the first transistor T1may be referred to as n-type transistor or p-type transistor. In some embodiments, the first transistor T1further includes a metal gate and a channel under the metal gate. The channel is located between the source region and the drain region to serve as a path for electron to travel when the first transistor T1is turned on. On the other hand, the metal gate is located above the substrate20and is embedded in the interconnect structure30. In some embodiments, the first transistor T1is formed using suitable Front-end-of-line (FEOL) process. For simplicity, one first transistor T1is shown inFIG.1. However, it should be understood that more than one first transistors T1may be presented depending on the application of the integrated circuit IC. When multiple first transistors T1are presented, these first transistors T1may be separated by shallow trench isolation (STI; not shown) located between two adjacent first transistors T1.

As illustrated inFIG.1, the interconnect structure30is disposed on the substrate20. In some embodiments, the interconnect structure30includes a plurality of conductive vias32, a plurality of conductive patterns34, a plurality of dielectric layers36, a memory cell MC, and a second transistor T2. As illustrated inFIG.1, the conductive patterns34and the conductive vias32are embedded in the dielectric layers36. In some embodiments, the conductive patterns34located at different level heights are connected to one another through the conductive vias32. In other words, the conductive patterns34are electrically connected to one another through the conductive vias32. In some embodiments, the bottommost conductive vias32are connected to the first transistor T1. For example, the bottommost conductive vias32are connected to the metal gate, which is embedded in the bottommost dielectric layer36, of the first transistor T1. In other words, the bottommost conductive vias32establish electrical connection between the first transistor T1and the conductive patterns34of the interconnect structure30. As illustrated inFIG.1, the bottommost conductive via32is connected to the metal gate of the first transistor T1. It should be noted that in some alternative cross-sectional views, other bottommost conductive vias32are also connected to source/drain regions of the first transistor T1. That is, in some embodiments, the bottommost conductive vias32may be referred to as “contact structures” of the first transistor T1.

In some embodiments, a material of the dielectric layers36includes polyimide, epoxy resin, acrylic resin, phenol resin, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer-based dielectric material. Alternatively, the dielectric layers36may be formed of oxides or nitrides, such as silicon oxide, silicon nitride, or the like. The dielectric layers36may be formed by suitable fabrication techniques such as spin-on coating, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or the like.

In some embodiments, a material of the conductive patterns34and the conductive vias32includes aluminum, titanium, copper, nickel, tungsten, or alloys thereof. The conductive patterns34and the conductive vias32may be formed by electroplating, deposition, and/or photolithography and etching. In some embodiments, the conductive patterns34and the underlying conductive vias32are formed simultaneously. It should be noted that the number of the dielectric layers36, the number of the conductive patterns34, and the number of the conductive vias32illustrated inFIG.1are merely for illustrative purposes, and the disclosure is not limited thereto. In some alternative embodiments, fewer or more layers of the dielectric layers36, the conductive patterns34, and/or the conductive vias32may be formed depending on the circuit design.

As illustrated inFIG.1, the memory cell MC is embedded in the interconnection structure30. For example, the memory cell MC is embedded in one of the dielectric layers36. For simplicity, one memory cell MC is shown inFIG.1. However, it should be understood that more than one memory cells MC may be presented depending on the application of the integrated circuit IC. The formation method and the structure of the memory cell MC will be described in detail later.

In some embodiments, the second transistor T2is also embedded in the interconnection structure30. For example, the second transistor T2is embedded in one of the dielectric layer36. For simplicity, one second transistor T2is shown inFIG.1. However, it should be understood that more than one second transistors T2may be presented depending on the application of the integrated circuit IC. In some embodiments, the second transistor T2is electrically connected to the conductive patterns34through the corresponding conductive vias32. In some embodiments, the second transistor T2is a thin-film transistors (TFT). For example, the second transistor T2includes a gate electrode, a gate dielectric layer, a channel layer, and source/drain regions. The gate dielectric layer is sandwiched between the channel layer and the gate electrode. The source/drain regions are respective disposed at two opposite ends of the channel layer. As illustrated inFIG.1, the conductive vias32are in physical contact with the source/drain regions to render electrical connection with the second transistor T2. It should be noted that in some alternative cross-sectional views, another conductive via32is also connected to gate electrode of the second transistor T2. In some embodiments, the second transistor T2is electrically connected to the memory cell MC. In some embodiments, the second transistor T2and the memory cell MC may be collectively referred to as a memory device. For example, the second transistor T2may serve as a selector for the memory device. As will be described later, since the memory cell MC includes phase change materials, the memory device illustrated inFIG.1may be referred to as Phase Change Random Access Memory (PCRAM) device. In some embodiments, since the second transistor T2and the memory cell MC are embedded in the interconnection structure30, the second transistor T2and the memory cell MC are being considered as formed during back-end-of-line (BEOL) process. It should be noted that althoughFIG.1illustrated that the second transistor T2and the memory cell MC are being embedded in different dielectric layers36, the disclosure is not limited thereto. In some alternative embodiments, the second transistor T2and the memory cell MC are embedded in the same dielectric layer36.

As illustrated inFIG.1, the passivation layer40, the conductive pads60, the post-passivation layer50, and the conductive terminals70are sequentially formed on the interconnect structure30. In some embodiments, the passivation layer40is disposed on the topmost dielectric layer36and the topmost conductive patterns34. In some embodiments, the passivation layer40has a plurality of openings partially exposing each topmost conductive pattern34. In some embodiments, the passivation layer40is a silicon oxide layer, a silicon nitride layer, a silicon oxy-nitride layer, or a dielectric layer formed by other suitable dielectric materials. The passivation layer40may be formed by suitable fabrication techniques such as high-density-plasma chemical vapor deposition (HDP-CVD), PECVD, or the like.

In some embodiments, the conductive pads60are formed over the passivation layer40. In some embodiments, the conductive pads60extend into the openings of the passivation layer40to be in physical contact with the topmost conductive patterns34. That is, the conductive pads60are electrically connected to the interconnect structure30. In some embodiments, the conductive pads60include aluminum pads, copper pads, titanium pads, nickel pads, tungsten pads, or other suitable metal pads. The conductive pads60may be formed by, for example, electroplating, deposition, and/or photolithography and etching. It should be noted that the number and the shape of the conductive pads60illustrated inFIG.1are merely for illustrative purposes, and the disclosure is not limited thereto. In some alternative embodiments, the number and the shape of the conductive pads60may be adjusted based on demand.

In some embodiments, the post-passivation layer50is formed over the passivation layer40and the conductive pads60. In some embodiments, the post-passivation layer50is formed on the conductive pads60to protect the conductive pads60. In some embodiments, the post-passivation layer50has a plurality of contact openings partially exposing each conductive pad60. The post-passivation layer50may be a polyimide layer, a PBO layer, or a dielectric layer formed by other suitable polymers. In some embodiments, the post-passivation layer50is formed by suitable fabrication techniques such as HDP-CVD, PECVD, or the like.

As illustrated inFIG.1, the conductive terminals70are formed over the post-passivation layer50and the conductive pads60. In some embodiments, the conductive terminals70extend into the contact openings of the post-passivation layer50to be in physical contact with the corresponding conductive pad60. That is, the conductive terminals70are electrically connected to the interconnect structure30through the conductive pads60. In some embodiments, the conductive terminals70are conductive pillars, conductive posts, conductive balls, conductive bumps, or the like. In some embodiments, a material of the conductive terminals70includes a variety of metals, metal alloys, or metals and mixture of other materials. For example, the conductive terminals70may be made of aluminum, titanium, copper, nickel, tungsten, tin, and/or alloys thereof. The conductive terminals70are formed by, for example, deposition, electroplating, screen printing, or other suitable methods. In some embodiments, the conductive terminals70are used to establish electrical connection with other components (not shown) subsequently formed or provided.

As mentioned above, the memory cell MC is embedded in the interconnection structure30. The formation method and the structure of the memory cell MC will be described below in conjunction withFIG.2AtoFIG.2P.

FIG.2AtoFIG.2Pare schematic cross-sectional views illustrating various stages of a manufacturing method of the memory cell MC inFIG.1. Referring toFIG.2A, a conductive layer100is provided. In some embodiments, the conductive layer100is one of the conductive patterns34of the interconnection structure30ofFIG.1, so the detailed description thereof is omitted herein. Thereafter, a dielectric layer200is formed on the conductive layer100. In some embodiments, the dielectric layer200is formed of a low-k dielectric material having a dielectric constant (k-value) lower than about 3.0, about 2.5, or even lower. In some embodiments, the dielectric layer200is formed of non-low-k dielectric materials such as silicon oxide, silicon carbide (SiC), silicon carbo-nitride (SiCN), silicon oxy-carbo-nitride (SiOCN), or the like. In some alternative embodiments, the material of the dielectric layer200includes polyimide, epoxy resin, acrylic resin, phenol resin, BCB, PBO, or any other suitable polymer-based dielectric material. The dielectric layer200may be formed by suitable fabrication techniques such as spin-on coating, CVD, PECVD, or the like.

In some embodiments, the dielectric layer200has an opening OP1. For example the dielectric layer200is patterned to form the opening OP1. In some embodiments, the dielectric layer200is patterned through a photolithography and etching process. For example, a patterned photoresist layer (not shown) is formed on the dielectric layer200. Thereafter, an etching process is performed to remove the dielectric layer200that is not covered by the patterned photoresist layer. The etching process includes, for example, an anisotropic etching process such as dry etch or an isotropic etching process such as wet etch. Subsequently, the patterned photoresist layer is removed through a stripping process or the like to expose the remaining dielectric layer200. As illustrated inFIG.2A, the opening OP1penetrates through the dielectric layer200to expose the underlying conductive layer100.

Referring toFIG.2B, a barrier material layer300ais conformally deposited on the dielectric layer200. For example, the barrier material layer300acovers a top surface T200of the dielectric layer200and extends into the opening OP1to cover sidewalls and a bottom surface of the opening OP1. For example, the barrier material layer300aexhibits a U shape in the cross-sectional view, as illustrated inFIG.2B. In some embodiments, the barrier material layer300aextends into the opening OP1to be in physical contact with the conductive layer100. In some embodiments, materials of the barrier material layer300aincludes titanium nitride (TiN), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN), titanium carbide (TiC), tantalum carbide (TaC), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), or a combination thereof. In some embodiments, the barrier material layer300ais formed by a suitable deposition process, such as CVD, PECVD, flowable chemical vapor deposition (FCVD), HDP-CVD, sub-atmospheric chemical vapor deposition (SACVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

Referring toFIG.2C, a bottom electrode material layer400ais formed on the barrier material layer300a. For example, the bottom electrode material layer400acovers a top surface of the barrier material layer300a. In some embodiments, the bottom electrode material layer400afills up the opening OP1. In some embodiments, the bottom electrode material layer400aincludes a metal oxide material, such as TiOx, WOx, RuOx, a combination thereof, or the like. In some alternative embodiments, the bottom electrode material layer400aincludes a metallic material, such as Ti, Co, Cu, AlCu, W, TiN, TiW, TiAl, TiAlN, Ru, a combination thereof, or the like. In some embodiments, the bottom electrode material layer400ais deposited through ALD, CVD, PVD, or the like.

Referring toFIG.2CandFIG.2D, a portion of the barrier material layer300aand a portion of the bottom electrode material layer400aare removed. For example, the barrier material layer300aand the bottom electrode material layer400ashown inFIG.2Care thinned until the underlying dielectric layer200is exposed, so as to form a barrier layer300and a bottom electrode400. In some embodiments, the barrier material layer300aand the bottom electrode material layer400aare thinned through a grinding process, such as a mechanical grinding process, a chemical mechanical polishing (CMP) process, or the like. After grinding, a top surface T200of the dielectric layer200, a top surface T300of the barrier layer300, and a top surface T400of the bottom electrode400are substantially located at the same level height. In other words, the top surface T200of the dielectric layer200, the top surface T300of the barrier layer300, and the top surface T400of the bottom electrode400are substantially coplanar. As illustrated inFIG.2D, the barrier layer300and the bottom electrode400are located within the dielectric layer200. In other words, the barrier layer300and the bottom electrode400are embedded in the dielectric layer200. That is, the dielectric layer200laterally surrounds the barrier layer300and the bottom electrode400. In some embodiments, the barrier layer300is sandwiched between the bottom electrode400and the dielectric layer200. In some embodiments, the barrier layer300laterally surrounds the bottom electrode400. For example, the barrier layer300exhibits a U-shape from the cross-sectional view to cover sidewalls and a bottom surface of the bottom electrode400, as illustrated inFIG.2D. In some embodiments, the barrier layer300is utilized to avoid diffusion of atoms between elements (for example, between the bottom electrode400and the dielectric layer200). In some embodiments, the bottom electrode400is electrically connected to the conductive layer100. In some embodiments, after grinding of the barrier material layer300aand the bottom electrode material layer400a, residues remain on the top surface T200of the dielectric layer200, the top surface T300of the barrier layer300, and the top surface T400of the bottom electrode400. These residues will contaminate subsequently formed elements and thereby resulting adverse effects. Therefore, a cleaning process may be performed to remove these residues.

Referring toFIG.2DandFIG.2E, the cleaning process is performed on the dielectric layer200, the barrier layer300, and the bottom electrode400. In some embodiments, during the cleaning process, a portion of the barrier layer300and a portion of the bottom electrode400are removed, so the cleaning process is referred to as a double plasma etching treatment ET. That is, the double plasma etching treatment ET is performed on the dielectric layer200, the barrier layer300, and the bottom electrode400to selectively remove a portion of the barrier layer300and a portion of the bottom electrode400. On the other hand, the dielectric layer200is not being affected by the double plasma etching process ET. Taking TiOxas a material for the bottom electrode400, the detailed mechanism of the double plasma etching treatment ET for removing a portion of the bottom electrode400will be described below in conjunction withFIG.3AtoFIG.3E.

FIG.3AtoFIG.3Eare schematic cross-sectional views illustrating a mechanism of the double plasma etching treatment ET inFIG.2E. Referring toFIG.3AandFIG.3B, a first soaking treatment ST1is performed on the bottom electrode400using a first gas. In some embodiments, the first gas includes N2H2or the like. In some embodiments, the N2H2gas may serve as hydrogen donor such that some of the oxygen atoms at the top surface of the bottom electrode400(i.e. oxygen atoms of TiOxlocated at the top surface of the bottom electrode400) are bonded to the hydrogen atoms originated from N2H2. In some embodiments, the first soaking treatment ST1is performed at a temperature ranging from about 200° C. to about 400° C. and a pressure ranging from about 200 mTorr to about 10 Torr. In some embodiments, during the first soaking treatment ST1, a flow rate of the first gas ranges from about 200 standard cubic centimeter per minute (sccm) to about 2000 sccm. In some embodiments, the first soaking treatment ST1does not involve the introduction of plasma.

Referring toFIG.3BandFIG.3C, after the first soaking treatment ST1, a first plasma treatment PT1is performed using the first gas to remove a first portion of the bottom electrode400. For example, the first plasma treatment PT1lifts off the oxygen atoms that are bonded to the hydrogen atoms. That is, the first plasma treatment PT1lifts off the OH molecules such that the first portion of the bottom electrode400is removed, as illustrated inFIG.3C. On the other hand, the oxygen atoms that are not bonded to the hydrogen atom maintain their bonding with the titanium atoms and remain in the bottom electrode400. In some embodiments, the first plasma treatment PT1is performed at a temperature ranging from about 200° C. to about 400° C. and a pressure ranging from about 100 mTorr to about 10 Torr. In some embodiments, during the first plasma treatment PT1, a flow rate of the first gas ranges from about 200 sccm to about 2000 sccm. In some embodiments, the power suppled in the chamber to generate plasma ranges from about 200 Watts to about 1000 Watts.

Referring toFIG.3CandFIG.3D, after the first plasma treatment PT1, a second soaking treatment ST2is performed on the bottom electrode400using a second gas. In some embodiments, the second gas is different from the first gas. In some embodiments, the second gas includes HBr of the like. Similar to that of the first gas, the HBr gas may also serve as hydrogen donor such that the remaining oxygen atoms at the top surface of the bottom electrode400(i.e. oxygen atoms of TiOxlocated at the top surface of the bottom electrode400) are bonded to the hydrogen atoms originated from HBr. In some embodiments, the second soaking treatment ST2is performed at a temperature ranging from about 200° C. to about 400° C. and a pressure ranging from about 100 mTorr to about 10 Torr. In some embodiments, during the second soaking treatment ST2, a flow rate of the second gas ranges from about 200 sccm to about 2000 sccm. In some embodiments, the second soaking treatment ST2does not involve the introduction of plasma.

Referring toFIG.3DandFIG.3E, after the second soaking treatment ST2, a second plasma treatment PT2is performed using the second gas to remove a second portion of the bottom electrode400. For example, the second plasma treatment PT2lifts off the oxygen atoms that are bonded to the hydrogen atoms. That is, the second plasma treatment PT1lifts off the OH molecules such that the second portion of the bottom electrode400is removed, as illustrated inFIG.3E. On the other hand, the titanium atoms remain at the top surface of the bottom electrode400. In some embodiments, the second plasma treatment PT2is performed at a temperature ranging from about 200° C. to about 400° C. and a pressure ranging from about 100 mTorr to about 10 Torr. In some embodiments, during the second plasma treatment PT2, a flow rate of the second gas ranges from about 200 sccm to about 2000 sccm. In some embodiments, the power suppled in the chamber to generate plasma ranges from about 200 Watts to about 1000 Watts.

In some embodiments, the double plasma etching treatment ET is a combination of the first soaking treatment ST1, the first plasma treatment PT1, the second soaking treatment ST2, and the second plasma treatment PT2shown inFIG.3AtoFIG.3E. Referring toFIG.3AtoFIG.3E, the double plasma etching treatment ET removes a portion of the bottom electrode400. In other words, the double plasma etching treatment ET reduces an overall thickness of the bottom electrode400. In some embodiments, since the double plasma etching treatment ET removes oxygen atoms from titanium atoms, the double plasma etching treatment ET may also be referred to as a chemical reduction treatment of metal oxides.

AlthoughFIG.3AtoFIG.3Eillustrated that the double plasma etching treatment ET is utilized to remove a portion of the bottom electrode400, the disclosure is not limited thereto. In some embodiments, the double plasma etching treatment ET is also applicable for removing a portion of the barrier layer300shown inFIG.2D. Specifically, referring back toFIG.2DandFIG.2E, the barrier layer300and the bottom electrode400in the opening OP1as shown inFIG.2Eare being recessed. After recessing of the barrier layer300and the bottom electrode400, a recess R is formed above the remaining barrier layer300and the remaining bottom electrode400. For example, the recess R sinks from the top surface T200of the dielectric layer200toward the top surface T300of the barrier layer300and the top surface T400of the bottom electrode400. That is, as illustrated inFIG.2E, the top surface T300of the barrier layer300and the top surface T400of the bottom electrode400are located at a level height lower than that of the top surface T200of the dielectric layer200. Meanwhile, the top surface T300of the barrier layer300and the top surface T400of the bottom electrode400are located at the same level height. That is, the top surface T300of the barrier layer300and the top surface T400of the bottom electrode400are substantially coplanar.

In some embodiments, the barrier layer300and the bottom electrode400are recessed such that a depth DRof the recess R ranges from about 3 Å to about 10 Å. As illustrated inFIG.2E, a sum of a minimum thickness t000of the barrier layer, a thickness t400of the bottom electrode400, and the depth DRof the recess R is substantially equal to a thickness t200of the dielectric layer200. In some embodiments, the minimum thickness t000of the barrier layer ranges from about 1 nm to about 4 nm, and the thickness t400of the bottom electrode ranges from about 50 nm to about 80 nm. On the other hand, the thickness t200of the dielectric layer200ranges from about 52 nm to about 82 nm.

FIG.2Eillustrated that the double plasma etching treatment ET recesses both the barrier layer300and the bottom electrode400. However, the disclosure is not limited thereto. In some alternative embodiments, the double plasma etching treatment ET only recesses the bottom electrode400and the barrier layer300remains unchanged after the double plasma etching treatment ET. Such scenario will be described below in conjunction withFIG.4.

FIG.4is a schematic cross-sectional view illustrating an intermediate stage of the manufacturing method of the memory cell MC1in accordance with some alternative embodiments of the disclosure. Referring toFIG.4, both of the dielectric layer200and the barrier layer300are undamaged by the double plasma etching treatment ET. Meanwhile, a portion of the bottom electrode400is removed by the double plasma etching treatment ET. In other words, the double plasma etching treatment ET only recesses the bottom electrode400. As a result, the top surface T300of the barrier layer300and the top surface T200of the dielectric layer200are located at the same level height. That is, the top surface T300of the barrier layer300and the top surface T200of the dielectric layer200are substantially coplanar. On the other hand, the top surface T400of the bottom electrode400is located at a level height lower than that of the top surface T300of the barrier layer300and the top surface T200of the dielectric layer200.

FIG.2Eillustrated that the barrier layer300and the bottom electrode400are being recessed at the same rate through the double plasma etching treatment ET. However, the disclosure is not limited thereto. In some alternative embodiments, the barrier layer300and the bottom electrode400may be recessed by the double plasma etching treatment ET at different rates. Such scenario will be described below in conjunction withFIG.5.

FIG.5is a schematic cross-sectional view illustrating an intermediate stage of the manufacturing method of the memory cell MC2in accordance with some alternative embodiments of the disclosure. Referring toFIG.5, the double plasma etching treatment ET removes a portion of the bottom electrode400and a portion of the barrier layer300. However, the bottom electrode400is being removed at a rate different from that of the barrier layer300. As a result, the top surface T400of the bottom electrode400is located at a level height lower than that of the top surface T300of the barrier layer300. On the other hand, since the dielectric layer200is undamaged by the double plasma etching treatment ET, the top surface T200of the dielectric layer200is located at a level height higher than that of the top surface T300of the barrier layer300. In other words, the dielectric layer200, the barrier layer300, and the bottom electrode400exhibits a staircase shape from the cross-sectional view illustrated inFIG.5.

It should be noted that althoughFIG.2E,FIG.4, andFIG.5illustrated that the top surface T300of the barrier layer300and the top surface T400of the bottom electrode400are substantially flat, the disclosure is not limited thereto. In some alternative embodiments, the top surface T300of the barrier layer300is not flat and may have a roughness ranging from about 0.5 nm to about 2 nm. Similarly, the top surface T400of the bottom electrode is also not flat and may have a roughness ranging from about 1 nm to about 2 nm.

In some embodiments, when multiple memory cells are formed, the double plasma etching treatment ET allows consistence cell profile in different areas. For example, the cell profiles of different memory cells located in the iso-area and the dense-area are substantially identical. Therefore, the double plasma etching process ET may sufficiently reduce the loading effect derived from non-uniformity in the iso-area and the dense-area.

Referring toFIG.2F, after performing the double plasma etching treatment ET, a variable resistance layer500is deposited on the dielectric layer200, the barrier layer300, and the bottom electrode400. In some embodiments, the variable resistance layer500includes a phase change material. The phase change material may include a chalcogenide material, such as an indium (In)-antimony(Sb)-tellurium (Te) (IST) material or a germanium(Ge)-antimony(Sb)-tellurium(Te) (GST) material. In some embodiments, the ISG material includes In2Sb2Te5, In1Sb2Te4, In1Sb4Te7, or the like. On the other hand, the GST material includes Ge8Sb5Te8, Ge2Sb2Te5, Ge1Sb2Te4, Ge1Sb4Te7, Ge4Sb4Te7, Ge4SbTe2, Ge6SbTe2, or the like. The hyphenated chemical composition notation, as used herein, indicates the elements included in a particular mixture or compound, and is intended to represent all stoichiometries involving the indicated elements. In some alternative embodiments, other phase change materials may include Ge—Te, In—Se, Sb—Te, Ga—Sb, In—Sb, As—Te, Al—Te, Ge—Sb—Te, Te—Ge—As, In—Sb—Te, Te—Sn—Se, Ge—Se—Ga, Bi—Se—Sb, Ga—Se—Te, Sn—Sb—Te, In—Sb—Ge, Te—Ge—Sb—S, Te—Ge—Sn—O, Te—Ge—Sn—Au, Pd—Te—Ge—Sn, In—Se—Ti—Co, Ge—Sb—Te—Pd, Ge—Sb—Te—Co, Sb—Te—Bi—Se, Ag—In—Sb—Te, Ge—Sb—Se—Te, Ge—Sn—Sb—Te, Ge—Te—Sn—Ni, Ge—Te—Sn—Pd, and Ge—Te—Sn—Pt. In some embodiments, the variable resistance layer500is deposited by a suitable deposition process, such as CVD, PECVD, FCVD, HDP-CVD, SACVD, PVD, or ALD.

In some embodiments, the variable resistance layer500includes a body portion500aand a protruding portion500bconnected to the body portion500a. In some embodiments, the protruding portion500bprotrudes from a bottom surface B500of the body portion500a. For example, the protruding portion500bprotrudes from the body portion500ato fill up the recess R. In other words, the variable resistance layer500extends into the opening OP1to fill up the opening OP1. As illustrated inFIG.2F, the variable resistance layer500contacts the top surface T200of the dielectric layer200, the top surface T300of the barrier layer300, and the top surface T400of the bottom electrode400. That is, a portion of a bottom surface of the variable resistance layer500is coplanar with the top surface T200of the dielectric layer200, and another portion of the bottom surface of the variable resistance layer500is coplanar with the top surface T300of the barrier layer300and the top surface T400of the bottom electrode400. For example, the bottom surface B500aof the body portion500ais coplanar with the top surface T200of the dielectric layer200while a bottom surface B500bof the protruding portion500bis coplanar with the top surface T300of the barrier layer300and the top surface T400of the bottom electrode400. In some embodiments, the bottom surface B500bof the protruding portion500band the top surface T400of the bottom electrode400form a thermal conservation interface.

In some embodiments, since the protruding portion500bof the variable resistance layer500fills up the recess R, a thickness t500bof the protruding portion500bis substantially equal to the depth DRof the recess R. For example, the thickness t500bof the protruding portion500branges from about 3 Å to about 10 Å. As illustrated inFIG.2F, a sum of the minimum thickness t300of the barrier layer300, the thickness t400of the bottom electrode400, and the thickness t500bof the protruding portion500bof the variable resistance layer500is substantially equal to the thickness t200of the dielectric layer200.

In some embodiments, since the variable resistance layer500includes a phase change material, the variable resistance layer500has a variable phase representing a data bit. For example, the variable resistance layer500has a crystalline phase and an amorphous phase which are interchangeable. The crystalline phase and the amorphous phase may respectively represent a binary “1” and a binary “0,” or vice versa. Accordingly, the variable resistance layer500has a variable resistance that changes with the variable phase of the variable resistance layer500. For example, the variable resistance layer500has a high resistance in the amorphous phase and a low resistance in the crystalline phase.

In some embodiments, the phase of the variable resistance layer500is changed by heating. For example, the bottom electrode400heats the variable resistance layer500to a first temperature that induces crystallization of the variable resistance layer500, so as to change the variable resistance layer500to the crystalline phase (e.g., to set the subsequently formed memory cell MC). Similarly, the bottom electrode400heats the variable resistance layer500to a second temperature that melts the variable resistance layer500, so as to change the variable resistance layer500to the amorphous phase (e.g., to reset the subsequently formed memory cell MC). In some embodiments, the first temperature is lower than the second temperature. For example, the first temperature is about 100° C. to about 200° C. and the second temperature is about 500° C. to about 800° C. Since the phase change of the variable resistance layer500relies on the temperature difference, thermal confinement is crucial in the memory cell MC. As mentioned above, the protruding portion500bof the variable resistance layer500fills into the recess R such that the bottom surface B500bof the protruding portion500band the top surface T400of the bottom electrode400form the thermal conservation interface. Since the thermal conservation interface between the variable resistance layer500and the bottom electrode400is located within the recess R, the heat can be sufficiently conserved within the variable resistance layer500. In other words, the heat dissipation within the variable resistance layer500may be sufficiently reduced with the configuration shown inFIG.2F, thereby ensuring the performance of the subsequently formed memory cell MC.

In some embodiments, the amount of heat generated by the bottom electrode400varies in proportion to the current applied to the bottom electrode400. That is, the variable resistance layer500is heated up to a certain temperature when a certain current passes through the bottom electrode400. In other words, the reset current (IRESET) of the subsequently formed memory cell MC is related to the heat conserved within the variable resistance layer500. As mentioned above, since the protruding portion500bof the variable resistance layer500sufficiently aids the conservation of heat within the variable resistance layer500, the configuration shown inFIG.2Fmay also sufficiently lower the reset current of the subsequently formed memory cell MC. As such, the performance of the subsequently formed memory cell MC may be further enhanced.

Referring toFIG.2G, a top electrode600is formed on the variable resistance layer500. In some embodiments, a material of the top electrode600is the same as the material of the bottom electrode400. However, the disclosure is not limited thereto. In some alternative embodiments, the material of the top electrode600may be different from the material of the bottom electrode400. In some embodiments, the top electrode600includes a metal oxide material, such as TiOx, WOx, RuOx, a combination thereof, or the like. In some alternative embodiments, the top electrode600includes a metallic material, such as Ti, Co, Cu, AlCu, W, TiN, TiW, TiAl, TiAlN, Ru, a combination thereof, or the like. In some embodiments, the top electrode600is deposited through ALD, CVD, PVD, or the like.

Referring toFIG.2H, a hard mask layer700is formed on the top electrode600. In some embodiments, the hard mask layer700is made of non-metallic materials, such as SiO2, SiC, SiN, SiON, or the like. However, the disclosure is not limited thereto. In some alternative embodiments, the hard mask layer700is made of metallic materials, such as Ti, TiN, Ta, TaN, Al, or the like. In some embodiments, the hard mask layer700is formed by CVD, PECVD, ALD, PVD, a combination thereof, or the like.

Referring toFIG.2I, a photoresist layer PR1is formed on the hard mask layer700. In some embodiments, the photoresist layer PR1partially coves the hard mask layer700. In other words, at least a portion of the hard mask layer700is exposed by the photoresist layer PR1.

Referring toFIG.2IandFIG.2J, the hard mask layer700, the top electrode600, and the variable resistance layer500are patterned using the photoresist layer PR1as a mask. For example, an etching process is performed to remove a portion of the hard mask layer700, a portion of the top electrode600, and a portion of the variable resistance layer500that are not covered by the photoresist layer PR1. The etching process includes, for example, an anisotropic etching process such as dry etch or an isotropic etching process such as wet etch. Subsequently, the photoresist layer PR1is removed through a stripping process or the like. In some embodiments, the hard mask layer700, the top electrode600, and the variable resistance layer500are patterned simultaneously through the same process. As such, sidewalls of the hard mask layer700, sidewalls of the top electrode600, and sidewalls of the variable resistance layer500are aligned. As illustrated inFIG.2J, after the hard mask layer700, the top electrode600, and the variable resistance layer500are patterned, a portion of the dielectric layer200is exposed.

Referring toFIG.2K, a pair of spacers800is formed aside the hard mask layer700, the top electrode600, and the variable resistance layer500. For example, the pair of spacers800is disposed on the dielectric layer200and covers the sidewalls of the hard mask layer700, the sidewalls of the top electrode600, and the sidewalls of the variable resistance layer500. In some embodiments, the spacers800are formed of dielectric materials, such as silicon oxide, silicon nitride, SiCN, SiOCN, a combination thereof, or the like. In some embodiments, the spacers800are formed by a deposition followed by an anisotropic etch. AlthoughFIG.2Killustrated that the spacers800are single-layered structure, the disclosure is not limited thereto. In some alternative embodiments, the spacers800may be a multi-layered structure.

Referring toFIG.2L, an etch stop layer900is formed on the dielectric layer200, the pair of spacers800, and the hard mask layer700. For example, the etch stop layer900conformally covers the dielectric layer200, the pair of spacers800, and the hard mask layer700. In some embodiments, the etch stop layer900includes silicon carbide, silicon nitride, silicon oxynitride, silicon carbo-nitride, or multi-layers thereof. In some embodiments, the etch stop layer900is deposited using CVD, HDP-CVD, SACVD, molecular layer deposition (MLD), or other suitable methods.

Referring toFIG.2M, a dielectric layer1000and a hard mask layer1100are sequentially disposed on the etch stop layer900. For example, the dielectric layer1000is sandwiched between the etch stop layer900and the hard mask layer1100. In some embodiments, a material of the dielectric layer1000is the same as the material of the dielectric layer200. However, the disclosure is not limited thereto. In some alternative embodiments, the material of the dielectric layer1000is different from the material of the dielectric layer200. In some embodiments, the dielectric layer1000is formed of a low-k dielectric material having a k-value lower than about 3.0, about 2.5, or even lower. In some embodiments, the dielectric layer1000is formed of non-low-k dielectric materials such as silicon oxide, SiC, SiCN, SiOCN, or the like. In some alternative embodiments, the material of the dielectric layer1000includes polyimide, epoxy resin, acrylic resin, phenol resin, BCB, PBO, or any other suitable polymer-based dielectric material. The dielectric layer1000may be formed by suitable fabrication techniques such as spin-on coating, CVD, PECVD, or the like.

In some embodiments, a material of the hard mask layer1100is the same as the material of the hard mask layer700. However, the disclosure is not limited thereto. In some alternative embodiments, the material of the hard mask layer1100is different from the material of the hard mask layer700. In some embodiments, the hard mask layer1100is made of non-metallic materials, such as SiO2, SiC, SiN, SiON, or the like. However, the disclosure is not limited thereto. In some alternative embodiments, the hard mask layer1100is made of metallic materials, such as Ti, TiN, Ta, TaN, Al, or the like. In some embodiments, the hard mask layer1100is formed by CVD, PECVD, ALD, PVD, a combination thereof, or the like.

Referring toFIG.2N, a photoresist layer PR2is formed on the hard mask layer1100. In some embodiments, the photoresist layer PR2partially covers the hard mask layer1100. For example, the photoresist layer PR2has an opening OP2which exposes a portion of the hard mask layer1100.

Referring toFIG.2NandFIG.2O, the hard mask layer1100, the dielectric layer1000, the etch stop layer900, the hard mask layer700, and the top electrode600are patterned using the photoresist layer PR2as a mask. For example, an etching process is performed to remove a portion of the hard mask layer1100, a portion of the dielectric layer1000, a portion of the etch stop layer900, a portion of the hard mask layer700, and a portion of the top electrode600, so as to form an opening OP3. The etching process includes, for example, an anisotropic etching process such as dry etch or an isotropic etching process such as wet etch. Subsequently, the photoresist layer PR2is removed through a stripping process or the like. As illustrated inFIG.2O, the opening OP3penetrates through the hard mask layer1100, the dielectric layer1000, the etch stop layer900, and the hard mask layer700. On the other hand, although the opening OP3does not penetrate through the top electrode600, the opening OP3extends into the top electrode600.

Referring toFIG.2P, a conductive contact1200is formed in the opening OP3to form the memory cell MC. In some embodiments, the conductive contact1200is formed by filling a conductive material (not shown) into the opening OP3. The conductive material includes, for example, tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys therefore, and/or multi-layers thereof. Subsequently, a planarization process is performed to remove excess portions of the conductive material over the hard mask layer1100, so as to form the conductive contact1200. As illustrated inFIG.2P, the conductive contact1200penetrates through the hard mask layer1100, the dielectric layer1000, the etch stop layer900, and the hard mask layer700to be in physical contact with the top electrode600. As mentioned above, since the opening OP3extends into the top electrode600, the conductive contact1200, which fills up the opening OP3, also extends into the top electrode600. For example, as illustrated inFIG.2P, a bottom surface B1200of the conductive contact1200is located at a level height lower than that of a topmost surface T600of the top electrode600.

Referring toFIG.2PandFIG.1, some of the conductive vias32shown inFIG.1may serve as the conductive contact1200to electrically connect the memory cell MC with the conductive patterns34. In other words, the memory cell MC is electrically connected to the first transistor T1, the second transistor T2, and/or the conductive terminals70through the conductive vias32and the conductive patterns34of the interconnection structure30.

FIG.6is a schematic cross-sectional view of a memory cell MC1in accordance with some alternative embodiments of the disclosure. The memory cell MC1inFIG.6corresponds to the final product of the intermediate stage shown inFIG.4. Referring toFIG.6, the memory cell MC1is similar to the memory cell MC inFIG.2P, so the detailed descriptions thereof are omitted herein. However, in the memory cell MC1ofFIG.6, the barrier layer300not only laterally surrounds the bottom electrode400, but also laterally surrounds the protruding portion500bof the variable resistance layer500. For example, sidewalls of the protruding portion500bof the variable resistance layer500are in physical contact with the barrier layer300. In some embodiments, the top surface T300of the barrier layer300is coplanar with a bottom surface B500aof the body portion500aof the variable resistance layer500.

In some embodiments, with the configuration as shownFIG.6, the heat can be sufficiently conserved within the variable resistance layer500. In other words, the heat dissipation within the variable resistance layer500of the memory cell MC1may be sufficiently reduced. Moreover, since the protruding portion500bof the variable resistance layer500sufficiently aids the conservation of heat within the variable resistance layer500, the configuration shown inFIG.6may also sufficiently lower the reset current of the memory cell MC1. As such, the performance of the memory cell MC1may be ensured.

FIG.7is a schematic cross-sectional view of a memory cell MC2in accordance with some alternative embodiments of the disclosure. The memory cell MC2inFIG.7corresponds to the final product of the intermediate stage shown inFIG.5. Referring toFIG.7, the memory cell MC2is similar to the memory cell MC inFIG.2P, so the detailed descriptions thereof are omitted herein. However, in the memory cell MC2ofFIG.7, a portion of the protruding portion500bof the variable resistance layer500is being laterally surrounded by the barrier layer300while another portion of the protruding portion500bof the variable resistance layer500is being laterally surrounded by the dielectric layer200. For example, a portion of the sidewall of the protruding portion500bof the variable resistance layer500is in physical contact with the barrier layer300while another portion of the sidewall of the protruding portion500bof the variable resistance layer500is in physical contact with the dielectric layer200. In some embodiments, the top surface T300of the barrier layer300is coplanar with a portion of a bottom surface B500bof the protruding portion500bof the variable resistance layer500while the top surface T400of the bottom electrode400is coplanar with another portion of the bottom surface B500bof the protruding portion500bof the variable resistance layer500. In some embodiments, the protruding portion500bof the variable resistance layer500exhibits a staircase shape from the cross-sectional view illustrated inFIG.7.

In some embodiments, with the configuration as shownFIG.7, the heat can be sufficiently conserved within the variable resistance layer500. In other words, the heat dissipation within the variable resistance layer500of the memory cell MC2may be sufficiently reduced. Moreover, since the protruding portion500bof the variable resistance layer500sufficiently aids the conservation of heat within the variable resistance layer500, the configuration shown inFIG.7may also sufficiently lower the reset current of the memory cell MC2. As such, the performance of the memory cell MC2may be ensured.

In accordance with some embodiments of the disclosure, a memory cell includes a bottom electrode, a first dielectric layer, a variable resistance layer, and a top electrode. The first dielectric layer laterally surrounds the bottom electrode. A top surface of the bottom electrode is located at a level height lower than that of a top surface of the first dielectric layer. The variable resistance layer is disposed on the bottom electrode and the first dielectric layer. The variable resistance layer contacts the top surface of the bottom electrode and the top surface of the first dielectric layer. The top electrode is disposed on the variable resistance layer.

In accordance with some embodiments of the disclosure, an integrated circuit includes a substrate, a first transistor, and an interconnect structure. The first transistor is over the substrate. The interconnect structure is disposed on the substrate. The interconnect structure includes a memory cell. The memory cell includes a bottom electrode, a first dielectric layer, a variable resistance layer, and a top electrode. The first dielectric layer laterally surrounds the bottom electrode. The variable resistance layer is disposed on the bottom electrode and the first dielectric layer. The variable resistance layer includes a body portion and a protruding portion connected to the body portion. A bottom surface of the protruding portion and a top surface of the bottom electrode form a thermal conservation interface. The top electrode is disposed on the variable resistance layer.

In accordance with some embodiments of the disclosure, a manufacturing method of a memory cell includes at least the following steps. A first dielectric layer having an opening is provided. A bottom electrode is formed within the opening. A double plasma etching treatment is performed to recess the bottom electrode in the opening. A variable resistance layer is deposited over the first dielectric layer and the bottom electrode. The variable resistance layer fills up the opening. A top electrode is formed on the variable resistance layer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.