Patent ID: 12230361

While embodiments described in this disclosure may be susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the embodiments to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the appended claims.

DETAILED DESCRIPTION OF EMBODIMENTS

Accelerating the computation of convolutional neural networks through dedicated circuits may help to achieve compelling real-time user experiences and extended battery life in modern consumer electronics devices. One novel approach is use of mixed-signal “in-memory-compute” (IMC) arrays to further optimize the execution of MAC operations in CNN accelerators. IMC arrays may be capable of running CNN operations in an efficient manner in the analog domain rather than in the digital one. To achieve highly power-efficient MAC computations with IMC arrays, it may be desirable to maximize a number of open IMC memory rows at any given time such that a high level of parallelism in MAC computations is achieved within a given IMC array. Routing input data to a plurality of IMC rows may pose a challenge in the digital circuitry that surrounds the IMC array as well as the memories that feed data to the IMC block itself. For example, processing of an image with millions of pixels may require a demanding amount of pixel data to be fed to the IMC array at every clock cycle.

It is noted that, as used herein, an “open row” of an IMC is a row that contributes a value to the computation based on an input value to the open row and a value stored in a memory cell of the open row. A “closed row” may not contribute any values to the computation.

The present disclosure considers a novel digital circuit and data path which tightly surrounds an IMC array from a floorplan perspective and enables efficient, high-throughput delivery of data to the IMC array such that a plurality of rows in the IMC array may be open at any given clock cycle throughout the computation of a CNN layer. The disclosed embodiments address systems and methods for performing a MAC operation as part of a CNN. The disclosed methods may increase an efficiency for routing groups of input data to open rows of an IMC. An example of a novel in-memory compute circuit may include a memory circuit that performs a MAC operation by generating a set of products by combining received input values with respective weight values stored in rows of the memory circuit, and then combining the set of products to generate an accumulated output value. The in-memory compute circuit may further include a plurality of routing circuits coupled to sets of rows of the memory circuit, as well as a control circuit that is configured to cause the routing circuits to route groups of input values to different ones of the sets of rows over a plurality of clock cycles. The memory circuit may then generate an accumulated output value based on the routed groups of input values. Use of the disclosed IMC circuits may provide a capability to perform MAC operations more rapidly and/or using less power than traditional MAC circuits.

FIG.1illustrates a block diagram of one embodiment of a system that uses an in-memory compute circuit to perform a MAC operation on three groups of input values. As illustrated, system100includes in-memory compute circuit101that receives input values111-113. In-memory compute circuit101, in turn, includes control circuit105, routing circuits130a-130d(collectively routing circuits130), and memory circuit120that further includes a plurality of sets of rows125a-1251(collectively sets of rows125).

As illustrated, in-memory compute circuit101includes memory circuit120that is configured to generate a set of products150by combining received input values118a-118dwith respective weight values140stored in sets of rows125. Memory circuit may combine products150to generate accumulated output value155. In some embodiments, each set of rows125may include one or more rows each with a respective plurality of memory cells, such that the memory cells are organized into a plurality of rows and columns. Weight values140are stored in at least a portion of these memory cells. For example, before a particular convolution operation begins, a processor in system100may cause weight values140to be sent to in-memory compute circuit101where they are stored in the memory cells. In some embodiments, each weight value may correspond to a particular row and column. For example, weight value “w00” may correspond to memory cell in a first column in a first row, “w01” to a memory cell in the first column of a second row, “w10” to a memory cell in a second column of the first row, and so forth.

Routing circuits130, as shown, include routing circuit130acoupled to sets of rows125a-125c, routing circuit130bcoupled to sets of rows125d-125f, routing circuit130ccoupled to sets of rows125g-125i, and routing circuit130dcoupled to sets of rows125j-1251. Each routing circuit130receives a respective group of input values118a-118d. As illustrated, the groups of input values correspond to various sets of data received as input values111-113. For example, routing circuit130areceives input values118athat includes A1a, B1a, and C1a, that correspond to the “la” values from each of input values111(“A”),112(“B”), and113(“C”). For a given clock cycle, each of routing circuits130, as shown, routes the respective group of input values to one of the three respective sets of rows.

As shown, control circuit105is configured to cause routing circuit130ato route input values118ato different ones of set of rows125aover a first of a plurality of clock cycles. In two subsequent clock cycles, additional input values are routed to set of rows125b, and then to set of rows125c. After the third clock cycle, all three sets of rows125a-125cmay have been presented with respective input values. In a like manner, control circuit105is further configured to route, using routing circuit130b, input values118bto different ones of set of rows125dover the first plurality of clock cycles. In the two subsequent clock cycles, additional input values are routed to set of rows125e, and then to set of rows125f. Routing circuits130cand130droute, concurrent with routing circuits130aand130b, input values118cand118d, respectively, to sets of rows125g-1251such that all illustrated sets of rows125may be presented with input values by the end of the third clock cycle.

Control circuit105may further be configured to cause memory circuit120to generate, on a fourth clock cycle following the third clock cycle, accumulated output value155that is computed based on the routed groups of input values118. For example, after the input values118are routed to the respective sets of rows125, each memory cell in a given column of memory cells may output a respective signal that is indicative of a product of the corresponding input value118and the respective weight value140stored in the memory cell, thereby generating products150. Accumulated output value155may then be indicative of a total value of all products150in a single column of memory cells.

As shown, products150includes input values118a(A1a, B1a, and C1a) multiplied by respective weight values (w00, w01, and w02), resulting in values corresponding to A1a×w00, B1a×w01, and C1a×w02. Further products150include input values118b-118dmultiplied by their respective weight values140, as well as additional input values routed during subsequent clock cycles further multiplied by respective one of weight values140. Accordingly, the number of rows in memory circuit120determines a limit of the number of products that may be totaled for a given accumulated output value155.

By using a plurality of routing circuits to route input values to respective rows of a memory circuit of an in-memory compute circuit, a desired number of rows may be opened for use in a single multiply-accumulate (MAC) operation. A number of columns in the memory circuit may further determine a number of respective MAC operations that may be performed concurrently. Such an in-memory compute circuit may provide a faster and/or more efficient technique for performing a number of MAC operations as compared to traditional MAC circuits.

It is noted that system100, as illustrated inFIG.1, is merely an example. The illustration ofFIG.1has been simplified to highlight features relevant to this disclosure. Various embodiments may include different configurations of the circuit elements. For example, the number of rows in memory circuit120may be different based on a desired number of input values to be used in a single MAC operation. In a similar manner, the number of routing circuits may be different based on how quickly it is desired to perform a single MAC operation.

The system illustrated inFIG.1is shown in a simplified depiction for clarity. In-memory compute circuits may be implemented in various fashions. A more detailed example of operation of an in-memory compute circuit is shown inFIGS.2-4.

Moving toFIGS.2-4, the in-memory compute circuit ofFIG.1is shown with additional details for the routing circuits and the memory circuit. Each ofFIGS.2-4depicts system200at a different point in time, demonstrating how data may be routed to different rows of memory circuit120. In some embodiments, system200is an image processing circuit that may receive image data (including e.g., one or more frames of a video) and analyze the image to generate output data that is indicative of one or more characteristics of the image. System200includes in-memory compute circuit101, and memory buffer circuit260that includes memory ranges265a,265b, and265c(collectively memory ranges265). In-memory compute circuit101includes, as previously described, routing circuits130aand130bas well as memory circuit120. As illustrated inFIGS.2-4, memory circuit120includes digital-to-analog converters (DACs)280a-280r(collectively DACs280) coupled to respective rows of memory cells227. Memory circuit120further includes analog-to-digital converters (ADCs)285aand285bcoupled to respective columns of memory cells227. Routing circuits130each include three respective sets of flip-flop circuits, flip-flops233a,235a, and237afor routing circuit130aand flip-flops233b,235b, and237bfor routing circuit130b.

As illustrated inFIG.2, memory buffer circuit260includes a plurality of memory ranges, including memory ranges265, that are configured to return a portion of stored data concurrently. In-memory compute circuit101may retrieve data from each of memory ranges265concurrently. For example, a read of data from column0, row0of memory range265amay overlap a read of data from column0, row1of memory range265b, as well as a read of column0, row2of memory range265c. In various embodiments, memory ranges265may be implemented as separate memory circuits, as different arrays within a same memory circuit, as a single multi-port memory array, or a combination thereof.

A memory access circuit (e.g., memory access circuit545shown inFIG.5) may be configured to distribute pixel data of a digitized image among memory ranges265. As shown, a digitized image may include a series of rows of pixels, including rows0through8. These rows are distributed across memory ranges265such that consecutive rows are in different memory ranges, allowing three adjacent rows to be accessed in a same memory access cycle. For example, rows0,3, and6are in memory range265a, rows1,4, and7in memory range265b, and rows2,5, and8are in memory range265c. Accordingly, any three consecutive rows may be accessed concurrently.

Each row of pixel data in memory buffer circuit260is shown with three columns of pixel data, columns0-2. Data corresponding to one pixel is stored at each combination of row and column numbers, such that twenty-seven pixels are shown inFIG.2. Only three columns and nine rows are shown for clarity, the digitized image may include more rows and/or columns of pixel data. Each pixel includes four data values, labeled ‘a’, ‘b’, ‘c’, and ‘d.’ These four values may correspond to any suitable format for representing one pixel of an image. For example, values for a, b, and c may correspond to levels of red, green, and blue color, respectively, while a value of d indicates a level of luminance for the pixel. Other types of pixel data formats are contemplated, such as cyan, magenta, yellow, and key (CMYK), hue, saturation, and lightness (HSL), and hue, saturation, and value (HSV), and different formats may include a different number of values to represent a given pixel.

In some embodiments, the pixel data may represent characteristics of a respective pixel other than color. For example, the pixel data may correspond to a likelihood that a respective pixel is part of a particular shape. The values for a, b, c, and d may, respectively, indicate a probability that the pixel is included in a circle, square, triangle, and oval. In some embodiments, more complex shapes may be indicated within the pixel data, such as different types of animals, tools, furniture, and the like. In addition, it is noted that data for one pixel may include any suitable number of values, including a different number of values than four. For example, one type of pixel data may include a respective value for various polygons, from a triangle to a decagon.

As shown, in-memory compute circuit101, includes sets of rows of memory cells227, as well as DACs280and ADCS285aand285b. Each of DACs280is coupled to a respective row of memory cells227, while ADC285ais coupled to a first column of memory cells227and ADC285bis coupled to a second column of memory cells227. In-memory compute circuit101is configured to receive a plurality of weight values (w00to w117) to be stored in memory cells227for at least a portion of the sets of rows. The illustrated weight values are labeled by row and column numbers, e.g., wcr, where ‘c’ represents the column number (‘O’ or ‘1’) and ‘r’ represents the row (‘O’ to ‘17’). Accordingly, w00to w017are the weight values stored in rows0to17of column0and w10to w117are the weight values stored in rows0to17of column1.

During a series of cycles of clock275, in-memory compute circuit101is configured to route groups of the pixel data to the sets of rows of memory cells227. The groups of the pixel data include portions of stored pixel data from memory ranges265. In-memory compute circuit101uses routing circuits130to route these groups of pixel data to the rows of memory cells227. As shown, input values218ainclude three values,00a,01a, and02a. These values correspond to the ‘a’ pixel data from column0of rows0,1, and2(e.g., ‘Ola’ indicates pixel data from column0, row1, portion a, from memory range265b). Similarly, input values218bincludes values00b,01b, and02b, corresponding to the ‘b’ values for three pixels in column0, rows0,1, and2. Routing the pixel data includes, in response to a first transition of clock275, routing input values218aand218b, each indicative of different characteristics of a respective pixel, to respective ones of the respective rows of memory cells227. For example, input values218aare routed to rows6,7, and8using routing circuit130a, while input values218bare routed to rows15,16, and17using routing circuit130b. While not shown for clarity, pixel data corresponding to the ‘c’ and ‘d’ values of the same column of pixels may be sent to additional rows of memory cells using routing circuits130cand130dfromFIG.1.

As illustrated, each of input values218ais sent to a respective one of flip-flops233a, and similarly, input values218bare sent to flip-flops233b. Flip-flops233,235, and237may be implemented using any suitable clocked latching circuit to store the received values in response to an active transition of clock275. In various embodiments, an active transition may be rising, falling, or both. Each of flip-flop233,235, and237is coupled to an input of a respective one of DACs280.

FIG.3depicts system200after a subsequent transition of clock275. Routing circuit130ais configured, in response to a second transition of clock275, to shift input values218afrom flip-flops233ato flip-flops235a, and shift input values318ato flip-flops233a. In a similar manner, routing circuit130bis configured to shift input values218bfrom flip-flops233bto flip-flops235b, and shift input values318bto flip-flops233b. Input values318aand318b, as shown, correspond to pixel data from column1of rows0,1, and2, of memory buffer circuit260, e.g., a column of pixel data adjacent to the column of pixel data corresponding to input values218aand218b. In a similar manner as described above, pixel data corresponding to the ‘c’ and ‘d’ values of column1may be sent to the additional rows of memory cells using routing circuits130cand130dfromFIG.1. Routing circuits130cand130dmay be similarly configured to shift their respective values for column0from a first set of flip-flops to a second set of flip-flops, and shift the pixel data for column1into the first set of flip-flops.

FIG.4corresponds to system200after a third transition of clock275. As described, routing circuits130aand130bare further configured, in response to the third transition, to shift the input values218aand218b, respectively, to flip-flops237aand237b, and shift input values318aand318bto flip-flops235aand235b, respectively. Routing circuits130aand130breceive input values418aand418b, and shift these values, respectively, into flip-flops233aand233b. Although not shown, routing circuits130cand130dmay perform similar data shifts.

After the third transition of clock275, ‘a’ pixel data values for columns0,1, and2of memory buffer circuit260are routed to rows of memory circuit120coupled to DACs280a-280i, and ‘b’ pixel data values for the same columns are routed to rows of memory circuit120coupled to DACs280j-280r. As described, ‘a’ pixel data may correspond to levels of the color red in each pixel, while ‘b’ pixel data may correspond to levels of the color green in each pixel. Accordingly, each routing circuit130may route data associated with a particular characteristic of a corresponding pixel. It is noted that, in the current example, data for a three-by-three group of pixels has been routed to the rows of in-memory compute circuit101, comprised of columns0-2and rows0-2, with pixel data corresponding to row, column1, being in the center of this group. In-memory compute circuit101, in the present embodiment, is configured to perform one or more convolution operations on this three-by-three group.

These convolutions may include producing a plurality of products based on the input values and the weight values, and then adding sets of products together. In response to a fourth transition of clock275, in-memory compute circuit101may be further configured to generate a set of products using input values218,318,418and the stored weight values. For example, in a first convolution operation, input value ‘00a’ may be multiplied by w00to generate a first product, and similarly, input values Ola,02a,10a,11a,12a,20a, and so forth, multiplied by the corresponding weight values in the first column of memory cells227. These products in the first column may then be totaled to generate a first convolution value, e.g., output value490A. In second convolution operation, the same input values may be multiplied by a different set of weight values, w10-w117, to generate a second set of products which are then added together to generate a second convolution output, e.g., output value490B.

To generate and combine a given set of products, memory circuit120is configured to use respective ones of input values218,318, and418to generate a particular voltage levels on outputs of the corresponding DACs280. For example, DAC280amay generate a particular output voltage level based on a value of00a. DACs280b-280rmay similarly generate respective output voltage levels based on the respective input values. Memory circuit120may be further configured to generate an accumulated voltage level indicative of the accumulated output value using the outputs of the DACs and a first column of memory cells227. Memory cells227of the first column of memory cells227store respective weight values w00-w017, which allow a portion of the respective DAC280output voltage level to propagate through the corresponding memory cell227. For example, the output value of DAC280ais based on the value of00a. Weight value w00allows a portion of this output voltage level, e.g., in proportion to the value of w00, to propagate to the output of the memory cell227in which w00is stored. Outputs of at least a portion of memory cells227in the first column are accumulated to produce an accumulated voltage level. To generate accumulated output value490A, memory circuit120is further configured to use ADC285ato convert the accumulated voltage level of the column to a digital value.

A second column of memory cells227that store weight values w10-w117may be used to generate a second accumulated voltage level associated with a second convolution operation of the same input values. Memory circuit120may be further configured to use ADC285bto convert this second accumulated voltage level of the second column to output value490B. Although two convolution operations are shown inFIG.4, additional columns of memory cells227may be included to perform additional convolution operations. Various different weight values may be used in the different convolution operations to emphasize different characteristics and/or different pixels in a particular three-by-three group of pixels. After a set of output values490have been generated for a given group of pixels, the disclosed process may repeat for a subsequent group of pixels and may continue to repeat until all, or a desired portion of, the pixels of the digitized image have been included in at least one set of convolution operations.

It is noted that the embodiment ofFIGS.2-4are one depiction of a system for performing convolution operations for a digitized image. Although the illustrated embodiment was directed towards operations on a three-by-three group of pixel data, any suitable number of data points may be supported in other embodiments. Convolution analysis of a digitized image is used as an example use case. The techniques described in regards toFIGS.2-4may be applied to any suitable type of data in which multiply-accumulate functions may be used.

The descriptions ofFIGS.2-4describe use of pixel data from a digitized image as input values to the in-memory compute circuits disclosed herein. This description included references to processing multiple groups of pixel data from the digitized image. One example for how groups of pixel data may be processed is presented now inFIG.5.

FIG.5shows an example of a digitized image may be processed using the in-memory compute circuit ofFIGS.1-4. An example of different portions of digitized image515being processed at different times is illustrated. Digitized image515may correspond to any suitable type of image file format, such as raw image file format (RAW), Joint Photographic Experts Group (JPEG), Tagged Image File Format (TIFF), Windows bitmap (BMP), Portable Network Graphics (PNG), and the like. Digitized image515includes pixel data (a given pixel's data values represented by a, b, c, and d) arranged in columns and rows in an order in which the pixels may be rendered on a display. Although four columns and nine rows are shown, digitized image515may include any suitable number of columns and rows of pixel data. Memory access circuit545may be used to copy the pixel data in digitized image515to memory buffer circuit260.

Prior to time t0, memory access circuit545, as shown, is configured to distribute pixel data from the columns and rows of digitized image515among memory ranges265of memory buffer circuit260. The pixel data is distributed such that adjacent rows of digitized image515are copied into different ones of memory ranges265, thereby enabling pixel data from three adjacent rows to be read concurrently.

At time t0, a first portion of a three-by-three portion of digitized image515is processed using the techniques described above. This three-by-three portion includes a first group of input values that are included in adjacent pixels in a first column of pixels, e.g., column0, rows0-2, a second group of input values that are included in adjacent pixels in a second column of pixels (column1, rows0-2), adjacent to the first column of pixels. A third group of input values are included in adjacent pixels in a third column of pixels (column2, rows0-2), adjacent to the second column of pixels. These three columns of pixel data may be routed to respective rows of memory circuit120over the course of three consecutive cycles of clock275, as described above.

One or more output values may be generated during a fourth cycle. In-memory compute circuit101, as shown inFIGS.2-4, is configured to perform a convolution of the three-by-three portion of digitized image515. To perform the convolution, in-memory compute circuit101is configured, as previously described, to generate a set of output values, ones of the set of output values indicative of respective characteristics of the portion of the digitized image. For example, one particular output value of the set may provide an indication of a degree of contrast between a middle pixel of the three-by-three portion, e.g., the pixel at row1, column1, and the surrounding eight pixels.

At time t1, a next three-by-three portion of digitized image515may be processed. As illustrated, the second and third groups of input values are reused, and the first group of input values are replaced by a fourth group of input values. This fourth group of input values are included in adjacent pixels in a fourth column of pixels (column3, rows0-2), adjacent to the third column of pixels. After routing the groups of input values to appropriate rows of memory circuit120, another convolution operation may be performed, generating, for example, an indication of a degree of contrast between a middle pixel of the new three-by-three portion, e.g., the pixel at row1, column2, and the surrounding eight pixels. This process may repeat, shifting by one column of pixel data for each convolution operation, until all pixels of rows0-2have been processed.

At time t2, a different three-by-three portion of digitized image515may be processed by shifting down one row. As shown, the different three-by-three portion includes pixel data from three adjacent columns (columns0-2) and three adjacent rows (rows1-3). Convolution operations are repeated for rows1-3, and may span across all columns in these rows. This process for processing the pixel data in the rows of digitized image515may be repeated until all the pixel data from all rows and all columns has been suitably processed.

It is noted that the example ofFIG.5is one embodiment for demonstrating disclosed concepts. As stated, although only four columns and nine rows of pixel data are illustrated for brevity, digitized images may include any suitable number of rows and columns of pixel data. In addition, a three-by-three portion of the digitized image is shown as being processed for each convolution operation. In other embodiments, any suitably sized portion of a given digitized image may be processed for a given convolution. For example, a five-by-five portion, a four-by-six portion, and the like.

In the description ofFIG.5, portions of a digitized image are described as including several adjacent rows and columns of pixel data. These rows of pixel data may be buffered in a memory buffer circuit with a plurality of memory ranges, and then routed to various rows of memory cells in an in-memory compute circuit. The routing of the pixel data from memory ranges265may be implemented using a variety of techniques. One such technique is described inFIG.6.

FIG.6shows an example of a system for routing input values from a memory buffer to an in-memory compute circuit. System200includes the same elements as described in regards toFIGS.1-4. InFIGS.2-4, input data from rows0-2is routed to particular rows of memory cells in memory circuit120. InFIG.6, input data from rows1-3is routed to memory circuit120. Operations associated withFIG.6may take place after input values from all columns in rows0-2has been processed.

As illustrated, input values from rows of a different three-by-three portion of memory buffer circuit260may be routed to respective subsets of the rows of memory circuit120. It is noted that two of the three rows of the different three-by-three portion include the same input values as the particular portion described inFIGS.2-4. In some embodiments of in-memory compute circuit101, memory ranges265may be hardwired to particular inputs of routing circuits130. For example, memory range265amay be wired to respective first inputs of routing circuits130, memory range265bto a second input, and memory range to a third input.

In-memory compute circuit101may be configured to, during a series of clock cycles shift the input values of rows1and2to the first and second sets of rows, respectively. As shown inFIG.6, input values618aand618beach include one input value from each of rows1-3. The top value, “23a,” corresponds to an ‘a’ value from column2, row3, from memory range265a. The second value, “21a,” is an ‘a’ value from column2, row1from memory range265b, and the third value, “22a,” is an ‘a’ value from column2of row2, from memory range265c. To reduce a time for processing data in memory buffer circuit260, the weight values stored in memory circuit120may remain constant, for at least a given set of data values stored in memory buffer circuit260. Accordingly, to apply the correct weight values for a given three-by-three portion, a top row of the portion should be routed to a top input of routing circuits130, a middle row to the middle input, and a bottom row to the bottom input.

Accordingly, values from row3should be routed to the bottom input, and values from rows1and2should be routed to the top and middle inputs respectively. Since, as described for the current example, memory ranges265a,265b, and265care hardwired to the top, middle, and bottom inputs, respectively, input values618aare shifted using multiplexing circuit (MUX)631a, such that the row3value (23a) is shifted down to the bottom one of flip-flops233a, the row1value (21a) is shifted up to the top one of flip-flops233a, and the row2value (22a) is shifted up to the middle one of flip-flops233a. In a similar manner, MUX631bmay be used to shift input values618bto the desired ones of flip-flops233b. It is noted that MUXs631aand631bmay include circuits for routing any of the respective three input values into any of the respective three flip-flops.

As shown, input values are routed into flip-flops233a,233b,235a,235b,237a, and237bsuch that input values from row1are in the top flip-flops, values from row2are in the middle flip-flops, and values from row3are in the bottom flip-flops. In-memory compute circuit101may then generate one or more sets of products using the values from rows1-3and the stored weight values, and generate accumulated output values690A and690B by accumulating at least a subset of these sets of products. The generated output values690A and690B may be stored in memory buffer circuit260, such as in row9, or stored in a different memory circuit such as a system memory (not shown).

In some embodiments, in-memory compute circuit101may be further configured, at a subsequent point in time, to route accumulated output values690A and690B as input values to a particular set of the rows of memory cells. For example, output values690A and690B may be included, in a subsequent cycle, in input values618aand618balong with values from rows2and3. In another example, input values618aand618bmay include a plurality of rows of previously stored output values, such that all three input values correspond to generated output values from memory circuit120. Such a feedback of generated outputs may allow for a further processing of the characteristics of the input values stored in memory buffer circuit260. For example, one round of convolution operations on a given image may produce output values indicative of an inclusion of a respective pixel being included in various geometric shapes. A subsequent round of convolution operations may utilize the geometric shape data to produce output values indicative of an inclusion of the respective pixel being included in images of various animals.

It is further noted that the example ofFIG.6is merely for demonstrating the disclosed techniques. Although only two sets routing circuits are illustrated, additional routing circuits may be included, such as routing circuits130cand130dinFIG.1. Although two output values are shown, other embodiments may include any suitable number of output values generated in a given clock cycle.

In the descriptions ofFIGS.1-6, the memory cells of the memory circuit are described as generating an output voltage level that is indicative of a product of a respective input value and stored weight value. Such memory cells may be implemented in a variety of fashions.FIG.7illustrates one such implementation.

Turning toFIG.7, a block diagram of an embodiment of memory cells used in an in-memory compute circuit is depicted. Many different types of memory cell circuits may be used to implement an IMC circuit.FIG.7is an embodiment demonstrating one such type of memory cell circuit. Other memory cells, for example, may include flash memory cells, or SRAM cells with an addition of capacitors. Memory circuit120, as illustrated, includes DACs280aand280b, ADCs285aand285b, and memory cells727aa,727ab,727ba, and727bb(collectively memory cells727). Although a two-by-two array of memory cells are shown, any suitable number of rows and columns of memory cells727may be implemented.

As described above, memory circuit120may be configured to perform multiply-accumulate compute (MAC) operations using input values and weight values as the operands. As shown, each column of memory cells727may be used to generate a respective MAC operation, with each MAC operation using the same input values, but independent weight values.

Prior to performing a MAC operation, memory cells727may be loaded with weight values, such as weight values140inFIG.1. As illustrated, memory cells727aa,727ab,727ba, and727bbstore weight values w00, w01, w10, and w11, respectively. Each weight value may determine an amount of transconductance of a respective memory cell727between an output of one of DACs280to an input of one of ADCs285.

After the weight values140have been stored, input values are routed to respective rows of memory circuit120. As shown, input value718ais routed to an input of DAC280aand input value718bis routed to an input of DAC280b. DACs280aand280beach generate a respective one of output voltages770aand770busing the respective input value718. Inputs to memory cells727on a same row receive the same output voltage. Accordingly, memory cells727aaand727baeach receive output voltage770aat their respective inputs and memory cells727aband727bbeach receive output voltage770b. Based on the weight value stored in a respective memory cell727, the amount of transconductance determines an amount of current that is allowed to pass from the output of a given DAC280to an input of a given ADC285. Memory cells727may, therefore, be configured to pass an amount of current that is indicative of the input value multiplied by the weight value. The passed currents contribute to an accumulated voltage775aor775bthat is applied to an input of each of ADCs285. Each memory cell in a given column essentially adding its respective current to a total current for the given column. This total current may be converted to an accumulated voltage775by passing the current through a resistive impedance, a higher total current producing a higher accumulated voltage770.

As shown, accumulated voltage775amay be determined based on input value718amultiplied by w00plus input value718bmultiplied by w01plus input values for any additional rows of memory cells727multiplied weight values stored in those additional rows of memory cells. In a similar manner, accumulated voltage775bmay be determined based on input value718amultiplied by w10plus input value718bmultiplied by w11plus input values for additional rows of memory cells727multiplied corresponding weight values. The weight values, therefore, may enable a particular input value, e.g., input value718a, to contribute more to one accumulated voltage770and less to another. For example, values of w00and w10may be chosen to produce a higher transconductance in memory cell727aa, than in memory cell727ba, thereby resulting in output voltage770acontributing more current to accumulated voltage775athan to accumulated voltage775b.

As illustrated, ADCs285convert the respective accumulated voltages775ato corresponding digital values. ADC285a, for example, may be configured to produce a digital value that is proportional to a level of accumulated voltage775ato produce output value790a. ADC285bmay be similarly configured to generate output value790bproportional to a level of accumulated voltage775b. Output values790may, accordingly, be indicative of MAC operations based on input values718and weight values in the respective columns of memory cells.

ADCs285may be configured to generate output values790with any suitable number of bits of accuracy. In some embodiments, DACs280and ADCs285may be configured to generate a set of output values790in a single clock cycle (e.g., a cycle of clock275inFIGS.2-4and6). In other embodiments, multiple clock cycles may be used to produce a given set of output values790.

It is noted that the memory circuit ofFIG.7is one example. Only elements for demonstrating the disclosed concepts have been illustrated. In other embodiments, additional elements may be included. For example, some embodiments may include additional rows and/or columns of memory cells and corresponding DACs and ADCs. Each column, in some embodiments, my include a resistive element for converting currents into proportionate voltage levels.

The in-memory compute circuits and techniques described above in regards toFIGS.1-7may be operated using a variety of methods. Two methods associated with operation of an in-memory compute circuit are described below in regards toFIGS.8-9.

Proceeding toFIG.8, a flow diagram for an embodiment of a method for performing a multiply-accumulate compute operation by an in-memory compute circuit is shown. As shown, the MAC operation is used to multiply a plurality of input values by a corresponding plurality of weight values, and then total the resulting products. Such MAC operations may be used in a variety of different applications, including for example, operations in a neural network, image analysis, digital-signal processing such as power conversion and motor control, and other applications. Method800may be performed by, for example, in-memory compute circuit101inFIGS.1-4and6. Referring collectively toFIGS.1and8, method800begins in block810.

At block810, method800includes, during a series of clock cycles, routing a plurality of groups of input values118to different ones of sets of rows125of in-memory compute circuit101. As shown inFIG.1, routing circuits130a-130dare used to route input values118a-118d, respectively, to particular ones of sets of rows125. This first group of input values may be routed to first sets of rows in a first clock cycle. Additional groups of input values from input values111-113may be routed in additional ones of the series of clock cycles. In various embodiments, routing circuits130may route the additional groups to different ones of the sets of rows125, or shift the previously routed groups to different sets of rows and route each additional group to the first sets of rows.

Method800, at block820, further includes, during a subsequent clock cycle following the series of clock cycles, performing operations of blocks830and840to perform a MAC operation. After input values118have been routed during the series of clock cycles, method800, at block830, includes combining, by in-memory compute circuit101, the groups of input values118with a set of weight values140stored in sets of rows125to generate a set of products150. Weight values140may be stored in memory cells of memory circuit120before operations of block810are performed.

In some embodiments, memory circuit120includes a DAC for at least some of the rows of memory cells, such as DACs280shown inFIGS.2-4and6-7. Each of input values118may cause a respective DAC to generate an output voltage with a level that is dependent upon the respective input value. Memory cells of memory circuit120may generate a particular current based on the output voltage of a respective DAC and a weight value stored in the corresponding memory cell. The generated current may, therefore, be indicative of a product of a corresponding input value and weight value.

Method800also includes, at block840, combining the set of products150to generate accumulated output value155. In-memory compute circuit101may generate accumulated output values155that are indicative of a total of the input values multiplied by a particular portion of the weight values. As illustrated, combining the groups of input values118with weight values140to generate products150includes generating a single analog signal for respective ones of products150. As described in regards toFIG.7, currents generated in block830may be combined to generate a single current that corresponds to the sum of the generated currents from a given column of memory circuit120. This total current may flow through a particular resistive impedance to generate a corresponding accumulated voltage level. This accumulated voltage level may then be sampled by an ADC (e.g., ADCs285inFIGS.2-4and6-7) to generate a given one of accumulated output values155. Each of accumulated output values155may, therefore, be indicative of a MAC operation using the routed input values and one column of weight values. In some embodiments, multiple MAC operations may be performed in parallel using the same routed input values and different columns of weight values.

In some embodiments, method800may end in block840, or in other embodiments, may repeat some or all operations. For example, method800may return to block810to perform another set of MAC operations using different groups of input values. It is noted that the method ofFIG.8is merely an example for performing a MAC operation using an in-memory compute circuit.

Moving now toFIG.9, a flow diagram for an embodiment of a method for using pixel data from a digitized image as input values for a MAC operation is shown. In a similar manner as method800, method900may be performed by an in-memory compute circuit, such as in-memory compute circuit101inFIGS.1-4and6. Referring collectively toFIGS.2-4, and9, method900begins in block910.

Method900at block910, includes, during a first of a series of cycles of clock275, routing pixel data corresponding to adjacent pixels in a first column of pixels. As illustrated inFIG.2, memory buffer circuit260may store pixel data from a digitized image, such as digitized image515inFIG.5. The pixel data may be distributed by rows across different memory ranges265of memory buffer circuit260, such that any three consecutive rows of pixel data are spread across all three memory ranges265. Each of the three memory ranges265may allow concurrent access, thereby enabling three consecutive rows of pixel data to be retrieved from memory buffer circuit260in a same cycle of clock275and routed to a first set of rows of memory circuit120.

As shown, routing the pixel data includes routing a plurality of values indicative of different characteristics of a given pixel to respective ones of a set of respective rows. For example, each set of pixel data illustrated in memory buffer circuit260includes four values, indicated by the letters ‘a’, ‘b’, ‘c’, and ‘d.’ As described above, the various values included in the pixel data may correspond to a color of a corresponding pixel, and/or probabilities of the corresponding pixel is included within a particular shape or object. Each of routing circuits130may route data for three pixels in a given column for a given one of the characteristics. Input values218aincludes values for the ‘a’ characteristic of pixels in column0, rows0-2. In a similar manner, input values218bincludes values for the ‘b’ characteristic of the same pixels. Although not shown inFIG.2, two more sets of values from the same column of three pixels, corresponding to the ‘c’ and ‘d’ characteristics, may be routed by routing circuits130cand130d(fromFIG.1).

At block920, method900includes, during a second cycle of clock275, routing pixel data corresponding to adjacent pixels in a second column of pixels that are adjacent to the first column of pixels. As shown inFIG.3, an adjacent column of pixel data (column1, rows0-2) is routed by routing circuits130during a second cycle of clock275. In the illustrated embodiment, pixel data from column0is shifted to a second set of rows of memory circuit120, different from the first set, while pixel data from column1is routed to the first set of rows. In other embodiments, pixel data from column0may remain in the first set of rows, while the pixel data from column1is routed to the second set of rows.

At block930, the method also includes, during a third cycle of clock275, routing pixel data corresponding to adjacent pixels in a third column of pixels that are adjacent to the second column of pixels. As shown inFIG.4, a next adjacent column of pixel data (column2, rows0-2) is routed by routing circuits130during a third cycle of clock275. As depicted, pixel data from column0is shifted to a third set of rows of memory circuit120, different from the first and second sets, pixel data from column1is shifted to the second set of rows, and pixel data from column2is routed to the first set of rows. In other embodiments, pixel data from columns0and1may remain in the first and second sets of rows, while the pixel data from column2is routed to the third set of rows.

Method900includes, at block940, during a fourth cycle of clock275, generating the accumulated output value as a convolution of a portion of digitized image515. After the pixel data from column2has been routed, a particular three-pixel by three-pixel portion of digitized image515is presented to memory circuit120. Weight values may be selected and stored in memory circuit120such that memory circuit120is configured to perform one or more convolution operations on the portion of digitized image515. Such convolutions may, for example, generate one or more output values490that are indicative of a relationship between one of the pixels of the three-by-three portion and the surrounding eight pixels, such as a level of contrast in color and/or brightness between the pixels. Such convolution data may be used, in some embodiments, to identify particular shapes and/or objects in digitized image515.

In some embodiments, method900may end in block940, or in other embodiments, may repeat some or all operations. For example, method900may return to block910, at a subsequent point in time, to route pixel data of rows of a different portion of digitized image515to the first, second and third sets of rows of memory circuit120. In some cases, one or two of the three rows of the different three-by-three portion of the image may include the same pixels as the particular three-by-three portion of the image. For example, in a subsequent convolution operation, the different portion may include pixels included in columns0-2, rows1-3.

It is noted that methods800and900are examples for performing MAC operations using an in-memory compute circuit. Performance of various operations of methods800and900may be performed concurrently. For example, blocks910-930of method900may correspond to block810of method800in some embodiments. Although use of a three-by-three portion of the image is disclosed, any suitable number of rows and columns may be used in other embodiments. For example, five-by-five, five-by-seven, one-by-one, and other size image portions are contemplated.

Use of the circuits and methods disclosed herein may enable an in-memory compute circuit to be implemented that performs multiple MAC operations in a few clock cycles, e.g., in four clock cycles as described above. An amount of input values that may be included in these MAC operations may be determined by a number and size of the disclosed routing cycles. Such an in-memory compute circuit may provide a capability to perform such MAC operations more rapidly and/or efficiently as compared to other MAC implementations.

FIGS.1-9illustrate circuits and methods for a system that includes an in-memory compute circuit for performing MAC operations. Any embodiment of the disclosed systems may be included in one or more of a variety of computer systems, such as a desktop computer, laptop computer, smartphone, tablet, wearable device, and the like. In some embodiments, the circuits described above may be implemented on a system-on-chip (SoC) or other type of integrated circuit. A block diagram illustrating an embodiment of computer system1000is illustrated inFIG.10. Computer system1000may, in some embodiments, include any disclosed embodiment of system100or200.

In the illustrated embodiment, the system1000includes at least one instance of a system on chip (SoC)1006which may include multiple types of processing circuits, such as a central processing unit (CPU), a graphics processing unit (GPU), or otherwise, a communication fabric, and interfaces to memories and input/output devices. In some embodiments, one or more processors in SoC1006includes multiple execution lanes and an instruction issue queue. In various embodiments, SoC1006is coupled to external memory1002, peripherals1004, and power supply1008.

A power supply1008is also provided which supplies the supply voltages to SoC1006as well as one or more supply voltages to the memory1002and/or the peripherals1004. In various embodiments, power supply1008represents a battery (e.g., a rechargeable battery in a smart phone, laptop or tablet computer, or other device). In some embodiments, more than one instance of SoC1006is included (and more than one external memory1002is included as well).

The memory1002is any type of memory, such as dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of the SDRAMs such as mDDR3, etc., and/or low power versions of the SDRAMs such as LPDDR2, etc.), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memory devices are coupled onto a circuit board to form memory modules such as single inline memory modules (SIMMs), dual inline memory modules (DIMMs), etc. Alternatively, the devices are mounted with a SoC or an integrated circuit in a chip-on-chip configuration, a package-on-package configuration, or a multi-chip module configuration.

The peripherals1004include any desired circuitry, depending on the type of system1000. For example, in one embodiment, peripherals1004includes devices for various types of wireless communication, such as Wi-Fi, Bluetooth, cellular, global positioning system, etc. In some embodiments, the peripherals1004also include additional storage, including RAM storage, solid state storage, or disk storage. The peripherals1004include user interface devices such as a display screen, including touch display screens or multitouch display screens, keyboard or other input devices, microphones, speakers, etc.

As illustrated, system1000is shown to have application in a wide range of areas. For example, system1000may be utilized as part of the chips, circuitry, components, etc., of a desktop computer1010, laptop computer1020, tablet computer1030, cellular or mobile phone1040, or television1050(or set-top box coupled to a television). Also illustrated is a smartwatch and health monitoring device1060. In some embodiments, the smartwatch may include a variety of general-purpose computing related functions. For example, the smartwatch may provide access to email, cellphone service, a user calendar, and so on. In various embodiments, a health monitoring device may be a dedicated medical device or otherwise include dedicated health related functionality. For example, a health monitoring device may monitor a user's vital signs, track proximity of a user to other users for the purpose of epidemiological social distancing, contact tracing, provide communication to an emergency service in the event of a health crisis, and so on. In various embodiments, the above-mentioned smartwatch may or may not include some or any health monitoring related functions. Other wearable devices1070are contemplated as well, such as devices worn around the neck, devices attached to hats or other headgear, devices that are implantable in the human body, eyeglasses designed to provide an augmented and/or virtual reality experience, and so on.

System1000may further be used as part of a cloud-based service(s)1080. For example, the previously mentioned devices, and/or other devices, may access computing resources in the cloud (i.e., remotely located hardware and/or software resources). Also illustrated inFIG.10is the application of system1000to various modes of transportation1090. For example, system1000may be used in the control and/or entertainment systems of aircraft, trains, buses, cars for hire, private automobiles, waterborne vessels from private boats to cruise liners, scooters (for rent or owned), and so on. In various cases, system1000may be used to provide automated guidance (e.g., self-driving vehicles), general systems control, and otherwise.

It is noted that the wide variety of potential applications for system1000may include a variety of performance, cost, and power consumption requirements. Accordingly, a scalable solution enabling use of one or more integrated circuits to provide a suitable combination of performance, cost, and power consumption may be beneficial. These and many other embodiments are possible and are contemplated. It is noted that the devices and applications illustrated inFIG.10are illustrative only and are not intended to be limiting. Other devices are possible and are contemplated.

As disclosed in regards toFIG.10, computer system1000may include one or more integrated circuits included within a personal computer, smart phone, tablet computer, or other type of computing device. A process for designing and producing an integrated circuit using design information is presented below inFIG.11.

FIG.11is a block diagram illustrating an example of a non-transitory computer-readable storage medium that stores circuit design information, according to some embodiments. The embodiment ofFIG.11may be utilized in a process to design and manufacture integrated circuits, for example, systems100or200as shown inFIGS.1-4. In the illustrated embodiment, semiconductor fabrication system1120is configured to process the design information1115stored on non-transitory computer-readable storage medium1110and fabricate integrated circuit1130(e.g., system100or200) based on the design information1115.

Non-transitory computer-readable storage medium1110, may comprise any of various appropriate types of memory devices or storage devices. Non-transitory computer-readable storage medium1110may be an installation medium, e.g., a CD-ROM, floppy disks, or tape device; a computer system memory or random-access memory such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; a non-volatile memory such as a Flash, magnetic media, e.g., a hard drive, or optical storage; registers, or other similar types of memory elements, etc. Non-transitory computer-readable storage medium1110may include other types of non-transitory memory as well or combinations thereof. Non-transitory computer-readable storage medium1110may include two or more memory mediums which may reside in different locations, e.g., in different computer systems that are connected over a network.

Design information1115may be specified using any of various appropriate computer languages, including hardware description languages such as, without limitation: VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. Design information1115may be usable by semiconductor fabrication system1120to fabricate at least a portion of integrated circuit1130. The format of design information1115may be recognized by at least one semiconductor fabrication system, such as semiconductor fabrication system1120, for example. In some embodiments, design information1115may include a netlist that specifies elements of a cell library, as well as their connectivity. One or more cell libraries used during logic synthesis of circuits included in integrated circuit1130may also be included in design information1115. Such cell libraries may include information indicative of device or transistor level netlists, mask design data, characterization data, and the like, of cells included in the cell library.

Integrated circuit1130may, in various embodiments, include one or more custom macrocells, such as memories, analog or mixed-signal circuits, and the like. In such cases, design information1115may include information related to included macrocells. Such information may include, without limitation, schematics capture database, mask design data, behavioral models, and device or transistor level netlists. As used herein, mask design data may be formatted according to graphic data system (gdsii), or any other suitable format.

Semiconductor fabrication system1120may include any of various appropriate elements configured to fabricate integrated circuits. This may include, for example, elements for depositing semiconductor materials (e.g., on a wafer, which may include masking), removing materials, altering the shape of deposited materials, modifying materials (e.g., by doping materials or modifying dielectric constants using ultraviolet processing), etc. Semiconductor fabrication system1120may also be configured to perform various testing of fabricated circuits for correct operation.

In various embodiments, integrated circuit1130is configured to operate according to a circuit design specified by design information1115, which may include performing any of the functionality described herein. For example, integrated circuit1130may include any of various elements shown or described herein. Further, integrated circuit1130may be configured to perform various functions described herein in conjunction with other components.

As used herein, a phrase of the form “design information that specifies a design of a circuit configured to . . . ” does not imply that the circuit in question must be fabricated in order for the element to be met. Rather, this phrase indicates that the design information describes a circuit that, upon being fabricated, will be configured to perform the indicated actions or will include the specified components.

The present disclosure includes references to “embodiments,” which are non-limiting implementations of the disclosed concepts. References to “an embodiment,” “one embodiment,” “a particular embodiment,” “some embodiments,” “various embodiments,” and the like do not necessarily refer to the same embodiment. A large number of possible embodiments are contemplated, including specific embodiments described in detail, as well as modifications or alternatives that fall within the spirit or scope of the disclosure. Not all embodiments will necessarily manifest any or all of the potential advantages described herein.

Unless stated otherwise, the specific embodiments are not intended to limit the scope of claims that are drafted based on this disclosure to the disclosed forms, even where only a single example is described with respect to a particular feature. The disclosed embodiments are thus intended to be illustrative rather than restrictive, absent any statements to the contrary. The application is intended to cover such alternatives, modifications, and equivalents that would be apparent to a person skilled in the art having the benefit of this disclosure.

Particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure. The disclosure is thus intended to include any feature or combination of features disclosed herein (either explicitly or implicitly), or any generalization thereof. Accordingly, new claims may be formulated during prosecution of this application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in the specific combinations enumerated in the appended claims.

For example, while the appended dependent claims are drafted such that each depends on a single other claim, additional dependencies are also contemplated, including the following: Claim3(could depend from any of claims1-2); claim4(any preceding claim); claim5(claim4), etc. Where appropriate, it is also contemplated that claims drafted in one statutory type (e.g., apparatus) suggest corresponding claims of another statutory type (e.g., method).

Because this disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. Public notice is hereby given that the following paragraphs, as well as definitions provided throughout the disclosure, are to be used in determining how to interpret claims that are drafted based on this disclosure.

References to the singular forms such “a,” “an,” and “the” are intended to mean “one or more” unless the context clearly dictates otherwise. Reference to “an item” in a claim thus does not preclude additional instances of the item.

The word “may” is used herein in a permissive sense (i.e., having the potential to, being able to) and not in a mandatory sense (i.e., must).

The terms “comprising” and “including,” and forms thereof, are open-ended and mean “including, but not limited to.”

When the term “or” is used in this disclosure with respect to a list of options, it will generally be understood to be used in the inclusive sense unless the context provides otherwise. Thus, a recitation of “x or y” is equivalent to “x or y, or both,” covering x but not y, y but not x, and both x and y. On the hand, a phrase such as “either x or y, but not both” makes clear that “or” is being used in the exclusive sense.

A recitation of “w, x, y, or z, or any combination thereof” or “at least one of . . . w, x, y, and z” is intended to cover all possibilities involving a single element up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrasings cover any single element of the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase “at least one of . . . w, x, y, and z” thus refers to at least one of element of the set [w, x, y, z], thereby covering all possible combinations in this list of options. This phrase is not to be interpreted to require that there is at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

Various “labels” may proceed nouns in this disclosure. Unless context provides otherwise, different labels used for a feature (e.g., “first circuit,” “second circuit,” “particular circuit,” “given circuit,” etc.) refer to different instances of the feature. The labels “first,” “second,” and “third” when applied to a particular feature do not imply any type of ordering (e.g., spatial, temporal, logical, etc.), unless stated otherwise.

Within this disclosure, different entities (which may variously be referred to as “units,” “circuits,” other components, etc.) may be described or claimed as “configured” to perform one or more tasks or operations. This formulation—[entity] configured to [perform one or more tasks]—is used herein to refer to structure (i.e., something physical). More specifically, this formulation is used to indicate that this structure is arranged to perform the one or more tasks during operation. A structure can be said to be “configured to” perform some task even if the structure is not currently being operated. Thus, an entity described or recited as “configured to” perform some task refers to something physical, such as a device, circuit, memory storing program instructions executable to implement the task, etc. This phrase is not used herein to refer to something intangible.

The hardware circuits may include any combination of combinatorial logic circuitry, clocked storage devices such as flops, registers, latches, etc., finite state machines, memory such as static random access memory or embedded dynamic random access memory, custom designed circuitry, analog circuitry, programmable logic arrays, etc. Similarly, various units/circuits/components may be described as performing a task or tasks, for convenience in the description. Such descriptions should be interpreted as including the phrase “configured to.”

In an embodiment, hardware circuits in accordance with this disclosure may be implemented by coding the description of the circuit in a hardware description language (HDL) such as Verilog or VHDL. The HDL description may be synthesized against a library of cells designed for a given integrated circuit fabrication technology, and may be modified for timing, power, and other reasons to result in a final design database that may be transmitted to a foundry to generate masks and ultimately produce the integrated circuit. Some hardware circuits or portions thereof may also be custom-designed in a schematic editor and captured into the integrated circuit design along with synthesized circuitry. The integrated circuits may include transistors and may further include other circuit elements (e.g. passive elements such as capacitors, resistors, inductors, etc.) and interconnect between the transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuits, and/or discrete elements may be used in some embodiments. Alternatively, the HDL design may be synthesized to a programmable logic array such as a field programmable gate array (FPGA) and may be implemented in the FPGA.

The term “configured to” is not intended to mean “configurable to.” An unprogrammed FPGA, for example, would not be considered to be “configured to” perform some specific function. This unprogrammed FPGA may be “configurable to” perform that function, however.

Reciting in the appended claims that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112(f) for that claim element. Should Applicant wish to invoke Section112(f) during prosecution, it will recite claim elements using the “means for” [performing a function] construct.

The phrase “based on” is used to describe one or more factors that affect a determination. This term does not foreclose the possibility that additional factors may affect the determination. That is, a determination may be solely based on specified factors or based on the specified factors as well as other, unspecified factors. Consider the phrase “determine A based on B.” This phrase specifies that B is a factor that is used to determine A or that affects the determination of A. This phrase does not foreclose that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover an embodiment in which A is determined based solely on B. As used herein, the phrase “based on” is synonymous with the phrase “based at least in part on.”

The phrase “in response to” describes one or more factors that trigger an effect. This phrase does not foreclose the possibility that additional factors may affect or otherwise trigger the effect. That is, an effect may be solely in response to those factors, or may be in response to the specified factors as well as other, unspecified factors. Consider the phrase “perform A in response to B.” This phrase specifies that B is a factor that triggers the performance of A. This phrase does not foreclose that performing A may also be in response to some other factor, such as C. This phrase is also intended to cover an embodiment in which A is performed solely in response to B.