Patent ID: 12260895

DETAILED DESCRIPTION

As described in greater detail below, the technology disclosed herein relates to an apparatus, such as memory systems, systems with memory devices, related methods, etc., for protecting data against hardware-level attacks. The apparatus (e.g., a memory device and/or a system including the memory device) can include a security mechanism (e.g., a voltage adjustment circuit) configured to adjust one or more internal processing voltages when non-operating conditions occur, such as when low environmental temperatures or other hardware-level attacking conditions are detected. The security mechanism may adjust the processing voltages to protect the operating states and/or stored data, such as by intentionally corrupting the states/data.

For illustrative purposes, one example of lower-level nefarious interactions is illustrated usingFIG.1.FIG.1is a schematic block diagram for a nefarious system100(“system100”). The system100can include a first module102and a second module122configured to introduce a new/nefarious controller during operation of a memory component. Accordingly, the system100includes a first controller112for the first module102and a second controller132for the second module122. In some embodiments, the first module102can include a first circuit board and/or subsystem110(“first subsystem110”) that simulate a computing environment that includes other devices/circuits (e.g., power supply, accelerators, etc.). Similarly, the second module122can include a second circuit board and/or subsystem130(“second subsystem130”) that simulate the computing environment (i.e., via the same set of devices/circuits or a different set) while replacing the first controller112with the second controller132.

The unauthorized access to memory114(e.g., dual inline memory module (DIMM)) occurs by initializing the memory114with the first controller112(i.e., a normal controller circuit) and subsequently using the second controller132(i.e., a nefarious controller circuit) to access/control the memory114. As such, the memory114can be “hot swapped” by being connected to a different set of devices (e.g., from the first module102to the second module122) during operation of the memory114. The operating states of the memory114can be preserved during the swap, such as by maintaining power, maintaining extremely low temperatures (e.g., below 0° C., below −40° C., etc.), and/or avoiding reinitialization of the memory114. For example, a module freeze spray, a low temperature or a cryogenic environment (e.g., bath), and/or a switching circuit may be used to preserve the operating state of the memory114while swapping the DIMM across modules102and122. Based on the swap, the conventional memory114may operate without detecting the change in the interfacing devices, and the second controller132may freely gain access to and control the memory114.

To protect against such lower-level nefarious interactions, embodiments of the technology described herein may include a security mechanism configured to protect the operating states and/or stored data, such as by adjusting one or more processing voltages. For example, the security mechanism can adjust the processing voltages intentionally corrupting the corresponding operating states and/or data.

In some embodiments, the security mechanism can receive temperature readings from an existing on-die temperature sensor and/or logic. When the measured temperature reaches a threshold temperature outside of the operating range of the apparatus, the security mechanism can adjust an on-die voltage supply for a reference voltage (Vref) used to refresh data. For example, the security mechanism can drive the Vref to a low state, thereby causing all bits to be detected high. The change in data may occur based on the refresh rate (e.g., 64 ms cycles) and in less time (e.g., less than 100 ms) than required to enable/facilitate a nefarious system to access the same data. Accordingly, the security mechanism can leverage an existing process and existing circuits to protect the data against hardware-level attacks (e.g., cold boot attacks). Additionally or alternatively, the security mechanism can leverage other existing processes and/or circuits, such as by adjusting the word-line supply level, by forcing all cells to leak voltage, and/or by triggering a state machine or a separate process (e.g., built-in self test (BIST)) that alters the stored data.

FIG.2is a block diagram of an apparatus200(e.g., a semiconductor die assembly, including a three-dimensional integration (3DI) device or a die-stacked package) in accordance with an embodiment of the present technology. For example, the apparatus200can include a DRAM or a portion thereof that includes one or more dies/chips.

The apparatus200may include an array of memory cells, such as memory array250. The memory array250may include a plurality of banks (e.g., banks 0-15), and each bank may include a plurality of word lines (WL), a plurality of bit lines (BL), and a plurality of memory cells arranged at intersections of the word lines and the bit lines. Memory cells can include any one of a number of different memory media types, including capacitive, magnetoresistive, ferroelectric, phase change, or the like. The selection of a word line WL may be performed by a row decoder240, and the selection of a bit line BL may be performed by a column decoder245. Sense amplifiers (SAMP) may be provided for corresponding bit lines BL and connected to at least one respective local I/O line pair (LIOT/B), which may in turn be coupled to at least respective one main I/O line pair (MIOT/B), via transfer gates (TG), which can function as switches. The memory array250may also include plate lines and corresponding circuitry for managing their operation.

The apparatus200may employ a plurality of external terminals that include command and address terminals coupled to a command bus and an address bus to receive command signals (CMD) and address signals (ADDR), respectively. The apparatus200may further include a chip select terminal to receive a chip select signal (CS), clock terminals to receive clock signals CK and CKF, data clock terminals to receive data clock signals WCK and WCKF, data terminals DQ, RDQS, DBI, and DMI, power supply terminals VDD, VSS, and VDDQ.

The command terminals and address terminals may be supplied with an address signal and a bank address signal (not shown inFIG.2) from outside. The address signal and the bank address signal supplied to the address terminals can be transferred, via a command/address input circuit205, to an address decoder210. The address decoder210can receive the address signals and supply a decoded row address signal (XADD) to the row decoder240, and a decoded column address signal (YADD) to the column decoder245. The address decoder210can also receive the bank address signal and supply the bank address signal to both the row decoder240and the column decoder245.

The command and address terminals may be supplied with command signals (CMD), address signals (ADDR), and chip select signals (CS), from a memory controller and/or a nefarious chipset. The command signals may represent various memory commands from the memory controller (e.g., including access commands, which can include read commands and write commands). The chip select signal may be used to select the apparatus200to respond to commands and addresses provided to the command and address terminals. When an active chip select signal is provided to the apparatus200, the commands and addresses can be decoded and memory operations can be performed. The command signals may be provided as internal command signals ICMD to a command decoder215via the command/address input circuit205. The command decoder215may include circuits to decode the internal command signals ICMD to generate various internal signals and commands for performing memory operations, for example, a row command signal to select a word line and a column command signal to select a bit line. The command decoder215may further include one or more registers for tracking various counts or values (e.g., counts of refresh commands received by the apparatus200or self-refresh operations performed by the apparatus200).

Read data can be read from memory cells in the memory array250designated by row address (e.g., address provided with an active command) and column address (e.g., address provided with the read). The read command may be received by the command decoder215, which can provide internal commands to input/output circuit260so that read data can be output from the data terminals DQ, RDQS, DBI, and DMI via read/write amplifiers255and the input/output circuit260according to the RDQS clock signals. The read data may be provided at a time defined by read latency information RL that can be programmed in the apparatus200, for example, in a mode register (not shown inFIG.2). The read latency information RL can be defined in terms of clock cycles of the CK clock signal. For example, the read latency information RL can be a number of clock cycles of the CK signal after the read command is received by the apparatus200when the associated read data is provided.

Write data can be supplied to the data terminals DQ, DBI, and DMI according to the WCK and WCKF clock signals. The write command may be received by the command decoder215, which can provide internal commands to the input/output circuit260so that the write data can be received by data receivers in the input/output circuit260, and supplied via the input/output circuit260and the read/write amplifiers255to the memory array250. The write data may be written in the memory cell designated by the row address and the column address. The write data may be provided to the data terminals at a time that is defined by write latency WL information. The write latency WL information can be programmed in the apparatus200, for example, in the mode register. The write latency WL information can be defined in terms of clock cycles of the CK clock signal. For example, the write latency information WL can be a number of clock cycles of the CK signal after the write command is received by the apparatus200when the associated write data is received.

The power supply terminals may be supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS can be supplied to an internal voltage generator circuit270. The internal voltage generator circuit270can generate various internal potentials VPP, VOD, VARY, VPERI, and the like based on the power supply potentials VDD and VSS. The internal potential VPP can be used in the row decoder240, the internal potentials VOD and VARY can be used in the sense amplifiers included in the memory array250, and the internal potential VPERI can be used in many other circuit blocks.

The power supply terminal may also be supplied with power supply potential VDDQ. The power supply potential VDDQ can be supplied to the input/output circuit260together with the power supply potential VSS. The power supply potential VDDQ can be the same potential as the power supply potential VDD in an embodiment of the present technology. The power supply potential VDDQ can be a different potential from the power supply potential VDD in another embodiment of the present technology. However, the dedicated power supply potential VDDQ can be used for the input/output circuit260so that power supply noise generated by the input/output circuit260does not propagate to the other circuit blocks.

The clock terminals and data clock terminals may be supplied with external clock signals and complementary external clock signals. The external clock signals CK, CKF, WCK, WCKF can be supplied to a clock input circuit220. The CK and CKF signals can be complementary, and the WCK and WCKF signals can also be complementary. Complementary clock signals can have opposite clock levels and transition between the opposite clock levels at the same time. For example, when a clock signal is at a low clock level a complementary clock signal is at a high level, and when the clock signal is at a high clock level the complementary clock signal is at a low clock level. Moreover, when the clock signal transitions from the low clock level to the high clock level the complementary clock signal transitions from the high clock level to the low clock level, and when the clock signal transitions from the high clock level to the low clock level the complementary clock signal transitions from the low clock level to the high clock level.

Input buffers included in the clock input circuit220can receive the external clock signals. For example, when enabled by a clock/enable signal from the command decoder215, an input buffer can receive the clock/enable signals. The clock input circuit220can receive the external clock signals to generate internal clock signals ICLK. The internal clock signals ICLK can be supplied to an internal clock circuit230. The internal clock circuit230can provide various phase and frequency controlled internal clock signals based on the received internal clock signals ICLK and a clock enable (not shown inFIG.2) from the command/address input circuit205. For example, the internal clock circuit230can include a clock path (not shown inFIG.2) that receives the internal clock signal ICLK and provides various clock signals to the command decoder215. The internal clock circuit230can further provide input/output (IO) clock signals. The IO clock signals can be supplied to the input/output circuit260and can be used as timing signals for determining output timing of read data and/or input timing of write data. The IO clock signals can be provided at multiple clock frequencies so that data can be output from and input to the apparatus200at different data rates. A higher clock frequency may be desirable when high memory speed is desired. A lower clock frequency may be desirable when lower power consumption is desired.

The apparatus200can be connected to any one of a number of electronic devices capable of utilizing memory for the temporary or persistent storage of information, or a component thereof. For example, a host device of apparatus200may be a computing device such as a desktop or portable computer, a server, a hand-held device (e.g., a mobile phone, a tablet, a digital reader, a digital media player), or some component thereof (e.g., a central processing unit, a co-processor, a dedicated memory controller, etc.). The host device may be a networking device (e.g., a switch, a router, etc.) or a recorder of digital images, audio and/or video, a vehicle, an appliance, a toy, or any one of a number of other products. In one embodiment, the host device may be connected directly to apparatus200; although in other embodiments, the host device may be indirectly connected to memory device (e.g., over a networked connection or through intermediary devices).

The apparatus200can include a trigger sensor292configured to observe or measure targeted aspects of an operating environment (e.g., environmental parameters characteristic of a low-level or a hardware level attack). For example, the trigger sensor292can include a temperature sensor and/or logic configured to control various operational settings according to operating temperature, such as to account for temperature-based resistance changes, noise levels, signal degradations, etc. In some embodiments, the trigger sensor292can be configured to flag and identify when environmental or operating temperatures fall below a threshold temperature (e.g., below 0° C., below −40° C., etc.) that is outside of the operating temperature range of the memory device. The threshold temperature can be predetermined according to one or more aspects of the apparatus200, such as the memory storage technology, circuit integrity, targeted industrial application, etc.

The apparatus200can include a security mechanism, such as a voltage adjustment circuit294, configured to protect the operating state of the apparatus200and/or data stored/processed by the apparatus200. In some embodiments, the voltage adjustment circuit294can adjust one or more voltage levels, such as by interacting with the voltage generator270, the memory array250, and/or other circuits described above. For example, the voltage adjustment circuit294can adjust a reference level (e.g., Vref) used for the data refresh and/or sense-amplifier operations. The voltage adjustment circuit294can adjust Vref, such as from the middle of two sense levels, to a low sense level or a high sense level. As a result, the stored information can be detected as the same value or bit level (e.g., all high when Vref is low or all low when Vref is high) during a read and/or a refresh operation. In other words, when a triggering condition is detected, the voltage adjustment circuit294can effectively drive/change all or a portion of the stored bits to a low state or a high state.

By adjusting Vref, the voltage adjustment circuit294can use the existing refresh operation to corrupt the data. Accordingly, the voltage adjustment circuit294can cause the data corruption within a response duration (e.g., less than 100 ms from detection of the triggering condition) that corresponds to the refresh rate (e.g., 64 ms). The resulting response duration can be less than the amount of time necessary to implement the hardware-level attack (e.g., such as to physically move the apparatus200from the first subsystem110ofFIG.1to the second subsystem130ofFIG.1). Thus, the voltage adjustment circuit294can protect the stored data from being accessed by the nefarious system/attack.

In other embodiments, the voltage adjustment circuit294can adjust the word-line supply voltage to corrupt the read data in response to detecting the targeted condition. Other examples of the protection mechanism can include circuitry configured to force all cells to leak stored charges and/or to trigger state machines or processes (e.g., BIST) that alter the stored data.

FIG.3is an example timing diagram300for the apparatus200ofFIG.2in accordance with an embodiment of the present technology. The timing diagram300can represent one or more timings associated with the trigger sensor292ofFIG.2, the protection mechanism (e.g., the voltage adjustment circuit294ofFIG.2), and/or one or more circuits described above. The timing diagram300can represent the apparatus200(via, e.g., the voltage adjustment circuit294) protecting a protection target in response to a change in an operating condition, such as by adjusting one or more processing voltages and/or implementing a protection process.

For the example illustrated inFIG.3, the apparatus200can protect stored data302(e.g., data stored in the memory array250ofFIG.2) when a sensed temperature304meets or falls below a threshold level306. The voltage adjustment circuit294can adjust a reference voltage308(Vref) used for sensing/determining bit values to change or intentionally corrupt the stored data302from a stored state310to a protected state312. In some embodiments, an on-board temperature sensor (e.g., a portion of the trigger sensor292ofFIG.2) can provide the sensed temperature304and a logic (e.g., a different portion of the trigger sensor292) can compare the sensed temperature304to the threshold level306. When the sensed temperature meets or falls below the threshold level306, the trigger sensor292can generate a trigger output314. The voltage adjustment circuit294can receive and respond to the trigger output314by adjusting the reference voltage308, such as by driving it from an operating level316(e.g., about midway between a high level and a low level that causes accurate reading of the stored state310) to a protection level318(e.g., the low level or alternatively the high level). By adjusting the reference voltage308to the protection level318, the voltage adjustment circuit294can leverage a refresh process320to implement the protection process. As a result of adjusting the reference voltage308, the stored data302can be read back or detected as the protected state312(e.g., all high levels of stored charges due to low reference levels) during a subsequent refresh operation.

The voltage adjustment circuit294configured to update the reference voltage308and leverage the refresh process320to protect the data can use existing processes to guarantee data protection against hardware-level attacks. Since the memory device is configured to implement the refresh process320after a refresh delay322(e.g., 64 ms), the voltage adjustment circuit294can provide a response time324that is closely related to and bounded by the refresh delay. In other words, a maximum value of the response time324can correspond to the refresh delay322and any related processing durations. Since the combination of the refresh delay322and refresh processing durations (e.g., milliseconds) are many orders of magnitudes lower than the duration necessary to implement a hardware-level attack (e.g., seconds or minutes), the voltage adjustment circuit294can guarantee that the stored data302will be protected against such attacks.

FIG.4is a flow diagram illustrating an example method400of operating an apparatus (e.g., the apparatus200ofFIG.2) in accordance with an embodiment of the present technology. The method400may correspond to the timing diagram300ofFIG.3. The method400can be for protecting an operating state of the apparatus and/or data associated with or stored in the apparatus.

At block402, the apparatus can be initiated for operation. The apparatus can implement a boot process or a load process according to a predetermined set of instructions. Accordingly, the apparatus can prepare the functional circuitry (e.g., the memory array250ofFIG.2and/or other circuits described above) for normal or intended operation.

At block404, the apparatus can measure a temperature thereof during or as part of normal operation. The apparatus can use an on-board temperature sensor (e.g., a portion of a trigger sensor292ofFIG.2) to determine the sensed temperature304ofFIG.3representative of a measurement of thermal energy in the apparatus and/or a surrounding environment thereof.

At decision block406, the apparatus can compare the temperature to a threshold. The threshold can correspond to a predetermined temperature that is outside of a normal operating range of the apparatus. For example, the threshold can be at or below a floor/minimum temperature (e.g., 0° C., −40° C., etc.) of the operating range. When the temperature is at or above the threshold, the apparatus can continue the normal operation including measuring/monitoring the temperature. When the temperature falls below the threshold, the apparatus can generate a protection trigger based on the comparison, as illustrated at block408. For example, the apparatus can use a portion of the trigger sensor292(e.g., a logic, a comparator, or the like) to generate the trigger output314ofFIG.3when the temperature is below the threshold.

At block410, the apparatus can implement the protection mechanism based on the trigger output. The apparatus can use a protection circuit to protect an operating state of the apparatus and/or data of the apparatus against an unauthorized access.

In some embodiments, as illustrate at block412, the protection circuit can provide the protection by changing the data stored on the apparatus (e.g., by intentionally changing or corrupting the stored data or one or more portions thereof). The protection circuit can change the data or one or more portions thereof from the initially stored state310ofFIG.3to the protected state312(e.g., a set of ‘0’ bit values or a set of ‘1’ bit values). The data may be changed based on adjusting a processing voltage as illustrated at block422. For example, the protection circuit can include the voltage adjustment circuit294ofFIG.2that changes the reference voltage308ofFIG.3for the sense amplifier from the operating level316ofFIG.3to the protection level318ofFIG.3(e.g., a non-operational level outside of an operation range that is configured to accurately process the stored data). Also, the voltage adjustment circuit294can adjust other processing voltage, such as the word line supply voltage, to the non-operational level that would adjust or corrupt the stored data.

Additionally or alternatively, the apparatus can change data values as illustrated at block424. The apparatus may change the data values by implementing a process that corresponds to the adjusted processing voltage. For example, the memory device can implement a data refresh operation (e.g., a regularly scheduled refresh occurring after the trigger) using the adjusted voltage reference. Accordingly, the memory device can change the stored data (e.g., the representative charge levels at the memory cells) to a predetermined state representative of a common bit value during a subsequently implemented refresh operation.

In some embodiments, the apparatus may change the data value independent of or without changing the processing voltage. For example, the apparatus can change the data values by implementing a BIST or a separate self-writing circuit to alter or replace the stored data. Accordingly, the apparatus can protect against an unauthorized system (e.g., the second subsystem130ofFIG.1) attempting to access the stored data, such as during a hardware-based attack (e.g., cold boot attack).

In addition to or instead of changing the data, the apparatus can implement the protection mechanism by locking the apparatus as illustrated at block414. The apparatus can implement the lock, for example, based on implementing a self-initiated reset, disabling one or more circuits (e.g., the input/output circuit260ofFIG.2, the address command input circuit205ofFIG.2, or the like), and/or disabling one or more internal clocks. Accordingly, the apparatus can protect any configuration information or device operating status associated with the data storage against unauthorized access.

FIG.5is a flow diagram illustrating an example method500of manufacturing an apparatus (e.g., the apparatus200ofFIG.2) in accordance with an embodiment of the present technology. For example, the method500can correspond to manufacturing a memory device that includes a protection circuit configured to protect an operating state of the memory device and/or data stored in the memory device.

At block502, the method500can include providing a temperature sensor (e.g., a portion of the trigger sensor292ofFIG.2). The provided temperature sensor may include an onboard or on-die temperature sensor configured to measure a temperature of the apparatus and/or a surrounding environment thereof.

At block504, the method500can include providing a voltage adjustment circuit (the voltage adjustment circuit294ofFIG.2or a portion thereof). The voltage adjustment circuit can be configured to adjust one or more voltages, such as the reference voltage for the sense amplifier, a wordline supply voltage, or the like used to process the stored data. The voltage adjustment circuit can be configured to adjust the one or more voltages during a normal operation, such as to account for variations associated with process, voltage, and temperature (PVT), for accurately processing the stored data.

At block506, the method500can include configuring a protection circuit/logic (e.g., a portion of the trigger sensor292, a portion of the voltage adjustment circuit294, or the like) to protect the apparatus against an unauthorized access thereto. The protection circuit can be configured to respond to the trigger output by changing the data values and/or locking the apparatus as described above. For example, the voltage adjustment circuit294and/or a corresponding logic can be configured to drive the reference voltage or the wordline supply voltage to non-operating levels that would change or intentionally corrupt the stored data during a corresponding data operation (e.g., refresh operation). Also, the self-test circuit, a self-write circuit, and/or a corresponding logic can be configured to separately alter the stored charge levels and the corresponding stored data to a predetermined pattern different from the initially stored content.

In some embodiments, providing one or more circuits for the method500can include forming the one or more circuits, such as using semiconductor manufacturing processes. For example, one or more of the circuits/logic described above can be formed in semiconductor material/substrate by doping the semiconductor, masking/etching to form connectors and/or isolation, or the like. Also, the circuits may be formed based on mounting one or more circuit components on a circuit substrate (e.g., a printed circuit board). The provided circuits can be electrically coupled to each other, such as using wired connectors (e.g., traces, buses, wires, etc.) and/or wireless mechanisms (e.g., inductor-based coupling). The provided circuits can be further coupled to other functional circuits, such as the memory array250ofFIG.2, the refresh circuit (not shown), a self-test circuit (not shown), and/or other circuits described above.

FIG.6is a schematic view of a system that includes an apparatus in accordance with embodiments of the present technology. Any one of the foregoing apparatuses (e.g., memory devices) described above with reference toFIGS.2-5can be incorporated into any of a myriad of larger and/or more complex systems, a representative example of which is system680shown schematically inFIG.6. The system680can include a memory device600, a power source682, a driver684, a processor686, and/or other subsystems or components688. The memory device600can include features generally similar to those of the apparatus described above with reference toFIGS.2-5, and can therefore include various features for performing a direct read request from a host device. The resulting system680can perform any of a wide variety of functions, such as memory storage, data processing, and/or other suitable functions. Accordingly, representative systems680can include, without limitation, hand-held devices (e.g., mobile phones, tablets, digital readers, and digital audio players), computers, vehicles, appliances and other products. Components of the system680may be housed in a single unit or distributed over multiple, interconnected units (e.g., through a communications network). The components of the system680can also include remote devices and any of a wide variety of computer readable media.

From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. In addition, certain aspects of the new technology described in the context of particular embodiments may also be combined or eliminated in other embodiments. Moreover, although advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages and not all embodiments need necessarily exhibit such advantages to fall within the scope of the technology. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described herein.

In the illustrated embodiments above, the apparatuses have been described in the context of DRAM devices. Apparatuses configured in accordance with other embodiments of the present technology, however, can include other types of suitable storage media in addition to or in lieu of DRAM devices, such as, devices incorporating NAND-based or NOR-based non-volatile storage media (e.g., NAND flash), magnetic storage media, phase-change storage media, ferroelectric storage media, etc.

The term “processing” as used herein includes manipulating signals and data, such as writing or programming, reading, erasing, refreshing, adjusting or changing values, calculating results, executing instructions, assembling, transferring, and/or manipulating data structures. The term data structure includes information arranged as bits, words or code-words, blocks, files, input data, system-generated data, such as calculated or generated data, and program data. Further, the term “dynamic” as used herein describes processes, functions, actions or implementation occurring during operation, usage or deployment of a corresponding device, system or embodiment, and after or while running manufacturer's or third-party firmware. The dynamically occurring processes, functions, actions or implementations can occur after or subsequent to design, manufacture, and initial testing, setup or configuration.

The above embodiments are described in sufficient detail to enable those skilled in the art to make and use the embodiments. A person skilled in the relevant art, however, will understand that the technology may have additional embodiments and that the technology may be practiced without several of the details of the embodiments described above with reference toFIGS.2-6.