Patent ID: 12249986

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Like features have been designated by like references in the various figures. In particular, the structural and/or functional features that are common among the various embodiments may have the same references and may dispose identical structural, dimensional and material properties.

For the sake of clarity, only the steps and elements that are useful for an understanding of the embodiments described herein have been illustrated and described in detail.

Unless indicated otherwise, when reference is made to two elements connected together, this signifies a direct connection without any intermediate elements other than conductors, and when reference is made to two elements coupled together, this signifies that these two elements can be connected or they can be coupled via one or more other elements.

In the following disclosure, unless otherwise specified, when reference is made to absolute positional qualifiers, such as the terms “front”, “back”, “top”, “bottom”, “left”, “right”, etc., or to relative positional qualifiers, such as the terms “above”, “below”, “higher”, “lower”, etc., or to qualifiers of orientation, such as “horizontal”, “vertical”, etc., reference is made to the orientation shown in the figures.

Unless specified otherwise, the expressions “around”, “approximately”, “substantially” and “in the order of” signify within 10%, and preferably within 5%.

FIG.1schematically shows in the form of blocks an embodiment of a level converter circuit10.

Converter circuit10receives, as an input, an analog input signal IN and outputs an analog output signal OUT. Input and output signals IN and OUT are used to transfer binary data. Converter circuit10is capable of converting the voltage levels of input signal IN into different voltage levels, output signal OUT corresponding to the converted input signal IN. The succession of logic states of output signal OUT is thus the same as that of input signal IN. More particularly, input signal IN is an analog signal comprising two states, a low state representing a logic “0” having a voltage level smaller than a first voltage level VinL, and a high state representing a logic “1” having a voltage level greater than a second voltage level VinH. Second voltage level VinH is greater than first voltage level VinL. Output signal OUT is an analog signal comprising two states, a low state representing a logic “0” having a voltage level smaller than a first voltage level VoutL, and a high state representing a logic “1” having a voltage level greater than a second voltage level VoutH. Second voltage level VoutH is greater than first voltage level VoutL.

Optionally, converter circuit10may output a second output signal N-OUT. Output signal N-OUT is an analog signal comprising two logic states, a low state representing a logic “0” having a voltage level smaller than voltage level VoutL, and a high state representing a logic “1” having a voltage level greater than voltage level VoutH. Output signal N-OUT represents a succession of logic states corresponding to the inverse of the logic states represented by output signal OUT.

Converter circuit10comprises a conversion circuit11(LS) receiving input signal IN and outputting output signal OUT and, optionally, output signal N-OUT. The conversion circuit receives, as a current, a current Itemp and receives, as voltages, voltage levels VinL, VoutH, and VoutL. Converter circuit10does not receive voltage level VinH. A detailed example of conversion circuit11is described in relation withFIG.2.

Converter circuit10further comprises a power supply circuit12(IPTAT) capable of supplying current Itemp. Current Itemp is a current proportional to the room temperature. An example of power supply circuit12is detailed in relation withFIG.2.

According to an embodiment, conversion circuit11and power supply circuit12are both formed on a same substrate, for example, a same silicon substrate.

Converter circuit10operates as follows. When input voltage IN is greater than a threshold VIH, output voltage OUT is set to voltage level VoutH and output voltage N-OUT is set to voltage level VoutL. When input voltage IN is smaller than or equal to a threshold VIL, output voltage OUT is set to voltage level VoutL, and output voltage N-OUT is set to voltage level VoutH. Voltage levels VinL and VoutL are smaller than threshold VIL. Voltage levels VinH and VoutH are greater than threshold VIH.

The inventors have observed that by supplying conversion circuit11with a current proportional to temperature, the number of conversion errors, that is, the number of erroneously converted bits, decreases. A conversion error may for example correspond to a non-compliance with a threshold VIH or VIL. Indeed, controlling an input transistor of conversion circuit11with current Itemp proportional to temperature enables to compensate for the drift of the switching threshold of the transistor. This phenomenon will be detailed in relation withFIGS.3and4.

In certain cases, the thresholds are defined by a standard, and an advantage of converter circuit10is that, due to the supply of its conversion circuit with the current proportional to temperature, it may comply with the standard.

Another advantage of converter circuit10is that it enables to convert input signal IN without knowing the “high” voltage level VinH. Thus, converter circuit10may convert an input signal IN having its “high” voltage level VinH varying, for example, randomly, between a plurality of voltage levels. According to an embodiment, the voltage level VinL of input signal IN is in the order of 0 V, the voltage level VinH of input signal IN varies randomly between a voltage in the order of 1.8 V, and a voltage in the order of 3.3 V.

FIG.2illustrates an electric diagram of an embodiment of the level converter circuit10described in relation withFIG.1.

The conversion circuit11(delimited in dotted lines) of circuit10comprises a first inverter stage formed of MOS transistors111N and111P. Transistor111N is of type N, and transistor111P is of type P. Transistors111N and111P are coupled, preferably connected, in series by their conduction terminals. The source of transistor111N is coupled, preferably connected, to a node receiving voltage level VinL. The drain of transistor111N is coupled, preferably connected, to a node A. The gate of transistor111N is coupled, preferably connected, to a node receiving input signal IN. The source of transistor111P is coupled, preferably connected, to a node receiving voltage level VoutH. The drain of transistor111P is coupled, preferably connected, to node A. The gate of transistor111P is coupled, preferably connected, to a node receiving current Itemp. Further, transistor111P is mirror-connected with transistors of power supply circuit12, and is not used as a switch.

Conversion circuit11further comprises a second inverter stage formed of MOS transistors112N and112P. Transistor112N is of type N and transistor112P is of type P. transistors112N and112P are coupled, preferably connected, in series by their conduction terminals. The source of transistor112N is coupled, preferably connected, to the node receiving voltage level VinL. The drain of transistor112N is coupled, preferably connected, to a node B. The gate of transistor112N is coupled, preferably connected, to node A. The source of transistor112P is coupled, preferably connected, to the node receiving voltage level VoutH. The drain of transistor112P is coupled, preferably connected, to node B. The gate of transistor112P is coupled, preferably connected, to node A.

Conversion circuit11further comprises a third inverter stage formed of MOS transistors113N and113P. Transistor113N is of type N and transistor113P is of type P. Transistors113N and113P are coupled, preferably connected, in series by their conduction terminals. The source of transistor113N is coupled, preferably connected, to a node receiving voltage level VoutL. The drain of transistor113N is coupled, preferably connected, to a node C supplying output signal N-OUT. The gate of transistor113N is coupled, preferably connected, to a node supplying output signal OUT. The source of transistor113P is coupled, preferably connected, to the node receiving voltage level VoutH. The drain of transistor113P is coupled, preferably connected, to node C. The gate of transistor113is coupled, preferably connected, to node B.

Conversion circuit11further comprises a fourth inverter stage formed of MOS transistors114N and114P. Transistor114N is of type N, and transistor114P is of type P. Transistors114N and114P are coupled, preferably connected, in series by their conduction terminals. The source of transistor114N is coupled, preferably connected, to the node receiving voltage level VoutL. The drain of transistor114N is coupled, preferably connected, to the node supplying output signal OUT. The gate of transistor114N is coupled, preferably connected, to node C. The source of transistor114P is coupled, preferably connected, to the node receiving voltage level VoutH. The drain of transistor114P is coupled, preferably connected, to the node supplying output signal OUT. The gate of transistor114P is coupled, preferably connected, to node A.

N-type MOS transistors111N,112N,113N, and114N are all sized to be conductive when the voltage at their gate is greater than threshold voltage VIH. P-type MOS transistors111P,112P,113P, and114P are all sized to be conductive when the voltage at their gate is greater than threshold voltage VIL.

The power supply circuit12(delimited in dotted lines) of circuit10comprises a first current mirror formed of two P-type MOS transistors121P and122P. The source of transistor121P is coupled, preferably connected, to the node receiving voltage level VoutH. The drain of transistor121P is coupled, preferably connected, to a node D. The gate of transistor121P is coupled, preferably connected, to a node E. The source of transistor122P is coupled, preferably connected, to the node receiving voltage level VoutH. The drain of transistor122P is coupled, preferably connected, to node E. The gate of transistor122P is coupled, preferably connected, to node E.

Power supply circuit12further comprises a second current mirror formed of two N-type MOS transistors123N and124N. The source of transistor123N is coupled, preferably connected, to the node receiving voltage level VinL. The drain of transistor123N is coupled, preferably connected, to node D. The gate of transistor123N is coupled, preferably connected, to node D. The source of transistor124N is coupled, preferably connected, to a first terminal of a resistor R. The second terminal of resistor R is coupled, preferably connected, to the node receiving voltage level VinL. The drain of transistor124N is coupled, preferably connected, to node E. The gate of transistor124N is coupled, preferably connected, to node D.

The transistors121P,122P,123N, and124N, of circuit12, all operate in a low inversion mode. The current Itemp supplied by circuit10is then proportional to the ratio of the difference between the potentials present on the gate and the source of transistors121P and122P to the resistance of resistor R. The resistance of resistor R being inversely proportional to temperature, current Itemp is proportional to temperature.

The general operation of the embodiment of circuit10, detailed in relation withFIG.2, is described in relation withFIGS.3and4.

FIG.3is a first equivalent electric diagram of the level converter circuit10described in relation withFIG.2, in the case where input signal IN represents a logic “0”.

InFIG.2, a so-called “conductive” transistor is represented by the electronic symbol of an on switch, and a so-called “non-conductive” transistor is represented by the electronic symbol of an off switch.

When input signal IN represents a logic “0”, its voltage is in the order of VinL, and is smaller than threshold VIL. Thus, the transistor111N of conversion circuit11is non-conductive. The current control of transistor111P is performed by current Itemp and the potential of node A is set to VoutH by transistor111P.

Transistors112N and112P are controlled by the potential of node A. Transistor112N is then conductive and transistor112P is then non-conductive. Node B is coupled to the node receiving voltage level VinL.

Transistor113P is controlled by the potential of node B and is then conductive. Node C is coupled to the node receiving voltage level VoutH. Output signal N-OUT then represents a logic “1” since its voltage is equal to voltage level VoutH.

Transistor114P is controlled by the potential of node A and is then non-conductive. Transistor114N is controlled by the potential of node C and is then conductive. The node supplying output signal OUT represents a logic “0” since its voltage is equal to voltage level VoutL.

Transistor113N is controlled by output signal OUT and is then non-conductive. Node C is thus only coupled to the node receiving voltage level VoutH.

FIG.4is a first equivalent electric diagram of the level converter circuit10described in relation withFIG.2, in the case where input signal IN represents a logic “1”.

InFIG.4, a so-called “conductive” transistor is represented by the electronic symbol of an on switch and a so-called “non-conductive” transistor is represented by the electronic symbol of an off switch.

When input signal IN represents a logic “1”, its voltage is in the order of VinH, and is greater than threshold VIH. Thus, the transistor111N of conversion circuit11is conductive. The current control of transistor111P is performed by current Itemp and the potential of node A is set to VinL by transistor111N.

Transistors112N and112P are controlled by the potential of node A. Transistor112N is then non-conductive and transistor112P is then conductive. Node B is coupled to the node receiving voltage level VoutH.

Transistor113P is controlled by the potential of node B and is then non-conductive.

Transistor114P is controlled by the potential of node A and is then conductive. The node supplying output signal OUT is coupled to the node receiving voltage VoutH. Output signal OUT represents a logic “1” since its voltage is equal to voltage level VoutH.

Transistor113N is controlled by output signal OUT and is then conductive. Node C is thus coupled to the node receiving voltage level VoutL. Output signal N-OUT then represents a logic “0” since its voltage is equal to voltage level VoutH.

Transistor114N is controlled by the potential of node C and is thus non-conductive.

Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants may be combined, and other variants will occur to those skilled in the art. In particular, other embodiments of conversion circuits and of current power supply circuits supplying a current proportional to temperature may be envisaged.

Finally, the practical implementation of the described embodiments and variations is within the abilities of those skilled in the art based on the functional indications given hereabove.