Patent ID: 12261074

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

A package and the method of forming the same are provided in accordance with various exemplary embodiments. The intermediate stages of forming the package are illustrated. The variations of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

FIGS.1through24illustrate the cross-sectional views of intermediate stages in the formation of an Integrated Fan-Out (InFO) package in accordance with some embodiments. The steps shown inFIG.1through24are also illustrated schematically in the process flow300as shown inFIG.27.

FIG.1illustrates a cross-sectional view of wafer10in accordance with some embodiments. Wafer10includes a plurality of semiconductor chips12. Wafer10further includes semiconductor substrate14, which extends into semiconductor chips12. Semiconductor substrate14may be a bulk silicon substrate or a silicon-on-insulator substrate. Semiconductor substrate14may also include other semiconductor materials including group III, group IV, and group V elements. Integrated circuit16is formed at surface14A of semiconductor substrate14. Integrated circuit16may include Complementary Metal-Oxide-Semiconductor (CMOS) transistors therein.

Semiconductor chips12may further include Inter-Layer Dielectric (ILD)17over semiconductor substrate14, and interconnect structure22over ILD17. Interconnect structure22includes dielectric layers24, and metal lines20and vias18formed in dielectric layers24. In accordance with some embodiments of the present disclosure, dielectric layers24are formed of low-k dielectric materials. The dielectric constants (k values) of the low-k dielectric materials may be less than about 2.8, or less than about 2.5, for example. Metal lines20and vias18may be formed of copper, a copper alloy, or other metal-containing conductive materials. Metal lines20and vias18may be formed using single damascene and/or dual damascene processes.

Metal pads26are formed over interconnect structure22, and may be electrically coupled to circuit16through metal lines20and vias18. Metal pads26may be aluminum pads or aluminum-copper pads, or may include other metals. In accordance with some embodiments of the present disclosure, the metal features that are underlying and contacting metal pad26are metal lines. In accordance with alternative embodiments, the metal features that are underlying and contacting metal pads26are metal vias.

Passivation layer28is formed to cover the edge portions of metal pads26. The central portion of each of metal pads26is exposed through an opening in passivation layer28. Passivation layer28may be formed of a non-porous material. In accordance with some embodiments of the present disclosure, passivation layer28is a composite layer including a silicon oxide layer (not shown), and a silicon nitride layer (not shown) over the silicon oxide layer. In accordance with alternative embodiments, passivation layer28is formed of Un-doped Silicate Glass (USG), silicon oxynitride, and/or the like. Although one passivation layer28is shown, there may be more than one passivation layer.

Polymer layer30is coated over and covering passivation layer28. The respective step is illustrated as step302in the process flow shown inFIG.27. Polymer layer30is formed of a polymer, which may be a photo-sensitive polymer such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), or the like. A pre-baking is performed, followed by light exposure as shown inFIG.1. Lithography mask32, which includes opaque portions and transparent portions with the desirable patterns, is used to light-expose polymer layer30, wherein light34penetrates through the transparent portions of lithography mask32, and is blocked by the opaque portions of lithography mask32.

Next, the light-exposed polymer layer30is developed, with some portions removed to form openings31, and the center portions of the underlying metal pads26are exposed to openings31. The respective step is illustrated as step304in the process flow shown inFIG.27. The resulting wafer10is shown inFIG.2. In accordance with some embodiments of the present disclosure, the tilt angle γ of the sidewalls of polymer layer30is substantially vertical, for example, in the range between about 85 degrees and about 95 degrees.

After the development of polymer layer30, wafer10is further baked in order to solidify polymer layer30and to drive solvents out. The respective step is illustrated as step306in the process flow shown inFIG.27. The resulting wafer10is shown inFIG.3. The relatively high temperature used for baking wafer10may be in the range between about 370° C. and about 410° C. in accordance with some embodiments. The baking may last for a period of time between about 40 minutes and about 120 minutes in accordance with some embodiments. The baking results in the full solidification of polymer layer30.

FIG.25illustrates a magnified view of a portion of wafer10. As shown inFIG.25, after the high-temperature baking, the sidewall profile of polymer layer30is smoothened and rounded, wherein sidewalls30′ of polymer layer30have a smoothly and continuous rounded portion. Alternatively stated, from the bottom to the top of sidewall30′, the tilt angles of sidewall30′ may be continually and smoothly increased. Dashed lines37schematically represent the position and the profile of the sidewalls of polymer layer30before the high-temperature baking, and the rounded sidewalls30′ illustrate the shape of polymer layer30after the high-temperature baking. It is observed that the high-temperature baking causes polymer layer30to reflow toward the center line of metal pad26. The reflow is a partial reflow, and polymer layer30is softened with a high viscosity. The reflow of polymer layer30causes the tilt angle of sidewalls30′ to be reduced. For example, at the locations where sidewall30′ contacts metal pad26(or the immediate neighboring regions), the tilt angle γ′ of sidewall30′ is in the range between about 15 degrees and about 45 degrees, and may be in the range between about 20 degrees and about 30 degrees. The reduced angle γ′ may contribute to the reduction of stress between polymer layer30and metal pad26during the subsequent planarization, and the likelihood of the peeling of polymer layer30from metal pad26is reduced.

The baking temperature is selected to be high enough to cause polymer layer30to be slightly reflowed to generate the profile as shown inFIG.25. The reflow, however, results in the width of opening31to be reduced from W1to W2. In accordance with some embodiments, the width difference (W1−W2) is in the range between about 6 μm and about 10 μm. Ratio W2/W1may be in the range between about 0.8 and about 0.9. To maintain adequate contact area between metal pad26and the overlying metal pillar46(FIG.26) that will be formed in subsequent steps, the reflow is controlled by selecting appropriate baking temperature. It is appreciated that the desirable baking temperature is partially determined by the material of polymer30. Furthermore, the composition (such as the amount of solvent that will be evaporated during the baking) of polymer30also affects the desirable baking temperature, and hence experiments may be performed to result in the desirable reflow.

Next, referring toFIG.4, Under-Bump Metallurgy (UBM) layer36is deposited on polymer layer30, for example, through physical Vapor Deposition (PVD). In accordance with some embodiments of the present disclosure, UBM layer36is formed of a copper layer or a copper alloy layer. In accordance with alternative embodiments, UBM layer36includes a titanium layer and a seed layer that is formed of copper or a copper alloy. UBM layer36is also in contact with metal pads26. Photo resist38is then applied and patterned to form openings, through which UBM layer36is exposed.

Referring toFIG.5, metal regions42are selectively deposited into openings40, for example, through plating. The respective step is illustrated as step308in the process flow shown inFIG.27. In accordance with some exemplary embodiments, metal regions42are formed of a non-solder material that does not melt in reflow processes for melting solder. For example, metal regions42may be formed of copper or a copper alloy. Solder caps44may be formed on the top surfaces of metal regions42, wherein solder caps44may be formed of a Sn—Ag alloy, a Sn—Cu alloy, a Sn—Ag—Cu alloy, or the like, and may be lead-free solder caps or lead-containing solder caps. Solder caps44may also be formed through plating.

After the formation of metal regions42and solder caps44, photo resist38is removed, as shown inFIG.6. Next, the portions of the UBM layer36that are previously covered by photo resist38are removed, leaving metal regions42and solder caps44un-removed, as shown inFIG.7. In subsequent discussion, the remaining portions of UBM layer36and metal regions42are in combination referred to as metal pillars46.

In accordance with some embodiments, a reflow is performed so that solder caps44have rounded top surfaces. The solder in solder caps44include some portions remaining overlapping metal regions42, and may or may not include some other portions flowing down to contact the sidewalls of metal pillars46. The reflowed solder caps44may not cover the bottom portions of the sidewalls of metal pillars46. In accordance with alternative embodiments, since solder caps44will be removed in a subsequent step, no reflow of solder caps44is performed.

Next, as shown inFIG.8, a probing step is performed on solder caps44to test the electrical properties of semiconductor chips12. The probing is performed by putting probe pins48in contact with solder caps44. Probe pins48are parts of probe card50, which is electrically connected to a test equipment (not shown). Through the probing, defective semiconductor chips12are found, and good semiconductor chips12are determined. Advantageously, solder caps44are softer than the underlying metal pillars46. Accordingly, the contact between probe pins48and solder caps44is better than the contact between probe pins48and metal pillars46. Hence, the probing is more reliable than if solder caps44are not formed.

After the probing, polymer layer52is formed to cover the top surface of wafer10, as shown inFIG.9. The respective step is illustrated as step310in the process flow shown inFIG.27. Hence, metal pillars46and solder caps44are embedded in polymer layer52, wherein the top surface of polymer layer52is higher than the top ends of solder caps44. Polymer layer52may be formed of a material selected from the same candidate materials (such as PBO) of polymer layer30. A die-saw is then performed on wafer10, and semiconductor chips12are separated from each other. The respective step is illustrated as step312in the process flow shown inFIG.27. The separated semiconductor chips12are referred to as device dies12hereinafter.

FIGS.10through23illustrate the packaging of device dies12to form InFO packages, so that the resulting electrical connectors (such as solder regions) of the InFO packages may be distributed to regions larger than device dies12.FIG.10illustrates carrier54and release layer56formed on carrier54. Carrier54may be a glass carrier, and may have a round top-view shape and a size of a common silicon wafer. Release layer56may be formed of a Light-To-Heat-Conversion (LTHC) coating material. The top surface of release layer56is planar. Dielectric layer58is formed on release layer56. In accordance with some embodiments, dielectric layer58is formed of a polymer, which may also be a photo-sensitive material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like, which may be patterned through light-exposure and development.

FIG.11through13illustrate the formation of metal posts60. The respective step is illustrated as step313in the process flow shown inFIG.27. Throughout the description, metal posts60are alternatively referred to as through-vias60since metal posts60penetrate through the subsequently dispensed encapsulating material.

Referring toFIG.11, metal seed layer62is formed, for example, through Physical Vapor Deposition (PVD). Metal seed layer62may include copper, or may include a titanium layer and a copper layer over the titanium layer in accordance with some embodiments. Photo resist64is formed over metal seed layer62.

A light-exposure is then performed on photo resist64using a photo lithography mask (not shown). After a subsequent development, openings66are formed in photo resist64, as shown inFIG.11. Metal seed layer62is exposed to openings66. Openings66may have a sand-timer profile, with the bottom width W1and top width W2being greater than middle width W3. Furthermore, the smallest widths of openings66may be close to the middle heights of openings66.

The material of photo resist64is selected to make the resulting openings66to have the sand-timer profile. In accordance with some exemplary embodiments, the photo resist includes TOK P50 series photo resist (manufactured by Tokyo Ohka Kogyo America Incorporated). The TOK P50 may include polyacrylate, cross-linker, and a photo-sensitive initiator in accordance with some embodiments. With the proper photo resist material being used, and process conditions for exposing and development being tuned, the sand-timer profile may be generated.

Next, as shown inFIG.12, through-vias60are formed by plating. The plating rate is controlled to ensure that the shape of the plated through-vias60follow the shape of openings66. In subsequent steps, photo resist64is removed, and hence the underlying portions of metal seed layer62are exposed. The exposed portions of metal seed layer62are then removed in an etching step. The resulting through-vias60are illustrated inFIG.13. Throughout the description, the remaining portions of metal seed layer62are considered as parts of through-vias60, and are not illustrated separately.

Through-vias60have middle portions narrower than the respective top portions and the respective bottom portions. It is noted thatFIG.13illustrates the shapes of through-vias60in one vertical plane. If viewed from any other vertical plane, through-vias60may also have the sand-timer profile. The top-view shapes of through-vias60may be circles, rectangles, squares, hexagons, or the like.

FIG.14illustrates the perspective view of the placement of device dies12onto the structure shown inFIG.13, wherein device dies12are arranged as rows and columns. The good device dies12that are found during the probing are placed, and defective device dies12are discarded. Through-vias60are not shown inFIG.14, although they also exist.

FIG.15illustrates the cross-sectional view of a portion of the structure shown inFIG.14. InFIG.15, only a single device die12and its surrounding through-vias60are illustrated. It is noted, however, the process steps shown inFIGS.15through23are performed at wafer level, and are performed on all of device dies12on carrier54. Device die12is placed on carrier54, and is adhered to dielectric layer58through Die-Attach Film (DAF)68, which is an adhesive film. The respective step is illustrated as step314in the process flow shown inFIG.27.

Next, referring toFIG.16, encapsulating material70is encapsulated on device die12and through-vias60. The respective step is illustrated as step316in the process flow shown inFIG.27. Encapsulating material70fills the gaps between neighboring through-vias60and the gaps between through-vias60and device die12. Encapsulating material70may include a molding compound, a molding underfill, an epoxy, or a resin. The molding compound may include a polymer (such as a resin) and fillers in the polymer, wherein the filler may include the spherical particles of silica (amorphous SiO2), aluminum oxide, etc. The top surface of encapsulating material70is higher than the top ends of metal pillar46and through-vias60.

Next, as shown inFIG.17, a planarization such as a Chemical Mechanical Polish (CMP) step or a grinding step is performed to thin encapsulating material70until through-vias60and metal pillars46are exposed. The respective step is illustrated as step318in the process flow shown inFIG.27. Due to the grinding, the top ends of through-vias60are level (coplanar) with the top surfaces of metal pillars46, and are coplanar with the top surface of encapsulating material70. In the illustrated exemplary embodiments, the planarization is performed until metal pillars46are exposed. Accordingly, the portions of solder caps44overlapping metal pillars46are removed. The portions of solder caps44on the sidewalls of metal pillars46(if resulted by reflow) may remain after the planarization.

FIG.26illustrates a cross-sectional view of a part of wafer10including metal pillar46. As shown inFIG.26, polymer layer30is joined to metal pad26with small tilt angle γ′. This may help release the stress applied on polymer layer30and metal pad26during the planarization due to the elimination of sharp bottom angles of metal pillar46. The small tilt angle γ′ is thus beneficial for reducing the delamination between polymer layer30and metal pad26, partly due to the increased contact/overlap of polymer layer30over metal pad26upon PI reflow toward the center of pad26, thus increasing the structural integrity at the joining interface and reducing the likelihood of delamination.

Metal pillar46includes lower portion46A lower than the top surface of polymer layer30, and upper portion46B higher than the top surface of polymer layer30. The thicknesses of lower portion46A and upper portion46B are T1and T2, respectively. In accordance with some embodiments, thickness ratio T1/T2is in the range between about 1.1 and 1.4. Tilt angle β of the sidewall of portion46B may be in the range between about 60 degrees and about 105 degrees, or in the range between about 70 degrees and about 90 degrees.

Further referring toFIG.26, the curved portion of sidewalls30′ may have radius R1, wherein ratio R1/T1may be greater than about 0.2, greater than about 0.3, or in the range between about 0.3 and 0.5 in accordance with some embodiments, the large radius R1is more effective in releasing stress in the subsequent planarization, as will be discussed in subsequent paragraphs. Radius R1, however, cannot be too big since the increased value R1may result in the contact area between metal pillar46and metal pad26to be too small.

Referring back toFIG.17, after the planarization, through-vias60may remain to have a sand-timer profile. Several profiles of through-vias60may be resulted by the preceding process steps. In accordance with some embodiments of the present disclosure, a through-via60may include top portion60A, middle portion60B, and bottom portion60C, wherein top portions60A and bottom portion60C may have vertical sidewalls and uniform widths (illustrated by dashed lines60′), while the middle portion60B has slanted sidewalls and continuously changed widths as illustrated. In accordance with alternatively embodiments, portions60A,60B, and60C all have gradually and continuously changed widths, with a middle part of through-via60being narrowest, and the respective upper portions become increasingly wider, and lower portions become increasingly wider also, as shown by solid lines inFIG.17.

FIGS.18through24illustrate the formation of front-side RDLs and solder regions. The respective step is illustrated as step320in the process flow shown inFIG.27. Referring toFIG.18, polymer layer72is formed, for example, using a photo-sensitive material. In accordance with some embodiments, polymer layer72is formed of polyimide. In accordance with alternative embodiments, polymer layer72is formed of other dielectric materials such as PBO. Openings74are formed in polymer layer72to expose through-vias60and metal pillars46.

The formation of polymer layer72and openings74includes dispensing polymer layer72, pre-baking polymer layer72, performing a light-exposure on polymer layer72, and developing the exposed polymer layer72. After the development, polymer layer72is baked. In accordance with some embodiments, openings74are narrower than openings31(FIG.2). Accordingly, it is desirable that the reflow effect of polymer layer72caused by the baking is less significant than polymer layer30, so that the width of openings74is not reduced as much as the reduction of openings31. Otherwise, the contact area between the Redistribution Lines (RDLs) that will fill openings74will be reduced too much, and the contact resistance will be too high. Furthermore, since no CMP will be performed in the formation of the RDLs, it is less demanding in the requirement of stress reduction, and tilt angle α1may be greater than tilt angle γ′ (FIG.25).

In accordance with some embodiments, to limit the reflow of polymer layer72, the baking temperature (performed after the development) is low, and is lower than the baking temperature of polymer layer30. In accordance with some embodiments of the present disclosure, the baking temperature of polymer layer72is in the range between about 225° C. and about 275° C. The baking temperature of polymer layer72may also be lower than the baking temperature of polymer layer30by a difference higher than about 100° C., and the difference may also be in the range between about 120° C. and 160° C. The baking period may be in the range between about 40 minutes and about 80 minutes.

In accordance with some embodiments, polymer layer30and polymer layer72are formed of a same material, for example, polyimide, and the baking temperature of polymer layer30is higher than the baking temperature of polymer layer72to induce more reflow in polymer layer30than polymer layer72. In accordance with alternative embodiments, polymer layer30and polymer layer72are formed of different materials, for example, with one formed of polyimide and the other formed of PBO, and the baking temperature of polymer layer30is also higher than the baking temperature of polymer layer72to induce more reflow in polymer layer30than polymer layer72. In accordance with yet alternative embodiments, polymer layer30and polymer layer72are formed of different materials. For example, polymer layer30may be formed of a material having a lower reflow temperature than polymer layer72, and hence both layers30and72may be performed at a same temperature (or similar temperature with a difference smaller than about 20° C.), while polymer layer30still reflows more than polymer layer72.

Since the lower baking temperature of polymer layer72results in smaller reflow effect than for polymer layer30, after the baking of polymer layer72, the originally vertical sidewalls of polymer layer72is less tilted and less rounded than the sidewalls of polymer layer30. In accordance with some embodiments of the present disclosure, tilt angle α1is greater than angle γ′ (FIG.26). The difference (β−γ′) may be greater than about 30 degrees, and may be in the range between about 30 degrees and about 60 degrees. Tilt angle α1may be in the range between about 70 degrees and 90 degrees. The lower baking temperature is also beneficial for carrier54, which cannot sustain very high temperature.

Next, referring toFIG.19, Redistribution Lines (RDLs)80are formed to connect to metal pillars46and through-vias60. RDLs80may also interconnect metal pillars46and through-vias60. RDLs80include metal traces (metal lines) over polymer layer72as well as vias extending into openings74(FIG.18) to electrically connect to through-vias60and metal pillars46. In accordance with some embodiments, RDLs80are formed in a plating process, wherein each of RDLs80includes a seed layer (not shown) and a plated metallic material over the seed layer. The seed layer and the plated material may be formed of the same material or different materials. RDLs80may include a metal or a metal alloy including aluminum, copper, tungsten, and/or alloys thereof. RDLs80are formed of non-solder materials. The via portions of RDLs80may be in physical contact with the top surfaces of metal pillars46and through-vias60. In accordance with some embodiments, thickness ratio T1/T3(with T1shown inFIG.26) is in the range between about 1.3 and 1.6, wherein thickness T3is the thickness of RDL80.

Referring toFIG.20, dielectric layer82is formed over RDLs80and polymer layer72. Dielectric layer82may be formed using a polymer, which may be selected from the same candidate materials as those of polymer layer72. For example, dielectric layer82may comprise polyimide, PBO, BCB, or the like. Openings84are also formed in dielectric layer82to expose RDLs80. The formation of openings84may be performed through a photo lithography process. Polymer layer82may be baked using processes similar to the baking of polymer layer72, and hence tilt angle α2of the sidewalls of polymer layer82may be in the same range as tilt angle α1of polymer layer72.

FIG.21illustrates the formation of RDLs86, which are electrically connected to RDLs80. The formation of RDLs86may adopt similar methods and materials to those for forming RDLs80. RDLs86and80are also referred to as front-side RDLs since they are located on the front side of device die12.

As shown inFIG.22, an additional dielectric layer88, which may be a polymer layer, is formed to cover RDLs86and dielectric layer82. Dielectric layer88may be selected from the same candidate polymers used for forming dielectric layers72and82. Opening(s)90are then formed in dielectric layer88to expose the metal pad portions of RDLs86. In accordance with some embodiments, before forming dielectric layer88, one or a plurality of dielectric layers and RDL layers may be formed over and electrically coupling to RDLs86, and the materials and methods may be similar to that of the underlying dielectric layers and RDLs.

FIG.23illustrates the formation of Under-Bump Metallurgies (UBMs)92and electrical connectors94in accordance with some exemplary embodiments. The formation of UBMs92may include deposition and patterning. The formation of electrical connectors94may include placing solder balls on the exposed portions of UBMs92and then reflowing the solder balls. In alternative embodiments, the formation of electrical connectors94includes performing a plating step to form solder regions over RDLs86and then reflowing the solder regions. Electrical connectors94may also include metal pillars or metal pillars and solder caps, which may also be formed through plating. Throughout the description, the combined structure including device die12, through-vias60, encapsulating material70, and the corresponding RDLs and dielectric layers will be referred to as package100, which may be a composite wafer with a round top-view shape.

Next, package100is de-bonded from carrier54. The respective step is illustrated as step322in the process flow shown inFIG.27. Release layer56is also cleaned from package100. The de-bonding may be performed by projecting a light such as UV light or laser on release layer56to decompose release layer56.

In the de-bonding, a tape (not shown) may be adhered onto dielectric layer88and electrical connectors94. In subsequent steps, carrier54and release layer56are removed from package100. A die-saw step is performed to saw package100into a plurality of packages, each including device die12and through-vias60. One of the resulting packages is shown as package102inFIG.24.

FIG.24illustrates the bonding of package102with another package200. The respective step is illustrated as step324in the process flow shown inFIG.27. In accordance with some embodiments of the present disclosure, the bonding is performed through solder regions98. In accordance with some embodiments, package200includes device dies202, which may be memory dies such as Static Random Access Memory (SRAM) dies, Dynamic Random Access Memory (DRAM) dies, or the like. The memory dies may also be bonded to package substrate204in some exemplary embodiments.

The embodiments of the present disclosure have some advantageous features. By making the bottom portions of sidewalls of metal pillars to have smaller tilt angles, the stress incurred in subsequent planarization is reduced, and delamination is reduced or eliminated.

In accordance with some embodiments of the present disclosure, a method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, forming a dielectric layer encircling and covering the metal pillar, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.

In accordance with some embodiments of the present disclosure, a method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening, with the metal pad exposed through the first opening. The method further includes baking the wafer at a first temperature, forming a metal pillar in the first opening, forming a dielectric layer encircling and covering the metal pillar, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening, with the metal pillar exposed through the second opening. The second polymer layer is baked at a second temperature lower than the first temperature. A redistribution line is formed to have a portion filling the second opening.

In accordance with some embodiments of the present disclosure, a package includes a device die, which includes a metal pad, a first polymer layer covering edge portions of the metal pad, and a metal pillar extending into the first polymer layer to contact a first sidewall of the first polymer layer. The first sidewall of the first polymer layer has a first tilt angle. The package further includes an encapsulating material encapsulating the device die. A top surface of the metal pillar is coplanar with a top surface of the encapsulating material. A second polymer layer is over the encapsulating material and the device die. A redistribution line has a portion extending into the second polymer layer to contact a second sidewall of the second polymer layer. The second sidewall has a second tilt angle greater than the first tilt angle.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.