Patent ID: 12232328

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Various embodiments provide a memory device such as a 3D memory device. In some embodiments, the 3D memory device is a ferroelectric field effect transistor (FeFET) memory circuit including a plurality of vertically stacked memory cells. In some embodiments, each memory cell is regarded as a FeFET that includes a word line region acting as a gate electrode, a bit line region acting as a first source/drain electrode, a source line region acting as a second source/drain electrode, a ferroelectric material acting as a gate dielectric, and an oxide semiconductor (OS) acting as a channel region. In some embodiments, each memory cell is regarded as a thin film transistor (TFT).

FIGS.1A and1Billustrate examples of a memory device according to some embodiments.FIG.1Aillustrates an example of a portion of a simplified memory device200in a partial three-dimensional view, andFIG.1Billustrates a circuit diagram of the memory device200in accordance with some embodiments. The memory device200(also referred to as a memory array) includes a plurality of memory cells202, which may be arranged in a grid of rows and columns. The memory cells202may be further stacked vertically to provide a three dimensional memory device, thereby increasing device density. The memory device200may be disposed in the back end of line (BEOL) of a semiconductor die. For example, the memory device is disposed in the interconnect layers of the semiconductor die, such as, above one or more active devices (e.g., transistors) formed on a semiconductor substrate.

In some embodiments, the memory device200is a flash memory device, such as a NOR flash memory device, or the like. In some embodiments, a gate of each memory cell202is electrically coupled to a respective word line (e.g., conductive line72), a first source/drain region of each memory cell202is electrically coupled to a respective bit line (e.g., conductive line116B as shown inFIG.25C), and a second source/drain region of each memory cell202is electrically coupled to a respective source line (e.g., conductive line116B as shown inFIG.25C). The memory cells202in a same horizontal row of the memory device200may share a common word line while the memory cells202in a same vertical column of the memory device200may share a common source line and a common bit line.

The memory device200includes a plurality of vertically stacked conductive lines72(e.g., word lines) with dielectric layers52disposed between adjacent ones of the conductive lines72. The conductive lines72extend in a direction parallel to a major surface of an underlying substrate (not explicitly illustrated inFIG.1A), which may be a complementary metal oxide semiconductor (CMOS) under array (CUA) die. The conductive lines72may have a staircase configuration such that lower conductive lines72are longer than and extend laterally past endpoints of upper conductive lines72. For example, inFIG.1A, multiple, stacked layers of conductive lines72are illustrated with topmost conductive lines72being the shortest and bottommost conductive lines72being the longest. Respective lengths of the conductive lines72may increase in a direction towards the underlying substrate. In this manner, a portion of each of the conductive lines72may be accessible from above the memory device200, and conductive contacts may be made to exposed portions of the conductive lines72, respectively.

The memory device200further includes conductive pillars106(e.g., electrically connected to bit lines) and conductive pillars108(e.g., electrically connected to source lines) arranged alternately. The conductive pillars106and108may each extend in a direction perpendicular to the conductive lines72. A dielectric material98is disposed between and isolates adjacent ones of the conductive pillars106and the conductive pillars108.

Pairs of the conductive pillars106and108along with an intersecting conductive line72define boundaries of each memory cell202, and an isolation structure102is disposed between and isolates adjacent pairs of the conductive pillars106and108. In some embodiments, the conductive pillars108are electrically coupled to ground. AlthoughFIG.1Aillustrates a particular placement of the conductive pillars106relative the conductive pillars108, it should be appreciated that the placement of the conductive pillars106and108may be exchanged in other embodiments.

In some embodiments, the memory device200includes an oxide semiconductor (OS) material as a channel layer92. The channel layer92may provide channel regions for the memory cells202. For example, when an appropriate voltage (e.g., higher than a respective threshold voltage (Vth) of a corresponding memory cell202) is applied through a corresponding conductive line72, a region of the channel layer92that intersects the conductive line72allows current to flow between the conductive pillars106and the conductive pillars108(e.g., from the conductive pillars108to the conductive pillars106).

In some embodiments, a memory material layer90is disposed between the channel layer92and each of the conductive lines72and the dielectric layers52, and the memory material layer90serve as a gate dielectric for each memory cell202. In some embodiments, the memory material layer90includes a ferroelectric material, such as a hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, or the like.

The memory material layer90may be polarized in one of two different directions, and the polarization direction may be changed by applying an appropriate voltage differential across the memory material layer90and generating an appropriate electric field. The polarization may be relatively localized (e.g., generally contained within each boundaries of the memory cells202), and a continuous region of the memory material layer90may extend across a plurality of memory cells202. Depending on a polarization direction of a particular region of the memory material layer90, a threshold voltage of a corresponding memory cell202varies, and a digital value (e.g., 0 or 1) can be stored. For example, when a region of the memory material layer90has a first electrical polarization direction, the corresponding memory cell202may have a relatively low threshold voltage, and when the region of the memory material layer90has a second electrical polarization direction, the corresponding memory cell202may have a relatively high threshold voltage. The difference between the two threshold voltages may be referred to as the threshold voltage shift. A larger threshold voltage shift makes it easier (e.g., less error prone) to read the digital value stored in the corresponding memory cell202.

To perform a write operation on a memory cell202in such embodiments, a write voltage is applied across a portion of the memory material layer90corresponding to the memory cell202. In some embodiments, the write voltage is applied, for example, by applying appropriate voltages to a corresponding conductive line72(e.g., the word line) and the corresponding conductive pillars106/108(e.g., the bit line/source line). By applying the write voltage across the portion of the memory material layer90, a polarization direction of the region of the memory material layer90may be changed. As a result, the corresponding threshold voltage of the corresponding memory cell202may also be switched from a low threshold voltage to a high threshold voltage or vice versa, and a digital value may be stored in the memory cell202. Because the conductive lines72intersect the conductive pillars106and108, individual memory cells202may be selected for the write operation.

To perform a read operation on the memory cell202in such embodiments, a read voltage (a voltage between the low and high threshold voltages) is applied to the corresponding conductive line72(e.g., the world line). Depending on the polarization direction of the corresponding region of the memory material layer90, the memory cell202may or may not be turned on. As a result, the conductive pillar106may or may not be discharged through the conductive pillar108(e.g., a source line that is coupled to ground), and the digital value stored in the memory cell202can be determined. Because the conductive lines72intersect the conductive pillars106and108, individual memory cells202may be selected for the read operation.

FIG.1Afurther illustrates reference cross-sections of the memory device200that are used in later figures. Cross-section B-B′ is along a longitudinal axis of conductive lines72and in a direction, for example, parallel to the direction of current flow of the memory cells202. Cross-section C-C′ is perpendicular to cross-section B-B′ and extends through the dielectric materials98and the dielectric materials102. Cross-section D-D′ is perpendicular to cross-section B-B′ and extends through the dielectric materials98and the conductive pillars106. Subsequent figures refer to these reference cross-sections for clarity.

InFIG.2, a substrate50is provided. The substrate50may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate50may be an integrated circuit die, such as a logic die, a memory die, an ASIC die, or the like. The substrate50may be a CUA die. The substrate50may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate50may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof.

FIG.2further illustrates circuits that may be formed over the substrate50. The circuits include transistors at a top surface of the substrate50. The transistors may include gate dielectric layers302over top surfaces of the substrate50and gate electrodes304over the gate dielectric layers302. Source/drain regions306are disposed in the substrate50on opposite sides of the gate dielectric layers302and the gate electrodes304. Gate spacers308are formed along sidewalls of the gate dielectric layers302and separate the source/drain regions306from the gate electrodes304by appropriate lateral distances. The transistors may include fin field effect transistors (FinFETs), nanostructure (e.g., nanosheet, nanowire, gate-all-around, or the like) FETS (nano-FETs), planar FETs, the like, or combinations thereof, and may be formed by gate-first processes or gate-last processes.

A first inter-layer dielectric (ILD)310surrounds and isolates the source/drain regions306, the gate dielectric layers302, and the gate electrodes304and a second ILD312is over the first ILD310. Source/drain contacts314extend through the second ILD312and the first ILD310and are electrically coupled to the source/drain regions306and gate contacts316extend through the second ILD312and are electrically coupled to the gate electrodes304. An interconnect structure320is over the second ILD312, the source/drain contacts314, and the gate contacts316. The interconnect structure320includes one or more stacked dielectric layers324and conductive features322formed in the one or more dielectric layers324, for example. The interconnect structure320may be electrically connected to the gate contacts316and the source/drain contacts314to form functional circuits. In some embodiments, the functional circuits formed by the interconnect structure320may include logic circuits, memory circuits, sense amplifiers, controllers, input/output circuits, image sensor circuits, the like, or combinations thereof. AlthoughFIG.2discusses transistors formed over the substrate50, other active devices (e.g., diodes or the like) and/or passive devices (e.g., capacitors, resistors, or the like) may also be formed as part of the functional circuits.

InFIG.3, a multi-layer stack58is formed over the structure ofFIG.2. The substrate50, the transistors, the ILDs310and312, and the interconnect structure320may be omitted from subsequent drawings for the purposes of simplicity and clarity. Although the multi-layer stack58is illustrated as contacting the dielectric layers324of the interconnect structure320, any number of intermediate layers may be disposed between the substrate50and the multi-layer stack58. For example, one or more interconnect layers including conductive features in insulating layers (e.g., low-k dielectric layers) may be disposed between the substrate50and the multi-layer stack58. In some embodiments, the conductive features may be patterned to provide power, ground, and/or signal lines for the active devices on the substrate50and/or the memory device200(seeFIGS.1A and1B). In some embodiments, one or more interconnect layers including conductive features in insulating layers (e.g., low-k dielectric layers) are disposed over the multi-layer stack58.

InFIG.3, the multi-layer stack58includes alternating layers of sacrificial layers53A-53D (collectively referred to as sacrificial layers53) and dielectric layers52A-52E (collectively referred to as dielectric layers52). The sacrificial layers53may be patterned and replaced in subsequent steps to define conductive lines72(e.g., the word lines). The sacrificial layers53may include dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like. The dielectric layers52may include insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like. The sacrificial layers53and the dielectric layers52include different materials with different etching selectivities. In some embodiments, the sacrificial layers53include silicon nitride, and the dielectric layers52include silicon oxide. Each of the sacrificial layers53and the dielectric layers52may be formed using, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), or the like.

AlthoughFIG.3illustrates a particular number of the sacrificial layers53and the dielectric layers52, other embodiments may include different numbers of the sacrificial layers53and the dielectric layers52. Besides, although the multi-layer stack58is illustrated as having dielectric layers as topmost and bottommost layers, the disclosure is not limited thereto. In some embodiments, at least one of the topmost and bottommost layers of the multi-layer stack58is a sacrificial layer.

FIGS.4through12are views of intermediate stages in the manufacturing a staircase structure of the memory device200, in accordance with some embodiments.FIGS.4through12are illustrated along reference cross-section B-B′ illustrated inFIG.1A.

InFIG.4, a photoresist56is formed over the multi-layer stack58. In some embodiments, the photoresist56is formed by a spin-on technique and patterned by an acceptable photolithography technique. Patterning the photoresist56may expose the multi-layer stack58in regions60, while masking remaining portions of the multi-layer stack58. For example, a topmost layer of the multi-layer stack58(e.g., the dielectric layer52E) is exposed in the regions60.

InFIG.5, the exposed portions of the multi-layer stack58in the regions60are etched using the photoresist56as a mask. The etching may be any acceptable etching process, such as a dry etch (e.g., a reactive ion etch (RIE), a neutral beam etch (NBE), the like), a wet etch, the like, or a combination thereof. The etching may be anisotropic. The etching may remove portions of the dielectric layer52E and the sacrificial layer53D in the regions60and define openings61. Because the dielectric layer52E and the sacrificial layer53D have different material compositions, etchants used to remove exposed portions of these layers may be different. In some embodiments, the sacrificial layer53D acts as an etch stop layer while etching the dielectric layer52E, and the dielectric layer52D acts as an etch stop layer while etching sacrificial layer53D. As a result, the portions of the dielectric layer52E and the sacrificial layer53D may be selectively removed without removing remaining layers of the multi-layer stack58, and the openings61may be extended to a desired depth. Alternatively, a time-mode etching process may be used to stop the etching of the openings61after the openings61reach a desired depth. In the resulting structure, the dielectric layer52D is exposed in the regions60.

InFIG.6, the photoresist56is trimmed to expose additional portions of the multi-layer stack58. In some embodiments, the photoresist56is trimmed by using an acceptable removing technique such as a lateral etching. As a result of the trimming, a width of the photoresist56is reduced and portions the multi-layer stack58in the regions60and regions62may be exposed. For example, top surfaces of the dielectric layer52D may be exposed in the regions60, and top surfaces of the dielectric layer52E may be exposed in the regions62.

InFIG.7, portions of the dielectric layer52E, the sacrificial layer53D, the dielectric layer52D, and the sacrificial layer53C in the regions60and the regions62are removed by acceptable etching processes using the photoresist56as a mask. The etching may be any acceptable etching process, such as a dry etch (e.g., RIE, NBE, the like), a wet etch, the like, or a combination thereof. The etching may be anisotropic. The etching may extend the openings61further into the multi-layer stack58. Because the sacrificial layers53D and53C and the dielectric layers52E and52D have different material compositions, etchants used to remove exposed portions of these layers may be different. In some embodiments, portions of the dielectric layers52E and52D in the regions62and60are removed by using the photoresist56as a mask and using the underlying sacrificial layers53D and53C as etch stop layers. Thereafter, the exposed portions of the sacrificial layers53D and53C in the regions62and60are removed by using the photoresist56as a mask and using the underlying dielectric layers52D and52C as etching stop layers. In the resulting structure, the dielectric layer52C is exposed in the regions60, and the dielectric layer52D is exposed in the regions62.

InFIG.8, the photoresist56is trimmed to expose additional portions of the multi-layer stack58. In some embodiments, the photoresist56is trimmed by using an acceptable removing technique such as a lateral etching. As a result of the trimming, a width of the photoresist56is reduced, and portions the multi-layer stack58in the regions60, the regions62, and regions64may be exposed. For example, top surfaces of the dielectric layer52C are exposed in the regions60; top surfaces of the dielectric layer52D are exposed in the regions62; and top surfaces of the dielectric layer52E are exposed in the regions64.

InFIG.9, portions of the dielectric layers52E,52D, and52C and the sacrificial layers53D,53C, and53B in the regions60, the regions62, and the regions64are removed by acceptable etching processes using the photoresist56as a mask. The etching may be any acceptable etching process, such as a dry etch (e.g., RIE, NBE, the like), a wet etch, the like, or a combination thereof. The etching may be anisotropic. The etching may extend the openings61further into the multi-layer stack58. Because the dielectric layers52C-52E and the sacrificial layers53B-53D have different material compositions, etchants used to remove exposed portions of these layers may be different. In some embodiments, portions of the dielectric layers52E,52D and52C in the regions64,62and60are removed by using the photoresist56as a mask and using the underlying sacrificial layers53D.53C and53B as etch stop layers. Thereafter, the exposed portions of the sacrificial layers53D,53C and53B in the regions64,62and60are removed by using the photoresist56as a mask and using the underlying dielectric layers52D,52C and52B as etching stop layers. In the resulting structure, the dielectric layer52B is exposed in the regions60; the dielectric layer52C is exposed in the regions62; and the dielectric layer52D is exposed in the regions64.

InFIG.10, the photoresist56is trimmed to expose additional portions of the multi-layer stack58. In some embodiments, the photoresist56is trimmed by using an acceptable removing technique such as a lateral etching. As a result of the trimming, a width of the photoresist56is reduced, and portions the multi-layer stack58in the regions60, the regions62, the regions64, and regions66are exposed. For example, top surfaces of the dielectric layer52B are exposed in the regions60; top surfaces of the dielectric layer52C are exposed in the regions62; and top surfaces of the dielectric layer52D are exposed in the regions64; and top surfaces of the dielectric layer52E are exposed in the regions66.

InFIG.11, portions of the dielectric layers52E,52D,52C, and52B in the regions60, the regions62, the regions64, and the regions66are removed by acceptable etching processes using the photoresist56as a mask. The etching may be any acceptable etching process, such as a dry etch (e.g., RIE, NBE, the like), a wet etch, the like, or a combination thereof. The etching may be anisotropic. The etching may extend the openings61further into the multi-layer stack58. In some embodiments, portions of the dielectric layers52E,52D,52C and52B in the regions66,64,62and60are removed by using the photoresist56as a mask and using the underlying sacrificial layers53D,53C.53B and53A as etch stop layers. In the resulting structure, the sacrificial layer53A is exposed in the regions60; the sacrificial layer53B is exposed in the regions62; the sacrificial layer53C is exposed in the regions64; and the sacrificial layer53D is exposed in the regions66. Thereafter, the photoresist56may be removed by an acceptable ashing or wet strip process.

InFIG.12, an inter-metal dielectric (IMD)70is formed over the multi-layer stack58. The IMD70may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, PECVD, flowable CVD (FCVD), or the like. The dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. In some embodiments, the IMD70includes an oxide (e.g., silicon oxide or the like), a nitride (e.g., silicon nitride or the like), a combination thereof or the like. Other dielectric materials formed by any acceptable process may be used. Thereafter, a removal process is performed to remove excess dielectric material over the multi-layer stack58. In some embodiments, the removal process is a planarization process, such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like. The planarization process exposes the multi-layer stack58such that top surfaces of the multi-layer stack58and IMD70are level after the planarization process is completed. The IMD70extends along sidewalls of the sacrificial layers53B-53D and sidewalls of the dielectric layers52B-52E. Further, the IMD70may contact top surfaces of the sacrificial layers53A-53D and the dielectric layer52E.

As shown inFIG.12, an intermediate and bulk staircase structure is thus formed. The intermediate staircase structure includes alternating layers of sacrificial layers53and dielectric layers52. The sacrificial layers53are subsequently replaced with conductive lines72, which will be described in details inFIGS.16A and16B. Lower conductive lines72are longer and extend laterally past upper conductive lines72, and a width of each of the conductive lines72increases in a direction towards the substrate50(seeFIG.1A).

FIGS.13through16Bare views of intermediate stages in the manufacturing of a memory region of the memory device200, in accordance with some embodiments. InFIGS.13through16B, the bulk multi-layer stack58is patterned to form trenches86therethrough, and sacrificial layers53are replaced with conductive materials to define the conductive lines72. The conductive lines72may correspond to word lines in the memory device200, and the conductive lines72may further provide gate electrodes for the resulting memory cells of the memory device200.FIGS.13,14,15B and16Bare illustrated along reference cross-section C-C′ illustrated inFIG.1A.FIGS.15A and16Aare illustrated in a partial three-dimensional view.

InFIG.13, photoresist patterns82and underlying hard mask patterns80are formed over the multi-layer stack58. In some embodiments, a hard mask layer and a photoresist layer are sequentially formed over the multi-layer stack58. The hard mask layer may include, for example, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. The photoresist layer is formed by a spin-on technique, for example.

Thereafter, the photoresist layer is patterned to form photoresist patterns82and trenches86between the photoresist patterns82. The photoresists is patterned by an acceptable photolithography technique, for example. The patterns of the photoresist patterns82are then transferred to the hard mask layer to form hard mask patterns80by using an acceptable etching process, such as by a dry etch (e.g., RIE, NBE, the like), a wet etch, the like, or a combination thereof. The etching may be anisotropic. Thus, trenches86are formed extending through the hard mask layer. Thereafter, the photoresist82may be optionally removed by an ashing process, for example.

InFIGS.14to15B, the patterns of the hard mask patterns80are transferred to the multi-layer stack58using one or more acceptable etching processes, such as by a dry etch (e.g., RIE, NBE, the like), a wet etch, the like, or a combination thereof. The etching processes may be anisotropic. Thus, the trenches86extend through the bulk multi-layer stack58, and strip-shaped sacrificial layers53and strip-shaped dielectric layers52are accordingly defined. In some embodiments, the trenches86extend through the bulk staircase structure, and strip-shaped staircase structures are accordingly defined. The hard mask patterns80may be then removed by an acceptable process, such as a wet etching process, a dry etching process, a planarization process, combinations thereof, or the like.

InFIGS.15A to16B, the sacrificial layers53A-53D (collectively referred to as sacrificial layers53) are replaced with conductive lines72A-72D (collectively referred to as conductive lines72). In some embodiments, the sacrificial layers53are removed by an acceptable process, such as a wet etching process, a dry etching process or both. Thereafter, conductive lines72are filled into the spacing between two adjacent dielectric layers52. As shown in the local enlarged view, each conductive line72includes two barrier layers71and75and a metal layer73between the barrier layers71and75. Specifically, a barrier layer is disposed between the metal layer73and the adjacent dielectric layer52. The barrier layers may prevent the metal layer from diffusion to the adjacent dielectric layers52. The barrier layers may also provide the function of increasing the adhesion between the metal layer and the adjacent dielectric layers, and may be referred to as glue layers in some examples. In some embodiments, both barrier layers and glue layers with different materials are provided as needed. The barrier layers71and75are formed of a first conductive material, such as a metal nitride, such as titanium nitride, tantalum nitride, molybdenum nitride, zirconium nitride, hafnium nitride, or the like. The metal layer73may are formed of a second conductive material, such as a metal, such as tungsten, ruthenium, molybdenum, cobalt, aluminum, nickel, copper, silver, gold, alloys thereof, or the like. The barrier layers71,75and metal layer73may each be formed by an acceptable deposition process such as CVD, PVD, ALD, PECVD, or the like. The barrier layers71,75and the metal layer73are further deposited on the sidewalls of the multi-layer stack58and fill in the trenches86. Thereafter, the barrier layers71,75and the metal layer73in the trenches86are removed by an etching back process. An acceptable etch back process may be performed to remove excess materials from the sidewalls of the dielectric layers52and the bottom surfaces of the trenches86. The acceptable etch back process includes a dry etch (e.g., RIE, NBE, the like), a wet etch, the like, or a combination thereof. The acceptable etch back process may be anisotropic.

In some embodiments, upon the replacement process, the sacrificial layers53of the strip-shaped staircase structures are subsequently replaced with conductive lines72(seeFIG.1A), so as to form a plurality of strip-shaped staircase structures68. In some embodiments, the strip-shaped staircase structure68includes alternating layers of conductive lines72A-72D (collectively referred to as conductive lines72) and dielectric layers52A-52E (collectively referred to as dielectric layers52).

FIGS.17through22Billustrate forming and patterning channel regions for the memory cells202(seeFIG.1A) in the trenches86.FIGS.20A,21A and22Aare illustrated in a partial three-dimensional view. InFIGS.17,18,19,20B,21B and22Bcross-sectional views are provided along line C-C′ ofFIG.1A.

InFIG.17, a memory material layer90, a channel layer92, and a dielectric material98A are deposited in the trenches86. In some embodiments, the memory material layer90is deposited conformally in the trenches86along sidewalls of the conductive lines72and along top surfaces of the dielectric layer52E, and along the bottom surfaces of the trenches86. In some embodiments, a memory material layer90may be further deposited on the IMD70and along the sidewall of each step of the staircase structure in the staircase region. The memory material layer90may include materials that are capable of switching between two different polarization directions by applying an appropriate voltage differential across the memory material layer90. For example, the memory material layer90includes a high-k dielectric material, such as a hafnium (Hf) based dielectric materials or the like. In some embodiments, the memory material layer90includes hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, or the like.

The memory material layer90may include barium titanium oxide (BaTiO3), lead titanium oxide (PbTiO3), lead zirconium oxide (PbZrO3), lithium niobium oxide (LiNbO3), sodium niobium oxide (NaNbO3), potassium niobium oxide (KNbO3), potassium tantalum oxide (KTaO3), bismuth scandium oxide (BiScO3), bismuth iron oxide (BiFeO3), hafnium erbium oxide (Hf1-xErxO), hafnium lanthanum oxide (Hf1-xLaxO), hafnium yttrium oxide (Hf1-xYxO), hafnium gadolinium oxide (Hf1-xGdxO), hafnium aluminum oxide (Hf1-xAlxO), hafnium zirconium oxide (Hf1-xZrxO, HZO), hafnium titanium oxide (Hf1-xTixO), hafnium tantalum oxide (Hf1-xTaxO), or the like. In some embodiments, the memory material layer90may include different ferroelectric materials or different types of memory materials. For example, in some embodiments, the memory material layer90may be replaced with a non-ferroelectric material, such as a multilayer memory structure including a layer of SiNxbetween two SiOxlayers (e.g., an ONO structure). In some embodiments, the method of forming the memory material layer90includes performing a suitable deposition technique, such as CVD, PECVD, metal oxide chemical vapor deposition (MOCVD), ALD, RPALD, PEALD, MBD or the like.

In some embodiments, the memory material layer90has a thickness of about 1-20 nm, such as 5-10 nm. Other thickness ranges (e.g., more than 20 nm or 5-15 nm) may be applicable. the memory material layer90is formed in a fully amorphous state. In alternative embodiments, the memory material layer90is formed in a partially crystalline state; that is, the memory material layer90is formed in a mixed crystalline-amorphous state and having some degree of structural order. In yet alternative embodiments, the memory material layer90is formed in a fully crystalline state. In some embodiments, the memory material layer90is a single layer. In alternative embodiments, the memory material layer90is a multi-layer structure.

After the memory material layer90is deposited, an annealing step may be performed, so as to achieve a desired crystalline lattice structure for the memory material layer90. In some embodiments, upon the annealing process, the memory material layer90is transformed from an amorphous state to a partially or fully crystalline state. In alternative embodiments, upon the annealing memory material layer90is transformed from a partially crystalline state to a fully crystalline state.

Then, the channel layer92is conformally deposited in the trenches86over the memory material layer90. The channel layer92includes materials suitable for providing channel regions for the memory cells202(seeFIG.1A). For example, the channel layer92includes oxide semiconductor (OS) such as zinc oxide (ZnO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO, IGZO), indium zinc oxide (InZnO), indium tin oxide (ITO), combinations thereof, or the like. In some embodiments, the channel layer92includes polycrystalline silicon (poly-Si), amorphous silicon (a-Si), or the like. The channel layer92may be deposited by CVD, PVD, ALD, PECVD, or the like. The channel layer92may extend along the sidewalls and the bottom surfaces of the trenches86over the memory material layer90. After the channel layer92is deposited, an annealing step may be performed to activate the charge carriers of the channel layer92.

In some embodiments, the dielectric material98A is deposited in the trenches86over the channel layer92. In some embodiments, the dielectric material98A includes silicon oxide, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. The dielectric material98A may extend along sidewalls and bottom surfaces of the trenches86over the channel layer92. In some embodiments, the dielectric material98A is optional and may be omitted as needed.

InFIG.18, bottom portions of the dielectric material98A and the channel layer92are removed in the trenches86. The removal process includes an acceptable etching process, such as a dry etch (e.g., RIE, NBE, the like), a wet etch, the like, or a combination thereof. The etching may be anisotropic. In some embodiments, the top portions of the dielectric material98A and the channel layer92are removed from the strip-shaped staircase structures68. In some embodiments, removal process includes a combination of photolithography and etching.

Accordingly, the remaining dielectric material98A and the channel layer92may expose portions of the memory material layer90on bottom surfaces of the trenches86. Thus, portions of the channel layer92on opposing sidewalls of the trenches86may be separated from each other, which improves isolation between the memory cells202of the memory device200(seeFIG.1A).

InFIG.19, a dielectric material98B is deposited to completely fill the trenches86. The dielectric material98B may be formed of one or more materials and by processes the same as or similar to those of the dielectric material98A. In some embodiments, the dielectric material98B and the dielectric material98A include different materials.

InFIGS.20A and20B, a removal process is applied to the dielectric materials98A/98B, the channel layer92, and the memory material layer90to remove excess materials over the strip-shaped staircase structures68. In some embodiments, a planarization process such as a CMP, an etch-back process, combinations thereof, or the like may be utilized. The planarization process exposes the strip-shaped staircase structures68such that top surfaces of the strip-shaped staircase structures68(e.g., the dielectric layer52E), the memory material layer90, the channel layer92, the dielectric materials98A/98B, and the IMD70are level after the planarization process is complete.

FIGS.21A through24Billustrate intermediate steps of manufacturing conductive pillars106and108(e.g., source/drain pillars) in the memory device200. The conductive pillars106and108may extend along a direction perpendicular to the conductive lines72such that individual cells of the memory device200may be selected for read and write operations.FIGS.21A,22A,23A and24Aare illustrated in a partial three-dimensional view. InFIGS.21B and22B, cross-sectional views are provided along line C-C′ ofFIG.1A. InFIGS.23B and24B, cross-sectional views are provided along line D-D′ ofFIG.1A.

InFIGS.21A and21B, trenches100are patterned through the channel layer92and the dielectric materials98A/98B. Patterning the trenches100may be performed through a combination of photolithography and etching, for example. The trenches100may be disposed between opposing sidewalls of the memory material layer90, and the trenches100may physically separate adjacent stacks of memory cells in the memory device200(seeFIG.1A).

As illustrated inFIG.21A, the trenches100may be formed in peripheral areas adjacent the IMD70by patterning the dielectric materials98and the OS layer92. Dielectric materials (such as the dielectric materials102, discussed below with respect toFIGS.22A and22B) may be subsequently formed in the trenches100in the peripheral areas adjacent the IMD70and the dielectric materials may be subsequently patterned to form conductive contacts (such as the conductive contacts110, discussed below with respect toFIGS.25A through25D) to underlying structures, such as the interconnect structures320.

InFIGS.22A and22B, dielectric materials102are formed in the trenches100. In some embodiments, an isolation layer is deposited over the strip-shaped staircase structures68filling in the trenches100. The isolation layer may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD. PVD, ALD, PECVD, or the like. The isolation layer may extend along sidewalls and bottom surfaces of the trenches100over the channel layer92. After deposition, a planarization process (e.g., a CMP, etch back, or the like) may be performed to remove excess portions of the isolation layer. In the resulting structure, top surfaces of the strip-shaped staircase structures68(e.g., dielectric layer52E), the memory material layer90, the channel layer92, and the dielectric materials102may be substantially level (e.g., within process variations). In some embodiments, materials of the dielectric materials98A/98B and dielectric materials102may be selected so that they may be etched selectively relative each other. For example, in some embodiments, the dielectric materials98A/98B include oxide and the dielectric materials102include nitride. In some embodiments, the dielectric materials98A/98B include nitride and the dielectric materials102include oxide. Other materials are also possible.

InFIGS.23A and23B, trenches104are defined for the subsequently formed the conductive pillars106and108. The trenches104are formed by patterning the dielectric materials98A/98B with a combination of photolithography and etching, for example. In some embodiments, a photoresist (not shown) is formed over the strip-shaped staircase structures68, the dielectric materials98A/98B, the dielectric materials102, the channel layer92, and the memory material layer90. In some embodiments, the photoresist is patterned by an acceptable photolithography technique to define openings (not shown). Each of the openings may expose the corresponding dielectric material102and two separate regions of the dielectric materials98A/98B beside the dielectric material102. In this way, each of the openings may define a pattern of a conductive pillar106and an adjacent conductive pillar108that are separated by the dielectric materials102.

Subsequently, portions of the dielectric materials98A/98B exposed by the openings may be removed by an acceptable etching process, such as by a dry etch (e.g., RIE, NBE, the like), a wet etch, the like, or a combination thereof. The etching may be anisotropic. The etching process may use an etchant that etches the dielectric materials98A/98B without significantly etching the dielectric materials102. As a result, even though the openings expose the dielectric materials102, the dielectric materials102may not be significantly removed. Patterns of the trenches104may correspond to the conductive pillars106and108(seeFIGS.24A and24B). After the trenches104are patterned, the photoresist may be removed by ashing, for example.

InFIGS.24A and24B, the trenches104are filled with a conductive material to form the conductive pillars106and108. The conductive material may include copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, or the like, which may be formed using, for example, CVD, ALD, PVD, PECVD, or the like. After the conductive material is deposited, a planarization (e.g., a CMP, etch back, or the like) may be performed to remove excess portions of the conductive material, thereby forming the conductive pillars106and108. In the resulting structure, top surfaces of the strip-shaped staircase structures68(e.g., the dielectric layer52E), the memory material layer90, the channel layer92, the conductive pillars106, and the conductive pillars108may be substantially level (e.g., within process variations). In some embodiments, the conductive pillars106correspond to and are electrically connected to the bit lines in the memory device, and the conductive pillars108correspond to correspond to and are electrically connected to the source lines in the memory device200. In alternative embodiments, the conductive pillars106correspond to and are electrically connected to the source lines in the memory device, and the conductive pillars108correspond to correspond to and are electrically connected to the bit lines in the memory device200.

As illustrated inFIG.24A, the memory device200may include a memory cell region204A, a first staircase region204B and a second staircase region204C. The first staircase region204B and the second staircase region204C include portions of the IMD70, portions of the dielectric materials102, portions of the memory material layer90, portions of the conductive lines72A-72D, and portions of the dielectric layers52A-52D. The memory cell region204A includes portions of the conductive lines72A-72D, portions of the dielectric layers52A-52D, the dielectric layer52E, the conductive lines106, the conductive lines108, the dielectric materials98, portions of the dielectric materials102, portions of the memory material layer90, and the channel layer92.

In some embodiments, stacked memory cells202are formed in the memory device200, as shown inFIG.24A. Each memory cell202includes a gate electrode (e.g., a portion of a corresponding conductive line72), a gate dielectric (e.g., a portion of a corresponding memory material layer90), a channel region (e.g., a portion of a corresponding channel layer92), and source/drain pillars (e.g., portions of corresponding conductive pillars106and108). The dielectric materials102isolates adjacent memory cells202in a same column and at a same vertical level. The memory cells202may be disposed in an array of vertically stacked rows and columns.

FIGS.25A through25Dillustrate intermediate steps of manufacturing conductive contacts and conductive lines.FIG.25Aillustrates a perspective view of the memory device200;FIG.25Billustrates a cross-sectional view of the device along line D-D′ ofFIG.1A;FIG.25Cillustrates a top-down view of the memory device200; andFIG.25Dillustrates a cross-sectional view of the device along line B-B′ ofFIG.1A.

InFIGS.25A,25B,25C and25D, an IMD74is formed on top surfaces of the strip-shaped staircase structures68(e.g., the dielectric layer52E), the memory material layer90, the channel layer92, the conductive pillars106, and the conductive pillars108and the IMD70. The IMD74may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, PECVD, flowable CVD (FCVD), or the like. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other dielectric materials formed by any acceptable process may be used. Thereafter, a removal process is applied to the IMD74to remove excess dielectric material over the strip-shaped staircase structures68. In some embodiments, the removal process may be a planarization process, such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like.

Then, conductive contacts110,112, and114are formed on the conductive lines72, the conductive pillars106, and the conductive pillars108, respectively. In some embodiments, forming the conductive contacts110,112, and114includes patterning openings in the IMD74and the IMD70to expose portions of the conductive lines72, the conductive pillars106, and the conductive pillars108using a combination of photolithography and etching. A liner (not shown), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may include copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from the surface of the IMD74. The remaining liner and conductive material form the conductive contacts110,112, and114in the openings. In some embodiments, the conductive contacts110,112, and114are formed simultaneously. In alternative embodiments, the conductive contacts110,112, and114are formed separately.

In some embodiments, as shown inFIGS.25A,25C and25D, after forming the conductive contacts110,112, and114, conductive lines116A,116B are formed over the IMD74in the memory cell region204A, and conductive lines116C are formed over the IMD74in at least one of the first staircase region204B and the second staircase region204C. As shown inFIGS.25A and25C, the conductive lines116B and the conductive lines116B may each extend in a direction perpendicular to the conductive lines72. The conductive lines116B are electrically connected to the conductive pillars106through the conductive contacts112, and the conductive lines116B are electrically connected to the conductive pillars108through the conductive contacts114. The conductive lines116C are electrically connected to the conductive lines72through the conductive contacts110. In some embodiments, the conductive contacts110,112, and114and the conductive lines116A,116B, and116C connect the memory device200to an underlying/overlying circuitry (e.g., control circuitry) and/or signal, power, and ground lines, respectively. Other conductive contacts or vias may be formed through the IMD74and the IMD70to electrically connect the conductive lines116A,116B, and116C to the underlying active devices of the substrate. In alternative embodiments, routing and/or power lines to and from the memory device are provided by an interconnect structure formed over the memory device200in addition to or in lieu of the interconnect structure320. In some embodiments, the conductive lines116A,116B,116C are formed using a combination of photolithography and etching techniques. The conductive lines116A,116B,116C may include copper, silver, gold, tungsten, aluminum, combinations thereof, or the like. In addition, the conductive lines116A,116B,116C may have other configurations.

In some embodiments, the staircase shape of the conductive lines72provides a surface on each of the conductive lines72for conductive contacts110to land on. The conductive line72has opposite side78a,78b, and the conductive contact110for the conductive line72are disposed on one of the sides78a,78b. For example, as shown inFIGS.25A and25C, the conductive contacts110for the strip-shaped staircase structure68are disposed at the same side78aof the conductive lines72. In some embodiments, the opposite sides78aand78bare also referred to as opposite sides of the memory region204A or opposite sides of the strip-shaped staircase structures68. In some embodiments, the strip-shaped staircase structure68includes a staircase69A in the first staircase region204B and a staircase69B in the second staircase region204C. The conductive contacts110may be formed on the conductive lines72in at least one of the first staircase region204B and the second staircase region204C. In an embodiment in which the conductive contacts110for the strip-shaped staircase structure68are all disposed on the staircase69A (as shown inFIGS.25A and25C), the staircase69A is also referred to as a used staircase, and the staircase69B is also referred to as a non-used staircase. In some embodiments, the conductive contacts110for the strip-shaped staircase structures68are all disposed at the same side (e.g., the side78a). In alternative embodiments (not shown), some of the conductive contacts110for the strip-shaped staircase structures68are disposed at one side (e.g., the side78a), and some of the conductive contacts110for the strip-shaped staircase structures68are disposed at the other side (e.g., the side78b).

In some embodiments, the conductive contacts110electrically connect the conductive lines72to the conductive lines116C and the underlying drivers (not shown) such as CMOS devices. In some embodiments, the drivers (e.g., words line drivers) are disposed corresponding to the conductive contacts110. For example, the drivers are disposed at one of the opposite sides78a,78bof the conductive lines72(also referred to as opposite sides of the memory region204A or opposite sides of the strip-shaped staircase structure68). In some embodiments, the drivers for the strip-shaped staircase structure68are disposed under the memory device200at the side78ain the first staircase region204B. In an embodiment in which the drivers are disposed at single side (i.e., the side78aor the side78b) of the conductive lines72, the strip-shaped staircase structure68is also referred to as a single-sided driving structure or a single-sided routing structure.

In some embodiments, the conductive lines116A and the conductive lines116B are alternately arranged over the staircase structures68. The conductive lines116A have widths W1, . . . . Wn-1, and Wn, in which n is the total number of the conductive lines116A over the strip-shaped staircase structure68and n is an integer larger than 1. The conductive line116A which is closest to the side78a/the conductive contacts110/the drivers/the used staircase69A has the width W1, and the conductive line116A which is farthest from the side78a/the conductive contacts110/the drivers/the used staircase69A (also closest to the side78b/the non-used staircase69B) has the width Wn. In some embodiments, the strip-shaped staircase structure68is a single-sided driving structure, the widths W1, . . . . Wn-1, and Wnof the conductive lines116A are increased as the conductive lines116A become far away from the side (i.e., the side78aor the side78b) at which the drivers are disposed, namely W1< . . . <Wn-1<Wn. For example, as shown inFIG.25C, the drivers are disposed at the side78a, and the widths W1, W2, W3, and W4of the conductive lines116A are increased as the conductive lines116A become far away from the side78a, namely W1<W2<W3<W4. In some embodiments, the strip-shaped staircase structure68is a single-sided driving structure, the widths W1, . . . . Wn-1, and Wnof the conductive lines116A are gradually increased along a direction from the used staircase69A to the non-used staircase69B. In some embodiments, the widths W1, . . . . Wn-1, and Wnare in a range of about 10 nm to about 20 nm. In some embodiments, the width Wnis substantially equal to the width W1and W1/n, namely Wn=W1+W1/n. A ratio of Wn/W1may be in a range of about 5 to about 20.

In some embodiments, spacings S1, . . . . Sn-1, and Snof the conductive lines116A, are different. The spacings S1, . . . . Sn-1, and Snmay be decreased as the spacings S1, . . . . Sn-1, and Snbecome far away from the side78aat which the drivers are disposed, namely S1> . . . >Sn-1>Sn. For example, as shown inFIG.25C, the drivers are disposed at the side78a, and the spacings S1, S2, S3, and S4are decreased as the spacings S1, S2, S3, and S4become far away from the side78a, namely S1>S2>S3>S4. A ratio of width W1, . . . . Wn-1, Wnto respective spacing S1, . . . . Sn-1, Snmay be in a range of about 1 to about 20. In some embodiments, the total of the width W1, . . . . Wn-1, Wnand the respective spacing S1, . . . . Sn-1, Snof the conductive line116A is substantially the same, namely W1+S1= . . . =Wn-1+Sn-1=Wn+Sn. In alternative embodiments, the spacings S1, . . . . Sn-1, and Snof the conductive lines116A are constant.

The conductive lines116B have widths W′1, . . . . W′n-1, and W′n, in which n is the total number of the conductive lines116B over the strip-shaped staircase structure68and n is an integer larger than 1. The conductive line116B which is closest to the side78a/the conductive contacts110/the drivers/the used staircase69A has the width W′1, and the conductive line116B which is farthest from the side78a/the conductive contacts110/the drivers/the used staircase69A (also closest to the side78b/the non-used staircase69B) has the width W′n. In some embodiments, the strip-shaped staircase structure68is a single-sided driving structure, the widths W′1, . . . . W′n-1, and W′nof the conductive lines116B are increased as the conductive lines116B become far away from the side (i.e., the side78aor the side78b) at which the drivers are disposed, namely W′1< . . . <W′n-1<W′n. For example, as shown inFIG.25C, the drivers are disposed at the side78a, and the widths W′1. W′2, W′3, and W′4of the conductive lines116B are increased as the conductive lines116B become far away from the side78a, namely W′1<W′2<W′3<W′4. In some embodiments, the strip-shaped staircase structure68is a single-sided driving structure, the widths W′1, . . . . W′n-1, and W′nof the conductive lines116B are gradually increased along a direction from the used staircase69A to the non-used staircase69B. In some embodiments, the widths W′1, . . . . W′n-1, and W′nare in a range of about 10 nm to about 20 nm. In some embodiments, the width W′nis substantially equal to the width W′1and W′1/n, namely W′n=W′1+W′1/n. A ratio of W′n/W′1may be in a range of about 5 to about 20.

In some embodiments, spacings S′1, . . . . S′n-1, and S′nof the conductive lines116B, are different. The spacings S′1, . . . . S′n-1, and S′nmay be decreased as the spacings S′1, . . . . S′n-1, and S′nbecome far away from the side78aat which the drivers are disposed, namely S′1> . . . >S′n-1>S′n. For example, as shown inFIG.25C, the drivers are disposed at the side78a, and the spacings S′1, S′2, S′3, and S′4are decreased as the spacings S′1, S′2, S′3, and S′4become far away from the side78a, namely S′1>S′2>S′3>S′4. A ratio of width W′1, . . . . W′n-1. W′nto respective spacing S′1, . . . . S′n-1, S′nmay be in a range of about 1 to about 20. In some embodiments, the total of the width W′1, . . . . W′n-1. W′nand the respective spacing S′1, . . . . S′n-1, S′nof the conductive line116B is substantially the same, namely W′1, +S′1= . . . =W′n-1+S′n-1=W′n+S′n. In alternative embodiments, the spacings S′1, . . . . S′n-1, and S′nof the conductive lines116B are constant.

In some embodiments, the widths W1, W′1, . . . . Wn-1, W′n-1, Wn, and W′nof the conductive lines116A and116B are increased as the conductive lines116B and116B become far away from the side78aat which the drivers are disposed, namely W1<W′1< . . . <Wn-1<W′n-1<Wn<W′n. For example, as shown inFIG.25C, the widths W1. W1, W′1. W2, W′2. W3, W′3. W4, and W′4of the conductive lines116A and116B are increased as the conductive lines116B and116B become far away from the side78aat which the drivers are disposed, namely W1<W′1<W2<W′2<W3<W′3<W4<W′4. In some embodiments, the conductive lines116A are bit lines, the conductive lines116B are source lines. In alternative embodiments, the conductive lines116A are source lines, the conductive lines116B are bit lines. In alternative embodiments, the adjacent two of the conductive lines116A and the conductive lines116B have substantially the same width, namely W1=W′1, . . . . Wn-1=W′n-1, and Wn=W′n. In some embodiments, the conductive lines116A and the conductive lines116B are alternately disposed over the staircase structures68. However, the disclosure is not limited thereto. The conductive lines116A and the conductive lines116B are arranged corresponding to the conductive pillars106and108. Additionally, in alternative embodiments, the conductive lines116A are disposed over the staircase structures68while the conductive lines116B are disposed under the staircase structures68. In alternative embodiments, the conductive lines116A are disposed under the staircase structures68while the conductive lines116B are disposed over the staircase structures68.

Generally, the memory device may have the worst bit which usually have a corresponding minimum read current. In some embodiments, by adjusting the widths of the conductive lines116A,116B, the resistance of the conductive lines116A,116B is optimized, and thus the worst bit performance in the memory device such as 3D ferroelectric memory device is improved.

FIG.26illustrates an embodiment in which the drivers are disposed at both sides78a,78bof each of the conductive lines72. The embodiment illustrated inFIG.26provides double the number of drivers to the conductive lines72and provides drivers for each of the conductive lines72in both of the first staircase region204B and the second staircase region204C. In some embodiments, the strip-shaped staircase structure68are also referred to as a double-sided driving structure or a double-sided routing structure. In such embodiments, the staircase69A and the staircase69B are both used staircase, and there is no non-used staircase in the strip-shaped staircase structures68.

In some embodiments, the drivers are disposed at both sides78a,78bof the conductive lines72. The conductive lines116A and the conductive lines116B may be alternately arranged, and the conductive lines116A,116B have widths W1, W′1, . . . . Wn-1, W′n-1. Wn, and W′n, in which n is an integer larger than 2. The conductive line116A.116B which is closest to the side78a/the conductive contacts110/the drivers/the first staircase region204B has the width W1, W′1, and the conductive line116A,116B which is closest to the side78b/the conductive contacts110/the drivers/the second staircase region204C has the width Wn, W′n. In some embodiments, the drivers are disposed at both sides78a,78b, and a middle205between the staircase region204B and the staircase region204C is farthest from the sides78a,78b. The middle205between the staircase region204B and the staircase region204C may be also referred to as a middle of the memory region204A. In some embodiments, the widths W1, W1, W′1, . . . . Wn-1, W′n-1. Wn, and W′nof the conductive lines116A,116B are increased as the conductive lines116A,116B become close to the middle205between the staircase region204B and the staircase region204C (also far away from the sides78a,78bat which the drivers are disposed). For example, as shown inFIG.26, the conductive lines116A,116B have widths W1, W′1. W2. W′2, W3, W′3, W4, W′4, W5, W′5, W6, and W′6, and the widths W1, W′1. W2, W′2, W3, W′3, W4, W′4, W5, W′5, W6, and W′6of the conductive lines116A,116B are increased as the conductive lines116A,116B become close to the middle205, namely W1<W2<W3, W6<W5<W4. W′1<W′2<W′3and W′6<W′5<W′4. In an embodiment in which the conductive lines116A and116B are arranged adjacently, the widths W1, W′1, W2, W′2. W3, W′3, W4, W′4, W5, W′5. W6, and W′6of the conductive lines116A,116B are increased as the conductive lines116A,116B become close to the middle205, namely W1<W′1<W2<W′2<W3<W′3and W′6<W6<W′5<W5<W′4<W4. In some embodiments, the conductive lines116A,116B opposite to each other with respect to the middle205have substantially the same width, for example, as shown inFIG.26, W1=W′6, W2=W′5, W3=W′4, W4=W′3, W5=W′2, and W6=W′1. In alternative embodiments, the conductive lines116A,116B opposite to each other with respect to the middle205have different widths. In some embodiments, the conductive lines116A,116B are symmetrically arranged with respect to the middle205between the staircase region204B and the staircase region204C. However, the disclosure is not limited thereto. In some embodiments, the total number of the conductive lines116A,116B may be odd or even, and the widths of other conductive lines116A and116B are decreased as the conductive lines116A and116B become far away from the middle205. In some embodiments, the widths W1. W′1, . . . . Wn-1, W′n-1, Wn, and W′nare in a range of about 10 nm to about 20 nm.

In some embodiments, the spacings S1, . . . . Sn-1, and Snof the conductive lines116A are increased as the spacings S1, . . . . Sn-1, and Snbecome close to the middle205, and the spacings S′1, . . . . S′n-1, and S′nof the conductive lines116B are increased as the spacings S′1, . . . . S′n-1, and S′nbecome close to the middle205. For example, as shown inFIG.26, the conductive lines116A,116B have spacings S1, S′1, S2, S′2, S3, S′3, S4, S′4, S5, S′5, S6, and S′6and the spacings S1, S′1, S2, S′2, S3, S′3, S4, S′4, S5, S′5, S6, and S′6are increased as the spacings become close to the middle205, namely S1>S2>S3, S6>S5>S4. S′1>S′2>S′3and S′6>S′5>S′4. In an embodiment in which the conductive lines116A and116B are arranged adjacently, the spacings S′1, S2, S′2, S3, S′3, S4, S′4, S5, S′5, S6, and S′6are increased as the spacings become close to the middle205, namely S1>S′1>S2>S′2>S3>S′3and S′6>S6>S′5>S5>S′4>S4. In alternative embodiments, the spacings S1, S′1, . . . . Sn-1, S′n-1, Sn, and S′nare constant. A ratio of width W1, W′1, . . . . Wn-1, W′n-1. Wn, W′nto respective spacing S1, S′1, . . . . Sn-1, S′n-1. Sn. S′nmay be in a range of about 1 to about 20. In some embodiments, the total of the width W1, W′1, . . . . Wn-1. W′n-1, Wn, W′nand the respective spacing S1, S′1, . . . . Sn-1, S′n-1. Sn, S′nis substantially the same, namely W1+S1= . . . =Wn-1+Sn-1=Wn+Sn=W′1+S′1= . . . =W′n-1+S′n-1=W′n+S′n. In some embodiments, the conductive lines116A and the conductive lines116B are alternately disposed over the staircase structures68. However, the disclosure is not limited thereto. The conductive lines116A and the conductive lines116B are arranged corresponding to the conductive pillars106and108. Additionally, in alternative embodiments, the conductive lines116A are disposed over the staircase structures68while the conductive lines116B are disposed under the staircase structures68. In alternative embodiments, the conductive lines116A are disposed under the staircase structures68while the conductive lines116B are disposed over the staircase structures68.

Generally, the memory device may have the worst bit which usually have a corresponding minimum read current. In some embodiments, by adjusting the widths of the conductive lines116A,116B, the resistance of the conductive lines116A,116B is optimized, and thus the worst bit performance in the memory device such as 3D ferroelectric memory device is improved.

Although the embodiments ofFIGS.1A through26illustrate a particular pattern for the conductive pillars106and108, other configurations are also possible. For example, in these embodiments, the conductive pillars106and108have a staggered pattern. However, in other embodiments, the conductive pillars106and108in a same row of the array are all aligned with each other, as shown in the memory device200ofFIG.27. In such embodiments, the widths of the conductive lines116B and116B are increased as the conductive lines116B and116B become far away from the side at which the drivers are disposed as described above forFIGS.25C and26.

In some embodiments of the disclosure, the memory device is single-sided driving or double-sided driving, in other words, the drivers may be disposed at one side or both sides of the staircase structure. In some embodiments of the disclosure, the widths of the conductive lines are increased as the conductive lines become far away from the side at which the drivers are disposed. Therefore, the resistance of the conductive lines is optimized, and the worst bit performance in the memory device such as 3D ferroelectric memory device is improved.

In the above embodiments, the memory device is formed by a “staircase first process” in which the staircase structure is formed before the memory cells are formed. However, the disclosure is not limited thereto. In other embodiments, the memory device may be formed by a “staircase last process” in which the staircase structure is formed after the memory cells are formed.

In the above embodiments, the gate electrodes (e.g., word lines) are formed by depositing sacrificial dielectric layers followed by replacing sacrificial dielectric layers with conductive layers. However, the disclosure is not limited thereto. In other embodiments, the gate electrodes (e.g., word lines) may be formed in the first stage without the replacement step as needed.

Many variations of the above examples are contemplated by the present disclosure. It is understood that different embodiments may have different advantages, and that no particular advantage is necessarily required of all embodiments.

In accordance with some embodiments of the present disclosure, a memory device includes a multi-layer stack. The multi-layer stack is disposed on a substrate and includes a plurality of first conductive lines and a plurality of dielectric layers stacked alternately, wherein each of the plurality of first conductive lines has a first side and a second side opposite to the first side. The memory device further includes a plurality of second conductive lines crossing over the plurality of first conductive lines, wherein widths of the plurality of second conductive lines are increased as the plurality of second conductive lines become far away from the first side.

In accordance with alternative embodiments of the present disclosure, a memory device includes a multi-layer stack. The multi-layer stack includes a plurality of first conductive lines and a plurality of dielectric layers stacked alternately. The multi-layer stack includes a memory region and a first staircase region and a second staircase region disposed on opposite sides of the memory region. The memory device further includes a plurality of second conductive lines over the plurality of first conductive lines in the memory region, wherein widths of the plurality of second conductive lines are increased as the plurality of second conductive lines become close to a middle of the memory region.

In accordance with yet alternative embodiments of the present disclosure, a memory device includes a staircase structure. The staircase structure includes a plurality of first conductive lines and a plurality of dielectric layers stacked alternately, and the staircase structure includes a memory region and a first staircase region aside the memory region. The memory device further includes a plurality of second conductive lines over the plurality of first conductive lines in the memory region, wherein widths of the plurality of second conductive lines are increased as the plurality of second conductive lines become far away from the first staircase region.

In accordance with yet alternative embodiments of the present disclosure, a memory device includes a multi-layer stack including a plurality of first conductive lines and a plurality of second conductive lines. The first conductive lines are stacked on one another. The second conductive lines cross over the plurality of first conductive lines, wherein widths of the plurality of second conductive lines are increased as the plurality of second conductive lines become close to a middle portion of the multi-layer stack.

In accordance with yet alternative embodiments of the present disclosure, a memory device includes a multi-layer stack including a plurality of first conductive lines and a plurality of second conductive lines. The first conductive lines are stacked on one another, and the multi-layer stack includes a memory region. The second conductive lines are disposed over the plurality of first conductive lines in the memory region, wherein widths of the plurality of second conductive lines are increased as the plurality of second conductive lines become close to a middle portion of the memory region.

In accordance with yet alternative embodiments of the present disclosure, a memory device includes a staircase structure including a plurality of first conductive lines and a plurality of second conductive lines. The first conductive lines are stacked on one another, and the staircase structure includes a first region and a second region. The second conductive lines are disposed over the plurality of first conductive lines and disposed in the first region, wherein widths of the plurality of second conductive lines are increased as the plurality of second conductive lines become close to the second region.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.