Patent ID: 12245491

DETAILED DESCRIPTION

Reference will now be made in more detail to aspects of some embodiments, which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, aspects of some embodiments are merely described below, by referring to the figures, to explain aspects of the present description. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression “at least one of a, b or c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

Various modifications may be applied to the present embodiments, and particular embodiments will be illustrated in the drawings and described in the detailed description section. The effect and features of the present embodiments, and a method to achieve the same, will be clearer referring to the detailed descriptions below with the drawings. However, the present embodiments may be implemented in various forms, not by being limited to the embodiments presented below.

Hereinafter, aspects of some embodiments will be described in more detail with reference to the accompanying drawings, and in the description with reference to the drawings, the same or corresponding constituents are indicated by the same reference numerals and redundant descriptions thereof are omitted.

In the specification, it will be understood that although the terms “first,” “second,” etc. may be used herein to describe various components, these components should not be limited by these terms.

In the specification, the expression of singularity in the specification includes the expression of plurality unless clearly specified otherwise in context.

In the specification, when a part may “include” or “have” a certain constituent element, unless specified otherwise, it may not be construed to exclude another constituent element but may be construed to further include other constituent elements.

In the specification, it will be understood that when a layer, region, or component is referred to as being “formed on” another layer, region, or component, it can be directly or indirectly formed on the other layer, region, or component. That is, for example, intervening layers, regions, or components may be present.

In the specification, it will be understood that when a layer, region, or component is referred to as being “connected to” another layer, region, or component, it can be directly connected to the other layer, region, or component or indirectly connected to the other layer, region, or component via intervening layers, regions, or components. For example, in the specification, when a layer, region, or component is referred to as being electrically connected to another layer, region, or component, it can be directly electrically connected to the other layer, region, or component or indirectly electrically connected to the other layer, region, or component via intervening layers, regions, or components.

In the specification, the expression such as “A and/or B” may include A, B, or A and B. Furthermore, the expression such as “at least one of A and B” may include A, B, or A and B.

In the specification, the x-axis, the y-axis and the z-axis are not limited to three axes of the rectangular coordinate system, and may be interpreted in a broader sense. For example, the x-axis, the y-axis, and the z-axis may be perpendicular to one another, or may represent different directions that are not perpendicular to one another.

In the specification, when a certain embodiment may be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order.

Sizes of components in the drawings may be exaggerated for convenience of explanation. For example, because sizes and thicknesses of components in the drawings are arbitrarily illustrated for convenience of explanation, the following embodiments are not limited thereto.

FIG.1is a schematic exploded perspective view of a portion of a display apparatus according to some embodiments.

The display apparatus according to some embodiments may include a window10, a display panel30, a cover panel50, and a printed circuit board40. As illustrated inFIG.1, the display apparatus may further include various constituent elements as necessary or desired. For example, the display apparatus may further include a light-transmissive adhesive layer20located between the window10and the display panel30and bonding or mechanically connecting the window10to the display panel30.

The window10may be formed of a light-transmissive material, and the window10may include, for example, glass or polymer resin. The window10may include polymer resin, for example, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

The window10may include a base11and an edge portion13. The base11forms the overall appearance of the window10, and exhibits or enables light transmittance. The edge portion13may have a shape protruding from a first virtual plane where the base11is located. InFIG.1, when a direction of a front surface of the display panel30where images are displayed is a z direction, the base11is arranged on the first virtual plane approximately parallel to an x-y plane, and the edge portion13has a shape protruding from the edge of the base11in a direction (−z direction) perpendicular to the x-y plane. The base11and the edge portion13may be integrally formed (e.g., formed as one integrated body) of the same material, but embodiments according to the present disclosure are not limited thereto. For example, the edge portion13, as a separate component from the base11, may be coupled to the edge of the base11. In this case, the edge portion13may be non-transmissive unlike the base11that is light-transmissive.

The base11is arranged on a first virtual plane, but the first plane may be a curved surface. For example, when an electronic apparatus is a smart watch, the base11in the window10has an overall flat shape, but a surface of the base11in a direction (+z direction) opposite to the display panel30may include a curved portion.

The display panel30may be located on the base11of the window10. The display panel30may include, on a substrate, a circuit including an electronic element such as a thin film transistor and the like, and a display element electrically connected to the circuit. The display element may be an organic light-emitting device (or OLED). Embodiments according to the present disclosure are not limited thereto, and the display panel30may include various display elements such as a liquid crystal device, not the organic light-emitting device (or OLED).

The display panel30may include a substrate100, and the substrate100may be flexible or bendable. For example, the substrate100may include a body portion101and a bending portion103. The body portion101of the substrate100may have a non-rectangular shape having curved sides or polygonal sides. The non-rectangular shape may include, for example, a circle, an oval, a polygon partially having a curved side, or a polygon except a rectangle.

The bending portion103of the substrate100may extend from the body portion101in one direction (−y direction), and may be bent with respect to a bending axis BAX to contact the printed circuit board40described below. Accordingly, when the substrate100that is bent is viewed from a direction (z direction) perpendicular to the substrate100, the size of a non-display area perceived (or perceivable) by users may be relatively reduced.

The cover panel50may be arranged in a rear surface direction (−z direction) of the display panel30, and may serve to shield the display panel30from external electrical signals, electromagnetic waves, external light, and the like.

According to some embodiments, the cover panel50may have a stacked or layered structure including any one or more of a light absorption layer, a buffer member, and a heat dissipation member. The light absorption layer may be provided as a polymer film layer including a light absorption material such as black pigment, dye, and the like. The buffer member may prevent or reduce damage to the display panel30by absorbing external shock. According to some embodiments, the buffer member may be provided as a single layer or a stack structure including an elastic material. The heat dissipation member may diffuse heat generated from the display panel30, the printed circuit board40, or the like. The heat dissipation member may include a metal plate, a graphite sheet, or the like having relatively excellent heat conductivity.

The printed circuit board40may be electrically connected to the display panel30, as described above. For example, a bending portion33of the display panel may be electrically attached on a surface of the printed circuit board40in the direction (z direction) toward the window10. In this case, wirings of the printed circuit board40may be electrically connected to pads placed on a surface of the display panel30in a direction toward the printed circuit board40through anisotropic conductive film, and the like.

The display panel30, the cover panel50, and the like may be placed on the window10. For example, the display panel30and the cover panel50may be located in a space defined by the base11and the edge portion13of the window10. The printed circuit board40electrically connected to the display panel30may be placed on the cover panel50.

FIG.2Ais a schematic plan view of the display panel30of the display apparatus illustrated inFIG.1, andFIG.2Bis a schematic plan view of a display panel according to some embodiments.

Referring toFIGS.2A and2B, the display panel30may include the substrate100. The substrate100may include a display area DA and a peripheral area PA outside (e.g., in a periphery or outside a footprint of) the display area DA. The display area DA may be arranged in the body portion101of the substrate100. According to some embodiments, as illustrated inFIG.2A, the body portion101and the display area DA of the substrate100may have a circular (or relatively circular) shape. According to some embodiments, as illustrated inFIG.2B, the body portion101and the display area DA of the substrate100may have a polygonal shape having curved sides, for example, a rectangle shape with rounded corners. Embodiments according to the present disclosure are not limited thereto.

The peripheral area PA may be arranged in the body portion101and the bending portion103of the substrate100to surround the display area DA. In the specification, for convenience of explanation, with reference toFIGS.2A and2B, the peripheral area PA corresponding to a curved side in the upper right side, the peripheral area PA corresponding to a curved side in the lower right side, the peripheral area PA corresponding to a curved side in the lower left side, and the peripheral area PA corresponding to a curved side in the upper left side may be referred to as a first corner area CR1, a second corner area CR2, a third corner area CR3, and a fourth corner area CR4, respectively.

According to some embodiments, as shown inFIG.2A, when the body portion101of the substrate100has a circular shape, the peripheral area PA may include the first corner area CR1, the second corner area CR2, the third corner area CR3, and the fourth corner area CR4. According to some embodiments, as shown inFIG.2B, when the body portion101of the substrate100has a rectangular shape with rounded corners, the peripheral area PA may include a straight area arranged between neighboring ones of the first corner area CR1, the second corner area CR2, the third corner area CR3, and the fourth corner area CR4. Embodiments according to the present disclosure are not limited thereto, and the body portion101of the substrate100may have various shapes with curved sides or polygonal sides.

The substrate100may include glass, metal, or polymer resin. For example, the substrate100may include polymer resin, such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate100may have various modifications, for example, the substrate100may have a multilayer structure including two layers each including the polymer resin as above and a barrier layer located between the two layers and including an inorganic material, for example, a silicon oxide (SiOx), a silicon nitride (SiNx), a silicon oxynitride (SiON), and the like.

AlthoughFIGS.2A and2Billustrate that, for convenience, the substrate100has a structure that is flat on an x-y plane, embodiments according to the present disclosure are not limited thereto. As described above, a portion of the substrate100, for example, the bending portion103, may be bent. For the substrate100that is bent, when viewed from the direction (z direction) perpendicular to the display area DA, the size of the peripheral area PA perceived by a user may be relatively reduced.

A plurality of pixels P may be arranged in the display area DA. In the specification, each of the pixels P may mean a sub-pixel, and include a display element such as an organic light-emitting diode. The pixels P may emit, for example, red, green, blue, or white light. The pixels P may be arranged in a first direction (x direction) and a second direction (y direction) intersecting the first direction (x direction).

Each pixel P may be electrically connected to outer circuits arranged in the peripheral area PA. The peripheral area PA is an area where the pixels P are not arranged, and a first driving portion110A, a second driving portion1106, a data driving circuit130, a power supply line150, and the like may be arranged in the peripheral area PA.

The first driving portion110A and the second driving portion1106may be spaced apart from each other. The first driving portion110A and the second driving portion1106may transmit the same signal or different signals to each pixel P. For example, the first driving portion110A and the second driving portion1106may provide scan signals to the pixels P through a scan line SL. At least one of the first driving portion110A or the second driving portion1106may provide an emission control signal to the pixels P through an emission control line EL.

The data driving circuit130may receive electrical signals from a printed circuit board40(seeFIG.1) and the like, and provide data signals to the pixels P through a data line DL. The data driving circuit130may be directly formed on the substrate100, may be an integrated circuit (IC) chip bonded to the substrate100via an electric adhesive, or may be attached to the substrate100in the form of a chip-on-film (COF), or may be connected to the substrate100using any other suitable bonding mechanism.

The power supply line150may be configured to provide power received from the printed circuit board40and the like to the pixels P through power voltage lines PL.

The data lines DL arranged in the display area DA may be electrically connected to the data driving circuit130arranged in the peripheral area PA, the scan lines SL and the emission control lines EL arranged in the display area DA may be electrically connected to the first driving portion110A or the second driving portion1108arranged in the peripheral area PA, and the power voltage lines PL arranged in the display area DA may be electrically connected to the power supply line150arranged in the peripheral area PA. Furthermore, the printed circuit board40may be electrically connected to the pads placed in an edge of the bending portion33of the display panel30, and the first driving portion110A, the second driving portion1108, the data driving circuit130, and the power supply line150may be electrically connected to the pads.

An alignment mark AM may be arranged in the first corner area CR1to the fourth corner area CR4. The alignment mark AM may be located outside the first driving portion110A and the second driving portion1108.

According to some embodiments, a first alignment mark AM1may be located in the first corner area CR1, and a second alignment mark AM2may be located in the fourth corner area CR4, to thus achieve symmetry with respect to a first virtual center line CL1passing through the center of the display area DA of the substrate100and extending in the second direction (y direction). Furthermore, a third alignment mark AM3may be located in the second corner area CR2to achieve symmetry with respect to a second virtual center line CL2passing through the center of the display area DA of the substrate100and extending in the first direction (x direction). Likewise, a fourth alignment mark AM4may be located in the third corner area CR3to achieve symmetry with the third alignment mark AM3with respect to the first virtual center line CL1. In some embodiments, the first alignment mark AM1, one or more of the second alignment mark AM2, the third alignment mark AM3, and the fourth alignment mark AM4may be omitted.

An electrode power line may be arranged in the peripheral area PA of the substrate100, and electrically connected to a counter electrode in the display area DA to provide electrode power to the counter electrode.

FIG.3is a schematic view showing the configuration of the display panel30according to some embodiments.

Referring toFIG.3, the display panel30may include the first driving portion110A, the second driving portion1106, and the data driving circuit130outside the display area DA. The first driving portion110A and the second driving portion1106may transmit the same signal or different signals to each pixel P.

According to some embodiments, any one of the first driving portion110A and the second driving portion1106may include one or more of an emission control circuit111, a first scan driving circuit113, and a second scan driving circuit115. The other one of the first driving portion110A and the second driving portion1106may include the rest of the emission control circuit111, the first scan driving circuit113, and the second scan driving circuit115. For example, as illustrated inFIG.3, the first driving portion110A may include the emission control circuit111and the first scan driving circuit113, and the second driving portion1106may include the second scan driving circuit115. According to some embodiments, the emission control circuit111may be arranged in both of the first driving portion110A and the second driving portion1106.

The emission control circuit111may be connected to the emission control lines EL, and may generate emission control signals in response to a control signal of a control unit and sequentially provide the generated emission control signals through the emission control lines EL. The emission control line EL may be a gate control signal to turn on or off a plurality of transistors of each pixel P. The emission control circuit111may include a plurality of stages (or shift registers) to sequentially generate and output emission control signals.

The first scan driving circuit113and the second scan driving circuit115may be connected to the scan lines SL, and may generate scan signals in response to the control signal of the control unit and sequentially provide the generated scan signals through the scan lines SL. The scan signal may be a gate control signal in which an on voltage to turn on the transistors of each pixel P and an off voltage to turn off the transistors are repeated. According to some embodiments, the on voltage may be a high-level voltage (or first gate voltage) or a low-level voltage (or second gate voltage). An on-voltage period and an off-voltage period of the scan signal may be determined depending on the function of a transistor in each pixel P that receives the scan signal. The first scan driving circuit113and the second scan driving circuit115may each include a plurality of stages (or shift registers) that sequentially generate and output scan signals.

According to some embodiments, the scan line SL may include first scan lines SL1, second scan lines SL2, third scan lines SL3, and fourth scan lines SL4, in which the first scan lines SL1and the second scan lines SL2may extend from the first driving portion110A to the pixels P arranged in the display area DA, and the third scan lines SL3and the fourth scan lines SL4may extend from the second driving portion1106to the pixels P arranged in the display area DA.

According to some embodiments, the scan line SL may include the first scan lines SL1, the second scan lines SL2, the third scan lines SL3, and the fourth scan lines SL4, in which the first scan lines SL1may extend from the first driving portion110A to the pixels P arranged in the display area DA, and the second scan lines SL2, the third scan lines SL3, and the fourth scan lines SL4may extend from the second driving portion1106to the pixels P arranged in the display area DA.

The first scan driving circuit113and the second scan driving circuit115may each output respective scan signals through the respective scan lines SL. The emission control circuit111may output emission control signals EM (seeFIG.4) through the emission control lines EL. The data driving circuit130may output data signals DATA (seeFIG.4) through the data lines DL.

As described above, the data driving circuit130may be arranged in various methods. For example, the data driving circuit130may be arranged directly above the bending portion103of the substrate100or in a separate flexible printed circuit board that may be electrically connected to the pads.

The scan line SL and the emission control line EL may extend in the first direction (x direction). The scan line SL and the emission control line EL may be shared by the pixels P neighboring in the first direction (x direction). The data line DL may extend in the second direction (y direction). The data line DL may be shared by the pixels P neighboring in the second direction (y direction).

The emission control circuit111, the first scan driving circuit113, and the second scan driving circuit115may be appropriately arranged in the peripheral area PA along the edge of the display area DA, that is, the periphery of the display area DA. At least one of the emission control circuit111, the first scan driving circuit113, or the second scan driving circuit115may be arranged in the peripheral area PA (seeFIG.2A) corresponding to the curved side or polygonal side, such as the first corner area CR1(seeFIG.2A), the second corner area CR2(seeFIG.2A), the third corner area CR3(seeFIG.2A), or the fourth corner area CR4(seeFIG.2A).

FIG.4is an equivalent circuit diagram of the pixel P in the display panel30according to some embodiments. Although the circuit diagram illustrated inFIG.4shows various components, embodiments according to the present disclosure may include additional components or fewer components without departing from the spirit and scope of embodiments according to the present disclosure.

Referring toFIG.4, each pixel P may include a plurality of first to seventh transistors T1, T2, T3, T4, T5, T6, and T7, a first capacitor Cst, a second capacitor Cbt, an organic light-emitting diode OLED as a display element, and the signal lines SL1, SL2, SL3, SL4, EL, and DL, an initialization voltage line VIL, and a power voltage line PL, which are connected thereto. According to some embodiments, at least any one of the signal lines SL1, SL2, SL3, SL4, EL, and DL, and the initialization voltage line VIL and/or the power voltage line PL may be shared by neighboring pixels. The first to seventh transistors T1to T7may be implemented by thin film transistors. InFIG.4, it is illustrated in, among the first to seventh transistors T1to T7, the third transistor T3and the fourth transistor T4are implemented by an n-channel MOSFET (NMOS), and the other is implemented by a p-channel MOSFET (PMOS).

The signal lines may include the data lines DL, the first scan lines SL1, the second scan lines SL2, the third scan lines SL3, the fourth scan lines SL4, and the emission control lines EL. According to some embodiments, the second scan line SL2may be connected to the first scan line SL1, and a first scan signal GP1may be a second scan signal GP2.

The power voltage line PL is configured to transmit a first driving voltage ELVDD to a first transistor T1, and the initialization voltage line VIL may be configured to transmit an initialization voltage Vint for initializing the first transistor T1and the organic light-emitting diode OLED to each pixel P.

The first scan line SL1, the second scan line SL2, the third scan line SL3, the fourth scan line SL4, the emission control line EL, and the initialization voltage line VIL may extend in the first direction (x direction) (seeFIG.3) and may be arranged in each row apart from each other. The data line DL and the power voltage line PL may extend in the second direction (y direction) (seeFIG.3) and may be arranged in each column apart from each other.

The first transistor T1may be connected to the power voltage line PL via a fifth transistor T5, and may be electrically connected to the organic light-emitting diode OLED via a sixth transistor T6. The first transistor T1may serve as a driving transistor, and according to the switching operation of a second transistor T2, receive a data signal DATA and provide a driving current IOLED to the organic light-emitting diode OLED.

The second transistor T2may be connected to the first scan line SL1and the data line DL, and connected to the power voltage line PL via the fifth transistor T5. The second transistor T2may be turned on in response to the first scan signal GP1received through the first scan line SL1, and may perform a switching operation of transmitting the data signal DATA received through the data line DL to a node N.

The third transistor T3may be connected to the fourth scan line SL4, and connected to the organic light-emitting diode OLED via the sixth transistor T6. The third transistor T3may be turned on in response to a fourth scan signal GN2received through the fourth scan line SL4and may make the first transistor T1diode-connected.

The fourth transistor T4may be connected to the third scan line SL3and the initialization voltage line VIL, and turned on in response to a third scan signal GN1received through the third scan line SL3to transmit the initialization voltage Vint from the initialization voltage line VIL to a gate electrode of the first transistor T1, thereby initializing the voltage of the gate electrode of the first transistor T1.

The fifth transistor T5and the sixth transistor T6may be connected to the emission control line EL, and simultaneously turned on in response to an emission control signal EM received through the emission control line EL to form a current path so that the driving current IOLED may flow in a direction from the power voltage line PL to the organic light-emitting diode OLED,

A seventh transistor T7may be connected to the second scan line SL2and the initialization voltage line VIL, and turned on in response to the second scan signal GP2received through the second scan line SL2to transmit the initialization voltage Vint from the initialization voltage line VIL to the organic light-emitting diode OLED, thereby initializing the organic light-emitting diode OLED. The seventh transistor T7may be omitted.

The first capacitor Cst may include a first electrode CE1and a second electrode CE2. The first electrode CE1may be connected to the gate electrode of the first transistor T1, and the second electrode CE2may be connected to the power voltage line PL. The first capacitor Cst may store and maintain a voltage corresponding to a voltage difference between opposite ends of the power voltage line PL and the gate electrode of the first transistor T1, thereby maintaining the voltage applied to the gate electrode of the first transistor T1.

The second capacitor Cbt may include a third electrode CE3and a fourth electrode CE4. The third electrode CE3may be connected to the first scan line SL1and a gate electrode of the second transistor T2. The fourth electrode CE4may be connected to the gate electrode of the first transistor T1and the first electrode CE1of the first capacitor Cst. The second capacitor Cbt, as a boosting capacitor, when the first scan signal GP1of the first scan line SL1is a voltage to turn off the second transistor T2, may decrease a voltage (black voltage) to display black by increasing the voltage of the node N.

The organic light-emitting diode OLED may include a pixel electrode and a counter electrode, and the counter electrode may receive a second power voltage ELVSS. The organic light-emitting diode OLED may display an image by receiving the driving current IOLED from the first transistor T1and emitting light.

A specific operation of each pixel P according to some embodiments is described as follows.

During an initialization period, when the third scan signal GN1is provided through the third scan line SL3, the fourth transistor T4may be turned on in response to the third scan signal GN1, and the first transistor T1may be initialized by the initialization voltage Vint received through the initialization voltage line VIL.

During a data programming period, when the first scan signal GP1, the second scan signal GP2, and the fourth scan signal GN2are provided through the first scan line SL1, the second scan line SL2, and the fourth scan line SL4, respectively, the second transistor T2, the seventh transistor T7, and the third transistor T3may be turned on in response to the first scan signal GP1, the second scan signal GP2, and the fourth scan signal GN2. In this state, the first transistor T1may be diode-connected by the third transistor T3that is turned on, and biased in a forward direction.

Then, a voltage in which a threshold voltage Vth of the first transistor T1is compensated from the data signal DATA supplied from the data line DL, is applied to the gate electrode of the first transistor T1. The organic light-emitting diode OLED may be initialized by the initialization voltage Vint received through the initialization voltage line VIL by the seventh transistor T7that is turned on. The first driving voltage ELVDD and compensation voltage may be applied to opposite ends of the first capacitor Cst, and electric charges corresponding to voltage difference between opposite ends may be stored in the first capacitor Cst.

During an emission period, the fifth transistor T5and the sixth transistor T6may be turned on in response to the emission control signal EM provided through the emission control line EL. The driving current IOLED according to the voltage difference between the voltage of the gate electrode of the first transistor T1and the first driving voltage ELVDD may be generated, and the driving current IOLED may be provided to the organic light-emitting diode OLED through the sixth transistor T6.

According to some embodiments, at least one of the transistors T1to T7may include a semiconductor layer including an oxide, and the other transistors may include a semiconductor layer including silicon. For example, the first transistor having a direct influence on the brightness of a display apparatus may include a semiconductor layer including polycrystalline silicon exhibiting high reliability, and thus, a display apparatus with a relatively high resolution may be implemented.

As an oxide semiconductor has high carrier mobility and a low leakage current, a voltage drop is not much in spite of a long driving time. In other words, as a color change of an image according to a voltage drop is not much even in low frequency driving, low frequency driving is possible. As such, as an oxide semiconductor may have a relatively low leakage current, at least one of the third transistor T3or the fourth transistor T4connected to the gate electrode of the first transistor T1may be employed as an oxide semiconductor, a leakage current that may flow to the gate electrode of the first transistor T1may be prevented or reduced and simultaneously power consumption may be relatively reduced.

FIG.5is a schematic plan view of a driving portion in the display panel30according to some embodiments, andFIG.6is a schematic block diagram of a driving portion in the display panel30according to some embodiments.

Referring toFIGS.5and6, at least portions of the first driving portion110A and the second driving portion1106may be arranged in the first corner area CR1, the second corner area CR2, the third corner area CR3, and the fourth corner area CR4corresponding to curved sides or polygonal sides.

The first driving portion110A and the second driving portion1106may each include a plurality of normal stages NSTG and a plurality of dummy stages DSTG. Each of the normal stages NSTG may correspond to a pixel row provided in the display area DA. The number of the normal stages NSTG arranged in the first driving portion110A and the second driving portion1106may be variously changed according to the number of pixel rows.

The normal stages NSTG may output a plurality of output signals in response to a start signal. For example, a first normal stage NSTG1may output a first output signal SC1, a second normal stage NSTG2may output a second output signal SC2, and the n-th normal stage may output the n-th output signal.

Each of the normal stages NSTG may include an input terminal IN, a first clock terminal CT1, a second clock terminal CT2, a first power terminal VT1, a second power terminal VT2, and an output terminal OUT.

The input terminal IN may receive, as a start signal, an external start signal STV or a carry signal output from the preceding normal stage NSTG. According to some embodiments, the external start signal STV may be applied to the input terminal IN of the first normal stage NSTG1, and from the second normal stage NSTG2, a carry signal (previous carry signal) output by the preceding normal stage NSTG may be applied to the input terminal IN. The previous carry signal may be a carry signal output by the preceding stage that is adjacent thereto. For example, the first normal stage NSTG1may start driving in response to the external start signal STV, and the carry signal output from the first normal stage NSTG1may be input to the input terminal IN of the second normal stage NSTG2.

A first clock signal CLK1or a second clock signal CLK2may be applied to the first clock terminal CT1and the second clock terminal CT2. The first clock signal CLK1and the second clock signal CLK2may be alternately applied to the normal stages NSTG. For example, the first clock signal CLK1may be applied to the first clock terminal CT1of odd-numbered normal stages, and the second clock signal CLK2may be applied to the second clock terminal CT2of the odd-numbered normal stages. The second clock signal CLK2may be applied to the first clock terminal CT1of even-numbered normal stages, and the second clock signal CLK2may be applied to the second clock terminal CT2of the even-numbered normal stages.

The first power terminal VT1may receive a first gate voltage VGH of a high voltage, and the second power terminal VT2may receive a second gate voltage VGL of a low voltage. The first gate voltage VGH and the second gate voltage VGL, as global signals, may be provided from a control unit, a power supply unit, and/or like.

The output terminal OUT may output output signals such as the first output signal SC1, the second output signal SC2, and the like. The first output signal SC1and the second output signal SC2may be scan signals. Each output signal may be provided to a pixel P (seeFIG.3) through a corresponding output line, for example, the scan line SL (seeFIG.3).

The dummy stages DSTG may each include the input terminal IN, the first clock terminal CT1, the second clock terminal CT2, the first power terminal VT1, the second power terminal VT2, and the output terminal OUT.

The dummy stages DSTG are arranged to improve the uniformity of a pattern density of the first driving portion110A and the second driving portion1106, and do not output output signals. In other words, the output terminal OUT of the dummy stages DSTG may be floating. In order to reduce the occurrence of defects due to static electricity because electric charges are introduced into the dummy stages DSTG, the input terminal IN, the first clock terminal CT1, and the second clock terminal CT2of each of the dummy stages DSTG may receive the first gate voltage VGH. Furthermore, the first power terminal VT1of each of the dummy stages DSTG may receive the first gate voltage VGH, and the second power terminal VT2may receive the second gate voltage VGL.

AlthoughFIG.6illustrates that the first normal stage NSTG1, a first dummy stage DSTG1, the second normal stage NSTG2, and a second dummy stage DSTG2are sequentially arranged, the number of the dummy stages DSTG arranged between the normal stages NSTG neighboring each other may vary according to the arrangement position. For example, one or more dummy stages DSTG may be arranged between the normal stages NSTG neighboring each other, or the normal stages NSTG may be arranged adjacent to each other without the dummy stage DSTG therebetween.

According to some embodiments, the first driving portion110A may be arranged in the third corner area CR3and the fourth corner area CR4, and arranged along a first virtual line VL1corresponding to a curved side (or a polygonal side). In other words, the normal stages NSTG and the dummy stages DSTG in the first driving portion110A may be arranged along the first virtual line VL1. At this time, the number of dummy stages arranged for each unit length of the first virtual line VL1may be determined based on an angle between the first virtual line VL1and the first direction (x direction).

Likewise, the second driving portion1106may be arranged in the first corner area CR1and the second corner area CR2, along a second virtual line VL2corresponding to a curved side (or a polygonal side). In other words, the normal stages NSTG and the dummy stages DSTG in the second driving portion1106may be arranged along the second virtual line VL2. At this time, the number of dummy stages arranged for each unit length of the second virtual line VL2may be determined based on an angle formed between the second virtual line VL2and the first direction (x direction).

When a portion of the second virtual line VL2is divided into three of a first arc a1, a second arc a2, and a third arc a3with the same arc length, a first length SP1that is the length of the first arc a1in the second direction (y direction), a second length SP2that is the length of the second arc a2in the second direction (y direction), and a third length SP3that is the length of the third arc a3in the second direction (y direction) may be different from one another.

The tangent line of the first arc a1may form a first angle θ1with the first direction (x direction), the tangent line of the second arc a2may form a second angle θ2with the first direction (x direction), and the tangent line of the third arc a3may form a third angle θ3with the first direction (x direction). When the first angle θ1is greater than the second angle θ2, and the second angle θ2is greater than the third angle θ3, the first length SP1may be greater than the second length SP2, and the second length SP2may be greater than the third length SP3.

As the stages including the normal stages NSTG and the dummy stages DSTG are arranged along the second virtual line VL2, the same number of stages may be arranged in each of the first arc a1, the second arc a2, and the third arc a3. In contrast, the number of pixel rows arranged in the display area DA corresponding to the first length SP1may be greater than the number of pixel rows arranged in the display area DA corresponding to the second length SP2, and the number of pixel rows arranged in the display area DA corresponding to the second length SP2may be greater than the number of pixel rows arranged in the display area DA corresponding to the third length SP3. Accordingly, the number of the normal stages NSTG arranged along the first arc a1may be greater than the number of the normal stages NSTG arranged along the second arc a2, and the number of the normal stages NSTG arranged along the second arc a2may be greater than the number of the normal stages NSTG arranged along the third arc a3. In order to the uniformity of a pattern density of the second driving portion1108, the number of the dummy stages DSTG arranged along the first arc a1may be less than the number of the dummy stages DSTG arranged along the second arc a2, and the number of the dummy stages DSTG arranged along the second arc a2may be less than the number of the dummy stages DSTG arranged along the third arc a3. The normal stages NSTG and the dummy stages DSTG of the first driving portion110A may be arranged in the same rule.

In a comparative example, when a first driving portion and a second driving portion include only normal stages for outputting output signals, it may be difficult to arrange normal stages with a uniform pattern density of the first driving portion and the second driving portion. Accordingly, due to a pattern density difference between stages, the timing of output signals output from the first driving portion and the second driving portion may be advanced or delayed. In contrast, in the display panel30according to some embodiments, the dummy stages DSTG are arranged between the normal stages NSTG to have a uniform pattern density of each of the first driving portion110A and the second driving portion1108, and thus, the first driving portion110A and the second driving portion1108may output output signals at an accurate timing.

FIG.7is a schematic plan view of the display panel30and the cover panel50according to some embodiments,FIG.8is a schematic enlarged plan view of a portion of the display panel30according to a comparative example, andFIG.9is a schematic enlarged plan view of a portion of the display panel30according to some embodiments.

FIG.7illustrates the display panel30and the cover panel50when viewed from a direction (−z direction) perpendicular to the display panel30, showing that the cover panel50is bonded to the rear surface of the display panel30.FIGS.8and9are schematic enlarged plan views of a portion of a display panel according to a comparative example and a portion of the display panel30according to some embodiments, when viewed from a direction (+z direction) perpendicular to the display panel30(e.g., from a direction perpendicular or normal with respect to a display surface of the display panel30, or in a plan view), to explain the arrangement of a second alignment notch AH2and the first driving portion110A in the fourth corner area CR4.

Referring toFIGS.7to9, the cover panel50may have a shape corresponding to the display panel30. As described above, the cover panel50may be implemented by a film or a plate-shaped member including any one or more of a light absorption layer, a buffer member, and a heat dissipation member.

The cover panel50may have the same size (or area) as or a different size (or area) from the display panel30. According to some embodiments, the size (or area) of the cover panel50may be less than the size (or area) of the display panel30. Accordingly, the edge of the cover panel50may be spaced apart a certain distance inwards from the edge of the display panel30. According to some embodiments, the size (or area) of the cover panel50may be the same as or greater than the size (or area) of the display panel30. The edge of the cover panel50may be located outside the first driving portion110A and the second driving portion1106. Accordingly, when viewed from the rear surface of the display panel30, the cover panel50may cover an area corresponding to the first driving portion110A and the second driving portion1106.

The cover panel50may have a first alignment notch AH1corresponding to the first alignment mark AM1, the second alignment notch AH2corresponding to the second alignment mark AM2, a third alignment notch AH3corresponding to the third alignment mark AM3, and a fourth alignment notch AH4corresponding to the fourth alignment mark AM4. In other words, the first alignment notch AH1may be formed in the edge of the cover panel50corresponding to the first corner area CR1, the second alignment notch AH2may be formed in the edge of the cover panel50corresponding to the fourth corner area CR4, the third alignment notch AH3may be formed in the edge of the cover panel50corresponding to the second corner area CR2, and the fourth alignment notch AH4may be formed in the edge of the cover panel50corresponding to the third corner area CR3. In some embodiments, some of the first alignment notch AH1, the second alignment notch AH2, the third alignment notch AH3, and the fourth alignment notch AH4may be omitted.

The first alignment mark AM1, the second alignment mark AM2, the third alignment mark AM3, and the fourth alignment mark AM4may be arranged on the front surface of the display panel30, and may include an opaque material. For example, the first alignment mark AM1, the second alignment mark AM2, the third alignment mark AM3, and the fourth alignment mark AM4may include a metal material.

The first alignment notch AH1, the second alignment notch AH2, the third alignment notch AH3, and the fourth alignment notch AH4of the cover panel50may be used as identification marks for alignment, during the assembly of the display panel and the cover panel50, with the first alignment mark AM1, the second alignment mark AM2, the third alignment mark AM3, and the fourth alignment mark AM4.

As the display area DA expands so that the size of the peripheral area PA decreases, the first alignment notch AH1, the second alignment notch AH2, the third alignment notch AH3, and the fourth alignment notch AH4may overlap the first driving portion110A and the second driving portion1108in a thickness direction (z-axis direction). In other words, portions of the first driving portion110A and the second driving portion1108may be exposed from the cover panel50by the first alignment notch AH1, the second alignment notch AH2, the third alignment notch AH3, and the fourth alignment notch AH4.

As the first alignment mark AM1, the second alignment mark AM2, the third alignment mark AM3, and the fourth alignment mark AM4are substantially the same as or similar to each other, and the first alignment notch AH1, the second alignment notch AH2, the third alignment notch AH3, and the fourth alignment notch AH4are substantially the same as or similar to each other, a case in which the second alignment mark AM2and the second alignment notch AH2arranged in the fourth corner area CR4is mainly described below.

Areas in which the substrate100of the display panel30overlaps the first alignment notch AH1, the second alignment notch AH2, the third alignment notch AH3, and the fourth alignment notch AH4of the cover panel50in the thickness direction (z-axis direction) may be defined as notch areas AHA. Accordingly, the notch areas AHA may be arranged to respectively overlap the first alignment mark AM1, the second alignment mark AM2, the third alignment mark AM3, and the fourth alignment mark AM4.

The notch area AHA may overlap portions of the first driving portion110A and the second driving portion1106. Referring toFIGS.8and9, the first driving portion110A may include the normal stages NSTG and the dummy stages DSTG. The normal stage NSTG may include the first normal stage NSTG1to a sixth normal stage NSTG6, and the dummy stage DSTG may include the first dummy stage DSTG1to a third dummy stage DSTG3. The disclosure is not limited thereto, and the numbers of the normal stages NSTG and the dummy stages DSTG may be changed variously.

As a comparative example, as illustrated inFIG.8, when the notch area AHA overlaps portions of the normal stages NSTG, a pixel row connected to a normal stage that overlaps the notch area AHA may have different light-emitting characteristics from a pixel row connected to a normal stage that does not overlap the notch area AHA. For example, inFIG.8, a third normal stage NSTG3, a fourth normal stage NSTG4, and a fifth normal stage NSTG5of the first driving portion110A may overlap the notch area AHA. A second pixel group PG2connected to the third normal stage NSTG3and a third pixel group PG3connected to the fourth normal stage NSTG4may have different light-emitting characteristics from a first pixel group PG1connected to the second normal stage NSTG2. Accordingly, in the display apparatus according to a comparative example, a user may perceive a horizontal stain across the display area DA in the first direction (x direction).

In contrast, according to one or more embodiments, the dummy stages DSTG may be arranged in the notch area AHA. For example, the first dummy stage DSTG1, the second dummy stage DSTG2, and the third dummy stage DSTG3may be arranged between the third normal stage NSTG3and the fourth normal stage NSTG4, and the notch area AHA may be arranged to overlap the first dummy stage DSTG1, the second dummy stage DSTG2, and the third dummy stage DSTG3. As the output terminals OUT (seeFIG.6) of the dummy stages DSTG may be floating, the dummy stages DSTG may not be electrically connected to each pixel P. As the normal stages NSTG electrically connected to the pixels P do not overlap the notch area AHA, the display apparatus according to one or more embodiments may display a high-quality image having no horizontal stain.

FIG.10is a schematic cross-sectional view of the display panel30illustrated inFIG.9taken along the line A-A′.

Referring toFIG.10, the display panel30of the display apparatus may include the substrate100including the display area DA and the peripheral area PA. A first buffer layer201and a second buffer layer202may be arranged in the display area DA of the substrate100. The first buffer layer201and the second buffer layer202may serve to increase smoothness of the upper surface of the substrate100, and may prevent or reduce infiltration of impurities from the substrate100and the like into a semiconductor layer Act. The first buffer layer201and the second buffer layer202may be provided as an oxide film such as SiOx, and/or a nitride film such as SiNx or a SiON.

According to some embodiments, a light blocking layer BM may be arranged between the first buffer layer201and the second buffer layer202. The light blocking layer BM may include a metal material. The metal material may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

A pixel circuit PC may be located on the second buffer layer202. The pixel circuit PC may include the semiconductor layer Act, a gate electrode GE, a source electrode S, a drain electrode D, and a capacitor electrode CE. The semiconductor layer Act may include a silicon semiconductor or an oxide semiconductor. The semiconductor layer Act may include a source region and a drain region, which are doped with impurities, are conductive, and are apart from each other, and a channel region arranged therebetween. The source region and the drain region may be electrically connected to the source electrode S and the drain electrode D, respectively.

The gate electrode GE may be located on the semiconductor layer Act, and a first gate insulating layer203may be located between the semiconductor layer Act and the gate electrode GE.

The gate electrode GE may be arranged to overlap the channel region of the semiconductor layer Act, and may include at least one of Mo, Cu, Ti, or Al.

A second gate insulating layer205may be located on the gate electrode GE, the capacitor electrode CE may be located on the second gate insulating layer205, and a first planarization layer207may be located on the capacitor electrode CE. The source electrode S and the drain electrode D may be located on an interlayer insulating layer206. The source electrode S may be connected to the source region of the semiconductor layer Act through a contact hole penetrating the interlayer insulating layer206, the second gate insulating layer205, and the first gate insulating layer203, and the drain electrode D may be connected to the drain region of the semiconductor layer Act through a contact hole penetrating the interlayer insulating layer206, the second gate insulating layer205, and the first gate insulating layer203.

The first gate insulating layer203, the second gate insulating layer205, and the interlayer insulating layer206may include an inorganic material including an oxide or a nitride. For example, the first gate insulating layer203, the second gate insulating layer205, and the interlayer insulating layer206may include at least one of SiO2, SiNx, SiON, an aluminum oxide (Al2O3), a titanium oxide (TiO2), a tantalum oxide (Ta2O5), a hafnium oxide (HfO2), or a zinc oxide (ZnO2).

The first planarization layer207may be arranged to cover the source electrode S and the drain electrode D, and a second planarization layer208may be located on the first planarization layer207. According to some embodiments, the second planarization layer208may be omitted. According to some embodiments, a third planarization layer may be located on the second planarization layer208. The first planarization layer207and/or the second planarization layer208may include an organic material, such as acryl, benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), or the like. Alternatively, the first planarization layer207and/or the second planarization layer208may include an inorganic material.

The organic light-emitting diode OLED, as a display element, may be located on the second planarization layer208. The organic light-emitting diode OLED may include a pixel electrode211, a counter electrode215, and an intermediate layer213arranged between the pixel electrode211and the counter electrode215and including a light-emitting layer.

The pixel electrode211may be connected to a connection electrode CM through a contact hole penetrating the second planarization layer208, and the connection electrode CM may be connected to the drain electrode D or the source electrode S through a contact penetrating the first planarization layer207.

A pixel define layer209may be located on the second planarization layer208. The pixel define layer209may have an opening corresponding to each pixel, that is, an opening to expose a portion of the pixel electrode211, thereby performing a function to define a pixel. Furthermore, the pixel define layer209may prevent or reduce generation of arc and the like in the edge of the pixel electrode211, by increasing a distance between an edge of the pixel electrode211and the counter electrode215. The pixel define layer209may include an organic insulating material, such as BCB, polyimide, HMDSO, or the like. According to some embodiments, the pixel define layer209may include a light blocking material, and may be provided in black. The light blocking material may include carbon black, carbon nanotube, resin or paste including black dye, a metal particle, for example, Ni, Al, Mo, and an alloy thereof, a metal oxide particle, for example, a chromium oxide, or a metal nitride particle, for example, a chromium nitride, and the like.

The intermediate layer213may include a light-emitting layer overlapping the pixel electrode211. The light-emitting layer may include a polymer organic material or a low molecular weight organic material emitting light of a certain color. The light-emitting layer may be patterned to correspond to the pixel electrode211through a deposition process using a mask. The intermediate layer213may further include a functional layer located below and/or above the light-emitting layer.

The counter electrode215may include a conductive material having a relatively work function. For example, the counter electrode215may include a (semi-) transparent layer including silver (Ag), magnesium (Mg), Al, Ni, Cr, lithium (Li), calcium (Ca), or an alloy thereof, and the like. Alternatively, a counter electrode230may further include a layer such as ITO, IZO, ZnO or In2O3on the (semi-)transparent layer including the materials described above. The counter electrode215, unlike the pixel electrode211, may be integrally provided on the entire surface of the display area DA.

An encapsulation layer300may be located on the organic light-emitting diode OLED. According to some embodiments, the encapsulation layer300may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the encapsulation layer300may include first and second inorganic encapsulation layers310and330and an organic encapsulation layer320arranged therebetween.

The first and second inorganic encapsulation layers310and330may each include one or more inorganic insulating materials. The inorganic insulating material may include Al2O3, TiO2, Ta2O5, HfO2, ZnO, SiOx, SiNx, or/and SiON. The first and second inorganic encapsulation layers310and330may be formed through a chemical vapor deposition method.

The organic encapsulation layer320may further include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resin, for example, polymethyl methacrylate, polyacrylic acid, and the like, or a combination thereof.

The peripheral area PA may be located outside the display area DA, and the peripheral area PA may include the fourth corner area CR4having a curved side or a polygonal side. A driving circuit DC and a power wire VSSL may be arranged in the fourth corner area CR4. The driving circuit DC may be the dummy stage DSTG in the first driving portion110A.

The cover panel50arranged on the rear surface of the substrate100in the direction (−z direction) may have an alignment notch AH, and the alignment notch AH may overlap at least a portion of the driving circuit DC in the thickness direction (z-axis direction). Accordingly, a lower portion of the driving circuit DC overlapping the alignment notch AH may be exposed from the cover panel50.

A dam portion DAM for controlling the flow of a monomer may be arranged outside the power wire VSSL. The dam portion DAM may include one or more organic material layers. For example, the dam portion DAM may include a first organic material layer207′, a second organic material layer208′, and a third organic material layer209′. According to some embodiments, the first organic material layer207′ may include the same material as the first planarization layer207, the second organic material layer208′ may include the same material as the second planarization layer208, and the third organic material layer209′ may include the same material as the pixel define layer209. In some embodiments, one or more of the first organic material layer207′, the second organic material layer208′, and the third organic material layer209′ may be omitted, or one or more other organic material layers may be added.

According to some embodiments, the alignment mark AM may be located outside the dam portion DAM. AlthoughFIG.10illustrates that the alignment mark AM is located on the first gate insulating layer203, the disclosure is not limited thereto. For example, the alignment mark AM may be formed through the same patterning process as any one of metal layers forming the pixel circuit PC and the driving circuit DC. Alternatively, the alignment mark AM, according to some embodiments, may be formed through the same patterning process as an input electrode layer of an input detection layer.

According to some embodiments, the alignment mark AM may be a single layer or a multilayer, and located on different layers.

An outer dam ODAM and an outer hole OH may be located outside the dam portion DAM. The outer dam ODAM may include at least one organic material layer. The outer hole OH may be arranged to overlap the outer dam ODAM. The outer hole OH may be formed by removing a portion of an inorganic material layer on the substrate100. The outer hole OH and the outer dam ODAM may prevent or reduce propagation of cracks from the edge of the substrate100.

The display apparatus according to one or more embodiments may include the normal stages NSTG (seeFIG.9) and the dummy stages DSTG (seeFIG.9) arranged between the normal stages NSTG, to improve the uniformity of a pattern density of the driving portion. At this time, by arranging the dummy stages DSTG in the driving circuit DC that overlaps the alignment notch AH of the cover panel50of the display apparatus, a high-quality image with no horizontal stain may be displayed.

According to one or more embodiments described as above, a display panel capable of displaying relatively high-quality images and a display apparatus including the same may be implemented. The scope of embodiments according to the present disclosure is not limited by the effect.

It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims, and their equivalents.