Patent ID: 12197352

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG.1illustrates an electronic device10according to an embodiment of the present disclosure. Referring toFIG.1, the electronic device10may include a coherency host100, a first coherency device200, and a second coherency device300.

In an embodiment of the present disclosure, the coherency host100may be implemented with a central processing unit (CPU) (or a central processing unit core) or an application processor (AP) (or an application processor core). Each of the first coherency device200and the second coherency device300may be implemented with a graphic processing unit (or graphic processing core), a neural processor (or neural processor core), a neuromorphic processor (or neuromorphic processor core), a digital signal processor (or digital signal processor core), an image signal processor (or image signal processor core), etc.

In an embodiment of the present disclosure, the coherency host100may be implemented as a host device that controls the first coherency device200and the second coherency device300. Each of the first coherency device200and the second coherency device300may be implemented with an accelerator that supports an operation of the coherency host100.

The coherency host100, the first coherency device200, and the second coherency device300may be implemented with one semiconductor device or may be implemented with two or more independent semiconductor devices. The coherency host100, the first coherency device200, and the second coherency device300may be components of the electronic device10; however, each of the coherency host100, the first coherency device200, and the second coherency device300may be referred to as an “electronic device”.

The coherency host100, the first coherency device200, and the second coherency device300may support the cache coherency. Each of the coherency host100, the first coherency device200, and the second coherency device300may include a memory that is used as a cache memory. In the case where the cache coherency is supported, when data of a cache memory included in one of the coherency host100, the first coherency device200, and the second coherency device300are updated, the same update may be performed on the remaining cache memories (under the condition that the same data are stored in the remaining cache memories).

The coherency host100may include a coherency host processor110, a host coherency memory120, and a host memory130. The coherency host processor110may support the cache coherency by using the host coherency memory120and may use the host memory130as a local memory.

The coherency host processor110may include a host processor core111, a coherency controller112, and a memory controller113. The host processor core111may execute an operating system of the electronic device10. The host processor core111may allocate or request a task to or from the first coherency device200and/or the second coherency device300.

An embodiment in which the electronic device10includes the coherency host100, the first coherency device200, and the second coherency device300is described, but the electronic device10may further include additional other components. For example, the electronic device10may include a third coherency device. The host processor core111may control the additional other components.

The coherency controller112may perform an operation associated with the cache coherency. The coherency controller112may support two or more modes associated with the cache coherency. The two or more modes may include a mode in which the cache coherency is partially supported, a mode in which the cache coherency is supported (e.g., fully supported), and a mode in which the cache coherency is not supported.

In the mode in which the cache coherency is partially supported, the coherency controller112may partially control accesses to memories associated with the coherency from among all memories associated with the cache coherency, for example, from among memories of the coherency host100, the first coherency device200, and/or the second coherency device300.

In the mode in which the cache coherency is supported, the coherency controller112may control accesses to the memories associated with the coherency from among all the memories associated with the cache coherency, for example, from among the memories of the coherency host100, the first coherency device200, and/or the second coherency device300.

The coherency controller112may control a switch between the two or more modes. The coherency controller112may perform a mode control in a 1:1 manner with each of the first coherency device200and the second coherency device300.

The coherency controller112may access the host coherency memory120through the memory controller113in response to a request of the host processor core111. When the cache coherency with the first coherency device200and/or the second coherency device300is supported and data of the host coherency memory120are modified, the coherency controller112may request the first coherency device200and/or the second coherency device300to perform the same modification on the same data stored in a cache coherency-related memory of the first coherency device200and/or the second coherency device300(immediately or after a specific time passes). For example, the coherency controller112may request the first coherency device200and/or the second coherency device300to perform the same modification on the same data stored in a device coherency memory220of the first coherency device200and/or a device coherency memory320of the second coherency device300.

When the cache coherency with the first coherency device200and/or the second coherency device300is supported and specific data of a cache coherency-related memory of the first coherency device200are modified, the coherency controller112may request the memory controller113or the second coherency device300to perform the same modification on the same data stored in a cache coherency-related memory of the host coherency memory120and/or the second coherency device300(immediately or after a specific time passes). For example, the same modification may be performed on the same data stored in the device coherency memory320of the second coherency device300.

Likewise, when the cache coherency with the first coherency device200and/or the second coherency device300is supported and specific data of a cache coherency-related memory of the second coherency device300are modified, the coherency controller112may request the memory controller113or the first coherency device200to perform the same modification on the same data stored in a cache coherency-related memory of the host coherency memory120and/or the first coherency device200(immediately or after a specific time passes). For example, the same modification may be performed on the same data stored in the device coherency memory220of the first coherency device200.

The memory controller113may access the host coherency memory120and the host memory130. For example, the memory controller113may access the host coherency memory120depending on a request of the coherency controller112and may access the host memory130depending on a request of the host processor core111.

In an embodiment of the present disclosure, the memory controller113may include a first controller for the host coherency memory120and a second controller for the host memory130.

The first coherency device200may include a coherency device processor210, the device coherency memory220, and a device memory230. The coherency device processor210may support the cache coherency by using the device coherency memory220and may use the device memory230as a local memory.

The coherency device processor210may include a device processor core211, a coherency engine212, and a memory controller213. The device processor core211may execute firmware of the first coherency device200or codes loaded by the coherency host100. The device processor core211may perform a task allocated or requested by the coherency host100by using the device coherency memory220or the device memory230.

For example, the device processor core211may process data (e.g., shared data) stored in the device coherency memory220. The device processor core211may use the device coherency memory220and/or the device memory230as a working memory for data processing. The device processor core211may update at least a portion of data of the device coherency memory220based on a processing result.

The coherency engine212may perform an operation associated with the cache coherency. The coherency engine212may support two or more modes associated with the cache coherency. The two or more modes may include a mode in which the cache coherency is partially supported, a mode in which the cache coherency is supported (e.g., fully supported), and a mode in which the cache coherency is not supported.

In the mode in which the cache coherency is partially supported, the coherency engine212may partially perform an access to a cache coherency-related memory, for example, the device coherency memory220under control of the coherency controller112. In the mode in which the cache coherency is supported, the coherency engine212may perform an access to the device coherency memory220under control of the coherency controller112. The coherency engine212may perform a switch between the two or more modes under control of the coherency controller112.

The coherency engine212may access the device coherency memory220through the memory controller213in response to a request of the coherency controller112and/or the device processor core211. When the cache coherency with the coherency host100is supported and data of the device coherency memory220are modified by the device processor core211, the coherency engine212may provide modification information (e.g., an address or a tag) and/or modified data to the coherency controller112(e.g., depending on a request of the coherency controller112or automatically in response to the modification being made).

The memory controller213may access the device coherency memory220and the device memory230. For example, the memory controller213may access the device coherency memory220depending on a request of the coherency engine212and may access the device memory230depending on a request of the device processor core211. In an embodiment of the present disclosure, the memory controller213may include a first controller for the device coherency memory220and a second controller for the device memory230.

The second coherency device300may include a coherency device processor310, the device coherency memory320, and a device memory330. The coherency device processor310may include a device processor core311, a coherency engine312, and a memory controller313.

Configurations, features, and functions of the coherency device processor310, the device coherency memory320, the device memory330, the device processor core311, the coherency engine312, and the memory controller313may respectively correspond to the configurations, features, and functions of the coherency device processor210, the device coherency memory220, the device memory230, the device processor core211, the coherency engine212, and the memory controller213. For example, the memory controller313may access the device coherency memory320depending on a request of the coherency engine312and may access the device memory330depending on a request of the device processor core311. Thus, additional description will be omitted to avoid redundancy.

In the embodiment ofFIG.1, the cache coherency-related memories may include the host coherency memory120, the device coherency memory220, and the device coherency memory320. In an embodiment of the present disclosure, the communication for cache coherency between the host coherency memory120, the device coherency memory220, and the device coherency memory320may be based on the Compute Express Link™ (CXL™).

FIG.2illustrates an example of an operating method of the electronic device10according to an embodiment of the present disclosure. For brevity of description, an example of an operation between the coherency host100and the first coherency device200will be described with reference toFIGS.1and2. However, the same operation may be performed between the coherency host100and the second coherency device300.

Referring toFIGS.1and2, in operation S110, the electronic device10may determine a bias mode. For example, the coherency host100may determine the bias mode. As another example, the coherency host100may determine the bias mode depending on a request of the first coherency device200. As another example, the first coherency device200may determine the bias mode and may request the determined mode from the coherency host100. As yet another example, the coherency host100may determine the bias mode depending on a request of the second coherency device300.

When a first bias mode is determined, operation S121to operation S123may be performed. For example, the first bias mode may be a delayed host bias mode. In operation S121, the coherency host100and the first coherency device200may enter the delayed host bias mode.

The delayed host bias mode may partially support the cache coherency. While the first coherency device200operates in the delayed host bias mode together with the coherency host100, the coherency host100may ignore the cache coherency with the first coherency device200and may not intervene in the access of the first coherency device200to the device coherency memory220. The first coherency device200may access the device coherency memory220without the intervention of the coherency controller112. In other words, the first coherency device200may access the device coherency memory220independent of the coherency controller112.

The first coherency device200may access the device coherency memory220without the intervention or control of the coherency controller112. Accordingly, a speed at which the first coherency device200accesses the device coherency memory220may be improved compared to the case when the device coherency memory220is accessed through the coherency controller112.

The first coherency device200may ignore the cache coherency until a wanted point in time, for example, until a task allocated or requested by the coherency host100is completely processed. Accordingly, the atomicity and isolation may be secured in the operation of the first coherency device200.

While the delayed host bias mode is maintained, in operation S122, the first coherency device200may access the device coherency memory220quickly (e.g., without the control of the coherency controller112) and safely (e.g., with the atomicity and isolation maintained).

When the delayed host bias mode ends (e.g., when entering a host bias mode), the coherency host100and the first coherency device200may recover the cache coherency. For example, in operation S123, the first coherency device200may provide the coherency host100with information (e.g., an address or a tag) about modified data of data of the device coherency memory220and/or the modified data. The coherency host100may recover the cache coherency based on the received information and/or the received data.

When a second bias mode is determined in operation S110, operation S131and operation S132may be performed. For example, the second bias mode may be a host bias mode of the CXL™. In operation S131, the coherency host100and the first coherency device200may enter the host bias mode.

While the host bias mode is maintained, in operation S132, the first coherency device200may access the device coherency memory220under the control of the coherency controller112. Because the cache coherency is maintained in the host bias mode, an additional operation (e.g., the above coherency recovery) associated with the cache coherency is not required when the host bias mode ends.

When a third bias mode is determined in operation S110, operation S141to operation S143may be performed. For example, the third bias mode may be a device bias mode of the CXL™. In operation S141, the coherency host100and the first coherency device200may enter the device bias mode.

While the device bias mode is maintained, in operation S142, the coherency host100may not require the first coherency device200to maintain the cache coherency. The coherency host100may release a storage space (e.g., a cache memory space) in the host coherency memory120allocated for the first coherency device200. The first coherency device200may access the device coherency memory220without the control of the coherency controller112.

A process in which the coherency host100and the first coherency device200terminate the device bias mode may be selectively performed. For example, when the recovery of the cache coherency is required, operation S143may be performed. In operation S143, the coherency host100may allocate a storage space (e.g., a cache memory space) for the first coherency device200to the host coherency memory120. The coherency host100may perform a cache fill operation in which data of the device coherency memory220of the first coherency device200are filled in the allocated storage space. As another example, when the recovery of the cache coherency is not required, operation S143may not be performed.

FIG.3illustrates an example of a process in which the coherency host100and the first coherency device200enter the first bias mode from the second bias mode. For example, a process of switching a bias mode may be called a “bias flip”.

Referring toFIGS.1and3, in operation S210, the coherency host100may request the first coherency device200to perform the bias flip from the second bias mode to the first bias mode, or the first coherency device200may request the coherency host100to perform the bias flip from the second bias mode to the first bias mode.

In operation S220, the coherency host100may detect first modified data. For example, the coherency host100may detect, as the first modified data, data that are modified (or updated) only in the host coherency memory120after being stored in common in the host coherency memory120and the device coherency memory220of the first coherency device200.

For example, the host coherency memory120may be used as a cache memory including a plurality of cache lines, and the detection of the first modified data may be performed units of at least one cache line. In operation S230, the coherency host100may send the first modified data corresponding to at least one cache line to the first coherency device200.

The first modified data may be sent together with information (e.g., an address or a tag) of the first modified data. The first coherency device200may update the device coherency memory220by using the information of the first modified data and the first modified data. For example, the first coherency device200may update (or replace) data of the device coherency memory220, which correspond to the information about the first modified data, with the first modified data.

When additional data necessary for the first coherency device200(e.g., data necessary for processing) are present in addition to the first modified data, the coherency host100may send the additional data and information (e.g., an address or a tag) of the additional data, as a portion of the first modified data and the information of the first modified data or together with the first modified data and the information of the first modified data. The first coherency device200may store the additional data and the information of the additional data in the device coherency memory220.

The transmitted data may be checked in operation S240to operation S260. For example, in operation S240, the first coherency device200may again send, to the coherency host100, the first modified data and/or the information of the first modified data received from the coherency host100.

In operation S250, the coherency host100may compare the transmitted data and/or the information of the transmitted data provided to the first coherency device200with the received data and/or the information of the received data provided from the first coherency device200. When a comparison result indicates “matched”, in operation S260, the coherency host100may send an acknowledgement message to the first coherency device200. When the comparison result indicates “mismatched”, operation S230to operation S260may again be performed.

After the acknowledgement message is sent from the coherency host100to the first coherency device200in operation S260, in operation S270, the coherency host100and the first coherency device200may enter the first bias mode from the second bias mode. After the coherency host100and the first coherency device200enter the first bias mode, in operation S280, the coherency host100may maintain a storage space (e.g., a cache memory space) in the host coherency memory120allocated for the first coherency device200without release.

In an embodiment of the present disclosure, operation S240to operation S260marked by a dotted line may be selectively performed. In the case where operation S240to operation S260are omitted, after the first modified data are sent from the coherency host100to the first coherency device200, the coherency host100and the first coherency device200may enter the first bias mode from the second bias mode.

FIG.4illustrates an example of a process in which the coherency host100and the first coherency device200enter the second bias mode from the first bias mode. For example, a process of switching a bias mode may be called a “bias flip”.

Referring toFIGS.1and4, in operation S310, the coherency host100may request the first coherency device200to perform the bias flip from the first bias mode to the second bias mode, or the first coherency device200may request the coherency host100to perform the bias flip from the first bias mode to the second bias mode. In other words, either the coherency host100or the first coherency device200may initiate the bias flip request.

In operation S320, the first coherency device200may send information (e.g., an address or a tag) of modified data to the coherency host100. For example, the first coherency device200may send information of data (e.g., second modified data), which are modified (or updated) after entering the first bias mode, from among data stored in the device coherency memory220to the coherency host100.

In operation S330, based on the received information, the coherency host100may invalidate data, which correspond to the second modified data modified (or updated) by the first coherency device200during the first bias mode, from among the data stored in the host coherency memory120. The invalidation of data may be performed in units of at least one cache line. The invalidated cache line may be released from allocation. In other words, the data of the invalidated cache line may be deleted.

In an embodiment of the present disclosure, after the second modified data are provided from the first coherency device200to the coherency host100, as in the above description given with reference to operation S240to operation S260ofFIG.3, the process of checking whether the second modified data are correctly transmitted may be selectively performed.

In operation S340, the coherency host100and the first coherency device200may enter the second bias mode from the first bias mode. Afterwards, the second modified data may be requested by the coherency host100. For example, the host processor core111of the coherency host100or the second coherency device300may require the second modified data.

Because data corresponding to the second modified data are absent from the host coherency memory120(due to the invalidation), a cache miss may occur. In operation S350, the coherency host100may request the second modified data from the first coherency device200. In response to the request, in operation S360, the first coherency device200may provide the second modified data and/or the information of the second modified data to the coherency host100.

In operation S370, the coherency host100may update the data of the host coherency memory120by storing the second modified data and/or the information of the second modified data in the host coherency memory120.

As described above, when the recovery of the cache coherency is required, the coherency host100and the first coherency device200may be configured to recover the cache coherency based on invalidation of data corresponding to the second modified data and a cache miss.

FIG.5illustrates another example of a process in which the coherency host100and the first coherency device200enter the second bias mode from the first bias mode. For example, a process of switching a bias mode may be called a “bias flip”.

Referring toFIGS.1and5, in operation S410, the coherency host100may request the first coherency device200to perform the bias flip from the first bias mode to the second bias mode, or the first coherency device200may request the coherency host100to perform the bias flip from the first bias mode to the second bias mode.

In operation S420, the first coherency device200may send the second modified data and/or the information (e.g., an address or a tag) of the second modified data to the coherency host100. For example, the first coherency device200may send, to the coherency host100, the second modified data, which are modified (or updated) after entering the first bias mode, from among data stored in the device coherency memory220and information of the second modified data.

In operation S430, the coherency host100may update the data of the host coherency memory120by storing the second modified data and/or the information of the second modified data in the host coherency memory120. In other words, the coherency host100may update a cache line in the host coherency memory120. In an embodiment of the present disclosure, after the second modified data and/or the information of the second modified data are provided from the first coherency device200to the coherency host100, as in the above description given with reference to operation S240to operation S260ofFIG.3, the process of checking whether the second modified data are correctly transmitted may be selectively performed.

In operation S440, the coherency host100and the first coherency device200may enter the second bias mode from the first bias mode. Compared to the operating method ofFIG.4, the first coherency device200sends the second modified data and/or the information of the second modified data to the coherency host100before entering the second bias mode. The coherency host100updates the data of the host coherency memory120by using the second modified data. In other words, after the cache coherency is completely recovered, the coherency host100and the first coherency device200may enter the second bias mode.

FIG.6illustrates an example corresponding to the case where the electronic device10is in the second bias mode before entering the first bias mode. Referring toFIG.6, the device coherency memory220of the first coherency device200may store input data for processing of the device processor core211. The device coherency memory320of the second coherency device300may store input data for processing of the device processor core311.

The cache coherency may be maintained between data of the device coherency memory220of the first coherency device200, data of the device coherency memory320of the second coherency device300, and the host coherency memory120of the coherency host100. In other words, the input data of the device processor core211and the input data of the device processor core311may be prepared based on the cache coherency. Like that shown inFIG.1, inFIG.6, the coherency engine212may communicate directly with the coherency controller112and the coherency engine312may communicate directly with the coherency controller112.

FIG.7illustrates an example corresponding to the case where the electronic device10operates in the first bias mode. Referring toFIG.7, the cache coherency may be blocked between data of the device coherency memory220of the first coherency device200, data of the device coherency memory320of the second coherency device300, and the host coherency memory120of the coherency host100. For example, unlike that shown inFIG.6, the coherency engine212may not be linked with the coherency controller112and the coherency engine312may not be linked with the coherency controller112.

The device coherency memory220of the first coherency device200may store input data for processing of the device processor core211. The device processor core241may perform processing based on the data stored in the device coherency memory220without the control of the coherency controller112through the coherency engine212. Accordingly, the processing of the device processor core211may be performed quickly.

The device processor core211may store a processing result in the device coherency memory220. Because the cache coherency (between the first coherency device200and the coherency host100) is blocked, the processing operation of the device processor core211is not notified to the coherency host100. Because the processing of the device processor core211is not exposed and the atomicity and isolation are secured, the device processor core211may safely access the device coherency memory220.

The device coherency memory320of the second coherency device300may store input data for processing of the device processor core311. The device processor core311may perform processing based on the data stored in the device coherency memory320without the control of the coherency controller112through the coherency engine312. Accordingly, the processing of the device processor core311may be performed quickly.

The device processor core311may store a processing result in the device coherency memory320. Because the cache coherency (between the second coherency device300and the coherency host100) is blocked, the processing operation of the device processor core311is not notified to the coherency host100. Because the processing of the device processor core311is not exposed and the atomicity and isolation are secured, the device processor core311may safely access the device coherency memory320.

FIG.8illustrates an example corresponding to the case where the electronic device10completes processing in the first bias mode and enters the second bias mode. Referring toFIG.8, the device coherency memory220of the first coherency device200may store output data corresponding to a processing result of the device processor core211. The device coherency memory320of the second coherency device300may store output data corresponding to processing result of the device processor core311.

As the electronic device10enters the second bias mode, the cache coherency of the coherency host100, the first coherency device200, and the second coherency device300may be recovered. Data modified by the processing of the first coherency device200may be shared by the coherency host100and/or the second coherency device300. Data modified by the processing of the second coherency device300may be shared by the coherency host100and/or the first coherency device200.

As described above, the electronic device10according to an embodiment of the present disclosure blocks the cache coherency while the first coherency device200and/or the second coherency device300performs an operation. When the operation of the first coherency device200and/or the second coherency device300is completed, the cache coherency is recovered. In other words, the cache coherency may be delayed until the operation of the first coherency device200and/or the second coherency device300is completed.

While the cache coherency is delayed, the first coherency device200and/or the second coherency device300may access the device coherency memory220and/or the device coherency memory320in a fast, safe manner and may perform an operation. When the cache coherency is recovered, only data modified by the first coherency device200and/or the second coherency device300may be shared, and thus, a tune and resource necessary to recover the cache coherency may decrease.

In particular, in the case of a database server, most processing is performed on previously stored data, and a result of the processing causes the update of the previously stored data. The methods according to an embodiment of the present disclosure, which support fast and safe operations by synchronizing input data and output data through the cache coherency before and after the operations and delaying the cache coherency during the operations, may show optimum performance in an environment such as the database server.

FIG.9is a diagram of a system1000to which a storage device is applied, according to an embodiment of the present disclosure. The system1000ofFIG.9may be a mobile system, such as a portable communication terminal (e.g., a mobile phone), a smartphone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of things (IOT) device. However, the system1000ofFIG.9is not necessarily limited to the mobile system and may be a PC, a laptop computer, a server, a media player, or an automotive device (e.g., a navigation device).

Referring toFIG.9, the system1000may include a main processor1100, memories (e.g.,1200aand1200b), and storage devices (e.g.,1300aand1300b). In addition, the system1000may include at least one of an image capturing device1410, a user input device1420, a sensor1430, a communication device1440, a display1450, a speaker1460, a power supplying device1470, and a connecting interface1480.

The main processor1100may control all operations of the system1000, more specifically, operations of other components included in the system1000. The main processor1100may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

The main processor1100may include at least one CPU core1110and further include a controller1120configured to control the memories1200aand1200band/or the storage devices1300aand1300b. In some embodiments of the present disclosure, the main processor1100may further include an accelerator1130, which is a dedicated circuit for a high-speed data operation, such as an artificial intelligence (AI) data operation. The accelerator1130may include a graphics processing unit (GPU), a neural processing unit (NPU) and/or a data processing unit (DPU) and be implemented as a chip that is physically separate from the other components of the main processor1100.

The memories1200aand1200bmay be used as main memory devices of the system1000. Although each of the memories1200aand1200bmay include a volatile memory, such as static random access memory (SRAM) and/or dynamic RAM (DRAM), each of the memories1200aand1200bmay include non-volatile memory, such as a flash memory, phase-change RAM (PRAM) and/or resistive RAM (RRAM). The memories1200aand1200bmay be implemented in the same package as the main processor1100.

The storage devices1300aand1300bmay serve as non-volatile storage devices configured to store data regardless of whether power is supplied thereto, and have a larger storage capacity than the memories1200aand1200b. The storage devices1300aand1300bmay respectively include storage controllers (STRG CTRL)1310aand1310band Non-Volatile Memorys (NVMs)1320aand1320bconfigured to store data under the control of the storage controllers1310aand1310b. Although the NVMs1320aand1320bmay include flash memories having a two-dimensional (2D) structure or a three-dimensional (3D) V-NAND structure, the NVMs1320aand1320bmay include other types of NVMs, such as PRAM and/or RRAM.

The storage devices1300aand1300bmay be physically separated from the main processor1100and included in the system1000or implemented in the same package as the main processor1100. In addition, the storage devices1300aand1300bmay have types of solid-state devices (SSDs) or memory cards and be removably combined with other components of the system100through an interface, such as the connecting interface1480that will be described below. The storage devices1300aand1300bmay be devices to which a standard protocol, such as a universal flash storage (UFS), an embedded multi-media card (eMMC), or a non-volatile memory express (NVMe), is applied, without being limited thereto.

The image capturing device1410may capture still images or moving images. The image capturing device1410may include a camera, a camcorder, and/or a webcam.

The user input device1420may receive various types of data input by a user of the system1000and include a touch pad, a keypad, a keyboard, a mouse, and/or a microphone.

The sensor1430may detect various types of physical quantities, which may be obtained from the outside of the system1000, and convert the detected physical quantities into electric signals. The sensor1430may include a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor, and/or a gyroscope sensor.

The communication device1440may transmit and receive signals between other devices outside the system1000according to various communication protocols. The communication device1440may include an antenna, a transceiver, and/or a modem.

The display1450and the speaker1460may serve as output devices configured to respectively output visual information and auditory information to the user of the system1000.

The power supplying device1470may convert power supplied from a battery embedded in the system1000and/or an external power source, and supply the converted power to each of components of the system1000.

The connecting interface1480may provide connection between the system1000and an external device, which is connected to the system1000and capable of transmitting and receiving data to and from the system1000. The connecting interface1480may be implemented by using various interface schemes, such as advanced technology attachment (ATA), serial ATA (SATA), external SATA (e-SATA), small computer small interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI), PCI express (PCIe), NVMe, IEEE 1394, a universal serial bus (USB) interface, a secure digital (SD) card interface, a multi-media card (MMC) interface, an eMMC interface, a UFS interface, an embedded UFS (eUFS) interface, and a compact flash (CF) card interface.

In an embodiment of the present disclosure, the coherency host100described with reference toFIGS.1to8may be implemented to correspond to the CPU core1110. The first coherency device200and/or the second coherency device300described with reference toFIGS.1to8may be implemented to correspond to the accelerator1130. As another example, the coherency host100described with reference toFIGS.1to8may be implemented to correspond to the main processor1100. The first coherency device200and/or the second coherency device300described with reference toFIGS.1to8may be implemented with a separate sub-processor (e.g., an accelerator processor) assisting the main processor1100.

In the above embodiments, components according to the present disclosure are described by using the terms “first”, “second”, “third”, etc. However, the terms “first”, “second”, “third”, etc. may be used to distinguish components from each other and do not limit the present disclosure. For example, the terms “first”, “second”, “third”, etc. do not involve an order or a numerical meaning of any form.

In the above embodiments, components according to embodiments of the present disclosure are referenced by using blocks. The blocks may be implemented with various hardware devices, such as an integrated circuit (IC), an application specific IC (ASIC), a field programmable gate array (FPGA), and a complex programmable logic device (CPLD), firmware driven in hardware devices, software such as an application, or a combination of a hardware device and software. In addition, the blocks may include circuits implemented with semiconductor elements in an integrated circuit, or circuits enrolled as an intellectual property (IP).

According to the present disclosure, an electronic device may block the cache coherency while performing an independent operation. Accordingly, the independent operation may be performed quickly and safely. In addition, as data modified before and after the independent operation are shared, the cache coherency is secured before and after the independent operation.

While the present disclosure has been described with reference to embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the present disclosure as set forth in the following claims.