Patent ID: 12237371

DETAILED DESCRIPTION

The following disclosure is drafted using terms and examples of a forksheet device, though the inventive concept is applicable to other types of semiconductor devices, such as any form of horizontal channel NSH- or NWFET.

In particular, a forksheet device makes use of a top sacrificial layer that is thicker than each lower sacrificial layer in order to define a height of an insulating wall. Such an insulating wall may be used in other semiconductor devices and the thickness of the top sacrificial layer may introduce similar challenges, as discussed in the introductory parts of the description.

FIG.1ais cross-sectional view of a semiconductor structure comprising a device layer stack20on a substrate10with a sacrificial gate structure30extending across the device layer stack20in a direction perpendicular to the cross-sectional view, i.e. in the Y direction.

Directions X and Y indicate a first and a second horizontal direction, respectively (along the substrate10). Direction Z indicates a vertical or bottom-up direction (normal to the substrate10). The cross section is taken along the XZ-plane.

The substrate10may be of a conventional type, such as a substrate suitable for complementary metal-oxide semiconductor (CMOS) processing and comprising (as a top-most layer) a semiconductor layer of a composition allowing forming of the device layer stack thereon. The substrate10may for instance be a semiconductor bulk substrate such as a Si substrate, a germanium (Ge) substrate or a silicon-germanium (SiGe) substrate. Other examples include a semiconductor-on-insulator (SOI) type of substrate such as a Si-on-insulator substrate, a Ge-on-insulator substrate or a SiGe-on-insulator substrate.

The device layer stack20comprises a top sacrificial layer26on top of the topmost channel layer24on top of an alternating sequence of two lower sacrificial layers22and a channel layer24. The alternating sequence of a lower sacrificial layer22and a channel layer24may in other embodiments continue with any number of layers.

The lower sacrificial layers may have a thickness of 5-15 nm, such as 7 nm. The lower sacrificial layers may have a uniform thickness.

The top sacrificial layer is thicker than each lower sacrificial layer. The top sacrificial layer may have a thickness of 15-50 nm, such as 25 nm.

The channel layers have a thickness of 5-15 nm, such as 10 nm. The channel layers may have a uniform thickness.

The device layer stack20may as shown be surrounded by shallow-trench insulation (STI) regions13.

Each sacrificial gate structure30extends across the device layer stack20in a direction perpendicular to the cross-sectional view. Each sacrificial gate structure30may as shown comprise a hard mask material as a gate cap36that was previously used for patterning the sacrificial gate structure30.

A sacrificial gate structure30may act as a place holder for and define a shape for a (functional) gate stack of the completed device. A functional gate stack may be formed in a Replacement Metal Gate (RMG) process, by replacing a sacrificial gate structure30with a stack of gate dielectric, and one or more gate metals.FIG.1aillustrates three sacrificial gate structures30formed across the layer stack20. However, more generally any number of sacrificial gate structures30may be provided, and one or more thereof may be replaced with gate stacks.

The regions between the sacrificial gate structures30, i.e. the portions of the device layer stack20that are not covered by a sacrificial gate structure30, defines where the source and drain regions are to be formed. As such, a finalized transistor device may have a source and drain region on either side of a gate stack. The finalized transistor device further comprises channels running below the gate in the horizontal direction ofFIG.1abetween the source and drain regions.

The layered structure of the device layer stack20allows forming of a finalized transistor structure having a respective channel region comprising a number of vertically distributed channel layer portions, the number corresponding to the number of channel layers in the device layer stack20.

Additionally, a portion of the top sacrificial layer26below the middle sacrificial gate structure30may also be replaced with the gate stack, as will be further described below.

FIG.1bis a different cross-sectional view of the semiconductor structure ofFIG.1a. In this view, it is apparent that the semiconductor structure comprises a first and second device layer stack20,21on a first and second device region11,12of the substrate10, respectively. The cross-section ofFIG.1bis perpendicular to the cross-section ofFIG.1a(i.e. along the YZ-plane) and taken where a sacrificial gate structure is not present.

The first and second device region11,12and the first and second device layer stacks20,21are separated by an insulating wall46. The insulating wall46is formed in a trench of the substrate10. The insulating wall46may extend along the entire height of the first and second device layer stacks20,21, with a top surface at least substantially flush with the top surface of the top sacrificial layer26. The trench may for example be formed with a width in a range from 5 nm to 20 nm.

The first and second device layer stacks20,21may be formed by patterning a structure of sequentially deposited sacrificial and channel material layers, e.g. a stack of SiGe sacrificial material layers and (epitaxial) Si channel material layers as one example. The first and second device layer stacks20,21may e.g. be patterned to form the respective device layer stacks, separated by a trench. Single- as well as multiple-patterning techniques may be employed, e.g. self-aligned double patterning (SADP), or quadruple patterning (SAQP) or some other conventional self-aligned multiple patterning (SAMP) technique. The first and second device layer stacks20,21may be patterned to form fin-shaped layer stacks, each comprising channel layers24in the form of channel nanosheets, i.e. nanosheet-shaped channel layers, thereby allowing forming of nanosheet-based transistor structures. A nanosheet may by way of example have a width (e.g. as seen across the length of the channel region) in a range from 10 nm to 30 nm and a thickness in a range from 3 nm to 10 nm. It is also possible to pattern the device layer stacks20,21such that the channel layers form nanowire-shaped layers. A nanowire may by way of example have a thickness similar to the example nanosheet however with a smaller width, such as 3 nm to 10 nm.

The insulating wall46may be formed after forming the first and second device stacks20,21by filling the trench of the substrate10between the device layer stacks20,21with an insulating wall material, e.g. an oxide such as SiN, SiCO, SiCN or SiOCN. The insulating wall material may be conformally deposited before being etched isotropically or anisotropically (i.e. in a top-down direction) to remove the deposited insulating material outside the trench. The insulating wall material may be deposited with a thickness such that the insulating wall material deposited at the respective sidewalls of the trench join to “pinch-off” and thus fill the trench. By etching, the insulating material may be removed outside of the trench but preserved in the trench to form the insulating wall46.

FIGS.2a-iillustrate method steps for forming a semiconductor device, applied to the semiconductor structure depicted inFIGS.1a-b. In particular, the figures illustrate results of sequential processing steps.

FIGS.2a-iall show a cross-section along the direction of channels of the finalized transistor device.FIGS.2c,2dand2ifurther show a cross-section perpendicular to the other cross-section, across an insulating wall46of the structure. These cross-sections correspond to the same cross-sections as inFIGS.1a-b.

FIG.2ashows the same semiconductor structure asFIG.1a, thus depicting the result of forming a device layer stack20on a substrate10, the device layer stack20comprising an alternating sequence of lower sacrificial layers22and channel layers24, and a top sacrificial layer26over the topmost channel layer, wherein the top sacrificial layer26is thicker than each lower sacrificial layer22.

A sacrificial gate structure30has further been formed extending across the device layer stack20. The sacrificial gate structure30may be formed in a manner which per se is known in the art, i.e. by patterning a layer of e.g. amorphous Si (e.g. using SADP or SAQP). Portions of the mask (e.g. of hard mask material such as SiO and/or Si3N4) used for the patterning may remain on the sacrificial gate structure30as gate caps36.

FIG.2bshows the result of etching the top sacrificial layer while using the sacrificial gate structure30as an etch mask to form a top sacrificial layer portion27underneath the sacrificial gate structure30. The exposed (i.e. not covered by the sacrificial gate structure30) top surfaces of the top sacrificial layer are thus etched back. As may be better understood from the following, the top sacrificial layer portions27may hence be considered as being incorporated into the sacrificial gate structures30.

This etching may be an anisotropic etch to etch the device layer stack20in a top-down direction. Any suitable dry etching process or wet etching process, or combination of a dry and a wet etching process, may be employed, such as reactive ion etching (RIE).

As shown inFIG.2b, the etching may extend through the entire thickness of the top sacrificial layer. In some embodiments, as will be discussed in relation toFIGS.5a-b, the device layer stack20may comprise an insulating interface layer to act as an etch stop during this process, in order to protect the topmost channel layer24from being etched.

FIG.2cshows the result of conformally depositing a first spacer material on exposed surfaces of the sacrificial gate structure and device layer stack. The dashed lines correspond to where the different cross-sections have been taken with respect to each other.

The first spacer material may further be deposited on outer sidewalls of the first and second device layer stacks20,21, as seen in the rightmost cross-section.

FIG.2dshows the result of an anisotropic etch, etching back (top-down) the first spacer material such that the first spacer material is removed from horizontally oriented surfaces but remain on the vertically oriented surfaces, thereby forming a first spacer41on opposite sidewalls of the sacrificial gate structure30and on end surfaces of the top sacrificial layer portion27.

Due to the conformal nature of the deposition of the first spacer material, first spacer material may as shown further be deposited on outer sidewalls of the first and second device layer stacks20,21inFIG.2c(i.e. sidewalls of the respective device layer stacks facing away from the insulating wall46). Accordingly, subsequent to the anisotropic etch, first spacer material may remain to form the first spacer41also on the outer sidewalls of the device layer stacks.

FIG.2eshows the result of etching the channel layers and lower sacrificial layers while using the sacrificial gate structure30and the first spacer41as an etch mask to form channel layer portions25and lower sacrificial layer portions23underneath the sacrificial gate structure30.

This etching may be an anisotropic etch adapted to etch the device layer stack in a top-down direction. Any suitable dry etching process may be employed, such as RIE.

The exposed (i.e. not covered by the sacrificial gate structure and/or the first spacer) top surfaces of the channel layers and lower sacrificial layers are etched. The etching process may comprise alternating different types or etchants, for example after the topmost channel layer is etched through, a different etchant may be used to etch the subsequent lower sacrificial layer. The use of different etchants may alternate as the materials of the device layer stack alternates.

While the top sacrificial layer portion27may be made from the same material as the lower sacrificial layer, the top sacrificial layer portion27is masked from being etched by both the sacrificial gate structure30and the first spacer41.

FIG.2fshows the result of etching the lower sacrificial layer portions23to form recesses44in the device layer stack on opposite sides of the sacrificial gate structure30, while the first spacer41masks the end surfaces of the top sacrificial layer portion27.

Each of the recesses44is surrounded by channel layer portions25above and/or below and an etched-back end surface of a lower sacrificial layer portion23at one side. Each of the recesses44may have a uniform depth, wherein the depth enables the second spacer to be formed there with sufficient thickness. The recesses may be 3-10 nm deep, such as 7 nm deep.

The exposed end surfaces of the lower sacrificial layer portions23(i.e. not covered by the sacrificial gate structure30and/or the first spacer41) are etched. The etch may be selective for the lower sacrificial layer portion23rather than the channel layer portion25, thereby more of the lower sacrificial layer portions23are etched back than the channel layer portions25, forming lateral recesses44bordered by the channel layer portions25.

The etching may be an isotropic etch process (i.e. non-directional), thus enabling a lateral etch-back of the end surfaces of the lower sacrificial layer portion23. Any suitable dry etching process or wet etching process, or combination of a dry and a wet etching process, may be employed.

FIG.2gshows the result of conformally depositing a dielectric material on exposed surfaces of the sacrificial gate structure30and device layer stack.

As the recesses have a higher degree of surface to volume ratio than the rest of the semiconductor structure, they may be pinched-off by the dielectric material such that a local thickness of the dielectric material deposited in the recesses may be greater than a local thickness of the dielectric material deposited on the end surfaces of the channel layer portion25. Hence, the recesses may be filled after depositing a relatively thin layer of the second spacer material.

FIG.2hshows the result of using an isotropic etch to etch the conformally deposited dielectric material such that end surfaces of the channel layer portions25are exposed on opposite sides of the sacrificial gate structure30and the dielectric material remains in the recesses to form the second spacer42.

The isotropic etch may be selective for the dielectric material of the second spacer42. The geometry of the recesses may cause the recesses to remain covered from the etchants by the dielectric material substantially until the end surfaces of the channel layer portions25are exposed, wherein the isotropic etching may be stopped. Therefore, by timing the end of the isotropic etch, only the dielectric material in the recesses may be left after the isotropic etch, thereby forming the second spacer42. In the schematic illustration ofFIG.2h, the recesses and the second spacers42are shown as structures with substantially straight profiles. However, as may be appreciated the recesses may in practice have an inner sidewall with a curved profile, while the second spacers42may be formed with a curved or crescent shape.

FIG.2ishows the result of forming source and drain regions50by epitaxially growing semiconductor material on the exposed end surfaces of the channel layer portions. The dashed lines correspond to where the different cross-sections have been taken with respect to each other.

Forming source and drain regions may comprise epitaxially growing semiconductor material, which may or may not be doped, for instance through in-situ doping, implantation doping or diffusion doping.

As the first spacer41was formed on the outer sidewalls of the device layer stack inFIG.2c, the first spacer41may act as lateral confinement for the epitaxial growth of source and drain regions50, while the insulating wall46may confine the epitaxial growth (laterally) within the first device region11.

The first spacer41may further remain on the insulating wall46, i.e. on the sidewalls of the insulating wall46exposed after removing the top sacrificial layer. This effectively widens the insulating wall46, which may extend the overlay margin when forming source and drain contacts on the source and drain regions50on either side of the insulating wall46, which may be formed e.g. using lithography.

Source and drain regions50may be formed in the second device region12in a similar manner as in the first device region11. If the source and drain regions50are formed with the same type of doping in both the first and second device region11,12, they may be formed in parallel on either side of the insulating wall46. The first device layer stack may be masked while forming source and drain regions50in the second device region12and vice versa, as will be discussed further in relation toFIGS.4a-d.

In a finalized transistor structure, the channel portions in the middle section of the semiconductor device act as channels between the source and drain regions50. The source and drain regions50may be doped to define whether an NFET or PFET device is to be formed.

FIG.3ais a cross-sectional view of a finalized transistor structure. The dashed line corresponds to where the cross-section ofFIG.3bhas been taken.

The sacrificial gate structures may be replaced with gate stacks34by first selectively etching the sacrificial gate structures leaving gate trenches between the first spacer41and subsequently depositing a gate metal in the gate trenches to form the gate stacks34.

The resulting gate stack34replacing the middle sacrificial gate structure of the semiconductor device may thereby act as a gate for the channels below.

The first spacer41may laterally confine the etch to the sacrificial gate structure. The first spacer41may be preserved in this process and remain as an electrically insulating gate spacer in a finalized transistor device.

The gate stacks34may be formed in a conventional RMG-process. A cover material35may be deposited to cover the source and drain regions50and surround the sacrificial gate structures. The cover material35may be an insulating material, such as an oxide, e.g. silicon oxide, or another gap fill dielectric material, deposited, planarized and recessed, e.g. by chemical mechanical polishing (CMP) and/or etch back. The CMP and/or etch back may proceed to also remove any gate cap36comprised in the sacrificial gate structure, thus revealing an upper surface of the sacrificial gate structure.

The sacrificial gate structure may thereafter be removed to form a gate trench extending across the first and second layer stacks and the insulating wall46and comprising a respective trench portion on either side of the insulating wall46.

After removing the sacrificial gate structure, “released” channel layer portions may be defined by selectively removing lower and upper sacrificial layer portions from the gate trench. As the lower and top sacrificial layer materials are different from the channel layer material, the sacrificial layer portions may be removed by a selective etching process. For example, an HCl-based dry etch may be used to remove SiGe sacrificial layer material with a greater Ge-content than a Si or SiGe channel layer material. However, other appropriate etching processes (e.g. wet etching processes) are also known in the art and may also be employed for this purpose. Upper and lower surfaces of the “released” channel layer portions may be exposed within the respective gate trench portions, extending between respective source/drain regions50. Accordingly, the final gate trench may be defined by the space left by the removal of the top sacrificial layer portion, the lower sacrificial layer portions and the sacrificial gate structure

As may be appreciated (see alsoFIG.3b), the channel layer portions may due to the presence of the insulating wall46be “partly released” in the sense that their upper and lower surfaces as well as outer sidewall surfaces are laid bare while their inner sidewall surfaces (i.e. facing the insulating wall46) are not laid bare but are covered by the insulating wall46.

The cover material may be an insulating material, such as an oxide, e.g. silicon oxide, or another gap fill dielectric material, deposited, planarized and recessed, e.g. by chemical mechanical polishing (CMP) and/or etch back. The CMP and/or etch back may proceed to also remove any gate cap comprised in the sacrificial gate structure, thus revealing an upper surface of the sacrificial gate structure.

During the removal of the sacrificial layer portions, the second spacers42may provide masking of the semiconductor material of the source and drain regions50from any etching chemistries employed.

FIG.3bis a different cross-sectional view of the finalized transistor structure ofFIG.3a. The cross-section ofFIG.3bis perpendicular to the cross-section ofFIG.3aand taken where a gate stack34is present. The dashed line corresponds to where the cross-section ofFIG.3ahas been taken.

Subsequent to the removal of the sacrificial gate structure, a respective gate stack34(comprising a replacement metal gate) may be formed in the respective gate trench portions on either side of the insulating wall46. The gate stack34may (e.g. due to the presence of the insulating wall46and the resulting partial release of the channel region layer portions) have a fork-like shape on either side of the insulating wall46, with a number of prongs extending along and between the channel layer portions25.

The second spacers42may serve to provide an increased electrical isolation and a reduced capacitive coupling between each source/drain region50and adjacent gate stack34.

Each gate stack34may have a composite structure comprising a gate dielectric layer (such as a high-k dielectric e.g. HfO2, HfSiO, LaO, AlO or ZrO) on the channel region layer portions, one or more effective WFM layers on the gate dielectric layer (e.g. an n-type WFM such as TiAl or TiAlC and/or a p-type WFM such as TiN or TaN), and optionally a gate fill metal (such as W, Al, Co or Ru). The WFM layers may be conformally deposited e.g. by ALD. The gate fill metal may for instance be deposited by CVD or PVD.

In more detail, forming the gate stacks may comprise depositing the gate dielectric layer in the gate trench portions. Subsequently, the p-type WFM (or n-type WFM) may be deposited in gate trench portions. The deposition of the p-type (or n-type) WFM may be followed by an etch-back in a top-down direction, in which the p-type (or n-type) WFM is recessed to a level below, at or slightly above an upper surface of the insulating wall46. A mask layer may be deposited, such as SoC or other organic spin-on, and etched back for instance by dry etching to a target level. The etched back mask layer may then be used as a mask while p-type (or n-type) WFM on surfaces above the target level (such as surfaces outside of the gate trench) is removed by for example isotropic etching, e.g. a wet metal etch.

A trench mask may subsequently be formed above a first one of the gate trench portions wherein the p-type (or n-type) WFM may be removed from the other/second gate trench portion by etching, the trench mask and the insulating wall46thus acting as a combined vertical and lateral etch mask for the p-type (or n-type) WFM in the first (or second) gate trench portion.

Subsequently an n-type (or p-type) WFM may be deposited in at least the second (or first) gate trench portion, optionally both.

The gate fill metal may subsequently be deposited to fill a remaining space in the first and second gate trench portions. The gate fill metal may be etched back (top-down) to obtain final gate stacks34of a desired height. The etch back may as shown inFIG.3bperformed such that the respective gate stacks34form electrically disconnected gate stacks, separated by the insulating wall46. It is however also possible to limit the etch back such that the gate stacks34remain connected across the insulating wall46. The gate stacks34may thus designate electrically connected parts of a common gate stack. This may be suitable configuration for e.g. a CMOS inverter.

The method may proceed with contact formation (for the gate stacks34and the source/drain regions50and routing layer formation, as per se is known in the art, to incorporate the transistor structures into a functioning circuit.

FIGS.4a-dillustrate alternative method steps for forming a semiconductor device with complementarily doped source and drain regions. In particular, the figures illustrate results of sequential processing steps.

FIG.4ashows the result of a parallel process for forming a semiconductor device as shown inFIGS.2a-g. The parallel processes have formed a first device layer stack on a first device region11of a substrate and a second device layer stack on a second device region12of the substrate, the first and second device layer stacks being spaced apart by a trench filled with an insulating wall material to form an insulating wall (not shown).

FIG.4bshows the result of filling the second device region12with a relatively inert fill material in order to counteract the following processing steps affecting the second device layer stack.

FIG.4cshows the result of using an isotropic etch to etch the conformally deposited dielectric material such that end surfaces of the channel layer portions of the first device layer stack are exposed on opposite sides of the sacrificial gate structure and the dielectric material remains in the recesses to form the second spacer. This step corresponds to the step ofFIG.2h.

FIG.4dshows the result of forming source and drain regions in the first device layer stack by epitaxially growing semiconductor material on the exposed end surfaces of the channel layer portions of the first device layer stack.

Subsequently, after the fill material is removed, the processing steps ofFIGS.4b-dmay be repeated while inverting the processing of the first and second device layer stacks to achieve a complimentary transistor structure once finalized.

FIG.5ais a cross-sectional view of a semiconductor structure similar to the one ofFIG.1a, further comprising an insulating interface layer47and a bottom insulating layer48.

The device layer stack may comprise an insulating interface layer47between the top sacrificial layer26and the topmost channel layer24. The insulating interface layer47may act as an etch stop when etching the top sacrificial layer26. In other words, the insulating interface layer47masks the topmost channel layer24when etching the top sacrificial layer26.

The insulating interface layer47may comprise a pad oxide or any suitable dielectric material such as SiO2, SiN, SiCN or SiOCN. The insulating interface layer47may be 3-10 nm thick, such as 5 nm thick.

The device layer stack may be formed on a bottom insulating layer48. The bottom insulating layer48is between the device layer stack and the substrate10. The bottom insulating layer48may be submerged into the substrate10as shown inFIG.2aor formed as part of the device layer stack.

The bottom insulating layer48may mitigate charge carrier leakage from e.g. the source, the drain or the channel into the underlying semiconductor substrate10.

The bottom insulating layer48may act as an etch stop to counteract over-etching into the substrate10while etching the channel layers24and lower sacrificial layers of each device layer stack.

The bottom insulating layer48may comprise any suitable dielectric, such as SiO2, SiN, SiCN or SiOCN. The bottom insulating layer48may be formed while forming the device layer stack or be a part of the substrate10. The bottom insulating layer48may be 5-15 nm thick, such as 10 nm thick.

FIG.5bis a cross-sectional view of the semiconductor device ofFIG.1bfurther comprising an insulating interface layer47and a bottom insulating layer48. These insulating layers47,48may be formed separately in each device region or jointly e.g. while forming the insulating wall46or while jointly forming the device stacks.

For example, the insulating interface layer47may be formed while forming the device layer stack by epitaxially growing or depositing a pad oxide or dielectric material after forming the topmost channel layer24and before forming the top sacrificial layer26.

The insulating interface layer47may alternatively be formed while forming the insulating wall46by forming parts of the insulating wall46before the formation of the top sacrificial layers26, forming the insulating wall material also on top of the topmost channel layers24and then forming the top sacrificial layers26on top of the insulating wall material acting as an insulating interface layer47before finalizing the formation of the insulating wall46.

In the above the inventive concept has mainly been described with reference to a limited number of examples. However, as is readily appreciated by a person skilled in the art, other examples than the ones disclosed above are equally possible within the scope of the inventive concept, as defined by the appended claims.