Patent ID: 12254200

DESCRIPTION OF EMBODIMENTS

To make the objectives, technical solutions, and advantages of this application clearer, the following further describes this application in detail with reference to the accompanying drawings. A specific operation method in a method embodiment may also be applied to an apparatus embodiment or a system embodiment. It should be noted that, in descriptions of this application, “at least one” means one or more, and “a plurality of” means two or more. In view of this, “a plurality of” may also be understood as “at least two” in the embodiments of the present application. The term “and/or” describes an association relationship between associated objects and indicates that three relationships may exist. For example, A and/or B may indicate the following three cases: Only A exists, both A and B exist, and only B exists. In addition, the character “/” usually indicates an “or” relationship between associated objects unless otherwise specified. In addition, it should be understood that in the descriptions of this application, terms such as “first” and “second” are merely used for distinguishing and description, but should not be understood as indicating or implying relative importance, or should not be understood as indicating or implying a sequence.

The following clearly describes the technical solutions in the embodiments of this application with reference to the accompanying drawings in the embodiments of this application.

A startup speed of an electronic device is an important indicator for measuring performance of the electronic device. Using a computer as an example, a higher startup speed of the computer can better shorten a waiting time of a user, and therefore is more conducive to improvement of user experience. In the computer, there are a plurality of function systems, such as a memory system and a video card system. The computer can be started up only after most of the function systems are initialized.

Generally, in a computer startup process, the computer usually needs to initialize the memory system first, to initialize another function system by using the initialized memory system. Therefore, memory system initialization (that is, memory initialization) is an important part of an electronic-device startup process. Shorter memory initialization duration better helps to increase an electronic-device startup speed.

Usually, memory initialization may be implemented by a processor, for example, a central processing unit (CPU), in an electronic device.FIG.1is an example of a schematic diagram of a structure of an electronic device. As shown inFIG.1, the electronic device100includes a processor101and at least one memory chip (memory chips0to L−1), where L is an integer greater than or equal to 1.

The processor101includes at least one core, for example, a core0to a core N−1 shown inFIG.1, where N is an integer greater than or equal to 1. Each core can implement a logical computing function. When N is greater than 1, the processor101may also be referred to as a multi-core processor. In this case, the plurality of cores in the processor101may perform parallel logical computing, to increase an overall computing speed of the processor101.

As shown inFIG.1, the processor101may further include a memory controller102. The memory controller102may control the memory chip0to the memory chip L−1. For example, the memory controller102may perform a read/write operation and a refresh operation on the memory chip0to the memory chip L−1. For example, the memory controller102may be a double data rate (DDR) subsystem.

In an embodiment, as shown inFIG.1, the memory controller102may include at least one memory channel, for example, a memory channel1to a memory channel M, where M is an integer greater than or equal to 1. Each memory channel may be connected to at least one memory chip, and each memory channel can control at least one memory chip connected to the memory channel.

As shown inFIG.1, the memory channel1is connected to the memory chip0and a memory chip1, and the memory channel1can control the memory chip0and the memory chip1. For another example, the memory channel M is connected to a memory chip L−2 and the memory chip L−1, and the memory channel M can control the memory chip L−2 and the memory chip L−1.

The memory channel1includes a DDR management controller (DMC)1and a physical layer interface (PHY interface)1. The read/write operation is used as an example. The DMC1may parse a read/write request sent by the cores0to N−1, and read data from or write data to the memory chip0and the memory chip1through the PHY interface1based on a parsing result. Similarly, a memory channel2may also include a DMC2and a PHY interface2, and the memory channel M may also include a DMC M and a PHY interface M. Details are not described herein.

After the electronic device is powered on, the processor101may perform memory initialization after completing basic system component initialization. For example, the processor101may perform memory initialization after completing system phase locked loop (system PLL) initialization, and initialization of system components such as a serial port and an inter-integrated circuit (I2C) interface.

Usually, in a memory initialization process, the processor101not only needs to initialize the memory chip0to the memory chip L−1, but also needs to initialize the memory controller102. Memory initialization may be understood as configuration and adjustment of a plurality of parameters in the memory chip0to the memory chip L−1 and the memory controller102.

A single-core initialization manner is used as an example. The processor101includes a core serving as a master core, and the master core initializes the memory controller102and the memory chip0to the memory chip L−1.

In a specific example, it is assumed that a core0is the master core. The core0may sequentially initialize, in a preset order, the M memory channels in the memory controller102and the memory chip0to the memory chip L−1. For example, the core0may first initialize the memory channel1, the memory chip0, and the memory chip1, then initialize the memory channel2, a memory chip2, and a memory chip3, . . . , and finally initialize the memory channel M, the memory chip L−2, and the memory chip L−1.

Initialization of the memory channel1, the memory chip0, and the memory chip1is used as an example. This process includes stages such as initialization configuration, memory training, and memory testing. Details are as follows:

Initialization Configuration

During initialization configuration, the core0may perform basic configuration on the M memory channels in the memory controller102and the memory chip0to the memory chip L−1, so that the memory controller102and the memory chip0to the memory chip L−1 can support subsequent channel initialization.

For example, the core0may separately read serial presence detect (SPD) information in the memory chip0and the memory chip1. The SPD information is stored in a small-capacity memory in the memory chip, and includes information such as a memory capacity and a read/write frequency of the memory chip. The core0may determine, by attempting to read the SPD information, whether the memory channel1is connected to the memory chip0and the memory chip1. After determining that the memory channel1is connected to the memory chip0and the memory chip1, the core0may further perform initialization configuration on the memory channel1, the memory chip0, and the memory chip1based on the SPD information.

For example, the memory chip0and the memory chip1usually have a same read/write frequency. The core0may configure, based on read/write frequencies of the memory chip0and the memory chip1, a working frequency of a phase locked loop (PLL) adapted to the memory chip0and the memory chip1. The PLL may provide a clock signal for the memory chip0and the memory chip1. For another example, the core0may alternatively configure a working frequency of the memory channel1based on the read/write frequencies of the memory chip0and the memory chip1, to adapt the working frequency of the memory channel1to the read/write frequencies of the memory chip0and the memory chip1, so that a control signal output by the memory channel1can be identified by the memory chip0and the memory chip1.

Memory Training

Control signals output by the memory channel1include a data strobe signal (DQS) and a data signal. A rising edge or falling edge of the DQS can trigger the memory chip0and the memory chip1to receive the data signal. For example, the rising edge of the DQS can trigger the memory chip0and the memory chip1to receive the data signal. As shown inFIG.2, the DQS and the data signal have a same cycle T. One cycle T may be further divided into two parts based on the rising edge of the DQS, where a part before the rising edge may be referred to as a setup time, and a part after the rising edge may be referred to as a hold time.

For the DQS before memory training shown inFIG.2, one cycle T may be divided into a setup time t1and a hold time t2based on a rising edge of the DQS before memory training. The setup time t1is comparatively short, and consequently, the memory chip0(the memory chip1likewise) prematurely starts to receive the data signal. Meanwhile, a level change of the data signal also requires a specific delay. In this case, misreading may occur on the memory chip0.

For example, if the memory chip0starts to receive the data signal before the data signal rises to a high level, the data signal at the high level may be misread as the data signal at a low level. It can be learned that the DQS before memory training is not conducive to improving stability of the memory channel1, the memory chip0, and the memory chip1. Similarly, if the hold time t2is comparatively short, the memory chip0may have no time to read a level status of the data signal, and consequently, a stability problem may also occur.

For the DQS after memory training shown inFIG.2, one cycle T may be divided into a setup time t3and a hold time t4based on a rising edge of the DQS after memory training. The setup time t3and the hold time t4have same or close duration. The “close” may be understood as that a difference between the setup time t3and the hold time t4is not greater than a specified threshold. In this case, the memory chip0can read a comparatively accurate level status of the data signal. This helps to ensure stability of the memory channel1, the memory chip0, and the memory chip1.

It should be noted that, usually, adjusting a time sequence relationship between the DQS and the data signal is merely a part of tasks in memory training. In addition to alignment between the DQS and the data signal, time sequence alignment between a plurality of signals such as the DQS and the clock signal also needs to be performed. In addition, during memory training, the core0may further adjust a magnitude of termination resistance, a reference voltage value, and the like in the memory channel1, which are not enumerated one by one in this embodiment of this application. The memory channel1can be matched with the memory chip0and the memory chip1through memory training, so that the memory channel1, the memory chip0, and the memory chip1can run stably in a subsequent memory control process.

Memory Testing

After completing memory training for the memory channel1, the memory chip0, and the memory chip1, the core0may further perform memory testing on the memory channel1, the memory chip0, and the memory chip1, to verify a memory training result. Generally, memory testing includes operations such as margin testing, eye scan, storage testing, and storage cleanup.

After memory testing is passed, channel initialization of the memory channel1, the memory chip0, and the memory chip1is completed. The core0may sequentially complete initialization of the memory channel1, the memory chip0, and the memory chip1to the memory channel M, the memory chip L−2, and the memory chip L−1 according to the foregoing process.

Then, the core0may further perform system configuration on the memory controller102and the memory chip0to the memory chip L−1, to generate management information. The management information may be used by the core0to the core N−1 to manage the memory chip0to the memory chip L−1. For example, system configuration may include memory interleaving configuration, non-uniform memory access (NUMA) setting, and the like.

Although memory initialization can be implemented by using the foregoing process, with the increase of a memory chip capacity and a memory chip read/write frequency, duration of memory initialization implemented by using the foregoing process is increasingly long. For example, in a process of memory training shown inFIG.2, because the read/write frequencies of the memory chip0and the memory chip1are increased, duration of the cycle T is shortened, and the core0needs to perform more refined adjustment to make the setup time t3and the hold time t4equal or close. As a result, the core0needs to send a larger amount of adjustment information to the memory channel1.

As shown inFIG.1, there is a comparatively long physical link between the core0and the memory channel1, and the physical link further includes elements such as a home agent (HA). Consequently, a delay between the core0and the memory channel1is comparatively long. The long delay and the increased amount of the adjustment information greatly prolong duration of memory training for the memory channel1, and memory training for another memory channel also has the same problem. Therefore, memory initialization duration is greatly prolonged. In addition, because a memory chip read/write frequency is increased, a quantity of signals on which time sequence alignment needs to be performed in a memory training process may also be increased, which further prolongs memory initialization duration.

For another example, in a memory testing process, the core0writes data to the memory chip0(e.g., storage testing), and after the testing is completed, further needs to clear the data written in the testing process (e.g., storage cleanup). Because a capacity of the memory chip0is increased, the core0needs to write more data to the memory chip0during storage testing, and clear more data during storage cleanup. It can be learned that, as a memory chip capacity increases, an amount of information read and written between the core0and the memory channel1is also increased, and therefore, memory initialization duration is also prolonged.

To sum up, under impact of a delay of control information (such as the foregoing adjustment information and read/write information) received by the memory controller102, with the increase of a memory chip capacity and a memory chip working frequency, memory initialization duration is increasingly long.

In view of this, embodiments of this application provide a memory initialization apparatus and solution, to shorten memory initialization duration by adding a second processor core to a memory controller. It should be noted that the memory initialization apparatus provided in the embodiments of this application may be a processor configured to control a memory, or may be a chip integrated with a processor, such as a CPU, a system on chip (SoC), or an electronic control unit.

For example, as shown inFIG.3, a processor30provided in an embodiment of this application includes a first processor core31and a memory controller32, and the memory controller32includes a second processor core321. In a process of performing memory initialization, the first processor core31may invoke the second processor core321to perform memory initialization.

Because the second processor core321is disposed in the memory controller32, compared with the first processor core31, a physical link between the second processor core321and each structure (such as a memory channel) in the memory controller32is shorter, and a signal transmission link delay is smaller. Therefore, invoking the second processor core321to perform some or all of tasks in memory initialization helps to shorten initialization duration. In addition, while the second processor core321is performing some of the tasks of memory initialization, the first processor core31may further perform another memory initialization task in parallel, thereby helping to further shorten the memory initialization duration.

The following further describes, as examples, specific implementations of the second processor core321and the first processor core31.

1. Second Processor Core321

The second processor core321may be a logical circuit (or module) with a logical computing capability, and can perform, based on invocation by the first processor core, all or some of the tasks in memory initialization.

In an embodiment, the second processor core321may be configured to perform an initialization task related to a single memory channel, that is, channel initialization. For example, channel initialization may include one or more of tasks such as memory training and memory testing.

In a current memory initialization solution, the first processor core31needs to send a large amount of control information (such as the read/write information sent in the memory testing process and the adjustment information sent in the memory training process described above) to the memory controller32. Under impact of a link delay between the first processor core31and the memory controller32, channel initialization occupies a comparatively large amount of time in memory initialization.

Compared with the link delay between the first processor core31and the memory controller32, a smaller link delay can be implemented for the second processor core321because the second processor core321is located inside the memory controller32. Therefore, invoking the second processor core321to perform channel initialization can significantly shorten channel initialization duration, thereby shortening the overall memory initialization duration.

It should be noted that a quantity of second processor cores321in the memory controller32is not limited in this embodiment of this application. For example, inFIG.4, the memory controller32may include one second processor core321, and the second processor core321is separately connected to M memory channels. In this case, the first processor core31may invoke the second processor core321to perform channel initialization on the M memory channels.

For another example, the memory controller32may include a plurality of second processor cores, and each second processor core may be connected to one or more memory channels. Specifically, a connection relationship between each second processor core and a memory channel may be any one of a one-to-one correspondence, a one-to-many correspondence, or a many-to-one correspondence.

If one second processor core is connected to a plurality of memory channels, the first processor core31may invoke the second processor core to perform channel initialization on the plurality of memory channels connected to the second processor core. If a plurality of second processor cores are connected to one memory channel, the first processor core31may invoke the plurality of second processor cores to perform channel initialization on the memory channel.

An example of a case in which one second processor core is connected to one memory channel is shown inFIG.5. The memory controller32includes M second processor cores (a second processor core321-1to a second processor core321-M). The M second processor cores are respectively connected to M memory channels in the memory controller32in one-to-one correspondence.

Each second processor core can perform, based on invocation by the first processor core31, channel initialization on a memory channel connected to the second processor core. In other words, the first processor core31may invoke any second processor core to perform channel initialization on a memory channel connected to the second processor core. For example, the first processor core31may invoke the second processor core321-1to perform channel initialization on a memory channel1, and invoke the second processor core321-M to perform channel initialization on a memory channel M.

For ease of understanding, unless otherwise specified, the processor30shown inFIG.5is used as an example for description below in this embodiment of this application.

2. First Processor Core31

In an embodiment of this application, the first processor core31may include one core (for example, a core0serving as a master core) in the processor30, or may include a plurality of cores in the processor30. In other words, the M second processor cores in the memory controller32may be invoked by one core in the processor30, or the M second processor cores in the memory controller32may be invoked in parallel by a plurality of cores in the processor30.

For example, a value of M is 8, that is, the memory controller32includes eight memory channels and eight second processor cores (a second processor core321-1to a second processor core321-8). The core0may invoke the second processor core321-1to a second processor core321-3, to perform channel initialization on a memory channel1to a memory channel3. A core1invokes a second processor core321-4to the second processor core321-8, to perform channel initialization on a memory channel4to a memory channel8. According to this implementation, the core0and the core1may invoke the second processor cores in parallel, thereby helping to further shorten the initialization duration.

In this embodiment of this application, the first processor core31may invoke the second processor core. In view of this, as shown inFIG.3, the memory controller32may further include a storage circuit322. The storage circuit322may be used as an interface for the first processor core31to invoke the second processor core321.

It should be noted that a quantity of storage circuits322is not limited in this embodiment of this application, and the memory controller32may include one or more storage circuits. A correspondence between each storage circuit and a second processor core may be any one of a one-to-one correspondence, a one-to-many correspondence, or a many-to-one correspondence. For example, in a case of the one-to-one correspondence, one storage circuit may be used as an invocation interface of one second processor core; in a case of the one-to-many correspondence, one storage circuit may be used as an invocation interface of a plurality of second processor cores; in a case of the many-to-one correspondence, a plurality of storage circuits may be jointly used as an invocation interface of one second processor core.

For ease of understanding, the one-to-one correspondence is used as an example for description below in this embodiment of this application. As shown inFIG.4, the second processor core321is correspondingly connected to the storage circuit322. For another example, inFIG.5, the second processor core321-1is correspondingly connected to a storage circuit322-1, . . . , and the second processor core321-M is correspondingly connected to a storage circuit322-M.

If the storage circuit is connected to the second processor core in one-to-one correspondence, the storage circuit and the second processor core may also be understood as a slave core subsystem. As shown inFIG.6, a slave core subsystem600is a slave core subsystem that includes the second processor core321-1and the storage circuit322-1inFIG.5. The storage circuit322-1is separately connected to the first processor core31and the second processor core321-1, and the second processor core321-1is connected to the memory channel1.

When invoking the second processor core321-1, the first processor core31may write invocation information to the storage circuit322-1. The second processor core321-1may read the invocation information from the storage circuit322-1and execute the invocation information. In this way, the second processor core321-1is invoked. The invocation information may be information used to implement memory initialization. For example, the invocation information may be written to the storage circuit322-1in a form of program code, and the second processor core321-1performs memory initialization by executing the invocation information. For example, the second processor core321-1may implement channel initialization of the memory channel1by executing the invocation information.

In an embodiment, after writing the invocation information to the storage circuit322-1, the first processor core31may further write reset deassertion information to the storage circuit322-1. After reading the reset deassertion information, the second processor core321-1reads the invocation information from the storage circuit322-1and executes the invocation information.

Generally, the first processor core31may write the reset deassertion information and the invocation information to different locations in the storage circuit322-1. For example, as shown inFIG.6, the storage circuit322-1includes a register611and a static random access memory (SRAM)612. The first processor core31may write the reset deassertion information to a flag bit of the register611, and write the invocation information to the SRAM612.

For example, an initial level state of the flag bit in the register611may be 0, and after the reset deassertion information is written, the level state of the flag bit is changed to 1. The second processor core321-1may periodically read a level state of the flag bit. When the level state of the flag bit is changed to 1, it means that the first processor core31has written the invocation information to the SRAM612. In this case, the second processor core321-1may read the invocation information from the SRAM612and execute the invocation information.

Generally, before invoking the second processor core321-1, the first processor core31may further allocate a communication address to the storage circuit322-1. Then, the first processor core31may read data from or write data to the storage circuit322-1based on the communication address. For example, the first processor core31may address the register611and the SRAM612of the storage circuit322-1together within an addressing range of the first processor core31, so that the first processor core31can read data from or write data to the register611and the SRAM612.

The following further describes the invocation information by using examples.

In an embodiment, the invocation information may be written to the second processor core321-1in a form of complete code, and the second processor core321-1executes the complete code, thereby completing channel initialization for the memory channel1.

In another embodiment, to implement more flexible invocation, the invocation information may include at least one instruction. Each instruction may correspond to one or more operations in memory initialization. When invoking the second processor core321-1, the first processor core31may flexibly invoke, by using an instruction sequence number, the second processor core321-1to execute an instruction corresponding to the instruction sequence number, so as to flexibly control an operation performed by the second processor core321-1.

For example, the invocation information may be divided into at least configuration function information, training function information, and testing function information. An instruction included in the configuration function information corresponds to a channel configuration related operation, and the second processor core321-1may complete configuration of the memory channel1, a memory chip0, and a memory chip1by running the configuration function information. An instruction included in the training function information corresponds to a memory training related operation, and the second processor core321-1may perform memory training on the memory channel1by running the training function information. An instruction included in the testing function information corresponds to a memory testing related operation, and the second processor core321-1performs memory testing on the memory channel1by running the testing function information.

Using the configuration function information as an example, a correspondence between an instruction sequence number and an instruction may be shown in Table 1 below:

TABLE 1Instruction sequence numberInstructionf1RCD configurationf2DB configurationf3PHY interface configurationf4DMC configurationf5MR configurationf6Other configuration

An instruction corresponding to the instruction sequence number f1is to configure a registered clock driver (RCD). The RCD is located in the memory chip0and the memory chip1. The first processor core31may invoke, by using the instruction sequence number f1, the second processor core321-1to configure the RCD in the memory chip0and the memory chip1.

An instruction corresponding to the instruction sequence number f2is to configure a data buffer (DB). The DB is located in the memory chip0and the memory chip1. The first processor core31may invoke, by using the instruction sequence number f2, the second processor core321-1to configure the DB in the memory chip0and the memory chip1.

An instruction corresponding to the instruction sequence number f3is to configure a PHY interface. the first processor core31may invoke, by using the instruction sequence number f3, the second processor core321-1to configure the PHY interface.

An instruction corresponding to the instruction sequence number f4is to configure a DMC. the first processor core31may invoke, by using the instruction sequence number f4, the second processor core321-1to configure the DMC.

An instruction corresponding to the instruction sequence number f5is to configure a mode register (MR). The first processor core31may invoke, by using the instruction sequence number f5, the second processor core321-1to configure the MR.

Running of some of instructions further requires a specific execution parameter. Therefore, when invoking the second processor core321-1to execute an instruction, the first processor core31may further write, to the storage circuit322-1, an execution parameter corresponding to the instruction, so that the second processor core321-1can execute the instruction.

For example, when the first processor core31invokes, by using the instruction sequence number f3, the second processor core321-1to configure the PHY interface, the first processor core31may write a resistance value of a termination resistor to the storage circuit322-1. In a process of configuring the PHY interface, the second processor core321-1may configure a termination resistor in the PHY interface based on the resistance value of the termination resistor in the storage circuit322-1.

In an embodiment, after executing any instruction, the second processor core321-1may further feed back an execution result of the instruction to the first processor core31. For example, whether the instruction is successfully executed is fed back to the first processor core31.

In an embodiment, as shown inFIG.7, the first processor core31may write the instruction sequence number to the register611, and write, to the SRAM612, the execution parameter corresponding to the instruction. After reading the instruction sequence number from the register611, the second processor core321-1reads, from the SRAM612, the instruction corresponding to the instruction sequence number and the execution parameter corresponding to the instruction. Then, the second processor core321-1may execute the target instruction based on the read execution parameter.

After executing the target instruction, the second processor core321-1may further write an instruction execution result to the SRAM612, so that the first processor core31can read the instruction execution result from the SRAM612. In this way, the first processor core31can know an execution status of the second processor core321-1. In another embodiment, the first processor core31may alternatively write the instruction sequence number to the SRAM612.

In an embodiment of this application, the storage circuit322-1is used as an interaction interface between the first processor core31and the second processor core321-1. An interaction interface format is agreed on, so that in a memory initialization process, the first processor core31can invoke, by writing to the register or SRAM space of the storage circuit322-1, the second processor core321-1to perform some or all of the tasks in memory initialization; and invocation of another second processor core is similar. Memory initialization is performed through cooperation and interaction between the first processor core31and each second processor core.

The “interaction interface format” may be understood as a correspondence between different types of data and different storage intervals in the storage circuit322-1. For example, a storage structure in the SRAM612may be shown inFIG.8. A0-76K interval is used to store the invocation information, written by the first processor core31and read by the second processor core321-1. In an embodiment, the invocation information may be information in firmware of the second processor core321-1, in other words, the firmware of the second processor core321-1includes the invocation information. The0-76K interval in the SRAM612may be used to store the firmware of the second processor core321-1.

A76K-78K interval is used to store an instruction sequence number queue, written by the first processor core31and read by the second processor core321-1. It can be understood that, if the register611stores the instruction sequence number, the part of storing the instruction sequence number queue may be omitted. A78K-84K interval is used to store feedback information, written by the second processor core321-1and read by the first processor core31.

In an embodiment of this application, the feedback information may include print information, event information, an instruction execution result, and the like. For example, an interval from80K to84K may be used to store the print information. For example, when performing channel initialization, the second processor core321-1may feed back current execution progress as the print information to the first processor core31. An interval from78K to80K may be used to store an event queue. For example, the second processor core321-1may report fault information of the memory channel1by using the event queue. An84K-96K interval is used to store basic data of the memory channel1, written by the first processor core31and read by the second processor core321-1. The basic data may be understood as data that may be used during running of the second processor core321-1, for example, may be global data such as a working frequency of the processor30and a startup mode of memory initialization.

In the following, a memory initialization procedure shown inFIG.9is used as an example to further describe the memory initialization apparatus (e.g., the processor30) provided in this embodiment of this application.

1. Initialization Configuration Stage

Similar to a conventional memory initialization process, in an embodiment of this application, the initialization configuration stage completes basic configuration for the memory controller32and the memory chip0to the memory chip L−1, so that the memory controller32and the memory chip0to the memory chip L−1 can perform a subsequent initialization process.

In an embodiment, the first processor core31may invoke the second processor core321-1, so that the second processor core321-1performs initialization configuration on the memory channel1, the memory chip0, and the memory chip1. In another embodiment, alternatively, the first processor core31may directly perform initialization configuration on the memory channel1, the memory chip0, and the memory chip1. This is not limited in this embodiment of this application.

For example, using the memory channel1as an example, as shown inFIG.9, the initialization configuration stage includes the following operations:

In operation S901, the first processor core31obtains SPD information.

In operation S902, the first processor core31configures read/write frequencies of the memory chip0and the memory chip1and a working frequency of the memory channel1based on the SPD information.

For specific implementation of operations S901and S902, refer to the conventional memory initialization process. Details are not described herein again.

For example, as shown inFIG.3, the processor30may further include an input/output (I/O) controller33. One end of the I/O controller33is connected to the first processor core31, and another end of the I/O controller33is connected to a nonvolatile memory40.

The nonvolatile memory40may be a memory such as a flash memory or a magnetic disk. The nonvolatile memory40stores firmware of the first processor core31. For example, the firmware of the first processor core31may include unified extensible firmware interface (UEFI) code.

After the processor30is powered on, the first processor core31may read the firmware of the first processor core31from the nonvolatile memory40, and execute the firmware. For example, the first processor core31may implement the foregoing initialization configuration by executing the firmware.

It should be noted that, if the first processor core31directly performs initialization configuration, in an embodiment, the first processor core31may first complete initialization configuration on the memory channel1to the memory channel M and the memory chip0to the memory chip L−1 together, and then, the first processor core31invokes the second processor core321-1to the second processor core321-M together to perform channel initialization.

In another embodiment, the first processor core31may invoke the second processor core321-1after completing initialization configuration for the memory channel1, the memory chip0, and the memory chip1. In a process in which the second processor core321-1performs channel initialization on the memory channel1based on invocation by the first processor core31, the first processor core31may continue to perform initialization configuration on the memory channel2, the memory chip2, and the memory chip3. In other words, the first processor core31may perform memory initialization in parallel with the second processor core. This implementation helps to further shorten memory initialization duration.

2. Memory Training Stage

In this embodiment of this application, the first processor core31may invoke the second processor core321-1to perform memory training. For example, as shown inFIG.9, the memory training stage includes the following operations:

In operation S903, the first processor core31writes the invocation information to the second processor core321-1.

In an embodiment of this application, the invocation information may be alternatively stored in the nonvolatile memory40. Specifically, the nonvolatile memory40may further store the firmware of the second processor core321-1, and the firmware of the second processor core321-1includes the invocation information.

It should be noted that firmware of different second processor cores may be the same or may be different. This is not limited in this embodiment of this application. Generally, the at least one second processor core in the memory controller32may have same firmware, to reduce occupation in the nonvolatile memory40.

In S903, the first processor core31may copy the firmware of the second processor core321-1to corresponding storage space in the SRAM612, such as space0-76K inFIG.8, so that the second processor core can be started. Then, the first processor core31delivers an instruction sequence number to the second processor core321-1by writing to the register611and the SRAM612, so as to perform memory initialization.

For example, as shown inFIG.10, firmware1is the firmware of the first processor core31, firmware2is the firmware of the second processor core321-1, and the firmware1and the firmware2may be separately stored in different areas in the nonvolatile memory40. According to this embodiment, same or different compilation manners may be used between the firmware1and the firmware2, and even if the first processor core31and the second processor core321-1use different architectures, the first processor core31can still invoke the second processor core321-1.

For example, the first processor core31uses an advanced reduced instruction set computing machine (ARM) architecture, and the second processor core321-1uses a fifth-generation reduced instruction set computing (RISC-V) architecture. In this case, the firmware1may be compiled based on the ARM architecture, so that the first processor core31can execute the firmware1; and the firmware2may be compiled by using the RISC-V architecture, so that the second processor core321-1can execute the firmware2.

In operation S904, after writing the invocation information, the first processor core31writes the reset deassertion information to the storage circuit322-1, so that the second processor core321-1starts to execute the invocation information. In an embodiment, after reading the reset deassertion information, the second processor core321-1further executes the firmware of the second processor core321-1to initialize the second processor core321-1. Then, the second processor core321-1may enter a ready state, and feed back current state information of the second processor core321-1to the first processor core31.

In operation S905, after the second processor core321-1enters the ready state, the first processor core31invokes, by using the instruction sequence number, the second processor core321-1to perform memory training. For a specific invocation process, refer to the foregoing embodiments, and details are not described again.

In operation S906, the second processor core321-1performs memory training based on invocation by the first processor core31. This process is similar to a conventional memory training process. A difference lies in that memory training in this embodiment of this application is performed by the second processor core321-1. A specific process is not described again.

3. Memory Testing Stage

As shown inFIG.9, the memory testing stage includes the following operations:

In operation S907, margin testing is performed.

In operation S908, eye scan is performed.

In operation S909, storage testing is performed.

In operation S910, configuration information is reported. In an embodiment, after all testing such as S907to S909is passed, the second processor core321-1may report configuration information of the memory channel1to the first processor core31after channel initialization. The configuration information of the memory channel1may include information such as an actual available memory capacity of the memory channel1.

In operation S911, storage cleanup is performed.

A specific implementation process of S907to S909and S911is similar to a memory testing process in conventional memory initialization. A difference lies in that memory testing in this embodiment of this application is performed by the second processor core321-1. A specific process is not described in detail.

At this point, channel initialization of the memory channel1is completed.

In an embodiment of this application, because the second processor core321-1can perform memory initialization in place of the first processor core31, a time of the first processor core31can be released. In other words, when the second processor core321-1performs channel initialization, the first processor core31may process another task in parallel. For example, the first processor core31may perform initialization configuration on another memory channel and a memory chip. For another example, the first processor core31may further initialize another component (for example, a peripheral such as a video card or a network adapter).

Specifically, initialization of the other component requires participation of a memory. After channel initialization is completed for any one or more memory channels, the first processor core31may initialize another component in parallel by using the memory channel for which channel initialization is completed. The memory channel1is used as an example. After channel initialization is completed for the memory channel1, the memory channel1has a stable read/write capability for the memory chip0and the memory chip1. In other words, the first processor core31can read from and write to the memory chip0and the memory chip1through the memory channel1. Therefore, the first processor core31may initialize another component by using the memory channel1, the memory chip0, and the memory chip1.

According to this embodiment, memory initialization and initialization of another component may be performed in parallel, thereby helping to further shorten an electronic-device power-on time, and helping to further improve user experience.

4. System Configuration Stage

For the multi-channel memory controller32, after channel initialization is completed for each memory channel, the first processor core31usually further needs to perform system configuration to generate management information. The management information may be used by the first processor core31to manage the memory chip coupled to the memory controller32. A specific implementation is not described in detail.

For example, as shown inFIG.9, the system configuration stage includes the following operations:

In operation S912, memory interleaving configuration is performed. In an embodiment, the first processor core31may configure contiguous storage addresses for memory chips connected to different memory channels, so that the plurality of memory channels can be accessed in parallel during data reading/writing, thereby helping to increase read/write bandwidth.

For example, the first processor core31configures addresses of a part of storage space in the memory chip1as0-20, and configures addresses of a part of storage space in the memory chip2as21-40. In this case, the first processor core31may write data to an address interval0-40through the memory channel1and the memory channel2. During the writing, a write operation is performed through the memory channel1and the memory channel2in parallel, thereby greatly increasing a data write speed.

It can be understood that the first processor core31may further perform memory interleaving configuration between different banks inside a single memory chip. A specific implementation is not described in detail.

In operation S913, non-uniform memory access (NUMA) setting is performed. In an embodiment, the first processor core31may configure access priorities of a plurality of memory channels for each core. The core0is used as an example. The first processor core31may configure access priorities of a plurality of memory channels for the core0based on a delay on a physical link, where a memory channel with a smallest delay on a physical link to the core0has a highest priority. According to this embodiment, in a subsequent read/write process, the core0can preferentially access the memory channel corresponding to the physical link with the smallest delay, thereby helping to increase an access speed.

In operation S914, memory map resource management is performed. For example, a storage area of an operating system or application data in the memory is determined, and a current memory occupation status is determined.

At this point, memory initialization is completed.

It should be noted that this embodiment of this application not only helps to shorten memory initialization duration, but also facilitates function expansion for the memory controller32, so that the memory controller32can flexibly adapt to different application requirements. Examples are provided below:

1. Power Management

After memory initialization is completed, the first processor core31may further invoke the second processor core321to perform power management.

The second processor core321-1inFIG.5is used as an example. The first processor core31may invoke the second processor core321-1to manage a power supply that supplies power to the memory chip0and the memory chip1. It is assumed that the memory chip0and the memory chip1share a same power supply. The second processor core321-1may monitor a working status of the memory chip0and the memory chip1. For example, the second processor core321-1may monitor a quantity of times of reading from and/or writing to the memory chip0and the memory chip1per unit time, and a quantity of times of occurrence of a correctable error in the memory chip0and the memory chip1.

The second processor core321-1may further adjust, based on the working status of the memory chip0and the memory chip1, output power of the power supply that supplies power to the memory chip0and the memory chip1. For example, if the quantity of times of reading from and/or writing to the memory chip0and the memory chip1per unit time is greater than a first quantity threshold, the output power of the power supply is increased, which may also be understood as increasing an output voltage of the power supply and/or increasing an output current of the power supply. If the quantity of times of reading from and/or writing to the memory chip0and the memory chip1per unit time is less than a second quantity threshold, the output power of the power supply is reduced.

According to an embodiment, the memory controller32can dynamically adjust a power supply of each memory chip based on a working status of the memory chip, thereby helping to reduce power consumption of the memory chip.

2. Repeated Memory Training

After memory initialization is completed, the first processor core31may further invoke the second processor core321to perform memory training.

The second processor core321-1inFIG.5is used as an example. As time elapses, a delay of some of signals in the memory channel1is offset, and as a result, a time sequence in the memory channel1is offset. This affects memory read/write stability.

In view of this, the first processor core31may invoke the second processor core321to periodically repeat memory training, to keep comparatively accurate alignment of the time sequence in the memory channel1, thereby helping to improve memory read/write stability.

3. Troubleshooting

After memory initialization is completed, the first processor core31may further invoke the second processor core321to perform troubleshooting on the memory controller32. For example, when the memory controller32is faulty, the second processor core321may determine a faulty node in the memory controller32, and feed back location information of the faulty node to the first processor core31.

The second processor core321-1inFIG.5is used as an example. When the memory channel1is faulty, the second processor core321-1may determine a faulty node in the memory channel1, and report location information of the faulty node to the first processor core31.

4. Firmware Upgrade

In an embodiment of this application, the first processor core31may further update firmware of each second processor core, to update a function of the second processor core. For example, the firmware of the second processor core321-1includes the foregoing invocation information used to implement memory initialization. The invocation information may be updated by upgrading the firmware of the second processor core321-1. For example, the instruction in the invocation information may be increased, decreased, or modified, so as to implement expansion and flexible configuration of memory initialization.

For another example, the firmware of the second processor core321-1may further include expansion information used to add a function other than memory initialization to the second processor core, and the invocation information may be updated by upgrading the firmware of the second processor core321-1, to optimize the extended function of the second processor core321-1. The extended function may be a function such as troubleshooting and power management described above. Upgrading the firmware of the second processor core321-1can add a new extended function to the second processor core321-1, and can also optimize an existing extended function of the second processor core321-1.

It can be learned that, in this embodiment of this application, adding the second processor core to the memory controller32not only helps to shorten memory initialization duration, but also can implement function expansion and optimization for the memory controller without modifying a hardware architecture, so that the memory controller can flexibly adapt to different application requirements.

Based on a same technical idea, an embodiment of this application provides a memory initialization method. The method may be applied to the memory initialization apparatus provided in the foregoing embodiment. For example, during the memory initialization method provided in this embodiment of this application, a first processor core invokes at least one second processor core in a memory controller to perform memory initialization.

For example, the memory controller further includes at least one memory channel, and each memory channel is configured to connect to at least one memory chip. When invoking the at least one second processor core, the first processor core may invoke the at least one second processor core to perform channel initialization on the at least one memory channel in the memory controller. Memory initialization includes channel initialization. For example, channel initialization may include memory training and/or memory testing. For example, in S903to S911inFIG.9, the first processor core may invoke the second processor core to perform memory training, and/or invoke the second processor core to perform memory testing.

For example, the at least one second processor core in the memory controller may be correspondingly connected to the at least one memory channel. For example, the connection may be a one-to-one connection, a one-to-many connection, or a many-to-one connection.

Generally, in a memory initialization process, system configuration, such as memory interleaving configuration, NUMA setting, and memory map resource management, further needs to be performed on the memory controller. In view of this, as shown in S912to S914inFIG.9, after channel initialization is completed for each memory channel in the memory controller, the first processor core performs system configuration on the memory controller32and a memory chip connected to the at least one memory channel, to generate management information. The management information may be used by the first processor core to manage the memory chip connected to the at least one memory channel.

It can be understood that, because the at least one second processor core in the memory controller can perform channel initialization in place of the first processor core in this embodiment of this application, a time of the first processor core can be released, so that the first processor core can initialize another component in parallel while the at least one second processor core is performing channel initialization. For example, after channel initialization is completed for any memory channel, the first processor core may further initialize another component by using the any memory channel for which channel initialization is completed and at least one memory chip connected to the any memory channel.

In an embodiment, as shown in S901and S902inFIG.9, after initialization configuration is completed for a first memory channel and at least one first memory chip connected to the first memory channel, the first processor core may invoke a second processor core correspondingly connected to the first memory channel. The first memory channel may be any one of the at least one memory channel in the memory controller.

In an embodiment of this application, the first processor core may first complete initialization configuration for all of the at least one memory channel in the memory controller, and then invoke the at least one second processor core together; or the first processor core may perform initialization configuration and invoke the second processor core in parallel. Details are as follows:

After invoking the second processor core correspondingly connected to the first memory channel, the first processor core may continue to perform initialization configuration on a second memory channel and at least one second memory chip connected to the second memory channel. The second memory channel is any memory channel for which channel initialization is not started in the at least one memory channel.

To allow the first processor core to invoke the at least one second processor core, in an embodiment, the memory controller may further include at least one storage circuit, and the at least one storage circuit may be correspondingly connected to the at least one second processor core in the memory controller.

When the first processor core invokes any second processor core, the first processor core may write invocation information to a storage circuit correspondingly connected to the any second processor core. The any second processor core may read the invocation information from the correspondingly connected storage circuit, and execute the invocation information. For example, the storage circuit may include any one or more of a register and/or a static random access memory.

In an embodiment, after the first processor core writes the invocation information to the storage circuit correspondingly connected to the any second processor core, the first processor core may further write reset deassertion information to the storage circuit. After reading the reset deassertion information, the any second processor core may read the invocation information from the correspondingly connected storage circuit, and execute the invocation information.

To implement more flexible invocation, in an embodiment, the invocation information may include at least one instruction, and the first processor core may invoke, by using an instruction sequence number, the any second processor core to execute an instruction corresponding to the instruction sequence number.

Running of some of instructions further requires a specific execution parameter. Therefore, the first processor core may further first write an execution parameter corresponding to the instruction to the storage circuit correspondingly connected to the any second processor core, and then invoke, by using the instruction sequence number, the any second processor core to execute the instruction corresponding to the instruction sequence number.

In an embodiment, the any second processor core may further feed back an instruction execution result to the first processor core.

Generally, firmware of the any second processor core is stored in a nonvolatile memory and can be updated, and the firmware includes the invocation information.

Generally, before writing the invocation information to the storage circuit correspondingly connected to the any second processor core, the first processor core may further allocate a communication address to the storage circuit. The first processor core may read data from or write data to the storage circuit based on the communication address.

It should be noted that the memory initialization method provided in this embodiment of this application not only helps to shorten memory initialization duration, but also facilitates function expansion for the memory controller, so that the memory controller can flexibly adapt to different application requirements. Examples are provided below:

1. Power Management

After memory initialization is completed, the first processor core may further invoke the second processor core correspondingly connected to the first memory channel, to manage output power of a power supply. The first memory channel may be any memory channel in the memory controller, and the power supply may supply power to the at least one first memory chip correspondingly connected to the first memory channel. The second processor core correspondingly connected to the first memory channel may monitor a working status of the at least one first memory chip. In addition, the second processor core correspondingly connected to the first memory channel adjusts the output power of the power supply based on the working status of the at least one first memory chip.

2. Repeated Memory Training

After memory initialization is completed, the first processor core may further invoke the at least one second processor core in the memory controller to perform memory training.

3. Troubleshooting

After memory initialization is completed, the first processor core may further invoke the at least one second processor core in the memory controller to perform troubleshooting. When the memory controller is faulty, the at least one second processor core may determine a faulty node in the memory controller, and feed back location information of the faulty node to the first processor core.

4. Firmware Upgrade

In an embodiment of this application, the first processor core may further update firmware of each second processor core, to update a function of the second processor core. For example, the firmware of the second processor core includes information used to add an extended function to the second processor core. The firmware of the second processor core may be updated, so that the second processor core can implement more functions, such as troubleshooting and power management described above. In addition, an existing function of the second processor core may also be optimized by updating the firmware of the second processor core.

For another example, the firmware of the second processor core includes the invocation information used to implement memory initialization. Further, the firmware of the second processor core may be updated to optimize operations performed by the second processor core in a memory initialization process. For example, some instructions are added or removed. For another example, initialization operations corresponding to some instructions are modified.

After the first processor core is powered on, the first processor core may write the updated firmware of the second processor core to the memory of the second processor core, so as to complete firmware upgrade of the second processor core.

It can be learned that, in an embodiment of this application, adding the second processor core to the memory controller not only helps to shorten memory initialization duration, but also can implement function expansion and optimization for the memory controller without modifying a hardware architecture, so that the memory controller can flexibly adapt to different application requirements.

Based on a same technical idea, an embodiment of this application further provides a computer system. The computer system may include the memory initialization apparatus provided in any one of the foregoing embodiments, and a memory chip coupled to the memory initialization apparatus. For example, the computer system may be a computer mainboard, or may be an electronic device such as a notebook computer, a mobile phone, or a digital camera. This is not limited in this embodiment of this application.

A person skilled in the art should understand that the embodiments of this application may be provided as a method, a system, or a computer program product. Therefore, the present application may use a form of hardware only embodiments, or embodiments with a combination of software and hardware. Moreover, this application may use a form of a computer program product that is implemented on one or more computer-usable storage media (including but not limited to a magnetic disk memory, a CD-ROM, an optical memory, and the like) that include computer-usable program code.

This application is described with reference to the flowcharts and/or block diagrams of the method, the device (or system), and the computer program product according to this application. It should be understood that computer program instructions may be used to implement each process and/or each block in the flowcharts and/or the block diagrams and a combination of processes and/or blocks in the flowcharts and/or the block diagrams. These computer program instructions may be provided for a general-purpose computer, a dedicated computer, an embedded processor, or a processor of any other programmable data processing device to generate a machine, so that the instructions executed by a computer or a processor of any other programmable data processing device generate an apparatus for implementing a specific function in one or more processes in the flowcharts and/or in one or more blocks in the block diagrams.

These computer program instructions may be stored in a computer readable memory that can instruct the computer or any other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory generate an artifact that includes an instruction apparatus. The instruction apparatus implements a specific function in one or more processes in the flowcharts and/or in one or more blocks in the block diagrams.

These computer program instructions may be loaded onto a computer or another programmable data processing device, so that a series of operations and operations are performed on the computer or the other programmable device, thereby generating computer-implemented processing. Therefore, the instructions executed on the computer or the other programmable device provide operations for implementing a specific function in one or more processes in the flowcharts and/or in one or more blocks in the block diagrams.

Definitely, a person skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. This application is intended to cover these modifications and variations of this application provided that the modifications and variations fall within the scope of protection defined by the following claims and their equivalent technologies.