Patent ID: 12243909

DETAILED DESCRIPTION

It is understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments, in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the sake of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, various features may be arbitrarily drawn in different scales for the sake of simplicity and clarity.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Still further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range including the number described, such as within +/−10% of the number described or other values as understood by person skilled in the art. For example, the term “about 5 nm” encompasses the dimension range from 4.5 nm to 5.5 nm.

Metal-Insulator-Metal (MIM) capacitors have been widely used in functional circuits such as mixed signal circuits, analog circuits, Radio Frequency (RF) circuits, Dynamic Random Access Memories (DRAMs), embedded DRAMs, and logic operation circuits. In system-on-chip (SOC) applications, different capacitors for different functional circuits have to be integrated on a same chip to serve different purposes. For example, in mixed-signal circuits, capacitors are used as decoupling capacitors and high-frequency noise filters. For DRAM and embedded DRAM circuits, capacitors are used for memory storage, while for RF circuits, capacitors are used in oscillators and phase-shift networks for coupling and/or bypassing purposes. For microprocessors, capacitors are used for decoupling. As its name suggests, an MIM capacitor includes a sandwich structure of interleaving metal layers and insulator layers (i.e., dielectric layers). An example MIM capacitor includes a bottom conductor plate layer, a middle conductor plate layer over the bottom conductor plate layer, and a top conductor plate layer over the middle conductor plate, each of which is insulated from an adjacent conductor plate layer by a dielectric layer. As an MIM capacitor is fabricated in a BEOL structure to have a larger surface area, its conductor plate layers extend over multiple contact features. Contact vias may be formed through the conductor plate layers to electrically couple the contact features to one or more of the conductor plate layers. The contact vias may be electrically coupled to contact pads for connection to external circuitry.

Performance and attributes of an MIM capacitor may be modeled using a parallel plate capacitor that includes a dielectric material sandwiched between two parallel electrode plates. A parallel plate capacitance of such a parallel plate capacitor may be expressed as: C=εr*ε0*A/d where εr is the dielectric constant of the dielectric material, ε0 is the dielectric constant of free space, A is the area of the parallel electrode plate, and d is the distance between the two parallel electrode plates. The capacitance of an MIM capacitor may thus be adjusted through an area of the conductor plates, the distance between conductor plates, and the dielectric constant of the dielectric layers between conductor plates. For application that requires frequent charging and discharging of an MIM capacitor, resistance of a series resistor also comes into play. A time constant (T) of a resistor-capacitor (RC) circuit that includes a series resistor having a series resistance (Rs) and a capacitor (C) may be expressed as: T=Rs*C. The time constant (T) represents the theoretical time to charge the capacitor to 63% of its total charge. For an MIM capacitor, resistance of its conductor plate layers is factored into the series resistance. When conductor plate layers of an MIM capacitor have lower resistance, the MIM capacitor has a smaller time constant, making it more suitable for high-frequency applications.

It follows that, in order to lower the time constant of an MIM capacitor, its conductor plate layers should be as electrically conductive as possible. Besides conductivity, there are other considerations. For example, each of the conductor plate layers should have good adhesion with adjacent dielectric materials that come in contact with it and is unlikely to be oxidized due to direct contact with these adjacent dielectric materials. Due to the foregoing considerations, metal nitrides, such as titanium nitride or tantalum nitride, have been used to form conductor plate layers. Metal nitrides adhere well to dielectric materials and are not susceptible to oxidation due to direct contact with oxygen-containing dielectric materials, such as silicon oxide. When it comes to conductivity, metal nitrides are conductive but not as conductive as metals.

The present disclosure provides a method and a semiconductor device to reduce the time constant of an MIM capacitor while maintaining the integrity of the conductor plate layers. In some embodiments, an MIM capacitor according to the present disclosure has multiple conductor plate layers and each of the conductor plate layers is a multilayer that includes at least a metal nitride layer and metal layer. In one embodiment, each of the conductor plate layers includes a metal layer sandwiched between a bottom metal nitride layer and a top metal nitride layer. The bottom and top metal nitride layers provide an oxygen atom barrier and the metal layer provides the desired conductivity. Processes of the present disclosure form the metal layer and metal nitride layer use the same metal target, such as titanium target or tantalum target. Due to the reduced time constant, MIM capacitors of the present disclosure are suitable high-frequency applications where MIM capacitors are frequently charged and discharged.

The various aspects of the present disclosure will now be described in more detail with reference to the figures. In that regard,FIG.1is a flowchart illustrating a method100for fabricating a semiconductor device according to embodiments of the present disclosure. The method100is merely an example and is not intended to limit the present disclosure to what is explicitly illustrated in the method100. Additional steps can be provided before, during, and after the method100, and some steps described can be replaced, eliminated, or moved around for additional embodiments of the method. Not all steps are described herein in detail for reasons of simplicity. The method100is described below in conjunction withFIGS.2-13, which are fragmentary cross-sectional views of a workpiece at different stages of fabrication according to embodiments of the present disclosure.

Referring toFIGS.1and2, method100includes a block102where a workpiece200is provided. The workpiece200includes various layers already formed thereon. Because a semiconductor device will be formed from the workpiece200, workpiece200may be referred to as semiconductor device200as the context requires. The workpiece200includes a substrate202, which may be made of silicon or other semiconductor materials such as germanium. The substrate202also may include a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, or indium phosphide. In some embodiments, the substrate202may include alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, the substrate202may include an epitaxial layer, for example an epitaxial layer overlying a bulk semiconductor. The substrate202may also be a silicon-on-insulator (SOI) substrate that includes an insulator layer. Various microelectronic components may be formed in or on the substrate202, such as transistor components including source/drain features, gate structures, gate spacers, source/drain contacts, gate contacts, isolation structures including shallow trench isolation (STI), or any other suitable components.

The workpiece200also includes an interconnect layer210. The interconnect layer210may be one of the interconnect layers in a multi-layered interconnect (MLI) structure, which is formed over the substrate202and may include multiple patterned dielectric layers and conductive layers that provide interconnections (e.g., wiring) between the various microelectronic components of the workpiece200. There may be intermediate layers or components between the interconnect layer210and the substrate202, but in the interest of simplicity such layers or components are not shown. In an embodiment, the interconnect layer210is about 169 to about 230 nanometers (nm) thick.

The interconnect layer210may include multiple conductive components as well as an interlayer dielectric (ILD) component that partially or fully surrounds the conductive components. The conductive components may include contacts, vias, or metal lines. The ILD component may be a silicon oxide or silicon oxide containing material where silicon exists in various suitable forms. As an example, the ILD component includes silicon oxide or a low-k dielectric material whose k-value (dielectric constant) is smaller than that of silicon oxide, which is about 4. In some embodiments, the low-k dielectric material includes a porous organosilicate thin film such as SiOCH, tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, silicon carbon nitride (SiCN), silicon oxycarbide (SiOCN), spin-on silicon based polymeric dielectrics, or combinations thereof.

The workpiece200may include a carbide layer220disposed on the interconnect layer210, an oxide layer230disposed on the carbide layer, an etch stop layer (ESL)240disposed over the oxide layer230. In some embodiments, the carbide layer220has a generally uniform thickness of between about 45 nm and about 70 nm. Any suitable type of carbide material such as silicon carbide (SiC) can be used in the carbide layer220. In some embodiments, the oxide layer230may include silicon oxide. In an embodiment, the interconnect layer210, the carbide layer220and the oxide layer230may be replaced with one or more interconnect structures. In some embodiments, the ESL240is about 45 nm to about 55 nm thick. The ESL240may include silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon carbide (SiC), silicon oxycarbonitride (SiOCN), or silicon nitride (SiN), or combinations thereof.

As shown inFIG.1, the workpiece200includes contact features253,254and255in a first dielectric layer250disposed on the ESL240. In some embodiments, the first dielectric layer250may be an undoped silica glass (USG) layer and may include silicon oxide. In some implementations, the first dielectric layer250is about 800 to about 1000 nm thick. The contact features253,254and255are surrounded by or embedded in the first dielectric layer250. The contact features253,254, and255are sometimes referred to as top metal (TM) contacts because they may reside above transistor features (not shown in figures herein) to interface the MIM structure. Each of the contact features253,254, and255may include a barrier layer251and a metal fill layer252. In some embodiments, the barrier layer251includes titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof. In some embodiments, the metal fill layer252includes a metal or metal alloy such as copper (Cu), cobalt (Co), nickel (Ni), aluminum (Al), tungsten (W), titanium (Ti), or combinations thereof.

Referring toFIGS.1and3, method100includes a block104where a first insulation layer258is deposited over the workpiece200. The first insulation layer258may include silicon oxide and may be an undoped silica glass (USG) layer. In some embodiments, the first insulation layer258may be deposited using chemical vapor deposition (CVD) or subatmospheric CVD (SACVD). The first insulation layer258may have a thickness between about 400 nm and about 500 nm. In some implementations illustrated inFIG.3, the workpiece200may further include a capping layer256between the contact features253,254and255and the first insulation layer258and between the first dielectric layer250and the first insulation layer258. In some embodiments, the capping layer256may include silicon carbonitride (SiCN) or silicon nitride (SiN). The capping layer256may be deposited using CVD and may be formed to a thickness between about 65 and about 85 nm. The capping layer256protects the contact features253,254, and255from being oxidized.

Referring toFIGS.1and4, method100includes a block106where a bottom conductor plate layer262is formed over the first insulation layer258. In some embodiments shown inFIG.4, the bottom conductor plate layer262is a multilayer that includes multiple sublayers, including a first metal nitride layer262-1, a first metal layer262-2over the first metal nitride layer262-1, and a second metal nitride layer262-3over the first metal layer262-2. The first metal nitride layer262-1, the first metal layer262-2and the second metal nitride layer262-3may be formed using physical vapor deposition (PVD). In some implementations, the first metal nitride layer262-1, the first metal layer262-2and the second metal nitride layer262-3include the same metal component, allowing them to be formed in-situ in the same PVD process chamber. In one example, the first metal layer262-2is formed of titanium (Ti) while the first metal nitride layer262-1and the second metal nitride layer262-3are formed of titanium nitride (TiN). In this example, the first metal nitride layer262-1, the first metal layer262-2and the second metal nitride layer262-3may be deposited in the same PVD process chamber that includes a titanium (Ti) target. In another example, the first metal layer262-2is formed of tantalum (Ta) while the first metal nitride layer262-1and the second metal nitride layer262-3are formed of tantalum nitride (TaN). In this example, the first metal nitride layer262-1, the first metal layer262-2and the second metal nitride layer262-3may be deposited in the same PVD process chamber that includes a tantalum (Ta) target.

The formation of the bottom conductor plate layer262may include deposition of the first metal nitride layer262-1, deposition of the first metal layer262-2, deposition of the second metal nitride layer262-3, and patterning of the bottom conductor plate layer262. The deposition of the first metal nitride layer262-1may be performed using a PVD process that includes a metal target, such as a titanium (Ti) target or a tantalum target (Ta), and a nitrogen-containing gas, such as ammonia (NH3). The deposition of the first metal layer262-2may be performed using a PVD process that includes a metal target, such as a titanium (Ti) target or a tantalum target (Ta), and an inert gas, such as argon (Ar). The deposition of the second metal nitride layer262-3may be performed using a PVD process that includes a metal target, such as a titanium (Ti) target or a tantalum target (Ta), and a nitrogen-containing gas, such as ammonia (NH3). The deposited first metal nitride layer262-1, first metal layer262-2and second metal nitride layer262-3constitute a multilayer and are then patterned by photolithography and etch processes. Although not explicitly shown inFIG.4, after the patterning of the bottom conductor plate layer262, sidewalls of the bottom conductor plate layer262may be treated using nitrous oxide (N2O) gas for passivation.

As shown inFIG.4, the bottom conductor plate layer262has a total thickness TT, the first metal nitride layer262-1has a first thickness T1, the first metal layer262-2has a second thickness T2, and the second metal nitride layer262-3has a third thickness T3. The total thickness TT is the sum of the first thickness T1, the second thickness T2and the third thickness T3. The first metal layer262-2is more conductive than the first metal nitride layer262-1and the second metal nitride layer262-3. For example, when the first metal layer262-2is formed of titanium (Ti) and the first metal nitride layer262-1and the second metal nitride layer262-3are formed of titanium nitride (TiN), titanium (Ti) is about three times as conductive as titanium nitride (TiN). When the first metal layer262-2is formed of tantalum (Ta) and the first metal nitride layer262-1and the second metal nitride layer262-3are formed of tantalum nitride (TaN), tantalum (Ta) is about 5 times as conductive as tantalum nitride (TaN). Because the first metal layer262-2is more conductive than the first metal nitride layer262-1and the second metal nitride layer262-3, the present disclosure maximizes the second thickness T2of the first metal layer262-2while minimizing the first thickness T1and the third thickness T3to reduce series resistance (Rs) attributable to the bottom conductor plate layer262. According to the present disclosure, the first metal nitride layer262-1and the second metal nitride layer262-3serve as conductive barrier layers to prevent oxygen from diffusing from adjacent dielectric layers, such as the first insulation layer258and the second dielectric layer264(shown inFIG.5), into the first metal layer262-2. In addition, the second metal nitride layer262-3protects the first metal layer262-2from being damaged or oxidized by plasma species generated during deposition of the second dielectric layer264(shown inFIG.5). To adequately serve the conductive barrier functions, the first metal nitride layer262-1the second metal nitride layer262-3may not be too thin. In some instances, each of the first thickness T1and the third thickness T3may be between about 20 Å and about 40 Å. The total thickness TT of the bottom conductor plate layer262may be between about 350 Å and about 800 Å. The second thickness T2may be between about 270 Å and about 760 Å.

In some alternative implementations, the first metal nitride layer262-1, the first metal layer262-2and the second metal nitride layer262-3include the different metal components and are formed in different PVD process chambers. In these alternative implementations, the first metal nitride layer262-1and the second metal nitride layer262-3may be formed of titanium nitride (TiN) or tantalum nitride (TaN) while the first metal layer262-2may include copper (Cu), cobalt (Co), nickel (Ni), aluminum (Al), tungsten (W), tantalum (Ta), platinum (Pt), molybdenum (Mo), ruthenium (Ru), titanium (Ti), or any suitable metal that is more conductive than metal nitrides (e.g., titanium nitride or tantalum nitride). These alternative implementations may require moving the workpiece200in and out of at least two PVD process chambers. In an example when the first metal nitride layer262-1and the second metal nitride layer262-3are formed of titanium nitride (TiN) and the second metal layer262-2is formed of tungsten (W), the workpiece200is first placed in a first PVD chamber that includess a titanium (Ti) target and is in fluid communication with an ammonia (NH3) source to form the first metal nitride layer262-1. The workpiece200is then removed from the first PVD chamber and placed in a second PVD chamber that includes a tungsten (W) target and is in fluid communication with an inert gas source to form the first metal layer262-2. Subsequently, the workpiece200is then removed from the second PVD chamber and placed again in the first PVD chamber to form the second metal nitride layer262-3.

Referring toFIGS.1and5, method100includes a block108where a second dielectric layer264is deposited over the bottom conductor plate layer262. In some embodiments, to increase capacitance of the resulting MIM capacitor, the second dielectric layer264may include high-k dielectric material(s) whose k-value is greater than that of silicon oxide, which is about 3.9. In some instances, the second dielectric layer264may include hafnium oxide, zirconium oxide (ZrO2), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), or a combination thereof. The second dielectric layer264may be formed using CVD, metalorganic CVD (MOCVD), or atomic layer deposition (ALD). In some implementations, the second dielectric layer264may be deposited to have a generally uniform thickness over first insulation layer258and the bottom conductor plate layer262. In some instances, the second dielectric layer264may have a thickness between about 50 nm and about 70 nm.

Referring toFIGS.1and6, method100includes a block110where a middle conductor plate layer266over the second dielectric layer264. In some embodiments shown inFIG.6, the middle conductor plate layer266is a multilayer that includes multiple sublayers, including a third metal nitride layer266-1, a second metal layer266-2over the third metal nitride layer266-1, and a fourth metal nitride layer266-3over the second metal layer266-2. The third metal nitride layer266-1, the second metal layer266-2and the fourth metal nitride layer266-3may be formed using PVD. In some implementations, the third metal nitride layer266-1, the second metal layer266-2and the fourth metal nitride layer266-3include the same metal component, allowing them to be formed in-situ in the same PVD process chamber. In one example, the second metal layer266-2is formed of titanium (Ti) while the third metal nitride layer266-1and the fourth metal nitride layer266-3are formed of titanium nitride (TiN). In this example, the third metal nitride layer266-1, the second metal layer266-2and the fourth metal nitride layer266-3may be deposited in the same PVD process chamber that includes a titanium (Ti) target. In another example, the second metal layer266-2is formed of tantalum (Ta) while the third metal nitride layer266-1and the fourth metal nitride layer266-3are formed of tantalum nitride (TaN). In this example, the third metal nitride layer266-1, the second metal layer266-2and the fourth metal nitride layer266-3may be deposited in the same PVD process chamber that includes a tantalum (Ta) target.

The formation of the middle conductor plate layer266may include deposition of the third metal nitride layer266-1, deposition of the second metal layer266-2, deposition of the fourth metal nitride layer266-3over the second metal layer266-2, and patterning of the middle conductor plate layer266. The deposition of the third metal nitride layer266-1may be performed using a PVD process that includes a metal target, such as a titanium (Ti) target or a tantalum target (Ta), and a nitrogen-containing gas, such as ammonia (NH3). The deposition of the second metal layer266-2may be performed using a PVD process that includes a metal target, such as a titanium (Ti) target or a tantalum target (Ta), and an inert gas, such as argon (Ar). The deposition of the fourth metal nitride layer266-3may be performed using a PVD process that includes a metal target, such as a titanium (Ti) target or a tantalum target (Ta), and a nitrogen-containing gas, such as ammonia (NH3). The deposited third metal nitride layer266-1, second metal layer266-2and fourth metal nitride layer266-3constitute a multilayer and are then patterned by photolithography and etch processes. Although not explicitly shown inFIG.5, after the patterning of the middle conductor plate layer266, sidewalls of the middle conductor plate layer266may be treated using nitrous oxide (N2O) gas for passivation.

As shown inFIG.6, like the bottom conductor plate layer262, the middle conductor plate layer266has the total thickness TT, the third metal nitride layer266-1has the first thickness T1, the second metal layer266-2has the second thickness T2, and the fourth metal nitride layer266-3has the third thickness T3. The total thickness TT is the sum of the first thickness T1, the second thickness T2and the third thickness T3. The second metal layer266-2is more conductive than the third metal nitride layer266-1and the fourth metal nitride layer266-3. For example, when the second metal layer266-2is formed of titanium (Ti) and the third metal nitride layer266-1and the fourth metal nitride layer266-3are formed of titanium nitride (TiN), titanium (Ti) is about three times as conductive as titanium nitride (TiN). When the second metal layer266-2is formed of tantalum (Ta), and the third metal nitride layer266-1and the fourth metal nitride layer266-3are formed of tantalum nitride (TaN), tantalum (Ta) is about 5 times as conductive as tantalum nitride (TaN). Because the second metal layer266-2is more conductive than the third metal nitride layer266-1and the fourth metal nitride layer266-3, the present disclosure maximizes the second thickness T2of the second metal layer266-2while minimizing the first thickness T1and the third thickness T3to reduce series resistance (Rs) attributable to the middle conductor plate layer266. According to the present disclosure, the third metal nitride layer266-1and the fourth metal nitride layer266-3serve as conductive barrier layers to prevent oxygen from diffusing from adjacent dielectric layers, such as the second dielectric layer264and the third dielectric layer268(shown inFIG.7), into the second metal layer266-2. In addition, the fourth metal nitride layer266-3protects the second metal layer266-2from being damaged or oxidized by plasma species generated during deposition of the second dielectric layer264(shown inFIG.5). To adequately serve the conductive barrier functions, the third metal nitride layer266-1the fourth metal nitride layer266-3may not be too thin. In some instances, each of the first thickness T1and the third thickness T3may be between about 20 Å and about 40 Å. The total thickness TT of the middle conductor plate layer266may be between about 350 Å and about 800 Å. The second thickness T2may be between about 270 Å and about 760 Å.

In some alternative implementations, the third metal nitride layer266-1, the second metal layer266-2and the fourth metal nitride layer266-3include the different metal components and are formed in different PVD process chambers. In these alternative implementations, the third metal nitride layer266-1and the fourth metal nitride layer266-3may be formed of titanium nitride (TiN) or tantalum nitride (TaN) while the second metal layer266-2may include copper (Cu), cobalt (Co), nickel (Ni), aluminum (Al), tungsten (W), tantalum (Ta), platinum (Pt), molybdenum (Mo), ruthenium (Ru), titanium (Ti), or any suitable metal that is more conductive than metal nitrides. As described above, these alternative implementations may require moving the workpiece200in and out of at least two PVD process chambers.

Referring toFIGS.1and7, method100includes a block112where a third dielectric layer268is deposited over the middle conductor plate layer266. In some embodiments, to increase capacitance of the resulting MIM capacitor, the third dielectric layer268may include high-k dielectric material(s) whose k-value is greater than that of silicon oxide, which is about 3.9. In some instances, the third dielectric layer268may include hafnium oxide, zirconium oxide (ZrO2), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), or a combination thereof. The second dielectric layer264may be formed using CVD, metalorganic CVD (MOCVD), or atomic layer deposition (ALD). In some implementations, the third dielectric layer268may be deposited to have a generally uniform thickness over second dielectric layer264and the middle conductor plate layer266. In some instances, the third dielectric layer268may have a thickness between about 50 nm and about 70 nm.

Referring toFIGS.1and8, method100includes a block114where a top conductor plate layer269is deposited over the third dielectric layer268. In some embodiments shown inFIG.8, the top conductor plate layer269is a multilayer that includes multiple sublayers, including a fifth metal nitride layer269-1, a third metal layer269-2over the fifth metal nitride layer269-1, and a sixth metal nitride layer269-3over the third metal layer269-2. The fifth metal nitride layer269-1, the third metal layer269-2and the sixth metal nitride layer269-3may be formed using PVD. In some implementations, the fifth metal nitride layer269-1, the third metal layer269-2and the sixth metal nitride layer269-3include the same metal component, allowing them to be formed in-situ in the same PVD process chamber. In one example, the third metal layer269-2is formed of titanium (Ti) while the fifth metal nitride layer269-1and the sixth metal nitride layer269-3are formed of titanium nitride (TiN). In this example, the fifth metal nitride layer269-1, the third metal layer269-2and the sixth metal nitride layer269-3may be deposited in the same PVD process chamber that includes a titanium (Ti) target. In another example, the third metal layer269-2is formed of tantalum (Ta) while the fifth metal nitride layer269-1and the sixth metal nitride layer269-3are formed of tantalum nitride (TaN). In this example, the fifth metal nitride layer269-1, the third metal layer269-2and the sixth metal nitride layer269-3may be deposited in the same PVD process chamber that includes a tantalum (Ta) target.

The formation of the top conductor plate layer269may include deposition of the fifth metal nitride layer269-1, deposition of the third metal layer269-2, deposition of the sixth metal nitride layer269-3over the third metal layer269-2, and patterning of the top conductor plate layer269. The deposition of the fifth metal nitride layer269-1may be performed using a PVD process that includes a metal target, such as a titanium (Ti) target or a tantalum target (Ta), and a nitrogen-containing gas, such as ammonia (NH3). The deposition of the third metal layer269-2may be performed using a PVD process that includes a metal target, such as a titanium (Ti) target or a tantalum target (Ta), and an inert gas, such as argon (Ar). The deposition of the sixth metal nitride layer269-3may be performed using a PVD process that includes a metal target, such as a titanium (Ti) target or a tantalum target (Ta), and a nitrogen-containing gas, such as ammonia (NH3). The deposited fifth metal nitride layer269-1, third metal layer269-2and sixth metal nitride layer269-3constitute a multilayer and are then patterned by photolithography and etch processes. Although not explicitly shown inFIG.8, after the patterning of the top conductor plate layer269, sidewalls of the top conductor plate layer269may be treated using nitrous oxide (N2O) gas for passivation.

As shown inFIG.8, like the bottom conductor plate layer262, the top conductor plate layer269has the total thickness TT, the fifth metal nitride layer269-1has the first thickness T1, the third metal layer269-2has the second thickness T2, and the sixth metal nitride layer269-3has the third thickness T3. The total thickness TT is the sum of the first thickness T1, the second thickness T2and the third thickness T3. The third metal layer269-2is more conductive than the fifth metal nitride layer269-1and the sixth metal nitride layer269-3. For example, when the third metal layer269-2is formed of titanium (Ti) and the fifth metal nitride layer269-1and the sixth metal nitride layer269-3are formed of titanium nitride (TiN), titanium (Ti) is about three times as conductive as titanium nitride (TiN). When the third metal layer269-2is formed of tantalum (Ta) and the fifth metal nitride layer269-1and the sixth metal nitride layer269-3are formed of tantalum nitride (TaN), tantalum (Ta) is about 5 times as conductive as tantalum nitride (TaN). Because the third metal layer269-2is more conductive than the fifth metal nitride layer269-1and the sixth metal nitride layer269-3, the present disclosure maximizes the second thickness T2of the third metal layer269-2while minimizing the first thickness T1and the third thickness T3to reduce series resistance (Rs) attributable to the top conductor plate layer269. According to the present disclosure, the fifth metal nitride layer269-1and the sixth metal nitride layer269-3serve as conductive barrier layers to prevent oxygen from diffusing from adjacent dielectric layers, such as the third dielectric layer268and the second insulation layer267(shown inFIG.9), into the third metal layer269-2. In addition, the sixth metal nitride layer269-3protects the third metal layer269-2from being damaged or oxidized by plasma species generated during deposition of the second insulation layer267(shown inFIG.9). To adequately serve the conductive barrier functions, the fifth metal nitride layer269-1the sixth metal nitride layer269-3may not be too thin. In some instances, each of the first thickness T1and the third thickness T3may be between about 20 Å and about 40 Å. The total thickness TT of the top conductor plate layer269may be between about 350 Å and about 800 Å. The second thickness T2may be between about 270 Å and about 760 Å.

In some alternative implementations, the fifth metal nitride layer269-1, the third metal layer269-2and the sixth metal nitride layer269-3include the different metal components and are formed in different PVD process chambers. In these alternative implementations, the fifth metal nitride layer269-1and the sixth metal nitride layer269-3may be formed of titanium nitride (TiN) or tantalum nitride (TaN) while the third metal layer269-2may include copper (Cu), cobalt (Co), nickel (Ni), aluminum (Al), tungsten (W), tantalum (Ta), platinum (Pt), molybdenum (Mo), ruthenium (Ru), titanium (Ti), or any suitable metal that is more conductive than metal nitrides. As described above, these alternative implementations may require moving the workpiece200in and out of at least two PVD process chambers.

At the conclusion of the operations at block114, an MIM structure260is formed. The MIM structure260includes the bottom conductor plate layer262, the second dielectric layer264, the middle conductor plate layer266, the third dielectric layer268, and the top conductor plate layer269. The MIM structure260may also be referred to as an MIM capacitor260.

Referring toFIGS.1and9, method100includes a block116where a second insulation layer267is deposited over the top conductor plate layer269. In some embodiments, the second insulation layer267may be an undoped silica glass (USG) layer and may include silicon oxide. In some embodiments, the second insulation layer267may be about 400 nm to about 500 nm thick. In some embodiments, the second insulation layer267is formed by blanketly depositing about 900 to about 1000 nm thick of the oxide material (e.g., USG) to cover the topography of the MIM structure260, followed by a chemical mechanical polishing (CMP) process to reach the final thickness of the second insulation layer267. The deposition of the second insulation layer267may be performing using CVD or SACVD. As shown inFIG.9, the MIM structure260is sandwiched between the first insulation layer258and the second insulation layer267, which may have the same material and/or the same thickness.

Referring toFIGS.1,10and11, method100includes a block118where conductive features275,276and277are formed. As shown inFIGS.10and11, block118includes formation of openings through the second insulation layer267, the MIM structure260, and the first insulation layer258and deposition of barrier layers and metal fill layers to form the conductive features in the openings. Referring toFIG.10, one or more openings (such as openings271,272, and273) are formed to penetrate through, from top to bottom, the second insulation layer267, the MIM structure260, the first insulation layer258, and the capping layer256. The openings271,272, and273expose top surfaces of the contact features253,254, and255, respectively. In some embodiments, a dry etching process is performed to form the openings271,272, and273. Depending on the application, the sidewall of each opening may expose different conductor plate layers of the MIM structure260. As illustrated inFIG.10, the opening271exposes sidewalls of the middle conductor plate layer266and the top conductor plate layer269. The opening272exposes sidewalls of the top conductor plate layer269and the middle conductor plate layer266. The opening273exposes sidewalls of the top conductor plate layer269and the bottom conductor plate layer262.

Referring toFIG.11, one or more conductive features (such as275,276, and277) are formed in and over the openings271,272, and273, respectively. The conductive features275,276, and277include contact vias that fill the openings271,272and273and may be referred to as contact via, metal vias, or metal lines. In some embodiments, to form the one or more conductive features (such as275,276and277), a barrier layer278is first conformally deposited over the second insulation layer267and into the openings271,272and273using a suitable deposition technique, such as atomic layer deposition (ALD), physical vapor deposition (PVD) or chemical vapor deposition (CVD) and then a metal fill layer is deposited over the barrier layer278using a suitable deposition technique, such as ALD, PVD or ALD. The deposited barrier layer278and the metal fill layer are then patterned to form conductive features275,276and277, as illustrated in the example inFIG.11. In some embodiments, the barrier layer278may include titanium nitride (TiN), tantalum nitride (TaN), or tantalum (Ta) and the metal fill layer may include copper (Cu), cobalt (Co), nickel (Ni), aluminum (Al), tungsten (W), titanium (Ti), or combinations thereof.

Referring toFIGS.1and12, method100includes a block120where passivation layers are deposited the conductive features275,276and277. As shown inFIG.12, a first passivation layer280is deposited over the workpiece200, including over the conductive features275,276, and277and the second insulation layer267. In some embodiments, the first passivation layer280may include one or more plasma-enhanced CVD (PECVD) oxide layers, one or more undoped silica glass (USG) layers, or a combination thereof. The first passivation layer280may be formed using CVD, spin-on coating, or other suitable technique. In some implementations, the first passivation layer280may be formed to a thickness between about 1000 nm and about 1400 nm, including 1200 nm. A second passivation layer282is then deposited over the first passivation layer280. In some embodiments, the second passivation layer282may include silicon nitride (SiN) and may be formed by CVD, PVD or a suitable method to a thickness between about 600 nm and about 800 nm, including 700 nm.

Referring toFIGS.1and13, method100includes a block122where further processes are performed. Such further processes may include formation of the openings284through the first passivation layer280and the second passivation layer282, deposition of one or more polymeric material layers, patterning of the one or more polymeric material layers, deposition of an under-bump-metallurgy (or under-bump-metallization, UBM) layer, deposition of a copper-containing bump layer, deposition of a cap layer, deposition of a solder layer, and reflowing of the solder layer. These further processes form contact structures for connection to external circuitry.

Methods and semiconductor devices according to the present disclosure provide advantages. For example, an MIM capacitor according to present disclosure includes multilayer conductor plate layers. Each of the conductor plate layers includes a metal layer sandwiched between two metal nitride layers. The metal layer provides increased conductivity while the metal nitride layers protect the metal layer from being oxidized due to contact with oxygen-containing dielectric layers. The lower resistance of the multilayer conductor plate layers reduces the time constant of the MIM capacitor, making them suitable for high-frequency applications.

One aspect of the present disclosure involves a semiconductor device. The semiconductor device includes a contact feature in a first dielectric layer, a first passivation layer over the contact feature, a bottom conductor plate layer over the first passivation layer, the bottom conductor plate layer including a first plurality of sublayers, a second dielectric layer over the bottom conductor plate layer, a middle conductor plate layer over the second dielectric layer, the middle conductor plate layer including a second plurality of sublayers, a third dielectric layer over the middle conductor plate layer, a top conductor plate layer over the third dielectric layer, the top conductor plate layer including a third plurality of sublayers, and a second passivation layer over the top conductor plate layer.

In some embodiments, the first plurality of sublayers includes a first metal nitride layer, a first metal layer over the first metal nitride layer, and a second metal nitride layer over the first metal layer. The second plurality of sublayers includes a third metal nitride layer, a second metal layer over the third metal nitride layer, and a fourth metal nitride layer over the second metal layer. The third plurality of sublayers includes a fifth metal nitride layer, a third metal layer over the fifth metal nitride layer, and a sixth metal nitride layer over the third metal layer. In some implementations, the first metal nitride layer, the second metal nitride layer, the third metal nitride layer, the fourth metal nitride layer, the fifth metal nitride layer, and the sixth metal nitride layer include titanium nitride and the first metal layer, the second metal layer, and the third metal layer include titanium. In some instances, the first metal nitride layer, the second metal nitride layer, the third metal nitride layer, the fourth metal nitride layer, the fifth metal nitride layer, and the sixth metal nitride layer include tantalum nitride and the first metal layer, the second metal layer, and the third metal layer include tantalum. In some embodiments, the first metal nitride layer and the third metal nitride layer include a thickness between about 20 nm and about 40 nm. In some embodiments, the second dielectric layer and the third dielectric layer include hafnium oxide, zirconium oxide, tantalum oxide, or aluminum oxide. In some implementations, the semiconductor device may further include a conductive feature extending through the top conductor plate layer, the third dielectric layer, the second dielectric layer, the bottom conductor plate layer, and the first dielectric layer and the conductive feature electrically couples the top conductor plate layer and the bottom conductor plate layer to the conductive feature.

Another aspect of the present disclosure involves a metal-insulator-metal structure. The metal-insulator-metal structure includes a bottom conductor plate layer, a first dielectric layer over the bottom conductor plate layer, a middle conductor plate layer, a third dielectric layer over the middle conductor plate layer, and a top conductor plate layer over the third dielectric layer. Each of the bottom conductor plate layer, the middle conductor plate layer, and the top conductor plate layer includes a first conductive barrier layer, a second conductive barrier layer, and a metal layer.

In some embodiments, the metal layer is sandwiched between the first conductive barrier layer and the second conductive barrier layer. In some embodiments, a conductivity of the metal layer is greater than a conductivity of the first conductive barrier layer and the second conductive barrier layer. In some implementations, the first conductive barrier layer and the second conductive barrier layer include a first thickness and the metal layer includes a second thickness greater than the first thickness. In some instances, the first thickness is between about 20 nm and about 40 nm. In some embodiments, the first conductive barrier layer and the second conductive barrier layer include titanium nitride and the metal layer includes titanium. In some implementations, the first conductive barrier layer and the second conductive barrier layer include tantalum nitride and the metal layer includes tantalum.

Still another aspect of the present disclosure involves a method. The method includes providing a workpiece including a conductive feature, depositing a first insulation layer over the conductive feature, forming a multilayer bottom conductor plate layer over the first insulation layer, depositing a first dielectric layer over the multilayer bottom conductor plate layer, forming a multilayer middle conductor plate layer over the first dielectric layer, depositing a second dielectric layer over the multilayer middle conductor plate layer, forming a multilayer top conductor plate layer over the second dielectric layer, and depositing a second insulation layer over the multilayer top conductor plate layer.

In some embodiments, the forming of the multilayer bottom conductor plate layer includes depositing a first metal nitride layer over the first insulation layer, depositing a first metal layer over the first metal nitride layer, and depositing a second metal nitride layer over the first metal layer. In some implementations, the depositing of the first metal nitride layer, the depositing of the first metal layer, and the depositing of the second metal nitride layer are performed in-situ in the same process chamber. In some embodiments, the forming of the multilayer middle conductor plate layer includes depositing a third metal nitride layer over the first dielectric layer, depositing a second metal layer over the third metal nitride layer, and depositing a fourth metal nitride layer over the second metal layer. In some instances, the forming of the multilayer top conductor plate layer includes depositing a fifth metal nitride layer over the second dielectric layer, depositing a third metal layer over the fifth metal nitride layer, and depositing a sixth metal nitride layer over the second metal layer. In some instances, the method may further include forming an opening through the second insulation layer, the sixth metal nitride layer, the third metal layer, the fifth metal nitride layer, the second dielectric layer, the first dielectric layer, the second metal nitride layer, the first metal layer, the first metal nitride layer, and the first insulation layer to expose the conductive feature, and forming a conductive feature in the opening.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.