Patent ID: 12244316

DETAILED DESCRIPTION

Various embodiments of the present disclosure will be explained below in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects, and various embodiments of the present disclosure. The detailed description provides in sufficient detail to enable those skilled in the art to practice these embodiments of the present disclosure. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessary mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

FIG.1is a block diagram showing a configuration of a semiconductor device according to an embodiment of the present disclosure. A semiconductor device according to the present embodiment is a DRAM and includes a memory cell array10, an access control circuit20, an I/O circuit30, and a clock control circuit100as shown inFIG.1. The access control circuit20makes access to the memory cell array10based on a command address signal CA input via a command address terminal11. With this access operation, when the command address signal CA indicates a read operation, read data DQ read out from the memory cell array10is output to a data terminal12via the I/O circuit30. When the command address signal CA indicates a write operation, write data DQ input to the data terminal12from outside is written into the memory cell array10via the I/O circuit30. The access control circuit20includes a mode register22. Various operating parameters are set in the mode register22. The clock control circuit100generates various internal clock signals including internal clock signals ICLK, CK0, CK90, CK180, and CK270, for example, based on complementary external clock signals CKT and CKC input via clock terminals13and14. The access control circuit20operates in synchronization with the internal clock signal ICLK. The I/O circuit30serially outputs the read data DQ in synchronization with the internal clock signals CK0, CK90, CK180, and CK270.

FIG.2is a block diagram showing a configuration of the clock control circuit100. The clock control circuit100includes a divider circuit102that divides the external clock signals CKT and CKC supplied via an input buffer101to generate divided clock signals iCK0, iCK90, iCK180, and iCK270. The cycle of each of the divided clock signals iCK0, iCK90, iCK180, and iCK270is two times longer than that of the external clock signals CKT and CKC. The phase of the divided clock signals iCK0, iCK90, iCK180, and iCK270and the phase of the external clock signals CKT and CKC are different from each other by 90 degrees. The divided clock signals iCK0and iCK90are input to delay lines111and121, respectively, through repeaters103. The divided clock signals iCK0and iCK180are input to a path control circuit130through the repeaters103. The delay lines111and121delay the divided clock signals iCK0and iCK90, respectively. The delays in the delay lines111and121are controlled by the path control circuit130. The divided clock signals iCK0and iCK90delayed by the delay lines111and121are input to duty-cycle adjusters (DCAs)112and122, respectively. The DCA112adjusts timings of a rising edge and a falling edge of the divided clock signal iCK0. The DCA122adjusts timings of a rising edge and a falling edge of the divided clock signal iCK90. The operations of the DCAs112and122are controlled by a DCA control circuit200. The divided clock signal iCK0with the timings adjusted by the DCA112is supplied to a phase splitter114. The phase splitter114generates, based on the divided clock signal iCK0, the internal clock signal CK0having the same phase as the divided clock signal iCK0and the internal clock signal CK180having the opposite phase to the divided clock signal iCK0. The divided clock signal iCK90with the timings adjusted by the DCA122is supplied to a phase splitter124. The phase splitter124generates, based on the divided clock signal iCK90, the internal clock signal CK90having the same phase as the divided clock signal iCK90and the internal clock signal CK270having the opposite phase to the divided clock signal iCK90.

The internal clock signals CK0, CK90, CK180, and CK270have waveforms shown inFIG.3. The internal clock signals CK0, CK90, CK180, and CK270are supplied to the I/O circuit30via a trim circuit150and a DCA160. The trim circuit150is a circuit for adjusting a delay difference between rising edges of the internal clock signals CK0, CK90, CK180, and CK270in order to correct an error of a duty-cycle detector (DCD) included in the DCA control circuit200and/or to correct variations in the DCA160and the I/O circuit30. Trimming for the trim circuit150is performed in a manufacturing stage. The DCA160is a circuit for adjusting a delay difference between the rising edges of the internal clock signals CK0, CK90, CK180, and CK270with the parameters set in the mode register22. The I/O circuit30includes a serializer31that receives the internal clock signals CK0, CK90, CK180, and CK270and read data read out from the memory cell array10, and an output buffer32driven by the serializer31. With this configuration, the read data read out from the memory cell array10is serially output to the data terminal12in synchronization with the internal clock signals CK0, CK90, CK180, and CK270. Since the serializer31performs parallel-to-serial conversion for the read data in synchronization with the rising edges of the internal clock signals CK0, CK90, CK180, and CK270, the widths of periods UI0, UI1, UI2, and UI3has to be kept constant.

The internal clock signal CK0is fed back to the path control circuit130via a replica circuit140. The delay of the internal clock signal CK0by the replica circuit140is set to be the same as the total (=t1+t2+t3) of a delay t1in an input section including the input buffer101, the divider circuit102, and the repeaters103, a delay t2in a clock tree that propagates the internal clock signals CK0, CK90, CK180, and CK270, and a delay t3in the I/O circuit30. The path control circuit130includes a phase detector131comparing the phase of the delayed internal clock signal CK0output from the replica circuit140and the phase of the divided clock signal iCK0or iCK180with each other, and controls the delay in each of the delay lines111and121to match both the phases. With this control, an output timing of the read data DQ output from the data terminal12is accurately synchronized with the external clock signals CKT and CKC. Here, when it is assumed that a period from a rising edge of the internal clock signal CK0to a rising edge of the internal clock signal CK90is UI0, a period from a rising edge of the internal clock signal CK180to a rising edge of the internal clock signal CK270is UI2, a period from a rising edge of the internal clock signal CK90to a rising edge of the internal clock signal CK180is UI1, and a period from a rising edge of the internal clock signal CK270to a rising edge of the internal clock signal CK0is UI3, the DCA control circuit200executes control to satisfy the relation UI0=UI1=UI2=UI3.

FIG.4is a block diagram showing a configuration of the DCA control circuit200. As shown inFIG.4, the DCA control circuit200includes a pulse extraction circuit210. As shown inFIG.5, the pulse extraction circuit210generates various control pulses based on the internal clock signals CK0, CK90, CK180, and CK270.FIG.6shows waveforms of the control pulses generated by the pulse extraction circuit210. As shown inFIG.6, each of the control pulses generated by the pulse extraction circuit210has four clock cycles. The number of clock cycles of the control pulse generated by the pulse extraction circuit210is not particularly limited as long as it is an even number. As the number of clock cycles of the control pulse is greater, a larger amount of error can be superimposed. Therefore, accurate detection of a small error becomes easy. However, the time required for performing duty check once is increased, so that the time required for locking becomes longer. A control pulse0F is an inverted signal of an original signal based on the internal clock signal CK0and is extracted by using an enable signal En0. A control pulse1T is an original signal based on the internal clock signal CK90, and control pulses1F and1D are an inverted signal of the original signal1T and a signal obtained by delaying the original signal1T, respectively. All these signals are extracted by using an enable signal En1. A control pulse2T is an original signal based on the internal clock signal CK180, and control pulses2F and2D are an inverted signal of the original signal2T and a signal obtained by delaying the original signal2T, respectively. All these signals are extracted by using an enable signal En2. A control pulse3T is an original signal based on the internal clock signal CK270, and control pulses3F and3D are an inverted signal of the original signal3T and a signal obtained by delaying the original signal3T, respectively. All these signals are extracted by using an enable signal En3. A control pulse4T is an original signal based on the internal clock signal CK0, and control pulses4F and4D are an inverted signal of the original signal4T and a signal obtained by delaying the original signal4T, respectively. All these signals are extracted by using an enable signal En4. A control pulse5T is an original signal based on the internal clock signal CK90, and a control pulse5F is an inverted signal of the original signal5T. Both the signals are extracted by using an enable signal En5. The above-described control pulses are supplied to duty-cycle detectors (DCDs)221to223included in the DCA control circuit200.

The DCDs221to223detect duty-cycles of the internal clock signals CK0, CK90, CK180, and CK270. Here, as shown inFIG.7, when it is assumed that a period from a rising edge of the internal clock signal CK0to a rising edge of the internal clock signal CK90is A, a period from a rising edge of the internal clock signal CK90to a rising edge of the internal clock signal CK180(or a period from a rising edge of the internal clock signal CK90to a falling edge of the internal clock signal CK0) is B, a period from a rising edge of the internal clock signal CK180to a rising edge of the internal clock signal CK270(or a period from a falling edge of the internal clock signal CK0to a falling edge of the internal clock signal CK90) is C, and a period from a rising edge of the internal clock signal CK270to a rising edge of the internal clock signal CK0(or a period from a falling edge of the internal clock signal CK90to a rising edge of the internal clock signal CK0) is D, the DCD221detects a difference between A+B and C+D, the DCD222detects a difference between A+D and B+C, and the DCD223detects a difference between A+C and B+D. That is, the DCD221determines duty-cycles of the internal clock signals CK0and CK180. The DCD222determines duty-cycles of the internal clock signals CK90and CK270. The DCD223determines a phase difference between the internal clock signals CK0and CK180and the internal clock signals CK90and CK270.

FIG.8Ais a circuit diagram of the DCD221. As shown inFIG.8A, the DCD221includes a P-channel MOS transistor313and an N-channel MOS transistor314connected in series between current sources311and312and a P-channel MOS transistor317and an N-channel MOS transistor318connected in series between current sources315and316. The control pulse0F is input to a gate electrode of the transistor313, and accordingly the transistor313is turned on in a period of A+B. The control pulse2T is input to a gate electrode of the transistor314, and accordingly the transistor314is turned on in a period of C+D. The control pulse2F is input to a gate electrode of the transistor317, and accordingly the transistor317is turned on in a period of C+D. The control pulse4T is input to a gate electrode of the transistor318, and accordingly the transistor318is turned on in a period of A+B. A connection point between the transistors313and314is connected to a capacitor321. With this configuration, as shown inFIG.9A, the capacitor321is charged when the transistor313is turned on, and is discharged when the transistor314is turned on. A connection point between the transistors317and318is connected to a capacitor322. With this configuration, as shown inFIG.9A, the capacitor322is charged when the transistor317is turned on, and is discharged when the transistor318is turned on. A potential difference between the capacitors321and322is detected by a comparator320, based on which a detection signal S1is generated. With this configuration, the DCD221places the detection signal S1at a low level when A+B is longer than C+D, and places the detection signal S1at a high level when A+B is shorter than C+D.

FIG.8Bis a circuit diagram of the DCD222. As shown inFIG.8B, the DCD222includes a P-channel MOS transistor333and an N-channel MOS transistor334connected in series between current sources331and332and a P-channel MOS transistor337and an N-channel MOS transistor338connected in series between current sources335and336. The control pulse1F is input to a gate electrode of the transistor333, and accordingly the transistor333is turned on in a period of B+C. The control pulse3T is input to a gate electrode of the transistor334, and accordingly the transistor334is turned on in a period of A+D. The control pulse3F is input to a gate electrode of the transistor337, and accordingly the transistor337is turned on in a period of A+D. The control pulse5T is input to a gate electrode of the transistor338, and accordingly the transistor338is turned on in a period of B+C. A connection point between the transistors333and334is connected to a capacitor341. With this configuration, as shown inFIG.9B, the capacitor341is charged when the transistor333is turned on, and is discharged when the transistor334is turned on. A connection point between the transistors337and338is connected to a capacitor342. With this configuration, as shown inFIG.9B, the capacitor342is charged when the transistor337is turned on, and is discharged when the transistor338is turned on. A potential difference between the capacitors341and342is detected by a comparator340, based on which a detection signal S2is generated. With this configuration, the DCD222places the detection signal S2at a low level when B+C is longer than A+D, and places the detection signal S2at a high level when B+C is shorter than A+D.

FIG.8Cis a circuit diagram of the DCD223. As shown inFIG.8C, the DCD223includes between a current source350and a node N1P-channel MOS transistors352and353connected in series and P-channel MOS transistors354and355connected in series and also includes between a current source360and the node N1P-channel MOS transistors362and363connected in series and P-channel MOS transistors364and365connected in series. The control pulse0F is input to gate electrodes of the transistors352and355, the control pulse1D is input to gate electrodes of the transistors353and354, the control pulse2F is input to gate electrodes of the transistors362and365, and the control pulse3D is input to gate electrodes of the transistors363and364. The DCD223further includes between the node N1and a current source351N-channel MOS transistors356and357connected in series and N-channel MOS transistors358and359connected in series and also includes between the node N1and a current source361N-channel MOS transistors366and367connected in series and N-channel MOS transistors368and369connected in series. The control pulse1T is input to gate electrodes of the transistors356and359, the control pulse2F is input to gate electrodes of the transistors357and358, the control pulse3T is input to gate electrodes of the transistors366and369, and the control pulse4F is input to gate electrodes of the transistors367and368.

The DCD223includes between a current source370and a node N2P-channel MOS transistors372and373connected in series and P-channel MOS transistors374and375connected in series and also includes between a current source380and the node N2P-channel MOS transistors382and383connected in series and P-channel MOS transistors384and385connected in series. The control pulse1F is input to gate electrodes of the transistors372and375, the control pulse2D is input to gate electrodes of the transistors373and374, the control pulse3F is input to gate electrodes of the transistors382and385, and the control pulse4D is input to gate electrodes of the transistors383and384. The DCD223further includes between the node N2and a current source371N-channel MOS transistors376and377connected in series and N-channel MOS transistors378and379connected in series and also includes between the node N2and a current source381N-channel MOS transistors386and387connected in series and N-channel MOS transistors388and389connected in series. The control pulse4T is input to gate electrodes of the transistors376and379, the control pulse5F is input to gate electrodes of the transistors377and378, the control pulse2T is input to gate electrodes of the transistors386and389, and the control pulse3F is input to gate electrodes of the transistors387and388.

The node N1is connected to a capacitor391. With this configuration, as shown inFIG.9C, the capacitor391is charged when the transistors352to355or362to365are turned on, and is discharged when the transistor356to359or366to369are turned on. The node N2is connected to a capacitor392. With this configuration, as shown inFIG.9C, the capacitor392is charged when the transistors372to375or382to385are turned on, and is discharged when the transistor376to379or386to389are turned on. A potential difference between the capacitors391and392is detected by a comparator390, based on which a detection signal S3is generated. With this configuration, the DCD223places the detection signal S3at a high level when A+C is longer than B+D, and places the detection signal S3at a low level when A+C is shorter than B+D.

As shown inFIG.4, the detection signals S1to S3are supplied to an analyzing circuit230included in the DCA control circuit200. The analyzing circuit230analyzes the detection signals S1to S3, thereby incrementing or decrementing count values of counters241to244. The count values of the counters241and242are parameters for controlling a rising edge and a falling edge of the divided clock signal iCK0, respectively. The count values of the counters243and244are parameters for controlling a rising edge and a falling edge of the divided clock signal iCK90, respectively. All the counters241to244execute control in such a manner that as the count value is increased, the corresponding edge is delayed. Default values of the counters241to244are 0, and therefore delays of all the edges are minimum in the initial state.

FIG.10is an explanatory diagram of an operation of the analyzing circuit230. As described above, the three-bit detection signals S1to S3are supplied to the analyzing circuit230from the DCDs221to223. Therefore, eight combinations of the detection signals S1to S3are possible. When Pattern #1in which the detection signals S1and S3are at a low level and the detection signal S2is at a high level appears, it is found that the period A is longer than the other periods B, C, and D. In this case, therefore, control for shortening the period A is required. To this end, it suffices that a rising edge of the divided clock signal iCK0is delayed or a rising edge of the divided clock signal iCK90is advanced. In this regard, the analyzing circuit230increments the counter241or decrements the counter243. When Pattern #2in which the detection signal S1is at a low level and the detection signals S2and S3are at a high level appears, it is found that the period C is shorter than the other periods A, B, and D. In this case, therefore, control for making the period C longer is required. To this end, it suffices that a falling edge of the divided clock signal iCK90is delayed or a falling edge of the divided clock signal iCK0is advanced. In this regard, the analyzing circuit230increments the counter244or decrements the counter242. When Pattern #3in which all the detection signals S1to S3are at a low level appears, it is found that the period D is shorter than the other periods A, B, and C. In this case, therefore, control for making the period D longer is required. To this end, it suffices that a rising edge of the divided clock signal iCK0is delayed or a falling edge of the divided clock signal iCK90is advanced. In this regard, the analyzing circuit230increments the counter241or decrements the counter244. When Pattern #4in which the detection signals S1and S2are at a low level and the detection signal S3is at a high level appears, it is found that the period B is longer than other the periods A, C, and D. In this case, therefore, control for shortening the period B is required. To this end, it suffices that a rising edge of the divided clock signal iCK90is delayed or a falling edge of the divided clock signal iCK0is advanced. In this regard, the analyzing circuit230increments the counter243or decrements the counter242.

When Pattern #5in which the detection signals S1and S2are at a high level and the detection signal S3is at a low level appears, it is found that the period B is shorter than the other periods A, C, and D. In this case, therefore, control for making the period B longer is required. To this end, it suffices that a falling edge of the divided clock signal iCK0is delayed or a rising edge of the divided clock signal iCK90is advanced. In this regard, the analyzing circuit230increments the counter242or decrements the counter243. When Pattern #6in which all the detection signals S1to S3are at a high level appears, it is found that the period D is longer than the other periods A, B, and C. In this case, therefore, control for shortening the period D is required. To this end, it suffices that a falling edge of the divided clock signal iCK90is delayed or a rising edge of the divided clock signal iCK0is advanced. In this regard, the analyzing circuit230increments the counter244or decrements the counter241. When Pattern #7in which the detection signal S1is at a high level and the detection signals S2and S3are at a low level appears, it is found that the period C is longer than the other periods A, B, and D. In this case, therefore, control for shortening the period C is required. To this end, it suffices that a falling edge of the divided clock signal iCK0is delayed or a falling edge of the divided clock signal iCK90is advanced. In this regard, the analyzing circuit230increments the counter242or decrements the counter244. When Pattern #8in which the detection signals S1and S3are at a high level and the detection signal S2is at a low level appears, it is found that the period A is shorter than the other periods B, C, and D. In this case, therefore, control for making the period A longer is required. To this end, it suffices that a rising edge of the divided clock signal iCK90is delayed or a rising edge of the divided clock signal iCK0is advanced. In this regard, the analyzing circuit230increments the counter243or decrements the counter241.

In accordance with the appearing Patterns #1to #8, the analyzing circuit230increments or decrements the counters241to244in this manner. Incrementing the counters241to244is usually selected, although not specifically limited. When all the count values of the counters241to244are not zero, decrementing the counters241to244may be selected. When the analyzing circuit230increments or decrements a required one of the counters241to244in this manner, the duty-cycles of the divided clock signals iCK0and iCK90become closer to 50%, and the phase difference between the divided clock signals iCK0and iCK90becomes closer to 90 degrees. When the phase difference between the divided clock signals iCK0and iCK90becomes 90 degrees, the phase differences between the internal clock signals CK0, CK90, CK180, and CK270also become 90 degrees. In the present embodiment, control is executed in such a manner that the duty-cycles of the divided clock signals iCK0and iCK90become 50%. Therefore, the lengths of the periods UI0to UI3shown inFIG.3also become uniform. The periods UI0to UI3correspond to the above-described periods A to D, respectively.

The counters241to244may be incremented or decremented by one step. However, a control stage in which the counters241to244are updated by multiple steps and a control stage in which the counters241to244are updated by one step may be performed in turn. In examples shown inFIGS.11A to11C, for example, a control stage Fstage1in which the counters241to244are updated by four steps (or eight steps), a control stage Fstage2in which the counters241to244are updated by two steps, and control stages Fstages3and4in which the counters241to244are updated by one step are executed in this order. The control stage may be updated to the next control stage when transitions of levels of all the detection signals S1to S3from the DCDs221to223have occurred. In a case where the detection signals S1to S3change as the example shown inFIG.12, for example, the control stage may be updated in response to the last changed detection signal S3. Further, in a case where one or two of the detection signals S1to S3do not change and only the remaining detection signal(s) change/changes repeatedly, the control stage may be updated forcibly. In addition, transition to the control stage Fstage3may be prohibited before completion of an initializing operation of a DLL circuit using the path control circuit130. In the case shown inFIG.11A, the initializing operation of the DLL circuit is performed in the course of the control stage Fstage2. In this regard, when the initializing operation of the DLL circuit ends, the control stage Fstage2is resumed. In the cases shown inFIGS.11B and11C, the initializing operation of the DLL circuit is performed in the course of the control stage Fstage1. In this regard, when the initializing operation of the DLL circuit ends, the control stage Fstage1may be resumed as shown inFIG.11Bor may be transitioned to the control stage Fstage2as shown inFIG.11C.

The count values of the counters241to244generated in this manner are supplied to decoders251to254, respectively, as shown inFIG.4. The decoder251generates control codes CD11to CD14by decoding the count value of the counter241. The decoder252generates control codes CD21to CD24by decoding the count value of the counter242. The decoder253generates control codes CD31to CD34by decoding the count value of the counter243. The decoder253generates control codes CD41to CD44by decoding the count value of the counter243. A relation between the count values of the counters241to244and the control codes CD11to CD14, CD21to CD24, CD31to CD34, and CD41to CD44is shown inFIG.13. The control codes CD11to CD14and CD21to CD24are supplied to the DCA112, and the control codes CD31to CD34and CD41to CD44are supplied to the DCA122.

FIG.14Ais a circuit diagram of the DCA112. The DCA112includes an inverter400that inverts the divided clock signal iCK0to generate a divided clock signal iCK0F and an even-path EP0and an odd-path OP0that receive the divided clock signal iCK0F. The even-path EP0includes inverters401and403connected in series. The odd-path OP0includes inverters402and404connected in series. The pull-up capability of the inverters401to404can be adjusted by the control codes CD11, CD12, CD23, and CD24, respectively. The pull-down capability of the inverters401to404can be adjusted by the control codes CD21, CD22, CD13, and CD14, respectively. A divided clock signal iCK0EF output from the even-path EP0and a divided clock signal iCK0OF output from the odd-path OP0are input to a mixer405. The mixer405synthesizes the divided clock signals iCK0EF and iCK0OF at a mixing ratio of 50%, thereby reproducing the divided clock signal iCK0with adjusted timings. The mixing ratio of the mixer405is fixed to 50%.

FIG.15is a circuit diagram of the inverter401. As shown inFIG.15, the inverter401includes five inverters410,420,430,440, and450connected in parallel. The inverter410includes a P-channel MOS transistor411and an N-channel MOS transistor412each having a gate electrode to which the divided clock signal iCK0F is supplied, P-channel MOS transistors413to415connected in series between a higher-potential power line and the transistor411, and N-channel MOS transistors416to418connected in series between a lower-potential power line and the transistor412. An inverted signal of the least significant bit of the control code CD11is supplied to a gate electrode of the transistor413. An inverted signal of the least significant bit of the control code CD21is supplied to a gate electrode of the transistor416. A ground potential is supplied to gate electrodes of the transistors414and415, whereby the transistors414and415are always in an ON-state. A power potential is supplied to gate electrodes of the transistors417and418, whereby the transistors417and418are always in an ON-state. The inverter420includes a P-channel MOS transistor421and an N-channel MOS transistor422each having a gate electrode to which the divided clock signal iCK0F is supplied, a P-channel MOS transistor423connected between the higher-potential power line and the transistor421, and an N-channel MOS transistor424connected between the lower-potential power line and the transistor422. An inverted signal of the second bit of the control code CD11is supplied to a gate electrode of the transistor423. An inverted signal of the second bit of the control code CD21is supplied to a gate electrode of the transistor424. This configuration makes the drive capability of the inverter420two times higher than the drive capability of the inverter410.

The inverter430includes P-channel MOS transistors431A and431B and N-channel MOS transistors432A and432B, each having a gate electrode to which the divided clock signal iCK0F is supplied, P-channel MOS transistor433A and433B connected between the higher-potential power line and the transistors431A and431B, respectively, and N-channel MOS transistor434A and434B connected between the lower-potential power line and the transistors432A and432B, respectively. An inverted signal of the third bit of the control code CD11is supplied to gate electrodes of the transistors433A and433B. An inverted signal of the third bit of the control code CD21is supplied to gate electrodes of the transistors434A and434B. This configuration makes the drive capability of the inverter430two times higher than the drive capability of the inverter420. The inverter440includes P-channel MOS transistors441A,442A,441B, and442B and N-channel MOS transistors443A,444A,443B, and444B, each having a gate electrode to which the divided clock signal iCK0F is supplied, P-channel MOS transistor445A,446A,445B, and446B connected between the higher-potential power line and the transistors441A,442A,441B, and442B, respectively, and N-channel MOS transistors447A,448A,447B, and448B connected between the lower-potential power line and the transistors443A,444A,443B, and444B, respectively. An inverted signal of the most significant bit of the control code CD11is supplied to gate electrodes of the transistors445A,446A,445B, and446B. An inverted signal of the most significant bit of the control code CD21is supplied to gate electrodes of the transistors447A,448A,447B, and448B. This configuration makes the drive capability of the inverter440two times higher than the drive capability of the inverter430.

With this configuration, the inverter401can change the pull-up capability in 16 stages based on the four-bit control code CD11and can also change the pull-down capability in 16 stages based on the four-bit control code CD21. The inverter450includes a P-channel MOS transistor451and an N-channel MOS transistor452each having a gate electrode to which the divided clock signal iCK0F is supplied, a P-channel MOS transistor453connected between the higher-potential power line and the transistor451, and an N-channel MOS transistor454connected between the lower-potential power line and the transistor452. The ground potential is supplied to a gate electrode of the transistor453, whereby the transistor453is always in an ON-state. The power potential is supplied to a gate electrode of the transistor454, whereby the transistor454is always in an ON-state. Accordingly, the inverter450operates irrespective of the control codes CD11and CD21.

The other inverters402to404also have a circuit configuration identical to that of the inverter401. Accordingly, the inverter402can change the pull-up capability in 16 stages based on the four-bit control code CD12and can also change the pull-down capability in 16 stages based on the four-bit control code CD22. The inverter403can change the pull-down capability in 16 stages based on the four-bit control code CD13and can also change the pull-up capability in 16 stages based on the four-bit control code CD23. The inverter404can change the pull-down capability in 16 stages based on the four-bit control code CD14and can also change the pull-up capability in 16 stages based on the four-bit control code CD24.

As shown inFIG.14B, the DCA122has a circuit configuration identical to that of the DCA112. The DCA122includes an inverter500that inverts the divided clock signal iCK90to generate a divided clock signal iCK90F and an even-path E90and an odd-path OP90that receive the divided clock signal iCK90F. The even-path EP90includes inverters501and503connected in series. The odd-path OP90includes inverters502and504connected in series. The pull-up capability of the inverters501to504can be adjusted by the control codes CD31, CD32, CD43, and CD44, respectively. The pull-down capability of the inverters501to504can be adjusted by the control codes CD41, CD42, CD33, and CD34, respectively. A divided clock signal iCK90EF output from the even-path EP90and a divided clock signal iCK90OF output from the odd-path OP90are input to a mixer505. The mixer505synthesizes the divided clock signals iCK90EF and iCK90OF at a mixing ratio of 50%, thereby reproducing the divided clock signal iCK90with adjusted timings. The mixing ratio of the mixer505is fixed to 50%.

As shown inFIG.13, when the count values of the counters241to244are default values (=0), the pull-up capability and the pull-down capability of the inverters401to404included in the DCA112and those of the inverters501to504included in the DCA122become the maximum. Accordingly, delays of rising edges and falling edges of the divided clock signals iCK0and iCK90become the minimum. When any of the counters241to244is incremented, the pull-up capability or the pull-down capability of a corresponding one of the inverters401to404and501to504is lowered, and the delay of the rising edge or the falling edge of the corresponding divided clock signal iCK0or iCK90is increased.

In one example, when the count value of the counter241is incremented from 0 as the default value to 1, the control code CD11is decreased by one bit, so that the pull-up capability of the inverter401is lowered by one step. Accordingly, the rising edge of the divided clock signal iCK0is delayed in the even-path EP0by one step. As a result, the divided clock signal iCK0EF in which a falling edge is delayed from the minimum value by one step and the divided clock signal iCK0OF in which a falling edge is the minimum value are input to the mixer405, and are synthesized at a mixing ratio of 50%. Consequently, the divided clock signal iCK0output from the DCA112has a waveform in which a rising edge is delayed by 0.5 steps.

Further, when the count value of the counter241is incremented from 1 to 2, the control code CD12is further decreased by one bit, so that the pull-up capability of the inverter402is lowered by one step. Accordingly, the rising edge of the divided clock signal iCK0is delayed in each of the even-path EP0and the odd-path OP0by one step. As a result, the divided clock signal iCK0EF in which the falling edge is delayed from the minimum value by one step and the divided clock signal iCK0OF in which the falling edge is delayed from the minimum value by one step are input to the mixer405, and are synthesized at a mixing ratio of 50%. Consequently, the divided clock signal iCK0output from the DCA112has a waveform in which the rising edge is delayed by one step.

Furthermore, when the count value of the counter241is incremented from 2 to 3, the control code CD13is further increased by one bit, so that the pull-down capability of the inverter403is lowered by one step. Accordingly, the rising edge of the divided clock signal iCK0is delayed in the even-path EP0by two steps and in the odd-path OP0by one step. As a result, the divided clock signal iCK0EF in which the falling edge is delayed from the minimum value by two steps and the divided clock signal iCK0OF in which the falling edge is delayed from the minimum value by one step are input to the mixer405, and are synthesized at a mixing ratio of 50%. Consequently, the divided clock signal iCK0output from the DCA112has a waveform in which the rising edge is delayed by 1.5 steps.

Furthermore, when the count value of the counter241is incremented from 3 to 4, the control code CD14is further increased by one bit, so that the pull-down capability of the inverter404is lowered by one step. Accordingly, the rising edge of the divided clock signal iCK0is delayed in each of the even-path EP0and the odd-path OP0by two steps. As a result, the divided clock signal iCK0EF in which the falling edge is delayed from the minimum value by two steps and the divided clock signal iCK0OF in which the falling edge is delayed from the minimum value by two steps are input to the mixer405, and are synthesized at a mixing ratio of 50%. Consequently, the divided clock signal iCK0output from the DCA112has a waveform in which the rising edge is delayed by two steps.

As described above, every time the count value of the counter241is incremented, the pull-up capability of the inverter401, the pull-up capability of the inverter402, the pull-down capability of the inverter403, and the pull-down capability of the inverter404are lowered in this order. This makes it possible to adjust the rising edge of the divided clock signal iCK0by 0.5 steps although the mixing ratio of the mixer405is fixed to 50%. The above description can also be applied to a falling edge of the divided clock signal iCK0. That is, every time the count value of the counter242is incremented, the pull-up capability of the inverter403, the pull-up capability of the inverter404, the pull-down capability of the inverter401, and the pull-down capability of the inverter402are lowered in this order. The DCA122also adjusts a rising edge and a falling edge of the divided clock signal iCK90based on the count values of the counters243and244in an identical manner to the DCA112.

FIG.16is a circuit diagram of the inverter401according to a modification. The inverter401shown inFIG.16is different from the inverter401shown inFIG.15in that the inverter440is divided into inverters440A and440B. The inverter440A is controlled by the transistors445A,446A,447A, and448A, and the inverter440B is controlled by the transistors445B,446B,447B, and448B. Therefore, the inverters430,440A, and440B are equal to each other in drive capability. In a case of using the inverter401shown inFIG.16, the most significant bit of each of the control codes CD11and CD21shown inFIG.13is divided into two bits, whereby the upper three bits of each of the CD11and CD21are converted into a thermometer code as shown inFIG.17. This configuration enables a glitch caused by inversion of the most significant bit to be prevented.

As described above, the semiconductor device according to the present embodiment detects phases of the four-phase internal clock signals CK0, CK90, CK180, and CK270by means of the three DCDs221to223and, based on the detection result, controls rising edges and falling edges of the divided clock signals iCK0and iCK90that have phases different from each other by 90 degrees. In this manner, the periods UI0to UI3shown inFIG.3can be made uniform.

Although various embodiments have been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the scope of the present disclosure extends beyond the specifically disclosed embodiments to other alternative embodiments and/or uses of the embodiments and obvious modifications and equivalents thereof. In addition, other modifications which are within the scope of this disclosure will be readily apparent to those of skill in the art based on this disclosure. It is also contemplated that various combination or sub-combination of the specific features and aspects of the embodiments may be made and still fall within the scope of the disclosure. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying modes of the disclosed embodiments. Thus, it is intended that the scope of at least some of the present disclosure should not be limited by the particular disclosed embodiments described above.