Patent ID: 12256563

DETAILED DESCRIPTION OF THE INVENTION

Hereinbelow, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be understood that the embodiment(s) of the present invention may be changed to a variety of embodiments, and the scope and spirit of the present invention are not limited to any particular embodiment described hereinbelow. The embodiments of the present invention described hereinbelow are provided for allowing those skilled in the art to more clearly comprehend the present invention.

Hereinbelow, if it is described that a first component (or layer) is on a second component (or layer), it should be understood that the first component may be directly on the second component, or one or more components or layers may be between the components. Furthermore, if it is described that the first component is directly on the second component, no additional components are between the first and second components. A location ‘on’, ‘upper’, ‘lower’, ‘above’, and ‘below’ or ‘beside’ the first component may describe a relative location relationship.

Terms such as ‘a first ˜’, ‘a second ˜’, and ‘a third ˜’ are used only for the purpose for describing various elements such as various components, regions, and/or parts, and the various elements are not limited to the terms.

It should also be noted that, in cases where certain embodiments are otherwise practicable, certain process sequences may be performed differently from those described below. For example, two processes described in succession may be performed substantially simultaneously or in a reverse order.

The term MOS (metal-oxide-semiconductor) used herein is a general term, and ‘M’ is not limited to metal, but may encompass any of various types of conductors. In addition, ‘S’ may be a substrate or a semiconductor structure, and ‘O’ may be an oxide such as silicon dioxide, but is not limited to oxides, and may include various types of organic or inorganic insulating materials.

In addition, a conductive or a doped region of the components may be defined as ‘P-type’ or ‘N-type’ depending on the main carrier properties, but such labels are only for convenience of the description, and the technical idea of the present disclosure is not limited to the embodiment. For example, ‘P-type’ or ‘N-type’ may be replaced herein with the more general terms ‘first conductive type’ or ‘second conductive type’. The first conductive type may refer to P-type, and the second conductive type may refer to N-type, but the present disclosure is not limited to this correlation.

Hereinbelow, prior to describing a superjunction semiconductor device1having a reduced source area according to a first embodiment of the present disclosure, an array structure of a general superjunction semiconductor device will be described.

Referring toFIG.2, the general superjunction semiconductor device has a core region C providing a current path in a channel between the source and the drain when a gate—source voltage is applied. Edge regions E function as a termination region for the channel (e.g., the channel does not format or beyond the edge regions E). In general, sources are not in the edge regions E. Furthermore, the edge regions E are formed at opposite ends or sides of the core region C (e.g., in the Y-axis direction inFIG.2). For example, the edge regions E may be curved (e.g., when the structure defining the edge regions E is defined by photolithographic patterning), but the present disclosure is not limited thereto.

Hereinbelow, for convenience of the description, in the plan views shown in the drawings, the X-axis direction is referred as ‘a cross-direction’ and the Y-axis direction is referred as ‘a longitudinal direction’.

FIG.4is a cross-sectional view showing a superjunction semiconductor device having sources with a reduced area according to a first embodiment of the present disclosure.

Hereinbelow, the superjunction semiconductor device1having a reduced source area will be described in detail with reference to accompanying drawings. According to a first embodiment of the present disclosure, the superjunction semiconductor device1includes a cell region (active region) and a ring region (termination region) enclosing the cell region. Furthermore, a transition region is between the cell region and the ring region. For convenience of the description, in the present disclosure, only the cell region, i.e., the active region including one or more source regions and other structures for transistor activity, will be described in detail.

Referring toFIG.4, the present disclosure relates to the superjunction semiconductor device1having sources with a reduced area and, more particularly, to a semiconductor device1configured to realize a reduction in the area of a source in a body region to reduce the value of the short circuit current, Isc, and thus delay or reduce the rate of junction temperature increase and increase the time (tsc) before device destruction.

The semiconductor device1may include, for example, a substrate101, such as a silicon substrate, a germanium substrate, etc., or a bulk wafer with an epitaxial layer (or “epi-layer”) thereon. The substrate101may comprise, for example, a heavily doped second conductive type substrate. A drain electrode110is under the substrate.

An epitaxial layer120is on the substrate101. The epitaxial layer120may comprise, for example, a lightly doped second conductive type epitaxial layer (e.g., having the same or substantially the same crystal structure and/or lattice as the substrate101). A plurality of pillars130, which are first conductive type dopant regions, may be in the epitaxial layer120, spaced apart from each other in a transversal direction. The pillars130may extend vertically toward the lower side (e.g., the drain electrode110), and surfaces thereof in contact with the epitaxial layer120may be flat or curved, but the scope of the present disclosure is not limited to a specific shape.

One or more body regions140may be in the epitaxial layer120, and each body region140may be on an upper portion of a corresponding one of the pillars130. The body region140has the first conductive type. The body region140may include a plurality of body regions140so that the body regions140may be respectively connected to upper portions of the pillars130in an upper portion of the epitaxial layer120. A source142, e.g., a second conductive type dopant region, is in each of the body regions140. A body contact144may be at a location adjacent to the source142or in contact with the source142.

Furthermore, a gate oxide film150is on the epitaxial layer120, between adjacent body regions140. The gate oxide film150preferably overlaps partially with the body regions140. The gate oxide film150comprises or consists of at least one of a silicon oxide film, a high dielectric film, and a combination thereof.

Furthermore, a gate electrode160comprising or consisting of, e.g., a polysilicon film is on the gate oxide film150. A channel region may be turned on and off by a voltage applied to the gate electrode160. The gate electrode160may comprise or consist of, for example, conductive (i.e., doped) polysilicon, a metal, a conductive metal nitride, or a combination of two or more of conductive polysilicon, a metal, a refractory metal silicide, and a conductive metal nitride.

Hereinbelow, the structure of the conventional superjunction semiconductor device9, a problem of the superjunction semiconductor device9, and the superjunction semiconductor device1having a reduced source area according to the present disclosure to solve the problem will be described in detail.

Referring toFIGS.1and2, in describing the structure of the conventional superjunction semiconductor device9again, the first conductive type pillars930are in the second conductive type epitaxial layer910, spaced apart from each other. Furthermore, a first conductive type body region950is on each of the pillars930. The two sources970are in left and right sides of the individual body region950. Therefore, current paths may be provided in the epitaxial layer910at opposite sides of each of the pillars930.

In a general high voltage and high current power system, during a short circuit fault, both a high voltage and a high current are applied to the device, causing high power consumption. Continuous high power consumption causes a temperature increase in the device, and a junction temperature increase may be a major factor of device destruction. The conventional semiconductor device9includes the two sources970in the body region950, and thus allowing channels to be formed in the epitaxial layers910at the opposite sides of each of the pillars930as described above. Therefore, the short circuit current (Isc) may be relatively high.

In order to solve the above problem, according to the first embodiment of the present disclosure, the superjunction semiconductor device1having a source with a reduced area includes the source142only in a limited location or area along a longitudinal direction or a cross-direction of the core region C (see, e.g.,FIGS.5-7).

FIG.5is a plan view showing a mask for forming a source in the superjunction semiconductor device according to the first embodiment of the present disclosure.

Referring toFIG.5, as the first embodiment, one source142may be in the body region140along an entire length (e.g., longitudinal direction) of the core region C. The source142may be in the same location in each individual body region140. For example, the source142may be on the left side or the right side of the body contact144(not shown inFIG.5) and/or of an individual body region140in the core region C. Alternatively, the sources142may be on the side of the corresponding body regions140closest to the gate electrode160. The semiconductor device with such a structure may have a channel density of about 50% compared to the channel density of the conventional semiconductor device9.

FIG.6is a plan view showing a mask for forming one or more sources in the body region in a superjunction semiconductor device according to a second embodiment of the present disclosure.

Referring toFIG.6, according to the second embodiment, the source(s)142may be at each of opposite ends or portions of the body region140, but not in a center portion of the body region140, along the longitudinal direction in the core region C. In detail, the individual body region140may include two sources142, and the two sources142may be at the opposite ends or portions of the body region140adjacent to the edge regions E, but not in the center portion or section along the longitudinal direction. For example, the longitudinal length of a (central) non-source region C1in the body region140may be equal to or higher than 35% and less than or equal to 85% of the longitudinal length of the core region C (or any value or range of values therein, such as 50-85%). When the longitudinal length of the non-source region C1is less than 35%, it is difficult to achieve the purpose of the present disclosure, and when the longitudinal width value is higher than 85%, the on-resistance of the device increases, thus reducing efficiency of the semiconductor device.

FIG.7is a plan view showing a mask for forming one or more sources in the body region in a superjunction semiconductor device according to a third embodiment of the present disclosure.

Referring toFIG.7, according to the third embodiment, the source142is in the center portion of the body region140along the longitudinal direction of the core region C, and may not be in the ends or portions of the body region140adjacent to the edge regions E. After formation of the body contact (not shown), there may be two sources142in the center portion of the individual body region140. For example, the total or cumulative longitudinal length of the non-source regions C1at the opposite ends of the body region140may be equal to or higher than 50% and less than or equal to 85% of the total longitudinal length of the core region C, but the present disclosure is not limited thereto. The semiconductor device with such a structure has a processing advantage, and a detailed description thereof will be provided below.

FIG.8is a graph showing the peak value of a short circuit current in the superjunction semiconductor device according to the first embodiment inFIG.5.

As the semiconductor device is configured with the structure shown inFIG.4, a peak value of the short circuit current (Isc) of the semiconductor device is reduced compared to the conventional semiconductor device9(compareFIGS.3and8), and the time of junction temperature increase also increases, confirming that the survival time of the device increases. When Vdd is 400V and Vg is 16.5V, a peak value of the short circuit current (Isc) is about 274 A in the conventional semiconductor device9. However, when the cross-directional width of the non-source region C1is about 50% of the width of the body region140as in the first embodiment of the present disclosure, the peak value is significantly lowered to 205 A. Therefore, the rate of the junction temperature increase is also significantly reduced.

FIGS.9to11are views showing a method of manufacturing the superjunction semiconductor device having a reduced source area according to one or more embodiments of the present disclosure.

Hereinbelow, a method of manufacturing a superjunction semiconductor device having a reduced source area according to the present disclosure will be described in detail with reference to accompanying drawings. It should be noted that each step of forming the components may differ in time from that described, or may be conducted substantially simultaneously. In addition, the method(s) of manufacturing the components are described only for illustrative purposes, and the scope of the present disclosure is not limited by the examples provided.

Referring toFIG.9, the second conductive type epitaxial layer120and the pillars130are formed on the substrate101. The epitaxial layer120may comprise crystalline silicon doped with a second conductive type dopant, and may be formed by, for example, epitaxial growth. Then, one or more deep trenches (not shown) may be formed, extending into the epitaxial layer120from an upper surface thereof. A plurality of trenches may be formed, spaced apart from each other. Furthermore, the trench(es) may be formed by, for example, an etching process using a mask pattern. Then, the mask pattern is removed. After the removal of the mask pattern, the pillars130may be formed. For example, a semiconductor material containing the first conductive type dopant is deposited onto the epitaxial layer120and into the trenches, and then a CMP process is performed to expose the upper surface of the epitaxial layer120, and the semiconductor material remains in the trenches. In a further embodiment, the semiconductor material deposition process and the CMP process may be repeatedly performed until the trench(es) are completely filled.

In another embodiment, a plurality of second conductive type epi-layers are successively formed, and in a predetermined area of each of the epi-layers (i.e., after each formation of an epi-layer), a first conductive type dopant is implanted therein. Thereafter, a diffusion process (e.g., heating or thermal annealing) is performed to form the epitaxial layer120and the pillars130. However, in the present disclosure, the formation processes of the epitaxial layer120and the pillars130are not limited to the above description, and are described for illustrative purposes.

After the formation of the pillars130, an insulator film151is formed on the epitaxial layer120, and a gate film161is formed on the insulator film151. The insulator film151may comprise silicon dioxide, a high-k insulating material, or a combination thereof, and the gate film161may comprise a conductive polysilicon film.

After forming the gate film161, and now referring toFIG.10, a mask pattern (not shown) is formed on the gate film161(e.g., by photolithographic patterning), and the gate film161and the insulator film151are sequentially etched by in the presence of the mask pattern, resulting in the gate oxide film150and the gate electrode160. The gate electrode160may have a stripe or strip-like shape, and may be between the pillars130.

After the formation of the gate electrode, and now referring toFIG.11, the body region140is formed. In detail, the body region140may be formed by injecting or implanting a first conductive type dopant into the upper portion of the epitaxial layer120and each of the pillars130with the gate electrode160as a mask. An additional mask (not shown) may be formed by photolithography to block implantation of the first conductive type dopant into regions of the epitaxial layer120in which the body region140is not desired and that are not masked by the gate electrode160.

Then, in order to form the source142, a second conductive type dopant is injected or implanted into the body region140.

For example, referring toFIGS.5and11, the mask pattern M1is formed, covering the edge regions E and part of a cross-directional width of the body region140in the core region C, and then the source142may be formed by injecting the second conductive type dopant into the body region140. Specifically, after the formation of the mask pattern M1covering about half of the cross-directional width of the body region140, the second conductive type dopant may be injected or implanted to form the source142. Thereafter, the mask pattern M1is removed, a new mask (not shown) is formed (e.g., by photolithographic patterning) exposing the area of the body region140in which the body contact144is to be formed (see, e.g.,FIG.4), and a first conductive dopant is injected or implanted into the body region140to form the body contact144. This exposed area of the body region140partially overlaps with the source142to ensure that the body contact144electrically contacts the source142. Therefore, the single source142may be in the body region140along the entire longitudinal length of the core region C. Therefore, the present device may have a channel density that is 50% (or about 50%) of the channel density of the conventional semiconductor device9inFIG.1.

In another embodiment, and now referring toFIG.6, a mask pattern M2may be formed over the edge regions E and in a center region of the body region140along the longitudinal direction, covering the cross-directional width of the body region140. Therefore, the source142is not formed in the center of the body region140along the longitudinal direction in the core region C, and two sources142may be formed in the body region140adjacent to the edge regions E.

In yet another embodiment, and now referring toFIG.7, a mask pattern M3may cover the body region140in the edge regions E and partially cover the body region140in the core region C. The mask pattern M3may be formed by extending a dimension of a conventional mask pattern covering only the edge regions E (see, e.g.,FIG.2), so a processing advantage may arise in this embodiment. As a result, the source142is not formed only in end portions of the body region140along the longitudinal direction (e.g., adjacent to the edge regions E), and two sources142are formed in each body region140in the center of the core region C.

The detailed descriptions disclosed herein are only to illustrate the present disclosure. Furthermore, the foregoing is intended to represent and describe various embodiments of the present disclosure, and the present disclosure may be used in various other combinations, variations, and environments. Changes or modifications are possible within the scope of the concept of the invention disclosed herein, the scope equivalent to the written disclosure, and/or within the scope of skill or knowledge in the art. The above-described embodiments describe the best state for implementing the technical idea of the present disclosure, and various changes in specific application fields and uses of the present disclosure are possible. Therefore, the detailed description of the above invention is not intended to limit the present disclosure to the disclosed embodiments.