Patent ID: 12219779

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The semiconductor industry continues to improve the integration density of various electronic devices (e.g., transistors, diodes, resistors, capacitors, etc.) by, for example, reducing minimum feature sizes and/or arranging electronic devices closer to one another, which allows more components to be integrated into a given area. As the nodes of fabrication continue to shrink, front-end-of-line (FEOL) transistor becomes the major bottleneck to drive high-density non-volatile memories (NVMs), such as in magnetoresistive random access memory (MRAM) devices. MRAM's operation requires a high write current (for example, greater than 200 μA/μm). One way to obtain this high write current is to enlarge transistor dimensions or to adopt multiple transistors for one memory element. For example, some proposed schematics use two transistors or more for one memory element in order to have enough drive current. Those approaches pose a large FEOL area penalty.

In view of above, the present disclosure relates to a back-end-of-line (BEOL) transistor used as a selecting transistor for a memory device and associated manufacturing methods to enable high-density non-volatile memory devices. In some embodiments, the memory device comprises a substrate. A back-end interconnect structure is disposed over the substrate and comprises a plurality of interconnect metal layers one stacked over another. A memory cell is disposed between an upper interconnect metal layer and an intermediate interconnect metal layer. A selecting transistor is disposed between the intermediate interconnect metal layer and a lower interconnect metal layer. By placing the selecting transistor within the back-end interconnect structure between two interconnect metal layers, front-end space is freed-up, and more integration flexibility is provided.

In some further embodiments, the selecting transistor is a planar transistor. A selector gate electrode of the selecting transistor can be disposed on and electrically coupled to the lower interconnect metal layer. A selector channel layer is disposed over the selector gate electrode. A selector source/drain layer is disposed on the selector channel layer. The selector source/drain layer comprises a first selector source/drain region and a second selector source/drain region separated by a sidewall spacer. A portion of the channel layer directly under the sidewall spacer serves as the channel region of the selecting transistor. Thus, a width of the sidewall spacer defines a channel length of the selecting transistor. In some embodiments, the channel layer comprises an oxide semiconductor (OS) material. For example, the channel layer can be made of indium gallium zinc oxide (IGZO). The OS material channel region provides ultra-low leakage currents (ION/IOFF>1013) and can be used to fabricate a BEOL compatible transistor for memory devices. In some embodiments, the selector source/drain regions can have various shapes. For example, the second selector source/drain region can be a circle, a square, a single-fin, a multiple fin, an oval or other application shapes. The sidewall spacer surrounds the second selector source/drain region, and the first selector source/drain region enclose outer peripherals of the sidewall spacer.

Also in some embodiments, the memory cell comprises a bottom electrode and a top electrode separated by a data storage structure. The selecting transistor may be connected to the bottom electrode of the memory cell through the intermediate interconnect metal layer. The storage structure and the top electrode are stacked over the bottom electrode. In some embodiments, the data storage structure is a magnetic tunnel junction (MTJ) or a spin-valve. In such cases, the memory cell is referred as a magnetic memory cell, and the memory device made of an array of such memory cells is referred as a MRAM device. In some alternative embodiments, the data storage structure is a metal-insulator-metal (MIM) stack, and the memory cell may be a resistance memory cell. Other structures for the data storage structure and/or other memory cell types for the memory cell are also amenable.

FIG.1illustrates a cross-sectional view of some embodiments of a memory device100comprising a selecting transistor118. In some embodiments, the memory device100comprises a memory cell108disposed within an interconnect structure104over a substrate102. The interconnect structure104comprises stacked interconnect metal layers disposed within stacked inter-level dielectric (ILD) layers. In some embodiments, the stacked ILD layers comprise a lower ILD layer104L arranged between the memory cell108and the substrate102, and an upper ILD layer104U surrounding the memory cell108. The lower ILD layer104L and the upper ILD layer104U may each comprise one or more dielectric layer. In some embodiments, the stacked interconnect metal layers comprise a lower interconnect metal layer130, an intermediate interconnect metal layer106stacked over the lower interconnect metal layer130, and an upper interconnect metal layer116disposed over the intermediate interconnect metal layer106.

The memory cell108may comprise a bottom electrode110, a data storage structure112arranged over the bottom electrode110, and a top electrode114arranged over the data storage structure112. The upper interconnect metal layer116extends through the upper ILD layer104U to reach on the top electrode114. In some embodiments, the bottom electrode110and the top electrode114may comprise tantalum nitride, titanium nitride, tantalum, titanium, platinum, nickel, hafnium, zirconium, ruthenium, iridium, or the like. In some embodiments, the data storage structure112is a magnetic tunnel junction (MTJ) or a spin-valve. In such cases, the memory cell108is referred as a magnetic memory cell, and the memory device100made of an array of such memory cells108is referred as a magnetoresistive random access memory (MRAM) device. In such embodiments, the data storage structure112may comprise a magnetic tunnel junction, a ferroelectric capacitor or junction, or the like. In some alternative embodiments, the data storage structure112is a metal-insulator-metal (MIM) stack, and the memory cell108may be a resistance memory cell. In such cases, the memory cell108is referred as a resistive memory cell, and the memory device100made of an array of such memory cells108is referred as a RRAM device. In such embodiments, the data storage structure112comprises a high-k dielectric material, such as hafnium dioxide (HfO2), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), tantalum pentoxide (Ta2O5), hafnium aluminum oxide (HfAlO), hafnium zirconium oxide (HfZrO), or the like. Other structures for the data storage structure112and/or other memory-cell types for the memory cell108are also amenable.

In some embodiments, the selecting transistor118is electrically coupled to the bottom electrode110of the memory cell108through the intermediate interconnect metal layer106. In some embodiments, a source/drain layer134is disposed under the intermediate interconnect metal layer106. The source/drain layer134comprises a first selector source/drain region120and a second selector source/drain region122separated by a sidewall spacer128. A selector channel layer126is disposed under the source/drain layer134. A selector gate dielectric layer132is disposed under the selector channel layer126and separating a selector gate electrode124from the selector channel layer126. The selector gate electrode124may be disposed on a lower interconnect metal layer130and surrounded by the lower ILD layer104L. During operation, a drain-source voltage is applied between the first selector source/drain region120and the second selector source/drain region122. A gate-source voltage is applied between the selector gate electrode124and the first selector source/drain region120. If the gate-source voltage is sufficient, a channel path in the selector channel layer126is turned on connecting the first selector source/drain region120and the second selector source/drain region122. A width of the sidewall spacer128defines a channel length Lc of the selecting transistor118in the selector channel layer126directly under the sidewall spacer128. An interface perimeter between the sidewall spacer128and the second selector source/drain region122defines a channel width of the selecting transistor118.

In some embodiments, the first selector source/drain region120and the second selector source/drain region122comprise doped semiconductor material (e.g., p-doped or n-doped polysilicon), and/or Titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), copper (Cu), or other CMOS contact metals. The first selector source/drain region120and the second selector source/drain region122may each have a thickness in a range of from about 10 nm to about 50 nm. In some embodiments, the sidewall spacer128may be a single layer of non-conductive material. In some alternative embodiments, the sidewall spacer128may include multiple layers of the same or different materials collectively insulating the second selector source/drain region122from the first selector source/drain region120. For example, the sidewall spacer128may comprise a dielectric material or multiple dielectric materials such as silicon dioxide, silicon nitride, or the like. The sidewall spacer128can have a thickness in a range of from about 5 nm to about 30 nm. In some embodiments, the selector channel layer126comprises an oxide semiconductor (OS) material. For example, the channel layer can be made of such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium tin oxide or indium titanium oxide (ITO), or another oxide semiconductor material. The selector channel layer126can have a thickness in a range of from about 3 nm to about 50 nm, or about 5 nm to about 30 nm. The OS material channel region provides ultra-low leakage and can be used to fabricate a BEOL compatible transistor for memory devices. In some embodiments, the selector gate dielectric layer132comprise aluminum oxide (Al2O3), Hafnium oxide (HfO2), tantalum oxide (Ta2O5), Zirconium oxide (ZrO2), Titanium oxide (TiO2), strontium titanium oxide (SrTiO3), or another high-k dielectric material, among others. The selector gate dielectric layer132may have a thickness in a range of from about 1 nm to about 15 nm, or about 1 nm to about 5 nm. By placing the selecting transistor within back-end interconnect structure between two interconnect metal layers, front-end becomes available for novel logic functions, and more integration flexibility is provided.

FIG.2illustrates a cross-sectional view of a memory device200comprising a selecting transistor118according to some additional embodiments with more details. In some embodiments, a logic device202is disposed within a substrate102. The logic device202may comprise a transistor device (e.g., a MOSFET device, a BJT, or the like). An interconnect structure104is disposed over the logic device202and the substrate102. The interconnect structure104comprises a plurality of stacked ILD layers104a-104ethat laterally surround a plurality of interconnect metal layers configured to provide electrically connection. In some embodiments, the interconnect metal layers may comprise a conductive contact204landing on the logic device202and interconnect lines206a-206cand interconnect vias disposed over the conductive contact204and surrounded by the plurality of stacked ILD layers104a-104e.

In some embodiments, a first interconnect line206ais disposed within a second ILD layer104bover the first ILD layer104a. The first interconnect line206amay function as a word line of the memory device200. The selecting transistor118comprises a selector gate electrode124stacked on the first interconnect line206aand configured to control current flow between a first selector source/drain region120and a second selector source/drain region122through a selector channel layer126. In some embodiments, the selector gate electrode124may comprise the same conductive material as the first interconnect line206aand may be seamless from the first interconnect line206a. Alternatively, the selector gate electrode124may comprise a conductive material different from the first interconnect line206a. A selector gate dielectric layer132may be disposed between the selector gate electrode124and the selector channel layer.

In some embodiments, the first selector source/drain region120and the second selector source/drain region122are disposed on the selector channel layer126and separated from each other by a sidewall spacer128. The sidewall spacer128may enclose an outer sidewall of the second selector source/drain region122. The first selector source/drain region120may enclose an outer sidewall of the sidewall spacer128and may be surrounded by a third ILD layer104c. In some embodiments, a dielectric layer222is disposed on the first selector source/drain region120and the third ILD layer104cand surround the sidewall spacer128or the second selector source/drain region122. In some embodiments, the sidewall spacer128covers a sidewall surface of the second selector source/drain region122. The first selector source/drain region120and the dielectric layer222may collectively cover an outer sidewall of the sidewall spacer128. In some embodiments, the dielectric layer222may comprise dielectric materials such as silicon dioxide, silicon nitride, or the like. The dielectric layer222can have a thickness in a range of from about 1 nm to about 5 nm.

In some embodiments, the first selector source/drain region120is coupled to a source line SL. The second selector source/drain region122is coupled to the memory cell108through a second interconnect line206b, which is surrounded by a fourth ILD layer104d. The second interconnect line206bmay be arranged over the first selector source/drain region120and separating from the first selector source/drain region120by the dielectric layer222.

In some embodiments, a lower insulating structure210is disposed over the fourth ILD layer104d. The lower insulating structure210comprises sidewalls that define an opening extending through the lower insulating structure210. In various embodiments, the lower insulating structure210may comprise one or more of silicon nitride, silicon dioxide, silicon carbide, or the like. A bottom electrode via212is disposed in the opening of the lower insulating structure210and lands on the second interconnect line206b. The memory cell108is arranged on the bottom electrode via212. In some embodiments, the memory cell108comprises a bottom electrode110that is separated from a top electrode114by way of a data storage structure112. In some embodiments, a hard mask layer216may be disposed on the top electrode114. A sidewall spacer218may be disposed on opposing sides of the top electrode114and the hard mask layer216. In some embodiments, the hard mask layer216may comprise a metal (e.g., titanium, tantalum, or the like) and/or a dielectric (e.g., a nitride, a carbide, or the like). In some embodiments, the sidewall spacer218may comprise an oxide (e.g., silicon rich oxide), a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), or the like.

In some embodiments, an upper insulating structure220is disposed over the memory cell108and on the lower insulating structure210. The upper insulating structure220continuously extends from a first position directly over the memory cell108to a second position abutting an upper surface of the lower insulating structure210. The upper insulating structure220separates the memory cell108from a fifth ILD layer104e. The upper insulating structure220may comprise one or more dielectric materials such as silicon nitride, silicon dioxide, silicon carbide, or the like. In some embodiments, an upper interconnect metal layer116extends through the fifth ILD layer104eto electrically contact the top electrode114. The upper interconnect metal layer116may comprise a top electrode via214disposed through the hard mask layer216and the upper insulating structure220and a third interconnect line206cconnecting to the top electrode via214. The third interconnect line206cmay function as a bit line of the memory device200.

During operation, signals (e.g., voltages and/or currents) may be selectively applied to the word line WL, the source line SL, and the bit line BL to read data from and to write data to the memory cell108.

FIG.3illustrates a cross-sectional view of a memory device300comprising a selecting transistor118according to some additional embodiments. The memory device300comprises a substrate102including a memory region302and a logic region304. The logic region304may comprise a logic device306arranged within the substrate102. For example, the logic device306may include a transistor comprising a first source/drain region306a, a second source/drain region306bseparated from the first source/drain region306aby a channel region, and a gate structure306cdisposed over the channel region. A conductive contact204may land on the first source/drain region306aor the second source/drain region306b. Similarly, another logic device202may be arranged within the substrate102in the memory region302. In some alternative embodiments, the logic devices202,306may be FinFET devices, nanowire devices, or other gate-all-around (GAA) devices. Thus, more integration flexibility is provided by utilizing the BEOL selecting transistor.

An interconnect structure104is disposed over the substrate102overlying the logic devices202,306. The interconnect structure104comprises a plurality of metal layers one stacked over another and including stacked metal lines206a-206eand metal vias208a-208edisposed within stacked ILD layers104a-104f. In some embodiments, the plurality of stacked ILD layers104a-104fmay comprise one or more of silicon dioxide, a fluorosilicate glass, a silicate glass (e.g., borophosphate silicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), or the like. In some embodiments, adjacent ILD layers104a-104fmay be separated by an etch stop layer (not shown) comprising a nitride, a carbide, or the like. The plurality of metal layers is referred by numerals in industry as M0, M1, M2, M3. . . from a lower position closer to the substrate to an upper position away from the substrate. M0is referred to a metal layer closest to the substrate and comprising metal lines electrically coupling to active regions of the logic devices through conductive contacts204. M1(not shown) is referred to a next metal layer stacked over the metal layer M0and comprising metal lines electrically coupling to metal lines of the metal layer M0through metal vias. Similarly, Mn+1 is referred to a next metal layer stacked over an underlying metal layer Mn and comprising metal lines electrically coupling to metal lines of the underlying metal layer Mn through metal vias, n is a positive integral number. It is emphasized that though some specific metal layer numbers are given hereafter, such as M6, M7, M8, M9, M10, etc., these specific numbers are not for limiting purpose, and various metal layers can be used for different applications.

A memory cell108is disposed between an upper interconnect metal layer116and an intermediate interconnect metal layer106, for example, between M10and M8as shown inFIG.3. In some embodiments, the memory cell108is inserted within one or more interconnect metal layers (for example, M9) between the intermediate interconnect metal layer106and the upper interconnect metal layer116(for example, between M8and M10). The memory cell108may comprise a bottom electrode110that is separated from a top electrode114by way of a data storage structure112. A hard mask layer216may be disposed on the top electrode114. A sidewall spacer218may be disposed on opposing sides of the top electrode114the hard mask layer216. In some embodiments, a selecting transistor118is connected to the bottom electrode110of the memory cell108. The selecting transistor118is disposed between the intermediate interconnect metal layer106and a lower interconnect metal layer130, for example, between M8and M6as shown inFIG.3.

In some embodiments, the selecting transistor118is inserted within one or more interconnect metal layer (for example, M7) between the intermediate interconnect metal layer106and the lower interconnect metal layer130(for example, between M8and M6). A selector gate electrode124of the selecting transistor118is disposed within a dielectric layer and electrically coupled to the lower interconnect metal layer130. A selector gate dielectric layer132and a selector channel layer126may be disposed in the memory region302on the selector gate electrode124and the surrounding dielectric layer. A first selector source/drain region120and a second selector source/drain region122may be disposed in the memory region302on the selector channel layer126and separated from each other by a sidewall spacer128. In some embodiments, the first selector source/drain region120is coupled to a source line SL. The second selector source/drain region122is coupled to the memory cell108through one or more interconnect lines206cand one or more interconnect vias208c, which is surrounded by one or more ILD layers.

As noted above, the selecting transistor118and the memory cell108can be flexibly positioned within various metal layers. In some embodiments, the selecting transistor118is located above fourth interconnect metal layer M4, and thus at least four interconnect metal layers (M1, M2, M3, M4) are disposed between the selector gate electrode124and the substrate102. Per routing needs, the interconnect structure104has denser metal lines with a smaller size in a lower metal layer than in an upper metal layer. It would consume precious routing area if the selecting transistor118is positioned within a metal layer lower than the fourth interconnect metal layer M4. Above the fourth interconnect metal layer M4, exact location of the selecting transistor118can be determined with reference to the routing needs, and thus provide design flexibility.

FIG.4illustrates a block diagram of a portion of a memory array400having a plurality of memory units C11-C33. The memory units C11-C33are arranged within the memory array400in rows and/or columns. The memory array400comprises a plurality of selecting transistors118correspondingly connected to a plurality of memory cells108. In some embodiments, device structures disclosed associated withFIG.1,FIG.2, orFIG.3can be incorporated as some embodiments of the individual memory units C11-C33of the memory array400. The plurality of selecting transistors118is disposed within an interconnect structure between a lower interconnect metal layer and an upper interconnect metal layer of the interconnect structure.

Although the memory array400is illustrated as having 3 rows and 3 columns, the memory array400may have any number of rows and any number of columns. Each of the memory units C11-C33may include a memory cell108coupled to a selecting transistor118. The selecting transistor118is configured to selectively provide access to the memory cell108selected while inhibiting leakage currents through non-selected memory units.

The memory units C11-C33may be controlled through bit-lines BL1-BL3, word-lines WL1-WL3, and source lines SL1-SL3The word-lines WL1-WL3may be used to operate the selecting transistors118corresponding to the memory units C11-C33. When a selecting transistor118for a memory cell108is turned on, a voltage may be applied to that memory cell. A bit line decoder119applies a read voltage or a write voltage to one of the bit-lines BL1-BL3. A word line decoder127applies another voltage to one of the word-lines WL1-WL3, which turns on the selecting transistor118for the memory units C11-C33in a corresponding row. Together, these operations cause the read voltage or the write voltage to be applied to a selected memory unit among the memory units C11-C33.

Appling a voltage to a selected memory cell108results in a current. During read operations, a sense amplifier117determines the programming state of the selected memory cell based on the current. The sense amplifier117may be connected to source lines SL1-SL3. Alternatively, the sense amplifier117may be connected to bit-lines BL1-BL3. The sense amplifier117may determine the programming state of the memory cell108based on the current. In some embodiments, the sense amplifier117determines the programming state of the memory cell108by comparing the current to one or more reference currents. The sense amplifier117may convey the programming state determination to an I/O buffer, which may be coupled to a driver circuit to implement write and write verify operations. The driver circuit is configured to select a voltage to apply to selected memory unit for read, write, and write-verify operations.

It will be appreciated that the voltage of significance is an absolute value of a potential difference across the memory cell108. For the memory array400, applying a voltage to a selected memory cell means operating a word line WL1-WL3to turn on the selecting transistor118corresponding to that memory cell and using the driver circuit to make the absolute value of the potential difference between the source line SL1-SL3and the bit line BL1-BL3corresponding to that cell equal in magnitude to that voltage. In some embodiments, applying a voltage to a memory cell is accomplished by coupling a corresponding bit line BL1-BL3to the voltage while holding a corresponding source line SL1-SL3at a ground potential. Also, source lines SL1-SL3may be held at other potentials and the roles bit-lines BL1-BL3, and source line SL1-SL3may be reversed.

FIG.5illustrates a cross-sectional view500of the memory array400ofFIG.4along a row direction according to some embodiments. For example, memory units shown inFIG.5can be the memory units C11, C12, and C13ofFIG.4. Besides device structures disclosed associated withFIG.1,FIG.2, orFIG.3, as shown inFIG.4andFIG.5, in some embodiments, the memory units of one row, e.g., C11, C12, and C13, may share a common bit line BL1connecting individual memory cells108through individual top electrode vias214.

FIG.6illustrates a cross-sectional view600of the memory array400ofFIG.4along a column direction according to some embodiments. For example, memory units shown inFIG.6can be the memory units C11, C21, and C31ofFIG.4. Besides device structures disclosed associated withFIG.1,FIG.2, orFIG.3, as shown inFIG.4andFIG.6, in some embodiments, the memory units of one column, e.g., C11, C21, and C31, may share a common gate electrode or has individual gate electrodes connecting to a common word line WL1connecting individual selecting transistors118through individual selector gate electrodes124.

FIGS.7A-7Dillustrate top views700a-700dof the memory array400ofFIG.4showing corresponding selecting transistors118according to some embodiments. As shown byFIGS.7A-7D, the first selector source/drain regions120and the second selector source/drain regions122can have various shapes. For example, the second selector source/drain regions122can be discrete islands enclosed by the sidewall spacers128. The sidewall spacers128can have discrete ring shapes. The first selector source/drain region120encloses an outer peripheral of the sidewall spacer128. In such embodiments, a width of the sidewall spacer128defines a channel length of the selecting transistor118, and a perimeter of the second selector source/drain region122defines a channel width of the selecting transistor118. As an example, the channel length Lc can be in a range of from about 5 nm to about 30 nm. The channel width can be in a range of from about 50 nm to about 500 nm. A resulted drain-source current can reach a range of from about 50 μA to about 100 μA.

In some embodiments, the second selector source/drain region122can have a centro-symmetrical shape such as a round circle as shown inFIG.7A, a square, or other orthopolygons. In some alternative embodiments, the second selector source/drain region122can have an axial symmetrical shape that is longer in a length direction of the shared first selector source/drain region120than a width direction of the shared first selector source/drain region120, such that an area of the second selector source/drain region122can be enlarged by arranging a longer length of the second selector source/drain region122. Examples of such second selector source/drain region122include an oval as shown inFIG.7B, or a rectangular as shown inFIG.7C. In some further alternative embodiments, the second selector source/drain region122may include multiple fins to further enlarge perimeters of the second selector source/drain region122, i.e., the channel width of the selecting transistor118. As a result, the drain current of the selecting transistor can be further increased.FIG.7Dshows the second selector source/drain region122having two rectangular fins as an example of those embodiments. Other applicable shapes not shown in the figures (e.g., a square, multiple round fins, etc.) are also amenable.

FIGS.8-17illustrate cross-sectional views800-1700of some embodiments of a method of forming a memory device comprising a BEOL selecting transistor. AlthoughFIGS.8-17are described in relation to a method, it will be appreciated that the structures disclosed inFIGS.8-17are not limited to such a method, but instead may stand alone as structures independent of the method.

As shown in a cross-sectional view800ofFIG.8, a substrate102is provided. In various embodiments, the substrate102may be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and/or one or more die on a wafer, as well as any other type of semiconductor and/or epitaxial layers, associated therewith. The substrate102comprises a memory region302and a logic region304. In some embodiments, a logic device306is formed within the substrate102. The logic device306may be formed in the memory region302or the logic region304. The logic device306may comprise a transistor formed by depositing and patterning a gate dielectric film and a gate electrode film over the substrate102to form a gate dielectric and a gate electrode. The substrate102may be subsequently implanted to form a source region and a drain region within the substrate102on opposing sides of the gate electrode.

In some embodiments, one or more lower interconnect metal layers may be formed within one or more lower ILD layers formed over the logic device306and the substrate102. In some embodiments, the one or more lower interconnect metal layers may comprise one or more of a conductive contact204formed in a first ILD layer104a, a first interconnect line206aand a first interconnect via208aformed in a second ILD layer104b, and more interconnect lines and vias stacked thereover (not shown). The one or one or more lower interconnect metal layers may be formed by repeatedly forming a lower ILD layer (e.g., an oxide, a low-k dielectric, or an ultra-low-k dielectric) over the substrate102, selectively etching the lower ILD layer to define a via hole and/or a trench within the lower ILD layer, forming a conductive material (e.g., copper, aluminum, etc.) within the via hole and/or the trench, and performing a planarization process (e.g., a chemical mechanical planarization process) to remove excess of the conductive material from over the lower ILD layer. The conductive contact204, the interconnect line206a/206b, and the interconnect via208ashown inFIG.8are drawn for illustration purpose, and more or fewer layers of interconnect lines, vias and lower ILD layers in either memory region302or the logic region304can be adjusted by various applications.

As shown in a cross-sectional view900ofFIG.9, a selector gate electrode124is formed within the second ILD layer104b. The selector gate electrode124may be formed by selectively etching the second ILD layer104bto define a trench within the second ILD layer104b, forming a conductive material (e.g., tungsten, copper, aluminum, etc.) within the trench, and performing a planarization process (e.g., a chemical mechanical planarization process) to remove excess of the conductive material from over the second ILD layer104b. In some embodiments, the selector gate electrode124is formed by a conductive material same with the first interconnect line206aand the first interconnect via208a. In some alternative embodiments, the selector gate electrode124is formed by a conductive material different from the first interconnect line206aand the first interconnect via208a. In some embodiments, the selector gate electrode124is formed by a deposition process followed by a planarization process (e.g., a chemical mechanical planarization process), and can have a thickness in a range of from about 5 nm to about 20 nm.

As shown in a cross-sectional view1000ofFIG.10, a selector gate dielectric layer132and a selector channel layer126is formed on the selector gate electrode124and the second ILD layer104b. In some embodiments, the selector gate dielectric layer132and the selector channel layer126are respectively formed by deposition techniques, such as atomic layer depositions. The selector gate dielectric layer132can have a thickness in a range of from about 1 nm to about 15 nm. The selector channel layer126can have a thickness in a range of from about 3 nm to about 50 nm. In some embodiments, the selector gate dielectric layer132comprise aluminum oxide (Al2O3), Hafnium oxide (HfO2), tantalum oxide (Ta2O5), Zirconium oxide (ZrO2), Titanium oxide (TiO2), strontium titanium oxide (SrTiO3), or another high-k dielectric material, among others. In some embodiments, the selector channel layer126comprises an oxide semiconductor (OS) material. For example, the channel layer can be made of such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium tin oxide or indium titanium oxide (ITO), or another oxide semiconductor material.

As shown in a cross-sectional view1100ofFIG.11, a third ILD layer104cis formed on the selector channel layer126, and a first selector source/drain layer120′ is formed within the third ILD layer104c. In some embodiments, the first selector source/drain layer120′ is formed as a plurality of parallel lines vertically crossed from the selector gate electrode124from a top view. An example of patterns of the selector gate electrode124and the first selector source/drain layer120′ can be found inFIGS.7A-7D. In some embodiments, the first selector source/drain layer120′ is formed by a deposition process followed by a patterning process. The first selector source/drain layer120′ can have a thickness in a range of from about 10 nm to about 50 nm. In some embodiments, the first selector source/drain layer120′ can be formed by titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), copper (Cu), or other CMOS contact metals and/or doped semiconductor material (e.g., p-doped or n-doped polysilicon).

As shown in a cross-sectional view1200ofFIG.12, the first selector source/drain layer120′ is patterned to form an opening1202there through and leaving a remaining portion as a first selector source/drain region120. The opening1202may be formed by a selective etching process that etches through the first selector source/drain layer120′ and stops on the selector channel layer126.

In some embodiments, a dielectric layer222is formed on the first selector source/drain layer120′ and the third ILD layer104cprior to forming the opening1202. The dielectric layer222may be patterned and may function as a hard mask for the formation of the opening1202. The dielectric layer222may be formed by a deposition process followed by a planarization process (e.g., a chemical mechanical planarization process), and may comprise oxide material such as silicon dioxide. In some embodiments, the dielectric layer222can have a thickness in a range of from about 1 nm to about 5 nm.

As shown in a cross-sectional view1300ofFIG.13, a sidewall spacer128is formed along a sidewall of the opening1202. In some embodiments, the sidewall spacer128is formed by depositing a conformal dielectric layer followed by an etching process to expose the selector channel layer126. In some embodiments, the etching process may be or be comprised of an anisotropic etch (e.g. a vertical dry etch) that removes lateral portions of the conformal dielectric layer including the portion overlying the selector channel layer126while leaving a vertical portion of the conformal dielectric layer on the sidewall of the opening1202. In some alternative embodiments, the lateral portion of the conformal dielectric layer overlying the selector channel layer126is removed, while the lateral portions of the conformal dielectric layer are kept for the final device structure. The sidewall spacer128may be formed by dielectric materials such as silicon dioxide, silicon nitride, or the like. In some embodiments, the sidewall spacer128can have a thickness in a range of from about 5 nm to about 30 nm. As the thickness of the sidewall spacer128further decreases, for example, smaller than 5 nm or 3 nm range, a source/drain leakage may be introduced. As the thickness of the sidewall spacer128further increases, for example, greater than 30 nm, a driving current is reduced, and thus the transistor performance degrades.

As shown in a cross-sectional view1400ofFIG.14, a second selector source/drain region122is formed in the opening1202. In some embodiments, the second selector source/drain region122is formed by depositing a conductive material in the opening1202followed by a planarization process remove excessive portions outside the opening1202. The second selector source/drain region122may have a top surface coplanar with those of the sidewall spacer128and/or the dielectric layer222. In some embodiments, the sidewall spacer128covers a sidewall surface of the second selector source/drain region122. The first selector source/drain region120and the dielectric layer222may collectively cover an outer sidewall of the sidewall spacer128. In some embodiments, the second selector source/drain region122can have a thickness in a range of from about 10 nm to about 50 nm. The thickness of the second selector source/drain region122may be same or greater than that of the first selector source/drain region120. In some embodiments, the second selector source/drain region122can be formed by titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), copper (Cu), or other CMOS contact metals and/or doped semiconductor material (e.g., p-doped or n-doped polysilicon).

As shown in a cross-sectional view1500ofFIG.15, a fourth ILD layer104dis formed over the first selector source/drain region120and the second selector source/drain region122, and an intermediate interconnect metal layer is formed and electrically coupled to the second selector source/drain region122. For example, a second interconnect via208bmay be formed through the fourth ILD layer104dand reach on the second selector source/drain region122, and a second interconnect line206bmay be formed on the second interconnect via208bwithin the fourth ILD layer104d. In some embodiments, the fourth ILD layer104dis formed by a deposition process followed by a patterning process to form vias and trenches for subsequent formation of the intermediate interconnect metal layer. The second interconnect via208band the second interconnect line206bmay then be deposited in the vias and trenches followed by a planarization process (e.g., a chemical mechanical planarization process).

As shown in a cross-sectional view1600ofFIG.16, a lower insulating structure210is formed over the second interconnect line206band the fourth ILD layer104d. In some embodiments, the lower insulating structure210comprises a plurality of different stacked dielectric materials. As an example, the lower insulating structure210may comprise silicon rich oxide, silicon carbide, silicon nitride, or the like. In some embodiments, the lower insulating structure210may be formed by one or more deposition processes (e.g., a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a plasma enhanced CVD (PE-CVD) process, or the like). In some embodiments, the lower insulating structure210is selectively etched to define an opening that extends through the lower insulating structure210and exposes an upper surface of the intermediate interconnect metal layer. A bottom electrode via212may be formed within the opening.

As shown in cross-sectional view1700ofFIG.17, a memory device stack is formed and patterned over the lower insulating structure210to form a memory cell108. The memory device stack is formed by a plurality of different deposition processes such as CVD, PE-CVD, sputtering, ALD, or the like. The memory device stack is patterned by one or more patterning processes. In some embodiments, a first patterning process is performed to define a top electrode114and a data storage structure112and according to a hard mask layer216. In various embodiments, the hard mask layer216may comprise a metal (e.g., titanium, titanium nitride, tantalum, or the like) and/or a dielectric material (e.g., silicon-nitride, silicon-carbide, or the like). A sidewall spacer218may then be formed along sidewalls of the data storage structure112, the top electrode114, and the hard mask layer216. In various embodiments, the sidewall spacer218may comprise silicon nitride, silicon dioxide, silicon oxynitride, and/or the like. In some embodiments, the sidewall spacer218may be formed by forming a spacer layer over the substrate102. The sidewall spacer layer is subsequently exposed to an etchant (e.g., a dry etchant), which removes the sidewall spacer layer from horizontal surfaces. Removing the sidewall spacer layer from horizontal surfaces leaves a part of the sidewall spacer layer along opposing sidewalls of the data storage structure112, the top electrode114, and the hard mask layer216as the sidewall spacer218. Then, a second patterning process is performed to a bottom metal layer to define a bottom electrode110not covered by the hard mask layer216and the sidewall spacer218.

As shown in cross-sectional view1800ofFIG.18, an upper insulating structure220is formed over the memory cell108. In some embodiments, the upper insulating structure220may be formed using one or more deposition techniques (e.g., PVD, CVD, PE-CVD, ALD, sputtering, etc.). In various embodiments, the upper insulating structure220may comprise one or more of silicon carbide, tetraethyl orthosilicate (TEOS), or the like. An upper ILD layer104U is formed over the upper insulating structure220as a part of an interconnect structure104over the substrate102. In some embodiments, the upper ILD layer104U may be formed by a deposition process (e.g., PVD, CVD, PE-CVD, ALD, or the like). In various embodiments, the upper ILD layer104U may comprise one or more of silicon dioxide, carbon doped silicon dioxide, silicon oxynitride, BSG, PSG, BPSG, FSG, USG, a porous dielectric material, or the like. Then, third interconnect vias208cand third interconnect lines206care formed within the upper ILD layer104U. In the memory region302, the third interconnect via208cand the third interconnect line206cmay be formed within the upper ILD layer104U on top of the memory cell108to expose an upper surface of the top electrode114. In the logic region304, the third interconnect via208cand the third interconnect line206cmay extend from a top surface of the upper ILD layer104U to vertically past the memory cell108and further extend through the upper insulating structure220and the lower insulating structure210and reach on a lower interconnect metal layer.

FIG.19illustrates a flow diagram of some embodiments of a method1900of forming a memory device comprising a BEOL selecting transistor.

While method1900is illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

At act1902, a substrate is prepared, and a lower interconnect metal layer is formed within a lower inter-level dielectric (ILD) layer over the substrate. In some embodiments, logic devices may be formed within the substrate in a memory region and/or a logic region prior to forming the lower interconnect metal layer.FIG.8illustrates the cross-sectional view800of some embodiments corresponding to act1902.

At act1904, a BEOL selecting transistor is formed over the lower interconnect metal layer. In some embodiments, the selecting transistor may be formed according to acts1906-1916.

At act1906, a select gate electrode is formed on the lower interconnect metal layer.FIG.9illustrates the cross-sectional view900of some embodiments corresponding to act1906.

At act1908, a selector channel layer is formed over the select gate electrode.FIG.10illustrates the cross-sectional view1000of some embodiments corresponding to act1908.

At act1910, a first selector source/drain region is formed over the selector channel layer.FIG.11illustrates the cross-sectional view1100of some embodiments corresponding to act1910.

At act1912, a dummy dielectric layer is formed on the first selector source/drain region.FIG.12illustrates the cross-sectional view1200of some embodiments corresponding to act1912.

At act1914, a sidewall spacer is formed along an opening of the dummy dielectric layer and the first selector source/drain region.FIG.13illustrates the cross-sectional view1300of some embodiments corresponding to act1914.

At act1916, a second selector source/drain region is formed within the opening and separated from the first selector source/drain region by the sidewall spacer.FIG.14illustrates the cross-sectional view1400of some embodiments corresponding to act1916.

At act1918, an intermediate interconnect metal layer is formed over the BEOL selecting transistor.FIG.15illustrates the cross-sectional view1500of some embodiments corresponding to act1918.

At act1920, a memory cell is formed over the intermediate interconnect metal layer.FIGS.16-17illustrate the cross-sectional views1600-1700of some embodiments corresponding to act1920.

At act1922, an upper interconnect metal layer is formed over the memory cell.FIG.18illustrates the cross-sectional view1800of some embodiments corresponding to act1922.

Accordingly, in some embodiments, the present disclosure relates to a memory device (e.g., an MRAM or RRAM device) having a BEOL selecting transistor layer inserted between two BEOL interconnect metal layers.

In some embodiments, the present disclosure relates to a memory device. The memory device comprises a substrate and a lower interconnect metal layer disposed over the substrate. A selecting transistor is disposed over the lower interconnect metal layer. A memory cell is disposed over the selecting transistor and comprises a bottom electrode electrically connected to the selecting transistor, a data storage structure disposed over the bottom electrode, and a top electrode disposed over the data storage structure.

In other embodiments, the present disclosure relates to a memory device. The memory device comprises a substrate and an interconnect structure disposed over the substrate. The interconnect structure is disposed over the substrate and comprises a plurality of interconnect metal layers one stacked over another. A plurality of memory cells is disposed within the interconnect structure and arranged in an array of rows and columns. A plurality of selecting transistors is disposed within the interconnect structure and correspondingly connected to the plurality of memory cells.

In yet other embodiments, the present disclosure relates to a memory device. The memory device comprises a selecting transistor disposed over a substrate. The selecting transistor comprises a selector channel layer, a selector gate electrode disposed on one side of the selector channel layer, and a first selector source/drain region and a second selector source/drain region disposed on the other side of the selector channel layer opposite to the selector gate electrode from a cross-sectional view. The first selector source/drain region and the second selector source/drain region are separated by a sidewall spacer having a ring-shape and enclosing the first selector source/drain region from a top view. A memory cell is disposed over the selecting transistor and electrically connected to the first selector source/drain region.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.