Patent ID: 12230317

DETAILED DESCRIPTION

Various implementations described herein are directed to column multiplexing schemes and techniques that may improve memory access operations in various physical memory layout designs. For instance, various schemes and techniques described herein may provide for a system or a device having a unique memory architecture that matches retention delay with clock-to-data output (CLK2Q) delay for mux-8, mux-16 and multi-bank memory applications. In some instances, the memory architecture may include multiple bitcell arrays, column multiplexer circuitry and control circuitry. The column multiplexer circuitry may be coupled to the memory architecture via multiple bitlines for read access operations, and the column multiplexer circuitry may perform read access operations in the multiple bitcell arrays via the bitlines based on a sense amplifier enable signal and a read multiplexer signal. The control circuitry may provide the read multiplexer signal to the column multiplexer circuitry based on a clock signal and the sense amplifier enable signal so that the column multiplexer circuitry performs read access operations.

Various implementations of column multiplexing schemes and techniques will be described in detail herein with reference toFIGS.1-8.

FIG.1illustrates a diagram100of memory circuitry102in accordance with various implementations described herein.

In various implementations, the memory circuitry102may be implemented as a system or a device having various integrated circuit (IC) components that are arranged and coupled together as an assemblage or combination of parts that provide for a physical circuit design and related structures. In some instances, a method of designing, providing and building the memory circuitry102as an integrated system or device that may involve use of various IC circuit components described herein so as to thereby implement column multiplexing schemes and techniques associated therewith. The memory circuitry102may be integrated with computing circuitry and related components on a single chip, and the memory circuitry102may be implemented in some embedded systems for electronic, mobile and Internet-of-things (IoT) applications, including sensor nodes.

As shown inFIG.1, the memory circuitry102may be referred to as memory architecture having various circuitry including an address decoder106, multiple banks of bitcell arrays104A,104B, clock generation circuitry110, column multiplexer circuitry124, and dummy wordline (DWL) circuitry associated with DWL loads114A,114B. The column multiplexer circuitry124may include column multiplexers126A,126B,128A,128B, sense amplifiers120A,120B, and output drivers132A,132B. The memory circuitry102may include various control circuitry, such as, e.g., first control logic116A and second control logic116B. The memory circuitry102may also include the dummy wordline (DWL) driver (id), the dummy wordline (DWL) loads114A,114B, and delay logic (Delay_N)112that are coupled to the dummy wordline DWL. The output drivers132A,132B may include a first output driver132A configured to provide a first output data signal (QA) and a second output driver132B configured to provide a second data output signal (QB).

The address decoder106may be coupled to the multiple banks of bitcell arrays104A,104B via wordline drivers (i0, . . . , in). The multiple banks of bitcell arrays104A,104B may include a first bitcell array104A and a second bitcell array104B that is different than the first bitcell arrays104A, and each bitcell array104A,104B may have multiple rows of bitcells row_0, . . . , row_n. The column multiplexers (Colmux)126A,126B,128A,128B and the sense amplifiers120A,120B may be coupled to each of the bitcells in each of the rows of bitcells row_0, . . . , row_n via complementary bitlines (BL/NBL[0:3]). Each bitcell array104A,104B may use a number of inverted wordlines (e.g., nwl_0, . . . , nwl_n) that are coupled between address decoder106and corresponding rows of bitcells row_0, . . . , row_n for access to each of the bitcells based on selected wordlines. Also, each of the inverted wordlines nwl_0, . . . , nwl_n may have a corresponding wordline driver (e.g., inverters i0, . . . , in) coupled thereto to provide wordlines signals (e.g., wl_0, . . . , wl_n) to corresponding rows of bitcells row_0, . . . , row_n. In some instances, the sense amplifiers (SA)120A,120B may include output latch circuitry (o/pLatch).

The memory circuitry102may receive a clock signal CLK and an address signal Addr. The clock generation circuitry (Clkgen)110may receive the clock signal CLK and provide one or more internal clock signals, such as, e.g., a first internal clock signal i_clk1to the address decoder106and also a second internal clock signal i_clk2to the dummy wordline driver (e.g., inverter id) via the dummy wordline (DWL). The DWL loads114A,114B may receive the DWL signal from the DWL driver (id) and provide a DWL turn signal (dwl_turn) to the delay logic (Delay_N)112, and also, the delay logic (Delay_N)112may provide a reset signal to Clkgen circuitry110. In addition, the address decoder106may receive multiple signals including, e.g., the address signal Addr and the first internal clock signal i_clk1and then access at least one inverted wordline (e.g., nwl_0, . . . , nwl_n) based on the received address signal Addr.

The memory circuitry102includes the first control logic116A, which is coupled between the clock generation circuitry (Clkgen)110and the column multiplexers (Colmux)126A,126B,128A,128B. The first control logic116A may receive a global timing pulse (gtp), receive a column address signal (CA_p2<0:1>), receive a global write enable signal (gwen_p2), and provide various timing and control signals (ypr<3:0>, sae) to the column multiplexers126A,126B,128A,128B and the sense amplifiers120A,120B. For instance, the memory circuitry102may utilize the first control logic116A to provide y-mux signals (ypr<3:0>) to the column multiplexers126A,126B,128A,128B and also provide a sense amplifier enable signal (sae) to the sense amplifiers120A,120B.

The memory circuitry102may include the second control logic116B, which is coupled to the column multiplexers (Colmux)128A,128B. The second control logic116B may receive the global timing pulse (gtp), receive a column address (CA<2>), receive a the sense amplifier enable signal (sae), and provide a read multiplexer signal (RdMux) to the column multiplexers128A,128B. For instance, in some implementations, the memory circuitry102may utilize the second control logic116B to provide the read multiplexer signal (RdMux) to the column multiplexers128A,128B.

In various implementations, each bitcell in the bitcell arrays104A,104B may be referred to as a memory cell, and each bitcell may be configured to store at least one data bit value (e.g., a data value associated with logical ‘0’ or ‘1’). Each row of bitcells row_0, . . . , row_n in the bitcell arrays104A,104B may include any number of memory cells arranged in various configurations, such as, e.g., a two-dimensional (2D) memory array having columns and rows of multiple bitcells arranged in a 2D grid pattern. Each bitcell may be implemented with random access memory (RAM) circuitry, or some other type of volatile type memory. In some instances, each memory cell may include a multi-transistor static RAM (SRAM) cell, including various types of SRAM cells, such as, e.g., 6T CMOS SRAM and/or other types of complementary MOS (CMOS) SRAM cells, such as, e.g., 4T, 8T, 10T, or more transistors per bit.

In some instances, the memory circuitry102may refer to memory architecture having multiple bitcell arrays (e.g.,104A,104B), and the memory circuitry102may include column multiplexer circuitry (e.g., Colmux124) that is coupled to the memory architecture via multiple bitlines (e.g., BL/NBL<0:3>) for read access operations. Also, the column multiplexer circuitry (e.g.,124) may be configured to perform read access operations in the multiple bitcell arrays (e.g.,104A,104B) via the bitlines (e.g., BL/NBL<0:3>) based on a sense amplifier enable signal (e.g., sae) and a read multiplexer signal (e.g., RdMux). In addition, the memory circuitry102may include control circuitry (e.g.,116A,116B) that is configured to provide the read multiplexer signal (e.g., RdMux) to the column multiplexer circuitry (e.g.,124) based on a clock signal (e.g., GTP) and the sense amplifier enable signal (e.g., sae) so that the column multiplexer circuitry (e.g.,124) is able to perform the read access operations in the multiple bitcell arrays (e.g.,104A,104B).

FIGS.2A-2Billustrate diagrams of column multiplexer circuitry in accordance with various implementations described herein. In particular,FIG.2Ashows portions of the memory circuitry102ofFIG.1in more detail including the first bitcell array104A, the DWL load114A, and the column multiplexer circuitry124, and also,FIG.2Bshows portions of the memory circuitry102ofFIG.1in more detail including the second bitcell array104B, the DWL load114B, and the column multiplexer circuitry124.

In some implementations, the column multiplexer circuitry124includes multiple separate circuits including a first column multiplexer circuit124A coupled to the first bitcell array104A via the bitlines (BL[3:0] and NBL[3:0]) and a second column multiplexer circuit124B coupled to the second bitcell array104B via the bitlines (BL[3:0], NBL[3:0]). In some instances, the first column multiplexer circuit124A may perform read access operations in the first bitcell array104A via bitlines (BL[3:0], NBL[3:0]) based on the sense amplifier enable signal (sae) and the read multiplexer signal (RdMux), and also, the second column multiplexer circuit124B may perform read access operations in the second bitcell array104B via bitlines (BL[3:0], NBL[3:0]) based on the sense amplifier enable signal (sae) and the read multiplexer signal (RdMux).

As shown inFIG.2A, the column multiplexer circuitry124A includes column multiplexers126A,128A, sense amplifier120A, and the first output driver132A that are arranged and configured to receive data from the first bitcell array104A via the bitlines (BL[3:0] and NBL[3:0]) and provide the first output signal (QA) as a first selected data output from the memory circuitry102inFIG.1.

In some instances, the column multiplexer circuitry124A may include multiple (e.g.,4) column multiplexers126A that are coupled to corresponding bitlines (BL[3:0] and NBL[3:0]) via a first DWL load114A. The column multiplexers126A may receive bitline signals from the bitlines (BL[3:0], NBL[3:0]) and provide data signals (SH_BL, SH_NBL) based on a read select signal (ypr<3:0>). Also, the column multiplexer circuitry124A may include multiple (e.g.,2) sense amplifiers120A (with output latches) that receive the data signals (SH_BL, SH_NBL) and provide sense amplifier output signals (SAO_1, SAO_2) based on the sense amplifier enable signal (sae). The column multiplexer128A receives sense amplifier output signals (SAO_1, SAO_2) and provides a first colmux data signal (CM)_1) to output driver132A based on read multiplexer signal (RdMux). The first output driver132A may be configured to receive the first colmux data signal (CMO_0) from the column multiplexer128A and provide the first output data signal (QA).

In some instances, the first column multiplexer circuit124A includes first column multiplexers126A (Colmux[3:0]), first sense amplifiers120A, first output multiplexer128A (Colmux[1:0]), and first output driver132A. The first column multiplexers126A receive read data from the first bitcell array104A via the bitlines (BL[3:0], NBL[3:0]) and provide first multiplexed signals (SH_BL, SH_NBL) to first sense amplifiers120A. The first sense amplifiers120A receive the first multiplexed signals (SH_BL, SH_NBL) from first column multiplexers126A and provide first sense amplifier output signals (SAO_1, SAO_2) to the first output multiplexer128A. The first output multiplexer128A may receive the first sense amplifier output signals (SAO_1, SAO_2) from the first sense amplifiers120A and provide a second multiplexed signal (CMO_0) to the first output driver132A. The first output driver132A receives the second multiplexed signal (CMO_0) from the first output multiplexer132A and provides the first data output signal (QA).

In some instances, the first sense amplifiers120A receive the sense amplifier enable signal (sae) and provide the first sense amplifier output signals (SAO_1, SAO_2) to the first output multiplexer128A based on the sense amplifier enable signal (sae). Also, the second control logic116B (inFIG.1) provides the read multiplexer signal (RdMux) to the first output multiplexer128A based on based on the clock signal (GTP) and the sense amplifier enable signal (sae).

As shown inFIG.2B, the column multiplexer circuitry124B includes column multiplexers126B,128B, sense amplifier120B, and the second output driver132B that are arranged and configured to receive data from the second bitcell array104B via the bitlines (BL[3:0] and NBL[3:0]) and provide the second output signal (QB) as a second selected data output from the memory circuitry102inFIG.1.

In some instances, the column multiplexer circuitry124B may include multiple (e.g.,4) column multiplexers126B that are coupled to corresponding bitlines (BL[3:0] and NBL[3:0]) via a second DWL load114B. The column multiplexers126B receive bitline signals from the bitlines (BL[3:0], NBL[3:0]) and provide data signals (SH_BL, SH_NBL) based on read select signal (ypr<3:0>). The column multiplexer circuitry124B includes multiple (e.g.,2) sense amplifiers120B (with output latches) that receive the data signals (SH_BL, SH_NBL) and provide sense amplifier output signals (SAO_3, SAO_4) based on the sense amplifier enable signal (sae). The column multiplexer128B receives sense amplifier output signals (SAO_3, SAO_4) and provides a second colmux data signal (CMO_1) to output driver132B based on read multiplexer signal (RdMux). The second output driver132B may be configured to receive the second colmux data signal (CMO_1) from the column multiplexer128B and provide the second output data signal (QA).

In some instances, the second column multiplexer circuit124B includes second column multiplexers126B (Colmux[3:0]), second sense amplifiers120B, second output multiplexer128B (Colmux[1:0]), and second output driver132B. The second column multiplexers126B receive read data from the second bitcell array104B via the bitlines (BL[3:0], NBL[3:0]) and provide second multiplexed signals (SH_BL, SH_NBL) to second sense amplifiers120B. The second sense amplifiers120B receive second multiplexed signals (SH_BL, SH_NBL) from second column multiplexers126B and provide second sense amplifier output signals (SAO_3, SAO_4) to the second output multiplexer128B. The second output multiplexer128B may receive second sense amplifier output signals (SAO_3, SAO_4) from second sense amplifiers120B and provide a second multiplexed signal (CMO_1) to the second output driver132B. The second output driver132B may receive the second multiplexed signal (CMO_1) from the second output multiplexer132B and provide the second data output signal (QB).

In some instances, the second sense amplifiers120B may receive the sense amplifier enable signal (sae) and then provide the second sense amplifier output signals (SAO_3, SAO_4) to the second output multiplexer128B based on the sense amplifier enable signal (sae). Also, the second control logic116B (inFIG.1) provides the read multiplexer signal (RdMux) to the second output multiplexer128B based on based on the clock signal (GTP) and the sense amplifier enable signal (sae).

FIG.3illustrates a diagram300of control logic circuitry116B in accordance with various implementations described herein. In this instance, the control logic circuitry116B refers to the second control logic116B inFIG.1.

As shown inFIG.3, the control logic circuitry116B may receive the column address (CA<2>), and the control logic circuitry116B may provide the read multiplexer signal (RdMux) to the column multiplexer circuitry124based on receiving the clock signal (gtp), the sense amplifier enable signal (sae), and the column address (CA<2>) so that the column multiplexer circuitry124is able to perform the read access operations in the multiple bitcell arrays104A,104B via the bitlines (BL[3:0], NBL[3:0]). In some instances, the clock signal may refer to the global timing pulse (gtp).

In some implementations, the control logic circuitry116B may include various components including, e.g., a first latch332(e.g., ph2latch), a second latch334(e.g., ph1latch), an input logic gate (LG1), and an output buffer (B1). The input logic gate (LG1) may receive the clock signal (gtp), receive the sense amplifier enable signal (sae), and then provide a buffered clock signal (bclk_ca2) to the first latch332. The input logic gate (LG1) may be an OR gate; however, various other logics gates may be used that provide similar results. The first latch332may refer to a ph2latch that is configured to operate as a negative edge-triggered latch, and the second latch334may refer to a ph1latch that is configured to operate as a positive edge-triggered latch. The first latch332may receive the buffered clock signal (bclk_ca2), receive the column address (CA<2>) at an inverting clock input, and provide a first latched signal (CA_p2<2>) to the second latch334. The second latch334receives the first latched signal (CA_p2<2>), receives the sense amplifier enable signal (sae) at a non-inverting clock input, and then provides a second latched signal (CA_p1<2>) to the output buffer (B1). The output buffer (B1) may receive the second latched signal (CA_p1<2>) and provide the read multiplexer signal (RdMux) as an output control signal to the column multiplexer circuitry124.

In some instances, the control logic circuitry116B may refer to a control circuit having input logic (e.g., LG1) that receives a global timing pulse (gtp), receives a sense amplifier enable signal (sae), and provides a clock signal (bclk_ca2). The control circuit may have first latch logic (e.g.,332) that receives the clock signal (bclk_ca2) from the input logic (e.g., LG1), receives a column address signal (CA<2>), and provides a first latched signal (CA_p2<2>). Also, the control circuit may have second latch logic334that receives the first latched signal (CA_p2<2>) from the first latch logic (e.g.,332), receives the sense amplifier enable signal (sae), and then provides a second latched signal (CA_p1<2>). Further, the control circuit may have output logic (e.g., B1) that receives the second latched signal (CA_p1<2>) from the second latch logic (e.g.,334) and provides a read multiplexer signal (RdMux) to column multiplexer circuitry (e.g.,124inFIG.1) for performing memory access operations in multiple bitcell arrays (e.g.,104A,104B).

Also, in some instances, the column multiplexer circuitry (e.g.,124) may be coupled to the multiple bitcell arrays (e.g.,104A,104B) via bitlines (e.g., BL[3:0], NBL[3:0]) for performing the memory access operations, and the column multiplexer circuitry (e.g.,124) may perform the memory access operations in the multiple bitcell arrays (e.g.,104A,104B) via the bitlines (e.g., BL[3:0], NBL[3:0]) based on the sense amplifier enable signal (sae) and the read multiplexer signal (RdMux).

FIG.4illustrates a waveform diagram400of multiplexer timing signals402in accordance with various implementations described herein. In this implementation, the multiplexer timing signals402refer to mux8waveforms for a mux8instance.

As shown inFIG.4, a rising edge of a first clock pulse (clk) triggers a rising edge of the global timing pulse (gtp). The rising edge of the gtp signal triggers a rising edge of the bclk signal, a rising edge of the bclk_ca2signal and a rising edge of the sense amplifier enable signal (sae) at (1). Also, a falling edge of the sae signal triggers a falling edge of the bclk_ca2signal at (2). Also, the rising edge of the sae signal triggers toggling of the read multiplexer signal (RdMux) at (3), and the rising edge of the RdMux signal triggers toggling of the output (Q) signal at (4).

In some instances, at (1), the rising edge of the blck_ca2signal will ensure that there is no impact on ca[2] hold time as the rising edge will be controlled through the gtp signal. Also, at (2), the falling edge of the bclk_ca2signal will ensure that the ph2latch opens when the ph1latch closes to thereby ensure that there is no ihold violation. Also, at (3), the ph1latch will open when the sae signal goes high, and the ph1latch will close when the sae signal goes low. Further, at (4), toggling of the Q signal will be controlled through sae gating of the ph1flop, which will ensure that the rdmux signal does not toggle before the sae signal arrives, which may simplify configuration of the logic and may also save power and timing at the system-on-a-chip (SoC) level.

FIG.5illustrates a block diagram500of multi-bank memory circuitry502in accordance with various implementations described herein.

In various implementations, the memory circuitry502may be implemented as a system or a device having various integrated circuit (IC) components that are arranged and coupled together as an assemblage or combination of parts that provide for a physical circuit design and related structures. In some instances, a method of designing, providing and building the memory circuitry502as an integrated system or device that may involve use of various IC circuit components described herein so as to thereby implement column multiplexing schemes and techniques associated therewith. The memory circuitry502may be integrated with computing circuitry and related components on a single chip, and the memory circuitry502may be implemented in some embedded systems for electronic, mobile and Internet-of-things (IoT) applications, including sensor nodes.

As shown inFIG.5, the memory circuitry502may be referred to as memory architecture having various multi-bank related circuitry including a first multi-bank array504A and a second multi-bank array504B. In some instances, the first multi-bank array504A may be referred to as a lower bank array having a first lower bank (Lower Bank_0) and a second lower bank (Lower Bank1). Also, in some instances, the second multi-bank array504B may be referred to as an upper bank array having a first upper bank (Upper Bank_2) and a second upper bank (Upper Bank_3). Thus, in some instances, the first multi-bank array504A may refer to the first lower bank (Lower Bank_0) as a first bank array and the second lower bank (Lower Bank1) as a second bank array, and also, the second multi-bank array may refer to the first upper bank (Upper Bank_2) as a third bank array and the second upper bank (Upper Bank_3) as a fourth bank array.

The memory circuitry502may include first control circuitry526A (CTRL Lower Bank_0, Lower Bank1) coupled to the first multi-bank array504A for performing read access operations in the first multi-bank array504A based on a first sense amplifier enable signal (sae_bot). The memory circuitry502may include second control circuitry526B526A (CTRL Upper Bank_2, Upper Bank_3) coupled to the second multi-bank array504B for performing read access operations in the second multi-bank array504B based on a second sense amplifier enable signal (sae_top). Also, the first sense amplifier enable signal (sae_bot) is derived from the second sense amplifier enable signal (sae_top).

The memory circuitry502includes multi-bank control circuitry516that provides a bank multiplexer selection signal (bank_mux_sel) to the multi-bank multiplexer circuitry532A,532B based on a clock signal (set_clk), a bank address (BA), and a mixed sense amplifier enable signal (sae_mixed) that is derived from the first sense amplifier enable signal (sae_bot) and the second sense amplifier enable signal (sae_top) so that the multi-bank multiplexer circuitry532A,532B is able to select output data (Q0, Q1) from the first multi-bank array504A or the second multi-bank array504B during the read access operations. In some instances, the multi-bank multiplexer circuitry516may include a first multi-bank output multiplexer532A and a second multi-bank output multiplexer532B, and the first bank array (Lower Bank_0) and the third bank array (Upper Bank_2) are coupled to the first multi-bank output multiplexer532A, and also, the second bank array (Lower Bank1) and the fourth bank array (Upper Bank_3) are coupled to the second multi-bank output multiplexer532B.

In some instances, the output data (Q0, Q1) may include first output data (Q0) and second output data (Q1). The multi-bank control circuitry516may provide the bank multiplexer selection signal (bank_mux_sel) to the first multi-bank output multiplexer532A for selection of the first output data (Q0) from the first bank array (Lower Bank_0) or the third bank array (Upper Bank_2). Also, the multi-bank control circuitry516may provide the bank multiplexer selection signal (bank_mux_sel) to the second multi-bank output multiplexer532B for selection of the second output data (Q1) from the second bank array (Lower Bank1) or the fourth bank array (Upper Bank_3).

In some instances, in reference to the first memory array504A, the memory circuitry502may have wordline driver circuitry522A,522B including first wordline driver circuitry522A (WLD Lower Bank_0) coupled to the first bank array (Lower Bank_0) and second wordline driver circuitry522B (WLD Lower Bank1) coupled to the second bank array (Lower Bank1). The memory circuitry502may have first multiplexer circuitry528A (MUX Lower Bank_0and Lower Bank1).

In some instances, in reference to the second memory array504B, the memory circuitry502may have wordline driver circuitry524A,524B including third wordline driver circuitry524A (WLD Upper Bank_2) coupled to the third bank array (Upper Bank_2) and fourth wordline driver circuitry524B (WLD Upper Bank_3) coupled to the fourth bank array (Upper Bank_3). The memory circuitry502may have second multiplexer circuitry528B (MUX Upper Bank_2and Upper Bank_3).

FIG.6illustrates a schematic diagram600of multi-bank control circuitry602in accordance with various implementations described herein. In the schematic diagram600ofFIG.6, the multi-bank control circuitry602shows more detailed views of various components of the multi-bank control circuitry502inFIG.5.

As shown inFIG.6, the first control circuitry526A (CTRL Lower Bank_0, Lower Bank1) may include various logic gates including a first logic gate (LG2A, e.g., an OR gate), a second logic gate (I1, e.g., an inverter), and a third logic gate (12, e.g., another inverter). The second control circuitry526B (CTRL Upper Bank_2, Upper Bank_3) may include various logic gates including a first logic gate (LG2B, e.g., an OR gate), a second logic gate (13, e.g., an inverter), and a third logic gate (14, e.g., another inverter). Also, the multi-bank control circuitry516may include control logic516A,516B.

In some implementations, the second control circuitry526B may be referred to as shared control circuitry for the upper (top) bank array504B. In reference to the second control circuitry526B, the logic gate (LG2B) may receive multiple sense amplifier control signals (sac_1, sac_2) and then provide an output control signal (sae_top_del) to the first control circuitry526A. The logic gate (13) receives the control signal (sac_2) and provides a sense amplifier enable signal (nsae_top) to the logic gate (14), and also, the logic gate (14) receives the sense amplifier enable signal (nsae_top) and provides another sense amplifier enable signal (sae_top) to the shared upper bank (Top)504B. Also, the shared upper bank (Top)504B may receive the sense amplifier enable signal (sae_top), provide a first data output signal (Q0_top) from the first upper bank (Upper Bank_2), and provide a second data output signal (Q1_top) from the second upper bank (Upper Bank_3).

In some implementations, the first control circuitry526A may be referred to as shared control circuitry for the lower (bottom or bot) bank array504A. In reference to the first control circuitry526A, the logic gate (LG2A) may receive multiple sense amplifier control signals (sae_top_del, sac_3) and provide an output control signal (sae_mixed) to the multi-bank control circuitry516. The logic gate (I1) receives the control signal (sac_3) and provides a sense amplifier enable signal (nsae_bot) to the logic gate (12), and the logic gate (12) receives the sense amplifier enable signal (nsae_bot) and provides another sense amplifier enable signal (sae_bot) to the shared lower bank (Bot)504A. The shared lower bank (Bot)504A may receive the sense amplifier enable signal (sae_bot), provide a first data output signal (Q0_bot) from the first lower bank (Lower Bank_0), and provide a second data output signal (Q1_bot) from the second lower bank (Lower Bank1).

In some implementations, the memory circuitry602may include the multi-bank control circuitry516that provides the bank multiplexer selection signal (bank_mux_sel) to the multi-bank multiplexer circuitry532A,532B based on the clock signal (set_clk), the bank address (BA), and the mixed sense amplifier enable signal (sae_mixed), which is derived from the sense amplifier enable signals (sae_top, sae_bot). In this instance, the multi-bank multiplexer circuitry532A,532B is able to select output data (Q0, Q1) from the output data signals (Q0_bot, Q1_bot) of the first multi-bank array504A or from the output data signals (Q0_top, Q1_top) of the second multi-bank array504B during read access operations. The multi-bank multiplexer circuitry516may be coupled to the first multi-bank output multiplexer532A and the second multi-bank output multiplexer532B.

In some implementations, the first bank array (Lower Bank_0) provides the first lower data signal (Q0_bot) to the first multi-bank output multiplexer532A, and the third bank array (Upper Bank_2) provides the first upper data signal (Q0_top) to the first multi-bank output multiplexer532A. Also, the second bank array (Lower Bank1) provides the second lower data signal (Q1_bot) to the second multi-bank output multiplexer532B, and the fourth bank array (Upper Bank_3) provides the second upper data signal (Q1_top) to the second multi-bank output multiplexer532B. Further, in this instance, the multi-bank multiplexer circuitry532A,532B is configured to select the output data (Q0, Q1) from the output data signals (Q0_bot, Q1_bot, Q0_top, Q1_top) based on the bank multiplexer selection signal (bank_mux_sel) during read access operations.

FIGS.7A-7Billustrate various diagrams of control logic circuitry in accordance with various implementations described herein. In some instances, as described herein, the multi-bank control circuitry516inFIGS.5-6may include multiple control logic516A,516B. In particular,FIG.7Ashows a diagram700A of control logic circuitry516A, andFIG.7Bshows a diagram700B of control logic circuitry516B.

As shown inFIG.7A, the control logic circuitry516A may include set clock logic circuitry720and a latch730. In some instances, the set clock logic circuitry720may include multiple logic gates that are arranged and configured to receive multiple input signals (e.g., clk_ext, gwen, ncen) and provide multiple output signals (e.g., bclk_ext, set_clk) based on the multiple input signals. For instance, the set clock logic circuitry720may include a first logic gate (inverter15) that receives an external clock signal (clk_ext) and provides an inverted external clock signal (nclk_ext) to a second logic gate (inverter16). The second logic gate (16) may receive the inverted external clock signal (nclk_ext) and provide a buffered external clock signal (bclk_ext). The set clock logic circuitry720may include a third logic gate (LG3, e.g., NAND gate) that receives the global write enable signal (gwen), receives an inverted column enable signal (ncen), and provides an output signal (out_1) to a fourth logic gate (LG4, e.g., NOR gate). The fourth logic gate (LG4) receives the inverted external clock signal (nclk_ext), receives the output signal (out_1), and provides a set clock signal (set_clk).

As shown inFIG.7A, the control logic circuitry516A may include a first latch730that may be configured to receive the set clock signal (set_clk) at a first input, receive the sae_mixed signal at a second input, and provide an output signal (bclk_gwen) based on the set_clk signal and the sae_mixed signal. In some implementations, the first latch730may refer to an SR latch having the first input as a set (S) input and the second input as a reset (R) input. Also, in some implementations, the first latch730(e.g., SR latch) may be configured to provide the output signal (bclk_gwen) as a mixed signal related to the buffered clock signal (bclk) and/or the global write enable signal (gwen).

As shown inFIG.7B, the control logic circuitry516B may include one or more latches and one or more logic gates. In some instances, the control logic circuitry516B may include multiple logic gates that are arranged and configured to receive multiple input signals (e.g., BA, bclk_gwen, sae_mixed) and provide one or more output signals (e.g., bank_mux_sel) based on the multiple input signals. For instance, the control logic circuitry516B may include a second latch732(e.g., ph2latch), a third latch734(e.g., ph1latch), and a fifth logic gate (B2, e.g., a second output buffer). The second latch732may refer to a ph2latch that is configured to operate as a negative edge-triggered latch, and the third latch734may refer to a ph1latch that is configured to operate as a positive edge-triggered latch. In some implementations, the second latch732may receive the bank address signal (BA) at an input, receive the bclk_gwen signal at an inverting clock input, and provide a first latched bank address signal (BA_p2). The third latch734may receive the first latched bank address signal (BA_p2) at an input, receive the sae_mixed signal at a non-inverting clock input, and provide a second latched bank address signal (BA_p2) to the fifth logic gate (B2, e.g., second output buffer). In this instance, the second output buffer (B2) receives the second latched bank address signal (BA_p2) from the third latch734and provides the bank multiplexer selection signal (bank_mux_sel).

In some implementations, in reference toFIGS.5-6and7A-7B, the multi-bank memory circuitry502refers to a multi-bank memory device having memory architecture with a first multi-bank array504A and a second multi-bank array504B. The multi-bank memory circuitry502may include first control circuitry526A coupled to the first multi-bank array504A for performing read access operations in the first multi-bank array504A based on one or more sense amplifier enable signals (sae_top_del, sac3). Also, the multi-bank memory circuitry502may include second control circuitry526B coupled to the second multi-bank array504B for performing read access operations in the second multi-bank array504B based on one or more sense amplifier enable signals (e.g., sac1, sac2). In some instances, the sense amplifier enable signal (sae_top_del) may be derived from the sense amplifier enable signals (sact sac2). Also, the multi-bank memory circuitry502may include multi-bank control circuitry516that provides the bank multiplexer selection signal (bank_mux_sel) to multi-bank multiplexer circuitry532A,532B based on the clock signal (set_clk), the bank address (BA), and/or the mixed sense amplifier enable signal (sae_mixed) that is derived from one or more of the sense amplifier enable signals (sac1, sac2, sac3, sae_top_del) so that the multi-bank multiplexer circuitry532A,532B is able to select output data (Q0, Q1) from the first multi-bank array504A or the second multi-bank array504B during the read access operations.

Also, in reference toFIGS.7A-7B, the multi-bank control circuitry516may include the first latch730(e.g., SR latch), the second latch732(e.g., Data latch), the third latch734(e.g., Data latch), and the output buffer (B2). The first latch730may receive the clock signal (set_clk), receive the mixed sense amplifier enable signal (sae_mixed), and provide the buffered clock signal (bclk_gwen) to the second latch732. The second latch732may receive the buffered clock signal (bclk_gwen), receive the bank address (BA), and provide the first latched signal (BA_p2) to the third latch734. The third latch734may receive the first latched signal (BA_p2), receive the mixed sense amplifier enable signal (sae_mixed), and provide the second latched signal (BA_p1) to the output buffer (B2). The output buffer (B2) may receive the second latched signal (BA_p1) and provide the bank multiplexer selection signal (bank_mux_sel) as an output control signal to the multi-bank multiplexer circuitry532A,532B.

In some implementations, the first latch730may refer to a set-reset (SR) latch, and the second latch may refer to a first data latch (D latch or data flip-flop (DFF)), and the third latch may refer to a second data latch (D latch or data flip-flop (DFF)). Also, in some implementations, the multi-bank control circuitry516,516A,516B may include the set clock logic circuitry720having multiple logic gates that are arranged and configured to receive the external clock signal (clk_ext), receive the global write enable signal (gwen), receive the column enable signal (ncen), and provide the clock signal (e.g., the set clock signal (set_clk)) to the first latch730.

FIG.8illustrates a waveform diagram800of multiplexer timing signal802for multi-bank memory circuitry in accordance with implementations described herein. In this implementation, the multiplexer timing signals802may refer to multi-bank waveforms for the multi-bank memory circuitry502in reference toFIG.5.

As shown inFIG.8, a rising edge of a first clock pulse (clk) triggers a rising edge of the global timing pulse (gtp), and the rising edge of the global timing pulse (gtp) triggers a rising edge of the buffered clock pulse (bclk). The rising edge of the clock pulse (clk) also triggers a rising edge of the bclk_gwen pulse signal, and the rising edge of the gtp signal triggers a rising edge of the sae pulse signal. The rising edge of the sae pulse signal triggers a rising edge of the sae_mixed pulse signal, and also, a falling edge of the sae_mixed pulse signal triggers a falling edge of the bclk_gwen signal. The rising edge of the sae_mixed pulse signal triggers toggling of the bank_mux_sel signal, and also, the toggling of the bank_mux_sel signal triggers toggling od the output data signal (Q).

In some instances, at (1), the rising edge of the blck_gwen signal will ensure that there is no impact on hold time of the bank address (BA) as the rising edge will be controlled through the external clock (clk_ext) via the SR latch730. Also, at (2), the falling edge of the sae_mixed pulse signal will ensure that the ph2latch732opens when the ph1latch734closes so as to ensure that there is no ihold violation. Also, at (3), the ph1latch734will open when the sae_mixed pulse signal goes high (i.e., rises), and the ph1latch734will close when the sae pulse signal goes low (i.e., falls). Also, at (4), toggling of the output signal (Q) may be controlled through sae_mixed gating of the ph1latch734, which will ensure that the bank_mux_sel signal does not toggle before the sae signal arrives, which simplifies the logic and saves power and timing at the SoC level.

It should be intended that the subject matter of the claims not be limited to the implementations and illustrations provided herein, but include modified forms of those implementations including portions of implementations and combinations of elements of different implementations in accordance with the claims. It should be appreciated that in the development of any such implementation, as in any engineering or design project, numerous implementation-specific decisions should be made to achieve developers' specific goals, such as compliance with system-related and business related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort may be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having benefit of this disclosure.

Described herein are various implementations of a device. The device may include memory architecture having multiple bitcell arrays. The device may include column multiplexer circuitry coupled to the memory architecture via multiple bitlines for read access operations, and the column multiplexer circuitry may perform read access operations in the multiple bitcell arrays via the bitlines based on a sense amplifier enable signal and a read multiplexer signal. The device may include control circuitry that provides the read multiplexer signal to the column multiplexer circuitry based on a clock signal and the sense amplifier enable signal so that the column multiplexer circuitry is able to perform the read access operations.

Described herein are various implementations of a control circuit. The control circuit may include input logic that receives a global timing pulse, receives a sense amplifier enable signal, and provides a clock signal. The control circuit may include first latch logic that receives the clock signal from the input logic, receives a column address, and provides a first latched signal. The control circuit may include second latch logic that receives the first latched signal from the first latch logic, receives the sense amplifier enable signal, and provides a second latched signal. The control circuit may include output logic that receives the second latched signal from the second latch logic and provides a read multiplexer signal to column multiplexer circuitry for performing memory access operations in multiple bitcell arrays.

Described herein are various implementations of a multi-bank memory device. The multi-bank memory device may include memory architecture having a first multi-bank array and a second multi-bank array. The multi-bank memory device may include first control circuitry coupled to the first multi-bank array for performing read access operations in the first multi-bank array based on a first sense amplifier enable signal. The multi-bank memory device may include second control circuitry coupled to the second multi-bank array for performing read access operations in the second multi-bank array based on a second sense amplifier enable signal that is derived from the first sense amplifier enable signal. The multi-bank memory device may include multi-bank control circuitry that provides a bank multiplexer selection signal to multi-bank multiplexer circuitry based on a clock signal, a bank address, and a mixed sense amplifier enable signal that is derived from the first sense amplifier enable signal and the second sense amplifier enable signal so that the multi-bank multiplexer circuitry is able to select output data from the first multi-bank array or the second multi-bank array during the read access operations.

Reference has been made in detail to various implementations, examples of which are illustrated in the accompanying drawings and figures. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the disclosure provided herein. However, the disclosure provided herein may be practiced without these specific details. In some other instances, well-known methods, procedures, components, circuits and networks have not been described in detail so as not to unnecessarily obscure details of the embodiments.

It should also be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element. The first element and the second element are both elements, respectively, but they are not to be considered the same element.

The terminology used in the description of the disclosure provided herein is for the purpose of describing particular implementations and is not intended to limit the disclosure provided herein. As used in the description of the disclosure provided herein and appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. The term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. The terms “includes,” “including,” “comprises,” and/or “comprising,” when used in this specification, specify a presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

As used herein, the term “if” may be construed to mean “when” or “upon” or “in response to determining” or “in response to detecting,” depending on the context. Similarly, the phrase “if it is determined” or “if [a stated condition or event] is detected” may be construed to mean “upon determining” or “in response to determining” or “upon detecting [the stated condition or event]” or “in response to detecting [the stated condition or event],” depending on the context. The terms “up” and “down”; “upper” and “lower”; “upwardly” and “downwardly”; “below” and “above”; and other similar terms indicating relative positions above or below a given point or element may be used in connection with some implementations of various technologies described herein.

While the foregoing is directed to implementations of various techniques described herein, other and further implementations may be devised in accordance with the disclosure herein, which may be determined by the claims that follow.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.