Patent ID: 12213296

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different nodes of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In some embodiments, the formation of a first node over or on a second node in the description that follows may include embodiments in which the first and the second nodes are formed in direct contact, and may also include embodiments in which additional nodes may be formed between the first and the second nodes, such that the first and the second nodes may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It should be understood that additional operations can be provided before, during, and/or after a disclosed method, and some of the operations described can be replaced or eliminated for other embodiments of the method.

Furthermore, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

For fin field effect transistors (FinFETs), the fins may be patterned using any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins.

The fins provide additional sidewalls device width (for Ion performance) as well as better short channel control (for subthreshold leakage). Therefore, because of their superior scalability by double gate mode operation, FinFETs are expected to be advantageous in terms of gate-length scaling and intrinsic threshold voltage (Vt) fluctuation.

Integrated circuits and the corresponding structures are provided in accordance with various exemplary embodiments. Some variations of some embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements.

FIG.1Ais a simplified diagram of an integrated circuit (IC)100A, in accordance with some embodiments of the disclosure. The IC100A includes a digital circuit (or so-called a logic circuit)10A and a SRAM50A. In some embodiments, the digital circuit10A is configured to access the SRAM50A to perform various applications. In some embodiments, the SRAM50A is accessed by a controller of the IC and the digital circuit10A is capable of performing various applications according to data stored in the SRAM50A and accessed by the controller.

The digital circuit10A includes a cell array formed by multiple standard cells STD1-STD10 (e.g., inverter, NAND, NOR, Flip-Flop, latch, and so on), and the standard cells STD1-STD10 are arranged in multiple rows and multiple columns of the cell array. For example, the standard cells STD1-STD5 are arranged in the same column, and the standard cells STD1-STD5 have the same cell width. The standard cells STD6-STD10 are arranged in the same column, and the standard cells STD6-STD10 have the same cell width. In some embodiments, different types of standard cells STD1-STD10 may have various widths and heights.

Each of the standard cells STD1-STD10 is formed by N-type and P-type fin field effect transistors (FinFETs). The N-type FinFETs of the standard cells STD6-STD10 are formed in a P-type well region PW1 of a substrate, and the N-type FinFETs of the standard cells STD1-STD5 are formed in a P-type well region PW2 of the substrate. An N-type well region NW1 is arranged between the P-type well regions PW1 and PW2. The P-type FinFETs of the standard cells STD1-STD10 are formed in the N-type well region NW1 of the substrate. Furthermore, the P-type FinFETs of the standard cells STD1-STD5 share a semiconductor fin110_1, and the P-type FinFETs of the standard cells STD6-STD10 share a semiconductor fin110_2. The semiconductor fins110_1and110_2are continuous fin lines including silicon germanium (SiGe) material, and the semiconductor fin110_1is parallel to the semiconductor fin110_2. In the logic circuit10A, the channel of each P-type FinFET is formed by a single semiconductor fin. In some embodiments, the channel of each P-type FinFET can be formed by multiple semiconductor fins.

The SRAM50A includes a cell array formed by multiple SRAM cells (also called bit cells) MC1-MC10, and the SRAM cells MC1-MC10 are arranged in multiple rows and multiple columns in the cell array. For example, the SRAM cells MC1-MC5 are arranged in the same column, and the SRAM cells MC6-MC10 are arranged in the same column. The SRAM cells have the same configurations in layout, e.g., the widths and heights of the SRAM cells are the same. The configurations of the SRAM cells are described below.

Each of the SRAM cells MC1-MC10 is formed by N-type and P-type FinFETs. The N-type FinFETs of the SRAM cells MC1-MC5 are formed in the P-type well regions PW4 and PW5 of the substrate, and P-type FinFETs of the SRAM cells MC1-MC5 are formed in an N-type well region NW2 of the substrate. The N-type FinFETs of the SRAM cells MC6-MC10 are formed in the P-type well regions PW3 and PW4 of the substrate, and the P-type FinFETs of the SRAM cells MC6-MC10 are formed in an N-type well region NW3 of the substrate. The N-type well region NW3 is positioned between the P-type well regions PW3 and PW4, the P-type well region PW4 is positioned between the N-type well regions NW2 and NW3, and the N-type well region NW2 is positioned between the P-type well regions PW4 and PW5.

In the SRAM50A, the P-type FinFETs of the two adjacent SRAM cells can share a semiconductor fin. Taking the SRAM cells MC1-MC5 arranged in the same column as an example, a half of the P-type FinFETs of the SRAM cell MC1 and a half of the P-type FinFETs of the SRAM cell MC2 share a semiconductor fin120_1. The other half of the P-type FinFETs of the SRAM cell MC2 and a half of the P-type FinFETs of the SRAM cell MC3 share a semiconductor fin120_2. The other half of the P-type FinFETs of the SRAM cell MC3 and a half of the P-type FinFETs of the SRAM cell MC4 share a semiconductor fin120_3. The other half of the P-type FinFETs of the SRAM cell MC4 and a half of the P-type FinFETs of the SRAM cell MC5 share a semiconductor fin120_4, and so on. Furthermore, the semiconductor fins120_1-120_10are discontinuous fin lines including non-SiGe material. The semiconductor fins120_1,120_3and120_5are arranged in the same line. The semiconductor fins120_2and120_4are arranged in the same line parallel to the semiconductor fins120_1,120_3and120_5. The semiconductor fins1206,120_8and120_10are arranged in the same line. The semiconductor fins120_7and120_9are arranged in the same line parallel to the semiconductor fins120_6,120_8and120_10. In some embodiments, the semiconductor fins120_1-120_10are formed by silicon (Si) material (e.g., non-SiGe material).

In the IC100A, the semiconductor fins of the P-type FinFETs of the logic circuit10A and the semiconductor fins of the P-type FinFETs of the SRAM50A are formed of different materials. For example, the P-type FinFETs of the standard cells STD1-STD10 of the logic circuit10A are formed by the SiGe content continuous semiconductor fins, and the P-type FinFETs of the SRAM cells MC1-MC10 of the SRAM50A are formed by the non-SiGe content discontinuous semiconductor fins. Therefore, in the IC100A, the semiconductor fins120_1-120_10of the SRAM50A are shorter than the semiconductor fins110_1-110_2of the logic circuit10A.

FIG.1Bis a simplified diagram of an IC100B, in accordance with some embodiments of the disclosure. The IC100B includes a digital circuit10B and a SRAM50B. In some embodiments, the digital circuit10B is configured to access the SRAM50B to perform various applications. In some embodiments, the SRAM50B is accessed by a controller of the IC and the digital circuit10B is capable of performing various applications according to data stored in the SRAM50B and accessed by the controller.

Compared with the logic circuit10A ofFIG.1A, the N-type FinFETs of the standard cells STD1-STD5 share a semiconductor fin130_1, and the N-type FinFETs of the standard cells STD6-STD10 share a semiconductor fin130_2. The semiconductor fins130_1and130_2are continuous fin lines including Si, and the semiconductor fin130_1is parallel to the semiconductor fin130_2. Furthermore, the semiconductor fin130_1is also parallel to the semiconductor fins110_1and110_2. In the logic circuit10B, the channel of each N-type FinFET is formed by a single semiconductor fin. In some embodiments, the channel of each N-type FinFET can be formed by multiple semiconductor fins. In some embodiments, the semiconductor fins110_1,110_2,130_1and130_2have the same length.

Compared with the SRAM50A ofFIG.1A, the N-type FinFETs formed in the P-type well region PW5 of the SRAM cells MC1-MC5 share a semiconductor fin140_1, and the N-type FinFETs formed in the P-type well region PW4 of the SRAM cells MC6-MC10 share a semiconductor fin140_2. Furthermore, the N-type FinFETs formed in the P-type well region PW4 of the SRAM cells MC6-MC10 share a semiconductor fin140_3, and the N-type FinFETs formed in the P-type well region PW3 of the SRAM cells MC6-MC10 share a semiconductor fin140_4. The semiconductor fins140_1-140_4are continuous fin lines including Si, and the semiconductor fins140_1-140_4are parallel to each other. Furthermore, the semiconductor fins140_1-140_4are also parallel to the semiconductor fins120_1-120_10. In the SRAM50B, the channel of each N-type FinFET is formed by a single semiconductor fin. In some embodiments, the channel of each N-type FinFET can be formed by multiple semiconductor fins.

In some embodiments, the semiconductor fins130_1and130_2of the logic circuit10B and the semiconductor fins140_1and140_2of the SRAM50B are continuous fin lines including non-SiGe material.

FIG.2is a simplified diagram of a logic circuit10C, in accordance with some embodiments of the disclosure. The digital circuit10C includes the standard cells STD_INV, STD_NAND, and STD_NOR arranged in the same column. The P-type FinFETs of the standard cells STD_INV, STD_NAND, and STD_NOR are formed in the N-type well region NW1, and the channel of each P-type FinFET is formed by dual semiconductor fins110_3and110_4. Moreover, the N-type FinFETs of the standard cells STD_INV, STD_NAND, and STD_NOR are formed in the P-type well region PW1, and the channel of each N-type FinFET is formed by dual semiconductor fins130_3and130_4.

FIG.3Ais a schematic diagram illustrating the standard cell STD_INV ofFIG.2. The standard cell STD_INV is an inverter including a P-type FinFET PU and an N-type FinFET PD, and the inverter is capable of receiving an input signal IN to provide an output signal OUT. A source of the P-type FinFET PU is coupled to a power line VDD (or a power supply node) through a node310, and a drain of the P-type FinFET PU is coupled to the N-type FinFET PD through a node312. A source of the N-type FinFET PD is coupled to a ground line VSS through a node316, and a drain of the N-type FinFET PD is coupled to the P-type FinFET PU through a node314. The gates of the P-type FinFET PU and the N-type FinFET PD are coupled together for receiving the input signal IN, and the drains of the P-type FinFET PU and the N-type FinFET PD are coupled together through the nodes312and314for providing the output signal OUT.

FIG.3Bis a schematic diagram illustrating the standard cell STD_NAND ofFIG.2. The standard cell STD_NAND is a NAND gate including the P-type FinFETs MP1 and MP2 and the N-type FinFETs MN1 and MN2, and the NAND gate is capable of receiving two input signals IN1 and IN2 to provide an output signal OUT. The sources of the P-type FinFETs MP1 and MP2 are coupled to a power line VDD through the nodes330and332, respectively. Both the drains of the P-type FinFETs MP1 and MP2 are coupled to the N-type FinFET MN1 through a node334. A source of the N-type FinFET MN2 is coupled to a ground line VSS through a node340, and a drain of the N-type FinFET MN2 is coupled to the N-type FinFET MN1 through a node338. A source of the N-type FinFET MN1 is coupled to the N-type FinFET MN2 through the node338, and a drain of the N-type FinFET MN1 is coupled to the P-type FinFETs MP1 and MP2 through a node336. Specifically, the P-type FinFETs MP1 and MP2 are coupled in parallel, and the N-type FinFETs MN1 and MN2 are coupled in series. The gates of the P-type FinFET MP1 and the N-type FinFET MN1 are coupled together for receiving the input signal IN1, and the gates of the P-type FinFET MP2 and the N-type FinFET MN2 are coupled together for receiving the input signal IN2. The drains of the P-type FinFETs MP1 and MP2 and the N-type FinFET MN1 are coupled together through the nodes334and336for providing the output signal OUT.

FIG.3Cis a schematic diagram illustrating the standard cell STD_NOR ofFIG.2. The standard cell STD_NOR is an NOR gate including the P-type FinFETs MP3 and MP4 and the N-type FinFETs MN3 and MN4, and the NOR gate is capable of receiving two input signals IN1 and IN2 to provide an output signal OUT. A source of the P-type FinFET MP3 is coupled to a power line VDD through a node350, and a drain of the P-type FinFET MP3 is coupled to the P-type FinFET MP4 through a node352. A source of the P-type FinFET MP4 is coupled to the P-type FinFET MP3 through the node352, and a drain of the P-type FinFET MP4 is coupled to the N-type FinFETs MN3 and MN4 through a node354. The sources of the N-type FinFETs MN3 and MN4 are coupled to a ground line VSS through the nodes360and358, respectively. Both the drains of the N-type FinFETs MN3 and MN4 are coupled to the P-type FinFET MP4 through a node356. Specifically, the P-type FinFETs MP3 and MP4 are coupled in series, and the N-type FinFETs MN3 and MN4 are coupled in parallel. The gates of the P-type FinFET MP3 and the N-type FinFET MN3 are coupled together for receiving the input signal IN1, and the gates of the P-type FinFET MP4 and the N-type FinFET MN4 are coupled together for receiving the input signal IN2. The drains of the N-type FinFETs MN3 and MN4 and the P-type FinFET MP4 are coupled together through the nodes356and354for providing the output signal OUT.

FIG.4shows the layout of the logic circuit10C ofFIG.2, in accordance with some embodiments of the disclosure.

In some embodiments, the length of the semiconductor fins110_3and110_4is arranged across at least three standard cells STD_INV, STD_NAND, and STD_NOR. Furthermore, the standard cells STD_INV, STD_NAND, and STD_NOR abut one another.

Referring toFIG.4andFIG.3Atogether, in the standard cell STD_INV, the P-type FinFET PU is formed in the N-type well region NW1 of a substrate, and the N-type FinFET PD is formed in the P-type well region PW1 of the substrate. The semiconductor fins110_3and110_4are configured to serve as the channel region of the P-type FinFET PU. For the P-type FinFET PU, an electrode430_3is configured to electrically connect a gate structure corresponding to a gate region of the P-type FinFET PU, and the electrode430_3is also configured to electrically couple to a signal line for receiving the input signal IN through the interconnect structure (not shown) in the logic circuit10C. In some embodiments, the interconnect structure is formed by multiple metals and multiple vias on the standard cell STD_INV.

In the standard cell STD_INV, the contacts410_1and410_2are configured to electrically connect the source region (e.g., node310ofFIG.3A) and the drain region (e.g., node312ofFIG.3A) of the P-type FinFET PU, respectively. Similarly, the contact410_1is configured to electrically couple to a power line VDD through the interconnect structure (not shown) in the logic circuit10C, and contact410_2is configured to electrically couple to a signal line for providing the output signal OUT through the interconnect structure (not shown) in the logic circuit10C.

In some embodiments, the electrodes430_1-430_13ofFIG.4are the gate electrode made of a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or another applicable material. In some embodiments, the gate electrode includes a structure selected from a group consisting of poly gate/SiON structure, metals/high-K dielectric structure, Al/refractory metals/high-K dielectric structure, silicide/high-K dielectric structure, or combination.

In the standard cell STD_INV, the semiconductor fins130_3and130_4are configured to serve as the channel region of the N-type FinFET PD. For the N-type FinFET PD, the electrode430_3is configured to electrically connect a gate structure corresponding to a gate region of the N-type FinFET PD, and the electrode430_3is also coupled to the gate region of the P-type FinFET PU. The contacts410_9and410_10are configured to electrically connect the source region (e.g. node316ofFIG.3A) and drain region (e.g. node314ofFIG.3A) of the N-type FinFET PD, respectively. Similarly, the contact410_9is configured to electrically couple to a ground line VSS through the interconnect structure (not shown) in the logic circuit10C. Furthermore, the contact410_10is configured to electrically couple to the signal line for providing the output signal OUT and the drain region of the P-type FinFET PU (e.g., contact410_2) through the interconnect structure (not shown) in the logic circuit10C.

Referring toFIG.4andFIG.3Btogether, in the standard cell STD_NAND, the P-type FinFETs MP1 and MP2 are formed in the N-type well region NW1, and the N-type FinFETs MN1 and MN2 are formed in the P-type well region PW1. The semiconductor fins110_3and110_4are configured to serve as the channel regions of the P-type FinFETs MP1 and MP2. For the P-type FinFET MP1, an electrode430_6is configured to electrically connect a gate structure corresponding to a gate region of the P-type FinFET MP1, and the electrode430_6is also configured to electrically couple to a signal line for receiving the input signal IN1 through the interconnect structure (not shown) in the logic circuit10C. The contacts410_3and410_4are configured to electrically connect the source region (e.g., node330ofFIG.3B) and the drain region (e.g., node334ofFIG.3B) of the P-type FinFET MP1, respectively.

For the P-type FinFET MP2 of the standard cell STD_NAND, an electrode430_7is configured to electrically connect a gate structure corresponding to a gate region of the P-type FinFET MP2, and the electrode430_7is also configured to electrically couple to a signal line for receiving the input signal IN2 through the interconnect structure (not shown) in the logic circuit10C. The contacts410_5and410_4are configured to electrically connect the source region (e.g., node332ofFIG.3B) and the drain region (e.g., node334ofFIG.3B) of the P-type FinFET MP2, respectively. Furthermore, the contacts410_3and410_5are configured to electrically couple to a power line VDD through the interconnect structure (not shown) in the logic circuit10C, and contact410_4is configured to electrically couple to a signal line for providing the output signal OUT through the interconnect structure (not shown) in the logic circuit10C.

In the standard cell STD_NAND, the semiconductor fins130_3and130_4are configured to serve as the channel region of the N-type FinFETs MN1 and MN2. For the N-type FinFET MN1 of the standard cell STD_NAND, the electrode430_6is configured to electrically connect a gate structure corresponding to a gate region of the N-type FinFET MN1, and the electrode430_6is also coupled to the gate region of the P-type FinFET MP1. The contacts410_11and410_12are configured to electrically connect the drain region (e.g. node336ofFIG.3B) and the source region (e.g. node338ofFIG.3B) of the N-type FinFET MN1, respectively. Furthermore, the contact410_11is also configured to electrically couple to the signal line for providing the output signal OUT and the drain region of the P-type FinFETs MP1 and MP2 (e.g., contact410_4) through the interconnect structure (not shown) in the logic circuit10C. The contact410_12is also configured to electrically couple to the drain region of the N-type FinFET MN2.

For the N-type FinFET MN2 of the standard cell STD_NAND, the electrode430_7is configured to electrically connect a gate structure corresponding to a gate region of the N-type FinFET MN2, and the electrode430_7is also coupled to the gate region of the P-type FinFET MP2. The contacts410_12and410_13are configured to electrically connect the drain region (e.g. node338ofFIG.3B) and the source region (e.g. node340ofFIG.3B) of the N-type FinFET MN1, respectively.

Referring toFIG.4andFIG.3Ctogether, in the standard cell STD_NOR, the P-type FinFETs MP3 and MP4 are formed in the N-type well region NW1, and the N-type FinFETs MN3 and MN4 are formed in the P-type well region PW1. The semiconductor fins110_3and110_4are configured to serve as the channel region of the P-type FinFETs MP3 and MP4. For the P-type FinFET MP3, an electrode430_10is configured to electrically connect a gate structure corresponding to a gate region of the P-type FinFET MP3, and the electrode430_10is also configured to electrically couple to a signal line for receiving the input signal IN1 through the interconnect structure (not shown) in the logic circuit10C. The contacts410_6and410_7are configured to electrically connect the source region (e.g., node350ofFIG.3C) and the drain region (e.g., node352ofFIG.3C) of the P-type FinFET MP3, respectively. Furthermore, the contact410_6is configured to electrically couple to a power line VDD through the interconnect structure (not shown) in the logic circuit10C.

For the P-type FinFET MP4 of the standard cell STD_NOR, an electrode430_11is configured to electrically connect a gate structure corresponding to a gate region of the P-type FinFET MP4, and the electrode430_11is also configured to electrically couple to a signal line for receiving the input signal IN2 through the interconnect structure (not shown) in the logic circuit10C. The contacts410_7and410_8are configured to electrically connect the source region (e.g., node352ofFIG.3C) and the drain region (e.g., node354ofFIG.3C) of the P-type FinFET MP4, respectively. The contact410_8is configured to electrically couple to a signal line for providing the output signal OUT through the interconnect structure (not shown) in the logic circuit10C.

In the standard cell STD_NOR, the semiconductor fins130_3and130_4are configured to serve as the channel region of the N-type FinFETs MN3 and MN4. For the N-type FinFET MN3, the electrode430_10is configured to electrically connect a gate structure corresponding to a gate region of the N-type FinFET MN3, and the electrode430_10is also coupled to the gate region of the P-type FinFET MP3. The contacts410_14and410_15are configured to electrically connect the source region (e.g. node360ofFIG.3C) and drain region (e.g. node356ofFIG.3C) of the N-type FinFET MN3, respectively. Furthermore, the contact410_15is also configured to electrically couple to the signal line for providing the output signal OUT and the drain region (e.g., contact410_8) of the P-type FinFET MP3 through the interconnect structure (not shown) in the logic circuit10C. The contacts410_14and410_16are configured to electrically couple to a ground line VSS through the interconnect structure (not shown) in the logic circuit10C.

InFIG.4, the isolation FinFETs are formed between the boundaries of the standard cells. For example, an electrode430_4is configured to electrically connect a gate structure corresponding to a gate region of an isolation P-type FinFET in the boundary of the standard cells STD_INV and STD_NAND, and the contacts410_3and410_2are configured to electrically connect the source and drain regions of the isolation P-type FinFET. Furthermore, an electrode430_5is configured to electrically connect a gate structure corresponding to a gate region of an isolation N-type FinFET in the boundary of the standard cells STD_INV and STD_NAND, and the contacts410_11and410_10are configured to electrically connect the source and drain regions of the isolation N-type FinFET. Similarly, the electrode430_1,430_8and430_12are configured to electrically connect the gate structures corresponding to the gate regions of the isolation P-type FinFETs, and the electrode430_2,430_9and430_13are configured to electrically connect the gate structures corresponding to the gate regions of the isolation N-type FinFETs.

FIG.5is a schematic diagram cross-sectional view taken along line A-AA ofFIG.4, illustrating a cross-sectional view of the standard cell STD_INV of the digital circuit10C. The P-type well PW1 and the N-type well region NW1 are formed on a substrate510. In some embodiments, the substrate510is a Si substrate. The semiconductor fins110_3and110_4are formed on the N-type well region NW1, and the semiconductor fins130_3and130_4are formed on the P-type well PW1. The semiconductor fins110_3and110_4are formed of SiGe material, and the semiconductor fins110_3and110_4are configured to serve as the channel regions560_1and560_2of the P-type FinFET PU. The semiconductor fins130_3and140_4are formed of Si-base (non-SiGe) material, and the semiconductor fins130_3and130_4are configured to serve as the channel regions560_3and560_4of the N-type FinFET PD. Furthermore, the semiconductor fins1103and1104and the semiconductor fins130_3and130_4are separated from each other by the shallow trench isolation (STI)520.

InFIG.5, a gate dielectric layer530and the electrode430_3(e.g., gate electrode) formed over the gate dielectric layer530, are positioned over sidewalls and a top surface of the semiconductor fins110_3,110_4,130_3and130_4. In some embodiments, the channel region of P-type FinFET PU includes a SiGe channel region. In addition, the Ge atomic concentration in the SiGe channel region is in a range from about 10% to about 40%. In some embodiments, the gate dielectric layer530is a high dielectric constant (high-k) dielectric material. A high-k dielectric material has a dielectric constant (k) higher than that of silicon dioxide. Examples of high-k dielectric materials include hafnium oxide, zirconium oxide, aluminum oxide, silicon oxynitride, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, another suitable high-k material, or a combination thereof. In some embodiments, the electrode430_3is made of a conductive material, such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), or another applicable material. In some embodiments, the electrode430_3includes multiple material structure selected from a group consisting of poly gate/SiON structure, metals/high-K dielectric structure, Al/refractory metals/high-K dielectric structure, silicide/high-K dielectric structure, or combination.

In some embodiments, the sidewall depth CH_D of the SiGe channel region of the P-type FinFETs of the standard cells of logic circuit10C is in a range from about 35 nm to about 90 nm.

In some embodiments, the source and drain regions of the N-type FinFETs of the standard cells of logic circuit10C include material selected from a group consisting of silicon carbide (SiC), silicon phosphorous (SiP), phosphorous-doped silicon carbon (SiCP), silicon arsenides (SiAs), silicon (Si), or a combination thereof.

FIG.6is a schematic diagram cross-sectional view taken along line B-BB ofFIG.4, illustrating a cross-sectional view of the P-type FinFETs PU and MP1-MP4 of the digital circuit10C, in accordance with some embodiments of the disclosure.

The N-type well region NW1 is formed on the substrate510. The semiconductor fin110_3is formed on the N-type well region NW1. Multiple gate structures610_1-610_9are positioned on the semiconductor fin110_3. Each of the gate structures610_1-610_9may include a gate dielectric layer530and a gate electrode (e.g.,430_1-430_12). Gate spacers620may be formed on opposite sidewalls of the gate structures and over the semiconductor fin110_3. In addition, source/drain features630_1-630_8may be formed in a doping layer on outer sidewalls of the gate spacers620of the two adjacent gate structures. For example, the source/drain feature630_4is formed between the gate spacer620on the right side of the gate structure610_4and the gate spacer620on the left side of the gate structure610_5. Specifically, each of the source/drain features630_1-630_8is extending from the channel regions of the P-type FinFETs. In some embodiments, a silicide layer is formed upon the source/drain features630_1-630_8.

The source/drain features630_1-630_8are configured to serve as the source/drain regions of the P-type FinFETs in the fin structure110_3. The source/drain features630_1-630_8are formed by etching the LDD regions (not shown) within the fin structure110_3to form recesses (not shown), and epitaxially growing a material in the recesses, using suitable methods such as metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), the like, or a combination thereof. In some embodiments, the source/drain features630_1-630_8include silicon germanium (SiGe), and a p-type impurity such as boron (e.g. B11) or indium.

In some embodiments, the Ge atomic concentration in source/drain features630_1-630_8is in a range from about 30% to about 75%. Furthermore, the Ge atomic concentration in the source/drain features630_1-630_8is higher than the Ge atomic concentration in the channel regions of the P-type FinFETs PU and MP1-MP4.

For the standard cell STD_INV, the gate structure610_2is configured to serve as the gate region of the P-type FinFET PU, and the source/drain features630_1and630_2are formed in the source and drain regions of the P-type FinFET PU.

For the standard cell STD_NAND, the gate structure610_4is configured to serve as the gate region of the P-type FinFET MP1, and the source/drain features630_3and630_4are formed in the source and drain regions of the P-type FinFET MP1. The gate structure610_5is configured to serve as the gate region of the P-type FinFET MP2, and the source/drain features630_5and630_4are formed in the source and drain regions of the P-type FinFET MP2.

For the standard cell STD_NOR, the gate structure610_7is configured to serve as the gate region of the P-type FinFET MP3, and the source/drain features630_6and630_7are formed in the source and drain regions of the P-type FinFET MP3. The gate structure610_8is configured to serve as the gate region of the P-type FinFET MP4, and the source/drain features630_7and630_8are formed in the source and drain regions of the P-type FinFET MP4.

In some embodiments, for each P-type FinFET, the width of the source/drain features630_1-630_8is greater than the width of the channel region under the gate structure of the P-type FinFET. Taking the P-type FinFET PU of the standard cell STD_INV as an example, the width of the source/drain features630_1and630_2is W1, and the channel region of the gate structure of the P-type FinFET PU have a width W2 less than W1 (i.e., W2<W1). In some embodiments, the width W2 of the channel region of the gate structure of the P-type FinFET PU is within a range from 3 nm to 10 nm.

Recent advances in FinFET transistor technology have made advanced SRAM cells using FinFET transistors possible. In contrast to the planar MOS transistor, which has a channel formed at the surface of a semiconductor substrate, a FinFET has a three dimensional channel region. The three-dimensional shape of the FinFET channel region allows for an increased gate width without increased silicon area, even as the overall scale of the devices is reduced with semiconductor process scaling and in conjunction with a reduced gate length, and provide a reasonable channel width characteristic at a low silicon area cost.

When an SRAM cell is formed using single fin finFET transistor for the pull up or “PU” transistor, the “alpha ratio” of the on current (“Ion”) for the P-type transistors, that is the ratio PU_Ion/PG_Ion, is negatively impacted. The SRAM cells formed of these transistors may therefore exhibit a poor write margin metric, and the amount that the cell positive supply voltage Vcc can be lowered (“Vcc_min”) while maintaining proper operation will be reduced. A reduced Vcc_min metric negatively impacts the power consumption for an integrated circuit using the SRAM cells. In the known approaches, solutions such as threshold voltage (“Vt”) tuning and gate length skew adjustments of certain ones of the FinFET devices are used to increase performance of the SRAM cells.

To have lower alpha ratio (Ion_PU/Ion_PG) to gain the cell write margin and without impact the chip speed or induced extra cost is important. SRAM and low leakage devices usually prefer higher Vt setting for low standby leakage requirements.

FIG.7is a simplified diagram of a SRAM cell MC (e.g., MC1-MC10 ofFIGS.1A and1B), in accordance with some embodiments of the disclosure. The SRAM cell MC includes a pair of cross-coupled inverters Inverter-1 and Inverter-2, and two pass-gate transistors PG1 and PG2. The inverters Inverter-1 and Inverter-2 are cross-coupled between the nodes712and710, and form a latch. The pass-gate transistor PG1 is coupled between a bit line BL and the node712, and the pass-gate transistor PG2 is coupled between a complementary bit line BLB and the node710, wherein the complementary bit line BLB is complementary to the bit line BL. The gates of the pass-gate transistors PG1 and PG2 are coupled to the same word-line WL. Furthermore, the pass-gate transistors PG1 and PG2 are N-type FinFETs.

The inverter Inverter-1 includes a pull-up transistor PU1 and a pull-down transistor PD1. The pull-up transistor PU1 is a P-type FinFET, and the pull-down transistor PD1 is an N-type FinFET. The drain of the pull-up transistor PU1 and the drain of the pull-down transistor PD1 are coupled to the node712connecting the pass-gate transistor PG1. The gates of the pull-up transistor PU1 and the pull-down transistor PD1 are coupled to the node710connecting the pass-gate transistor PG2. Furthermore, the source of the pull-up transistor PU1 is coupled to a power line VDD, and the source of the pull-down transistor PD1 is coupled to a ground line VSS.

Similarly, the inverter Inverter-2 includes a pull-up transistor PU2 and a pull-down transistor PD2. The pull-up transistor PU2 is a P-type FinFET, and the pull-down transistor PD2 is an N-type FinFET. The drains of the pull-up transistor PU2 and the pull-down transistor PD2 are coupled to the node710connecting the pass-gate transistor PG2. The gates of the pull-up transistor PU2 and the pull-down transistor PD2 are coupled to the node712connecting the pass gate transistor PG1. Furthermore, the source of the pull-up transistor PU2 is coupled to the power line VDD, and the source of the pull-down transistor PD2 is coupled to the ground line VSS.

FIG.8shows the layout of the SRAM cells MC7 and MC8 of the SRAM50B ofFIG.1B, in accordance with some embodiments of the disclosure. The two adjacent SRAM cells MC7 and MC8 are arranged in the same column of the cell array of the SRAM50B. In some embodiments, the two adjacent SRAM cells MC7 and MC8 are arranged in mirror symmetry. A interconnect structure of the two adjacent SRAM cells MC7 and MC8 will be described in detail below. It should be noted that various levels of the interconnect structure shown inFIG.8is merely an example and is not intended to limit the SRAM cells MC of the SRAM.

In the SRAM cell MC8 ofFIG.8, the semiconductor fin140_3is configured to serve as the channel regions of the pass-gate transistor PG1 and the pull-down transistor PD1. Furthermore, the pass-gate transistor PG1 and the pull-down transistor PD1 are formed in the P-type well region PW4. For the pass-gate transistor PG1, an electrode430_22is configured to electrically connect a gate structure corresponding to a gate region of the pass-gate transistor PG1, and the contacts410-23and410-22are configured to electrically connect the drain and source regions of the pass-gate transistor PG1, respectively. For the pull-down transistor PD1, an electrode430_23is configured to electrically connect a gate structure corresponding to a gate region of the pull-down transistor PD1, and the contacts410_23and410_24are configured to electrically connect the drain and source regions of the pull-down transistor PD1, respectively.

In the SRAM cell MC8 ofFIG.8, the semiconductor fin120_8is configured to serve as the channel region of the pull-up transistor PU1. Furthermore, the pull-up transistor PU1 is formed in the N-type well region NW3. For the pull-up transistor PU1, the electrode430_23is configured to electrically connect a gate structure corresponding to a gate region of the pull-up transistor PU1, and the contact410_23and410_31are configured to electrically connect the drain and source regions of the pull-up transistor PU1, respectively. As described above, the electrode430_23is also electrically coupled to the gate region of the pull-down transistor PD1, and the contact410_23is also electrically coupled to the drain regions of the pull-down transistor PD1 and the pass-gate transistor PG1.

In the SRAM cell MC8 ofFIG.8, the semiconductor fin120_7is configured to serve as the channel region of the pull-up transistor PU2. Furthermore, the pull-up transistor PU2 is formed in the N-type well region NW3. For the pull-up transistor PU2, the electrode430_26is configured to electrically connect a gate structure corresponding to a gate region of the pull-up transistor PU2, and the contact410_30and410_28are configured to electrically connect the drain and source regions of the pull-up transistor PU2, respectively. Furthermore, the electrode430_26is configured to electrically connect the contact410_23through a gate contact810_3, thus the gate region of the pull-up transistor PU2 is electrically coupled to the drain regions of the pull-up transistor PU1, the pull-down transistor PD1, and the pass-gate transistor PG1.

In the SRAM cell MC8 ofFIG.8, the semiconductor fin140_4is configured to serve as the channel regions of the pass-gate transistor PG2 and the pull-down transistor PD2. Furthermore, the pass-gate transistor PG2 and the pull-down transistor PD2 are formed in the P-type well region PW3. In some embodiments, the N-type well region NW3 is positioned between the P-type well regions PW3 and PW4. For the pass-gate transistor PG2, an electrode430_27is configured to electrically connect a gate structure corresponding to a gate region of the pass-gate transistor PG2, and the contacts410_30and410_32are configured to electrically connect the drain and source regions of the pass-gate transistor PG2, respectively. For the pull-down transistor PD2, the electrode430_26is configured to electrically connect a gate structure corresponding to a gate region of the pull-down transistor PD2, and the contacts410_30and410_29are configured to electrically connect the drain and source regions of the pull-down transistor PD2, respectively. As described above, the electrode430_26is also electrically coupled to the gate region of the pull-up transistor PU2, thus the gate region of the pull-down transistor PD2 is also electrically coupled to the drain regions of the pull-up transistor PU1, the pull-down transistor PD1, and the pass-gate transistor PG1. Moreover, the contact410_30is electrically coupled to the drain region of the pull-up transistor PU2 and to the electrode430_23through the gate contact810_4, thus the drain regions of the pull-down transistor PD2 and the pass-gate transistor PG2 are also electrically coupled to the drain region of the pull-up transistor PU2, and the gate regions of the pull-up transistor PU1 and the pull-down transistor PD1.

For the SRAM cells MC7 and MC8, the N-type well region NW3 is arranged in the middle of the SRAM cells MC7 and MC8, and the P-type well regions PW3 and PW4 are arranged on opposite sides of the N-type well region NW3.

In the SRAM cell MC7 ofFIG.8, the semiconductor fin140_3is also configured to serve as the channel regions of the pass-gate transistor PG1 and the pull-down transistor PD1. Furthermore, the pass-gate transistor PG1 and the pull-down transistor PD1 are formed in the P-type well region PW4. For the pass-gate transistor PG1, an electrode430_21is configured to electrically connect a gate structure corresponding to a gate region of the pass-gate transistor PG1, and the contacts410-21and410-22are configured to electrically connect the drain and source regions of the pass-gate transistor PG1, respectively. For the pull-down transistor PD1, an electrode430_20is configured to electrically connect a gate structure corresponding to a gate region of the pull-down transistor PD1, and the contacts410_21and410_20are configured to electrically connect the drain and source regions of the pull-down transistor PD1, respectively.

For the SRAM cells arranged in the same column, the semiconductor fin140_3is shared by the pass-gate transistor PG1 and the pull-down transistor PD1 of the SRAM cells, and the semiconductor fin140_3is configured to serve as the channel regions of the pass-gate transistor PG1 and the pull-down transistor PD1 of the SRAM cells arranged in the same column. As described above, the semiconductor fin140_3is continuous fin including with Si.

In the SRAM cell MC7 ofFIG.8, the semiconductor fin120_6is configured to serve as the channel region of the pull-up transistor PU1. Furthermore, the pull-up transistor PU1 is formed in the N-type well region NW3. For the pull-up transistor PU1, the electrode430_20is configured to electrically connect a gate structure corresponding to a gate region of the pull-up transistor PU1, and the contact410_21and410_25are configured to electrically connect the drain and source regions of the pull-up transistor PU1, respectively. As described above, the electrode430_20is also electrically coupled to the gate region of the pull-down transistor PD1, and the contact410_21is also electrically coupled to the drain regions of the pull-down transistor PD1 and the pass-gate transistor PG1.

In the SRAM cell MC7 ofFIG.8, the semiconductor fin120_7is also configured to serve as the channel region of the pull-up transistor PU2. Furthermore, the pull-up transistor PU2 is formed in the N-type well region NW3. For the pull-up transistor PU2, the electrode430_25is configured to electrically connect a gate structure corresponding to a gate region of the pull-up transistor PU2, and the contact410_27and410_28are configured to electrically connect the drain and source regions of the pull-up transistor PU2, respectively. Furthermore, the electrode430_25is configured to electrically connect the contact410_27through a gate contact810_1, thus the gate region of the pull-up transistor PU2 is electrically coupled to the drain regions of the pull-up transistor PU1, the pull-down transistor PD1, and the pass-gate transistor PG1.

For the SRAM cells arranged in the same column, the pull-up transistors PU1 of the two adjacent SRAM cells share the same semiconductor fin, and the pull-up transistors PU2 of the two adjacent SRAM cells share the same semiconductor fin. As described above, the semiconductor fins120_6,120_7and120_8are discontinuous fin lines including non-SiGe material.

In the SRAM cell MC7 ofFIG.8, the semiconductor fin140_4is also configured to serve as the channel regions of the pass-gate transistor PG2 and the pull-down transistor PD2. Furthermore, the pass-gate transistor PG2 and the pull-down transistor PD2 are formed in the P-type well region PW3. For the pass-gate transistor PG2, an electrode430_24is configured to electrically connect a gate structure corresponding to a gate region of the pass-gate transistor PG2, and the contacts410_27and410_26are configured to electrically connect the drain and source regions of the pass-gate transistor PG2, respectively. For the pull-down transistor PD2, the electrode430_25is configured to electrically connect a gate structure corresponding to a gate region of the pull-down transistor PD2, and the contacts410_27and410_29are configured to electrically connect the drain and source regions of the pull-down transistor PD2, respectively. As described above, the electrode430_25is also electrically coupled to the gate region of the pull-up transistor PU2, thus the gate region of the pull-down transistor PD2 is also electrically coupled to the drain regions of the pull-up transistor PU1, the pull-down transistor PD1, and the pass-gate transistor PG1. Moreover, the contact410_27is electrically coupled to the drain region of the pull-up transistor PU2 and to the electrode430_20through the gate contact8102, thus the drain regions of the pull-down transistor PD2 and the pass-gate transistor PG2 are also electrically coupled to the drain region of the pull-up transistor PU2, and the gate regions of the pull-up transistor PU1 and the pull-down transistor PD1.

For the SRAM cells arranged in the same column, the semiconductor fin140_4are shared by the pass-gate transistor PG2 and the pull-down transistor PD2 of the SRAM cells, and the semiconductor fin140_4are configured to serve as the channel regions of the pass-gate transistor PG2 and the pull-down transistor PD2 of the SRAM cells arranged in the same column. As described above, the semiconductor fin140_4is continuous fin lines including Si.

For the SRAM cell MC7, the word line WL corresponding to the SRAM cell MC7 is coupled to the gate regions of the pass-gate transistors PG1 and PG2 through the gate contacts820_1and8203, respectively. Similarly, for the SRAM cell MC8, the word line WL corresponding to the SRAM cell MC8 is coupled to the gate regions of the pass-gate transistors PG1 and PG2 through the gate contacts820_2and820_4, respectively.

FIG.9is a schematic diagram cross-sectional view taken along line C-CC ofFIG.8, illustrating a cross-sectional view of the SRAM cells MC7 and MC8 of the SRAM50B, in accordance with some embodiments of the disclosure.

The N-type well region NW3 is formed on the substrate510. The semiconductor fin120_7is formed on the N-type well region NW3. Multiple gate structures610_10-610_13are positioned on the semiconductor fin120_7. Each of the gate structures610_10-610_13may include a gate dielectric layer530and a gate electrode (e.g.,430_20,430_25,430_26and430_23). Gate spacers620may be formed on opposite sidewalls of the gate structures. In addition, source/drain features630_10-630_12may be formed in a doping layer on outer sidewalls of the gate spacers620of the two adjacent gate structures. For example, the source/drain feature630_11is formed between the gate spacer620on the right side of the gate structure610_11and the gate spacer620on the left side of the gate structure61012. Specifically, each of the source/drain features630_10-630_12is extending from the channel regions of the P-type FinFETs.

The source/drain features630_10-630_12are configured to serve as the source/drain regions of the pull-up transistors PU2 in the fin structure120_7. The source/drain features630_10-630_12are formed by etching the LDD regions (not shown) within the fin structure120_7to form recesses (not shown), and epitaxially growing a material in the recesses, using suitable methods such as metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), selective epitaxial growth (SEG), the like, or a combination thereof. In some embodiments, the source/drain features630_10-630_12include silicon germanium (SiGe), and a p-type impurity such as boron or indium. In some embodiments, the Ge atomic concentration in source/drain features630_10-630_12is in a range from about 30% to about 75%. Furthermore, the Ge atomic concentration in the source/drain features630_10-630_12is higher than the Ge atomic concentration in the channel regions of the pass-gate transistors PG2 and PG1. In some embodiments, a silicide layer is formed upon the source/drain features630_10-630_12.

In some embodiments, a fin end of the semiconductor fin120_7is under the electrode430_20, and another fin end of the semiconductor fin120_7is under the electrode43023. Specifically, each semiconductor fin including non-SiGe material across the two adjacent SRAM cells in the N-type well. Furthermore, the semiconductor fin has discontinuous line shape, and the discontinuous ports of the semiconductor fin are closed to the drain regions of the pass-gate transistors PG1 and PG2.

For the SRAM cell MC_7, the gate structure610_11is configured to serve as the gate region of the pull-up transistors PU2, and the source/drain features630_11and630_10are formed in the source and drain regions of the pull-up transistors PU2.

For the SRAM cell MC_8, the gate structure610_12is configured to serve as the gate region of the pull-up transistors PU2, and the source/drain features630_11and630_12are formed in the source and drain regions of the pull-up transistors PU2.

In some embodiments, for each pull-up transistors PU1 and PU2 (i.e., P-type FinFETs of the SRAM cell), the width of the source/drain features is greater than the width of the channel region under the gate structure of the pull-up transistor PU1 or PU2. Taking the pull-up transistor PU2 of the SRAM cell MC7 as an example, the width of the source/drain features630_10and630_11is W3, and the channel region of the gate structure of the pull-up transistor PU2 have a width W4 less than W3 (i.e., W4<W3). In some embodiments, the width W4 of the channel region of the gate structure of the pull-up transistor PU1 or PU2 is within a range from 3 nm to 10 nm.

In an IC, the semiconductor fins including SiGe material are configured to serve as the channel regions of the P-type FinFETs within the standard cells, and the semiconductor fins including non-SiGe material (e.g., Si) are configured to serve as the channel regions of the P-type FinFETs (e.g., pull-up transistors PU1 and PU2) within the SRAM cells. In some embodiments, the channel width (e.g., W4 ofFIG.9) of the P-type FinFETs within the SRAM is narrow than the channel width (e.g., W2 ofFIG.6) of the P-type FinFETs within the logic circuit.

Embodiments of ICs including multiple standard cells and multiple SRAM cells are provided. The standard cells include the P-type FinFETs including SiGe channel formed by the continuous fin lines. Each continuous fin line is arranged across at least three standard cells abutted together. By using the continuous fin lines, line end shrink control of the semiconductor fins become easy and length of diffusion (LOD) effect is decreased for the P-type FinFETs within the standard cells. Furthermore, the SRAM cells include the P-type FinFETs including non-SiGe (e.g. Si) channel formed by the discontinuous fin lines. Each discontinuous fin line is arranged across the two adjacent SRAM cells. Therefore, high channel strain P-type FinFETs (e.g., Ion/Ioff>10% gain) of standard cells (e.g., speed driven logic circuit) and high threshold voltage (Vt) P-type FinFET PU device (that includes purely Si channel without extra channel strain layer) of SRAM cell are provided for write margin improvement as well as low standby requirements. Extra high threshold voltage FinFETs are provided for SRAM cell and lower leakage requirement devices. Therefore, the channel dopant concentration is decreased without considering mis-match and junction leakage. Furthermore, the source and drain regions of the P-type FinFETs of all the standard cells and the SRAM cells include SiGe content.

In some embodiments, an integrated circuit (IC) includes a standard cell array and a SRAM cell array. The standard cell array includes standard cells having first P-type transistors arranged in a first column of the standard cell array and a first fin structure shared by the first P-type transistors. The SRAM cell array includes SRAM cells having second P-type transistors arranged in a second column of the SRAM cell array and second fin structures arranged in the second column. Each of the second fin structures is shared by two adjacent second P-type transistors respectively disposed in two adjacent SRAM cells. A material of the first fin structure is different from a material of the second fin structures. A dimension of the first fin structure along the first column is greater than a dimension of each of the second fin structures along the second column.

In some embodiments, an integrated circuit (IC) includes a first cell array having standard cells and a second cell array having SRAM cells. The first cell array includes a first fin structure shared by first P-type transistors of the standard cells in the same first column of the first cell array and a second fin structure shared by first N-type transistors of the standard cells in the same first column. The second cell array includes a third fin structure shared by two adjacent second P-type transistors in two adjacent SRAM cells in the same second column of the second cell array and a fourth fin structure shared by second N-type transistors of the SRAM cells in the same second column. The second fin structure, the third fin structure, and the fourth fin structure have the same first material, and the first fin structure has a second material different from the first material. Lengths of the first fin structure, second fin structure, and fourth fin structure are longer than a length of the third fin structure.

In some embodiments, an integrated circuit (IC) includes P-type transistors and N-type transistors. The P-type transistors includes first P-type transistors in a first column of a logic cell (10C) array and sharing a first SiGe fin, and second P-type transistors in a second column of a SRAM cell array. Two adjacent second P-type transistors share a first non-SiGe fin. The N-type transistors includes first N-type transistors in the first column and sharing a second non-SiGe fin, and second N-type transistors in the second column and sharing a third non-SiGe fin. A channel width of the second P-type transistors is less than a channel width of the first P-type transistors.

The foregoing outlines nodes of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.