Patent ID: 12189959

DETAILED DESCRIPTION

FIG.1is a diagram of an electronic device10according to an embodiment of the present invention, where the electronic device10may comprise a host device50and a memory device100. The host device50may comprise at least one processor (e.g. one or more processors) which may be collectively referred to as the processor52, and may further comprise a power supply circuit54coupled to the processor52. The processor52is arranged for controlling operations of the host device50, and the power supply circuit54is arranged for providing power to the processor52and the memory device100, and outputting one or more driving voltages to the memory device100. The memory device100may be arranged for providing the host device50with storage space, and obtaining the one or more driving voltages from the host device50as power source of the memory device100. Examples of the host device50may include, but are not limited to: a multifunctional mobile phone, a wearable device, a tablet computer, and a personal computer such as a desktop computer and a laptop computer. Examples of the memory device100may include, but are not limited to: a solid state drive (SSD), and various types of embedded memory devices such as that conforming to Peripheral Component Interconnect Express (PCIe) specification, etc. According to this embodiment, the memory device100may comprise a flash memory controller110, and may further comprise a flash memory module120, where the flash controller110is arranged to control operations of the memory device100and access the flash memory module120, and the flash memory module120is arranged to store information. The flash memory module120may comprise at least one flash memory chip such as a plurality of flash memory chips122-1,122-2, . . . , and122-N, where “N” may represent a positive integer that is greater than one.

As shown inFIG.1, the flash memory controller110may comprise a processing circuit such as a microprocessor112, a storage unit such as a read-only memory (ROM)112M, a control logic circuit114, a RAM116, and a transmission interface circuit118, where the above components may be coupled to one another via a bus. The RAM116is implemented by a Static RAM (SRAM), but the present invention is not limited thereto. The RAM116may be arranged to provide the memory controller110with internal storage space. For example, the RAM116may be utilized as a buffer memory for buffering data. In addition, the ROM112M of this embodiment is arranged to store a program code112C, and the microprocessor112is arranged to execute the program code112C to control the access of the flash memory120. Note that, in some examples, the program code112C may be stored in the RAM116or any type of memory. Further, the control logic circuit114may be arranged to control the flash memory120, and may comprise an encoder132, a decoder134, a randomizer136, a de-randomizer138and other circuits. The transmission interface circuit118may conform to a specific communications specification (e.g. Serial Advanced Technology Attachment (Serial ATA, or SATA) specification, Peripheral Component Interconnect (PCI) specification, Peripheral Component Interconnect Express (PCIe) specification, UFS specification, etc.), and may perform communications according to the specific communications specification, for example, perform communications with the host device50for the memory device100, where the host device50may comprise the corresponding transmission interface circuit conforming to the specific communications specification, for performing communications with the memory device100for the host device50.

In this embodiment, the host device50may transmit host commands and corresponding logical addresses to the memory controller110to access the memory device100. The memory controller110receives the host commands and the logical addresses, and translates the host commands into memory operating commands (which may be simply referred to as operating commands), and further controls the flash memory module120with the operating commands to perform reading, writing/programing, etc. on memory units (e.g. pages) having physical addresses within the flash memory module120, where the physical addresses correspond to the logical addresses. When the flash memory controller110perform an erase operation on any flash memory chip122-nof the plurality of NV memory elements122-1,122-2, . . . , and122-N (in which “n” may represent any integer in the interval [1, N]), at least one block of multiple blocks of the flash memory chip122-nmay be erased, where each block of the blocks may comprise multiple pages (e.g. data pages), and an access operation (e.g. reading or writing) may be performed on one or more pages.

FIG.2is a diagram of a three-dimensional (3D) NAND flash memory according to an embodiment of the present invention. For example, any memory element within the aforementioned at least one of the flash memory chips122-1,122-2, . . . , and122-N, may be implemented based on the 3D NAND flash memory shown inFIG.2, but the present invention is not limited thereto.

According to this embodiment, the 3D NAND flash memory may comprise a plurality of memory cells arranged in a 3D structure, such as (Nx*Ny*Nz) memory cells {{M(1, 1, 1), . . . , M(Nx, 1, 1)}, {M(1, 2, 1), . . . , M(Nx, 2, 1)}, . . . , {M(1, Ny, 1), . . . , M(Nx, Ny, 1)}, {M(1, 1, 2), . . . , M(Nx, 1, 2)}, {M(1, 2, 2), . . . , M(Nx, 2, 2)}, . . . , {M(1, Ny, 2), . . . , M(Nx, Ny, 2)}, . . . , and {M(1, 1, Nz), . . . , M(Nx, 1, Nz)}, {M(1, 2, Nz), . . . , M(Nx, 2, Nz)}, . . . , {M(1, Ny, Nz), . . . , M(Nx, Ny, Nz)}} that are respectively arranged in Nz layers perpendicular to the Z-axis and aligned in three directions respectively corresponding to the X-axis, the Y-axis, and the Z-axis, and may further comprise a plurality of selector circuits for selection control, such as (Nx*Ny) upper selector circuits {MBLS(1, 1), . . . , MBLS(Nx, 1)}, {MBLS(1, 2), . . . , MBLS(Nx, 2)}, . . . , and {MBLS(1, Ny), . . . , MBLS(Nx, Ny)} that are arranged in an upper layer above the Nz layers and (Nx*Ny) lower selector circuits {MSLS(1, 1), . . . , MSLS(Nx, 1)}, {MSLS(1, 2), . . . , MSLS(Nx, 2)}, . . . , and {MSLS(1, Ny), . . . , MSLS(Nx, Ny)} that are arranged in a lower layer below the Nz layers. In addition, the 3D NAND flash memory may comprise a plurality of bit lines and a plurality of word lines for access control, such as Nx bit lines BL(1), . . . , and BL(Nx) that are arranged in a top layer above the upper layer and (Ny*Nz) word lines {WL(1, 1), WL(2, 1), . . . , WL(Ny, 1)}, {WL(1, 2), WL(2, 2), . . . , WL(Ny, 2)}, . . . , and {WL(1, Nz), WL(2, Nz), . . . , WL(Ny, Nz)} that are respectively arranged in the Nz layers. Additionally, the 3D NAND flash memory may comprise a plurality of selection lines for selection control, such as Ny upper selection lines BLS(1), BLS(2), . . . , and BLS(Ny) that are arranged in the upper layer and Ny lower selection lines SLS(1), SLS(2), . . . , and SLS(Ny) that are arranged in the lower layer, and may further comprise a plurality of source lines for providing reference levels, such as Ny source lines SL(1), SL(2), . . . , and SL(Ny) that are arranged in a bottom layer below the lower layer.

As shown inFIG.2, the 3D NAND flash memory may be divided into Ny circuit modules PS2D(1), PS2D(2), . . . , and PS2D(Ny) distributed along the Y-axis. For better comprehension, the circuit modules PS2D(1), PS2D(2), . . . , and PS2D(Ny) may have some electrical characteristics similar to that of a planar NAND flash memory having memory cells arranged in a single layer, and therefore may be regarded as pseudo-2D circuit modules, respectively, but the present invention is not limited thereto. In addition, any circuit module PS2D(ny) of the circuit modules PS2D(1), PS2D(2), . . . , and PS2D(Ny) may comprise Nx secondary circuit modules S(1, ny), . . . , and S(Nx, ny), where “ny” may represent any integer in the interval [1, Ny]. For example, the circuit module PS2D(1) may comprise Nx secondary circuit modules S(1, 1), . . . , and S(Nx, 1), the circuit module PS2D(2) may comprise Nx secondary circuit modules S(1, 2), . . . , and S(Nx, 2), . . . , and the circuit module PS2D(Ny) may comprise Nx secondary circuit modules S(1, Ny), . . . , and S(Nx, Ny). In the circuit module PS2D(ny), any secondary circuit module S(nx, ny) of the secondary circuit modules S(1, ny), . . . , and S(Nx, ny) may comprise Nz memory cells M(nx, ny, 1), M(nx, ny, 2), . . . , and M(nx, ny, Nz), and may comprise a set of selector circuits corresponding to the memory cells M(nx, ny, 1), M(nx, ny, 2), . . . , and M(nx, ny, Nz), such as the upper selector circuit MBLS(nx, ny) and the lower selector circuit MSLS(nx, ny), where “nx” may represent any integer in the interval [1, Nx]. The upper selector circuit MBLS(nx, ny) and the lower selector circuit MSLS(nx, ny) and the memory cells M(nx, ny, 1), M(nx, ny, 2), . . . , and M(nx, ny, Nz) may be implemented with transistors. For example, the upper selector circuit MBLS(nx, ny) and the lower selector circuit MSLS(nx, ny) may be implemented with ordinary transistors without any floating gate, and any memory cell M(nx, ny, nz) of the memory cells M(nx, ny, 1), M(nx, ny, 2), . . . , and M(nx, ny, Nz) may be implemented with a floating gate transistor, where “nz” may represent any integer in the interval [1, Nz], but the present invention is not limited thereto. Further, the upper selector circuits MBLS(1, ny), . . . , and MBLS(Nx, ny) in the circuit module PS2D(ny) may perform selection according to the selection signal on the corresponding selection line BLS(ny), and the lower selector circuits MSLS(1, ny), . . . , and MSLS(Nx, ny) in the circuit module PS2D(ny) may perform selection according to the selection signal on the corresponding selection line SLS(ny).

FIG.3is a diagram illustrating a flash memory chip300according to one embodiment of the present invention, wherein the flash memory chip300can be any one of the flash memory chips122-1-122-N shown inFIG.1. As shown inFIG.3, the flash memory chip300comprises a peripheral circuit310, a control circuit320, a sense amplifier330and a memory array340, wherein the memory array340comprises the memory cells as shown inFIG.2, the control circuit320is configured to control the sense amplifier330to read the data from the memory array340, and the peripheral circuit310comprise pads and interface circuits that are connected to the flash memory controller110.

FIG.4is a flowchart of a control method of the memory device100according to one embodiment of the present invention. In Step400, the flow starts, and the memory device100is powered on. In Step402, the flash memory device110sends a first read command to the flash memory module120, wherein the first read command requests data in at least one page of a block within the flash memory module120. In the following description, it is assumed that the first read command requests the data in one page of a SLC block. In Step404, after receiving the first read command from the flash memory controller110, the control circuit320uses a read voltage to read all of the memory cells corresponding to the page to generate first readout information.FIG.5shows a voltage distribution of a memory cell and a read voltage Vr according to one embodiment of the present invention. As shown inFIG.5, the memory cell is configured to store one bit, and the memory cell has only one of two states S0 and S1, wherein the state S0 corresponds to a logical value “0”, and the state S1 corresponds to a logical value “1”. The control circuit320controls the sense amplifiers330to use the read voltage Vr to read each memory cell to determine the logical value of the memory cell, if the memory cell is conductive when the read voltage Vr is applied, the control circuit320determines that the memory cell corresponds to the logical value “1”; and if the memory cell is not conductive when the read voltage Vr is applied, the control circuit320determines that the memory cell corresponds to the logical value “0”. The above logical value of each memory cell determined by the control circuit320can be called a sign bit, and the sign bits of all the memory cells corresponding to the page can be called hard information, wherein the first readout information comprises the hard information. It is noted that, because of the voltage distribution of the state S0 and state S1, the sign bit of the memory cell determined by the control circuit320may not be the actual logical value.

In Step406, the flash memory module120transmits the first readout information to the flash memory controller110.

In Step408, after receiving the first readout information from the flash memory module120, the de-randomizer138de-randomizes the first readout information, and the decoder134performs a hard decoding method, such as Bose-Chaudhuri-Hocquenghem (BCH) decoding method or LDPC decoding method, to decode the first readout information (de-randomized first readout information).

In Step410, if the decoder134fail to use the hard decoding method to decode the first readout information, the flow enters Step414; and if the first readout information is successfully decoded, the flow enters Step412to finish this flow.

In Step414, because the decoder134fail to use the hard decoding method to decode the first readout information, it means that a number of error bits in the readout information exceeds a number of error bits that the decoder134can correct. Therefore, the flash memory controller110sends a second read command to the flash memory module120, wherein the second read command requests soft information in the same page as the first read command in Step402.

In this embodiment, the second read command comprises at least a compression mode indicator, a voltage offset value Δ, a physical address of the page.

In Step416, after receiving the second read command from the flash memory controller110, the control circuit320uses two read voltages to read all of the memory cells corresponding to the page to generate soft information, wherein the two read voltages are (Vr+Δ) and (Vr−Δ).FIG.6shows using the read voltages (Vr+Δ) and (Vr−Δ) to read the memory cell according to one embodiment of the present invention. As shown inFIG.6, the control circuit320controls the sense amplifiers330to use the read voltages (Vr+Δ) and (Vr−Δ) to read each memory cell to determine the soft bit of the memory cell. For example, if the memory cell is conductive when the read voltage (Vr+Δ) is applied, or the memory cell is not conductive when the read voltage (Vr−Δ) is applied, the control circuit320determines that the memory cell corresponds to a strong region, and the soft bit of the memory cell is a strong bit “1”. If the memory cell is conductive when the read voltage (Vr−Δ) is applied, and the memory cell is not conductive when the read voltage (Vr+Δ) is applied, the control circuit320determines that the memory cell corresponds to a weak region, and the soft bit of the memory cell is a soft bit “0”. The soft bits of all the memory cells corresponding to the page can be called soft information.

In this embodiment, most of the soft bits of the pages should be the strong bit “1”, for example, assuming that the soft information comprises 32768 soft bits, only a few hundred of them may be “0”. Therefore, since most of the soft bits within the soft information are strong bits “1”, the control circuit320can compress the soft information to lower the size in Step418, to reduce the burden of subsequent data transmission. Specifically, referring toFIG.7andFIG.8,FIG.7shows hard information and soft information according to one embodiment of the present invention, andFIG.8shows compressed soft information800according to one embodiment of the present invention. As shown inFIG.7andFIG.8, the control circuit320can record a weak bit location of the soft bits of the soft information, wherein the weak bit location can be a sequence number of the soft bit whose value is “0”, such as the sequence number #6 and sequence number #11 shown inFIG.7. Then, the control circuit320generates the compressed soft information800comprising a header810and a plurality of fields820_1-820_N, wherein the header810comprises at least a compression mode indicator, a number of weak bits (i.e., the value “N”) and the physical address of the page, and each of the fields820_1-820_N records a weak bit location. For example, the field820_1records the sequence number #6, and the field820_2records the sequence number #11 shown inFIG.7.

In the above embodiment, if the soft information comprises 600 weak bits, and each of the field820_1-820_N uses two bytes to record the weak bit location, the size of the compressed soft information may be a little over 1200 bytes. Therefore, compared with the uncompressed soft information with 32768 bits (4096 bytes), the compressed soft information indeed has lower size.

In Step420, the flash memory module120transmits the second readout information to the flash memory controller110, wherein the second readout information comprises the compressed soft information.

In Step422, after receiving the second readout information from the flash memory module120, an internal circuit of the control logic circuit114decompresses the second readout information to regenerate the soft information shown inFIG.7. In Step424, the decoder134performs a soft decoding method to decode the hard information obtained in Step408by using the soft information. For example, the decoder134can use a weighted bit-flipping decoding algorithm of the LDPC to decode the hard information by using the soft information. Because the soft decoding method is known by a person skilled in the art, the descriptions of the detailed decoding steps are omitted here.

In light of the above embodiments shown inFIG.3-FIG.8, by compressing the soft information, the second readout information transmitted by the flash memory module120has much smaller data size, so that the performance of the memory interface will not be affected due to the bandwidth occupied by the soft information transmission.

FIG.9is a flowchart of a control method of the memory device100according to one embodiment of the present invention. In Step900, the flow starts, and the memory device100is powered on. In Step902, the flash memory device110sends a first read command to the flash memory module120, wherein the first read command requests data in at least one page of a block within the flash memory module120. In the following description, it is assumed that the first read command requests the data in one page of a SLC block. In Step904, after receiving the first read command from the flash memory controller110, the control circuit320uses a read voltage to read all of the memory cells corresponding to the page to generate first readout information, as shown inFIG.5. Similar to the Step404shown inFIG.4, the first readout information comprises hard information including a plurality of sign bits of the page.

In Step906, the flash memory module120transmits the first readout information to the flash memory controller110.

In Step908, after receiving the first readout information from the flash memory module120, the de-randomizer138de-randomizes the first readout information, and the decoder134performs the hard decoding method to decode the first readout information (de-randomized first readout information).

In Step910, if the decoder134fails to use the hard decoding method to decode the first readout information, the flow enters Step914; and if the first readout information is successfully decoded, the flow enters Step912to finish this flow.

In Step914, the decoder134estimates a number of error bits of the first readout information, and if the estimated number of error bits of the first readout information is greater than a threshold value, the flow enters Step928; and if the estimated number of error bits of the first readout information is not greater than a threshold value, the flow enters Step916.

In one embodiment, in the LDPC decoding steps, many syndromes and many syndrome weights are generated, and the decoder134can use a distribution of these syndrome weights to estimate the number of error bits of the first readout information. It is noted that the estimation of the number of error bits is known by a person skilled in the art, so the detailed description is omitted here.

In Step916, the flash memory controller110sends a second read command with a compression mode indicator to the flash memory module120, wherein the second read command requests soft information in the same page as the first read command in Step902. In addition, the second read command further comprises a voltage offset value Δ and a physical address of the page.

In Step918, after receiving the second read command from the flash memory controller110, the control circuit320uses two read voltages to read all of the memory cells corresponding to the page to generate soft information, wherein the two read voltages are (Vr+Δ) and (Vr−Δ) shown inFIG.6. In Step920, the control circuit320compresses the soft information to generate compressed soft information. In Step922, the flash memory module120transmits the second readout information to the flash memory controller110, wherein the second readout information comprises the compressed soft information. In Step924, after receiving the second readout information from the flash memory module120, an internal circuit of the control logic circuit114decompresses the second readout information to regenerate the soft information shown inFIG.7. In Step926, the decoder134performs a soft decoding method to decode the hard information obtained in Step908by using the soft information. For example, the decoder134can use a weighted bit-flipping decoding algorithm of the LDPC to decode the hard information by using the soft information.

In Step928, the flash memory controller110sends a second read command with a normal mode indicator or a non-compression mode indicator to the flash memory module120, wherein the second read command requests soft information in the same page as the first read command in Step902. In addition, the second read command further comprises a voltage offset value Δ and a physical address of the page.

In Step930, after receiving the second read command from the flash memory controller110, the control circuit320uses two read voltages to read all of the memory cells corresponding to the page to generate soft information, wherein the two read voltages are (Vr+Δ) and (Vr−Δ) shown inFIG.6. In Step932, the flash memory module120transmits the second readout information to the flash memory controller110, wherein the second readout information comprises the soft information shown inFIG.7. In Step934, the decoder134performs a soft decoding method to decode the hard information obtained in Step908by using the soft information. For example, the decoder134can use a weighted bit-flipping decoding algorithm of the LDPC to decode the hard information by using the soft information.

In the embodiment shown inFIG.9, in order to avoid that the compressed soft information has larger size close to a size of original soft information, when the number of error bits of the first readout information is greater than the threshold value, the control circuit320within the flash memory module120does not compress the soft information, and the second readout information comprising the original soft information is transmitted to the flash memory controller110. That is, only when the number of error bits of the first readout information is lower than the threshold value, the control circuit320will compress the soft information to generate the compressed soft information.

Briefly summarized, in the control method of the memory device of the present invention, by compressing the soft information, the second readout information transmitted by the flash memory module has much smaller data size, so that the performance of the memory interface will not be affected due to the bandwidth occupied by the soft information transmission.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.