Patent ID: 12231144

Throughout the drawings and the detailed description, unless otherwise described or provided, the same drawing reference numerals will be understood to refer to the same elements, features, and structures. The drawings may not be to scale, and the relative size, proportions, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience.

DETAILED DESCRIPTION

The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and/or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatuses, and/or systems described herein will be apparent after an understanding of the disclosure of this application. For example, the sequences of operations described herein are merely examples, and are not limited to those set forth herein, but may be changed as will be apparent after an understanding of the disclosure of this application, with the exception of operations necessarily occurring in a certain order. Also, descriptions of features that are known in the art may be omitted for increased clarity and conciseness.

The features described herein may be embodied in different forms, and are not to be construed as being limited to the examples described herein. Rather, the examples described herein have been provided merely to illustrate some of the many possible ways of implementing the methods, apparatuses, and/or systems described herein that will be apparent after an understanding of the disclosure of this application.

Although terms such as “first,” “second,” and “third” may be used herein to describe various members, components, regions, layers, or sections, these members, components, regions, layers, or sections are not to be limited by these terms. Rather, these terms are only used to distinguish one member, component, region, layer, or section from another member, component, region, layer, or section. Thus, a first member, component, region, layer, or section referred to in examples described herein may also be referred to as a second member, component, region, layer, or section without departing from the teachings of the examples.

Throughout the specification, when an element, such as a layer, region, or substrate, is described as being “on,” “connected to,” or “coupled to” another element, it may be directly “on,” “connected to,” or “coupled to” the other element, or there may be one or more other elements intervening therebetween. In contrast, when an element is described as being “directly on,” “directly connected to,” or “directly coupled to” another element, there can be no other elements intervening therebetween.

As used herein, the term “and/or” includes any one and any combination of any two or more of the associated listed items.

Spatially relative terms such as “above,” “upper,” “below,” and “lower” may be used herein for ease of description to describe one element's relationship to another element as shown in the figures. Such spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, an element described as being “above” or “upper” relative to another element will then be “below” or “lower” relative to the other element. Thus, the term “above” encompasses both the above and below orientations depending on the spatial orientation of the device. The device may also be oriented in other ways (for example, rotated 90 degrees or at other orientations), and the spatially relative terms used herein are to be interpreted accordingly.

The terminology used herein is for describing various examples only, and is not to be used to limit the disclosure. The articles “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms “comprises,” “includes,” and “has” specify the presence of stated features, numbers, operations, members, elements, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, members, elements, and/or combinations thereof.

Due to manufacturing techniques and/or tolerances, variations of the shapes shown in the drawings may occur. Thus, the examples described herein are not limited to the specific shapes shown in the drawings, but include changes in shape that occur during manufacturing.

The features of the examples described herein may be combined in various ways as will be apparent after an understanding of the disclosure of this application. Further, although the examples described herein have a variety of configurations, other configurations are possible as will be apparent after an understanding of the disclosure of this application.

Unless otherwise defined, all terms used herein including technical or scientific terms have the same meaning as commonly understood by one of ordinary skill in the art to which examples belong. Terms, such as those defined in commonly used dictionaries, are to be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art, and are not to be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings. When describing the example embodiments with reference to the accompanying drawings, like reference numerals refer to like elements and a repeated description related thereto will be omitted.

In order to improve the accuracy of the SAR-type ADC, it is important that the output value of the DAC included in the SAR-type ADC is not affected by external influences such as noise, etc. However, in practical applications, the output value of the DAC may be affected by various noise components (e.g., power noise, ground noise, and noise caused by other external influences).

Accordingly, the examples present an analog-to-digital converter having high performance even in the presence of noise, and an operation method thereof.

In the successive approximation register (SAR) type analog-to-digital converter (ADC) according to various examples, by applying noise components applied to the output value of an internal digital-to-analog converter to the analog signal input terminal of the comparator, the same performance may be obtained as that of a noise-free environment even in the presence of various noise.

FIG.1illustrates a structure of a typical SAR-type ADC100.

Referring toFIG.1, the typical SAR-type ADC100may include a comparator110, a successive approximation register (SAR)120, and a digital-to-analog converter (DAC)130.

The comparator110may compare an analog input signal (or analog input voltage) Vin input through a first input terminal of the comparator110, and a signal Vdac input through a second input terminal of the comparator110, and may output a high or low digital signal Vout according to a result of the comparison. The signal Vdac input through the second input terminal of the comparator110may be an analog signal (or analog voltage) output from the DAC130. In an example, the comparator110may output a high signal when the analog input signal Vin is greater than the output signal Vdac of the DAC130, and the comparator110may output a low signal when the analog input signal Vin is less than the output signal Vdac of the DAC130.

The SAR120may continuously store digital signal values from the most significant bit (MSB) to the least significant bit (LSB) based on the digital signal output from the comparator110, and may output the stored value as a digital signal data (digital output data).

The DAC130may convert the digital signal value stored in the SAR120into an analog signal in accordance with a reference voltage Vref, and output the converted digital signal.

In an example, the DAC130may output an analog signal corresponding to the digital signal value based on a reference voltage ladder132. The analog signal output from the DAC130may be provided to the second input terminal of the comparator110.

As described above, the typical SAR-type ADC100may convert an analog signal into a digital signal based on the DAC130and the comparator110. However, various noise components exist in an actual environment, and the various noise components may affect the output signal of the DAC130. The noise components may degrade the performance of the SAR-type ADC100. In an example, the analog signal output from the reference voltage ladder of the DAC130may be a signal in which various noise components such as power noise, ground noise, or noise caused by external influences, are reflected. The typical SAR-type ADC100may output incorrect digital signal data based on the output signal of the DAC130in which the noise component is reflected.

In an example, in an ideal situation without noise, if an analog input signal is “4.5 mV” and a digital signal value stored in the three-bit SAR120is “101”, the DAC130may output an analog signal of “5 mV” corresponding to the digital signal value “101” based on the reference voltage ladder. In this instance, the comparator110may output a low signal because the analog input signal of “4.5 mV” input through the first input terminal is smaller than the output signal of the “5 mV” of the DAC130input through the second input terminal.

However, in the presence of noise, if an analog input signal is “4.5 mV” and a digital signal value stored in the three-bit SAR120is “101”, the DAC130may output an analog signal of “4 mV” in which a noise component (ΔVnoise=−1 mV) is reflected, instead of an analog signal of “5 mV” corresponding to the digital signal value “100”, based on the reference voltage ladder. In this instance, the comparator110may output a high signal because the analog input signal of “4.5 mV” input through the first input terminal is greater than the output signal of the “4 mV” of the DAC130input through the second input terminal. That is, as the DAC outputs the analog signal in which the noise component is reflected, the comparator outputs the opposite result to the ideal situation without noise, which leads to degradation of the performance of the SAR-type ADC.

Accordingly, in one or more examples of the present disclosure, an analog-to-digital converter having high performance even in the presence of noise and an operation method thereof will be described.

FIG.2illustrates an example structure of a SAR-type ADC200, in accordance with one or more embodiments. Hereinafter, some components of the SAR-type ADC200will be described with reference toFIGS.3A and3B.

FIG.3Aillustrates an example structure of an N-bit SAR-type ADC, in accordance with one or more embodiments.FIG.3Billustrates an example structure of a three-bit SAR-type ADC350, in accordance with one or more embodiments.

Referring toFIG.2, the SAR-type ADC200, according to one or more embodiments, may include a comparator210, a successive approximation register (SAR)220, and a digital-to-analog converter (DAC)230.

In one or more examples, the comparator210may compare an analog signal (or voltage) input through a first input terminal of the comparator210with an analog signal input through a second input terminal of the comparator210, and may output a high digital signal or a low digital signal Vout according to a result of the comparison.

In an example, the analog signal input through the first input terminal of the comparator210may be a signal Vin+ΔVnoise obtained by adding an analog signal ΔVnoise having a noise component output from the DAC230to an analog input signal Vin. The analog input signal Vin may refer to an analog signal input through an input terminal of the SAR-type ADC200. In an example, a signal Vdac′ input through the second input terminal of the comparator210is a signal output from the DAC230, and may be an analog signal Vdac+ΔVnoise in which a noise component is reflected. The comparator210may output a high signal when the analog signal Vin+ΔVnoise input through the first input terminal is greater than the analog signal Vdac+ΔVnoise input through the second input terminal (that is, Vin+ΔVnoise>Vdac+ΔVnoise). The comparator210may output a low signal when the analog signal Vin+ΔVnoise input through the first input terminal is less than the analog signal Vdac+ΔVnoise input through the second input terminal (that is, Vin+ΔVnoise<Vdac+ΔVnoise).

In one or more examples, the SAR220may include an N-bit register, and thus, may continuously store digital signal values from the most significant bit (MSB) to the least significant bit (LSB) based on the digital signal output from the comparator210, and may output the stored value as a digital signal data (digital output data).

In one or more examples, the DAC230may convert the digital signal value stored in the SAR220into an analog signal in accordance with a reference voltage, and may output the analog signal. In one or more examples, the DAC230may output an analog signal corresponding to the digital signal value in accordance with the reference voltage based on a reference voltage ladder1231. In an example, the output analog signal Vdac′ may be a signal Vdac+ΔVnoise to which a noise component applied to the reference voltage ladder1 is applied. In an example, Vdac means an analog signal that the DAC230outputs for a corresponding first digital signal value by using the reference voltage ladder1, in an ideal situation in which no noise component is applied to the reference voltage ladder1.

ΔVnoise may be an analog signal corresponding to the noise component applied to the reference voltage ladder1 in an actual situation in which noise components exist. In an example, the reference voltage ladder1231may be implemented in the form of a resistance type including a plurality of resistance elements, of a capacitor type including a plurality of capacitors, or a combination thereof.

In one or more examples, the DAC230may output the analog signal ΔVnoise corresponding to the noise component applied to the reference voltage ladder1 based on a reference voltage ladder2233. The analog signal ΔVnoise which has the noise component, and is output based on the reference voltage ladder2233, may be provided to the first input terminal of the comparator210, and may be added to the analog input signal Vin. In one or more examples, the analog signal ΔVnoise, which has the noise component, may be added to the analog input signal Vin input to the SAR-type DAC200through an adder. In one or more examples, the reference voltage ladder2233may be formed in the same structure as that of the reference voltage ladder1231in order to have the same resistance value as a resistance value of the reference voltage ladder1231.

In an example, when the reference voltage ladder1231is composed of a plurality of resistance elements or resistors, the reference voltage ladder2233may be composed of a plurality of resistance elements or resistors in the same manner as the reference voltage ladder1231. In another example, when the reference voltage ladder1231is composed of a plurality of capacitors, the reference voltage ladder2233may be composed of a plurality of capacitors in the same manner as the reference voltage ladder1231.

In another example, when the reference voltage ladder1231is implemented in the form of a combination of a plurality of resistance elements and a plurality of capacitors, the reference voltage ladder2233may be implemented in the form of a combination of a plurality of resistance elements and a plurality of capacitors in the same manner as the reference voltage ladder1231.

Referring toFIG.3A, in an example, the reference voltage ladder1231and the reference voltage ladder2233may be connected through a capacitor301. The reference voltage ladder2233may be connected with the reference voltage ladder1231through the capacitor301, so that the reference voltage ladder2233may receive, through the capacitor301, the noise component applied to the reference voltage ladder1231. In an example, a node between the reference voltage ladder2233and the capacitor301may be virtually grounded.

In an example, the reference voltage ladder1231and the reference voltage ladder2233may be configured to have the same structure with the same elements. However, in an example, one end of the reference voltage ladder1231may be connected to the ground, and one end of the reference voltage ladder2233may be open. In an example, the opening of the reference voltage ladder2 means a floating state. In an example, as illustrated inFIG.3B, while the reference voltage ladder1231and the reference voltage ladder2233have the same structure including a plurality of resistance elements, one end of the reference voltage ladder1231may be connected to the ground, and one end of the reference voltage ladder2233may be open. In an example, the opening of the reference voltage ladder2233means a floating state.

In an example, the reference voltage ladder2233may output an analog signal corresponding to a virtual ground value in a state in which the noise component is not applied to the reference voltage ladder1231. According to the example, when the noise component is applied to the reference voltage ladder1231, the reference voltage ladder2233receives, through the capacitor301, the noise component applied to the reference voltage ladder1231, thereby outputting the analog signal ΔVnoise corresponding to the noise component.

Hereinafter, examples of operations of the SAR-type ADC proposed in the one or more examples will be described with reference toFIG.3Bas follows. In an example, for convenience of description, it is assumed that the SAR includes a three-bit register. Additionally, for convenience of description, it is assumed that noise is applied in an operation of determining the value of the least significant bit among operations of determining the values from the most significant bit to the least significant bit of the three-bit SAR. However, one or more examples may be applied in the same manner even when noise is applied in all of the operations of determining the values of the most significant bit to the least significant bit.

First, in an example, an analog input signal Vin of 4.5 mV may be input to the SAR-type ADCs200and350. In an example, the SAR220may perform a preset operation to set the value of the most significant bit D2 to “high”, and preset operations to set the values of the remaining lower-order bits D1 and DO to “low”. Depending on the preset operation, the digital signal value stored in the SAR200may be “100”.

The DAC230may designate a value de4 corresponding to the digital signal value “100” stored in the SAR220by using an internal decoder, thereby outputting an analog signal corresponding to “100” through the reference voltage ladder1231. Since a noise component is not applied to the reference voltage ladder1231, the DAC230may output an analog signal of 4 mV (Vdac=4 mV) corresponding to “100” through the reference voltage ladder1231. In an example, the reference voltage ladder2233of the DAC230may output an analog signal corresponding to the virtual ground value. Since a noise component is not applied to the reference voltage ladder1231, the reference voltage ladder2233may output an analog signal of 0 mV.

The comparator210may compare the analog signal of 4.5 mV input through the first input terminal and the analog signal of 4 mV output from the DAC230, that is, the output signal of the DAC230, input through the second input terminal. Since the value (4.5 mV) of the analog signal input through the first input terminal is greater, the comparator210may output “high”.

The SAR220may set the value of the most significant bit D2 to “high” since the output of the comparator210is “high”.

Next, the SAR220may preset values of the remaining bits other than the set most significant bit. In order to determine the value of the second most significant bit D1, the SAR200may preset the value of the second most significant bit D1 to “high” and the value of the least significant bit D0 to “low”.

Depending on the setting of the most significant bit and the preset operation to set other bits (D1 and D0) other than the most significant bit (D1), the digital signal value stored in the SAR200may be “110”.

The DAC230may designate a value de6 corresponding to the digital signal value “110” stored in the SAR220by using an internal decoder, thereby outputting an analog signal corresponding to “110” through the reference voltage ladder1231. Since a noise component is not applied to the reference voltage ladder1231, the DAC230may output an analog signal of 6 mV (Vdac=6 mV) corresponding to “110” through the reference voltage ladder1231. In an example, the reference voltage ladder2233of the DAC230may output an analog signal corresponding to the virtual ground value. Since a noise component is not applied to the reference voltage ladder1231, the reference voltage ladder2233may output an analog signal of 0 mV.

The comparator210may compare the analog signal of 4.5 mV input through the first input terminal and the analog signal of 6 mV, that is, the output signal of the DAC230, input through the second input terminal. Since the value of the analog signal input through the first input terminal may be smaller than the value of the signal input through the second input terminal, the comparator210may output “low”.

The SAR220may set the value of the second most significant bit D1 to “low” since the output of the comparator210is “low”.

Next, the SAR220may preset the value of the least significant bit DO, that is the remaining bit other than the set most significant bit D2 and the second most significant bit D1. In order to determine the value of the least significant bit DO, the SAR200may preset the value of the least significant bit D0 to “high”.

Based on the setting of the most significant bit (D2) and the second most significant bit (D1) and the preset operation to set the least significant bit (D0), the digital signal value stored in the SAR200may be “101”.

The DAC230designates a value de5 corresponding to the digital signal value “101” stored in the SAR220by using an internal decoder, thereby outputting an analog signal corresponding to “101” through the reference voltage ladder1231. In an example, since the noise component is applied to the reference voltage ladder1231, the DAC230may output the analog signal of 4 mV (5 mV(Vdac)+(−1 mV(ΔVnoise))) which has been changed by the influence of the noise component instead of an analog signal of 5 mV corresponding to “101” through the reference voltage ladder1231. In an example, the reference voltage ladder2233of the DAC230may receive the noise component applied to the reference voltage ladder1231through the capacitor301, and thus may output an analog signal of −1 mV corresponding to the noise component. The analog signal of −1 mV having the noise component output from the reference voltage ladder2233may be added to the analog input signal Vin and input to the first input terminal of the comparator210.

In an example comparator210may receive, through the first input terminal, an analog signal of 3.5 mV (4.5 mV (Vin)+(−1 mV (ΔVnoise))) obtained by adding the analog input signal Vin of 4.5 mV and an analog signal of −1 mV having the noise component output from the DAC230. The comparator210may compare the analog signal of 3.5 mV input through the second input terminal and the analog signal of 4 mV (5 mV (Vdac)+(−1 mV(ΔVnoise))), that is, the output signal of the DAC230. Since the value of the analog signal input through the first input terminal may be smaller than the value of the analog signal input through the second input terminal (Vin+ΔVnoise<Vdac+ΔVnoise), the comparator210may output “low”.

The SAR220may set the value of the least significant bit D0 to “low” since the output of the comparator210is “low”.

Finally, the SAR220may output a final digital data of “100”.

As described above, in the SAR-type ADC according to one or more embodiments, the same noise component may be applied to analog signals which are input to both terminals of the comparator210, so that the influence by the noise component in the comparator210can be cancelled. That is, in the SAR-type ADC according to one or more examples, even if noise is generated in the DAC, the comparator210may be able to output a result signal based on the difference between the analog input signal (Vin) and the output signal (Vdac) of the internal DAC, without being affected by the noise.

InFIG.3Bdescribed above, it is assumed that the DAC230is a resistor type DAC (RDAC), which includes the reference voltage ladders231and233composed of resistance elements. However, according to various embodiments, the reference voltage ladder1231and the reference voltage ladder2233of the DAC may be disposed to include both the capacitor and resistance elements.

In one or more examples, in an n-bit SAR-type ADC, the DAC may be composed of the resistor type DAC (RDAC) which is responsible for higher-order “a” bits and a capacitor type DAC (CDAC) which is responsible for lower-order “b” (n-a) bits. Conversely, in the n-bit SAR-type ADC, the DAC may be composed of the CDAC which is responsible for the higher-order “a” bits and the RDAC which is responsible for the lower-order “b” (n-a) bits.

FIG.4illustrates an example structure of a ten-bit SAR-type ADC, in accordance with one or more embodiments.

As illustrated inFIG.4, a DAC401may include a reference voltage ladder1431composed of a RDAC1413which is responsible for higher-order seven bits, and a CDAC1411which is responsible for lower-order three bits, and a reference voltage ladder2433composed of a RDAC2423which is responsible for the higher-order seven bits, and a CDAC2421which is responsible for the lower-order three bits. The SAR-type ADC illustrated inFIG.4differs from the example ofFIG.3Bonly in that the reference voltage ladder1 and the reference voltage ladder2 are composed of resistance elements and capacitors, and other example structures and/or example operation methods may be the same as described with reference toFIG.3B.

In an example, the reference voltage ladder1431and the reference voltage ladder2433may be, as described inFIGS.2to3B, connected through the capacitor301, and one end of the reference voltage ladder1431may be connected to the ground and one end of the reference voltage ladder2433may be opened. Additionally, the reference voltage ladder2433may receive a voltage component applied to the reference voltage ladder1431through the capacitor301, thereby outputting an analog signal corresponding to the noise component.

FIG.5is a flowchart illustrating an example of converting an analog signal to a digital signal in the SAR-type ADC, in accordance with one or more embodiments.

The operations inFIG.5may be performed in the sequence and manner as shown, although the order of some operations may be changed or some of the operations omitted without departing from the spirit and scope of the illustrative examples described. Many of the operations shown inFIG.1may be performed in parallel or concurrently.

In an example, the SAR-type ADC may be the SAR-type ADC described with reference toFIGS.2,3A,3B, and/or4.

Referring toFIG.5, in operation501, the SAR-type ADC may receive the analog input signal Vin. The analog input signal Vin may be provided to a first input terminal of the comparator210.

In operation503, the SAR220of the SAR-type ADC may perform a preset operation from the most significant bit to the least significant bit of the N-bit register. In an example, the SAR220may preset the value of the bit, which is to be set, to “high”, and may then set the next lower-order bits to “low”. In an example, in an operation of setting the most significant bit (MSB), the value of the most significant bit (MSB) may be preset to “high”, and the other bits may be preset to “low”. In another example, in an operation of setting the second most significant bit, the value of the second most significant bit may be preset to “high”, and the next lower-order bits may be preset to “low”.

In operation505, the DACs230and401of the SAR-type ADC may output an analog signal (Vdac+ΔVnoise) in which the noise component is reflected to a second input terminal of the comparator. In an example, the DACs230and401may convert the digital signal value set in the SAR into an analog signal in accordance with a reference voltage by using the reference voltage ladders1231and431. In an example, a noise component may be applied to the reference voltage ladders1231and431, and the analog signal converted by reflecting the noise component may be output by the reference voltage ladders1231and431.

In operation507, the DACs230and401of the SAR-type ADC may output the signal ΔVnoise having a noise component. In an example, the DACs230and401may output an analog signal corresponding to the noise component by using the reference voltage ladders2233and433through the reference voltage ladders1231and431and the capacitor301. For example, the reference voltage ladders2233and433receive, through the capacitor301, the noise component applied to the reference voltage ladders1231and431, thereby outputting the analog signal corresponding to the noise component. When a noise component is not applied to the reference voltage ladders1231and431, the reference voltage ladders2233and433may output a virtual ground value.

In operation509, the SAR-type ADC may add the signal ΔVnoise having the noise component output from the DACs230and401to the analog signal received in operation501, and may input the signal to a first input terminal of the comparator210.

In operation511, the comparator210of the SAR-type ADC may compare the signals of the first input terminal and the second input terminal, and may output a result signal based on a result of the comparison to the SAR220.

In operation513, the SAR220of the SAR-type ADC may set (or fix) the value of the corresponding bit based on the output signal of the comparator210.

In operation515, the SAR220of the SAR-type ADC may determine whether the value setting for all N bits is completed. When the value setting for all N bits is not completed, the SAR220may return to operation503in order to set the value of the next lower-order bit. When the value setting for all N bits is completed, in an example, when values are set from the most significant bit to the least significant bit, the SAR220may output the values for the N bits as digital data in operation517. In an example, the SAR220may output the values for the N bits as a digital signal for the analog signal received in operation501.

Table 1 below shows the performance evaluation results of a typical SAR-type ADC and the SAR-type ADC proposed in the one or more examples.

In Table 1 below, the typical structure means a typically provided 10-bit SAR-type ADC shown inFIG.1, and the proposed structure may mean a 10-bit SAR-type ADC proposed in the one or more examples illustrated inFIGS.2to4.

TABLE 1PerformanceSNR(dB)SNDR(dB)THD(-dB)ENOB(bit)Typical structure5449517.98Example structure6059679.57

Referring to the performance evaluation results shown in Table 1, it may be seen that characteristics of the ADC having the proposed structure illustrated in the one or more examples with noise components removed, may be significantly better than characteristics of the ADC having the typical structure. In one or more examples, a signal-to-noise ratio (SNR) means an analog signal-to-noise ratio, and a signal-to-noise distortion ratio (SNDR) means an analog signal-to-noise and harmonic distortion ratio. Additionally, a total harmonic distortion (THD) means a total harmonic distortion ratio, and an effective number of bits (ENOB) means the effective number of bits excluding noise and harmonic distortion.

In an example, the SNR may be defined as follows in Equation 1 below.
SNR=10 log(Ps/Pnoise)=20 log(Vsignal/Vnoise)[dB]  Equation (1):

In Equation 1, Ps may mean a desired signal power, and Pnoise may mean an undesired signal power, which may mean noise.

A high analog signal-to-noise ratio means that an applied analog signal can be converted into a more detailed digital signal. In an example, a nine-bit ADC can subdivide an analog signal into 512 (=29) codes, and a ten-bit ADC can subdivide an analog signal into 1024 (=210) codes. In terms of SNR characteristics, this can be noted as Equation 2 and Equation 3 below.

Equation 2 represents the SNR of the nine-bit ADC, and Equation 3 represents the SNR of the ten-bit ADC.
SNR=20 log(Vsignal/noise)==20 log 29/1)=20 log(512)=54 dB  Equation (2):
SNR=20 log(Vsignal/Vnoise)=20 log(210/1)=20 log(1024)=60 dB  Equation (3):

As shown in Equations 2 and 3, when the ADC proposed in the one or more examples is used instead of the typical structure, it can be seen that the characteristics of the ADC may be improved.

The comparator110/210, SAR120/220, DAC130/230, and other apparatuses, units, modules, devices, and other components described herein and with respect toFIGS.1-5, are implemented by hardware components. Examples of hardware components that may be used to perform the operations described in this application where appropriate include controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, and any other electronic components configured to perform the operations described in this application. In other examples, one or more of the hardware components that perform the operations described in this application are implemented by computing hardware, for example, by one or more processors or computers. A processor or computer may be implemented by one or more processing elements, such as an array of logic gates, a controller and an arithmetic logic unit, a digital signal processor, a microcomputer, a programmable logic controller, a field-programmable gate array, a programmable logic array, a microprocessor, or any other device or combination of devices that is configured to respond to and execute instructions in a defined manner to achieve a desired result. In one example, a processor or computer includes, or is connected to, one or more memories storing instructions or software that are executed by the processor or computer. Hardware components implemented by a processor or computer may execute instructions or software, such as an operating system (OS) and one or more software applications that run on the OS, to perform the operations described in this application. The hardware components may also access, manipulate, process, create, and store data in response to execution of the instructions or software. For simplicity, the singular term “processor” or “computer” may be used in the description of the examples described in this application, but in other examples multiple processors or computers may be used, or a processor or computer may include multiple processing elements, or multiple types of processing elements, or both. For example, a single hardware component or two or more hardware components may be implemented by a single processor, or two or more processors, or a processor and a controller. One or more hardware components may be implemented by one or more processors, or a processor and a controller, and one or more other hardware components may be implemented by one or more other processors, or another processor and another controller. One or more processors, or a processor and a controller, may implement a single hardware component, or two or more hardware components. A hardware component may have any one or more of different processing configurations, examples of which include a single processor, independent processors, parallel processors, single-instruction single-data (SISD) multiprocessing, single-instruction multiple-data (SIMD) multiprocessing, multiple-instruction single-data (MISD) multiprocessing, and multiple-instruction multiple-data (MIMD) multiprocessing.

The methods that perform the operations described in this application and illustrated inFIGS.1-5are performed by computing hardware, for example, by one or more processors or computers, implemented as described above executing instructions or software to perform the operations described in this application that are performed by the methods. For example, a single operation or two or more operations may be performed by a single processor, or two or more processors, or a processor and a controller. One or more operations may be performed by one or more processors, or a processor and a controller, and one or more other operations may be performed by one or more other processors, or another processor and another controller, e.g., as respective operations of processor implemented methods. One or more processors, or a processor and a controller, may perform a single operation, or two or more operations.

Instructions or software to control computing hardware, for example, one or more processors or computers, to implement the hardware components and perform the methods as described above may be written as computer programs, code segments, instructions or any combination thereof, for individually or collectively instructing or configuring the one or more processors or computers to operate as a machine or special-purpose computer to perform the operations that are performed by the hardware components and the methods as described above. In one example, the instructions or software include machine code that is directly executed by the one or more processors or computers, such as machine code produced by a compiler. In another example, the instructions or software includes higher-level code that is executed by the one or more processors or computers using an interpreter. The instructions or software may be written using any programming language based on the block diagrams and the flow charts illustrated in the drawings and the corresponding descriptions in the specification, which disclose algorithms for performing the operations that are performed by the hardware components and the methods as described above.

The instructions or software to control computing hardware, for example, one or more processors or computers, to implement the hardware components and perform the methods as described above, and any associated data, data files, and data structures, may be recorded, stored, or fixed in or on one or more non-transitory computer-readable storage media. Examples of a non-transitory computer-readable storage medium include read-only memory (ROM), random-access programmable read only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random-access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROMs, CD-Rs, CD+Rs, CD-RWs, CD+RWs, DVD-ROMs, DVD-Rs, DVD+Rs, DVD-RWs, DVD+RWs, DVD-RAMs, BD-ROMs, BD-Rs, BD-R LTHs, BD-REs, blue-ray or optical disk storage, hard disk drive (HDD), solid state drive (SSD), flash memory, a card type memory such as multimedia card micro or a card for example, secure digital (SD) or extreme digital (XD)), magnetic tapes, floppy disks, magneto-optical data storage devices, optical data storage devices, hard disks, solid-state disks, and any other device that is configured to store the instructions or software and any associated data, data files, and data structures in a non-transitory manner and provide the instructions or software and any associated data, data files, and data structures to one or more processors or computers so that the one or more processors or computers can execute the instructions. In one example, the instructions or software and any associated data, data files, and data structures are distributed over network-coupled computer systems so that the instructions and software and any associated data, data files, and data structures are stored, accessed, and executed in a distributed fashion by the one or more processors or computers.

A number of example embodiments have been described above. Nevertheless, it should be understood that various modifications may be made to these example embodiments. In an example, suitable results may be achieved if the described techniques are performed in a different order and/or if components in a described system, architecture, device, or circuit are combined in a different manner and/or replaced or supplemented by other components or their equivalents.

While this disclosure includes specific examples, it will be apparent after an understanding of the disclosure of this application that various changes in form and details may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in a descriptive sense only, and not for purposes of limitation. Descriptions of features or aspects in each example are to be considered as being applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and/or if components in a described system, architecture, device, or circuit are combined in a different manner, and/or replaced or supplemented by other components or their equivalents. Therefore, the scope of the disclosure is defined not by the detailed description, but by the claims and their equivalents, and all variations within the scope of the claims and their equivalents are to be construed as being included in the disclosure.