Patent ID: 12205541

DETAILED DESCRIPTION

In order to make objects, technical solutions, and advantages of the embodiments of the present disclosure apparent, the technical solutions of the embodiments of the present disclosure will be described in a clearly and fully understandable way in connection with the drawings related to the embodiments of the present disclosure. Apparently, the described embodiments are just a part but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, those skilled in the art can obtain other embodiment(s), without any inventive work, which should be within the scope of the present disclosure.

Unless otherwise defined, all the technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms “first,” “second,” etc., which are used in the present disclosure, are not intended to indicate any sequence, amount or importance, but distinguish various components.

The terms “comprise,” “comprising,” “include,” “including,” etc., are intended to specify that the elements or the objects stated before these terms encompass the elements or the objects and equivalents thereof listed after these terms, but do not preclude the other elements or objects. The phrases “connect”, “connected”, etc., are not intended to define a physical connection or a mechanical connection, but may comprise an electrical connection which is direct or indirect.

FIG.1is a schematic diagram of a pixel driving circuit. As illustrated byFIG.1, the pixel driving circuit includes a driving transistor T1, a compensation transistor T3, a data writing transistor T2, a first light emitting control transistor T4, a second light emitting control transistor T5, an initialization transistor T6, and an electrode reset transistor T7. A source electrode of the driving transistor T1, a drain electrode of the data writing transistor T2and a drain electrode of the first light emitting control transistor T4are electrically connected; a drain electrode of the driving transistor T1, a source electrode of the compensating transistor T3and a source electrode of the second light emitting control transistor T5are electrically connected; a gate electrode of the driving transistor T1, a drain electrode of the compensating transistor T3and a drain electrode of the initialization transistor T6are electrically connected; a drain electrode of the second light emitting control transistor T5and a drain electrode of the electrode reset transistor T7are electrically connected to an anode11of a light emitting element10.

As illustrated byFIG.1, the initialization transistor T6and the electrode reset transistor T7are connected to the same initialization signal line20, and the initialization signal line20needs to drive two kinds of transistors, so that the voltage drop of the initialization signal line from one end to the other end is large, which leads to different potentials of initialization signals reset to the anodes of different light emitting elements upon the electrode reset transistor T7being reset, thus causing problems such as poor brightness uniformity and abnormal brightness jump. On the other hand, because the above initialization signal is used to initialize the voltage of the gate electrode of the driving transistor T1and the voltage of the anode of the light emitting element, the initialization signal needs to meet the initialization requirements of the gate electrode of the driving transistor T1, and the voltage of the initialization signal is usually larger than that of the driving signal on the cathode of the light emitting element. Therefore, in the case where the above initialization signal is used to initialize the voltage of the anode of the light emitting element, there is still a certain voltage difference (usually 1V or more) between the anode and the cathode of the light emitting element, which cannot ensure that the light emitting element is completely turned off.

In this regard, embodiments of the present disclosure provide an array substrate and a display device. The array substrate includes abase substrate and a plurality of pixel driving circuits arranged on the base substrate; each pixel driving circuit includes a driving transistor, a first light emitting control transistor, a compensation transistor, a first initialization transistor and a second initialization transistor; a first electrode of the first initialization transistor and a first electrode of the first light emitting control transistor are connected to a first node, the first initialization transistor is configured to provide a first initialization signal to an anode of a light emitting element through the first node, a first electrode of the second initialization transistor and a first electrode of the compensation transistor are connected to a second node, and the second initialization transistor is configured to provide a second initialization signal to a gate electrode of the driving transistor through the second node, a second electrode of the first initialization transistor is configured to receive a first initialization signal, and a cathode of the light emitting element is configured to receive the first driving signal, and a difference between a potential of the first initialization signal and a potential of the first driving signal is less than 1.5V. Therefore, by setting the difference between the potential of the first initialization signal and the potential of the first driving signal to be less than 1.5V, the array substrate can reduce the voltage difference between the anode and cathode of the light emitting element when initializing the anode of the light emitting element, so that the charge on the anode of the light emitting element can be quickly discharged, and the light emitting element can be turned off completely, so that the problems of stroboscopic and uneven brightness in low gray scale can be alleviated, and the contrast can be improved. In addition, the first initialization signal and the second initialization signal of the array substrate can be transmitted by different initialization signal lines, thereby reducing the load on a single initialization signal line, reducing the voltage drop on a single initialization signal line, and further improving the brightness uniformity.

Hereinafter, the array substrate and the display device provided by the embodiments of the present disclosure will be described below with reference to the accompanying drawings.

An embodiment of the present disclosure provides an array substrate.FIG.2is a schematic plan view of an array substrate according to an embodiment of the present disclosure;FIG.3is an equivalent schematic diagram of a pixel driving circuit in an array substrate according to an embodiment of the present disclosure.

As illustrated byFIG.2andFIG.3, the array substrate100includes a base substrate110and a plurality of pixel driving circuits120disposed on the base substrate110. Each pixel driving circuit120includes a driving transistor T1, a first light emitting control transistor T4, a compensation transistor T3, a first initialization transistor T7and a second initialization transistor T6; a first electrode of the first initialization transistor T7and a first electrode of the first light emitting control transistor T4are connected to the first node N1, and the first initialization transistor T7is configured to provide a first initialization signal Vinit1to an anode131of a light emitting element130through the first node N1, thereby initializing the anode131of the light emitting element130. A first electrode of the second initialization transistor T6and a first electrode of the compensation transistor T3are connected to the second node N2, and the second initialization transistor T6is configured to provide a second initialization signal Vinit2to a gate electrode of the driving transistor T1through the second node N2, so that the gate electrode of the driving transistor T1can be initialized.

As illustrated byFIG.2andFIG.3, a second electrode of the first initialization transistor T7is configured to receive the first initialization signal Vinit1, and a cathode132of the light emitting element130is configured to receive a first driving signal Vss. A difference between a potential of the first initialization signal Vinit1and a potential of the first driving signal Vss is less than 1.5V.

In the array substrate provided by the embodiment of the present disclosure, by setting the difference between the potential of the first initialization signal Vinit1and the potential of the first driving signal Vss to be less than 1.5V, the voltage difference between the anode and the cathode of the light emitting element can be reduced upon the anode of the light emitting element being initialized, so that the charge on the anode of the light emitting element can be quickly released, and the light emitting element can be turned off completely. Therefore, the array substrate can alleviate the problem of stroboscopic and uneven brightness in low gray scale; and because the array substrate can realize the complete turning off of the light emitting elements, the array substrate can also improve the contrast. On the other hand, the first initialization signal and the second initialization signal of the array substrate can be transmitted by different initialization signal lines, thereby reducing the load on a single initialization signal line and reducing the voltage drop on the single initialization signal line. Thus, the array substrate can improve the uniformity of initialization signals reset to the anodes of different light emitting elements when initializing the anodes of light emitting elements, thereby alleviating the problems of poor brightness uniformity, abnormal brightness jump, Flicker and the like.

It should be noted that the transistors used in the embodiments of the present disclosure can be triodes, thin film transistors, field effect transistors or other similar transistors. In the present disclosure, in order to distinguish the two electrodes of a transistor except the control electrode, one of these two electrodes is called the first electrode and the other is called the second electrode. For example, in the case where the transistor is a triode, the first electrode can be the collector and the second electrode can be the emitter; in the case where the transistor is a thin film transistor or a field effect transistor, the first electrode can be a drain electrode and the second electrode can be a source electrode. Of course, the embodiments of the present disclosure include but are not limited thereto, and the types of electrodes referred to by the above-mentioned first electrode and second electrode can be interchanged.

In some examples, further, the difference between the potential of the first initialization signal Vinit1and the potential of the first driving signal Vss is less than 0.5V.

In some examples, as illustrated byFIG.2andFIG.3, each pixel driving circuit120further includes a storage capacitor Cst, and the gate electrode of the driving transistor T1is electrically connected with a first electrode plate CE1of the storage capacitor Cst. The second initialization transistor T6can simultaneously provide a second initialization signal to the gate electrode of the driving transistor T1and the first electrode plate CE1of the storage capacitor Cst through the second node N2, so that the gate electrode of the driving transistor T1and the first electrode plate CE1of the storage capacitor Cst can be initialized.

In some examples, as illustrated byFIG.2andFIG.3, the potential of the first initialization signal Vinit1and the potential of the second initialization signal Vinit2are different. Therefore, the first initialization signal and the second initialization signal of the array substrate are transmitted by different initialization signal lines, thereby reducing the load on a single initialization signal line and reducing the voltage drop on the single initialization signal line. Therefore, the array substrate can improve the uniformity of initialization signals reset to the anodes of different light emitting elements when initializing the anodes of light emitting elements, thereby alleviating the problems of poor brightness uniformity, abnormal brightness jump, Flicker and the like.

In some examples, as illustrated byFIG.2andFIG.3, the potential of the first initialization signal Vinit1is the same as that of the first driving signal Vss. Therefore, by setting the potential of the first initialization signal and the potential of the first driving signal to be the same, the array substrate provided by the embodiment of the present disclosure can eliminate the voltage difference between the anode and cathode of the light emitting element when initializing the anode of the light emitting element, so that the light emitting element can be completely turned off, and the display quality can be improved. In addition, because the cathodes of light emitting elements and Vss signal lines are distributed throughout the array substrate, the voltage drop of the initialization signal line used to transmit the first initialization signal Vinit1can be further reduced, so that the uniformity of initialization signals reset to the anodes of different light emitting elements can be further improved, and the problems of poor brightness uniformity, abnormal brightness jump, Flicker and the like can be alleviated.

In some examples, as illustrated byFIG.2andFIG.3, the array substrate100further includes a first initialization signal line141, a second initialization signal line142, a light emitting element130, and a first power line151; the first initialization signal line141extends in the first direction and applies the first initialization signal Vinit1to the second electrode of the first initialization transistor T7. The second initialization signal line142extends in the first direction and is connected with the second electrode of the second initialization transistor T6to apply the second initialization signal Vinit2to the second electrode of the second initialization transistor T6. The light emitting element130includes an anode131and a cathode132; the first power line151is used to provide a cathode signal to the cathode132of the light emitting element130. The anode131of the light emitting element130is electrically connected with the first node N1, and the first initialization signal line141is connected with the first power line151or the cathode132of the light emitting element130.

In the array substrate provided in this example, because the first initialization signal Vinit1of the first initialization signal line141is the same as the first driving signal Vss of the first power line151, the voltage difference between the anode and the cathode of the light emitting element can be zero when initializing the anode of the light emitting element, so that the charge in the anode of the light emitting element can be quickly released and the light emitting element can be turned off completely. The array substrate can further alleviate the problem of stroboscopic and uneven brightness in low gray scale; and because the array substrate can realize the complete turning off of the light emitting elements, the array substrate can further improve the contrast. In addition, because the first initialization signal line is electrically connected with the first power line or the cathode of the light emitting element, the first initialization signal line does not need to be routed separately, so that the resistance and voltage drop of the first initialization signal line are small, and the uniformity of initialization signals reset to the anodes of different light emitting elements can be further improved, so that the problems of poor brightness uniformity, abnormal brightness jump, Flicker and the like can be alleviated, and the display quality of the display device adopting the array substrate can be significantly improved.

For example, the light emitting element130may further include a light emitting layer (not shown) between the anode131and the cathode132, the specific structure of the light emitting element130can be found in the general design. For example, the light emitting element may be an organic light emitting diode, and the light emitting layer may be an organic light emitting layer. In addition, the light emitting element may also include auxiliary functional film layers such as an electron transport layer, an electron injection layer, a hole transport layer and a hole injection layer.

In some examples, as illustrated byFIG.2andFIG.3, the pixel driving circuit120further includes a second light emitting control transistor T5and a data writing transistor T2. The array substrate100further includes a second power line152, a data line160, a first light emitting control line171, a gate line180, a first reset signal line191and a second reset signal line192; the first electrode of the driving transistor T1, the second electrode of the first light emitting control transistor T4and the second electrode of the compensation transistor T3are connected to the third node N3, the gate electrode of the driving transistor T1is connected with the first electrode plate CE1of the storage capacitor Cst, and the second electrode of the driving transistor T1, the first electrode of the data writing transistor T2and the first electrode of the second light emitting control transistor T5are connected to the fourth node N4.

In some examples, as illustrated byFIG.2andFIG.3, the gate electrode of the first initialization transistor T7is connected with the first reset signal line191, and the first reset signal line191can provide a reset signal to the gate electrode of the first initialization transistor T7; the gate electrode of the second initialization transistor T6is connected to a second reset signal line192, which can provide a reset signal to the gate electrode of the second initialization transistor T6. The second electrode of the data writing transistor T2is connected with the data line160, the gate electrode of the data writing transistor T2and the gate electrode of the compensation transistor T3are respectively connected with the gate line180, the second electrode of the second light emitting control transistor T5and the second electrode plate CE2of the storage capacitor Cst are respectively connected with the second power line152, and a gate electrode of the first light emitting control transistor T4and a gate electrode of the second light emitting control transistor T5are respectively connected with the first light emitting control line171. The first light emitting control line171may provide light emitting control signals to the gate electrode of the first light emitting control transistor T4and the gate electrode of the second light emitting control transistor T5, respectively.

An operation mode of the above pixel driving circuit will be schematically described below. At first, a reset signal is transmitted to the gate electrode of the first initialization transistor T7through the first reset signal line191and the first initialization transistor T7is turned on, and the first initialization signal Vinit1is provided to the second electrode of the first initialization transistor T7through the first initialization signal line141. At this time, the residual current of the anode131of the light emitting element130is discharged through the first initialization transistor T7, so that light emission because of the residual current on the anode of the light emitting element can be suppressed.

The reset signal is transmitted to the gate electrode of the second initialization transistor T6through the second reset signal line192and the second initialization transistor T6is turned on; at this time, the second initialization signal Vinit2is transmitted to the second electrode of the second initialization transistor T6through the second initialization signal line142. At this time, the second initialization signal Vinit2can be applied to the gate electrode of the driving transistor T1and the first electrode plate CE1of the storage capacitor Cst through the second initialization transistor T6, so that the gate electrode of the driving transistor T1and the storage capacitor Cst are initialized.

Then, a gate signal is transmitted to the gate electrode of the data writing transistor T2and the gate electrode of the compensation transistor T3through the gate line180, and the data writing transistor T2and the compensation transistor T3are turned on; the data signal Vd is transmitted to the second electrode of the data writing transistor T2through the data line160; at this time, the driving transistor T1is turned on, and the data signal Vd is applied to the gate electrode of the driving transistor T1through the data writing transistor T2and the compensation thin film transistor T3. At this time, the voltage applied to the gate electrode of the driving transistor T1is the compensation voltage Vd+Vth, and the compensation voltage applied to the gate electrode of the driving transistor T1is also applied to the first electrode plate CE1of the storage capacitor Cst.

Then, the driving voltage Vel is applied to the second electrode plate CE2of the storage capacitor Cst through the second power line152, and the compensation voltage Vd+Vth is applied to the first electrode plate CE1, so that the charges corresponding to the difference between the voltages applied to the two electrode plates of the storage capacitor Cst are stored in the storage capacitor Cst, and the driving transistor T1is turned on for a predetermined time.

Subsequently, emitting control signals are applied to the gate electrode of the first emitting control transistor T4and the gate electrode of the second emitting control transistor T5through the first emitting control line171, and both the first emitting control transistor T4and second emitting control transistor T5are turned on, and the second driving signal Vel is applied to the second electrode of the second emitting control transistor T5through the second power line152. At this time, when the second driving signal Vel passes through the driving transistor T1turned on by the storage capacitor Cst, the voltage of the second electrode of the driving transistor T1is Vel, and the voltage of the gate electrode of the driving transistor T1is Vd+Vth, so that the driving transistor T1can be in a saturated state, and the driving current Ids: Id=K*((Vd+Vth−Vel)−Vth) 2=K*(Vd−Vel)2, K is a structural constant related to the process and the design. Then, the driving current Id is applied to the anode of the light emitting element through the first light emitting control transistor T4, so that the light emitting element emits light.

It should be noted that the above operation mode of the driving circuit is only one possible driving mode of the driving circuit, and the embodiments of the present disclosure include but are not limited thereto.

In some examples, as illustrated byFIG.2, the orthographic projection of the first initialization signal line141on the base substrate110and the orthographic projection of the first reset signal line191on the base substrate110at least partially do not overlap, so that the load can be reduced; similarly, the orthographic projection of the second initialization signal line142on the base substrate110and the orthographic projection of the second reset signal line192on the base substrate110at least partially do not overlap, so that the load can be reduced.

In some examples, as illustrated byFIG.2andFIG.3, the pixel driving circuit120further includes an anti-leakage transistor T8, the first electrode of the anti-leakage transistor T8is electrically connected to the gate electrode of the driving transistor T1, the second electrode of the anti-leakage transistor T8is connected to the second node N2, and the second initialization transistor T6initializes the gate electrode of the driving transistor T1through the second node N2and the anti-leakage transistor T8.

During the operation of the pixel driving circuit, the stability of the voltage on the gate electrode of the driving transistor T1is an important factor related to the display quality such as the uniformity of the display brightness and whether the Flicker phenomenon occurs. Because the first electrode of the second initialization transistor T6and the first electrode of the compensation transistor T3are connected to the second node N2, assuming that the second node N2is directly connected to the gate electrode of the driving transistor T1, to ensure the stability of the voltage on the gate electrode of the driving transistor T1, it is necessary to reduce the leakage current of the second initialization transistor T6and the compensation transistor T3. However, the array substrate provided in this example can improve the stability of the voltage on the gate electrode of the driving transistor T1only by reducing the leakage current of the anti-leakage transistor T8by arranging the anti-leakage transistor T8between the second node N2and the gate electrode of the driving transistor T1, thus improving the display quality.

In some examples, the material of the active layer of the anti-leakage transistor T8includes an oxide semiconductor material. It should be noted that the transistor whose active layer is made of oxide semiconductor material has the characteristics of good hysteresis characteristics and low leakage current (below 1e-14A), and at the same time, its mobility is also low, which can realize low leakage current and ensure the voltage stability on the gate electrode of the driving transistor T1.

In some examples, the materials of the active layer of the first light emitting control transistor, the active layer of the second light emitting control transistor, the active layer of the compensation transistor, the active layer of the first initialization transistor, the active layer of the second initialization transistor, the active layer of the driving transistor, and the active layer of the data writing transistor include silicon-based semiconductor materials, such as low-temperature polysilicon (LTPS), which can have higher mobility and more stable source voltage. Therefore, the array substrate can make use of the characteristics of two transistors at the same time, thus achieving better display quality. In addition, because the array substrate provided in this example is provided with the anti-leakage transistor T8between the second node N2and the gate electrode of the driving transistor T1, only the anti-leakage transistor T8can be provided as a transistor whose active layer is an oxide semiconductor, so that the layout difficulty and manufacturing cost of the array substrate can be reduced.

In some examples, as illustrated byFIG.2andFIG.3, the array substrate100further includes a second gate line172, and the gate electrode of the anti-leakage transistor T8is connected with the second gate line172; the active layer of the anti-leakage transistor T8is located on a side of the second electrode plate CE2away from the base substrate110, and the first initialization line141and the second gate line142are arranged on the same layer, and are located on a side of the active layer of the anti-leakage transistor T8away from the base substrate110. Therefore, the second gate line172can be used to control the turn-on and turn-off of the anti-leakage transistor T8; and the first initialization line141is located on a side of the active layer of the anti-leakage transistor T8away from the base substrate110, so as to facilitate connection with the first power line151.

FIGS.4A-4Gare schematic diagrams of film layers of pixel driving circuits in an array substrate according to an embodiment of the present disclosure.

In some examples, as illustrated byFIG.4A, the array substrate100includes a base substrate110and a first semiconductor layer310on the base substrate110. The first semiconductor layer310includes an active layer of a driving transistor T1, an active layer of a data writing transistor T2, an active layer of a compensation transistor T3, an active layer of a first light emitting control transistor T4, an active layer of a second light emitting control transistor T5, an active layer of a first initialization transistor T7and an active layer of a second initialization transistor T6.

For example, the first semiconductor layer310can be made of low-temperature polycrystalline silicon (LTPS) material, so that the driving transistor T1, the data writing transistor T2, the compensation transistor T3, the first light emitting control transistor T4, the second light emitting control transistor T5, the first initialization transistor T7and the second initialization transistor T6have higher mobility and more stable source voltages.

For example, as illustrated byFIG.4B, the array substrate100includes a first gate layer320located on the side of the first semiconductor layer310away from the base substrate110; the first gate layer320includes a first reset signal line191, a second reset signal line192, a first electrode plate CE1, a gate line180and a first light emitting control line171. The first reset signal line191overlaps with the active layer of the first initialization transistor T7, and the part where the first reset signal line191overlaps with the first initialization transistor T7can be used as the gate electrode of the first initialization transistor T7; the second reset signal line192overlaps with the active layer of the second initialization transistor T6, and the part where the second reset signal line192overlaps with the second initialization transistor T6can be used as the gate electrode of the second initialization transistor T6; the gate line180overlaps with the active layer of the data writing transistor T2and the active layer of the compensation transistor T3, respectively, and the part of the gate line180overlapping with the active layer of the data writing transistor T2can be used as the gate electrode of the data writing transistor T2, and the part of the gate line180overlapping with the active layer of the compensation transistor T3can be used as the gate electrode of the compensation transistor T3. The first light emitting control line171overlaps with the active layer of the first light emitting control transistor T4and the active layer of the second light emitting control transistor T5, respectively, and the part where the first light emitting control line171overlaps with the active layer of the first light emitting control transistor T4can be used as the gate electrode of the first light emitting control transistor T4, the part where the first light emitting control line171overlaps with the active layer of the second light emitting control transistor T5can be used as the gate electrode of the second light emitting control transistor T5.

For example, as illustrated byFIG.4C, the array substrate100further includes a second gate layer330located on a side of the first gate layer320away from the base substrate110, and the second gate layer330includes a second gate line172and a second electrode plate CE2. An orthographic projection of the second electrode plate CE2on the base substrate110overlaps an orthographic projection of the first electrode plate CE1on the base substrate110to form the storage capacitor Cst.

For example, as illustrated byFIG.4D, the array substrate100further includes a second semiconductor layer340located on a side of the second gate layer330away from the base substrate110, and the second semiconductor layer340includes the active layer of the anti-leakage transistor T8. The second semiconductor layer340may be made of an oxide semiconductor material (for example, indium gallium zinc oxide (IGZO)), so that the anti-leakage transistor T8has a lower leakage current.

For example, as illustrated byFIG.4E, the array substrate100further includes a third gate layer350located on a side of the second semiconductor layer340away from the base substrate110; the third gate layer350includes a second gate line172and a first initialization signal line141. The second gate line172overlaps with the active layer of the anti-leakage transistor T8, and the overlapping part of the active layer of the anti-leakage transistor T8and the second gate line172can be used as the gate electrode of the anti-leakage transistor T8. Therefore, the anti-leakage transistor T8has a double-gate structure, which can further reduce the leakage current.

For example, as illustrated byFIG.4F, the array substrate100further includes a first conductive layer360located on a side of the third gate layer350away from the base substrate110; the first conductive layer360includes the second initialization signal line142, a first connection block361, a second connection block362, a third connection block363, a fourth connection block364, a fifth connection block365and a sixth connection block366.

As illustrated byFIGS.4E and4F, because the film layer where the first initialization signal line141is located is far away from the film layer where the active layer of the first initialization transistor T7is located, it is difficult to directly connect them through a via hole connection structure. In the array substrate provided in this example, the first initialization signal line141includes a first bent portion141A, and the first bent portion141A avoids the second electrode of the first initialization transistor T7, so that an orthographic projection of the first initialization signal line141on the base substrate110does not overlap with an orthographic projection of the second electrode of the first initialization transistor T7on the base substrate110. An orthographic projection of the first connection block361on the base substrate110overlaps with the orthographic projection of the first initialization signal line141and the orthographic projection of the second electrode of the first initialization transistor T7on the base substrate110, respectively, and the first connection block361electrically connects the first initialization signal line141with the second electrode of the first initialization transistor T7. Therefore, the via hole connection structure between the first connection block361and the first initialization signal line141only needs to be punched in one insulating layer, so the manufacturing difficulty is low and the process is easier to control. On the other hand, because of the avoidance of the first bent portion141A, the via hole connection structure between the first connection block361and the second electrode of the first initialization transistor T7has a large space, which can reduce the manufacturing difficulty and improve the yield. At this time, the first connection block361is located on a side of the first initialization signal line141away from the base substrate110.

As illustrated byFIG.4F, the second connection block362is configured connect with the first electrode of the first light emitting control transistor T4to serve as a relay connection electrode. Therefore, the anode131of the light emitting element130can be electrically connected to the first electrode of the first light emitting control transistor T4by being connected to the second connection block362, thus reducing the difficulty of directly connecting the anode131of the light emitting element130to the first electrode of the first light emitting control transistor T4.

As illustrated byFIG.4F, the third connection block363is configured to be connected with the second power line152, the second electrode plate CE2and the second electrode of the second light emitting control transistor T5, which are formed later, so that the second power line152can be electrically connected with the second electrode plate CE2and the second light emitting control transistor T5, respectively.

As illustrated byFIG.4F, the fourth connection block364is configured to be connected with the first electrode plate CE1and the first electrode of the anti-leakage transistor T8, respectively, so that the first electrode plate CE1and the first electrode of the anti-leakage transistor T8can be electrically connected.

As illustrated byFIG.4F, the fifth connection block365is configured to be connected with the second electrode of the anti-leakage transistor T8and the first electrode of the compensation transistor T3, respectively. The sixth connection block366is configured to be connected with the data line160and the second electrode of the data writing transistor T2, respectively.

For example, as illustrated byFIG.4G, the array substrate100further includes a second conductive layer370, which is located on a side of the first conductive layer360away from the base substrate110; the second conductive layer370includes the data line160and the second power line152.

In some examples, as illustrated byFIG.4A-FIG.4F, the first initialization signal line141is located between the first reset signal line191or the second reset signal line192and the second initialization signal line142in the direction perpendicular to the base substrate110.

FIG.5is a schematic plan view of an array substrate according to an embodiment of the present disclosure;FIG.6is a partial schematic diagram of an array substrate according to an embodiment of the present disclosure. As illustrated byFIG.5andFIG.6, the base substrate110includes a display region112and a peripheral region114around the display region112. The pixel driving circuit120and the light emitting element130are located in the display region112; a first power line151is located in the peripheral region114. The array substrate100further includes a first connection line161and a second connection line162located in the peripheral region. The first initialization line141extends from the display region112to the peripheral region114and is connected with the first connection line161. One end of the second connection line162is connected with the first power line151, and the other end of the second connection line162is connected with the first connection line161. Therefore, the array substrate can connect the first initialization line141with the first power line151through the first connection line161and the second connection line162. In addition, compared with directly connecting respectively first initialization lines141to the first power line151, the array substrate provided by this example can make the number of the second connection lines162between the first power line151and the first connection lines161less than the number of the first initialization signal lines141, thus reducing the number of wirings in the peripheral region.

For example, the first power line151is arranged around the display region112, so both ends of each first initialization line141can be electrically connected with the first power line151, so that the voltage drop of the first initialization line141can be further reduced, and the potentials of initialization signals reset to the anodes of different light emitting elements are the same, so that problems such as poor brightness uniformity and abnormal brightness jump can be avoided, and the display quality of the display device using the array substrate can be significantly alleviated.

In some examples, as illustrated byFIG.5andFIG.6, the first connection line161includes a first sub-connection portion161A extending along a second direction Y intersecting the first direction X; a second sub-connection portion161B extending in the second direction; and a third sub-connection portion161C extending along the first direction, one end of the third sub-connection portion161C being electrically connected with the first sub-connection portion161A, and the other end of the third sub-connection portion161C being electrically connected to the second sub-connection portion161B. The first sub-connection portion161A is located at a first side of the display region112in the first direction, the second sub-connection portion161B is located at a second side opposite to the first side of the display region112in the first direction, and the third sub-connection portion161C is located at a side of the display region112in the second direction, one end of the first initialization line141is electrically connected with the first sub-connection portion161A, and the other end of the first initialization line141is electrically connected with the second sub-connection portion161B. Therefore, the array substrate can reduce the voltage drop of the first initialization line141, so that the potentials of initialization signals reset to the anodes of different light emitting elements are the same, thus avoiding the problems of poor brightness uniformity, abnormal brightness jump and the like, and thus significantly improving the display quality of the display device using the array substrate.

FIG.7is a schematic plan view of another array substrate according to an embodiment of the present disclosure. As illustrated byFIG.7, a plurality of pixel driving circuits120may form a plurality of pixel driving rows210, each pixel driving row210includes multiple pixel driving circuits120arranged in a first direction X, the plurality of pixel driving rows210arranged in the second direction Y intersecting the first direction X, and a plurality of first initialization signal lines141are provided, the plurality of first initialization signal lines141are configured to apply first initialization signals to the plurality of pixel driving rows210. At this time, the array substrate100further includes at least one interconnection line230, which extends in the second direction and is connected to the plurality of first initialization signal lines141, respectively. Therefore, the interconnection line230can further reduce the voltage drop of the first initialization signal line141, and further make the potentials of initialization signals reset to the anodes of different light emitting elements the same, so that problems such as poor brightness uniformity and abnormal brightness jump can be avoided, and the display quality of the display device using the array substrate can be significantly improved.

For example, as illustrated byFIG.4D, the interconnection line230may be located in the second semiconductor layer340, that is, the interconnection line230may be arranged in the same layer as the active layer of the anti-leakage transistor T8.

In some examples, as illustrated byFIG.7, a plurality of pixel driving circuits120form a plurality of pixel driving columns240, each pixel driving column240includes multiple pixel driving circuits120arranged in a second direction, and the plurality of pixel driving columns240are arranged in a first direction. The array substrate100includes a plurality of interconnection lines230as mentioned above, and the plurality of interconnection lines230are arranged corresponding to the plurality of pixel driving columns240. Therefore, the array substrate can further reduce the voltage drop of the first initialization signal line141by correspondingly arranging one interconnection line230in each pixel driving column240.

In some examples, as illustrated byFIG.2, the array substrate100further includes a plurality of second power lines152, which are arranged corresponding to the plurality of pixel driving columns240; in an area corresponding to one pixel driving circuit120, an overlapping area of the orthographic projection of the second power line152on the base substrate110and the orthographic projection of the interconnection line230on the base substrate110is less than 50% of the area of the orthographic projection of the interconnection line230on the base substrate110, so that the capacitance between the interconnection line230and the power line152can be reduced and the load of the power line152can be reduced.

In some examples, as illustrated byFIG.2, the overlapping area of the orthographic projections of the second power line152and the interconnection line230on the base substrate110is less than 20% of the orthographic projection area of the interconnection line230on the base substrate110, so that the capacitance between the interconnection line230and the power line152can be further reduced and the load of the power line152can be reduced.

FIG.8is a schematic plan view of another array substrate according to an embodiment of the present disclosure. As illustrated byFIG.8, the base substrate110includes a display region112and a peripheral region114around the display region112. The pixel driving circuit120and the light emitting element130are located in the display region112, the first power line151is located in the peripheral region114, and the first initialization line141extends from the display region112to the peripheral region114and is directly connected to the first power line151.

FIG.9is a schematic plan view of another array substrate according to an embodiment of the present disclosure. As illustrated byFIG.9, a plurality of pixel driving circuits120may form a plurality of pixel driving rows210, each pixel driving row210includes multiple pixel driving circuits120arranged in a first direction X, the plurality of pixel driving rows210arranged in a second direction Y intersecting the first direction X, and a plurality of first initialization signal lines141are provided, the plurality of first initialization signal lines141configured to apply first initialization signals to the plurality of pixel driving rows210. At this time, the array substrate100further includes at least one interconnection line230, which extends in the second direction and is connected to the plurality of first initialization signal lines141, respectively. Therefore, the interconnection line230can further reduce the voltage drop of the first initialization signal line141, and further make the potentials of initialization signals reset to the anodes of different light emitting elements the same, so that problems such as poor brightness uniformity and abnormal brightness jump can be avoided, and the display quality of the display device using the array substrate can be significantly improved.

In some examples, as illustrated byFIG.9, a plurality of pixel driving circuits120form a plurality of pixel driving columns240, each pixel driving column240includes multiple pixel driving circuits120arranged in a second direction, and a plurality of pixel driving columns240are arranged in a first direction. The array substrate100includes a plurality of interconnection lines230described above, and the plurality of interconnection lines230are arranged corresponding to the plurality of pixel driving columns240. Therefore, the array substrate can further reduce the voltage drop of the first initialization signal line141by correspondingly arranging one interconnection line230in each pixel driving column240.

FIG.10is a schematic plan view of another array substrate provided by an embodiment of the present disclosure. As illustrated byFIG.10, the array substrate100includes an interconnection line230extending in a second direction; unlike the array substrate shown inFIG.2, the interconnection lines230are connected with a plurality of second initialization signal lines142, respectively. Therefore, the interconnection line230can further reduce the voltage drop of the second initialization signal line142, thereby significantly improving the display quality of the display device using the array substrate.

FIG.11is an equivalent schematic diagram of a pixel driving circuit in another array substrate according to an embodiment of the present disclosure. As illustrated byFIG.11, the first electrode plate CE1of the storage capacitor Cst and the gate electrode of the driving transistor T1are directly connected to the second node N2. Therefore, the first initialization transistor T6can directly initialize the gate electrode of the driving transistor T1and the first electrode plate CE1of the storage capacitor Cst through the second node N2.

At least one embodiment of the present disclosure also provides a display device.FIG.12is a schematic diagram of a display device provided by an embodiment of the present disclosure. As illustrated byFIG.12, the display device500includes the array substrate100as mentioned above. As the array substrate can reduce the voltage difference between the anode and cathode of the light emitting element when initializing the anode of the light emitting element, the charge on the anode of the light emitting element can be quickly released, and the light emitting element can be turned off completely, so that the problems of stroboscopic and uneven brightness in low gray scale can be alleviated, and the contrast can be improved. In addition, the first initialization signal and the second initialization signal of the array substrate can be transmitted by different initialization signal lines, thereby reducing the load on a single initialization signal line, reducing the voltage drop on a single initialization signal line, and further improving the brightness uniformity. Therefore, the display device can also improve the problem of stroboscopic and uneven brightness in low gray scale, and can improve the contrast and brightness uniformity.

For example, in some examples, the display device can be any product or component with display function, such as a smart phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

The following points need to be explained:(1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.(2) The features of the same embodiment and different embodiments of the present disclosure can be combined with each other without conflict.

The above are only the specific embodiments of this disclosure, but the scope of protection of the present disclosure is not limited thereto. Any skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be covered by the scope of protection of this disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.