Patent ID: 12199126

DESCRIPTION OF EMBODIMENTS

First Embodiment

FIG.1is a block diagram illustrating a configuration of an image-capturing apparatus1according to a first embodiment. The image-capturing apparatus1includes a photographing optical system2, an image sensor3, and a control unit4. The image-capturing apparatus1is, for example, a camera. The photographing optical system2forms a subject image on the image sensor3. The image sensor3captures the subject image formed by the photographing optical system2and generates an image signal. The image sensor3is, for example, a CMOS image sensor. The control unit4outputs, to the image sensor3, a control signal for controlling the operation of the image sensor3. Additionally, the control unit4performs various types of image processing on the image signal output from the image sensor3and functions as an image generation unit generating image data. Note that the photographing optical system2may be detachable from the image-capturing apparatus1.

FIG.2is a circuit diagram illustrating a configuration of a pixel10according to the first embodiment. The image sensor3has a plurality of pixels10arranged two-dimensionally. The pixel10has a photoelectric conversion unit12, such as a photodiode (PD), and a readout unit20. The photoelectric conversion unit12has a function of converting incident light into an electric charge and accumulating the photoelectrically converted electric charge. The readout unit20includes a transfer unit13, a discharge unit14, a floating diffusion (FD)15, an amplification unit16, and a selection unit17.

The transfer unit13is controlled by a signal Vtx to transfer the electric charge photoelectrically converted by the photoelectric conversion unit12to the floating diffusion15. In other words, the transfer unit13forms an electric charge transfer path between the photoelectric conversion unit12and the floating diffusion15. The floating diffusion15holds (accumulates) the electric charge. The amplification unit16amplifies a signal caused by the electric charge held in the floating diffusion15to output the signal to a vertical signal line30via the selection unit17. In the example illustrated inFIG.2, the amplification unit16includes a transistor M3having a drain terminal, a gate terminal, and a source terminal, which are respectively connected to a power supply VDD, the floating diffusion15, and the selection unit17. The source terminal of the amplification unit16is connected to the vertical signal line30via the selection unit17. The amplification unit16functions as a part of a source follower circuit with an electric current source60(described later) as a load electric current source.

The discharge unit (reset unit)14is controlled by a signal Vrst to discharge the electric charge of the floating diffusion15and reset a potential of the floating diffusion15to a reset potential (reference potential). The selection unit17is controlled by a signal Vsel to output the signal from the amplification unit16to the vertical signal line30. For example, the transfer unit13, the discharge unit14, and the selection unit17respectively include a transistor M1, a transistor M2, and a transistor M4.

The readout unit20reads out, to the vertical signal line30, a signal (a photoelectric conversion signal) corresponding to the electric charge transferred by the transfer unit13from the photoelectric conversion unit12to the floating diffusion15and a signal (a noise signal) at a time of resetting the potential of the floating diffusion15to the reset potential. The noise signal is a reference signal indicating a reference level for the photoelectric conversion signal. Furthermore, the amplification unit16and the selection unit17constitute an output unit that outputs a signal caused by the electric charge accumulated in the floating diffusion15. The output unit outputs the photoelectric conversion signal and the noise signal to the vertical signal line30.

FIG.3is a circuit diagram illustrating a configuration of a part of the image sensor3according to the first embodiment. The image sensor3includes a plurality of pixels10arranged in a matrix, a vertical scanning circuit40, a selection circuit50, electric current sources60(electric current sources60a-60d), first switch units70(first switch units70a-70d), second switch units80(second switch units80a-80d), accumulation units90(accumulation units90a-90d), a horizontal scanning circuit100, and an output amplifier unit110.FIG.3illustrates a circuit diagram having the accumulation units90juxtaposed with the pixels10, for ease of comprehension; however, practically, the accumulation units90are arranged to be stacked on a semiconductor substrate in a pixel region where the pixels10are densely arranged in a matrix. The pixel region is a region where the plurality of pixels10each having the photoelectric conversion unit12and the readout unit20are arranged two-dimensionally. In other words, in the pixel region, a plurality of pixels10are arranged in a first direction (e.g., column direction) and a second direction (e.g., row direction) intersecting the first direction. Outside the pixel region, peripheral circuits (the vertical scanning circuit40, the horizontal scanning circuit100, etc.) are arranged.

InFIG.3, an accumulation unit90ais provided at a pixel region where a first pixel column at the leftmost is arranged, and an accumulation unit90bis provided at a pixel region where a second pixel column, which is adjacent to the first pixel column on the right, is arranged. Similarly, an accumulation unit90cand an accumulation unit90dare respectively provided to correspond to a third pixel column and a fourth pixel column, which is adjacent to the third column on the right. In the present embodiment, the accumulation units90are provided to be stacked on the semiconductor substrate at the pixel regions. The accumulation units90are juxtaposed with the pixels10in a direction in which the accumulation units90are stacked on the semiconductor substrate. This achieves a large capacitance value without increasing a chip area.

An accumulation unit90, an electric current source60, a first switch unit70, and a second switch unit80are provided for each pixel column including a plurality of pixels10arranged in the column direction, that is, in the vertical direction. In other words, inFIG.3, one accumulation unit90, one electric current source60, one first switch unit70, and one second switch unit80are provided corresponding to the first pixel column at the leftmost. Similarly, another accumulation unit90, another electric current source60, another first switch unit70, and another second switch unit80are provided corresponding to each of the second pixel column adjacent to the first pixel column on the right, the third pixel column adjacent to the second pixel column on the right, and the fourth pixel column adjacent to the third pixel column on the right.

Furthermore, a vertical signal line30(respectively, vertical signal lines30a-30d) is provided corresponding to each column of the pixels10. Note that the example inFIG.3illustrates only four pixels10in the horizontal direction and four pixels10in the vertical direction, for simplification of explanation.

The electric current sources60a-60dare provided respectively corresponding to the vertical signal lines30a-30dand connected to the vertical signal lines30a-30d. Additionally, the electric current sources60a-60dare connected to respective pixels10via the vertical signal lines30a-30d, respectively. The electric current sources60a-60dgenerate electric currents for reading out photoelectric conversion signals and noise signals from the respective pixels10. The electric current sources60a-60drespectively supply generated electric currents to the vertical signal lines30a-30dand the respective pixels10.

The vertical scanning circuit40supplies control signals such as a signal Vtxn, a signal Vrstn, and a signal Vseln to each pixel10. The vertical scanning circuit40outputs a signal Vtxn and other signals to a pixel10to control the operation of the pixel10. Note that the “n” at the end of “Vtxn”, “Vrstn”, “Vseln” indicates a row number of a pixel. For example, a signal Vtx1is a signal for controlling transfer units13of pixels10in a first row.

The first switch units70a-70dare provided respectively corresponding to the vertical signal lines30a-30dand connected to the vertical signal lines30a-30d. The first switch units70a-70drespectively switch electrical connection states between the vertical signal lines30a-30dand the accumulation units90a-90d. The first switch units70a-70dare controlled by control signals output from the selection circuit50to transfer the photoelectric conversion signals and the noise signals output from the pixels10to the accumulation units90a-90d, respectively. Each of the first switch units70a-70dhas a switch TN1, a switch TS1, a switch TN2, and a switch TS2. The switch TN1, the switch TS1, the switch TN2, and the switch TS2each include a transistor.

The second switch units80a-80dare provided respectively corresponding to the vertical signal lines30a-30d. The second switch units80a-80drespectively switch electrical connection states between the accumulation units90a-90dand the output amplifier unit110. The second switch units80a-80dare controlled by control signals output from the horizontal scanning circuit100to transfer the photoelectric conversion signals and the noise signals accumulated in the accumulation units90a-90dto the output amplifier unit110via a horizontal signal line S and a horizontal signal line N. Each of the second switch units80a-80dhas a switch PH1N, a switch PH1S, a switch PH2N, and a switch PH2S. The switch PH1N, the switch PH1S, the switch PH2N, and the switch PH2S each include a transistor.

The selection circuit50supplies control signals such as a signal Vtn1, a signal Vts1, a signal Vtn2, and a signal Vts2to the first switch units70a-70d. The selection circuit50outputs control signals to control the operations of the first switch units70a-70d.

The horizontal scanning circuit100supplies control signals such as a signal Vph11, a signal Vph12, a signal Vph21, a signal Vph22, a signal Vph31, a signal Vph32, a signal Vph41, and a signal Vph42to the second switch units80a-80d. The horizontal scanning circuit100outputs control signals to control the operations of the second switch units80a-80d.

The accumulation units90a-90dare provided corresponding to columns of the pixels10to accumulate (store) the photoelectric conversion signals and the noise signals output from the pixels10. The accumulation units90a-90dhave capacitances for accumulating the photoelectric conversion signals and the noise signals. The capacitance is, for example, a capacitance formed by conductors, such as a capacitance formed by adjacent metals. Specifically, such capacitance is, for example, a capacitance formed between a conductor to which a photoelectric conversion signal or a noise signal is input and a conductor to which a predetermined potential is applied. Note that specific configuration examples of the accumulation units90a-90dwill be described later in detail with reference toFIG.5andFIG.6.

In the example illustrated inFIG.3, each of the accumulation units90a-90dhas conductors CN1and CN2to which noise signals are input, and conductors CS1and CS2to which photoelectric conversion signals are input. Additionally, each of the accumulation units90a-90dhas a fixed potential line120as a conductor to which the above-described predetermined potential is applied. Note that inFIG.3, the fixed potential line120is indicated by a dotted line to distinguish it from the conductor CN1, the conductor CS1, the conductor CN2, and the conductor CS2.

For example, a power supply potential or a ground potential is supplied to the fixed potential terminal illustrated inFIG.3, and the power supply potential or the ground potential is applied to the fixed potential line120. Reference symbol C representing a plurality of capacitances illustrated inFIG.3schematically indicate that capacitances are respectively formed between the conductor CN1and the fixed potential line120, between the conductor CS1and the fixed potential line120, between the conductor CN2and the fixed potential line120, and between the conductor CS2and the fixed potential line120. In the present embodiment, the conductors CN1and CN2function as noise accumulation units for accumulating the noise signals, and the conductors CS1and CS2function as signal accumulation units for accumulating the photoelectric conversion signals.

The output amplifier unit110outputs a signal based on a difference between the noise signal input via the horizontal signal line N and the photoelectric conversion signal input via the horizontal signal line S, to an output terminal illustrated inFIG.3. For example, the output amplifier unit110outputs a signal obtained by amplifying the difference between the noise signal and the photoelectric conversion signal by a predetermined gain.

FIG.4is a timing chart illustrating an operation example of the image sensor3according to the first embodiment. InFIG.4, the vertical axis represents voltage levels of the control signals and the horizontal axis represents time. In the timing chart illustrated inFIG.4, a transistor to which a control signal is inputted is turned on when a control signal is at high level (e.g., at a power supply potential), and a transistor to which a control signal is input is turned off when a control signal is at low level (e.g., at a ground potential). A period from time t1to time t10, a period from time t10to time t22, a period from time t22to time t34, a period from time t34to time t46, and a period from time t46to time t50each represent one horizontal period. Note that the electric charge accumulated in the photoelectric conversion unit12is reset in synchronization with the discharge of the electric charge of the floating diffusion15, that is, the reset of the floating diffusion15; however, description of the reset of the photoelectric conversion unit12is omitted in the following description, for simplification of explanation.

At time t1, the signal Vsel1becomes high to turn on the transistor M4of the selection unit17in each pixel10in the first row. At time t2, the signal Vrst1becomes high to turn on the transistor M2of the discharge unit14in each pixel10in the first row. As a result, the potential of the floating diffusion15becomes the reset potential. Additionally, the noise signals of the pixels10in the first row are output to the corresponding vertical signal lines30a-30dby the amplification units16and the selection units17. At time t3, the signal Vrst1becomes low to turn off the transistor M2. At time t4, the signal Vtn1becomes high to turn on the switch TN1of each of the first switch units70a-70d. As a result, the noise signals from the pixels10are transferred to the conductors CN1of the corresponding accumulation units90a-90d. The capacitances given (or added) to the conductors CN1of the accumulation units90a-90daccumulate the noise signals from the respective pixels10in the first row. At time t5, the signal Vtn1becomes low to turn off the switch TN1. When the switch TN1is turned off, the capacitances given to the conductors CN1hold (accumulate) the noise signals.

At time t6, the signal Vtx1becomes high to turn on the transistor M1of the transfer unit13in each pixel10in the first row. This allows the electric charge photoelectrically converted by the photoelectric conversion unit12to be transferred to the floating diffusion15. Additionally, the photoelectric conversion signals of the pixels10in the first row are output to the corresponding vertical signal lines30a-30dby the amplification units16and the selection units17. At time t7, the signal Vtx1becomes low to turn off the transistor M1. At time t8, the signal Vts1becomes high to turn on the switch TS1of each of the first switch units70a-70d. This allows the photoelectric conversion signals to be transferred to the conductors CS1of the accumulation units90a-90d. The capacitances given to the conductors CS1accumulate the photoelectric conversion signals from the respective pixels10in the first row. At time t9, the signal Vts1becomes low to turn off the switch TS1. When the switch TS1is turned off, the capacitances given to the conductors CS1hold the photoelectric conversion signals.

At time t10, signals Vph11and Vsel2becomes high. The signal Vph11becomes high to turn on the switches PH1N and PH1S of the second switch unit80a. As a result, the signals from the pixels10in the first row accumulated in the accumulation unit90acorresponding to the first column of the pixels10are output to the horizontal signal line S and the horizontal signal line N. In other words, the photoelectric conversion signal accumulated in the conductor CS1of the accumulation unit90ais output to the horizontal signal line S, and the noise signal accumulated in the conductor CN1of the accumulation unit90ais output to the horizontal signal line N. The output amplifier unit110outputs a signal based on a difference between the noise signal and the photoelectric conversion signal.

Additionally, at time t10, the signal Vsel2becomes high to turn on the transistor M4of each pixel10in the second row. At time t11, the signal Vrst2becomes high to turn on the transistor M2and reset the floating diffusion15. Additionally, the noise signal of each pixel10in the second row is output to each of the vertical signal lines30a-30d. At time t12, the signal Vrst2becomes low to turn off the transistor M2. At time t13, the signal Vtn2becomes high to turn on the switch TN2. As a result, the noise signals are transferred to the conductors CN2of the corresponding accumulation units90a-90d. The capacitances given to the conductors CN2accumulate the noise signals from the respective pixels10in the second row.

At time t14, the signal Vph11becomes low and the signal Vph21becomes high. The signal Vph11becomes low to turn off the switch PH1N and the switch PH1S of the second switch unit80a. The signal Vph21becomes high to turn on the switches PH1N and PH1S of the second switch unit80b. As a result, the photoelectric conversion signal from the pixel10in the first row accumulated in the accumulation unit90bcorresponding to the second column of the pixels10is output to the horizontal signal line S, and the noise signal is output to the horizontal signal line N. The output amplifier unit110outputs a signal based on a difference between the noise signal and the photoelectric conversion signal.

At time t15, the signal Vtn2becomes low to turn off the switch TN2. When the switch TN2is turned off, the capacitances given to the conductors CN2hold the noise signals.

At time t16, the signal Vph21becomes low and the signal Vph31becomes high. The signal Vph21becomes low to turn off the switch PH1N and the switch PH1S of the second switch unit80b. The signal Vph31becomes high to turn on the switches PH1N and PH1S of the second switch unit80c. As a result, the photoelectric conversion signal from the pixel10in the first row accumulated in the accumulation unit90ccorresponding to the third column of the pixels10is output to the horizontal signal line S, and the noise signal is output to the horizontal signal line N. The output amplifier unit110outputs a signal based on a difference between the noise signal and the photoelectric conversion signal.

At time t17, the signal Vtx2becomes high to turn on the transistor M1in each pixel10in the second row. This allows the electric charge photoelectrically converted by the photoelectric conversion unit12to be transferred to the floating diffusion15. Additionally, the photoelectric conversion signals of the pixels10in the second row are output to the corresponding vertical signal lines30a-30d. At time t18, the signal Vtx2becomes low to turn off the transistor M1. At time t19, the signal Vts2becomes high to turn on the switch TS2of each of the first switch units70a-70d. This allows the photoelectric conversion signals to be transferred to the conductors CS2of the accumulation units90a-90d. The capacitances given to the conductors CS2accumulate the photoelectric conversion signals from the respective pixels10in the second row.

At time t20, the signal Vph31becomes low and the signal Vph41becomes high. The signal Vph31becomes low to turn off the switch PH1N and the switch PH1S of the second switch unit80c. The signal Vph41becomes high to turn on the switch PH1N and the switch PH1S of the second switch unit80d. As a result, the photoelectric conversion signal from the pixel10in the first row accumulated in the accumulation unit90dcorresponding to the fourth column of the pixels10is output to the horizontal signal line S, and the noise signal is output to the horizontal signal line N. The output amplifier unit110outputs a signal based on a difference between the noise signal and the photoelectric conversion signal.

At time t21, the signal Vts2becomes low to turn off the switch TS2. When the switch TS2is turned off, the capacitances given to the conductors CS2hold the photoelectric conversion signals.

As described above, in a period from time t10to time t22, a horizontal transfer is performed in which the signals are read out from the pixels10in the second row to the accumulation units90, while the signals from the pixels10in the first row accumulated in the accumulation units90are output to the horizontal signal line S and the horizontal signal line N.

At time t22, the signal Vph41becomes low, and the signal Vph12and the signal Vsel2becomes high. The signal Vph41becomes low to turn off the switch PH1N and the switch PH1S of the second switch unit80d. The signal Vph12becomes high to turn on the switch PH2N and the switch PH2S of the second switch unit80a. As a result, the signals from the pixels10in the second row accumulated in the accumulation unit90acorresponding to the first column of the pixels10are output to the horizontal signal line S and the horizontal signal line N. In other words, the photoelectric conversion signal accumulated in the conductor CS2of the accumulation unit90ais output to the horizontal signal line S, and the noise signal accumulated in the conductor CN2of the accumulation unit90ais output to the horizontal signal line N. The output amplifier unit110outputs a signal based on a difference between the noise signal and the photoelectric conversion signal.

At time t22, the signal Vsel3becomes high to turn on the transistor M4in each pixel10in the third row. At time t23, the signal Vrst3becomes high to turn on the transistor M2and reset the floating diffusion15. Additionally, the noise signals of the pixels10in the third row are output to the corresponding vertical signal lines30a-30d. At time t24, the signal Vrst3becomes low to turn off the transistor M2. At time t25, the signal Vtn1becomes high to turn on the switch TN1. As a result, the noise signals are transferred to the conductors CN1of the corresponding accumulation units90a-90d. The capacitances given to the conductors CN1accumulate the noise signals from the respective pixels10in the third row.

At time t26, the signal Vph12becomes low and the signal Vph22becomes high. The signal Vph12becomes low to turn off the switch PH2N and the switch PH2S of the second switch unit80a. The signal Vph22becomes high to turn on the switch PH2N and the switch PH2S of the second switch unit80b. As a result, the photoelectric conversion signal from the pixel10in the second row accumulated in the accumulation unit90bcorresponding to the second column of the pixels10is output to the horizontal signal line S, and the noise signal is output to the horizontal signal line N. The output amplifier unit110outputs a signal based on a difference between the noise signal and the photoelectric conversion signal.

At time t27, the signal Vtn1becomes low to turn off the switch TN1. When the switch TN1is turned off, the capacitances given to the conductors CN1hold the noise signals.

At time t28, the signal Vph22becomes low and the signal Vph32becomes high. The signal Vph22becomes low to turn off the switch PH2N and the switch PH2S of the second switch unit80b. The signal Vph32becomes high to turn on the switch PH2N and the switch PH2S of the second switch unit80c. As a result, the photoelectric conversion signal from the pixel10in the second row accumulated in the accumulation unit90ccorresponding to the third column of the pixels10is output to the horizontal signal line S, and the noise signal is output to the horizontal signal line N. The output amplifier unit110outputs a signal based on a difference between the noise signal and the photoelectric conversion signal.

At time t29, the signal Vtx3becomes high to turn on the transistor M1in each pixel10in the third row. This allows the electric charge photoelectrically converted by the photoelectric conversion unit12to be transferred to the floating diffusion15. Additionally, the photoelectric conversion signals of the pixels10in the third row are output to the corresponding vertical signal lines30a-30d. At time t30, the signal Vtx3becomes low to turn off the transistor M1. At time t31, the signal Vts1becomes high to turn on the switch TS1of each of the first switch units70a-70d. This allows the photoelectric conversion signals to be transferred to the conductors CS1of the accumulation units90a-90d. The capacitances given to the conductors CS1accumulate the photoelectric conversion signals from the respective pixels10in the third row.

At time t32, the signal Vph32becomes low and the signal Vph42becomes high. The signal Vph32becomes low to turn off the switch PH2N and the switch PH2S of the second switch unit80c. The signal Vph42becomes high to turn on the switch PH2N and the switch PH2S of the second switch unit80d. As a result, the photoelectric conversion signal from the pixel10in the second row accumulated in the accumulation unit90dcorresponding to the fourth column of the pixels10is output to the horizontal signal line S, and the noise signal is output to the horizontal signal line N. The output amplifier unit110outputs a signal based on a difference between the noise signal and the photoelectric conversion signal.

At time t33, the signal Vts1becomes low to turn off the switch TS1. When the switch TS1is turned off, the capacitances given to the conductors CS1hold the photoelectric conversion signals.

In a period from time t34to time t46, the transistors controlled by the signals Vsel4, Vrst4, Vtn2, Vtx4, Vts2are sequentially turned on and off in the same manner as in the period from time t10to time22and the period from time t22to time34. As a result, the noise signals from the pixels10in the fourth row are accumulated in the capacitances given to the conductors CN2, and the photoelectric conversion signals from the pixels10in the fourth row are accumulated in the capacitances given to the conductors CS2. Furthermore, in a period from time t34to time t46, the transistors controlled by the signals Vph11, Vph21, Vph31, Vph41are sequentially turned on and off. As a result, the noise signals and the photoelectric conversion signals from the pixels10in the third row accumulated in the respective accumulation units90a-90dare sequentially output. The output amplifier unit110sequentially outputs signals based on differences between the noise signals and the photoelectric conversion signals output from the accumulation units90a-90d.

In a period from time t46to time t50, the transistors controlled by the signals Vph12, Vph22, Vph32, Vph42are sequentially turned on and off. As a result, the noise signals and the photoelectric conversion signals from the pixels10in the fourth row accumulated in the respective accumulation units90a-90dare sequentially output. The output amplifier unit110sequentially outputs signals based on differences between the noise signals and the photoelectric conversion signals output from the accumulation units90a-90d.

As described above, in the present embodiment, while signals are read out from pixels10in a row to the accumulation units90, a horizontal transfer is performed in which signals from pixels10in another row accumulated in the accumulation units90are output to the horizontal signal line S and the horizontal signal line N. The readout time from all the pixels10can be reduced by performing the horizontal transfer operation in parallel during the readout period from the pixel10. Reducing the readout time can achieve a readout at a high frame rate.

FIG.5is a view illustrating an example of a cross-sectional structure of the image sensor3according to the first embodiment.FIG.5is a cross-sectional view taken along a line A-A′ inFIG.6(described later). The image sensor3is, for example, a back side illumination type image sensor. As illustrated inFIG.5, incident light is mainly incident in the Z-axis plus direction. Further, as illustrated in the coordinate axes, the leftward direction of the paper sheet orthogonal to the Z-axis is the X-axis plus direction, and the depth direction of the paper sheet orthogonal to the Z-axis and the X-axis is the Y-axis plus direction. In some subsequent figures, coordinate axes are illustrated so that the orientation of each figure can be understood with reference to the coordinate axes ofFIG.5.

The image sensor3is configured to include a semiconductor substrate200made of a semiconductor material such as silicon and a wiring layer210stacked on the semiconductor substrate200. The image sensor3further has a microlens layer, a color filter layer, and a passivation layer, which are not illustrated. In the image sensor3, the microlens layer, the color filter layer, the passivation layer, the semiconductor substrate200, and the wiring layer210are arranged in this order in the Z-axis plus direction, for example.

The semiconductor substrate200has a first surface201a, and a second surface201bthat is different from the first surface201a. The first surface201ais to be an incident surface on which light is incident. The second surface201bis opposite to the first surface201a. In the present embodiment, a “back side” of the image sensor3represents the first surface201alocated on a side opposite to the wiring layer210, and the “back side illumination type” is a configuration in which light is incident from the first surface201a, which is the back side. The wiring layer210has a surface (a third surface203a) on the second surface201bside of the semiconductor substrate200and a surface (a fourth surface203b) opposite to the third surface203a.

The semiconductor substrate200has the photoelectric conversion unit12and the readout unit20between the first surface201aand the second surface201b. A plurality of pixels10each having the photoelectric conversion unit12and the readout unit20are arranged in the X-axis direction and the Y-axis direction. The photoelectric conversion unit12converts incident light into an electric charge, the incident light being incident from one side of the semiconductor substrate200, that is, from the first surface201aside of the semiconductor substrate200. The accumulation unit90is provided to be stacked on the photoelectric conversion unit12on a side opposite to the one side of the semiconductor substrate200, that is, on the second surface201bside of the semiconductor substrate200. In other words, the accumulation unit90is provided between the photoelectric conversion unit12and the fourth surface203bof the wiring layer210.

On the second surface201bof the semiconductor substrate200, a multilayer wiring layer210including conductor films (metal films) and insulating films is formed. The wiring layer210has a plurality of wirings, vias, and the like arranged therein. The conductor films are made of copper, aluminum, or the like. The insulating films include an insulating film between the conductor films, a gate insulating film, and the like, and is made of an oxide film, a nitride film, and the like.

The wiring layer210has a signal wiring layer211provided with signal lines for control signals Vtxn, Vrstn, Vseln, or the like input to each pixel10and the vertical signal lines30, and an accumulation unit wiring layer212constituting the accumulation units90(accumulation units90a-90d). The signal wiring layer211is stacked on the second surface201bof the semiconductor substrate200, and the accumulation unit wiring layer212is stacked on the signal wiring layer211a.

In the accumulation unit wiring layer212, the accumulation unit90acorresponding to the first pixel column is stacked via the signal wiring layer211in a pixel region in which the first pixel column is located, the accumulation unit90bcorresponding to the second pixel column is stacked via the signal wiring layer211in a pixel region in which the second pixel column is located, the accumulation unit90ccorresponding to the third pixel column is stacked via the signal wiring layer211, the accumulation unit90dcorresponding to the fourth pixel column is stacked via the signal wiring layer211, and so forth, as illustrated inFIG.3andFIG.5. In this way, each of the accumulation units90a-90dof the accumulation unit wiring layer212is provided in each pixel region220for each corresponding pixel column. The size of each of the accumulation units90a-90dof the accumulation unit wiring layer212corresponds to the size of one column of the pixels10. The accumulation units90a-90dof the accumulation unit wiring layer212have the same configuration, and the accumulation unit90illustrated inFIG.5thus corresponds to any one of the accumulation units90a-90d.

As described above, the accumulation unit90has the conductor CN1, the conductor CS1, the conductor CN2, the conductor CS2, and the fixed potential line120. As illustrated inFIG.5, for example, the fixed potential line120has a first fixed potential line120a, a second fixed potential line120b, and a third fixed potential line120c, which are formed by conductor films in different layers. The first fixed potential line120aand the third fixed potential line120care arranged apart from each other in the Z-axis direction, which is the stacking direction of the wiring layer210. The first fixed potential line120aand the third fixed potential line120care common to all the accumulation units90a,90b,90c,90d, and accordingly are formed so as to cover all the pixels10of the image sensor3. The first fixed potential line120aand the third fixed potential line120cmay be common to all the accumulation units as described above, or may be configured for each accumulation unit.

The conductors CN1, CS1, CN2, and CS2extend in a direction in which a plurality of pixels10constituting each pixel column are arranged. The conductors CN1, CS1, CN2, CS2are arranged away from the first fixed potential line120aand the third fixed potential line120cbetween the first fixed potential line120aand the third fixed potential line120c. The second fixed potential line120bis arranged between the conductors CN1, CS1, CN2, CS2, and is connected to the first fixed potential line120aand the third fixed potential line120cthrough vias. Insulating films are provided between the conductors CN1, CS1, CN2, CS2and the first to third fixed potential lines120a-120c. The insulating films may be oxide films or nitride films. Specifically, the insulating films are silicon oxide films, silicon nitride films, silicon oxynitride films, or multilayer films composed of these films.

In the accumulation unit90, capacitances are formed between each of the conductors CN1, CS1, CN2, CS2and the first to third fixed potential lines120a-120c. The capacitance can be increased by reducing distances between each of the conductors CN1, CS1, CN2, CS2and the first to third fixed potential lines120a-120c. A high dielectric constant material having a dielectric constant higher than that of a silicon oxide film or the like may be used in order to increase the capacitance. MIM capacitors may also be used. Note that capacitances are also given to conductors CN1, CS1, CN2, CS2, which are formed between the conductors CN1, CS1, CN2, CS2and wirings or the like different from the fixed potential lines.

A predetermined potential such as the power supply potential or the ground potential is applied to the first fixed potential line120a, the second fixed potential line120b, and the third fixed potential line120c. The first fixed potential line120afunctions as a shield between the vertical signal lines30, the control signal lines, or the like of the signal wiring layer211and the conductors CN1, CS1, CN2, CS2. Providing the first fixed potential line120acan reduce formation of a large parasitic capacitance between the vertical signal lines30, the control signal lines, or the like and the conductors CN1, CS1, CN2, CS2. Additionally, crosstalks between the vertical signal lines30, the control signal lines, or the like and the conductors CN1, CS1, CN2, CS2can be reduced. Furthermore, the first fixed potential line120a, the second fixed potential line120b, and the third fixed potential line120care provided so as to surround four sides of each of the conductors CN1, CS1, CN2, CS2to function as shields between the conductors CN1, CS1, CN2, CS2. The formation of a large parasitic capacitance between the conductors CN1, CS1, CN2, CS2may be avoided and crosstalks between the conductors CN1, CS1, CN2, CS2may be reduced.

In the example illustrated inFIG.5, the first fixed potential line120ais set to the ground potential, and is connected to the semiconductor substrate200through a via202and the like. In other words, the first fixed potential line120ais commonly connected to each pixel10as a ground line for supplying the ground potential to each pixel10. Note that a power supply potential may be applied to the first fixed potential line120ato use it as a power supply line common to the pixels10. Thus, the fixed potential lines are shared by: conductors for forming the capacitances formed by the conductors CN1, CS1, CN2, CS2; a shield for reducing noise contamination; and power supply lines or ground lines of the pixels10. Using the fixed potential lines as the power supply line or the ground line for each pixel10eliminates the need for separately providing any wiring for the power supply line or the ground line. Therefore, the number of wiring layers210can be reduced.

FIG.6is a view illustrating a planar layout example of a part of the accumulation unit wiring layer212of the image sensor3according to the first embodiment.FIG.6(a)is a view illustrating an example of a planar layout of a layer in which the third fixed potential line120cis formed,FIG.6(b)is a view illustrating an example of a planar layout of a layer in which the second fixed potential line120band the conductors CN1, CS1, CN2, CS2are formed, andFIG.6(c)is a view illustrating an example of a planar layout of a layer in which the first fixed potential line120ais formed.

As described above, the third fixed potential line120cand the first fixed potential line120aare formed in planar shapes as illustrated inFIG.6. The third fixed potential line120cand the first fixed potential line120aare formed to cover all the pixels10arranged two-dimensionally in a matrix, for example. The second fixed potential line120b, the conductor CN1, the conductor CS1, the conductor CN2, and the conductor CS2are each linearly formed. The second fixed potential line120bis arranged facing to the conductors CN1, CS1, CN2, CS2. The length of the second fixed potential line120bin the Y-axis direction is a length corresponding to the lengths of the conductors CN1, CS1, CN2, CS2in the Y-axis direction. In the present embodiment, since the accumulation units90a-90dare provided corresponding to the pixel rows of the pixels10, the lengths in the Y-axis direction of the second fixed potential line120band the conductors CN1, CS1, CN2, CS2correspond to the length of one pixel column. The third fixed potential line120cand the second fixed potential line120bare connected through a plurality of vias, and the second fixed potential line120band the first fixed potential line120aare connected through a plurality of vias.

According to the above-described embodiment, the following operations and effects can be obtained.

(1) An image sensor3includes: a plurality of pixels10each having a photoelectric conversion unit12that converts incident light into an electric charge, the incident light being incident from one side of a substrate200, and an output unit (an amplification unit16and a selection unit17) that outputs a signal caused by the electric charge, the plurality of pixels10being arranged in a first direction and a second direction intersecting the first direction; and an accumulation unit90provided to be stacked on the photoelectric conversion unit12on a side opposite to one side of the substrate200, the accumulation unit90accumulating the signal. In the present embodiment, the accumulation unit90is provided to be stacked on the second surface200bof the semiconductor substrate200in the pixel region220. In the prior art, a large number of capacitances are provided in a region around the pixel region220where an analog/digital conversion circuit and the like are disposed. This leads to an increase in the chip area of the image sensor. In contrast, in the present embodiment, the accumulation unit90is provided to be stacked on the second surface201bof the semiconductor substrate200. Thus, an increase in the chip area can be reduced. Additionally, providing the accumulation unit90in the pixel region220can avoid an increase in the area of the region around the pixel region220where the analog/digital conversion circuit and the like are disposed. Furthermore, a large capacitance can be formed by providing capacitances corresponding to one pixel column, for example.

(2) An image sensor3includes a photoelectric conversion unit12that converts light incident on a first surface201aof a semiconductor substrate200into an electric charge; a readout unit20that outputs a signal caused by the electric charge to a second surface201bof the semiconductor substrate200; and an accumulation unit90that accumulates the signal output by the readout unit20, the accumulation unit90being provided to be stacked on the pixel region220of the second surface201b. In this way, an increase in the chip area can be reduced.

(3) The accumulation unit90is commonly connected to the plurality of pixels10arranged in the first direction. In this way, capacitances can be provided corresponding to one pixel column, for example.

(4) The image sensor3further includes a signal line (a vertical signal line30) which is commonly connected to the plurality of pixels10arranged in the first direction and to which a signal is output by the readout unit20. The accumulation unit90is commonly connected to the plurality of pixels10via the signal line. In this way, the signal from each pixel10read out via the vertical signal line30can be accumulated in the accumulation unit90.

(5) The readout unit20outputs a signal caused by the electric charge, and a noise signal. The accumulation unit90includes a signal accumulation unit that accumulates the signal caused by the electric charge and a noise accumulation unit that accumulates the noise signal. In this way, the photoelectric conversion signal and the noise signal output from the readout unit20can be separately accumulated in the accumulation unit90.

(6) The image sensor includes a first wiring (a second fixed potential line120b) which is provided between the signal accumulation unit and the noise accumulation unit and to which a constant potential (for example, a power supply potential or a ground potential) is applied; a second wiring (a first fixed potential line120a) which is provided between the readout unit20and the accumulation unit90and to which a constant potential is applied; and a third wiring (a third fixed potential line120c) which is provided on a side opposite to the side on which light is incident, via the accumulation unit90and the insulating film and to which a constant potential is applied. In the present embodiment, the first fixed potential line120a, the second fixed potential line120b, and the third fixed potential line120care provided so as to surround four sides of each of the conductors CN1, CS1, CN2, CS2. Thus, a noise contamination can be reduced.

(7) The accumulation unit90includes a first accumulation unit (for example, an accumulation unit90a) connected to a first plurality of pixels10arranged in the first direction, and a second accumulation unit (for example, an accumulation unit90b) connected to a second plurality of pixels arranged in the first direction, the second plurality of pixels being different from the first plurality of pixels10. A plurality of the first accumulation units and the second accumulation units are arranged side by side in a second direction. In this way, an accumulation unit can be provided for each pixel column, for example, to obtain a large capacitance.

(8) The readout unit90includes: the holding unit15that holds the electric charge converted by the photoelectric conversion unit12; the transfer unit13that transfers the electric charge to the holding unit15; the discharge unit14that discharges the electric charge held in the holding unit15; and an amplification unit16that amplifies the signal caused by the electric charge transferred by the transfer unit13. In this way, the photoelectric conversion signal based on the electric charge photoelectrically converted by the photoelectric conversion unit12can be read out from each pixel10.

(9) The noise signal is a signal when the electric charge held in the holding unit15has been discharged. In this way, a noise signal serving as a reference level for the photoelectric conversion signal can be obtained.

(10) An image sensor3includes: a first layer (a semiconductor substrate200) having a photoelectric conversion unit12that converts light incident on a first surface201aof a semiconductor substrate200into an electric charge, and a readout unit20that outputs a signal caused by the electric charge to a second surface201bof the semiconductor substrate200; and a second layer (an accumulation wiring layer212) having an accumulation unit90that accumulates the signal output by the readout unit20. In this way, a large capacitance value can be obtained without increasing the chip area.

(11) The accumulation unit90has a capacitance caused by a conductor. In this way, an increase in the chip area can be reduced as compared with a case where a diffusion capacitance is provided.

(12) An image sensor3includes a plurality of pixels10having a photoelectric conversion unit12that converts incident light to an electric charge, a first accumulation unit (a floating diffusion15) to which the electric charge photoelectrically converted by the photoelectric conversion unit12is transferred, and an output unit (an amplification unit16and a selection unit17) that outputs a signal caused by the electric charge transferred to the first accumulation unit; an output control unit (a vertical scanning circuit40) that switches a pixel signal (a photoelectric conversion signal) caused by the electric charge transferred from the photoelectric conversion unit12to the first accumulation unit and a reset signal (a noise signal) in which the electric charge in the first accumulation unit is reset, to output the pixel signal or the noise signal from the output unit; a second accumulation unit (a signal accumulation unit) that accumulates the pixel signal output from the output unit; and a third accumulation unit (a noise accumulation unit) that accumulates the reset signal output from the output unit. The pixel10is arranged between the surface on which light is incident and the second accumulation unit or the third accumulation unit. In this way, an increase in the chip area can be reduced. Additionally, a large capacitance value can be obtained without increasing the chip area.

Second Embodiment

An image-capturing apparatus according to a second embodiment has the same configuration as that of the image-capturing apparatus1according to the first embodiment. The image sensor according to the second embodiment is different from the first embodiment mainly in that a plurality of vertical signal lines are provided for each pixel column to simultaneously read out pixels10in a plurality of rows. Note that parts similar to or equivalent to that in the first embodiment are denoted by the same reference numbers in the figures, and differences between the first and second embodiments will mainly be described.

FIG.7is a circuit diagram illustrating a configuration of a part of an image sensor3according to the second embodiment. In the second embodiment, two vertical signal lines (vertical signal lines30A and30B) are provided corresponding to each column of the pixels10. The pixels10in each column are connected to different vertical signal lines for each row. In the second embodiment, the image sensor3includes selection circuits50(selection circuits50A and50B), electric current sources60(electric current sources60A1-60A3, electric current sources60B1-60B3), first switch units70(first switch units70A1-70A3, first switch units70B1-70B3), second switch units80(second switch units80A1-80A3, second switch units80B1-80B3), accumulation units90(accumulation units90A1-90A3, accumulation units90B1-90B3), horizontal scanning circuits100(horizontal scanning circuits100A and100B), and output amplifier units110(output amplifier units110A and110B). Note that the example inFIG.7illustrates only three pixels10in the horizontal direction and four pixels10in the vertical direction, for simplification of explanation.

FIG.8is a timing chart illustrating an operation example of the image sensor3according to the second embodiment. InFIG.8, a period from time t1to time t10, a period from time t10to time t22, and a period from time t22to time t26each represent one horizontal period.

At time t1, the signals Vsel1and Vsel2become high to turn on the transistor M4of the selection unit17in each pixel10in the first and second rows. At time t2, the signals Vrst1and Vrst2become high to turn on the transistor M2of the discharge unit14in each pixel10in the first and second rows, and the potential of the floating diffusion15becomes the reset potential. Additionally, the noise signals of the pixels10in the first row are output to the corresponding vertical signal lines30B1-30B3and the noise signals of the pixels10in the second row are output to the corresponding vertical signal lines30A1-30A3.

At time t3, the signals Vrst1and Vrst2become low to turn off the transistor M2. At time t4, the signal Vtn1becomes high to turn on the switch TN1of each of the first switch units70A1-70A3and the first switch units70B1-70B3. As a result, the noise signals from the pixels10in the first row are transferred to the conductors CN1of the corresponding accumulation units90B1-90B3, and the noise signals from the pixels10in the second row are transferred to conductors CN1A of the corresponding accumulation units90A1-90A3. At time t5, the signal Vtn1becomes low to turn off the switch TN1. When the switch TN1is turned off, capacitances given to conductors CN1B of the accumulation units90B1-90B3hold the noise signals from the respective pixels10in the first row. Additionally, capacitances given to the conductors CN1A of the accumulation units90A1-90A3hold the noise signals from the respective pixels10in the second row.

At time t6, the signal Vtx1the signal Vtx2become high to turn on the transistor M1of the transfer unit13in each pixel10in the first and second row, and the electric charge photoelectrically converted by the photoelectric conversion unit12is transferred to the floating diffusion15. Additionally, the photoelectric conversion signals of the pixels10in the first row are output to the corresponding vertical signal lines30B1-30B3, and the photoelectric conversion signals of the pixels10in the second row are output to the corresponding vertical signal lines30A1-30A3. At time t7, the signals Vtx1and Vtx2become low to turn off the transistor M1.

At time t8, the signal Vts1becomes high to turn on the switches TS1of the first switch units70A1-70A3and the first switch units70B1-70B3. This allows the photoelectric conversion signals from the pixels10in the first row to be transferred to the conductors CS1B of the accumulation units90B1-90B3and allows the photoelectric conversion signals from the pixels10in the second row to be transferred to the conductors CS1A of the accumulation units90A1-90A3. At time t9, the signal Vts1becomes low to turn off the switch TS1. When the switch TS1is turned off, the capacitances given to the conductors CS1B of the accumulation units90B1-90B3hold the photoelectric conversion signals from the respective pixels10in the first row. Additionally, the capacitances given to the conductors CS1A of the accumulation units90A1-90A3hold the photoelectric conversion signals from the respective pixels10in the second row.

As described above, in a period from time t1to time t10, the signals of the pixels10in the first row are read out to the accumulation units90B1-90B3, and the signals of the pixels10in the second row are read out to the accumulation unit90A1-90A3.

In a period from time t10to time t22, the transistors controlled by the signals Vsel3, Vsel4, Vrst3, Vrst4, Vtn2, Vtx3, Vtx4, Vts2are sequentially turned on and off in the same manner as in the period from time t1to time10. This allows the capacitances given to the conductors CN2B and CS2B of the accumulation units90B1-90B3to accumulate the noise signals and the photoelectric conversion signals from the respective pixels10in the third row. This also allows the capacitances given to the conductors CN2A and CS2A of the accumulation units90A1-90A3to accumulate the noise signals and the photoelectric conversion signals from the respective pixels10in the fourth row. Thus, in the present embodiment, the conductors CN1A, CN2A, CN1B, and CN2B function as noise accumulation units for accumulating the noise signals. Additionally, the conductors CS1A, CS2A, CS1B, and CS2B function as signal accumulation units for accumulating the photoelectric conversion signals.

Furthermore, at time t10, the signal Vph11becomes high to turn on the switches PH1N and PH1S of the second switch units80A1and80B1. As a result, the signals from the pixels10in the first row accumulated in the accumulation unit90B1are output to the horizontal signal line BS and the horizontal signal line BN. Furthermore, the signals from the pixels10in the second row accumulated in the accumulation unit90A1are output to the horizontal signal line AS and the horizontal signal line AN. Each of the output amplifier unit110A and the output amplifier unit110B outputs a signal based on a difference between the noise signal and the photoelectric conversion signal.

At time t14, the signal Vph21becomes high to turn on the switches PH1N and PH1S of the second switch units80A2and80B2. As a result, the signals from the pixels10in the first row accumulated in the accumulation unit90B2are horizontally transferred, and the signals from the pixels10in the second row accumulated in the accumulation unit90A2are horizontally transferred. At time t16, the signal Vph31becomes high to turn on the switches PH1N and PH1S of the second switch units80A3and80B3. As a result, the signals from the pixels10in the first row accumulated in the accumulation unit90B3are horizontally transferred, and the signals from the pixels10in the second row accumulated in the accumulation unit90A3are horizontally transferred.

In a period from time t22to time t25, the transistors controlled by the signals Vph12, Vph22, Vph32are sequentially turned on and off. As a result, the noise signals and the photoelectric conversion signals from the pixels10in the third row accumulated in the respective accumulation units90B1-90B3are sequentially output. Furthermore, the noise signals and the photoelectric conversion signals from the pixels10in the fourth row accumulated in the respective accumulation units90A1-90A3are sequentially output. The output amplifier units110A and110B sequentially output signals based on differences between the noise signals and the photoelectric conversion signals.

FIG.9is a view illustrating an example of a cross-sectional structure of the image sensor3according to the second embodiment.FIG.9is a cross-sectional view taken along a line A-A′ inFIG.10(described later). The wiring layer210is provided with an accumulation unit wiring layer212A having accumulation units90A (accumulation units90A1-90A3) and an accumulation unit wiring layer212B having accumulation units90B (accumulation units90B1-90B3). The accumulation unit wiring layer212B is provided to be stacked on the accumulation unit wiring layer212A in the pixel region220of the second surface201bof the semiconductor substrate200. Additionally, the size of each of the accumulation units90A and90B corresponds to the size of one column of the pixels10.

As illustrated inFIG.9, the fixed potential line120has a first fixed potential line120a, a second fixed potential line120b, a third fixed potential line120c, a fourth fixed potential line120d, and a fifth fixed potential line120e, which are formed by conductor films in different layers. In the accumulation unit wiring layer212A, capacitances are formed mainly between each of the conductors CN1A, CS1A, CN2A, CS2A and the first to third fixed potential lines120a-120c. Furthermore, in the accumulation unit wiring layer212B, capacitances are formed mainly between each of the conductors CN1B, CS1B, CN2B, CS2B and the third to fifth fixed potential lines120c-120e. The third fixed potential line120cfunctions as a shield between the conductors CN1A, CS1A, CN2A, CS2A of the accumulation unit90A and the conductors CN1B, CS1B, CN2B, CS2B of the accumulation unit90B.

FIG.10is a view illustrating a planar layout example of a part of the accumulation unit wiring layer212of the image sensor3according to the second embodiment.FIG.10(a)is a view illustrating an example of a planar layout of a layer in which the fifth fixed potential line120eis formed,FIG.10(b)is a view illustrating an example of a planar layout of a layer in which the fourth fixed potential line120dand the conductors CN1B, CS1B, CN2B, CS2B are formed, andFIG.10(c)is a view illustrating an example of a planar layout of a layer in which the third fixed potential line120cis formed. Furthermore,FIG.10(d)is a view illustrating an example of a planar layout of a layer in which the second fixed potential line120band the conductors CN1A, CS1A, CN2A, CS2A are formed, andFIG.10(e)is a view illustrating an example of a planar layout of a layer in which the first fixed potential line120ais formed.

The fifth fixed potential line120eis formed to cover all the pixels10arranged two-dimensionally in a matrix, for example, in the same manner as the third fixed potential line120cand the first fixed potential line120a. The fourth fixed potential line120dis linearly formed in the same manner as the second fixed potential line120b. In the present embodiment, since the accumulation units90A and90B are provided corresponding to the pixel rows of the pixels10, the lengths in the Y-axis direction of the fourth fixed potential line120dand the conductors CN1B, CS1B, CN2B, CS2B correspond to the length of one pixel column. The fifth fixed potential line120eand the fourth fixed potential line120dare connected to each other through a plurality of vias, the fourth fixed potential line120dand the third fixed potential line120care connected to each other through a plurality of vias.

According to the above-described embodiment, the following operations and effects can be obtained in addition to the same operations and effects as those in the first embodiment.

(13) The accumulation unit90includes a first accumulation unit90A connected to a first plurality of pixels10among the plurality of pixels10arranged in the first direction and a second accumulation unit90B connected to a second plurality of pixels10among the plurality of pixels10arranged in the first direction. In the present embodiment, the image sensor3further includes a third layer (an accumulation unit wiring layer212B) stacked on the second layer (the accumulation unit wiring layer212A). In this way, an increase in the chip area can be reduced while a plurality of accumulation units90can be provided. Additionally, providing a plurality of accumulation units90for each pixel column can achieve a simultaneous readout of pixels10in a plurality of rows.

Third Embodiment

An image-capturing apparatus according to a third embodiment has the same configuration as that of the image-capturing apparatus1according to the first embodiment. The image sensor according to the third embodiment is different from the image sensor in the second embodiment mainly in that the accumulation unit90A and the accumulation unit90B are separately arranged without being stacked. Note that parts similar to or equivalent to that in the first embodiment are denoted by the same reference numbers in the figures, and differences between the first and second embodiments will mainly be described.

FIG.11is a circuit diagram illustrating a configuration of a part of the image sensor3according to the third embodiment. The image sensor according to the third embodiment has the same circuit configuration as that of the image sensor3according to the second embodiment. In the second embodiment, an example is illustrated in which each of the accumulation unit90A and the accumulation unit90B is provided to have a size corresponding to one column of pixels10. In contrast, in the third embodiment, each of the accumulation unit90A and the accumulation unit90B is provided to have a size corresponding to a predetermined number of pixels10among pixels10in one column. For example, the size of each of the accumulation units90A and90B corresponds to the size of a half column of the pixels10. Note that the operation of the image sensor3according to the third embodiment is the same as that of the image sensor3according to the second embodiment.

FIG.12is a view illustrating an example of a cross-sectional structure of the image sensor3according to the third embodiment.FIG.12(a)is a cross-sectional view taken along a line A-A′ inFIG.13(described later) andFIG.12(b)is a cross-sectional view taken along a line B-B′ inFIG.13(described later). The accumulation unit wiring layer212of the wiring layer210is provided with the accumulation units90A (accumulation units90A1-90A4) and the accumulation units90B (accumulation units90B1-90B4). A cross-sectional view inFIG.12(a)illustrates an accumulation unit90B. Furthermore, as illustrated inFIG.12(b), the conductor film and the insulating film of the same layer are used to form the accumulation unit90A and the accumulation unit90B.

FIG.13is a view illustrating a planar layout example of a part of the accumulation unit wiring layer210of the image sensor3according to the third embodiment.FIG.13(a)is a view illustrating an example of a planar layout of a layer in which the third fixed potential line120cis formed,FIG.13(b)is a view illustrating an example of a planar layout of a layer in which the second fixed potential line120band the conductors CN1A, CS1A, CN2A, CS2A, CN1B, CS1B, CN2B, CS2B are formed, andFIG.13(c)is a view illustrating an example of a planar layout of a layer in which the first fixed potential line120ais formed.

The second fixed potential line120bis arranged between the conductors CN1A, CS1A, CN2A, CS2A of the accumulation unit90A. Furthermore, the second fixed potential line120bis arranged between the conductors CN1B, CS1B, CN2B, CS2B of the accumulation unit90B. In the present embodiment, since the size of each of the accumulation units90A and90B corresponds to a size of a predetermined number of pixels10among the pixels in one pixel column, the lengths in the Y-axis direction of the conductors CN1A, CS1A, CN2A, CS2A and the conductors CN1B, CS1B, CN2B, CS2B correspond to the lengths of the predetermined number of pixels10in one pixel column. Furthermore, the second fixed potential line120bfunctions as a shield between the conductors CN1A, CS1A, CN2A, CS2A of the accumulation unit90A and the conductors CN1B, CS1B, CN2B, CS2B of the accumulation unit90B.

According to the above-described embodiment, the following operations and effects can be obtained in addition to the same operations and effects as those in the first embodiment.

(14) The accumulation unit90includes a first accumulation unit90A connected to a first plurality of pixels10among the plurality of pixels10arranged in the first direction and a second accumulation unit90B connected to a second plurality of pixels10among the plurality of pixels10arranged in the first direction. In the present embodiment, each of the plurality of accumulation units90corresponds to an individual one of the plurality of pixel columns and stores signals read out from the pixels10of the corresponding pixel column. The plurality of accumulation units90are provided in the pixel region200including a predetermined number of pixels in the corresponding pixel column. In this way, the plurality of accumulation units90can be arranged without stacking them. Therefore, the number of wiring layers210can be reduced.

The following modifications are also included in the scope of the present invention, and one or more of the modifications may be combined with the above-described embodiments.

First Modification

FIG.14is a circuit diagram illustrating a configuration of a part of an image sensor3according to a first modification. The image sensor3according to the first modification is provided with amplifiers (buffers)130connected to respective vertical signal lines30. The amplifier130(amplifiers130a-130d) outputs a signal obtained by amplifying a signal read out from a pixel10. This can reduce a signal delay and a reduction in a signal level between each pixel10and each accumulation unit90. As a result, a readout at a high frame rate can also be performed when the capacitance of the accumulation unit90is large, for example.

Additionally, the image sensor3according to the first modification is provided with two analog/digital conversion circuits (the AD conversion circuit140A and the AD conversion circuit140B) for each pixel column. The AD conversion circuit140A and the AD conversion circuit140B each output a digital signal based on a difference between a photoelectric conversion signal and a noise signal from the corresponding pixel column. The digital signal output from the AD conversion circuit140A and the digital signal output from the AD conversion circuit140B are averaged. The digital signal output from the AD conversion circuit140A1and the digital signal output from the AD conversion circuit140B1are averaged, and the digital signal output from the AD conversion circuit140A2and the digital signal output from the AD conversion circuit140B2are averaged. Similarly, the digital signal output from the AD conversion circuit140A3and the digital signal output from the AD conversion circuit140B3are averaged, and the digital signal output from the AD conversion circuit140A4and the digital signal output from the AD conversion circuit140B4are averaged. The averaged signal is output to an output terminal illustrated inFIG.14. In the present modification, each of the AD conversion circuits140A and140B converts a signal from the pixels10accumulated in the accumulation unit90into a digital signal to average two digital signals. Therefore, a signal having a reduced noise contamination during a transfer of a signal from the accumulation unit90to the second switch unit80can be output to the output terminal.

Second Modification

In the above-described embodiment, an example has been described in which capacitances caused by conductors are provided as capacitances for accumulating a photoelectric conversion signal and a noise signal. However, capacitances made of materials other than conductors may be provided to be stacked on the second surface201bof the semiconductor substrate.

Third Modification

In the above-described embodiment, an example has been described in which the signal wiring layer211is stacked on the second surface201bof the semiconductor substrate200, and the accumulation unit wiring layer212is stacked on the signal wiring layer211. However, the accumulation unit wiring layer212may be stacked on the second surface201bof the semiconductor substrate200, and the signal wiring layer211may be stacked on the accumulation unit wiring layer212. Additionally, the accumulation unit wiring layer212may be stacked on the second surface201bof the semiconductor substrate200via a conductor film or an insulating film, or directly.

Fourth Modification

In the above-described embodiment, an example has been described in which the image sensor3has a back illuminated configuration. However, the image sensor3may have a front side illumination type configuration in which the wiring layer210is provided on a light incident surface on which light is incident. In this case, the image sensor3has a configuration in which light is incident on the second surface201bof the semiconductor substrate200. A plurality of pixels10are arranged in a first direction (e.g., column direction) and a second direction (e.g., row direction) intersecting the first direction. The accumulation units90may be arranged between a plurality of pixels, for example, between a plurality of pixels arranged in the second direction.

Fifth Modification

In the above embodiments and modifications, the accumulation units90that accumulate photoelectric conversion signals and noise signals from the pixels10have been described. However, the accumulation units may also be applied as accumulation units of another circuit included in the image sensor3.

Although various embodiments and variations have been described above, the present invention is not limited to these. Other aspects contemplated within the technical idea of the present invention are also included within the scope of the present invention.

The disclosure of the following priority application is herein incorporated by reference:

Japanese Patent Application No. 2016-38161 (filed Feb. 29, 2016)

REFERENCE SIGNS LIST

3. . . image sensor,12. . . photoelectric conversion unit,20. . . readout unit,90. . . accumulation unit,200. . . semiconductor substrate