Patent ID: 12199409

MODES FOR CARRYING OUT THE INVENTION

Embodiment 1

FIG.1AtoFIG.4are provided for illustrating an optical semiconductor device and a method of manufacturing the optical semiconductor device, according to Embodiment 1.FIG.1AtoFIG.1Cshow sectional views for illustrating the configuration of the optical semiconductor device, in whichFIG.1Ais a sectional view parallel to a light traveling direction and a stacking direction, at a ridge stripe portion (corresponding to a line A inFIG.1B);FIG.1Bis a sectional view of the optical semiconductor device perpendicular to the light traveling direction, at a portion in the light traveling direction near an end face (corresponding to a line B-B inFIG.1A); andFIG.1Cis a sectional view of the optical semiconductor device perpendicular to the light traveling direction, at a portion in the light traveling direction where a λ/4 phase shifter of the semiconductor device is formed (corresponding to a line C-C inFIG.1A). Further,FIG.2AtoFIG.2Fare sectional views perpendicular to the light traveling direction (corresponding toFIG.1B) in respective steps in the method of manufacturing the optical semiconductor device by using stacking, after the time when a ridge stripe is formed on an n-type substrate.

Further,FIG.3is a characteristic diagram as a comparative example conventional optical for illustrating characteristics of a semiconductor device, in which a light intensity distribution in an active layer, a p-cladding resistance distribution and a carrier density distribution, each in the light traveling direction and at the time of laser oscillation, are shown individually, together with a sectional perspective view corresponding toFIG.1A. On the other hand,FIG.4is a characteristic diagram for illustrating characteristics of the optical semiconductor device according to Embodiment 1, in which a light intensity distribution in an active layer, a p-cladding resistance distribution, a carrier density distribution and a distribution of opening width of the current narrowing window for controlling the p-cladding resistance distribution, each in the light traveling direction and at the time of laser oscillation, are shown individually, together with a sectional perspective view corresponding toFIG.1A. Note that when description is made about the conventional optical semiconductor device, with respect to its component that is equivalent to a component of the optical semiconductor device according to this embodiment, a symbol “C” is affixed to the end of the numeral to be given thereto, to thereby make a distinction between these components.

Hereinafter, description will be made about an optical semiconductor device and a method of manufacturing the optical semiconductor device, according to Embodiment 1 in this application, with reference to the drawings. As shown inFIG.1A, an optical semiconductor device100is configured so that a stack of semiconductor layers that extends along a light traveling direction Dr is sandwiched by electrodes10. As shown inFIG.1BandFIG.1C, on the lowermost face of the semiconductor layers, an n-type InP substrate1having (001) plane as a principal plane is placed. On this substrate, an n-type cladding layer2, an active layer3including a multiple quantum well, and a 0.1 μm-thick p-type first cladding layer4made of InP, are stacked in this order, to thereby constitute a ridge stripe5that is also referred to as an active layer ridge.

In the n-type InP substrate1, S (Sulfur) is doped in a concentration of 4.0×1018cm−3, and in the n-type cladding layer2, S is doped in a concentration of 4.0×1018cm−3. The active layer3is formed of an AlGaInAs-based or InGaAsP-based material, and in the p-type first cladding layer4, Zn (Zinc) is doped in a concentration of 1.0×1018cm−3.

Further, in the n-type cladding layer2, a diffraction grating6made of an InGaAsP-based material and having a thickness of 40 nm, a width of 100 nm and a period of about 200 nm is embedded, and as shown inFIG.1A, a λ/4 phase shifter6qis formed in a central portion in the light traveling direction Dr of the diffraction grating6. Note that the diffraction grating6may be embedded in the p-type first cladding layer4not in the n-type cladding layer2, and the λ/4 phase shifter6qis not limited to being placed in the central portion and may be placed at any given position in the light traveling direction Dr.

The ridge stripe5is formed by etching the semiconductor layers stacked as described above, up to a position lower than the active layer3, while leaving their central portion in the width direction (a direction perpendicular to the stacking direction and the light traveling direction Dr) unremoved. Accordingly, the cross-section of the n-type InP substrate1perpendicular to the light traveling direction Dr forms an inverted-T shape. Note that although a width W5of the ridge stripe5is generally about from 0.8 to 1.4 μm, it is not limited to in this range. The respective lateral sides of the ridge stripe5are buried up to a position higher than the active layer3, by first burying layers7each made of InP that is doped with Fe as a semi-insulative material in a concentration of 5.0×1016cm−3. The material of the first burying layer7is not limited to the above, and may be another semi-insulative material, such as InP that is doped with another material of Ti, Co, Ru or the like.

Further, the first burying layer7may be configured as a combination of different semiconductor layers which are different in impurity concentration or conductivity type. On the first burying layers7, a 0.4 μm-thick n-type second burying layer8made of InP that is doped with S in a concentration of 7.0×1018cm−3, is formed, and end portions in the n-type second burying layer8that are directed to the width-direction center thereof are protruding onto the upper face of the ridge stripe5. The n-type second burying layer8and the ridge stripe5are buried under a p-type second cladding layer9made of InP that is doped with Zn in a concentration of 2.0×1018cm−3. Furthermore, on the lower side of the n-type InP substrate1and on the upper side of the p-type second cladding layer9, electrodes10each made of a metal, such as Au, Ge, Zn, Pt, Ti or the like, are formed.

On a width-direction central portion of the uppermost part (top part) of the ridge stripe5having the active layer3, the n-type second burying layer8is open widthwise to thereby form a current narrowing window8athat extends in the light traveling direction Dr, and the p-type first cladding layer4and the p-type second cladding layer9are in contact with each other through the current narrowing window8a.An opening width Wa of the current narrowing window8ais basically set to 0.7 μm, but is adjusted to vary along the light traveling direction Dr. Specifically, the current narrowing window8ais configured so that its opening width Waq on a region where the λ/4 phase shifter6qis placed, that is shown inFIG.1C, is larger than the opening width Wa on another region, that is shown inFIG.1B, and becomes maximum. Note that the basic opening width Wa of the current narrowing window8ais generally about from 0.5 to 1.0 μm; however, it is not limited to in this range so far as it is narrower than the width of the ridge stripe5(precisely, the p-type first cladding layer4).

In the optical semiconductor device100according to Embodiment 1, a front-end face100feand a rear-end face100feformed by cleavage, constitute a resonator. Emitted light obtained in the active layer3, due to injection of a current, is amplified in the resonator resulting in laser oscillation. Although the length of the resonator is set to from 150 μm to 300 μm in many cases, it is not limited to in this range.

Next, one exemplary method of manufacturing the optical semiconductor device100according to Embodiment 1 will be described usingFIG.2. First, as shown inFIG.2A, the n-type cladding layer2having the diffraction grating6embedded therein, the active layer3and the p-type first cladding layer4are stacked on the n-type InP substrate1. Thereafter, a first mask24is formed which has a distribution of width Wm that is matched with the distribution of opening width Wa of the current narrowing window8aalong the light traveling direction, and then a second mask25is formed with a width that is same as the width W5of the ridge stripe5so as to cover the above mask. The first mask24uses a material whose etching rate is lower than that of the second mask25. Further, the width Wm of the first mask24is narrower than the width W5of the second mask25, and it is desired that the first mask24be placed centrally with respect to the second mask25. Using such a double mask comprised of the first mask24and the second mask, etching is performed up to the position lower than the active layer3, to thereby form the ridge stripe5.

Then, as shown inFIG.2B, both sides of the ridge stripe5are buried by the first burying layers7up to the position higher than the active layer3. Thereafter, as shown inFIG.2C, the second mask25is subjected to selective etching. For example, in the case where the material of the first mask24is SiO2and the material of the second mask25is SiN, when SF6is used as an etching gas, it is possible to etch only the second mask25selectively by making use of the difference between their etching rates.

Then, as shown inFIG.2D, the n-type second burying layer8is grown so as to bury the first burying layers7and the ridge stripe5. Subsequently, after removing the first mask24by using buffered hydrofluoric acid or hydrofluoric acid as shown inFIG.2E, the p-type second cladding layer9is grown so as to cover the first cladding layer4and the n-type second burying layer8as shown inFIG.2F. Lastly, the electrodes10are formed on the lower side of the n-type InP substrate1and the upper side of the p-type second cladding layer9, so that the optical semiconductor device100shown inFIG.1is configured.

When a current is injected into the thus-configured optical semiconductor device100through the upper and lower electrodes10, electrons and holes are supplied, respectively, from the n-type InP substrate1and the n-type cladding layer2and from the p-type first cladding layer4and the p-type second cladding layer9. The holes supplied from the p-type second cladding layer9flow out toward the n-type substrate1. The holes are blocked by a potential barrier placed at the interface between the p-type second cladding layer9and the n-type second burying layer8, and injected into the active layer3while passing the p-type first cladding layer4through the current narrowing window8a. A resistance R of such a current-flow path is generally represented by a formula (1) under the assumption that the electrical resistivity is ρ, the sectional area of the path is S and the length of the path is L.
R=ρ(L/S). . .   (1)

The opening width Waq of the current narrowing window8anear the center thereof in the light traveling direction Dr around which the λ/4 phase shifter6qis placed, is larger than the opening width Wa at another region such as a region near the end face, or the like, resulting in a larger sectional area S. Accordingly, the resistance R becomes lower as represented by the formula (1), and this facilitates the injection of current.

In order to explain the characteristics of the optical semiconductor device100according to Embodiment 1 while taking the above-described configuration into consideration, the characteristics of an optical semiconductor device100C having a conventional structure will be firstly described by usingFIG.3. In the light intensity distribution at the time laser oscillation in a usual single mode is established for the optical semiconductor device100C, the intensity is strongest at the region where a λ/4 phase shifter6qC is placed, and becomes weaker as the position becomes farther from the placement position of the λ/4 phase shifter6qC. Thus, at the region in a light traveling direction DrC where the λ/4 phase shifter6qC is placed and light density is high, stimulated emission is likely to occur as compared with the other region, so that the carrier density is relatively decreased.

It is herein noted that, in the conventional optical semiconductor device100C, an opening width WaC of its current narrowing window8aC is constant regardless of the position in the light traveling direction DrC, so that the p-cladding resistance distribution is uniform. Thus, holes are injected almost uniformly regardless of the position in the light traveling direction DrC, so that the carrier density around the placement position of the λ/4 phase shifter6qC becomes lower, causing a phenomenon referred to as “longitudinal hole burning”. This causes variation in refractive index in the light traveling direction DrC, so that the single mode operation becomes unstable.

On the other hand, even in the case of the optical semiconductor device100according to Embodiment 1, in the light intensity distribution at the time laser oscillation in a usual single mode is established, the intensity is strongest at the region where the λ/4 phase shifter6qis placed, and becomes weaker as the position becomes farther from the placement position of the λ/4 phase shifter6q.Thus, at the region in the light traveling direction Dr where the λ/4 phase shifter6qis placed and light density is high, stimulated emission is likely to occur as compared with the other region, so that the carrier density is relatively decreased.

In that regard, in the optical semiconductor device100according to Embodiment 1, the opening width Wa of the current narrowing window8ais varied along the light traveling direction Dr so that, at the region where the λ/4 phase shifter6qis placed, the opening width Waq becomes largest as shown in the lowermost figure. Accordingly, the p-cladding resistance varies along the light traveling direction Dr so that it shows a minimum value at the region where the λ/4 phase shifter6qis placed. Therefore, at the region in the light traveling direction Dr where the λ/4 phase shifter6qis placed, holes are injected in a largest amount, so that the carrier density distribution along the positions in the light traveling direction Dr can be made uniform. Accordingly, the longitudinal hole burning is suppressed, thus making possible a stable single-mode operation.

It is noted that, with respect to the current narrowing window8ain the optical semiconductor device100according to Embodiment 1, the opening width Wa is adjusted by dimensional designing (shape control) using usual semiconductor lithography for an element, to thereby cause the resistance to vary. According to the shape control, unlike material control, it is possible to easily realize highly-accurate manufacturing, so that, as shown inFIG.4, it is possible to control the opening width Wa in a stepless manner along the light traveling direction Dr so as to make compensation for the distribution of light intensity. In this case, the opening width Waq at the region where the λ/4 phase shifter6qis placed, is preferable to be in a range about from 1.2 to 2.4 times relative to a narrowest width Wce near the end face100fe.

However, the distribution of the opening width Wa is not necessarily fitted completely to a curve that compensates the light intensity distribution. For example, if the opening width Wa is varied stepwise between the region where the λ/4 phase shifter6qis placed and a region other than that, it is possible, at the region where the λ/4 phase shifter6qis placed, to reduce stimulated emission that is otherwise excessive in comparison to the other region. Namely, it suffices to adjust the opening width Wa of the current narrowing window8aso that the p-cladding resistance is varied to the extent that the longitudinal hole burning is suppressed. With the application of such shape control, complex operational control is also not required at the time of operating the optical semiconductor device after completion.

Embodiment 2

In Embodiment 1, a case has been shown where, in order to adjust the distribution of p-cladding resistance in the light traveling direction, the width of the current narrowing window is varied depending on the position in the light traveling direction. In Embodiment 2, a case will be described where a layer thickness at a current-narrowing window portion is varied depending on the position in the light traveling direction, to thereby adjust the distribution of p-cladding resistance in the light traveling direction.

FIG.5andFIG.6are provided for illustrating an optical semiconductor device and a method of manufacturing the optical semiconductor device, according to Embodiment 2, andFIG.5shows sectional views for illustrating the configuration of the optical semiconductor device, in whichFIG.5Ais a sectional view of the optical semiconductor device perpendicular to the light traveling direction, at a portion in the light traveling direction near an end face (corresponding to the line B-B inFIG.1A); andFIG.5Bis a sectional view of the optical semiconductor device perpendicular to the light traveling direction, at a portion in the light traveling direction where a λ/4 phase shifter of the semiconductor device is formed (corresponding to the line C-C inFIG.1A). Further,FIG.6AtoFIG.6D, FIG.6E1and FIG.6E2are sectional views perpendicular to the light traveling direction (corresponding toFIG.5A,FIG.5B) in respective steps in the method of manufacturing the optical semiconductor device by using stacking, after the time when a ridge stripe is formed on an n-type substrate. Note that, for the parts similar to those in Embodiment 1, the same reference numerals are given, and description for the same specifications will be omitted.

Also in an optical semiconductor device100according to Embodiment 2, as shown inFIG.5AandFIG.5B, the ridge stripe5is configured in such a manner that the n-type cladding layer2having the diffraction grating6embedded therein, the active layer3and the p-type first cladding layer4are sequentially stacked on the n-type InP substrate1. After being formed into a ridge shape, it is then buried by the first burying layers7, the n-type second burying layer8and the p-type second cladding layer9. Note also that the p-type second cladding layer9and the p-type first cladding layer4that constitutes the uppermost portion of the ridge stripe5are in contact with each other through the current narrowing window8asandwiched between portions of the n-type second burying layer8. The configuration described so far is basically the same as in Embodiment 1.

Here, what is different from Embodiment 1 is that the n-type second burying layer8is configured so that its thickness D8q on a region shown inFIG.5Bwhere the λ/4 phase shifter6qis placed, is thinner than its basic thickness D8set for another region shown inFIG.5A, and is minimum. In this case, although the thickness D8of the n-type second burying layer8varies, the thickness of the p-type second cladding layer9at its portion covering over the current narrowing window8ais constant in the light traveling direction Dr.

Next, a method of manufacturing the optical semiconductor device100according to Embodiment 2 will be described usingFIG.6AtoFIG.6D, FIG.6E1and FIG.6E2. Note that the steps shown inFIG.6AtoFIG.6Dare the same as the steps shown inFIG.2AtoFIG.2Ddescribed in Embodiment 1, so that description for the figures up toFIG.6Cwill be omitted and the steps fromFIG.6Dwill be described. In Embodiment 1, the n-type second burying layer8is formed at once so as to bury the first burying layers7and the ridge stripe5, whereas, in Embodiment 2, the n-type second burying layer8is formed by a plurality of separate processes (for example, two processes). First, as shown inFIG.6D, a lower layer portion81of the n-type second burying layer8is grown up to the thickness D8q set for the region where the λ/4 phase shifter6qis placed, regardless of the position in the light traveling direction Dr. Thereafter, other semiconductor layers are formed using different steps between the region where the λ/4 phase shifter6qis placed and the region other than that (referred to as “the other region”).

Specifically, for the other region, as shown in FIG.6E1, an upper layer portion82of the n-type second burying layer8is grown successively on the lower layer portion81until a total thickness as the n-type second burying layer8reaches the specified thickness D8. In contrast, for the region where the λ/4 phase shifter6qis placed, as shown in FIG.6E2, since a third mask26is formed on the lower layer portion81, the upper layer portion82is not formed thereon, so that the thickness D8as the n-type second burying layer is equal to the thickness D8q of the lower layer portion81.

Subsequently, after removing the first mask24and the third mask26by using buffered hydrofluoric acid or hydrofluoric acid, similarly to in the step described usingFIG.2Fin Embodiment 1, the p-type second cladding layer9is grown so as to cover the first cladding layer4and the n-type second burying layer8. Lastly, the electrodes10are formed respectively on the lower side of the n-type InP substrate1and on the upper side of the p-type second cladding layer9. As the result, it is possible to configure the optical semiconductor device100in which, as shown inFIG.5AandFIG.5B, the thickness D8q of the n-type second burying layer8on the region where the λ/4 phase shifter6qis placed, is thinner than the thickness D8thereof set for the other region, and is minimum.

As a result, as represented byFIG.5A,FIG.5Band the formula (1) described in Embodiment 1, the thickness D8q of the n-type second burying layer8at the region where the λ/4 phase shifter6qis placed becomes thinner than the thickness at the other region, such as, near the end face100feor the like, causing the length L of the current path through the current narrowing window8ato become shorter. Accordingly, like inFIG.4, the resistance R at the region where the λ/4 phase shifter6qis placed becomes lower, and this facilitates the injection of current into the active layer3, so that it is possible to uniformize the carrier density distribution along the light traveling direction Dr. Accordingly, the longitudinal hole burning is suppressed, thus making possible a stable single-mode operation.

This effect is due to that the resistance is varied by adjustment of a shape (dimension), that is, a thickness distribution of the n-type second burying layer8. Thus, unlike material control, it is possible to easily realize highly-accurate manufacturing and further, complex operational control is not required at the time of use, like in Embodiment 1.

It is noted that, in the above example, a case is shown where the n-type second burying layer8is formed separately of two layers, that is, the lower layer portion81and the upper layer portion82; however, this is not limitative. For example, the n-type second burying layer8may be grown separately as three or more plural layers in such a manner that a portion to be covered by the third mask26(a region in the light traveling direction Dr) is enlarged step by step. Namely, when separate processes that are represented by FIG.6E1and FIG.6E2and depending on the position in the light traveling direction Dr, are repeated two or more times, it is also possible to elaborately vary the thickness D8of the n-type second burying layer8along the light traveling direction Dr. Note that such adjustment in thickness is not limited to being solely based on the difference in grown thickness. For example, it is also possible to fabricate that layer in such a manner that, after the change of the mask region in the light traveling direction Dr, the thickness is adjusted based on the degree of etching (thickness reduction amount).

On the other hand, in order to elaborately vary the thickness D8of the n-type second burying layer8, the repeated number of processes will be increased regardless of whether based on growing or etching. Thus, in order to obtain an elaborate variation, it is more suitable to vary the opening width Wa of the current narrowing window. However, unlike the opening width Wa of the current narrowing window8a,because of absence of such restriction by the width W5of the ridge stripe5, it is more preferable to adjust the thickness D8in the case where it is desired to largely change the ratio between the resistance at the region where the λ/4 phase shifter6qis placed and the resistance at the other region.

Embodiment 3

In Embodiment 3, a case will be described which corresponds to a combination of Embodiments 1 and 2, and in which the distribution of p-cladding resistance in the light traveling direction is adjusted by making variations in both the width of the current narrowing window and the layer thickness at the current-narrowing window portion.FIG.7A,FIG.7BandFIG.8are provided for illustrating a configuration of an optical semiconductor device according to Embodiment 3, andFIG.7shows sectional views for illustrating the configuration of the optical semiconductor device, in whichFIG.7Ais a sectional view of the optical semiconductor device perpendicular to the light traveling direction, at a portion in the light traveling direction near an end face (corresponding to the line B-B inFIG.1A); andFIG.7Bis a sectional view of the optical semiconductor device perpendicular to the light traveling direction, at a portion in the light traveling direction where the λ/4 phase shifter of the semiconductor device is formed (corresponding to the line C-C inFIG.1A).

Further,FIG.8is a characteristic diagram for illustrating characteristics of the optical semiconductor device according to Embodiment 3, in which a light intensity distribution in the active layer, a p-cladding resistance distribution, a carrier density distribution, a distribution of opening width of the current narrowing window for controlling the p-cladding resistance distribution and a thickness distribution of the n-type second burying layer, each in the light traveling direction at the time of laser oscillation, are shown individually, together with a sectional perspective view corresponding toFIG.1A. Note that, for the parts similar to those in the foregoing Embodiment 1 or Embodiment 2, the same reference numerals are given, and description for the same specifications will be omitted.

While the feature of an optical semiconductor device100according to Embodiment 3 may be described on the basis of either Embodiment 1 or Embodiment 2, here, it will be described on the basis of Embodiment 2. In the optical semiconductor device100according to Embodiment 2, although the thickness D8of the n-type second burying layer8varies depending on the position in the light traveling direction Dr, the opening width Wa of the current narrowing window8ais constant and remains the same regardless of the position in the light traveling direction Dr. However, as shown inFIG.7AandFIG.7B, the optical semiconductor device100according to Embodiment 3 is configured so that, in addition to the thickness D8of the n-type second burying layer8, the opening width Wa of the current narrowing window8adiffers depending on the position in the light traveling direction Dr.

For example, as shown inFIG.7B, on the region where the λ/4 phase shifter6qis placed, the opening width Wa of the current narrowing window8abecomes larger and the thickness D8of the n-type second burying layer8becomes thinner, in comparison to the other region, such as, near the end face100feor the like, represented byFIG.7A. Accordingly, as described using the formula (1) in Embodiment 1, near the center in the light traveling direction Dr around which the λ/4 phase shifter6qis placed, the length L of the current path through the current narrowing window8abecomes shorter, so that the p-cladding resistance (resistance R) becomes lower as shown inFIG.8. Furthermore, the width of the current narrowing window8abecomes larger and thus the sectional area S becomes larger, so that the resistance R becomes much lower and this facilitates the injection of current.

Namely, by the semiconductor device100according to Embodiment 3, in addition to achieving an effect that is the same as the effect described in Embodiment 1 (Uniformization of the carrier density distribution described usingFIG.4, that is due to adjustment in p-cladding resistance distribution matched with the light intensity distribution), it becomes possible to control the p-cladding resistance over a broader range and in an elaborate manner, by changing together the length L of the path through the current narrowing window8aand the sectional area S thereof. Namely, by combining the adjustment of the thickness D8that is favorable for enlarging the range and the adjustment of the opening width Wa that is favorable for elaborate control, it is possible to easily accomplish ideal adjustment of the resistance distribution in the light traveling direction Dr.

At that time, the opening width Wa and the thickness D8may be designed to show a monotonic decrease and a monotonic increase, respectively, both from the region where the λ/4 phase shifter6qis placed, as a peak; however, the opening width Wa may be controlled so as to compensate a stepwise variation of the thickness D8. For example, inFIG.8(the lowermost figure), the thickness D8varies in two steps so that the ratio between the thickness D8q at the region of the λ/4 phase shifter6qand a thickness D8e at the other region may be largely changed in response to a change of the light intensity. In that case, when focusing on a direction directed from the center to the end face100fe, at a portion where the thickness D8decreases abruptly, the resistance decreases non-continuously due to such a change of the thickness D8.

Therefore, for example, at each portion inFIG.8where the thickness D8decreases abruptly (changes from D8e to D8q), the opening width Wa may be adjusted to increase non-continuously in order to compensate the non-continuously decreasing resistance due to the change of the thickness D8. Further, for the region where the thickness D8remains the same, the opening width Waq may be varied in a stepless manner. Accordingly, a wide resistance range can be established without unreasonably enlarging the ratio between the opening width Waq that is maximum and an opening width Wae that is minimum. In this case, the adjustment of the thickness D8is not limited to two-step adjustment and may, of course, be three or more-step adjustment.

In addition, the characteristics as described above can be achieved by resistance adjustment based on dimensional designing using semiconductor lithography and crystal growth for an element. Thus, it is possible to realize manufacturing in a well-controlled manner and further, complex operational control is not required at the time of operation.

It is noted that, in each of the foregoing Embodiments, the optical semiconductor device100using the n-type InP substrate1and the manufacturing method thereof have been described; however, the device may instead have a structure which uses a p-type InP substrate and in which the conductivity type of each of the semiconductor layers is reversed. Therefore, with respect to the conductivity types of p-type and n-type described in this application, one of them may be referred to as a first conductivity type while the other one may be referred to as a second conductivity type. Namely, the second conductivity type is an opposite conductivity type to the first conductivity type, so that if the first conductivity type is p-type, the second conductivity type is n-type, and if the first conductivity type is n-type, the second conductivity type is p-type. Accordingly, for example, the member described as the n-type InP substrate1, the member described as the n-type cladding layer2, the member described as the p-type first cladding layer4and the member described as the p-type second cladding layer9, may be read as, a substrate of the first conductivity type, a cladding layer of the first conductivity type, a first cladding layer of the second conductivity type and a second cladding layer of the second conductivity type, respectively, without specifying the conductivity type and the material.

Furthermore, it should be noted that, in this application, a variety of exemplary embodiments and examples are described; however, every characteristic, configuration or function that is described in one or more embodiments, is not limited to being applied to a specific embodiment, and may be applied singularly or in any of various combinations thereof to another embodiment. Accordingly, an infinite number of modified examples that are not exemplified here are supposed within the technical scope disclosed in the present description. For example, such cases shall be included where at least one configuration element is modified; where any configuration element is added or omitted; and furthermore, where at least one configuration element is extracted and combined with a configuration element of another embodiment.

As described above, the optical semiconductor device100according to each of Embodiments, is configured to include: the ridge stripe5which includes a cladding layer of the first conductivity type (n-type cladding layer2), the active layer3, and a first cladding layer of the second conductivity type as an opposite conductivity type to the first conductivity type (p-type first cladding layer4), that are stacked in this order on a surface of a substrate of the first conductivity type (for example, n-type InP substrate1); the first burying layers7by which respective both sides (in the direction perpendicular to the light traveling direction Dr and the stacking direction) of the ridge stripe5are buried, while leaving the top part (topmost end in the stacking direction) of the ridge stripe5exposed; a second burying layer of the first conductivity type (n-type second burying layer8) which covers the respective first burying layers7and has the current narrowing window8awhere portions of the second burying layer that are protruding onto the top part of the ridge stripe5are opposed to each other on the top part with an interval therebetween (opening width Wa); a second cladding layer of the second conductivity type (p-type second cladding layer9) under which the n-type second burying layer8is buried together with the current narrowing window8a;and the diffraction grating6which is formed in the n-type cladding layer2or the p-type first cladding layer4, and in which the λ/4 phase shifter6qis placed at an intermediate portion in the light traveling direction Dr;

wherein a sectional shape (opening width Wa, thickness D8or a combination thereof) of the current narrowing window8ain a direction perpendicular to the light traveling direction Dr varies depending on a position in the light traveling direction Dr so that, at a region in the light traveling direction Dr where the λ/4 phase shifter6qis placed, the resistance R of a current path from the p-type second cladding layer9to the p-type first cladding layer4through the current narrowing window8ais minimum.

Thus, it is possible to easily provide an optical semiconductor device which is capable of stable operation because of reduction of imbalance in the carrier density, without requiring complex operational control.

In particular, when, as described in Embodiment 1, the current narrowing window8ais configured so that its thickness Wa is maximum at the region in the light traveling direction Dr where the λ/4 phase shifter6qis placed, it is possible to reduce imbalance in the carrier density by using elaborate control matched with the distribution of light intensity.

Instead, when, as described in Embodiment 2 or 3, the n-type second burying layer8is configured so that the thickness D8of its portions protruding onto the top part of the ridge stripe5is minimum at the region in the light traveling direction Dr where the λ/4 phase shifter6qis placed, it is possible, even if a large ratio is provided between the maximum and minimum values of the light intensity, to reduce imbalance in the carrier density in a manner of compensating that ratio.

Further, when, at the region in the light traveling direction Dr where the λ/4 phase shifter6qis placed, the resistance R of the current path is designed to fall in a range from five-twelfths to ten-twelfths (respective inverse numbers of 2.4 and 1.2) of the resistance R of the current path at the other region, it is possible to optimize optical semiconductor devices100of almost all types of specifications.

Further, as described above, the method of manufacturing the optical semiconductor device100according to each of Embodiments, is designed to include: a step of forming a stacked structure by stacking a cladding layer of the first conductivity type (n-type cladding layer2), the active layer3, and a first cladding layer of the second conductivity type as an opposite conductivity type to the first conductivity type (p-type first cladding layer4), in this order, on a surface of a substrate of the first conductivity type (for example, n-type InP substrate1); a step of etching both side portions of the stacked structure up to a position nearer to the n-type InP substrate1than to the active layer3, to thereby form the ridge stripe5; a step of burying, using a burying material doped with a semi-insulative material, respective both sides of the ridge stripe5while leaving the top part of the ridge stripe5exposed, to thereby form the first burying layers7; a step of forming a second burying layer of the first conductivity type (n-type second burying layer8) while covering, with at least one mask (first mask24or third mask26), a middle portion of the top part of the ridge stripe5except for both ends thereof so that the second burying layer has the current narrowing window8awhere respective protruding portions of the second burying layer that are protruding from the first burying layers7onto the top part of the ridge stripe5are opposed to each other with an interval therebetween (opening width Wa); and a step of forming, using a material of the second conductivity type (p-type), a second cladding layer of the second conductivity type (p-type second cladding layer9) under which the n-type second burying layer8is buried together with the current narrowing window8a;

wherein, in the step of forming the stacked structure, the diffraction grating6in which the λ/4 phase shifter6qis placed at an intermediate portion in the light traveling direction Dr, is formed in the n-type cladding layer2or the p-type first cladding layer4; and

wherein, in the step of forming the second burying layer of the first conductivity type, at least one of the width and the use number of said at least one mask is changed depending on a position in the light traveling direction Dr so that, at the region in the light traveling direction Dr where the λ/4 phase shifter6qis placed, at least one of the following conditions is satisfied: the opening width Wa of the current narrowing window8ais maximum; and the thickness D8of the portions of the n-type second burying layer8protruding onto the top part of the ridge stripe5is minimum.

Thus, a sectional shape in line with the light traveling direction Dr can be easily formed as designed, so that it is possible to easily provide an optical semiconductor device which is capable of stable operation because of reduction of imbalance in the carrier density, without requiring complex operational control.

DESCRIPTION OF REFERENCE NUMERALS AND SIGNS

1: n-type InP substrate (substrate of the first conductivity type),2: n-type cladding layer (cladding layer of the first conductivity type),3: active layer,4: p-type first cladding layer (first cladding layer of the second conductivity type),5: ridge stripe,6: diffraction grating,6q: λ/4 phase shifter,7: first burying layer,8: n-type second burying layer (second burying layer of the first conductivity type),8a: current narrowing window,9: p-type second cladding layer (second cladding layer of the second conductivity type),10: electrode,24: first mask (mask),25: second mask,26: third mask (mask),100: optical semiconductor device,100fe: end face, D8: thickness, Dr: light traveling direction, R: resistance, Wa: opening width.