Patent ID: 12237038

DETAILED DESCRIPTION

Exemplary embodiments will now be described more comprehensively with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided such that the present disclosure will be more thorough and complete, and the concept of the exemplary embodiments will be fully conveyed to those skilled in the art. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous details are provided to provide a thorough understanding of the embodiments of the present disclosure. Those skilled in the art will recognize, however, that the technical solution of the present disclosure may be practiced without one or more of the details described, or that other methods, components, devices, steps and so on may be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring aspects of the present disclosure.

Furthermore, the accompanying drawings are merely schematic illustrations of the present disclosure. Same or similar parts are denoted by same reference numbers in the drawings and, thus, a detailed description thereof will be omitted. Some block diagrams shown in the figures are functional entities and not necessarily to be corresponding to a physically or logically individual entities. These functional entities may be implemented in software form, or implemented in one or more hardware circuits or integrated circuits, or implemented in different networks and/or processor apparatuses and/or microcontroller apparatuses.

A detailed description of the exemplary embodiments of the present disclosure will be made in the following with reference to the accompanying drawings.

FIG.2is a schematic structural diagram of a local sensing amplifier according to an exemplary embodiment of the present disclosure.

Referring toFIG.2, a local sensing amplifier200is connected to a global signal line Gdata, and is connected to a sense amplifier array SA by means of a local signal line Ldata and a complementary local signal line Ldata #. The local sensing amplifier200is configured to transmit a signal on the local signal line Ldata to the global signal line Gdata when a read control signal Rd is received, and to transmit a signal on the global signal line Gdata to the local signal line Ldata when a write control signal Wr is received. The local sensing amplifier200may include:a precharge circuit1connected to a preset voltage source2, the local signal line Ldata and the complementary local signal line Ldata #. The preset voltage source2is configured to provide a first voltage Vcc in a read-write interval and provide a second voltage VEQ in an idle period. The precharge circuit1is configured to transmit the first voltage Vcc to the local signal line Ldata and the complementary local signal line Ldata # in the read-write interval, and to transmit the second voltage VEQ to the local signal line Ldata and the complementary local signal line Ldata # in the idle period, where the second voltage VEQ is smaller than the first voltage Vcc.

In the embodiments of the present disclosure, the precharge circuit1is arranged in the sense amplifier array SA.

Compared with the existing technologies where the local sensing amplifier is divided into two parts, in the embodiments of the present disclosure, the precharge circuit1capable of providing two voltages may transmit different voltages to the local signal line Ldata and the complementary local signal line Ldata # in different operating states, such that number of components and a layout area can be reduced for the local sensing amplifier.

The embodiments of the present disclosure will be described in detail below.

FIG.3is a circuit diagram of a precharge circuit according to one embodiment of the present disclosure;

Referring toFIG.3, in one embodiment, the precharge circuit1includes:a first transistor M1, the first terminal of the first transistor M1being connected to the preset voltage source2, a second terminal of the first transistor M1being connected to the local signal line Ldata, and a control terminal of the first transistor M1being connected to a precharge signal line Eq;a second transistor M2, a first terminal of the second transistor M2being connected to the preset voltage source2, a second terminal of the second transistor M2being connected to the complementary local signal line Ldata #, and a control terminal of the second transistor M2being connected to the precharge signal line Eq; anda third transistor M3, a first terminal of the third transistor M3being connected to the local signal line Ldata, a second terminal of the third transistor M3being connected to the complementary local signal line Ldata #, and a control terminal of the third transistor M3being connected to the precharge signal line Eq.

The precharge signal line Eq is configured to transmit a precharge signal, which is configured for controlling voltage setting of the local signal line Ldata and the complementary local signal line Ldata # in different operating states. When the precharge signal is a high-level signal, the first transistor M1, the second transistor M2and the third transistor M3may all be N-type transistors, and in response to the precharge signal, the local signal line Ldata and the complementary local signal line Ldata # are set to be equivalent, and are equivalent to the first voltage Vcc or the second voltage VEQ.

In other embodiments, the precharge circuit1may also be implemented by other components, which are not particularly limited in the present disclosure.

FIG.4is a schematic diagram of a preset voltage source according to one embodiment of the present disclosure;

Referring toFIG.4, in the embodiment of the present disclosure, the preset voltage source2is arranged in a row decoding and control circuit (X Decoder, XDEC), and the preset voltage source2includes:a first switch element K1, a first terminal of the first switch element K1being connected to the first voltage, a second terminal of the first switch element K1being connected to an output terminal of the preset voltage source2, and a control terminal of the first switch element K1being connected to a first voltage output control signal;a second switch element K2, a first terminal of the second switch element K2being connected to the second voltage, a second terminal of the second switch element K2being connected to the output terminal of the preset voltage source2, and a control terminal of the second switch element K2being connected to a second voltage output control signal EN2; anda voltage switching subcircuit21connected to the first switch element K1and the second switch element K2, where the voltage switching subcircuit21is configured to output the first voltage output control signal EN1in the read-write interval, and output the second voltage output control signal EN2in the idle period.

A voltage outputted from the output terminal of the preset voltage source2may be marked as a mode voltage VLSAloc. From the above embodiments it may be known that the mode voltage VLSAloc is equivalent to the first voltage Vcc in the read-write interval and is equivalent to the second voltage VEQ in the idle period.

The voltage switching subcircuit21may be a controller in the XDEC. According to different types of the first voltage output control signal EN1and the second voltage output control signal EN2outputted by the voltage switching subcircuit21, the first switch element K1and the second switch element K2may be implemented by means of transistors or other components. In the embodiment as shown inFIG.4, both the first switch element K1and the second switch element K2are N-type transistors. In other embodiments, the first switch element K1and the second switch element K2may also be other elements.

In the embodiment of the present disclosure, the preset voltage source2is simultaneously connected to a plurality of local sensing amplifiers. That is, the preset voltage source2is simultaneously connected to a plurality of precharge circuits1.

By means of the preset voltage source2arranged in the XDEC to provide the first voltage Vcc and the second voltage VEQ in different operating periods, two functions of the local sensing amplifier may be implemented by means of one precharge circuit1, and each read-write conversion circuit may be only provided with one precharge circuit1. The read-write conversion circuit is only arranged in the SA array, there is no need to arrange another part (in the prior art, this part generally is two sets of voltage transmission circuits controlled by control signals corresponding to two operating states) of the read-write conversion circuit in an SWC circuit, and thus there is no need to consider arrangement and area of the two voltage transmission circuits in layout, which can greatly save the number of components and the layout area for the local sensing amplifier.

FIG.5is a schematic diagram of a local sensing amplifier according to one embodiment of the present disclosure;

Referring toFIG.5, in one embodiment, on the basis of the local sensing amplifier200, a local sensing amplifier500is further connected to a complementary global signal line Gdata #, a read control signal line and a write control signal line, where the read control signal line is configured to transmit the read control signal Rd, and the write control signal line is configured to transmit the write control signal Wr. The local sensing amplifier500further includes:a first read-write control circuit51connected to the local signal line Ldata, the complementary local signal line Ldata #, the global signal line Gdata, the read control signal line Rd and the write control signal line Wr, where the first read-write control circuit51is configured to transmit the signal on the global signal line Gdata to the local signal line Ldata when the write control signal is in an enabled state, and output a second signal S2to the global signal line Gdata when the read control signal is in the enabled state and the complementary local signal line Ldata # transmits a first signal S1, the second signal S2being inverse in phase to the first signal S1; anda second read-write control circuit52connected to the local signal line Ldata, the complementary local signal line Ldata #, the complementary global signal line Gdata #, the read control signal line Rd and the write control signal line Wr, where the second read-write control circuit52is configured to transmit a signal on the complementary global signal line Gdata # to the complementary local signal line Ldata # when the write control signal is in an enabled state, and output the second signal S2to the complementary global signal line Gdata # when the read control signal is in the enabled state and the local signal line Ldata transmits the first signal S1.

FIG.6AandFIG.6Brespectively are schematic diagrams of two circuit embodiments of the local sensing amplifier as shown inFIG.5;

Referring toFIG.6A, in one embodiment, the first read-write control circuit51may include:a fourth transistor M4, a first terminal of the fourth transistor M4being connected to the local signal line Ldata, a second terminal of the fourth transistor M4being connected to the global signal line Gdata, and a control terminal of the fourth transistor M4being connected to the write control signal line Wr;a fifth transistor M5, a first terminal of the fifth transistor M5being connected to the global signal line Gdata, and a control terminal of the fifth transistor M5being connected to the complementary local signal line Ldata #;a sixth transistor M6, a first terminal of the sixth transistor M6being connected to a second terminal of the fifth transistor M5, a second terminal of the sixth transistor M6being configured to receive the second signal S2, and a control terminal of the sixth transistor M6being connected to the read control signal line Rd.

The second read-write control circuit52may include:a seventh transistor M7, a first terminal of the seventh transistor M7being connected to the complementary local signal line Ldata #, a second terminal of the seventh transistor M7being connected to the complementary global signal line Gdata #, and a control terminal of the seventh transistor M7being connected to the write control signal line Wr;an eighth transistor M8, a first terminal of the eighth transistor M8being connected to the complementary global signal line Gdata #, and a control terminal of the eighth transistor M8being connected to the local signal line Ldata; anda ninth transistor M9, a first terminal of the ninth transistor M9being connected to a second terminal of the eighth transistor M8, a second terminal of the ninth transistor M9being configured to receive the second signal S2, and a control terminal of the ninth transistor M9being connected to the read control signal line Rd.

An operating principle of the embodiment as shown inFIG.6Ais as below.

During the read-write interval, a precharge phase is entered, the precharge signal is in the enabled state, the first transistor M1and the second transistor M2are enabled, and the signal on the local signal line Ldata and the signal on the complementary local signal line Ldata # are equivalent to the first voltage Vcc, and are manifested as a logic level signal1. Next, the precharge signal enters a disabled state, and the precharge phase is ended.

When the read control signal is in the enabled state, the write control signal is in the disabled state, and the sixth transistor M6and the ninth transistor M9are enabled. At this moment, a gate of the fifth transistor M5is controlled by the complementary local signal line Ldata #, and a gate of the eighth transistor M8is controlled by the local signal line Ldata.

When the local signal line Ldata is set to the first signal (logic level signal 1) by the sense amplifier and the complementary local signal line Ldata # is set to the second signal (logic level signal 0) by the sense amplifier, the fifth transistor M5is disabled, the eighth transistor M8is enabled, and the complementary global signal line Gdata # is grounded by means of the enabled eighth transistor M8and the ninth transistor M9, and is manifested as a logic level signal of 0. The state of the complementary global signal line Gdata # is the same as that of the complementary local signal line Ldata #.

When the local signal line Ldata is set to the second signal (logic level signal 0) by the sense amplifier and the complementary local signal line Ldata # is set to the first signal (logic level signal 1) by the sense amplifier, the fifth transistor M5is enabled, the eighth transistor M8is disabled, and the global signal line Gdata is grounded by means of the enabled fifth transistor M5and the sixth transistor M6, and is embodied as the logic level signal 0. The state of the global signal line Gdata is the same as that of the local signal line Ldata.

Thus, data transmitted by the sense amplifier to the local signal line Ldata and the complementary local signal line Ldata # are correspondingly transmitted to the global signal line Gdata and the complementary global signal line Gdata # by means of the local sensing amplifier.

When the write control signal is in the enabled state, the read control signal is in the disabled state. At this moment, the fourth transistor M4and the seventh transistor M7are enabled, the state of the global signal line Gdata is the same as the state of the local signal line Ldata, and the state of the complementary global signal line Gdata # is the same as that of the complementary local signal line Ldata #. The data on the global signal line Gdata and the data on the complementary global signal line Gdata # are correspondingly transmitted to the local signal line Ldata and the complementary local signal line Ldata # by means of the local sensing amplifier, and then are transmitted to the sense amplifier by means of the local signal line Ldata and the complementary local signal line Ldata #.

During the idle period (for example, when a read-write process is ended), after the precharge phase is ended, the third transistor M3is disabled, and a voltage of the local signal line Ldata is equal to that of the complementary local signal line Ldata #, both being equal to or lower than the first voltage Vcc or the second voltage VEQ. At this moment, both the read control signal and the write control signal are in the disabled state, neither the first read-write control circuit51nor the second read-write control circuit52runs, and the circuit operates at lower power consumption.

Referring toFIG.6B, in one embodiment, the local sensing amplifier may further include:a second signal control circuit61, a first terminal of the second signal control circuit61being connected to the first read-write control circuit51and the second read-write control circuit52, and a second terminal of the second signal control circuit61being configured to receive the second signal S2, and controlled by a preset enable signal En, the second signal control circuit61being configured to transmit the second signal S2to the first read-write control circuit51and the second read-write control circuit52when the preset enable signal En is in the enabled state.

In the embodiment as shown inFIG.6B, the second signal control circuit61may include:a tenth transistor M10, a first terminal of the tenth transistor M10being connected to the first read-write control circuit51and the second read-write control circuit52, a second terminal of the tenth transistor M10being configured to receive the second signal S2, and a control terminal of the tenth transistor M10being configured to receive the preset enable signal En. In the embodiment as shown inFIG.6, the second signal S2is equal to the logic level signal 0, and the first signal S1is equal to the logic level signal 1.

In the embodiments as shown inFIG.6AandFIG.6B, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9and the tenth transistor M10are all N-type transistors, the second signal S2is the logic level signal 0, and the first signal S1is the logic level signal 1.

The circuits as shown inFIG.6AandFIG.6Bare only examples. In other embodiments, functions of the circuits as shown inFIG.6AandFIG.6Bmay also be implemented by means of other logic circuits. When the functions of the circuits as shown inFIG.6AandFIG.6Bare implemented by other means, other relationships may be established between the first signal S1and the second signal S2, which is not particularly limited in the present disclosure.

FIG.7is a schematic diagram of a local sensing amplifier according to another embodiment of the present disclosure;

Referring toFIG.7, in one embodiment, on the basis of the local sensing amplifier200, a local sensing amplifier700is further connected to a read control signal line Rd and a write control signal line Wr, where the read control signal line Rd is configured to transmit the read control signal, and the write control signal line Wr is configured to transmit the write control signal. The local sensing amplifier700also includes:a read control circuit71connected to the global signal line Gdata, the complementary local signal line Ldata # and the read control signal line Rd, the read control circuit71being configured to output a second signal S2to the global signal line Gdata when the complementary local signal line Ldata # transmits a first signal S1and the read control signal is in an enabled state;a first write control circuit72connected to the global signal line Gdata, the local signal line Ldata and the write control signal line Wr, the first write control circuit72being configured to transmit the signal on the global signal line Gdata to the local signal line Ldata when the write control signal is in an enabled state; anda second write control circuit73connected to the global signal line Gdata, the complementary local signal line Ldata # and the write control signal line Wr, the second write control circuit73being configured to output the second signal S2to the complementary local signal line Ldata # when the write control signal is in an enabled state and the global signal line Gdata transmits the first signal S1.

FIG.8is a schematic diagram of one circuit embodiment of the local sensing amplifier as shown inFIG.7.

Referring toFIG.8, in one embodiment, the read control circuit71includes a fourth transistor M4, where a first terminal of the fourth transistor M4is connected to the local signal line Ldata, a second terminal of the fourth transistor M4is connected to the global signal line Gdata, and a control terminal of the fourth transistor M4is connected to the write control signal line Wr.

The first write control circuit72includes:a fifth transistor M5, a first terminal of the fifth transistor M5being connected to the global signal line Gdata, and a control terminal of the fifth transistor M5being connected to the complementary local signal line Ldata #; anda sixth transistor M6, a first terminal of the sixth transistor M6being connected to a second terminal of the fifth transistor M5, a second terminal of the sixth transistor M6being configured to receive the second signal S2, and a control terminal of the sixth transistor M6being connected to the read control signal line Rd.

The second write control circuit73includes:an eleventh transistor M11, a first terminal of the eleventh transistor M11being connected to the complementary local signal line Ldata #, and a control terminal of the eleventh transistor M11being connected to the global signal line Gdata; anda twelfth transistor M12, a first terminal of the twelfth transistor M12being connected to a second terminal of the eleventh transistor M11, a second terminal of the twelfth transistor M12being configured to receive the second signal S2, and a control terminal of the twelfth transistor M12being connected to the write control signal line Wr.

In the embodiment shown inFIG.8, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the eleventh transistor M11and the twelfth transistor M12are all N-type transistors, the first signal S1is a logic level signal 1, and the second signal S2is a logic level signal 0.

An operating process of the embodiment as shown inFIG.8is as below.

During the read-write interval, a precharge phase is entered, the precharge signal is in the enabled state, the first transistor M1and the second transistor M2are enabled, and the signal on the local signal line Ldata and the signal on the complementary local signal line Ldata # are equivalent to the first voltage Vcc, and are manifested as a logic level signal 1. Next, the precharge signal enters a disabled state, and the precharge phase is ended.

When the read control signal is in the enabled state, the write control signal is in the disabled state, and the sixth transistor M6is enabled. At this moment, the gate of the fifth transistor M5is controlled by the complementary local signal line Ldata #. First, the global signal line Gdata is precharged to the first voltage Vcc, which is manifested as the logic level signal 1. When the complementary local signal line Ldata # is set to the second signal (the logic level signal 0) by the sense amplifier, the fifth transistor M5is disabled. In this case, the global signal line Gdata is remained at the first voltage Vcc, and is manifested as the logic level signal 1.

When the complementary local signal line Ldata # is set to the first signal (the logic level signal 1) by the sense amplifier, this means that the local signal line Ldata is set to the second signal (the logic level signal 0) by the sense amplifier at this moment, the fifth transistor M5is enabled, and the global signal line Gdata is grounded by means of the enabled fifth transistor M5and the sixth transistor M6, and is embodied as the logic level signal 0. The state of the global signal line Gdata is the same as that of the local signal line Ldata.

When the write control signal is in the enabled state, the read control signal is in the disabled state. At this moment, the fourth transistor M4is enabled, and the state of the global signal line Gdata is the same as that of the local signal line Ldata. That is, the data on the global signal line Gdata are transmitted to the local signal line Ldata, and then are transmitted to the sense amplifier by means of the local signal line Ldata.

In this case, when the global signal line Gdata transmits the logic level signal 1, the eleventh transistor M11is enabled, and the complementary local signal line Ldata # is grounded by means of the enabled eleventh transistor M11and the twelfth transistor M12, and is embodied as the logic level signal 0, which is opposite to the state of the local signal line Ldata. When the global signal line Gdata transmits the logic level signal 0, the eleventh transistor M11is disabled, and the complementary local signal line Ldata # still maintains the logic level signal 1 at the end of the precharge state, which is opposite to the state of the local signal line Ldata. Thereby, the signal on the global signal line Gdata is transmitted to the sense amplifier by means of the local signal line Ldata and the complementary local signal line Ldata # which are in opposite states.

During the idle period, after the precharge phase is ended, the third transistor M3is disabled, and the voltage of the local signal line Ldata is equal to that of the complementary local signal line Ldata #, both being equal to or lower than the first voltage Vcc or the second voltage VEQ. At this moment, both the read control signal and the write control signal are in the disabled state, none of the read control circuit71, the first write control circuit72and the second write control circuit73runs, and the circuit operates at lower power consumption.

FIG.9is a schematic diagram of the local sensing amplifier as shown inFIG.7according to one embodiment.

Referring toFIG.9, in one embodiment, on the basis of the local sensing amplifier700, a local sensing amplifier900further includes:an auxiliary read-write circuit91connected to the first write control circuit72, the local signal line Ldata and the complementary local signal line Ldata #, where the auxiliary read-write circuit91is configured to output the first signal S1to the complementary local signal line Ldata # when the write control signal is in the enabled state and the global signal line Gdata transmits the second signal S2.

The auxiliary read-write circuit91is further configured to amplify a signal transmitted by the local signal line Ldata and a signal transmitted by the complementary local signal line Ldata # when the read control signal Rd is in the enabled state.

In one embodiment, the auxiliary read-write circuit91is further connected to a preset voltage source2, which is configured to provide the first voltage Vcc when the read control signal is in the enabled state. The auxiliary read-write circuit91is further configured to output the first signal S1to the local signal line Ldata when a voltage transmitted by the local signal line Ldata is greater than a voltage transmitted by the complementary local signal line Ldata #, and to output the first signal S1to the complementary local signal line Ldata # when the voltage transmitted by the local signal line Ldata is smaller than the voltage transmitted by the complementary local signal line Ldata #, where the first signal S1is equivalent to the first voltage Vcc.

FIG.10is a schematic circuit diagram of the local sensing amplifier as shown inFIG.9.

Referring toFIG.10, in one embodiment, the auxiliary read-write circuit91may include:a thirteenth transistor M13, a first terminal of the thirteenth transistor M13being connected to the preset voltage source2(mode voltage VLSAloc), a second terminal of the thirteenth transistor M13being connected to the complementary local signal line Ldata #, and a control terminal of the thirteenth transistor M13being connected to the local signal line Ldata;a fourteenth transistor M14, a first terminal of the fourteenth transistor M14being connected to the preset voltage source2(the mode voltage VLSAloc), a second terminal of the fourteenth transistor M14being connected to the local signal line Ldata, and a control terminal of the fourteenth transistor M14being connected to the complementary local signal line Ldata #;a fifteenth transistor M15, a first terminal of the fifteenth transistor M15being connected to the local signal line Ldata, a second terminal of the fifteenth transistor M15being configured to receive the second signal S2, and a control terminal of the fifteenth transistor M15being connected to the complementary local signal line Ldata #; anda sixteenth transistor M16, a first terminal of the sixteenth transistor M16being connected to the complementary local signal line Ldata #, a second terminal of the sixteenth transistor M16being configured to receive the second signal S2, and a control terminal of the sixteenth transistor M16being connected to the local signal line Ldata.

In the embodiment as shown inFIG.10, both the thirteenth transistor M13and the fourteenth transistor M14are P-type transistors, and the fifteenth transistor M15and the sixteenth transistor M16are both N-type transistors. The first signal S1is a logic level signal1, and the second signal S2is a logic level signal 0.

An operating process of the auxiliary read-write circuit91of the embodiment as shown inFIG.10is as below.

No matter in the read-write interval or the idle period, after the precharge phase is ended, the third transistor M3is disabled. In this case, when the voltage of the local signal line Ldata is higher than the voltage of the complementary local signal line Ldata #, the fourteenth transistor M14and the sixteenth transistor M16are enabled first, causing the thirteenth transistor M13and the fifteenth transistor M15to be disabled, the voltage of the local signal line Ldata connected to the second terminal of the fourteenth transistor M14is equivalent to the mode voltage VLSAloc, and the voltage of the complementary local signal line Ldata # connected to the first terminal of the sixteenth transistor M16is equivalent to the second signal S2, i.e., the logic level signal 0. On the contrary, when the voltage of the local signal line Ldata is lower than the voltage of the complementary local signal line Ldata #, the thirteenth transistor M13and the fifteenth transistor M15are enabled first, causing the fourteenth transistor M14and the sixteenth transistor M16to be disabled, the voltage of the local signal line Ldata connected to the first terminal of the fifteenth transistor M15is equivalent to the second signal S2, i.e., the logic level signal 0, and the voltage of the complementary local signal line Ldata # connected to the second terminal of the thirteenth transistor M13is equivalent to the mode voltage VLSAloc.

Therefore, as long as there is a voltage difference between the local signal line Ldata and the complementary local signal line Ldata #, the auxiliary read-write circuit91can amplify the voltage difference to be the mode voltage VLSAloc. The mode voltage VLSAloc varies according to operating phases, and detailed descriptions thereof are omitted here.

FIG.11is a schematic diagram of the local sensing amplifier as shown inFIG.9according to one embodiment.

Referring toFIG.11, in one embodiment, the local sensing amplifier further includes:a second signal auxiliary circuit111configured to receive the second signal S2. Controlled by a preset enable signal En, the second signal auxiliary circuit111is configured to transmit the second signal S2to the complementary local signal line Ldata # when the preset enable signal En is in an enabled state and a voltage transmitted by the local signal line Ldata is greater than a voltage transmitted by the complementary local signal line Ldata #, and to transmit the second signal S2to the local signal line Ldata when the preset enable signal En is in the enabled state and the voltage transmitted by the local signal line Ldata is smaller than the voltage transmitted by the complementary local signal line Ldata #.

In the embodiment as shown inFIG.11, when the second signal auxiliary circuit111is connected to the auxiliary read-write circuit91, the second signal auxiliary circuit111may include:a seventeenth transistor M17, where a first terminal of the seventeenth transistor M17is connected to the second terminal of the fifteenth transistor M15and the second terminal of the sixteenth transistor M16, a second terminal of the seventeenth transistor M17is configured to receive the second signal S2, and a control terminal of the seventeenth transistor M17is configured to receive the preset enable signal. The second signal auxiliary circuit111is configured to output the second signal S2to the fifteenth transistor M15and the sixteenth transistor M16when the preset enable signal En is in the enabled state.

In the circuit as shown inFIG.11, the fifteenth transistor M15and the sixteenth transistor M16are both N-type transistors, the fifth transistor M5and the eleventh transistor M11are both N-type transistors, the first signal S1is the logic level signal 1, and the second signal S2is the logic level signal 0.

FIG.12is a schematic diagram of a memory according to an exemplary embodiment of the present disclosure.

Referring toFIG.12, a memory1200may include:a plurality of memory arrays121, a sense amplifier array122being arranged between adjacent two of the plurality of memory arrays121, and each of the sense amplifier arrays122being connected to adjacent two of the plurality of memory arrays121;a local sensing amplifier123according to any one of the embodiments as shown inFIG.2toFIG.11, the local sensing amplifier123being connected to the global signal line Gdata, and being connected to the sense amplifier array122by means of the local signal line Ldata and the complementary local signal line Ldata #; and a row decoding and control circuit XDEC provided with a preset voltage source124, where the preset voltage source124is configured to output a first voltage Vcc and a second voltage VEQ to the local sensing amplifier123.

In the embodiment as shown inFIG.12, the local sensing amplifier123may be arranged in the sense amplifier array122and is connected to the sense amplifier array122.

In the local sensing amplifier and the memory using the local sensing amplifier provided by the embodiments of the present disclosure, by arranging a precharge circuit connected to a preset voltage source connected to a plurality of local sensing amplifiers to provide two voltages in two operating states, the local sensing amplifier is allowed to set the local signal line/complementary local signal line to the first voltage or the second voltage in the two operating states in the case where only one precharge circuit is arranged, thereby reducing the number of components for the local sensing amplifier and reducing circuit complexity. The local sensing amplifier is only arranged in the sense amplifier array, such that the number of components and the layout area can be reduced for the entire storage circuit, and thus volume of the memory can be reduced.

It is to be noticed that although a plurality of circuits or subcircuits of a device for action execution have been mentioned in the above detailed description, this partition is not compulsory. Actually, according to the embodiments of the present disclosure, features and functions of two or more circuits or subcircuits as described above may be embodied in one circuit or subcircuit. Reversely, features and functions of one circuit or subcircuit as described above may be further embodied in more circuits or subcircuits.

Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed here. This application is intended to cover any variations, uses, or adaptations of the present disclosure following the general principles thereof and including such departures from the present disclosure as come within known or customary practice in the art. It is intended that the specification and embodiments be considered as exemplary only, with a true scope and spirit of the present disclosure being indicated by the claims.

INDUSTRIAL APPLICABILITY

In the embodiments of the present disclosure, by modifying a circuit structure of the local sensing amplifier, one local sensing amplifier is provided to connect different power supply voltages, and by adjusting a control sequence, the local sensing amplifier may be caused to connect different power supply voltages in different operating stages to implement different functions. Two parts of the local sensing amplifier (LSA) may be integrated to reduce the layout area of the LSA.