Patent ID: 12254794

DETAILED DESCRIPTION

In order to make objects, technical solutions, and advantages of the embodiments of the present disclosure apparent, the technical solutions of the embodiments of the present disclosure will be described in a clearly and fully understandable way in connection with the drawings related to the embodiments of the present disclosure. Apparently, the described embodiments are just a part but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, those skilled in the art can obtain other embodiment(s), without any inventive work, which should be within the scope of the present disclosure.

Unless otherwise defined, all the technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms “first,” “second,” etc., which are used in the present disclosure, are not intended to indicate any sequence, amount or importance, but distinguish various components. The terms “comprise,” “comprising,” “include,” “including,” etc., are intended to specify that the elements or the objects stated before these terms encompass the elements or the objects and equivalents thereof listed after these terms, but do not preclude the other elements or objects.

FIG.1is a schematic plan structure of a display panel. As shown inFIG.1, the display panel includes a base substrate01. The display panel includes a first display region A1and a second display region A2, and the first display region A1may at least partially surround the second display region A2. For example, the second display region A2as shown inFIG.1is located in a middle of a top of the base substrate01, and four sides of the first display region A1having a rectangular shape may all surround the second display region A2, that is, the second display region A2may be completely surrounded by the first display region A1.

For example, the second display region A2may not be located in the middle of the top of the base substrate01as shown inFIG.1, but may be located in other positions. For example, the second display region A2may be located at an upper left corner or an upper right corner of the base substrate01.

FIG.2is an enlarged view of a partial detail of the display panel as shown inFIG.1. As shown inFIGS.1and2, the display panel includes a plurality of first pixel circuits10, a plurality of second pixel circuits20and a plurality of first light-emitting elements30located in the first display region A1, and a plurality of second light-emitting elements40located in the second display region A2, and at least one column of first pixel circuits10can be arranged between two adjacent columns of second pixel circuits20.

For example, as shown inFIGS.1and2, at least one first pixel circuit10may be connected with at least one first light-emitting element30, and an orthographic projection of the first pixel circuit10on the base substrate01and an orthographic projection of the at least one first light-emitting element30connected with the first pixel circuit on the base substrate01may at least partially overlap. The first pixel circuit10can be used to provide a driving signal for the first light-emitting element30connected with the first pixel circuit to drive the first light-emitting element30to emit light.

For example, as shown inFIGS.1and2, at least one second pixel circuit20may be connected with at least one second light-emitting element40through a conductive line L1, and the second pixel circuit20may be used to provide a driving signal for the second light-emitting element40connected with the second pixel circuit to drive the second light-emitting element40to emit light. The second light-emitting element40and the second pixel circuit20are located in different regions, there is no overlap between an orthographic projection of at least one second pixel circuit20on the base substrate01and an orthographic projection of at least one second light-emitting element40on the base substrate01.

For example, the first display region A1can be a non-transparent display region, and the second display region A2can be a transparent display region. Therefore, the display panel can directly set the required hardware structures, such as photosensitive sensors, etc., in the second display region A2without digging holes, thus providing a foundation for realizing a full screen. Because the second display region A2only includes the light-emitting element, but does not include the pixel circuit, the light transmittance of the second display region A2can also be improved.

FIG.3is an enlarged view of a region E1in the display panel as shown inFIG.1. As shown inFIG.3, the first display region A1includes not only the plurality of pixels, but also the plurality of columns of second pixel circuits20, and the second display region A2includes only the plurality of second light-emitting elements40.

The above-mentioned pixel refers to a structure including a pixel circuit and a light-emitting element. Taking the first pixel circuit10and the first light-emitting element30as examples, it can be seen with reference toFIG.3that each pixel as shown inFIG.3includes a red sub-pixel R, two green sub-pixels G1and G2, and a blue sub-pixel B, and the red sub-pixel R and the blue sub-pixel B are located in the same column, and the two green sub-pixels G1and G2are located in the same column. Of course, in some embodiments, the pixels may also include sub-pixels with other colors and sub-pixels with other numbers, and the arrangement of each sub-pixel is not limited to the structure as shown inFIG.3. For example, each pixel may only include one red sub-pixel R, one blue sub-pixel B, and one green sub-pixel G.

For example, the electrical connection relationship between the plurality of first pixel circuits10and the plurality of first light-emitting elements30can be in one-to-one correspondence. That is, each first pixel circuit10may be connected with one first light-emitting element30, and the first light-emitting elements30connected with respective first pixel circuits10are different. Therefore, the orthographic projection of each first pixel circuit10on the base substrate01and the orthographic projection of the connected first light-emitting element30on the base substrate01are at least partially overlapped. Of course, the embodiment of the present disclosure is not limited thereto, and some of the first pixel circuits may be divided into a plurality of first pixel circuit pairs, and one first pixel circuit pair is electrically connected with one first light-emitting element.

For example, similar to the electrical connection relationship between the first pixel circuit10and the first light-emitting element30, the electrical connection relationship between the second pixel circuits20and the second light-emitting elements40can also be in one-to-one correspondence. For example, the orthographic projection of each second pixel circuit20on the base substrate01does not overlap with the orthographic projection of the second light-emitting element40connected with the second pixel circuit20on the base substrate01.

For example, a density of the second light-emitting elements40located in the second display region A2may be the same as a density of the first light-emitting elements30located in the first display region A1. For example, in two regions, with the same area, respectively in the first display region A1and the second display region A2, an amount of the light-emitting elements is the same, for example, an amount of light-emitting elements per inch in the first display region A1and an amount of light-emitting elements per inch in the second display region A2are the same. Therefore, the first display region A1(including a main display region, for example) does not have two partitions with different pixels per inch, and there is no bright-dark boundary in the first display region A1when displaying a picture, so that the display effect of the display panel is good.

For example,FIG.4is an enlarged view of a region E2of the display panel as shown inFIG.1. As shown inFIGS.1to4, a resolution of the first display region A1may be larger than that of the second display region A2. For example, an area of the first display region A1is larger than that of the second display region A2, and an amount of the light-emitting elements included in the first display region A1is larger than that included in the second display region A2.

For example, the resolution of the first display region A1may be less than or equal to the resolution of the second display region A2. For example, the area of the first display region A1and the area of the second display region A2may be the same, and the amount of light-emitting elements in the first display region A1and the amount of light-emitting elements in the second display region A2may be the same. For example, the area of the first display region A1may be smaller than that of the second display region A2, and the amount of the light-emitting elements in the first display region A1is smaller than the amount of the light-emitting elements in the second display region A2.

For example, each light-emitting element may include a first electrode, a light-emitting layer, and a second electrode which are stacked, and the second electrode is located on a side of the light-emitting layer facing the base substrate. For example, the second electrode may be an anode of the light-emitting element. For example, as shown inFIG.4, a size of an anode of the first light-emitting element30may be larger than that of an anode of the second light-emitting element40to ensure that the light transmittance of the second display region A2is larger than that of the first display region A1. For example, the shape and size of the anode of the second light-emitting element40can be further optimized to ensure better light transmittance. For example, as shown inFIG.4, a light-emitting region of the second light-emitting element40may have a shape of elliptical.

For example, in order to improve the light transmittance of the second display region A2, the conductive line L1connecting the second light-emitting element and the second pixel circuit may be a transparent conductive line. For example, the conductive line L1can be made of a transparent material, such as indium tin oxide (ITO), indium gallium zinc oxide (IGZO) or indium zinc oxide (IZO), etc. For example, in the case where the conductive line L1is made of ITO material, the conductive line L1can also be called ITO trace. The following embodiments all take the case that the conductive line L1is an ITO trace as an example.

In a display panel, the pixel circuit (including the first pixel circuit10and the second pixel circuit20) and the first light-emitting element30have the same pitch. For example, a width of the pixel circuit ranges from about 30 microns (μm) to 32 μm, and a length of the pixel circuit ranges from about 60 μm to 65 μm. For example, the size of one pixel circuit may be 31.6 μm*63.2 μm. In the present disclosure, on the premise of not reducing the amount of pixels in the first display region A1, to provide sufficient space for the second pixel circuit20, each pixel circuit can be compressed along the first direction X (for example, the extending direction of a gate line, which can also be referred to as a lateral direction), so that the width of the pixel circuit in the first direction is smaller than that of the first light-emitting element30; or, the width of the first light-emitting element30in the first direction may be larger than that of the first light-emitting element30by extending the first light-emitting element30in the first direction. Therefore, on the premise of the same size of the base substrate01, by compressing the size of the pixel circuit in the first direction, more regions can be found in the first display region A1, and correspondingly, the second pixel circuit20dedicated to driving the second light-emitting element40located in the second display region A2can be provided in the extra regions.

For example, the width of the compressed pixel circuit and the width of the first light-emitting element30may differ by about 4 μm. For example, the size of the compressed pixel circuit may be 27.6 μm×63.2 μm.

For example, taking the case that the shape of the second display region is a circle, and taking half of the diameter of the second display region (for example, a left half of the second display region) extending along the Y direction as an example, for the second display region with a radius of 1390.4 μm, before compression, there are 44 (which is obtained by 1390.4/31.6) columns of light-emitting elements in this radius range, that is, extra 44 columns of pixel circuits are needed to control the second light-emitting elements of the second display region. Then, the total number of pixel circuits to be compressed in the X direction is 347.6 (which is obtained by 1390.4/4) columns Because the amount of pixel circuits is an integer, at least 348 columns of original pixel circuits need to be compressed here; after compression, some of the pixel circuits (i.e. the first pixel circuits) are used to control the first light-emitting elements in the first display region, and the surplus pixel circuits (i.e. the second pixel circuits) are used to control the second light-emitting elements in the second display region.

FIG.5shows a comparison diagram of structure layouts of pixel circuits before and after compression. For example, as shown inFIG.5, taking the difference of the widths of the pixel circuit before and after compression as an example, the pixel circuit may include a driving structure and a transfer portion B1for connecting to the anode of the light-emitting element, and the size of the transfer portion B1may represent the size of the pixel circuit. Before compression, the sizes of the pixel circuit and the light-emitting element both have a width of 1-100 μm and a height of 2-200 μm. After compression, the size of the light-emitting element and the height of the pixel circuit are unchanged, but the width of the pixel circuit is narrowed by 1-20 μm, so that there will be at least one column of compressed pixel circuits which is added in every few columns of compressed pixel circuits. The whole screen adopts this design to realize full-screen compression. For example, the added columns of compression circuit can be configured to connect the second light-emitting elements40in the second display region A2to control the second light-emitting elements40to emit light. For example, the added columns of compression circuit close to the periphery of the second display region A2can be used as the second pixel circuit20to be connected with the second light-emitting element40. The design of the above-mentioned compressed pixel circuit can realize normal display without changing the resolution of the display panel, thus enabling full use of the existing space of the display panel to realize normal display.

FIG.6is a schematic diagram of one pixel. As shown inFIGS.1to6, the width of the pixel circuit may refer to the width of the orthographic projection of the layout of the pixel circuit on the base substrate01along the first direction X. The width of the first light-emitting element30refers to the width of the orthographic projection of the anode of the first light-emitting element30on the base substrate01along the first direction X.

For example, each first light-emitting element is included in one sub-pixel in one pixel. For example, each first light-emitting element may be a light-emitting element in a red sub-pixel R, a green sub-pixel G1or G2, or a blue sub-pixel B. As shown inFIG.6, upon determining the size of the anode of the first light-emitting element, the width D10of the pixel in the first direction X can be measured in a period of one pixel, and then for the width D01of each first light-emitting element, the total width D10of the pixel can be divided by the amount of sub-pixels included in the pixel. Similarly, because each first light-emitting element is correspondingly connected with one pixel circuit, the width of the pixel circuit in the first direction X can still be measured by taking the pixel circuit connected with one pixel as a period, and then for the width DO of each pixel circuit, the total width can be divided by the amount of sub-pixels included in the pixel. The figure schematically shows that the X direction is the first direction, but it is not limited thereto. The Y direction can also be called the first direction, and the X direction and the Y direction can be interchanged.

For example, as shown inFIG.5, the pixel circuit can have a 7T1C structure, that is, it includes seven transistors and one capacitor.FIG.7shows a schematic structure diagram of 7T1C pixel circuit, andFIG.8shows a structural layout of 7T1C pixel circuit. The pixel circuits shown inFIGS.5to8are the first pixel circuit, and the second pixel circuit can have the 7T1C structure shown inFIG.5, and the layout of the second pixel circuit can be the same as or different from that as shown inFIG.8.

For example, as shown inFIGS.1to8, the 7T1C pixel circuit10includes a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first light-emitting control transistor T4, a second light-emitting control transistor T5, a first reset transistor T6, a second reset transistor T7, and a storage capacitor C1. The pixel circuit can be connected with a gate signal terminal Gate, a data signal terminal Data, a reset signal terminals RST1and RST2, a light-emitting control signal terminal EM, a power supply terminal VDD, an initial power supply terminals Vinit1and Vinit2, and a light-emitting element EL, which can also be connected with a power supply terminal VSS. The pixel circuit can be used to drive the connected light-emitting element to emit light in response to the signals provided by the connected signal terminals.

For example, the gate signal terminal Gate may be a gate line, the data signal terminal Data may be a data line, the reset signal terminals RST1and RST2may be reset control signal lines, the light-emitting control signal terminal EM may be a light-emitting control signal line, the power supply terminal VDD may be a power supply signal line, and the initial power supply terminals Vinit1and Vinit2may be reset power supply signal lines.

For example, transistors can be divided into N-type transistors and P-type transistors according to their characteristics. The present disclosure is explained by taking the case that transistors are all P-type transistors as an example.

FIG.9is a partial structural diagram of a first display region A1.FIG.10is a schematic diagram of the structure of some pixel circuits in the display panel as shown inFIG.2, andFIG.11is a schematic diagram of the structure of some light-emitting elements in the display panel shown inFIG.2. As shown inFIGS.1to11, the width of the pixel circuit is smaller than that of the light-emitting element, so that the pixel circuits in the second column and ninth column in the first display region are not connected with any first light-emitting elements30, and are the added columns of pixel circuits, which can be used as the second pixel circuit20to connect the second light-emitting elements40in the second display region A2. For example, the plurality of first light-emitting elements30may include four kinds of light-emitting elements: R (a red light-emitting element), G1(a first green light-emitting element), B (a blue light-emitting element), and G2(a second green light-emitting element), and each light-emitting element includes a transfer portion B2connected with the first pixel circuit10. The connecting portion B1of the first pixel circuit10and the connecting portion B2of the first light-emitting element30may be connected by a conductive layer, for example, the conductive layer may be a source-drain metal layer SD2. Of course, the present disclosure is not limited thereto, and the first pixel circuit10and the first light-emitting element30can be overlapped together, without providing the source-drain metal layer SD2to connect them.

For example, at least one second pixel circuit20and at least one second light-emitting element40may both have a transfer portion, and the transfer portion of at least one second pixel circuit20and the transfer portion of at least one second light-emitting element40may be electrically connected by the conductive line L1.

In order to ensure sufficient space for setting the conductive line L1, the axis extending in the row direction of the transfer portion of each second pixel circuit20may be in a straight line with the axis extending in the row direction of the transfer portion of any second light-emitting element40located in the same row as the second pixel circuit20. For example, in the second pixel circuits20and the second light-emitting elements40located in the same row, the transfer portion of the second pixel circuit20and the transfer portion of the second light-emitting element40are on the same straight line. Similarly, in the first pixel circuit10and the first light-emitting element30located in the same row, the transfer portion B1of the first pixel circuit10and the transfer portion B2of the first light-emitting element30can also be located on the same straight line, so that the trace can be arranged neatly.

FIG.12is a schematic plan view of the display panel as shown inFIG.1. As shown inFIG.12, the first display region A1may include a first sub-display region A11and a second sub-display region A12arranged along the second direction Y. The first sub-display region A11may include two symmetrical target sub-display regions A110. For example, the layout of the two target sub-display regions A110is the same. The second display region A2may include two third sub-display regions A21symmetrically arranged. For example, the layouts of the two third sub-display regions A21are the same. For example, one target sub-display region A110, the second display region A2, and the other target sub-display region A110may be sequentially arranged along the first direction X.

For example, a left half and a right half of the display panel in the present disclosure have the same layout. Therefore, the following embodiments only show the left half structure of the display panel, that is, a target sub-display region A110and an adjacent third sub-display region A21located in the left half. The right part is the same as the left part, so the repetition will not be repeated herein again.

For example, the above-mentioned added columns of pixel circuits, that is, the plurality of second pixel circuits20, can be dispersed in the first display region A1, and their disposed positions can be flexibly adjusted according to the requirements, as long as the plurality of second pixel circuits20can be effectively connected with the second light-emitting element40and drive the second light-emitting element40to emit light reliably. For example, in the embodiment of the present disclosure, taking the plurality of second pixel circuits20scattered in the column direction, the row direction and the diagonal direction as an example, the following schematic explanation is made on the installation positions of the second pixel circuits20.

FIG.13is a partially enlarged schematic diagram of the pixel circuit of the display panel shown inFIG.12, andFIG.14is a schematic diagram of some light-emitting elements in the third sub-display region and the target sub-display region shown inFIG.13. As shown inFIGS.1to14, a plurality of first pixel circuits10may include a plurality of columns of first pixel circuits10extending in the second direction Y and arranged in the first direction X, and a plurality of second pixel circuits20may include a plurality of columns of second pixel circuits20extending in the second direction Y and arranged in the first direction X. At least one column of first pixel circuits10is arranged between two adjacent columns of second pixel circuits20. In the present disclosure, the column direction and the row direction can be interchanged. For example, the plurality of first pixel circuits may also include a plurality of rows of first pixel circuits, and the plurality of second pixel circuits may include a plurality of rows of second pixel circuits.

For example, the same amount of columns of first pixel circuits10can be arranged between any two adjacent columns of second pixel circuits20, so that the arrangement of pixel circuits can be uniform. For example, eight columns of first pixel circuits10are arranged between any two adjacent columns of second pixel circuits20. For example, different amount of columns of first pixel circuits10can be arranged between any two adjacent columns of second pixel circuits20.

For example, as shown inFIG.14, from a left boundary between the third sub-display region A21and the target sub-display region A110as a starting position, the pixel circuits in a second column and the pixel circuits in a twelfth column to the left may both be the second pixel circuits20. For example, the second pixel circuits20in the added columns below the second display region A2may be dummy columns, which are not connected with any light-emitting elements.

FIG.15is a schematic diagram of the connection between the second light-emitting element of the third sub-display region and the second pixel circuit of the target sub-display region located at one side of the third sub-display region. As shown inFIG.1toFIG.15, the added columns of pixel circuits, that is, the second pixel circuits20, and the second light-emitting element40can be connected by the conductive line L1, and the stacked layers of the conductive line L1can be flexibly adjusted according to the radius of a light transmission hole. For example, as shown inFIG.15, the conductive line L1in the display panel may include three conductive line layers, such as a first conductive line L11(for example, ITO1), a second conductive line L12(for example, ITO2) and a third conductive line L13(for example, ITO3).

For example, as shown inFIGS.1to15, each third sub-display region A21may include k light-emitting element groups. Each light-emitting element group may include a plurality of columns of second light-emitting elements40, and a first light-emitting element group to a k-th light-emitting element group may be sequentially arranged along a direction indicated by an arrow in the X direction. For example, each target sub-display region A110includes k pixel circuit groups which are in one-to-one correspondence with k light-emitting element groups Z0. Each pixel circuit group may include a plurality of columns of second pixel circuits20, and the first pixel circuit group to the k-th pixel circuit group may be sequentially arranged in a direction opposite to the direction indicated by the arrow in the X direction.

For example, the above k can be an integer greater than 0. For example, the embodiment shown inFIG.15is illustrated by taking k as 4, but is not limited thereto, and k may be less than 4 or more than 4. For example, each of the first light-emitting element group Z01to third light-emitting element group Z03may include thirteen columns of second light-emitting elements40. A fifth light-emitting element group Z04may include five columns of second light-emitting elements40. For example, each of the first pixel circuit group Z11to the third pixel circuit group Z13may include thirteen columns of second pixel circuits20. The fifth pixel circuit group Z14may include five columns of second pixel circuits20.

For example, as shown inFIGS.1to15, in the third sub-display region A21, the first light-emitting element group Z01includes the first column of second light-emitting elements40to the thirteenth column of second light-emitting elements40(i.e., R1to R13); the second light-emitting element group Z02includes the fourteenth column of second light-emitting elements40to the twenty-sixth column of second light-emitting elements40(i.e., R14to R26); the third light-emitting element group Z03includes the twenty-seventh column of second light-emitting elements40to the thirty-ninth column of second light-emitting elements40(i.e., R27to R39); the fourth light-emitting element group Z04includes the fortieth column second light-emitting elements40to the forty-fourth column second light-emitting elements40(i.e., R40to R44).

For example, in the target sub-display region A110, the first pixel circuit group Z11includes the first column of second pixel circuits20to the thirteenth column of second pixel circuits20(i.e., P1to P13); the second pixel circuit group Z12includes the fourteenth column second pixel circuit20to the twenty-sixth column second pixel circuit20(i.e., P14to P26); the third pixel circuit group Z13includes the twenty-seventh column second pixel circuit20to the thirty-ninth column second pixel circuit20(i.e., P27to P39); the fourth pixel circuit group Z14includes the fortieth column second pixel circuit20to the forty-fourth column second pixel circuit20(i.e., P40to P44).FIG.15does not show the first pixel circuit10and the first light-emitting element30.

For example, each second light-emitting element40in each light-emitting element group and each second pixel circuit20in a corresponding pixel circuit group may be connected by the first conductive line L11, the second conductive line L12and/or the third conductive line L13.

For example,FIG.16is a distribution diagram of some conductive lines in the display panel shown inFIG.15. As shown inFIG.15andFIG.16, for example, taking the case that each row of pixels is provided with at most thirteen conductive lines L (the number of conductive lines L is limited by the width of the conductive lines L and a size of a pixel) as an example, then each row of pixels in the display panel can be provided with thirteen first conductive lines L11, thirteen second conductive lines L12or thirteen third conductive lines L13, and the conductive lines in the same layer cannot overlap, and some conductive lines in different layers can be connected through via holes.

For example, as shown inFIGS.15to16, the second light-emitting element in the first light-emitting element group Z01is connected with the second pixel circuit in the first pixel circuit group Z11through the first conductive line L11; the second light-emitting element in the second light-emitting element group Z02is connected with the second pixel circuit in the second pixel circuit group Z12through the second conductive line L12; the second light-emitting element in the third light-emitting element group Z03is connected with the second pixel circuit in the third pixel circuit group Z13through the third conductive line L13; in the fourth light-emitting element group Z04, some second light-emitting elements are connected with the corresponding second pixel circuits in the fourth pixel circuit group Z14through the first conductive line L11, some second light-emitting elements are connected with the corresponding second pixel circuits in the fourth pixel circuit group Z14through the second conductive line L12, and some second light-emitting elements are connected with the corresponding second pixel circuits in the fourth pixel circuit group Z14through the third conductive line L13.

For example, one row of second light-emitting elements in the first light-emitting element group Z01is connected with one row of second pixel circuits in the first pixel circuit group Z11through thirteen first conductive lines L11; one row of second light-emitting elements in the second light-emitting element group Z02is connected with one row of second pixel circuits in the second pixel circuit group Z12through thirteen second conductive lines L12; and one row of second light-emitting elements in the third light-emitting element group Z03is connected with one row of second pixel circuits in the third pixel circuit group Z13through thirteen third conductive lines L13.

For example, as shown inFIG.16, the first conductive line L11connected with some second light-emitting elements in the fourth light-emitting element group Z04passes through the second light-emitting element group Z02, a part of a region where the third light-emitting element group Z03and a part of a region where the fourth light-emitting element group Z04are located; the second conductive line L12connected with some second light-emitting elements in the fourth light-emitting element group Z04passes through a part of the region where the third light-emitting element group Z03is located and a part of the region where the fourth light-emitting element group Z04is located; the third conductive line L13connected with some second light-emitting elements in the fourth light-emitting element group Z04passes through a part of the region where the fourth light-emitting element group Z04is located. The positions of the conductive lines L11˜L13connected with the second light-emitting elements in the fourth light-emitting element group Z04should be set so that there are at most thirteen conductive lines in adjacent row of pixels.FIG.16only schematically shows the arrangement of some conductive lines connected with the light-emitting elements in the half region of the second display region. The conductive lines connected with the light-emitting elements in the other half region of the second display region and the conductive lines connected with the light-emitting elements in the half region shown inFIG.16are symmetrically distributed with a center line of the second display region extending in the Y direction as the central axis.

In the research, the inventor of the present application found that, as shown inFIGS.15and16, taking the space where the conductive lines connected with the first light-emitting element group Z01to the third light-emitting element group Z03are located as a main trace region, the conductive lines connecting the second light-emitting element in the fourth light-emitting element group Z04and the fourth pixel circuit group Z14are routed from the space above or below the main trace region without crossing the main trace region. The lengths of the part of conductive lines (L11& L12& L13) are significantly larger than those of the conductive lines (for example, the first conductive line L11) located in the main trace region.

As shown inFIGS.15and16, the distance between the second light-emitting elements R1to R44located in the second display region in the X direction is small (i.e., the distance between the second light-emitting elements in adjacent columns is small), the distance between the second light-emitting elements R1and R44is small, while the distance between the pixel circuits P1to P44in the added columns connected with the second light-emitting elements R1to R44are large in the row direction (i.e., the distance between the second pixel circuits in adjacent columns is large). Then the distance between the second pixel circuit P1and the second pixel circuit P44is large, thereby resulting in that the line length (the shortest line length) of the conductive line connecting the second light-emitting element R1and the second pixel circuit P1is much smaller than the line length (the longest line length) of the conductive line connecting the second light-emitting element R44and the second pixel circuit P44. For example, the ratio of the shortest line length to the longest line length can range from 2% to 4%. Therefore, the line length of the conductive line connecting the second light-emitting element R44and the second pixel circuit P44is very long, and it has a great resistance. Moreover, the excessive difference between the shortest line length and the longest line length will lead to excessive resistance difference among different conductive lines, which will affect the display effect of the second display region.

The embodiment in the present disclosure provides a display panel and a display device, the display panel includes a base substrate. The display panel includes a first display region and a second display region, the second display region is on at least one side of the first display region in a first direction, the first display region includes a plurality of first light-emitting units on the base substrate, and the second display region includes a plurality of second light-emitting units, a plurality of first pixel circuits and a plurality of second pixel circuits on the base substrate, at least one of the plurality of first pixel circuits is between adjacent second pixel circuits, at least one of the plurality of first pixel circuits is connected with at least one of the plurality of first light-emitting units, and at least one of the plurality of second pixel circuits is connected with at least one of the plurality of second light-emitting units. The display panel also includes a plurality of traces on the base substrate and configured to connect the first pixel circuit and a corresponding first light-emitting unit. The first display region includes a plurality of regions arranged along the first direction, the plurality of regions include a first region and a second region, the second display region includes a third region and a fourth region arranged along the first direction, a first light-emitting unit in the first region is connected with a first pixel circuit in the third region, a first light-emitting unit in the second region is connected with a first pixel circuit in the fourth region, the fourth region is on a side of the third region close to the first display region, and the first region is on a side of the second region close to the second display region. According to the embodiment of the present disclosure, by setting the position of the first pixel circuit connected with the first light-emitting unit in the first display region, the length difference of the traces connecting a plurality of first light-emitting units and a plurality of first pixel circuits can be reduced as much as possible, and the resistance difference of traces with different lengths can be reduced, thereby improving the display effect of the display panel.

The display panel and display device provided by the embodiments of the present disclosure are described below with reference to the drawings.

FIG.17is a partial plane structure diagram of a display panel provided by an embodiment of the present disclosure, andFIG.18is a partial plane structure diagram of the display panel shown inFIG.17. As shown inFIGS.17and18, the display panel includes a base substrate01. The display panel includes a first display region100and a second display region200, and the second display region200is located on at least one side of the first display region100in the first direction. The embodiment of the present disclosure takes the X direction shown inFIG.17as the first direction. For example, the second display region200is located on both sides of the first display region100in the first direction. The first display region100includes a plurality of first light-emitting units110on the base substrate01, and the second display region200includes a plurality of second light-emitting units120, a plurality of first pixel circuits210and a plurality of second pixel circuits220on the base substrate01. In the first direction, at least one second pixel circuit220is arranged between two adjacent first pixel circuits210, at least one of the plurality of first pixel circuits210is connected with at least one of the plurality of first light-emitting units110, and at least one of the plurality of second pixel circuits220is connected with at least one of the plurality of second light-emitting units120. The display panel further includes a plurality of traces300located on the base substrate01, and the plurality of traces300are configured to connect the first pixel circuit210and the corresponding first light-emitting unit110. Here, the trace300and the conductive line L1in the display panel shown inFIGS.1to16play a role in connecting the first light-emitting unit and the first pixel circuit located in different regions.

As shown inFIGS.17and18, the first display region100includes a plurality of regions arranged in a first direction, the plurality of regions includes a first region410and a second region420, and the second display region20includes a third region430and a fourth region440arranged in the first direction. The first light-emitting unit110in the first region410is connected with the first pixel circuit210in the third region430, the first light-emitting unit110in the second region420is connected with the first pixel circuit210in the fourth region440, the fourth region440is located on a side of the third region430close to the first display region100, and the first region410is located on a side of the second region420close to the second display region200. According to the embodiment of the present disclosure, by setting the position of the first pixel circuit connected with the first light-emitting unit in the first display region, the length difference of the traces connecting the plurality of first light-emitting units and the plurality of first pixel circuits can be reduced as much as possible, and the resistance difference of traces with different lengths can be reduced, thereby improving the display effect of the display panel.

The first display region100in the embodiment of the present disclosure may have the same position distribution as the second display region A2inFIGS.1to12, and the second display region200in the embodiment of the present disclosure may have the same position distribution as the first display region A1inFIGS.1and12. Therefore, The first light-emitting unit110, the first pixel circuit210, the second light-emitting unit120and the second pixel circuit220in the embodiment of the present disclosure have the same position distribution as the second light-emitting element40, the second pixel circuit20, the first light-emitting element30and the first pixel circuit10in the display panel shown inFIGS.1to12, respectively. For example, the plurality of second pixel circuits include a plurality of columns of second pixel circuits extending in a second direction intersecting the first direction and arranged in the first direction, and the plurality of first pixel circuits include a plurality of columns of first pixel circuits extending in the second direction and arranged in the first direction; at least one column of second pixel circuits is distributed between two adjacent columns of first pixel circuits, that is, both the first pixel circuits and the second pixel circuits in the embodiment of the present disclosure are compressed pixel circuits.

The connection relationship between the second light-emitting unit120and the second pixel circuit220in the embodiment of the present disclosure is the same as that between the first light-emitting element30and the first pixel circuit10in the display panel shown inFIGS.1to12. Each light-emitting unit in the embodiment of the present disclosure can also be called a light-emitting element, and can have the same structure as the light-emitting elements shown inFIGS.1to16. For example, the light-emitting unit includes a first electrode, a light-emitting layer, and a second electrode which is located on a side of the light-emitting layer facing the base substrate, and the second electrode of the light-emitting unit is configured to be connected with a pixel circuit. For example, the light-emitting unit may include a blue light-emitting unit, a red light-emitting unit, and a green light-emitting unit. The shape of the light-emitting unit in the first display region of the embodiment of the present disclosure (including the shape of the light-emitting region and the shape of the second electrode) may be the same as the shape of the light-emitting elements with the same color in the second display region of the display panel shown inFIGS.1to16(including the shape of the light-emitting region and the shape of the second electrode), and the description thereof will not be repeated herein again.

The above-mentioned “light-emitting region” may refer to a two-dimensional planar region parallel to the base substrate. For example, the display panel further includes a pixel defining layer on the base substrate, which includes an opening for defining the light-emitting region of the light-emitting unit, the opening exposes the second electrode of the light-emitting unit. In the case where at least part of the light-emitting layer of the light-emitting unit is formed in the opening of the pixel defining layer, the light-emitting layer located in the opening is in contact with the second electrode, so that this part can drive the light-emitting layer to emit light to form the light-emitting region. For example, an orthographic projection of the light-emitting region on the base substrate is approximately coincident with an orthographic projection of the opening of the corresponding pixel defining layer on the base substrate. For example, the orthographic projection of the light-emitting region on the base substrate completely falls within the orthographic projection of the opening of the corresponding pixel defining layer on the base substrate, and the two shapes are similar. The projection area of the light-emitting region on the base substrate is slightly smaller than that of the opening of the corresponding pixel defining layer on the base substrate.

As shown inFIGS.17to18, the connection relationship between the first light-emitting unit120and the first pixel circuit210in the embodiment of the present disclosure is at least partially different from the connection relationship between the second light-emitting element40and the second pixel circuit20in the display panel shown inFIGS.15to16.

For the display panel shown inFIG.15toFIG.16, the pixel circuit layout shown inFIG.7is the pixel circuit layout where the first pixel circuit10is connected with the first light-emitting element30, while the second pixel circuit20and the second light-emitting element40need to be connected by a conductive line, such as an ITO trace, which is equivalent to that the resistance of the ITO trace is formed at the connection between the second light-emitting element40and the second pixel circuit30, or the load formed by the resistance of the ITO trace and parasitic capacitance generated by the ITO trace and other film structures are formed at the connection between the second light-emitting element40and the second pixel circuit30. Therefore, for the second display region of the display panel shown inFIGS.15to16, the length of each conductive line and the length difference of different conductive lines will have a great influence on the display effect.

For example, the plurality of traces300include transparent traces. For example, the material of the transparent trace may include indium tin oxide (ITO), indium gallium zinc oxide (IGZO) or indium zinc oxide (IZO).

For example, as shown inFIGS.17and18, the plurality of traces300include a plurality of traces distributed in different layers, and the plurality of traces distributed in different layers sequentially include a first trace layer310, a second trace layer320, and a third trace layer330in the direction perpendicular to the base substrate01, the first trace layer310is located between the second trace layer320and the base substrate01. The first trace layer310in the display panel shown inFIGS.17and18may be the same layer as the first conductive line L11in the display panel shown inFIGS.15and16, the second trace layer320in the display panel shown inFIGS.17and18may be the same layer as the second conductive line L12in the display panel shown inFIGS.15and16, and the third trace layer330in the display panel shown inFIGS.17and18may be the same layer as the third conductive line L13in the display panel shown inFIGS.15and16.

For example, as shown inFIGS.17and18, the plurality of regions further include a fifth region450and a sixth region460, the fifth region450is located on a side of the first region410close to the second display region200, the sixth region460is located between the first region410and the second region420, and the first light-emitting unit110of the fifth region450is connected with the first trace layer310. The first light-emitting unit110of the first region410is connected with the second trace layer320, the first light-emitting unit110of the sixth region460is connected with the third trace layer330, the first light-emitting unit110of the second region420is connected with at least one of the first trace layer310, the second trace layer320and the third trace layer330, and the second region420is the farthest one from the second display region200among the plurality of regions.

Compared with the display panel shown inFIG.15in which the fourth light-emitting element group farthest from the first display region and the fourth pixel circuit group farthest from the second display region are connected, the first pixel circuit connected with the first light-emitting unit in the second region farthest from the second display region is set in the fourth region, and the fourth region is located on a side of the third region facing the first display region, that is, the fourth region is not the farthest region from the first display region. Therefore, the length of the trace connected with the first light-emitting unit in the farthest region from the second display region can be reduced, and the resistance of this part of trace can be further reduced. For example, the parasitic capacitance generated by this part of trace and other film structures can also be reduced, and the display effect of the first display region can be improved.

It should be noted that the second display region200shown inFIG.17includes a first sub-display region201and a second sub-display region202. The first pixel circuit210provided in the first sub-display region201is configured to be connected with the first light-emitting unit110, while the first pixel circuit210provided in the second sub-display region202may be a dummy pixel circuit, which is not connected with the first light-emitting unit110.FIG.18shows only a part of the first display region, which is a quarter of the complete first display region100(one of the four regions divided by two central axes in the X direction and the Y direction in the first display region), such as the upper left corner of the complete first display region100. The connection relationship between the first light-emitting units in the other three quarters of the first display region and the first pixel circuits in the second display region is the same as the connection relationship between the first light-emitting units in the quarter of the first display region and the first pixel circuits in the second display region.

For example,FIG.19is a schematic plan view of the second electrode and the first conductive layer of the light-emitting unit at a junction position of the first display region and the second display region on the display panel, andFIG.20is a schematic plan view of the first conductive layer at the junction position of the first display region and the second display region in the display panel shown inFIG.19. As shown inFIGS.19and20, the display panel includes a first conductive layer500, which may be located on the side of the second electrode of the light-emitting unit facing the base substrate. For example, the display panel further includes a second conductive layer where data lines and power signal lines are located, a third conductive layer where gate lines are located, and a semiconductor layer where channels of transistors are located. The third conductive layer is located on a side of the semiconductor layer away from the base substrate, the second conductive layer is located on a side of the third conductive layer away from the base substrate, and the first conductive layer500is located between the second conductive layer and the second electrode of the light-emitting unit.

For example, the first conductive layer500includes a conductive electrode501, which can be connected with the power signal line to be supplied with a constant voltage, and the conductive electrode501can be used to shield the influence of the trace300on the potential of the driving transistor T1.

For example, as shown inFIGS.19and20, the first conductive layer500further includes a first connection portion502configured to connect the second electrode of the second light-emitting unit with the second light-emitting control transistor T5of the second pixel circuit. The first conductive layer500further includes a second connecting portion503configured to connect the second light-emitting control transistor T5of the first pixel circuit with the trace300. For example, the above-mentioned first connection portion is provided in the first pixel circuit configured to be connected with the first light-emitting unit. For example, in the case where the indium tin oxide (ITO) is used as the material of the trace, the first transfer portion can also be called an ITO transfer portion.

For example, as shown inFIGS.19and20, the first conductive layer500further includes a light shielding portion03surrounding the first display region to reduce the influence of diffraction on the lens provided in the first display region. For example, the light shielding portion03may be connected with a power signal.

For example, as shown inFIGS.19and20, the boundary between the first display region100and the second display region200may be a stepped boundary line02as shown in the figure, and the step width (i.e., the size along the X direction) and the step height (i.e., the size along the Y direction) at the boundary line between the first display region100and the second display region200may be arbitrarily set, for example, the step width may be an integer multiple of the sum of the widths of four light-emitting units (e.g., D01as shown inFIG.6), that is, 31.6*4*N(N=1, 2, 3 . . . ), and the step height can be an integer multiple of the sum of the heights of two light-emitting units (e.g., D02shown inFIG.6), that is, 63.2*2*N(N=1, 2, 3 . . . ).

For example, as shown inFIGS.19and20, at least one column of added-column pixel circuits located between the first column of first pixel circuits P1near the first display region100in the second display region200and the first display region100is further provided. The at least one column of added-column pixel circuits is not provided with the above-mentioned first connection portion and is not connected with the first light-emitting unit through the trace, and the at least one column of added-column pixel circuits is a dummy pixel circuit. For example, the dummy pixel circuit is arranged around the first display region to improve the etching uniformity around the first display region.

FIG.21is a schematic plan view of a first conductive layer and a first trace layer at a junction position of the first display region and the second display region,FIG.22is a schematic plan view of a first trace layer at a junction position of the first display region and the second display region, andFIG.23is a schematic plan view of a first trace layer in a region, away from the first display region, in the second display region. As shown inFIGS.21to23, the film layer where the trace is located (including at least one of the first trace layer, the second trace layer and the third trace layer) includes an anode connection portion311, and the anode connection portion311located in the first display region is configured to connect the trace300with the second electrode of the first light-emitting unit.

For example, as shown inFIGS.21to23, the trace300connected with some of the first light-emitting units in one of the plurality of regions farthest from the second display region200(e.g., the second region420) includes a main portion301extending in the first direction and an edge portion302extending in the first direction, for example, the edge portion302is located on at least one side of the main portion301in the first direction. For example, the main portion301and the edge portion302are located on different straight lines, the length of the main portion301is longer than the length of the edge portion302, and the main portion301passes through the second display region200. For example, the edge portion302extends to the corresponding pixel circuit and is connected with the pixel circuit. For example, the main portion301and the edge portion302may be connected by a line segment extending in the Y direction.

For example, the circular boundary04shown inFIG.22may be the boundary of the first display region, and the shape of the first display region is circular, but is not limited thereto, and the first display region may have other shapes.

Compared with the display panel shown inFIG.16, in which the conductive traces connected with the light-emitting elements in the farthest region from the first display region A1in the second display region A2are routed from the uppermost side or the lowermost side and then connected with the corresponding pixel circuits in the first display region, in the embodiment of the present disclosure, some of the traces connected with the light-emitting elements in the farthest region from the second display region in the first display region directly pass through the second display region, instead of bypassing the second display region from the uppermost side or the lowermost side and connecting with the corresponding pixel circuit, it can reduce the partial trace lengths of a plurality of trace lines connected with the light-emitting units in the area farthest from the second display region in the first display region, and further improve the display effect of the second display region.

For example, as shown inFIGS.17and18, the ratio of the length of the longest trace300in the second trace layer320connected with the first light-emitting unit110in the first region410to the length of the longest trace300connected with the first light-emitting unit110in the second region420ranges from 0.8 to 1.2, which can reduce the parasitic capacitance on the whole trace layer and improve the display effect of the second display region. For example, the ratio of the length of the longest trace300in the second trace layer320connected with the first light-emitting unit110in the first region410to the length of the longest trace300connected with the first light-emitting unit110in the second region420ranges from 0.9 to 1.1. For example, the length of the longest trace300in the second trace layer320connected with the first light-emitting unit110in the first region410is not less than that of the longest trace300connected with the first light-emitting unit110in the second region420.

For example, in the direction perpendicular to the base substrate, the overlapping area between the first trace layer and the third trace layer is large, and the first trace layer has a certain overlapping area with the film layers such as the first conductive layer on the side away from the third trace layer, so the first trace layer has a large parasitic capacitance; in the direction perpendicular to the base substrate, the overlapping area between the second trace layer and the first trace layer, and the overlapping area between the second trace layer and the third trace layer are both very small, so the second trace layer has a small parasitic capacitance. According to the size relationship between the parasitic capacitance on the first trace layer and the second trace layer, the average length of the trace in the second trace layer is set to be larger than that of the trace in the first trace layer, which can reduce the parasitic capacitance on the whole trace layer.

For example, as shown inFIGS.17to18, the ratio of the average length of the traces300connecting the first light-emitting units110in the second region420and the first pixel circuits210in the fourth region440to the average length of the traces300connecting the first light-emitting units110in the first region410and the first pixel circuits210in the third region430may range from 0.7 to 1.3. For example, the ratio of the average length of the traces300connecting the first light-emitting units110in the second region420and the first pixel circuits210in the fourth region440to the average length of the traces300connecting the first light-emitting units110in the first region410and the first pixel circuits210in the third region430may range from 0.9 to 1.1. For example, the ratio of the length of the longest trace among the traces300connecting the first light-emitting units110in the second region420and the first pixel circuits210in the fourth region440to the length of the longest trace among the traces300connecting the first light-emitting units110in the first region410and the first pixel circuits210in the third region430may range from 0.7 to 1.3. For example, the ratio of the length of the longest trace among the traces300connecting the first light-emitting units110in the second region420and the first pixel circuits210in the fourth region440to the length of the longest trace among the traces300connecting the first light-emitting units110in the first region410and the first pixel circuits210in the third region430may range from 0.9 to 1.1.

Compared with the trace mode in the display panel shown inFIGS.15and16, on the one hand, the embodiment of the present disclosure reduces the length of the trace connected with the light-emitting unit in the region farthest from the second display region; on the other hand, in the embodiment of the present disclosure, the longest trace among the plurality of traces connecting the light-emitting units in the first region and the pixel circuits in the third region is set as the longest trace in the display panel, and the ratio of the length of the longest trace to the length of the trace connecting the light-emitting units in the region farthest from the second display region ranges from 0.8 to 1.2. Therefore, the length of the longest trace in the embodiment of the present disclosure is also smaller than that in the display panel shown inFIGS.15and16. In the display panel provided by the embodiment of the present disclosure, by adjusting the position of the first pixel circuits connected with the first light-emitting units in some regions, the longest length of the trace connecting the first light-emitting unit and the first pixel circuit can be effectively reduced, and the resistance and parasitic capacitance of the trace can be reduced, thereby improving the display effect of the second display region.

For example, as shown inFIGS.17and23, the second display region200further includes a seventh region470. The first light-emitting units110in the fifth region450are connected with the first pixel circuits210in the seventh region470through a plurality of third traces3300in the first trace layer310, and the seventh region470is located on the side of the fourth region440facing the first display region100.

For example, the seventh region470is not the region closest to the first display region100in the second display region200, other regions may be provided between the seventh region470and the first region100.

In the embodiment of the present disclosure, the first pixel circuit connected with the first light-emitting unit in the region closest to the second display region is not arranged in the region closest to the first display region, so that the length of the shortest trace among traces can be increased as much as possible, the length difference between the longest trace and the shortest trace among the plurality of traces can be further reduced, the numerical range of the trace resistance can be reduced, and the display effect of the first display region can be improved.

For example, in the embodiment of the present disclosure, among the plurality of traces, the length ratio of the longest trace to the shortest trace ranges from 8% to 20%. For example, among the plurality of traces, the length ratio of the longest trace to the shortest trace ranges from 10% to 15%.

For example, in the embodiment of the present disclosure, the distance between the seventh region470and the first display region100cannot be set too large because the parasitic capacitance of the traces in the first trace layer310is larger than that in other trace layers. For example, the number of columns of effective first pixel circuits210arranged between one column of the first pixel circuits210in the seventh region470closest to the first display region100and the first display region100is no more than 10 columns. For example, the number of columns of the effective first pixel circuits210arranged between one column of the first pixel circuits210in the seventh region470closest to the first display region100and the first display region100is no more than 5 columns. The above-mentioned “effective first pixel circuit” refers to a pixel circuit configured to be connected with the first light-emitting unit.

For example, as shown inFIGS.17to23, some of the first light-emitting units110in the second region420are connected with the corresponding first pixel circuits210in the fourth region440through a plurality of fourth traces3400located in the first trace layer310. The plurality of fourth traces3400located in the first trace layer310include a plurality of first sub-traces3410and a plurality of second sub-traces3420. A portion extending along the first direction of the first sub-traces3410passes through the display region in the seventh region470to connect with the first pixel circuit210located in the fourth region440, and the plurality of second sub-traces3420bypass the seventh region470to connect with the pixel circuits located in the fourth region440.

For example, as shown inFIGS.17to23, the display panel includes a central axis region C extending in the first direction and passing through the center of the first display region, the traces connected with the first light-emitting units in the fifth region450do not pass through the central axis region C, and the first sub-traces3410passing through the seventh region470include a portion passing through the central axis region C, and a portion interspersed among the plurality of third traces300(i.e., portions passing through a region where the third traces300are located). However, the second sub-trace3420is not interspersed among the plurality of third traces3300, and is connected with the first pixel circuit210in the fourth region440after bypassing the upper edge (or lower edge) of the third traces3300by winding.

For example, an amount of the second sub-traces3420is greater than an amount of the first sub-traces3410. For example, most of the fourth traces3400connected with the first light-emitting units in the second region420are routed above (or below) the trace region where the third trace3300is located, and a few traces are routed from the trace region where the third trace3300is located and the central axis region.

For example, an amount of the first sub-traces3410passing through a side of the central line extending in the first direction of the central axis region C may be six. For example, an amount of the first sub-traces3410passing through both sides of the center line extending in the first direction of the center axis region C may all be six.

Compared with the display panel shown inFIG.15andFIG.16, in which the first conductive lines connected with the light-emitting elements in the farthest region from the first display region are connected with the corresponding pixel circuits by winding (instead of being inserted in the trace region). In this embodiment of the present disclosure, some of the fourth traces are inserted among the plurality of third traces, and even some of the fourth traces are arranged to pass through the central axis region, which can effectively reduce the length of some of the fourth traces to reduce the resistance of some of the fourth traces.

For example, as shown inFIGS.17to23, because the traces300(fourth traces3400) connected with some of the first light-emitting units110in the second region420and the traces300(third traces3300) connected with the first light-emitting units110in the fifth region450are both located in the first trace layer310, and the fourth region430is located on a side of the seventh region470away from the first display region100, the second region420is located on the side of the fifth region450away from the second region200. In order to realize the connection between the fourth trace3400and the first pixel circuit210of the fourth region440, it is necessary to set one region between the fourth region440and the seventh region470to realize the winding of some of the fourth trace3400.

For example, as shown inFIGS.17to23, an eighth region480is arranged between the fourth region440and the seventh region470, and the plurality of second sub-traces3420bypass the edge of the seventh region470and are connected with the first pixel circuits210located in the fourth region440through the eighth region480.

FIG.24is a schematic plan view of a first conductive layer and a second trace layer at a junction position of the first display region and the second display region on the display panel;FIG.25is a schematic plan view of a second trace layer at a junction position of the first display region and the second display region on the display panel;FIG.26is a schematic plan view of the second trace layer in the third region; andFIG.27is a schematic plan view of the second trace layer in the fourth region. As shown inFIGS.17to18and24to27, the first light-emitting units110in the first region410are connected with the first pixel circuits210in the third region430through the plurality of first traces3100in the second trace layer320, and some of the first light-emitting units110in the second region420are connected with the corresponding first light-emitting units in the fourth region440through the plurality of second traces3200in the second trace layer320.

For example, as shown inFIGS.17-18and24-27, the first region410includes a first central region431extending in the first direction and first edge regions432on both sides of the first central region431in the second direction, the first trace3100is located in the first edge region432and the second trace3200is located in the first central region431. For example, the first central region431is a partial region of the central axis region shown inFIG.23. For example, the second direction may be the Y direction, and the second direction intersects the first direction. The embodiment of the present disclosure is not limited thereto, and the first direction and the second direction can be interchanged.

For example, as shown inFIGS.17-18and24-27, a part of traces (the second traces3200) in the second trace layer320are arranged in a trace pattern extending in the first direction and arranged in the second direction, and another part of traces (the first traces3100) in the second trace layer320passes through the central axis region.

Compared with the display panel shown inFIGS.15and16, where the second conductive lines connected with the light-emitting elements in the farthest region from the first display region are connected with the corresponding pixel circuits by winding (instead of penetrating through the trace region), in the embodiment of the present disclosure, the second trace is set to pass through the central axis region, so that the length of the second trace can be reduced, the resistance and parasitic capacitance of the second trace can be reduced, and the display effect of the first display region can be improved.

For example, as shown inFIGS.24to27, an amount of the second traces3200located on a side of the center line extending in the first direction of the first central region431may be six. For example, an amount of the second traces3200located on both sides of the center line extending in the first direction of the first central region431may be six.

For example, as shown inFIGS.17to18and24to27, the first conductive layer500(located on a side of the first trace layer310facing the base substrate01) further includes a transfer line504, and the traces300connected with some of the first light-emitting units110in the second region420are connected with the corresponding first pixel circuits210through the transfer line504. Because the fourth region is located on the side of the third region facing the first display region, the second region is located on the side of the first region away from the second display region, and the traces connecting the first light-emitting units in the first region are located on the second trace layer, and a part of the traces connecting the first light-emitting units in the second region are also located on the second trace layer, in order to prevent the two parts of traces located in the second trace layer (i.e., the first trace and the second trace) from crosstalk, at least part of the second traces needs to be connected with the first pixel circuit through the transfer line.

For example,FIG.28is a schematic plan view of a third trace layer at a junction position of the first display region and the second display region on the display panel,FIG.29is a schematic plan view of a third trace layer of an eighth region, a fourth region, a tenth region and a part of a seventh region,FIG.30is a schematic plan view of a third trace layer of a second region, a sixth region and a part of a first region; andFIG.31is a schematic plan view of a third trace layer in a fourth region and a part of an eighth region. As shown inFIGS.17to18and28to31, the first light-emitting units110in the sixth region460may be connected with the first pixel circuits210distributed in at least two nonadjacent regions. For example, the at least two nonadjacent regions may include a ninth region490and an eighth region480located on the side of the seventh region470facing the first display region100.

For example, as shown inFIGS.17-18and28-31, first light-emitting units of belong to a first part of the first light-emitting units110in the sixth region460are connected with the corresponding first pixel circuits210in the eighth region480through a plurality of fifth traces3500in the third trace layer330, and some of the first light-emitting units110in the second region420are connected with the corresponding first pixel circuits210in the fourth region through a plurality of sixth traces3600in the third trace layer330.

For example, as shown inFIGS.17to18and28to31, first light-emitting units110belong to a second part of the first light-emitting units110of the sixth region460are connected with the corresponding first pixel circuits210in the ninth region490through the plurality of fifth traces3500in the third trace layer330.

For example, as shown inFIGS.17to18and28to31, the ninth region490includes a second central region491extending in the first direction and second edge regions492on both sides of the second central region491in the second direction. The fifth trace3500is located in the second edge region492, and the sixth trace3600is located in the second central region492. For example, the second central region491is a part of the central axis region shown inFIG.23. For example, the second direction may be the Y direction, and the second direction intersects the first direction. The embodiment of the present disclosure is not limited thereto, and the first direction and the second direction can be interchanged.

For example, as shown inFIGS.17-18and28-31, part of traces (the fifth trace3500) in the third trace layer330are arranged in a trace pattern extending in the first direction and arranged in the second direction, and another part of traces (the sixth trace3600) in the third trace layer330pass through the central axis region.

Compared with the display panel shown inFIGS.15and16, the third conductive line connected with the light-emitting element in the farthest region from the first display region is connected with the corresponding pixel circuit by winding (instead of penetrating the trace region). In this embodiment of the present disclosure, the sixth trace is set to pass through the central axis region, which can reduce the length of the sixth trace, reduce the resistance and parasitic capacitance of the sixth trace, and it is beneficial to improve the display effect of the first display region.

For example, as shown inFIGS.28to31, an amount of the sixth traces3600located on a side of the center line extending in the first direction of the second central region491may be six. For example, an amount of the sixth traces3600located on both sides of the center line extending in the first direction of the second central region491may be six.

For example, as shown inFIGS.17to18and28to31, the second display region200further includes a tenth region4100located between the fourth region440and the third region430, and first light-emitting units belong to a third part of the first light-emitting units110of the sixth region460are connected with the corresponding first pixel circuits210located in the tenth region4100through the plurality of fifth traces3500located in the third trace layer330.

For example, the tenth region is located on a side of the fourth region away from the first display region, the sixth region is located on a side of the second region close to the second display region, and the trace connecting the first light-emitting unit in the tenth region is located on the third trace layer, and the traces connecting some of the first light-emitting units in the second region are located on the third trace layer. In order to prevent the crosstalk between these two parts of traces (i.e., the fifth traces and the sixth traces) in the third trace layer, at least part of the third trace needs to be connected with the first pixel circuit through the transfer line504.

For example, as shown inFIGS.17to31, at least one selected from the group consisting of the third region430, the fourth region440, the seventh region470, the eighth region480, the ninth region490and the tenth region4100has no more than 18 columns of the first pixel circuits210configured to be connected with the first light-emitting units110. For example, an amount of columns of the first pixel circuits in the above region can be determined according to the distance between two adjacent rows of ITO transfer portions. For example, at least one selected from the group consisting of the third region430, the fourth region440, the seventh region470, the eighth region480, the ninth region490, and the tenth region4100has no more than 13 columns of the first pixel circuits210configured to be connected with the first light-emitting units110.

For example, as shown inFIGS.17to31, the embodiment of the present disclosure schematically shows that the second display region200includes 44 columns of first pixel circuits, and the first display region10includes 44 columns of first light-emitting units, but is not limited thereto. The second display region200includes 48 columns of first pixel circuits, and the first display region10includes 48 columns of first light-emitting units.

For example, as shown inFIGS.17to31, the ninth region490includes the first pixel circuits210in columns P1to P4, the seventh region470includes the first pixel circuits210in columns P5to P17, the eighth region480includes the first pixel circuits210in columns P18to P21, the fourth region440includes the first pixel circuits210in columns P22to P26, the tenth region4100includes the first pixel circuits210in columns P27to P31, and the third region430includes the first pixel circuits210in columns P32to P44.

For example, as shown inFIGS.17to31, the fifth region450includes first light-emitting units110in columns R1to R13, the first region410includes first light-emitting units110in columns R14to R26, the sixth region460includes first light-emitting units110in columns R27to R39, and the second region420includes first light-emitting units110in columns R40to R44.

For example, as shown inFIGS.17to30, the first display region includes a first central axis CA1extending in the first direction and a second central axis CA2perpendicular to the first central axis CA1, and the traces300connected with the first light-emitting units in at least one of the first region410, the fifth region450, and the sixth region460are symmetrically distributed with the first central axis CA1as the central axis.

For example, the traces300connected with the first light-emitting units110in the first region410, the fifth region450and the sixth region460are all distributed in an axisymmetric manner with the first central axis CA1as the central axis, so that, for example, the space for arranging the second traces3200can be formed between the first traces3100, which are located on both sides of the first central region431in the Y direction and are adjacent to the first central region431, shown inFIG.25, therefore, the second trace3200is prevented from winding from the peripheral regions of the first display region and the second display region, thereby being beneficial to reducing the length of the second trace. For example, as shown inFIG.28, the space for arranging the sixth trace3600can be formed between the fifth traces3500, which are located on both sides of the second central region421in the Y direction and are adjacent to the second central region421, which prevents the sixth trace3600from winding from the peripheral regions of the first display region and the second display region, thus being beneficial to reducing the length of the sixth trace.

For example, the direction indicated by the arrow in the Y direction is upward, and the traces300located above the first central axis CA1, such as the traces300connected with the first light-emitting units in the first region410, the fifth region450and the sixth region460, are routed in an upward folding way; the traces300located below the first central axis CA1, for example, the traces300connected with the first light-emitting units in the first region410, the fifth region450and the sixth region460, are routed in a downward folding way, so that the traces300located above and below the first central axis CA1are respectively folded in directions away from each other to form an axisymmetric distribution, and thus a space can be formed between the first central region431and the second central region491.

For example, the plurality of traces300are symmetrically distributed with the first central axis CA1, and the plurality of traces300are symmetrically distributed with the second central axis CA2, which can facilitate the design of traces. For example, the traces300located in the first edge region432are symmetrically distributed with the first central axis CA1, and the traces300located in the first central region431are also symmetrically distributed with the first central axis CAL For example, the centerline of the first central region431extending in the X direction includes the first central axis CAL

For example, as shown inFIG.17toFIG.31, the first display region100includes a display center region101located in the center, and the plurality of traces300are distributed in a central symmetry about the display center region101. For example, the symmetry center of the plurality of traces300may be located in the center of the display center region or may be offset from the center of the display center region. The above center symmetrical distribution can be set according to actual products. For example, the symmetrical centers of plurality of traces can be determined according to the placement position of the ITO transfer portions. If a horizontal line extending in the first direction through the center of the display center region does not coincide with a central line extending in the first direction of two adjacent rows of ITO transfer portions closest to the horizontal line, the symmetrical centers of plurality of traces will deviate from the center of the display center region, but the traces are basically symmetrical as a whole, that is, the display center region can be distributed as a center symmetrical distribution. Because the pixel circuits and the light-emitting units are not symmetrical, the position of connecting the light-emitting units or the pixel circuits will shift. For example, taking the center of the camera hole under the screen on the center axis of the scree as an example, the length of the trace connecting the first column of light-emitting elements, farthest from the center, in the left half of the first display region with the corresponding pixel circuit is L11, for example, 80 μm, however, the length of the trace connecting the first column of light-emitting elements, farthest from the center, in the right half of the first display region with the corresponding pixel circuits are L12, for example, 190 μm, and L11and L12are different. After connecting the light-emitting elements in the left and right halves of the first display region with the corresponding pixel circuits, the trace lengths on both sides of the trace will be different. For example, each trace in the left half of the first display region will be shorter than each trace in the right half of the second display region, which is mainly because the ITO transfer portions on both sides of the first display region are asymmetric from the central axis of the screen, it can be called that the pixel circuits and the light-emitting units are asymmetric. In the case where the traces are set to be centrosymmetric, although the lengths of the traces are different, the routing trend of the traces is the same. For example, in the case where the center position of the camera hole under the screen is limited to the central axis of the screen, but the positions of the first pixel circuits are not symmetrical about the central axis of the screen, which leads to lengths of left and right traces to be unequal. If the center position of the camera hole is adjusted, the symmetry of the first pixel circuits about the central axis of the hole can be improved to some extent.

In the display panel shown inFIG.15toFIG.16, the conductive lines L1are symmetrically distributed with respect to the center line of the second display region A2extending in the Y direction, and the conductive lines L1connected with the light-emitting elements in the region farthest from the first display region A1bypass the upper part (or the lower part) of the first display region A1to realize winding connection. In the embodiment of the present disclosure, the traces300are distributed roughly symmetrically with respect to the display center region of the first display region100, so that part of the traces connected with the light-emitting units in the region farthest from the second display region can pass through the central axis region, and the lengths of the traces can be effectively reduced to reduce the resistance and parasitic capacitance of the traces, which is conducive to improving the display effect of the first display region.

Another embodiment of the present disclosure provides a display device including the display panel as mentioned above.

For example, the display device provided by the embodiment of the present disclosure may be an organic light-emitting diode display device.

For example, in the display device provided by the embodiment of the present disclosure, by setting the position of the first pixel circuit connected with the first light-emitting unit in the first display region, it is possible to minimize the length difference of the traces connecting the plurality of first light-emitting units and the plurality of first pixel circuits, reduce the resistance difference of traces with different lengths, and further improve the display quality of the second display region (the region where the camera under the screen is located).

For example, the display device may further include a cover on a display side of the display panel. For example, the display device may further include a functional component located on the side of the base substrate away from the light-emitting unit, and the functional component is opposite to the second display region.

For example, the functional components include at least one of a camera module (e.g., a front camera module), a 3D structured light module (e.g., a 3D structured light sensor), a time of flight 3D imaging module (e.g., a time of flight sensor), an infrared sensing module (e.g., an infrared sensor), etc.

For example, the front camera module is usually activated when the user takes a selfie or makes a video call, and the pixel display region of the display device displays the image obtained by the selfie for the user to watch. The front camera module includes a lens, an image sensor, an image processing chip, etc. The optical image generated by the lens of the scene is projected on the surface of the image sensor (the image sensor includes CCD and CMOS) and converted into an electrical signal, which is converted into a digital image signal by the image processing chip, and then sent to the processor for processing, and the image of the scene is output on the display screen.

For example, the 3D structured light sensor and the time of flight (ToF) sensor can be used for face recognition to unlock the display device.

For example, the functional component may only include a camera module to realize the function of selfie or video call; for example, the functional component may further include a 3D structured light module or a time of flight 3D imaging module to realize face recognition unlocking, etc. This embodiment includes but is not limited thereto.

For example, the display device can be any product or component with a display function, such as a mobile phone with an under-screen camera, a tablet computer, a notebook computer, a navigator, etc. This embodiment is not limited thereto.

The following statements should be noted:(1) In the accompanying drawings of the embodiments of the present disclosure, the drawings involve only the structure(s) in connection with the embodiment(s) of the present disclosure, and other structure(s) can be referred to common design(s).(2) In the case of no conflict, features in one embodiment or in different embodiments can be combined.

What have been described above are only specific implementations of the present disclosure, the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be based on the protection scope of the claims.