Patent ID: 12254155

The features and advantages of embodiments of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements.

SUMMARY

A first embodiment of the present invention may be a CDC including a comparator coupled to a sensing electrode and to a reference signal. A capacitive digital-to-analog converter (DAC) may be coupled to the sensing electrode and to the input of the comparator and controlled by a counter coupled to the output of the comparator through a logic circuit. In this embodiment, capacitance change may be detected by a processing circuit by comparing values of the counter from one time to another.

A second embodiment of the present invention may be a CDC including a comparator coupled to a pair of sensing electrodes or other similar inputs. A pair of capacitive DAC may be coupled to the sensing electrode or similar inputs and to the corresponding inputs of the comparator and controlled by a counter coupled to the output of the comparator through a logic circuit. The capacitive DACs may be controlled by complimentary signals. In this embodiment, capacitance change may be detected by a processing circuit by comparing values of the counter from one time to another.

A third embodiment of the present invention may be a method of detecting a change of capacitance on a sensing electrode by first applying a signal to the sensing electrode and then comparing the signal to a reference signal. The applied signal may the be incremented or decremented based on the comparison until a toggle condition is reached, at which time a counter value associated with the signal at which the toggle condition is reached is stored.

DETAILED DESCRIPTION

This specification discloses one or more embodiments that incorporate the features of this invention. The disclosed embodiment(s) merely exemplify the present invention. The scope of the present invention is not limited to the disclosed embodiment(s). The present invention is defined by the claims appended hereto.

The embodiment(s) described, and references in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment(s) described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is understood that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

FIG.1illustrates a capacitive sensing system100for detecting the presence of a conductive object on or in proximity to sensing electrodes101.1-101.4. Capacitive sensing system100may include circuit103including a capacitance-to-digital converter (CDC)110which may be triggered or enabled by timer115, which may also provide clocking and/or control signals to multiplexer120. Multiplexer120may be coupled to an input of CDC110through analog filter125and to input/outputs (I/Os)105.1-105.4of a circuit103. IOs105.1-105.4may be coupled to sensing electrodes101.1-101.4, such that sensing electrodes101.1-101.4are coupled to CDC110though IOs105.1-105.4, multiplexer120, and analog filter125. The output of CDC110may be coupled to digital filter127. In various embodiments, analog filter125and digital filter127may be used to reduce the frequency of false touch or proximity events that may be caused by environmental noise, human body noise, or other system interference. The output of digital filter127may be coupled to a processing circuit (not shown) for processing the output of CDC110.

While four sensing electrodes are illustrated inFIG.1, more or fewer sensing electrodes may be implemented depending on application requirements. Additionally, while the embodiment of capacitance sensing system100illustrates a single CDC for all of the sensing electrodes, different numbers of CDCs may be implemented. In one embodiment, a CDC may be implemented for each sensing electrode. In another embodiment, sensing electrodes may be grouped together and correspond to one of a plurality of CDCs that may be configured to operate simultaneously.

FIG.2illustrates CDC110ofFIG.1in a single-ended asynchronous configuration210(hereafter referred to as CDC210). CDC210may include a comparator220having an input coupled to a reference voltage (VREF) and another input coupled to sensing electrode201having a capacitance, CS. Sensing electrode201may correspond to sensing electrodes101.1-101.4ofFIG.1. In one embodiment, sensing electrode201may be coupled to CDC210through I/O205as described inFIG.1. The input of comparator220coupled to sensing electrode201may also be coupled to a capacitive digital-to-analog converter (CapDAC)225. CapDAC225may include a number of capacitors (C0-2N-1C0) and control circuitry, such that a capacitance of CapDAC225may be changed in response to control signals during operation of CDC210. CapDAC225nat also be referred to as a current DAC or just “DAC.” Outputs of comparator220may be coupled to logic230, which may be coupled to binary counter240. In other embodiments, counters may be used that are not binary. The output (Data) of binary counter240may be coupled to an input of AND gate245for control of CapDAC225if a reset signal (Rst) is not asserted. The values of CapDAC225and the capacitance of the sensing electrode, CS, may yield a signal, VS, on the input of comparator220. VSmay be given by:

VS=D*C0CS+(2N-1)*C0*Vd⁢d=D*C0CS*CD⁢A⁢C*Vd⁢d,
where D is the digital code (Data) provided by the binary counter, C0is the least significant bit (LSB) capacitor, CDACis the total capacitance of CapDAC225, and CSis the capacitance of sensing electrode201.

FIG.3Aillustrates a method301for operating CDC210. Logic230first increments binary counter240in step310, which increases the value of CapDAC225on the input of comparator220. This increases the signal, VS, on the input of comparator220. VSis compared to VREFin step315. If VSis not equal to or greater than VREF, binary counter240is incremented again in step310and the comparison is repeated. If VSis equal to or greater than VREF, binary counter240is decremented in step320. If VStoggles about VREFfor a prescribed number of cycles such that a toggle condition is detected in step325, the binary counter code is stored in step330. If not, the increment/decrement process continues until a toggle condition about VREFis detected and the counter value is stored in step330.

FIG.3Billustrates a method302for detecting the presence or proximity of a conductive object to sensing electrode201. First, the stored value from step330of method301is loaded into binary counter240in step340. If VSis not greater or equal to VREFin step345, binary counter240is incremented in step356and the comparison is repeated. If VSis equal to or greater than VREF, binary counter240is decremented in step354and the comparison is repeated as well. At each stage it is determined if the value of VSis toggling about VREFin step355(a toggle condition is reached). If the counter value upon determination that VSis toggling about VREFis the same as the stored value from step330of method300, no capacitance change is detected in steps365and370. If the change in the binary counter value is greater than a threshold value in step375, a conductive object is detected on or in proximity to the sensing electrode in step380. If the binary counter value is not greater than the threshold in step375, than no conductive object is detected on or in proximity to the sensing electrode in step390. In various embodiments, the newly determined counter value detected after the toggle is detected in step355may be stored and replace the counter value stored in step330of method300. The method ofFIG.3Bmay sore the binary counter value after each conversion, such that CDC210is loaded with the previous binary counter value for the start of each conversion.

FIG.4illustrates a plot400of the signal, VS, on the input of comparator220during operation of CDC210. After the reset signal, Rst, is asserted, VSis incremented through successive operation of the comparator and the binary counter incrementing or decrementing. Once VSreaches VREF, the binary counter is decremented and incremented as VStoggles about VREF. After a certain number of cycles wherein the VStoggles about VREF, the value of the binary counter is stored. In the plot ofFIG.4, once VShas toggled about VREFfour times, the value of the binary counter is stored. While four toggles are illustrated, one of ordinary skill in the art would understand that more or fewer toggles could be used. Fewer toggles may result in faster response, but more toggles will result in better hysteretic control. As stated about, the binary counter value of the previous conversion may be loaded at the start of each conversion. In another embodiment, if a sensor is active (a conductive object is determined to be on or in proximity to the sensing electrode), storing of the binary count value may be suspended to ensure that the conductive object is detected on successive conversion cycles as long as it remains in contact with of proximity to the sensing electrode.

In one embodiment, the CDC210may be used to quantize the sensor capacitance. After a conversion cycle, CS may be given by:
CS=Dout*2*C0−CDAC

FIG.5Aillustrates a differential architecture for a CDC500creating a differential asynchronous CDC. Two sensing electrodes501and502may be coupled to inputs of comparator520through IOs505and506, respectively. In one embodiment, one of the electrodes may be a dummy electrode or a fixed capacitance that is positioned such that its capacitance does not change in proximity to a conductive object (such as a finger). CapDACs525and526may be coupled to the inputs corresponding to sensing electrodes501and502and operate similar to CapDAC225ofFIG.2. CapDAC525may be controlled by a data signal (Data) from binary counter540, while CapDAC526may be controlled by a Data_bar signal from binary counter540. Data_bar may be a complimentary signal to Data, such that the signal added to the inputs of comparator540corresponding to sensing electrodes501and502are opposite.

Logic530coupled to the output of comparator540may form a feedback loop, such that the incrementing and decrementing of the binary counter540forces the signal on the comparator input corresponding to sensing electrode501(VS1) to equal the signal on the comparator input corresponding to sensing electrode502(VS2). VS1and VS2are then equal only at the midcode of binary counter540. If there is a non-zero change in capacitance, the counter code deviates from its midcode by a value proportional to the change in capacitance. This relationship may be given by:

Δ⁢C=Dout[2⁢C0(1+CSCD⁢A⁢C)]-(CD⁢A⁢C+CS),

where DOUTis the output of binary counter540. DOUTmay is represented as “Data” inFIG.5A.

The absolute value of the capacitance change may be derived linearly from the value of the LSB of CapDACs525and526by:

L⁢S⁢B=2⁢C0(1+CSCD⁢A⁢C)

The linearity holds with fully differential signals, +/−ΔC, superimposed on the baseline capacitance of both sensors. That is, the capacitance change (ΔC) on both sensing electrodes is identical. This is infrequent. In many systems the capacitance change from a conductive object in contact with or in proximity to a sensing electrode is greater on one sensing electrode than it is on another. If only buttons are used, the capacitance change may only be present on a single sensing electrode. And if multiple sensing electrodes have conductive objects present on or near them, the physics of each sensing electrode and its environment make it unlikely that the ideal case (perfect linearity) is achieved.

FIG.5Billustrates capacitance and the resultant signals on differential electrodes501and502. After the Rst signal is asserted, voltage, VS1, increases on an input of comparator520and CS1. Voltage VS2increases on the other input of comparator520and CS2. Each signal toggles (reaches a toggle condition) and the binary counter value is stored. If capacitance does not change, the toggle condition is detected right away. If capacitance does change, VS1and VS2are incremented/decremented until the toggle condition is reached again and the binary counter value is stored to for subsequent conversions.

In cases where capacitance changes only for a single sensing electrode, the CDC may operate in a pseudo-differential mode, making the CDC nonlinear. However, the nonlinearity may be negligible when the capacitance change on the sensing electrode is small relative to the total capacitance of the CapDAC.FIGS.6A and6Billustrate the differences in capacitances measured in differential mode and pseudo-differential mode.

FIG.6Aillustrates a differential measurement600by CDC610, where both sensing electrodes601and602coupled to inputs605and605, respectively, have their capacitances changed by ΔC, but in opposite directions such that:

Δ⁢CDo⁢u⁢t∝2⁢C0(1+CSCD⁢A⁢C).

FIG.6Billustrates a pseudo-differential measurement620of CDC620, where only a single sensing electrode601coupled to input605has its capacitance changed by ΔC. The capacitance of sensing electrode602coupled to CDC610through input606, remains constant. The change in capacitance can therefore be given by:

Δ⁢CDo⁢u⁢t∝2⁢C0(1+CSCD⁢A⁢C+Δ⁢C2⁢CD⁢A⁢C).

As ΔC is much smaller than the value of the CapDAC (CDAC), there is little noticeable change in the performance of the CDC when operating in pseudo-differential mode. In other embodiments, both capacitances may change, but the ΔC applied to each capacitance is different. In this case, the pseudo-differential operation may be applied.

When the value of the baseline or parasitic capacitance is high, it may take too long to charge up/down the capacitor to the comparator midcode. In this case, a zoom capacitor may be used to provide a step voltage signal on the sensing electrodes.FIG.7illustrates a CDC700with zoom capacitors755and756coupled to sensing electrodes501and502, respectively. The capacitance, CZ, of the zoom capacitor may be used to increase the common mode voltage at the input of comparator520. This may ensure that the values of VS1and VS2remain in the common-mode range of comparator520, even if the parasitic or baseline capacitance of the sensing electrodes is high. The effect of the zoom capacitance on the signals on the inputs of the comparator may be given by:

VS⁢1=CZ+Dout⁢C0CZ+CD⁢A⁢C+CS+Δ⁢C⁢Vd⁢dVS⁢2=CZ+Dout_⁢C0CZ+CD⁢A⁢C+CS-Δ⁢C⁢Vd⁢d

The use of a zoom capacitor may also improve the resolution of the conversion. Using the zoom capacitor may obviate the use of some of the bits of CapDACs525and526by skipping the increment/decrementing of the code associated with the greater capacitances necessary to reach the comparator's midcode. The improvement to the resolution of the conversion may be seen by:

Δ⁢CDo⁢u⁢t∝2⁢C0*(1+CS+CDAC2CZ+CD⁢A⁢C2).

The actual change in voltage (signal) on the comparator inputs is therefore given by:

Δ⁢V=C0CS+CZ+CD⁢A⁢C.

For clarification, a zoom capacitor may compensate for common mode capacitance (capacitance that exists on both sensing electrodes), while the CapDAC is used to convert the differential capacitance to a digital value (the counter value) and is controlled by the counter output.

Further Power Optimization

Because more power is required for midcode transitions than is required for LSB transitions of the CapDAC, a coarse/fine operation may be employed to allow for a greater range of LSB transitions before a midcode transition is required. That is, a coarse/fine scan operation may reduce the frequency at which a small capacitance change on a sensing electrode causes a midcode transition. The CapDAC may be split into a 4-bit coarse CapDAC and a 6-bit fine CapDAC. The 6-bit fine CapDAC may have a range equivalent to two coarse CapDAC LSBs. In various other embodiments, different resolutions of coarse and fine CapDACs may be used.

FIGS.8A and8Billustrate embodiments of coarse and fine operation.FIG.8Aillustrates a fine CapDAC801with a range of two LSBs of a coarse CapDAC centered on the second bit of the coarse CapDAC811. The fine CapDAC is at its highest value when all bits of the fine CapDAC high. To move to the next level, illustrated inFIG.8B, then the coarse CapDAC811is incremented, and the fine CapDAC802is set to its midcode. Using this coarse/fine overlap may reduce the maximum switching losses from the CapDAC by16x. Fine CapDACs may have greater overlap with coarse CapDACs in some embodiments, such that a fine CapDAC overlaps three bits of a coarse CapDAC.

To realize the coarse/fine operation described above, separate linked binary counters for the coarse CapDAC and the fine CapDAC may be implemented.FIG.9illustrates a combined binary counter940for the coarse and fine CapDACs. Fine Binary Counter941may have a control signal (“Up/Down”) for incrementing or decrementing the counter value and a clock input (“Clk”) to enable the increment/decrement. Incrementing or decrementing fine binary counter941increases or decreases the CapDAC value by one LSB (C0) until the code from the fine binary counter is 63 or 0 and the CapDAC value is therefore 63C0or 0. When this occurs, the coarse binary counter942may by incremented or decremented by receiving the up/down signal and having an enabled input from fine binary counter941. If the fine binary counter941has a value of 63 or 0, meaning that it is saturated or completely off, the coarse binary counter942may be incremented or decremented and the fine binary counter941reset to its midcode. That is, the fine binary counter's MSB is set to 1 and the rest of the bits are set two zero.

Table 1 illustrates the binary counter increasing about the coarse and fine binary counters.

TABLE 1Time4-bit Coarse6-bit FineCapDAC10010111110126C020010111111127C030011100000128C0

When the objective is low-power operation, other system components should also be optimized for power consumption. Rather than implement a high-frequency clock, which may consume more power than is necessary, the CDC of the present invention may employ an asynchronous logic loop for the counter and the comparator.

FIG.10Aillustrates an embodiment of an edge detector1000including comparator1040with differential inputs and outputs. Differential outputs are coupled to inverters1042, which are in turn coupled to OR gate1044. The output of one of the inverters is provided to the D input of flip-flop (F/F)1046. The output of OR gate1040is coupled to the clock of the F/F, which may provide the up/down (increment/decrement) signal to the CapDAC.

FIG.10Billustrates an oscillation loop1001including the edge detector1000ofFIG.10Acoupled to a first buffer1052(Delay1), the output of which is coupled to AND gate1053. When a Finish signal is not asserted (seeFIG.10C, below), a clock signal is provided to the CapDAC (as shown inFIG.9). The output of the AND gate1053is inverted by inverter1054and delayed again through a second buffer1056(Delay2). In one embodiment, the second delay by the second buffer1056may be a number of cascaded buffers. In the embodiment ofFIG.10B, four buffers are used. One of ordinary skill in the art would understand that more or fewer buffers may be implemented depending on the desired delay. In another embodiment, delays may be programmable to adjust to various system and timing requirements. More or fewer buffers may be used based on program settings. The output of the second delay is input to AND gate1057with a scan signal from a low-frequency clock (seeFIG.11, below). If the scan signal is asserted and the output of the second delay is high, a control signal is provided to comparator1040of edge detector1000and the comparison of the signals on the comparator inputs is executed again. This starts the oscillation loop again.

FIG.10Cillustrates a circuit1002for generating the Finish signal on AND gate1053of the oscillation loop1001ofFIG.10B. An edge generator1060receives the up/down signal from the F/F1046of edge detector1000(fromFIG.10A). This signal is inverted by inverter1062and input with the same signal to an AND gate1064. The delay of the inverter1062generates a pulse that clocks the first F/F1071. Two additional F/Fs,1072and1073, are coupled in series, with their Q outputs coupled to an input of an AND gate1080. When all three F/Fs output a high, a Finish signal is asserted and the clock signal for the CapDAC (seeFIG.10B) is stopped.

Further power savings may be achieved by the use of a low-frequency clock.FIG.11Aillustrates a low-power relaxation oscillator1100acting as the low-frequency clock. A current source1110is provided to an integration capacitor, CINT1120, which ramps the voltage across the integration capacitor at a rate of

Rate=IrefCint

Continuous time comparator1140may reset the integration capacitor every time the voltage, VINT, across the integration capacitor crosses VREF. The output of comparator1140is coupled to F/F1150, which outputs the scan signal to the CDC (see the input of AND gate1057ofFIG.10B).

FIG.11Billustrates waveforms for the various voltage signals and outputs of low-power relaxation oscillator1100. VINTis increased at the rate of IREF/CINTand is reset when it reaches VREF. The output of comparator, VOUT, is high with each crossing of VINTof VREF. The scan signal is changed at each comparator output pulse. The period of the low-power relaxation oscillator may be given by

Tperiod=Vr⁢e⁢fIr⁢e⁢f⁢Cint&&Td≪Tperiod,

where Tdis the comparator delay, Tperiodis the oscillation period, and VREFand IREFare the reference voltage and reference current, respectively. A F/F may be added to the output of the comparator to 50% by dividing the frequency of the comparator by 2.

FIG.12illustrates a graph1200of current consumption for analog and digital circuitry of the CDC. When the CDC detects no change in capacitance (no conductive object is on or proximate to the sensing electrodes. The analog power consumption1201is approximately 25 nA at a low clock frequency (1 kHz). The digital power consumption1202for the digital portions of the circuit is less than 20 nA. As the change in capacitance increases, the analog power consumption1201and the digital power consumption1202increase. However, a sensing device spends most of its life in an idle state, where capacitance has not changed. The quiescent power can therefore be the dominant factor in the overall power consumption of a capacitance sensing system. Power consumption that is proportionate to the capacitance change can vastly increase battery life for devices that are not connected to mains power.

It will further be appreciated that the Detailed Description section, and not the Summary and Abstract sections, is intended to be used to interpret the claims. The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present invention as contemplated by the inventor(s), and thus, are not intended to limit the present invention and the appended claims in any way.

Embodiments of the present invention have been described above with the aid of functional and schematic block diagrams illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present invention. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

The breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.