Patent ID: 12205925

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG.1is a cross-sectional view showing a semiconductor package according to the inventive concept.

Referring toFIG.1, a semiconductor package1may include a package substrate100, a semiconductor chip10attached to an upper surface of the package substrate100, an auxiliary chip20attached to a lower surface of the package substrate100, and an encapsulant50encapsulating the semiconductor chip10and the auxiliary chip20.

The package substrate100may include a substrate base110, a plurality of substrate upper surface pads122and a plurality of substrate lower surface pads124respectively disposed on the upper and lower surfaces of the substrate base110, and a plurality of substrate vias128penetrating at least a portion of the substrate base110. In some embodiments, the substrate base110may be formed of a stacked structure of a plurality of base layers, and the package substrate100may further include a plurality of internal wiring patterns126disposed on an upper surface and/or a lower surface of each of the plurality of base layers. Among the plurality of substrate upper surface pads122and the plurality of substrate lower surface pads124, each of the substrate upper surface pads122and a corresponding one of the substrate lower surface pads124may be electrically connected with each other through some of the plurality of substrate vias128, or may be electrically connected through some of the plurality of substrate vias128and some of the plurality of internal wiring patterns126.

In some embodiments, the package substrate100may be a printed circuit board. For example, the package substrate100may be a multi-layer printed circuit board.

The substrate base110may be made of at least one material selected from phenol resin, epoxy resin, and polyimide. The substrate base110may include or may be formed of, for example, at least one material selected from frame retardant 4 (FR4), tetrafunctional epoxy, polyphenylene ether, epoxy/polyphenylene oxide, bismaleimide triazine (BT), thermount, cyanate ester, polyimide, and liquid crystal polymer.

In some embodiments, the plurality of upper substrate pads122, the plurality of substrate lower surface pads124, the plurality of internal wiring patterns126, and the plurality of substrate vias128may include or may be formed of copper. For example, the plurality of substrate upper surface pads122, the plurality of substrate lower surface pads124, the plurality of internal wiring patterns126, and the plurality of substrate vias128may include or may be formed of an electrolytically deposited (ED) copper foil, rolled-annealed (RA) copper foil, ultra-thin copper foils, sputtered copper, copper alloys, or the like.

In some embodiments, the package substrate100may further include a solder resist layer130covering the upper and lower surfaces of the substrate base110. The solder resist layer130may include an upper surface solder resist layer132that exposes the plurality of substrate upper surface pads122and covers the upper surface of the substrate base110and a lower surface solder resist layer134that exposes the plurality of substrate lower surface pads124and covers the lower surface of the substrate base110.

The package substrate100may have at least one communication hole100H extending from an upper surface of the package substrate100to a lower surface of the package substrate100and penetrating the package substrate100. The communication hole100H allows a space on the upper surface of the package substrate100to communicate with a space on the lower surface of the package substrate100. In some embodiments, the communication hole100H may connect a first space between a lower surface of a semiconductor substrate12and an upper surface of the package substrate100to a second space between a lower surface of the package substrate100and an upper surface of the auxiliary chip20. In some embodiments, the communication hole100H may have a tapered shape extending from the upper surface to the lower surface of the package substrate100with the horizontal width of the communication hole100H narrowing toward the lower surface of the package substrate100. The communication hole100H may have a hole diameter DH. The hole diameter DH may be, for example, about 30 μm to about 200 μm. In some embodiments, when the communication hole100H has a tapered shape extending from the upper surface to the lower surface of the package substrate100with the horizontal width of the communication hole100H narrowing toward the lower surface of the package substrate100, the hole diameter DH may be about 50 μm or more at the upper surface of the package substrate100and about 30 μm or more at the lower surface of the package substrate100. Terms such as “about” or “approximately” may reflect amounts, sizes, orientations, or layouts that vary only in a small relative manner, and/or in a way that does not significantly alter the operation, functionality, or structure of certain elements. For example, a range from “about 0.1 to about 1” may encompass a range such as a 0%-5% deviation around 0.1 and a 0% to 5% deviation around 1, especially if such deviation maintains the same effect as the listed range.

In some embodiments, at least one communication hole100H of the package substrate100may be under the semiconductor chip10. In some embodiments, the semiconductor chip10may cover the at least one communication hole100H. For example, all portions of the at least one communication hole100H may overlap the semiconductor chip10in a vertical direction (Z direction). The at least one communication hole100H may communicate with (i.e., may be connected to) a space between the semiconductor chip10and the package substrate100. In some embodiments, at least one communication hole100H of the package substrate100may be located on the auxiliary chip20. In some embodiments, the auxiliary chip20may cover the at least one communication hole100H. For example, all portions of the at least one communication hole100H may overlap the auxiliary chip20in the vertical direction (Z direction). The at least one communication hole100H may communicate with (i.e., may be connected to) a space between the auxiliary chip20and the package substrate100.

In some embodiments, the at least one communication hole100H may be disposed in a portion of the package substrate100in which the semiconductor chip10and the auxiliary chip20overlap each other in the vertical direction (Z direction) to communicate a space between the semiconductor chip10and the package substrate100and a space between the auxiliary chip20and the package substrate100with each other.

The semiconductor chip10may include a semiconductor substrate12having an active surface and an inactive surface opposite to each other, a semiconductor device14formed at the active surface of the semiconductor substrate12, and a plurality of chip pads16disposed on a first surface of the semiconductor chip10. In this specification, the first surface of the semiconductor chip10and a second surface of the semiconductor chip10are opposite to each other, and the second surface of the semiconductor chip10means the inactive surface of the semiconductor substrate12. Because the active surface of the semiconductor substrate12is very adjacent to the first surface of the semiconductor chip10, it is omitted to illustrate the active surface of the semiconductor substrate12separately from the first surface of the semiconductor chip10.

In some embodiments, the semiconductor chip10may have a face-down arrangement in which the first surface thereof faces the package substrate100, and be attached to the upper surface of the package substrate100. In this case, the first surface of the semiconductor chip10may be referred to as a lower surface of the semiconductor chip10, and the second surface of the semiconductor chip10may be referred to as an upper surface of the semiconductor chip10. For example, a plurality of chip connecting members18may be between the plurality of chip pads16of the semiconductor chip10and the plurality of substrate upper surface pads122of the package substrate100. For example, the chip connecting member18may be a solder ball or a micro bump. The semiconductor chip10and the package substrate100may be electrically connected with each other through the plurality of chip connecting members18.

Unless otherwise specified in the present specification, the upper surface refers to a surface facing upward in the drawing, and the lower surface refers to a surface facing downward in the drawing.

The semiconductor substrate12may include or may be formed of, for example, a semiconductor material such as silicon (Si) and germanium (Ge). In some embodiments, the semiconductor substrate12may include or may be formed of a compound semiconductor material such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The semiconductor substrate12may include a conductive region (for example, a well) doped with impurities. The semiconductor substrate12may have various device isolation structures such as a shallow trench isolation (STI) structure.

The semiconductor device14including various types of a plurality of individual devices may be formed at the active surface of the semiconductor substrate12. The plurality of individual devices may include various microelectronic devices, for example, a metal-oxide-semiconductor field effect transistor (MOSFET) such as complementary metal-oxide semiconductor (CMOS) transistor, a system large scale integration (LSI), an active device, a passive device, and the like. The plurality of individual devices may be electrically connected to the conductive region of the semiconductor substrate12. The semiconductor device14may further include a conductive wire or a conductive plug electrically connecting at least two of the plurality of individual devices with each other, or the plurality of individual devices to the conductive region of the semiconductor substrate12. Each of the plurality of individual elements may be electrically isolated from neighboring individual elements by an insulating layer.

In some embodiments, the semiconductor chip10may be a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip. In some embodiments, the semiconductor chip10may be, for example, a memory semiconductor chip. The memory semiconductor chip may be, for example, a nonvolatile memory semiconductor chip such as flash memory, phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (RRAM). The flash memory may be, for example, a NAND flash memory or a V-NAND flash memory. In some embodiments, the semiconductor chip10may be a volatile memory semiconductor chip such as dynamic random access memory (DRAM) and static random access memory (SRAM).

The auxiliary chip20may be a semiconductor chip of a different type from that of the semiconductor chip10. In this specification, the semiconductor chip10may hereinafter be referred to as a main semiconductor chip10to clearly distinguish the semiconductor chip10from the auxiliary chip20. The auxiliary chip20may have a smaller horizontal width and smaller horizontal area than the main semiconductor chip10, and may be a semiconductor chip for assisting the operation of the main semiconductor chip10. For example, the auxiliary chip20may be a silicon capacitor, a controller chip, or a memory semiconductor chip, but is not limited thereto.

In some embodiments, when the main semiconductor chip10is a CPU chip, a GPU chip, or an AP chip, the auxiliary chip20may be a silicon capacitor. In some embodiments, the silicon capacitor may include silicon-based dielectrics such as silicon nitride and silicon dioxide as a capacitor dielectric.

In some embodiments, when the main semiconductor chip10is a non-volatile memory semiconductor chip such as a flash memory, the auxiliary chip20may be a controller chip having a controller built therein. The controller may control access to data stored in the main semiconductor chip10. For example, the controller may control a write/read operation of the main semiconductor chip10, for example, a flash memory, depending on a control command from an external host. The controller may perform wear leveling, garbage collection, bad block management, or error correction code (ECC) for the nonvolatile memory semiconductor chip.

In some embodiments, when the main semiconductor chip10is a memory semiconductor chip, the auxiliary chip20may be a memory semiconductor chip having a capacity and/or operation speed different from that of the main semiconductor chip10. For example, the auxiliary chip20may be a memory semiconductor chip that performs a buffer function.

The auxiliary chip20may be connected to some of the plurality of substrate lower surface pads124of the package substrate100through a plurality of chip terminals28. In some embodiments, the plurality of chip terminals28may be micro pins or micro bumps attached to the auxiliary chip20, but is not limited thereto. For example, the auxiliary chip20may have four or more chip terminals28. In some embodiments, the auxiliary chip20may have a plurality of connection pads similar to the plurality of chip pads16of the semiconductor chip10, and the plurality of chip terminals28may be solder balls or micro bumps between the plurality of connection pads and some of the plurality of substrate lower surface pads124.

The encapsulant50may encapsulate the semiconductor chip10and the auxiliary chip20. The encapsulant50may cover at least a portion of the upper surface of the package substrate100, and may cover a portion of the lower surface of the package substrate100. In some embodiments, the encapsulant50may cover all of the upper surface (i.e., the entire upper surface) of the package substrate100, and may cover a portion of the lower surface of the package substrate100, but may not cover the remaining portion thereof. For example, the encapsulant50may be, for example, a molding member including or being formed of an epoxy mold compound (EMC).

The encapsulant50may include a main encapsulation portion50M, a main underfill portion50UM, an auxiliary encapsulation portion50S, an auxiliary underfill portion50US, and a hole filling portion50V. The main encapsulation portion50M, the main underfill portion50UM, the auxiliary encapsulation portion50S, the auxiliary underfill portion50US, and the hole filling portion50V may be integrally formed to constitute the encapsulant50.

The main encapsulation portion50M may cover the semiconductor chip10on the upper surface of the package substrate100. In some embodiments, the main encapsulation portion50M may cover both the second surface, that is, the upper surface and the side surface of the semiconductor chip10. In some other embodiments, the main encapsulation portion50M may cover the side surface of the semiconductor chip10, but may expose the second surface (i.e., the upper surface) of the semiconductor chip10without covering the second surface. The main underfill portion50UM may fill a space between the first surface (i.e., the lower surface) of the semiconductor chip10and the upper surface of the package substrate100, and surround the plurality of chip connecting members18. For example, the main underfill portion50UM may surround each of the plurality of chip connecting members18.

The auxiliary encapsulation portion50S may cover the auxiliary chip20on the lower surface of the package substrate100. In some embodiments, the auxiliary encapsulation portion50S may cover both the lower surface and the side surface of the auxiliary chip20. In some other embodiments, the auxiliary encapsulation portion50S may cover the side surface of the auxiliary chip20, but may expose the lower surface of the auxiliary chip20without covering the lower surface thereof. The auxiliary underfill portion50US may fill a space between the upper surface of the auxiliary chip20and the lower surface of the package substrate100, and surround the plurality of chip terminals28. For example, the auxiliary underfill portion50US may surround each of the plurality of chip terminals28. The hole filling portion50V may fill the communication hole100H. The hole filling portion50V may have a tapered shape extending from the upper surface to the lower surface of the package substrate100, that is, from the upper end to the lower end of the communication hole100H with the horizontal width of the communication hole100H narrowing toward the lower surface of the package substrate100.

The encapsulant50may include the main underfill portion50UM and the auxiliary underfill portion50US that are molded under-fill (MUF) which may fill a narrow gap between a chip and a substrate with mold resin.

The main encapsulation portion50M and the main underfill portion50UM may be connected with each other, and the auxiliary encapsulation portion50S and the auxiliary underfill portion50US may be connected with each other, an upper end of the hole filling portion50V may be connected to the main underfill portion50UM, and a lower end thereof may be connected to the auxiliary underfill portion50US.

Each of the main encapsulation portion50M, the main underfill portion50UM, the auxiliary encapsulation portion50S, the auxiliary underfill portion50US, and the hole filling portion50V may be referred to as distinguishing portions included in the encapsulant50. Each name of the distinguishing portions may represent a position at which each distinguishing portion is disposed in the encapsulant50for the convenience of description. The main encapsulation portion50M, the main underfill portion50UM, the auxiliary encapsulation portion50S, the auxiliary underfill portion50US, and the hole filling portion50V may be integrally formed by a single manufacturing process to form the encapsulant50.

In some embodiments, the main encapsulation portion50M may cover the entire upper surface of the package substrate100, and the auxiliary encapsulation portion50S may cover a portion of the lower surface of the package substrate100but not the remaining portion thereof. For example, the horizontal width of the main encapsulation portion50M may have a greater value than the horizontal width of the auxiliary encapsulation portion50S.

The main semiconductor chip10may have a larger horizontal width and a larger horizontal area than the auxiliary chip20, and the main underfill portion50UM may have a larger horizontal width and a larger horizontal area than the auxiliary underfill portion50US.

In some embodiments, after the semiconductor chip10and the auxiliary chip20are attached to the upper and lower surfaces of the package substrate100, the encapsulant50may be formed by injecting an encapsulation material into the upper surface of the package substrate100in an injection direction DF. In some embodiments, the injection direction DF may be a first horizontal direction (X direction). After the encapsulation material is first injected into the upper surface of the package substrate100, the encapsulation material may be supplied to the space between the semiconductor chip10and the package substrate100, and sequentially supplied along the communication hole100H to the lower surface of the package substrate100to form the encapsulant50.

According to the inventive concept, the encapsulant50encapsulating the semiconductor chip10attached to the upper surface of the package substrate100and the auxiliary chip20attached to the lower surface of the package substrate100may be formed in one manufacturing process, and thus the process steps of manufacturing the semiconductor package1may be reduced, and manufacturing costs of the semiconductor package1may be reduced.

A plurality of external connection terminals150may be attached to other portions of the plurality of lower surface pads124. The plurality of external connection terminals150may electrically connect the semiconductor package1to the outside.

The auxiliary chip20may be spaced apart from the plurality of external connection terminals150with a separation distance WD. The separation distance WD may be less than about 100 μm. In the semiconductor package1, after an encapsulation material for forming the encapsulant50is first injected into the upper surface of the package substrate100, the encapsulation material is supplied to the space between the semiconductor chip10and the package substrate100and sequentially supplied along the communication hole100H to the lower surface of the package substrate100to form the encapsulant50. Thus, the semiconductor package1does not require an additional space for injecting the encapsulation material into the lower surface of the package substrate100. Therefore, the separation distance WD between the auxiliary chip20and the plurality of external connection terminals150may be reduced, thereby minimizing a horizontal area of the semiconductor package5, and thus, the size (i.e., a form factor) of the semiconductor package5may be reduced.

FIGS.2A and2Bare layout views illustrating a planar arrangement of main components of a semiconductor package according to the inventive concept. For example, a cross-sectional view of each of a semiconductor package1-1shown inFIG.2Aand a semiconductor package1-2shown inFIG.2Bis the same as the cross-sectional view of the semiconductor package1shown inFIG.1, and in the descriptions ofFIGS.2A and2B,FIG.1may also be referred to.

Referring toFIG.2A, the semiconductor package1-1may include a package substrate100-1, a semiconductor chip10attached to an upper surface of the package substrate100-1, and an auxiliary chip20attached to a lower surface of the package substrate100-1.

The package substrate100-1may have at least one communication hole100H extending from an upper surface of the package substrate100-1to a lower surface of the package substrate100-1and penetrating the package substrate100-1. All portions of the communication hole100H may overlap the semiconductor chip10in the vertical direction (Z direction), and all portions of the communication hole100H may overlap the auxiliary chip20in a vertical direction (Z direction). For example, the communication hole100H may be disposed in a portion of the package substrate100-1where the semiconductor chip10and the auxiliary chip20overlap each other in the vertical direction (Z direction).

In some embodiments, the communication hole100H may be disposed in a central portion of the auxiliary chip20in an X-Y plane, in a central portion of the auxiliary chip20or in a portion adjacent to the center, in a top view. Because the semiconductor package1-1may include the communication hole100H disposed at a central portion of the auxiliary chip20in the X-Y plane, an encapsulation material for forming the encapsulant50shown inFIG.1may be supplied from a central portion of a space between the package substrate100-1and the auxiliary chip20to the space therebetween, and thus, the encapsulant50may encapsulate the auxiliary chip20by uniformly filling the space between the package substrate100-1and the auxiliary chip20.

Referring toFIG.2B, the semiconductor package1-2may include a package substrate100, a semiconductor chip10attached to an upper surface of a package substrate100-2, and an auxiliary chip20attached to a lower surface of the package substrate100-2.

The package substrate100-2may have at least one communication hole100H extending from an upper surface of the package substrate100-2to a lower surface of the package substrate100-2and penetrating the package substrate100-2. All portions of each of the plurality of communication holes100H may overlap the semiconductor chip10in a vertical direction (Z direction), and all portions of each of the plurality of communication holes100H may overlap the auxiliary chip20in the vertical direction (Z direction). For example, a plurality of communication holes100H may be disposed in a portion of the package substrate100-2where the semiconductor chip10and the auxiliary chip20overlap each other in the vertical direction (Z direction).

The encapsulation material for forming the encapsulant50shown inFIG.1may be injected in an injection direction DF. For example, the injection direction DF may be a first horizontal direction (X direction). In some embodiments, the plurality of communication holes100H may be disposed in a central portion of the auxiliary chip20in the first horizontal direction (X direction).

In some embodiments, the plurality of communication holes100H may be arranged in a row in a second horizontal direction (Y direction) orthogonal to a first horizontal direction (X direction) that is the injection direction DF.

Because the semiconductor package1-2has a plurality of communication holes100H arranged in a row in the second horizontal direction (Y direction) orthogonal to the first horizontal direction (X direction) that is the injection direction DF, the encapsulation material may be supplied to a space between the package substrate100-2and the auxiliary chip20through a plurality of communication holes100H that are arranged in a row in the second horizontal direction (Y direction), and thus, the encapsulant50may encapsulate the auxiliary chip20by uniformly filling the space between the package substrate100-2and the auxiliary chip20. In some embodiments, the plurality of communication holes100H may be arranged in two or more rows.

FIGS.3A and3Bare cross-sectional views illustrating a semiconductor package according to the inventive concept. In the description given with reference toFIGS.3A and3B, descriptions already given with reference toFIGS.1to2Bmay be omitted.

Referring toFIG.3A, a semiconductor package1amay include a package substrate100, a semiconductor chip10attached to an upper surface of the package substrate100, an auxiliary chip20attached to a lower surface of the package substrate100, and an encapsulant50encapsulating the semiconductor chip10and the auxiliary chip20. The semiconductor package1amay further include a unit device chip30attached to the lower surface of the package substrate100. The auxiliary chip20and the unit device chip30may be attached to the lower surface of the package substrate100while being spaced apart from each other.

The package substrate100may have at least one communication hole100H extending from an upper surface of the package substrate100to a lower surface of the package substrate100and penetrating the package substrate100. The communication hole100H may allow a space on the upper surface of the package substrate100to communicate with a space on the lower surface of the package substrate100. In some embodiments, the communication hole100H may connect a first space between the lower surface of a semiconductor substrate12and an upper surface of the package substrate100to a second space between a lower surface of the package substrate100and an upper surface of the auxiliary chip20. In some embodiments, the communication hole100H may have a tapered shape extending from the upper surface to the lower surface of the package substrate100with the horizontal width of the communication hole100H narrowing toward the lower surface of the package substrate100.

In some embodiments, the at least one communication hole100H may be disposed in a portion of the package substrate100in which the semiconductor chip10and the auxiliary chip20overlap each other in the vertical direction (Z direction) to communicate a space between the semiconductor chip10and the package substrate100and a space between the auxiliary chip20and the package substrate100with each other.

The unit device chip30may be a passive device or an active device. For example, the passive device may be a resistor, an inductor, or a capacitor, and the active device may be a transistor, a diode, or an operational amplifier. In some embodiments, the unit device chip30may be an intermediate storage capacitor (ISC). For example, the unit device chip30may be a ceramic capacitor or a ceramic resistor. In some embodiments, the unit device chip30may be a discrete chip with just one circuit element, either passive (such as resistor, capacitor, and an inductor), or active (such as a transistor, a diode, and an operational amplifier). The discrete chip as the unit device chip30may be provided in the form of a chip without being packaged or in the form of a package. When the unit device chip30is provided in the form of a package, the encapsulant50may not cover the unit device chip30as shown inFIG.3A. When the unit device chip30is provided in the form of a chip, the encapsulant50may cover the unit device chip30as shown inFIG.3B.

The unit device chip30may be connected to some of the plurality of lower surface pads124of the package substrate100through two or three device terminals38. In some embodiments, a solder paste may be between the device terminal38of the unit device chip30and the substrate lower surface pad124.

The semiconductor chip10may have an integrated circuit including two or more unit devices. The auxiliary chip20may have an integrated circuit, or may have four or more chip terminals28. The unit device chip30may have two or three device terminals38. The number of chip connecting members18connected to the semiconductor chip10may be greater than the number of chip terminals28connected to the auxiliary chip20or included in the auxiliary chip20. The number of chip terminals28connected to the auxiliary chip20or included in the auxiliary chip20may be greater than the number of device terminals38of the unit device chip30.

The encapsulant50may encapsulate the semiconductor chip10and the auxiliary chip20. The encapsulant50may include a main encapsulation portion50M, a main underfill portion50UM, an auxiliary encapsulation portion50S, an auxiliary underfill portion50US, and a hole filling portion50V. The main encapsulation portion50M, the main underfill portion50UM, the auxiliary encapsulation portion50S, the auxiliary underfill portion50US, and the hole filling portion50V may be integrally formed to constitute the encapsulant50. The encapsulant50may not cover the unit device chip30. The encapsulant50may be formed to be spaced apart from the unit device chip30. For example, the auxiliary encapsulation portion50S of the encapsulant50may be spaced apart from the unit device chip30.

In the semiconductor package1a, after an encapsulation material for forming the encapsulant50is first injected into the upper surface of the package substrate100, the encapsulation material is supplied to the space between the semiconductor chip10and the package substrate100and sequentially supplied along the communication hole100H to the lower surface of the package substrate100to form the encapsulant50. Thus, the semiconductor package1adoes not require an additional space for injecting the encapsulation material into the lower surface of the package substrate100. Accordingly, the area occupied by the auxiliary chip20and the space for the encapsulation material injection on the lower surface of the package substrate100is reduced, and thus, the unit device chip30may be attached to the lower surface of the package substrate100without increasing the area of the package substrate100or at a minimum increase of the area of the package substrate100.

Referring toFIG.3B, the semiconductor package1bmay include a package substrate100, a semiconductor chip10attached to an upper surface of the package substrate100, an auxiliary chip20attached to a lower surface of the package substrate100, a unit device chip30attached to the lower surface of the package substrate100, and an encapsulant50aencapsulating the semiconductor chip10, the auxiliary chip20, and the unit device chip30together. The auxiliary chip20and the unit device chip30may be attached to the lower surface of the package substrate100while being spaced apart from each other. The package substrate100may have at least one communication hole100H extending from an upper surface of the package substrate100to a lower surface of the package substrate100and penetrating the package substrate100.

The encapsulant50amay encapsulate the semiconductor chip10, the auxiliary chip20, and the unit device chip30. The encapsulant50amay include a main encapsulation portion50M, a main underfill portion50UM, an auxiliary encapsulation portion50Sa, an auxiliary underfill portion50US, and a hole filling portion50V. The auxiliary encapsulation portion50Sa may cover the auxiliary chip20and the unit device chip30together. The encapsulant50amay include a main underfill portion50UM and an auxiliary underfill portion50US that are MUF.

FIG.4is a cross-sectional view illustrating a semiconductor package according to the inventive concept. In the description given with reference toFIG.4, descriptions already given with reference toFIGS.1to2Bmay be omitted.

Referring toFIG.4, a semiconductor package2may include a package substrate100a, a semiconductor chip10attached to an upper surface of the package substrate100a, an auxiliary chip20attached to a lower surface of the package substrate100a, and an encapsulant50encapsulating the semiconductor chip10and the auxiliary chip20.

The package substrate100amay have at least one communication hole100Ha extending from an upper surface of the package substrate100ato a lower surface of the package substrate100aand penetrating the package substrate100a. The communication hole100Ha may allow a space on the upper surface of the package substrate100ato communicate with a space on the lower surface of the package substrate100a. In some embodiments, the communication hole100Ha may connect a first space between the lower surface of a semiconductor substrate12and an upper surface of the package substrate100ato a second space between a lower surface of the package substrate100aand an upper surface of the auxiliary chip20. In some embodiments, the communication hole100Ha may have a tapered shape extending from the upper surface to the lower surface of the package substrate100awith the horizontal width of the communication hole100H narrowing toward the lower surface of the package substrate100a.

In some embodiments, at least one communication hole100Ha of the package substrate100amay be at a position spaced apart from the lower surface of the semiconductor chip10. For example, the at least one communication hole100Ha may not overlap the semiconductor chip10in the vertical direction (Z direction). At least one communication hole100Ha may communicate with a space on the top surface of the package substrate100a. In some embodiments, at least one communication hole100Ha of the package substrate100amay be on the auxiliary chip20. For example, all portions of the at least one communication hole100Ha may overlap the auxiliary chip20in the vertical direction (Z direction). At least one communication hole100Ha may communicate with a space between the auxiliary chip20and the package substrate100a.

The encapsulant50bmay encapsulate the semiconductor chip10and the auxiliary chip20. The encapsulant50bmay cover at least a portion of the upper surface of the package substrate100a, and may cover a portion of the lower surface of the package substrate100a. In some embodiments, the encapsulant50bmay cover all of the upper surface of the package substrate100a, and may cover a portion of the lower surface of the package substrate100a, but may not cover the remaining portion thereof. The encapsulant50bmay be, for example, a molding member including or being formed of an epoxy mold compound.

The encapsulant50bmay include a main encapsulation portion50M, a main underfill portion50UM, an auxiliary encapsulation portion50S, an auxiliary underfill portion50US, and a hole filling portion50Va. The main encapsulation portion50M, the main underfill portion50UM, the auxiliary encapsulation portion50S, the auxiliary underfill portion50US, and the hole filling portion50Va may be integrally formed to constitute the encapsulant50b. The encapsulant50bmay include a main underfill portion50UM and an auxiliary underfill portion50US that are MUF.

The main encapsulation portion50M may cover the semiconductor chip10on the top surface of the package substrate100a. The main underfill portion50UM may fill a space between the first surface (i.e., the lower surface) of the semiconductor chip10and the upper surface of the package substrate100, and surround the plurality of chip connecting members18. For example, the main underfill portion50Um may surround each of the plurality of chip connecting members18.

The auxiliary encapsulation portion50S may cover the auxiliary chip20on the lower surface of the package substrate100a. The auxiliary underfill portion50US may fill a space between the upper surface of the auxiliary chip20and the lower surface of the package substrate100a, and surround the plurality of chip terminals28. For example, the auxiliary encapsulation portion50S may surround each of the plurality of chip terminals28. The hole filling portion50V may fill the communication hole100Ha.

The main encapsulation portion50M and the main underfill portion50UM may be connected with each other. The auxiliary encapsulation portion50S and the auxiliary underfill portion50US may be connected with each other. An upper end of the hole filling portion50Va may be connected to the main encapsulation portion50M, and a lower end thereof may be connected to the auxiliary underfill portion50US.

In some embodiments, after attaching the semiconductor chip10and the auxiliary chip20on the upper and lower surfaces of the package substrate100a, an encapsulation material is injected into the upper surface of the package substrate100ain the injection direction DF, thereby forming the encapsulant50b. After the encapsulation material is first injected into the upper surface of the package substrate100a, a portion of the encapsulation material may be supplied to a space between the semiconductor chip10and the package substrate100a, and another portion of the encapsulation material may be supplied to the lower surface of the package substrate100aalong the communication hole100Ha, thereby forming the encapsulant50b.

FIGS.5A and5Bare layout views illustrating a planar arrangement of main components of a semiconductor package according to the inventive concept. For example, a cross-sectional view of each of a semiconductor package2-1as shown inFIG.5Aand a semiconductor package2-2as shown inFIG.5Bis the same as the cross-sectional view of the semiconductor package2as shown inFIG.4, and in the descriptions ofFIGS.5A and5B,FIG.4may also be referred to.

Referring toFIG.5A, the semiconductor package2-1may include a package substrate100a-1, a semiconductor chip10attached to an upper surface of a package substrate100a-1, and an auxiliary chip20attached to a lower surface of the package substrate100a-1.

The package substrate100a-1may have at least one communication hole100Ha extending from an upper surface of the package substrate100a-1to a lower surface of the package substrate100a-1and penetrating the package substrate100a-1. The communication hole100Ha may be located at a position spaced apart from the bottom of the semiconductor chip10. For example, the communication hole100Ha may not overlap the semiconductor chip10in the vertical direction (Z direction). The communication hole100Ha may be located on the auxiliary chip20. For example, all portions of the communication hole100Ha may overlap the auxiliary chip20in the vertical direction (Z direction).

In some embodiments, the communication hole100Ha may be disposed in a central portion of the auxiliary chip20in an X-Y plane, in a central portion of the auxiliary chip20or in a portion adjacent to the center, in a top view. Because the semiconductor package2-1may include the communication hole100Ha disposed at a central portion of the auxiliary chip20in the X-Y plane, an encapsulation material for forming the encapsulant50bas shown inFIG.4may be supplied from a central portion of a space between the package substrate100a-1and the auxiliary chip20to the space therebetween, and thus, the encapsulant50bmay encapsulate the auxiliary chip20by uniformly filling the space between the package substrate100a-1and the auxiliary chip20.

Referring toFIG.5B, the semiconductor package2-2may include a package substrate100a-2, a semiconductor chip10attached to an upper surface of a package substrate100a-2, and an auxiliary chip20attached to a lower surface of the package substrate100a-2.

The package substrate100a-2may have at least one communication hole100Ha extending from an upper surface of the package substrate100a-2to a lower surface of the package substrate100a-2and penetrating the package substrate100a-2. The communication hole100Ha may be at a position spaced apart from the lower surface of the semiconductor chip10. For example, the communication hole100Ha may not overlap the semiconductor chip10in the vertical direction (Z direction). The communication hole100Ha may be located on the auxiliary chip20. For example, all portions of the communication hole100Ha may overlap the auxiliary chip20in the vertical direction (Z direction).

The encapsulation material for forming the encapsulant50bas shown inFIG.4may be injected in the injection direction DF. For example, the injection direction DF may be a first horizontal direction (X direction). In some embodiments, the plurality of communication holes100Ha may be disposed in a central portion of the auxiliary chip20in the first horizontal direction (X direction).

In some embodiments, the plurality of communication holes100Ha may be arranged in a row in a second horizontal direction (Y direction) orthogonal to a first horizontal direction (X direction) that is the injection direction DF.

Because the semiconductor package2-2has a plurality of communication holes100Ha arranged in a row in the second horizontal direction (Y direction) orthogonal to the first horizontal direction (X direction) that is the injection direction DF, the encapsulation material may be supplied to the space between the package substrate100a-2and the auxiliary chip20through a plurality of communication holes100Ha arranged in the row in the second horizontal direction (Y direction), and thus, the encapsulant50bmay encapsulate the auxiliary chip20by uniformly filling the space between the package substrate100a-2and the auxiliary chip20. In some embodiments, the plurality of communication holes100Ha may be arranged in two or more rows.

FIGS.6A and6Bare cross-sectional views illustrating a semiconductor package according to the inventive concept. In the description given with reference toFIGS.6A and6B, descriptions already given with reference toFIGS.4to5Bmay be omitted.

Referring toFIG.6A, the semiconductor package2amay include a package substrate100a, a semiconductor chip10attached to an upper surface of the package substrate100a, an auxiliary chip20attached to a lower surface of the package substrate100a, and an encapsulant50bencapsulating the semiconductor chip10and the auxiliary chip20. The semiconductor package2amay further include a unit device chip30attached to the lower surface of the package substrate100a. The auxiliary chip20and the unit device chip30may be attached to the lower surface of the package substrate100awhile being spaced apart from each other.

The package substrate100amay have at least one communication hole100Ha extending from an upper surface of the package substrate100ato a lower surface of the package substrate100aand penetrating the package substrate100a. The communication hole100Ha may allow a space on the upper surface of the package substrate100ato communicate with a space on the lower surface of the package substrate100a. In some embodiments, the communication hole100Ha may connect a first space between the lower surface of a semiconductor substrate12and an upper surface of the package substrate100ato a second space between a lower surface of the package substrate100aand an upper surface of the auxiliary chip20. In some embodiments, the communication hole100Ha may have a tapered shape extending from the upper surface to the lower surface of the package substrate100awith the horizontal width of the communication hole100Ha narrowing toward the lower surface of the package substrate100a.

In some embodiments, the at least one communication hole100Ha may be spaced apart from the lower surface of the semiconductor chip10in the vertical direction (Z direction) and be disposed in a portion of the package substrate100aoverlapping the auxiliary chip20, so that the at least one communication hole100Ha may communicate a space on the upper surface of the package substrate100awith a space between the auxiliary chip20and the package substrate100a.

The encapsulant50bmay include a main encapsulation portion50M, a main underfill portion50UM, an auxiliary encapsulation portion50S, an auxiliary underfill portion50US, and a hole filling portion50V. The main encapsulation portion50M, the main underfill portion50UM, the auxiliary encapsulation portion50S, the auxiliary underfill portion50US, and the hole filling portion50V may be integrally formed to constitute the encapsulant50b. The encapsulant50bmay not cover the unit device chip30. The encapsulant50bmay be formed to be spaced apart from the unit device chip30. For example, the auxiliary encapsulation portion50S of the encapsulant50bmay be spaced apart from the unit device chip30.

In the semiconductor package2a, after an encapsulation material for forming the encapsulant50bis first injected into the upper surface of the package substrate100a, a portion of the injected encapsulation material is supplied to a space between the semiconductor chip10and the package substrate100a, and the other portion of the injected encapsulation material is supplied to the lower surface of the package substrate100aalong the communication hole100Ha. Thus, the semiconductor package2adoes not require an additional space for injecting the encapsulation material into the lower surface of the package substrate100a. Accordingly, the area occupied by the auxiliary chip20and the space for the encapsulation material injection on the lower surface of the package substrate100ais reduced, and thus, the unit device chip30may be attached to the lower surface of the package substrate100awithout increasing the area of the package substrate100aor at a minimum increase of the area of the package substrate100a.

Referring toFIG.6B, the semiconductor package2bmay include a package substrate100a, a semiconductor chip10attached to an upper surface of the package substrate100a, an auxiliary chip20attached to a lower surface of the package substrate100a, a unit device chip30attached to the lower surface of the package substrate100a, and an encapsulant50cencapsulating the semiconductor chip10, the auxiliary chip20, and the unit device chip30together. The auxiliary chip20and the unit device chip30may be attached to the lower surface of the package substrate100awhile being spaced apart from each other. The package substrate100amay have at least one communication hole100Ha extending from an upper surface of the package substrate100ato a lower surface of the package substrate100aand penetrating the package substrate100a.

The encapsulant50cmay encapsulate the semiconductor chip10, the auxiliary chip20, and the unit device chip30. The encapsulant50cmay include a main encapsulation portion50M, a main underfill portion50UM, an auxiliary encapsulation portion50Sa, an auxiliary underfill portion50US, and a hole filling portion50V. The auxiliary encapsulation portion50Sa may cover the auxiliary chip20and the unit device chip30together. The encapsulant50cmay include a main underfill portion50UM and an auxiliary underfill portion50US that are MUF.

FIGS.7A and7Bare cross-sectional views illustrating a semiconductor package according to the inventive concept. In the description given with reference toFIGS.7A and7B, descriptions already given with reference toFIGS.1to6Bmay be omitted.

Referring toFIG.7A, the semiconductor package3may include a package substrate100b, a semiconductor chip10attached to an upper surface of the package substrate100b, a first auxiliary chip20aand a second auxiliary chip20battached to a lower surface of the package substrate100b, and an encapsulant50dencapsulating the semiconductor chip10, the first auxiliary chip20a, and the second auxiliary chip20b. The first auxiliary chip20aand the second auxiliary chip20bmay be attached to the lower surface of the package substrate100bwhile being spaced apart from each other.

The package substrate100bmay have at least one communication hole100H1and at least one communication hole100H2extending from an upper surface of the package substrate100bto a lower surface of the package substrate100band penetrating the package substrate100b. Each of the first communication hole100H1and the second communication hole100H2may allow a space on the upper surface of the package substrate100bto communicate with a space on the lower surface of the package substrate100b. In some embodiments, the first communication hole100H1may connect a first space between the lower surface of a semiconductor substrate12and an upper surface of the package substrate100bto a second space between a lower surface of the package substrate100band an upper surface of the first auxiliary chip20a. In some embodiments, the second communication hole100H2may connect a third space adjacent to the upper surface of the package substrate100bto a fourth space between the lower surface of the package substrate100band an upper surface of the second auxiliary chip20b. In some embodiments, each of the first communication hole100H1and the second communication hole100H1and100H2may have a tapered shape extending from the upper surface to the lower surface of the package substrate100bwith the horizontal width of the communication hole100H narrowing toward the lower surface of the package substrate100b. The first communication hole100H1is substantially the same as the communication hole100H as described with reference toFIGS.1to3B, the second communication hole100H2is substantially the same as the communication hole100Ha as described with reference toFIGS.4to6A, and thus a detailed description of the first communication hole100H1and the second communication hole100H2will be omitted.

The encapsulant50dmay surround the semiconductor chip10, the first auxiliary chip20a, and the second auxiliary chip20b. The encapsulant50dmay include a main encapsulation portion50M, a main underfill portion50UM, a first auxiliary encapsulation portion50S1, a second auxiliary encapsulation portion50S2, a first auxiliary underfill portion50US1, a second auxiliary underfill portion50US2, a first hole filling portion50V1, and a second hole filling portion50V2. The main encapsulation portion50M, the main underfill portion50UM, the first auxiliary encapsulation portion50S1, the second auxiliary encapsulation portion50S2, the first auxiliary underfill portion50US1, the second auxiliary underfill portion50US2, the first hole filling portion50V1, and the second hole filling portion50V2may be integrally formed to constitute the encapsulant50d.

The main encapsulation portion50M may cover the semiconductor chip10on the top surface of the package substrate100b. The main underfill portion50UM may fill a space between the first surface, that is, the lower surface of the semiconductor chip10and the upper surface of the package substrate100, and surround the plurality of chip connecting members18.

The first auxiliary encapsulation portion50S1may cover the first auxiliary chip20aon the lower surface of the package substrate100b. The second auxiliary encapsulation portion50S2may cover the second auxiliary chip20bon the lower surface of the package substrate100b. The first auxiliary underfill portion50US1may fill a space between the upper surface of the auxiliary chip20aand the lower surface of the package substrate100b, and surround a plurality of first chip terminals28aelectrically connecting the first auxiliary chip20ato the package substrate100b. The second auxiliary underfill portion50US2may fill a space between the upper surface of the auxiliary chip20band the lower surface of the package substrate100b, and surround a plurality of second chip terminals28belectrically connecting the second auxiliary chip20bto the package substrate100b. The first hole filling portion50V1may fill the first communication hole100H1. The second hole filling portion50V2may fill the second communication hole100H2.

The main encapsulation portion50M and the main underfill portion50UM may be connected with each other. The first auxiliary encapsulation portion50S1and the first auxiliary underfill portion50US1may be connected with each other. The second auxiliary encapsulation portion50S2and the second auxiliary underfill portion50US2may be connected with each other. An upper end of the first hole filling portion50V1may be connected to the main underfill portion50UM, and a lower end thereof may be connected to the first auxiliary underfill portion50US1. An upper end of the second hole filling portion50V2may be connected to the main underfill portion50UM, and a lower end thereof may be connected to the second auxiliary underfill portion50US2. The first auxiliary encapsulation portion50S1and the first auxiliary underfill portion50US1may be spaced apart from the second auxiliary encapsulation portion50S2and the second auxiliary underfill portion50US2, respectively, on the lower surface of the package substrate100b.

Referring toFIG.7B, the semiconductor package3amay include a package substrate100b, a semiconductor chip10attached to an upper surface of the package substrate100b, a first auxiliary chip20aand a second auxiliary chip20battached to a lower surface of the package substrate100b, and an encapsulant50eencapsulating the semiconductor chip10and the first auxiliary chip20aand the second auxiliary chip20b. The package substrate100bmay have at least one communication hole100H1and at least one communication hole100H2extending from an upper surface of the package substrate100bto a lower surface of the package substrate100band penetrating the package substrate100b.

The encapsulant50emay surround the semiconductor chip10, the first auxiliary chip20a, and the second auxiliary chip20b. The encapsulant50emay include a main encapsulation portion50M, a main underfill portion50UM, an auxiliary encapsulation portion50Sb, a first auxiliary underfill portion50US1, a second auxiliary underfill portion50US2, a first hole filling portion50V1, and a second hole filling portion50V2. The main encapsulation portion50M, the main underfill portion50UM, the auxiliary encapsulation portion50Sb, the first auxiliary underfill portion50US1, the second auxiliary underfill portion50US2, the first hole filling portion50V1, and the second hole filling portion50V2may be integrally formed to constitute the encapsulant50e. The auxiliary encapsulation portion50Sb may cover the first auxiliary chip20aand the second auxiliary chip20btogether on the lower surface of the package substrate100b.

The main encapsulation portion50M and the main underfill portion50UM may be connected with each other. The auxiliary encapsulation portion50Sb may be connected to each of the first auxiliary underfill portion50US1and the second auxiliary underfill portion50US2. An upper end of the first hole filling portion50V1may be connected to the main underfill portion50UM, and a lower end thereof may be connected to the first auxiliary underfill portion50US1. An upper end of the second hole filling portion50V2may be connected to the main underfill portion50UM, and a lower end thereof may be connected to the second auxiliary underfill portion50US2.

FIGS.8A to8Care cross-sectional views illustrating a semiconductor package according to the inventive concept. In the description given with reference toFIGS.8A to8C, descriptions already given with reference toFIGS.1to7Bmay be omitted.

Referring toFIG.8A, the semiconductor package4may include a package substrate100a, a semiconductor chip10aattached to an upper surface of the package substrate100a, an auxiliary chip20attached to a lower surface of the package substrate100a, and an encapsulant50fencapsulating the semiconductor chip10aand the auxiliary chip20.

The semiconductor chip10amay include a semiconductor substrate12having an active surface and an inactive surface opposite to each other, a semiconductor device14formed at the active surface of the semiconductor substrate12, and a plurality of chip pads16adisposed on a first surface of the semiconductor chip10.

In some embodiments, the semiconductor chip10ahas a face-up arrangement in which a second surface opposite to the first surface faces the package substrate100a, and may be attached to the upper surface of the package substrate100a. In this case, the first surface of the semiconductor chip10amay be referred to as an upper surface of the semiconductor chip10a, and the second surface of the semiconductor chip10amay be referred to as a lower surface of the semiconductor chip10a. The semiconductor chip10ahas a die adhesive film15attached to the second surface and may be attached to the upper surface of the package substrate100a. A plurality of chip connecting members18amay be connected between the plurality of chip pads16aof the semiconductor chip10aand a plurality of substrate upper surface pads122of the package substrate100a, respectively. For example, the chip connecting member18amay be a bonding wire. The semiconductor chip10aand the package substrate100amay be electrically connected with each other through the plurality of chip connecting members18a.

The package substrate100amay have at least one communication hole100Ha extending from an upper surface of the package substrate100ato a lower surface of the package substrate100aand penetrating the package substrate100a. In some embodiments, at least one communication hole100Ha of the package substrate100amay be at a position spaced apart from the lower surface of the semiconductor chip10. In some embodiments, at least one communication hole100Ha of the package substrate100amay be on the auxiliary chip20.

The encapsulant50fmay encapsulate the semiconductor chip10aand the auxiliary chip20. The encapsulant50fmay cover at least a portion of the upper surface of the package substrate100a, and may cover a portion of the lower surface of the package substrate100a. The encapsulant50fmay include a main encapsulation portion50M, an auxiliary encapsulation portion50S, an auxiliary underfill portion50US, and a hole filling portion50Va. The main encapsulation portion50M, the auxiliary encapsulation portion50S, the auxiliary underfill portion50US, and the hole filling portion50Va may be integrally formed to constitute the encapsulant50f.

Referring toFIG.8B, the semiconductor package4amay include a package substrate100a, a semiconductor chip10aattached to an upper surface of the package substrate100a, an auxiliary chip20attached to a lower surface of the package substrate100a, and an encapsulant50fencapsulating the semiconductor chip10aand auxiliary chip20. The semiconductor package4amay further include a unit device chip30attached to the lower surface of the package substrate100a. The package substrate100amay have at least one communication hole100Ha extending from an upper surface of the package substrate100ato a lower surface of the package substrate100aand penetrating the package substrate100a.

The encapsulant50fmay include a main encapsulation portion50M, an auxiliary encapsulation portion50S, an auxiliary underfill portion50US, and a hole filling portion50Va. The main encapsulation portion50M, the auxiliary encapsulation portion50S, the auxiliary underfill portion50US, and the hole filling portion50Va may be integrally formed to constitute the encapsulant50f. The encapsulant50fmay not cover the unit device chip30. The encapsulant50fmay be formed to be spaced apart from the unit device chip30. For example, the auxiliary encapsulation portion50S of the encapsulant50fmay be spaced apart from the unit device chip30.

Referring toFIG.8C, the semiconductor package4bmay include a package substrate100a, a semiconductor chip10aattached to an upper surface of the package substrate100a, an auxiliary chip20attached to a lower surface of the package substrate100a, a unit device chip30attached to the lower surface of the package substrate100a, and an encapsulant50gencapsulating the semiconductor chip10, the auxiliary chip20, and the unit device chip30together. The auxiliary chip20and the unit device chip30may be attached to the lower surface of the package substrate100awhile being spaced apart from each other. The package substrate100amay have at least one communication hole100Ha extending from an upper surface of the package substrate100ato a lower surface of the package substrate100aand penetrating the package substrate100a.

The encapsulant50gmay surround the semiconductor chip10a, the auxiliary chip20, and the unit device chip30. The encapsulant50gmay include a main encapsulation portion50M, an auxiliary encapsulation portion50Sa, an auxiliary underfill portion50US, and a hole filling portion50V. The auxiliary encapsulation portion50Sa may cover the auxiliary chip20and the unit device chip30together.

FIGS.9A and9Bare cross-sectional views illustrating a semiconductor package according to the inventive concept. In the description given with reference toFIGS.9A and9B, descriptions already given with reference toFIGS.1to2Bmay be omitted.

Referring toFIG.9A, the semiconductor package5may include a package substrate100, a semiconductor chip10attached to an upper surface of the package substrate100, an auxiliary chip20attached to a lower surface of the package substrate100, and a first encapsulant52encapsulating the semiconductor chip10. The package substrate100may have at least one communication hole100H extending from an upper surface of the package substrate100to a lower surface of the package substrate100and penetrating the package substrate100.

The semiconductor package5may further include a second encapsulant60filling a space between the upper surface of the package substrate100and the lower surface of the semiconductor chip10, a space between the lower surface of the package substrate100and an upper surface of the auxiliary chip20, and the at least one communication hole100H.

The second encapsulant60may include a main underfill portion60M, an auxiliary underfill portion60S, and a hole filling portion60V. The main underfill portion60M may fill a space between the first surface (i.e., the lower surface) of the semiconductor chip10and the upper surface of the package substrate100, and surround the plurality of chip connecting members18. The auxiliary underfill portion60S may fill a space between the upper surface of the auxiliary chip20and the lower surface of the package substrate100, and surround the plurality of chip terminals28. The hole filling portion60V may fill the communication hole100H.

The first encapsulant52may encapsulate the semiconductor chip10and the main underfill portion60M of the second encapsulant60on the upper surface of the package substrate100. The first encapsulant52and the second encapsulant60may be formed separately, so that the interface between the first encapsulant52and the second encapsulant60may be formed.

An upper end of the hole filling portion60V may be connected to the main underfill portion60M, and a lower end thereof may be connected to the auxiliary underfill portion60S. Each of the main underfill portion60M, the auxiliary underfill portion60S, and the hole filling portion60V may be referred to as distinguishing portions of the second encapsulant60. Each name of the distinguishing portions may represent a position at which each distinguishing portion is disposed in the encapsulant60for the convenience of description. The main underfill portion60M, the auxiliary underfill portion60S, and the hole filling portion60V may be integrally formed by a single manufacturing process to form the encapsulant60. The second encapsulant60may be made of, for example, a resin material formed by a capillary underfill method.

The main underfill portion60M may have a first main protrusion60MP and a second main protrusion60MF protruding outward from a space between the lower surface of the semiconductor chip10and the upper surface of the package substrate100. The first main protrusion60MP has a first extension length ED1in a horizontal direction (X direction or Y direction), and the second main protrusion60MF may have a second extension length ED2in a horizontal direction (X direction or Y direction). For example, the first main protrusion60MP may be formed at a first end of the space between the lower surface of the semiconductor chip10and the upper surface of the package substrate100, and the second main protrusion60MF may be formed at a second end, opposite to the first end, of the space between the lower surface of the semiconductor chip10and the upper surface of the package substrate100. Each of the first extension length ED1and the second extension length ED2may be a length in which each of the first main protrusion60MP and the second main protrusion60MF extends outward from a corresponding side surface of the semiconductor chip10. InFIG.9A, each of the first main protrusion60MP and the second main protrusion60MF is illustrated to extend in the first horizontal direction (X direction), but this is exemplary and not limited thereto. In some embodiments, each of the first main protrusion60MP and the second main protrusion60MF may extend in the second horizontal direction (Y direction), which is the front-back direction with respect toFIG.9A.

The second encapsulant60may be formed by dispensing an underfill material from the side of the second main protrusion60MF. The second extended length ED2may have a greater value than the first extended length ED1. In the second encapsulant60, the underfill material applied from the side of the second main protrusion60MF fills between the lower surface of the semiconductor chip10and the upper surface of the package substrate100, and may also fill a space between the upper surface of the auxiliary chip20and the lower surface of the package substrate100through the communication hole100H.

The auxiliary underfill portion60S may have a first auxiliary protrusion60SP1and a second auxiliary protrusion60SP2exposed to the outside from a space between the lower surface of the package substrate100and the auxiliary chip20. Each of the first auxiliary protrusion60SP1and the second auxiliary protrusion60SP2may have substantially the same extension length in the horizontal direction (X direction or Y direction).

In the semiconductor package5, after an underfill material for forming the second encapsulant60is first applied to the upper surface of the package substrate100, the underfill material is supplied to the space between the semiconductor chip10and the package substrate100and sequentially supplied along the communication hole100H to the lower surface of the package substrate100to form the second encapsulant60. Thus, the semiconductor package5does not require an additional space for applying the underfill material to the lower surface of the package substrate100. Therefore, a separation distance WD between the auxiliary chip20and the plurality of external connection terminals150may be reduced, thereby minimizing a horizontal area of the semiconductor package5, and thus, the size of the semiconductor package5, that is, a form factor, may be reduced.

Referring toFIG.9B, the semiconductor package5amay include a package substrate100, a semiconductor chip10attached to an upper surface of the package substrate100, an auxiliary chip20attached to a lower surface of the package substrate100, and a first encapsulant52encapsulating the semiconductor chip10and the auxiliary chip20. The package substrate100may have at least one communication hole100H extending from an upper surface of the package substrate100to a lower surface of the package substrate100and penetrating the package substrate100. The semiconductor package5amay further include a second encapsulant60filling a space between the upper surface of the package substrate100and the lower surface of the semiconductor chip10, a space between the lower surface of the package substrate100and the lower surface of the auxiliary chip20, and the at least one communication hole100H.

The semiconductor package5amay further include a unit device chip30attached to the lower surface of the package substrate100. The auxiliary chip20and the unit device chip30may be attached to the lower surface of the package substrate100while being spaced apart from each other. The second encapsulant60may be formed to be spaced apart from the unit device chip30.

In the semiconductor package5a, after an underfill material for forming the second encapsulant60is first applied to the upper surface of the package substrate100, the underfill material is supplied to the space between the semiconductor chip10and the package substrate100and sequentially supplied along the communication hole100H to the lower surface of the package substrate100to form the second encapsulant60. Thus, the semiconductor package5adoes not require an additional space for applying the underfill material to the lower surface of the package substrate100. Accordingly, the area occupied by the auxiliary chip20and the space for the underfill material injection on the lower surface of the package substrate100is reduced, and thus the unit device chip30may be attached to the lower surface of the package substrate100without increasing the area of the package substrate100or at a minimum increase of the area of the package substrate100.

FIG.10is a cross-sectional view illustrating a semiconductor package according to the inventive concept. In the description given with reference toFIG.10, descriptions already given with reference toFIGS.1to9Bmay be omitted.

Referring toFIG.10, the semiconductor package6may include a package substrate100b, a semiconductor chip10attached to an upper surface of the package substrate100b, a first auxiliary chip20aand a second auxiliary chip20battached to a lower surface of the package substrate100, and a first encapsulant50hencapsulating the first semiconductor chip10and the auxiliary chip20b. The first auxiliary chip20aand the second auxiliary chip20bmay be attached to the lower surface of the package substrate100bwhile being spaced apart from each other. The package substrate100bmay have at least one communication hole100H1and at least one communication hole100H2extending from an upper surface of the package substrate100bto a lower surface of the package substrate100band penetrating the package substrate100b. Each of the first communication hole100H1and the second communication hole100H2may allow a space on the upper surface of the package substrate100bto communicate with a space on the lower surface of the package substrate100b. In some embodiments, the first communication hole100H1may connect a first space between the lower surface of a semiconductor substrate12and an upper surface of the package substrate100bto a second space between a lower surface of the package substrate100band an upper surface of the first auxiliary chip20a. In some embodiments, the second communication hole100H2may connect a third space adjacent to the upper surface of the package substrate100bto a fourth space between the lower surface of the package substrate100band an upper surface of the second auxiliary chip20b.

The semiconductor package6may further include a second encapsulant60filling a space between the upper surface of the package substrate100band the lower surface of the semiconductor chip10, a space between the lower surface of the package substrate100band the lower surface of the auxiliary chip20a, and the at least one communication hole100H1. The second encapsulant60may include a main underfill portion60M, a first auxiliary underfill portion60S, and a hole filling portion60V. The main underfill portion60M may fill a space between the first surface (i.e., the lower surface) of the semiconductor chip10and the upper surface of the package substrate100, and surround the plurality of chip connecting members18. The auxiliary underfill portion60S may fill a space between the upper surface of the first auxiliary chip20aand the lower surface of the package substrate100b, and surround the plurality of chip terminals28a. The first hole filling portion60V may fill the communication hole100H.

The first encapsulant50hmay include a main encapsulation portion50Ma, an auxiliary encapsulation portion50S, a second auxiliary underfill portion50US, and a second hole filling portion50Va. The main encapsulation portion50Ma, the auxiliary encapsulation portion50S, the second auxiliary underfill portion50US, and the second hole filling portion50Va may be integrally formed to constitute the first encapsulant50h. The main encapsulation portion50Ma may cover the semiconductor chip10and the main underfill portion60M of the second encapsulant60on the upper surface of the package substrate100b. The auxiliary encapsulation portion50S may cover the second auxiliary chip20bon the lower surface of the package substrate100b. The second auxiliary underfill portion50US may fill a space between the upper surface of the second auxiliary chip20band the lower surface of the package substrate100b, and surround the plurality of second chip terminals28b. The second hole filling portion50Va may fill the second communication hole100H2. The auxiliary encapsulation portion50S and the second auxiliary underfill portion50US may be spaced apart from the first auxiliary underfill portion60S on the lower surface of the package substrate100b.

In some embodiments, the auxiliary encapsulation portion50S may cover the first auxiliary chip20a, the first auxiliary underfill portion60S, and the second auxiliary chip20btogether, similarly to the auxiliary encapsulation portion50Sb as shown inFIG.7B.

FIG.11is a cross-sectional view illustrating a semiconductor package according to the inventive concept. In the description given with reference toFIG.11, descriptions already given with reference toFIGS.1to8Cmay be omitted.

Referring toFIG.11, the semiconductor package7may include a package substrate100, a first semiconductor chip10attached to an upper surface of the package substrate100, a second semiconductor chip70attached to the first semiconductor chip10, an auxiliary chip20attached to a lower surface of the package substrate100, and an encapsulant50encapsulating the first semiconductor chip10, the second semiconductor chip70, and the auxiliary chip20.

The first semiconductor chip10may include a first semiconductor substrate12having an active surface and an inactive surface opposite to each other, a first semiconductor device14formed at the active surface of the first semiconductor substrate12, and a plurality of first chip pads16disposed on a first surface of the first semiconductor chip10. The first semiconductor chip10and the package substrate100may be electrically connected with each other through a plurality of first chip connecting members18. The first semiconductor chip10may be the semiconductor chip10shown inFIG.1.

The second semiconductor chip70may include a second semiconductor substrate72having an active surface and an inactive surface opposite to each other, a second semiconductor device74formed at the active surface of the second semiconductor substrate72, and a plurality of second chip pads76disposed on a first surface of the second semiconductor chip70.

In some embodiments, the second semiconductor chip70may have a face-up arrangement in which a second surface opposite to the first surface faces the first semiconductor chip10, and may be attached to an upper surface of the first semiconductor chip10. The second semiconductor chip70may have a die adhesive film75attached to the second surface and may be attached to the upper surface of the first semiconductor chip10. A plurality of second chip connecting members78may be connected between a plurality of second chip pads76of the second semiconductor chip70and a plurality of substrate upper surface pads122of the package substrate100. For example, the second chip connecting member78may be a bonding wire. The second semiconductor chip70and the package substrate100may be electrically connected with each other through a plurality of second chip connection members78.

The semiconductor package7is illustrated as the semiconductor package1as shown inFIG.1with the second semiconductor chip70, but may also be as the semiconductor packages1-1,1-2,1a,1b,2,2b,2-1,2-2,2a,2b,3,3a,4,4a, and4bas shown inFIGS.2A,2B,3A,3B,4,5A,5B,6A,6B,7A,7B,8A,8B, and8C, respectively, with the second semiconductor chip70.

FIG.12is a cross-sectional view illustrating a semiconductor package according to the inventive concept. In the description given with reference toFIG.12, descriptions already given with reference toFIGS.9A to11may be omitted.

Referring toFIG.12, the semiconductor package8may include a package substrate100, a first semiconductor chip10attached to an upper surface of the package substrate100, a second semiconductor chip70attached to the first semiconductor chip10, an auxiliary chip20attached to a lower surface of the package substrate100, and a first encapsulant52encapsulating the first semiconductor chip10and the second semiconductor chip70. The package substrate100may have at least one communication hole100H extending from an upper surface of the package substrate100to a lower surface of the package substrate100and penetrating the package substrate100. The semiconductor package8may further include a second encapsulant60filling a space between the upper surface of the package substrate100and the lower surface of the first semiconductor chip10, a space between the lower surface of the package substrate100and the lower surface of the auxiliary chip20, and the at least one communication hole100H1.

The second semiconductor chip70may have a die adhesive film75attached to the second surface and may be attached to the upper surface of the first semiconductor chip10. A plurality of second chip connecting members78may be connected between a plurality of second chip pads76of the second semiconductor chip70and a plurality of substrate upper surface pads122of the package substrate100. For example, the second chip connecting member78may be a bonding wire.

The semiconductor package8is illustrated as the semiconductor package5as shown inFIG.9Awith the second semiconductor chip70, but may also be as the semiconductor packages5aand6as shown inFIGS.9B and10with the second semiconductor chip70.

FIG.13is a cross-sectional view of a semiconductor package in the form of a package on package (PoP) according to embodiments of the inventive concept. In the description given with reference toFIG.13, descriptions already given with reference toFIGS.1to8Cmay be omitted.

Referring toFIG.13, a semiconductor package1000may be a package on package (PoP) type semiconductor package in which an upper package UP is attached on a lower package LP.

The lower package LP may include a first package substrate100c, a lower semiconductor chip10attached to an upper surface of the first package substrate100c, an auxiliary chip20attached to a lower surface of the first package substrate100c, an encapsulant50encapsulating the lower semiconductor chip10and the auxiliary chip20, and a second package substrate200covering the encapsulant50.

The lower semiconductor chip10may include a lower semiconductor substrate12having an active surface and an inactive surface opposite to each other, a lower semiconductor device14formed at the active surface of the lower semiconductor substrate12, and a plurality of lower chip pads16disposed on the first surface of the lower semiconductor chip10. The lower semiconductor chip10and the first package substrate100cmay be electrically connected with each other through a plurality of lower chip connecting members18. The lower semiconductor chip10may be the semiconductor chip10as shown inFIG.1.

The first package substrate100cis substantially the same as the package substrate100shown inFIG.1, and thus overlapping descriptions may be omitted. The first package substrate100cmay include a first substrate base110, a plurality of first substrate upper surface pads122and a plurality of first substrate lower surface pads124respectively disposed on an upper surface and a lower surface of the first substrate base110, and a plurality of substrate vias128passing through at least a portion of the first substrate base110. In some embodiments, the first substrate base110may have a stacked structure of a plurality of first base layers, and the first package substrate100cmay further include a plurality of first internal wiring patterns126disposed on an upper surface and/or a lower surface of each of the plurality of first base layers. In some embodiments, the first package substrate100cmay further include a first solder resist layer130covering the upper and lower surfaces of the first substrate base110and including a first upper surface solder resist layer132and a first lower surface solder resist layer134.

The encapsulant50is substantially similar to the encapsulant50shown inFIG.1, but may have a plurality of through-via holes50VH extending from an upper surface of the encapsulant50to a lower surface of the encapsulant50. A plurality of through-connecting members58may be disposed in the plurality of through-via holes50VH.

The second package substrate200may include a second substrate base210, a plurality of second substrate upper surface pads222and a plurality of second substrate lower surface pads224respectively disposed on the upper and lower surfaces of the second substrate base210, and a plurality of second substrate vias228passing through at least a portion of the second substrate base210. In some embodiments, the second package substrate200may further include a plurality of second internal wiring patterns similar to the plurality of first internal wiring patterns126of the first package substrate100. In some embodiments, the second package substrate200may further include a second solder resist layer230covering the upper and lower surfaces of the second substrate base210and including a second upper surface solder resist layer232, and a second lower surface solder resist layer234. The second package substrate200is substantially similar to the first package substrate100c, and thus overlapping descriptions may be omitted.

The plurality of through connection members58may electrically connect some of the plurality of second substrate lower surface pads224to the plurality of first substrate upper surface pads122.

The upper package UP may include a third package substrate300, an upper semiconductor chip410attached to an upper surface of the third package substrate300, and an upper molding member450surrounding the upper semiconductor chip410.

The third package substrate300may include a third substrate base310, a plurality of third substrate upper surface pads322and a plurality of third substrate lower surface pads324respectively disposed on the upper and lower surfaces of the third substrate base310, and a plurality of third substrate vias328passing through at least a portion of the third substrate base310. In some embodiments, the third package substrate300may further include a plurality of third internal wiring patterns similar to the plurality of first internal wiring patterns126of the first package substrate100. In some embodiments, the third package substrate300may further include a third solder resist layer330covering the upper and lower surfaces of the third substrate base310and including a third upper surface solder resist layer332, and a third lower surface solder resist layer334. The third package substrate300is substantially similar to the second package substrate200, and thus overlapping descriptions may be omitted.

The upper semiconductor chip410may include an upper semiconductor substrate412having an active surface and an inactive surface opposite to each other, an upper semiconductor device414formed at the active surface of the upper semiconductor substrate412, and a plurality of upper chip pads416disposed on the first surface of the upper semiconductor chip410. The upper semiconductor chip410and the third package substrate300may be electrically connected with each other through a plurality of upper chip connecting members418. The plurality of upper chip connecting members418may connect the plurality of upper chip pads416to the plurality of third substrate upper surface pads322, respectively. The upper semiconductor chip410is substantially similar to the lower semiconductor chip10, and thus overlapping descriptions may be omitted.

In some embodiments, the lower semiconductor chip10may be a central processing unit chip, a graphic processing unit chip, or an application processor chip, and the upper semiconductor chip410may be a memory semiconductor chip.

In some embodiments, an upper underfill layer460surrounding the plurality of upper chip connecting members418may be between the second surface (i.e., the lower surface) of the upper semiconductor chip410and the third package substrate300. In some embodiments, the upper molding member450may cover the upper surface of the third package substrate300and surround the upper semiconductor chip410and the upper underfill layer460.

FIG.13illustrates that the upper semiconductor chip410has a face-up arrangement and is attached to the upper surface of the third package substrate300, but is not limited thereto. For example, the upper semiconductor chip410may have a face-down arrangement and may be attached to the upper surface of the third package substrate300.

The lower package LP of the semiconductor package1000is shown to be configured similarly to the semiconductor package1shown inFIG.1, but may be configured similarly to the semiconductor package1-1,1-2,1a,1b,2,2-1,2-2,2a,2b,3,3a,4,4a,4bas shown inFIGS.2A,2B,3A,3B,4,5A,5B,6A,6B,7A,7B,8A,8B, and8C, respectively.

FIG.14is a cross-sectional view of a PoP-type semiconductor package according to embodiments of the inventive concept. In the description given with reference toFIG.14, descriptions already given with reference toFIGS.9A to11andFIG.13may be omitted.

Referring toFIG.14, a semiconductor package2000may be a package on package (PoP) type semiconductor package in which an upper package UP is attached on a lower package LPa.

The lower package LPa may include a first package substrate100c, a lower semiconductor chip10attached to an upper surface of the first package substrate100c, an auxiliary chip20attached to a lower surface of the first package substrate100c, a first encapsulant52encapsulating the lower semiconductor chip10and the auxiliary chip20, and a second package substrate200covering the first encapsulant52.

The first encapsulant52is substantially similar to the first encapsulant52as shown inFIG.9A, but may have a plurality of through-via holes52H extending from an upper surface of the first encapsulant52to a lower surface of the first encapsulant52. The plurality of through-connecting members58may be disposed in the plurality of through-via holes52H.

The second package substrate200may further include a second encapsulant60filling between the upper surface of the first package substrate100cand the lower surface of the lower semiconductor chip10, between the lower surface of the first package substrate100cand the lower surface of the auxiliary chip20, and the at least one communication hole100H.

The upper package UP may include a third package substrate300, an upper semiconductor chip410attached to an upper surface of the third package substrate300, and an upper molding member450surrounding the upper semiconductor chip410.

The lower package LPa of the semiconductor package2000is shown to be configured similarly to the semiconductor package5as shown inFIG.9A, but may be configured similarly to the semiconductor packages5aand6as shown inFIGS.9B and10.

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.