Patent ID: 12229452

DETAILED DESCRIPTION

Aspects of the present disclosure are directed to managing queues in a memory sub-system using a read counter for quality of service (QOS) design. A memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction withFIG.1. In general, a host system can utilize a memory sub-system that includes one or more memory components (also hereinafter referred to as “memory devices”). The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

A memory sub-system can include one or more memory cells, such as negative-and (NAND) memory cells (e.g., NAND flash memory cells). Such memory cells are capable of remaining in a charged or uncharged state for prolonged periods of time. Whether the memory cells resides in a charged state or an uncharged state is representative of a logic value stored to the cell (e.g., a logic “0” or a logic “1”). Multiple NAND cells can be strung together, and strings can be replicated multiple times within a single block. Each column of cells can be referred to as a “string” and each row can be referred to as a “page.” Multiple strings and pages of NAND cells can collectively be referred to as a “block,” multiple blocks can be included in a single plane, and multiple planes can be included in a memory die (e.g., a logical unit number (LUN)).

In traditional access operations of NAND cells, commands can be constantly transmitted to various memory dies. The commands can be associated with different access operations (e.g., read operations, write operations, etc.) having varying levels of priority. That is, it can be desirable for a host read command to be transmitted to a particular memory die before a read command or write command is transmitted to the same die. However, because memory sub-systems include many dies, and each die can be associated with a multitude commands and command types, traditional access operations can be unable to effectively prioritize transmitting commands. Accordingly, traditional access operations can result in backpressure on a local memory controller (e.g., due to a backlog of commands to be issued), which can tie up resources needed by the memory sub-system to issue commands. Thus a system to effectively manage commands, and command queues, at a die level may be beneficial.

Aspects of the present disclosure address the above and other deficiencies by managing queues of a memory sub-system at a die level. For example, each memory die of a memory sub-system can be associated with a queue (e.g., a memory die queue) for managing commands associated with the respective die. Further, each memory die queue can include multiple sub-queues (e.g., priority queues) for managing commands associated with particular priority levels. Thus when a command associated with a memory die is received, an associated request (e.g., a request for the command) can be assigned to the associated memory die queue (and to the relevant priority queue) for issuance. Based on the priority level associated with the command, it can be issued by a local memory controller.

For example, a memory die queue associated with a particular memory die of a memory sub-system can include one or more (e.g., three) priority queues. Each priority queue can be associated with (e.g., reserved for) commands associated with a particular priority level. One priority queue can be associated with commands having a priority level (e.g., a highest: a most-urgent), another priority queue can be associated with commands having a different priority level (e.g., an intermediate: a middle priority level), and an additional priority queue can be associated with commands having yet another (e.g., a lowest: a least-urgent) priority level. When a command for the memory die is received, it can be assigned to a priority queue based on its associated priority level, which can be predefined. Accordingly, commands in a higher priority queue can be issued before commands in a lower priority queue—i.e., a command in the highest priority queue can be issued before a command in the low priority queue. Further, when a command is assigned to a higher-priority queue when commands from a lower-priority queue are being issued, the issuance of the commands in the lower-priority queue can be temporarily paused in order for the higher-priority command to be issued. Once the higher-priority command is issued, the issuance of the commands in the lower-priority queue can resume. Such techniques can be performed die-by-die (e.g., each memory die can include respective queues), which can reduce backpressure that a local memory controller may otherwise incur, and may allow for the sub-system to issue commands based on available resources.

However, the commands having different priority levels in respective priority queues may, in some examples, result in a backlog of commands in the lower priority queues. For example, in the situation where commands having a highest priority level are assigned to a one queue and commands having a lower priority level are assigned to a different queue, the commands in the different queue may be unable to be issued when there is a constant or steady stream of commands arriving at the high priority queue. For instance, the commands in the other queue (e.g., the lower priority queue) must wait until the high priority queue have issued. Accordingly, aspects of the described techniques may associate a counter (or timer) with each queue (e.g., or with each priority queue) which can be leveraged to resolve this issue. For example, the counter (or timer) may be associated with the high priority queue (e.g., the higher priority queue) that tracks or otherwise monitors the number of commands (e.g., high priority commands in the high priority queue) have issued. The memory sub-system (or die) may determine that a threshold number of the high priority commands of the high priority queue have issued without a command from the low priority commands (e.g., the commands in the low priority or lower priority queue) having issued. When the counter reaches the threshold number of issued high priority commands from the high priority queue, command(s) from the low priority queue will be issued. For example, one, two, three, or some other number of commands from the low priority queue may issue once the counter reaches the threshold number for the number of issued high priority commands. The counter may then be reset or otherwise re-instantiated to once again monitor the number of commands issuing from the high priority queue without commands from the low priority queue having issued.

Features of the disclosure are initially described in the context of a computing environment as described with reference toFIG.1. Features of the disclosure are described on the context of methods, firmware queue, command pool, etc., as described with reference toFIGS.2-4. These and other features of the disclosure are further illustrated by and described with reference to a computer system that relates to a read counter for a quality of service design as described with reference toFIG.5.

FIG.1is an example of a computing environment100that includes memory sub-system110in accordance with some embodiments of the present disclosure. The memory sub-system110can include media, such as one or more volatile memory devices (e.g., memory device140), one or more non-volatile memory devices (e.g., memory device130), or a combination of such.

A memory sub-system110can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of a storage device include a solid-state drive (SSD), a flash drive, a universal serial bus (USB) flash drive, an embedded Multi-Media Controller (eMMC) drive, a Universal Flash Storage (UFS) drive, and a hard disk drive (HDD). Examples of memory modules include a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), and a non-volatile DIMM (NVDIMM).

The computing environment100can include a host system105that is coupled with one or more memory sub-systems110. In some examples, the host system105is coupled with different types of memory sub-systems110.FIG.1illustrates one example of a host system105coupled with one memory sub-system110. The host system105uses the memory sub-system110, for example, to write data to the memory sub-system110and read data from the memory sub-system110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

The host system105can be a computing device such as a desktop computer, laptop computer, network server, mobile device, a vehicle (e.g., airplane, drone, train, automobile, or other conveyance), Internet of Things (IoT) enabled device, embedded computer (e.g., one included in a vehicle, industrial equipment, or a networked commercial device), or such computing device that includes a memory and a processing device. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, USB interface, a Fiber Channel, a Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), etc. The physical host interface can be used to transmit data between the host system105and the memory sub-system110. The host system105can further utilize an non-volatile memory Express (NVMe) interface to access the memory components (e.g., memory devices130) when the memory sub-system110is coupled with the host system105by the PCIe interface. The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system110and the host system105.

The memory devices can include any combination of the different types of non-volatile memory devices and/or volatile memory devices. The volatile memory devices (e.g., memory device140) can be, but are not limited to, random access memory (RAM), such as dynamic RAM (DRAM) and synchronous DRAM (SDRAM).

Some examples of non-volatile memory devices (e.g., memory device130) include negative-and (NAND) type flash memory and write-in-place memory, such as three-dimensional cross-point (“3D cross-point”) memory. One type of memory cell, for example, single level cells (SLC) can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple level cells (TLCs), and quad-level cells (QLCs), can store multiple bits per cell. In some embodiments, each of the memory devices130can include one or more array's of memory cells such as SLCs, MLCs, TLCs, QLCs, or any combination of such. In some examples, a particular memory component can include an SLC portion, and an MLC portion, a TLC portion, or a QLC portion of memory cells. The memory cells of the memory devices130can be grouped as memory pages or memory blocks that can refer to a unit of the memory component used to store data.

Although non-volatile memory components such as NAND type flash memory are described, the memory device130can be based on any other type of non-volatile memory, such as ROM, phase change memory (PCM), self-selecting memory, other chalcogenide based memories, ferroelectric RAM (FeRAM), magneto RAM (MRAM), negative-or (NOR) flash memory, electrically erasable programmable ROM (EEPROM), and a cross-point array of non-volatile memory cells. A cross-point array of non-volatile memory can perform bit storage based on a change of bulk resistance, in conjunction with a stackable cross-gridded data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform a write in-place operation, where a non-volatile memory cell can be programmed without the non-volatile memory cell being previously erased.

In some examples, a material of a storage element of a memory cell can include a chalcogenide material or other alloy including selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In), or various combinations thereof. In some examples, a chalcogenide material having primarily selenium (Se), arsenic (As), and germanium (Ge) can be referred to as a SAG-alloy. In some examples, a SAG-alloy can also include silicon (Si) and such chalcogenide material can be referred to as SiSAG-alloy. In some examples, SAG-alloy can include silicon (Si) or indium (In) or a combination thereof and such chalcogenide materials can be referred to as SiSAG-alloy or InSAG-alloy, respectively, or a combination thereof. In some examples, the chalcogenide glass can include additional elements such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular forms.

The memory sub-system controller115(or controller115for simplicity) can communicate with the memory devices130to perform operations such as reading data, writing data, moving data, or erasing data at the memory devices130and other such operations. The memory sub-system controller115can include hardware such as one or more integrated circuits and/or discrete components, a buffer memory, or a combination of such. The hardware can include a digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller115can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), digital signal processor (DSP)), or another suitable processor.

The memory sub-system controller115can include a processor120(e.g., a processing device) configured to execute instructions stored in a local memory125. In the illustrated example, the local memory125of the memory sub-system controller115includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory sub-system110, including handling communications between the memory sub-system110and the host system105.

In some examples, the local memory125can include memory registers storing memory pointers, fetched data, etc. The local memory125can also include ROM for storing micro-code. While the example memory sub-system110inFIG.1has been illustrated as including the memory sub-system controller115, in another example of the present disclosure, a memory sub-system110cannot include a memory sub-system controller115, and can instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory sub-system).

In general, the memory sub-system controller115can receive commands or operations from the host system105and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices130. The memory sub-system controller115can be responsible for other operations such as wear leveling operations, garbage collection procedures, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical block address and a physical block address that are associated with the memory devices130. The memory sub-system controller115can further include host interface circuitry to communicate with the host system105via the physical host interface. The host interface circuitry can convert the commands received from the host system into command instructions to access the memory devices130as well as convert responses associated with the memory devices130into information for the host system105.

The memory sub-system110can also include additional circuitry or components that are not illustrated. In some examples, the memory sub-system110can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., a row decoder and a column decoder) that can receive an address from the memory sub-system controller115and decode the address to access the memory devices130.

In some examples, the memory devices130include local media controllers135that operate in conjunction with memory sub-system controller115to execute operations on one or more memory cells of the memory devices130. In some examples, the memory devices140include local media controllers145that operate in conjunction with the memory sub-system controller115to execute operations on one or more memory cells of the memory devices140.

The memory sub-system110includes a queue manager150that manages commands according to an associated priority level. For example, each memory die of a memory sub-system can be associated with a memory die queue. The memory die queues can each include one or more priority queues where commands (e.g., read commands, write commands, host read commands, etc.) are allocated for issuance. When a command associated with a particular die is received, the queue manager150can determine a priority level associated with the command (i.e., the queue manager150can determine a type of the command) and allocate the command to a respective priority queue associated with the die. Commands may be issued from respective priority queues based on the associated priority levels. Thus commands associated with queues having a higher priority level can be issued before commands associated with queues having relatively lower priority levels. The commands can be issued on a die-by-die level (e.g., higher priority commands of a die are issued before lower priority commands of the same die) or globally (e.g., higher priority commands are issued before lower priority commands regardless of the die). In either example, issuing commands according to a priority level of the respective command can reduce backpressure that a local memory controller may otherwise incur, and may allow for the memory sub-system to issue commands based on available resources.

Accordingly, the queue manager150may assign high priority commands to a high priority queue of a memory die of the memory sub-system110, the high priority queue being associated with a high priority level. The memory die may also include a low priority queue associated with a low priority level that is different from (e.g., lower than) the high priority level. As discussed above, in some examples the queue manager150may issue commands from the high priority queue (e.g., the priority queue associated with the highest priority level) before issuing commands from the low priority queue (e.g., the priority queue associated with a lower priority level with respect to the high priority level). In some cases, this may create the situation where commands in the low priority queue (and a third queue, a fourth queue, etc., having lower respective priority level(s)) must wait an extended amount of time before being processed. Accordingly, aspects of the described techniques may associate a counter (or timer) with at least the high priority queue that tracks or otherwise monitors the number of commands being issued from the high priority queue. The commands in the low priority queue may also be tracked or otherwise monitored by the counter associated with the high priority queue and/or by a low priority counter associated with the low priority queue. Based on the counter(s), it may be determined that the number of commands issuing from the high priority queue without commands from the low priority queue having issued has reached a threshold number, e.g., the number of commands from the high priority queue and/or for a threshold amount of time. Accordingly, command(s) from the low priority queue may issue in response to the threshold number of commands from the high priority queue having issued. This may serve as a pressure relief valve preventing/mitigating backpressure on the memory sub-system110with respect to the low priority queue (and any other queues having a lower priority level than the high priority queue).

In some examples, the memory sub-system controller115includes at least a portion of the queue manager150. For example, the memory sub-system controller115can include a processor120(e.g., a processing device) configured to execute instructions stored in local memory125for performing the operations described herein. In some examples, the queue manager150is part of the host system105, an application, or an operating system.

FIG.2is a flow diagram of an example method200for managing queues using a read counter for quality of service design in accordance with some embodiments of the present disclosure. The method200can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some examples, the method200is performed by the queue manager150ofFIG.1. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated examples should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various examples. Thus, not all processes are required in every example. Other method flows are possible.

The method200can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method200is performed by the queue manager150ofFIG.1. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

At operation205, the processing device can assign high priority commands to a high priority queue and low priority commands to a low priority queue of a memory die of a memory sub-system. The high priority queue can be associated with a high priority level and the memory die can include a low priority queue associated with a low priority level different from the high priority level. The low priority queue can include a low priority command and the high priority command and the low priority command can each be associated with a respective operation to be performed on the memory sub-system.

In some examples, the high priority level is a higher priority level than the low priority level. In some example, the high priority commands may be examples of host read commands. In some examples, the low priority commands may be examples of other commands, e.g., host write command(s), read command(s), write command(s), erase command(s), and the like. Accordingly, host read commands may be assigned or otherwise associated with a higher priority level than other command types.

At operation210, the processing device can issue the high priority command from the high priority queue. The high priority command from the high priority queue may be issued without issuing a low priority command from the low priority queue based at least in part on the high priority and low priority levels.

In some examples, the method200can include assigning or otherwise associating a counter (or timer) with the high priority queue. In some examples, the method200may include assigning or otherwise associating a counter (or timer) with each queue of the memory sub-system. In some example, each counter may monitor or otherwise manage counting the number of commands issuing from the respective queue. For example, each counter associated with the respective queue may count each time a command issues from the queue. In another example, a single counter (or subset of counters) may be used to monitor or otherwise manage counting the number of commands issuing from each queue.

At operation215, the processing device can increment the counter associated with the high priority queue. For example, the counter (or timer) may be incremented each time a command from the high priority queue issues. In some examples, the counter may increment each time a command from the high priority queue issues, each time a command from the high priority queue issues without a corresponding command from the low priority queue issuing, and the like. In some examples, the counter may track the number of commands issuing from the high priority counter and/or the number of commands assigned to the low priority queue.

In some examples, the method200can include incrementing a low priority counter associated with the low priority queue each instance that a command from the high priority queue issues without a command from the low priority queue has issued. In some examples, the method200can include the processing device determining that a command from the low priority queue has not issued for a threshold amount of time (e.g., the counter is based on a timer and/or there is a separate timer instantiated). In this example, the threshold number of commands issuing from the high priority queue without a command issuing from the low priority queue may be based on the threshold amount of time.

At operation220, the processing device can determine whether a threshold number of commands from the high priority queue have issued without a command from the low priority queue having issued. In some examples, the threshold number for the counter (or timer) may be selected or otherwise set to a value that prevents backpressure from building on the processing device due to an excessive number of commands in the low priority queue backing up. For example, the threshold number may be set to a number (or time period) selected based on system throttling, load balancing, fairness, and the like.

If, at operation220, the processing device determines that the counter has not reached the threshold number, the method200may return to the operation210and continue issuing command(s) from the high priority queue.

If, at operation220, the processing device determines that the counter has reached the threshold number, the method200may continue to operation225where the processing device issues a command (or commands) from the low priority queue. In some examples, the command from the low priority queue may issue before issuing another command from the high priority queue.

In some examples, the method200can include issuing a plurality of commands from the low priority queue before issuing the next command from the high priority queue. In some examples, the method200can include resetting the counter after issuing the command(s) from the low priority queue. In some examples, the processing device may resume issuing commands from the high priority queue after issuing the command(s) from the low priority queue (e.g., return to operation210).

Although the method200is generally described with reference to a processing device managing the high priority and low priority queues, it is to be understood that these techniques may be implemented across the processing device and in any number of queues of memory dies in the memory sub-system. For example, the processing device may assign commands to a plurality of high priority queues (e.g., on one or more dies), with each of the high priority queues being associated with a higher priority level and having an associated counter (or timer). The processing device may also assign commands to a plurality of low priority queues, with each of the low priority queues being associated with a lower priority level than the commands in the high priority queue. The processing device may determine, for each high priority queue and low priority queue, that the threshold number of commands from the high priority queue has issued without a command from the low priority queue having issued. The processing device may then issue command(s) from the low priority queue(s) based on the counter reaching the threshold number.

FIG.3Aillustrates an example of a firmware queue300-athat supports managing queues using a read counter for quality of service design in accordance with some embodiments of the present disclosure. The firmware queue300-aillustrates a plurality of memory die queues305(e.g., LUN queues305) that each include one or more priority queues. For example, a first memory die queue305can include priority queues310,310-a, and310-b. In some examples, priority queue310can correspond to a high priority queue, priority queue310-acan correspond to a low priority queue, and priority queue310-bcan correspond to a lowest priority queue. The priority queues310can include particular commands (e.g., requests to complete commands), and the commands can be issued by a local memory controller (e.g., a flash memory controller) according to the priority level of the respective priority queue310. In some examples, commands can be assigned to a priority queue310on-the-fly, which may result in the issuance of other commands (associated with different priority levels) being temporarily suspended. Incorporating queues at a memory die level can reduce backpressure that a local memory controller may otherwise incur, and may allow for the sub-system to issue commands based on available resources.

As discussed herein, the memory die queue305can include priority queues310,310-a, and310-b, which may correspond to a high priority queue, a low priority queue, and a lowest priority queue, respectively. In some examples, the first priority queue310can be assigned a highest priority level (e.g., relative to the low priority and lowest priority queues). By assigning the priority queue310a highest priority level, any command pertaining to the associated memory die that is placed in the priority queue310can be issued (e.g., sent to a local memory controller) before commands in the priority queues310-aand310-b. Similarly, the low priority queue310-acan be assigned an intermediate priority level (e.g., relative to the high priority and lowest priority queues). By assigning the priority queue310-aan intermediate priority level, any command pertaining to the associated memory die that is placed in the priority queue310-acan be issued before commands in the priority queue310-b. In other examples, the third priority queue310-bcan be assigned a lowest priority level (e.g., relative to the high priority and low priority queues). By assigning the priority queue310-ba lowest priority level, any command pertaining to the associated memory die that is placed in the priority queue310-bcan be issued only when priority queues310and310-aare empty (e.g., they do not contain any commands).

By way of example, the first memory die queue305can include command328in the priority queue310and commands330and330-ain the priority queue310-a. The first memory die queue305can also include commands335,335-a, and335-bin the priority queue310-b. In some examples, each of the commands in the priority queues310,310-a, and310-bcan be different commands that are received at different times. That is, commands can be entered into the priority queues310,310-a, and310-bas they are issued. Accordingly, because the priority queue310can be associated with a higher priority level than the priority queues310-aand310-b, the command328can be issued before the commands330,330-a,335,335-a, and335-b.

Additionally or alternatively, one or more of the commands335,335-a, and335-bcan be entered into the priority queue310-bbefore the commands328,330, and/or330-aare entered into the priority queues310and310-a, respectively. The commands in the priority queue310-bcan be issued (e.g., individually: one-by-one) until a command is entered into either of the priority queue310or the priority queue310-a. When a command is entered into either of the priority queues310or310-a, commands in the priority queue310-bmay not be issued. That is, any commands in the priority queue310-bcan be paused (e.g., placed on hold: suspended) until all commands in the priority queues310and/or310-aare issued. Upon issuing all commands in the priority queues310and/or310-a, any commands in the priority queue310-bcan be issued (or continue being issued). Similarly, commands in the priority queue310can be prioritized over commands in the priority queue310-a. Accordingly, any commands in the priority queue310-acan be paused (e.g., placed on hold: suspended) until all commands in the priority queue310are issued. When commands are satisfied (e.g., the requests from the queues are passed to a local memory controller), the associated command can be entered into a global pool shown inFIG.3B. Commands in the global pool can be issued by a local memory controller.

In some examples, the second memory die queue305-acan include commands340,340-a, and340-bin the priority queue315-a. The second memory die queue305-acan also include commands345,345-a, and345-bin the priority queue315-b. As shown inFIG.3Athe priority queue315can be temporarily empty (e.g., NULL), but can receive one or more commands (e.g., at a subsequent time; at a different time than shown). In some examples, each of the commands in the priority queues315-aand315-bcan be different commands that are received at different times. That is, commands can be entered into the priority queues315-aand315-bas they are issued. In some examples, the commands can be entered at a same or different time than the commands entered into the priority queues310-aand310-bof the first memory die queue305. Because the priority queue315-acan be associated with a higher priority level than the priority queue315-b, the commands340,340-a, and340-bcan be issued before the commands345,345-a, and345-b.

As discussed above with respect to the memory die queue305, one or more of the commands345,345-a, and345-bcan be entered into the priority queue315-bbefore the commands340,340-aand/or340-bare entered into the priority queue315-a. The commands in the priority queue315-bcan be issued (e.g., individually: one-by-one) until a command is entered into the priority queue315-a. When a command is entered into the priority queue315-a, commands in the priority queue315-bmay not be issued. That is, any commands in the priority queue315-bcan be paused (e.g., placed on hold: suspended) until all commands in the priority queue315-aare issued. Upon issuing all commands in the priority queue315-a, any commands in the priority queue315-bcan be issued (or continue being issued). As discussed herein, when commands (e.g., the requests for the commands) are issued from a queue, they can be entered into a global pool shown inFIG.3B. Commands in the global pool can be issued by a local memory controller.

In some examples, commands may be entered into corresponding priority queues of different memory die queues. For example, the memory die queue305and the memory die queue305-acan both include highest, lower, and lowest priority queues. Accordingly, commands can be issued from corresponding priority queues of different memory die queues either on a die-by-die basis or globally (e.g., based on corresponding priority queues of different memory die queues). For example, the priority queue310-acan include commands330and330-a, and the priority queue315-acan include commands340,340-a, and340-b. Because, at any one time, both priority queues can include one or more of the commands, the commands can either be issued on a die-by-die basis—e.g., memory die queue305can issue commands according to its own priority queues and memory die queue305-acan issue commands according to its own priority queues). Or the respective commands can be issued based on an order that the commands were entered into the respective priority queues—e.g., commands330,330-a,340,340-a, and340-bcan be issued based on the order that each command was entered into the respective priority queue because each command is associated with a same priority level.

In some examples, the firmware queue300-acan also include a third memory die queue305-band a fourth memory die queue305-c. The fourth memory die queue305-ccan also be or represent an nthmemory die queue of the firmware queue300-a. That is, the firmware queue300-acan include a plurality of memory die queues that correspond to the memory dies of the memory sub-system. In some examples, the third memory die queue305-band fourth memory die queue305-ccan each include one or more priority queues for commands. For example, the third memory die queue305-bcan include commands350,350-a, and350-bin the priority queue320-aand commands355,355-a, and355-bin the priority queue320-b. As shown inFIG.3Athe priority queues of the fourth memory die queue305-ccan be temporarily empty (e.g., NULL), but can receive one or more commands (e.g., at later time: at a different time).

As discussed with reference to memory die queues305and305-a, the memory die queues305-band305-ccan issue commands according to the priority levels associated with the respective priority queues. For example, commands350,350-a, and350-bcan be issued before commands355,355-a, and355-bdue to the priority level associated with the priority queue320-a. In other examples, and as discussed herein, issuance of the commands355,355-a, and355-bmay be temporarily suspended (e.g., paused: put on hold) when commands are assigned to the priority queue320-a. Upon the issuance of any commands in the priority queue320-a, the issuance of commands in the priority queue320-b(e.g., commands355,355-a, and/or355-b) may resume. Additionally or alternatively, commands associated with the third memory die queue305-band/or the fourth memory die queue305-ccan be issued on a die-by-die basis or globally (e.g., based on corresponding priority queues of different memory die queues).

In some examples, particular commands can be associated with predefined priority levels. For example, a high priority level (e.g., a highest priority level) can be associated with a host read command. That is, each time a host read associated with a particular memory die is issued, it can be assigned to the high priority queue of the memory die queue associated with the particular die. In other examples, a high priority level (e.g., an intermediate priority level) can be associated with a host write command, a read command, a write command, an erase command, or a combination thereof. All other types of commands can be associated with a lowest priority (or lower) priority level.

Accordingly, the processing device may assign high priority commands to a high priority queue (e.g., priority queue310by way of example only) of memory die305, with the high priority queue having or otherwise being associated with a high priority level. The processing device may assign low priority command(s) to a low priority queue (e.g., priority queues310-aand/or310-b), with the low priority queue having or otherwise being associated with a low priority level that is different from (e.g., lower than) the high priority level.

In some examples, a counter (or timer) may be associated with the high priority queue (or with each priority queue in some examples). Broadly, the counter (or timer) may track, monitor, or otherwise manage aspects of the number of instances that a command issues from the respective queue. In some examples, a counter may be associated with the high priority queue that tracks, monitor, or otherwise manages the number of high priority commands issuing from the high priority queue without a low priority command issuing from the low priority queue.

In some examples, the counter may be implemented in the situation where there is a mixed read/write workload. In this example, this may include maintaining a firmware counter on a per-die-basis, such that each memory die queue305maintains its own counter. In this example, the counter(s) for each memory die305may keep count or otherwise track the number of commands issuing from the respective priority queues. For example, a high priority counter may be maintained on the high priority memory die queue305that tracks the commands issuing from priority queues310, a low priority counter may be maintained on the second memory die queue305-athat tracks the commands issuing from priority queues315, a lowest priority counter may be maintained on the third memory die queue305-bthat tracks the commands issuing from priority queues320, and a fourth counter may be maintained on the fourth memory die queue305-cthat tracks the commands issuing from priority queues325. This may support, for each counter initiated on each memory die305, the firmware counter tracking how many read operations (e.g., host read commands issuing) have surpassed a write operation, for example.

Based on the counter and different priority levels, a determination may be made that a threshold number of commands from the high priority queue have issued without a command from the low priority queue having issued. For, if the counter exceeds a threshold, this may enable to the memory die queue305let the write operation go (e.g., issue a command from the low priority queue). As one example, this may include determining that the threshold number of commands have issued from priority queue310before a command from priority queues310-aand/or310-chave issued. In another examples, this may include determining that the threshold number of commands have issued from priority queue320-abefore a command from priority queue320-bhas issued.

In some examples, the threshold number provided by the counter may refer to an absolute number of commands having issued (e.g., read operations performed). In some examples, the threshold number provided by the counter may refer to a measure of time in which the commands have issued from the high priority queue without a command issuing from the low priority queue. In some examples, the threshold number provided by the counter may refer to both an absolute number of commands and/or expiry of a threshold amount of time having passed.

In some examples, the threshold number may be selected or otherwise set based on previous, current, and/or expected system performance. In some examples, the threshold number may be selected or otherwise set based on system balancing considerations, system load, system performance, etc. Accordingly, the counter associated with each memory die queue305may provide a relief mechanism by which commands from the low priority queue (e.g., any memory die queue305that is lower in priority level) are allowed to be processed in lieu of commands from the higher priority queue to prevent the commands assigned to the low priority queue from becoming stale, obsolete, etc. Moreover, this may ensure that the commands assigned to the low priority queue are allowed to be processed, at least to some extent, rather than the low priority queue becoming overly full.

Once the commands from the low priority queue are issued before the next command from the high priority queue issues, the counter may be reset, started over, cleared, etc. For example, the counter may then be reset or cleared after the command(s) from the low priority queue have been allowed to issue. The counter may then be restarted with the issuance of the next command from the high priority queue.

FIG.3Billustrates an example of a global pool of commands300-bin accordance with some embodiments of the present disclosure. The global pool of commands300-bmay include one or more commands from the priority queues discussed with reference toFIG.3A. That is, requests to complete commands may be issued (e.g., released) from the priority queues to the global pool, and a local memory controller may issue an associated command based on the order in which they are entered into the pool. Issuing the commands from the pool in an order received (i.e., according to the time the commands were received and the respective priority of each command) can reduce backpressure that the local memory controller may otherwise incur, and may allow for the sub-system to issue commands based on available resources.

In some examples, the global pool of commands300-bcan include each of the commands discussed with reference toFIG.3A. The commands can be entered into (e.g., included in) the pool of commands300-bbased on an order received (e.g., by the respective memory die queue305), a respective priority level associated with the command, or both. In some examples, the commands in the pool of commands300-bcan correspond to one or more resources (e.g., a memory address) associated with the command. That is, the commands in the pool of commands300-bcan be issued by a local memory controller to access a particular memory cell or group of memory cells.

The global pool of commands300-bcan include commands from each of the memory die queues305discussed with reference toFIG.3A. For example, commands328,330,303-a,335,335-a, and335-bfrom the first memory die queue305can be included in the global pool of commands300-b. Additionally or alternatively, commands340,340-a,340-b,345,345-a, and345-bfrom the second memory die queue305-acan be included, as well as commands350,350-a,350-b,355,355-a, and355-bfrom the second memory die queue305-b. The commands can be entered into the pool of commands300-bbased on an order received at the respective memory die queue305, based on a respective priority level associated with the command, or both.

In some examples, command350from the second priority queue320-aof the third memory die queue305-bcan be the high priority command in the pool of commands300-b. The command350can be the high priority command entered into the pool of commands300-bdue to it being received before any commands associated with a higher priority (e.g., command328). In some examples, the command350can be entered into the pool of commands300-bbefore other commands associated with a same priority level (e.g., commands330,330-a,340,340-a,340-b,350-a, and/or350-b) due to the command350being received first. Stated another way, the second priority queue320-acan receive and the command350before any other memory die queues receive and issue a command with a same (or higher) priority level.

In some examples, command340from the second priority queue315-aof the second memory die queue305-acan be the next (e.g., the second) command in the pool of commands300-b. The command340can be entered into the pool of commands based on it being received after the command350but before any commands associated with a higher priority (e.g., command328). In some examples, the command340can be entered into the pool of commands300-bbefore other commands associated with a same priority level (e.g., commands330,330-a,340,340-a,340-b,350-a, and/or350-b) due to the command340being received first.

In some examples, command350-afrom the second priority queue320-aof the third memory die queue305-bcan be the next command in the pool of commands300-b. The command350-acan be entered into the pool of commands based on it being received after the command340but before any commands associated with a higher priority (e.g., command328). In some examples, the command350-acan be entered into the pool of commands300-bbefore other commands associated with a same priority level (e.g., commands330,330-a,340-a,340-b,350-a, and/or350-b) due to the command350-abeing received first.

In some examples, command340-afrom the second priority queue315-aof the second memory die queue305-acan be the next command in the pool of commands300-b. The command340-acan be entered into the pool of commands based on it being received after the command350-abut before any commands associated with a higher priority (e.g., command328). In some examples, the command340-acan be entered into the pool of commands300-bbefore other commands associated with a same priority level (e.g., commands330,330-a,340-a,340-b, and/or350-b) due to the command350-abeing received first.

In some examples, command335from the third priority queue310-bof the first memory die queue305can be the next command in the pool of commands300-b. The command335can be entered into the pool of commands based on it being received when no other memory die queues include higher-priority commands. In some examples, the command335can be entered into the pool of commands300-bbefore other commands associated with a same priority level (e.g., commands335-a,335-b,345,345-a,345-b,355,355-a, and/or355-b) due to the command335being received first.

In some examples, command328from the first priority queue310of the first memory die queue305can be the next command in the pool of commands300-b. The command328can be entered into the pool of commands based on its priority alone. For example, because the command328is associated with a high priority (e.g., a highest priority), it can be entered into the pool of commands300-beven if other memory die queues include commands in respective priority queues. For example, the first memory die queue305can include commands330and330-ain the second priority queue310-a. However, due to the priority of the command328, the command328may be issued first (e.g., before commands330and330-a).

In some examples, commands330and330-afrom the second priority queue310-aof the first memory die queue305can be the next commands in the pool of commands300-b. The commands330and330-acan be entered into the pool of commands based on them being received after the command328but before any commands associated with a higher priority (e.g., another command in a high priority queue). In some examples, the commands330and330-acan be entered into the pool of commands300-bbefore other commands associated with a same priority level (e.g., commands340-a,340-b, and/or350-b) due to the commands330and330-abeing received first.

In some examples, command335-afrom the third priority queue310-bof the first memory die queue305can be the next command in the pool of commands300-b. The command335can be entered into the pool of commands based on it being received when no other memory die queues include higher-priority commands. In some examples, the command335-acan be entered into the pool of commands300-bbefore other commands associated with a same priority level (e.g., commands335-b,345,345-a,345-b,355,355-a, and/or355-b) due to the command335-abeing received first.

In some examples, command340-bfrom the second priority queue315-aof the second memory die queue305-acan be the next command in the pool of commands300-b. The command340-bcan be entered into the pool of commands based on it being received after the command335-abut before any commands associated with a higher priority (e.g., another command in a high priority queue). In some examples, the command340-bcan be entered into the pool of commands300-bbefore other commands associated with a same priority level (e.g., command350-b) due to the command340-bbeing received first.

In some examples, commands335-band345from the third priority queues310-band315-bcan be the next commands in the pool of commands300-b. The commands335-band345can be entered into the pool of commands based on them being received when no other memory die queues include higher-priority commands. In some examples, the commands335-band345can be entered into the pool of commands300-bbefore other commands associated with a same priority level (e.g., commands345-a,345-b,355,355-a, and/or355-b) due to the commands335-band345being received first. In some examples, command335-bcan be received before command345, hence it being entered into the pool of commands300-bfirst. In other examples, the command335-bcan be received before command345based on the first memory die queue305being associated with a higher priority level than the second memory die queue305-a, or based on a random entry of commands associated with a same priority queue.

In some examples, command350-bfrom the second priority queue320-aof the third memory die queue305-bcan be the next command in the pool of commands300-b. The command350-bcan be entered into the pool of commands based on it being received after the command345but before any commands associated with a higher priority (e.g., another command in a high priority queue). In some examples, the command350-bcan be entered into the pool of commands300-bbefore any other commands associated with a same priority level due to the command350-bbeing received first.

In some examples, each of the remaining commands (e.g., commands345-a,345-b,355,355-a, and355-b) can be entered into the pool of commands300-blast. In some examples, the commands can be entered based on an order received or based on a priority level associated with a respective memory die queue of each command. As discussed herein, each command in the pool of commands300-bcan be issued by a local memory controller according to the order in which it is entered into the pool. In some examples, the order that each command enters the pool of commands300-bmay be based on the counter discussed above with respect toFIG.3A, e.g., based on when the command issues dependent upon the counter associated with the high priority queue. Issuing commands in such an order (e.g., according to a respective priority level, based on the counter, etc.) can reduce backpressure that the local memory controller may otherwise incur, and may allow for the sub-system to issue commands based on available resources.

FIG.4illustrates an example of a memory system400for managing queues in accordance with some embodiments of the present disclosure. The memory system400can include a memory sub-system405that is coupled with a host device410. In some examples, the host device410can communicate with the memory sub-system405through a processor415. The host device410can also communicate with a read manager420(e.g., a read IO manager) and/or a write manager425(e.g., a write IO manager), which can both communicate with the memory sub-system405. That is, the host device410can be coupled with the memory sub-system405via the processor415, read manager420, and/or the write manager425. In some examples, the memory sub-system405can include one or more reception components (e.g., reception components430,430-a,430-b), a memory die manager435(e.g., a LUN manager), a priority manager440, and memory die queues445and455that correspond to one or more memory dies. In some examples, the memory sub-system can include more than two memory dies (and subsequently more than two memory die queues). Each memory die queue can include priority queues (e.g., priority queues450and460) which can be examples of the priority queues discussed with reference toFIGS.3A and3B. In some examples, the priority queues450) and460can issue commands (e.g., requests to complete associated commands) according to an associated priority. The requests can be entered into a pool of commands465, where a local memory controller can then issue an associated command. The pool of commands465can be an example of the pool of commands300-bas discussed with reference toFIG.3B.

The host device410can communicate with the memory sub-system405via the processor415. In some examples, the host device410can transmit one or more commands (e.g., a host read, a host write) to the memory sub-system405. The commands can be associated with particular memory cells (e.g., blocks of memory cells, memory dies, etc.) of the memory sub-system405and can be prioritized accordingly as discussed herein. In some examples, the read manager420can manage read operations (e.g., internal read operations) of the memory sub-system405and the write manager425can manage write operations (e.g., internal write operations) of the memory sub-system405. The read manager420and the write manager425can each communicate with the host device410and/or the processor415.

A command may be received by a reception component (e.g., reception component430,430-a, and/or430-b) of the memory sub-system405. As discussed above, commands can be received from the host device410, the read manager420, and/or the write manager425. The reception component(s) can pass (e.g., transmit) the received command(s) to the memory die manager435. In some examples, the memory die manager435can determine a particular memory die associated with the command. That is, the memory die manager435can determine a memory address associated with a received command. The memory die manager435can pass (e.g., transmit) the memory address associated with the received command to the priority manager440.

The priority manager440can determine a priority level associated with a command. As discussed herein, certain commands (e.g., a host read command) can be associated with a high priority level and other commands (e.g., host write commands, read commands, write commands, erase commands, etc.) can be associated with a different priority level that is lower in priority than the high priority level. The priority level of the command can determine the priority queue (of a memory die queue) that a command can be entered in. Thus the memory die manager435and the priority manager440can determine a memory die (e.g., an address of a memory die) associated with a command and ensure that the command is entered into a correct priority queue associated with the particular die. For example, the command can be entered into one of priority queues450or460.

The memory die queues445and455can each include one or more priority queues, with each of the one or more priority queues being associated with a counter (or timer). For example, priority queue450of memory die queue445can represent multiple priority queues as discussed with reference toFIG.3A. Similarly, priority queue460of memory die queue455can represent multiple priority queues as discussed with reference toFIG.3A. As shown inFIG.4, priority queue450can include three priority queues (e.g., a highest, lower, and lowest priority queue) that include one, two, and three commands respectively. Additionally or alternatively, priority queue460can include three priority queues (e.g., a highest, lower, and lowest priority queue) that include zero, three, and two commands respectively. The commands can be issued (e.g., released) according to the respective priority level of each command and/or the order in which the commands are entered into the respective priority queues. The commands can be issued based on the counter associated with a respective priority queue. For example, once the threshold number of commands from the high priority queue have issued without a command from a low priority queue having issued, the command(s) from the low priority queue may be issued. Once the requests (e.g., the commands) are released, they can be entered into the pool of commands465, where they can be issued by a local memory controller. Issuing the commands from the pool of commands465in an order received (i.e., according to the time the commands were received and the respective priority of each command) can reduce backpressure that the local memory controller may otherwise incur, and may allow for the sub-system to issue commands based on available resources.

FIG.5illustrates an example machine of a computer system500in which examples of the present disclosure can operate. The computer system500can include a set of instructions, for causing the machine to perform any one or more of the techniques described herein. In some examples, the computer system500can correspond to a host system (e.g., the host system105described with reference toFIG.1) that includes, is coupled with, or utilizes a memory sub-system (e.g., the memory sub-system110described with reference toFIG.1) or can be used to perform the operations of a controller (e.g., to execute an operating system to perform operations corresponding to the queue manager150) described with reference toFIG.1). In some examples, the machine can be connected (e.g., networked) with other machines in a local area network (LAN), an intranet, an extranet, and/or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term “machine” can also include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

The example computer system500can include a processing device505, a main memory510(e.g., ROM, flash memory, DRAM such as SDRAM or Rambus DRAM (RDRAM), etc.), a static memory515(e.g., flash memory, static RAM (SRAM), etc.), and a data storage system525, which communicate with each other via a bus545.

Processing device505represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device505can also be one or more special-purpose processing devices such as an ASIC, an FPGA, a DSP, network processor, or the like. The processing device505is configured to execute instructions535for performing the operations and steps discussed herein. The computer system500can further include a network interface device520to communicate over the network540.

The data storage system525can include a machine-readable storage medium530(also known as a computer-readable medium) on which is stored one or more sets of instructions535or software embodying any one or more of the methodologies or functions described herein. The instructions535can also reside, completely or at least partially, within the main memory510and/or within the processing device505during execution thereof by the computer system500, the main memory510and the processing device505also constituting machine-readable storage media. The machine-readable storage medium530, data storage system525, and/or main memory510can correspond to a memory sub-system.

In one example, the instructions535include instructions to implement functionality corresponding to a queue manager550(e.g., the queue manager150described with reference toFIG.1). While the machine-readable storage medium530is shown as a single medium, the term “machine-readable storage medium” can include a single medium or multiple media that store the one or more sets of instructions. The term “machine-readable storage medium” can also include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term “machine-readable storage medium” can include, but not be limited to, solid-state memories, optical media, and magnetic media.

Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the ways used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions, which can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some examples, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as ROM, RAM, magnetic disk storage media, optical storage media, flash memory components, etc.

In the foregoing specification, examples of the disclosure have been described with reference to specific example examples thereof. It will be evident that various modifications can be made thereto without departing from the broader spirit and scope of examples of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.