Patent ID: 12230536

DETAILED DESCRIPTION

Overview

Integrated circuits commonly include electrically conductive microelectronic structures, which are known in the arts as vias, to electrically connect metal lines or other interconnects above the vias to metal lines or other interconnects below the vias. Vias are typically formed by a lithographic process. For example, a photoresist layer may be spin coated over a dielectric layer, the photoresist layer may be exposed to patterned actinic radiation through a patterned mask, and then the exposed layer may be developed to form an opening in the photoresist layer. Next, an opening for the via may be etched in the dielectric layer by using the opening in the photoresist layer as an etch mask. This opening is referred to as a via opening. An example via opening is a contact hole. Finally, the via opening may be filled with one or more metals or other conductive materials to form the via. The via may be a plating through via, blind via (e.g., a via connecting the outermost circuit of a printed circuit board (PCB) and the adjacent inner layer), buried via (e.g., a via connecting circuit layers of a PCB but not passing to the outer layer of the PCB), or other types of vias.

In the past, the sizes and the spacing of vias has progressively decreased, and it is expected that in the future the sizes and the spacing of the vias will continue to progressively decrease, for at least some types of integrated circuits (e.g., advanced microprocessors, chipset components, graphics chips, etc.). One measure of the size of the vias is the critical dimension (e.g., a diameter or some other transverse cross-sectional dimension) of the via opening. Another measure of the spacing of the vias is the via pitch, representing the center-to-center distance between the closest adjacent vias.

When patterning extremely small vias with extremely small pitches by such lithographic processes, several challenges present themselves. One such challenge is that the overlay between the vias and the overlying interconnects, and the overlay between the vias and the underlying landing interconnects, generally need to be controlled to high tolerances on the order of a quarter of the via pitch. As via pitches scale ever smaller over time, the overlay tolerances tend to scale with them at an even greater rate than lithographic equipment.

Another such challenge is that the critical dimensions of the via openings generally tend to scale faster than the resolution capabilities of the lithographic scanners. Via opening rectification technologies exist to reduce the critical dimensions of the via openings. However, the reduced amount tends to be limited by the minimum via pitch, as well as by the ability of the via opening rectification process to be sufficiently optical proximity correction (OPC) neutral, and to not significantly compromise line width roughness (LWR) and/or critical dimension uniformity (CDU). Yet another such challenge is that the LWR and/or CDU characteristics of photoresists generally need to improve as the critical dimensions of the via openings decrease to maintain the same overall fraction of the critical dimension budget. However, currently the LWR and/or CDU characteristics of most photoresists are not improving as rapidly as the critical dimensions of the via openings are decreasing.

A further such challenge is that the extremely small via pitches generally tend to be below the resolution capabilities of even extreme ultraviolet (EUV) lithographic scanners. As a result, commonly two, three, or more different lithographic masks may be used, which tend to increase the costs. At some point, if pitches continue to decrease, it may not be possible, even with multiple masks, to print via openings for these extremely small pitches using EUV scanners. Even though EUV defined via openings offer a lot of design flexibility and helps save number of masks, EUV defined via openings show a lot of variability in LWR and/or CDU due to stochastic nature of the process. The variability increases with decreasing critical dimensions. Additionally, the via opening critical dimensions needed are beyond what EUV can do currently.

A present state of the art method to reduce the critical dimension of EUV holes is to print a relatively large hole and then taper it down to final dimension using etching. Any variability in the starting hole dimension persists post taper and, in some cases, results in missing holes.

The DSA-based approach described herein uses a diblock copolymer deposited over a guiding pattern to generate cylindrical structures for forming contact holes. A diblock copolymer is a polymeric molecule formed of a chain of covalently bonded monomers. In a diblock copolymer, there are two different types of monomers, and these different types of monomers are primarily included within different blocks or contiguous sequences of monomers, e.g., a block of polymer A, and a block of polymer B. The two different monomers making up the diblock copolymer may have different chemical properties, e.g., polymer A may be relatively more hydrophobic, and polymer B may be relatively more hydrophilic.

In many DSA applications, diblock copolymers includes polymer blocks of equal length, e.g., a 1:1 ratio of polymer A to polymer B. In such applications, the diblock copolymer applied and annealed to form a striped arrangement, e.g., alternating stripes of polymer A and polymer B. If the diblock copolymer includes polymer blocks with an unequal ratio (e.g., a 7:3 ratio of polymer A to polymer B), applying and annealing the diblock copolymer results in an array of cylinders. The cylinders have a roughly hexagonal pattern, but the pattern is not regular, and is not aligned to structures underneath the DSA layer. Polymer A and polymer B may each be converted to a different hard mask material prior to forming the vias. Some cylinders of the hard mask converted from polymer B may alternatively be etched and filled with an insulator plug.

As described herein, by applying a guiding pattern below a diblock copolymer layer with an unequal ratio between the two polymers, an array of cylinders generated through DSA are well-aligned to structures below the DSA layer. In particular, the guiding pattern is aligned to the structures below the DSA layer, and the cylinders formed in the DSA layer are aligned to the guiding layer and, thus, to the structures below the DSA layer. For example, if a guiding pattern is applied over a tight-pitched metal grating, the DSA layer formed over the guiding pattern results in an array of cylindrical structures (e.g., cylinders formed from polymer B and surrounded by polymer A), where the cylindrical structures are well-aligned with the metal portions of the metal grating. The DSA layer can then be used to form vias connecting to the structure below, e.g., by etching at least some of the cylinders formed from polymer B and filling the holes with a metal or another conductor.

The systems, methods and devices of this disclosure each have several innovative aspects, no single one of which is solely responsible for all of the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.

In the following detailed description, various aspects of the illustrative implementations may be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the term “connected” means a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term “coupled” means either a direct electrical or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. As used herein, a “logic state” (or, alternatively, a “state” or a “bit” value) of a memory cell may refer to one of a finite number of states that the cell can have, e.g., logic states “1” and “0,” each state represented by a different voltage of the capacitor of the cell, while “READ” and “WRITE” memory access or operations refer to, respectively, determining/sensing a logic state of a memory cell and programming/setting a logic state of a memory cell. If used, the terms “oxide,” “carbide,” “nitride,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc., the term “high-k dielectric” refers to a material having a higher dielectric constant (k) than silicon oxide, while the term “low-k dielectric” refers to a material having a lower k than silicon oxide. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−20% of a target value based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−5-20% of a target value based on the context of a particular value as described herein or as known in the art.

The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer “on” a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers.

For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation “A/B/C” means (A), (B), and/or (C).

The description may use the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. For convenience, if a collection of drawings designated with different letters are present, e.g.,FIGS.4A-4B, such a collection may be referred to herein without the letters, e.g., as “FIG.4.”

In the drawings, some schematic illustrations of example structures of various devices and assemblies described herein may be shown with precise right angles and straight lines, but it is to be understood that such schematic illustrations may not reflect real-life process limitations which may cause the features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region, and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication.

Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

Various IC devices with vias deposited using the DSA process described herein may be implemented in, or associated with, one or more components associated with an IC or/and may be implemented between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.

Example Unguided DSA Result

FIG.1is an example of an array of cylindrical structures formed using directed self-assembly without a guiding pattern, according to some embodiments of the present disclosure. The image shown inFIG.1is a top view of a layer of roughly cylindrical structures, e.g., cylindrical structures110aand110b, formed of a first polymer, represented in black, within a second polymer, represented in white. The cylindrical structures110are shown from their tops, and the cylinders110extend through the layer, e.g., in the z-direction (into the page) in the coordinate system illustrated inFIG.1.

As noted above, if a DSA process is performed using a diblock copolymer with an uneven ratio between the two polymers, e.g., a 7:3 ratio between the first polymer and a second polymer, the diblock copolymer may self-assemble to form cylindrical structures, such as the structures110illustrated inFIG.1. The cylindrical structures110have a roughly hexagonal arrangement, e.g., the seven structures110surrounded by the outline120are arranged in a hexagon, with one central structure surrounded by six evenly-distributed structures. However, the DSA result shown inFIG.1does not have a consistent structure across the array. For example, the area included in the outline130has eight cylindrical structures110instead of the expected seven. Furthermore, the structures in the outline130are slightly offset from the structures in the outline120, e.g., the structures in the outline130are shifted in the y-direction relative to the structures in the outline120. Moreover, the cylindrical structures110are not aligned to structures in a layer below the DSA layer illustrated inFIG.1. Because the cylindrical structures110are not well-aligned with each other or to the layer below, the DSA result illustrated inFIG.1may not be suitable for forming a contact hole pattern.

Example Process for Generating an Aligned Hexagonal Array Using a Guiding Pattern

FIG.2is a flow chart illustrating a method200for generating an aligned hexagonal array using a guiding pattern and forming vias in the hexagonal array, according to some embodiments of the present disclosure.FIGS.3A-3Killustrate various stages in the process of generating the aligned hexagonal array and forming vias in the hexagonal array according to the method ofFIG.2, according to some embodiments of the present disclosure. More specifically,FIGS.3A-3Killustrate top-down and cross-sectional side views for various stages in the process of generating the aligned hexagonal array according to the method200. In particular, each ofFIGS.3A-3Kshows, at the top of the page of the drawing, a top-down view (i.e., a view in a x-y plane) of an IC structure; in the middle of the page of the drawing, a cross-section side view of the IC structure with the cross-section taken along an x-z plane AA′ of the reference coordinate system x-y-z shown inFIGS.3A-3K; and, at the bottom of the page of the drawing, a cross-section side view of the IC structure with the cross-section taken along a y-z plane BB′ of the reference coordinate system x-y-z shown inFIGS.3A-3K.

A number of elements referred to in the description ofFIGS.3A-3Kwith reference numerals are illustrated in these figures with different patterns, with a legend showing the correspondence between the reference numerals and patterns being provided at the bottom of each drawing page containingFIGS.3A-3K. For example, the legend illustrates thatFIGS.3A-3Kuse different patterns to show a support structure302, an insulator304, and an electrically conductive material306. Furthermore, although a certain number of a given element may be illustrated in some ofFIGS.3A-3K(e.g., fourteen cylindrical structures inFIG.3D, and one example via and one example plug inFIGS.3J and3K), this is simply for ease of illustration, and more, or less, than that number may be included in an IC structure according to various embodiments of the present disclosure. Still further, various IC structure views shown inFIGS.3A-3Kare intended to show relative arrangements of various elements therein, and that various IC structures, or portions thereof, may include other elements or components that are not illustrated (e.g., transistor portions, various components that may be in electrical contact with the capacitor or contacts, etc.).

FIG.3Aillustrates an example of a grating320, e.g., a metal grating, over which an array of contacts may be formed. The grating320includes a series of conducting portions, e.g., conducting portion324, separated by insulting portions, e.g., insulating portion322. The conducting portions are formed of the electrically conductive material306, and the insulating portions are formed of the insulator304. The conducting portions and insulating portions are formed over a support structure302.

In general, implementations of the disclosure may be formed or carried out on a substrate, such as a semiconductor substrate composed of semiconductor material systems including, for example, N-type or P-type materials systems. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V, group II-VI, or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which an IC may be built falls within the spirit and scope of the present disclosure. In various embodiments, the support structure302may include any such substrate, possibly with some layers and/or devices, e.g., the grating320, already formed thereon, providing a suitable surface for forming the metal contacts as described herein.

The insulator304may include any insulating medium such as an interlayer dielectric (ILD). The insulator304may include any suitable ILD materials such as silicon oxide, carbon-doped silicon oxide, silicon carbide, silicon nitride, aluminum oxide, and/or silicon oxynitride.

The electrically conductive material306may include one or more of any suitable electrically conductive materials (conductors). Such materials may include any suitable electrically conductive material, alloy, or a stack of multiple electrically conductive materials. In some embodiments, the electrically conductive material306may include one or more metals or metal alloys, with metals such as copper, tungsten, molybdenum, ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, and aluminum. In some embodiments, the electrically conductive material306may include one or more electrically conductive alloys, oxides (e.g., conductive metal oxides), carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide, tungsten, tungsten carbide), or nitrides (e.g., hafnium nitride, zirconium nitride, titanium nitride, tantalum nitride, and aluminum nitride) of one or more metals. In some embodiments, a metal may be doped, e.g., copper may be doped with aluminum or manganese. In some embodiments, a metal structure may further include a metal liner; a suitable metal liner may include, for example, one or more of tantalum, tantalum nitride, ruthenium, cobalt, ruthenium-cobalt, titanium, or titanium nitride. In many implementations, the electrically conductive material306is formed of metal or includes a metal; thus, the grating320may be referred to as a metal grating320.

Turning toFIG.2, the method200may begin with depositing202a guiding pattern over a grating, e.g., the grating320shown inFIG.3A.FIG.3Billustrates an example result of depositing a guiding pattern330over the grating. As shown inFIG.3B, the guiding pattern330includes a first anchoring material308and a second anchoring material310.

As discussed further below, the diblock copolymer includes two different types of monomers with different chemical properties. The guiding pattern330chemically modifies the surface of the grating320to impose different affinity to different polymer blocks of the diblock copolymer. This enforces the orientation of a diblock copolymer formed over the guiding pattern330, as illustrated inFIG.3D. Each anchoring material308and310may have a greater interaction tendency (e.g., repulsive or attractive) with one polymer block than with another, e.g., the first anchoring material308attracts a first polymer block (e.g., polymer A) or repels a second polymer block (e.g., polymer B), whereas the second anchoring material310attracts the polymer block (e.g., polymer B) or repels the first polymer block (e.g., polymer A). Thus, the anchoring materials308and310tend to influence the self-assembly of the diblock copolymer.

In some embodiments, the guiding pattern330may be deposited by applying coatings of the anchoring materials308and310having a different chemical property (e.g., a hydrophilic/hydrophobic property). In some embodiments, the guiding pattern330may be applied by spin coating, spray coating, dipping coating, immersion coating, or otherwise depositing or applying a relatively thin coating of a material that has a chemical property (e.g., a hydrophilicity or hydrophobicity) that corresponds to chemical properties of the different polymer blocks. The chemical properties of the grating320may influence the placement of the anchoring materials308and310over the grating320. In particular, the first anchoring material308may adhere to the insulator304(e.g., the insulating portions in the metal grating320), while being repelled from the electrically conductive material306. The second anchoring material310may adhere to the electrically conductive material306(e.g., metal portions in a metal grating320), while being repelled from the insulator304. Additionally or alternatively, other types of surface treatments (e.g., oxidizing or de-oxidizing) may be used to modify the surface of the grating320to generate the guiding pattern330.

The first anchoring material308and the second anchoring material310are illustrated as having a striped pattern with alternating stripes of the first anchoring material308and the second anchoring material310, with the stripes' widths and positions following the widths and positions of the conducting portions324and insulating portions322of the grating320below the guiding pattern330. In other embodiments, the first anchoring material308and/or second anchoring material310may be applied in different arrangements, e.g., as shown inFIGS.4and5. In other embodiments, only one or the other of the first anchoring material308and the second anchoring material310may be applied in a striped pattern, and areas between the stripes of the anchoring material are not covered or treated, or a neutral material may be applied.

After the guiding pattern330is deposited, the method200proceeds with depositing204a solution of a diblock copolymer over the guiding pattern330.FIG.3Cillustrates an example result of depositing a layer340of a diblock copolymer312over the guiding pattern330.

The diblock copolymer312is a polymeric molecule formed of a chain of covalently bonded monomers. The diblock copolymer312may be deposited in a solution comprising the diblock copolymer combined with a liquid solvent, e.g., a glycol ether such as propylene glycol monomethyl ether acetate (PGMEA). The diblock copolymer312is formed from two different types of monomers. The different monomers are primarily included within different blocks or contiguous sequences of monomers. For example, a molecule of the diblock copolymer312includes a block of first polymer, referred to as, polymer A, and a block of a second polymer, referred to as polymer B. The block of polymer A and the block of polymer B are covalently bonded together. An individual block of polymer A includes predominantly a chain of covalently linked monomer A (e.g., A-A-A-A-A . . . ), whereas the block of polymer B includes predominantly a chain of covalently linked monomer B (e.g., B-B-B-B-B . . . ). The monomers A and B may represent any of the different types of monomers used in block copolymers known in the arts. Examples of the polymer A and polymer B include polyethylene, polystyrene, polyvinylchloride, polytetrafluorethylene, polydimethylsiloxane, some polyesters, some polyurethanes, acrylics, epoxies, P(t-Buytl Acrylate), polyacrylic acid, polyacrylamide, maleic anhydride polymers, polyethylene, polypropylene, polyacrylonitrile, polybutadiene, polyvinyl acetate, polyacetic acid, polybutyl acrylate, polylactic acid, polycaprolactone, poly(ethylene glycol), polyisoprene, poly(methyl methacrylate) (PMMA), and so on. In other embodiments, the polymer A or polymer B may be other polymers. In some embodiments, an individual block may include different types of monomers. For example, the individual block may itself be a copolymer of two or more types of monomers.

The blocks of polymer A and polymer B are of different lengths, so that one block is longer than the other. This results in a diblock copolymer solution with a greater concentration of polymer A to polymer B (or vice versa). For example, the length ratio of polymer A to polymer B may be greater than 1:1, e.g., 6:4, 7:3, 8:2, etc. The mismatched lengths of polymer A and polymer B results in a diblock copolymer solution with a greater concentration of polymer A than polymer B. For example, the diblock copolymer312may have at least a 6:4 ratio of polymer A to polymer B, or at least a 7:3 ratio of polymer A to polymer B.

As noted above, the block of polymer A and the block of polymer B have different chemical properties. As one example, one of the blocks may be relatively more hydrophobic (e.g., water disliking) and the other may be relatively more hydrophilic (water liking). As another example, one of the blocks may be relatively more similar to oil and the other block may be relatively more similar to water. Such differences in chemical properties between the different blocks of polymers, whether a hydrophilic-hydrophobic difference or otherwise, may cause the diblock copolymer312to self-assemble. For example, the self-assembly may be based on microphase separation of the polymer blocks. Conceptually, this may be similar to the phase separation of oil and water which are generally immiscible. Similarly, differences in hydrophilicity between the polymer blocks (e.g., one block is relatively hydrophobic and the other block is relatively hydrophilic), may cause a roughly analogous microphase separation where the different polymer blocks try to separate from each other due to chemical dislike for the other.

Returning toFIG.2, in some embodiments, an annealing process206may be performed after the diblock copolymer312is deposited in order to initiate, accelerate, or otherwise promote the self-assembly. In some embodiments, the annealing treatment may be a solvent annealing treatment that happens in an atmosphere of solvent vapor. The solvent vapor may be a vapor of acetone, tetrahydrofuran, or other types of organic solvent. The solvent annealing treatment can promote diffusion and self-assembly kinetics of larger polymers, such as diblock copolymers. In other embodiments, the annealing treatment may include a treatment that is operable to increase a temperature of the diblock copolymer. Such a treatment may include heating the IC device (e.g., in an oven or under a thermal lamp), applying infrared radiation to the diblock copolymer, or otherwise applying heat to or increasing the temperature of the layer340of the diblock copolymer312. The heating may help to provide energy to the molecules of the diblock copolymer312to make them more mobile and/or flexible, which can increase the rate of the microphase separation. The annealing is performed at a temperature that is high enough to increase the rate of microphase separation but low enough to avoid damaging the diblock copolymer or other components of the IC device. In some embodiments, the annealing temperature is in a range from 50° C. to 300° C.

FIG.3Dillustrates an example result of the self-assembly of the diblock copolymer312, e.g., after annealing the diblock copolymer312. In general, because the blocks of polymer A and polymer B are covalently bonded to one another in each diblock copolymer molecule, the blocks of polymer A and polymer B cannot be completely separated on a macroscopic scale. Rather, polymer blocks of a given type may tend to segregate or conglomerate with polymer blocks of the same type of other molecules. Self-assembly of the diblock copolymer312into regions of polymer A and polymer B, whether based on hydrophobic-hydrophilic differences or otherwise, is used to form extremely small periodic structures (e.g., precisely spaced nanoscale structures), such as the hexagonal pattern shown inFIG.3D.

More specifically, as shown inFIG.3D, the regions of polymer B316form cylindrical structures350, e.g., cylindrical structures350aand350b(referred to generally as “cylindrical structures350” or simply “cylinders350”). The regions of polymer B316are formed within a region or layer of polymer A314, i.e., polymer A314surrounds the cylinders350of polymer B316. In this example, the cylinders350are arranged in a hexagonal pattern, e.g., the seven cylinders350surrounded by the outline352are arranged in a hexagon, with one central cylinder350bsurrounded by six evenly-distributed cylinders350, including cylinder350a. The guiding pattern330causes the cylinders350, which are formed from polymer B316, to be precisely aligned over the second anchoring material310, which is aligned over the electrically conductive material306(e.g., metal portions in a metal grating320). Thus, the cylinders350are aligned over the metal portion of the metal grating320.

Each of the cylinders350may have a diameter between, e.g., 5 and 30 nanometers. The diameter of the cylinders350may depend at least in part on the length of the diblock copolymer312, and in particular, the length of the polymer B portion of the diblock copolymer312. The cylinders350may be arranged with a pitch between, e.g., 10 nanometers and 60 nanometers. The pitch refers to the distance between the centers of adjacent cylinders, e.g., an example pitch354between the cylinders350aand350bis illustrated inFIG.3D. The pitch of the array is based on the pitch of the grating320. Furthermore, the length of the diblock copolymer312, including the length of the polymer A portion of the diblock copolymer312, and/or the ratio of polymer A to polymer B in the diblock copolymer312may be selected to obtain a pattern of a particular pitch.

The array may exhibit a high degree of regularity, e.g., a higher degree of regularity compared to the unguided array shown inFIG.1. For example, in a hexagonal array formed over a guiding pattern such as the guiding pattern330, pitches between adjacent cylinders350may be within, e.g., ±5%, ±10%, or ±20% of a target pitch. For example, if a target pitch is 30 nanometers and the pitches are within ±10% of the target pitch, all or most (e.g., at least 90% or at least 95%) of the adjacent cylinders350may have a pitch between 27 and 33 nanometers. Furthermore, the cylinders350may have a high degree of regularity in their diameters, e.g., across a hexagonal array formed over a guiding pattern, all or most (e.g., at least 90% or at least 95%) of cylinder diameters may be within, e.g., ±5%, ±10%, or ±20% of a target diameter.

The array of cylindrical structures350can be used to form via openings over the metal portions of the metal grating320. Returning toFIG.2, the method200proceeds with converting208polymer A314and polymer B316to two different hard mask materials390and392. For example, polymer A314is selectively etched, and a first hard mask material is deposited in place of polymer A314. After polymer A314is converted to a hard mask, polymer B316may be selectively etched, and a second hard mask material is deposited in place of polymer B316. During this process, the materials in the guiding pattern330under polymer A314and polymer B316may also be etched. In some embodiments, rather than etching one or both of the polymers314and316, a polymer may be converted to a metal oxide, e.g., by sequential infiltration synthesis, vapor phase infiltration, or liquid phase infiltration.

FIG.3Eillustrates an example result of converting polymer A314to a first hard mask material390(also referred to as hard mask A390) and converting polymer B316to a second hard mask material392(also referred to as hard mask B392). The layer of the hard mask materials390and392may be referred to as a hard mask layer. The hard mask materials390and392replicate the structure of polymer A314and polymer B316, e.g., the cylindrical structures350are present in the hard mask layer, with the cylindrical structures350now comprised of the hard mask B392and surrounded by hard mask A390. The hard mask materials390and392may be different materials with strong etch selectivity, so that one or both of the hard masks themselves may be selectively etched (e.g., a cylinder350of the hard mask B392may be etched without etching hard mask A390surrounding the cylinder350). This way, the cylinders350may be selectively etched to form holes, and vias may be deposited in the holes and coupled to metal306in the grating320.

The method200may proceed with depositing210a layer of insulator and a layer of a resist material over the hard mask layer.FIG.3Gillustrates an example result of depositing an insulator layer and a resist layer over the hard mask layer. In this example, the same insulator material304included in the grating320is deposited over the hard mask layer. In other embodiments, a different insulator material may be used, e.g., any of the insulators mentioned above with respect to the insulator304. A resist394is deposited over the insulator304. The resist394may be, for example, a photoresist that is spin coated over the insulator304.

The method200proceeds with patterning212a portion of the resist over one of the cylinders350.FIG.3Hillustrates an example of patterning the resist394. For example, if the resist394is a photoresist, the photoresist may be exposed to patterned actinic radiation through a patterned mask, and then the exposed layer may be developed to form an opening in the photoresist. An example opening360is illustrated inFIG.3H. As illustrated inFIG.3H, the surface area in the x-y plane of the opening360may be somewhat larger than the surface area of the underlying cylinder350(in this example, cylinder350b), and the opening360may not be centered directly over the cylinder350. The structure of the hard mask layer and the etch selectivity between hard mask A390and hard mask B392provides a tolerance in the lithographic process performed over the hard mask layer, reducing the precision required for the lithographic process. While one opening360over one example cylinder350bis illustrated inFIG.3H, openings over any number of the cylinders350may be formed during the patterning process212.

The method200proceeds with etching214a portion of the insulator over the cylinder.FIG.3Iillustrates an example of etching a portion of the insulator304to form an opening362over the cylinder350b. The opening360in resist394acts as an etch mask for etching the opening362in the insulator304. After the opening362has been etched (and any similar openings over other cylinders350), the remaining resist394may be removed, as illustrated inFIG.3I.

The method200proceeds with etching216a cylinder under the opening formed in the insulator. The etching216may be performed using an isotropic chemically selective etch material.FIG.3Jillustrates an example of etching the cylinder350bunder the opening362to form an opening364. Here, the opening362in the insulator304acts as an etch mask for etching the opening364. In addition, the etch selectivity between hard mask A390and hard mask B392prevents a portion of hard mask A390that is exposed by the opening362from being etched. In this example, the opening364is an opening for forming a via connecting to the metal306below the opening364.

The method200proceeds with depositing218a via in the opening in the hard mask layer.FIG.3Jillustrates an example result of depositing a via370in the opening364. The via370extends through the hard mask layer and the layer of insulator304over the hard mask layer. The via370may be formed of any suitable conductive material396, e.g., any of the materials described with respect to the electrically conductive material306. The via370may include the same material or materials as the electrically conductive material306used in the metal grating320, or the via370may be formed from a different material or materials. In some embodiments, the via370may be separated from the electrically conductive material306by a barrier layer, e.g., the barrier layers described above with respect to the electrically conductive material306. The via370may be deposited using a conformal deposition method (e.g., ALD (atomic layer deposition) or CVD (chemical vapor deposition)), or a non-conformal deposition method (e.g., sputtering). The via370is coupled to a metal portion of the metal grating320.

While one example via370is illustrated inFIG.3J, multiple or many similar vias370may be formed through the processes212-218, e.g., by including additional areas over additional cylinders in the patterned mask used to pattern the resist in the lithographic patterning process212. Thus, the processes212-218may be used to form an array of vias370, with each via370at the position of one of the cylinders350. The vias370have shapes and patterns corresponding to the cylinders350described with respect toFIG.3D. In particular, each of the vias370may have a diameter between, e.g., 5 and 30 nanometers. As noted above, the diameter of the vias370may depend at least in part on the length of the diblock copolymer312, and in particular, the length of the polymer B portion of the diblock copolymer312. The vias370may be arranged with a pitch between, e.g., 10 nanometers and 60 nanometers. As noted above, the pitch of the array is based on the pitch of the grating320, and the length of the diblock copolymer312, including the length of the polymer A portion of the diblock copolymer312, and/or the ratio of polymer A to polymer B in the diblock copolymer312may be selected to obtain a via pattern of a particular pitch.

The via array may exhibit a high degree of regularity. For example, in a hexagonal array of vias formed using a guiding pattern such as the guiding pattern330, pitches between adjacent vias370may be within, e.g., ±5%, ±10%, or ±20% of a target pitch. For example, if a target pitch is 30 nanometers and the pitches are within ±10% of the target pitch, all or most (e.g., at least 90% or at least 95%) of the adjacent vias370may have a pitch between 27 and 33 nanometers. Furthermore, the vias370may have a high degree of regularity in their diameters, e.g., across a hexagonal array formed over a guiding pattern, all or most (e.g., at least 90% or at least 95%) of the via diameters may be within, e.g., ±5%, ±10%, or ±20% of a target diameter.

In some embodiments, an IC design may not require vias370to be formed within all of the cylinders350of the array, and instead, some subset of the cylinders350may be filled with insulating plugs instead of vias370. For example, if a subset of the cylinders350are not replaced with the conductive material396but left as hard mask B392, the hard mask B392may act as an insulating plug. In some embodiments, an IC design may have a plug extend below the cylinder350and into the metal grating320.

The process200may proceed with forming220a plug that extends into the metal grating320.FIG.2Killustrates an example plug380that may be formed at the location of cylinder350c. To form a plug at a particular cylinder, the hard mask B392may be removed using a method similar to processes210-216, discussed above. After the hard mask B392is etched, a portion of the metal306exposed by the hard mask layer is etched, which exposes a portion of the support structure302, or other layer below the metal grating320. This opening is filled in with an insulator material398. The insulator material398may be a different material from hard mask A392. For example, the insulator material398may include, for example, carbon-doped silicon oxides, silicon nitride, silicon carbide, undoped oxides, and any combination or mixture of silicon carbide, silicon oxide, and silicon nitride. While one insulator plug380is illustrated inFIG.3K, it should be understood that any number of the cylinders350may be removed and filled by the insulator material398instead of the vias370to form any number of insulator plugs380. In other embodiments, the process220of forming plugs380may be performed prior to the process210-218of forming the vias370.

Alternate Guiding Patterns for Generating an Aligned Array

In the guiding pattern330shown inFIG.3, the first anchoring material308and the second anchoring material310have a striped pattern with alternating stripes of the first anchoring material308and the second anchoring material310, with the stripes' widths and positions following the metal and insulating portions of the grating320below the guiding pattern330. While this guiding pattern may result in cylinders350and resulting vias370that are well-aligned over the metal portions of the metal grating (i.e., in the x-direction in the coordinate system shown inFIG.3), in some cases, the cylinders350and resulting vias370that may be less well-aligned along the metal portions of the metal grating320(i.e., in the y-direction in the coordinate system shown inFIG.3). For example, whileFIG.3Ddepicts the structures350band350cas being well-aligned in the y-direction, in some cases, these vias may be less well-aligned, e.g., the structure350cmay be offset in the y-direction relative to the structure350b.FIGS.4and5illustrate two example guiding patterns that may result in improved structure alignment and subsequent improved via alignment, particularly in a direction parallel to the metal portions of the metal grating.

FIG.4illustrates an example guiding pattern400for generating an aligned hexagonal array, according to some embodiments of the present disclosure. The guiding pattern400includes the first anchoring material308and the second anchoring material310. The first anchoring material308is arranged in stripes over the insulator304portions of the grating, similar to the arrangement of the first anchoring material308inFIG.3B. The second anchoring material310is arranged in guiding dots410, e.g., guiding dots410aand410blabelled inFIG.4. The guiding dots410are formed over portions of the electrically conductive material306, e.g., the metal portions of a metal grating. The remainder of the insulator304not covered by the guiding dots410may be covered by a neutral material402. The neutral material402may be chemically neutral, or at least relatively more neutral, to different the polymer blocks of the diblock copolymer312than the first anchoring material308and the second anchoring material310.

The guiding dots410correspond to certain ones of the cylinders350shown inFIG.3D. The guiding pattern400in combination with a diblock copolymer, e.g., the diblock copolymer312shown inFIG.3C, may result in the hexagonal array of cylinders350shown inFIG.3D. In this example, there are fewer guiding dots410than cylinders350, i.e., the guiding dots410are less dense than the hexagonal array formed from the guiding pattern400. The guiding dots410may encourage the placement of some subset of the cylinders350in the hexagonal array, and the properties of the diblock copolymer312and the overall arrangement of the guiding pattern400, including the first anchoring material308, encourages the formation of the denser hexagonal array shown inFIG.3D. In other embodiments, a guiding dot may be deposited at each expected position of a cylinder350.

The guiding dots410may be deposited using a resist process. For example, in one embodiment, the striped portion of the guiding pattern400is first formed (e.g., by depositing the first anchoring material308and the neutral material402in alternating stripes over the insulator304and the electrically conductive material306, respectively). Next, a resist is deposited over the striped pattern. The resist is patterned based on the locations for the guiding dots410, e.g., using EUV patterning. The resist is etched to expose the regions in which the guiding dots410will be placed. The second anchoring material310is deposited in the exposed regions to form the guiding dots410, and the remaining resist is removed.

In a second example embodiment, a layer of the second anchoring material310is deposited over the metal grating. A resist is deposited over the second anchoring material310and patterned, e.g., using EUV patterning, and a portion of the resist is etched. In this example, the etched portion corresponds to regions outside of the guiding dots410, so that the resist is left over the guiding dots410. The exposed portion of the second anchoring material310is removed, and the neutral material402and first anchoring material308are then deposited over the insulator304and exposed portions of the electrically conductive material306. The remaining resist over the guiding dots410is also removed, either before or after the neutral material402and the first anchoring material308are deposited.

FIG.5illustrates another example guiding pattern500for generating an aligned hexagonal array, according to some embodiments of the present disclosure. In this example, diagonal stripes, e.g., stripes510aand510b, are formed from the first anchoring material308. The diagonal stripes510may be deposited using an EUV resist process, e.g., either of the resist processes described with respect to the guiding dots410ofFIG.4. In areas where the guiding stripes510are not formed, the first anchoring material308and second anchoring material310are deposited in stripes aligned vertically in the y-direction in the orientation shown inFIG.5; as described with respect toFIG.3, the vertical stripes of the first and second anchoring materials308and310may mimic an underlying metal grating320.

The diagonal stripes510encourage placement of the cylinders of polymer B so that they are properly aligned in the y-direction. Outlines showing the expected locations of cylinders550of polymer B are illustrated inFIG.5. The cylinders550, which form over the second anchoring material310, do not form over the diagonal stripes510. For example, the cylinders550aand550blabelled inFIG.5are formed between the two diagonal lines510aand510b.

While the example arrays illustrated herein have a hexagonal pattern, in other embodiments, in other embodiments, a guiding pattern may encourage cylinders to form in a different pattern. For example, alternate guiding patterns may produce an array of cylinders in a square pattern (with cylinders placed at the corners of squares, where the corners are aligned over an underlying metal layer), or an array of cylinders in a rectangular pattern (with cylinders placed at the corners of the rectangles, where the corners are aligned over an underlying metal layer).

Generating an Aligned Hexagonal Array Over a Grating-Replicating Layer

In the example process described with respect toFIGS.2and3, the array is formed over a guiding pattern330, which is formed directly over the metal grating320. In an alternate embodiment, a first DSA process may be performed to generate a first layer that replicates the pattern of a metal grating, and a second DSA process may be performed over the first layer to generate a second layer with an array, e.g., a hexagonal array.

FIG.6A-6Fillustrate various stages in a process of generating an aligned hexagonal array over a grating-replicating layer, according to some embodiments of the present disclosure.FIG.6Aillustrates a grating replicating layer630formed using a DSA process over a metal grating620. The metal grating620is similar to the metal grating320described with respect toFIG.1. A guiding pattern625is formed over the metal grating620. The guiding pattern625includes the first anchoring material308formed over the portions of insulator304in the metal grating620. The guiding pattern625may also include the second anchoring material310formed over the portions of the electrically conductive material306in the metal grating620, similar to the guiding pattern330shown inFIG.3B.

A first solution of self-assembling diblock copolymer is deposited over the guiding pattern625and optionally annealed to form a striped pattern that replicates the metal grating620. Unlike the diblock copolymer312described with respect toFIG.3, the first diblock copolymer for generating the grating replicating layer630may have an equal ratio of a first polymer, e.g., polymer A, to a second copolymer, e.g., polymer B. In some embodiments, the first polymer and the second polymer may not have an equal ratio (e.g., if the width of the metal portions and insulator portions of the metal grating620are unequal), but the ratio of the polymers used to generate the grating replicating layer630is closer to an equal ratio than a diblock copolymer used to form a hexagonal pattern. While the same polymer A314is illustrated in the grating replicating layer, in other embodiments, a different first polymer and/or a different second polymer (e.g., selected from the list of polymers given above) may be used to form the grating replicating layer630.

In the example shown inFIG.6A, after the diblock copolymer self-assembles to form a striped pattern replicating the metal grating320, polymer B is selectively etched and replaced by depositing a hard mask602. The hard mask602may be an insulator that forms a suitable insulating layer in an IC device. In this example, polymer A314remains, but in other embodiments, polymer A314may be selectively etched and replaced with a second hard mask material, and in particular, a different hard mask material from the hard mask602.

As depicted inFIG.6B, a second guiding pattern640is deposited over the grating replicating layer630. In this example, the second guiding pattern640includes stripes of the second anchoring material310formed over the portions of hard mask602in the grating replicating layer630. The stripes of polymer A314in the grating replicating layer630may act as an anchoring material for a DSA layer formed over the grating replicating layer630and the second guiding pattern640. Alternatively, if the polymer A314in the grating replicating layer630was etched and replaced by a second hard mask material, stripes of the first anchoring material308may be formed over the second hard mask material in the second guiding pattern640. While the second guiding pattern640is shown as having a striped arrangement, in other embodiments, additional guiding features, such as the guiding dots or diagonal lines illustrated inFIGS.4and5, may be included in the second guiding pattern640.

After the second guiding pattern640is deposited, a solution of a diblock copolymer is deposited over the second guiding pattern640. The diblock copolymer may be similar to the diblock copolymer312described with respect toFIG.3. The diblock copolymer self-assembles, e.g., in response to an annealing treatment, to form the array650illustrated inFIG.6C. The array650includes an array of cylinders in a hexagonal pattern, similar to the hexagonal array of cylinders350illustrated inFIG.3D. The cylinders are aligned with the hard mask602in the grating replicating layer630, which is aligned with the electrically conductive material306in the metal grating620. Thus, the cylinders are aligned over the electrically conductive material306, with the grating replicating layer630between the array650and the metal grating620.

In the example shown inFIG.6C, the array650includes cylinders formed from polymer B316within a layer of polymer A314. Both the grating replicating layer630and the array layer include polymer A314. In other embodiments, a different first polymer forming the bulk of the array layer and/or a different second polymer forming the cylinders (e.g., selected from the list of polymers given above) may be used to form the array650.

After the array650is formed, the process proceeds with etching polymer B316, i.e., removing the polymer forming the cylinders of the array650, and etching portions of the hard mask602under the etched regions of the array650.FIG.6Dillustrates an example result of etching the polymer B regions and the hard mask602. A multi-step etching process may be used, e.g., a first etching process to selectively etch polymer B316, followed by a second etching process to selectively etch the exposed portions of the hard mask602. In some embodiments, an additional etching process may be performed to selectively etch the exposed portions of the second anchoring material310. Most or all of the polymer A314and the unexposed regions of the hard mask602may remain after the multi-step etching process. The etching process forms etched regions660, also referred to as openings660, e.g., the openings660aand660blabelled inFIG.6D. The openings660have the same pattern as the cylinders in the array650. For example, the openings660may have the locations, pitch, and diameters described with respect to the cylinders350ofFIG.3.

After forming the openings660, the process may proceed with depositing a hard mask material into the openings660. For example, as illustrated inFIG.6E, the second hard mask material392, described with respect toFIG.3, may be deposited into the openings660, forming cylindrical structures670of the second hard mask material392. For example, the opening660ais filled with a cylindrical hard mask structure670a, and the opening660bis filled with a cylindrical hard mask structure670b.

The process may proceed with converting polymer A314to a different hard mask material. For example, polymer A314may be etched and replaced with a hard mask, or polymer A314may be converted to a metal oxide, e.g., by sequential infiltration synthesis, vapor phase infiltration, or liquid phase infiltration.FIG.6Fillustrates an example result of replacing polymer A314with a hard mask, e.g., the first hard mask material390described with respect toFIG.3. In this example, a layer of the hard mask602remains below hard mask A390, i.e., hard mask390replaces polymer A314, but not the hard mask602that was below polymer A314. In other embodiments, the hard mask602may also be etched and replaced with hard mask A390. WhileFIGS.6E and6Fillustrate that polymer B316is converted to hard mask B392and then polymer A314is converted to hard mask B390, in other embodiments, these processes may be performed in the opposite order.

After converting polymer A314and polymer B316to the hard mask materials390and392, at least some of the cylindrical structures670formed of hard mask B392may be etched and replaced with via material, e.g., the conductive material396, to form vias. Vias may be formed using a method similar to processes210-218, described above with respect toFIG.2andFIGS.3E-3J. In some embodiments, others of the cylindrical structures670formed of hard mask B392may be etched and replaced with an insulator material, e.g., the insulator material398, to form plugs. Plugs may be formed using a method similar to process220, described above with respect toFIG.2andFIG.3K.

Additional Features of Aligned Arrays Formed Using a Guiding Pattern

The processes described above for generating arrays over guiding patterns using DSA can result in highly regular and well-aligned patterns and via placement. However, IC devices may exhibit certain physical characteristics in the area where the guided pattern was performed which may indicate that the guided DSA process described herein was used. Furthermore, IC devices may exhibit differences between a first region in which guided DSA was performed and a second region in which guided DSA was not performed, which can indicate the use of the guided DSA process in the first region.

FIG.7illustrates a contrast between an aligned hexagonal region and a non-aligned hexagonal region, according to some embodiments of the present disclosure. In this example, the guiding pattern, e.g., any of the guiding patterns330,400,500, or640, may be formed over a first region700of a layer of an IC device, where the first region700is surrounded by a dashed box illustrated inFIG.7. The guiding pattern is not formed over a second region710of the layer of the IC device, where the second region710is the region not surrounded by the dashed box. The first region700may correspond to an active area of an IC device, and the second region710may correspond to an inactive area of the IC device, such as a frame, guard etch, or guard ring.

In the first region700, structures illustrated in white (e.g., a hexagonal array of vias) are formed within another material (e.g., an insulating material, illustrated in gray). In this example, the structures are arranged in a highly regular hexagonal array. The array of structures may be well-aligned to each other and well-aligned to a grating below the array of structures. For example, pitches between adjacent structures in the first region700all or mostly (e.g., 80%, 90%, or 95% of the pairs) may be within a certain error range of a target pitch, e.g., ±5% of the target pitch, ±10% of the target pitch, or ±20% of the target pitch. By contrast, in the second region710, the structures have a roughly hexagonal pattern, but without the high level of regularity and alignment exhibited in the first region700. As another example, the structures in the second region710may have a similar arrangement to the arrangement shown inFIG.1. For example, pitches between at least a threshold number of pairs of adjacent structures in the second region710(e.g., greater than 10% of the pairs, or greater than 20% of the pairs) may be outside the error range of a target pitch, e.g., outside±10% of the target pitch.

This contrast between the first region700and the second region710may indicate that the guiding pattern was applied and the DSA process performed over the first region700, but that the guiding pattern was not applied in the second region710. For example, the second region710, which may be an inactive portion of the IC device, may not have the same underlying grating structure of the first region700to encourage the formation of the guiding pattern, as described with respect toFIGS.2and3.

FIG.8illustrates an example line defect that may be exhibited by the guided array process, according to some embodiments of the present disclosure. In this example, cylindrical structures810(e.g., via structures) are formed using the guided array process described with respect to any ofFIGS.2-6. The cylindrical structures810are formed of one material illustrated in white (e.g., a via metal) and are formed within a layer of another material illustrated in gray (e.g., an insulator).

In some cases, a guided array process may result in an array of cylindrical structures in a highly regular pattern, as discussed with respect toFIGS.2-7, but line defects connecting pairs of adjacent structures may be formed. One example line defect820ais formed between the adjacent structures810aand810b. Two additional line defects820band820cconnect through the structure810c. A line defect may occur if a linear region of polymer B316forms between two cylinders of polymer B316, e.g., two of the cylinders350. This linear region of polymer B is etched and filled with a via material, resulting in the line defect structures820illustrated inFIG.8in an IC structure. Thus, the line defect structures820may be formed of the same material is the cylindrical structures810.

As illustrated inFIG.8, the line defect structures820may have a width that is less than the diameter of the cylindrical structures810. In other embodiments, the line defect structures820may have a width equal to or greater than the diameter of the cylindrical structures810.

The line defect structures820may be observed in an active region in which the guided DSA process was performed (e.g., the first region700illustrated inFIG.7) and/or an inactive region in which the guiding pattern was not used (e.g., the second region710illustrated inFIG.7).

FIG.9illustrates an example array defect that may be exhibited by the guided array process, according to some embodiments of the present disclosure. In this example, cylindrical structures (e.g., via structures) are formed using the guided hexagonal array process described with respect to any ofFIGS.2-6. The cylindrical structures are formed of one material illustrated in white (e.g., a via metal) and are formed within a layer of another material illustrated in gray (e.g., an insulator).

In some cases, a guided array process may result in cylindrical structures having a highly regular pattern, as discussed with respect toFIGS.2-7, but some subset of the expected cylindrical structures may not successfully form. For example, the polymer B may not completely span the DSA layer in the z-direction, e.g., if a line defect forms during the self-assembly. This can result in an array defect in which certain structures expected based on the hexagonal pattern are missing. The positions of the example array defects inFIG.9are illustrated by dashed circles, e.g., two adjacent array defects910aand910bare labelled inFIG.9.

Example Electronic Devices

Layers of cylindrical via structures in an array formed using the guided array process described herein may be included in any suitable electronic device.FIGS.10-14illustrate various examples of devices and components that may include cylindrical structures, e.g., vias, deposited in an array, such as the hexagonal array as described herein.

FIGS.10A and10Bare top views of a wafer and dies that include one or more IC structures with devices including vias deposited in a guided array in accordance with any of the embodiments disclosed herein. The wafer1500may be composed of semiconductor material and may include one or more dies1502having IC structures formed on a surface of the wafer1500. Each of the dies1502may be a repeating unit of a semiconductor product that includes any suitable IC structure (e.g., the IC structures as shown in any ofFIG.1,2, or4-6, or any further embodiments of the IC structures described herein). After the fabrication of the semiconductor product is complete (e.g., after manufacture of one or more IC structures with one or more devices including vias deposited in a guided array as described herein, included in a particular electronic component, e.g., in a transistor or in a memory device), the wafer1500may undergo a singulation process in which each of the dies1502is separated from one another to provide discrete “chips” of the semiconductor product. In particular, devices that include one or more devices that include vias deposited in a guided array as disclosed herein may take the form of the wafer1500(e.g., not singulated) or the form of the die1502(e.g., singulated). The die1502may include one or more transistors (e.g., one or more of the transistors1640ofFIG.11, discussed below) and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components (e.g., one or more devices that include vias deposited in a guided array). In some embodiments, the wafer1500or the die1502may include a memory device (e.g., an SRAM device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die1502. For example, a memory array formed by multiple memory devices may be formed on a same die1502as a processing device (e.g., the processing device1802ofFIG.13) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

FIG.11is a cross-sectional side view of an IC device1600that may include one or more devices including vias deposited in a guided array in accordance with any of the embodiments disclosed herein. The IC device1600may be formed on a substrate1602(e.g., the wafer1500ofFIG.10A) and may be included in a die (e.g., the die1502ofFIG.10B). The substrate1602may be any substrate as described herein. The substrate1602may be part of a singulated die (e.g., the dies1502ofFIG.10B) or a wafer (e.g., the wafer1500ofFIG.10A).

The IC device1600may include one or more device layers1604disposed on the substrate1602. The device layer1604may include features of one or more transistors1640(e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate1602. The device layer1604may include, for example, one or more source and/or drain (S/D) regions1620, a gate1622to control current flow in the transistors1640between the S/D regions1620, and one or more S/D contacts1624to route electrical signals to/from the S/D regions1620. The transistors1640may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors1640are not limited to the type and configuration depicted inFIG.11and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors.

Each transistor1640may include a gate1622formed of at least two layers, a gate electrode layer and a gate dielectric layer.

The gate electrode layer may be formed on the gate interconnect support layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor, respectively. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer or/and an adhesion layer.

For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 electron Volts (eV) and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, tungsten, tungsten carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

In some embodiments, when viewed as a cross section of the transistor1640along the source-channel-drain direction, the gate electrode may be formed as a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may be implemented as a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may be implemented as one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers. In some embodiments, the gate electrode may consist of a V-shaped structure (e.g., when a fin of a FinFET transistor does not have a “flat” upper surface, but instead has a rounded peak).

Generally, the gate dielectric layer of a transistor1640may include one layer or a stack of layers, and the one or more layers may include silicon oxide, silicon dioxide, and/or a high-k dielectric material. The high-k dielectric material included in the gate dielectric layer of the transistor1640may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

The S/D regions1620may be formed within the substrate1602adjacent to the gate1622of each transistor1640, using any suitable processes known in the art. For example, the S/D regions1620may be formed using either an implantation/diffusion process or a deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate1602to form the S/D regions1620. An annealing process that activates the dopants and causes them to diffuse farther into the substrate1602may follow the ion implantation process. In the latter process, an epitaxial deposition process may provide material that is used to fabricate the S/D regions1620. In some implementations, the S/D regions1620may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions1620may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions1620. In some embodiments, an etch process may be performed before the epitaxial deposition to create recesses in the substrate1602in which the material for the S/D regions1620is deposited.

Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the transistors1640of the device layer1604through one or more interconnect layers disposed on the device layer1604(illustrated inFIG.11as interconnect layers1606-1610). For example, electrically conductive features of the device layer1604(e.g., the gate1622and the S/D contacts1624) may be electrically coupled with the interconnect structures1628of the interconnect layers1606-1610. The one or more interconnect layers1606-1610may form an ILD stack1619of the IC device1600.

The interconnect structures1628may be arranged within the interconnect layers1606-1610to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures1628depicted inFIG.11). Although a particular number of interconnect layers1606-1610is depicted inFIG.11, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

In some embodiments, the interconnect structures1628may include trench contact structures1628a(sometimes referred to as “lines”) and/or via structures1628b(sometimes referred to as “holes”) filled with an electrically conductive material such as a metal. The trench contact structures1628amay be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate1602upon which the device layer1604is formed. For example, the trench contact structures1628amay route electrical signals in a direction in and out of the page from the perspective ofFIG.11. The via structures1628bmay be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate1602upon which the device layer1604is formed. In some embodiments, the via structures1628bmay electrically couple trench contact structures1628aof different interconnect layers1606-1610together.

The interconnect layers1606-1610may include a dielectric material1626disposed between the interconnect structures1628, as shown inFIG.11. The dielectric material1626may take the form of any of the embodiments of the dielectric material provided between the interconnects of the IC structures disclosed herein.

In some embodiments, the dielectric material1626disposed between the interconnect structures1628in different ones of the interconnect layers1606-1610may have different compositions. In other embodiments, the composition of the dielectric material1626between different interconnect layers1606-1610may be the same.

A first interconnect layer1606(referred to as Metal 1 or “M1”) may be formed directly on the device layer1604. In some embodiments, the first interconnect layer1606may include trench contact structures1628aand/or via structures1628b, as shown. The trench contact structures1628aof the first interconnect layer1606may be coupled with contacts (e.g., the S/D contacts1624) of the device layer1604.

A second interconnect layer1608(referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer1606. In some embodiments, the second interconnect layer1608may include via structures1628bto couple the trench contact structures1628aof the second interconnect layer1608with the trench contact structures1628aof the first interconnect layer1606. Although the trench contact structures1628aand the via structures1628bare structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer1608) for the sake of clarity, the trench contact structures1628aand the via structures1628bmay be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.

A third interconnect layer1610(referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer1608according to similar techniques and configurations described in connection with the second interconnect layer1608or the first interconnect layer1606.

The IC device1600may include a solder resist material1634(e.g., polyimide or similar material) and one or more bond pads1636formed on the interconnect layers1606-1610. The bond pads1636may be electrically coupled with the interconnect structures1628and configured to route the electrical signals of the transistor(s)1640to other external devices. For example, solder bonds may be formed on the one or more bond pads1636to mechanically and/or electrically couple a chip including the IC device1600with another component (e.g., a circuit board). The IC device1600may have other alternative configurations to route the electrical signals from the interconnect layers1606-1610than depicted in other embodiments. For example, the bond pads1636may be replaced by or may further include other analogous features (e.g., posts) that route the electrical signals to external components.

FIG.12is a cross-sectional side view of an IC device assembly1700that may include components having or being associated with (e.g., being electrically connected by means of) one or more devices including vias deposited in a guided array accordance with any of the embodiments disclosed herein. The IC device assembly1700includes a number of components disposed on a circuit board1702(which may be, e.g., a motherboard). The IC device assembly1700includes components disposed on a first face1740of the circuit board1702and an opposing second face1742of the circuit board1702; generally, components may be disposed on one or both faces1740and1742. In particular, any suitable ones of the components of the IC device assembly1700may include any of the vias deposited in a guided array as disclosed herein.

In some embodiments, the circuit board1702may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board1702. In other embodiments, the circuit board1702may be a non-PCB substrate.

The IC device assembly1700illustrated inFIG.12includes a package-on-interposer structure1736coupled to the first face1740of the circuit board1702by coupling components1716. The coupling components1716may electrically and mechanically couple the package-on-interposer structure1736to the circuit board1702and may include solder balls (as shown inFIG.12), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure1736may include an IC package1720coupled to an interposer1704by coupling components1718. The coupling components1718may take any suitable form for the application, such as the forms discussed above with reference to the coupling components1716. Although a single IC package1720is shown inFIG.12, multiple IC packages may be coupled to the interposer1704; indeed, additional interposers may be coupled to the interposer1704. The interposer1704may provide an intervening substrate used to bridge the circuit board1702and the IC package1720. The IC package1720may be or include, for example, a die (the die1502ofFIG.10B), an IC device (e.g., the IC device1600ofFIG.11), or any other suitable component. In some embodiments, the IC package1720may include vias deposited in a guided hexagonal array, as described herein. Generally, the interposer1704may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer1704may couple the IC package1720(e.g., a die) to a ball grid array (BGA) of the coupling components1716for coupling to the circuit board1702. In the embodiment illustrated inFIG.12, the IC package1720and the circuit board1702are attached to opposing sides of the interposer1704; in other embodiments, the IC package1720and the circuit board1702may be attached to a same side of the interposer1704. In some embodiments, three or more components may be interconnected by way of the interposer1704.

The interposer1704may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer1704may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer1704may include metal interconnects1708and vias1710, including but not limited to TSVs1706. The interposer1704may further include embedded devices1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer1704. The package-on-interposer structure1736may take the form of any of the package-on-interposer structures known in the art.

The IC device assembly1700may include an IC package1724coupled to the first face1740of the circuit board1702by coupling components1722. The coupling components1722may take the form of any of the embodiments discussed above with reference to the coupling components1716, and the IC package1724may take the form of any of the embodiments discussed above with reference to the IC package1720.

The IC device assembly1700illustrated inFIG.12includes a package-on-package structure1734coupled to the second face1742of the circuit board1702by coupling components1728. The package-on-package structure1734may include an IC package1726and an IC package1732coupled together by coupling components1730such that the IC package1726is disposed between the circuit board1702and the IC package1732. The coupling components1728and1730may take the form of any of the embodiments of the coupling components1716discussed above, and the IC packages1726and1732may take the form of any of the embodiments of the IC package1720discussed above. The package-on-package structure1734may be configured in accordance with any of the package-on-package structures known in the art.

FIG.13is a block diagram of an example computing device1800that may include one or more components including one or more devices including vias deposited in a guided array in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the computing device1800may include a die (e.g., the die1502ofFIG.10B) having vias deposited in a guided array as described herein. Any one or more of the components of the computing device1800may include, or be included in, an IC device1600(FIG.11). Any one or more of the components of the computing device1800may include, or be included in, an IC device assembly1700(FIG.12).

A number of components are illustrated inFIG.13as included in the computing device1800, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the computing device1800may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

Additionally, in various embodiments, the computing device1800may not include one or more of the components illustrated inFIG.13, but the computing device1800may include interface circuitry for coupling to the one or more components. For example, the computing device1800may not include a display device1806, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device1806may be coupled. In another set of examples, the computing device1800may not include an audio input device1824or an audio output device1808but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device1824or audio output device1808may be coupled.

The computing device1800may include a processing device1802(e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device1802may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device1800may include a memory1804, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random-access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory1804may include memory that shares a die with the processing device1802. This memory may be used as cache memory and may include embedded dynamic random-access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-MRAM).

In some embodiments, the computing device1800may include a communication chip1812(e.g., one or more communication chips). For example, the communication chip1812may be configured for managing wireless communications for the transfer of data to and from the computing device1800. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

The communication chip1812may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip1812may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip1812may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip1812may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip1812may operate in accordance with other wireless protocols in other embodiments. The computing device1800may include an antenna1822to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

In some embodiments, the communication chip1812may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip1812may include multiple communication chips. For instance, a first communication chip1812may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip1812may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip1812may be dedicated to wireless communications, and a second communication chip1812may be dedicated to wired communications.

The computing device1800may include battery/power circuitry1814. The battery/power circuitry1814may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device1800to an energy source separate from the computing device1800(e.g., AC line power).

The computing device1800may include a display device1806(or corresponding interface circuitry, as discussed above). The display device1806may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

The computing device1800may include an audio output device1808(or corresponding interface circuitry, as discussed above). The audio output device1808may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

The computing device1800may include an audio input device1824(or corresponding interface circuitry, as discussed above). The audio input device1824may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

The computing device1800may include a GPS device1818(or corresponding interface circuitry, as discussed above). The GPS device1818may be in communication with a satellite-based system and may receive a location of the computing device1800, as known in the art.

The computing device1800may include an other output device1810(or corresponding interface circuitry, as discussed above). Examples of the other output device1810may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

The computing device1800may include an other input device1820(or corresponding interface circuitry, as discussed above). Examples of the other input device1820may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

The computing device1800may have any desired form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device1800may be any other electronic device that processes data.

Select Examples

The following paragraphs provide various examples of the embodiments disclosed herein.

Example 1 provides a method for hole patterning, the method including depositing a guiding pattern; depositing a solution of a diblock copolymer over the guiding pattern, the diblock copolymer including first polymer and a second polymer, the diblock copolymer having a greater concentration of the first polymer than the second polymer; annealing the diblock copolymer to generate a pattern in the first polymer and the second polymer, the pattern including a plurality of regions of the second polymer, the regions arranged in a regular pattern.

Example 2 provides the method of example 1, where the regions are arranged in a hexagonal pattern.

Example 3 provides the method of example 1 or 2, further including converting the plurality of regions of the second polymer to a hard mask; etching a region of the hard mask to form an etched region; and depositing metal into the etched region.

Example 4 provides the method of example 3, where the guiding pattern is deposited over a metal grating, the metal grating including a plurality of metal portions separated by a plurality of insulating portions.

Example 5 provides the method of example 4, where the etched region is over one of the metal portions of the metal grating, the metal deposited into the etched region forming a via.

Example 6 provides the method of examples 4 or 5, where the guiding pattern includes a first anchoring material and a second anchoring material, the first anchoring material adheres to the metal portions in the metal grating, and the second anchoring material adheres to the insulating portions in the metal grating.

Example 7 provides the method of any of the preceding examples, where annealing the deposited solution of the diblock copolymer generates the pattern using directed self-assembly (DSA) of the diblock copolymer.

Example 8 provides the method of any of the preceding examples, where the diblock copolymer has at least a 6:4 ratio of the first polymer to the second polymer.

Example 9 provides the method of any of the preceding examples, where the diblock copolymer has at least a 7:3 ratio of the first polymer to the second polymer.

Example 10 provides the method of any of the preceding examples, where the guiding pattern includes a first anchoring material that attracts the first polymer and a second anchoring material that attracts the second polymer.

Example 11 provides the method of example 10, where the first anchoring material and the second anchoring material are arranged in alternating stripes.

Example 12 provides the method of example 11, where the guiding pattern further includes a plurality of diagonal lines extending across the alternating stripes, the diagonal lines formed from the first anchoring material.

Example 13 provides the method of example 10, where the guiding pattern includes a plurality of guiding dots, the guiding dots corresponding to a subset of the plurality of regions forming the hexagonal pattern, the guiding dots formed from the second anchoring material.

Example 14 provides an IC device including a layer including a first material, the layer including an active area and an inactive area; and a plurality of structures formed in the active area of the layer and the inactive area of the layer, the structures including a second material different from the first material; where, in at least a portion of the active area, the plurality of structures are arranged in a regular pattern.

Example 15 provides the IC device of example 14, where, in at least a portion of the inactive area, the plurality of structures are arranged in an irregular pattern.

Example 16 provides the IC device of example 14 or 15, where, in the portion of the active area, the plurality of structures are arranged in a hexagonal pattern.

Example 17 provides the IC device of any of examples 14 to 16, where one of the plurality of structures in the active area has a diameter between 5 and 30 nanometers.

Example 18 provides the IC device of any of examples 14 to 17, where an adjacent pair of structures in the active area have a pitch between 10 and 60 nanometers.

Example 19 provides the IC device of any of examples 14 to 18, where, in the active area, pitches between adjacent structures of the plurality of structures arranged in the hexagonal pattern are within ±10% of a target pitch.

Example 20 provides the IC device of example 19, where, in the inactive area, pitches between at least a portion of adjacent structures vary by greater than ±10% of the target pitch.

Example 21 provides the IC device of any of examples 14 through 20, where the plurality of structures form vias extending through the layer to a second layer, the second layer under the layer.

Example 22 provides the IC device of any of examples 14 through 21, where the plurality of structures are a first set of structures, the IC device further including a second set of structures arranged in the regular pattern, the second set of structures formed from a third material different from the first material and the second material.

Example 23 provides the IC device of any of examples 14 through 22, where a pair of adjacent structures in the inactive area are connected by a line.

Example 24 provides an IC device including a layer including a first material; a plurality of structures formed in the layer, one of the plurality of structures including a second material different from the first material, and the plurality of structures arranged in a regular pattern, where an adjacent pair of the structures includes a first structure and a second structure; and a line connects the first structure and the second structure, the line formed from the second material.

Example 25 provides the IC device of example 24, where at least a portion of the plurality of structures are arranged in a hexagonal pattern.

Example 26 provides the IC device of example 24 or 25, where first structure has a first diameter, and the line has a width no greater than the first diameter.

Example 27 provides the IC device of any of examples 24 to 26, where the first structure and the second structure each have a diameter between 5 and 30 nanometers.

Example 28 provides the IC device of any of examples 24 through 27, where the first structure and the second structure have a pitch between 10 and 60 nanometers.

Example 29 provides the IC device of any of examples 24 to 28, where pitches between adjacent structures in the hexagonal pattern are within ±10% of a target pitch.

Example 30 provides the IC device of any of examples 24 through 29, where the plurality of structures form vias extending through the layer to a second layer, the second layer under the layer.

Example 31 provides the IC device of any of examples 24 through 30, where the plurality of structures arranged in the hexagonal pattern are in an active area of the layer, the layer further including an inactive area having a second plurality of structures, the second plurality of structures arranged in an irregular pattern.

Example 32 provides an IC device including a layer comprising a first insulator material; and a plurality of structures formed in the layer, the structures arranged in a hexagonal pattern, the plurality of structures including a first set of structures comprising a second insulator material different from the first insulator material, and a second set of structures comprising a conductive material.

Example 33 provides the IC device of example 32, where the layer is a first layer, the first layer is over a second layer including alternating conductive and non-conductive portions, and one of the second set of structures extends through the layer to a conductive portion of the second layer.

Example 34 provides the IC device of example 33, where one of the first set of structures extends into a conductive portion of the second layer.

Example 35 provides the IC device of any of examples 32 through 34, where the second insulator material includes silicon.

Example 36 provides the IC device of example 35, where the second insulator material further includes at least one of carbon, oxygen, or nitrogen.

Example 37 provides the IC device of any of examples 32 through 36, further including comprising an ILD layer over the layer, where the plurality of structures extend through the ILD layer.

Example 38 provides an IC package that includes an IC die, including one or more of the memory/IC devices according to any one of the preceding examples. The IC package may also include a further component, coupled to the IC die.

Example 39 provides the IC package according to example 38, where the further component is one of a package substrate, a flexible substrate, or an interposer.

Example 40 provides the IC package according to examples 38 or 39, where the further component is coupled to the IC die via one or more first level interconnects.

Example 41 provides the IC package according to example 40, where the one or more first level interconnects include one or more solder bumps, solder posts, or bond wires.

Example 42 provides a computing device that includes a circuit board; and an IC die coupled to the circuit board, where the IC die includes one or more of the memory/IC devices according to any one of the preceding examples (e.g., memory/IC devices according to any one of examples 14-36), and/or the IC die is included in the IC package according to any one of the preceding examples (e.g., the IC package according to any one of examples 38-41).

Example 43 provides the computing device according to example 42, where the computing device is a wearable computing device (e.g., a smart watch) or handheld computing device (e.g., a mobile phone).

Example 44 provides the computing device according to examples 42 or 43, where the computing device is a server processor.

Example 45 provides the computing device according to examples 42 or 43, where the computing device is a motherboard.

Example 46 provides the computing device according to any one of examples 41-45, where the computing device further includes one or more communication chips and an antenna.

The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications may be made to the disclosure in light of the above detailed description.