Patent ID: 12207395

DETAILED DESCRIPTION

The inventors have recognized and appreciated that, although substantial focus has been placed on providing improved electrical connectors in order to improve the performance of interconnection systems, at some very high frequencies significant performance improvement may be achieved by inventive designs for printed circuit boards. In accordance with some embodiments, improvements may be achieved by the incorporation of structures to alter the electrical properties of the printed circuit board in a connector footprint. The structures shown and described herein may be utilized in any type of printed circuit board, including but not limited to backplanes, mother boards, daughter boards, orthogonally mating daughter cards that mate with or without a midplane and daughter cards that mate to a cable.

Those structures, for example, may include conducting structures, known as vias, extending vertically through a printed circuit board. In some embodiments, the structures may be shadow vias which are plated or filled with conductive material through some or all of the layers of the printed circuit board. The shadow vias are not required to accept contact tails of the connector and are configured and positioned relative to signal vias to improve performance, particularly at high frequencies. In some embodiments, the shadow vias reduce crosstalk between signal vias in adjacent columns of signal vias in a connector footprint. In some embodiments, the shadow vias are located between signal vias of a differential signal pair.

Referring toFIG.1, an electrical interconnection system100with two connectors is shown. The electrical interconnection system100includes a daughter card connector120and a backplane connector150.

Daughter card connector120is designed to mate with backplane connector150, creating electronically conducting paths between a backplane160and a daughter card140. Though not expressly shown, interconnection system100may interconnect multiple daughter cards having similar daughter card connectors that mate to similar backplane connections on backplane160. Accordingly, the number and type of subassemblies connected through an interconnection system is not a limitation.

FIG.1shows an interconnection system using a right-angle, separable mating interface connector. It should be appreciated that in other embodiments, the electrical interconnection system100may include other types and combinations of connectors, as the invention may be broadly applied in many types of electrical connectors, such as right-angle, separable mating interface connectors, mezzanine connectors and chip sockets.

Backplane connector150and daughter connector120each contains conductive elements. The conductive elements of daughter card connector120are coupled to traces, of which trace142is numbered, ground planes or other conductive elements within daughter card140. The traces carry electrical signals and the ground planes provide reference levels for components on daughter card140. Ground planes may have voltages that are at earth ground or positive or negative with respect to earth ground, as any voltage level may act as a reference level.

Similarly, conductive elements in backplane connector150are coupled to traces, of which trace162is numbered, ground planes or other conductive elements within backplane160. When daughter card connector120and backplane connector150mate, conductive elements in the two connectors mate to complete electrically conductive paths between the conductive elements within backplane160and daughter card140.

Backplane connector150includes a backplane shroud158and a plurality of conductive elements. The conductive elements of backplane connector150extend through floor514of the backplane shroud158with portions both above and below floor514. Here, the portions of the conductive elements that extend above floor514form mating contacts, shown collectively as mating contact portions154, which are adapted to mate to corresponding conductive elements of daughter card connector120. In the illustrated embodiment, mating contacts154are in the form of blades, although other suitable contact configurations may be employed, as the disclosed technology is not limited in this regard.

Tail portions, shown collectively as contact tails156, of the conductive elements extend below the shroud floor514and are adapted to be attached to backplane160. Here, the tail portions are in the form of a press fit, “eye of the needle” compliant sections that fit within via holes, shown collectively as via holes164, on backplane160. However, other configurations are also suitable, such as surface mount elements, spring contacts, solderable pins, etc., as the disclosed technology is not limited in this regard.

Daughter card connector120includes a plurality of wafers1221. . .1226coupled together, with each of the plurality of wafers1221. . .1226having a housing and a column of conductive elements. In the illustrated embodiment, each column has a plurality of signal conductors and a plurality of ground conductors as discussed below. The ground conductors may be employed within each wafer1221. . .1226to minimize crosstalk between signal conductors or to otherwise control the electrical properties of the connector.

In the illustrated embodiment, daughter card connector120is a right angle connector and has conductive elements that traverse a right angle. As a result, opposing ends of the conductive elements extend from perpendicular edges of the wafers1221. . .1226.

Each conductive element of wafers1221. . .1226has at least one contact tail, shown collectively as contact tails126that can be connected to daughter card140. Each conductive element in daughter card connector120also has a mating contact portion, shown collectively as mating contacts124, which can be connected to a corresponding conductive element in backplane connector150. Each conductive element also has an intermediate portion between the mating contact portion and the contact tail, which may be enclosed by or embedded within a wafer housing.

The contact tails126electrically connect the conductive elements within daughter card and connector120to conductive elements, such as traces142in daughter card140. In the embodiment illustrated, contact tails126are press fit “eye of the needle” contacts that make an electrical connection through via holes in daughter card140. However, any suitable attachment mechanism may be used instead of or in addition to via holes and press fit contact tails.

In the illustrated embodiment, each of the mating contacts124has a dual beam structure configured to mate to a corresponding mating contact154of backplane connector150. The conductive elements acting as signal conductors may be grouped in pairs, separated by ground conductors in a configuration suitable for use as a differential electrical connector. However, embodiments are possible for single-ended use in which the conductive elements are evenly spaced without designated ground conductors separating signal conductors or with a ground conductor between each signal conductor.

In the embodiments illustrated, some conductive elements are designated as forming a differential pair of conductors and some conductive elements are designated as ground conductors. These designations refer to the intended use of the conductive elements in an interconnection system as they would be understood by one of skill in the art. For example, though other uses of the conductive elements may be possible, differential pairs may be identified based on preferential coupling between the conductive elements that make up the pair. Electrical characteristics of the pair, such as its impedance, that make it suitable for carrying a differential signal may provide an alternative or additional method of identifying a differential pair. As another example, in a connector with differential pairs, ground conductors may be identified by their positioning relative to the differential pairs. In other instances, ground conductors may be identified by their shape or electrical characteristics. For example, ground conductors may be relatively wide to provide low inductance, which is desirable for providing a stable reference potential, but provides an impedance that is undesirable for carrying a high speed signal.

For exemplary purposes only, daughter card connector120is illustrated with six wafers1221. . .1226, with each wafer having a plurality of pairs of signal conductors and adjacent ground conductors. As pictured, each of the wafers1221. . .1226includes one column of conductive elements. However, the disclosed technology is not limited in this regard, as the number of wafers and the number of signal conductors and ground conductors in each wafer may be varied as desired.

As shown, each wafer1221. . .1226is inserted into front housing130such that mating contacts124are inserted into and held within openings in front housing130. The openings in front housing130are positioned so as to allow mating contacts154of the backplane connector150to enter the openings in front housing130and allow electrical connection with mating contacts124when daughter card connector120is mated to backplane connector150.

Daughter card connector120may include a support member instead of or in addition to front housing130to hold wafers1221. . .1226. In the pictured embodiment, stiffener128supports the plurality of wafers1221. . .1226. Stiffener128is, in the embodiment illustrated, a stamped metal member. However, stiffener128may be formed from any suitable material. Stiffener128may be stamped with slots, holes, grooves or other features that can engage a wafer.

A side view of a wafer220is shown inFIG.2. Wafer220may correspond to each of wafers1221,1222, . . . ,1226shown inFIG.1. Wafer220includes a housing260with conductors interconnecting contact tails126and mating contacts124. Wafer220further includes insulative portions240and lossy portions250, as well as attachment elements242and244. Further details regarding wafer220are provided in U.S. Pat. No. 7,794,278, which is hereby incorporated by reference.

An example of a printed circuit board is described with reference toFIGS.3and4. A partial top view of backplane160showing a connector footprint310of vias for mating with the contact tails of backplane connector150is shown inFIG.3. The backplane160may be implemented as a printed circuit board as described below. As shown, the connector footprint310includes an array of columns of via patterns320. Each via pattern320corresponds to one differential pair of signal conductors and associated reference conductors.

Columns322and324are shown inFIG.3. A complete connector footprint includes one column for each wafer in connector120. Thus, the connector footprint170ofFIG.1includes six columns. However, the number of columns is not limited and may correspond to the number of wafers in the mating connector. As further shown inFIG.3, adjacent columns322and324are offset by a distance d in a direction344of the columns. The offset distance d may be on the order of one half the distance between the centers of signal vias330and332. However, this is not a limitation.

As shown, each via pattern320includes a first signal via330and a second signal via332, which form a differential signal pair, and ground vias340and342associated with each pair of signal vias330,332. It will be understood that each of the via patterns320matches a pattern of contact tails of backplane connector150shown inFIG.1and described above. In particular, each column of via patterns320corresponds to one of the columns of contact tails of backplane connector150. It will be understood that the parameters of the connector footprint310may vary, including the number and arrangement of via patterns320and the configuration of each via pattern320, provided that the connector footprint310matches the pattern of contact tails in backplane connector150.

In forming the backplane160, a ground plane350is partially removed, such as by patterning a copper layer on a laminate, to form an antipad352, forming a ground clearance surrounding signal vias330and332, so that the dielectric sheet of the attachment layer is exposed. The areas where the ground plane is removed may be called “non-conductive areas” or “antipads”. The antipad322has a size and shape to preclude shorting of ground plane350to signals vias330and332, even if there is some imprecision in forming the signal vias relative to the ground plane, and to establish a desired impedance of the signal path formed by signal vias330and332. InFIG.3, the antipad352is rectangular in shape. However, the antipad352can have any suitable shape and may have rounded corners.

A simplified cross-sectional view of a portion of backplane160in accordance with embodiments is shown inFIG.4. The portion shown may be representative of a signal via in a connector footprint.FIG.4shows the layered structure of backplane160and a signal via450for purposes of illustration. It will be understood that an actual backplane160includes multiple, closely-spaced vias in particular patterns as described below. The backplane160may be implemented as a printed circuit board.

As shown inFIG.4, the backplane160includes multiple layers. Each layer of the multiple layers of backplane160may include a conductive layer and a dielectric sheet, so that the backplane160includes an alternating arrangement of conductive layers and dielectric sheets. Each conductive layer may serve as a ground plane, may be patterned to form conductive traces, or may include a ground plane and conductive traces in different areas. The layers may be formed, during assembly, by stacking multiple sheets of laminate with patterned copper and pre-preg and then pressing them under heat to fuse all the sheets. Patterning the copper may create traces and other conductive structures within the printed circuit board. As a result of fusing, the layers may not be structurally separable in a finished backplane. However, the layers may nonetheless be recognized in the fused structure based on the position of the conductive structures.

The layers may be allocated for different functions and accordingly may have different structural characteristics. In some embodiments, a first portion of the layers, those nearest a surface, may have vias of sufficient diameter to receive contact tails of a connector mounted to the surface. These layers may be called “attachment layers”. A second portion of the layers may have vias of smaller diameter, providing additional area for signal routing. These layers may be called “routing layers”.

In the illustrated embodiment, the backplane160includes attachment layers460,462, etc. and routing layers470,472, etc. The attachment layers are located in an upper portion of the backplane160, and the routing layers are located below the attachment layers. The attachment layers460,462, etc. and the routing layers470,472, etc. are adhered together to form a single structure in the form of a printed circuit board. The number of attachment layers and the number of routing layers in a particular backplane may vary according to application.

As shown inFIG.4, backplane160may include ground planes440between the layers of the structure and may include signal traces442in or between the routing layers. A signal trace444is shown as connected to signal via450.

The signal via450includes plating452in the attachment layers and in one or more of the routing layers. The signal via450may be back drilled in a lower region454of the backplane160to remove the plating. A ground clearance456is provided between signal via450and the ground planes440.

As further shown inFIG.4, the signal via450has a first diameter480in the attachment layers and a second diameter482in the routing layers. The first diameter480is larger than the second diameter482. In particular, the first diameter480is selected to accept a contact tail of the backplane connector150, and the second diameter482is selected in accordance with typical via diameters for printed circuit boards. Because the signal via450has a relatively large first diameter480and because the vias are closely spaced to match high density backplane connector150, little area remains in attachment layers460,462, etc. for signal routing. In routing layers470,472, etc. which are below the vias of the attachment layers, additional area is available for signal routing.

In some embodiments, the vias may have the same diameter in the attachment layers and in the routing layers. For example, the contact elements of the connector may attach to pads on the surface of the backplane160in a surface mount configuration.

In some embodiments, the backplane160may include a conductive surface layer490on its top surface. The conductive surface layer490is patterned to provide an antipad492, or non-conductive area, around each of the signal vias. The conductive surface layer490may be connected to some or all of the ground vias and may provide a contact for a connector ground, such as a conductive gasket pressed between the printed circuit board and a connector mounted to the printed circuit board or a conductive finger extending from a connector or other component attached to the printed circuit board. The conductive gasket and/or the conductive finger may provide current flow paths between grounding structures in the connector and in the printed circuit board, increasing the effectiveness of the ground structures and enhancing signal integrity.

Embodiments of a printed circuit board are described with reference toFIGS.5A,5B and6. A partial top view of an embodiment of an attachment layer, such as attachment layer460, of the backplane160is shown inFIG.5A. In the case of multiple attachment layers, each of the attachment layers of backplane160may have the same configuration.FIG.5Ashows two columns500and502of a connector footprint510. Each of columns500and502includes via patterns, with each via pattern corresponding to a differential signal pair. Thus, column500includes via patterns520and522, and column502includes via patterns524and526.

As further shown inFIG.5A, adjacent columns500and502may be offset by a distance d in a direction of the columns500and502. The offset distance d may be on the order of one half the distance between the centers of the signal vias530and532(FIG.5B). However, this is not a limitation.

In implementations of the printed circuit board, each of columns500and502may include additional via patterns and the connector footprint510may include additional columns of via patterns. The number of via patterns in a column and the number of columns in a connector footprint are not limitations. In general, the number of columns in the connector footprint510may correspond to the number of wafers in connector120(FIG.1) and the number of via patterns in each column may correspond to the number of differential signal pairs in each wafer.

It should be appreciated thatFIG.5Ais partially schematic in that all of the illustrated structures may not in all embodiments be seen in a visual inspection of the top of a printed circuit board. A coating that obscures some of the structures may be placed over the board. In addition, some structures may be formed on layers below the surface of the board. Those layers may nonetheless be shown in a top view so that the relative positions of the structures in the layers may be understood. For example, signal traces and ground planes may not both be visible in the same view of the board, as they are on different vertical planes within the printed circuit board. However, because the relative positioning of signal and ground structures may be important to performance of a printed circuit board, both may be shown in what is referred to as a top view.

An enlarged top view of via pattern520is shown inFIG.5B. Each of the via patterns520,522,524,526may have the same configuration. In the example ofFIGS.5A and5B, each via pattern520,522,524,526of attachment layer460includes a first signal via530and a second signal via532, which form a differential signal pair. The signal vias530and532extend vertically through the attachment layers and may have diameters in the attachment layers that are selected to accept the contact tails156of backplane connector150. In forming the board, a ground plane540is partially removed, such as by patterning a copper layer on a laminate, to form an antipad542, forming a ground clearance between ground plane540and signal vias530and532, so that the dielectric sheet of the attachment layer460is exposed. The antipad542has a size and shape to preclude shorting of ground plane540to signal vias530and532, even if there is some imprecision in forming the vias relative to ground plane540, and to establish a desired impedance of the signal path formed by signal vias530and532. In the embodiment ofFIGS.5A and5B, antipad542is rectangular in shape, and the signal vias530and532are centrally located in antipad522. However, the antipad522may have any suitable shape and may have rounded corners.

Each via pattern520,522,524,526of attachment layer460may further include ground vias550and552associated with signal vias530and532. In this example, ground via550is located near one end of via pattern520adjacent to signal via530, and ground via552is located near an opposite end of via pattern520adjacent to signal via532. In the example ofFIGS.5A and5B, the ground vias550and552overlap respective ends of antipad542. The ground vias550and552may be dimensioned to accept corresponding contact tails156of backplane connector150. The ground vias interconnect the ground planes of some or all of the layers of the backplane160. In particular, the ground vias may extend through all of the layers of the backplane160and may be plated with a conductive material.

Each via pattern520,522,524,526of attachment layer460further includes shadow vias560and562located between the first signal via530and the second signal via532of the differential signal pair. The shadow vias560and562do not accept contact tails of backplane connector150and may have a smaller diameter than the signal vias and the ground vias. The shadow vias560and562may extend through the layers of the backplane160and may be plated or filled with a conductive material to form conductive shadow vias.

As indicated above, the shadow vias560and562are located between signal vias530and532. As shown inFIG.5B, shadow vias560and562are located on a first line570that is perpendicular to a second line572that passes through signal vias530and532in a direction of the columns500,502. The first line570may be located midway between signal vias530and532, such that the shadow vias560and562are equally spaced from signal vias530and532. In addition, the shadow vias560and562may at least partially overlap the edges of antipad542, thus effectively electrically shorting opposite sides of antipad542between signal vias530and532and dividing antipad542into two separate antipad sections respectively surrounding signal vias530and532.

The shadow vias560and562include pads564and566, respectively. In some embodiments, the pads of the shadow vias560and562physically and electrically contact each other, while in other embodiments the pads of the shadow vias560and562are spaced apart and do not contact each other.

In the example ofFIG.5A, each of via patterns520,522,524and526includes two shadow vias located between the signal vias of each differential signal pair. In further embodiments, each via pattern may include a single shadow via located between the signal vias or more than two shadow vias. Furthermore, the shadow vias may be implemented as one or more circular shadow vias or one or more slot-shaped shadow vias.

The connector footprint510shown inFIGS.5A and5Bmay further include additional shadow vias between adjacent via patterns in each column. As shown inFIG.5B, shadow vias580and582are located between via patterns520and522and, more particularly, between ground via552of via pattern520and ground via550of via pattern522. Additional shadow vias may be located between the other via patterns as well. The additional shadow vias580and582do not accept contact tails of backplane connector150and may have a smaller diameter than the signal vias and the ground vias. The additional shadow vias580and582may, for example, have the same diameters as the shadow vias560and562located between the signal vias of the differential signal pair. The additional shadow vias580and582may extend through the layers of the backplane160and may be plated or filled with a conductive material.

In the example ofFIGS.5A and5B, additional shadow vias580and582may be located on a third line584that is perpendicular to second line572and is located midway between ground vias552and550of adjacent via patterns. The additional shadow vias580and582may be equally spaced from ground vias550and552of adjacent via patterns. Further, the additional shadow vias580and582are located outside the antipad542of each via pattern.

In the example ofFIGS.5A and5B, two additional shadow vias are located between the adjacent via patterns in each column500,502of the connector footprint510. In further embodiments, the connector footprint may include a single additional shadow via located between the ground vias of adjacent via patterns or more than two additional shadow vias. Furthermore, the additional shadow vias may be implemented as one or more circular shadow vias or one or more slot-shaped shadow vias.

A simplified cross-sectional view of a portion of backplane160in accordance with embodiments is shown inFIG.6. The portion shown may be representative of via pattern520in connector footprint510.FIG.6shows the layered structure of backplane160in via pattern520for purposes of illustration. It will be understood that an actual backplane includes multiple via patterns as described herein. The backplane160may be implemented as a printed circuit board.

As shown inFIG.6, the backplane160includes multiple layers. Each layer of the multiple layers of backplane160may include a conductive layer and a dielectric sheet, so that the backplane160includes an alternating arrangement of conductive layers and dielectric sheets. Each conductive layer may serve as a ground plane, may be patterned to form conductive traces or may include a ground plane and conductive traces in different areas. The layers may be formed, during assembly, by stacking multiple sheets of laminate with patterned copper and pre-preg and then pressing them under heat to fuse all the sheets. Patterning the copper may create traces and other conductive structures within the printed circuit board. As a result of fusing, the layers may not be structurally separable in a finished backplane. However, the layers may nonetheless be recognized in the fused structure based on the position of the conductive structures.

The layers may be allocated for different functions and accordingly may have different structural characteristics. In some embodiments, a first portion of the layers, those nearest the surface, may have vias of sufficient diameter to receive contact tails of a connector mounted to the surface. These layers may be called “attachment layers”. A second portion of the layers may have vias of smaller diameter, providing additional area for signal routing. These layers may be called “routing layers”.

In the illustrated embodiment, the backplane160includes attachment layers660,662, etc. and routing layers670,672, etc. The attachment layers are located in the upper portion of the backplane160, and the routing layers are located below the attachment layers. The attachment layers660,662, etc. and the routing layers670,672, etc. are adhered together to form a single structure in the form of a printed circuit board. The number of attachment layers and the number of routing layers in a particular backplane may vary according to application.

As shown inFIG.6, backplane160may include ground planes640between the layers of the structure and may include signal traces in or between the routing layers. It will be understood that the ground planes640do not contact the signal vias530and532and may be separated from the signal vias by providing antipad542(FIG.5B). A signal trace644is shown as connected to signal via530, and a signal trace646is shown as connected to signal via532.

The signal vias530and532include plating in the attachment layers and in one or more of the routing layers. The signal vias530and532may be backdrilled in the lower region of the backplane160to remove the plating.

As further shown inFIG.6, the signal vias530and532may have a first diameter in the attachment layers and a second diameter in the routing layers, where the first diameter is larger than the second diameter. In particular, the first diameter is selected to accept a contact tail of the backplane connector150, and the second diameter is selected in accordance with typical via diameters for printed circuit boards.

In one non-limiting example, the first diameter of signal vias530and532in the attachment layers is 15.7 mils and the second diameter in the routing layers is 11 mils. These diameters are primary drill diameters. The primary drill diameter is the size of the hole before the printed circuit plating process. The center-to-center spacing of the signal vias530and532may be in a range of 55 mils (1.2 mm) to 79 mils (2.0 mm), and the center-to-center spacing between columns of via patterns may be in a range of 71 mils (1.8 mm) to 98 mils (2.5 mm). In this example, the shadow vias560,562have primary drill diameters of 13.8 mils and are equally spaced from signal vias530and532. The ground vias550and552may have primary drill diameters of 15.7 mils, and the additional shadow vias580,582may have primary drill diameters of 13.8 mils. The signal vias530and532may have primary drill diameters in a range of 14 to 22 mils, and the shadow vias560and562may have primary drill diameters in a range of 8 to 14 mils. The signal vias may be 3 to 6 mils larger in diameter than the shadow vias. The signal vias are dimensioned to accept contact tails of the connector, whereas the shadow vias are dimensioned in accordance with typical via diameters of the printed circuit board. It will be understood that these dimensions are not limiting and that other dimensions may be utilized.

Further embodiments of a printed circuit board are described with reference toFIGS.7and8. An enlarged top view of a via pattern720is shown inFIG.7. The via pattern720may be the same in all of the layers of the printed circuit board above a signal breakout layer. An enlarged top view of a via pattern820is shown inFIG.8. The via pattern820may be used in the signal breakout layer and shows an antipad configuration in a layer below the signal breakout layer.

The via pattern720ofFIG.7may have the same configuration as the via pattern520ofFIG.5B, except for the antipad configuration. In particular, via pattern720includes a first antipad740that surrounds signal via530and a second antipad742that surrounds signal via532. Each of the antipads740and742is an area of the respective layer of the printed circuit board where ground plane540is removed, such as by patterning a copper layer on a laminate, to form a ground clearance between the ground plane540and the signal vias530and532. The antipads740and742have a size and shape to preclude shorting of ground plane540to signal vias530and532, even if there is some imprecision in forming the vias relative to the ground plane540, and to establish a desired impedance of the signal path formed by signal vias530and532.

In the embodiment ofFIG.7, the antipads740and742are rectangular in shape, and the signal vias530and532are more or less centrally located in the respective antipads740and742. However, the antipads740and742may have any suitable shape and may have rounded corners. As shown inFIG.7, ground via550is located on one edge of antipad740, and shadow vias560and562are located on an opposite edge of antipad740. Similarly, ground via552is located on one edge of antipad742, and shadow vias560and562are located on an opposite edge of antipad742.

The embodiment ofFIG.7provides two distinct antipads740and742, one for each of the signal vias530and532, independent of the configuration of shadow vias560and562. In contrast, the embodiment ofFIG.5Bprovides a single antipad542that surrounds signal vias530and532. In the embodiment ofFIG.5Bthe shadow vias560and562may form a conductive bridge across antipad542, depending on the size and location of shadow vias560and562. However, the shadow vias560and562do not necessarily form a bridge across antipad542in the embodiment ofFIG.5B.

In the embodiment ofFIG.8, a routing layer that serves a signal breakout layer for the signal vias530and532is shown. The via pattern820ofFIG.8may be located in the routing layers below the via pattern720ofFIG.7. As shown, a signal trace850connects to signal via530, and a signal trace852connects to signal via532. Each of the signal traces850and852has a first width throughout most of its length and a second width near the respective signal vias530and532, wherein the second width is greater than the first width. The wider portions near signal vias530and532are provided to control impedance in the regions near the transition to the signal vias530and532.

The via pattern820further includes a first antipad860which surrounds signal via530and a second antipad862which surrounds the signal via532. The antipads860and862may correspond to the antipads740and742, respectively, ofFIG.7except that antipad860includes a ground plane projection864, and antipad862includes a ground plane projection866. Each of the projections864and866is an area of ground plane840that projects into the respective antipad toward the signal vias and is located underneath the respective signal traces850and852. As shown, each of the projections864and866may be curved to correspond to the curvature of the respective signal vias530and532. The projections864and866are located close to, but do not physically or electrically contact, the signal vias530and532. The projections864and866provide a more controlled impedance connection between the signal traces850and852and the signal vias530and532than is the case where the signal traces pass over a substantial area of the antipad where the ground plane840has been removed. In particular, the transmission lines where the signal traces are spaced from the ground plane840extend almost to the signal vias530and532.

As described above, the printed circuit boards shownFIGS.5A,5B,7and8and described above may include shadow vias560and562located between signal vias530and532, and may include additional shadow vias580and582located between adjacent via patterns. The shadow vias560,562,580and582may be conductive shadow vias that are plated or filled with a conductive material.

The printed circuit boards may also include ground plane540, referred to herein as a conductive surface film540, on its top surface. The conductive surface film540may be electrically connected to ground. The conductive surface film540may be formed on an uppermost dielectric layer of the printed circuit board and may be patterned to form antipads, such as antipad542. The conductive surface film540covers the entire surface of the printed circuit board, except in areas, such as antipads, where it is removed by a patterning process. In particular, the conductive surface film540surrounds each of the via patterns and surrounds each of the antipads of the printed circuit board.

In some embodiments, the conductive shadow vias of each via pattern may be electrically connected to the conductive surface film540. For example, as shown in FIG. shadow vias560and562overlap the edges of antipad542and thus are in electrical contact with conductive surface film540. In particular, shadow vias560and562may include pads564and566, respectively, which are electrically connected to conductive surface film540. As further shown inFIG.5B, additional shadow vias580and582are electrically connected to conductive surface film540. By providing grounded shadow vias in close proximity to signal vias530and532, the connector footprints disclosed herein exhibit improved performance.

The ground vias are also electrically connected to the conductive surface film. As shown inFIG.5B, ground vias550and552overlap the edge of antipad542and are electrically connected to conductive surface film540.

Backplane connector150shown inFIG.1and described above may include an electrical contact for a connector ground, such as a conductive gasket, a conductive finger, or other conductive element. The connector ground may be in electrical contact with the conductive surface film540after the connector is installed on the printed circuit board, thereby establishing electrical continuity between the ground of the connector and the ground of the printed circuit board. The conductive gasket, conductive finger or other conductive element may be in physical and electrical contact with conductive surface film540but is not attached to the conductive surface film540, such that the two elements are separable. This configuration is in contrast to the contact tails of the connector, which may be inserted into and soldered to respective signal vias and ground vias of the printed circuit board. The conductive gasket may be pressed between the printed circuit board and a connector mounted to the printed circuit board. The conductive finger may extend from a connector or other component attached to the printed circuit board. The conductive gasket and/or the conductive finger may provide current flow paths between grounding structures in the connector and in the printed circuit board, increasing the effectiveness of the ground structures and enhancing signal integrity.

It will be understood that the electrical connection between the conductive shadow vias and the conductive surface film is not limited to the via patterns shown inFIGS.5A,5B,7and8. The conductive shadow vias may be electrically connected to a conductive surface film in any via pattern which has a conductive surface film and which utilizes conductive shadow vias.

In embodiments in which a printed circuit board includes a conductive surface layer, such as conductive surface layer490or conductive surface film540, that is contacted by a conductive structure connecting ground structures within a connector or other component to grounds within the printed circuit board, shadow vias may be positioned to shape the current flow through the conductive surface layer. Conductive shadow vias may be placed near contact points on the conductive surface layer of members that connect to the ground structure of the connector. For example, if a conductive gasket or conductive finger makes such a connection, shadow vias may be preferentially positioned near contact points of the gasket or conductive finger on the conductive surface layer. This positioning of shadow vias limits the length of a primary conductive path from that contact point to a via that couples that current flow into the inner ground layers of the printed circuit board.

Limiting current flow in the ground conductors in a direction parallel to the surface of the board, which is perpendicular to the direction of signal current flow, may improve signal integrity. In some embodiments, the shadow vias may be positioned such that the length of a conducting path through the surface layer to the nearest shadow via coupling the conductive surface layer to an inner ground layer may be less than the thickness of the printed circuit board. In some embodiments, the conducting path through the surface layer may be less than 50%, 40%, 30%, 20% or 10% of the thickness of the board.

In some embodiments, shadow vias may be positioned so as to provide a conducting path through the surface layer that is less than the average length of the conducting paths for signals between the connector or other component mounted to the board and inner layers of the board where the conductive traces are connected to the signal vias. In some embodiments, the shadow vias may be positioned such that the conducting path through the surface layer may be less than 50%, 40%, 30%, 20% or 10% of the average length of the signal paths.

In some embodiments, shadow vias may be positioned so as to provide a conducting path through the surface layer that is less than 5 mm. In some embodiments, the shadow vias may be positioned such that conducting path through the surface layer may be less than 4 mm, 3 mm, 2 mm or 1 mm.

It has been discovered that connector footprints of the type shown inFIGS.5B,7and8and described above provide improved performance as compared with the connector footprints shown inFIG.3. In particular, the connector footprints ofFIGS.5B,7and8, exhibit reduced crosstalk between signal vias in offset adjacent columns500and502. The reduced crosstalk extends to very high operating frequencies, such as 18-30 GHz. The disclosed connector footprints also exhibit improved differential mode and common mode performance.

The disclosed technology is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the drawings. The disclosed technology is capable of other embodiments and of being practiced or of being carried out in various ways. Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” “having,” “containing,” or “involving,” and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.

Having thus described at least one illustrative embodiment of the invention, various alterations, modifications and improvements will readily occur to those skilled in the art.

For example, layers may be described as upper layers, or “above” or “below” other layers. It should be appreciated these terms are for ease of illustration and not a limitation on the orientation of layers. In the embodiment illustrated, “upper” refers to a direction towards a surface of a printed circuit board to which components are attached. In some embodiments, components may be attached to two sides of a printed circuit board, such that upper and lower may depend on which vias are being considered. Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention.

Further, it was described that each column of signal conductors within a connector may comprise pairs of signal conductors with one or more ground conductors between each pair. In some embodiments, the signal conductors and ground conductors may be arranged such that each pair of signal conductors is between and adjacent to two ground conductors. Such connectors may have a footprint with pairs of signal vias530,532with one or more ground vias in between each pair of signal vias, and, in some embodiments, with each pair of signal vias530,532between and adjacent to two ground vias550,552. However, it should be appreciated that, in some embodiments, the ground conductors of the connector, and corresponding ground vias550,552of the printed circuit board, may be omitted from a column. Regardless of the configuration of ground conductors or ground vias, one or more shadow vias may nonetheless be disposed between the signal vias of each pair.

Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.