Patent ID: 12206417

Like references symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

In contemporary electronic systems, space is at a premium on customer circuit boards, e.g. on a circuit board near a processor. Additionally, thermal management considerations place limits on the efficiency and power dissipation of power supplies at, or near, the point of load. Many very large scale integrated (“VLSI”) semiconductor dies such as central processing units (“CPU”), graphics processing units (“GPU”), and application specific integrated circuits (“ASIC”) are mounted to a multilayer ceramic substrate which translates the electrical connections from the die to larger connections suitable for interfacing with a customer motherboard. As feature sizes decrease and transistor counts increase, so too do the power supply current requirements for such large chips. Current requirements for a typical CPU can easily exceed 200 amps creating challenges for the package and system designers to efficiently supply such high currents. For example, power connections between the component package (such as a chip carrier or substrate or other package in or on which the semiconductor die is mounted) and the printed circuit board (PCB) on which the package is mounted may demand a large number of connector pins, leads, solder bumps, etc., to carry very high currents challenging package designers to accommodate both power and signal requirements. In many cases the large number and high frequency demands of signals may limit the maximum voltage, e.g. the interlayer breakdown voltage, to which the substrate or package may be subjected, in some cases as low as a few volts, further challenging power connections to and within the package or substrate.

A Factorized Power Architecture well suited for supplying power to low voltage high current loads is described in Vinciarelli, Factorized Power with Point of Load Sine Amplitude Converters, U.S. Pat. No. 6,975,098, issued Dec. 13, 2005 (the “Micro FPA Patent”) and U.S. Pat. No. 6,984,965, issued Jan. 10, 2006 (the “FPA Patent”) (both assigned to VLT, Inc. of Sunnyvale, CA, and the entire disclosure of each patent is incorporated herein by reference). Power converters which function as DC-to-DC transformers called Voltage Transformation Modules (“VTM”) and Sine Amplitude Converters (“SAC”) which have a transfer function approximating Vo=KVTM*Vin−Io*RVTMare described in Vinciarelli, Factorized Power with Point of Load Sine Amplitude Converters, U.S. Pat. No. 6,930,893, issued Aug. 16, 2005 (the “SAC Patent”) and in Vinciarelli, Point of Load Sine Amplitude Converters and Methods, U.S. Pat. No. 7,145,786, issued Dec. 5, 2006 (the “POL SAC Patent”) (both assigned to VLT, Inc. of Sunnyvale, CA, the entire disclosure of each patent is incorporated herein by reference).

I. In-Package Power Conversion Topologies

A. Fault-Tolerant Topology

FIG.5is a replica of FIG. 14 from U.S. Pat. No. 9,112,422, issued Aug. 18, 2015, which is incorporated herein by reference in its entirety (hereinafter the “FT Patent”). InFIG.5, a power converter400is shown including a driver420connected to drive one or more point-of-load (“POL”) current multiplier circuits430having inputs447,448connected to the driver outputs427,428via an AC power bus410. The driver420may comprise a full-bridge fault-tolerant input circuit such as input circuit 250 of FIG. 11 in the FT Patent and a switch controller425similar to the switch controller described in connection with FIG. 11 of the FT Patent.

The POL circuit430may include a transformer circuit440and a rectification circuit450. The transformer circuit440may include none, one, or both, of resonant capacitors441,442shown inFIG.5connected to the primary winding82of transformer81. The secondary winding may be connected to a full-bridge fault-tolerant rectification circuit450as shown inFIG.5and described in the FT Patent. The full-bridge fault-tolerant rectification circuit450may use switches, R1, R2, R3, R4, operated as rectifiers in the manner described in the FT Patent in connection with output circuit 100 of FIG. 3 (of the FT Patent) and may preferably employ the common-source synchronous rectifiers described in connection withFIGS.7and8(of the FT Patent). Note that a simplified symbol is used inFIG.5for switches S1-S4and R1-R4(instead of the enhancement mode MOSFET symbols used, e.g. in FIGS. 2-4, 7, 8, 11 of the FT Patent) in which the arrow indicates the direction of current flow through the intrinsic body drain diode when the switch is open.

As its name implies, the POL circuit430(FIG.5) may be designed to be deployed as close to the point of load, where space and thermal requirements are stringent, as possible. Because the driver circuit420does not need to be close to the point of load, it may be deployed elsewhere, away from the point of load, reducing the space required by the POL circuitry and reducing the power dissipation in proximity to the load. One benefit of removing the driver circuitry from the POL is that a larger transformer structure and array of output switches (R1-R4) may be used in the POL circuit thereby improving overall converter efficiency and further reducing dissipation at the POL. Similarly, larger input switches (S1-S4) may be used in the driver circuit to further improve overall efficiency without impacting space considerations at the POL.

However counter intuitive separating the driver420from the POL circuitry430and deploying an AC bus may initially seem, closer inspection refutes such objections. For example, power carried by the AC bus410may be spectrally pure (sine wave) and voltage and current slew rates substantially lower than those typically found in other switching power converter topologies, such as buck and multiphase buck converters, and even in the signal paths of computer circuitry, reducing concerns about noise and electromagnetic emissions.

The POL circuit430may be enclosed as a single module, i.e. packaged for deployment as a single self-contained unit (as shown inFIGS.5,6, and8), or as a multiplicity, specifically a pair, of modules for deployment as component pairs, e.g.440and450, (as shown inFIGS.1-3,7). Because switches R1-R4, need only withstand the output voltage, the rectification circuit450may be integrated (with or without the control circuitry, e.g. as shown in FIGS. 7 and 8 of the FT Patent) onto a die with circuitry to which it supplies power, e.g. a processor core or an ASIC.

B. Alternative POL Topology

Referring toFIG.6, an alternate embodiment 401 of the converter topology is shown comprising driver circuit481and POL circuit431. In addition to outputs427,428for driving the AC power bus410, the driver circuit481as shown also includes a bias output429for supplying a small amount of power to operate control circuitry in the POL, and a control output426for supplying timing and/or control information to the POL circuit431. A small signal bus415may be provided to connect driver outputs429,426, which may be low power and low voltage signals, to the input of the POL circuit431.

An example of suitable control circuitry is described in Digital Control of Resonant Power Converters, Vinciarelli et al., U.S. Pat. No. 9,166,481, issued Oct. 15, 2015, assigned to VLT, Inc. and incorporated here by reference (the “Controller patent”), e.g. in connection withFIGS.15and16. The driver may further include clamp and control circuitry to implement the clamped capacitor techniques to increase efficiency as described in Clamped Capacitor Resonant Power Converter, Vinciarelli, U.S. patent application Ser. No. 14/874,054, filed Oct. 2, 2015 (the “CSAC” patent application), assigned to VLT, Inc. and incorporated here by reference. As shown inFIG.6, the converter401may be partitioned with the resonant capacitors441,442located in the driver module481. Alternatively, a single resonant capacitor may be located within the driver for ease of implementing the clamp circuitry.

The POL circuit431as shown may include a switch driver460having inputs449,446for receiving a bias voltage (449) and a control signal (446) from the driver circuit481. The bias voltage provides power to operate the switch driver and the control signal provides timing information to the switch driver to synchronize operation of the secondary switches451,452,453,454as controlled rectifiers. The secondary controller200B shown inFIG.15of the Controller patent may be used for the POL switch driver460inFIG.6. Although the switch driver460is shown inFIG.6with a dedicated bias supply from the driver, it may, as shown in the Controller patent, derive the power it requires to operate from the control signal or from an independent bias supply. The switch driver460may alternatively be co-packaged with, or integrated within, the driver circuit481and the secondary switches may be driven directly by the driver circuit481, in which case the small signal bus may be used to carry gate drive signals for the secondary switches instead of the bias and timing/control signals shown.

The POL circuit431may be enclosed as a single module, i.e. packaged for deployment as a single self-contained unit, or as a plurality of modules for deployment as component parts, e.g. transformer module440, secondary switches451-454, and driver circuit460. Because the secondary switches451-454need only withstand the output voltage, the rectification circuit450may be integrated with driver circuitry460onto a single die or even on the same die as the circuitry to which it supplies power, e.g. a processor core, such as a GPU, CPU, or ASIC.

C. Single-Driver Multi-POL Topology

Referring toFIG.7, another embodiment of the topology is shown as converter402including a single driver circuit481and a plurality of POL circuits,431-1,431-2. The driver circuit481and POL circuits431-1,431-2may be the same as driver circuit481and POL circuit431shown inFIG.6, respectively. The converter402may include an AC bus410connected to outputs427,428of driver circuit481and a small signal bus415(low power, low voltage) connected to the bias429and control426outputs of the driver481for establishing the requisite connections to each POL circuit431-1,431-2.

The POL circuits may be connected to operate with their outputs413,414connected in parallel for low voltage loads such as a CPU, GPU, or ASIC101. Alternatively, inputs to the POL circuits may be connected in series for lower output voltages. To summarize, power may be supplied to the POL circuits431by the driver481at a bus voltage, Vbus, that is a multiple, X, times greater than the voltage, Vload, required by the load (e.g., one or more semiconductor chips101). The multiple X may preferably be an integer (or alternatively a non-integer rational number), preferably at least 5, or greater, e.g., 10, 20, and more preferably 40 or more. Each POL circuit may have a fixed voltage transformation ratio, K=Vout/Vin at a load current, where K may be equal to or greater than the turns ratio or step-down ratio, N, of the respective transformer in each POL circuit, depending for example on the output circuitry. The voltage transformation ratio, K, of each POL circuit may be less than or equal to the inverse of the multiple, X=Vbus/Vload, depending on the number and configuration of POL circuits supplying the load. For example, with the inputs and outputs of two or more POL circuits connected in parallel, the bus voltage, Vbus, may be set to X=1/K times the load voltage, Vload: Vbus=Vload/K. Alternatively, it may be preferable for very low output voltages, to arrange a number, M, of POL circuits with their respective inputs connected in series and outputs connected in parallel, in which case the bus voltage Vbus may be set to X=1/(M*K) times the load voltage, Vload: Vbus=Vload/(M*K). The POL circuits431-1,431-2may be deployed as close as possible to the load or preferably co-packaged together with the load as shown schematically inFIG.7and mechanically inFIGS.1-3.

D. Integrated Driver Regulator

Referring toFIG.9, another power converter system403is shown including a driver490electrically connected to the semiconductor package100via connections formed by a system PCB in which the driver490and semiconductor package100may be mounted. The bias and control connections (415,FIG.6) and AC power connections (410,FIG.6) between the driver490and the substrate102are not shown inFIG.9for clarity, however, it should be understood that the desired connections, e.g. as shown inFIGS.5-7may be provided in the manner described above. The driver490as shown inFIG.9may include the transformer driver circuitry481(which may be of the type shown inFIG.5or7), a power regulator circuit482, and a supervisory circuit483. The power regulator482may be used to control the voltage, VF, input to the driver circuit481as a means of controlling the AC voltage supplied to the POL circuits431-1,431-2and in turn the DC output voltage to the semiconductor die101.

The supervisory circuit483may be connected to communicate with the semiconductor die101and optionally the POL circuits431-1,431-2via a digital or analog communication bus497as shown inFIG.9. Although shown as a single bus, the semiconductor die101and POL circuits431may have one or more separate buses for direct communication on the substrate102and the supervisory circuit483may have separate busses for communication with the die101and with the POL circuits431, e.g. to accommodate different communication speeds and protocols. The supervisory circuit483may be connected to communicate with external system components via a digital or analog communication bus495as shown inFIG.9, e.g. to report on conditions in the semiconductor package or power system, e.g. temperature, voltage, current, power, fault conditions, etc. or to receive commands, e.g. reset, disable, etc. For example, some CPU's require the power system to adjust the voltage supplied to the CPU in response to commands issued by the CPU, e.g. many Intel processors send VID information to a voltage regulator which in turn adjusts the voltage supplied to the processor. The supervisory circuit483may receive such voltage commands from the semiconductor die101via bus497and issue appropriate commands to regulator482via digital or analog communication bus496to adjust the output voltage. The regulator may, in response to commands received from the supervisory circuit483, adjust the DC output voltage of the output circuits (via the control voltage, VF) to comply with the requirements of the semiconductor die101.

E. Multi-Driver Multi-Rail Topology

Referring toFIG.13, another embodiment of the topology is shown as converter404, which is configured to supply multiple voltage supply rails, V1, V2, to the semiconductor load101. Converter404includes two driver circuits490-1,490-2for driving two POL circuits,431-1and431-2, respectively. The driver circuits490-1,490-2and POL circuits431-1,431-2, may be of the same type as driver circuit490(shown inFIG.9) and POL circuits431(shown inFIG.6), respectively. For simplicity, the connections between the drivers and POL circuits and semiconductor package are shown as single connections, it being understood that each may include an AC power bus, a control bus, and communications bus as described above. Preferably, the drivers may be synchronized to the same clock as shown inFIG.13by the broken arrow from driver490-1(the master) to driver490-2(slave). Preferably, the POL circuits431-1and431-2may be co-packaged as a single POL circuit module431. Each driver may, in response to commands received from the semiconductor die101, adjust the DC output voltage of the POL circuit associated with it to comply with the requirements of the semiconductor die101. For example, driver490-1may adjust the output V1of POL circuit431-1and driver490-2may adjust the output V2of POL circuit431-2.

F. Driver Compensation

Separation of the driver481and integrated controller425(FIG.6) from the POL circuits431may introduce parasitic capacitances and inductances, which, depending upon the layout of the customer's system board, e.g. the distance between driver and POL circuits and the size and routing of the electrical connections between them, may adversely affect operation of the converter. For example, the parasitic inductance may lower (raise) the resonant frequency (period) of the resonant circuit (formed by the resonant capacitors441,442and the transformer440) which if uncompensated can lead to timing errors in the operation of the switches disrupting zero-voltage switching (ZVS) and zero-current switching (ZCS) operation, which in turn may lead to increased losses, power dissipation, and noise.

Preferably, the driver481may include compensation circuitry able to detect and adjust for the effects of parasitic capacitances and inductances introduced by the separation of driver and POL circuits and the vagaries of different system board layouts on converter operation. One method uses current detection, e.g. in one or more of the primary switches (e.g. switches421,422,423,424inFIG.6) of the driver circuit (using known techniques such as sensing the voltage across a switch while in the ON state) to detect errors in the switch timing. For example, if the compensation circuitry detects that the resonant current at the end of a power transfer interval has not returned to zero, the controller may incrementally increase the duration of the power transfer intervals until the current returns to zero or within a tolerance band of zero, e.g. 1% of the maximum resonant current. For the clamped version described in the CSAC patent application, the compensation circuitry may additionally sense the rate of change of the switch current at the end of the first resonant interval, extending it until the rate of change of the current returns to zero, or within a tolerance band of zero, or within a percentage of the maximum rate of change, e.g. 10%, 5%, or 1%. In this way, the compensation circuitry may adjust the overall timing of the converter operating cycle and/or specific aspects of the converter operating cycle, e.g. the power transfer intervals (described in the SAC, POL-SAC, and Controller patents), or the first and second resonant intervals (described in the CSAC patent application), etc.

II. Semiconductor Package with Top-Mounted Integrated POL Circuits

InFIGS.1,2and3, a semiconductor package100is shown (in isometric, top plan, and side views, respectively) including a multilayer substrate102, a large semiconductor die101, such as an ASIC, CPU, or GPU, and a plurality of POL modules110-1,110-2mounted to the substrate adjacent to the semiconductor die101. As shown inFIG.8, the POL modules110may be packaged as a leadless module, such as described in Vinciarelli, et al., Panel Molded Electronic Assemblies with Multi-Surface Conductive Contacts, application Ser. No. 14/731,287, filed Jun. 4, 2015, and incorporated here by reference (the “Panel Mold” application”), having connections115(FIGS.1,8) for surface mount soldering to respective conductive pads on the substrate102and preferably include shielding for improved low noise performance. (See, e.g. leadless electronic module100described in connection withFIGS.1-3of the Panel Mold application.) The POL modules110-1and110-2(FIGS.1-3) may each include a respective POL circuit, e.g.431-1,431-2, as described in connection withFIG.7.

Referring toFIG.1, the POL modules110-1,110-2are shown having a multiplicity of electrical contacts115arranged along their respective perimeters. The contacts may be formed as shown inFIGS.1-3and8(and as described in the Panel Mold application) to extend along the entire vertical span of the perimeter walls and onto the top and bottom module surfaces. The common terminals may be extended as shown onto the top and bottom surfaces to form shielding. As shown for the two POL Module example inFIGS.1-3, a plurality of discrete components105, such as capacitors, e.g. for filtering, may be provided in the free space along the semiconductor die101. It may be preferable for very high current applications to use four POL modules, each mounted along a respective one of the four sides of the semiconductor die101to lower the interconnection resistance between the POL module outputs and the die. Using four POL modules to power the die may allow a reduction in the length of each POL module, e.g. by a factor of two, leaving space for discrete components such as capacitors along a respective one of the four sides of the semiconductor die101.

InFIG.2, several of the contacts115are labeled to show their preferred function. For example, at the left end of each POL module as shown inFIG.2, two terminals are labeled consistent withFIG.7showing the AC power inputs447-1and448-1for module110-1and447-2and448-2for module110-2; similarly, two terminals are labeled showing the respective bias and control inputs:449-1and446-1for POL module110-1and449-2and446-2for POL module110-2. A multiplicity of output terminals413-1,413-2and ground terminals414-1,414-2are provided along the perimeter of the POL modules110-1,110-2respectively to provide a low impedance distributed connection to the substrate.

InFIG.7, the substrate102of semiconductor package101is represented with broken lines: electrical connections between the substrate102and a system board (to which it may be connected) are represented by interface connections465,466,467-1,468-1,467-2, and468-2; connections contained within the broken lines may be formed by the substrate102; and connections outside the broken lines may be formed by the system board which typically may be a multi-layer printed circuit board (“PCB”). The driver circuit481may be mounted away from the point-of-load, e.g. the semiconductor die101or the semiconductor package100, on the system level board, which may provide electrical connections between the driver and the semiconductor package100or substrate102as shown symbolically inFIG.7. Note that connections to the semiconductor die101, which may be great in number, are not shown inFIG.7for clarity.

The substrate102, in typical applications, carries a multitude of electrical connections between the semiconductor die101and a system-level PCB using, e.g. connector pins, ball grid array, land grid array, or other connection schemes. The breakdown voltage of the substrate102may be very low, e.g. on the order of 3 to 5 volts; the number of interface connections available for power connections between the substrate102and the system PCB may be limited due to the large number of input/output signals (“I/Os”) required by the semiconductor die101; and consequently the ability to efficiently conduct large power supply currents may be limited. InFIG.7, the POL circuit bias power connections449-1and449-2and control connections446-1and446-2are shown connected to bias and control interface connections465,466respectively. The POL circuit power connections447-1,447-2,448-1, and448-2are shown connected to a power interface connections467-1,467-2,468-1,468-2.

As shown, the bias and control signals (FIG.7), which are relatively low in voltage and power, may be handled by the substrate102and interface connections465,466in the same manner as normal I/O signals to, and within, the package, e.g. the bias and control signals may be routed laterally along the substrate as shown by the small signal bus415within the substrate102(FIG.7). However, connections to the AC power bus410, which may need to carry voltages exceeding the voltage capabilities of the substrate102, may not be suitable for wiring on the substrate. Accordingly,FIG.7shows a separate set of interface connections (467,468) for carrying AC power from the bus410to each of the POL circuits (431-1,431-2): interface connections467-1and468-1for POL circuit431-1; and interface connections467-2and468-2for POL circuit431-2. The AC power interface connections467and468will be described in greater detail with reference to the semiconductor package drawings ofFIGS.1-4.

A. High Voltage Connections

The section taken along lines4-4(FIG.2) is shown enlarged in the cross-sectional view ofFIG.4providing physical detail of the AC power bus410-2(FIGS.4,7) in the substrate102. Because its voltage may exceed the voltage rating of the substrate, the AC power bus, e.g.410-2, may be kept as short as possible in the substrate preferably extending vertically through the thickness of the substrate102from the interface connections467-2,468-2on the bottom of the substrate to the conductive pads117-2,118-2on top of the substrate for mating with POL module terminals447-2,448-2, respectively. The interface connections (e.g.,467-2,468-2) on the bottom of the substrate102may be electrically coupled to connectors on the system board using, e.g. connector pins, ball grid array, land grid array, or other connection schemes. All lateral travel of the AC power bus in the substrate is preferably eliminated or, if unavoidable, then minimalized. In the example shown inFIGS.1-4, the AC power bus is divided into two sections410-1and410-2each of which consist of a pair of plated vertical through holes in the substrate102around which a minimum keep out distance is maintained to account for the low interlayer breakdown voltage of the substrate. Thus as shown inFIG.4, AC power bus410-2includes two vertical conductive through holes (collectively410-2) connected to interface contacts467-2,468-2on the bottom of the substrate102and conductive pads117-2,118-2on the top of the substrate102, all of which are preferably vertically aligned minimizing or eliminating any lateral conduction requirements for the AC power bus. The heavy broken lines103inFIG.4indicate a volume104of the substrate102defined by a projection around the high voltage connection in which no other electrical features should be formed to manage the relatively high voltage requirements of the AC power bus and the low breakdown voltage of the substrate. Ground referenced through holes may be formed in the substrate around the keep-out area to provide shielding.

B. Magnetic Field Management

Referring toFIG.12, an example of a magnetically permeable core structure150in the POL modules110-1,110-2is shown including a multilayer printed circuit board151in which the transformer windings (not shown) may be formed around a plurality of holes155. The transformer may incorporate self-aligned windings as described in Vinciarelli, Self-Aligned Planar Magnetic Structure and Method, U.S. patent application Ser. No. 14/822,561, filed Aug. 10, 2015, (the “Self-Aligned” patent application) assigned to VLT, Inc. of Sunnyvale, CA, the entire disclosure of which is incorporated herein by reference). Core legs154may be placed in the holes155and mated with top and bottom core plates152and153when assembled to form complete magnetic loops. A small gap of 1 mil or less may be provided between one or both of the top and bottom core plates and the legs. Preferably, the effective magnetic permeability (u) of the core legs and core plates is greater than 25 and preferably greater than 100, and more preferably greater than 200 to contain the magnetic flux during operation. Lower effective permeability core structures may result in greater flux leakage which can couple to signal conductors in the substrate, semiconductor die, or system board creating noise problems.

Referring toFIGS.14A and14B, an alternate transformer structure160is shown having essentially the same PCB151in which the transformer windings (not shown), preferably self-aligned windings described in the Self-Aligned patent application, may be formed around a plurality of holes155to accommodate core legs such as the core legs154shown inFIG.12, and bottom core plates153on the bottom surface of the PCB151. The top core plates162may as shown include apertures166arranged to align with apertures155in the PCB when the core is in position. The transformer160may be fabricated by affixing the bottom core plates153to the bottom surface of the PCB151with a suitable adhesive such as epoxy. The top core plates162may be similarly affixed to the top surface of the PCB151with apertures166aligned with apertures155. A magnetically permeable fluid, such as a powder with or without a suitable binder material or other injectable material, preferably having a permeability of 10 or greater, may be injected through apertures166to fill the PCB apertures155and alternatively some or all of the core apertures166. After the apertures are filled with the magnetically permeable material, the core apertures may be sealed with an epoxy or other suitable material to prevent the magnetically permeable material from escaping. One or more plugs can be disposed in one or more of the apertures166, in which the one or more plugs form seals covering the respective one or more of the apertures166. Optionally, the PCB may be heated before the apertures are filled and sealed to ensure that the apertures are completely filled after the PCB is cooled. For example, the core plate153can be a ferrite core plate, and the core plate162can be a ferrite core plate having one or more apertures that is/are filled with one or more plugs.

The transformer structure160ofFIGS.14A and14Bmay be particularly well suited to low voltage and high frequency applications such as the POL circuits discussed above. Using a material that may be injected as a powder or fluid into the apertures in the PCB overcomes the mechanical tolerances of conventional planar magnetic core structures where small solid core legs have to fit within small PCB apertures. By replacing small solid magnetic core legs with magnetic powder or fluid, PCB apertures can be filled with a permeable medium providing greater PCB aperture utilization and converter efficiency.

Additionally, as mentioned above, the output circuit may be covered with a conductive covering, preferably connected to a common terminal, to provide additional shielding.

C. Noise Management

The POL modules110-1,110-2, and preferably the driver circuits also, may use zero-current switching and/or zero-voltage switching to minimize the slew rate of voltages and currents in and around the semiconductor package100and system board. The power converter topologies shown inFIGS.6,7, and9may preferably be based on the Sine Amplitude Converter (“SAC”) topology described in the SAC patent or on the clamped capacitor resonant topology described in the CSAC patent application. The SAC topology is preferred for the sinusoidal current and voltage waveforms and zero-current switching (“ZCS”) and zero-voltage switching (“ZVS”) and the ability to constrain the slew rates of voltages and currents in the converter. For example, the slew rates may be limited to dV/dT≤Vpk/(Top*0.2) and dI/dT≤Ipk/(Top*0.2) in the output circuits shown inFIGS.6and7using the SAC topology. In contrast, multiphase buck regulators typically exhibit characteristic current slew rates an order of magnitude greater than those in the output circuits.

In one example, the POL modules110-1,110-2in the semiconductor package100may use a current multiplication factor K of 48 and an input voltage of 48 volts to supply 1 VDC at 100 A to the semiconductor die. Using a SAC topology operating at 1 MHz (Top=1 μS), the maximum voltage is 48V and the maximum current lin=100/48=2.1 Amps. Thus, the voltage and current slew rates for the output circuit may be limited to 240 V/μS and 10.4 A/μS.

D. Thermal Management

The semiconductor package100may include a lid103, preferably made of thermally conductive material such as aluminum, copper, or other metallic or non-metallic thermally conductive material as shown inFIG.10. The lid as shown may have a stepped lower surface to mate or accommodate the difference in height between the relatively short semiconductor die101and the relatively tall POL modules110-1,110-2. Lower surfaces103A of lid103may mate with the top surfaces of the POL modules110-1,110-2and lower surface103B may mate with the top surface of the semiconductor die101. Referring to the side view of the semiconductor package100inFIG.11, dotted arrows104,105and106show the direction of heat flow in the package. Heat generated by the semiconductor die101typically flows up through the lid as shown by arrow106. Other proposed in-package power solutions rely on removal of the heat generated in the regulator circuits through the substrate, thus heating the substrate and the semiconductor die. However, the POL modules110-1,110-2, as shown provide thermally conductive conduits between the substrate and the lid, facilitating removal of heat generated by the output circuits directly through the lid and further provide a path for heat flow from the die101through the substrate102and up through the POL modules110-1,110-2as shown by arrows105and104. As a result, the package100provides thermally enhanced operation over other solutions.

III. Semiconductor Package with Bottom-Mounted Integrated POL Module

Referring toFIGS.15A,15B,16A,16B,17, and20, a second semiconductor package300is shown in bottom and top isometric exploded, top and bottom isometric assembled, and side views, respectively. Like the package100described above (FIGS.1-3,10,11), the second semiconductor package300includes a multilayer substrate302and a large semiconductor die301, such as an ASIC, CPU, or GPU, mounted on a top surface302A of the substrate302and also includes a POL module310. However, as shown inFIGS.15A,15B,16A,16B, and17, the POL module310may be mounted on the bottom surface302B of the substrate302beneath the die301in semiconductor package300. AlthoughFIGS.15A,15B,16A,16B, and17show a single large POL module310, a plurality of smaller POL modules may be used in place of the single large module shown.

Preferably, the POL module310(or POL modules) may occupy substantially all of the area beneath the semiconductor die301in the same, or a very similar, footprint allowing the remaining area, i.e. outside of the projection of the semiconductor die footprint, on the bottom surface, to be used for making connections between the substrate302and a system board. For example, the POL module310may preferably be smaller than, and fit completely within the footprint of, the die301as shown in the side view ofFIG.17. Note the difference304between the edge of the die301(on the top surface302A of the substrate) and the edge of the POL module310on the bottom302B of the substrate, which appears inFIG.17as symmetrical overhang on the left and right sides of the POL module. Although the POL module is shown slightly smaller than the die, it may be the same size as or slightly larger than the die, provided sufficient area remains for making connections between the die and the system board.

As shown inFIGS.15-17, the POL module310may be preferably packaged as a leadless module, such as described in the Panel Mold application, having electrical connections for surface mount soldering to respective conductive pads on the substrate302. For example, conductive terminations, e.g. terminations315, may be provided along two or more sides of the POL module310for surface mount soldering to conductive pads305on the bottom302B of the substrate302. Additionally, conductive terminations, e.g. terminations325A may be arranged along the top surface310A of the POL module310for surface mount soldering to conductive pads305on the bottom302B of the substrate302. A pair of the conductive terminations, preferably located centrally and near an edge of the POL module310may be provided for making AC power connections, e.g. terminals326A shown inFIG.15Balong a centerline and close to one edge of the POL module310. Conductive terminations for the relatively low power bias and control signals may be provided along an edge of the module, e.g. terminals317are shown formed in an edge of the POL module310inFIG.15B.

Preferably the conductive pads305on the bottom surface302B may be electrically and thermally connected to conductive pads307on the top surface302A of the substrate302(e.g. using conductive vias between the substrate layers (not shown)), which connect with power terminals303located on the bottom surface301B of die301. As shown inFIGS.15A,15B, and17, direct vertical alignment may be established between power terminals303, conductive pads307, conductive pads305, and conductive terminations315providing the shortest electrical and thermal path between the POL module310and the die301. Additionally, the power terminals303, conductive pads307, conductive pads305, and conductive terminations315may be spatially arranged to allow signal connections to be routed between them on the inner and optionally outer layers of the substrate302. For example, the power connections including terminals303, pads307, vias (not shown), pads305, and terminations315and325A are shown spaced apart and generally arranged in columns, e.g. five columns are shown inFIGS.15A,15B. As shown inFIGS.15B and16B, the POL module310may include conductive coverings316A,316B extending over the top310A and bottom310B surfaces of the POL module310, which as discussed above may enhance the thermal and noise performance of the POL module310and help contain the magnetic fields in the transformer cores.

Referring toFIG.16B, the POL module310may optionally include conductive terminals,325B,326B on the bottom surface310B preferably aligned with the respective conductive terminations325A,326A on the top surface310A of the POL module310. Such through-module terminations, described in the Panel Mold application, may enhance the thermal conductivity, providing heat conductors through the POL module310. As described in the Panel Mold application, a conduit (an example of which, conduit265, is shown inFIG.11of the Panel Mold application) may expose conductive features to provide thermal and electrical connections between a substrate and the top and/or bottom conductive layers. The conductive terminations325B,326B may be used to engage with suitable terminations on the system board, directly or through a socket, to provide electrical connections and or allow heat to be conducted away through the system board as described below in connection withFIG.20A.

Remote Gate Driver

Referring toFIG.19, another power converter system is shown including a driver490B, the semiconductor package300including the die301and a POL circuit331which may include the output transformer440and secondary switches451-454of the POL circuit431(FIG.6). Preferably, the driver490B may include transformer driver circuitry (481,FIG.9) including switch control circuitry (e.g.425,FIG.9), power regulator circuitry (482,FIG.9), and supervisory circuitry (483,FIG.9) as described above and may be electrically connected to the semiconductor package300via connections formed by a system PCB (e.g. system board11A or11B inFIGS.20A,20B) on which the driver490B and semiconductor package300may be mounted. Preferably, the switch driver (460:FIG.6) which is shown as part of the POL circuits described above (431:FIG.6) may be incorporated into the driver490B (FIG.19) to further reduce the size of the POL module310.

Although counterintuitive because of the high switching frequency and the parasitic inductances introduced by the system board, the package of the driver490B, the POL module package, and the semiconductor package300, the switch driver may incorporate resonant gate driver techniques (See, e.g. Controller patent: Col. 13, ln 56-Col. 15, ln 24;FIGS.8,9) to use the inductances introduced by the connections between the separated driver490B and the POL module310in semiconductor package300as some or all of the inductance required to resonantly charge and discharge the gate capacitances of the secondary switches in the rectification circuit of the POL module310. Preferably additional inductance may be added in series with gate runs of the gate drive circuit using discrete, e.g. chip, inductors, to trim the circuit to the desired resonant frequency. For example, a power converter of the type shown inFIG.19configured to operate at 2 MHz with 250 nS half-cycles may require gate-voltage rise and fall times of 60-80 nS. Secondary switches configured to deliver 350 to 400 Amperes to the load may require 60 nC of gate charge to turn ON or OFF, representing approximately 12 nF of gate capacitance on each terminal446,449. The total inductance in the driver circuit between gate drivers in the driver490B and the secondary switches in the POL module310therefore should be limited to 7.6 to 13.5 nH. Allowing for 1 nH of package inductance for each of the driver and POL module and discrete inductance of approximately 3 nH, the maximum distribution inductance budget for the gate runs is between 2.6 and 8.5 nH. Design rules may be provided to keep the gate runs within the allocated inductance budget, e.g. limiting the length and width of the conductive traces, requiring a ground plane in an adjacent layer separated by an acceptable dielectric thickness.

As described above, the controller may detect and adjust for small timing errors produced by differences in the parasitic inductances in the AC power bus410and in the gate drive signal bus415. Preferably, more than 50%, or 75%, or most preferably more than 90% of the energy stored in the gate capacitances of the secondary switches in the POL module310may be recycled using at least in part the inductances introduced by the wiring between driver and POL module.

As shown inFIG.19, the control outputs426,429of driver490B (e.g. either bias and control or gate driver outputs) may be connected to a signal bus415on the system board which may in turn be connected to terminals465,466on the substrate302of the package300and carried through the substrate302to input terminals449,446, respectively. Similarly, a communication bus497as described above in connection withFIG.9may provide communication between the semiconductor package300, e.g. with the die301, and supervisory circuitry in the driver490B.

The AC power connections410between the driver490B (outputs427,428) and the POL module310(AC Inputs447,448) may be provided in part by the substrate302in the manner described above in connection withFIG.4using suitable conductor free zones around the AC connections formed in the substrate. Providing connections between the POL module310and the driver490B through the substrate302may require routing the AC power laterally in or on the substrate in turn requiring elimination of any conductive features in a volume surrounding the AC power conductors, e.g. in a space radially around the conductors including a number of adjacent layers above and below the layer in which the AC power connections are made. Alternatively, the AC power connections410may be established between the system board (e.g. system board11A,FIG.20A) and the POL module310directly, e.g. using a socket15with suitable conductive terminations16B to engage with terminations326B on the bottom surface310B of the POL module310.

Alternatively, the AC power connections410between the system board and the POL module310may be formed using a wire harness18including a connector body configured to engage with AC power pins327preferably protruding from the bottom surface310B of the POL module as shown inFIG.18. The AC power pins327may be configured to be inserted into, engage with, and soldered to conductive features, e.g. plated holes, formed in the POL module310. For example, a conduit, such as the feature265shown inFIG.11of the Panel Mold application, may be appropriately shaped and sized to provide a conductive receptacle for a conductive pin.

Underside Thermal Management

Referring to the side view ofFIG.20A, the package300may be assembled onto a surface of system board11A using a socket15which may include contacts16for establishing electrical connections to the bottom surface302B of the substrate. Heat may be conducted from the POL module310up through the substrate302, e.g. through conductive features,305,307and the connections there between, up through, and out the top of, the die301, into a heat sink or lid (not shown) as represented by arrow21inFIG.20A. Optionally, heat may be conducted away from the POL module through the system board11A as represented by arrows23inFIG.20A.

Referring to the side view ofFIG.20B, the package300may be assembled onto a surface of system board11B using a low profile socket15B having an aperture sized to accommodate the POL module310and contacts16for establishing electrical connections to the bottom surface302B of the substrate. However, the system board11B may include an aperture17sized to accommodate the POL module310, providing a lower profile mounting alternative. In the embodiment ofFIG.20B, heat may be removed from the POL module310through the aperture17as represented by arrow22, e.g. using forced air convection, a heat sink, or a cold plate (not shown).

A number of embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, a single resonant capacitor may be used instead of the two resonant capacitors shown in the symmetrical balanced circuit ofFIG.5andFIG.6. A center-tapped secondary circuit may be used in place of the full-bridge circuit shown. Although full-bridge driver circuits are shown inFIGS.5,6, and9, a half-bridge primary circuit may be used to drive the power transformer. Although converter topologies having one, and two POL circuits have been shown, it will be appreciated that a larger number of POL circuits may be used. The POL outputs may be connected in parallel as shown to supply higher current loads, or independently for multiple loads. The POL circuits may be deployed within the semiconductor package or at locations near, or adjacent to the semiconductor package or other loads. The magnetically permeable fluid injected into the apertures155of the PCB151can include a powder with or without a curable medium. There can be two or more semiconductor chips mounted on the substrate102, in which the semiconductor chips are all powered by the POL modules110. The magnetically permeable fluid can be a liquid material.

Accordingly, other embodiments are within the scope of the following claims.