Patent ID: 12251931

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Embodiments of the present disclosure are described below with reference to the accompanying drawings. The drawings are just for descriptive purposes. The embodiments described below do not unduly limit the scope of the present disclosure described in the claims. Also, not all of the configurations described below are necessarily essential components of the present disclosure.

1. Configuration of Liquid Ejecting Apparatus

FIG.1is a drawing illustrating a schematic configuration of a liquid ejecting apparatus1according to the present embodiment. The liquid ejecting apparatus1of the present embodiment is, for example, an ink jet printer that ejects ink, which is an example of a liquid, according to image data supplied from an external host computer and thereby forms an image corresponding to the image data on a medium P such as paper. Here, the liquid ejecting apparatus1is not limited to an ink jet printer, but may also be, for example, a color material ejecting apparatus used to manufacture a color filter for a liquid crystal display, an electrode material ejecting apparatus used to form electrodes for an organic electroluminescent (EL) display and a surface-emitting display, or a bioorganic material ejecting apparatus used to manufacture a biochip.

As illustrated inFIG.1, the liquid ejecting apparatus1includes a head unit2, a moving mechanism3, and a conveying mechanism4. InFIG.1, some components of the liquid ejecting apparatus1, such as a housing and a cover, are omitted.

The head unit2includes an ejection head20and a carriage24. The carriage24is configured to hold a predetermined number of ink cartridges22that store inks to be ejected from the ejection head20. Also, the ejection head20includes multiple nozzles described later. The nozzles are attached to the carriage24so as to face the medium P. The ejection head20ejects a predetermined amount of ink from each nozzle at a timing determined by various control signals supplied via a cable190such as a flexible flat cable.

The moving mechanism3moves the carriage24of the head unit2back and forth along a main-scanning direction. The moving mechanism3includes a carriage motor31, a carriage guide shaft32, a timing belt33, and a linear encoder90. The carriage guide shaft32is fixed at both ends to the housing of the liquid ejecting apparatus1and supports the carriage24such that the carriage24is movable back and forth. The timing belt33extends approximately parallel to the carriage guide shaft32, and a part of the timing belt33is fixed to the carriage24. The carriage motor31supplies a driving force to the timing belt33. With this configuration, when the carriage motor31rotates the timing belt33forward and backward, the carriage24fixed to the timing belt33is guided by the carriage guide shaft32to move back and forth along the main-scanning direction. That is, the moving mechanism3moves the carriage24back and forth along the main-scanning direction.

Also, the linear encoder90detects the scanning position of the carriage24in the main-scanning direction and outputs the detected scanning position as a detection signal. Based on information on the scanning position of the carriage24output by the linear encoder90, the liquid ejecting apparatus1controls the output of the carriage motor31and thereby controls the scanning position of the ejection head20along the main-scanning direction.

The conveying mechanism4conveys the medium P along the sub-scanning direction that intersects the main-scanning direction along which the carriage24moves back and forth. The conveying mechanism4includes a conveying motor41, a conveyor roller42, and a platen43. The conveying motor41supplies a driving force to the conveyor roller42. As a result, the conveyor roller42rotates. The rotation of the conveyor roller42conveys the medium P along the sub-scanning direction. While being conveyed, the medium P is supported by the platen43. That is, the platen43guides the medium P, which is being conveyed by the conveyor roller42, along the sub-scanning direction.

Also, as illustrated inFIG.1, the liquid ejecting apparatus1includes a capping part81, a wiping part82, and a flushing box83. The capping part81and the wiping part82are located at one end of the moving range of the carriage24and are provided at the home position from which the carriage24starts moving. The capping part81covers a nozzle forming surface of the ejection head20, and the wiping part82wipes the nozzle forming surface. On the other hand, the flushing box83is provided at another end of the platen43in the main-scanning direction, i.e., at an end that is located opposite the home position from which the carriage24starts moving. The flushing box83receives ink ejected from the ejection head20during a flushing operation. Here, the flushing operation indicates forcibly ejecting ink from the nozzles with no relation to image data to reduce the probability that a proper amount of ink cannot be ejected from the nozzles due to clogging of the nozzles, which results from thickening of ink near the nozzles, or entry of bubbles into the nozzles.

In the liquid ejecting apparatus1configured as described above, the medium P is conveyed in the sub-scanning direction while being supported by the platen43, and the carriage24moves back and forth along the main-scanning direction in synchronization with the timing of conveyance of the medium P. Then, in synchronization with the conveyance of the medium P and the movement of the carriage24, the ejection head20attached to the carriage24ejects ink. This configuration makes it possible to cause ink to land in desired positions on the medium P and thereby makes it possible to form a desired image on the medium P. In the descriptions below, the sub-scanning direction in which the medium P is conveyed may be referred to as a conveying direction.

2. Functional Configuration of Liquid Ejecting Apparatus

Next, a functional configuration of the liquid ejecting apparatus1is described.FIGS.2A and2Bare drawings illustrating a functional configuration of the liquid ejecting apparatus1. As illustrated inFIGS.2A and2B, the liquid ejecting apparatus1includes a control unit10and a head unit2. The control unit10and the head unit2are electrically connected to each other via the cable190.

The control unit10includes a control circuit100, a carriage motor driver35, a conveying motor driver45, and a voltage output circuit110.

The control circuit100is supplied with image data from a host computer provided outside of the liquid ejecting apparatus1. The control circuit100generates various control signals according to the supplied image data and outputs the control signals to components of the liquid ejecting apparatus1.

Specifically, the control circuit100determines the current scanning position of the head unit2based on a detection signal output by the linear encoder90. Then, the control circuit100generates control signals CTR1and CTR2according to the current scanning position of the head unit2. The control signal CTR1is supplied to the carriage motor driver35. The carriage motor driver35drives the carriage motor31according to the supplied control signal CTR1. Also, the control signal CTR2is supplied to the conveying motor driver45. The conveying motor driver45drives the conveying motor41according to the supplied control signal CTR2. Thus, the control circuit100controls the back-and-forth movement of the carriage24in the main-scanning direction and the conveyance of the medium P in the sub-scanning direction.

Also, the control circuit100generates a clock signal SCK, a print data signal SI, a latch signal LAT, a change signal CH, a base drive signal dA, and a detection control signal Lck based on image data supplied from the host computer and a detection signal output by the linear encoder90, and outputs the generated signals to the head unit2.

Furthermore, the control circuit100causes a maintenance unit80to perform a maintenance process for restoring the ink ejection state of the ejection unit600to normal. The maintenance unit80includes a cleaning mechanism810, a wiping mechanism820, and a flushing mechanism830. The cleaning mechanism810performs, as a maintenance process, a pumping process in which thickened ink, air bubbles, and so on accumulated inside of the ejection unit600are sucked out by a tube pump (not shown). The wiping mechanism820performs, as a maintenance process, a wiping process in which a foreign matter such as paper dust adhering to the vicinity of the nozzles of the ejection unit600is wiped off by the wiping part82. The flushing mechanism830performs a flushing operation for restoring the ink ejection state of the ejection unit600to normal.

The voltage output circuit110generates a voltage signal VHV with a potential Vh and outputs the voltage signal VHV to the head unit2. The voltage signal VHV is used, for example, as a power-supply voltage for components of the head unit2. The voltage signal VHV generated by the voltage output circuit110may also be used as a power-supply voltage for components of the control unit10. The voltage signal VHV is, for example, a direct-current voltage of 42 V. The voltage output circuit110may also be configured to generate, in addition to the voltage signal VHV, a direct-current voltage signal with a voltage value of, for example, 3.3 V or 7.5 V that is different from the voltage value of the voltage signal VHV and to supply the direct-current voltage signal to components included in the control unit10and the head unit2.

The head unit2includes a drive circuit50, a reference voltage output circuit52, a leakage current detection circuit70, and an ejection head20.

The leakage current detection circuit70receives the voltage signal VHV output by the voltage output circuit110and the detection control signal Lck output by the control circuit100. The leakage current detection circuit70outputs the voltage signal VHV passing through the leakage current detection circuit70to the drive circuit50as a voltage signal Vamp. That is, the leakage current detection circuit70is provided in a transmission path through which the voltage signal VHV output by the voltage output circuit110is transmitted to the drive circuit50as the voltage signal Vamp.

Also, the leakage current detection circuit70detects a leakage current, which may be generated in the drive circuit50, based on the variation of the voltage value of the voltage signal Vamp passing through the leakage current detection circuit70. Then, the leakage current detection circuit70generates a detection voltage Vleak with a voltage value corresponding to the detected leakage current and outputs the detection voltage Vleak to the control circuit100. The detection control signal Lck input to the leakage current detection circuit70indicates whether it is necessary to detect a leakage current that may be generated in the drive circuit50. That is, the leakage current detection circuit70determines whether to detect a leakage current that may be generated in the drive circuit50based on the detection control signal Lck input from the control circuit100.

The drive circuit50receives the digital base drive signal dA output by the control circuit100and the voltage signal Vamp output by the leakage current detection circuit70. Then, the drive circuit50converts the received digital base drive signal dA into an analog signal and generates a drive signal COM by amplifying the analog signal according to the voltage signal VHV. Then, the drive circuit50outputs the generated drive signal COM to the ejection head20. Here, the base drive signal dA defines the waveform of the drive signal COM and may be an analog signal.

The reference voltage output circuit52generates a reference voltage signal VBS with a constant voltage value of, for example, 5.5 V or 6 V, and supplies the reference voltage signal VBS to the ejection head20. The reference voltage signal VBS output by the reference voltage output circuit52serves as a reference potential for driving a piezoelectric element60described later. Alternatively, the reference voltage signal VBS may have a ground potential.

The ejection head20includes a drive signal selection circuit200and n ejection units600. The drive signal selection circuit200includes a selection control circuit210and n selection circuits230corresponding to the n ejection units600.

The selection control circuit210receives the clock signal SCK, the print data signal SI, the latch signal LAT, and the change signal CH output by the control circuit100. The selection control circuit210generates selection signals S corresponding to the n selection circuits230based on the clock signal SCK, the print data signal SI, the latch signal LAT, and the change signal CH and outputs the selection signals S to the corresponding selection circuits230.

Each of the n selection circuits230receives the drive signal COM and the corresponding selection signals S. The selection circuit230generates a drive signal VOUT by selecting or deselecting signal waveforms in the drive signal COM based on the received selection signals S. Then, the selection circuit230outputs the generated drive signal VOUT to the corresponding ejection unit600.

Each of the n ejection units600includes a piezoelectric element60. The drive signal VOUT output by the corresponding selection circuit230is supplied to one end of the piezoelectric element60. Also, the reference voltage signal VBS output by the reference voltage output circuit52is supplied to another end of the piezoelectric element60. The piezoelectric element60is driven according to the potential difference between the drive signal VOUT supplied to one end and the reference voltage signal VBS supplied to the other end. An amount of ink corresponding to the driving of the piezoelectric element60is ejected from the corresponding ejection unit600.

3. Configurations and Operations of Ejection Head

Next, configurations and operations of the ejection head20are described. First, a configuration of the ejection unit600of the ejection head20is described.FIG.3is a drawing illustrating a schematic configuration of the ejection unit600. In addition to the ejection unit600,FIG.3illustrates a reservoir641and a supply port661.

As illustrated inFIG.3, the ejection unit600includes the piezoelectric element60, a vibration plate621, a cavity631, and a nozzle plate632.

The piezoelectric element60includes a piezoelectric body601and electrodes611and612. In the piezoelectric element60, the electrodes611and612are disposed to sandwich the piezoelectric body601. The piezoelectric element60configured as described above is driven such that the central portion of the piezoelectric body601is displaced in the vertical direction according to the potential difference between a voltage supplied to the electrode611and a voltage supplied to the electrode612. In the piezoelectric element60of the present embodiment, the drive signal VOUT based on the drive signal COM is supplied to the electrode611and the reference voltage signal VBS with a constant potential is supplied to the electrode612. That is, the piezoelectric element60is driven such that the central portion of the piezoelectric element60is displaced in the vertical direction as a result of a variation of the voltage value of the drive signal VOUT supplied to the electrode611.

The vibration plate621is located below the piezoelectric element60inFIG.3. In other words, the piezoelectric element60is formed on the upper surface of the vibration plate621inFIG.3. The vibration plate621is deformed in the vertical direction when the piezoelectric element60is driven and displaced in the vertical direction.

The cavity631is located below the vibration plate621inFIG.3. The cavity631communicates with the reservoir641that is shared by multiple ejection units600. Also, the reservoir641communicates with the supply port661through which ink stored in the ink cartridge22is supplied. Accordingly, ink stored in the ink cartridge22is supplied into the cavity631via the supply port661and the reservoir641. As a result, the cavity631is filled with the ink stored in the ink cartridge22. The internal volume of the cavity631changes as the vibration plate621is displaced in the vertical direction. That is, the vibration plate621functions as a diaphragm that changes the internal volume of the cavity631, and the cavity631functions as a pressure chamber the internal pressure of which changes when the vibration plate621is displaced.

A nozzle651is formed in the nozzle plate632. That is, the ejection unit600includes the nozzle651. The nozzle651is an opening formed in the nozzle plate632and communicates with the cavity631. When the internal volume of the cavity631changes, the ink filling the cavity631is ejected from the nozzle651.

In the ejection unit600configured as described above, when the piezoelectric element60is driven to warp upward, the vibration plate621is displaced upward. This causes the internal volume of the cavity631to increase, and as a result, the ink stored in the reservoir641is drawn into the cavity631. In contrast, when the piezoelectric element60is driven to warp downward, the vibration plate621is displaced downward. This causes the internal volume of the cavity631to decrease, and as a result, an amount of ink corresponding to the decrease in the internal volume of the cavity631is ejected from the nozzle651.

Here, the configuration of the piezoelectric element60is not limited to the configuration illustrated inFIG.3, as long as the piezoelectric element60is configured to be driven by the drive signal VOUT corresponding to the drive signal COM and to be able to eject ink from the nozzle651.

Next, a configuration and an operation of the drive signal selection circuit200of the ejection head20are described. As described above, the drive signal selection circuit200generates and outputs the drive signal VOUT by selecting or deselecting signal waveforms in the drive signal COM based on the clock signal SCK, the print data signal SI, the latch signal LAT, and the change signal CH. Therefore, before describing the functional configuration of the drive signal selection circuit200, an example of waveforms of the drive signal COM to be input to the drive signal selection circuit200is described.

FIG.4is a drawing illustrating an example of waveforms of the drive signal COM. As illustrated inFIG.4, the drive signal COM includes a trapezoidal waveform Adp in a period T1from the rise of the latch signal LAT to the rise of the change signal CH, a trapezoidal waveform Bdp in a period T2from the rise of the change signal CH to the next rise of the change signal CH, and a trapezoidal waveform Cdp in a period T3from the rise of the change signal CH to the rise of the latch signal LAT. The trapezoidal waveform Adp, when supplied to the piezoelectric element60, drives the piezoelectric element60to eject a predetermined amount of ink from the ejection unit600corresponding to the piezoelectric element60. The trapezoidal waveform Bdp, when supplied to the piezoelectric element60, drives the piezoelectric element60to eject an amount of ink less than the predetermined amount from the ejection unit600corresponding to the piezoelectric element60. The trapezoidal waveform Cdp, when supplied to the piezoelectric element60, drives the piezoelectric element60to such an extent that ink is not ejected from the ejection unit600corresponding to the piezoelectric element60. Here, when the trapezoidal waveform Cdp is supplied to the piezoelectric element60, the piezoelectric element60vibrates ink near the nozzle opening of the corresponding ejection unit600. This reduces the probability that the viscosity of ink near the nozzle opening increases.

Here, at the start timing and the end timing, all of the trapezoidal waveforms Adp, Bdp, and Cdp have the same voltage Vc and the same shape. That is, each of the trapezoidal waveforms Adp, Bdp, and Cdp starts at the voltage Vc and ends at the voltage Vc.

In the descriptions below, a predetermined amount of ink ejected from the ejection unit600corresponding to the piezoelectric element60to which the trapezoidal waveform Adp is supplied may be referred to as a medium amount, and an amount of ink that is less than the predetermined amount and ejected from the ejection unit600corresponding to the piezoelectric element60to which the trapezoidal waveform Bdp is supplied may be referred to as a small amount. Also, an operation performed when the trapezoidal waveform Cdp is supplied to the piezoelectric element60to vibrate ink near the nozzle opening of the ejection unit600corresponding to the piezoelectric element60and thereby prevent an increase in ink viscosity may be referred to as micro vibration. Here, the waveforms of the drive signal COM illustrated inFIG.4are non-limiting examples, and various combinations of waveforms may be used depending on, for example, the property of ink to be ejected and/or the material of the medium P on which the ink lands.

The ejection head20controls the amount of ink to be ejected by selecting or deselecting the trapezoidal waveforms Adp, Bdp, and Cdp in a cycle Ta including the periods T1, T2, and T3. As a result, the size of a dot formed on the medium P in the cycle Ta is controlled. The cycle Ta including the periods T1, T2, and T3corresponds to a dot formation cycle in which a dot with a predetermined size is formed on the medium P.

Next, a configuration and an operation of the drive signal selection circuit200, which generates the drive signal VOUT by selecting or deselecting signal waveforms included in the drive signal COM, are described.FIG.5is a drawing illustrating a configuration of the drive signal selection circuit200. As illustrated inFIG.5, the drive signal selection circuit200includes the selection control circuit210and the n selection circuits230.

The selection control circuit210receives the clock signal SCK, the print data signal SI, the latch signal LAT, and the change signal CH. The selection control circuit210includes a combination of a shift register (S/R)212, a latch circuit214, and a decoder216for each of the n ejection units600. That is, the drive signal selection circuit200includes n shift registers212, n latch circuits214, and n decoders216.

The print data signal SI is input to the selection control circuit210in synchronization with the clock signal SCK. Also, the print data signal SI includes, for the respective n ejection units600, serially-arranged multiple sets of two-bit print data [SIH, SIL] each of which is used to select one of “large dot LD”, “medium dot MD”, “small dot SD”, and “non-recording ND”. In other words, the print data signal SI is a 2n-bit serial signal. The multiple sets of print data [SIH, SIL] included in the print data signal SI are stored in the n shift registers212corresponding to the n ejection units600. Specifically, the n shift registers212corresponding to the n ejection units600are coupled to each other in a cascade, and serially-input print data signal SI is sequentially transferred to the shift registers212in the subsequent stages according to the clock signal SCK. Then, when the multiple sets of print data [SIH, SIL] are stored in the corresponding shift registers212, the clock signal SCK stops. In other words, when the supply of the clock signal SCK stops, the multiple sets of print data [SIH, SIL] included in the print data signal SI are stored in the corresponding shift registers212. InFIG.5, to distinguish the n shift registers212, stage numbers “first stage”, “second stage”, . . . , and “nth stage” are sequentially assigned to the n shift registers212from the upstream in the flow of the print data signal SI.

The n latch circuits214simultaneously latch the multiple sets of print data [SIH, SIL] stored in the corresponding shift registers212at the rise of the latch signal LAT. The multiple sets of print data [SIH, SIL] latched by the latch circuits214are input to the corresponding decoders216.FIG.6is a table showing an example of information decoded by the decoder216. The decoder216outputs, in each of the periods T1, T2, and T3, a selection signal S with a logic level specified by input print data [SIH, SIL]. For example, when print data [SIH, SIL]=[1, 0] is input to the decoder216, the decoder216outputs selection signals S with logic levels H, L, and L in the corresponding periods T1, T2, and T3.

The selection signal S output by the decoder216is input to the selection circuit230. The selection circuit230is provided for each of the n ejection units600. That is, the drive signal selection circuit200includes n selection circuits230corresponding to the n ejection units600.FIG.7is a drawing illustrating a configuration of the selection circuit230corresponding to one ejection unit600. As illustrated inFIG.7, the selection circuit230includes an inverter232, which is a NOT circuit, and a transfer gate234.

The selection signal S is input to a positive control terminal of the transfer gate234not marked with a circle and is also input to a negative control terminal of the transfer gate234marked with a circle after the logic level is inverted by the inverter232. Also, the drive signal COM is supplied to the input terminal of the transfer gate234. The transfer gate234electrically connects the input terminal and the output terminal of the transfer gate234to each other when a high-level selection signal S is input, and electrically disconnects the input terminal and the output terminal from each other when a low-level selection signal S is input. That is, the transfer gate234outputs a signal waveform included in the drive signal COM from the output terminal when the logic level of the selection signal S is high and does not output a signal waveform included in the drive signal COM from the output terminal when the logic level of the selection signal S is low.

Then, the drive signal selection circuit200outputs a signal output to the output terminal of the transfer gate234of the selection circuit230as the drive signal VOUT.

Here, an operation of the drive signal selection circuit200is described with reference toFIG.8.FIG.8is a timing chart for describing an operation of the drive signal selection circuit200. The print data signal SI is input to the selection control circuit210as a serial signal synchronized with the clock signal SCK. Then, the print data signal SI is sequentially transferred through the n shift registers212corresponding to the n ejection units600in synchronization with the clock signal SCK. When the input of the clock signal SCK is stopped, sets of print data [SIH, SIL] corresponding to the n ejection units600are stored in the shift registers212. Here, the print data signal SI is input in the order corresponding to the order of the ejection units600for the nth stage, . . . , 2nd stage, and 1st stage shift registers212.

Then, when the latch signal LAT rises, the latch circuits214simultaneously latch the sets of print data [SIH, SIL] stored in the shift registers212. Here, LT1, LT2, . . . , and LTn inFIG.8indicate the sets of print data [SIH, SIL] latched by the latch circuits214corresponding to the 1st, 2nd, . . . , and nth stage shift registers212.

The decoder216outputs the selection signals S with the logic levels as shown inFIG.6in the respective periods T1, T2, and T3according to a dot size specified by the latched print data [SIH, SIL]. Then, the selection circuit230generates the drive signal VOUT by selecting or deselecting signal waveforms in the drive signal COM according to the logic levels of the selection signals S output by the decoder216.

Specifically, when print data [SIH, SIL]=[1, 1] is input to the decoder216, the decoder216sets the logic levels of the selection signals S in the periods T1, T2, and T3to H, H, and L, respectively. In this case, the selection circuit230selects the trapezoidal waveform Adp in the period T1, selects the trapezoidal waveform Bdp in the period T2, and does not select the trapezoidal waveform Cdp in the period T3. As a result, the drive signal selection circuit200outputs the drive signal VOUT corresponding to “large dot LD”.

When the drive signal VOUT corresponding to “large dot LD” and output by the drive signal selection circuit200is supplied to the piezoelectric element60of the ejection unit600, the ejection unit600ejects a medium amount of ink in the period T1, ejects a small amount of ink in the period T2, and does not eject ink in the period T3. When the medium amount of ink and the small amount of ink ejected from the ejection unit600land on the medium P and join together, “large dot LD” is formed on the medium P.

Also, when print data [SIH, SIL]=[1, 0] is input to the decoder216, the decoder216sets the logic levels of the selection signals S in the periods T1, T2, and T3to H, L, and L, respectively. In this case, the selection circuit230selects the trapezoidal waveform Adp in the period T1, does not select the trapezoidal waveform Bdp in the period T2, and does not select the trapezoidal waveform Cdp in the period T3. As a result, the drive signal selection circuit200outputs the drive signal VOUT corresponding to “medium dot MD”.

When the drive signal VOUT corresponding to “medium dot MD” and output by the drive signal selection circuit200is supplied to the piezoelectric element60of the ejection unit600, the ejection unit600ejects a medium amount of ink in the period T1, does not eject ink in the period T2, and does not eject ink in the period T3. When the medium amount of ink ejected from the ejection unit600lands on the medium P, “medium dot MD” is formed on the medium P.

When print data [SIH, SIL]=[0, 1] is input to the decoder216, the decoder216sets the logic levels of the selection signals S in the periods T1, T2, and T3to L, H, and L, respectively. In this case, the selection circuit230does not select the trapezoidal waveform Adp in the period T1, selects the trapezoidal waveform Bdp in the period T2, and does not select the trapezoidal waveform Cdp in the period T3. As a result, the drive signal selection circuit200outputs the drive signal VOUT corresponding to “small dot SD”.

When the drive signal VOUT corresponding to “small dot SD” and output by the drive signal selection circuit200is supplied to the piezoelectric element60of the ejection unit600, the ejection unit600does not eject ink in the period T1, ejects a small amount of ink in the period T2, and does not eject ink in the period T3. When the small amount of ink ejected from the ejection unit600lands on the medium P, “small dot SD” is formed on the medium P.

When print data [SIH, SIL]=[0, 0] is input to the decoder216, the decoder216sets the logic levels of the selection signals S in the periods T1, T2, and T3to L, L, and H, respectively. In this case, the selection circuit230does not select the trapezoidal waveform Adp in the period T1, does not select the trapezoidal waveform Bdp in the period T2, and selects the trapezoidal waveform Cdp in the period T3. As a result, the drive signal selection circuit200outputs the drive signal VOUT corresponding to “non-recording ND”.

When the drive signal VOUT corresponding to “non-recording ND” and output by the drive signal selection circuit200is supplied to the piezoelectric element60of the ejection unit600, the ejection unit600does not eject ink in the period T1, does not eject ink in the period T2, and does not eject ink in the period T3. Accordingly, no ink is ejected from the ejection unit600, resulting in “non-recording ND” in which no dot is formed on the medium P.

Here, when print data [SIH, SIL]=[0, 0] is input to the decoder216, the corresponding selection circuit230does not select the trapezoidal waveform Adp in the period T1, does not select the trapezoidal waveform Bdp in the period T2, and selects the trapezoidal waveform Cdp in the period T3. That is, the selection circuit230outputs the drive signal VOUT including the trapezoidal waveform Cdp. As a result, micro vibration BSD is performed to reduce the probability that the viscosity of ink near the nozzle opening of the corresponding ejection unit600increases.

As described above, in the liquid ejecting apparatus1of the present embodiment, the ejection head20includes the piezoelectric element60as an example of a driven element that is driven by the drive signal COM and ejects ink, which is an example of a liquid, when the piezoelectric element60is driven.

4. Configuration and Operation of Drive Circuit

Next, a configuration and an operation of the drive circuit50are described.FIG.9is a drawing illustrating an example of a configuration of the drive circuit50. As illustrated inFIG.9, the drive circuit50includes an amplification control circuit500and an amplifier circuit510.

The amplification control circuit500includes a memory501, a latch circuit502, an adder503, a latch circuit504, a digital-to-analog (D/A) converter505, and a drive circuit506. The amplification control circuit500receives voltage variation data dDATA, a latch signal dLAT, and a clock signal dCK each of which is output as the base drive signal dA by the control circuit100.

The memory501stores voltage variation information Dv included in the voltage variation data dDATA that is output as the base drive signal dA by the control circuit100. The latch circuit502latches the voltage variation information Dv stored in the memory501at the rise of the latch signal dLAT that is output as the base drive signal dA by the control circuit100. Then, the latch circuit502outputs the latched voltage variation information Dv to the adder503. The adder503receives the voltage variation information Dv latched by the latch circuit502and an output of the latch circuit504described later. The adder503calculates and retains summed voltage variation information that indicates the sum of the voltage variation information Dv latched by the latch circuit502and the output of the latch circuit504.

The latch circuit504latches, at the rise of the clock signal dCK, the summed voltage variation information calculated and retained by the adder503. Then, the latch circuit504outputs the latched summed voltage variation information to the adder503and the D/A converter505. That is, the adder503newly calculates and retains summed voltage variation information by adding the voltage variation information Dv latched by the latch circuit502to the summed voltage variation information latched by the latch circuit504.

The D/A converter505converts the summed voltage variation information output by the latch circuit504into an analog signal and outputs the analog signal to the drive circuit506as a drive waveform signal WS. A signal obtained by amplifying the drive waveform signal WS corresponds to the drive signal COM. The drive circuit506generates amplification control signals Hdr and Ldr according to the drive waveform signal WS input from the D/A converter505and a feedback signal FB fed back from the amplifier circuit510described later, and outputs the amplification control signals Hdr and Ldr to the amplifier circuit510.

Here, an example of an operation of the amplification control circuit500is described.FIG.10is a timing chart for describing an example of an operation of the amplification control circuit500. As illustrated inFIG.10, at time t0, the control circuit100generates the voltage variation data dDATA including voltage variation information Dv1for changing the voltage value by a voltage Δv1and outputs the voltage variation data dDATA to the memory501as the base drive signal dA. As a result, the voltage variation information Dv1is stored in the memory501.

Then, at time t1, the control circuit100sets the logic level of the latch signal dLAT, which is to be output as the base drive signal dA, to high. As a result, the voltage variation information Dv1stored in the memory501is latched by the latch circuit502. Next, at time t3, the control circuit100outputs the voltage variation data dDATA, which includes voltage variation information Dv0for keeping the voltage value constant, to the memory501as the base drive signal dA. As a result, the voltage variation information Dv0is stored in the memory501in place of the voltage variation information Dv1.

The voltage variation information Dv1latched by the latch circuit502is input to the adder503. The adder503adds the voltage variation information Dv1latched by the latch circuit502to the summed voltage variation information output by the latch circuit504and retains the result of addition as new summed voltage variation information.

Also, the control circuit100generates the clock signal dCK that becomes high (H level) at an interval AT and outputs the clock signal dCK to the latch circuit504as the base drive signal dA. Then, when a H-level clock signal dCK is input to the latch circuit504at each of time t2, time t4, and time t5, the latch circuit504latches summed voltage variation information the voltage value of which has been increased by the voltage ΔV1and outputs the summed voltage variation information to the D/A converter505. In response, at each of time t2, time t4, and time t5, the D/A converter505generates and outputs the drive waveform signal WS the voltage value of which increases by the voltage ΔV1.

At subsequent time t6, the control circuit100sets the logic level of the latch signal dLAT, which is to be output as the base drive signal dA, to high. As a result, the voltage variation information Dv0for keeping the voltage value stored in the memory501constant is latched by the latch circuit502. Also, at subsequent time t8, the control circuit100generates the voltage variation data dDATA including voltage variation information Dv2for changing the voltage value by a voltage −ΔV2and outputs the voltage variation information Dv2to the memory501as the base drive signal dA. As a result, the memory501stores the voltage variation information Dv2in place of the voltage variation information Dv0.

The voltage variation information Dv0latched by the latch circuit502is input to the adder503. The adder503adds the voltage variation information Dv0latched by the latch circuit502to the summed voltage variation information output by the latch circuit504and retains the result of addition as new summed voltage variation information.

Also, at each of time t7and time t9, the H-level clock signal dCK is input to the latch circuit504. In this case, because the voltage variation information Dv0latched by the latch circuit502is for keeping the voltage value constant, the latch circuit504latches summed voltage variation information that does not cause a change in the voltage value even when the H-level clock signal dCK is input and outputs the summed voltage variation information to the D/A converter505. As a result, at each of time t7and time t9, the D/A converter505generates and outputs the drive waveform signal WS with a constant voltage value.

Then, at time t10, the control circuit100sets the logic level of the latch signal dLAT, which is to be output as the base drive signal dA, to high. As a result, the voltage variation information Dv2for changing the voltage value stored in the memory501by the voltage −ΔV2is latched by the latch circuit502.

The voltage variation information Dv2latched by the latch circuit502is input to the adder503. The adder503adds the voltage variation information Dv2latched by the latch circuit502to the summed voltage variation information output by the latch circuit504and retains the result of addition as new summed voltage variation information.

Also, the control circuit100generates the clock signal dCK that becomes high (H level) at the interval AT and outputs the clock signal dCK to the latch circuit504as the base drive signal dA. Then, when the H-level clock signal dCK is input to the latch circuit504at each of time t11and time t12, the latch circuit504latches summed voltage variation information the voltage value of which has been decreased by the voltage ΔV2and outputs the summed voltage variation information to the D/A converter505. In response, at each of time t11and time t12, the D/A converter505generates and outputs the drive waveform signal WS the voltage value of which decreases by the voltage ΔV2.

Thus, the drive circuit506receives the drive waveform signal WS the voltage value of which increases, the drive waveform signal WS the voltage value of which is constant, and the drive waveform signal WS the voltage value of which decreases. The drive circuit506generates the amplification control signals Hdr and Ldr according to the voltage value of the input drive waveform signal WS and the feedback signal FB fed back from the amplifier circuit510described later, and outputs the amplification control signals Hdr and Ldr to the amplifier circuit510.

Referring back toFIG.9, the amplifier circuit510includes a transistor511and a transistor512. In the present embodiment, the transistor511is an NPN transistor and the transistor512is a PNP transistor.

The voltage signal Vamp is input to the collector terminal of the transistor511, and the amplification control signal Hdr is input to the base terminal of the transistor511. The emitter terminal of the transistor511is electrically connected to the emitter terminal of the transistor512. The amplification control signal Ldr is input to the base terminal of the transistor512, and a ground potential Gnd is input to the collector terminal of the transistor512. A signal at the connection point between the emitter terminal of the transistor511and the emitter terminal of the transistor512is output as the drive signal COM and is also fed back to the drive circuit506as the feedback signal FB.

In the amplifier circuit510as described above, the transistor511is controlled such that the collector terminal and the emitter terminal of the transistor511are electrically connected to each other when the voltage value of the drive waveform signal WS increases. As a result, the drive signal COM, the voltage value of which increases according to the voltage signal Vamp based on the voltage signal VHV, is output to the connection point between the emitter terminal of the transistor511and the emitter terminal of the transistor512. In contrast, the transistor512is controlled such that the emitter terminal and the collector terminal of the transistor512are electrically connected to each other when the voltage value of the drive waveform signal WS decreases. As a result, the drive signal COM, the voltage value of which decreases according to the ground potential Gnd, is output to the connection point between the emitter terminal of the transistor511and the emitter terminal of the transistor512.

That is, when the voltage value of the drive waveform signal WS output by the D/A converter505increases, the drive circuit506outputs the amplification control signal Hdr for controlling the transistor511such that the collector terminal and the emitter terminal of the transistor511are electrically connected to each other and the amplification control signal Ldr for controlling the transistor512such that the emitter terminal and the collector terminal of the transistor512are electrically disconnected from each other; and when the voltage value of the drive waveform signal WS output by the D/A converter505decreases, the drive circuit506outputs the amplification control signal Hdr for controlling the transistor511such that the collector terminal and the emitter terminal of the transistor511are electrically disconnected from each other and the amplification control signal Ldr for controlling the transistor512such that the emitter terminal and the collector terminal of the transistor512are electrically connected to each other. Here, the drive circuit506controls the amounts of current of signals output as the amplification control signals Hdr and Ldr based on the feedback signal FB. This results in controlling the current amplification factor of the drive signal COM supplied to the ejection head20.

When the voltage value of the drive waveform signal WS is constant, the transistor511is controlled such that the collector terminal and the emitter terminal of the transistor511are electrically disconnected from each other, and the transistor512is also controlled such that the emitter terminal and the collector terminal of the transistor512are electrically disconnected from each other. That is, when the voltage value of the drive waveform signal WS output by the D/A converter505is constant, the drive circuit506outputs the amplification control signal Hdr for controlling the transistor511such that the collector terminal and the emitter terminal of the transistor511are electrically disconnected from each other and the amplification control signal Ldr for controlling the transistor512such that the emitter terminal and the collector terminal of the transistor512are electrically disconnected from each other. As a result, a constant drive signal COM with an immediately-preceding voltage value is output to the connection point between the emitter terminal of the transistor511and the emitter terminal of the transistor512.

As described above, the drive circuit50of the present embodiment includes the amplifier circuit510that outputs the drive signal COM. The amplifier circuit510includes the transistor511that includes the collector terminal as one end to which the voltage signal Vamp based on the voltage signal VHV is supplied; and the transistor512that includes the emitter terminal as one end which is electrically connected to another end, i.e., the emitter terminal of the transistor511and includes the collector terminal as another end to which the ground potential Gnd is supplied. The amplifier circuit510amplifies, through the operations of the transistors511and512, the base drive signal dA, based on which the drive signal COM is generated, according to the voltage signal Vamp that is based on the voltage signal VHV corresponding to an amplification voltage.

5. Configuration and Operation of Leakage Current Detection Circuit

Next, a configuration and an operation of the leakage current detection circuit70are described. In the liquid ejecting apparatus1of the present embodiment, as described above, the drive circuit50generates the drive signal COM according to the voltage signal Vamp based on the voltage signal VHV with a high voltage and outputs the drive signal COM to the ejection head20. If a leakage current is generated in the drive circuit50, unintended heat generation may occur in the drive circuit50according to the leakage current and the voltage signal Vamp based on the high voltage signal VHV. Such unintended heat generation in the drive circuit50may affect the characteristics of various electronic components of the drive circuit50. This in turn may reduce the waveform accuracy of the drive signal COM output by the drive circuit50and reduce the operational stability of the drive circuit50. In particular, in the transistor511to which the high voltage signal Vamp is supplied, the heat generation caused by the leakage current may become significant.

For the above reason, the leakage current detection circuit70of the present embodiment detects a leakage current that may be generated in the drive circuit50, particularly the leakage current that may be generated in the transistor511, to reduce the probability that unintended heat generation occurs in the drive circuit50, thereby reduce the probability that the characteristics of various electronic components of the drive circuit50unintendedly change, and thereby reduce the probability that the waveform accuracy of the drive signal COM output by the drive circuit50decreases and the probability that the operational stability of the drive circuit50is reduced. In other words, in the liquid ejecting apparatus1of the present embodiment, the leakage current detection circuit70is electrically connected to the transistor511in the amplifier circuit510to which the voltage signal Vamp is supplied and configured to detect the leakage current that may be generated in the drive circuit50to reduce the probability that unintended heat generation occurs in the drive circuit50, thereby reduce the probability that the characteristics of various electronic components of the drive circuit50unintendedly change, and thereby reduce the probability that the waveform accuracy of the drive signal COM output by the drive circuit50decreases and the probability that the operational stability of the drive circuit50is reduced.

Next, a specific configuration and operation of the leakage current detection circuit70are described.FIG.11is a drawing for describing a configuration and operations of the leakage current detection circuit70. As illustrated inFIG.11, the leakage current detection circuit70includes a switch circuit710and a resistance element720. One end of the switch circuit710receives the voltage signal VHV, and another end of the switch circuit710is electrically connected to the collector terminal of the transistor511of the drive circuit50. The switch circuit710may be implemented by various types of switching devices such as a transistor. One end of the resistance element720receives the voltage signal VHV, and another end of the resistance element720is electrically connected to the collector terminal of the transistor511of the drive circuit50. In other words, the leakage current detection circuit70includes the switch circuit710and the resistance element720, one end of the switch circuit710is electrically connected to one end of the resistance element720, and another end of the switch circuit710and another end of the resistance element720are electrically connected to the transistor511.

In the leakage current detection circuit70configured as described above, the conduction state between one end and the other end of the switch circuit710is controlled according to the detection control signal Lck output by the control circuit100. Accordingly, when the switch circuit710is controlled by the detection control signal Lck such that one end and the other end of the switch circuit710are electrically connected to each other, the leakage current detection circuit70outputs the voltage signal VHV passing through the switch circuit710to the drive circuit50as the voltage signal Vamp; and when the switch circuit710is controlled by the detection control signal Lck such that one end and the other end of the switch circuit710are electrically disconnected from each other, the leakage current detection circuit70outputs the voltage signal VHV passing through the resistance element720to the drive circuit50as the voltage signal Vamp.

Also, the leakage current detection circuit70outputs a signal at a connection point between the other end of the switch circuit710and the other end of the resistance element720to a determination circuit101of the control circuit100as the detection voltage Vleak. That is, the leakage current detection circuit70outputs, to the determination circuit101, a signal having the same potential as the voltage signal Vamp output to the drive circuit50, as the detection voltage Vleak.

The determination circuit101determines whether a leakage current is generated in the drive circuit50based on the voltage value of the detection voltage Vleak input to the determination circuit101. That is, the liquid ejecting apparatus1of the present embodiment includes the determination circuit101that determines whether a leakage current generated in the drive circuit50is greater than or equal to a predetermined threshold, and the determination circuit101determines whether a leakage current is generated in the drive circuit50based on the voltage value of the transmission path through which the voltage signal Vamp is transmitted. The determination circuit101may also be provided as a component separate from the control circuit100.

When the determination circuit101determines, based on the detection voltage Vleak, that the amount of the leakage current generated in the drive circuit50is greater than or equal to the predetermined threshold, the control circuit100controls the transistor511to be non-conductive. Specifically, when the determination circuit101determines that the amount of the leakage current generated in the drive circuit50is greater than or equal to the predetermined threshold, the control circuit100generates a base drive signal dA for controlling the transistor511to be non-conductive and outputs the base drive signal dA to the drive circuit50. In response, the drive circuit50controls the transistor511to be non-conductive and stops outputting the drive signal COM. Here, the control circuit100may also be configured to cause the voltage output circuit110to stop the generation of the voltage signal VHV when the determination circuit101determines that the amount of the leakage current generated in the drive circuit50is greater than or equal to the predetermined threshold.

Next, an example of an operation of the leakage current detection circuit70configured as described above is described.FIG.12is a timing chart for describing an example of an operation of the leakage current detection circuit70in a case in which no leakage current is generated in the drive circuit50. In the descriptions below, in a cycle Ta of the drive signal COM, a period in which the voltage value of the drive signal COM increases is referred to as a period Tu, a period in which the voltage value of the drive signal COM decreases is referred to as a period Td, and a period in which the voltage value of the drive signal COM is constant is referred to as a period Tc.

In the period Tu in which the leakage current is not generated in the drive circuit50, the amplification control circuit500outputs a H-level amplification control signal Hdr and a H-level amplification control signal Ldr. Accordingly, in the period Tu in which the leakage current is not generated in the drive circuit50, the transistor511is controlled such that the collector terminal and the emitter terminal of the transistor511are electrically connected to each other, and the transistor512is controlled such that the emitter terminal and the collector terminal of the transistor512are electrically disconnected from each other.

Also, in the period Tu in which the leakage current is not generated in the drive circuit50, the control circuit100generates the detection control signal Lck for controlling the switch circuit710such that one end and the other end of the switch circuit710are electrically connected to each other and outputs the detection control signal Lck to the leakage current detection circuit70. As a result, the leakage current detection circuit70outputs the voltage signal VHV passed through the switch circuit710as the voltage signal Vamp. That is, the voltage signal Vamp with the same potential Vh as the voltage signal VHV is supplied to the collector terminal of the transistor511. As a result, the amplifier circuit510outputs the drive signal COM the voltage value of which increases toward the potential Vh.

Also, as described above, the leakage current detection circuit70generates the detection voltage Vleak with the same potential as the voltage signal Vamp supplied to the amplifier circuit510and outputs the detection voltage Vleak to the determination circuit101. That is, in the period Tu in which the leakage current is not generated in the drive circuit50, the leakage current detection circuit70generates the detection voltage Vleak with the potential Vh and outputs the detection voltage Vleak to the determination circuit101.

In the period Td in which the leakage current is not generated in the drive circuit50, the amplification control circuit500outputs a L-level amplification control signal Hdr and a L-level amplification control signal Ldr. Accordingly, in the period Td in which the leakage current is not generated in the drive circuit50, the transistor511is controlled such that the collector terminal and the emitter terminal of the transistor511are electrically disconnected from each other, and the transistor512is controlled such that the emitter terminal and the collector terminal of the transistor512are electrically connected to each other. As a result, the amplifier circuit510outputs the drive signal COM the voltage value of which decreases toward the ground potential Gnd.

Also, in the period Td in which the leakage current is not generated in the drive circuit50, the control circuit100generates the detection control signal Lck for controlling the switch circuit710such that one end and the other end of the switch circuit710are electrically disconnected from each other and outputs the detection control signal Lck to the leakage current detection circuit70. Accordingly, the leakage current detection circuit70outputs the voltage signal VHV passed through the resistance element720as the voltage signal Vamp. As a result, the voltage signal VHV passed through the resistance element720is supplied to the collector terminal of the transistor511as the voltage signal Vamp.

In this case, in the example shown inFIG.12, because the leakage current is not generated in the drive circuit50, no electric current flows between the collector terminal and the emitter terminal of the transistor511that is controlled to be non-conductive. Accordingly, no electric current flows to the resistance element720either. Therefore, no voltage drop is caused by the resistance element720, and the leakage current detection circuit70outputs the voltage signal Vamp with the same potential Vh as the voltage signal VHV. That is, the voltage signal Vamp with the same potential Vh as the voltage signal VHV is supplied to the collector terminal of the transistor511.

Also, as described above, the leakage current detection circuit70outputs, to the determination circuit101, the detection voltage Vleak with the same potential as the voltage signal Vamp supplied to the amplifier circuit510. That is, in the period Td in which the leakage current is not generated in the drive circuit50, the leakage current detection circuit70generates the detection voltage Vleak with the potential Vh and outputs the detection voltage Vleak to the determination circuit101.

In the period Tc in which the leakage current is not generated in the drive circuit50, the amplification control circuit500outputs a L-level amplification control signal Hdr and a H-level amplification control signal Ldr. Accordingly, in the period Tc in which the leakage current is not generated in the drive circuit50, the transistor511is controlled such that the collector terminal and the emitter terminal of the transistor511are electrically disconnected from each other, and the transistor512is controlled such that the emitter terminal and the collector terminal of the transistor512are electrically disconnected from each other. As a result, the amplifier circuit510outputs a constant drive signal COM with an immediately-preceding voltage value.

Also, in the period Tc in which the leakage current is not generated in the drive circuit50, the control circuit100generates the detection control signal Lck for controlling the switch circuit710such that one end and the other end of the switch circuit710are electrically disconnected from each other and outputs the detection control signal Lck to the leakage current detection circuit70. Accordingly, the leakage current detection circuit70outputs the voltage signal VHV passed through the resistance element720as the voltage signal Vamp. As a result, the voltage signal VHV passed through the resistance element720is supplied to the collector terminal of the transistor511as the voltage signal Vamp. In this case, in the example shown inFIG.12, because the leakage current is not generated in the drive circuit50, no electric current flows between the collector terminal and the emitter terminal of the transistor511that is controlled to be non-conductive. Accordingly, no electric current flows to the resistance element720either. Therefore, no voltage drop is caused by the resistance element720, and the leakage current detection circuit70outputs the voltage signal Vamp with the same potential Vh as the voltage signal VHV. That is, the voltage signal Vamp with the same potential Vh as the voltage signal VHV is supplied to the collector terminal of the transistor511.

Also, as described above, the leakage current detection circuit70outputs, to the determination circuit101, the detection voltage Vleak with the same potential as the voltage signal Vamp supplied to the amplifier circuit510. That is, in the period Tc in which the leakage current is not generated in the drive circuit50, the leakage current detection circuit70generates the detection voltage Vleak with the potential Vh and outputs the detection voltage Vleak to the determination circuit101.

Next, an example of an operation of the leakage current detection circuit70in a case in which the leakage current is generated in the drive circuit50is described.FIG.13is a timing chart for describing an example of an operation of the leakage current detection circuit70in a case in which the leakage current is generated in the drive circuit50. Similarly toFIG.12,FIG.13illustrates the period Tu in which the voltage value of the drive signal COM increases, the period Td in which the voltage value of the drive signal COM decreases, and the period Tc in which the voltage value of the drive signal COM is constant.

In the period Tu in which the leakage current is generated in the drive circuit50, as in the period Tu in which the leakage current is not generated in the drive circuit50, the amplification control circuit500outputs a H-level amplification control signal Hdr and a H-level amplification control signal Ldr. Accordingly, the transistor511is controlled such that the collector terminal and the emitter terminal of the transistor511are electrically connected to each other, and the transistor512is controlled such that the emitter terminal and the collector terminal of the transistor512are electrically disconnected from each other.

Also, in the period Tu in which the leakage current is generated in the drive circuit50, as in the period Tu when the leakage current is not generated in the drive circuit50, the control circuit100generates the detection control signal Lck for controlling the switch circuit710such that one end and the other end of the switch circuit710are electrically connected to each other and outputs the detection control signal Lck to the leakage current detection circuit70. Therefore, the leakage current detection circuit70outputs the voltage signal VHV passed through the switch circuit710as the voltage signal Vamp. Accordingly, the voltage signal Vamp with the same potential Vh as the voltage signal VHV is supplied to the collector terminal of the transistor511. As a result, the amplifier circuit510outputs the drive signal COM the voltage value of which increases toward the potential Vh. Also, in the period Tu in which the leakage current is generated in the drive circuit50, as in the period Tu in which the leakage current is not generated in the drive circuit50, the leakage current detection circuit70generates the detection voltage Vleak with the potential Vh and outputs the detection voltage Vleak to the determination circuit101.

In the period Td in which the leakage current is generated in the drive circuit50, as in the period Td in which the leakage current is not generated in the drive circuit50, the amplification control circuit500outputs a L-level amplification control signal Hdr and a L-level amplification control signal Ldr. Accordingly, the transistor511is controlled such that the collector terminal and the emitter terminal of the transistor511are electrically disconnected from each other, and the transistor512is controlled such that the emitter terminal and the collector terminal of the transistor512are electrically connected to each other. As a result, the amplifier circuit510outputs the drive signal COM the voltage value of which decreases toward the ground potential Gnd.

Also, in the period Td in which the leakage current is generated in the drive circuit50, as in the period Td in which the leakage current is not generated in the drive circuit50, the control circuit100generates the detection control signal Lck for controlling the switch circuit710such that one end and the other end of the switch circuit710are electrically disconnected from each other and outputs the detection control signal Lck to the leakage current detection circuit70. Accordingly, the leakage current detection circuit70outputs the voltage signal VHV passed through the resistance element720as the voltage signal Vamp. As a result, the voltage signal VHV passed through the resistance element720is supplied to the collector terminal of the transistor511as the voltage signal Vamp.

In this case, in the example shown inFIG.13, because the leakage current is generated in the drive circuit50, the leakage current flows between the collector terminal and the emitter terminal of the transistor511that is controlled to be non-conductive. Therefore, a voltage drop ΔV occurs at the ends of the resistance element720due to the resistance element720and the leakage current generated in the transistor511. Accordingly, the leakage current detection circuit70outputs the voltage signal Vamp with a potential Vl that has decreased from the voltage signal VHV by the voltage drop ΔV. That is, the voltage signal Vamp with the potential Vl, which has decreased by the voltage drop ΔV from the voltage signal VHV, is supplied to the collector terminal of the transistor511. Accordingly, in the period Td in which the leakage current is generated in the drive circuit50, the leakage current detection circuit70generates the detection voltage Vleak with the potential Vl lower than the potential Vh and outputs the detection voltage Vleak to the determination circuit101.

In the period Tc in which the leakage current is generated in the drive circuit50, as in the period Tc in which the leakage current is not generated in the drive circuit50, the amplification control circuit500outputs a L-level amplification control signal Hdr and a H-level amplification control signal Ldr. Accordingly, the transistor511is controlled such that the collector terminal and the emitter terminal of the transistor511are electrically disconnected from each other, and the transistor512is controlled such that the emitter terminal and the collector terminal of the transistor512are electrically disconnected from each other. As a result, the amplifier circuit510outputs a constant drive signal COM with an immediately-preceding voltage value.

Also, in the period Tc in which the leakage current is generated in the drive circuit50, as in the period Tc in which the leakage current is not generated in the drive circuit50, the control circuit100generates the detection control signal Lck for controlling the switch circuit710such that one end and the other end of the switch circuit710are electrically disconnected from each other and outputs the detection control signal Lck to the leakage current detection circuit70. Accordingly, the leakage current detection circuit70outputs the voltage signal VHV passed through the resistance element720as the voltage signal Vamp. As a result, the voltage signal VHV passed through the resistance element720is supplied to the collector terminal of the transistor511as the voltage signal Vamp.

In this case, in the example shown inFIG.13, because the leakage current is generated in the drive circuit50, the leakage current flows between the collector terminal and the emitter terminal of the transistor511that is controlled to be non-conductive. Therefore, the voltage drop ΔV occurs at the ends of the resistance element720due to the resistance element720and the leakage current generated in the transistor511. Accordingly, the leakage current detection circuit70outputs the voltage signal Vamp with the potential Vl that has decreased from the voltage signal VHV by the voltage drop ΔV. That is, the voltage signal Vamp with the potential Vl, which has decreased by the voltage drop ΔV from the voltage signal VHV, is supplied to the collector terminal of the transistor511. Accordingly, in the period Tc in which the leakage current is generated in the drive circuit50, the leakage current detection circuit70generates the detection voltage Vleak with the potential Vl lower than the potential Vh and outputs the detection voltage Vleak to the determination circuit101.

As described above, in the liquid ejecting apparatus1of the present embodiment, the control circuit100controls the switch circuit710of the leakage current detection circuit70to be non-conductive in the periods Tc and Td in which the transistor511is controlled such that the collector terminal and the emitter terminal of the transistor511are electrically disconnected from each other. That is, one end and the other end of the switch circuit710are electrically disconnected from each other when the transistor511is controlled to be non-conductive. As a result, the voltage signal VHV passes through the resistance element720and is supplied to the collector terminal of the transistor511.

The determination circuit101determines whether the leakage current is generated in the drive circuit50based on the potential of the detection voltage Vleak that is input when the transistor511is controlled to be non-conductive. That is, the leakage current detection circuit70detects the leakage current in the drive circuit50when the transistor511is controlled to be non-conductive, and the determination circuit101determines whether the leakage current is generated in the drive circuit50based on a detection result of the leakage current detection circuit70obtained while the transistor511is controlled to be non-conductive.

Specifically, when the switch circuit710is controlled such that one end and the other end of the switch circuit710are electrically disconnected from each other, the voltage signal VHV passes through the resistance element720and is supplied to the collector terminal of the transistor511. In this case, the voltage drop ΔV occurs at the ends of the resistance element720due to an electric current flowing between the collector terminal and the emitter terminal of the transistor511. That is, when the leakage current is not generated in the transistor511, no electric current flows to the resistance element720during a period in which the transistor511is controlled to be non-conductive, and as a result, the voltage drop ΔV does not occur at the ends of the resistance element720. In contrast, when the leakage current is generated in the transistor511, the leakage current flows to the resistance element720even in a period during which the transistor511is controlled to be non-conductive, and as a result, the voltage drop ΔV corresponding to the amount of the leakage current occurs at the ends of the resistance element720. The leakage current detection circuit70generates the detection voltage Vleak with a potential lower than the potential Vh of the voltage signal VHV by the voltage drop ΔV that has occurred at the ends of the resistance element720in a period in which the transistor511is controlled to be non-conductive, and outputs the detection voltage Vleak to the determination circuit101.

The determination circuit101calculates the amount of current flowing into the drive circuit50based on a potential difference between the potential Vl of the received detection voltage Vleak and the potential Vh of the voltage signal VHV and the resistance value of the resistance element720, and determines whether the leakage current is generated in the drive circuit50based on whether the calculated amount of current is greater than or equal to the predetermined threshold. Then, the determination circuit101causes the drive circuit50to stop outputting the drive signal COM or cause the voltage output circuit110to stop outputting the voltage signal VHV when the calculated amount of current is greater than or equal to the predetermined threshold, i.e., when it is determined that the leakage current is generated in the drive circuit50. With this configuration, the leakage current detection circuit70can detect the leakage current that may be generated in the drive circuit50. This in turn makes it possible to reduce the probability that various electronic components of the drive circuit50unintendedly generate heat due to the leakage current and also reduce the probability that the operational stability of the drive circuit50and the liquid ejecting apparatus1is reduced due to the generation of heat.

Here, the drive signal COM and the drive signal VOUT based on the drive signal COM are examples of drive signals, the transistor511of the drive circuit50is an example of a first transistor, the transistor512is an example of a second transistor, the voltage signal Vamp output by the leakage current detection circuit70and input to the collector terminal of the transistor511is an example of an amplification voltage, and a wiring pattern that electrically connects the leakage current detection circuit70to the drive circuit50and through which the voltage signal Vamp output by the leakage current detection circuit70is transmitted is an example of a transmission path.

6. Effects

As described above, the liquid ejecting apparatus1of the present embodiment includes the piezoelectric element60that is driven by the drive signal VOUT based on the drive signal COM; the ejection head20that ejects ink when the piezoelectric element60is driven; the drive circuit50that outputs the drive signal COM, the drive circuit50including the amplifier circuit510that includes the transistors511and512and amplifies, based on the voltage signal Vamp and through the operations of the transistors511and512, the base drive signal dA based on which the drive signal COM is generated; and the leakage current detection circuit70that detects the leakage current in the drive circuit50. The leakage current detection circuit70is electrically connected to the transistor511included in the amplifier circuit510to which the voltage signal Vamp is supplied. That is, the leakage current detection circuit70detects the leakage current that may be generated in the drive circuit50due to the voltage signal Vamp used as an amplification voltage for generating the drive signal COM in the drive circuit50.

With the above configuration, the liquid ejecting apparatus1of the present embodiment can accurately detect whether the leakage current is generated in the drive circuit50due to the voltage signal Vamp. This in turn makes it possible to reduce the probability that various electronic components of the drive circuit50unintendedly generate heat due to the leakage current and also reduce the probability that the operational stability of the drive circuit50and the liquid ejecting apparatus1is reduced due to the generation of heat.

Particularly, because the voltage signal Vamp is a high voltage signal used to generate the drive signal COM, it is highly probable that the leakage current is generated in the drive circuit50due to the voltage signal Vamp. Also, when the leakage current is generated in the drive circuit50due to the voltage signal Vamp, the amount of heat generated in the drive circuit50may become large. With the leakage current detection circuit70that detects, in a path through which the voltage signal Vamp is transmitted, whether the leakage current is generated in the drive circuit50, it is possible to efficiently reduce the probability that various electronic components of the drive circuit50unintendedly generate heat due to the leakage current and to also efficiently reduce the probability that the operational stability of the drive circuit50and the liquid ejecting apparatus1is reduced due to the generation of heat.

Also, considering that the drive signal COM output by the drive circuit50is a signal amplified based on the voltage signal Vamp and that the drive signal VOUT based on the drive signal COM is supplied to the electrode611of the piezoelectric element60, if the leakage current is generated in the transistor511, it is probable that a signal with an unintended voltage value is supplied to the electrode611of the piezoelectric element60due to the leakage current. Such a signal having an unintended voltage value and supplied to the piezoelectric element60may affect the drive characteristics of the piezoelectric element60. This in turn may affect ink ejection characteristics of the ejection head20, may apply unintended stress on the piezoelectric element60, and may form a crack in the piezoelectric element60.

In view of the above problems, the leakage current detection circuit70is provided to detect, in a path through which the voltage signal Vamp is transmitted, whether the leakage current is generated in the drive circuit50. This makes it possible to reduce the probability that a signal with an unintended voltage value is supplied to the piezoelectric element60due to the leakage current, thereby reduce the probability that the ink ejection characteristics of the ejection head20are degraded, and also reduce the probability that a crack is formed in the piezoelectric element60.

Furthermore, the leakage current detection circuit70includes the switch circuit710and the resistance element720and detects the leakage current generated in the drive circuit50when the transistor511is controlled such that the collector terminal and the emitter terminal of the transistor511are electrically disconnected from each other and the switch circuit710is controlled such that one end and the other end of the switch circuit710are electrically disconnected from each other. This configuration reduces the probability that the operation of the leakage current detection circuit70affects the waveform of the drive signal COM output by the drive circuit50, improves the waveform accuracy of the drive signal COM, and improves the accuracy of ink ejection from the ejection head20.

7. Second Embodiment

Next, a liquid ejecting apparatus1according to a second embodiment is described. In describing the liquid ejecting apparatus1of the second embodiment, the same reference numbers assigned to components of the liquid ejecting apparatus1of the first embodiment are assigned to the corresponding components of the liquid ejecting apparatus1of the second embodiment, and the descriptions of those components are omitted or simplified.

FIG.14is a timing chart for describing an example of an operation of the leakage current detection circuit70of the liquid ejecting apparatus1of the second embodiment in a case in which no leakage current is generated in the drive circuit50.FIG.15is a timing chart for describing an example of an operation of the leakage current detection circuit70of the liquid ejecting apparatus1of the second embodiment in a case in which a leakage current is generated in the drive circuit50. As shown inFIGS.14and15, the liquid ejecting apparatus1of the second embodiment differs from the liquid ejecting apparatus1of the first embodiment in that the control circuit100generates the detection control signal Lck for controlling the switch circuit710such that one end and the other end of the switch circuit710are electrically connected to each other and outputs the detection control signal Lck to the leakage current detection circuit70in the period Td in which the voltage value of the drive signal COM output by the drive circuit50decreases.

That is, in the liquid ejecting apparatus1of the second embodiment, the leakage current detection circuit70detects the leakage current that may be generated in the drive circuit50when the transistor511is controlled to be non-conductive and the transistor512is controlled to be non-conductive.

The liquid ejecting apparatus1of the second embodiment configured as described above can provide advantageous effects similar to those provided by the first embodiment, and the leakage current detection circuit70can detect the leakage current, which may be generated in the drive circuit50, in the period Tc in which the voltage value of the drive signal COM is constant. This reduces the provability that the variation of the voltage value of the voltage signal VHV, which may vary according to the operations of the transistors511and512, affects the detection of the leakage current, which may be generated in the drive circuit50, by the leakage current detection circuit70and further improves the detection accuracy of the leakage current that may be generated in the drive circuit50.

8. Variations

In the liquid ejecting apparatus1of the first embodiment and the liquid ejecting apparatus1of the second embodiment described above, it is assumed that the drive circuit50includes a class B amplifier circuit or a class AB amplifier circuit that amplifies a signal corresponding to the base drive signal dA through the operations of the transistors511and512. However, the drive circuit50is not limited to a class B amplifier circuit or a class AB amplifier circuit, but may also be, for example, a class A amplifier circuit or a class D amplifier circuit.

However, in view of reducing the power consumption of the liquid ejecting apparatus1and improving the waveform accuracy of the drive signal COM, the drive circuit50is preferably implemented by a class AB amplifier circuit or a class D amplifier circuit. Here, when a class D amplifier circuit, in which a switching element corresponding to the transistor511operates at a high frequency, is used in a configuration in which the leakage current detection circuit70detects the leakage current, which may be generated in the drive circuit50, in a period in which the transistor511is non-conductive, the number of operations of the switch circuit710may increase and as a result, heat generation in the switch circuit710may increase. For this reason, the drive circuit50is preferably implemented by a class AB amplifier circuit as described in the above embodiments.

That is, although the drive circuit50may be implemented by any of a class A amplifier circuit, a class B amplifier circuit, a class AB amplifier circuit, and a class D amplifier circuit, the drive circuit50is particularly preferably implemented by a class AB amplifier circuit.

Also, in the liquid ejecting apparatus1of the first embodiment and the liquid ejecting apparatus1of the second embodiment described above, the determination circuit101calculates the amount of the leakage current that may be generated in the drive circuit50by comparing the potential Vh of the predetermined voltage signal VHV with the potential Vl of the detection voltage Vleak input from the leakage current detection circuit70. Alternatively, the determination circuit101may be configured to receive both of the voltage signal VHV and the detection voltage Vleak and to calculate the amount of the leakage current that may be generated in the drive circuit50by comparing the potential Vh of the received voltage signal VHV and the potential Vl of the received detection voltage Vleak.

The embodiments and variations of the present disclosure are described above. However, the present disclosure is not limited to the above-described embodiments and variations and may be implemented in various manners without departing from the spirit of the present disclosure. For example, the above embodiments may be combined in any appropriate manner.

The present disclosure includes configurations that are substantially the same as the configurations described in the embodiments (e.g., a configuration the functions, methods, and results of which are the same as those of the above embodiments, or a configuration the purpose and effects of which are the same as those of the above embodiments). Also, the present disclosure includes a configuration obtained by replacing non-essential components of a configuration described in the embodiments. Also, the present disclosure includes a configuration that can provide the same effect or achieve the same purpose as that provided or achieved by a configuration described in the embodiments. Furthermore, the present disclosure includes a configuration obtained by adding a known technology to a configuration described in the embodiments.

The following configurations may be derived from the embodiments described above.

A liquid ejecting apparatus according to an embodiment includes a driven element that is driven by a drive signal; an ejection head that ejects a liquid when the driven element is driven; a drive circuit that outputs the drive signal, the drive circuit including an amplifier circuit that includes a first transistor and amplifies, based on an amplification voltage and through an operation of the first transistor, a base drive signal based on which the drive signal is generated; and a leakage current detection circuit that detects a leakage current in the drive circuit. The leakage current detection circuit is electrically connected to the first transistor included in the amplifier circuit to which the amplification voltage is supplied.

According to this liquid ejecting apparatus, the leakage current detection circuit for detecting the leakage current in the drive circuit is electrically connected to the first transistor included in the amplifier circuit that is included in the drive circuit and amplifies, based on the amplification voltage, the base drive signal based on which the drive signal is generated. With this configuration, the leakage current detection circuit can detect, based on the amplification voltage that is a high voltage, the leakage current that may be generated in the drive circuit. This in turn makes it possible to efficiently reduce the probability that various electronic components of the drive circuit unintendedly generate heat due to the leakage current generated in the drive circuit and to also efficiently reduce the probability that the operational stability of the drive circuit and the liquid ejecting apparatus is reduced due to the generation of heat.

In the liquid ejecting apparatus according to the embodiment, the amplification voltage may be supplied to one end of the first transistor, and the leakage current detection circuit may detect the leakage current when the first transistor is controlled to be non-conductive.

In the liquid ejecting apparatus according to the embodiment, the amplifier circuit may include a second transistor including one end that is electrically connected to the first transistor and another end to which a ground potential is supplied, and the leakage current detection circuit may detect the leakage current when the first transistor is controlled to be non-conductive and the second transistor is controlled to be non-conductive.

According to this liquid ejecting apparatus, the leakage current detection circuit detects the leakage current that may be generated in the drive circuit in a period in which both of the first transistor and the second transistor of the drive circuit are controlled to be non-conductive. This makes it possible to reduce the probability that the operations of the first transistor and the second transistor affect the leakage current detection circuit. As a result, the accuracy of detecting the leakage current, which may be generated in the drive circuit, by the leakage current detection circuit is improved.

In the liquid ejecting apparatus according to the embodiment, the leakage current detection circuit may include a switch circuit and a resistance element, one end of the switch circuit may be electrically connected to one end of the resistance element, and another end of the switch circuit and another end of the resistance element may be electrically connected to the first transistor.

In the liquid ejecting apparatus according to the embodiment, the switch circuit may be controlled such that one end and the other end of the switch circuit are electrically disconnected from each other when the first transistor is controlled to be non-conductive.

The liquid ejecting apparatus according to the embodiment may further include a determination circuit that determines whether the amount of the leakage current is greater than or equal to a predetermined threshold, and the determination circuit may determine whether the leakage current is present based on a voltage value of a transmission path through which the amplification voltage is transmitted.

In the liquid ejecting apparatus according to the embodiment, the first transistor may be controlled to be non-conductive when the determination circuit determines that the amount of the leakage current is greater than or equal to the predetermined threshold.

According to this liquid ejecting apparatus, the operation of the drive circuit can be stopped when the leakage current generated in the drive circuit is greater than or equal to a predetermined current value. This makes it possible to further improve the operational stability of the drive circuit and the liquid ejecting apparatus.