Patent ID: 12217971

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

FIGS.1A to16Bshow various stages of a sequential manufacturing operation of a semiconductor device according to an embodiment of the present disclosure. It is understood that additional operations can be provided before, during, and after the processes shown byFIGS.1A to16B, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. Material, configuration, dimensions and/or processes the same as or similar to the foregoing embodiments described withFIGS.1A to16Bmay be employed in the following embodiments, and detailed explanation thereof may be omitted.

Reference is made toFIGS.1A and1B, in whichFIG.1Bis a cross-sectional view along line A-A ofFIG.1A. Shown there is a substrate100. In some embodiments, the substrate100includes a semiconductor substrate. The substrate100may include a crystalline silicon substrate or a doped semiconductor substrate (e.g., p-type semiconductor substrate or n-type semiconductor substrate). In some alternative embodiments, the substrate100includes a semiconductor substrate made of other suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide.

A gate structure110is formed over the substrate100. In some embodiments, the gate structure110may include a gate dielectric, a work function metal layer, and a filling metal. For example, the gate dielectric may be silicon oxide, and may include high-K dielectrics, such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3(STO), BaTiO3(BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3(BST), Al2O3, Si3N4, oxynitrides (SiON), combinations thereof, or other suitable material. The work function metal layer may be a p-type work function layers for p-type device, or an n-type work function layers for n-type device. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals include Ti, TiN, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function metal layer may include a plurality of layers. In some embodiments, the filling metal may include tungsten (W). In some other embodiments, the gate electrode includes aluminum (Al), copper (Cu) or other suitable conductive material. In some other embodiments, the gate structure110may include a gate dielectric and a gate electrode. For example, the gate dielectric may be silicon oxide, and the gate electrode may be a conductive and may be selected from a group including polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals.

Gate spacers115are formed on opposite sidewalls of the gate structure110. In some embodiments, the gate spacers115may be formed of silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, using techniques such as thermal oxidation or deposited by CVD, ALD, or the like.

Source/drain regions120may be formed as doped regions in the substrate100and on opposite sides of the gate structures110. In some embodiments, the source/drain regions120may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable material, and may be doped with N-type dopants or P-type dopants. In some embodiments, the source/drain regions120are epitaxially grown over there substrate100, and may also be referred to as source/drain epitaxial structures. In some embodiments, the gate structure110and the source/drain regions120on opposite sides of the gate structure110may form a transistor.

An interlayer dielectric (ILD) layer130may be formed over the substrate100. In some embodiments, the ILD layer130may include silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or other suitable dielectric materials. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. In some embodiments, the ILD layer130may be formed by suitable deposition process, such as CVD, PVD, ALD, or the like.

Source/drain contacts135are formed in the ILD layer130and are electrically connected to the source/drain regions120. In some embodiments, the source/drain contacts135may include Ti, W, Co, Cu, Al, Mo, MoW, W, TiN, TaN, WN, combinations thereof, or other suitable conductive material.

An interlayer dielectric (ILD) layer140may be formed over the ILD layer130. In some embodiments, the ILD layer140may include silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or other suitable dielectric materials, Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. In some embodiments, the ILD layer140may be formed by suitable deposition process, such as CVD, PVD, ALD, or the like.

Via plugs145are formed in the ILD layer140, and may be formed in contact with the gate structure110, and may be formed in contact with at least one of the source/drain contacts135. In some embodiments, the via plugs145may include Ti, W, Co, Cu, Al, Mo, MoW, W, TiN, TaN, WN, combinations thereof, or other suitable conductive material. In some embodiments, the via plug145over the gate structure110can be referred to as a gate contact, and the via plugs145over the source/drain contacts135can be referred to as source/drain vias.

An interlayer dielectric (ILD) layer150may be formed over the ILD layer140. In some embodiments, the ILD layer150may include silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric material, and/or other suitable dielectric materials, Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. In some embodiments, the ILD layer150may include extreme low-k dielectric (ELK) material. In some embodiments, the ILD layer150may be formed by suitable deposition process, such as CVD, PVD, ALD, or the like.

An anti-reflective coating (ARC) layer160is formed over the ILD layer150. In some embodiments, the ARC layer160may be a nitrogen-free anti-reflection coating (NFARC) layer, and may also be referred to as a NFARC layer160. In some embodiments, the NFARC layer160may include a material such as silicon oxide, silicon oxygen carbide, or plasma enhanced chemical vapor deposited silicon oxide. In some embodiments, the ARC160may be formed by suitable deposition process, such as CVD, PVD, ALD, or the like. In some embodiments, the ARC layer160may also be referred to as a dielectric layer.

A titanium nitride (TiN) layer165is then formed over the ARC layer160. The titanium nitride layer165is formed by a radio-frequency physical vapor deposition (RFPVD) process in the some embodiments, or may be formed by an alternative processes in other embodiments. In some embodiments, the titanium nitride layer165may also be referred to as a conductive layer.

A tetraethyl orthosilicate (TEOS) layer170is then formed over the titanium nitride layer165. In some embodiments, the TEOS layer170is formed by a process such as PVD, CVD, plasma enhanced chemical vapor deposition (PECVD), combinations thereof, or another suitable technique. In some embodiments, the TEOS layer170may also be referred to as a dielectric layer.

An amorphous silicon layer175is then formed over the TEOS layer170. The amorphous silicon layer175is formed by a process such as PVD, CVD, sputtering, or another suitable technique. The amorphous silicon layer175herein may serve as a mask layer to be patterned by a photoresist layer (discussed below). In other embodiments, a mask layer of another suitable material may be used instead of the amorphous silicon layer175. In some embodiments, the amorphous silicon layer175may be patterned according to a predetermined pattern. Accordingly, as shown inFIGS.1A and1B, portions of top surfaces of the TEOS layer170are covered by the amorphous silicon layer175, and portions of the top surfaces of the TEOS layer170are exposed by the amorphous silicon layer175.

Reference is made toFIGS.2A and2B, in whichFIG.2Bis a cross-sectional view along line A-A ofFIG.2A. A first spacer layer180is formed over the amorphous silicon layer175. In some embodiments, the first spacer layer180is formed in a conformal manner. That is, the first spacer layer180may be formed conformal to the underlying structure (i.e., following the topography of underlying structure), such as the amorphous silicon layer175and the exposed portions of the TEOS layer170. In some embodiments, the first spacer layer180may include titanium oxide, and thus the first spacer layer180may also be referred to as a first titanium oxide layer.

Reference is made toFIGS.3A and3B, in whichFIG.3Bis a cross-sectional view along line A-A ofFIG.3A. A second spacer layer190is formed over the first spacer layer180. In some embodiments, the second spacer layer190is formed in a conformal manner. That is, the second spacer layer190may be formed conformal to the first spacer layer180(i.e., following the topography of the first spacer layer180). In some embodiments, the second spacer layer190may include titanium oxide, and thus the second spacer layer190may also be referred to as a second titanium oxide layer.

In some embodiments, the first and second spacer layers180and190may be made of the same material, such as titanium oxide (TiO). However, the first and second spacer layers180and190may be deposited via different processes and/or different process conditions. For example, the first spacer layer180may be deposited by ALD without using plasma treatment (i.e., plasma-free ALD), while the second spacer layer190may be deposited by ALD with plasma treatment (e.g., plasma-enhanced ALD (PEALD)). In some embodiments, the plasma treatment may use Ar, N2, or N2O plasma. In this way, the second spacer layer190may include better crystalline quality than the first spacer layer180, which in turn will increase the etching resistance of the second spacer layer190and hence reduce the etch rate of the second spacer layer190during the following etching processes (e.g., the etching process discussed inFIGS.12Aand12B), and will improve the process reliability. In some embodiments, the first and second spacer layers180and190may be deposited under temperatures in a ranged from about 50° C. to about 200° C. In some embodiments, the first spacer layer180is deposited under a temperature lower than 200° C. In some other embodiments, the second spacer layer190may be made of silicon nitride (SiNx), metal oxide (e.g., aluminum oxide (Al2O3)), metal nitride (e.g., titanium nitride (TiN)), or other suitable materials.

After the second spacer layer190is formed, the first spacer layer180and the second spacer layer190can be collectively referred to as a composite spacer layer200(or a bilayer spacer film). In some embodiments, the composite spacer layer200may include first horizontal portions200A horizontally extending along top surfaces of the amorphous silicon layer175, vertical portions200B vertically extending along sidewalls of the amorphous silicon layer175, and second horizontal portions200C horizontally extending along top surfaces of the exposed portions of the TEOS layer170.

Reference is made toFIGS.4A and4B, in whichFIG.4Bis a cross-sectional view along line A-A ofFIG.4A. A tri-layer photoresist210is formed over the composite spacer layer200. In some embodiments, the tri-layer photoresist210may include a bottom layer (BL)212, a middle layer (ML)214, and a top layer (IL)216. In some embodiments, the bottom layer212may include a CxHyOzmaterial, the middle layer214may include a SiCxHyOzmaterial, and the top layer216may include a CxHyOzmaterial. The CxHyOzmaterial of the bottom layer212may be the same as the CxHyOzmaterial of the top layer212in some embodiments, or may also be different in other embodiments. The top layer216also includes a photo-sensitive element, such as a photo-acid generator (PAG). This allows a photolithography process to be performed to pattern the top layer212. It is understood that in other embodiments, one or more layers of the tri-layer photoresist may be omitted, or additional layers may be provided as a part of the tri-layer photoresist, and the layers may be formed in difference sequences.

InFIGS.4A and4B, the top layer216is patterned by a photolithography process, which may include one or more exposure, developing, rinsing, and baking processes (not necessarily performed in this order). The photolithography process patterns the top layer216into a photoresist mask, which may have one or more trenches or openings that expose the middle layer214therebelow. As an example, openings O1are formed in the top layer216, and the openings O1expose portions of the middle layer214.

Reference is made toFIGS.5A and5B, in whichFIG.5Bis a cross-sectional view along line A-A ofFIG.5A. One or more etching processes may be performed to “open” the middle layer214and the bottom layer212. Stated another way, the openings O1in the top layer216are extended downwardly into the middle layer214and the bottom layer212. After the openings O1are formed in the middle layer214and the bottom layer212, portions of the composite spacer layer200is exposed ion greater details, the first horizontal portions200A, the vertical portions200B, and the second horizontal portions200C of the composite spacer layer200are exposed by the openings O1.

Reference is made toFIGS.6A and6B, in whichFIG.6Bis a cross-sectional view along line A-A ofFIG.6A. The top layer216may be removed to expose the middle layer214. In some embodiments, the top layer216may be removed by suitable process, such as plasma ashing, wet strip, or combinations thereof.

Reference is made toFIGS.7A and7B, in whichFIG.7Bis a cross-sectional view along line A-A ofFIG.7A. A hard mask layer220is formed over the middle layer214and filling the openings O1of the middle layer214and the bottom layer212. Accordingly, the hard mask layer220may be formed in contact with the second spacer layer190of the composite spacer layer200. In greater details, the hard mask layer220may be in contact with the first horizontal portions200A, the vertical portions200B, and the second horizontal portions200C of the composite spacer layer200that are exposed by the openings O1. In some embodiments, the hard mask layer220may include a dielectric material. In some embodiments, the hard mask layer220may include oxide, such as silicon oxide, silicon dioxide (SiO2), or other suitable materials.

Reference is made toFIGS.8A and8B, in whichFIG.8Bis a cross-sectional view along line A-A ofFIG.8A. The hard mask layer220(seeFIGS.7A and7B) is etched back to lower a top surface of the hard mask layer220to form a plurality of hard masks230. In some embodiments, the top surface of the hard mask layer220may be lowered to a position that is below a topmost position of the first horizontal portions200A of the composite spacer layer200. Stated another way, the top surface of the hard mask layer220may be lowered to a position that is below a topmost position of the second spacer layer190of the composite spacer layer200. In some embodiments, the top surfaces of the hard masks230may be lower than the topmost position of the second spacer layer190of the composite spacer layer200, and may be higher than the topmost position of the first spacer layer180of the composite spacer layer200. In some other embodiments, the top surface of the hard mask layer220may be lowered to a position that is substantially level with the topmost position of the first horizontal portions200A of the composite spacer layer200, or is substantially level with the topmost position of the second spacer layer190of the composite spacer layer200.

Accordingly, after the etch back process, the top surfaces of the first horizontal portions200A of the composite spacer layer200are exposed by the hard masks230, and are free from coverage by the material of the hard masks230. In some embodiments, the hard masks230may remain in contact with the sidewalk of the vertical portion200B of the composite spacer layer200and the top surfaces of the second horizontal portions200C of the composite spacer layer200.

Reference is made toFIGS.9A and9B, in whichFIG.9Bis a cross-sectional view along line A-A ofFIG.9A. The middle layer214and the bottom layer212of the tri-layer photoresist210are removed. In some embodiments, the middle layer214and the bottom layer212may be removed by suitable process, such as etching.

Reference is made toFIGS.10A and10B, in whichFIG.10Bis a cross-sectional view along line A-A ofFIG.10A. An anisotropic etching process is performed to remove the first horizontal portions200A and the second horizontal portions200C of the composite spacer layer200to form a plurality of composite spacers205. After the anisotropic etching process, because the first horizontal portions200A and the second horizontal portions200C of the composite spacer layer200are removed, the top surfaces of the amorphous silicon layer175are exposed, and portions of the TEOS layer170are exposed. In some embodiments, the composite spacers205may include the remaining portions of the vertical portions200B of the composite spacer layer200, and thus the composite spacers205may include a vertical portion205B in contact with the sidewalls of the amorphous silicon layer175. In some embodiments, after the anisotropic etching process, the top surfaces of the hard masks230may be substantially level with top surfaces of the vertical portions205B of the composite spacer layer205.

Moreover, during the anisotropic etching process, the hard masks230can act as a protective layer to protect the underlying second horizontal portions200C of the composite spacer layer200. Accordingly, parts of the second horizontal portions200C of the composite spacer layer200that are under and protected by the hard masks230may remain after the anisotropic etching process. As a result, the composite spacers205may also include horizontal portions205C that are vertically below the hard masks230. Stated another way, the horizontal portions205C of the composite spacers205only exist below the hard masks230.

Reference is made toFIGS.11A and11B, in whichFIG.11Bis a cross-sectional view along line A-A ofFIG.11A. A photoresist240is formed over the substrate100. In some embodiments, the photoresist240may include openings O2that expose portions of the amorphous silicon layer175(seeFIGS.10A and10B). Next, an etching process is performed to remove the portions of the amorphous silicon layer175that are exposed by the openings O2of the photoresist240. Accordingly, after the portions of the amorphous silicon layer175are removed, portions of the TEOS layer170are exposed.

Reference is made toFIGS.12A and12B, in whichFIG.12Bis a cross-sectional view along line A-A′ ofFIG.12A. The photoresist240is removed. Next, an etching process is performed, by using the remaining portions of the amorphous silicon layer175, the composite spacers205, and the hard masks230as etch mask, to pattern the TEOS layer170and the titanium nitride layer165. After the etching process, the patterned TEOS layer170and the patterned titanium nitride layer165may include openings O3that expose the ARC160.

As mentioned above, because the second spacer layer190has better crystalline quality than the first spacer layer180, the second spacer layer190may have higher etching resistance to the etching process ofFIGS.12A and12B. Stated another way, the second spacer layer190and the hard masks230may provide sufficient etching selectivity during the etching process. In some embodiments, the hard masks230may be consumed during the etching process and may not have enough height as an etch mask. However, the second spacer layer190, which has etching selectivity to the hard masks230, may provide sufficient etching resistance to the etching process, and thus will reduce process defect at smaller line width and critical dimension. Accordingly, the process reliability and the device performance may be improved. Stated differently, in some embodiments, this etching step etches the second spacer layer190at a lower etch rate than it etches the first spacer layer180and/or the hard masks230.

Reference is made toFIGS.13A and13B, in whichFIG.13Bis a cross-sectional view along line A-A ofFIG.13A. The remaining portions of the amorphous silicon layer175, the composite spacers205, and the hard masks230are removed. In some embodiments, the amorphous silicon layer175, the composite spacers205, and the hard masks230may be removed by suitable etching process, such as dry etch, wet etch, or combinations thereof.

Reference is made toFIGS.14A and14B, in whichFIG.14Bis a cross-sectional view along line A-A ofFIG.14A. An etching process is performed, by using the patterned TEOS layer170and the patterned titanium nitride layer165as etch mask, to pattern the ARC layer160and the ILD layer150. After the etching process, the patterned ARC layer160and the patterned ILD layer150may include openings O4that expose the ILD layer140and the via plugs145.

Reference is made toFIGS.15A and15B, in whichFIG.15Bis a cross-sectional view along line A-A ofFIG.15A. The patterned TEOS layer170, the patterned titanium nitride layer165, and the patterned ARC layer160are removed. In some embodiments, the patterned TEOS layer170, the patterned titanium nitride layer165, and the patterned ARC layer160are removed may be removed by suitable etching process, such as dry etch, wet etch, or combinations thereof.

Reference is made toFIGS.16A and16B, in whichFIG.16Bis a cross-sectional view along line A-A ofFIG.16A. Metal lines250are formed in the openings O4of the patterned ILD layer150, and may be electrically connected to the via plugs145. In some embodiments, the metal lines250may be formed by, for example, depositing a conductive material over the ILD layer150and filling the openings O4of the ILD layer150, and performing a CMP process to remove excess conductive material until the ILD layer150is exposed. In some embodiments, the metal lines250may include Ti, W, Co, Cu, Al, Mo, MoW, W, TiN, TaN, WN, combinations thereof, or other suitable conductive material.

FIGS.17A to26Bshow various stages of a sequential manufacturing operation of a semiconductor device according to an embodiment of the present disclosure. Some elements ofFIGS.17A to26Bare similar to those described inFIGS.1A to16B, such elements are labeled the same, and relevant details will not be repeated for simplicity. It is understood that additional operations can be provided before, during, and after the processes shown byFIGS.17A to26B, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. Material, configuration, dimensions and/or processes the same as or similar to the foregoing embodiments described withFIGS.17A to26Bmay be employed in the following embodiments, and detailed explanation thereof may be omitted.

Reference is made toFIGS.17A and17B, in whichFIG.17Bis a cross-sectional view along line A-A ofFIG.17A.FIGS.17A and17Billustrate deposition of first and second spacer layers, as previously described in the step ofFIGS.3A and3B.FIGS.17A and17Bare different fromFIGS.3A and3B, at least in that a second spacer layer300is formed overfilling the spaces defined by the amorphous silicon layer175, instead of formed in a conformal manner. Stated differently, the second spacer layer300is non-conformal to the underlying first spacer layer180. The material and the formation method of the second spacer layer300may be similar to those of the second spacer layer190discussed inFIGS.1A to16B. In some embodiments, the second spacer layer300may be formed by a timed deposition process until an entirety of the top surface of the second spacer layer300is higher than the topmost position of the first spacer layer180. In some embodiments, a CMP process may be optionally performed to planarize the top surface of the second spacer layer300.

Reference is made toFIGS.18A and18B, in whichFIG.18Bis a cross-sectional view along line A-A ofFIG.18A. The second spacer layer300is etched back to lower the top surface of the second spacer layer300. In greater details, the top surface of the second spacer layer300may be lowered to a position under the topmost position of the first spacer layer180. In some embodiments, the top surface of the second spacer layer300may be lowered to a position under the top surface of the amorphous silicon layer175. In some embodiments, the first spacer layer180and the second spacer layer300can also be collectively referred to as a composite spacer. In some embodiments, the second spacer layer300is etched back by a selective etching process that uses an etchant that etches the second spacer layer300at a faster etch rate than etching the first spacer layer180.

In some embodiments, the first spacer layer180may include first horizontal portions180A horizontally extending along top surfaces of the amorphous silicon layer175, vertical portions180B vertically extending along sidewalls of the amorphous silicon layer175, and second horizontal portions180C horizontally extending along top surfaces of the TEOS layer170. During the etch back process, portions of the second spacer layer300are removed to expose the first horizontal portions180A of the first spacer layer180, and expose upper parts of the vertical portions180B of first spacer layer180. After the etch back process, the remaining portions of the second spacer layer300still cover the second horizontal portions180C of the first spacer layer180.

Reference is made toFIGS.19A and19B, in whichFIG.19Bis a cross-sectional view along line A-A ofFIG.19A. The structure inFIGS.18A and18Bmay undergo the processes discussed inFIGS.4A to6B, and the resulting structure is shown inFIGS.19A and19B. A photoresist210, which includes a bottom layer (BL)212and a middle layer (ML)214, is formed over the substrate100. In some embodiments, the photoresist210includes openings O1that expose portions of the first spacer layer180and the second spacer layer300.

Reference is made toFIGS.20A and20B, in whichFIG.20Bis a cross-sectional view along line A-A ofFIG.20A. A hard mask layer220is formed over the photoresist210and filling the openings O1of the photoresist210. Accordingly, the hard mask layer220may be formed in contact with the first spacer layer180and the second spacer layer300. In greater details, the hard mask layer220may be in contact with the first horizontal portions180A of the first spacer layer180, the upper parts of the vertical portions180B of the first spacer layer180, and the top surface of the second spacer layer300. In some embodiments, the second horizontal portions180C of the first spacer layer180are separated from the hard mask layer220by the second spacer layer300.

Reference is made toFIGS.21A and21B, in whichFIG.21Bis a cross-sectional view along line A-A ofFIG.21A. The hard mask layer220(seeFIGS.20A and20B) is etched back to lower a top surface of the hard mask layer220to form a plurality of hard masks230. In some embodiments, the top surface of the hard mask layer220may be lowered to a position that is below a topmost position of the first horizontal portions180A of the first spacer layer180. In some embodiments, the top surfaces of the hard masks230may be lower than the topmost position of the first spacer layer180, while higher than the topmost position of the second spacer layer300. In some other embodiments, the top surface of the hard mask layer220may be lowered to a position that is substantially level with the topmost position of the first spacer layer180.

Reference is made toFIGS.22A and22B, in whichFIG.22Bis a cross-sectional view along line A-A ofFIG.22A. The photoresist210is removed. In some embodiments, the photoresist210may be removed by suitable process, such as etching.

Reference is made toFIGS.23A and23B, in whichFIG.23Bis a cross-sectional view along line A-A ofFIG.23A. An anisotropic etching process is performed to remove the first horizontal portions180A and the second horizontal portions180C of the first spacer layer180to form a plurality of spacers185, in which the spacers185includes the remaining portions of the first spacer layer180. In some embodiments, the spacers185include vertical portions185B along sidewalls of the amorphous silicon layer175. After the anisotropic etching process, because the first horizontal portions180A and the second horizontal portions180C of the first spacer layer180are removed, the top surfaces of the amorphous silicon layer175are exposed, and portions of the TEO layer170are exposed. In some embodiments, after the anisotropic etching process, the top surfaces of the hard masks230may be substantially level with top surfaces of the spacers185.

Moreover, during the anisotropic etching process, the hard masks230can act as a protective layer to protect the underlying second spacer layer300and the second horizontal portions180C of the first spacer layer180. Accordingly, parts of the second horizontal portions180C of the first spacer layer180that are under and protected by the hard masks230may remain after the anisotropic etching process. As a result, the spacers185may also include the horizontal portions185C that are vertically below the hard masks230and the second spacer layer300. Stated another way, the second spacer layer300is between the horizontal portions185C of the spacers185and the hard masks230.

Reference is made toFIGS.24A and24B, in whichFIG.24Bis a cross-sectional view along line A-A ofFIG.24A. A photoresist240is formed over the substrate100. In some embodiments, the photoresist240may include openings O2that expose portions of the amorphous silicon layer175(seeFIGS.23A and23B). Next, an etching process is performed to remove the portions of the amorphous silicon layer175that are exposed by the openings O2of the photoresist240. Accordingly, after the portions of the amorphous silicon layer175are removed, portions of the TEOS layer170are exposed.

Reference is made toFIGS.25A and25B, in which25B is a cross-sectional view along line A-A ofFIG.25A. The photoresist240is removed. Next, an etching process is performed, by using the remaining portions of the amorphous silicon layer175, the spacers185, and the hard masks230as etch mask, to pattern the TEOS layer170and the titanium nitride layer165. After the etching process, the patterned TEOS layer170and the patterned titanium nitride layer165may include openings O3that expose the ARC160.

Reference is made toFIGS.26A and26B, in whichFIG.26Bis a cross-sectional view along line A-A ofFIG.26A. The remaining portions of the amorphous silicon layer175, the spacers185, and the hard masks230are removed. In some embodiments, the amorphous silicon layer175, the composite spacers205, and the hard masks230may be removed by suitable etching process, such as dry etch, wet etch, or combinations thereof.

It is noted that the structure shown inFIGS.26A and26Bmay further undergo the processes discussed inFIGS.14A to16B, wherein the ILD layer150is patterned to form trenches extending in the ILD layer150, and then metal lines250are formed in the trenches in the ILD layer150. The resultant structure is exemplarily illustrated inFIGS.16A and16B. Relevant details will not be repeated for simplicity.

FIGS.27A to35Bshow various stages of a sequential manufacturing operation of a semiconductor device according to an embodiment of the present disclosure. Some elements ofFIGS.27A to35Bare similar to those described inFIGS.1A to16B, such elements are labeled the same, and relevant details will not be repeated for simplicity. It is understood that additional operations can be provided before, during, and after the processes shown byFIGS.27A to35B, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. Material, configuration, dimensions and/or processes the same as or similar to the foregoing embodiments described withFIGS.27A to35Bmay be employed in the following embodiments, and detailed explanation thereof may be omitted.

Reference is made toFIGS.27A and27B, in whichFIG.27Bis a cross-sectional view along line A-A ofFIG.27A.FIGS.27A and27Billustrates an intermediate stage following the step shown inFIGS.2A and2B, wherein a photoresist210, which includes a bottom layer (BL)212and a middle layer (ML)214, has been formed over the first spacer layer180. In some embodiments, the photoresist210is patterned to form openings O1that expose portions of the first spacer layer180.

Reference is made toFIGS.28A and28B, in whichFIG.28Bis a cross-sectional view along line A-A ofFIG.28A. A second spacer layer350is formed in the openings O1of the photoresist210and over the exposed portions of the first spacer layer180. In some embodiments, the second spacer layer350is formed over the exposed portions of the first spacer layer180via a bottom-up manner. That is, the deposition rate of the second spacer layer350is higher on the surfaces of the first spacer layer180than on the surfaces of the photoresist210. In some embodiments, the bottom-up deposition may be achieved by, for example, treating the first spacer layer180to increase deposition rate of a material of the second spacer layer350on the treated first spacer layer180and/or treating the photoresist210to reduce the deposition rate of a material of the second spacer layer350on the treated photoresist350. In some other embodiments, the second spacer layer350may be formed by, for example, depositing a conformal layer of second spacer material over the structure shown inFIGS.27A and27B, followed by a directional etching process performed using directional ions directed toward the substrate100at tilt angles. Accordingly, in some embodiments, the second spacer layer350may only cover the exposed portions of the first spacer layer180, while the surfaces of the photoresist210may be free from coverage by the second spacer layer350. In some embodiments, the first spacer layer180and the second spacer layer350can also be collectively referred to as a composite spacer.

In some embodiments, the first spacer layer180may include first horizontal portions180A horizontally extending along top surfaces of the amorphous silicon layer175, vertical portions180B vertically extending along sidewalls of the amorphous silicon layer175, and second horizontal portions180C horizontally extending along top surfaces of the TEOS layer170. In some embodiments, the second spacer layer350may covers the first horizontal portions180A, the vertical portions180B, and the second horizontal portions180C of the first spacer layer180that are exposed by the openings O1of the photoresist210.

Reference is made toFIGS.29A and29B, in whichFIG.29Bis a cross-sectional view along line A-A ofFIG.29A. A hard mask layer220is formed over the middle layer214and filling the openings O1of the photoresist210. Accordingly, the hard mask layer220may be formed in contact with the second spacer layer350. In some embodiments, the first spacer layer180is separated from the hard mask layer220by the second spacer layer350.

Reference is made toFIGS.30A and30B, in whichFIG.30Bis a cross-sectional view along line A-A ofFIG.30A. The hard mask layer220(seeFIGS.29A and29B) is etched back to lower a top surface of the hard mask layer220to form a plurality of hard masks230. In some embodiments, the top surface of the hard mask layer220may be lowered to a position that is below a topmost position of the second spacer layer350. In some embodiments, the top surfaces of the hard masks230may be lower than the topmost position of the second spacer layer350, and may be higher than the topmost position of the first spacer layer180. In some other embodiments, the top surface of the hard mask layer220may be lowered to a position that is substantially level with the topmost position of the second spacer layer350of the composite spacer layer200.

Reference is made toFIGS.31A and31B, in whichFIG.31Bis a cross-sectional view along line A-A ofFIG.31A. The photoresist210is removed. In some embodiments, the photoresist210may be removed by suitable process, such as etching.

Reference is made toFIGS.32A and32B, in whichFIG.32Bis a cross-sectional view along line A-A ofFIG.32A. An anisotropic etching process is performed to remove the first horizontal portions180A and the second horizontal portions180C of the first spacer layer180to form a plurality of spacers185, in which the spacers185includes the remaining portions of the first spacer layer180. In some embodiments, the spacers185include vertical portions185B along sidewalls of the amorphous silicon layer175. After the anisotropic etching process, because the first horizontal portions180A and the second horizontal portions180C of the first spacer layer180are removed, the top surfaces of the amorphous silicon layer175are exposed, and portions of the TEOS layer170are exposed. In some embodiments, after the anisotropic etching process, the top surfaces of the hard masks230may be substantially level with top surfaces of the spacers185and the second spacer layer350.

Moreover, during the anisotropic etching process, the hard masks230and the second spacer layer350can act as a protective layer to protect the underlying second horizontal portions180C of the first spacer layer180. Accordingly, parts of the second horizontal portions180C of the first spacer layer180that are under and protected by the hard masks230may remain after the anisotropic etching process. As a result, the spacers185may also include the horizontal portions185C that are vertically below the hard masks230and the second spacer layer350. Stated another way, the second spacer layer300is between the horizontal portions185C of the spacers185and the hard masks230. In some embodiments, the top surfaces of the second spacer layer350are exposed by the spacers185and the hard masks230.

Reference is made toFIGS.33A and33B, in which33B is a cross-sectional view along line A-A ofFIG.33A. A photoresist240is formed over the substrate100. In some embodiments, the photoresist240may include openings O2that expose portions of the amorphous silicon layer175(seeFIGS.32A and32B). Next, an etching process is performed to remove the portions of the amorphous silicon layer175that are exposed by the openings O2of the photoresist240. Accordingly, after the portions of the amorphous silicon layer175are removed, portions of the TEOS layer170are exposed.

Reference is made toFIGS.34A and34B, in whichFIG.34Bis a cross-sectional view along line A-A ofFIG.34A. The photoresist240is removed. Next, an etching process is performed, by using the remaining portions of the amorphous silicon layer175, the spacers185, the second spacer layer350, and the hard masks230as etch mask, to pattern the TEOS layer170and the titanium nitride layer165. After the etching process, the patterned TEOS layer170and the patterned titanium nitride layer165may include openings O3that expose the ARC160.

Reference is made toFIGS.35A and35B, in whichFIG.35Bis a cross-sectional view along line A-A ofFIG.35A. The remaining portions of the amorphous silicon layer175, the spacers185, the second spacer layer350, and the hard masks230are removed. In some embodiments, the amorphous silicon layer175, the composite spacers205, and the hard masks230may be removed by suitable etching process, such as dry etch, wet etch, or combinations thereof.

It is noted that the structure shown inFIGS.35A and35Bmay further undergo the processes discussed inFIGS.14A to14B, wherein the ILD layer150is patterned to form trenches extending in the ILD layer150, and then the metal lines250are formed in the trenches in the ILD layer150. The resultant structure is exemplarily illustrated inFIGS.16A and16B. Relevant details will not be repeated for simplicity.

According to the aforementioned embodiments, it can be seen that the present disclosure offers advantages in fabricating semiconductor devices. It is understood, however, that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all embodiments. One advantage is that a bi-layer spacer is used as an etch mask during an etching process. For example, the bi-layer spacer may include a first spacer layer and a second spacer layer over the first spacer layer. Next, a hard mask is formed over the second spacer layer of the bi-layer spacer. The second spacer layer of bi-layer spacer has better crystalline quality than the first spacer layer of the bi-layer spacer. Accordingly, the second spacer layer and the hard mask may provide sufficient etching selectivity during the etching process. In some embodiments, the hard mask may be consumed during the etching process and may not have enough height as an etch mask. However, the second spacer layer, which has etching selectivity to the hard mask, may provide sufficient etching resistance to the etching process, and thus will reduce process defect at smaller line width and critical dimension. Accordingly, the process reliability and the device performance may be improved.

In some embodiments of the present disclosure, a method includes forming a dielectric layer over a substrate; forming a patterned amorphous silicon layer over a dielectric layer; depositing a first spacer layer over the patterned amorphous silicon layer; depositing a second spacer layer over the first spacer layer; forming a photoresist having an opening over the substrate; depositing a hard mask layer in the opening of the photoresist; after depositing the hard mask layer in the opening of the photoresist, removing the photoresist; and performing an etching process to etch the dielectric layer by using the patterned amorphous silicon layer, the first spacer layer, the second spacer layer, and the hard mask layer as an etch mask, wherein the etching process etches the second spacer layer at a slower etch rate than etching the first spacer layer. In some embodiments, the method further includes after removing the photoresist and prior to etching the dielectric layer, performing an anisotropic etching process to remove first horizontal portions of the first spacer layer and the second spacer layer, while leaving second horizontal portions of the first spacer layer and the second spacer layer under the hard mask layer. In some embodiments, the method further includes etching back the hard mask layer to lower a top surface of the hard mask layer to a position lower than a top surface of the second spacer layer. In some embodiments, wherein depositing the second spacer layer is performed after forming the photoresist, and the second spacer layer is deposited in the opening of the photoresist. In some embodiments, wherein the photoresist is formed after depositing the second spacer layer over the first spacer layer. In some embodiments, wherein after removing the photoresist, a first portion of the first spacer layer is exposed and a second portion of the first spacer layer is covered by the second spacer layer. In some embodiments, the method further includes etching back the second spacer layer prior to forming the photoresist. In some embodiments, wherein etching back the second spacer layer is performed until a top surface of the first spacer layer is exposed. In some embodiments, wherein depositing the hard mask layer is performed after etching back the second spacer layer, such that the hard mask layer is in contact with the first spacer layer.

In some embodiments of the present disclosure, a method includes forming a dielectric layer over a substrate; forming a patterned amorphous silicon layer over a dielectric layer; depositing a first spacer layer over the patterned amorphous silicon layer; depositing a second spacer layer over the first spacer layer to form a bilayer spacer film including the first spacer layer and the second spacer layer; forming a hard mask covering a first horizontal portion of the bilayer spacer film; performing an etching process to remove a second horizontal portion of the bilayer spacer film not covered by the hard mask, wherein the first horizontal portion of the bilayer spacer film and a vertical portion of the bilayer spacer film along a sidewall of the patterned amorphous silicon layer remain after the etching process is complete; and etching the dielectric layer by using the remaining first horizontal portion and vertical portion of the bilayer spacer film and the hard mask as an etch mask. In some embodiments, wherein forming the hard mask comprises forming a photoresist having an opening over the second spacer layer; depositing a hard mask layer in the opening in the photoresist; and etching back the hard mask layer until the hard mask layer falls below a topmost position of the first spacer layer. In some embodiments, the method further includes after performing the etching process to remove the second horizontal portion of the bilayer spacer film, forming a photoresist having an opening exposing a portion of the patterned amorphous silicon layer; and etching the exposed portion of the patterned amorphous silicon layer. In some embodiments, wherein the hard mask is separated from the first spacer layer by the second spacer layer. In some embodiments, wherein the second spacer layer is in contact with sidewalls and a bottom surface of the hard mask. In some embodiments, the method further includes etching back the second spacer layer prior to forming the hard mask. In some embodiments, wherein the hard mask is in contact with the first spacer layer and the second spacer layer.

In some embodiments of the present disclosure, a method includes forming a dielectric layer over a substrate; forming a patterned amorphous silicon layer over a dielectric layer; depositing a first spacer layer over the patterned amorphous silicon layer; forming a photoresist having an opening exposing a portion of the first spacer layer; depositing a second spacer layer in the opening of the photoresist and over the first spacer layer; forming a hard mask layer in the opening of the photoresist and over second spacer layer; after forming the hard mask in the opening of the photoresist, removing the photoresist; and etching the dielectric layer by using the first spacer layer, the second spacer layer, and the hard mask layer as an etch mask. In some embodiments, the method further includes etching horizontal portions of the first spacer layer that are exposed by the hard mask after removing the photoresist and prior to etching the dielectric layer. In some embodiments, wherein the hard mask layer is in contact with a sidewall of the photoresist. In some embodiments, wherein the first spacer layer is deposited using a plasma-free atomic layer deposition (ALD), and the second spacer layer is deposited using a plasma-enhanced ALD process.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.