Patent ID: 12191370

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for case of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Still further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within +/−10% of the number described, unless otherwise specified. For example, the term “about 5 nm” encompasses the dimension range from 4.5 nm to 5.5 nm.

This application generally relates to semiconductor structures and fabrication processes, and more particularly to integrate circuit (IC) chips having multi-gate transistors with tunable numbers of stacked semiconductor channel layers in different regions suiting different applications on one chip. A multi-gate transistor generally refers to a device having a gate structure, or portion thereof, disposed over more than one side of a channel region. Multi-bridge-channel (MBC) transistors are examples of multi-gate devices that have become popular and promising candidates for high performance and low leakage applications. An MBC transistor has a gate structure that can extend, partially or fully, around a channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel regions, an MBC transistor may also be referred to as a surrounding gate transistor (SGT) or a gate-all-around (GAA) transistor. In various embodiments, at least two gate-all-around (GAA) transistors with different (also referred to tunable or varying) numbers of stacked semiconductor channel layers (also referred to as channel layers) on the same substrate are placed in a core area (e.g., for high-power applications) and an I/O area (for low-leakage applications) of one IC chip, respectively. The tunable numbers of stacked channel layers can be achieved by isolating one or more bottom channel layers from contacting epitaxial source/drain (S/D) features, according to various aspects of the present disclosure.

The details of the structure and fabrication methods of the present disclosure are described below in conjunction with the accompanied drawings, which illustrate a process of making GAA devices, according to some embodiments. A GAA device has vertically-stacked horizontally-oriented channel layers. The channel layer may be referred to as “nanostructure” or “nanosheet,” which is used herein to designate any material portion with nanoscale, or even microscale dimensions, and having an elongate shape, regardless of the cross-sectional shape of this portion. Thus, the term “nanostructure” or “nanosheet” as used herein designates both circular and substantially circular cross-section elongate material portions, and beam or bar-shaped material portions including for example a cylindrical in shape or substantially rectangular cross-section. GAA devices are promising candidates to take CMOS to the next stage of the roadmap due to their better gate control ability, lower leakage current, and fully FinFET device layout compatibility. For the purposes of simplicity, the present disclosure uses GAA devices as an example. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures (such as other types of MBC transistors) for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein.

Embodiments of the present disclosure offer advantages over the existing art, though it is understood that other embodiments may offer different advantages, not all advantages are necessarily discussed herein, and no particular advantage is required for all embodiments. For example, embodiments discussed herein include methods and structures for providing an insulation layer interposing the epitaxial source/drain features and one or more bottom channel layers to adjust the number of available functional channel layers. The insulation layer also interposes the epitaxial source/drain features and the semiconductor substrate thereunder. A gate structure extending around the stacked channel layers also directly engages a top surface of a semiconductor substrate under the bottommost channel layer, which may cause leakage current flowing into the semiconductor substrate. The insulation layer also assists in suppressing the leakage current.

The various aspects of the present disclosure will now be described in more detail with reference to the figures.FIGS.1A and1Billustrate flowcharts of a method100and an alternative method100′, respectively, for forming a semiconductor device. Each method is merely an example and is not intended to limit the present disclosure to what is explicitly illustrated in the method. Additional steps may be provided before, during and after the respective method, and some steps described can be replaced, eliminated, or moved around for additional embodiments of the respective method. Not all steps are described herein in detail for reasons of simplicity. The methods100and100′ are described below in conjunction withFIGS.2-24D, which illustrate diagrammatic perspective views and fragmentary cross-sectional views of a workpiece200at different stages of fabrication according to embodiments of the methods100and100′. Because a semiconductor device will be formed from the workpiece200, the workpiece200may be referred to as a semiconductor device200or a device200as the context requires.FIGS.2-4are diagrammatic perspective views of the workpiece200at various stages of fabrication according to some embodiments. AmongFIGS.5A-24D, for better illustration of various aspects of the present disclosure, each of the figures ending with the capital letter A illustrates a fragmentary cross-sectional view in a channel region (i.e., as illustrated inFIG.4, a cut along A-A line in a channel region along a lengthwise direction of gate structures and perpendicular to a lengthwise direction of channel layers) of the to-be-formed transistor(s). Each of the figures ending with the capital letter B illustrates a fragmentary cross-sectional view of a source/drain region (i.e., as illustrated inFIG.4, a cut along B-B line in a source/drain region that is perpendicular to the lengthwise direction of channel layers) of the to-be-formed transistor(s). Each of the figures ending with the capital letter C illustrates a fragmentary cross-sectional view along a first fin in a first region (i.e., as illustrated inFIG.4, a cut along C-C line along a first fin in a first region). Each of the figures ending with the capital letter D illustrates a fragmentary cross-sectional view along a second fin in a second region (i.e., as illustrated inFIG.4, a cut along D-D line along a second fin in a second region). ThroughoutFIGS.2-24D, the X direction, the Y direction, and the Z direction are perpendicular to one another and are used consistently. Additionally, throughout the present disclosure, like reference numerals are used to denote like features. Embodiments of the present disclosure are described using an MBC transistor structure, particularly, a GAA transistor structure, which is for illustration purpose only and should not be construed as limiting the scope of the present disclosure; for example, the present disclosure may also be applicable to other multi-gate devices, including FinFET transistors.

Referring toFIGS.1A and2, the method100includes a block102where a workpiece200is received. The workpiece200includes a substrate202. In some embodiments, the substrate202may be a semiconductor substrate such as a silicon (Si) substrate. In some embodiments, the substrate202includes a single crystalline semiconductor layer on at least its surface portion. The substrate202may comprise a single crystalline semiconductor material such as, but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb and InP. Alternatively, the substrate202may include a compound semiconductor and/or an alloy semiconductor. The substrate202may include various layers, including conductive or insulating layers formed on a semiconductor substrate. The substrate202includes a first region204and a second region206. The first region204may be an I/O area that includes I/O cells, ESD cells, and other circuits. Transistors formed in the first region204are for low-power and/or low-leakage applications. The second region206may be a core area that includes high performance computing (HPC) unit, central processing unit (CPU) logic circuits, memory circuits, and other core circuits. Transistors formed in the second region206are for high-power and/or high-speed applications. Generally, transistors in the second region206due to their power-hungry applications need stronger current driving capability than transistors in the first region204. Notably, although in the illustrate embodiment, the regions204and206are depicted as adjacent to each other, it is for illustrative purposes only. In various embodiments, the regions204and206may be adjacent to each other or separated from one another with one or more other regions disposed therebetween, so are the transistors formed in the regions204and206.

Referring toFIG.3, the method100includes a block104(FIG.1A) where one or more epitaxial layers are formed over the substrate202. In some embodiments, an epitaxial stack212is formed over the regions204and206. The epitaxial stack212includes epitaxial layers214of a first composition interposed by epitaxial layers216of a second composition, and a top epitaxial layer214T of the first composition over the top epitaxial layer216. The first and second composition can be different. In an embodiment, the epitaxial layers214are silicon germanium (SiGe) and the epitaxial layers216are silicon (Si). However, other embodiments are possible including those that provide for a first composition and a second composition having different oxidation rates and/or etch selectivity. It is noted that three (3) layers of each of the epitaxial layers214and216are illustrated inFIG.3, which is for illustrative purposes only and not intended to be limiting beyond what is specifically recited in the claims. It can be appreciated that any number of epitaxial layers can be formed in the epitaxial stack212; the number of epitaxial layers depending on the desired number of channel layers for forming transistors. In some embodiments, the number of epitaxial layers216is between 2 and 10.

In some embodiments, the epitaxial layer214has a thickness ranging from about 8 nm to about 12 nm. The epitaxial layers214may be substantially uniform in thickness. In some embodiments, the epitaxial layer216has a thickness ranging from about 8 nm to about 10 nm. In some embodiments, the epitaxial layers216may be substantially uniform in thickness. As described in more detail below, the epitaxial layers216may serve as channel layers (or channel members) for subsequently-formed GAA transistors and its thickness is chosen based on device performance considerations. The epitaxial layers214may serve to reserve a spacing (or referred to as a gap) between adjacent channel layers and its thickness is chosen based on device performance considerations. The epitaxial layers214would be subsequently removed and may also be referred to as the sacrificial layers214. Like the epitaxial layers214, the top epitaxial layer214T may be formed of silicon germanium (SiGe). The top epitaxial layer214T may be thicker than the epitaxial layers214and function to protect the epitaxial stack212from damages during fabrication processes. In some instances, a thickness of the top epitaxial layer214T may be between about 20 nm and about 40 nm.

By way of example, epitaxial growth of the epitaxial stack212may be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and/or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layers, such as the epitaxial layers216, include the same material as the substrate202, such as silicon (Si). In some embodiments, compositions of the top epitaxial layer214T and the epitaxial layers214are substantially the same. In some embodiments, the epitaxial layers214and216include a different material than the substrate202. As stated above, in at least some examples, the epitaxial layer214includes an epitaxially grown Si1-xGexlayer (e.g., x is about 25˜55%) and the epitaxial layer216includes an epitaxially grown Si layer. Alternatively, in some embodiments, either of the epitaxial layers214and216may include other materials such as germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or combinations thereof. As discussed, the materials of the epitaxial layers214and216may be chosen based on providing differing oxidation and etch selectivity properties. In various embodiments, the epitaxial layers214and216are substantially dopant-free (i.e., having an extrinsic dopant concentration from about 0 cm−3to about 1×1017cm−3), where for example, no intentional doping is performed during the epitaxial growth process.

Further, a mask layer218is formed over the epitaxial stack212. In some embodiments, the mask layer218includes a first mask layer218A and a second mask layer218B. The first mask layer218A is a pad oxide layer made of silicon oxide, which can be formed by a thermal oxidation process. The second mask layer218B is made of silicon nitride (SiN), which is formed by chemical vapor deposition (CVD), including low pressure CVD (LPCVD) and plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable process.

Referring toFIG.4andFIGS.5A-5D, the method100includes a block106(FIG.1A) where the epitaxial stack212are patterned to form a first semiconductor fin220-1in the first region204and a second semiconductor fin220-2in the second region206(collectively referred to as fins220), as shown inFIG.4andFIGS.5A-5D. In various embodiments, each of the fins220includes an upper portion220A (also termed as epitaxial portion220A) of the interleaved epitaxial layers214/216and the top epitaxial layer214T, and a base portion220B that is formed by patterning a top portion of the substrate202. The base portion220B still has a fin-shape protruding from the substrate202and is also termed as the fin-shape base220B. The mask layer218is patterned into a mask pattern by using patterning operations including photolithography and etching. In some embodiments, operations at the block106patterns the epitaxial stack212using suitable processes including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a material layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the epitaxial stack212in an etching process, such as a dry etch (e.g., reactive ion etching), a wet etch, and/or other suitable process, through openings defined in the patterned mask layer218. The stacked epitaxial layers214and216are thereby patterned into fins220with trenches between adjacent fins. Each of the fins220protrudes upwardly in the Z-direction from the substrate202and extends lengthwise in the Y-direction. InFIG.4, two (2) fins220are spaced apart along the X-direction with one fin disposed above the first region204and one fin disposed above the second region206. But the number of the fins is not limited to two, and may be as small as one or more than two. Notably, although in the illustrate embodiment, the two fins220are depicted as adjacent to each other, it is for illustrative purposes only. In various embodiments, the fins220may be adjacent to each other or separated from one another with other fins disposed therebetween.

Referring toFIGS.6A-6D, the method100includes a block108(FIG.1A) where the trenches between adjacent fins220are filled with a dielectric material to form an isolation feature222. The isolation feature222may include one or more dielectric layers. Suitable dielectric materials for the isolation feature222may include silicon oxides, silicon nitrides, silicon carbides, fluorosilicate glass (FSG), low-K dielectric materials, and/or other suitable dielectric materials. The dielectric material may be deposited by any suitable technique including thermal growth, CVD, HDP-CVD, PVD, ALD, and/or spin-on techniques. Then, a planarization operation, such as a chemical mechanical polishing (CMP) method, is performed such that the upper surface of the top epitaxial layer214T is exposed from the isolation feature222. Operations at the block108subsequently recesses the isolation features222to form shallow trench isolation (STI) features (also denoted as STI features222). Any suitable etching technique may be used to recess the isolation features222including dry etching, wet etching, RIE, and/or other etching methods, and in an exemplary embodiment, an anisotropic dry etching is used to selectively remove the dielectric material of the isolation features222without etching the fins220. In the illustrated embodiment, the mask layer218is removed by a CMP process performed prior to the recessing of the isolation features222. In some embodiments, the mask layer218is removed by an etchant used to recess the isolation features222. In the illustrated embodiment, the STI feature222is disposed on sidewalls of the fin-shape base220B. A top surface of the STI feature222may be coplanar with a bottom surface of the epitaxial portion220A (or a top surface of the fin-shape base220B) or below the bottom surface of the epitaxial portion220A (or the top surface of the fin-shape base220B) for about 1 nm to about 10 nm. In some embodiments, a liner layer223is blanket deposited over the fins220before depositing the isolation feature222. In some embodiments, the liner layer223is made of SiN or a silicon nitride-based material (e.g., SiON, SiCN or SiOCN). Then, as shown inFIGS.6A and6B, liner layer223is recessed so that the epitaxial portion220A (and a top portion of the fin-shape base220B in the illustrated embodiment) of the fins220are exposed.

Referring toFIGS.7A-7D, the method100includes a block110(FIG.1A) where a cladding layer226is deposited on sidewalls of the fins220. In some embodiments, the cladding layer226may have a composition similar to that of the epitaxial layers214or the top epitaxial layer214T. In one example, the cladding layer226may be formed of silicon germanium (SiGe). Their common composition allows selective and simultaneous removal of the epitaxial layers214and the cladding layer226in a subsequent etching process. In some embodiments, the cladding layer226may be conformally and epitaxially grown as a blanket layer on the workpiece200using vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE). Depending on the extent of the selective growth of the cladding layer226, an etch-back process may be performed to expose the isolation feature222.

Referring toFIGS.8A-8D, the method100includes a block112(FIG.1A) where dielectric fins228are formed in trenches between the fins220. An example process to form the dielectric fins228includes conformally depositing a first dielectric layer230and subsequently depositing a second dielectric layer232in trenches between the fins220. The second dielectric layer232is surrounded by the first dielectric layer230. The first dielectric layer230may be conformally deposited using CVD, ALD, or a suitable method. The first dielectric layer230lines the sidewalls and the bottom surfaces of the trenches between the fins220. The second dielectric layer232is then deposited over the first dielectric layer230using CVD, high density plasma CVD (HDPCVD), and/or other suitable process. In some instances, a dielectric constant of the second dielectric layer232is smaller than that of the first dielectric layer230. The first dielectric layer230may include silicon, silicon nitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium aluminum oxide, hafnium oxide, or a suitable dielectric material. In one embodiment, the first dielectric layer230includes aluminum oxide. The second dielectric layer232may include silicon oxide, silicon carbide, silicon oxynitride, silicon oxycarbonitride, or a suitable dielectric material. In one embodiment, the second dielectric layer232includes silicon oxide. The dielectric layers230and232are then etched back. The etch back process may include a dry etching process that uses oxygen, nitrogen, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCl3), a bromine-containing gas (e.g., HBr and/or CHBr3), an iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof. Subsequently, a third dielectric layer234is deposited above the dielectric layers230and232using CVD, high density plasma CVD (HDPCVD), and/or other suitable process. The third dielectric layer234includes a high-K dielectric material (e.g., k>7) and is also referred to as the high-K dielectric layer234. In some embodiments, the high-K dielectric layer234may include hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium aluminum oxide (HfAlOx), hafnium silicate (HfSiOx), aluminum oxide (Al2O3), or other suitable high-K dielectric material. After the deposition of the dielectric layer234, the workpiece200is planarized using a chemical mechanical polishing (CMP) process to expose the top epitaxial layer214T. As shown inFIGS.8A and8B, upon conclusion of the CMP process, the dielectric layers230,232, and234collectively define the dielectric fins228between the fins220. The dielectric fins228may also be referred to as hybrid fins228.

Referring toFIGS.9A-9D, the method100includes a block114(FIG.1A) where the top epitaxial layer214T in the fins220are removed. At the block114, the workpiece200is etched to selectively remove the top epitaxial layer214T and a portion of the cladding layer226to expose the topmost epitaxial layer216, without substantially damaging the dielectric fins228. In some instances, because the top epitaxial layer214T and the cladding layer226are formed of silicon germanium (SiGe), the etching process at the block114may be selective to silicon germanium (SiGe). For example, the cladding layer226and the top epitaxial layer214T may be etched using a selective wet etching process that includes ammonium hydroxide (NH4OH), hydrogen fluoride (HF), hydrogen peroxide (H2O2), or a combination thereof. After the removal of the top epitaxial layer216T and a portion of the cladding layer226, the dielectric fins224, particularly the third dielectric layer234, rise above the topmost epitaxial layer216.

Referring toFIGS.10A-10D, the method100includes a block116(FIG.1A) where a dummy gate stacks240are formed over the channel regions of the fins220. In some embodiments, a gate replacement process (or gate-last process) is adopted where the dummy gate stack240serves as a placeholder for functional gate structures. Other processes and configuration are possible. In the illustrated embodiment, the dummy gate stack240includes a dummy dielectric layer and a dummy electrode disposed over the dummy dielectric layer. For patterning purposes, a gate top hard mask242is deposited over the dummy gate stack240. The gate top hard mask242may be a multi-layer and include a silicon nitride mask layer242A and a silicon oxide mask layer242B over the silicon nitride mask layer242A. The regions of the fins220underlying the dummy gate stack240may be referred to as channel regions. Each of the channel regions in either the fin220-1or the fin220-2is sandwiched between two source/drain regions for source/drain formation. In an example process, the dummy dielectric layer in the dummy gate stack240is blanket deposited over the workpiece200by CVD. A material layer for the dummy electrode is then blanket deposited over the dummy dielectric layer. The dummy dielectric layer and the material layer for the dummy electrode are then patterned using photolithography processes to form the dummy gate stack240. In some embodiments, the dummy dielectric layer may include silicon oxide and the dummy electrode may include polycrystalline silicon (polysilicon).

Referring toFIGS.11A-11D, the method100includes a block118(FIG.1A) where sidewall spacers244are formed on sidewall of the dummy gate stack240. In some embodiments, the sidewall spacers244may have a thickness between about 2 nm and about 10 nm. In some embodiments, the sidewall spacers244may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, a low-K material, and/or combinations thereof. In some embodiments, the sidewall spacers244include multiple layers, such as a liner spacer layer244A and a main spacer layer244B. By way of example, the sidewall spacers244may be formed by conformally depositing a dielectric material over the device200using processes such as a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, an ALD process, a PVD process, or other suitable process. Following the conformal deposition of the dielectric material, portions of the dielectric material used to form the sidewall spacers244may be etched-back to expose portions of the fins220not covered by the dummy gate stack240(e.g., in source/drain regions). In some instances, the etch-back process removes portions of dielectric material used to form the sidewall spacers244along a top surface of the dummy gate stack240, thereby exposing the gate top hard mask242. In some embodiments, the etch-back process may include a wet etch process, a dry etch process, a multiple-step etch process, and/or a combination thereof. It is noted that after the etch-back process, the sidewall spacers244remain disposed on sidewalls of the dummy gate stack240.

Referring toFIGS.12A-12D, the method100includes a block120(FIG.1A) where the source/drain regions of the fins220are recessed to form source/drain recesses250-1in the first region204and source/drain recesses250-2in the second region206(collectively as source/drain recesses250). With the dummy gate stack240and the sidewall spacers244serving as an etch mask, the workpiece200is anisotropically etched to form the source/drain recesses250over the source/drain regions of the fins220. In some embodiments, operations at the block120remove the epitaxial layers214and216, the cladding layer226, as well as a top portion of the fin-shape base220B from the source/drain regions, thereby exposing the isolation feature222in the source/drain recesses250. In the illustrated embodiment, the source/drain recesses250extend into the fin-shape base220B and are below a top surface of the isolation feature222. The anisotropic etch at the block120may include a dry etching process. For example, the dry etching process may implement hydrogen, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCl3), a bromine-containing gas (e.g., HBr and/or CHBr3), an iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof.

Referring toFIGS.13A-13D, the method100includes a block122(FIG.1A) where inner spacers252are formed on lateral ends of the epitaxial layers214. In some embodiments, a lateral etching (or horizontal recessing) is performed to recess the epitaxial layers214to form cavities on lateral ends of the epitaxial layers214. The amount of etching of the epitaxial layers214may range from about 2 nm to about 10 nm. When the epitaxial layers214are SiGe, the lateral etching process may use an etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solutions. Subsequently, an insulating layer is deposited in the source/drain recesses250and fill the cavities on lateral ends of the epitaxial layers214. The insulating layer may include a dielectric material, such as SiN, SiOC, SiOCN, SiCN, SiO2, and/or other suitable material. In some embodiments, the insulating layer is conformally deposited, for example, by ALD or any other suitable method. After the conformal deposition of the insulating layer, an etch-back process is performed to partially remove the insulating layer from outside of the cavities. By this etching the insulating layer remains substantially within the cavities, thereby forming the inner spacers252.

Referring toFIGS.14A-14D, the method100includes a block124(FIG.1A) where a base epitaxial layer254is epitaxially grown from the recessed top surface of the fin-shape base220B in both the first region204and the second region206. By way of example, epitaxial growth of the base epitaxial layer254may be performed by vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and/or other suitable processes. In some embodiments, the base epitaxial layer254include the same material as the substrate202, such as silicon (Si). In some alternative embodiments, the base epitaxial layer254includes a different semiconductor material than the substrate202, such as silicon germanium (SiGe). As shown inFIG.14B, the base epitaxial layer254may exhibit faceted growth when it raises above the top surface of the isolation feature222, such that a width of the base epitaxial layer254above the isolation feature222is larger than a width of the fin-shape base220B above the isolation features222(under the dummy gate stack240). In some embodiments, the base epitaxial layer254is substantially dopant-free (i.e., having an extrinsic dopant concentration from about 0 cm−3to about 1×1017cm−3). As a comparison, in one instance, the fin-shape base220B is lightly doped and has a higher doping concentration than the base epitaxial layer254. Referring toFIGS.14C and14D, the growth of the base epitaxial layer254is under time control such that the top surface of the base epitaxial layer254is above the top surface of the fin-shape base220B under the dummy gate stack240. In other words, the base epitaxial layer254partially covers sidewalls of the bottommost inner spacers252in the illustrated embodiment.

Referring toFIGS.15A-15D, the method100includes a block126(FIG.1A) where an insulation layer256is formed over the base epitaxial layer254in both the first region204and the second region206. In some embodiments, the insulation layer256includes silicon oxide (SiO2), aluminum oxide (AlOx), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbon oxynitride (SiCON), silicon carbide (SiC), silicon oxycarbide (SiOC), or a combination thereof. The insulation layer256insulates the base epitaxial layer254from contacting epitaxial source/drain features to be formed in subsequent processes to suppress leakage current into the buck substrate. In some embodiments, the insulation layer256is first deposited in the source/drain recesses250using a plasma-enhanced chemical vapor deposition (PECVD) process, covering the base epitaxial layer254and sidewalls of the source/drain recesses250. Since deposition under a PECVD process usually forms a deposited layer thicker in a bottom portion of a recess but thinner on its sidewalls, an etch-back process is subsequently performed to remove the insulation layer256from sidewalls of the source/drain recesses250and also slightly recess the insulation layer256to a determined height h1(e.g., by controlling the etching time), such that sidewalls of the bottommost epitaxial layer216are fully covered by the insulation layer256, as shown inFIGS.15C and15D. In some embodiments, the height h1ranges from about 20 nm to about 28 nm. The removing of the insulation layer256from sidewalls of the source/drain recesses250may include a suitable etching process, such as a dry etching process, a wet etching process, or an RIE process. In various embodiments, a top surface of the insulation layer256is below a bottom surface of the second epitaxial layer216to the bottom. Referring toFIG.15B, air gaps258may be trapped at corner regions of the source/drain recesses250, being capped by the insulation layer256. A height h2of the air gaps258may range from about 4 nm to about 6 nm. The term “air gap” is used to describe a void defined by surrounding substantive features, where a void may contain air, nitrogen, ambient gases, gaseous chemicals used in previous or current processes, or combinations thereof.

In some embodiments, the source/drain recesses250may have a high aspect ratio and to prevent the dielectric material during the deposition of the insulation layer256from capping the top openings of the source/drain recesses250, operations at the block126may adopt a cyclic deposition process. In the cyclic deposition process, operations at the block126alternates between a dielectric material deposition and an etching process to clean up dielectric material from accumulating at edges of the top opening of the source/drain recesses250and gradually grow the thickness of the insulation layer256through cycles. The etching process also helps removing dielectric material from sidewalls of the source/drain recesses250. In some instances, the cyclic deposition process may take from about 1 cycle to about 5 cycles.

Referring toFIGS.16A-16D, the method100includes a block128(FIG.1A) where the insulation layer256is recessed in the second region206in an etch-back process. A mask layer260with an opening exposing the source/drain recesses250-2in the second region206restrains the etching process to the insulation layer256in the second region206. The mask layer260may be a bottom anti-reflective coating (BARC) layer and patterned by using a photolithography process, which may include forming a resist layer on the mask layer260, exposing the resist by a lithography exposure process, performing a post-exposure bake process, developing the resist layer to form the patterned resist layer that exposes part of the mask layer260, patterning the mask layer260, and finally removing the patterned resist layer. The etch back process may use a suitable etching process, such as a dry etching process, a wet etching process, or an RIE process. The etch back process recesses the insulation layer256in the source/drain recesses250-2to a determined height h3(e.g., by controlling the etching time), such that sidewalls of the bottommost epitaxial layer216are fully exposed. In some embodiments, the height h3ranges from about 4 nm to about 6 nm. In various embodiments, a top surface of the insulation layer256in the second region206is below a bottom surface of the bottommost epitaxial layer216and the bottommost inner spacer252is partially exposed, as shown inFIG.16D. Referring toFIG.16B, air gaps258previously trapped at corner regions of the source/drain recesses250-2may be released due to the thinning of the insulation layer256in the source/drain recesses250-2. The mask layer260is then removed in a suitable process such as etching, resist stripping or plasma ashing.

Referring toFIGS.17A-17D, the method100includes a block130(FIG.1A) where first epitaxial source/drain features264-1are formed in the source/drain recesses250-1and second epitaxial source/drain features264-2are formed in the source/drain recesses250-2(collectively as source/drain features264). In an embodiment, forming the epitaxial source/drain features264includes epitaxially growing one or more semiconductor layers by an MBE process, a chemical vapor deposition process, and/or other suitable epitaxial growth processes. In a further embodiment, the epitaxial source/drain features264are in-situ or ex-situ doped with an n-type dopant or a p-type dopant. For example, in some embodiments, the epitaxial source/drain features264include silicon doped with phosphorous for forming epitaxial source/drain features for an n-type FET. In some embodiments, the epitaxial source/drain features264include silicon-germanium (SiGe) doped with boron for forming epitaxial source/drain features for a p-type FET. The semiconductor layers of the epitaxial source/drain features264are selectively grown on different semiconductor surfaces exposed in the source/drain recesses, such as the lateral ends of the epitaxial layers216. Since the insulation layer256covers the top surface of the base epitaxial layer254, the epitaxial growth of the epitaxial source/drain features264does not take place therefrom. In other words, the insulation layer256blocks possible current path from the bottom of the epitaxial source/drain features264to the fin-shape base220B (or substrate202). Accordingly, substrate leakage current is significantly reduced. Further, the epitaxial source/drain features264-1in the first region204has a smaller height and smaller volume than the epitaxial source/drain features264-2in the second region206. The epitaxial source/drain features264-1contacts top epitaxial layers216but not the bottom ones (e.g., the bottommost one as shown inFIG.17C). As a comparison, the epitaxial source/drain feature264-2contacts all available epitaxial layers216in the second region206. Therefore, the GAA transistors formed in the subsequent processes in the first region204would have less functional channel layers than the GAA transistors formed in the second region206.

Reference is made toFIG.17B. The epitaxial source/drain features264may exhibit faceted growth. Air gaps266may be formed between the bottom surface of the epitaxial source/drain feature264-1and the top surface of the insulation layer256. The air gaps266is stacked above the air gaps258. The air gaps266may have a height h4ranges from about 12 nm to about 24 nm. Air gaps268may be formed between the bottom surface of the epitaxial source/drain feature264-2and the top surface of the insulation layer256. The air gaps268are positioned below the air gaps266. Yet since the air gaps268extend upward from corner regions of the source/drain recesses250-2, the air gaps268have the largest height and the largest volume among the air gaps258,266, and268. The air gaps268may have a height h5ranges from about 15 nm to about 30 nm.

Referring toFIGS.18A-18D, the method100includes a block132(FIG.1A) where a contact etch stop layer (CESL)270and an interlayer dielectric layer (ILD)272are deposited on the frontside of the workpiece200. In an example process, the CESL270is first conformally deposited over the workpiece200and then the ILD layer272is deposited over the CESL270. The CESL270may include silicon nitride, silicon oxide, silicon oxynitride, and/or other materials known in the art. The CESL270may be deposited using ALD, plasma-enhanced chemical vapor deposition (PECVD) process and/or other suitable deposition or oxidation processes. In some embodiments, the ILD layer272includes materials such as SiCN, SiON, SiOCN, tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. The ILD layer272may be deposited by spin-on coating, an FCVD process, or other suitable deposition technique. In some embodiments, after formation of the ILD layer272, the workpiece200may be annealed to improve integrity of the ILD layer272. To remove excess materials (including the gate top hard mask242) and to expose top surfaces of the dummy gate stacks240, a planarization process (such as a CMP process) may be performed to the workpiece200to provide a planar top surface. Top surfaces of the dummy gate stacks240are exposed on the planar top surface.

Referring toFIGS.19A-19D, the method100includes a block134(FIG.1B) where the dummy gate stacks240, the epitaxial layers214, and the cladding layer226are selectively removed. The dummy gate stacks240exposed at the conclusion of the block132are removed from the workpiece200by a selective etching process. The selective etching process may be a selective wet etching process, a selective dry etching process, or a combination thereof. In the depicted embodiment, the selective etching process selectively removes the dummy dielectric layer and the dummy electrode without substantially damaging the epitaxial layers216and the sidewall spacers244. The removal of the dummy gate stacks240results in gate trenches274over the channel regions. After the removal of the dummy gate stacks240, the epitaxial layers214, epitaxial layers216, and the cladding layer226in the channel regions are exposed in the gate trenches274. Subsequently, operations at the block134selectively removes the epitaxial layers214and the cladding layer226from the gate trenches274to release the epitaxial layers216. The selective removal of the epitaxial layers214and the cladding layer226may be implemented by selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, the selective wet etching includes ammonium hydroxide (NH4OH), hydrogen fluoride (HF), hydrogen peroxide (H2O2), or a combination thereof (e.g. an APM etch that includes an ammonia hydroxide-hydrogen peroxide-water mixture). In some alternative embodiments, the selective removal includes silicon germanium oxidation followed by a silicon germanium oxide removal. For example, the oxidation may be provided by ozone clean and then silicon germanium oxide removed by an etchant such as NH4OH. The released epitaxial layers216are also denoted as channel layers (or channel members)216, or referred to as nanostructures216due to the nanoscale of the feature. In the depicted embodiment where the channel layers216resemble a sheet or a nanosheet, the channel layer release process may also be referred to as a sheet formation process. The channel layers216may have rounded corners at the conclusion of a sheet formation process. The channel layers216are vertically stacked along the Z direction. All channel layers216are spaced apart from the dielectric fins228for a distance reserved by the cladding layer226. Yet, as shown inFIGS.19C and19D, in the region204, at least the bottommost channel layer216is laterally sandwiched by the insulation layer256and has no contact with the epitaxial source/drain feature264-1. Thus, a GAA transistor formed in the region204have one less functional channel layer than its counterpart in the region206. In an alternative embodiment, the insulation layer256in the region204can be deposited with larger height so as to block two or more bottom channel layers216from contacting the epitaxial source/drain features264-1. Accordingly, a GAA transistor formed in the region204may have two or more functional channel layers less than its counterpart in the region206.

Referring toFIGS.20A-20D, the method100includes a block136(FIG.1B) where gate structures276(also known as functional gate structures276or metal gate structures276) are formed in the gate trenches274to engage each of the channel layer216. Each of the gate structures276includes an interfacial layer278disposed on the channel layers216, a high-k dielectric layer280disposed on the interfacial layer278, and a gate electrode layer282over the gate dielectric layer280. The interfacial layer278and the high-k dielectric layer280are collectively referred to as a gate dielectric layer. The interfacial layer278may include silicon oxide and be formed as result of a pre-clean process. An example pre-clean process may include use of RCA SC-1(ammonia, hydrogen peroxide and water) and/or RCA SC-2(hydrochloric acid, hydrogen peroxide and water). The pre-clean process oxidizes the exposed semiconductive surfaces of the channel layers216and exposed semiconductive surfaces of the fin-shape base202B to form the interfacial layer. That is, the exposed dielectric surfaces of the isolation feature222may be not covered by the interfacial layer278. The high-k dielectric layer280is then deposited over the interfacial layer278using ALD, CVD, and/or other suitable methods. The high-k dielectric layer280also covers the exposed surfaces of the isolation feature222. The high-k dielectric layer280includes high-K dielectric materials. In one embodiment, the high-k dielectric layer280may include hafnium oxide. Alternatively, the high-k dielectric layer280may include other high-K dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3(STO), BaTiO3(BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr) TiO3(BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable material.

After the formation of the high-k dielectric layer280, the gate electrode layer282is deposited over the high-k dielectric layer280. The gate electrode layer282may be a multi-layer structure that includes at least one work function layer and a metal fill layer. By way of example, the at least one work function layer may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), or tantalum carbide (TaC). The metal fill layer may include aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metal materials or a combination thereof. In various embodiments, the gate electrode layer282may be formed by ALD, PVD, CVD, e-beam evaporation, or other suitable process. Although not explicitly shown in the figures, the gate structures276are deposited as a joint gate structure and then etched back until the dielectric fins228separate the joint gate structure into the gate structures276that are separated apart from each other. The dielectric fins228also provide electrical isolation between neighboring gate structures276. The etching back of the gate structures276may include a selective wet etching process that uses nitric acid, hydrochloric acid, sulfuric acid, ammonium hydroxide, hydrogen peroxide, or a combination thereof. In the depicted embodiment, each of the channel layers216is wrapped around by a respective gate structure276. At the conclusion of the block136, the protruding portions of the dielectric fins228, particularly the third dielectric layer234, may be etched back in the channel regions, as illustrated inFIG.20A.

Referring toFIGS.21A-21D, the method100includes a block138(FIG.1A) where a metal cap layer284, a self-aligned cap (SAC) layer286, a gate cut feature288, and a source/drain contact290are formed in the frontside of the workpiece200. In some embodiments, the metal cap layer284may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), ruthenium (Ru), cobalt (Co), or nickel (Ni) and may be deposited using PVD, CVD, or metal organic chemical vapor deposition (MOCVD). In one embodiment, the metal cap layer284includes tungsten (W), such as fluorine-free tungsten (FFW), and is deposited by PVD. The metal cap layer284electrically connects the gate structures276. After the deposition of the metal cap layer284, the SAC layer286is deposited over the workpiece200by CVD, PECVD, or a suitable deposition process. The SAC layer286may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium aluminum oxide, hafnium oxide, or a suitable dielectric material. Photolithography processes and etching processes are then performed to etch the deposited SAC layer286to form gate cut openings to expose the top surfaces of the dielectric fins. Thereafter, a dielectric material is deposited and planarized by a CMP process to form the gate cut feature288in the gate cut openings. The dielectric material for the gate cut feature288may be deposited using HDPCVD, CVD, ALD, or a suitable deposition technique. In some instances, the gate cut feature288may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium aluminum oxide, hafnium oxide, or a suitable dielectric material. In some embodiments, the gate cut feature288and the SAC layer286may have different compositions to introduce etch selectivity. The gate cut feature288and the corresponding dielectric fin228directly thereunder collectively separate the metal cap layer284into segments. The source/drain contact290may include tungsten (W), ruthenium (Ru), cobalt (Co), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), nickel (Ni), or a combination thereof, and may be deposited using PVD, CVD, or metal organic chemical vapor deposition (MOCVD). The workpiece200may also include a silicide feature292between the source/drain contact290and the epitaxial source/drain features264to further reduce contact resistance. The silicide feature292may include titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel-platinum silicide (NiPtSi), nickel-platinum-germanium silicide (NiPtGeSi), nickel-germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), a combination thereof, or other suitable compounds. Alternatively, the silicide formation may be skipped and the source/drain contact290directly contacts the epitaxial source/drain feature264.

The workpiece200may undergo further processing to form various features and regions known in the art. For example, subsequent processing may form various contacts, vias, metal lines, and multilayers interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate202, configured to connect the various features to form a functional circuit that may include one or more multi-gate devices. In furtherance of the example, a multilayer interconnection may include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal lines. The various interconnection features may employ various conductive materials including copper, tungsten, and/or silicide. In one example, a damascene and/or dual damascene process is used to form a copper related multilayer interconnection structure. Moreover, additional process steps may be implemented before, during, and after the method100, and some process steps described above may be replaced or eliminated in accordance with various embodiments of the method100.

Reference is now made toFIG.1B, which demonstrate a flow chart for an alternative embodiment of the method100, denoted as method100′. The method100′ proceeds through operations at the blocks102-124. After operations at the block124, the method100′ proceeds to operations at the blocks125and127. After operations at the block127, the method100′ continues to proceed through operations at the blocks130-138. The method100′ is described below in conjunction withFIGS.22A-24D. Shared operations are not repeated below in the interest of conciseness.

Referring toFIGS.22A-22D, after operations at the block122, the method100′ includes a block125(FIG.1B) where the base epitaxial layer254in the first region204continues to grow for an extra height. In some embodiments, the extra height may range from about 20 nm to about 28 nm, such that the base epitaxial layer254in the first region204fully covers sidewalls of the bottommost epitaxial layer216, as shown inFIG.22C. A mask layer260with an opening exposing the source/drain recess250-1in the first region204restrains the extra epitaxial growth to the first region204, as shown inFIG.22B. The mask layer260may be a bottom anti-reflective coating (BARC) layer and patterned by using a photolithography process, which may include forming a resist layer on the mask layer260, exposing the resist by a lithography exposure process, performing a post-exposure bake process, developing the resist layer to form the patterned resist layer that exposes part of the mask layer260, patterning the mask layer260, and finally removing the patterned resist layer. The extra epitaxial growth of the base epitaxial layer254in the first region204may be performed with substantially the same operations as in the block124, such as by vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and/or other suitable processes. The base epitaxial layer254may exhibit faceted growth when it continues to raise in the first region204, such that a width of the base epitaxial layer254in the first region204is larger than its counterpart in the second region206, as well as height and volume. The extra growth of the base epitaxial layer254in the first region204may be under time control. The mask layer260is then removed in a suitable process such as etching, resist stripping or plasma ashing.

Referring toFIGS.23A-23D, the method100′ includes a block127where an insulation layer256is formed over the base epitaxial layer254in both the first region204and the second region206. In some embodiments, the insulation layer256includes silicon oxide (SiO2), aluminum oxide (AlOx), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbon oxynitride (SiCON), silicon carbide (SiC), silicon oxycarbide (SiOC), or a combination thereof. The insulation layer256isolates the base epitaxial layer254from contacting epitaxial source/drain features to be formed in subsequent processes to suppress leakage current from the buck substrate. In some embodiments, the insulation layer256is first deposited in the source/drain recesses250using a plasma-enhanced chemical vapor deposition (PECVD) process, covering the base epitaxial layer254and sidewalls of the source/drain recesses250. Since deposition under a PECVD process usually forms a deposited layer thicker in the bottom portion of a recess but thinner on sidewalls, an etch-back process is subsequently performed to remove the insulation layer256from sidewalls of the source/drain recesses250and also slightly recess the insulation layer256to a determined height h6(e.g., by controlling the etching time), such that in the first region204the sidewalls of the inner spacers252right above the bottommost epitaxial layer216are partially covered by the insulation layer256and in the second region206the sidewalls of the bottommost inner spacers252are partially covered by the insulation layer256, as shown inFIGS.23C and23D. In furtherance of some embodiments, the insulation layer256in the first region204may also partially covers sidewalls of the bottommost epitaxial layer216(when the top surface of the base epitaxial layer254in the first region204is below the top surface of the bottommost epitaxial layer216). In some embodiments, the height h6ranges from about 4 nm to about 6 nm. The thickness of the insulation layer256in the first region204and the second region206is substantially the same. The removing of the insulation layer256from sidewalls of the source/drain recesses250may include a suitable etching process, such as a dry etching process, a wet etching process, or an RIE process. Referring toFIG.23B, air gaps258may be trapped at corner regions of the source/drain recesses250, being capped by the insulation layer256. A height h7of the air gaps258may range from about 4 nm to about 6 nm.

In some embodiments, the source/drain recesses250may have a high aspect ratio and to prevent the dielectric material during the deposition of the insulation layer256from capping the top openings of the source/drain recesses250, operations at the block127may adopt a cyclic deposition process. In the cyclic deposition process, operations at the block126alternates between a dielectric material deposition and an etching process to clean up dielectric material from accumulating at edges of the top opening of the source/drain recesses250and gradually grow the thickness of the insulation layer256through cycles. The etching process also helps removing dielectric material from sidewalls of the source/drain recesses250. In an example, the cyclic deposition process may take about 5 to about 100 cycles.

After operation at the block127, the method100′ continues to operations at the blocks130-138, which are shared with the method100. The shared operations are not repeated below for the interest of conciseness. After operations at the block138, a resultant workpiece200is shown inFIGS.24A-24D. The epitaxial source/drain features264are in-situ or ex-situ doped with an n-type dopant or a p-type dopant. For example, in some embodiments, the epitaxial source/drain features264include silicon doped with phosphorous for forming epitaxial source/drain features for an n-type FET. In some embodiments, the epitaxial source/drain features264include silicon-germanium (SiGe) doped with boron for forming epitaxial source/drain features for a p-type FET. The semiconductor layers of the epitaxial source/drain features264are selectively grown on different semiconductor surfaces exposed in the source/drain recesses, such as the lateral ends of the epitaxial layers216. Since the insulation layer256covers the top surface of the base epitaxial layer254, the epitaxial growth of the epitaxial source/drain features264does not take place therefrom. In other words, the insulation layer256blocks possible current path from the bottom of the epitaxial source/drain features264to the fin-shape base220B (or substrate202). Accordingly, substrate leakage current is significantly reduced. Further, the epitaxial source/drain features264-1in the first region204has a smaller height and smaller volume than the epitaxial source/drain features264-2in the second region206. The epitaxial source/drain features264-1contacts top channel layers216but not the bottom ones (e.g., the bottommost one as shown inFIG.24C). As a comparison, the epitaxial source/drain feature264-2contacts all available channel layers216in the second region206. Therefore, the GAA transistors in the first region204have less functional channel layers than the GAA transistors formed in the second region206.

Although not intended to be limiting, embodiments of the present disclosure provide one or more of the following advantages. For example, embodiments of the present disclosure form tunable numbers of stacked channel layers in different regions of one IC chip serving different functions. This advantageously meets requirements of different current driving capabilities of various transistors. Further, some embodiments of the present disclosure provide substrate leakage current suppression. Embodiments of the present disclosure can be readily integrated into existing semiconductor manufacturing processes.

In one exemplary aspect, the present disclosure is directed to a method. The method includes forming a stack of channel layers and sacrificial layers on a substrate, the channel layers and the sacrificial layers having different material compositions and being alternatingly disposed in a vertical direction, patterning the stack to form a semiconductor fin, forming an isolation feature on sidewalls of the semiconductor fin, recessing the semiconductor fin, thereby forming a source/drain recess, such that a recessed top surface of the semiconductor fin is below a top surface of the isolation feature, growing a base epitaxial layer from the recessed top surface of the semiconductor fin, depositing an insulation layer in the source/drain recess. The insulation layer is above the base epitaxial layer and above a bottommost channel layer. The method further includes forming an epitaxial feature in the source/drain recess, wherein the epitaxial feature is above the insulation layer. In some embodiments, the insulation layer separates the base epitaxial layer from contacting the epitaxial feature. In some embodiments, the insulation layer fully covers sidewalls of the bottommost channel layer. In some embodiments, a top surface of the base epitaxial layer is below a bottom surface of the bottommost channel layer and above a top surface of a bottommost sacrificial layer. In some embodiments, the base epitaxial layer fully covers sidewalls of the bottommost channel layer. In some embodiments, the insulation layer and the base epitaxial layer collectively cover sidewalls of the bottommost channel layer. In some embodiments, the depositing of the insulation layer includes a cyclic deposition process. In some embodiments, the depositing of the insulation layer includes a plasma-enhanced chemical vapor deposition (PECVD) process. In some embodiments, the method further includes forming first and second dielectric fins sandwiching the semiconductor fin, wherein the depositing of the insulation layer traps first air gaps under the insulation layer at corner regions of the first and second dielectric fins. In some embodiments, the forming of the epitaxial feature traps second air gaps between the epitaxial feature and the insulation layer, and the second air gaps are above the first air gaps.

In another exemplary aspect, the present disclosure is directed to a method of fabricating a semiconductor device. The method includes forming an epitaxial stack of channel layers and sacrificial layers on a semiconductor substrate, the channel layers and the sacrificial layers having different material compositions and being alternatingly stacked in a vertical direction, patterning the epitaxial stack to form a first semiconductor fin in a first region of the semiconductor substrate and a second semiconductor fin in a second region of the semiconductor substrate, recessing the first semiconductor fin in a first source/drain region, recessing the second semiconductor fin in a second source/drain region, forming an epitaxial layer in the first and second source/drain regions, forming a dielectric layer on the epitaxial layer in the first and second source/drain regions, wherein a top surface of the dielectric layer in the first source/drain region is above the top surface of the dielectric layer in the second source/drain region, and forming a first source/drain feature in the first source/drain region and a second source/drain feature in the second source/drain region, wherein the second source/drain feature is in contact with a bottommost channel layer in the second semiconductor fin, and the first source/drain feature is free of contact with a bottommost channel layer in the first semiconductor fin. In some embodiments, the first source/drain feature is free of contact with two or more bottom channel layers in the first semiconductor fin. In some embodiments, the forming of epitaxial layer includes growing the epitaxial layer in the first and second source/drain regions, depositing a masking layer covering the epitaxial layer in the second source/drain region, continue growing the epitaxial layer in the first source/drain region, and removing the masking layer. In some embodiments, the forming of the dielectric layer includes depositing the dielectric layer, such that the top surface of the dielectric layer in the first source/drain region is above the bottommost channel layer in the first semiconductor fin, and the top surface of the dielectric layer in the second source/drain region is above the bottommost channel layer in the second semiconductor fin, depositing a masking layer covering the dielectric layer in the first source/drain region, recessing the top surface of the dielectric layer in the second source/drain region, and removing the masking layer. In some embodiments, the method further includes removing the sacrificial layers from the first and second semiconductor fins, and forming a gate structure, wherein the gate structure wraps around each of the channel layers in the first and second semiconductor fins. In some embodiments, the method further includes forming inner spacers abutting the gate structure, wherein at least a bottommost inner spacer is laterally stacked between the dielectric layer and the gate structure.

In yet another exemplary aspect, the present disclosure is directed to a semiconductor device. The semiconductor device includes channel layers disposed over a substrate, a gate structure wrapping each of the channel layers, the gate structure including a gate dielectric layer and a gate electrode layer, a first epitaxial feature abutting a topmost channel layer, a second epitaxial feature under the first epitaxial feature, an inner spacer interposing the first epitaxial feature and the gate structure, and a dielectric layer disposed between the first and second epitaxial features. The dielectric layer and the second epitaxial feature separate the first epitaxial feature from contacting at least a bottommost channel layer. In some embodiments, the dielectric layer fully covers sidewalls of the bottommost channel layer. In some embodiments, the second epitaxial feature fully covers sidewalls of the bottommost channel layer. In some embodiments, a width of the first epitaxial feature is larger than a width of the second epitaxial feature.

The foregoing outlines features of several embodiments so that those of ordinary skill in the art may better understand the aspects of the present disclosure. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.