Patent ID: 12201041

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

FIG.1Ais a schematic cross-sectional view illustrating a memory device100according to some embodiments of the present disclosure.FIG.1Bis a schematic plan view illustrating a heater120of the memory device100as shown inFIG.1A.FIG.1Cis a schematic plan view illustrating active regions112of the phase change layer110as shown inFIG.1A.

Referring toFIG.1A, in some embodiments, the memory device100is a storage unit in a phase change random access memory (PCRAM). The memory device100includes a phase change layer110. As crystallinity of the phase change layer110is altered, the phase change layer110is able to be switched between multiple resistance states. Accordingly, the phase change layer110can be configured to store multiple logic states. When the phase change layer110has the highest crystallinity, the phase change layer110may have the lowest resistance, and a resistance state 11 (as will be described with reference toFIG.3A) can be stored in the phase change layer110. On the other hand, when the phase change layer110has the lowest crystallinity, the phase change layer110may have the highest resistance, and a resistance state 00 can be stored in the phase change layer110(as will be described with reference toFIG.3A). Furthermore, in some embodiments, at least one intermediate state can exist between the resistance state 11 and the resistance state 00 (e.g., resistance states 01, 10 as will be described with reference toFIG.3A). In these embodiments, the memory device100can be used for multi-level programming. The phase change layer110is made of a phase change material. In some embodiments, the phase change material is a chalcogenide material. In these embodiments, the chalcogenide material may include one or more of Ge, Te and Sb. For instance, the chalcogenide material may be GeSbTe, such as Ge2Sb2Te5(GST225), Ge4Sb2Te4(GST424) or so forth). In certain cases, the chalcogenide material may be doped with N, Si, C, In, Ga or the like, and an example of such chalcogenide material may be doped Ge6Sb1Te2(GST612). In some embodiments, a thickness of the phase change layer110may range from 100 Å to 600 Å. In addition, a method for forming the phase change layer110may include a deposition process, such as a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process. However, those skilled in the art may select other suitable materials or other viable method for forming the phase change layer110, and/or may modify dimension of the phase change layer110according to process requirements, the present disclosure is not limited thereto.

The memory device100further includes a heater120. The heater120is configured to provide thermal energy to the phase change layer110via a joule heating manner, such that the crystallinity of the phase change layer110can be altered. In this way, the phase change layer110can be switched between different resistance states. The heater120includes multiple heat conducting materials122having different electrical resistivities, and these heat conducting materials122are in contact with different regions of the phase change layer110. These regions of the phase change layer110are referred as active regions112, as being close to or in contact with the heat conducting materials122, and as undergoing a phase transition while being heated by the heat conducting materials122. Since the heat conducting materials122have different electrical resistivities, the heat conducting materials122can provide different amounts of joule heat to the active regions112of the phase change layer110, and change of crystallinity in the active regions112may be different from one another during a programming operation. In some embodiments, the heat conducting materials122with different electrical resistivities are made of the same material system (i.e., the same combination of elements), but may have different compositions (i.e., different elemental percentages). For instance, the heat conducting materials122may be made of titanium nitride, and have different titanium contents (e.g., titanium atomic percentages). The heat conducting material122with greater titanium content may exhibit lower electrical resistivity, and may produce less joule heat. On the other hand, the heat conducing material122with less titanium content may exhibit higher electrical resistivity, and produce greater joule heat.

In some embodiments, the heater120lies below the phase change layer110, and may be formed in a pillar shape having a footprint area smaller than a footprint area of the phase change layer110. The heater120may taper downwardly, or may have a width substantially constant along a vertical direction. In some embodiments, a height H120of the heater120ranges from 30 nm to 90 nm. Top surfaces of the heat conductive materials122collectively define at least a portion of a top surface of the heater120, and are in contact with the active regions112of the phase change layer110, respectively. At least one of the heat conducting materials122conformally cover a bottom surface and a sidewall of the heater120, and may be formed in a cup shape having a periphery wall portion and a bottom plate portion connected to and surrounded by the periphery wall portion. Remainder of the heat conducting materials122is formed at an inner side of the heat conductive material(s)122having the cup shape, and may be formed in a pillar shape. For instance, the heat conducting materials122may include a heat conducting material122a, a heat conducing material122band a heat conducting material122c. The heat conducting materials122a,122bare respectively formed in a cup shape. The heat conducting material122bis located at an inner side of the heat conducting material122a, and covers an inner surface of the heat conductive material112a. In addition, the heat conducting material122cfills a recess defined by an inner surface of the heat conducing material122b, and may be formed in a pillar shape. The heat conducting materials122a,122b,122chave different electrical resistivities, in order to provide different amount of joule heat to the active regions112of the phase change layer110. In those embodiments where the heat conducting materials122are made of titanium nitride, the heat conducting material122ahas a composition of Tix1Ny1, the heat conducting material122bhas a composition of Tix2Ny2, and the heat conducting material122chas a composition of Tix3Ny3. The coefficients x1, x2, x3 are different from one another. Similarly, the coefficients y1, y2, y3 are different from one another. In certain cases, the heat conducting material122ahas the lowest electrical resistivity, the heat conducting material122chas the highest electrical resistivity, and the heat conducting material122bhas an intermediate electrical resistivity. In these cases, the coefficient x1 is greater than the coefficient x2, and the coefficient x2 is greater than the coefficient x3. On the other hand, the coefficient y1 is smaller than the coefficient y2, and the coefficient y2 is smaller than the coefficient y3. In other words, a titanium atomic percentage in the heat conducting material122ais greater than a titanium atomic percentage in the heat conducting material122b, and the titanium atomic percentage in the heat conducting material122bis greater than a titanium atomic percentage in the heat conducting material122c. On the other hand, a nitrogen atomic percentage in the heat conducting material122ais smaller than a nitrogen atomic percentage in the heat conducting material122b, and the nitrogen atomic percentage in the heat conducting material122bis smaller than a nitrogen atomic percentage in the heat conducting material122c. For instance, the titanium atomic percentage and the nitrogen atomic percentage in the heat conducting material122arespectively range from 45% to 55%. The titanium atomic percentage in the heat conducting material122bmay range from 35% to 45%, whereas the nitrogen atomic percentage in the heat conducting material122bmay range from 55% to 65%. The titanium atomic percentage in the heat conducting material122cmay range from 25% to 35%, whereas the nitrogen atomic percentage in the heat conducting material122cmay range from 65% to 75%.

Referring toFIG.1B, in some embodiments, the heat conducting materials122a,122b,122care formed as having circular top view shapes. Viewing from above the heater120, the heat conducting materials122a,122b,122cmay be concentric circular patterns, and the heat conducting material122cis located within the heat conducting material122b, which is located within the heat conducting material122a. In this way, a diameter D122aof the circular top view shape of the heat conducting material122ais greater than a diameter D122bof the circular top view shape of the heat conducting material122b, which is greater than a diameter D122cof the circular top view shape of the heat conducting material122c. For instance, a ratio of the diameter D122awith respect to the diameter D122bmay range from 1 to 8, and a ratio of the diameter D122awith respect to the diameter D122cmay range from 2 to 40. In addition, the diameter D122amay be in a range from 10 nm to 40 nm, the diameter D122bmay be in a range from 5 nm to 10 nm, and the diameter D122cmay be in a range from 1 nm to 5 nm. However, those skilled in the art may form the heat conducting materials122a,122b,122cas having other top view shapes (e.g., rectangular top view shapes), and/or adjust dimensions of the heat conducting materials122a,122b,122caccording to design requirements, the present disclosure is not limited thereto.

In some embodiments, a method for forming the heat conducting materials122a,122b,122cincludes forming an opening in a dielectric layer (e.g., one of the dielectric layers210as will be described with reference toFIG.2) by a lithography process and an etching process. Subsequently, the heat conducting materials122a,122b,122care deposited in the opening by, for example, a chemical vapor deposition (CVD) process or an atomic layer deposition (ALD) process. The heat conducting materials122a,122bmay be conformally deposited on a sidewall and a bottom surface of the opening, whereas the subsequently deposited heat conducting material122cfills up the opening. In certain embodiments, recipes used for depositing the heat conducting materials122a,122b,122care identical to one another. Since dimensions of the heat conducting materials122a,122b,122csequentially reduce, compositions of the heat conducting materials122a,122b,122cdeposited by using the same recipe may be different from one another, and such composition variation is verified by using an energy-dispersive X-ray spectroscopy (EDX) analysis. As described above, in those embodiments where the heat conducting materials122a,122b,122care made of titanium nitride, the titanium atomic percentages of the heat conducting materials122a,122b,122cmay sequentially decrease, and the nitrogen atomic percentages of the heat conducting materials122a,122b,122cmay sequentially increase. It should be noted that, such relationship between the dimensions and the compositions of the heat conducting materials122a,122b,122cdeposited by using the same recipe may be observed when the dimensions of the heat conducting materials122a,122b,122care in a certain range. For instance, such relationship may be observed when the diameters D122a, D122b, D122cof the heat conducting materials122a,122b,122c(as shown inFIG.1B) are less than 40 nm, 10 nm, 5 nm, respectively. In alternative embodiments, the heat conducting materials122a,122b,122care deposited by using different recipes. In those embodiments where the heat conducting materials122a,122b,122care made of titanium nitride, the recipes for depositing the heat conducting materials122a,122b,122cmay have different ratios of titanium-containing precursor with respect to nitrogen-containing precursor (e.g., in terms of flow rate). For instance, the recipe for depositing the heat conducting material122ahas the highest value of such ratio, the recipe for depositing the heat conducting material122chas the lowest value of such ratio, and the recipe for depositing the heat conducting material122bhas an intermediate value of such ratio.

Referring toFIG.1A,FIG.1BandFIG.1C, in some embodiments, the active regions112of the phase change layer110include active regions112a,112b,112c, which are extending upwardly from the top surfaces of the heat conducting materials122a,122b,122c, respectively. The joule heats provided by the heat conducting materials122a,122b,122cmay move into the active regions112a,112b,112cmainly along a vertical direction. Since the heat conducting materials122a,122b,122chave different electrical resistivities, different amounts of joule heat can be provided to the active regions112a,112b,112c. In this way, the active regions112a,112b,112cmay be selectively subjected to phase transition. In other words, by controlling an input current provided to the heater120, some of the active regions112a,112b,112ccan be subjected to a phase transition, while no phase transition or a reverse phase transition may be observed in other(s) of the active regions112a,112b,112c. Accordingly, multiple intermediate resistance states can exist between the most crystallized state (i.e., the lowest resistance state) and the most amorphous state (i.e., the highest resistance state) of the phase change layer110, and a multi-level programming can be performed by using the memory device100. In addition, the phase change layer110can be accurately programmed to a certain resistance state by controlling how many of the active regions112a,112b,112cis/are subjected to phase transition(s) and what direction each phase transition goes. In this way, a verification step may be omitted, and a speed of multi-level programming of the memory device100may be improved. As shown inFIG.1BandFIG.1C, in those embodiments where the top view shapes of the heat conducting materials122a,122b,122care circular and concentric, the active regions112a,112b,112cmay have circular and concentric top view shapes as well. The diameters of the top view shapes of the active regions112a,112b,112cmay be slightly greater than, equal to or slightly less than the diameters D122a, D122b, D122cof the top view shapes of the heat conducting materials122a,122b,122c. In addition, as shown inFIG.1A, the active regions112a,112b,112cmay not extend to a top surface of the phase change layer110. Alternatively, the active regions112a,112b,112cspan from a bottom surface to the top surface of the phase change layer110.

In alternative embodiments, the heater120may include more/less than three of the heat conducting materials122, and an amount of the active regions112and a span of each active region112may be altered accordingly.

Referring toFIG.1A, in some embodiments, the heater120further includes a heat isolation layer124. The heat isolation layer124encloses a sidewall and a bottom surface of the outermost one of the heat conducting materials122(e.g., the heat conducting material122a), and may be configured to block the joule heat produced by the heat conducting materials122from laterally leaking to surrounding components. A top surface of the heat isolation layer124and the top surfaces of the heat conducting materials122collectively define the top surface of the heater120. A sidewall and a bottom surface of the heat isolation layer124define a sidewall and a bottom surface of the heater120, respectively. In addition, a height of the heat isolation layer124defines the height H120of the heater120, and a footprint area of the heat isolation layer124defines a footprint area of the heater120. The heat isolation layer124may be composed of a first material, whereas the heat conducting materials122are made of a second material. A thermal conductivity of the first material is smaller than a thermal conductivity of the second material. For instance, the first material may include tantalum nitride, which has a thermal conductivity of about 3 W/mK, whereas the second material may include titanium nitride, which has a thermal conductivity of about 20 W/mK. In addition, a method for forming the heat isolation layer124may include a deposition process, such as a PVD process or a CVD process. However, those skilled in the art may select other suitable material or other viable method for forming the heat isolation layer124according to process requirements, the present disclosure is not limited thereto.

Referring toFIG.1A, the memory device100further includes a bottom electrode130and a top electrode140. The heater120and the phase change layer110are in electrical contact with the bottom electrode130and the top electrode140. Whether an electrical current could pass through the heater120and the phase change layer110can be controlled by adjusting a voltage bias between the bottom electrode130and the top electrode140. In this way, reading and programming operations of the memory device100can be performed by controlling signals provided to the bottom electrode130and the top electrode140. A top surface of the bottom electrode130may be in contact with the bottom surface of the heater120(e.g., the bottom surface of the heat isolation layer124), and a bottom surface of the top electrode140may be in contact with a top surface of the phase change layer110. In some embodiments, a footprint area of the bottom electrode130is greater than the footprint area of the heater120, and a portion of the bottom electrode130may laterally surround the heater120. In addition, in some embodiments, a footprint area of the top electrode140is substantially identical to the footprint area of the phase change layer110, and a sidewall of the top electrode140may be substantially coplanar with a sidewall of the phase change layer110. However, those skilled in the art may modify the footprint areas of the bottom electrode130and the top electrode140according to design requirements, as long as the bottom electrode130and the top electrode140are in electrical contact with the heater120and the phase change layer110. In addition, in some embodiments, materials of the bottom electrode130and the top electrode140may respectively include Al, Cu, AlCu, W or other metallic materials.

FIG.2is a cross-sectional view illustrating a memory cell20in a memory integrated circuit according to some embodiments of the present disclosure.

Referring toFIG.1AandFIG.2, in some embodiments, a PCRAM integrated circuit includes a plurality of memory cells20each exemplarily illustrated inFIG.2. The memory cell20includes an access transistor200, and includes the memory device100electrically connected to a source terminal or a drain terminal of the access transistor200. The access transistor200is functioned as a switch controlling access to the memory device100. In some embodiments, the access transistor200is a planar-type metal-oxide-semiconductor field effect transistor (MOSFET). In these embodiments, the access transistor200is formed in and over a portion of a semiconductor substrate202having a planar top surface. This portion of the semiconductor substrate202may be referred as an active region of the access transistor200. An isolation structure204may be formed in the semiconductor substrate202, and laterally surrounds the active region of the access transistor200. The access transistor200may include a gate structure206covering the active region of the access transistor200, and may include doped regions208formed in the active region and located at opposite sides of the gate structure206. The gate structure206may be functioned as a gate terminal of the access transistor200, and may include a gate dielectric layer and a gate electrode covering the gate dielectric layer (both not shown). The gate electrode may be a portion of one of the word lines (not shown) functioned for switching on/off the access transistors200of a column/row of the memory cells20. In addition, the doped regions208may be functioned as the source and drain terminals of the access transistor200, and may have a conductive type (e.g., N type) opposite to a conductive type (e.g., P type) of the active region of the access transistor200. One of the doped regions208may be electrically connected to the memory device100, while the other one of the doped regions208may be electrically connected to a source line (not shown) configured to receive a reference voltage (e.g., a ground voltage). In addition, the top electrode140of the memory device100may be connected to a bit line (not shown). By switching the access transistor200and controlling the voltage of the bit line, input current provided to the memory device100can be controlled. In alternative embodiments, the access transistor200is a fin-type MOSFET (also referred as fin-FET). In these alternative embodiments, the access transistor200is formed in and over an active region shaped as a fin structure (not shown), and the gate structure206may cover a sidewall and a top surface of the fin-shape active region. Furthermore, in some embodiments, the doped regions208may be replaced by epitaxial structures formed in recesses at a top portion of the active region. Those skilled in the art may modify structure, configuration and dimensions of the access transistor200according to design requirements, the present disclosure is not limited thereto.

In some embodiments, the memory device100is formed in a stack of dielectric layers210disposed on the semiconductor substrate202. The access transistor200is covered by the bottommost one of the dielectric layers210. In some embodiments, the memory device100may be disposed on the bottommost one of the dielectric layers210, and laterally surrounded by others of the dielectric layers210. When the access transistor200is in an on-state, whether the memory device100is subjected to a reading/programming operation can be determined by a potential difference between the bit line connected to the top electrode140of the memory device100and the source line connected to one of the doped regions208of the access transistor200. A contact plug212may penetrate through the bottommost dielectric layer210, in order to establish electrical connection between the memory device100and one of the source and drain terminals of the access transistor200(e.g., one of the doped regions208). In some embodiments, the contact plug212is in contact with the bottom electrode130of the memory device100. In alternative embodiments, the memory device100is vertically spaced apart from the contact plug212, and electrically connected to the contact plug212through interconnection(s) (not shown) formed in additional dielectric layer(s) between the memory device100and the contact plug212.

In some embodiments, the memory cells20are formed within a central region of the integrated circuit, and are laterally surrounded by a peripheral region of the integrated circuit (not shown). The peripheral region of the integrated circuit may include logic circuits configured to manage data input/output during reading/programming operations of the memory cells20. For instance, the logic circuits may include field effect transistors respectively similar to the access transistor200as described above. In addition, the logic circuits may be free of a memory device (e.g., the memory device100as described above).

FIG.3Ais a schematic diagram illustrating various resistance states of the memory device100before and during a set programming operation according to some embodiments of the present disclosure.FIG.3Bis a schematic diagram illustrating waveforms of input currents provided to the memory device100before and during a set programming operation according to some embodiments of the present disclosure.FIG.4AthroughFIG.4Dare schematic diagrams illustrating the heater120and the phase change layer110of the memory device100at various stages before and during the set programming operation according to some embodiments of the present disclosure.

Referring toFIG.3A,FIG.3BandFIG.4A, in some embodiments, the set programming operation is a multi-level set programming operation, and a resistance state of the phase change layer110changes from a highest resistance state 00 to multiple low resistance states during the set programming operation. For instance, these low resistance states include a resistance state 11 with the lowest resistance, and include resistance states 01, 10 with resistances between the highest resistance and the lowest resistance corresponding to the resistance states 00, 11, respectively. In some embodiments, prior to the set programming operation, the entire phase change layer110may be in a crystalline phase, and then at least partially subjected to a phase transition from the crystalline phase to an amorphous state. In this way, the phase change layer110is at least partially amorphous before initiation of the set programming operation, and is in the highest resistance state 00. In some embodiments, as shown inFIG.4A, a portion AM of the phase change layer102in contact with the heater120turns into the amorphous state before the set programming operation, while the remaining portion of the phase change layer102stays crystallized. The active regions112of the phase change layer110are included in the portion AM, and are currently amorphous. As shown inFIG.3B, in order to turn the portion AM of the phase change layer110into the amorphous state, a current pulse P00may be provided to the heater120. An amplitude A00of the current pulse P00is high enough that the joule heats provided to the phase change layer110by the heat conducting materials122are able to substantially melt the portion AM of the phase change layer110. In addition, a duration time T00of the current pulse P00is short enough that the melted portion AM can be quenched to form the amorphous state. In some embodiments, the current pulse P00is provided with a sharp/abrupt rising edge and a sharp/abrupt falling edge. For instance, the current pulse P00may be a rectangular current pulse. Those skilled in the art may adjust the amplitude A00, the duration time T00and other characteristics of the current pulse P00according to materials of the heater120and the phase change layer110or other process conditions, the present disclosure is not limited thereto. Moreover, a shape and a volume of the portion AM of the phase change layer102may be altered along with adjustment of the current pulse P00and/or selection of the materials of the heater120and the phase change material100, the present disclosure is not limited thereto as well.

Referring toFIG.3A,FIG.3BandFIG.4B, in some embodiments, during the transition from the resistance state 00 to the resistance state 11, a resistance of the phase change layer110is drop from a highest level to a lowest level. As shown inFIG.4B, in some embodiments, all of the active regions112are crystallized by receiving the joule heats provided by the heat conducting materials122during the transition from the resistance state 00 to the resistance state 11. On the other hands, the remaining region in the portion AM of the phase change layer110stays amorphous. Alternatively, the remaining region in the portion AM of the phase change layer110is at least partially crystallized, along with the crystallization of the active regions112. As shown inFIG.3B, in order to crystallize all of the active regions112, a current pulse P11may be provided to the heater120. An amplitude A11of the current pulse P11should be high enough that the joule heats provided to the phase change layer110by the heat conductive materials122are able to crystallize all of the active regions112in the phase change layer110. Considering the heat conducting materials122are formed as having different electrical resistivities, even the joule heat produced by the heat conducting material122with the lowest electrical resistivity (e.g., the heat conducting material122a) upon receiving the current pulse P11should be able to crystallize the corresponding active region112(e.g., the active region112a). In addition, the amplitude Au of the current pulse P11should not be too high to result in melting of the active regions112. In other words, even the joule heat produced by the heat conducting material122with the highest electrical resistivity (e.g., the heat conducting material122c) upon receiving the current pulse P11should not be able to melt the corresponding active region112(e.g., the active region112c). As a result, the amplitude A11of the current pulse P11should be lower than the amplitude A00of the current pulse P00. Moreover, a duration time T11of the current pulse P11should be long enough not to result in quenching of the crystallized active regions112, so as to avoid from accidentally turning the active regions112into the amorphous state. In this way, the duration time T11of the current pulse P11should be longer than the duration time T00of the current pulse P00. In some embodiments, the current pulse P11has a stair-down falling edge (i.e., a stepwise descending edge), in order to reduce a cooling rate of the active regions112in the phase change layer110. On the other hand, as similar to the current pulse P00, the current pulse P11may have a sharp/abrupt rising edge as well. However, those skilled in the art may adjust the amplitude A11, the duration time T11, shape and other characteristics of the current pulse P11according to materials of the heater120and the phase change layer110or other process conditions, as long as all of the active regions112are ensured to be crystallized.

Referring toFIG.3A,FIG.3BandFIG.4C, in some embodiments, the resistance state of the phase change layer110is subsequently changed from the lowest resistance state 11 to the resistance state 01 with a resistance lower than the highest resistance corresponding to the resistance state 00, and higher than the lowest resistance corresponding to the resistance state 11. As shown inFIG.3B, during the transition from the resistance state 11 to the resistance state 01, a current pulse P01is provided to the heater120. An amplitude A01of the current pulse P01is higher than the amplitude A11of the current pulse P11, and is lower than the amplitude A00of the current pulse P00. In addition, a duration time T01of the current pulse P01is longer than the duration time T00of the current pulse P00, and may be slightly longer than, identical to or slightly shorter than the duration time T11of the current pulse P11. In some embodiments, as similar to the current pulse P11, the current pulse P01has a stair-down falling edge, and has a sharp/abrupt rising edge. As shown inFIG.4C, such current pulse P01may render some of the active regions112at least partially amorphous. On the other hand, other(s) of the active regions112may stay crystallized. Accordingly, an overall resistance of the phase change layer110is slightly increased, but not greater than the highest resistance corresponding to the resistance state 00 since at least some portions in the active regions112stay crystallized. For instance, the active regions112b,112creceiving the joule heats provided by the heat conducting materials122b,122cwith relatively high electrical resistivities are at least partially melted, and then cooled down to form amorphous parts in the active regions112b,112c. In those embodiments where the heater120is disposed below the phase change layer110, the joule heats are provided from below the active regions112b,112c. Accordingly, the amorphous parts of the active regions112b,112cmay extend upwardly from bottoms of the active regions112b,112c, and may or may not reach tops of the active regions112b,112c. On the other hand, when the heater120receives the current pulse P01, a joule heat provided by the heat conducting material122awith the relatively low electrical resistivity may not be sufficient to melt the active region112a. As a result, the active region112amay stay crystallized.

Referring toFIG.3A,FIG.3BandFIG.4D, in some embodiments, the resistance state of the phase change layer110is subsequently changed from the resistance state 01 to the resistance state 10. As shown inFIG.3A, a resistance of the resistance state 10 is slightly lower than the resistance of the resistance state 01, but higher than the lowest resistance corresponding to the resistance state 11. As shown inFIG.3B, during the transition from the resistance state 01 to the resistance state 10, a current pulse P10is provided to the heater120. An amplitude A10of the current pulse P10is higher than the amplitude A01of the current pulse P01, but lower than the amplitude A00of the current pulse P00. In addition, a duration time T10of the current pulse P10is longer than the duration time T00of the current pulse P00, and may be slightly longer than, identical to or slightly shorter than the duration time T01of the current pulse P01. In some embodiments, as similar to the current pulse P11, the current pulse P10has a stair-down falling edge, and has a sharp/abrupt rising edge. As shown inFIG.4D, when the heater120receives the current pulse P10, the amorphous parts previously existed in some of the active regions112may currently be re-crystallized as being heated by the corresponding heat conductive material(s)122. On the other hand, the current pulse P10may render other(s) of the active regions112partially amorphous. For instance, when the heater120receives the current pulse P10, the amorphous parts previously existed in the active regions112b,112care currently re-crystallized while receiving the joule heats provided by the heat conducting materials122b,122c. In addition, the active region112apreviously stayed crystallized is at least partially melted and then cooled down to form an amorphous part in the active region112aupon receiving the joule heat provided by the heat conducting material122a. In those embodiments where the heater120is disposed below the phase change layer110, the joule heat is provided from below the active region112a. Accordingly, the amorphous part of the active region112amay extend upwardly from bottom of the active region112a, and may or may not reach top of the active region112a. Since the amorphous parts previously existed in the active regions112b,112care currently re-crystallized, a resistance of the phase change layer110may decrease. In addition, the resistance of the phase change layer110at the resistance state 10 may not be lower than the resistance corresponding to the resistance state 11 because the active region112abecomes partially amorphous.

According to the embodiments described with reference toFIG.3A,FIG.3Band FIG.4A throughFIG.4D, during the set programming operation, the resistance state of the phase change layer110changes from the resistance state 00 to the resistance state 01 through the resistance state 10 and the resistance state 01. The resistance state 00 has the highest resistance, the resistance state 01 has the lowest resistance, and resistances of the resistance states 10, 01 are between the highest resistance and the lowest resistance corresponding to the resistances states 00, 11, respectively. During the transition from the resistance state 00 with the highest resistance to the resistance state 11 with the lowest resistance, all of the active regions112turn from the amorphous state to the crystalline state, and a significant resistance drop can be observed. During the transition from the resistance state 11 to the resistance state 10, some of the active regions112may be at least partially subjected to a phase transition from the crystalline phase to the amorphous state, and a resistance of the phase change layer110is increased accordingly (but still lower than the highest resistance corresponding to the resistance state 00). Subsequently, during the transition from the resistance state 10 to the resistance state 01, the amorphous parts previously existed in some of the active regions112may be re-crystallized, and the active region102previously crystallized may currently be at least partially subjected to a phase transition from the crystalline phase to the amorphous state. Consequently, a resistance of the phase change layer110is slightly lowered during the transition from the resistance state 10 to the resistance state 01 (but not lower than the lowest resistance corresponding to the resistance state 11). Therefore, by selecting different sets of the active regions112for phase transition, the phase change layer110can be programmed with more than two resistance states. In other words, a multi-level set programming can be achieved by using the memory device100. In addition, the phase change layer110can be accurately programmed to a certain resistance state by controlling how many of the active regions112a,112b,112care subjected to phase transition(s) and what direction each phase transition goes. In this way, a verification step following each transition from one resistance state to another may be omitted, and a speed of the multi-level set programming of the memory device100may be effectively improved.

FIG.5is a diagram of a resistance variation of the phase change layer110with respect to a variation of amplitude of the current input to the heater120during a set programming operation according to some embodiments of the present disclosure.

Referring toFIG.1AandFIG.5, as the amplitude of the current input to the heater120increases, the resistance of the phase change layer110is changed from the resistance state 00 to the resistance states 11, 01, 10. As shown inFIG.5, steps can be observed from the resistance variation of the phase change layer110as the amplitude of the current input increases, and the resistance states 11, 01, 10 are defined at these steps. In other words, the resistance of the phase change layer110is substantially fixed within ranges of these steps. Therefore, the phase change layer110can be accurately programmed to the resistance states 11, 01, 10 by controlling the amplitude of the input current to be within certain ranges corresponding to these steps of the resistance variation. Accordingly, a verification step may be omitted from the multi-level set programming of the memory device100. Furthermore, in certain embodiments, the multi-level set programming process does not have to follow the sequence from the resistance states 00 to the resistance state 10 through the resistance states 01, 10 as described with reference toFIG.3A,FIG.3BandFIG.4AthroughFIG.4D. In these certain embodiments, the resistance of the phase change layer110may be directly changed from the resistance state 00 to the resistance states 11, 01, 10 during the multi-level set programming process by setting the input currents provided to the heater120respectively within a range corresponding to a step of the resistance variation of the phase change layer110as shown inFIG.5.

It should be noted that, although the multi-level set programming process is described with reference toFIG.4AthroughFIG.4Dby using a mechanism regarding selecting different combinations of the active regions102for phase transition(s) and controlling the direction of each phase transition, other mechanism(s) can be used to explain the relationship of the resistance variation of the phase change layer110with respect to the input current provided to the heater120during the multi-level set programming process, the present disclosure is not limited thereto.

FIG.6is a diagram of a resistance variation of the phase change layer110with respect to a variation of amplitude of the current input to the heater120during a set programming operation according to alternative embodiments of the present disclosure.FIG.7AthroughFIG.7Care schematic diagrams illustrating the heater120and the phase change layer110of the memory device100at various stages during the set programming operation according to alternative embodiments of the present disclosure. The alternative embodiments to be described with reference toFIG.6andFIG.7AthroughFIG.7Care similar to the embodiments described with reference toFIG.3A,FIG.3B,FIG.4AthroughFIG.4DandFIG.5, only the differences therebetween will be discussed, the same or the like parts will not be repeated again.

Referring toFIG.1AandFIG.6, in alternative embodiments, a resistance of the phase change layer110gradually decreases as an amplitude of the current input to the heater120increases during a multi-level set programming operation. In these alternative embodiments, the resistance of the phase change layer110is sequentially changed from the resistance state 00 to the resistance states 01, 10, 11. As similar to the embodiments described with reference toFIG.5, each of the resistance states 01, 10, 11 shown inFIG.6is defined at a step of the resistance variation of the phase change layer110during the multi-level set programming operation.

Referring toFIG.6andFIG.7A, during the transition from the resistance state 00 to the resistance state 01, at least one of the active region(s)112is subjected to a phase transition from the amorphous state to the crystalline state. For instance, as shown inFIG.7A, the active region112cis crystallized during the transition from the resistance state 00 to the resistance state 01, while the active regions112a,112bmay remain amorphous. In some embodiments, an amplitude of a current pulse provided to the heater120for initiating the transition from the resistance state 00 to the resistance state 01 is high enough that the joule heat provided to the active region112cby the heat conducting material122cis able to crystallize the active region112c. In addition, the amplitude of this current pulse should not be too high, so as to prevent phase transitions of the active regions112a,112band melting of the active region112c. In some embodiments, a duration time of this current pulse is longer than the duration time of the current pulse Poo as described with reference toFIG.3B. In addition, in some embodiment, this current pulse has a stair-down falling edge and a sharp/abrupt rising edge, as similar to the current pulses P11, P01, P10described with reference toFIG.3B.

Referring toFIG.6andFIG.7B, during the transition from the resistance state 01 to the resistance state 10, one or more of the active regions112is/are further subjected to the phase transition from the amorphous state to the crystalline state. For instance, as shown inFIG.7B, the active region112bis further crystallized during the transition from the resistance state 01 to the resistance state 10, while the active region112amay currently remain amorphous. In some embodiments, an amplitude of a current pulse provided to the heater120for initiating the transition from the resistance state 01 to the resistance state 10 is high enough that the joule heat provided to the active region112bby the heat conducting material122bis able to crystallize the active region112b. In addition, the amplitude of this current pulse should not be too high, so as to prevent phase transitions of the active regions112aand melting of the active region112c. In some embodiments, a duration time of this current pulse is longer than the duration time of the current pulse P00as described with reference toFIG.3B. In addition, in some embodiment, this current pulse has a stair-down falling edge and a sharp/abrupt rising edge, as similar to the current pulses P11, P01, P10described with reference toFIG.3B.

Referring toFIG.6andFIG.7C, during the transition from the resistance state 10 to the resistance state 11, the rest of the active regions112is/are subjected to the phase transition from the amorphous state to the crystalline state, such that all of the active regions112are currently in the crystalline state. For instance, as shown inFIG.7C, the active region112ais further crystallized during the transition from the resistance state 10 to the resistance state 11. In some embodiments, an amplitude of a current pulse provided to the heater120for initiating the transition from the resistance state 10 to the resistance state 11 is high enough that the joule heat provided to the active region112aby the heat conducting material122ais able to crystallize the active region112a. In addition, the amplitude of this current pulse should not be too high, so as to prevent melting of the active region112b,112c. In some embodiments, a duration time of this current pulse is longer than the duration time of the current pulse Poo as described with reference toFIG.3B. In addition, in some embodiment, this current pulse has a stair-down falling edge and a sharp/abrupt rising edge, as similar to the current pulses P11, P01, P10described with reference toFIG.3B.

Although the multi-level set programming process shown inFIG.6is described as following a specific sequence (i.e., from the resistance state 00, the resistance state 01, the resistance state 10 to the resistance state 11) shown inFIG.7AthroughFIG.7C, such multi-level set programming process may not follow a certain sequence according to other embodiments. In other words, the resistance of the phase change layer110may be directly changed from the resistance state 00 to the resistance states 11, 01, 10 during the multi-level set programming process by setting the input currents provided to the heater120respectively within a range corresponding to a step of the resistance variation of the phase change layer110as shown inFIG.6.

FIG.8is a diagram of a resistance variation of the phase change layer110with respect to a variation of amplitude of the current input to the heater120during a reset programming operation according to alternative embodiments of the present disclosure.

Referring toFIG.1AandFIG.8, during a reset programming operation, a resistance of the phase change layer110may be changed from the resistance state 11 to the resistance states 10, 01, 00. As similar to the set programming processes as described with reference toFIG.5andFIG.6, the resistance states 01, 10, 11 are defined at steps of a resistance variation of the phase change layer110during the reset programming process (as shown inFIG.8). As a possible mechanism, the higher the resistance state of the phase change layer110is programmed, the more of the active regions102are subjected to a phase transition from a crystalline state to an amorphous state, thus the input current with the higher amplitude is required to be provided to the heater120for producing joule heats to the active regions112of the phase change layer110. In some embodiments, the currents input to the heater120during a reset programming process may be respectively provided as a current pulse similar to the current pulse P00as described with reference toFIG.3B, and are different from one another in terms of amplitude. Furthermore, the reset programming process may follow the sequence from the resistance state 11, the resistance state 10, the resistance state 01 to the resistance state 00. Alternatively, the resistance of the phase change layer110may be directly changed from the resistance state 11 to the resistance states 10, 01, 00 during the reset programming process by setting the input currents provided to the heater120respectively within a range corresponding to a step of the resistance variation of the phase change layer110as shown inFIG.8.

As above, the memory device according to embodiments of the present disclosure is a storage unit in a PCRAM. The memory device includes the bottom electrode, the heater standing on the bottom electrode, the phase change layer lying above the heater, and the top electrode disposed on the phase change layer. The heater comprises the heat conducting materials different from one another in terms of electrical resistivity. As having different electrical resistivities, the heat conducting materials can simultaneously produce different amounts of joule heat to the active regions in the phase change layer. In this way, the active regions can be selectively heated during a programming operation. By controlling an amplitude of the input current provided to the heater, some of the active regions can be subjected to a phase transition, while no phase transition or a reverse phase transition may be observed in other(s) of the active regions. Accordingly, multiple intermediate resistance states can exist between the most crystallized state (i.e., the lowest resistance state) and the most amorphous state (i.e., the highest resistance state) of the phase change layer, and a multi-level programming can be performed by using the memory device. Moreover, the phase change layer can be accurately programmed to a certain resistance state by controlling how many of the active regions is/are subjected to phase transition and what direction each phase transition goes. As a result, steps can be observed from the resistance variation of the phase change layer as the amplitude of the current input increases, and the resistance states are defined at these steps. In other words, the resistance of the phase change layer is substantially fixed within ranges of these steps. Therefore, the phase change layer can be accurately programmed to the resistance states by controlling the amplitude of the input current to be within certain ranges corresponding to these steps of the resistance variation. Accordingly, a verification step may be omitted from the multi-level programming of the memory device.

In an aspect of the present disclosure, a memory device is provided. The memory device comprises: a bottom electrode; a heater, disposed on the bottom electrode and comprising heat conducting materials, wherein electrical resistivities of the heat conducting materials are different from one another, a first one of the heat conducting materials has a periphery wall portion and a bottom plate portion connected to and surrounded by the periphery wall portion, a second one of the heat conducting materials is disposed on the bottom plate portion of the first one of the heat conducting materials, and laterally surrounded by the periphery wall portion of the first one of the heat conducting materials; a phase change layer, disposed on the heater and in contact with the heat conducting materials; and a top electrode, disposed on the phase change layer.

In another aspect of the present disclosure, a memory device is provided. The memory device comprises: a bottom electrode; a heater, disposed on the bottom electrode and having heat conducting regions configured to simultaneously produce different amounts of joule heat, wherein metallic element percentages of the heat conducting regions are different from one another; a phase change layer, disposed on the heater and in contact with top ends of the heat conducting regions; and a top electrode, disposed on the phase change layer.

In yet another aspect of the present disclosure, a programming method of a memory device is provided. The memory device comprises a bottom electrode, a heater disposed on the bottom electrode and having heat conducting materials different from one another in terms of electrical resistivity, and a phase change layer disposed on the heater and having active regions respectively in contact with one of the heat conducting materials of the heater. The programming method comprises: providing a first current pulse to the heater, so as to subject all of the active regions for phase transition; and providing a second current pulse to the heater, so as to select a portion of the active regions for phase transition.

It should be appreciated that the following embodiment(s) of the present disclosure provides applicable concepts that can be embodied in a wide variety of specific contexts. The embodiments are intended to provide further explanations but are not used to limit the scope of the present disclosure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.