Patent ID: 12230601

DESCRIPTION

In some implementations, the sub-modules and packages described herein include high power devices that are assembled together into a single package. For example, the sub-modules or packages can include a single semiconductor die or multiple semiconductor die (e.g., silicon semiconductor die, silicon carbide (SiC) semiconductor die, insulated-gate bipolar transistor (IGBT) die, metal-oxide-semiconductor field effect transistor (MOSFET) die, etc.). Assembling multiple semiconductor die together in a single package can provide high performance and high reliability configurations for electrical performance of the sub-modules. Alternatively or additionally, assembling multiple semiconductor die together in a single package can lead to improvement in thermal management while maintaining proper electrical performance of the sub-modules. The multiple semiconductor die may be assembled together in the single package so that two package components (including packaging materials or substrates) can conduct heat to and from each other (in other words, the two package components can be thermally coupled).

A typical dual-side cooled device package can include a semiconductor die disposed between a first DBC substrate and a second DBC substrate. In the package, the semiconductor die is positioned to conduct heat to (i.e., is thermally coupled to) the first DBC substrate and a conductive spacer block is disposed between the semiconductor die and the second DBC substrate. The conductive spacer block is thermally coupled to both the semiconductor die and to the second DBC substrate. The dual-side cooled device package can include a leadframe for accessing electrical terminals of the device, for example, through a circuit board in the first DBC substrate and the second DBC substrate.

Like the semiconductor die for the modern high power devices (e.g., insulated gate bipolar transistors (IGBTs), fast recovery diodes (FRD), etc.), modern power module packages have increasingly large areas and decreasing thicknesses. The modern power high power devices can have silicon die sizes that are substantially greater than the silicon die sizes of previous high power devices (e.g., <100 square millimeters). For example, the modern power high power devices may have silicon die sizes that are greater than 100 square millimeters or even greater than 225 square millimeters. Further, the modern power high power devices along with the greater silicon die size can have thinner and thinner silicon thicknesses (e.g., a thickness of 70 micrometers of less). As a result, the modern power module packages have increasingly large areas and decreasing thicknesses leading to increased susceptibility to thermally induced stress and defects (e.g., warpage).

To meet a higher thermal performance, thermal-mechanical stress balance across all components (DBC substrates, semiconductor die, spacer blocks, leadframe, mold compounds, solder, etc.) and their material properties have to be considered. For example, the components of a sub-module or package may be required to have low or closely matching coefficients of thermal expansion (CTE) (e.g., of the spacer block and the semiconductor die). There is a limited selection of low CTE material that can be used for the conductive spacer block without causing problems with cracking (e.g., of the semiconductor die, and the inter-component adhesive layers, etc.) during thermal cycling of the package. Only expensive materials with low CTE (e.g., copper molybdenum (CuMo)/aluminum silicon carbide (AlSiC) having 8˜9 ppm CTE)) are considered for use as the conductive spacer block.

In addition to a high cost of the conductive spacer block, complex processing steps for spacer interconnection are required in assembly of a power module or dual-side cooled device package that includes a conductive spacer block. Further, in typical assembly using conductive spacer blocks, component tolerances (e.g., substrate thickness tolerance, spacer block thickness tolerance, three adhesive layer thickness tolerances) and assembly jig tolerances (e.g., die attach, spacer attach, and stacking jigs tolerances, etc.) are not tightly controlled adequately at least because of the large number of components and jigs involved. The lack of tight tolerances can result in large mechanical stresses and die cracking in an assembled dual-side cooled power module or device package that includes a spacer block.

Example power modules and dual-side cooled device packages that avoid the high cost and assembly tolerance issues associated with use of conductive spacer blocks in the modules and packages are disclosed herein.

FIG.1Ashows, in cross sectional view, an example sub-module100including a semiconductor device die110(a single or multiple semiconductor device die) sandwiched between (e.g., in a gap between) a pair of substrates with no intermediate or intervening conductive spacer block (e.g., a spacer block is excluded) between the die and the substrates in accordance with the principles of the present disclosure.

FIG.1Bpictorially represents a multiple semiconductor device die configuration110M. The configuration may include multiple dies (e.g., dies110a,110b,110c,110d, and110e) that may be included in sub-module100. Dies110a,110b,110c110d, and110emay, for example, be diodes or transistors made of wide band gap (WBG) material (e.g., silicon carbide (SiC)). InFIG.1Band while discussing sub-module100herein, single semiconductor device die110may represent a single semiconductor device die or multiple semiconductor dies (e.g., multiple semiconductor device die configuration110M).

In a sub-module100shown inFIG.1A, a semiconductor device die110may, for example, be a power device die (e.g., an IGBT, a FRD, etc.). Device die110may be made of, for example, silicon material or a WBG semiconductor material. Device die110may be sandwiched (placed in the gap) between a pair of opposing substrates140,180. Device die110may be have a thickness T. In example implementations, thickness T depending for example, on device type, may be between about 5 microns and 50 microns.

An example substrate140,180can be a direct bonded metal (DBM) substrate (e.g., direct bonded copper (DBC) substrate, a DBM circuit board, etc.). In some implementations, one or more of the DBM substrates140,180can include a dielectric layer disposed between two metal layers. Substrate140and substrate180may, for example, include dielectric layers (e.g., a ceramic layer, a polymer layer)141and181that are plated, coated, or printed, on both sides, with copper or other electrically conductive material layers (e.g., conductive layer142, conductive layer182). Dielectric layers141and181may be made from electrically insulating, but thermally conductive materials (e.g., Zr-doped alumina). In some implementations, conductive layer142and conductive layer182may be, or can include, a copper layer.

Device die110may be bonded to (i.e., placed in direct thermal contact with) the pair of opposing substrates140,180, using, for example, adhesive layers112aand112b, respectively. In example implementations, device die110may be placed in a flip-chip configuration on substrate180. Adhesive layers112a,112bmay be formed, for example, by a solder bump, a preform solder, a solder paste, a sintering or a fusion bond. Adhesive layers112a,112bmay, for example, be solder material layers having thicknesses ta, tb, respectively.

Sub-module100may have a limited opening, clearance, or in-between space (e.g., in-between space120, also can be referred to as a space) having a height H between the pair of opposing substrates140,180. Height H may be limited by the vertical height or thicknesses (e.g., thickness T) of semiconductor die110and vertical heights or thicknesses (e.g., thicknesses ta, tb) of the adhesive layers212aand212bused to bond the die to the substrates). The height H, for example, may be equal to or about a same as the sum T+ta+tb. In example implementations, height H may be about a same as semiconductor die thickness T. Semiconductor die thickness T may depend on the type and materials of the device (e.g., IGBT, FRD, silicon, WBG, etc.). In example implementations, semiconductor die thickness T may depend on the type and materials of the device (e.g., IGBT, FRD, silicon, WBG, etc.).

The limited height of in-between space120between the two substrates may limit the sizes of other package components (e.g., leadframes210,220,FIG.2) that can be disposed in or placed between the two substrates in the package and wire bonded) e.g., to bonding pads on the substrates) to provide electrical connections to the enclosed (e.g., included) power device (e.g., via bond pads130,132on substrate140). In the example implementations discussed herein, sub-module100is used in a device package with leadframes in direct contact (i.e., in wireless contact) with the bonding pads formed on substrates140,180to provide electrical connections from outside the package to the enclosed power device.

FIG.2shows an example dual-side cooled device package (e.g., device module200) that avoids the use of conductive spacer blocks in the package, in accordance with the principles of the present disclosure.

Device module200may include sub-module100with leadframe210and leadframe220in direct contact with substrates140,180to carry electrical signals from die110to the outside. For example, on one side of module200, a portion210aof leadframe210may, for example, be disposed (inserted) in the opening (e.g., in-between space120,FIG.1) between substrate140and substrate180and bonded to bonding pads130,132on the substrates. On another side of module200, a portion210bof leadframe210may, for example, be disposed (inserted) in the opening (e.g., in-between space120,FIG.1) between substrate140and substrate180for bonding to pads (e.g., bonding pads130,132,FIG.1, etc.).

Portions210aand210bmay have heights Y2that are similar or comparable to (or slightly less than) the height H of the opening so that the leadframes can be fitted in the opening (in-between space) without mechanical obstruction. Other portions of the leadframes (e.g., portions210b,220a) that are not inserted in the opening may have a height Y1(e.g., Y1>Y2) that is not limited by the height H of the opening.

The bonding of the inserted leadframe portions210A and220A to the bonding pads (e.g., bonding pads130,132,FIG.1, etc.) may be accomplished using adhesive layers112c(e.g., a solder or sintering material, a solder bump, a preform solder, a solder paste, sintering or a fusion bond.). Further, in example implementations, components of device module200may be encapsulated in mold material200m(e.g., electrically isolating encapsulation material). Mold material200mmay electrically isolate at least one component of the package (e.g., semiconductor die, leadframes, etc.) from the other components.

Leadframe210and leadframe220be made of standard metal stock (e.g., metal bars, rod or pins). For example, as shown in cross section inFIG.3A, the standard metal stock may be a single gauge bar300having a rectangular cross section with a height Y1(corresponding, for example, to height Y1of leadframe portion220B). In example implementations, height Y1of single gauge bar300may be in the range of about 0.5 millimeters to 1.2 millimeters. In preparation of leadframes (e.g., leadframes210and220), as shown inFIG.3B, a portion of single gauge bar300A may be coined to prepare a dual gauge bar300B for use as, for example, leadframe220. Dual gauge bar300B may, for example, have heights Y2and Y1corresponding to portions220A and220B of leadframe220.

FIGS.4A through4Eillustrate an example process400for assembling a dual-side cooled device package (e.g., device module200) that includes semiconductor device die110and avoids the use of conductive spacer blocks in the package, in accordance with the principles of the present disclosure.

At a stage of the process, as shown inFIG.4A, an adhesive layer (adhesive layer112b, a sinter or solder material) may be lithographically patterned and printed on substate180. At a next stage of the process, as shown inFIG.4B, device module components (e.g., device die110, leadframe210and leadframe220) in may be placed or positioned (e.g., using jigs (not shown)) on adhesive layer112bon the lithographically patterned and printed substate180. Device die110may, for example, be placed on substate180in a flip-chip configuration. The components may be bonded to substrate180using, for example, sintering or solder reflow processes.

At a stage of the process, as shown inFIG.4C, an adhesive layer (adhesive layer112a, a sinter or solder material) may be lithographically patterned and printed on substate140.

At a next stage of the process, as shown inFIG.4D, the lithographically patterned and printed substate140may be stacked on top of the assembly (FIG.4B) of the components (e.g., device die110, leadframe210and leadframe220) on substrate180. The components may now be bonded to substrate140using, for example, sintering or solder reflow processes.

At a next stage of the process, as shown inFIG.4E, the components may be encased in a mold material (e.g., mold material200m) to assemble device module200. Further, trim and forming processes (e.g., to remove burrs, etc.) may be used to complete assembly of device module200.

Process400provides a leadframe direct interconnection between substrates140and180in device module200in a manner that is simpler, and more straightforward with fewer process steps than processes for fabricating typical device modules having conductive spacer blocks. Process400may also reduce cost by reducing the number of processing steps, and reduce material costs (e.g., spacer, wire, solder costs) compared to processes for fabricating typical device modules having conductive spacer blocks.

Process400also may result in a higher reliability package (e.g., device module200) by reducing use of CTE mismatched material (e.g., conducive spacer block, wire, solder, etc.) associated with the typical device modules having conductive spacer blocks.

Power devices (e.g., silicon semiconductor die, silicon carbide (SiC) semiconductor die, insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field effect transistor (MOSFET) die, fast recovery diodes (FRD), etc.) may be assembled in a dual-side cooled power device module or package (e.g., device module200) to benefit from the dual-side cooling, which may be provided by the pair of opposing substrates (e.g., substrate140and substrate180) in the power device module or package. The package components may be assembled together in thermal contact in the module or package to provide high performance, reliability, and/or improvement in thermal management while maintaining proper electrical performance of the power device module or package (e.g., device module200).

As noted previously, a device package (e.g., a dual-side cooled power module or package) may include more than one semiconductor device die enclosed (e.g., at least partially enclosed, disposed) within a pair of opposing substrates (e.g., substrate140and substrate180) without intervening conductive spacer blocks for dual-side cooling.FIG.5shows, for example, a side view, of a device package500that includes at least two device die510and520thermally coupled to the pair of opposing substrates140and180without intervening conductive spacer blocks between the die and either substrate. Device package500may also include leadframe540and leadframe550that are bonded directly to substrate140and substrate180to carry electrical signals from device die510and520to the outside of device package500.

In some implementations, the packages described herein can be used in applications with high voltages (e.g., higher than 600 V), high current densities (e.g., between 100 A to 1500 A (e.g., 1200 A)), and/or high switching frequencies (e.g., greater than 1 kHz). In some implementations, the packages can be used in a variety of industrial applications including, for example, automotive applications (e.g., automotive high power module (AHPM), electrical vehicles (EV), and hybrid electrical vehicles (EHV)), computer applications, industrial equipment, traction invertors, on-board charging applications, inverter applications, and/or so forth.

In an example implementations, as shown inFIGS.6A through6E, a high current (e.g.,1200A) bridge circuit (e.g., motor drive circuit) may be provided as a dual-side cooled power module package that includes multiple semiconductor die.

FIG.6Ashows, for example, a dual-side cooled power module package (e.g., unit600) including a bridge circuit for an EV system. Unit600may include multiple device sub-modules (e.g., sub-modules610,612,620and622) placed on a leadframe structure650and encased (at least partially) in a molding material (e.g., molding material200m). Each of sub-modules610,612,620and622may enclose (e.g., at least partially enclose, dispose) multiple semiconductor die (e.g., multiple semiconductor device die configuration110M) within the pair of opposing substrates140and180without an intervening conductive spacer block for dual-side cooling. Having multiple semiconductor die enclosed within the same substrates may result in equal or uniform cooling and a better temperature-balanced electrical performance of multiple semiconductor die in electrical circuits.

FIG.6C(likeFIG.1B) is a pictorial representation of multiple dies (e.g., dies110a,110b,110c,110d,110e, and100f) that may be included the multiple semiconductor device die (e.g., multiple semiconductor device die configuration110M) that are enclosed, for example, in sub-modules610,612,620and622. Each of the multiple semiconductor die may be thermally coupled to the first DBM substrate and the second DBM substrate without any intervening spacer blocks.

Dies110a,110b,110c110d,110e. and110fin multiple semiconductor device die configuration110M may, for example, include devices (e.g., WBG diodes) made of silicon carbide (SiC).

Unit600may provide a bridge driver circuit (e.g., a load driver circuit such as a motor driver circuit).FIG.6Bshows a circuit diagram of an example bridge driver circuit60that may be provided by unit600. Bridge driver circuit60may include a high-side half-bridge61and a low-side half-bridge62to drive a load (e.g., a motor63).

In unit600shown inFIG.6A, sub-modules610and612(e.g., each containing six SiC devices) may be placed in parallel to form a high-side half-bridge driver. Further, sub-modules620and622(e.g., each contain six SiC devices) may be placed in parallel to form a low-side half-bridge driver.

FIG.6DandFIG.6Eshows top and bottom views of a sub-module (e.g., sub-module610) in which multiple semiconductor device die configuration110M (FIG.6C) is enclosed (e.g., disposed between) between the pair of opposing substrates140and180without intervening conductive spacer block for dual-side cooling. In top and bottom views shown inFIG.6DandFIG.6Eonly outer copper layers182or142of substrates140,180are visible with the enclosed multiple semiconductor device die configuration110M hidden from view.

In unit600shown inFIG.6A, sub-modules610and612(e.g., each containing six SiC devices) may be placed in parallel to form a high-side half-bridge driver (e.g., high side half-bridge61,FIG.6B). Further, sub-modules620and622(e.g., each containing six SiC devices) may be placed in parallel to form a low-side half-bridge driver (e.g., low side half-bridge62,FIG.6B). The large number of parallel die (e.g., 2×6=12 die) in each half-bridge may result in increased current carrying capacity and an increased power rating for unit600.

FIG.7shows an example method700for assembling an example dual-side cooled device package that avoids the use of conductive spacer blocks.

Method700includes disposing a first direct bonded metal (DBM) substrate substantially parallel to a second DBM substrate a distance apart to define a space (710), and disposing at least a semiconductor die in the space (720). The method further includes bonding the semiconductor die to the first DBM substrate using a first adhesive layer without any intervening spacer block between the semiconductor die and the first DBM substrate (730), and bonding the semiconductor die to the second DBM substrate using a second adhesive without any intervening spacer block between the semiconductor die and the second DBM substrate (740).

The method further includes disposing a portion of a leadframe in the space to be in direct contact with at least one the first DBM substrate and the second DBM substrate. The portion of the leadframe inserted in the space has a height that is equal to, or about a same as, a height of the space between the first DBM substrate and the second DBM substrate. Further, the portion of the leadframe disposed in the space may be a portion of a stock metal coined to fit the space.

The method further includes bonding the portion of the leadframe disposed in the space to a bond pad on the first DBM substrate.

Some implementations of the packages, modules, and sub-modules described herein may be implemented using various semiconductor processing and/or packaging techniques. Some implementations may be implemented using various types of semiconductor processing techniques associated with semiconductor substrates including, but not limited to, for example, Silicon (Si), Gallium Arsenide (GaAs), Gallium Nitride (GaN), and/or so forth.

The terminology used herein is for the purpose of describing particular implementations only and is not intended to be limiting of the implementations. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used in this specification, specify the presence of the stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof.

It will also be understood that when an element, such as a layer, a region, or a substrate, is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it may be directly on, connected or coupled to the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to or directly coupled to another element or layer, there are no intervening elements or layers present. Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements that are shown as being directly on, directly connected or directly coupled can be referred to as such. The claims of the application may be amended to recite exemplary relationships described in the specification or shown in the figures.

As used in this specification, a singular form may, unless definitely indicating a particular case in terms of the context, include a plural form. Spatially relative terms (e.g., over, above, upper, under, beneath, below, lower, and so forth) are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. In some implementations, the relative terms above and below can, respectively, include vertically above and vertically below. In some implementations, the term adjacent can include laterally adjacent to or horizontally adjacent to.

Example implementations of the present inventive concepts are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized implementations (and intermediate structures) of example implementations. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example implementations of the present inventive concepts should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Accordingly, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example implementations.

It will be understood that although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a “first” element could be termed a “second” element without departing from the teachings of the present implementations.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this present inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the implementations. It should be understood that they have been presented by way of example only, not limitation, and various changes in form and details may be made. Any portion of the apparatus and/or methods described herein may be combined in any combination, except mutually exclusive combinations. The implementations described herein can include various combinations and/or sub-combinations of the functions, components and/or features of the different implementations described.