Patent ID: 12199184

DETAILED DESCRIPTION

Exemplary embodiments of the present invention will be described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.

It will be understood that, although the terms “first” and/or “second” may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element, from another element. For instance, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure. Similarly, the second element could also be termed the first element.

Other expressions that explain the relationship between elements, such as “between”, “directly between”, “adjacent to” or “directly adjacent to” should be construed in the same way.

The drawings are not necessarily to scale and in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When a first layer is referred to as being “on” a second layer or “on” a substrate, it not only refers to a case where the first layer is formed directly on the second layer with no intervening layers but also to a case where intervening layers are formed between the first and second layers. It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

FIG.1is a perspective view schematically illustrating a semiconductor device according to an embodiment of the present disclosure. Referring toFIG.1, a semiconductor device according to an embodiment of the present disclosure may include a buried insulating layer15entirely formed over a substrate10, a fin-type insulating pattern20formed over the buried insulating pattern15to have a line shape extending in a first horizontal direction X over the buried insulating layer15, a source/drain pattern30covering a portion of an upper surface and a portion of a side surface of the fin-type insulating pattern20, and a gate pattern50covering a portion of an upper surface and a portion of a side surface of the fin-type insulating pattern20over the buried insulating layer15to extend in a second horizontal direction Y. The first horizontal direction X and the second horizontal direction Y may be perpendicular to each other. In an embodiment, the source/drain pattern30and the gate pattern50may each have a Greek pi shape “π” cross section (cut at a right angle to the first horizontal direction X) with the bottom surface of the legs of the pi touching the top surface of the buried insulating layer15.

FIGS.2A to2Care longitudinal sectional views taken along lines I-I′, II-II′, and III-III′ of a semiconductor device according to an embodiment of the present disclosure illustrated inFIG.1. Referring toFIGS.2A to2C, a semiconductor device according to the embodiment of the present disclosure may include a buried insulating layer15, a fin-type insulating pattern20, a source/drain pattern30, a gate pattern50, a lower source/drain contact pattern61, an upper source/drain contact pattern62, a gate contact pattern63, and insulating layers41,42,43, and44over a substrate10.

The substrate10may include a semiconductor layer such as a silicon wafer. In some embodiments, the substrate10may include one of a compound semiconductor layer, an epitaxially grown silicon layer, silicon-on-insulator (SOI), or other semiconducting material layers. The substrate10may have a gate area GA and a contact area CA. The gate pattern50and the gate contact pattern63may be formed in the gate area GA. The source/drain pattern30, the lower source/drain contact pattern61, and the upper source/drain contact pattern62may be formed in the contact area CA.

The buried insulating layer15may be formed over the substrate10in its entirety, meaning that the entire bottom surface of the buried insulating layer15may be in contact with the top surface of the substrate10. The buried insulating layer15may include at least one insulating material such as silicon oxide (SiO2), silicon oxy-carbide (SiOC), and silicon nitride (SiN).

The fin-type insulating pattern20may have a fin shape or a bar shape that protrudes from an upper surface of the buried insulating layer15and extends in the first horizontal direction X. The fin-type insulating pattern20may include an insulating material such as silicon oxide (SiO2).

The source/drain pattern30may cover an upper surface and side surfaces of the fin-type insulating pattern20in the contact area CA. The source/drain pattern30may include a lower metal layer31, a channel layer32, and a buffer insulating layer33. The lower metal layer31may be directly formed over the upper and side surfaces of the fin-type insulating pattern20. The lower metal layer31may include a Ti (titanium)-based metal. For example, the lower metal layer31may include at least one of titanium (Ti), titanium nitride (TiN), titanium carbide (TiC), titanium aluminum (TiAl), and titanium aluminum nitride (TiAlN). In an embodiment, the lower metal layer31may include one of titanium carbide (TiC) or titanium aluminum (TiAl). The channel layer32may be directly formed over the lower metal layer31. The channel layer32may include an oxide semiconductor material. For example, the channel layer32may include at least one of InGaZnO, InGaZnSnO, InSnO, InSnZnO, SiInGaZnO, SiInGaZnSnO, SiInSnO, SiInSnZnO, AlGaZnO, AlGaZnSnO, AlSnO, AlSnZnO, SiAlGaZnO, SiAlGaZnSnO, SiAlSnO, SiAlSnZnO, InGaMgO, InGaMgSnO, InSnMgO, SiInGaMgO, SiInGaMgSnO, SiInSnMgO, AlGaMgO, AlGaMgSnO, AlSnMgO, SiAlGaMgO, SiAlGaMgSnO, SiAlSnMgO, or other oxide-based semiconductor materials. The buffer insulating layer33may be formed over the channel layer32. The buffer insulating layer33may include silicon oxide (SiO2) or aluminum oxide (Al2O3). A portion of the buffer insulating layer33may be removed so that the channel layer32and the lower source/drain contact pattern61can be in contact with each other in the contact area CA.

The gate pattern50may surround the upper surface and the side surfaces of the fin-type insulating pattern20and extend in the second horizontal direction Y in the gate area GA. The gate pattern50may be formed over the buffer insulating layer33in the gate area GA. The gate pattern50may include a gate insulating layer52and a gate electrode55. In an embodiment, the gate insulating layer52may be formed to contact at least partially with an upper surface of the buffer insulating layer33. The gate electrode55may be formed over the gate insulating layer52. The gate insulating layer52may include at least one of a compound containing hafnium (Hf), such as hafnium oxide (HfO), hafnium oxy-nitride (HfON), hafnium silicon oxy-nitride (HfSiON), hafnium aluminum oxide (HfAlO), or hafnium aluminum oxide nitride (HfAlON), or compounds containing lanthanum (La), erbium (Er), strontium (Sr), barium (Ba), or zirconium (Zr). The gate electrode55may include at least one of polycrystalline silicon, a silicide, a metal, a metal alloy, and a metal compound. In an embodiment, a barrier metal layer may be further formed between the gate insulating layer52and the gate electrode55. For example, the barrier metal layer may include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and tungsten nitride (WN).

The insulating layers41,42,43, and44may include a lower interlayer insulating layer41, a capping insulating layer42, a middle interlayer insulating layer43, and an upper interlayer insulating layer44. The lower interlayer insulating layer41may be formed over the buried insulating layer15to surround the lower source/drain contact pattern61and the gate pattern50. The capping insulating layer42may be formed over an upper surface of the lower interlayer insulating layer41and an upper surface of the gate electrode55. The upper interlayer insulating layer44may be formed over the capping insulating layer42to surround the upper source/drain contact pattern62and the gate contact pattern63. The lower interlayer insulating layer41and the upper interlayer insulating layer44may include a silicon oxide-based insulating material such as silicon oxide (SiO2), silicon hydro-oxide (SiHO), silicon oxy-carbide (SiOC), or silicon hydro-oxy-carbide (SiHOC). The capping insulating layer42may include an insulating material that is denser and harder than the lower interlayer insulating layer41and the upper interlayer insulating layer44. For example, the capping insulating layer42may include silicon nitride (SiN).

The lower source/drain contact pattern61may have a wall shape in which a width in the second horizontal direction Y is several times greater than a width in the first horizontal direction X, and the upper source/drain contact pattern62may have a pillar shape in which a width in the second horizontal direction Y and a width in the first horizontal direction X are similar. The lower source/drain contact pattern61may include a lower source/drain contact barrier layer61aand a lower source/drain contact plug61b. The lower source/drain contact barrier layer61amay surround a side surface of the lower source/drain contact plug61b. The lower source/drain contact barrier layer61amay be in contact with the channel layer32. The lower source/drain contact barrier layer61amay include titanium (Ti). For example, the lower source/drain contact barrier layer61amay include at least one of titanium (Ti), titanium nitride (TiN), titanium carbide (TiC), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), and tungsten nitride (WN). The lower source/drain contact plug61bmay include at least one of polycrystalline silicon, a silicide, a metal, a metal alloy, or a metal compound. The upper source/drain contact pattern62may include an upper source/drain contact barrier layer62aand an upper source/drain contact plug62b. The upper source/drain contact barrier layer62amay be in contact with the lower source/drain contact plug62b. The upper source/drain contact barrier layer62amay cover the lower surface and side surfaces of the upper source/drain contact plug62b.The upper source/drain contact barrier layer62amay include a barrier metal such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or tungsten nitride (WN). The upper source/drain contact plug62bmay include at least one of polycrystalline silicon, a silicide, a metal, a metal alloy, or a metal compound.

The gate contact pattern63may be connected with the gate electrode55. The gate contact pattern63may have a pillar shape. The gate contact pattern63may include a gate contact barrier layer63aand a gate contact plug63b. The gate contact barrier layer63amay cover the lower surface and the side surfaces of the gate contact plug63b. The gate contact barrier layer63amay include a barrier metal such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or tungsten nitride (WN). The gate contact plug63bmay include at least one of polycrystalline silicon, a silicide, a metal, a metal alloy, and a metal compound.

FIGS.3A to3Care longitudinal sectional views taken along the lines I-I′, II-II′, and III-III′ of a semiconductor device according to an embodiment of the present disclosure illustrated inFIG.1, respectively. Referring toFIGS.3A to3C, a semiconductor device according to an embodiment of the present disclosure may further include an interfacial insulating layer51formed between the channel layer32and the gate insulating layer52as compared to the semiconductor device described with reference toFIGS.2A to2C. In the semiconductor device illustrated inFIGS.2A to2C, the interfacial insulating layer51may replace the buffer insulating layer33between the lower metal layer31and the gate insulating layer52in the gate region GA. That is, the interfacial insulating layer51may be formed in a region from which the buffer insulating layer33is removed. The interfacial insulating layer51may include aluminum oxide (Al2O3). The buffer insulating layer33may include silicon oxide (SiO2). Reference numerals not described may be understood with reference toFIGS.2A to2C.

FIGS.4A to4Care longitudinal sectional views taken along the lines I-I′, II-II′, and III-III′ of a semiconductor device according to an embodiment of the present disclosure illustrated inFIG.1, respectively. Referring toFIGS.4A to4C, a semiconductor device according to an embodiment of the present disclosure may further include an upper metal layer34surrounding the lower surface and the side surfaces of the contact pattern61as compared to the semiconductor device described with reference toFIGS.2A to2Cand the semiconductor device described with reference toFIGS.3A to3C. The upper metal layer34may be formed to surround a portion of the upper surface and the side surfaces of the channel layer32and the upper surface of the buried insulating layer15in the contact area CA. The upper metal layer34may be spaced apart from the gate pattern50in a horizontal direction. Accordingly, parasitic capacitance between the lower source/drain contact pattern61and the gate pattern50by the upper metal layer34may be reduced. The upper metal layer34may include at least one of titanium (Ti), titanium nitride (TiN), titanium carbide (TiC), titanium aluminum (TiAl), and titanium aluminum nitride (TiAlN). In an embodiment, the upper metal layer34may include one of titanium carbide (TiC) or titanium aluminum (TiAl). For example, the lower metal layer31and the upper metal layer34may be formed of the same material. Reference numerals not described with respect toFIGS.4A to4Cmay be understood with reference toFIGS.2A to2C and3A to3C.

The semiconductor devices according to the embodiments of the present disclosure may have a multi-channel structure having a three-dimensional structure covering the side surfaces and the upper surface of the fin-type insulating pattern20. Accordingly, the driving capability of the transistor can be improved.

The oxide semiconductor materials have lower carrier mobility than intrinsic silicon. Therefore, when the oxide semiconductor materials are used as the channel material of the transistor, the off-current of the transistor can be lowered. However, the oxide semiconductor materials have high resistance due to low carrier concentration and the carrier mobility. The semiconductor device according to the present embodiment may include the lower metal layer31disposed below the channel layer32including the oxide semiconductor material. The lower metal layer31may include the Ti-based metal layer. The Ti-based metal layer may provide oxygen vacancy to the oxide semiconductor material by a scavenging phenomenon. The oxygen vacancy can increase a carrier concentration. Accordingly, the electrical resistance of the channel layer32corresponding to the source/drain can decrease and the conductivity can increase.

The semiconductor devices according to the present embodiments may further include the upper metal layer34including the Ti-based metal. Accordingly, the conductivity of the oxide semiconductor channel layer32can be more improved. In addition, the contact resistance between the channel layer32and the lower source/drain contact pattern61can be reduced.

FIGS.5A to12Care longitudinal sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.FIGS.5A to12Aare longitudinal sectional views taken along the line I-I′ inFIG.1,FIGS.5B to12Bare longitudinal sectional views taken along the line II-II′ inFIG.1, andFIGS.5C to12Care longitudinal sectional views taken along the line III-III′ inFIG.1.

Referring toFIGS.5A to5C, the method of manufacturing a semiconductor device according to an embodiment of the present disclosure may include forming a buried insulating layer15over a substrate10, forming a fin-type insulating pattern20over the buried insulating layer15, and forming a lower metal layer31over the fin-type insulating pattern20.

The substrate10may include a semiconducting layer such as a silicon wafer. The substrate10may have a gate area GA and a contact area CA.

Forming the buried insulating layer15may include entirely forming an insulating material such as silicon oxide (SiO2) over the substrate10by performing a deposition process. In an embodiment, the buried insulating layer15may include multiple insulating layers.

Forming the fin-type insulating pattern20may include forming an insulating material such as silicon oxide (SiO2) to have a fin shape or a bar shape extending in the first horizontal direction X by performing a deposition process, a photolithography process, and an etching process.

Forming the lower metal layer31may include forming a Ti-based metal layer to cover the fin-type insulating pattern20in the contact area CA by performing a deposition process and a patterning process. The Ti-based metal layer may include at least one of titanium (Ti), titanium nitride (TiN), titanium carbide (TiC), or titanium aluminum (TiAl). The lower metal layer31may cover the side surfaces and the upper surface of the fin-type insulating pattern20in the contact area CA in a pad form. In an embodiment, the lower metal layer31may partially extend onto the upper surface of the buried insulating pattern20in the contact area CA. In the gate area GA, the lower metal layer31may not cover the fin-type insulating pattern20. That is, the lower metal layer31may not be formed in the gate area GA.

Referring toFIGS.6A to6C, the method may include forming a channel layer32over the lower metal layer31and the exposed fin-type insulating pattern20, and forming a buffer insulating layer33over the channel layer32. Forming the channel layer32may include entirely forming an oxide semiconductor material by performing a deposition process. The oxide semiconductor material may include indium (In), gallium (Ga), and zinc (Zn). For example, the oxide semiconductor material may include at least one of InGaZnO, InGaZnSnO, InSnO, InSnZnO, SiInGaZnO, SiInGaZnSnO, SiInSnO, SiInSnZnO, AlGaZnO, AlGaZnSnO, AlSnO, AlSnZnO, SiAlGaZnO, SiAlGaZnSnO, SiAlSnO, SiAlSnZnO, InGaMgO, InGaMgSnO, InSnMgO, SiInGaMgO, SiInGaMgSnO, SiInSnMgO, AlGaMgO, AlGaMgSnO, AlSnMgO, SiAlGaMgO, SiAlGaMgSnO, SiAlSnMgO, or other oxide-based semiconductor materials. Forming the buffer insulating layer33may include entirely forming an insulating material such as silicon oxide (SiO2) or aluminum oxide (Al2O3) over the channel layer32by performing a deposition process. In an embodiment, the channel layer32and the buffer insulating layer33may be formed to partially extend onto the upper surface of the buried insulating pattern20, respectively. The method may further include removing the channel layer32and the buffer insulating layer33over the buried insulating layer15by performing a patterning process. In an embodiment, the channel layer32and the buffer insulating layer33may not be removed and may partially remain over the buried insulating layer15.

Referring toFIGS.7A to7C, the method may further include forming a sacrificial gate electrode35and a lower interlayer insulating layer41. Forming the sacrificial gate electrode35may include forming polycrystalline silicon over the buffer insulating layer33and the buried insulating layer15in the gate area GA by performing a deposition process and a patterning process. Forming the lower interlayer insulating layer41may include entirely forming an insulating material such as silicon oxide (SiO2) or silicon oxy-carbide (SiOC) by performing a deposition process, and planarizing the insulating material by performing a planarization process such as chemical-mechanical polishing (CMP). By the planarization process, the upper surface of the sacrificial gate electrode35and the upper surface of the lower interlayer insulating layer41may be coplanar.

Referring toFIGS.8A to8C, the method may further include forming a gate trench GT in the gate area GA by removing the sacrificial gate electrode35. The buffer insulating layer33and the buried insulating layer15may be exposed in the gate trench GT.

Referring toFIGS.9A to9C, the method may further include forming a gate insulating layer52and a gate electrode55in the gate trench GT. Forming the gate insulating layer52may include conformally forming a high-k material over the bottom and inner walls of the gate trench GT by performing a deposition process.

The gate insulating layer52may include at least one of a compound containing hafnium (Hf), such as hafnium oxide (HfO), hafnium oxy-nitride (HfON), hafnium silicon oxy-nitride (HfSiON), hafnium aluminum oxide (HfAlO), or hafnium aluminum oxy-nitride (HfAlON), or compounds containing lanthanum (La), erbium (Er), strontium (Sr), barium (Ba), or zirconium (Zr). The gate electrode55may include polycrystalline silicon, a silicide, a metal, a metal alloy, or a metal compound. The method may further include co-planarizing the upper surface of the lower interlayer insulating layer41, the upper surface of the gate insulating layer52, and the upper surface of the gate electrode55by performing a planarization process such as CMP.

Referring toFIGS.10A to10C, the method may further include forming a capping insulating layer42over the lower interlayer insulating layer41and the gate electrode55, forming a middle interlayer insulating layer43over the capping insulating layer42, and forming a lower source/drain contact slit CS exposing the channel layer32in the contact area CA. Forming the capping insulating layer42may include entirely forming a denser and harder material than the lower interlayer insulating layer41by performing a deposition process. The capping insulating layer42may include a barrier insulating material that prevents a reaction between the gate electrode55and the upper interlayer insulating layer44. For example, the capping insulating layer42may include silicon nitride (SiN). Forming the middle interlayer insulating layer43may include forming an insulating material such as silicon oxide (SiO2) or silicon oxy-carbide (SiOC) over the capping insulating layer42by performing a deposition process. Forming the lower source/drain contact slit CS may include selectively etching the middle interlayer insulating layer43, the capping insulating layer42, and the lower interlayer insulating layer41to expose the buffer insulating layer33, and removing the exposed buffer insulating layer33to expose the channel layer32. The lower source/drain contact slit CS may be spaced apart from the gate electrode55in a horizontal direction. The lower source/drain contact slit CS may expose the surface of the channel layer32formed over the sidewall of the fin-type insulating pattern20and expose the upper surface of the buried insulating layer15.

Referring toFIGS.11A to11C, the method may further include forming a lower source/drain contact barrier layer61ain the lower source/drain contact slit CS. Forming the lower source/drain contact barrier layer61amay include conformally forming a metal layer including titanium (Ti) over inner walls and a bottom surface of the lower source/drain contact slit CS by performing a deposition process. Accordingly, the lower source/drain contact barrier layer61amay be directly formed over the channel layer32exposed in the lower source/drain contact slit CS. For example, the lower source/drain contact barrier layer61amay include at least one of titanium (Ti), titanium nitride (TiN), titanium carbide (TiC), titanium aluminum (TiAl), or titanium aluminum nitride (TiAlN). In an embodiment, the lower source/drain contact barrier layer61amay include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), or other barrier metals.

Referring toFIGS.12A to12C, the method may further include forming a lower source/drain contact plug61bby filling the lower source/drain contact slit CS with a conductive material. The lower source/drain contact plug61bmay include a metal such as tungsten (W). The method may further include co-planarizing an upper surface of the lower source/drain contact plug61band an upper surface of the middle interlayer insulating layer43by performing a planarization process such as CMP.

Thereafter, the method may include forming an upper interlayer insulating layer44, and forming an upper source/drain contact pattern62and a gate contact pattern63with further reference toFIGS.2A to2C. Forming the upper interlayer insulating layer44may include forming an insulating material such as silicon oxide (SiO2) or silicon oxy-carbide (SiOC) by performing a deposition process. Forming the upper source/drain contact pattern62may include performing an etching process to form a hole that vertically penetrates the upper interlayer insulating layer44to expose the upper surface of the lower source/drain contact pattern61, performing a deposition process to conformally form an upper source/drain contact barrier layer62aover an inner wall and a bottom surface the hole, and performing a filling process to form an upper source/drain contact plug62bthat fills the hole. Forming the gate contact pattern63may include forming a hole that vertically penetrates the upper interlayer insulating layer44to expose the gate electrode55by performing an etching process, conformally forming a gate contact barrier layer63aover an inner wall and a bottom surface of the hole by performing a deposition process, and forming a gate contact plug63bthat fills the hole by performing a filling process. The upper source/drain contact barrier layer62aand gate contact barrier layer63amay include at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), and other barrier metals. The upper source/drain contact plug62band the gate contact plug63bmay include a metal such as tungsten (W).

FIGS.13A to14Care longitudinal sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.FIGS.13A and14Aare longitudinal sectional views taken along the line I-I′ ofFIG.1,FIGS.13B and14Bare longitudinal sectional views taken along the line II-II′ ofFIG.1, andFIGS.13C and14Care longitudinal sectional views taken along the line III-III′ ofFIG.1.

Referring toFIGS.13A to13C, the method of manufacturing a semiconductor device according to an embodiment of the present disclosure may include performing the processes described with reference toFIGS.5A to8C, and exposing the channel layer32in the gate trench GT by removing the buffer insulating layer33exposed in the gate trench GT.

Referring toFIGS.14A to14C, the method may further include forming an interfacial insulating layer51over the exposed channel layer32. The interfacial insulating layer51may include at least one of silicon oxide (SiO2), aluminum oxide (Al2O3), or other insulating material. In an embodiment, the interfacial insulating layer51may extend onto the buried insulating layer15.

Thereafter, the method further includes performing the processes described with reference toFIGS.9A to12C, and forming an upper interlayer insulating layer44with reference toFIGS.3A to3C, and forming an upper source/drain contact pattern62and a gate contact pattern63.

FIGS.15A to15Care longitudinal sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.FIG.15Ais a longitudinal sectional view taken along the line I-I′ ofFIG.1,FIG.15Bis a longitudinal sectional view taken along the line II-II′ ofFIG.1, andFIG.15Cis a longitudinal sectional view taken along the line III-III′ ofFIG.1. Referring toFIGS.15A to15C, a method of manufacturing a semiconductor device according to an embodiment of the present disclosure may include performing the processes described with reference toFIGS.5A to10C, and forming an upper metal layer34over a bottom surface of the lower source/drain contact slit CS. The upper metal layer34may be formed over the channel layer32and the buried insulating layer15exposed by the lower source/drain contact slit CS. The upper metal layer34may also be conformally formed over inner walls of the lower source/drain contact slit CS.

Thereafter, the method further include performing the processes described with reference toFIGS.11A to12C, forming an upper interlayer insulating layer44with reference toFIGS.4A to4C, and forming an upper source/drain contact pattern62and a gate contact pattern63.

According to embodiments of the present disclosure, a semiconductor device can include a transistor having a multi-oxide semiconductor channel. Since the transistor has an oxide semiconductor channel, the transistor can have a low off-current characteristic. Since the transistor has multiple channels, the transistor can have excellent driving capability. The resistance of the oxide semiconductor channel scavenged by the Ti-based metal may be lowered. Accordingly, the resistance of the source/drain contact may be lowered.

Although the present invention has been specifically described according to the above-described preferred embodiments, it should be noted that the above-described embodiments are for the purpose of explanation and not for the limitation thereof. In addition, it will be appreciated by person having ordinary skill in the art that various embodiments are possible within the scope of the present invention.