Patent ID: 12206409

Like reference numerals refer to corresponding parts throughout the several views of the drawings.

DESCRIPTION OF EMBODIMENTS

Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the various described embodiments. However, it will be apparent to one of ordinary skill in the art that the various described embodiments may be practiced without these specific details. In other instances, well-known methods, procedures, components, circuits, and networks have not been described in detail so as not to unnecessarily obscure aspects of the embodiments.

FIG.1is a block diagram of an example electronic system100in which a first electronic device102is electrically coupled to a second electronic device104via a data link106, in accordance with some embodiments. The first electronic device102and second electronic device104are configured to exchange data via the data link106. In an example, the first electronic device102includes a video source, and the second electronic device104includes a display device. The display device has a screen configured to display visual content provided by the first electronic device102via the data link106. In another example not shown, the first electronic device102includes a desktop computer, and the second electronic device104includes a mobile phone that exchanges data with the desktop computer via the data link106. Examples of the electronic devices102and104include, but are not limited to, a desktop computer, a laptop computer, a tablet computer, a video player, a camera device, a gameplayer device, or other formats of electronic devices which are configured to provide data or receive data. Video data, audio data, text, program data, control data, configuration data, or any other data are transmitted between the first and second electronic devices102and104via the data link106.

The data link106includes two connectors108at two of its ends. The two connectors108are configured to connect the data link106to respective connectors108of the first electronic device102and second electronic device104. For example, the connector108is a DisplayPort connector having a digital display interface developed by a consortium of personal computer and chip manufacturers and standardized by the Video Electronics Standards Association (VESA). The DisplayPort connector is configured to connect the data link106to the first electronic device102and carry video, audio, and control data according to a data communication protocol. In another example, the connector108is a universal serial bus (USB) connector. e.g., configured to connect a computer to a peripheral device. Exemplary types of the USB connector include, but are not limited to: USB-A, USB-B, USB-C, USB Micro-A, USB Micro-B, USB Mini-B, USB 3.0A, USB 3.0B, USB 3.0 Micro B, and USB Micro-AB. Further, a data communication protocol of USB4 is applied to communicate data using a USB-C connector, thereby providing a throughput of up to 40 Gbps, power delivery of up to 100 W, support for 4K and 5K displays, and backward compatibility with USB 3.2 and USB 2.

In some embodiments, the connector108includes a bidirectional channel for communicating a stream of data between the first and second electronic device102and104. The bidirectional channel of the connector108includes two data lanes and a pair of differential pins110coupled to the two data lanes. The pair of differential pins110are configured to receive a differential input signal from the first electronic device102or the second electronic device104, and the differential input signal carries a serial data command or serial content data (e.g., video or audio data) that are communicated via the two data lanes of the connector108. As such, the two data lanes and pair of differential pins110of the connector108are configured to facilitate bidirectional communication between the first electronic device102and the second electronic device104. The bidirectional channel is a data channel or an auxiliary channel. Specifically, the auxiliary channel of the connector108is used for communication of additional serial data beyond video and audio data, such as consumer electronics control (CEC) commands. In some embodiments, the pair of differential pins110is coupled to a dedicated set of twisted-pair wires configured to carry two input signals of the differential input signal.

Each connector108of the data link106is configured to be coupled to a respective connector108of the first electronic device102and a respective connector108of the second electronic device104. Each connector108of the data link106is bidirectional, so is each respective connector108of the electronic devices102and104. When the connector108of the data link106is coupled to the first or second electronic device102or104, the pair of differential pins110of the connector108of the data link106are physically and electrically coupled to a pair of differential pins110of the connector108of the first or second electronic device102or104. The pair of differential pins110of the connector108of the first or second electronic device102or104is configured to receive data from, or transmit data to, the differential pins110of the connector108of the data link106.

FIG.2is a schematic diagram of another example electronic system100in which a first electronic device or component102is electrically coupled to a second electronic device or component104via a data link106, in accordance with some implementations. In an example, the first electronic device102includes a central processing unit (CPU) of a personal computer, and the second electronic device104is a peripheral component of the personal computer, such as a graphics card, a hard drive, a solid state drive, a Wi-Fi communication module, or an Ethernet card. The data link106includes a connection port for receiving from the second electronic device104. The connection port is optionally formed on a mother board of the personal computer. In some implementations, the data link106complies with a high-speed serial computer expansion bus standard (e.g., PCI Express (PCIe), USB 4) and provides an interface to communicate data packets between the first and second electronic devices102and104in compliance with the bus standard. The data link106is a serial data bus including one or more data channels225. In some embodiments, each data channel225includes two wire sets230A and230B (also called two data lanes) for transmitting and receiving data packets, respectively, thereby supporting full-duplex communication between the first and second electronic devices102and104. In some examples, the data link106has 1, 4, 8, or 16 channels coupled in a single data port of the data link106. For each data channel225, the two wire sets230A and230B correspond to a downstream data direction240or an upstream data direction250defined with respect to the first electronic device102. Optionally, each wire set230A or230B includes two respective wires232and234for carrying a pair of differential signals.

In some implementations, the first electronic device102includes or is coupled to a root complex device (not shown) that is further coupled to the data link106. The root complex device is configured to generate requests for transactions including a series of one or more packet transmissions on behalf of the first electronic device102. Examples of the transactions include, but are not limited to, Memory Read, Memory Read Lock, Input Output (IO) Read, IO Write, Configuration Read, Configuration Write, and Message. In some implementations, the first electronic device102is coupled to one or more additional electronic devices besides the second electronic device104. The data link106includes one or more switch devices to couple the root complex device of the first electronic device102to multiple endpoints including the second electronic device104and additional electronic devices not shown inFIGS.1and2.

A data transmission protocol (e.g., PCI Express) is established based on a layered model including an application layer, a transaction layer, a data link layer, and a physical layer. As the top layer, the application layer is implemented in software programs, such as Ethernet, NVMe, SOP, AHCI, and SATA. In the transaction layer, each transaction of a series of packet transmissions is implemented as requests and responses separated by time. For example, a memory-related transaction is translated to device configuration and control data transferred to or from the second electronic device104(e.g., a memory device). Data packets associated with each transaction are managed by data flows on the data link layer. The physical layer controls link training and electrical (analog) signaling, and includes a logical block and an electrical block. The logic block defines ordered data sets in training states, and the electrical block defines eye diagram characteristics and analog waveforms. Each layer of the layered model includes first specifications for a transmitting side where a root complex device is coupled and second specifications for a receiving side where a peripheral component (i.e., the second electronic device104) is coupled.

As signals are transmitted within the wire sets230of each data channel225of the data link106, the signals are distorted and spread over sequential symbols and result in inter symbol interferences (ISI) and bit errors at the receiving side of the second electronic device104. In some implementations, these ISI and bit errors can be suppressed by a finite impulse response (FIR) driver that is coupled serially on a path of the data link106and configured with equalization settings using an equalization procedure. For example, the equalization procedure is implemented when a high speed data transfer rate needs to be initialized, when an equalization request is issued from the application layer, or when a bit error rate (BER) exceeds a data error tolerance.

The electronic system100includes a serializer and deserializer (SERDES) system corresponding to the data link106. The SERDES system of the data link106includes a serializer206, a transmitter208, the data channel225, a receiver218, and a deserializer216. The serializer206converts parallel data received from the first electronic device102to serial data. The transmitter208sends the serial data to the data channel225. The receiver218processes the serial data and send the processed serial data to the deserializer216, which converts the serial data back to the parallel data for the second electronic device104. In some implementations, the receiver218includes an FIR driver. On a transmitting side, a phase lock loop210generates a transmitter clock signal212based on a reference clock224, and the transmitter clock signal212is applied to control serialization of the data to be transmitted by the data channel225of the data link106.

On a receiving side, a clock data recovery (CDR) circuit222is used to recover a receiver clock signal224from the serial data received via the data channel225and compensate a variation of signal amplitudes caused by a loss and other factors in this data channel225. The receiver clock signal224is used with the receiver218and deserializer216to condition the serial data received via the data channel226and regenerate the parallel data from the serial data. During this process, the receiver218is configured to reduce signal distortion, data spreading over sequential symbols, inter symbol interferences, and resulting bit errors of the serial data on the receiving side of the second electronic device104. Specifically, in some embodiments, the receiver218includes a continuous time linear equalizer (CTLE)242, a decision feedback equalizer (DFE)244, and an FIR driver246. The CTLE242is configured to selectively attenuate low frequency signal components, amplify signal components around the Nyquist frequency, and remove higher frequency signal components to generate filtered serial data. The DFE244is configured to further amplify the filtered serial data, e.g., using level shifters, and recover one or more data bits at each clock switching edge or during each clock cycle. The one or more recovered data bits form data packets. The FIR driver246has a plurality of equalization settings (e.g., filtering coefficients), and is applied to improve signal quality of the data packets via digital signal conditioning (e.g., via high frequency filtering in a digital domain).

In some embodiments, the DFE244includes a loop-unroll DFE and is optionally used in wireless or wired communication. The DFE244includes a multiplexer configured to select one of a plurality of input signals based on a selection signal. For each input signal, ISI has been pre-compensated on a plurality of ISI compensation levels. The selection signal is generated based on previous data, and corresponds to a desirable ISI compensation level determined from the previous data. The one of the plurality of input signals is selected by the selection signal based on the desirable ISI compensation level. Further, in some situations, the selection signal includes two substantially complementary selection signals generated based on the previous data. The two substantially complementary selection signals correspond to two different timing paths and two different delays, thereby failing to be strictly complementary or opposite to each other. Instead, the two substantially complementary selection signals both stay at “1” (high level) or “0” (low level) momentarily for a short period of time corresponding to each switching edge of the selection signal. During this short period of time, an intermediate or output node of the multiplexer is floating and decoupled from any power supply, thereby potentially causing a circuit startup or function failure in the multiplexer.

In various embodiments of this application, a modulation circuit is coupled to an output interface of a multiplexer to suppress floating voltage states of the multiplexer, particularly when the multiplexer is applied in a data communication path that operates under a high speed data communication protocol (e.g., USB4 v1.0, USB4 v2.0 Gen 4 PAM-3, PCIe). A multiplexer selects one of a plurality of input signals as an output signal under the control of a selection signal. The modulation circuit combines the input signals and is applied to control the output signal, independently of the selection signal. This modulation circuit does not wait for the output signal to be generated, detect a floating voltage state, or take an action upon detection of the floating voltage state. Rather, the modulation circuit creates a current path to a certain power supply concurrently with or prior to an selection operation of the multiplexer, thereby preventing the floating voltage state from occurring to the multiplexer particularly when the multiplexer is applied in a high speed data communication path. In some embodiments, the multiplexer integrated with the modulation circuit is applied in the DFE244associated with the data link106. Alternatively, in some embodiments, the multiplexer integrated with the modulation circuit is not applied in the data link106. In some embodiments, the multiplexer integrated with the modulation circuit is configured to select one of an integer number N of input signals, where the integer number N is equal to 2, 3, 4, . . . and the like.

FIG.3Ais a symbolic diagram of an example two-input (2:1) multiplexer300, in accordance with some embodiments, andFIG.3Bis a truth table320of the two-input multiplexer300shown inFIG.3A, in accordance with some embodiments. The 2:1 multiplexer300receives a first input signal302, a second input signal304, a first selection signal306, and a first inverse signal308, and selects one of the first input signal302and the second input signal304as a multiplexed output signal310based on the first selection signal306and the first inverse signal308. Stated another way, the 2:1 multiplexer300is controlled by the first selection signal306and the first inverse signal308to generate the multiplexed output signal310tracking the selected one of the first input signal302and the second input signal304. In some embodiments, the multiplexed output signal310has a delay (e.g., ˜0.3 ns) from the selected one of the first input signal302and the second input signal304.

The first inverse signal308is substantially complementary and opposite to the first selection signal306. In some embodiments (e.g.,FIG.6A), the first inverse signal308is substantially complementary and opposite to the first selection signal306at any time. Alternatively, in some embodiments (e.g.,FIG.6B), both the first inverse signal308and the first selection signal306are enabled for a plurality of first durations corresponding to a plurality of first switching edges of the first selection signal306, and both the first inverse signal and the first selection signal are disabled for a plurality of second durations corresponding to a plurality of second switching edges of the first selection signal306. Each of the first and second durations is less than a threshold duration length (e.g., 0.1 ns) when the first inverse signal308is substantially complementary to the first selection signal306. In other words, the first selection signal306and the first inverse signal308are substantially complementary to each other even if the first selection signal306and the first inverse signal308are both enabled or disabled for short durations of time (i.e., durations that are shorter than threshold duration length).

In some embodiments, a length of a propagation path or a load of the first selection signal306is greater than that of the first inverse signal308. A rising or falling edge of the first selection signal306is delayed by a delay time with respect to a corresponding falling or rising edge of the first inverse signal308, respectively. Conversely, in some embodiments, a length of a propagation path or a load of the first selection signal306is less than that of the first inverse signal308. A rising or falling edge of the first inverse signal308has a delay time with respect to a corresponding falling or rising edge of the first selection signal306, respectively. As a result of the delay times, the first selection signal306and the first inverse signal308are both enabled or disabled for short durations of time.

Referring toFIG.3B, in some embodiments (322), the first selection signal306is enabled (i.e., “1”) at a high supply voltage (e.g., VDD), and the first inverse signal308is disabled (i.e., “0”) at a low supply voltage (e.g., GND, VSS). The multiplexer300selects the first input signal302as the multiplexed output signal310. Conversely, in some embodiments (324), the first selection signal306is disabled (i.e., “0”) at the low supply voltage, and the first inverse signal308is enabled (i.e., “1”) at the high supply voltage. The multiplexer300selects the second input signal304as the multiplexed output signal310. In some embodiments (326), both of the first selection signal306and the first inverse signal308are disabled (i.e., “0”) at the low supply voltage, and one or more nodes of the multiplexer300float and are not electrically coupled to any power supply by a current path, which may cause a startup or function failure in the multiplexer300. In some embodiments (328), both of the first selection signal306and the first inverse signal308are enabled (i.e., “1”) at the high supply voltage, and one or more nodes of the multiplexer300float and are not connected to any power supply by a current path, which may cause a startup or function failure in the multiplexer300.

FIG.4is a circuit diagram of an example two-input (2:1) multiplexer300, in accordance with some embodiments. The 2:1 multiplexer300includes two multiplexer branches402and404and an output interface410. The two multiplexer branches includes a first multiplexer branch402and a second multiplexer branch404. The first multiplexer branch402is configured to generate a first output signal406from a first selection signal306(SEL), a first inverse signal308(SEL_B), and a first input signal302(Input A). The first inverse signal308is substantially complementary to the first selection signal306. The second multiplexer branch404is configured to generate a second output signal408from the first selection signal306(SEL), the first inverse signal308(SEL_B), and a second input signal304(Input B). The output interface410is coupled to both outputs of the two multiplexer branches402and404, and configured to generate a multiplexed output signal310tracking one of the first input signal302and the second input signal304based on the first output signal406and the second output signal408.

In some embodiments, the first multiplexer branch402includes a plurality of P-type transistors (e.g., MP1and MP2) and a plurality of N-type transistors (e.g., MN1and MN2), and the plurality of P-type transistors and the plurality of N-type transistors of the first multiplexer branch402are coupled in series and between two distinct power supplies (e.g., VDD and GND, VDD and VSS). Specifically, in an example, the first input signal302is coupled to a gate of a first P-type transistor MP1and a gate of a first N-type transistor MN1. The first selection signal306and the first inverse signal308are coupled to a gate of a second N-type transistor MN2and a gate of a second P-type transistor MP2, respectively. Alternatively, in another example (not shown), the first input signal302is coupled to the gates of the first P-type transistor MP1and the second N-type transistor MN2. The first selection signal306and the first inverse signal308are coupled to the gates of the first N-type transistor MN1and the second P-type transistor MP2, respectively. Alternatively, in another example (not shown), the first input signal302is coupled to the gates of the second P-type transistor MP2and the second N-type transistor MN2. The first selection signal306and the first inverse signal308are coupled to the gates of the first N-type transistor MN1and the first P-type transistor MP1, respectively.

In some embodiments, the second multiplexer branch404includes a plurality of P-type transistors (e.g., MP3and MP4) and a plurality of N-type transistors (e.g., MN3and MN4), and the plurality of P-type transistors and the plurality of N-type transistors of the second multiplexer branch404are coupled in series and between the two distinct power supplies (e.g., VDD and GND), i.e., in parallel with the first multiplexer branch402. The second input signal304is coupled to a gate of one of the P-type transistors MP3and MP4and a gate of one of the N-type transistors MN3and MN4of the second multiplexer branch404. The first selection signal306and the first inverse signal308are coupled to a gate of the other one of the P-type transistors MP3and MP4and a gate of the other one of the N-type transistors MN3and MN4of the second multiplexer branch404, respectively.

In some embodiments, the output interface410includes a complementary metal-oxide semiconductor (CMOS) inverter including an output P-type transistor MP5and an output N-type transistor MN5. An input of the CMOS inverter is coupled to both of the outputs of the first multiplexer branch402and the second multiplexer branch404. Stated another way, the first output signal406and the second output signal408are electrically coupled to each other and to the input of the CMOS inverter. An output of the CMOS inverter is configured to output the multiplexed output signal310tracking the selected one of the first and second input signals302and304with a delay.

Referring toFIG.4, in some situations, both of the first selection signal306and the first inverse signal308are disabled at a low supply voltage (i.e., set at “0”). The N-type transistors MN2and MN4are turned off, and current paths connecting outputs of the two multiplexer branches402and404to a low power supply (e.g., GND, VSS) are disabled, independently of the first and second input signals302and304. The P-type transistors MP2and MP4are turned on. If the first input signal302and the second input signal304are enabled at a high supply voltage (i.e., set to “1”), current paths connecting the outputs of the two multiplexer branches402and404to a high power supply (e.g., VDD) are also disabled, causing the outputs of the two multiplexer branches402and404to float. Alternatively, in some situations, both of the first selection signal306and the first inverse signal308are enabled at the high supply voltage (i.e., set at “1”). The P-type transistors MP2and MP4are turned off, and current paths connecting the outputs of the two multiplexer branches402and404to the high power supply (e.g., VDD) are disabled, independently of the first and second input signals302and304. The N-type transistors MN2and MN4are turned on. If the first input signal302and the second input signal304are disabled at the low supply voltage (i.e., set to “0”), current paths connecting the outputs of the two multiplexer branches402and404to the low power supply (e.g., VSS) are disabled, causing the outputs of the two multiplexer branches402and404to float. As such, the multiplexer300enters floating voltage states, which may cause a circuit startup or function failure. (1) when the first selection signal306and first inverse signal308are disabled and the first and second input signals302and304are enabled or (2) when the first selection signal306are first inverse signal308are enabled and the first and second input signals302and304are disabled.

FIG.5is a circuit diagram of another example two-input (2:1) multiplexer300including a modulation circuit502for controlling floating voltage states, in accordance with some embodiments. The multiplexer300includes the modulation circuit502in addition to the two multiplexer branches402and404and the output interface410. The modulation circuit502is configured to generate a logic output signal504from the first input signal302and the second input signal304, independently of the first selection signal306and the first inverse signal308. The output interface410is also coupled to an output of the modulation circuit502in addition to the outputs of the first multiplexer branch402and the second multiplexer branch404. The output interface410is configured to generate a multiplexed output signal310tracking one of the first input signal302and the second input signal304based on the first output signal406, the second output signal408, and the logic output signal504. Stated another way, an input of the output interface410, the output of the first multiplexer branch402, the output of the second multiplexer branch404, and the output of the modulation circuit502are shorted to one another. In some embodiments, the multiplexed output signal310has a delay (e.g., ˜0.3 ns) from the tracked one of the first input signal302and the second input signal304.

The modulation circuit502is configured to hold the input of the output interface to the logic output signal504, when the first and second input signals302and304are both enabled or when the first and second input signals302and304are both disabled. Particularly, in some situations, both the first inverse signal308and the first selection signal306are enabled, and a floating voltage state occurs to the two multiplexer branches402and404if the first and second input signals302and304are disabled. If the first and second input signals302and304are disabled. P-type transistors MP6and MP7of the modulation circuit502are turned on to provide a current path to the high power supply (e.g., VDD), thereby suppressing the floating voltage state of the multiplexer300. Conversely in some situations, both the first inverse signal308and the first selection signal306are disabled, and the floating voltage state also occurs to the two multiplexer branches402and404if the first and second input signals302and304are enabled. If the first and second input signals302and304are enabled. N-type transistors MN6and MN7of the modulation circuit502are turned on to provide a current path to the low power supply (e.g., GND), thereby suppressing the floating voltage state of the multiplexer300. In other words, the modulation circuit502is configured to provide a current path, coupling an input of the output interface410to (1) a first supply voltage (e.g., VDD), when both the first inverse signal308and the first selection signal306are enabled and when the first input signal302and the second input signal304are disabled: and (2) a second supply voltage (e.g., GND), when both the first inverse signal and the first selection signal are disabled and when the first input signal302and the second input signal304are enabled.

Alternatively, in some situations, when the first and second input signals302and304are both enabled or disabled, the first inverse signal308and the first selection signal306are opposite, and the logic output signal504is consistent with the selected one of the first input signal302and the second input signal304. Additionally, in some situations, if one signal of the first and second input signals302and304is enabled and the other signal is disabled, a corresponding one of the two multiplexer branches402and404provides a current path to a high or low power supply to the input of the output interface410. The floating voltage state does not occur to the two multiplexer branches402and404, while the output of the modulation circuit502is floating.

Referring toFIG.5, in some embodiments, the modulation circuit502includes a plurality of transistors coupled in series between a high supply voltage (e.g., VDD) and a low supply voltage (e.g., VSS, GND). The plurality of transistors include a first N-type transistor MN6, a second N-type transistor MN7, a first P-type transistor MP6, and a second P-type transistor MP7. The first input signal302is coupled to gates of the first P-type transistor MP6and the first N-type transistor MN6, and the second input signal340is coupled to gates of the second P-type transistor MN7and the second N-type transistor MN7. Further, in some embodiments, the first P-type transistor MP6is coupled between the second P-type transistor MP7and the high supply voltage, and the second N-type transistor MN7is coupled between the first N-type transistor MN6and the low supply voltage. Alternatively, in some embodiments not shown, while the first P-type transistor MP6is coupled between the second P-type transistor MP7and the high supply voltage MP7, the first N-type transistor MN6is coupled between the second N-type transistor MN6and the low supply voltage.

The modulation circuit502generates the logic output signal504based on the input signals302and304, independently of the first selection signal306and the first inverse signal308. The modulation circuit502combines the input signals302and304in such a manner that it may provide the input of the output interface410with a current path to a certain power supply, as the floating voltage state occurs to the two multiplexer branches402and404. Conversely, as the floating voltage state does not occur to the two multiplexer branches402and404, the modulation circuit502goes to its own floating voltage state or provides the logic output signal504that is consistent with the output signal406or408, without interfering with operation of the two multiplexer branches402and404. The modulation circuit502prepares the logic output voltage504in advance or concurrently to anticipate the floating voltage state of the two multiplexer branches402and404, and therefore, does not disturb performance of the multiplexer300when the floating voltage state does not occur to the two multiplexer branches402and404. By these means, the modulation circuit502does not wait for the first output signal406, the second output signal408, or the multiplexed output signal310to be available for detection of the floating voltage state, and offers an effective solution to suppress the floating voltage state in a high speed communication link (e.g., in which the first selection signal306has a frequency that is greater than a threshold frequency).

FIG.6Ais a temporal diagram600of a selection signal306and an inverse signal308that are applied in a two-input multiplexer300, in accordance with some embodiments, andFIG.6Bis a temporal diagram650of a selection signal306and an inverse signal308applied in a two-input multiplexer300, in accordance with some embodiments. Referring toFIG.6A, in some embodiments, the first inverse signal308is substantially complementary and opposite to the first selection signal306at any time of a time axis. Each switching edge602-608has a switching time that is controlled within a threshold switching time. Each switch edge602-608is one of a rising edge602and a falling edge604of the first selection signal306and a falling edge606and a rising edge608of the first inverse signal308. Each rising edge602of the first selection signal306is temporally aligned (i.e., synchronous) with a respective falling edge606of the first inverse signal308, and each falling edge604of the first selection signal306is temporally aligned (i.e., synchronous) with a respective rising edge608of the first inverse signal308.

Referring toFIG.6B, in some embodiments, rising edges602of the first selection signal306are not synchronous with respective falling edges606of the first inverse signal308, and falling edges604of the first selection signal306are not synchronous with respective rising edges608of the first inverse signal308. Both of the first inverse signal308and the first selection signal306are enabled for a plurality of first durations TAcorresponding to a plurality of first switching edges (e.g., falling edges604) of the first selection signal306, and both of the first inverse signal308and the first selection signal306are disabled for a plurality of second durations TBcorresponding to a plurality of second switching edges (e.g., rising edges602) of the first selection signal306. Each of the first and second durations TAand TBis less than a threshold duration length (e.g., 0.1 ns) when the first inverse signal308is substantially complementary to the first selection signal306. In other words, the first selection signal306and the first inverse signal308are substantially complementary to each other even if the first selection signal306and the first inverse signal308are both enabled or disabled for short durations of time (e.g., the first and second durations TAand TBthat are less than the threshold duration length).

FIG.7Ais a symbolic diagram of an example three-input (3:1) multiplexer700, in accordance with some embodiments, andFIG.7Bis a truth table720of the 3:1 multiplexer700shown inFIG.7A, in accordance with some embodiments. In some embodiments, the 3:1 multiplexer700is applied in three-level pulsed amplitude modulation (PAM-3), and three levels represented by 2 data bits are transmitted in each sampling cycle. In some embodiments, a floating voltage states occurs with outputs of multiplexer branches of the multiplexer700when all of the selection signals and corresponding inverse signals are disabled or enabled concurrently.

The 3:1 multiplexer700receives a first input signal302, a second input signal304, a third input signal702, a first selection signal306, a first inverse signal308, a second selection signal706, and a second inverse signal708. The multiplexer700selects one of the first input signal302, the second input signal304, and the third input signal702as a multiplexed output signal710based on the first selection signal306, the first inverse signal308, the second selection signal706, and the second inverse signal708. Stated another way, the 3:1 multiplexer700is controlled by the first selection signal306, the first inverse signal308, the second selection signal706, and the second inverse signal708to select one of the input signals302,304, and702and generate the multiplexed output signal310tracking the selected one of the first input signal302, the second input signal304, and the third input signal702. In some embodiments, the multiplexed output signal710has a delay (e.g., ˜0.3 ns) from the selected one of the first input signal302, the second input signal304, and the third input signal702.

The first inverse signal308is substantially complementary and opposite to the first selection signal306, so is the second inverse signal708to the second selection signal706. In some embodiments, the second inverse signal708is substantially complementary and opposite to the second selection signal706at any time. Alternatively, in some embodiments, both the second inverse signal708and the second selection signal706are enabled for a plurality of third durations corresponding to a plurality of first switching edges of the second selection signal706, and both the second inverse signal708and the second selection signal706are disabled for a plurality of fourth durations corresponding to a plurality of second switching edges of the second selection signal706. Each of the third and fourth durations is less than a threshold duration length (e.g., 0.1 ns) when the second inverse signal708is substantially complementary to the second selection signal706. In other words, the second selection signal706and the second inverse signal708are substantially complementary to each other even if the second selection signal706and the second inverse signal708are both enabled or disabled for short durations of time (e.g., the third and fourth durations that are less than the threshold duration length).

Referring toFIG.7B, in some embodiments (722), the first and second selection signals306and706are disabled (i.e., “0”) at the low supply voltage, and the first and second inverse signal308and708are enabled (i.e., “1”) at the high supply voltage. The multiplexer300selects the first input signal302as the multiplexed output signal310. In some embodiments (724), the first selection signal306is disabled (i.e., “0”) at the low supply voltage, and the first inverse signal308is enabled (i.e., “1”) at the high supply voltage. The second selection signal706is enabled (i.e., “1”) at the high supply voltage, and the second inverse signal708is disabled (i.e., “0”) at the low supply voltage. The multiplexer300selects the second input signal304as the multiplexed output signal310. Additionally, in some embodiments (726), the first and second selection signals306and706are enabled (i.e., “1”) at the high supply voltage, and the first and second inverse signal308and708are disabled (i.e., “0”) at the low supply voltage. The multiplexer700selects the third input signal702as the multiplexed output signal710. Additionally and alternatively, in some embodiments (not shown), the first selection signal306is enabled (i.e., “1”) at the high supply voltage, and the first inverse signal308is disabled (i.e., “0”) at the low supply voltage. The multiplexer700selects the third input signal702as the multiplexed output signal710, independently of the second selection signal706and the second inverse signal708.

In some embodiments (728), all of the selection signals306and706and the inverse signals308and708are enabled (i.e., “1”) at the high supply voltage, one or more nodes of the multiplexer700float and are not electrically coupled to any power supply by a current path, which may cause a startup or function failure in the multiplexer700. In some embodiments (730), all of the selection signals306and706and the inverse signals308and708are disabled (i.e., “0”) at the low supply voltage, and one or more nodes of the multiplexer700float and are not electrically coupled to any power supply by a current path, which may cause a startup or function failure in the multiplexer700.

FIG.8is a circuit diagram of a three-input (3:1) multiplexer700, in accordance with some embodiments. The 3:1 multiplexer700includes three multiplexer branches402,404, and802and an output interface410. The three multiplexer branches includes a first multiplexer branch402, a second multiplexer branch404, and a third multiplexer branch802. The first multiplexer branch402is configured to generate a first output signal406from a first selection signal306(SEL0), a first inverse signal308(SEL0_B), a second selection signal706(SEL1), a second inverse signal708(SEL1_B), and a first input signal302(Input A). The first inverse signal308is substantially complementary to the first selection signal306, and the second inverse signal708is substantially complementary to the second selection signal706. The second multiplexer branch404is configured to generate a second output signal408from the first selection signal306(SEL0), the first inverse signal308(SEL0_B), the second selection signal706(SEL1), the second inverse signal708(SEL1_B), and a second input signal304(Input B). In some embodiments, the third multiplexer branch802is configured to generate a third output signal804from the first selection signal306(SEL0), the first inverse signal308(SEL0_B), the second selection signal706(SEL1), the second inverse signal708(SEL1_B), and a third input signal702(Input C). Alternatively, in some embodiments, the third multiplexer branch802is configured to generate a third output signal804from the second selection signal706(SEL1), the second inverse signal708(SEL1_B), and a third input signal702(Input C). The output interface410is coupled to outputs of the three multiplexer branches402,404, and802and configured to generate a multiplexed output signal710tracking one of the first input signal302, the second input signal304, and the third input signal702.

In addition to the three multiplexer branches402,404, and802and the output interface410, the multiplexer700includes a modulation circuit502. The modulation circuit502is configured to generate a logic output signal504from the first input signal302, the second input signal304, and the third input signal702, independently of the selection signals306and706and the inverse signals308and708. The output interface410is also coupled to an output of the modulation circuit502in addition to the outputs of the first multiplexer branch402, the second multiplexer branch404, and the third multiplexer branch802. The output interface410is configured to generate the multiplexed output signal710tracking one of the first input signal302, the second input signal304, and the third input signal702based on the first output signal406, the second output signal408, the third output signal804, and the logic output signal504. Stated another way, an input of the output interface410is shorted to the outputs of the first multiplexer branch402, second multiplexer branch404, third multiplexer branch802, and modulation circuit502. In some embodiments, the multiplexed output signal710has a delay (e.g., ˜0.3 ns) from the one of the first input signal302, the second input signal304, and the third input signal702.

In some embodiments, the first multiplexer branch402includes a plurality of P-type transistors (e.g., MP1, MP2, MP8) and a plurality of N-type transistors (e.g., MN1, MN2, MP8), and the plurality of P-type transistors and the plurality of N-type transistors of the first multiplexer branch402are coupled in series and between two distinct power supplies (e.g., VDD and GND). Specifically, in an example, the first input signal302is coupled to a gate of a first one of the plurality of P-type transistors and a gate of a first one of the plurality of N-type transistors. The first selection signal306and the first inverse signal308are coupled to a gate of a second one of the plurality of P-type transistors and a gate of a second one of the plurality of N-type transistors, respectively. The second selection signal706and the second inverse signal708are coupled to a gate of a third one of the plurality of P-type transistors and a gate of a third one of the plurality of N-type transistors, respectively.

The second multiplexer branch404includes a plurality of P-type transistors (e.g., MP3, MP4, MP9) and a plurality of N-type transistors (e.g., MN3, MN4, MN9), and the plurality of P-type transistors and the plurality of N-type transistors of the second multiplexer branch404are coupled in series and between the two distinct power supplies (e.g., VDD and GND), i.e., in parallel with the first multiplexer branch402. Further, the third multiplexer branch802includes a plurality of P-type transistors (e.g., MP10, MP11, MP12) and a plurality of N-type transistors (e.g., MN10, MN11, MN12), and the plurality of P-type transistors and the plurality of N-type transistors of the third multiplexer branch802are coupled in series and between the two distinct power supplies (e.g., VDD and GND), i.e., in parallel with the first and second multiplexer branches402and404. In some embodiments, all of the selection signals306and706and the inverse signals308and708are used to select each of the first, second, and third input signals302,304, and702. Alternatively, in some embodiments, only the second selection signal SEL1and second inverse signal SEL1_B are applied to select the third input signal702, while all of the selection signals SEL0and SEL1and the inverse signals SEL0_B and SEL1_B are used to select the first and second input signals302and304.

Referring toFIG.8, in some situations, the selection signals306and706and the inverse signal308and708are disabled at a low supply voltage (i.e., set at “0) concurrently. The N-type transistors MN2, MN4, MN8, MN9, MN11, and MN12are turned off, and current paths connecting outputs of the three multiplexer branches402,404, and802to the low power supply (e.g., GND) are disabled, independently of the input signals302,304, and702. The P-type transistors MP2, MP4, MP8, MP9, MP11, and MP12are turned on. If the first input signal302, the second input signal304, and the third input signal702are enabled at a high supply voltage (i.e., set to 37 1”), current paths connecting the outputs of the three multiplexer branches402,404, and802to the high power supply (e.g., VDD) are disabled, potentially causing the outputs of the three multiplexer branches402,404, and802to float. Alternatively, in some situations, the selection signals306and706and the inverse signal308and708are enabled at the high supply voltage (i.e., set at “1”). The P-type transistors MP2, MP4, MP8, MP9, MP11, and MP12are turned off, and current paths connecting the outputs of the three multiplexer branches402,404, and802to the high power supply (e.g., VDD) are disabled, independently of the input signals302,304, and702. The N-type transistors MN2, MN4, MN8, MN9, MN11, and MN12are turned on. If the input signals302,304, and702are disabled at the low supply voltage (i.e., set to “0”), current paths connecting the outputs of the three multiplexer branches402,404, and802to the low power supply (e.g., VSS) are disabled, potentially causing the outputs of the three multiplexer branches402,404, and802to float. In the absence of the modulation circuit502, the multiplexer700enters floating voltage states, potentially causing a circuit startup or function failure, (1) when the selection signals306and706and inverse signals308and708are disabled and the input signals302,304, and702are enabled or (2) when the selection signals306and706and inverse signals308and708are enabled and the input signals302,304, and702are disabled.

The modulation circuit502is configured to hold the input of the output interface to the logic output signal504, when the input signals302,304, and702are all enabled or all disabled. Particularly, in some situations, all of the inverse signals308and708and the selection signals306and706are enabled concurrently, and a floating voltage state occurs to the three multiplexer branches402,404, and802if the input signals302,304, and702are all disabled. If the input signals302,304, and702are all disabled, P-type transistors MP6, MP7, and MP13of the modulation circuit502are turned on to provide a current path to the high power supply (e.g., VDD), thereby suppressing the floating voltage state of the multiplexer300. Conversely in some situations, all of the inverse signals308and708and the selection signals306and70are disabled, and the floating voltage state also occurs to the three multiplexer branches402,404, and802if the input signals302,304, and702are all enabled. If the input signals302,304, and702are enabled, N-type transistors MN6, MN7, and MN13of the modulation circuit502are turned on to provide a current path to the low power supply (e.g., GND), thereby suppressing the floating voltage state of the multiplexer700. In other words, the modulation circuit502is configured to provide a current path, coupling an input of the output interface410to (1) a first supply voltage (e.g., VDD), when all of the inverse signals308and708and the selection signals306and706are enabled and when the input signals302,304, and702are disabled: or (2) a second supply voltage (e.g., GND), when all of the inverse signals308and708and the selection signals306and706are disabled and when the input signals302,304, and702are enabled.

Alternatively, in some situations, when the input signals302,304, and702are all enabled or all disabled, the first inverse signal308and the first selection signal306are opposite, and the second inverse signal708and the second selection signal706are opposite. The logic output signal504is consistent with the selected one of the input signals302,304, and702. Additionally, in some situations, if one signal of the input signals302,304, and702is enabled and the other two signals are disabled, a corresponding one of the three multiplexer branches402,404, and802provides a current path to a high or low power supply to the input of the output interface410. The floating voltage state does not occur to the three multiplexer branches402,404, and802, while the output of the modulation circuit502is floating.

Referring toFIG.8, in some embodiments, the modulation circuit502of the 3:1 multiplexer includes a plurality of transistors coupled in series between the high supply voltage and the low supply voltage. The plurality of transistors include three N-type transistor MN6, MN7, and MP13and three P-type transistors MP6, MP7, and MP13. Each of the input signals302,304, and702is coupled to a gate of a distinct P-type transistor and a distinct N-type transistor of the modulation circuit502. For each input signal302,304, or702, a relative position of the distinct P-type transistor in the plurality of P-type transistors is selected independently of a relative position of the distinct N-type transistor in the plurality of N-type transistors in the respective multiplexer branch402,404, or802.

The modulation circuit502generates the logic output signal504based on the input signals302,304, and702, independently of the selection signals306and706and the inverse signals308and708. The modulation circuit502prepares the logic output voltage504concurrently with, or in advance of, operation of the three multiplexer branches402,404, and802to anticipate the floating voltage state of the three multiplexer branches402,404, and802, while not disturbing performance of the multiplexer700when the floating voltage state does not occur to the three multiplexer branches402,404, and802. By these means, the modulation circuit502does not wait for the first output signal406, the second output signal408, the third output signal804or the multiplexed output signal310to be available for detection of the floating voltage state, and offers an effective solution to suppress the floating voltage state in a high speed communication link (e.g., in a DFE244(FIG.2), where the selection signals306and706have frequencies that are greater than a threshold frequency).

FIG.9is an eye diagram900of an example input signal Vin in a PAM-3 system, in accordance with some embodiments. In PAM-3, three levels defined by 2 data bits are transmitted in each sampling cycle. A first reference voltage902(Vref_High) is lower than a high supply voltage (e.g., 1.5V) of a first power supply (e.g.,VDD) and higher than a second reference voltage904. The second reference voltage904(Vref_Low) is higher than a low supply voltage (e.g., 0V, −1.5V) of a second power supply (e.g., GND, VSS). In some embodiments, the first reference voltage902is higher than an average of the high and low supply voltages, and the second reference voltage904is lower than the average of the high and low supply voltages. In accordance with a determination that the input signal Vin is higher than the first reference voltage902, a PAM-3 system provides output data is a first two-bit data item (e.g., “11”). In accordance with a determination that the input signal Vin is lower than the second reference voltage904, the PAM-3 system provides output data is a second two-bit data item (e.g., “00”). In accordance with a determination that the input signal Vin is between the first and second reference voltages902and904, the PAM-3 system provides output data is a third two-bit data item (e.g., “01”, “10”).

In some embodiments, two slice circuits generate a two-bit data item of the output data with reference to the first reference voltage902and the second reference voltage904. The two-bit data item of the output data is further used to provide the first selection signal306and the second selection signal706for selecting one of the input signals302,304, and702.

It is noted that in some embodiments, a multi-input multiplexer includes an integer number M of multiplexer branches for selecting one of the integer number M of input signals, where M is equal to 2, 3, 4, or above. The multi-input multiplexer is used with M-level pulsed amplitude modulation in which the integer number M of different voltage levels are transmitted in each sampling cycle. A modulation circuit502is configured to combine the integer number M of input signals to address a floating voltage state issue of such a multi-input multiplexer, particularly in a high speed communication link (e.g., in a DFE244(FIG.2), where the selection signals306and706have frequencies that are greater than a threshold frequency).

FIG.10is a flow diagram of an example method1000for multiplexing input signals, in accordance with some embodiments. The method1000is implemented by an electronic device. The electronic device obtains (1002) a first selection signal306, a first inverse signal308, a first input signal302, and a second input signal304. The first inverse signal308is substantially complementary to the first selection signal306. A first multiplexer branch402(FIG.4) generates (1004) a first output signal406based on the first selection signal306, the first inverse signal308, and the first input signal302. A second multiplexer branch404(FIG.4) generates (1006) a second output signal408based on the first selection signal306, the first inverse signal308, and the second input signal304. A modulation circuit502(FIG.5) generates (1008) a logic output signal504from the first and second input signals302and304, independently of the first selection signal306and the first inverse signal308. The electronic device generates (1010) a multiplexed output signal tracking one of the first and second input signals302and304based on the first output signal406, the second output signal408, and the logic output signal504via an output interface410.

In some embodiments, the modulation circuit502holds (1012) an input of the output interface410to the logic output signal504, when the first input signal302and the second input signal304are disabled (1014) or when the first input signal302and the second input signal304are enabled (1016).

In some embodiments, the modulation circuit502provides (1018) a current path, coupling an input of the output interface410to a first supply voltage when the first input signal302and the second input signal304are disabled (1020) or to a second supply voltage when both the first inverse signal308and the first selection signal306are disabled and when the first input signal302and the second input signal304are enabled (1022).

In some embodiments, the modulation circuit provides a current path to outputs of the first multiplexer branch402and the second multiplexer branch404, (1) when both the first inverse signal308and the first selection signal306are enabled and when the first input signal302and the second input signal304are disabled (1024); or (2) when both the first inverse signal308and the first selection signal306are disabled and when the first input signal302and the second input signal304are enabled (1026). Otherwise, in the absence of the modulation circuit502, a respective output of each of the first multiplexer branch402and the second multiplexer branch404has a floating voltage state and is electrically decoupled from any power supply.

In some embodiments, an input of the output interface410, an output of the first multiplexer branch402, an output of the second multiplexer branch404, and an output of the modulation circuit502are shorted to one another.

In some embodiments, the first output signal406tracks the first input signal302when the first selection signal306is enabled and the first inverse signal308is disabled. The second output signal408tracks the second input signal304when the first selection signal306is disabled and the first inverse signal308is enabled.

In some embodiments, both the first inverse signal308and the first selection signal306are enabled for a plurality of first durations TA(FIG.6B), and both the first inverse signal308and the first selection signal306are disabled for a plurality of second durations TB(FIG.6B). Each of the first and second durations is less than a threshold duration length when the first inverse signal308is substantially complementary to the first selection signal306.

In some embodiments, the modulation circuit502includes a plurality of transistors coupled in series between a high supply voltage and a low supply voltage, and the plurality of transistors include a first N-type transistor MN6, a second N-type transistor MN7, a first P-type transistor MP6, and a second P-type transistor MP6(FIG.5). The first input signal302is coupled to gates of the first P-type transistor MP6and the first N-type transistor MN6, and the second input signal304is coupled to gates of the second P-type transistor MP7and the second N-type transistor MN7. Further, in some embodiments, the first P-type transistor MP6is coupled between the second P-type transistor MP7and the high supply voltage (e.g., VDD), and the first N-type transistor MN6is coupled between the second N-type transistor MN7and the low supply voltage (e.g., VSS). Alternatively, in some embodiments, the first P-type transistor MP6is coupled between the second P-type transistor MP7and the high supply voltage, and the second N-type transistor MN7is coupled between the first N-type transistor MN6and the low supply voltage (FIG.5).

In some embodiments, the first selection signal306has a frequency that is greater than a threshold frequency.

In some embodiments, the first multiplexer branch402includes a plurality of P-type transistors and a plurality of N-type transistors, and the plurality of P-type transistors and the plurality of N-type transistors are coupled in series and between two distinct supply voltages. The first input signal302is coupled to a gate of a first P-type transistor MP1and a gate of a first N-type transistor MN1. The first selection signal306and the first inverse signal308are coupled to a gate of a second N-type transistor MN2and a gate of a second P-type transistor MP2, respectively (FIG.5).

In some embodiments, the output interface410) includes a complementary metal-oxide semiconductor (CMOS) inverter including an output P-type transistor MP5and an output N-type transistor MN5(FIG.5). An output of the CMOS inverter is configured to output the multiplexed output signal310tracking the one of the first and second input signals302and304. An input of the CMOS inverter is coupled to outputs of the first multiplexer branch402, the second multiplexer branch404, and the modulation circuit502.

FIG.11is a flow diagram of an example method1100for providing a multiplexer300in which a modulation circuit502is applied to control or suppress a floating voltage state, in accordance with some embodiments. The method1100includes providing (1102) a first multiplexer branch configured to obtain a first selection signal306, a first inverse signal308, and a first input signal302and generate a first output signal406. The first inverse signal308is substantially complementary to the first selection signal306. The method1100further includes providing (1104) a second multiplexer branch configured to obtain the first selection signal306, the first inverse signal308, and a second input signal304and generate a second output signal408. The method1100further includes providing (1106) a modulation circuit502configured to generate a logic output signal504from the first and second input signals302and304, independently of the first selection signal306and the first inverse signal308. The method1100further includes providing (1108) an output interface410coupled to the modulation circuit502, the first multiplexer branch, and the second multiplexer branch. The output interface410is configured to generate (1110) a multiplexed output signal tracking one of the first and second input signals302and304based on the first output signal406, the second output signal408, and the logic output signal504.

In some embodiments, the method1100further includes providing (1112) a third multiplexer branch802(FIG.8) configured to generate a third output signal804based on a second selection signal706, a second inverse signal708, and a third input signal702. The second inverse signal708is substantially complementary to the second selection signal706. The modulation circuit502is configured (1114) to generate the logic output signal504from the first, second, and third input signals302,304, and702, and the multiplexed output signal generated by the output interface410is configured to track one of the first, second, and third input signals302,304, and702based on the first, second, third, and logic output signals406,408,804, and504. Further, in some embodiments, the third output signal804is generated based on the third input signal702when the second selection signal706is enabled and the second inverse signal708is disabled. Additionally. In some embodiments, the first output signal406depends on the first input signal302when the second selection signal706is disabled and the second inverse signal708is enabled, and the second output signal408depends on the second input signal304when the second selection signal706is disabled and the second inverse signal708is enabled.

In some embodiments (FIG.8), the third multiplexer branch802is configured to generate the third output signal804based on the first selection signal306and the first inverse signal308in addition to the second selection signal706, the second inverse signal708, and the third input signal702.

In some embodiments, the modulation circuit502is configured to, when the first input signal302, the second input signal304, and the third input signal702are all enabled or all disabled, hold an input of the output interface410to the logic output signal504and provide a current path coupling the input of the output interface410to at least one power supply (e.g., VDD, GND).

In some embodiments, the modulation circuit provides a current path to outputs of the first multiplexer branch402, the second multiplexer branch404, and the third multiplexer branch802, (1) when the first inverse signal308, the first selection signal306, the second inverse signal708and the second selection signal706are enabled and when the first input signal302, the second input signal304, and the third input signal702are disabled, or (2) when the first inverse signal308, the first selection signal306, the second inverse signal708and the second selection signal706are disabled and when the first input signal302, the second input signal304, and the third input signal702are enabled. Otherwise, in the absence of the modulation circuit502, a respective output of each of the first multiplexer branch402, the second multiplexer branch404, and the third multiplexer branch802has a floating voltage state and is electrically decoupled from any power supply.

In some embodiments, the methods1000and1100are, optionally, governed by instructions that are stored in a non-transitory computer readable storage medium and that are executed by one or more processors (e.g., a controller) of an electronic device (e.g., a driver device). Each of the operations shown inFIGS.10and11may correspond to instructions stored in a memory or non-transitory computer readable storage medium. The computer readable storage medium may include a magnetic or optical disk storage device, solid state storage devices such as Flash memory, or other non-volatile memory device or devices. The instructions stored on the computer readable storage medium may include one or more of: source code, assembly language code, object code, or other instruction format that is interpreted by one or more processors. Some operations in methods1000and1100may be combined and/or the order of some operations may be changed.

It should be understood that the particular order in which the operations inFIGS.10and11have been described are merely exemplary and are not intended to indicate that the described order is the only order in which the operations could be performed. One of ordinary skill in the art would recognize various ways to multiplexing signals while suppressing a floating voltage state as described herein. Additionally, it should be noted that details of other processes and structures described above with respect toFIGS.1-9are also applicable in an analogous manner to methods1000and1100described above with respect toFIGS.10and11. For brevity, these details are not repeated here.

It will also be understood that, although the terms first, second, etc. are, in some instances, used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first electronic device can be termed a second electronic device, and, similarly, a second electronic device can be termed a first electronic device, without departing from the scope of the various described embodiments. The first electronic device and the second electronic device are both electronic device, but they are not the same electronic device.

The terminology used in the description of the various described embodiments herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used in the description of the various described embodiments and the appended claims, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms “includes,” “including.” “comprises,” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

As used herein, the term “if” is, optionally, construed to mean “when” or “upon” or “in response to determining” or “in response to detecting” or “in accordance with a determination that,” depending on the context. Similarly, the phrase “if it is determined” or “if [a stated condition or event] is detected” is, optionally, construed to mean “upon determining” or “in response to determining” or “upon detecting [the stated condition or event]” or “in response to detecting [the stated condition or event]” or “in accordance with a determination that [a stated condition or event] is detected,” depending on the context.

Although various drawings illustrate a number of logical stages in a particular order, stages that are not order dependent may be reordered and other stages may be combined or broken out. While some reordering or other groupings are specifically mentioned, others will be obvious to those of ordinary skill in the art, so the ordering and groupings presented herein are not an exhaustive list of alternatives. Moreover, it should be recognized that the stages can be implemented in hardware, firmware, software or any combination thereof.

The above description, for purpose of explanation, has been described with reference to specific embodiments. However, the illustrative discussions above are not intended to be exhaustive or to limit the scope of the claims to the precise forms disclosed. Many modifications and variations are possible in view of the above teachings. The embodiments were chosen in order to best explain the principles underlying the claims and their practical applications, to thereby enable others skilled in the art to best use the embodiments with various modifications as are suited to the particular uses contemplated.