Patent ID: 12249826

While the disclosure is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that other embodiments, beyond the particular embodiments described, are possible as well. All modifications, equivalents, and alternative embodiments falling within the spirit and scope of the appended claims are covered as well.

DETAILED DESCRIPTION

FIG.1represents an example power device100. The power device100(e.g. a “half-bridge” w/two MOSFETS) includes a high-side (HS) switch102, a low-side (LS) switch104, receiving a supply voltage106and coupled to a ground reference108. Between the HS switch102and the LS switch104is a mid-node (LX)110(e.g. a switching node). The mid-node110is coupled to an inductor112configured to route an output current (Iout)118and present an output voltage (Vout)116at an output of the power device100.

While there are many possible parasitic elements, for purposes of the discussion that follows the focus is on a parasitic bipolar114across the LS switch104that conducts a parasitic output current120under certain circuit operating conditions. This parasitic output current120is not desired and becomes part of the output current118.

For example, in applications where the power device100is configured as a synchronous buck converter half bridge, the switching node (LX)110flies to a negative voltage (i.e. back EMF voltage) at each discharge cycle, due to the output current (Iout)118flowing into the inductor112. If the low-side (LS) switch104is not isolated (e.g. not an SOI (silicon on insulator) switch) and this negative flyback voltage exceeds a diode threshold, then the parasitic NPN bipolar114is triggered and the undesired parasitic output current120begins to flow. A similar parasitic output current would flow if the power device100was configured as a synchronous boost converter half bridge, then a parasitic PNP bipolar in the HS switch102would be triggered.

One brute force approach to avoid triggering the parasitic bipolar114is to oversize the switches102,104. In other words, the switches102,104would need to have a Ron (on resistance) small enough to avoid having mid-node (LX)110swinging below (or above) a diode threshold (Ron*I<Vd), including during worst-case conditions of high current conduction and high temperature.

For example, if the power device's100output current (Iout)118must be limited to a range from 1.95 A to 2.9 A, and the device's100max temperature can reach 200 degrees, then the power device's100low-side switch104should be sized to avoid triggering the parasitic bipolar114at 200 C and 2.9 A.

Calculating this, if an output current (Iout) ripple is 0.5 A, then the power device100should have a worst-case Ron=(700 m−175*2 m)/(2.9+½ I_ripple)˜110 mOhm. Since carrier mobility derates with temperature: mobility derate˜(T/T0){circumflex over ( )}1.5 and if Ron is 20% larger than typical, then a calculated Ron will be about: Ron_Typical_@Room_Temperature=110/(1.2*(500/300){circumflex over ( )}(1.5))˜42.5 mOhm.

The above brute force approach shows that we need a power device of ˜42.5 mOhm for the power to be operative and safe up to 200 C, but from the spec tells us that if need to guarantee 1.95 A @ 125 C with the output current (Iout) ripple of 0.5 A, then the power device's100worst-case Ron=(700 m−100*2 m)/(1.95+½ I_ripple)˜227 mOhm. Taking in to account the mobility derate with temperature and if the slow Ron is 20% larger than typical, then the calculated Ron will be about: Ron_Typical_@Room_Temperature=227/(1.2*(400/300){circumflex over ( )}(1.5))˜122.8 mOhm. Hence we could use smaller devices if the max operating temperature were smaller.

However a problem with this brute force approach is that the larger the Ron, then the larger an area needed for the power device's100switches102,104.

Another approach makes use of isolated devices either using SOI (silicon on insulator) or isolating the switches102,140inside a SiO2 pocket. In this kind of technology the device it is physically isolated by growing it above/inside a SiO2 pocket. No collector is present. This approach both removes the LS switch's104parasitic NPN and the HS switch's102parasitic PNP.

In another approach, guard rings on the supply voltage106can be used to try to avoid large power losses and minimize latch-up problems.

Also the parasitic PNP substrate current's at the HS switch102can be minimized by toggling the substrate body connection so as to disconnect the substrate body from the supply voltage106.

Now discussed, are example power devices that require an area potentially 2 or 3 times smaller than the brute force approach power device100ofFIG.1while still having the current capability needed by the spec at 125 C. The example power devices to be discussed thus could have an area three times smaller while still guaranteeing, for example, a current range of 1.95 A to 2.9 A over various temperature extremes specified in the parametric specification.

Usually devices are requested to be operative up to a preterminal thermal shutdown temperature (e.g. 200 C), however the parametric specification requires a guarantee of the range of current (in this case 1.95 A-2.9 A) only up to 125 C. The example power devices to be discussed optimize the power device's area to fit this parametric specification. Since above 125 C (in worst case) the maximum output current does not need to fit the parametric specification, by folding back the current limit (and avoid triggering the parasitic device), such example power devices can avoid being damaged.

These example power devices control and minimize parasitic currents flowing into a silicon substrate that hosts the power device's switches. These devices detect when parasitic elements are about to turn-on, particularly during high output (Iout) current conduction conditions. Overcurrent protection (i.e. a foldback function) is triggered at a predetermined power device temperature, and reduces an overcurrent limit in proportion to the temperature increase.

FIG.2is a first example current limited power device200(DCDC Buck converter). The current limited power device200includes a high-side (HS) switch202, a low-side (LS) switch204, receiving a supply voltage206and coupled to a ground reference208. Between the HS switch202and the LS switch204is a mid-node (LX)210(e.g. a switching node). The mid-node210is coupled to an inductor212configured to route an output current (Iout)218and present an output voltage (Vout)216at an output of the power device200.

While there are many possible parasitic elements, for purposes of the discussion that follows the focus is on a parasitic diode214across the LS switch204that conducts a parasitic output current under certain circuit operating conditions. This parasitic output current is not desired and becomes part of the output current218.

The current limited power device200also includes a control loop220. The control loop220includes a voltage sensor222, a blanking circuit224, an adjustable output current limit226, a nominal output current limit228, and an output current (Iout) limiter circuit230.

The voltage sensor222is configured to monitor a voltage across the parasitic diode214(e.g. PNP, NPN, etc.) formed by the low-side (LS) switch204and detect when the voltage exceeds the parasitic diode's214threshold turn-on voltage (e.g. in response to a discharge cycle of the power device200). Such detection is shown by a trigger signal232.

The adjustable output current limit226circuit is configured to increment or decrement an output current limit234sent to the output current (Iout) limiter circuit230in response to state changes in the trigger signal232, a low-side gate driver signal236(e.g. QB from the SR_latch), and the nominal output current limit228.

In some example embodiments (e.g. digital embodiments) the adjustable output current limit226includes a counter driven by the trigger signal232from the voltage sensor222. The counter increments or decrements the output current limit234based on the output of the voltage sensor232filtered by the blanking circuit224, that removes spurious signals.

In other example embodiments (e.g. analog embodiments) the adjustable output current limit226includes an integrator (usually a capacitor) driven by the trigger signal232from the voltage sensor222. The adjustable output current limit226increments or decrements the output current limit234based on a charge stored on the capacitor that is increased or decreased by the integrator based on the output of the voltage sensor232.

The presence of an output signal out of the blanking circuit224(during a LS204on-phase) triggers a count down in the counter, causing a decrease of the current limit. The absence of any signal from the blanking circuit224during a LS on-phase triggers a count up in the counter till saturation is reached and the current limit reference becomes the nominal output current limit228. In this way the parasitic current flowing in the parasitic bipolar214is minimized and kept under control.

The blanking circuit224is configured to generate a blanking signal that blocks the voltage sensor's222trigger signal232from reaching the adjustable output current limit226circuit when the low-side (LS) switch204is turned-off. The blanking signal (seeFIG.4A) begins before the low-side (LS) switch204is about to turn-off, and ends after the low-side (LS) switch204gate voltage from the QB pin of the SR-latch has reached a nominal gate voltage (i.e. an LS turn-on time418).

Thus the blanking circuit's224blanking signal masks any false trigger signals232from the voltage sensor222. A duration of the blanking signal408filtering time should be longer than a maximum dead time414possible and preferably longer than the maximum time needed to the LS power switch204to be fully driven (i.e. an LS turn-on time).

The output current (Iout) limiter circuit230is configured to compare the output current (Iout)218using an output current sense signal238from an output current (Iout) sensor to the output current limit234signal. If the output current sense signal238is greater than the output current limit234then the output current (Iout) limiter circuit230sinks current output by a GM source (as shown) and thus lower the output current (Iout)218in order to avoid having large currents flowing the parasitic diode214. As a result, the output current (Iout)218is kept at or below the output current limit234.

In alternate embodiments, the current limit control can be configured to act directly on the logic and switch off the HS as soon as the current limit it is triggered. This can be done with controls loop done in a different ways, usually hysteretic or without Ccomp integrator.

Using the control loop220, the current limited power device200can dynamically respond to increases in temperature that lower the parasitic diode's214threshold turn-on voltage, so as to keep the parasitic output current minimized. The control loop220thus automatically reduces the output current (Iout)218as temperature increases providing a fold-back effect. In some example embodiments, the output current (Iout)218reduction will be linear with the temperature, being controlled by the parasitic diode's214threshold, which decreases ˜2 mV/C.

FIG.3Ais a first parasitic voltage sensing example300for the current limited power device200. In this example300just the interface between the low-side (LS) switch204and the voltage sensor222is shown. Diode (D) is a sensing diode in the voltage sensor222.

As soon as a current (ID) flowing in D detects that the parasitic BD_diode214is about to turn-on, the voltage sensor222outputs the trigger signal232. The current flowing in D in various example embodiments will be a fraction of the current (ID) flowing in the parasitic diode214(e.g. body-drain diode) and will depend on the diodes area ratio: ID=(D_diode_area/BD_diode_area)*IBD_diode. In some example embodiments, a second diode could be added to clamp the source of the LS switch204, in order to avoid damaging it.

FIG.3Bis a second parasitic voltage sensing example302for the current limited power device200. In this example302the interface between the low-side (LS) switch204and the voltage sensor222is also shown. In some example embodiments, the sensing diode (D) is closely matched with the parasitic diode214in the low-side (LS) switch204to improve temperature matching. In this example302a parasitic substrate (e.g. body-drain) diode304is also shown and the sensing diode (D) current will monitor both diodes214,304. In order to minimize the current flowing into the parasitic substrate (e.g. body-drain) diode304a substrate connection to PGND208should be more ohmic than a connection of the LS Switch Source pin to a same pad.

FIG.4Arepresents a first example set of waveforms400for the current limited power device200. The first waveforms400correspond to operation of the first example current limited power device200and include: the LX mid-node210voltage402, inductor212current (Iout)404, LS switch204gate voltage406from OB pin of the SR-latch, a blanking signal408generated by the blanking circuit224, a sensor output signal410from the voltage sensor222, and a filtered sensor output signal412output by the blanking circuit224.

A dead time414when both the low-side (LS) switch204and the high-side (HS) switch are off and a LS switch204turn-on time418is shown inFIG.4A, as is a spurious voltage sensor222output410signal416. As introduced above, the output410of the voltage sensor222needs to be blanked during the dead time414and till the LS gate it is fully driven, in order to avoid generating a false trigger signal232. The duration of the blanking signal408filtering time should be longer than a maximum dead time414possible and preferably longer than the maximum time needed to the LS power switch204to be fully driven (i.e. the LS turn-on time418).

FIG.4Brepresents a second example set of waveforms418for the current limited power device200. A same set of waveforms are shown as for the first example set of waveforms400; however, a range of time shown has increased so that a current limit reduction420generated and modulated by the current limited power device200can be better viewed.

As shown, the Iout current404starts with a larger maximum current that the control loop220reduces so as to minimize the parasitic diode's214turn-on time.

FIG.5represents a second example current limited power device500(DCDC Boost converter). The second current limited power device500includes a high-side (HS) switch502, a low-side (LS) switch504, receiving a supply voltage506and coupled to a ground reference508. Between the HS switch502and the LS switch504is a mid-node (LX)510(e.g. a switching node). The mid-node510is coupled to an inductor512which is itself coupled to receive the supply voltage506. The HS switch502is configured to route an output current (Iout)518and present an output voltage (Vout)516at an output of the power device500.

While there are many possible parasitic diodes, capacitance and such, for purposes of the discussion that follows the focus is on a parasitic diode514across the HS switch502that conducts a parasitic output current under certain circuit operating conditions. This parasitic output current is not desired and becomes part of the output current518.

The current limited power device500also includes a control loop520. The control loop520includes a voltage sensor522, a blanking circuit524, an adjustable output current limit526, a nominal output current limit528, and an output current (Iout) limiter circuit530.

The voltage sensor522is configured to monitor a voltage across the parasitic diode514(e.g. PNP, NPN, etc.) formed by the high-side (HS) switch502and detect when the voltage exceeds the parasitic diode's514threshold turn-on voltage (e.g. in response to a charge cycle of the power device500). Such detection is shown by a trigger signal532.

The output current limit534signal, low-side gate driver signal536, and output current sense signal538operate in a manner similar but symmetrical to that discussed with respect toFIG.2. Thus the second example current limited power device500is substantially the same as the first current limited power device200, except instead of being a DCDC Buck converter, the second current limited power device500is in a DCDC Boost converter configuration.

Various instructions and/or operational steps discussed in the above Figures can be executed in any order, unless a specific order is explicitly stated. Also, those skilled in the art will recognize that while some example sets of instructions/steps have been discussed, the material in this specification can be combined in a variety of ways to yield other examples as well, and are to be understood within a context provided by this detailed description.

In some example embodiments these instructions/steps are implemented as functional and software instructions. In other embodiments, the instructions can be implemented either using logic gates, application specific chips, firmware, as well as other hardware forms.

It will be readily understood that the components of the embodiments as generally described herein and illustrated in the appended figures could be arranged and designed in a wide variety of different configurations. Thus, the detailed description of various embodiments, as represented in the figures, is not intended to limit the scope of the present disclosure, but is merely representative of various embodiments. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the invention is, therefore, indicated by the appended claims rather than by this detailed description. All changes which come within the meaning and range of equivalency of the claims are to be embraced within their scope.

Reference throughout this specification to features, advantages, or similar language does not imply that all of the features and advantages that may be realized with the present invention should be or are in any single embodiment of the invention. Rather, language referring to the features and advantages is understood to mean that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the present invention. Thus, discussions of the features and advantages, and similar language, throughout this specification may, but do not necessarily, refer to the same embodiment.

Furthermore, the described features, advantages, and characteristics of the invention may be combined in any suitable manner in one or more embodiments. One skilled in the relevant art will recognize, in light of the description herein, that the invention can be practiced without one or more of the specific features or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments of the invention.

Reference throughout this specification to “one embodiment,” “an embodiment,” or similar language means that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present invention. Thus, the phrases “in one embodiment,” “in an embodiment,” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment.