Patent ID: 12199051

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In accordance with some embodiments, a super large micro-system is a system-on-wafer (SoW) assembly comprising technology from chip-on-wafers (CoWs), front-to-front and/or front to back system-on-integrated chips (SoICs), and silicon chip-on-wafer-on-substrates (CoWoS). The SoW assembly may have a small form factor and exhibit superior electrical performance due to its compact structure. Wafer scale interposer(s) may comprise integrated passive devices (IPDs), e.g. capacitors, or static random access memory (SRAM) circuitry. The SoW may allow for heterogeneous integration with short interconnects from system-on-chip (SoC) dies to SRAM circuitry, symmetrical molding structure, which may reduce small component warpage, and miniaturization of voltage regulator modules (VRMs) as embedded solenoid inductors in redistribution structures. Integrated fan-out (InFO) packages directly combining Pulse Width Modulation (PWM) circuits for power management and Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) may be attached to the VRMs through the redistribution structure. Wafer scale patterning of the wafer scale interposer and the redistribution structure may allow the super-large micro system to have high performance computing power compared with a conventional printed circuit board (PCB) system. Wafer scale patterning may be performed with image shift exposure or multi-mask exposure in a single layer. The interposer and InFO packages may have fine redistribution layer pitches, which may provide high bandwidth between die-to-die interconnects.

FIG.1illustrates a system-on-wafer100, in accordance with some embodiments. Integrated circuit (IC) dies50(labeled50A,50B, and50C) are encapsulated by an encapsulant112. In some embodiments, the IC dies50A are input/output (I/O) dies, the IC dies50B are memory dies, and the IC dies50C are system-on-chip (SoC) dies. In some embodiments, the IC dies50B may be replaced with stacked high bandwidth memory (HBM) devices that each include multiple memory dies. A wafer scale interposer102is bonded over the IC dies50A,50B, and50C and the encapsulant112. Conductive pads108and an insulating, bonding layer110are on a side of the interposer102facing the IC dies50, which allow the IC dies50to be bonded to the interposer102by hybrid bonding, for example. The interposer102may comprise a bulk silicon wafer with active and passive components, such as static random access memory (SRAM) circuitry comprising transistors connected by metallization layers, capacitors, inductors, diodes, resistors and the like (not shown) formed in the interposer102. The interposer further includes conductive pads114on a surface opposing the IC dies50, and the conductive pads114are physically and electrically coupled to through substrate vias (TSVs)104in the interposer102for connection of the circuitry of the interposer102(e.g., SRAM circuitry) to dies150and through dielectric vias (TDVs)118. The dies150and the TDVs118are on the interposer102and are encapsulated by an encapsulant122. The dies150may be integrated passive device (IPD) dies comprising passive devices such as, e.g., resistors, inductors, capacitors, or the like. A redistribution structure124, also referred to as an interconnect structure124, is on the dies150and the TDVs118and physically and electrically couples the dies150and the TDVs118with components160and external connectors170on a top side of the redistribution structure124. The redistribution structure124comprises solenoid inductors146, which may function as miniaturized voltage regulator modules (VRMs) to provide increased electrical performance. The components160may be dies, chips, or packages such as integrated fan-out (InFO) packages. In some embodiments, the components160comprise Pulse Width Modulation (PWM) circuits that comprise Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) for power management, logic circuits, combinations thereof, or the like. The external connectors170may be electrical and physical interfaces for the system-on-wafer100to external systems such as optical connectors (see below,FIG.37B).

FIG.2illustrates a cross-sectional view of an integrated circuit die50, in accordance with some embodiments. The integrated circuit die50will be packaged in subsequent processing to form a system-on-wafer, such as the system-on-wafers100and400shown inFIGS.1and21. The integrated circuit die50may be a logic die (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management die (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) dies), an application-specific die (e.g., an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), etc.), the like, or combinations thereof.

The integrated circuit die50may be formed in a wafer, which may include different device regions that are singulated in subsequent steps to form a plurality of integrated circuit dies. The integrated circuit die50may be processed according to applicable manufacturing processes to form integrated circuits. For example, the integrated circuit die50includes a semiconductor substrate52, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate52may include other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. The semiconductor substrate52has an active surface (e.g., the surface facing upwards inFIG.1), sometimes called a front side, and an inactive surface (e.g., the surface facing downwards inFIG.1), sometimes called a back side. Devices may be formed at the front surface of the semiconductor substrate52. The devices may be active devices (e.g., transistors, diodes, etc.) or passive devices (e.g., capacitors, resistors, inductors, etc.).

An interconnect structure54is over the semiconductor substrate52, and interconnects the devices to form an integrated circuit. The interconnect structure54may be formed by, for example, metallization patterns in dielectric layers on the semiconductor substrate52. The metallization patterns include metal lines and vias formed in one or more low-k dielectric layers. The metallization patterns of the interconnect structure54are electrically coupled to the devices of the semiconductor substrate52. The integrated circuit die50further includes pads, such as aluminum pads, to which external connections are made. The pads are on the active side of the integrated circuit die50, such as in and/or on the interconnect structure54. One or more passivation films may be on the integrated circuit die50, such as on portions of the interconnect structure54. Die connectors56, such as conductive pillars (for example, formed of a metal such as copper), are physically and electrically coupled to the interconnect structure54. The die connectors56may be formed by, for example, plating, or the like. The die connectors56electrically couple the respective integrated circuits of the integrated circuit die50.

Optionally, solder regions (e.g., solder balls or solder bumps) may be disposed on the pads of the interconnect structure54. The solder balls may be used to perform chip probe (CP) testing on the integrated circuit die50. CP testing may be performed on the integrated circuit die50to ascertain whether the integrated circuit die50is a known good die (KGD). Thus, only integrated circuit dies50, which are KGDs, undergo subsequent processing and packaging, and dies, which fail the CP testing, are not packaged. After testing, the solder regions may be removed in subsequent processing steps.

A dielectric layer58may (or may not) be on the active side of the integrated circuit die50, such as on the passivation films and the die connectors56. The dielectric layer58laterally encapsulates the die connectors56, and the dielectric layer58is laterally coterminous with the integrated circuit die50. Initially, the dielectric layer58may bury the die connectors56, such that the topmost surface of the dielectric layer58is above the topmost surfaces of the die connectors56. In some embodiments where solder regions are disposed on the die connectors56, the dielectric layer58may also bury the solder regions. Alternatively, the solder regions may be removed prior to forming the dielectric layer58.

The dielectric layer58may be a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; the like, or a combination thereof. The dielectric layer58may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. In some embodiments, the die connectors56are exposed through the dielectric layer58during formation of the integrated circuit die50. In some embodiments, the die connectors56remain buried and are exposed during a subsequent process for packaging the integrated circuit die50. Exposing the die connectors56may remove any solder regions that may be present on the die connectors56.

In some embodiments, the integrated circuit die50is a stacked device that includes multiple semiconductor substrates52. For example, the integrated circuit die50may be a memory device such as a hybrid memory cube (HMC) device, a high bandwidth memory (HBM) device, or the like that includes multiple memory dies. In such embodiments, the integrated circuit die50includes multiple semiconductor substrates52interconnected by through-substrate vias (TSVs). Each of the semiconductor substrates52may (or may not) have an interconnect structure54.

FIGS.3-20illustrate cross-sectional views of intermediate steps during a process for forming a system-on-wafer100as shown above inFIG.1, in accordance with some embodiments. As such, the system-on-wafer100is large. For example, the system-on-wafer100can have a surface area in excess of 10,000 mm2.

InFIG.3, conductive pads108and a bonding layer110are formed on a wafer scale interposer102. The interposer102may comprise a bulk silicon wafer. In some embodiments, the interposer102may comprise any semiconductor substrate, ceramic substrate, quartz substrate, or the like. In some embodiments, interposer102comprises a silicon-on-insulator (SOI) or other composite wafer. In some embodiments, active and passive components, such as transistors, diodes, resistors and the like (not shown) may be formed in the interposer102. In some embodiments, transistors and conductive lines and vias forming SRAM circuitry are embedded within the interposer102. For example, active devices may be formed on the semiconductor substrate, and conductive features106may be formed over the active devices. The conductive features106electrically connect the active devices to form one or more SRAM arrays.

Embedded within the interposer102are various metal interconnect features, such as through substrate vias (TSVs)104and conductive features106. A passivation layer62is disposed on a top surface of the interposer102, and input/output (I/O) pads6oare exposed at a top surface of the passivation layer62. The I/O pads6oare physically and electrically coupled to the conductive features106and may comprise a conductive material such as, e.g., copper, titanium, tungsten, aluminum, or the like. The passivation layer62may be a polymer such as PBO, polyimide, BCB, or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; the like, or a combination thereof. The passivation layer62may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like.

Still referring toFIG.3, conductive pads108are formed on the I/O pads60for connection of the TSVs104, conductive features106, and SRAM circuitry embedded within the interposer102to subsequently attached IC dies (see below,FIG.4). The conductive pads108are formed on top surfaces of the I/O pads60. The conductive pads108may exhibit fine pitches in a range of about 10 μm to about 100 μm, which may provide high bandwidth between subsequently attached IC dies50s(see below,FIG.5) and embedded SRAM circuitry components60in the interposer102.

In some embodiments, the conductive pads108are formed with a seed layer and plating process. A seed layer is formed over the interposer102. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD) or the like. A photoresist is then formed and patterned on the seed layer. Wafer scale patterning of the photoresist may be performed with image shift exposure or multi-mask exposure in a single layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the conductive pads108. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material and underlying portions of the seed layer form the conductive pads108. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching.

In some embodiments, the conductive pads108are formed with a damascene process in which the bonding layer no, which is a dielectric layer, is patterned and etched utilizing photolithography techniques to form trenches corresponding to the desired pattern of conductive pads. An optional diffusion barrier and/or optional adhesion layer may be deposited and the trenches may be filled with a conductive material. Suitable materials for the barrier layer includes titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, titanium oxide, or other alternatives, and suitable materials for the conductive material include copper, silver, gold, tungsten, aluminum, combinations thereof, or the like. In an embodiment, the conductive pads108may be formed by depositing a seed layer of copper or a copper alloy, and filling the trenches by electroplating. A chemical mechanical planarization (CMP) process or the like may be used to remove excess conductive material from a surface of the bonding layer no and to planarize the surface for subsequent processing.

FIG.3further shows a bonding layer no formed over the interposer102between the conductive pads108. The bonding layer no may be a dielectric material such as an oxide, e.g. silicon oxide, or the like. The bonding layer no may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. However, any suitable method or materials may be used. After forming the bonding layer110, a planarization process is performed on the bonding layer no to expose the conductive pads108. Top surfaces of bonding layer no and the conductive pads108may be substantially coplanar after the planarization process within process variations. The planarization process may be, for example, a chemical-mechanical polish (CMP), a grinding process, or the like.

InFIG.4, integrated circuit (IC) dies50(labelled as50A,50B, and50C) are attached to the conductive pads108using a suitable bonding method, forming a chip-on-wafer (CoW) structure100with the interposer102. In some embodiments, the IC dies50are attached to the interposer102with hybrid bonds comprising metal-metal bonds, e.g. Cu—Cu or Al—Al bonds, between the die connectors56and oxide-oxide bonds between the bonding layer no and a dielectric layer of the interconnect structure58. Attaching the IC dies50, such as e.g. HBM dies, with metal-metal or hybrid bonds rather than with solder joints may reduce insertion loss.

As an example of hybrid bonding between the IC dies50and the interposer102, the hybrid bonding process starts with aligning and bonding the IC dies50with the interposer102. Bonding may include applying a surface treatment to one or more of the dielectric layers58or the bonding layer110. The surface treatment may include a plasma treatment. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., a rinse with deionized water, or the like) that may be applied to one or more of the dielectric layers58or the bonding layer110. The hybrid bonding process may then proceed to aligning die connectors56with the conductive pads108. When the IC dies50and the interposer102are aligned, the die connectors56may overlap with the corresponding conductive pads108. Next, the hybrid bonding includes a pre-bonding step, during which each IC die50is put in contact with the interposer102. The pre-bonding may be performed at room temperature (e.g., between about 21° C. and about 25° C.). The hybrid bonding process continues with performing an anneal, for example, at a temperature between about 150° C. and about 400° C. for a duration between about 0.5 hours and about 3 hours, so that the metal in the die connectors56(e.g., copper) and the metal of the conductive pads108(e.g., copper) inter-diffuses to each other, and hence the direct metal-to-metal bonding is formed.

A desired type and quantity of integrated circuit dies50(labelled as50A,50B, and50C) are attached to the interposer102. In some embodiments, IC dies50A are a first type of IC die, IC dies50B are a second type of IC die, and IC dies50C are a third type of die such as, e.g. logic dies (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), memory dies (e.g., dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, high bandwidth memory (HBM) dies, etc.), power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, sensor dies, micro-electro-mechanical-system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), application-specific dies (e.g., an application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), etc.), input/output (I/O) dies, or the like. In some embodiments, IC dies50A are I/O dies, IC dies50B are HBM dies, and IC dies50C are SoC dies. Known good dies (KGDs) may be used for the IC dies50A,50B, and50C to provide good system yield.

InFIG.5, an encapsulant112is formed on and around the various components. After formation, the encapsulant112encapsulates the integrated circuit dies50. The encapsulant112may be a molding compound, epoxy, or the like, and may be applied by compression molding, transfer molding, or the like. The encapsulant112may be applied in liquid or semi-liquid form and then subsequently cured. In some embodiments, the encapsulant112is formed over the interposer102such that the integrated circuit dies50are buried or covered, and a planarization process is then performed on the encapsulant112to expose the integrated circuit dies50. Topmost surfaces of the encapsulant112and IC dies50are coplanar after the planarization process. The planarization process may be, for example, a chemical-mechanical polish (CMP).

InFIG.6, the interposer102and encapsulated IC dies50are flipped and placed on a carrier substrate66. In some embodiments, an adhesive layer108is on the carrier substrate66. The carrier substrate66may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate66may be a wafer, such that multiple packages can be formed on the carrier substrate66simultaneously. The adhesive layer108may be removed along with the carrier substrate66from the overlying structures that will be formed in subsequent steps. In some embodiments, the adhesive layer108is any suitable adhesive, epoxy, die attach film (DAF), or the like, and is applied over the surface of the carrier substrate66.

InFIG.7, the back side of the interposer102(the side facing away from the carrier substrate66) is planarized to expose top surfaces of the through substrate vias (TSVs)104. The planarization process may be, for example, a grinding and/or a chemical-mechanical polish (CMP).

InFIG.8, conductive pads114, a bonding layer116, and through dielectric vias (TDVs)118are formed for connection of the TSVs104to a subsequently formed redistribution structure124(see below,FIGS.11-13). The conductive pads114are formed on top surfaces of the TSVs104. As an example to form the conductive pads114, a seed layer is formed over the interposer102. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD) or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the conductive pads114. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material and underlying portions of the seed layer form the conductive pads114. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching.

FIG.8further shows a bonding layer116formed over the interposer102between the conductive pads114. The bonding layer116may be formed using substantially similar methods and materials as the bonding layer no as described above in reference toFIG.3. However, any suitable method or materials may be used. After forming the bonding layer116, a planarization process is performed on the bonding layer116to expose the conductive pads114. Top surfaces of bonding layer116and the conductive pads114may be substantially coplanar after the planarization process within process variations. The planarization process may be, for example, a chemical-mechanical polish (CMP), a grinding process, or the like.

Still referring toFIG.8, through dielectric vias (TDVs)118are formed on some of the conductive pads114. As an example to form the through vias118, a photoresist is formed and patterned on the conductive pads114. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the subsequently formed TDVs118. The patterning forms openings through the photoresist to expose the conductive pads114. The TDVs118are formed by forming a conductive material in the openings of the photoresist and on the conductive pads114. The conductive material of the TDVs118may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. The photoresist removed, such as by an acceptable ashing or stripping process, such as using an oxygen plasma or the like, leaving the TDVs118extending from the conductive pads114.

InFIG.9, dies150are attached to conductive pads114adjacent to the TDVs118, forming a chip-on-wafer (CoW) structure comprising the interposer102with chips, e.g. the dies150, on both sides of the interposer102. In some embodiments, the dies150are integrated passive device (IPD) dies comprising passive devices such as, e.g., resistors, inductors, capacitors, or the like. The dies150may have a substantially similar configuration as the IC die50described with respect toFIG.2but comprising passive device such as resistors, inductors, capacitors and not comprising any active devices such as, e.g., transistors. However, the dies150may be another suitable type of die, e.g. an IC die as described above with respect toFIG.4. In some embodiments, the dies150are attached to the interposer102with hybrid bonds comprising metal-metal bonds, e.g. Cu—Cu bonds or Al—Al bonds, between the conductive pads die connectors56of the dies150and oxide-oxide bonds between the bonding layer116and a dielectric layer of the interconnect structure58of the dies iso. The hybrid bonding process may be substantially similar as the hybrid bonding described above with respect toFIG.4. A desired type and quantity of dies150are attached to the interposer102. In some embodiments, the dies150comprise through substrate vias (TSVs)120extending to topmost surfaces of the dies iso.

InFIG.10, an encapsulant122is formed on and around the various components. After formation, the encapsulant122encapsulates the dies150and the TDVs118. The encapsulant122may be a molding compound, a polymer, an epoxy, silicon oxide filler material, the like, or a combination thereof, and may be applied by compression molding, transfer molding, or the like. The encapsulant122may be applied in liquid or semi-liquid form and then subsequently cured. In some embodiments, the encapsulant122is formed such that the dies150and the TDVs118are buried or covered, and a planarization process is then performed on the encapsulant122to expose the TSVs120of the dies150and the TDVs118. Topmost surfaces of the encapsulant122, TSVs120, and TDVs118are coplanar after the planarization process. The planarization process may be, for example, a chemical-mechanical polish (CMP).

FIG.11illustrates the formation of a bottom portion124A of a redistribution structure124. The bottom portion124A includes dielectric layers126and130and metallization patterns128and132. In some embodiments, the dielectric layers126and130are formed from a same dielectric material, and are formed to a same thickness. Likewise, in some embodiments, the conductive features of the metallization patterns128and132are formed from a same conductive material, and are formed to a same thickness. Bottom portions of the metallization patterns128of redistribution structure124may have a fine pitch in a range of about 1 μm to about 50 μm, which may provide high bandwidth between interconnects of the IC dies50.

As an example of forming the bottom portion124A, the dielectric layer126is deposited on the encapsulant122, dies iso, and TDVs118. In some embodiments, the dielectric layer126is formed of a photo-sensitive material such as PBO, polyimide, BCB, or the like, which may be patterned using a lithography mask. The dielectric layer126may be formed by spin coating, lamination, CVD, the like, or a combination thereof. The dielectric layer126is then patterned. The patterning may be by an acceptable process, such as by exposing the dielectric layer126to light when the dielectric layer126is a photo-sensitive material or by etching using, for example, an anisotropic etch. If the dielectric layer126is a photo-sensitive material, the dielectric layer126can be developed after the exposure.

The metallization pattern128is then formed. The metallization pattern128has line portions (also referred to as conductive lines or traces) on and extending along the major surface of the dielectric layer126, and has via portions (also referred to as conductive vias) extending through the dielectric layer126to physically and electrically couple TDVs118and TSVs120. As an example to form the metallization pattern128, a seed layer is formed over the dielectric layer126and in the openings extending through the dielectric layer126. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD) or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern128. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material and underlying portions of the seed layer form the metallization pattern128. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching.

The dielectric layer130is then deposited on the metallization pattern128and dielectric layer126. The dielectric layer130may be formed in a similar manner and of a similar material as the dielectric layer126. The metallization pattern132is then formed. The metallization pattern132has line portions on and extending along the major surface of the dielectric layer130, and has via portions extending through the dielectric layer130to physically and electrically couple the metallization pattern128. The metallization pattern132may be formed in a similar manner and of a similar material as the metallization pattern128.

InFIG.12, magnetic core sheets134are placed on the dielectric layer130in order to form embedded solenoid inductors in the redistribution structure124. Forming embedded solenoid inductors in the redistribution structure124may be useful in order to form miniaturized voltage regulator modules (VRMs) in the redistribution structure124, which may provide increased electrical performance due to a more compact structure. The magnetic core sheets134comprise a conductive material such as a metal, like copper, titanium, tungsten, aluminum, or the like. The magnetic core sheets134may have a height in a range of about 1 μm to about 10 μm, a width in a range of about 1 mm to about 10 mm, and a length in a range of about 1 mm to about 10 mm. In some embodiments, the magnetic core sheets134are copper coils.

InFIG.13, a top portion124B of the redistribution structure124is formed over the bottom portion124A, completing solenoid inductors146around the magnetic core sheets134. The symmetrical molding structure of the embedded solenoid inductors146may prevent warpage of small components in the solenoid inductors146, such as the magnetic core sheets134. The top portion124B includes dielectric layers138and142and metallization patterns140and144. In some embodiments, the dielectric layers138and142are formed from a same dielectric material, and are formed to a same thickness. Likewise, in some embodiments, the conductive features of the metallization patterns140and144are formed from a same conductive material, and are formed to a same thickness.

The dielectric layer138is deposited on the metallization pattern132, dielectric layer130, and magnetic core sheets134. The dielectric layer138may be formed in a similar manner and of a similar material as the dielectric layer126. The metallization pattern140is then formed. The metallization pattern140has line portions on and extending along the major surface of the dielectric layer138, and has via portions extending through the dielectric layer138to physically and electrically couple the metallization pattern132. The metallization pattern140may be formed in a similar manner and of a similar material as the metallization pattern128.

The dielectric layer142is then deposited on the metallization pattern140and the dielectric layer138. The dielectric layer142may be formed in a similar manner and of a similar material as the dielectric layer126. The metallization pattern144is then formed. The metallization pattern144has line portions on and extending along the major surface of the dielectric layer142, and has via portions extending through the dielectric layer142to physically and electrically couple the metallization pattern140. The metallization pattern144may be formed in a similar manner and of a similar material as the metallization pattern128.

Solenoid inductors146are formed from the magnetic core sheets134and surrounding portions of the metallization patterns128,132,140, and144. The solenoid inductors146are formed to be embedded in the redistribution structure124. This may be useful to form miniaturized voltage regulator modules (VRMs) in the redistribution structure124. The compact structure of the embedded solenoid inductors146may provide increased electrical performance.

InFIG.14, UBMs148that are electrically and physically coupled to the metallization pattern144are formed for external connection to the redistribution structure124. The UBMs148have bump portions on and extending along the major surface of the dielectric layer142. In some embodiments (not illustrated), the UBMs148have via portions extending through the dielectric layer142to physically and electrically couple the metallization pattern144. As a result, the UBMs148are electrically coupled to the dies150, the TDVs118, and the solenoid inductors146. The UBMs148may be formed in a similar manner and of a similar material as the metallization pattern128. In some embodiments, the UBMs148have a different size than the metallization patterns128,132,140, and144.

InFIG.15, the structure is turned over and placed on a tape142and a carrier substrate debonding is performed to detach (or “debond”) the carrier substrate66from the encapsulant112and integrated circuit dies50. In some embodiments, the debonding includes removing the carrier substrate66and adhesive layer108by, e.g., a grinding or planarization process, such as a CMP. After removal, back side surfaces o f the integrated circuit dies50are exposed, and the back side surfaces of the encapsulant112and integrated circuit dies50are level. A cleaning may be performed to remove residues of the adhesive layer108.

InFIG.16, the structure is turned over again and conductive connectors152are formed on the UBMs148. The conductive connectors152may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connectors152may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors152are formed by initially forming a layer of solder or solder paste through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shapes.

InFIG.17, components160and external connectors170are attached to the redistribution structure124. The components160may be dies, chips, or packages such as integrated fan-out (InFO) packages. In some embodiments, the components160comprise Pulse Width Modulation (PWM) circuits that comprise Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) for power management. The external connectors170may include electrical and physical interfaces for the system-on-wafer100to external systems. For example, when the system-on-wafer100is installed as part of a larger external system, such as a data center, the external connectors170may be used to couple the system-on-wafer170to the external system. Examples of external connectors170include optical connectors (see below,FIG.37B), receptors for ribbon cables, flexible printed circuits, or the like.

InFIG.18, an underfill154may be formed to fill the gaps between the components160and external connectors170and the redistribution structure122. The underfill154may be formed by a capillary flow process after the components160and external connectors170are attached, or may be formed by a suitable deposition method before the components160and external connectors170are attached.

InFIG.19, bolt holes156are formed through the system-on-wafer100. The bolt holes156may be formed by a drilling process such as laser drilling, mechanical drilling, or the like. The bolt holes156may be formed by drilling an outline for the bolt holes156with the drilling process, and then removing the material separated by the outline. In some embodiments, the bolt holes156are formed earlier, such as prior to forming the conductive connectors inFIG.16. However, the bolt holes156may be formed at any suitable step of the process.

FIG.20illustrates a cross-sectional view of a system-on-wafer assembly, in accordance with some embodiments. The system-on-wafer assembly is formed by securing the system-on-wafer100between a thermal module200and a mechanical brace300. The thermal module200may be a heat sink, a heat spreader, a cold plate, or the like. The mechanical brace300is a rigid support that may be formed from a material with a high stiffness, such as a metal, e.g., steel, titanium, cobalt, or the like. The mechanical brace300physically engages portions of the redistribution structure124. Warpage of the system-on-wafer100, such as that induced by carrier substrate debonding, may be reduced by clamping the system-on-wafer100between the thermal module200and mechanical brace300. The mechanical brace300may be a grid that has openings exposing the components160and external connectors170, for ease of module installation.

The system-on-wafer100is removed from the tape142and is fastened between the thermal module200and mechanical brace300with bolts202. The bolts202are threaded through the bolt holes144of the system-on-wafer100, through corresponding bolt holes in the thermal module200, and through corresponding bolt holes in the mechanical brace300. Fasteners204are threaded onto the bolts202and tightened to clamp the system-on-wafer100between the thermal module200and mechanical brace300. The fasteners204may be, e.g., nuts that thread to the bolts202. The fasteners204attach to the bolts202at both sides of the system-on-wafer assembly (e.g., at the side having the thermal module200(sometimes referred to as the back side) and at the side having the mechanical brace300(sometimes referred to as the front side)). After being attached, portions of the mechanical brace300are disposed between the components160and/or the external connectors170.

Before fastening together the various components, a thermal interface material (TIM)208may be dispensed on the back side of the system-on-wafer100, physically and thermally coupling the thermal module200to the integrated circuit dies50. In some embodiments, the TIM206is formed of a film comprising indium and a HM03 type material. During fastening, the fasteners204are tightened, thereby increasing the mechanical force applied to the system-on-wafer100by the thermal module200and the mechanical brace300. The fasteners204are tightened until the thermal module200exerts a desired amount of pressure on the TIM206.

FIG.21illustrates a system-on-wafer400, in accordance with some alternate embodiments. The system-on-wafer400may be similar to the system-on-wafer100described above in reference toFIGS.1andFIGS.4-19where like reference numerals indicate like elements formed using like processes. Integrated circuit (IC) dies50(labeled50A and50B) and packages450are encapsulated by an encapsulant112. In some embodiments, the IC dies50A are input/output (I/O) dies, the IC dies50B are stacked high bandwidth memory (HBM) devices that each include multiple memory dies, and the IC dies50E are hybrid SRAM/SoC dies that comprise SoC circuitry, SRAM circuitry, and through substrate vias (TSVs) that may electrically couple the IC dies50E to a wafer scale interposer102over the IC dies50A,50B, and50E and the encapsulant112. Conductive pads408and a bonding layer410are on a side of the interposer402facing the IC dies50. The interposer402may comprise a bulk silicon wafer with active and/or passive components, such as e.g. diodes, capacitors, inductors, resistors and the like (not shown) formed in the interposer402. Conductive pads414are physically and electrically coupled to through substrate vias (TSVs)404for connection of the IPD circuitry to a redistribution structure424, also referred to as an interconnect structure424, on the interposer402. The redistribution structure424physically and electrically couples the interposer402with components160and external connectors170on a top side of the redistribution structure124. The redistribution structure424comprises solenoid inductors446, which may function as miniaturized voltage regulator modules (VRMs) to provide increased electrical performance. The components160may be may be InFO packages comprising, e.g., PWM circuits for power management and MOSFETs. The external connectors170may be electrical and physical interfaces for the system-on-wafer400to external systems such as optical connectors (see below,FIG.37B).

FIG.22illustrates a cross-sectional view of a package450, in accordance with some embodiments. The package450comprises an IC die460stacked on and bonded to another IC die470. The IC die460may be a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management die (e.g., power management integrated circuit (PMIC) die), and the IC die470may be a logic die e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.). In some embodiments, the IC die460is an SRAM die and the IC die470is a SoC die.

In some embodiments, the IC dies460and470have similar structures and materials as the IC die50described above with respect toFIG.2. The IC die460has a semiconductor substrate462, an interconnect structure464over the semiconductor substrate462, die connectors466physically and electrically coupled to the interconnect structure464, and a dielectric layer468over the interconnect structure464and laterally encapsulating the die connectors466. The IC die460may also have through substrate vias (TSVs)463extending through the semiconductor substrate462and physically and electrically coupling the interconnect structure464. The IC die470has a semiconductor substrate472, an interconnect structure474over the semiconductor substrate472, die connectors476physically and electrically coupled to the interconnect structure474, and a dielectric layer478over the interconnect structure474and laterally encapsulating the die connectors476.

The IC die460and the IC die470may be bonded by a suitable bonding method between the respective dielectric layers468and478and the respective die connectors466and476, such as hybrid bonding. The hybrid bonding may be performed in a similar manner as the hybrid bonding between the IC dies50and the interposer102as described above with respect toFIG.4.

After bonding the die460to the IC die470, through dielectric vias (TDVs)454are formed on the die connectors476. The TDVs454may be formed in a similar manner as the TDVs118as described above with respect toFIG.8. The IC die46oand the TDVs454are then encapsulated by an encapsulant452, which may be formed in a similar manner as the encapsulant112as described above with respect toFIG.5. In some embodiments, the encapsulant452is formed over the IC die460and the TDVs454such that the IC die460and the TDVs454are buried or covered, and a planarization process is then performed on the encapsulant452to expose the TDVs454and the TSVs463of the IC die460. Topmost surfaces of the encapsulant452, TDVs454, semiconductor substrate462, and the TSVs463are coplanar after the planarization process. The planarization process may be, for example, a chemical-mechanical polish (CMP).

Conductive pads456are then formed over top surfaces of the TDVs454and the TSVs463and a bonding layer is formed over the encapsulant452and the semiconductor substrate462between the conductive pads456. The conductive pads456and the bonding layer458may be formed using substantially similar methods and materials as the conductive pads108and the bonding layer no as described above in reference toFIG.3. However, any suitable method or materials may be used. The conductive pads456and the bonding layer458may allow package450, comprising the IC dies460and470, to be hybrid bonded to, e.g., an interposer402as described below with respect toFIG.24. The conductive pads456may be electrically connected to the TDVs454as well as circuitry of the IC dies460and470.

FIGS.23-35illustrate cross-sectional views of intermediate steps during a process for forming a system-on-wafer400as shown above inFIG.21, in accordance with some embodiments. As such, the system-on-wafer400is large. For example, the system-on-wafer400can have a surface area in excess of 10,000 mm2.

InFIG.23, conductive pads408and a bonding layer410are formed on a wafer scale interposer402. The interposer402may be a semiconductor substrate or wafer. The interposer402may comprises a bulk silicon wafer. In some embodiments, the interposer402may comprise any semiconductor substrate, ceramic substrate, quartz substrate, or the like. In some embodiments, interposer102comprises a silicon-on-insulator (SOI) or other composite wafer. In some embodiments, various metal interconnect features, such as through substrate vias (TSVs)404and conductive features406are embedded in the interposer402. The conductive features406may include embedded passive components, such as resistors, inductors, capacitors, and the like (not shown). In some embodiments, the interposer402may be free of any active components such as transistors, or the like.

Further referring toFIG.23, a passivation layer72is disposed on a top surface of the interposer402, and input/output (I/O) pads70are exposed at a top surface of the passivation layer72. The I/O pads70are physically and electrically coupled to the conductive features406and may comprise a conductive material such as, e.g., copper, titanium, tungsten, aluminum, or the like. The passivation layer72may be a polymer such as PBO, polyimide, BCB, or the like; a nitride such as silicon nitride or the like; an oxide such as silicon oxide, PSG, BSG, BPSG, or the like; the like, or a combination thereof. The passivation layer72may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like.

Still referring toFIG.23, conductive pads408are formed on the I/O pads70for connection of the metallization pattern72to subsequently attached IC dies (see below,FIG.24). The conductive pads408are formed on top surfaces of the IPD components60or the metallization pattern62. The conductive pads108may exhibit fine pitches, which may provide high bandwidth between subsequently attached IC dies50(see below,FIG.24) and passive devices, such as e.g. capacitors, embedded in the interposer102. The conductive pads408may be formed with substantially similar methods and materials as the conductive pads108as described above with respect toFIG.4.

FIG.23further shows a bonding layer410formed over the interposer402between the conductive pads408. The bonding layer410may be formed with substantially similar methods and materials as the bonding layer no as described above with respect toFIG.4. However, any suitable methods or materials may be used. After forming the bonding layer410, a planarization process is performed on the bonding layer410to expose the conductive pads408. Top surfaces of the bonding layer410and the conductive pads408may be substantially coplanar after the planarization process within process variations. The planarization process may be, for example, a chemical-mechanical polish (CMP), a grinding process, or the like.

InFIG.24, integrated circuit (IC) dies50(labeled as50A and50B) and packages450(see above,FIG.22) are attached to the conductive pads408using a suitable bonding method, forming a chip-on-wafer (CoW) structure400with the interposer402. In some embodiments, the IC dies50and the packages450are attached to the interposer402with hybrid bonds comprising metal-metal bonds, e.g. Cu—Cu bonds or Al—Al bonds, between the die connectors56and the conductive pads408and between the conductive pads456and the conductive pads408, oxide-oxide bonds between the bonding layer no and the dielectric58of the IC dies50and between the bonding layer no and the bonding layer456of the packages450. Attaching the IC dies5o, such as e.g. HBM dies, and the packages450with metal-metal or hybrid bonds rather than with solder joints may reduce insertion loss. The hybrid bonding process may be substantially similar as the hybrid bonding described above with respect toFIG.4. A desired type and quantity of integrated circuit dies50and packages450are attached to the interposer402. In some embodiments, IC dies50A are a first type of IC die and IC dies50B are a second type of IC die such as, e.g. logic dies (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), memory dies (e.g., dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, high bandwidth memory (HBM) dies, etc.), power management dies (e.g., power management integrated circuit (PMIC) dies), radio frequency (RF) dies, sensor dies, micro-electro-mechanical-system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) dies), front-end dies (e.g., analog front-end (AFE) dies), application-specific dies (e.g., an application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), etc.), input/output (I/O) dies, integrated passive device (IPD) dies, or the like. In some embodiments, IC dies50A are I/O dies, and IC dies50B are HBM dies. Known good dies (KGDs) may be used for the IC dies50A and50B to provide good system yield.

InFIG.25, an encapsulant112is formed on and around the various components. After formation, the encapsulant112encapsulates the integrated circuit dies50and packages450. The encapsulant112may be a molding compound, epoxy, or the like, and may be applied by compression molding, transfer molding, or the like. The encapsulant112may be applied in liquid or semi-liquid form and then subsequently cured. In some embodiments, the encapsulant112is formed over the interposer402such that the integrated circuit dies50and the packages450are buried or covered, and a planarization process is then performed on the encapsulant112to expose the integrated circuit dies50and the packages450. Topmost surfaces of the encapsulant112, IC dies50, and packages450are coplanar after the planarization process. The planarization process may be, for example, a chemical-mechanical polish (CMP).

InFIG.26, the interposer402and encapsulated IC dies50and packages450are flipped and placed on a carrier substrate66. In some embodiments, an adhesive layer108is on the carrier substrate66. The carrier substrate66may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate66may be a wafer, such that multiple packages can be formed on the carrier substrate66simultaneously. The adhesive layer108may be removed along with the carrier substrate66from the overlying structures that will be formed in subsequent steps. In some embodiments, the adhesive layer108is any suitable adhesive, epoxy, die attach film (DAF), or the like, and is applied over the surface of the carrier substrate66.

InFIG.27, the back side of the interposer402(the side facing away from the carrier substrate66) is planarized to expose top surfaces of the through substrate vias (TSVs)404. The planarization process may be, for example, a grinding and/or a chemical-mechanical polish (CMP).

FIG.28illustrates the formation of a bottom portion424A of a redistribution structure424. The bottom portion424A includes dielectric layers414,426, and430and metallization patterns416,428, and432. In some embodiments, the dielectric layers414,426, and430are formed from a same dielectric material, and are formed to a same thickness. Likewise, in some embodiments, the conductive features of the metallization patterns416,428, and432are formed from a same conductive material, and are formed to a same thickness. Bottom portions of the metallization patterns416of the redistribution structure424may have a fine pitch in a range of about 10 μm to about 100 μm, which may provide high bandwidth between interconnects of the IC dies50.

As an example of forming the bottom portion424A, the dielectric layer41426is deposited on the back side of the interposer402. In some embodiments, the dielectric layer414is formed of a photo-sensitive material such as PBO, polyimide, BCB, or the like, which may be patterned using a lithography mask. The dielectric layer414may be formed by spin coating, lamination, CVD, the like, or a combination thereof. The dielectric layer414is then patterned. The patterning may be by an acceptable process, such as by exposing the dielectric layer414to light when the dielectric layer414is a photo-sensitive material or by etching using, for example, an anisotropic etch. If the dielectric layer414is a photo-sensitive material, the dielectric layer414can be developed after the exposure.

The metallization pattern416is then formed. The metallization pattern416has line portions (also referred to as conductive lines or traces) on and extending along the major surface of the dielectric layer414, and has via portions (also referred to as conductive vias) extending through the dielectric layer414426to physically and electrically couple the TSVs404. As an example to form the metallization pattern416, a seed layer is formed over the dielectric layer416and in the openings extending through the dielectric layer416to top surfaces of the TSVs404. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD) or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern416. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may comprise a metal, like copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material and underlying portions of the seed layer form the metallization pattern416. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching.

The dielectric layer426is then deposited on the metallization pattern416and dielectric layer414. The dielectric layer426may be formed in a similar manner and of a similar material as the dielectric layer414. The metallization pattern428is then formed. The metallization pattern428has line portions on and extending along the major surface of the dielectric layer426, and has via portions extending through the dielectric layer426to physically and electrically couple the metallization pattern416. The metallization pattern428may be formed in a similar manner and of a similar material as the metallization pattern416.

The dielectric layer430is then deposited on the metallization pattern428and dielectric layer426. The dielectric layer430may be formed in a similar manner and of a similar material as the dielectric layer414. The metallization pattern432is then formed. The metallization pattern432has line portions on and extending along the major surface of the dielectric layer430, and has via portions extending through the dielectric layer430to physically and electrically couple the metallization pattern428. The metallization pattern432may be formed in a similar manner and of a similar material as the metallization pattern416.

InFIG.29, magnetic core sheets434are placed on the dielectric layer430in order to form embedded solenoid inductors in the redistribution structure424. Forming embedded solenoid inductors in the redistribution structure424may be useful in order to form miniaturized voltage regulator modules (VRMs) in the redistribution structure424, which may provide increased electrical performance due to a more compact structure. The magnetic core sheets434comprise a conductive material such as a metal, like copper, titanium, tungsten, aluminum, or the like. The magnetic core sheets434may have a height in a range of about 1 μm to about 10 μm, a width in a range of about 1 mm to about 10 mm, and a length in a range of about 1 mm to about 10 mm. In some embodiments, the magnetic core sheets434are copper coils.

InFIG.30, a top portion424B of the redistribution structure424is formed over the bottom portion424A, completing solenoid inductors446around the magnetic core sheets434, and UBMs448are formed on the redistribution structure424. The symmetrical molding structure of the embedded solenoid inductors446may prevent warpage of small components in the solenoid inductors446, such as the magnetic core sheets434. The top portion424B includes dielectric layers438and442and metallization patterns440and444. In some embodiments, the dielectric layers438and442are formed from a same dielectric material, and are formed to the same thickness as each other, such as in a range of about 1 μm to about 50 μm. Likewise, in some embodiments, the conductive features of the metallization patterns440and444are formed from a same conductive material, and are formed to a same thickness as each other, such as in a range of about 1 μm to about 30 μm.

The dielectric layer438is deposited on the metallization pattern432, dielectric layer430, and magnetic core sheets434. The dielectric layer438may be formed in a similar manner and of a similar material as the dielectric layer414. The metallization pattern440is then formed. The metallization pattern440has line portions on and extending along the major surface of the dielectric layer438, and has via portions extending through the dielectric layer438to physically and electrically couple the metallization pattern432. The metallization pattern440may be formed in a similar manner and of a similar material as the metallization pattern416.

The dielectric layer442is then deposited on the metallization pattern440and the dielectric layer438. The dielectric layer142may be formed in a similar manner and of a similar material as the dielectric layer414. The metallization pattern444is then formed. The metallization pattern444has line portions on and extending along the major surface of the dielectric layer442, and has via portions extending through the dielectric layer442to physically and electrically couple the metallization pattern440. The metallization pattern444may be formed in a similar manner and of a similar material as the metallization pattern416.

Solenoid inductors446are formed from the magnetic core sheets434and surrounding portions of the metallization patterns428,432,440, and444. The solenoid inductors446are formed to be embedded in the redistribution structure424. This may be useful to form miniaturized voltage regulator modules (VRMs) in the redistribution structure424. The compact structure of the embedded solenoid inductors446may provide increased electrical performance.

Further referring toFIG.30, UBMs148that are electrically and physically coupled to the metallization pattern444are formed for external connection to the redistribution structure424. The UBMs448have bump portions on and extending along the major surface of the dielectric layer442. In some embodiments (not illustrated), the UBMs448have via portions extending through the dielectric layer442to physically and electrically couple the metallization pattern444. As a result, the UBMs448are electrically coupled to the solenoid inductors446and the interposer402. The UBMs448may be formed in a similar manner and of a similar material as the metallization pattern416. In some embodiments, the UBMs448have a different size than the metallization patterns416,428,432,440, and444.

InFIG.31, the structure is turned over and placed on a tape142and a carrier substrate debonding is performed to detach (or “debond”) the carrier substrate66from the encapsulant112and integrated circuit dies50. In some embodiments, the debonding includes removing the carrier substrate66and adhesive layer108by, e.g., a grinding or planarization process, such as a CMP. After removal, back side surfaces of the integrated circuit dies50are exposed, and the back side surfaces of the encapsulant112and integrated circuit dies50are level. A cleaning may be performed to remove residues of the adhesive layer108.

InFIG.32, the structure is turned over again and conductive connectors152are formed on the UBMs148. The conductive connectors152may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connectors152may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors152are formed by initially forming a layer of solder or solder paste through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shapes.

InFIG.33, components160and external connectors170are attached to the redistribution structure424. The components160may be dies, chips, or packages such as integrated fan-out (InFO) packages. In some embodiments, the components160comprise Pulse Width Modulation (PWM) circuits that comprise Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) for power management. The external connectors170are electrical and physical interfaces for the system-on-wafer100to external systems. For example, when the system-on-wafer100is installed as part of a larger external system, such as a data center, the external connectors170may be used to couple the system-on-wafer170to the external system. Examples of external connectors170include optical connectors (see below,FIG.38), receptors for ribbon cables, flexible printed circuits, or the like.

InFIG.34, an underfill154may be formed to fill the gaps between the components160and external connectors170and the redistribution structure122. The underfill154may be formed by a capillary flow process after the components160and external connectors170are attached, or may be formed by a suitable deposition method before the components160and external connectors170are attached.

InFIG.35, bolt holes156are formed through the system-on-wafer400. The bolt holes156may be formed by a drilling process such as laser drilling, mechanical drilling, or the like. The bolt holes156may be formed by drilling an outline for the bolt holes156with the drilling process, and then removing the material separated by the outline. In some embodiments, the bolt holes156are formed earlier, such as prior to forming the conductive connectors inFIG.32. However, the bolt holes156may be formed at any suitable step of the process.

FIG.36illustrates a cross-sectional view of a system-on-wafer assembly, in accordance with some embodiments. The system-on-wafer assembly is formed by securing the system-on-wafer400between a thermal module200and a mechanical brace300. The thermal module200may be a heat sink, a heat spreader, a cold plate, or the like. The mechanical brace30ois a rigid support that may be formed from a material with a high stiffness, such as a metal, e.g., steel, titanium, cobalt, or the like. The mechanical brace30ophysically engages portions of the redistribution structure424. Warpage of the system-on-wafer400, such as that induced by carrier substrate debonding, may be reduced by clamping the system-on-wafer400between the thermal module200and mechanical brace300. The mechanical brace30omay be a grid that has openings exposing components160and external connectors170, for ease of module installation.

The system-on-wafer400is removed from the tape142and is fastened between the thermal module200and mechanical brace30owith bolts202. The bolts202are threaded through the bolt holes156of the system-on-wafer100, through corresponding bolt holes in the thermal module200, and through corresponding bolt holes in the mechanical brace300. Fasteners204are threaded onto the bolts202and tightened to clamp the system-on-wafer100between the thermal module200and mechanical brace300. The fasteners204may be, e.g., nuts that thread to the bolts202. The fasteners204attach to the bolts202at both sides of the system-on-wafer assembly (e.g., at the side having the thermal module200(sometimes referred to as the back side) and at the side having the mechanical brace300(sometimes referred to as the front side)). After being attached, portions of the mechanical brace300are disposed between the components160and/or the external connectors170.

Before fastening together the various components, a thermal interface material (TIM)208may be dispensed on the back side of the system-on-wafer400, physically and thermally coupling the thermal module200to the integrated circuit dies50. In some embodiments, the TIM206is formed of a film comprising indium and a HM03 type material. During fastening, the fasteners204are tightened, thereby increasing the mechanical force applied to the system-on-wafer400by the thermal module200and the mechanical brace300. The fasteners204are tightened until the thermal module200exerts a desired amount of pressure on the TIM206.

FIG.37illustrates a system-on-wafer500, in accordance with some embodiments. The system-on-wafer450may be similar to the system-on-wafer400described above in reference toFIG.33, where like reference numerals indicate like elements formed using like processes, but with optical connectors600, as described below with respect toFIG.39, attached to the bottom side of the interposer402in place of the IC dies50A and encapsulated by the encapsulant112, as well as being attached to the top of the redistribution structure424. In some embodiments, the functions of the IC dies50A and packages450are combined in packages550, as described below in respect toFIG.38, that are hybrid bonded to the interposer402. Placing I/O circuitry with SRAM circuitry together in the packages550may provide minimal distance between the SRAM and I/O circuitry, which may lead to improved system efficiency. Having optical connections600attached on both sides of the system-on-wafer500may allow for high bandwidth connections to external devices.

FIG.38illustrates a cross-sectional view of a package550that may be part of a system-on-wafer500as illustrated above byFIG.37, in accordance with some embodiments. The package550comprises an IC die590stacked on a package580, and the package580comprises IC dies460and470. In some embodiments, the package580is similar to the package450described above in reference toFIG.22, where like reference numerals indicate like elements formed using like processes. The IC die460may be a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management die (e.g., power management integrated circuit (PMIC) die), the IC die470may be a logic die e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), and the IC die590may be an input/output (I/O) die. In some embodiments, the IC die460is an SRAM die, the IC die470is a SoC die, and the IC die590is an I/O die.

In some embodiments, the IC die590has similar structures and materials as the IC die50described above with respect toFIG.2. The IC die590has a semiconductor substrate592, an interconnect structure594over the semiconductor substrate592, die connectors596physically and electrically coupled to the interconnect structure594, and a dielectric layer598over the interconnect structure594and laterally encapsulating the die connectors596. The IC die590may also have through substrate vias (TSVs)555extending through the semiconductor substrate592and physically and electrically coupling the interconnect structure594.

The package580and the IC die590may be bonded by a suitable bonding method between the bonding layer458and the dielectric layer468and between the conductive pads456and the die connectors596, such as hybrid bonding. The hybrid bonding may be performed in a similar manner as the hybrid bonding between the IC dies50and the interposer102as described above with respect toFIG.4.

Conductive pads556are then formed over top surfaces of the TSVs555and a bonding layer558is formed over the semiconductor substrate592between the conductive pads456. The conductive pads556and the bonding layer558may be formed using substantially similar methods and materials as the conductive pads108and the bonding layer no as described above in reference toFIG.3. However, any suitable method or materials may be used. The conductive pads556and the bonding layer558may allow package550, comprising the IC dies460,470, and590, to be hybrid bonded to, e.g. an interposer402as described above with respect toFIG.37.

FIG.39illustrates a detailed view of an example of an optical connector600, in accordance with some embodiments. Optical connectors such as an optical connector600may be integrated into any of the system-on-wafers shown above, such as in the system-on-wafer500(see above,FIG.37), or in the system-on-wafer100(see above,FIG.1) or the system-on-wafer400(see above,FIG.21) in place of an external connector170. The optical connector600comprises a grating coupler607A configured to optically couple to an optical fiber650. The optical fiber650may be mounted to the optical connector600using an optical glue652or the like. The optical fiber650may be mounted at an angle with respect to the vertical axis or may be laterally offset from the grating coupler607A. A grating coupler607A may be located in a photonic routing structure610near the edges of optical connector600or away from the edges of the optical connector600. The optical signals and/or optical power transmitted between the vertically mounted optical fiber650and the grating coupler607A are transmitted through the dielectric layer608, the dielectric layers615in the interconnect structure620, and the dielectric material626formed over the grating coupler607A. For example, optical signals may be transmitted from the optical fiber650to the grating coupler607A and into the waveguides604, wherein the optical signals may be detected by a photodetector606A and transmitted as electrical signals through conductive features614into an electronic die622. Optical signals generated within the waveguides604by the modulator606B may similarly be transmitted from the grating coupler607A to the vertically mounted optical fiber650. Conductive pads628may be physically and electrically coupled to respective conductive pads508or conductive connectors152in the system-on-wafer500(see above,FIG.37). Vias612extending through the photonic routing structure610and through the substrate602physically and electrically couple the conductive pads628with the conductive features614in order to electrically connect the electronic die622with the system-on-wafer500.

Embodiments may achieve advantages. System-on-wafer (SoW) assemblies may have small form factors, allowing for compact structure to exhibit superior electrical performance. Integrated passive devices (IPDs), e.g. capacitors, or static random access memory (SRAM) circuitry may be embedded into wafer scale interposer(s). Heterogeneous integration with short interconnects from system-on-chip (SoC) dies to SRAM circuitry may be included in the SoW structure. Symmetrical molding structure may reduce small component warpage. Embedded solenoid inductors may allow for redistribution structures miniaturization of voltage regulator modules (VRMs). The super-large micro system may have high performance computing power compared with a conventional printed circuit board (PCB) system due to wafer scale patterning of the wafer scale interposer and the redistribution structure. The wafer scale patterning may be performed with multi-mask exposure in a single layer or image shift exposure. High bandwidth between die-to-die interconnects may be provided by fine redistribution layer pitches of the interposer and InFO packages.

In accordance with an embodiment, a semiconductor device includes: a first plurality of dies encapsulated by an encapsulant; an interposer over the first plurality of dies, the interposer including a plurality of embedded passive components, each die of the first plurality of dies being electrically connected to the interposer; an interconnect structure over and electrically connected to the interposer, the interconnect structure including a solenoid inductor in a metallization layer of the interconnect structure; and a plurality of conductive pads on a surface of the interconnect structure opposite the interposer. In an embodiment, the semiconductor device further includes a first package encapsulated by the encapsulant, the first package being electrically connected to the interposer, the first package including static random access memory (SRAM) circuitry. In an embodiment, the SRAM circuitry is in a first die of the first package and a second die of the first package includes a system-on-chip. In an embodiment, a third die of the first package includes an input/output device. In an embodiment, a first component is attached to conductive pads of the plurality of conductive pads, the first component including a pulse width modulation (PWM) controller. In an embodiment, the first component is electrically coupled to the solenoid inductor, the solenoid inductor being a voltage regulator module for the first component. In an embodiment, a first connector is attached to conductive pads of the plurality of conductive pads. In an embodiment, the first connector is a first optical connector. In an embodiment, a second optical connector is electrically coupled to a respective embedded passive component of the plurality of embedded passive components of the interposer, the second optical connector being on an opposite side of the interposer from the first optical connector. In an embodiment, the second optical connector is encapsulated by the encapsulant.

In accordance with another embodiment, a semiconductor device includes: a first molding compound around a first die and a second die; an interposer over the first die, the second die, and the first molding compound, the interposer including static random access memory (SRAM) circuitry, the first die and the second die each being electrically coupled to the interposer; a conductive via on the interposer; a third die bonded to and electrically coupled to the interposer; a second molding compound around the conductive via and the third die; an interconnect structure over the conductive via, the third die, and the second molding compound, the interconnect structure including a solenoid inductor; and a plurality of contact pads on the interconnect structure opposite the conductive via, the third die, and the second molding compound. In an embodiment, the interposer is a wafer, the wafer including silicon. In an embodiment, the third die is an integrated passive device. In an embodiment, the first die is electrically coupled to the interposer with a metal-metal bond.

In accordance with yet another embodiment, a method of forming a semiconductor device includes: bonding a first plurality of dies to an interposer, the interposer including a plurality of conductive features, each die of the respective plurality of dies being bonded to a respective conductive feature of the plurality of conductive features; encapsulating the first plurality of dies with an encapsulant; forming a first interconnect over a first surface of the interposer, the first surface being opposite the first plurality of dies, forming the first interconnect including: forming a bottom portion of the first interconnect; placing a magnetic core on the bottom portion of the first interconnect; and forming a top portion of the first interconnect over the bottom portion of the first interconnect and the magnetic core, wherein forming the top portion forms a solenoid inductor including the magnetic core; forming a first plurality of contact pads on the first interconnect opposite the interposer; and attaching a first device to the first interconnect, the first device being electrically coupled to contact pads of the first plurality of contact pads. In an embodiment, bonding the first plurality of dies to the interposer includes forming a metal-metal bond and forming an oxide-oxide bond. In an embodiment, a die of the first plurality of dies includes static random access memory (SRAM) circuitry. In an embodiment, the interposer includes a plurality of embedded passive components. In an embodiment, the interposer includes static random access memory (SRAM) circuitry. In an embodiment, the method further includes: forming a conductive via on the interposer; bonding an integrated passive device (IPD) die to the interposer; and encapsulating the conductive via and the IPD die with a second encapsulant.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.