Patent ID: 12243798

DETAILED DESCRIPTION OF EMBODIMENTS

The following will now describe a semiconductor package according to the present inventive concepts with reference to the accompanying drawings.

FIG.1illustrates a plan view showing a semiconductor package according to some embodiments of the present inventive concepts.FIGS.2to4illustrate cross-sectional views showing a semiconductor package according to some embodiments of the present inventive concepts.FIG.2corresponds to a cross section taken along line A-A′ ofFIG.1.FIGS.3and4correspond to a cross section taken along line B-B′ ofFIG.1.FIG.5illustrates a plan view showing deformation of a semiconductor package according to some embodiments of the present inventive concepts.FIGS.6and7illustrate cross-sectional views showing deformation of a semiconductor package according to some embodiments of the present inventive concepts.FIG.6corresponds to a cross-section taken along line C-C′ ofFIG.5.FIG.7corresponds to a cross section taken along line D-D′ ofFIG.5.

Referring toFIGS.1,2, and3, a circuit substrate100may be provided. The circuit substrate100may be a flexible film type substrate. The circuit substrate100may include a dielectric material. For example, the circuit substrate100may include a substrate formed of a flexible material, such as polyimide (PI). Alternatively, the circuit substrate100may include a rigid substrate. The circuit substrate100may include or may be, for example, a printed circuit board (PCB), a redistribution substrate in which a dielectric pattern and a conductive pattern are stacked alternately with each other, a semiconductor wafer, or any other suitable substrate.

A semiconductor chip200may be provided on the circuit substrate100. The semiconductor chip200may be mounted on a bonding terminal such as a lead frame or a pad provided on the circuit substrate100. The semiconductor chip200may have a top surface200u substantially parallel to a top surface100aof the circuit substrate100. The present inventive concepts, however, are not limited thereto. The semiconductor chip200may have a rectangular shape in a plan view. For example, the semiconductor chip200may have a first length L1in a first direction D1greater than a second length L2in a second direction D2. The first direction D1and the second direction D2may be parallel to the top surface100aof the circuit substrate100and may be orthogonal to each other. The semiconductor chip200may have short lateral surfaces200sthat are opposite to each other in the first direction D1and long lateral surfaces200lthat are opposite to each other in the second direction D2. In this description, the term “short lateral surface” may indicate a lateral surface which has a width/length less than those of other lateral surfaces of a certain component, and the term “long lateral surface” may indicate a lateral surface which has a width/length greater than those of other lateral surfaces of the certain component. In addition, the term “width of a lateral surface” may denote a width obtained when the lateral surface is measured in a direction parallel to a top surface perpendicular to the lateral surface. A width (e.g., identical to the first length L1) of each long lateral surface200lof the semiconductor chip200may be greater than a width (e.g., identical to the second length L2) of each short lateral surface200sof the semiconductor chip200. The semiconductor chip200may have a rectangular hexahedral shape (or bar shape) that extends lengthwise in the first direction D1. In this description, it is not required that the semiconductor chip200should have an exact rectangular hexahedral shape (or bar shape), and the semiconductor chip200may have any suitable shape in which a length in the first direction D1is greater than a length in the second direction D2. The semiconductor chip200may be a transistor such as junction transistor or field effect transistor, a diode such as rectification diode, light emitting diode, or photodiode, a memory element, or an active element such as integrated circuit. Alternatively, the semiconductor chip200may be a passive element such as condenser, resistor, or coil.

Terms such as “same,” “equal,” “parallel,” “perpendicular,” “planar,” or “coplanar,” as used herein encompass identicality or near identicality including variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise.

An item, layer, or portion of an item or layer described as extending “lengthwise” in a particular direction has a length in the particular direction and a width perpendicular to that direction, where the length is greater than the width.

A thermal radiation film300may be provided on the circuit substrate100. The thermal radiation film300may cover the semiconductor chip200. The thermal radiation film300may closely attach the semiconductor chip200to the circuit substrate100, and may outwardly discharge heat received from the semiconductor chip200. The thermal radiation film300may have a planar shape larger than that of the semiconductor chip200. Planar shapes in the present disclosure may mean shapes in plan views. For example, the thermal radiation film300may have a larger area than the semiconductor chip200in a plan view. The thermal radiation film300may have a length in the first direction D1greater than a length in the second direction D2. For example, the thermal radiation film300may have a rectangular shape in a plan view. The thermal radiation film300may have short sides300sthat are opposite to each other in the first direction D1and long sides3001that are opposite to each other in the second direction D2. The thermal radiation film300may have first ends or the short sides300sthat face the short lateral surfaces200sof the semiconductor chip200, and may also have second ends or the long sides3001that face the long lateral surfaces200lof the semiconductor chip200. In this description, the term “short side” may indicate a side which has a length less than those of other sides of a certain shape, and the term “long side” may indicate a side which has a length greater than those of other sides of the certain shape. In this description, the thermal radiation film300may have various planar shapes in which a length in the first direction D1is greater than a length in the second direction D2. The planar shapes in the present description may be shapes in plan views. The thermal radiation film300may have a thickness of, for example, about 10 μm to about 50 μm. The present inventive concepts, however, are not limited thereto. The thickness of the thermal radiation film300may be variously changed depending on configuration and size of the thermal radiation film.

As shown inFIG.1, the thermal radiation film300may have rounded corners. For example, the thermal radiation film300may not have a prismatic shape, but may have a rounded shape at its corners where the short sides300smeet the long sides3001. For example, the corners of the thermal radiation film300may each have a curvature radius of about 0.1 mm to about 0.3 mm Alternatively, the corners of the thermal radiation film300may not have rounded shapes, but may have vertex shapes where the short sides300smeet the long sides3001.

The thermal radiation film300may be formed of a metallic material, such as copper (Cu), aluminum (Al), or stainless steels, or formed of a non-metallic material with high thermal conductivity. When the thermal radiation film300is formed of a metallic material, the thermal radiation film300may have an electromagnetic shielding effect that blocks electromagnetic waves from outside or generated from the semiconductor chip200. The thermal radiation film300may be made of a single-layered film or a multi-layered film The following will describe in detail the multi-layered thermal radiation film300with reference toFIGS.13and14.

The thermal radiation film300may have a central part CP that covers the semiconductor chip200and a peripheral part PP that surrounds the central part CP.

The central part CP of the thermal radiation film300may correspond to a portion that provides an internal space IS to accommodate the semiconductor chip200on the circuit substrate100. For example, the central part CP of the thermal radiation film300may overlap an entirety of the semiconductor chip200, e.g., in a vertical direction, and may cover the top surface200u, the short lateral surfaces200s, and the long lateral surfaces200lof the semiconductor chip200. The semiconductor chip200may be interposed between the circuit substrate100and the central part CP of the thermal radiation film300. The central part CP of the thermal radiation film300may be in contact with the top surface200u of the semiconductor chip200. Therefore, the central part CP of the thermal radiation film300may directly receive heat from the semiconductor chip200to outwardly discharge the heat through a top surface of the thermal radiation film300.

It will be understood that when an element is referred to as being “connected” or “coupled” to or “on” another element, it can be directly connected or coupled to or on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as “contacting” or “in contact with” another element, there are no intervening elements present at the point of contact.

The central part CP of the thermal radiation film300may be disposed on and spaced apart from the lateral surfaces200sand200lof the semiconductor chip200. The central part CP of the thermal radiation film300may not be significantly spaced apart from the lateral surfaces200sand200lof the semiconductor chip200. For example, on the lateral surfaces200sand200lof the semiconductor chip200, an angle ranging from about 0° to about 45° may be provided between the central part CP of the thermal radiation film300and each of the lateral surfaces200sand200lof the semiconductor chip200. For example, as shown inFIG.4, the central part CP of the thermal radiation film300may be in contact with the lateral surfaces200sand200lof the semiconductor chip200. For example, on the lateral surfaces200sand200lof the semiconductor chip200, an angle of about 0° may be provided between the central part CP of the thermal radiation film300and each of the lateral surfaces200sand200lof the semiconductor chip200. When the central part CP of the semiconductor chip200is in contact with the lateral surfaces200sand200lof the semiconductor chip200, the thermal radiation film300may receive heat through the lateral surfaces200sand200lof the semiconductor chip200, and may increase in thermal radiation efficiency. The following description will focus on the embodiment ofFIG.3.

The peripheral part PP of the thermal radiation film300may correspond to a portion that attaches the thermal radiation film300to the circuit substrate100. In a plan view, the peripheral part PP of the thermal radiation film300may completely surround the central part CP of the thermal radiation film300. The peripheral part PP of the thermal radiation film300may be attached to the top surface100aof the circuit substrate100around the semiconductor chip200. Therefore, the internal space IS may be hermetically sealed which is a space between the circuit substrate100and the thermal radiation film300or which is defined between the circuit substrate100and the central part CP of the thermal radiation film300. The peripheral part PP of the thermal radiation film300may closely attach the semiconductor chip200to the circuit substrate100, and the semiconductor chip200may be rigidly mounted on the circuit substrate100. The peripheral part PP of the thermal radiation film300may receive heat from the semiconductor chip200through the central part CP of the thermal radiation film300, and the heat may be outwardly discharged. For example, the thermal radiation film300may have a thermal radiation area that corresponds to a sum of an area of the central part CP and an area of the peripheral part PP, and the peripheral part PP may increase the thermal radiation area of the thermal radiation film300, with the result that a semiconductor package may increases in thermal radiation efficiency.

The thermal radiation film300may have slits310. The slits310may be positioned on the peripheral part PP of the thermal radiation film300. For example, on the peripheral part PP, the slits310may be disposed adjacent to the short lateral surfaces200sof the semiconductor chip200. The slits310may be positioned between the semiconductor chip200and the short sides300sof the thermal radiation film300. The slits310may be connected to the short sides300sof the thermal radiation film300. The slits310may extend from the short sides300sof the thermal radiation film300toward the short lateral surfaces200sof the semiconductor chip200. For example, each of the slits310may extend from one of the short sides300sof the thermal radiation film300toward a facing one of the short lateral surfaces200sof the semiconductor chip200. For example, the slits310may be open to outside of the thermal radiation film300through respective short sides300s. As shown inFIG.1, the slits310may each have a linear or rectangular shape that extends in the first direction D1or its opposite direction from the short side300sof the thermal radiation film300. Therefore, the thermal radiation film300including the slits310may have an H shape, e.g., in a plan view. The slits310may each have a slit width sw measured in the second direction D2, and the slit width sw may be about0.8times to about2times the width of the short lateral surfaces200sof the semiconductor chip200(or the second length L2in the second direction D2of the semiconductor chip200). For example, the slit width sw of the slit310may be substantially the same as the second length L2of the short lateral surfaces200sof the semiconductor chip200. The slit width sw of the slit310may range, for example, from about 0.5 mm to about 10 mm In certain embodiments, the slit width sw of the slit310may be about 3 mm.

The slits310may each have an end310eopposite to the short side300sof the thermal radiation film300, and the end310emay be spaced apart at a first interval gl from a corresponding one of the short lateral surfaces200sof the semiconductor chip200. The first interval g1may be given to a distance between the slit310and its corresponding one of the short lateral surfaces200sof the semiconductor chip200. The first interval g1may be about 1% to about 20% of the width of the long lateral surfaces200lof the semiconductor chip200. For example, the first interval g1may range from about 1 mm to about 2.5 mm In certain embodiments, the first interval g1may be about 1.5 mm

As shown inFIG.1, the end310eof the slit310may have rounded corners. For example, the slit310may not have a prismatic shape, but may have a rounded shape at the corners of the end310e. For example, the corners of the end310eof the slit310may each have a curvature radius of about 0.05 mm to about 0.1 mm Alternatively, the end310eof the slit310may not have rounded shapes, and but may have vertex shapes at the corners thereof.

According to some embodiments of the present inventive concepts, as the slits310are formed at the thermal radiation film300, there may be a reduction in stress applied to the thermal radiation film300. With reference toFIGS.5to7, the following will describe in detail a reduction in deformation and stress of the thermal radiation film300.FIG.5illustrates a plan view showing deformation of a semiconductor package according to some embodiments of the present inventive concepts.FIGS.6and7illustrate cross-sectional views showing deformation of a semiconductor package according to some embodiments of the present inventive concepts.

A semiconductor package may be a deformable electronic device such as a flexible device, a foldable device, or a wearable device. For example, when an external force is applied to the semiconductor package, the semiconductor package may change in shape. As designated by arrows shown inFIG.5, the semiconductor package may be twisted by an external force. For example, when viewed along the first direction D1, the semiconductor package may rotate in different directions at its opposite ends in the first direction D1. Alternatively, the semiconductor package may be bent or rolled by an external force. For example, as designated by arrows shown inFIG.6, when viewed along the first direction D1, one end of the semiconductor package may ascend to a higher level or descend to a lower level than another end of the semiconductor package. For another example, as designated by arrows shown inFIG.7, when viewed along the second direction D2, one end of the semiconductor package may ascend to a higher level or descend to a lower level than another end of the semiconductor package. The semiconductor package may move or be deformed freely without being limited thereto. For example, the above-described bending, rolling, and twisting may be concurrently generated due to an external force applied to the semiconductor package. For example, one end of the semiconductor package may twist or ascend while approaching another end of the semiconductor package. For example, a center portion of the circuit substrate100may ascend or descend while edge/end portions of the circuit substrate100remain at the same vertical level.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “vertical,” “horizontal” and the like, may be used herein for ease of description to describe positional relationships. It will be understood that the spatially relative terms encompass different orientations of the device in addition to the orientation depicted in the figures.

As shown inFIGS.6and7, the thermal radiation film300may be located at different levels on the central part CP and the peripheral part PP. In addition, the central part CP of the thermal radiation film300may be attached to the semiconductor chip200, and the peripheral part PP of the thermal radiation film300may be attached to the circuit substrate100. Therefore, when a semiconductor package is deformed, the central part CP of the thermal radiation film300may have different behavior from that of the peripheral part PP of the thermal radiation film300, and a stress applied to the thermal radiation film300may be the largest between the central part CP and the peripheral part PP. For example, when a length in the first direction D1of the semiconductor chip200is greater than a length in the second direction D2of the semiconductor chip200, the largest boundary between the central part CP and the peripheral part PP may be provided on an end in the first direction D1of the semiconductor chip200. For example, the largest stress may be applied to the thermal radiation film300in the vicinity of the short lateral surfaces200sof the semiconductor chip200.

According to some embodiments of the present inventive concepts, because the slits310are formed at the thermal radiation film300, the slits310may relieve a stress due to the deformation of the thermal radiation film300. For example, because the slits310are formed adjacent to the short lateral surfaces200sof the semiconductor chip200, it may be possible to effectively relieve the stress applied to the thermal radiation film300in the vicinity of the short lateral surfaces200sof the semiconductor chip200. As a result, a semiconductor package may be provided to have increased structural stability.

In addition, the slits310may be formed to have linear shapes that extend from the short sides300sof the thermal radiation film300toward the short lateral surfaces200sof the semiconductor chip200, and the slits310may occupy small areas in the thermal radiation film300. For example, because the slits310are formed to correspond to the short lateral surfaces200sof the semiconductor chip200, the slit widths sw of the slits310may be small, and thus the slits310may occupy small areas. In this case, it may be possible to increase a thermal radiation area of the thermal radiation film300and a contact area between the thermal radiation film300and the circuit substrate100. Therefore, the thermal radiation film300may relieve a stress that occurs when a semiconductor package is deformed, and also may increase thermal radiation efficiency and adhesion to the circuit substrate100. A semiconductor package may thus be provided to have increased structural stability and improved thermal radiation efficiency.

In addition, the thermal radiation film300may entirely surround the top surface200u, the short lateral surfaces200s, and the long lateral surfaces200lof the semiconductor chip200. For example, the thermal radiation film300may contact all of the top surface200u, the short lateral surfaces200s, and the long lateral surfaces200lof the semiconductor chip200. For example, the semiconductor chip200may not be exposed outside the thermal radiation film300, and may be prevented from being in contact with air caused by partial opening of the thermal radiation film300. In this case, the semiconductor chip200may be completely covered with the thermal radiation film300. The term “completely covered” in this context may indicate that no part of an object or objects are exposed to the outside. Therefore, there may be an improvement in heat transfer from the semiconductor chip200to the thermal radiation film300. In addition, there may be a uniformity of heat transfer to the thermal radiation film300throughout the semiconductor chip200, and thus the semiconductor chip200may have no temperature gradient therein, with the result that the semiconductor chip200may be less damaged due to heat. Moreover, the thermal radiation film300that surrounds the entirety of the semiconductor chip200may have an electromagnetic shielding effect.

In relation toFIGS.5to7, it is explained that a semiconductor package is a deformable electronic device and that the semiconductor package is deformed by an external force, but the present inventive concepts are not limited thereto. Even when the circuit substrate100is formed of a rigid substrate such as a printed circuit board (PCB), the semiconductor package may be partially deformed due to an external force or heat-induced warpage. According to some embodiments of the present inventive concepts, because the thermal radiation film300includes the slits310formed adjacent to the short lateral surfaces200sof the semiconductor chip200, it may be possible to provide a semiconductor package with improved structural stability and increased thermal radiation efficiency.

FIG.8illustrates a plan view showing a semiconductor package according to some embodiments of the present inventive concepts. In the embodiments that follow, a detailed description of technical features repetitive to those discussed above with reference toFIGS.1to7will be omitted or briefly described and differences will be discussed in detail. The same reference numerals will be allocated to the components the same as or similar to those of the semiconductor package discussed above.

Referring toFIG.8, on the peripheral part PP, the slits310may be disposed adjacent to the short lateral surfaces200sof the semiconductor chip200. For example, the slits310may be positioned between the semiconductor chip200and the short sides300sof the thermal radiation film300. The slits310may be connected to the short sides300sof the thermal radiation film300. For example, the slits310may be open to an outside of the thermal radiation film300through the respective short sides300s. The slits310may extend from the short sides300sof the thermal radiation film300toward the short lateral surfaces200sof the semiconductor chip200. For example, each of the slits310may extend from one of the short sides300sof the thermal radiation film300toward a facing one of the short lateral surfaces200sof the semiconductor chip200. As shown inFIG.8, the slits310may have their slit widths sw, e.g., in the second direction, each of which increases in a direction approaching the semiconductor chip200from the short side300sof the thermal radiation film300. For example, the slits310may each have a triangular shape or a dew shape which has a vertex directed toward the short side300sof the thermal radiation film300. In certain embodiments, each of the slits310may have a trapezoid shape. The slits310may have their largest widths, e.g., in the second direction D2, in regions adjacent to the short lateral surfaces200sof the semiconductor chip200, and may also have their smallest widths, e.g., in the second direction D2, in regions adjacent to the short sides300sof the thermal radiation film300. For example, in the region adjacent to the short lateral surfaces200sof the semiconductor chip200, the slit width sw of the slit310may be about 0.8 times to about 2 times the width of the short lateral surfaces200sof the semiconductor chip200(or the second length L2in the second direction D2of the semiconductor chip200). For example, in the region adjacent to the short lateral surfaces200sof the semiconductor chip200, the slit width sw of the slit310may be substantially the same as the second length L2of the short lateral surfaces200sof the semiconductor chip200.

According to some embodiments of the present inventive concepts, because the slits310are formed adjacent to the short lateral surfaces200sof the semiconductor chip200, it may be possible to effectively relieve a stress applied to the thermal radiation film300in the vicinity of the short lateral surfaces200sof the semiconductor chip200. In addition, because the slit width sw of the slit310decreases in a direction receding from the short lateral surfaces200sof the semiconductor chip200, the thermal radiation film300of a semiconductor package may have an increased overall area, and thus may have high efficiency of thermal radiation and excellent adhesion to the circuit substrate100.

FIG.9illustrates a plan view showing a semiconductor package according to some embodiments of the present inventive concepts.FIG.10illustrates a cross-sectional view taken along line E-E′ ofFIG.9, showing a semiconductor package according to some embodiments of the present inventive concepts.

FIGS.1to8depict that a single slit310is provided on one of the short lateral surfaces200sof the semiconductor chip200, but the present inventive concepts are not limited thereto.

Referring toFIGS.9and10, at least two sub-slits312may be provided on each of the short lateral surfaces200sof the semiconductor chip200. The following will describe configurations of the sub-slits312connected to one short side300sof the thermal radiation film300. The sub-slits312may extend from the short side300sof the thermal radiation film300toward a facing short lateral surface200sof the semiconductor chip200. The sub-slits312may have their ends312e that are provided adjacent to corners of the semiconductor chip200. In this case, the corners may indicate sides where the short lateral surfaces200smeet the long lateral surfaces200lof the semiconductor chip200. The sub-slits312may extend in the first direction D1and may be spaced apart from each other in the second direction D2. For example, the sub-slits312may have their linear shapes that extend from one short side300sof the thermal radiation film300toward the corners of the semiconductor chip200. Compared to the embodiment shown inFIG.1, the embodiment ofFIG.9corresponds to a shape that each of the slits (see310ofFIG.1) may have in its inside an extension314that extends in the first direction D1from the thermal radiation film300. Referring back toFIGS.9and10, the extension314may define shapes of the sub-slits312, and the sub-slits312may be spaced apart from each other across the extension314. The sub-slits312may each have a sub-slit width ssw less than the width of the short lateral surfaces200sof the semiconductor chip200(or the second length L2in the second direction D2of the semiconductor chip200). The sub-slit width ssw of the sub-slit312may be about 0.3 times to about 0.5 times the second length L2of the short lateral surfaces200sof the semiconductor chip200. The extension314may have an extension width ew less than about 0.5 times the second length L2of the short lateral surfaces200sof the semiconductor chip200.

When the semiconductor chip200has a tetragonal shape in a plan view, a larger or largest stress may be applied to the thermal radiation film300in the vicinity of the semiconductor chip200. According to some embodiments of the present inventive concepts, because the sub-slits312are formed adjacent to the corners of the semiconductor chip200, it may be possible to effectively relieve the stress applied to the thermal radiation film300in the vicinity of the corners of the semiconductor chip200. In addition, the extension314between the sub-slits312may be attached to the circuit substrate100at regions adjacent to the lateral surfaces200sof the semiconductor chip200. Therefore, ends in the first direction D1of the semiconductor chip200may be rigidly attached through the extension314to the circuit substrate100.

FIG.11illustrates a plan view showing a semiconductor package according to some embodiments of the present inventive concepts.FIG.12illustrates a cross-sectional view taken along line F-F′ ofFIG.11, showing a semiconductor package according to some embodiments of the present inventive concepts.

As shown inFIGS.11and12, the sub-slits312may be in contact with the corners of the semiconductor chip200. In this case, the extension width ew of the extension314may be substantially the same as the width of the short lateral surfaces200sof the semiconductor chip200(or the second length L2in the second direction D2of the semiconductor chip200), and the sub-slits312may be spaced apart in the second direction D2from each other across the extension314. The sub-slit width ssw of the sub-slit312may be less than the second length L2of the short lateral surfaces200sof the semiconductor chip200. The extension314may be in contact with the short lateral surfaces200sof the semiconductor chip200. Therefore, no empty space may be formed between the extension314and the semiconductor chip200, and there may be an increase in efficiency of thermal radiation through the extension314from the short lateral surfaces200sof the semiconductor chip200. In addition, the extension314whose area is relatively large may cause that ends in the first direction D1of the semiconductor chip200is rigidly attached to the circuit substrate100.

FIG.13illustrates a cross-sectional view showing a semiconductor package according to some embodiments of the present inventive concepts.FIG.14illustrates an enlarged view showing section A ofFIG.13.

Referring toFIGS.13and14, a semiconductor package may be a chip-on-film (COF) type semiconductor device.

A base film101may be provided. The base film101may have a circuit substrate100and lead frames400formed on the circuit substrate100.

The circuit substrate100may be a flexible film type substrate. The circuit substrate100may include a dielectric material. For example, the circuit substrate100may include polyimide (PI).

The lead frames400may be provided on the circuit substrate100. A configuration of the lead frame400will be discussed together with an arrangement of the semiconductor chip200.

Although not shown, the circuit substrate100may have a thermal radiation member disposed on a bottom surface thereof The thermal radiation member may cover an entirety of the bottom surface of the circuit substrate100. Alternatively, the thermal radiation member may be disposed only below a region where the semiconductor chip200is mounted on the base film101. The thermal radiation member may be in contact with the bottom surface of the circuit substrate100. The thermal radiation member may be provided to externally discharge heat that is generated from the semiconductor chip200and then is transferred downwardly through the lead frames400. The thermal radiation member may include a metallic conductor or an insulator which has a high thermal conductivity. For example, the thermal radiation member may include or be formed of aluminum (Al).

The semiconductor chip200may be mounted on the base film101. The semiconductor chip200may be a flip-chip mounted on the base film101. For example, a front surface of the semiconductor chip200may be directed toward the base film101. In this description below, the term “front surface” may be defined to refer to an active surface on which a circuit layer of the semiconductor chip200is formed, and the term “rear surface” may be defined to refer to an inactive surface or a surface opposite to the front surface. For example, the semiconductor chip200may include chip pads210provided on the front surface thereof. The chip pads210may face the base film101.

The lead frames400may be provided between the circuit substrate100and the semiconductor chip200. The semiconductor chip200may be coupled to the lead frames400provided on a top surface of the circuit substrate100. For example, the chip pads210of the semiconductor chip200may be in contact with the lead frames400. The circuit substrate100may be provided thereon with the lead frames400electrically connected to the chip pads210of the semiconductor chip200. On the circuit substrate100, the lead frames400may serve to transfer electrical signals from the semiconductor chip200to an external output apparatus. The lead frames400may be disposed spaced apart from each other. The lead frames400may have their outer distal ends that extend toward an outer side of the semiconductor chip200. The lead frames400may include or be formed of metal, such as copper (Cu).

As used herein, components described as being “electrically connected” are configured such that an electrical signal can be transferred from one component to the other (although such electrical signal may be attenuated in strength as it transferred and may be selectively transferred).

An under-fill part500may be provided between the base film101and the semiconductor chip200. The under-fill part500may fill a space between the base film101and the semiconductor chip200. The under-fill part500may encapsulate the chip pads210and may partially cover the lead frames400. The under-fill part500may include, for example, an anisotropic conductive film (ACF) or a non-conductive paste (NCP).

A surface dielectric layer600may further be provided in the base film101. The surface dielectric layer600may partially cover the lead frames400that outwardly extend from the semiconductor chip200. For example, a solder resist layer may be used as the surface dielectric layer600. The surface dielectric layer600may be provided to cover the lead frames400.

The thermal radiation film300may be provided on the surface dielectric layer600. The thermal radiation film300may cover the semiconductor chip200. The thermal radiation film300may closely attach the semiconductor chip200to the base film101, and may outwardly discharge heat generated from the semiconductor chip200. The thermal radiation film300may have a planar shape the same as or similar to that discussed with reference toFIGS.1to12. For example, the thermal radiation film300may have a planar shape larger than that of the semiconductor chip200. For example, a plan view of the thermal radiation film300of the embodiment illustrated inFIGS.13and14may be the same as or similar to any plan view of the thermal radiation films300of the embodiments illustrated inFIGS.1to12. The thermal radiation film300may have a length in the first direction D1greater than a length in the second direction D2. For example, the thermal radiation film300may have a rectangular shape in a plan view. The thermal radiation film300may have slits310. The slits310may extend from the short sides300sof the thermal radiation film300toward the short lateral surfaces200sof the semiconductor chip200.

The thermal radiation film300may be formed of a plurality of layers. For example, the thermal radiation film300may include an adhesion layer320, a thermal conduction layer330, and a protection layer340that are sequentially stacked.

The adhesion layer320may be in contact with a top surface of the surface dielectric layer600and a top surface of the semiconductor chip200. Alternatively, when the surface dielectric layer600is not provided in the base film101, the adhesion layer320may be in contact with a top surface of the lead frames and/or a top surface of the circuit substrate100. The adhesion layer320may be provided to attach the thermal radiation film300to the base film101. For example, the adhesion layer320may be attached to the top surface of the surface dielectric layer600and the top surface of the semiconductor chip200. The adhesion layer320may be provided in the form of an adhesive film or thin layer. For example, the adhesion layer320may include or be formed of an adhesive polymer. For another example, the adhesion layer320may include or be formed of a material of which thermal conductivity is high or in which particles having high thermal conductivity are dispersed. The adhesion layer320may include or be formed of, for example, a pressure sensitive adhesive (PSA). The adhesion layer320may have a thickness of about 1 μm to about 10 μm.

The thermal conduction layer330may be attached through the adhesion layer320to the top surface of the surface dielectric layer600and the top surface of the semiconductor chip200. The thermal conduction layer330may be provided to receive heat from the semiconductor chip200and to discharge the heat outwardly from a semiconductor package. The thermal conduction layer330may be formed of a metallic material, such as copper (Cu), aluminum (Al), or stainless steels, or formed of a non-metallic material with high thermal conductivity. The thermal conduction layer330may have a thickness of about 10 μm to about 50 μm.

The protection layer340may cover the thermal conduction layer330. The protection layer340may be provided to protect the thermal conduction layer330and the semiconductor chip200inside the thermal radiation film300. For example, the protection layer340may include or be formed of polyimide (PI). The protection layer340may have a thickness of about 10 μm to about 30 μm. Alternatively, the protection layer340may be formed of a metallic material, such as copper (Cu), aluminum (Al), or stainless steels. When the protection layer340and the thermal conduction layer330are formed of the same material, the protection layer340and the thermal conduction layer330may be provided as one metal layer.

No limitation is imposed on the material and thickness of each of the adhesion layer320, the thermal conduction layer330, and the protection layer340. In certain embodiments, the adhesion layer320, the thermal conduction layer330, and the protection layer340may each be formed of various materials and may be provided to have various thicknesses.

The adhesion layer320, the thermal conduction layer330, and the protection layer340may have the same planar shape. The adhesion layer320, the thermal conduction layer330, and the protection layer340may completely vertically overlap each other. For example, as shown inFIG.14, the adhesion layer320, the thermal conduction layer330, and the protection layer340may have respective sidewalls320a,330a, and340athat are vertically aligned with each other. For example, the adhesion layer320, the thermal conduction layer330, and the protection layer340may have the same shape in a plan view.

FIG.15illustrates a cross-sectional view showing a method of fabricating a semiconductor package according to some embodiments of the present inventive concepts.FIG.16illustrates a plan view showing a method of fabricating a semiconductor package according to some embodiments of the present inventive concepts.

Referring toFIGS.15and16, a base film101may be provided. The base film101may be the same as or similar to that discussed with reference toFIGS.13and14. For example, the base film101may have the circuit substrate100and the lead frames400formed on the circuit substrate100. The semiconductor chip200may be mounted on the base film101.

The thermal radiation film300may be provided on the base film101. Although not shown, the thermal radiation film300may be formed by forming a stack film by sequentially stacking the adhesion layer320, the thermal conduction layer330, and the protection layer340, and then patterning the stack film A cutting process may be performed one time to process the stack film Therefore, the adhesion layer320, the thermal conduction layer330, and the protection layer340may be formed to have the same planar shape and to be vertically aligned with each other. When the cutting process is performed, the thermal radiation film300may be formed to have the slits310. The thermal radiation film300may have the central part CP that covers the semiconductor chip200which will be discussed below and the peripheral part PP that surrounds the central part CP, and the slits310may be formed on the peripheral part PP. According to some embodiments of the present inventive concepts, the cutting process may be performed one time to form the thermal radiation film300. For example, the thermal radiation film300may be formed by a simplified process, and a simplified method of fabricating a semiconductor package may be provided.

Afterwards, the thermal radiation film300may approach the base film101and then may be attached to the base film101. For example, the thermal radiation film300may be aligned with the semiconductor chip200so as to allow the slits310of the thermal radiation film300to face the short lateral surfaces200sof the semiconductor chip200, and the slits310may have their slit widths sw each of which may be greater than the second length L2of the short lateral surfaces200sof the semiconductor chip200. In this case, because the semiconductor chip200protrudes beyond a top surface of the base film101, the thermal radiation film300may be attached to the top surface of the semiconductor chip200rather than to the top surface200u of the base film101, e.g., in the area where the semiconductor chip200is disposed.

Thereafter, while the thermal radiation film300continuously approaches the base film101, as designated by arrows shown inFIGS.15and16, a thermal radiation film300′ may be partially deformed. In this description, an apostrophe is added to a thermal radiation film and its components after attachment. The thermal radiation film300′ may overlap the entirety of the semiconductor chip200. For example, the central part CP of the thermal radiation film300′ may cover all of the top surface200u and the lateral surfaces200sand200lof the semiconductor chip200. In a plan view, the deformation mentioned above may reduce a planar area of the thermal radiation film300′ and may also reduce the slit widths sw′ of the slits310′ of the thermal radiation film300′. For example, after the deformation of the thermal radiation film300′, the slit widths sw′ of the slits310′ of the thermal radiation film300′ may be about 0.8 times to about 2 times the second length L2of the short lateral surfaces200sof the semiconductor chip200.

While the thermal radiation film300′ continuously approaches the base film101, the peripheral part PP of the thermal radiation film300′ may be attached to the base film101. While the peripheral part PP of the thermal radiation film300′ is attached to the base film101, the semiconductor chip200may be positioned in the internal space IS that is hermetically sealed by the base film101and the central part CP of the thermal radiation film300′.

As for a semiconductor package according to some embodiments of the present inventive concepts, slits may be formed adjacent to short lateral surfaces of a semiconductor chip, and thus it may be possible to effectively relieve a stress applied to a thermal radiation film in the vicinity of the short lateral surfaces of the semiconductor chip. As a result, the semiconductor package may be provided to have increased structural stability.

In addition, the slits may have their small widths and may occupy small areas. Thus, it may be possible to increase a thermal radiation area of the thermal radiation film and a contact area between the thermal radiation film and a circuit substrate. Therefore, the thermal radiation film may relieve a stress that occurs when the semiconductor package is deformed, and also may increase thermal radiation efficiency and adhesion to the circuit substrate. Accordingly, the semiconductor package may be provided to have increased structural stability and improved thermal radiation efficiency.

In addition, the semiconductor chip may be completely covered with the thermal radiation film Thus, there may be an improvement in heat transfer from the semiconductor chip to the thermal radiation film Furthermore, there may be a uniformity of heat transfer to the thermal radiation film in accordance with the position of the semiconductor chip, and thus the semiconductor chip may have no temperature gradient therein, with the result that the semiconductor chip may be less damaged due to heat. Moreover, the thermal radiation film that surrounds the entirety of the semiconductor chip may have an electromagnetic shielding effect.

In a method of fabricating a semiconductor package according to some embodiments of the present inventive concepts, a cutting process may be performed one time to form the thermal radiation film For example, only one cutting process may complete the formation of the thermal radiation film Accordingly, the thermal radiation film may be formed by a simplified process, and a simplified method of fabricating a semiconductor package may be provided.

Although the present inventive concepts have been described in connection with some embodiments of the present inventive concepts illustrated in the accompanying drawings, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and essential feature of the present inventive concepts. The above disclosed embodiments should thus be considered illustrative and not restrictive.