Patent ID: 12206532

DETAILED DESCRIPTION

Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. The present disclosure may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present disclosure to those skilled in the art. Like reference numerals in the drawings denote like elements.

As used in any embodiment described herein, “circuitry” may include, for example, singly or in any combination, hardwired circuitry, programmable circuitry, state machine circuitry, and/or firmware that stores instructions executed by programmable circuitry. It should be understood at the outset that any of the operations and/or operative components described in any embodiment herein may be implemented in software, firmware, hardwired circuitry and/or any combination thereof.

The adoption of pulse amplitude modulation 4-level (PAM4) over non-return-to-zero (NRZ) in high speed serializer/deserializer (SerDes) wireline receivers introduces new challenges in receiver design. Specifically, the design of samplers able to discern a quaternary symbol tend to be complex and power hungry. Recently, the trend has been for high speed SerDes wireline receivers to switch to PAM4 to achieve higher data rates. The present disclosure aims to reduce the number of samplers required to do PAM4 symbol detection, which in turn helps to reduce the amount of surface area occupied by the circuit while also reducing the amount of power consumed by the circuit. More specifically, this design only requires two samplers, one of which may include a strongarm latch and the other may include a design that has two threshold voltages.

FIG.1shows where PAM4 signal generation has three distinct threshold levels to differentiate between four distinct symbols: 00, 01, 11, and 10. As shown in graphical representation 100 two bits of information are contained in each symbol. Ordinarily, a conventional sampler may sample the most significant bit (MSB) without too much difficulty, but detecting the least significant bit (LSB) is not as straight forward and requires more processing. For conventional PAM4 detectors, the detection of the LSB cannot be completed until the MSB is resolved. This is because LSB detection involves two threshold levels as indicated by Vthpand VthninFIG.1. The MSB decides which threshold level is to be used to resolve the LSB. This inherently creates a constraint in how fast the overall PAM4 symbol may be resolved. Existing approaches attempt to work around this delay by having two independent data paths one having a threshold of Vthpand one having a threshold of Vthnand subsequently selecting the correct path depending on the resolved value of the MSB. This alleviates the delay to a certain degree but does so at the cost of an additional data path, which increases area and power consumption as well as increasing the complexity of the clock tree necessary to drive the samplers. The present disclosure circumvents this by making the LSB detector capable of independent LSB detection. Hence, substantial power, area and clocking complexity can be reduced.

Referring now toFIG.2, sampler circuit200is provided. In some embodiments, sampler circuit200may use data sense amplifier circuit202(a data arm) and reference sense amplifier circuit204(a reference arm) to compete with one another to discharge capacitive node206,208. The rates of discharge of both data arm202and reference arm204may be used to determine if there is a high enough differential input magnitude to set the output to logic 0, and if the differential input is not high enough then the output may be set to logic 1. Both data arm202and reference arm204may be directly connected to latch circuit210, which may be configured to receive a first input at node212from data arm202and a second input at node214from reference arm204. Latch circuit210may be further configured to use the first input at node212and the second input at node214to generate an LSB at output node216or output node218. Additionally, both data arm202and reference arm204include pairs of differential transistors220,222, such that data arm202includes differential pair220and reference arm204includes differential pair222.

In some embodiments, the latch circuit210is a set/reset latch (SR latch circuit)210, which may compare an absolute value of a differential input212,214to a threshold value to generate the least significant bit at output nodes216,218. Such embodiments effectively replace the two independent comparators used in conventional LSB detector circuits with one structure that has two symmetrical thresholds about 0V differential. Additionally, a fast SR latch circuit210may be used to convert the LSB at output nodes216,218to CMOS Logic, which aids in overcoming the difficulty involved in establishing proper phase relationships between many interleaved ADC paths at very high data rates.

During the transition from the reset state of the sampler to the data settling, the transistors in the differential pair220,222of both arms go through three distinct regions of operation: (i) the cutoff/reset region, (ii) the linear region, and (iii) the triode region (output stable). The decision to classify the LSB as a 0 is made when the data arm can discharge output node216out faster than the reference arm can discharge output node218. Since in the reset state either pair of differential transistors220,222has a gate source voltage (Vgs) of zero and in the third state, the absolute maximum voltage between the drain and the source (Vds) is minimized due to discharging of the first stage output nodes. Accordingly, the highest currents and thus the biggest impact on the fall-time of output nodes216,218is made when the differential pairs220,222are in the linear region of operation where the output nodes216,218are transitioning.

Further, during the transition in the linear region, the effective impedance looking into the drain would be Rds=Vds/(K*W/L*(Vgs−Vth)2) or Rdsα 1/(Vgs−Vth){circumflex over ( )}2. This means that if either IN_Por IN_Mfrom data arm202is driven higher than the gates of the references branch transistors (which are at Vref) there will be a threshold voltage Vthresh(Vref) where Zout,GND>Zout_ref,GND. At this point, the output at node216will be discharged faster than the output at node218. The SR latch circuit210will be released from reset as soon as either node moved from Vddwill regenerate the difference and latch the output nodes216,218to GND and Vddrespectively. Hence Vthp=Vthresh(Vref) and Vthn=−Vthresh(Vref). The relationship between Vthreshand Vrefdue to reference arm204having half the impedance of the data arm202uses competing data sense amplifier202and reference sense amplifier204to do LSB detection.

For sense amplifiers an important criteria that determines the clock-to-Q (C2Q) delay is the strength of the tail switch, where C2Q is a measure of how fast the output of the circuit resolves when a clock edge triggers sampling. The faster the switch activates and the lower its impedance to GND the better the speed may be of the sense amplifier structure204. For the circuit structure200, inFIG.2, when the data arm202has one of its inputs at a significantly higher voltage than the other it will be harder for the tail of data arm202switch to turn on due to the lower impedance seen to the node212. Thus, re-using the switches of reference arm204for discharging the tail of data-arm202ensures a faster discharge of the tail data-arm202tail and thus a faster overall response of the circuit.

The circuit structure300inFIG.3ensures the tail nodes settle during reset at one transistor threshold voltage below the average voltage (common-mode voltage) supplied to the gates of each branch. When the tail nodes are connected together as inFIG.2, the data arm and reference arms are not allowed to settle at independent tail node voltages but are rather forced to settle at a common voltage. Hence, when the data arm's gates are both connected to high voltages (implies a high common-mode voltage), there may be a point where the data arm has lower impedance to GND than the reference arm. This may result in a false detection of LSB. Hence, the stage that precedes this sampler in the datapath must have good common-mode rejection.

This means that the structure inFIG.2is more likely to trigger in the presence of a high input common-mode voltage than the structure inFIG.3. Hence, circuit structure200inFIG.2has a lower common-mode rejection than the circuit structure300inFIG.3.

FIG.3shows a sampler circuit300also using a data sense amplifier circuit302(a data arm) and a reference sense amplifier circuit304(a reference arm) to compete with one another to discharge a capacitive node306,308. For low differential swings, output node310of reference arm304falls to GND faster than data arm302, and output node312of data arm302falls to GND faster than reference arm304when the differential swing of IN_Por IN_Mfrom data arm302is high enough. Sampler circuit300offers almost equally fast C2Q compared to strongarm and sense amplifier based latches. In some embodiments, the stages used do not have static power consumption, i.e., they may not employ current mode logic (CML). Additionally, under circuit topology300one sampler may perform the function of two, hence it may occupy a smaller surface area and require lower power consumption, lower clock tree and support logic complexity. More specifically, the present disclosure uses a single reference voltage to set the two symmetrical threshold voltages about 0V differential. These thresholds are highly symmetric, and their on-chip variation may be highly correlated to one other. Further, as the data-path may be easily available to probing, this topology offers a more reliable detection scheme.

Now referring toFIG.4, a sampler circuit400consistent with embodiments of the present disclosure is provided. In some embodiments, sampler circuit400may include an odd path402and an even path404, where odd path402may be triggered on a rising edge of the clk0 input signal and where even path404may be active on the falling edge. This dual path architecture may be used to lower the clock frequency required, which, in turn, conserves the power needed to drive very high frequency clocks. Each data path402,404may include one conventional sampler to resolve MSB and one instance of the sampler design for LSB detection. InFIG.4, data path404shows the conventional sampler406directly below the LSB sampler408, while neither the MSB sampler nor the LSB sampler are illustrated for data path402.

In some embodiments, the output of data paths402,404may be selected based on the valid clock edge in the SerDes/DFE410logic and then fed back into the summer stage for decision feedback equalization (DFE), where the summer stage may include one or more “taps” that add or subtract weighted versions of previously detected symbols to equalize the inter symbol interference (ISI) created by the channel. Each data path may be related to an edge sampler, such that odd data path402relates to an odd edge sampler412, and even data path404relates to an even edge sampler414. Odd edge sampler412and even edge sampler414may both be driven by quadrature clocks, which represent 90 degree phase shifted versions of the clk0 input signal. The edge samplers412,414may be used by the clock data recovery (CDR) block416to control outputs of the phase interpolator (PI)418by means of phase rotation, in order to track the optimum sampling instant in the data unit interval (UI). One or more error samplers420may be driven by a special clock path and used to probe the equalized data and tune the tap coefficients of the DFE as well any continuous time linear equalizer (CTLE) that may/may not be present in the particular wireline receiver the DFE is used in. In some embodiments, an additional reference creation block422may be added to the DFE to aid in the generation of the reference voltage that controls the threshold of the LSB detector.

Referring now toFIG.5, a flowchart depicting operations consistent with the present disclosure is provided. The method may include providing502a data sense amplifier circuit and a reference sense amplifier circuit electrically connected with the data sense amplifier circuit. The method may include receiving504a first input from the data sense amplifier circuit and a second input from the reference sense amplifier circuit at a latch circuit. The method may further include generating506a least significant bit output based upon, at least in part, the first input and the second input. In some embodiments, the method may further include comparing a respective output voltage of the data sense amplifier circuit and the reference sense amplifier circuit. In still other embodiments the method may also include comparing an absolute value of a differential input to a threshold value to generate the least significant bit output.

Numerous other operations are also within the scope of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made in embodiments of the present disclosure without departing from the spirit or scope of the invention. Thus, it is intended that embodiments of the present disclosure cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.