Patent ID: 12232322

DETAILED DESCRIPTION

The present disclosure provides many different embodiments, or examples, for implementing different features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In one process of forming a 3D memory array, control gate layers and dielectric layers are alternately deposited to form a broad stack. Trenches are formed to divide the broad stack into a row of narrow stacks, each stack including multiple tiers of gate strips vertically separated by dielectric strips. Dielectric plugs are formed periodically along the trenches dividing the trenches into cell areas. A data storage film and a channel film are deposited on the sidewalls of the cell areas. The middles of the cell areas are filled with an intracell dielectric. Openings are etched in the intracell dielectric and filled with conductive material to provide vertical source lines and drain lines.

With each of the data storage film and channel film depositions, the remaining cell area becomes smaller. The data storage film and channel film are vertical films that deposit all about a perimeter (four sides) of the cell area. This leaves only a small space for the source lines and the drain lines. The source lines and the drain lines may be border on three sides by the channel layer. Making the source lines and the drain lines larger causes the source lines and the drain lines to be closer together. A distance along the channel layer from a source line to a drain line is the operative channel length of the memory cell and cannot be arbitrarily reduced without affecting the functioning of the memory cells. Accordingly, it is difficult to widen the source lines and the drain lines without significantly reducing the overall density of the memory array.

In accordance with some aspects of the present teachings, the source lines and the drain lines are each provided with a bulge toward the interior of the cell area. The bulges increase the source line and the drain line cross-sectional areas without reducing the channel lengths. In the resulting structure, a distance between the source lines and the drain lines is less than the channel length. In some embodiments, the bulges have elliptical edges.

Some aspects of the present teachings relate to methods of forming a 3D memory array. In these methods, openings for the source lines and drain lines are etched through elliptical mask openings. In some of these teachings, there is one mask opening for each source line and one other opening for each drain line. In some of these teachings, the mask openings are circular. In others of these teachings, single elliptical mask openings are used to etch pairs of source line and drain line openings. The elliptical mask openings may be centered over dielectric plugs having a different composition from the intracell dielectric. A selective etch process leaves the dielectric plugs separating source line/drain line pairs.

In some embodiments, the dielectric plugs have concave sidewalls. The channel layer may be deposited over the concave sidewalls and the resulting shape may facilitate good contact between the channel layer and the source lines and the drain lines. This advantage may be enhanced when the source and drain lines are formed by etching through circular or nearly circular openings. In some embodiments, the dielectric plugs are formed by filling the trenches with an intercell dielectric and etching the intercell dielectric through a mask having elliptical openings corresponding to the desired locations for cell areas. The etching through the elliptical openings may produces the concave sidewalls.

In some aspects of the present teachings, the areas available for the source lines and the drain lines are increased by preventing the data storage film from forming on the dielectric plugs. In some embodiments, this is accomplished by forming the data storage film selectively on the control gate strip sidewalls. In some embodiments, this is accomplished by depositing the data storage film in recesses in the narrow stacks, the recesses being formed adjacent the control gate strips. Any portion of the data storage film that deposits outside the recesses may be removed by etching. In some embodiments, the data storage film is formed before the dielectric plugs.

In some aspects of the present teachings, the areas available for the source lines and the drain lines are increased by eliminating all or part of the channel layer that would be disposed on the dielectric plugs. In some embodiments, this is accomplished by forming the channel layer selectively on the data storage film. In some embodiments, this is accomplished by depositing all or part of the channel layer in recesses in the narrow stacks. In some of these embodiments, a second portion of the channel layer be disposed outside the recesses to provide the channel with a sufficient thickness. In some embodiments, the channel layer is formed before the dielectric plugs.

FIG.1Aillustrates a perspective view of a first 3D memory array100A of memory cells101A according to some aspects of the present teachings.FIG.1Billustrates a cross-section of the first 3D memory array100A along a plane B ofFIG.1A.FIG.1Cillustrates a cross-section along a plane C ofFIG.1A. The line BC inFIGS.1B and1Cis at the intersection of the plane B and the plane C. The plane B is vertical. The plane C is horizontal.

A row of stacks135A is disposed within the first 3D memory array100A. Each of the stacks135A has gate strips123A in a plurality of tiers141A-141D separated by dielectric strips131A. This example shows four tiers141A-141D, but the stacks135A may have a greater or lesser number of tiers. Cell areas122A are areas between the stacks135A separated by intercell dielectric plugs121A. Data storage structures108A include data storage films111A and are formed around perimeters of the cell areas122A. Channel layers107A are formed about inner walls of the data storage structures108A. Vertically oriented source lines103A and drain lines119A are disposed within the cell areas122A and are separated within each of the cell areas122A by intracell dielectric115A. The source lines103A and drain lines119A have bulges106A.

The memory cells101A may be formed on a first side133A and a second side133B, which are opposite sides of a stack135A. The memory cells101A are arrayed horizontally and vertically on the first side133A and on the second side133B. Each of the memory cells101A includes a control gate109A, a data storage structure108A, a channel113A, a source side105A, and a drain side117A. The control gates109A are provided by the gate strips123A. A single gate strip123A may provide control gates109A for a plurality of memory cells101A including memory cells101A that are horizontally adjacent along a length of a gate strip123A and memory cells101A that are on opposite sides133A-133B of the stack135A that includes the gate strip123A. The channel113A, the source side105A, and the drain side117A are all provided by a channel layer107A. The source side105A is a portion of the channel layer107A adjacent a source line103A. The drain side117A is a portion of the channel layer107A adjacent a drain line119A. The channel113A is a portion of the channel layer107A between the source side105A and the drain side117A.

The channel layer107A extends horizontally to provide channels113A, source sides105A, and drain sides117A for multiple memory cells101A. The channel layer107A may also extend vertically through the tiers141A-141D. In some embodiments, the channel layer107A is continuous across a length and a height of a stack135A. Portions of the channel layer107A may provide the channels113A, the source sides105A, and the drain sides117A for all the horizontally and vertically distributed memory cells101A on either the first side133A or the second side133B of a stack135A.

With reference toFIG.1C, one source line103A and one drain line119A are disposed within each of the cell areas122A. Due to the bulges106A, a distance D1between the source line103A and the drain line119A is less than a channel length L1. The channel length L1may be a distance from a point at which the channel layer107A abuts the source line103A to a point at which the channel layer107A abuts the drain line119A. In some embodiments, the distance D1is 90% or less the length L1. In some embodiments, the distance D1is 80% or less the length L1. In some embodiments, the distance D1is 70% or less the length L1. In some embodiments, areas of the source line103A and the drain line119A are 5% or more greater than they would be absent the bulges106A. In some embodiments, areas of the source line103A and the drain line119A are 10% or more greater than they would be absent the bulges106A. In some embodiments, areas of the source line103A and the drain line119A are 20% or more greater than they would be absent the bulges106A.

FIG.2illustrates a top view of the first 3D memory array100A in an integrated circuit200.FIG.3illustrates a partial cross-sectional view of the integrated circuit200. As shown in these figures, the gate strips123A may extend beyond one end of the first 3D memory array100A to progressively varying lengths forming a staircase pattern206that allows each of the gate strips123A to be coupled to a distinct word line wire207in an overlying metal interconnect layer301D through vias209. Source line wires201and bit line wires203may also be formed in the metal interconnect layer301D. The source line wires201and the bit line wires203may extend crosswise with respect to the gate strips123A and the stacks135A. Each of the source line wires201may be coupled to a plurality of source lines103A through vias205. Each of the bit line wires203may be coupled to a plurality of drain lines119A.

FIG.4provides an equivalent circuit diagram400for the first 3D memory array100A. As illustrated by the equivalent circuit diagram400, each of the memory cells101A operates as a transistor. There are M memory cells arranged along each of the gate strips123A. There are K stacks135A each having N tiers141A-141D giving a total of K*N gate strips123A. Each of the memory cells101A may be individually addressed by selecting a corresponding word line wire207, bit line wire203, and source line wire201. The numbers of gate strips123A connected to each word line wire207, the number of source lines103A connected to each source line wire201, and the number of drain lines119A connected to each bit line wire203may be varied while preserving this feature.

Transistors have a threshold gate voltage at which a source to drain connection switches from open to closed. In a memory cell, that threshold may be varied through write and erase operations to provide two or more distinct threshold voltages. For example, the data storage structure108A may include a data storage film111A that retains a polarization of electrical dipoles. An orientation of these dipoles may be varied to modulate a threshold voltage on the control gate109A at which an electric field renders the channel113A conductive. A first orientation of those electrical dipoles provides a first threshold voltage that may represent a logical “1” and a second orientation provides a second threshold voltage that may represent a logical “0”.

In the first 3D memory array100A, a write operation for one of the memory cells101A may include setting a corresponding word line wire207to a programming voltage Vthwhile a corresponding bit line wire203and a corresponding source line wire201are coupled to ground. The bit line wires203and the source line wires201of non-selected cells may be left floating or set to a voltage such as ½ Vdd. Vthmay be the highest possible threshold voltage for the memory cells101A. For an erase operation, the corresponding word line wire207may be set to −Vthwhile grounding the corresponding bit line wire203and the corresponding source line wire201and holding the other bit line wires203and source line wires201at −½ Vdd. A read operation may include setting the word line wire207to a voltage intermediate between the first threshold voltage and the second threshold voltage, for example ½ Vth, setting the source line wire201to Vdd, setting the bit line wire203to ground, and determining whether a resulting current is above or below a threshold.

FIGS.2-4show one way in which the memory cells101A in the first 3D memory array100A may be coupled within an integrated circuit200to enable read, write, and erase operations. Any other suitable coupling may be used including alternate couplings that cause variations in the numbers of source lines103A, drain lines119A, and gate strips123A that are connected to each source line wire201, bit line wire203, and word line wire207respectively.FIGS.2-3show all the connections being made through vias209and vias205that connect to source line wires201, bit line wires203, and word line wires207disposed in the metal interconnect layer301D above the first 3D memory array100A, but some or all of these connections may be made to wires in a metal interconnect layer301C below the first 3D memory array100A. Using both the metal interconnect layer301C and the metal interconnect layer301D to make these connections may enable reductions in parasitic resistances and capacitances.

As shown inFIG.3, the first 3D memory array100A may be disposed between the metal interconnect layer301C and the metal interconnect layer301D within a metal interconnect structure315over a substrate309. The metal interconnect layer301C and the metal interconnect layer301D may be the 3rdand 4thmetal interconnect layers, the 4thand 5thmetal interconnect layers, or any other adjacent pair of metal interconnect layers in the metal interconnect structure315. The substrate309may be a semiconductor substrate and may support field effect transistors (FETs)307and other devices used to operate the first 3D memory array100A. These devices may be connected to the first 3D memory array100A through wires303and vias305within the metal interconnect structure315.

The substrate309may be a die cut from a wafer, such as a silicon wafer or the like. The substrate309may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. Other substrates, such as a multilayered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate309is or includes silicon, germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, gallium indium arsenide phosphide, combinations thereof, or the like. The substrate309may be or include a dielectric material. For example, the substrate309may be a dielectric substrate or may include a dielectric layer on a semiconductor substrate. The dielectric material may be an oxide such as silicon oxide, a nitride such as silicon nitride, a carbide such as silicon carbide, combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, the like, or any other suitable dielectric.

With reference toFIG.3, the substrate309has a major surface308. A direction D4is perpendicular to the major surface308. The direction D4is the one referred to herein as the vertical direction and is also a stacking direction for the stacks135A. A direction D5is perpendicular to the direction D4, is parallel to the major surface308, is a direction along which the gate strips123A extend, and is referred to herein as a horizontal direction.

The memory cells101A may be any type of memory cell that has the structure of a transistor. In some embodiments, the memory cells101A are ferroelectric memory cells and the data storage film111A is or comprises a ferroelectric material that contains electrical dipoles and retains polarization of those dipoles. Examples of ferroelectric materials that may be suitable include hafnium zirconium oxide (HfZrO), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium cerium oxide (HfCeO), hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium gadolinium oxide (HFGdO), or the like. In some embodiments, the ferroelectric material is a doped hafnium oxide. In some embodiments, the doped hafnium oxide is in the orthorhombic phase. In some embodiments, the dopant is present in an atomic percentage of 50% or less.

In some embodiments, a thickness of the data storage film111A is in a range from about 5 nanometers to about 20 nanometers. In some embodiments, the thickness is from about 5 to about 10 nanometers. In some embodiments, the thickness is from about 10 to about 20 nanometers. If the data storage film111A is a ferroelectric material and the thickness is too small (e.g., less than about 5 nanometer), polarization may not be well retained and reliability may be low. If the thickness is too large (e.g., greater than about 20 nanometers), program and erase voltages may be large and adversely affect power efficiency.

If the memory cells101A are ferroelectric memory cells, the data storage structure108A of each of the memory cells101A includes a portion of the data storage film111A. The data storage structure108A may further include a gate dielectric layer (not shown) between the data storage film111A and the channel113A. The gate dielectric layer may be deposited as a separate layer or may be allowed to form spontaneously by a reaction such as a reaction between the data storage film111A and the channel layer107A. The gate dielectric layer may be of any suitable material. For example, the gate dielectric layer may be or include silicon oxide (e.g., SiO2), aluminum oxide (e.g., Al2O3), silicon oxynitride (e.g., SiON), silicon nitride (e.g., Si3N4), lanthanum oxide (e.g., La2O3), strontium titanium oxide (e.g., SrTiO3), undoped hafnium oxide (e.g., HfO2), a combination thereof, or the like. In some embodiments, the gate dielectric layer is or includes a high k dielectric, which is a material having a dielectric constant greater than about 3.9. In various embodiments, the gate dielectric layer has a dielectric constant of about 3.9-15, about 3.9-10, or about 10-15.

In some embodiments, a thickness of the gate dielectric layer is less than about 2.5 nanometers. In some embodiments, the thickness is about 1.5-2.5 nanometers. In some embodiments, the thickness is about 1.5-1.8 nanometers. In some embodiments, the thickness is about 1.7-2.5 nanometers. If the thickness is too small (e.g., about 1 nanometer or less), data retention may be low. If the thickness is too great (e.g., greater than about 2.5 nanometers), the program and erase voltages may be too large or the memory window (i.e., a difference between the high and low threshold voltages) may be too small. High program and erase voltages reduce power efficiency and a small memory window reduces reliability.

The channel layer107A may be or include a semiconductor. In some embodiments, the channel layer107A is or includes an oxide semiconductor. An oxide semiconductor may react with a ferroelectric material to spontaneously form the gate dielectric layer. Oxide semiconductors that may be suitable for the channel layer107A include, without limitation, zinc oxide (ZnO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium zinc tin oxide (InGaZnSnO or IGZTO), indium tin oxide (InSnO or ITO), combinations thereof, or the like. In some embodiments, the channel layer107A is or includes polysilicon, amorphous silicon, or the like. In some embodiments, the channel layer has a thickness from about 2 nm to about 30 nm. In some embodiments, the channel layer has a thickness from about 2 nm to about 10 nm. In some embodiments, the channel layer has a thickness from about 5 nm to about 20 nm.

In some embodiments, the memory cells101A are floating gate memory cells and the data storage structure108A is a charge storage structure. In these embodiments, programming involves storing or removing a charge from a data storage film111A between two dielectric layers. Each of the two dielectric layers may be an oxide such as silicon oxide, a nitride such as silicon nitride, a carbide such as silicon carbide, combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, or the like. The data storage film111A may also be a dielectric of one of these types or some other type. For example, the data storage structure108A may be an ONO structure in which a the data storage structure108A is a nitride layer and is sandwiched between two oxide layers.

The gate strips123A are conductive structures formed by one or more layers of conductive materials. Suitable conductive materials for the gate strips123A may include doped polysilicon, conductive carbon-based materials such as graphene and microcrystalline graphite, and metals. In some embodiments, the conductive material includes a metal. Forming the gate strips123A of metal may provide a compact design with low parasitic resistance. Some examples of metals that may be used are tungsten (W), copper (Cu), ruthenium (Ru), molybdenum (Mo), cobalt (Co), aluminum (Al), nickel (Ni), silver (Ag), gold (Au) the like, and alloys thereof. In some embodiments, the gate strips123A further include a diffusion barrier layer, a glue layer, or other such layer bordering abutting dielectric strips131A. Some examples of materials that may be used for a diffusion barrier layer or a glue layer are titanium nitride (TiN), tantalum nitride (TaN), molybdenum nitride (MoN), zirconium nitride (ZrN), hafnium nitride (HfN), and the like. In some embodiments, a portion of the diffusion barrier or glue layer extends vertically through a central area of the gate strip123A. This vertical portion may indicate the gate strip was formed using a replacement gate process that is described more fully below. The vertical portion may have approximately twice a thickness of a portion of the diffusion barrier or glue layer that abuts the dielectric strip131A. In some embodiments, the conductive material is carbon-based. Forming the gate strips123A of a carbon-based material may facilitate patterning the stacks135A.

The source lines103A and the drain lines119A may also be formed of any suitable conductive material. The examples given for the gate strips123A are also applicable to the source lines103A and the drain lines119A. As with the gate strips123A, the source lines103A and the drain lines119A may also include a glue layer or a diffusion barrier layer.

An intracell dielectric115A provides fill and insulation between pairs of source lines103A and drain lines119A corresponding to individual memory cells101A. The intercell dielectric plugs121A provide fill and insulation between pairs of source lines103A and drain lines119A corresponding to horizontally adjacent memory cells101A. The intracell dielectric115A, the intercell dielectric plugs121A, and the dielectric strips131A may each be any suitable dielectric. Suitable dielectrics for these structures may be, for example, oxides such as silicon oxide, nitrides such as silicon nitride, carbides such as silicon carbide, combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, or the like. Distinct dielectrics may be selected for the intracell dielectric115A and the intercell dielectric plugs121A in order to provide etch selectivity and facilitate manufacturing.

In some embodiments, a height H1of the dielectric strips131A and a height H2of the gate strips123A are each in a range from about 15 nm to about 90 nm. In some embodiments, the height H1is in a range from about 15 nm to about 45 nm. In some embodiments, the height H1is in a range from about 45 nm to about 90 nm. In some embodiments, the height H2is in the range from about 15 nm to about 30 nm. In some embodiments, the height H2is in the range from about 30 nm to about 60 nm. In some embodiments, the height H1is greater than the height H2. In some embodiments, the height H2is greater than the height H1. In some embodiments, the height H1is within a factor of three of the height H2. In some embodiments, the height H1is within a factor of two of the height H2. The width W2of the dielectric strips131A is also a width of the stacks135A. In some embodiments, the width W2is in a range from about 10 nm to about 200 nm. In some embodiments, the width W2is in a range from about 20 nm to about 120 nm.

The source lines103A and the drain lines119A may be of similar sizes to one another. In some embodiments, a width W1and a length L2of the source lines103A and the drain lines119A is in a range from about 20 nm to about 100 nm. In some embodiments, the width W1and the length L2are each in a range from about 30 nm to about 80 nm. In some embodiments, areas of the source lines103A and the drain lines119A in a horizontal plane are in a range from 500 nm2to about 10,000 nm2. In some embodiments, the areas are in a range from 900 nm2to about 6,000 nm2.

In some embodiments, a width D2between adjacent stacks135A is approximately the width W1of the source lines103A and the drain lines119A plus twice a thickness of the channel layer107A and twice a thickness of the data storage structures108A. In some embodiments the width D2is from about 40 nm to about 250 nm. In some embodiments the width D2is from about 60 nm to about 140 nm.

In some embodiments, a length L1of the channels113A is in a range from about 30 nm to about 200 nm. In some embodiments, the length L1is in a range from about 60 nm to about 150 nm. In some embodiments, a spacing S1between adjacent memory cells101A within a tier141A-D is in a range from about 30 nm to about 200 nm. In some embodiments, the spacing S1is in a range from about 30 nm to about 100 nm. In some embodiments, the spacing S1is in a range from about 60 nm to about 200 nm.

FIGS.5A and5Billustrate cross-sections of a second 3D memory array100B. The second 3D memory array100B has memory cells101B and is generally similar to the first 3D memory array100A and has corresponding features except that the 3D memory array100B has oval cell areas122B. Each cell area122B is bounded on two opposite sides by stacks135B and on two opposite ends by intercell dielectric plugs121B. The ends of the cell areas122B that abut the intercell dielectric plugs121B have elliptical shapes. The intercell dielectric plugs121B have correspondingly shaped concave ends. A data storage structure108B and a channel layer107B are formed conformally on the perimeter of the cell area122B. The data storage structure108B includes at least a data storage film111B.

A source line103B and a drain line119B are disposed at opposite ends of the cell area122B just inside the channel layer107B. Each of the source line103B and the drain line119B has a first side118B that abuts the channel layer107B and a second side116B that abuts the intracell dielectric115B. The first side118B traces an arc on a first ellipse and the second side116B traces an arc of a second ellipse. The shape of the first side118B is determined by a shape of the channel layer107B which in turn is determined by a shape of a concave end of an intercell dielectric plug121B. In some embodiments, the channel113B is provided by a portion of the channel layer107B that is flat. In some embodiments, all or part of the source area105B and the drain area117B is provided by a portion of the channel layer107B that is curved.

The oval shape of the cell area122B allows the source lines103B and the drain lines119B to be formed with nearly circular openings while assuring good contact with the channel layer107B. Making the openings nearly circular facilitates making the bulges106B large while also keeping the channel length L1large. The second side116B in a horizontal cross-section like the one shown inFIG.1Ctraces an arc on an ellipse and opening size is related to the length of a minor axis of that ellipse. In some embodiments, the minor axis is between 75% and 200% a distance D6between the channels113B on opposite sides of the intracell dielectric115B. In some embodiments, the minor axis is between 110% and 150% the distance D6. Other examples of 3D memory cells provided herein may use the oval cell areas and/or the near circular source/drain line shapes described in this example.

FIGS.6A and6Billustrate cross-sections of a third 3D memory array100C. The third 3D memory array100C has memory cells101C and is generally similar to the first 3D memory array100A except that the data storage films111C are only formed on sides of the gate strips123C. The data storage films111C may have a mushroom shape that results from the data storage films111C having been formed by a selective growth process. Whereas in the first 3D memory array100A the data storage films111A extend between the source lines103A/the drain lines119A and the intercell dielectric plugs121A, the data storage films111C do not. This allows the source lines103C and the drain lines119C to be larger than the source lines103A and the drain lines119A.

Because the data storage film111C has been grown from the gate strip123C, an upper edge155C of the data storage film111C is above an upper edge153C of the gate strip123C by an amount less than or approximately equal to a thickness of the data storage film111C. Likewise, a lower edge161C of the data storage film111C is below a lower edge163C of the gate strip123C by an amount less than or approximately equal to a thickness of the data storage film111C.

FIGS.7A and7Billustrate cross-sections of a fourth 3D memory array100D. The fourth 3D memory array100D has memory cells101D and is generally similar to the third 3D memory array100C except that the channel layers107D are formed only on the data storage films111D. Whereas in the third 3D memory array100C the channel layers107C are disposed between the source lines103C/the drain lines119C and the intercell dielectric plugs121C, the channel layers107D are not. This allows the source lines103D and the drain lines119D to be larger than the source lines103C and the drain lines119C. The source lines103D and the drain lines119D may abut the intercell dielectric plugs121D.

FIGS.8A and8Billustrate cross-sections of a fifth 3D memory array100E.FIG.8Cprovides a perspective view of the fifth 3D memory array100E. The fifth 3D memory array100E has memory cells101E and is like the third 3D memory array100C in that only the channel layer107E separates the source lines103E/the drain lines119E from the intercell dielectric plugs121E. The main difference is that the data storage film111E are disposed in recesses127E formed in sides of the stacks135E adjacent the gate strips123E. The stacks135E may be wider than the stacks135C by a thickness of the data storage film111E while other dimensions remain the same.

The gate strips123E have gate sidewalls125E that are indented relative to the dielectric sidewalls129E to create the recesses127E in the stacks135E. The recesses127E are regions inward from the dielectric sidewalls129E in a cross section extending along a vertical direction, which is a stacking direction of the stacks135E. The gate sidewalls125E are concave and indented relative to the dielectric sidewalls129E by a distance D3.

In some embodiments, the data storage films111E fill the recesses127E. The data storage films111E have an upper edge155E and a lower edge161E horizontally aligned respectively with an upper edge153E and a lower edge163E of a gate strip123E. Within the tiers141A-141C, the upper edge153E and the upper edge155E abut an overlying dielectric strip131E. Within the tiers141B-141D, the lower edge161E and the lower edge163E abut an underlying dielectric strip131E. Sidewalls126E of the data storage films111E are vertically aligned with vertically adjacent dielectric sidewalls129E.

FIGS.9A and9Billustrate cross-sections of a sixth 3D memory array100F. The sixth 3D memory array100F has memory cells101F and is similar to the fifth 3D memory array100E but has a channel layer107F that is disposed within recesses127F of stacks135F. In the sixth 3D memory array100F, the channel layers107F are not disposed between the intercell dielectric plugs121F and either the source lines103F or the drain lines119F. In addition to creating more areas for the source lines103F and the drain lines119F, restricting the channel layer107F to the recesses127F may be useful in preventing the channel layer107F from being etched while forming openings for the source lines103F and the drain lines119F.

To make room for the channel layer107F to be disposed in the recesses127F, the dielectric strips131F are made wider than the dielectric strips131E and the recesses127F are made deeper than the recesses127E. The distance between adjacent stacks135F may be made smaller to keep the sixth 3D memory array100F the same size as an equivalent first 3D memory array100A. The sidewalls126F of the data storage films111F are set back from the dielectric sidewalls129F by the distance D7, which is a thickness of the channel layer107F. The gate sidewalls125F are set back from the dielectric sidewalls129F by a distance D6. D6is greater than the distance D7by a thickness of the data storage structure108F.

The data storage structures108F include the data storage films111F and may include additional layers as well, such as dielectric layers. The data storage structures108F together with the channel layers107F fill the recesses127F. In some embodiments, the channel layers107F are entirely contained within the recesses127F. In some other embodiments, an additional channel layer is disposed outside the recesses127F in the configuration of the channel layer107E ofFIG.8B. The channel layer107F has an upper edge156F horizontally aligned with an upper edge155F of the data storage film111F and with an upper edge153F of the gate strip123F. The channel layer107F has a lower edge160F horizontally aligned with a lower edge161F of the data storage film111F and with a lower edge163F of the gate strip123F. Within the tiers141A-141C, the upper edge153F, the upper edge155F, and the upper edge156F each abut an overlying dielectric strip131F. Within the tiers141A-141D, the lower edge160F, the lower edge161F, and the lower edge163E each abut an underlying dielectric strip131F. The channel layer107F has a sidewall164F that is vertically aligned with dielectric sidewalls129F of adjacent dielectric strips131F and sidewalls165F. The channel layer107F has an additional sidewall that is convex and faces an adjacent gate strip123F.

FIGS.10A and10Billustrate cross-sections of a seventh 3D memory array100G.FIG.10Cprovides a perspective view of the seventh 3D memory array100G. The seventh 3D memory array100G has memory cells101G and is generally similar to the first 3D memory array100A and has corresponding features except that the 3D memory array100G has data storage structures108G, which include data storage films111G, and channel layers107G that are formed prior to intercell dielectric plugs121G. As a result of this order of formation, the data storage structure108G and the channel layer107G are disposed between the intercell dielectric plugs121G and adjacent gate strips123G but not between the intercell dielectric plugs121G and either the source lines103G or the drain lines119G. As a consequence, the source lines103G and the drain lines119G may be larger than the source lines103A and the drain lines119A.

FIGS.11A and11Billustrate cross-sections of an eighth 3D memory array100H according to some other aspects of the present teachings. The eighth 3D memory array100H has memory cells101H and has features corresponding to the first 3D memory array100A. The eighth 3D memory array100H has a dielectric layer173disposed between the data storage film111H and the gate strip123H and another dielectric layer171disposed between the data storage film111H and the channel layer107H. The data storage structure108H includes the dielectric layer173, the data storage film111H, and the dielectric layer171, and may be, for example, an ONO data storage structure.

FIGS.12A and12BthroughFIGS.18A and18Bare a series of paired top view illustrations and cross-sectional view illustrations exemplifying a method according to the present teachings of forming a device comprising a 3D memory array with features of the first 3D memory array100A. WhileFIGS.12A and12BthroughFIGS.18A and18Bare described with reference to various embodiments of a method, it will be appreciated that the structures shown inFIGS.12A and12BthroughFIGS.18A and18Bare not limited to the method but rather may stand alone separate from the method. WhileFIGS.12A and12BthroughFIGS.18A and18Bare described as a series of acts, it will be appreciated that the order of the acts may be altered in other embodiments. WhileFIGS.12A and12BthroughFIGS.18A and18Billustrate and describe a specific set of acts, some acts that are illustrated and/or described may be omitted in other embodiments. Further, acts that are not illustrated and/or described may be included in other embodiments. While the method ofFIGS.12A and12BthroughFIGS.18A and18Bis described in terms of forming the first 3D memory array100A, the method may be used to form other memory arrays.

As shown by the top view1200A ofFIG.12Aand the cross-sectional view1200B ofFIG.12B, the method begins with forming a broad stack1205of alternating gate layers1201and dielectric layers1203over a dielectric layer317. The dielectric layer317may be one or more layers formed over the metal interconnect layer301C as shown inFIG.3, but more generally could be the top layer of any suitable substrate. In the broad stack1205, the top and bottom layers are gate layers1201, but either could be a dielectric layer1203.

The dielectric layers1203and the gate layers1201may be formed by any suitable process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. In some embodiments, the gate layers1201are dummy layers that are later replaced by conductive material to provide gate strips. In some embodiments, the gate layers1201have the composition of gate strips. In some embodiments, the gate layers1201are metallic. In addition to the processes noted above, a metallic layer may be formed by electroplating, electroless plating, or the like.

As shown by the top view1300A ofFIG.13Aand the cross-sectional view1300B ofFIG.13B, a mask1301may be formed and used to pattern trenches1303that divide the broad stack1205into a series of stacks135A. The mask1301may be a hard mask of any suitable material. The mask1301may be formed by a CVD process, a spin-on process, the like, or any other suitable process. The mask1301may be patterned by etching through a photoresist mask (not shown). The photoresist mask may be pattern by photolithography.

The stacks135A may include gate strips123A formed from the gate layers1201and dielectric strips131A formed from the dielectric layers1203. A ratio of a height H3to a width D2is an aspect ratio of the trenches1303. In some embodiments, the aspect ratio is in a range from about 5 to about 15. Forming trenches1303with an aspect ratio of less than about 5 may compromise the cell density of the 3D memory array100A. Forming trenches1303with an aspect ratio greater than about 15 may cause twisting or collapsing of the stacks135A during processing.

As shown by the top view1400A ofFIG.14Aand the cross-sectional view1400B ofFIG.14B, the trenches1303may be filled by depositing intercell dielectric1401. The intercell dielectric may be deposited by CVD, the like, or any other suitable process. Excess material may be removed by CMP.

As shown by the top view1500A ofFIG.15Aand the cross-sectional view1500B ofFIG.15B, a mask1501may be formed and used in conjunction with the mask1301to etch and define cell areas122A in the intercell dielectric1401. The remaining intercell dielectric1401forms the intercell dielectric plugs121A. The cell areas122A correspond to desired locations for memory cells101A, one to be formed on each of two facing sides of each of the cell areas122A.

As shown by the top view1600A ofFIG.16Aand the cross-sectional view1600B ofFIG.16B, layers of the data storage structure108A, which include at least the data storage film111A, and the channel layer107A may be deposited within the cell areas122A. These are vertical films that form around the perimeters of the cell areas122A. As further shown by the top view1600A ofFIG.16Aand the cross-sectional view1600B ofFIG.16B, remaining portions of the cell areas122A may be filled with intracell dielectric115A. These layers may be formed by CVD, ALD, the like, or any other suitable process. Excess material may be removed by planarization process such as CMP.

As shown by the top view1700A ofFIG.17Aand the cross-sectional view1700B ofFIG.17B, a mask1701with openings1705may be formed and used to etch openings1703in the intracell dielectric115A. In accordance with some aspects of the present teachings, the openings1705may be elliptical. The openings1705are approximately centered over intercell dielectric plugs121A. Each of the openings may have a first end that extends over the intracell dielectric115A on one side of an intercell dielectric plug121A and a second end that extends over an opposite side of the intercell dielectric plug121A. The etch process may be anisotropic and selective to remove the exposed intracell dielectric115A without substantially etching either the intercell dielectric plugs121A, the data storage film111A, or the channel layer107A. The etch process may be a plasma etch, the like, or any other suitable process.

As shown by the top view1800A ofFIG.18Aand the cross-sectional view1800B ofFIG.18B, the openings1703may be filled with conductive material to form the source lines103A and the drain lines119A. Due to the shapes of the openings1703, the source lines103A and the drain lines119A form with bulges106A. A CMP process may remove excess conductive material, the mask1301, and the mask1701. The resulting structure may be substantially the same as the one shown inFIG.1A-1C.

FIGS.19A and19BthroughFIGS.22A and22Bare a series of paired top view illustrations and cross-sectional view illustrations showing a variation on the methodFIGS.12A and12BthroughFIGS.18A and18B. This variation may be used to form a memory array with features of the second 3D memory array100B ofFIGS.5A-5B. The variation begins with a structure like the one shown by the top view1400A ofFIG.14Aand the cross-sectional view1400B ofFIG.14B. As shown by the top view1900A ofFIG.19Aand the cross-sectional view1900B ofFIG.19B, a mask1901having elliptical openings1903may be formed and used in conjunction with the mask1301to etch and define cell areas122B in the intercell dielectric1401. The remaining intercell dielectric1401forms the intercell dielectric plugs121B. The cell areas122B include planar sides formed where the elliptical openings1903extended over the stacks135B and elliptical ends between the stacks135B. The intercell dielectric plugs121B have concave ends with profiles corresponding to the elliptical openings1903.

As shown by the top view2000A ofFIG.20Aand the cross-sectional view2000B ofFIG.20B, the layers of the data storage structure108B, which include at least the data storage film111B, and the channel layer107B may then be deposited and the remainder of the cell areas122A may be filled with intracell dielectric115B. The data storage film111B and the channel layer107B may have shapes determined by the shapes of the perimeters of the cell areas122B, including convex curved ends that trace elliptical arcs.

As shown by the top view2100A ofFIG.21Aand the cross-sectional view2100B ofFIG.21B, a mask2101may be formed with openings2105and used to etch openings2103in the intracell dielectric115B. In contrast to the case shown by the top view1700A ofFIG.17A, one opening2105is provided for each of the openings2103that is to be formed in the intracell dielectric115B. The openings2105are smaller than the openings1705and may have a smaller radius of curvature. In some embodiments, the openings2105are circular or are ellipses that are nearly circular. As shown by the top view2200A ofFIG.22Aand the cross-sectional view2200B ofFIG.22B, the openings2103may be filled with conductive material to form the source lines103B and the drain lines119B.

The openings2103in the intracell dielectric115B may have a first side2107that faces toward an adjacent intercell dielectric plug121B and a second side2109the faces an interior of the cell area122B. The first side2107is rimed by the channel layer107B and the second side2109is rimmed by the intracell dielectric115B. If the cell area122B did not have curved ends but was rectangular like the cell area122A, the first side2107might not be fully rimmed by the channel layer107B and the source lines103B and the drain lines119B might not make sufficient contact with the channel layer107B. That issue may be avoided with larger openings2105, but that approach may reduce the areas of the bulges106B.

FIGS.23A and23BthroughFIGS.25A and25Bare a series of paired top view illustrations and cross-sectional view illustrations showing a variation on the methodFIGS.12A and12BthroughFIGS.18A and18Bthat may be used to form a memory array with features of the fourth 3D memory array100D ofFIGS.7A-7B. The variation begins with a structure like the one shown by the top view1500A ofFIG.15Aand the cross-sectional view1500B ofFIG.15B. As shown by the top view2300A ofFIG.23Aand the cross-sectional view2300B ofFIG.23B, a data storage structure108D and a channel layer107D may be formed selectively on the exposed portions of the gate strips123D. The data storage structure108D includes the data storage film111D. To form the third 3D memory array100C ofFIGS.6A-6B, the channel layer107C is deposited non-selectively rather than by a selective growth process.

In some embodiments, a selective growth process includes forming a self-assembled monolayer (SAM) on the sidewalls of the dielectric strips131D and the intercell dielectric plugs121D. An ALD process or the like may then be used to grow the data storage film111D on the gate strips123D while the SAM blocks growth on the dielectric strips131D. The SAM may include molecules that have a head group that adsorbs preferentially on the dielectrics and a tail group that resist the ALD process. The selective growth process may give the data storage films111D a characteristic mushroom shape. A similar process may be used to grow the channel layer107D on the data storage film111D.

In some embodiments, the selective growth process includes forming a seed layer for the growth of the data storage film111D on the gate sidewalls125D. In some embodiments, the seed layer is provided by etching the gate strips123D to form recesses in the gate stacks135D by depositing the seed layer, and anisotropic etching to remove the seed layer from outside the recesses whereby the remaining seed layer is restricted to the gate strips123D.

As further shown by the top view2300A ofFIG.23Aand the cross-sectional view2300B ofFIG.23B, the remaining cell area may then be filled with the intracell dielectric115D. As shown by the top view2400A ofFIG.24Aand the cross-sectional view2400B ofFIG.24B, a mask2401may then be formed and used to etch openings2403in the intracell dielectric115D. The etch may be selective to remove the exposed intracell dielectric115D without removing the intercell dielectric plugs121D or the channel layer107D. The channel layer107D may protect the data storage film111D from etching during this process. As shown by the top view2500A ofFIG.25Aand the cross-sectional view2500B ofFIG.25B, the openings2403may be filled with conductive material to provide source lines103D and drain lines119D.

FIGS.26A and26BthroughFIGS.30A and30Bare a series of paired top view illustrations and cross-sectional view illustrations showing a variation on the methodFIGS.12A and12BthroughFIGS.18A and18Bthat may be used to form a memory array with features of the fifth 3D memory array100E ofFIGS.8A-8B. The variation begins with a structure similar to the one shown by the top view1500A ofFIG.15Aand the cross-sectional view1500B ofFIG.15Bexcept that the mask2601may have narrower openings than the mask1301, the stacks135E may be wider than the stacks135A and the cell areas122E may be proportionally narrower than the cell areas122A.

As shown by the top view2600A ofFIG.26Aand the cross-sectional view2600B ofFIG.26B, etching may take place within the cell areas122E to form recesses127E in the gate strips123E. The intercell dielectric plugs121E may block the etching that forms the recesses127E, whereby one recess127E is formed for each desired location for a memory cells101E. The etch process is selective for removing the material of gate strips123E over the material of the dielectric strips131E. The etch causes gate sidewalls125E to be indented relative to dielectric sidewalls129E. The etch may also cause gate sidewalls125E to become concave as shown. In some embodiments, the etch is isotropic. In some embodiments, the etch is a wet etch.

As shown by the top view2700A ofFIG.27Aand the cross-sectional view2700B ofFIG.27B, a data storage film111E is deposited on the sides of the stacks135E including sides within the trenches1303. The data storage film111E may deposit conformally on the gate sidewalls125E and the dielectric sidewalls129E. The deposition process may be CVD, ALD, the like, or any other suitable process. The data storage film111E may form continuous layers extending across the heights of the stacks135E. Additional layers may be deposited before or after the data storage film111E if desired to form the data storage structures108E. The data storage film111E may be etched to remove portions of the data storage film111E that deposit between the tiers141A-141D. The removed portions include those that are deposited on the dielectric sidewalls129E. The remaining portions of the data storage film111E are contained within the recesses127E. The etch is anisotropic. The anisotropic etch may be a plasma etch or the like or any other suitable etch process. The mask2601may align the etch to the stacks135E.

As shown by the top view2800A ofFIG.28Aand the cross-sectional view2800B ofFIG.28B, the channel layers107E may be deposited on the sides of the stacks135E. The channel layer107E may deposit conformally on the data storage film111E and on the dielectric sidewalls129E. The deposition process may be CVD, ALD, the like, or any other suitable process. The channel layers107E may be continuous across the heights of the stacks135E. One or more additional layers may be deposited before the channel layers107E if desired to complete the formation of the data storage structures108E. In some embodiments, the data storage structures108E are completed by a dielectric layer that forms during deposition of the channel layers107E.

As further shown by the top view2800A ofFIG.28Aand the cross-sectional view2800B ofFIG.28B, an intracell dielectric115E may be deposited to fill the cell areas122E. The deposition process may be CVD, the like, or any other suitable process. In some embodiments, the deposition includes a flowable CVD process. Following deposition of the intracell dielectric115E, a planarization process may be used to remove any intracell dielectric115E or other material above the mask2601.

As shown by the top view2900A ofFIG.29Aand the cross-sectional view2900B ofFIG.29B, a mask2903with openings2905is used to etch openings2901in the intracell dielectric115E. As shown by the top view3000A ofFIG.30Aand the cross-sectional view3000B ofFIG.30B, the openings2901may be filled with conductive material to form source lines103E and drain lines109E. Excess conductive material, the mask2903, and the mask2601may be removed by CMP, the like, or other suitable processes to produce the illustrated structure which corresponds to the fifth 3D memory array100E ofFIGS.8A-8C.

The sixth 3D memory array100F ofFIGS.9A-9Bmay be produced by following essentially the same process except that the channel layer107F is formed along with the data storage film111F in the recesses127F and is limited to the recesses127F by an anisotropic etch process. Optionally an additional channel layer may subsequently be deposited to form a structure in which the channel layer if partially with the recesses and shown inFIGS.9A-9Band partially outside the recesses as shown inFIGS.8A-8B.

FIGS.31A and31BthroughFIGS.35A and35Bare a series of paired top view illustrations and cross-sectional view illustrations showing a variation on the methodFIGS.12A and12BthroughFIGS.18A and18Bthat may be used to form a memory array with features of the seventh 3D memory array100G ofFIGS.10A-10C. A principal difference is that the data storage structures108G and the channel layers107G are formed prior to the intercell dielectric plugs121G.

The variation begins with a structure like the one shown by the top view1400A ofFIG.14Aand the cross-sectional view1400B ofFIG.14B. As shown by the top view3100A ofFIG.31Aand the cross-sectional view3100B ofFIG.31B, trenches between the stacks135G are filled by successively depositing the layers of a data storage structure108G, a channel layer107G, and intracell dielectric115G. The layers of the data storage structure108G include at least a data storage film111G.

As shown by the top view3200A ofFIG.32Aand the cross-sectional view3200B ofFIG.32B, a mask3201may formed and used to etch openings3203in the intracell dielectric115G. As shown by the top view3300A ofFIG.33Aand the cross-sectional view3300B ofFIG.33B, the openings3203may be filled with intercell dielectric to form the intercell dielectric plugs121G. Alternatively, the intercell dielectric may be formed first and the inverse of the mask3201may be used to etch the cell areas122G. An etch defining opening for the intercell dielectric plugs121G need not be as selective. In this example, the etch removes an exposed portion of the channel layer107G.

As shown by the top view3400A ofFIG.34Aand the cross-sectional view3400B ofFIG.34B, a mask3401may be formed and used to etch openings3403in the intracell dielectric115G. As shown by the top view3500A ofFIG.35Aand the cross-sectional view3500B ofFIG.35B, the openings3403may be filled with conductive material to form source lines103G and drain lines119G. The resulting structure corresponds to seventh 3D memory array100G ofFIGS.10A-10C.

FIGS.36through43provide cross-sectional views illustrating a variation on the method ofFIGS.12A through18B. The illustrated process also incorporates variations illustrated byFIGS.31A and31BthroughFIGS.35A and35Bbut may be applied in conjunction with any of the methods shown herein to produce any of the 3D memory arrays. This alternate method avoids a process stage at which the stacks135A or the like are left freestanding as shown the cross-sectional view1300B ofFIG.13B. When left freestanding, the stacks135A may have the potential to twist, collapse, or otherwise shift or deform. The method also provides an opportunity to initially form the gate layer with a dummy layer and subsequently replace that layer with the material of the gate strips.

As shown be the cross-sectional view3600ofFIGS.36, a mask3601is formed and used to etch trenches3607that divide a broad stack3609into smaller stacks3605. The broad stack3609may be the same as the broad stack1205ofFIG.12B, or may have dummy gate layers3603in place of gate layers1201. The dummy gate layers3603may be a dielectric with a different etch selectivity from the dielectric layers1203. The dummy gate layers3603may alternatively be polysilicon, the like, or any other suitable material. The trenches3607may have the same dimensions as the trenches1303ofFIG.13B, but are half or less in number density.

As shown by the cross-sectional view3700ofFIG.37, the dummy gate layers3603may be etched back from surfaces exposed adjacent the trenches3607to form recesses3701. The etch process may remove approximately half the volume of the dummy gate layers3603. The etch process may be an isotropic etch. For example, the dielectric layers1203may be silicon oxide, the dummy gate layers3603may be silicon nitride, and the recesses3701may be formed by wet etching with phosphoric acid (H3PO4).

As shown by the cross-sectional view3800ofFIG.38, the recesses3701may be filled by depositing a barrier layer3801and a metal layer3803. These layers may be deposited by CVD, ALD, electroplating, electroless plating, the like, or any other suitable process or combination of processes. After depositing the metal layer3803in an amount sufficient to complete the fill of the recesses3701, excess material may be removed by an anisotropic etch process.

As shown by the cross-sectional view3900ofFIG.39, the trenches3607are filled. In this example, the trenches3607are filled by the process steps illustrated by the top view3300A ofFIG.33Aand the cross-sectional view3300B ofFIG.33B. These process steps form the data storage structures108G, the channel layers107G, and complete the fill of the trenches3607with intracell dielectric115G. Alternatively, the trenches3607could be filled by the process steps shown inFIGS.14A and14BthroughFIGS.16A and16B.

As shown by the cross-sectional view4000ofFIG.40, a mask4003may then be formed and used to etch trenches4001in the stacks3605. As shown by the cross-sectional view4100ofFIG.41, remaining portions of the dummy gate layer3603may be removed by etching to form the recesses4101. As shown by the cross-sectional view4200ofFIG.42, the recesses4101may be filled by depositing a second barrier layer4201and a second metal layer4203and the excess material may be removed by anisotropic etching. As shown by the cross-sectional view4300ofFIG.43, the trenches4001may be filled by repeating the process steps illustrated by the top view3300A ofFIG.33Aand the cross-sectional view3300B ofFIG.33B. Processing may continue, e.g., as shown by the top view3400A ofFIG.34Aand the cross-sectional view3400B ofFIG.34B. The method ofFIG.36throughFIG.43, with or without the replacement gate process steps, may be used to form other structures in accordance with other embodiments and examples provided herein to provide the advantage of preventing twisting, collapsing or other deformation that may occur with narrow free standing stacks.

FIG.44presents a flow chart for a method4400which may be used to form a 3D memory arrays according to the present disclosure. The method4400begins with act4401, forming a broad stack of alternating gate layers and dielectric layers as shown by the cross-sectional view1200B ofFIG.12B.

Act4403is etching trenches in the broad stack to form a row of narrow stacks of alternating gate strips and dielectric strips as shown by the cross-sectional view1300B ofFIG.13B.

Act4405is filling the trenches between the narrow stack with intercell dielectric as shown by the cross-sectional view1400B ofFIG.14B. Act4407is patterning the intercell dielectric to define the cell areas and form intercell dielectric plugs. The cross-sectional view1500B ofFIG.15Bprovides an example in which the cell areas are made rectangular and the intercell dielectric plugs are formed with planar ends. The cross-sectional view1900B ofFIG.19Bprovides an example in which the cell areas are made elliptical and the intercell dielectric plugs are formed with concave ends.

Act4409is an optional act of etching the gate strips to form recesses in the narrow stacks. The cross-sectional view2600B ofFIG.26Bprovides an example.

Act4411is an optional step of forming a top layer of a data storage structure. “Top” is used with reference to the ordering of layers seen in a horizontal memory cell. In particular, the top layer is one or more layers formed between the data storage film and the control gate. The dielectric layer173shown inFIGS.11A and11Bis an example.

Act4413is forming a data storage film. The cross-sectional view1600B ofFIG.16Bprovides a basic example. The cross-sectional view2300B ofFIG.23Bprovides an example in which the data storage film is formed by a selective growth process. The cross-sectional view2700B ofFIG.27Bprovides an example in which the data storage film is formed in recesses within the narrow stacks. The cross-sectional view2700B ofFIG.27Balso illustrates act4415, which is an optional step of etching the data storage film to remove any portion of the data storage film that has deposited outside the recesses. The etching may include a directional or anisotropic etch that removes the data storage film from areas outside the recesses. The etching may also include an isotropic etch that cause the data storage film to be indented within the recesses to provide room in the recesses for a channel layer.

Act4417is an optional step of forming a bottom layer of the data storage structure. “Bottom” is used with reference to the ordering of layers seen in a horizontal memory cell. In particular, the bottom layer is one or more layers formed between the data storage film and the channel. The dielectric layer171shown inFIGS.11A and11Bis an example.

Act4419is forming a channel layer. The cross-sectional view1600B ofFIG.16B, the cross-sectional view2300B ofFIG.23B, and the cross-sectional view2800B ofFIG.28Bprovide various examples.

Act4421is an optional step of anisotropic etching to remove a portion of the channel layer that is outside the recesses. This may be used to produce a structure such as the one illustrated inFIGS.9A and9B. Act4423is an optional step of depositing another layer of the channel material. This step may be used when act4421leaves the channel layer too thin.

Act4425is depositing the intracell dielectric. The cross-sectional view1600B ofFIG.16B, the cross-sectional view2300B ofFIG.23B, and the cross-sectional view2800B ofFIG.28Bprovide various examples.

Act4431is etching to form openings for vertical connectors such as source lines and drain lines. This etch may be made with oval mask openings to provide bulges in the source lines and drain lines. In some embodiments, two source line/drain line openings are formed for each mask opening and the etch is aligned in part by the intercell dielectric plugs. The top view1700A ofFIG.17A, the top view2400A ofFIG.24, and the top view2900A ofFIG.29Aprovide various examples. In some embodiments, one source line/drain line opening is formed for each mask opening and the mask openings may be circular or nearly so. The top view2100A ofFIG.21Aprovides an example.

Act4433is filling the openings to provide vertical conductive structures such as source lines and drain lines. The top view1800A ofFIG.18A, the top view2200A ofFIG.22A, the top view2500A ofFIG.25, and the top view3000A ofFIG.30Aprovide various examples.

FIG.45presents a flow chart for a method4500, which is another method that may be used to form a 3D memory array according to the present disclosure. The method4500include many of the same acts as the method4400, but has differences relating to the intercell dielectric plugs being formed after the data storage structures and the channel layers.

In the method4500, the intercell dielectric plugs are not formed until act4419, the channel layer deposition. This alternate processing is illustrated by the paired top view illustrations and cross-sectional view illustrations provided byFIGS.31A and31BthroughFIGS.35A and35B.

The method4500includes act4527, a cell area definition etch illustrated by top view3200A ofFIG.32Aand cross-sectional view3200B ofFIG.32B. The etch defines the cell areas by removing the intracell dielectric from locations for the intercell dielectric plugs. Act4529is filling the openings with the intercell dielectric to form the intercell dielectric plugs. Alternatively, the intercell dielectric may be deposited in Act4425and the cell area definition etch of Act4527may be used to remove that intercell dielectric from the cell areas followed by backfill with the intracell dielectric.

FIG.46presents a flow chart for a method4600, which is another method that may be used to form a 3D memory array according to the present disclosure. The method4600include many of the same acts as the method4500but uses the type of processing illustrated byFIG.36throughFIG.43.

The method4600includes act4601, forming a broad stack of alternating gate layers and dielectric layers. This may be the same as act4401except that the gate layers may be dummy gate layers. The cross-sectional view1200B ofFIG.12Bprovides an example.

Act4603is forming a first set of trenches. The cross-sectional view3600ofFIG.36provides an example. These trenches are half or less in number compared to the trenches formed by act4403for which the cross-sectional view1300B ofFIG.13Bprovides an example.

Acts4605and4607are optional steps that are used when the gate layer is a dummy layer. Act4605is etching away a first portion of the dummy layer. The cross-sectional view3700ofFIG.37provides an example. Act4607is replacing the first portion of the dummy layer with conductive material. The cross-sectional view3800ofFIG.38provides an example.

The method4600continues with act4411through act4425which may be the same as in the method4400except that they operate within only the first set of trenches. The cross-sectional view3900ofFIG.39provides an example.

Act4609is forming a mask that covers the first set of trenches and etching to form a second set of trenches. The cross-sectional view4000ofFIG.40provides an example. If the gate layer is a dummy gate layer, the method may continue with a repetition of act4605and act4607to complete the gate replacement process. The cross-sectional view4100ofFIG.41and the cross-sectional view4200ofFIG.42illustrate this process.

The method4600continues with a repetition of act4411through act4425. The cross-sectional view4300ofFIG.43provides an example. Processing may continue with act4527, act4529, act4431, and act4433as described in connection with the method4400.

While the methods4400,4500, and4600ofFIGS.44-46are illustrated and described herein as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events is not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. Further, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein, and one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

Some aspects of the present teachings relate to a memory device having a plurality of stacks, each stack having alternately stacked gate strips and dielectric strips, over a substrate. Source lines and drain lines are positioned between the stacks and extend along a stacking direction of the gate strips and the dielectric strips. A memory cell has a channel extending a channel length between one of the source lines and one of the drain lines and a data storage structure positioned between the channel and one the gate strips. A distance between the one of the source lines and the one of the drain lines is less than the channel length.

Some aspects of the present teachings relate to a memory device that includes a three-dimensional array of memory cells disposed between two adjacent metal interconnect layers in a metal interconnect structure. Each of the memory cells has a source side, a drain side, a channel extending between the source side and the drain side, a control gate, and a data storage film between the control gate and the channel. Within the memory device is an array of stacks. Each stack comprising vertically stacked gate strips separated by dielectric strips. The gate strips extend horizontally to connect a plurality of the control gates. Drain lines extends vertically through the memory device. Each drain line connects with a plurality of the drain sides. Source lines also extend vertically through the memory device. Each of the source lines connects with a plurality of the source sides. The source lines and the drain lines are arranged in a row between two adjacent stacks in the array of stacks. Within the row, the source lines and the drain lines are alternately separated by first dielectric plugs and second dielectric plugs, whereby each of the source lines and each of the drain lines has a first side that faces an adjacent first dielectric plug and a second side that faces an adjacent second dielectric plug. The first dielectric plugs and the second dielectric plugs have distinct compositions. The first sides are convex.

Some aspects of the present teachings relate to a method of forming a memory device. The method includes forming a trench within a stack of alternating gate strips and dielectric strips and depositing an intracell dielectric in the trenches. A mask having elliptical openings is formed and the intracell dielectric is etched through the mask to form second openings. The second openings are filled with conductive material to form source lines and drain lines.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.