Patent ID: 12255564

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown, by way of illustration, specific examples in which the present disclosure may be practiced. These examples are described in sufficient detail to enable a person of ordinary skill in the art to practice the present disclosure. However, other examples may be utilized, and structural, material, and process changes may be made without departing from the scope of the disclosure.

The illustrations presented herein are not meant to be actual views of any particular method, system, device, or structure, but are merely idealized representations that are employed to describe the examples of the present disclosure. The drawings presented herein are not necessarily drawn to scale. Similar structures or components in the various drawings may retain the same or similar numbering for the convenience of the reader; however, the similarity in numbering does not mean that the structures or components are necessarily identical in size, composition, configuration, or any other property.

The following description may include examples to help enable one of ordinary skill in the art to practice the disclosed examples. The use of the terms “exemplary.” “by example,” and “for example,” means that the related description is explanatory, and though the scope of the disclosure is intended to encompass the examples and legal equivalents, the use of such terms is not intended to limit the scope of an example of this disclosure to the specified components, steps, features, functions, or the like.

It will be readily understood that the components of the examples as generally described herein and illustrated in the drawing could be arranged and designed in a wide variety of different configurations. Thus, the following description of various examples is not intended to limit the scope of the present disclosure, but is merely representative of various examples. While the various aspects of the examples may be presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

Furthermore, specific implementations shown and described are only examples and should not be construed as the only way to implement the present disclosure unless specified otherwise herein. Elements, circuits, and functions may be depicted by block diagram form in order not to obscure the present disclosure in unnecessary detail. Conversely, specific implementations shown and described are only examples and should not be construed as the only way to implement the present disclosure unless specified otherwise herein. Additionally, block definitions and partitioning of logic between various blocks is an example of a specific implementation. It will be readily apparent to one of ordinary skill in the art that the present disclosure may be practiced by numerous other partitioning solutions. For the most part, details concerning timing considerations and the like have been omitted where such details are not necessary to obtain a complete understanding of the present disclosure and are within the abilities of persons of ordinary skill in the relevant art.

Those of ordinary skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, and symbols that may be referenced throughout this description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings may illustrate signals as a single signal for clarity of presentation and description. It will be understood by a person of ordinary skill in the art that the signal may represent a bus of signals, wherein the bus may have a variety of bit widths and the present disclosure may be implemented on any number of data signals including a single data signal. A person having ordinary skill in the art would appreciate that this disclosure encompasses communication of quantum information and qubits used to represent quantum information.

The various illustrative logical blocks, modules, and circuits described in connection with the examples disclosed herein may be implemented or performed with a general purpose processor, a special purpose processor, a Digital Signal Processor (DSP), an Integrated Circuit (IC), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions. A general-purpose processor (may also be referred to herein as a host processor or simply a host) may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. A general-purpose computer including a processor is considered a special-purpose computer while the general-purpose computer executes computing instructions (e.g., software code, without limitation) related to examples of the present disclosure.

The examples may be described in terms of a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe operational acts as a sequential process, many of these acts can be performed in another sequence, in parallel, or substantially concurrently. In addition, the order of the acts may be re-arranged. A process may correspond to a method, a thread, a function, a procedure, a subroutine, or a subprogram, without limitation. Furthermore, the methods disclosed herein may be implemented in hardware, software, or both. If implemented in software, the functions may be stored or transmitted as one or more instructions or code on computer-readable media. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.

In this description the term “coupled” and derivatives thereof may be used to indicate that two elements co-operate or interact with each other. When an element is described as being “coupled” to or with another element, then the elements may be in direct physical or electrical contact or there may be one or more intervening elements or layers present. In contrast, when an element is described as being “directly coupled” to or with another element, then there are no intervening elements or layers present. It will be understood that when an element is referred to as “coupling” a first element and a second element then it is coupled to the first element and it is coupled to the second element.

Some electronic inverters may provide drive signals to loads (e.g., electrical motors) that may exhibit changes in voltage over time (“dV/dt”) that may exceed operational limits of the loads, cause stress in the loads, or may cause degradation of the loads over time. As a non-limiting example, a drive signal exhibiting a high change in voltage over a short period of time (e.g., several volts per nanosecond, without limitation) may cause stresses in the load which may degrade the load over time. Such dV/dt may be referred to herein as “excessive.” Further, in some cases, excessive dV/dt may cause electromagnetic interference (EMI). Excessive dV/dt may be a result of the speed at which electronic switches in the inverter open or close, i.e., switching speeds of inverters.

Some systems may include a passive filter between an inverter and a load (e.g., a motor). Such passive filters may decrease the impact of the switching speed of the inverter on the load. As a non-limiting example, the passive filters may limit dV/dt at terminals of the load despite switching speeds of the electronic switches.

Silicon Carbide (SiC) metal-oxide semiconductor field-effect transistors (MOSFETs) may exhibit faster switching speeds than other electronic switches (e.g., silicon electronic switches including e.g., MOSFETS or insulated-gate bipolar transistors (IGBTs), without limitation). Thus, inverters using SiC MOSFETs may result in dV/dt at terminals of a load that are excessive, for example, dV/dt that is greater than dV/dt resulting from inverters including other electronic switches.

One or more examples may include a passive filter that may be more effective at limiting dV/dt than conventional passive filters. The passive filter may keep dV/dt within acceptable limits. As a non-limiting example, the passive filter may keep dV/dt at terminals of a load (e.g., an electrical motor) within acceptable limits for the load.

One or more examples may include an inverter for a load (e.g., an electrical motor), the inverter including SiC MOSFETs. Such examples may also include one or more instances of a passive filter such that the one or more passive filters limit dV/dt, despite the inherently fast switching speeds of the SiC MOSFETs.

One or more examples may include inverters that themselves exhibit higher efficiency and further that may allow loads driven thereby to exhibit higher efficiency than other inverters or than loads driven by typical inverters. As a non-limiting example, one or more examples may exhibit increased efficiency as a result of including SiC MOSFETs rather than other electronic switches.

Further, one or more examples may allow for better control of electrical stresses applied to a load as a result of drive signals applied at terminals than other inverters. As a non-limiting example, passive filters as described herein may allow inverters to decreases electrical stresses applied to a load by limiting dV/dt at terminals of the load, and thereby increase reliability of the load.

Further, one or more examples may limit a change in current over time (“di/dt”) which may allow for enhancing efficiency of inverters by reducing turn-on losses of switches compared with other inverters. As a non-limiting example, by using passive filters as described herein, di/dt may be limited, which may in turn decrease turn-on losses of electronic switches of inverters. In some inverters or loads, turn-on losses may represent a significant portion of total power losses.

Although some examples described herein refer to electrical motors, this disclosure is not so limited. One or more examples may be used in any inverter (including, e.g., multi-stage inverters, without limitation) (whether solid-state or not solid-state) designed to drive any suitable load. Some suitable loads may exhibit inductive behavior. For example, some suitable loads may have an inductance greater than inductance of inductors included in passive filters of the inverter. The inductance may be high enough to not interfere with the operation of the examples during the switching frequency period. As non-limiting examples, suitable loads include electrical motors (including e.g., multi-phase electrical motors), and line transformers (e.g., multi-phase line transformers). In one non-limiting example, the inductance of the load is more than 1,000 times greater than the combined inductances of the inductor.

One or more examples may have application in high-power motors (e.g., motors that operate using several kilowatts, without limitation). In such applications, even small gains in efficiency may result in economic benefits. Examples are not, however, limited to high-power applications.

One or more examples included SiC MOSFETs. Other examples may include silicon MOSFETS, Insulated Gate Bipolar Transistors (IGBTs), or other switches, without limitation.

FIG.1is a functional block diagram illustrating an apparatus100according to one or more examples. Apparatus100includes a circuit106(which circuit106may be an inverter) which may efficiently drive a load (e.g., a multi-phase motor) while limiting dV/dt at a terminal112, which may be coupled to the load. Circuit106may, additionally or alternatively, limit di/dt in circuit106(e.g., at a first switch114and a second switch116) and/or in the load. As indicated above, apparatus100may find application in relation to a multi-phase motor, but is not limited to such an application.

Apparatus100may include a circuit106coupled between a supply line108, a return line110, and a terminal112. Circuit106may provide an oscillating signal105to terminal112. Circuit106may include first switch114to couple supply line108with terminal112. Circuit106may include second switch116to couple return line110with terminal112. Circuit106may include a first inductor118coupled between first switch114and terminal112. Circuit106may include a second inductor120coupled between second switch116and terminal112. Circuit106may include a first diode122coupled between return line110and a first internal node126, first internal node126common to both first switch114and first inductor118. Circuit106may include a second diode124coupled between supply line108and a second internal node128, second internal node128common to both second switch116and second inductor120.

Circuit106may provide oscillating signal105at terminal112for a motor (e.g., as a control signal of a multi-phase motor (not illustrated inFIG.1)). The multi-phase motor is given as an example of something to be driven by circuit106. The multi-phase motor may be an electrical motor to be driven by a drive signal at one or more terminals. The multi-phase motor may include three phases and three terminals. Circuit106may likewise include three phases (not illustrated inFIG.1for descriptive purposes).

Circuit106may generate or provide oscillating signal105(e.g., to a multi-phase motor) by alternately electrically coupling terminal112to supply line108and to return line110. Supply line108may provide positive voltage, and current, e.g., for operation of the load (e.g., the multi-phase motor), without limitation. Return line110may be an electrically conductive line to provide a return path for the current. Terminal112may be an electrical node of circuit106. Terminal112may be for electrical coupling to a terminal of the load.

First switch114may electrically couple terminal112to supply line108and second switch116may couple terminal112to return line110. One or the other of first switch114and second switch116may be closed at a time. Thus, first switch114and second switch116may alternately electrically couple terminal112to supply line108and return line110, with a dead time optionally provided between opening one of first switch114and second switch116and the closing of a second one of first switch114and second switch116. First switch114and second switch116may be controlled by a modulator (not illustrated inFIG.1). First switch114or second switch116, or both, may be a SiC MOSFET.

First inductor118may be coupled between first switch114and terminal112. Second inductor120may be coupled between second switch116and terminal112. First inductor118and second inductor120may collectively be a passive filter or portions of a passive filter. As a non-limiting example, first inductor118and second inductor120may respectively resist a change in current flow (“di/dt”) into, or out of, terminal112. Utilizing half of the cycle for case of understanding, when current flows into terminal112from the load, first inductor118may resist a change in a first electrical current from terminal112to first internal node126and second inductor120may resist a change in a second electrical current from terminal112to second internal node128, respectively. It is to be understood that during the second half of the cycle, the above current directions are reversed, but for ease of understanding will not be further detailed. Thus, first inductor118may limit di/dt of the current flowing through the load and first switch114. Limiting di/dt may reduce turn-on losses in first switch114, during the half of the cycle, it being understood that similarly second inductor120may limit di/dt of the current flowing through the load and second switch116during the second half of the cycle. Additionally, first inductor118and second inductor120may, in combination with a first capacitor coupled between supply line108and terminal112and a second capacitor coupled between return line110and terminal112(neither the first capacitor nor the second capacitor is illustrated inFIG.1), limit dV/dt.

First inductor118and second inductor120may be separate inductors, e.g., on separate sides of terminal112, without limitation. First inductor118and second inductor120being separate, and on either side of terminal112, may be advantageous over alternative inverters including a single inductor, for example, between terminal112and the load because first inductor118and second inductor120, as separate components, may more effectively limit di/dt at through first switch114and second switch116respectively. Limiting di/dt through first switch114and second switch116may decrease the turn-on losses of first switch114and second switch116.

First diode122may be coupled between return line110and first internal node126. First internal node126may be defined as a point between first switch114and first inductor118. Second diode124may be coupled between supply line108and second internal node128. Second internal node128may be defined as a point between second switch116and second inductor120. First diode122may act as a clamping diode (or “flyback diode” or “freewheeling diode”) for first inductor118, e.g., to limit a voltage spike when first switch114opens and second switch116closes, e.g., by providing a path for a decay current, without limitation. Second diode124may act as a clamping diode for second inductor120, e.g., to limit a voltage spike when second switch116opens and first switch114closes, e.g., by providing a path for a decay current, without limitation. In one non-limiting example, the inductance of the load is more than 100 times greater than the combined inductances of the first and second inductors118,120. In another non-limiting example, the inductance of the load is more than 1,000 times greater than the combined inductances of the first and second inductors118,120.

FIG.2is a functional block diagram illustrating an apparatus200according to one or more examples. Apparatus200includes a circuit206(which circuit206may be an inverter) which may efficiently drive a load202(e.g., a multi-phase motor) while limiting dV/dt at a terminal204of load202. Circuit206may, additionally or alternatively, limit di/dt in circuit206(e.g., at a first switch214and a second switch216) and/or in load202.

In the present disclosure, elements of some drawings or apparatuses may be the same as, or substantially similar to, elements of other drawings or other apparatuses. Thus, a reference number having the same last two digits as a corresponding reference number in another drawing, may indicate that elements referenced by the respective reference numbers are substantially the same, absent explicit description to the contrary. As a non-limiting example, first switch214ofFIG.2may be the same as, or substantially similar to first switch114ofFIG.1. Load202is optional in apparatus200. The optionality of load202and of terminal204(and the other illustrated terminals of load202) is illustrated by load202and terminal204(and the other terminals) being illustrated using dashed lines.

In addition to elements that are the same as, or substantially similar to elements of apparatus100ofFIG.1, apparatus200includes a first capacitor230and a second capacitor232. First switch214may be a SiC MOSFET234. First diode222may define part of first path236and second diode224may define part of second path238.

In one or more examples, first capacitor230may be coupled between supply line208and terminal212. Further, second capacitor232may be coupled between return line210and terminal212. First capacitor230or second capacitor232may be part of a passive filter, e.g., to limit dV/dt at terminals212,204, without limitation. First inductor218and second inductor220in combination with first capacitor230and second capacitor232may limit dV/dt at terminal212. First inductor218and second inductor220may limit di/dt at terminal212(e.g., as described above with regard to first inductor118and second inductor120) and, as indicated, may also (in combination with first capacitor230and second capacitor232) limit dV/dt at terminal212.

First diode222, acting as a clamping, flyback or freewheeling diode, may provide first path236for a first decay current. Likewise, second diode224, acting as a clamping, flyback or freewheeling diode, may provide a second path238for a second decay current. Additionally, first diode222may prevent current to flow from first internal node226to return line210. Similarly, second diode224may prevent current to flow from supply line208to second internal node228.

As a non-limiting example of contemplated operations of circuit206, circuit206may provide a sinusoidal current at terminal204, through terminal212of circuit206, into load202. While providing the sinusoidal current, there may be four transitions. Description is provided relative to each of the four transitions.

Before a first transition the load current may flow from load202into circuit206at terminal212. Before the first transition, second switch216may be closed, and first switch214may be open. Before the first transition, the voltage at terminal212may be the same as the voltage at return line210, second capacitor232may be fully discharged and first capacitor230may be charged to have a potential thereacross equal to the voltage of supply line208, less the voltage of return line210, which for case of understanding will be assumed to be ground, without limitation. The load current may flow through second inductor220and second switch216.

At the first transition, second switch216may open and, after an optional dead time, first switch214may close. Current from second inductor220may be diverted from second switch216into second diode224, which second diode224may become forward biased and may clamp the drain voltage of second switch216at the voltage of supply line208. Initially, the current flowing through second inductor220is the same as the current flowing from load202, and thus no current is initially available to charge second capacitor232, and discharge first capacitor230. Additionally, initially second diode224clamps the voltage at second internal node228to be roughly equal to the voltage of supply line208, while the voltage at terminal212remains at the voltage of return line210due to first and second capacitors230,232, which voltage condition begins to discharge second inductor220.

As second inductor220begins to discharge, some of the load current may begin to discharge first capacitor230and charge second capacitor232, and as a result the voltage at terminal212slowly rises. After the voltage at terminal212has reached the potential of supply line208, a small overshoot of the voltage at terminal212above the voltage of supply line208may occur because of resonance between the parallel operation of first capacitor230and second capacitor232in combination with first inductor218and second inductor220. The overshoot is limited by properly sizing first and second inductors218and220, as well as first and second capacitors230and232so as to protect components of circuit206and/or load202. Proper sizing is done in accordance with resonant circuit design known to those skilled in the art.

Additionally or alternatively, first inductor218is charged through the body diode of first switch214being forward biased to carry the load current, due to the overshoot. When first switch214is closed, initially, the current in first inductor218is diverted from first switch214body diode to the first switch214channel internally to first switch214.

FIG.7includes graphs700illustrating voltages and currents at various points in a circuit (e.g., circuit206ofFIG.2), according to one or more examples. Graphs700include a graph702of a voltage704at a terminal (e.g., terminal212ofFIG.2) over time. Graphs700include a graph706of a current708in a first switch (e.g., first switch214ofFIG.2) and a first inductor (e.g., first inductor218ofFIG.2) over time, where the current rises slowly (slow di/dt) from an initial current after the first transition to a final current. Graphs700include a graph710of a current712in a second switch (e.g., second switch216ofFIG.2) over time, which was initially carrying the load current, and drops rapidly to zero when second switch216is opened. Graphs700include a graph714of a current716in a second diode (e.g., second diode224ofFIG.2) over time, which initially carries the load current and decays over time as second inductor220discharges. The first transition may occur during a first time duration 718.

Returning to the description ofFIG.2and the transitions, before a second transition the load current may flow from load202into circuit206at terminal212. Before the first transition, second switch216may be open, and first switch214may be closed. Before the second transition, the voltage at terminal204may be approximately the same as the voltage at supply line208, and thus first capacitor230is fully discharged and second capacitor232is fully charged. The load current may flow through first inductor218.

At the second transition, first switch214may be opened, and, after an optional dead time, second switch216may closed. When first switch214is opened, load current continues to flow through first inductor218and the body diode of first switch214. When second switch216is closed, first inductor218is carrying almost all the load current while second inductor220and second diode224may carry some residual current. The amount of residual current depends on the duration of the control signals alternately closing and opening first switch214and second switch216, which control signals may be determined by a modulator. After second switch216is closed, the voltage at second internal node228is approximately the voltage of return line210, which begins to charge second inductor220. The voltage at terminal212is constrained to change slowly due first and second capacitors230,232and the rate of change of current through second inductor220.

A portion of the load current discharges second capacitor232and charges first capacitor230. The voltage at terminal212transitions from high to low. This transition is slowed down as the second inductor220charges up to the full load current. The current of second inductor220primarily flows into the second switch216after the second switch216has been fully closed, and, therefore, the change of current of second inductor220(di/dt) results in reduced transition losses.

For example,FIG.8illustrates a graph800illustrating a drain-to-source voltage802of a second switch (e.g., second switch216ofFIG.2) and a current804through the second switch (e.g., second switch216), according to one or more examples. The small “bump” in current804is due to damping resistors in series with a first capacitor (e.g., first capacitor230ofFIG.2) and a second capacitor (e.g., second capacitor232ofFIG.2) respectively. The damping resistors are optional, and are not illustrated inFIG.2. The damping resistors, if supplied, serve to reduce the oscillations due to the resonances between first and second inductors218,220and first and second capacitors230,232.

Returning to the description ofFIG.2, circuit206(including first inductor218, second inductor220, first capacitor230, and second capacitor232) limit dV/dt at terminals212,204and, at the same time, circuit206limits di/dt of second switch216during the second transition, and further limits the current through second switch216to be primarily after the second switch216has closed.

Before a third transition the load current may flow from circuit206into load202at terminal204. Before the third transition, second switch216may be closed, and first switch214may be open. Before the third transition, the voltage at terminal204may be the same as the voltage at return line210. The load current may flow through second inductor220.

At the third transition, second switch216may open and, after an optional dead time, first switch214may close. When second switch216is opened, current will initially continue to flow through second inductor220through the body diode of second switch216. When first switch214is closed, because of the effect of first inductor218, the current change (di/dt) of the first inductor218and, as a result of the first switch214, will be slow. Slowing di/dt of the first switch214may reduce transition losses. At the same time first inductor218will have voltage at terminals of first inductor218to be charged; which means voltage at terminals212,204may remain low for the time needed first inductor218to be charged, in cooperation with first and second capacitors230,232. This also slows down the dV/dt at terminal204.

The increasing voltage at terminals212,204will now apply a voltage to second inductor220in the direction to discharge second inductor220. The current into second switch216and second inductor220will then decrease until second inductor220is fully discharged and the body diode of second switch216stops conducting.

Before a fourth transition the load current may flow from circuit206into load202at terminal204. Before the fourth transition, second switch216may be open, and first switch214may be closed. Before the second transition, the voltage at terminal204may be the same as the voltage at supply line208. The load current may flow through first inductor218.

At the fourth transition, first switch214may be opened, and, after an optional dead time, second switch216may closed. The inductance of the load202may then force the load current to continue to flow into some other path, i.e., other than through first switch214. This path is provided by first diode222, first inductor218, first capacitor230, and second capacitor232. In the meanwhile, first inductor218may be discharged and second inductor220may be charged.

The voltage at terminals212,204will not change very quickly (e.g., a limit to dV/dt), because of the effect of first and second capacitors230,232and the discharge and charge times of first and second inductors218,220, respectively.

In the fourth transition, first switch214may stop conducting at the time it is opened; as a result the current into first inductor218follow a different path through first diode222.

For example,FIG.9includes graphs900illustrating voltages and currents at various points in a circuit (e.g., circuit206ofFIG.2), according to one or more examples of the fourth transition. Graphs900include a graph902of a voltage904at a terminal (e.g., terminals212,204ofFIG.2) over time. Graphs900include a graph906of a current908in a first switch (e.g., first switch214ofFIG.2) over time. Graphs900include a graph910of a current912in a second switch (e.g., second switch216ofFIG.2) over time. Graphs900include a graph914of a current916in a first inductor (e.g., first inductor218ofFIG.2) over time. Graphs900include a graph918of a current920in a second inductor (e.g., second inductor220ofFIG.2) over time. Graphs900include a graph922of a current924in a first diode (e.g., first diode222ofFIG.2).

Just before transition time930, the voltage at terminal212is approximately equal to the voltage of supply line208. After transition time930, current flows to charge first capacitor230and discharge capacitor232, which occurs with overshoot, as seen in graph902. First switch214is opened, and as a result the current through first switch214drops to zero, as seen in graph906, however the current first inductor218begins to fall, as seen in graph914, i.e., first inductor begins to discharge. The current for first inductor218is provided by first diode222as seen in graph922. The overshoot seen in graph902begins charging second inductor220, as seen in graph918, and the current through second switch216begins to rise, as seen in graph910, it being understood that in this example current flow is shown as negative due to the polarity of the current flow.

In one non-limiting example, the inductance of the load202is more than 100 times greater than the combined inductances of the first and second inductors218,220. In another non-limiting example, the inductance of the load202is more than 1,000 times greater than the combined inductances of the first and second inductors218,220.

FIG.3is a functional block diagram illustrating an apparatus300according to one or more examples. Apparatus300includes a circuit306(which circuit306may be an inverter) which may efficiently drive a load302(e.g., a multi-phase motor) while limiting dV/dt at multiple terminals of load302. Circuit306may, additionally or alternatively, limit di/dt in circuit306(e.g., at a first switch314and a second switch316) and/or in load302.

In addition to elements that are the same as, or substantially similar to elements of apparatus100ofFIG.1or apparatus200ofFIG.2, apparatus300includes a third switch342coupled between supply line308and a second terminal340. Second terminal340may for electrically coupling to a second terminal358. Apparatus300may include a fourth switch344coupled between return line310and second terminal340. Apparatus300may include a third inductor346coupled between third switch342and second terminal340. Apparatus300may include a fourth inductor348coupled between fourth switch344and second terminal340. Apparatus300may include a third diode350coupled between return line310and an internal node354of third switch342and third inductor346. Apparatus300may include a fourth diode352coupled between supply line308and an internal node356of fourth switch344and fourth inductor348. Apparatus300may include a third capacitor360coupled between supply line308and second terminal340. Apparatus300may include a fourth capacitor362coupled between return line310and second terminal340. As first switch314and second switch316are to alternately electrically couple first terminal312to supply line308and return line310respectively; third switch342and fourth switch344may alternately electrically couple second terminal340to supply line308and return line310respectively.

Apparatus300may include a fifth switch372coupled between supply line308and a third terminal370. Third terminal370may be for electrical coupling to a third terminal392. Apparatus300may include a sixth switch374coupled between return line310and third terminal370. Apparatus300may include a fifth inductor376coupled between fifth switch372and third terminal370. Apparatus300may include a sixth inductor378coupled between sixth switch374and third terminal370. Apparatus300may include a fifth diode380coupled between return line310and an internal node384of third switch342and fifth inductor376. Apparatus300may include a sixth diode382coupled between supply line308and an internal node386of sixth switch374and sixth inductor378. Apparatus300may include a fifth capacitor388coupled between supply line308and third terminal370. Apparatus300may include a sixth capacitor390coupled between return line310and third terminal370. As first switch314and second switch316are to alternately electrically couple first terminal312to supply line308and return line310respectively; fifth switch372and sixth switch374may alternately electrically couple third terminal370to supply line308and return line310respectively.

Circuit306may drive load302(e.g., three-phase electrical motor (e.g., multi-phase motor, without limitation)) by providing drive signals at each of first terminal304, second terminal358, and third terminal392. Circuit306may limit dV/dt at each of first terminal304, second terminal358, and third terminal392.

FIG.4is a functional block diagram illustrating an apparatus400according to one or more examples. Apparatus400includes a circuit406(which circuit406may be an inverter) which may efficiently drive a load402(e.g., a multi-phase motor) while limiting dV/dt at a first terminal404of load402. Circuit406may, additionally or alternatively, limit di/dt in circuit406(e.g., at a first switch414and a second switch416) and/or in load402.

In addition to elements that are the same as, or substantially similar to elements of apparatus100ofFIG.1, apparatus200ofFIG.2, or apparatus300ofFIG.3, includes a modulator464, a first gate driver466, and a second gate driver468.

Modulator464may provide a first control signal for first switch414and a second control signal for second switch416. As a non-limiting example, modulator464may be a pulse-width modulator. Modulator464may provide the first control signal in phase opposition to the second control signal, with an optional dead time. For example, the first control signal may be high while the second control signal is low and the first control signal may be low while the second control signal is high. The first control signal may be functionally isolated from the second control signal. The functional isolation between the first control signal and the second control signal may be higher than the voltage difference between first internal node426and return line410.

First gate driver466may generate a first gate-control signal responsive to the first control signal. The first gate-control signal may be a first square wave which may exhibit voltages suitable to close and open first switch414. First gate driver466includes a grounding reference (not labeled inFIG.4) to reference first gate driver466to first internal node426, so as to supply the gate voltage referenced to the source of first switch414.

Second gate driver468may generate a second gate-control signal responsive to the second control signal. The second gate-control signal may be a second square wave (which second square wave may be the phase opposite the first square wave) which exhibit voltages suitable to close and open second switch416. The first gate-control signal and the second gate-control signal may be such that the first switch414and the second switch416are not closed at the same time. Second gate driver468includes a grounding reference (not labeled inFIG.4) to reference second gate driver468to return line410, so as to supply the gate voltage referenced to the source of second switch416.

Circuit406may include additional elements, e.g., passive elements (not illustrated inFIG.4) (e.g., between first gate driver466and first switch414and between second gate driver468and second switch416), to adjust the voltage of the first gate-control signal such that the first gate-control signal is suitable to close and open first switch414or to adjust a voltage of the second gate-control signal such that the second gate-control signal is suitable to close and open second switch416.

FIG.5is a functional block diagram illustrating a system500according to one or more examples. System500includes a circuit506(which circuit506may be an inverter) which may efficiently drive a load502(e.g., a motor) while limiting dV/dt at a first terminal504of load502. Circuit506may, additionally or alternatively, limit di/dt in circuit506(e.g., at a first switch514and a second switch516) and/or in load502.

System500may include load502(which load502may be a motor). System500may include circuit506coupled between a supply line508, a return line510, and a terminal512. Circuit506may provide an oscillating signal to load502at terminal512. Circuit506may include first switch514to couple supply line508with terminal512. Circuit506may include second switch516to couple return line510with terminal512. Circuit506may include a first inductor518coupled between first switch514and terminal512. Circuit506may include a second inductor520coupled between second switch516and terminal512. Circuit506may include a first diode522coupled between return line510and an internal node526of first switch514and first inductor518. Circuit506may include a second diode524coupled between supply line508and an internal node528of second switch516and second inductor520.

FIG.6is a flowchart of a method600, according to one or more examples. At least a portion of method600may be performed, in some examples, by a device or system, such as apparatus100ofFIG.1, apparatus200ofFIG.2, apparatus300ofFIG.3, apparatus400ofFIG.4, system500ofFIG.5, or another device or system. Although illustrated as discrete blocks, various blocks may be divided into additional blocks, combined into fewer blocks, or eliminated, depending on the desired implementation.

At operation602, a terminal may be alternately coupled to a supply line and to a return line via a first switch between the supply line and the terminal and via a second switch between the return line and the terminal.

At operation604, a change of a first electrical current may be resisted at a first inductor between the first switch and the terminal. As a non-limiting example, the first electrical current may be through a first inductor e.g., first inductor118ofFIG.1, or first inductor218ofFIG.2.

At operation606, a change of a second electrical current may be resisted at a second inductor between the second switch and the terminal. As a non-limiting example, the second electrical current may be through a second inductor e.g., second inductor120ofFIG.1, or second inductor220ofFIG.2.

At operation608, a first path may be provided for a first decay current for the first inductor (and the second inductor). As a non-limiting example, the first path may be between the return line and an internal node of the first switch and the first inductor and through a first diode.

At operation610, a second path may be provided for a second decay current for the second inductor (and the first inductor). As a non-limiting example, the second path may be between an internal node of the second switch and the second inductor and the supply line through a second diode.

Modifications, additions, or omissions may be made to method600without departing from the scope of the present disclosure. For example, the operations of method600may be implemented in differing order. Furthermore, the outlined operations and actions are only provided as examples, and some of the operations and actions may be optional, combined into fewer operations and actions, or expanded into additional operations and actions without detracting from the essence of the disclosed example.

As used herein, the term “substantially” in reference to a given parameter, property, or condition means and includes to a degree that one skilled in the art would understand that the given parameter, property, or condition is met with a small degree of variance, such as within acceptable manufacturing tolerances. For example, a parameter that is substantially met may be at least about 90% met, at least about 95% met, or even at least about 99% met.

As used in the present disclosure, the terms “module” or “component” may refer to specific hardware implementations may perform the actions of the module or component or software objects or software routines that may be stored on or executed by general purpose hardware (e.g., computer-readable media, processing devices, without limitation) of the computing system. In one or more examples, the different components, modules, engines, and services described in the present disclosure may be implemented as objects or processes that execute on the computing system (e.g., as separate threads, without limitation). While some of the system and methods described in the present disclosure are generally described as being implemented in software (stored on or executed by general purpose hardware), specific hardware implementations or a combination of software and specific hardware implementations are also possible and contemplated.

As used in the present disclosure, the term “combination” with reference to a plurality of elements may include a combination of all the elements or any of various different sub-combinations of some of the elements. For example, the phrase “A, B, C, D, or combinations thereof” may refer to any one of A, B, C, or D; the combination of each of A, B, C, and D; and any sub-combination of A, B, C, or D such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

Terms used in the present disclosure and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as “open” terms (e.g., the term “including” should be interpreted as “including, but not limited to,” the term “having” should be interpreted as “having at least,” the term “includes” should be interpreted as “includes, but is not limited to,” without limitation). As used herein, “each” means “some or a totality.” As used herein, “each and every” means “a totality.”

Additionally, if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases “at least one” and “one or more” to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim recitation to examples containing only one such recitation, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” or “an” means “at least one” or “one or more”); the same holds true for the use of definite articles used to introduce claim recitations.

In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the bare recitation of “two recitations,” without other modifiers, means at least two recitations, or two or more recitations). Furthermore, in those instances where a convention analogous to “at least one of A, B, and C, without limitation” or “one or more of A, B, and C, without limitation.” is used, in general such a construction is intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, without limitation.

Further, any disjunctive word or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms. For example, the phrase “A or B” should be understood to include the possibilities of “A” or “B” or “A and B.”

Additional non-limiting examples of the disclosure may include:

Example 1: An apparatus comprising: a circuit coupled between a supply line, a return line, and a terminal, the circuit to provide an oscillating signal to the terminal, the circuit comprising: a first switch to couple the supply line with the terminal; a second switch to couple the return line with the terminal; a first inductor coupled between the first switch and the terminal; a second inductor coupled between the second switch and the terminal; a first diode coupled between the return line and an internal node of the first switch and the first inductor; and a second diode coupled between the supply line and an internal node of the second switch and the second inductor.

Example 2: The apparatus according to Example 1, wherein the first switch to couple the supply line with the terminal responsive to a signal from a modulator.

Example 3: The apparatus according to any of Examples 1 and 2, wherein the signal is a first signal and wherein the second switch to couple the return line with the terminal responsive to a second signal from the modulator.

Example 4: The apparatus according to any of Examples 1 through 3, comprising: a first capacitor coupled between the supply line and the terminal; and a second capacitor coupled between the return line and the terminal.

Example 5: The apparatus according to any of Examples 1 through 4, wherein the first switch comprises a silicon carbide metal-oxide semiconductor field effect transistor.

Example 6: The apparatus according to any of Examples 1 through 5, wherein the first switch and the second switch are to alternately couple the terminal to the supply line and the return line respectively.

Example 7: The apparatus according to any of Examples 1 through 6, wherein the first diode to provide a first path for a first decay current for the first inductor, and wherein the second diode to provide a second path for a second decay current for the second inductor.

Example 8: The apparatus according to any of Examples 1 through 7, wherein the first diode to prevent current to flow from the internal node of the first switch and the first inductor to the return line, and wherein the second diode to prevent current to flow from the supply line to the internal node of the second switch and the second inductor.

Example 9: The apparatus according to any of Examples 1 through 8, wherein the circuit is a first circuit, wherein the terminal is a first terminal, wherein the oscillating signal is a first oscillating signal, and wherein the apparatus comprises: a second circuit coupled between the supply line, the return line, and a second terminal, the second circuit to provide a second oscillating signal to the second terminal, the second circuit comprising: a third switch to couple the supply line with the second terminal; a fourth switch to couple the return line with the second terminal; a third inductor coupled between the third switch and the second terminal; a fourth inductor coupled between the fourth switch and the second terminal; a third diode coupled between the return line and an internal node of the third switch and the third inductor; and a fourth diode coupled between the supply line and an internal node of the fourth switch and the fourth inductor.

Example 10: The apparatus according to any of Examples 1 through 9, comprising: a first capacitor coupled between the supply line and the first terminal; a second capacitor coupled between the return line and the first terminal; a third capacitor coupled between the supply line and the second terminal; and a fourth capacitor coupled between the return line and the second terminal.

Example 11: The apparatus according to any of Examples 1 through 10, wherein the first switch and the second switch are to alternately couple the first terminal to the supply line and the return line respectively and wherein the third switch and the fourth switch are to alternately couple the second terminal to the supply line and the return line respectively.

Example 12: The apparatus according to any of Examples 1 through 11, comprising: a third circuit coupled between the supply line, the return line, and a third terminal, the third circuit to provide a third oscillating signal to the third terminal, the third circuit comprising: a fifth switch to couple the supply line with the third terminal; a sixth switch to couple the return line with the third terminal; a fifth inductor coupled between the fifth switch and the third terminal; a sixth inductor coupled between the sixth switch and the third terminal; a fifth diode coupled between the return line and an internal node of the third switch and the fifth inductor; and a sixth diode coupled between the supply line and an internal node of the sixth switch and the sixth inductor.

Example 13: The apparatus according to any of Examples 1 through 12, wherein the first switch and the second switch are to alternately couple the first terminal to the supply line and the return line respectively, wherein the third switch and the fourth switch are to alternately couple the second terminal to the supply line and the return line respectively, and wherein the fifth switch and the sixth switch are to alternately couple the third terminal to the supply line and the return line respectively.

Example 14: The apparatus according to any of Examples 1 through 13, wherein the first switch to couple the supply line with the first terminal responsive to a first signal from a modulator, wherein the second switch to couple the return line with the first terminal responsive to a second signal from the modulator, wherein the third switch to couple the supply line with the second terminal responsive to a third signal from the modulator, and wherein the fourth switch to couple the return line with the second terminal responsive to a fourth signal from the modulator.

Example 15: The apparatus according to any of Examples 1 through 14, comprising a modulator to provide a first control signal for the first switch and a second control signal for the second switch.

Example 16: The apparatus according to any of Examples 1 through 15, comprising a first gate driver coupled between the modulator and the first switch and a second gate driver coupled between the modulator and the second switch.

Example 17: An apparatus comprising: an inverter for a load, the inverter comprising: a terminal to be coupled to the load; a supply line; a return line; a first switch; a second switch; a first inductor; a second inductor; a first diode; and a second diode, wherein: the first switch is coupled between the supply line and the terminal; the second switch is coupled between the return line and the terminal; the first inductor is coupled between the first switch and the terminal; the second inductor is coupled between the second switch and the terminal; the first diode is coupled between the return line and an internal node of the first switch and the first inductor; and the second diode is coupled between the supply line and an internal node of the second switch and the second inductor.

Example 18: The apparatus according to Example 17, wherein the first switch comprises a silicon carbide metal-oxide semiconductor field effect transistor.

Example 19: The apparatus according to any of Examples 17 and 18, wherein an inductance of the load is greater than an inductance of the first inductor and an inductance of the second inductor.

Example 20: The apparatus according to any of Examples 17 through 19, wherein the load comprises a motor.

Example 21: A method, comprising: alternately coupling a terminal to a supply line and to a return line via a first switch between the supply line and the terminal and via a second switch between the return line and the terminal; resisting change of a first electrical current at a first inductor between the first switch and the terminal; resisting change of a second electrical current at a second inductor between the second switch and the terminal; providing a first path for a first decay current between the return line and an internal node of the first switch and the first inductor through a first diode; and providing a second path for a second decay current between an internal node of the second switch and the second inductor and the supply line through a second diode.

Example 22: A system, comprising: a load; a circuit coupled between a supply line, a return line, and a terminal, the circuit to provide an oscillating signal to a motor at the terminal, the circuit comprising: a first switch to couple the supply line with the terminal; a second switch to couple the return line with the terminal; a first inductor coupled between the first switch and the terminal; a second inductor coupled between the second switch and the terminal; a first diode coupled between the return line and an internal node of the first switch and the first inductor; and a second diode coupled between the supply line and an internal node of the second switch and the second inductor.

While the present disclosure has been with respect to certain illustrated examples, those of ordinary skill in the art will recognize and appreciate that the present invention is not so limited. Rather, many additions, deletions, and modifications to the illustrated and described examples may be made without departing from the scope of the invention as hereinafter claimed along with their legal equivalents. In addition, features from one example may be combined with features of another example while still being encompassed within the scope of the invention as contemplated by the inventor.