Patent ID: 12230203

DETAILED DESCRIPTION

Exemplary aspects (embodiments) to embody the present invention are described below in greater detail with reference to the accompanying drawings. The contents described in the embodiments below are not intended to limit the present disclosure. Components described below include components easily conceivable by those skilled in the art and components substantially identical therewith. Furthermore, the components described below may be appropriately combined. What is disclosed herein is given by way of example only, and appropriate modifications made without departing from the spirit of the present disclosure and easily conceivable by those skilled in the art naturally fall within the scope of the present disclosure. To simplify the explanation, the drawings may possibly illustrate the width, the thickness, the shape, and other elements of each unit more schematically than the actual aspect. These elements, however, are given by way of example only and are not intended to limit interpretation of the present disclosure. In the present disclosure and the drawings, components similar to those previously described with reference to previous drawings are denoted by like reference numerals, and detailed explanation thereof may be appropriately omitted.

To describe an aspect where a first structure is disposed on a second structure in the present specification and the claims, the term “on” includes both of the following cases unless otherwise noted: a case where the first structure is disposed directly on the second structure in contact with the second structure, and a case where the first structure is disposed on the second structure with another structure interposed therebetween.

First Embodiment

FIG.1is a plan view of a display apparatus according to a first embodiment. A display apparatus1according to the present embodiment is an organic EL display apparatus with organic light-emitting diodes (OLEDs) serving as self-light-emitting elements. As illustrated inFIG.1, the display apparatus1includes an array substrate2, a plurality of pixels PX, a scanning line drive circuit12, a signal line drive circuit13, a light emission control circuit14, and a drive integrated circuit (IC)210.

The array substrate2is a drive circuit substrate that drives the pixels PX and is also called a backplane or an active matrix substrate. The array substrate2is composed of a substrate21serving as a base and includes a plurality of transistors, a plurality of capacitances, various kinds of wiring, and other components on the substrate21. A wiring substrate (e.g., flexible printed circuits (FPC)) or the like, which is not specifically illustrated, may be coupled on the array substrate2to receive various control signals and electric power from an external control substrate.

In the following description, a first direction Dx is one direction in a plane parallel to the substrate21. A second direction Dy is one direction in the plane parallel to the substrate21and is orthogonal to the first direction Dx. The second direction Dy may intersect the first direction Dx without being orthogonal thereto. A third direction Dz is orthogonal to the first direction Dx and the second direction Dy and is the normal direction of the substrate21. “Plan view” indicates the positional relation viewed from the third direction Dz.

The scanning line drive circuit12is a drive circuit that supplies writing control signals SG to scanning lines (writing control scanning lines GL (refer toFIG.4)) in a display region AA to drive the pixels PX. The signal line drive circuit13is a drive circuit that supplies video signals VSG to signal lines (first video signal lines SL1and second video signal lines SL2(refer toFIG.4)) in the display region AA to drive the pixels PX. The light emission control circuit14is a drive circuit that supplies signals to scanning lines (first light emission control scanning lines PWL1and second light emission control scanning lines PWL2(refer toFIG.4)) in the display region AA to drive the pixels PX.

The drive IC210is a circuit that supplies control signals to the scanning line drive circuit12, the signal line drive circuit13, and the light emission control circuit14to control display of the pixels PX. At least part of the scanning line drive circuit12, the signal line drive circuit13, and the light emission control circuit14may be formed integrally with the drive IC210. The drive IC210is provided on the array substrate2. The configuration is not limited thereto, and the drive IC210may be provided to the wiring substrate coupled to the array substrate2.

The array substrate2has the display region AA and a peripheral region GA. The display region AA is provided with the pixels PX. The pixels PX are arrayed in a matrix (row-column configuration) in the display region AA. The peripheral region GA is a region outside the display region AA and is not provided with the pixels PX. The peripheral region GA is provided with the scanning line drive circuit12, the signal line drive circuit13, the light emission control circuit14, and the drive IC210. The scanning line drive circuit12and the light emission control circuit14are provided in a region extending along the second direction Dy in the peripheral region GA. The signal line drive circuit13and the drive IC210are provided in a region extending along the first direction Dx in the peripheral region GA. More specifically, the scanning line drive circuit12is provided along the left side of the display region AA, and the light emission control circuit14is provided along the right side of the display region AA with respect to the display region AA inFIG.1. The signal line drive circuit13and the drive IC210are provided along the lower side of the display region AA. The scanning line drive circuit12and the light emission control circuit14may be provided in a region along the same side of the peripheral region GA.

The following describes an example where the display region AA is divided into four parts of a first partial display region AAs1, a second partial display region AAs2, a third partial display region AAs3, and a fourth partial display region AAs4(refer toFIG.5), and the display apparatus1performs the display operation on each of the partial display regions.

To simplify the explanation, the display region AA according to the present embodiment has a rectangular shape, and the peripheral region GA has a rectangular frame shape surrounding the display region AA. The shapes are not limited thereto, and the display region AA may have a polygonal shape or an irregular shape with cutouts (notches) or curved portions in part of the outer periphery. The peripheral region GA may also have various different shapes corresponding to the shape of the display region AA.

FIG.2is a plan view of an example of the pixel of the display apparatus according to the first embodiment. As illustrated inFIG.2, the pixel PX includes a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3each include an organic light-emitting diode as a light-emitting element100(refer toFIG.4). In the following description, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3are simply referred to as sub-pixels SPX when they need not be distinguished from each other.

The first sub-pixel SPX1displays red (R), for example. The second sub-pixel SPX2displays green (G), for example. The third sub-pixel SPX3displays blue (B), for example. The first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3are adjacently disposed in the first direction Dx. The configuration is not limited thereto, and the pixel PX may have other arrangements. For example, the first sub-pixel SPX1and the second sub-pixel SPX2may be adjacently disposed in the second direction Dy, and one third sub-pixel SPX3may be disposed adjacently to the first sub-pixel SPX1and the second sub-pixel SPX2adjacently disposed in the second direction Dy. The pixel PX may be configured in what is called the PenTile arrangement. The pixel PX is not necessarily composed of three sub-pixels SPX and may be composed of four or more sub-pixels SPX.

The following describes gradation control performed by the display apparatus1.FIG.3is a block diagram of an exemplary configuration of the display apparatus according to the first embodiment. As illustrated inFIG.3, the display apparatus1includes a pixel circuit50and a drive signal controller200that controls the drive of the pixel circuit50. The pixel circuit50is a circuit that supplies drive signals (electric current) to the light-emitting element100to drive the light-emitting element100. While one pixel circuit50(light-emitting element100) is schematically illustrated inFIG.3, a plurality of pixel circuits50and a plurality of light-emitting elements100are provided to the respective sub-pixels SPX (refer toFIG.2) and are arrayed in a matrix (row-column configuration) in the display region AA.

The drive signal controller200includes a gradation value analyzer201, a drive gradation generator202, and a timing signal generator203. The gradation value analyzer201is a circuit that calculates a gradation value (a gray scale value, a gray level value) for each pixel PX (sub-pixel SPX) based on image signals input from an external control circuit. The gradation value may be hereinafter referred to as a target luminance level.

The drive gradation generator202is a circuit that generates first video signals VSG1and second video signals VSG2based on the target luminance level received from the gradation value analyzer201. The signal line drive circuit13of the array substrate2outputs the first video signals VSG1and the second video signals VSG2supplied from the drive gradation generator202to the pixel circuits50to drive the pixels PX at the target luminance level. In the following description, the first video signal VSG1and the second video signal VSG2may be simply referred to as video signals VSG when they need not be distinguished from each other.

The timing signal generator203generates timing signals based on synchronization signals input from the external control circuit and the target luminance level received from the gradation value analyzer201. The scanning line drive circuit12and the light emission control circuit14output control signals (writing control signals SG and light emission control signals PG) to the pixel circuits50based on the timing signals (control signals) supplied from the timing signal generator203.

The first video signal VSG1and the second video signal VSG2have a predetermined signal potential to turn on the optical element100. The timing signal (control signal) supplied from the timing signal generator203includes information on the lighting period of the light-emitting element100by the light emission control circuit14. The display apparatus1can perform multi-gradation display by combining a system that expresses the gradation by controlling the value of an electric current supplied to the optical element100of each sub-pixel SPX (hereinafter referred to as a current drive system or an analog drive system) and a system that expresses the gradation by controlling the lighting time of the optical element100while keeping the value of an electric current supplied thereto constant (hereinafter referred to as a PWM drive system). The drive signal controller200may be formed integrally with the drive IC210or may be provided to the external control circuit.

FIG.4is a circuit diagram of an exemplary configuration of the pixel circuit. As illustrated inFIG.4, the pixel circuit50includes a first pixel circuit50aand a second pixel circuit50b. The first pixel circuit50aand the second pixel circuit50bare coupled to one light-emitting element100. In other words, the first pixel circuit50aand the second pixel circuit50bare provided to each of the sub-pixels SPX. The first pixel circuit50ais a circuit that drives the light-emitting element100by the current drive system. The first pixel circuit50acan also serve as a circuit that drives the light-emitting element100by the PWM drive system in part of a frame period for displaying an image of one screen. The second pixel circuit50bis a circuit that drives the light-emitting element100by the PWM drive system.

The first pixel circuit50aincludes a first light emission control transistor PWT1, a first writing transistor SST1, a first drive transistor DRT1, and a first coupling switching transistor CNT1. The gate of the first light emission control transistor PWT1is coupled to the first light emission control scanning line PWL1. One of the source and the drain of the first light emission control transistor PWT1is coupled to a power supply voltage VDD. The other of the source and the drain of the first light emission control transistor PWT1is coupled to the first drive transistor DRT1. When the first light emission control transistor PWT1is turned on (coupled state), the power supply voltage VDD is supplied to the first drive transistor DRT1.

The gate of the first writing transistor SST1is coupled to the writing control scanning line GL. The source or the drain of the first writing transistor SST1is coupled to the first video signal line SL1. The other of the source and the drain of the first writing transistor SST1is coupled to the gate of the first drive transistor DRT1. When the first writing transistor SST1is turned on (coupled state), the first video signal VSG1is supplied from the signal line drive circuit13to the gate of the first drive transistor DRT1. The ON state of the drive transistor DRT varies depending on the magnitude of the first video signal VSG1. For example, if the first video signal VSG1corresponds to a signal potential that achieves the maximum luminance of the light-emitting element100, the drive transistor DRT is substantially completely turned on according to the electric potential. As a result, an electric current (predetermined fixed potential) from the power supply voltage VDD passes through the drive transistor DRT substantially without any change and is supplied to the light-emitting element100. By contrast, if the first video signal VSG1corresponds to the lowest luminance of the light-emitting element100, that is, a signal potential that displays black, the drive transistor DRT is turned off, and the electric current from the power supply voltage VDD is not supplied to the light-emitting element100.

The first video signal VSG1can also have signal potentials between the maximum luminance and the lowest luminance. When the signal potential is supplied to the drive transistor DRT, the drive transistor DRT is turned on by the magnitude corresponding to the signal potential. As a result, the electric current from the power supply voltage VDD is supplied to the light-emitting element100only by the amount corresponding to the ON state of the drive transistor DRT.

The gate of the first coupling switching transistor CNT1is coupled to the second light emission control scanning line PWL2. One of the source and the drain of the first coupling switching transistor CNT1is coupled to the first drive transistor DRT1. The other of the source and the drain of the first coupling switching transistor CNT1is coupled to the light-emitting element100. In other words, the first coupling switching transistor CNT1is coupled between the first drive transistor DRT1and the light-emitting element100.

The writing control scanning line GL is coupled to the scanning line drive circuit12. The scanning line drive circuit12supplies the writing control signals SG to the writing control scanning line GL. The first light emission control scanning line PWL1and the second light emission control scanning line PWL2are coupled to the light emission control circuit14. The light emission control circuit14supplies first light emission control signals PG1and second light emission control signals PG2to the first light emission control scanning line PWL1and the second light emission control scanning line PWL2, respectively.

The transistors (the first light emission control transistor PWT1, the first writing transistor SST1, and the first drive transistor DRT1) included in the first pixel circuit50aare n-type thin-film transistors (TFTs). The first coupling switching transistor CNT1is a p-type TFT. When the electric potential of the first light emission control scanning line PWL1is turned to a high (H) level, and the electric potential of the second light emission control scanning line PWL2is turned to a low (L) level, the first coupling switching transistor CNT1is turned on (coupled state) in synchronization with the first light emission control transistor PWT1. Alternatively, when the electric potential of the first light emission control scanning line PWL1is turned to the L level, and the electric potential of the second light emission control scanning line PWL2is turned to the H level, the first coupling switching transistor CNT1is turned off (uncoupled state) in synchronization with the first light emission control transistor PWT1.

The first pixel circuit50aincludes holding capacitance Cs1. The holding capacitance Cs1is capacitance formed between the gate and the source of the first drive transistor DRT1.

The second pixel circuit50bincludes a second light emission control transistor PWT2, a second writing transistor SST2, a second drive transistor DRT2, and a second coupling switching transistor CNT2. The second pixel circuit50bhas a configuration similar to that of the first pixel circuit50a, and redundant explanation thereof is omitted. The gate of the second light emission control transistor PWT2is coupled to the second light emission control scanning line PWL2. When the second light emission control transistor PWT2is turned on (coupled state), the power supply voltage VDD is supplied to the second drive transistor DRT2.

The gate of the second writing transistor SST2is coupled to the writing control scanning line GL. In other words, the first writing transistor SST1and the second writing transistor SST2are coupled to the common writing control scanning line GL. When the second writing transistor SST2is turned on (coupled state), the second video signal VSG2is supplied from the signal line drive circuit13to the gate of the second drive transistor DRT2.

The gate of the second coupling switching transistor CNT2is coupled to the first light emission control scanning line PWL1. One of the source and the drain of the second coupling switching transistor CNT2is coupled to the second drive transistor DRT2. The other of the source and the drain of the second coupling switching transistor CNT2is coupled to the light-emitting element100. In other words, the second coupling switching transistor CNT2is coupled between the second drive transistor DRT2and the light-emitting element100.

The second pixel circuit50bincludes holding capacitance Cs2. The holding capacitance Cs2is capacitance formed between the gate and the source of the second drive transistor DRT2.

FIG.5is a timing chart for explaining an example of the operations performed by the display apparatus according to the first embodiment. WhileFIG.5illustrates the operation of driving the sub-pixels SPX in the first partial display region AAs1and the second partial display region AAs2, the sub-pixels SPX in the third partial display region AAs3to those in the last row are continuously driven. In the following description, the period for driving the sub-pixels SPX in the first row to those in the last row is referred to as a frame period.

As illustrated inFIG.5, a period t1is a video signal writing operation period for the first partial display region AAs1. Specifically, in the period t1, the electric potentials of the first light emission control scanning line PWL1and the second light emission control scanning line PWL2are turned to the L level, and the writing control scanning lines GL1, GL2, . . . , and GL270are turned to the H level by the control signals supplied from the scanning line drive circuit12and the light emission control circuit14.

As a result, the first light emission control transistor PWT1of the first pixel circuit50aand the second light emission control transistor PWT2of the second pixel circuit50bare turned off. The first writing transistor SST1of the first pixel circuit50aand the second writing transistor SST2of the second pixel circuit50bare turned on. In the period t1, the writing control scanning lines GL belonging to the first partial display region AAs1are sequentially scanned. The writing control scanning line GL1is the writing control scanning line GL1coupled to the sub-pixels SPX in the first row, and the writing control scanning line GL2is the writing control scanning line GL2coupled to the sub-pixels SPX in the second row. The first partial display region AAs1is the region including the writing control scanning lines GL1to GL270, for example.

In the period t1, a first video signal VSG1-1is input to the gate of the first drive transistor DRT1of the first pixel circuit50ain the sub-pixels SPX belonging to the writing control scanning line GL at the H level. In the same period, a second video signal VSG2-1is input to the gate of the second drive transistor DRT2of the second pixel circuit50b. The gate potential of the first drive transistor DRT1changes to the electric potential of the first video signal VSG1-1by the video signal writing operation in the period t1. The gate potential of the second drive transistor DRT2changes to the electric potential of the second video signal VSG2-1. As illustrated inFIG.5, the display based on the video signals following the period t1is performed by what is called a pulse width modulation system in both periods t1aand t1b(display drive by the pulse width modulation system is hereinafter referred to as the PWM drive system). The PWM drive system is a system that expresses the gradation of the light-emitting element100according to the length of the pulse width of the signals output from the light emission control circuit14to each of the light emission control scanning lines PWL. When the light-emitting element100is turned on by the PWM drive system, the brightness is preferably the maximum luminance of the light-emitting element100. Therefore, all the video signals input in the period t1according to the present embodiment are what is called signals (signal potentials) corresponding to the maximum luminance of the light-emitting element100. Thus, the gradation of the light-emitting element100is controlled by either the maximum luminance or a luminance of 0 in the period of the PWM drive system. In the following description, the video signal supplied in the display period by the PWM drive system may be referred to as a digital signal. In view of the fact that the pulse width modulation system defines the length of the lighting time of the light-emitting element100, the PWM drive system may be hereinafter referred to as a time division modulation system.

The periods t1aand t1bare light-emitting operation periods. Specifically, in the period t1a, the first light emission control scanning line PWL1is turned to the H level, and the second light emission control scanning line PWL2is turned to the L level by the control signals supplied from the scanning line drive circuit12and the light emission control circuit14. The writing control scanning lines GL1, GL2, . . . , and GL270in the first partial display region AAs1are turned to the L level.

As a result, the first light emission control transistor PWT1of the first pixel circuit50ais turned on, and the first writing transistor SST1is turned off. In addition, the first coupling switching transistor CNT1is turned on. The power supply voltage VDD is supplied to the first drive transistor DRT1via the first light emission control transistor PWT1. The first drive transistor DRT1supplies an electric current corresponding to the voltage between the gate and the source set in the period t1to the light-emitting element100. In other words, the first drive transistor DRT1is substantially completely turned on by the video signal, and the light-emitting element100emits light at the maximum luminance due to the potential difference between VDD and VSS.

By contrast, focusing on the light emission period, the period (pulse width) in which the first emission control transistor PWT1is turned on in the period t1ais set to a period for achieving a target luminance level of 12.5% with respect to the maximum lighting luminance. In the period t1a, no electric current flows from the second drive transistor DRT2to the light-emitting element100because the second light emission control transistor PWT2of the second pixel circuit50bis turned off. The voltage between the gate and the source of the second drive transistor DRT2is held by the holding capacitance Cs2. In the period t1a, fluctuations in voltage between the gate and the source of the second drive transistor DRT2due to the electric current from the first drive transistor DRT1is suppressed because the second coupling switching transistor CNT2of the second pixel circuit50bis turned off.

Subsequently, in the period t1b, the first light emission control scanning line PWL1is turned to the L level, and the second light emission control scanning line PWL2is turned to the H level by the control signals supplied from the scanning line drive circuit12and the light emission control circuit14. The writing control scanning lines GL1, GL2, . . . , and GL270in the first partial display region AAs1are maintained at the L level.

As a result, the second light emission control transistor PWT2of the second pixel circuit50bis turned on, and the second writing transistor SST2is turned off. In addition, the second coupling switching transistor CNT2is turned on. The power supply voltage VDD is supplied to the second drive transistor DRT2via the second light emission control transistor PWT2. The second drive transistor DRT2supplies an electric current corresponding to the voltage between the gate and the source set in the period t1to the light-emitting element100. In other words, the second drive transistor DRT2is substantially completely turned on by the digital signal, and the light-emitting element100emits light at the maximum luminance based on the potential difference between VDD and VSS.

By contrast, focusing on the light emission period, the period (pulse width) in which the second emission control transistor PWT2is turned on in the period t1bis set to a period for achieving a target luminance level of 50% with respect to the maximum lighting luminance. In other words, the period t1bis longer than the period t1a, and the period t1baccording to the present embodiment is four times the length of the period t1a. In the period t1b, no electric current flows from the first drive transistor DRT1to the light-emitting element100because the first light emission control transistor PWT1of the first pixel circuit50ais turned off. In the period t1b, fluctuations in voltage between the gate and the source of the first drive transistor DRT1due to the electric current from the second drive transistor DRT2is suppressed because the first coupling switching transistor CNT1of the first pixel circuit50ais turned off.

In both the periods t1aand t1bcorresponding to the light emission periods described above, the light-emitting element100is turned on at the maximum luminance. By contrast, the light emission period of the period t1ais shorter than that of the period1b. Therefore, the luminance of the light-emitting element100can be changed by switching on and off the light-emitting element100in each of the periods. More specifically, if the light-emitting element100is turned on at the maximum luminance in both of the periods t1aand t1b, a user of the display apparatus1visually recognizes that the light-emitting element100is turned on at the brightest luminance over the periods t1aand t1bdue to the integral effect of the human eye (the luminance at this time is referred to as luminance A).

By contrast, let us assume a case where the light-emitting element100is turned on only in the period t1bout of the periods t1aand t1b. In this case, if the light-emitting element100is turned on at the maximum luminance in the period t1b, the luminance is darker than the luminance A when viewed in the entire periods t1aand t1bdue to the integral effect in the time-axis direction, and the user visually recognizes that the light-emitting element100is turned on at luminance B darker than the luminance A.

Let us assume a case where the light-emitting element100is turned on only in the period t1aout of the periods t1aand t1b. In this case, if the light-emitting element100is turned on at the maximum luminance in the period t1a, the luminance is darker than the luminance B when viewed in the entire periods t1aand t1bdue to the integral effect in the time-axis direction, and the user visually recognizes that the light-emitting element100is turned on at luminance C darker than the luminance B. Thus, the time division modulation system changes the luminance according to the length of the lighting period of the light-emitting element100.

In a period t2to a period t3overlapping the periods t1aand t1b, the video signal writing operations for the second partial display region AAs2to the fourth partial display region AAs4are sequentially performed. In periods t2a, t2b, t5a, and t5b, the light-emitting operation for the second partial display region AAs2is performed in the same manner as in the first partial display region AAs1.

In a period t4, the video signal writing operation for the first partial display region AAs1is performed in the same manner as in the period t1. The gate potential of the first drive transistor DRT1changes to the electric potential of the first video signal VSG1-2by the video signal writing operation in the period t4. The gate potential of the second drive transistor DRT2changes to the electric potential of the second video signal VSG2-2.

Subsequently, in a period t4a, the first light emission control scanning line PWL1is turned to the L level, and the second light emission control scanning line PWL2is turned to the H level by the control signals supplied from the scanning line drive circuit12and the light emission control circuit14. The writing control scanning lines GL1, GL2, . . . , and GL270in the first partial display region AAs1are turned to the L level. The operations of the transistors of the second pixel circuit in the period t4aare the same as those in the period t1bdescribed above, and redundant explanation thereof is omitted.

As illustrated inFIG.5, the period t4ais a period for display by the PWM drive system in the display based on the video signals following the period t4. By contrast, a period t4bis a display period by analog gradation. In the display by analog gradation, the lighting period is fixed to a predetermined period, the pixel signal has an analog potential, the ON state of the gate of the drive transistor is adjusted corresponding to the analog potential, and the electric current flowing from the power supply voltage VDD to the light-emitting element100has the magnitude corresponding to the ON state of the gate. As a result, the luminance of the light-emitting element100is brightness corresponding to the analog potential of the pixel signal. More specifically, the brightness of the light-emitting element100based on the pixel signal with the analog potential has any brightness from a luminance of 0 to a predetermined luminance. In other words, if the period is the PWM drive system period, the light-emitting element emits light only at the maximum luminance or a luminance of 0 in the entire period. In the display period by analog gradation, however, the light-emitting element emits light at any luminance between a luminance of 0 and the maximum luminance by gradation expression with the analog potential. In the following description, display by analog gradation may be referred to as the analog drive system.

The pixel signal supplied to the pixel circuit in the display period by the analog drive system can be set to a value corresponding to what is called 0 to 255 gradations. Considering that the period for expressing the gradation based on the analog potential is 12.5% of the entire lighting period, the luminance expression by the pixel signal according to the present embodiment is approximately 0 to 32 gradations.

In the period t4a, the period (pulse width) in which the second emission control transistor PWT2is turned on is set to a period for achieving a target luminance level of 25% with respect to the maximum lighting luminance. In the period t4a, no electric current flows from the first drive transistor DRT1to the light-emitting element100because the first light emission control transistor PWT1of the first pixel circuit50ais turned off.

Subsequently, in the period t4b, the first light emission control scanning line PWL1is turned to the H level, and the second light emission control scanning line PWL2is turned to the L level by the control signals supplied from the scanning line drive circuit12and the light emission control circuit14. The writing control scanning lines GL1, GL2, . . . , and GL270in the first partial display region AAs1are maintained at the L level. The operations of the transistors of the first pixel circuit50ain the period t4bare the same as those in the period t1adescribed above, and redundant explanation thereof is omitted.

In the period t4b, the first drive transistor DRT1supplies an electric current (first drive current) corresponding to the first video signal VSG1-2serving as an analog signal to the light-emitting element100. The period (pulse width) in which the first emission control transistor PWT1is turned on is fixed to a period for achieving a target luminance level of 12.5% with respect to the maximum lighting luminance. The electric potential of the first video signal VSG1-2in the period t4bis set for each sub-pixel SPX by the drive signal controller200. In the period t4b, no electric current flows from the second drive transistor DRT2to the light-emitting element100because the second light emission control transistor PWT2of the second pixel circuit50bis turned off.

When the operations described above are completed in the second partial display region AAs2to the fourth partial display region AAs4, an image of one frame is displayed.

The drive signal controller200(refer toFIG.3) can control the luminance (gradation) of the light-emitting element100by the total of the light-emitting operation periods of the periods t1aand t1band the periods t4aand t4b. More specifically, 87.5% of the luminance of the optical element is achieved in the display period by the PWM drive system based on the video signals with the digital potential (the first video signal VSG1-1and the second video signals VSG2-1and VSG2-2). The remaining 12.5% of the luminance is achieved by the video signals with the analog potential (first video signal VSG1-2). The brightness of 12.5% of the luminance can be more finely set according to the analog potential. Therefore, significantly fine gradation expression can be achieved by combining the PWM drive system period and the analog drive system period.

In the example illustrated inFIG.5, an electric current flows to the light-emitting element100in the entire period of the periods t1aand t1band the periods t4aand t4bto display 100% of the luminance. The drive signal controller200(refer toFIG.3), however, controls turning on/off the lighting in the periods t1aand t1band the period t4a, thereby supplying a fixed current to the light-emitting element100for a period with the length corresponding to the video signal VSG. In addition, the drive signal controller200adjusts the electric current (first video signal VSG1-2) in the period t4b, thereby appropriately controlling the luminance (gradation).

FIG.6is a diagram for explaining an example of the combination of the current drive system and the PWM drive system for each display luminance level. As illustrated inFIG.6, in the range where the target luminance level is larger than 0% and equal to or smaller than 12.5%, the drive signal controller200turns on the first light emission control transistor PWT1in the period t4band supplies the electric current (first video signal VSG1-2) to the light-emitting element100to adjust the lighting luminance level. In other words, the drive signal controller200turns off the first light emission control transistor PWT1and the second light emission control transistor PWT2in the periods t1aand t1band the period t4a. In other words, the light-emitting element100is turned off in all the periods t1a, t1b, and t4a.

In the range where the target luminance level is larger than 12.5% and equal to or smaller than 25%, the drive signal controller200turns on the first light emission control transistor PWT1in the period t1aand supplies the electric current (first video signal VSG1-1) to the light-emitting element100for a period with the length corresponding to a target luminance level of 12.5%. The drive signal controller200turns on the first light emission control transistor PWT1in the period t4band supplies the electric current (first video signal VSG1-2) to the light-emitting element100to adjust the lighting luminance level in the range from 12.5% to 25%. In other words, the drive signal controller200turns off the first light emission control transistor PWT1and the second light emission control transistor PWT2in the period t1band the period t4a. In other words, the light-emitting element100is turned off in both the periods t1band t4a.

In the range where the target luminance level is larger than 25% and equal to or smaller than 37.5%, the drive signal controller200turns on the second light emission control transistor PWT2in the period t4aand supplies the electric current (second video signal VSG2-2) to the light-emitting element100for a period with the length corresponding to a target luminance level of 25%. The drive signal controller200turns on the first light emission control transistor PWT1in the period t4band supplies the electric current (first video signal VSG1-2) to the light-emitting element100to adjust the lighting luminance level in the range from 25% to 37.5%. In other words, the drive signal controller200turns off the first light emission control transistor PWT1and the second light emission control transistor PWT2in the period t1aand the period t1b. In other words, the light-emitting element100is turned off in both the periods t1aand t1b.

In the range where the target luminance level is larger than 37.5% and equal to or smaller than 50%, the drive signal controller200turns on the first light emission control transistor PWT1and the second light emission control transistor PWT2in the periods t1aand t4a, respectively, and supplies the electric current (the first video signal VSG1-1and the second video signal VSG2-2) to the light-emitting element100for a period with the length corresponding to a target luminance level of 12.5% and a period with the length corresponding to a target luminance level of 25%. The drive signal controller200turns on the first light emission control transistor PWT1in the period t4band supplies the electric current (first video signal VSG1-2) to the light-emitting element100to adjust the lighting luminance level in the range from 37.5% to 50%. In other words, the drive signal controller200turns off the first light emission control transistor PWT1and the second light emission control transistor PWT2in the period t1b. In other words, the light-emitting element100is turned off in the period t1b.

In the same manner as described above, the drive signal controller200combines the electric current (the first video signal VSG1-1and the second video signals VSG2-1and VSG2-2) and the electric current (the first video signal VSG1-2), thereby achieving display of the lighting luminance level.

As described above, the display apparatus1includes a plurality of light-emitting elements100, a first pixel circuit50aand a second pixel circuit50b, a first drive transistor DRT1, a second drive transistor DRT2, and a drive circuit (signal line drive circuit13). The light-emitting elements100are arrayed in the display region AA. The first pixel circuit50aand the second pixel circuit are coupled to each of the light-emitting elements100. The first drive transistor DRT1is provided to the first pixel circuit50aand supplies the first drive current (electric current corresponding to the first video signal VSG1-2) to the light-emitting element100. The second drive transistor DRT2is provided to the second pixel circuit50band supplies the second drive current (e.g., the electric current corresponding to the second video signal VSG2-2) to the light-emitting element100. The drive circuit supplies the video signal VSG to the first drive transistor DRT1and the second drive transistor DRT2.

In the display apparatus1, the first drive transistor DRT1provided to the first pixel circuit50asupplies the first drive current (electric current corresponding to the first video signal VSG1-2) set corresponding to the video signal VSG to the light-emitting element100. The second drive transistor DRT2provided to the second pixel circuit supplies the fixed second drive current (e.g., a fixed current corresponding to the second video signals VSG2-1and VSG2-2) to the light-emitting element100for a period (periods t1band t4a) with the length corresponding to the video signal VSG.

With this configuration, the display apparatus1can suitably perform gradation control by combining the PWM drive system that expresses the gradation by combining the periods t1a, t1b, and t4ahaving different light emission periods and the analog drive system that expresses the gradation by controlling the amount of electric current (first video signal VSG1-2) to the light-emitting element100in the period t4a.

In the display apparatus1, the light-emitting element100is driven by the first drive current in the range equal to or smaller than the maximum low gradation value defined by the maximum value of the first drive current (electric current corresponding to the first video signal VSG1-2) (e.g., the range equal to or smaller than a target luminance level of 12.5% inFIG.6). In the range on the high gradation side larger than the maximum gradation value defined by the maximum value of the first drive current (e.g., the range larger than a target luminance level of 12.5% inFIG.6), the light-emitting element100is driven by at least the second drive current (e.g., at least one or more of the electric currents corresponding to the first video signal VSG1-1and the second video signals VSG2-1and VSG2-2).

With this mechanism, the gradation control range can be made smaller than in a case where all the gradations are controlled by the current drive system. The current value of the PWM drive system according to the present embodiment is larger than that of the current drive system on the high gradation side. Therefore, the present embodiment can suppress changes in light emission chromaticity due to fluctuations in current value.

In the display apparatus1, the first drive transistor DRT1and the second drive transistor DRT2are supplied with the video signals VSG in a common writing period (e.g., the period t1). The first drive transistor DRT1and the second drive transistor DRT2supply the first drive current (electric current corresponding to the first video signal VSG1-2) and the second drive current (e.g., the electric current corresponding to the second video signals VSG2-1and VSG2-2) to the light-emitting element100in a time-division manner.

In the display apparatus1, two pixel circuits of the first pixel circuit50aand the second pixel circuit50bare provided for one light-emitting element100. With this configuration, the display apparatus1can perform the video signal writing operation on the first pixel circuit50aand the second pixel circuit50bin the same writing period (e.g., the period t1). Therefore, the display apparatus1can reduce the time required for the video signal writing operation compared with a case where multi-gradation display is performed by one pixel circuit.

The pixel circuit50and the driving method illustrated inFIGS.4to6are given by way of example only and can be appropriately modified. While the display apparatus1combines the three periods (pulse widths) t1a, t1b, and t2ahaving different lengths to implement the PWM drive system, the present embodiment is not limited thereto. The display apparatus1may combine two different periods (pulse widths) or four or more different periods (pulse widths), for example, to implement the PWM drive system.

As illustrated inFIG.5, the display period by the PWM drive system is longer in the first pixel circuit50athan in the second pixel circuit50b. Therefore, the holding capacitance Cs1may be larger than the holding capacitance Cs2.

Modifications of the First Embodiment

FIG.7is a circuit diagram of an exemplary configuration of the pixel circuit according to a modification of the first embodiment. In the following description, the same components as those described in the embodiment above are denoted by like reference numerals, and overlapping explanation thereof is omitted.

As illustrated inFIG.7, in the first pixel circuit according to the modification, the gate of the first coupling switching transistor CNT1is coupled to the first light emission control scanning line PWL1. In other words, the first coupling switching transistor CNT1is supplied with the same first light emission control signal PG1as that for the first light emission control transistor PWT1. The first coupling switching transistor CNT1and the first light emission control transistor PWT1are n-type TFTs. With this configuration, the first coupling switching transistor CNT1is controlled to be turned on and off in synchronization with the first light emission control transistor PWT1.

Also in the second pixel circuit50b, the gate of the second coupling switching transistor CNT2is coupled to the second light emission control scanning line PWL2. In other words, the second coupling switching transistor CNT2is supplied with the same second light emission control signal PG2as that for the second light emission control transistor PWT2. The second coupling switching transistor CNT2and the second light emission control transistor PWT2are n-type TFTs. With this configuration, the second coupling switching transistor CNT2is controlled to be turned on and off in synchronization with the second light emission control transistor PWT2.

Second Embodiment

FIG.8is a timing chart for explaining an example of the operations performed by the display apparatus according to a second embodiment.FIG.9is a diagram for explaining an example of the combination of the current drive system and the PWM drive system for each display luminance level of the display apparatus according to the second embodiment.FIG.10is an enlarged explanatory diagram schematically illustrating the range of target luminance levels of 0% to 12.8% inFIG.9.

In the range on the low gradation side, the display apparatus1according to the second embodiment drives the light-emitting element100by the PWM drive system that expresses the gradation by controlling the lighting time. In the range on the high gradation side, the display apparatus1drives the light-emitting element100by combining the PWM drive system and the current drive system that expresses the gradation by controlling the electric current (first video signals VSG1-1and VSG1-2).

As illustrated inFIG.8, the periods t1, t4, t7, and t10are the video signal writing operation periods for the first partial display region AAs1. In the period t1a, the second light emission control transistor PWT2of the second pixel circuit50bis turned on, and the second drive transistor DRT2supplies the electric current (second drive current) corresponding to the second video signals VSG2-1and VSG2-2to the light-emitting element100. In the period t1a, the period (pulse width) in which the second light emission control transistor PWT2is turned on is set to a period for achieving a target luminance level of 0.2% (second video signal VSG2-1) or 0.4% (second video signal VSG2-2), for example, with respect to the maximum lighting luminance. The second video signal VSG2-1and the second video signal VSG2-2are alternately switched and each turn on the light-emitting element100once every two times. As a result, their contribution to the display luminance is 0.1% and 0.2%, respectively. This control system can increase the number of gradations because the pulses with low luminance do not cause flicker even if the turning-on/-off frequency is small.

In the period t1b, the first light emission control transistor PWT1of the first pixel circuit50ais turned on, and the first drive transistor DRT1supplies the electric current (first drive current) corresponding to the first video signal VSG1-1to the light-emitting element100. In the period t1b, the period (pulse width) in which the first light emission control transistor PWT1is turned on is set to a period for achieving a luminance level of approximately one half of the luminance range allocated to the current drive system. More specifically, the pulses in the periods t1band t7bare set to 43.6%. As a result, the total of the pulses in the two periods t1band t7bis 87.2% (=100%−12.8%). In contrast to the period t1a, the lighting is controlled two separate times because the luminance is high, and flicker is more likely to occur.

In the period t4a, the first light emission control transistor PWT1of the first pixel circuit50ais turned on, and the first drive transistor DRT1supplies the electric current (second drive current) corresponding to the first video signal VSG1-4to the light-emitting element100. In the period t4a, the period (pulse width) in which the first emission control transistor PWT1is turned on is set to a period for achieving a target luminance level of 6.4%, for example, with respect to the maximum lighting luminance.

In the period t4b, the second light emission control transistor PWT2of the second pixel circuit50bis turned on, and the second drive transistor DRT2supplies the electric current (second drive current) corresponding to the second video signal VSG2-4to the light-emitting element100. In the period t4b, the period (pulse width) in which the second emission control transistor PWT2is turned on is set to a period for achieving a target luminance level of 0.8%, for example, with respect to the maximum lighting luminance.

In the period t7a, the second light emission control transistor PWT2of the second pixel circuit50bis turned on, and the second drive transistor DRT2supplies the electric current (second drive current) corresponding to the second video signal VSG2-3to the light-emitting element100. In the period t7a, the period (pulse width) in which the second emission control transistor PWT2is turned on is set to a period for achieving a target luminance level of 0.4%, for example, with respect to the maximum lighting luminance.

In the period t7b, the first light emission control transistor PWT1of the first pixel circuit50ais turned on, and the first drive transistor DRT1supplies the electric current (first drive current) corresponding to the first video signal VSG1-2to the light-emitting element100. In the period t7b, the period (pulse width) in which the first light emission control transistor PWT1is turned on is set to a period for achieving a luminance level of approximately one half of the luminance range assigned to the current drive system.

In the period t10a, the first light emission control transistor PWT1of the first pixel circuit50ais turned on, and the first drive transistor DRT1supplies the electric current (second drive current) corresponding to the first video signal VSG1-3to the light-emitting element100. In the period t10a, the period (pulse width) in which the first emission control transistor PWT1is turned on is set to a period for achieving a target luminance level of 3.2%, for example, with respect to the maximum lighting luminance.

In the period t10b, the second light emission control transistor PWT2of the second pixel circuit50bis turned on, and the second drive transistor DRT2supplies the electric current (second drive current) corresponding to the second video signal VSG2-5to the light-emitting element100. In the period t10b, the period (pulse width) in which the second emission control transistor PWT2is turned on is set to a period for achieving a target luminance level of 1.6%, for example, with respect to the maximum lighting luminance.

The display apparatus1according to the second embodiment controls the combination of the periods t1a, t4a, t4b, t7a, t10a, and t10bso as to achieve the lighting time corresponding to the video signals VSG on the low gradation side. Thus, the display apparatus1supplies the electric current (the first video signals VSG1-3and VSG1-4and the second video signals VSG2-1, VSG2-2, VSG2-3, VSG2-4, and VSG2-5) to the light-emitting element100to express the gradation. In the range on the high gradation side, the display apparatus1drives the light-emitting element100by combining the PWM drive system and the current drive system that expresses the gradation by controlling the electric current (first video signals VSG1-1and VSG1-2).

As illustrated inFIGS.9and10, in the range where the target luminance level is larger than 0% and equal to and smaller than 12.8%, the drive signal controller200adjusts the lighting luminance level by combining the electric currents (the first video signals VSG1-3and VSG1-4and the second video signals VSG2-1, VSG2-2, VSG2-3, VSG2-4, and VSG2-5). In other words, the drive signal controller200turns off the first light emission control transistor PWT1and the second light emission control transistor PWT2in the periods t1band t7bin the range on the low gradation side.

As illustrated inFIG.9, in the range where the target luminance level is larger than 12.8% and equal to or smaller than 100%, the drive signal controller200turns on the first light emission control transistor PWT1in at least one of the periods t1band t7bto supply the electric current (first video signals VSG1-1and VSG1-2) to the light-emitting element100. In the range larger than 12.8% and equal to or smaller than 100%, the drive signal controller200supplies all the electric currents (the first video signals VSG1-3and VSG1-4and the second video signals VSG2-1, VSG2-2, VSG2-3, VSG2-4, and VSG2-5) to the light-emitting element100. In other words, the drive signal controller200adjusts the lighting luminance level by combining the PWM drive system and the current drive system in the range on the high gradation side.

In some of the light-emitting elements100, the degree of color change may possibly increase when the current value is small, thereby making changes in light emission chromaticity more likely to occur. The second embodiment employs the PWM drive system that expresses the gradation by controlling the lighting time with the electric current on the low gradation side. Therefore, the second embodiment can supply, although for a short period, a stable current to the optical element on the low gradation side, thereby suppressing changes in light emission chromaticity.

In the periods t1band t7b, the second embodiment achieves the lighting luminance level by the total of the electric currents corresponding to the two first video signals VSG1-1and VSG1-2. The present embodiment is not limited thereto and may achieve the lighting luminance level by the electric current corresponding to one first video signal VSG1. The resolution of the lighting luminance level on the low gradation side can be appropriately modified. The number of currents (the first video signals VSG1-3and VSG1-4and the second video signals VSG2-1, VSG2-2, VSG2-3, VSG2-4, and VSG2-5) and the period (pulse width) can also be modified depending on the resolution of the lighting luminance level.

While the display apparatus1described above is an organic EL display apparatus including OLEDs as the light-emitting elements, it is not limited thereto. The display apparatus1may be an inorganic EL display apparatus including micro LEDs or mini LEDs as the light-emitting elements.

While exemplary embodiments according to the present invention have been described, the embodiments are not intended to limit the invention. The contents disclosed in the embodiments are given by way of example only, and various modifications may be made without departing from the spirit of the present invention. Appropriate modifications made without departing from the spirit of the present invention naturally fall within the technical scope of the invention. At least one of various omissions, substitutions, and modifications of the components may be made without departing from the gist of the embodiments above and the modification thereof.