Patent ID: 12224290

DESCRIPTION OF SPECIFIC EMBODIMENTS OF THE INVENTION

Preferred embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, so as to fully introduce a technical content of the present invention to those skilled in the art, to demonstrate that the present invention can be implemented, thereby making the technical content of the present invention clearer, and making it easier for those skilled in the art to understand how to implement the present invention. However, the present invention can be embodied by many different embodiments. The claimed scope of the present invention is not limited to the embodiments described herein. The description of the embodiments below is not intended to limit the claimed scope of the present invention.

Directional terms mentioned in the present disclosure, such as “above”, “below”, “front”, “back”, “left”, “right”, “inside”, “outside”, “side”, are merely used to indicate directions of the accompanying drawings. The directional terms are used for explaining and illustrating the present invention rather than limiting the claimed scope of the present invention.

In the accompanying drawings, components with a same structure are indicated by similar reference numerals. Components that are similar in structure or function are indicated by a same reference numeral. In addition, for ease of understanding and description, a size and thickness of each component shown in the accompanying drawings are arbitrarily shown, and the size and thickness of each component are not limited in the present disclosure.

Embodiment 1

Please refer toFIG.1, the present disclosure provides a display panel100. The display panel100comprises an array substrate1, a color filter substrate2, and a liquid crystal layer3.

The array substrate1comprises an opening area1100and a non-opening area1200. The array substrate1further comprises a first substrate101, an active layer102, a gate insulating layer103, a gate electrode layer104, a first interlayer insulating layer105, a second interlayer insulating layer106, a source/drain electrode layer107, a planarization layer108, a common electrode layer109, a passivation layer110, and a pixel electrode layer111.

The first substrate101is made of one or more of glass, polyimide, polycarbonate, polyethylene terephthalate, and polyethylene naphthalate, so that the first substrate101has a better impact resistance, and can effectively protect the display panel100. In this embodiment, the first substrate101is made of glass.

The active layer102is disposed on a side of the first substrate101close to the color filter substrate2. The active layer102is located in the non-opening area1200. In this embodiment, the active layer102is made of low temperature polysilicon.

The gate insulating layer103covers a side of the active layer102away from the first substrate101, and extends to cover the first substrate101. The gate insulating layer103is located in the opening area1100and the non-opening area1200. The gate insulating layer103is mainly used to prevent short circuit due to contact between the active layer102and the gate electrode layer104. The gate insulating layer103may be made of SiOx, SiNx, Al2O3, a combined structure of SiNx and SiOx, a combined structure of SiOx, SiNx, and SiOx, or the like. In this embodiment, the gate insulating layer103is made of SiOx.

The gate electrode layer104is disposed on a side of the gate insulating layer103away from the first substrate101and located in the non-opening area1200. The gate electrode layer104may be made of Mo, a combined structure of Mo and Al, a combined structure of Mo and Cu, a combined structure of Mo, Cu, and indium zinc oxide (IZO), a combined structure of IZO, Cu, and IZO, a combined structure of Mo, Cu, and indium tin oxide (ITO), a combined structure of Ni, Cu, and Ni, a combined structure of NiCr, Cu, and NiCr, CuNb, or the like.

The first interlayer insulating layer105covers a side of the gate electrode layer104away from the first substrate101and extends to cover a surface of a part of the gate insulating layer103in the non-opening area1200away from the first substrate101. There are grain boundaries among the polysilicon grains, and there is an interface between polysilicon (the active layer102) and an oxide layer (the gate insulating layer103), which affects electrical properties of a thin film transistor. Therefore, hydrogenation treatment is generally used to improve conductivity, electron mobility, and threshold voltage uniformity of the thin film transistor. In this embodiment, the first interlayer insulating layer105is made of SiNx as a source of hydrogen atoms. The first interlayer insulating layer105is baked at a specific temperature to diffuse hydrogen atoms into the active layer102(polysilicon) and the gate insulating layer103(the oxide layer).

A projection of the first interlayer insulating layer105on the first substrate101is tangent to or separated from a projection of the opening area1100on the first substrate101. In other words, the first interlayer insulating layer105is only disposed in the non-opening area1200, but not disposed in the opening area1100.

The second interlayer insulating layer106covers a side of the first interlayer insulating layer105away from the first substrate101, and is located in the opening area1100and the non-opening area1200. The second interlayer insulating layer106is made of a same material as the gate insulating layer103. That is, in this embodiment, the second interlayer insulating layer106is made of SiOx.

A surface of a part of the second interlayer insulating layer106in the opening area1100close to the first substrate101is attached to a surface of a part of the gate insulating layer103in the opening area1100away from the first substrate101.

The source/drain electrode layer107is disposed on a side of the second interlayer insulating layer106away from the first substrate101, is located in the non-opening area1200, and is electrically connected to the active layer102. The source/drain electrode layer107may be made of Mo, a combined structure of Mo and Al, a combined structure of Mo and Cu, a combined structure of Mo, Cu, and indium zinc oxide (IZO), a combined structure of IZO, Cu, and IZO, a combined structure of Mo, Cu, and indium tin oxide (ITO), a combined structure of Ni, Cu, and Ni, a combined structure of NiCr, Cu, and NiCr, CuNb, or the like.

The planarization layer108covers a side of the source/drain electrode layer107away from the first substrate101, and extends to cover a surface of the second interlayer insulating layer106away from the first substrate101. The planarization layer108is located in the opening area1100and the non-opening area1200. The planarization layer108may be made of SiOx, SiNx, SiNOx, a combined structure of SiNx and SiOx, or the like. In this embodiment, the planarization layer108is made of SiOx.

The common electrode layer109is disposed on a surface of the planarization layer108away from the first substrate101. In this embodiment, the common electrode layer109is made of indium tin oxide (ITO).

The passivation layer110is disposed on a surface of the common electrode layer109away from the first substrate101. The passivation layer110is mainly used to prevent short circuit due to contact between the common electrode layer109and the pixel electrode layer111. The passivation layer110may be made of SiOx, SiNx, Al2O3, a combined structure of SiNx and SiOx, a combined structure of SiOx, SiNx, and SiOx, or the like. In this embodiment, the passivation layer110is made of SiOx.

The pixel electrode layer111is disposed on a surface of the passivation layer110away from the first substrate101. In this embodiment, the pixel electrode layer111is made of indium tin oxide (ITO).

In this embodiment, the second interlayer insulating layer106is made of SiOx, the first interlayer insulating layer is made of SiNx, and the gate insulating layer103is made of SiOx. In actual measurement, a refractive index of the second interlayer insulating layer106is 1.47, a refractive index of the first interlayer insulating layer105is 1.87, and a refractive index of the gate insulating layer103is 1.45.

Please refer toFIG.2, R1=(1.47−1.87)2/(1.47+1.87)2=1.43%, and R2=(1.87−1.45)2/(1.87+1.45)2=1.6%.

Please refer toFIG.3, R3=(1.47−1.45)2/(1.47+1.45)2=0.005%. R3is less than R1+R2. In the display panel100of the present disclosure, the projection of the first interlayer insulating layer105on the first substrate101is tangent to or separated from the projection of the opening area1100on the first substrate101, so that the surface of the part of the second interlayer insulating layer106in the opening area1100close to the first substrate101is attached to the surface of the part of the gate insulating layer103in the opening area1100away from the first substrate101. And, the gate insulating layer103and the second interlayer insulating layer106are made of the same material, so as to reduce a reflectivity of light at a contact surface between the part of the second interlayer insulating layer106and the part of the gate insulating layer103in the opening area1100without affecting characteristics of a thin film transistor (TFT) of the array substrate1. Therefore, the reflectivity of the light at the contact surface between the part of the second interlayer insulating layer106and the part of the gate insulating layer103in the opening area1100is less than a reflectivity of light at a contact surface between a part of the second interlayer insulating layer106and a part of the first interlayer insulating layer105in the non-opening area1200. The reflectivity of the light at the contact surface between the part of the second interlayer insulating layer106and the part of the gate insulating layer103in the opening area1100is less than a reflectivity of light at a contact surface between the part of the first interlayer insulating layer105and a part of the gate insulating layer103in the non-opening area1200. This reduces a reflectivity of the display panel, thereby reducing reflection of the display panel to ambient light, improving a contrast ratio of the display panel, and improving a display effect of the display panel.

The color filter substrate2is disposed opposite to the array substrate1. The color filter substrate2comprises a second substrate201, a plurality of color resist units202, and a plurality of black matrix units203.

The second substrate201is made of one or more of glass, polyimide, polycarbonate, polyethylene terephthalate, and polyethylene naphthalate, so that the second substrate201has a better impact resistance, and can effectively protect the display panel100. In this embodiment, the second substrate201is made of glass.

The black matrix units203are disposed on a surface of the second substrate201close to the first substrate101at intervals. The black matrix units203are configured to prevent cross-color. A projection of one black matrix unit203on the first substrate101coincides with a projection of one non-opening area1200on the first substrate101. The color resist units202are disposed on surfaces of the black matrix units203close to the first substrate101, and extends to cover the surface of the second substrate201close to the first substrate101. The color resist units202comprise red color resist units, green color resist units, and blue color resist units. A projection of one color resist unit202on the first substrate101overlaps with the projection of the opening area1100on the first substrate101. The color resist units202include first color resist parts2021and second color resist parts2022connected to each other. The first color resist parts2021are disposed on surfaces of the black matrix units203close to the first substrate101, and the second color resist parts2022are disposed on a surface of the second substrate201close to the first substrate101. A projection of one of the first color resist parts2021on the first substrate101coincides with a corresponding one of the black matrix units203on the first substrate101, and a projection of one of the second color resist units2022on the first substrate101coincides with the projection of the opening area1100on the first substrate101.

The liquid crystal layer3is disposed between the array substrate1and the color filter substrate2.

Please refer toFIG.1andFIG.4, the present disclosure further provides a method for fabricating an array substrate1, which comprises the following steps. Step S1: defining an opening area1100and a non-opening area1200on a first substrate101, and forming a gate insulating layer103on the first substrate101in the opening area1100and the non-opening area1200. Step S2: forming a first interlayer insulating layer105on a side of a part of the gate insulating layer103in the non-opening area1200away from the first substrate101, wherein a projection of the first interlayer insulating layer105on the first substrate101is tangent to or separated from a projection of the opening area1100on the first substrate101. Step S3: forming a second interlayer insulating layer106covering the first interlayer insulating layer105in the non-opening area1200and a part of the gate insulating layer103in the opening area1100.

Step S2comprises: forming the first interlayer insulating layer105on a side of the gate insulating layer103in the opening area1100and the non-opening area1200away from the first substrate101, removing a part of the first interlayer insulating layer105in the opening area1100, and retaining a part of the first interlayer insulating layer105in the non-opening area1200.

The array substrate, the method for fabricating the same, and the display panel provided by the present disclosure are described in detail above. The present disclosure uses specific embodiments to describe principles and implementations of the present disclosure. The above description of the embodiments is only for helping to understand solutions and core ideas of the present disclosure. Furthermore, those skilled in the art may make modifications to the specific embodiments and applications according to ideas of the present disclosure. In conclusion, the present specification should not be construed as a limitation to the present disclosure.