Patent ID: 12224225

DETAILED DESCRIPTION

Various embodiments will be described more fully hereinafter with reference to accompanying drawings, which are provided for illustrative and explaining purposes rather than a limiting purpose. For clarity, the components may not be drawn to scale. In addition, some components and/or reference numerals may be omitted from some drawings. It is contemplated that the elements and features of one embodiment can be beneficially incorporated in another embodiment without further recitation. In the following methods for manufacturing semiconductor devices, there may be one or more additional operations between the operations described, and the order of the operations may vary. The illustration uses the same/similar reference numerals to indicate the same/similar elements.

As used in the specification and the appended claims, the ordinals such as “first”, “second” and the like to describe elements do not imply or represent a specific position in the structure, or the order of arrangement, or the order of manufacturing. The ordinals are only used to clearly distinguish multiple elements with the same name. As used in the specification and the appended claims, spatial relation terms such as “on”, “above”, “over”, “upper,” “top”, “below”, “beneath”, “under”, “lower”, “bottom” and the like may be used to describe the relative spatial relations or positional relations between one element(s) and another element(s) as illustrated in the drawings, and these spatial relations or positional relations, unless specified otherwise, can be direct or indirect. The spatial relation terms are intended to encompass different orientations of structures in addition to the orientation depicted in the drawings. The structure can be inverted or rotated by various angles, and the spatial relation descriptions used herein can be interpreted accordingly.

Additionally, the terms “electrically connected” and “electrically coupled” used in the specification and claims can refer to an ohmic contact between elements, or current passing through elements, or an operational relation between elements. The operational relation may mean, for example, that one element is used to drive another element, but current may not flow directly between these two elements.

In conventional semiconductor circuit structure of a semiconductor substrate, there are many active regions or active areas (AA) in which the transistors or circuit elements are located, and there are many shallow trench isolation (STI) regions surrounding those active regions, as shown inFIG.1a. Moreover,FIG.1bandFIG.1cdescribe top view of some portion area inFIG.1aand cross section thereof. Wherein, before manufacturing the transistors, the silicon islands in the active regions are covered by the oxide layer and the nitride layer, all of which are deposited above the original semiconductor surface (OSS) of the semiconductor substrate. Nevertheless, the depth of the STI region extending down from the OSS is usually 250˜300 nm, and the material of the STI region is commonly SiO2with quite low thermal conductivity of 1.3˜1.5 W/m×K. Thus, STI regions could elevate higher die temperature and slow down the speed of transistors. To be worse, the STI regions in the semiconductor substrate may occupy 40% or more of total area of the semiconductor substrate, and those STI regions provide no special function except the isolation purpose.

The following describes how to manufacturing heat removal structures in the substrate or the die according to an embodiment of the present invention. Please refer toFIG.2aandFIG.2b. To begin with, on top of the original semiconductor surface, a thin pad-oxide layer101is thermally grown and then a layer of pad-nitride-1102is deposited over the thin pad-oxide layer101. Use the photolithographic etching technique to define the active region103in which the transistor body1031or fin structure will be located under the composite layer of pad-nitride-1102and the pad-oxide101. Outside of this active region103a concave trench region104(its depth t1 calculated from OSS is 250˜300 nm) connected in the wafer has been formed. Then deposit a thick oxide and use the CMP (Chemical-Mechanical-Polishing) technique to make the STI (Shallow Trench Isolation)201with its top surface leveled up with the top surface of the Pad-Nitride-1 layer102(wherein the top view and the cross section are shown inFIG.2aandFIG.2b, respectively).

Then refer toFIG.3aandFIG.3b. Deposit a pad-nitride-2 layer301and use the photolithographic mask technique to leave a portion of this pad-Nitride-2 layer301at the center of the active region103. Wherein, the top view and the cross section are shown inFIG.3aandFIG.3b, respectively. Afterward, please refer toFIG.4aandFIG.4b(the top view and the cross section are shown inFIG.4aandFIG.4b, respectively), etch away the oxide inside the exposed STI region201to a depth of t2 (e.g., 70 nm, or 100˜170 nm deep). Keep the pad-nitride-2 layer301and the oxide of the STI region201under the pad-nitride-2 layer301untouched. So, there are silicon sidewalls under the OSS are exposed. Then use a thermal oxidation proceed to grow a thin layer of oxide401on these sidewalls (e.g., the thickness is about 1.5˜3 nm). Afterward, deposit another pad-nitride-3 layer403. Use an anisotropic etching technique to make the pad-nitride-3 layer403as spacers on the vertical sidewalls. Under an appropriate design on purpose, the pad-nitride-2 layer301is remained on its planar surface but is getting thinner due to the anisotropic etching of making the pad-nitride-3 spacer403.

Please refer toFIG.5aandFIG.5bwhich show the top view and the cross section, respectively. Use an anisotropic etching technique to remove the exposed oxide layer inside most of the STI region201by a thickness of t3 around 8 nm, which results in a planar oxide surface with its distance from the top of the exposed oxide surface to the OSS by a distance around 78 nm (t2+t3). Use an isotropic etching technique to remove the exposed thin oxide layers401so that the silicon on sidewalls is revealed.

Please refer toFIG.6a,FIG.6bandFIG.6c, whereinFIG.6ais the top view,FIG.6bis the cross section along cut line6b-6b′ shown inFIG.6a, andFIG.6cis the cross section along cut line6c-6c′ shown inFIG.6a, respectively. Use an isotopic etching technique to remove part of the exposed silicon surface, especially that etching rate over the crystalline orientation of (110) can be optimally adjusted in much faster than that of (100). Therefore, the silicon layer along the created exposed region can be removed to form vacant tunnel regions601, but the removal process can be well controlled to be terminated at an appropriate adjustment time to leave the silicon protected by the vertical distance underneath the pad-nitride-3 spacer403.

It should be noticed that a different process could be used to accomplish the similar structure as show inFIG.6a,FIG.6bandFIG.6c. For example, after the structure was created as shown inFIG.5aandFIG.5b, then instead of using the aforementioned isotropic etching technique to remove part of the exposed silicon surface, a thermal oxidation process can be used to grown away the exposed silicon areas. Since the exposed silicon area can have somewhat narrow horizontal distance, the grown oxide layer (such as thermal oxide) underneath the top surface of the silicon island can fill the horizontal void quickly with nice smooth close-up shape but the bulk silicon material under the coverage of the pad-Nitride-3 spacer403is well protected to connect the semiconductor body region of the transistor to the wafer substrate as a strong pillar area without being oxidized too much. Then use an isotropic etching technique to remove this thermal oxide to result in similar structures shown inFIG.6a,FIG.6bandFIG.6c.

Please refer toFIGS.7aand7b. Adopt an isotropic etching technique to take away the pad-nitride-3 spacer403. Use a thermal oxidation process to grow a very thin oxide layer701(e.g., 1˜3 nm) to well protect the just created and exposed silicon surface. Then select a suitable material which has very high thermal conductivity (such as Boron-Nitride, BN, which is an electrical insulator but has very high thermal conductivity, such as 600 W/m×K versus 149 W/m×K of silicon material; Aluminum-Nitride, AlN, material which has its thermal conductivity as high as 321 W/m×K; or any other material with suitable thermal conductivity, any of which could be called as Z material702). Then use a CVD process to fill in the vacant tunnel regions601as created by the aforementioned processing results, for example, BN is selected. Of course, the vacancy inside the STI area is filled by BN material (wherein the top view and the cross section are shown inFIG.7aandFIG.7b, respectively).

In another embodiment, the thermal conductivity of the Z material702is higher than silicon, or higher than silicon nitride, or higher than 10 W/m·K or 30 W/m·K. Of course, other possible material of Z material702could be graphene or metal, (such as Copper, Tungsten, or composite metal, etc.), and it is better that the tungsten layer could be covered by another barrier TiN layer or suitable layer. When the material of Z material702is metal, there could be a thin insulator, such as thermal oxide, between the active region and the Z material702. Moreover, the material of Z material702could be a composite material comprising two or more above-mentioned materials. It is clear that the Z material702is different from the original material (SiO2) of the STI region. In another embodiment, the Z material is also different from silicon nitride. The Z material702may include material with thermal conductivity higher than the original isolation material (such as oxide) in the STI region, such as AlN, BN, SiC, Si, deposited diamond, or SiGe, etc.

Thereafter, a CMP technique can be used to take away the BN material or Z material702over the pad-nitride-1 layer102to a planar surface topography, and an anisotropic etching technique is further used to remove some BN material or Z material702over the STI region201. The top of the remained Z material702could be aligned with the OSS, or lower than the OSS. Then deposit a layer of oxide801over the top of the remained Z material702and level up to the pad-nitride-1 layer102. After removal of the pad-nitride-2 layer301, the silicon surface is covered by the pad-nitride-1 layer102and oxide-covered STI region201, and the familiar processes can be carried on to complete the transistors (such as planar transistor, FinFET transistor, or GAA transistor, etc.) in the remaining semiconductor active region (seeFIG.8, wherein the top view and the cross section are shown in8aand8b, respectively).

Some BN material or Z material702is filled into the vacant tunnel regions under the active region (or the silicon body region of the FinFET/Tri-gate device), it is thus given a name as Horizontal Heat-Dissipation Plate (HHDP), as shown inFIG.8. Some Z material702is filled into the STI's vertical vacant area, which is then named as Vertical Heat-Dissipation Column (VHDC). After the transistor is formed in the active region, the source/drain regions of the transistor are positioned close to HDDP and VHDC which have higher thermal conductivity than that of either silicon dioxide (or silicon) materials surrounding the conventionally designed transistor. Actually, the hottest areas of transistor in full operation are centered at the p/n junction areas between the drain region and the source region both connected with the channel region of the transistor, respectively, these HDDP and VHDC structures are very effective to dissipate the heat generated in those p/n junction regions.

Another possibility is to use similar methods previously described to create the HHDP structure with deeper distance from the OSS (Original Silicon Surface). This can increase more HHDPs to enlarge the thermal dissipation areas. For example, after the BN material or Z material702is completed by CVD process, then an anisotropic etching technique can be used to take away the BN material or Z material702standing vertically inside the STI region201. Then the bottom oxide material of the STI region201can be also taken away or etched down by using an anisotropic etching technique (e.g., only 20˜50 nm-thick oxide can be retained inside the STI region without hurting the BN materials already inserted in the vacant tunnel regions601horizontally). Then with the second time of depositing BN material or Z material702into the vacancies of the STI regions, this two-step of forming BN material or Z material702, first for HHDP, then the second for optimizing the volume of BN or Z material702inside almost all of STI regions (seeFIG.9, wherein the top view and the cross section are shown in9aand9b, respectively). Of course, before the second deposition of the Z material702, an additional step to form a thin vertical isolating layer (just like the thin layer of oxide401) could be applied, such that the vertical isolating layer is under the HDDP, and between sidewalls of the silicon substrate and the Z material702.

It is also noted that, as shown inFIG.1a, the STI regions are spread all over the wafer substrate. With HHDP materials all laid below the body region of MOSFETs/transistors (or in the active region) and are connected to all the VHDC material inside the STI regions, this constructed high thermal dissipation materials network can work out as the connected heat-dissipation sink from the operated PN junctions of transistors. By designing the Z material inside the monolithic die and utilizing the familiar monolithic processing recipe, all the Z material could be connected to an edge ring of the chip or die, and then the Z material702inside STI region can be contacted by opening its top surface so that an entire die's Z material702can be thermally connected to the outside edge of the chip/die for even more directly and effectively dissipating the heat, seeFIG.10, wherein the bottom figure ofFIG.10is the cross section view along the cut line10ashown in the top figure ofFIG.10. Therefore, the VHDC in the STI region (and/or HHDP in the active region) is a kind of Direct Die Heat Remover (“DDHR”), and the present invention provides Direct Die Cooling Technology (“DDCT”) based on the proposed VHDC (and/or HHDP).

There are many active regions in the semiconductor substrate, and in the present invention, the active region (or a plurality of active regions) is surrounded by the Z material702. The Z material702extends from one active region to another active regions, and further extends to the edge of the chip/die. Each active region could accommodate the circuit element, such as transistors. In another embodiment, the die/chip with the VHDC (and/or the HHDP) could be thinned first and then opened to reveal the VHDC (and/or the HHDP), such that another substrate with thermal vias or heat sink could be connected to the VHDC (and/or the HHDP) from the bottom of the die/chip.

After the structure of VHDC (and/or the HHDP) is completed by portion of front end of line (FEOL) processes, the rest of FEOL foundry processes could be used to form the transistors in the active region, as shown inFIG.11. The diffusion regions (or source/drain region) of the transistor are contacted or almost contacted to the VHDC (and/or the HHDP). Thus, it could be described that the VHDC (and/or the HHDP) is formed during the FEOL processes of the foundry manufacturing methods, or within the FEOL region of the semiconductor die.

InFIG.11, the transistor comprises a gate structure which includes a gate metal region1101and a Hi-K dielectric1102. The transistor also comprises a source region1103which includes a lightly-doped region laterally extending from a sidewall of the substrate and a heavily-doped region laterally extending from the sidewall of the lightly-doped region. Those lightly-doped region and heavily-doped region are formed by selective growth methods, such as epitaxial growth methods. Over the top of the source region1104there is a metal contact1105between the gate structure of the transistor and the STI region801. It is noticed that the top surface of the STI region801is higher than the OSS (such as level up with the top of the gate structure), such that a contact hole is automatically formed without using photo lithography process to form such contact hole, and therefore the metal contact1105would be self-aligned with the source region1103. Moreover, in another embodiment, the metal contact1105could not only be connected to the top of the source region1103, but also connected to the most lateral sidewall of the source region1103. The transistor also comprises a drain region1104the structure of which is the same or substantially the same as that of the source region1103, and the description thereof is omitted.FIG.11shows the final transistor structure with the HHDP and VHDC microstructures for a new “Cool Transistor (CQT)” which is the best term to describe one embodiment of the present invention. Such a CQT structure can realize the scaling-up (more transistors) and scaling-down (smaller transistor size) strategy from present GSI (GigaScale Integration) to the near-future TSI (Tera Scale Integration) era. The newly created thermal dissipation path for a chip or die is directly to generate heating paths from a transistor level to the entire die level. There is some design which can connect the die-level thermal path to a chip-level thermal path which can certainly be an effective heat-dissipation sink for a chip package and/or for some heterogeneous integration module (e.g., Through TSV or TIV, etc.) under the present cooling method out of die and package/heterogeneous integration module.

Furthermore, in another embodiment, the processes to form the Horizontal Heat-Dissipation Plate (HHDP) could be skipped and only the Vertical Heat-Dissipation Columns (VHDC) are constructed. For example, please refer toFIG.2, the STI region201could be first etched down to reveal sidewalls of the Si substrate such that the remained depth of the STI material is around 150˜200 nm, then the thin thermal oxide layer401could be formed along the revealed sidewalls of the Si substrate. Afterward, the Z material702could be deposited and etched back with a depth of 100˜150 nm to form the VHDC, and additional oxide801or other isolating material is deposited over the VHDC, as shown inFIG.12a.

FIG.12bshows a cross section view regarding VHDC in STI region of another embodiment according to the present invention. The difference betweenFIG.12bandFIG.12bis that, most of SiO2material in STI region are replaced by VHDC. Conventionally, the depth of STI region, starting from the original semiconductor surface (OSS) of the die, is 250˜300 nm. InFIG.12b, only 20˜50 nm of SiO2material is left in the lower portion of STI region, however, there is 150˜200 nm depth of SiO2material left in the lower portion of STI region shown inFIG.12a. The more SiO2is replaced by the VHDC, the higher of the heat conductivity of the die structure. Of course, the top of the VHDC could be lower or higher than the OSS. Similarly, the VHDC structure inFIG.12aorFIG.12bcould extend along all STI regions within the semiconductor die as well, as shown inFIG.12c, wherein the bottom figure ofFIG.12cis the cross section view along the cut line12cshown in the top figure ofFIG.12c.

FIG.13shows another Cool Transistor, and the difference between theFIG.13andFIG.11is that, the Cool Transistor ofFIG.13is based on the VHDC in STI region shown inFIG.12b. The other descriptions of the Cool Transistor ofFIG.13are the same as those of the Cool Transistor ofFIG.11, and the details of which are skipped for simplicity.

As previously mentioned, the VHDC or the Z material could be made of a single high thermal dissipation material, and could be made of a composite structure as well. For example, the VHDC comprises a layer of first high thermal dissipation material (such as BN, AlN, etc., not shown inFIG.12aorFIG.12b) and another metal or metal-like column covered by the first high thermal dissipation material. Since the VHDC is within the STI region and the metal-like material is surrounded by the first high thermal dissipation material which is a non-conductive during the operation of the transistors in the die/chip (and in this situation, the thin thermal oxide layer401may be skipped), the metal-like material of the VHDC will not impact the operation of the transistors in the die/chip. Of course, both the first high thermal dissipation material and the metal or metal-like column could further extend to edges of the die/chip, and form heat dissipation network as previously mentioned. Therefore, there is a composite-material STI region (including the original STI material SiO2and the VHDC; just including just VHDC which is a composite material with two different layers) or Heterogeneous STI (HSTI) region in the semiconductor structure according to the present invention.

Furthermore, in one embodiment, all or most of the STI regions inFIG.1acould be replaced by the composite-material STI region, such that four sidewalls of the active region are surrounded by the composite-material STI region. Such composite-material STI region extends from one active region to another active regions, and further extends to the edge of the chip/die. In another embodiment, a peripheral border of a first set of active regions is surrounded by the composite-material STI region which extends to a second set of active regions, and further extends to the edge of the chip/die.

FIG.14aillustrates a schematic top view of a semiconductor circuit structure200in the substrate according to one embodiment of the present disclosure. The semiconductor circuit structure200can be formed within a semiconductor chip or substrate.FIG.14ashows more active areas or active regions220A, STI regions220B, and pad open layers220C which may accommodate contacting pads of the semiconductor circuit structure200. Some big STI regions224-1˜224-4of the STI regions220B could be located at corner area adjacent to peripheral/edge area of the semiconductor chip, or at center spare area of the chip. Big VHDC structures (such as VHDC pads)209are located within the big STI regions224-1˜224-4and positioned under the original semiconductor surface of the semiconductor substrate. Additionally, other thin or long VHDC structures (such as VHDC line)205are positioned under the original semiconductor surface of the semiconductor substrate and formed within those thin or long STI regions214-1˜214-4of the STI region220B. The VHDC structures205and the STI regions214-1˜214-4may extend along the X direction (or along the length direction of active areas). Furthermore, the VHDC structure205may extend over two or more active regions220A, e.g., the VHDC structure205located on the top-right portion ofFIG.14aextends from one predetermined point adjacent to the active area220A-1to the big STI region224-1.

InFIG.14a, on one side of the STI regions214-1, there is a first set of active regions extending along the x direction; and one the other side of the STI regions214-1, there is a second set of active regions extending along the x direction as well. Thus, the STI regions214-1is between the first set of active regions and the second set of active regions, and extends along the x direction. Moreover, the VHDC structure205within the STI regions214-1is also between the first set of active regions and the second set of active regions and extends along the x direction. In one embodiment, the smallest one and/or the longest width of the VHDC structure205(such as, along the y direction) between the first set of active regions and the second set of active regions is smaller than the width of the VHDC structure209(such as, along the y direction) connected to the VHDC structure205.

Furthermore, each of the STI regions214-1˜214-4may neighbor a set of transistors in a plurality of active areas220A, and the big STI region224-1may be remote from the set of transistors. The VHDC structure205is coupled to or directly connected to the VHDC structure209.

The width of the VHDC structure209along the Y direction is greater the width of the VHDC structure205along the Y direction. For example, the width of the VHDC structure209along the Y direction may range from about 2 μm˜8 μm. The width of the VHDC structure205along the Y direction may range from about 10 nm˜100 nm. The area of the VHDC structure209may range from about 4 μm2to about 50 μm2. The materials of the VHDC structures205and209may be the same or different.

The spare or big STI regions224may form extra alignment marks for the backside through silicon vias (TSVs) or thermal vias extending from the bottom of the big STI regions224to the bottom side of the substrate, as shown inFIG.14b. Those TSVs pr thermal vias are right under and connected to the big size VHDC pads within the big STI region224. The area of the spare or big STI regions224is big enough to accommodate one or more TSVs or thermal vias therein. Of course, those spare or big STI regions224may also form extra alignment marks for the topside TSVs or thermal vias extending from the top of the big STI regions224to the top side of the substrate. Those thermal vias are right above and connected to the big size big size VHDC pads within the spare STI region. The TSVs or thermal vias of the present invention could be made by the back end of line (BEOL) foundry processes and connected to the big size VHDC pads. Thus, it could be described that the TSVs or thermal vias are formed during the BEOL processes of the foundry manufacturing methods, or within the BEOL region of the semiconductor die.

In other embodiments, the VHDC structures may extend along directions other than the X direction, as shown inFIG.15a.FIG.15aillustrates a schematic top view of a semiconductor circuit structure300according to some embodiments of the present disclosure. As compared with the semiconductor circuit structure200shown inFIG.14a, the semiconductor circuit structure300shown inFIG.15afurther includes STI regions314-1,314-2and314-3, and VHDC structures305-1,305-2and305-3extending along the Y direction. The VHDC structures305-1,305-2and305-3are positioned under the original semiconductor surface of the semiconductor substrate and formed within the STI regions314-1,314-2and314-3, respectively. The VHDC structures305-1,305-2and305-3can be VHDC lines. The VHDC structures305-1,305-2and305-3and the STI regions314-1,314-2and314-3may extend along the Y direction (or along the width direction of active areas). Furthermore, the VHDC structure305-1,305-2and305-3may extend over two or more active regions220A, e.g., the VHDC structure305-1located on the top-left portion ofFIG.15extends from one predetermined point adjacent to the active area220A-2to the horizontal STI region214. Each of the STI regions314-1,314-2and314-3may neighbor a set of transistors in the active areas220A.

InFIG.15a, the VHDC structures extending along directions other than the X direction may be connected to (or electrically coupled to) the VHDC structures extending along the X direction and/or the VHDC pads within the big STI regions. For example, the VHDC structure305-1is connected to (or electrically coupled to) the VHDC structure205; the VHDC structure305-2is connected to (or electrically coupled to) two VHDC structures205and between these two VHDC structures205; the VHDC structure305-3is connected to (or electrically coupled to) the VHDC pad209within the big STI region224. The VHDC structures305-1,305-2and305-3can be similar in size and material to the VHDC structures205.

With the arrangement of the VHDC structures/lines extending along the X direction, the VHDC structures/lines extending along the Y direction (or directions other than the X direction), and the VHDC pads within the big STI regions, an VHDC mesh within the chip or the semiconductor substrate and under the original semiconductor surface of the semiconductor substrate (or called as “Direct Die Cooling Technology”) is provided. The VHDC structures extending along the X direction (i.e., the horizontal VHDC lines) can be used to connect the VHDC structures within the big STI regions (i.e., the VHDC pads), and the VHDC structures extending along the Y direction (i.e., the vertical VHDC lines) can be used to connect the VHDC pads or the horizontal VHDC lines.

In some embodiments, the VHDC structures extending along directions other than the X direction, such as the VHDC structures305-1,305-2and305-3shown inFIG.15a, can be manufactured through the follow steps.FIGS.15bto15cillustrate schematic top views of structures at different stages of the manufacturing method. A pad-oxide layer (not shown) and a pad-nitride layer3206are sequentially deposited on the semiconductor substrate. Then, temporary active areas could be firstly defined by a photolithographic process, and the temporary STI regions and the big STI regions (indicated by dotted lines inFIG.15b) can be defined outside the temporary active areas. The Z material is then formed in the temporary STI regions and the big STI regions. Then, true active areas150A can defined by another photolithographic process, and the removed temporary active areas then be used for rest STI regions, as shown inFIG.15c.

The position, size, number of the VHDC structures are not limited to those shown inFIGS.14and15a. As mentioned, for heat dissipation application, the VHDC structures can include (or can be made of) high thermal conductivity materials such as tungsten (having a thermal conductivity around 170 W/m·K), boron nitride (BN, having a thermal conductivity around 600 W/m·K), aluminum nitride (AlN, having a thermal conductivity around 321 W/m·K). It is also possible that other material with thermal conductivity higher than the original material (silicon dioxide) of STI region could be used, such as SiC, SiGe, undoped Si, or deposited diamond. In some embodiments, the VHDC structures can include (or can be made of) composite materials including two or more high thermal conductivity material. In the present invention, portion of silicon dioxide in the original STI regions can be replaced by the VHDC structures, thereby improving the ability of heat dissipation due to the thermal conductivity of the materials of the VHDC structures are higher than silicon dioxide and/or silicon.

As shown inFIG.15a, the VHDC structures used for heat dissipation extend from some STI regions next to active areas in which transistors are located to the big STI regions in which the VHDC pads (for example, the area of the VHDC pad may range from about 4 μm2to about 50 μm2) are located. In another example, all VHDC structures can be thermally coupled together. For example, the VHDC structure in the big STI region (i.e., the VHDC pad) can be thermally coupled to the VHDC structure in the STI region (i.e., the VHDC line). Furthermore, the big STI regions can be adopted to align with one or more thermal vias as shown inFIG.14b. Moreover, all or most of STI regions (such as more than 60%, or even 70%-90%) in the semiconductor chip could be filled with the proposed VHDC structures for heat dissipation purpose.

FIG.16aillustrates a schematic cross-sectional view of a semiconductor circuit structure700according to some embodiments of the present disclosure. The semiconductor circuit structure700includes an upper interconnection structure440over the semiconductor substrate400. The upper interconnection structure440includes a contact structure441, metal layers M1to M3, connecting vias V1and V2, and a dielectric layer (or a set of insulator layers)442. The contact structure441, the metal layers M1to M3, and the connecting vias V1and V2are in the dielectric layer442which may include multiple dielectric sub-layers. The contact structure441is between the transistor TS and the metal layer M1. The metal layers M1to M3are sequentially positioned above the original semiconductor surface OSS of the semiconductor substrate400along the Z direction. The metal layers M1to M3are vertically separately from each other. The connecting vias V1and V2are positioned above the original semiconductor surface OSS of the semiconductor substrate400. The connecting via V1is between the metal layers M1and M2. The connecting via V2is between the metal layers M2and M3. The metal layers M1to M3and the connecting vias V1and V2are electrically connected to each other.

The semiconductor circuit structure700further includes a backside TSV733right under and connected to the second VHDC structure209(i.e. the VHDC pad which includes composite layers as shown inFIG.16a) within the big STI region424, a heat dissipation film734on a sidewall of the TSV733, a barrier or isolating film735on a sidewall of the heat dissipation film734, a heat dissipation plate737located on or close to the backside surface400B of the semiconductor substrate400(or on the backside of the chip), and a top heat dissipation plate739above the upper interconnection structure440. The TSV733is used for heat dissipation and can be understood as a (backside) thermal via. The heat dissipation plate737can be a heat sink and the material of which could be the same as that of the heat dissipation film734or the TSV733. The TSV733extends from the bottom surface of the second VHDC structure209to the backside surface400B of the semiconductor substrate400. The TSV733is connected between the second VHDC structure209and the heat dissipation plate737to form a heat dissipation path which includes the second VHDC structure, the TSV733and the heat dissipation plate737.

For heat dissipation, the VHDC structures in the present embodiment may include (or may be made of) materials having thermal conductivities higher than the thermal conductivity of SiO2. For example, the VHDC structures may include tungsten, copper, BN, AlN, SiC, SiGe, or deposited diamond, undoped Si, or the combination thereof. In some embodiments, the VHDC structures include isolation material with a thermal conductivity higher than the thermal conductivity of Si. The TSV733may include copper, and the heat dissipation film734could be BN or AlN.

Furthermore, the TSV733are directly connected to the second VHDC structures209, the second VHDC structures209are then connected to the first VHDC structures205(that is, the VHDC line which includes composite layers as shown inFIG.16a) in the STI isolation414, and the first VHDC structures205could be further connected to the transistors (such as source/drain regions of the transistors) through the corresponding connecting plug431. As such, heat generated from the transistor can be dissipated through the connecting plug431, the first VHDC structure205, and the second VHDC structure209to the TSV733. Thus, an VHDC heat dissipation network with high heat dissipation efficiency is provided. In another embodiment, the VHDC structures may be isolated from the transistors, but the heat dissipation purpose could be reached through the VHDC lines, the VHDC pads, and the TSV733.

The VHDC205within and extended along the STI region414can be connected to, through a self-aligned or self-constructed method, the source or drain terminal of the transistor through the connecting plug431which is within the active area accommodating the transistor. The connecting plug431is connected to a sidewall of the VHDC structure.

The conventional semiconductor circuit structure only includes upper thermal vias in the upper interconnection structure440and does not include VHDC structures, especially the VHDC pads. Therefore, the alignment of the upper thermal vias is a critical issue. In addition, the upper thermal vias of the conventional semiconductor circuit structure are just positioned within and isolated by the dielectric layer442of the upper interconnection structure440, and those upper thermal vias are remoted from the transistors. Thus, the heat generated from the transistors is difficult to be dissipated efficiently. However, the semiconductor circuit structure according to the present disclosure provides bigger alignment window for the thermal vias through the help of VHDC pads. Moreover, the thermal coupling path between the thermal vias and the source/drain terminal of the transistors are shorter through the help of VHDC structures. Therefore, heat generated from the transistors can be dissipated efficiently through the configuration of the present disclosure.

FIG.16billustrates a schematic cross-sectional view of a semiconductor circuit structure800according to some embodiments of the present disclosure. The semiconductor circuit structure800includes upper or topside thermal vias833in the dielectric layer442of the upper interconnection structure440. The upper thermal vias833extend upward from the upper surface of the second VHDC structure209to the top heat dissipation plate739and penetrate the dielectric layer442of the upper interconnection structure440.

Thus, the upper thermal vias833are connected the second VHDC structure209(the VHDC pads in the STI isolation424), the second VHDC structure209is then connected to the first VHDC structures205(that is, the VHDC lines in the STI isolation414), and the first VHDC structures205are connected to the transistors (such as source/drain regions of the transistors) through the corresponding connecting plug431. Therefore, the top heat dissipation plate739, the upper thermal vias833, the first VHDC structures205and the second VHDC structures209could form a heat dissipation path for the heat generated by the transistors. As such, heat generated from the transistor can be dissipated through the connecting plug431, the first VHDC structure205, and the second VHDC structure209to the upper thermal vias833. An VHDC heat dissipation network with high heat dissipation efficiency is provided according to the present direct heat cooling technology. In another embodiment, the VHDC structures205(the VHDC lines in the STI isolation414) may be isolated from the transistors, but the heat dissipation purpose could still be reached. In other embodiments, the upper thermal vias833can extend from the upper surface of the upper interconnection structure440to the first VHDC structures205. Furthermore, the material of the upper thermal via833may be the Z material having a thermal conductivity higher than Si or SiO2, such as copper, and the material of the upper thermal via833could be the same as or different from the material of the top heat dissipation plate739.

FIG.16cillustrates a schematic cross-sectional view of a semiconductor circuit structure900according to some embodiments of the present disclosure. The difference between the semiconductor circuit structure900shown inFIG.16cand the semiconductor circuit structure800shown inFIG.16bis that, the semiconductor circuit structure900includes upper heat dissipation films934on sidewalls of the upper thermal vias833. The upper heat dissipation film934may include (or may be made of) a material having a thermal conductivity higher than Si or SiO2, such as BN or AlN. Configuring upper heat dissipation film934on the upper thermal via833can improve heat dissipation efficiency.

In some embodiments, the TSV733shown inFIG.16aand the upper thermal via833shown inFIG.16b(or the upper heat dissipation films934and the upper thermal vias833inFIG.16c) can be combined together, as shown inFIG.16d. In the semiconductor circuit structure910shown inFIG.16d, some upper thermal vias833extend from the upper surface of the upper interconnection structure440to the second VHDC structure209, and are connected to the top heat dissipation plate739. The TSV733(additional thermal vias) extends from the backside surface400B of the semiconductor substrate400to the second VHDC structure209(or other VHDC structure), and are connected to the heat dissipation plate737located on or close to the backside surface400B of the semiconductor substrate400. Such sandwich structure (with middle VHDC structures in the chip, the top heat dissipation plate connected to the middle VHDC structures, and the heat dissipation plate on the backside surface of the semiconductor substrate and connected to the middle VHDC structures) can greatly enhance the ability of heat dissipation of the IC chip.

For the advanced 2.5D or 3D packaging structure or even the HBM structure, there are two or more IC/memory chips stacked together. Thus, any of the structures ofFIG.16a˜16dcould be utilized in those IC chips which are then vertically stacked together. For example, as shown inFIG.16e, the VHDC structures inFIG.16dare utilized in both the chip C1and chip C2which are stacked together. In another embodiment, the chip C1(with the VHDC structure inFIG.16b) could be flipped upside down first and then stacked over the chip C2(with the VHDC structure inFIG.16d), as shown inFIG.16f. Of course, there could be another interposer (such as Si interposer or other interposer) disposed between those two IC chips, and any of the structures ofFIG.16a,16b, or16ccould be utilized in the interposer.

FIG.17ashows the semiconductor circuit structure including a FinFET transistor and a STI region adjacent to (or surrounding) the FinFET transistor, in which portion of the STI region (marked by slash lines) is replaced by the VHDC structure made of Tungsten.FIG.17afurther shows the temperature distribution of FinFET established by Sentaurus of TCAD simulation software. The temperature difference (ΔT) between the peak temperature of the transistor (the hot spot region) and the ambient temperature (40° C.) is calculated when a portion of the STI region is replaced by Tungsten, as shown inFIG.17b. The term “Full” inFIG.17brepresents that none of the STI region is not replaced by Tungsten. The terms “1 nm” to “15 nm” represent the remaining thickness of the STI region not replaced by Tungsten. It is clear that the smaller the remaining thickness of the STI region, the smaller the temperature difference between the peak temperature of the transistor and the ambient temperature (the better the heat dissipation performance). Thus, the present disclosure can effectively reduce the peak temperature of the transistor.

The present disclosure provides direct die cooling technology based on the composite-material STI regions (or heat remover structures, e.g., VHDC lines and VHDC pads under the original semiconductor surface and within the STI regions). Depending on the requirement, some VHDC structures could be connected to the transistors, and the heat remover structures can form a VHDC mesh or heat dissipation network within the chip or semiconductor substrate, which provides bigger misalignment tolerance due to the big STI regions with a lot of space for accommodating the VHDC pads, and shorten the path to connect backside TSVs to VHDC mesh to improve IR drop of the signal delivery, and enhance the heat dissipation.

It is noted that the structures and methods as described above are provided for illustration. The disclosure is not limited to the configurations and procedures disclosed above. Other embodiments with different configurations of known elements can be applicable, and the exemplified structures could be adjusted and changed based on the actual needs of the practical applications. It is, of course, noted that the configurations of figures are depicted only for demonstration, not for limitation. Thus, it is known by people skilled in the art that the related elements and layers in a semiconductor structure, the shapes or positional relationship of the elements and the procedure details could be adjusted or changed according to the actual requirements and/or manufacturing steps of the practical applications.

While the disclosure has been described by way of example and in terms of the exemplary embodiment(s), it is to be understood that the disclosure is not limited thereto. On the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.