Patent ID: 12232318

DETAILED DESCRIPTION

A nonvolatile memory device according to some embodiments will be described below with reference toFIGS.1through17.

FIG.1is an exemplary circuit diagram of the nonvolatile memory device according to some embodiments.

Referring toFIG.1, a memory cell array of the nonvolatile memory device according to some embodiments may include a common source line CSL, a plurality of bit lines BL1and BL2, and a plurality of cell strings CSTR1to CSTR4.

The plurality of bit lines BL1and BL2may be arranged two-dimensionally. In an implementation, the respective bit lines BL1and BL2may be spaced apart from each other and extend in a first direction X. A plurality of cell strings CSTR1to CSTR4may be connected in parallel to each of the bit lines BL1and BL2. The cell strings CSTR1to CSTR4may be commonly connected to a common source line CSL. In an implementation, a plurality of cell strings CSTR1to CSTR4may be between the plurality of bit lines BL1and BL2and the common source line CSL.

A plurality of common source lines CSL may be arranged two-dimensionally. In an implementation, the respective common source lines CSL may be spaced apart from each other and extend in a second direction Y. The same voltage may be electrically applied to the common source lines CSL or different voltages may be applied to the common source lines CSL to be controlled separately.

In an implementation, each of the cell strings CSTR1to CSTR4may include ground selection transistors GST connected to the common source line CSL, a plurality of string selection transistors SST1to SST3connected to the bit lines BL1and BL2, and a plurality of memory cell transistors MCT1to MCT4interposed between the ground selection transistor GST and the string selection transistor SST1to SST3. Each of the memory cell transistors MCT1to MCT4may include a data storage element. The ground selection transistors GST, the string selection transistors SST1to SST3and the memory cell transistors MCT1to MCT4may be connected in series.

The common source line CSL may be commonly connected to the sources of the ground selection transistors GST. Further, the ground selection lines GSL, a plurality of word lines WL1to WLn and the string selection lines SSL1to SSL3may be between the common source line CSL and the bit lines BL1and BL2.

The ground selection line GSL may be used as the gate electrode of the ground selection transistor GST, the plurality of word lines WL1to WLn may be used as the gate electrodes of the memory cell transistors MCT1to MCT4, and the string selection lines SSL1to SSL3may be used as the gate electrodes of the string selection transistors SST1to SST3.

In an implementation, the respective string selection lines SSL1to SSL3may be separated from each other. In an implementation, the first string selection line SSL1may include first and second sub-string selection lines SSL1_1and SSL1_2separated from each other. The second string selection line SSL2may include third and fourth sub-string selection lines SSL2_1and SSL2_2separated from each other. The third string selection line SSL3may include fifth and sixth sub-string selection lines SSL3_1and SSL3_2separated from each other.

The first sub-string selection line SSL1_1may form a first sub-string selection transistor SST1_1, and the second sub-string selection line SSL1_2may form a second sub-string selection transistor SST1_2. The third sub-string selection line SSL2_1may form a third sub-string selection transistor SST2_1, and the fourth sub-string selection line SSL2_2may form a fourth sub-string selection transistor SST2_2. The fifth sub-string selection line SSL3_1may form a fifth sub-string selection transistor SST3_1, and the sixth sub-string selection line SSL3_2may form a sixth sub-string selection transistor SST3_2.

In an implementation, each of the memory cell transistors MCT1to MCT4may be selected separately by the string selection lines SSL1to SSL3and controlled. For example, the first memory cell transistor MCT1may be selected by the first, third, and fifth sub-string selection transistors SST1_1, SST2_1and SST3_1. The second memory cell transistor MCT2may be selected by the second, third, and fifth sub-string selection transistors SST1_2, SST2_1and SST3_1. The third memory cell transistor MCT3may be selected by the second, third, and sixth sub-string selection transistors SST1_2, SST2_1and SST3_2. The fourth memory cell transistor MCT4may be selected by the second, fourth, and sixth sub-string selection transistors SST1_2, SST2_2and SST3_2.

Therefore, the nonvolatile memory device according to some embodiments may help improve the degree of integration using a plurality of string selection lines SSL1to SSL3, even without an additional bit line.

FIG.2is a layout diagram of a nonvolatile memory device according to some embodiments.FIG.3is a cross-sectional view taken along a line A-A ofFIG.2.FIG.4is an enlarged view of a part R1ofFIG.3.FIGS.5A to5Eare various enlarged views of a part R2ofFIG.3.FIG.6is a schematic partial perspective view of the first to third string selection lines ofFIG.3. For convenience of explanation, repeated parts of contents described above usingFIG.1may be briefly described or omitted.

Referring toFIGS.2to5E, the nonvolatile memory device according to some embodiments may include a substrate100, a mold structure MS, a plurality of channel structures C1to C8, a plurality of cutting lines S1to S3, and a plurality of bit lines BL1and BL2.

The substrate100may include, e.g., a semiconductor substrate such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. In an implementation, the substrate100may include a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or the like. As used herein, the term “or” is not an exclusive term, e.g., “A or B” would include A, B, or A and B.

The mold structure MS may be on the substrate100. The mold structure MS may include a plurality of gate electrodes (GSL, WL1to WLn, and SSL1to SSL3) and a plurality of insulating patterns110stacked on the substrate100. In an implementation, each of the gate electrodes (GSL, WL1to WLn, and SSL1to SSL3) and each insulating pattern110may have a layered structure extending in the first direction X and the second direction Y.

The respective gate electrodes (GSL, WL1to WLn, and SSL1to SSL3) may be alternately stacked with the respective insulating patterns110.

In an implementation, a plurality of gate electrodes (GSL, WL1to WLn, and SSL1to SSL3) may be stacked in a step pattern. In an implementation, as illustrated inFIG.3, the plurality of gate electrodes (GSL, WL1to WLn, and SSL1to SSL3) may have the same thickness. In an implementation, the plurality of gate electrodes (GSL, WL1to WLn, and SSL1to SSL3) may have thicknesses different from each other.

In an implementation, the plurality of gate electrodes (GSL, WL1to WLn, and SSL1to SSL3) may include a ground selection line GSL, a plurality of word lines WL1to WLn, and a plurality of string selection lines SSL1to SSL3. The ground selection line GSL, the plurality of word lines WL1to WLn, and the plurality of string selection lines SSL1to SSL3may be sequentially stacked on the substrate100.

In an implementation, as illustrated inFIG.3, three word lines may be between the ground selection line GSL and the string selection lines SSL1to SSL3. In an implementation, eight, sixteen, thirty-two, sixth-four or more word lines may be stacked between the ground selection line GSL and the string selection lines SSL1to SSL3.

In an implementation, a plurality of string selection lines SSL1to SSL3may include first to third string selection lines SSL1to SSL3sequentially stacked on a plurality of word lines WL1to WLn. As used herein, the numbering of described elements is not intended to require the elements be provided sequentially. In addition, the numbering of described elements may be changed for ease of description.

In an implementation, the first string selection line SSL1may be on the uppermost word line WLn. The second string selection line SSL2may be on the first string selection line SSL1. The third string selection line SSL3may be on the second string selection line SSL2. In an implementation, the third string selection line SSL3may be a gate electrode at an uppermost part (e.g., distal to the substrate100in a vertical or third direction Z) among the plurality of gate electrodes (GSL, WL1to WLn, and SSL1to SSL3).

Each of the gate electrodes (GSL, WL1to WLn, and SSL1to SSL3) may include a conductive material. In an implementation, each of the gate electrodes (GSL, WL1to WLn, and SSL1to SSL3) may include, e.g., a metal such as tungsten (W), cobalt (Co), nickel (Ni) or a semiconductor material such as silicon.

Each insulating pattern110may include an insulating material. In an implementation, each insulating pattern110may include, e.g., silicon oxide.

The mold structure MS may be cut by a first cutting region WLC1and a second cutting region WLC2. Each of the gate electrodes (GSL, WL1to WLn, and SSL1to SSL3) may be cut by the first cutting region WLC1and the second cutting region WLC2. In an implementation, as shown inFIGS.2and3, the first cutting region WLC1and the second cutting region WLC2may extend side by side along the second direction Y to form a mold structure MS.

In an implementation, a cutting structure150may be in the first cutting region WLC1and the second cutting region WLC2. As shown inFIG.3, the cutting structure150may penetrate the mold structure MS and extend to the substrate100(e.g., in the third direction Z). The cutting structure150may extend (e.g., lengthwise) in the second direction Y to cut the mold structure MS. In an implementation, the cutting structure150may include a plug pattern152and a spacer154.

The plug pattern152may penetrate the mold structure MS and be connected to the substrate100. In an implementation, the plug pattern152may be a common source line (e.g., CSL ofFIG.1) of the nonvolatile memory device according to some embodiments. In an implementation, the plug pattern152may include a conductive material. In an implementation, the plug pattern152may be connected to the impurity region105in the substrate100. The impurity region105may extend, e.g., in the second direction Y.

The spacer154may be between the plug pattern152and the mold structure MS. In an implementation, the spacer154may extend along the side face of the plug pattern152. The spacer154may include an insulating material. The plug pattern152may be electrically spaced apart from the plurality of gate electrodes (GSL, WL1to WLn, and SSL1to SSL3) of the mold structure MS.

The plurality of channel structures C1to C8may penetrate the mold structure MS and intersect the respective gate electrodes (GSL, WL1to WLn, and SSL1to SSL3). In an implementation, each of the channel structures C1to C8may have a pillar shape extending in the third direction Z intersecting an upper surface of the substrate100. In an implementation, each of the channel structures C1to C8may penetrate the mold structure MS and be connected to the substrate100. Each of the channel structures C1to C8may include a semiconductor pattern130and an information storage film132.

The semiconductor pattern130may penetrate the mold structure MS and be connected to the substrate100. In an implementation, as illustrated inFIG.3, the semiconductor pattern130may have a cup shape. In an implementation, the semiconductor pattern130may have various shapes such as a cylindrical shape, a square cylindrical shape, and a sold pillar shape.

The semiconductor pattern130may include, e.g., semiconductor materials such as single crystal silicon, polycrystalline silicon, organic semiconductor material, and carbon nanostructure.

The information storage film132may be between the semiconductor pattern130and each of the gate electrodes (GGS, WL1to WLn, and SSL1to SSL3). In an implementation, the information storage film132may extend along the side face of the semiconductor pattern130. In an implementation, as illustrated inFIG.2, the information storage film132may continuously extend along the side face of the semiconductor pattern130. In an implementation, the information storage film132may discontinuously extend on the side face of the semiconductor pattern130. In an implementation, a part of the information storage film132may extend along the upper surface and/or the lower surface of each gate electrodes (GSL, WL1to WLn, and SSL1to SSL3).

The information storage film132may include, e.g., at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high dielectric constant material having a dielectric constant higher than that of silicon oxide.

In an implementation, the information storage film132may include a plurality of films. In an implementation, as shown inFIG.4, the information storage film132may include a tunnel insulating film132a, a charge storage film132b, and a blocking insulating film132cstacked in order on the semiconductor pattern130. The tunnel insulating film132amay include, e.g., silicon oxide or a high dielectric constant material (e.g., aluminum oxide (Al2O3), and hafnium oxide (HfO2)). The charge storage film132bmay include, e.g., silicon nitride. The blocking insulating film132cmay include, e.g., silicon oxide or a high dielectric constant material (e.g., aluminum oxide (Al2O3), and hafnium oxide (HfO2)).

In an implementation, each of the channel structures C1to C8may further include a filling insulating pattern134. The filling insulating pattern134may be formed to fill the inside of the semiconductor pattern130having a cup shape. In an implementation, the semiconductor pattern130may conformally extend along the side face and the lower surface (e.g., inner surfaces) of the filling insulating pattern134. The filling insulating pattern134may include, e.g., silicon oxide.

In an implementation, each of the channel structures C1to C8may further include a channel pad136. The channel pad136may be connected to the upper part of the semiconductor pattern130(e.g., a part of the semiconductor pattern130that is distal to the substrate100in the third direction Z). In an implementation, the channel pad136may be in the first interlayer insulating film140on the mold structure MS.

In an implementation, as illustrated inFIG.3, the channel pad136may be on the upper surface of the semiconductor pattern130. In an implementation, the upper part of the semiconductor pattern130may extend along the side face of the channel pad136. The channel pad136may include, e.g., polysilicon doped with impurities.

In an implementation, each of the channel structures C1to C8may have a tapered shape. In an implementation, the width of each of the channel structures C1to C8may increase as it goes away from the substrate100(e.g., in the third direction Z). This may be due to the characteristics of the etching process for forming the channel structures C1to C8.

In an implementation, the plurality of channel structures C1to C8may include first to eighth channel structures C1to C8that are sequentially (e.g., laterally) arranged along the first direction X between the first cutting region WLC1and the second cutting region WLC2. In an implementation, the plurality of channel structures C1to C8may be arranged in a zigzag shape along the first direction X (e.g., channel structures immediately adjacent in the first direction X may be offset in the second direction Y). In an implementation, the first to eighth channel structures C1to C8may be arranged in a line (e.g., aligned linearly) along the first direction X.

A plurality of cutting lines S1to S3may be in the mold structure MS between the first cutting region WLC1and the second cutting region WLC2. In an implementation, the plurality of cutting lines S1to S3may be provided in the same number as the plurality of string selection lines SSL1to SSL3.

In an implementation, three or more string selection lines SSL1to SSL3and three or more cutting lines S1to S3may be in the mold structure MS. In an implementation, first to third string selection lines SSL1to SSL3and first to third cutting lines S1to S3may be in the mold structure MS.

The first cutting line S1may extend, e.g., in the second direction Y and cut the first string selection line SSL1. In an implementation, a part of the first string selection line SSL1may be on one side of the first cutting line S1, and another part of the first string selection line SSL1may be on another side of the first cutting line S1. The first string selection line SSL1on one side of the first cutting line S1may correspond to the first sub-string selection line SSL1_1ofFIG.1, and the first string selection line SSL1on the other side of the first cutting line S1may correspond to the second sub-string selection line SSL1_2ofFIG.1.

The first cutting line S1may re-separate the first string selection line SSL1separated by the first cutting region WLC1and the second cutting region WLC2. The first cutting line S1may be separated from the first cutting region WLC1by a first distance L1a(in the first direction X), and may be separated from the second cutting region WLC2by a second distance L1b. As used herein, the separated distance between both components means the shortest distance between two components.

In an implementation, the first distance L1aand the second distance L1bmay be different from each other. In an implementation, a first difference between the first distance L1aand the second distance L1bmay not be zero. In an implementation, as shown inFIGS.2and3, the second distance L1bmay be greater than the first distance L1a.

The first cutting region WLC1, the second cutting region WLC2, and the first cutting line S1may extend side by side along the second direction Y. In an implementation, from a planar viewpoint (e.g., in plan view and/or when viewed along the third direction Z), a first area (e.g., as defined by dimensions in the first direction X and the second direction Y) of the first string selection line (SSL1or SSL1_1ofFIG.1) on one side of the first cutting line S1may be different from a second area of the first string selection line (SSL1or SSL1_2ofFIG.1) on the other side of the first cutting line S1. In an implementation, when the first distance L1ais smaller than the second distance L1b, the first area may be smaller than the second area. In an implementation, the first cutting line S1may cut the first string selection line SSL1into unequally sized pieces.

In an implementation, the first cutting line S1may not cut the second string selection line SSL2. In an implementation, as shown inFIG.3, the upper surface (e.g., surface facing away from the substrate100) of the first cutting line S1may be lower than (e.g., closer to the substrate100in the third direction Z) or the same as the lower (e.g., substrate100-facing) surface of the second string selection line SSL2.

In an implementation, a plurality of channel structures may be between the first cutting line S1and the first cutting region WLC1and between the first cutting line S1and the second cutting region WLC2. In an implementation, as shown inFIGS.2and3, the first and second channel structures C1and C2may be between the first cutting line S1and the first cutting region WLC1, and the third to eighth channel structures C3to C8may be between the first cutting line S1and the second cutting region WLC2.

The second cutting line S2may extend, e.g., in the second direction Y to cut the second string selection line SSL2. This allows a part of the second string selection line SSL2to be on one side of the second cutting line S2and another part of the second string selection line SSL2to be on another side of the second cutting line S2. The second string selection line SSL2on one side of the second cutting line S2may correspond to the third sub-string selection line SSL2_1ofFIG.1, and the second string selection line SSL2on the other side of the second cutting line S2may correspond to the fourth sub-string selection line SSL2_2ofFIG.1.

The second cutting line S2may re-separate the second string selection line SSL2separated by the first cutting region WLC1and the second cutting region WLC2. The second cutting line S2may be separated from the first cutting region WLC1by a third distance L2aand may be separated from the second cutting region WLC2by a fourth distance L2b(in the first direction X).

In an implementation, the third distance L2aand the fourth distance L2bmay be different from each other. In an implementation, a second difference between the third distance L2aand the fourth distance L2bmay not be zero. In an implementation, as shown inFIGS.2and3, the fourth distance L2bmay be smaller than the third distance L2a. In an implementation, the second difference between the third distance L2aand the fourth distance L2bmay be the same as the first difference between the first distance L1aand the second distance L1b. In this specification, the term “same” means not only the completely same case but also a minute difference that may occur due to a process margin or the like.

The first cutting region WLC1, the second cutting region WLC2, and the second cutting line S2may extend side by side along the second direction Y. From a planar viewpoint, a third area of the second string selection line (SSL2or SSL2_1ofFIG.1) on one side of the second cutting line S2may be different from a fourth area of the second string selection line (SSL2or SSL2_2ofFIG.1) on the other side of the second cutting line S2. In an implementation, when the third distance L2ais larger than the fourth distance L2b, the third area may be made larger than the fourth area.

In an implementation, the second cutting line S2may not cut the first string selection line SSL1and may not cut the third string selection line SSL3. In an implementation, as shown inFIG.3, the lower surface of the second cutting line S2may be higher than or the same as the upper surface of the first string selection line SSL1, and the upper surface of the second cutting line S2may be lower than or the same as the lower surface of the third string selection line SSL3.

In an implementation, a plurality of channel structures may be between the second cutting line S2and the first cutting region WLC1, and between the second cutting line S2and the second cutting region WLC2. In an implementation, as shown inFIGS.2and3, the first to sixth channel structures C1to C6may be between the second cutting line S2and the first cutting region WLC1, and the seventh and eighth channel structures C7and C8may be between the second cutting line S2and the second cutting region WLC2.

The third cutting line S3may extend, e.g., in the second direction Y to cut the third string selection line SSL3. A part of the third string selection line SSL3may be on one side of the third cutting line S3, and another part of the third string selection line SSL3may be on another side of the third cutting line S3. The third string selection line SSL3on one side of the third cutting line S3may correspond to the fifth sub-string selection line SSL3_1ofFIG.1, and the third string selection line SSL3on the other side of the third cutting line S3may correspond to the sixth sub-string selection line SSL3_2ofFIG.1.

The third cutting line S3may re-separate the third string selection line SSL3separated by the first cutting region WLC1and the second cutting region WLC2. The third cutting line S3may be separated from the first cutting region WLC1by a fifth distance L3a, and may be separated from the second cutting region WLC2by a sixth distance L3b(in the first direction X).

In an implementation, a third difference between the fifth distance L3aand the sixth distance L3bmay be smaller than the first difference between the first distance L1aand the second distance L1b. In an implementation, the third difference between the fifth distance L3aand the sixth distance L3bmay be smaller than the second difference between the third distance L2aand the fourth distance L2b. In an implementation, from a planar viewpoint, the third cutting line S3may be between the first cutting line S1and the second cutting line S2.

In an implementation, the fifth distance L3aand the sixth distance L3bmay be the same. In an implementation, the third difference between the fifth distance L3aand the sixth distance L3bmay be zero.

The first cutting region WLC1, the second cutting region WLC2, and the third cutting line S3may extend side by side along the second direction Y. From a planar viewpoint, a fifth area of the third string selection line (SSL3or SSL3_1ofFIG.1) on one side of the third cutting line S3may be the same as a sixth area of the third string selection line (SSL3or SSL3_2ofFIG.1) on the other side of the third cutting line S3.

In an implementation, the fifth distance L3aand the sixth distance L3bmay be greater than the first distance L1a(e.g., the smaller distance among the first distance L1aand the second distance L1b). From a planar viewpoint, the fifth area of the third string selection line (SSL3or SSL3_1ofFIG.1) on one side of the third cutting line S3, and the sixth area of the third string selection line (SSL3or SSL3_2ofFIG.1) on the other side of the third cutting line S3may be greater than the first area of the first string selection line (SSL1or SSL1_1ofFIG.1) on one side of the first cutting line S1, respectively.

In an implementation, the fifth distance L3aand the sixth distance L3bmay be greater than the fourth distance L2b(e.g., the smaller distance among the third distance L2aand the fourth distance L2b). From a planar viewpoint, the fifth area of the third string selection line (SSL3or SSL3_1ofFIG.1) on one side of the third cutting line S3, and the sixth area of the third string selection line (SSL3or SSL3_2ofFIG.1) on the other side of the third cutting line S3may be larger than the fourth area of the second string selection line (SSL2or SSL2_2ofFIG.1) on the other side of the second cutting line S2, respectively.

In an implementation, the third cutting line S3may not cut the first string selection line SSL1and may not cut the second string selection line SSL2. In an implementation, as shown inFIG.3, the lower surface of the third cutting line S3may be higher (e.g., farther from the substrate100in the third direction X) than or the same as the upper surface of the second string selection line SSL2.

In an implementation, a plurality of channel structures may be between the third cutting line S3and the first cutting region WLC1, and between the third cutting line S3and the second cutting region WLC2. In an implementation, as shown inFIGS.2and3, the first to fourth channel structures C1to C4may be between the third cutting line S3and the first cutting region WLC1, and the fifth to eighth channel structures C5to C8may be between the third cutting line S3and the second cutting region WLC2.

In an implementation, the first to third cutting lines S1to S3may not overlap each other from a planar viewpoint (e.g., when viewed in plan view and/or along the third direction X). In an implementation, the third cutting line S3may be separated from the first cutting line S1in the first direction X, and the second cutting line S2may be separated from the third cutting line S3in the first direction X.

In the nonvolatile memory device according to some embodiments, any string selection line may not be cut by the plurality of cutting lines. In an implementation, the first string selection line SSL1may be cut only by a single cutting line (the first cutting line S1), the second string selection line SSL2may be cut only by a single cutting line (the second cutting line S2), and the third string selection line SSL3may be cut only by a single cutting line (the third cutting line S3).

The first to third cutting lines S1to S3may include an insulating material. The first to third cutting lines S1to S3may each independently include, e.g., silicon oxide, silicon nitride, or silicon oxynitride.

The plurality of bit lines BL1and BL2may be connected to the plurality of channel structures C1to C8. In an implementation, each of the bit lines BL1and BL2may be connected to corresponding ones of the channel structures C1to C8through the bit line contact170. For example, the bit line contact170may penetrate the second interlayer insulating film160on the mold structure MS to electrically connect each of the channel structures C1to C8and a corresponding one of the bit lines BL1and BL2.

In an implementation, each of the bit lines BL1and BL2may intersect the first to third cutting lines S1to S3. In an implementation, each of the bit lines BL1and BL2may extend (e.g., lengthwise) in the first direction X.

In an implementation, each of the bit lines BL1and BL2may be connected to a plurality of channel structures arranged in a line. In an implementation, the first bit line BL1may be connected to the first, third, fifth, and seventh channel structures C1, C3, C5, and C7, and the second bit line BL2may be connected to the second, fourth, sixth, and eighth channel structures C2, C4, C6, and C8.

Various shapes of the first to third cutting lines S1to S3according to some embodiments will be described below with reference toFIGS.5A to5E. AlthoughFIGS.5A to5Eshow only the first cutting line S1, the second cutting line S2and the third cutting line S3may have the same shape.

Referring toFIG.5A, in some embodiments, the lower (e.g., substrate100-facing) surface of the first cutting line S1may be lower (e.g., closer to the substrate100in the third direction Z) than the lower surface of the first string selection line SSL1. In an implementation, the first cutting line S1may penetrate the insulating pattern110below the first string selection line SSL1. In an implementation, the lower surface of the first cutting line S1may be in contact with the upper surface of the gate electrode (e.g., a word line WLn) below the first string selection line SSL1.

Referring toFIG.5B, in some embodiments, the first cutting line S1may have a tapered shape. For example, the width of the first cutting line S1may increase as it goes away from the word line WLn below the first string selection line SSL1(e.g., the width of the first cutting line S1as measured in the first direction X may increase from a substrate100-facing surface thereof in the third direction Z). This may be due to the characteristics of the etching process for forming the first cutting line S1.

Referring toFIG.5C, in some embodiments, the lower surface of the first cutting line S1may be higher than the lower surface of the insulating pattern110below the first string selection line SSL1. In an implementation, the lower part of the first cutting line S1may be embedded in the insulating pattern110below the first string selection line SSL1. In an implementation, the lower surface of the first cutting line S1may not contact the upper surface of the gate electrode (e.g., the word line WLn) below the first string selection line SSL1.

Referring toFIG.5D, in some embodiments, the lower surface of the first cutting line S1may be on the same plane as the lower surface of the first string selection line SSL1. In an implementation, the lower surface of the first cutting line S1may be in contact with the upper surface of the insulating pattern110below the first string selection line SSL1.

Referring toFIG.5E, in some embodiments, the upper surface of the first cutting line S1may be higher than the upper surface of the first string selection line SSL1. In an implementation, the first cutting line S1may penetrate the insulating pattern110on the first string selection line SSL1(e.g., the insulating pattern110that is between the first string selection line SSL1and the second string selection line SSL2). In an implementation, the upper surface of the first cutting line S1may contact the lower surface of the gate electrode (e.g., the second string selection line SSL2) on the first string selection line SSL1.

The nonvolatile memory device according to some embodiments may help improve the degree of integration, using a plurality of string selection lines SSL1to SSL3and a plurality of cutting lines S1to S3for cutting them, even without an additional bit line. The electrical resistance per unit thickness of the string selection line may increase, as the string selection line is cut from a planar viewpoint. The electrical resistance per unit thickness may further increase in the string selection line (or the sub-string selection line) on the upper part due to the channel structure having a tapered shape.

In an implementation, as shown inFIG.6, the first channel structure C1may penetrate the first to third string selection lines SSL1to SSL3. The width of the first channel structure C1may be narrowed downward (e.g., with increasing proximity to the substrate100in the third direction Z).

In an implementation, a diameter DI1of the first channel structure C1intersecting the first string selection line SSL1may be smaller than a diameter DI2of the first channel structure C1intersecting the second string selection line SSL2. In an implementation, a diameter DI2of the first channel structure C1intersecting the second string selection line SSL2may be smaller than a diameter DI3of the first channel structure C1intersecting the third string selection line SSL3.

From a planar viewpoint, the area of the string selection lines may decrease upward (e.g., with increasing distance from the substrate100in the third direction Z). In an implementation, as illustrated inFIG.6, an area of the upper surface US2of the second string selection line SSL2may be smaller than an area of the upper surface US1of the first string selection line SSL1. In an implementation, as illustrated inFIG.6, an area of the upper surface US3of the third string selection line SSL3may be smaller than an area of the upper surface US2of the second string selection line SSL2. The electrical resistance per unit thickness may further increase in the string selection line (or the sub-string selection line) at the upper part of the device (e.g., distal to the substrate100in the third direction Z).

In the nonvolatile memory device according to some embodiments, by maintaining a large area of the string selection line (or the sub-string selection line) at the upper part of the device, even when the string selection line is cut by the cutting lines, it is possible to help improve the operating performance and reliability of the nonvolatile memory device.

In an implementation, as described above, the third string selection line SSL3in the upper part may be cut by the third cutting line S3. The third difference between the fifth distance L3aand the sixth distance L3bmay be smaller than the first difference between the first distance L1aand the second distance L1b, and smaller than the second different between the third distance L2aand the fourth distance L2b. As a result, the area of the third string selection line SSL3at sides of the third cutting line S3may be kept wide. In an implementation, from a planar viewpoint, the first area of the third string selection line (SSL3or SSL3_1ofFIG.1) on one side of the third cutting line S3, and the second area of the third string selection line (SSL3or SSL3_2ofFIG.1) on the other side of the third cutting line S3may be kept wide.

As a result, a nonvolatile memory device in which the electrical resistance per unit thickness of the string selection line (or the sub-string selection line) in the upper part may be improved, and operating performance and reliability are improved may be provided.

FIG.7is a cross-sectional view of a nonvolatile memory device according to some embodiments. For convenience of explanation, repeated parts of contents described above usingFIGS.1to6may be briefly described or omitted.

Referring toFIG.7, in the nonvolatile memory device according to some embodiments, the mold structure MS may further include a dummy word line DM.

The dummy word line DM may be between, e.g., the uppermost word line WLn and the first string selection line SSL1.

In an implementation, the first cutting line S1may cut the dummy word line DM, the second cutting line S2may cut the first string selection line SSL1, and the third cutting line S3may cut the second string selection line SSL2.

In an implementation, the third difference between the fifth distance L3aand the sixth distance L3bmay be smaller than the first difference between the first distance L1aand the second distance L1b. In an implementation, the third difference between the fifth distance L3aand the sixth distance L3bmay be smaller than the second difference between the third distance L2aand the fourth distance L2b. In an implementation, from a planer viewpoint, the third cutting line S3may be between the first cutting line S1and the second cutting line S2.

In an implementation, the second string selection line SSL2may be a gate electrode at the uppermost part of a plurality of gate electrodes (GSL, WL1to WLn, DM, SSL1, and SSL2).

FIG.8is a layout diagram of a nonvolatile memory device according to some embodiments.FIGS.9and10are various cross-sectional views taken along a line B-B ofFIG.8. For convenience of explanation, repeated parts of contents described above usingFIGS.1to7may be briefly described or omitted.

Referring toFIGS.8and9, the nonvolatile memory device according to some embodiments may further include dummy channel structures D1to D3.

The dummy channel structures D1to D3may penetrate the mold structure MS and intersect the respective gate electrodes (GSL, WL1to WLn, and SSL1to SSL3). In an implementation, the dummy channel structures D1to D3may have the same shape as that of the channel structures C1to C16. In an implementation, the dummy channel structures D1to D3may have a pillar shape extending in the third direction Z. In an implementation, the dummy channel structures D1to D3may include a semiconductor pattern130and an information storage film132.

In an implementation, the dummy channel structures D1to D3may cross the first to third cutting lines S1to S3. In an implementation, the dummy channel structures D1to D3may include a first dummy channel structure D1that crosses the first cutting line S1, a second dummy channel structure D2that crosses the third cutting line SS3, and a third dummy channel structure D3that crosses the second cutting line S2.

In an implementation, as illustrated in the drawing, each of the three dummy channel structures D1to D3may cross one of the first to third cutting lines S1to S3. In an implementation, at least one of the first to third dummy channel structures D1to D3may be omitted.

In an implementation, the plurality of channel structures C1to C8may include first to sixteenth channel structures C1to C16sequentially and laterally arranged along the first direction X between the first cutting region WLC1and the second cutting region WLC2.

In an implementation, the device may include the first to sixteenth channel structures C1to C16, and the first to third dummy channel structures D1to D3arranged along the first direction X in a zigzag shape.

In an implementation, first to fourth channel structures C1to C4may be between the first cutting line S1and the first cutting region WLC1, and the fifth to sixteenth channel structures C5to C16may be between the first cutting line S1and the second cutting region WLC2.

In an implementation, first to twelfth channel structures C1to C12may be between the second cutting line S2and the first cutting region WL1, and thirteenth to sixteenth channel structures C13to C16may be between the second cutting line S2and the second cutting region WLC2.

In an implementation, first to eighth channel structures C1to C8may be between the third cutting line S3and the first cutting region WLC1, and ninth to sixteenth channel structures C9to C16may be between the third cutting line S3and the second cutting region WLC2.

As more channel structures C1to C16are between the first cutting region WLC1and the second cutting region WLC2, a larger number of bit lines may be on the channel structures C1to C16. In an implementation, the bit lines BL1to BL4ofFIG.8may be larger than the bit lines BL1and BL2ofFIG.2.

In an implementation, each of the bit lines BL1to BL4may be connected to a plurality of channel structures arranged in a row. In an implementation, the first bit line BL1may be connected to the first, sixth, ninth and fourteenth channel structures C1, C6, C9and C14. The second bit line BL2may be connected to the third, eighth, eleventh and sixteenth channel structures C3, C8, C11and C16. The third bit line BL3may be connected to the second, fifth, tenth and thirteenth channel structures C2, C5, C10and C13. The fourth bit line BL4may be connected to the fourth, seventh, twelfth and fifteenth channel structures C4, C7, C12and C15.

In an implementation, the dummy channel structures D1to D3may not be connected to the plurality of bit lines BL1to BL4. In an implementation, the bit line contact170may not be on the dummy channel structures D1to D3.

Referring toFIGS.8and10, in the nonvolatile memory device according to some embodiments, the first to third cutting lines S1to S3may cut a plurality of strings, respectively.

In an implementation, the first string selection line SSL1may include a first lower string selection line SSL1aand a first upper string selection line SSL1b. The first lower string selection line SSL1aand the first upper string selection line SSL1bmay be sequentially stacked on the uppermost word line WLn. In an implementation, the first cutting line S1may cut both the first lower string selection line SSL1aand the first upper string selection line SSL1b.

In an implementation, the second string selection line SSL2may include a second lower string selection line SSL2aand a second upper string selection line SSL2b. The second lower string selection line SSL2aand the second upper string selection line SSL2bmay be sequentially stacked on the first string selection line SSL1. In an implementation, the second cutting line S2may cut both the second lower string selection line SSL2aand the second upper string selection line SSL2b.

In an implementation, the third string selection line SSL3may include a third lower string selection line SSL3aand a third upper string selection line SSL3b. The third lower string selection line SSL3aand the third upper string selection line SSL3bmay be sequentially stacked on the second string selection line SSL2. In an implementation, the third cutting line S3may cut both the third lower string selection line SSL3aand the third upper string selection line SSL3b.

In an implementation, each of the first to third cutting lines S1to S3may cut two string selection lines. In an implementation, each of the first to third cutting lines S1to S3may, e.g., cut three or more string selection lines.

In an implementation, all of the first to third cutting lines S1to S3may cut the two string selection lines. In an implementation, at least one of the first to third cutting lines S1to S3may cut only one string selection line.

FIG.11is a layout diagram of the nonvolatile memory device according to some embodiments. For convenience of explanation, repeated parts of contents described above usingFIGS.1to10may be briefly described or omitted.

Referring toFIG.11, in the nonvolatile memory device according to some embodiments, each of the first to third cutting lines S1to S3may have a zigzag shape from a planar viewpoint.

In an implementation, the first cutting line S1may meanderingly cross between the fourth channel structure C4and the fifth channel structure C5. In an implementation, the second cutting line S2may meanderingly cross between the twelfth channel structure C12and the thirteenth channel structure C13. In an implementation, the third cutting line S3may meanderingly cross between the eighth channel structure C8and the ninth channel structure C9.

In an implementation, each of the first to third cutting lines S1to S3may extend lengthwise along the second direction Y in a zigzag shape from a planar viewpoint.

In an implementation, all of the first to third cutting lines S1to S3may have a zigzag shape. In an implementation, at least one of the first to third cutting lines S1to S3may extend in a straight line along the second direction Y.

In this embodiment, the dummy channel structure (e.g., D1, D2, and D3ofFIG.8) may not be formed between the first cutting region WLC1and the second cutting region WLC2, and a nonvolatile memory device with further improved degree of integration may be provided.

FIG.12is a layout diagram of a nonvolatile memory device according to some embodiments.FIGS.13and14are various cross-sectional views taken along a line C-C ofFIG.12. For convenience of explanation, repeated parts of contents described above usingFIGS.1to11may be briefly described or omitted.

Referring toFIGS.12and13, the nonvolatile memory device according to some embodiments may further include a fourth string selection line SSL4and a fourth cutting line S4.

The fourth string selection line SSL4may be on the third string selection line SSL3. In an implementation, the fourth string selection line SSL4may be a gate electrode at the uppermost part among the plurality of gate electrodes (GSL, WL1to WLn, and SSL1to SSL4).

The fourth cutting line S4may extend, e.g., in the second direction Y to cut the fourth string selection line SSL4.

The fourth cutting line S4may re-separate the fourth string selection line SSL4separated by the first cutting region WLC1and the second cutting region WLC2. The fourth cutting line S4may be separated from the first cutting region WLC1by a seventh distance L4a, and may be separated from the second cutting region WLC2by an eighth distance L4b(e.g., in the first direction X).

In an implementation, the fifth distance L3aand the sixth distance L3bmay be different from each other. In an implementation, the third difference between the fifth distance L3aand the sixth distance L3bmay not be zero. In an implementation, as shown inFIG.13, the sixth distance L3bmay be smaller than the fifth distance L3a.

In an implementation, the seventh distance L4aand the eighth distance L4bmay be different from each other. In an implementation, the fourth difference between the seventh distance L4aand the eighth pattern L4bmay not be zero. In an implementation, as shown inFIG.13, the eighth distance L4bmay be greater than the seventh distance L4a.

In an implementation, the fourth difference between the seventh distance L4aand the eighth distance L4bmay be smaller than the first difference between the first distance L1aand the second distance L1b, and smaller than the second difference between the third distance L2aand the fourth distance L2b. In an implementation, from a planar viewpoint, the fourth cutting line S4may be between the first cutting line S1and the second cutting line S2.

In an implementation, the fourth difference between the seventh distance L4aand the eighth path L4bmay be the same as the third difference between the fifth distance L3aand the sixth distance L3b. In an implementation, the seventh distance L4amay be the same as the sixth distance L3b, and the eighth distance L4bmay be the same as the fifth distance L3a.

Referring toFIGS.12and14, in the nonvolatile memory device according to some embodiments, the second distance L1bmay be smaller than the first distance L1a, and the fourth distance L2bmay be greater than the third distance L2a.

In an implementation, from a planar viewpoint, the positions of the first cutting line S1and the second cutting line S2ofFIG.14may be in the form in which the positions of the first cutting line S1and the second cutting line S2ofFIG.13are changed from each other.

In an implementation, the fourth difference between the seventh distance L4aand the eighth distance L4bmay be smaller than the first difference between the first distance L1aand the second distance L1b, and smaller than the third difference between the fifth distance L3aand the sixth distance L3b. In an implementation, from a planar viewpoint, the fourth cutting line S4may be between the first cutting line S1and the second cutting line S2.

FIG.15is a layout diagram of a nonvolatile memory device according to some embodiments.FIGS.16and17are various cross-sectional views taken along a line D-D ofFIG.15. For convenience of explanation, repeated parts of contents described above usingFIGS.1to14may be briefly described or omitted.

Referring toFIGS.15and16, the nonvolatile memory device according to some embodiments may further include a fifth string selection line SSL5and a fifth cutting line S5.

The fifth string selection line SSL5may be on the fourth string selection line SSL4. In an implementation, the fifth string selection line SSL5may be a gate electrode at the uppermost part among the plurality of gate electrodes (GSL, WL1to WLn, and SSL1to SSL5).

The fifth cutting line S5may extend, e.g., in the second direction Y to cut the fifth string selection line SSL5.

The fifth cutting line S5may re-separate the fifth string selection line SSL5separated by the first cutting region WLC1and the second cutting region WLC2. The fifth cutting line S5may be separated from the first cutting region WLC1by a ninth distance L5a, and may be separated from the second cutting region WLC2by a tenth distance L5b(e.g., in the first direction X).

In an implementation, a fifth difference between the ninth distance L5aand the tenth distance L5bmay be smaller than the first difference between the first distance L1aand the second distance L1b, and smaller than the second difference between the third distance L2aand the fourth distance L2b. In an implementation, the fifth difference between the ninth distance L5aand the tenth distance L5bmay be smaller than the third difference between the fifth distance L3aand the sixth distance L3b, and smaller than the fourth difference between the seventh distance L4aand the eighth distance L4b.

In an implementation, the ninth distance L5aand the tenth distance L5bmay be the same. In an implementation, the fifth difference between the ninth distance L5aand the tenth distance L5bmay be zero.

Referring toFIGS.15and17, in the nonvolatile memory device according to some embodiments, the sixth distance L3bmay be smaller than the fifth distance L3a,and the eighth distance L4bmay be greater than the seventh distance L4a.

In an implementation, from a planar viewpoint, the positions of the third cutting line S3and the fourth cutting line S4ofFIG.17may be in the form in which the positions of the third cutting line S3and the fourth cutting line S4ofFIG.16are changed from each other.

In an implementation, the fifth difference between the ninth distance L5aand the tenth distance L5bmay be smaller than the third difference between the fifth distance L3aand the sixth distance L3b, and smaller than the fourth difference between the seventh distance L4aand the eighth distance L4b.

Hereinafter, a method for fabricating a nonvolatile memory device according to some embodiments will be described with reference toFIGS.2,3, and18to26.

FIGS.18to26are sectional view of stages in a method for fabricating the nonvolatile memory device according to some embodiments. For convenience of explanation, repeated parts of contents described above usingFIGS.1to17may be briefly described or omitted. For reference,FIGS.18to26are cross-sectional views taken along a line A-A ofFIG.2.

Referring toFIG.18, a plurality of first sacrificial patterns115, a plurality of insulating patterns110, and a second sacrificial pattern210may be formed on the substrate100.

Each first sacrificial pattern115may be alternately stacked with each insulating pattern110.

The second sacrificial pattern210may be stacked on the plurality of first sacrificial patterns115and the plurality of insulating patterns110. In an implementation, the second sacrificial pattern210may be formed on the uppermost first sacrificial pattern115. In an implementation, the second sacrificial pattern210may be spaced apart from the uppermost first sacrificial pattern115by the insulating pattern110.

Referring toFIG.19, the second sacrificial pattern210may be cut.

In an implementation, a trench210T for cutting the second sacrificial pattern210may be formed in the second sacrificial pattern210. The trench210T may be formed, e.g., by etching a part of the second sacrificial pattern210.

In an implementation, the trench210T may extend in the second direction Y. In an implementation, the bottom surface of the trench210T may be lower (e.g., closer to the substrate100in the third direction Z) than the bottom surface of the second sacrificial pattern210. In an implementation, the trench210T may penetrate the insulating pattern110below the second sacrificial pattern210and expose the upper surface of the first sacrificial pattern115.

Referring toFIG.20, a first cutting line S1(for cutting the second sacrificial pattern210) may be formed.

In an implementation, an insulating material for filling the trench210T may be formed on the second sacrificial pattern210, and then, a planarization process may be performed. Therefore, a first cutting line S1filling the trench210T may be formed. The insulating material may include, e.g., silicon oxide, silicon nitride, or silicon oxynitride.

Referring toFIG.21, a third sacrificial pattern220, a second cutting line S2, a fourth sacrificial pattern230and the third cutting line S3may be formed on the second sacrificial pattern210and the first cutting line S1.

Formation of the third sacrificial pattern220, the second cutting line S2, the fourth sacrificial pattern230, and the third cutting line S3may be similar to the formation of the second sacrificial pattern210and the first cutting line S1, and a repeated detailed description thereof may be omitted.

Referring toFIG.22, a plurality of channel structures C1to C8that penetrates the first to fourth sacrificial patterns115,210,220and230and the plurality of insulating patterns110and connected to the substrate100may be formed.

In an implementation, a penetration hole that penetrates the first to fourth sacrificial patterns115,210,220and230and the plurality of insulating patterns110and that exposes the substrate100may be formed. Subsequently, an information storage film132and a semiconductor pattern130sequentially stacked in the penetration hole may be formed.

In an implementation, a filling insulating pattern134may be further formed on the semiconductor pattern130. In an implementation, a channel pad136may be further formed on the semiconductor pattern130.

Referring toFIG.23, a first cutting region WLC1and a second cutting region WLC2may be formed in the first to fourth sacrificial patterns115,210,220and230and the plurality of insulating patterns110.

The first cutting region WLC1and the second cutting region WLC2may cut the first to fourth sacrificial patterns115,210,220and230and the plurality of insulating patterns110.

In an implementation, each of the first cutting region WLC1and the second cutting region WLC2may be formed to extend side by side along the second direction Y.

In an implementation, an impurity region105may be formed in the substrate100exposed during forming of the first cutting region WLC1and the second cutting region WLC2.

Referring toFIG.24, the first to fourth sacrificial patterns115,210,220and230exposed by the first cutting region WLC1and the second cutting region WLC2may be removed.

The removal of the first to fourth sacrificial patterns115,210,220and230may be performed by, e.g., an anisotropic etching process.

Referring toFIG.25, a plurality of gate electrodes (GSL, WL1to WLn, and SSL1to SSL3) may be formed on the substrate100.

The plurality of gate electrodes (GSL, WL1to WLn, and SSL1to SSL3) may be formed in a region in which the first to fourth sacrificial patterns115,210,220and230have been removed. In an implementation, the first to fourth sacrificial patterns115,210,220and230may be replaced with a plurality of gate electrodes (GSL, WL1to WLn, and SSL1to SSL3).

The first cutting line S1may cut the first string selection line SSL1, the second cutting line S2may cut the second string selection line SSL2, and the third cutting line S3may cut the third string selection line SSL3.

Referring toFIG.26, the cutting structure150may be formed in the first cutting region WLC1and the second cutting region WLC2.

In an implementation, the cutting structure150may include a plug pattern152and a spacer154.

Subsequently, referring toFIG.3, a plurality of bit lines BL1and BL2may be formed on the mold structure MS.

The plurality of bit lines BL1and BL2may be formed to be connected to the plurality of channel structures C1to C8. In an implementation, the second interlayer insulating film160may be formed on the mold structure MS. Subsequently, a bit line contact170that penetrates the second interlayer insulating film160to electrically connect the respective channel structures CS1to CS6and the respective bit lines BL1and BL2may be formed.

One or more embodiments may provide a nonvolatile memory device including a plurality of string selection lines.

One or more embodiments may provide a nonvolatile memory device with improved operating performance and reliability.

One or more embodiments may provide a method for fabricating a nonvolatile memory device with improved operating performance and reliability.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.