Patent ID: 12198722

DETAILED DESCRIPTION

The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

The embodiments described below are not intended to limit the disclosure to the precise form disclosed, nor are they intended to be exhaustive. Rather, the embodiment is presented to provide a description so that others skilled in the art may utilize its teachings. Technology continues to develop, and elements of the described and disclosed embodiments may be replaced by improved and enhanced items, however the teaching of the present disclosure inherently discloses elements used in embodiments incorporating technology available at the time of this disclosure.

Disk drives typically employ a multi-phase spindle motor (e.g., a 3-phase spindle motor) for spinning a disk while a head writes data to and reads data from the disk. The head is connected to a distal end of an actuator arm which is rotated about a pivot by a voice coil motor (VCM) in order to actuate the head radially over the disk to access radially spaced, concentric tracks. The disk drive receives power from a host computer (e.g., host25inFIG.2A), including a first power supply (e.g., 12V supply) for powering the spindle motor210and VCM20, and a second power supply (e.g., 5V supply) for powering the integrated circuits that control the operation of the disk drive. In some examples, the amount of current that can be drawn by the disk drive from either supply may be limited so as not to interfere with the proper operation of the host computer25.

The disk(s)16, such as disks16A through16D inFIG.2B, are typically rotated by a spindle motor210at a high speed so that an air bearing forms between the head18and the disk surface17. In some cases, a commutation controller (e.g., of the control circuitry22) applies a drive signal to the windings211(e.g., windings211-a,211-b,211-c) of the spindle motor210using a particular commutation sequence in order to generate a rotating magnetic field that causes the spindle motor210to rotate. In some cases, the commutation of the windings can be controlled by measuring a zero-crossing frequency of a back electromotive force (BEMF) voltage generated by the windings211of the spindle motor210, although other techniques are also contemplated in different embodiments. For instance, in some cases, a BEMF voltage generated by the windings of the spindle motor210may be processed in order to drive the commutation sequence of the commutation controller. In another example, the commutation sequence may be driven based on data recorded on the disk(s)16, such as servo sectors321through32N that define the servo tracks.

Broadly, aspects of the present disclosure are directed to connecting two or more spindle drivers of a data storage device in parallel to provide higher spin up and spin down currents, which in turn facilitates faster spin and spin down times, as compared to the prior art. Some aspects of the present disclosure are also directed to optimizing spindle motor efficiency by employing a plurality of spindle drivers in parallel, which helps reduce the current drawn by each driver during normal operation of the disk drive, as described in further detail below. For example, when two or more spindle drivers are coupled in parallel to the windings of the spindle motor, the overall/cumulative resistance coupled to the windings is reduced (i.e., as compared to the case when a single spindle driver is connected), which also reduces the current drawn by the spindle drivers, and thereby helps enhance power efficiency.

In some cases, aspects of the present disclosure can be implemented in firmware (FW), as described below in relation toFIG.3. Alternatively, aspects of the present disclosure can also be implemented using hardware (HW) modifications, further described in relation toFIG.4. In yet other cases, spin up and spin down times may be enhanced through a combination of FW and HW modifications. While generally described in relation to enhancing spin and spin down times, aspects of the present disclosure can also help enhance power efficiency when the spindle motor is “at speed”, i.e., rotating at a target RPM, by driving the plurality of spindle drivers in parallel.

Turning now toFIGS.2A and2B, which illustrate conceptual block diagrams of a top view and a side view of a data storage device in the form of a disk drive15, in accordance with aspects of the present disclosure. Disk drive15comprises control circuitry22, an actuator assembly19, and a plurality of hard disks16A,16B,16C,16D (“hard disks16,” “disks16”).

FIG.2Cdepicts a flowchart for an example method80that control circuitry22of disk drive15may perform or execute in controlling the operations of disk drive15, including the operations of heads18(e.g., heads18A-18H) disposed on actuator assembly19, the operations of the spindle motor210, and/or the operations of spindle drivers230-aand230-b, in accordance with aspects of the present disclosure, as further described below.

Each disk (shown as disks16A-D) can have thin film magnetic material on each of the planar surfaces. Each recording surface may comprise a dedicated pair of read and write heads packaged in a slider that is mechanically positioned over the rotating disk by an actuator (e.g., shown as actuator assembly19inFIG.2B). In some examples, the actuator(s) also provide the electrical connections to the components of the slider. The actuator assembly19may also comprise one or more preamps (e.g., read or write preamp) for the heads, write driver, read driver, and fly-height controls.

Actuator assembly19thus comprises heads18and is configured to position the one or more heads18over disk surfaces17of the one or more disks16. Heads18may each comprise write and read elements, configured for writing and reading control features and data to and from a corresponding disk surface17of hard disks16. In some cases, the disk drive15according to various aspects of the disclosure comprises a system on a chip (SoC), where the SoC comprises the electronics and firmware for the disk drive15. The SoC (e.g., SoC350, SoC450) may be used to control the functions of the disk drive15including providing power and/or control signals to the components of the disk drive. In some cases, the SoC may include the control circuitry22. Alternatively, one or more aspects of the control circuitry22may be implemented in or using the SoC.

Actuator assembly19comprises a primary actuator20(e.g., a voice coil motor (“VCM”)) and a number of actuator arms40(e.g., topmost actuator arm40A, as seen in the perspective view ofFIGS.2A and2B). Each of actuator arms40comprises a head18at a distal end thereof (e.g., head18A in topmost actuator arm40A, in the view ofFIGS.2A and2B). Each of actuator arms40is configured to suspend one of heads18in close proximity over a corresponding disk surface17(e.g., head18A suspended by topmost actuator arm40A over topmost corresponding disk surface17A, head18H suspended by lowest actuator arm40H over lowest corresponding disk surface17H). Various examples may include any of a wide variety of other numbers of hard disks and disk surfaces, other numbers of actuator arm assemblies and primary actuators besides the one actuator assembly19and the one primary actuator20in the example ofFIGS.2A and2B, and other numbers of fine actuators on each actuator arm, for example.

FIG.2Aalso depicts servo sectors32(e.g., servo sectors321through32N) written onto disk surfaces17. In some examples, the servo sectors32(or servo wedges32) on a disk drive may be curved, but for sake of illustration, the servo sectors32inFIG.2Ahave been shown with straight lines. In some cases, when manufacturing a disk drive, servo sectors32may be written to disk surfaces17to define a plurality of evenly-spaced, concentric tracks34. As an example, each servo sector32may include a phase lock loop (PLL) field, a servo sync mark (SSM) field, a track identification (TKID) field, a sector ID, and a group of servo bursts (e.g., an alternating pattern of magnetic transitions) that the servo system of the disk drive samples to align the moveable transducer head (e.g., disk head18) with and relative to, a particular track34. Each circumferential track34includes a plurality of embedded servo sectors32utilized in seeking and track following. The plurality of servo sectors32are spaced sequentially around the circumference of a circumferential track34and extend radially outward from the inner diameter (ID) of disk surface17. These embedded servo sectors32contain servo information utilized in seeking and track following and are interspersed between data regions on disk surfaces17. Data is conventionally written in the data regions in a plurality of discrete data sectors. Each data region is typically preceded by a servo sector32. Host25may be a computing device such as a desktop computer, a laptop, a server, a mobile computing device (e.g., smartphone, tablet, Netbook, to name a few non-limiting examples), or any other applicable computing device. Alternatively, host25may be a test computer that performs calibration and testing functions as part of the disk drive manufacturing process

In some examples, the control circuitry22is configured to control the actuation of the primary actuator (i.e., VCM20). Further, the VCM20is configured to actuate the head18over the disk surfaces17. The control circuitry22is further configured to control the spindle motor210via one or more of the spindle drivers230-aand230-b. In some embodiments, the spindle motor210is configured to rotate the disk16. The spindle motor210comprises a plurality of windings, and the control circuitry22(or alternatively, the spindle drivers230-aand/or230-b) is configured to commutate the windings to generate a rotating magnetic field that causes the spindle motor210to rotate. In this example, the spindle motor210comprises three windings211-a,211-b, and211-c, each coupled to the first and second spindle drivers230-aand230-b. In this example, the spindle drivers230-aand230-bare coupled in parallel to the windings211of the spindle motor210.

As seen in method80inFIG.2C, the control circuitry22is configured to detect a back electromotive force (BEMF) signal corresponding to one or more of a velocity and a position of the spindle motor (operation82). At operation84, the control circuitry22is further configured to control, based at least in part on detecting the BEMF signal, the first spindle driver (e.g., spindle driver230-a) and the second spindle driver (e.g., spindle driver230-b). In some cases, controlling the first spindle driver and the second spindle driver comprises commutating, at or near the same time, the windings of the spindle motor using both the first and the second spindle driver (operation86-a). Alternatively, controlling the first spindle driver and the second spindle driver comprises commutating the windings of the spindle motor using the first spindle driver followed by the second spindle driver or vice versa (operation86-b). That is, the control circuitry22is configured to control the first spindle driver and the second spindle driver to simultaneously commutate the windings of the spindle motor during one or more of the spin up routine, the spin down routine, and the at-speed routine (operation86-a) or to sequentially commutate the windings of the spindle motor during one or more of the spin up and spin down routine of the spindle motor (operation86-b). In some embodiments, the first spindle driver230-aand the second spindle driver230-bare coupled in parallel, as further described in relation toFIGS.3and/or4. In some cases, the control circuitry22may also be configured to help reduce power consumption during an ‘at speed’ routine of the spindle motor210, where the reduction in power consumption may be based at least in part on (1) reducing the overall resistance connected to the windings211of the spindle motor210(i.e., overall resistance is reduced when the two or more spindle drivers230are coupled in parallel to the spindle motor windings), and/or (2) reducing the current drawn by the spindle drivers.

In the embodiment ofFIG.2A, the control circuitry22may also process a read signal36emanating from the head18A to demodulate servo data written on the disk (e.g., servo sectors32) to generate a position error signal (PES) representing an error between the actual position of the head and a target position relative to a target track. The control circuitry22may process the PES using a suitable servo control system to generate the control signal38(e.g., a VCM control signal) applied to the VCM20which rotates an actuator arm40about a pivot in order to actuate the head18radially over the disk surface17in a direction that reduces the PES. In one embodiment, the disk drive may also comprise a suitable microactuator, such as a suitable piezoelectric (PZT) element for actuating the head18relative to a suspension, or for actuating a suspension relative to the actuator arm40.

In one embodiment, the servo data (e.g., servo sectors32) read from the disk surface17, i.e., in order to servo the head over the disk during access operations, may be self-written to the disk using the control circuitry22internal to the disk drive. In some examples, a plurality of spiral servo tracks are first written to the disk surface17, and then servo sectors32are written to the disk while servoing on the spiral servo tracks. In order to write the spiral servo tracks to the disk surface17, at least one bootstrap spiral track is first written to the disk without using position feedback from servo data (i.e., the actuator or VCM20is controlled open loop with respect to servo data on the disk). Before writing the bootstrap spiral track, feedforward compensation is generated by evaluating the BEMF voltage generated by the VCM20during a calibration seek (where the BEMF voltage represents an estimated velocity of the VCM). The bootstrap spiral track is then written to the disk using the feed-forward compensation. In some embodiments, the BEMF voltage representing the velocity of the VCM20may be sampled at any suitable sample rate in order to update the feed-forward compensation at any suitable frequency during seek operations.

It should be noted that spindle motor210may also generate a BEMF signal/voltage, which may be sampled to estimate one or more of the position and velocity/speed of the spindle motor210.

FIG.3illustrates a block diagram300of various components of a data storage device, such as data storage device200-ainFIG.2A, according to various aspects of the disclosure. Specifically,FIG.3illustrates a spindle motor310, as well as control circuitry configured for enhancing spin up and spin down times, according to various aspects of the disclosure. Additionally, or alternatively, the control circuitry inFIG.3may be configured to help reduce power consumption during an ‘at speed’ routine for the spindle motor310. The control circuitry may be similar or substantially similar to the control circuitry22described in relation toFIG.2A, and may include the SoC350, the lead PLSI320, and the support PLSI330.

In some cases, a data storage device comprises a spindle motor310for rotating or spinning a disk while a head (e.g., head18A inFIG.2A) writes data to and reads data from the disk. In some cases, the performance of a disk drive may be quantified using a few different performance metrics, some non-limiting examples of which include the spin up time (i.e., the amount of time required for the spindle motor310to spin up the disk to its operating RPM), the spin down time (i.e., amount of time required for the spindle motor310to brake or stop the disk from spinning, or amount of time required for the spindle310to brake the rotating disk from a higher RPM to a lower RPM), and/or the seek time (i.e., amount of time required for the VCM to position the head over a target track). As can be appreciated, a short spin-up period may not only help enhance user experience, but also satisfy the time-out restriction (if any) imposed by the host25.

In some cases, the spindle motor310may be an example of a multi-phase spindle motor comprising a plurality of windings, each winding comprising a first end and a second end, where the second ends of each winding are connected together at a center tap389. In some cases, the data storage device comprises a plurality of spindle drivers, each associated with a single power large scale integrated circuit (PLSI). For example, the data storage device shown inFIG.3comprises a lead PLSI320having a first spindle driver330-aand a first serial port311-a, and a support PLSI330having a second spindle driver330-band a second serial port311-c. bThe first spindle driver330-aincludes a first driver control module313-a, and the second spindle driver330-bincludes a second driver control module313-b. In some cases, the first and the second driver control modules313-a,313-bare coupled to a serial port311-cof a system on chip (SoC)350via a respective serial port of a PLSI. In some cases, each spindle driver comprises a plurality of switch pairs (or half-bridge of switches), each switch pair coupled to one of the windings of the spindle motor310, further described below. In some cases, each switch pair comprises a plurality of commutation switches (e.g., field effect transistors (FETs), such as metal-oxide semiconductor field effect transistors or MOSFETs).

As seen inFIG.3, the spindle motor310comprises three windings, i.e., L16, L17, and L18corresponding to three phases. It should be noted, however, that any suitable number of windings may be employed to implement any suitable multi-phase spindle motor, and the number of windings/phases described herein are not intended to be limiting. In the example shown, a first end of each of the windings is coupled to a center-point of one of the commutation switch pairs (i.e., half-bridge of switches) in the spindle driver330-a. For example, a first end of the first winding, L17, is coupled between switches M59and M60. Similarly, a first end of the second winding, L16, is coupled between switches M57and M58, while a first end of the third winding, L18, is coupled between switches M56and M55. In this example, the first end of the winding, L17, is also coupled to a center-point of the switch pair comprising switches M65and M66of the second spindle driver330-b. Additionally, the first end of the winding, L16, is also coupled to a center-point of the switch pair comprising switches M63and M64, and the first end of the winding, L18, is also coupled to a center point of the switch pair comprising switches M61and M62. Furthermore, the second end of each of the windings L16, L17, and L18are connected to a center tap389. In this way, the first spindle driver330-aand the second spindle driver330-bare coupled in parallel to the windings of the spindle motor310.

In some aspects, higher current capabilities (i.e., faster spin up and/or spin down times) and/or more optimal efficiency (i.e., for the same amount of current used) may be achievable by using two spindle drivers in parallel, as compared to the prior art. For instance, spindle run efficiency may be enhanced since the same amount of current can be split between the two spindle drivers330-aand330-b. That is, a reduction in power consumption can be seen when the two spindle drivers330-aand330-bare connected in parallel, as this parallel configuration serves to reduce the overall resistance coupled between the spindle motor310and the SoC350. Additionally, aspects of the present disclosure also enable a higher current capability, as compared to the prior art, during one or more of a spin up, spin down, and/or at speed routine. For instance, if the spindle high side and low side field effect transistor (FET) drivers are limited to 3 amps, a total of 6 amps (e.g., for spin up and/or spin down) may be achievable when the two spindle drivers330-a,330-bare employed in a parallel configuration, in accordance with aspects of the present disclosure.

In some embodiments, the SoC350is configured to drive the spindle motor310via an open loop driving method. In one non-limiting example, the SoC350may command the two spindle drivers330-aand330-bto commutate the windings of the spindle motor310at the same time (e.g., simultaneously through the two SoC serial ports311-a,311-b), or in back-to-back communications (e.g., via one of the serial ports311-aor311-bat a time). In accordance with aspects of the present disclosure, the spin up routine and at speed routine may be open loop, in which case the SoC350is constantly commutating the windings of the spindle motor310through each position based upon the BEMF signal feedback. In some embodiments, the SoC350may send an advance signal through the serial port (e.g., serial port311-aor serial port311-b) into the driver control module (e.g., driver control module313-aof the spindle driver330-a, driver control module313-bof the spindle driver330-b) to commutate to the next profile step in the sine wave. For instance, the firmware (FW) in the SoC350receives the BEMF feedback signal, which allows it to estimate/measure the position and velocity of the spindle motor310. Furthermore, the FW and/or the SoC350may adjust the advance/commutation update frequency to align with the increasing speed of the spindle motor (e.g., during spin up). In some cases, the advancing serves to move the profile through each step of the sine wave (or another profile, such as trapezoidal wave).

In some cases, the SoC350and/or the PLSIs (e.g., lead PLSI320, support PLSI330) are configured to control the switch pairs (e.g., switch pairs M56-M55, M57-M58, M59-M60, etc.) to commutate the windings of the spindle motor310in a two-phase, three-phase, hybrid two-phase/three-phase mode, or any other applicable mode. In some cases, the commutation logic employed by the spindle drivers330-aand/or330-bmay operate in any suitable manner, for instance, by driving the switches as linear amplifiers that apply continuous-time sinusoidal voltages to the windings L16, L17, L18of the spindle motor310. In some other cases, the commutation logic may drive the switches of the spindle drivers330using pulse wide modulation (PWM), such as, but not limited to, a square wave PWM, trapezoidal PWM, or sinusoidal PWM. It should be noted that the commutation logic described herein is not intended to be limiting and any applicable commutation logic known or contemplated in the art may be utilized in different embodiments.

Regardless as to how the windings of the spindle motor310are driven, the SoC350generates the control signal(s)338(e.g., control signal338-a, control signal338-b) so that the windings are commutated at the correct periods, thereby generating the target rotating magnetic field that causes the spindle motor310to rotate. In one embodiment, the control circuitry or SoC350may generate a control signal338that controls the effective amplitude of the driving voltages (continuous or PWM), thereby controlling the speed of the spindle motor310. In some cases, the SoC350provides the control signals338-a,338-bat or near the same time, which causes the spindle drivers330-aand330-bto also commutate the windings of the spindle motor at or near the same time. In this way, the spindle drivers330-aand330-bcan be driven in parallel, which serves to enhance the spin up and/or spin down times, as compared to the prior art. In other cases, the SoC350may provide the control signal338-ato the spindle driver and the control signal338-bto the spindle driver330-bat different times, which causes the windings of the spindle motor to be commutated sequentially, e.g., first by the spindle driver330-afollowed by the spindle driver330-bor vice-versa. In some embodiments, when the first and the second spindle driver are driven in parallel, the control signal338-aand the control signal338-bmay be the same. Alternatively, the first control signal338-amay be different from the second control signal338-b.

In one non-limiting example, the windings (e.g., windings L16, L17, L18) of the spindle motor310are connected to a BEMF detector (not shown) which detects threshold crossings (e.g., zero crossings) in the BEMF voltage generated by the windings with respect to the center tap389. In some circumstances, the BEMF voltage is distorted when current is flowing through the windings. In such cases, one or more of the spindle drivers330-aand330-bsupplies a signal to the BEMF detector identifying the “open” winding generating a valid BEMF signal. At each BEMF threshold crossing, the BEMF detector toggles a signal to generate a sin wave signal, a square wave signal, or any other applicable signal. The frequency of the BEMF threshold crossings and thus the frequency of the signal (e.g., square wave signal, sin wave signal) represent the speed of the spindle motor310. In some embodiments, one or more of the SoC350and/or the driver control modules (e.g., driver control module313-aof the lead PLSI320) evaluates the signal (e.g., square wave signal) and adjusts the PWM signal in order to control the speed of the spindle motor310. In some other cases, the spindle driver(s)330comprise suitable circuitry for generating the PWM signal internally in response to a speed error signal generated by the control circuitry22. In some embodiments, the spindle driver(s)330may sense the current flowing through the windings of the spindle motor310and use current feedback to generate the PWM signal.

FIG.4illustrates another block diagram400of various components of a data storage device, according to various aspects of the disclosure. Specifically,FIG.4illustrates a spindle motor410, as well as control circuitry configured for enhancing spin up and spin down times, according to various aspects of the disclosure. Additionally, or alternatively, the control circuitry inFIG.4may be configured to help reduce power consumption during an ‘at speed’ routine for the spindle motor410. The data storage device shown and described in relation toFIG.4implements one or more aspects of the data storage devices described herein, including at least in relation toFIGS.2A and3.

In some cases, the spindle motor410may be an example of a multi-phase spindle motor comprising a plurality of windings, each winding comprising a first end and a second end, where the second ends of each winding are connected together at a center tap489. In some cases, the data storage device comprises a plurality of spindle drivers, each associated with one power large scale integrated circuit (PLSI). For example, the data storage device shown inFIG.4comprises a lead PLSI420having a first spindle driver430-aand a first serial port411-a, and a support PLSI430having a second spindle driver430-band a second serial port411-b. The first spindle driver430-aincludes a first driver control module413-a, and the second spindle driver430-bincludes a second driver control module413-b. In some cases, the first and the second driver control modules413-a,413-bare coupled to a serial port411-cof a system on chip (SoC)450via a respective serial port411of a PLSI. In some cases, each spindle driver430comprises a plurality of switch pairs, each switch pair coupled to one of the windings of the spindle motor410, further described below. In some cases, each switch pair comprises a plurality of commutation switches (e.g., field effect transistors or FETs, such as MOSFETs).

As shown, the spindle motor410comprises three windings, i.e., L14, L13, and L15corresponding to three phases. It should be noted, however, that any suitable number of windings may be employed to implement any suitable multi-phase spindle motor, and the number of windings/phases described herein are not intended to be limiting. In the example shown, a first end of each of the windings is coupled to a center-point of one of the commutation switch pairs in the spindle driver430-a. For example, a first end of the winding, L14, is coupled between switches M47and M48; a first end of the winding, L13, is coupled between switches M45and M46; and a first end of the winding, L15, is coupled between switches M43and M44.

In this example, the first end of the winding, L14, is also coupled to a center-point of the switch pair comprising switches M53and M54of the second spindle driver430-b. Additionally, the first end of the winding, L15, is coupled to a center-point of the switch pair comprising switches M49and M50; and the first end of the winding, L13, is coupled to a center point of the switch pair comprising switches M51and M52. Furthermore, the second end of each of the windings L13, L14, and L15are connected to a center tap489, as shown inFIG.4. In this way, the first spindle driver430-aand the second spindle driver430-bare connected in parallel to the windings of the spindle motor410.

Some aspects of the present disclosure can be implemented using one or more hardware (HW) modifications, as further described below. In some embodiments, a plurality of pins may be added to both the lead PLSI420and the support PLSI440. In the example shown, three pins434are added to the lead PLSI420and three pins444are added to the support PLSI440. As seen inFIG.4, the pins434of the lead PLSI are connected (or coupled) to the driver control module413-aof the lead PLSI420. Furthermore, the pins434of the lead PLSI420are also coupled to the pins444of the support PLSI440using one or more wire connections (e.g., flex cables414). In some aspects, the pins434and pins444of the lead PLSI420and the support PLSI440, respectively, are used to electrically, communicatively, and/or logically couple the driver control modules413-aand413-b. In the example shown inFIG.4, one pin is provided for each switch pair of the lead and support PLSIs. It should be noted, however, that the number of pins added to each of the lead PLSI and the support PLSI440are not intended to be limiting. For instance, in some embodiments, more than three pins may be added to each of the lead PLSI420and the support PLSI440. In one non-limiting example, six pins may be added to each of the lead and the support PLSI, for instance, one pin for each of the switches M43, M44, M45, M46, M47, M48of the lead PLSI420and one pin for each of the switches M49, M50, M51, M52, M53, and M54of the support PLSI440.

In some cases, when the PLSI device is configured for support operation, such as support PLSI440, the pins444may serve as the input for the spindle control FETs (e.g., FET or switches M49through M54). Additionally, when the PLSI device is configured for lead operation, such as lead PLSI420, the pins434may serve as the output for the support PLSI440. In some embodiments, instead of having to commutate the lead and support spindle drivers in a sequential manner from the SoC serial port, the lead spindle driver may automatically drive the support spindle driver via control signals such that the support spindle driver mirrors (or, is in parallel with) the lead spindle driver.

In one non-limiting example, for the 3-pin configuration shown inFIG.4, each pin corresponds to an output (e.g., SPA, SPB, SPC) of one of the half bridge of commutation switches, where each output is connected to one of the windings (e.g., phase A winding, phase B winding, phase C winding) of the spindle motor410. In other words, each pin corresponds to one of the windings (e.g., L13, L14, L15) or phases (e.g., phase A, phase B, phase C) of the spindle motor410. In some cases, each half bridge of commutation switches may be set to one of three (3) conditions, where each condition further corresponds to a state of each pin. For example, a first condition may comprise the high side FET=ON, low side FET=OFF, a second condition may comprise the high side FET=OFF, low side FET=ON, and a third condition may comprise both the high side and low side FETs being tri-stated. Alternatively, the third condition may comprise both the high side and low side FETs being in the OFF state.

In some cases, a high signal (e.g., a control signal set to a high value) may be used to instruct the spindle driver control module413-ato drive the high side FET (e.g., M44, M45, M47) of a corresponding spindle/winding (e.g., SPA, SPB, or SPC) to an ON state, and the low side FET (e.g., M43, M46, M48) to an OFF state. Furthermore, a low signal (e.g., a control signal set to a low value) may be used to instruct the spindle driver control413-ato drive the high side FET (e.g., M44, M45, M47) of a corresponding spindle/winding (e.g., SPA, SPB, or SPC) to an OFF state, and the low side FET (e.g., M43, M46, M48) to an ON state. In some embodiments, the SoC450provides an indication of these high and low signals to the driver control module413-aof the lead PLSI420via the serial ports411-cand411-a. In some cases, a “mid” signal (e.g., control signal supply level/2, control signal at VIO/2) may be used to instruct the spindle driver control413-ato tri-state the SPx driver, where SPx corresponds to one or more of SPA, SPB, and SPC. As an example, if the control signal supply level can be varied from a high level (e.g., 1.8 volts) to a low level (e.g., 0 volts), then the mid level can be determined to be 1.8 volts/2=0.9 volts. It should be noted that the different control signals (e.g., high, low, mid-level control signals) discussed above can be repeated for each phase (e.g., phase A, phase B, phase C) of the spindle motor410. In one non-limiting example, one control signal may be provided for each phase during normal operation (e.g., spin up, spin down, or at speed) of the disk drive. In some other cases, more than three (3) control signals (e.g., 6 signals, 9 signals) may be utilized, with less control function on each signal.

In some cases, the lead PLSI420is configured to control the commutation (of the windings), internally, in a closed loop from the BEMF feedback. As used herein, closed loop may imply that the internal PLSI hardware (of the lead PLSI420) controls the advancing of the spindle motor driving profile based upon the BEMF feedback. In other words, the FW may not need to continually send in the advance signal to move through the spindle motor driving profile (i.e., to the next profile step, for instance, in the sine wave or trapezoidal wave). Additionally, or alternatively, the lead PLSI420is configured to send the driver output control signal to the plurality of pins444via the pins434, which allows the support PLSI440to perform the same or similar operations described above. In this way, the two spindle drivers430-a,430-bcan be driven in parallel.

In some aspects, the HW implementation described above in relation toFIG.4may allow for PLSI closed loop control, i.e., in lieu of the open loop driving method from the SoC firmware (FW), as described in relation toFIG.3. Furthermore, as noted above, the commutation of the windings may be based at least in part on the BEMF voltage/signal generated by the windings of the spindle motor410.

FIG.5illustrates a conceptual graph500showing RPM594(on the vertical or y-axis577) against time592(on the horizontal or x-axis576) for a spindle motor, according to various aspects of the disclosure. Graph500shows a first trace545corresponding to the RPM of a spindle motor during a spin up routine when a plurality of spindle drivers (e.g., spindle drivers330-a,330-binFIG.3) are connected in parallel and simultaneously used to commutate the windings (e.g., windings L16, L17, and L18) of the spindle motor (e.g., spindle motor310). This allows for a higher spin up current to be used, which helps reduce spin up time, as compared to the prior art. Graph500also shows a second trace555corresponding to the RPM of a spindle motor during a spin up routine when a single spindle driver is used to commutate the windings of the spindle motor. As seen, a faster spin up time (i.e., amount of time required to the target RPM is shorter) can be achieved when a plurality of spindle drivers are used in parallel (trace545) as compared to the case where a single spindle driver is used (trace555) during a spin up routine.

Turning now toFIG.6, which illustrates a conceptual graph600showing spindle phase current686(on the vertical or y-axis677) against time692(on the horizontal or x-axis676) during a spin up procedure/routine of a data storage device, according to various aspects of the disclosure. Graph600depicts two traces646,655, where trace645corresponds to the spindle current during spin up when a plurality of spindle drivers are utilized in parallel to commutate the windings of the spindle motor, while trace655corresponds to the spindle current during spin up when a single spindle driver is utilized to commutate the windings of the spindle motor.FIG.6also shows intercepts674-aand674-bcorresponding to the intersections of the traces645and655, respectively, with the y-axis677. In one non-limiting example, the intercepts674may be based on a maximum threshold current that can be supported by the spindle driver(s), the field effect transistors (FETs), or a combination thereof. As an example, if a single spindle driver (or its FETs) can support a maximum current of ‘I’ amps during spin up, where I=3, 4, etc., then two spindle drivers (or their FETs) may be able to support a maximum current of ‘2*I’ amps, where 2*I=6, 8, etc. In some cases, the magnitude of the intercept674-amay be around twice that of the intercept674-b, for instance, when two spindle drivers are used in parallel during spin up. In other cases, however, the intercept674-amay be more than twice the intercept674-b, for instance, when more than two spindle drivers are used in parallel.

During spin up, the current686gradually drops from a high current (e.g., intercept674-a) to around 0 amps, as shown by trace645. Furthermore, when a single spindle driver is used, the current686may remain relatively steady (e.g., little deviation from the intercept674-b) for a first portion of time, followed by a gradual drop from a high current (e.g., intercept674-b) to around 0 amps, as shown by trace655.

In some cases, the spindle current is at or near 0 amps following the spin-up routine, for instance, when the RPM of the spindle motor is at or near the target RPM (referred to as “at-speed”). In some embodiments, the spin-up and/or at-speed routines may be open loop, in which case the SoC (e.g., SoC350) is constantly commutating the spindle motor (e.g., spindle motor310) through each position based upon the BEMF feedback signal. Alternatively, the spin-up and/or at-speed routines may be controlled closed-loop, as described above in relation toFIG.4.

Turning now toFIGS.7A and7B, which illustrate conceptual graphs700-aand700-b, respectively, during a spin-down routine, according to various aspects of the disclosure.

FIG.7Aillustrates a conceptual graph700-ashowing spindle current (trace707-a) and RPM (trace717-a) against time792-awhen a single spindle driver is utilized, as in the prior art.

FIG.7Billustrates a conceptual graph700-bshowing spindle current (trace707-b) and RPM (trace717-b) against time792-bwhen a plurality of spindle drivers are used in parallel, in accordance with aspects of the disclosure. In some cases, the y-axis intercept of trace707-bmay be higher than the y-axis intercept of trace707-a, indicating a higher spin-down braking current. In some cases, the y-axis intercept of trace707-bmay be around twice (or slightly lower) than the y-axis intercept of trace707-a, for instance, when two spindle drivers are utilized in parallel. Furthermore, the y-axis intercept of traces707-aand707-bmay be at or around the same, indicating the initial RPM before the braking current is applied is around the same in both situations.

Similar to the spin-up case, a reduction in spin-down time may be achieved when two or more spindle drivers are connected in parallel and used to brake the spindle motor. In some cases, a higher braking current (e.g., 6 amps instead of 3 amps) can be utilized when multiple spindle drivers are connected in parallel (to the windings of the spindle motor) and used to perform the open-loop brake in parallel. In some cases, the total braking current during spin down may be based in part on the BEMF level. For example, a slightly lower braking current (e.g., 4-5 amps instead of 6 amps) can be employed when the BEMF is below a threshold, and a maximum braking current (e.g., 6 amps) can be employed when the BEMF is above a threshold. In some cases, the maximum braking current (IBrake) can be calculated using Ohms-law, e.g., IBrake=VBEMF/Spindle Resistance.

Any suitable control circuitry (e.g., control circuitry22inFIG.2A) may be employed to implement the flow diagrams in the above examples, such as any suitable integrated circuit or circuits. For example, the control circuitry may be implemented within a read channel integrated circuit, or in a component separate from the read channel, such as a data storage controller, or certain operations described above may be performed by a read channel and others by a data storage controller. In one example, the read channel and data storage controller are implemented as separate integrated circuits, and in another example, they are fabricated into a single integrated circuit or system on a chip (SOC), such as SoC350inFIG.3, SoC450inFIG.4. In addition, the control circuitry22may include a preamp circuit, where the preamp circuit is implemented as a separate integrated circuit, integrated into the read channel or data storage controller circuit, or integrated into the SoC.

In some examples, the control circuitry, such as, but not limited to, control circuitry22, comprises a microprocessor executing instructions, the instructions being operable to cause the microprocessor to perform the flow diagrams (e.g., shown inFIG.2C) described herein. The instructions may be stored in any computer-readable medium. In some examples, they may be stored on a non-volatile semiconductor memory device, component, or system external to the microprocessor, or integrated with the microprocessor in the SoC. In some examples, the instructions are stored on the disk and read into a volatile semiconductor memory when the disk drive is powered on. In some examples, the control circuitry comprises suitable logic circuitry, such as state machine circuitry. In some examples, at least some of the flow diagram blocks may be implemented using analog circuitry (e.g., analog comparators, timers, etc.), and in other examples at least some of the blocks may be implemented using digital circuitry or a combination of analog and digital circuitry.

In various examples, one or more processing devices may comprise or constitute the control circuitry22as described herein, and/or may perform one or more of the functions of control circuitry as described herein. In various examples, the control circuitry22, or other one or more processing devices performing one or more of the functions of control circuitry as described herein, may be abstracted away from being physically proximate to the disks and disk surfaces. The control circuitry, or other one or more processing devices performing one or more of the functions of control circuitry as described herein, may be part of or proximate to a rack of or a unitary product comprising multiple data storage devices, or may be part of or proximate to one or more physical or virtual servers, or may be part of or proximate to one or more local area networks or one or more storage area networks, or may be part of or proximate to a data center, or may be hosted in one or more cloud services, in various examples.

In various examples, a disk drive, such as disk drive15, may include a magnetic disk drive, an optical disk drive, a hybrid disk drive, or other types of disk drive. In addition, some examples may include electronic devices such as computing devices, data server devices, media content storage devices, or other devices, components, or systems that may comprise the storage media and/or control circuitry as described above.

The various features and processes described above may be used independently of one another or may be combined in various ways. All possible combinations and subcombinations are intended to fall within the scope of this disclosure. In addition, certain method(s), event(s), or process blocks may be omitted in some implementations. The methods and processes described herein are also not limited to any particular sequence, and the blocks or states relating thereto can be performed in other sequences. For example, described tasks or events may be performed in an order other than that specifically disclosed, or multiple may be combined in a single block or state. The example tasks or events may be performed in serial, in parallel, or in another manner. Tasks or events may be added to or removed from the disclosed examples. The example systems and components described herein may be configured differently than described. For example, elements may be added to, removed from, or rearranged compared to the disclosed examples.

While certain example embodiments are described herein, these embodiments are presented by way of example only, and do not limit the scope of the disclosure. Thus, nothing in the foregoing description implies that any particular feature, characteristic, step, module, or block is necessary or indispensable. The novel methods and systems described herein may be embodied in a variety of other forms. Various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit and scope of the present disclosure.

Method80and other methods of this disclosure may include other steps or variations in various other embodiments. Some or all of any of method80may be performed by or embodied in hardware, and/or performed or executed by a controller, a CPU, a field-programmable gate array (FPGA), a SoC, a multi-processor system on chip (MPSoC), which may include both a CPU and an FPGA, and other elements together in one integrated SoC, or other processing device or computing device processing executable instructions, in controlling other associated hardware, devices, systems, or products in executing, implementing, or embodying various subject matter of the method.

Data storage systems, devices, and methods are thus shown and described herein, in various foundational aspects and in various selected illustrative applications, architectures, techniques, and methods for enhancing spin up and spin down times for data storage devices, and other aspects of this disclosure. Persons skilled in the relevant fields of art will be well-equipped by this disclosure with an understanding and an informed reduction to practice of a wide panoply of further applications, architectures, techniques, and methods for enhancing spin up and spin down times for data storage devices, and other aspects encompassed by the present disclosure and by the claims set forth below.

As used herein, the recitation of “at least one of A, B and C” is intended to mean “either A, B, C or any combination of A, B and C.” The descriptions of the disclosed examples are provided to enable any person skilled in the relevant fields of art to understand how to make or use the subject matter of the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art based on the present disclosure, and the generic principles defined herein may be applied to other examples without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The present disclosure and many of its attendant advantages will be understood by the foregoing description, and various changes may be made in the form, construction, and arrangement of the components without departing from the disclosed subject matter or without sacrificing all of its material advantages. The form described is merely explanatory, and the following claims encompass and include a wide range of embodiments, including a wide range of examples encompassing any such changes in the form, construction, and arrangement of the components as described herein.

While the present disclosure has been described with reference to various examples, it will be understood that these examples are illustrative and that the scope of the disclosure is not limited to them. All subject matter described herein are presented in the form of illustrative, non-limiting examples, and not as exclusive implementations, whether or not they are explicitly called out as examples as described. Many variations, modifications, and additions are possible within the scope of the examples of the disclosure. More generally, examples in accordance with the present disclosure have been described in the context of particular implementations. Functionality may be separated or combined in blocks differently in various examples of the disclosure or described with different terminology, without departing from the spirit and scope of the present disclosure and the following claims. These and other variations, modifications, additions, and improvements may fall within the scope of the disclosure as defined in the claims that follow.