Patent ID: 12207471

DETAILED DESCRIPTION OF THE EMBODIMENTS

Embodiments will now be described more fully with reference to the accompanying drawings. In the accompanying drawings, like reference numerals may refer to like elements, and repeated descriptions of the like elements will be omitted. In the following drawings, the thickness or the size of each layer are exaggerated for convenience and clarity of description, and thus may be slightly different from the actual shape and ratio.

FIG.1is a block diagram of a semiconductor memory device10according to some embodiments.

Referring toFIG.1, the semiconductor memory device10includes a memory cell array50and a peripheral circuit60. According to some embodiments, the semiconductor memory device10may further include a data input/output (I/O) circuit or an I/O interface.

The memory cell array50is connected to string select lines SSL, word lines WL, a ground select line GSL, and bit lines BL. The peripheral circuit60includes a control logic unit61, a row decoder62, and a page buffer63. According to some embodiments, the memory cell array50is connected to the row decoder62via the string select lines SSL, the word lines WL, and the ground select line GSL, connected to the page buffer63via the bit lines BL, and connected to a common source line driver64via a common source line CSL.

FIG.2is a conceptual diagram schematically illustrating a structure of the semiconductor memory device10ofFIG.1according to some embodiments.

The semiconductor memory device10includes the memory cell array50and the peripheral circuit60, and these components of the semiconductor memory device10may be formed via a semiconductor manufacturing process.

Referring toFIGS.1and2, the semiconductor memory device10includes a first semiconductor device layer L1and a second semiconductor device layer L2. According to some embodiments, the second semiconductor device layer L2is arranged on the first semiconductor device layer L1in a first direction (Z direction). According to some embodiments, the memory cell array50ofFIG.1may be formed in the second semiconductor device layer L2, and the peripheral circuit60may be formed in the first semiconductor device layer L1.

The first semiconductor layer L1may include a lower substrate. The first semiconductor device layer L1may include semiconductor devices, such as transistors, and wires for driving the semiconductor devices, formed on the lower substrate. Accordingly, for example, circuits corresponding to the control logic unit61, the row decoder62, the page buffer63, and the common source line driver64ofFIG.1may be formed.

The second semiconductor layer L2may include a conductive layer and an upper substrate arranged on the conductive layer. According to some embodiments, upper surfaces of the upper substrate and the lower substrate may be substantially perpendicular to the first direction (Z direction), but the inventive concept is not limited thereto. According to some embodiments, the upper substrate may include a plurality of layers. The second semiconductor layer L2may include the memory cell array50formed on the upper substrate. According to some embodiments, at least one conductive layer may serve to supply the common source voltage to the memory cell array50.

According to some embodiments, conductive patterns for connecting the memory cell array50to the peripheral circuit60included in the first semiconductor device layer L1may be formed in the second semiconductor device layer L2. According to some embodiments, a plurality of word lines WL may extend in a second direction (X direction) perpendicular to the first direction (Z direction). According to some embodiments, a plurality of bit lines BL may extend in a third direction (Y direction) perpendicular to the first direction (Z direction). The first direction (Z direction), the second direction (X direction), and the third direction (Y direction) may be substantially perpendicular to one another. A term ‘vertical direction’ used below may refer to a direction substantially parallel to the first direction (Z direction), and a term ‘vertical level’ may refer to a height from a reference surface (for example, an upper surface of the upper substrate) in the first direction (Z direction). A term ‘horizontal direction’ used below may refer to a direction perpendicular to the first direction (Z direction). For example, the horizontal direction may refer to the third direction (Y direction), the second direction (X direction) or any direction between the third direction and the second direction.

The memory cells included in the memory cell array50may be accessed by the plurality of word lines WL and the plurality of bit lines BL. The plurality of word lines WL and the plurality of bit lines BL may be electrically connected to the peripheral circuit60formed in the first semiconductor device layer L1.

Accordingly, the semiconductor memory device10may have a structure in which the memory cell array50and the peripheral circuit60are arranged in the first direction (Z direction), namely, a Cell-On-Peripheral Circuit or Cell-Over-Peripheral Circuit (COP) structure. According to some embodiments, a circuit other than the memory cell array50may be arranged below the memory cell array50, and thus the COP structure may reduce a horizontal area of the semiconductor memory device10. Accordingly, the degree of integration of the semiconductor memory device10may be increased.

Although the semiconductor memory device10has a COP structure inFIG.2, this is merely an example, and the inventive concept is not limited thereto. For example, the technical spirit of the inventive concept is substantially equally applicable to memory devices having a structure in which a peripheral circuit region is arranged horizontally apart from a cell region on the same level as the cell region.

FIG.3is a schematic circuit diagram for explaining a circuit structure of the memory blocks BLK1through BLKz ofFIG.1according to some embodiments. A memory block BLK ofFIG.3may be one of the memory blocks BLK1through BLKz ofFIG.1.

Referring toFIG.3, the memory block BLK may be a NAND flash memory having a vertical structure. The memory block BLK includes a plurality of NAND strings NS11through NS33(that is, NAND strings NS11, NS12, NS13, NS21, NS22, NS23, NS31, NS32and NS33), a ground select line GSL, a plurality of string select lines SSL1, SSL2, and SSL3(that is, first, second, and third string select lines SSL1, SSL2, and SSL3), a plurality of word lines WL1through WL8(that is, first, second, third, fourth, fifth, sixth, seventh, and eighth word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8), a plurality of bit lines BL1through BL3(that is, first, second, and third bit lines BL1, B2, and BL3), and a common source line CSL. The number of NAND strings, the number of word lines, the number of bit lines, the number of ground select lines, and the number of string select lines may vary according to embodiments, and the inventive concept is not limited thereto.

According to some embodiments, the plurality of NAND strings NS11through NS33are connected between the plurality of bit lines BL1through BL3and the common source line CSL. Each of the NAND strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33includes a string select transistor SST, a plurality of memory cells MC1through MC8(that is, memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7and MC8), and a ground select transistor GST that are serially connected to each other.

FIG.4Ais a cross-sectional view for explaining the semiconductor memory device10according to some embodiments, andFIG.4Bis an enlarged cross-sectional view of a region E1ofFIG.4A.

Referring toFIG.4A, the semiconductor memory device10includes a first semiconductor device layer L1including a peripheral circuit, and a second semiconductor device layer L2including channel structures operating as memory cells. The second semiconductor layer L2is arranged on the first semiconductor device layer L1.

The first semiconductor device layer L1includes a lower substrate101, peripheral transistors111and112, peripheral circuit wires electrically connected to the peripheral transistors111and112, and a lower insulation layer150covering the peripheral transistors111and112and the peripheral circuit wires. The peripheral transistors111and112, the peripheral circuit wires, and the lower insulation layer150are arranged on the lower substrate101. According to some embodiments, the lower insulation layer150may include an insulative material. For example, the lower insulation layer150may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or the like.

According to some embodiments, the lower substrate101may include a semiconductor substrate including a semiconductor material, such as monocrystalline silicon or monocrystalline germanium. A trench for defining an active area and an inactive area, and an isolation layer120filling the trench may be formed on the lower substrate101.

According to some embodiments, the peripheral transistors111and112may constitute the peripheral circuit60ofFIG.1. According to some embodiments, the peripheral transistors111and112may constitute the control logic unit61, the row decoder62, the page buffer63, and the common source line driver64ofFIG.1.

The peripheral circuit wires include a plurality of peripheral conductive patterns140sequentially stacked on the lower substrate101. The peripheral circuit wires further include a plurality of peripheral vias130that connect the peripheral transistors111and112with the plurality of peripheral conductive patterns140formed on different levels. According to some embodiments, the peripheral circuit wires are illustrated as including three layers of peripheral conductive patterns140and peripheral vias130connecting them to each other, but the inventive concept is not limited thereto. The peripheral circuit wires may include two layers or at least four layers of peripheral conductive lines and vias connecting them to each other.

The second semiconductor device layer L2includes a common source line CSL, an upper substrate201arranged on the common source line CSL, insulation layers230and gate electrodes240stacked alternately and repeatedly on the upper substrate201, and first and second upper insulation layers261and263covering them. The second semiconductor device layer L2includes channel structures250penetrating through the insulation layers230and the gate electrodes240, word line cut insulation layers WLCI separating the gate electrodes240from each other, and string selection line cut insulation layers SSLCI separating uppermost gate electrodes240(SE) from each other. According to some embodiments, the second semiconductor device layer L2may further include wires enabling the gate electrodes240and the channel structures250to operate as the memory cell array50ofFIG.1.

The common source line CSL is arranged on the first semiconductor device layer L1. According to some embodiments, the common source line CSL may be in a flat plate shape. According to some embodiments, the common source line CSL may include tungsten (W) or a W compound.

According to some embodiments, the upper substrate201may be a support layer that supports the insulation layers230and the gate electrodes240. According to some embodiments, the upper substrate201may include, but is not limited to, a plurality of layers. For example, the upper substrate201may include a single layer. According to some embodiments, the upper substrate201includes a first upper substrate layer201aarranged on the common source line CSL, a second upper substrate layer201barranged on the first upper substrate layer201a, and a third upper substrate layer201cbetween the first and second upper substrate layers201aand201b. The first upper substrate layer201acontacts the third upper substrate layer201c. The third upper substrate layer201cmay contact the second upper substrate layer201b. The third upper substrate layer201cmay include an opening that exposes an upper surface of the first upper substrate layer201a. The second upper substrate layer201bmay partially contact the first upper substrate layer201avia the opening. The term “contact,” as used herein, refers to a direct connection (i.e., touching) unless the context indicates otherwise.

According to some embodiments, the first, second, and third upper substrate layers201a,201b, and201cmay include polysilicon. According to some embodiments, the first, second, and third upper substrate layers201a,201b, and201cmay include doped polysilicon layers. According to some embodiments, the first, second, and third upper substrate layers201a,201b, and201cmay be doped at substantially the same concentration, but the inventive concept is not limited thereto.

The first, second, and third upper substrate layers201a,201b, and201cmay include bulk silicon substrates, silicon on insulator (SOI) substrates, germanium substrates, germanium on insulator (GOI) substrates, silicon-germanium substrates, or epitaxial thin-film substrates obtained via selective epitaxial growth (SEG). The first, second, and third upper substrate layers201a,201b, and201cmay include, for example, at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenic (GaAs), indium gallium arsenic (InGaAs), aluminum gallium arsenic (AlGaAs), or a mixture thereof.

According to some embodiments, the gate electrodes240may correspond to gates of the transistors ofFIG.3. For example, lowermost gate electrodes240(GE) may correspond to gates of the ground selection transistors GST ofFIG.3, the uppermost gate electrode240(SE) may correspond to gates of the string selection transistors SST ofFIG.3, and gate electrodes240(WE) between the lowermost and uppermost gate electrodes240(GE) and240(SE) may correspond to gates of the plurality of memory cells MC1through MC8ofFIG.3. Referring toFIG.4A, the eight gate electrodes240(WE) are illustrated as operating as the gates of the memory cells, but the inventive concept is not limited thereto. For example, various numbers of gate electrodes240, such as 4, 16, 32, 64, or 128, may operate as the gates of the memory cells.

According to some embodiments, one or more dummy gate electrodes may be further arranged between the gate electrodes240(GE) corresponding to the ground selection transistors GST ofFIG.3and the gate electrodes240(WE) corresponding to the memory cells MC1ofFIG.3, and/or between the gate electrodes240(SE) corresponding to the string selection transistors SST ofFIG.3and the gate electrode240(WE) corresponding to the memory cells MC8ofFIG.3. In this case, inter-cell interference generated between adjacent gate electrodes240may be reduced.

According to some embodiments, the gate electrodes240may include a conductive material. According to some embodiments, as shown inFIG.4B, each of the gate electrodes240may include a plurality of layers. According to some embodiments, the gate electrodes240may include tungsten, tantalum, cobalt, nickel, tungsten silicide, tantalum silicide, cobalt silicide, or nickel silicide. According to some embodiments, the gate electrodes240may include polysilicon.

According to some embodiments, first and second bit line contact vias271and275, an upper conductive pattern273, and a bit line BL, which will be described later, may include at least one of the materials mentioned above to explain the gate electrodes240.

According to some embodiments, the first and second upper insulation layers261and263are arranged on the uppermost gate electrodes240(SE). The first and second upper insulation layers261and263may include an insulative material.

According to some embodiments, the plurality of channel structures250penetrate through the first upper insulation layer261, the gate electrodes240, and the insulation layers230in the first direction (Z direction). The channel structures250may penetrate through the second upper substrate layer201b. Lower portions of the channel structures250may be covered by the first upper substrate layer201a. Upper surfaces of the channel structures250may be coplanar with (i.e., positioned at the same height as) an upper surface of the first upper insulation layer261, and lower surfaces of the channel structures250may be lower than an upper surface of the first upper substrate layer201a. Adjacent channel structures may be arranged apart from each other at certain intervals in the second and third directions (X and Y directions).

According to some embodiments, each of the channel structures250may include a plurality of layers. For example, each of the channel structures250includes a gate insulation layer251, a channel layer253, and a buried insulation layer255.

According to some embodiments, the gate insulation layer251may have a conformal thickness. According to some embodiments, the gate insulation layer251may constitute a bottom surface and an external lateral surface of the channel structure250. Accordingly, according to some embodiments, the gate insulation layer251may insulate the channel layer253from the gate electrodes240.

According to some embodiments, the gate insulation layer251may include a plurality of layers having a conformal thickness. According to some embodiments, the gate insulation layer251may include a tunnel insulation layer, a charge storage layer, and a blocking insulation layer. The tunnel insulation layer may include silicon oxide, hafnium silicide, aluminum oxide, zirconium oxide, tantalum oxide, or the like. The charge storage layer may be a region where electrons tunneled from the channel layer253are stored, and may include silicon nitride, boron nitride, silicon boron nitride, or impurity-doped polysilicon. The blocking insulation layer may include a single layer or a stacked layer of silicon oxide, silicon nitride, hafnium silicide, aluminum oxide, zirconium oxide, tantalum oxide, or the like. However, the material of the blocking insulation layer is not limited thereto, and the blocking insulation layer may include a dielectric material having a high dielectric constant value.

According to some embodiments, the gate insulation layer251may not be arranged on the same level as the third upper substrate layer201c, because a portion of the gate insulation layer251is removed during a replacement process with respect to the third upper substrate layer201c. For example, the third upper substrate layer201cdivides the gate insulation layer251into an upper gate insulation layer serving as gate insulation layers for the uppermost gate electrodes240(SE), the gate electrodes240(WE) and the lowermost gate electrodes240(GE), and a lower gate insulation layer covering bottom ends of the channel structures250. Thus, the third upper substrate layer201cand the channel layer253are connected to each other.

According to some embodiments, the channel layer253may fill a portion of an internal space defined by the gate insulation layer251. The channel layer253formed on an inner sidewall of the gate insulation layer251may have a certain thickness. According to some embodiments, an upper portion of the channel layer253may have a thickness larger than a portion of the channel layer253which is in contact with the inner sidewall of the gate insulation layer251.

According to some embodiments, a space defined by the channel layer253may be filled with the buried insulation layer255. An upper surface of the buried insulation layer255may be covered by the upper portion of the channel layer253. According to some embodiments, an upper surface of the channel layer253may serve as a pad for forming electrical connection with the first bit line contact vias271. In some cases, a separate contact pad may be provided on the upper surface of the channel layer253.

Referring toFIG.4A, the gate insulation layer251is illustrated as covering a lower surface of the channel layer253, but the inventive concept is not limited thereto. In an example embodiment, the gate insulation layer251may expose a lower surface of the channel layer253and constitute only a sidewall of each of the channel structures250. In this case, a semiconductor pattern grown from an upper substrate via SEG and the lower surface of the channel layer may contact each other, and the channel layer may not be directly connected to the upper substrate.

According to some embodiments, the word line cut insulation layer WLCI penetrates through the first and second upper insulation layers261and263, the gate electrodes240, and the insulation layers230in the first direction (Z direction). The word line cut insulation layer WLCI further penetrates through the second upper substrate layer201band a portion of the first upper substrate layer201a. In this case, an end portion of the word line cut insulation layer WLCI is buried in the first upper substrate layer201a. The inventive concept, however, is not limited thereto. According to some embodiments, the word line cut insulation layer WLCI may insulate different gate electrodes240arranged on the same vertical level from each other. For example, the gate electrodes240separated from other gate electrodes may be disposed between two adjacent word line cut insulation layers (i.e., a pair of word line cut insulation layers). According to some embodiments, the word line cut insulation layer WLCI may extend long in the second direction (X direction) and thus separate the gate electrodes240from each other in the second direction (X direction). A length of the word line cut insulation layer WLCI in the second direction (X direction) may be greater than that of the gate electrodes240in the second direction (X direction). Accordingly, the word line cut insulation layer WLCI may completely separate the gate electrodes240from each other. Accordingly, the gate electrodes240horizontally spaced apart from each other may operate as gates of different transistors (for example, ground selection transistors, memory cell transistors, and/or string selection transistors).

According to some embodiments, the word line cut insulation layer WLCI has a tapered shape in the first direction (Z direction). The tapered shape refers to a shape of which a horizontal width linearly or gradually decreases in a direction toward the upper substrate201. According to some embodiments, the word line cut insulation layer WLCI includes a portion having a width (for example, a width in the third direction (Y direction)) that decreases in the first direction (Z direction). The word line cut insulation layer WLCI further includes a portion that protrudes on the same level as the gate electrodes240in the horizontal direction (for example, the third direction (Y direction)). Accordingly, a portion of the word line cut insulation layer WLCI that is on the same level as a gate electrode240has a greater width than a portion of the word line cut insulation layer WLCI that is on the same level as an insulation layer230adjacent to the gate electrode240. The above-described structure of the word line cut insulation layer WLCI may be formed by recessing gate electrode materials during a node separation process P180ofFIG.9.

According to some embodiments, the word line cut insulation layer WLCI may include an insulative material, such as silicon oxide, silicon nitride, or silicon oxynitride. According to some embodiments, even when the word line cut insulation layer WLCI has the same composition as one of the insulation layers230and the first and second upper insulation layers261and263, a first barrier241ofFIG.4Bis between the word line cut insulation layer WLCI and the insulation layers230, between the word line cut insulation layer WLCI and the first upper insulation layer261, and between the word line cut insulation layer WLCI and the second upper insulation layer263, and thus the word line cut insulation layer WLCI may be distinguished from the insulation layers230and the first and second upper insulation layers261and263. The first barrier241may be referred to a first barrier layer.

Because a space filled with the word line cut insulation layer WLCI separates gate electrodes connected to adjacent word lines, the space will be referred to as a word line cut. The word line cut is substantially the same as a second word line cut trench WCT2ofFIG.18A.

Structural and compositional features of the string selection line cut insulation layer SSLCI will be described in detail with reference toFIGS.4A and4B. The string selection line cut insulation layer SSLCI may extend in the first direction (Z direction). According to some embodiments, the string selection line cut insulation layer SSLCI is positioned on the same level as the first and second upper insulation layers261and263and the uppermost gate electrodes240(SE). According to some embodiments, the string selection line cut insulation layer SSLCI penetrates through the uppermost gate electrodes240(SE) operating as gate electrodes of the string selection transistors SST ofFIG.3, in the first direction (Z direction). According to some embodiments, the string selection line cut insulation layer SSLCI may insulate horizontally-spaced uppermost gate electrodes240(SE) from each other.

According to some embodiments, the string selection line cut insulation layer SSLCI may extend long in the second direction (X direction) and thus separate the uppermost gate electrodes240(SE) from each other in the third direction (Y direction). A length of the string selection line cut insulation layer SSLCI in the second direction (X direction) may be greater than that of the uppermost gate electrodes240(SE) in the second direction (X direction). According to some embodiments, the string selection line cut insulation layer SSLCI may completely separate the uppermost gate electrodes240(SE) from each other. Accordingly, uppermost gate electrodes240(SE) disposed between two adjacent word line cut insulation layers WLCI and horizontally spaced apart from each other may operate as gates of different string selection transistors. For example, as shown inFIG.3, each block includes three string selection lines SSL1, SSL2and SSL3that may be independently controlled, and inFIG.4A, the uppermost gate electrode240(SE) is separated by two string selection line cut insulation layers to form three separated uppermost gate electrodes serving as the three string selection lines SSL1, SSL2and SSL3.

According to some embodiments, a portion of the string selection line cut insulation layer SSLCI that is on the same level as the first and second upper insulation layers261and263has a tapered shape in the first direction (Z direction). According to some embodiments, the string selection line cut insulation layer SSLCI has a discontinuously-changed width at an interface between the first upper insulation layer261and the uppermost gate electrodes240(SE). According to some embodiments, a width of the string selection line cut insulation layer SSLCI includes a protrusion R protruding from a center of the string selection line cut insulation layer SSLCI in a horizontal direction (for example, the third direction (Y direction)), on the same level as the uppermost gate electrodes240(SE). According to some embodiments, the string selection line cut insulation layer SSLCI has a maximum width on the same level as the uppermost gate electrodes240(SE), but the inventive concept is not limited thereto. In an example embodiment, a horizontal width (for example, a width in the third direction (Y direction)) of the string selection line cut insulation layer SSLCI may be maximum at an upper surface of the second upper insulation layer263.

Each of the uppermost gate electrodes240(SE) includes the first barrier241, a second barrier242, and a gate conductive layer243. The second barrier242may be referred to as a second barrier layer. According to some embodiments, the first barrier241, the second barrier242, and the gate conductive layer243may include different materials from one another. According to some embodiments, the first barrier241and the second barrier242may have uniform thicknesses. According to some embodiments, the first barrier241may have, but is not limited to, a thickness of about 2 nm. According to some embodiments, the second barrier242may have, but is not limited to, a thickness of about 2 nm. According to some embodiments, the first barrier241may include, but is not limited to, one of metal oxide (for example, aluminum oxide), metal nitride, and metal oxynitride. According to some embodiments, the second barrier242may include, but is not limited to, titanium nitride. According to some embodiments, the gate conductive layer243may include, but is not limited to, tungsten.

According to some embodiments, a lateral surface of the protrusion R contacts the second barrier242and the gate conductive layer243. According to some embodiments, the protrusion R has a thickness in the first direction (Z direction) that is substantially the same as a sum of respective thicknesses of the second barrier242and the gate conductive layer243in the first direction (Z direction), but the inventive concept is not limited thereto. Accordingly, a thickness of the uppermost gate electrode240(SE) in the first direction (Z direction) is greater than that of the protrusion R in the first direction (Z direction).

According to some embodiments, the first barrier241may be between the string selection line cut insulation layer SSLCI and the second upper insulation layer263. According to some embodiments, the first barrier241is disposed between the string selection line cut insulation layer SSLCI and the first upper insulation layer261. Accordingly, the string selection line cut insulation layer SSLCI is spaced apart from the first and second upper insulation layers261and263. According to some embodiments, an upper surface of the protrusion R and a lower surface thereof contact the first barrier241.

According to some embodiments, the first barrier241covers the upper and lower surfaces of the protrusion R. According to some embodiments, the first barrier241covers the portion of the string selection line cut insulation layer SSLCI that is on the same level as the first and second upper insulation layers261and263. According to some embodiments, the first barrier241covers the first and second upper insulation layers261and263adjacent to the string selection line cut insulation layer SSLCI.

According to some embodiments, the string selection line cut insulation layer SSLCI may include an insulative material, such as silicon oxide, silicon nitride, or silicon oxynitride. According to some embodiments, even when the string selection line cut insulation layer SSLCI has the same composition as one of the first and second upper insulation layers261and263, the first barrier241is between the string selection line cut insulation layer SSLCI and the first and second upper insulation layers261and263, and thus the string selection line cut insulation layer SSLCI may be distinguished from the insulation layers230and the first and second upper insulation layers261and263by the first barrier241. A sidewall of the string selection line cut insulation layer SSLCI is spaced apart from sidewalls of the first and second upper insulation layers261and263by the first barrier241. In an example embodiment, the first barrier241may contact the sidewall of the string selection line cut insulation layer SSLCI and the sidewalls of the first and second upper insulation layers261and263.

Referring toFIG.4A, two string selection line cut insulation layers SSLCI are illustrated as being arranged between adjacent word line cut insulation layers WLCI, but the present disclosure is not limited thereto. For example, three or more string selection line cut insulation layers SSLCI may be arranged between adjacent word line cut insulation layers WLCI.

A third upper insulation layer265is arranged on the second upper insulation layer263. The third upper insulation layer265may include an insulative material. According to some embodiments, the first and second bit line contact vias271and275may extend in the first direction (Z direction) on the same level as at least a portion of the third upper insulation layer265. According to some embodiments, combined structures of the first and second bit line contact vias271and275, and the upper conductive pattern273penetrate through third upper insulation layer265, and the first bit line contact vias271further penetrate through the second upper insulation layer263. According to some embodiments, the first bit line contact vias271may contact the channel layers253. According to some embodiments, the upper conductive pattern273is arranged between the first and second bit line contact vias271and275. According to some embodiments, the upper conductive pattern273may extend in a horizontal direction (for example, the second direction (X direction) and/or the third direction (Y direction)). According to some embodiments, the upper conductive pattern273contacts the first and second bit line contact vias271and275. According to some embodiments, the bit line BL contacts the second bit line contact vias275.

According to some embodiments, the channel structures250are connected to the bit line BL via the first bit line contact vias271, the upper conductive pattern273, and the second bit line contact vias275.

FIG.5Ais a schematic cross-sectional view for explaining a semiconductor memory device11according to some other embodiments.FIG.5Bis an enlarged cross-sectional view of a region E2ofFIG.5A.

For convenience of explanation, a description ofFIGS.5A and5Bthat is the same as or similar to that given above with reference toFIGS.4A and4Bwill not be repeated herebelow, and differences between them will now be focused on and described.

Referring toFIG.5A, the semiconductor memory device11includes a plurality of gate electrodes240. The gate electrodes240may correspond to the gates of the transistors ofFIG.3. In detail, lowermost gate electrodes240(GE) may correspond to the gates of the ground selection transistors GST ofFIG.3. Uppermost gate electrodes240(SE) and gate electrodes240(SE) right therebelow may correspond to the gates of the string selection transistors SST ofFIG.3.

Gate electrodes240(WE) arranged on each of the lowermost gate electrodes240(GE) may correspond to the gates of the plurality of memory cells MC1through MC8ofFIG.3. Referring toFIG.5A, the eight gate electrodes240(WE) are illustrated as operating as the gates of the memory cells MC1through MC8, but the inventive concept is not limited thereto. For example, various numbers of gate electrodes240, such as 4, 16, 32, 64, and 128, may operate as the gates of memory cells.

A plurality of (for example, two) dummy gate electrodes240(DE) may be arranged between the gate electrodes240(WE) corresponding to the eight memory cells MC1through MC8ofFIG.3and the gate electrodes240(SE) corresponding to the string selection transistors SST ofFIG.3.

However,FIG.5Aillustrates, as a structure of the gate electrodes240, a case where the plurality of dummy gate electrodes240(DE) and the gate electrodes240(SE) corresponding to the string selection transistors SST ofFIG.3are given, and does not limit the technical spirit of the inventive concept. For example, one or more dummy gate electrodes may be further disposed between the lowermost gate electrodes240(GE) and the gate electrodes240(WE), or three or more gate electrodes240(SE) may correspond to the string selection transistors SST ofFIG.3, or the number of dummy gate electrodes240(DE) may be one or at least three.

The semiconductor memory device11includes a string selection line cut insulation layer SSLCI1. A structure of the string selection line cut insulation layer SSLCI1will now be described in detail with reference toFIG.5B.

The string selection line cut insulation layer SSLCI1may extend in the first direction (Z direction). According to some embodiments, the string selection line cut insulation layer SSLCI1is positioned on the same level as the first and second upper insulation layers261and263, the gate electrodes240(SE) corresponding to the string selection transistors SST ofFIG.3, and the dummy gate electrodes240(DE).

According to some embodiments, the string selection line cut insulation layer SSLCI1penetrates through the gate electrodes240(SE) corresponding to the gate electrodes of the string selection transistor SST ofFIG.3, namely, an uppermost gate electrode240(SE) and a second-uppermost gate electrode240(SE) right below the uppermost gate electrode240(SE), in the first direction (Z direction). The string selection line cut insulation layer SSLCI1further penetrates through the dummy gate electrodes240(DE) in the first direction (Z direction).

According to some embodiments, the string selection line cut insulation layer SSLCI1may insulate horizontally-spaced uppermost gate electrodes240(SE) and horizontally-spaced second-uppermost gate electrodes240(SE) from each other. According to some embodiments, the string selection line cut insulation layer SSLCI1may extend long in the second direction (X direction) and thus separate the gate electrodes240from each other in the third direction (Y direction). A length of the string selection line cut insulation layer SSLCI1in the second direction (X direction) may be equal to or greater than that of the gate electrodes240in the second direction (X direction). Accordingly, the string selection line cut insulation layer SSLCI1may completely separate the uppermost gate electrodes240(SE) from each other. Accordingly, uppermost gate electrodes240(SE) disposed between two adjacent word line cut insulation layers WLCI and horizontally spaced apart from each other may operate as gates of different string selection transistors. According to some embodiments, the string selection line cut insulation layer SSLCI1may insulate horizontally-spaced dummy gate electrodes240(DE) from each other.

According to some embodiments, a portion of the string selection line cut insulation layer SSLCI1that is on the same level as the first and second upper insulation layers261and263has a tapered shape in the first direction (Z direction). A portion of the string selection line cut insulation layer SSLCI1that is on the same level as the insulation layers230has a tapered shape in the first direction (Z direction).

According to some embodiments, the string selection line cut insulation layer SSLCI1has a width (for example, a width in the third direction (Y direction)) discontinuously changing at an interface between the first upper insulation layer261and the uppermost gate electrodes240(SE). According to some embodiments, the string selection line cut insulation layer SSLCI1includes a first protrusion R1protruding from a center of the string selection line cut insulation layer SSLCI1in a horizontal direction (for example, the third direction (Y direction)), on the same level as the uppermost gate electrodes240(SE). According to some embodiments, the string selection line cut insulation layer SSLCI1has a maximum width on the same level as the uppermost gate electrodes240(SE), but the inventive concept is not limited thereto. According to some embodiments, a lateral surface of the first protrusion R1contacts the second barrier242and the gate conductive layer243. An upper surface and a lower surface of the first protrusion R1contacts the first barrier241.

According to some embodiments, the string selection line cut insulation layer SSLCI1has widths (for example, a width in the third direction (Y direction)) discontinuously changing at interfaces between the insulation layers230and some gate electrodes, for example, the second-uppermost gate electrode240(SE) and the dummy gate electrodes240(DE). According to some embodiments, the string selection line cut insulation layer SSLCI1further includes second, third, and fourth protrusions R2, R3, and R4protruding from the center of the string selection line cut insulation layer SSLCI1in the horizontal direction (for example, the third direction (Y direction)), on the same level as the second-uppermost gate electrodes240(SE) and the dummy gate electrodes240(DE). Lateral surfaces of the second, third, and fourth protrusions R2, R3, and R4contact the second barriers242and the gate conductive layers243, respectively. Upper surfaces and lower surfaces of the second, third, and fourth protrusions R2, R3, and R4contact the first barrier241.

The second protrusion R2is positioned on the same level as the second-uppermost gate electrode240(SE). The third protrusion R3is positioned on the same level as a dummy gate electrode240(DE) farther from the upper substrate201from among the dummy gate electrodes240(DE). The fourth protrusion R4is positioned on the same level as a dummy gate electrode240(DE) closer to the upper substrate201from among the dummy gate electrodes240(DE).

The first protrusion R1protrudes from the center of the string selection line cut insulation layer SSLCI1farther than the second protrusion R2. The second protrusion R2protrudes from the center of the string selection line cut insulation layer SSLCI1farther than the third protrusion R3. The third protrusion R3protrudes from the center of the string selection line cut insulation layer SSLCI1farther than the fourth protrusion R4.

According to some embodiments, the string selection line cut insulation layer SSLCI1penetrates through the entire portions of the dummy gate electrodes240(DE). According to some embodiments, the string selection line cut insulation layer SSLCI1may extend to a lower level than the lower surfaces of the dummy gate electrodes240(DE). For example, a lower surface of the string selection line cut insulation layer SSLCI1is located closer to the upper substrate201than the lower surfaces of the dummy gate electrodes240(DE). In this case, the string selection line cut insulation layer SSLCI1partially penetrates through an upper portion of the insulation layer230arranged below the dummy gate electrodes240(DE). A bottom end of the string selection line cut insulation layer SSLCI1is buried in the upper portion of the insulation layer230arranged below the dummy gate electrodes240(DE). The string selection line cut insulation layer SSLCI1has a minimum width on its lower surface of the bottom end.

FIGS.6,7, and8are cross-sectional views for explaining semiconductor memory devices12,13, and14according to some other embodiments, respectively.

For convenience of explanation, a description ofFIGS.6through8that is the same as or similar to that given above with reference toFIGS.4A through5Bwill not be repeated hereunder, and differences between them will now be focused on and described.

Referring toFIG.6, a string selection line cut insulation layer SSLCI2included in the semiconductor memory device12may have a different shape from the string selection line cut insulation layer SSLCI1included in the semiconductor memory device11ofFIG.5A.

For example, a lower surface of the string selection line cut insulation layer SSLCI2is coplanar with (i.e., at the same height as) the lower surface of the dummy gate electrode240(DE) closer to the upper substrate201from among the dummy gate electrodes240(DE). A horizontal width (for example, a width in the third direction (Y direction)) of an upper surface of the string selection line cut insulation layer SSLCI2is less than a horizontal width (for example, a width in the third direction (Y direction)) of the lower surface of the string selection line cut insulation layer SSLCI2.

Referring toFIG.7, a string selection line cut insulation layer SSLCI3included in the semiconductor memory device13may have a different shape from the string selection line cut insulation layer SSLCI1included in the semiconductor memory device11ofFIG.5A.

According to some embodiments, the string selection line cut insulation layer SSLCI3may penetrate through only some of the dummy gate electrodes240(DE). For example, the string selection line cut insulation layer SSLCI3penetrates through only an upper dummy gate of the two dummy gate electrodes240(DE). In this case, a lower surface of the string selection line cut insulation layer SSLCI3is coplanar with (i.e. positioned at the same height as) the lower surface of the upper dummy gate electrode farther from the upper substrate201from among the dummy gate electrodes240(DE). According to some embodiments, a horizontal width (for example, a width in the third direction (Y direction)) of an upper surface of the string selection line cut insulation layer SSLCI3is less than a horizontal width (for example, a width in the third direction (Y direction)) of the lower surface of the string selection line cut insulation layer SSLCI3.

Referring toFIG.8, a string selection line cut insulation layer SSLCI4included in the semiconductor memory device14may have a different shape from the string selection line cut insulation layer SSLCI1included in the semiconductor memory device11ofFIG.5A.

For example, the string selection line cut insulation layer SSLCI4may penetrate through only the uppermost and second-uppermost gate electrodes240(SE) corresponding to the string selection transistors SST ofFIG.3. In this case, the string selection line cut insulation layer SSLCI4penetrates through only the uppermost and second-uppermost gate electrodes240(SE). A horizontal width (for example, a width in the third direction (Y direction)) of an upper surface of the string selection line cut insulation layer SSLCI4is less than a horizontal width (for example, a width in the third direction (Y direction)) of the lower surface of the string selection line cut insulation layer SSLCI4.

FIG.9is a flowchart of a method of manufacturing a semiconductor memory device, according to some embodiments.

FIGS.10-13A,14A,15A,16,17A,18A, and19are cross-sectional views for explaining a method of manufacturing a semiconductor memory device, according to some embodiments.FIG.13Bis a cross-sectional view taken along line A-A′ ofFIG.13A,FIG.14Bis a cross-sectional view taken along line B-B′ ofFIG.14A,FIG.15Bis a cross-sectional view taken along line C-C′ ofFIG.15A,FIG.17Bis a cross-sectional view taken along line D-D′ ofFIG.17A, andFIG.18Bis a cross-sectional view taken along line E-E′ ofFIG.18A.

The method of manufacturing a semiconductor memory device, which will be described below, is an example of a method of manufacturing the semiconductor memory device10ofFIGS.4A and4B, and does not limit the technical spirit of the inventive concept. One of ordinary skill in the semiconductor technology field may manufacture the semiconductor memory devices11,12,13, and14ofFIGS.5A through8using substantially the same method as the method which will be described below with reference toFIGS.9through19.

Referring toFIGS.9and10, in P110, the first semiconductor layer L1, the first and second upper substrate layers201aand201b, a stacked structure SS, and the first upper insulation layer261may be formed.

The provision of the first semiconductor device layer L1may include a process of forming the isolation layer120on the lower substrate101, a process of forming a p-well region and an n-well region in this stated order (or in a reverse order) in the lower substrate101via a first ion injection process using a photoresist pattern for the lower substrate101, a process of forming the peripheral transistors111and112, and a process of patterning a conductive material and providing an insulative material to thereby form the peripheral circuit wires.

The common source line CSL and the first upper substrate layer201amay be formed on the lower insulation layer150. The common source line CSL and the first upper substrate layer201amay be formed via chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or the like.

After an upper substrate sacrificial layer202is provided on the first upper substrate layer201aand a portion of the upper substrate sacrificial layer202is patterned and removed, the second upper substrate layer201bmay be conformally formed on the partially-removed upper substrate sacrificial layer202. The second upper substrate layer201bmay include doped polysilicon. Accordingly, the first upper substrate layer201aand the second upper substrate layer201bcontact each other through the removed portion of the upper substrate sacrificial layer202. According to some embodiments, the first and second upper substrate layers201aand201bmay include doped polysilicon.

According to some embodiments, the upper substrate sacrificial layer202may include an insulative material. According to some embodiments, the upper substrate sacrificial layer202may include one of silicon oxide, silicon nitride, and silicon oxynitride. According to some embodiments, the upper substrate sacrificial layer202may have high etch selectivity with respect to the insulation layers230.

Then, sacrificial layers220and the insulation layers230are alternately stacked on the second upper substrate layer201bto thereby form the stacked structure SS. According to some embodiments, the insulation layers230and the sacrificial layers220may include different materials from each other. According to some embodiments, the insulation layers230may have high etch selectivity with respect to the sacrificial layers220. For example, when the sacrificial layers220include silicon oxide, the insulation layers230may include silicon nitride. As another example, when the sacrificial layers220include silicon nitride, the insulation layers230may include silicon oxide. As another example, when the sacrificial layers220include undoped polysilicon, the insulation layers230may include silicon nitride or silicon oxide.

The first upper insulation layer261may be formed on the stacked structure SS. The first upper insulation layer261may include an insulative material.

Referring toFIGS.9and11, in P120, channel holes CH may be formed. After a photoresist material layer is provided on the stacked structure SS, the channel holes CH may be formed via sequential executions of exposure, development, and etching to penetrate through the first upper insulation layer261, the stacked structure SS, the second upper substrate layer201b, the upper substrate sacrificial layer202, and an upper portion of the first upper substrate layer201a.

Referring toFIGS.9and12, in P130, the channel structures250may be formed. After a gate insulative material layer, a channel material layer, and a buried insulative material layer are sequentially provided on the stacked structure SS having the channel holes CH ofFIG.11formed therein, material layers that fill the channel holes CH may be separated from each other by performing a planarization process until an upper surface of the first upper insulation layer261is exposed. In an example embodiment, the planarization process my include an etchback process or a chemically-mechanical polish (CMP) process. Then, an upper portion of the buried insulative material layer within the channel holes CH is further removed to form recessed regions, and then the same material as the channel material layer may be deposited in the recessed regions to cover a recessed upper portion of the buried insulation layer255. In an example embodiment, the channel material formed in the recessed regions may serve as pads to be contacted by the first bit line contact vias271ofFIG.4A.

Referring toFIGS.9,13A, and13B, in P140, a first string selection line cut trench SCT1may be formed. The formation of the first string selection line cut trench SCT1may include forming the second upper insulation layer263on the first upper insulation layer261and then etching the first and second upper insulation layers261and263and an uppermost sacrificial layer220via dry or wet etching. The first string selection line cut trench SCT1exposes an upper surface of an uppermost insulation layer230by penetrating through the first and second upper insulation layers261and263and an uppermost sacrificial layer220. In some cases, the first string selection line cut trench SCT1may partially penetrate through an upper portion of the uppermost insulation layer230via excessive etching (i.e., over-etching).

The first string selection line cut trench SCT1may have a tapered shape in the first direction (Z direction). A length of the first string selection line cut trench SCT1in the second direction (X direction) may be equal to or greater than that of the uppermost sacrificial layer220in the second direction (X direction). Accordingly, the first string selection line cut trench SCT1may horizontally separate the uppermost sacrificial layer220.

Referring toFIGS.9and14A through15B, in P150, a first word line cut trench WCT1may be formed. The formation of the first word line cut trench WCT1may include forming a hard mask layer HDM filling the first string selection line cut trench SCT1and then etching a stacked structure by using the hard mask layer HDM.

In more detail, referring toFIGS.14A and14B, the hard mask layer HDM is formed on the first and second upper insulation layers261and263to cover the first and second upper insulation layers261and263. The hard mask layer HDM fills the first string selection line cut trench SCT1ofFIG.13A.

Then, referring toFIGS.15A and15B, after the hard mask layer HDM is patterned, the stacked structure SS, the first and second upper substrate layers201aand201b, and the upper substrate sacrificial layer202are etched using the patterned hard mask layer HDM as an etch mask to thereby form the first word line cut trench WCT1.

After the first word line cut trench WCT1is formed, the patterned hard mask layer HDM may be removed. According to some embodiments, the first word line cut trench WCT1may have a tapered shape in the first direction (Z direction). According to some embodiments, a length of the first word line cut trench WCT1in the second direction (X direction) may be greater than that of each of the sacrificial layers220in the second direction (X direction). Accordingly, the first word line cut trench WCT1may horizontally separate the sacrificial layers220from each other.

In the related art, before word line cut trenches are formed, string selection line cut trenches are filled with an insulative material. However, in this case, sacrificial layers arranged between string selection line cut trenches filled with the insulative material are not replaced by gate insulative material layers. In addition, even when gate electrodes for string selection lines are formed and then separated from each other, it is difficult for tungsten and the like frequently used as a gate electrode material to be etched via dry etching.

According to some embodiments, after first string selection line cut trenches SCT1are formed, the string selection line cut trenches SCT1undergo a subsequent process without being filled with an insulative material, and thus the uppermost sacrificial layer220between adjacent first string selection line cut trenches SCT1may be replaced by gate electrode material layers.

Referring toFIGS.9and16, in P160, the third upper substrate layer201cmay be formed. The formation of the third upper substrate layer201cmay include removing the upper substrate sacrificial layer202ofFIG.15Aand forming the third upper substrate layer201cin a space formed by removing the upper substrate sacrificial layer202.

After a word line cut liner material layer is formed in the first word line cut WLC1, a lower portion of the word line cut liner material layer is removed via an etchback process, thereby forming a word line cut liner PL. The word line cut liner PL may be a material having high etch selectivity with respect to the upper substrate sacrificial layer202ofFIG.15A. The sacrificial layers220are covered by the word line cut liner PL, but the upper substrate sacrificial layer202ofFIG.15Ais exposed. The word line cut liner PL may be a layer for protecting the sacrificial layers220in a process of removing the upper substrate sacrificial layer202ofFIG.15A. In an example embodiment, the upper substrate sacrificial layer202may be removed through the first word line cut trench WCT1using a wet etching process, for example. In this case, the upper substrate sacrificial layer200may have high etch selectivity with respect to the word line cut liner PL, the second upper substrate layer201band the first upper substrate layer201a.

The third upper substrate layer201cmay be formed in a space formed by selective removal of the upper substrate sacrificial layer202ofFIG.15A. As described above, the third upper substrate layer201cmay include polysilicon doped using substantially the same method as the first and second upper substrate layers201aand201b. At this time, the gate insulation layer251on the same level as the upper substrate sacrificial layer202ofFIG.15Amay be removed together with the upper substrate sacrificial layer202ofFIG.15A. Accordingly, the newly formed third upper substrate layer201ccontacts the channel layer253. Accordingly, a charge moving path for enabling the channel structures250to operate as memory cells may be formed.

Moreover, because the first upper substrate layer201aand the second upper substrate layer201bpartially contact each other, the first and second upper substrate layers201aand201band the stacked structure SS arranged thereon may be prevented from collapsing. After the third upper substrate layer201cis formed, the word line cut liner PL may be removed.

Referring toFIGS.9,17A, and17B, in P170, a gate electrode material layer EML may be formed on the resulting structure ofFIG.16after the word line cut liner PL is removed therefrom.

The gate electrode material layer EML may include a first barrier material layer, a second barrier material layer, and a gate conductive material layer corresponding to the first barrier241and the second barrier242ofFIG.4Band the gate conductive layer243ofFIG.4B, respectively. The first barrier material layer may include aluminum oxide, and the second barrier material layer may include aluminum nitride.

Referring toFIGS.9,18A, and18B, in P180, a node separation process may be performed.

The node separation process may be a process of removing the gate electrode material layer EML ofFIG.17A, which is exposed, via wet etching. Because the first barrier material layer corresponding to the first barrier241ofFIG.4Bis an oxide layer, the first barrier material layer may remain. Accordingly, as shown inFIG.4B, the first barrier241is disposed between the first and second upper insulation layers261and263and the string selection line cut insulation layer SSLCI. However, because the second barrier material layer and the gate conductive material layer corresponding to the second barrier242ofFIG.4Band the gate conductive layer243ofFIG.4Bhave properties of a metal layer, the second barrier material layer and the gate conductive material layer may be removed via the node separation process. Accordingly, each of the first string selection line cut trench SCT1and the first word line cut trench WCT1ofFIG.15Aexpands in a lateral direction and thus the second string selection line cut trench SCT2and a second word line cut trench WCT2ofFIG.18Amay be formed.

Then, referring toFIGS.9and19, in P190, a selection line cut insulative material may be formed.

The selection line cut insulative material may fill the second string selection line cut trench SCT2and the second word line cut trench WCT2ofFIG.18A. Accordingly, the string selection line cut insulation layer SSLCI, the word line cut insulation layer WLCI, and the third upper insulation layer265may be formed.

According to some embodiments, after the third upper insulation layer265is formed, the first bit line contact vias271penetrating the second upper insulation layer263and the third upper insulation layer265and contacting the channel layers253of the channel structures250may be further formed.

Then, referring toFIG.4A, the upper conductive pattern273, the second bit line contact vias275, and the bit line BL may be further formed. Accordingly, the semiconductor memory device10may be provided.

While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the present inventive concept. Thus, the above-described embodiments should be considered in descriptive sense only and not for purposes of limitation.