Patent ID: 12248869

DETAILED DESCRIPTION

In the following detailed description of the invention, numerous details, examples, and embodiments of the invention are set forth and described. However, it will be clear and apparent to one skilled in the art that the invention is not limited to the embodiments set forth and that the invention may be practiced without some of the specific details and examples discussed.

Some embodiments of the invention provide a three-dimensional (3D) circuit structure that uses latches to transfer signals between two bonded circuit layers. In some embodiments, this structure includes a first circuit partition on a first bonded layer and a second circuit partition on a second bonded layer. It also includes at least one latch to transfer signals between the first circuit partition on the first bonded layer and the second circuit partition on the second bonded layer. In some embodiments, the latch operates in (1) an open first mode (also called a transparent mode) that allows a signal to pass from the first circuit partition to the second circuit partition and (2) a closed second mode that maintains the signal passed through during the prior open first mode.

Unlike a flip-flop that releases in one clock cycle a signal that it stores in a prior clock cycle, a transparent latch does not introduce such a setup time delay in the design. In fact, by allowing the signal to pass through the first circuit partition to the second circuit partition during its open mode, the latch allows the signal to borrow time from a first portion of a clock cycle of the second circuit partition for a second portion of the clock cycle of the second circuit partition. This borrowing of time is referred to below as time borrowing. Also, this time borrowing allows the signal to be available at the destination node in the second circuit partition early so that the second circuit can act on it in the clock cycle that this signal is needed. Compared to flip-flops, latches also reduce the clock load because, while flip-flops require at least two different clock transitions to store and then release a value, transparent latches only require one signal transition to latch a value that they previously passed through.

The first and second bonded layers are different in different embodiments. In some embodiments, both bonded layers are integrated circuit (IC) dies. In other embodiments, both bonded layers are IC wafers. In still other embodiments, one of these bonded layers is an IC die, while the other bonded layer is an IC wafer. The first and second bonded layers are vertically stacked on top of each other with no other intervening bonded layers in some embodiments, while these two bonded layers have one or more intervening bonded layers between them in other embodiments.

In some embodiments, the 3D circuit has several such latches at several boundary nodes between different circuit partitions on different bonded layers. Each latch in some embodiments is associated with one pair of boundary nodes, with one node in the first bonded layer and another node in the second bonded layer. Each pair of nodes is electrically interconnected through a conductive interface, such as a through-silicon via (TSV) or a direct bond interface (DBI) connection. Each latch in some embodiments is defined on just one of the two bonded layers.

FIG.1illustrates an example of a 3D circuit structure that has several latches at several boundary nodes between the two bonded layers. This structure is a 3D IC100that is formed by vertically stacking two IC dies102and104. In this example, the two dies102and104have the same size and are aligned so that their bounding shapes overlap each other. This does not have to be the case, as in some embodiments, the different dies have different sizes and are vertically aligned differently.

InFIG.1, the 3D circuit structure100has several conductive vertical connections110that connect circuits on the two IC dies102and104. Examples of such connections include TSV s and DBI connections. DBI provides area-efficient, dense interconnect between two blocks. In two dimensions, the number of interconnects between two blocks is limited to the perimeter facing each other. Fine pitch 3D interface, on the other hand, is only limited by the area of the block overlap. For example, a 1×1 mm block with 100 nm wire pitch and 2 um DBI pitch can fit 10,000 wires through one side in a 2D format versus 250,000 wires spread across the entire block through DBI in a 3D format. DBI is further described in U.S. Pat. Nos. 6,962,835 and 7,485,968, both of which are incorporated herein by reference.

For each of several conductive vertical connections between two adjacent dies, one or both of the dies has a latch that electrically connects (through interconnect) to the conductive-interface connection. In some embodiments, each such latch iteratively operates in two sequential modes, an open first mode (also called a transparent mode) to let a signal pass from one circuit partition on one IC die to a circuit partition on the other IC die, and a closed second mode to hold the signal passed during the prior open first mode.

FIG.1illustrates one such latch132. This latch facilitates signal flow between a first node130in a first circuit block120on the IC die104to a second node138in a second circuit block122on the IC die102. This signal flow traverses along a conductive vertical connection110a(e.g., one DBI connection) between the IC dies102and104. As shown, this conductive vertical connection110aconnects two nodes on the two dies, a node134on die104and a node136on die102. In this example, the latch132on the IC dies104has its output carried to the IC die102by interconnect (e.g., wires) and the conductive vertical connection110a.

FIG.2illustrates how the latch132allows the signal traversing the two dies102and104to time borrow. Specifically, it shows the latch132operating in an open first phase202. During this phase, the latch is open and transparent. Thus, it allows a signal to pass from the first circuit partition120to location205in the second circuit partition122.FIG.2also shows the latch132operating in a closed second phase204. During this phase, the latch has closed. When the latch closes, it maintains the signal that passed through it during the prior open first phase. As shown, the signal reaches the node138during the second phase.

Because the latch was open during its first phase, the signal was allowed to pass through from the first circuit block120to the second circuit block in this phase, which, in turn, allowed the signal to reach its destination138in the second circuit block120sooner in the closed second phase204of the latch132. In this manner, the latch allows the signal to time borrow (e.g., borrow time from the first phase to speed up the operation of the second circuit block during the second phase).

Instead of placing a latch on the IC die layer from which the signal originates, some embodiments place the latch on the IC die layer on which the signal terminates.FIGS.3and4illustrate one such example. The example in this figure is similar to the example inFIGS.1and2, except that the latch132on the IC die104has been replaced with a latch342on the IC die102. This latch is used when a signal traverses from a node330on a circuit block320on the first die104along a vertical connection110bto node338on a circuit block322on the second die102. The vertical connection110bconnects two nodes334and336on the two dies105and102.

As shown inFIG.4, the latch342operates in an open first phase402. During this phase, the signal from a node330passes from the first circuit partition320to location405in the second circuit partition322. When the latch342closes (i.e., operates in the closed second phase404), the latch maintains the signal that passed through it during the prior open first phase to allow the signal to reach the node338during the second phase.

In other embodiments, a conductive vertical connection can be associated with two latches on the two bonded layers that it connects, and either latch can be used to facilitate time borrowing as a signal travels between the two circuit partitions on the two bonded layers through the conductive vertical connection. Thus, for the examples illustrated inFIGS.1-4, the 3D IC has both latches132and142respectively in circuit partitions120and122, and either of these latches can be selectively enabled to facilitate time borrowing across the two layers.

FIG.5illustrates an example of a transparent latch500. This latch is a D-latch that is formed by an inverter525, two AND gates535aand535b, and two XOR gates540aand540b. The inverter receives the input signal at its D terminal505and provides its output to an input of AND gate535a. The input signal is also fed to one of the inputs of the AND gate535b. The AND gates535aand535balso get a latch enable signal Eat the latch's enable terminal510. This enable signal can be a signal generated by another user-design circuit or a signal supplied by a clock or by a storage location driven by the clock or a user-design circuit.

The outputs of the AND gates535aand535bare supplied respectively to XOR gates540aand540b. These XOR gates are cross-coupled such that their outputs are fed back to the inputs of each other. The outputs of the XOR gates540aand540brepresent the output of the latch. When only one latch output is needed, the output of XOR gate540apresented at the Q terminal515of the latch serves as the output of the latch500. As shown by the truth table550inFIG.5, the latch operates in its open/transparent mode (to pass through a signal) when the enable signal is 1, while it operates in a close/latch mode (to maintain the signal previously passed) when the enable signal is 0.

Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. For instance, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combination of wafers and dies for the different bonded layers. Also, the machine-trained network includes an arrangement of processing nodes in some embodiments. In several examples described below, the processing nodes are neurons and the machine-trained network is a neural network. However, one of ordinary skill will realize that other embodiments are implemented with other machine-trained networks that have other kinds of machine-trained processing nodes.

FIG.6illustrates an example of a 3D circuit structure with a neural network on at least one of its bonded layers. In this example, the 3D circuit structure is a 3D IC600that has two vertically stacked dies602and604, with IC die604having a neural network605. In this example, the IC dies602and604have the same size and are aligned so that their bounding shapes overlap. This does not have to be the case, as in some embodiments, the different dies have different sizes and are vertically aligned differently. As shown inFIG.6, the IC dies602and604have several vertical connections, which in some embodiments are DBI connections. In other embodiments, these connections are other types of direct bonding connections or TSV connections.

As further shown, the neural network605in some embodiments includes several stages of neurons610with routing fabric that supplies the outputs of earlier stage neurons to drive the inputs of later stage neurons. In some embodiments, one or more parameters associated with each neuron is defined through machine-trained processes that define the values of these parameters in order to allow the neural network to perform particular operations (e.g., face recognition, voice recognition, etc.).

FIG.6illustrates an example of such machine-trained parameters for some embodiments. These parameters are the weight values Wi that are used to sum several output values Yi of several earlier stage neurons to produce an input value zifor an activation function625of a later stage neuron. In this example, the neural network is a feed-forward neural network that has multiple neurons arranged in multiple layers (multiple stages), with each neuron having a linear component620and a non-linear component625, called an activation function. In other embodiments, the neural network is not a feed forward network (e.g., is a recurrent network, etc.).

In all but the last layer of the feed-forward neural network605, each neuron610receives two or more outputs of neurons from earlier neuron layers (earlier neuron stages) and provides its output to one or more neurons in subsequent neuron layers (subsequent neuron stages). The outputs of the neurons in the last layer represent the output of the network605. In some embodiments, each output dimension of the network600is rounded to a quantized value.

The linear component (linear operator)620of each interior or output neuron computes a dot product of a vector of weight coefficients and a vector of output values of prior nodes, plus an offset. In other words, an interior or output neuron's linear operator computes a weighted sum of its inputs (which are outputs of the previous stage neurons that the linear operator receives) plus an offset. Similarly, the linear component620of each input stage neuron computes a dot product of a vector of weight coefficients and a vector of input values, plus an offset. Each neuron's nonlinear component (nonlinear activation operator)625computes a function based on the output of the neuron's linear component620. This function is commonly referred to as the activation function.

The notation ofFIG.6can be described as follows. Consider a neural network with L hidden layers (i.e., L layers that are not the input layer or the output layer). Hidden layers are also referred to as intermediate layers. The variable l can be any of the L hidden layers (i.e., l∈{1, . . . , L} index the hidden layers of the network). The variable Zi(l+1)represents the output of the linear component of an interior neuron i in layer l+1. As indicated by the following Equation (A), the variable Z(l+1)in some embodiments is computed as the dot product of a vector of weight values W(l)and a vector of outputs y(l)from layer l plus an offset bi, typically referred to as a bias.
Zi(l+1)=(Wi(l+1)·y(l))+bi(l+1)(A)

The symbol · is the dot product. The weight coefficients W(l)are weight values that can be adjusted during the network's training in order to configure this network to solve a particular problem. Other embodiments use other formulations than Equation (A) to compute the output Zi(l+1)of the linear operator620.

The output y(l+1)of the nonlinear component625of a neuron in layer l+1 is a function of the neuron's linear component, and can be expressed as by Equation (B) below.
yi(l+1)=ƒ(zi(l+1)),  (B)

In this equation, ƒ is the nonlinear activation function for node i. Examples of such activation functions include a sigmoid function (ƒ(x)=1/(1+e−x)), a tanh function, a ReLU (rectified linear unit) function or a leaky ReLU function.

Traditionally, the sigmoid function and the tanh function have been the activation functions of choice. More recently, the ReLU function has been proposed for the activation function in order to make it easier to compute the activation function. See Nair, Vinod and Hinton, Geoffrey E., “Rectified linear units improve restricted Boltzmann machines,” ICML, pp. 807-814, 2010. Even more recently, the leaky ReLU has been proposed in order to simplify the training of the processing nodes by replacing the flat section of the ReLU function with a section that has a slight slope. See He, Kaiming, Zhang, Xiangyu, Ren, Shaoqing, and Sun, Jian, “Delving deep into rectifiers: Surpassing human-level performance on imagenet classification,” arXiv preprint arXiv: 1502.01852, 2015. In some embodiments, the activation functions can be other types of functions, like cup functions and periodic functions.

Before the neural network605can be used to solve a particular problem (e.g., to perform face recognition), the network in some embodiments is put through a supervised training process that adjusts (i.e., trains) the network's configurable parameters (e.g., the weight coefficients of its linear components). The training process iteratively selects different input value sets with known output value sets. For each selected input value set, the training process in some embodiments forward propagates the input value set through the network's nodes to produce a computed output value set. For a batch of input value sets with known output value sets, the training process back propagates an error value that expresses the error (e.g., the difference) between the output value sets that the network605produces for the input value sets in the training batch and the known output value sets of these input value sets. This process of adjusting the configurable parameters of the machine-trained network605is referred to as supervised, machine training (or machine learning) of the neurons of the network605.

In some embodiments, the IC die on which the neural network is defined is an ASIC (Application Specific IC) and each neuron in this network is a computational unit that is custom-defined to operate as a neuron. Some embodiments implement a neural network by re-purposing (i.e., reconfiguring) one or more neurons used for earlier neural network stages to implement one or more neurons in later neural network stages. This allows fewer custom-defined neurons to be needed to implement the neural network. In such embodiments, the routing fabric between the neurons is at least partially defined by one or more output memories that are used to store the outputs of earlier stage neurons to feed the inputs of later stage neurons.

In some embodiments, the neural network includes a first sub-network on one bonded layer and a second sub-network on another bonded layer, with these two sub-networks partially or fully overlapping.FIG.7illustrates an example of such an embodiment. It shows a 3D IC700with a neural network that is formed by two sub-networks705and707. As shown, the first sub-network705is on a first IC die702while the second sub-network707is on a second IC die704. The footprints of these two sub-networks705and707on the two different IC dies702and704partially or fully overlap.

As further shown inFIG.7, the components on the IC's dies702and704are interconnected by several vertical connections710, which in some embodiments are DBI connections. In other embodiments, these connections are other types of direct bonding connections or TSV connections. As shown, numerous such connections710are used to electrically connect nodes on the two sub-networks705and707on the dies702and704.

In some embodiments, the sub-network705are the neurons that are used to implement the odd layer neurons in the multi-layer neuron arrangement (e.g., the multi-layer arrangement shown inFIG.6), while the sub-network707are the neurons that are used to implement the even layer neurons in this arrangement. In other embodiments, each sub-network has multiple layers (stages) of neurons (e.g., two layers of neurons) for implementing multiple adjacent layers of neurons (e.g., sub-network705implements even adjacent pairs of neuron layers, while sub-network707implements odd adjacent pairs of neuron layers, where even and odd layer pairs sequentially alternate and the first layer pair are the first two neuron layers).

In some embodiments, the vertical connections710connect the output of neurons of subnetwork705on the first IC die to an output memory on the second die that connects to the subnetwork707, so that these values can be stored in the output memory. From this memory, the stored output values are supplied to neurons of the sub-network707on the second die so that these neurons can perform computations based on the outputs of the neurons of the sub-network705that implement an earlier stage of the neural network's operation.

In some of these embodiments, the outputs of the neurons of the sub-network707are then passed through the vertical connections710to an output memory on the first die702that connects to the sub-network705. From the output memory on the first die702, the outputs of the neurons of the sub-network707of the second die are supplied to the neurons of the sub-network705of the first die once these neurons have been configured to perform the operation of later stage neurons of the neural network. Based on these outputs, the neurons of the sub-network705can then perform computations associated with the later stage neurons of the neural network. In this manner, the output values of the neurons of the sub-networks705and707can continue to pass back and forth between the two IC dies702and704as the neurons of each sub-network705and707are reconfigured to perform successive or successive sets (e.g., pairs) of stages of operation of the neural network.

Alternatively, or conjunctively, the neural network or sub-network on one bonded layer partially or fully overlaps a memory (e.g., formed by one or more memory arrays) on another bonded layer in some embodiments. This memory in some embodiments is a parameter memory that stores machine-trained parameters for configuring the neurons of the neural network or subnetwork to perform a particular operation. In other embodiments, this memory is an output memory that stores the outputs of the neurons (e.g., outputs of earlier stage neurons for later stage neurons).

While being vertically aligned with one memory, the neural network's neurons in some embodiments are on the same bonded layer with another memory.FIG.8illustrates one such example. It illustrates a 3D IC800with two IC dies802and804that have several components of the neural network. These components are several neurons805and an output memory812on the IC die804, and a parameter memory815on the IC die802. The output memory812stores values produced by the neurons805, while the parameter memory815stores machine-trained parameters for configuring the neurons. As shown, the footprints of arrangement of neurons805and the parameter memory815fully overlap in some embodiments. These footprints partially overlap in other embodiments, or do not overlap in yet other embodiments.

As further shown inFIG.8, the components on the IC's dies802and804are interconnected by several vertical connections810, which in some embodiments are DBI connections. In other embodiments, these connections are other types of direct bonding connections or TSV connections. As shown, numerous such connections810are used to electrically connect nodes of the neurons805on the IC die804to nodes of the parameter memory815on the IC die802. Through these connections, the neurons receive the machine-trained parameters that configure the neural network to perform a set of operations (e.g., a set of one or more tasks, such as face recognition) for which the neural network has been trained.

The neurons805connect to the output memory812through one or more interconnect layers (also called metal layers or wiring layers) of the IC die804. As known in the art, each IC die is manufactured with multiple interconnect layers that interconnect the circuit components (e.g., transistors) defined on the IC die's substrate. Through its connection with the output memory, the outputs of the neurons are stored so that these outputs can later be retrieved as inputs for later stage neurons or for the output of the neural network.

FIG.9illustrates another example of a 3D IC with different components of a neural network on different IC dies. This figure illustrates a 3D IC900with two IC dies902and904that have several components of the neural network. These components are several neurons905and a parameter memory915on the IC die904, and an output memory912on the IC die902. As shown, the footprints of arrangement of neurons905and the output memory912partially overlap in some embodiments. In other embodiments, these footprints fully overlap, while in yet other embodiments, they do not overlap.

As further shown inFIG.9, the components on the IC's dies902and904are interconnected by several vertical connections910, which in some embodiments are DBI connections. In other embodiments, these connections are other types of direct bonding connections or TSV connections. As shown, numerous such connections910are used to electrically connect nodes of the neurons905on the IC die904to nodes of the output memory912on the IC die902. Through these connections, the outputs of the neurons are stored so that these outputs can later be retrieved as inputs for later stage neurons or for the output of the neural network. As described above, the 3D IC of some embodiments has output memories and neurons on each of two face-to-face mounted dies (like dies902and904) with the output memory on each die receiving outputs from neurons on another die and providing its content to neurons on its own die.

The neurons905connect to the parameter memory915through one or more interconnect layers of the IC die904. Through its connection with the parameter memory, the neurons receive the machine-trained parameters (e.g., weight values for the linear operators of the neurons) that configure the neural network to perform a set of one or more tasks (e.g., face recognition) for which the neural network has been trained. When neurons are placed on both face-to-face mounted dies, some embodiments also place parameter memories on both dies in order to provide machine-trained parameters to neurons on the same IC die or to neurons on the other IC die.

FIG.10illustrates another example of a 3D IC with different components of a neural network on different IC dies. This figure illustrates a 3D IC1000with two IC dies1002and1004that have several components of the neural network. These components are several neurons1005on the IC die1004, and an output memory1012and a parameter memory1015on the IC die1002. As shown, the footprint of arrangement of neurons1005partially overlaps the output memory1012and the parameter memory1015.

As further shown inFIG.10, the components on the IC's dies1002and1004are interconnected by several vertical connections1010, which in some embodiments are DBI connections. In other embodiments, these connections are other types of direct bonding connections or TSV connections. As shown, numerous such connections1010are used to electrically connect nodes of the neurons1005on the IC die1004to either nodes of the output memory1012on the IC die1002, or to nodes of the parameter memory1015on the IC die1002. Through the connections1010with the output memory1012, the outputs of the neurons are stored so that these outputs can later be retrieved as inputs for later stage neurons or for the output of the neural network. Also, through the connections1010with the parameter memory1015, the neurons receive the machine-trained parameters (e.g., weight values for the linear operators of the neurons) that configure the neural network to perform a set of one or more tasks (e.g., face recognition) for which the neural network has been trained.

In some embodiments, the neurons on one bonded layer partially or fully overlap two memories on two different layers, with one memory storing machine-trained parameters and the other memory storing neuron output values.FIG.11illustrates one such example. This figure illustrates a 3D IC1100with multiple IC dies1102,1104, and1106, each of which has a component of the neural network. These components are several neurons1105on the IC die1104, an output memory1112on the IC die1102, and a parameter memory1115on the IC die1106. As shown, the footprints of the arrangement of neurons1105on the IC die1104and the output memory1112on the IC die1102partially or fully overlap. The footprint of the arrangement of neurons1105on the IC die1104also partially or fully overlaps with the footprint of the parameter memory1115on the IC die1106.

As further shown inFIG.11, the components on the IC's dies1102,1104, and1106are interconnected by several vertical connections1110and1111. In this example, IC dies1102and1104are face-to-face mounted, while the IC dies1106and1104are face-to-back mounted with the face of the IC die1106mounted with the back of the IC die1104. In some embodiments, the vertical connections1110between the dies1102and1104are direct bonded connections (like DBI connections), while the vertical connections1111between dies1104and1106are TSVs.

As shown, numerous such connections1110and1111are used to electrically connect nodes of the neurons1105on the IC die1104to either nodes of the output memory1112on the IC die1102, or to nodes of the parameter memory1115on the IC die1106. Through the connections1110with the output memory1112, the outputs of the neurons are stored so that these outputs can later be retrieved as inputs for later stage neurons or for the output of the neural network. Also, through the connections1111with the parameter memory1115, the neurons receive the machine-trained parameters that configure the neural network to perform a set of one or more tasks (e.g., face recognition) for which the neural network has been trained.

One of ordinary skill will realize that other permutations of 3D circuit structures are also possible. For instance, in some embodiments, the 3D circuit has neurons on two or more bonded layers with parameter and/or output memories on the same or different bonded layers. Also, in the above-described embodiments, the bonded layers (two or more) that contain a neural network's neurons and memories do not have any intervening bonded layer in some embodiments. In other embodiments, however, these bonded layers have one or more intervening bonded layers between or among them.

In some embodiments, the output and parameter memories of the neural network have different memory structures (i.e., are different types of memories). For instance, in some embodiments, the output memory (e.g., memory812,912,1012, or1112) has a different type of output interface than the parameter memory (e.g., the memory815,915,1015, or1115). For example, the output memory's output interface allows for random access of this memory's storage locations, while the parameter memory's output interface only supports sequential read access.

Alternatively, or conjunctively, the parameter memory (e.g., the memory815,915,1015, or1115) of the neural network is a read-only memory (ROM), while the output memory (e.g., memory812,912,1012, or1112) of the neural network is a read-write memory in some embodiments. The parameter memory in some embodiments is a sequential ROM that sequentially reads out locations in the ROM to output the parameters that configure the neural network to perform certain machine-trained task(s).

The output memory (e.g., memory812,912,1012, or1112) in some embodiments is a dynamic random access memory (DRAM). In other embodiments, the output memory is an ephemeral RAM (ERAM) that has one or more arrays of storage cells (e.g., capacitive cells) and pass transistors like traditional DRAMs. However, unlike traditional DRAMs, the ERAM output memory does not use read-independent refresh cycles to charge the storage cells. This is because the values in the ERAM output memory are written and read at such rates that these values do not need to be refreshed with separate refresh cycles. In other words, because intermediate output values of the neural network only need to be used as input into the next layer (or few layers) of the neural network, they are temporary in nature. Thus, the output memory can be implemented with a compact, DRAM-like memory architecture without the use of the read-independent refresh cycles of traditional DRAMs.

Using different dies for the output memory1112and parameter memory1115allows these dies to be manufactured by processes that are optimal for these types of memories. Similarly, using a different die for the neurons of the neural network than for the output memory and/or parameter memory also allows each of these components to be manufactured by processes that are optimal for each of these types of components.

FIG.12illustrates a device1200that uses a 3D IC1205, such as 3D IC100,600,700,800,900, or1000. In this example, the 3D IC1205is formed by two face-to-face mounted IC dies1202and1204that have numerous direct bonded connections1210between them. In other examples, the 3D IC1205includes three or more vertically stacked IC dies, such as the 3D IC1100. In some embodiments, the 3D IC1205implements a neural network that has gone through a machine-learning process to train its configurable components to perform a certain task (e.g., to perform face recognition).

As shown, the 3D IC1205includes a case1250(sometimes called a cap or epoxy packaging) that encapsulates the dies1202and1204of this IC in a secure housing1215. On the back side of the die1204one or more interconnect layers1206are defined to connect the 3D IC to a ball grid array1220that allows this to be mounted on a printed circuit board1230of the device1200. In some embodiments, the 3D IC includes packaging with a substrate on which the die1204is mounted (i.e., between the ball grid array and the IC die1204), while in other embodiments this packaging does not have any such substrate.

Some embodiments of the invention provide an integrated circuit (IC) with a defect-tolerant neural network. The neural network has one or more redundant neurons in some embodiments. After the IC is manufactured, a defective neuron in the neural network can be replaced by a redundant neuron (i.e., the redundant neuron can be assigned the operation of the defective neuron). The routing fabric of the neural network can be reconfigured so that it re-routes signals around the discarded, defective neuron. In some embodiments, the reconfigured routing fabric does not provide any signal to or forward any signal from the discarded, defective neuron, and instead provides signals to and forwards signals from the redundant neuron that takes the defective neuron's position in the neural network.

In the embodiments that implement a neural network by re-purposing (i.e., reconfiguring) one or more individual neurons to implement neurons of multiple stages of the neural network, the IC discards a defective neuron by removing it from the pool of neurons that it configures to perform the operation(s) of neurons in one or more stages of neurons, and assigning this defective neuron's configuration(s) (i.e., its machine-trained parameter set(s)) to a redundant neuron. In some of these embodiments, the IC would re-route around the defective neuron and route to the redundant neuron, by (1) supplying machine-trained parameters and input signals (e.g., previous stage neuron outputs) to the redundant neuron instead of supplying these parameters and signals to the defective neuron, and (2) storing the output(s) of the defective neuron instead of storing the output(s) of the defective neuron.

FIGS.13and14illustrate an example of one such neural network. These figures show a machine-trained circuit1300that has two sets of neurons1305and1310that are re-purposed (reconfigured) to implement a multi-stage neural network1350. In this example, the neural network1350has nine layers. Each of these neuron sets has one redundant neuron1325or1330to replace any defective neuron in its set, as further described below.

The machine-trained circuit1300has two parameter memories1315aand1315bthat respectively store machine-trained parameters for the neuron sets1305and1310. These machine-trained parameters iteratively configure each neuron set to implement a different stage in the multistage network. In the example illustrated inFIG.13, the parameters in memory1315astore parameters that sequentially re-configure the neuron set1305to implement the odd neuron layers (i.e., the first, third, fifth, seventh and ninth layers) of the neural network, while the memory1315bstores parameters that sequentially re-configure the neuron set1310to implement the even neuron layers (i.e., the second, fourth, sixth and eight layers). The parameters in the memories1315aand1315bwere generated through machine-learning processes, and configure the neurons in the sets1305and1310to perform a set of one or more operations (e.g., to perform face recognition or voice recognition).

The machine-trained circuit1300also has an output memory1312. The output of each neuron is stored in the output memory1312. With the exception of the neurons in the first neuron stage, the inputs of the neurons in the other stages are retrieved from the output memory. Based on their inputs, the neurons compute their outputs, which again are stored in the output memory1312for feeding the next stage neurons (when intermediate neurons compute the outputs) or for providing the output of the neural network (when the final stage neurons compute their outputs).

In some embodiments, all the components1305,1310,1312, and1315of the circuit1300are on one bonded layer (e.g., one IC die or wafer). In other embodiments, different components are on different layers. For instance, the neurons1305and1310can be on a different IC die than the IC die that includes one of the memories1312or1315, or both memories1312and1315. Alternatively, in some embodiments, the neurons1305are on one IC die while the neurons1310are on another IC die. In some of these embodiments, the IC die of neurons1305or neurons1310also include one or both of the parameter and output memories.

In the example illustrated inFIG.13, none of the neurons are defective. Hence, the redundant neurons1325and1330are not used to implement any of the neuron stages of the neural network1350.FIG.14, however, illustrates an example where one neuron1405in the first neuron set1305is defective and a neural network1450is implemented by using the redundant neuron1325of the first neuron set1305. This figure illustrates a machine-trained circuit1400that is identical to the machine-trained circuit1300, except that the neuron1405in the first neuron set1305is defective.

To address this defect, a defect-curing process that configures the circuit1400removes the defective neuron1405from the first neuron set and replaces this defective neuron with the redundant neuron1325of this set. The defect-curing process assigns to the redundant neuron the machine-trained parameters that would have been assigned to the defective neuron, in order to allow this neuron to implement one of the neurons in the odd stages of the neural network1450. This process also changes the storage and retrieval logic of the machine-trained circuit1400to ensure that the redundant neuron1325receives the desired input from and stores its output in the output memory1312.FIG.14shows the neural network1450implemented with the set of neurons1305R implementing the odd stages of this network. Here, the designation R is indicative that the neuron set1305is using its redundant neuron1325.

FIG.15illustrates a defect-curing process1500of some embodiments. In some embodiments, this process is performed each time the IC with the neural network is initializing (i.e., is powering up). The process1500initially determines (at1505) whether a setting stored on the IC indicates that one or more neurons are defective. In some embodiments, this setting is stored in a ROM of the IC during a testing phase of the IC after it has been manufactured. This testing phase identifies defective neurons and stores the identity of the defective neuron on the ROM in some embodiments. If only one redundant neuron exists for each neuron set (e.g.,1305or1310) of the IC, the testing process in some embodiments discards any IC with more than one defective neuron in each neuron set.

When the setting does not identify any defective neuron, the process1500loads (at1515) the settings that allow the neurons to be configured with a user-design that has been provided in order to configure the neural network to implement a set of operations. After1515, the process ends. On the other hand, when the setting identifies a defective neuron, the process1500removes (at1520) the defective neuron from the pool of neurons, and replaces (at1520) this defective neuron with the redundant neuron. The defect-curing process then assigns (at1525) to the redundant neuron the machine-trained parameters that would have been assigned to the defective neuron to allow this neuron to implement operations of the defective neuron that are needed to implement the neural network. At1530, the process changes the storage and retrieval logic of the machine-trained circuit to ensure that the redundant neuron receives the desired input from and stores its output in the output memory. Finally, at1535, the process1500directs the neural network to start operating based on the new settings that were specified at1525and1530. After1335, the process ends.

While the invention has been described with reference to numerous specific details, one of ordinary skill in the art will recognize that the invention can be embodied in other specific forms without departing from the spirit of the invention. For instance, one of ordinary skill will understand that while several embodiments of the invention have been described above by reference to machine-trained neural networks with neurons, other embodiments of the invention are implemented on other machine-trained networks with other kinds of machine-trained processing nodes.

The 3D circuits and ICs of some embodiments have been described by reference to several 3D structures with vertically aligned IC dies. However, other embodiments are implemented with a myriad of other 3D structures. For example, in some embodiments, the 3D circuits are formed with multiple smaller dies placed on a larger die or wafer. Also, some embodiments are implemented in a 3D structure that is formed by vertically stacking two sets of vertically stacked multi-die structures. Therefore, one of ordinary skill in the art would understand that the invention is not to be limited by the foregoing illustrative details, but rather is to be defined by the appended claims.