Patent ID: 12255189

DETAILED DESCRIPTION OF THE INVENTION

The various embodiments are described more fully with reference to the accompanying drawings. These example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to readers of this specification having knowledge in the technical field. Like numbers refer to like elements throughout.

Semiconductor packages are described which increase the density of electronic components within. The semiconductor package may incorporate interposers having a multitude of redistribution layers. Relatively narrow and laterally elongated interposers to form the indentations used to house the electronic components. The height of the clearance may be equal to the height of the standoff interposers. The semiconductor package designs described herein may be used to reduce footprint, reduce profile and increase electronic component and transistor density for semiconductor products. The spaces and clearances may form a conduit configured to promote fluid flow and enhance cooling of the electronic components during operation in embodiments.

In some embodiments, the semiconductor packages described herein possess cavities and/or standoff interposers (generally referred to herein as interposer) to create spaces for a plurality of electronic components in a high density and high performance configuration. In some embodiments, the semiconductor packages described may result in a smaller footprint, lower profile, miniaturized, higher performance thermally enhanced, and more secured packages. The packages may involve a combination of interposers, redistribution layers (RDL), zero-ohm links, copper pillars, solder bumps, compression bonding, and bumpless packaging. In addition to these techniques, cavities may be made into the interposer and/or substrate, and/or standoff interposers and secondary or side substrate may be used to provide spaces (clearance) for a plurality of electronic components (e.g., passives, antennas, integrated circuits or chips) in embodiments. The standoff interposers and secondary or side substrate may include RDL on the top and/or bottom. Standoff interposers may be formed, for example, by bonding multiple interposers together by thermocompression bonding or another low-profile connection technique. Oxide bonding techniques or laterally shifting any standoff interposer described herein enable wirebonds to be used to connect the standoff interposer to a printed circuit board, or substrate, or an underlying interposer in embodiments. Generally speaking, any interposer described herein may be shifted relative to the other interposers in the stack to allow the formation of wirebonds. The semiconductor interposer may be a silicon interposer according to embodiments.

A method of creating a scalable 2.5D/3D structure which requires no TSVs is disclosed. This method uses various combinations of wirebond, flip chip bumping, redistribution layer (RDL) with or without RDL vias to transition signals or supplies In other words, signals and supplies are routed through the RDL layers, thus eliminating TSV usage and reducing the cost of manufacturing and improving performance. In addition, an improved method of solder joint reliability is disclosed. Surfaces of assemblies disclosed herein maybe be covered with a high-Z material to create a radiation harden component.

Electronic packages formed in the manner described herein possess improved reliability, lower cost, and higher performance due to a shortening of electrical distance and an increase in density of integrated circuit mounting locations. Reliability may be improved for embodiments which use the same semiconductor (e.g., silicon) for all interposer used to form the semiconductor package. The techniques presented also provide improved in solder joint reliability and a reduction in warpage. Warping may occur during the wafer processing and thinning of the semiconductor interposer. The second opportunity for warping occurs during the package and assembly. The chance of warping increases for larger interposer lengths and package dimensions which is currently necessary for a variety of 2.5D/3D integration applications (e.g., networking). The vertical density of integrated circuits may be increased which allows the horizontal area to be reduced to achieve the same performance.

When describing all embodiments herein, “top” and “up” will be used herein to describe portions/directions perpendicularly distal from the printed circuit board (PCB) plan and further away from the center of mass of the PCB in the perpendicular direction. “Vertical” will be used to describe items aligned in the “up” direction towards the “top.” Other similar terms may be used whose meanings will now be clear. “Major planes” of objects will be defined as the plane which intersects the largest area of an object such as an interposer. Some standoff interposers may be “aligned” in “lines” along the longest of the three dimensions and may therefore be referred to as “linear” standoff interposers. Electrical connections may be made between interposers (standoff or planar interposer) and the pitch of the electrical connections may be between 1 micron and 50 micron or between 10 micron and 100 micron in some embodiments. Electrical connections between neighboring semiconductor interposers herein may be direct ohmic contacts which may include direct bonding/oxide bonding or adding a small amount of metal such as a pad. In the following it is understood that a substrate includes metal layers, vias and other passive components used for transfer of signals.

FIG.1Ais a side view of a TSV-less (i.e., without any through silicon vias) assembly55(alternatively referred to herein as structure) in accordance with an exemplary embodiment of the present invention. Assembly55is shown as including, in part, a semiconductor die50mounted on a interposer90via a multitude of electrical signal conductors (e.g., bumps). Interporser90is further shown, as including, in part, one or more redistribution layers60(RDL), and a substrate70. Although for simplicity only one such redistribution layer is shown inFIG.1A, it is understood that layer60may include any number of redistribution later, collectively referred to herein as a redistribution layer.

Redistribution layer(s)60is shown as including 5 metal layers62,64,65,66,68used to transfer signals to and from semiconductor die50, as described further below.FIG.1Bis a side view of another substrate94having a multitude of electrical signal conductors99and a cavity96adapted to receive assembly55therein.FIG.1Cshows assembly55after being disposed in cavity94. A multitude of wirebonds (two which, namely wirebonds97and98are shown inFIG.1C) may be used to transfer signals to and from silicon die50via the metal layers disposed in RDL60. Alternatively, a flip-chip substrate (not shown) may be used in place of the wirebonds to transfer signals between silicon die50and substrate94over cavity96. Although for simplicity only five metal layers are shown in redistribution layer60, it is understood that layer60may include any number of metal layers.

FIG.1Eis a side view of a TSV-less assembly100in accordance with another exemplary embodiment of the present invention. Assembly100is shown as including, in part, semiconductor dies (device)50and52mounted on interposer90. Although exemplary embodiment of assembly100is shown as including only two semiconductor devices, it is understood that an assembly, in accordance with embodiments of the present invention, may have any number of semiconductor devices.

Semiconductor device50is shown as communicating with other devices, such as device52, or to receive voltage/current supplies via a multitude of electrical signal conductors58. Likewise, semiconductor device52is shown as communicating with other devices, such as device50, or to receive voltage/current supplies via a multitude of electrical signal conductors78. Interposer90is further shown, as including, in part, one or more redistribution layers60(RDL), and a substrate70. Although for simplicity only one such redistribution layer is shown inFIG.1E, it is understood that layer60may include any number of redistribution later. Redistribution layer(s)60is shown as including 5 metal layers62,64,65,66,68used to transfer signals to and from semiconductor devices50,52.

FIG.1Fis a side view of a substrate94having a multitude of electrical signal conductors99and a cavity96adapted to receive assembly100therein.FIG.1Gshows assembly100after being disposed in cavity94. A multitude of wirebonds (two which, namely wirebonds97and98are shown inFIG.1C) may be used to transfer signals to, from or between silicon devices50,52via the metal layers disposed in RDL60. Alternatively, a flip-chip substrate (not shown) may be used in place of the wirebonds to transfer signals to, from or between silicon devices50,52and substrate94over cavity96. Although for simplicity only five metal layers are shown in redistribution layer60, it is understood that layer60may include any number of metal layers.FIG.1His a top view of an exemplary embodiment of assembly100, showing devices50and52, top metal layers62, wirebonds97,98, and bonding pads93.

FIG.2Ashows an assembly210in accordance with another embodiment of the present invention. Devices227,229together with interposer225form an assembly235that corresponds to and is formed in the same manner as assembly100shown inFIG.1F. Similarly, devices230,240together with interposer220form an assembly245that corresponds to and is formed in the same manner as assembly100shown inFIG.1F. Assemblies235and245are mounted to substrate214to from an assembly210. Devices229,227,240and230of assembly210are adapted to communicate with one another via wirebonds250,260and the redistribution layers disposed in interposers220and225. Electrical signal conductors233(e.g., BGA) facilitate communication between the devices disposed in assembly210and devices not formed on assembly210.

FIG.2Bshows an assembly270in accordance with another embodiment of the present invention. Assembly270is shown, as including, in part, two assemblies235A and235, each of which corresponds to assembly235shown inFIG.2A. The devices disposed in assemblies235A and235B are adapted to communicate with one another via wirebonds250,260and the redistribution layers disposed in their respective interposers220and225. Electrical signal conductors290(e.g., BGA) facilitate communication between the devices disposed in assembly270and devices not formed on assembly270. In one embodiment, substrates275disposed between assemblies235A and235surrounds interposers220and the devices mounted there to inhibit access to these devices. In yet another embodiment, substrates275is disposed along one of the edges of assembly235to enable airflow between assemblies235A and235so as to allow for heat flow and dissipation. The following embodiments of the present invention are similar in many aspects to those described above with reference toFIGS.1A,1B,1C,1D,1E,1F,1G,1H,2A,2B; accordingly, for simplicity and clarity, in the following and where applicable, only the differences between such embodiments are described. It is also understood that similar reference numbers may be used to identify the same elements in the Figures.

FIG.3Ais a cross-section view of stacking of interposers in accordance with an exemplary embodiment. An assembly310may include in part multiple assemblies, for example one according to assembly105and one according to assembly210, stacked and separated using a BGA315having a ball size and pitch appropriate for providing enough clearance so that devices of the assemblies fit and function properly. Assembly210has clearance from substrate330due to BGA320.

FIG.3Bis a cross-section view of stacking or interposers, using larger BGA ball sizes, in accordance with an exemplary embodiment. An assembly350comprises stacked assemblies according to assembly210. BGAs340and345provide clearance for the stacked assemblies between one another and substrate355. BGAs340and345have a larger ball size and pitch, appropriate for providing enough clearance so that devices of the assemblies fit and function properly.

FIG.3Cis a cross-section view of stacking of interposers, using smaller BGA ball sizes, in accordance with an exemplary embodiment. An assembly360comprises stacked assemblies according to assembly210. The two assemblies are shown as separated by a thin side-substrate380and BGAs having smaller ball size and pitch. Larger BGA370provides clearance from substrate390.

FIG.4illustrates arrangements of bump patterns used to mask critical signals and/or supplies in accordance with an exemplary embodiment. Bump pattern420includes in part critical signals or supplies460and non-critical signals or supplies470. According to one embodiment of the invention, critical signal/supply bumps460or traces may be shielded against probing or tampering by placing the critical signal or supply bumps on an inner most line of bumps, namely bumps441-446while the non-critical signals or supplies470are placed on an outer most line of bumps. Similarly, bump pattern410includes in part critical signals or supplies440, and non-critical signals or supplies430,450. Similarly, signals451-457are shielded from probing or tampering by placing these signals on innermost line of the bumps. In another embodiment of this invention, critical signals or supplies440may be positioned on a line of bumps between the non-critical signals or supplies430and450.

FIG.5Ais an exemplary embodiment of an assembly in accordance with another exemplary embodiment of the present invention. Substrate94is adapted to have a cavity95adapted to receive assembly100(SeeFIG.1E) and cavities520disposed either along the periphery or opposite edges of substrate94to receive bumps538also formed on assembly538. Since bumps58,78, and538are fully embedded within the walls of substrate94, the signals used by devices50and52are shielded from tampering.FIG.5Bshows various components ofFIG.5Aafter they have been assembled together to form assembly540.FIGS.6A and6Bare respectively similar toFIGS.5A and5Bexcept that inFIGS.6A and6B, bumps538are not placed in a cavity.FIG.7shows two assemblies640(seeFIG.6B) that are stacked together but separated via substrate710.

The assembly shown inFIG.8Bis similar to that shown inFIG.8Aexcept that in the assembly ofFIG.8B, semiconductor devices50,52, interposer90, and a portion of each of substrates45,48is disposed on a copper layer550. The remaining portions of substrates45and48are disposed on substrates552and554. Substrate94is disposed above devices50,52and substrates45,48. Bumps560are used to transfer signals to or from devices50,52to bumps99for communication with devices external to the assembly. It is understood that transfer of signals between bumps560and99is facilitated through signal traces formed in PCB or substrate94using vias, and the like. The assembly ofFIG.9is similar to that shown inFIG.8Bexcept that inFIG.9wirebonds935are used to transfer signals between various metal layers disposed in interposer90and bumps560.

FIG.10Ais an exemplary embodiment of an assembly1000, in accordance with another embodiment of the present invention. Assembly1000includes, in part, a pair of substrates94A and94B (each corresponding to substrate90as described above). Each substrate has a cavity formed on its top and bottom surfaces. For example, substrate90A is shown as including a cavity96Atopformed on its top surface and a cavity96Abottomformed on its bottom surface. Likewise, substrate90B is shown as including a cavity96Btopformed on its top surface and a cavity96Bbottomformed on its bottom surface. Interposer90Atophas devices50Atop,52Atopas well as substrates45Atop,48Atopdisposed thereon. Interposer90Abottomhas devices50Abottom,52Abottomas well as substrates45Abottom,48Abottomdisposed thereon. Interposers90Btopand90Bbottomhave similar devices and substrates thereon as shown. Bumps610,620,630and640together with substrates45Atop,48Atop45Abottom,48Abottomare used to facilitate signal transfer between the devices shown as well as devices external to assembly1000. InFIG.10, a copper heat spreader is disposed below substrates45Abottom,48Abottomand devices50Abottomand52Abottom. It is understood however, that a copper hear spreader may be disposed in other layers.

FIG.10Billustrates stacking and scaling up low profile thermally enhanced and secured interconnects in accordance with an exemplary embodiment. In this example, there are no cavities in the substrate1050, instead an interposer1055is attached to a copper heat spreader1060which is attached to side substrate1065. It is understood that interposer1055does not have any TSVs. A secondary flip chip substrate1070is used to route the signals and supplies from the interposer1055the side-substrate1065. In another embodiment, wirebonds are used to connect the interposer1055to the side-substrate1065instead of secondary flip chip substrates1070.

FIG.11is a cross-section of a substrate connector used to route signals and supplies over a cavity in accordance with an exemplary embodiment. Substrate connector1140includes an array of fine pitch bumps1130and an array of coarse pitch bumps1120. A gap1110between the fine pitch bumps1130and the coarse pitch bumps1120provides a bridge for connecting over a cavity.

FIG.12is a cross-section of a substrate connector used to route signals and supplies over a cavity in accordance with an exemplary embodiment. Substrate connector1140includes a first array of fine pitch bumps1130and a second array of fine pitch bumps1150. A gap1110between the first array of fine pitch bumps1130and the second array of fine pitch bumps1150provides a bridge for connecting over a cavity.

FIG.13Ais a bump joint assembly between two substrates according to prior art. Substrate1320and substrate1310are connected using bump1330.FIG.13Bis a bump joint assembly between a substrate and a die according to prior art. Substrate1320and die1340are connected using bump1330.FIG.13Cis a bump joint assembly between two die according to prior art. Die1340and die1350are connected using bump1330.

FIG.14is a top view of a landing pad used to connect components, and side view of a plurality of holes shape and depth used to enforce a connection between components in accordance with an exemplary embodiment. Landing pad1410includes a hole1420. Landing pad1410can also include a hole1430that has a different shape and depth than hole1420. Similarly, landing pad1410can have a hole1440that has a different shape and depth than holes1420and1430.

FIG.15Ais a top view of a plurality of holes with uniform pitch, shape and depth in accordance with an exemplary embodiment. Landing pad1510includes an array of holes1515, each having the same pitch, shape, and depth.

FIG.15Bis a top view of a plurality of holes with varying pitch, shape and depth in accordance with an exemplary embodiment. Landing pad1520includes an array of holes, including holes1530,1540,1550and1560having varying pitch, shape, and depth.

FIG.16illustrates an assembly process used to assemble mask defined components and substrates without under bump metallization (UBM) in accordance with an exemplary embodiment. Components1610and1620are assembled using bumps1630and1640and spaced apart by spacers1660. The bumps1630and1640are placed partially inside a through hole with proper depth. After process reflow, the bumps1630and1640are melted and joined together to form a connection1670between the components1610and1620.

FIG.17illustrates an assembly process used to assemble mask defined components and substrates in accordance with an exemplary embodiment. Components1710and1720are assembled together using bumps1730and1740. Conductive material1750partially fills a mask defined hole. After a reflow the bumps1730and1740are melted and joined together to form a connection between components1710and1720.

FIG.18Aillustrates a plurality of wirebonded dies placed inside a substrate cavity in accordance with an exemplary embodiment. Assembly1810includes a substrate1820with a cavity1825created therein. Devices1830and1835are wirebonded1840to substrate1820.

FIG.18Billustrates a plurality of wirebonded dies placed on a copper heat spreader in accordance with an exemplary embodiment. In assembly1850, devices1860and1865are placed on a copper heat spreader1855(or substrate) and wirebonded1885to substrate1870. A substrate1875is assembled to substrate1870using bumps1880.

FIG.19Aillustrates a plurality of wirebonded dies placed side by side inside a substrate cavity in accordance with an exemplary embodiment. Assembly1910includes a stack of assemblies having a substrate1915with a cavity1920created therein. Multiple devices1925can be placed in the cavity1920and wirebonded1930to the substrate1915. Assemblies are stacked and separated using bumps1935.

FIG.19Billustrates a plurality of wirebonded dies placed inside a substrate cavity side by side and on top of each other in accordance with an exemplary embodiment. Assembly1940is similar to assembly1910, except multiple devices1945are placed on top of one another within the substrate cavity.

FIG.19Cillustrates a plurality of wirebonded dies placed side by side inside substrate cavities in accordance with an exemplary embodiment. Assembly1950comprises multiple stacked assemblies, each including a substrate having multiple cavities created therein. Devices are placed side by side within the cavities and are wirebonded to the substrate.

FIG.19Dillustrates a plurality of wirebonded dies placed side by side and on top of each other inside substrate cavities in accordance with an exemplary embodiment. Assembly1960comprises multiple stacked assemblies and is similar to assembly1950except multiple devices are placed on top of one another within the substrate cavities.

It is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.

Having disclosed several embodiments, it will be recognized by those of skill in the art that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the disclosed embodiments. Additionally, a number of well-known processes and elements have not been described to avoid unnecessarily obscuring the embodiments described herein. Accordingly, the above description should not be taken as limiting the scope of the claims.

Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Each smaller range between any stated value or intervening value in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of these smaller ranges may independently be included or excluded in the range, and each range where either, neither or both limits are included in the smaller ranges is also encompassed within the embodiments described, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

As used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a process” includes a plurality of such processes and reference to “the dielectric material” includes reference to one or more dielectric materials and equivalents thereof known to those skilled in the art, and so forth.

Also, the words “comprise,” “comprising,” “include,” “including,” and “includes” when used in this specification and in the following claims are intended to specify the presence of stated features, integers, components, or steps, but they do not preclude the presence or addition of one or more other features, integers, components, steps, acts, or groups.