Patent ID: 12193235

DETAILED DESCRIPTION

Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, “at least one of A, B, and C,” “at least one of A, B, or C,” “one of A, B, C, or a combination thereof,” and “one of A, B, C, and a combination thereof,” respectively, may be construed as covering any one of the following combinations: A; B; A and B; A and C; B and C; and A, B, and C.”

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. The embodiments to be described are merely examples, and various modifications may be made from the embodiments. In the following drawings, the same reference numerals refer to the same components, and a size of each component in the drawings may be exaggerated for the sake of clear and convenient description.

Hereinafter, what is described as “upper portion” or “on” may also include not only components directly thereon in contact therewith but also components thereon without being in contact therewith.

Terms such as first and second may be used to describe various components but are used only for the purpose of distinguishing one component from another component. These terms are not intended to limit differences in materials or structures of components.

Singular expressions include plural expressions unless the context clearly indicates otherwise. In addition, when a portion “includes” a certain component, this means that other components may be further included rather than excluding other components unless specifically stated to the contrary.

In addition, terms such as “ . . . unit”, “ . . . portion”, and “module” described in the specification mean units that process at least one function or operation, which may be implemented as hardware or software, or as a combination of hardware and software.

Use of a term “the” and similar reference terms may correspond to both the singular and the plural.

Steps constituting a method may be performed in any suitable order unless there is a clear statement that the steps constituting the method should be performed in the order described. In addition, use of all example terms (for example, and so on) is merely for describing technical ideas in detail, and the scope of claims is not limited by the terms unless limited by the claims.

FIG.1is a cross-sectional view illustrating a schematic structure of a nonvolatile memory device100according to an embodiment, andFIG.2is a perspective view illustrating a schematic structure of a memory string included in the nonvolatile memory device100ofFIG.1.FIG.3is an equivalent circuit diagram of the nonvolatile memory device100ofFIG.1.

The nonvolatile memory device100according to the present embodiment may be a vertical NAND (VNAND) memory in which a plurality of memory cells MC are vertically arrayed.

A detailed configuration of the nonvolatile memory device100will be described below with reference toFIGS.1to3. First, referring toFIG.1, a plurality of cell strings are formed on a substrate101.

The substrate101may include a semiconductor material doped with a first type impurity. For example, the substrate101may include a silicon material doped with a p-type impurity. For example, the substrate101may be a p-type well (for example, a pocket p-well). Hereinafter, it is assumed that the substrate101is p-type silicon. However, the substrate101is not limited to p-type silicon.

A doped region102is provided in the substrate101. For example, the doped region102may be doped with a second type impurity that is different from the substrate101. For example, the doped region102may be doped with an n-type impurity. Hereinafter, it is assumed that the doped region102may be doped with an n-type impurity. However, the doped region102is not limited to an n-type impurity. The doped region102may be connected to a common source line CSL.

k*n cell strings CS may be provided and arranged in a matrix as illustrated in the circuit diagram ofFIG.3and may be referred to as CSij (1≤i≤k and 1≤j≤n) depending on the positions of respective rows and columns. Each of the cell strings CSij is connected to a bit line BL, a string select line SSL, a word line WL, and the common source line CSL.

Each of the cell strings CSij includes memory cells MC and a string select transistor SST. The memory cells MC of each of the cell strings CSij and the string select transistor SST may be stacked in a height direction.

Rows of the plurality of cell strings CS are respectively connected to string select lines SSL1to SSLk that are different from each other. For example, the string select transistors SST of the cell strings CS11to CS1nare commonly connected to the string select line SSL1. The string select transistors SST of the cell strings CSk1to CSkn are commonly connected to the string select line SSLk.

Columns of the plurality of cell strings CS are respectively connected to bit lines190or BL1to BLn. For example, the memory cells MC and the string select transistors SST of the cell strings CS11to CSk1may be commonly connected to the bit line190or BL1, and the memory cells MC and the string select transistors SST of the cell strings CS1nto CSkn may be commonly connected to the bit line190or BLn.

The rows of the plurality of cell strings CS may be respectively connected to the common source lines CSL1to CSLk that are different from each other. For example, the string select transistors SST of the cell strings CS11to CS1nmay be commonly connected to the common source line CSL1, and the string select transistors SST of the cell strings CSk1to CSkn may be commonly connected to the common source line CSLk.

The memory cells MC at the same height from the substrate101or the string select transistors SST may be commonly connected to one word line WL, and the memory cells MC at different heights may be respectively connected to the word lines WL1to WLm that are different from each other.

The illustrated circuit structure is an example. For example, the number of rows of the cell strings CS may be increased or decreased. As the number of rows of the cell string CS is changed, the number of string select lines connected to the rows of the cell string CS and the number of cell strings CS connected to one bit line190also may be changed. As the number of rows of the cell strings CS is changed, the number of common source lines connected to the rows of the cell strings CS also may be changed.

The number of columns of the cell strings CS also may be increased or decreased. As the number of columns of the cell string CS is changed, the number of bit lines190connected to the columns of the cell strings CS and the number of cell strings CS connected to one string select line also may be changed.

Heights of the cell strings CS also may be increased or decreased. For example, the number of stacked memory cells MC in each of the cell strings CS may be increased or decreased. As the number of stacked memory cells MC in each of the cell strings CS is changed, the number of word lines WL also may be changed. For example, the number of string select transistors provided to each of the cell strings CS may be increased. As the number of string select transistors provided to each of the cell strings CS is changed, the number of string select lines or the number of common source lines also may be changed. When the number of string select transistors is increased, the string select transistors may be stacked in the same shape as the memory cells MC.

For example, write and read may be performed in units of rows of the cell strings CS. The cell strings CS may be selected in units of rows by the common source line CSL, and the cell strings CS may be selected in units of one row by the string select lines SSL. In addition, a voltage may be applied to the common source lines CSL in a state in which at least two common source lines are set as a unit. The voltage may be applied to the common source lines CSL in a state in which all the common source lines CSL are set as a unit.

In the selected row of the cell strings CS, write and read may be performed in units of pages. A page may be one row of memory cells connected to one word line WL. In the selected row of cell strings CS, memory cells may be selected in units of pages by the word lines WL.

As illustrated inFIG.1, the cell string CS includes a cylindrical channel hole, and a plurality of gate electrodes110and a plurality of separation layers120surrounding the cylindrical channel hole CH in a ring shape. The plurality of gate electrodes110and the plurality of separation layers120may be alternately stacked with each other in a vertical direction (Z direction).

Each of the gate electrodes110may be formed of a metal material or a silicon material doped with a high concentration. Each of the gate electrodes110is connected to one of the word line WL and the string select line SSL.

The separation layers120may serve as spacers for insulation between conductive layers. The separation layers120will be described below.

The separation layers120and the gate electrodes110are formed such that the channel hole CH passes therethrough. Here, the channel hole CH may be formed to extend in a direction (that is, the z-axis direction inFIG.2) perpendicular to a surface of the substrate101. The channel hole CH may be formed to have a circular cross-section.

A charge blocking layer130, a charge trap layer140, a charge tunneling layer150, and a channel layer160are sequentially provided on an inner wall of the channel hole CH. Here, when a certain voltage is applied to the gate electrode110, electric charges flowing between a source and a drain180on the channel layer160pass through the charge tunneling layer150and are trapped in the charge trap layer140, and thus, information is stored.

Each of the charge blocking layer130, the charge trap layer140, and the charge tunneling layer150may be provided to extend in a direction perpendicular to a surface of the substrate101. Each of the charge blocking layer130, the charge trap layer140, and the charge tunneling layer150may be provided to have a cylindrical shape.

The charge blocking layer130may be provided on the inner wall of the channel hole CH to be in contact with the separation layer120and the gate electrode110.

The channel layer160may include a semiconductor material doped with a first type impurity. The channel layer160may include a silicon material doped with the same type of impurity as the substrate101, and for example, when the substrate101includes a silicon material doped with a p-type impurity, the channel layer160may also include the silicon material doped with the p-type impurity. Alternatively, the channel layer160may also include a material such as Ge, IGZO, or GaAs. The channel layer160may have a cylindrical shape.

The inside of the channel layer160may be filled with a filling layer170. The filling layer170may include, for example, silicon oxide or air, but is not limited thereto.

The channel layer160may be in contact with the doped region102, that is, a common source region.

The drain180may be provided in the channel hole CH. The drain180may include a silicon material doped with a second type impurity. For example, the drain180may include a silicon material doped with an n-type impurity.

The bit line190may be provided on the drain180. The drain180and the bit line190may be connected to each other through a contact plug.

Each of the gate electrodes110, and the separation layer120, and the channel layer160at positions facing the gate electrode110in the horizontal direction (X direction) may constitute the memory cell MC. That is, the memory cell MC may have a circuit structure in which a transistor including the gate electrode110, the separation layer120, and the channel layer160is connected in parallel to the charge trap layer140.

The memory cells MC are continuously arranged in the vertical direction (Z direction) to constitute the cell string CS. In addition, both ends of the cell string CS may be connected to the common source line CSL and the bit line BL, as illustrated in the circuit diagram ofFIG.3. By applying a voltage to the common source line CSL and the bit line BL, a program process, a read process, and an erasure process may be performed on the plurality of memory cells MC.

For example, when the memory cell MC to be written is selected, a gate voltage value of the cell is adjusted such that a channel is not formed in the selected cell, that is, the channel is off, and the gate voltage values of unselected cells are adjusted such that channels are on. Accordingly, a current path by a voltage applied to the common source line CSL and the bit line BL passes through the selected memory cell MC, and in this case, the applied voltage may be set to Vset or Vreset to cause the memory cell MC to be in a low resistance state or a high resistance state, and desirable information of 1 or 0 may be written to the selected memory cell MC.

During a read operation, a read of a selected memory cell may be performed similarly thereto. That is, after a gate voltage applied to the gate electrode110is adjusted such that the selected memory cell MC is in a channel-off state and the unselected memory cells are in a channel-on state, a memory cell state (1 or 0) may be checked by measuring a current flowing through the memory cell MC due to an application voltage Vread between the common source line CSL and the bit line BL.

The nonvolatile memory device100according to an embodiment has a structure in which memory cells are vertically connected to each other. When information is stored, electric charges diffuse in the vertical direction to move to an adjacent cell, thereby affecting an operation of the adjacent cell. Accordingly, the charge trap layer140of the nonvolatile memory device100according to the embodiment is separated from the separation layer120for each cell.

Specifically, the charge tunneling layer150, the charge trap layer140, and the charge blocking layer130may be sequentially arranged from the channel layer160toward the gate electrode110. In addition, the charge trap layer140and the charge blocking layer130may be separated by the separation layer120such that the memory cells may not be connected to each other. In addition, the charge tunneling layer150is not separated by the separation layer120, and thus, the memory cells are connected to each other to surround the channel layer160.

At least one of the charge tunneling layer150and the charge blocking layer130may include a plurality of layers. For example, the charge tunneling layer150may include first and second charge tunneling layers152and154, and the charge blocking layer130may include first and second charge blocking layers132and134. The first and second charge tunneling layers152and154are connected to each other between memory cells, while the charge trap layer140and the first and second charge blocking layers132and134may be separated from each other by the separation layer120. That is, the charge trap layer140and the first and second charge blocking layers132and134are arranged only between the second charge tunneling layer154and the gate electrode110, and only the separation layer120may be arranged in upper and lower portions of the gate electrode110. Thus, each of the charge trap layer140, the charge blocking layer130, and the gate electrode110may be in direct contact with the separation layer120.

The charge tunneling layer150is a layer through which electric charges may be tunneled and may include, for example, silicon oxide or metal oxide, but is not limited thereto. In particular, the second charge tunneling layer154may not only perform a function of tunneling electric charges but also perform an etch stop function in a manufacturing process of the nonvolatile memory device100. The second charge tunneling layer154may be formed of a dielectric constant material with a dielectric constant greater than 1 and/or a dielectric constant material with a dielectric constant less than 50. The second charge tunneling layer154may include a dielectric material including Si, Hf, or Al.

The charge trap layer140may store the introduced electric charges. The electric charges (for example, electrons) in the channel layer160may flow into the charge trap layer140due to a tunneling effect or so on. The electric charges introduced into the charge trap layer140may be fixed to the charge trap layer140. The charge trap layer140may include silicon nitride capable of charge trapping.

The charge blocking layer130may perform a barrier function of limiting and/or preventing electric charges from transferring between the charge trap layer140and the gate electrode110. A first surface of the charge blocking layer130may be in contact with the charge trap layer140, and a second surface of the charge blocking layer130may be in contact with the gate electrode110. The charge blocking layer130may include, for example, silicon oxide or metal oxide but is not limited thereto.

The separation layer120may not only serve as a spacer for maintaining an interval between the gate electrodes110but also limit and/or prevent the electric charges trapped in the charge trap layer140from diffusing to other memory cells. The separation layer120may be formed of a material with a low trap concentration or a high trap energy level. For example, the separation layer120may be formed of a material with a trap concentration less than 1×1019cm−3or a material with a trap energy level higher than 1.0 eV.

The separation layer120may include one or more layers. For example, the separation layer120may include a first separation layer122and a second separation layer124that surrounds the first separation layer122and are in contact with the gate electrode110, the charge blocking layer130, and the charge trap layer140. A thickness of the first separation layer122may be greater than a thickness of the second separation layer124. For example, the thickness of the first separation layer122may be 50 nm or less, and the thickness of the second separation layer124may be 5 nm or less.

The first separation layer122may have sufficient strength to support a structure of the nonvolatile memory device100. For example, a hardness of the first separation layer122may be greater than a hardness of the second separation layer124. The first separation layer122may be formed of a material such as silicon oxide, silicon nitride, AlN, HfO2, ZrO2, or so on. An air gap may be naturally added during a process of the first separation layer122.

The second separation layer124may limit and/or prevent the electric charges trapped in the charge trap layer140from diffusing. The charge tunneling layer150and the charge blocking layer130may be damaged during a manufacturing process. Thus, defects may be generated in the charge tunneling layer150and the charge blocking layer130, and the defects may cause electric charges to be trapped in the charge tunneling layer150and the charge blocking layer130. The second separation layer124may limit and/or prevent charge trapping by removing the defects generated in the charge tunneling layer150and the charge blocking layer130.

A trap concentration of the second separation layer124may be different from a trap concentration of the first separation layer122. The trap concentration of the second separation layer124may be greater than the trap concentration of the first separation layer122. For example, the trap concentration of the second separation layer124may be less than 1×1019cm−3. The second separation layer124may limit and/or prevent electric charges from moving from the charge trap layer140to the second separation layer124. The second separation layer124may be formed of a material with a chemically stable and low dielectric constant, for example, a material with a dielectric constant of 10 or less. For example, the material may be carbon-doped silicon dioxide (SiOC), fluorine-doped silicon dioxide (SiOF), or a two-dimensional material. The two-dimensional material may be hexagonal boron nitride (h-BN). The second separation layer124may reduce coupling between memory cells and cure the damaged charge tunneling layer150and the damaged charge blocking layer130to increase a breakdown voltage.

FIG.4is a view illustrating a nonvolatile memory device200including a charge trap layer140aconnected between memory cells as a comparative example. When comparingFIGS.2and4with each other, a charge blocking layer130aand the charge trap layer140aofFIG.4may be connected to each other between memory cells. Thus, even if electric charges are stored in the charge trap layer140a, the stored electric charges may diffuse to adjacent memory cells over time. A distance between memory cells, that is, a distance between the gate electrodes110, may be maintained to a certain distance or more to limit and/or prevent the electric charges from diffusing. This may hinder integration of the nonvolatile memory device200.

In addition, the charge trap layer140according to an embodiment is separated between memory cells by the separation layer120, and thus, electric charges stored in the charge trap layer140do not diffuse to adjacent memory cells even after time passes. Electric charges are not diffused by the separation layer120, and thus, an interval between the gate electrodes110of the nonvolatile memory device100according to an embodiment may be less than an interval between the gate electrodes110of the nonvolatile memory device200according to the comparative example. For example, the interval between the gate electrodes110of the nonvolatile memory device100according to an embodiment may be 50 nm or less.

FIGS.5A to5Iare reference views illustrating a method of manufacturing the nonvolatile memory device100, according the embodiment.

As illustrated inFIG.5A, a first sacrificial layer310and a second sacrificial layer320are alternately stacked on the substrate101. The first sacrificial layer310and the second sacrificial layer320may be alternately stacked in a direction perpendicular to a surface of the substrate101. The first sacrificial layer310and the second sacrificial layer320may be formed of different materials. The first sacrificial layer310and the second sacrificial layer320may include, for example, silicon oxide or silicon nitride but are not limited thereto. The first sacrificial layer310and the second sacrificial layers320may be formed by using various deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD).

As illustrated inFIG.5B, the channel hole CH is formed to penetrate the first sacrificial layer310and the second sacrificial layer320. Here, the channel hole CH may be formed to extend in a direction perpendicular to a surface of the substrate101. The channel hole CH may be formed to have a circular cross-section. The channel hole CH may be formed by anisotropically etching the first sacrificial layer310and the second sacrificial layer320.

As illustrated inFIG.5C, a blocking material layer330, a trap material layer340, the charge tunneling layer150, and the channel layer160may be sequentially formed on an inner wall of the channel hole CH. The blocking material layer330, the trap material layer340, and the charge tunneling layer150may be formed to extend in a direction perpendicular to the surface of the substrate101. The blocking material layer330may be formed on the inner wall of the channel hole CH to be in contact with the first sacrificial layer310and the second sacrificial layer320, the trap material layer340may be formed to be in contact with an inner wall of the blocking material layer330, and the charge tunneling layer150may be formed to be in contact with an inner wall of the trap material layer340. The channel layer160may be formed to be in contact with the inside of the charge tunneling layer150. The filling layer170may be further formed inside the channel layer160.

As illustrated inFIG.5D, the blocking material layer330may be exposed by removing the first sacrificial layer310.

As illustrated inFIG.5E, the charge blocking layer130and the charge trap layer140may be formed by partially and sequentially removing the blocking material layer330and the trap material layer340through a region from which the first sacrificial layer310is removed. The blocking material layer330and the trap material layer340may be etched by an atomic layer etching process or a wet etching process. At least one of the charge blocking layer130and the charge trap layer140may include a tapered region of which a thickness gradually decreases toward the outside through a wet etching process.

As illustrated inFIG.5F, a separation material layer370may be formed on a region from which the first sacrificial layer310, the blocking material layer330, and the trap material layer340are removed. A second separation material layer374surrounding the second sacrificial layer320, the charge blocking layer130, and the charge trap layer140may be formed, and a first separation material layer372filling the remaining region may be formed. The separation material layer370may be formed by using various deposition methods such as CVD, ALD, or PVD.

The separation material layer370may be formed of a material with a low trap concentration or a high trap energy level. For example, the separation material layer370may be formed of a material with a trap concentration less than 1×1019cm−3or a material with a trap energy level higher than 1.0 eV.

The second separation material layer374may limit and/or prevent electric charges trapped in the charge trap layer140from diffusing. The charge tunneling layer150and the charge blocking layer130may be damaged during a manufacturing process. The second separation material layer374may limit and/or prevent charge trapping by removing defects generated in the charge tunneling layer150and the charge blocking layer130.

A trap energy level of the second separation material layer374may be different from a trap energy level of the first separation material layer372. The trap energy level of the second separation material layer374may be higher than the trap energy level of the first separation material layer372. For example, the trap energy level of the second separation material layer374may be higher than 1.2 eV. Thus, electric charges may be limited and/or prevented from moving from the charge trap layer140to the second separation material layer374.

The second separation material layer374may be formed of a material that is chemically stable and has a dielectric constant of 10 or less. For example, the second separation material layer374may be formed of Al2O3, SiOC, SiOF, or a two-dimensional material. The two-dimensional material may be h-BN.

The first separation material layer372may have a sufficient strength to support a structure of the nonvolatile memory device100. For example, a hardness of the first separation material layer372may be greater than a hardness of the second separation material layer374. The first separation material layer372may be formed of a material such as silicon oxide or silicon nitride.

As illustrated inFIG.5G, forming the separation layer120may be completed by removing the separation material layer370protruding along an outer surface of the first sacrificial layer310.

As illustrated inFIG.5H, the charge blocking layer130may be exposed by removing the first sacrificial layer310. In addition, as illustrated inFIG.5I, the gate electrode110may be formed in a region from which the first sacrificial layer310is removed.

FIG.6is a view illustrating part of a nonvolatile memory device100aaccording to another embodiment. When comparingFIGS.1and6with each other, the nonvolatile memory device100aofFIG.6may include a separation layer120aformed as a single layer. For example, the separation layer120aalso may be formed of only a material included in the first separation layer122ofFIG.1.

FIG.7is a view illustrating part of a nonvolatile memory device100baccording to another embodiment. When comparingFIGS.6and7with each other, the nonvolatile memory device100bofFIG.7may include a charge tunneling layer150aformed as a single layer. For example, the charge tunneling layer150aofFIG.7may be formed of only a material included in the first charge tunneling layer152ofFIG.1.

FIG.8is a cross-sectional view illustrating a schematic structure of a nonvolatile memory device according to an embodiment.

When comparingFIGS.1and8with each other, the nonvolatile memory device100cofFIG.8may include a charge tunneling layer150band separation layers120bhaving different structures compared to the charge tunneling layer150and separation layers120inFIG.1. For example, the charge tunneling layer150bofFIG.8may include first charge tunneling layers152aalternately arranged in the Z direction between the plurality of separation layers120b. The charge tunneling layer150bmay further include the second charge tunneling layer154. The first charge tunneling layers152amay be between the charge blocking layer130and the second charge tunneling layer154. The first separation layer122aand second separation layer124bin each of the of the plurality of separation layers120bmay directly contact the second charge tunneling layer154and may extend between adjacent first charge tunneling layers152ain the Z direction. The first charge tunneling layers152aeach may include a tapered region in which a thickness in the Z direction gradually decreases toward the gate electrode110. Although not shown inFIG.8, the nonvolatile memory device100cmay be modified like the nonvolatile memory device100ainFIG.6such that the nonvolatile memory100cincludes separation layers formed as a single layer.

FIG.9is a block diagram schematically illustrating an electronic apparatus300including a nonvolatile memory device, according to an embodiment.

Referring toFIG.9, the electronic apparatus400according to an embodiment includes a personal digital assistant (PDA), a laptop computer, a portable computer, a web tablet, a wireless telephone, a mobile phone, a digital music player, a wired/wireless electronic apparatus, or a composite electronic apparatus including at least two thereof. The electronic apparatus400may include a controller420, an input/output apparatus430such as a keypad, a keyboard, or a display, a memory440, and a wireless interface450coupled to each other through a bus410.

The controller420may include, for example, one or more microprocessors, a digital signal processor, a microcontroller, or so on. The memory440may be used to store commands executed by, for example, the controller420.

The memory440may be used to store user data. The memory440may include at least one of the nonvolatile memory devices100,100a,100b, and100caccording to an embodiment.

The electronic apparatus400may use the wireless interface450to transmit data to a wireless communication network that communicates by using an RF signal or to receive data from the network. For example, the wireless interface450may include an antenna, a wireless transceiver, and so on. The electronic apparatus300may be used in a communication interface protocol such as a third generation communication system such as code division multiple access (CDMA), global system for mobile communications (GSM), NADC, extended time division multiple access (E-TDMA), wideband code division multiple access (WCDAM), and CDMA2000.

FIG.10is a block diagram schematically illustrating a memory system500including a nonvolatile memory device, according to an embodiment.

Referring toFIG.10, the nonvolatile memory devices100,100a,100b, and100caccording to an embodiment may be used to implement the memory system500. The memory system500may include a memory510for storing a large amount of data and a memory controller520. The memory controller520controls the memory510to read the stored data from the memory510or to write data to the memory510in response to a read/write request from a host530. The memory controller520may constitute an address mapping table for mapping an address provided from the host530such as a mobile apparatus or a computer system into a physical address of the memory510. The memory510may include at least one of the memory devices100,100a,100b, and100caccording to the embodiments of the present disclosure.

The memory devices100,100a,100b, and100caccording to the embodiments described above may be implemented in a chip form and may be used as a neuromorphic computing platform. For example,FIG.11schematically illustrates a neuromorphic apparatus including a memory device, according to an embodiment. Referring toFIG.11, a neuromorphic apparatus600may include a processing circuit610and/or a memory620. The memory620of the neuromorphic apparatus600may include the memory system500according to the embodiment.

The processing circuit610may be configured to control functions for driving the neuromorphic apparatus600. For example, the processing circuit610may control the neuromorphic apparatus600by executing a program stored in the memory620of the neuromorphic apparatus600.

The processing circuit610may include hardware such as a logic circuit, a combination of software and hardware such as a processor that executes software, or a combination thereof. For example, the processor may include a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP) in the neuromorphic device600, an arithmetic logic unit (ALU), a digital processor, a microcomputer, a field programmable gate array (FPGA), a system-on-chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), and so on.

In addition, the processing circuit610may read and write various data from and to an external apparatus630and operate the neuromorphic device600by using the data. The external apparatus630may include a sensor array including an external memory and/or an image sensor (for example, a CMOS image sensor circuit).

The neuromorphic device600illustrated inFIG.11may be applied to a machine learning system. The machine learning system may utilize various processing models and various artificial neural network organizations including, for example, a convolutional neural network (CNN), a deconvolutional neural network, a recurrent neural network (RNN) selectively including a long short-term memory (LSTM) and/or a gated recurrent unit (GRU), a stacked neural network (SNN), a state-space dynamic neural network (SSDNN), a deep belief network (DBN), generative adversarial networks (GANs), and/or restricted Boltzmann machines (RBMs).

The machine learning system may include, for example, linear regression and/or logistic regression, statistical clustering, Bayesian classification, decision trees, dimensionality reduction such as principal component analysis, and another type of machine learning model such as an expert system, and/or a combination thereof including an ensemble technique such as random forest. The machine learning model may be used to provide various services, for example, an image classification service, a user authentication service based on biometric information or biometric data, an advanced driver assistance system (ADAS), a voice assistant service, and an automatic speech recognition (ASR) service and may be installed in other electronic apparatuses to be executed.

The above-described nonvolatile memory devices may reduce a diffusion of electric charges between memory cells.

The above-described nonvolatile memory devices easily implement low power and high integration.

The nonvolatile memory devices100,100a,100b, and100care described above with reference to the embodiments illustrated in the drawings, but these are only examples, and those skilled in the art may appreciate that various modifications and equivalent other examples may be derived therefrom.

It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.