Patent ID: 12237259

DETAILED DESCRIPTION

An electronic device (e.g., an apparatus, a semiconductor device, a memory device) that includes one or more multilevel bitlines is disclosed. The bitlines (e.g., data lines, digit lines) of the electronic device are located at multiple levels (elevations, heights) of the electronic device, with one set of bitlines extending continuously in a first level (L1) of the electronic device and another set of bitlines extending continuously in a second level (L2) of the electronic device. The set of bitlines in the first level is referred to herein as L1 bitlines or first bitlines, and the set of bitlines in the second level is referred to herein as L2 bitlines or second bitlines. The L1 bitlines are proximal to a base material and the L2 bitlines are distal to the base material. The L1 bitlines and the L2 bitlines are not in physical contact with one another or in electrical contact with one another.

Adjacent L1 bitlines are separated from (e.g., isolated from) one another by a dielectric material (e.g., a liner). The liner may extend between the adjacent L1 bitlines for at least a portion of a height of the L1 bitlines. The liner may extend between the adjacent L1 bitlines substantially the entire height of the L1 bitlines or may extend a greater height than the height of the L1 bitlines or a lesser height than the height of the L1 bitlines. Therefore, the liner may be substantially coextensive with the L1 bitlines along its entire height or may extend partially above or partially below the height of the L1 bitlines. At least a portion of the liner may, therefore, be present between the adjacent L1 bitlines. By adjusting dimensions (e.g., a height) of the liner, capacitance of the electronic device containing the liner may be tailored. A portion of L2 contacts, which electrically couple the L2 bitlines to other conductive components of the electronic device, may also separate the adjacent L1 bitlines from one another. Adjacent L2 bitlines are separated from (e.g., isolated from) one another by a dielectric material or by an air gap. The liner may be adjacent to at least a portion of the L2 contacts, such as laterally adjacent to the L2 contacts along an entire height thereof or along only a portion thereof.

The multilevel bitlines (e.g., a combination of the L1 bitlines and the L2 bitlines) are operably coupled to (e.g., electrically connected to) underlying contacts (e.g., pillar contacts), with each bitline of the multilevel bitlines electrically connected to a single (e.g., one) pillar contact in a subblock. The multilevel bitlines and the pillar contacts are electrically connected to one another through L1 contacts and L2 contacts, with the L1 contacts and the L2 contacts exhibiting a different dimension (e.g., a length) from one another through materials of the electronic device. Each of the multilevel bitlines is electrically connected to a single (e.g., one) L1 contact or a single (e.g., one) L2 contact, which, in turn, is electrically connected to a single (e.g., one) pillar contact in the subblock. The bitlines of the multilevel bitlines are also substantially equally spaced from one another. The electronic device containing the multilevel bitlines according to embodiments of the disclosure exhibits improved bitline-bitline capacitance in comparison to a conventional electronic device in which bitlines are located in only a single (e.g., one) level.

The following description provides specific details, such as material types, material thicknesses, and process conditions in order to provide a thorough description of embodiments described herein. However, a person of ordinary skill in the art will understand that the embodiments disclosed herein may be practiced without employing these specific details. Indeed, the embodiments may be practiced in conjunction with conventional fabrication techniques employed in the semiconductor industry. In addition, the description provided herein does not form a complete description of an electronic device or a complete process flow for manufacturing the electronic device and the structures described below do not form a complete electronic device. Only those process acts and structures necessary to understand the embodiments described herein are described in detail below. Additional acts to form a complete electronic device may be performed by conventional techniques.

Unless otherwise indicated, the materials described herein may be formed by conventional techniques including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced ALD, physical vapor deposition (PVD) (including sputtering, evaporation, ionized PVD, and/or plasma-enhanced CVD), or epitaxial growth. Alternatively, the materials may be grown in situ. Depending on the specific material to be formed, the technique for depositing or growing the material may be selected by a person of ordinary skill in the art. The removal of materials may be accomplished by any suitable technique including, but not limited to, etching (e.g., dry etching, wet etching, vapor etching), ion milling, abrasive planarization (e.g., chemical-mechanical planarization), or other known methods unless the context indicates otherwise.

Drawings presented herein are for illustrative purposes only, and are not meant to be actual views of any particular material, component, structure, electronic device, or electronic system. Variations from the shapes depicted in the drawings as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as being limited to the particular shapes or regions as illustrated, but include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as box-shaped may have rough and/or nonlinear features, and a region illustrated or described as round may include some rough and/or linear features. Moreover, sharp angles that are illustrated may be rounded, and vice versa. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of a region and do not limit the scope of the present claims. The drawings are not necessarily to scale. Additionally, elements common between figures may retain the same numerical designation.

As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

As used herein, the term “air gap” means and includes an opening that is empty of a solid material and/or liquid material. However, the air gap may contain a gaseous material (e.g., air, oxygen, nitrogen, argon, helium, or a combination thereof).

As used herein, “and/or” includes any and all combinations of one or more of the associated listed items.

As used herein, “about” or “approximately” in reference to a numerical value for a particular parameter is inclusive of the numerical value and a degree of variance from the numerical value that one of ordinary skill in the art would understand is within acceptable tolerances for the particular parameter. For example, “about” or “approximately” in reference to a numerical value may include additional numerical values within a range of from 90.0 percent to 110.0 percent of the numerical value, such as within a range of from 95.0 percent to 105.0 percent of the numerical value, within a range of from 97.5 percent to 102.5 percent of the numerical value, within a range of from 99.0 percent to 101.0 percent of the numerical value, within a range of from 99.5 percent to 100.5 percent of the numerical value, or within a range of from 99.9 percent to 100.1 percent of the numerical value.

As used herein, spatially relative terms, such as “beneath,” “below,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” “right,” and the like, may be used for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Unless otherwise specified, the spatially relative terms are intended to encompass different orientations of the materials in addition to the orientation depicted in the figures. For example, if materials in the figures are inverted, elements described as “below” or “beneath” or “under” or “on bottom of” other elements or features would then be oriented “above” or “on top of” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below, depending on the context in which the term is used, which will be evident to one of ordinary skill in the art. The materials may be otherwise oriented (e.g., rotated 90 degrees, inverted, flipped) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term “conductive material” means and includes an electrically conductive material. The conductive material may include, but is not limited to, one or more of a doped polysilicon, undoped polysilicon, a metal, an alloy, a conductive metal oxide, a conductive metal nitride, a conductive metal silicide, and a conductively doped semiconductor material. By way of example only, the conductive material may be one or more of tungsten (W), tungsten nitride (WNy), nickel (Ni), tantalum (Ta), tantalum nitride (TaNy), tantalum silicide (TaSix), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al), molybdenum (Mo), titanium (Ti), titanium nitride (TiNy), titanium silicide (TiSix), titanium silicon nitride (TiSixNy), titanium aluminum nitride (TiAlxNy), molybdenum nitride (MoNx), iridium (Ir), iridium oxide (IrOz), ruthenium (Ru), ruthenium oxide (RuOz), n-doped polysilicon, p-doped polysilicon, undoped polysilicon, and conductively doped silicon.

As used herein, the term “configured” refers to a size, shape, material composition, and arrangement of one or more of at least one structure and at least one apparatus facilitating operation of one or more of the structure and the apparatus in a pre-determined way.

As used herein, the phrase “coupled to” refers to structures operably connected with each other, such as electrically connected through a direct ohmic connection or through an indirect connection (e.g., via another structure).

As used herein, the term “dielectric material” means and includes an electrically insulative material. The dielectric material may include, but is not limited to, one or more of an insulative oxide material or an insulative nitride material. A dielectric oxide may be an oxide material, a metal oxide material, or a combination thereof. The dielectric oxide may include, but is not limited to, a silicon oxide (SiOx, silicon dioxide (SiO2)), doped SiOx, phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, tetraethylorthosilicate (TEOS), aluminum oxide (AlOx), gadolinium oxide (GdOx), hafnium oxide (HfOx), magnesium oxide (MgOx), niobium oxide (NbOx), tantalum oxide (TaOx), titanium oxide (TiOx), zirconium oxide (ZrOx), hafnium silicate, a dielectric oxynitride material (e.g., SiOxNy), a dielectric carboxynitride material (e.g., SiOxCzNy), a combination thereof, or a combination of one or more of the listed materials with silicon oxide. A dielectric nitride material may include, but is not limited to, silicon nitride.

As used herein, the term “electronic device” includes, without limitation, a memory device, as well as semiconductor devices which may or may not incorporate memory, such as a logic device, a processor device, or a radiofrequency (RF) device. Further, an electronic device may incorporate memory in addition to other functions such as, for example, a so-called “system on a chip” (SoC) including a processor and memory, or an electronic device including logic and memory. The electronic device may, for example, be a 3D electronic device, such as a 3D NAND Flash memory device.

As used herein, the term “etch stop” material means and includes a material that is resistant to removal (e.g., etch) relative to removal of one or more other exposed materials.

As used herein, the term “level” refers to a particular elevation (in a z direction) of a particular feature. Features that are present at different levels of the electronic device do not physically contact each other.

As used herein, the term “low-k dielectric material” means and includes a dielectric material, such as a dielectric oxide material, having a dielectric constant lower than the dielectric constant of a silicon oxide (SiOx, SiO2) material or of a carbon-doped silicon oxide material that includes silicon atoms, carbon atoms, oxygen atoms, and hydrogen atoms. The dielectric constant of silicon dioxide is from about 3.7 to about 3.9. The term “low-k dielectric material” is a relative term and is distinguished from the term “dielectric material” by a relative value of its dielectric constant.

As used herein, the term “multilevel bitlines” refers to multiple bitlines (e.g., sets of bitlines) present at different locations (e.g., levels, elevations) in the electronic device. The bitlines include and are formed of a conductive material, with each set of the multilevel bitlines operably connected (e.g., electrically connected) to the pillar contacts and to access lines (e.g., wordlines) of the electronic device. The multilevel bitlines are electrically connected to the pillar contacts by contacts (e.g., L1 contacts, L2 contacts) adjacent to the different levels.

As used herein, reference to an element as being “on” or “over” another element means and includes the element being directly on top of, adjacent to (e.g., laterally adjacent to, vertically adjacent to), underneath, or in direct contact with the other element. It also includes the element being indirectly on top of, adjacent to (e.g., laterally adjacent to, vertically adjacent to), underneath, or near the other element, with other elements present therebetween. In contrast, when an element is referred to as being “directly on” or “directly adjacent to” another element, no intervening elements are present.

As used herein, the terms “selectively removable” or “selectively etchable” mean and include a material that exhibits a greater etch rate responsive to exposure to a given etch chemistry and/or process conditions relative to another material exposed to the same etch chemistry and/or process conditions. For example, the material may exhibit an etch rate that is at least about five times greater than the etch rate of another material, such as an etch rate of about ten times greater, about twenty times greater, or about forty times greater than the etch rate of the another material. The etch selectivity between materials may be achieved by selecting materials of different chemical compositions or by using materials of similar chemical compositions and different dopants or dopant concentrations. Etch chemistries and etch conditions for selectively etching a desired material may be selected by a person of ordinary skill in the art.

As used herein, the term “substantially” in reference to a given parameter, property, or condition means and includes to a degree that one of ordinary skill in the art would understand that the given parameter, property, or condition is met with a degree of variance, such as within acceptable manufacturing tolerances. By way of example, depending on the particular parameter, property, or condition that is substantially met, the parameter, property, or condition may be at least 90.0% met, at least 95.0% met, at least 99.0% met, or even at least 99.9% met.

As used herein, the term “substrate” means and includes a material (e.g., a base material) or construction upon which additional materials are formed. The substrate may be a an electronic substrate, a semiconductor substrate, a base semiconductor layer on a supporting structure, an electrode, an electronic substrate having one or more materials, layers, structures, or regions formed thereon, or a semiconductor substrate having one or more materials, layers, structures, or regions formed thereon. The materials on the electronic substrate or semiconductor substrate may include, but are not limited to, semiconductive materials, insulating materials, conductive materials, etc. The substrate may be a conventional silicon substrate or other bulk substrate comprising a layer of semiconductive material. As used herein, the term “bulk substrate” means and includes not only silicon wafers, but also silicon-on-insulator (“SOI”) substrates, such as silicon-on-sapphire (“SOS”) substrates and silicon-on-glass (“SOG”) substrates, epitaxial layers of silicon on a base semiconductor foundation, and other semiconductor or optoelectronic materials, such as silicon-germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. The substrate may be doped or undoped.

As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” are in reference to a major plane of a structure and are not necessarily defined by Earth's gravitational field. A “horizontal” or “lateral” direction is a direction that is substantially parallel to the major plane of the structure, while a “vertical” or “longitudinal” direction is a direction that is substantially perpendicular to the major plane of the structure. The major plane of the structure is defined by a surface of the structure having a relatively large area compared to other surfaces of the structure.

An electronic device24including L1 contacts14, multilevel bitlines16,22, L2 contacts20, and liner26is shown inFIGS.1A and1B. The electronic device24includes multiple blocks (not shown) and subblocks (not shown), with multiple blocks being present. The electronic device24includes L1 bitlines16adjacent to (e.g., over) a base material (not shown), and L2 bitlines22adjacent to (e.g., over) the L1 bitlines16. The L1 bitlines16are proximal to the base material and the L2 bitlines22are distal to the base material. The L1 bitlines16and the L2 bitlines22are equally spaced from one another and run parallel to one another in the horizontal direction (e.g., depth direction) ofFIG.1A. The L1 bitlines16are separated from one another in a horizontal direction by one or more dielectric materials (e.g., a first dielectric material6, a second dielectric material8), the liner26, and a lower portion of the L2 contacts20. WhileFIGS.1A and1Billustrate a single dielectric material8around the L1 contacts14, multiple (e.g., two) dielectric materials may be present as described in relation toFIGS.4A-7B. The L2 bitlines22are separated from one another in the horizontal direction by a third dielectric material18. The L1 contacts14, the L1 bitlines16, and the first and second dielectric materials6,8form a first level (e.g., a first deck) of the electronic device24. The L2 bitlines22, the third dielectric material18, and an upper portion of the L2 contacts20form a second level (e.g., a second deck) of the electronic device24adjacent to (e.g., over) the first level. A lower portion of the L2 contacts20extends into the first level. The L2 contacts20exhibit a greater length than a length of the L1 contacts14since the L2 contacts20extend through the first and second decks of the electronic device24. The L2 bitlines22may exhibit greater dimensions (e.g., greater widths) relative to the widths of the L2 contacts20, providing an increased width (e.g., surface area) of the L2 bitlines22. While two levels of bitlines are described and illustrated, two or more levels of bitlines may be present in the electronic device24.

The L1 bitlines16are present at a single level, L1 and are continuous (e.g., extend substantially continuously) in a horizontal (e.g., x) direction. Each of the L1 contacts14may be configured to be in electrical contact (e.g., electrical connection) with alternate (e.g., every other) L1 bitlines16. A portion of each of the L1 bitlines16directly contacts the L1 contacts14, electrically connecting the L1 bitlines16to the pillar contacts. Therefore, each L1 contact14is electrically connected to one (e.g., a single) L1 bitline16in the subblock. The L1 bitlines16are also electrically connected to wordlines1905(seeFIG.19). Each of the L1 bitlines16may be formed at substantially the same pitch and exhibit substantially the same critical dimension (CD) as one another. The pitch of the L1 bitlines16may range from about 40 nm to about 75 nm, such as from about 45 nm to about 75 nm, from about 50 nm to about 75 nm, from about 60 nm to about 75 nm, from about 65 nm to about 75 nm, or from about 70 nm to about 75 nm. The L1 bitlines16are equally spaced from one another in the horizontal direction, and spaces between the laterally adjacent L1 bitlines16exhibit substantially the same dimensions as one another. However, the CD of the L1 bitlines16may be different than the CD of the spaces between the L1 bitlines16. A width (e.g., the CD) of the L1 bitlines16may be selected depending on desired electrical performance characteristics of the electronic device24containing the L1 bitlines16. The CD of the L1 bitlines16may substantially correspond to (e.g., be substantially the same as) a width of the L1 contacts14. However, the width of the L1 bitlines16may be greater than (e.g., slightly greater than) or less than (e.g., slightly less than) the width of the L1 contacts14, depending on the desired electrical performance characteristics of the electronic device24containing the L1 bitlines16. The width of the first bitlines16may range from about 15 nm to about 40 nm, such as from about 15 nm to about 30 nm, from about 20 nm to about 30 nm, from about 15 nm to about 35 nm, or from about 15 nm to about 25 nm.

The L2 bitlines22are present at a single level, L2, and are electrically connected to the L2 contacts20and to vertical strings1907(seeFIG.19). A portion of each of the L2 bitlines22may directly contact the L2 contacts20, electrically connecting the L2 bitlines22to the pillar contacts. Each L2 contact20is electrically connected to one (e.g., a single) second bitline22in the subblock. The L2 bitlines22are continuous in the horizontal direction ofFIG.1A. The L2 bitlines22are also electrically connected to wordlines1905(seeFIG.19), with a portion of level 2 used as routing1906. Each of the L2 bitlines22may be formed at substantially the same pitch and exhibit substantially the same CD, with the pitch and CD within the ranges disclosed above for the L1 bitlines16. The L2 bitlines22are equally spaced from one another in the horizontal direction, and spaces between the L2 bitlines22exhibit substantially the same dimensions as one another. However, the CD of the L2 bitlines22may be different than the CD of the spaces between the L2 bitlines22. A width of the L2 bitlines22may substantially correspond to a width of the L2 contacts20. However, the width of the L2 bitlines22may be greater than (e.g., slightly greater than) or less than (e.g., slightly less than) the width of the L2 contacts20, depending on the desired electrical performance characteristics of the electronic device24containing the L1 bitlines16and the L2 bitlines22.

The L1 contacts14, the L1 bitlines16, the L2 contacts20, and the L2 bitlines22are not all visible in the same cross-sectional views. Therefore, inFIG.1A, and other drawings, solid lines are used to indicate the rightmost L1 contact14and L1 bitline16, and dashed lines are used to indicate the other L1 contacts14and L1 bitlines16. InFIG.1A, one L1 contact14and one L1 bitline16(the rightmost L1 contact14and L1 bitline16) are in the foreground of this cross-sectional view while the remaining L1 contacts14and L1 bitlines16are in the background of this cross-sectional view. Similarly, one L2 contact20and one L2 bitline22(the leftmost L2 contact20and L2 bitline22) are in the foreground of this cross-sectional view while the remaining L2 contacts20and L2 bitlines22are in the background of this cross-sectional view. InFIG.1Aand other drawings, some of the L1 contacts14and the L1 bitlines16are shown using dashed lines, indicating these structures are offset (e.g., laterally offset) in a y direction relative to the L1 contact14and the L1 bitline16that are shown using solid lines. Some of the L2 contacts20and the L2 bitlines22are shown using dashed lines, indicating these structures are offset in the y direction relative to the L2 contact20and the L2 bitline22that are shown using solid lines. For simplicity in the top down view ofFIG.1B, some materials are omitted for clarity. In other words, not all of the L1 contacts14, L1 bitlines16, L2 contacts20, and L2 bitlines22are shown inFIG.1B.

The liner26surrounds the L2 contacts20, isolating the L2 contacts20from the L1 bitlines16and the L1 contacts14. The liner26extends a height H1(an entire height) of the L2 contacts20. The liner26, thus, is substantially coextensive with the L2 contacts20along its entire height (i.e., the z direction). The L1 contacts14are separated from one another by the second dielectric material8, a lower portion of the liner26, and the lower portion of the L2 contacts20. The L2 contacts20are separated from one another by the third dielectric material18and an upper portion of the liner26. The L1 bitlines16are equally spaced from one another in the horizontal direction (i.e., the x direction) and exhibit a height H2. The L2 bitlines22are equally spaced from one another in the horizontal direction. The L1 contacts14are equally spaced from one another in the horizontal direction, and the L2 contacts20are equally spaced from one another in the horizontal direction.

The L1 contacts14and the L2 contacts20electrically connect the L1 bitlines16and the L2 bitlines22, respectively, to pillar contacts (not shown inFIGS.1A and1B) below the L1 bitlines16. The L1 contacts14are adjacent to (e.g., over) the pillar contacts, which are adjacent to (e.g., over) the base material. The pillar contacts may be formed in an underlying dielectric material (not shown) that separates horizontally adjacent pillar contacts from one another. The pillar contacts may, for example, be configured to electrically connect to pillars (e.g., memory pillars, memory strings, channel strings) (not shown) adjacent to (e.g., below) the pillar contacts and to the overlying L1 contacts14and the L1 bitlines16. The pillar contacts may be adjacent to (e.g., vertically adjacent to, on) and in direct electrical contact with contact plugs (not shown) of the pillars, electrically connecting the pillars to the pillar contacts. The pillars are present in tiers (not shown inFIGS.1A and1B) of alternating dielectric materials and conductive materials on the base material (e.g., a substrate). The pillars may, for example, be memory pillars and include a channel material of a cell film surrounding a fill material. The cell film may include a cell material and the channel material is formed adjacent to (e.g., around) the cell material. The cell material and the channel material in the tiers define memory cells of the electronic device24. Alternatively, one or more of the pillars in the electronic device24may be dummy pillars.

By including the liner26around the L2 contacts20, the L1 bitlines16may be electrically isolated from one another and from the L2 contacts20. Therefore, shorting between adjacent conductive features, such as between the L2 contacts20, the L2 bitlines22, and the L1 bitlines16, is reduced (e.g., minimized) compared to conventional electronic devices lacking such a liner26. In addition, the L1 bitlines16may exhibit greater dimensions (e.g., greater widths) than conventional L1 bitlines since the L1 bitlines16may partially overlap with the L2 bitlines22and the L2 contacts20. In other words, spacing of the L1 bitlines16may be narrower than a diameter of the L2 contacts20. The greater dimensions of the L1 bitlines16correspond to lower resistance between adjacent L1 bitlines16. The L2 bitlines22may exhibit greater dimensions (e.g., greater widths) relative to the widths of the L2 contacts20, providing an increased surface area of the L2 bitlines22.

An electronic device24′ including the L1 contacts14, the L1 bitlines16, the L2 contacts20, the L2 bitlines22, and the liner26is shown inFIGS.2A and2B. The electronic device24′ is similar to the electronic device24except that air gaps28are adjacent to (e.g., laterally adjacent to) one or more of the L1 contacts14, the L1 bitlines16, the L2 contacts20, or the L2 bitlines22. In other words, the air gaps28replace at least a portion of the second and third dielectric materials8,18that are present in the electronic device24. The liner26may substantially completely surround the L2 contacts20, providing stability to the electronic device24′ and separating the L2 contacts20from other conductive materials of the electronic device24′. The liner26extends along substantially an entire height of (e.g., is substantially coextensive with) the L2 contacts20. The L2 bitlines22may exhibit greater dimensions (e.g., greater widths) relative to the widths of the L2 contacts20, providing an increased width (e.g., surface area) of the L2 bitlines22. Features (e.g., materials and structures) and method acts of forming of the electronic device24′ that are substantially similar to those of the electronic device24are as described above. Features and method acts that differ from those described above are further described below.

Similar toFIGS.1A and1B, the L1 contacts14, the L1 bitlines16, the L2 contacts20, and the L2 bitlines22inFIGS.2A and2Bare not all visible in the same cross-sectional views. InFIG.2Aand other drawings, solid lines are used to indicate the rightmost L1 contact14and L1 bitline16and dashed lines are used to indicate the other L1 contacts14and L1 bitlines16. InFIG.2A, one L1 contact14and one L1 bitline16(the rightmost L1 contact14and L1 bitline16) are in the foreground of this cross-sectional view while the remaining L1 contacts14and L1 bitlines16are in the background of this cross-sectional view. Similarly, one L2 contact20and one L2 bitline22(the leftmost L2 contact20and L2 bitline22) are in the foreground of this cross-sectional view while the remaining L2 contacts20and L2 bitlines22are in the background of this cross-sectional view. InFIG.2A, some of the L1 contacts14and the L1 bitlines16are shown using dashed lines, indicating these structures are offset (e.g., laterally offset) in a y direction relative to the L1 contact14and the L1 bitline16that are shown using solid lines. Some of the L2 contacts20and the L2 bitlines22are shown using dashed lines, indicating these structures are offset in the y direction relative to the L2 contact20and the L2 bitline22that are shown using solid lines. For simplicity in the top down view ofFIG.2B, some materials are omitted for clarity. In other words, not all of the L1 contacts14, L1 bitlines16, L2 contacts20, and L2 bitlines22are shown inFIG.2B.

While electronic device24′ includes the liner26, an electronic device24″ including only a portion of the liner26′ is shown inFIGS.3A and3B. Features (e.g., materials and structures) and method acts of forming of the electronic device24″ that are substantially similar to those of the electronic device24are as described above. Features and method acts that differ from those described above are further described below. A portion of the liner26may be removed such that only the liner26′ remains, producing the electronic device24″. By way of example only, the portion of the liner26may be removed such that the liner26′ is only present adjacent to (e.g., laterally adjacent to) the L1 bitlines16. The liner26′ extends along only a portion of the L2 contacts20. In other words, the liner26′ extends a distance that is less than the height H1of the L2 contacts20and less than the height H2of the L1 bitlines16. The L2 bitlines22may exhibit greater dimensions (e.g., greater widths) relative to the widths of the L2 contacts20, providing an increased surface area of the L2 bitlines22. As in other drawings, dashed lines are used to indicate structures that are offset (e.g., laterally offset) in a y direction relative to structures that are shown using solid lines. InFIGS.3A and3B, solid lines are used to indicate the rightmost L1 contact14and L1 bitline16in the foreground and dashed lines are used to indicate the other L1 contacts14and L1 bitlines16in the background. Solid lines are used to indicate the leftmost L2 contact20and L2 bitline22in the foreground and dashed lines are used to indicate the other L2 contacts20and L2 bitlines22in the background.

A method of forming the electronic device24is shown inFIGS.4A-7B. The L1 contacts14are formed in a first dielectric material6and a second dielectric material8of the first level and the L1 bitlines16are formed in the second dielectric material8of the first level as shown inFIGS.4A and4B. The L1 contacts14are formed by conventional techniques, such as by forming openings10in the first dielectric material6and the second dielectric material8and forming a conductive material in the openings10. The first dielectric material6and the second dielectric material8(or the single dielectric material8) may be formed at a thickness sufficient to provide desired dimensions of the subsequently-formed L1 contacts14. The openings10are formed by conventional photolithography and removal techniques. The L1 contacts14extend partially into the second dielectric material8and through the first dielectric material6. The L1 contacts14are separated from one another by portions of the first dielectric material6and the second dielectric material8. The L1 bitlines16are formed adjacent to (e.g., over) the L1 contacts14. The L1 bitlines16are formed in the second dielectric material8by conventional techniques, such as by forming openings12in the second dielectric material8and forming a conductive material in the openings12. The conductive material of the L1 bitlines16may be the same as or different than the conductive material of the L1 contacts14. The openings12are formed by conventional photolithography and removal techniques. As shown inFIGS.4A and4B, the L1 contacts14are equally spaced from one another and the L1 bitlines16are equally spaced from one another.

The first dielectric material6and the second dielectric material8may be selected from one of the dielectric materials mentioned above. Each of the first dielectric material6and the second dielectric material8may be formed from an electrically insulative material, such as an electrically insulative oxide material. The first dielectric material6and the second dielectric material8may exhibit the same material (e.g., the same chemical composition) or a different material (e.g., a different chemical composition). Even if the first dielectric material6and the second dielectric material8are formed from the same chemical composition, the first dielectric material6and the second dielectric material8may be visually distinguishable if the first dielectric material6and the second dielectric material8are formed at different times (e.g., by different process acts). In some embodiments, the first dielectric material6and the second dielectric material8are different materials and are selected to be selectively etchable relative to one another or selectively etchable relative to other dielectric materials used to form the electronic device24. WhileFIGS.4A and4Bshow forming the L1 contacts14and the L1 bitlines16in the first dielectric material6and the second dielectric material8, the L1 contacts14and the L1 bitlines16may be formed in a single dielectric material8.

A third dielectric material18is formed over the first level and openings31are formed in the first, second, and third dielectric materials6,8,18, as shown inFIGS.5A and5B. The L2 contacts20are formed in the openings31. A thickness of the third dielectric material18defines the thickness of the second level in which the L2 bitlines and the L2 contacts20are formed. The third dielectric material18may, for example, be an interlayer dielectric material. The openings31are formed by conventional photolithography and removal techniques and extend through the first, second, and third dielectric materials6,8,18. Sidewalls of the third dielectric material18define the openings31in which the liner26and the L2 contacts20are to be formed.

The liner26is formed in the openings31, as shown inFIGS.6A and6B. The liner26may be formed of and include a dielectric material, such as silicon nitride. The liner26may be conformally formed in the openings31, with a volume of the openings31remaining for subsequent formation of the L2 contacts20. Since the liner26occupies a portion of the volume of the openings31, the remaining volume to be occupied by the L2 contacts20may be reduced compared to the volume of the L2 contacts20if the liner26was not present. The liner26may initially be formed along the sidewalls of the third dielectric material18, extending from an upper surface of the third dielectric material18to a lower surface of the first dielectric material6. A portion of the liner26may subsequently be removed depending on a desired height of the L2 contacts20.

The L2 contacts20and the L2 bitlines22of the second level are formed, as shown inFIGS.7A and7B. A portion of the liner26at the bottom of the openings31is removed and a conductive material of the L2 contacts20is formed in the openings31. The liner26at the bottom of the openings31may be removed by a so-called “punch etch” process. The conductive material of the L2 contacts20substantially fills the openings31, with the liner26surrounding the L2 contacts20. The L2 contacts20extend through the third dielectric material18, the second dielectric material8, and the first dielectric material6. After forming the L2 contacts20, additional openings (not shown) are formed, by conventional photolithography and removal techniques, such as by an anisotropic etching process. A conductive material is formed in the openings and adjacent to (e.g., over) the L2 contacts20, forming the L2 bitlines22of the electronic device24. The L2 bitlines22exhibit a greater width than a width of the adjacent portion of the L2 contacts20, providing an increased surface area of the L2 bitlines22. The electronic device24shown inFIGS.7A and7Bis substantially the same as the electronic device24shown inFIGS.1A and1Bexcept that first and second dielectric materials6,8are illustrated inFIGS.7A and7Bwhile a single dielectric material8is illustrated inFIGS.1A and1B. The conductive material of the L2 bitlines may be the same as or different than the conductive material of the L2 contacts20.

One or more electronic device24may be present in an apparatus. Alternatively, the electronic device24may be further processed to form the electronic device24′, one or more of which is present in an apparatus. The electronic device24′ including the air gaps28is formed by removing the second and third dielectric materials8,18, as shown inFIGS.8A and8B. The electronic device24′ differs from the electronic device24in that the air gaps28are present in place of the second and third dielectric materials8,18, with the air gaps28extending along at least a portion of the height of the L2 contacts20. The third dielectric material18and the second dielectric material8may be removed by conventional techniques, forming the air gaps28between the L2 bitlines22, the L2 contacts20, the L1 bitlines16, and the L1 contacts. The air gaps28may extend from an upper surface of the L2 bitlines22to below a lower surface of the L1 bitlines16and, optionally, into the first dielectric material6. The third dielectric material18and the second dielectric material8may be selectively removed, by conventional techniques, relative to the conductive materials of the L1 bitlines16and the L2 bitlines22, the L2 contacts20, the L1 contacts14, the liner26, and the first dielectric material6. During the selective removal of the third dielectric material18and the second dielectric material8, substantially all of the conductive materials of the L1 bitlines16, the L2 bitlines22, the L2 contacts20, and the L1 contacts14may remain.

The liner26and the first dielectric material6located laterally adjacent to the L2 contacts20may provide stability (e.g., structural stability) to the L2 contacts20. If, however, the L2 contacts20are sufficiently stable, a portion of the first dielectric material6may, optionally, be removed by conventional techniques. The air gaps28may be extended into the first dielectric material6by selectively removing the portion of the first dielectric material6relative to the conductive materials of the L1 bitlines16and the L2 bitlines22and to the liner26. While the liner26may contribute to higher capacitance of the electronic device24′, the air gaps28may compensate for the increase and achieve desired electrical performance of the electronic device24′.

If only the liner26′ is to present adjacent to the L2 contacts20, as shown in the electronic device24″ ofFIGS.3A and3B, a portion of the liner26may be removed. The electronic device24″ differs from the electronic device24′ in that the air gaps28′ have a larger volume than the air gaps28due to the removal of the portion of the liner26. The electronic device24″ differs from the electronic device24in that the air gaps28′ are present in place of the second and third dielectric materials8,18. The electronic device24″ differs from the electronic device24′ and the electronic device24in that the liner26′ is only laterally adjacent to the L2 contacts20proximal to the L1 bitlines16. In other words, the liner26′ does not extend along the entire height of the L2 contacts20. The liner26′ may, for example, extend a height less than the height H2of the L1 bitlines16. While the liner26′ may contribute to higher capacitance of the electronic device24″, by increasing the volume of the air gaps28′, the desired electrical performance of the electronic device24″ may be achieved.

The electronic device24′ ofFIGS.8A and8Bmay be further processed to form the electronic device24″ ofFIGS.3A and3B. By way of example only, a portion of the liner26may be selectively removed relative to the conductive materials of the L1 bitlines16and the L2 bitlines22, the L2 contacts20, the L1 contacts14, and the first dielectric material6. The removal of the portion of the liner26increases the volume of the air gaps28′ compared to the air gaps28in the electronic device24′. The portion of the liner26may be removed by conventional techniques.

The liner26′ may remain adjacent (e.g., laterally adjacent) to a portion of the L1 bitlines16and to a portion of the L2 contacts20, providing stability (e.g., structural stability) and electrical isolation to the L2 contacts20. As shown inFIGS.3A and3B, upper and lower surfaces of the liner26′ are recessed relative to upper and lower surfaces of the L1 bitlines16. However, the upper and lower surfaces of the liner26′ may be substantially coplanar with the upper and lower surfaces of the L1 bitlines16or may extend slightly above and slightly below the upper and lower surfaces of the L1 bitlines16. The amount of liner26′ remaining proximal to the L1 bitlines16may depend on the degree of stability to be provided to the L2 contacts20and/or the degree of isolation to be achieved between the L2 contacts20and other conductive components of the electronic device24″. The remaining amount of the liner26′ may be tailored by adjusting the conditions (e.g., the etch conditions) used to remove the portion of the liner26. By tailoring the liner26′, the air gaps28′ are correspondingly tailored to achieve desired properties of the electronic device24″.

Additional electronic devices24′″ and24″″ (seeFIGS.17A-18B) are also disclosed and are similar to the electronic devices24,24′,24″. The electronic devices24′″ and24″″ include L1 contacts14, L1 bitlines16, L2 contacts20, and L2 bitlines22. The electronic device24″″ also includes air gaps28. Methods of forming the electronic devices24′″ and24″″ (seeFIGS.17A-18B) are shown inFIGS.9A-16Band may be used to substantially reduce or prevent misalignment of the first and second levels (e.g., the first and second decks) of the electronic devices24′″ and24″″. Features (e.g., materials and structures) and method acts of forming the electronic devices24′″ and24″″ that are substantially similar to those of the electronic devices24,24′,24″ are as described above. Features and method acts that differ from those described above are further described below. While the electronic devices24′″ and24″″ are described and illustrated without a liner26, the liner26may be present.

As shown inFIGS.9A and9B, a first dielectric material6and a fourth dielectric material7may be formed and patterned. The first dielectric material6and the fourth dielectric material7may be one of the dielectric materials previously discussed and are selected to exhibit etch selectivity. In some embodiments, the first dielectric material6is silicon oxide and the fourth dielectric material7is silicon nitride. Openings9are formed through the fourth dielectric material7to expose locations in the first dielectric material6where L1 contacts14(seeFIGS.11A and11B) are ultimately to be formed. The openings9may be formed by conventional photolithography and removal techniques. InFIGS.9A and9B, a single material is shown as the first dielectric material6. However, two or more materials may be used, such as first dielectric material6and second dielectric material8.

A third dielectric material18is formed over the first dielectric material6and the fourth dielectric material7and openings11are formed into and through the first dielectric material6, as shown inFIGS.10A and10B. The third dielectric material18may be one of the dielectric materials previously discussed. In some embodiments, the third dielectric material18is an interlayer dielectric material. The openings11are formed in locations where L1 bitlines16(seeFIGS.11A and11B) are ultimately to be formed. In some locations, the openings11are formed through the third dielectric material18and through the first dielectric material6. The openings11may be formed by conventional photolithography and removal techniques. The openings11that extend into and through the first dielectric material6are formed in locations where the L1 contacts14and the L1 bitlines16(seeFIGS.11A and11B) are ultimately to be formed.

One or more conductive materials of the L1 contacts14and the L1 bitlines16are formed in the openings11, as shown inFIGS.11A and11B. The conductive material may be one or more of the conductive materials previously discussed. In some embodiments, the conductive material of the L1 contacts14and the L1 bitlines16is tungsten and titanium nitride is used as a liner for the tungsten of the L1 bitlines16. However, in other embodiments, different conductive materials may be used for the L1 contacts14and the L1 bitlines16. The conductive material may be formed by conventional techniques, at least partially filling the openings11to form the L1 contacts14and the L1 bitlines16. If the openings11are substantially filled with the conductive material, a portion of the conductive material is removed to recess the conductive material and form the L1 contacts14and the L1 bitlines16. A portion of the third dielectric material18may then be removed, widening the openings11to form openings11′ and to expose upper sidewalls of the L1 bitlines16. A desired portion of the third dielectric material18may be removed by conventional techniques, such as by a wet etch process. The increased width of the openings11′ enables a width at which the L2 bitlines22and L2 contacts20(seeFIGS.15A and15B) are formed to be narrower than a spacing of the L1 bitlines16and reduces or prevents shorting between the L1 contacts14, the L1 bitlines16, the L2 bitlines22, and the L2 contacts20.

As shown inFIGS.12A and12B, a cap material13may be formed in the openings11′. Since the openings11′ are wider than the openings11in which the L1 bitlines16are formed, the cap material13formed over the L1 bitlines16exhibits a greater width than a width of the L1 bitlines16. The cap material13may be a dielectric material. In some embodiments, the cap material13is silicon nitride. Excess cap material13formed over an upper surface of the third dielectric material18may be removed, such as by a CMP process. An upper surface of the cap material13may be substantially coplanar with the upper surface of the third dielectric material18. The cap material13protects the underlying L1 bitlines16during formation of the L2 contacts20and L2 bitlines22.

To form the L2 contacts20and L2 bitlines22, openings15(15A,15B) are formed in the third dielectric material18as shown inFIGS.13A-14B. The openings15may be formed by conducting multiple photolithography and removal acts. By way of example only, the openings15may be formed by a dry etch process. The openings15A are formed through the third dielectric material18and the first dielectric material6in locations where the L2 contacts20are ultimately to be formed, as shown inFIGS.13A and13B. The openings15A may be formed by conventional techniques, such as by conducting a reactive ion etch (RIE) process. A sacrificial material17, such as a resist material, is formed in the openings15A to protect materials underlying the sacrificial material17while the openings15B are formed. The sacrificial material17may at least partially fill the openings15A. If the sacrificial material17substantially fills the openings15A, a portion of the sacrificial material17may be removed to recess the sacrificial material17in the openings15A. As shown inFIGS.14A and14B, the openings15B are formed in locations where the L2 bitlines22are ultimately to be formed. The openings15B may be formed by conventional techniques, such as by conventional selective reactive ion etching techniques. Conventional photolithography techniques may be used to protect other portions of the memory array.

After removing the sacrificial material17, one or more conductive materials may be formed in the openings15A,15B to form the L2 contacts20and L2 bitlines22, as shown inFIGS.15A and15B. The conductive material may be one or more of the conductive materials previously discussed and may be formed by conventional techniques. In some embodiments, the conductive material of the L2 contacts20and the L2 bitlines22is tungsten and titanium nitride is used as a liner for the tungsten. However, in other embodiments, different conductive materials may be used for the L2 contacts20and the L2 bitlines22. Excess conductive material may be removed from over the cap material13, such as by CMP. The cap material13may then be removed, as shown inFIGS.16A and16B, forming the openings11′ and exposing a portion of the L1 bitlines16. The cap material13may be removed by conventional techniques.

As shown inFIGS.17A and17B, additional third dielectric material18is formed in the openings11′, in place of the cap material13, to form the electronic device24′″. Since the openings11′ are wider than the L1 bitlines16, the third dielectric material18may also be formed around a portion of the upper sidewalls of the L1 bitlines16. The third dielectric material18may be formed between the L2 contacts20and the L2 bitlines22and over the L1 bitlines16by conventional techniques. In some embodiments, the third dielectric material18is silicon dioxide. Excess third dielectric material18may be removed, such as by CMP, forming the electronic device24′″ ofFIGS.17A and17B. Adjacent (e.g., laterally adjacent) L2 bitlines22of the electronic device24′″ may, therefore, be separated from one another by the third dielectric material18and adjacent (e.g., laterally adjacent) L1 bitlines16may be separated from one another by the third dielectric material18. In addition, adjacent (e.g., laterally adjacent) L2 contacts20may be separated from one another by the third dielectric material18and adjacent (e.g., laterally adjacent) L1 contacts14may be separated from one another by the third dielectric material18and the first dielectric material6. The third dielectric material18, therefore, isolates the conductive components (e.g., the L1 contacts14, the L1 bitlines16, the L2 contacts20, the L2 bitlines22) of the electronic device24′″.

To form the electronic device24″″ shown inFIGS.18A and18B, exposed portions of the third dielectric material18inFIGS.16A and16Bmay be removed to form the air gaps28′. The electronic device24″″ includes the air gaps28′, which are formed by removing portions of the third dielectric material18. The third dielectric material18below the L2 bitlines22may be removed to form the air gaps28′ that extend from a lower surface of the L2 bitlines22and into the first dielectric material6. The air gaps28′ are located between the L2 contacts20, the L2 bitlines22, and the L1 bitlines16. The air gaps28′ may also extend below the L1 bitlines16proximal to the L2 contacts20in the first dielectric material6. Adjacent (e.g., laterally adjacent) L2 bitlines22may, therefore, be separated from one another by the air gaps28′ and adjacent (e.g., laterally adjacent) L1 bitlines16may be separated from one another by the air gaps28′. In addition, adjacent (e.g., laterally adjacent) L2 contacts20may be separated from one another by the air gaps28′ and adjacent (e.g., laterally adjacent) L1 contacts14may be separated from one another by the air gaps28′. The air gaps28′, therefore, isolate the conductive components (e.g., the L1 contacts14, the L1 bitlines16, the L2 contacts20, the L2 bitlines22) of the electronic device24″″.

During use and operation of the electronic devices24,24′,24″,24′″,24″″ containing the L1 bitlines16and the L2 bitlines22, each of the L1 bitlines16and the L2 bitlines22may be separately controlled by a respective select gate drain (SGD)1908(seeFIG.19) of the subblock. The ability to separately control the SGDs1908enables the L1 bitlines16and the L2 bitlines22to be separately controlled.

In the electronic devices24,24′,24″, lower resistance between adjacent L1 bitlines16is achieved compared to conventional electronic devices in which bitlines are located in only a single (e.g., one) level. Lower resistance is also achieved between adjacent L2 bitlines22compared to conventional electronic devices. The bitline-bitline capacitance of both the L1 bitlines16and the L2 bitlines22may also be lower in comparison to conventional electronic devices in which bitlines are located in only a single (e.g., one) level. The lower capacitance is able to be achieved in embodiments having the air gaps28while maintaining the integrity of the electronic devices24′,24″ because the liner26,26′ provides stability to the electronic devices24′,24″. The capacitance between the L1 bitlines16and the L2 contacts20is also lower due to the presence of the liner26,26′. In addition, the L1 contacts14and the L2 contacts20may be formed by processes having improved process margins compared by methods of forming the conventional electronic devices. The increased width of the L2 bitlines22compared to the width in the conventional electronic devices in which bitlines are located in only a single (e.g., one) level also contributes to the lower resistance.

In the electronic devices24′″,24″″, the capacitance between the L1 bitlines16and the L2 contacts20is reduced compared to conventional electronic devices in which bitlines are located in only a single (e.g., one) level since upper portions of the L1 bitlines16are surrounded by the third dielectric material18.

The multilevel bitlines16,22of the electronic devices24,24′,24″,24′″,24″″ may be formed at smaller pitches than bitlines of conventional electronic devices. Therefore, the multilevel bitlines16,22according to embodiments of the disclosure may achieve reduced bitline-bitline capacitance even while the first and second bitlines16,22are formed at lower pitches. Additionally, the bitline-bitline capacitance may be reduced by forming the first bitlines16and the second bitlines22in a staggered configuration. The multilevel bitlines16,22according to embodiments of the disclosure provide improved bitline-bitline capacitance between adjacent first and second bitlines16,22since the bitlines are in the staggered configuration. The improved bitline-bitline capacitance may be achieved even as the pitch of the first and second bitlines16,22is reduced. In other words, for a given pitch of the first and second bitlines16,22, the bitline-bitline capacitance is reduced compared to the bitline-bitline capacitance of a conventional electronic device. The staggered configuration of the bitlines also enables further scaling of the electronic device in the x- and z-directions.

Accordingly, an electronic device is disclosed and comprises multilevel bitlines comprising first bitlines and second bitlines. The first bitlines and the second bitlines are positioned at different levels. Pillar contacts are electrically connected to the first bitlines and to the second bitlines. Level 1 contacts are electrically connected to the first bitlines and level 2 contacts are electrically connected to the second bitlines. A liner is between the first bitlines and the level 2 contacts. Each bitline of the first bitlines is electrically connected to a single pillar contact in a subblock adjacent to the level 1 contacts and each bitline of the second bitlines is electrically connected to a single pillar contact adjacent to the level 2 contacts.

Accordingly, a method of forming an electronic device is disclosed and comprises forming a first level comprising first bitlines and level 1 contacts in a first dielectric material. A second dielectric material is formed adjacent to the first level. Openings are formed through the second dielectric material and into the first dielectric material and a liner is formed in the openings. A conductive material is formed in the openings to form level 2 contacts adjacent to the liner and level 2 bitlines are formed in electrical contact with the level 2 contacts.

Accordingly, a method of forming an electronic device is disclosed and comprises forming a first level comprising first bitlines and level 1 contacts in openings in a dielectric material. A cap material is formed adjacent to the first level and in the openings and adjacent to the first bitlines and level 1 contacts. A width of the cap material is greater than a width of the first bitlines. A portion of the dielectric material between adjacent first bitlines is removed to form openings between adjacent portions of the cap material. A sacrificial material is formed in the openings between the adjacent portions of the cap material. An additional portion of the dielectric material is removed to form additional openings in the dielectric material. One or more conductive materials is formed in the openings and in the additional openings to form second bitlines and level 2 contacts in electrical contact with one another.

The multilevel bitlines16,22in the electronic devices24,24′,24″,24′″,24″″ (shown inFIG.19as1901) according to embodiments of the disclosure correspond to multilevel bitlines1902and are electrically connected to access lines (e.g., wordlines1905), as shown in apparatus1900ofFIG.19. The apparatus1900includes the multilevel bitlines1902(e.g., first bitlines16and second bitlines22) of the electronic devices24,24′,24″,24′″,24″″. The apparatus1900includes blocks (e.g., memory blocks), with each block including multiple subblocks that contain the multilevel bitlines1902. In some embodiments, each block includes four subblocks. In other embodiments, each block includes six subblocks. The apparatus1900may include a staircase structure1920defining contact regions for connecting the wordlines1905to conductive materials of tiers, which are positioned below the pillar contacts. The apparatus1900may include vertical strings1907of memory cells1903that are coupled to each other in series. The vertical strings1907may extend vertically (e.g., in the Z-direction) and orthogonally to the multilevel bitlines1902. The apparatus1900also includes first select gate drain1908(e.g., upper select gates, first select gates, select gate drains (SGDs)), select lines1909, and a second select gate1910(e.g., a lower select gate, a source select gate (SGS).

The apparatus1900may also include a control unit1912positioned under the staircase structure1920. The control unit1912may include at least one of string driver circuitry, pass gates, circuitry for selecting gates, circuitry for selecting the multilevel bitlines1902and the wordlines1905, circuitry for amplifying signals, and circuitry for sensing signals. The control unit1912may be electrically coupled to the multilevel bitlines1902including the L1 bitlines16and the L2 bitlines22, the wordlines1905, a source tier1904, the first select gate drain1908, and the second select gates1910, for example. In some embodiments, the control unit1912includes CMOS (complementary metal-oxide-semiconductor) circuitry. In such embodiments, the control unit1912may be characterized as having a “CMOS under Array” (“CuA”) configuration. The electronic devices24,24′,24″,24′″,24″″ or apparatus1900according to embodiments of the disclosure may include, but is not limited to, a 3D electronic device, such as a 3D NAND Flash memory device, (e.g., a multideck 3D NAND Flash memory device).

During use and operation, the apparatus1900containing the first bitlines16and the second bitlines22(e.g., the multilevel bitlines16,22) may be independently controlled by a respective SGD1908of the subblock. The SGDs1908are formed adjacent to (e.g., under) the first bitlines16and the second bitlines22, as known in the art. Within a particular block, the wordlines1905are connected together and the SGDs1908have different biases and may be separately controlled. Therefore, the first bitlines16and the second bitlines22may read out the state of a selected memory cell between “ON” and “OFF,” and control the potential of the vertical strings using the SGDs1908.

One or more of the electronic devices24,24′,24″,24′″,24″″ or apparatus1900may be present in a memory array2000, as shown schematically inFIG.20. The memory array2000includes a memory array of memory cells2002and a control logic component2004. The electronic devices24,24′,24″,24′″,24″″ or the apparatus1900according to embodiments of the disclosure include multiple memory cells. The control logic component2004may be configured to operatively interact with the memory array of memory cells2002so as to read, write, or re-fresh any or all memory cells within the memory array of memory cells2002. The memory cells of the memory array2000are coupled to access lines (e.g., the wordlines1905), and the access lines are coupled to control gates of the memory cells. A string of memory cells of the memory array2000is coupled in series between a source line and the multilevel bitlines1902. The memory cells are positioned between the wordlines1905and the multilevel bitlines1902. The wordlines1905may be in electrical contact with, for example, conductive materials of the tiers, and the multilevel bitlines1902may be in electrical contact with an electrode (e.g., a top electrode) of the tiers. The multilevel bitlines1902may directly overlie a row or column of the memory cells and contact the top electrode thereof. Each of the wordlines1905may extend in a first direction and may connect a row of the memory cells. Each of the multilevel bitlines1902may extend in a second direction that is at least substantially perpendicular to the first direction and may connect a column of the memory cells. A voltage applied to the wordlines1905and the multilevel bitlines1902may be controlled such that an electric field may be selectively applied at an intersection of at least one wordline1905and at least one multilevel bitline1902, enabling the memory cells to be selectively operated. Additional process acts to form the memory array2000including the one or more electronic devices24,24′,24″,24′″,24″″ or apparatus1900are conducted by conventional techniques.

An electronic system2100is also disclosed, as shown inFIG.21, and includes the one or more electronic devices24,24′,24″,24′″,24″″ or apparatus1900according to embodiments of the disclosure.FIG.21is a simplified block diagram of the electronic system2100implemented according to one or more embodiments described herein. The electronic system2100may comprise, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular telephone, a digital camera, a personal digital assistant (PDA), portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet such as, for example, an iPad® or SURFACE® tablet, an electronic book, a navigation device, etc. The electronic system2100includes at least one memory device2102, which includes the electronic devices24,24′,24″,24′″,24″″ or apparatus1900as previously described. The electronic system2100may further include at least one processor device2104, such as a microprocessor, to control the processing of system functions and requests in the electronic system2100. The processor device2104and other subcomponents of the electronic system2100may include the memory cells. The processor device2104may, optionally, include one or more memory arrays2100as previously described.

Various other devices may be coupled to the processor device2104depending on the functions that the electronic system2100performs. For example, an input device2106may be coupled to the processor device2104for inputting information into the electronic system2100by a user, such as, for example, a mouse or other pointing device, a button, a switch, a keyboard, a touchpad, a light pen, a digitizer and stylus, a touch screen, a voice recognition system, a microphone, a control panel, or a combination thereof. An output device2108for outputting information (e.g., visual or audio output) to a user may also be coupled to the processor device2104. The output device2108may include an LCD display, an SED display, a CRT display, a DLP display, a plasma display, an OLED display, an LED display, a three-dimensional projection, an audio display, or a combination thereof. The output device2108may also include a printer, an audio output jack, a speaker, etc. In some embodiments, the input device2106and the output device2108may comprise a single touchscreen device that can be used both to input information to the electronic system2100and to output visual information to a user. The one or more input devices2106and output devices2108may communicate electrically with at least one of the memory device2102and the processor device2104. The at least one memory device2102and processor device2104may also be used in a system on chip (SoC).

Accordingly, a system is disclosed. The system comprises a processor operably coupled to an input device and an output device, and one or more electronic devices operably coupled to the processor. The one or more electronic devices comprise multilevel bitlines comprising first bitlines and second bitlines. The first bitlines and second bitlines are positioned at different levels and the first bitlines and the second bitlines are electrically connected to memory cells. Level 1 contacts are electrically connected to the first bitlines and level 2 contacts are electrically connected to the second bitlines. The level 2 contacts are separated from laterally adjacent first bitlines by a liner. Pillar contacts are electrically connected to the first bitlines and to the second bitlines.

While certain illustrative embodiments have been described in connection with the figures, those of ordinary skill in the art will recognize and appreciate that embodiments encompassed by the disclosure are not limited to those embodiments explicitly shown and described herein. Rather, many additions, deletions, and modifications to the embodiments described herein may be made without departing from the scope of embodiments encompassed by the disclosure, such as those hereinafter claimed, including legal equivalents. In addition, features from one disclosed embodiment may be combined with features of another disclosed embodiment while still being encompassed within the scope of the disclosure.