Patent ID: 12197735

In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.

DETAILED DESCRIPTION OF ILLUSTRATIVE EXAMPLES

A memory controller includes a command queue, an arbiter circuit, and a memory sprint controller. The command queue has a plurality of entries for holding memory access commands. The arbiter circuit is for selecting memory access commands from the command queue for dispatch over a memory channel to a dynamic random access memory (DRAM). The memory sprint controller, responsive to an indicator of an irregular memory access phase, enters a sprint mode in which it temporarily adjusts at least one timing parameter of the DRAM to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM.

A method includes receiving a plurality of memory access commands and selecting memory access commands from the plurality of memory access commands for dispatch over a memory channel to a DRAM. Responsive to an indicator of an irregular memory access phase, the method includes entering a sprint mode by temporarily adjusting at least one timing parameter of the DRAM to reduce a time in which a designated number of ACT commands are allowed to be dispatched to the DRAM.

A data processing system includes a processor, a data fabric coupled to the processor, and a memory controller coupled to the data fabric for fulfilling memory access requests made through the data fabric. The memory controller includes a command queue, an arbiter circuit, and a memory sprint controller. The command queue has a plurality of entries for holding memory access commands. The arbiter circuit is for selecting memory access commands from the command queue for dispatch over a memory channel to a DRAM. The memory sprint controller, responsive to an indicator of an irregular memory access phase, enters a sprint mode in which it temporarily adjusts at least one timing parameter of the DRAM to reduce a time in which a designated number of ACT commands are allowed to be dispatched to the DRAM.

The total transfer rates or throughput for a memory module is affected by whether the memory accesses frequently access memory rows that are already open (regular accesses) or access a higher variety of addresses in an irregular sequence (irregular accesses). Various applications such as hyperscalars, high-performance computing (HPC), advanced driver assistance systems (ADAS), and gaming and computer graphics frequently run irregular applications like graph analytics, unstructured grid simulations, and point-cloud data processing. Such applications frequently exhibit irregular memory access periods, which are time periods or phases in which accesses frequently involve activating a row in the DRAM memory. The appearance of irregular memory access periods tend to reduce the bandwidth efficiency and throughput of the DRAM channel as compared with the those of regular memory access periods, which include more frequent accesses to already activated rows. These efficiency issues are a result of timing associated with activating a new row, as compared with accessing an already open or activated row.

One proposed solution to these efficiency issues is to adopt very small row sizes in the DRAM memory. Another solution is to increase the number of voltage pumps and power delivery networks for the networks for the wordline voltage (VPP) inside the DRAM device to mitigate the power burden of activating a row. However, while these approaches may be useful for specific applications, they are not favored for mainstream memory designs because of the increased costs of including such features and the timeline necessary for adoption.

FIG.1illustrates in block diagram form an accelerated processing unit (APU)100with a connected DRAM memory according to some embodiments. APU100is implemented as a System-on-Chip (SoC) which may be part of a variety of host data processing platforms. While an APU is shown in this embodiment, other data processing platforms such as a central processing unit (CPU) or a graphics processing unit (GPU) may be used. APU100includes generally a CPU core complex110, a graphics core120, a set of display engines130, a memory management hub140, a data fabric150, a set of peripheral controllers160, a set of peripheral bus controllers170, a system management unit (SMU)180, a platform security processor (PSP)210, a flash memory205, a set of memory controllers190. Also shown connected to APU100are two DRAM memories193and195, and a liquid cooling system196, which together form a data processing system.

CPU core complex110includes a CPU core112and a CPU core114. In this example, CPU core complex110includes two CPU cores, but in other embodiments CPU core complex110can include an arbitrary number of CPU cores. Each of CPU cores112and114is bidirectionally connected to a system management network (SMN)145, which forms a control fabric, and to data fabric150, and is capable of providing memory access requests to data fabric150. Each of CPU cores112and114may be unitary cores, or may further be a core complex with two or more unitary cores sharing certain resources such as caches.

Graphics core120is a high performance graphics processing unit (GPU) capable of performing graphics operations such as vertex processing, fragment processing, shading, texture blending, and the like in a highly integrated and parallel fashion. Graphics core120is bidirectionally connected to the SMN145and to data fabric150, and is capable of providing memory access requests to data fabric150. In this regard, APU100may either support a unified memory architecture in which CPU core complex110and graphics core120share the same memory space, or a memory architecture in which CPU core complex110and graphics core120share a portion of the memory space, while graphics core120also uses a private graphics memory not accessible by CPU core complex110.

Display engines130render and rasterize objects generated by graphics core120for display on a monitor. Graphics core120and display engines130are bidirectionally connected to a common memory management hub140for uniform translation into appropriate addresses in memory, and memory management hub140is bidirectionally connected to data fabric150for generating such memory accesses and receiving read data returned from the memory system. Data fabric150includes a crossbar switch for routing memory access requests and memory responses between any memory accessing agent and memory controllers190. It also includes a system memory map, defined by basic input/output system (BIOS), for determining destinations of memory accesses based on the system configuration, as well as buffers for each virtual connection.

Peripheral controllers160include a USB controller162and a serial advanced technology attachment (SATA) interface controller164, each of which is bidirectionally connected to a system hub166and to SMN145. These two controllers are merely exemplary of peripheral controllers that may be used in APU100.

Peripheral bus controllers170include a system controller hub172and a peripheral controller hub174, each of which is bidirectionally connected to an input/output (I/O) hub176and to SMN145. System controller hub172connects to Flash memory205over a suitable communications link. I/O hub176is also bidirectionally connected to system hub166and to data fabric150. Thus, for example, a CPU core can program registers in USB controller162, SATA interface controller164, system controller hub172, or peripheral controller hub174through accesses that data fabric150routes through I/O hub176.

SMU180is a local controller that controls the operation of the resources on APU100and synchronizes communication among them. SMU180manages power-up sequencing of the various processors on APU100and controls multiple off-chip devices via reset, enable and other signals. SMU180also manages power for the various processors and other functional blocks.

Set of memory controllers190includes a first memory controller192coupled to a DRAM memory193, and a second memory controller194coupled to a DRAM memory195. Each of memory controller193and195includes a bidirectional connection to data fabric150, a bidirectional connection to SMN145, and a bidirectional connection to a respective DRAM memory over a DRAM channel. In this embodiment, DRAM memories193and195are HBM memory modules, but in other embodiments may be other types of memory modules such as DDRx DIMMs.

Liquid cooling system196has a bidirectional connection to data fabric150, but may instead be connected to SMN145. Liquid cooling system196is thermally coupled to each of DRAM memories193and195through a liquid coolant flow system, and generally includes electronics for controlling the flow of liquid coolant to provide additional cooling to DRAM memories193and195.

Platform security processor (PSP)210is a local security controller that controls the firmware booting process aboard APU100. PSP210also performs certain software validation and Firmware Anti-Rollback (FAR) features, as will be further described below.

In operation, CPU cores112and114, and graphics cores120, may execute tasks that generate memory accesses to memory controllers192and194with irregular access phases in which a new memory row is activated more frequently than during regular or typical memory operation. To handle such phases with more efficient use of the DRAM channels, memory controllers192and194are able to enter a sprint mode in which memory timing parameters are adjusted, as further discussed below. During a sprint mode, liquid cooling system196may also be used to increase coolant flow to one or both of DRAM memories193and195.

While a SoC implementation is shown, this is not limiting, and other computing platforms may also benefit from memory sprint techniques set forth herein.

FIG.2illustrates in block diagram form a memory controller200that is suitable for use in an APU like that ofFIG.1. Memory controller200includes generally an interface212, a memory interface queue214, a command queue220, an address generator222, a content addressable memory (CAM)224, a memory sprint controller230, a refresh control logic block232, refresh control logic232, a timing block234, a page table236, an arbiter238, an ECC generation block244, a data buffer246.

Interface212has a first bidirectional connection to data fabric over an external bus, and has an output. In memory controller200, this external bus is compatible with the advanced extensible interface version four specified by ARM Holdings, PLC of Cambridge, England, known as “AXI4”, but can be other types of interfaces in other embodiments. Interface212translates memory access requests from a first clock domain known as the FCLK (or MEMCLK) domain to a second clock domain internal to memory controller200known as the UCLK domain. Similarly, memory interface queue214provides memory accesses from the UCLK domain to a DFICLK domain associated with the DFI interface.

Address generator222decodes addresses of memory access requests received from the data fabric over the AXI4 bus. The memory access requests include access addresses in the physical address space represented in a normalized format. Address generator222converts the normalized addresses into a format that can be used to address the actual memory devices in memory system, as well as to efficiently schedule related accesses. This format includes a region identifier that associates the memory access request with a particular rank, a row address, a column address, a bank address, and a bank group. On startup, the system BIOS queries the memory devices in memory system to determine their size and configuration, and programs a set of configuration registers associated with address generator222. Address generator222uses the configuration stored in the configuration registers to translate the normalized addresses into the appropriate format. Command queue220is a queue of memory access requests received from the memory accessing agents in APU100, such as CPU cores112and114and graphics core120. Command queue220stores the address fields decoded by address generator222as well other address information that allows arbiter238to select memory accesses efficiently, including access type and quality of service (QOS) identifiers. CAM224includes information to enforce ordering rules, such as write after write (WAW) and read after write (RAW) ordering rules. Command queue220is a stacked command queue including multiple entry stacks each containing multiple command entries, in this embodiment 32 entry stacks of four entries each, as further described below.

Error correction code (ECC) generation block244determines the ECC of write data to be sent to the memory. This ECC data is then added to the write data in data buffer246. An ECC check circuit (not shown separately) checks the received ECC against the incoming ECC.

In this embodiment, memory sprint controller230is a digital circuit including a bidirectional connection to interface212, a bidirectional connection to arbiter238, a bidirectional connection to memory interface queue214, and a bidirectional connection to timing block234. Generally, memory sprint controller230is operable to, responsive to an indicator of an irregular memory access phase, enter a sprint mode in which it temporarily adjusts at least one timing parameter of the DRAM to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the RAM. The functionality of memory sprint controller230is further described below with respect toFIG.5-FIG.7. Memory sprint controller230may also include circuitry for calculating a ratio of column-address strobe (CAS) commands to ACT commands, on which the indicator of an irregular memory access phase is based in some embodiments. Such a ratio may be forward looking, that is, calculated based on memory access commands currently in the command queue. Or, such a ratio may be calculated based on a rolling window of memory access commands dispatched to the DRAM.

Refresh control logic232includes state machines for various powerdown, refresh, and termination resistance (ZQ) calibration cycles that are generated separately from normal read and write memory access requests received from memory accessing agents. For example, if a memory rank is in precharge powerdown, it must be periodically awakened to run refresh cycles. Refresh control logic232generates refresh commands periodically and in response to designated conditions to prevent data errors caused by leaking of charge off storage capacitors of memory cells in DRAM chips. In addition, refresh control logic232periodically calibrates ZQ to prevent mismatch in on-die termination resistance due to thermal changes in the system.

Arbiter238is bidirectionally connected to command queue220and is the heart of memory controller200, performing intelligent scheduling of accesses to improve the usage of the memory bus. Arbiter238uses timing block234to enforce proper timing relationships by determining whether certain accesses in command queue220are eligible for issuance based on DRAM timing parameters. For example, each DRAM has a minimum specified time between activate commands to the same bank, known as “tRC”, a time four activate window known as “tFAW” which provides a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the RAM, and a minimum specified time required between any two refresh per-bank (REFpb) or refresh per two banks (REFp2b) commands, known as “tRREFD”. Timing block234maintains a set of counters that determine eligibility based on this and other timing parameters specified in the JEDEC specification, based on a set of DRAM timing parameters stored locally in a timing parameter table or other suitable data structure. Page table236maintains state information about active pages in each bank and rank of the memory channel for arbiter238. Arbiter238includes a single command input for each entry stack of command queue220, and selects commands therefrom to schedule for dispatch through memory interface queue214to the DRAM channel.

In response to write memory access requests received from interface212, ECC generation block244computes an ECC according to the write data. Data buffer246stores the write data and ECC for received memory access requests. It outputs the combined write data/ECC to memory interface queue214when arbiter238picks the corresponding write access for dispatch to the memory channel.

Memory controller200includes circuitry that allows it to pick memory accesses for dispatch to the associated memory channel. In order to make the desired arbitration decisions, address generator222decodes the address information into predecoded information including rank, row address, column address, bank address, and bank group in the memory system, and command queue220stores the predecoded information. Configuration registers (not shown) store configuration information to determine how address generator222decodes the received address information. Arbiter238uses the decoded address information, timing eligibility information indicated by timing block234, and active page information indicated by page table236to efficiently schedule memory accesses while observing other criteria such as quality of service (QOS) requirements.

FIG.3illustrates in block diagram form a portion of a memory system300according to some alternative embodiments. The depicted portion of memory system300implements a memory sprint controller as software or firmware, as opposed to the hardware implementation shown inFIG.2, and is suitable for use with a memory controller constructed as described above with respect toFIG.2, only without memory sprint controller230implemented in the memory controller. The depicted portion of a memory system300includes a processor312executing a memory sprint controller software or firmware module314in communication with a memory controller392including timing parameters334, which as discussed above control a timing block of the memory controller.

Processor312may be any type of processor that generates memory accesses to a memory controller and has need of improving DRAM channel efficiency during irregular memory access periods. For example, some or all of CPU cores112and114and graphics cores120(FIG.1) may employ memory sprint controller software or firmware modules314. In some embodiments, another dedicated processor core in the host SoC may execute one or more memory sprint controller software or firmware modules314. For example, such a processor core may be attached to data fabric150and be in communication with multiple CPU or GPU cores for implementing a memory sprint controller.

As shown inFIG.3, in this embodiment memory sprint controller software or firmware module314receives application hints or outputs of core performance counters316from various applications or processor core firmware to characterize the memory accesses for a DRAM accessed through memory controller392. An application hint is a message from an application, such as an inter-thread message or other suitable message format, that communicates that the application is starting or ending a series of irregular memory accesses. Such hints may be provided by application developers through an application protocol interface (API), for example. Core performance counters such as translation lookaside buffer (TLB) misses may be passed to memory sprint controller software or firmware module314. Based on such core performance counters, memory sprint controller software or firmware module314may identify when an irregular memory access phase has started or will start, and has ended or will end.

Memory sprint controller software or firmware module314also receives various data from memory controller392, passed through interface212for example, and used for determining when to enter and leave memory sprint modes. An irregularity metric may be communicated, as shown by arrow396. Such an irregularity metric may be a CAS/ACT ratio, as further discussed below, or other metrics or performance counter data tracked by memory performance counters in memory controller392, based upon which an irregular memory access phase may be identified. For example, performance counter data such as CAS commands issued, ACT commands issued may be passed from memory controller392to memory sprint controller software or firmware module314. Memory power draw and memory temperature data398are communicated from memory controller392to memory sprint controller software or firmware module314. These data elements provide current temperature and power draw readings from the DRAM for determining whether a memory sprint may be safely entered or continued.

In order to control the memory sprint phase, memory sprint controller software or firmware module314causes memory sprint control signals394to be transmitted to memory controller392. In this embodiment, the memory sprint control signals are implemented by writing new values to selected timing parameters in timing parameters334. In other embodiments, other suitable signals commanding memory controller392to start and stop a memory sprint mode may be used. For example, two or more sets of timing parameters may be held at memory controller392, which may be instructed to change operation to use a different set of timing parameters.

In operation, memory sprint controller software or firmware module314, responsive to an indicator of an irregular memory access phase, causes the memory controller to enter a sprint mode in which it temporarily adjusts at least one timing parameter of the DRAM to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the DRAM. As further described below, memory sprint controller software or firmware module314may also adjust other timing parameters. Memory sprint controller software or firmware module314may also control a liquid cooling system to increase coolant flow to the DRAM.

As can be understood, while a hardware implementation and a software/firmware implementation have been shown, in other embodiments the functionality of a memory sprint controller may be implemented by a mixture of memory controller hardware and system software/firmware in cooperation.

FIG.4shows a timing diagram400illustrating an example scenario including irregular memory access phase without a memory sprint mode. Timing diagram400shows a series of memory access commands dispatched to a DRAM over time. The depicted scenario includes two regular memory access phases, labelled “Regular Phase”, and an irregular memory access phase labelled “Irregular Phase”. In the first Regular Phase, an ACT command is followed by five read commands (“RD”) to the activated row, with a tFAW timing interval labelled “tFAW” shown relative to the commands. In the Irregular Phase, only one read is performed to each activated row for seven consecutive ACT commands. During a tFAW interval only a designated number (four) activated commands are allowed to be dispatched, and so the fifth ACT in the Irregular phase is delayed. As discussed above, the length of tFAW is typically set to limit high row activation power, and so the highlighted delay before the fifth ACT allows time for the memory PDN to recover from the first four ACT commands. A new fFAW interval begins and the fifth ACT command is allowed to be dispatched. As can be understood, the longer the setting for tFAW, the more inefficiency may result during an irregular memory access phase because a longer delay results at the location of the depicted delay. The depicted scenario is one in which no memory sprint is employed, and tFAW is constant across the Regular Phases and the Irregular Phase.

FIG.5shows a timing diagram500illustrating an example scenario including an irregular memory access phase during a memory sprint mode. As shown, the tFAW timing interval is shrunk at the start of an Irregular Phase, as indicated by the shorter tFAW interval labelled “tFAW shrink”. This allows the fifth ACT command in the Irregular Phase to immediately follow the fourth ACT command, increasing the bandwidth efficiency during the Irregular Phase. The timing window is expanded again to end the memory sprint mode after two of the tFAW shrink periods. As discussed further below, ending the memory sprint mode may be based on the irregular access phase ending, or based on the memory temperature exceeding a designated temperature, such as the thermal design point, or the memory power draw exceeding a predetermined threshold.

FIG.6shows a flowchart600of a process for controlling a memory sprint mode according to some embodiments. The depicted process is suitable for use with a variety of SoCs such as APU100(FIG.1) or other processing SoCs which may use a variety of processor types. The process is suitable for use with a memory controller including a memory sprint controller320(FIG.2), or a system with a software or firmware based memory sprint controller such as a that ofFIG.3, or a mixed implementation in which some of the process is performed in the memory controller and some in one or more processors. While flowchart600shows a linear process flow, it is understood that actions may occur in a different order using a different logical flow such as an event-driven process in which changes in inputs cause the memory sprint controller to perform actions in response.

At block602, the process includes a memory sprint controller observing or predicting an indicator of an irregular memory access phase. Block602may include calculating the indicator of an irregular memory access phase, or the indicator may be observed directly from data provided to the memory sprint controller. For example, the indicator of the irregular memory access phase may be based on a ratio of column-address strobe (CAS) commands to ACT commands. Such a ratio may be forward looking, that is, calculated based on memory access commands currently in the command queue of the memory controller. Or, such a ratio may be calculated based on a rolling window of memory access commands dispatched to the DRAM. As another example, the indicator of an irregular memory access phase may be a hint from a processor coupled to the memory controller communicating that a period with frequent irregular memory accesses will occur. As yet another example, the indicator of an irregular memory access phase may include a communication from an application running on a host processor indicating that a period with frequent irregular memory accesses will occur. Other performance metrics from the memory controller or the host processor may also be used in calculating or producing the indicator of an irregular memory access phase.

At block604, the process determines whether an indicator is above or below a threshold. If so, flow goes directly or indirectly to a block612, in which the process causes the memory controller to enter a sprint mode by temporarily adjusting at least one timing parameter of a random access memory (RAM) to reduce a time in which a designated number of activate (ACT) commands are allowed to be dispatched to the RAM. As shown at block604, in this embodiment, the indicator is determined to be above a designated threshold. In other embodiments, a Yes/No indicator may be used, or a number of data points may be used together to make the decision at block604that an irregular memory access phase will start or has started.

In some embodiments, as indicated by the dotted boxes on flowchart600, additional data is checked before starting a memory sprint phase. At block604, the memory sprint controller receives data about the current power usage and current temperature of the DRAM memory device or module for which a memory sprint may be activated. At block608, this data is checked to determine if the power usage is below a designated threshold and the temperature is below a designated threshold. If so, the process continues to block612where it starts the memory sprint mode.

At block612, the the process starts memory sprint mode by temporarily adjusting at least one timing parameter of the DRAM to reduce a time in which a designated number of ACT commands are allowed to be dispatched to the DRAM. In one example, the tFAW is reduced at this point to shorten the time window limiting ACT commands sent to the DRAM. In some embodiments, other timing parameters may be changed. For example, a refresh interval may be increased to compensate for greater local power draws in the DRAM PDN due to the sprint mode. As shown, in this embodiment, the tRREFD interval is increased. In some embodiments, temporarily adjusting the at least one timing parameter of the DRAM includes causing a new value to be written to a timing parameter table of the memory controller. For memory systems that include a liquid cooling system, such as liquid cooling system196ofFIG.1, the memory sprint mode may also include commanding the liquid cooling system to increase the flow of coolant to the DRAM.

From block612, the process returns to block602where it continues to observe or predict the irregularity indicator. During the memory sprint mode, if the indicator of an irregular memory access phase drops below the threshold at block604, the process goes to block611where it ends the memory sprint mode. As shown, ending the memory sprint mode in this embodiment includes increasing the time in which a designated number of ACT commands are allowed to be dispatched to the DRAM, in this embodiment the tFAW parameter. This parameter is set back to its normal value. If a refresh interval has been increased during the memory sprint mode, it is also decreased at block611. If a memory coolant flow was increased during the memory sprint mode, it is also decreased at block611. Decreasing coolant flow may be performed with delay in order to remove additional heat generated during the memory sprint mode.

During the memory sprint mode, if the indicator of an irregular memory access phase is still above the threshold at block604, the process may also decide to end the memory sprint mode based on the temperature or power consumption of the memory device. As shown at blocks604and606, the DRAM temperature and DRAM power consumption are also monitored during the memory sprint mode. If either one exceeds their designated threshold, the process at block610goes to block611where it ends the memory sprint mode as described above. If neither threshold is exceeded at block610, the process continues the memory sprint mode.

Thus a process has been described suitable for use with a hardware based memory sprint controller, or a software or firmware based memory sprint controller. While this particular process may be used for a memory sprint controller, other suitable processes may also be used with hardware or software/firmware based memory sprint controllers. For example, the process ofFIG.6implements the memory sprint by temporarily adjusting one or more timing parameters for the DRAM without concern for the memory clock speed or voltage. In other embodiments, a change in the memory clock speed and data rate may be used instead of or in addition to adjusting one or more timing parameters of the DRAM, assuming that the DRAM and DRAM channel support a ramp time fast enough to benefit from such a memory sprint mode.

Generally, a memory sprint mode as described herein includes a temporary adjustment that ends, as described, when the irregular memory access phase is completed or when thermal or power conditions at the memory no longer allow the increased rate of ACT commands. In some memory systems, or in some conditions, the memory sprint mode may be as short as one or two periods of the tFAW timing parameter, while in other memory systems a sprint mode may be allowed to be active for a longer time. For example, some systems may provide for memory sprint modes that last many iterations of the tFAW period, such a 4, 8, 16, 32 or some other power-of-two multiple tFAW periods before thermal and power conditions at the memory trigger an exit from the memory sprint mode. While the process of selecting the length of the reduced tFAW period depends on the capabilities of the particular DRAM memory in use in the system, ideally it should be selected to allow release of ACT commands as soon as they are available, as depicted inFIG.5. The speed of reporting temperature and power data from the DRAM for use in the memory sprint control process should also be considered, and would generally be set as fast as allowable for a particular DRAM memory in order to best control a memory sprint mode.

FIG.7shows a chart comparing the throughput bandwidth for a DRAM channel for a baseline system without memory a memory sprint mode and a system using a memory sprint mode. The vertical axis shows the shows throughput bandwidth. On the left is shown throughput for an irregular access period for which a benchmark application for giga-updates per second (GUPS) is used. On the right is shown throughput for a regular access period for which a benchmark streaming application is used. Results are shown for normal timing parameter values, labelled “Baseline”, and for memory sprint mode timing values (labelled “lower tFAW, higher tRREFD”). In the tests, tRREFD is increased from 8 nanoseconds (ns) (baseline) to 30 ns, a nominal value selected to compensate for tFAW=4xtRRD in a reference 1 TB/s HBM3 device.

Using the sprint mode, throughput is greatly increased for the GUPS benchmark application, while throughput is slightly reduced for the streaming benchmark application. The techniques herein to improve irregular access bandwidth by lowering tFAW in conjunction with increasing tRREFD affects regular bandwidth adversely. Increasing tRREFD from 8 ns to 30 ns to compensate for an optimal tFAW=4*tRRDS degrades regular bandwidth by 7.25% in this test. While a lower tFAW may be compensated for by increasing the refresh period to obtain better irregular bandwidth, this technique affects regular streaming application performance by increasing the time period when a bank remains inaccessible.

The circuits ofFIG.1,FIG.2, andFIG.3, or any portions thereof, such as arbiter238and memory sprint controller230may be described or represented by a computer accessible data structure in the form of a database or other data structure which can be read by a program and used, directly or indirectly, to fabricate integrated circuits. For example, this data structure may be a behavioral-level description or register-transfer level (RTL) description of the hardware functionality in a high level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool which may synthesize the description to produce a netlist including a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware including integrated circuits. The netlist may then be placed and routed to produce a data set describing geometric shapes to be applied to masks. The masks may then be used in various semiconductor fabrication steps to produce the integrated circuits. Alternatively, the database on the computer accessible storage medium may be the netlist (with or without the synthesis library) or the data set, as desired, or Graphic Data System (GDS) II data.

While particular embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. For example, the internal architecture of memory controller200may vary in different embodiments. Memory controller200may interface to other types of memory besides DDRx, such as high bandwidth memory (HBM), RAMbus DRAM (RDRAM), and the like. While the illustrated embodiment showed each rank of memory corresponding to separate DIMMs or SIMMs, in other embodiments each module can support multiple ranks. Still other embodiments may include other types of DRAM modules or DRAMs not contained in a particular module, such as DRAMs mounted to the host motherboard. Accordingly, it is intended by the appended claims to cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.