Patent ID: 12255251

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and in which are shown by way of illustrations specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. For example, features illustrated or described for one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present invention includes such modifications and variations. The examples are described using specific language, which should not be construed as limiting the scope of the appending claims. The drawings are not scaled and are for illustrative purposes only. For clarity, the same elements have been designated by corresponding references in the different drawings if not stated otherwise.

The terms “having”, “containing”, “including”, “comprising” and the like are open, and the terms indicate the presence of stated structures, elements or features but do not preclude the presence of additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

The term “electrically connected” describes a permanent low-resistive connection between electrically connected elements, for example a direct contact between the concerned elements or a low-resistive connection via a metal and/or heavily doped semiconductor material. The term “electrically coupled” includes, in addition to a permanent low-resistive connection, that one or more intervening element(s) adapted for signal and/or power transmission may be connected between the electrically coupled elements, for example, elements that are controllable to temporarily provide a low-resistive connection in a first state and a high-resistive electric decoupling in a second state. An ohmic contact is a non-rectifying electrical junction with a linear or almost linear current-voltage characteristic.

Ranges given for physical dimensions include the boundary values. For example, a range for a parameter y from a to b reads as a≤y≤b. A parameter y with a value of at least c reads as c≤y and a parameter y with a value of at most d reads as y≤d.

The term “on” is not to be construed as meaning only “directly on”. Rather, if one element is positioned “on” another element (e.g., a layer is “on” another layer or “on” a substrate), a further component (e.g., a further layer) may be positioned between the two elements (e.g., a further layer may be positioned between a layer and a substrate if the layer is “on” said substrate).

An example of a semiconductor device may include a drift region of a first conductivity type in a semiconductor body having a first main surface. The semiconductor device may further include a body region of a second conductivity type between the drift region and the first main surface. The semiconductor device may further include a plurality of trenches extending into in the semiconductor body from the first main surface. The plurality of trenches pattern the semiconductor body into a plurality of mesas comprising a first mesa between a first trench and a second trench, and a second mesa between the second trench and a third trench. The semiconductor device may further include an electrode in the first trench that is one electrode out of an electrode group of a first gate electrode electrically coupled to a first gate driver output, a second gate electrode electrically coupled to a second gate driver output, and a source electrode electrically connected to a first load electrode. The semiconductor device may further include an electrode in the second trench that is another electrode out the electrode group. The semiconductor device may further include an electrode in the third trench that is a remaining electrode out of the electrode group. The semiconductor device may further include a barrier region of the first conductivity type having a higher doping concentration than the drift region and being arranged between the drift region and the body region in each of the first mesa and the second mesa. A first vertical distance from a bottom of the barrier region to the first main surface may greater than 60% of a second vertical distance from a bottom of the second trench to the first main surface. In some examples, the first vertical distance from a bottom of the barrier region to the first main surface may range from 60% to 150% of the second vertical distance, or from 60% to 120%, or from 60% to 90% of the second vertical distance.

The semiconductor device may be a vertical power semiconductor device having a load current flow between a first load terminal or load contact at the first main surface and a second load terminal or load contact at a second main surface opposite to the first main surface. The semiconductor device may be a vertical power semiconductor IGBT (insulated gate bipolar transistor), or a power semiconductor reverse conducting (RC) IGBT or a power semiconductor transistor such as a power semiconductor IGFET (insulated gate field effect transistor, e.g. a metal oxide semiconductor field effect transistor), or a power semiconductor diode. The vertical power semiconductor device may be configured to conduct currents of more than 1 A or more than 10 A or even more than 30 A and may be further configured to block voltages between load terminals, e.g. between emitter and collector of an IGBT, or between drain and source of a MOSFET in the range of several hundreds of up to several thousands of volts, e.g. 400 V, 650V, 1.2 kV, 1.7 kV, 3.3 kV, 4.5 kV, 5.5 kV, 6 kV, 6.5 kV. The blocking voltage may correspond to a voltage class specified in a datasheet of the power semiconductor device, for example.

The semiconductor body may include or consist of a semiconductor material from the group IV elemental semiconductors, IV-IV compound semiconductor material, III-V compound semiconductor material, or II-VI compound semiconductor material. Examples of semiconductor materials from the group IV elemental semiconductors include, inter alia, silicon (Si) and germanium (Ge). Examples of IV-IV compound semiconductor materials include, inter alia, silicon carbide (SiC) and silicon germanium (SiGe). Examples of III-V compound semiconductor material include, inter alia, gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), indium phosphide (InP), indium gallium nitride (InGaN) and indium gallium arsenide (InGaAs). Examples of II-VI compound semiconductor materials include, inter alia, cadmium telluride (CdTe), mercury-cadmium-telluride (CdHgTe), and cadmium magnesium telluride (CdMgTe). For example, the semiconductor body may be a magnetic Czochralski, MCZ, or a float zone (FZ) or an epitaxially deposited silicon semiconductor body.

The first main surface may be a level at an interface between the semiconductor body and a wiring area above the semiconductor body at a first side of the semiconductor body.

For example, each of the electrodes in the first to third trenches may be electrically insulated from a surrounding part of the semiconductor body, e.g. from a body or source region, by a dielectric in the corresponding one of the trenches. The dielectric may include one layer or a combination of layers, e.g. a layer stack of dielectric layers, for example oxide layers such as thermal oxide layers or deposited oxide layers, e.g. undoped silicate glass (USG), phosphosilicate glass (PSG), boron silicate glass (BSG), borophosphosilicate glass (BPSG), nitride layers, high-k dielectric layers or low-k dielectric layers. Each of the electrodes in the first to third trenches may include one electrode material or a combination of electrode materials, for example a doped semiconductor material (e.g. a highly doped semiconductor material) such as doped polycrystalline silicon, metal or metal compounds. Although the electrodes in the first to third trenches may be concurrently formed, the electrodes may differ from one another with respect to an electric connection, for example.

All or some parts of each of plurality of first, second and third trenches may be stripe-shaped, for example.

An impurity concentration in the drift region may gradually or in steps increase or decrease with increasing distance to the first main surface at least in portions of its vertical extension. According to other examples the impurity concentration in the drift region may be approximately uniform. For IGBTs based on silicon, a mean impurity concentration in the drift region may be between 2×1012cm−3and 1×1015cm−3, for example in a range from 5×1012cm−3to 1×1014cm−3. In the case of a semiconductor device based on SiC, a mean impurity concentration in the drift region may be between 5×1014cm−3and 1×1017cm−3, for example in a range from 1×1015cm−3to 2×1016cm−3. A vertical extension of the drift region may depend on voltage blocking requirements, e.g. a specified voltage class, of the vertical power semiconductor device. When operating the vertical power semiconductor device in voltage blocking mode, a space charge region may vertically extend partly or totally through the drift region depending on the blocking voltage applied to the vertical power semiconductor device. When operating the vertical power semiconductor device at or close to the specified maximum blocking voltage, the space charge region may reach or penetrate into a field stop region. The field stop region is configured to prevent the space charge region from further reaching to the cathode or collector at a second main surface of the semiconductor body opposite to the first main surface. In this manner, the drift or base region may be formed using desired low doping levels and with a desired thickness while achieving soft switching for the semiconductor device thus formed. For IGBTs, a carrier injection region, e.g. a p+-doped hole injection region for n-channel IGBTs, may be formed between the field stop region and a second load contact at the second main surface of the semiconductor body, for example.

By electrically connecting one of the electrodes, e.g. the first gate electrode, in the first to third trenches to a first gate driver output and another one of the electrodes, e.g. the second gate electrode, in the first to third trenches to a second gate driver output, a dual gate semiconductor device, e.g. a dual gate IGBT, can be provided. The dual gate semiconductor device may allow for switching the device between a conduction optimized state and a switching optimized state. In the conduction optimized state, a voltage applied to the second gate electrode, e.g. VG2, is above a certain threshold voltage. In the switching optimized state, the voltage applied to the second gate electrode, e.g. VG2, is below the certain threshold voltage Vth. Below the threshold voltage a hole inversion channel, i.e. p-channel, may be formed in n-type drift region devices in the mesa below the body region that adjoins to a sidewall of the trench including the second gate electrode. This channel may provide a low-ohmic path for the holes to leave the semiconductor body towards the emitter (source), i.e. the first load contact, and consequently reduces carrier confinement. Switching between VG2 with high carrier confinement, e.g. +15V, and VG2<threshold voltage Vth, e.g. VG2=−8V, or VG2=−10V, or VG2=−15V takes place shortly before the turn-off of the device, e.g. in a so-called desaturation phase.

By electrically connecting another one of the electrodes, the source electrode, to the first load electrode, in case of n-type drift region devices, a distance between the n-channel (carrying the load current) and the p-channel (for desaturation purposes) may be increased, thereby reducing a mutual interference between the n-channel and the p-channel in the desaturation phase. This may allow for improving the desaturation behavior as well as the stability of desaturation.

The barrier region may, e.g. for n-type drift region IGBTs, allow for decreasing a conductivity of the hole path during the desaturation phase and keep the hole current flow restricted next to the trench including the second gate electrode, i.e. away from the trench including the first gate electrode. This may as well allow for improving the desaturation behavior as well as the stability of desaturation.

In some examples, the electrode in the first trench may be the source electrode. The electrode in the second trench may be the first gate electrode, and the electrode in the third trench may be the second gate electrode. For example, only the first mesa out of the first mesa and the second mesa may include a source region adjoining to the second trench. For example, in the first mesa, a source region may adjoin to the second trench. For n-type drift region devices, the first gate electrode may be configured to control an electron channel at an interface between the first mesa and the second trench. Likewise, the second gate electrode may be configured to control a hole channel at an interface between the second mesa and the third trench. This may allow for separating the n-type, i.e. electron channel and the p-type, i.e. hole channel in the desaturation phase by the second trench, and consequently, may allow for reducing a mutual interference between the n-channel and the p-channel in the desaturation phase.

In some examples, the body region in the first mesa and the body region in the second mesa are electrically separated. For example, the body region in the first mesa may be electrically connected to the first load contact, e.g. source (emitter) contact, and the body region in the second mesa may be electrically floating. For example, a contact, e.g. contact plug on the second mesa may be omitted or may be electrically floating.

In some examples, the electrode in the first trench may be the first gate electrode, the electrode in the second trench may be the source electrode, and the electrode in the third trench may be the second gate electrode. For n-type drift region devices, the first gate electrode may be configured to control an electron channel at an interface between the first mesa and the first trench. Likewise, the second gate electrode may be configured to control a hole channel at an interface between the second mesa and the third trench. This may allow for separating the n-type, i.e. electron channel and the p-type, i.e. hole channel in the desaturation phase by the second trench, and consequently, and may allow for reducing a mutual interference between the n-channel and the p-channel in the desaturation phase.

In some examples, any source region in the first mesa adjoins to only the first trench out of the first and second trenches. Thereby, no source region may adjoin to the third trench including the second gate electrode. This may allow for adjusting a saturation current independent of a voltage of the second gate electrode in the third trench, for example.

In some examples, a source region in the second mesa may adjoin to the third trench. This may allow for modulating a saturation current depending on a voltage of the second gate electrode in the third trench, for example.

In some examples, any source region is absent in a part of the second mesa adjoining to the third trench. This may allow for adjusting a saturation current independent of a voltage of the second gate electrode in the third trench, for example, and may further allow for avoiding a combination of the p-channel between the second mesa and the third trench and an n-channel between the second mesa and the second trench, e.g. by omitting the n-channel in the second mesa due to the missing source region.

In some examples, a width of the first mesa at a vertical level corresponding to half of a vertical extension of the first mesa may be smaller than 1.2 μm. The width of the first mesa may even be smaller than 0.8 μm, or smaller than 0.4 μm.

In some examples, a ratio between i) a width of the first mesa at a vertical level corresponding to half of a vertical extension of the first mesa and ii) the vertical extension of the first mesa may be larger than 4. The ratio between a width of the first mesa and a vertical extension of the first mesa may even be larger than 6, or larger than 10, or larger than 14.

In some examples, a maximum doping concentration in the barrier region may be at least a factor of 100 higher than a maximum doping concentration in a part of the drift region adjoining to the barrier region. A vertical extension of the part of the drift region may be equal to a vertical extension of the barrier region. For example, the vertical extension of the barrier region may be equal to a vertical distance between the body region and the drift region, for example. In some other examples, a vertical extension of the part of the drift region may be equal to half of a vertical distance between the barrier region and the second main surface.

In some examples, a dose of first conductivity type dopants of the barrier region may be larger than 2×1013cm−2. The dose of first conductivity type dopants of the barrier region may even be larger than 4×1013cm−2, or larger than 8×1013cm−2. The dose of first conductivity type dopants may correspond to a number of implanted first conductivity type dopant ions per unit area (atoms/cm2). The dose may be determined by integrating a profile of the implanted first conductivity type dopant concentration along the vertical extension of the barrier region. The profile of first conductivity type dopants of the barrier region may be determined by one or more of depth profiling of dopants and contaminants using secondary ion mass spectrometry (classic dynamic SIMS and TOF (time of flight)-SIMS), spreading resistance profiling (SRP), or scanning probe techniques for 2D-profiling, for example.

In some examples, a vertical distance between a maximum doping concentration peak in the barrier region and the first main surface may range from 30% to 70% of the second vertical distance. A vertical distance between a maximum doping concentration peak in the barrier region and the first main surface may also range from 40% to 60% of the second vertical distance.

In some examples, the semiconductor device may further include a second electrode in the first trench, a second electrode in the second trench, and a second electrode in the third trench. In each of the first to third trenches, the electrode and the second electrode may face one another along a lateral direction and a dielectric may be arranged between the electrode and the second electrode. For example, the electrode and the second electrode in each of the first to third trenches may have a same or similar vertical extension and position. By arranging the dielectric between the electrode and the second electrode in the trenches, a lower feedback capacitance may be achieved. This may allow for lower turn-off switching losses Eoff, for example.

In some examples, the semiconductor device may include a transistor cell area and an edge termination area at least partly surrounding the transistor cell area at the first main surface. A percentage of trenches including the second gate electrode may be smaller in a first part of the transistor cell area than in a second part of the transistor cell area. The second part may be arranged between the first part and the edge termination area. The second part may also be arranged between the first part and a gate pad, or between the first part and a gate interconnection line, for example.

In some examples, the width of a channel configured to be controlled by the first gate electrode in one of the plurality of trenches differs from a width of a channel configured to be controlled by the second gate electrode in another one of the plurality of trenches. The width of a channel may correspond to a sum of lateral extensions of all source regions disposed along a longitudinal direction of the corresponding trench where the channel is formed, for example.

The examples and features described above and below may be combined.

Functional and structural details described with respect to the examples above shall likewise apply to the exemplary examples illustrated in the figures and described further below.

In the following, further examples of semiconductor devices are explained in connection with the accompanying drawings. Functional and structural details described with respect to the examples above shall likewise apply to the exemplary embodiments illustrated in the figures and described further below.

FIG.1Aschematically and exemplarily shows a section of a cross-sectional view of a semiconductor device100, andFIG.1Bis a schematic graph for illustrating exemplary doping concentration profiles along line AA ofFIG.1A.

The semiconductor device100includes an n-doped drift region102in a semiconductor body104having a first main surface106. A p-doped body region108is arranged between the drift region102and the first main surface106.

A plurality of trenches extends into in the semiconductor body104from the first main surface106. The plurality of trenches pattern the semiconductor body104into a plurality of mesas including a first mesa1101between a first trench1121and a second trench1122, and a second mesa1102between the second trench1122and a third trench1123. The trenches can have straight roughly sidewalls, tilted sidewalls or can be bulge shaped with a higher lateral width at the bottom part compared to the top part of more than 15%, or more than 30%, or even more than 50%.

An electrode in the first trench1141is one electrode out of an electrode group of a first gate electrode electrically coupled to a first gate driver output (not illustrated inFIG.1A), a second gate electrode electrically coupled to a second gate driver output (not illustrated inFIG.1A), and a source electrode electrically connected to a first load contact1151. An electrode in the second trench1142is another electrode out the electrode group, and an electrode in the third trench1143is a remaining electrode out of the electrode group. The electrodes in the electrode group may be assigned to the first, second and third trenches according to various combinations or permutations. Depending on the specific combination, source region(s) may be arranged in the first and/or second mesa1101,1102(not illustrated inFIG.1A). Dielectrics1171,1172,1173in the first to third trenches1121,1122,1123electrically insulate the electrode in the first to third trenches1141,1142,1143from a surrounding part of the semiconductor body104.

An n-doped barrier region116having a higher doping concentration than the drift region102is arranged between the drift region102and the body region108in each of the first mesa1101and the second mesa1102. A first vertical distance d1from a bottom of the barrier region116to the first main surface106is greater than 60% of a second vertical distance d2from a bottom of the second trench1122to the first main surface106.

The semiconductor device100may be a vertical power semiconductor device. In a vertical semiconductor device, a load current may flow along a vertical direction y between a first load contact1151at the first surface106and a second load contact1152at a second surface opposite to the first surface106, for example. The first load contact1151may be an emitter (source) terminal of an IGBT or reverse conducting (RC) IGBT, for example. In case of IGBTs, an n-doped field stop region may be arranged between the drift region102and the second load contact1152, and a p+-doped collector region or hole injection region may be arranged between the field stop region and the second load contact1152and may further be electrically connected to the second load contact1152.

The first load contact1151may include or consist of a conductive material or a combination of conductive materials, for example a doped semiconductor material (e.g., a degenerate doped semiconductor material) such as doped polycrystalline silicon, metal or metal compound, for example. The first load contact1151may also include a combination of these materials, e.g. a liner or adhesion material and an electrode material. Exemplary contact materials include one or more of titanium nitride (TiN) and tungsten (W), aluminum (Al), copper (Cu), alloys of aluminum or copper, for example AlSi, AlCu or AlSiCu, nickel (Ni), titanium (Ti), tungsten (W), tantalum (Ta), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), for example. The first load contact1151may constitute or be part of a wiring area formed over the semiconductor body104. The wiring area may include one, two, three or even more wiring levels that may include patterned or non-patterned metal layers and interlayer dielectrics arranged between the patterned or non-patterned metal layers. Vias may electrically interconnect the different wiring levels, for example. A groove contact118electrically connects the semiconductor body104, e.g. the body region108, and the first load contact1151. As an alternative or in addition to a groove contact, a planar contact may be formed (not illustrated). An interlayer dielectric120is arranged between the first load contact1151and the first main surface106. Details for the first load contact1152likewise apply to the second load contact1152.

A ratio between a width w of the first mesa1101(or second mesa1102) at the first main surface106and a vertical extension d of the first mesa1101is larger than 4. For example, the width of the first mesa1101at the first main surface106may be smaller than 1.2 μm.

Exemplary profiles of doping concentrations c1, c2are illustrated in the schematic graph ofFIG.1Bthat is taken along the vertical direction y of line AA′ ofFIG.1A. The profiles of doping concentrations c1, c2extend across the body region108and the barrier region116. A vertical distance dv between a maximum doping concentration peak P1, P2in the barrier region116and the first main surface106ranges from 30% to 70% of the second vertical distance d2.

A dose of n-type dopants of the barrier region116may be determined by integrating the concentrations c1, c2along the vertical extension of the barrier region116, for example. For example, the dose may be larger than 2×1013cm−2.

Referring to the exemplary IGBT101in the schematic cross-sectional view ofFIG.2, the electrode in the first trench1141is a source electrode electrically coupled to the first load contact1151. The electrode in the second trench1142is a first gate electrode electrically coupled to a first gate driver output G1. The electrode in the third trench1143is a second gate electrode electrically coupled to a second gate driver output G2. The first mesa1101includes a source region122adjoining to the second trench1122. The electrode in the second trench1142is configured to control an electron channel at an interface124between the body region108in the first mesa1101and the second trench1122. Likewise, the electrode in the third trench1143may be configured to control a hole channel at an interface126between the second mesa1102and the third trench1123. This may allow for separating the n-type, i.e. electron channel and the p-type, i.e. hole channel in the desaturation phase by the second trench1142, thereby allowing for reducing a mutual interference between the n-channel and the p-channel in the desaturation phase.

The IGBT101further includes an n-doped field stop region128between the drift region102and the second load contact1152, and further includes a p-doped collector region or hole injection region130between the field stop region128and the second load contact1152.

The exemplary IGBT101in the schematic cross-sectional view ofFIG.3is similar to the IGBT101inFIG.2except that the body region108in the second mesa1102is electrically separated from the body region108in the first mesa1101. The body region108in the second mesa1102is electrically floating by omitting an electric contact between the first load contact1151and the body region108. A p-channel for supporting the desaturation phase can be controlled by the electrode in the third trench1123at an interface127between the body region108in a third mesa1103and the third trench1123.

The exemplary IGBT101in the schematic cross-sectional view ofFIG.4Ais similar to the IGBT101inFIG.2except that a further source region122is arranged in the second mesa1102that adjoins to the third trench1123but not to the second trench1122. Alternatively to several groove contacts contacting the mesa and the electrode in the trench separately (mentioned above), a shared groove contact1181may connect a mesa and the electrode in a trench adjoining the mesa (seeFIG.4B). A shared groove contact1182may also connect mesas and the electrode in a trench between the mesas (seeFIG.4C).

Another exemplary IGBT101is illustrated in the schematic cross-sectional view ofFIG.5. The electrode in the first trench1141is a first gate electrode electrically coupled to a first gate driver output G1. The electrode in the second trench1142is a source electrode electrically coupled to the first load contact1151. The electrode in the third trench1143is a second gate electrode electrically coupled to a second gate driver output G2. The first mesa1101includes a source region122adjoining to the first trench1121. The electrode in the first trench1141is configured to control an electron channel at an interface123between the body region108in the first mesa1101and the first trench1121. Likewise, the electrode in the third trench1143may be configured to control a hole channel at an interface126between the second mesa1102and the third trench1123. This may allow for separating the n-type, i.e. electron channel and the p-type, i.e. hole channel in the desaturation phase by the second trench1142, thereby allowing for reducing a mutual interference between the n-channel and the p-channel in the desaturation phase.

The exemplary IGBT101in the schematic cross-sectional view ofFIG.6is similar to the IGBT101inFIG.5except that the body region108in the second mesa1102is electrically separated from the body region108in the first mesa1101. The body region108in the second mesa1102is electrically floating by omitting an electric contact between the first load contact1151and the body region108. A p-channel at an interface127between the body region108in a third mesa1103and the third trench1123can be controlled by the electrode in the third trench1123for supporting the desaturation phase.

The exemplary IGBT101in the schematic cross-sectional view ofFIG.7is similar to the IGBT101inFIG.5except that a further source region122is arranged in the second mesa1102that adjoins to the third trench1123.

The IGBT designs illustrated inFIGS.5to7may be modified by arranging more than one second trench1122including the source electrode between the first and third trenches1121,1123. The exemplary IGBT101in the schematic cross-sectional view ofFIG.8illustrates two second trenches1122between the first and third trenches1121,1123. InFIG.8, a fourth mesa region1104between the second trenches1122is electrically connected to the first load electrode1151. The exemplary IGBT101illustrated inFIG.9is similar to the IGBT101inFIG.8except that the body region108in the first mesa1101is electrically separated from the body region108in the fourth mesa1104.

The schematic cross-sectional view ofFIG.10illustrates fourth trenches1124that may be arranged between different groups of first to third trenches1121,1122,1123, for example. The view ofFIG.10merely illustrates the arrangement of the trenches without providing details with respect to semiconductor regions or contact schemes. Each of the fourth trenches1124includes an electrode in the fourth trench1144and a dielectric1174. By altering a number of the fourth trenches1124between different groups of first to third trenches1121,1122,1123, a lateral extension wl of the sequence of fourth trenches1124may be varied. For example, the lateral extension wl may be smaller than 20%, or smaller than 15%, or smaller than 10% of a thickness, i.e. vertical extension, of the semiconductor body104. This may allow for adjusting charge carrier accumulation, e.g. a charge carrier plasma in an on-state, capacitances, e.g. input and output capacitances, and a gate charge, for example. The electrodes in the fourth trenches1144may be electrically coupled to a first load contact L1, or to the first or second gate driver output G1, G2. When electrically coupling the electrodes in the fourth trenches1144to the first or second gate driver output G1, G2, mesa regions adjoining to the corresponding fourth trenches1144may not be electrically contacted, e.g. be electrically floating and/or may not include any source regions. This may allow for avoiding injection of electrons toward the collector in an on-state of the device.

The schematic cross-sectional view ofFIG.11illustrates an exemplary IGBT101including a third trench1123having an electrode1143electrically coupled to the first gate driver output G1. The third trench1123is arranged between second trenches1122, wherein an electrode1142in each of the second trenches1122is electrically coupled to a first load contact terminal L1, e.g. a source or emitter terminal. The second trenches1122and the third trench1123are arranged between the first trenches1121, wherein an electrode1141in each of the first trenches1121is electrically coupled to the second gate driver output G2. This may allow for further improving the desaturation mechanism.

The exemplary IGBTs101illustrated in the schematic cross-sectional views ofFIGS.12A to12Ceach include a second electrode in the first to third trenches. The second electrode in the first to third trenches is also electrically coupled to one of the first gate driver output G1, the second gate driver output G2and the first load contact1151. The schematic views ofFIGS.12A to12Cillustrate a second electrode in the first trench11412and a second electrode in the second trench11422.

A variety of combinations and electrode permutations may be achieved by electrically connecting the two electrodes in the first to third trenches1141,1142,1143to same or different electrodes of the electrode group. In each of the first to third trenches1141,1142,1143, the electrode and the second electrode face one another along a lateral direction and a dielectric is arranged between the electrode and the second electrode (see e.g. the dielectric1172between the electrode in the second trench1142and the second electrode in the second trench11422).

The schematic plan view ofFIG.13illustrates an exemplary semiconductor device100including a transistor cell area132and an edge termination area134at least partly surrounding the transistor cell area132at the first main surface. A percentage of trenches including the second gate electrode is smaller in a first part1321of the transistor cell area132than in a second part1322of the transistor cell area132, wherein the second part1322is arranged between the first part1321and the edge termination area134. The trenches in the transistor cell area132may extend in parallel along a first lateral direction xl.

The schematic plan view ofFIG.14Aillustrates an exemplary semiconductor device100having a width of a channel configured to be controlled by the second gate electrode G2in the second part1322that is larger than in the first part1321. This may allow for increasing a load current density in the second part1322compared with the first part1321, for example. The examples illustrated inFIGS.13and14Amay allow for homogenizing energy dissipation across an active area, e.g. a transistor cell area, of the device, for example. Moreover, a width of a channel configured to be controlled by the first gate electrode G1in the second part1322may also be larger than in the first part1321. This may allow for lowering the current density in the second part1322during switching, and may allow for improving robustness during switching. For example, a lateral extension wt of the second part1322be larger than 10% of a thickness of the semiconductor body, or larger than 20% of a thickness of the semiconductor body, or even larger than 30% of a thickness of the semiconductor body. The second part1322may cover between 20% and 70%, or between 30% and 60%, or between 40% and 60% of the active area of the device100, for example. Referring to the schematic top view ofFIG.14B, the second part1322may also be divided into several sub-parts13221,13222, wherein the sub-parts13221,13222may differ from one another with respect to one or more characteristic, for example.

The aspects and features mentioned and described together with one or more of the previously described examples and figures, may as well be combined with one or more of the other examples in order to replace a like feature of the other example or in order to additionally introduce the feature to the other example.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.