Patent ID: 12245418

DETAILED DESCRIPTION OF THE EMBODIMENTS

Numerous different embodiments or examples are provided in the description of the disclosure below to implement different features of the subject matter set forth herein. Specific examples of elements, arrangements and configurations are provided in the description below to simplify the present disclosure. It should be noted that the description is merely illustrative of and is not restrictive of the present disclosure. For example, in the description below, a first feature formed on/over or above a second feature may also include an embodiment in which the first feature and the second feature are formed in a direct contact manner, and may include an embodiment in which an additional feature is formed between the first feature and the second feature in a way that the first feature and the second feature may not be in direct contact with each other. Moreover, numerals and/or symbols may be repeatedly used for elements in the various embodiments of the present disclosure. Such repetition is intended for simplicity and clarity, and does not determine or represent relations between the embodiments and/or configurations discussed herein.

Moreover, for the sake for better description, relative spatial terms such as “under”, “below”, “lower”, “above” and “upper” may be used to describe a relation between one element or feature and another element or feature shown in the drawings. In addition to the orientations depicted in the drawings, these relative spatial terms are also intended to comprise different orientations of an apparatus in use or in operation. The apparatus may be configured in other orientations (for example, rotated by 90 degrees or oriented otherwise), and the relative spatial terms may be interpreted correspondingly and similarly.

Although numerical ranges and parameters in broader ranges defined in the present disclosure are all approximate values, related values in the specific embodiments are presented as precisely as possible herein. However, any value intrinsically and inevitably contains a standard deviation as a result of individual testing methods. Thus, unless otherwise specified, the numerical parameters set forth in the present disclosure and the appended claims may be approximate values variable according to requirements. These numerical parameters should be at least understood as the numbers of significant digits specified and values obtained by applying an ordinary rounding method. Herein, a numerical range is represented as from one endpoint to another endpoint, or between two endpoints. Unless otherwise specified, all numerical ranges disclosed herein are inclusive of endpoints.

FIG.1shows a schematic diagram of a semiconductor structure100according to an embodiment of the present disclosure. The semiconductor structure100may include a substrate110, a logic element120and a memory element130. The substrate110has a first region110A and a second region110B, and the first region110A is laterally adjacent to the second region110B. The logic element120may be disposed in the first region110A of the substrate110, and the memory element130may be disposed in the second region110B of the substrate110. In the present embodiment, the logic element120located in the first region110A may include, for example, multiple transistors, and is operable to perform a data write operation or a data read operation upon a memory cell of the memory element130in the second region110B.

In some embodiments, the substrate110may include a semiconductor material, for example, silicon (Si), germanium (Ge), gallium (Ga), any combination of the above, semiconductor on diamond (SOD), silicon on insulator (SOI) or silicon on sapphire (SOS).

In the present embodiment, each transistor in the logic element120may include, for example, a complementary metal-oxide-semiconductor field-effect transistor (MOSFET); however, the present disclosure is not limited to the example above. In some other embodiments, the logic element120may also include a multi-bridge channel FET (MBCFET), a stacked nano-sheet FET, a fin FET (FINFET), a gate-all-around FET (GAAFET) or other types of FET. Moreover, each transistor in the logic element120may be an enhancement mode transistor or a depletion mode transistor. In some embodiments, by effective use of enhancement-mode transistors and depletion-mode transistors, a basic logic gate (for example, a NAND gate or a NOR gate) can be implemented by a smaller number of transistors, thereby reducing components needed by an overall circuit.

In the present embodiment, the memory element130may include a memory cell of a dynamic random-access memory (DRAM); however, the present disclosure is not limited to the example above. In some embodiments, the memory element130may include a memory cell of an electrically-erasable programmable read-only memory (EEPROM), a ferroelectric memory or other types of memory.

Since the manufacturing process of the logic element120and is compatible with the manufacturing process of the memory element130in the semiconductor structure100, they can be fabricated on the same substrate110, such that the logic element120can access the memory element130nearby so as to increase the memory access speed. Moreover, in some embodiments of the present disclosure, each memory element130can be controlled and accessed by one single adjacent transistor. Thus, the number of transistors needed is reduced, thereby further increasing the computing speed. Compared with the prior art in which a memory element and a logic element are separately fabricated on different dies and are then packaged via an interposer (such as silicon) by means of 2.5D or 3D, the logic element120and the memory element130of the semiconductor structure100of the present disclosure can be fabricated on the same wafer substrate, hence achieving better heat dissipation efficiency and operation performance. The semiconductor structure100provided by the embodiments of the present disclosure is applicable to attach a memory cell in a logic circuit or to attach a logic unit in a memory circuit, thereby enhancing performance of various circuits.

In some embodiments, the memory element130may include a decoding circuit having bit lines and word lines; however, the present disclosure is not limited to the example above. In some embodiments, the memory element130may further include logic circuits for executing computation. In other words, both of the logic circuit and the memory circuit can be fabricated on the substrate of a same chip (for example, forming a computing-in-memory (CIM) structure in a memory chip), hence alleviating the issue of “memory wall” in the prior art.

In the semiconductor structure100, the logic element120may include multiple transistors, and the memory element130may include multiple capacitors. However, in the present embodiment, to better understand the details of the present disclosure, only one FET in the logic element120and one capacitor in the memory element130adjacent to the FET are depicted inFIG.1.

As shown inFIG.1, the substrate110may include a wafer layer112, an epitaxial layer114, and a P-well PW1and an N-well NW1formed in the epitaxial layer114. In the present embodiment, the logic element120may include an NMOSEFT disposed in the P-well PW1, and the memory element130may include a capacitor disposed on the N-well NW1. The P-well PW1of the logic element120includes N-type heavily doped regions121A and121B, which can respectively be-adopted as the source and the drain of a transistor. In the present embodiment, in the P-well PW1, N-type lightly doped regions122A and122B may be disposed between the N-type heavily doped regions121A and121B and adjacent to the N-type heavily doped regions121A and121B, so as to enhance conduction efficiency and reliability of transistors. Moreover, in the present embodiment, in the P-well PW1, an indium gallium zinc oxide (IGZO) channel123may be disposed between the N-type lightly doped regions122A and122B, and may be doped with a trivalent element, calcium (Ca), magnesium (Mg) or copper (Cu), so as to adjust a threshold voltage of transistors; however, the present disclosure is not limited to the examples above. In some embodiments, the channel123may be formed by silicon-germanium material, for example, Si(1-x)Gex, where 0≤x≤0.5.

In addition, the logic element120may further include a gate structure124disposed on the channel123. In some embodiments, the gate structure124may include a high-k dielectric layer1241and a polycrystalline silicon layer1242, wherein the high-k dielectric layer1241is made of a material such as, for example but not limited to, hafnium oxide (HfO2). Moreover, as shown inFIG.1, on the substrate110, the semiconductor structure100may further include a dielectric layer126disposed on the substrate110, wherein the dielectric layer126may cover the logic element120. In some embodiments, the dielectric layer126may include, for example, silicate glass, for example but not limited to, phosphosilicate glass or borophosphosilicate glass.

In the present embodiment, the logic element120may further include conductive plugs125A,125B and125C passing through the dielectric layer126. The conductive plugs125A,125B and125C are respectively in contact with the N-type heavily doped region121A (that is, the source of the transistor), the N-type heavily doped region121B (that is, the drain of the transistor), and the gate structure124. In some embodiments, multiple metal line layers (not depicted inFIG.1) may further be disposed on the logic element120, and the source, the drain and the gate of the transistor in the logic element120are electrically connected to lines in the metal line layers via the conductive plugs125A,125B and125C.

In the present embodiment, the conductive plugs125A,125B and125C may have a multi-layer structure. For example, the conductive plug125A may include a barrier layer1251, a copper-phosphorus alloy layer1252and an electrode metal layer1253. The barrier layer1251and the copper-phosphorus alloy layer1252may be formed along a contour of a recess of the dielectric layer126, and the electrode metal layer1253may fill a recess of the copper-phosphorus alloy layer1252, such that the copper-phosphorus alloy layer1252is sandwiched between the electrode metal layer1253and the barrier layer1251. In some embodiments, for example, the barrier layer1251may include titanium nitride (TiN), and the electrode metal layer1253may include Cu, tungsten (W), cobalt (Co), or ruthenium (Rh).

InFIG.1, the memory element130may include a lower electrode132, an upper electrode133, and dielectric layers134and135disposed between the lower electrode132and the upper electrode133. The lower electrode132may be disposed above the substrate110, and the upper electrode133may be disposed above the substrate110and the lower electrode132. In the present embodiment, the memory element130may include, for example, a memory cell of a DRAM, and the upper electrode133, the lower electrode132and dielectric materials therein (including the dielectric layers134and135) may form a capacitor for storing electric charge. In some embodiments, the dielectric layers134and135may have high dielectric constants (k), and be made of materials such as hafnium oxide (HfO2).

As shown inFIG.1, the memory element130may be disposed in the second region110B of the substrate110and on the drain of the transistor of the logic element120, and the upper electrode133of the memory element130may cover the conductive plug125B along a vertical direction (for example, the Z direction). In other words, the upper electrode133of the memory element130may be electrically connected to the drain (that is, the N-type heavily doped region121B) of the transistor of the logic element120.

Moreover, in the present embodiment, the lower electrode132may include a metal layer1321, a copper-phosphorus alloy layer1322and a barrier layer1323. The copper-phosphorus alloy layer1322may extend along a contour of the metal layer1321to surround the metal layer1321, and the barrier layer1323may also surround the copper-phosphorus alloy layer1322along a contour of the copper-phosphorus alloy layer1322.FIG.2shows a partial enlarged schematic diagram of the barrier layer1323, the copper-phosphorus alloy layer1322and the metal layer1321located in the region B inFIG.1according to an embodiment of the present disclosure. As shown inFIG.2, due to properties of copper-phosphorus alloy, a surface of the copper-phosphorus alloy layer1322has needle-like structures, so that a surface area of the lower electrode132can be increased, thereby increasing a capacitance value of a capacitor formed by the upper electrode133and the lower electrode132. Similarly, the upper electrode133may include a metal layer1331, a copper-phosphorus alloy layer1332and a barrier layer1333. The copper-phosphorus alloy layer1332may extend along a contour of the metal layer1331to surround the metal layer1331, and the barrier layer1333may also surround the copper-phosphorus alloy layer1332along a contour of the copper-phosphorus alloy layer1332.

In the present embodiment, in the second region110B of the substrate110, a shallow trench isolation structure138made of a material including undoped silicate glass (USG) may be further formed in the N-well NW1. As such, the lower electrode132can be isolated from the N-well NW1of the substrate110by the shallow trench isolation structure138.

As shown inFIG.1, the metal layer1321may have a comb-like structure including multiple protrusions1321A, and the metal layer1331may also have a comb-like structure including multiple protrusions1331A. The protrusions1321A extend toward the upper electrode133, the protrusions1331A extend toward the lower electrode132, and the multiple protrusions1321A and the multiple protrusions1331A may interlace each other. With the design of such interlacing comb-like structures, an effective overlapping surface area between the metal layer1321and the metal layer1331can be increased, thereby increasing a capacitance value of the memory element130. In some embodiments, the multiple protrusions1321A may be arranged in an array, and the multiple protrusions1331A may also be arranged in an array; however, the present disclosure is not limited to the examples above.

InFIG.1, the substrate110may include the first region110A in which the logic element120is to be formed, and the second region110B in which the memory element130is to be formed. As shown inFIG.1, the N-type heavily doped regions121A and121B may be disposed in the P-well PW1in the first region110A, the N-type lightly doped regions122A and122B may be disposed between the N-type heavily doped regions121A and121B and adjacent to the N-type heavily doped regions121A and121B, and the IGZO channel123may be disposed between the N-type lightly doped regions122A and122B. In some embodiments, the channel123may be silicon-germanium channel that include silicon-germanium material.

Moreover, in the semiconductor structure100, the memory element130may be formed in the second region110B in which a P-type transistor is generally to be formed. More specifically, the shallow trench isolation structure138may be formed in the N-well NW1, and the lower electrode132may be formed on the shallow trench isolation structure138. In the present embodiment, the shallow trench isolation structure138may be, for example, USG.

InFIG.1, the gate structure124may be formed on the channel123. After the gate structure124is formed, at least one dielectric layer126may be further formed, wherein the dielectric layer126may include, for example, silicate glass. Moreover, the gate structure124may include the high-k dielectric layer1241and the polycrystalline silicon layer1242. In some embodiments, the high-k dielectric layer1241may include HfO2, may be fabricated by means of atomic layer deposition (ALD) to enhance its reliability, and may have a thickness between, for example, 5 nm and 10 nm; however, the present disclosure is not limited to the examples above. In some embodiments, the high-k dielectric layer1241may also include a two-layer stacked structure of zirconium dioxide (ZrO2) and HfO2.

InFIG.1, the dielectric layer126on the N-type heavily doped regions121A and121B and on the gate structure124(that is, on the source, drain and gate of the transistor) may be formed to have an opening, and the dielectric layer126in the second region110B may be formed to have a deep trench structure (a larger opening). In such case, by means of a lift-off process, the barrier layer1251and the copper-phosphorus alloy layer1252are sequentially deposited in the openings of the dielectric layer126in the first region110A, and the barrier layer1323and the copper-phosphorus alloy layer1322are sequentially deposited in the deep trench of the dielectric layer126in the second region110B.

Next, the electrode metal layer1253may be continuously filled into the openings of the dielectric layer126in the first region110A, so as to form an electrode connected to the source, the drain and the gate of the transistor. In the present embodiment, the electrode metal layer1253may include, for example, Cu, W, Co or Rh. Moreover, the metal layer1321may also be formed on the barrier layer1323and the copper-phosphorus alloy layer1322in the second region110B, and the metal layer1321may be partially removed by means of lithography and lift-off processes such that the metal layer1321may have the multiple protrusions1321A. In some embodiments, the metal layer1321may be made of a material such as Cu, W, Co or Rh, and may be fabricated in the same manufacturing process as the electrode metal layer1253. Thus, the capacitor manufacturing process of the memory element130is compatible with the transistor manufacturing process of the logic element120. In the present embodiment, the copper-phosphorus alloy layer1322and the barrier layer1323may be sequentially formed on the metal layer1321, such that the copper-phosphorus alloy layer1322and the barrier layer1323can extend along the contour of the metal layer1321and completely protect the metal layer1321. In some embodiments, a copper-phosphorus alloy layer and a barrier layer (not depicted) may be further formed above the electrode metal layer1253.

FIG.3shows a cross-sectional diagram of the semiconductor structure100inFIG.1by cutting along the section line A1-A1′ inFIG.1.

In the embodiment inFIG.3, the multiple protrusions1321A may be arranged in an array to thereby increase the surface area of the lower electrode132; however, the present disclosure is not limited to the example above.

InFIG.1, the dielectric layer134may be formed in recesses between the protrusions1321A so as to fill the recesses. In some embodiments, the dielectric layer134may be formed by depositing HfO2by means of ALD. Since the dielectric constant of HfO2may get as high as 26 to 30, compared with a memory element using a conventional material, the memory element130can achieve a higher capacitance value within the same area. Moreover, the dielectric layer134having a high dielectric constant formed by means of ALD can improve reliability and help in reducing capacitance leakage, hence further enhancing the performance of the memory element130.

The dielectric layer135may be formed by means of a lithography process on the protrusions1321A, and may be made of a material the same as that of the dielectric layer134. Next, the upper electrode133(including the barrier layer1333, the copper-phosphorus alloy layer1332and the metal layer1331) may be formed on the dielectric layers134and135. As such, the protrusions1331A of the metal layer1331are interlaced with the protrusions1321A of the lower electrode132.

With the interlacing protrusions1321A and1331A present on the metal layer1321of the lower electrode132and the metal layer1331of the upper electrode133, an effective overlapping surface area between the lower electrode132and the upper electrode133can be increased. As such, compared with a conventional structure, the memory element130of the present disclosure can increase the capacitance value of a capacitor within the same base area, thereby increasing the memory density and capacity within unit base area of the semiconductor structure100. Moreover, since the transistor in the logic element120may be electrically connected to the capacitor in the adjacent memory element130, parasitic capacitance of bit lines can also be more readily decreased to reduce heat and power loss generated during charging/discharging of the capacitor.

FIG.4shows a schematic diagram of a semiconductor structure300according to an embodiment of the present disclosure. The semiconductor structure300differs from the semiconductor structure100in that, a memory element330in the semiconductor structure300may include a memory cell of an EEPROM. However, the structure of the memory cell is different from a floating gate of silicon-oxide-nitride-oxide-silicon (SONOS) used by a common EEPROM. In the present embodiment, in the memory cell of the memory element330, a copper-phosphorus alloy layer having multiple protruding structures may be added to the floating gate to reinforce an electric field for write operations and erase operations, so that operations of the memory element330can be more efficient. Moreover, similar to the semiconductor structure100, manufacturing processes of a logic element320and the memory element330in the semiconductor structure300may also be compatible with each other, and the two can thus be fabricated by the same manufacturing process on the same wafer substrate.

The semiconductor structure300includes a substrate310, the logic element320and the memory element330. The substrate310has a first region310A, and a second region310B laterally adjacent to the first region310A. The logic element320may be disposed in the first region310A of the substrate310, and the memory element330may be disposed in the second region310B of the substrate310.

In the present embodiment, the substrate310may include a wafer layer312, an epitaxial layer314, and P-wells PW1and PW2and an N-well NW1that are formed in the epitaxial layer314. The logic element320may include multiple transistors. For example, as shown inFIG.4, the logic element320may include an N-type transistor MIN and a P-type transistor MIP. The N-type transistor MIN may include the P-well PW1, N-type heavily doped regions321A and321B, a gate structure324A, and conductive plugs325A and325B. The P-type transistor MIP may include the N-well NW1, P-type heavily doped regions321C and321D, a gate structure324B, and conductive plugs325C and325D.

The N-type heavily doped regions321A and321B are disposed on two opposite sides of the P-well PW1, and may respectively serve as the source and the drain of the transistor MIN. In the present embodiment, to enhance the reliability of the N-type transistor MIN, the transistor MIN may further include N-type lightly doped regions322A and322B disposed between the N-type heavily doped regions321A and321B and adjacent to the N-type heavily doped regions321A and321B. The gate structure324A of the transistor MIN may be disposed on the P-well PW1, and be between the N-type heavily doped region321A and the N-type heavily doped region321B. The gate structure324A includes an oxide layer3244(for example, a silicon dioxide (SiO2) layer formed by means of ALD), a polycrystalline silicon layer3245, a barrier layer3241(for example, including TiN), a copper-phosphorus alloy layer3242and an electrode metal layer3243(for example, including Cu, W, Co, or Rh). The conductive plugs325A and325B may pass through a SiO2layer342and a silicate glass layer344(for example, phosphosilicate glass or borophosphosilicate glass) formed on the substrate310, and be electrically connected to the source and the drain (that is, the N-type heavily doped regions321A and321B) of the transistor MIN. In the present embodiment, the conductive plugs325A and325B may also have a multi-layer structure. For example, the conductive plug325A may include a barrier layer3251(for example, TiN), a copper-phosphorus alloy layer3252and an electrode metal layer3253(for example, including Cu, W, Co or Rh).

The P-type transistor MIP may include the N-well NW1, the P-type heavily doped regions321C and321D, the gate structure324B, and the conductive plugs325C and325D. The P-type heavily doped regions321C and321D are disposed on two opposite sides of the N-well NW1, and may respectively serve as the source and the drain of the transistor MIP. In the present embodiment, to enhance the reliability of the P-type transistor MIP, the transistor MIP may further include P-type lightly doped regions322C and322D disposed between the P-type heavily doped regions321C and321D and adjacent to the P-type heavily doped regions321C and321D. The gate structure324B of the transistor MIP may be disposed on the N-well NW1, and be between the P-type heavily doped region321C and the P-type heavily doped region321D. The gate structure324B may have a multi-layer structure the same as that of the gate structure324A, and the conductive plugs325C and325D may also have a multi-layer structure the same as that of the conductive plugs325A and325B. Moreover, the conductive plugs325C and325D may pass through the SiO2layer342and the silicate glass layer344on the substrate310, and be electrically connected to the source and the drain (that is, the P-type heavily doped regions321C and321D) of the transistor M1P.

The memory element330may include a source334A, a drain334B, an oxide layer331, copper-phosphorus alloy layers333and337(having needle-like structures arranged in an array) capable of quickly attracting or releasing electrons, a charge storage layer338, an oxide layer336, a control gate332and conductive plugs339A and339B. In the present embodiment, the memory element330may be disposed in the P-well PW2, and the source334A and the drain334B may be disposed in N-type heavily doped regions in the P-well PW2. Moreover, as shown inFIG.4, the memory element330may further include N-type lightly doped regions335A and335B disposed between the source334A and the drain334B and adjacent to the source334A and the drain334B.

The oxide layer331may be disposed on the substrate310between the source334A and the drain334B. In some embodiments, the oxide layer331may include SiO2, and may be formed by means of ALD. In such case, the oxide layer331can have higher reliability, and thus can help in preventing electric charge from escaping from the charge storage layer338. Moreover, the oxide layer331formed by means of ALD can have a smaller thickness, and can thus further reduce an operating voltage needed for read operations and write operations performed by the memory element330.

As shown inFIG.4, the copper-phosphorus alloy layer333may be disposed on the oxide layer331, the charge storage layer338may be disposed on the copper-phosphorus alloy layer333and the oxide layer331, and the copper-phosphorus alloy layer337may be disposed on the charge storage layer338. In other words, the copper-phosphorus alloy layers333and337(having needle-like structures arranged in an array) capable of quickly attracting or releasing electrons may be disposed above and below the charge storage layer338, respectively. Moreover, the oxide layer336may be disposed on the charge storage layer338and the copper-phosphorus alloy layer337. In such case, the copper-phosphorus alloy layer333is sandwiched between the oxide layer331and the charge storage layer338, and the copper-phosphorus alloy layer337is sandwiched between the oxide layer336and the charge storage layer338. In some embodiments, the oxide layer331may be referred to a first oxide layer, the oxide layer336may be referred to a second oxide layer, the copper-phosphorus alloy layer333may be referred to a first copper-phosphorus alloy layer, and the copper-phosphorus alloy layer337may be referred to a second copper-phosphorus alloy layer; however, the present disclosure is not limited to the examples above.

In the present embodiment, the copper-phosphorus alloy layer333has multiple protruding structures facing the copper-phosphorus alloy layer337, and the copper-phosphorus alloy layer337has multiple protruding structures facing the copper-phosphorus alloy layer333.FIG.5shows a top view of the copper-phosphorus alloy layer333obtained from cutting along the section line A2-A2′ inFIG.4.

In the present embodiment, after the oxide layer331(for example, SiO2having a thickness between 1 nm and 2 nm) is formed between the source334A and the drain334B on the substrate310by means of ALD, a layer of SiN may be deposited on the oxide layer331, as the charge storage layer338. Then, an array of needle-like holes may be formed in the SiN layer by means of a lithography process, and the copper-phosphorus alloy layer333is formed in the holes of the SiN layer by means of a lift-off process. In some embodiments, before the copper-phosphorus alloy layer333is formed, a barrier layer (not depicted) may be first filled into the holes to prevent diffusion and contamination of metal. In some embodiments, the barrier layer may be made of a material such as TiN.

After the copper-phosphorus alloy layer333is formed, another layer of SiN is deposited on the copper-phosphorus alloy layer333and the original SiN layer, and the two upper and lower SiN layers sequentially formed then become the charge storage layer338. Next, multiple holes are formed in the newly formed SiN layer, and then the copper-phosphorus alloy layer337is formed in the holes of the SiN layer by means of a lift-off process. In the present embodiment, the protruding structures of the copper-phosphorus alloy layer333and the protruding structures of the copper-phosphorus alloy layer337may interlace each other. For example, the respective protruding structures of the copper-phosphorus alloy layer333and the copper-phosphorus alloy layer337may not overlap in the X-axis direction. In the present embodiment, the protruding structures of the copper-phosphorus alloy layer333and the copper-phosphorus alloy layer337have smaller radiuses of curvature, which helps in reinforcing electric fields for capturing or releasing electrons, thereby respectively enhancing efficiency of write operations and erase operations for the EEPROM (i.e., the memory element330).

In the embodiments above, the charge storage layer338may include, for example, SiN; however, the present disclosure is not limited to the example above. In some embodiments, the charge storage layer338may include SiN, hafnium aluminum oxide (HaAlO), HfO2, aluminum oxide (Al2O3), or a combination of the above. For example, the charge storage layer338may include HaAlO. Since an energy band difference between conduction bands of HaAlO and Si is only 1.63 electron volts, electrons moving in the channel329of memory element330are more easily tunneled to the conduction band of the charge storage layer338under the same gate voltage.

Moreover, the charge storage layer338may also include HfO2. Because the structure of HfO2helps in capturing electrons and is conducive to resolving the issue of excessive erasing, the performance of the memory element330can be enhanced. Moreover, the copper-phosphorus alloy may be used as deoxidizer and create oxygen vacancy with two positive charges at the lattice site of HfO2. Thus, the copper-phosphorus alloy layers333and337disposed on upper and lower sides of the charge storage layer338are capable of improving the capability of charge storage of HfO2. Meanwhile, the copper-phosphorus alloy layers333and337are further capable of preventing oxygen atoms from breaking away from HfO2and diffusing to the substrate310, and thus preventing an increase in the thickness of silicon dioxide (SiO2), as well as alleviating a degradation speed of the performance of the memory element330. In other words, with the copper-phosphorus alloy layers333and337and the charge storage layer338including HfO2, the memory element330of the present embodiment achieves better performance and reliability.

In the present embodiment, the control gate332may also include a multi-layer structure. For example, the control gate332may include a barrier layer3321, a copper-phosphorus alloy layer3322(for example, a third copper-phosphorus alloy layer) and a gate electrode layer3323sequentially formed on the oxide layer336. The barrier layer3321is capable of preventing metal of gate electrode layer3323from diffusing to the oxide layer336, and the copper-phosphorus alloy layer3322may serve as a wetting layer for plating the gate electrode layer3323. In some embodiments, for example, the barrier layer3321may include TiN, and the gate electrode layer3323may include Cu, W, Co or Rh. Moreover, in the present embodiment, the conductive plugs339A and339B may also include a multi-layer structure. For example, the conductive plug339A may include a barrier layer3391, a copper-phosphorus alloy layer3392and an electrode metal layer3393.

Details of operations of the memory element330, including write operations, erase operations (including two types) and read operations, are to be described below.

When a write operation is performed, the control gate332and the drain334B may receive a positive voltage (for example, a power supply voltage), and the source334A may receive a ground voltage. In such case, a vertically downward (for example, a negative direction of the Z axis) electric field is generated between the control gate332and the substrate310. When electrons accelerate from the source334A toward the drain334B along the channel329and bump into a junction region of the drain334B, an effect of hot electron injection is induced, such that some of the electrons are attracted by the vertically downward electric field in the channel329, pass through the oxide layer331, and enter the charge storage layer338. Since the electrons having entered the charge storage layer338do not possess excessive energy, these electrons are preserved in the charge storage layer338after the write operation, such that the memory element330is in a written state. In the present embodiment, the copper-phosphorus alloy layers333and337have needle-like protruding structures arranged in an array, which can increase both the charge density at the tips and the vertically downward electric field in the channel329, so the electrons that are halfway passing through the channel329can be captured, quickly pass through the oxide layer331and enter the charge storage layer338. Therefore, the time of the write operation can be reduced, and the performance of the memory element330is also enhanced.

When a first-type erase operation is performed, the control gate332may receive a ground voltage or a negative voltage, and the source334A and the drain334B may receive a positive voltage (for example, a power supply voltage). In this case, a vertically upward (for example, a positive direction of the Z axis) electric field is generated between the control gate332and the substrate310, and electrons residing in the charge storage layer338are attracted into the copper-phosphorus alloy layer333(which is capable of causing a tip effect that can enhance and concentrate the vertically upward electric field) and quickly return into the channel329between the source334A and the drain334B, thereby erasing the written state of the memory element330.

In some other embodiments, when a second-type erase operation is performed, the control gate332may receive a positive voltage, and the source334A and the drain334B may simultaneously receive a negative voltage. In such case, the strong vertically downward electric field can further attract the electrons residing in the charge storage layer338into the copper-phosphorus alloy layer337(which is capable of causing a tip effect that can enhance and concentrate the vertically downward electric field), thereby allowing the trapped electrons to quickly pass to the control gate332and erasing the written state of the memory element330. In other words, in the second-type erase operation, the memory element330of the present disclosure can attract the electrons residing in the charge storage layer338to the control gate332so that the electrons would pass through another oxide layer336, thereby reducing the number of times for the electrons passing through the oxide layer331and prolonging the durability of the memory element330.

When a read operation is performed, the control gate332may receive a ground voltage, the drain334B may receive a second positive voltage (for example, a threshold voltage), the source334A may receive a ground voltage, and a current flowing from the drain334B to the source334A in the channel is measured in the condition above. When the measured current is less than a predetermined threshold, it means that electrons are stored in the charge storage layer338, and the memory element330is determined as being in a written state (for example, represented by a value “1”) at this point in time. Conversely, when the measured current is greater than another predetermined threshold, it means that electrons stored in the charge storage layer338are not sufficient, and the memory element330is determined as being in an erased state or an unwritten state (for example, represented by a value “0”) at this point in time.

In some embodiments, the memory element330may have more than two storage states. That is to say, the memory element330may be a multi-level cell (MLC) capable of storing multiple bits. For example, according to the number of electrons in the charge storage layer338, the memory element330may be determined as being in one of the multiple storage states. In such case, a state of the number of electrons stored in the memory element330can be determined according to the magnitude of a current rating read on the channel. In some embodiments, according to the number of electrons stored in the memory element330, there may be four (or eight) states, and the memory element330can then be used to store 2-bit (or 3-bit) data.

FIG.6shows a schematic diagram of a semiconductor structure400according to an embodiment of the present disclosure. The semiconductor structure400may further add IGZO or silicon-germanium (e.g., Si(1-x)Gex, where 0≤x≤0.5) to channels between sources and drains of a transistors of the logic element and memory element. For example, a transistor MIN′ in a logic element420may further include a channel421A between the source321A and the drain321B, a transistor MIP′ in the logic element420may further include a channel421B between the source321C and the drain321D, and the memory element430may further include a channel431between the source334A and the drain334B. In the present embodiment, the channel421A,421B, and431can be IGZO channel or silicon-germanium channel.

Compared with a monocrystalline silicon enhancement mode element, IGZO is a depletion mode element and has a higher carrier concentration as well as a higher electron mobility, and thus provides not only higher speed of read and write operation but also better conductivity to reduce the operating voltage and size of transistor. Moreover, generally speaking, since a surface of IGZO can absorb oxygen in the environment, electrons (i.e., carriers) therein become bound, thereby allowing a transistor to have a higher threshold voltage. Thus, in some embodiments, the channels421A,421B and431can be IGZO channels and Ca, Mg or Cu may be further doped therein, so as to adjust threshold voltages of the logic element320and the memory element330. As such, the transistors therein can also be configured as enhancement modes transistors, thereby achieving better power-saving effects.

In some embodiments, the logic element and the memory element may include FINFETs. In the present embodiment the memory element may be formed as an EEPROM unit based on the structure of the FINFET.FIG.7shows a schematic diagram of a memory element530according to an embodiment of the present disclosure. The memory element530includes N memory cells530_1to530_N in parallel, where N is an integer greater than 1. Each of the memory cells530_1to530_N includes a fin structure532of a substrate510, and a control gate539for controlling a fin structure channel.

As shown inFIG.7, each of the memory cells530_1to530_N may further include a source52and a drain53disposed on two opposite ends of the fin structure532. In the present embodiment, the fin structure532between the source52and the drain53may be designed as a narrow nano-scale transistor channel. In this case, due to a narrow channel width between the source52and the drain53as well as an array structure (not depicted) of a copper-phosphorus alloy in the charge storage region, the possibility of collision between electrons and the crystal lattice in the channel or the junction area can be increased, thereby increasing the rate of the occurrence of hot electron injection, reducing an operating voltage and an operating time required by the memory element530, and enhancing the overall performance of the memory element530.

Moreover, to allow the memory element530to generate a sufficient current for facilitating the read operation, the memory cells530_1to530_N in the memory element530may be connected in parallel. For example, as shown inFIG.7, the sources52of the memory cells530_1to530_N may be connected to one another by a conductive line51A, and the drains53of the memory cells530_1to530_N may be connected to one another by a conductive line51B. In other words, the memory cells530_1to530_N receive the same voltage so that the write operations, erase operations and read operations can be performed upon them simultaneously. In some embodiments, the conductive lines51A and51B may be made of materials such as a multi-layer structure including a TiN layer, a copper-phosphorus alloy layer and a metal layer (Cu, W, Co or Rh), wherein the copper-phosphorus alloy layer may be disposed between the TiN layer and the metal layer; however, the present disclosure is not limited thereto.

In the present embodiment, the channels of the logic element and the memory element (for example, the channel between the sources52and the drains53) may include silicon-germanium material (for example, Si(1-x)Gex, where 0≤x≤0.5). Compared with a silicon-based channel, a channel made by using a silicon-germanium material has higher mobility (for example, 40% higher) and higher operating frequency (for example, 10% higher) as well as a lower threshold voltage. Moreover, by using silicon-germanium as a material for a channel, negative-bias temperature instability (NBTI) of the threshold voltage of a P-type transistor can be improved.

FIG.8shows a cross-sectional diagram of the memory element530seen from cutting along the section line A3-A3′ inFIG.7. In the present embodiment, the memory cells530_1to530_N may have a same structure, and are operable synchronously. For example, the memory cell530_1may include an oxide layer533(for example, including SiO2), a copper-phosphorus alloy layer534, a charge storage layer535(for example, including SiN, HaAlO, HfO2, Al2O3, or a combination of the above), a copper-phosphorus alloy layer536, an oxide layer537and a control gate539(for example, including Cu, W, Co or Rh) sequentially stacked on the fin structure532and surrounding a top and a sidewall of the fin structure532. In some embodiments, the oxide layer533may be a first oxide layer, the copper-phosphorus alloy layer534may be a first copper-phosphorus alloy layer, the oxide layer537may be a second oxide layer, and the copper-phosphorus alloy layer536may be a second copper-phosphorus alloy layer; however, the present disclosure is not limited thereto.

In the present embodiment, operation details of the memory element530are the same as that of the memory element330aforementioned, and such repeated description is omitted herein.

In addition to the DRAM unit in the memory elements130above and the EEPROM unit in the memory elements330,430and530aforementioned, the memory element may also be implemented by a ferroelectric memory cell, which also has a manufacturing process compatible with that of the transistors in the logic element.

FIG.9shows a schematic diagram of a semiconductor structure600according to an embodiment of the present disclosure. The memory element630of the semiconductor structure600is a ferroelectric memory cell.

The semiconductor structure600includes a substrate610, a logic element620and the memory element630. The logic element620may be disposed in a first region610A of the substrate610, and the memory element630may be disposed in a second region610B of the substrate610. The substrate610may include a wafer layer612, an epitaxial layer614, and P-wells PW1and PW2and an N-well NW1formed in the epitaxial layer614. The logic element620may include an N-type transistor MIN and a P-type transistor MIP respectively formed in the P-well PW1and the N-well NW1. The N-type transistor MIN and the P-type transistor MIP have the same structure as the transistors in the logic element320of the semiconductor structure300, and such repeated description is omitted herein.

The memory element630includes a source634A and a drain634B disposed in the P-well PW2, an oxide layer631, an array-structured ferroelectric material layer636(thickness between 5 nm and 15 nm), a copper-phosphorus alloy layer633and a control gate632. The source634A and the drain634B are N-type heavily doped regions in the P-well PW2. Moreover, in the present embodiment, N-type lightly doped regions635A and635B may be further disposed between the source634A and the drain634B and adjacent to the source634A and the drain634B, so as to enhance reliability of the memory element630.

The oxide layer631is disposed on the substrate610between the source634A and the drain634B.FIG.10shows a cross-sectional diagram of the ferroelectric material layer636by cutting along the section line A4-A4′ inFIG.9. In the present embodiment, the ferroelectric material layer636may be disposed on the oxide layer631(having a thickness between 1 nm and 5 nm), and may include an array formed by multiple protruding structures, as shown inFIG.10. The copper-phosphorus alloy layer633may be formed on the oxide layer631and filling the gaps around the array-structured ferroelectric material layer636. The control gate632may include electrode metal (for example, Cu, W, Co or Rh), and may be disposed on the copper-phosphorus alloy layer633and filled into the recess of the copper-phosphorus alloy layer633. In this case, the copper-phosphorus alloy layer633is disposed between the oxide layer631and the control gate632, and the array-structured ferroelectric material layer636is disposed between the copper-phosphorus alloy layer633and the oxide layer631. In another embodiment, the ferroelectric material layer636and the copper-phosphorus alloy layer633can be planar structures having uniform thicknesses and stacked sequentially (not depicted).

In the present embodiment, the ferroelectric material layer636may include HfO2. Compared with a conventional perovskite ferroelectric material, HfO2can be more compatible with CMOS manufacturing processes. Moreover, even with a thickness between 5 nm and 15 nm, HfO2can still maintain efficient and high-speed ferroelectricity. In some embodiments, Si, Zr, Al, N, La (lanthanum) or Ti may be added while HfO2is deposited so as to combine with HfO2to form electric dipoles. However, due to a lower crystallization temperature of HfO2, the oxide layer631may crystallize during a manufacturing process of the semiconductor structure600, such that electrons may tunnel easily to result in a large leakage current. In the present embodiment, to avoid the issue above, finer SiO2may be formed by means of ALD when the oxide layer631is formed, so as to reduce the occurrence of the leakage current.

Since the copper-phosphorus alloy layer633of the memory element630can extend into the holes in the ferroelectric material layer636, the ferroelectric material layer636having an array of multiple protruding structures can receive strengthened electric field induction in multiple directions during a write operation, thereby accelerating the speed of electric dipole polarization. Moreover, as the copper-phosphorus alloy layer633can serve as a deoxidizer, oxygen vacancies in the HfO2can be increased and the electric dipole effect can be reinforced, thereby reducing the operating voltage required by the memory element630. Meanwhile, deoxygenation performance of the copper-phosphorus alloy layer633is capable of preventing oxygen atoms of HfO2from diffusing to the substrate610, thereby preventing an increase in the thickness of SiO2as well as alleviating a degradation speed of the performance of the ferroelectric memory cell.

Details of operations of the memory element630are to be described below, including write operations and read operations.

In the present embodiment, corresponding to different storage states, the memory element630can support two write operation modes. For example, the write operation of the first type provides the ferroelectric material layer636with a first dipole polarization direction (for example, a negative direction of the Z axis), and the write operation of the second type provides the ferroelectric material layer636with a second dipole polarization direction (for example, a positive direction of the Z axis). In some embodiments, when the ferroelectric material layer636has the first dipole polarization direction, it means that the memory element630is in a first storage state (for example, logic “0”); conversely, when the ferroelectric material layer636has the second dipole polarization direction, it means that the memory element630is in a second storage state (for example, logic “1”).

When the write operation of the first type is performed, the source634A and the drain634B may receive a ground voltage or a negative voltage, and the control gate632may receive a positive voltage (for example, a threshold voltage). As such, the ferroelectric material layer636surrounded by the copper-phosphorus alloy layer633from three sides receives a downward (that is, a negative direction of the Z axis) electric field from multiple directions, that is, the top (a positive direction of the Z axis), the left (a negative direction of the X axis) and the right (a positive direction of the X axis), so that HfO2can quickly generate a downward electric dipole. At this point in time, the memory element630is written to have the first storage state (for example, logic “0”).

When the write operation of the second type is performed, the source634A and the drain634B may receive a positive voltage (for example, a threshold voltage), and the control gate632may receive a ground voltage or a negative voltage. As such, the ferroelectric material layer636surrounded by the copper-phosphorus alloy layer633from three sides receives an upward (that is, a direction of the Z axis) electric field in multiple directions, so that HfO2can quickly generate an upward electric dipole. At this point in time, the memory element630is written to have the second storage state (for example, logic “1”).

When a read operation is performed, the control gate632may receive a ground voltage, the drain634B may receive a positive voltage (for example, a threshold voltage), and the source634A may receive the ground voltage. If the memory element630is written to have the first storage state (that is, the electric dipole of the ferroelectric material layer636is directed downward), only an extremely small current (approximating to zero current) is generated in the channel. However, if the memory element630is written to have the second storage state (that is, the electric dipole of the ferroelectric material layer636is directed upward), a large current is generated in the channel. Thus, by reading the magnitude of the read channel current, the storage state of the memory element630can be determined.

FIG.11shows a schematic diagram of a semiconductor structure700according to an embodiment of the present disclosure. The semiconductor structure700may further add IGZO (or silicon-germanium) to channels between sources and drains of transistor structures in the logic element and the memory element. For example, a transistor MIN′ in a logic element720may further include a channel721A disposed in the substrate610between a source621A and a drain621B, a transistor MIP′ may further include a channel721B disposed in the substrate610between a source621C and a drain621D, and a memory element730may further include a channel731disposed in the substrate610between the source634A and the drain634B. In some embodiments, the channels721A,721B, and731may be added with IGZO or silicon-germanium, for example, Si(1-x)Gex, where 0≤x≤ 0.5.

Compared with non-crystalline silicon, IGZO has a higher carrier concentration as well as higher electron mobility, and thus provides better conductivity, thereby reducing an operating voltage and a size of a transistor. Moreover, the IGZO channel731can further prevent leakage current of the ferroelectric non-volatile memory cell and increase the response speed. In some embodiments, the IGZO channel731may be doped with a trivalent or pentavalent element so as to adjust a threshold voltage according to requirements. In some embodiments, the transistors MIN′ and MIP′ may be designed to be enhancement-mode transistors or depletion-mode transistors as needed. With effective use of the enhancement-mode transistors or depletion-mode transistors, the number of transistors needed in a logic gate (for example, a NAND gate or NOR gate) can be decreased, thereby reducing the overall circuit area needed.

Moreover, the IGZO channel731helps operations of the memory element730. For example, when the write operation of the first type is performed, the source634A and the drain634B may receive a ground voltage or a negative voltage, and the control gate632may receive a positive voltage. As such, the ferroelectric material layer636surrounded by the copper-phosphorus alloy layer633from three sides receives a downward (that is, a direction reverse to the Z axis) electric field in multiple directions, that is, the top (a direction of the Z axis), the left (a direction reverse to the X axis) and the right (a direction of the X axis), so that HfO2can quickly generate a downward electric dipole to write the memory element730to the first storage state (for example, logic “0”). Moreover, due to influences of the downward electric dipole, electron holes are produced on an upper surface of the IGZO channel731close to the oxide layer631as a result of induction of an electric field, hence forming an NPN transistor. Since the voltages of the source634A and the drain634B are ground voltages (or negative voltages) when the first-type write operation is performed, the junctions of the P-well PW2with respect to the source634A and the drain634B will not be forward biased, such that the holes in the channel are immobile, and a turned-off state is exhibited. In the present embodiment, such turned-off state may serve as the basis for determining a data state when a read operation is subsequently performed.

In contrast, when the second-type write operation is performed, the source634A and the drain634B may receive a positive voltage, and the control gate632may receive a negative voltage. As such, the ferroelectric material layer636surrounded by the copper-phosphorus alloy layer633from three sides receives an upward (that is, a direction of the Z axis) electric field in multiple directions, so that HfO2can quickly generate an upward electric dipole and the memory element630is quickly written to the second storage state (for example, logic “1”). Moreover, due to influences of the upward electric dipole in the ferroelectric material layer636and the induction of an electric field therein, more electrons are produced on the upper surface of the IGZO channel731close to the oxide layer631as a result of induction of an electric field, so that the IGZO channel731exhibits a more turned-on state. In the present embodiment, such turned-on state may serve as the basis for determining a data state when a read operation is subsequently performed.

When the read operation is performed, the source634A may receive a ground voltage, the drain634B may receive a positive voltage, and the control gate632may receive a ground voltage. In this case, if the memory element730is written to have the first storage state, due to the turned-off state exhibited by the IGZO channel731, a current flowing between the source634A and the drain634B approximates 0. In contrast, if the memory element730is written to have the second storage state, due to the turned-on state exhibited by the IGZO channel731, the current flowing between the source634A and the drain634B is more apparent. As such, according to the magnitude of the current flowing between the source634A and the drain634B, the storage state of the memory element730that is written can be determined. Moreover, in the present embodiment, the direction of the electric dipole of the ferroelectric material layer636does not change because no significant electric field is produced by the read operation between the control gate632, the source634A and the drain634B. That is to say, during the read operation, regardless of whether the memory element730is in the first storage state or the second storage state, the storage state thereof is not altered.

In some embodiments, with an appropriate design (for example, by applying electric fields in different sizes), the memory element730may be capable of supporting more storage states, and the storage state of the memory element730can be further determined according to the magnitude of a read channel current during a read operation. In other words, the memory element730may also be an MLC capable of storing multiple bits. For example, if the memory element730can be written into four storage states according to the direction and level of electric dipole polarization of the ferroelectric material layer636, the memory element730would be used to store 2-bit data.

In high performance computing, since computing operations often involve a large number of memory access operations, a large amount of heat energy is generated. In this case, heat dissipation is necessarily performed to maintain normal system operations. For example, a high bandwidth memory (HBM) frequently used in high performance computing urgently demands a solution for heat dissipation. Moreover, a DRAM that needs to frequently charge and discharge also highly demands for heat dissipation.

In such case, in order to enhance heat dissipation efficiency, a circuit board for carrying a memory may be placed in a cooling gas or a cooling liquid. In some embodiments of the present disclosure, an organic solderability preservative (OSP) on a circuit board may be partially removed to allow conductive lines to come into direct contact with a cooling gas or a cooling liquid, hence achieving better heat dissipation effects.

FIG.12shows a schematic diagram of a circuit board B1according to an embodiment of the present disclosure. The circuit board B1may include multiple conductive line layers; however, only a surface conductive line layer C1(for example, a copper foil formed by means of electroplating) of the circuit board B1is depicted inFIG.12. The lines in the surface conductive line layer C1may be used to connect various electronic components. Moreover, the surface conductive line layer C1is generally coated with an OSP P1, that is, the so-called green paint. The OSP P1is capable of reducing oxidation of the conductive lines in the surface conductive line layer C1and preventing the conductive lines in the surface conductive line layer C1from being scratched during test operations or short-circuitry during operations.

The surface conductive line layer C1may include multiple solder contacts S1for soldering with the electronic components (for example, chips). The solder contacts S1(e.g., a pad of SMT) may be exposed from the OSP P1so as to better perform subsequent solder printing for soldering with the electronic components. For example, an electronic component including the semiconductor structure100may have multiple pins, and the multiple pins of the electronic component may be soldered to the corresponding solder contacts S1. In the present embodiment, in addition to exposing the solder contacts S1from the OSP P1, the OSP P1on a portion of the conductive lines in the surface liner layer C1may be removed. As such, when the circuit board B1operates in a cooling gas or is immersed in a cooling liquid, at least a portion of the conductive lines in the surface conductive line layer C1can be in direct contact with the cooling gas or the cooling liquid, thereby improving the heat dissipation. In some embodiments, the portion of conductive lines exposed from the OSP P1may include, for example, a ground line G1for analog signals, a ground line G2for digital signals and a ground line G3for power supply. In some embodiments, the three ground lines G1, G2and G3may be connected to one another in a ground layer (not depicted). Since these ground lines are usually thick, wide and long, heat dissipation effects can be further enhanced. Moreover, these ground lines G1, G2and G3impose minimal influences on the overall system safety since the voltages thereof are 0.

Moreover, in the semiconductor structures100to700of the embodiments of the present disclosure, the conductive lines for connecting the logic element and the memory element may be enveloped by a copper-phosphorus alloy, so the occurrence of oxidation and corrosion of the conductive lines in high-temperature conditions can be reduced. Similarly, conductive lines on the circuit board B1can also be enveloped by copper-phosphorus alloy to reduce the occurrence of oxidation of the conductive lines in high-temperature conditions as well as the oxidation and corrosion in the working environment of air or liquid.

In conclusion, the semiconductor structure provided by the embodiments of the present disclosure is capable of integrating a logic element and a memory element into a same manufacturing process on a same chip, thereby lowering the production time and cost, as well as reducing the time needed for accessing a memory. In addition, the method improving overall heat dissipation performance of PCB is included, and thus promoting the development of high-performance computing.

The features of the various embodiments are described above to enable a person of ordinary skill in the art to better understand the aspects of the present disclosure. A person of ordinary skill in the art would be able to easily employ the details of the present disclosure as the basis to design or modify other operations and structures, so as to implement the same objects or achieve the same advantages as those of the embodiments. A person of ordinary skill in the art would be able to understand that, these equivalent solutions do not depart the spirit or scope of the present disclosure, and various alterations, replacements, substitutions and modifications may be made without departing from the spirit or scope of the present disclosure.

Moreover, the scope of the present disclosure is not limited to specific implementation forms of the processes, machines, manufactured products, substance compositions, means, methods and steps described in the detailed description. A person skilled in the art could easily understand from the present disclosure that, existing or future developed processes, machines, manufactured products, substance compositions, means, methods or steps that achieve the same functions or achieve substantially the same results corresponding to those of the embodiments described herein can be utilized according to the present disclosure. Accordingly, such processes, machines, manufactured products, substance compositions, device, methods or steps are encompassed within the scope of the appended claims.