Patent ID: 12237005

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG.1is a block diagram that illustrates a nonvolatile memory device according to some embodiments, andFIG.2is a block diagram that illustrates another nonvolatile memory device according to some embodiments. Referring toFIG.1, a nonvolatile memory device100according to some embodiments includes a memory cell array110, a row decoder120, a column decoder130, a write driver140, a data buffer150, and control logic160. As shown, the control logic160may include a normal standby mode circuit162and a deep standby mode circuit164. Referring now toFIG.2, the nonvolatile memory device100according to another embodiment includes a normal standby mode circuit162and/or a deep standby mode circuit164, which extend outside the control logic160. Hereinafter, the description will be made on the assumption that the normal standby mode circuit162and the deep standby mode circuit164are included inside the control logic160of the nonvolatile memory device100according to some embodiments.

Referring again toFIG.1, the row decoder120may control the voltages of a plurality of word lines WL in accordance with the control of the control logic160. For example, the row decoder120may apply a selective voltage for reading or writing to the selected word line, and may apply an unselective voltage (or voltages) for preventing the reading or writing to other unselected word lines.

The column decoder130may be connected to source lines and bit lines inside the memory cell array110. The column decoder130may be connected to the write driver. In accordance with the control of the control logic160, the column decoder130may electrically connect some selected source lines among the source lines and some selected bit lines among the bit lines to the write driver.

In accordance with the control of the control logic160, the column decoder130may apply bias voltages to the unselected remaining source lines among the source lines and the unselected remaining bit lines among the bit lines. The bias voltages may be defined not to affect the write operation or the read operation on the selected memory cells connected to the selected word line, some selected bit lines, and some selected source lines, and may include, for example, a ground voltage.

The data buffer150may be connected to the write driver140through the data lines DL. The data buffer150may exchange data with an external device (for example, a storage controller) in accordance with the control of the control logic160. For example, at the time of the write operation, the data buffer150may transmit the data, which is received from the external device, to the write driver140. At the time of the read operation, the data buffer150may output the data transmitted from sense amplifiers (not shown) in the write driver140to the external device.

The control logic160may receive a control signal and address from an external device (e.g., a storage controller). In response to the control signal and address received from an external device (e.g., a storage controller), the control logic may control the row decoder120, the column decoder130, the write driver140, and the data buffer150to perform the write operation or the read operation.

The control logic160may provide a write active signal and an inverting write active signal to the write driver140. The write active signal and the inverting write active signal may be, but are not limited to, complementary signals. When performing the write operation, the control logic160may control the write active signal to a high level, and control the inverting write active signal to a low level.

When the nonvolatile memory device100is in an active mode, peripheral circuits (e.g., the row decoder120, the column decoder130or the write driver140) may operate to perform an operation of storing data in the memory cells inside the memory cell array110or outputting the data stored in the memory cell to the outside. However, when the nonvolatile memory device100is in a normal standby mode, a standby status in which the read or write operation on the memory cell of the memory cell array110is not performed may be performed. When the nonvolatile memory device100enters the normal standby mode, peripheral circuits (e.g., the row decoder120, the column decoder130, or the write driver140) are deactivated, and the power consumed by the peripheral circuits (e.g., the row decoder120, the column decoder130, or the write driver140) may be reduced.

Furthermore, when the nonvolatile memory device100operates in the normal standby mode for a long time, in order to reduce the power consumption due to the leakage current in the nonvolatile memory device100, a deep standby mode in which the operation of the peripheral circuits (for example, the row decoder120, the column decoder130, or the write driver140) is completely stopped may be performed.

However, a leakage current may still occur even in the normal standby mode and the deep standby mode of the nonvolatile memory device100, and the power may be consumed by the nonvolatile memory device100. Therefore, the normal standby mode circuit162that operates in the normal standby mode and the deep standby mode circuit164that operates in the deep standby mode may be advantageously configured to minimize the leakage current generated in each mode.

For example, the normal standby mode circuit162, which is configured as a circuit that receives an analog signal (for example, light, temperature, humidity, etc.) and switches it into an electric signal, may operate when the nonvolatile memory device100enters the normal standby mode. Furthermore, the deep standby mode circuit164, which is configured as a circuit that receives an analog signal (for example, light, temperature, humidity, etc.) and switches it into an electric signal, has a circuit diagram that is equivalent to the normal standby mode circuit162. However, the areas of the elements constituting the deep standby mode circuit164may be smaller (with less leakage) than those of the plurality of elements constituting the normal standby mode circuit162.

That is, by making the circuits that operate in the normal standby mode and the deep standby mode different from each other, the leakage current generated in each mode may be minimized. More specifically, since the areas of the plurality of elements of the deep standby mode circuit164are smaller than the areas of the plurality of elements of the normal standby mode circuit162, the leakage current flowing through the deep standby mode circuit164may become smaller.

This will be explained in detail through the normal standby mode circuit162and the deep standby mode circuit164, which are schematically configured, through the circuit which receives an analog signal (for example, light, temperature, humidity, etc.) and switches it into an electric signal inFIGS.3and4. The configuration of the circuit that receives the analog signal (e.g., light, temperature, or humidity, etc.) and switches it into an electrical signal is not limited toFIGS.3and4.

FIG.3is an exemplary circuit diagram for explaining a normal standby mode circuit which operates in a normal standby mode, whereasFIG.4is an exemplary circuit diagram for explaining a deep standby mode circuit which operates in a deep standby mode. Referring toFIG.3, the normal standby mode circuit162that operates when the nonvolatile memory device is in the normal standby mode may include a sensing circuit (a) that senses an analog signal, and an OP AMP (a) that amplifies the analog signal.

The sensing circuit (a) of the normal standby mode circuit162includes transistors P1a and P3a that are connected to a power supply voltage VDD and gated by a first voltage NSM_V1. Further, the sensing circuit (a) includes a transistor P2a connected in series with the transistor P1a, and a transistor P4a connected in series with a transistor P3a. The transistor P2a and the transistor P4a may be gated by a second voltage NSM_V2. One end of each of the transistors P2a and P4a may receive analog signals V_INa and V_IMa, respectively. A resistor R1a may be connected to a node at which the transistor P4a receives the analog signal V_IMa.

The sensing circuit (a) may include bipolar junction transistors PNP1a and PNP2a connected to a ground voltage VSS. The base terminals of the bipolar junction transistors PNP1a and PNP2a are connected to each other and may be connected to the ground voltage VSS. The OP AMP (a) of the normal standby mode circuit162receives each of the analog signals V_INa and V_IMa, and may amplify the received analog signal into an electric signal. The OP AMP (a) includes transistors N1a and N2a that receive each of the analog signals V_INa and V_IMa.

One end of each of the transistors N1a and N2a are connected to each other, and may be connected to a transistor N3a connected to the ground voltage VSS. A first voltage NSM_V1 and a second voltage NSM_V2 may applied to each of both ends (first node n1 and second node n2) of a resistor R2a connected to the transistor N1a.

The OP AMP (a) may include transistors P5a and P6a which are connected to the power supply voltage VDD and have gates connected to each other. One end of the transistor P5a may be connected to the first node n1. Further, one end of the transistor P6a may be connected to the resistor R3a. The other end of the resistor R3a may be connected to the transistor N2a. At this time, when the nonvolatile memory device is in the normal standby mode, the sensing circuit (a) of the normal standby mode circuit162is turned on (ON) and the OP AMP (a) is turned off (OFF). That is, in the normal standby mode, only the sensing circuit (a) of the normal standby mode circuit162may operate.

Referring toFIGS.3and4, the deep standby mode circuit164that operates when the nonvolatile memory device is in the deep standby mode may include a sensing circuit (b) that senses an analog signal, and an OP AMP (b) that amplifies the analog signal. Since the configurations of the circuit diagram of the deep standby mode circuit164and the circuit diagram of the normal standby mode circuit162are the same, differences will be mainly described. Advantageously, to reduce leakage currents during standby mode, the areas of the plurality of elements constituting the deep standby mode circuit164are smaller than the corresponding areas of the plurality of elements constituting the normal standby mode circuit162.

For example, areas of transistors P1b, P2b, P3b, P4b, P5b, P6b, N1 b, N2b, N3b, PNP1b, and PNP2b that form the switching elements of the deep standby mode circuit164are smaller than areas of corresponding transistors P1 a, P2a, P3a, P4a, P5a, P6a, N1a, N2a, N3a, PNP1a, and PNP2a that form the normal standby mode circuit162. Further, areas of resistors R1b, R2b, and R3b that form the deep standby mode circuit164are smaller than areas of resistors R1a, R2a, and R3a that form the normal standby mode circuit162.

For example, the areas of the transistors P1b, P2b, P3b, P4b, P5b, P6b, N1 b, N2b, N3b, PNP1b, and PNP2b and the resistors R1b, R2b, and R3b that form the deep standby mode circuit164may be one-half (½) the areas of the transistors P1 a, P2a, P3a, P4a, P5a, P6a, N1a, N2a, N3a, PNP1a, and PNP2a and the resistors R1a, R2a, and R3a that form the normal standby mode circuit162, however, size ratios other than one-half may also be utilized in other embodiments of the invention.

Based on these smaller dimensions, current flowing through the sensing circuit (b) of the deep standby mode circuit164is smaller than the current flowing through the sensing circuit (a) of the normal standby mode circuit162under otherwise equivalent circumstances. Further, the current flowing through the OP AMP (b) of the deep standby mode circuit164is smaller than the current flowing through the OP AMP (a) of the normal standby mode circuit162.

For example, a case is assumed where the areas of the transistors P1b, P2b, P3b, P4b, P5b, P6b, N1 b, N2b, N3b, PNP1b, and PNP2b and the resistors R1b, R2b, and R3b that form the deep standby mode circuit164are one-half the areas of the transistors P1 a, P2a, P3a, P4a, P5a, P6a, N1a, N2a, N3a, PNP1a, and PNP2a and the resistors R1a, R2a, and R3a that form the normal standby mode circuit162.

For example, assuming that the current flowing through the power supply voltage VDD of the sensing circuit (a) of the normal standby mode circuit162is 3 u, the current flowing through the power supply voltage VDD of the sensing circuit (b) of the deep standby mode circuit164may be 1.5 u. Further, assuming that the current flowing through the power supply voltage VDD of the OP AMP (a) of the normal standby mode circuit162is 1.5 u, the current flowing through the power supply voltage VDD of the OP AMP (b) of the deep standby mode circuit164may be 0.75 u.

Accordingly, when the nonvolatile memory device is in the deep standby mode, the sensing circuit (b) of the deep standby mode circuit164is turned off (OFF), and the OP AMP (b) is turned on (ON). That is, in the deep standby mode, only the OP AMP (b) of the deep standby mode circuit164may operate.

Therefore, the configurations of the normal standby mode circuit162and the deep standby mode circuit164are set to be the same, but the areas of each element are set to be different, and by operating the circuit that may minimize the power consumption according to the mode in which the nonvolatile memory device operates, it is possible to reduce the power consumption due to the leakage current of the nonvolatile memory device.

Referring toFIG.1again, the control logic160may generate gate voltages V1 and V2 at the time of the write operation. The gate voltages V1 and V2 may be transmitted to the write driver140and the row decoder120. The first voltage V1 may be used by the write driver to generate a write voltage. Further, the second voltage V2 drives the word line driver and may be used by the row decoder120to select the word line. The gate voltages V1 and V2 may have a higher level than the level of the write voltage or the power supply voltage of the nonvolatile memory device100.

The write driver140may generate write voltages having the same levels, using the first voltage V1. Since the first voltage V1 is higher than the write voltage or the power supply voltage, the write driver140may generate a write voltage having a level close to the level of the power supply voltage.

FIG.5is an exemplary circuit diagram for explaining a memory cell array.FIG.6is an exemplary perspective view for explaining the memory cell of a memory cell array. Referring toFIGS.1,5and6, the memory cell array110includes a memory cell MC. The memory cell MC may be connected to source lines SL1 to SLn (n is a positive integer), bit lines BL1 to BLn, and word lines WL1 to WLm (m is a positive integer). The memory cells MC may be placed in rows and columns to thereby form a two-dimensional array of memory cells. The rows of the memory cells MC may be connected to each of the word lines WL1 to WLm. The rows of the memory cells MC may be connected to each of the source lines SL1 to SLn and the bit lines BL1 to BLn. The voltages of the word lines WL1 to WLm may be controlled through the row decoder120by the control of the control logic160. The bit lines BL1 to BLn and the source lines SL1 to SLn may be connected to the column decoder130.

One memory cell MC may include a selection transistor ST and a variable resistance element VR (that specifies a logic state of the MC). The selection transistor ST includes a first junction connected to each of the source lines SL1 to SLn, a second junction connected to each of the bit lines BL1 to BLn through the variable resistance element VR, and a gate connected to each of the word lines WL1 to WLm between the first junction and the second junction. For example, a gate of the selection transistor ST may be connected to the first word line WL1. One electrode of the selection transistor ST may be connected to the first bit line BL1 through the variable resistance element VR. Further, another electrode of the selection transistor ST may be connected to the first source line SL1.

The variable resistance element VR may include a pinned layer PL, a tunnel layer TL, and a free layer FL. The pinned layer PL may have a fixed magnetization direction. The free layer FL may have a magnetization direction that changes depending on the voltage (or current) applied to the variable resistance element VR. As will be understood by those skilled in the art, the resistance of the variable resistance element VR may change depending on whether the magnetization direction of the free layer FL is the same as (or how it is the same) or different from (or how it is different) the magnetization direction of the pinned layer PL. The variable resistance element VR may store data in the form of resistance magnitude.

FIG.7is a diagram for explaining the operation of the nonvolatile memory device according to some embodiments. Referring toFIGS.1and7, the nonvolatile memory device100according to some embodiments may further include a first switch unit170and a second switch unit172. The first switch unit170and/or the second switch unit172may be placed inside or outside the control logic160, as described hereinabove with respect toFIGS.1-2. The first switch unit170may be connected to the normal standby mode circuit162. The first switch unit170may include a plurality of switches SW1a and SW1b. The first switch unit170may be controlled by a first switch enable signal SW1_EN. The first switch enable signal SW1_EN may be received from the control logic160.

The second switch unit172may be connected to the deep standby mode circuit164. The second switch unit172may include a plurality of switches SW2a and SW2b. The second switch unit172may be controlled by a second switch enable signal SW2_EN. The second switch enable signal SW2_EN may be received from the control logic160.

The normal standby mode circuit162may be activated by a normal standby mode enable signal NSM_EN. The normal standby mode enable signal NSM_EN may be received from the control logic160. The deep standby mode circuit164may be activated by a deep standby mode enable signal DSM_EN. The deep standby mode enable signal DSM_EN may be received from the control logic160.

The first voltage NSM_V1 of the normal standby mode circuit162is transmitted to a switch SW1a, and the second voltage NSM_V2 may be transmitted to a switch SW1b. If the first switch unit170is activated by the first switch enable signal SW1_EN and the switches SW1a and SW1b are turned on, the first voltage NSM_V1 may be applied with a voltage V1 that gates the transistors T1 and T1a to T1n that form the write driver140through the first node n1. Further, if the first switch unit170is activated by the first switch enable signal SW1_EN and the switches SW1a and SW1b are turned on, the second voltage NSM_V2 may be applied with a voltage V2 that gates the transistor T2 connected to the row decoder120through the second node n2.

A first voltage DSM_V1 of the deep standby mode circuit164is transmitted to the switch SW2a, and a second voltage DSM_V2 may be transmitted to the switch SW2b. If the second switch unit172is activated by the second switch enable signal SW2_EN and the switches SW2a and SW2b are turned on, the first voltage DSM_V1 may be applied with the voltage V1 that gates the transistors T1 and T1a to T1n that form the write driver140through the first node n1. Further, if the second switch unit172is activated by the second switch enable signal SW2_EN and the switches SW2a and SW2b are turned on, the second voltage DSM_V2 may be applied with the voltage V2 that gates the transistor T2 connected to the row decoder120through the second node n2.

The transistor T1 may be connected to the power supply voltage VDD and the other end may be connected in series with the transistor T2. The resistor R connected in series with the transistors T1 and T2 may be connected to the ground voltage VSS. A reference voltage V_ref may be output through the node by which the transistor T2 and the resistor R are connected. The transistors T1 and T2 and the resistor R may form a reference voltage generation circuit unit180.

FIG.8is a timing diagram for explaining the operation of the nonvolatile memory device according to some embodiments. Referring toFIGS.7and8, the deep standby mode enable signal DSM_EN may be applied from a first time point t1 to a third time point t3. At this time, the deep standby mode enable signal DSM_EN is delayed during wake-up time, and a deep standby mode enable delay signal DSM_EN_D may be applied at a second time point t2 delayed by the wake-up time. That is, the deep standby mode enable delay signal DSM_EN_D is delayed during the wake-up time from a third time point t3 when the deep standby mode enable signal DSM_EN is turned off, and the deep standby mode enable delay signal DSM_EN_D may be turned off at a fourth time point t4 which is delayed by the wake-up time.

In contrast, the normal standby mode enable signal NSM_EN may be turned on during the wake-up time (e.g., during the time from the first time point t1 to the second time point t2 and during the time from the third time point t3 to the fourth time point t4). For example, the normal standby mode enable signal NSM_EN may be turned on until the second time point t2, turned off from the second time point t2 to the third time point t3, and turned on from the third time point t3 to the fourth time point t4. As shown, the second switch enable signal SW2_EN that activates the second switch unit172connected to the deep standby mode circuit164may be turned on from the second time point t2 to the fourth time point t4 when the deep standby mode enable delay signal DSM_EN_D is turned on. Thus, the first switch enable signal SW1_EN that activates the first switch unit170connected to the normal standby mode circuit162may be turned off, while the second switch enable signal SW2_EN is turned on. That is, the first switch enable signal SW1_EN may be turned off from the second time point t2 to the fourth time point t4.

FIGS.9and10are circuit diagrams for explaining another exemplary embodiment of the reference voltage generation circuit unit180ofFIG.7. Referring toFIG.9, a reference voltage generation circuit unit180aincludes transistors T11 and T22 connected in series with the power supply voltage VDD, and further includes transistors T1 and T2 connected in series with the power supply voltage VDD.

Transistors T1 and T11 may be gated by the first voltage V1. Further, transistors T2 and T22 may be gated by the second voltage V2. A transistor T1 and a transistor T11 may have an area ratio of N:1 (N is a natural number). Further, a transistor T2 and a transistor T22 may have an area ratio of N:1. The transistor T22 may be connected to a switch SW3. A switch SW22 and a resistor R22 connected in series may be connected to a third node n3 in which the reference voltage V_ref is generated. Further, a switch SW11 and a resistor R11 connected in series may be connected to the third node n3 in which the reference voltage V_ref is generated.

A ratio of the resistance magnitudes of the resistor R11 and the resistor R22 may be N+1:1. For example, when the nonvolatile memory device operates in the normal standby mode, the switches SW3 and SW22 may be open, and the switch SW11 may be closed. Further, when the nonvolatile memory device operates in the deep standby mode, the switch SW11 may be open, and the switches SW3 and SW22 may be closed.

That is, the reference voltage V_ref that is output through the third node n3 is the same in the normal standby mode and the deep standby mode. However, since the current flowing through the transistors T11 and T22 whose resistance decreases in the deep standby mode decreases, the leakage current can still be reduced.

Referring toFIG.10, unlikeFIG.9, the transistor T33 may be connected to the third node n3 of the reference voltage generation circuit unit180b. The transistor T33 has a structure in which a gate and a drain are connected.FIG.11is a circuit diagram for explaining another exemplary embodiment of the output terminal P_O ofFIGS.9and10. Referring toFIG.11, the output terminal P_Oa includes a resistor R5, and a switch SW4 connected in series with the resistor, between the third node n3 and the reference voltage V_ref generation node. Further, a buffer190may be included between the third node n3 and the reference voltage V_ref generation node. Further, a capacitor C may be connected to the reference voltage V_ref generation node.

The buffer190may be activated by the buffer enable signal EN. One end of the buffer190may be connected to the third node n3, and the other end of the buffer190may be connected to the output of the buffer190. A switch SW5 may be connected between the output of the buffer190and the reference voltage V_ref generation node.

The operation of the output terminal P_Oa is explained throughFIG.12. In particular,FIG.12is a timing diagram for explaining the operation of the output terminal. Referring toFIGS.11and12, for example, the nonvolatile memory device is assumed to be turned on at the first time point t1 (tON). After that, the reset time after the normal standby mode or the deep standby mode is assumed to progress from the second time point t2 to the third time point t3 (tREST). At this time, the buffer enable signal EN that activates the buffer190may be activated from the second time point t2 at which the reset time starts to the fourth time point t4 at which the capacitor C is charged. The switch SW5 may also be turned on from the second time point t2 to the fourth time point t4 (tSW).

FIGS.13and14are block diagrams for explaining a storage system according to some embodiments.FIG.13is a diagram showing a system1000to which the nonvolatile memory device according to the embodiment of the present disclosure is applied. The system1000ofFIG.13may be basically a mobile system such as a mobile phone terminal, a smart phone, a tablet PC (tablet personal computer), a wearable device, a healthcare device, or an Internet of Things (IOT) device. However, the system1000ofFIG.13is not necessarily limited to the mobile system, but may be a personal computer, a laptop computer, a server, a media player, or an automotive device such as navigation.

Referring toFIG.13, the system1000may include a main processor1100, memories1200aand1200b, and storage devices1300aand1300b, and may additionally include one or more of an image capturing device1410, a user input device1420, a sensor1430, a communication device1440, a display1450, a speaker1460, a power supplying device1470, and a connecting interface1480.

The main processor1100may control the overall operations of the system1000, more specifically, the operations of other components that form the system1000. Such a main processor1100may be implemented as a general purpose processor, a dedicated processor, an application processor, or the like. In some embodiments, the main processor1100may include one or more CPU cores1110, and may further include a controller1120for controlling the memories1200aand1200band/or the storage devices1300aand1300b. Depending on the embodiments, the main processor1100may further include an accelerator1130, which is a dedicated circuit for a high-speed data computation such as an Al (artificial intelligence) data computation. Such an accelerator1130may include a GPU (Graphics Processing Unit), an NPU (Neural Processing Unit) and/or a DPU (Data Processing Unit), and the like, and may be implemented as separate chips that are physically independent of other components of the main processor1100.

The memories1200aand1200bmay be used as a main memory unit of the system1000, and may include a volatile memory such as an SRAM and/or a DRAM, but may also include a nonvolatile memory such as a flash memory, a PRAM and/or a RRAM. The memories1200aand1200bcan also be implemented in the same package as the main processor1100.

The storage devices1300aand1300bmay function as nonvolatile storage devices that store data regardless of whether a power is supplied, and may have a relatively larger capacity than those of the memories1200aand1200b. The storage devices1300aand1300bmay include storage controllers1310aand1310b, and nonvolatile memories (NVM)1320aand1320bthat store data under the control of the storage controllers1310aand1310b.

The nonvolatile memories1320aand1320bmay be nonvolatile memory devices explained above, for example, throughFIGS.1to12. The nonvolatile memories1320aand1320bmay include a flash memory of a 2D (2-dimensional) structure or a 3D (3-dimensional) V-NAND (Vertical NAND) structure, but may also include other types of nonvolatile memory such as a PRAM, a MRAM and/or a RRAM.

The storage devices1300aand1300bmay be included in the system1000in a state of being physically separated from the main processor1100, and may be implemented inside the same package as the main processor1100. Further, since the storage devices1300aand1300bhave a shape such as an SSD (solid state device) or a memory card, the storage devices1300aand1300bmay also be detachably coupled with other constituent elements of the system1000through an interface such as a connecting interface1480to be described below. Such storage devices1300aand1300bmay be, but are not necessarily limited to, devices to which standard protocols such as a UFS (universal flash storage), an eMMC (embedded multi-media card) or an NVMe (nonvolatile memory express) are applied.

The image capturing device1410may capture still images or moving images, and may be a camera, a camcorder, and/or a webcam and the like. The user input device1420may receive various types of data that are input from users of the system1000, and may be a touch pad, a key pad, a key board, a mouse and/or a microphone.

The sensor1430may detect various different physical quantities that may be acquired from the outside of the system1000, and convert the detected physical quantities into electrical signals. Such a sensor1430may be a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor and/or a gyroscope sensor.

The communication device1440may transmit and receive signals to and from other devices outside the system1000according to various communication protocols. Such a communication device1440may be implemented to include an antenna, a transceiver and/or a modem and the like.

The display1450and the speaker1460may each function as output devices that output visual and auditory information to the user of the system1000. In addition, the power supplying device1470may appropriately convert the power supplied from a battery (not shown) equipped in the system1000and/or an external power supply and supply the power to each constituent element of the system1000.

The connecting interface1480may provide a connection between the system1000and an external device that may be connected to the system1000to transmit and receive data to and from the system1000. The connecting interface1480may be implemented by various interface types, such as an ATA (Advanced Technology Attachment), a SATA (Serial ATA), an e-SATA (external SATA), a SCSI (Small Computer Small Interface), a SAS (Serial Attached SCSI), a PCI (Peripheral Component Interconnection), a PCIe (PCI express), a NVMe, an IEEE 1394, a USB (universal serial bus), an SD (secure digital) card, a MMC (multi-media card), an eMMC, a UFS, an eUFS (embedded Universal Flash Storage), and a CF (compact flash) card interface.

Referring toFIG.14. a host-storage system2000may include a host2100and a storage device2200. Further, the storage device2200may include a storage controller2210and a nonvolatile memory (NVM)2220. Further, according to exemplary embodiments of the present disclosure, the host2100may include a host controller2110and a host memory2120. The host memory2120may function as a buffer memory for temporarily storing data to be transmitted to the storage device2200or data transmitted from the storage device2200.

The storage device2200may include storage medium for storing data in response to a request from the host2100. As an example, the storage device2200may include at least one of an SSD (Solid status Drive), an embedded memory, and an attachable and detachable external memory. When the storage device2200is the SSD, the storage device2200may be, for example, a device that complies with a non-volatility memory express (NVMe) standard. When the storage device2200is an embedded memory or an external memory, the storage device2200may be a device that complies with a UFS (universal flash storage) or an eMMC (embedded multi-media card) standard. The host2100and the storage device2200may each generate and transmit packets according to the adopted standard protocol.

When the nonvolatile memory2220of the storage device2200includes a flash memory, such a flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the storage device2200may include different various types of nonvolatile memories. For example, the storage device2200may include a MRAM (Magnetic RAM), a spin-transmit torque MRAM, a conductive bridging RAM (CBRAM), a FeRAM (Ferroelectric RAM), a PRAM (Phase RAM), a resistive memory (Resistive RAM), and various other types of memories.

The nonvolatile memory2220may be the nonvolatile memory device explained above throughFIGS.1to12. According to an embodiment, the host controller2110and the host memory2120may be implemented as separate semiconductor chips. Further, in some embodiments, the host controller2110and the host memory2120may be integrated on the same semiconductor chip. As an example, the host controller2110may be any one of a plurality of modules provided in the application processor, and the application processor may be implemented as a system on chip (SoC). Further, the host memory2120may be an embedded memory provided inside the application processor, or a nonvolatile memory or a memory module placed outside the application processor.

The host controller2110may manage an operation of storing the data (for example, write data) of a buffer region of the host memory2120in the nonvolatile memory2220or storing the data (for example, read data) of the nonvolatile memory2220in the buffer region.

The storage controller2210may include a host interface2211, a memory interface2212, and a CPU (central processing unit)2213. Also, the storage controller2210may further include a flash translation layer (FTL)2214, a packet manager2215, a buffer memory2216, an ECC (error correction code, 2217) engine, and an encryption/decryption engine2218. The storage controller2210may further include a working memory (not shown) into which the flash translation layer (FTL)2214is loaded, and when the CPU2213executes the flash translation layer, the data write and read operations on the nonvolatile memory may be controlled.

The host interface2211may transmit and receive packets to and from the host2100. The packets transmitted from the host2100to the host interface2211may include a command, data to be written in the nonvolatile memory2220, or the like. The packets transmitted from the host interface2211to the host2100may include a response to the command, data that is read from the nonvolatile memory2220or the like. The memory interface2212may transmit the data to be written in the nonvolatile memory2220to the nonvolatile memory2220or receive the data that is read from the nonvolatile memory2220. Such a memory interface2212may be implemented to comply with standard protocols such as Toggle or ONFI (Open NAND Flash Interface).

The flash translation layer2214may perform various functions such as address mapping, wear-leveling, and garbage collection. The address mapping operation is an operation of changing a logical address received from the host2100into a physical address which is used for actually storing the data in the nonvolatile memory2220. The wear-leveling is a technique for ensuring that blocks in the nonvolatile memory2220are used uniformly to prevent an excessive degradation of a particular block, and may be implemented, for example, through a firmware technique for balancing the erasure counts of the physical blocks. The garbage collection is a technique for ensuring an available capacity in the nonvolatile memory2220through a method of copying the valid data of the block to a new block and then erasing the existing block.

The packet manager2215may generate a packet according to the protocol of the interface discussed with the host2100, or may parse various types of information from the packet received from the host2100. Further, the buffer memory2216may temporarily store the data to be written in the nonvolatile memory2220or the data to be read from the nonvolatile memory2220. The buffer memory2216may be configured to be provided inside the storage controller2210, but may be placed outside the storage controller2210.

An ECC engine2217may perform error detection and correction functions on the read data that is read from the nonvolatile memory2220. More specifically, the ECC engine2217may generate parity bits for the write data to be written on the nonvolatile memory2220, and the parity bits thus generated may be stored in the nonvolatile memory2220together with the write data. When reading the data from the nonvolatile memory2220, the ECC engine2217may correct an error of the read data, using the parity bits that are read from the nonvolatile memory2220, together with the read data, and may output the read data with a corrected error.

The encryption/decryption engine2218may perform at least one operation of the encryption operation and the decryption operation on the data that is input to the storage controller2210.

For example, the encryption/decryption engine2218may perform the encryption operation and/or the decryption operation using a symmetric-key algorithm. At this time, the encryption/decryption engine2218may perform encryption and/or decryption operations using, for example, an AES (Advanced Encryption Standard) algorithm or a DES (Data Encryption Standard) algorithm.

Further, for example, the encryption/decryption engine2218may perform the encryption operation and/or the decryption operation, using a public key encryption algorithm. At this time, for example, the encryption/decryption engine2218may perform the encryption using the public key at the time of the encryption operation, and may perform the decryption using the private key at the time of the decryption operation. For example, the encryption/decryption engine2218may use RSA (Rivest Shamir Adleman), ECC (Elliptic Curve Cryptography) or DH (Diffie-Hellman) encryption algorithm.

The encryption/decryption engine2218may perform the encryption operation and/or the decryption operation, using quantum cryptography such as HO (Homomorphic Encryption), PQC (Post-Quantum Cryptography) or FE (Functional Encryption), without being limited thereto.

In concluding the detailed description, those skilled in the art will appreciate that many variations and modifications may be made to the preferred embodiments without substantially departing from the principles of the present disclosure. Therefore, the disclosed preferred embodiments of the disclosure are used in a generic and descriptive sense only and not for purposes of limitation.