Patent ID: 12230197

DESCRIPTION OF THE EMBODIMENTS

Like features have been designated by like references in the various figures. In particular, the structural and/or functional features that are common among the various embodiments may have the same references and may dispose identical structural, dimensional and material properties. For the sake of clarity, only the steps and elements that are useful for an understanding of the embodiments described herein have been illustrated and described in detail.

In the following description, when reference is made to terms qualifying absolute positions, such as terms “front”, “rear”, “top”, “bottom”, “left”, “right”, etc., or relative positions, such as terms “above”, “under”, “upper”, “lower”, etc., or to terms qualifying directions, such as terms “horizontal”, “vertical”, etc., it is referred, unless specified otherwise, to the orientation of the drawings or to a display screen in a normal position of use.

Unless indicated otherwise, when reference is made to two elements connected together, this signifies a direct connection without any intermediate elements other than conductors, and when reference is made to two elements coupled together, this signifies that these two elements can be connected or they can be coupled via one or more other elements.

Further, there is called “binary signal” a signal which alternates between a first constant state, for example, a low state, noted “0”, and a second constant state, for example, a high state, noted “1”. The high and low states of different binary signals of a same electronic circuit may be different. In practice, the binary signals may correspond to voltages which may not be perfectly constant in the high or low state.

Further, in the following description, there are called “power terminals” of an insulated gate field-effect transistor, or MOS transistor, the source and the drain of the MOS transistor.

Further, unless indicated otherwise, when it is spoken of a voltage at a conductive pad, the difference between the potential at said conductive pad and a reference potential, for example, the ground, taken as equal to 0 V, is considered.

Further, it is here considered that the terms “insulating” and “conductive” respectively signify “electrically insulating” and “electrically conductive”.

Unless specified otherwise, the expressions “around”, “approximately”, “substantially” and “in the order of” signify within 10%, and preferably within 5%.

FIG.1partially and schematically shows a known example of a display screen10. Display screen10comprises display pixels12i,j, for example, arranged in M rows and in N columns, M being an integer varying from 1 to 8,000 and N being an integer varying from 1 to 16,000, i being an integer varying from 1 to M, and j being an integer varying from 1 to N. As an example, inFIG.1, M and N are equal to 6. Each display pixel12i,jis coupled to a source of a low reference potential Gnd, for example, the ground, via an electrode14iand to a source of a high reference potential Vcc via an electrode16j. As an example, electrodes14iare shown as being aligned along the rows inFIG.1and electrodes16jare shown as being aligned along the columns inFIG.1, the reverse layout being possible. The power supply voltage of the display screen corresponds to the voltage between high reference potential Vcc and low reference potential Gnd, and is noted Vcc like the high reference potential. Power supply voltage Vcc particularly depends on the arrangement of the light-emitting diodes and on the technology according to which the light-emitting diodes are manufactured. As an example, power supply voltage Vcc may be in the order of from 4 V to 5 V.

For each row, the display pixels12i,jin the row are coupled to a row electrode18i. For each column, the display pixels12i,jin the column are coupled to a column electrode20j. Display screen10comprises a selection circuit22coupled to row electrodes18iand adapted to delivering a selection and timing signal Comion each row electrode18i. Display screen10comprises a data delivery circuit24coupled to column electrodes20jand adapted to delivering a data signal Datajon each column electrode20j. Selection circuit22and control circuit24are controlled by a circuit26, for example comprising a processor.

FIG.2is a very simplified cross-section view of a known example of display pixel12i,jandFIG.3is a bottom view of display pixel12i,j. Each display pixel12i,jcomprises a control circuit30covered with a display circuit32. Display circuit32comprises at least one light-emitting diode LED, preferably at least three light-emitting diodes LED. The display pixel comprises a lower surface34and an upper surface35opposite to lower surface34, surfaces34and35being preferably planar and parallel. Control circuit30further comprises conductive pads36, not shown inFIG.2, on lower surface34. Control circuit30may correspond to an integrated circuit comprising electronic components, particularly insulated gate field effect transistors, also called MOS transistors, or thin film transistors, also called TFTs. Preferably, display circuit32only comprises light-emitting diodes LED and the conductive elements of these light-emitting diodes LED and control circuit30comprises all the electronic components necessary for the control of the light-emitting diodes LED of display circuit32. As a variant, display circuit32may also comprise other electronic components in addition to light-emitting diodes LED. Light-emitting diodes LED may be 2D light-emitting diodes, also called planar light-emitting diodes, comprising a stack of planar layers, or 3D light-emitting diodes, each comprising a three-dimensional semiconductor element covered with an active area. InFIG.2, light-emitting diodes LED are shown as being connected with a common anode. It may however be desirable to arrange light-emitting diodes LED according to another configuration. As an example, light-emitting diodes LED may be connected with a common cathode, or be connected independently from one another.

According to an embodiment, display pixel12i,jcomprises three display sub-pixels emitting light at first, second, and third wavelengths. According to an embodiment, the first wavelength corresponds to blue light and is within the range from 430 nm to 490 nm. According to an embodiment, the second wavelength corresponds to green light and is within the range from 510 nm to 570 nm. According to an embodiment, the third wavelength corresponds to red light and is within the range from 600 nm to 720 nm.

Each conductive pad36is intended to be connected to one of the electrodes14i,16j,18i,20jschematically shown inFIG.2. A first conductive pad36is coupled to the source of low reference potential Gnd. A second conductive pad is coupled to the source of high reference potential Vcc. A third conductive pad36is coupled to row electrode18; and receives selection and timing signal Comi. A fourth conductive pad36is coupled to column electrode20jand receives data signal Dataj. The dimensions of conductive pads36and the layout of conductive pads36on surface34are particularly imposed by the rules of design of display pixel12i,jand by the method of assembly of display pixels12i,jin display screen10.

FIG.4shows an example of a block diagram of a display pixel12i,jof display screen10. InFIG.4, there has been indicated, above each block, the power supply voltage used to power the electronic components of the blocks.

According to an example, display pixel12i,jcomprises at least three light-emitting diodes, a single light-emitting diode LED being shown inFIG.4. Each light-emitting diode LED is coupled in series with a controllable current source CS, for example comprising a MOS transistor. In the present example, for each light-emitting diode LED, the anode of light-emitting diode LED is for example coupled to the conductive pad36receiving high reference potential Vcc and the cathode of light-emitting diode LED is for example coupled to a terminal of controllable current source CS, the other terminal of controllable current source CS being coupled to the conductive pad36receiving low reference potential Gnd.

Display pixel12i,jfurther comprises a circuit40for driving controllable current source CS. Driver circuit40may particularly comprise electronic components such as MOS transistors. It may be desirable to use a low power supply voltage, lower than 4 V, for example in the order of 1 V or of 1.8 V, to power the electronic components of driver circuit40, this low power supply voltage for example corresponding to the voltage likely to be applied between the power terminals of the MOS transistors. For this purpose, display pixel12i,jcomprises a circuit42(Vdd Generation) for delivering, based on power supply voltage Vcc, a decreased power supply voltage Vdd particularly used for the power supply of driver circuit40. Circuit42for example comprises a voltage divider.

According to an embodiment, detection and timing signal Comi, received at one of the conductive pads36of each display pixel12i,j, is a binary signal alternating between a low state “0” and a high state “1”, the low state corresponding to low reference potential Gnd and the high state “1” corresponding to a low voltage, substantially equal to decreased power supply voltage Vdd. Data signal Datajis a binary signal alternating between a low state “0” and high state “1”, the low state corresponding to low reference potential Gnd and the high state “1” corresponding to a low voltage, substantially equal to decreased power supply voltage Vdd.

Driver circuit40comprises a circuit44(Clk & data separation) coupled to the conductive pad36receiving data signal Datajand delivering, based on data signal Dataj, a clock signal Clk and data Data. Driver circuit40comprises a circuit46(Mode selection) receiving signals Clk and Data, coupled to the conductive pad36receiving selection and timing signal Comi, and configured to deliver signals Clk and Data to a storage circuit48(Color Data registers) or to deliver a PWM signal to a circuit50(LED driver) for controlling the controllable current source CS associated with each light-emitting diode LED. Storage circuit48is configured to store color signals R, G, B representative of the image pixel to be displayed. Circuit50is adapted to controlling the controllable current sources CS coupled to light-emitting diodes LED with signals I_red, I_green, and I_blue, obtained from the R, G, B color signals, and from signal PWM.

As will be described hereafter, to limit the number of conductive pads36per display pixel12i,j, data signals Datajallow both the determination, by each display pixel12i,j, of a clock signal and of the R, G, B color signals representative of the light intensities desired for the radiations at the first, second, and third wavelengths. According to another embodiment, clock signal Clk is obtained from selection and timing signal Comi.

The static power consumption of display pixel12i,jis for a significant part due to electronic components other than the MOS transistors of driver circuit40, particularly the circuit42for delivering decreased power supply voltage Vdd. The current tendency is to increase the number of display pixels12i,jof display screen10. The static power consumption of the display pixels may then become a critical factor. Indeed, for a so-called 4K display screen10, having a resolution of 2,160 by 3,840 display pixels, the static power consumption of display screen10may be greater than 150 W.

It may be envisaged to provide an additional conductive pad36, on each display pixel12i,jin addition to those shown inFIG.3, to supply display pixel12i,jwith an additional high reference potential Vdd, so that decreased power supply voltage Vdd is not generated within display pixel12i,j. However, it may be impossible to add an additional conductive pad36without increasing the lateral dimensions of display pixel12i,j, which may not be desirable.

According to an embodiment according to the invention, decreased voltage Vdd is generated from signals Comiand data signals Dataj. Thereby, the total number of conductive pads36is not modified. Further, the generation of decreased power supply voltage Vdd is no longer performed from Vcc within each display pixel12i,jand the static power consumption of the display screen is decreased. Further, the lateral dimensions of display pixels12i,jmay be unmodified.

FIG.5shows a block diagram of an embodiment of a display pixel12i,j. The display pixel12i,jofFIG.5has the same structure as the display pixel12i,jshown inFIG.4, with the difference that circuit42for delivering decreased power supply voltage Vdd is replaced with a circuit60for delivering decreased power supply voltage Vdd receiving selection and timing signal Comiand data signal Dataj.

FIG.6shows a block diagram of an embodiment of the circuit60for delivering decreased power supply voltage Vdd of the display pixel12i,jofFIG.5. Circuit60comprises a first switch T1coupling the conductive pad36receiving selection and timing signal Comito a node Q of delivery of decreased power supply voltage Vdd and a second switch T2coupling the conductive pad36receiving data signal Datajto node Q. Circuit60comprise a circuit64for delivering a signal GT1for controlling switch T1and a circuit66for delivering a signal GT1for controlling switch T1. Circuit60comprises a capacitor C having a plate coupled, preferably connected, to node Q, and a second plate coupled to the conductive pad36receiving low reference signal Gnd. Node Q corresponds to the output of circuit60for delivering decreased voltage Vdd.

Switch T1is on when selection and timing signal Comiis at state “1”, that is, at voltage Vdd, and switch T1is off when selection and timing signal Comiis at state “0”, for example, equal to 0 V. When switch T1is on, capacitor C is charged by voltage Vdd via switch T1. The turning off of switch T1when selection and timing signal Comiis at state “0” prevents a discharge of capacitor C by switch T1. Switch T2may be on when data signal Datajis at state “1”, that is, at voltage Vdd, and switch T2is off when data signal Datajis at state “0”, for example, equal to 0 V. When switch T2is on, capacitor C is charged with voltage Vdd via switch T2. The turning off of switch T2when data signal Datajis at state “0” prevents a discharge of capacitor C by switch T2.

Each switch T1, T2may correspond to a MOS transistor, for example, to an N-channel MOS transistor having its source coupled, preferably connected, to node Q. Signal GT1then corresponds to the voltage for controlling the gate of transistor T1and signal GT2corresponds to the voltage for controlling the gate of transistor T2.

In the embodiment illustrated inFIG.6, circuit64comprises a buffer circuit having its input receiving signal Comiand having its output delivering signal GT1. Circuit64copies at its output the signal Comireceived as an input. Circuit66comprises an AND logic gate having a first input receiving data signal Dataj, having a second input receiving the inverse of selection and timing signal Comi, and having its output delivering signal GT2. Thereby, when selection and timing signal Comiis at state “1”, that is, at voltage Vdd, transistor T1is on and transistor T2is off. Capacitor C is then charged with voltage Vdd via switch T1. When selection and timing signal Comiis at state “0”, for example, equal to 0 V, and data signal Datajis at state “1”, that is, at voltage Vdd, transistor T1is off and transistor T2is on. Capacitor C is then charged with voltage Vdd via switch T2. When selection and timing signal Comiis at state “0”, for example, equal to 0 V, and data signal Datajis at state “0”, for example, equal to 0 V, transistor T1is off and transistor T2is off. Capacitor C does not discharge via transistor T1and transistor T2.

Capacitor C is thus charged to decreased voltage Vdd as soon as one of selection and timing signal Comior of data signal Datajis at state “1”. This enables to use a capacitor C having a decreased capacitance, for example, in the range from 10 fF to 10 pF.

FIG.7shows a block diagram of another embodiment of circuit60for delivering decreased voltage Vdd of the display pixel12i,jofFIG.5. The circuit60shown inFIG.7comprises all the elements of the circuit60shown inFIG.6, with the difference that circuit64corresponds to a conductive track connecting the gate of transistor T1to the drain of transistor T1, transistor T1being thus diode-assembled, and that circuit66corresponds to a conductive track connecting the gate of transistor T2to the drain of transistor T2, transistor T2thus being diode-assembled. The embodiment ofFIG.7is, advantageously, more responsive than the embodiment ofFIG.6.

According to another embodiment, circuit64is not present and switch T1corresponds to a diode having its anode coupled, preferably connected, to the conductive pad36receiving selection and timing signal Comiand having its cathode coupled, preferably connected, to node Q. According to another embodiment, circuit66is not present and switch T2corresponds to a diode having its anode coupled, preferably connected, to the conductive pad36receiving data signal Datajand having its cathode coupled, preferably connected, to node Q.

FIG.8shows a timing diagram of signals received by display pixels12i,jhaving the structure shown inFIG.5for an embodiment of a method of displaying an image on display screen10.

Potentials Vcc and Gnd are substantially constant. The image pixels of a new image to be displayed are successively displayed from the row of rank 1 to the row of rank M. Call frame duration T the duration separating two successive selections of the same row of display screen10. Timing diagrams of signals Com1and Data1will be detailed for the row of rank 1, knowing that the timing diagrams of signals Comiare similar to the timing diagram of signal Com1, although shifted in time. The display of a new image pixel by a display pixel121,j, with j varying from 1 to N, of the row of rank 1 comprises a first phase P1followed by a second phase P2. During phase P1, data signals Datajare transmitted to each display pixel121,jof the row of rank 1, only signal Data1being shown inFIG.8. During second phase P2, the light-emitting diodes of each display pixel121,jare controlled from the R, G, B color signals, determined based on data signals Dataj.

During first phase P1, selection and timing signal Com1is set to state “1”. The setting to state “1” of signal Com1for a long duration is detected by the circuit46of each display pixel121,jof the row of rank 1 and thus enables to select the display pixels121,jof this row, while the display pixels of the other rows are not selected. During first phase P1, data signals Datajare transmitted onto column electrodes20j. For each display pixel121,j, circuit44determines clock signal Clk and data Data based on the pulses of data signal Dataj. As an example, each pulse of data signal Datajmay have a first duration or a second duration, longer than the first duration. Signal Clk may correspond to a sequence of pulses of same durations having their rising edges coinciding, to within a possible constant offset, with the rising edges of the pulses of data signal Dataj. Data Data may correspond to a binary signal at state “0” when the pulse of signal Datajhas the first duration, and at state “1” when the pulse of signal Datajhas the second duration. Circuit46, selected by signal Com1at state “1”, delivers, at the rate of clock signal Clk, the data Data which are stored in circuit50in the form of R, G, B digital signals having their bits provided by the successive values of signal Data. The end of first period P1for a row corresponds to the beginning of first period P1for the next row.

According to an embodiment, the light-emitting diodes of display pixel121,jare controlled by pulse-width modulation or PWM control. For this purpose, during second phase P2, selection and timing signal Com1exhibits the repetition of a succession of pulses at state “1” which are transmitted by the circuit46of each display pixel121,jof the row of rank 1 to circuit50(PWM signal) to clock the operation of circuit50for the control of light-emitting diodes LED by pulse-width modulation. The number of pulses in the succession corresponds to the number of bits of each R, G, and B digital signal. As an example, when current source CS corresponds to a MOS transistor, this transistor is turned on or is turned off, at the rate of the PWM pulses, according to the value “0” or “1” of each bit of R, G, or B color signal, starting by the most significant bit, this transistor being maintained on or off until the next pulse of signal Com1. The duration between two successive pulses of signal Com1is divided each time by two, so that the total duration for which the light-emitting diode is on depends on the value of the R, G, or B color signal. The succession of pulses of signal Com1is repeated until the next first phase P1of the row of rank 1, a single repetition being illustrated as an example inFIG.8.

FIG.9shows a timing diagram of signals received by display pixels12i,jhaving the structure shown inFIG.5for another embodiment of a method of displaying an image on display screen10.

The timing diagrams of signals Vcc, Gnd, and Datajof the embodiment illustrated inFIG.9may be identical to those shown inFIG.8. The signal Comi, i varying from 1 to M, of the embodiment illustrated inFIG.9corresponds to the complementary of the signal Comiof the embodiment illustrated inFIG.8, that is, the signal Comi, i varying from 1 to M, of the embodiment illustrated inFIG.9is at state “1” when the signal Comiof the embodiment illustrated inFIG.8is at state “0” and the signal Comiof the embodiment illustrated inFIG.9is at state “0” when the signal Comiof the embodiment illustrated inFIG.8is at state “1”. For this purpose, pixel12i,jis configured to detect a phase P1when signal Comiis at state “0” for a long time and the pulse width modulation or PWM control is performed during phase P2by pulses of signal Comiat state “0”.

Signal Comiis most often at state “1” in the embodiment described in relation withFIG.9as compared with the embodiment described in relation withFIG.8. This advantageously enables to obtain a more frequent recharging of the capacitor C of circuit60for delivering decreased voltage Vdd, and thus to further decrease the capacitance of capacitor C.

Generally, according to an embodiment, the ratio of the average duration for which at least one of signal Comiand of signal Datajis at decreased voltage Vdd to the sum of the average duration for which signal Comiand signal Datajare at low reference potential Gnd and of the average duration for which at least one of signal Comiand of second signal Datajis at voltage Vdd is greater than 75%, preferably greater than 85%, more preferably greater than 95%.

According to another embodiment, selection circuit22, control circuit24, and circuit26are configured so that, for each display pixel12i,j, there is always one of selection and timing signal Comiand of data signal Datajreceived by display pixel12i,jwhich is at state “1”, that is, at voltage Vdd. In this embodiment, the capacitor C of circuit60for delivering decreased voltage Vdd may then not be present.

FIG.10shows a timing diagram of signals received by display pixels12i,jhaving the structure shown inFIG.5for another embodiment of a method of displaying an image on display screen10.

InFIG.10, timing diagrams of signals Com1, Com2, Com3and Dat1for the rows of rank 1, 2, and 3 and the column of rank 1 have been shown, knowing that the timing diagram of the other signals Comiare similar to the timing diagram of signal Com1although shifted in time. The timing diagrams of signals Vcc, Gnd, not shown, and of the signals Comiof the embodiment illustrated inFIG.10may be identical to those shown inFIG.9. The timing diagrams of the data signals Datajof the embodiment illustrated inFIG.9are identical to those shown inFIG.8with the difference that each phase P1comprises two successive phases P1.1and P1.2. During phase P1.1, each data signal Dataj, j varying from 1 to N, is held at state “1” when one of signals Comi, i varying from 1 to N, is at state “0” for the long duration for the selection of the row of rank i. During the phase P1.2which follows phase P1, data signals Datajare transmitted onto the column electrodes20jand are acquired by the display pixels12i,jof the row of rank i.

This embodiment is particularly adapted in the case where the capacitor C of circuit60for delivering decreased voltage Vdd is not present. Indeed, at any time, for each display pixel12i,j, at least one of the signal Comiand of the data signal Datajreceived by display pixel12i,jis at state “1”, so that node Q permanently delivers voltage Vdd, even if capacitor C is not present.

In the previously-described embodiments, the light-emitting diodes LED of display pixel121,jare controlled by pulse-width modulation. However, the control of the light-emitting diodes LED of display pixel121,jmay be different from a control by pulse-width modulation. According to an embodiment, the control of light-emitting diodes LED is a current level control.

FIG.11shows an embodiment of current source CS where current source CS comprises N elementary controllable current sources CS1to CSN, where N is an integer greater than or equal to 2. Preferably, N is equal to the number of bits of the R, G, or B digital color signal. In the present embodiment, elementary current sources CSj, j varying from 1 to N, are assembled in parallel between a node A1and a node A2. When the light-emitting diodes LED are assembled with a common anode, as shown inFIG.4or5, for each color, node A1is coupled, preferably connected, to the cathode of the light-emitting diode LED corresponding to the considered color, and node A2is coupled, preferably connected, to the conductive pad36coupled to the source of low reference potential Gnd. When the light-emitting diodes LED are assembled with a common cathode, node A1is coupled, preferably connected, to the conductive pad36coupled to the source of high reference potential Vcc and, for each color, node A2is coupled, preferably connected, to the anode of the light-emitting diode LED corresponding to the considered color.

Each elementary current source CSjis activated or deactivated by circuit50by means of a control signal Cj. As an example, control signal Cjis a binary signal corresponding to the bit of rank j of the R, G, or B digital color signal. Elementary current source CSjis off when signal Cjis in a first state, for example, the low state, and current source CSjis activated when signal Cjis in a second state, for example, the high state.

The larger the number of current sources CSjwhich are activated, the higher the intensity of current ICS. According to an embodiment, current source CS is capable of supplying a current ICS having an intensity at a level from among a plurality of constant levels and having its level depending on the number of general light-emitting diodes which are conductive. The currents supplied by the elementary current sources CS1of current source CS may be identical or different. According to an embodiment, each elementary current source CSjis capable of supplying a current of intensity I*2j−1. Current source CS is then adapted to supplying a current having an intensity ICS which may, according to control signals Cj, take any value k*I, with k varying from 0 to 2M−1.

According to an embodiment, the control of light-emitting diodes LED is an analog control.

FIG.12shows an embodiment of current source CS where the current source comprises a MOS transistor T assembled in series with a resistor Rs between nodes A1and A2, nodes A1and A2being defined as previously in relation withFIG.11. Current source CS further comprises a digital-to-analog converter DAC receiving the R, G, or B digital color signal and an operational amplifier having its inverting input (−) coupled, preferably connected, to the midpoint between resistor Rs and the MOS transistor and having its non-inverting input (+) receiving the analog signal delivered by digital-to-analog converter DAC. Transistor T is made more or less conductive according to the R, G, or B digital color signal transmitted to digital-to-analog converter DAC.

Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants may be combined, and other variants will occur to those skilled in the art. In particular, the PWM modulation may be internally generated in the control circuit30of display pixel12i,jto avoid using signal Comito generate it. Other embodiments may also not use a PWM modulation but a linear driving of light-emitting diode LED. Other embodiments may also use other electro-optical components such as organic light-emitting diodes.

Finally, the practical implementation of the described embodiments and variations is within the abilities of those skilled in the art based on the functional indications given hereabove. In particular, as concerns the second embodiment described inFIG.5, it may be advantageous to use SOI-type (Silicon on Insulator) structures to facilitate the management of negative voltages.