Patent ID: 12191845

DESCRIPTION OF EMBODIMENTS

Hereinafter, embodiments of the present invention will be described with reference to accompanying drawings.

EMBODIMENTS

First Embodiment

FIG.1is a diagram illustrating a load drive device1according to a first embodiment of the present invention.

InFIG.1, the load drive device1includes a first transistor10, an active clamp circuit20, a second transistor30, a buffer circuit50, a resistor60, and a trigger circuit100.

The first transistor10is connected between a first control electrode10E and an inductive load40. Then, the first transistor10has a gate connected to the first control electrode10E, a source connected to GND, and a drain connected to a second control electrode2CE.

The active clamp circuit20has one end connected to the first control electrode10E and the other end connected to the second control electrode2CE. Then, when a differential voltage between the second control electrode2CE and the first control electrode10E exceeds a certain threshold larger than a battery voltage VBAT, the active clamp circuit20causes a current corresponding to the differential voltage to flow through an output resistance of the buffer circuit50. This means that the active clamp circuit20causes10E current to flow from the second control electrode2CE to the first control electrode when a terminal voltage of the second control electrode2CE between the first transistor10and the inductive load40exceeds a threshold.

The second transistor30is connected to the second control electrode2CE and connected in parallel to the first transistor10. Then, the second transistor30has a gate connected to a third control electrode3CE, a source connected to GND, and a drain connected to one end of the resistor60. Further, the second transistor30is arranged to have an interval for securing heat dissipation performance from the first transistor10.

The buffer circuit50is connected to the first transistor10via the first control electrode10E in order to drive the first transistor10, and receives an input of an input signal for driving the inductive load40. Further, an output terminal of the buffa circuit50is connected to the first control electrode10E. Further, the buffer circuit50has a finite output resistance component, and a release voltage thereof is set to a value (hereinafter, a value sufficient for turning on the transistor is referred to as a gate Hi-level) that is sufficient to turn on the first transistor10when the input signal is equal to or more than a predetermined threshold (hereinafter, referred to as an input Hi-level).

Further, the release voltage of the buffer circuit50is set to a value (hereinafter, a value sufficient to turn off the transistor is referred to as a gate Lo-level) that is sufficient to turn off the first transistor10when the input signal is equal to or less than a predetermined threshold (hereinafter, referred to as an input Lo-level).

The resistor60is connected in series to the second transistor30, and has the one end connected to the drain of the second transistor30and the other end connected to the second control electrode2CE. Further, the resistor60is arranged to have an interval from the first transistor10to secure the heat dissipation performance.

The trigger circuit100(a first trigger output circuit) outputs a trigger signal from a time point at which the input signal with respect to the buffer circuit50is switched from ON to OFF. Then, the conduction of the second transistor30is controlled by the trigger signal output from the trigger circuit100. The trigger circuit100receives an input of the same input signal as the input signal with respect to the buffer circuit50, and has an output terminal connected to the gate of the second transistor30via the third control electrode3CE. The trigger circuit100outputs a signal of the gate Hi-level for turning on the second transistor30only for a predetermined time from a time point at which the input signal with respect to the trigger circuit100transitions from the input Hi-level to the input Lo-level. At the other time points, the trigger circuit100outputs a signal of the gate Lo-level for turning off the second transistor30. That is, the trigger circuit100, which is a second transistor control signal output unit, turns on the second transistor at a timing when the first transistor10is turned off.

Further, the inductive load40has one end connected to the battery voltage VBAT and the other end connected to the second control electrode2CE.

Next, the operation of the device illustrated inFIG.1will be described with reference toFIG.2.

FIG.2is an example of a timing chart for describing the operation of the device illustrated inFIG.1, and illustrates a temporal change of the load drive device1that starts from an OFF state, transitions to an ON state, and then, returns to the OFF-state again through a clamp period in which an active clamp operation is performed.

Here, the OFF state of the load drive device1is a state in which no current flows through the induced load40in the following description, and refers to a state in which voltages of the first control electrode10E and the third control electrode3CE are sufficiently low. That is, the OFF state of the load drive device is a state in which the first transistor10and the second transistor30are turned off, and the active clamp circuit20is not conductive. Therefore, the voltage of the second control electrode2CE is in a state of being raised to the battery voltage VBAT connected to the induced load40in the OFF state of the load drive device1.

Further, the ON state of the load drive device1is a state of being conductive to cause a current to flow through the induced load40, and refers to a state in which the voltage of the first control electrode10E is at the gate Hi-level. That is, the ON state of the load drive device1is a state in which the first transistor10is turned on and the second transistor30is turned off. Therefore, the voltage of the second control electrode2CE is in the state of being lower than the battery voltage VBAT in the ON state of the load drive device1.

Further, the clamp period is a transient period generated when the load drive device1transitions from the ON state to the OFF state. That is, the clamp period refers to a state in which the second control electrode2CE rises from a state of being lower than the battery voltage VBAT to a voltage higher than the battery voltage VBAT due to the release of energy, stored in the inductive load40, through an internal circuit of the load drive device1in the ON state of the load drive device1, and thereafter, settles at a voltage level in the OFF state.

The maximum voltage value of the second control electrode2CE at this time is clamped to be equal to or lower than a certain value by conduction of the active clamp circuit20, and is thus referred to as the clamp period. During this period, the amount of current flowing through the induced load40changes to the OFF state.

InFIG.2, T10is a time when the input signal is turned on, and T11is a time when the input signal is turned off. Further, T12is an operation start time of the active clamp circuit20, and T13is an interruption time of the second transistor30. Further, T14is an operation end time of the active clamp circuit20, and CLAMP is a clamp operation period caused by conduction of the active clamp circuit20.

First, it is considered that the input signal input to the load drive device1is switched from the input Lo-level to the input Hi-level at time T10illustrated inFIG.2.

At this time, the active clamp circuit20is not conductive, the voltage of the first control electrode10E becomes the gate Hi-level of the first transistor10by the buffer circuit50, and the first transistor10is turned on. As a result, the voltage of the second control electrode2CE is dropped with respect to the GND level, and a drain current starts to flow through the first transistor10.

At this time point, an output of the trigger circuit100is the gate Lo-level of the second transistor30, and thus, the second transistor30is maintained off, and no current flows through the second transistor30.

Next, it is considered that the input signal is switched from the input Hi-level to the input Lo-level at time T11.

First, from time T11to time T12when the clamp period starts, the active clamp circuit20is not conductive, the voltage of the first control electrode10E becomes the gate Lo-level by the buffer circuit50, and the first transistor10is turned off.

On the other hand, the voltage of the third control electrode3CE becomes the gate Hi-level of the second transistor30by the trigger circuit100so that the second transistor30is turned on. At this time, the drain current flowing through the second transistor30is determined from a series resistance value of the resistor60and the second transistor30and a voltage value of the second control electrode2CE. If this is set to be smaller than the amount of current flowing through the load drive device1at a time point in time T11, the voltage of the second control electrode2CE continues to rise beyond the battery voltage VBAT.

Then, at time T12, the voltage of the second control electrode2CE exceeds a certain threshold of the active clamp circuit20, and the active clamp circuit20becomes conductive. When the active clamp circuit20becomes conductive, the current flows through the output resistance component of the buffer circuit50, and the voltage of the first control electrode10E rises. Eventually, the first transistor10becomes conductive such that the voltage of the second control electrode2CE reaches a peak at a constant value.

At this time point, the first transistor10consumes the maximum instantaneous power. At the same time, however, the second transistor30is turned on, and thus, part of energy released from the inductive load40is distributed to the second transistor30and the resistor60. Therefore, heat generation is not concentrated and is dispersed to the respective parts.

Finally, at time T13, the output of the trigger circuit100ends and is lowered to the gate Lo-level of the second transistor30. Here, a path of the second transistor30is interrupted, and thereafter, the entire remaining energy starts to be consumed in the first transistor10, the current flowing through the load becomes zero at time T14, and the clamp period ends.

Through the above operation, the power consumption is distributed to the first transistor10, the second transistor30, and the resistor60from time T12at which the instantaneous power consumption is the highest to time T13during the clamp period.

Therefore, the heat generation is dispersed without being concentrated, and a local peak temperature can be lowered. Thus, an operation temperature range can be widened as a whole.

In particular, the second transistor30and the resistor60do not need to be connected with a low resistance as compared with the first transistor10that has a low resistance when turned on but has a high resistance when turned off. Therefore, the arrangement away from a heat source is possible, and thus, the heat dissipation efficiency can be improved as compared with the first transistor10. In this case, the peak temperature can be suppressed with a smaller area as compared with a case of simply widening the area of the first transistor10.

According to the first embodiment of the present invention, it is possible to achieve the load drive device capable of suppressing local concentration of temperature at the time of absorbing a counter electromotive force of the inductive load while suppressing a size of a power transistor.

Second Embodiment

Next, a second embodiment of the present invention will be described.

FIG.3is a diagram illustrating a load drive device2according to the second embodiment.

InFIG.3, the load drive device2includes an active clamp circuit21and a trigger circuit200.

A difference between the first embodiment and the second embodiment is a connection point of the trigger circuit100and a connection point of the trigger circuit200. The other configurations have the same functions as the configurations denoted by the same reference signs illustrated inFIG.1described above, and thus, the description thereof will be omitted.

In the active clamp circuit21, a first terminal1T (connected to an anode of a Zener diode) is connected to the first control electrode10E, a second terminal2T (connected to an anode of a diode) is connected to the second control electrode2CE, and a third terminal3T (connected to a connection point between the diode and the Zener diode) is connected to an input terminal of the trigger circuit200.

Then, when a differential voltage between the second control electrode2CE and the first control electrode10E exceeds a certain threshold larger than the battery voltage VBAT, the active clamp circuit21causes a current corresponding to the differential voltage to flow to the second terminal2T. Further, the third terminal3T is an intermediate node between the first terminal1T and the second terminal2T.

The trigger circuit200(a second trigger output circuit) outputs a trigger signal from a time point at which the active clamp circuit21becomes conductive. The conduction of the second transistor30is controlled by the trigger signal output from the trigger circuit200. The trigger circuit200has the input terminal connected to the third terminal3T of the active clamp circuit21and an output terminal connected to the third control electrode3CE. Then, the trigger circuit200outputs the gate Hi-level of the second transistor30only for a predetermined time when a voltage of the input terminal exceeds a predetermined threshold voltage, and outputs the gate Lo-level of the second transistor30at the other time points.

Here, the predetermined threshold voltage is set to a voltage level of the third terminal3T only when the active clamp circuit21is conductive. Therefore, it is assumed that the output of the trigger circuit200is switched simultaneously with the conduction of the active clamp circuit21.

Hereinafter, the operation of the device illustrated inFIG.3will be described with reference toFIG.4.

FIG.4is an example of a timing chart for describing the operation of the device illustrated inFIG.3. InFIG.4, T10is a time when the input signal is turned on, and T11is a time when the input signal is turned off. Further, T12is an operation start time of the active clamp circuit21, and T20is an interruption time of the second transistor30. Further, T14is an operation end time of the active clamp circuit20, and CLAMP is a clamp operation period caused by conduction of the active clamp circuit21.

A difference between the second embodiment and the first embodiment is the operation after time T11.

InFIG.4, the voltage of the third control electrode3CE is maintained at the gate Lo-level of the second transistor30by the trigger circuit200while the active clamp circuit21is not conductive from time T11to time T12. Then, both the first transistor10and the second transistor30are turned off. During this period, the voltage of the second control electrode2CE rises. Note that a load current during this period is mainly used for the voltage rise due to charging of a capacitive component of the second control electrode2CE, and thus, power consumption is small, and heat generation can be ignored.

At time T12, the active clamp circuit21becomes conductive, and the voltage of the second control electrode2CE is clamped to be equal to or lower than a certain value. At this time point, the first transistor10consumes the maximum instantaneous power. However, the second transistor30is turned on from this time point, and thus, part of energy released from the inductive load40is distributed to the second transistor30and the resistor60. Therefore, heat generation is not concentrated and is dispersed to the respective parts.

Finally, at time T20, the output of the trigger circuit200ends and is lowered to the gate Lo-level of the second transistor30. Here, a path of the second transistor30is interrupted, and thereafter, the entire remaining energy starts to be consumed in the first transistor10, the current flowing through the inductive load40becomes zero at time T14, and the clamp period ends.

Through the above operation, the second embodiment can obtain the same effects as those of the first embodiment. In addition, it is possible to achieve the load drive device capable of reliably distributing the heat generated by the maximum power during the clamp period regardless of the time until the active clamp circuit21operates.

Third Embodiment

Next, a third embodiment of the present invention will be described.

FIG.5is a circuit diagram illustrating a load drive device3according to the third embodiment.

InFIG.5, the load drive device3includes a voltage amplifier (voltage amplifier circuit)300and a reference voltage source310.

The third embodiment is different from the first embodiment in that the trigger circuit100is omitted and the voltage amplifier300and the reference voltage source310are added. The other configurations have the same functions as the configurations denoted by the same reference signs illustrated inFIG.1described above, and thus, the description thereof will be omitted.

The voltage amplifier300compares a voltage of the second control electrode2CE with a predetermined voltage threshold. Then, the voltage amplifier300outputs a voltage level obtained by amplifying a differential voltage between the voltage of the second control electrode2CE and the predetermined voltage threshold. The conduction of the second transistor30is controlled by the voltage level amplified by the voltage amplifier300.

In the voltage amplifier300, a first input terminal (non-inverting input terminal) is connected to the second control electrode2CE, a second input terminal (inverting input terminal) is connected to an output terminal of the reference voltage source310, and an output terminal is connected to the third control electrode3CE. Then, the voltage amplifier300outputs a voltage corresponding to a differential voltage between the first input terminal and the second input terminal from the output terminal.

Further, the maximum voltage that can be output from the voltage amplifier300is equal to or higher than the gate Hi-level of the second transistor30, and the minimum voltage that can be output is equal to or lower than the gate Lo-level of the second transistor30.

The reference voltage source310has an output terminal (positive terminal) connected to the second input terminal (inverting input terminal) of the voltage amplifier300and a reference terminal (negative terminal) connected to a reference potential (GND). Then, the reference voltage source310applies a predetermined voltage VREF between the output terminal and the reference terminal. Further, the voltage VREF is set to a value lower than a certain threshold at which the active clamp circuit20becomes conductive.

Hereinafter, the operation of the device illustrated inFIG.5will be described with reference toFIG.6.

FIG.6is an example of a timing chart for describing the operation of the load drive device3illustrated inFIG.5.

A difference from the second embodiment is the operation after time T30.

At time T30, when the voltage of the second control electrode2CE exceeds the voltage VREF of the reference voltage source310, the voltage of the third control electrode3CE becomes equal to or higher than the gate Hi-level of the second transistor30by the voltage amplifier300, and the second transistor30is turned on.

Next, at time T12, the active clamp circuit20becomes conductive, and the voltage of the second control electrode2CE is clamped to be equal to or lower than a certain value. At this time point, the first transistor10consumes the maximum instantaneous power. At the same time, however, the second transistor30is turned on, and thus, part of energy released from the induced load40is distributed to the second transistor30and the resistor60.

Thereafter, at time T31, the active clamp circuit20stops the operation at a time point at which the current flowing through the first transistor10decreases to such an extent that it is difficult to maintain a clamp voltage. As a result, the voltage of the second control electrode2CE decreases to VREF. At this time point, the voltage of the second control electrode2CE is maintained at the voltage VREF by the voltage amplifier300.

Finally, the current flowing through the second transistor30decreases from time T31to time T32, and the clamp period ends.

Through the above operation, it is possible to disperse heat generation over the entire period during the active clamp operation in which the power consumption is high, and to achieve the load drive device capable of suppressing local concentration of temperature at the time of absorbing a counter electromotive force of the inductive load while suppressing a size of a power transistor according to the third embodiment, which is similar to the first embodiment.

Fourth Embodiment

Next, a fourth embodiment of the present invention will be described.

FIG.7is a diagram illustrating a load drive device4, a control unit (CPU)400, and a storage unit410according to the fourth embodiment.

The fourth embodiment is different from the first embodiment in that the trigger circuit100is omitted and the control unit400and the storage unit410are added. The other configurations have the same functions as the configurations denoted by the same reference signs illustrated inFIG.1described above, and thus, the description thereof will be omitted.

In the example illustrated inFIG.7, the control unit400and the storage unit410are illustrated as devices separate from the load drive device4, but the control unit400and the storage unit410can be provided in the load drive device4.

InFIG.7, an input signal to the buffer circuit50is output from a first output terminal400-1OT of the control unit400, and a second output terminal400-2OT is connected to the third control electrode3CE. Then, a drive command for controlling the load drive device4is input to an input terminal400IT of the control unit400. Further, the control unit400is connected to the storage unit410.

Then, the control unit400can control a voltage switching timing of the first output terminal400-1OT and the second output terminal400-2OT according to a setting value stored in the storage unit410. Further, voltages of the first output terminal400-1OT and the second output terminal400-2OT of the control unit400can be set to the gate Hi-level or the gate Lo-level.

The control unit400controls the conduction of the inductive load40. The control unit400outputs a trigger signal corresponding to an inductance value of the inductive load40, a resistance value, a value of the battery voltage VBAT, and a clamp voltage value from a time point at which the interruption of the inductive load40is started. The conduction of the second transistor30is controlled by the trigger signal output from the control unit400.

Here, first, a temporal change of a current flowing through the induced load40during the operation of the active clamp circuit20will be described with reference toFIG.8prior to the description regarding the voltage switching timing of the control unit400.

FIG.8is a graph illustrating changes of a voltage and a current during the operation of the active clamp circuit20when the impedance of the inductive load40in the load drive device illustrated inFIG.7is regarded as a series model of a component of inductance L and a component of resistance R.

InFIG.8, T41is a time when the active clamp circuit20starts to conduct, and the load current at this time point is set as i0.

Further, T42is a time when the active clamp circuit20ends the operation, and the load current at this time point is set as 0.

T40is a time when reaching an arbitrarily specified current value i40. Assuming that time taken from time T41to T40is T, T is expressed by the following Formula (1).
T=(L/R)log((i0+ie)/(i40+ie))  (1)

The load current i0in the above Formula (1) is a steady-state current flowing through the inductive load40after a lapse of sufficient time in the ON state of the load drive device4, and can be expressed by the battery voltage VBAT and R as in the following Formula (2).
i0=VBAT/R(2)

Further, Iein the above Formula (1) can be expressed by the following Formula (3), and is an absolute value of a convergence value when it is assumed that the voltage of the second control electrode2CE is set to a clamp voltage VC (voltage clamped by the active clamp circuit20) for the infinite time, and is one of parameters for calculating T.
Ie=(VC−VBAT)/R(3)

Assuming that the amount of current flowing through a path (the inductive load40→the resistor60→the second transistor30→GND) of the second transistor30during the clamp period is i40, the maximum use is possible until time T40inFIG.8. Then, T (between times T41and T40) can be calculated using the above Formulas (1) to (3). T has L, R, VC, and VBAT as parameters, and it is possible to determine how long the second transistor30can be turned on if values of L, R, VC, and VBAT are known in advance.

Hereinafter, the operation of the device illustrated inFIG.7will be described with reference toFIG.9.

FIG.9is an example of a timing chart for describing the operation of the device illustrated inFIG.7.

First, as a precondition, it is assumed that the respective values of L, R, VC, and VBAT are written in the storage unit410. Further, the control unit400reads the respective values in the storage unit410to calculate the time T.

First, it is considered that the drive command (a drive signal) input to the control unit400is switched from the input Lo-level to the input Hi-level at time T44.

When receiving the drive signal, the control unit400switches the input signal with respect to the buffa circuit50, output from the first output terminal400-1OT, from the input Lo-level to the output Hi-level at time T10. The voltage of the second output terminal400-2OT is at the gate Lo-level, and the voltage of the third control electrode3CE is maintained at the gate Lo-level. The same operation as that in the first embodiment is performed from time T10to time T45.

Next, when the drive signal is switched to the input Lo-level at time T45, in response to this, the control unit400switches the input signal with respect to the buffer circuit50to the input Lo-level at time T11. At the same time, the voltage of the second output terminal400-2OT is set to the gate Hi-level. That is, the voltage of the third control electrode3CE is switched to the gate Hi-level.

Thereafter, the voltage of the second control electrode2CE is clamped at T12, and the voltage of the second output terminal400-2OT is controlled at T46, so that the third control electrode3CE is switched to the gate Lo-level, and the second transistor30is turned off. At this time, a time difference from T11to T46is determined by T calculated above.

Finally, the clamp period ends at T14.

Through the above operation, the same effects as those of the first embodiment can be obtained according to the fourth embodiment. In addition, it is possible to set an energy consumption period according to an individual load (the resistance R and the inductance L of inductive load40) to be connected, and to achieve the load drive device capable of dispersing heat generation using the second transistor30to the maximum without affecting the clamp operation.

That is, the energy consumption period is limited to a situation in which destruction is likely to occur by heat according to the fourth embodiment, so that it is possible to achieve the load drive device capable of dispersing the heat generation if necessary while suppressing excessive degradation of components.

Note that a configuration of a low-side driver has been described as all the load drive devices in the above first to fourth embodiments, but a high-side driver may be similarly adopted, and the invention is not limited thereto.

Since the trigger circuits100and200, the voltage amplifier300, and the control unit400in the above first to fourth embodiments control on/off of the second transistor30, the trigger circuits100and200, the voltage amplifier300, and the control unit400can be collectively referred to as the second transistor control signal output unit that turns on the second transistor30at a timing when one transistor10is turned off.

Note that the present invention is not limited to the above-described embodiments, but includes various modifications.

For example, the above-described embodiments have been described in detail in order to describe the invention in an easily understandable manner, and are not necessarily limited to those including the entire configuration that has been described above.

That is, a load drive device, provided with the first transistor10connected between the first control electrode10E and the inductive load40, the active clamp circuit20that becomes conductive when a terminal voltage of the second control electrode2CE between the first transistor40and the inductive load40exceeds a threshold, and the second transistor30connected to the second control electrode2CE and connected in parallel to the first transistor10, is also included in the embodiments of the present invention.

As the voltage of the second control electrode2CE exceeds a certain threshold of the active clamp circuit20, the active clamp circuit20becomes conductive. When the active clamp circuit20is conductive, a voltage of the first control electrode10E rises. Then, the first transistor10becomes conductive such that the voltage of the second control electrode2CE reaches a peak at a constant value. As a result, power is consumed by the first transistor10. Accordingly, the above example is also included in the present invention.

Further, a load drive device, provided with the first transistor10connected between the first control electrode10E and the inductive load40, the second transistor30connected to the second control electrode2CE and connected in parallel to the first transistor10, and the second transistor control signal output unit (the trigger circuit100or200, the voltage amplifier300, or the control unit400) that turns on the second transistor30at a timing when the first transistor10is turned off, is also included in the embodiments of the present invention. The second transistor control signal output unit is a general term for the trigger circuits100and200, the voltage amplifier300, and the control unit400. Accordingly, the second transistor control signal output unit may be any of the trigger circuits100and200, the voltage amplifier300, and the control unit400.

Even in a case where the active clamp circuit (20or21), the buffer circuit50, and the resistor60do not exist, power is consumed by the second transistor30by turning on the second transistor30at the timing when the first transistor10is turned off. Accordingly, the above example is also included in other embodiments of the present invention.

Further, in the other embodiments described above, the following examples are also included in the present invention.

In the other embodiments described above, the buffer circuit10, which is connected to the first transistor10via the first control electrode10E, receives an input signal for driving the inductive load40, and drives the first transistor10, is provided.

Further, in the other embodiments described above, the resistor60connected in series to the second transistor30is provided.

Further, in the other embodiments described above, the second transistor control signal output unit is a first trigger output circuit (trigger output circuit100) that outputs a trigger signal from a time point at which the input signal of the buffer circuit is switched from on to off, and conduction of the second transistor30is controlled by the trigger signal.

Further, in the other embodiments described above, the active clamp circuit21, which causes a current to flow from the second control electrode2CE to the first control electrode10E when a terminal voltage of the second control electrode2CE between the first transistor10and the inductive load40exceeds a threshold, is provided, the second transistor control signal output unit is a second trigger output circuit (trigger output circuit200) that outputs a trigger signal from a time point at which the active clamp circuit21becomes conductive, and the conduction of the second transistor30is controlled by the trigger signal.

Further, in the other embodiments described above, the second transistor control signal output unit is the voltage amplifier circuit300that compares the voltage of the second control electrode2CE with a predetermined voltage threshold, the voltage amplifier circuit300outputs a voltage level obtained by amplifying a differential voltage between the voltage of the second control electrode2CE and the voltage threshold, and the conduction of the second transistor30is controlled by the amplified voltage level.

Further, in the other embodiments described above, the second transistor control signal output unit is a control unit that controls the conduction of the inductive load40, the control unit outputs a trigger signal according to an inductance value of the inductive load40, a resistance value, a battery voltage value, and a clamp voltage value from a time point at which the interruption of the inductive load40is started, and the conduction of the second transistor30is controlled by the trigger signal.

Further, in the other embodiments described above, the active clamp circuit20, which causes a current to flow from the second control electrode2CE to the first control electrode10E when a terminal voltage of the second control electrode2CE between the first transistor10and the inductive load40exceeds a threshold, is provided. The embodiments of the present invention also includes the example in which the active clamp circuit20that performs the operation of the first embodiment is provided in the other embodiments described above.

Further, some configurations of a certain embodiment can be substituted by configurations of another embodiment, and further, a configuration of another embodiment can be also added to a configuration of a certain embodiment.

Further, addition, deletion or substitution of other configurations can be made with respect to some configurations of each embodiment.

Further, the signal polarity described in the timing chart is an example, and the invention is not limited thereto.

Further, a part or all of each of the above-described configurations, functions, processing units, processing means, and the like may be implemented by, for example, hardware designed with one integrated circuit and the like or by a plurality of integrated circuits.

REFERENCE SIGNS LIST

1,2,3,4load drive device1CE first control electrode1T first terminal2CE second control electrode2T second terminal3CE third control electrode3T third terminal10first transistor20,21active clamp circuit30second transistor40inductive load50buffer circuit60resistor100,200trigger circuit300voltage amplifier310reference voltage source400control unit400IT input terminal400-1OT first output terminal400-2OT second output terminal