Patent ID: 12218657

DETAILED DESCRIPTION

In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail with reference to the drawings and specific embodiments.

For the convenience of the following description, the high level and the low level defined below are technical concepts or terms well known in the field of analog circuits or digital circuits. For example, the high level may be a voltage of 5V, 12V or 24V, and the low level may be a voltage of less than IV or a negative voltage lower than a logical or actual ground voltage.

FIG.4is a block diagram of a driver for parallel switching transistors according to a preferred embodiment of the present invention. As shown inFIG.4, a driver4is substantially the same as a driver shown inFIG.3, except that the driver4further includes an auxiliary Miller clamping circuit401, an auxiliary Miller clamping circuit402and an auxiliary Miller clamping circuit403, wherein the auxiliary Miller clamping circuit401is connected between a gate of a switching transistor Q41and a Miller clamping terminal CLAMP of a built-in Miller clamping circuit431of a driver chip43; the auxiliary Miller clamping circuit402is connected between a gate of a switching transistor Q42and the Miller clamping terminal CLAMP of the Miller clamping circuit431; and the auxiliary Miller clamping circuit403is connected between a gate of a switching transistor Q43and the Miller clamping terminal CLAMP of the Miller clamping circuit431. A direct-current (DC) power supply42is used for providing the same DC voltage to the auxiliary Miller clamping circuit401and a driving power amplification device411, providing the same DC voltage to the auxiliary Miller clamping circuit402and a driving power amplification device412, and providing the same DC voltage to the auxiliary Miller clamping circuit403and a driving power amplification device413.

When a pulse width modulation signal PWM output by an output terminal OUT of the driver chip43is at a high level, the driving power amplification devices411,412and413respectively power amplify the pulse width modulation signal PWM to output pulse width modulation driving signals, and the pulse width modulation driving signals are output to the gates of the switching transistors Q41, Q42and Q43through driving resistors Rg41, Rg42and Rg43respectively, thereby controlling the switching transistors Q41, Q42and Q43to be turned on.

When the pulse width modulation signal output by the output terminal OUT of the driver chip43is at a low level, the driving power amplification devices411,412and413respectively output the low level to the switching transistors, and Miller currents generated by the switching transistors Q41, Q42and Q43are output to the gates of the switching transistors Q41, Q42and Q43through parasitic Miller capacitors (not shown inFIG.4). At this time, when the built-in Miller clamping circuit431is triggered for Miller clamping, conduction paths are formed in the auxiliary Miller clamping circuits401,402and403, so that the Miller currents generated by the switching transistors Q41. Q42and Q43flow from the gates of the switching transistors Q41, Q42and Q43to low-level DC voltages through the auxiliary Miller clamping circuits401,402and403respectively.

A current path of the Miller currents is not formed between the gate and source of each of the switching transistors Q41, Q42and Q43, so the switching transistors Q41, Q42and Q43are kept in a cut-off state and may not be turned on accidentally. Therefore, an auxiliary Miller clamping device40of the present invention may be used for performing Miller clamping on a plurality of parallel switching transistors.

The auxiliary Miller clamping circuits401,402and403isolate the gates of the switching transistors Q41. Q42and Q43from one another, thus avoiding the damage of the switching transistors caused by asynchronous ON/OFF of the switching transistors Q41, Q42and Q43.

On a circuit board, the auxiliary Miller clamping circuits401,402and403may be arranged close to the switching transistors Q41, Q42and Q43respectively, thereby shortening the current paths of the Miller currents generated by the switching transistors Q41, Q42and Q43and improving the Miller clamping performance.

FIG.5is a circuit diagram of a driver for parallel switching transistors according to a second embodiment of the present invention. As shown inFIG.5, a driver5includes driving power amplification devices511,512and513, and a Miller clamping device50. The Miller clamping device50includes a driver chip53and auxiliary Miller clamping circuits501,502and503. An output terminal OUT of the driver chip53is connected to input terminals of the driving power amplification devices511,512and513; the auxiliary Miller clamping circuit501is connected between a Miller clamping terminal CLAMP of a built-in Miller clamping circuit531of a driver chip53and a gate of an MOSFET Q51; the auxiliary Miller clamping circuit502is connected between the Miller clamping terminal CLAMP of the built-in Miller clamping circuit531and a gate of an MOSFET Q52; and the auxiliary Miller clamping circuit503is connected between the Miller clamping terminal CLAMP of the built-in Miller clamping circuit531and a gate of an MOSFET Q53.

A DC power supply (not shown inFIG.5) provides a high-level DC voltage Vdd1and a low-level DC voltage Vss1to each of the driving power amplification device511and the auxiliary Miller clamping circuit501, provides a high-level DC voltage Vdd2and a low-level DC voltage Vss2to each of the driving power amplification device512and the auxiliary Miller clamping circuit502, and provides a high-level DC voltage Vdd3and a low-level DC voltage Vss3to each of the driving power amplification device513and the auxiliary Miller clamping circuit503. Voltage values of the high-level DC voltages Vdd1, Vdd2and Vdd3are equal, and voltage values of the low-level DC voltages Vss1, Vss2and Vss3are equal.

The auxiliary Miller clamping circuits501,502and503have the same circuit structure. Here, only the auxiliary Miller clamping circuit501is taken as an example for introduction. The auxiliary Miller clamping circuit501includes a PNP-type triode T51, a resistor R51, a resistor R52, a capacitor C51, a diode D51and a diode D52, wherein the capacitor C51is connected between an emitter and a base of the PNP-type triode T51; the resistor R51is connected between the Miller clamping terminal CLAMP of the built-in Miller clamping circuit531and an emitter of the PNP-type triode T51; the resistor R52is connected between the Miller clamping terminal CLAMP of the built-in Miller clamping circuit531and the base of the PNP-type triode T51; a collector of the PNP-type triode T51is connected to the low-level DC voltage Vss1; a node formed by connecting a positive electrode of the diode D51with a positive electrode of the diode D52is connected to the gate of the MOSFET Q51, a negative electrode of the diode D51is connected to the high-level DC voltage Vdd1, and a negative electrode of the diode D52is connected to the emitter of the PNP-type triode T51.

The driving power amplification devices511,512and513have the same circuit structure. Here, only the driving power amplification device511is taken as an example for introduction. The driving power amplification device511includes an NPN-type triode T52and a PNP-type triode T53as well as capacitors C52, C53and C54, wherein the NPN-type triode T52and the PNP-type triode T53are connected into a push-pull structure, that is, a base of the NPN-type triode T52and a base of the PNP-type triode T53are both connected to the output terminal OUT of the driver chip53; a collector of the NPN-type triode T52is connected to the DC voltage Vdd1; a collector of the PNP-type triode T53is connected to the DC voltage Vss1; and a node formed by connecting an emitter of the PNP-type triode T53with an emitter of the NPN-type triode T52is used as a gate output terminal of the driving power amplification device511. One ends of the capacitors C52, C53, C54are connected with each other to serve as a source output terminal S of the driving power amplification device511, and the other ends are connected to the DC voltages Vdd1. Vss1and the gate output terminal G respectively. The capacitors C52, C53, and C54are used for voltage stabilization, which prevents the high level of the pulse width modulation drive signal output by the driving power amplification device511from decreasing.

When the pulse width modulation signal output by the output terminal OUT of the driver chip53is at a high level (i.e., greater than a turn-on voltage of a triode), the NPN-type triode T52is turned on, and the PNP-type triode T53is cut off. At this time, a voltage of the gate output terminal G of the driving power amplification device511is equal to or slightly smaller than the DC voltage Vdd1, and the current is greater than a base current, so the high level output by the driving power amplification device511controls the MOSFET Q51to be turned on.

When the pulse width modulation signal output by the output terminal OUT of the driver chip53is at a low level (i.e., less than the turn-on voltage of the triode), the NPN-type triode T52is cut off, and the PNP-type triode T53is turned on. At this time, the voltage of the gate output terminal G of the driving power amplification device511is equal to or roughly equal to the DC voltage Vss1, so the low level output by the driving power amplification device511controls the MOSFET Q51to be cut off. At this time, the Miller current generated by the MOSFET Q51flows from the drain to the gate through a Miller capacitor, and then flows to a node N5formed by connecting the positive electrodes of the diode D51and the diode D52in the auxiliary Miller clamping circuit501. Because the built-in Miller clamping circuit531is triggered to be in a low-resistance state when the output terminal OUT outputs a low level and is used for absorbing a Miller current, a small amount of current will flow through the resistor R51to generate a voltage drop across the resistor R51, and the voltage drop across the resistor R51is greater than a sum of a positive bias voltage of an emitter junction of the PNP-type triode T51and a turn-on voltage of the diode D52. Therefore, the PNP-type triode T51is turned on, and the Miller current flows from the node N5to the DC voltage Vss1through the diode D52and the PNP-type triode T51which is in a turn-on state.

According to the above-mentioned Miller clamping principle, a very small part of the Miller currents generated by the MOSFETs Q51, Q52and Q53flow into the built-in Miller clamping circuit531, and the vast majority of the Miller currents flow to the DC voltages Vss1, Vss2and Vss3respectively through the turned-on auxiliary Miller clamping circuits501,502and503. The auxiliary Miller clamping circuits501,502and503amplify the current absorption capability of the built-in Miller clamping circuit531, so only one driver chip53is adopted to absorb the Miller currents generated by a plurality of parallel MOSFETs. Compared with the Miller clamping device adopting a plurality of driver chips53, the Miller clamping device50of the present invention saves the circuit cost.

The gates of the parallel MOSFETs Q51, Q52and Q53are isolated from one another, so the MOSFETs Q51, Q52and Q53may not be damaged due to asynchronous ON/OFF of the MOSFETs Q51, Q52and Q53.

When the auxiliary Miller clamping circuits501,502,503are arranged on the circuit board, the auxiliary Miller clamping circuits501,502,503may be made close to the gates of the switching transistors Q51, Q52and Q53, thereby reducing Miller current conduction paths, then reducing equivalent resistance in the Miller current conduction paths, improving the Miller clamping effect, and ensuring that the MOSFETs Q51, Q52and Q53may not be turned on accidentally.

The resistor R51may be used as a voltage dividing resistor with a larger resistance value (for example, several thousand ohms), and a voltage across the resistor is greater than the positive bias voltage of the emitter junction of the PNP-type triode T51, to enable the PNP-type triode T51to be turned on. The resistor R52may be used as a base current limiting resistor with a smaller resistance value (for example, several ohms to tens of ohms) to prevent a damage on the PNP-type triode T51due to an excessive base current.

The capacitor C51may be used as a high-frequency negative feedback capacitor with an appropriate capacitance value, to improve the stability of the PNP-type triode T51and avoid high-frequency parasitic oscillation.

The diode D51is used for clamping a gate voltage of the MOSFET Q51. If the gate voltage of the MOSFET Q51is much greater than the DC voltage Vdd1, the diode D51is turned on, thus clamping the gate voltage of the MOSFET Q51to a sum of the DC voltage Vdd1and the turn-on voltage of the diode D51. The diode D52is connected between the emitter of the PNP-type triode T51and the gate of the MOSFET Q51, to prevent the situation that an emitter current of the PNP-type triode T51reversely flows into the gate of the MOSFET Q51, and then affects the ON/OFF state or causes a damage on the MOSFET Q51.

FIG.6is a circuit diagram of a driver for parallel switching transistors according to a third embodiment of the present invention. As shown inFIG.6, a driver6is substantially the same as the driver5shown inFIG.5, except that a Miller clamping device60further includes a pulse width modulation signal locking device64connected between an output terminal OUT of a driver chip63and a Miller clamping terminal CLAMP of a built-in Miller clamping circuit631. One end of a resistor R61in an auxiliary Miller clamping circuit601is connected to the Miller clamping terminal CLAMP of the built-in Miller clamping circuit631, and the other end is connected to a node formed by connecting a negative electrode of a diode D62with an emitter of a PNP-type triode T61. Auxiliary Miller clamping circuits602and603are the same as the auxiliary Miller clamping circuit601, which will not be repeated here.

The pulse width modulation signal locking device64includes a resistor R64and a diode D64which are connected in series. When a pulse width modulation signal output by the output terminal OUT of the driver chip63is at a low level VL, the Miller clamping terminal CLAMP is triggered to be in a low-resistance state, and a conduction path is formed by the resistor R64and the diode D64, so that a voltage of the Miller clamping terminal CLAMP is less than VL minus a voltage drop of the diode D64. Thus, the voltage of the Miller clamping terminal CLAMP is clamped at a low level, to prevent the situation that an electrical potential of the Miller clamping terminal CLAMP is changed by signal interference to affect the ON/OFF state of the PNP-type triode T61, and to further prevent the parallel MOSFETs from being turned on accidentally.

FIG.7is a circuit diagram of a driver for parallel switching transistors according to a fourth embodiment of the present invention. As shown inFIG.7, a driver7is substantially the same as the driver5shown inFIG.5, except that a Miller clamping device70includes a driver chip73and identical auxiliary Miller clamping circuits701,702and703. A built-in Miller clamping circuit731of the driver chip73is a voltage source configured to output a high-level Miller enable signal. Each of the auxiliary Miller clamping circuits701,702, and703adopts an NPN-type triode instead of the PNP-type triode in the auxiliary Miller clamping circuit501,502, or503, and omits a resistor connected between a positive electrode or negative electrode of a diode D72and a Miller clamping terminal CLAMP of the built-in Miller clamping circuit731.

Specifically, the auxiliary Miller clamping circuit701includes an NPN-type triode T71, diodes D71and D72, a resistor R72and a capacitor C71, wherein the capacitor C71is connected between a base and a collector of the NPN-type triode T71; the resistor R72is connected between the base of the NPN-type triode T71and the Miller clamping terminal CLAMP of the Miller clamping circuit731; a negative electrode of diode D71is connected to a high-level DC voltage Vdd1; a node formed by connecting a positive electrode of the diode D71with a positive electrode of the diode D72is connected to a gate of an MOSFET Q71; a negative electrode of the diode D72is connected to the collector of the NPN-type triode T71; and an emitter of the NPN-type triode T71is connected to a low-level DC voltage.

When an MOSFET (not shown inFIG.7) connected to a same bridge arm as the MOSFET Q71is controlled to be turned on, a Miller current generated by the MOSFET Q71flows from a drain to a gate of the MOSFET Q71through a parasitic Miller capacitor, and a Miller clamping circuit831outputs a high-level Miller enable signal at the same time, so that an emitter junction of the NPN-type triode T71is forward biased. Thus, the NPN-type triode T71is turned on, the Miller current flows from the gate of the MOSFET Q71to the low-level DC voltage Vss1through the diode D72and the turned-on NPN-type triode T71in sequence. Therefore, no voltage drop is generated between the gate and the source of the MOSFET Q71, preventing the MOSFET Q71from being turned on accidentally.

In another embodiment of the present invention, the Miller clamping device50further includes the pulse width modulation signal locking device64inFIG.6.

In other embodiments of the present invention, controllable transistors such as P-type MOSFET, etc. may be adopted instead of the PNP-type triodes in the auxiliary Miller clamping circuits501,502,503inFIG.5or the PNP-type triodes in the auxiliary Miller clamping circuits601,602,603inFIG.6, wherein a gate of the P-type MOSFET is a control electrode, a source is connected to a gate of a corresponding switching transistor, and a drain is connected to a low-level DC voltage. In other embodiments of the present invention, controllable transistors such as N-type MOSFET, etc. may be adopted instead of NPN-type triodes in the auxiliary Miller clamping circuits701,702,703inFIG.7, wherein a gate of the N-type MOSFET is a control electrode, a drain is connected to a gate of a corresponding switching transistor, and a source is connected to a low-level DC voltage. The MOSFET has a faster ON/OFF speed and can achieve better dynamic performance.

The Miller clamping device of the present invention can also be used for Miller clamping switching transistors such as multiple insulated gate bipolar transistors connected in parallel, etc. The number of the switching transistors connected in parallel is not limited to three, and may be more or less than three.

For the driver of the present invention, various models and types of driving power amplification devices may be selected, and various driving power amplification devices capable of performing power amplification on the pulse width modulation signal in the prior art may be selected.

For the Miller clamping device of the present invention, various models and types of driver chips having the built-in Miller clamping circuits may be selected.

Although the present invention has been described in terms of the preferred embodiments, the present invention is not limited to the embodiments described herein, and various variations and changes can be made without departing from the scope of the present invention.