Patent ID: 12261139

DETAILED DESCRIPTION

The techniques and devices disclosed herein include semiconductor chips (herein referred to simply as “chips”) that comprise one or more backside layers (BLs) and one or more integrated circuits (ICs), such as electronic integrated circuits (EICs) and photonic integrated circuits (PICs). The utilization of BLs can provide control over the stress and shape of a chip (e.g., the spatial profile of a surface of the chip) by modifying the stress applied to at least a portion of the chip (e.g., when the chip is at a static temperature, or when the chip is undergoing a change in temperature). As used herein, a “chip” can refer to an individual die (e.g., after a wafer has been diced into multiple dies) or a wafer that has not yet been diced into multiple dies.

In some examples, BLs enable a reduction in the variation of the height of one or more surfaces of the chip (also referred to as warpage). In chips that do not comprise BLs, such variations of the height may be larger after a thinning process (e.g., backside grinding) is performed and can be on the order of several microns, for example. In some applications, it can be challenging to utilize a thicker chip (e.g., a chip that has not undergone a thinning process), for example due to limitations inherent to the scribe and break process utilized in fabrication, or due to the space available in the packaging design of the chip. Therefore, in examples where a chip has a relatively thin backside (e.g., a thin handle), BLs may be particularly suited for reducing variation of the height of one or more surfaces of the chip. Furthermore, BLs can reduce the sensitivity of the chip to warpage induced by changes in temperature that may occur during some fabrication processes or during usage of the chip. In some examples, BLs can be designed as a stack of materials (e.g., formed by thin film deposition) on the backside of the chip so as to increase mechanical stability (e.g., by modifying stresses within the chip at a static temperature) and thermal stability of the chip (e.g., by modifying stresses within the chip during changes in temperature).

During fabrication at a foundry, the stress that a chip undergoes may be managed such that the warpage of the chip is reduced, or that the chip achieves a flatter spatial profile of a surface of the chip. Gaining control over such stress can result in better fabrication control of the optical properties of the chip, which can be modified by stress. In some cases, chips may undergo a thinning process (e.g., backside grinding) that is performed at the wafer level. In such a case in which the chip is a wafer that is then diced into multiple dies, each die can be impacted by the shape of the wafer (e.g., the warpage of the chip) acquired during the fabrication of the wafer. In general, a chip comprises one or more electronic structures (e.g., metal traces or metallic waveguides) and/or photonic structures (e.g., optical waveguides or electro-optic devices) that can impact the stress and shape of the chip. For example, a spatially asymmetric distribution of electronic or photonic structures can result in asymmetric stresses within the chip that lead to asymmetric warpage (i.e., an asymmetric shape of the chip). Furthermore, such asymmetry may also induce thermal dependencies on the warpage of the chip that may be undesirable.

FIGS.1A,1B,2A, and2Bcollectively show an example flip chip attachment process of a thinned chip that does not comprise BLs, whileFIGS.1A,1B,3A, and3Bcollectively show an example flip chip attachment process of a thinned chip that comprises BLs.

FIG.1Ashows an example chip100A comprising a first volume102(e.g., comprising a silicon handle or an indium phosphide handle) and a second volume104(e.g., comprising one or more photonic structures and one or more metal layers). In this example, there is some modest curvature of the chip100A that has been acquired during fabrication of the structures in the second volume104.

FIG.1Bshows an example chip100B comprising a thinned first volume106(e.g., formed by performing backside grinding of the first volume102shown inFIG.1A) and the second volume104. In this example, a first curvature of the chip100B is larger than a second curvature of the chip100A shown inFIG.1Adue to the differences in stress associated with the thinned first volume106and stress associated with the first volume102shown inFIG.1A.

FIG.2Ashows an example flip chip processing step200A, prior to reflow soldering, where a first chip202is in contact with a second chip (or carrier)204. The first chip202comprises a thinned first volume206, a second volume208, and metal structures210. The first chip202may be formed, for example, by adding metal bumps (e.g., composed of copper) to the chip100B shown inFIG.1Bto form the metal structures210.

FIG.2Bshows an example flip chip processing step200B, after reflow soldering, where the first chip202is in contact with the second chip (or carrier)204. In this example, the first chip202goes from a positive curvature before reflow soldering, to a negative curvature after reflow soldering. Due to such warpage, the resulting flip chip attachment can result in fewer than all of the metal structures210from making contact with the second chip (or carrier)204, or in weak solder joints between the first chip202and the second chip (or carrier)204. In a mass production scenario, applying a force on the first chip202during the reflow soldering process can be time consuming, since it may require individual processing of each chip rather than bulk processing of multiple chips in a tray that is located within a reflow furnace. The amount of curvature shown in this example is for illustrative purposes, and is not necessarily meant to be to scale.

FIG.3Ashows an example flip chip processing step300A, prior to reflow soldering, where a first chip302is in contact with a second chip (or carrier)304. The first chip302comprises BLs305(e.g., comprising one or more metal layers), a thinned first volume306, a second volume308, and metal structures310. The first chip302may be formed, for example, by adding the BLs305and the metal structures310to the chip100B shown inFIG.1B. These steps may result in some change of the overall curvature of the first chip302such that any curvature will ultimately be reduced (or substantially removed) after final processing in later steps.

In some examples, BLs can be used to control an initial shape of a chip (e.g., before the chip undergoes reflow soldering or other temperature changes), as well as the thermal dependency of the shape (e.g., during reflow soldering). In examples where a first chip is being bonded to a second chip (e.g., as shown inFIG.3B), BLs on the first chip or on the second chip can be used to enhance the amount of contact surface area between the first chip and the second chip during a change in temperature (e.g., during heating for reflow soldering) so as to increase the number and/or quality of the solder joints between the two chips.

FIG.3Bshows an example flip chip processing step300B, after reflow soldering, where the first chip302is in contact with the second chip (or carrier)304. In this example, the first chip302goes from a first curvature before reflow soldering, to a second curvature after reflow soldering, where the second curvature is less than the first curvature. In other examples, the second curvature may be larger than the first curvature, but still less than a third curvature that would be present in the first chip302if the BLs305were not present.

Referring again toFIGS.3A and3B, the BLs305can comprise one or more dielectric layers (e.g., composed of silicon dioxide or silicon nitride) and/or one or more metal layers (e.g., composed of gold, aluminum, palladium, platinum, silver, titanium, tantalum, chromium, or tungsten). In some examples, the patterning of the BLs305can be designed so as to compensate for stress that results from a thinning process or for stress that results from changes in temperature to the first chip302. For example, the patterning of the BLs305can be designed so as to reduce the impact of thermal variations of the first chip302that can depend at least in part on electronic structures (not shown) or photonic structures (not shown) within the first chip302. In the case of reflow soldering (e.g., in a flip chip attachment process), the temperature of the first chip302can range from room temperature (e.g., 20° C.) to 280° C., for example. Such changes in temperature can affect the shape and curvature of the first chip302. In some examples, reflow soldering may be performed at temperatures as low as 150° C.

FIG.4shows a top view of an example chip400comprising numerous BLs402. The design of the BLs402(e.g., the height, material, and location of each BL, the evaporation parameters, or the vertical arrangement of each BL to form a stack of BLs) can depend at least in part on the chip400, an estimated change in temperature of the chip400, and/or a fabrication process (e.g., flip chip attachment) of the chip400. In some examples, the BLs402can be patterned to form fiducials that can be used to more accurately determine the position and orientation of the chip400for subsequent processes (e.g., passive alignment of free space optical elements). Without such fiducials, the subsequent traceability of the chip400and additional processing of the chip400may be more challenging.

FIGS.5,6,7, and8each show various example chips that comprise BLs that can comprise metal layers, adhesion layers, and passivation layers (also referred to as dielectric layers). The BLs can be selected based on their material properties, such as their coefficient of thermal expansion (CTE), on which the stresses applied to the chip can depend upon. Furthermore, the vertical stack up of the BLs (e.g., their arrangement and their heights) can be used along with their CTE to manage the stress applied to the chip (e.g., before, during, or after the chip undergoes a change in temperature). For example, a first thickness of a metal layer in the set of BLs can be less than half a second thickness of the volume of the chip (e.g., so as to reduce the amount of metal added to the chip). In such examples, a first CTE of a metal layer in the set of BLs can be larger than a second CTE of a metal layer in the volume of the chip, such that the stress applied by the metal layer in the set of BLs counteracts the stress applied by the metal layer in the volume of the chip despite having a different thickness.

Referring again toFIGS.5,6,7, and8, in general, the BLs need not necessarily be electrically connected to other metal layers in the volume of the chip, or to metal structures on another surface of the chip. In some examples, the backside of the chip further is “active” and comprises one or more sensors (e.g., temperature sensors or stress sensors), one or more heating elements, and/or one or more piezoelectric crystals. For example, the one or more heating elements can control the temperature of the chip and can be based at least in part on one or more measurements from the one or more sensors. In other examples, the one or more piezoelectric crystals can be actively controlled (e.g., by a voltage) so as to modify the stress of the chip by changing the size of the piezoelectric crystal. The control signals transmitted to the piezoelectric crystals can be based at least in part on the one or more sensors. Thus, the stress of the chip can be modified by one or more heating elements and/or piezoelectric crystals, and the amount of stress modification can be based at least in part on one or more measurements from sensors. Such control over the stress of the chip can be used to control the shape (e.g., curvature) of the chip.

FIG.5shows an example chip500comprising a first metal layer502A adjacent to a second metal layer502B, where the first metal layer502A and the second metal layer502B are BLs and can be composed of different metals. An adhesion layer504is located between the second metal layer502B and a first passivation layer506A (e.g., composed of an oxide). The first passivation layer506A is adjacent to a volume508(e.g., comprising silicon or indium phosphide) that can include electronic or photonic structures and/or metal layers (e.g., as part of an electro-optic modulator). A second passivation layer506B is adjacent to the volume508and to a third metal layer510.

FIG.6shows an example chip600comprising a first metal layer602(a BL) adjacent to an adhesion layer604. The adhesion layer604is adjacent to a first passivation layer606A, and the first passivation layer606A is adjacent to a volume608that can include electronic or photonic structures and/or additional metal layers. A second passivation layer606B is adjacent to the volume608and to a second metal layer610. In this example, the second metal layer610is asymmetrically distributed on the chip600such that only the left side of the chip600comprises the second metal layer610. In order to compensate for the stress associated with the second metal layer610, the first metal layer602is formed asymmetrically as well, such that the first metal layer602can counterbalance stresses imposed by the second metal layer610.

FIG.7shows an example chip700comprising a first passivation layer701A located between a first metal layer702A and a second metal layer702B, all of which are BLs. A second passivation layer701B is located between the second metal layer702B and a volume704. A third passivation layer701C is located between the volume704and a third metal layer706. In this example, the first passivation layer701A separates the first metal layer702A and the second metal layer702B and can be designed to have a desired coefficient of thermal expansion (CTE) together with the other BLs (i.e., the first metal layer702A, the second metal layer702B, and the second passivation layer701B).

FIG.8shows an example chip800comprising a first set of one or more metal layers802, where the first set of one or more metal layers802is characterized by a first thickness and comprises at least one metal layer that is characterized by a first coefficient of thermal expansion. The chip800further comprises a first volume804A that is adjacent to the first set of one or more metal layers802. The chip800further comprises a second volume804B that comprises one or more electronic or photonic structures (not shown). The second volume804B further comprises a second set of one or more metal layers (not shown) that is characterized by a second thickness that is at least twice as large as the first thickness, where at least one metal layer in the second set of one or more metal layers is characterized by a second coefficient of thermal expansion. The chip800further comprises a set of one or more metal structures806that is adjacent to the second volume804B and comprises at least one metal structure that is electrically connected to at least a portion of at least one metal layer in the second set of one or more metal layers.

Referring again toFIG.8, in some examples, the second volume804B comprises the third passivation layer701C and the third metal layer706shown inFIG.7. In other examples, the second volume804B comprises the second passivation layer606B and the second metal layer610shown inFIG.6. In other examples, the second volume804B comprises the second passivation layer506B and the third metal layer510shown inFIG.5. In general, the second volume804B may comprise one or more passivation layers (not shown) that are adjacent to the metal structures806. In some examples, a first location of the first set of one or more metal layers802depends at least in part on a second location of the second set of one or more metal layers located in the second volume804B. For example, the first set of one or more metal layers802may have reduced metal (or no metal) above locations where the second set of metal layers have metal. Such an arrangement can be used to reduce stray capacitance and/or interference (e.g., in an electro-optic modulator), particularly for sensitive devices or components.

FIG.9shows a flowchart of an example fabrication process900comprising forming (902) a first volume of a chip comprising structures, the first volume of the chip being adjacent to a second volume of the chip, forming (904) a set of one or more metal structures of the chip, forming (906) a first set of one or more metal layers adjacent to the second volume of the chip, and modifying (908) a curvature of an outer surface of the chip. (The generic labels “first” and “second” do not necessarily imply any order in which the steps are performed.) The first set of one or more metal layers is characterized by a first thickness and comprises at least one metal layer that is characterized by a first coefficient of thermal expansion. The first volume comprises one or more electronic or photonic structures, and a second set of one or more metal layers that is characterized by a second thickness, where at least one metal layer in the second set of one or more metal layers is characterized by a second coefficient of thermal expansion. The set of one or more metal structures is adjacent to the first volume and comprises at least one metal structure that is electrically connected to at least a portion of at least one metal layer in the second set of one or more metal layers in the first volume. The curvature of an outer surface of the chip is modified (908) by heating at least a portion of the chip from a first temperature to a second temperature, and the modifying (908) of the curvature is based at least in part on the first coefficient of thermal expansion, the second coefficient of thermal expansion, and a temperature difference between the first temperature and the second temperature. In other example fabrication processes, the order of steps can be changed, and other steps can optionally be performed, such as thinning the chip when forming the second volume before forming (906) the first set of one more layers.

While the disclosure has been described in connection with certain embodiments, it is to be understood that the disclosure is not to be limited to the disclosed embodiments but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims, which scope is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures as is permitted under the law.