Patent ID: 12230359

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

The terms used in this specification generally have their ordinary meanings in the art and in the specific context where each term is used. The use of examples in this specification, including examples of any terms discussed herein, is illustrative, and in no way limits the scope and meaning of the disclosure or of any exemplified term. Likewise, the present disclosure is not limited to various embodiments given in this specification.

Although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

Furthermore, spatially relative terms, such as “underlying,” “below,” “lower,” “overlying,” “upper” and the like, may be used throughout the description for ease of understanding to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The structure may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

An anti-fuse memory device and cell structures therein are provided in accordance with various embodiments. Some variations of some embodiments are discussed. Throughout various views and illustrative embodiments, like elements are designated with the like reference numbers for ease of understanding.

Reference is now made toFIG.1.FIG.1is a schematic diagram of an anti-fuse memory cell100, in accordance with some embodiments of the present disclosure. In some embodiments, the anti-fuse memory cell100is also referred to as a one-time programming (OTP) memory cell. For illustration inFIG.1, the anti-fuse memory cell100includes a reading device102and a programming device104. The programming device104is coupled to the reading device102, and a terminal of the reading device102is coupled to a bit line BL to receive data signal from the bit line BL.

In some embodiments, the reading device102and the programming device104are implemented with Metal-Oxide-Semiconductor (MOS) transistors. In some embodiments, the reading device102and the programming device104are implemented with N type MOS (NMOS) transistors. For illustration ofFIG.1, the reading device102and the programming device104are implemented with MOS transistors TR and TP, respectively. A first source/drain terminal of the transistor TR is coupled to the bit line BL, and a gate terminal of the transistor TR is coupled to a read word line that is designated with WLR. A first source/drain terminal of the transistor TP is coupled to a second source/drain terminal of the transistor TR, and a gate terminal of the transistor TP is coupled to a program word line that is designated with WLP. A second source/drain terminal of the transistor TP is coupled to a voltage line (not shown).

The reference designation WLR in the present disclosure denotes a general read word line throughout the description. The reference designation WLP in the present disclosure denotes a general program word line throughout the description. The reference designations of the features throughout the description may be referred to using the reference designations WLR and WLP followed by a number. For example, when features are denoted as WLR0and WLR1, they indicate two different read word lines, and when features are denoted as WLP0and WLP1, they indicate two different program word lines. In some embodiments, the read word line WLR is also referred to as “selection word line,” “word line gate line,” and so on. In some embodiments, the program word line WLP is also referred to as “program gate line,” “anti-fuse gate line,” “anti-fuse control line,” and so on. Moreover, the reference designation BL in the present disclosure denotes a general bit line throughout the description.

Similarly, the reference designations TR and TP in the present disclosure denote transistors that are coupled to the read word line WLR and the program word line WLP, respectively, throughout the description. Accordingly, in some embodiments, the transistor TR is also referred to as “selection transistor,” and the transistor TP is also referred to as “program transistor.”

For illustration of operation, for programming the anti-fuse memory cell100, a ground voltage (0V) is provided to the voltage line and the bit line BL, a selecting voltage Vdd is provided to the read word line WLR, and a programming voltage Vp is provided to the program word line WLP. In some embodiments, the magnitude of the programming voltage Vp is larger than that of the selecting voltage Vdd. For example, the magnitude of the programming voltage Vp ranges from about 3.6V to about 6V, and the selecting voltage Vdd ranges from about 1.5V to about 2.2V. In some other embodiments, the magnitude of the voltage on the bit line BL ranges from about 0V to about 0.5V.

When the transistor TR is turned on in response to the selecting voltage Vdd applied to the read word line WLR and the ground voltage is applied to the bit line BL, the programming voltage Vp that is high enough is applied to the gate of the transistor TP. Because the programming voltage Vp is beyond a withstanding voltage range of the gate, the gate of the transistor TP is ruptured. The ruptured gate is considered as a resistor with a low resistance value, for illustration. The anti-fuse memory cell100accordingly generates a program current flowing to the bit line BL through the turn-on transistor TR.

During a read operation, the ground voltage (0V) is provided to the bit line BL and the voltage line, the selecting voltage Vdd is provided to the read word line WLR, and a read voltage Vr is provided to the program word line WLP. When the transistor TR is turned on in response to the reading voltage Vdd, the transistor TP generates a read current in response to the read voltage Vr. The anti-fuse memory cell100accordingly generates the read current flowing through the transistor TR to the bit line BL. According to the magnitude of the read current flowing through the bit line BL, the anti-fuse memory cell100is configured to have a storing state in some embodiments. In some embodiments, the magnitude of the selecting voltage Vdd is the same as that of the read voltage Vr. For example, the magnitude of the read voltage Vr ranges from about 1V to about 2V, and the selecting voltage Vdd ranges from about 0.75V to about 1.5V. In some other embodiments, the magnitude of the voltage on the bit line BL ranges from about 0V to about 0.5V.

The above implementations of the reading device102and the programming device104are given for illustrative purposes. Various implementations of the reading device102and the programming device104are within the contemplated scope of the present disclosure. For example, depending on various manufacturing processes, the reading device102and the programming device104are implemented with various types of MOS transistors, including, for example, Fin Field Effect Transistors (FinFETs), in various embodiments. For another example, in various embodiments, the reading device102and the programming device104as discussed above are implemented with a single transistor. For illustration, the transistors TP and TR as discussed above are manufactured as a single transistor to perform the same functions of the transistors TP and TR.

The configuration of the anti-fuse memory cell100as illustrated above is also given for illustrative purposes. Various configurations of the anti-fuse memory cell100are within the contemplated scope of the present disclosure. For example, in various embodiments, the second source/drain terminal of the transistor TP as the programming device104is not coupled to the voltage line and is electrically floating (unconnected). The transistor TP having the second source/drain terminal being electrically floating is applicable in all of the embodiments as discussed in the present disclosure.

Reference is now made toFIG.2.FIG.2is an equivalent circuit200of the anti-fuse memory cell100shown inFIG.1, in accordance with some embodiments of the present disclosure. The equivalent circuit200of the anti-fuse memory cell100is illustrated with resistors and the transistor TR to show the effective circuit connections. For illustration inFIG.2, the equivalent circuit200includes a resistor Rvg, a resistor Rmg, a resistor Rcell, a resistor Rwlr, the transistor TR, and a resistor Rbl.

For illustration inFIG.2, the resistor Rvg couples the program word line WLP to the resistor Rmg, the resistor Rwlr couples the read word line WLR to the transistor TR, the resistor Rcell is coupled between the resistor Rmg and the transistor TR, and the resistor Rbl couples the transistor TR to the bit line BL.

The resistor Rvg indicates the resistance between the program word line WLP and the gate terminal of the transistor TP, and the resistor Rwlr indicates the resistance between the read word line WLR and the gate terminal of the transistor TR. The resistor Rbl indicates the resistance between the first source/drain terminal of the transistor TR and the bit line BL.

The resistor Rmg indicates the resistance of the gate structure corresponding to the gate terminal of the transistor TP. For example, when a current or a signal is transmitted through the gate structure, the resistor Rmg indicates the resistance which the current or the signal experienced. In some embodiments, compared to other resistors shown inFIG.2, the resistor Rmg is relatively small because a distance of path through which the current or the signal traveled in the gate structure is very short. Thus, the resistor Rmg is omitted in some embodiments.

In some embodiments, after the anti-fuse memory cell100is programmed, the gate of the transistor TP is ruptured, and thus an electrical path between the gate terminal of the transistor TP and the first source/drain terminal of the transistor TP is effectively viewed as the resistor Rcell as illustrated inFIG.2. In some embodiments, a resistance of the resistor Rcell is about several kilo-ohms.

In some embodiments, the anti-fuse memory cell100is formed with several layers. For example, the sources/drains of the transistors TP and TR are arranged in a layer of active area, the gates of the transistors TP and TR are arranged in a layer of gate structure above the layer of active area, and the word lines WLP and WLR and the bit line BL are arranged in a layer above the layer of gate structure. Accordingly, the resistor Rbl also indicates the resistance of the electrical connection between the layer of the active area and the layer of bit line BL in some embodiments. Moreover, in some embodiments, vias are applied in the electrical connections between the layers. Accordingly, the resistors Rvg, Rwlr, and Rbl indicate effective resistances of the vias connected between the layers, in some embodiments.

In some embodiments, during the read operation, a current path is provided for the read current from the program word line WLP to the bit line BL. For illustration inFIG.2, the current path is illustrated along the current flow, and the current is designated as Iread.

The above implementation of the equivalent circuit200is provided for illustrative purposes. Various implementations of the equivalent circuit200are within the contemplated scope of the present disclosure. For example, the equivalent circuit200includes more or less resistors indicating other connections in the anti-fuse memory cell100.

Reference is made toFIG.3.FIG.3is a circuit schematic diagram of an anti-fuse memory cell array300, in accordance with some embodiments of the present disclosure. For illustration inFIG.3, the anti-fuse memory cell array300includes eight anti-fuse memory cells which are designated as bit1, bit2, bit3, bit4, bit5, bit6, bit7, and bit8, each of which corresponds to the anti-fuse memory cells100ofFIG.1. The bit1, bit2, bit3, and bit4are arranged in a column connected to the program word line WLP0and read word line WLR0, and the bit5, bit6, bit7, and bit8are arranged in a column connected to the program word line WLP1and read word line WLR1. The bit1and bit5are arranged in a row connected to the bit line BL1, the bit2and bit6are arranged in a row connected to the bit line BL2, the bit3and bit7are arranged in a row connected to the bit line BL3, and the bit4and bit8are arranged in a row connected to the bit line BL4.

FIG.3further illustrates Rwl connected to the program word lines WLP0and WLP1and the read word lines WLR0and WLR1, and resistors Rbl connected to the bit lines BL1-BL4. The resistors Rwl and Rbl indicate the effective resistances of electrical connections of the program word lines WLP0and WLP1, the read word lines WLR0and WLR1, and the bit lines BL1-BL4to the anti-fuse memory cells bit1-bit8. In some embodiments, each one of the resistors Rwl is a combination of the resistor Rvg and the resistor Rmg shown inFIG.2.

During the program operation, similar to the program operation described inFIG.1, the ground voltage is provided to the voltage line (not shown) and the bit lines BL1-BL4, the selecting voltage Vdd is provided to the read word lines WLR0and WLR1, and programming voltages Vp and Vp′ are provided to the program word lines WLP0and WLP1, respectively. In some embodiments, the magnitude of each one of the programming voltages Vp and Vp′ is larger than that of the selecting voltage Vdd.

During the read operation, similar to the read operation described inFIG.1, the ground voltage is provided to the bit lines BL1-BL4and the voltage line (not shown), the selecting voltage Vdd is provided to the read word line WLR0, and a read voltage Vr is provided to the program word line WLP0. The anti-fuse memory cells bit1-bit4accordingly generates the read current flowing through the anti-fuse memory cells bit1-bit4to the bit lines BL1-BL4, respectively. According to the magnitude of the read current flowing to the bit lines BL1-BL4, the anti-fuse memory cells bit1-bit4are configured to have storing states in some embodiments.

Similar to the anti-fuse memory cells bit1-bit4, during the read operation, the ground voltage is provided to the bit lines BL1-BL4and the voltage line (not shown), the selecting voltage Vdd is provided to the read word line WLR1, and a read voltage Vr is provided to the program word line WLP1. The anti-fuse memory cells bit5-bit8accordingly generates the read current flowing through the anti-fuse memory cells bit5-bit8to the bit lines BL1-BL4, respectively. According to the magnitude of the read current flowing to the bit lines BL1-BL4, the anti-fuse memory cells bit5-bit8are configured to have storing states in some embodiments. In some embodiments, the read operation of the anti-fuse memory cells bit1-bit4and the read operation of the anti-fuse memory cells bit5-bit8are not performed at the same time, to avoid signal interference.

Reference is made toFIG.4.FIG.4is a layout structure400of part of the anti-fuse memory cell array300shown inFIG.3, in accordance with some embodiments of the present disclosure. In some embodiments, the layout structure400corresponds to the anti-fuse memory cells bit1and bit5shown inFIG.3. Alternatively stated, the layout structure400illustrates a row of the anti-fuse memory cell array300. In some embodiments, at least one of the other rows in the anti-fuse memory cell array300is implemented with the same layout as the layout structure400.

FIG.5is a schematic diagram500illustrating a cross-section view, along a LINE A, of the anti-fuse memory cells bit1and bit5shown inFIG.4, in accordance with some embodiments of the present disclosure. For ease of understanding, the embodiments with respect toFIG.4are discussed with reference toFIG.5.

For illustration inFIG.4, the layout structure400includes an active area AA1, a gate G1, a gate G2, a gate G3, a gate G4, a gate Gd1, a gate Gd2, a conductive segment CS1, a conductive segment CS2, a conductive segment CS3, a program word line WLP0, a program word line WLP1, a read word line WLR0, a read word line WLR1, a bit line BL1, a gate via Vg1, a gate via Vg5, and a conductive via Vd1.

The gates G1-G4are arranged above the active area AA1, and the gates G1-G4extend to cross over the active area AA1. The gates G1-G4are arranged to be separate from each other. The conductive segments CS1and CS3are arranged above the gate G1and the gate G4, respectively. In some embodiments, the conductive segments CS1and CS3are disposed directly above the active area AA1. The program word lines WLP0and WLP1are arranged above the conductive segments CS1and CS3, respectively. The read word lines WLR0and WLR1are arranged at two opposite sides of the active area AA1in a layout view of the layout structure400.

In some embodiments, the active area AA1is implemented by a doped region/area, in order for the formation of the transistors included in the anti-fuse memory cells bit1and bit5as shown inFIG.3. In some embodiments, the active area AA1is configured for the source/drain of the transistors TP and transistors TR of the anti-fuse memory cells bit1and bit5. The gate G1corresponds to the gate of the transistor TP0of the anti-fuse memory cell bit1, and the gate G2corresponds to the gate of the transistor TR0of the anti-fuse memory cell bit1. The gate G4corresponds to the gate of the transistor TP1of the anti-fuse memory cell bit5, and the gate G3corresponds to the gate of the transistor TR1of the anti-fuse memory cell bit5.

In some embodiments, the gate via Vg1is disposed directly above the active area AA1, and couples the gate G1to the conductive segment CS1. The conductive segment CS1is coupled to the program word line WLP0through a via V01(shown inFIG.5), and configured to receive the reading voltage Vr and/or programming voltage Vp. In some embodiments, the gate via Vg5is disposed directly above the active area AA1, and couples the gate G4to the conductive segment CS3. The conductive segment CS3is coupled to the program word line WLP1through a via V02(shown inFIG.5), and configured to receive the reading voltage Vr and/or programming voltage Vp.

In some embodiments, the vias V01and V02are disposed above and overlap the gate vias Vg1and Vg5, respectively, in the layout view of the layout structure400, as well as shown inFIG.5. Accordingly, inFIG.4, the layout structure400only illustrates the gate vias Vg1and Vg5, for simplicity of illustration. However, the present disclosure is not limited to the embodiments ofFIGS.4and5. Various positions of the vias V01-V02are within the contemplated scope of the present disclosure. For example, in various embodiments, the via V01is disposed at a position where the via V01is not overlapped with the active area AA1in the layout view of the layout structure400.

In some embodiments, the active area AA1is coupled to the conductive segment CS2through the conductive via Vd1, in which the conductive segment CS2is disposed between the gate G2and the gate G3in the layout view of the layout structure400, and the conductive via Vd1is disposed directly above the active area AA1. In some embodiments, the conductive segment CS2is arranged along a direction Y in which the gate G1extends. For illustration, the conductive segment CS2is coupled to the bit line BL1through a via V03(shown inFIG.5), and is configured to receive data signals transmitted from the bit line BL1.

In some embodiments, the via V03is disposed above and overlaps the conductive via Vd1in the layout view of the layout structure400, as well as shown inFIG.5. Accordingly, inFIG.4, the layout structure400only illustrates the conductive via Vd1, for simplicity of illustration. However, the present disclosure is not limited to the embodiments ofFIGS.4and5. Various positions of the via V03are within the contemplated scope of the present disclosure. For example, in various embodiments, the via V03is disposed above the conductive segment CS2but is not overlapped with the active area AA1in the layout view of the layout structure400.

For illustration inFIG.4, the gates Gd1and Gd2are arranged to be separate from the gates G1-G4, and the gates Gd1and Gd2are arranged at two opposite sides of the active area AA1in the layout view of the layout structure400. In some embodiments, the gates Gd1and Gd2are configured as dummy gates, in which a “dummy gate” does not act as the gate for MOS devices in some embodiments. The above configuration of the gates Gd1and Gd2is provided for illustrative purposes. Various configurations of the gates Gd1and Gd2are within the contemplated scope of the present disclosure. For example, in various embodiments, the gates Gd1and Gd2are omitted and not arranged in the layout structure400.

In some approaches, a gate, corresponding to, for example, the gate of the transistor TP0ofFIG.3, is coupled to, for example, the program word line WLP0through a gate via, and the gate via is not disposed directly above an active area. Accordingly, when the program word line WLP0and the active area have a current path therebetween associated with, for example, a reading operation, the current needs to flow from the program word line WLP0through the gate via and a segment of the gate to the active area because the gate via is not disposed directly above the active area. With the current flowing through the segment of the gate, the current encounters a resistance (e.g., the resistance of the resistor Rmg inFIG.2) corresponding to the segment of the gate. Alternatively stated, there is a relatively larger equivalent resistance on the current path. Accordingly, the performance of the operation (e.g., operation speed) associated with the current path is affected.

Compared to the above approaches, in the embodiments of the present disclosure, for example with reference toFIG.4, the gate via Vg1is disposed directly above the active area AA1in the layout view of the layout structure400. For illustration inFIG.5, the program word line WLP0is coupled to the gate G1through the via V01, the conductive segment CS1, and the gate via Vg1. In such structures, the current on the current path substantially flows directly from the program word line WLP0through the via V01, the conductive segment CS1, and the gate via Vg1to the active area AA1. Accordingly, the current or signal transmitting through the gate G1does not have to experience the resistance of the segment of the gate as discussed in the above approaches. Accordingly, the equivalent resistance on the current path between the program word line WLP0and the active area AA1is reduced. As a result, the performance of the operation (e.g., operation speed) associated with the current path is able to be improved.

In some approaches, a bit line corresponding to, for example, the bit line BL1ofFIG.3, is coupled to, for example, the transistor TR0through a via, and the via is not disposed directly above an active area. Similarly, when the bit line BL1and the active area have a current path therebetween associated with, for example, a reading operation, the current needs to flow from the bit line BL1through the via and an additional conductive segment to the active area because the via is not disposed directly above the active area. With the current flowing through the additional conductive segment, the current encounters a resistance (e.g., the resistance of the resistor Rbl inFIG.2) corresponding to the additional conductive segment. Alternatively stated, there is a relatively larger equivalent resistance on the current path. Accordingly, the performance of the operation (e.g., operation speed) associated with the current path is affected.

Compared to the above approaches, in the embodiments of the present disclosure, for example with reference toFIGS.4and5, the conductive via Vd1and the via V03are disposed directly above the active area AA1in the layout view of the layout structure400. For illustration inFIG.5, the bit line BL1is coupled to the active area AA1through the via V03, the conductive segment CS2, and the conductive via Vd1. In such structures, the current on the current path substantially flows directly from the bit line BL1through the via V03, the conductive segment CS2, and the conductive via Vd1to the active area AA1. Accordingly, the current or signal transmitting from the bit line BL1does not have to experience the resistance of the additional conductive segment as discussed in the above approaches. Accordingly, the equivalent resistance on the current path between the active area AA1and the bit line BL1is reduced. As a result, the performance of the operation (e.g., operation speed) associated with the current path is able to be improved.

Reference is made toFIG.6.FIG.6is a layout structure600of part of the anti-fuse memory cell array300shown inFIG.3, in accordance with some embodiments of the present disclosure. In some embodiments, the layout structure600corresponds to the anti-fuse memory cells bit1, bit2, bit5, and bit6shown inFIG.3. Alternatively stated, the layout structure600illustrates two rows in the anti-fuse memory cell array300.

In some embodiments, structures of the anti-fuse memory cells bit1and bit5in the layout structure600are the same as those of the anti-fuse memory cells bit1and bit5in the layout structure400shown inFIG.4. Accordingly, they are not further detailed herein.

Compared to the layout structure400, the layout structure600further includes an active area AA2, a conductive segment CS4, a conductive segment CS5, a conductive segment CS6, a conductive segment CS7, a gate via Vg2, a gate via Vg6, a gate via Vgr, a conductive via Vd2, and a via V07.

For illustration inFIG.6, the active area AA1and the active area AA2are separate from each other. In some embodiments, the active area AA2is implemented by a doped region/area, in order for the formation of the transistors included in the anti-fuse memory cells bit2and bit6as shown inFIG.3. For illustration, the active area AA2is configured for the source/drain of the transistors TP and transistors TR of the anti-fuse memory cells bit2and bit6.

The gates G1-G4are arranged above the active area AA1and the active area AA2, and the gates G1-G4extend to cross over the active area AA1and the active area AA2. Alternatively stated, the anti-fuse memory cells bit1and bit2share the same gate structures of the gates G1and G2, and the anti-fuse memory cells bit5and bit6share the same gate structures of the gates G3and G4. Accordingly, the anti-fuse memory cells bit1and bit2receive the same voltage, current, and/or signal from the program word line WLP0and the read word line WLR0, and the anti-fuse memory cells bit5and bit6receive the same voltage, current, and/or signal from the program word line WLP1and the read word line WLR1.

The conductive segments CS4and CS6are arranged above the gate G1and the gate G4, respectively. In some embodiments, the conductive segments CS4and CS6are disposed directly above the active area AA2. The program word lines WLP0and WLP1are arranged above the conductive segments CS4and CS6, respectively. The read word lines WLR0and WLR1are arranged at two opposite sides of the active area AA1and the active area AA2in the layout view of the layout structure600.

In some embodiments, the gate via Vg2is disposed directly above the active area AA2, and couples the gate G1to the conductive segment CS4. The conductive segment CS4is coupled to the program word line WLP0through a via V04(not shown, for simplicity of illustration) which is similar to the via V01as illustrated inFIG.5, and configured to receive the reading voltage Vr and/or programming voltage Vp as discussed above. In some embodiments, the gate via Vg6is disposed directly above the active area AA2, and couples the gate G4to the conductive segment CS6. The conductive segment CS6is coupled to the program word line WLP1through a via V05(not shown, for simplicity of illustration) which is similar to the via V02as illustrated inFIG.5, and configured to receive the reading voltage Vr and/or programming voltage Vp′ as discussed above.

In some embodiments, the vias V04and V05, that are similar to the vias V01and V02as discussed above inFIG.5, are disposed above and overlap the gate vias Vg2and Vg6, respectively, in the layout view of the layout structure600. Accordingly, inFIG.6, the layout structure600only illustrates the gate vias Vg2and Vg6, for simplicity of illustration. However, the present disclosure is not limited to the embodiments ofFIG.6. Various positions of the vias V04-V05are within the contemplated scope of the present disclosure. For example, in various embodiments, the via V05is disposed at a position where the via V05is not overlapped with the active area AA2in the layout view of the layout structure600.

In some embodiments, the active area AA2is coupled to the conductive segment CS5through the conductive via Vd2, in which the conductive segment CS5is disposed between the gate G2and the gate G3in the layout view of the layout structure600, and the conductive via Vd2is disposed directly above the active area AA2. In some embodiments, the conductive segment CS5is arranged along the direction Y in which the gate G1extends. For illustration, the conductive segment CS5is coupled to the bit line BL2through a via V06(not shown, for simplicity of illustration) which is similar to the via V03as illustrated inFIG.5, and is configured to receive data signals transmitted from the bit line BL2.

In some embodiments, the via V06is disposed above and overlaps the conductive via Vd2in the layout view of the layout structure600. Accordingly, inFIG.6, the layout structure600only illustrates the conductive via Vd2, for simplicity of illustration. However, the present disclosure is not limited to the embodiments ofFIG.6. Various positions of the via V06are within the contemplated scope of the present disclosure. For example, in various embodiments, the via V06is disposed above the conductive segment CS5but is not overlapped with the active area AA2in the layout view of the layout structure600.

For illustration inFIG.6, the bit line BL2is separate from the bit line BL1. The bit line BL1and the bit line BL2are arranged along the direction Y in which the gate G1extends. The program word line WLP0and program word line WLP1are arranged along the direction Y in which the gate G1extends. Alternatively stated, the program word line WLP0, the program word line WLP1, the bit line BL1, and the bit line BL2are substantially arranged in parallel to each other.

With reference toFIG.6, the gate G3is coupled to the conductive segment CS7through a gate via Vgr (also shown inFIG.9). The conductive segment CS7is coupled to the read word line WLR1through the via V07(also shown inFIG.9), and is configured to receive the selecting voltage Vdd as discussed above.

The above configuration of the layout structure600is provided for illustrative purposes. Various configurations of the layout structure600are within the contemplated scope of the present disclosure. For example, in various embodiments, the layout structure600includes additional conductive segments that are coupled to the gate G1and/or G4, which will be discussed below with reference toFIG.7.

FIG.7is a layout structure700of part of the anti-fuse memory cell array300shown inFIG.3, in accordance with various embodiments of the present disclosure. In some embodiments, the layout structure700corresponds to the anti-fuse memory cells bit1, bit2, bit5, and bit6shown inFIG.3. With respect to the embodiments ofFIG.6, like elements inFIG.7are designated with the same reference numbers for ease of understanding. The specific configurations of similar elements, which are already discussed in detail in above paragraphs, are omitted herein for the sake of brevity.

FIG.8is a schematic diagram800illustrating a cross-section view, along a LINE B, of part of the layout structure700shown inFIG.7, in accordance with some embodiments of the present disclosure.FIG.9is a schematic diagram900illustrating a cross-section view, along a LINE C, of part of the layout structure700shown inFIG.7, in accordance with some embodiments of the present disclosure. For ease of understanding, the embodiments with respect toFIG.7are discussed with reference toFIGS.8and9.

Compared to the layout structure600ofFIG.6, the layout structure700ofFIG.7further includes a conductive segment CS8, a conductive segment CS9, a conductive segment CS10, a gate via Vgs1, a gate via Vgs2, and a gate via Vgs3.

For illustration inFIG.7, the conductive segment CS8and the conductive segment CS9are disposed between the active area AA1and the active area AA2in the layout view. The conductive segment CS8is disposed between the anti-fuse memory cells bit1and bit2in the layout view, and the conductive segment CS9is disposed between the anti-fuse memory cells bit5and bit6in the layout view. In other words, the conductive segments CS8and CS9are not overlapped with the active area AA1and the active area AA2in the layout view of the layout structure700.

With reference toFIGS.7and8, the conductive segment CS8is coupled to the gate G1through the gate via Vgs1, and the conductive segment CS8is further coupled to the program word line WLP0through a via V08. The conductive segment CS9is coupled to the gate G4through the gate via Vgs2, and the conductive segment CS9is further coupled to the program word line WLP1through a via V09.

In some embodiments, the vias V08and V09are disposed above and overlap the gate vias Vgs1and Vgs2, respectively, in the layout view of the layout structure700, as well as shown inFIG.8. Accordingly, inFIG.7, the layout structure700only illustrates the gate vias Vgs1and Vgs2, for simplicity of illustration. However, the present disclosure is not limited to the embodiments ofFIGS.7and8. Various positions of the vias V08-V09are within the contemplated scope of the present disclosure. For example, in various embodiments, the via V08is disposed at a position where the via V08is not overlapped with the gate G1in the layout view of the layout structure700.

In some embodiments, the resistance on the current path between the program word line WLP0and the gate G1is associated with the conductive segments and vias between the program word line WLP0and the gate G1. Compared to the layout structure600, the conductive segment CS8, the gate via Vgs1, and the via V08, as discussed above, provide an additional current path for current flowing from the program word line WLP0to the gate G1. Accordingly, additional current is provided from the program word line WLP0through the additional current path to the gate G1. Correspondingly, compared to the layout structure600, the conductive segment CS9, the gate via Vgs2, and the via V09, as discussed above, also provide an additional current path for current flowing from the program word line WLP1to the gate G4. Accordingly, still additional current is provided from the program word line WLP1through the additional current path to the gate G4. With the additional current path associated with the conductive segment CS8and/or CS9, more current is able to flow from the program word line WLP to the corresponding transistor TP, compared to those without the conductive segment CS8and/or CS9. Accordingly, the operations of the above anti-fuse memory cells are able to be further improved, because of the more current.

For illustration inFIG.7, the conductive segment CS10is disposed separate from the active area AA1, and is not overlapped with the active area AA1in the layout view of the layout structure700. The conductive segment CS10is opposite to the conductive segment CS8with respect to the active area AA1.

With reference toFIGS.7and9, the conductive segment CS10is coupled to the gate G1through the gate via Vgs3, and the conductive segment CS10is further coupled to the program word line WLP0through a via V010.

In some embodiments, the vias V010is disposed above and overlap the gate via Vgs3in the layout view of the layout structure700, as well as shown inFIG.9. Accordingly, inFIG.7, the layout structure700only illustrates the gate via Vgs3, for simplicity of illustration. However, the present disclosure is not limited to the embodiments ofFIGS.7and9. Various positions of the via V010are within the contemplated scope of the present disclosure. For example, in various embodiments, the via V010is disposed at a position where the via V010is not overlapped with the gate G1in the layout view of the layout structure700.

In addition to the current paths associated with the conductive segments CS8and CS9as discussed above, the conductive segment CS10, the gate via Vgs3, and the via V010also contribute an additional current path for the current flowing from the program word line WLP0to the gate G1. Accordingly, more current is able to flow from the program word line WLP0to the corresponding transistor TP, compared to those with the conductive segments CS8and CS9, but without the conductive segment CS10. Accordingly, the operations of the above anti-fuse memory cells are able to be further improved, because of the more current.

The above configuration of the layout structure700is provided for illustrative purposes. Various configurations of the layout structure700are within the contemplated scope of the present disclosure. For example, in various embodiments, the layout structure700includes additional conductive segments configured to provide additional current paths for the current or signal transmitting from the program word line WLP0to the gate G1. For another example, in alternative embodiments, one or two of the conductive segments CS8-CS10and the related structures are omitted.

Reference is made toFIG.10.FIG.10is a layout structure1000of part of the anti-fuse memory cell array300ofFIG.3, in accordance with alternative embodiments of the present disclosure. For illustration inFIG.10, the layout structure1000includes a unit UA and a unit UB. As illustrated inFIG.10, the unit UA abuts the unit UB. The unit UA corresponds to the layout structure700ofFIG.7, and accordingly, the configurations of the unit UA correspond to those of the layout structure700ofFIG.7as discussed above and thus are not further detailed herein. Moreover, the unit UB corresponds to a layout structure mirroring to the unit UA. With the layout structure mirroring to the unit UA, the configurations of the unit UB are not further detailed herein, for simplicity of illustration. Because the unit UA, mirroring to the unit UB, corresponds to the layout structure700ofFIG.7, for simplicity of illustration, some reference numbers inFIG.7are omitted inFIG.10.

For illustration inFIG.10, the unit UA includes the anti-fuse memory cells bit1, bit2, bit5, and bit6, and the unit UB includes the anti-fuse memory cells bit3, bit4, bit7, and bit8. The anti-fuse memory cells bit1-bit4share the gate G1and the gate G2, and the anti-fuse memory cells bit5-bit8share the gate G3and the gate G4. In the unit UA, the conductive segment CS7is coupled to the gate G3and thus couples the anti-fuse memory cells bit5-bit6to the read word line WLR1, as discussed above. For illustration inFIG.10, the unit UB also includes a conductive segment CS11, which is arranged with respect to the conductive segment CS7. The conductive segment CS11is coupled to the gate G2and thus couples the anti-fuse memory cells bit3-bit4to the read word line WLR0.

FIG.11is an equivalent circuit1100of part of the anti-fuse memory cell array300inFIG.3, in accordance with some embodiments of the present disclosure. As shown inFIG.11, the equivalent circuit1100corresponds to the anti-fuse memory cells bit1-bit4ofFIG.3and will be discussed in more detail below.

For illustration inFIG.11, the equivalent circuit1100includes resistors Rvg, resistors Rmg, and the anti-fuse memory cells bit1-bit4. Each one of the resistors Rvg indicates the resistance between the program word line WLP0and the gate terminal of the corresponding transistor TP of one of the anti-fuse memory cells bit1-bit4, as discussed above with respect toFIG.2, and/or indicates the resistance contributed by gate vias including, for example, the gate via Vg1ofFIG.5, in some embodiments. Each one of the resistors Rmg indicates the resistance of the gate structure corresponding to the gate terminal of the corresponding transistor TP of one of the anti-fuse memory cells bit1-bit4, as discussed above with respect toFIG.2, and/or indicates the resistance contributed by gate structures including, for example, the gate G1ofFIG.7, in some embodiments. Each one of the anti-fuse memory cells bit1-bit4is connected to the program word line WLP0(also as shown inFIG.3) via one corresponding resistor Rvg. With the gate vias disposed directly above the active areas, as illustrated in the above layout structures, the current flows from the program word line WLP0directly to the anti-fuse memory cells bit1-bit4and does not have to experience the resistors Rmg, as shown inFIG.11.

Reference is made toFIGS.12A-12B.FIG.12Ais a layout structure1200A including the units shown inFIG.10, in accordance with some embodiments of the present disclosure. For simplicity of illustration, inFIG.12A(andFIG.12B), the reference number “A” indicates the unit UA ofFIG.10, and the reference number “B” indicates the unit UB ofFIG.10. The layout structure1200A is configured to have a sequence of A units and/or B units from left to right or from top to bottom, in some embodiments. For illustration ofFIG.12A, from the left to right in the X direction, the units are arranged in a sequence of “AAAA” or “BBBB”. From the top to bottom in the Y direction, the units are arranged in a sequence of “ABAB”. The layout structure1200A includes an array of 4 by 4 units as shown inFIG.12A. The above number of the units of the layout structure1200A is given for illustrative purposes. Various numbers of the units of the layout structure1200A are within the contemplated scope of the present disclosure.

FIG.12Bis a layout structure1200B including the units shown inFIG.10, in accordance with some other embodiments of the present disclosure. Compared to the embodiments ofFIG.12A, inFIG.12B, from the left to right in the X direction, the units are arranged in a sequence of “ABAB” or “BABA”. From the top to bottom in the Y direction, the units are arranged in a sequence of “ABAB” or “BABA”. The above number of the units of the layout structure1200B is given for illustrative purposes. Various numbers of the units of the layout structure1200B are within the contemplated scope of the present disclosure.

In some embodiments, in the layout structures1200A and1200B as discussed above, each A unit (or each B unit) abuts the units surrounding the A unit (or the B unit) and includes structures connected to the surrounding units as discussed with respect toFIG.10.

FIG.13is a layout structure1300including the layout structure1000ofFIG.10, in accordance with some embodiments of the present disclosure. For illustration inFIG.13, the layout structure1300includes two units UA and two units UB, in which the left-side units UA and UB together correspond to the layout structure1000ofFIG.10and thus they are not further detailed herein. The right-side units UA and UB also together correspond to the layout structure1000ofFIG.10, and thus they are not further detailed herein as well. In some embodiments, the left-side units UA and UB do not abut the right-side units UA and UB, as shown inFIG.13. However, the configuration of the layout structure1300inFIG.13is given for illustrative purposes. Various configuration of the layout structure1300are within the contemplated scope of the present disclosure. For example, in various embodiments, with reference toFIG.12A, the layout structure1300corresponds to an array of 2 by 2 units (i.e., ABAB) that abut each other, for example in the left-top corner, of the layout structure1200A.

FIG.14is a flow chart of a method1400for generating an anti-fuse memory cell array, in accordance with some embodiments of the present disclosure. For ease of understanding, the method1400is described with reference toFIGS.1-13. However, the method1400is not limited to being applied to generate the above layout structures. The method1400is able to be applied to generate any suitable layout structure. For illustration inFIG.14, the method1400includes operations S1401, S1402, S1403, S1404, and S1405, which will be discussed in detail below.

In operation S1401, the active areas AA1and AA2are arranged to be separate from each other and extend in the X direction, for example as shown inFIG.7.

In operation S1402, with reference toFIG.7, the gates G1-G4are generated to extend in the Y direction and cross over the active areas AA1and AA2. As discussed above, the gates G1and G4correspond to the gate terminals of transistors TP, and the gates G2and G3correspond to the gate terminals of transistors TR.

In operation S1403, with reference toFIG.7, the gate vias Vg1-Vg2are generated on the gate G1, and the gate vias Vg5-Vg6are generated on the gate G4. The gate vias Vg1and Vg5are disposed directly above the active area AA1, and the gate vias Vg2and Vg6are disposed directly above the active area AA2.

In operation S1404, with reference toFIG.7, the conductive segments CS1and CS4are generated to be disposed directly above the active areas AA1and AA2, respectively, and the conductive segments CS1and CS4couple the gate G1through the gate vias Vg1-Vg2to the program word line WLP0for receiving the programming voltage Vp.

In operation S1405, with reference toFIG.7, the conductive segments CS3and CS6are generated to be disposed directly above the active areas AA1and AA2, respectively, and the conductive segments CS3and CS6couple the gate G4through the gate vias Vg5-Vg6to the program word line WLP1for receiving another programming voltage Vp′. In some embodiments, the programming voltage Vp is different form the programming voltage Vp′. In some other embodiments, the programming voltage Vp is the same as the programming voltage Vp′.

In some embodiments, with reference toFIG.7, the method1400further includes the following operations of: generating the gate via Vgs1on the gate G2, between the active areas AA1and AA2, to couple the gate G2to the read word line WLR0for receiving the reading voltage Vdd; and generating the gate via Vgs2on the gate G3, between the active areas AA1and AA2, to couple the gate G3to the read word line WLR1for receiving the reading voltage Vdd′. In some embodiments, the reading voltage Vdd is different form the reading voltage Vdd′. In some other embodiments, the reading voltage Vdd is the same as the reading voltage Vdd′.

In some embodiments, with reference toFIG.7, the method1400further includes the following operations of: generating the gate vias Vgs1, Vgs3each disposed between the active areas AA1and AA2, on the gate G1, to couple the gate G1to the program word line WLP0for receiving the programming voltage Vp; and generating the gate via Vgs2disposed between the active areas AA1and AA2, on the gate G4, to couple the gate G4to the program word line WLP1for receiving the programming voltage Vp′.

In some embodiments, with reference toFIG.7, the method1400further includes the following operations of: generating conductive segments CS8and CS10each disposed between the active areas AA1and AA2to couple the gate G1to the program word line WLP0for receiving the programming voltage Vp; and generating the conductive segment CS9disposed between the active areas AA1and AA2to couple the gate G4to the program word line WLP1for receiving the programming voltage Vp′.

In some embodiments, with reference toFIG.7, the method1400further includes the operation of generating the conductive segments CS2and CS5that are separate from each other and disposed directly above the active areas AA1and AA2, respectively. The conductive segments CS2and CS5are arranged along the Y direction and are configured to receive data signals different from each other.

The above illustrations include exemplary operations, but the operations are not necessarily performed in the order shown. Operations may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of various embodiments of the present disclosure.

Reference is made toFIG.15.FIG.15is a block diagram of an integrated circuit (IC) device design system1500, in accordance with some embodiments. One or more operations of the method1400, as discussed above with respect toFIG.14, are implementable using the IC device design system1500, in accordance with some embodiments.

In some embodiments, the IC device design system1500is a computing device including a hardware processor1502and a non-transitory computer-readable storage medium (also referred to as storage medium)1504. Non-transitory computer-readable storage medium1504, amongst other things, is encoded with, i.e., stores, computer program code1506, i.e., a set of executable instructions. Execution of computer program code1506by hardware processor1502represents (at least in part) an IC device design system which implements a portion or all of, e.g., the method1400discussed above with respect toFIG.14(hereinafter, the noted processes and/or methods).

Processor1502is electrically coupled to non-transitory computer-readable storage medium1504via a bus1508. Processor1502is also electrically coupled to an I/O interface1510and a fabrication tool1530by bus1508. A network interface1512is also electrically connected to processor1502via bus1508. Network interface1512is connected to a network1514, so that processor1502and non-transitory, computer-readable storage medium1504are capable of being connected to external elements via network1514. Processor1502is configured to execute computer program code1506encoded in non-transitory computer-readable storage medium1504in order to cause IC device design system1500to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, processor1502is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit.

In one or more embodiments, non-transitory computer-readable storage medium1504is an electronic, magnetic, optical, electromagnetic, infrared, and/or a semiconductor system (or apparatus or device). For example, non-transitory computer-readable storage medium1504includes a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or an optical disk. In one or more embodiments using optical disks, non-transitory computer-readable storage medium1504includes a compact disk-read only memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or a digital video disc (DVD).

In one or more embodiments, non-transitory computer-readable storage medium1504stores computer program code1506configured to cause IC device design system1500to be usable for performing a portion or all of the noted processes and/or method1400. In one or more embodiments, non-transitory computer-readable storage medium1504also stores information which facilitates performing a portion or all of the noted processes and/or methods. In various embodiments, non-transitory computer-readable storage medium1504stores one or a combination of at least one IC layout diagram1520or at least one design specification1522, each of which corresponds to the layout structures as discussed above with respect to the method1400andFIGS.1-13, or at least one layout design applicable to manufacture the corresponding layout structure400,600,700,1000,1200A,1200B, or1300, as discussed above.

In some embodiments, non-transitory computer-readable storage medium1504stores instructions (e.g., computer program code1506) for interfacing with manufacturing machines. The instructions (e.g., computer program code1506) enable processor1502to generate manufacturing instructions readable by the manufacturing machines to effectively implement method1400during a manufacturing process.

IC device design system1500includes I/O interface1510. I/O interface1510is coupled to external circuitry. In various embodiments, I/O interface1510includes one or a combination of a keyboard, keypad, mouse, trackball, trackpad, display, touchscreen, and/or cursor direction keys for communicating information and commands to and/or from processor1502.

IC device design system1500also includes network interface1512coupled to processor1502. Network interface1512allows system1500to communicate with network1514, to which one or more other computer systems are connected. Network interface1512includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion or all of the noted processes and/or methods is implemented in two or more systems1500.

The IC device design system1500also includes the fabrication tool1530coupled to the processor1502. The fabrication tool1530is configured to fabricate integrated circuits, including, for example, the layout structure400illustrated inFIG.4, the layout structure600illustrated inFIG.6, the layout structure700illustrated inFIG.7, the layout structure1000illustrated inFIG.10, and the layout structure1300illustrated inFIG.13, based on the design files processed by the processor1502and/or the IC layout designs as discussed above.

IC device design system1500is configured to receive information through I/O interface1510. The information received through I/O interface1510includes one or a combination of at least one design rule instructions, at least one set of criteria, at least one design rule, at least one DRM, and/or other parameters for processing by processor1502. The information is transferred to processor1502via bus1508. IC device design system1500is configured to transmit and/or receive information related to a user interface through I/O interface1510.

In some embodiments, a portion or all of the noted processes and/or method1400is implemented as a standalone software application for execution by a processor. In some embodiments, a portion or all of the noted processes and/or method1400is implemented as a software application that is a part of an additional software application. In some embodiments, a portion or all of the noted processes and/or method1400is implemented as a plug-in to a software application. In some embodiments, at least one of the noted processes and/or method1400is implemented as a software application that is a portion of an EDA tool. In some embodiments, an IC layout diagram or layout design is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generating tool.

In some embodiments, the processes are realized as functions of a program stored in a non-transitory computer-readable recording medium. Examples of a non-transitory computer-readable recording medium include, but are not limited to, external/removable and/or internal/built-in storage or memory unit, e.g., one or more of an optical disk, such as a DVD, a magnetic disk, such as a hard disk, a semiconductor memory, such as a ROM, a RAM, a memory card, and the like.

By being usable to implement one or more operations of method1400, as discussed above with respect toFIGS.1-13, IC device design system1500enables the benefits discussed above with respect to method1400.

Reference is made toFIG.16.FIG.16is a block diagram of IC manufacturing system1600, and an IC manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, based on a layout diagram/design, at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is fabricated using the manufacturing system1600.

InFIG.16, IC manufacturing system1600includes entities, such as a design house1620, a mask house1630, and an IC manufacturer/fabricator (“fab”)1650, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device1660. The entities in system1600are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house1620, mask house1630, and IC fab1650is owned by a single larger company. In some embodiments, two or more of design house1620, mask house1630, and IC fab1650coexist in a common facility and use common resources.

Design house (or design team)1620generates an IC design layout diagram (also noted as IC design inFIG.16)1622based on the method1400, as discussed above with respect toFIGS.1-13. IC design layout diagram1622includes various geometrical patterns that correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device1660to be fabricated. The various patterns are combined to form various IC features. For example, a portion of IC design layout diagram1622includes various IC features, such as an active region, gate electrode, source and drain, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house1620implements a proper design procedure including method1400, discussed above with respect toFIGS.1-13, to form IC design layout diagram1622. The design procedure includes one or more of logic design, physical design or place and route. IC design layout diagram1622is presented in one or more data files having information of the geometrical patterns. For example, IC design layout diagram1622can be expressed in a GDSII file format or DFII file format.

Mask house1630includes mask data preparation (also noted as data preparation inFIG.16)1632and mask fabrication1644. Mask house1630uses IC design layout diagram1622to manufacture one or more masks to be used for fabricating the various layers of IC device1660according to IC design layout diagram1622. Mask house1630performs mask data preparation1632, where IC design layout1622is translated into a representative data file (“RDF”). Mask data preparation1632provides the RDF to mask fabrication1644. Mask fabrication1644includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle) or a semiconductor wafer1652. The design layout diagram1622is manipulated by mask data preparation1632to comply with particular characteristics of the mask writer and/or requirements of IC fab1650. InFIG.16, mask data preparation1632and mask fabrication1644are illustrated as separate elements. In some embodiments, mask data preparation1632and mask fabrication1644can be collectively referred to as mask data preparation.

In some embodiments, mask data preparation1632includes optical proximity correction (OPC) which uses lithography enhancement techniques to compensate for image errors, such as those that can arise from diffraction, interference, other process effects and the like. OPC adjusts IC design layout diagram1622. In some embodiments, mask data preparation1632includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

In some embodiments, mask data preparation1632includes a mask rule checker (MRC) that checks the IC design layout diagram1622that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram1622to compensate for limitations during mask fabrication1644, which may undo part of the modifications performed by OPC in order to meet mask creation rules.

In some embodiments, mask data preparation1632includes lithography process checking (LPC) that simulates processing that will be implemented by IC fab1650to fabricate IC device1660. LPC simulates this processing based on IC design layout diagram1622to create a simulated manufactured device, such as IC device1660. The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC are be repeated to further refine IC design layout diagram1622.

It should be understood that the above description of mask data preparation1632has been simplified for the purposes of clarity. In some embodiments, mask data preparation1632includes additional features such as a logic operation (LOP) to modify the IC design layout diagram1622according to manufacturing rules. Additionally, the processes applied to IC design layout diagram1622during mask data preparation1632may be executed in a variety of different orders.

After mask data preparation1632and during mask fabrication1644, a mask or a group of masks are fabricated based on the modified IC design layout diagram1622. In some embodiments, mask fabrication1644includes performing one or more lithographic exposures based on IC design layout diagram1622. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle) based on the modified IC design layout diagram1622. Mask can be formed in various technologies. In some embodiments, mask is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask version of mask includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask is formed using a phase shift technology. In a phase shift mask (PSM) version of mask, various features in the pattern formed on the phase shift mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication1644is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in semiconductor wafer1652, in an etching process to form various etching regions in semiconductor wafer1652, and/or in other suitable processes.

IC fab1650includes wafer fabrication. IC fab1650is an IC fabrication business that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, IC Fab1650is a semiconductor foundry. For example, there may be a manufacturing facility for the front end fabrication of a plurality of IC products (front-end-of-line (FEOL) fabrication), while a second manufacturing facility may provide the back end fabrication for the interconnection and packaging of the IC products (back-end-of-line (BEOL) fabrication), and a third manufacturing facility may provide other services for the foundry business.

IC fab1650uses mask(s) fabricated by mask house1630to fabricate IC device1660. Thus, IC fab1650at least indirectly uses IC design layout diagram1622to fabricate IC device1660. In some embodiments, semiconductor wafer1652is fabricated by IC fab1650using mask(s) to form IC device1660. In some embodiments, the IC fabrication includes performing one or more lithographic exposures based at least indirectly on IC design layout diagram1622. Semiconductor wafer1652includes a silicon substrate or other proper substrate having material layers formed thereon. Semiconductor wafer1652further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps).

In this document, the term “coupled” may also be termed as “electrically coupled,” and the term “connected” may be termed as “electrically connected”. “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other.

Also disclosed is a semiconductor device that includes anti-fuse cells. The anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. The first gate and the second gate are separate from each other. The first gate and the second gate extend to cross over the first active area. The at least one first gate via is coupled to the first gate and disposed directly above the first active area. The at least one second gate via is coupled to the second gate. The first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.

Also disclosed is a semiconductor device that includes an anti-fuse cell array. The anti-fuse cell array includes anti-fuse cells that are arranged in columns and rows. The anti-fuse cells include active areas, gates, and first conductive segments. The active areas are separate from each other and extend in a first direction. The gates are separate from each other. Each one of the gates extends in a second direction and crosses over the active areas. The first conductive segments are disposed directly above the active areas, respectively. The first conductive segments couple a first gate of the gates through first gate vias to a first word line for receiving a first programming voltage.

Also disclosed is a semiconductor device that includes a first word line, a first active area, a first gate, a second gate, a third gate, a first gate via, a second gate via, a third gate via and a fourth gate via. The first active area extends along a first direction. The first gate crosses over the first active area and extends along a second direction. The second gate crosses over the first active area and extends along the second direction. The third gate is disposed between the first gate and the second gate, crosses over the first active area and extends along the second direction. The first gate via is disposed directly above the first active area and is configured to couple the first gate to the first word line. The second gate via is disposed directly above the first gate and is configured to couple the first gate to the first word line. The third gate via is disposed directly above the third gate and is aligned with the second gate via along the first direction. The fourth gate via is disposed directly above the second gate and is aligned with the first gate via along the first direction.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.