Patent ID: 12259973

DETAILED DESCRIPTION

Examples described in this disclosure relate to systems and methods for flush plus reload cache side-channel attack mitigation. Certain examples relate to flush plus reload cache side-channel attack mitigation in a computing system or a multi-tenant computing system. The multi-tenant computing system may be a public cloud, a private cloud, or a hybrid cloud. The public cloud includes a global network of servers that perform a variety of functions, including storing and managing data, running applications, and delivering content or services, such as streaming videos, electronic mail, office productivity software, or social media. The servers and other components may be located in data centers across the world. While the public cloud offers services to the public over the Internet, businesses may use private clouds or hybrid clouds. Both private and hybrid clouds also include a network of servers housed in data centers. Compute entities may be executed using compute and memory resources of the data center. As used herein, the term “compute entity” encompasses, but is not limited to, any executable code (in the form of hardware, firmware, software, or in any combination of the foregoing) that implements a functionality, a virtual machine, an application, a service, a micro-service, a container, or a unikernel for serverless computing. Alternatively, compute entities may be executing on hardware associated with an edge-compute device, on-premises servers, or other types of systems, including communications systems, such as base stations (e.g., 5G or 6G base stations).

Caches help alleviate the long latency associated with access to main memories (e.g., double data rate (DDR) dynamic random access memory (DRAM)) by providing data with low latency. A processor may have access to a cache hierarchy, including L1caches, L2caches, and L3caches, where the L1caches may be closest to the processing cores and the L3caches may be the furthest. Data accesses may be made to the caches first and if the data is found in the cache, then it is viewed as a hit. If the data, however, is not found in the cache, then it is viewed as a miss, and the data will need to be loaded from the main memory (e.g., the DRAM). Unfortunately, the timing difference between the cache hit and a cache miss can be used as a side-channel by an adversary to infer the access pattern and obtain unauthorized information from the system. Such cache attacks have been demonstrated to leak sensitive information like encryption keys or other credentials and secrets.

FIG.1is a block diagram of a system100in accordance with one example. Each system may include compute resources (e.g., a processor) and memory resources (e.g., caches and system memory). As an example, system100may include a compute node110and a host operating system190supported by compute node110. Compute node110may include a central processing unit (CPU)120, which in turn may include several processing cores and different cache levels. In this example, CPU120may include core0122, core1132, and core N142, where N is an integer equal to the number of cores in the CPU, which in this example may range from 3 to 256. Core0122may have exclusive access to level1and level2caches (e.g., L1cache124and L2cache126). Core1132may have exclusive access to level1and level2caches (e.g., L1cache134and L2cache136). Core N142may have exclusive access to level1and level2caches (e.g., L1cache144and L2cache146). Each of the cores may further have access to a shared last level cache (LLC)150, which may be viewed as the level3cache in the cache hierarchy. AlthoughFIG.1shows a certain hierarchy of caches, CPU120may include caches that are non-hierarchical and are arranged differently.

With continued reference toFIG.1, CPU120may further include a system level cache controller (e.g., SLCC152) for managing transactions between the caches and the system memory. SLCC152may be coupled via bus164to memory controller160(e.g., a DRAM controller). Memory controller160may be coupled to system memory172via bus174. System memory172may be any combination of non-volatile storage or volatile storage (e.g., flash memory, DRAM, SRAM, or other types of memories). A bus system180may further couple CPU120and system memory172to other components of compute node110, including data storage182, sensors184, and networking interfaces186. Sensors184may include telemetry or other types of sensors configured to detect, and/or receive, information (e.g., memory usage by various virtual machines being executed by various compute nodes in a data center). Sensors184may further include sensors configured to sense conditions associated with CPUs, memory or other storage components, FPGAs, motherboards, baseboard management controllers, or the like. Network interfaces186may include communication interfaces, such as Ethernet, cellular radio, Bluetooth radio, UWB radio, or other types of wireless or wired communication interfaces. In addition, although not shown, compute node110may further include I/O port(s) such as Ethernet ports, Fiber-optic ports, wireless ports, or other communication or diagnostic ports. Although each compute node inFIG.1is shown is having a single CPU, each compute node may include additional CPUs, and other devices, such as graphics processor units (GPU)s, field programmable gate arrays (FPGA)s, application specific integrated circuits (ASIC)s, or other devices. In addition, each compute node110may have system memory172organized as memory modules. Examples of such memory modules include, but are not limited to, dual-in-line memory modules (DIMMs) or single-in-line memory modules (SIMMs). Memory included in these modules may be dynamic random access memory (DRAM), flash memory, static random access memory (SRAM), phase change memory, magnetic random access memory, or any other type of memory technology.

Still referring toFIG.1, each compute node110may be configured to execute several compute entities. In this example, host OS190may support several containers (e.g., container1192, container2194, and container M196, where M is a positive integer). In this example, the containers may be light weight virtual interface modules that may share the host OS190to support other applications. In this manner, these containers may share a significant percentage of the codebase, including shared libraries, making the containers susceptible to side-channel attacks through the caches associated with a CPU executing the shared libraries. Other compute entities that share libraries or other code may similarly be susceptible to similar side-channel attacks.

In one example, compute node110may be part of a data center. As used in this disclosure, the term data center may include, but is not limited to, some or all of the data centers owned by a cloud service provider, some or all of the data centers owned and operated by a cloud service provider, some or all of the data centers owned by a cloud service provider that are operated by a customer of the service provider, any other combination of the data centers, a single data center, or even some clusters in a particular data center. In one example, each cluster may include several identical compute nodes. Thus, a cluster may include compute nodes including a certain number of CPU cores and a certain amount of memory. Instead of compute nodes, other types of hardware such as edge-compute devices, on-premises servers, or other types of systems, including communications systems, such as base stations (e.g., 5G or 6G base stations) may also be used. AlthoughFIG.1shows system100as having a certain number of components, including a compute node and memory components, arranged in a certain manner, system100may include additional or fewer components, arranged differently.

As explained earlier, the timing difference between a cache hit and a cache miss can be used as a side-channel by an attacker to infer the access pattern and obtain unauthorized information from the system. Such cache attacks have been demonstrated to leak sensitive information like encryption keys or other credentials and secrets. One such attack is referred to as the flush plus reload attack. Referring back toFIG.1, the flush plus reload attack is described assuming an attacker A is accessing compute node110ofFIG.1through one of the containers and a victim V is also accessing compute node110ofFIG.1through one of the containers. This example further assumes that attacker A and victim V map to a shared library (e.g., a cryptographic library for executing AES-cryptographic functions) stored in system memory172ofFIG.1. As part of faster access to the shared library, the executable code corresponding to the shared library may be stored in the cache hierarchy associated with CPU120of compute node110ofFIG.1. As part of the flash plus reload attack, once the shared library has been cached, attacker A flushes the shared library from the cache to the system memory. As an example, for the ×86-based CPUs the flush operation may be accomplished by using the CLFLUSH instruction, which can be executed in the user mode. The CLFLUSH instruction flushes a given cache line from all caching hierarchy (e.g., L1cache, L2cache, and the last-level cache (LLC)) and writes back any dirty data to the system memory. Using the CLFLUSH instruction, the attacker can mount timing attacks on the victim.

Next, after flushing the cache, attacker A waits for a sampling interval (e.g., one microsecond, one millisecond, or some other appropriate amount of time for a certain CPU). After the expiration of the sampling interval, attacker A reload the shared library. If the reload operation takes a short amount of time, then attacker A knows that victim V had accessed the shared library from the memory. As part of that access by victim V, the cache controller loads the shared library into the associated caches. Alternatively, if the reload operation takes a longer amount of time, then attacker A knows that victim V has not accessed the shared library during the sampling interval. Attacker A can then reload the shared library, flush it again, wait for the sampling interval, and decipher whether victim V accessed the shared library. By repeatedly flushing and reloading the shared library, attacker A can have access to a plot of samples over time and can use those samples to discern patterns. The patterns may provide sufficient information to attacker A over time to determine the cryptographic key victim V is using. Existing solutions to the flush plus reload attack are inferior for several reasons. As an example, a solution involves tracking zombie cache lines. This solution, however, is an invasive and complex solution to implement. As an example, this solution requires changes to the CPU hardware and thus it cannot be used with the existing CPUs. In addition, the tracking of zombie cache lines not only impacts the performance of the CPU but also uses up storage associated with the CPU.

To address the flush plus reload attack, a solution involving using a microcode patch to autonomously map all cache flush instructions (e.g., CLFLUSH instructions) to a cache write back instruction (e.g., CLWB instructions) is described. Like the CLFLUSH instruction, the CLWB instruction writes back dirty data to memory. However, unlike the CLFLUSH instruction, the CLWB instructions retains any non-modified copies of the line in the cache hierarchy. As a result, the attacker (e.g., attacker A described earlier) can no longer influence the access timing for the victim (e.g., victim V described earlier), thus defeating the flush plus reload attack.

FIG.2shows a diagram of a processor200that may include functionality to remap the CLFLUSH instruction to the CLWB instruction. Processor200may be any complex instruction set computer (CISC) ISA compatible CPU or another type of processor. Processor200includes a fetch unit210, an instruction cache220, a microcode unit230, a decode unit240, and an execution unit250. Additional aspects of processor200, including branch prediction logic, reorder logic, and issue logic, are not shown. Fetch unit210fetches instructions (e.g., using the addresses provided by the branch prediction logic (not shown)) and stores the fetched instructions into instruction cache220. Instructions are then provided to microcode unit230, which translates the fetched instructions (e.g., the CLFLUSH instruction) into micro-instructions. A microcode patch may be uploaded to the CPU (e.g., CPU120ofFIG.1) by the firmware (e.g., the BIOS or the UEFI) associated with the CPU during the boot process, After uploading, the microcode patch may be stored in a microcode patch RAM associated with microcode unit230.

The microcode patch may contain a number of micro-instructions corresponding to any instruction (e.g., the CLFLUSH instruction) that is being patched. As explained with respect toFIG.3, when the CLFLUSH instruction is encountered by microcode unit230, the micro-instructions for the CLFLUSH instructions are obtained from the microcode patch RAM. In one example, the microcode instructions in microcode patch RAM correspond to the CLWB instruction even when the CLFLUSH instruction is encountered by microcode unit310. This, in turn, results in a remapping of the CLFLUSH instruction as a CLWB instruction. Using similar logic, any other cache flush instruction similar to the CLFLUSH instruction may be remapped as a cache write back instruction similar to the CLWB instruction. The micro-instructions are then decoded by decode unit240and the cache write back operation is performed instead of the cache flush operation. This results in mitigating the flush plus reload technique described earlier. AlthoughFIG.2shows processor200as including certain components arranged in a certain way, processor200may include additional or fewer components that are arranged differently. In addition, althoughFIG.2describes the mitigation of the flush plus reload technique with respect to the CLFLUSH instruction, any other cache flush instruction may also be processed in an equivalent way to mitigate the flush plus reload side-channel attack.

FIG.3shows an example implementation of a microcode unit300included in processor200ofFIG.2. Microcode unit300(e.g., corresponding to microcode unit230ofFIG.2) may include the logic, registers, and other components required for remapping a cache line instruction (e.g., the CLFLUSH instruction) to a cache write back instruction (e.g., the CLWB instruction). In this example, microcode unit300may include a microcode unit input stage310, a sequencer320, a next address register330, match registers340, a comparator350, a lookup table360, a multiplexer370, a microcode read only memory (ROM)380, and a microcode patch random access memory (RAM)390. As explained earlier a microcode patch for remapping the CLFLUSH instruction to the micro-instructions corresponding to the CLWB instruction may be loaded into microcode patch RAM390. Microcode input unit stage310may calculate the address (e.g., the address for the micro-instructions stored in microcode ROM380or microcode patch RAM390) for the first micro-instruction that corresponds to the instruction received from instruction cache220of FIG.

With continued reference toFIG.3, an instruction (e.g., the CLFLUSH instruction) may require the decoding of a set of micro-instructions before being decoded. Sequencer320controls the multiplexer370to supply the correct next address to next address register330. Sequencer320may be implemented using finite state machines or other logic. Sequencer320ensures that all of the micro-instructions corresponding to an instruction are processed in sequence. The address stored in next address register330is provided to comparator350. Comparator350compares the address provided by next address register330with the addresses stored in match registers340. If there is a match between the address and any of the addresses stored in match register340, then a patch from microcode patch RAM390is implemented. In this example, when there is a match, a signal from comparator350is used to select an address from lookup table360for microcode patch RAM390. Lookup table360may be implemented as a programmable logic array or using other logic. Sequencer320controls multiplexer370to feed the looked up address from lookup table360for further processing. As a result, instead of the micro-instructions located in microcode ROM380, the micro-instructions located in microcode patch RAM390are provided to the decoder (e.g., decode unit240ofFIG.2). Thus, in this example, match registers340include an entry that allows for the micro-instructions corresponding to the CLWB instruction be supplied from microcode patch RAM390when processing the CLFLUSH instruction. This, in turn, results in a mapping of the CLFLUSH instruction to the CLWB instruction. AlthoughFIG.3shows microcode unit300as having a certain number of components that are arranged in a certain manner, microcode unit300may include additional or fewer components that are arranged differently. In addition, althoughFIG.3describes the mitigation of the flush plus reload technique with respect to the CLFLUSH instruction, any other cache flush instruction may also be processed in an equivalent way to mitigate the flush plus reload side-channel attack.

Among other advantages, the example solutions described herein are compatible with existing x86 processors and the related functionality. The CLFLUSH instruction was designed primarily for non-coherent direct memory access (DMA) devices (e.g., Peripheral Component Interconnect Express (PCIe) devices) that may write to the system memory directly. In such an environment, if an application wants to read the latest data, it will first execute the CLFLUSH instruction, let the non-coherent DMA device write the data to the system memory, and then perform a load operation. This load instruction would result in a miss with respect to the cache and the latest data will be obtained from the system memory (e.g., the DRAM). However, over time, modern CPUs (e.g., Intel and AMD CPUs) have implemented coherent DMA. This means that when a non-coherent DMA device updates data (e.g., data in the form of a cache line), it gets updated not just in the system memory but also in any associated CPU caches. Advantageously, this automatic update eliminates the need for using the CLFLUSH instruction.

In addition, even if the CLFLUSH instruction is present in legacy code, the automatic update also makes it safe to remap the CLFLUSH instruction to the CLWB instruction. The CLFLUSH instruction may also be used for checkpointing and flushing the contents of volatile memory to persistent memory (e.g., flash memory). However, because the CLWB instruction flushes any dirty cache lines to the system memory (e.g., the DRAM), the use of the CLWB instruction (instead of the CLFLUSH instruction) does not create any issues.

FIG.4shows a data center400for implementing flush plus reload cache side-channel attack mitigation in accordance with one example. As an example, data center400may include several clusters of racks including platform hardware, such as compute resources, storage resources, networking resources, or other types of resources. Compute resources may be offered via compute nodes provisioned via servers that may be connected to switches to form a network. The network may enable connections between each possible combination of switches. Data center400may include server1410and serverN430each of which may be implemented using similar functionality as described earlier for compute node110ofFIG.1. Data center400may further include data center related functionality460, including deploymentimonitorina470, directory/identity services472, load balancing474, data center controllers476(e.g., software defined networking (SDN) controllers and other controllers), and routers/switches478. Server1410may include CPU(s)411, host hypervisor412, memory413, storage interface controller(s) (SIC(s))414, cooling415, network interface controller(s) (NIC(s))416, and storage disks417and418. ServerN430may include CPU(s)431, host hypervisor432, memory433, storage interface controller(s) (SIC(s))434, cooling435, network interface controller(s) (NIC(s))436, and storage disks437and438. Server1410may be configured to support virtual machines (or containers), including VM1419, VM2420, and VMN421. The virtual machines may further be configured to support applications, such as APP1422, APP2423, and APPN424. ServerN430may be configured to support virtual machines (or containers), including VM1439, VM2440, and VMN441. The virtual machines may further be configured to support applications, such as APP1442, APP2443, and APPN444. Each of host hypervisors412and432may reference shared libraries that may be used to support any compute entities, including the containers described earlier with respect toFIG.1.

With continued reference toFIG.4, in one example, data center400may be enabled for multiple tenants using the Virtual eXtensible Local Area Network (VXLAN) framework. Each virtual machine (VM) may be allowed to communicate with VMs in the same VXLAN segment. Each VXLAN segment may be identified by a VXLAN Network Identifier (VNI). AlthoughFIG.4shows data center400as including a certain number of components arranged and coupled in a certain way, it may include fewer or additional components arranged and coupled differently. In addition, the functionality associated with data center800may be distributed or combined, as needed.

FIG.5shows a flow chart500of an example method for mitigating a side-channel timing attack in a system including a processor having at least one cache. In one example, the steps associated with this method may be executed by various components of the systems described earlier (e.g., system100ofFIG.1and processor200ofFIG.2). Step510may include receiving a first instruction, where the first instruction, when executed by the processor, is configured to flush at least one cache line from the at least one cache associated with the processor. As an example, this step may include receiving the CLFLUSH instruction as the first instruction. As described earlier, an attacker may use the flush plus reload attack to steal another user's information from the cache associated with the processor.

Step520may include, prior to execution of the first instruction by the processor, automatically mapping the first instruction to a second instruction such that the at least one cache line is not flushed from the at least one cache even in response to receiving the first instruction. As an example, this step may include receiving the CLFLUSH instruction as the first instruction and automatically mapping the CLFLUSH instruction to the second instruction (e.g., the CLWB instruction). As explained earlier, a microcode patch may be applied to the processor by loading such a patch during boot time. The microcode patch itself may be loaded from a flash memory associated with a computing system including the processor. Additional details regarding one way to apply the patch are provided earlier with respect toFIG.3.

FIG.6shows a flow chart600of another example method for mitigating a side-channel timing attack in a system including a processor having at least one cache. In one example, the steps associated with this method may be executed by various components of the systems described earlier (e.g., system100ofFIG.1and processor200ofFIG.2). Step610may include receiving a first instruction, where the first instruction, when executed by the processor, is configured to flush at least one cache line from the at least one cache associated with the processor. As an example, this step may include receiving the CLFLUSH instruction as the first instruction. As described earlier, an attacker may use the flush plus reload attack to steal another users information from the cache associated with the processor.

Step620may include, prior to execution of the first instruction by the processor, a microcode unit associated with the processor automatically mapping the first instruction to a second instruction such that the at least one cache line is not flushed from the at least one cache even in response to receiving the first instruction, wherein the automatically mapping the first instruction to the second instruction comprises applying a microcode patch to the processor. As an example, this step may include receiving the CLFLUSH instruction as the first instruction and a microcode unit (e.g., microcode unit230ofFIG.2) automatically mapping the CLFLUSH instruction to the second instruction (e.g., the CLWB instruction). As explained earlier, a microcode patch may be applied to the processor by loading such a patch during boot time. The microcode patch itself may be loaded from a flash memory associated with a computing system including the processor. Additional details regarding one way to apply the patch are provided earlier with respect toFIG.3.

In conclusion, the present disclosure relates to a method for mitigating a side-channel timing attack in a system including a processor having at least one cache. The method may include receiving a first instruction, where the first instruction, when executed by the processor, is configured to flush at least one cache line from the at least one cache associated with the processor. The method may further include, prior to execution of the first instruction by the processor, automatically mapping the first instruction to a second instruction such that the at least one cache line is not flushed from the at least one cache even in response to receiving the first instruction.

The processor may include a microcode unit. The automatically mapping the first instruction to the second instruction may include the microcode unit applying a microcode patch to the processor. The first instruction may comprise a cache flush instruction and the second instruction may comprise a cache write back instruction.

The microcode patch may include micro-instructions for the cache write back instruction such that an application of the microcode patch to the processor results in micro-instructions for the cache write back instruction being processed by the processor instead of the micro-instructions for the cache flush instruction. The at least one cache may include a hierarchical arrangement of caches, and when executed each of the cache flush instruction and the cache write back instruction may write back dirty cache lines to a memory associated with the processor but unlike the cache flush instruction, the cache write back instruction may retain any non-modified copies of cache lines in the hierarchical arrangement of caches. The side-channel timing attack may comprise a flush plus reload attack.

In another example, the present disclosure relates to a processor having at least one cache. The processor may include circuitry configured to receive a first instruction, wherein the first instruction, when executed by the processor, is configured to flush at least one cache line from the at least one cache associated with the processor. The circuitry may further be configured to prior to execution of the first instruction by the processor, automatically map the first instruction to a second instruction such that the at least one cache line is not flushed from the at least one cache even in response to receiving the first instruction.

The circuitry may comprise a microcode unit. The circuitry may be configured to automatically map the first instruction to the second instruction by applying a microcode patch to the processor. The first instruction may comprise a cache flush instruction and the second instruction may comprise a cache write back instruction.

The microcode patch may include micro-instructions for the cache write back instruction such that an application of the microcode patch to the processor results in micro-instructions for the cache write back instruction being processed by the processor instead of the micro-instructions for the cache flush instruction. The at least one cache may include a hierarchical arrangement of caches, and when executed each of the cache flush instruction and the cache write back instruction may write back dirty cache lines to a memory associated with the processor but unlike the cache flush instruction, the cache write back instruction may retain any non-modified copies of cache lines in the hierarchical arrangement of caches. The side-channel timing attack may comprise a flush plus reload attack.

In yet another example, the present disclosure relates to a method for mitigating a side-channel timing attack in a system including a processor having at least one cache. The method may include receiving a first instruction, where the first instruction, when executed by the processor, is configured to flush at least cache line from the at least one cache associated with the processor. The method may further include prior to execution of the first instruction by the processor, a microcode unit associated with the processor automatically mapping the first instruction to a second instruction such that the at least one cache line is not flushed from the at least one cache even in response to receiving the first instruction, where the automatically mapping the first instruction to the second instruction comprises applying a microcode patch to the processor.

The first instruction may comprise a cache flush instruction and the second instruction may comprise a cache write back instruction. The microcode patch may comprise micro-instructions for the cache write back instruction such that an application of the microcode patch to the processor results in micro-instructions for the cache write back instruction being processed by the processor instead of the micro-instructions for the cache flush instruction.

The at least one cache may include a hierarchical arrangement of caches, and when executed each of the cache flush instruction and the cache write back instruction may write back dirty cache lines to a memory associated with the processor but unlike the cache flush instruction, the cache write back instruction may retain any non-modified copies of cache lines in the hierarchical arrangement of caches. The side-channel timing attack may comprise a flush plus reload attack.

It is to be understood that the methods, modules, and components depicted herein are merely exemplary. Alternatively, or in addition, the functionality described herein can be performed, at least in part, by one or more hardware logic components. For example, and without limitation, illustrative types of hardware logic components that can be used include Field-Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application-Specific Standard Products (ASSPs), System-on-a-Chip systems (SOCs), Complex Programmable Logic Devices (CPLDs), etc. In an abstract, but still definite sense, any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of architectures or inter-medial components. Likewise, any two components so associated can also be viewed as being “operably connected,” or “coupled,” to each other to achieve the desired functionality. Merely because a component, which may be an apparatus, a structure, a system, or any other implementation of a functionality, is described herein as being coupled to another component does not mean that the components are necessarily separate components. As an example, a component A described as being coupled to another component B may be a sub-component of the component B, the component B may be a sub-component of the component A, or components A and B may be a combined sub-component of another component C.

The functionality associated with some examples described in this disclosure can also include instructions stored in a non-transitory media. The term “non-transitory media” as used herein refers to any media storing data and/or instructions that cause a machine to operate in a specific manner. Exemplary non-transitory media include non-volatile media and/or volatile media. Non-volatile media include, for example, a hard disk, a solid-state drive, a magnetic disk or tape, an optical disk or tape, a flash memory, an EPROM, NVRAM, PRAM, or other such media, or networked versions of such media. Volatile media include, for example, dynamic memory such as DRAM, SRAM, a cache, or other such media. Non-transitory media is distinct from, but can be used in conjunction with transmission media. Transmission media is used for transferring data and/or instruction to or from a machine. Exemplary transmission media include coaxial cables, fiber-optic cables, copper wires, and wireless media, such as radio waves.

Furthermore, those skilled in the art will recognize that boundaries between the functionality of the above described operations are merely illustrative. The functionality of multiple operations may be combined into a single operation, and/or the functionality of a single operation may be distributed in additional operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.

Although the disclosure provides specific examples, various modifications and changes can be made without departing from the scope of the disclosure as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present disclosure. Any benefits, advantages, or solutions to problems that are described herein with regard to a specific example are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.

Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles.

Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.