Patent ID: 12262338

DETAILED DESCRIPTION

FIG.1is a block diagram illustrating the format of a BLE LR packet2. The BLE LR packet2comprises: an 80 μs sync word (SW) preamble field4, a 256 μs coded access address (AA) field6, a 16 μs coding indicator (CI) field8, a 24 μs first terminator (TERM1) field10, an N*16*P μs protocol data unit (PDU) field12, a 48*P μs cyclic redundancy check (CRC) field14, and a 6*P μs second terminator (TERM2) field16.

The AA field6, CI field8, and TERM1 field10collectively form a first FEC block18.

The PDU field12, CRC field14, and TERM2 field16collectively form a second FEC block20.

The SW field4of the BLE LR packet2is a 80 μs long preamble portion, consisting of ten repetitions of the sync word sequence [00111100] used for reaching initial frame synchronisation in low sensitivity conditions.

FIG.2is a plot of a correlator response under good SNR conditions.FIG.2shows what the output of a conventional decoder in a prior art radio receiver looks like under good (−90 dBm) SNR conditions.

The highlighted area21in the SW region22shows the location of the actual SW field4. Frame synchronization (FRS) is achieved at the end of this sequence, where the frame synchronisation process looks for a match. The word to be matched is called the frameSynch word (FW).

It can be readily seen fromFIG.2that the peaks in the SW region22(i.e. the period of time corresponding to the SW preamble field4) are much stronger than the peaks following immediately prior which correspond to noise responses; and are also stronger than the peaks that follow afterwards which are due to the spreading pattern not matching multiple [00111100] sequences. Thus if the peak requirements are set high enough, there is little danger of locking synchronisation too early on noise (i.e. a false positive), and thus being unable to correctly synchronise to the beginning of the actual packet2.

Conversely, however,FIG.3provides a plot of a correlator response under poor SNR conditions (−105 dBm). Here, the distortion is now sufficiently heavy that the magnitude of peaks in the SW region22are reduced down towards the magnitude of peaks arising from noise. In order to still be able to detect the packet2, the peak requirements must be reduced. However, this increases the likelihood of synchronising early on noise (i.e. a false positive). In this corner, significant distortion is experienced such that the SW peaks can no longer be trusted to be higher than the noise peaks nor the peaks produced in the FW portion of the packet2.

FIG.4is a plot of a correlator response in the presence of a heavy co-channel interference source.FIG.4shows the situation when a heavy S8 interferer is in the channel. Even though the source of interference is not sending multiple [00111100] patterns back to back, it nevertheless produces decoder peaks that are much stronger than an actual SW would be at poor SNR conditions. If a single synchronization threshold is to be used, a trade off must be made between selectivity and sensitivity.

FIG.5is a block diagram of a radio receiver device100in accordance with an embodiment of the present invention. The radio receiver device100comprises a preamble recognition module102, which deals with all calculations related to the autocorrelation for recognising the SW4in the BLE LR data packet2described previously. This preamble recognition module102comprises a core104and a filter106, which will be explained in further detail later.

The device100also includes: a double correlator (DBC)108; a peak classifier110; two data path processing blocks112a,112b; a block selector114; and a frame sync checker116.

The DBC108includes logic for performing various functions including automatic gain control (AGC) training and symbol timing estimation, as well as finite state machine (FSM) logic.

The peak classifier110is a decision maker which evaluates the received peak chain from the DBC108and decides whether it is a strong peak chain or weak peak chain. When a strong peak is seen, the peak classifier110starts or restarts a specified data path processing block112a,112bfor receiving data. When seeing a weak peak, the peak classifier110tells all blocks to decay their thresholds, as explained in more detail later. The block selector114is configured to decide which block112a,112bshall respond to a strong peak event.

The frame sync checker116handles all frame sync signals from the data path processing blocks112a,112b. As soon as receiving a frame sync from one of these block112a,112b, it keeps that block alive but disables and resets the other block. If multiple frame sync signals arrive simultaneously, it may pick the one with the lowest index.

In general, ‘late’ re-syncs can cause issues with frame synchronisation and/or frequency offset estimates. This generally sets a lower bound on how relaxed the thresholds can be set.

FIG.6is a block diagram of the preamble recognition module102in the device ofFIG.5, and shows the core104and the filter106which acts to smooth the output from the core104. The preamble recognition module102is responsible for detecting the start of the packet2, i.e. for detecting the SW4. In some conventional receivers, known in the art per se, the DBC108would be responsible for this function, rather than having a dedicated module as provided by embodiments of the present invention.

Thus the main task of the preamble recognition module102is to recognise the preamble period of a BLE LR packet, and to reduce the likelihood of erroneous synchronisation to noise or a constant carrier signal in front of valid data, and re-synching on bit patterns occurring in the FRS region.

FIG.7is a block diagram of the core104ofFIG.6. The core104includes two autocorrelators202,204which receive samples of the input IQ signal. The latest 32 samples yi-1, yi-2, . . . y1-32of the IQ signal are stored in a 32-bit shift register206. The arrangement is configured such that 32 samples corresponds to an entire period of the preamble portion, i.e. the SW4. It will of course be appreciated that a different sampling rate could be used, and a different sized shift register could be used accordingly.

The first autocorrelator202receives the sample from 32 samples ago, i.e. yi-32, and the current sample of the IQ signal, subject to a conjugate function208. Thus the first autocorrelator202correlates the IQ signal with itself from one period ago. Using the BLE LR preamble pattern of [00111100], it would be expected that, if the preamble is present, this autocorrelator202would output a high correlation value.

The output of the correlation is stored in a shift register210that stores the latest 96 outputs (i.e. the latest 96 calculations of yt-32yt*) u0to u95from the first autocorrelator202.

The second autocorrelator204receives the sample from 16 samples ago, i.e. yi-16, and the current sample of the IQ signal, subject to the conjugate function208. Thus the second autocorrelator204correlates the IQ signal with itself from half a period ago. Using the BLE LR preamble pattern of [00111100], it would be expected that, if the preamble is present, this autocorrelator202would output a low correlation value. The output of the correlation is stored in a further shift register212that stores the latest 96 outputs (i.e. the latest 96 calculations of yt-16yt*) v0to v95from the second autocorrelator204.

A further correlator214is configured to correlate the samples with its own conjugate (from the conjugate function208) to determine the power of the received IQ signals. The last 128 samples of the power p0to p127are stored in a further shift register216.

Thus the results of the two autocorrelations (one between ytand yt-32and another between ytand yt-16) are stored in the respective shift registers210,212. These shift registers210,212each store the latest 96 values, i.e. corresponding to the last three periods.

After these two registers210,212get the data, the elements of the registers are summed up using respective sum blocks218,220and the power of the sums are calculated by respective power calculation blocks222,224. The power calculation blocks222,224multiply their respective input from the respective sum block218,220by its conjugate to obtain the power.

The calculated powers from the power calculation blocks222,224are each passed to a respective calculate ratio unit (CRU)226,228.

Partial sums230a-cof the samples of the power in the respective shift register216are calculated. A first230acalculates a partial sum of the most recent 96 samples of the power. A second230bcalculates a partial sum of the power 16 samples ago and the 95 preceding samples (i.e. corresponding to half a period ago and the 95 samples preceding it). A third230ccalculates a partial sum of the power 32 samples ago and the 95 preceding samples (i.e. corresponding to a full period ago and the 95 samples preceding it).

The first CRU226divides the power from the first power calculation block222(i.e. corresponding to the power of the autocorrelation of the IQ signal with the samples from one period ago) by the product of the outputs put of the first partial sum230a(i.e. the sum of the powers of the 0thto 95thmost recent samples) and the third partial sum230c(i.e. the sum of the powers of the 32ndto 127thmost recent samples).

The second CRU228divides the power from the second power calculation block224(i.e. corresponding to the power of the autocorrelation of the IQ signal with the samples from half a period ago) by the product of the outputs put of the second partial sum230a(i.e. the sum of the powers of the 16thto 111thmost recent samples) and the third partial sum230c(i.e. the sum of the powers of the 32ndto 127thmost recent samples).

Finally, the output of the second CRU228is subtracted from the output of the first CRU226using a summation block232to produce an output signal x.

FIG.8is a block diagram of the filter106ofFIG.6. The filter106is arranged to receive the output signal x from the core104, and produce a filtered output signal y. The filter106is also configured to receive a ‘clear’ signal, which acts to reset the filter106. If the clear signal is set, the filter output y is set equal to the input signal x from the core104.

The filter106follows a particular filter algorithm, making use of a dampening factor α of the moving average filter which used on the correlator output. If the clear signal is asserted, the filter output y is set equal to the input signal x from the core104as above. If, however, the clear signal is not set, a further condition is checked.

If the dampening factor α is zero, the filter output y is set highest of itself and the input signal x from the core104, or in other words y is set to the value of the input signal x if x is higher than y, i.e. y=max(y, x).

Otherwise, if the dampening factor α is non-zero, the filter output y is set to be the sum of (1−α)*y and α*x, i.e. y=(1−α)y+αx.

FIG.9is a block diagram of the peak classifier110in the device100ofFIG.5. The peak classifier110is a decision maker and is configured to evaluate the quality of the peak chain detected by the DBC108(which is supplied to input B), with the assistance of the output y from the preamble recognition module102(which is supplied to input A). The peak classifier110handles two kinds of peaks.

Firstly, if both A (i.e. the output y from the preamble recognition module102) and B (i.e. the DBC108peak strength) are larger than respective thresholds C and D, the peak classifier110regards the event as a strong peak detection. In this case, the peak classifier110starts (or restarts) the first data processing block112aand passes the new values of the peak strength and the output y from the preamble recognition module102to the block to update the thresholds C, D.

Secondly, if the B is not larger than the threshold D or the A is not larger than the threshold C, but they are still larger than the configured lower bounds, the peak classifier110regards the event as a weak peak detection. In this case, the peak classifier110sends a trigger signal to all blocks to decay their thresholds accordingly. The lower bounds may be set via a configurable register (not shown).

FIG.10is a simulated plot showing a packet error rate (PER) comparison when the constant carrier is disabled and enabled, both with and without use of an embodiment of the present invention. Specifically,FIG.10shows the comparative PER curves when the constant carrier blocker is disabled and enabled of a conventional BLE LR receiver shown by plots500and502and one operating in accordance with an embodiment of the present invention shown by plots504and506(i.e. having the preamble recognition module).

Specifically, plot500shows a conventional receiver with the constant carrier disabled; plot502shows a conventional receiver with the constant carrier enabled; plot504shows a receiver in accordance with an embodiment of the present invention with the constant carrier disabled; and plot506shows a receiver in accordance with an embodiment of the present invention with the constant carrier enabled.

It can be seen that when the constant carrier is enabled, the conventional BLE receiver suffers a significant reduction in performance, as evidenced by the much higher PER of plot502compared to plot500. Comparatively, with the constant carrier enabled, the performance of the BLE LR receiver of the present invention follows more closely the performance of the conventional receiver without the constant carrier, as evidenced by comparing plot506to plots500. This shows a significant improvement over the performance of the conventional receiver under constant carrier conditions, as shown by comparing plots506and502.

Even with the constant carrier disabled, the BLE LR receiver of the present invention provides improved performance compared to the conventional receiver, as shown by a comparison of plots504and500respectively.

It can be seen fromFIG.10that the BLE LR receiver of the present invention is significantly more robust to constant carrier conditions than a conventional receiver.

While specific embodiments of the present invention have been described in detail, it will be appreciated by those skilled in the art that the embodiments described in detail are not limiting on the scope of the claimed invention.