Patent ID: 12237034

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, example embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

FIG.1is a block diagram illustrating a memory system including a memory controller according to an embodiment.

Referring toFIG.1, a memory system1according to an embodiment may include a memory controller10and a memory device20.

The memory system1may be implemented as an internal memory embedded in an electronic device, or may be implemented as an external memory detachable from an electronic device. For example, the memory system1may be implemented in various forms, such as an embedded Universal Flash Storage (UFS), an embedded multi-media security card (eMMC), a solid state drive (SSD), a UFS memory card, a compact flash (CF), a secure digital (SD), a micro secure digital (micro-SD), a mini secure digital (mini-SD), an extreme digital (xD), a memory stick, and the like.

The memory system1may perform a data read operation, a data write operation, and the like, based on a request received from an external host2. In an embodiment, the memory system1may operate based on an Error Correction Code (ECC) select signal ECC Sel, a request Req, and a data burst DB received from the host2.

The memory controller10may control the overall operation of the memory system1. For example, the memory controller10may control data exchange between the host2and the memory device20. The memory controller10may operate based on the ECC select signal ECC Sel, the request Req, and the data burst DB, which are received from the host2.

In one embodiment, when the request Req received from the host2is a write request, the memory controller10may generate ECC data by encoding the data burst DB based on the ECC select signal ECC Sel, and write the data burst DB and ECC data to the memory device20.

In addition, in one embodiment, when the request Req received from the host2is a read request, the memory controller10may decode the data burst DB and ECC data output from the memory device20based on the ECC select signal ECC Sel and transmit the decoded result to the host2.

The memory controller10may include a processor100and an ECC circuit200.

The processor100may control the overall operation of the memory controller10. For example, the processor100may control an operation inside the memory controller10by executing an instruction stored in the memory controller10, or may control various operations related to data erasure, a program, etc. In addition, the processor100may control the ECC circuit200.

The ECC circuit200may generate first ECC data or second ECC data by receiving the data burst DB from the host2.

In detail, the ECC circuit200may select one of first ECC conversion data and second ECC conversion data based on the ECC select signal ECC Sel. In addition, the ECC circuit200may generate the first ECC data by encoding the data burst DB based on the first ECC conversion data, or may generate the second ECC data by encoding the data burst DB based on the second ECC conversion data.

In addition, the ECC circuit200may decode the data burst DB and ECC data output from the memory device20.

In detail, the ECC circuit200may select one of first ECC conversion data and second ECC conversion data based on the ECC select signal ECC Sel. In addition, the ECC circuit200may decode the data burst DB and ECC data output from the memory device20based on one selected from the first ECC conversion data and the second ECC conversion data.

A detailed configuration and operation of the ECC circuit200will be described later with reference toFIG.3.

The memory device20may be controlled by the memory controller10. The memory device20may write or read data based on a command received from the memory controller10.

In an embodiment, the memory device20may be a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRRAM) device. However, the embodiments are not limited thereto. The memory device20may be any one of volatile memory devices, such as a Low Power Double Data Rate (LPDDR) SDRAM, a Wide I/O DRAM, a High Bandwidth Memory (HBM), and a Hybrid Memory Cube (HMC). According to an embodiment, the memory device20may be any one of nonvolatile memory devices, such as a flash memory, a Phase Change RAM (PRAM), a Magnetic RAM (MRAM), a Resistive RAM (RRAM), and a Ferroelectric RAM (FRAM).

The host2may store data in the memory system1or read data stored in the memory system1.

The host2may transmit an ECC select signal ECC Sel, a request Req, and a data burst DB to store data in the memory system1. In addition, the host2may transmit an ECC select signal ECC Sel and a request Req to read data stored in the memory system1, and may receive a data burst DB from the memory system1. In this case, the host2may set and output the ECC select signal ECC Sel according to the request Req and the data burst DB.

In an embodiment, the host2may include a machine learning model. In this case, the host2may transmit the weight, the activation value, and the like used in the machine learning model to the memory system1as a data burst DB and store the same.

The host2may be any one of devices, such as a central processing unit (CPU) or a graphical processing unit (GPU) in an electronic device in which the memory system1is embedded.

FIG.2is a diagram illustrating an example of a machine learning model that may be included in a host connected to a memory system according to an embodiment.

Referring toFIG.2, the machine learning model505may include an input layer510, a hidden layer530, an output layer550, first connection lines520, and second connection lines540.

The input layer510may include input nodes511,512, and513. The hidden layer530may include hidden nodes531and532. The output layer550may include output nodes551,552, and553.

The input nodes511,512, and513of the input layer510may receive learning data LDT or a feature vector FV and transmit the learning data LDT or the feature vector FV to the hidden layer530through the first connection lines520having the first weights WT11to WT16.

The hidden nodes531and532of the hidden layer530may perform operations on the learning data LDT or the feature vector FV received from the input layer510and transmit the operation to the output layer550through the second connection lines540having the second weights WT21to WT26.

The output nodes551,552, and553of the output layer550may perform operations on values transmitted from the hidden layer530to output result data RDT corresponding to the learning data LDT or the feature vector FV.

In another embodiment, the machine learning model505may be included in the memory system1.

Values, such as first weights WT11to WT16, second weights WT21to WT26, and result data RDT used in the machine learning model505may be written to the memory system1, and may be read from the memory system1and used again for the operations of the machine learning model505. In this case, values, such as the first weights WT11to WT16and the second weights WT21to WT26do not significantly affect the operational reliability of the machine learning model505if the critical bit value (e.g., the most significant bit (MSB) value) is accurate, even if all bits included in the data are not accurate. Accordingly, the memory system1according to the inventive concept may generate ECC data based on critical bit values, thereby improving recovery performance for critical bits and increasing the operating speed of the memory system1.

FIG.3is a block diagram illustrating, in more detail, an ECC circuit included in a memory controller according to an embodiment.

Referring toFIG.3, the ECC circuit200included in the memory controller10according to an embodiment may include an ECC select circuit210and an ECC conversion circuit220.

The ECC select circuit210may select and output one of the first ECC conversion data and the second ECC conversion data based on the ECC select signal ECC Sel received from the outside of the memory controller10(e.g., host2).

The ECC select signal ECC Sel may be a signal for configuring how the ECC circuit200performs ECC conversion on the data burst DB. For example, the ECC select signal ECC Sel may be a command CMD transmitted from the host2. The ECC select circuit210may select and output one of the first ECC conversion data and the second ECC conversion data based on the ECC select signal ECC Sel, so that the ECC conversion corresponding to the ECC select signal ECC Sel may be performed in the ECC conversion circuit220.

The ECC conversion data may be data including information used in an operation for ECC conversion. In an embodiment, the ECC conversion data may include a parity check matrix (e.g., an H-matrix) used for ECC conversion.

The ECC conversion data may include first ECC conversion data and second ECC conversion data.

The first ECC conversion data may be set to correct an error occurring in any one of all bits included in the data burst DB. For example, the first ECC conversion data may correspond to ECC conversion data for correcting errors included in all bits of the data burst DB. For example, the first ECC conversion data may be data set to enable single error correction (SEC), single 2-symbol error correction (S2EC), or single error correction double error detection (SECDED).

In an embodiment, the first ECC conversion data may include a plurality of bits. For example, when the first ECC conversion data is “000” the ECC conversion circuit220may perform an ECC operation by using SEC, when the first ECC conversion data is “001” the ECC conversion circuit220may perform an ECC operation by using S2EC, and when the first ECC conversion data is “010” the ECC conversion circuit220may perform an ECC operation by using SECDED.

The second ECC conversion data may be set to be capable of correcting an error occurring in one or more preset protected bits among bits included in each of pieces of the partial data included in the data burst DB.

The partial data may be data corresponding to each of a plurality of values included in the data burst DB. For example, when the data burst DB has a total of 128 bits and includes four values of 32 bit length, the partial data may be 32 bit data corresponding to each value included in the data burst DB.

The protected bit may be at least one bit having the greatest influence on the reliability of data when an error occurs among bits included in the partial data. The protected bit may be preset by the user according to the type of data. In an embodiment, the protected bit may include the most significant bit of partial data.

The second ECC conversion data may be set to include one of a plurality of pieces of partial conversion information. In this case, each of the plurality of pieces of partial conversion information may be set to correct errors occurring in different numbers of protected bits. For example, any one of the plurality of pieces of partial conversion information may be information set to be capable of correcting errors occurring in one protected bit including the most significant bit of partial data. In addition, another of the plurality of pieces of partial conversion information may be information set to be capable of correcting errors occurring in two protected bits including the most significant bit and the second-most significant bit of the partial data. For example, the accuracy of the data burst DB and the conversion time of the data burst DB may vary when using the second ECC conversion data, depending on which partial conversion information of the plurality of partial conversion information the second ECC conversion data includes.

Since the second ECC conversion data is set to be capable of correcting errors generated among fewer bits compared to the first ECC conversion data, the second ECC conversion data may occupy a less capacity than the first ECC conversion data. For example, the parity check matrix included in the second ECC conversion data may have a smaller size than the parity check matrix included in the first ECC conversion data. Therefore, when the data burst DB is converted using the second ECC conversion data, the reliability of the data burst DB to the protected bit may be improved, and the operations required for conversion may be reduced.

In an embodiment, when the ECC select signal ECC Sel is a signal indicating that the data burst DB is data not used for machine learning, the ECC select circuit210may select and output the first ECC conversion data. In the case of general data other than data used for machine learning, all bits included in the data may have a similar level of importance. Therefore, the ECC select circuit210may select and output the first ECC conversion data for error detection and correction of all bits included in the data burst DB, when the ECC Sel is a signal indicating that the data burst DB is not used for machine learning.

Conversely, if the ECC select signal ECC Sel is a signal indicating that the data burst DB is data used for machine learning, the ECC select circuit210may select and output the second ECC conversion data.

In the case of data used for machine learning, if no error occurs in the protected bit, the operation reliability of machine learning model505is not greatly reduced. Therefore, the ECC select circuit210may select and output the second ECC conversion data to reliably correct the error of the protected bit when the ECC select signal ECC Sel is data in which the data burst DB is used for machine learning.

In an embodiment, the second ECC conversion data may be set by the ECC select circuit210to include one of the plurality of pieces of partial conversion information based on the type and characteristics of machine learning.

For example, when the type and characteristics of machine learning require a relatively high level of accuracy, such as human face recognition, the second ECC conversion data may be set to include partial conversion information with a large number of protected bits among the plurality of pieces of partial conversion information. In addition, when the type and characteristics of machine learning require a relatively low level of accuracy, such as animal classification, the second ECC conversion data may be set to include partial conversion information with a small number of protected bits among the plurality of pieces of partial conversion information.

In another embodiment, the second ECC conversion data may be set by the ECC select circuit210to include one of a plurality of pieces of partial conversion information based on the accuracy required for the data burst DB and the limit of the conversion time of the data burst DB.

In an embodiment, the second ECC conversion data may include a plurality of bits. For example, when the second ECC conversion data is “100” the ECC conversion circuit220may perform an ECC operation for the protected bit of one bit included in each of pieces of partial data included in the data burst DB, when the second ECC conversion data is “101” the ECC conversion circuit220may perform an ECC operation for the protected bit of two bits included in each of pieces of partial data included in the data burst DB, and when the second ECC conversion data is “110” the ECC conversion circuit220may perform an ECC operation for the protected bit of three bits included in each of pieces of partial data included in the data burst DB.

In detail, the second ECC conversion data may be set to include one of a plurality of pieces of partial conversion information such that the number of protected bits is proportional to the accuracy required for the data burst DB. For example, when the accuracy required for the data burst DB is relatively low, the second ECC conversion data may be set to include partial conversion information with a small number of protected bits among a plurality of pieces of partial conversion information. In addition, when the accuracy required for the data burst DB is relatively high, the second ECC conversion data may be set to include partial conversion information with a large number of protected bits among a plurality of pieces of partial conversion information.

The second ECC conversion data may be set by the ECC select circuit210to include one of a plurality of pieces of partial conversion information such that the number of protected bits is proportional to the limit of the conversion time of the data burst DB. For example, when the conversion time limit of the data burst DB is relatively short, the second ECC conversion data may be set to include partial conversion information with a small number of protected bits among a plurality of pieces of partial conversion information. In addition, when the conversion time limit of the data burst DB is relatively long, the second ECC conversion data may be set to include partial conversion information with a large number of protected bits among a plurality of pieces of partial conversion information.

The ECC select circuit210may include a switching circuit211, a first ECC conversion data block212, and a second ECC conversion data block213.

The switching circuit211may be selectively connected to one of the first ECC conversion data block212and the second ECC conversion data block213based on the ECC select signal ECC Sel.

When the ECC select signal ECC Sel is a signal for outputting the first ECC conversion data, the switching circuit211may be connected to the first ECC conversion data block212. Conversely, when the ECC select signal ECC Sel is a signal for outputting the second ECC conversion data, the switching circuit211may be connected to the second ECC conversion data block213.

The first ECC conversion data block212may store the first ECC conversion data. In this case, when the first ECC conversion data block212is connected to the switching circuit211, the first ECC conversion data may be output to the ECC conversion circuit220. For example, when the first ECC conversion data block212is connected to the switching circuit211according to the ECC select signal ECC Sel, the first ECC conversion data may be output to the ECC conversion circuit220.

The second ECC conversion data block213may store the second ECC conversion data. In this case, when the second ECC conversion data block213is connected to the switching circuit211, the second ECC conversion data may be output to the ECC conversion circuit220. For example, when the second ECC conversion data block213is connected to the switching circuit211according to the ECC select signal ECC Sel, the second ECC conversion data may be output to the ECC conversion circuit220.

The ECC conversion circuit220may convert the data burst DB based on the ECC conversion data received from the ECC select circuit210. In an embodiment, the ECC conversion circuit220may generate the first ECC data by encoding the data burst DB based on the first ECC conversion data, or may generate the second ECC data by encoding the data burst DB based on the second ECC conversion data. In addition, the ECC conversion circuit220may decode data burst DB and the first ECC data from the memory device20based on the first ECC conversion data or decode the data burst DB and the second ECC data based on the second ECC conversion data.

The first ECC data may be data including one or more parity bits generated as the data burst DB is encoded based on the first ECC conversion data. In this case, the first ECC data may include one or more parity bits that enable correction of errors occurring in any one of all bits included in the data burst DB.

The second ECC data may be data including one or more parity bits generated when the data burst DB is encoded based on the second ECC conversion data. Here, the second ECC data may include one or more parity bits that enable correction of errors occurring in a preset protected bit among bits included in each of pieces of the partial data included in the data burst DB.

The ECC conversion circuit220may include an encoder221and a decoder222.

The encoder221may encode the data burst DB received from the host2based on the ECC conversion data received from the ECC select circuit210. In an embodiment, the encoder221may generate the first ECC data by encoding the data burst DB based on the first ECC conversion data, or may generate the second ECC data by encoding the data burst DB based on the second ECC conversion data. The encoder221may output the data burst DB and ECC data to the memory device20.

The decoder222may decode data burst DB and ECC data received from the memory device20based on the ECC conversion data received from the ECC select circuit210. In an embodiment, the decoder222may decode the data burst DB and the first ECC data based on the first ECC conversion data or decode the data burst DB and the second ECC data based on the second ECC conversion data.

In an embodiment, the decoder222may not be able to determine whether the ECC data is the first ECC data or the second ECC data from the memory device20. Here, the memory controller10selects one of the first ECC conversion data and the second ECC conversion data on the basis of the ECC select signal ECC Sel received together with the read request from the host2and transmits the selected one to the decoder222. Accordingly, the data burst DB and the ECC data may be decoded by using the ECC conversion data used for encoding between the first ECC conversion data and the second ECC conversion data.

In an embodiment, the ECC conversion circuit220may change the circuit connection by the first ECC conversion data or the second ECC conversion data. For example, the ECC conversion circuit220may have a circuit connection changed to perform an operation based on the parity check matrix included in the first ECC conversion data or the second ECC conversion data.

In an embodiment, the ECC conversion circuit220may include variable ECC configurations, such as Repetition code, Hamming code, BCH code, and the like. For example, the ECC conversion circuit220may perform the encoding operation or the decoding operation by using Repetition code, Hamming code, or BCH code based on the first ECC conversion data or the second ECC conversion data.

In an embodiment, the ECC conversion circuit220may change H-matrix, such as Linear-Feedback Shift Register (LFSR) parameter. For example, the LF SR parameter may include three parameters that characterize the sequence of bits it produces, such as the number of bits N, the initial seed (the sequence of bits that initializes the register), and the tap position tap. For example, the ECC conversion circuit220may perform the encoding operation or the decoding operation based on the LF SR parameter.

When using the ECC circuit200included in the memory controller10as described above, the reliability of the data stored in the memory device20may be improved by encoding the data burst DB to correct errors for the preset protected bits among bits included in the data burst DB based on the ECC Sel. In addition, it is possible to increase the operating speed of the memory system1while improving the recovery performance for the protected bit.

FIG.4is a flowchart illustrating a method of encoding a data burst of a memory controller according to an embodiment.

Referring toFIG.4, in operation S410, the memory controller10may receive a data burst DB and an ECC select signal ECC Sel from the host2.

The data burst DB and the ECC select signal ECC Sel may be input to the ECC circuit200of the memory controller10. In this case, the ECC select signal ECC Sel may be input to the ECC select circuit210of the ECC circuit200, and the data burst DB may be input to the ECC conversion circuit220of the ECC circuit200.

In operation S420, the memory controller10may select ECC conversion data based on the ECC select signal ECC Sel.

The memory controller10may select and output one of the first ECC conversion data and the second ECC conversion data based on the ECC select signal ECC Sel through the ECC select circuit210of the ECC circuit200.

In this case, the ECC select signal ECC Sel may be a signal set by the host2based on whether the data burst DB is data used for machine learning, and based on the type and characteristics of machine learning, the accuracy required for the data burst DB, and the conversion time limit of the data burst DB.

An example in which the ECC select circuit210selects ECC conversion data based on the ECC select signal ECC Sel may be confirmed with reference toFIG.5.

FIG.5is a flowchart illustrating a method of selecting ECC information by a memory controller according to an embodiment.

Referring toFIG.5, in operation S510, the ECC select circuit210may determine whether the data burst DB is data used for machine learning.

The ECC select circuit210may determine whether the ECC select signal ECC Sel is a signal indicating that the data burst DB is data used for machine learning, and may determine whether the data burst DB is data used for machine learning.

When the data burst DB is data used for machine learning, the ECC select circuit210may select the second ECC conversion data by moving to operation S520.

Conversely, when the data burst DB is not data used for machine learning, the ECC select circuit210may select the first ECC conversion data by moving to operation S530.

Returning back toFIG.4, in operation S430, the memory controller10may encode the data burst DB based on the ECC conversion data.

The memory controller10may encode the data burst DB based on ECC conversion data received from the ECC select circuit210through the ECC conversion circuit220of the ECC circuit200.

Upon receiving the first ECC conversion data from the ECC select circuit210, the ECC conversion circuit220may generate the first ECC data by encoding the data burst DB based on the first ECC conversion data. Upon receiving the second ECC conversion data from the ECC select circuit210, the ECC conversion circuit220may generate the second ECC data by encoding the data burst DB based on the second ECC conversion data.

In operation S440, the memory controller10may store the data burst DB and ECC data (e.g., the first ECC data or the second ECC data) in the memory device20.

The memory controller10may store, in the memory device20together with the data burst DB, ECC data generated by encoding the data burst DB through the ECC conversion circuit220.

FIG.6is a flowchart illustrating a protected bit included in partial data of a data burst encoded in a memory controller according to an embodiment.

Referring toFIG.6, protected bits set with respect to partial data of the data burst DB in the first case and the second case may be identified. In the first case and the second case, the protected bits may include continuous bits including the most significant bit of partial data. For example, in the first case, the partial data may include 32 bits and the protected bit may include one or two bits. In the second case, the partial data may include 32 bits and the protected bit may include four or eight bits.

In the embodiment ofFIG.6, compared with the second case, the first case may have a relatively low accuracy required for the data burst DB and a relatively short limit of the conversion time of the data burst DB.

The number of bits set as the protected bit in the first case may be smaller than the number of bits set as the protected bit in the second case. In this case, the ECC select circuit210may set the second ECC conversion data to include partial conversion information capable of error correction for a small number of protected bits among a plurality of pieces of partial conversion information in the first case. In addition, the ECC select circuit210may set the second ECC conversion data to include partial conversion information capable of error correction for a large number of protected bits among a plurality of pieces of partial conversion information in the second case.

FIG.7is a flowchart illustrating a method of decoding a data burst of a memory controller according to an embodiment.

Referring toFIG.7, in operation S710, the memory controller10may receive a read request and an ECC select signal ECC Sel from the host2.

The read request and the ECC select signal ECC Sel may be input to the ECC circuit200of the memory controller10. In this case, the data burst DB may be input to the ECC select circuit210of the ECC circuit200.

In operation S720, the memory controller10may select ECC conversion data based on the ECC select signal ECC Sel.

The memory controller10may select and output one of the first ECC conversion data and the second ECC conversion data based on the ECC select signal ECC Sel through the ECC select circuit210of the ECC circuit200.

In this case, the ECC select signal ECC Sel may be a signal set by the host2based on whether the data burst DB to be read from the memory device20is data used for machine learning, and based on the type and characteristics of machine learning, the accuracy required for the data burst DB, and the conversion time limit of the data burst DB.

A method of selecting ECC conversion data by the ECC select circuit210based on the ECC select signal ECC Sel may be as described above with reference toFIGS.3to5.

In operation S730, the memory controller10may receive the data burst DB and ECC data from the memory device20.

The memory controller10may read ECC data corresponding to the data burst DB together with the data burst DB from the memory device20based on the read request. The data burst DB and ECC data received from the memory device20by the memory controller10may be input to the ECC conversion circuit220of the ECC circuit200.

In operation S740, the memory controller10may decode the data burst DB and ECC data based on the ECC conversion data.

The memory controller10may decode the data burst DB received from the memory device20and the ECC data corresponding to the data burst DB based on the ECC conversion data received from the ECC select circuit210through the ECC conversion circuit220of the ECC circuit200.

Upon receiving the first ECC conversion data from the ECC select circuit210, the ECC conversion circuit220may decode the data burst DB and the ECC data corresponding to the data burst DB based on the first ECC conversion data. Upon receiving the second ECC conversion data from the ECC select circuit210, the ECC conversion circuit220may decode the data burst DB and the ECC data corresponding to the data burst DB based on the second ECC conversion data.

As the ECC conversion circuit220decodes the data burst DB and the ECC data corresponding to the data burst DB, an error occurring in the protected bits included in the data burst DB may be corrected.

In operation S750, the memory controller10may transmit the decoded data burst DB to the host2.

The memory controller10may transmit the error-corrected data burst DB to the host2through the decoding process described above.

FIG.8is a block diagram illustrating a memory system based on a write operation according to an embodiment.

Referring toFIG.8, a memory system3according to an embodiment may include a memory controller30and a memory device40.

In an embodiment, the memory controller30may include a processor300, and the memory device40may include an ECC circuit400and a plurality of memory cell arrays500. For example, in the memory system3according to an embodiment, the ECC circuit400may be included in the memory device40rather than the memory controller30.

The memory controller30may receive an ECC select signal ECC Sel, a write request Write Req, and a data burst DB from the host2. The memory controller30may transmit the received ECC select signal ECC Sel and the data burst DB to the memory device40.

An operation of the processor300included in the memory controller30may be the same as an operation of the processor100included in the memory controller10ofFIG.1.

The ECC circuit400of the memory device40may receive the ECC select signal ECC Sel and the data burst DB from the memory controller30. The ECC circuit400may select one of the first ECC conversion data and the second ECC conversion data based on the ECC select signal ECC Sel, and may generate the first ECC data or the second ECC data by encoding the data burst DB based on the one selected from the first ECC conversion data and the second ECC conversion data. In addition, the ECC circuit400may transmit the data burst DB and the ECC data to the plurality of memory cell arrays500.

Operations of the ECC circuit400, such as a method of selecting ECC conversion data by the ECC circuit400, and a specific method of generating ECC data by encoding a data burst DB, by the ECC circuit400, and configuration of the ECC circuit400may be similar to those of the ECC circuit200described above throughFIGS.1to7.

The plurality of memory cell arrays500may store the first ECC data or the second ECC data generated by the ECC circuit400together with the data burst DB.

FIG.9is a block diagram illustrating a memory system based on a read operation according to an embodiment.

Referring toFIG.9, in the memory system3ofFIG.8, a block diagram in which only signal flows are displayed differently may be identified.

The memory controller30may receive an ECC select signal ECC Sel and a read request Read Req from the host2. The memory controller30may transmit the received ECC select signal ECC Sel to the memory device40.

The memory device40may read the data burst DB and ECC data from a plurality of memory cell arrays500. The data burst DB and ECC data read from the plurality of memory cell arrays500may be decoded by the ECC circuit400based on the ECC select signal ECC Sel. As the ECC circuit400decodes the data burst DB and the ECC data corresponding to the data burst DB, an error occurring in the protected bits included in the data burst DB may be corrected.

The memory device40may transmit the decoded data burst DB to the memory controller30. The memory controller30may transmit the received data burst DB to the host4in response to the read request Read Req.

FIG.10is a block diagram illustrating an electronic device according to an embodiment.

Referring toFIG.10, an electronic device1000may include a processor1100, a memory device1200, a storage device1300, a modem1400, an input/output device1500, a power supply1600, and a bus1700. The processor1100, the memory device1200, the storage device1300, the modem1400, the input/output device1500, and the power supply1600of the electronic device1000may be connected to each other through the bus1700. In this case, the storage device1300may be implemented to include any one of the memory systems1and3as described above with reference toFIGS.1to9.

According to memory controllers10and30according to the embodiments, the reliability of data stored in the memory device may be improved by encoding a data burst to enable error correction for a preset protected bit among bits included in the data burst DB based on the ECC select signal ECC Sel. In addition, it is possible to increase the operating speed of the memory system while improving the recovery performance for the protected bit.

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.