Patent ID: 12206147

EMBODIMENTS FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of the present invention are described with reference the accompanying drawings.

First Embodiment

First, a first embodiment of the present invention are described. As shown inFIG.1, a digital phase shifter A1according to the first embodiment is a high frequency circuit configured to output a high frequency signal with a phase shifted by a predetermined phase shift quantity to the outside using a signal (a high frequency signal) such as microwaves, sub-millimeter waves, millimeter waves, or the like, as an input.

As shown inFIG.1, the digital phase shifter A1includes a plurality of (“n”) digital phase shift circuits B1to Bn, a pair of connection circuits C1and C2, a ground pattern D, and a pair of additional lines E1and E2. Further, in the present embodiment, the above-mentioned “n” is a natural number. In addition, the following “i” is a natural number of 2 or more and “n” or less.

As shown in the drawings, the “n” (plurality of) digital phase shift circuits B1to Bn are disposed in two rows (multiple rows) through the pair of connection circuits C1and C2. That is, the digital phase shifter A1according to the first embodiment includes a multi-row structure related to the digital phase shift circuits B1to Bn using the pair of connection circuits C1and C2. Further, a two-row structure shown inFIG.1is an example of the multi-row structure, and the number of rows may be three or more.

While described below in detail, as representatively shown in the digital phase shift circuit B1, each of the digital phase shift circuits B1to Bn includes a signal line1, two inner lines2(a first inner line2aand a second inner line2b), two outer lines3(a first outer line3aand a second outer line3b), two ground conductors4(a first ground conductor4aand a second ground conductor4b), and the like.

In the digital phase shifter A1, a transmission direction of a high frequency signal is a direction from a first digital phase shift circuit B1toward an n-th digital phase shift circuit Bn. The first digital phase shift circuit B1is positioned on the uppermost side (the foremost stage) in the transmission direction of the high frequency signal, and the n-th digital phase shift circuit Bn is located on the lowermost side (the final stage) in the transmission direction of the high frequency signal.

In the “n” digital phase shift circuits B1to Bn, the first to (“i”−1)-th digital phase shift circuits B1to B(i−1) constitute a front row (a first row), and are cascade-connected linearly. Meanwhile, the (i+1)-th to n-th digital phase shift circuits B(i+1) to Bn constitute a rear row (a second row), and are cascade-connected linearly. The front row (the first row) and the rear row (the second row) are provided substantially in parallel through the pair of connection circuits C1and C2and the i-th digital phase shift circuit B1.

In the first to (i−1)-th digital phase shift circuits B1to B(i−1) of the front row (the first row), the signal lines1neighboring in the row direction (an extension direction of the front row and the rear row) are serially connected in a row. In addition, in the (i+1)-th to n-th digital phase shift circuits B(i+1) to Bn of the rear row (the second row), the signal lines1neighboring in the row direction are serially connected in a row.

In addition, in the first to (i−1)-th digital phase shift circuits B1to B(i−1) of the front row (the first row), the first inner lines2aneighboring in the row direction, the second inner lines2bneighboring in the row direction, the first outer lines3aneighboring in the row direction and the second outer lines3bneighboring in the row direction are respectively serially connected in a row. In addition, in the (i+1)-th to n-th digital phase shift circuits B(i+1) to Bn of the rear row (the second row), the first inner lines2aneighboring in the row direction, the second inner lines2bneighboring in the row direction, the first outer lines3aneighboring in the row direction and the second outer lines3bneighboring in the row direction are respectively serially connected in a row.

In addition, in the first to (i−1)-th digital phase shift circuits B1to B(i−1) of the front row (the first row), the first ground conductor4aand the second ground conductor4bneighboring in the row direction are connected to each other. In addition, in the (i+1)-th to n-th digital phase shift circuits B(i+1) to Bn of the rear row (the second row), the first ground conductor4aand the second ground conductor4bneighboring in the row direction are connected to each other. That is, in the first to (i−1)-th digital phase shift circuits B1to B(i−1) of the front row (the first row), or in the (i+1)-th to n-th digital phase shift circuits B(i+1) to Bn of the rear row (the second row), the first ground conductor4aof one digital phase shift circuit and the second ground conductor4bof another digital phase shift circuit neighboring in the row direction are connected to each other.

The first to (i−1)-th digital phase shift circuits B1to B(i−1) of the front row (the first row) and the (i+1)-th to n-th digital phase shift circuits B(i+1) to Bn of the rear row (the second row) have a neighboring relation between the rows. In the first to (i−1)-th digital phase shift circuits B1to B(i−1) of the front row (the first row) and the (i+1)-th to n-th digital phase shift circuits B(i+1) to Bn of the rear row (the second row) having a relation neighboring between the rows, at least ones of the first outer lines3aneighboring in an inter-row direction (a direction in which the front row and the rear row are adjacent to each other), the first ground conductor4aand the second ground conductor4bneighboring in an inter-row direction, and the second ground conductor4band the first ground conductor4aneighboring in an inter-row direction are connected to each other through the ground pattern D.

That is, the ground pattern D connects at least ones of the first outer lines3aneighboring in the inter-row direction, the first ground conductor4aand the second ground conductor4bneighboring in the inter-row direction, and the second ground conductor4band the first ground conductor4aneighboring in the inter-row direction, which are electrically grounded. The digital phase shifter A1including the ground pattern D includes an inter-row connection structure.

Here, in the digital phase shifter A1according to the first embodiment, among the “n” digital phase shift circuits B1to Bn, the i-th digital phase shift circuit B1does not constitute the front row (the first row) and the rear row (the second row), and is disposed while being sandwiched between the pair of connection circuits C1and C2. However, the i-th digital phase shift circuit B1may be disposed to constitute the front row (the first row) or the rear row (the second row).

The pair of connection circuits C1and C2are circuits connected in a state in which the front row (the first row) and the rear row (the second row) are parallel to each other. In the pair of connection circuits C1and C2, as shown in the drawings, the first connection circuit C1connects the (i−1)-th digital phase shift circuit B(i−1) located on the final stage in the front row (the first row) and the i-th digital phase shift circuit B1. As shown in the drawings, the first connection circuit C1includes five individual connection lines F1, F2a, F2b, F3aand F3b.

Among these individual connection lines F1, F2a, F2b, F3aand F3b, the first individual connection line F1is a beltlike conductor that connects an output end (one end) of the signal line1in the (i−1)-th digital phase shift circuit B(i−1) and an input end (the other end) of the signal line1in the i-th digital phase shift circuit B1. The first individual connection line F1is a long plate-shaped conductor having a fixed width, a fixed thickness and a predetermined length, and extends diagonally as shown in the drawings (when seen in a plan view shown inFIG.1).

The second individual connection line F2ais a beltlike conductor configured to connect one end of the first inner line2ain the (i−1)-th digital phase shift circuit B(i−1) and the other end of the first inner line2ain the i-th digital phase shift circuit B1. The second individual connection line F2ais a long plate-shaped conductor having a fixed width, a fixed thickness and a predetermined length, and extends diagonally like the first individual connection line F1.

The third individual connection line F2bis a beltlike conductor configured to connect one end of the second inner line2bin the (i−1)-th digital phase shift circuit B(i−1) and the other end of the second inner line2bin the i-th digital phase shift circuit B1. The third individual connection line F2bis a long plate-shaped conductor having a fixed width, a fixed thickness and a predetermined length, and extends diagonally like the first individual connection line F1.

The fourth individual connection line F3ais a beltlike conductor configured to connect one end of the first outer line3ain the (i−1)-th digital phase shift circuit B(i−1) and the other end of the first outer line3ain the i-th digital phase shift circuit B1. The fourth individual connection line F3ais a long plate-shaped conductor having a fixed width, a fixed thickness and a predetermined length, and extends diagonally like the first individual connection line F1.

The fifth individual connection line F3bis a beltlike conductor configured to connect one end of the second outer line3bin the (i−1)-th digital phase shift circuit B(i−1) and the other end of the second outer line3bin the i-th digital phase shift circuit B1.

The fifth individual connection line F3bis a long plate-shaped conductor having a fixed width, a fixed thickness and a predetermined length, and extends diagonally like the first individual connection line F1.

Meanwhile, as shown in the drawings, the second connection circuit C2connects the i-th digital phase shift circuit B1and the (i+1)-th digital phase shift circuit B(i+1) located on the foremost stage in the rear row (the second row). As shown in the drawings, the second connection circuit C2includes five individual connection lines G1, G2a, G2b, G3aand G3b.

Among these individual connection lines G1, G2a, G2b, G3aand G3b, the sixth individual connection line G1is a beltlike conductor configured to connect an output end (one end) of the signal line1in the i-th digital phase shift circuit B1and an input end (the other end) of the signal line1in the (i+1)-th digital phase shift circuit B(i+1). The sixth individual connection line G1is a long plate-shaped conductor having a fixed width, a fixed thickness and a predetermined length, and extends diagonally as shown in the drawings (when seen in a plan view shown inFIG.1).

The seventh individual connection line G2ais a beltlike conductor configured to connect one end of the first inner line2ain the i-th digital phase shift circuit B1and the other end of the first inner line2ain the (i+1)-th digital phase shift circuit B(i+1). The seventh individual connection line G2ais a long plate-shaped conductor having a fixed width, a fixed thickness and a predetermined length, and extends diagonally like the sixth individual connection line G1.

The eighth individual connection line G2bis a beltlike conductor configured to connect one end of the second inner line2bin the i-th digital phase shift circuit B1and the other end of the second inner line2bin the (i+1)-th digital phase shift circuit B(i+1). The eighth individual connection line G2bis a long plate-shaped conductor having a fixed width, a fixed thickness and a predetermined length, and extends diagonally like the sixth individual connection line G1.

The ninth individual connection line G3ais a beltlike conductor configured to connect one end of the first outer line3ain the i-th digital phase shift circuit B1and the other end of the first outer line3ain the (i+1)-th digital phase shift circuit B(i+1). The ninth individual connection line G3ais a long plate-shaped conductor having a fixed width, a fixed thickness and a predetermined length, and extends diagonally like the sixth individual connection line G1.

The tenth individual connection line G3bis a beltlike conductor configured to connect one end of the second outer line3bin the i-th digital phase shift circuit B1and the other end of the second outer line3bin the (i+1)-th digital phase shift circuit B(i+1). The tenth individual connection line G3bis a long plate-shaped conductor having a fixed width, a fixed thickness and a predetermined length, and extends diagonally like the sixth individual connection line G1.

The ground pattern D is positioned in a region between the front row (the first row) and the rear row (the second row), and a rectangular conductor provided along the extension direction of the front row (the first row) and the rear row (the second row). As shown in the drawings, the ground pattern D has a width slightly narrower than an interval between the front row (the first row) and the rear row (the second row). The ground pattern D is provided between the front row (the first row) and the rear row (the second row), for example, for a switch controller8described below.

While described below in detail, the digital phase shift circuits B1to Bn are constituted by conductive layers. The ground pattern D is any one layer of the conductive layers. That is, the ground pattern D is provided on any one layer of the conductive layers that constitute the digital phase shift circuits B1to Bn. However, the ground pattern D is not limited to any one layer of these conductive layers, and may be a conductive layer different from these conductive layers. That is, the ground pattern D may be provided on a conductive layer different from the conductive layers that constitute the digital phase shift circuits B1to Bn.

The pair of additional lines E1and E2are conductors configured to connect the ground pattern D to the front row (the first row) and the rear row (the second row).

These additional lines E1and E2are substantially beltlike conductors having a predetermined width. The additional line E1connects the front row (the first row) to the ground pattern D at one point, and the additional line E2connects the rear row (the second row) to the ground pattern D at one point.

In these additional lines E1and E2, the first additional line E1connects a rear end of the front row (the first row) and the ground pattern D at one point by a shortest distance. That is, as shown in the drawings, the first additional line E1connects one end of the first outer line3ain the (i−1)-th digital phase shift circuit B(i−1) located on the final stage of the front row (the first row) to the ground pattern D.

Meanwhile, the second additional line E2connects a rear end of the rear row (the second row) and the ground pattern D at one point by a shortest distance. That is, as shown in the drawings, the second additional line E2connects one end of the first outer line3ain the n-th digital phase shift circuit Bn located on the final stage of the rear row (the second row) to the ground pattern D.

Next, detailed configurations of the digital phase shift circuits B1to Bn according to the first embodiment are described. As shown by representative reference sign B inFIG.2, each of the digital phase shift circuits B1to Bn includes a capacitor5, connection conductors6, four electronic switches7(a first electronic switch7a, a second electronic switch7b, third electronic switch7cand a fourth electronic switch7d) and the switch controller8, in addition to the signal line1, the pair of inner lines2(the first inner line2aand the second inner line2b), the pair of outer lines3(the first outer line3aand the second outer line3b), and the pair of ground conductors4(the first ground conductor4aand the second ground conductor4b).

The signal line1is a linear beltlike conductor extending in a predetermined direction. That is, the signal line1is a long plate-shaped conductor having a fixed width, a fixed thickness and a predetermined length. InFIG.2, a high frequency signal flows through the signal line1from a front side toward a back side. The high frequency signal is a signal having a frequency band such as microwaves, sub-millimeter waves, millimeter waves, or the like.

Further, inFIG.2, the forward/rearward direction of the digital phase shift circuit B is referred to as an X-axis direction, the leftward/rightward direction is referred to as a Y-axis direction, and the upward/downward direction (vertical direction) is referred to as a Z-axis direction. In addition, a +X direction is a direction from a front side toward a back side in the X-axis direction, and a −X direction is a direction directed opposite to the +X direction. A +Y direction is a direction directed rightward in the Y-axis direction, and a −Y direction is a direction directed opposite to the +Y direction. A +Z direction is a direction directed upward in the Z-axis direction, and a −Z direction is a direction directed opposite to the +Z direction.

The pair of inner lines2(the first inner line2aand the second inner line2b) are linear beltlike conductors provided on both sides of the signal line1. The first inner line2ais a long plate-shaped conductor having a fixed width, a fixed thickness and a predetermined length. The first inner line2aextends in the same direction as the extension direction of the signal line1. The first inner line2ais provided parallel to the signal line1with separated by a predetermined distance M. Specifically, the first inner line2ais disposed on one side of the signal line1with separated by the predetermined distance M. In other words, the first inner line2ais disposed separated from the signal line1by the predetermined distance M in the +Y direction.

Like the first inner line2a, the second inner line2bhas a long plate-shaped conductor having a fixed width, a fixed thickness and a predetermined length. The second inner line2bextends in the same direction as the extension direction of the signal line1. The second inner line2bis provided parallel to the signal line1with separated by the predetermined distance M. Specifically, the second inner line2bis disposed on the other side of the signal line1with separated by the predetermined distance M. In other words, the second inner line2bis disposed separated from the signal line1by the predetermined distance M in the −Y direction.

The pair of outer lines3(the first outer line3aand the second outer line3b) are linear beltlike conductors provided on outer sides of the inner lines. The first outer line3ais a linear beltlike conductor provided on one side of the signal line1at a position farther from the signal line1than the first inner line2a.

That is, the first outer line3ais a linear beltlike conductor disposed further in the +Y direction than the first inner line2a(disposed spaced further apart from the signal line1than the first inner line2ain the +Y direction). The first outer line3ais a long plate-shaped conductor having a fixed width, a fixed thickness and a predetermined length. The first outer line3ais provided parallel to the signal line1while being separated from the signal line1by a predetermined distance with the first inner line2asandwiched therebetween. Like the first inner line2aand the second inner line2b, the first outer line3aextends in the same direction as the extension direction of the signal line1.

The second outer line3bis a linear beltlike conductor provided on the other side of the signal line1at a position farther from the signal line1than the second inner line2b. That is, the second outer line3bis a linear beltlike conductor disposed further in the −Y direction than the second inner line2b(disposed spaced further apart from the signal line1than the second inner line2bin the −Y direction). Like the first outer line3a, the second outer line3bis a long plate-shaped conductor having a fixed width, a fixed thickness and a predetermined length. The second outer line3bis provided parallel to the signal line1while being separated from the signal line1by a predetermined distance with the second inner line2bsandwiched therebetween. Like the first inner line2aand the second inner line2b, the second outer line3bextends in the same direction as the extension direction of the signal line1.

The first ground conductor4ais a linear beltlike conductor provided on one end side of the first inner line2a, the second inner line2b, the first outer line3aand the second outer line3b. The first ground conductor4ais electrically connected to one ends of the first inner line2a, the second inner line2b, the first outer line3aand the second outer line3b. The first ground conductor4ais a long plate-shaped conductor having a fixed width, a fixed thickness and a predetermined length.

The first ground conductor4ais provided perpendicular to the first inner line2a, the second inner line2b, the first outer line3aand the second outer line3bextending in the same direction. That is, the first ground conductor4ais disposed to extend in the Y-axis direction. The first ground conductor4ais provided below the first inner line2a, the second inner line2b, the first outer line3aand the second outer line3bwith separated by a predetermined distance.

In the example shown inFIG.2, the first ground conductor4ais set such that one end that is an end in the +Y direction of the first ground conductor4ais located at substantially the same position as a right side edge portion of the first outer line3a. In the example shown inFIG.2, the first ground conductor4ais set such that the other end that is an end in the −Y direction of the first ground conductor4ais located at substantially the same position as a left side edge portion of the second outer line3b.

The second ground conductor4bis a linear beltlike conductor provided on the other end side of the first inner line2a, the second inner line2b, the first outer line3aand the second outer line3b. Like the first ground conductor4a, the second ground conductor4bis a long plate-shaped conductor having a fixed width, a fixed thickness and a predetermined length.

The second ground conductor4bis disposed parallel to the first ground conductor4a, and like the first ground conductor4a, provided perpendicular to the first inner line2a, the second inner line2b, the first outer line3aand the second outer line3b. The second ground conductor4bis provided below the first inner line2a, the second inner line2b, the first outer line3aand the second outer line3bwith separated by a predetermined distance.

The second ground conductor4bis provided such that one end that is an end in the +Y direction of the second ground conductor4bis located at substantially the same position as a right side edge portion of the first outer line3a. The second ground conductor4bis set such that the other end that is an end in the −Y direction of the second ground conductor4bis located at substantially the same position as a left side edge portion of the second outer line3b. InFIG.2, the second ground conductor4bis located at the same position as the first ground conductor4ain the Y-axis direction.

The capacitor5is provided between the signal line1and the first ground conductor4aor the second ground conductor4b. For example, the capacitor5includes an upper electrode connected to the signal line1and a lower electrode electrically connected to the fourth electronic switch7d. For example, the capacitor5is a thin film capacitor formed in a metal insulator metal (MIM) structure. Further, the capacitor5may be a parallel plate type capacitor or may be an opposite comb type capacitor (an interdigital capacitor).

The connection conductors6include at least the connection conductors6ato6i. The connection conductor6ais a conductor configured to electrically and mechanically connect one end of the first inner line2aand the first ground conductor4a. For example, the connection conductor6ais a conductor extending in the Z-axis direction, and has one end (an upper end) connected to a lower surface of the first inner line2aand the other end (a lower end) connected to an upper surface of the first ground conductor4a.

The connection conductor6bis a conductor configured to electrically and mechanically connect one end of the second inner line2band the first ground conductor4a. For example, the connection conductor6bis a conductor extending in the Z-axis direction like the connection conductor6a, and has one end (an upper end) connected to a lower surface of the second inner line2band the other end (a lower end) connected to an upper surface of the first ground conductor4a.

The connection conductor6cis a conductor configured to electrically and mechanically connect one end of the first outer line3aand the first ground conductor4a. For example, the connection conductor6cis a conductor extending in the Z-axis direction, and has one end (an upper end) connected to a lower surface in one end of the first outer line3aand the other end (a lower end) connected to an upper surface of the first ground conductor4a.

The connection conductor6dis a conductor configured to electrically and mechanically connect the other end of the first outer line3aand the second ground conductor4b. For example, the connection conductor6dis a conductor extending in the Z-axis direction, and has one end (an upper end) connected to a lower surface in the other end of the first outer line3aand the other end (a lower end) connected to an upper surface of the second ground conductor4b.

The connection conductor6eis a conductor configured to electrically and mechanically connect one end of the second outer line3band the first ground conductor4a. For example, the connection conductor6eis a conductor extending in the Z-axis direction, and has one end (an upper end) connected to a lower surface in one end of the second outer line3band the other end (a lower end) connected to an upper surface of the first ground conductor4a.

The connection conductor6fis a conductor configured to electrically and mechanically connect the other end of the second outer line3band the second ground conductor4b. For example, the connection conductor6fis a conductor extending in the Z-axis direction, and has one end (an upper end) connected to a lower surface in the other end of the second outer line3band the other end (a lower end) connected to an upper surface of the second ground conductor4b.

The connection conductor6gis a conductor configured to electrically and mechanically connect the other end of the signal line1and the upper electrode of the capacitor5. For example, the connection conductor6gis a conductor extending in the Z-axis direction, and has one end (an upper end) connected to a lower surface in the other end of the signal line1and the other end (a lower end) connected to the upper electrode of the capacitor5.

The first electronic switch7ais connected to the other end of the first inner line2aand the second ground conductor4btherebetween. The first electronic switch7ais, for example, a metal oxide semiconductor field effect transistor (MOSFET), and includes a drain terminal electrically connected to the other end of the first inner line2a, a source terminal electrically connected to the second ground conductor4band a gate terminal electrically connected to the switch controller8.

The first electronic switch7ais controlled to a closed state or an open state based on the gate signal input to the gate terminal from the switch controller8. The closed state is a state in which the drain terminal and the source terminal are conducted.

The open state is a state in which the drain terminal and the source terminal are not conducted and the electrical connection thereof is disconnected. The first electronic switch7ais switched to a conduction state in which the other end of the first inner line2aand the second ground conductor4bare electrically connected or a disconnection state in which the electrical connection therebetween is disconnected under control of the switch controller8.

The second electronic switch7bis connected to the other end of the second inner line2band the second ground conductor4btherebetween. The second electronic switch7bis, for example, a MOSFET, and includes a drain terminal connected to the other end of the second inner line2b, a source terminal connected to the second ground conductor4band a gate terminal connected to the switch controller8.

The second electronic switch7bis controlled to a closed state or an open state based on the gate signal input to the gate terminal from the switch controller8. The second electronic switch7bis switched to a conduction state in which the other end of the second inner line2band the second ground conductor4bare electrically connected or a disconnection state in which the electrical connection therebetween is disconnected under control of the switch controller8.

The third electronic switch7cis connected to the other end of the signal line1and the second ground conductor4btherebetween. The third electronic switch7cis, for example, a MOSFET, and includes a drain terminal connected to the other end of the signal line1, a source terminal connected to the second ground conductor4band a gate terminal connected to the switch controller8. Further, as shown inFIG.2, while the third electronic switch7cis provided on the other end side of the signal line1, it is not limited thereto and may be provided on one end side of the signal line1.

The third electronic switch7cis controlled to a closed state or an open state based on the gate signal input to the gate terminal from the switch controller8. The third electronic switch7cis switched to a conduction state in which the other end of the signal line1and the second ground conductor4bare electrically connected or a disconnection state in which the electrical connection therebetween is disconnected under control of the switch controller8.

The fourth electronic switch7dis an electronic switch for a capacitor serially connected to the capacitor5between the other end of the signal line1and the second ground conductor4b. The fourth electronic switch7dis, for example, a MOSFET. As shown inFIG.2, the fourth electronic switch7dincludes a drain terminal connected to a lower electrode of the capacitor5, a source terminal connected to the second ground conductor4band a gate terminal connected to the switch controller8.

The fourth electronic switch7dis controlled to a closed state or an open state based on the gate signal input to the gate terminal from the switch controller8. The fourth electronic switch7dis switched to a conduction state in which the lower electrode of the capacitor5and the second ground conductor4bare electrically connected or a disconnection state in which the electrical connection therebetween is disconnected under control of the switch controller8.

The switch controller8is a control circuit configured to control the first electronic switch7a, the second electronic switch7b, the third electronic switch7cand the fourth electronic switch7d, which are the electronic switches7. For example, the switch controller8includes four output ports. The switch controller8individually controls the electronic switches7to an open state or a closed state by outputting individual gate signals from the individual output ports and supplying the signals to the individual gate terminals of the electronic switches7.

Here, whileFIG.2shows a schematic perspective view of the digital phase shift circuit B so that a mechanical structure of the digital phase shift circuit B can be easily understood, the actual digital phase shift circuit B is a multilayer structure using a semiconductor manufacturing technology. For example, the digital phase shift circuit B includes the signal line1, the first inner line2a, the second inner line2b, the first outer line3aand the second outer line3b, which are formed on the first conductive layer. In addition, the first ground conductor4aand the second ground conductor4bare formed on the second conductive layers facing the first conductive layer with the insulating layer sandwiched therebetween. The components formed on the first conductive layer and the components formed on the second conductive layers are connected to each other by via holes (via-holes). In addition, the connection conductors6correspond to the via holes embedded in the insulating layer.

Next, an operation of the digital phase shift circuit B having the above-mentioned configuration are described with reference toFIG.3andFIG.4. The digital phase shift circuit B has a high delay mode and a low delay mode as operation modes, which are described below. That is, the digital phase shift circuit B is operated in the high delay mode or the low delay mode by being controlled by the switch controller8.

[High Delay Mode]

The high delay mode is a mode in which a first phase difference is generated in a high frequency signal S. As shown inFIG.3, in the high delay mode, the first electronic switch7aand the second electronic switch7bare controlled to the open state, and the fourth electronic switch7dis controlled to the closed state.

When the first electronic switch7ais controlled to the open state, electrical connection between the other end of the first inner line2aand the second ground conductor4bis disconnected. When the second electronic switch7bis controlled to the open state, connection between the other end of the second inner line2band the second ground conductor4bof the multilayer structure is disconnected. When the fourth electronic switch7dis controlled to the closed state, the other end of the signal line1is connected to the second ground conductor4bthrough the capacitor5.

When the high frequency signal S is propagated through the signal line1from the input end (the other end) toward the output end (one end), a return current R1flows from one end toward the other end in a direction opposite to the high frequency signal S (opposite to a direction in which the high frequency signal S propagates). That is, the return current R1is a current flowing in the −X direction that is a direction opposite to the high frequency signal S flowing in the +X direction. In the high delay mode, since the first electronic switch7aand the second electronic switch7bare in the open state, as shown inFIG.3, the return current R1mainly flows through the first outer line3aand the second outer line3bin the −X direction.

In the high delay mode, since the return current R1flows through the first outer line3aand the second outer line3b, an inductance value L is higher than that in the low delay mode. In addition, since the fourth electronic switch7dis in the closed state, the capacitor5is working. For this reason, in the high delay mode, a delay quantity greater than that in the low delay mode can be obtained.

[Low Delay Mode]

The low delay mode is a mode in which a second phase difference smaller than the first phase difference is generated in the high frequency signal S. In the low delay mode, as shown inFIG.4, the first electronic switch7aand the second electronic switch7bare controlled to the closed state, and the fourth electronic switch7dis controlled to the open state.

When the first electronic switch7ais controlled to the closed state, the other end of the first inner line2aand the second ground conductor4bare electrically connected. When the second electronic switch7bis controlled to the closed state, the other end of the second inner line2band the second ground conductor4bare electrically connected.

In the low delay mode, since the first electronic switch7aand the second electronic switch7bare in the closed state, as shown inFIG.4, a return current R2mainly flows through the first inner line2aand the second inner line2bin the −X direction. In the low delay mode, since the return current R2flows through the first inner line2aand the second inner line2b, the inductance value L is lower than that in the high delay mode. In addition, since the fourth electronic switch7dis in the open state, the capacitor5is not working. For this reason, a capacitance value C is smaller than that in the high delay mode. For this reason, a delay quantity in the low delay mode is lower than a delay quantity in the high delay mode.

Next, characteristic effects of the digital phase shifter A1according to the first embodiment are described with reference toFIG.1.

In the digital phase shifter A1, as described above, the ground pattern D provided between the front row (the first row) and the rear row (the second row) is connected to the front row (the first row) by the additional line E1at one point and connected to the rear row (the second row) by the additional line E2at one point.

In addition, each of the one points is one end of the first outer line3ain the (i−1)-th digital phase shift circuit B(i−1) located on the final stage in the front row (the first row), and one end of the first outer line3ain the n-th digital phase shift circuit Bn located on the final stage in the rear row (the second row). That is, a connection point (a first connection point) to the ground pattern D in the front row (the first row) and a connection point (a second connection point) to the ground pattern D in the rear row (the second row) are located in an area in the vicinity of one diagonal line in the rectangular ground pattern D as shown inFIG.1. That is, the first connection point and the second connection point are located in an area in the vicinity of both ends of one diagonal line of a pair of diagonal line in the rectangular ground pattern D. The first connection point and the second connection point correspond to the farthest positions in the ground pattern D,

According to the digital phase shifter A1, since the ground pattern D is connected to the front row (the first row) by the first connection point at one point and connected to the rear row (the second row) by the second connection point at one point, and the first connection point and the second connection point are separated from each other, reduction in phase shift quantity in the first to (i−1)-th digital phase shift circuits B1to B(i−1) and the (i+1)-th to n-th digital phase shift circuits B(i+1) to Bn due to connection of the ground pattern D to the front row (the first row) and the rear row (the second row) can be suppressed.

Second Embodiment

Next, a second embodiment of the present invention are described with reference toFIG.5.

While the digital phase shifter A1according to the first embodiment includes the ground pattern D between the front row (the first row) and the rear row (the second row), i.e., inside the front row (the first row), the digital phase shifter A2according to the second embodiment includes the ground pattern Da outside the front row (the first row) as shown in the drawings.

In addition, the digital phase shifter A2includes an additional line E3configured to connect the front row (the first row) and the ground pattern Da at one point. As shown in the drawings, the additional line E3is a substantially beltlike conductor configured to connect an area in the vicinity of the other end of the second outer line3bin the first digital phase shift circuit B1, i.e., the front end of the front row (the first row) and the ground pattern Da at one point by the shortest distance.

According to the digital phase shifter A2, since the front row (the first row) and the ground pattern Da are connected by the additional line E3at one point, it is possible to minimize the influence on the phase shift characteristics due to connection of the ground pattern Da. That is, according to the second embodiment, it is possible to provide the digital phase shifter A2capable of suppressing reduction in phase shift quantity of the digital phase shift circuit due to connection of the ground pattern Da.

Further, the digital phase shifter A1according to the first embodiment and the digital phase shifter A2according to the second embodiment include a two-row structure in which the number of rows is two as an example of the multi-row structure. However, the present invention is not limited thereto and can also be applied to a digital phase shifter including a structure with three rows or more, in which the number of rows is three or more.

REFERENCE SIGNS

A1, A2Digital phase shifterB, B1to Bn Digital phase shift circuitC1, C2Connection circuitD, Da Ground patternE1, E2, E3Additional line1Signal line2Inner line2aFirst inner line2bSecond inner line3Outer line3aFirst outer line3bSecond outer line4Ground conductor4aFirst ground conductor4bSecond ground conductor5Capacitor6Connection conductor7Electronic switch7aFirst electronic switch7bSecond electronic switch7cThird electronic switch7dFourth electronic switch (electronic switch for capacitor)8Switch controller