Patent ID: 12230646

REFERENCE NUMERALS

100, array substrate;10, substrate;20, gate;30, gate insulating layer;301, first sub-layer;301a, recess;302, second sub-layer;40, oxide semiconductor layer;50, source-drain metal layer;51, source;52, drain;60, source-drain insulating layer;200, passivation layer;200a, via hole;300, pixel electrode;400, opposite substrate.

DETAILED DESCRIPTION

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some, but not all, embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present disclosure. Furthermore, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure, and not to limit the present disclosure. In the present disclosure, unless specified otherwise, orientation terms such as “up” and “low” are used generally to refer to upper and lower in the actual use or operating state of the device, specifically the direction of the drawing in the drawings; while “inner” and “outer” refer to the outline of the device.

Referring toFIG.1, which is a schematic cross-sectional view of an array substrate in the prior art. The array substrate100in the prior art includes a substrate10, a gate20, a gate insulating layer30, an oxide semiconductor layer40, and a source-drain metal layer50. The gate insulating layer30is disposed between the gate20and the oxide semiconductor layer40. The source-drain metal layer50includes a source51and a drain52. Material of the gate insulating layer30is generally an inorganic insulating material such as silicon nitride or silicon oxide, and material of the oxide semiconductor layer40is generally a metal oxide material such as IGZO (indium gallium zinc oxide). Therefore, material compositions of the gate insulating layer30and the oxide semiconductor layer40are different, resulting in a higher density of defect states at a transition interface between the two, which in turn leads to lower device mobility and stability of the thin film transistor.

In view of this, embodiments of the present disclosure provide an array substrate100. A difference from the array substrate100in the prior art is that material of an oxide semiconductor layer40of the array substrate100of the embodiments of the present disclosure includes an oxide of a first metal element. Moreover, material of at least a portion of a gate insulating layer30in contact with the oxide semiconductor layer40includes the oxide of the first metal element.

It can be understood that, in the embodiments of the present disclosure, the material of the oxide semiconductor layer40includes the first metal element, and the material of at least the portion of the gate insulating layer30in contact with the oxide semiconductor layer40includes the oxide of the first metal element. Since the gate insulating layer30and the oxide semiconductor layer40have the same composition at a transition interface therebetween, the transition interface has a lower density of defect states. In the prior art, since the gate insulating layer30and the oxide semiconductor layer40have different materials, more defect states are generated at the transition interface when the two are in direct contact. The above situation is prevented, which is beneficial to improve the mobility and stability of the thin film transistor.

It should be noted that the thin film transistors may be top-gate thin film transistors or bottom-gate thin film transistors. In order to clearly describe the technical solution provided by the present disclosure, the embodiments of the present disclosure focus on taking the thin film transistors as an example of the bottom-gate thin film transistors for illustration and description. However, the top-gate thin film transistors adopting the concept of the application provided by the present disclosure also falls within the protection scope of the present disclosure.

In one embodiment, as shown inFIG.2,FIG.2is a schematic cross-sectional view of a first array substrate of an embodiment of the present disclosure. Thin film transistors may be bottom-gate thin film transistors. Specifically, the array substrate100includes a substrate10, a gate20, a gate insulating layer30, an oxide semiconductor layer40, and a source-drain metal layer50. The gate20, the gate insulating layer30, the oxide semiconductor layer40, and the source-drain metal layer50are disposed on the substrate10. The gate20, the gate insulating layer30, the oxide semiconductor layer40, and the source-drain metal layer50are sequentially stacked in a direction away from the substrate10. Specifically, the gate20is disposed on a side of the substrate10. The gate insulating layer30covers a side of the gate20away from the substrate10. The oxide semiconductor layer40is disposed on a side of the gate insulating layer30away from the substrate10. The source-drain metal layer50is disposed on a side of the oxide semiconductor layer40away from the substrate10. The source-drain metal layer50includes a source51and a drain52.

In this embodiment, a difference betweenFIG.2andFIG.1is that material of all portions of the gate insulating layer30is an oxide of the first metal element. The gate insulating layer30can be formed by only one process. Simply put, in this embodiment, the material of the gate insulating layer30in the prior art is replaced with the oxide of the first metal element. A transition interface between the gate insulating layer30and the oxide semiconductor layer40has the same material composition. In the prior art, when the gate insulating layer30and the oxide semiconductor layer40are in direct contact, many defect states are generated at the transition interface. The above situation is prevented.

Specifically, the first metal element includes one of aluminum Al, hafnium Hf, titanium Ti, zirconium Zr, praseodymium Pr, and lanthanum La. Correspondingly, the material of the gate insulating layer30includes one of aluminum oxide (Al2O3), hafnium oxide (HfO2), titanium oxide (TiO2), zirconium oxide (ZrO2), praseodymium oxide (Pr6O11), and lanthanum oxide (La2O3). The material of the oxide semiconductor layer40includes one of aluminum oxide (Al2O3), hafnium oxide (HfO2), titanium oxide (TiO2), zirconium oxide (ZrO2), praseodymium oxide (Pr6O11), and lanthanum oxide (La2O3).

Preferably, the first metal element is aluminum, and the material of the gate insulating layer30is aluminum oxide.

Specifically, in this embodiment, the material of the gate insulating layer30includes One of aluminum oxide (Al2O3), hafnium oxide (HfO2), titanium oxide (TiO2), zirconium oxide (ZrO2), praseodymium oxide (Pr6O11), and lanthanum oxide (La2O3).

Furthermore, the oxide semiconductor layer40further includes a second metal element and a third metal element. The first metal element, the second metal element, and the third metal element are different metal elements. Alternatively, the second metal element is one of indium In, gallium Ga, zinc Zn, and tin Sn. The third metal element is one of indium In, gallium Ga, zinc Zn, and tin Sn.

Generally, the material of the oxide semiconductor layer40in the prior art is a metal oxide material such as IGZO, and specifically includes four elements of indium In, gallium Ga, zinc Zn, and oxygen O. Since indium In is expensive, in the embodiments of the present disclosure, the first metal element may replace indium In. That is, the second metal element is one of gallium Ga, zinc Zn, and tin Sn. The third metal element is one of gallium Ga, zinc Zn, and tin Sn. On the premise that properties of the oxide semiconductor layer40are not affected, the cost can be greatly reduced.

Specifically, in the embodiment, the first metal element is aluminum Al, the second metal element is gallium Ga, and the third metal element is zinc Zn. Molar contents of the aluminum Al, the gallium Ga, and the zinc Zn satisfy following relationships:
0.1≤Al/(Al+Ga+Zn)≤0.5
0.2≤Ga/(Al+Ga+Zn)≤0.4
0.3≤Zn/(Al+Ga+Zn)≤0.5

Specifically, material of the substrate10includes a glass substrate10. Material of the gate20includes gold (Au), silver (Ag), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), aluminum (Al), molybdenum (Mo), or chromium (Cr) of single or multiple layers. Material of the source-drain metal layer50includes molybdenum, copper, and a molybdenum-copper alloy.

In another embodiments, refer toFIG.3,FIG.4, andFIG.5,FIG.3is a schematic cross-sectional view of a second array substrate of an embodiment of the present disclosure,FIG.4is a schematic cross-sectional view of a third array substrate of an embodiment of the present disclosure, andFIG.5is a schematic cross-sectional view of a fourth array substrate of an embodiment of the present disclosure.FIG.3,FIG.4, andFIG.5are different fromFIG.2in that only a portion of the gate insulating layer30is made of the oxide of the first metal element, and the material of the rest of the gate insulating layer30is a different material from the oxide of the first metal element. Alternatively, the material of the rest of the gate insulating layer30is the same as the material of the gate insulating layer30in the prior art.

To put it simply, in this embodiment, on a basis of the gate insulating layer30in the prior art, the portion of the material of the gate insulating layer30is replaced with the oxide of the first metal element. Alternatively, an additional film layer is added on the basis of maintaining the gate insulating layer30in the prior art. The two layers together constitute the gate insulating layer30in the embodiments of the present disclosure. The material of the film layer is the oxide of the first metal element, so that the transition interface between the gate insulating layer30and the oxide semiconductor layer40has the same material composition, thereby reducing the defect states at the transition interface.

Specifically, the gate insulating layer30includes a first sub-layer301and a second sub-layer302which are connected to each other. The first sub-layer301is disposed on a side of the gate20close to the oxide semiconductor layer40. The second sub-layer302is disposed between the first sub-layer301and the oxide semiconductor layer40. An orthographic projection of the second sub-layer302on the substrate10covers an orthographic projection of the oxide semiconductor layer40on the substrate10. Materials of the first sub-layer301and the second sub-layer302are different, and the material of the second sub-layer302is the oxide of the first metal element.

It can be understood that since the material of the second sub-layer302and the material of the oxide semiconductor layer40are both the oxide of the first metal element, the material of the second sub-layer302is the same as the material of the oxide semiconductor layer40. Also, since the second sub-layer302is in direct contact with the oxide semiconductor layer40, the transition interface between the second sub-layer302and the oxide semiconductor layer40has a lower density of defect states. It is beneficial to improve the mobility and stability of thin film transistors in the array substrate100.

In this embodiment, the material of the first sub-layer301is different from the material of the second sub-layer302. That is, the first sub-layer301and the second sub-layer302are two different film layers. The first sub-layer301and the second sub-layer302are correspondingly formed through different processes.

Specifically, the material of the first sub-layer301includes at least one of silicon nitride, silicon oxide, and silicon oxynitride. In this embodiment, the material of the gate insulating layer30is silicon nitride. The material of the second sub-layer302includes one of aluminum oxide (Al2O3), hafnium oxide (HfO2), titanium oxide (TiO2), zirconium oxide (ZrO2), praseodymium oxide (Pr6O11), and lanthanum oxide (La2O3). In other embodiments, the gate insulating layer30may also be silicon nitride and silicon oxide which are stacked in layers.

Similarly, in this embodiment, the orthographic projection of the second sub-layer302on the substrate10covers the orthographic projection of the oxide semiconductor layer40on the substrate10to ensure that the oxide semiconductor layer40is completely formed on the second sub-layer302. There is no direct contact between the oxide semiconductor layer40and the first sub-layer301, thereby preventing defect states from being generated between the oxide semiconductor layer40and the first sub-layer301. Furthermore, the defect states are prevented from being generated between the oxide semiconductor layer40and the gate insulating layer30.

Specifically, as shown inFIG.3, the first sub-layer301includes a recess301aformed on a side of the first sub-layer301away from the substrate. At least a portion of the recess301ais arranged corresponding to the oxide semiconductor layer40. The second sub-layer302is filled in the recess301a. It should be noted that the “corresponding arrangement” here means that the recess301aand the oxide semiconductor layer40at least partially overlap in a stacking direction.

In this embodiment, there is a certain distance between a bottom of the recess301aand the side of the gate20away from the substrate10. This prevents the gate20from being damaged when the recess301ais formed by a yellow light process, thereby affecting a performance of the thin film transistor.

Specifically, a cross-sectional shape of the recess301amay be one of a rectangle, a trapezoid, and an inverted triangle, which is not limited by the present disclosure.

Specifically, a thickness of the second sub-layer302ranges from 5 nanometers to 1 micrometer. The thickness of the second sub-layer302cannot be set too large or too small. If the thickness is too small, the second sub-layer302is likely to be broken down, and the effect of reducing the defect states of the transition interface between the gate insulating layer30and the oxide semiconductor layer40cannot be achieved. If the thickness is too large, the overall thickness of the array substrate100will increase, which is not conducive to the thinning of products.

As shown inFIG.4andFIG.5, a difference betweenFIG.4andFIG.5andFIG.3is that the second sub-layer302is disposed between the oxide semiconductor layer40and the first sub-layer30, and the oxide semiconductor layer40is disposed on at least one side of the first sub-layer301away from the substrate10.

As shown inFIG.4, the second sub-layer302completely covers all portion of the first sub-layer301. The second sub-layer302can be formed through only one manufacturing process, which is beneficial to reducing manufacturing processes and saving costs.

As shown inFIG.5, a difference betweenFIG.5andFIG.4is that the second sub-layer302covers a portion of the first sub-layer301. The orthographic projection of the second sub-layer302on the substrate10completely overlaps with the orthographic projection of the oxide semiconductor layer40on the substrate10, which is beneficial to saving material costs.

Referring toFIG.6,FIG.6is a schematic cross-sectional view of a fifth array substrate of an embodiment of the present disclosure. A thin film transistor may be a top-gate thin film transistor. The oxide semiconductor layer40, the gate insulating layer30, the gate20, and the source-drain metal layer50are sequentially stacked in a direction away from the substrate. Specifically, the oxide semiconductor layer40is disposed on a side of the substrate10. The gate insulating layer30covers a side of the oxide semiconductor layer40away from the substrate10. The gate20is disposed on a side of the gate insulating layer30away from the substrate10. The source-drain metal layer50is disposed on a side of the oxide semiconductor layer40away from the substrate10. The source-drain metal layer50includes a source51and a drain52. The array substrate100further includes a source-drain insulating layer60disposed between the source-drain metal layer50and the gate20. The source51extends through via holes of the source-drain layer60and the gate insulating layer30and is electrically connected to the oxide semiconductor layer40. The drain52extends through another via holes of the source-drain insulating layer60and the gate insulating layer30and is electrically connected to the oxide semiconductor layer40.

Similarly, in this embodiment, the material of the oxide semiconductor layer40includes the oxide of the first metal element, and the material of a portion of the gate insulating layer30in contact with the oxide semiconductor layer40is the oxide of the first metal element. Since the gate insulating layer30and the oxide semiconductor layer40have the same composition at the transition interface therebetween, the transition interface has a lower density of defect states, which is beneficial to improve the mobility and stability of the thin film transistor.

Specifically, the gate insulating layer30may also include a first sub-layer301and a second sub-layer302which are connected to each other. The first sub-layer301is disposed on a side of the gate20close to the oxide semiconductor layer40. The second sub-layer302is disposed between the first sub-layer301and the oxide semiconductor layer40. The orthographic projection of the second sub-layer302on the substrate10covers the orthographic projection of the oxide semiconductor layer40on the substrate10. At least a portion of the second sub-layer302is in contact with the oxide semiconductor layer40. The materials of the first sub-layer301and the second sub-layer302are different, and the material of the second sub-layer302is oxide of the first metal element.

For example, refer to Table 1. In order to clearly illustrate technical solutions provided by the present disclosure, the applicant takes the first metal element being aluminum Al, the second metal element being gallium Ga, and the third metal element being zinc Zn as an example. The technical solutions provided by the embodiments of the present disclosure have been experimentally verified, and the specific experimental results are now described as follows:

It should be noted that in the process of experimental verification, it is necessary to control the manufacturing process, environmental conditions, and measurement methods to be consistent. The mobility of the finally formed thin film transistor is measured by changing the composition and proportion (target composition) of the metal element in the oxide semiconductor layer40.

It can be seen from the Ref in Table 1 that when the material of the oxide semiconductor layer40in the prior art includes three metal elements of indium In, gallium Ga, and zinc Zn, and molar contents of indium In, gallium Ga, and zinc Zn satisfy the following relationships: In/(In+Ga+Zn)=0.3, Ga/(In+Ga+Zn)=0.3, and Zn/(In+Ga+Zn)=0.4, the device mobility of the thin film transistor is 8.3. When the material of the oxide semiconductor layer40includes three metal elements of aluminum Al, gallium Ga, and zinc Zn, the device mobility of the thin film transistor is all greater than 8.3. It can be seen that the technical solutions provided by the embodiments of the present disclosure can improve the mobility and stability of the thin film transistor.

In addition, Example 1, Example 2, Example 3, and Example 4 are compared. In Example 1, the molar contents of aluminum Al, gallium Ga, and zinc Zn in the oxide semiconductor layer40satisfy the following relationships:
Al/(Al+Ga+Zn)=0.3
Ga/(Al+Ga+Zn)=0.3
Zn/(Al+Ga+Zn)=0.4

At this time, the device mobility of the thin film transistor is 10.6.

In Example 2, the molar contents of aluminum Al, gallium Ga, and zinc Zn in the oxide semiconductor layer40satisfy the following relationships:
Al/(Al+Ga+Zn)=0.4
Ga/(Al+Ga+Zn)=0.3
Zn/(Al+Ga+Zn)=0.4

At this time, the device mobility of the thin film transistor is 16.

In Example 3, the molar contents of aluminum Al, gallium Ga, and zinc Zn in the oxide semiconductor layer40satisfy the following relationships:
Al/(Al+Ga+Zn)=0.4
Ga/(Al+Ga+Zn)=0.3
Zn/(Al+Ga+Zn)=0.4

At this time, the device mobility of the thin film transistor is 16.

In Example 4, the molar contents of aluminum Al, gallium Ga, and zinc Zn in the oxide semiconductor layer40satisfy the following relationships:
Al/(Al+Ga+Zn)=0.1
Ga/(Al+Ga+Zn)=0.4
Zn/(Al+Ga+Zn)=0.5

At this time, the device mobility of the thin film transistor is 2.3.

It can be seen that, as the molar content of aluminum Al in the oxide semiconductor layer40increases, the device mobility of the thin film transistor is improved. Therefore, the content of aluminum Al in the oxide semiconductor layer40can be set larger within an allowable range.

TABLE 1RefExample 1Example 2Example 3Example 4targetIn/(In + Ga +Al/(Al + Ga +Al/(Al + Ga +Al/(Al + Ga +Al/(Al + Ga +compositionZn) = 0.3Zn) = 0.3Zn) = 0.4Zn) = 0.5Zn) = 0.1Ga/(In + Ga +Ga/(Al + Ga +Ga/(Al + Ga +Ga/(Al + Ga +Ga/(Al + Ga +Zn) = 0.3Zn) = 0.3Zn) = 0.3Zn) = 0.2Zn) = 0.4Zn/(In + Ga +Zn/(Al + Ga +Zn/(Al + Ga +Zn/(Al + Ga +Zn/(Al + Ga +Zn) = 0.4Zn) = 0.4Zn) = 0.3Zn) = 0.3Zn) = 0.5Mobility8.310.616252.3(cm2/Vs)

Furthermore, refer toFIG.7,FIG.7is a schematic cross-sectional view of a sixth array substrate of an embodiment of the present disclosure. The array substrate10of the embodiment of the present disclosure further includes a passivation layer200and a pixel electrode300. The passivation layer200covers a side of the source-drain52of the metal layer50away from the substrate10. The pixel electrode300is disposed on a side of the passivation layer200away from the substrate10. The pixel electrode300is electrically connected to the source-drain52of the metal layer50through a via hole200aextending through the passivation layer200.

Specifically, material of the passivation layer200includes one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. Material of the pixel electrode300includes indium tin oxide.

Furthermore, an embodiment of the present disclosure also provides a display panel. The display panel includes an opposite substrate400and the array substrate100in the above embodiments. The opposite substrate400is relatively spaced apart from the array substrate100.

Advantages are as follows. In the array substrate and the display panel of the present disclosure, the material of the oxide semiconductor layer includes the oxide of the first metal element, and the material of at least the portion of the gate insulating layer in contact with the oxide semiconductor layer includes the oxide of the first metal element. Since the gate insulating layer and the oxide semiconductor layer have the same composition at a transition interface therebetween, the transition interface has a lower density of defect states. In the prior art, since the gate insulating layer and the oxide semiconductor layer have different materials, direct contact between the two causes many defect states at the transition interface. The above situation is prevented, which is beneficial to improve the mobility and stability of the thin film transistor.

In conclusion, although the present disclosure has been disclosed above with preferred embodiments, the above preferred embodiments are not intended to limit the present disclosure. Various changes and modifications can be made by those of ordinary skill in the art without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure is subject to the scope defined by the claims.