Patent ID: 12230693

DETAILED DESCRIPTION OF THE EMBODIMENTS

In the description hereafter, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure may be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described.

In an exemplary technique, as shown inFIG.1, a semiconductor device includes a substrate100, a well region101, an isolation structure102, drift regions103and104, a source region105, a drain region106, and a gate structure107. The withstand voltage of the transistor is carried by a lateral drift, region, and the drift region of a transistor with a certain withstand voltage would have a certain length, or in other words, would have a lower limit for the length (the physical limit of silicon withstand voltage). Therefore, the size of the drift region cannot be reduced indefinitely. Even if the characteristic size of the process is reduced, the size of the withstand voltage cannot be reduced.

In view of the deficiencies of the semiconductor device shown inFIG.1, the present disclosure provides a semiconductor device and a manufacturing method therefor.

Referring toFIGS.2A and2B, in which,FIG.2Ais a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present disclosure, andFIG.2Bis a cross-sectional view of another semiconductor device according to an exemplary embodiment of the present disclosure.

According to an embodiment of the present disclosure, the structure of the semiconductor device provided by the embodiment of the present disclosure will be described with reference toFIG.2AandFIG.2B. The semiconductor device includes:a semiconductor substrate200, in which a first drift region204is formed;a gate structure207is formed on the semiconductor substrate, and a part of the gate structure207covers a part of the first drift region204; anda first trench is formed in the first drift region204, and a drain region206is formed in the semiconductor substrate at a bottom of the first trench.

Illustratively, the semiconductor device includes an LDMOS device or an EDMOS device.

Illustratively, the semiconductor substrate200may be at least one of the following mentioned materials: single crystal silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), and the like. In this embodiment, the semiconductor substrate200is a P-type silicon substrate (P-sub), and a specific doping concentration thereof is not limited by the present disclosure. The semiconductor substrate200may be formed by epitaxial growth, or may be a wafer substrate.

Illustratively, an isolation structure202is further formed in the semiconductor substrate200. The isolation structure202is a shallow trench isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure. The isolation structure divides the semiconductor substrate200into different active regions, and various semiconductor devices, such as N-type metal oxide semiconductor (NMOS) and P-type metal oxide semiconductor (PMOS) and the like, can be formed in the active regions. Various well structures are further formed in the semiconductor substrate200.

Illustratively, a well region201is formed in the semiconductor substrate200. As an example, a P-type well region (P-well) is formed in the semiconductor substrate200.

Illustratively, at least a first drift region (Drift)204is formed in the semiconductor substrate200.

In an embodiment, only the first drift region204is formed in the semiconductor substrate, as shown inFIG.2B.

In another embodiment, a first drift region204and a second drift region203are formed in the semiconductor substrate, as shown inFIG.2A.

Illustratively, a gate structure207is formed on the semiconductor substrate200. The gate structure207includes a gate dielectric layer and a gate material layer sequentially stacked from bottom to top. The gate dielectric layer includes an oxide layer, such as a silicon dioxide (SiO2) layer. The gate material layer includes one or more of a polysilicon layer, a metal layer, a conductive metal nitride layer, a conductive metal oxide layer, and a metal silicide layer. Spacer structures located at two sides of the gate structure207and close to the gate structure207are further formed on the semiconductor substrate200.

In an embodiment, as shown inFIG.2A, the second drift region203and the first drift region204are respectively disposed on two sides of the gate structure207, a part of the gate structure207covers a part of the first drift region204, and a part of the gate structure207covers a part of the second drift region203.

In another embodiment, as shown inFIG.2B, a part of the gate structure207covers a part of the first drift region204.

By forming the first drift region204and the second drift region203located on two sides of the gate structure207, a symmetric transistor is formed, as shown inFIG.2A; while, when the first drift region204is formed on only one side of the gate structure207, then an asymmetric transistor can be formed, as shown inFIG.2B.

Illustratively, a first trench is formed in the first drift region204, and a drain region206is formed in the semiconductor substrate200at the bottom of the first trench.

In an embodiment, as shown inFIG.2B, a first trench is formed in the first drift region204, and a drain region206is formed in the semiconductor substrate200at the bottom of the first trench. A source region205is formed on a surface of the semiconductor substrate200, and the source region205and the drain region206are respectively disposed on two sides of the gate structure207.

By forming the first trench in the first drift region204and forming the drain region206in the semiconductor substrate200at the bottom of the first trench, the length of the first drift region204is lengthened longitudinally, thereby improving the withstand voltage of the drain terminal of the semiconductor device while reducing the area of the semiconductor device.

In another embodiment, as shown inFIG.2A, a first trench is formed in the first drift region204, and a drain region206is formed in the semiconductor substrate200at the bottom of the first trench, a second trench is formed in the second drift region203, and a source region205is formed in the semiconductor substrate200at the bottom of the second trench.

By forming the first trench and the second trench in the first drift region204and the second drift region203respectively, forming the drain region206in the semiconductor substrate200at the bottom of the first trench, and forming the source region205in the semiconductor substrate200at the bottom of the second trench, the lengths of the first drift region204and the second drift region203are lengthened longitudinally, thereby improving the withstand voltage of the two terminals of the semiconductor device while reducing the area of the semiconductor device.

Referring toFIGS.2A,2B, and3, in which,FIG.2Ais a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present disclosure,FIG.2Bis a cross-sectional view of another semiconductor device according to an exemplary embodiment of the present disclosure, andFIG.3shows a schematic flowchart of a manufacturing method for a semiconductor device according to an exemplary embodiment of the present disclosure.

The present disclosure provides a manufacturing method for a semiconductor device, as shown inFIG.3, which mainly includes the following steps.

At step S301, a semiconductor substrate is provided, and a first drift region is formed in the semiconductor substrate.

At step S302, a gate structure is formed on the semiconductor substrate, a part of the gate structure covers a part of the first drift region.

At step S303, the first drift region is etched to form a first trench in the first drift region.

At step S304, ion implantation is performed to form a drain region in the semiconductor substrate at a bottom of the first trench.

The manufacturing method for a semiconductor device of the present disclosure specifically includes the following steps.

First, step S101is performed: a semiconductor substrate200is provided, and a first drift region204is formed in the semiconductor substrate.

Illustratively, the semiconductor device includes an LDMOS device or an EDMOS device.

Illustratively, the semiconductor substrate200may be at least one of the following mentioned materials: single crystal silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), and the like. In this embodiment, the semiconductor substrate200is a P-type silicon substrate (P-sub), and a specific doping concentration thereof is not limited by the present disclosure. The semiconductor substrate200may be formed by epitaxial growth, or may be a wafer substrate.

Illustratively, an isolation structure202is further formed in the semiconductor substrate200, The isolation structure202is a shallow trench isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure. The isolation structure divides the semiconductor substrate200into different active regions, and various semiconductor devices, such as NMOS and PMOS and the like, can be formed in the active regions. Various well structures are further formed in the semiconductor substrate200.

Illustratively, a well region201is formed in the semiconductor substrate200.

Illustratively, the well region201is formed in the semiconductor substrate200by using a well implantation process. As an example, a P-type well region (P-well) is formed in the semiconductor substrate by using a standard well implantation process. The P-type well region can be formed by a high energy implantation process, or the P-type well region can be formed by a low energy implantation in combination with a high-temperature thermal annealing process.

Illustratively, a first drift region204is formed in the semiconductor substrate.

Illustratively, at least a first drift region (Drift)204is formed in the semiconductor substrate200. In an embodiment, only the first drift region204is formed in the semiconductor substrate, as shown inFIG.2B. In another embodiment, a first drift region204and a second drift region203are formed in the semiconductor substrate, as shown inFIG.2A.

Illustratively, the first drift region204and/or the second drift region203are located in the semiconductor substrate200and are generally lightly doped regions. For N-channel transistors, the drift regions are N-type doped. As an example, first, a drift region masking layer is formed on the semiconductor substrate200. Specifically, the drift region masking layer is a photoresist layer. Then, an opening pattern is formed in the photoresist by exposing and developing processes. Then, the first drift region204and/or the second drift region203are formed in the region of the opening by a high-energy implantation process, alternatively, the first drift region204and/or the second drift region203may also be formed by a low-energy implantation in combination with a high-temperature thermal annealing process.

Next, step S102is performed: a gate structure207is formed on the semiconductor substrate200, and a part of the gate structure207covers a part of the first drift region204.

Illustratively, a gate structure207is formed on the semiconductor substrate200, The gate structure207includes a gate dielectric layer and a gate material layer sequentially stacked from bottom to top. The gate dielectric layer includes an oxide layer, such as a silicon dioxide (SiO2) layer. The gate material layer includes one or more of a polysilicon layer, a metal layer, a conductive metal nitride layer, a conductive metal oxide layer, and a metal suicide layer. Spacer structures located at two sides of the gate structure207and close to the gate structure207are further formed on the semiconductor substrate200.

In an embodiment, as shown inFIG.2A, the second drift region203and the first drift region204are respectively disposed on two sides of the gate structure207, a part of the gate structure207covers a part of the first drift region204, and a part of the gate structure207covers a part of the second drift region203.

In another embodiment, as shown inFIG.2B, a part of the gate structure207covers a part of the first drift region204.

By forming the first drift region204and the second drift region203located on two sides of the gate structure207, a symmetric transistor is formed, as shown inFIG.2A; while, when the first drift region204is formed on only one side of the gate structure207, then an asymmetric transistor can be formed, as shown inFIG.2B.

Next, step S303is performed: the first drift region204is etched to form a first trench in the first drift region204.

In an embodiment, as shown inFIG.2B, only the first drift region204is etched to form the first trench in the first drift region204.

In another embodiment, as shown inFIG.2A, the first drift region204and the second drift region203are etched to form the first trench in the first drift region204and to form the second trench in the second drift region203.

For etching the first drift region204and/or the second drift region203, dry etching or wet etching may be used. Illustratively, the dry etching process includes, but is not limited to, reactive ion etching (RIE), ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method may also be used, or more than one etching method may be used. The source gas for the dry etching may include HBr and/or CF4gas.

Next, step S304is performed: ion implantation is performed to form a drain region206in the semiconductor substrate200at the bottom of the first trench.

Illustratively, the method further includes a step of forming a source region205at the same time of forming the drain region206.

In an embodiment, as shown inFIG.2B, the step of forming the source region205includes: performing ion implantation to form the source region205on a surface of the semiconductor substrate200.

In another embodiment, as shown inFIG.2A, the step of forming the source region205includes: performing ion implantation to form the source region205in the semiconductor substrate200at a bottom of the second trench.

As an example, N-type impurities are implanted into the surface of the semiconductor substrate200or in the semiconductor substrate200at the bottom of the second trench to form the source region205, and N-type impurities are implanted in the semiconductor substrate200at the bottom of the first trench to form the drain region206. The doping concentration of the source region205and the doping concentration of the drain region206may be the same. Therefore, the source region205and the drain region206can be formed by doping simultaneously.

By forming the first trench in the first drift region204and forming the drain region206in the semiconductor substrate200at the bottom of the first trench, the length of the first drift region204is lengthened longitudinally, thereby improving the withstand voltage of the drain terminal of the semiconductor device while reducing the area of the semiconductor device.

Further, by forming the first trench and the second trench in the first drift region204and the second drift region203respectively, forming the drain region206in the semiconductor substrate200at the bottom of the first trench, and forming the source region205in the semiconductor substrate200at the bottom of the second trench, the lengths of the first drift region204and the second drift region203are lengthened longitudinally, thereby improving the withstand voltage of the two terminals of the semiconductor device while reducing the area of the semiconductor device.

The present disclosure has been described through the above embodiments, but it should be understood that, the above embodiments are merely for the purpose of illustration and description, and are not intended to limit the present disclosure to the scope of the described embodiments. In addition, those skilled in the art can understand that, the present application is not limited to the above described embodiments, further variations and modifications can be made according to the teachings of the present disclosure, and these variations and modifications all fall within the claimed protection scope of the present disclosure. The protection scope of the present disclosure is defined by the appended claims and equivalent scope thereof.