Patent ID: 12224315

DETAILED DESCRIPTION

Although the drawings of a semiconductor device according to some embodiments show a fin-type transistor (FinFET) including a channel region of a fin-type pattern shape, embodiments are not limited thereto. For example, embodiments may include a transistor having, e.g., a nanowire or a nanosheet, and a MBCFET™ (Multi-Bridge Channel Field Effect Transistor). The semiconductor device according to some embodiments may include a tunneling field effect transistor (FET) or a three-dimensional (3D) transistor. The semiconductor device according to some embodiments may include a planar transistor. In addition, embodiments may be applied to a transistor based on two-dimensional material (2D material based FETs) and a heterostructure thereof. Further, the semiconductor device according to some embodiments may also include a bipolar junction transistor, a laterally diffused metal oxide semiconductor (LDMOS), or the like.

The semiconductor device according to some embodiments will be described hereinafter referring toFIGS.1to4.

FIG.1is an exemplary layout diagram of a semiconductor device according to some embodiments.FIG.2is an exemplary cross-sectional view along line A-A′ ofFIG.1, andFIG.3is an exemplary cross-sectional view along line B-B′ ofFIG.1.

Referring toFIGS.1to3, a semiconductor device according to some embodiments may include at least one or more first active patterns AP1, at least one or more second active patterns AP2, first to third gate electrodes120,220and320, a first active contact180, a second active contact280, and a gate contact160on a substrate100.

The substrate100may include a first active region RX1, a second active region RX2, and a field region FX, as illustrated inFIG.1. The field region FX may be formed immediately adjacent to the first active region RX1and the second active region RX2. The field region FX may form a boundary between the first active region RX1and the second active region RX2.

The first active region RX1and the second active region RX2are spaced apart from each other, e.g., along a second direction Y. The first active region RX1and the second active region RX2may be separated by the field region FX.

In other words, an element separation film may be placed around the first active region RX1and the second active region RX2which are spaced apart from each other. At this time, in the element separation film, a portion between the first active region RX1and the second active region RX2may be the field region FX. For example, a first portion, in which a channel region of the transistor (which may be an example of the semiconductor device) is formed, may be the active region, and a second portion that divides the channel region of the transistor may be the field region. In another example, the active region may be a portion in which the fin-type pattern or nanosheet used as the channel region of the transistor is formed, and the field region may be a region in which the fin-type pattern or nanosheet is not formed. For example, as shown inFIG.3, the field region FX may be defined by a deep trench DT.

In some embodiments, one of the first active region RX1and the second active region RX2may be a PMOS formation region, and the other thereof may be an NMOS formation region. In another embodiment, the first active region RX1and the second active region RX2may be the PMOS formation region. In yet another embodiment, the first active region RX1and the second active region RX2may be the PMOS formation region.

For example, the substrate100may be a silicon substrate or an SOI (silicon-on-insulator) substrate. In another example, the substrate100may further include silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead tellurium compounds, indium arsenic, indium phosphide, gallium arsenide or gallium antimonide.

At least one or more first active patterns AP1may be formed in the first active region RX1. The first active pattern AP1may protrude from the substrate100of the first active region RX1. The first active pattern AP1may extend long, e.g., lengthwise, along the first direction X on the substrate100. For example, the first active pattern AP1may include a long side extending in the first direction X, and a short side extending in the second direction Y. Here, the first direction X may intersect the second direction Y and a third direction Z. Also, the second direction Y may intersect the third direction Z.

At least one or more second active patterns AP2may be formed in the second active region RX2. Description of the second active pattern AP2may be substantially the same as that of the first active pattern AP1.

The first active pattern AP1and the second active pattern AP2may each be multi-channel active patterns. In the semiconductor device according to some embodiments, each of the first active pattern AP1and the second active pattern AP2may be, e.g., a fin-type pattern. Each of the first active pattern AP1and the second active pattern AP2may be used as a channel pattern of the transistor. Although each of the number of the first active patterns AP1and the second active patterns AP2is shown as three in the figures, any suitable number of each of the first and second active patterns AP1and AP2may be used. Each of the number of the first active patterns AP1and the second active patterns AP2may be one or more.

Each of the first active pattern AP1and the second active pattern AP2may be a part of the substrate100, and may include an epitaxial layer that is grown from the substrate100. The first active pattern AP1and the second active pattern AP2may include, e.g., silicon and germanium which is an elemental semiconductor material. Further, the first active pattern AP1and the second active pattern AP2may include a compound semiconductor, e.g., a group IV-IV compound semiconductor or a group III-V compound semiconductor.

For example, the group IV-IV compound semiconductor may include a binary compound or a ternary compound containing at least two or more of, e.g., carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound obtained by doping these elements with a group IV element. For example, the group compound semiconductor may be at least one of a binary compound, a ternary compound or a quaternary compound formed by combining at least one of, e.g., aluminum (Al), gallium (Ga) and indium (In) as a group III element with one of phosphorus (P), arsenic (As) and antimony (Sb) as a group V element.

In some embodiments, the first active pattern AP1and the second active pattern AP2may include the same material. In other embodiments, the first active pattern AP1and the second active pattern AP2may include materials different from each other.

As illustrated inFIG.3, a field insulating film105may be formed on the substrate100. The field insulating film105may be formed over the first active region RX1, the second active region RX2, and the field region FX. The field insulating film105may fill the deep trench DT.

The field insulating film105may be partially formed on side walls of the first active pattern AP1and side walls of the second active pattern AP2. Each of the first active pattern AP1and the second active pattern AP2may protrude upward from, e.g., above, the upper surface of the field insulating film105. The field insulating film105may include, e.g., an oxide film, a nitride film, an oxynitride film or a combination film thereof.

As illustrated inFIG.2, first to third gate structures GS1, GS2and GS3may be placed on the substrate100. The first to third gate structures GS1, GS2and GS3may extend in the second direction Y (into the page ofFIG.2). The first gate structure GS1, the second gate structure GS2, and the third gate structure GS3may be spaced apart from each other in the first direction X. The second gate structure GS2may be placed between the first gate structure GS1and the third gate structure GS3. Since the second gate structure GS2and the third gate structure GS3may be substantially the same as the first gate structure GS1, only the first gate structure GS1will be explained below.

The first gate structure GS1may be placed on the first active pattern AP1and the second active pattern AP2. The first gate structure GS1may intersect the first active pattern AP1and the second active pattern AP2.

Although the first gate structure GS1is shown as being placed over the first active region RX1and the second active region RX2, this is merely for convenience of explanation, and the embodiment is not limited thereto. That is, a part of the first gate structure GS1is divided into two parts by a gate separation structure placed on the field insulating film105, and may be placed on the first active region RX1and the second active region RX2.

The first gate structure GS1may include, e.g., a first gate electrode120, a first gate insulating film130, a first gate spacer140, and a first gate capping pattern150. The second gate structure GS2may include, e.g., a second gate electrode220, a second gate insulating film230, a second gate spacer240, and a second gate capping pattern250. The third gate structure GS3may include, e.g., a third gate electrode320, a third gate insulating film330, a third gate spacer340, and a third gate capping pattern350.

Since the second gate electrode220and the third gate electrode320are substantially the same as the first gate electrode120, only the first gate electrode120will be described below. Since the second gate insulating film230and the third gate insulating film330are substantially the same as the first gate insulating film130, only the first gate insulating film130will be described below. Since the second gate spacer240and the third gate spacer340are substantially the same as the first gate spacer140, only the first gate spacer140will be described below. Since the second gate capping pattern250and the third gate capping pattern350are substantially the same as the first gate capping pattern150, only the first gate capping pattern150will be described below.

The first gate electrode120may be formed on the first active pattern AP1and the second active pattern AP2. The first gate electrode120may intersect the first active pattern AP1and the second active pattern AP2. The first gate electrode120may wrap the first active pattern AP1and the second active pattern AP2that protrude upward from the upper surface of the field insulating film105. The first gate electrode120may include a long side extending in the second direction Y, and a short side extending in the first direction X.

The first gate electrode120may include, e.g., at least one of titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC—N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni—Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof. The first gate electrode120may include a conductive metal oxide, a conductive metal oxynitride, and the like, and may also include an oxidized form of the above-mentioned materials.

The first gate spacer140may be placed on the side walls of the first gate electrode120. The first gate spacer140may extend in the second direction Y. The first gate spacer140may include, e.g., at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBN), silicon oxyboronitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

The first gate insulating film130may extend along the side walls and the lower surface of the first gate electrode120. The first gate insulating film130may be formed on the first active pattern AP1, the second active pattern AP2, and the field insulating film105. The first gate insulating film130may be formed between the first gate electrode120and the first gate spacer140.

The first gate insulating film130may be formed along a profile of the first active pattern AP1protruding upward from the field insulating film105and the upper surface of the field insulating film105. Although not shown, an interfacial film may be further formed along the profile of the first active pattern AP1protruding upward from the field insulating film105. The first gate insulating film130may be formed on the interfacial film. Although not shown, the first gate insulating film130may be formed along the profile of the second active pattern AP2protruding upward from the field insulating film105.

The first gate insulating film130may include, e.g., at least one of silicon oxide, silicon oxynitride, silicon nitride or a high dielectric constant material having a higher dielectric constant than silicon oxide. The high dielectric constant material may include, e.g., one or more of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide or lead zinc niobate.

The semiconductor device according to some other embodiments may include an NC (Negative Capacitance) FET using a negative capacitor. For example, the first gate insulating film130may include a ferroelectric material film having ferroelectric properties, and a paraelectric material film having the paraelectric properties.

The ferroelectric material film may have a negative capacitance, and the paraelectric material film may have a positive capacitance. For example, when two or more capacitors are connected in series, and the capacitance of each capacitor has a positive value, the entire capacitance decreases from the capacitance of each individual capacitor. On the other hand, when at least one of the capacitances of two or more capacitors connected in series has a negative value, the entire capacitance may be greater than an absolute value of each individual capacitance, while having a positive value.

When the ferroelectric material film having the negative capacitance and the paraelectric material film having the positive capacitance are connected in series, the entire capacitance values of the ferroelectric material film and the paraelectric material film connected in series may increase. Taking advantage of the increased overall capacitance value, a transistor including the ferroelectric material film may have a subthreshold swing (SS) below 60 mV/decade at room temperature.

The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may include, e.g., at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, the hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). As another example, the hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

The ferroelectric material film may further include a doped dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant included in the ferroelectric material film may vary, depending on which type of ferroelectric material is included in the ferroelectric material film.

When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film may include, e.g., at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y). When the dopant is aluminum (Al), the ferroelectric material film may include 3 at % (atomic %) to 8 at % aluminum. Here, a ratio of the dopant may be a ratio of aluminum to the sum of hafnium and aluminum.

When the dopant is silicon (Si), the ferroelectric material film may include 2 at % to 10 at % silicon. When the dopant is yttrium (Y), the ferroelectric material film may include 2 at % to 10 at % yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may include 1 at % to 7 at % gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may include 50 at % to 80 at % zirconium.

The paraelectric material film may have paraelectric properties. The paraelectric material film may include at least one of, e.g., a silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material film may include, e.g., at least one of hafnium oxide, zirconium oxide, and aluminum oxide.

The ferroelectric material film and the paraelectric material film may include the same material. The ferroelectric material film has the ferroelectric properties, but the paraelectric material film may not have the ferroelectric properties. For example, when the ferroelectric material film and the paraelectric material film include hafnium oxide, a crystal structure of hafnium oxide included in the ferroelectric material film is different from a crystal structure of hafnium oxide included in the paraelectric material film.

The ferroelectric material film may have a thickness having the ferroelectric properties. A thickness of the ferroelectric material film may be, e.g., 0.5 nm to 10 nm. Since a critical thickness that exhibits the ferroelectric properties may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

In some embodiments, the first gate insulating film130may include one ferroelectric material film. In another embodiment, the first gate insulating film130may include a plurality of ferroelectric material films spaced apart from each other. The first gate insulating film130may have a stacked film structures in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

The first gate capping pattern150may be placed on the upper surface of the first gate electrode120and the upper surface of the first gate spacer140. The first gate capping pattern150may be formed inside a first gate capping recess150R. The first gate capping pattern150may include a first gate capping liner151and a first gate capping filling film153.

The first gate capping liner151may define the first gate capping recess150R. The first gate capping liner151may be formed along the profile of the first gate capping recess150R. The first gate capping liner151may extend along the upper surface of the first gate electrode120. The first gate capping liner151may extend along the upper surface of the first gate spacer140. The first gate capping liner151may include, e.g., at least one of aluminum oxide (AlO), aluminum nitride (AlN), silicon oxycarbide (SiOC), and a combination thereof.

The first gate capping filling film153may be placed on the first gate capping liner151, e.g., the first gate capping liner151may be between the first gate capping filling film153and the first gate electrode120. The first gate capping filling film153may fill the first gate capping recess150R. The first gate capping filling film153may include, e.g., at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof.

A first epitaxial pattern170and a second epitaxial pattern270may be formed on the first active pattern AP1. The first epitaxial pattern170and the second epitaxial pattern270may be located on the substrate100. The first epitaxial pattern170may be placed between the first gate structure GS1and the second gate structure GS2. The second epitaxial pattern270may be placed between the second gate structure GS2and the third gate structure GS3.

The first and second epitaxial patterns170and270may be source/drain regions. That is, the first and second epitaxial patterns170and270may be included in the source/drain region of the transistor that uses the first active pattern AP1as a channel region.

A first etching stop film176may be placed on the side wall of the first gate structure GS1, the side wall of the second gate structure GS2, and the upper surface of the first epitaxial pattern170. The first etching stop film176may include a material having an etching selectivity with respect to an interlayer insulating film190to be described below. The first etching stop film176may include, e.g., at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBN), silicon oxyboronitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

A second etching stop film276may be placed on the side wall of the second gate structure GS2, the side wall of the third gate structure GS3, and the upper surface of the second epitaxial pattern270. The second etching stop film276may include, e.g., at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBN), silicon oxyboronitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

The interlayer insulating film190may be placed on the first epitaxial pattern170and the second epitaxial pattern270. The interlayer insulating film190may not cover the upper surfaces of the first gate capping pattern150, the second gate capping pattern250, and the third gate capping pattern350. For example, the upper surface of the interlayer insulating film190may be placed on the same plane as the upper surfaces of the first gate capping pattern150, the second gate capping pattern250, and the third gate capping pattern350.

The interlayer insulating film190may include, e.g., at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. The low dielectric constant material may include, e.g., Fluorinated TetraEthylOrthoSilicate (FTEOS), Hydrogen SilsesQuioxane (HSQ), Bis-benzoCycloButene (BCB), TetraMethylOrthoSilicate (TMOS), OctaMethylcyCloTetraSiloxane (OMCTS), HexaMethylDiSiloxane (HMDS), TriMethylSilyl Borate (TMSB), DiAcetoxyDitertiaryButoSiloxane (DADBS), TriMethylSilil Phosphate (TMSP), PolyTetraFluoroEthylene (PTFE), TOSZ (Tonen SilaZen), FSG (Fluoride Silicate Glass), polyimide nanofoams such as polypropylene oxide, CDO (Carbon Doped silicon Oxide), OSG (Organo Silicate Glass), SiLK, Amorphous Fluorinated Carbon, silica aerogels, silica xerogels, mesoporous silica or combinations thereof.

The first active contact180and the second active contact280may be placed on the first active region RX1. A third active contact380and a fourth active contact480may be placed on the second active region RX2.

The first active contact180may be connected to the first epitaxial pattern170formed in the first active region RX1. The second active contact280may be connected to the second epitaxial pattern270formed in the first active region RX1. Although not shown, the third active contact380and the fourth active contact480may be connected to a source/drain region formed in the second active region RX2. Since the third active contact380and the fourth active contact480are substantially the same as the first active contact180and the second active contact280, only the first and second active contacts180and280will be described below.

The gate contact160may be placed inside the first gate structure GS1. The gate contact160may be connected to the first gate electrode120. The gate contact160may be placed at a position where it overlaps the first gate structure GS1. In some embodiments, at least a part of the gate contact160may be placed at a position where it overlaps the first active pattern AP1.

The gate contact160may include a gate barrier film161, and a gate filling film163on the gate barrier film161. The gate barrier film161may extend along the side walls and the lower surface of the gate filling film163. Although a lower surface160_BS of the gate contact160is shown to have a wavy shape, the embodiment is not limited thereto.

The gate barrier film161may include, e.g., at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium (Ru), cobalt (Co), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh) and a two-dimensional (2D) material. In the semiconductor device according to some embodiments, the two-dimensional material may be a metallic material and/or a semiconductor material. The two-dimensional (2D material) may include a two-dimensional allotrope or a two-dimensional compound, and may include, but is not limited to, e.g., at least one of graphene, molybdenum disulfide (MoS2), molybdenum diselenide (MoSe2), tungsten diselenide (WSe2), tungsten disulfide (WS2). That is, since the above-mentioned two-dimensional materials are only listed by way of example, the two-dimensional materials that may be included in the semiconductor device of the present disclosure are not limited by the above-mentioned materials.

The gate filling film163may include, e.g., at least one of aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), silver (Ag), gold (Au), manganese (Mn), and molybdenum (Mo).

The first active contact180may be connected to the first epitaxial pattern170. The second active contact280may be connected to the second epitaxial pattern270. The first active contact180and the second active contact280may be placed inside the interlayer insulating film190. The first active contact180and the second active contact280may be surrounded by the interlayer insulating film190.

A first silicide film175may be formed between the first active contact180and the first epitaxial pattern170. A second silicide film275may be formed between the second active contact280and the second epitaxial pattern270. Although the first silicide film175is shown as being formed along the profile of an interface between the first epitaxial pattern170and the first active contact180, the embodiment is not limited thereto. Similarly, although the second silicide film275is shown as being formed along the profile of the interface between the second epitaxial pattern270and the second active contact280, the embodiment is not limited thereto. The first silicide film175and the second silicide film275may include, e.g., a metal silicide material.

The first active contact180may include a first active barrier film181, and a first active filling film183on the first active barrier film181. The first active barrier film181may extend along the side walls and the lower surface of the first active filling film183. The contents of the materials included in the first active barrier film181and the first active filling film183may be the same as the description of the materials included in the gate barrier film161and the gate filling film163.

In terms of a cross-section, the lower surface160_BS of the gate contact160is higher than an upper surface180_US of the first active contact180. That is, a height from the upper surface AP1_US of the first active pattern AP1to the lower surface160_BS of the gate contact160is greater than a height from the upper surface AP1_US of the first active pattern AP1to the upper surface180_US of the first active contact180.

In terms of a cross-section, the upper surface180_US of the first active contact180is lower than the upper surface280_US of the second active contact280. That is, the height from the upper surface AP1_US of the first active pattern AP1to the upper surface180_US of the first active contact180is smaller than the height from the upper surface AP1_US of the first active pattern AP1to the upper surface280_US of the second active contact280.

FIG.4is an enlarged view of portion P ofFIG.2. The gate contact160, the first gate capping pattern150, the second gate capping pattern250, the first active contact180, and the second active contact280will be explained in detail, usingFIG.4. For convenience of explanation, only enlarged features not illustrated previously inFIGS.1to3will be mainly described.

Referring toFIG.4, the first gate capping pattern150may include a first gate capping liner151and a first gate capping filling film153. The second gate capping pattern250may include a second gate capping liner251and a second gate capping filling film253. The third gate capping pattern350may include a third gate capping liner351and a third gate capping filling film353.

The first gate capping liner151may define a first gate capping recess150R. The second gate capping liner251may define a second gate capping recess250R. The third gate capping liner351may define a third gate capping recess350R.

The first gate capping liner151may be placed on a part of the side wall of the gate contact160. The second gate capping liner251and the third gate capping liner351may be placed on parts of the side walls of the second active contact280, e.g., the second gate capping liner251and the third gate capping liner351may be on opposite walls of the second active contact280. The first gate capping liner151may extend to the upper surface160_US of the gate contact160. The second gate capping liner251and the third gate capping liner351may extend to the upper surface280_US of the second active contact280.

The first gate capping filling film153may fill the first gate capping recess150R. The second gate capping filling film253may fill the second gate capping recess250R. The third gate capping filling film353may fill the third gate capping recess350R.

The first gate capping liner151may include a first horizontal portion151HP extending along the upper surface of the first gate structure GS1, e.g., the first gate electrode120, and a first vertical portion151VP extending in the third direction Z from the first horizontal portion151HP. For example, as illustrated inFIG.4, the first horizontal portion151HP may overlap the upper surface of the first gate electrode120, continuously extend to overlap the upper surface of the first gate insulating film130, and continuously extend to overlap the upper surface of first gate spacer140. For example, referring toFIGS.3and4, the first horizontal portion151HP may directly contact the upper surface of the first gate electrode120around the gate contact160.

The second gate capping liner251may include a second horizontal portion251HP extending along the upper surface of the second gate electrode220, and a second vertical portion251VP extending from the second horizontal portion251HP in the third direction Z.

The first horizontal portion151HP extends along the upper surface140_US of the first gate spacer140. That is, at least a part of the first horizontal portion151HP overlaps the upper surface140_US of the first gate spacer140in the third direction Z.

The second horizontal portion251HP extends along the upper surface240_US of the second gate spacer240. That is, at least a part of the second horizontal portion251HP overlaps the upper surface240_US of the second gate spacer240in the third direction Z.

The first vertical portion151VP extends along the side wall of the first gate capping filling film153. The first vertical portion151VP may be placed on the side wall of the first gate capping filling film153. The second vertical portion251VP extends along the side wall of the second gate capping filling film253. The second vertical portion251VP may be placed on the side wall of the second gate capping filling film253.

In some embodiments, the first vertical portion151VP may extend to the upper surface160_US of the gate contact160. The second vertical portion251VP may extend to the upper surface280_US of the second active contact280.

The upper surface151VP_US of the first vertical portion151VP may be placed on the same plane as the upper surface160_US of the gate contact160, e.g., may be level with each other. The upper surface251VP_US of the second vertical portion251VP may be placed on the same plane as the upper surface280_US of the second active contact280, e.g., may be level with each other.

The gate contact160may be formed to penetrate through the first gate capping pattern150. The gate contact160may penetrate the first gate capping pattern150in the third direction Z. The gate contact160may penetrate the first gate capping pattern150and be connected to the first gate electrode120.

In some embodiments, at least a part of the gate contact160may overlap the first active contact180in the first direction X in terms of a plane. At least some of the gate contacts160may overlap the second active contact280in the first direction X in terms of a plane.

In terms of a cross-section, the lower surface160_BS of the gate contact160is higher than the upper surface180_US of the first active contact180. In terms of a cross-section, the lower surface160_BS of the gate contact160is lower than the upper surface280_US of the second active contact280. The upper surface160_US of the gate contact160may be located on the same plane as the upper surface180_US of the first active contact180.

FIG.5is a cross-sectional view of a semiconductor device according to some embodiments.FIG.6is an enlarged view of portion Q inFIG.5. For convenience of explanation, only features different from those described previously with reference toFIGS.1to4will be described in detail.

Referring toFIG.5, at least a part of the interlayer insulating film190may be placed on the first gate capping pattern150. At least a part of the interlayer insulating film190may be placed on the second gate capping pattern250. At least a part of the interlayer insulating film190may be placed on the third gate capping pattern350.

That is, at least a part of the interlayer insulating film190may overlap the first gate capping pattern150in the third direction Z. At least a part of the interlayer insulating film190may overlap the second gate capping pattern250in the third direction Z. At least a part of the interlayer insulating film190may overlap the third gate capping pattern350in the third direction Z.

In some embodiments, the first gate capping liner151may not extend to the upper surface160_US of the gate contact160. The second gate capping liner251may not extend to the upper surface280_US of the second active contact280.

Referring toFIG.6, the upper surface151VP_US of the first vertical portion151VP of the first gate capping liner151may be lower than the upper surface160_US of the gate contact160. That is, the gate contact160may protrude upward from, e.g., above, the upper surface151VP_US of the first vertical portion151VP. The upper surface151VP_US of the first vertical portion151VP is higher than the upper surface180_US of the first active contact180.

The second vertical portion251VP may include a second short vertical portion251VP_1and a second long vertical portion251VP_2. The second short vertical portion251VP_1and the second long vertical portion251VP_2may be spaced apart from each other in the first direction X. The second long vertical portion251VP_2may be placed between the second short vertical portion251VP_1and the side wall of the second active contact280.

The second short vertical portion251VP_1may not extend to the upper surface280_US of the second active contact280. That is, the upper surface251VP_1_US of the second short vertical portion251VP_1may be lower than the upper surface280_US of the second active contact280.

The second long vertical portion251VP_2may extend to the upper surface280_US of the second active contact280. That is, the upper surface251VP_2_US of the second long vertical portion251VP_2and the upper surface280_US of the second active contact280may be placed in the same plane, e.g., may be level with each other.

FIG.7is a cross-sectional view of a semiconductor device according to some embodiments corresponding to line A-A′ ofFIG.1.FIG.8is a cross-sectional view of a semiconductor device according to some embodiments corresponding to line B-B′ ofFIG.1. For convenience of explanation, only features different from those described previously with reference toFIGS.1to4will be mainly described.

Referring toFIGS.7and8, the first gate capping liner151, the second gate capping liner251, and the third gate capping liner351may each include multi-films. Since the second gate capping liner251and the third gate capping liner351may be substantially the same as the first gate capping liner151, only the first gate capping liner151will be described below.

The first gate capping liner151may include a first lower gate capping liner151L and a first upper gate capping liner151U. The first upper gate capping liner151U may be placed on the first lower gate capping liner151L.

Etching selectivity of the first lower gate capping liner151L and etching selectivity of the first upper gate capping liner151U may be different from each other. The first lower gate capping liner151L may include, e.g., at least one of aluminum oxide (AlO) and aluminum nitride (AlN). The second upper gate capping liner151U may include, e.g., silicon oxycarbide (SiOC). Although the first gate capping liner151is shown as a double film, the first gate capping liner151may include any suitable number of films, e.g., may be a triple film.

FIG.9is a cross-sectional view of a semiconductor device according to some embodiments corresponding to line A-A′ ofFIG.1.FIG.10is a cross-sectional view of a semiconductor device according to some embodiments corresponding to line A-A′ ofFIG.1. For convenience of explanation, only features different from those described previously with reference toFIGS.1to4will be mainly described.

Referring toFIG.9, in the semiconductor device according to some embodiments, the second active contact280may include a second lower active contact280aand a second upper active contact280b. The second lower active contact280amay include a second lower active barrier film281aand a second lower active filling film283a. The second upper active contact280bmay include a second upper active barrier film281band a second upper active filling film283b.

The upper surface280_US of the second active contact280may be an upper surface of the second upper active contact280b. The materials included in the second lower active barrier film281aand the second upper active barrier film281bmay be the same as the description of the materials included in the gate barrier film161. Contents of the materials included in the second lower active filling film283aand the second upper active filling film283bmay be the same as the description of the materials included in the gate filling film163.

Referring toFIG.10, the second upper active barrier film281bmay not extend along the side wall of the second upper active filling film283b. The second upper active barrier film281bmay be formed only on the lower surface of the second upper active filling film283b.

FIG.11is an exemplary layout diagram of a semiconductor device according to some embodiments.FIGS.12and13are exemplary cross-sectional views taken along line C-C′ ofFIG.11.FIG.14is an exemplary cross-sectional view taken along line D-D′ ofFIG.11.FIG.15is a diagram for explaining the semiconductor device according to some embodiments.FIG.16is a diagram for explaining the semiconductor device according to some embodiments. For convenience of explanation, only features different from those described previously with reference toFIGS.1to8will be mainly described.

Referring toFIGS.11to16, the first active pattern AP1of the semiconductor device according to some embodiments may include a lower pattern BP1and a sheet pattern UP1. Although not shown, the second active pattern AP2may include a lower pattern and a sheet pattern.

The sheet pattern UP1may include a plurality of sheet patterns stacked in the third direction Z. Although three sheet patterns UP1are shown, this is merely for convenience of explanation, and the number thereof is not limited thereto.

The sheet pattern UP1may be connected to the first epitaxial pattern170and the second epitaxial pattern270. The sheet pattern UP1may be a channel pattern used as the channel region of the transistor. For example, the sheet pattern UP1may be nanosheets or nanowires.

The first gate insulating film130may extend along the upper surface of the lower pattern BP1and the upper surface of the field insulating film105. The first gate insulating film130may wrap the periphery of the sheet pattern UP1. The second gate insulating film230may extend along the upper surface of the lower pattern BP1and the upper surface of the field insulating film105. The second gate insulating film230may wrap, e.g., surround, the periphery of the sheet pattern UP1. The third gate insulating film330may extend along the upper surface of the lower pattern BP1and the upper surface of the field insulating film105. The third gate insulating film330may wrap, e.g., surround, the periphery of the sheet pattern UP1.

InFIG.13, the first gate spacer140may include a first outer spacer141and a first inner spacer142. The first inner spacer142may be placed between the lower pattern BP1and the sheet pattern UP1, and between the adjacent sheet patterns UP1. The second gate spacer240may include a second outer spacer241and a second inner spacer242. The second inner spacer242may be placed between the lower pattern BP1and the sheet pattern UP1, and between the adjacent sheet patterns UP1. The third gate spacer340may include a third outer spacer341and a third inner spacer342. The third inner spacer342may be placed between the lower pattern BP1and the sheet pattern UP1, and between the adjacent sheet patterns UP1.

FIGS.17to34are cross-sectional views of stages in a method for fabricating the semiconductor device according to some embodiments.

Referring toFIG.17, the first epitaxial pattern170and the second epitaxial pattern270may be formed on the first active pattern AP1. First to third pre gate insulating films130P,230P and330P, first to third pre gate electrodes120P,220P and320P, first to third pre gate spacers140P,240P and340P, the first etching stop film176, the second etching stop film276, and the interlayer insulating film190may be formed on the first active pattern AP1.

The first etching stop film176may extend along the side walls of the first pre gate spacer140P, the upper surface of the first epitaxial pattern170, and the side walls of the second pre gate spacer240P. The second etching stop film276may extend along the side walls of the second pre gate spacer240P, the upper surface of the second epitaxial pattern270, and the side walls of the third pre gate spacer340P. The interlayer insulating film190may be formed on the first etching stop film176and the second etching stop film276.

Referring toFIG.18, a first gate capping trench150t, a second gate capping trench250t, and a third gate capping trench350tmay be formed. Although lower surfaces of the first to third gate capping trenches150t,250tand350tare shown to have a wavy shape, embodiments are not limited thereto, e.g., the lower surfaces of the first to third gate capping trenches150t,250tand350tmay have a flat shape.

Referring toFIG.19, a pre gate capping liner500may be formed along the profile of the first gate capping trench150t, the profile of the second gate capping trench250t, the profile of the third gate capping trench350t, and the upper surface of the interlayer insulating film190. The pre gate capping liner500may define first to third gate capping recesses150R,250R and350R.

The pre gate capping liner500may be formed conformally. The pre gate capping liner may be formed using, e.g., an atomic layer deposition (ALD) process. Contents of the material included in the pre gate capping liner500may be the same as the description of the material included in the first gate capping liner. Although the pre gate capping liner500is shown as a single film, embodiments area not limited thereto, e.g., the pre gate capping liner500may be a double film or a triple film.

Referring toFIG.20, a pre gate capping filling film600may be formed on the pre gate capping liner500. The pre gate capping filling film600may be formed to cover the upper surface of the pre gate capping liner500. The pre gate capping filling film600may fill the first gate capping recess150R, the second gate capping recess250R, and the third gate capping recess350R. The contents of the material included in the pre gate capping filling film600may be the same as the description of the material included in the first gate capping filling film.

Referring toFIG.21, the first gate capping pattern150, the second gate capping pattern250, and the third gate capping pattern350may be formed, by removing a part of the pre gate capping filling film600and a part of the pre gate capping liner500. The first gate capping pattern150includes the first gate capping liner151that defines the first gate capping recess150R, and the first gate capping filling film153that fills the first gate capping recess150R. The second gate capping pattern250and the third gate capping pattern350may be substantially the same as the first gate capping pattern150.

Referring toFIG.22, a mask film700may be formed on the first gate capping pattern150, the second gate capping pattern250, the third gate capping pattern350, and the interlayer insulating film190. The mask film700may be formed to cover the upper surfaces of the interlayer insulating film190, the first gate capping pattern150, the second gate capping pattern250, and the third gate capping pattern350. Although the mask film700may include, e.g., an oxide-based insulating material, embodiments are not limited thereto.

Referring toFIG.23, the first photoresist PR1may be formed on the mask film700. The first photoresist PR1may be used to form a first active contact and a second active contact, which will be described below.

Referring toFIG.24, a mask pattern700P, a first trench180t, and a second trench280tmay be formed, using the first photoresist PR1as a mask. The first trench180tmay be a trench for forming a first active contact. The second trench280tmay be a trench for forming a second active contact.

Referring toFIG.25, the first photoresist PR1may be removed. Subsequently, a pre active barrier film810may be formed along the profile of the first trench180t, the profile of the second trench280t, and the upper surface of the mask pattern700P. A first silicide film175may be formed at a portion in which the pre active barrier film810and the first epitaxial pattern170are in contact with each other. A second silicide film275may be formed at a portion in which the pre active barrier film810and the second epitaxial pattern270are in contact with each other.

A pre active filling film820that fills the first trench180tand the second trench280tmay be formed on the pre active barrier film810. Contents of the materials included in the pre active barrier film810and the pre active filling film820are the same as the description of the materials included in the first active barrier film and the first active filling film.

Referring toFIG.26, a pre first active contact180P and a second active contact280may be formed, by removing a part of the pre active barrier film810, a part of the pre active filling film820, and the mask pattern700P. The pre first active contact180P may include a pre first active barrier film181P and a pre first active filling film183P. The second active contact280may include a second active barrier film281and a second active filling film283.

Referring toFIG.27, a second photoresist PR2may be formed on the second active contact280. The second photoresist PR2may be formed to overlap the second active contact280in the third direction Z.

Referring toFIG.28, an interlayer insulating film trench195tmay be formed, by removing a part of the pre first active contact180P, using a second photoresist PR2as a mask. A first active contact180may be formed, by removing a part of the pre first active contact180P. In terms of a cross-section, the upper surface of the first active contact180is lower than the upper surface of the second active contact280.

Since the etching selectivity of the pre first active contact180P is different from the etching selectivity of the first gate capping pattern150, the second gate capping pattern250and the third gate capping pattern350, only the pre first active contact180P may be removed.

Referring toFIG.29, an interlayer insulating film195that fills the interlayer insulating film trench195tmay be formed. The interlayer insulating film195may include, but is not limited to, e.g., silicon oxycarbide (SiOC).

Referring toFIG.30, the third photoresist PR3may be formed on the second gate capping pattern250, the third gate capping pattern350, and the interlayer insulating films190and195. The third photoresist PR3may cover the upper surfaces of the second gate capping pattern250, the third gate capping pattern350, and the interlayer insulating films190and195. The third photoresist PR3may overlap the upper surfaces of the second gate capping pattern250, the third gate capping pattern350, and the interlayer insulating film190in the third direction Z. The third photoresist PR3may expose, e.g., only, a part of the upper surface of the first gate capping pattern150.

Referring toFIG.31, a gate contact trench160tmay be formed, using the third photoresist PR3as a mask. For example, as illustrated inFIG.31, the first gate capping pattern150may be etched through the opening in the third photoresist PR3to form the gate contact trench160tto a predetermined depth within the first gate capping pattern, e.g., a portion of the first gate capping filling film153may be removed to expose a portion of the upper surface of the first gate capping liner151. A lower surface of the gate contact trench160tmay be the same as the upper surface of the first gate capping liner151.

Referring toFIG.32, a part of the first gate capping liner151may be removed. The first gate capping liner151that overlaps the lower surface of the gate contact trench160tin the third direction Z may be removed. The first gate capping liner151may be removed, using a wet etching process. The gate contact trench160tmay expose the first gate electrode120, e.g., the portion of the first gate capping liner151exposed by the gate contact trench160tmay be completely removed by the wet etching to expose the gate electrode120. The lower surface of the gate contact trench160tmay be the same as the upper surface of the first gate electrode120.

Referring toFIG.33, a pre gate barrier film910extending along a profile of the gate contact trench160tand the upper surface of the third photoresist PR3may be formed. A pre gate filling film920may be formed on the pre gate barrier film910. The materials of the pre gate barrier film910and the pre gate filling film920are the same as those of the gate barrier film and the gate filling film.

Referring toFIG.34, the gate contact160may be formed, by removing a part of the pre gate barrier film910, and a part of the pre gate filling film920. The gate contact160may include the gate barrier film161and the gate filling film163.

By way of summation and review, as a pitch size of the semiconductor device decreases, a decrease in capacitance and increased electrical stability between contacts in the semiconductor device may be required. Therefore, aspects of the present disclosure provide a semiconductor device capable of improving device performance and reliability.

That is, embodiment are directed to a method of etching a metal gate to a desired height when forming a gate contact. More specifically, an etching stop layer is formed on the metal gate by forming a gate capping liner (e.g., ALN/ODC) on the metal gate, and a gate capping filling film (e.g., SiN) on the gate capping liner. As the gate capping filling film is etched by a dry etching process, and the gate capping liner is subsequently etched by a wet etching process, e.g., in two separate processes, portions of the gate capping filling film and the gate capping liner may remain between the gate contact (formed subsequently on the metal gate) and an adjacent contact.

Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.