Patent ID: 12204482

DETAILED DESCRIPTION

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a memory chiplet is disclosed. The memory chiplet includes a D2D interface of a first type for coupling to a host IC chip via multiple lanes. The D2D interface includes multiple unit interface modules, each of the multiple unit interface modules corresponding to a first set of signal path resources of a lowest granularity provided by the multiple lanes. A memory port includes a memory physical interface of a first memory type for accessing memory storage of the first memory type. The memory physical interface of the first memory type includes a second set of signal path resources corresponding to multiple memory channels of the first memory type. Mapping circuitry maps the second set of signal path resources to the first set of signal path resources in a manner that utilizes all of the signal path resources for an integer number of the multiple unit interface modules.

Throughout the disclosure provided herein, the term multi-chip module (MCM) is used to represent a semiconductor device that incorporates multiple semiconductor die or sub-packages in a single unitary package. An MCM may also be referred to as a system in a package (SiP). The die or sub-packages are referred to herein as chiplets. The die or sub-packages that are interconnected in an MCM or SiP are referred to herein as chiplets. Packaged die that are disposed external to an MCM or SiP, such as being mounted on a printed circuit board (PCB), are referred to herein as chips.

FIG.1illustrates one embodiment of an MCM, generally designated100, that employs a package substrate102for mounting a host integrated circuit (IC) chiplet104and a memory chiplet106. A die-to-die (D2D) interface circuit108provides a communications path and protocol between the host IC chiplet104and the memory chiplet106. For one embodiment, the D2D interface circuit108takes the form of a Universal Chiplet Interface Express (UCIe) circuit that employs a UCIe physical (PHY) signaling lane architecture and a UCIe-specified signaling protocol, herein referred to as a UCIe die-to-die (D2D) interface. In another embodiment, the D2D interface circuit108may employ a physical interface similar to the UCIe standard, but operating in accordance with a universal memory interface (UMI) packet-based protocol, herein referred to as a UMI die-to-die (D2D) interface. For some embodiments, use of the UCIe D2D interface or the UMI D2D interface as the interface circuit108may be selectable for corresponding UCIe or UMI modes of operation via the use of configurable mapping circuitry, described more fully below.

Further referring toFIG.1, the package substrate102may take a variety of forms, depending on the application. For some embodiments, the package substrate102may be realized as a “standard” package substrate, formed with an organic non-silicon material and incorporating a relatively sparse trace density appropriate for standard ball grid array (BGA) contact arrays (such as on the order of approximately one hundred to one hundred fifty microns). In other embodiments, the package substrate102may take the form of an “advanced” package substrate.

FIG.2illustrates one embodiment of the MCM100ofFIG.1with an advanced package substrate200. The advanced package substrate200includes a package substrate202that, for one embodiment, takes the form of a silicon interposer202disposed on a standard organic main substrate204. The host IC chiplet104and the memory chiplet106are mounted on the silicon interposer202. The silicon interposer202routes high-density signal paths, at206, that couple the chiplets together. In some embodiments, the silicon interposer202may be substituted with a silicon bridge-based structure that may be embedded or mounted to the standard main substrate204that provides a trace density on the order of approximately twenty-five to fifty-five microns.

Referring back toFIG.1, the host IC chiplet104generally includes processor circuitry110or other logic that performs operations on data, with the need to periodically carry out read and write data transfers with the memory chiplet106. The processor circuitry110may take the form of one or more processors such as a computer processing unit (CPU), graphics processing unit (GPU), tensor processing unit (TPU), artificial intelligence (AI) processing circuitry, field-programmable gate array (FPGA) circuitry or other form of host chiplet with a need to access memory.

Further referring toFIG.1, for situations where the UMI interface mode of operation is selected, the host IC chiplet104may include a communications fabric111for controlling communications on-chip, and for also controlling how the host IC chiplet104communicates off-chip with other chiplets, such as the memory chiplet106. For one embodiment, the communications fabric111includes network-on-chip (NoC) circuitry, such as that disclosed in U.S. patent application Ser. No. 18/528,702, filed Dec. 4, 2023, titled: “UNIVERSAL NETWORK-ATTACHED MEMORY ARCHITECTURE”, owned by the assignee of the instant application and expressly incorporated herein by reference.

With continued reference toFIG.1, the host IC chiplet104includes a host interface sub-circuit112of the overall D2D interface circuit108. Consistent with the various embodiments for the D2D interface circuit108, the host interface sub-circuit112may take the form of a standardized UCIe D2D interface, or a UMI interface. Further detail for one embodiment of a UMI interface is described in copending U.S. patent application Ser. No. 18/652,675, filed May 1, 2024, titled “UNIVERSAL MEMORY INTERFACE”, owned by the assignee of the instant application and expressly incorporated herein by reference.

Further referring toFIG.1, the host interface sub-circuit112includes host input/output (I/O) circuitry114and host mapping circuitry116. For embodiments utilizing a UCIe-based lane infrastructure, the host I/O circuitry114may be organized into unit interface modules, described more fully below with respect to the memory chiplet106. The host mapping circuitry116generally maps an on-chip processor interface (not shown) of the processor circuitry110to the UCIe unit interface modules of the host I/O circuitry114.

Further referring toFIG.1, for one embodiment, the memory IC chiplet106includes a memory-centric interface118for accessing memory of a specific standard or type, such as high-bandwidth memory (HBM), double-data rate (DDR) memory, low-power double data rate (LPDDR), graphics double data rate (GDDR), to name but a few. For some embodiments, memory control circuitry120may be positioned on the memory chiplet106rather than the host IC chiplet104. Positioning the memory control circuitry120on the memory chiplet106removes the need for the host IC chiplet104(often a costly application-specific integrated circuit) to know the type of memory being accessed, thereby allowing the host IC chiplet104the freedom to interact with a variety of memory types, and not constrained to one type of memory type associated with a specific on-chip memory controller.

For one embodiment, the memory chiplet106includes a second portion of the overall D2D interface108, referred to herein as a memory interface sub-circuit122. For one embodiment, the memory interface subcircuit122includes a D2D input/output (I/O) portion119that matches the host D2D unit interface circuitry114, such as a standardized UCIe I/O configuration, or a UMI I/O configuration. A converter portion of the memory interface subcircuit122takes the form of mapping circuitry124that maps signals from the memory-centric interface circuitry118to the D2D I/O portion119of the memory interface subcircuit122. Further details regarding various embodiments of the mapping circuitry124are set out below. To provide for user configurability, in some embodiments, register storage126may be provided on the memory chiplet106to store configurable parameters, such as one or more D2D interface modes for the memory chiplet106, among other things.

For some embodiments, the memory chiplet106may take the form of a single-die chiplet that includes the memory control circuitry120and the features of the memory interface sub-circuit122. The single-die chiplet may then be employed as a base die upon which are stacked memory die130for a stacked memory implementation, such as for HBM. Other embodiments may employ the single die as a buffer or intermediary between the IC chiplet104and memory die disposed proximate the single die on the package substrate102or off-MCM (not shown).

For one embodiment, the host interface subcircuit112of the host IC chiplet104connects to the memory interface subcircuit122of the memory chiplet106via multiple lanes132. For a UCIe-based D2D interface embodiment, the multiple lanes132may be configured in accordance with a standardized UCIe unit interface or module architecture. A unit interface module generally corresponds to a lowest granularity of lanes to support a given interface width. One such example is an interface width of sixty-four data lanes, referred to as x64, which includes sixty-four data lanes along with supporting clock and control lanes.

FIG.3Aillustrates one embodiment of a UCIe unit interface, generally designated300disposed between chiplets302and304. The UCIe unit interface includes a first fixed set of unidirectional data lanes306for transmitting data and associated clock and control lanes in a first direction, and a second set of unidirectional lanes308for receiving data in a second direction opposite the first direction, and a variety of control and clock lanes associated with the received data. Sideband links310may also be included in the UCIe unit interface architecture. For applications involving, for example, HBM memory, where as many as thirty-two or more memory channels may be employed, a plurality of UCIe unit interface modules300are employed, such as unit interface A (FIG.1), unit interface B, and so on to the extent that all thirty-two channels are supported.

FIG.3Billustrates a UMI-based D2D unknit interface architecture312, where the multiple lanes132(FIG.1) may be configured in accordance with a dynamic bidirectional lane architecture such as that disclosed in copending U.S. patent application Ser. No. 18/652,707, filed May 1, 2024, titled “UNIVERSAL MEMORY INTERFACE WITH DYNAMIC BIDIRECTIONAL DATA TRANSFERS”, owned by the assignee of the instant application and expressly incorporated herein by reference. For one embodiment, the UMI unit interface architecture312includes a set of N bidirectional data lanes314, at least one egress lane316, at least one ingress lane318and a sideband link320. For one embodiment, described more fully below, UCIe modules may be reconfigured such that groups of opposing unidirectional lanes are used to mimic the operation of bidirectional lanes.

Generally, from the perspective of the host IC chiplet104, one specific version of the UMI lane architecture partitions the set of bidirectional lanes312into a first sub-set of switchable bidirectional data lanes for transferring first data in a first selected direction, and a second sub-set of the bidirectional lanes for transferring second data in the same or opposite direction. The UMI interface is configured with memory transactions in mind to employ and utilize memory-centric features and functionality, thereby reducing latency and power consumption that might otherwise result from use of a generic D2D interface, such as UCIe, designed for a wide range of applications.

Use of the UCIe D2D interface300or the UMI D2D interface312to transfer signals between the chiplets104and106provides significant silicon area and power consumption benefits over previously proposed chiplet interconnect alternatives. In using either D2D interface architecture, signals traversing over the D2D interface signaling paths eventually must originate or end at the memory interface circuitry118on the memory chiplet106. In an effort to more efficiently organize the D2D unit interface usage for minimum area and power usage, the memory mapping circuitry124maps the memory-centric signals between the memory interface circuitry118and the plurality of unit interface units or modules119to minimize the number of active modules, thus reducing power consumption and potentially the chiplet beachfront area.

FIG.4illustrates two tables of signals for mapping an HBM interface onto a x64 UCIe unit interface module that may be used for advanced packaging applications. At400, a first table of signals, labeled HBM SIGNALS, identifies signal paths used by the memory-centric interface circuitry118that correspond to one HBM memory channel of an HBM memory device architecture. Operating at a data rate of up to 8 Gbps, and generally described above, the number of signals amounts to one-hundred-twenty, at402, including data (64 signals), at404, parity bits (6), at406, address bits (18), at408, and a variety of other control, clocking-related, and redundancy-related bits (32), at410.

Further referring toFIG.4, at412, a second table of signals, labeled UCIe SIGNALS, identifies a mapping of the number of UCIe paths to support the single channel of HBM memory. For one embodiment, certain signal paths used in a memory-specific interface, such as column and row address paths, DBI, APAR and others, may be omitted, which allows for reducing the number of signaling paths from one-hundred twenty to eighty-four, at414.

FIG.5illustrates a high-level organization of I/Os represented by two UCIe unit interface modules, at502and504, each unit interface module representing the unit lane architecture ofFIG.3A. For one embodiment, a single bidirectional channel of HBM may be mapped to one-half of the first UCIe unit interface module502, at506, along with ⅛ of the second UCIe unit interface module504, distributed at508and510. For one embodiment, the HBM data lanes are mapped to the first module502, with supporting address, control and other related signals (such as ECC, DERR, AERR, APAR) for the channel mapped as a remainder portion to the second module504.

FIG.6illustrates how the module mapping ofFIG.5scales to eight HBM channels, CH1through CH8, which are mapped over five UCIe unit interface modules512,514,516,518and520. Since each HBM channel mapping involves a remainder portion of ⅛ of one module, for one embodiment, the middle module516includes the remainder portions from channels CH1-CH8mapped to the four other modules512,514,518and520. Mapping eight HBM channels to five UCIe unit interface modules enables a full complement of thirty-two HBM channels to be mapped to twenty UCIe unit interface modules. With advanced packaging contact bump pitch dimensions on the order of forty-five to fifty-five micrometers, minimizing the number of UCIe modules allows for all thirty-two channels to be accessible via a single chiplet edge. Additionally, fully packing the modules eliminates any unnecessary power consumption from underutilized partial modules.

FIG.7illustrates two tables of signals for mapping HBM onto multiple UCIe unit interface modules, but repurposing the unidirectional UCIe lanes into bidirectional data lanes and the support lanes shown inFIG.3B. This may be accomplished by configuring (with supporting I/O circuitry) the UCIe unidirectional lanes and associated contact bumps to mimic the functionality of bidirectional lanes and bumps. At700, a first table of signals, labeled HBM SIGNALS, identifies the signal paths used by the memory-centric interface circuitry118that correspond to one HBM memory channel of an HBM memory device architecture. This table was previously presented inFIG.4, but reproduced here for ease of comparison to the UMI signals, which are presented in the second table704, labeled UMI SIGNALS. Of note is the significant reduction in signal count using the UMI unit interface, from eighty-four to fifty-two signals, shown at706. A corresponding UCIe module mapping for eight HBM channels using the UMI unit architecture mapped onto UCIe is shown inFIG.8. Like the earlier UCIe mapping, the UMI mapping may be spread out over five UCIe modules, at802,804,806,808, and810, but with half the data lanes of each module, resulting in approximately half the area usage at the beachfront edge of the memory chiplet106, where the electrical connections between the memory chiplet106and the package substrate102are made.

For one embodiment, instead of mapping the eight HBM channels to five modules, three fully-packed modules may be mapped, reducing the number of active modules by forty percent.FIG.9illustrates one embodiment of such a mapping, with modules902and904mapped for data lanes, and module906mapped for partial module portions.

In some situations, mapping from the HBM interface to the UCIe PHY infrastructure using a UMI-based architecture may be avoided by providing a UMI PHY that is optimized for use in memory applications. In such an embodiment, involving mapping bidirectional HBM signals to bidirectional UMI lanes, further efficiencies in power and bandwidth are possible.

For one embodiment, the memory mapping circuitry124is configurable to allow for a selection between mappings for multiple D2D PHY architectures.FIG.10illustrates a potential module mapping that supports the use of both UCIe and UMI with the UCIe advanced package unit interface module structures. The entire resources of five modules1002,1004,1006,1008and1010support a UCIe D2D configuration, while half the modules1002,1004,1008, and1010are used to support the UMI data lane configuration. The middle module, at1006, supports partial mappings for the four other modules in order to minimize the number of modules employed. Selections between one D2D configuration or another may be made, for example, through loading and storing a selectable value in the register circuitry126of the memory chiplet106.

When received within a computer system via one or more computer-readable media, such data and/or instruction-based expressions of the above described circuits may be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with execution of one or more other computer programs including, without limitation, net-list generation programs, place and route programs and the like, to generate a representation or image of a physical manifestation of such circuits. Such representation or image may thereafter be used in device fabrication, for example, by enabling generation of one or more masks that are used to form various components of the circuits in a device fabrication process.

In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols have been set forth to provide a thorough understanding of the present disclosure. In some instances, the terminology and symbols may imply specific details that are not required to practice aspects of the disclosure. For example, any of the specific numbers of bits, signal path widths, signaling or operating frequencies, component circuits or devices and the like may be different from those described above in alternative embodiments. Also, the interconnection between circuit elements or circuit blocks shown or described as multi-conductor signal links may alternatively be single-conductor signal links, and single conductor signal links may alternatively be multi-conductor signal links. Signals and signaling paths shown or described as being single-ended may also be differential, and vice-versa. Similarly, signals described or depicted as having active-high or active-low logic levels may have opposite logic levels in alternative embodiments. Component circuitry within integrated circuit devices may be implemented using metal oxide semiconductor (MOS) technology, bipolar technology or any other technology in which logical and analog circuits may be implemented. With respect to terminology, a signal is said to be “asserted” when the signal is driven to a low or high logic state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition. Conversely, a signal is said to be “deasserted” to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating state that may occur when the signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition). A signal driving circuit is said to “output” a signal to a signal receiving circuit when the signal driving circuit asserts (or deasserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits. A signal line is said to be “activated” when a signal is asserted on the signal line, and “deactivated” when the signal is deasserted. Additionally, the prefix symbol “/” attached to signal names indicates that the signal is an active low signal (i.e., the asserted state is a logic low state). A line over a signal name (e.g., ‘<signal name>’) is also used to indicate an active low signal. The term “coupled” is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures. Integrated circuit device “programming” may include, for example and without limitation, loading a control value into a register or other storage circuit within the device in response to a host instruction and thus controlling an operational aspect of the device, establishing a device configuration or controlling an operational aspect of the device through a one-time programming operation (e.g., blowing fuses within a configuration circuit during device production), and/or connecting one or more selected pins or other contact structures of the device to reference voltage lines (also referred to as strapping) to establish a particular device configuration or operation aspect of the device. The term “exemplary” is used to express an example, not a preference or requirement.

While aspects of the disclosure herein have been described with reference to specific embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the disclosure. For example, features or aspects of any of the embodiments may be applied, at least where practicable, in combination with any other of the embodiments or in place of counterpart features or aspects thereof. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.