Patent ID: 12223922

DETAILED DESCRIPTION

Aspects (embodiments) of the present disclosure will be described below in detail with reference to the accompanying drawings. Contents described below in the embodiments do not limit the present disclosure.

Constituent components described below include those that could be easily thought of by the skilled person in the art and those identical in effect. Constituent components described below may be combined as appropriate. What is disclosed herein is merely exemplary, and any modification that could be easily thought of by the skilled person in the art as appropriate without departing from the gist of the present disclosure is contained in the scope of the present disclosure. For clearer description, the drawings are schematically illustrated for the width, thickness, shape, and the like of each component as compared to an actual aspect in some cases, but the drawings are merely exemplary and do not limit interpretation of the present disclosure. In the present disclosure and the drawings, any component same as that already described with reference to an already described drawing is denoted by the same reference sign, and detailed description thereof is omitted as appropriate in some cases.

In the present specification and the claims, an expression with “on” in description of an aspect in which one structural body is disposed on another structural body includes both a case in which the one structural body is directly disposed on the other structural body in contact and a case in which the one structural body is disposed above the other structural body with still another structural body interposed therebetween, unless otherwise stated in particular.

First Embodiment

FIG.1is a configuration diagram illustrating an exemplary display system according to a first embodiment. In the present embodiment, a display system1is a display system configured to change display in accordance with motion of a user. For example, the display system1is a VR system configured to provide virtual reality to the user by stereoscopically displaying a VR image illustrating a three-dimensional object or the like in a virtual space and changing the stereoscopic display in accordance with the orientation (position) of the head of the user.

As illustrated inFIG.1, the display system1includes, for example, a display device100and a control device200. The display device100and the control device200have a configuration in which information (signal) can be input and output through a cable300. Examples of the cable300include a universal serial bus (USB) cable and a high-definition multimedia interface (HDMI) (registered trademark) cable. The display device100and the control device200may have a configuration in which information can be input and output through wireless communication.

The display device100includes a display panel. The display panel is, for example, a liquid crystal display but may be an organic electro-luminescence (organic EL) panel, a μ-OLED, a μ-LED panel, a mini-LED panel, or the like.

The display device100is fixed to a mounting member400. Examples of the mounting member400include a head set, goggles, and a helmet and a mask that cover the eyes of the user. The mounting member400is mounted on the head of the user. When mounted, the mounting member400is disposed in front of the user to cover the eyes of the user. The mounting member400functions as an immersive mounting member by positioning the display device100fixed therein in front of the eyes of the user. The mounting member400may include an output unit configured to output, for example, a sound signal output from the control device200. Alternatively, the mounting member400may have a structure with built-in functions of the control device200.

In the example illustrated inFIG.1, the display device100is slotted into the mounting member400but may be fixed to the mounting member400. In other words, the display system1may be constituted by a mounting display device and the control device200, the mounting display device including the mounting member400and the display device100.

FIG.2is a schematic diagram illustrating an exemplary relative relation between the display device and an eye of the user. As illustrated inFIG.2, the mounting member400includes, for example, a lens410corresponding to each eye of the user. The lens410is a magnifying lens for imaging an image on the eye of the user. When mounted on the head of the user, the mounting member400positions the lens410in front of an eye E of the user. The user visually recognizes a display region of the display device100, which is magnified through the lens410. Thus, the resolution of the display device100needs to be increased to clearly display an image (screen). Although one lens410is exemplarily described in the present disclosure, for example, a plurality of lenses410may be provided and the display device100may be disposed at a position different from in front of eyes.

The control device200causes the display device100to display, for example, an image. The control device200may be an electronic apparatus such as a personal computer or a gaming apparatus. Examples of a virtual image include a computer graphic video and a 360 degree live video. The control device200outputs, to the display device100, a three-dimensional image exploiting the parallax between the eyes of the user. The control device200outputs, to the display device100, right-eye and left-eye images that follow the orientation of the head of the user.

FIG.3is a block diagram illustrating an exemplary configuration of the display system according to the first embodiment. As illustrated inFIG.3, the display device100includes two display panels110, a sensor120, an image separation circuit150, and an interface160.

One of the two display panels110included in the display device100is used as a left-eye display panel110, and the other display panel110is used as a right-eye display panel110.

Each of the two display panels110includes a display region111and a display control circuit112. Each display panel110includes a non-illustrated light source device (backlight IL to be described later) configured to irradiate the display region111from back.

The display region111includes a two-dimensional matrix (with a row-column configuration) of P0×Q0pixels Pix (P0pixels in the row direction and Q0pixels in the column direction). In the present embodiment, P0is 2880 and Q0is 1700. The row direction corresponds to a first direction Dx, and the column direction corresponds to a second direction Dy.FIG.3schematically illustrates an arrangement of the pixels Pix, and detailed arrangement of the pixels Pix will be described later.

The display panels110includes scanning lines GL extending in the first direction Dx and signal lines SL extending in the second direction Dy intersecting the first direction Dx. For example, the display panels110includes 2880 signal lines SL and 1700 scanning lines GL. In the display panels110, the pixels Pix are disposed in regions surrounded by the signal lines SL and the scanning lines GL. Each pixel Pix includes a switching element (thin film transistor (TFT)) coupled to the signal line SL and the scanning line GL, and a pixel electrode coupled to the switching element. Each scanning line GL is coupled to the pixels Pix disposed in the direction in which the scanning line GL extends. Each signal line SL is coupled to the pixels Pix disposed in the direction in which the signal line SL extends.

In the following description, the first direction Dx is an in-plane direction parallel to the surface of a first substrate10(refer toFIG.6). The second direction Dy is an in-plane direction parallel to the surface of the first substrate10and orthogonal to the first direction Dx. The second direction Dy may intersect the first direction Dx instead of being orthogonal. A third direction Dz is orthogonal to the first direction Dx and the second direction Dy. The third direction Dz is the normal direction of the surface of the first substrate10. A “plan view” illustrates a positional relation when viewed in a direction orthogonal to the surface of the first substrate10.

The display region111of one of the two display panels110is for the right eye, and the display region111of the other display panel110is for the left eye. In description of the first embodiment, the display panels110include the two display panels110for the left and right eyes. However, the display device100is not limited to a structure including the two display panels110as described above. For example, one display panel110may be provided and the display region111of the display panel110may be divided into two so that a right-eye image is displayed in the right half region and a left-eye image is displayed in the left half region.

The display control circuit112includes a driver integrated circuit (IC)115, a signal line coupling circuit113, and a scanning line drive circuit114. The signal line coupling circuit113is electrically coupled to the signal lines SL. The driver IC115controls, through the scanning line drive circuit114, on and off of a switching element (for example, TFT) for controlling operation (light transmittance) of the pixels Pix. The scanning line drive circuit114is electrically coupled to the scanning lines GL.

The sensor120detects information based on which the orientation of the head of the user can be estimated. For example, the sensor120detects information indicating motion of the display device100and the mounting member400, and the display system1estimates the orientation of the head of the user on which the display device100is mounted based on the information indicating motion of the display device100and the mounting member400.

The sensor120detects information based on which the orientation of the line of sight can be estimated by using, for example, at least one of the angles, accelerations, angular velocities, orientations, and distances of the display device100and the mounting member400. The sensor120may use, for example, a gyro sensor, an acceleration sensor, or an orientation sensor. For example, the sensor120may detect the angles and angular velocities of the display device100and the mounting member400by using the gyro sensor. For example, the sensor120may detect the direction and magnitude of acceleration applied to the display device100and the mounting member400by using the acceleration sensor.

For example, the sensor120may detect the orientation of the display device100by using the orientation sensor. For example, the sensor120may detect movement of the display device100and the mounting member400by using a distance sensor, a global positioning system (GPS) receiver, or the like. The sensor120may be any other sensor such as an optical sensor for detecting the orientation of the head of the user, change of the line of sight, movement, or the like and may be a combination of a plurality of sensors. The sensor120is electrically coupled to the image separation circuit150through the interface160to be described later.

The image separation circuit150receives left-eye image data and right-eye image data fed from the control device200through the cable300, feeds the left-eye image data to the display panel110configured to display a left-eye image, and feeds the right-eye image data to the display panel110configured to display a right-eye image. The interface160includes a connector to which the cable300(FIG.1) is coupled. A signal from the control device200is input to the interface160through the coupled cable300. The image separation circuit150outputs a signal input from the sensor120to the control device200through the interface160and an interface240. The signal input from the sensor120includes the above-described information based on which the orientation of the line of sight can be estimated. Alternatively, the signal input from the sensor120may be directly output to a controller230of the control device200through the interface160. The interface160may be, for example, a wireless communication device and may transmit and receive information to and from the control device200through wireless communication.

The control device200includes an operation portion210, a storage220, the controller230, and the interface240.

The operation portion210receives an operation from the user. The operation portion210may be, for example, an input device such as a keyboard, a button, or a touch screen. The operation portion210is electrically coupled to the controller230. The operation portion210outputs information in accordance with the operation to the controller230.

The storage220stores computer programs and data. The storage220temporarily stores results of processing by the controller230. The storage220includes a storage medium. Examples of the storage medium include a ROM, a RAM, a memory card, an optical disk, and a magneto optical disc. The storage220may store data of images to be displayed on the display device100.

The storage220stores, for example, a control program211and a VR application212. The control program211can provide, for example, functions related to various kinds of control for operating the control device200. The VR application212can provide a function to cause the display device100to display a virtual reality image. The storage220can store various kinds of information input from the display device100, such as data indicating results of detection by the sensor120.

The controller230includes, for example, a micro control unit (MCU) or a central processing unit (CPU). The controller230can collectively control operation of the control device200. Various kinds of functions of the controller230are achieved based on control by the controller230.

The controller230includes, for example, a graphics processing unit (GPU) configured to generate images to be displayed. The GPU generates an image to be displayed on the display device100. The controller230outputs the image generated by the GPU to the display device100through the interface240. The controller230of the control device200includes the GPU in description of the present embodiment but is not limited thereto. For example, the GPU may be provided in the display device100or the image separation circuit150of the display device100. In this case, the display device100may acquire data from the control device200, an external electronic apparatus, or the like, and the GPU may generate an image based on the data.

The interface240includes a connector to which the cable300(refer toFIG.1) is coupled. A signal from the display device100is input to the interface240through the cable300. The interface240outputs the signal input from the controller230to the display device100through the cable300. The interface240may be, for example, a wireless communication device and may transmit and receive information to and from the display device100through wireless communication.

When the VR application212is executed, the controller230causes the display device100to display an image in accordance with motion of the user (display device100). When having detected change of the user (display device100) while causing the display device100to display the image, the controller230changes the image displayed on the display device100to an image in the direction of the change. At start of image production, the controller230produces an image based on a reference viewpoint and a reference line of sight in a virtual space, and when having detected change of the user (display device100), changes a viewpoint or line of sight for producing a displayed image from the direction of the reference viewpoint or the reference line of sight in accordance with motion of the user (display device100), and causes the display device100to display an image based on the changed viewpoint or line of sight.

For example, the controller230detects rightward movement of the head of the user based on a result of detection by the sensor120. In this case, the controller230changes a currently displayed image to an image when the line of sight is changed in the right direction. Accordingly, the user can visually recognize an image in the right direction of the image displayed on the display device100.

For example, when having detected movement of the display device100based on a result of detection by the sensor120, the controller230changes an image in accordance with the detected movement. When having detected frontward movement of the display device100, the controller230changes the currently displayed image to an image in a case of movement to the front side of the currently displayed image. When having detected backward movement of the display device100, the controller230changes the currently displayed image to an image in a case of movement to the back side of the currently displayed image. The user can visually recognize an image in a direction in which the user moves from an image displayed on the display device100.

FIG.4is a circuit diagram illustrating pixel arrangement of the display region according to the first embodiment. Hereinafter, the scanning lines GL described above collectively refer to a plurality of scanning lines G1, G2, and G3. The signal lines SL described above collectively refer to a plurality of signal lines S1, S2, and S3. In the example illustrated inFIG.4, the scanning lines GL are orthogonal to the signal lines SL, but the present disclosure is not limited thereto. For example, the scanning lines GL do not necessarily need to be orthogonal to the signal lines SL.

As illustrated inFIG.4, for example, switching elements TrD1, TrD2, and TrD3of pixels PixR, PixG, and PixB, the signal lines SL, and the scanning lines GL are formed in the display region111. The signal lines S1, S2, and S3are wires for supplying pixel signals to pixel electrodes PE1, PE2, and PE3(refer toFIG.6). The scanning lines G1, G2, and G3are wires for supplying gate signals that drive the switching elements TrD1, TrD2, and TrD3.

The pixels Pix in the display region111include the arrayed pixels PixR, PixG, and PixB. Hereinafter, the pixels PixR, PixG, and PixB are collectively referred to as pixels Pix in some cases. The pixels PixR, PixG, and PixB include the respective switching elements TrD1, TrD2, and TrD3and capacitors of a liquid crystal layer LC. The switching elements TrD1, TrD2, and TrD3are each constituted by a thin film transistor and, in this example, constituted by an n-channel metal oxide semiconductor (MOS) TFT. A sixth insulating film16(refer toFIG.6) is provided between the pixel electrodes PE1, PE2, and PE3and a common electrode COM to be described later, and holding capacitors Cs illustrated inFIG.4are formed by these components.

Color filters CFR, CFG, and CFB illustrated inFIG.4correspond to periodically arrayed color regions colored in, for example, three colors of red (R; first color), green (G; second color), and blue (B; third color). The above-described pixels PixR, PixG, and PixB illustrated inFIG.4are associated with a set of color regions in the three colors of R, G, and B. The pixels PixR, PixG, and PixB corresponding to the color regions in the three colors are grouped as a set. The color filters may include color regions in four or more colors. The pixels PixR, PixG, and PixB are each called a sub pixel in some cases.

FIG.5is a schematic diagram illustrating an exemplary display panel according to the first embodiment. InFIG.5, some of the signal lines are omitted for clearer appearance of the drawing.

As illustrated inFIG.5, the display region111of each display panel110has a polygonal shape in a plan view. More specifically, the display region111has an octagonal shape with a first side e1, a second side e2, a third side e3, a fourth side e4, a first tilted side ea1, a second tilted side ea2, a third tilted side ea3, and a fourth tilted side ea4. A region between a substrate end part of the first substrate10of the display panel110and each side of the display region111is called a peripheral region.

The first side e1is positioned on the right side on the outer periphery of the display region111and extends in the second direction Dy. The second side e2is positioned on a side opposite the first side e1, in other words, on the left side on the outer periphery of the display region111and extends in the second direction Dy. The third side e3is positioned on the upper side on the outer periphery of the display region111and extends in the first direction Dx. The fourth side e4is positioned on a side opposite the third side e3, in other words, on the lower side on the outer periphery of the display region111and extends in the first direction Dx.

A plurality of signal lines SL provided in regions corresponding to the third side e3and the fourth side e4have equal lengths in the second direction Dy. A plurality of scanning lines GL provided in regions corresponding to the first side e1and the second side e2have equal lengths in the first direction Dx.

The first tilted side ea1is a side between the first side e1and the third side e3and is coupled to one end side (upper end side inFIG.5) of the first side e1and tilted in the second direction Dy. The second tilted side ea2is a side between the first side e1and the fourth side e4and is coupled to the other end side (lower end side inFIG.5) of the first side e1and tilted in the second direction Dy. The third tilted side ea3is a side between the second side e2and the third side e3and is coupled to one end side of the second side e2and tilted in the second direction Dy. The fourth tilted side ea4is a side between the second side e2and the fourth side e4and is coupled to the other end side of the second side e2and tilted in the second direction Dy.

In the present embodiment, the first tilted side ea1and the second tilted side ea2are provided in a line symmetric manner with the axis of symmetry at a virtual line parallel to the first direction Dx through the middle point of the first side e1. The lengths of the signal lines SL provided in regions corresponding to the first tilted side ea1and the second tilted side ea2in the second direction Dy are shorter than the lengths of the signal lines SL provided in the regions corresponding to the third side e3and the fourth side e4in the second direction Dy. The lengths of the signal lines SL provided in the regions corresponding to the first tilted side ea1and the second tilted side ea2in the second direction Dy decrease as separation from the right ends of the third side e3and the fourth side e4in the first direction Dx increases (in other words, as separation from the first side e1decreases).

The third tilted side ea3and the fourth tilted side ea4are provided in a line symmetric manner with the axis of symmetry at a virtual line parallel to the first direction Dx through the middle point of the second side e2. The lengths of the signal lines SL provided in regions corresponding to the third tilted side ea3and the fourth tilted side ea4in the second direction Dy are shorter than the lengths of the signal lines SL provided in the regions corresponding to the third side e3and the fourth side e4in the second direction Dy. The lengths of the signal lines SL provided in the regions corresponding to the third tilted side ea3and the fourth tilted side ea4in the second direction Dy decrease as separation from the left ends of the third side e3and the fourth side e4in the first direction Dx increases (in other words, as separation from the second side e2decreases).

The first tilted side ea1and the third tilted side ea3are provided in a line symmetric manner with the axis of symmetry at a virtual line parallel to the second direction Dy through the middle point of the third side e3. The lengths of the scanning lines GL provided in regions corresponding to the first tilted side ea1and the third tilted side ea3in the first direction Dx are shorter than the lengths of the scanning lines GL provided in the regions corresponding to the first side e1and the second side e2in the first direction Dx. The lengths of the scanning lines GL provided in each of the regions corresponding to the first tilted side ea1and the third tilted side ea3in the first direction Dx decrease as separation from one end of the corresponding one of the first side e1and the second side e2in a direction along the first tilted side ea1or the third tilted side ea3increases (in other words, as separation from the third side e3decreases).

The second tilted side ea2and the fourth tilted side ea4are provided in a line symmetric manner with the axis of symmetry at a virtual line parallel to the second direction Dy through the middle point of the fourth side e4. The lengths of the scanning lines GL provided in regions corresponding to the second tilted side ea2and the fourth tilted side ea4in the first direction Dx are shorter than the lengths of the scanning lines GL provided in the regions corresponding to the first side e1and the second side e2in the first direction Dx. The lengths of the scanning lines GL provided in each of the regions corresponding to the second tilted side ea2and the fourth tilted side ea4in the first direction Dx decrease as separation from the other end of the corresponding one of the first side e1and the second side e2in a direction along the second tilted side ea2or the fourth tilted side ea4increases (in other words, as separation from the fourth side e4decreases).

A scanning line drive circuit114A is disposed in the peripheral region between the substrate end part of the first substrate10of the display panel110and each of the first tilted side ea1, the first side e1, and the second tilted side ea2of the display region111. More specifically, the scanning line drive circuit114A includes a first circuit portion31provided along the first side e1, a second circuit portion32provided along the first tilted side ea1, and a third circuit portion33provided along the second tilted side ea2.

A scanning line drive circuit114B is positioned on a side opposite the scanning line drive circuit114A and disposed in the peripheral region between the substrate end part of the first substrate10of the display panel110and each of the second tilted side ea2, the second side e2, and the fourth tilted side ea4of the display region111. More specifically, the scanning line drive circuit114B includes a fourth circuit portion34provided along the second side e2, a fifth circuit portion35provided along the third tilted side ea3, and a sixth circuit portion36provided along the fourth tilted side ea4. The right end sides of the scanning lines GL are electrically coupled to the scanning line drive circuit114A, and the left end sides of the scanning lines GL are electrically coupled to the scanning line drive circuit114B.

The signal line coupling circuit113is disposed in the peripheral region between the substrate end part of the first substrate10of the display panel110and the fourth side e4of the display region111. The signal line coupling circuit113is electrically coupled the signal lines SL. The driver IC115is disposed in the peripheral region between the substrate end part of the first substrate10of the display panel110and the fourth side e4of the display region111. The driver IC115is a circuit configured to control the scanning line drive circuits114A and114B and the signal line coupling circuit113.

In the example illustrated inFIG.5, the signal lines SL are arrayed alongside each other in the first direction Dx and extend in parallel to the second direction Dy. The scanning lines GL extend in parallel to the direction (first direction Dx) intersecting the signal lines SL. Since the direction in which the scanning lines GL extend is orthogonal to the direction in which the signal lines SL extend, for example, the pixels PixR, PixG, and PixB (refer toFIG.7) have rectangular shapes. However, the pixels PixR, PixG, and PixB are not limited to rectangular shapes.

The pixels PixR, PixG, and PixB may have, for example, parallelogram shapes. The pixels PixR, PixG, and PixB are referred to as pixels PixS in some cases.

The following describes a sectional structure of each display panel110with reference toFIG.6.FIG.6is a sectional view schematically illustrating a section of each display panel according to the first embodiment. InFIG.6, an array substrate SUB1is based on the translucent first substrate10such as a glass substrate or a resin substrate. The array substrate SUB1includes, on a side on which the first substrate10faces a counter substrate SUB2, a first insulating film11, a second insulating film12, a third insulating film13, a fourth insulating film14, a fifth insulating film15, the sixth insulating film16, the signal lines S1to S3, the pixel electrodes PE1to PE3, the common electrode COM, a first alignment film AL1, and the like. In the following description, the direction from the array substrate SUB1toward the counter substrate SUB2is referred to as upward or up.

The first insulating film11is positioned on the upper side of the first substrate10. The second insulating film12is positioned on the upper side of the first insulating film11. The third insulating film13is positioned on the upper side of the second insulating film12. The signal lines S1to S3are positioned on the upper side of the third insulating film13. The fourth insulating film14positioned on the upper side of the third insulating film13and covers the signal lines S1to S3.

Wires may be disposed on the upper side of the fourth insulating film14as necessary. The wires are covered by the fifth insulating film15. The wires are omitted in the present embodiment. The first insulating film11, the second insulating film12, the third insulating film13, and the sixth insulating film16are formed of a translucent inorganic material such as silicon oxide or silicon nitride. The fourth insulating film14and the fifth insulating film15are formed of a translucent resin material and have thicknesses larger than those of the other insulating films formed of the inorganic material. However, the fifth insulating film15may be formed of an inorganic material.

The common electrode COM is positioned on the upper side of the fifth insulating film15. The common electrode COM is covered by the sixth insulating film16. The sixth insulating film16is formed of a translucent inorganic material such as silicon oxide or silicon nitride.

The pixel electrodes PE1to PE3are positioned on the upper side of the sixth insulating film16and face the common electrode COM through the sixth insulating film16. The pixel electrodes PE1to PE3and the common electrode COM are formed of a translucent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel electrodes PE1to PE3are covered by the first alignment film AL1. The first alignment film AL1covers the sixth insulating film16as well.

The counter substrate SUB2is based on a translucent second substrate20such as a glass substrate or a resin substrate. The counter substrate SUB2includes, on a side on which the second substrate20faces the array substrate SUB1, a light-shielding layer BM, the color filters CFR, CFG, and CFB, an overcoat layer OC, a second alignment film AL2, and the like.

As illustrated inFIG.6, the light-shielding layer BM is positioned on the side on which the second substrate20faces the array substrate SUB1. The light-shielding layer BM defines the sizes of openings facing the respective pixel electrodes PE1to PE3. The light-shielding layer BM is formed of a black resin material or a light-shielding metallic material.

The color filters CFR, CFG, and CFB are positioned on the side on which the second substrate20faces the array substrate SUB1, and end parts of each color filter overlap the light-shielding layer BM. The color filter CFR faces the pixel electrode PE1. The color filter CFG faces the pixel electrode PE2. The color filter CFB faces the pixel electrode PE3. For example, the color filters CFR, CFG, and CFB are formed of resin materials colored in blue, red, and green, respectively.

The overcoat layer OC covers the color filters CFR, CFG, and CFB. The overcoat layer OC is formed of a translucent resin material. The second alignment film AL2covers the overcoat layer OC. The first alignment film AL1and the second alignment film AL2are formed of, for example, a material having horizontal orientation.

As described above, the counter substrate SUB2includes the light-shielding layer BM and the color filters CFR, CFG, CFB, and the like. The light-shielding layer BM is disposed in regions facing wire parts such as the scanning lines G1, G2, and G3, the signal lines S1, S2, and S3, the switching elements TrD1, TrD2, and TrD3illustrated inFIG.4.

The counter substrate SUB2includes the color filters CFR, CFG, and CFB in three colors inFIG.6, but may include color filters in four or more colors including color filters in other colors such as white, transparent, yellow, magenta, and cyan, which are different from blue, red, and green. The color filters CFR, CFG, and CFB may be included in the array substrate SUB1.

The color filters CF are provided in the counter substrate SUB2inFIG.6, but what is called a color-filter-on-array (COA) structure including the color filters CF in the array substrate SUB1may be employed.

The array substrate SUB1and the counter substrate SUB2described above are disposed so that the first alignment film AL1and the second alignment film AL2face each other. The liquid crystal layer LC is encapsulated between the first alignment film AL1and the second alignment film AL2. The liquid crystal layer LC is made of a negative liquid crystal material having negative dielectric constant anisotropy or a positive liquid crystal material having positive dielectric constant anisotropy.

The array substrate SUB1faces a backlight unit IL, and the counter substrate SUB2is positioned on a display surface side. The backlight unit IL is applicable in various kinds of forms, but description of a detailed structure thereof is omitted.

A first optical element OD1including a first polarization plate PL1is disposed on the outer surface of the first substrate10or its surface facing the backlight unit IL. A second optical element OD2including a second polarization plate PL2is disposed on the outer surface of the second substrate20or its surface on an observation position side. A first polarization axis of the first polarization plate PL1and a second polarization axis of the second polarization plate PL2are in, for example, a cross Nicol positional relation on an X-Y plane. The first optical element OD1and the second optical element OD2may each include another optical functional element such as a wave plate.

For example, in a state in which no voltage is applied to the liquid crystal layer LC when the liquid crystal layer LC is a negative liquid crystal material, the long axis of each liquid crystal molecule LM is initially oriented in the X direction on an X-Y plane. In a state in which voltage is applied to the liquid crystal layer LC, in other words, in an “on” state in which an electric field is formed between each of the pixel electrodes PE1to PE3and the common electrode COM, the orientation state of the liquid crystal molecule LM changes due to influence of the electric field. In the “on” state, the polarization state of incident linearly polarized light changes in accordance with the orientation state of the liquid crystal molecule LM as the light passes through the liquid crystal layer LC.

FIG.7is a diagram illustrating an exemplary pixel arrangement according to the first embodiment. InFIG.7, Ph1represents the distance (disposition pitch) between pixels PixS (pixels PixR, PixG, and PixB) in the second direction Dy, and Pw1represents the distance (disposition pitch) therebetween in the first direction Dx. InFIG.8, only any constituent component necessary for description in the present disclosure is illustrated and any other constituent component is omitted or simplified.

As illustrated inFIG.7, the color filters CF (CFR, CFG, and CFB) of the pixels PixS (pixels PixR, PixG, and PixB) are partitioned by the light-shielding layer BM in each display panel110according to the present embodiment. The pixels PixS (pixels PixR, PixG, and PixB) emit light in colors (blue, red, and green) as light radiated from the backlight unit IL transmits through opening parts at which the color filters CF (CFR, CFG, and CFB) are provided.

The pixels PixR, PixG, and PixB are repeatedly arrayed in the stated order in the first direction Dx. The pixels PixR, PixG, and PixB in each color are arrayed alongside each other in the second direction Dy.

The following describes a detailed configuration of the scanning line drive circuit114A with reference toFIGS.8to12. Although the following description is made on the scanning line drive circuit114A, the description of the scanning line drive circuit114A is also applicable to the scanning line drive circuit114B since the scanning line drive circuit114B has the same configuration.

As illustrated inFIG.8, the scanning line drive circuit114A includes a plurality of output circuits50, a shift register51, and an inverting circuit52. The shift register51is a circuit configured to sequentially output a scanning signal SR to the output circuits50based on, for example, a clock signal from the driver IC115(refer toFIG.5). The scanning signal SR output from the shift register51is supplied as a common input signal Vin to four output circuits50.

The inverting circuit52is a circuit configured to output an input signal xVin obtained by inverting the scanning signal SR from the shift register51. When the scanning signal SR is high (high level voltage), the inverting circuit52outputs the input signal xVin that is low (low level voltage). When the scanning signal SR is low (low level voltage), the inverting circuit52outputs the input signal xVin that is high (high level voltage). The input signal xVin output from the inverting circuit52is supplied as a common signal to the four output circuits50.

A drive signal supply circuit54is a circuit configured to supply a first control signal Venb and a second control signal VGL to the four output circuits50. The first control signal Venb is supplied to the four output circuits50through respective four wires L1. The second control signal VGL is supplied to the four output circuits50through a common wire L2. The drive signal supply circuit54is, for example, a circuit included in the driver IC115. However, the drive signal supply circuit54may be provided individually from the driver IC115.

Each of the output circuits50is provided at the corresponding one of a plurality of scanning lines GL-1, GL-2, GL-3, and GL-4, respectively. The output circuits50are circuits configured to output output signals Vo to the scanning lines GL-1, GL-2, GL-3, and GL-4based on the input signals Vin and xVin. In the following description, the scanning lines GL-1, GL-2, GL-3, and GL-4are simply referred to as scanning lines GL when not needing to be distinguished from one another.

The output signals Vo are gate drive signals for the switching elements TrD1, TrD2, and TrD3(refer toFIG.4) included in the pixels Pix and each include any one of the first control signal Venb and the second control signal VGL from the drive signal supply circuit54. The first control signal Venb is a signal having potential with which the switching elements TrD1, TrD2, and TrD3are turned on, and the second control signal VGL is a signal having potential with which the switching elements TrD1, TrD2, and TrD3are turned off.

Although the four output circuits50and the four scanning lines GL are illustrated inFIG.8, the shift register51sequentially supplies the scanning signal SR to the four output circuits50(four scanning lines GL) in a time divisional manner. The number of the output circuits50to which the common scanning signal SR is supplied is not limited to four but may be one to three inclusive or five or more. The scanning line drive circuit114A inFIG.8is merely schematically illustrated and may include another circuit such as a buffer circuit or a level shifter as necessary.

FIG.9is a circuit diagram illustrating an exemplary configuration of each output circuit of each scanning line drive circuit. As illustrated inFIG.9, each output circuit50includes a first switching element Tr1, a second switching element Tr2, and a third switching element Tr3. The first switching element Tr1is constituted by an n-channel MOS TFT. The second switching element Tr2is constituted by a p-channel MOS TFT. The first switching element Tr1and the second switching element Tr2are coupled to each other in parallel and configured as a switching element TrC having a CMOS structure. The third switching element Tr3is constituted by an n-channel MOS TFT.

The gate of the first switching element Tr1is supplied with the input signal Vin based on the scanning signal SR from the shift register51. The first switching element Tr1is turned on and off under control of the input signal Vin. The gates of the second switching element Tr2and the third switching element Tr3are supplied with the input signal xVin obtained by inverting the scanning signal SR from the shift register51. The second switching element Tr2and the third switching element Tr3are turned on and off under control of the input signal xVin.

The first control signal Venb is supplied from the drive signal supply circuit54to the input side of the first switching element Tr1and the input side of the second switching element Tr2through the corresponding wire L1(refer toFIG.8). The second control signal VGL is supplied from the drive signal supply circuit54to the input side of the second switching element Tr2through the wire L2(refer toFIG.8). The output side of the first switching element Tr1, the output side of the second switching element Tr2, and the output side of the third switching element Tr3are electrically coupled to the corresponding scanning line GL and output the output signal Vo.

When the input signal Vin is high (high level voltage) and the input signal xVin is low (low level voltage), the first switching element Tr1and the second switching element Tr2are turned on (conduction state) and the third switching element Tr3is turned off (non-conduction state). Thus, the output circuit50outputs the first control signal Venb as the output signal Vo. Accordingly, the scanning line GL coupled to the output circuit50is selected.

When the input signal Vin is low (low level voltage) and the input signal xVin is high (high level voltage), the first switching element Tr1and the second switching element Tr2are turned off (non-conduction state) and the third switching element Tr3is turned on (conduction state). Thus, the output circuit50outputs the second control signal VGL as the output signal Vo. Accordingly, the scanning line GL coupled to the output circuit50is not selected.

Since the four output circuits50are supplied with the common input signals Vin and xVin as illustrated inFIG.8, the switching elements Tr of the four output circuits50are controlled and turned on and off in synchronization. Moreover, since the four output circuits50are individually coupled to the wires L1, the drive signal supply circuit54may output the first control signal Venb to the four output circuits50in a time divisional manner. In this case, the scanning lines GL coupled to the four output circuits50, respectively, are sequentially selected in a time divisional manner.

Since the four output circuits50are coupled to the common wire L2as illustrated inFIG.8, the drive signal supply circuit54outputs the second control signal VGL as the common output signal Vo to the four output circuits50. In this case, the scanning lines GL coupled to the four output circuits50are not selected in synchronization.

FIG.10is a plan view illustrating a region A1inFIG.5in an enlarged manner. As illustrated inFIG.10, a plurality of output circuits50-1,50-2,50-3, and50-4are arrayed alongside each other in the second direction Dy along the first side e1of the display region111. The output circuits50-1,50-2,50-3, and50-4illustrated inFIG.10serve as some circuits of the first circuit portion31of the scanning line drive circuit114A. In the following description, the output circuits50-1,50-2,50-3, and50-4are simply referred to as output circuits50when not needing to be distinguished from one another.

The first switching element Tr1, the second switching element Tr2, and the third switching element Tr3of each output circuit50are arrayed alongside each other in the direction (first direction Dx) orthogonal to the first side e1of the display region111. The wires L1extend in the second direction Dy along the first side e1between the first side e1of the display region111and the first switching element Tr1. The wire L2is provided on the substrate end part side of the third switching element Tr3and extends in the second direction Dy.

The first switching element Tr1, the second switching element Tr2, and the third switching element Tr3each include a semiconductor layer SC, a source electrode SE, a drain electrode DE, and a gate electrode GE. The source electrode SE, the drain electrode DE, and the gate electrode GE each extend in the direction (first direction Dx) orthogonal to the first side e1of the display region111. The gate electrode GE is provided over the semiconductor layer SC and disposed between the source electrode SE and the drain electrode DE in the direction (second direction Dy) along the first side e1. The semiconductor layer SC is electrically coupled to the drain electrode DE through a contact hole on one side of the gate electrode GE in the first direction Dx and electrically coupled to the source electrode SE through a contact hole on the other side of the gate electrode GE in the first direction Dx.

A channel region is formed at a part of the semiconductor layer SC, the part overlapping the gate electrode GE. The lengths of the channel regions of the semiconductor layers SC in a direction (inFIG.10, the first direction Dx) along the direction in which each gate electrode GE extends are referred to as channel widths W1a, W2a, and W3a. In other words, the channel widths W1a, W2a, and W3aare the widths of the channel regions of the semiconductor layers SC in a direction orthogonal to the direction in which the source electrodes SE and the gate electrodes GE are connected. In the region A1, the directions (channel width direction) of the channel widths W1a, W2a, and W3aare along the direction (first direction Dx) orthogonal to the first side e1of the display region111.

In the following description, the channel widths W1a, W2a, and W3aare simply referred to as channel widths W when not needing to be distinguished from one another. The first switching element Tr1, the second switching element Tr2, and the third switching element Tr3are simply referred to as switching elements Tr when not needing to be distinguished from one another.

In each output circuit50, the channel widths W1a, W2a, and W3aof the first switching element Tr1, the second switching element Tr2, and the third switching element Tr3are equal to one another in effect. The channel widths W1aof the first switching elements Tr1of the output circuits50-1,50-2,50-3, and50-4are equal to one another in effect. Similarly, the channel widths W2aof the second switching elements Tr2are equal to one another in effect and the channel widths W3aof the third switching element Tr3are equal to one another in effect. In other words, the channel widths W1a, W2a, and W3aof the switching elements electrically coupled to common wires L3and L4and turned on and off under control of the common input signals Vin and xVin are equal to one another in effect.

The drain electrodes DE of the first switching element Tr1, the second switching element Tr2, and the third switching element Tr3are formed of a common wire and electrically coupled to an output wire L5. The output wire L5extends toward the display region111across the wires L1and is electrically coupled to the corresponding scanning line GL. The output wire L5is a wire through which the output signal Vo from the output circuit50is output to the scanning line GL.

The source electrodes SE of the first switching element Tr1and the second switching element Tr2are formed of a common wire and electrically coupled to the corresponding wire L1through which the first control signal Venb is supplied. The source electrode SE of the third switching element Tr3are separated from the source electrodes SE of the first switching element Tr1and the second switching element Tr2and electrically coupled to the wire L2through which the second control signal VGL is supplied.

The gate electrodes GE of the first switching elements Tr1of the output circuits50-1,50-2,50-3, and50-4are coupled in parallel to one another through a gate coupling wire GB1. The gate coupling wire GB1extends in the second direction Dy across the source electrodes SE and the drain electrodes DE in a plan view. The four gate electrodes GE coupled through the gate coupling wire GB1are electrically coupled to the wire L3through a bridge wire LB. The wire L3is a wire through which the input signal Vin is supplied to the gates of the first switching elements Tr1.

The gate electrodes GE of the second switching elements Tr2and the gate electrodes GE of the third switching elements Tr3are formed of a common wire. The gate electrodes GE of the second switching elements Tr2and the gate electrodes GE of the third switching elements Tr3in the output circuits50-1,50-2,50-3, and50-4are coupled in parallel to one another through a gate coupling wire GB2. The gate coupling wire GB2extends in the second direction Dy across the drain electrodes DE and the gate coupling wire GB1in a plan view.

The gate electrodes GE of the second switching elements Tr2and the gate electrodes GE of the third switching element Tr3coupled to one another through the gate coupling wire GB2are electrically coupled to the wire L4. The wire L4is a wire through which the input signal xVin is supplied to the gates of the second switching elements Tr2and the gates of the third switching elements Tr3.

FIG.11is a plan view illustrating a region A2inFIG.5in an enlarged manner. The region A2illustrated inFIG.11in an enlarged manner is located on a side of the first tilted side ea1, which is close to a coupling part to the third side e3(refer toFIG.5), in other words, on the upper end side of the display region111, which is farthest away from the driver IC115. The output circuits50-1,50-2,50-3, and50-4illustrated inFIG.11serve as some circuits of the second circuit portion32of the scanning line drive circuit114A.

As illustrated inFIG.11, the output circuits50-1,50-2,50-3, and50-4are arrayed alongside each other along the first tilted side ea1of the display region111. The first switching elements Tr1, the second switching elements Tr2, and the third switching elements Tr3of the output circuits50in the region A2are coupled in the same manner as in the region A1described above with reference toFIG.10, and duplicate description thereof is omitted.

In the region A2, the first switching element Tr1, the second switching element Tr2, and the third switching element Tr3of each output circuit50are arrayed alongside each other in a direction orthogonal to the first tilted side ea1(direction intersecting the first direction Dx and the second direction Dy). The wires L1extend along the first tilted side ea1between the first tilted side ea1of the display region111and the first switching element Tr1. The wire L2is provided on the substrate end part side of the third switching element Tr3and extends in a direction parallel to a direction along the first tilted side ea1.

In the region A2, the source electrodes SE, the drain electrodes DE, and the gate electrodes GE of the first switching element Tr1, the second switching element Tr2, and the third switching element Tr3extend in the direction orthogonal to the first tilted side ea1of the display region111(direction intersecting the first direction Dx and the second direction Dy).

In the region A2, the directions of channel widths W1b, W2b, and W3bare provided along the direction orthogonal to the first tilted side ea1of the display region111(direction intersecting the first direction Dx and the second direction Dy). The channel widths W1b, W2b, and W3bof the first switching element Tr1, the second switching element Tr2, and the third switching element Tr3are equal to one another in effect. The channel widths W1b, W2b, and W3bof the switching elements are equivalent in effect among the output circuits50-1,50-2,50-3, and50-4.

The channel widths W1b, W2b, and W3bin the region A2illustrated inFIG.11are shorter than the channel widths W1a, W2a, and W3ain the region A2illustrated inFIG.10. More specifically, the channel widths W1b, W2b, and W3bof the switching elements Tr (the first switching element Tr1, the second switching element Tr2, and the third switching element Tr3) arrayed along the first tilted side ea1are shorter than the channel widths W1a, W2a, and W3aof the switching elements arrayed along the first side e1.

FIG.12is a plan view schematically illustrating a plurality of output circuits arrayed along the first tilted side of the display region.FIG.12illustrates, in an enlarged manner, the side (region A2) of the first tilted side ea1, which is close to the coupling part to the third side e3(refer toFIG.5), a side (side close to the region A1) of the first tilted side ea1, which is close to a coupling part to the first side e1(refer toFIG.5), and a middle region between these regions. Although the output circuits50-1are illustrated inFIG.12, the output circuits50-2,50-3, and50-4have the same configuration as the above-described configuration inFIG.11.

As illustrated inFIG.12, the channel widths W1b, W2b, and W3bof the switching elements in the region A2are shorter than channel widths W1c, W2c, and W3cof switching elements in the middle region. The channel widths W1c, W2c, and W3cof switching elements in the middle region are shorter than channel widths W1d, W2d, and W3dof switching elements on the side close to the region A1.

As illustrated inFIGS.11and12, the channel widths W1of the switching elements Tr arrayed along the first tilted side ea1decrease as separation from one end of the first side e1in the direction along the first tilted side ea1increases (in other words, as separation from the third side e3decreases).

As described above with reference toFIG.5, the lengths of the scanning lines GL provided in the region corresponding to the first tilted side ea1in the first direction Dx are shorter than the lengths of the scanning lines GL provided in the regions corresponding to the first side e1and the second side e2in the first direction Dx. Moreover, the lengths of the scanning lines GL provided in the region corresponding to the first tilted side ea1in the first direction Dx decrease as separation from the first side e1in the direction along the first tilted side ea1increases (in other words, as separation from the third side e3decreases).

Accordingly, in the present embodiment, the channel width W of the switching element Tr is longer as the length of the scanning line GL electrically coupled to the switching elements (first switching element Tr1, second switching element Tr2, and third switching element Tr3) in the first direction Dx is longer. More specifically, the lengths of the scanning lines GL provided in the region corresponding to the first tilted side ea1in the first direction Dx decrease as separation from the first side e1in the direction along the first tilted side ea1increases, and the channel widths W of the switching elements Tr arrayed along the first tilted side ea1decrease as separation from the first side e1increases.

The channel widths W of the switching elements Tr do not necessarily need to continuously decrease along the first tilted side ea1but may decrease for each set of the switching elements Tr (for example, the switching elements Tr included in the four output circuits50-1to50-4). The scanning lines GL do not necessarily need to continuously decrease along the first tilted side ea1but may decrease for each scanning line block including the scanning lines GL.

In the present embodiment, illustration of the third circuit portion33provided along the second tilted side ea2in the scanning line drive circuit114A is omitted. The output circuits50of the third circuit portion33are disposed at tilt to which the output circuits50inFIGS.11and12are inverted in the up-down direction. For example, when the source electrode SE, the drain electrode DE, and the gate electrode GE of each switching element Tr in the output circuits50of the second circuit portion32illustrated inFIGS.11and12are tilted at an angle +θ° in the first direction Dx, the source electrode SE, the drain electrode DE, and the gate electrode GE of each switching element Tr in the output circuits50of the third circuit portion33are tilted at an angle −θ° in the first direction Dx.

The channel widths W of the switching elements Tr arrayed along the second tilted side ea2are equal to the channel widths W of the switching elements Tr arrayed along the first tilted side ea1in effect. Moreover, the channel widths W of the switching elements Tr arrayed along the second tilted side ea2are shorter than the channel widths W of the switching elements Tr arrayed along the first side e1. Accordingly, the lengths of the scanning lines GL provided in the region corresponding to the second tilted side ea2in the first direction Dx decrease as separation from the first side e1in the direction along the second tilted side ea2increases, and the channel widths W of the switching elements Tr arrayed along the second tilted side ea2decrease as separation from the first side e1increases.

In the display device100of the present embodiment with such a configuration, the resistance values of the switching elements Tr coupled to the scanning lines GL are reduced as the resistance values of the scanning lines GL are larger. Accordingly, the display device100of the present embodiment can reduce load variance among the scanning lines GL even when the display region111has a deformed shape.

The following describes a total load on each display panel110including loads on the scanning lines GL. FIG.13is an explanatory diagram for description of a total load from the driver IC to a scanning line in each display panel according to the first embodiment. As illustrated inFIG.13, the total load on the display panel110from the driver IC115to the scanning line GL includes resistances R1, R2, R3, and R4and capacitances C1and C2.

The resistance R1is a resistance component of output impedance of the driver IC115. The resistance R2and the capacitance C1are a resistance component and a capacitance component of the wire L1for supplying the first control signal Venb and the wire L2for supplying the second control signal VGL (refer toFIGS.10to12). The resistance R3is a resistance component of the output circuit50. The resistance R4and the capacitance C2are a resistance component and a capacitance component of the scanning line GL.FIG.13illustrates the load on the display panel110for one scanning line GL, and the resistance R2and the capacitance C1of the wires L1and L2are the resistance R2and the capacitance C1of the wires L1and L2coupled to one scanning line GL.

The scanning lines GL have lengths different among regions, and the values of the resistance R4and the capacitance C2inFIG.13are larger as the lengths of the scanning lines GL are longer. As described above, the channel widths W of switching elements Tr are longer as the lengths of the scanning lines GL in the first direction Dx are longer. In other words, the value of the resistance R3of the output circuit50inFIG.13is smaller. Accordingly, load variance among the scanning lines GL can be reduced even when the display region111has a deformed shape and the lengths of the scanning lines GL are different from one another.

The following describes the “length of the scanning line GL in the first direction Dx”.FIG.14is an explanatory diagram for description of the length of a scanning line.FIG.14is a plan view schematically illustrating part of each display panel110in an enlarged manner, and the light-shielding layer BM is hatched. As illustrated inFIG.14, the light-shielding layer BM includes a peripheral overlapping part BMa, a scanning line overlapping part BMb, and a signal line overlapping part BMc. The peripheral overlapping part BMa is provided in the peripheral region and overlaps a peripheral circuit such as the scanning line drive circuit114A. The peripheral overlapping part BMa has an opening in a region overlapping the display region111and includes an inner edge part BMe provided along the outer periphery of the display region111. The scanning line overlapping part BMb and the signal line overlapping part BMc are provided in a region surrounded by the inner edge part BMe (region overlapping the display region111in effect) and overlap the scanning line GL and the signal line SL, respectively.

In the present specification, when the inner edge part BMe of the peripheral overlapping part BMa has a straight shape along each side of the outer periphery of the display region111, a length W-GL of the scanning line GL in the first direction Dx means the length of a part by which the scanning line GL extends on a side closer to a central part of the display region111than the inner edge part BMe. The inner edge part BMe of the peripheral overlapping part BMa is a virtual inner edge part BMe at which the scanning line overlapping part BMb and the signal line overlapping part BMc are not provided and that is continuous along each side of the outer periphery of the display region111.

More specifically, when the scanning line drive circuit114A is coupled to the right side of the scanning line GL in the first direction Dx and the scanning line drive circuit114B (refer toFIG.5) is coupled to the left side of the scanning line GL in the first direction Dx, the length W-GL of the scanning line GL in the first direction Dx is half of the length between a position at which the scanning line GL overlaps the inner edge part BMe on the right side in the first direction Dx and a position at which the scanning line GL overlaps the inner edge part BMe on the left side in the first direction Dx. In other words, the length W-GL is the length between a position at which the scanning line GL overlaps the inner edge part BMe and the middle point of the scanning line GL in the first direction Dx (left end of the scanning line GL inFIG.14).

When only one of the scanning line drive circuits114A and114B is coupled to the scanning line GL, the length W-GL of the scanning line GL in the first direction Dx is the length between the position at which the scanning line GL overlaps the inner edge part BMe on the right side in the first direction Dx and the position at which the scanning line GL overlaps the inner edge part BMe on the left side in the first direction Dx.

Example

FIG.15is a graph schematically illustrating the relation of the voltages of the first control signal and a plurality of scanning lines with time in display devices according to examples and comparative examples.FIG.15is a simulation result indicating change in voltage of each scanning line GL when the first control signal Venb supplied from the driver IC115(drive signal supply circuit54) changes from high (high level voltage) to low (low level voltage).

In Examples 1-1 to 1-4 inFIG.15, the channel widths W1a, W2a, and W3aof the switching elements Tr of each output circuit50provided along the first side e1of the display region111(refer toFIG.10) are 60 μm, and the channel widths W1b, W2b, and W3b(refer toFIG.11) of the switching elements Tr of each output circuit50provided along the first tilted side ea1of the display region111are 25 μm. In Comparative Examples 1-1 and 1-2, the channel widths W1a, W2a, and W3aof the switching elements Tr of each output circuit50provided along the first side e1of the display region111(refer toFIG.10) and the channel widths W1b, W2b, and W3bof the switching elements Tr of each output circuit50provided along the first tilted side ea1of the display region111(refer toFIG.11) are 60 μm.

Example 1-1 illustrates voltage change of a scanning line GL (refer to a scanning line GLa inFIG.14) at a position (refer to a position N1inFIG.14) overlapping the inner edge part BMe, the scanning line GL being located at a position farthest away from the driver IC115among the scanning lines GL provided in the region corresponding to the first tilted side ea1of the display region111. Example 1-2 illustrates voltage change of the scanning line GL at the middle point (refer to a position N2inFIG.14), the scanning line GL being located at the position farthest away from the driver IC115(refer to the scanning line GLa inFIG.14). Example 1-3 illustrates voltage change of a scanning line GL (refer to a scanning line GLb inFIG.14) at the same position in the first direction Dx (refer to a position N3inFIG.14) as the position N1in Example 1-1, the scanning line GL being provided in the region corresponding to the first side e1of the display region111. Example 1-4 illustrates voltage change of the scanning line GL (refer to the scanning line GLb inFIG.14) at the middle point (refer to position N4inFIG.14), the scanning line GL being provided in the region corresponding to the first side e1of the display region111.

Comparative Examples 1-1 and 1-2 illustrate voltage change of the scanning line GLa at the positions N1and N2when the channel widths W1a, W2a, W3a, W1b, W2b, and W3b(refer toFIG.11) are 60 μm. In Comparative Examples 1-1 and 1-2, voltage change of the scanning line GL (refer to the scanning line GLbFIG.14) provided in the region corresponding to the first side e1is the same as in Examples 1-3 and 1-4, and illustration thereof is omitted.

As illustrated inFIG.15, when the channel widths W of the switching elements Tr of each output circuit50is increased as the length of the corresponding scanning line GL in the first direction Dx is longer, the difference between the voltage values in Examples 1-1 and 1-2 and the voltage values in Examples 1-3 and 1-4 decreases and voltage change equivalent to that in Examples 1-3 and 1-4 occurs. In Comparative Examples 1-1 and 1-2, the difference of the voltage values is larger than in Examples 1-1, 1-2, 1-3, and 1-4.

The above-described result indicates that, in Examples 1-1 to 1-4, load variance among the scanning lines GL is reduced and the difference of the voltage values is reduced as compared to Comparative Examples 1-1 and 1-2.

Second Embodiment

FIG.16is a schematic diagram illustrating an exemplary display panel according to a second embodiment. In the following description, any same constituent component as in the above-described embodiment is denoted by the same reference sign and duplicate description thereof is omitted.

As illustrated inFIG.16, in a display panel110A according to the second embodiment, a plurality of signal line coupling wires SLCN coupling the signal lines SL to the signal line coupling circuit113are provided in a region between the third circuit portion33and the second tilted side ea2of the display region111. The third circuit portion33of the scanning line drive circuit114A is disposed at a tilt angle different from that for the second circuit portion32. Specifically, the distance between the third circuit portion33and the second tilted side ea2of the display region111is longer than the distance between the second circuit portion32and the first tilted side ea1of the display region111. The third circuit portion33is disposed so that the distance to the second tilted side ea2of the display region111is longer at a position closer to the signal line coupling circuit113.

Although the following description of the second embodiment is made on the third circuit portion33of the scanning line drive circuit114A, the description of the third circuit portion33of the scanning line drive circuit114A is also applicable to the sixth circuit portion36of the scanning line drive circuit114B.

FIG.17is a plan view schematically illustrating a plurality of output circuits arrayed along the second tilted side of the display region in the display panel according to the second embodiment.FIG.17is a plan view illustrating a region A3inFIG.16in an enlarged manner. The first switching elements Tr1, the second switching elements Tr2, and the third switching elements Tr3of a plurality of output circuits50in the region A3are coupled in the same manner as in the regions A1and A2described above with reference toFIGS.10and11, and duplicate description thereof is omitted.

As illustrated inFIG.17, the signal line coupling wires SLCN are provided in a region from the second tilted side ea2to a plurality of switching elements Tr arrayed along the second tilted side ea2and four wires L1for supplying the first control signal Venb. Each output wire L5is coupled to the drain electrode DE of the corresponding switching element Tr, extends toward the display region111across the wires L1and the signal line coupling wires SLCN, and is electrically coupled to the corresponding scanning line GL. Accordingly, the distance between the second tilted side ea2and the switching elements Tr arrayed along the second tilted side ea2is longer than the distance between the first tilted side ea1and the switching elements Tr arrayed along the first tilted side ea1. A load on the output circuits50in the region A3is larger than that on the output circuits50(refer toFIG.11) in the region A2by an amount corresponding to the capacitance of parts at which the output wires L5intersects the signal line coupling wires SLCN. In other words, the capacitance C2(refer toFIG.13) of each scanning line GL is larger in effect.

In the second embodiment, channel widths W1e, W2e, and W3eof the switching elements Tr arrayed along the second tilted side ea2are longer than the channel widths W1b, W2b, and W3bof the switching elements Tr arrayed along the first tilted side ea1(refer toFIG.11). Moreover, the channel widths W1e, W2e, and W3eof the switching elements Tr arrayed along the second tilted side ea2are shorter than the channel widths W1a, W2a, and W3aof the switching elements Tr arrayed along the first side e1(refer toFIG.10).

For example, when the channel widths W1b, W2b, and W3bof the switching elements Tr arrayed along the first tilted side ea1are 25 μm, the channel widths W1e, W2e, and W3eof the switching elements Tr arrayed along the second tilted side ea2are 30 μm approximately. However, the lengths of the channel widths W1e, W2e, and W3eare merely exemplary and may be changed as appropriate. Although only four output circuits50among the output circuits50along the second tilted side ea2are illustrated inFIG.17, the channel widths W of the switching elements Tr arrayed along the second tilted side ea2decrease as separation from the first side e1in the direction along the second tilted side ea2increases (in other words, as separation from the fourth side e4decreases), as in the example illustrated inFIG.12.

In the second embodiment with such a configuration, load variance among the scanning lines GL can be reduced across the entire side including the first tilted side ea1, the first side e1, and the second tilted side ea2of the display region111even when resistance value variance occurs between the scanning lines GL at the first tilted side ea1and the scanning lines GL at the second tilted side ea2.

InFIG.17, the source electrode SE, the drain electrode DE, and the gate electrode GE of each switching element Tr extend in a direction not orthogonal to the second tilted side ea2. However, the present disclosure is not limited thereto and the source electrode SE, the drain electrode DE, and the gate electrode GE of each switching element Tr may extend in a direction orthogonal to the second tilted side ea2.

Modification

FIG.18is a diagram illustrating a modification of the pixel arrangement. As illustrated inFIG.18, in the pixel arrangement according to the modification, the pixels PixR, PixG, and PixB are repeatedly arranged in the stated order in the first direction Dx and the positions of the pixels PixR, PixG, and PixB are shifted between rows. The pixels PixR, PixG, and PixB are repeatedly arranged in the stated order in the second direction Dy as well.

A distance Ph1(disposition pitch) between pixels PixS (pixels PixR, PixG, and PixB) illustrated inFIG.18in the second direction Dy is shorter than the distance Ph1(disposition pitch) in the pixel configuration according to the first embodiment illustrated inFIG.7. A distance Pw1between pixels PixS (pixels PixR, PixG, and PixB) illustrated inFIG.18in the first direction Dx is longer than the distance Pw1in the pixel configuration according to the first embodiment illustrated inFIG.7.

In the pixel arrangement according to the modification, the disposition pitch between scanning lines GL decreases in accordance with the distance Ph1(disposition pitch) between the pixels PixS. Accordingly, constraint on disposition of a peripheral circuit becomes large and it becomes difficult to dispose a circuit or element for adjusting loads on the scanning lines GL. In this case as well, according to the first and second embodiments described above, no circuit nor element for adjusting the loads needs to be added and it is possible to reduce variance among the loads on the scanning lines GL by adjusting the channel widths W of the switching elements Tr. Moreover, such pixel arrangement can increase the resolution of the display panel110and is excellently employed in the display panel110for a VR system. The pixel arrangement according to the modification is also applicable to any of the first and second embodiments.

Third Embodiment

FIG.19is a schematic diagram illustrating an exemplary display panel according to a third embodiment. As illustrated inFIG.19, in a display panel110B according to the third embodiment, the direction in which the scanning lines GL extend is not parallel nor orthogonal to the direction in which the signal lines SL extend. Specifically, the signal lines SL extend in the second direction Dy. The scanning lines GL extend in a direction tilted in the first direction Dx and the second direction Dy.

The scanning line drive circuit114B includes a seventh circuit portion37extending along the third side e3so that scanning lines GL are provided at a corner part of the display region111where the third side e3is coupled to the first tilted side ea1. The scanning lines GL at the fourth side e4of the display region111are electrically coupled to the scanning line drive circuit114A through scanning line coupling wires GLCN.

In the example illustrated inFIG.19, a scanning line GL connecting a corner part of the display region111where the first side e1is coupled to the second tilted side ea2and a corner part of the display region111where the second side e2is coupled to the third tilted side ea3is longest among the scanning lines GL. The lengths of the scanning lines GL gradually decrease as separation from the longest scanning line GL in a direction orthogonal to the scanning lines GL increases.

In the present embodiment, the lengths of the scanning lines GL provided in the region corresponding to the first side e1of the display region111are not constant but decrease in the direction from the second tilted side ea2side to the first tilted side ea1side. The channel widths W of the switching elements Tr arrayed along the first side e1are shorter as the scanning lines GL are shorter. The scanning lines GL provided in the region corresponding to the first side e1of the display region111are shorter in the direction from the third tilted side ea3side to the fourth tilted side ea4side. The channel widths W of the switching elements Tr arrayed along the second side e2are shorter as the scanning lines GL are shorter.

FIG.20is a schematic diagram illustrating the relation among a pixel arrangement, signal lines, and scanning lines in the display panel according to the third embodiment. As illustrated inFIG.20, the pixels PixR, PixG, and PixB are arranged and shifted from each other in the second direction Dy. The relation of Pw1:Ph1=1:3 holds when the lengths of the pixels PixR, PixG, and PixB in the first direction Dx are the distance Pw1and the lengths of the pixels PixR, PixG, and PixB in the second direction Dy are the distance Ph1.

InFIG.20, a direction Vs1is a direction in which the signal lines SL extend. A direction Vsg orthogonal to the direction Vs1is parallel to the first direction Dx. A direction Vss is a direction in which the scanning lines GL extend. The scanning lines GL are tilted in the first direction Dx by an angle θg between the directions Vss and Vsg.

As illustrated inFIG.20, the direction Vss is a direction in which a virtual line connecting first reference positions Pg1at the pixels PixR coupled to one scanning line GL extends. For example, each first reference position Pg1is the middle point on the scanning line GL between adjacent signal lines SL intersecting the scanning line GL in a plan view. The first reference position Pg1is not limited thereto but may be, for example, the area barycenter of the pixel PixR. The first reference position Pg1is defined with reference to the pixel PixR above but may be defined with reference to a pixel PixG or PixB in place of the pixel PixR.

As illustrated inFIG.20, the direction Vs1is a direction in which a virtual line connecting second reference positions Ps1at the pixels PixR coupled to one signal line SL extends. For example, each second reference position Ps1is the middle point on the signal line SL between intersection positions Pt of scanning lines GL with the signal line SL in a plan view. The second reference position Ps1is not limited thereto but may be, for example, the area barycenter of the pixel PixR. The second reference position Ps1is defined with reference to the pixel PixR above but may be defined with reference to a pixel PixG or PixB in place of the pixel PixR.

As illustrated inFIG.20, the pixel PixR is shifted from an adjacent pixel PixG by a distance Δh1in the direction Vs1. Two pixels PixR coupled to one scanning line GL are shifted from each other by triple of the distance Δh1. When half of the distance Ph1illustrated inFIG.6is equal to triple of the distance Δh1illustrated inFIG.20, adjacent pixels of the same color in the first direction Dx, for example, the pixels PixR are shifted from each other by half in the direction Vs1. Thus, pixels of the same color are located at two kinds of positions in an even-numbered column and an odd-numbered column. As a result, black and white lines in the horizontal direction can be displayed more finely, and accordingly, the effective resolution of the display device100is improved. When the scanning lines GL illustrated inFIG.20extend straight in the direction Vss, the pixels PixR, PixG, and PixB form parallelograms as illustrated inFIG.19.

The pixel arrangement and pixel disposition pitches illustrated inFIG.20are merely exemplary and may be changed as appropriate.

Preferable embodiments of the present disclosure are described above, but the present disclosure is not limited to such embodiments. Contents disclosed in the embodiments are merely exemplary, and various kinds of modifications are possible without departing from the scope of the present disclosure. Any modification performed as appropriate without departing from the scope of the present disclosure belongs to the technical scope of the present disclosure. At least one of omission, replacement, and change of various constituent components may be performed without departing from the scope of the embodiments and the modification described above.