Patent ID: 12217792

DETAILED DESCRIPTION

The following disclosure provides different embodiments, or examples, for implementing features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, examples and are not limiting. Other components, materials, values, steps, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In accordance with some embodiments, a memory circuit includes a set of memory cells configured to store data, and a local input output (LIO) circuit coupled to a global bit line and the set of memory cells.

In some embodiments, the LIO circuit includes a sense amplifier configured to sense a first signal in response to at least a sense amplifier signal. In some embodiments, the first signal corresponds to a value of the data stored in the set of memory cells.

In some embodiments, the LIO circuit further includes a driver circuit configured to generate a global bit line signal in response to at least the first signal or an inverted first signal.

In some embodiments, the LIO circuit further includes a booster circuit coupled to the driver circuit and the global bit line. In some embodiments, the booster circuit is configured to adjust the global bit line signal in response to a delayed global bit line signal.

In some embodiments, the driver circuit is configured to cause a rising edge or a falling edge transition of the global bit line signal during a read operation of one or more memory cells in the set of memory cells. In some embodiments, in response to the rising edge or the falling edge transition of the global bit line signal, the booster circuit406causes the rising edge or the falling edge transition of the read global bit line signal to transition faster than other approaches without the booster circuit, thereby resulting in faster read operations than other approaches without the booster circuit.

FIG.1is a block diagram of a memory circuit100, in accordance with some embodiments.

FIG.1is simplified for the purpose of illustration. In some embodiments, memory circuit100includes various elements in addition to those depicted inFIG.1or is otherwise arranged so as to perform the operations discussed below.

Memory circuit100is an IC that includes memory partitions102A-102D, a global control circuit100GC and global input output (GIO) circuits100BL.

Each memory partition102A-102D includes memory banks110U and110L adjacent to a word line (WL) driver circuit110AC and a local control circuit110LC. Each memory bank110U and110L includes a memory cell array110AR and a local input output (LIO) circuit110BS.

A memory partition, e.g., a memory partition102A-102D, is a portion of memory circuit100that includes a subset of memory devices (not shown inFIG.1) and adjacent circuits configured to selectively access the subset of memory devices in program and read operations. In the embodiment depicted inFIG.1, memory circuit100includes a total of four partitions. In some embodiments, memory circuit100includes a total number of partitions greater or fewer than four.

GIO circuit100BL is a circuit configured to control access to one or more electrical paths, e.g., bit lines, to each memory device of the corresponding memory bank110U or110L of each memory partition102A-102D, e.g., by generating one or more bit line signals. In some embodiments, GIO circuit100BL includes a global bit line driver circuit. In some embodiments, GIO circuit100BL is coupled to each memory bank110U and110L by a corresponding global bit line (e.g., shown inFIG.2as RGBL or RGBLB).

Global control circuit100GC is a circuit configured to control some or all of program and read operations on each memory partition102A-102D, e.g., by generating and/or outputting one or more control and/or enable signals.

In some embodiments, global control circuit100GC includes one or more analog circuits configured to interface with memory partitions102A-102D, cause data to be programmed in one or more memory devices, and/or use data received from one or more memory devices in one or more circuit operations. In some embodiments, global control circuit100GC includes one or more global address decode or pre-decoder circuits configured to output one or more address signals to the WL driver circuit110AC of each memory partition102A-102D.

Each WL driver circuit110AC is configured to generate word line signals on corresponding word lines WL. In some embodiments, each WL driver circuit110AC is configured to output word line signals on corresponding word lines WL to the adjacent memory banks110U and110L of the corresponding memory partition102A-102D.

Each local control circuit110LC is an electronic circuit configured to receive one or more address signals. Each local control circuit110LC is configured to generate signals corresponding to adjacent subsets of memory devices identified by the one or more address signals. In some embodiments, the adjacent subsets of memory devices correspond to columns of memory devices. In some embodiments, each local control circuit110LC is configured to generate each signal as a complementary pair of signals. In some embodiments, each local control circuit110LC is configured to output the signals to corresponding word line driver circuits within the adjacent WL driver circuit110AC of the corresponding memory partition102A-102D. In some embodiments, the local control circuit110LC includes a bank decoder circuit.

Each LIO circuit110BS is configured to selectively access one or more bit lines (shown inFIG.2) coupled to adjacent subsets of memory devices of the corresponding memory cell array110AR responsive to GIO circuit100BL, e.g., based on one or more BL control signals. In some embodiments, the adjacent subsets of memory devices correspond to rows of memory devices. In some embodiments, the LIO circuit110BS includes a bit line selection circuit.

Each memory bank110U and110L includes the corresponding memory cell array110AR including memory cells or memory devices112configured to be accessed in program and read operations by the adjacent LIO circuit110BS and the adjacent WL driver circuit110AC.

Each memory cell array110AR includes an array of memory devices112having N rows and M columns, where M and N are positive integers. The rows of cells in memory cell array102are arranged in a first direction X. The columns of cells in memory cell array102are arranged in a second direction Y. The second direction Y is different from the first direction X. In some embodiments, the second direction Y is perpendicular to the first direction X. In some embodiments, each memory cell array110AR is divided into an upper region and a lower region (shown inFIG.2).

Memory device112is shown in memory bank110U and110L of memory partition102A. For ease of illustration, memory device112is not shown in memory bank110U and110L of memory partitions102B,102C and102D.

Memory device112is an electrical, electromechanical, electromagnetic, or other device configured to store bit data represented by logical states. At least one logical state of memory device112is capable of being programmed in a write operation and detected in a read operation. In some embodiments, a logical state corresponds to a voltage level of an electrical charge stored in a given memory device112. In some embodiments, a logical state corresponds to a physical property, e.g., a voltage, a current, a resistance or a magnetic orientation, of a component of a given memory device112.

In some embodiments, memory device112includes one or more single port (SP) static random access memory (SRAM) cells. In some embodiments, memory device112includes one or more dual port (DP) SRAM cells. In some embodiments, memory device112includes one or more multi-port SRAM cells. Different types of memory cells in memory device112are within the contemplated scope of the present disclosure. In some embodiments, memory device112includes one or more dynamic random access memory (DRAM) cells. In some embodiments, memory device112includes one or more one-time programmable (OTP) memory devices such as electronic fuse (eFuse) or anti-fuse devices, flash memory devices, random-access memory (RAM) devices, resistive RAM devices, ferroelectric RAM devices, magneto-resistive RAM devices, erasable programmable read only memory (EPROM) devices, electrically erasable programmable read only memory (EEPROM) devices, or the like. In some embodiments, memory device112is an OTP memory device including one or more OTP memory cells.

Other configurations of memory circuit100are within the scope of the present disclosure.

FIG.2is a circuit diagram of a memory circuit200, in accordance with some embodiments.

Memory circuit200is an embodiment of memory circuit100ofFIG.1, and similar detailed description is therefore omitted. For example, LIO circuit210BS of memory circuit200is an embodiment of LIO circuit110BS.

Memory circuit200includes memory partitions102A-102D, global control circuit100GC, GIO circuits100BL and a conductive line260.

Each memory partition102A-102D includes memory banks110U and110L adjacent to a WL driver circuit212and a local control circuit110LC. Each memory bank110U and110L includes a memory cell array210and a LIO circuit210BS.

In comparison with memory circuit100ofFIG.1, each memory cell array210is an embodiment of memory cell array110AR, each LIO circuit210BS is an embodiment of LIO circuit110BS, and each of WL driver circuit212is an embodiment of WL driver circuit110AC, and similar detailed description is therefore omitted.

In comparison with each memory cell array110AR ofFIG.1, each memory cell array210is divided into an upper region of memory cells210aand a lower region of memory cells210b, and similar detailed description is therefore omitted.

In comparison with each WL driver circuit110AC ofFIG.1, each WL driver circuit212is divided into WL driver circuit212aand WL driver circuit212b, and similar detailed description is therefore omitted.

LIO circuit210BS in memory partition102A includes a booster circuit206dand a RGBL driver circuit230d. LIO circuit210BS in memory partition102B includes a booster circuit206cand a RGBL driver circuit230c. LIO circuit210BS in memory partition102C includes a booster circuit206band a RGBL driver circuit230b. LIO circuit210BS in memory partition102D includes a booster circuit206aand a RGBL driver circuit230a.

Each booster circuit206a,206b,206cor206dis coupled to a corresponding RGBL driver circuit230a,230b,230cor230d. Each of the booster circuits206a,206b,206cor206dand the corresponding RGBL driver circuits230a,230b,230cor230dare coupled to the GIO circuit100BL by conductive line260.

Conductive line260extends in the second direction Y. Conductive line260extends from the GIO circuit100BL to memory partition102A. Conductive line260overlaps at least a portion of the GIO circuit100BL, memory partitions102B-102D and at least a portion of memory partition102A. In some embodiments, conductive line260is referred to as a global bit line GBL. The global bit line GBL has a global bit line signal GBL′. In some embodiments, conductive line260is referred to as a read global bit line RGBL, and has a corresponding read global bit line signal RGBL′. In some embodiments, conductive line260is referred to as a global bit line bar GBLB. The global bit line bar GBLB has a global bit line bar signal GBLB′. In some embodiments, conductive line260is referred to as a read global bit line bar RGBLB, and has a corresponding read global bit line bar signal RGBLB′. In some embodiments, conductive line260extends in the second direction Y across each of the memory partitions102A-102D of memory circuit200.

Each RGBL driver circuit230a,230b,230cor230dis coupled to the read global bit line RGBL or the read global bit line bar RGBLB. Each RGBL driver circuit230a,230b,230cor230dis configured to generate a global bit line signal GBL′ or a global bit line bar signal GBLB′. In some embodiments, each RGBL driver circuit230a,230b,230cor230dis configured to set the global bit line signal GBL′ or global bit line bar signal GBLB′ in response to a corresponding value of datum stored in the corresponding memory cell within the corresponding memory partition102A,102B,102C or102D. In some embodiments, at least one of RGBL driver circuit230a,230b,230cor230dis configured to cause a transition of the global bit line signal GBL′ or global bit line bar signal GBLB′ in response to the corresponding value of datum stored in the corresponding memory cell within the corresponding memory partition102A,102B,102C or102D.

Each booster circuit206a,206b,206cor206dis coupled to the read global bit line RGBL or the read global bit line bar RGBLB. In some embodiments, during a read operation of one or more memory cells in corresponding memory partition102A,102B,102C or102D, the corresponding booster circuit206a,206b,206cor206dis configured to adjust the read global bit line signal RGBL′ in response to a transition of the corresponding read global bit line signal RGBL′ and a corresponding delayed read global bit line signal (e.g., signal S2inFIGS.4-7). In some embodiments, during a read operation of one or more memory cells in corresponding memory partition102A,102B,102C or102D, the corresponding booster circuit206a,206b,206cor206dis configured to adjust a rising edge or a falling edge of the read global bit line signal RGBL′ in response to the transition of the corresponding read global bit line signal RGBL′ and the corresponding delayed read global bit line signal (e.g., signal S2inFIGS.4-7).

In some embodiments, during a read operation of one or more memory cells in corresponding memory partition102A,102B,102C or102D, the corresponding booster circuit206a,206b,206cor206dis configured to adjust the read global bit line bar signal RGBLB′ in response to a transition of the corresponding read global bit line bar signal RGBLB′ and a corresponding delayed read global bit line bar signal (e.g., signal S2inFIGS.4-7). In some embodiments, during a read operation of one or more memory cells in corresponding memory partition102A,102B,102C or102D, the corresponding booster circuit206a,206b,206cor206dis configured to adjust a rising edge or a falling edge of the read global bit line bar signal RGBLB′ in response to the transition of the corresponding read global bit line bar signal RGBLB′ and the corresponding delayed read global bit line bar signal (e.g., signal S2inFIGS.4-7).

In some embodiments, during a read operation of one or more memory cells in corresponding memory partition102A,102B,102C or102D, a transition of the corresponding read global bit line signal RGBL′ or the read global bit line bar signal RGBLB′ from logically low to logically high causes the corresponding booster circuit206a,206b,206cor206dto thereby cause the transition of the corresponding read global bit line signal RGBL′ or read global bit line bar signal RGBLB′ from logically low to logically high (e.g., rising edge) to be increased or improved compared to other approaches, thereby resulting in timing improvements of memory circuit200during one or more read operations.

In some embodiments, during a read operation of one or more memory cells in corresponding memory partition102A,102B,102C or102D, a transition of the corresponding read global bit line signal RGBL′ or the read global bit line bar signal RGBLB′ from logically high to logically low causes the corresponding booster circuit206a,206b,206cor206dto thereby cause the transition of the corresponding read global bit line signal RGBL′ or read global bit line bar signal RGBLB′ from logically high to logically low (e.g., falling edge) to be increased or improved compared to other approaches, thereby resulting in timing improvements of memory circuit200during one or more read operations.

In some embodiments, booster circuits206a,206b,206cand206d, RGBL driver circuits230a,230b,230cand230d, and conductive line260are shown as being configured for the left-side portion of memory circuit200for ease of illustration. However, in some embodiments, memory circuit200is configured such that circuits similar to the booster circuits206a,206b,206cand206d, RGBL driver circuits230a,230b,230cand230d, and conductive line260are included in the right-side portion of memory circuit200, are not shown for ease of illustration, and similar detailed description is therefore omitted.

Other configurations of memory circuit200are within the scope of the present disclosure.

Memory Cell

FIG.3is a circuit diagram of a memory cell300usable inFIGS.1and2, in accordance with some embodiments.

Memory cell300is usable as one or more memory cells MCB in at least one of memory cell array110AR ofFIG.1, memory device112ofFIG.1, memory cell array210aofFIG.2or memory cell array210bofFIG.2.

Memory cell300is a six transistor (6T) single port (SP) SRAM memory cell used for illustration. In some embodiments, memory cell300employs a number of transistors other than six. Other types of memory are within the scope of various embodiments.

Memory cell300comprises two P-type metal oxide semiconductor (PMOS) transistors P1and P2, and four N-type metal oxide semiconductor (NMOS) transistors N1, N2, N3, and N4. Transistors P1, P2, N1, and N2form a cross latch or a pair of cross-coupled inverters. For example, PMOS transistor P1and NMOS transistor N1form a first inverter while PMOS transistor P2and NMOS transistor N2form a second inverter.

A source terminal of each of PMOS transistors P1and P2are configured as a voltage supply node NODE_1. Each voltage supply node NODE_1is coupled to a first voltage source VDDI. A drain terminal of PMOS transistor P1is coupled with a drain terminal of NMOS transistor N1, a gate terminal of PMOS transistor P2, a gate terminal of NMOS transistor N2, and a source terminal of NMOS transistor N3, and is configured as a storage node ND.

A drain terminal of PMOS transistor P2is coupled with a drain terminal of NMOS transistor N2, a gate terminal of PMOS transistor P1, a gate terminal of NMOS transistor N1, and a source terminal of NMOS transistor N4, and is configured as a storage node NDB. A source terminal of each of NMOS transistors N1and N2is configured as a supply reference voltage node (not labelled) having a supply reference voltage VSS. The source terminal of each of NMOS transistors N1and N2is also coupled to supply reference voltage VSS.

A word line WL is coupled with a gate terminal of each of NMOS transistors N3and N4. Word line WL is also called a write control line because NMOS transistors N3and N4are configured to be controlled by a signal on word line WL in order to transfer data between bit lines BL, BLB and corresponding nodes ND, NDB.

A drain terminal of NMOS transistor N3is coupled to a bit line BL. A drain terminal of NMOS transistor N4is coupled to a bit line BLB. Bit lines BL and BLB are configured as both data input and output for memory cell300. In some embodiments, in a write operation, applying a logical value to a first bit line BL and the opposite logical value to the other bit line BLB enables writing the logical values on the bit lines to memory cell300. Each of bit lines BL and BLB is called a data line because the data carried on bit lines BL and BLB are written to and read from corresponding nodes ND and NDB.

Word line WL corresponds to one or more word lines WL inFIG.2. Bit line BL corresponds to one or more bit lines BL inFIG.2. Bit line bar BLB corresponds to one or more bit line bars BLB inFIG.2.

Other configurations of memory cell300are within the scope of the present disclosure.

Memory Circuit

FIG.4is a circuit diagram of a memory circuit400, in accordance with some embodiments.

Memory circuit400is an embodiment of LIO circuit210BS and GIO circuit100BL ofFIG.2, and similar detailed description is therefore omitted. For example, memory circuit400illustrates a non-limiting example where an LIO circuit402ofFIG.4is an embodiment of LIO circuit210BS ofFIG.2, and a GIO circuit404ofFIG.4is an embodiment of GIO circuit100BL ofFIG.2, and similar detailed description is therefore omitted.

Memory circuit400includes LIO circuit402coupled to GIO circuit404by conductive line260. In some embodiments, conductive line260is a read global bit line bar RGBLB. For ease of illustration and brevity,FIGS.4-7are described with conductive line260as the read global bit line bar RGBLB. In some embodiments, conductive line260is a read global bit line RGBL.

LIO circuit402includes a booster circuit406, a sense amplifier420, an inverter I3, and a driver circuit430.

In comparison with memory circuit200ofFIG.2, booster circuit406is an embodiment of at least one of booster circuit206a,206b,206cor206d, driver circuit430is an embodiment of at least one of driver circuit230a,230b,230cor230d, and similar detailed description is therefore omitted.

Booster circuit406is coupled to the read global bit line bar RGBLB. Booster circuit406is configured to adjust a rising edge or a falling edge of the read global bit line bar signal RGBLB′ in response to a signal S2and a transition of the corresponding read global bit line bar signal RGBLB′.

Booster circuit406includes an inverter I1, a delay circuit410, an inverter I2and a feedback circuit416.

Inverter I1is configured to generate a signal RGBL′ in response to the read global bit line bar signal RGBLB′. In some embodiments, the signal RGBL′ is inverted from the read global bit line bar signal RGBLB′. An input terminal of inverter I1is coupled to the read global bit line bar RGBLB, and is configured to receive the read global bit line bar signal RGBLB′. An output terminal of inverter I1is coupled to an input terminal of delay circuit410and a first input terminal of feedback circuit416, and is configured to output the signal RGBL′.

Delay circuit410is coupled between inverter I1and inverter I2. Delay circuit410is configured to generate a delayed signal S1in response to the signal RGBL′. In some embodiments, the delayed signal S1is delayed from the signal RGBL′. An input terminal of delay circuit410is configured to receive the signal RGBL′. An output terminal of delay circuit410is coupled to an input terminal of inverter I2by a conductive path412. The output terminal of delay circuit410is coupled to an input terminal of inverter I2, and is configured to output the signal RGBL′. In some embodiments, the conductive path412is a conductive wire loop that introduces a delay to delayed signal S1. In some embodiments, the delay circuit410is replaced with conductive path412, and similar detailed description is therefore omitted.

Other configurations of delay circuit410are within the scope of the present disclosure.

Inverter I2is configured to generate a signal S2in response to the delayed signal S1. In some embodiments, the signal S2is inverted from the delayed signal S1. The input terminal of inverter I2is configured to receive the delayed signal S1. An output terminal of inverter I2is coupled to a second input terminal of feedback circuit416, and is configured to output the signal S2. In some embodiments, the signal S2corresponds to a delayed version of the read global bit line bar signal RGBLB′.

Feedback circuit416is coupled between inverter I2and the read global bit line bar RGBLB. Feedback circuit416is configured to adjust the rising edge or the falling edge of the read global bit line bar signal RGBLB′ in response to the signal S2and a transition of the signal RGBL′. In some embodiments, feedback circuit416is configured to adjust the rising edge or the falling edge of the read global bit line bar signal RGBLB′ in response to the signal S2and the transition of the corresponding read global bit line bar signal RGBLB′.

Feedback circuit416includes PMOS transistors MP1and MP2, and NMOS transistors MN1and MN2. A gate of NMOS transistor MN2and a gate of PMOS transistor MP2correspond to the first input terminal of feedback circuit416. A gate of NMOS transistor MN1and a gate of PMOS transistor MP1correspond to the second input terminal of feedback circuit416.

A source of PMOS transistor MP1is coupled to a voltage supply VDD. A gate of PMOS transistor MP1is configured to receive the signal S2, and is coupled to the output terminal of inverter I2and a gate of NMOS transistor MN1. Each of a drain of PMOS transistor MP1and a source of PMOS transistor MP2are coupled together by least a node (not labelled).

A gate of PMOS transistor MP2is configured to receive the signal RGBL′, and is coupled to the output terminal of inverter I1and a gate of NMOS transistor MN2. A drain of PMOS transistor MP2and a drain of NMOS transistor MN2are coupled together by an output node (not labelled), and the output node (not labelled) is further coupled to the read global bit line bar RGBLB. Thus, the drain of PMOS transistor MP2and the drain of NMOS transistor MN2are coupled to the read global bit line bar RGBLB.

A gate of NMOS transistor MN2is configured to receive the signal RGBL′, and is coupled to the output terminal of inverter I1and the gate of PMOS transistor MP2. Each of a source of NMOS transistor MN2and a drain of NMOS transistor MN1are coupled together by least a node (not labelled).

A gate of NMOS transistor MN1is configured to receive the signal S2, and is coupled to the output terminal of inverter I2and the gate of PMOS transistor MP1. A source of NMOS transistor MN1is coupled to a reference voltage supply VSS.

Other configurations, numbers of transistor or types of transistors in feedback circuit416are within the scope of the present disclosure.

Sense amplifier420is coupled to the driver circuit430and inverter I3. In some embodiments, sense amplifier420is further coupled to one or more memory cells in memory cell array210aor210b. Sense amplifier420is configured to sense a bit line bar signal RBLB and a bit line signal RBL in response to at least a sense amplifier signal SAE. In some embodiments, bit line bar signal RBLB is a local bit line bar signal, and bit line signal RBL is a local bit line signal. In some embodiments, the bit line bar signal RBLB corresponds to a value of data stored in one or more memory cells in memory cell array210aor210b.

Inverter I3is coupled to the sense amplifier420and the driver circuit430. Inverter I3is configured to generate an inverted bit line signal RBLN in response to the bit line signal RBL. In some embodiments, the inverted bit line signal RBLN is inverted from the bit line signal RBL. An input terminal of inverter I3is coupled to the sense amplifier420by a local bit line. The input terminal of inverter I3is configured to receive the bit line signal RBL from the sense amplifier420. An output terminal of inverter I3is coupled to a gate of NMOS transistor MN3of driver circuit430, and is configured to output the inverted bit line signal RBLN. In some embodiments, the inverted bit line signal RBLN corresponds to the bit line bar signal RBLB. In some embodiments, the inverted bit line signal RBLN corresponds to the value of data stored in one or more memory cells in memory cell array210aor210b.

Driver circuit430is coupled to the read global bit line bar GBLB, sense amplifier420and inverter I3. Driver circuit430is configured to adjust the read global bit line bar signal RGBLB′ in response to at least the inverted bit line signal RBLN or the bit line bar signal RBLB. In some embodiments, driver circuit430is configured to cause a transition of the read global bit line bar signal RGBLB′ to a logic 1 or a logic 0 based on a value of datum stored in a memory cell (not shown) coupled to the sense amplifier. In some embodiments, driver circuit430is configured to cause a transition of the read global bit line bar signal RGBLB′ to a logic 1 or a logic 0 in response to at least the inverted bit line signal RBLN or the bit line bar signal RBLB.

Driver circuit430includes PMOS transistor MP3and NMOS transistor MN3.

A source of PMOS transistor MP3is coupled to the voltage supply VDD. A gate of PMOS transistor MP3is configured to receive the bit line bar signal RBLB, and is coupled to the sense amplifier420by a local bit line bar. Each of a drain of PMOS transistor MP3and a drain of NMOS transistor MN3are coupled together by least an output node (not labelled). Each of the drain of PMOS transistor MP3and the drain of NMOS transistor MN3are coupled to the read global bit line bar RGBLB.

A gate of NMOS transistor MN3is configured to receive the inverted bit line signal RBLN, and is coupled to the output terminal of inverter I3. A source of NMOS transistor MN3is coupled to the reference voltage supply VSS.

WhileFIGS.4-7are described with the conductive line260as the read global bit line bar RGBLB, in some embodiments, the conductive line260is a read global bit line RGBL, and similar detailed description is therefore omitted. In these embodiments, the local bit line and the local bit line bar would be swapped with each other, as well as the bit line signal RBL of the local bit line and the bit line bar signal RBLB of the local bit line bar.

Other configurations, numbers of transistor or types of transistors in driver circuit430are within the scope of the present disclosure.

Other configurations, other circuit elements, numbers of transistor or types of transistors in LIO circuit402are within the scope of the present disclosure.

GIO circuit404is coupled to the read global bit line bar RGBLB and the LIO circuit402. GIO circuit404is configured to output a data signal Q in response to the read global bit line bar signal RGBLB. In some embodiments, the data signal Q corresponds to the value of data stored in one or more memory cells in memory cell array210aor210b.

GIO circuit404includes an inverter I6and a latch circuit408.

Inverter I6is configured to generate the data signal Q in response to the read global bit line bar signal RGBLB′. In some embodiments, the data signal Q is inverted from the read global bit line bar signal RGBLB′. An input terminal of inverter I6is coupled to the read global bit line bar RGBLB, and is configured to receive the read global bit line bar signal RGBLB′. An output terminal of inverter I6is configured to output the data signal Q. In some embodiments, the data signal Q corresponds to the bit line bar signal RBLB.

Latch circuit408is coupled to the read global bit line bar RGBLB and the input terminal of inverter I6. Latch circuit408is configured to latch a state or the value of the read global bit line bar signal RGBLB′. In some embodiments, latch circuit408is enabled or disabled by an enable signal RGBLEN and an inverted enable signal RGBLENB. In some embodiments, latch circuit408is disabled immediately prior to driver circuit430beginning to drive the read global bit line bar RGBLB. In some embodiments, latch circuit408is enabled after driver circuit430drives the read global bit line bar RGBLB.

Latch circuit408includes an inverter I4and an inverter I5.

Inverter I4is configured to generate a signal S3in response to the read global bit line bar signal RGBLB′. In some embodiments, the signal S3is inverted from the read global bit line bar signal RGBLB′. An input terminal of inverter I4is coupled to the read global bit line bar RGBLB, and is configured to receive the read global bit line bar signal RGBLB′. An output terminal of inverter I4is coupled to an input terminal of inverter I5, and is configured to output the signal S3.

Inverter I5is configured to generate the read global bit line bar signal RGBLB′ in response to signal S3. A first input terminal of inverter I5is coupled to the output terminal of inverter I4, and is configured to receive the signal S3. A second input terminal of inverter I5is configured to receive the enable signal RGBLEN. A third input terminal of inverter I5is configured to receive the inverted enable signal RGBLENB. An output terminal of inverter I5is coupled to the input terminal of inverter I6, and is configured to output the read global bit line bar signal RGBLB′.

In some embodiments, inverter I5is enabled or disabled by the enable signal RGBLEN and the inverted enable signal RGBLENB. In some embodiments, inverter I5is disabled immediately prior to driver circuit430beginning to drive the read global bit line bar RGBLB. In some embodiments, inverter I5is enabled after driver circuit430drives the read global bit line bar RGBLB. In some embodiments, inverter I5is disabled during read operations of memory cells. In some embodiments, inverter I5is enabled before or after read operations of memory cells.

Other configurations, other types of circuit elements or numbers of circuit elements in GIO circuit404are within the scope of the present disclosure.

A non-limiting example of a read operation of a memory cell coupled to the LIO circuit402is described with respect to driver circuit430, sense amplifier420and inverter I3, and GIO circuit404. For brevity, operation of at least booster circuit406is described below with respect toFIG.5.

For example, in some embodiments, if the memory cell coupled to LIO circuit402is configured to store a logic 1, and a difference between a voltage of the bit line bar signal RBLB and the bit line signal RBL is greater than 0 (e.g., V(RBLB)−V(RBL)>0), then when the sense amplifier420turns on in response to the sense amplifier signal SAE, the bit line signal RBL becomes a logic 0, and the bit line bar signal RBLB stays a logic 1. In response to the bit line signal RBL becoming a logic 0, the inverter I3causes signal RBLN to be a logic 1 thereby turning on NMOS transistor N3. In response to turning on NMOS transistor N3, NMOS transistor N3pulls the read global bit line bar RGBLB and the read global bit line bar signal RGBLB′ towards the reference voltage supply VSS, and is a logic 0. In response to the read global bit line bar signal RGBLB′ being a logic 0, the inverter I6causes the output signal Q to be a logic 1 which corresponds to the data stored in the memory cell coupled to the LIO circuit402.

For example, in some embodiments, if the memory cell coupled to LIO circuit402is configured to store a logic 0, and a difference between a voltage of the bit line signal RBL and the bit line bar signal RBLB is greater than 0 (e.g., V(RBL)−V(RBLB)>0), then when the sense amplifier420turns on in response to the sense amplifier signal SAE, the bit line signal RBL becomes a logic 1, and the bit line bar signal RBLB becomes a logic 0. In response to the bit line signal RBL becoming a logic 1, the inverter I3causes signal RBLN to be a logic 0 thereby turning off NMOS transistor N3. In response to the bit line bar signal RBLB becoming a logic 0, causes PMOS transistor P3to turn on. In response to turning on PMOS transistor P3, PMOS transistor P3pulls the read global bit line bar RGBLB and the read global bit line bar signal RGBLB′ towards the voltage supply VDD, and is a logic 1. In response to the read global bit line bar signal RGBLB′ being a logic 1, the inverter I6causes the output signal Q to be a logic 0 which corresponds to the data stored in the memory cell coupled to the LIO circuit402.

In some embodiments, memory circuit400operates to achieve one or more benefits described herein including the details discussed above with respect to memory circuit100or200.

Other configurations of memory circuit400are within the scope of the present disclosure.

Waveforms

FIG.5is a timing diagram500of waveforms of a memory circuit, such as memory circuit400inFIG.4, memory circuit600inFIG.6, memory circuit700inFIG.7or memory circuits800A-800B inFIGS.8A-8B, in accordance with some embodiments.

In some embodiments,FIG.5is a timing diagram500of at least memory circuit100-200, memory circuit400or memory circuit600-900ofFIGS.6-9, in accordance with some embodiments.

In some embodiments, one or more read operations of the memory banks in at least memory circuit200or900ofFIG.9are applied to at least one of memory partition102A,102B,102C or102D, and timing diagram500corresponds to waveforms during the read operations of at least one of memory partition102A,102B,102C or102D.

Timing diagram500includes waveforms of the read global bit line bar signal RGBLB′, the read global bit line signal RGBL′, the signal S1and the signal S2.

At time T0, the read global bit line bar signal RGBLB′ is logically low, the read global bit line signal RGBL′ is logically high, the signal S1is logically high and the signal S2is logically low.

At time T0, in response to the read global bit line signal RGBL′ being logically high, and in response to the signal S2being logically low, the feedback circuit416is turned off. For example, at time TO, in response to the read global bit line signal RGBL′ being logically high, the NMOS transistor MN2is turned on, and PMOS transistor MP2is turned off, and in response to the signal S2being logically low, the NMOS transistor MN1is turned off, and PMOS transistor MP1is turned on.

At time T1, the driver circuit430causes the read global bit line bar signal RGBLB′ to transition from logically low to logically high, and inverter I1causes the read global bit line signal RGBL′ to transition from logically high to logically low.

At time T2, the delay circuit410causes the signal S1to transition from logically high to logically low, and inverter I2causes the signal S2to transition from logically low to logically high.

In some embodiments, the signal S1is delayed with respect to the read global bit line signal RGBL′ by at least a delay D1. In some embodiments, the delay D1is caused by the delay circuit410. In some embodiments, the signal S2is delayed with respect to the read global bit line bar signal RGBLB′ by at least the delay D1.

At time T3, the transition of the read global bit line signal RGBL′ to logically low is sufficient enough to cause the feedback circuit416to turn on. For example, in some embodiments, at time T3, the transition of the read global bit line signal RGBL′ to logically low is sufficient enough to cause PMOS transistor MP2to turn on, and NMOS transistor MN2to turn off.

At time T3, since the signal S2is delayed with respect to the transition of the read global bit line bar signal RGBLB′ by delay D1, the signal S2at time T3causes PMOS transistor MP1to remain turned on, and NMOS transistor MN1to remain turned off.

At time T3, in response to the feedback circuit416turning on, the read global bit line bar signal RGBLB′ is boosted, and therefore transitions toward logically high faster than before time T3. For example, at time T3, in response to PMOS transistor MP2turning on and PMOS transistor MP1being already turned on, the feedback circuit416turns on, thereby causing the output node of the feedback circuit416to be electrically coupled to the voltage supply VDD, and PMOS transistors MP1and MP2pull the output node and the read global bit line bar signal RGBLB′ towards supply voltage VDD.

At time T4, the read global bit line bar signal RGBLB′ is logically high, and the read global bit line signal RGBL′ is logically low.

Between time T4and T5, the transition of signal S2to logically high is sufficient enough to cause PMOS transistor MP1to turn off, and NMOS transistor MN1to turn on, and the feedback circuit416is turned off, and the read global bit line bar signal RGBLB′ is no longer boosted by feedback circuit416. In some embodiments, the read global bit line bar signal RGBLB′ is boosted until the delay D1has passed. For example, in some embodiments, PMOS transistors MP1and MP2pull the output node and the read global bit line bar signal RGBLB′ towards supply voltage VDD until the transition of signal S2to logically high is sufficient enough to cause PMOS transistor MP1to turn off, and NMOS transistor MN1to turn on (e.g., between time T4and T5).

At time T5, the read global bit line bar signal RGBLB′ is logically high, the read global bit line signal RGBL′ is logically low, the signal S1is logically low and the signal S2is logically high. For example, at time T5, in response to the read global bit line signal RGBL′ being logically low, the NMOS transistor MN2is turned off, and PMOS transistor MP2is turned on, and in response to the signal S2being logically high, the NMOS transistor MN1is turned on, and PMOS transistor MP1is turned off.

At time T6, the driver circuit430causes the read global bit line bar signal RGBLB′ to transition from logically high to logically low, and inverter I1causes the read global bit line signal RGBL′ to transition from logically low to logically high.

At time T7, the delay circuit410causes the signal S1to transition from logically low to logically high, and inverter I2causes the signal S2to transition from logically high to logically low.

In some embodiments, the signal S1is delayed with respect to the read global bit line signal RGBL′ by at least the delay D1.

At time T8, the transition of the read global bit line signal RGBL′ to logically high is sufficient enough to cause the feedback circuit416to turn on. For example, in some embodiments, at time T8, the transition of the read global bit line signal RGBL′ to logically high is sufficient enough to cause PMOS transistor MP2to turn off, and NMOS transistor MN2to turn on.

At time T8, since the signal S2is delayed with respect to the transition of the read global bit line bar signal RGBLB′ by delay D1, the signal S2at time T8causes PMOS transistor MP1to remain turned off, and NMOS transistor MN1to remain turned on.

At time T8, in response to the feedback circuit416turning on, the read global bit line bar signal RGBLB′ is boosted, and therefore transitions toward logically low faster than before time T8. For example, at time T8, in response to NMOS transistor MN2turning on and NMOS transistor MN1being already turned on, the feedback circuit416turns on, thereby causing the output node of the feedback circuit416to be electrically coupled to the reference voltage supply VSS, and NMOS transistors MN1and MN2pull the output node and the read global bit line bar signal RGBLB′ towards the reference voltage supply VSS.

At time T9, the read global bit line bar signal RGBLB′ is logically low, and the read global bit line signal RGBL′ is logically high.

Between time T9and T10, the transition of signal S2to logically low is sufficient enough to cause PMOS transistor MP1to turn on, and NMOS transistor MN1to turn off, and the feedback circuit416is turned off, and the read global bit line bar signal RGBLB′ is no longer boosted by feedback circuit416. In some embodiments, the read global bit line bar signal RGBLB′ is boosted until the delay D1has passed. For example, in some embodiments, NMOS transistors MN1and MN2pull the output node and the read global bit line bar signal RGBLB′ towards the reference voltage supply VSS until the transition of signal S2to logically low is sufficient enough to cause PMOS transistor MP1to turn on, and NMOS transistor MN1to turn off (e.g., between time T9and T10).

At time T10, the read global bit line bar signal RGBLB′ is logically low, the read global bit line signal RGBL′ is logically high, the signal S1is logically high and the signal S2is logically low. For example, at time T10, in response to the read global bit line signal RGBL′ being logically high, the NMOS transistor MN2is turned on, and PMOS transistor MP2is turned off, and in response to the signal S2being logically low, the NMOS transistor MN1is turned off, and PMOS transistor MP1is turned on.

As shown between at least times T3and T4, booster circuit406causes the read global bit line bar signal RGBLB′ to transition from logically low to logically high faster than approaches without booster circuit406, thereby resulting in faster read operations than other approaches without booster circuit406.

As shown between at least times T8and T9, booster circuit406causes the read global bit line bar signal RGBLB′ to transition from logically high to logically low faster than approaches without booster circuit406, thereby resulting in faster read operations than other approaches without booster circuit406.

In some embodiments, while timing diagram500is described with respect to memory banks110U, timing diagram500is also applicable to memory banks110L in a similar manner, and is not described for brevity.

Other configurations of timing diagram500are within the scope of the present disclosure.

FIG.6is a circuit diagram of a memory circuit600, in accordance with some embodiments.

Memory circuit600is an embodiment of LIO circuit210BS and GIO circuit100BL ofFIG.2, and similar detailed description is therefore omitted. For example, memory circuit600illustrates a non-limiting example where a delay circuit610includes a pair of inverters (e.g., inverter I6and inverter I7), and similar detailed description is therefore omitted.

Memory circuit600includes an LIO circuit602coupled to GIO circuit404by conductive line260. Memory circuit600is a variation of memory circuit400ofFIG.4, and similar detailed description is therefore omitted. In comparison with memory circuit400ofFIG.4, LIO circuit602ofFIG.6replaces LIO circuit402, and similar detailed description is therefore omitted.

LIO circuit602includes a booster circuit606, sense amplifier420, inverter I3, and driver circuit430.

Booster circuit606is a variation of booster circuit406. For example, booster circuit606replaces booster circuit406, and similar detailed description is therefore omitted. Booster circuit606includes inverter I1, a delay circuit610, inverter I2and feedback circuit416.

Delay circuit610of booster circuit606ofFIG.6is an embodiment of delay circuit410, and similar detailed description is therefore omitted.

Delay circuit610includes an inverter I6and an inverter I7.

Inverter I6is configured to generate a signal S4in response to the signal RGBL′. In some embodiments, the signal S4is inverted from the signal RGBL′. An input terminal of inverter I6is coupled to the output terminal of inverter I1, and is configured to receive the signal RGBL′. An output terminal of inverter I6is coupled to an input terminal of inverter I7, and is configured to output the signal S4.

Inverter I7is configured to generate the signal S1in response to the signal S4. In some embodiments, the signal S4is inverted from the signal S1. An input terminal of inverter I7is coupled to the output terminal of inverter I6, and is configured to receive the signal S4. An output terminal of inverter I7is coupled to the input terminal of inverter I2, and is configured to output the signal S1.

Other configurations, other circuit elements, numbers of inverters, numbers of transistor or types of transistors in LIO circuit602are within the scope of the present disclosure.

In some embodiments, memory circuit600operates to achieve one or more benefits described herein including the details discussed above with respect to memory circuit100,200or400.

Other configurations of memory circuit600are within the scope of the present disclosure.

FIG.7is a circuit diagram of a memory circuit700, in accordance with some embodiments.

Memory circuit700is an embodiment of LIO circuit210BS and GIO circuit100BL ofFIG.2, and similar detailed description is therefore omitted. For example, memory circuit700illustrates a non-limiting example where a delay circuit710includes a buffer circuit B1, and similar detailed description is therefore omitted.

Memory circuit700includes an LIO circuit702coupled to GIO circuit404by conductive line260. Memory circuit700is a variation of memory circuit400ofFIG.4, and similar detailed description is therefore omitted. In comparison with memory circuit400ofFIG.4, LIO circuit702ofFIG.7replaces LIO circuit402, and similar detailed description is therefore omitted.

LIO circuit702includes a booster circuit706, sense amplifier420, inverter I3, and driver circuit430.

Booster circuit706is a variation of booster circuit406. For example, booster circuit706replaces booster circuit406, and similar detailed description is therefore omitted. Booster circuit706includes inverter I1, a delay circuit710, inverter I2and feedback circuit416.

Delay circuit710of booster circuit706ofFIG.7is an embodiment of delay circuit410, and similar detailed description is therefore omitted.

Delay circuit710includes a buffer circuit B1.

Buffer circuit B1is configured to generate the delayed signal S1in response to the signal RGBL′. An input terminal of buffer circuit B1is coupled to the output terminal of inverter I1, and is configured to receive the signal RGBL′. An output terminal of buffer circuit B1is coupled to the input terminal of inverter I2, and is configured to output the delayed signal S1.

Other configurations, other circuit elements, numbers of buffer circuits, numbers of transistor or types of transistors in LIO circuit702are within the scope of the present disclosure.

In some embodiments, memory circuit700operates to achieve one or more benefits described herein including the details discussed above with respect to memory circuit100,200or400.

Other configurations of memory circuit700are within the scope of the present disclosure.

FIGS.8A-8Bare corresponding circuit diagrams of corresponding memory circuits800A-800B, in accordance with some embodiments.

Memory circuits800A-800B are a variation of memory circuit600ofFIG.6, and similar detailed description is therefore omitted. For example, memory circuit800A illustrates a non-limiting example where a feedback circuit816adoes not include NMOS transistors MN1and MN2, and memory circuit800B illustrates a non-limiting example where a feedback circuit816bdoes not include PMOS transistors MP1and MP2, and similar detailed description is therefore omitted.

Memory circuits800A-800B are embodiments of LIO circuit210BS and GIO circuit100BL ofFIG.2, and similar detailed description is therefore omitted.

Memory circuit800A includes an LIO circuit802acoupled to GIO circuit404by conductive line260. Memory circuit800B includes an LIO circuit802bcoupled to GIO circuit404by conductive line260. Memory circuits800A-800B are variations of memory circuit600ofFIG.6, and similar detailed description is therefore omitted. In comparison with memory circuit600of FIG.6, LIO circuit802aofFIG.8Areplaces LIO circuit602, and LIO circuit802bofFIG.8Breplaces LIO circuit602, and similar detailed description is therefore omitted.

LIO circuit802aincludes a booster circuit806a, sense amplifier420, inverter I3, and driver circuit430. LIO circuit802bincludes a booster circuit806b, sense amplifier420, inverter I3, and driver circuit430.

Booster circuits806a-806bare variations of booster circuit606. For example, booster circuits806aand806breplace booster circuit606, and similar detailed description is therefore omitted. Booster circuit806aincludes inverter I1, delay circuit710, inverter I2and a feedback circuit816a. Booster circuit806bincludes inverter I1, delay circuit710, inverter I2and a feedback circuit816b.

In comparison withFIG.6, feedback circuit816aofFIG.8Aand feedback circuit816bofFIG.8Breplace feedback circuit616, and similar detailed description is therefore omitted.

Feedback circuit816aincludes PMOS transistors MP1and MP2.

In comparison with feedback circuit416, feedback circuit816adoes not include NMOS transistors MN1and MN2. By not including NMOS transistors MN1and MN2, memory circuit800A includes less number of transistors, and therefore occupies less area than other approaches.

Feedback circuit816bincludes NMOS transistors MN1and MN2.

In comparison with feedback circuit416, feedback circuit816bdoes not include PMOS transistors MP1and MP2. By not including PMOS transistors MP1and MP2, memory circuit800B includes less number of transistors, and therefore occupies less area than other approaches.

Other configurations, numbers of transistor or types of transistors in feedback circuits816a-816bare within the scope of the present disclosure.

Other configurations, other circuit elements, numbers of inverters, numbers of transistor or types of transistors in LIO circuit802aor802bare within the scope of the present disclosure.

In some embodiments, memory circuits800A-800B operate to achieve one or more benefits described herein including the details discussed above with respect to memory circuit100,200or400.

Other configurations of memory circuits800A-800B are within the scope of the present disclosure.

FIG.9is a circuit diagram of a memory circuit900, in accordance with some embodiments.

Memory circuit900is a variation of memory circuit200ofFIG.2, and similar detailed description is therefore omitted. For example, memory circuit900illustrates a non-limiting example where at least one of the LIO circuits (e.g., LIO circuit210BS) does not include a booster circuit, and similar detailed description is therefore omitted.

Memory circuit900includes memory partitions102A-102D, global control circuit100GC, GIO circuits100BL and conductive line260.

Memory circuit900is a variation of memory circuit200ofFIG.2, and similar detailed description is therefore omitted. In comparison with memory circuit200ofFIG.2, LIO circuit210BS in memory partition102A does not include booster circuit206d.

LIO circuit210BS in memory partition102A includes RGBL driver circuit230d.

The memory banks110U and110L in memory partition102D are located adjacent to the GIO circuit100BL. The memory banks110U and110L in memory partition102A are located adjacent to a first end or an edge of memory circuit900that is opposite from a second end of the memory circuit900. The second end of memory circuit900is the end of memory circuit900where the GIO circuit100BL is located.

In some embodiments, one or more read operations of the memory banks in memory circuit900are applied in a sequential manner as shown inFIG.10. For example, read operations are applied to memory banks110U and110L in memory partition102A, then read operations are applied to memory banks110U and110L in memory partition102B, then read operations are applied to memory banks110U and110L in memory partition102C and then read operations are applied to memory banks110U and110L in memory partition102D.

In some embodiments, since the read operations of memory banks110U and110L in memory partition102A occur prior to the read operations of memory banks110U and110L in memory partitions102B-102D, the read global bit line bar signal RGBLB′ (e.g., shown as waveform1002inFIG.10) is not corrupted from noise and resistive/capacitive loading, therefore the memory partition102A in memory circuit900does not include booster circuit206d.

Other configurations, other circuit elements, numbers of inverters, numbers of transistor or types of transistors in LIO circuit802are within the scope of the present disclosure.

In some embodiments, memory circuit900operates to achieve one or more benefits described herein including the details discussed above with respect to memory circuit100,200or400.

Other configurations of memory circuit900are within the scope of the present disclosure.

Waveforms

FIG.10is a timing diagram1000of waveforms of a memory circuit, such as circuit200inFIG.2or circuit900inFIG.9, in accordance with some embodiments.

In some embodiments,FIG.10is a timing diagram1000of at least memory circuit100-200, memory circuit400or memory circuit600-900ofFIGS.6-9, in accordance with some embodiments.

In some embodiments, one or more read operations of the memory banks in at least memory circuit200or900are applied to memory partition102A, memory partition102B, memory partition102C and memory partition102D in a sequential manner (e.g., time T1-time T5) as shown inFIG.10, and waveforms1002,1004a,1004b,1006a,1006b,1008a,1008b,1010aand1010bcorrespond to the waveforms during the sequential read operations of memory partition102A, memory partition102B, memory partition102C and memory partition102D.

Timing diagram1000includes waveforms1002,1004a,1004b,1006a,1006b,1008a,1008b,1010aand1010b.

In some embodiments, waveform1002corresponds to the read global bit line RGBL during a read operation of memory bank110U of memory partition102A ofFIG.2with booster circuit206d. In some embodiments, waveform1002corresponds to the read global bit line RGBL during a read operation of memory bank110U of memory partition102B ofFIG.8A or8Bwithout booster circuit206d.

In some embodiments, waveform1004acorresponds to the read global bit line RGBL during a read operation of memory bank110U of memory partition102B with booster circuit206c, and waveform1004bcorresponds to the read global bit line RGBL during a read operation of memory bank110U of memory partition102B without booster circuit206c.

In some embodiments, waveform1006acorresponds to the read global bit line RGBL during a read operation of memory bank110U of memory partition102C with booster circuit206b, and waveform1006bcorresponds to the read global bit line RGBL during a read operation of memory bank110U of memory partition102C without booster circuit206b.

In some embodiments, waveform1008acorresponds to the read global bit line RGBL during a read operation of memory bank110U of memory partition102D with booster circuit206a, and waveform1008bcorresponds to the read global bit line RGBL during a read operation of memory bank110U of memory partition102D without booster circuit206a.

In some embodiments, waveform1010acorresponds to waveform1008aat the GIO circuit100BL, and waveform1010bcorresponds to waveform1008aat the GIO circuit100BL.

In some embodiments, waveforms1002,1004a,1004b,1006a,1006b,1008a,1008b,1010aand1010bcorrespond to a read “1” of the read global bit line RGBL. In some embodiments, waveforms1002,1004a,1004b,1006a,1006b,1008a,1008b,1010aand1010bcorrespond to a read “0” of the read global bit line RGBL.

At time T1, waveform1002transitions from logically low to logically high, and since the read operations of memory bank110U in memory partition102A occur prior to the read operations of memory bank110U in memory partitions102B-102D, the read global bit line bar signal RGBLB′ (e.g., shown as waveform1002) is not corrupted from noise and resistive/capacitive loading. In some embodiments, since waveform1002is not corrupted from noise and resistive/capacitive loading, memory bank110U in memory partition102A can be configured without booster circuit206d.

At time T2, waveforms1004aand1004btransition from logically low to logically high. In some embodiments, by including booster circuit206cin memory bank110U in memory partition102B, waveform1004atransitions from logically low to logically high faster than waveform1004b, thereby resulting in faster read operations than approaches without booster circuit206c.

At time T3, waveforms1006aand1006btransition from logically low to logically high. In some embodiments, by including booster circuit206bin memory bank110U in memory partition102C, waveform1006atransitions from logically low to logically high faster than waveform1006b, thereby resulting in faster read operations than approaches without booster circuit206b.

At time T4, waveforms1008aand1008btransition from logically low to logically high. In some embodiments, by including booster circuit206ain memory bank110U in memory partition102D, waveform1008atransitions from logically low to logically high faster than waveform1008b, thereby resulting in faster read operations than approaches without booster circuit206a.

At time T5, waveforms1010aand1010btransition from logically low to logically high.

At time T6, waveform1002transitions from logically high to logically low.

At time T7, waveforms1004aand1004btransition from logically high to logically low. In some embodiments, by including booster circuit206cin memory bank110U in memory partition102B, waveform1004atransitions from logically high to logically low faster than waveform1004b, thereby resulting in faster read operations than approaches without booster circuit206c.

At time T8, waveforms1006aand1006btransition from logically high to logically low. In some embodiments, by including booster circuit206bin memory bank110U in memory partition102C, waveform1006atransitions from logically high to logically low faster than waveform1006b, thereby resulting in faster read operations than approaches without booster circuit206b.

At time T9, waveforms1008aand1008btransition from logically high to logically low. In some embodiments, by including booster circuit206ain memory bank110U in memory partition102D, waveform1008atransitions from logically high to logically low faster than waveform1008b, thereby resulting in faster read operations than approaches without booster circuit206a.

At time T10, waveforms1010aand1010btransition from logically high to logically low.

In some embodiments, while timing diagram1000is described with respect to memory banks110U, timing diagram1000is also applicable to memory banks110L in a similar manner, and is not described for brevity.

Other configurations of timing diagram1000are within the scope of the present disclosure.

Method

FIG.11is a flowchart of a method1100of operating a circuit, in accordance with some embodiments.

In some embodiments,FIG.11is a flowchart of a method of operating at least one of memory circuit100ofFIG.1, memory circuit200ofFIG.2, memory circuit400ofFIG.4, memory circuit600,700,800A,800B or900of correspondingFIGS.6-9or memory cell300ofFIG.3.

It is understood that additional operations may be performed before, during, and/or after the method1100depicted inFIG.11, and that some other operations may only be briefly described herein. It is understood that method1100utilizes features of one or more of memory circuit100, memory circuit200, memory circuit400, memory circuit600,700,800A,800B or900or memory cell300, and similar detailed description is omitted for brevity.

In some embodiments, other order of operations of method1100is within the scope of the present disclosure. Method1100includes exemplary operations, but the operations are not necessarily performed in the order shown. Operations may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of disclosed embodiments. In some embodiments, one or more of the operations of method1100is not performed.

In operation1102of method1100, a first memory cell is read in response to at least a sense amplifier signal SAE. In some embodiments, the first memory cell is read by an LIO circuit.

In some embodiments, the first memory cell includes at least one of memory cell112, or one or more memory cells in at least memory cell array210a,210bor110AR.

In some embodiments, the LIO circuit includes at least one of LIO circuit LIO circuit110BS, LIO circuit210BS, LIO circuit402, LIO circuit602, LIO circuit702or LIO circuit802.

In some embodiments, operation1102includes at least one of operation1104,1106,1108or1110.

In operation1104of method1100, a first bit line signal and a second bit line signal are sensed in response to at least the sense amplifier signal.

In some embodiments, the first bit line signal includes bit line bar signal RBLB, and the second bit line signal includes bit line signal RBL. In some embodiments, the second bit line signal includes bit line bar signal RBLB, and the first bit line signal includes bit line signal RBL.

In some embodiments, the first bit line signal and the second bit line signal are sensed by a sense amplifier420. In some embodiments, the sense amplifier is coupled to the first memory cell.

In operation1106of method1100, an inverted second bit line signal is generated in response to the second bit line signal.

In some embodiments, the inverted second bit line signal includes at least inverted bit line signal RBLN. In some embodiments, the inverted second bit line signal corresponds to the first bit line signal.

In some embodiments, the inverted second bit line signal is generated by a first inverter. In some embodiments, the first inverter includes at least inverter I3. In some embodiments, the first inverter is coupled to the sense amplifier.

In operation1108of method1100, a global bit line signal is set in response to at least the first bit line signal or the inverted second bit line signal.

In some embodiments, the global bit line signal is on a global bit line. In some embodiments, the global bit line signal includes read global bit line signal RGBL′ or read global bit line bar signal RGBLB′. In some embodiments, the global bit line includes read global bit line RGBL or read global bit line bar RGBLB.

In some embodiments, the global bit line signal is set by a driver circuit430. In some embodiments, the driver circuit is coupled to the global bit line, the sense amplifier and the first inverter.

In operation1110of method1100, a rising edge or a falling edge of the global bit line signal is adjusted in response to a delayed global bit line signal.

In some embodiments, the delayed global bit line signal includes at least signal S2.

In some embodiments, the rising edge or the falling edge of the global bit line signal is adjusted by a booster circuit. In some embodiments, the booster circuit includes at least one of booster circuit206a,206b,206c,206d,406,606,706or806.

In some embodiments, operation1110includes at least one of operation1202,1204,1206or1208of method1200(shown inFIG.12).

In operation1112of method1100, at least a first value of datum stored in the first memory cell is output in response to the global bit line signal.

In some embodiments, the first value of datum stored in the first memory cell is output by GIO circuit100BL. In some embodiments, the first value of datum stored in the first memory cell is output by GIO circuit404. In some embodiments, the GIO circuit is coupled to the global bit line. In some embodiments, the first value of datum stored in the first memory cell is a logic 1 or a logic 0.

FIG.12is a flowchart of a method1200of operating a circuit, in accordance with some embodiments.

In some embodiments, method1200is an embodiment of operation1110of method1100ofFIG.11, and similar detailed description is omitted for brevity.

In some embodiments,FIG.12is a flowchart of a method of operating at least one of memory circuit100ofFIG.1, memory circuit200ofFIG.2, memory circuit400ofFIG.4, memory circuit600,700,800A,800B or900of correspondingFIGS.6-9or memory cell300ofFIG.3.

It is understood that additional operations may be performed before, during, and/or after the method1200depicted inFIG.12, and that some other operations may only be briefly described herein. It is understood that method1200utilizes features of one or more of memory circuit100, memory circuit200, memory circuit400, memory circuit600,700,800A,800B or900or memory cell300, and similar detailed description is omitted for brevity.

In some embodiments, other order of operations of method1200is within the scope of the present disclosure. Method1200includes exemplary operations, but the operations are not necessarily performed in the order shown. Operations may be added, replaced, changed order, and/or eliminated as appropriate, in accordance with the spirit and scope of disclosed embodiments. In some embodiments, one or more of the operations of method1200is not performed.

In operation1202of method1200, a second signal is generated in response to the global bit line signal.

In some embodiments, the second signal includes signal RGBL′ or RGBLB′.

In some embodiments, the second signal is generated by a first inverter. In some embodiments, the first inverter includes inverter I1. In some embodiments, the first inverter is coupled to the global bit line.

In operation1204of method1200, a delayed second signal is generated in response to the second signal.

In some embodiments, the delayed second signal includes signal S1.

In some embodiments, the delayed second signal is generated by a delay circuit. In some embodiments, the delay circuit includes at least one of delay circuit410,610or710or conductive path412. In some embodiments, the delay circuit is coupled to the first inverter.

In operation1206of method1200, a third signal is generated in response to the delayed second signal.

In some embodiments, the third signal includes signal S2. In some embodiments, the third signal corresponds to the delayed global bit line signal.

In some embodiments, the third signal is generated by a second inverter. In some embodiments, the second inverter includes inverter I2. In some embodiments, the second inverter is coupled to the delay circuit.

In operation1208of method1200, the rising edge or the falling edge of the global bit line signal is adjusted in response to the third signal and the second signal.

In some embodiments, the rising edge or the falling edge of the global bit line signal is adjusted in response to a transition of the global bit line signal or the global bit line bar signal caused by driver circuit402.

In some embodiments, the rising edge or the falling edge of the global bit line signal is adjusted by a feedback circuit. In some embodiments, the feedback circuit includes at least one of feedback circuit416or816. In some embodiments, the feedback circuit includes at least one of PMOS transistors MP1, PMOS transistor MP2, NMOS transistor MN1, NMOS transistor MN2or NMOS transistor MN4. In some embodiments, the feedback circuit is coupled between the second inverter and the global bit line.

While method1100and1200are described with respect to the global bit line GBL and the global bit line signal GBL′, at least one of method1100or1200is similarly applicable to the global bit line bar GBLB and the global bit line bar signal GBLB′, and similar detailed description is omitted for brevity.

By operating at least one of method1100or1200, the circuit operates to achieve the benefits discussed above with respect to at least one of memory circuit100ofFIG.1, memory circuit200ofFIG.2, memory circuit400ofFIG.4, memory circuit600,700,800A,800B or900of correspondingFIGS.6-9or memory cell300ofFIG.3.

In some embodiments, one or more of the operations of at least one of method1100or1200is not performed. Furthermore, various PMOS or NMOS transistors shown inFIGS.3-4and6-8are of a particular dopant type (e.g., N-type or P-type) are for illustration purposes. Embodiments of the disclosure are not limited to a particular transistor type, and one or more of the PMOS or NMOS transistors shown inFIGS.3-4and6-8can be substituted with a corresponding transistor of a different transistor/dopant type. Similarly, the low or high logical value of various signals used in the above description is also for illustration. Embodiments of the disclosure are not limited to a particular logical value when a signal is activated and/or deactivated. Selecting different logical values is within the scope of various embodiments. Selecting different numbers of inverters or buffers inFIGS.3-4and6-8is within the scope of various embodiments. Selecting different numbers of transistors inFIGS.3-4and6-8is within the scope of various embodiments. Selecting different numbers of delay circuits inFIG.3-12is within the scope of various embodiments.

It will be readily seen by one of ordinary skill in the art that one or more of the disclosed embodiments fulfill one or more of the advantages set forth above. After reading the foregoing specification, one of ordinary skill will be able to affect various changes, substitutions of equivalents and various other embodiments as broadly disclosed herein. It is therefore intended that the protection granted hereon be limited only by the definition contained in the appended claims and equivalents thereof.

One aspect of this description relates to a memory circuit. The memory circuit includes a set of memory cells configured to store data, and a local input output (LIO) circuit coupled to a global bit line and the set of memory cells. The LIO circuit includes a sense amplifier, a driver circuit and a booster circuit. The sense amplifier is configured to sense a first signal in response to at least a sense amplifier signal. The first signal corresponds to a value of the data stored in the set of memory cells. The driver circuit is configured to generate a global bit line signal in response to at least the first signal or an inverted first signal. The booster circuit is coupled to the driver circuit and the global bit line, and configured to adjust the global bit line signal in response to a delayed global bit line signal. In some embodiments, the booster circuit further includes a first inverter configured to generate a second signal in response to the global bit line signal, the first inverter including a first input terminal coupled to the global bit line, and a first output terminal. In some embodiments, the booster circuit further includes a delay circuit coupled to the first output terminal of the first inverter, and configured to generate a delayed second signal in response to the second signal. In some embodiments, the booster circuit further includes a second inverter configured to generate a third signal in response to the delayed second signal, the second inverter including a second input terminal and a second output terminal, the second input terminal being coupled to an output terminal of the delay circuit, the third signal corresponds to the delayed global bit line signal. In some embodiments, the booster circuit further includes a feedback circuit coupled between the second output terminal of the second inverter and the global bit line, and configured to adjust the global bit line signal in response to the third signal and the second signal. In some embodiments, the feedback circuit further includes a first P-type transistor having a first source coupled to a first voltage supply, a first gate of the first P-type transistor is configured to receive the third signal and is coupled to the second output terminal of the second inverter, and a first drain of the first P-type transistor is coupled with at least a first node. In some embodiments, the feedback circuit further includes a second P-type transistor having a second source coupled with the first drain of the first P-type transistor and the first node, a second gate of the second P-type transistor is configured to receive the second signal and is coupled to the first output terminal of the first inverter, and a second drain of the second P-type transistor is coupled with at least the global bit line by a second node. In some embodiments, the feedback circuit further includes a first N-type transistor having a third source coupled to at least a third node, a third gate of the first N-type transistor is configured to receive the second signal and is coupled to the first output terminal of the first inverter and the second gate of the second P-type transistor, and a third drain of the first N-type transistor is coupled with at least the second drain of the second P-type transistor, the global bit line and the second node. In some embodiments, the feedback circuit further includes a second N-type transistor having a fourth source coupled to at least a fourth node, a fourth gate of the second N-type transistor is configured to receive the third signal and is coupled to the second output terminal of the second inverter and the first gate of the first P-type transistor, and a fourth drain of the second N-type transistor is coupled with the third source of the first N-type transistor and the third node. In some embodiments, the feedback circuit further includes a third N-type transistor having a fifth source coupled to a reference voltage supply, a fifth gate of the third N-type transistor is configured to receive the sense amplifier signal, and a fifth drain of the third N-type transistor is coupled with the fourth source of the second N-type transistor and the fourth node. In some embodiments, the fourth source of the second N-type transistor and the fourth node are coupled to a reference voltage supply. In some embodiments, the delay circuit includes a third inverter configured to generate a first intermediate signal in response to the second signal, the third inverter including a third input terminal coupled to the first output terminal of the first inverter, and a third output terminal. In some embodiments, the delay circuit further includes a fourth inverter configured to generate the delayed second signal in response to the first intermediate signal, the fourth inverter including a fourth input terminal coupled to the third output terminal of the third inverter, and a fourth output terminal coupled to the second input terminal of the second inverter. In some embodiments, the delay circuit includes a first buffer configured to generate the delayed second signal in response to the second signal, the first buffer including a third input terminal coupled to the first output terminal of the first inverter, and a third output terminal coupled to the second input terminal of the second inverter. In some embodiments, the memory circuit further includes a global input output (GIO) circuit coupled to the LIO circuit and the global bit line, and configured to output the value of the data stored in a memory cell of the set of memory cells in response to the global bit line signal. In some embodiments, the GIO circuit includes a first inverter configured to generate the value of the data stored in the memory cell in response to the global bit line signal, the first inverter including a first input terminal coupled to the global bit line, and a first output terminal configured to output the value of the data stored in the memory cell. In some embodiments, the GIO circuit further includes a latch circuit configured to latch the global bit line signal in response to at least an enable signal, and being coupled to the global bit line and the first inverter. In some embodiments, the latch circuit includes a second inverter configured to generate a first intermediate signal in response to the global bit line signal, the second inverter including a second input terminal coupled to the global bit line, and a second output terminal configured to output the first intermediate signal. In some embodiments, the latch circuit further includes a third inverter configured to generate a latched global bit line signal in response to the first intermediate signal, the third inverter including a third input terminal coupled to the second output terminal of the second inverter, a first enable terminal configured to receive the enable signal, a second enable terminal configured to receive an inverted enable signal, and a third output terminal coupled to the first input terminal of the first inverter.

Another aspect of this description relates to a memory circuit. The memory circuit includes a global bit line, a set of memory banks including a first memory bank, and a global input output (GIO) circuit. In some embodiments, the first memory bank includes a first set of memory cells configured to store data, and a first local input output (LIO) circuit coupled to the global bit line and the first set of memory cells. In some embodiments, the first LIO circuit includes a first driver circuit and a first booster circuit. In some embodiments, the first driver circuit is coupled to the global bit line, is and configured to adjust a global bit line signal in response to at least a first signal. In some embodiments, the first signal corresponds to a first value of the data stored in a first memory cell of the first set of memory cells. In some embodiments, the first booster circuit is coupled to the global bit line, and is configured to adjust a rising edge or a falling edge of the global bit line signal in response to a first delayed global bit line signal. In some embodiments, the GIO circuit is coupled to the first LIO circuit and the global bit line, and configured to output the first value of the data stored in the first memory cell of the first set of memory cells in response to the global bit line signal. In some embodiments, the first LIO circuit further includes a first sense amplifier coupled to the first driver circuit, and configured to sense a first bit line signal and a second bit line signal in response to at least a first sense amplifier signal, the first signal corresponding to the first bit line signal or the second bit line signal. In some embodiments, the first LIO circuit further includes a first inverter coupled to the first sense amplifier and the first driver circuit, and configured to generate an inverted second bit line signal in response to the second bit line signal, the inverted second bit line signal corresponding to the first bit line signal. In some embodiments, the set of memory banks further includes a second memory bank separated from the first memory bank in a first direction. In some embodiments, the second memory bank includes a second set of memory cells configured to store the data. In some embodiments, the second memory bank further includes a second LIO circuit coupled to the global bit line and the second set of memory cells. In some embodiments, the second LIO circuit includes a second driver circuit coupled to the global bit line, and configured to adjust the global bit line signal in response to at least a third bit line signal, the third bit line signal corresponds to a first value of the data stored in a first memory cell of the second set of memory cells. In some embodiments, the second LIO circuit further includes a second sense amplifier coupled to the second driver circuit, and configured to sense the third bit line signal and a fourth bit line signal in response to at least a second sense amplifier signal. In some embodiments, the second LIO circuit further includes a second inverter coupled to the second sense amplifier and the second driver circuit, and configured to generate an inverted fourth bit line signal in response to the fourth bit line signal, the inverted fourth bit line signal corresponding to the third bit line signal. In some embodiments, the first memory bank is located adjacent to the GIO circuit, the second memory bank is located adjacent to a first end of the memory circuit opposite from the GIO circuit, and the second LIO circuit does not include a booster circuit. In some embodiments, the second LIO circuit further includes a second booster circuit coupled to the global bit line, and configured to adjust the rising edge or the falling edge of the global bit line signal in response to a second delayed global bit line signal. In some embodiments, the first memory bank is located adjacent to the GIO circuit, and the second memory bank is located adjacent to a first end of the memory circuit opposite from the GIO circuit. In some embodiments, the first booster circuit includes a first inverter configured to generate a second signal in response to the global bit line signal, the first inverter including a first input terminal coupled to the global bit line, and a first output terminal. In some embodiments, the first booster circuit further includes a delay circuit coupled to the first output terminal of the first inverter, and configured to generate a delayed second signal in response to the second signal. In some embodiments, the first booster circuit further includes a second inverter configured to generate a third signal in response to the delayed second signal, the second inverter including a second input terminal and a second output terminal, the second input terminal being coupled to an output terminal of the delay circuit, the third signal corresponds to the first delayed global bit line signal. In some embodiments, the first booster circuit further includes a feedback circuit coupled between the second output terminal of the second inverter and the global bit line, and configured to adjust the rising edge or the falling edge of the global bit line signal in response to the third signal and the second signal. In some embodiments, the delay circuit includes a third inverter configured to generate a first intermediate signal in response to the second signal, the third inverter including a third input terminal coupled to the first output terminal of the first inverter, and a third output terminal. In some embodiments, the delay circuit further includes a fourth inverter configured to generate the delayed second signal in response to the first intermediate signal, the fourth inverter including a fourth input terminal coupled to the third output terminal of the third inverter, and a fourth output terminal coupled to the second input terminal of the second inverter. In some embodiments, the delay circuit includes a first buffer configured to generate the delayed second signal in response to the second signal, the first buffer including a third input terminal coupled to the first output terminal of the first inverter, and a third output terminal coupled to the second input terminal of the second inverter.

Still another aspect of this description relates to a method of operating a memory circuit. The method includes reading, by a local input output (LIO) circuit, a first memory cell in response to at least a sense amplifier signal and outputting, by a global input output (GIO) circuit a first value of datum stored in a first memory cell in response to the global bit line signal, the GIO circuit being coupled to a global bit line. In some embodiments, reading the first memory cell includes sensing, by a sense amplifier, a first bit line signal and a second bit line signal in response to at least the sense amplifier signal, the sense amplifier being coupled to the first memory cell. In some embodiments, reading the first memory cell further includes generating, by a first inverter, an inverted second bit line signal in response to the second bit line signal, the inverted second bit line signal corresponding to the first bit line signal, the first inverter being coupled to the sense amplifier. In some embodiments, reading the first memory cell further includes setting, by a driver circuit, a global bit line signal on a global bit line in response to at least the first bit line signal or the inverted second bit line signal, the driver circuit being coupled to the global bit line, the sense amplifier and the first inverter. In some embodiments, reading the first memory cell further includes causing, by a booster circuit, a rising edge or a falling edge of the global bit line signal to be adjusted in response to a delayed global bit line signal.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.