Patent ID: 12224257

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.

Embodiments of the present disclosure are discussed in the context of semiconductor manufacturing, and in particular, in the context of forming three-dimensional (3D) semiconductor structures. A 3D semiconductor structure includes an integrated circuit (IC) portion and a warpage control portion bonded to the IC portion. By the configuration of the warpage control portion, warpage of the 3D semiconductor structure may be effectively reduced. Some variations of embodiments are discussed. It should be appreciated that the illustration throughout the drawings are schematic and not in scale. Throughout the various views and illustrative embodiments, the identical or similar numbers refer to the identical or similar elements.

FIGS.1A-1Eillustrate schematic cross-sectional views of an integrated circuit (IC) portion at various stages of fabrication, in accordance with some embodiments. Referring toFIG.1A, a redistribution structure110is formed over a temporary carrier TC. The temporary carrier TC may include any suitable material that provides mechanical support for the structure formed thereon in subsequent processing. Thereafter, the temporary carrier TC may be removed from the resulting structure once the manufacturing process is finished. For example, the temporary carrier TC includes glass, ceramic, metal, silicon, or the like. In some embodiments, the redistribution structure110is formed over the temporary carrier TC with an adhesive layer (not shown) interposed therebetween. For example, the adhesive layer is a light-to-heat conversion (LTHC) film which reduces or loses its adhesiveness when exposed to a radiation source (e.g., ultra-violet light, or a laser). Therefore, to remove the temporary carrier TC in subsequent processing, ultra-violet (UV) light or external energy may be applied to the adhesive layer to easily remove the temporary carrier TC and the adhesive layer from the resulting structure. Other suitable adhesive layers, such as die attach film (DAF), may be used, and the removal process of the temporary carrier TC may include a mechanical peel-off process, a grinding process, or an etching process, and may include additional cleaning process. In other embodiments, the adhesive layer is omitted.

The redistribution structure110may include one or more conductive features114(e.g., lines, vias, and pads) formed in one or more dielectric layers112. The dielectric layers112of the redistribution structure110may include silicon oxide, silicon nitride, low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, combinations of these, or the like, and may be formed through a process such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or any other suitable deposition method. The conductive features114of the redistribution structure110may be formed of a metal such as aluminum, copper, tungsten, titanium, alloy, or combinations thereof, and may be formed by patterning and metallization techniques, or other suitable deposition methods.

In some embodiments, a bottommost dielectric layer112bis deposited over the temporary carrier TC, and then a bottommost layer114bof the conductive feature114is deposited on the bottommost dielectric layer112b. Next, a middle dielectric layer112mis formed on the bottommost dielectric layer112bto cover the bottommost layer of the conductive feature114, where a portion of the bottommost layer114bof the conductive feature114is accessibly revealed by the openings of the middle dielectric layer112m. The middle layer114mof the conductive feature114is then formed in the openings of the middle dielectric layer112mand extending to the top surface of the middle dielectric layer112m. The steps of forming the middle dielectric layer112mand the middle layer114mof the conductive feature114may be repeated based on circuit design requirements.

Subsequently, a topmost dielectric layer112tis formed on the middle dielectric layer112mto cover the middle layer114mof the conductive feature114, and then a topmost layer114tof the conductive feature114is formed in the openings of the topmost dielectric layer112t. The topmost layer114tof the conductive feature114may be formed through damascene process (e.g., single damascene or dual damascene), or other suitable process. In some embodiments, the topmost layer114tof the conductive feature114functions as bonding connectors, and the topmost dielectric layer112tfunctions as bonding dielectric. For example, at least a portion of the topmost layer114tof the conductive feature114is in physical and electrical contact with the middle layer114mof the conductive feature114. In some embodiments, a portion of the topmost layer114tof the conductive feature114is dummy connectors and may be electrically floating. In some embodiments, the topmost layer114tof the conductive feature114and the topmost dielectric layer112tare used to bond the semiconductor die(s) together in a hybrid bonding process.

Referring toFIG.1B, a plurality of integrated circuit (IC) components120are bonded to the redistribution structure110. It should be noted that although two IC components120are illustrated, the number of the IC component120is not limited in the disclosure. The types of the IC components120may be the same or may be different. For example, the respective IC component120includes logic circuits, processing circuits, memory circuits, bias circuits, reference circuits, and/or the like. In some embodiments, the IC component120is referred to as a die or a chip that are singulated from a device wafer.

In some embodiments, each IC component120includes a semiconductor substrate122and an interconnect structure124formed on the semiconductor substrate122. The semiconductor substrate122may include circuitries (not shown) formed in a front-end-of-line (FEOL), and the interconnect structure124may be formed in a back-end-of-line (BEOL). In some embodiments, the interconnect structure124includes an inter-layer dielectric (ILD) layer formed over the semiconductor substrate122, and an inter-metallization dielectric (IMD) layer formed over the ILD layer. In some embodiments, the ILD layer and the IMD layer are formed of a low-K dielectric material, such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like. The ILD layer and the IMD layer may include any suitable number of dielectric material layers which is not limited thereto.

For example, the semiconductor substrate122includes a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, other supporting substrate (e.g., quartz, glass, etc.), combinations thereof, or the like, which may be doped or undoped. In some embodiments, the semiconductor substrate122includes an elementary semiconductor (e.g., silicon or germanium in a crystalline, a polycrystalline, or an amorphous structure, etc.), a compound semiconductor (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, etc.), an alloy semiconductor (e.g., silicon-germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminium gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), etc.), combinations thereof, or other suitable materials. For example, the compound semiconductor substrate may have a multilayer structure, or the substrate may include a multilayer compound semiconductor structure. In some embodiments, the alloy SiGe is formed over a silicon substrate. In other embodiments, a SiGe substrate is strained.

In some embodiments, a die attach film DAF is disposed on the back side122bof the semiconductor substrate122. For example, the die attach film DAF is provided before the IC component120is bonded to the redistribution structure110. Alternatively, the die attach film DAF is omitted. In some embodiments, a plurality of semiconductor devices123, which is symbolized by a block, is formed on the front side122aof the semiconductor substrate122, and the interconnect structure124may interconnect the semiconductor devices123. For example, the semiconductor devices123may be or may include active devices (e.g., transistors, diodes, etc.) and/or passive devices (e.g., capacitors, resistors, inductors, etc.), or other suitable electrical components. For example, the interconnect structure124includes a dielectric layer1241formed over the semiconductor substrate122, and an interconnecting circuitry1242embedded in the dielectric layer1241. The interconnecting circuitry1242may include conductive lines, conductive pads, conductive vias, etc. A material of the interconnecting circuitry1242may include copper or copper alloys, although other conductive materials (e.g., aluminum, silver, gold, and combinations thereof) may also be used. In some embodiments, two or more layers of conductive lines of the interconnecting circuitry1242are vertically interconnected by conductive vias of the interconnecting circuitry1242. The interconnecting circuitry1242embedded in the dielectric layer1241may be electrically coupled to the semiconductor devices123formed in and/or on the semiconductor substrate122.

In some embodiments, the interconnect structure124includes bonding connectors1243embedded in the dielectric layer1241. For example, the bonding connectors1243are formed using a damascene process (e.g., single damascene or dual damascene) or other suitable techniques. In some embodiments, a portion of the dielectric layer1241where the bonding connectors1243are buried functions as bonding dielectric. The bonding surface of the dielectric layer1241may be substantially leveled with the bonding surfaces of the bonding connectors1243. For example, at least a portion of the bonding connectors1243is in physical and electrical contact with the interconnecting circuitry1242. In some embodiments, a portion of the bonding connectors1243is dummy connectors and may be electrically floating. In some embodiments, the interconnect structure124of the IC component120is in physical and electrical contact with the redistribution structure110. For example, bonding of the IC component120to the redistribution structure110is achieved through the joint bonding mechanisms of the dielectric layer1241and the topmost dielectric layer112tbeing bonding together, and also the respective bonding connectors1243and the topmost layer114tof the conductive feature114being aligned and bonded together. In some embodiments, the bonding connector1243is in direct contact with the topmost layer114tof the conductive feature114, where the contact area of the bonding connector1243at the bonding interface IF of the topmost layer114tof the conductive feature114and the bonding connector1243is substantially equal to the surface area of the topmost layer114tof the conductive feature114. For example, the contact area of the bonding connector1243and the contact area of the topmost layer114tof the conductive feature114are substantially aligned at the bonding interface IF.

In some embodiments in which the dielectric layer1241and the topmost dielectric layer112tare both oxide materials, an oxide-oxide bond is formed between the dielectric layer1241and the topmost dielectric layer112t. In embodiments wherein the bonding connectors1243and114tare both formed of copper, the copper in the bonding connectors (1243and114t) forms a copper-copper bond. Thus, the IC component120and the redistribution structure110are hybrid bonded by the bonding connectors1243disposed in the uppermost part of the interconnect structure124of the IC component120and the topmost layer114tof the conductive feature114of the redistribution structure110. For example, at least a portion of connections of the bonding connectors (1243and114t) provides vertical electrical connections between the IC component120and the redistribution structure110. In some embodiments, the bonding may be performed at a die-to-wafer level. Alternatively, the bonding may be at wafer level, where the redistribution structure110and the IC component120are in a wafer form and bonded together, and then the bonded structure is singulated into separated packages.

Referring toFIG.1C, an insulating layer130is formed on the redistribution structure110to at least laterally cover the IC components120. For example, the insulating layer130is formed on the topmost dielectric layer112tof the redistribution structure110and extends along the sidewalls120sof the IC components120. The adjacent IC components120may fill the gap between adjacent IC components120and may be spatially separated from one another by the insulating layer130. In some embodiments, the insulating layer130may include silicon oxide, silicon nitride, and/or tetraethoxysilane (TEOS). In some embodiments, the insulating layer130may be formed through CVD, PECVD, ALD, or the like. In some embodiments, the insulating layer130may be referred to as “gap fill oxide”. In some other embodiments, the insulating layer130includes a molding compound, a molding underfill, a resin (such as epoxy), or the like. Other suitable insulating material that can provide a degree of protection for the IC components120may be used.

In some embodiments, a chemical mechanical polishing (CMP) step may next be employed to planarize the top surface130aof the insulating layer130. In some embodiments, the die attach films DAF disposed on the back sides122bof the semiconductor substrates122are at least laterally covered by the insulating layer130. For example, the top surface130aof the insulating layer130is substantially leveled with the top surfaces Dt of the die attach films DAF. In some embodiments, a bonding layer (15; as shown inFIG.4) is optionally formed over the IC components120and the insulating layer130. In some embodiments, the bonding layer is in physical contact with the top surface130aof the insulating layer130and the top surfaces Dt of the die attach films DAF. Alternatively, the die attach films DAF are omitted, and the top surface130aof the insulating layer130may be substantially leveled with the back sides122bof the semiconductor substrates122.

Referring toFIGS.1D and1E, the temporary carrier TC is removed to reveal the bottommost dielectric layer112bof the redistribution structure110, and then electrical connections are formed on the redistribution structure110opposite to the IC components120. For example, a portion of the bottommost dielectric layer112bis removed to form openings112oby using lithography and etching techniques or other suitable removal process. The openings112oof the bottommost dielectric layer112bmay accessibly expose at least a portion of the bottommost layer114bof the conductive feature114. Next, conductive materials may be formed in the openings112oof the bottommost dielectric layer112band patterned on the surface of the bottommost dielectric layer112b, so that through vias142in the openings112oof the bottommost dielectric layer112band contact pads144on the surface of the bottommost dielectric layer112bare formed. For example, the contact pads144and the through vias142connected to the contact pads144are electrically connected to the bottommost dielectric layer112b. In some embodiments, the contact pads144include under-bump metallurgy (UBM) pattern for further electrical connection.

In some embodiments, a passivation layer146is optionally formed on the bottommost dielectric layer112bin order to provide a degree of protection for the underlying structures. The passivation layer146may be made of one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, combinations of these, or other suitable dielectric materials. The passivation layer146may be formed through a process such as CVD, although any suitable process may be utilized. For example, the passivation layer146includes openings accessibly revealing at least a portion of the contact pads144.

Subsequently, a plurality of conductive terminals150are formed in the openings of the passivation layer146and may be in physical and electrical contact with the contact pads144that are exposed by the passivation layer146. In some embodiments, the respective conductive terminal150is a metal pillar152with a solder cap154formed thereon. In some embodiments, the conductive terminals150include controlled collapse chip connection (C4) bumps, and/or may include a material such as solder, tin, or other suitable materials (e.g., silver, lead-free tin, copper, etc.). Other terminal structures (e.g., ball grid array (BGA) balls, micro-bumps, and/or the like) may be used. Up to here, the IC portion10A of the semiconductor structure is fabricated. The above examples are provided for illustrative purposes only, and other embodiments may utilize fewer or additional elements in the IC portion.

FIGS.2A-2Billustrate schematic warpage profiles of an IC portion in accordance with some embodiments, andFIGS.3A-3Billustrate schematic contour diagrams of an IC portion in accordance with some embodiments. For illustration purposes, the warpage profiles of the IC portion may be schematic and exaggerated throughout the drawings and the details of the IC portion are not illustrated. Referring toFIGS.2A-2BandFIG.1E, as a result of the manufacturing process, warping of the IC portion10A shown inFIG.1Emay occur. For example, warpage occurs due to mismatch of the coefficients of thermal expansion (CTE) between materials, application of heat, temperature fluctuations, and/or the like. It is understood that the warpage of structure may adversely impact the electrical performance of the devices/circuits formed in the IC portion10A, and the warpage issue may affect subsequent processing and/or product reliability.

The bowing of the IC portion10A causes a bonding surface BS (e.g., the surface opposite to the conductive terminals150) to be on a curved plane. In some embodiments, the IC portion10A has a concave warpage (i.e. smiling profile), where the bonding surface BS of the IC portion10A bows upwards as illustrated inFIG.2A. In some other embodiments, the IC portion10A has a convex warpage (i.e. crying profile), where the bonding surface BS of the IC portion10A bows downwards as illustrated inFIG.2B. In some embodiments, a height difference H1in the bonding surface BS of the IC portion10A at a high temperature (e.g., joint temperature about 250 degrees Celsius) may be about 80 μm or less than 80 μm. In the examples described above, the warpage of the IC portion may be symmetrical. Due to a complicated semiconductor processing, the IC portion10A may present more complex warpages rather than simple convex or simple concave warpages.

Referring toFIGS.3A-3B, in some embodiments, some regions of the IC portion10A present a convex warpage and some other regions of the IC portion10A present a concave warpage, where a portion of the bonding surface BS may bow upwards and another portion of the bonding surface BS may bow downwards. In some embodiments, the IC portion10A may have asymmetric warpage. The various factors may result in warpage when the IC portion10A is at room temperature (e.g., about 25 degrees Celsius) as well as when the IC portion10A is exposed to high temperature (e.g., about 250 degrees Celsius or higher), as respectively shown inFIGS.3A and3B.

In some embodiments, at room temperature, an encountered warpage situation is such that the corner regions of the IC portion10A bend downwardly as indicated by the arrows A1, while the center region of the IC portion10A protrudes upwardly as indicated by the arrow A2. The warpage direction may change from the center region to the corner regions. In some embodiments, under a high temperature condition, the IC portion10A may have an irregular warpage profile as illustrated inFIG.7B. An encountered warpage situation may be such that the corner regions of the IC portion10A bend upwardly as indicated by the arrows A2, while the center region of the IC portion10A is recessed downwardly as indicated by the arrow A1.

Due to the curved plane of the IC portion10A, it is difficult to bond all of the conductive terminals150to the respective contact pads of another package component (not shown), because some conductive terminals150would not contact the respective contact pads of package component. This may result in cold joints between the conductive terminals150and the contact pads of package component, and the cold joints result in defective semiconductor structure and reduce yields of the semiconductor manufacturing. In some embodiments, in order to reduce and/or eliminate warpage of the IC portion10A, a warpage control portion is bonded to the IC portion10A for warpage management. Details of which will be discussed hereinafter.

FIGS.4A-4Billustrate schematic cross-sectional views of a warpage control portion at various stages of fabrication, in accordance with some embodiments. Referring toFIG.4A, a first dielectric layer220is formed over a substrate210. For example, the substrate210is a silicon substrate. In some embodiments, the substrate210may include another elementary semiconductor, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may be used. In some embodiments, the substrate210is made of glass, ceramic, metal, or other suitable materials which have a certain degree of rigidity.

In some embodiments, the first dielectric layer220is an oxide layer. In some embodiments, the first dielectric layer220may be formed of non-organic materials such as silicon oxide, un-doped silicate glass, silicon oxynitride, and the like. Other suitable dielectric materials (e.g., polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), combinations of these, or the like) may also be used. For example, the interface between the substrate210and the first dielectric layer220may be silicon-to-silicon, silicon-to-oxide, oxide-to-oxide, or any other covalent bonding mechanism. The thickness210tof the substrate210and the thickness220tof the first dielectric layer220may be changed to control the warpage of the warpage control portion as will be explained later in other embodiments.

Referring toFIG.4B, a second dielectric layer222and a metal pattern224A which is embedded in the second dielectric layer222are formed on the first dielectric layer220. In some embodiments, a dielectric material is formed by suitable fabrication techniques such as spin-on coating, CVD, PECVD, lamination, or other suitable deposition process, and then a portion of the dielectric material is removed to form the second dielectric layer222with openings by using lithography and/or etching, laser drilling, or other suitable removal process. The second dielectric layer222may be referred to as a patterned dielectric layer.

The first dielectric layer220and the second dielectric layer222may be made of one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, combinations of these, etc. In other embodiments, the first dielectric layer220and/or the second dielectric layer222may be made of a polymer such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), combinations of these, or the like. In some embodiments, the first dielectric layer220and the second dielectric layer222are both oxides, and an etch stop layer (not shown) is interposed therebetween.

Next, the metal pattern224A may be formed in the openings of the second dielectric layer222. For example, a seed layer is conformally formed on the second dielectric layer222, and the conductive material (e.g., copper, copper alloy, aluminum, aluminum alloy, or combinations thereof) is filled in the openings using plating or other suitable process. A planarization process (e.g., a CMP, mechanical grinding, etc.) may be performed such that the top surface of the second dielectric layer222and the top surface of the metal pattern224A are substantially level. In some embodiments, additional second dielectric layer222and additional metal pattern224A may be repeatedly formed to control the warpage of the warpage control portion as will be described later in accompanying withFIGS.9-10. The metal pattern224A may include inclined sidewalls or vertical sidewalls, which depend on the process requirements. The specific configuration of the metal pattern224A is based on the warpage characteristics of the IC portion to be bonded, and the details with respect to the configuration of the metal pattern224A will be described later in other embodiments.

In some embodiments, a bonding layer (15; as shown inFIG.5) is optionally formed on the second dielectric layer222and the metal pattern224A. For example, if the bonding layer is formed during fabricating the IC portion10A, then the bonding layer may not be formed on the second dielectric layer222and the metal pattern224A. If the bonding layer is absence in the IC portion10A, then the forming process of the bonding layer is performed on the second dielectric layer222and the metal pattern224A. In some embodiments, the bonding layers are formed both of in the IC portion10A and the warpage control portion20A. Up to here, the warpage control portion20A of the semiconductor structure is fabricated.

FIG.5illustrates a schematic cross-sectional view of a semiconductor structure including an IC portion and a warpage control portion in accordance with some embodiments. Referring toFIG.5, a semiconductor structure S1including the IC portion10A and the warpage control portion20A stacked upon one another is provided. For example, the IC portion10A and the warpage control portion20A are bonded together by such as a thermal bonding process, a gluing process, a pressure bonding process, a combination thereof, or other types of bonding processes. In some embodiments, the IC portion10A and the warpage control portion20A are bonded together through a bonding layer15interposed therebetween. For example, the bonding layer15is an oxide based layer of dielectric to form an oxide-to-oxide bonding (oxide fusion bonding) to another portion in the subsequent process. An anneal process may be performed after the bonding process to increase bonding strength between the IC portion10A and the warpage control portion20A. In other embodiments, the bonding layer15is an adhesive layer or a glue layer for physical connection. For example, the bonding layer15includes a die attach film that may be made of epoxy resin, phenol resin, acrylic rubber, silica filler, combination thereof, or the like.

In some embodiments, the bottom surface15bof the bonding layer15is in physical contact with the second dielectric layer222and the metal pattern224A of the warpage control portion20A. The metal pattern224A of the warpage control portion20A may be electrically isolated by the dielectric materials. For example, the sidewalls of the metal pattern224A are covered by the second dielectric layer222, the bottom surface of the metal pattern224A is covered by the first dielectric layer220, and the top surface of the metal pattern224A is covered by the bonding layer15. The metal pattern224A of the warpage control portion20A may be electrically floating in the semiconductor structure S1. The metal pattern224A may be referred to as a dummy pattern or dummy conductive features. In some embodiments, the top surface15aof the bonding layer15is connected to the IC portion10A. For example, the insulating layer130and the die attach films DAF that are substantially leveled with the insulating layer130are in physical contact with the top surface15aof the bonding layer15. In some embodiments in which the die attach films DAF are omitted, the top surface15aof the bonding layer15is in physical contact with the insulating layer130and the semiconductor substrate122of the IC component120.

In some embodiments, bonding of the IC portion10A and the warpage control portion20A may be at wafer level, and after the bonding step, the resulting structure is singulated to form individual semiconductor structures S1. For example, the singulation involves cutting through successive layers, such as the passivation layer146, the redistribution structure110, the insulating layer130, the bonding layer15, the second dielectric layer222, the first dielectric layer220, and the substrate210. Thus, after the singulation, the sidewalls of these successive layers may be substantially leveled with one another.

In some embodiments, one of the functions of the warpage control portion20A is to control the warpage of the IC portion10A. As mentioned above, the IC portion10A may undergo warpage due to several factors (e.g., CTE mismatch, excessive thermal stress, temperature fluctuations, and/or the like). As is known, the warpage of the IC portion may adversely impact electrical performance. In addition, low planarity (or severely warped) of the IC portion may cause stress to packaged IC components and interferes with the singulation process. By attaching the warpage control portion20A to the IC portion10A, the warpage problem of the IC portion10A may be solved. For example, the warpage control portion20A bonded to the IC portion10A has an inherent stress, which may cause the IC portion10A to warp against the existing warpage direction, hence compensating for the existing warpage. In some embodiments, the warped IC portion10A is to be flattened by bonding to the warpage control portion20A before being sawed into individual semiconductor structures S1to enable proper sawing and good package planarity.

FIG.6illustrates a schematic top view of a warpage control portion inFIG.5in accordance with some embodiments. Referring toFIGS.5and6, the metal pattern224A may include a plurality of first features2241formed in the openings of the second dielectric layer222. For example, the first features2241are arranged in an array. In some embodiments, the first features2241are arranged in a linear array. Alternatively, the first features2241are arranged such as in a non-linear manner, a curvilinear manner, a geometric-sequence manner, or other uniform distribution manner. In other embodiments, the first features2241are arranged such as in a uniform distribution, in a random manner, or in otherwise irregular distribution.

Although the illustrated first features2241are all rectangular in shape in the top view, it is understood that the first features2241in other embodiments may have any shape, such as, circular, oval, triangular, square, cross, polygonal, combination of these, etc. In some embodiments, the first features2241include dummy metal vias, dummy metal lines, and/or dummy metal pads. The respective first feature2241may be spatially apart from one another. For example, the first features2241are not electrically connected and may be isolated from one another. In some embodiments, the metal lines of a certain line width W have a certain amount of spacing S between them. The first features2241may be designed with distributed lines and spaces so as to conform to design rules and provide the desired warpage effect and level. In some embodiments, the line width W of the respective first feature2241is about 15 μm or may be less than 15 μm. By way of example, the line width W is in a range of about 0.3 μm and about 15 μm. In some embodiments, the line spacing S of the adjacent first features2241is at least 0.3 μm or greater than 0.3 μm.

In some embodiments, the first features2241are formed in accordance with design rules where the spacing S between the metal lines is varied to achieve the desired global pattern density. For example, the global pattern density ranges from about 10% to about 80%. In some embodiments, the first features2241are laid out in a window in which the local pattern density is in a range of about 10% and about 90%. In some embodiments, a density difference between windows is substantially equal to or less than 40%, where the respective window may have a length and width of 250 μm by 250 μm. It is appreciated that the dimensions recited herein are merely examples, and may be changed if different formation technologies are used, or if simulations reveal that different dimensions are preferred.

The formation of the first features2241may increase or reduce stress by redistributing local stresses to specific region(s) of the warpage control portion20A. For example, the first features2241are located in the region(s) selected to more effectively control warping of the IC portion10A. In some embodiments, the warpage control portion20A includes a first region R1and a second region R2surrounding the first region R1. The first features2241may be distributed within the first regions R1, and the first regions may correspond to the regions of the IC components120in the IC portion10A. For example, the orthographic projection area of the respective IC component120may substantially overlap the corresponding first region R1. In other embodiments, the orthographic projection area of the IC component120partially overlaps the first region R1. Alternatively, the orthographic projection area of the IC component120is fully staggered from the first region R1. The distribution area of the first region R1may be determined based on warpage profiles so as to counteract or compensate an undesirable warpage of the IC portion10A. The details with respect to the warpage control will be described later in other embodiments.

In some embodiments, the metal pattern224A includes at least one second feature2242disposed within the second region R2. For example, the second region R2is a border region of the warpage control portion20A in the top view. For example, the first features2241are limited to being in the first regions R1that correspond to the IC components120, and the second features2242in the second region R2are located at the periphery of the warpage control portion20A. The first features2241and the second features2242may not have electrical functions in the semiconductor structure S1and may not be electrically connected to the overlying IC portion10A. In some embodiments, the second features2242are formed of same conductive materials as that of the first features2241, and the second features2242may be formed substantially concurrent with formation of the first features2241. In some embodiments, a plurality of the second features2242is disposed in a diagonal arrangement in the second region R2. Other arrangement may be used to form the second features2242.

In some embodiments, the second feature2242may function as an alignment mark so that the second feature2242may be referred to as the alignment feature. The second features2242may be formed into blank areas on the warpage control portion20A inside scribed lines (not shown) so that after the singulation, the second features2242are remained in the warpage control portion20A. In some embodiments, the second features2242may be formed in edge areas overlapping the scribed lines (not shown) so that the second features2242are cut through and partially remained in the warpage control portion20A after the singulation. In other embodiments, the second features2242may be formed in areas outside the scribed lines (not shown) so that the second features2242are removed after the singulation. The second feature2242serving as the alignment mark may be of a geometrical shape (e.g., triangular, rectangular, square, cross, circular, oval, polygonal), or any suitable shape. The illustrated second features2242are not intended to be limiting as the second features2242may have any number, shape, or size. It is appreciated that the metal pattern224A shown inFIGS.5-6is merely an example, and should not limit the scope of the present disclosure.

FIGS.7A-7Billustrate schematic views of assembling of a semiconductor structure in accordance with some embodiments. It is noted that the degree of warpages shown inFIGS.7A-7Bis exaggerated, and the details of the IC portion are omitted for illustrative purposes. Referring toFIG.7A, the semiconductor structure S1includes the IC portion10A and the warpage control portion20A. In some embodiments, the IC portion10A presents a concave warpage (i.e. smiling profile), and the warpage control portion20A with the predetermined convex warpage (i.e. crying profile) may be fabricated to counteract an internal stress leading to concave warpage of the IC portion10A, thereby reducing manufacturing defects.

In some embodiments, the warpage characteristics of the IC portion10A are determined prior to bonding. For example, the height difference H1in the bonding surface BS of the IC portion10A (shown inFIGS.2A-2B) is estimated through simulation or experiments. In some embodiments, the warpage simulation is performed based on the design of the IC portion10A to generate a contour diagram of the warpage profile. By analyzing the warpage of the IC portion10A, the configuration of the warpage control portion20A may be estimated. For example, the pattern density, line width and spacing of the metal pattern of the warpage control portion20A may depend on the warpage to be compensated for. In some embodiments, the warpage of the warpage control portion20A may be achieved by forming the dielectric materials (e.g., the first dielectric layer220and/or the second dielectric layer222shown inFIG.3B) on the substrate210, with the dielectric materials having an inherent stress, which provides the desired warpage effect and level. In some embodiments, the thickness of the substrate210may be determined based on the warpage characteristics of the IC portion10A to permit tuning of the warping control of the IC portion10A.

Referring toFIG.7B, the semiconductor structure S1includes the IC portion10A and the warpage control portion20A. In some embodiments, the IC portion10A presents a convex warpage (i.e. crying profile) and the warpage control portion20A may have a concave warpage (i.e. smiling profile), so that the bonding of the IC portion10A and the warpage control portion20A may achieve the flatness requirements of the semiconductor structure. As discussed above, the configuration of the warpage control portion20A may vary due to warpage profile. In some embodiments, the simulated warpage characteristics of the IC portion10A are used to determine a desired warpage degree of the warpage control portion20A that is used to bond the IC portion10A.

For example, the metal pattern that fills the openings of the second dielectric layer may have the effect of inducing concave warpage. A greater pattern density of the metal pattern of the warpage control portion20A may result in a greater warpage compensation effect. The pattern density may be referred to as a density of the first features occupying a region of the warpage control portion in the top view. The pattern density may be a ratio of the area occupied by the first features in the first regions with respect to the total area of the warpage control portion. The dielectric materials (e.g., the first dielectric layer220and/or the second dielectric layer222shown inFIG.3B) formed on the substrate210may be selected to cause the concave warpage or the convex warpage of the warpage control portion20A. In some embodiments, the dielectric materials of the warpage control portion20A are selected to relieve the bending force provided by the metal pattern222of the warpage control portion20A. In some embodiments, the warpage control portion20A having thicker dielectric materials is prone to warpage resulting from the stress imposed by these dielectric materials. In some embodiments, thickness of the substrate210is changed to control the warpage of the warpage control portion20A. For example, the thicker substrate210is used to reduce the concavity of the warpage control portion20A.

In the examples described above, the warpage of the IC portion10A may be symmetrical, and the warpage control portion20A may also be symmetrical. In some embodiments, due to a complicated semiconductor processing, the IC portion10A presents more complex warpage profiles. In such embodiments, the warped IC portion10A may be simulated and analyzed. Based on the simulation results (e.g., three-dimensional contour diagrams shown inFIGS.3A-3B), warpage compensation may be tailored to form the warpage control portion20A having the specific configuration that corresponds to the warped IC portion. Accordingly, the warpage of the IC portion10A is compensated by the preplanned internal stress of the warpage control portion20A so as to prevent the warpage of semiconductor structure S1as a whole.

FIG.8illustrates a schematic cross-sectional view of a semiconductor structure including an IC portion and a warpage control portion in accordance with some embodiments andFIGS.9A-9Billustrate schematic top views of a warpage control portion inFIG.8with different configurations in accordance with some embodiments. Throughout the various views and illustrative embodiments of the present disclosure, like reference numbers are used to designate like elements.

Referring toFIG.8, a semiconductor structure S2including the IC portion10B and the warpage control portion20B attached to the IC portion10B. The semiconductor structure S2may be similar to the semiconductor structure S1described inFIG.5. The differences between the semiconductor structures S1and S2include that a single IC component120is disposed therein, and the topmost layer114t′ of the conductive feature114′ of the redistribution structure110′ is correspondingly modified. Again, the number of the IC components120is not limited in the disclosure, and examples are provided for illustrative purposes only.

The warpage control portion20B may be similar to the warpage control portion20A of the semiconductor structure S1described inFIG.5, except that the configuration of the metal pattern224B is modified. For example, referring toFIGS.8and9A, the warpage control portion20B includes the first region R1, a third region R3and a fourth region R4located at two opposite sides of the first region R1, and the second region R2surrounding the first region R1, the third region R3, and the fourth region R4. The first features2241may be distributed within the first regions R1that correspond to the region of the IC component120in the IC portion10B.

The metal pattern224B may further include a plurality of third features2243distributed within the third region R3, and a plurality of fourth features2244distributed within the fourth region R4. The third features2243and the fourth features2244may be generated by a rule-based procedure. In some embodiments, the pattern density of the first features2241in the first region R1is sparser than the pattern density of the third features2243in the third region R3. In some embodiments, the pattern density of the first features2241in the first region R1is also sparser than the pattern density of the fourth features2244in the fourth region R4. In some embodiments, the pattern densities of the third features2243and the fourth features2244are substantially the same. Alternatively, the pattern density of the third features2243in the third region R3may be denser or sparser than that of the fourth features2244in the fourth region R4.

Referring toFIG.9Bwith reference toFIG.8, another configuration of the warpage control portion20C is provided. For example, the pattern density of the first features2241in the first region R1is denser than the pattern density of the third features2243in the third region R3. In some embodiments, the pattern density of the first features2241in the first region R1is also denser than the pattern density of the fourth features2244in the fourth region R4. In some embodiments, the pattern densities of the third features2243and the fourth features2244are substantially the same. Alternatively, the pattern density of the third features2243in the third region R3may be denser or sparser than that of the fourth features2244in the fourth region R4. In other embodiments, the pattern density of the first features2241in the first region R1is between the pattern density of the third features2243and the pattern density of the fourth features2244. For example, the pattern density of the first features2241in the first region R1is denser than the pattern density of the third features2243in the third region R3, but sparser than the pattern density of the fourth features2244in the fourth region R4. Alternatively, the pattern density of the first features2241in the first region R1may be sparser than the pattern density of the third features2243in the third region R3, but denser than the pattern density of the fourth features2244in the fourth region R4.

The second features2242may be distributed within the second region R2where may be a border region of the warpage control portion20B in the top view. In some embodiments, the second features2242′ function as the alignment marks and may be disposed aside the fourth region R4and the third region R3. For example, the second features2242′ are disposed at the middle of the periphery of the warpage control portion20C in the top view. Although the illustrated second features2242′ are cross-shaped marks, it is understood that the second features in other embodiments may have any shape and should not limit the scope of the present disclosure. It is appreciated that the characteristics (e.g., density, dimension, shape, arrangement, etc.) of the metal pattern (224B,224C) illustrated herein are merely examples, and may be changed if other type of IC portion is to be bonded.

FIGS.10-11illustrate schematic cross-sectional views of variations of a semiconductor structure in accordance with some embodiments. Throughout the various views and illustrative embodiments of the present disclosure, like reference numbers are used to designate like elements. Referring toFIG.10, a semiconductor structure S3including the IC portion10A and the warpage control portion20D attached to the IC portion10A. The semiconductor structure S3may be similar to the semiconductor structure S1described inFIG.5, except that the warpage control portion20D of the semiconductor structure S3includes a plurality of metal patterns stacked upon one another. For example, after forming the metal pattern224A in the second dielectric layer222as described inFIG.4B, additional dielectric layer(s)226and additional metal pattern(s)228are subsequently formed over the dielectric layer222and the metal pattern224A. The forming processes of the additional dielectric layer(s)226and the additional metal pattern(s)228may be similar to the forming processes of the second dielectric layer222and the metal pattern224A, so the detailed descriptions are omitted for the sake of brevity. For example, as the number of dielectric layers and metal pattern formed over the substrate210increase, the bending forces provided by these layers result in significant warpage of the warpage control portion20D. The numbers of the additional dielectric layer(s)226and the additional metal pattern(s)228are dependent upon the designs of the warpage control portion20D and the IC portion10A that is to be bonded.

In some embodiments, the pattern distribution of the additional metal pattern(s)228may be different from that of the underlying metal pattern224A. In some other embodiments, the additional metal pattern(s)228has a pattern distribution similar or same as the pattern distribution of the underlying metal pattern224A. Any combination of pattern distribution types for the various metal patterns may be used. The additional metal pattern(s)228may be or may not be in physical contact with the underlying metal pattern224A. In some embodiments, the additional metal pattern(s)228and the underlying metal pattern224A are staggered from one another. For example, the metal pattern224A and the additional metal pattern(s)228are electrically isolated from one another. The thickness of the additional dielectric layer(s)226may be adjusted to exert the appropriate amount of counteracting stress. In some embodiments, the metal pattern224A is replaced with the metal pattern224B or224C as described in conjunction withFIGS.8and9A-9B. In some embodiments, the IC portion10A is replaced with the IC portion10B as illustrated in conjunction withFIG.8. It is appreciated that the IC portion may be replaced with other types of device (e.g., system on integrated circuit (SoIC) devices, system on a chip (SoC), package structure, or the like).

Referring toFIG.11, a semiconductor structure S4including the IC portion10A and the warpage control portion20E attached to the IC portion10A. The semiconductor structure S4may be similar to the semiconductor structure S3described inFIG.5, except for the configuration of the warpage control portion20E. For example, the warpage control portion20E includes a first tier T1and a second tier T2bonded to the first tier T1. The configuration of the first tier T1may be similar to that of the warpage control portion20A described inFIG.4B. The second tier T2may be bonded to the first tier T1opposite to the IC portion10A. The bonding of the first tier T1and the second tier T2may include adhesive bonding, fusion bonding via oxide-to-oxide bond, bonding by a glue medium such as benzocyclobutene (BCB), and the like. In some embodiments, the second tier T2is bonded to the substrate210of the first tier T1via a bonding layer16. The material of the bonding layer16may be similar to the material of the bonding layer15, and the detailed descriptions are not repeated for the sake of brevity.

The second tier T2may include a substrate310, a first dielectric layer320formed on the substrate310, a second dielectric layer322formed on the first dielectric layer320, a first metal pattern324embedded in the second dielectric layer322, a third dielectric layer326formed on the second dielectric layer322, and a second metal pattern328embedded in the third dielectric layer326. The substrate310may be similar to the substrate210. In some embodiments, the substrate210of the first tier T1and the substrate310of the second tier T2are of different materials. In some embodiments, the substrate210and the substrate310may have different thicknesses. The substrate210may be thicker or thinner than the substrate310, and the thicknesses of the substrates may depend on the warpage to be compensated for. The stack of dielectric layers (e.g.,320,322, and326) as well as the bonding layer16may be interposed between the substrate210of the first tier T1and the substrate310of the second tier T2. The materials and the thicknesses of the stack of dielectric layers (e.g.,320,322, and326) as well as the bonding layer16may be changed based on warpage design requirements. The first metal pattern324may be similar to the metal pattern (224A,224B, or224C). The second metal pattern328may be similar to the additional metal pattern228. In some embodiments, the configuration of the second tier T2may be similar to that of the warpage control portion20D described inFIG.10. Other configuration(s) may be used as long as the warpage control portion20E exerts the appropriate amount of counteracting stress.

FIG.12illustrate a schematic cross-sectional view of an application of a semiconductor structure in accordance with some embodiments. Referring toFIG.12, a component assembly SC including a first component C1and a second component C2disposed over the first component C1is provided. The first component C1may be or may include an interposer, a package substrate, a printed circuit board (PCB), a printed wiring board, and/or other carrier that is capable of carrying integrated circuits. The second component C2may be or may include a semiconductor structure S5.

For example, the semiconductor structure S5includes an IC portion10C and the warpage control portion20A attached to the IC portion10C. In some embodiments, the IC portion10C includes a carrier die L1and die stack L2stacked on and electrically connected to the carrier die L1. In some embodiments, the carrier die L1may be configured to perform read, program, erase, and/or other operations, and the die stack L2may be a memory stack including memory dies stacked upon one another and programmed by the carrier die L1. For example, the carrier die may be or may include a system-on-a-chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), or other types of IC components. The die stack L2may include dynamic random access memory (DRAM) dies, static random access memory (SRAM) dies, synchronous dynamic random access memory (SDRAM) dies, NAND flash dies, or other types of IC components.

In some embodiments, the carrier die L1includes a semiconductor substrate410having semiconductor devices formed thereon, a redistribution structure420disposed over the front side410aof the semiconductor substrate410to be electrically connected to the semiconductor devices, a plurality of through substrate vias (TSVs)430penetrating through the semiconductor substrate410to be electrically connected to the redistribution structure420, a bonding dielectric layer442disposed on the back side410bof the semiconductor substrate410, and a plurality of bonding pads440embedded in the bonding dielectric layer442and electrically connected to the TSVs430. The conductive terminals150are formed on the redistribution structure420opposite to the semiconductor substrate410.

The die stack L2includes a plurality of tiers (e.g., M1-M4) stacked upon one another, where each tier may include an IC component (e.g.,520,620) laterally covered by the insulating layer130. The IC component in the overlying tier is in physical and electrical contact with the IC component in the underlying tier. The IC component620at the topmost tier M4is attached to the warpage control portion20A via the bonding layer15. The IC component620may be similar to the IC component120. The bottommost IC component520may be similar to the IC component620at the topmost tier M4, except that the IC component520includes through substrate vias (TSVs)522. For example, the respective TSV522of the IC component520penetrates through the semiconductor substrate122to be in physical and electrical contact with the interconnect structure124. In some embodiments, the bonding dielectric layer442is interposed between the adjacent tiers (e.g., M1and M2, M2and M3, or M3and M4). A plurality of bonding pads440may be embedded in each of the bonding dielectric layers442to be physically and electrically connected to the TSVs522of the IC component520at the underlying tier and also connected to the bonding connectors1243of the interconnect structure124at the overlying tier. It is appreciated that the four-tier stack is provided for illustrative purposes, and other embodiments may utilize fewer or additional tiers in the die stack.

It is noted that the IC portion10C and the warpage control portion20A may be replaced with any IC portion and warpage control portion discussed above. The second component C2mounted on the first component C1may be similar to the semiconductor structure (e.g., S1, S2, S3, S4) described above. For example, one or more semiconductor structures described above may be electrically coupled to the first component C1through a plurality of terminals CT. The terminals CT may be the conductive terminals150. In the case of processing, the temperature is risen such that the terminals CT is deformed and bonded to the contact pads (not shown) of the first component C1. By using the warpage control portion, the warpage of the bonded package components (C1and C2) may not occur. In some embodiments, an underfill layer UF is formed between the gap of the first component C1and the second component C2to at least laterally cover the terminals CT. Alternatively, the underfill layer UF is omitted.

In some other embodiments, the second component C2mounted on the first component C1may be an integrated fan-out (InFO) package including at least one semiconductor structure (e.g., S1-S5) packaged therein. For example, the second component C2includes a plurality of semiconductor structures (e.g., any combinations of semiconductor structures S1-S5) disposed side by side and surrounding by a packaging encapsulation (not shown; e.g., a molding compound). Other packaging techniques may be used to form the component assembly SC, which are not limited in the disclosure. For example, the component assembly SC is formed using a wafer level packaging (WLP), a chip-on-wafer-on-substrate (CoWoS) process, a chip-on-chip-on-substrate (CoCoS) process, etc. The component assembly SC may be a part of an electronic system for such as computers (e.g., high-performance computer), computational devices used in conjunction with an artificial intelligence system, wireless communication devices, computer-related peripherals, entertainment devices, etc. It should be noted that other electronic applications are also possible.

According to some embodiments, a semiconductor structure includes an integrated circuit (IC) component, an insulating layer laterally encapsulating the IC component, a redistribution structure disposed on the insulating layer and the IC component, and a warpage control portion coupling to a back side of the IC component opposite to the redistribution structure. The redistribution structure is electrically connected to the IC component. The warpage control portion includes a substrate, a patterned dielectric layer disposed between the substrate and the IC component, and a metal pattern embedded in the patterned dielectric layer and electrically isolated from the IC component.

According to some alternative embodiments, a semiconductor structure includes an encapsulated integrated circuit (IC) component, a redistribution structure overlying and bonded to the encapsulated IC component, and a warpage control portion underlying the encapsulated IC component. A bonding interface of the redistribution structure and the encapsulated IC component is substantially flat. The warpage control portion includes a first substrate, a first patterned dielectric layer disposed between the first substrate and the encapsulated IC component, and a first metal pattern laterally covered by the first patterned dielectric layer and electrically floating in the warpage control portion.

According to some alternative embodiments, a manufacturing method of a semiconductor structure includes at least the following steps. An intermediate structure is formed, where the intermediate structure comprises an integrated circuit (IC) component, an insulating layer laterally covering the IC component, and a redistribution structure overlying the IC component and the insulating layer. Warpage characteristics of the intermediate structure are analyzed. A warpage control portion based on the warpage characteristics of the intermediate structure is formed, and this step includes embedding a metal pattern in a patterned dielectric layer over a substrate, where the metal pattern is electrically isolated from the IC component. The intermediate structure is flattened by coupling a backside of the IC component of the intermediate structure to the warpage control portion.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.