Patent ID: 12217687

DETAILED DESCRIPTION

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure. It will be understood, however, by those skilled in the art that the disclosed aspects may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail to not obscure the subject matter disclosed herein.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment disclosed herein. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” or “according to one embodiment” (or other phrases having similar import) in various places throughout this specification may not necessarily all be referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments. Additionally, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Also, depending on the context of discussion herein, a singular term may include the corresponding plural forms and a plural term may include the corresponding singular form.

Similarly, a hyphenated term (e.g., “two-dimensional,” “pre-determined,” “pixel-specific,” etc.) may be occasionally interchangeably used with a corresponding non-hyphenated version (e.g., “two dimensional,” “predetermined,” “pixel specific,” etc.), and a capitalized entry (e.g., “Counter Clock,” “Row Select,” “PIXOUT,” etc.) may be interchangeably used with a corresponding non-capitalized version (e.g., “counter clock,” “row select,” “pixout,” etc.). Such occasional interchangeable uses shall not be considered inconsistent with each other.

It is further noted that various figures (including component diagrams) shown and discussed herein are for illustrative purposes only, and are not drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, if considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and/or analogous elements.

The terminology used herein is for the purpose of describing some example embodiments only and is not intended to be limiting of the claimed subject matter. It will be further understood that the terms “comprise,” “include,” “have,” and their variations, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

The terms “first,” “second,” etc., as used herein, are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) unless explicitly defined as such. Furthermore, the same reference numerals may be used across two or more figures to refer to parts, components, blocks, circuits, units, or modules having the same or similar functionality. Such usage is, however, for simplicity of illustration and ease of discussion only; it does not imply that the construction or architectural details of such components or units are the same across all embodiments or such commonly-referenced parts/modules are the only way to implement some of the example embodiments disclosed herein.

As used herein, the terms “circuit” and “circuitry” can refer to any combination of dedicated logic, programmable logic, tangible memories (e.g., Read Only Memories, Random Access Memories, magnetic discs, optical discs), and computer/processor/controller based hardware operating upon any combination of software and firmware disposed in a memory capable of being accessed by the computer/processor/controller. For example, “circuitry” can refer to an Application Specific Integrated Circuit (ASIC), a microprocessor based system operating upon software/firmware residing in a Read Only Memory and manipulating data in a Random Access Memory, or a combination thereof.

As customary in the field, some embodiments are described and illustrated in the accompanying drawings in terms of functional blocks, units, parts, and/or modules. Those skilled in the art will appreciate that these blocks, units, parts, and/or modules are physically implemented by electronic (or optical) circuits, such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, and the like, which may be formed using semiconductor-based fabrication techniques or other manufacturing technologies. In the case of the blocks, units, parts, and/or modules being implemented by microprocessors or other similar hardware, they may be programmed and controlled using software (e.g., microcode) to perform various functions discussed herein and may optionally be driven by firmware and/or software. It is also contemplated that each block, unit, part, and/or module may be implemented by dedicated hardware, or as a combination of dedicated hardware to perform some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) to perform other functions. Also, each block, unit, part, and/or module of some embodiments may be physically separated into two or more interacting and discrete blocks, units, parts, and/or modules without departing from the scope of the disclosure. Further, the blocks, units, parts, and/or modules of some embodiments may be physically combined into more complex blocks, units, parts, and/or modules without departing from the scope of the disclosure.

The term “about” or “approximately” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

For the purposes of this disclosure, the phrase “at least one of A and B” may be construed as A only, B only, or any combination of A and B. Also, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be construed as X only, Y only, Z only, or any combination of two or more of X, Y, and Z.

The term “and/or” includes all combinations of one or more of which associated configurations may define. For example, “A and/or B” may be understood to mean “A, B, or A and B.”

The term “display data” as used herein refers to any type of data that a display panel may visually represent on its screen. Some examples of the “display data” are a picture, photo, image, video, GUI, and the like.

The term “pixel data” as used herein refers to any type of data that is included in display data for unit pixels of a display panel.

The term “frame” as used herein refers to a single complete image that may be displayed on a screen.

The term “block averaging” as used herein refers to determining a stress value for a block (or a number of contiguous pixels) based on a number of sampled pixels over at least one frame.

The term “unbiased average” as used herein refers to determining an average value of a plurality of values (e.g., a number of stress values of contiguous pixels) based on a number of sampled pixels over at least one frame while removing bias that may accumulate due to quantization of data.

The term “dither value” as used herein refers to a parameter that may be used in a dithering process usable to remove bias. Some examples of the “dither value” include a uniform random variable.

The term “quantization” as used herein refers to the process of mapping values to a smaller set of discrete finite values by way of truncation or rounding. In practice, this can involve zeroing or removing some one or more of the least significant bits from a calculated number. By way of example and as will be explained below, a floor function can inherently quantize a value by rounding to a lower integer.

Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the disclosure, and should not be interpreted in an ideal or excessively formal sense unless clearly so defined herein.

Turning now to the figures,FIG.1is a schematic block diagram of a display apparatus100that uses stress compensation to compensates for luminance degradation according to an embodiment. As shown inFIG.1, the display apparatus100may include a source110, a stress compensation system120, and a display panel130with the source110communicatively coupled to the stress compensation system120, and the stress compensation system120communicatively coupled to the display panel130.

The source110may be a computer-based device capable of either storing display data pc(i.e., data capable of being displayed on any number of display devices) or receiving display data pcfrom an external device, such as a remote server or a broadcasting device, then forwarding the display data pcto the stress compensation system120. However, in other examples, the source110may take the form of dedicated electronics and/or optical systems capable of performing the same tasks.

The stress compensation system120ofFIG.1may be a combination of dedicated logic. computer-based memory, and processing systems capable of receiving display data pcfrom the source110or any other number of devices capable of providing display data pc, compensating the received display data to produce compensated display data pm,c, then providing the compensated display data pm,cto the display panel130. However, in other examples, the form of the stress compensation device120may vary so as to take the form of dedicated electronics only, a processor only based system only, or any number of hybrid systems as is discussed below.

The display panel130may be a display device capable of receiving the compensated display data pm,c, performing a number of intermediate operations on compensated display data pm,cusable to map the compensated display data pm,cto appropriate individual pixels incorporated into the display panel130, then display the compensated display data pm,c. While the display panel130may be an Organic Light Emitting Display (OLED) panel that includes a plurality of OLED-type pixels, the exact form of the display panel may vary to include any form of pixels whether or not such pixels are known to degrade with time and/or usage.

Turning now toFIG.2,FIG.2is a schematic functional flow diagram of the stress compensation system120ofFIG.1according to an embodiment. As illustrated inFIG.2, the stress compensation system120may include stress compensation circuitry210, block averaging circuitry220, adding circuitry230, a memory240, and degradation circuitry250. The block averaging circuitry220may include sampling circuitry222, stress circuitry224, and averaging circuitry226. The memory240may include a table242that stores a stress profile me for a display panel, such as the display panel130ofFIG.1.

Term “table” as used herein may be a table of numbers (or “stress values”) indicating (or from which may be inferred) the amount of stress each sub-pixel has been subjected to during the life of the display device. The term “stress” as used herein may be the total (time-integrated or accumulated) drive current that has flowed through each pixel or sub-pixel during the life of the display panel, e.g., the total charge that has flowed through each sub-pixel during the life of the display device. For example, a stress value may be a values that is proportional to a lifetime integral of driving current for a particular Organic Light Emitting Diode (OLED) pixel in a display panel. Similarly, a “stress profile” for a display panel may include values that are proportional to a lifetime integral of driving current for respective OLED pixels or for blocks of OLED pixels in the display panel.

In operation, the stress compensation circuitry210may receive display data pcfrom some form of data source, such as the source110ofFIG.1, and compensate the received display data pcto produce compensated display data pm,c. The compensated display data pm,c, in turn, may be provided to both the aforementioned display panel130ofFIG.1as well as to the block averaging circuitry220. In various examples, the stress compensation circuitry210may compensate the received display data pcby multiplying each item of pixel data with an inverse of the degradation value dcrepresenting a loss of efficiency of an individual pixel due to accumulated stress. However, in other embodiments the exact form of compensation may vary.

During operation, the sampling circuitry222may selectively sample the compensated display data pm,caccording to any of a number of various block averaging techniques. To explain such various technique,FIG.5is provided to demonstrate how the display panel130ofFIG.1may be conceptually divided into individual blocks B with each block B being a 4 by 4 array of contiguous pixels PX.FIG.5depicts blocks B of pixels according to a 4 by 4 array of contiguous pixels PX, in other embodiments each block B may be of different shapes and sizes. For instance, each block B may be a 2 by 2 array of contiguous pixels PX, an 8 by 8 array of contiguous pixels PX, a 2 by 8 array of contiguous pixels PX, a 1 by 8 array of contiguous pixels PX, and so on. Various sampling techniques usable by the sampling circuitry222are hereafter described.

Turning toFIGS.6A-6D, a first sampling technique is presented where sampling is sparce. Specifically, in the example ofFIGS.6A-6D, only every fourth pixel for a single line of pixels is sampled in a given frame. For instance, as depicted inFIG.6A, for a display having a height of M blocks of 4 by 4 pixels (or 4M pixels), for a first frame FRAME0, only the top left pixel0for the first row of blocks is sampled; for a second frame FRAME1, only the top left pixel0for the second row of blocks is sampled; and so on until the top left pixel0is sampled for every block of every row of a display. Similarly, as is depicted inFIG.6B, for a next sequence of M frames, in FRAME M, only pixel1for the first row of blocks is sampled; in FRAME M+1, only pixel1for the second row of blocks is sampled; and so on until pixel1is sampled for every block of every row of a display. This sampling technique continues as is shown inFIGS.6C and6Duntil every pixel (0through15) is sampled for every block in a display. According to the example ofFIGS.6A-6D, a total of 16M frames are used to sample every pixel location in the frame.

In still other embodiments, it is permissible that pixels be sampled less frequently. For example, instead of sampling pixels every frame, pixels may be sampled every other frame such that a total of 32M frames are used to sample every pixel. Similarly, in an embodiment where only every fourth frame is used for sampling, a total of 64M frames are used to sample every pixel. Conversely, sampling may occur at multiple block lines in a frame so that sampling occurs more frequently. For example, two samplings of different lines of 4×4 blocks might occur for a total of 8M frames to sample all pixel locations.

Turning toFIG.7,FIG.7depicts a variation of pixel sampling whereby, for each frame, four pixels (pixels0,2,8,10in the example ofFIG.7) are sampled per block for a row of pixels. Using this approach, a total of 4M frames may be used to sample every pixel for a display. Still further, within the scope of the disclosure, it is permissible to sample a single pixel for every block of a display for each frame thereby using sixteen (16) total frames to sample every pixel of a display. Similarly, within the scope of the disclosure, it is permissible to sample all of the pixels in a block for each frame thereby using M total frames to sample every pixel of a display.

Continuing, it is further contemplated within the scope of the application that sampling rates may change over time. For instance, after the first one-hundred hours of use, a sampling rate may change, i.e., increase or decrease, to reflect that degradation of a given pixel type is not linear over time and usage, and that lower sampling rates may be acceptable in case that pixels are less likely degraded for the same current stress as compared to another time.

Returning toFIG.2, as pixel data is sampled, the stress circuitry224may determine an amount of stress (or stress value) s for each pixel. In various embodiments, stress s may be determined using a look-up table. However, the exact approach to determining/calculating stress s may alternatively be determined using any number of mathematical operations, such as using a parametric equation. Each stress value s produced by the stress circuitry224may then be provided to the averaging circuitry226.

The averaging circuitry226may receive the various stress values s provided by the stress circuitry224to produce an average stress valuesfor a given block of contiguous pixels. It is contemplated that the averaging circuitry226may produce an average stress valuesfor a given block of contiguous pixels only after a sufficient number stress values s (i.e., 2 or more) are provided to the averaging circuitry226. For instance, turning toFIG.8A, in a number of embodiments an average stress valuesmay be produced once all sixteen (16) pixels for a 4 by 4 block of data are accumulated. Similarly, when using 8 by 8 blocks of data as shown inFIG.8B, an average stress valuesmay be produced once all sixty-four (64) pixels are accumulated according to a number of embodiments. However, it is to be appreciated that, instead of storing individual stress values s and later adding them together, it is contemplated that the averaging circuitry226may receive and accumulate the individual stress values s of the sampled pixels as they become available, which would reduce memory requirements. That is, for a given block of pixels, an incoming stream of stress values s for a block of pixels may be added to one another, e.g., using a single memory location or a single buffer thereby reducing memory usage. The number of pixels in a given block of data is hereby designated as nbwith nbbeing sixteen (16) for the 4 by 4 block ofFIG.8Aand nbbeing sixty-four (64) for the 8 by 8 block ofFIG.8B.

In various embodiments, the averaging circuitry226may produce an average stress valuesin case that pixel data for every pixel or a subset of pixels for a given block of contiguous pixels is sampled. For example, in view ofFIG.9A, it is possible to produce an average stress valuesusing pixel data for only four of sixteen (16) pixels. As shown inFIG.9A, while data from all sixteen (16) pixels of a 4 by 4 array are eventually used, four separate average stress valuessfor four respective pixels may be used in each of four update periods.FIG.9Bdepicts a variation of this approach whereby the various pixels used to produce an average stress valuesare spaced apart from one another within a block. To provide improved results, each pixel in each block can be sampled evenly over time. For the purpose of this disclosure, the number of sampled pixels from a block used to produce an average stress valuesis designated as nswith the range of nsbeing 1<ns≤nb.FIGS.10A and10Blikewise depict the idea that an average stress value s for an 8 by 8 block of sixty-four pixels may be produced in manners similar to that depicted inFIGS.9A and9B. In various embodiments, it may be useful for both nsand nbto be an integer power of two given that division using a number that is a power of two may be accomplished by a shift operation.

In view ofFIGS.8A-10B, it is to be appreciated that different stress values (i.e., 2 or more) used to calculate an average stress valuesmay be sampled from a common frame.

Returning toFIG.2, the averaging circuitry226may produce/calculate a quantized unbiased average stress value Scaccording to the following equation:

Sc=⌊(∑i=0ns-1⁢si)+Dns⌋(Equation⁢1)
where siis a stress value of an i-th sampled pixel data of a block, i is a natural number, nsis the number of pixels sampled per block, the brackets indicate a floor function, and D is a dither value defined by Equation 2:
D˜U[0,ns−1]  (Equation 2)
where U[0, ns−1] is an integer representing a uniform distribution between 0 and ns−1. Similarly, for the example ofFIG.9Awhere nsis 4 for each update of a stress profile, dither value D will take the form of a uniform distribution between 0 and 3. In this averaging process, as is stated above a dither value D may be added to compensate for biasing that results from the quantization of a floor function.

Turning now toFIG.3,FIG.3illustrates a schematic functional view of the averaging circuitry226ofFIG.2according to an embodiment usable to carry out the calculation of Equations 1 and 2 above. As shown inFIG.3, the averaging circuitry226may include summing circuitry310, dithering circuitry320, adding circuitry330, division circuitry340, and floor circuitry350.

In operation, the summing circuitry310may receive a number of stress values s for sampled pixel data of multiple pixels to produce a sum of stress values according to the following equation:

sum=(∑i=0ns-1si)(Equation⁢3)

For each sum of stress values calculated by the summing circuitry310, the dithering circuitry320may produce a dither value D according to Equation 2 above.

Thereafter, the adding circuitry330may add the sum calculated by the summing circuitry310and the dither value produced by the dithering circuitry320to produce a modified sum′ according to the equation:

sum′=(∑i=0ns-1si)+D(Equation⁢4)

Thereafter, the division circuitry340may divide the modified sum′ above by nsto produce a quotient that the floor circuitry350operates upon to produce/calculate the quantized unbiased average stress value Scof Equation 1.

While the averaging circuitry226ofFIG.3is shown according to one particular form, the arrangement of mathematical operations may vary in light that Equation 1 above may be rewritten according to equation 5:

Sc=⌊(∑i=0ns-1⁢si)ns+Dns⌋(Equation⁢5)

As can be seen above in Equation 5, the form of Equation 1 may take an alternate organization. Thus, the particular arrangement of circuitry310,320,330,340, and350inFIG.3may vary.

Returning again toFIG.2, the adding circuitry230may add each quantized unbiased average stress value Scfrom the averaging circuitry226to an appropriate entry of the stress profile mcof table242to produce an updated stress profile mc′ which is then stored in table242. Accordingly, over time each entry of the stress profile mcof table242may be updated such that individual entries of the stress profile mcmay be provided to the degradation circuitry250. The degradation circuitry250, in turn, may produce degradation values dcfor each pixel in display panel130, and provide these degradation values dcto the stress compensation circuitry210for future compensation, i.e., to produce the compensated display data pm,cdiscussed above. The degradation circuitry250may produce degradation values dcby any number of operations, such as by a simple inversion operation or by using a parametric equation. However, it is to be appreciated that the operations used by the degradation circuitry250may vary according to the particular form of data in a stress profile and the particular form of the stress compensation circuitry210. After the stress profile mcand degradation values de are updated, the stress compensation circuitry210may compensate received display data pc using the degradation values dc.

Turning now toFIG.4,FIG.4is a flowchart outlining operations for a display compensation method400according to an embodiment. While the various steps inFIG.4are organized according to a particular order for ease of explanation, it is to be appreciated that, in differing embodiments, the various steps S410to S480may occur in different orders or may occur concurrently. For example, it is possible for steps S430and S450to occur simultaneously or that step S450may occur before steps S430and S440.

Operation may begin at step S401and continue to step S410where display data, such as the display data pcdiscussed above with respect toFIGS.1-3above, is received by a device, such as the stress compensation circuitry210ofFIG.2. Control continues to step S420.

In step S420, the received display data pc for each pixel received in step S410may be compensated using a respective degradation value dcderived from a stress profile to produce compensated display data pm,c. Next, in step S430, the compensated display data pm,cproduced in step S420may be provided to a display panel, such as the display panel130ofFIG.1. Then, in step S440, the compensated display data pm,cmay be displayed. Control continues to step S450.

In step S450, the compensated display data pm,cmay be sampled by a device, such as the sampling circuitry222inFIG.2. As discussed above, sampling may take a number of different forms including the forms of sampling discussed with respect toFIGS.6A to10B. Next, in step S460, a stress value s may be determined for each sampled item of compensated display data. Control continues to step S470.

In step S470, a quantized unbiased average stress value Scis determined. The quantized unbiased average stress value Scof step S470may be determined consistent with the device ofFIG.3and Equations 1-5 discussed above while observing that variations consistent with the scope of the present disclosure may occur. Then in step S480, a stress profile, such as the stress profile mcdiscussed above with respect toFIG.2, may be updated along with respective degradation values dc. Thereafter, control jumps back to step S410where display data may continue to be received and subsequently compensated using an updated stress profile mc′ and degradation values dc.

While particular embodiments of the subject matter have been described herein, it is to be understood that other embodiments are within the scope of the following claims. In some cases, the actions set forth in the claims may be performed in a different order and still achieve desirable results. Additionally, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.

As will be recognized by those skilled in the art, the innovative concepts described herein may be modified and varied over a wide range of applications. Accordingly, the scope of claimed subject matter should not be limited to any of the specific teachings discussed above, but is instead defined by the following claims.