Patent ID: 12255113

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

An alignment method and an alignment device of the present disclosure are more particularly described in the following examples that are intended as illustrative only since numerous modifications and variation therein will be apparent to those skilled in the art. Those skilled in the art can understand the advantages and effects of the present disclosure from the content disclosed in this specification. The present disclosure can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present disclosure. In addition, it is stated in advance that the accompanying drawings of the present disclosure are merely schematic illustrations and are not drawn according to the actual size. The following embodiments will further describe the related technical content of the present disclosure in detail, but the disclosed content is not intended to limit the protection scope of the present disclosure. In addition, the term “or”, as used herein, should include any one or a combination of more of the associated listed items, as the case may be.

In the embodiment of the present disclosure, as shown inFIG.1,FIG.2, andFIG.3, a wafer100has a plurality of dicing roads120, and each of the dicing roads has a plurality of test keys121. The test keys121are used for wafer acceptance test (WAT), and each of the test keys121has at least two second bonding pads1211. The test keys121are present on the dicing road120before the wafer process, and the arrangement of the second bonding pads1211on the dicing roads120is determined before the wafer process. The present disclosure is not limited to the arrangement of the second bonding pads1211, so each of the second bonding pads1211on the dicing roads120may be arranged in an equidistant arrangement or an unequal arrangement.

In addition, in practice, the test keys121are usually designed with many components, such as a N-Metal-Oxide-Semiconductor (NMOS), a positive channel Metal Oxide Semiconductor (PMOS), a transistor, a resistor, a capacitor, a memory unit, a ring oscillator, etc., but the present disclosure is not limited to the test keys121.

In some embodiments, when the second bonding pads1211are arranged in the equidistant arrangement, any two of the second bonding pads1211adjacent to each other have a second fixed distance L2 there-between, and each of the second bonding pads1211and the chips110adjacent to sides thereof have a second distance R2 there-between.

For a description of the wafer coordinate information, please refer toFIG.1,FIG.3andFIG.6. The wafer100has a wafer coordinate system, and the wafer coordinate system is determined before the wafer process. The wafer coordinate system has a lateral direction (i.e., a X-axis direction inFIG.1) and a length direction (i.e., a Y-axis direction inFIG.1). A position of each of the chips110and the test keys121is defined on the wafer coordinate system. For example, a coordinate of a point where the X-axis and the −Y axis intersect is (X0, Y0) (not shown). Therefore, each of the chips110and the test keys121on the wafer100have a specific point coordinate. In addition, referring toFIG.6, each of the chips100has a chip coordinate system, and the chip coordinate system is determined before the wafer process. The chip coordinate system has a lateral direction (i.e., a X′-axis direction inFIG.6) and a length direction (i.e., a Y′-axis direction inFIG.6). A position of each of first bonding pads111on the chip110is defined on the chip coordinate system.

First Embodiment

Referring toFIG.1toFIG.4, when the wafer100passes the wafer acceptance test before the process is completed, the wafer100passing the test conditions is sent to the next process to start the manufacturing of the wafer110. The wafer100includes one or more chips110, and each of the chips110has a plurality of first bonding pads111on a surface thereof, and the first bonding pads111are used for wire bonding to connect the chips and a lead frame (not shown in the figure) with a metal wire. Each of the first boding pads111on the chips may be arranged in an equidistant arrangement or an unequal arrangement. When the chip110is manufactured, the arrangement of the first bonding pads111on the chip110is determined, so the present disclosure is no limited to the arrangement of the first bonding pads111. When the first bonding pads111are arranged in the equidistant arrangement, any two of the first bonding pads111adjacent to each other have a first fixed distance L1 there-between, and each of the first bonding pads1211and an edge of one of the chips110adjacent to sides thereof have a first distance R1 there-between (as shown inFIG.2).

Referring toFIG.4, a first embodiment of the present disclosure provides an alignment device1000. The alignment device1000includes at least two of probes2000, an image capture device3000, and a processor4000. The alignment device1000is used to confirm the position of at least one of the chips110on the wafer100. The two probes2000and the image capture device3000are both electrically connected to the processor4000. Wafer coordinate information can be pre-stored in the processor4000to determine the coordinate position of each of components on the wafer, that is, the wafer coordinate system and the chip coordinate system. The wafer coordinate information such as a size of the wafer, a width of the dicing road, a size of the chip, a position of the chip, a position of a welding point on the chip, a size of the test key, a position of the test key, but the present disclosure is not limited thereto. The wafer coordinate information records the coordinates of each of the chips110and the test keys121on the wafer100, and the coordinates of each of the first bonding pads111on the chips110, and the coordinates of the second bonding pads1211on the test keys121. The wafer coordinate information also includes the relative positions between the test keys.

Furthermore, as shown inFIG.5, the alignment device1000may further include a probe card5000, and the probe card5000is used to perform a wafer test on the chips110to confirm whether the first bonding pads111on the chip110can be electrically connected to the metal wire.

The positions of the test keys121and the second bonding pads1211on the wafer100are known before the wafer process is completed. After the chips110is manufactured, the arrangement of the first bonding pads111on the chips110and the positions of the chips110on the wafer100are also known. Therefore, the coordinates of each of the chips110and the test keys121on the wafer100, the coordinates of each of the first bonding pads111on the chips110and the coordinates of the second bonding pads1211on the test keys121are also known.

Second Embodiment

Referring toFIG.7,FIG.7is a flowchart of the alignment device1000executing an alignment method S100. The alignment method S100includes the following steps.

A step S10is implemented by providing a wafer100. The wafer100has wafer coordinate information.

A step S20is implemented by storing the wafer coordinate information of the wafer100in a processor4000for subsequent comparison. In addition, when the wafer coordinate information has been stored in the processor4000in advance, the step S20can be omitted.

A step S30is implemented by providing two probes2000. The two probes2000can be respectively aligned with the test keys121located on the dicing road120. More precisely, the two probes2000are capable of aligning the second bonding pads1211on any two of the test keys121, respectively. In addition, the two probes2000may also be paired with any two of the second bonding pads1211located on the same test key121as required by the situation. The two probes2000can selectively contact any two of the second bonding pads1211, or only directly above the second bonding pads1211.

Furthermore, in the step S30, when the two probes2000are respectively aligned with the second bonding pads1211located on the two test keys121, the image capturing device3000can capture images to assist the alignment, or the probe2000can touch down the test keys121to determine whether the probes2000are aligned above the second bonding pads1211by means of scratches generated on the test keys121after the probes2000touch down.

In a step S40, when two of the probes2000are aligned with any two of the test keys121, the image capture device3000obtains actual wafer information by capturing the relative positions of the two probes2000directly above the wafer100and the relative positions of the two probes2000and a body of the wafer100on the same plane. The actual wafer information records the relative positions of any two of the test keys121on the wafer100.

In a step S50, the actual wafer information captured by the image capture device3000will be sent to the processor4000and compared with the wafer coordinate information to help confirm whether the two probes2000are aligned directly above the two test keys121. When the actual wafer information is consistent with the wafer coordinate information, it is determined that the relative positions of any two of the probes2000on any two of the test keys121on the wafer100are consistent with the wafer coordinate information including the coordinates on the test keys121and is determined the position of a particular one of the chips110on the wafer100. More precisely, when the actual wafer information is consistent with the wafer coordinate information, it means that the two probes2000are located directly above the two test keys121, respectively, which means that the positions of the two test keys121on the wafer100are confirmed. That is to say, it is to confirm the positions of the two second bonding pads1211on the wafer100. The coordinates of the first bonding pads111, the second bonding pads1211, and the chips110on the wafer100have already been determined after the semiconductor etching. Therefore, when the positions of the two test keys121on the wafer are known, the positions of the first bonding pads111, the second bonding pads1211, and the chips110on the wafer100can be determined by the relative positions among the first bonding pads111, the second bonding pads1211, and the chips110.

Furthermore, in the step S50, in the process of comparing whether the actual wafer information is consistent with the wafer coordinate information, the two probes2000can confirm that they are located directly above the two second bonding pads1211by comparing whether the relative positions of the second bonding pads1211included in the actual wafer information match the actual positions of the second bonding pads1211included in the wafer coordinate information.

When the actual wafer information does not match the wafer coordinate information, it means that the two probes2000are not located directly above the two test keys121, respectively. Therefore, the step S30will be re-executed, so that the two probes2000are re-aligned and located directly above any two of the test keys121, until the actual wafer information and wafer coordinate information are consistent.

In a step S60, after the comparison between the actual wafer information and the wafer coordinate information is completed, a chip testing step may be implemented to determine whether the first bonding pads111on the chips110can be electrically connected to the metal wires. However, the step S60can also be omitted according to actual requirements.

Referring toFIG.5, andFIG.7, when the step S60is implemented, the probe card5000may only contact a part of a surface of the chip110. To be more precise, each of the probe heads5001of the probe card5000will only contact a probe needle region A1 on each of the chips110, while a rest of each of the chips110is a non-needle region A2. The non-needling area A2 can be used for subsequent wire bonding, and can also be used for other purposes.

The position of the probe needle region A1 on each of the chips is fixed, so the scratches caused by the test can be limited to the probe needle region A1. For example, as shown inFIG.6, the probe needle region A1 is formed with an offset on each of the first bonding pads111. Preferably, an area occupied by the probe needle region A1 on the first bonding pads111is within a range from 10% to 50%. For example, an offset side of the probe needle region A1 is located on a N side of the chip, and the probe needle region A1 may also be located on the a S/W/E side of the chip110according to actual requirements. As required by the situation, the present disclosure is not limited to the position of the offset side of the probe needle region A1 on the chip110. Accordingly, a single one of the chips110can not only be effectively aligned to determine each of the probe needle regions A1, but also each of the chips110can be wire-bonded.

Beneficial Effects of the Embodiments

In conclusion, one of the beneficial effects of the present disclosure is that the alignment method can confirm whether the probe is directly above the first bonding pads by comparing the wafer coordinate information with the actual information of the wafer, and then judge the positional relationship of the probe on the chip. When the probe is confirmed to be aligned directly over the first bonding pad, confirm the position of the second bonding pad located on the chip on the wafer to perform the chip test step by a coordinate relationship between the first bonding pad on the test keys and the second bonding pad on the wafer after the wafer is etched and formed. The alignment method of the present disclosure can not only effectively confirm the position of the second bonding pad of the wafer, reduce the misjudgment of the tester's eyesight, but also effectively reduce the scratches on the wafer and the resistance during wire bonding.

In addition, the alignment method of the present disclosure can further use each of the test keys that have passed the wafer acceptance test as an alignment reference, so that the probe head can be effectively aligned and pinned to the probe needle region on the chip. Accordingly, the alignment method does not need to add additional auxiliary components on the wafer to save costs while improving the accuracy of the probe head.

The foregoing description of the exemplary embodiments of the disclosure has been presented only for the purposes of illustration and description and is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible in light of the above teaching.

Although the present disclosure has been specifically described above with reference to the accompanying drawings and embodiments, it should be understood that the above description is not limited to the present disclosure in any form. Those skilled in the art can make modifications and changes of the present disclosure as required without departing from the essential spirit and scope of the present disclosure, and these modifications and changes all fall within the scope of the present disclosure.