Patent ID: 12253957

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present embodiments. It will be apparent, however, to one having ordinary skill in the art that the specific detail need not be employed to practice the present embodiments. In other instances, well-known materials or methods have not been described in detail in order to avoid obscuring the present embodiments.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present embodiments. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable combinations and/or sub-combinations in one or more embodiments.

FIG.1is a diagram illustrating an electronic device10according to an embodiment of the present invention, where the electronic device10comprises a host device50and a memory device100. The host device50may comprise: at least one processor52configured to control operations of the host device50. Examples of the host device50may include, but are not limited to: a smartphone, a tablet computer, a wearable device, a personal computer such as a desktop computer and a laptop computer, an imaging device such as a digital still camera or a video camera a game console, a car navigation system, a printer, a scanner or a server system. Examples of the memory device100may include, but are not limited to: a portable memory device (such as a memory card conforming to SD/MMC, CF, MS, XD or UFS specifications), a solid state drive (SSD) and various embedded storage device (such as an embedded storage device conforming to UFS or EMMC specifications).

According to various embodiments, the memory device100may comprise a controller such as a memory controller110, and may further comprise a non-volatile (NV) memory120. The NV memory120is configured to store information. The NV memory120may comprise at least one NV memory element (e.g. one or more NV memory elements), such as a plurality of NV memory elements122_1-122_N. For example, the NV memory120may be a flash memory, and the NV memory elements122_1-122_N may be a plurality of flash memory chips or a plurality of flash memory dies, respectively, but the present invention is not limited thereto. In addition, the NV memory120may comprise memory cells having a two-dimensional structure or may comprise memory cells having a three-dimensional structure.

As shown inFIG.1, the memory controller110may comprise a processing circuit such as a microprocessor112, a storage component such as a read-only memory (ROM)112M, a control logic circuit114, a random access memory (RAN)116, and a transmission interface circuit118, where at least one portion (e.g. a portion or all) of these components may be coupled to one another through a bus. The RAM116may be a static RAM (SRAM) or a dynamic RAM (DRAM), which is configured to provide internal storage space for the memory controller110, for example, temporarily storing information, such as variables, data, commands, addresses and/or address mapping tables. Moreover, the RAM116may be provided by allocating a part of a system memory (not shown) of the host device50. In addition, the ROM112M of this embodiment is configured to store a program code112C, and the microprocessor112is configured to execute the program code112C to control access of the NV memory120. Alternatively, the program code112C may be stored in the NV memory120.

The memory controller110controls reading, writing and erasing of the NV memory120through a control logic circuit114. In addition, the memory controller110could perform writing of user data based on host commands from the host device50and writing of valid data which is read from the NV memory120by the garbage collection and or wear-leveling concurrently. The control logic circuit114may be further configured to control the NV memory120and comprise an Error Correction Code (ECC) circuit (not shown), to perform data protection and/or error correction, but the present invention is not limited thereto. The transmission interface circuit118may conform to a specific communications specification (such as Serial Advanced Technology Attachment (SATA) specification, Universal Serial Bus (USB) specification, Peripheral Component Interconnect Express (PCIE) specification, embedded Multi Media Card (eMMC) specification, or Universal Flash Storage (UFS) specification) and may perform communications with the host50according to the specific communications specification.

Typically, the host device50may access the memory device100, indirectly, through transmitting host commands and corresponding logic addresses to the memory controller110. The memory controller110receives the host commands and the logic addresses, and translates the host commands to memory operation commands, and further controls the NV memory120with the memory operation commands to perform read, write or erase operations upon memory units or data pages having physical addresses within the NV memory120, where the physical addresses corresponds to the logic addresses. When the memory controller110performs an erase operation on any NV memory element122_kwithin the plurality of NV memory elements122_1-122_N, at least one block of the NV memory element122_kmay be erased. In addition, each block of the NV memory element122_kmay comprise multiple pages, and an access operation (e.g. read or write) may be performed on one or more pages.

In one embodiment, each one of NV memory elements122_1-122_N could be a NV memory die (or chip). There is control circuitry on each one of NV memory dies122_1-122_N for executing memory operation commands issued by the memory controller110. In addition, each of the NV memory dies122_1-122_N could comprise a plurality of planes. Each plane may comprise a number of blocks of memory cells and associated row and column control circuitry. The memory cells in each plane may be arranged in a 2D or 3D memory structure. Multiple operations may be performed in parallel (i.e., simultaneously) on memory blocks of different planes according to a multi-plane (e.g. read, program, erase) operation. The multi-plane operation may perform various processing operations on different planes simultaneously.

In one embodiment, the memory controller110may be configured to group memory blocks of NV memory120into a plurality of super blocks. In one embodiment, the super block may be formed across a plurality of NV memory chips122_1-122_K. The super block may be configured as one or more memory blocks included in each of the NV memory chips NV memory chip122_1-122_K.

In one embodiment of the present invention, a logical-to-physical (L2P) address mapping table, which includes a plurality of L2P address mapping entries for performing logical to physical address translation, will be divided into multiple mapping groups, each includes a part of mapping entries of the L2P address mapping table. These mapping groups are permanently stored in the blocks of NV memory120and will be loaded to the RAM116when necessary. Similarly, a physical-to-logical (P2L) address mapping table, which includes a plurality of P2L address mapping entries for performing physical to logical address translation, will be divided into multiple mapping groups, each includes a part of mapping entries of the P2L address mapping table. These mapping groups are permanently stored in the blocks of NV memory120and will be loaded to the RAM116when necessary.

In one embodiment, the host device50may notify the memory controller110of one or more logical blocks that are no longer in-use or outdated (i.e., invalid data) and thus may be deleted by sending a trim command to the memory controller110. Please refer toFIG.2for further understandings. As illustrated, a trim command typically includes one or more trim entries. That is, a first trim entry indicates a start logical block address (LBA) and a trim length of 2 (which means 2 mapping units needs to be trimmed, and each of the mapping unit could be preferably 4K bytes), which means data of two mapping units that starts from LBA200no longer in use by the host device50. In addition, a second trim entry indicates a start LBA300and a trim length of 1, while a third trim entry indicates a start LBA400and a trim length of 1.

In this embodiment, a L2P address mapping table records mapping entries as follow: 1) LBA0is mapped to physical block address7and physical page address555; 2) LBA200is mapped to physical block address5and physical page address99; 3) LBA201is mapped to physical block address5and physical page address100; 4) LBA300is mapped to physical block address23and physical page address51; and 5) LBA400is mapped to physical block address11and physical page address36. Moreover, a valid page count table records a number of valid pages (or valid LBA) included in physical blocks. For example, 150 valid pages (or 150 valid LBAs) in the physical block at physical block address0; 700 valid pages (or 700 valid LBAs) in the physical block at physical block address1; 10 valid pages (or 10 valid LBAs) in the physical block at physical block address5; 200 valid pages (or 200 valid LBAs) in the physical block at physical block address11; and 5) 500 valid pages (500 valid LBAs) in the physical block at block address23.

Please refer toFIG.3, which illustrates how the memory controller110handles a trim command at a first step of a handling flow according to one embodiment of the present invention. At first, the L2P address mapping table and the valid page count table would be loaded to the RAM116of the memory controller110from the NV memory120(if they have not been loaded before). Specifically, the memory controller110may not load the full L2P address mapping table and/or the full valid page count table to the RAM116. Instead, the memory controller may only load a portion (e.g. one or several groups) of the full L2P address mapping table and/or a portion (e.g. one or several groups) of the full valid page count table to the RAM116.

After that, the memory controller110firstly re-calculates valid page counts of physical blocks that are associated with data to be trimmed. As presented, a first trim entry is intended to trim data from LBA200with length of 2, a second trim entry is intended to trim data from LBA300with length of 1 and a third trim entry of the trim command is intended to trim data from LBA400with length of 1. Accordingly, the memory controller110would check the L2P address mapping table to map the LBAs to physical addresses of data that is intended to be trimmed. In accordance with the L2P address mapping table, LBA200is mapped to the physical block address5and physical page address99, and LBA201is mapped to the physical block address5and physical page address100. LBA300is mapped to the physical block address23and physical page address51. LBA400is mapped physical block address11and physical page address36.

Thus, the valid page count of the physical block at PBA5will be subtracted by according to data amount of data to be trimmed by the first trim entry, such that the valid page count (or the valid LBA count) of PBA5will become 8 (i.e., 10-2). The valid page count of the physical block at PBA11will be subtracted by data amount of data to be trimmed by the third trim entry, such that the valid page count (or the valid LBA count) of PBA11will become 199 (i.e., 200−1=199). The valid page count of the physical block at PBA23will be subtracted by the data amount of data to be trimmed by the second trim entry, such that the valid page count (or the valid LBA count) of PBA23will become 499 (i.e., 500−1=499).

Please refer toFIG.4, which illustrates how the memory controller110handles the trim command at a second step of the handling flow according to one embodiment of the present invention. At the second step shown byFIG.4, the memory controller110would erase all L2P address mapping entries that are associated with trim ranges of the trim entries by modifying corresponding physical addresses as null value. Specially, a trim range of the first trim entry is two mapping units starting from LBA200, and thus the L2P address mapping entries that are associated with LBA200(which map LBA200to physical block address5and page address99) and LBA201(which maps LBA201to physical block address5and page address100) will be erased from the L2P mapping table. A trim range of the second trim entry is one mapping unit starting from LBA300and thus the L2P address mapping entry that is associated with LBA300(which maps LBA300to physical block address23and page address51) will be erased from the L2P mapping table. A trim range of the third trim entry is one mapping unit starting from LBA400and thus the L2P address mapping entry that is associated with LBA400(which maps LBA400to physical block address11and page address36) will be erased from the L2P mapping table.

Please refer toFIG.5, which illustrates how the memory controller110handles a trim command at a third step of the handling flow according to one embodiment of the present invention. At the third step shown byFIG.5, the memory controller110would store trim information regarding the trim command into a current data block of the NV memory120that the memory controller110is currently using for writing (user) data to. Specifically, trim information regards start LBAs and trim lengths (or trim ranges) of all the trim entries contained in the trim command will be saved to a blank page of the current data block. Moreover, blocks of the NV memory120comprises data blocks and log blocks, and the trim information will be written into one of the data blocks (; preferably the data block that the memory controller is currently using for writing data to).

In one embodiment, the memory controller110would start sudden power off and recover (SPOR) after a power cycle (e.g. power off (by shutdown or power-interrupting event) and then power on) of the storage device100. Specifically, the memory controller110would perform a power-on data rebuild process in response to SPOR. During the power-on data rebuild process, the memory controller110would load the saved trim information from the data block of the NV memory120. Accordingly, the memory controller110would executes operations as mentioned in steps ofFIG.3,FIG.4andFIG.5again since data to be trimmed may be recovered in the power-on data rebuild process. In one embodiment, the memory controller110will redo the trim command and rebuild other user data in an order in which data is written to pages of the data block. By redoing the trim command according to the stored trim information in the power-on data rebuild process, it can be guaranteed that the validity of data can be recovered to the newest state (e.g., guarantying that data intended to be trimmed by the host device50is exactly trimmed) even if unintentional power off event occurs.

In one embodiment, a data block that the trim information is saved cannot be selected as a source block of a GC operation if all the address mapping information regarding the data block that the trim information is stored has not been saved to the NV memory120(e.g. saved to one of log blocks). In other words, the data block that the trim information is stored can be selected as a source block of the GC operation if all the address mapping information regarding the data block that the trim information is stored has been saved to the NV memory120. Moreover, if the data block that the trim information is stored is selected as the source block of the GC operation, the trim information will be regarded as invalid data.

FIG.6illustrates a method of handling trim commands for a flash memory. As shown in the figure, the method of the present invention includes the following simplified flow:

Step S210: receiving a trim command;

Step S220: modifying logical-to-physical (L2P) address mapping entries of a L2P address mapping table according to the trim command; and

Step S230: storing trim information of the trim command into one of data blocks of the flash memory after modifying the L2P address mapping entries according to the trim command.

Since principles and specific details of the foregoing steps have been explained in detail through the above embodiments, further descriptions will not be repeated here. It should be noted that the above flow may be possible, by adding other extra steps or making appropriate modifications and adjustments, to better improve flexibility and further improve efficiency of handling trim commands. Furthermore, all the operations set forth in the above embodiments can be implemented by the memory controller110shown inFIG.1.

In conclusion, the method and the mechanism provided by the present invention can effectively complete trim commands that are associated with writing dummy patterns to the flash memory. Also, method and the mechanism provided by the present invention life by avoiding writing dummy patterns to the flash memory.

Embodiments in accordance with the present embodiments can be implemented as an apparatus, method, or computer program product. Accordingly, the present embodiments may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects that can all generally be referred to herein as a “module” or “system.” Furthermore, the present embodiments may take the form of a computer program product embodied in any tangible medium of expression having computer-usable program code embodied in the medium. In terms of hardware, the present invention can be accomplished by applying any of the following technologies or related combinations: an individual operation logic with logic gates capable of performing logic functions according to data signals, and an application specific integrated circuit (ASIC), a programmable gate array (PGA) or a field programmable gate array (FPGA) with a suitable combinational logic.

The flowchart and block diagrams in the flow diagrams illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present embodiments. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It is also noted that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions. These computer program instructions can be stored in a computer-readable medium that directs a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable medium produce an article of manufacture including instruction means which implement the function/act specified in the flowchart and/or block diagram block or blocks.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.