Patent ID: 12223908

DETAILED DESCRIPTION OF EMBODIMENTS

In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some, but not all, embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all of the other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present disclosure.

It will be noted that, in the drawings, a size and a relative size of the elements may be exaggerated for clarity and/or description. In this way, a dimension and a relative dimension of the various elements are not necessarily limited to those shown in the drawings. In the specification and drawings, a same or similar reference number refer to a same or similar part.

When an element is described as being “on”, “connected to”, or “coupled to” another element, the element may be directly on, directly connected to, or directly coupled to the other element, or intermediate elements may be existed. However, when an element is described as being “directly on”, “directly connected to”, or “directly coupled to” another element, there is no intermediate element existed. Other terms and/or expressions used to describe a relationship between elements should be interpreted in a similar fashion, e.g., “between” versus “directly between”, “adjacent” versus “directly adjacent”, or “on” versus “directly on” etc. Furthermore, the term “connected” may refer to a physical connection, an electrical connection, a communication connection, and/or a fluid connection. In addition, an X axis, a Y axis and a Z axis are not limited to a three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X, Y, and Z axes may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For a purpose of the present disclosure, “at least one of X, Y, and Z” and “at least one of the selected groups consisted of X, Y, and Z” may be interpreted as X only, Y only, Z only, or such as any combination of two or more of X, Y and Z in XYZ, XYY, YZ and ZZ. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be noted that, although the terms “first”, “second”, etc. may be used herein to describe various components, members, elements, regions, layers and/or parts, these components, members, elements, regions, layers and/or parts shall not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer and/or part from another. Thus, for example, a first component, a first member, a first element, a first region, a first layer and/or a first part discussed below could be referred to as a second component, a second member, a second element, a second region, a second layer and/or a second part without departing from the teachings of the present disclosure.

For ease of description, a spatially relational term, e.g., “upper”, “lower”, “left”, “right”, etc. may be used herein to describe a relationship between one element or feature with another element or feature as shown in the drawings. It should be understood that the spatially relational term are intended to encompass other different orientations of the apparatus in use or operation in addition to an orientation depicted in the drawings. For example, if the apparatus in the drawings is turned over, the elements described as “below” or “beneath” the other elements or features would then be oriented “above” or “on” the other elements or features.

In the present disclosure, the terms “basically”, “about”, “approximately”, “roughly” and other similar terms are used as approximate terms rather than as terms of degree, and they are intended to explain the fixed deviation of measured or calculated values that will be recognized by those skilled in the art. Taking into account factors such as process fluctuations, measurement problems and errors related to the measurement of a specific amount (i.e., the limitations of the measurement system), the “about” or “approximately” used here includes the stated value, and indicates that the specific value determined by ordinary technicians in the art is within the acceptable deviation range. For example, “about” may be expressed within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated values.

It will be noted that the expression “same layer” refers to a layer structure which is formed by forming a layer used to form a specific pattern by the same film-forming process, and then patterning the layer by using the same mask through one patterning process. According to the difference between the specific patterns, the patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures and/or parts located in the “same layer” are made of the same material and formed by the same patterning process. Generally, multiple elements, components, structures and/or parts located in the “same layer” have substantially the same thicknesses.

Those skilled in the art will understand that herein, unless otherwise specified, the expression “height” or “thickness” refers to a dimension of a surface of each film layer along a direction perpendicular to the display substrate, i.e., a dimension along a light exit direction of the display substrate, or referred to as a dimension along a normal direction of the display device.

In this text, the expression “transistor” may refer to a transistor, a thin film transistor, or a field-effect transistor, or other devices with the same characteristics. In embodiments of the present disclosure, in order to distinguish between the two electrodes of the transistor except for a control electrode, one electrode is referred to as a first electrode and the other electrode is referred to as a second electrode. In practical operation, when the transistor is a thin film transistor or a field-effect transistor, the first electrode may be a drain, and the second electrode may be a source. Alternatively, the first electrode may be a source, and the second electrode may be a drain.

Embodiments of the present disclosure provides at least a display substrate. The display substrate includes: a base substrate; a first semiconductor layer disposed on the base substrate; a first conductive layer disposed on a side of the first semiconductor layer away from the base substrate; and a second conductive layer disposed on a side of the first conductive layer away from the base substrate. The display substrate further includes a pixel driving circuit disposed on the base substrate. The pixel driving circuit includes a driving circuit, a storage circuit, and a reset circuit. The reset circuit is electrically connected to a first terminal of the driving circuit or a second terminal of the driving circuit and is used to initialize a potential at the first terminal of the driving circuit or a potential at the second terminal of the driving circuit in an initialization stage. The driving circuit is used to conduct a path between the first terminal of the driving circuit and the second terminal of the driving circuit under the control of a potential at a control terminal of the driving circuit. The storage circuit is electrically connected to the control terminal of the driving circuit and is used to store electrical energy. The reset circuit includes a first capacitor. The storage circuit includes a second capacitor. The first capacitor includes a first electrode plate and a second electrode plate disposed opposite to the first electrode plate. The second capacitor includes a first electrode plate and a second electrode plate disposed opposite to the first electrode plate. The first electrode plate of the first capacitor and the first electrode plate of the second capacitor are located in the first conductive layer. The second electrode plate of the first capacitor and the second electrode plate of the second capacitor are located in the second conductive layer. An orthographic projection of the first electrode plate of the first capacitor on the base substrate and an orthographic projection of the first electrode plate of the second capacitor on the base substrate are spaced from each other. An orthographic projection of the second electrode plate of the first capacitor on the base substrate and an orthographic projection of the second electrode plate of the second capacitor on the base substrate are spaced from each other. The orthographic projection of the first electrode plate of the first capacitor on the base substrate at least partially overlaps with the orthographic projection of the second electrode plate of the first capacitor on the base substrate. The orthographic projection of the first electrode plate of the second capacitor on the base substrate at least partially overlaps with the orthographic projection of the second electrode plate of the second capacitor on the base substrate. An area of the overlap between the orthographic projection of the first electrode plate of the first capacitor on the base substrate and the orthographic projection of the second electrode plate of the first capacitor on the base substrate is smaller than an area of the overlap between the orthographic projection of the first electrode plate of the second capacitor on the base substrate and the orthographic projection of the second electrode plate of the second capacitor on the base substrate. In the embodiments of the present disclosure, when the pixel driving circuit operates, before a data voltage is written into the driving circuit, the reset circuit initializes the potential at the first terminal of the driving circuit or the potential at the second terminal of the driving circuit in the initialization stage, so as to reduce the magnetic hysteresis of the driving circuit and solve the problem of residual image, flicker and other phenomena caused by the magnetic hysteresis of a driving transistor in a low-frequency state.

FIG.1is a schematic plan view of a display device according to some embodiments of the present disclosure. For example, the display device may be an OLED display device. With reference toFIG.1, the display device1000may include a display panel1100, a gate driver1200, a data driver1300, a controller1400and a voltage generator1500. The display panel1100may include an array substrate1000and a plurality of pixels PX. The array substrate1000may include a display area AA and a non-display area NA, and the plurality of pixels PX are arranged in an array in the display area AA. A signal generated by the gate driver1200may be applied to the pixel PX through a signal line such as a scanning signal line GL. A signal generated by the data driver1300may be applied to the pixel PX through a signal line such as a data line DL. For example, a first voltage such as VDD and a second voltage such as VSS may be applied to the pixel PX. The first voltage such as VDD may be higher than the second voltage such as VSS. Optionally, the first voltage such as VDD may be applied to an anode of a light-emitting element (such as an OLED), and the second voltage such as VSS may be applied to a cathode of the light-emitting element, so that the light-emitting element may emit light.

For example, each pixel PX may include a plurality of sub-pixels, such as a red sub-pixel, a green sub-pixel and a blue sub-pixel. Alternatively, each pixel PX may include a white sub-pixel, a red sub-pixel, a green sub-pixel and a blue sub-pixel.

FIG.2is a schematic plan view of a display substrate included in a display device according to some embodiments of the present disclosure. For example, the display substrate may be an array substrate for an OLED display panel.

With reference toFIG.2, the display substrate may include a display area AA and a non-display area NA. For example, the display area AA and the non-display area NA may include a plurality of boundaries, such as AAS1, AAS2, AAS3and AAS4as shown inFIG.2. The display substrate may further include a driver located in the non-display area NA. For example, the driver may be located on at least one side of the display area AA. In the embodiment shown inFIG.2, drivers are respectively located on a left side of the display area AA and a right side of the display area AA. It will be noted that the left side and the right side may be respectively a left side of the display substrate (screen) and a right side of the display substrate (screen) viewed by human eyes during the display. The driver may be used to drive each pixel in the display substrate for display. For example, the driver may include the gate driver1200and the data driver1300mentioned above. The data driver1300is used to latch input data based on timings of clock signals sequentially, convert the latched data into analog signals, and then input the analog signals to the respective data lines of the display substrate. The gate driver1200is usually implemented by shift registers, which convert clock signals into on/off voltages and respectively output the on/off voltages to the respective scanning signal lines of the display substrate.

It will be noted that although the drivers shown inFIG.2are located on the left side of the display area AA and the right side of the display area AA, the embodiments of the present disclosure are not limited to this. The driving circuit may be located at any suitable position in the non-display area NA.

For example, the driver may adopt a GOA technology, i.e., Gate Driver on Array. According to the GOA technology, a gate driving circuit is directly provided on the array substrate instead of an external driving chip. Each GOA unit serves as a stage of shift register, and each stage of shift register is connected to a gate line. Turn-on voltages are sequentially output by the respective stages of shift register in turn to scan the pixels row by row. In some embodiments, each stage of shift register may also be connected to a plurality of gate lines, which may adapt to a development trend of high resolution and narrow bezel of the display substrate.

With reference toFIG.2, a left GOA circuit DA1, a plurality of pixels P in the display area AA and a right GOA circuit DA2are provided in the display substrate. Each of the left GOA circuit DA1and the right GOA circuit DA2is electrically connected to a display IC through a signal line, where the display IC is configured to control a supply of GOA signals. For example, the display IC is disposed on a lower side (an observation direction of human eyes) of the display substrate. The left GOA circuit DA1and the right GOA circuit DA2are further electrically connected to the respective pixels through signal lines (such as the scanning signal lines GL) to supply driving signals to the pixels.

It will be noted that the figure shows that a shape of an orthographic projection of a sub-pixel on the base substrate is a rounded rectangle. However, the embodiments of the present disclosure are not limited to this. For example, the shape of the orthographic projection of the sub-pixel on the base substrate may be a rectangle, hexagon, pentagon, square, circle or other shapes. Moreover, an arrangement of three sub-pixels in a pixel unit is not limited to the arrangement shown inFIG.1andFIG.2.

With reference toFIG.1andFIG.2, each pixel unit PX may include a plurality of sub-pixels, such as a first sub-pixel SP1, a second sub-pixel SP2and a third sub-pixel SP3. For convenience of understanding, the first sub-pixel SP1, the second sub-pixel SP2and the third sub-pixel SP3may be described as red sub-pixels, green sub-pixels and blue sub-pixels respectively. However, the embodiments of the present disclosure are not limited to this.

The plurality of sub-pixels are arranged in an array along a row direction X and a column direction Y on the base substrate1. It will be noted that although in the illustrated embodiments, the row direction X and the column direction Y are perpendicular to each other, the embodiments of the present disclosure are not limited to this.

It will be understood that in the embodiments of the present disclosure, each sub-pixel includes a pixel driving circuit and a light-emitting element. For example, the light-emitting element may be an OLED light-emitting element including an anode, a light-emitting layer and a cathode which are stacked. The pixel driving circuit may include a plurality of thin film transistors and at least one storage capacitor.

FIG.3is a block diagram of a structure of a pixel driving circuit according to some embodiments of the present disclosure.FIG.4is an equivalent circuit diagram of a pixel driving circuit according to some embodiments of the present disclosure. It will be noted that in the following explanation, a structure of the pixel driving circuit will be described in detail by taking an 8T2C pixel driving circuit as an example. However, the embodiments of the present disclosure are not limited to the 8T2C pixel driving circuit. Without conflict, other known structures of a pixel driving circuit may be applied to the embodiments of the present disclosure.

As shown inFIG.3, the pixel driving circuit according to the embodiments of the present disclosure is used to drive a light-emitting element100. The pixel driving circuit includes a driving circuit110and a reset circuit220. The reset circuit220is electrically connected to a first terminal of the driving circuit110and is used to initialize a potential at the first terminal of the driving circuit110in an initialization stage. The driving circuit110is used to conduct a path between the first terminal of the driving circuit110and the second terminal of the driving circuit110under the control of a potential at a control terminal of the driving circuit.

In the embodiments of the present disclosure, when the pixel driving circuit operates, before a data voltage is written into the driving circuit, the reset circuit initializes the potential at the first terminal of the driving circuit or the potential at the second terminal of the driving circuit in the initialization stage, so as to reduce the magnetic hysteresis of the driving transistor and solve the problem of residual image, flicker and other phenomena caused by the magnetic hysteresis of a driving transistor in a low-frequency state.

With continued reference toFIG.3, the pixel driving circuit further includes a first light-emitting control circuit310and a second light-emitting control circuit320.

The first light-emitting control circuit310is electrically connected to each of a first light-emitting control line E1, the first terminal of the driving circuit11and a first voltage line V1. The first light-emitting control circuit310is used to conduct a path between the first terminal of the driving circuit11and the first voltage line V1under the control of a first light-emitting control signal provided by the first light-emitting control line E1.

A second light-emitting control circuit320is electrically connected to a second light-emitting control line E2, the second terminal of the driving circuit11and a first electrode of the light-emitting element100. The second light-emitting control circuit320is used to conduct a path between the second terminal of the driving circuit110and the first electrode of the light-emitting element100under the control of a second light-emitting control signal provided by the second light-emitting control line E2.

A second electrode of the light-emitting element100is electrically connected to a second voltage line V2.

In the embodiments of the present disclosure, when the pixel driving circuit operates, in a light-emitting stage, the first light-emitting control circuit310conducts a path between the first terminal of the driving circuit110and the first voltage line V1under the control of the first light-emitting control signal, and the second light-emitting control circuit320conducts a path between the second terminal of the driving circuit110and the first electrode of the light-emitting element100under the control of the second light-emitting control signal.

With reference toFIG.3andFIG.4, the pixel driving circuit further includes a reset circuit20. The reset circuit20may include a first capacitor C1. The first capacitor C1may include a first electrode plate C1aand a second electrode plate C1b.

The first electrode plate of the first capacitor C1is electrically connected to the first light-emitting control line E1, and the second electrode plate of the first capacitor C1is electrically connected to the first terminal of the driving circuit11.

InFIG.4, a first node labeled N1is electrically connected to the control terminal of the driving circuit11, a second node labeled N2is electrically connected to the first terminal of the driving circuit11, and a third node labeled N3is electrically connected to the second terminal of the driving circuit11.

In the embodiments of the present disclosure, when the pixel driving circuit operates, in an initialization stage, a potential of the light-emitting control signal provided by E1changes from a low voltage Vgl to a high voltage Vgh, N2is in a floating state, and a potential at N2changes as a potential at the first electrode plate of the first capacitor C1changes. The potential at N2changes to (V1+Vgh−Vgl). At this time, a gate-source voltage of the driving transistor in the driving circuit110is less than Vth (Vth being a threshold voltage of the driving transistor), and the driving transistor is in a conductive bias state, so as to reduce magnetic hysteresis of N2caused by the floating.

In the embodiments of the present disclosure, when the pixel driving circuit operates, before the data writing, the driving transistor is in a conductive bias state, so as to ensure that the charging and compensation of the driving transistor in each pixel driving circuit start in the conduction bias state of the driving transistor, without being affected by a previous frame data voltage. In this way, it is possible to eliminate an influence of the magnetic hysteresis of the driving transistor, reduce residual image, and improve response time.

With continued reference toFIG.3andFIG.4, the pixel driving circuit may further include a storage circuit210, a data writing circuit530, a compensation control circuit520, an on-off control circuit510, a first initialization circuit410and a second initialization circuit420. The storage circuit210is electrically connected to the control terminal of the driving circuit11, and used for storing electrical energy. The data writing circuit530is electrically connected to each of a scanning line S1, a data line D1and the first terminal of the driving circuit110, and used for writing the data voltage on the data line D1into the first terminal of the driving circuit110under the control of a scanning signal provided by the scanning line S1. The on-off control circuit510is electrically connected to each of the scanning line S1, the control terminal of the driving circuit110and a connection node N0, and used for conducting a path between the control terminal of the driving circuit110and the connection node N0under the control of the scanning signal. The compensation control circuit520is electrically connected to each of the scanning line S1, the connection node N0and the second terminal of the driving circuit110, and used for conducting a path between the connection node N0and the second terminal of the driving circuit110under the control of the scanning signal provided by the scanning line S1. The first initialization circuit410is electrically connected to each of a reset control line R1, a first initial voltage line Vi1and the connection node N0, and used for writing a first initial voltage provided by the first initial voltage line into the connection node N0under the control of a reset control signal provided by the reset control line R1. The second initialization circuit420is electrically connected to each of a light-emitting element reset line R2, a second initial voltage line Vi2and the first electrode of the light-emitting element100, and used for writing a second initial voltage provided by the second initial voltage line into the first electrode of the light-emitting element10under the control of the reset control signal provided by the light-emitting element reset line R2.

In the embodiments of the present disclosure, when the pixel driving circuit operates, a display cycle may include an initialization stage, a data writing stage and a light-emitting stage, which are set in sequence.

In the initialization stage, the on-off control circuit510conducts a path between the control terminal of the driving circuit110and the connection node N0under the control of the scanning signal, and the first initialization circuit410writes the first initial voltage to the connection node N0under the control of the reset control signal, so as to write the first initial voltage to the control terminal of the driving circuit110. The second initialization circuit420writes the second initial voltage provided by the second initial voltage line Vi2to the first electrode of the light-emitting element100under control of the reset control signal provided by the light-emitting element reset line R2, so as to control the light-emitting element100to not emit light and purge residual charges from the first electrode of the light-emitting element100.

In the data writing stage, the data writing circuit530writes the data voltage on the data line D1to the first terminal of the driving circuit110under the control of the scanning signal, and the compensation control circuit520conduct the path between the connection node N0and the second terminal of the driving circuit110under the control of the scanning signal. At a beginning of the data writing stage, the driving transistor in the driving circuit110is turned on, so as to charge the storage circuit by using the data voltage to change the potential at the control terminal of the driving circuit110until the driving transistor is turned off.

In the light-emitting stage, the first light-emitting control circuit310conducts the path between the first terminal of the driving circuit110and the first voltage line V1under the control of the first light-emitting control signal, the second light-emitting control circuit320conducts the path between the second terminal of the driving circuit110and the first electrode of the light-emitting element100under the control of the second light-emitting control signal, and the driving circuit110drives the light-emitting element100to emit light.

For example, in the embodiment shown inFIG.4, the reset circuit220includes the first capacitor C1. The first light-emitting control circuit310includes a fifth transistor T5. The second light-emitting control circuit320includes a sixth transistor T6. The on-off control circuit510includes an eighth transistor T8. The second initialization circuit420includes a seventh transistor T7. The first initialization circuit410includes a first transistor T1. The compensation control circuit520includes a second transistor T2. The data writing circuit530includes a fourth transistor T4. The driving circuit110includes the driving transistor T3. The storage circuit210includes a second capacitor C2. The light-emitting element is an organic light-emitting diode100.

The first electrode plate of the first capacitor C1is electrically connected to the light-emitting control line E1, and the second electrode plate of the first capacitor C1is electrically connected to the node N2. That is, the second electrode plate of the first capacitor C1is electrically connected to a second electrode of the fifth transistor T5and a first electrode of the third transistor T3.

The first electrode plate of the second capacitor C2is electrically connected to the node N1, and the second electrode plate of the second capacitor C2is electrically connected to the first voltage line.

A gate of the first transistor T1is electrically connected to the reset control line R1, A first electrode of the first transistor T1is electrically connected to the first initial voltage line Vi1, and a second electrode of the first transistor T1is electrically connected to the node N0. For example, the first initial voltage line Vi1is used to provide the first initial voltage.

A gate of the second transistor T2is electrically connected to the scanning line S1, a second electrode of the second transistor T2is electrically connected to the node N3, and a first electrode of the second transistor T2is electrically connected to the node N0. That is, the first electrode of the second transistor T2is electrically connected to the second electrode of the first transistor T1and a first electrode of the eighth transistor T8.

A gate of the third transistor T3is electrically connected to the node N1, the first electrode of the third transistor T3is electrically connected to the node N2, and a second electrode of the third transistor T3is electrically connected to the node N3.

A gate of the fourth transistor T4is electrically connected to the scanning line S1, a first electrode of the fourth transistor T4is electrically connected to the data line D1, and a second electrode of the fourth transistor T4is electrically connected to the node N2.

A gate of the fifth transistor T5is electrically connected to the light-emitting control line E1, a first electrode of the fifth transistor T5is electrically connected to the first voltage line V1, and the second electrode of the fifth transistor T5is electrically connected to the first electrode of the third transistor T3. The first voltage line is used to provide a high voltage VDD.

A gate of the sixth transistor T6is electrically connected to the light-emitting control line E1, and a first electrode of the sixth transistor T6is electrically connected to the node N3. That is, the first electrode of the sixth transistor T6is electrically connected to the second electrode of the third transistor T3and the second electrode of the second transistor T2. A second electrode of the sixth transistor T6is electrically connected to an anode of the organic light-emitting diode100.

A gate of the seventh transistor T7is electrically connected to the light-emitting element reset line R2, a first electrode of the seventh transistor T7is electrically connected to the second initial voltage line Vi2, and a second electrode of the seventh transistor T7is electrically connected to the node N4. That is, the second electrode of the seventh transistor T7is electrically connected to the first electrode of the sixth transistor T6and the anode of the organic light-emitting diode100. For example, the second initial voltage line Vi2is used to provide the second initial voltage, and the signal provided by the light-emitting element reset line R2will be further described in detail in the following text.

A gate of the eighth transistor T8is electrically connected to the second light-emitting control line E2, the first electrode of the eighth transistor T8is electrically connected to the node N0, and a second electrode of the eighth transistor T8is electrically connected to the node N1.

The anode of the organic light-emitting diode100is electrically connected to the node N4, and a cathode of the organic light-emitting diode100is electrically connected to the second voltage line. The second voltage line is used to provide a low voltage VSS.

In the embodiments of the present disclosure, the first light-emitting control line E1applies the first light-emitting control signal to the gate of the fifth transistor T5, the gate of the sixth transistor T6, and the first electrode plate C1aof the first capacitor C1.

In the embodiments of the present disclosure, Vi2may be the same as Vi1. Also, Vi1may be different from Vi2.

In the embodiments of the present disclosure, the eighth transistor T8may be an oxide thin film transistor, and other transistors T1to T7may be low temperature poly-silicon thin film transistors. However, the embodiments of the present disclosure are not limited by this.

According to at least one embodiment of the pixel driving circuit described in the present disclosure, a voltage value of Vi1may be greater than or equal to −6V, and less than or equal to −2V. For example, the voltage value of Vi1may be −2V, −3V, −4V, −5V, or −6V, etc., but not limited by this.

Threshold voltages Vth of the transistors may be greater than or equal to −5V, and less than or equal to −0.5V. For example, Vth may be −2.5V or −3V, or the like.

A voltage value of the high voltage VDD provided by the first voltage line may be greater than or equal to 3V, and less than or equal to 6V. For example, the voltage value of VDD may be 4.6V, but not limited by this.

An absolute value of the voltage value of the high voltage VDD may be greater than 1.5 times of an absolute value of Vth. For example, the absolute value of the voltage value of VDD may be 1.6 times, 1.8 times, 2 times of the absolute value of Vth, or the like.

Optionally, a voltage value of the low voltage VSS provided by the second voltage line may be greater than or equal to −6V, and less than or equal to −3V. For example, the voltage value of VSS may be −5V, −4V, or −3V.

In at least one embodiment of the present disclosure, the voltage value of Vi2may be greater than or equal to −7V, and less than or equal to 0V. For example, the voltage value of the second initialization voltage may be −6V, −5V, −4V, −3V, or −2V, but not limited by this.

Optionally, a voltage difference between the voltage value of Vi2and the voltage value of VSS needs to be less than a lightening voltage of the light-emitting element, so that when the first electrode of the light-emitting element receives Vi2, the light-emitting element does not emit light.

FIG.5is an operation timing diagram for at least one embodiment of the pixel driving circuit shown inFIG.4. With reference toFIG.3toFIG.5, during the operation of the pixel driving circuit according to the embodiments of the present disclosure, a display cycle may include an initialization stage t1, a data writing stage t2and a light-emitting stage t3which are set in sequence.

In the initialization stage t1, the potential of the light-emitting control signal provided by the first light-emitting control line E1is converted from the low voltage Vgl to the high voltage Vgh, the reset control line R1provides a low voltage signal, the second light-emitting control line E2provides a high voltage signal, and the scanning line S1provides a high voltage signal. The transistor T6and the transistor T4are turned on, Vi1is written to the node N1, and the potential at the node N2is changed to VDD+(Vgh−Vgl). At this time, the gate-source voltage of the transistor T3is less than the threshold voltage Vth of the transistor T3, so that the transistor T3is in the conduction bias state; the transistor T5is turned on, Vi2is written to the anode of organic light-emitting diode100, the organic light-emitting diode100does not emit light, and residual charges are purged from the anode of the organic light-emitting diode100.

In the data writing stage t2, the reset control line R1provides a high voltage signal, the second light-emitting control line E2provides a high voltage signal, the scanning line S1provides a low voltage signal, and the first light-emitting control line E1provides a high voltage signal. The transistors T2, T4and T8are turned on, the data voltage Vdata on the data line D1is written to the node N2, the path between the node N1and the node N3is conducted. The second capacitor C2is charged by using Vdata, so as to change a potential at the gate of the transistor T3, and until the transistor T3is turned off, the potential of the gate of the transistor T3is changed to Vdata+Vth.

In the light-emitting stage t3, the reset control line R1provides a high voltage signal, the second light-emitting control line E2provides a low voltage signal, the scanning line S1provides a high voltage signal, and the first light-emitting control line E1provides a low voltage signal. The transistors T3, T5and T6are turned on, and the transistor T3drives the organic light-emitting diode100to emit light. At this time, a light-emitting current of the organic light-emitting diode100is 0.5K(Vdata−VDD)2, where K is a current coefficient of the transistor T3.

In the embodiments of the present disclosure, a pulse width of the first light-emitting control signal provided by the first light-emitting control line E1may be the same as a pulse width of the second light-emitting control signal provided by the second light-emitting control line E2. Alternatively, the pulse width of the first light-emitting control signal provided by the first light-emitting control line E1may be larger than the pulse width of the second light-emitting control signal provided by the second light-emitting control line E2by a predetermined time.

When the pulse width of the first light-emitting control signal provided by the first light-emitting control line E1may be the same as the pulse width of the second light-emitting control signal provided by the second light-emitting control line E2, in the initialization stage, the transistors T5and T6may fail to be turned off correctly. Based on this, in at least one embodiment of the present disclosure, the pulse width of the first light-emitting control signal provided by the first light-emitting control line E1may be larger than the pulse width of the second light-emitting control signal provided by the second light-emitting control line E2by the predetermined time. The predetermined time may be less than or equal to 0.5H, and 1H is the time for scanning one row. In this way, in the initialization stage, under the control of the first light-emitting control signal, the transistors T5and T6are turned off, so as to disconnect the path between the first voltage line and the first electrode of the transistor T3and the path between the second electrode of the transistor T3and the anode of the organic light-emitting diode100, so that the organic light-emitting diode100does not emit light, which does not affect light-emitting.

In the embodiments of the present disclosure, the transistor T8included in the on-off control circuit may be an oxide thin film transistor. In this way, a leakage of the control terminal of the driving circuit may be reduced, so as to ensure a stability of the voltage of the control terminal of the driving circuit during a low-frequency operation, thereby improving display quality and display uniformity, and reducing flicker.

In the embodiments of the present disclosure, the transistor T7may be controlled by a separate GOA, which is electrically connected to the light-emitting element reset line R2, so as to permit the organic light-emitting diode100to be reset at a frequency of 60 Hz.

FIG.6AandFIG.6Bare each a schematic diagram of a signal provided by a light-emitting element reset line according to some exemplary embodiments of the present disclosure. With reference toFIG.6AandFIG.6B, in the embodiments of the present disclosure, the signal provided by the light-emitting element reset line R2may be a high-frequency signal. For example, the frequency of the signal provided by the light-emitting element reset line R2may be higher than the frequency of the reset control signal provided by the reset control line R1. The frequency of the signal provided by the light-emitting element reset line R2shown inFIG.6Bis higher than the frequency of the signal provided by the light-emitting element reset line R2shown inFIG.6A. In the embodiment shown inFIG.6A, the frequency of the signal provided by the light-emitting element reset line R2is substantially equal to the frequency of the reset control signal provided by the reset control line R1.

FIG.23is a diagram of a luminescence effect of a light-emitting element when using a high-frequency signal shown inFIG.6B. With reference toFIG.23, by increasing the frequency of the signal provided by the light-emitting element reset line R2, a refresh frequency of the reset of the anode of the light-emitting element may be increased, so that a brightness establishment time of a refreshing stage of the light-emitting element is consistent with a brightness establishment time of a maintaining stage of the light-emitting element. In this way, it is possible to reduce a low component of the light-emitting maintaining stage, visible brightness changes and the flicker level, while reducing load and power consumption.

It will be noted that in the embodiments of the present disclosure, each thin film transistor T1, T2, T3, T4, T5, T6, T7and T8may be a p-channel field-effect transistor. However, the embodiments of the present disclosure is not limited thereto, and at least some of the thin film transistors T1, T2, T3, T4, T5, T6, T7and T8may be n-channel field-effect transistors.

FIG.7is a schematic plane configuration view of a first semiconductor layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure.FIG.8is a plane configuration view of a first conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure.FIG.9is a schematic plane configuration view of a combination of a first semiconductor layer of a pixel driving circuit and a first conductive layer of the pixel driving circuit according to an exemplary embodiment of the present disclosure.FIG.10is a schematic plane configuration view of a second conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure.FIG.11is a schematic plane configuration view of a second semiconductor layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure.FIG.12is a schematic plane configuration view of a combination of a first semiconductor layer of a pixel driving circuit, a first conductive layer of the pixel driving circuit, a second conductive layer of the pixel driving circuit and a second semiconductor layer of the pixel driving circuit according to an exemplary embodiment of the present disclosure.FIG.13is a schematic plane configuration view of a third conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure.FIG.14is a schematic plane configuration view of a combination of a first semiconductor layer of a pixel driving circuit, a first conductive layer of the pixel driving circuit, a second conductive layer of the pixel driving circuit, a second semiconductor layer of the pixel driving circuit and a third conductive layer of the pixel driving circuit according to an exemplary embodiment of the present disclosure.FIG.15is a schematic diagram showing via holes in an insulation layer formed on the structure inFIG.14.FIG.16is a schematic diagram showing via holes in an insulation layer formed on the structure inFIG.15.FIG.17a schematic plane configuration view of a fourth conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure.FIG.18is a schematic plane configuration view of a combination of a first semiconductor layer of a pixel driving circuit, a first conductive layer of the pixel driving circuit, a second conductive layer of the pixel driving circuit, a second semiconductor layer of the pixel driving circuit, a third conductive layer of the pixel driving circuit and a fourth conductive layer of the pixel driving circuit according to an exemplary embodiment of the present disclosure.FIG.19is a schematic plane configuration view of a fifth conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure.FIG.20is a schematic plane configuration view of a combination of a first semiconductor layer of a pixel driving circuit, a first conductive layer of the pixel driving circuit, a second conductive layer of the pixel driving circuit, a second semiconductor layer of the pixel driving circuit, a third conductive layer of the pixel driving circuit, a fourth conductive layer of the pixel driving circuit and a fifth conductive layer of the pixel driving circuit according to an exemplary embodiment of the present disclosure.FIG.21is a plan view schematically showing an overlapping area of a first capacitor and a second capacitor.FIG.22is a schematic diagram showing a sectional structure of a display substrate taken along line AA′ inFIG.20according to some exemplary embodiments of the present disclosure.

With reference toFIG.7toFIG.22, the display substrate includes a base substrate1and a plurality of film layers disposed on the base substrate1. In some embodiments, the plurality of film layers shown include at least a first semiconductor layer2, a first conductive layer3, a second conductive layer4, a second semiconductor layer5, a third conductive layer6, a fourth conductive layer7and a fifth conductive layer8. The first semiconductor layer2, the first conductive layer3, the second conductive layer4, the second semiconductor layer5, the third conductive layer6, the fourth conductive layer7and the fifth conductive layer8are sequentially disposed away from the base substrate1.

For example, the first semiconductor layer2may be formed of a semiconductor material such as low-temperature poly-silicon, and a film layer thickness of the first semiconductor layer2is in a range of 400 angstroms to 800 angstroms, such as 500 angstroms. The second semiconductor layer5may be formed of an oxide semiconductor material, such as a poly-silicon oxide semiconductor material such as IGZO, and a film layer thickness of the second semiconductor layer5may be in a range of 300 to 600 angstroms, such as 400 angstroms. The first conductive layer3, the second conductive layer4and the third conductive layer6may be formed of a conductive material that forms the gates of the thin film transistors, for example, the conductive material may be Mo, and a film layer thickness of first conductive layer3, a film layer thickness of the second conductive layer4and a film layer thickness of the third conductive layer6may be in a range of 2000 angstroms to 3000 angstroms, such as 2500 angstroms. The fourth conductive layer7and the fifth conductive layer8may be formed of a conductive material that forms the sources and the drains of the thin film transistors, such as Ti and Al. The fourth conductive layer7and the fifth conductive layer8may have a stack structure formed of Ti/Al/Ti, a film thickness of which is in a range of 7000 to 9000 angstroms. For example, in the case that the fourth conductive layer7and the fifth conductive layer8have the stack structure formed of Ti/Al/Ti, thicknesses of the respective layers of the Ti/Al/Ti stack structure may be substantially 500 angstroms, 5500 angstroms and 500 angstroms, respectively.

In the embodiments of the present disclosure, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6and the seventh transistor T7may be formed along the first semiconductor layer2as shown inFIG.7. The eighth transistor T8may be formed along the second semiconductor layer5as shown inFIG.12.

As shown inFIG.7, the first semiconductor layer2may have a curved shape or a bent shape, and may include a first active layer20acorresponding to the first transistor T1, a second active layer20bcorresponding to the second transistor T2, a third active layer20ccorresponding to the third transistor T3, a fourth source layer20dcorresponding to the fourth transistor T4, a fifth active layer20ecorresponding to the fifth transistor T5, a sixth active layer20fcorresponding to the sixth transistor T6, and a seventh active layer20gcorresponding to the seventh transistor T7.

For example, the first semiconductor layer2may include poly-silicon, such as a low-temperature poly-silicon material. The active layer of each transistor may include a channel region, a source region and a drain region. The channel region may be a non-doped region, or a doping type of the channel region is different from a doping type of the source region and a doping type of the drain region, and the channel region therefore has semiconductor characteristics. The source region and the drain region are respectively located on both sides of the channel region and doped with impurities, and are thus conductive. Impurities may be varied depending on whether the TFT is an N-type transistor or a P-type transistor.

The first transistor T1includes the first active layer20aand a first gate G1. The first active layer20aincludes a first source region203a, a first drain region205a, and a first channel region201aconnecting the first source region203aand the first drain region205a. The first source region203aand the first drain region205aextend in two opposite directions with respect to the first channel region201a.

The second transistor T2includes the second active layer20band a second gate G2. The second active layer20bincludes a second source region203b, a second drain region205b, and a second channel region201bconnecting the second source region203band the second drain region205b. The second source region203band the second drain region205bextend in two opposite directions with respect to the second channel region201b.

The third transistor T3includes the third active layer20cand a third gate G3. The third active layer20cincludes a third source region203c, a third drain region205c, and a third channel region201cconnecting the third source region203cand the third drain region205c. The third source region203cand the third drain region205cextend in two opposite directions with respect to the third channel region201c.

The fourth transistor T4includes the fourth source layer20dand a fourth gate G4. The fourth source layer20dincludes a fourth source region203d, a fourth drain region205d, and a fourth channel region201dconnecting the fourth source region203dand the fourth drain region205d. The fourth source region203dand the fourth drain region205dextend in two opposite directions with respect to the fourth channel region201d.

The fifth transistor T5includes the fifth active layer20eand a fifth gate G5. The fifth active layer20eincludes a fifth source region203e, a fifth drain region205e, and a fifth channel region201econnecting the fifth source region203eand the fifth drain region205e. The fifth source region203eand the fifth drain region205eextend in two opposite directions with respect to the fifth channel region201e.

The sixth transistor T6includes the sixth active layer20fand a sixth gate G6. The sixth active layer20fincludes a sixth source region203f, a sixth drain region205f, and a sixth channel region201fconnecting the sixth source region203fand the sixth drain region205f. The sixth source region203fand the sixth drain region205fextend in two opposite directions with respect to the sixth channel region201f.

The seventh transistor T7includes the seventh active layer20gand a seventh gate G7. The seventh active layer20gincludes a seventh source region203g, a seventh drain region205g, and a seventh channel region201gconnecting the seventh source region203gand the seventh drain region205g. The seventh source region203gand the seventh drain region205gextend in two opposite directions with respect to the seventh channel region201g.

With reference toFIG.7, structures21and22in the first semiconductor layer2are active layers of adjacent sub-pixels. That is to say,FIG.7mainly shows an active layer of one sub-pixel.

As shown inFIG.8andFIG.9, the reset control line R1, the scanning line S1, the first light-emitting control line E1, and the light-emitting element reset line R2are all located in the first conductive layer3. A first conductive structure CG1is also located in the first conductive layer3. An overlap between the first conductive structure CG1and the first semiconductor layer2forms the third gate G3of the third transistor T3. An overlap between the reset control line R1and the first semiconductor layer2forms the first gate G1of the first transistor T1. A part of an overlap between the scanning line S1and the first semiconductor layer2forms the second gate G2of the second transistor T2, and another part of the overlap between the scanning line S1and the first semiconductor layer2forms the fourth gate G4of the fourth transistor T4. A part of an overlap between the first light-emitting control line E1and the first semiconductor layer2forms the fifth gate G5of the fifth transistor T5, and another part of the overlap between the first light-emitting control line E1and the first semiconductor layer2forms the sixth gate G6of the sixth transistor T6. An overlap between the light-emitting element reset line R2and the first semiconductor layer2forms the seventh gate G7of the seventh transistor T7.

The first conductive structure CG1also forms an electrode plate of the second capacitor C2, such as the first electrode plate C2a. That is, the first conductive structure CG1serve as both the gate of the third transistor T3and one electrode plate of the second capacitor C2.

The first light-emitting control line E1has a widened portion E1W between the fifth gate G5and the sixth gate G6. As shown inFIG.9, in an extension direction of the first light-emitting control line E1, i.e., in a first direction X, the widened portion E1W is between the fifth gate G5and the sixth gate G6. A size of the widened portion E1W along a second direction Y is greater than a size of other portions of the first light-emitting control line E1along the second direction Y. The size of the widened portion E1W along the second direction Y is greater than a size of each of the fifth gate G5and the sixth gate G6along the second direction Y. The first light-emitting control line E1extends along the first direction X, and the second direction Y intersects with the first direction X. For example, the second direction Y is perpendicular to the first direction X.

For example, an orthographic projection of the first electrode plate C1aof the first capacitor on the base substrate is between an orthographic projection of the first electrode plate C2aof the second capacitor on the base substrate and an orthographic projection of the light-emitting element reset line R2on the base substrate in the second direction Y.

As shown inFIG.9, a spacing PD1between the first gate G1and the first electrode plate C1aof the first capacitor in the first direction X is smaller than a spacing PD2between the seventh gate G7and the first electrode plate C1aof the first capacitor in the first direction X. It will be noted that the spacing PD1between the first gate G1and the first electrode plate C1aof the first capacitor in the first direction X may be represented by a distance between a midline of the first electrode gate G1in the first direction X and a midline of the first electrode plate C1aof the first capacitor in the first direction X. Similarly, a spacing PD2between the seventh gate G7and the first electrode plate C1aof the first capacitor in the first direction X may be represented by a distance between a midline of the seventh gate G7in the first direction X and the midline of the first electrode plate C1aof the first capacitor in the first direction X.

As shown inFIG.10, the second light-emitting control line E2is located in the second conductive layer4. The second electrode plate C1bof the first capacitor C1and the second electrode plate C2bof the second capacitor C2are also located in the second conductive layer4.

For example, the orthographic projection of the second electrode plate C1bof the first capacitor C1at least partially overlaps with an orthographic projection of the widened portion E1W of the first light-emitting control line E1on the base substrate. The overlap between the first light-emitting control line E1and the second electrode plate C1bof the first capacitor C1forms the first electrode plate C1aof the first capacitor C1. That is to say, at least a part of the widened portion E1W forms the first electrode plate C1aof the first capacitor C1.

For example, the orthographic projection of the second electrode plate C2bof the second capacitor C2at least partially overlaps with an orthographic projection of the first conductive structure CG1on the base substrate. The overlap between the first conductive structure CG1and the second electrode plate C2bof the second capacitor C2forms the second electrode plate C2aof the second capacitor C2.

FIG.21schematically shows an orthographic projection of the overlap between the first electrode plate C1aand the second electrode plate C1bof the first capacitor C1on the base substrate, and an orthographic projection of the overlap between the first electrode plate C2aand the second electrode plate C2bof the second capacitor C2on the base substrate.

In the embodiments of the present disclosure, the orthographic projection of the second electrode plate C1bof the first capacitor on the base substrate substantially covers the orthographic projection of the widened portion E1W on the base substrate, and an area of the orthographic projection of the first electrode plate C2aof the second capacitor on the base substrate is greater than an area of the orthographic projection of the widened portion E1W on the base substrate.

In the embodiments of the present disclosure, the first electrode plate C1ain the first conductive layer3and the second electrode plate C1bin the second conductive layer4are disposed opposite to each other. It will be understood that there is an insulation layer or a dielectric layer formed between the first conductive layer3and the second conductive layer4. In this way, the first capacitor C1is formed by the first electrode plate C1ain the first conductive layer3and the second electrode plate C1bin the second conductive layer4. Similarly, the second capacitor C2is formed by the first electrode plate C2ain the first conductive layer3and the second electrode plate C2bin the second conductive layer4.

As shown inFIG.21, an area of the orthographic projection of the overlap between the first electrode plate C1aand the second electrode plate C1bof the first capacitor C1on the base substrate is smaller than an area of the orthographic projection of the overlap between the first electrode plate C2aand the second electrode plate C2bof the second capacitor C2on the base substrate. In this way, a capacitance value of the first capacitor C1is smaller than a capacitance value of the second capacitor C2. For example, a ratio of the capacitance value of the second capacitor C2to the capacitance value of the first capacitor C1may be within a range of 5 to 20, for example, within a range of 5 to 10, a range of 8 to 10, or a range of 8 to 9. In the embodiments of the present disclosure, by setting the capacitance value of the first capacitor, the first capacitor may maintain a constant potential at the node N2. In this way, even when the frequency of the driving signal changes, flicker and/or ghost may be prevented by controlling the voltage at the first electrode of the driving transistor. In addition, by setting a large capacitance value of the second capacitor C2, it is possible to improve the performance of the display panel and reduce a power consumption of the display panel. In the embodiments of the present disclosure, the ratio of the capacitance value of the second capacitor C2to the capacitance value of the first capacitor C1may be within the range of 5 to 20, especially within the range of 8 to 10, which is conducive to the improvement of the stability of the driving transistor, and when the driving frequency changes, the display device may prevent flicker and/or ghost by controlling the voltage at the first electrode of the driving transistor.

With reference toFIG.10andFIG.12, the second electrode plate C2bincludes a through hole4H, which exposes a part of the first conductive structure CG1, so as to electrically connect the third gate G3of the third transistor T3to other components.

For example, the through hole4H exposes at least a part of the first electrode plate C2aof the second capacitor. For example, a ratio of an area of the orthographic projection of the second electrode plate C1bof the first capacitor on the base substrate to an area of an orthographic projection of the through hole4H on the base substrate is within a range of 1.1 to 5. That is, the area of the orthographic projection of the second electrode plate C1bof the first capacitor on the base substrate is slightly greater than the area of the orthographic projection of the through hole4H on the base substrate.

As shown inFIG.9toFIG.12, the orthographic projection of the widened portion E1W of the first light-emitting control line E1, which forms the first electrode plate C1a, on the base substrate has a substantially rectangular shape. The orthographic projection of the second electrode plate C1bon the base substrate has a substantially rectangular shape. The “substantially rectangular shape” here includes shapes such as a rectangle, a rectangle with at least one chamfer, and rectangles with at least one rounded corner.

As shown inFIG.10, a second light-emitting control line42is located in the second conductive layer4.

For example, an orthographic projection of the second light-emitting control line42on the base substrate, the orthographic projection of the second electrode plate C2bof the second capacitor on the base substrate, and the orthographic projection of the second electrode plate C1bof the first capacitor on the base substrate are disposed at intervals along the second direction Y. The orthographic projection of the second electrode plate C1bof the first capacitor on the base substrate and the orthographic projection of the second light-emitting control line42on the base substrate are respectively located on both sides of the orthographic projection of the second electrode plate C2bof the second capacitor on the base substrate in the second direction.

As shown inFIG.11, the second semiconductor layer5includes the eighth active layer20hcorresponding to the eighth transistor T8. For example, the eighth active layer20hof the eighth transistor T8substantially extends along the second direction Y in the figures. The eighth active layer20hincludes an eighth source region203h, an eighth drain region205h, and an eighth channel region201hconnecting the eighth source region203hand the eighth drain region205h. The eighth source region203hand the eighth drain region205hextend in two opposite directions with respect to the eighth channel region201h.

For example, the second semiconductor layer5may include an oxide semiconductor material, such as a low-temperature poly-silicon oxide semiconductor material (abbreviated as LTPO). The active layer of each transistor may include a channel region, a source region and a drain region. The channel region may be a non-doped region, or a doping type of the channel region is different from a doping type of the source region and a doping type of the drain region, and the channel region therefore has semiconductor characteristics. The source region and the drain region are respectively located on both sides of the channel region and doped with impurities, and are thus conductive. Impurities may be varied depending on whether the TFT is an N-type transistor or a P-type transistor.

As shown inFIG.13, another second light-emitting control line62is provided in the third conductive layer6. For example, each of the two second light-emitting control lines42and62may transmit the second light-emitting control signal. In some examples, the two second light-emitting control lines42and62may be electrically connected to each other in a peripheral area of the display substrate, thereby forming the second light-emitting control line E2as shown.

With reference toFIG.12, an overlap between the second light-emitting control line42and the second conductive layer4forms a bottom gate G81of the eighth transistor T8. An overlap between the other second light-emitting control line62and the second conductive layer4forms a top gate G82of the eighth transistor T8. That is, the eighth transistor T8has a dual gate structure. In the embodiments of the present disclosure, the eighth transistor T8is implemented as an oxide semiconductor transistor with the dual gate structure, which is conducive to the reduction of the leakage current of the node N1, thereby stabilizing the potential at the node Ni.

With reference toFIG.13, the first initial voltage line Vi1is located in the third conductive layer6. That is, a part of the second light-emitting control line E2and the first initial voltage line Vi1are located in the same layer. In the embodiments of the present disclosure, by providing the second light-emitting control line E2in the third conductive layer6, a separate light-emitting control signal may be provided for the eighth transistor T8.

With reference toFIG.17, the display substrate further includes the second initial voltage line Vi2located in the fourth conductive layer7and a plurality of conductive portions. For example, the plurality of conductive portions may include a first conductive portion71, a second conductive portion72, a third conductive portion73, a fourth conductive portion74, a fifth conductive portion75, a sixth conductive portion76and a seventh conductive portion77.

With reference toFIG.19, the display substrate further includes the data line D1, the first voltage line V1, and a first conductive member81, which are all located in the fifth conductive layer8.

With reference toFIG.15toFIG.20, a plurality of via holes are schematically shown. One end of the first conductive portion71is electrically connected to the source region203aof the first transistor T1through a via hole VH2, and the other end of the first conductive portion71is electrically connected to the first initial voltage line Vi1through a via hole VH1. In this way, the source of the first transistor T1is electrically connected to the first initial voltage line Vi1, and the first initial voltage may be applied to the source of the first transistor T1.

One end of the second conductive portion72is electrically connected to the source region203dof the fourth transistor T4through a via hole VH3, and the other end of the second conductive portion72is electrically connected to the data line D1through a via hole VH4. In this way, the source of the fourth transistor T4is electrically connected to the data line D1, and the data signal may be applied to the source of the fourth transistor T4.

One end of the third conductive portion73is electrically connected to the source region203bof the second transistor T2through a via hole VH5, and the other end of the third conductive portion73is electrically connected to the drain region205hof the eighth transistor T8through a via hole VH6. In this way, the source of the second transistor T2may be electrically connected to the drain of the eighth transistor T8.

One end of the fourth conductive portion74is electrically connected to the source region203hof the eighth transistor T8through a via hole VH7, and the other end of the fourth conductive portion74is electrically connected to the third gate G3through a via hole VH8and the through hole4H. In this way, the node N1shown inFIG.4is formed, so as to electrically connect the source of the eighth transistor T8, the third gate G3and the electrode plate C2aof the second capacitor C2.

For example, an orthographic projection of the via hole VH8on the base substrate falls within the orthographic projection of the through hole4H on the base substrate. In this way, the via hole VH8and the through hole4H expose a part of the third gate G3below, so as to electrically connect the third gate G3and the source of the eighth transistor T8.

One end of the fifth conductive portion75is electrically connected to the electrode plate C1bof the first capacitor through a via hole VH10, and the other end of the fifth conductive portion75is electrically connected to the drain region205dof the fourth transistor T4and the drain region205cof the third transistor T3through a via hole VH9. In this way, the node N2shown inFIG.4is formed, so as to electrically connect the drain of the fourth transistor T4, the drain of the third transistor T3and the electrode plate C1bof the first capacitor C1. A first part of the sixth conductive portion76is electrically connected to the drain region205eof the fifth transistor T5through a via hole VH11, a second part of the sixth conductive portion76is electrically connected to the electrode plate C2bof the second capacitor C2through a via hole VH12, and a third part of the sixth conductive portion76is electrically connected to the first voltage line V1through a via hole VH13. In this way, the high voltage VDD may be applied to the drain of the fifth transistor T5and the electrode plate C2bof the second capacitor C2.

With reference toFIG.17, an orthographic projection of the fifth conductive portion75on the base substrate is between an orthographic projection of the fourth conductive portion74on the base substrate and an orthographic projection of the sixth conductive portion76on the base substrate.

For example, the sixth conductive portion76may include a first part and a second part, where an orthographic projection of the first part on the base substrate has a shape of an inverse L, and an orthographic projection of the second part on the base substrate has a shape approximately to a rectangle, hexagon or octagon. The first part of the sixth conductive portion76and the second part of the sixth conductive portion76are interconnected to form an integral structure.

For example, the orthographic projection of the fifth conductive portion75on the base substrate overlaps with an orthographic projection of each of the first electrode plate and the second electrode plate of the second capacitor C2on the base substrate, In this way, in the light-emitting stage, one of the electrode plates of the second capacitor C2is connected to a low potential, so as to further pull down the potential at the node N1, which is conducive to the light-emitting and display.

In the embodiments of the present disclosure, the seventh conductive portion77is electrically connected to the source region203fof the sixth transistor T6and the drain region205gof the seventh transistor T7through a via hole VH14, that is, the node N4inFIG.4is led upwards. The seventh conductive portion77in the fourth conductive layer7and the first conductive member81in the fifth conductive layer8are electrically connected to each other through a via hole. The anode of the organic light-emitting diode100may be electrically connected to the first conductive member81through a via hole. In this way, the source of the sixth transistor T6and the drain of the seventh transistor T7may be electrically connected to the anode of the organic light-emitting diode100.

For example, the orthographic projection of the first electrode plate C1aof the first capacitor on the base substrate is between the orthographic projection of the sixth conductive portion76on the base substrate and the orthographic projection of the seventh conductive portion77on the base substrate in the first direction X. Any two of the orthographic projection of the first electrode plate C1aof the first capacitor on the base substrate, the orthographic projection of the sixth conductive portion76on the base substrate and the orthographic projection of the seventh conductive portion77on the base substrate are spaced apart from each other. The orthographic projection of the second electrode plate C1bof the first capacitor on the base substrate partially overlaps with the orthographic projection of the seventh conductive portion77on the base substrate.

For example, the orthographic projection of the first voltage line V1on the base substrate covers the orthographic projection of the fourth conductive portion74on the base substrate; and/or, the orthographic projection of the first voltage line V1on the base substrate covers the orthographic projection of the active layer of the eighth transistor T8on the base substrate.

Other film layers (such as insulation layers) of the display substrate according to the embodiments of the present disclosure will be described below in combination with plan views (such asFIG.7toFIG.20) and a sectional view (FIG.22).

In an exemplary embodiment, the display substrate may include the first semiconductor layer2disposed on the base substrate1, and a first gate insulation layer107disposed on a side of the first semiconductor layer2away from the base substrate1. For example, the first gate insulation layer107may be formed of silicon oxide with a thickness of approximately 1000 to 2000 angstroms.

The display substrate may include the first conductive layer3disposed on a side of the first gate insulation layer107away from the base substrate1, and a first interlayer dielectric layer108disposed on a side of the first conductive layer3away from the base substrate1. For example, the first interlayer insulation layer108may be formed of silicon nitride with a thickness of approximately 1000 to 2000 angstroms.

The display substrate may include the second conductive layer4disposed on a side of the first interlayer dielectric layer108away from the base substrate1, and a second interlayer dielectric layer109disposed on a side of the second conductive layer4away from the base substrate1. For example, the second interlayer dielectric layer109may be formed of an insulation material such as silicon nitride.

The display substrate may include a buffer layer110disposed on a side of the second interlayer dielectric layer109away from the base substrate1, the second semiconductor layer5disposed on a side of the buffer layer110away from the base substrate1, and a second gate insulation layer116disposed on a side of the second semiconductor layer5away from the base substrate1.

The display substrate may include the third conductive layer6disposed on a side of the second gate insulation layer116away from the base substrate1, a third interlayer dielectric layer111disposed on a side of the third conductive layer6away from the base substrate1, the fourth conductive layer7disposed on a side of the third interlayer dielectric layer111away from the base substrate1, a first planarization layer112disposed on a side of the fourth conductive layer7away from the base substrate1, the fifth conductive layer8disposed on a side of the first planarization layer112away from the base substrate1, a second planarization layer113disposed on a side of the fifth conductive layer8away from the base substrate1, an anode layer208disposed on a side of the second planarization layer113away from the base substrate1, and a pixel definition layer114disposed on a side of the anode layer208away from the base substrate1.

For example, the planarization layers may be formed of polyimide (PI).

At least some embodiments of the present disclosure further provide a display panel, which includes the display substrate as described above. For example, the display panel may be an OLED display panel.

With reference toFIG.1, at least some embodiments of the present disclosure further provide a display device, which may include the display substrate as described above.

The display device may include any device or product with a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a headset, an electronic dress, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, and a smart watch), a television, etc.

It will be understood that according to the embodiments of the present disclosure, the display panel and the display device have all the characteristics and advantages of the display substrate mentioned above, and for details, reference may be made to the above description, which will not be repeated here.

Although some embodiments of the general technical concept of the present disclosure have been shown and described, those of ordinary skill in the art will understand that changes may be made to these embodiments without departing from the principle and spirit of the general technical concept. The scope of the present disclosure is defined by the claims and their equivalents.