Patent ID: 12224319

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, (some) embodiment(s) of the present invention will be described. The embodiment(s) do(es) not limit the invention according to the claims, and all the combinations of the features described in the embodiment(s) are not necessarily essential to means provided by aspects of the invention.

In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as an “upper” side, and the other side is referred to as a “lower” side. One of two principal surfaces of a substrate, layer or another member is referred to as an upper surface, and the other is referred to as a lower surface. The directions toward the “upper” and “lower” sides are not limited by the direction of gravity or the direction in which an implemented semiconductor device is mounted on a substrate or the like.

In this specification, technical matters may be described using orthogonal coordinate axes of X-axis, Y-axis and Z-axis. In this specification, an X-Y plane is a plane parallel to the upper surface of a semiconductor substrate, and Z-axis is along the depth direction of the semiconductor substrate.

While each example embodiment shows a case where a first conductivity type is N-type and a second conductivity type is P-type, the first conductivity type may be P-type and the second conductivity type may be N-type. In that case, the respective conductivity types of substrates, layers, regions and the like in each example embodiment will be of the opposite polarity.

In this specification, doping concentration refers to the concentration of impurities acting as donors or acceptors. In this specification, doping concentration may refer to the difference in concentration of donors and acceptors. If the doping concentration distribution of a doped region has a peak, the value of the peak may be used as the doping concentration of the doped region. If the doping concentration of a doped region is approximately uniform, or the like, an average value of the doping concentration of the doped region may be used as the doping concentration.

FIG.1ashows a partial view of an example of the upper surface of a semiconductor device100according to the present embodiment. The semiconductor device100of the present example is a semiconductor chip including a transistor section70and a diode section80. The transistor section70includes transistors such as IGBTs. The diode section80includes diodes such as FWDs (Free Wheel Diodes). The transistor section70and the diode section80are arranged in an array along a predetermined array direction (Y-axis direction in the present example) on the upper surface of the semiconductor substrate. In the example ofFIG.1a, the transistor section70and the diode section80are alternately arranged along the array direction. The transistor section70and the diode section80may be in contact or spaced apart in the array direction. The transistor section70may include a boundary section90. In the example ofFIG.1a, the boundary section90is a region of the transistor section70positioned at the boundary with the diode section80.FIG.1ashows the upper surface of the chip in the vicinity of an end of the chip, and does not show the other regions.

WhileFIG.1ashows an active region of the semiconductor substrate in the semiconductor device100, the semiconductor device100may include an edge termination structure surrounding the active region. The active region refers to a region in which currents flow when the semiconductor device100is controlled into ON state. The edge termination structure relaxes the concentration of electric fields near the upper surface the semiconductor substrate. The edge termination structure includes, for example, a guard ring, field plate or RESURF structure, or combinations thereof.

The semiconductor device100of the present example is provided inside the semiconductor substrate, and includes gate trench portions40, dummy trench portions well regions11, emitter regions12, base regions14and contact regions15, exposed on the upper surface of the semiconductor substrate. The semiconductor device100of the present example also includes an emitter electrode52and a gate metal layer50provided above the upper surface of the semiconductor substrate. The emitter electrode52and the gate metal layer50are separated from each other.

Although not shown inFIG.1a, an interlayer dielectric film is provided between the upper surface of the semiconductor substrate and each of the emitter electrode52and the gate metal layer50. In the present example, the interlayer dielectric film is provided with contact holes56, contact holes49and contact holes54penetrating the interlayer dielectric film.

The emitter electrode52is connected to dummy conductive portions inside the dummy trench portions30via the contact holes56. Connecting portions25, formed of a conductive material such as impurity-doped polysilicon, may be provided between the emitter electrode52and the dummy conductive portions. An insulating film such as an oxide film is provided between the connecting portions25and the upper surface of the semiconductor substrate.

The gate metal layer50contacts a gate runner48through a contact hole49. The gate runner48is formed of impurity-doped polysilicon or the like. The gate runner48is connected to gate conductive portions inside the gate trench portions40at the upper surface of the semiconductor substrate. The gate runner48is not connected to the dummy conductive portions inside the dummy trench portions30. In the present example, the gate runner48is provided from a position below the contact hole49to edge portions of the gate trench portions40. An insulating film such as an oxide film is provided between the gate runner48and the upper surface of the semiconductor substrate. At the edge portions of the gate trench portions40, the gate conductive portions are exposed on the upper surface of the semiconductor substrate and contact the gate runner48.

The emitter electrode52and the gate metal layer50are formed of a metal-containing material. For example, at least a partial region of each electrode is formed of aluminum or an aluminum-silicon alloy. Each electrode may include a barrier metal formed of titanium, a titanium compound or the like in a layer below the region formed of aluminum or the like, and may include a plug formed of tungsten or the like in the contact hole.

One or more gate trench portions40and one or more dummy trench portions30are arrayed at predetermined intervals along a predetermined array direction (Y-axis direction in the present example). Each gate trench portion40may have two extending portions39extending along an extending direction (X-axis direction in the present example) parallel to the upper surface of the semiconductor substrate and orthogonal to the array direction, and a connecting portion41connecting the two extending portions39. At least a part of the connecting portion41is preferably provided in a curved shape. Connecting the ends of the two extending portions39of the gate trench portion40can relax the concentration of electric fields at the ends of the extending portions39. In this specification, each extending portion39of the gate trench portion40may be regarded as one gate trench portion40. The gate runner48may be connected to the gate conductive portions at the connecting portions41of the gate trench portions40.

At least one dummy trench portion30may be provided between the extending portions39of each gate trench portion40. The dummy trench portion30may have a U-shape on the upper surface of the semiconductor substrate, in like manner with the gate trench portion40. That is, in the present example, the dummy trench portion30may have two extending portions29extending along the extending direction and a connecting portion31connecting the two extending portions29.

At least one dummy trench portion30may have the shape of a straight line whose longitudinal direction is the extending direction (the X-axis direction) on the upper surface of the semiconductor substrate. In the example ofFIG.1a, U-shaped dummy trench portions30are provided in the diode section80and the boundary section90and straight line-shaped dummy trench portions30are provided in at least a part of the transistor section70.

The emitter electrode52is provided above the gate trench portions40, the dummy trench portions30, the well regions11, the emitter regions12, the base regions14and the contact regions15. The well regions11are of the second conductivity type. In the present example, the well regions11are of (P+)-type, as an example. Each well region11is provided over a predetermined area from an end closer to the gate metal layer50in the active region. The diffusion depth of the well region11may be deeper than the lower ends of the gate trench portions40and the dummy trench portions30. Partial regions of the gate trench portions40and the dummy trench portions30closer to the gate metal layer50are provided in the well region11. The bottoms of the extending-direction ends of the gate trench portions40and the dummy trench portions30may be covered by the well region11.

In the transistor section70, the contact holes54are provided above the contact regions15and the emitter regions12. In the diode section80, the contact hole54is provided above the base region14. No contact hole54is arranged above the base regions14and well regions11arranged on both X-axis-direction ends.

In a direction parallel to the upper surface of the semiconductor substrate, mesa portions are provided in direct contact with the trench portions in the Y-axis direction. A mesa portion may be the portion of the semiconductor substrate that is sandwiched between two adjacent trench portions and extends from the upper surface of the semiconductor substrate to the greatest depth of the bottom portion of each trench portion. Each extending portion of the trench portions may be regarded as one trench portion. That is, the region sandwiched between two extending portions may be regarded as a mesa portion.

In the transistor section70, except in the boundary section90, first mesa portions60are provided in contact with trench portions. In the boundary section90, a second mesa portion62is provided in contact with trench portions. In the diode section80, third mesa portions64are provided in the regions sandwiched between adjacent dummy trench portions30and in contact with the dummy trench portions30. Base regions14, as an example, are provided at both X-axis-direction ends of the first mesa portions60, the second mesa portion62and the third mesa portions64. Note thatFIG.1aonly shows one of the X-axis-direction ends.

On the upper surface of the first mesa portions60, first-conductivity-type emitter regions12are provided in contact with gate trench portions40. In the present example, the emitter regions12are of (N+)-type, as an example. On the upper surface the first mesa portions60, second-conductivity-type contact regions15having a higher doping concentration than the base regions14are also provided. In the present example, the contact regions15are of (P+)-type, as an example. In the first mesa portions60, the emitter regions12and the contact regions15may be alternately provided along the extending direction of the gate trench portions40. The emitter regions12and the contact regions15may be provided in contact with each other.

On the upper surface of the first mesa portions60, the emitter regions12may be provided in contact with or spaced apart from dummy trench portions30. In the example ofFIG.1a, the emitter regions12are provided in contact with dummy trench portions30.

On the upper surface of the first mesa portions60, the emitter regions12and the contact regions15are provided also below the contact hole54. On the upper surface of the first mesa portions60, the emitter regions12and the contact regions15are provided continuously in the Y-axis direction from one of the trench portions sandwiching each first mesa portion60to the other trench portion. The emitter regions12and the contact regions15may be in contact with both of the two trench portions sandwiching each first mesa portion60. In the example ofFIG.1a, two trench portions sandwiching each first mesa portion60are a gate trench portion40and a dummy trench portion30.

A second-conductivity-type contact region15having a higher doping concentration than the base regions14is provided on the upper surface of the second mesa portion62. The contact region15may be provided between the base regions14at both X-axis-direction ends of the second mesa portion62. The contact region15may be provided in the entire region sandwiched between the base regions14at both ends.

On the upper surface of the second mesa portion62, the contact region15is provided also below the contact hole54. On the upper surface of the second mesa portion62, the contact region15is provided continuously in the Y-axis direction from one of the dummy trench portions30sandwiching the second mesa portion62to the other dummy trench portion30. The contact region15may be in contact with both of the two dummy trench portions30sandwiching the second mesa portion62.

In the present example, two contact regions15are provided in the region of the upper surface of each third mesa portion64that is sandwiched between the base regions14at both X-axis-direction ends. The respective contact regions15may be arranged in contact with the base regions14at both ends. On the upper surface of the third mesa portion64, a base region14is provided in the region sandwiched between the contact regions15. The base region14may be provided in the entire region sandwiched between the contact regions15.

On the upper surface of the third mesa portion64, the base region14is provided also below the contact hole54. On the upper surface of the third mesa portion64, the base region14is provided continuously in the Y-axis direction from one of the dummy trench portions30sandwiching the third mesa portion64to the other dummy trench portion30. The base region14may be in contact with both of the two dummy trench portions30.

In the semiconductor device100of the present example, dummy trench portions30are provided in the diode section80. In the present example, each dummy trench portion30arranged in the diode section80has straight line-shaped extending portions29connected at a connecting portion31. The third mesa portions64are provided in the regions sandwiched between the extending portions29.

Emitter regions12may or may not be provided in the third mesa portions64. In the present example, no emitter region12is provided in the third mesa portions64. In each third mesa portion64, the contact regions15and the base regions14are provided from one of the dummy trench portions30sandwiching the third mesa portion64to the other dummy trench portion30. That is, on the upper surface of the semiconductor substrate, the Y-axis direction width of each third mesa portion64is equal to the Y-axis direction width of each contact region15or base region14provided in the third mesa portion64.

The diode section80includes a first-conductivity-type cathode region82on the lower surface side of the semiconductor substrate. InFIG.1a, the region in which the cathode region82is provided is indicated by dashed lines. The diode section80may be the region in which the cathode region82is projected onto the upper surface of the semiconductor substrate. The region in which the cathode region82is projected onto the upper surface of the semiconductor substrate may be spaced apart, toward the inner side of the third mesa portion64, from the contact region15of the third mesa portion64. The inner side of the third mesa portions64refers to the side closer to the center of the third mesa portion64in the X-axis direction. A second-conductivity-type collector region may be provided in the region in direct contact with the lower surface of the semiconductor substrate and in which the cathode region82is not provided. The transistor section70may be the region in which trench portions or mesa portions provided in the region in which the collector region is projected onto the upper surface of the semiconductor substrate.

The semiconductor device100includes, inside the semiconductor substrate, first-conductivity-type accumulation regions16having a higher doping concentration than the drift region. The dopant of the accumulation regions16is of the same conductivity type as the dopant of the drift region. The dopant of the accumulation regions16is accumulated at a higher concentration than the dopant for the drift region. The accumulation regions16are arranged below base regions14. The accumulation regions16may be arranged above the lower end of each trench portion. The accumulation regions16may be in contact with gate trench portions40. Providing the accumulation regions16can enhance the carrier injection-enhancement effect (IE effect) to reduce the ON voltage. InFIG.1a, the region in which the accumulation regions16are provided is indicated by long dashed short dashed lines. Note that, while in the dashed lines traverse regions of trench portions inFIG.1a, the accumulation regions16may not be formed in the regions overlapping with the trench portions.

In first mesa portions60, second-conductivity-type floating regions17are provided below the accumulation regions16. The floating regions17are in contact with gate trench portions40. In the present example, the floating regions17are of (P+)-type, as an example. The doping concentration of the floating regions17is higher than the doping concentration of the base regions14. InFIG.1a, the region in which the floating regions17are provided in top view of the semiconductor substrate is indicated by dashed lines. Note that, while the dashed lines traverse regions of trench portions inFIG.1a, the floating regions17may not be formed in the regions overlapping with the trench portions.

As shown inFIG.1a, in top view of the semiconductor substrate, each floating region17is provided in a part of the first mesa portion60in the array direction (Y-axis direction) orthogonal to the extending direction of the gate trench portions40. That is, each floating region17is not provided over the entire width of the first mesa portion60in the Y-axis direction, but is provided over a partial region thereof in the Y-axis direction. In the example ofFIG.1a, each floating region17is provided continuously from the position contacting a gate trench portion40to a predetermined Y-axis direction position within the first mesa portion60. The floating region17is not provided at a position farther from the gate trench portion40than the predetermined position.

The predetermined position may be between two trench portions sandwiching the first mesa portion60. The two trench portions sandwiching the first mesa portion60are respectively referred to as a first trench portion and a second trench portion. The first trench portion is a gate trench portion40contacting the floating region17. The second trench portion may be a dummy trench portion30or may be a gate trench portion40. In the present example, the second trench portion is a dummy trench portion30. The predetermined position is a position spaced apart, in the array direction, from the second trench portion. In top view of the semiconductor substrate, the array-direction end of each floating region17is referred to as a floating region end13. The floating region end13may be positioned at the predetermined position. That is, the floating region17may be spaced apart from the second trench portion.

The predetermined Y-axis direction position in each first mesa portion60may or may not overlap with the contact hole54in top view of the semiconductor substrate.FIG.1ashows an example where the predetermined position does not overlap with the contact hole54. Each floating region17may be provided closer to the gate trench portion40than the contact hole54in the Y-axis direction.

Each floating region17may be provided continuously from one of the contact regions15provided at both X-axis-direction ends of the first mesa portion60to the other. As described above, the floating regions17may be provided in contact with gate trench portions40.

The positions of both X-axis-direction ends of the floating regions17may coincide with or different from the positions of both X-axis-direction ends of the accumulation regions16.FIG.1ashows a case where the X-axis-direction end of the floating regions17and the X-axis-direction end of the accumulation regions16are at different positions.

In the first mesa portions60, the floating regions17may not be in contact with dummy trench portions30. Floating regions17may not be provided in the second mesa portion62and the third mesa portions64.

FIG.1bshows an example of the cross section along a-a′ inFIG.1a. The cross section along a-a′ is a Y-Z plane passing through emitter regions12of first mesa portions60and the contact region15of the second mesa portion62. The semiconductor device100of the present example includes, in the cross section along a-a′, the semiconductor substrate10, an interlayer dielectric film38, the emitter electrode52and a collector electrode24. The emitter electrode52is provided on the upper surfaces of the interlayer dielectric film38and the semiconductor substrate10.

The collector electrode24is provided on a lower surface23of the semiconductor substrate10. The emitter electrode52and the collector electrode24are formed of a conductive material such as a metal. In this specification, the direction connecting the emitter electrode52and the collector electrode24is referred to as the depth direction (Z-axis direction).

The semiconductor substrate10may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as gallium nitride, a gallium oxide substrate, or the like. In the present example, the semiconductor substrate10is a silicon substrate.

The semiconductor substrate10includes a first-conductivity-type drift region18. In the present example, the drift region18is of (N−)-type. The drift region18may be the remaining region of the semiconductor substrate10in which the other doped regions are not provided.

One or more gate trench portions40and one or more dummy trench portions are provided in the upper surface21of the semiconductor substrate10. Each trench portion is provided from the upper surface21to penetrate the base region14and reach the drift region18.

Each gate trench portion40includes a gate trench provided in the upper surface21, a gate insulating film42and a gate conductive portion44. The gate insulating film42is provided to cover the inner wall of the gate trench. The gate insulating film42may be formed by oxidizing or nitriding the semiconductor material of the inner wall of the gate trench. The gate conductive portion44is provided inside the gate trench and at an inner side relative to the gate insulating film42. That is, the gate insulating film42insulates the gate conductive portion44and the semiconductor substrate10from each other. The gate conductive portion44is formed of a conductive material such as polysilicon.

The gate conductive portion44includes, in the depth direction, a region facing at least adjacent base regions14with intervention of the gate insulating film42. In this cross section, the gate trench portion40is covered by the interlayer dielectric film38on the upper surface21. When a predetermined voltage is applied to the gate conductive portion44, a channel is formed as an inversion layer of electrons in the interfacial surface layer of the base region14contacting the gate trench.

In this cross section, the dummy trench portions30may have the same structure as the gate trench portions40. Each dummy trench portion30includes a dummy trench provided in the upper surface21, a dummy insulating film32and a dummy conductive portion34. The dummy insulating film32is provided to cover the inner wall of the dummy trench. The dummy conductive portion34is provided inside the dummy trench and provided at an inner side relative to the dummy insulating film32. The dummy insulating film32insulates the dummy conductive portion34and the semiconductor substrate10from each other.

The dummy conductive portion34may be formed of the same material as that of the gate conductive portion44. For example, the dummy conductive portion34is formed of a conductive material such as polysilicon. The dummy conductive portion34may have the same length in the depth direction as the gate conductive portion44. In this cross section, the dummy trench portions30are covered by the interlayer dielectric film38on the upper surface21. Note that, the bottom portions of the dummy trench portions30and gate trench portions40may have a shape of a downwardly-convex curved surface (curved line in the cross section).

In each first mesa portion60, one or more first-conductivity-type accumulation regions16are provided above the drift region18. The accumulation regions16may be in contact with gate trench portions40. If a plurality of accumulation regions16are provided, the accumulation regions16are arranged in an array along the Z-axis direction. The drift region18may be provided between the accumulation regions16. The accumulation regions16are of (N+)-type, as an example. The doping concentration of the accumulation regions16is higher than the doping concentration of the drift region18. Providing the accumulation regions16can enhance the carrier injection-enhancement effect (IE effect) to reduce the ON voltage.

In the first mesa portion60, one or more accumulation regions16may be in contact with or spaced apart from dummy trench portions30.FIG.1bshows an example where accumulation regions16are provided in contact with dummy trench portions30. Note that accumulation regions16may not be provided in the second mesa portion62and the third mesa portions64.

In each first mesa portion60, a second-conductivity-type base region14is provided above the accumulation regions16. The base region14may be in contact with a gate trench portion40. The base region14is of (N−)-type, as an example. In each first mesa portion60, the base region14may be provided in contact with a dummy trench portion30.

In the cross section along a-a′, in first mesa portions60, emitter regions12are provided in contact with the upper surface21of the semiconductor substrate10. The emitter regions12are in contact with a gate trench portion40. The doping concentration of the emitter regions12is higher than the doping concentration of the drift region18. In a Y-Z cross section passing through contact regions15in first mesa portions60, contact regions15are provided instead of the emitter regions12shown inFIG.1b. The contact regions15are exposed on the upper surface21of the semiconductor substrate10. The contact regions15may be in contact with a gate trench portion40and a dummy trench portion30.

In the second mesa portion62of the boundary section90, a second-conductivity-type base region14is provided above the drift region18. The base region14may be in contact with dummy trench portions30.

In the second mesa portion62, a contact region15is provided in contact with the upper surface21of the semiconductor substrate10. The contact region15may be in contact with or spaced apart from dummy trench portions30.FIG.1bshows an example where the contact region15is provided in contact with dummy trench portions30.

In each third mesa portion64of the diode section80, a second-conductivity-type base region14is provided above the drift region18. In each third mesa portion64, the base region14is provided in contact with the upper surface21. The base region14may be in contact with dummy trench portions30.

A first-conductivity-type buffer region20may be provided below the drift region18. The buffer region20is of (N+)-type, as an example. The doping concentration of the buffer region20is higher than the doping concentration of the drift region18. The buffer region20may serve as a field stop layer to prevent a depletion layer expanding from the lower surface side of the base region14from reaching the (P+)-type collector region22and the (N+)-type cathode region82.

In the transistor section70, a collector region22of (P+)-type is provided below the buffer region20and exposed on the lower surface23. In the diode section80, a cathode region82of (N+)-type is provided below the buffer region20and exposed on the lower surface23. In the boundary section90, either the collector region22or the cathode region82is provided below the buffer region20. In the present example, in the boundary section90, the collector region22is provided below the buffer region20.

Note that the diode section80is the region overlapping with the cathode region82in the direction perpendicular to the lower surface23. The transistor section70is the region overlapping with the collector region22in the direction perpendicular to the lower surface23and in which predetermined unit structures including emitter regions12and contact regions15are regularly arranged.

In a first mesa portion60of the transistor section70, a floating region17is provided below the accumulation region16. The floating region17is provided in contact with a gate trench portion40. The floating region17is provided in a part of the first mesa portion60in the array direction (Y-axis direction). The floating region17may be spaced apart from a dummy trench portion30, rather than contacting it.

The region between the floating region17and the dummy trench portion30may be the drift region18. The region between the floating region17and the accumulation region16may also be the drift region18. In this cross section, the floating region17may be surrounded by the gate trench portion40and the drift region18.

No floating region17may be provided for the dummy trench portions30of the second mesa portion62in the boundary section90. No floating region17may be provided for the dummy trench portions30of the third mesa portions64in the diode section80.

The doping concentration of the floating region17may be substantially equal to the doping concentration of the contact region15, or may be lower than or higher than the doping concentration of the contact region15. Note that the doping concentration of the floating region17is high to an extent that an inversion layer of electrons (channel) is not formed in the interface with the gate trench portion40when a gate voltage is applied to the gate conductive portion44. As an example, the doping concentration of the floating region17may be between 1×1017/cm3and 5×1020/cm3, inclusive.

The floating region17is not in contact with either the collector electrode24or the emitter electrode52. The floating region17may or may not be continuous with the base region14as a P-type region.

FIG.2ashows the paths of electron current and displacement current in a semiconductor device150according to a first comparative example. The semiconductor device150of the first comparative example includes one accumulation region16in a first mesa portion60of the transistor section70. In the first comparative example, no floating region17is provided.FIG.2ashows current paths during turn-on. During turn-on, the voltage of the gate conductive portion44gradually rises from 0 [V]. Then, in the base region14in the vicinity of the gate trench portion40, negative charge is induced to form a channel.

Electron current, rather than hole current, mainly flows during an early period of turn-on. The early period refers to the period that begins immediately before gate voltage Vg reaches a threshold voltage and ends before entering a Miller period, in which Vg is constant at approximately the value of the threshold voltage. When Vg becomes near the threshold voltage, a channel begins to open and the injection of electrons into the drift region18begins.

In the first comparative example ofFIG.2a, electrons moving downward from the channel first begin to flow in the negative Y-axis direction (the direction from the vicinity of the gate trench portion40toward the center of the first mesa portion60) in the first accumulation region16. However, in the drift region18below the first accumulation region16, an accumulation layer of electrons is already formed in the vicinity of the gate trench portion40(the threshold voltage for an accumulation layer of electrons to be formed in an N-type region is much smaller than the threshold voltage for an inversion layer in a P-type region), and therefore impedance is lower in the vicinity of the gate trench portion40than in the drift region18. Thus, electron current mainly flows in the vicinity of the gate trench portion40.

When electrons reach the collector region22on the back side, the injection of holes from the collector region22to the buffer region20and the drift region18begins. In this manner, holes are accumulated in the vicinity of the lower ends of trench portions. As an example, holes have a concentration between 1×1016/cm3and 5×1018/cm3, inclusive, in the region from the vicinity of the lower end of the gate trench portion40to the side portion of the dummy trench portion30below the first accumulation region16.

Holes are accumulated at the lower end of the gate trench portion40and the lower end of the dummy trench portion30. In particular, since the dummy conductive portion34has the same potential as the emitter electrode52, an inversion layer of holes is easily formed at the side wall of the dummy trench portion30. Holes injected from the collector region22concentrate in the vicinity of this inversion layer of holes. Holes are distributed continuously from the dummy trench portion30to the lower end of the gate trench portion40. Due to such distribution of holes, a large displacement current flows into the vicinity of the lower end of the gate trench portion40during turn-on.

The displacement current generated due to the accumulation of holes causes charging of the gate conductive portion44opposing across the gate insulating film42. The charging of the gate conductive portion44causes a momentary increase in Vg of the gate metal layer. The larger the displacement current is, the more the gate conductive portion44is charged, and the more quickly the potential of the gate conductive portion44increases. As a result, the potential of the gate conductive portion44momentarily exceeds the gate threshold.

When the potential of the gate conductive portion44momentarily exceeds the gate threshold, the injection of large amounts of electrons and holes begins, and the current flowing between the collector electrode24and the emitter electrode52(CE current) increases. The rate of decrease in the voltage between the collector electrode24and the emitter electrode52(CE voltage), (dVce/dt), increases as a function of the change rate of the increasing CE current. The larger the displacement current is, the larger (dVce/dt) is. In particular, the smaller the amount of accumulated holes that flow toward the emitter electrode52is, the larger the displacement current is, and the larger the momentary increase in the potential of the gate conductive portion44is. Thus, in the first comparative example ofFIG.2a, (dVce/dt) is large, and also electromagnetic noise is significant.

FIG.2bshows the paths of electron current and displacement current in a semiconductor device160according to a second comparative example. The semiconductor device160of the second comparative example includes a first accumulation region16-1and a second accumulation region16-2in a first mesa portion of the transistor section70. The second accumulation region16-2is provided below the first accumulation region16-1. In the semiconductor device160of the second comparative example, the doping concentration of the second accumulation region16-2is higher than the doping concentration of the first accumulation region16-1. In the second comparative example, no floating region17is provided.

Electrons, after passing through the channel, first begin to flow in the negative Y-axis direction (the direction from the vicinity of the gate trench portion40toward the center of the first mesa portion60) in the first accumulation region16-1. In the present example, since the second accumulation region16-2has a higher doping concentration than the first accumulation region16-1, impedance for electron current is lower along the path of directly flowing from the first accumulation region16-1to the second accumulation region16-2than along the path of flowing from the vicinity of the center of the first accumulation region16-1, returning to the vicinity of the gate trench portion40, and reaching the second accumulation region16-2. Thus, the electron current easily flows from the vicinity of the center of the first accumulation region16-1to the second accumulation region16-2without returning to the vicinity of the gate trench portion40.

Holes are easily accumulated in a high hole concentration region87, a region below the first accumulation region16and in direct contact with the gate trench portion40. Also, electron current flows in the vicinity of the center of the first mesa portion60rather than the vicinity of the gate trench portion40, so that the accumulation of holes in the high hole concentration region87is facilitated. This facilitates the flowing of electron current in the vicinity of the center of the first mesa portion60.

As the electron current flows in the vicinity of the center of the first mesa portion60, the hole distribution in the vicinity of the bottom portion of the first mesa portion60is divided at the vicinity of the center of the first mesa portion60. Thus, holes closer to the dummy trench portion30than the path of electron current do not flow in the vicinity of the gate trench portion40. The division of the hole distribution at the central portion of the first mesa portion60reduces the accumulation of holes at the lower end of the gate trench portion40. As a result, the displacement current can be reduced. Due to the reduced displacement current, the charging of the gate conductive portion44is also reduced, and the momentary increase in Vg of the gate metal layer is also reduced. This reduces the rate of decrease in CE voltage (dVce/dt).

The accumulation region16, provided in the vicinity of the base region14, generates a negative capacitance between the gate and the collector (CG capacitance). In the semiconductor device160of the second comparative example, while the rate of decrease in CE voltage (dVce/dt) can be reduced as described above, providing two accumulation regions16may increase the CG capacitance. The increased CG capacitance worsens the trade-off between the ON voltage and turn-off loss of the transistor section70.

FIG.3shows an example of the paths of electron current and displacement current in the semiconductor device100according to the present embodiment.FIG.3shows an example of the paths of electron current and displacement current when a floating region17is provided in contact with a gate trench portion40.

In the semiconductor device100of the present example, electrons moving downward from the channel first begin to flow in the negative Y-axis direction (the direction from the vicinity of the gate trench portion40toward the center of the first mesa portion60) in the first accumulation region16. However, in the drift region18below the first accumulation region16, an accumulation layer of electrons is already formed in the vicinity of the gate trench portion40, and thus impedance is lower in the vicinity of the gate trench portion40than in the drift region18. Thus, the electron current mainly flows in the vicinity of the gate trench portion40toward a lower portion of the semiconductor substrate10.

The floating region17has a larger resistance against electron current than the drift region18. As the semiconductor device100of the present example includes the floating region17below the accumulation region16, the electron current flowing in the vicinity of the gate trench portion40toward a lower portion of the semiconductor substrate10is bent in its path by the floating region17, and follows a path of flowing from the vicinity of the gate trench portion40into the vicinity of the center of the first mesa portion60.

As the electron current flows in the vicinity of the center of the first mesa portion60, the hole distribution in the vicinity of the bottom portion of the first mesa portion60is divided at the vicinity of the center of the first mesa portion60. Thus, holes closer to the dummy trench portion30than the path of electron current do not flow in the vicinity of the gate trench portion40. The division of the hole distribution at the vicinity of the center of the first mesa portion60reduces the accumulation of holes at the lower end of the gate trench portion40. As a result, the displacement current can be reduced. Due to the reduced displacement current, the charging of the gate conductive portion44is also reduced, and the momentary increase in Vg of the gate metal layer is also reduced. This reduces the rate of decrease in CE voltage (dVce/dt).

Further, in the semiconductor device100of the present example, providing the floating region17allows electron current to flow in the vicinity of the center of the first mesa portion60even with only one accumulation region16. Thus, the increase in the CG capacitance can be better prevented than in the case where a plurality of accumulation regions16are provided along the Z-axis direction as in the semiconductor device160of the second comparative example. That is, in the semiconductor device100of the present example, the increase in CG capacitance can be reduced while reducing the rate of decrease in CE voltage (dVce/dt). Thus, in the semiconductor device100of the present example, the turn-on loss can be reduced while reducing the rate of decrease in CE voltage (dVce/dt). Also, the trade-off between the ON voltage and the turn-off loss can be maintained.

Note that the operations of the semiconductor devices described with reference toFIG.2atoFIG.3are operations in the transistor section70, and it is apparent that a semiconductor device including no diode section80operates similarly. That is, even if the semiconductor device100includes no diode section80, the effect of providing the floating region17occurs. The semiconductor device100may not include the diode section.

FIG.4ashows an example of the time waveforms of gate voltage Vg and CE voltage Vce during turn-on. InFIG.4a, the respective characteristics of the semiconductor device100of the present example, the semiconductor device150of the first comparative example and the semiconductor device160of the second comparative example are indicated by solid lines, dashed lines and long dashed short dashed lines. Note that the waveforms for the first comparative example150overlap with the waveforms for the semiconductor device100except in the portions where Vg and Vce transition over time.

FIG.4bis an enlarged view of transitioning waveforms of gate voltage Vg and CE voltage Vce in the time waveforms ofFIG.4a. However, inFIG.4b, the scale and position of the axis of CE voltage Vce are changed. As shown inFIG.4aandFIG.4b, in the semiconductor device100, the changes in gate voltage Vg and CE voltage Vce during turn-on are gentler than in the semiconductor device150of the first comparative example. Thus, in the semiconductor device100of the present example, the turn-on loss can be reduced more than in the semiconductor device150of the first comparative example. Also, the trade-off between the ON voltage and the turn-off loss can be maintained.

In the semiconductor device160of the second comparative example, the changes in gate voltage Vg and CE voltage Vce during turn-on are further gentler than in the semiconductor device100of the present example. However, as described above, the CG capacitance is increased in the semiconductor device160of the second comparative example. The increased CG capacitance worsens the trade-off between the ON voltage and turn-off loss of the transistor section70.

FIG.5ashows an example of the cross section along b-b′ inFIG.1a. The cross section along b-b′ is a Y-Z plane passing through emitter regions12in the transistor section70. The semiconductor device100of the present example includes, in the cross section along b-b′, the semiconductor substrate10, the interlayer dielectric film38, the emitter electrode52and the collector electrode24. The emitter electrode52is provided on the upper surfaces of the interlayer dielectric film38and the semiconductor substrate10.

The semiconductor device100of the present example includes, in the cross section along b-b′, an emitter region12provided in contact with the upper surface21. The emitter region12is in contact with a gate trench portion40in the Y-axis direction. A base region14is provided below the emitter region12. The base region14is in contact with the gate trench portion40in the Y-axis direction. An accumulation region16is provided below the base region14. The accumulation region16is in contact with the gate trench portion40in the Y-axis direction. The drift region18is provided below the accumulation region16. The buffer region20is provided below the drift region18. The collector region22is provided below the buffer region20. The collector electrode24is provided on the lower surface23.

The semiconductor device100of the present example includes a floating region17provided in contact with the gate trench portion40. The floating region17may be provided below the accumulation region16and spaced apart from the accumulation region16. At least a part of the floating region17in the depth direction of the semiconductor substrate10may be provided in contact with the bottom portion of the gate trench portion40. The bottom portion of the gate trench portion40will be described in detail with reference toFIG.5b.

Width Wgd is the Z-axis direction width from the upper surface21to the end of the bottom portion of the gate trench portion40, that is, the depth of the gate trench portion40from the upper surface21. Width Wfd is the Z-axis direction width from the upper surface21to the upper end of the floating region17. Width Wb is the Z-axis direction width of the base region14in the transistor section70. Width Wb may be the Z-axis direction width of the base region14at the position contacting the gate trench portion40. Width Wbf is the Z-axis direction width from the lower end of the base region14to the upper end of the floating region17. Width Wbf may be the Z-axis direction width from the lower end of the base region14to the lower end of the floating region17at the position contacting the gate trench portion40.

Width Wm is the mesa width of the first mesa portion60. Width Wm may be the mesa width of the first mesa portion60at the upper surface21of the semiconductor substrate10. Width Wf is the Y-axis direction width of the floating region17. Width Wf may be the maximum value of the Y-axis direction width of the floating region17. Width Wef is the Y-axis direction width of the drift region18at the depth at which the floating region17is provided. Width Wef may be the Y-axis direction width from the Y-axis-direction end of the floating region17to the dummy trench portion30. Width Wfv is the Z-axis direction width of the floating region17, that is, the thickness of the floating region17. Width Wfv may be the maximum value of the Z-axis direction width of the floating region17. Width Wfv may also be the Z-axis direction width of the floating region17at the position contacting the gate trench portion40. As an example, width Wfv is between 0.1 μm and 1.0 μm, inclusive. Width Wfv may also be between 0.3 μm and 0.7 μm, inclusive.

The floating region17is provided in a part of the first mesa portion60in the Y-axis direction. That is, Wf<Wm. In the example ofFIG.5a, the floating region17is provided over width Wf from the position contacting the gate trench portion40to a predetermined Y-axis direction position in the first mesa portion60. The floating region17is not provided at a position farther from the gate trench portion40than the predetermined position.

Width Wbf may be larger than width Wb. By making width Wbf larger than width Wb, when the transistor section70is in the ON state, a depletion layer expanding in the depth direction of the semiconductor substrate10from the junction interface between the base region14and the drift region18becomes less prone to reach the floating region17. Thus, in the semiconductor device100of the present example, electron current can flow in the vicinity of the center of the first mesa portion60without being blocked. Width Wbf may be twice or more width Wb. As an example, width Wbf is between 2.5 μm and 3.5 μm, inclusive.

Holes are accumulated in the floating region17at a high concentration. Thus, if the floating region17is provided in contact with the accumulation region16in the Z-axis direction, the holes accumulated in the floating region17easily pass through the accumulation region16in the upward direction. This lowers the IE effect of the accumulation region16. In the semiconductor device100of the present example, the floating region17is spaced apart from the accumulation region16in the Z-axis direction, and thus the lowering of the IE effect can be reduced. This can reduce the increase in ON voltage Von of the transistor section70.

FIG.5bis an enlarged view of region A inFIG.5a.FIG.5bshows the bottom portion,89, of the gate trench portion40on an enlarged scale. In the present example, the bottom portion89of the gate trench portion40is a region in which the line indicating the cross-sectional outline of the gate trench portion40forms a curved line that is convex downward (in the negative Z-axis direction) in the Y-Z plane. That is, the bottom portion89of the gate trench portion40is the region of the gate trench portion40below line s-s′ in the Y-axis direction inFIG.5b. Line s-s′ passes through singular point T. Singular point T is a point at which the cross-sectional shape of the side wall43of the gate trench portion40changes from an approximately straight line to a curved line. Singular point T may also be a point at which the slope of the side wall43begins to change. The bottom portion89of the gate trench portion40may also be defined as the region of 0.5 μm upward (in the positive Z-axis direction) from the lowest end of the gate trench portion40, or the bottom portion89of the gate trench portion40may also be defined as the region of 0.1×Wgd upward from the lowest end of the gate trench portion40.

At least a part of the floating region17in the depth direction of the semiconductor substrate10may be provided in contact with the bottom portion89of the gate trench portion40. That is, the Z-axis direction position of the floating region17may be such that the upper end of the floating region17is above (i.e. closer to the upper surface21of the semiconductor substrate10than) line s-s′ and the lower end of the floating region17is below (i.e. closer to the lower surface23of the semiconductor substrate10than) line s-s′ in the Y-Z plane. The Z-axis direction position of the upper end of the floating region17may coincide with line s-s′. The Z-axis direction position of the lower end of the floating region17may coincide with line s-s′.

FIG.6ashows an example of the relationship between width Wfd and ON voltage Von for the semiconductor device100according to the present example. InFIG.6a, width Wfd is indicated as a ratio relative to width Wgd. That is, the horizontal axis inFIG.6aindicates Wfd/Wgd [%]. Also, ON voltage Von of the semiconductor device100is indicated as a ratio relative to Von of the semiconductor device150of the first comparative example. That is, the vertical axis inFIG.6aindicates Von of the semiconductor device100/Von of the semiconductor device150[%]. InFIG.6a, the position of the bottom portion89of the gate trench portion40is in a range in which width ratio Wfd/Wgd=90% to 100%. Width Wfv of the floating region17is a width corresponding to approximately 10% on the horizontal axis ofFIG.6a.

By arranging the floating region17in the vicinity of the bottom portion89of the gate trench portion40, the increase in ON voltage Von relative to Von of the first comparative example can be reduced to less than 10%, as shown inFIG.6a. As an example, at least a part of the floating region17in the Z-axis direction may be arranged at a depth contacting the bottom portion89of the gate trench portion40. In this case, the remaining portion of the floating region17other than the part in the Z-axis direction may be arranged above the bottom portion89of the gate trench portion40. The floating region17may also be arranged such that its entirety in the Z-axis direction is in contact with the bottom portion89of the gate trench portion40.

FIG.6bshows an example of the relationship between width Wfd and Qg, the integral value of the gate current during turn-on (charge), for the semiconductor device100of the present example. The horizontal axis inFIG.6bindicates Wfd/Wgd [%], in like manner withFIG.6a. InFIG.6b, charge Qg for the semiconductor device100is indicated as a ratio relative to charge Qg for the semiconductor device160of the second comparative example. That is, the vertical axis inFIG.6bindicates Qg of the semiconductor device100/Qg of the semiconductor device160[%].

In semiconductor devices, a larger value of Qg indicates a larger CG capacitance. As shown inFIG.6b, whatever depth the floating region17is provided at, charge Qg for the semiconductor device100can be reduced by about 40% relative to Qg for the second comparative example. That is, the CG capacitance of the semiconductor device100can be reduced.

FIG.6cshows an example of the relationship between width Wfd and the rate of decrease in CE voltage (dVce/dt) during turn-on for the semiconductor device100according to the present example. The horizontal axis inFIG.6cindicates Wfd/Wgd [%], in like manner withFIG.6a. InFIG.6c, (dVce/dt) is indicated as a ratio relative to (dVce/dt) of the first comparative example. That is, the vertical axis inFIG.6cindicates (dVce/dt) of the semiconductor device100/(dVce/dt) of the semiconductor device150[%].

In the semiconductor device100of the present example, as shown inFIG.6c, the voltage decrease rate (dVce/dt) indicates values of about 80% or more in the section in which Wfd/Wgd is smaller than about 70% (or 73%) and in the section in which Wfd/Wgd is larger than 95%. In contrast, dVce/dt is decreased in the section in which Wfd/Wgd is 70% or more (or 73% or more) and smaller than 100%. In particular, dVce/dt is abruptly decreased in the section in which Wfd/Wgd is 95% or less. Also, the voltage decrease rate (dVce/dt) takes a local minimum of about 50% in the range in which Wfd/Wgd is approximately from 80% to 92%. The range of Wfd/Wgd in which dVce/dt takes the local minimum approximately coincides with the range in which at least a part of the floating region17in the Z-axis direction is arranged at the bottom portion89of the gate trench portion40.

Arranging the floating region17in the vicinity of the bottom portion89of the gate trench portion40allows electron current to easily flow through the center of the mesa portion. Thus, in the vicinity of the bottom portion89of the gate trench portion40where holes are accumulated, the region in which holes are distributed can be easily divided by the electron current, so that the displacement current is easily reduced. Thus, the voltage decrease rate (dVce/dt) can be reduced. As an example, as shown inFIG.6c, the rate of decrease in CE voltage (dVce/dt) can be reduced by about 50% relative to the voltage decrease rate (dVce/dt) of the first comparative example.

When the floating region17is arranged at a deeper position than the bottom portion89of the gate trench portion40(in a region where Wfd/Wgd is larger than 100% inFIG.6c), the gate trench portion40and the floating region17are spaced apart, and electron current flows between the gate trench portion40and the floating region17. In this case, the displacement current cannot be reduced. Thus, as shown inFIG.6c, by making Wfd/Wgd larger than 100%, the voltage decrease rate (dVce/dt) of the semiconductor device100is abruptly increased and indicates substantially the same value as the voltage decrease rate (dVce/dt) of the first comparative example. Consequently, providing at least a part of the floating region17in the Z-axis direction in contact with the bottom portion89of the gate trench portion40can significantly improve the rate of decrease in CE voltage.

Consequently, Wfd/Wgd may be 70% or more and less than 100%. Further, Wfd/Wgd may be 73% or more, or may be 80% or more. Wfd/Wgd may be 95% or less, or may be 92% or less.

FIG.7shows an example of doping concentration distribution in the cross section along c-c′ inFIG.5a. InFIG.7, the vertical axis is a logarithmic axis and the horizontal axis is a linear axis. As shown inFIG.7, in the semiconductor device100of the present example, the doping concentration of the floating region17may be higher than the doping concentration of the accumulation region16. The doping concentration of the floating region17may be higher by a factor of 10 or more, or higher by 100 or more than the doping concentration of the accumulation region16. As an example, the doping concentration of the accumulation region16is 1×1017/cm3. The doping concentration of the floating region17may be a concentration of 1×1019/cm3or more.

As shown inFIG.7, in the semiconductor device100of the present example, the doping concentration of the floating region17may be higher than the doping concentration of the base region14. The doping concentration of the floating region17may be higher by a factor of 10 or more, or higher by 100 or more than the doping concentration of the base region14. As an example, the doping concentration of the base region14is 3×1017/cm3. The doping concentration of the floating region17may be a concentration of 1×1019/cm3or more.

FIG.8ashows an example of the relationship between the doping concentration of the floating region17and ON voltage Von for the semiconductor device100according to the present example. InFIG.8a, at least a part of the floating region17in the Z-axis direction is provided in contact with the bottom portion89of the gate trench portion40. InFIG.8a, ON voltage Von for each value of the concentration of the floating region17is indicated as a ratio relative to ON voltage Von for the concentration of the floating region17being 1×1014/cm3. That is, the vertical axis inFIG.8aindicates ON voltage Von/(ON voltage Von for the concentration of the floating region17being 1×1014/cm3) [%].

As shown inFIG.8a, ON voltage Von of the semiconductor device100of the present example begins to increase when the doping concentration of the floating region17exceeds 1×1017/cm3. Von indicates 104% to 105% when the doping concentration is between 1×1020/cm3and 1×1021/cm3. That is, the increase in ON voltage Von can be reduced to less than 5% even when the doping concentration of the floating region17is increased by 103times to 104times. Thus, it may be considered that ON voltage Von of the semiconductor device100of the present example is substantially free from the effect of the doping concentration of the floating region17.

FIG.8bshows an example of the relationship between the doping concentration of the floating region17and the rate of decrease in CE voltage (dVce/dt) for the semiconductor device100according to the present example. InFIG.8b, at least a part of the floating region17in the Z-axis direction is provided in contact with the bottom portion89of the gate trench portion40. InFIG.8b, the rate of decrease in CE voltage (dVce/dt) for each value of the concentration of the floating region17is indicated as a ratio relative to the rate of decrease in CE voltage (dVce/dt) for the concentration of the floating region17being 1×1014/cm3. That is, the vertical axis inFIG.8bindicates the rate of decrease in CE voltage (dVce/dt)/the rate of decrease in CE voltage (dVce/dt) for the concentration of the floating region17being 1×1014/cm3[%].

As shown inFIG.8b, the rate of decrease in CE voltage (dVce/dt) of the semiconductor device100of the present example begins to decrease when the doping concentration of the floating region17exceeds 1×1016/cm3, or particularly 8×1016/cm3. When the doping concentration reaches 3×1017/cm3, the rate of decrease in CE voltage (dVce/dt) indicates about 55% of the rate of decrease in CE voltage (dVce/dt) for the doping concentration being 1×1014/cm3. Further, when the doping concentration exceeds 1×1018/cm3, the rate of decrease in CE voltage (dVce/dt) indicates about 50% of the rate of decrease in CE voltage (dVce/dt) for the doping concentration being 1×1014/cm3. That is, in the semiconductor device100of the present example, the rate of decrease in CE voltage (dVce/dt) can be significantly reduced by setting the doping concentration of the floating region17to 1×1018/cm3or more.

The doping concentration of the floating region17may be 8×1016/cm3or more, may be 3×1017/cm3or more, may be 1×1018/cm3or more, or may be 1×1019/cm3or more. The doping concentration of the floating region17may be 3×1020/cm3or less.

Meanwhile, in order to reduce the increase in ON voltage to about 3% or less, the upper limit of the doping concentration of the floating region17may be set to 1×1019/cm3or less (or less than 1×1019/cm3), as can be seen fromFIG.8a. In this case, the lower limit of the doping concentration of the floating region17may be 1×1017/cm3, as can be seen fromFIG.8a.

FIG.9ashows an example of the relationship between the ratio of width Wf relative to width Wm (Wf/Wm [%]) and ON voltage Von for the semiconductor device100according to the present example.FIG.9ashows the relationship between (Wf/Wm [%]) and ON voltage Von when at least a part of the floating region17in the Z-axis direction is provided in contact with the bottom portion89of the gate trench portion40. That (Wf/Wm) is 0% means that Wf is zero, that is, the floating region17is not provided. Also, that (Wf/Wm) is 100% means that the floating region17is provided over the entire mesa width. InFIG.9a, ON voltage Von is indicated as a ratio relative to ON voltage Von for (Wf/Wm) being 0%. That is, the vertical axis inFIG.9aindicates ON voltage Von/ON voltage Von for (Wf/Wm) being 0% [%].

When (Wf/Wm) is about 60%, ON voltage Von is increased by about 20% relative to when (Wf/Wm) being 0%. When (Wf/Wm) is about 85%, ON voltage Von is increased by about 40% relative to when (Wf/Wm) is 0%. When (Wf/Wm) is between 10% and 50%, inclusive, that is, width Wf is between 0.1 times and 0.5 times, inclusive, of mesa width Wm, the increase in ON voltage Von can be reduced to less than 20%.

FIG.9bshows an example of the relationship between the ratio of width Wf relative to width Wm (Wf/Wm [%]) and charge Qg accumulated in the gate metal layer for the semiconductor device100according to the present example.FIG.9bshows the relationship between (Wf/Wm [%]) and charge Qg when at least a part of the floating region17in the Z-axis direction is provided in contact with the bottom portion89of the gate trench portion40. InFIG.9b, charge Qg is indicated as a ratio relative to charge Qg for (Wf/Wm) being 0%. That is, the vertical axis inFIG.9bindicates charge Qg/charge Qg for (Wf/Wm) being 0% [%].

When (Wf/Wm) is about 60%, charge Qg is decreased by about 5% relative to when (Wf/Wm) is 0%. When (Wf/Wm) exceeds about 60%, charge Qg has a tendency to be increased. That is, charge Qg indicates a local minimum value when (Wf/Wm) is about 60%. Consequently, it is apparent that charge Qg accumulated at the gate metal layer of the semiconductor device100of the present example can be reduced by providing the floating region17.

FIG.9cshows an example of the relationship between the ratio of width Wf relative to width Wm (Wf/Wm [%]) and the rate of decrease in CE voltage (dVce/dt) for the semiconductor device100according to the present example.FIG.9cshows the relationship between (Wf/Wm [%]) and the rate of decrease in CE voltage (dVce/dt) when at least a part of the floating region17in the Z-axis direction is provided in contact with the bottom portion89of the gate trench portion40. InFIG.9c, the rate of decrease in CE voltage (dVce/dt) is indicated as a ratio relative to the rate of decrease in CE voltage (dVce/dt) for (Wf/Wm) being 0%. That is, the vertical axis inFIG.9cindicates the rate of decrease in CE voltage (dVce/dt)/the rate of decrease in CE voltage (dVce/dt) for (Wf/Wm) being 0% [%].

In the semiconductor device100of the present example, the rate of decrease in CE voltage (dVce/dt) indicates a local minimum value when (Wf/Wm) is about 30%. When (Wf/Wm) is about 30%, the rate of decrease in CE voltage (dVce/dt) can be reduced to about 50% relative to when (Wf/Wm) is 0%. As described with reference toFIG.3, providing the floating region17allows electron current to flow along the path from the vicinity of the gate trench portion40to the vicinity of the center of the first mesa portion60. The electron current flowing in the vicinity of the center of the first mesa portion60divides the hole distribution, reducing the displacement current. Thus, the rate of decrease in CE voltage (dVce/dt) can be reduced.

If (Wf/Wm) is excessively small (for example, smaller than 10%), electron current does not sufficiently flow in the central vicinity and the hole distribution is not sufficiently divided, the rate of decrease in CE voltage (dVce/dt) is not sufficiently reduced. Conversely but similarly, if (Wf/Wm) is excessively large (for example, larger than 60%), electron current does not sufficiently flow in the central vicinity and the hole distribution is not sufficiently divided, the rate of decrease in CE voltage (dVce/dt) is not sufficiently reduced. When (Wf/Wm) is about 30%, electron current can flow in the central vicinity, so that the hole distribution is divided and the rate of decrease in CE voltage (dVce/dt) indicates the local minimum value. For this reason, (Wf/Wm) is preferably between 10% and 60%, inclusive. (Wf/Wm) may be 20% or more, or may be 25% or more. (Wf/Wm) may be 50% or less, may be 40% or less, or may be 35% or less.

Width Wf is preferably smaller than width Wef. Width Wf may be between 11% (1/9) of width Wef and 50% of width Wef, inclusive. Width Wf may be between 0.07 μm and 0.35 μm, inclusive.

FIG.10shows another example of the cross section along b-b′ inFIG.1a. The semiconductor device100shown inFIG.10is different from the semiconductor device100shown inFIG.5ain that a plurality of accumulation regions16are provided along the depth direction of the semiconductor substrate10. Structures other than the accumulation regions16may be the same as those of the semiconductor device100described with reference toFIG.5a. The semiconductor device100of the present example includes an accumulation region16-1, an accumulation region16-2and an accumulation region16-3, arranged along the depth direction. The drift region18may be provided in the respective regions sandwiched between the accumulation region16-1and the accumulation region16-2in the Z-axis direction and sandwiched between the accumulation region16-2and the accumulation region16-3in the Z-axis direction.

In a first mesa portion60, a floating region17is provided below the third accumulation region16-3. The floating region17is in contact with a gate trench portion40. The floating region17is provided in only a part of the first mesa portion in the Y-axis direction. That is, the floating region17is not provided over the entire width of the first mesa portion60in the Y-axis direction, but is provided over a partial region thereof in the Y-axis direction. In the example ofFIG.10, the floating region17is provided continuously from the position contacting the gate trench portion to a predetermined Y-axis direction position within the first mesa portion60, and is not provided at a position farther from the gate trench portion40than the predetermined position.

FIG.11shows an example of doping concentration distribution in the cross section along d-d′ inFIG.10. As shown inFIG.11, in the semiconductor device100of the present example, the doping concentration of the third accumulation region16-3provided at the lowest position may be lower than the doping concentration of the first accumulation region16-1arranged at the uppermost position. The doping concentrations of the first accumulation region16-1, the second accumulation region16-2and the third accumulation region16-3may decrease toward the third accumulation region16-3arranged at the lower position.

The doping concentration of the second accumulation region16-2may be between ⅓ and ⅔, inclusive, of the doping concentration of the first accumulation region16-1. The doping concentration of the third accumulation region16-3may be 1/10 or more of the doping concentration of the first accumulation region16-1. The doping concentration of the third accumulation region16-3may be 3/10 or less of the doping concentration of the first accumulation region16-1. The doping concentration of the first accumulation region16-1may be between 8×1016/cm3and 2×1017/cm3, inclusive. As an example, the doping concentration of the first accumulation region16-1is 1×1017/cm3. The doping concentration of the second accumulation region16-2may be between 3×1016/cm3and 7×1016/cm3, inclusive. As an example, the doping concentration of the second accumulation region16-2is 5×1016/cm3. The doping concentration of the third accumulation region16-3may be between 1×1016/cm3and 3×1016/cm3, inclusive. As an example, the doping concentration of the third accumulation region16-3is 2×1016/cm3.

In the semiconductor device100of the present example, the doping concentrations of the accumulation regions16decrease toward the third accumulation region16-3arranged at the lower position. Thus, in the semiconductor device100, the increase in CG capacitance can be reduced relative to when the first accumulation region16-1, the second accumulation region16-2and the third accumulation region16-3are provided to have substantially equal doping concentrations, or to have doping concentration increasing toward the third accumulation region16-3arranged at the lower position.

In the semiconductor device100of the present example, the floating region17is provided below the third accumulation region16-3, and thus electron current flows in the vicinity of the center of the first mesa portion60as shown inFIG.3. Also, the hole distribution is divided at the vicinity of the center of the first mesa portion60, and thus the displacement current generated due to the charging of the gate conductive portion44can be reduced. Thus, the rate of decrease in CE voltage (dVce/dt) can be reduced. That is, in the semiconductor device100of the present example, the increase in CG capacitance can be reduced while reducing the rate of decrease in CE voltage (dVce/dt). Thus, in the semiconductor device100of the present example, the turn-on loss can be reduced while reducing the rate of decrease in CE voltage (dVce/dt). Also, the trade-off between the ON voltage and the turn-off loss can be maintained.

FIG.12ashows a partial view of another example of the upper surface of the semiconductor device100according to the present embodiment. The semiconductor device100shown inFIG.12ais different from the semiconductor device100shown inFIG.1ain that, as compared with the semiconductor device100of shown inFIG.1a, floating regions17are additionally provided in contact with the dummy trench portions30below the accumulation regions16in the first mesa portions60of the transistor section70. InFIG.12a, the region in which the floating regions17are provided in top view of the semiconductor substrate10is indicated by dashed lines.

As shown inFIG.12a, a floating region17is provided in a part of a first mesa portion60in the array direction (Y-axis direction). That is, the floating region17is not provided over the entire width of the first mesa portion60in the Y-axis direction, but is provided over a partial region thereof in the Y-axis direction. In the example ofFIG.12a, in the first mesa portion60, the floating region17is provided continuously from the position contacting a dummy trench portion30to a predetermined Y-axis direction position within the first mesa portion60. Also, in the first mesa portion60, the floating region17is provided continuously from the position contacting a gate trench portion40to a predetermined Y-axis direction position within the first mesa portion60. The end position of the floating region17contacting the gate trench portion40is different in the Y-axis direction from the end position of the floating region17contacting the dummy trench portion30. Another floating region17is not provided between the two floating regions17in the Y-axis direction.

The positions of the Y-axis-direction ends of each floating region17may or may not overlap with the contact hole54in top view of the semiconductor substrate.FIG.12ashows an example where both of the end positions of each floating region17do not overlap with the contact hole54.

The floating region17contacting the dummy trench portion30may be provided continuously from one of the contact regions15provided at both X-axis-direction ends of the first mesa portion60to the other. As described above, the floating region17may be provided in contact with dummy trench portion30.

The positions of both X-axis-direction ends of the floating region17contacting the dummy trench portion30may coincide with or different from the positions of both X-axis-direction ends of the accumulation region16.FIG.12ashows a case where the X-axis-direction end of the floating region17contacting the dummy trench portion30and the X-axis-direction end of the accumulation region16are at different positions.

FIG.12bshows an example of the cross section along e-e′ inFIG.12a. The floating region17is provided in a part of the first mesa portion60in the Y-axis direction. That is, Wf<Wm. In the example ofFIG.12b, a floating region17contacting a dummy trench portion30is provided over width Wf from the position contacting the dummy trench portion30. Another floating region17contacting a gate trench portion40is provided over width Wf from the position contacting the gate trench portion40.

The floating region17provided in contact with the dummy trench portion30is spaced apart, in the Y-axis direction, from the floating region17provided in contact with the gate trench portion40. That is, the floating region17contacting the dummy trench portion30and the other floating region17contacting the gate trench portion40, provided in the same first mesa portion60, are not in contact with each other in the first mesa portion60.

The floating region17contacting the dummy trench portion30may be provided at substantially the same depth as the other floating region17contacting the gate trench portion40. The drift region18may be provided in the region sandwiched between the floating region17contacting the dummy trench portion30and the floating region17contacting the gate trench portion40in the Y-axis direction.

In the semiconductor device100of the present example, the floating region17provided in contact with the dummy trench portion30is spaced apart, in the Y-axis direction, from the floating region17provided in contact with the gate trench portion and thus electron current flows in the vicinity of the center of the first mesa portion at the depth of the floating regions17due to a similar effect to that inFIG.3. As the electron current flows in the vicinity of the center of the first mesa portion60, the hole distribution in the vicinity of the bottom portion of the first mesa portion60is divided at the vicinity of the center of the first mesa portion60, so that the accumulation of holes at the lower end of the gate trench portion40is reduced. Thus, the displacement current can be reduced. Thus, the rate of decrease in CE voltage (dVce/dt) can be reduced.

FIG.12cshows another example of the cross section along e-e′ inFIG.12a. The semiconductor device100shown inFIG.12cis different from the semiconductor device100shown inFIG.12bin that, as compared with the semiconductor device100shown inFIG.12b, a plurality of accumulation regions16are provided. The drift region18may be provided in the respective regions sandwiched between the accumulation region16-1and the accumulation region16-2in the Z-axis direction and sandwiched between the accumulation region16-2and the accumulation region16-3in the Z-axis direction. The doping concentrations of the accumulation region16-1, the accumulation region16-2and the accumulation region16-3may respectively be the same as the doping concentrations of the accumulation region16-1, the accumulation region16-2and the accumulation region16-3in the semiconductor device100shown inFIG.10.

The floating region17provided in contact with the dummy trench portion30is spaced apart, in the Y-axis direction, from the floating region17provided in contact with the gate trench portion40. The floating region17provided in contact with the dummy trench portion30may be provided at substantially the same depth as the floating region17provided in contact with the gate trench portion40.

In the semiconductor device100of the present example, a floating region17is provided in contact with a dummy trench portion30, and a plurality of accumulation regions16are provided. Thus, when holes accumulated in the floating region17contacting the dummy trench portion30move toward the upper surface21in the vicinity of the dummy trench portion30, they are easily accumulated in the accumulation regions16, which are provided above the floating region17. This can reduce the holes going out to the emitter electrode52.

In the semiconductor device100of the present example, the floating region17provided in contact with the dummy trench portion30is spaced apart, in the Y-axis direction, from the floating region17provided in contact with the gate trench portion and thus electron current flows in the vicinity of the center of the first mesa portion at the depth of the floating regions17, in like manner with the semiconductor device100shown inFIG.12b. Thus, the rate of decrease in CE voltage (dVce/dt) can be reduced, in like manner with the semiconductor device100shown inFIG.12b.

FIG.13ashows another example of the cross section along b-b′ inFIG.1a. The semiconductor device100shown inFIG.13ais different from the semiconductor device100shown inFIG.10in that, as compared with the semiconductor device100shown inFIG.10, the second accumulation region16-2and the third accumulation region16-3are spaced apart from the gate trench portion40. The drift region18may be provided in the respective regions sandwiched between the accumulation region16-1and the accumulation region16-2in the Z-axis direction and sandwiched between the accumulation region16-2and the accumulation region16-3in the Z-axis direction.

In the present example, width Ws1is the Y-axis direction width of the second accumulation region16-2, and width Ws2is the Y-axis direction width of the third accumulation region16-3. In the present example, width Ws1and width Ws2are both smaller than width Wm.

As described with reference toFIG.2b, the second accumulation region16-2provided below the first accumulation region16-1allows electron current, when beginning to return to the gate trench portion40from the vicinity of the center of the first accumulation region16-1, to easily flow in the vicinity of the center of the first mesa portion60. Thus, as long as the second accumulation region16-2is provided in the vicinity of the center of the first mesa portion60, even though not provided over the entire Y-axis direction length of the first mesa portion60, the path of electron current can be formed in the vicinity of the center of the first mesa portion60.

The third accumulation region16-3allows electron current, which easily flows in the vicinity of the center of the first mesa portion60by virtue of the second accumulation region16-2, to further easily flow in the vicinity of the center of the first mesa portion60. The electron current that begins to return to the gate trench portion from the second accumulation region16-2is smaller than the electron current that begins to return to the gate trench portion40from the first accumulation region16-1. Thus, width Ws2may be smaller than width Ws1.

Width Ws1and width Ws2may be between 60% and 90%, inclusive, of width Wm. Width Ws2may be smaller than or larger than width Ws1.FIG.13ashows an example where width Ws2is smaller than width Ws1.

The second accumulation region16-2and the third accumulation region16-3may be in contact with or spaced apart from the dummy trench portion30.FIG.13ashows an example where the second accumulation region16-2and the third accumulation region16-3are in contact with the dummy trench portion30.

FIG.13bshows another example of the cross section along b-b′ inFIG.1a. The semiconductor device100shown inFIG.13bis different from the semiconductor device100shown inFIG.10in that, as compared with the semiconductor device100shown inFIG.10, the second accumulation region16-2and the third accumulation region16-3are spaced apart from the dummy trench portion30. The drift region18may be provided in the respective regions sandwiched between the accumulation region16-1and the accumulation region16-2in the Z-axis direction and sandwiched between the accumulation region16-2and the accumulation region16-3in the Z-axis direction.

In the present example, width Ws1′ is the Y-axis direction width of the second accumulation region16-2, and width Ws2′ is the Y-axis direction width of the third accumulation region16-3. In the present example, width Ws1′ and width Ws2′ are both smaller than width Wm.

As described with reference toFIG.2b, in the semiconductor device100of the present example, electron current flows in the depth direction of the semiconductor substrate10in a region from the vicinity of the gate trench portion40to the vicinity of the center of the first mesa portion60. Thus, the second accumulation region16-2and the third accumulation region16-3may be spaced apart from the dummy trench portion as long as they are provided in the vicinity of the center of the first mesa portion60.

Width Ws1′ and width Ws2′ may be between 60% and 90%, inclusive, of width Wm. Width Ws2′ may be smaller than or larger than width Ws1′.FIG.13ashows an example where width Ws2′ is smaller than width Ws1′.

The second accumulation region16-2and the third accumulation region16-3may be in contact with or spaced apart from the gate trench portion40.FIG.13bshows an example where the second accumulation region16-2and the third accumulation region16-3are in contact with the gate trench portion40.

FIG.14shows another example of the cross section along b-b′ inFIG.1a. The semiconductor device100shown inFIG.14is different from the semiconductor device100shown inFIG.5ain that, as compared with the semiconductor device100shown inFIG.5a, no accumulation region16is provided. In the semiconductor device100the present example, width Wm, width Wf, width Wef, width Wgd, width Wfd, width Wb and width Wbf may be the same as those in the semiconductor device100shown inFIG.5a.

In the semiconductor device100of the present example as well, width Wbf may be larger than width Wb. By making width Wbf larger than width Wb, when the transistor section70is in the ON state, a depletion layer expanding in the depth direction of the semiconductor substrate10from the junction interface between the base region14and the drift region18becomes less prone to reach the floating region17. If the depletion layer reaches the floating region17, electron current would be blocked. In the semiconductor device100of the present example, since width Wbf is larger than width Wb, electron current can flow in the vicinity of the center of the first mesa portion without being blocked. Width Wbf may be twice or more width Wb. As an example, Width Wbf is 3 μm.

In the semiconductor device100of the present example, since no accumulation region16is provided, electron current continues to flow in the depth direction of the semiconductor substrate10in the vicinity of the gate trench portion40after passing through the channel in the base region14in the vicinity of the gate trench portion40. As described with reference toFIG.3, the electron current continuing to flow in the depth direction of the semiconductor substrate10in the vicinity of the gate trench portion40is bent in its path by the floating region17and follows a path of flowing from the vicinity of the gate trench portion40into the vicinity of the center of the first mesa portion60.

As the electron current flows in the vicinity of the center of the first mesa portion60, the hole distribution in the vicinity of the bottom portion of the first mesa portion60is divided at the vicinity of the center of the first mesa portion60, so that the accumulation of holes at the lower end of the gate trench portion40is reduced. As a result, the displacement current can be reduced. In the semiconductor device100of the present example, due to the reduced displacement current, the charging of the gate conductive portion44is also reduced, and the momentary increase in gate voltage Vg is also reduced. This reduces the rate of decrease in CE voltage (dVce/dt).

Further, in the semiconductor device100of the present example, no accumulation region16is provided in contact with the gate trench portion40. Thus, in the semiconductor device100of the present example, the increase in CG capacitance can be better prevented than in the semiconductor device100shown inFIG.5a. That is, in the semiconductor device100of the present example, the increase in CG capacitance can be reduced while reducing the rate of decrease in CE voltage (dVce/dt). Thus, in the semiconductor device100of the present example, the turn-on loss can be reduced while reducing the rate of decrease in CE voltage (dVce/dt). Also, the trade-off between the ON voltage and the turn-off loss can be maintained.

FIG.15shows another example of arrangement of floating regions17in first mesa portions60.FIG.15is a partial top view of first mesa portions60. InFIG.15, the regions in which the floating regions17are provided are hatched with oblique lines. Structures other than the floating regions17may be the same as those in the semiconductor device100of any of the aspects described with reference toFIG.1atoFIG.14. For example, while floating regions17are provided for a gate trench portion but not provided for a dummy trench portion30inFIG.15, floating regions17similar to those of the gate trench portion40may be provided for the dummy trench portion30.

In the present example, the floating regions17are discretely arranged along the extending direction of the gate trench portion40(X-axis direction). That is, a plurality of floating regions17are arranged at intervals in the X-axis direction. Width Wf, the Y-axis direction width of the floating region17, is the same as that of the floating region17of any of the aspects described with reference toFIG.1atoFIG.14.

Each floating region17may be provided over a larger portion in the X-axis direction than the emitter region12. That is, each floating region17may be arranged to cover the entire portion of the emitter region12in the X-axis direction. In this case, the X-axis-direction ends of the floating region17are arranged at positions overlapping with contact regions15. The region sandwiched between two floating regions17in the X-axis direction is referred to as a gap19. The entire gap19may overlap with a contact region15. The floating regions17may not be formed below the contact region15. In particular, in the region below the center of the contact region15along the extending direction, the gap19is arranged and the floating regions17are not formed.

The X-axis direction length of each contact region15is referred to as Lc. In the X-axis direction, the length by which one floating region17overlaps with one contact region15, Lf, is smaller than half of length Lc of the contact region15. Length Lf may be ⅓ or less of length Lc.

FIG.16is a partial perspective cross-sectional view of the semiconductor substrate10.FIG.16shows the respective surfaces of a Y-Z plane passing through emitter regions12, a X-Z plane passing through the Y-axis direction center of a first mesa portion60in direct contact with a gate trench portion40, and the upper surface21of the semiconductor substrate10.

In the X-Z plane, regions overlapping with the emitter regions12are indicated by dashed lines. Each floating region17is arranged to overlap with the entire portion of an emitter region12and portions of contact regions15in the X-axis direction. By selectively arranging floating regions17to cover emitter regions12, the increase in ON voltage Von can be reduced, and the rate of decrease in CE voltage (dVce/dt) can be reduced. Also, the trade-off between ON voltage Von and the turn-off loss can be maintained.

In the X-axis direction, the length by which a floating region17overlaps with a contact region15, Lf, may be smaller than the Y-axis direction width of the floating region17, Wf. Length Lf may be the same as width Wf, or may be larger than width Wf.

The electro-static potential distribution in the vicinity of the floating region17is such that holes are easily concentrated at the floating region17. Thus, if a floating region17is provided below a contact region15, holes are easily dispersed to the contact region15via the floating region17. This may reduce the IE effect and increase ON voltage Von. Not forming floating regions17below contact regions15, as in the present example, allows holes to be easily concentrated at the emitter regions12, so that the IE effect can be maintained and the increase in ON voltage Von can be reduced.

Note that the semiconductor device100of the present example includes a plurality of buffer regions20arranged along the Z-axis direction. The doping concentration distribution in the Z-axis direction has a peak in each buffer region20. The doping concentration distribution in the Z-axis direction may have valleys arranged between the individual buffer regions20. The structure of the buffer regions20may be similar to that in the examples described with reference toFIG.1atoFIG.14.

While the embodiments of the present invention have been described, the technical scope of the invention is not limited to the above described embodiments. It is apparent to persons skilled in the art that various alterations and improvements can be added to the above-described embodiments. It is also apparent from the scope of the claims that the embodiments added with such alterations or improvements can be included in the technical scope of the invention.

The operations, procedures, steps, and stages of each process performed by an apparatus, system, program, and method shown in the claims, embodiments, or diagrams can be performed in any order as long as the order is not indicated by “prior to,” “before,” or the like and as long as the output from a previous process is not used in a later process. Even if the process flow is described using phrases such as “first” or “next” in the claims, embodiments, or diagrams, it does not necessarily mean that the process must be performed in this order.

EXPLANATION OF REFERENCES

10: semiconductor substrate,11: well region,12: emitter region,13: floating region end,14: base region,15: contact region,16: accumulation region,16-1: first accumulation region,16-2: second accumulation region,16-3: third accumulation region,17: floating region,18: drift region,19: gap,20: buffer region,21: upper surface,22: collector region,23: lower surface,24: collector electrode,25: connecting portion,29: extending portion,30: dummy trench portion,31: connecting portion,32: dummy insulating film,34: dummy conductive portion,38: interlayer dielectric film,39: extending portion,40: gate trench portion,41: connecting portion,42: gate insulating film,43: side wall,44: gate conductive portion,48: gate runner,49: contact hole,50: gate metal layer,52: emitter electrode,54: contact hole,56: contact hole,60: first mesa portion,62: second mesa portion,64: third mesa portion,70: transistor section,80: diode section,82: cathode region,87: high hole concentration region,89: bottom portion,90: boundary section,100: semiconductor device,150: semiconductor device,160: semiconductor device