Patent ID: 12216369

DETAILED DESCRIPTION OF THE EMBODIMENTS

In order to make objectives, technical solutions and advantages of embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are a part of embodiments of the present disclosure, rather than all the embodiments. Under the condition that no conflict, the embodiments of the present disclosure and the features of the embodiments may be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present disclosure.

Unless otherwise defined, technical or scientific terms used in the present disclosure shall have the ordinary meaning as understood by those of ordinary skill in the art to which this present disclosure belongs. “First”, “second” and similar words used in the present disclosure do not represent any order, quantity, or importance, but are merely used to distinguish different components. Similar words such as “comprise” or “include” mean that elements or items appearing before the words encompass elements or items recited after the words and their equivalents, but do not exclude other elements or items. Similar words such as “connected” or “linked” are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that dimensions and shapes of figures in the accompanying drawings do not reflect a real scale, and are only intended to illustrate the contents of the present disclosure. The same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout.

An embodiment of the present disclosure provides a display panel. As shown inFIG.1,FIG.2,FIG.3andFIG.4, the display panel includes an array substrate1, an opposing substrate7, a liquid crystal layer8and a plurality of supporting parts9.

The array substrate1includes a plurality of scanning lines2extending in a first direction X, a plurality of data lines3extending in a second direction Y, and a plurality of sub-pixels4in regions divided by the plurality of scanning lines2and the plurality of data lines3. The first direction X intersects with the second direction Y. At least two sub-pixels adjacent in the first direction X and the second direction Y constitute a pixel island6. The plurality of sub-pixels4include a plurality of sub-pixel rows5arranged in the second direction Y, and each sub-pixel row5includes a plurality of sub-pixels4arranged in the first direction X.

The opposing substrate7is arranged opposite to the array substrate1.

The liquid crystal layer8is between the array substrate1and the opposing substrate7.

The plurality of supporting parts9is between the array substrate1and the opposing substrate7. An orthographic projection of each supporting part9on the array substrate1is between orthographic projections of adjacent sub-pixel rows5on the array substrate1. Each supporting part9includes: a first sub-supporting part12and a second sub-supporting part13. The first sub-supporting part12extends in the first direction X and the second sub-supporting part13extends in the second direction Y One of the first sub-supporting part12and the second sub-supporting part13is arranged on a surface of a side of the array substrate1facing the opposing substrate7, and the other of the first sub-supporting part12and the second sub-supporting part13is arranged on a surface of a side of the opposing substrate7facing the array substrate1. An orthographic projection of the first sub-supporting part12on the array substrate1divides an orthographic projection of the second sub-supporting part13on the array substrate1into a first part14and a second part15. In each supporting part9, a length of the first part14in the second direction Y is not equal to a length of the second part15in the second direction Y.

According to the display panel provided by the embodiment of the present disclosure, each supporting part includes the first sub-supporting part and the second sub-supporting part arranged on different substrates and extending in different directions, and the orthographic projection of the first sub-supporting part on the array substrate divides the orthographic projection of the second sub-supporting part on the array substrate into the first part and the second part, i.e. the first sub-supporting part has a certain sliding distance relative to the second sub-supporting part, so a situation that in a display panel manufacturing process, the first sub-supporting part or the second sub-supporting part scratches other film layers due to sliding may be avoided. The length of the first part of the supporting part in the second direction is not equal to the length of the second part of the supporting part in the second direction. In this way, a maximum sliding distance of each supporting part is the sum of a width of the one, of the first part and the second part, with the larger length in the second direction and a width of the corresponding second sub-supporting part in the second direction. Compared with a situation that in each supporting part, the length of the first part in the second direction is equal to the length of the second part in the second direction, the maximum sliding distance of the supporting part may be increased. Therefore, the display panel provided by the embodiment of the present disclosure may reduce a length of a light shielding region of the display panel covering the supporting parts in the second direction under a condition of not changing the sliding distance of the supporting parts, so that an area of a light-transmitting region of a sub-pixel may be improved and an aperture ratio of the sub-pixel is improved, thus further improving a display effect and improving user experience.

It should be noted that,FIG.2,FIG.3andFIG.4are planar diagrams of the array substrate, andFIG.1may, for example, be a sectional diagram of a partial region ofFIG.2,FIG.3andFIG.4in the first direction X.

In some embodiments, as shown inFIG.2andFIG.3, the lengths h6of the first parts14in the plurality of supporting parts9in the second direction Y are equal; and the lengths h7of the second parts15in the plurality of supporting parts9in the second direction Y are equal.

In some embodiments, as shown inFIG.2, in the plurality of supporting parts9, the lengths h6of the first parts14in the second direction Y are larger than the lengths h7of the second parts15in the second direction Y.

Or, as shown inFIG.3, in the plurality of supporting parts9, the lengths h6of the first parts14in the second direction Y are smaller than the lengths h7of the second parts15in the second direction Y.

In some embodiments, as shown inFIG.4, the plurality of supporting parts9include: a plurality of first supporting parts10and a plurality of second supporting parts11. Each first supporting part10includes: a first sub-supporting part12and a second sub-supporting part13; and each second supporting part11includes: a first sub-supporting part12and a second sub-supporting part13.

In each first supporting part10, the length h1of the first part14in the second direction Y is larger than the length h2of the second part15in the second direction Y In each second supporting part11, the length h3of the first part14in the second direction Y is smaller than the length h4of the second part15in the second direction Y.

According to the display panel provided by the embodiment of the present disclosure, each supporting part includes the first sub-supporting part and the second sub-supporting part arranged on different substrates and extending in different directions, and the orthographic projection of the first sub-supporting part on the array substrate divides the orthographic projection of the second sub-supporting part on the array substrate into the first part and the second part, i.e. the first sub-supporting part has a certain sliding distance relative to the second sub-supporting part, so a situation that in a display panel manufacturing process, the first sub-supporting part or the second sub-supporting part scratches other film layers due to sliding may be avoided. An upward sliding distance of each first supporting part is the sum of a length of the first part in the first supporting part in the second direction and the width of the corresponding second sub-supporting part in the second direction. A downward sliding distance of each second supporting part is the sum of a length of the second part in the second supporting part in the second direction and the width of the corresponding second sub-supporting part in the second direction. Compared with a situation that in each supporting part, the length of the first part in the second direction is equal to the length of the second part in the second direction, the upward sliding distance and downward sliding distance of the supporting part may be increased. In addition, because the display panel includes the two kinds of supporting parts namely the first supporting parts and the second supporting parts, compared with a situation that in each supporting part, the length of the first part in the second direction is equal to the length of the second part in the second direction, a total sliding distance of the supporting parts may be further increased. Therefore, the display panel provided by the embodiment of the present disclosure may reduce the length of the light shielding region of the display panel covering the supporting parts in the second direction under the condition of not changing the sliding distance of the supporting parts, so that an area of a light-transmitting region of a sub-pixel may be improved and an aperture ratio of the sub-pixel is improved, thus further improving the display effect and improving the user experience.

It should be noted that, H1inFIG.4is an upward sliding distance of the first sub-supporting part in each first supporting part, H2is a downward sliding distance of the first sub-supporting part in each second supporting part, and the total sliding distance of the supporting parts of the display panel is H1+H2.FIG.4merely illustrates part of the sub-pixels and supporting parts, and merely illustrates one scanning line and one data line as an example to describe the display panel provided by the embodiment of the present disclosure. During specific implementations, the quantity of the sub-pixels, the quantity of the supporting parts, the quantity of the scanning lines and the quantity of the data lines may be set according to actual needs.

It should be noted that the display panel provided by the embodiment of the present disclosure is a liquid crystal display panel, and may be a Twisted Nematic (TN) type, a Vertical Alignment (VA) type, an In-Plane Switching (IPS) type or an Advanced Super Dimension Switch (ADS) type liquid crystal display panel.

In some embodiments, as shown inFIG.2,FIG.3andFIG.4, the plurality of sub-pixels4in each sub-pixel row5are in the same color.

In this way, interference between different viewpoints may be avoided, and moiré may also be alleviated.

In some embodiments, as shown inFIG.2,FIG.3andFIG.4, the sub-pixel rows5include: red sub-pixel rows16, blue sub-pixel rows18and green sub-pixel rows17. As shown inFIG.2,FIG.3andFIG.4, each of the red sub-pixel rows16includes a plurality of red sub-pixels R arranged in the first direction X, each of the green sub-pixel rows17includes a plurality of green sub-pixels G arranged in the first direction X, and each of the blue sub-pixel rows18includes a plurality of blue sub-pixels B arranged in the first direction X.

In some embodiments, as shown inFIG.2,FIG.3,FIG.4, andFIG.5, the opposing substrate includes: a light shielding layer. The light shielding layer merely includes a plurality of first light shielding parts19extending in the first direction X.

Orthographic projections of the first light shielding parts19on the array substrate cover orthographic projections of the scanning lines2on the array substrate and orthographic projections of the supporting parts9on the array substrate.

In some embodiments, as shown inFIG.2,FIG.3,FIG.4, andFIG.5, a width of a first light shielding part19between each of the red sub-pixel rows16and each of the blue sub-pixel rows18in the second direction Y is larger than a width of a first light shielding part19between each of the red sub-pixel rows16and each of the green sub-pixel rows17in the second direction Y.

The width of the first light shielding part19between the red sub-pixel row16and the blue sub-pixel row18in the second direction Y is larger than a width of a first light shielding part19between the blue sub-pixel row18and the green sub-pixel row17in the second direction Y.

It should be noted that, a region defined by a dotted line inFIG.2,FIG.3, andFIG.4is a region covered by the orthographic projection of each first light shielding part19on the array substrate.

It should be noted that a size ratio of the first light shielding parts between the sub-pixel rows inFIG.2,FIG.3,FIG.4, andFIG.5does not represent a true ratio, and regions between the blue sub-pixel rows and the red sub-pixel rows are set to be relatively large merely in order to clearly illustrate a structure of the supporting parts.

It should be noted that,FIG.5is a planar diagram of the opposing substrate. As shown inFIG.5, the opposing substrate further includes color resists20arranged in opening regions of the light shielding layer. Colors of the color resists20are in one-to-one correspondence to the colors of the sub-pixels, i.e. the color resists20include red resists r, blue resists b and green resists g.

It should be noted that, in the related art, a pattern of a light shielding layer of an opposing substrate is grid-shaped, and grid openings are light-transmitting regions of corresponding sub-pixels. According to the display panel provided by the embodiment of the present disclosure, the light shielding layer of the opposing substrate merely includes the first light shielding parts extending in the first direction, i.e. no light shielding part is arranged in the second direction. Compared to the light shielding layer with the grid-shaped pattern in the related art, an aperture ratio of the sub-pixels may be improved. In addition, because a row of sub-pixels extending in the first direction are in the same color, the situation that no light shielding part extending in the second direction is arranged will not cause an influence on the display effect.

In some embodiments, as shown inFIG.2,FIG.3, andFIG.4, orthographic projections of the supporting parts9on the array substrate are located between adjacent blue sub-pixel rows18and red sub-pixel rows16.

That is, according to the display panel provided by the embodiment of the present disclosure, the supporting parts are arranged in a region where widths of the first light shielding parts in the second direction Y are relatively large.

It should be noted that, compared with the red sub-pixels and the blue sub-pixels, a light emitting efficiency of the green sub-pixels is affected by the aperture ratio to a greater extent. Therefore, according to the display panel provided by the embodiment of the present disclosure, the region where the widths of the first light shielding parts in the second direction Y are relatively large is arranged between the red sub-pixel row and the blue sub-pixel row, so that influence of the increased widths of the first light shielding parts in the second direction Y on the green sub-pixels may be avoided.

When the plurality of supporting parts include the first supporting parts and the second supporting parts, in some embodiments, as shown inFIG.4, the first supporting parts10or the second supporting parts11are located between the adjacent blue sub-pixel rows18and red sub-pixel rows16.

Or, when the plurality of supporting parts include the first supporting parts and the second supporting parts, in some embodiments, as shown inFIG.6, the first supporting parts10and the second supporting parts11are located between the adjacent blue sub-pixel rows18and red sub-pixel rows16.

In some embodiments, as shown inFIG.4andFIG.6, a length h1of the first part14in each first supporting part10in the second direction Y is equal to a length h4of the second part15in each second supporting part11in the second direction Y.

In some embodiments, as shown inFIG.4andFIG.6, a length h2of the second part15in each first supporting part10in the second direction Y is equal to a length h3of the first part14in each second supporting part11in the second direction Y.

In some embodiments, as shown inFIG.2,FIG.3,FIG.4, andFIG.6, the orthographic projection the first sub-supporting part12on the array substrate is symmetric relative to the orthographic projection the second sub-supporting part13on the array substrate.

In some embodiments, as shown inFIG.2,FIG.3,FIG.4, andFIG.6, a pattern of the orthographic projection of each supporting part9on the array substrate is cross-shaped.

It should be noted that, the cross-shaped pattern in the embodiment of the present disclosure refers to: a pattern composed by strip-shaped patterns extending in different directions and vertically intersecting with each other.

As shown inFIG.2,FIG.3,FIG.4, andFIG.6, the first sub-supporting part and the second sub-supporting part included by the supporting part are strip-shaped patterns extending in different directions, and the first sub-supporting part and the second sub-supporting part vertically intersect with each other to form the cross-shaped pattern.

In some embodiments, as shown inFIG.2,FIG.3,FIG.4, andFIG.6, a width of each first sub-supporting part12in the second direction Y is equal to a width of each second sub-supporting part13in the first direction X.

In some embodiments, as shown inFIG.2,FIG.3,FIG.4, andFIG.6, a length of each first sub-supporting part12in the first direction X is larger than a length of each second sub-supporting part13in the second direction Y.

In this way, a supporting strength of the supporting parts in the first direction may be improved.

That is, under a condition of unchanged supporting strength of the supporting parts, by using the arrangement mode of the first sub-supporting parts and the second sub-supporting parts provided by the embodiment of the present disclosure, the lengths of the second sub-supporting parts in the second direction may be reduced, so that a width of the first light shielding layer covering the supporting parts in the second direction may be reduced, thus improving the aperture ratio of the sub-pixels.

During specific implementation, the length of each first sub-supporting part in the first direction and the length of each second sub-supporting part in the second direction are 20 microns, and the width of each first sub-supporting part in the second direction and the width of each second sub-supporting part in the first direction are 6 microns. A minimum distance between an edge of each first light shielding part extending in the first direction and the first sub-supporting part may be about 5 microns. The length of the first light shielding part located between the red sub-pixel row and the blue sub-pixel row in the first direction is 44 microns, and a width thereof in the second direction is 10 microns. A minimum distance between the edge of each first light shielding part extending in the first direction and the second sub-supporting part is 3 microns. In each first supporting part, the upward or downward sliding distance of the first sub-supporting part is 12 microns, and in each second supporting part, the downward sliding distance of the first sub-supporting part is 12 microns. That is, the sliding distance of the supporting parts is 24 microns. In actual design, for the sliding distance of the supporting parts, reference should be made to a size of the display panel, magnitude of external force used for product specification testing, and a stress area. For design of sizes of the second sub-supporting parts, the sliding distance of the supporting parts, contact supporting force of the supporting parts, materials of the supporting parts, heights and other factors should be considered. In specific design, when the lengths of the sub-pixels are 52 um, a pixel pitch is 9.75 microns. When a design of the first supporting parts and the second supporting parts provided by the embodiment of the present disclosure is adopted, the width of the first light shielding part in the second direction are 30 microns at most, so it may be ensured that an average aperture ratio of the sub-pixels is larger than 50%.

In some embodiments, as shown inFIG.1, the first sub-supporting parts12are arranged on a surface of a side of the opposing substrate7facing the array substrate1.

The second sub-supporting parts13are arranged on a surface of a side of the array substrate1facing the opposing substrate7.

In some embodiments, as shown inFIG.7andFIG.8, the array substrate specifically includes: a first base substrate21, a first conductive layer22, a second conductive layer23and a pixel electrode layer24.

The first conductive layer22is located on a side of the first base substrate facing the opposing substrate and includes the data lines48and first terminals36of driving transistors electrically connected to the data lines.

The second conductive layer23is on a side of the first conductive layer away from the first base substrate and includes second terminals37of the driving transistors.

The pixel electrode layer24is located on a side of the second conductive layer away from the first conductive layer and includes a plurality of pixel electrodes47in one-to-one correspondence to the sub-pixels. The pixel electrodes are electrically connected to the second poles of the driving transistors.

That is, in the embodiments of the present disclosure, the second terminals of the driving transistors and the data lines are arranged in different conductive layers, so that even a distance between an edge of an orthographic projection of the second terminal of each driving transistor on the first base substrate and an edge of an orthographic projection of the corresponding data line on the first base substrate is reduced, short circuit between the second terminals of the driving transistors and the data lines will not be caused, so a design difficulty of an array substrate layout may be simplified.

It should be noted that,FIG.8may, for example, be a sectional diagram along AA′ inFIG.7.

In some embodiments, a width of each scanning line is in a range of 2.5 microns to 3.5 microns. The smaller a resistivity of a material of the gate conductive layer is, the wider the scanning lines may be arranged. The resistivity of the material of the gate conductive layer may be selected to be 0.07 square resistance (Ω/□) to 0.1 (Ω/□).

In some embodiments, a width of each data line is in a range of 1.5 microns to 1.8 microns. In order to prevent broken lines in intersection regions with the scanning lines, a design of compensatory increased width is adopted in the intersection regions with the scanning lines, and the width of each single edge is increased by 0.5 micron.

In some embodiments, a minimum distance between an edge of an orthographic projection of the second terminal of each driving transistor on the first base substrate and an edge of an orthographic projection of each data line on the first base substrate is in a range of 0.8 micron to 1 micron.

In some embodiments, the width of the second terminal of each driving transistor is in a range of 4.3 microns to 6.65 microns.

In some embodiments, as shown inFIG.7andFIG.8, the array substrate further includes an active layer26. The active layer26is located between the first base substrate21and the first conductive layer22and includes a plurality of patterns of the active layer in one-to-one correspondence to the sub-pixels.

As shown inFIG.10, a shape of an orthographic projection of each pattern of the active layer26on the first base substrate is provided with a corner, and at the corner, the orthographic projection of the pattern of the active layer on the first base substrate is provided with a first groove.

In some embodiments, a material of the active layer may, for example, include polycrystalline silicon. The active layer includes a semiconductor region and a conductor region. During specific implementation, for example, a self-alignment process may be used to perform low-temperature doping to form a conductor region. In order to ensure a doping accuracy, a distance between an edge of an orthographic projection of the active layer on the first base substrate and the edge of the orthographic projection of each scanning line on the first base substrate is in a range of 1 micron to 1.5 microns. In order to ensure an accuracy of a corner shape of the active layer, an exposure compensation design needs to be performed at the corner, that is, the corner is hollowed out by 1 micron to form the first groove.

In some embodiments, as shown inFIG.7andFIG.8, the array substrate further includes: the light shielding layer25between the active layer26and the first base substrate21; a buffer layer40between the light shielding layer25and the active layer26; a gate conductive layer27between the active layer26and the first conductive layer22, including control poles39of the driving transistors and the scanning lines; a gate insulating layer35between the active layer26and the gate conductive layer27; a first interlayer insulating layer29between the gate conductive layer27and the first conductive layer22; a second interlayer insulating layer31between the first conductive layer22and the second conductive layer23; and a first passivation layer33between the second conductive layer23and the pixel electrode layer24.

The second terminal of the driving transistor is in contact with the active layer26through first a via hole32that penetrates through the second interlayer insulating layer, the first interlayer insulating layer and the gate insulating layer.

The pixel electrode is in contact with the second terminal of the driving transistor through second a via hole34that penetrates through the first passivation layer33.

The first terminal of the driving transistor is in contact with the active layer through a third via hole30that penetrates through the first interlayer insulating layer and the gate insulting layer.

It should be noted that, the light shielding layer is configured to shield channel regions of the driving transistors.

In some embodiments, a size of each first via hole is in a range of 1.5 microns to 2.5 microns.

In some embodiments, a size of each second via hole is in a range of 2.5 microns to 3.5 microns.

In some embodiments, a size of each third via hole is in a range of 1.5 microns to 2.5 microns.

In order to avoid etching residue of the via holes, in some embodiments, a minimum distance between an edge of an orthographic projection of each second via hole on the first base substrate and an edge of an orthographic projection of each first via hole on the base substrate is larger than or equal to 0.35 micron and smaller than or equal to 0.7 micron.

In order to avoid the short circuit between the control terminal of the driving transistor and the second terminal of the driving transistor caused by connection between the first via hole and the scanning line, in some embodiments, a minimum distance between the edge of the orthographic projection of the second via hole on the first base substrate and an edge of an orthographic projection of the control terminal of the driving transistor on the first base substrate is larger than or equal to 1 micron and smaller than or equal to 2 microns.

In some embodiments, as shown inFIG.7andFIG.17, the array substrate further includes: a common electrode layer28on a side of the pixel electrode layer24away from the second conductive layer23, including: common electrodes38; and a second passivation layer41between the common electrode layer28and the pixel electrode layer24.

In some embodiments, as shown inFIG.19, the gate conductive layer27further includes: common electrode lines46electrically connected to the common electrodes38. The common electrode lines are arranged between adjacent blue sub-pixel rows and red sub-pixel rows.

During specific implementation, for example, the common electrode lines may be arranged in regions corresponding to the supporting parts between the blue sub-pixel rows and the red sub-pixel rows, so that an influence caused by the arrangement of the common electrode lines on the aperture ratio of the display panel may be avoided.

In some embodiments, the second conductive layer23further includes connecting electrodes49. Each of the connecting electrodes49is electrically connected to the common electrode line46through a fourth via hole50that penetrates through the second interlayer insulating layer and the first interlayer insulating layer. The common electrode38is electrically connected with the connecting electrode49through a fifth via holes52that penetrates through the second passivation layer and a sixth via hole51that penetrates through the first passivation layer. Orthographic projections of the fourth via hole, the fifth via hole and the sixth via hole on the first base substrate overlap with one another.

It should be noted that, the pixel electrode layer and the common electrode layer may adopt materials with a relatively high transmittance. For example, the pixel electrode layer and the common electrode layer may include indium tin oxide (ITO). That is, two ITO layers may be arranged in the array substrate. The first ITO layer serves as the pixel electrode layer, so that the quantity of via holes may be reduced, thus improving the aperture ratio.

During specific implementation, the pixel pitch may, for example, designed to be 9.75 microns. Under this condition, ITO with the highest transmittance may be used, so that a width to length ratio at a notch of the common electrode is 4.8 microns/4.95 microns, i.e. the common electrode arranged into an entire layer are hollowed out by 4.8 microns in a light light-transmitting region of pixels.

It should be noted that,FIG.9toFIG.18are patterns of the light shielding layer25, the active layer26, the gate conductive layer27, the first interlayer insulating layer29, the first conductive layer22, the second interlayer insulating layer31, the second conductive layer23, the first passivation layer33, the pixel electrode layer24and the common electrode layer28corresponding to the region illustrated inFIG.7.FIG.20toFIG.27are patterns of the gate conductive layer27, the second interlayer insulating layer31, the second conductive layer23, the first passivation layer33, the pixel electrode layer24, the second passivation layer41and the common electrode layer28corresponding to the region shown inFIG.19. Among them,FIG.12,FIG.14,FIG.16,FIG.21,FIG.23, andFIG.25respectively merely show the pattern of each via hole in each insulating layer. Reference should be made toFIG.10for the pattern of the active layer corresponding toFIG.19, and reference should be made toFIG.13for the pattern of the first conductive layer22corresponding toFIG.19.

Next, to take second sub-supporting parts prepared on a side of an array substrate facing an opposing substrate as an example, preparation of the array substrate in the display panel provided by the embodiment of the present disclosure is described by examples. A preparation method of the array substrate includes the following steps.

S101, a light shielding layer material is deposited on a first base substrate, and a pattern of a light shielding layer is formed by using a patterning process.

S102, a buffer layer material is deposited to form a buffer layer.

S103, a semiconductor material is deposited and a pattern of an active layer is formed through etching.

S104, a gate insulating layer material is deposited to form a gate insulating layer.

S105, a gate metal material is deposited and a pattern of a gate metal layer is formed through etching, and a conductor region is formed on the active layer by using a semiconductor self-alignment doping process.

S106, a first interlayer insulating layer material is deposited and a third via hole is formed through etching.

S107, a metal material is deposited to form a first conductive layer, and a pattern of the first conductive layer is formed through etching.

S108, a second interlayer insulating layer material is deposited and a first via hole is formed through etching.

S109, a metal material is deposited to form a second conductive layer, and a pattern of the second conductive layer is formed through etching.

S110, a first passivation layer material is deposited to form a first passivation layer, and a second via hole is formed by using an exposure process.

S111, ITO is deposited to form a pixel electrode layer, and a pixel electrode is formed through etching.

S112, a second passivation layer material is deposited to form a second passivation layer, and a via hole in a surrounding region is formed through etching.

S113, ITO is deposited to form a common electrode layer, and a pattern the common electrode is formed through etching.

S114, a second sub-supporting part material is deposited, and a pattern of a second sub-supporting part is formed through etching.

An embodiment of the present disclosure provides a display apparatus, as shown inFIG.27, including the display panel42provided by the embodiment of the present disclosure.

In some embodiments, as shown inFIG.27, the display apparatus further includes: a cylindrical lens structure43on a light emitting side of the display panel. The cylindrical lens structure includes a plurality of cylindrical lens arranged in an array.

In some embodiments, as shown inFIG.27, the display apparatus further includes: a light-transmitting spacer layer44between the display panel42and the cylindrical lens structure43; and a flat layer45, located on a side of the cylindrical lens structure43away from the light-transmitting spacer layer44.

In some embodiments, when the display panel is a liquid crystal display panel, for example, the display apparatus further includes a backlight module located on the display panel away from the cylindrical lens structure.

In some embodiments, the display apparatus further includes: an eye-tracking system, configured to determine a gaze region of a user's eyes on the display apparatus in real time.

In this way, display information of each sub-pixel in a pixel island corresponding to the gaze region may be determined according to the gaze region of the user's eyes on the display apparatus.

During specific implementation, due to sub-pixel subdivision carried out in the pixel island (a sub pixel that can be displayed as a two-dimensional image (2D)), in a three-dimensional image (3D) display mode, the same resolution as the 2D display can be maintained. Combined with eye-tracking, multi-view display with large viewing angle can be realized, and 3D display with higher pixel density (ppi) can be achieved, thus realizing larger information volume and lower color crosstalk between adjacent viewpoints. Dizziness of a user when viewing a 3D image can also be reduced, so user experience can be improved. When the display apparatus is provided with a cylindrical lens array, the cylindrical lens array may not only perform pixel mapping on the sub-pixels in the pixel island, but also perform light field modulation on emergent light from the pixel island, so that final emergent light from the pixel island can form multiple view point, so as to realize light field 3D display.

The display apparatus provided by the embodiment of the present disclosure is: a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator and other product or component with a display function. Other essential components of the display apparatus should be understood by those of ordinary skill in the art, and will not be described in detail here, nor should it be regarded as a limitation to the present disclosure. For implementation of the display apparatus, reference may be made to the above-mentioned embodiment of the display panel, and repeated descriptions will not be made here.

In conclusion, the display panel provided by the embodiment of the present disclosure is the display apparatus, each supporting part includes the first sub-supporting part and the second sub-supporting part arranged on different substrates and extending in different directions, and the orthographic projection of the first sub-supporting part on the array substrate divides the orthographic projection of the second sub-supporting part on the array substrate into the first part and the second part, i.e. the first sub-supporting part has a certain sliding distance relative to the second sub-supporting part, so a situation that in a display panel manufacturing process, the first sub-supporting part or the second sub-supporting part scratches other film layers due to sliding may be avoided. An upward sliding distance of each first supporting part is the sum of a length of the first part in the first supporting part in the second direction and the width of the corresponding second sub-supporting part in the second direction. A downward sliding distance of each second supporting part is the sum of a length of the second part in the second supporting part in the second direction and the width of the corresponding second sub-supporting part in the second direction. Compared with a situation that in each supporting part, the length of the first part in the second direction is equal to the length of the second part in the second direction, the upward sliding distance and downward sliding distance of the supporting part may be increased. In addition, because the display panel includes the two kinds of supporting parts namely the first supporting parts and the second supporting parts, compared with a situation that in each supporting part, the length of the first part in the second direction is equal to the length of the second part in the second direction, a total sliding distance of the supporting parts may be further increased. Therefore, the display panel provided by the embodiment of the present disclosure may reduce the length of the light shielding region of the display panel covering the supporting parts in the second direction under the condition of not changing the sliding distance of the supporting parts, so that an area of a light-transmitting region of a sub-pixel may be improved and an aperture ratio of the sub-pixel is improved, thus further improving the display effect and improving the user experience.

While preferred embodiments of the present disclosure have been described, additional changes and modifications to these embodiments may be made by those of skill in the art once they are aware of basic inventive concepts. Therefore, appended claims are intended to be construed to include the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

Obviously, those of skill in the art can make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, provided that these changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to cover such changes and modifications.