Patent ID: 12189471

The same reference numbers (or other feature designators) are used in the drawings to designate the same or similar (functionally and/or structurally) features.

DETAILED DESCRIPTION

Some approaches for verifying data integrity may be performed through software-based processes. For example, following a data read or a data write, software may read the data a second time, or read the written data, and compare the read data to the data that was first read or written, respectively. However, such a software-based process may place a large processing burden on a central processing unit performing the verification, increasing power consumption in a system that performs the verification. The software-based process may also have a complicated development and testing process.

Aspects of this disclosure provide for hardware-based data integrity verification. The hardware-based data integrity verification may be performed for data transfers, such as direct memory access (DMA) transfers, between memory devices (e.g., random access memory and flash, etc.). The hardware-based data integrity verification may be performed for data transfers between memory devices and peripheral devices. The hardware-based data integrity verification may be performed for data transfers between peripheral devices. In at least some examples, the peripheral devices are first-in, first-out (FIFO) based devices.

In some examples, the data may be copied from a source device to a destination device. At least one of the source device or the destination device is a DMA component having a buffer. A first checksum may be calculated for data provided in the buffer of the DMA component and stored in a first register. Subsequently, a verify read may be performed to replace the contents of the buffer of the DMA component with the data that was just copied by the DMA component. In some examples, the verify read may read the data from the source in the source-destination copy scheme. In other examples, the verify read may read the data from the destination device in the source-destination copy scheme. A second checksum may be calculated for the data provided in the buffer of the DMA component and the first and second checksums may be compared. If the checksums match, the data copying passed the data integrity verification and operation continues. If the checksums do not match, the data copying failed the data integrity verification and a fault notification is provided. In at least some examples, a peripheral device functioning as the source device or the destination device includes a FIFO buffer that has a pointer indicating a read location, or a write location, of the FIFO buffer. In some implementations, a second pointer is added to the FIFO buffer as a verify-read pointer. The verify-read pointer may trail the pointer of the FIFO buffer such that the pointer of the FIFO buffer increments as data is written to, or read from, the FIFO buffer during the copying operation and the verify-read pointer increments as data is read from the FIFO buffer during the data integrity verification.

FIG.1is a block diagram of a system100in accordance with various examples. In at least some examples, the system100is representative of an integrated circuit or system on a chip (SOC). In some examples, the system100may be suitable for a functional safety application such that at least some components of the system100are functional safety compliant hardware. In some examples, the system100includes a system control module (SCM)102, a DMA104, a source device106, and a destination device108. The SCM may be coupled to at least some of the DMA104, the source device106, and/or the destination device108. The source device106and the destination device108may each be coupled to the DMA104. The source device106and the destination device108may each be a memory device (e.g., flash, random access memory (RAM) such as static RAM (SRAM), etc.) or a peripheral device (such as a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), etc.).

In an example of operation of the system100, a data bit, such as a safety enable bit, may be asserted (e.g., “set”) in a safety register of the SCM102. In some examples, the register may be an Enable Safety register. The safety enable bit may be set in the SCM102according to any suitable process and according to any suitable control signal or trigger event, received from any suitable source, the scope of which is not limited herein. Responsive to assertion of the safety enable bit, the SCM102may provide an asserted safety active signal, that is otherwise de-asserted, to at least some components of the system100. For example, the SCM102may provide the safety active signal to the DMA104. The SCM102may also provide the safety active signal to the source device106and/or the destination device108, when the respective source device106or destination device108is a peripheral device. Responsive to assertion of the safety enable signal, the DMA104, source device106, and/or destination device108may perform data integrity verification as described herein.

For example, subsequent to the DMA104moving data, either from the source device106to a buffer of the DMA104described in more detail below, or from the buffer of the DMA104to the destination device108, the DMA104may initiate a verify-read operation. The verify-read operation may be performed automatically following the DMA104writing data to the buffer of the DMA104or the destination device104, such as without specific user initiation, based at least in part on the assertion of the safety enable signal. The verify-read operation may make a second copy, from the source device106, of data copied from the source device106to the buffer of the DMA104, or may make a new copy, from the destination device108, of data copied from the buffer of the DMA104to the destination device108. The DMA104may compute checksums of the data provided in the buffer of the DMA104during both the copy operation and the verify-read operation and may compare the checksums. If the checksums match, the copy operation passed the data integrity verification and operation continues. If the checksums do not match, the copy operation failed the data integrity verification and the DMA104provides a fault notification. In some examples, the fault notification is provided to the SCM102. In other examples, the fault notification is provided to any other device or component (not shown). In examples of the system100in which the source device106and/or the destination device108are peripheral devices, the peripheral device includes a FIFO buffer (not shown) that has a pointer indicating a read location, or a write location, of the FIFO buffer. In some implementations, a second pointer is added to the FIFO buffer as a verify-read pointer. The verify-read pointer may trail the pointer of the FIFO buffer such that the pointer of the FIFO buffer increments as data is written to, or read from, the FIFO buffer during the copying operation and the verify-read pointer increments as data is read from the FIFO buffer during the data integrity verification, such as during the verify read operation.

FIG.2is an implementation of the system100in which the source device106is a memory device and the destination device108is a memory device in accordance with various examples. For example, the source device106may be flash memory, RAM memory, or any other suitable memory device. Similarly, the destination device108may be flash memory, RAM memory, or any other suitable memory device. In at least some examples, the DMA104includes control logic202, a data buffer204, a checksum generator206, a register208, a register210, and comparison logic212.

In an example of operation of the system100according to the implementation ofFIG.2, the DMA104reads data from the source device106. The DMA104may read the data from the source device106responsive to the DMA104receiving a request, from the SCM102or any other suitable component (not shown) to copy data from the source device106to the destination device108. The read data may be stored in the data buffer204in a copying operation. After the data from the source device106is copied to the data buffer204, the control logic202may control the checksum generator206to generate and provide a checksum of the contents of the data buffer204. The control logic202may also control the register208to store the checksum provided by the checksum generator206. In various examples, the checksum generator206may be any hardware component or circuit suitable for, and capable of, generating and providing a checksum of received data, the scope of which is not limited herein.

Following the checksum being generated by the checksum generator206and/or stored in the register208, the DMA104may perform a verify-read operation. For example, the control logic202may again copy the data from the source device106to the data buffer204, possibly overwriting data previously stored in the data buffer204, such as the older copy of the data from the source device106. After the data from the source device106is copied to the data buffer204, the control logic202may control the checksum generator206to generate and provide a checksum of the contents of the data buffer204. The control logic202may also control the register210to store the checksum provided by the checksum generator206. Following storing of the checksum in the register210, the control logic202may control the comparison logic212to compare values stored and provided by the register208and the register210to perform data integrity verification. For example, the register208may contain a checksum of data copied from the source device106to the data buffer204during a copying operation and the register210may contain a checksum of data copied from the source device106to the data buffer204during a verify-read operation. If an error has occurred in the copying or a fault exists in the source device106or the DMA104, the checksum values may not match. Responsive to the checksum values stored by the register208and the register210matching, the comparison logic212provides a comparison result indicating a match (e.g., a “pass” of the data integrity verification). Responsive to the checksum values stored by the register208and the register210not matching, the comparison logic212provides a comparison result indicating no match (e.g., a “fail” of the data integrity verification). The comparison result may be provided by the DMA104as a fault notification to any suitable component as dictated by specifications of the functional safety environment in which the system100is implemented. In at least some examples, responsive to failure of the data integrity verification, the DMA104may abandon the requested copy of data from the source device106to the destination device108, erasing contents of the data buffer204, register208, and register210. Responsive to passage of the data integrity verification, the DMA104may continue the requested copy of data from the source device106to the destination device108.

To continue the requested copy of data from the source device106to the destination device108, the control logic202may copy the contents of the data buffer204to the destination device108in a copying operation. After the data from the data buffer204is copied to the destination device108, the DMA104may perform a verify-read operation. For example, the control logic202may copy the data from the destination device108back to the data buffer204, possibly overwriting data previously stored in the data buffer204, such as the contents copied to the destination device108. After the data from the destination device108is copied back to the data buffer204, the control logic202may control the checksum generator206to generate and provide a checksum of the contents of the data buffer204. The control logic202may also control the register210to store the checksum provided by the checksum generator206, overwriting any data previously stored in the register210. Following storing of the checksum in the register210, the control logic202may control the comparison logic212to compare values stored and provided by the register208and the register210to perform data integrity verification. For example, the register208may contain a checksum of data copied from the source device106to the data buffer204during a copying operation and the register210may contain a checksum of data copied from the destination device108to the data buffer204during a verify-read operation. If an error has occurred in the copying or a fault exists in the destination device108or the DMA104, the checksum values may not match. Responsive to the checksum values stored by the register208and the register210matching, the comparison logic212provides a comparison result indicating a match (e.g., a “pass” of the data integrity verification). Responsive to the checksum values stored by the register208and the register210not matching, the comparison logic212provides a comparison result indicating no match (e.g., a “fail” of the data integrity verification). The comparison result may be provided by the DMA104as a fault notification to any suitable component as dictated by specifications of the functional safety environment in which the system100is implemented. In various examples, the fault notification may cause a device or component receiving the fault notification to take remedial action, such as causing the DMA104to perform the copy operation again, cause the destination device106to erase the data written to the destination device106, ceasing operation of a system or device (e.g., such as a partial or full system shutdown), providing a notification to a user, etc.

FIG.3is an implementation of the system100in which the source device106is a memory device and the destination device108is a peripheral device in accordance with various examples. For example, the source device106may be flash memory, RAM memory, or any other suitable memory device. The destination device108may be a peripheral device, such as, in one example, a DAC. In at least some examples, the DMA104includes control logic302, a data buffer304, a checksum generator306, a register308, a register310, and comparison logic312.

In an example of operation of the system100according to the implementation ofFIG.3, the DMA104reads data from the source device106and performs data integrity verification. The DMA104may read the data from the source device106and perform the data integrity verification in a manner substantially the same as described above with respect toFIG.2, the description of which is not repeated herein.

Responsive to determining that the copying operation from the source device106to the data buffer304passed the data integrity verification, the control logic302may copy the contents of the data buffer304to the destination device108. The destination device108, in at least some examples, includes a FIFO buffer314. The FIFO buffer314includes a write pointer318and a verify pointer320. The FIFO buffer314may also include buffer logic316configured to control the write pointer318and the verify pointer320. As used herein, a pointer may be an internal register that stores an index value that identifies a memory address of a memory (such as a buffer) to which the pointer corresponds or is otherwise assigned. The write pointer318may indicate a memory address in the FIFO buffer314at which a next data item received by the FIFO buffer314is to be written or stored. After writing to a memory address indicated by the write pointer318, the write pointer318may be increased in value to a memory address of a next unused portion of the FIFO buffer314. The verify pointer320may indicate a memory address in the FIFO buffer314that is to be read first during a verify-read operation. For example, at the beginning of a copying operation while the safety active signal is asserted, the write pointer318and the verify pointer320may both indicate a same memory address. As data is copied from the data buffer304to the FIFO buffer314, the write pointer318increases in value such that the write pointer318and the verify pointer320no longer indicate the same memory address. After copying the data from the data buffer304to the FIFO buffer314, the DMA104may initiate the data integrity verification with the verify-read operation. During the verify-read operation, the DMA104reads data from the FIFO buffer314and stores the read data back to the data buffer304. In at least some examples, the data read by the DMA104is indicated by the verify pointer320. Accordingly, after data is read by the DMA104from a memory address indicated by the verify pointer320, the verify pointer320increments to a next memory address. In this way, in at least some examples at a conclusion of the verify-read operation, the write pointer318and the verify pointer320may again both indicate a same memory address. In other examples, the write pointer318and the verify pointer320may not indicate a same memory address. For example, the DMA104may fail to initiate the verify-read operation, which may cause the verify pointer320to not advance to indicate the same memory address as the write pointer318. For example, following receipt by the buffer logic316of an instruction to perform write operation from the DMA104, the buffer logic316may receive an instruction to perform a second write operation before receiving an instruction to perform a verify-read operation. In such examples, the buffer logic316may provide a fault notification to the DMA104, or to any other suitable device, indicating that the verify-read operation was not performed.

In at least some examples, the destination device108receives data from the DMA104in an encoded format. The encoded format may include both instructions and data. The instructions may be, for example, a WRITE instruction to cause the destination device108to write the data to the FIFO buffer314at a position indicated by the write pointer318, as well as the data to write to the FIFO buffer314. In another example, the instruction may be a VERIFY-READ instruction to cause the destination device108to read data from the FIFO buffer314at a position indicated by the verify pointer320, and provide the read data to the DMA104. In at least some examples, the buffer logic316controls a memory address indicated by the write pointer318and the verify pointer320at least partially based on WRITE and VERIFY-READ.

After the data from the destination device108(e.g., such as stored in the FIFO buffer314) is copied back to the data buffer304, the control logic302may control the checksum generator306to generate and provide a checksum of the contents of the data buffer304. The control logic302may also control the register310to store the checksum provided by the checksum generator306, overwriting any data previously stored in the register310. Following storing of the checksum in the register310, the control logic302may control the comparison logic312to compare values stored and provided by the register308and the register310to perform data integrity verification. For example, the register308may contain a checksum of data copied from the source device106to the data buffer304during a copying operation and the register310may contain a checksum of data copied from the destination device108to the data buffer304during a verify-read operation. If an error has occurred in the copying or a fault exists in the destination device108or the DMA104, the checksum values may not match. Responsive to the checksum values stored by the register308and the register310matching, the comparison logic312provides a comparison result indicating a match (e.g., a “pass” of the data integrity verification). Responsive to the checksum values stored by the register308and the register310not matching, the comparison logic312provides a comparison result indicating no match (e.g., a “fail” of the data integrity verification). The comparison result may be provided by the DMA104as a fault notification to any suitable component as dictated by specifications of the functional safety environment in which the system100is implemented. In various examples, the fault notification may cause a device or component receiving the fault notification to take remedial action, such as causing the DMA104to perform the copy operation again, ceasing operation of a system or device (e.g., such as a partial or full system shutdown), providing a notification to a user, etc.

In some examples, data may be subsequently read, responsive to a read request, from the destination device108after a verify-read operation has been performed, such as by the DMA104or by any other suitable component. In such examples, the buffer logic316may provide data from the FIFO buffer314responsive to the read request based on a memory location of the FIFO buffer314indicated by the verify-read pointer320. Providing the data based on a memory location of the FIFO buffer314indicated by the verify-read pointer320may, in some examples, provide data that has undergone the verify-read operation described herein, increasing confidence in accuracy of the read data.

FIG.4is an implementation of the system100in which the source device106is a peripheral device and the destination device108is a memory device in accordance with various examples. For example, the source device106may be a peripheral device, such as, in one example, an ADC. The destination device108may be flash memory, RAM memory, or any other suitable memory device. In at least some examples, the DMA104includes control logic402, a data buffer404, a checksum generator406, a register408, a register410, and comparison logic412.

In an example of operation of the system100according to the implementation ofFIG.4, the DMA104reads data from the source device106. The DMA104may read the data from the source device106responsive to the DMA104receiving a request, from the SCM102or any other suitable component (not shown) to copy data from the source device106to the destination device108. The source device106, in at least some examples, includes a FIFO buffer414. The FIFO buffer414includes a read pointer418and a verify pointer420. The FIFO buffer414may also include buffer logic416configured to control the read pointer420and the verify pointer420. The read pointer418may indicate a memory address in the FIFO buffer414from which data should be read next in response to a received read request. After reading from the memory address indicated by the read pointer418, the read pointer418may be increased in value to a next memory address of the FIFO buffer414.

The read data may be stored in the data buffer404in a copying operation. After the data from the source device106(e.g., from the FIFO buffer414) is copied to the data buffer404, the control logic402may control the checksum generator406to generate and provide a checksum of the contents of the data buffer404. The control logic402may also control the register408to store the checksum provided by the checksum generator406. In various examples, the checksum generator406may be any hardware component or circuit suitable for, and capable of, generating and providing a checksum of received data, the scope of which is not limited herein.

The verify pointer420may indicate a memory address in the FIFO buffer414that is to be read first during a verify-read operation. For example, at the beginning of a copying operation while the safety active signal is asserted, the read pointer418and the verify pointer420may both indicate a same memory address. As data is copied from the FIFO buffer414to the data buffer404, the read pointer418increases in value such that the read pointer418and the verify pointer420no longer indicate the same memory address. After copying the data from the FIFO buffer414to the data buffer404, the DMA104may initiate the data integrity verification with the verify-read operation. During the verify-read operation, the DMA104reads data from the FIFO buffer414and again stores the read data to the data buffer404. In at least some examples, the data read by the DMA104is indicated by the verify pointer420. Accordingly, after data is read by the DMA104from a memory address indicated by the verify pointer420, the verify pointer420increments to a next memory address. In this way, in at least some examples at a conclusion of the verify-read operation, the read pointer418and the verify pointer420may again both indicate a same memory address. In other examples, the read pointer418and the verify pointer420may not indicate a same memory address. For example, the DMA104may fail to initiate the verify-read operation, which may cause the verify pointer420to not advance to indicate the same memory address as the read pointer418. For example, following receipt by the buffer logic416of an instruction to perform read operation from the DMA104, the buffer logic416may receive an instruction to perform a second read operation before receiving an instruction to perform a verify-read operation. In such examples, the buffer logic416may provide a fault notification to the DMA104, or to any other suitable device, indicating that the verify-read operation was not performed.

After the data from the source device106(e.g., such as stored in the FIFO buffer414) is again copied to the data buffer404, the control logic402may control the checksum generator406to generate and provide a checksum of the contents of the data buffer404. The control logic402may also control the register410to store the checksum provided by the checksum generator406, overwriting any data previously stored in the register410. Following storing of the checksum in the register410, the control logic402may control the comparison logic412to compare values stored and provided by the register408and the register410to perform data integrity verification. For example, the register408may contain a checksum of data copied from the source device106to the data buffer404during a copying operation and the register410may contain a checksum of data copied from the source device106to the data buffer404during a verify-read operation. If an error has occurred in the copying or a fault exists in the source device106or the DMA104, the checksum values may not match. Responsive to the checksum values stored by the register408and the register410matching, the comparison logic412provides a comparison result indicating a match (e.g., a “pass” of the data integrity verification). Responsive to the checksum values stored by the register408and the register410not matching, the comparison logic412provides a comparison result indicating no match (e.g., a “fail” of the data integrity verification). The comparison result may be provided by the DMA104as a fault notification to any suitable component as dictated by specifications of the functional safety environment in which the system100is implemented. In various examples, the fault notification may cause a device or component receiving the fault notification to take remedial action, such as causing the DMA104to perform the copy operation again, ceasing operation of a system or device (e.g., such as a partial or full system shutdown), providing a notification to a user, etc.

In an example of operation of the system100according to the implementation ofFIG.4, responsive to verification of the copy operation from the source device106to the DMA104(e.g., passage of the data integrity verification), the DMA104writes data to the destination device108from the data buffer304and again performs data integrity verification. The DMA104may write the data to the destination device108and perform the data integrity verification in a manner substantially the same as described above with respect toFIG.2, the description of which is not repeated herein.

FIG.5is an implementation of the system100in which the source device106is a peripheral device and the destination device108is a peripheral device in accordance with various examples. For example, the source device106may be a peripheral device, such as, in one example, an ADC. The destination device108may be a peripheral device, such as, in one example, a DAC. In at least some examples, the DMA104includes control logic502, a data buffer504, a checksum generator506, a register508, a register510, and comparison logic512.

In an example of operation of the system100according to the implementation ofFIG.5, the DMA104reads data from the source device106and performs data integrity verification. The DMA104may read the data from the source device106and perform the data integrity verification in a manner substantially the same as described above with respect toFIG.4, the description of which is not repeated herein. Similarly, responsive to verification of the copy operation from the source device106to the DMA104(e.g., passage of the data integrity verification), the DMA104writes data to the destination device108from the data buffer504and again performs data integrity verification. The DMA104may write the data to the destination device108and perform the data integrity verification in a manner substantially the same as described above with respect toFIG.3, the description of which is not repeated herein.

FIG.6is a flowchart of a method600in accordance with various examples. The method600may provide for copying of data between first and second devices and verification of that copying by performing a verify-read operation, as described above. In at least some examples, the method600is implemented, at least in part, by the DMA104as described above with respect to any of the preceding figures. Accordingly, reference may be made in describing the method600to components described above with respect to any of the preceding figures.

At operation602, data is copied between a source device and a destination device. The copied data may form first copied data. In some examples, the source device is a peripheral device or a memory device, as described above herein, and the destination device is the DMA104. In other examples, the source device is the DMA104and the destination device is a peripheral device or a memory device, as described above herein.

At operation604, a verify-read operation is automatically performed, responsive to completion of the copying. The verify-read operation may be performed by the DMA104automatically, as defined above herein, upon completion of the copying to form the first copied data. Accordingly, the DMA104may perform the copy of the data described at operation602and the verify-read operation described at operation604and subsequent operations606-614in response to a single instruction. The verify-read operation may verify or validate accuracy of the first copied data, as stored in the destination device.

At operation606, as a function of the verify-read operation, a first checksum of the first copied data is determined. In at least some examples, the first checksum is determined by the DMA104according to any suitable means.

At operation608, as a function of the verify-read operation, data is copied between the source device and the destination device to form second copied data. In examples in which the destination device is the DMA104, the data is copied from the source device to the DMA104to form the second copied data. In examples in which the source device is the DMA104, the data is copied from the destination device to the DMA104to form the second copied data.

At operation610, as a function of the verify-read operation, a second checksum of the second copied data is determined. In at least some examples, the second checksum is determined by the DMA104according to any suitable means.

At operation612, as a function of the verify-read operation, the first checksum is compared to the second checksum to determine a comparison result. In at least some examples, the DMA104performs the comparison.

At operation614, as a function of the verify-read operation, a data integrity validation result is determined based on the comparison result. For example, the data integrity validation result may have a value of pass, or other affirmative value, responsive to the comparison result indicating a match between the first checksum and the second checksum. In another examples, the data integrity validation result may have a value of fail, or other negative value, responsive to the comparison result indicating no match between the first checksum and the second checksum.

FIG.7is a state diagram700in accordance with various examples. In at least some examples, the diagram700corresponds to a state machine implemented by the buffer logic316, as described above with respect toFIG.3. For example, based on the state machine configured to operate according to the diagram700, the buffer logic316is configured to control the write pointer318and the verify pointer320. All operations of the diagram700are under an operational assumption that the safety active signal (shown inFIG.7as “SAFETY”) is asserted.

At a state702, the buffer logic316is idle. For example, responsive to receipt of WRITE and VERIFY-READ each having de-asserted values (e.g., such as a logical low or binary “0” value), the buffer logic316may remain idle and the write pointer318and verify pointer320may remain unchanged. Responsive to receipt of WRITE having an asserted value while VERIFY-READ maintains a de-asserted value, the buffer logic316transitions to state704.

At state704, the buffer logic316handles the write pointer318. For example, at state704the buffer logic316may monitor the FIFO buffer314, waiting for data to be written to the FIFO buffer314. In at least some examples, the buffer logic316may determine that data is being written to the FIFO buffer314based on detection of WRITE having an asserted value. Responsive to data being written to the FIFO buffer314, the buffer logic316transitions to state706, advances the write pointer318to a next unused memory address of the FIFO buffer314, and returns to state704.

At state708, the buffer logic316provides a fault notification message. In at least some examples, the fault notification message provided at state708indicates that a DMA from which data was received by the FIFO buffer314did not perform data integrity verification subsequent to performing the write and prior to performing a next write. From state708, the buffer logic316returns to state702.

Returning to state704, responsive to receipt of WRITE having a de-asserted value and VERIFY-READ having an asserted value, the buffer logic316transitions to state710. At state710, the buffer logic316handles the verify pointer320. For example, at state710the buffer logic316may monitor the FIFO buffer314, waiting for data to be read from the FIFO buffer314. In at least some examples, the buffer logic316may determine that data is being read from the FIFO buffer314based on detection of VERIFY having an asserted value. Responsive to a change in data (e.g., reading of data from the FIFO buffer314), the buffer logic316transitions to state712, advances the verify pointer320to a next memory address of the FIFO buffer314, and returns to state710. Responsive to receipt of WRITE having a de-asserted value and VERIFY-READ having a de-asserted value, the buffer logic316returns to state702.

FIG.8is a state diagram800in accordance with various examples. In at least some examples, the diagram800corresponds to a state machine implemented by the buffer logic416, as described above with respect toFIG.4. For example, based on the state machine configured to operate according to the diagram800, the buffer logic416is configured to control the read pointer418and the verify pointer420. All operations of the diagram800are under an operational assumption that the safety active signal (shown inFIG.8as “SAFETY”) is asserted.

At a state802, the buffer logic416is idle. For example, responsive to receipt of READ and VERIFY-READ each having de-asserted values (e.g., such as a logical low or binary “0” value), the buffer logic416may remain idle and the read pointer418and verify pointer420may remain unchanged. Responsive to receipt of READ having an asserted value while VERIFY-READ maintains a de-asserted value, the buffer logic416transitions to state804.

At state804, the buffer logic416handles the read pointer418. For example, at state804the buffer logic416may monitor the FIFO buffer414, waiting for data to be read from the FIFO buffer414. In at least some examples, the buffer logic416may determine that data is being read from the FIFO buffer414based on detection of READ having an asserted value. Responsive to a change in data (e.g., reading of data to the FIFO buffer414), the buffer logic416transitions to state806, advances the read pointer418to a next memory address of the FIFO buffer414, and returns to state804. After having received READ having an asserted values, responsive to a subsequent receipt of READ having an asserted value without first receiving VERIFY-READ having an asserted value, the buffer logic416transitions to state808.

At state808, the buffer logic416provides a fault notification message. In at least some examples, the fault notification message provided at state808indicates that a DMA which read data from the FIFO buffer414did not perform data integrity verification subsequent to the read and before performing a next read. From state808, the buffer logic416returns to state802.

Returning to state804, responsive to receipt of READ having a de-asserted value and VERIFY-READ having an asserted value, the buffer logic416transitions to state810. At state810, the buffer logic816handles the verify pointer420. For example, at state810the buffer logic416may monitor the FIFO buffer414, waiting for data to be read from the FIFO buffer414. In at least some examples, the buffer logic416may determine that data is being read from the FIFO buffer414based on detection of VERIFY having an asserted value. Responsive to a change in data (e.g., reading of data from the FIFO buffer414), the buffer logic416transitions to state812, advances the verify pointer420to a next memory address of the FIFO buffer414, and returns to state810. Responsive to receipt of READ having a de-asserted value and VERIFY-READ having a de-asserted value, the buffer logic416returns to state802.

In this description, the term “couple” may cover connections, communications or signal paths that enable a functional relationship consistent with this description. For example, if device A provides a signal to control device B to perform an action, then: (a) in a first example, device A is directly coupled to device B; or (b) in a second example, device A is indirectly coupled to device B through intervening component C if intervening component C does not substantially alter the functional relationship between device A and device B, so device B is controlled by device A via the control signal provided by device A.

A device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or reconfigurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof.

A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. Circuits described herein are reconfigurable to include the replaced components to provide functionality at least partially similar to functionality available prior to the component replacement. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value means+/−10 percent of the stated value.

Modifications are possible in the described examples, and other examples are possible within the scope of the claims.