Patent ID: 12205957

DETAILED DESCRIPTION

In order to make the objects, the technical solutions and the advantages of the present disclosure more apparent, the present disclosure will be described hereinafter in a clear and complete manner in conjunction with the drawings and embodiments. Obviously, the following embodiments merely relate to a part of, rather than all of, the embodiments of the present disclosure, and based on these embodiments, a person skilled in the art may, without any creative effort, obtain the other embodiments, which also fall within the scope of the present disclosure.

In order to solve the problem of using the TFT with the single gate structure in the high-PPI display device, which results in large leakage current, gray-scale bright spots, flicker, and other defects, as shown inFIG.1andFIG.2, the present disclosure provides in some embodiments a display substrate, which includes a base substrate101and a plurality of pixels arranged on the base substrate101, each pixel including a plurality of sub-pixels, and each sub-pixel including a first active layer104, a first gate insulation layer105, a gate electrode106, a second gate insulation layer107, a second active layer108, a first insulation layer109, a source electrode110and a drain electrode111laminated one on another. The source electrode110is connected with the first active layer104through a via hole penetrating through the first insulation layer109, the second gate insulation layer107and the first gate insulation layer105; and the source electrode110and the drain electrode111are connected with the second active layer108through a via hole penetrating through the first insulation layer109.

According to the embodiments of the present disclosure, the active layers with upper and lower laminated structures are provided, and the gate electrode and the gate insulation layer are arranged between the laminated active layers, so as to implement a TFT with the same effect as a TFT with the double gate structure. Without changing the pixel size and an aperture ratio, it is able to effectively reduce leakage current of the TFT and improve gray scale bright spots, flicker and other related defects, thereby to improve customer experience.

In a possible embodiment of the present disclosure, the base substrate101is a glass substrate or a substrate made of other materials.

In the embodiments of the present disclosure, the first active layer104is used to form a first switch of the TFT with the same effect as the TFT with the double gate structure. The first active layer104is made of a poly (polycrystalline silicon) material or other semiconductor materials, such as indium gallium zinc oxide (IGZO).

In a possible embodiment of the present disclosure, the first gate insulation layer105and the second gate insulation layer107are made of the same insulation material or different materials.

In the embodiments of the present disclosure, the gate electrode106is used to control the conduction of the TFT, and the gate electrode106is made of a metal material.

In the embodiments of the present disclosure, the second active layer108is used to form a second switch of the TFT with the same effect as the TFT with the double gate structure. The second active layer108is made of a poly or other semiconductor materials, such as IGZO, and the materials of the second active layer108and the first active layer104may be the same or different.

In the embodiments of the present disclosure, the first insulation layer109is an interlayer insulation layer for separating the source electrode, the drain electrode and the second active layer108, and for forming a via hole.

In the embodiments of the present disclosure, the source electrode110and the drain electrode111are made of a metal material, and the source electrode110and the drain electrode111are made of the same or different metal materials as the gate electrode106.

In a possible embodiment of the present disclosure, as shown inFIG.2, an orthographic projection of the second active layer108onto the base substrate101is arranged within a region of an orthographic projection of the first active layer104onto the base substrate101, so as to further improve the aperture ratio of the pixel.

In a possible embodiment of the present disclosure, as shown inFIG.1andFIG.2, the display substrate further includes a data line102and a second insulation layer103. The data line102is arranged at a side of the base substrate101close to the first active layer104, the second insulation layer103is arranged between the data line102and the first active layer104, and the first active layer104is connected with the data line102through a via hole penetrating through the second insulation layer103. The data line102is used to transmit data signals to the TFT, and also used to isolate metal ions in the base substrate101.

In a possible embodiment of the present disclosure, an orthographic projection of the first active layer104onto the base substrate101and an orthographic projection of the second active layer108onto the base substrate101are arranged within a region of an orthographic projection of the data line102onto the base substrate, that is, the data line102may be reused as a light shieling layer for the first active layer104and the second active layer108, so as to prevent the first active layer104and the second active layer108from being illuminated by the backlight, thereby to improve performance of the TFT.

Of course, in some other embodiments of the present disclosure, the data line102may be arranged on the same layer and made of the same material as the source electrode110and the drain electrode111, so as to form the data line102, the source electrode110and the drain electrode111through a single patterning process, so as to save the quantity of masks.

In a possible embodiment of the present disclosure, the display substrate further includes a third insulation layer112, a pixel electrode113, a fourth insulation layer114and a common electrode115. The pixel electrode113is connected with the drain electrode111through a via hole penetrating through the third insulation layer112, and the fourth insulation layer114is arranged between the pixel electrode113and the common electrode115.

In a possible embodiment of the present disclosure, the third insulation layer112may be a planarization layer for isolating the source electrode110and the drain electrode111.

In a possible embodiment of the present disclosure, the fourth insulation layer114may be a passivation (PVX) layer.

In the embodiments of the present disclosure, the pixel electrode113and the common electrode115are used to form a pixel driving electric field, and strip-shaped hollows are formed in the common electrode115. The pixel electrode113and the common electrode115may be made of the same transparent conductive material, such as indium tin oxide (ITO).

In a possible embodiment of the present disclosure, a pixel density of the display substrate is greater than or equal to 1500 PPI, which may be used to form the high-PPI display device.

The present disclosure further provides in some embodiments a display device, including the above-mentioned display substrate.

In a possible embodiment of the present disclosure, the display device is an AR display device or a VR display device.

As shown inFIG.3, the present disclosure further provides in some embodiments a manufacturing method of the display substrate, which includes the following steps.

Step31: forming a base substrate.

Step32: forming a first active layer, a first gate insulation layer, a gate electrode, a second gate insulation layer, a second active layer, a first insulation layer, a source electrode and a drain electrode on the base substrate in sequence. The source electrode is connected with the first active layer through a via hole penetrating through the first insulation layer, the second gate insulation layer and the first gate insulation layer; and the source electrode and the drain electrode are connected with the second active layer through a via hole penetrating through the first insulation layer.

According to the embodiments of the present disclosure, the active layers with upper and lower laminated structures are provided, and the gate electrode and the gate insulation layer are arranged between the laminated active layers, so as to implement a TFT with the same effect as a TFT with the double gate structure. Without changing the pixel size and an aperture ratio, it is able to effectively reduce leakage current of the TFT and improve gray scale bright spots, flicker and other related defects, thereby to improve customer experience.

In a possible embodiment of the present disclosure, an orthographic projection of the second active layer onto the base substrate is arranged within a region of an orthographic projection of the first active layer onto the base substrate.

In a possible embodiment of the present disclosure, prior to forming the first active layer on the base substrate, the manufacturing method further includes:

Step301of forming a data line on the base substrate; and

Step302of forming a second insulation layer on the data line and forming a via hole in the second insulation layer. The first active layer is connected with the data line through a via hole penetrating through the second insulation layer. An orthographic projection of the first active layer onto the base substrate and an orthographic projection of the second active layer onto the base substrate are arranged within a region of an orthographic projection of the data line onto the base substrate.

In a possible embodiment of the present disclosure, after forming the source electrode and the drain electrode on the base substrate, the manufacturing method further includes the following steps.

Step33: forming a third insulation layer and forming a via hole in the third insulation layer.

Step34: forming a pixel electrode connected with the drain electrode through a via hole penetrating through the third insulation layer.

Step35: forming a fourth insulation layer.

Step36: forming a common electrode.

FIG.4toFIG.14show a manufacturing method of the display substrate in another embodiment of the present disclosure, and the method includes the following steps.

Step41: as shown inFIG.4, forming a data line102on a base substrate (not shown).

Step42: as shown inFIG.5, forming a second insulation layer (not shown) on the data line102, and forming a via hole A1in the second insulation layer.

Step43: as shown inFIG.6, forming a first active layer104on the second insulation layer, and the first active layer104being connected with the data line102through the via hole A1.

Step44: as shown inFIG.7, forming a first gate insulation layer (not shown) on the first active layer104, forming a gate electrode106on the first gate insulation layer, and forming a gate line being simultaneously with the gate electrode106.

Step45: as shown inFIG.8, forming a second gate insulation layer (not shown) on the gate electrode106, and forming a second active layer108on the second gate insulation layer.

Step46: as shown inFIG.9, forming a first insulation layer (not shown) on the second active layer108, and forming a via hole A2in the first insulation layer.

Step47: as shown inFIG.10, forming a via hole A3, the via hole A3penetrating through the first insulation layer, the second gate insulation layer and the first gate insulation layer.

Step48: as shown inFIG.11, forming a source electrode110and a drain electrode111, the source electrode110being connected with the second active layer108through the via hole A2, the drain electrode111being connected with the second active layer108through the via hole A2, and the source electrode110being connected with the first active layer104through the via hole A3.

Step49: as shown inFIG.12, forming a third insulation layer (not shown), and forming a via hole A4in the third insulation layer.

Step410: as shown inFIG.13, forming a pixel electrode113, the pixel electrode113being connected with the drain electrode111through the via hole A4penetrating through the third insulation layer.

Step411: as shown inFIG.14, forming a fourth insulation layer (not shown), and forming a common electrode115on the fourth insulation layer.

The above embodiments are for illustrative purposes only, but the present disclosure is not limited thereto. Obviously, a person skilled in the art may make further modifications and improvements without departing from the spirit of the present disclosure, and these modifications and improvements shall also fall within the scope of the present disclosure.