Patent ID: 12199159

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Unless explicitly stated otherwise, each element having the same reference numeral is presumed to have the same material composition and to have a thickness within a same thickness range.

The present disclosure is directed to semiconductor devices, and particularly to flash memory devices including a buried floating gate and a buried erase gate and method of forming the same.

Generally, the methods and structures of the present disclosure may be used to provide a flash memory device including a buried floating gate electrode and a buried erase gate electrode. Use of the buried erase gate electrode improves the lifespan of a tunneling dielectric. In addition, the buried configurations for the floating gate electrode and the erase gate electrode may reduce the topography of the flash memory device. Thus, the lithographic images utilized for the formation of the device may be provided with better focus during formation of a control gate electrode. The flash memory device may be formed in a two-dimensional array configuration. The various features and aspects of embodiments of the present disclosure are now described with reference to the drawings.

Referring toFIGS.1A and1B, an exemplary structure according to an embodiment of the present disclosure is illustrated, which includes a semiconductor substrate8that may comprise a substrate semiconductor layer10. The semiconductor substrate8may be a bulk semiconductor substrate in which the substrate semiconductor layer10may extend from a front surface to a backside surface, or may be a semiconductor-on-insulator (SOI) substrate including a buried insulator layer (not shown) underlying the substrate semiconductor layer10and a handle substrate (not shown) that underlies the buried insulator layer. For example, the semiconductor substrate8may be a commercially available single crystalline bulk semiconductor substrate or a commercially available semiconductor-on-insulator substrate.

The substrate semiconductor layer10may include a single crystalline semiconductor material or a polycrystalline semiconductor material. In one embodiment, the entirety of the substrate semiconductor layer10may include a single crystalline semiconductor material such as single crystalline silicon. The semiconductor material of the substrate semiconductor layer10may have a doping of a first conductivity type, which may be p-type or n-type. The atomic concentration of dopants of the first conductivity type in the substrate semiconductor layer10may be in a range from 1.0×1014/cm3to 3.0×1017/cm3, although lesser and greater atomic concentrations may also be used. In one embodiment, the substrate semiconductor layer10may consist essentially of silicon and dopants of the first conductivity type.

Shallow trench isolation structures12may be formed in an upper portion of the substrate semiconductor layer10. For example, shallow trenches having a depth in a range from 50 nm to 500 nm may be formed through the top surface of the substrate semiconductor layer10, although greater or lesser depths used. The shallow trenches may be formed by applying and patterning a photoresist layer over the top surface of the substrate semiconductor layer10, and by transferring the pattern in the photoresist layer into the upper portion of the substrate semiconductor layer10using an anisotropic etch process. The photoresist layer may be subsequently removed, for example, by ashing. A dielectric material may be deposited in the shallow trenches, and excess portions of the dielectric may be removed from above the horizontal plane including the top surface of the substrate semiconductor layer10using a planarization process such as a chemical mechanical polishing (CMP) process. The remaining portions of the dielectric material that fill the shallow trenches comprise the shallow trench isolation structures12. In one embodiment, the shallow trench isolation regions may define device regions that are laterally spaced apart along a first horizontal direction hd1. Each device region laterally extends along the first horizontal direction hd1between a neighboring pair of shallow trench isolation structures12. Each device region may have a uniform width along the first horizontal direction hd1, and may laterally extend along a second horizontal direction hd2that is perpendicular to the first horizontal direction hd1. Each shallow trench isolation structure12may have a width in a range from 30 nm to 300 nm along the first horizontal direction hd1, although greater or lesser width may be used. The shallow trench isolation structures12may be arranged as a periodic one-dimensional array with a first pitch P1, i.e., a lateral distance at which a pattern is repeated, along the first horizontal direction hd1. While the present disclosure is described using portions of two device regions, it is understood that the exemplary structure may include multiple device regions and the illustrated structure may be repeated along the first horizontal direction hd1and along the second horizontal direction hd2.

Referring toFIGS.2A and2B, a first photoresist layer17may be applied over the top surface of the semiconductor substrate8. The first photoresist layer17may be lithographically patterned to form an array of openings therethrough. The openings in the first photoresist layer17may be located within the areas of the device regions located between neighboring pairs of shallow trench isolation structures12. The pattern of the openings in the first photoresist layer17may be a two-dimensional periodic pattern which has the first pitch P1along the first horizontal direction hd1and has a second pitch P2along a second horizontal direction hd2that is perpendicular to the first horizontal direction. In such an embodiment, the pattern of the openings in the first photoresist layer17may be a rectangular two-dimensional periodic array.

An anisotropic etch process may be performed to transfer the pattern of the openings in the first photoresist layer17into the substrate semiconductor layer10. First openings19may be formed in regions of the substrate semiconductor layer10that underlie the openings in the first photoresist layer17. The first openings19formed in the substrate semiconductor layer10are also referred to as floating gate openings. The horizontal cross-sectional shape of each first opening19may be a shape of a rectangle, a rounded rectangle (a shape derived from a rectangle by rounding the four corners), a circle, an ellipse, or any other curvilinear two-dimensional shape with, or without, straight edges. In one embodiment, the horizontal cross-sectional shape of each first opening19may be substantially rectangular (as shown inFIGS.2A and2B). The lateral dimension of each first opening19along the first horizontal direction hd1may be in a range from 20 nm to 200 nm, such as from 40 nm to 100 nm, although lesser and greater lateral dimensions may also be used. The lateral dimension of each first opening19along the second horizontal direction hd2may be in a range from 20 nm to 200 nm, such as from 40 nm to 100 nm, although lesser and greater lateral dimensions may also be used. The bottom surface of each first opening19may be located at a first depth d1from the horizontal plane including the top surface of the substrate semiconductor layer10. The first depth d1may be in a range from 20 nm to 200 nm, such as from 40 nm to 100 nm, although lesser and greater first depths may also be used. The first photoresist layer17may be subsequently removed, for example, by ashing.

Referring toFIGS.3A and3B, a tunneling dielectric layer20L may be formed on the bottom surfaces and the sidewalls of the first openings19and over the top surface of the substrate semiconductor layer10. The tunneling dielectric layer20L includes a tunneling dielectric material, i.e., a dielectric material through which charge carriers (such as electrons or holes) may tunnel through. For example, the tunneling dielectric layer20L may include thermal oxide formed by thermal oxidation of surface portions of the substrate semiconductor layer10that may be physically exposed to the first openings19or located at the top surface of the substrate semiconductor layer10. The thickness of the tunneling dielectric layer20L may be in a range from 2 nm to 6 nm, although lesser and greater thicknesses may also be used. In one embodiment, the horizontal portions and the vertical portions of the tunneling dielectric layer20L may have the same thickness throughout.

A floating gate electrode layer22L may be subsequently formed over the tunneling dielectric layer20L. The floating gate electrode layer22L includes a floating gate material, i.e., a material that may be used to form a floating gate electrode. For example, the floating gate electrode layer22L may include a doped semiconductor material (such as p-doped polysilicon or n-doped polysilicon), a metallic nitride material (such as titanium nitride or tantalum nitride), and/or an elemental metal or an intermetallic alloy. Other suitable materials are within the contemplated scope of the disclosure. In an illustrative example, the floating gate electrode layer22L includes doped poly silicon. The thickness of the floating gate electrode layer22L may be selected such that remaining volumes of the first openings19are filled with the floating gate electrode layer22L. The floating gate electrode layer22L may be deposited by a conformal deposition process such as a chemical vapor deposition (CVD) process.

Referring toFIGS.4A and4B, a planarization process may be performed to remove portions of the floating gate electrode layer22L and the tunneling dielectric layer20L that are located above the horizontal plane including the top surface of the substrate semiconductor layer10. The planarization process may use a chemical mechanical planarization (CMP) process and/or a recess etch process. In one embodiment, a chemical mechanical planarization process may be performed to planarize the floating gate electrode layer22L and the tunneling dielectric layer20L. Each remaining portion of the tunneling dielectric layer20L located in a respective first opening19comprises a tunneling dielectric20. Each remaining portion of the floating gate electrode layer22L located in a respective first opening19comprises a floating gate electrode22. A tunneling dielectric20and a floating gate electrode22may be formed in each first opening19. The tunneling dielectrics20and the floating gate electrodes22may have top surfaces located within the horizontal plane including the top surface of the substrate semiconductor layer10. Each floating gate electrode22may be formed within, and is laterally surrounded by, a respective tunneling dielectric20.

Each floating gate electrode22may be formed within a respective first opening19that vertically extends from the top surface of the substrate semiconductor layer10toward a backside surface of the substrate semiconductor layer10. Each tunneling dielectric20may be formed on sidewalls and a bottom surface of a respective first opening19. A two-dimensional array of floating gate electrodes22may be formed within the substrate semiconductor layer10that has a doping of the first conductivity type. The two-dimensional array of floating gate electrodes22may be a periodic array having a first pitch P1along the first horizontal direction hd1and having the second pitch P2along the second horizontal direction hd2. A two-dimensional array of tunneling dielectrics20may be formed within the substrate semiconductor layer10. The two-dimensional array of tunneling dielectrics20may be a periodic array having a first pitch P1along the first horizontal direction hd1and having the second pitch P2along the second horizontal direction hd2.

Referring toFIGS.5A and5B, a second photoresist layer27may be applied over the top surface of the semiconductor substrate8. The second photoresist layer27may be lithographically patterned to form an array of openings therethrough. The openings in the second photoresist layer27may be located adjacent to the areas of the first openings19that include the tunneling dielectrics20and the floating gate electrodes22. In one embodiment, the openings in the second photoresist layer27may be positioned such that each opening in the second photoresist layer27is laterally offset along the first horizontal direction hd1from a respective one of the first openings19. In one embodiment, a periphery of each opening in the second photoresist layer27may overlap with a periphery of a respective one of the first openings19in a plan view, i.e., a top-down view along a vertical direction that is perpendicular to the top surface of the semiconductor substrate8. The pattern of the openings in the second photoresist layer27may be a two-dimensional periodic pattern which has the first pitch P1along the first horizontal direction hd1and has a second pitch P2along a second horizontal direction hd2that is perpendicular to the first horizontal direction hd1. In such an embodiment, the pattern of the openings in the second photoresist layer27may be a rectangular two-dimensional periodic array. In one embodiment, each opening in the second photoresist layer27may have a sidewall that overlies, and contacts, a top surface of a respective one of the tunneling dielectrics20.

An anisotropic etch process may be performed to transfer the pattern of the openings in the second photoresist layer27into the substrate semiconductor layer10. Second openings29may be formed in regions of the substrate semiconductor layer10that underlie the openings in the second photoresist layer27. The second openings29formed in the substrate semiconductor layer10are also referred to as erase gate openings. Each second opening29may be formed adjacent to a respective one of the first openings19. In one embodiment, the chemistry of the anisotropic etch process may be selected such that the anisotropic etch process etches the semiconductor material of the substrate semiconductor layer10selective to the dielectric material of the tunneling dielectrics20. Thus, an outer sidewall of each second opening29may coincide with an outer sidewall of a respective one of the tunneling dielectrics20.

The horizontal cross-sectional shape of each second opening29may be a shape of a rectangle, a rounded rectangle (a shape derived from a rectangle by rounding the four corners), a circle, an ellipse, or any other curvilinear two-dimensional shape with, or without, straight edges. In one embodiment, the horizontal cross-sectional shape of each second opening29may be substantially rectangular. The lateral dimension of each second opening29along the first horizontal direction hd1may be in a range from 20 nm to 200 nm, such as from 40 nm to 100 nm, although lesser and greater lateral dimensions may also be used. The lateral dimension of each second opening29along the second horizontal direction hd2may be in a range from 20 nm to 200 nm, such as from 40 nm to 100 nm, although lesser and greater lateral dimensions may also be used. The bottom surface of each second opening29may be located at a second depth d2from the horizontal plane including the top surface of the substrate semiconductor layer10. The second depth d2may be less than, greater than, or equal to, the first depth d1. The second depth d2may be in a range from 200 nm to 200 nm, such as from 40 nm to 100 nm, although lesser and greater second depths may also be used. In one embodiment, the second depth d2may be less than the first depth d1. The second photoresist layer27may be subsequently removed, for example, by ashing.

Referring toFIGS.6A and6B, an erase gate dielectric layer30L may be formed on the bottom surfaces and the sidewalls of the second openings29and over the top surface of the substrate semiconductor layer10. The erase gate dielectric layer30L may include an erase gate dielectric material through which charge carriers (such as electrons or holes) may tunnel through. For example, the erase gate dielectric layer30L may include an ONO stack, i.e., a stack of a first silicon oxide layer301, a silicon nitride layer302, and a second silicon oxide layer303. The ONO stack may be formed, for example, by forming the first silicon oxide layer301by deposition of a silicon oxide material (for example, by thermal decomposition of tetraethylorthosilicate glass) or by thermal conversion of physically exposed surface portions of the substrate semiconductor layer10, by depositing a silicon nitride layer302, and by converting a surface portion of the silicon nitride layer into the second silicon oxide layer303by a thermal oxidation process. The thickness of the erase gate dielectric layer30L may be in a range from 2 nm to 6 nm, although lesser and greater thicknesses may also be used. In one embodiment, the horizontal portions and the vertical portions of the erase gate dielectric layer30L may have the same thickness throughout.

An erase gate electrode layer32L may be subsequently formed on the erase gate dielectric layer30L. The erase gate electrode layer32L includes a gate electrode material. For example, the erase gate electrode layer32L may include a doped semiconductor material (such as p-doped polysilicon or n-doped polysilicon), a metallic nitride material (such as titanium nitride or tantalum nitride), and/or an elemental metal or an intermetallic alloy. Other suitable materials are within the contemplated scope of disclosure. In an illustrative example, the erase gate electrode layer32L includes doped polysilicon. The thickness of the erase gate electrode layer32L may be selected such that remaining volumes of the second openings29may be filled with the erase gate electrode layer32L. The erase gate electrode layer32L may be deposited by a conformal deposition process such as a chemical vapor deposition (CVD) process.

Referring toFIGS.7A and7B, a planarization process may be performed to remove portions of the erase gate electrode layer32L and the erase gate dielectric layer30L that are located above the horizontal plane including the top surface of the substrate semiconductor layer10. The planarization process may use a chemical mechanical planarization (CMP) process and/or a recess etch process. In one embodiment, a chemical mechanical planarization process may be performed to planarize the erase gate electrode layer32L and the erase gate dielectric layer30L. Each remaining portion of the erase gate dielectric layer30L located in a respective second opening29comprises an erase gate dielectric30. Each remaining portion of the erase gate electrode layer32L located in a respective second opening29comprises an erase gate electrode32. An erase gate dielectric30and an erase gate electrode32may be formed in each second opening29. The erase gate dielectrics30and the erase gate electrodes32may have top surfaces located within the horizontal plane including the top surface of the substrate semiconductor layer10. Each erase gate electrode32may be formed within, and may be laterally surrounded by, a respective erase gate dielectric30.

Each erase gate electrode32may be formed within a respective second opening29that vertically extends from the top surface of the substrate semiconductor layer10toward a backside surface of the substrate semiconductor layer10. Each erase gate dielectric30may be formed on sidewalls and a bottom surface of a respective second opening29. A two-dimensional array of erase gate electrodes32may be formed within the substrate semiconductor layer10that has a doping of the first conductivity type. The two-dimensional array of erase gate electrodes32may be a periodic array having a first pitch P1along the first horizontal direction hd1and having the second pitch P2along the second horizontal direction hd2. A two-dimensional array of erase gate dielectrics30may be formed within the substrate semiconductor layer10. The two-dimensional array of erase gate dielectrics30may be a periodic array having a first pitch P1along the first horizontal direction hd1and having the second pitch P2along the second horizontal direction hd2.

The floating gate electrodes22and the erase gate electrodes32may be formed within the substrate semiconductor layer10. In one embodiment, each erase gate electrode32may be laterally spaced apart from the most proximal floating gate electrode22along the first horizontal direction hd1. In one embodiment, each erase gate electrode32may be formed at a location that is laterally spaced apart, i.e., laterally offset, from a most proximal floating gate electrode22along the first horizontal direction hd1. In one embodiment, each erase gate electrode32may be laterally spaced from the most proximal floating gate electrode22by a vertical portion of a tunneling dielectric20and a vertical portion of an erase gate dielectric30. In such an embodiment, the lateral spacing between each erase gate electrode32and the most proximal floating gate electrode22may be the sum of the thickness of the tunneling dielectric20and the thickness of the erase gate dielectric30. A two-dimensional array of erase gate electrodes32may be formed within the substrate semiconductor layer10, and may be laterally offset from the two-dimensional array of floating gate electrodes22along the first horizontal direction hd1. The offset direction between each neighboring pair of an erase gate electrode32and a floating gate electrode22is herein referred to as an axial direction. Each adjoined set of a tunneling dielectric20, a floating gate electrode22, an erase gate dielectric30, and an erase gate electrode32may have mirror symmetry about a vertical plane that horizontally extends along the axial direction. In the illustrated example, the axial direction may be the first horizontal direction hd1.

Referring toFIGS.8A and8B, a control gate dielectric layer40L may be deposited over the top surface of the substrate semiconductor layer10. The control gate dielectric layer40L may be deposited directly on the top surfaces of the tunneling dielectrics20, the floating gate electrodes22, the erase gate dielectrics30, and the erase gate electrodes32. In one embodiment, top surfaces of the tunneling dielectrics20, the floating gate electrodes22, the erase gate dielectrics30, and the erase gate electrodes32may be coplanar with the top surface of the substrate semiconductor layer10. The control gate dielectric layer40L includes a control gate dielectric material that is thick enough to prevent tunneling of charge carriers during operation. For example, the control gate dielectric layer40L may include an ONO stack, i.e., a stack of a first silicon oxide layer401, a silicon nitride layer402, and a second silicon oxide layer403. The ONO stack may be formed, for example, by forming the first silicon oxide layer401by deposition of a silicon oxide material (for example, by thermal decomposition of tetraethylorthosilicate glass) or by thermal conversion of physically exposed surface portions of the substrate semiconductor layer10, the floating gate electrodes22, and the erase gate electrodes32, by depositing a silicon nitride layer402, and by converting a surface portion of the silicon nitride layer into the second silicon oxide layer403by a thermal oxidation process. The thickness of the control gate dielectric layer40L may be in a range from 3 nm to 12 nm, although lesser and greater thicknesses may also be used. The control gate dielectric layer40L may be formed as a planar material layer having a uniform thickness throughout.

A control gate electrode layer42L may be subsequently formed on the control gate dielectric layer40L. The control gate electrode layer42L includes a gate electrode material. For example, the control gate electrode layer42L may include a doped semiconductor material (such as p-doped polysilicon or n-doped polysilicon), a metallic nitride material (such as titanium nitride or tantalum nitride), and/or an elemental metal or an intermetallic alloy. Other suitable materials are within the contemplated scope of disclosure. In an illustrative example, the control gate electrode layer42L includes doped poly silicon. The thickness of the control gate electrode layer42L may be in a range from 50 nm to 300 nm, such as from 100 nm to 200 nm, although lesser and greater thicknesses may also be used. The control gate electrode layer42L may be deposited by a conformal deposition process such as a chemical vapor deposition (CVD) process, or may be deposited by a non-conformal deposition process such as physical vapor deposition (PVD), i.e., sputtering.

Referring toFIGS.9A and9B, a third photoresist layer47may be applied over the control gate electrode layer42L, and may be lithographically patterned to form a patterned photoresist layer including discrete photoresist material portions. The patterned portions of the photoresist material portions of the third photoresist layer47may be formed as in areas that overlap with the areas of the two-dimensional array of floating gate electrodes22. In one embodiment, each of the floating gate electrodes22may be completely covered with lithographically patterned portions of the third photoresist layer47. In one embodiment, sidewalls of the discrete patterned portions of the third photoresist layer47may be formed within the areas of the top surfaces of the tunneling dielectrics20. In one embodiment, the discrete patterned portions of the third photoresist layer47may be formed as a periodic two-dimensional array of photoresist material portions having the first pitch P1along the first horizontal direction hd1and the second pitch P2along the second horizontal direction hd2.

The control gate dielectric layer40L and the control gate electrode layer42L are formed on a planar surface with no, or minimal, topographical variations. The lithographic patterning process that patterns the third photoresist layer47may form a lithographic image with a focal plane located within the third photoresist layer47. Since the third photoresist layer47does not have any topographical variations at the time of image formation, the third photoresist layer47may be patterned with high pattern fidelity.

An anisotropic etch process such as a reactive ion etch process may be performed to transfer the pattern in the third photoresist layer47through the control gate electrode layer42L and the control gate dielectric layer40L. The control gate electrode layer42L and the control gate dielectric layer40L may be anisotropically etched using the patterned third photoresist layer47as an etch mask. Patterned portion of the control gate electrode layer42L comprise the control gate electrodes42, and patterned portions of the control gate dielectric layer40L comprise control gate dielectrics40. A vertical stack of a control gate dielectric40and a control gate electrode42may be formed over each floating gate electrode22. Each control gate dielectric40may be located directly on a top surface of an underlying floating gate electrode22. Thus, the control gate dielectric40may contact the entirety of the top surface of the underlying floating gate electrode22, and may contact an inner periphery of the top surface of the underlying tunneling dielectric20. Each control gate electrode42overlies a respective underlying floating gate electrode22, and is vertically spaced from the respective underlying floating gate electrode22by a control gate dielectric40. Each tunneling dielectric20laterally surrounding a respective floating gate electrode22, and contacts a bottom surface of a respective control gate dielectric40. A two-dimensional array of control gate electrodes42may be formed, which may be a periodic two-dimensional array having the first pitch P1along the first horizontal direction hd1and having the second pitch P2along the second horizontal direction hd2. The third photoresist layer47may be subsequently removed, for example, by ashing.

Referring toFIGS.10A and10B, a dielectric spacer material layer may be conformally deposited on the physically exposed surfaces of the control gate electrodes42, the control gate dielectrics40, and the various structures formed in the semiconductor substrate8. The dielectric spacer material layer includes a dielectric material such as silicon oxide or silicon nitride. Other suitable materials are within the contemplated scope of disclosure. The conformal deposition of the dielectric spacer material layer may be effected, for example, by a chemical vapor deposition process such as a low pressure chemical vapor deposition (LPCVD) process. The thickness of the dielectric spacer material layer may be in a range from 5 nm to 80 nm, such as from 10 nm to 40 nm, although lesser and greater thicknesses may also be used. The thickness of the dielectric spacer material layer is less than the lateral dimension of each erase gate dielectric30along the first horizontal direction hd1so that a top surface of each erase gate electrode32may be physically exposed after formation of dielectric gate spacers.

An anisotropic etch process may be performed to remove horizontally-extending portions of the dielectric spacer material layer. The horizontally-extending portions of the dielectric spacer material layer are removed from above the top surfaces of the control gate electrodes42, and from above portions of the top surface of the semiconductor substrate8that are laterally spaced from the control gate electrodes42by a spacing greater than the thickness of the dielectric spacer material layer. Vertically-extending portions of the dielectric spacer material layer that laterally surround a respective one of the control gate electrodes42constitute dielectric gate spacers46. Each dielectric gate spacer46may have a generally tubular configuration, and thus, may be topologically homeomorphic to a torus. The lateral thickness of each dielectric gate spacer46may be the same as the thickness of the dielectric spacer material layer, and thus, may be in a range from 5 nm to 80 nm, such as from 10 nm to 40 nm, although lesser and greater thicknesses may also be used. Top surfaces of the erase gate electrodes32and the erase gate dielectrics30may be physically exposed after formation of the dielectric gate spacers46. Each dielectric gate spacer46contacts a top surface of a vertical segment of an erase gate dielectric30. In one embodiment, each dielectric gate spacer46may contact at least a portion, and/or all of, the outer periphery of a top surface of an underlying tunneling dielectric20. In one embodiment, each dielectric gate spacer46may contact all sidewalls of a respective control gate electrode42and a top surface of a respective underlying tunneling dielectric20, which may be formed in the substrate semiconductor layer10and laterally surrounds a floating gate electrode22.

Referring toFIGS.11A-11E, various active regions (62,66,132,138) may be formed in various regions of the exemplary structure by performing at least one masked ion implantation process.FIGS.11A-11Cillustrate a memory region in which a two-dimensional array of flash memory cells is formed.FIGS.11D and11Eillustrate a logic region in which logic devices, such as field effect transistors of a control circuit that controls the operation of the flash memory cells, are formed. A logic gate dielectric layer may be formed in the logic region in lieu of the control gate dielectric layer40L at the processing steps ofFIGS.8A and8B, for example, by removal of the silicon nitride layer402and the first silicon oxide layer401from the logic region prior to formation of the second silicon oxide layer403. A silicon oxide layer may be formed in the logic region on the top surface of the substrate semiconductor layer10concurrently with formation of the second silicon oxide layer403. The control gate electrode layer42L may be formed in the logic region concurrently with formation of the control gate electrode layer42L in the memory array region. The control gate electrode layer42L and the silicon oxide layer in the logic region may be patterned to form gate stacks, each which may include a gate dielectric140and a gate electrode142. Gate spacers146may be formed around each gate stack (140,142) concurrently with formation of the dielectric gate spacers46.

Electrical dopants (such as p-type dopants or n-type dopants) may be implanted into unmasked portions of the substrate semiconductor layer10in the logic region prior to, and/or after, formation of the gate spacers146to form source regions132and drain regions138. Each source region132may include a source extension region132E and a deep source region132D, and each drain region138may include a drain extension region138E and a deep drain region138D. Each surface portion of the substrate semiconductor layer10that underlies a gate stack (140,142) and located between a pair of a source region132and a drain region138constitutes a semiconductor channel135. The logic region may include p-type field effect transistors (i.e., field effect transistors including a p-doped source region, a p-doped drain region, and an n-doped channel region) and n-type field effect transistors (i.e., field effect transistors including an n-doped source region, an n-doped drain region, and a p-doped channel region).

A subset of the masked ion implantation processes used to form the source regions132and the drain regions138of the field effect transistors may be used to implant dopants of a second conductivity type into discrete surface portions of the substrate semiconductor layer10in the memory array region. The second conductivity type is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa.

The dopants of the second conductivity type that are implanted into the memory array region may form active region (62,66). The active regions (62,66) may function as source regions or drain regions during operation of the flash memory cells. The active regions (62,66) may include axial active regions62that are laterally offset from a most proximal one of the floating gate electrodes22along the axial direction, such as the first horizontal direction hd1. Further, the active regions (62,66) may include lateral active regions66that are laterally offset from a most proximal one of the floating gate electrodes22along a lateral direction, which is the horizontal direction that is perpendicular to the axial direction. In the illustrative example, the lateral direction may be the second horizontal direction hd2.

In one embodiment, each lateral active region66may be formed between a pair of tunneling dielectrics20that is laterally spaced apart along the lateral direction such as the second horizontal direction hd2. Each axial active region62may be spaced from a most proximal floating gate electrode22along the axial direction such as the first horizontal direction hd1. The axial active region62may be located on the opposite side of an erase gate electrode32with respective to the most proximal floating gate electrode22. A lateral active region66may contact sidewalls of a pair of tunneling dielectrics20. The sidewalls of the tunneling dielectrics20that contact a respective lateral active region66may be parallel to the first horizontal direction hd1. An axial active region62may contact a sidewall of a most proximal tunneling dielectric20. The sidewalls of the tunneling dielectric20that contact a respective axial active region62may be parallel to the second horizontal direction hd2. The axial active regions62may contact a respective one of the shallow trench isolation structures12.

A p-n junction may be formed at each interface between the active regions (62,66) and the substrate semiconductor layer10. The axial active regions62may be formed as a two-dimensional periodic array of axial active regions62having the first pitch P1along the first horizontal direction hd1and having the second pitch P2along the second horizontal direction hd2. The lateral active regions66may be formed as a two-dimensional array of lateral active regions66having the first pitch P1along the first horizontal direction hd1and having the second pitch P2along the second horizontal direction hd2.

A pair of active regions (such as a pair of lateral active regions66) may be formed within the substrate semiconductor layer10by implanting dopants having a doping of the second conductivity type for each flash memory cell. The pair of active regions may be laterally spaced apart by the floating gate electrode22located therebetween. For example, the pair of active regions is formed on opposing sides of the floating gate electrode22, and is laterally spaced apart along the second horizontal direction hd2that is perpendicular to the first horizontal direction hd1.

In embodiments in which a plurality of flash memory cells may be formed in a two-dimensional array configuration, the lateral active regions66may be shared by a neighboring pair of flash memory cells that are laterally spaced along the second horizontal direction hd2. In such an embodiment, a two-dimensional array of active regions (such as a two-dimensional array of lateral active regions66) may be formed within the substrate semiconductor layer10. The two-dimensional array of lateral active regions66may have a doping of the second conductivity type, and may be laterally offset from the two-dimensional array of floating gate electrodes22along the second horizontal direction hd2that is different from the first horizontal direction hd1. Each of the floating gate electrodes22may be located between a neighboring pair of lateral active regions66within the two-dimensional array of lateral active regions66.

In one embodiment, each dielectric gate spacer46may contact all sidewalls of a respective control gate electrode42, each top surface of a pair of active regions (such as a pair of lateral active regions66), and a top surface of an underlying tunneling dielectric20formed within the substrate semiconductor layer10and laterally surrounding a respective floating gate electrode22.

Referring toFIGS.12A-12C, a planarization dielectric layer70may be deposited over the two-dimensional array of control gate electrodes42and the semiconductor substrate8. The planarization dielectric layer70includes a self-planarizing dielectric material or a dielectric material that may be planarized by a planarization process. For example, the planarization dielectric layer70may include flowable oxide (FOX), undoped silicate glass, or a doped silicate glass. In embodiments in which the planarization dielectric layer70may be planarized, a chemical mechanical planarization process may be performed to form a horizontal top surface that overlies the top surfaces of the control gate electrodes42. The planarization dielectric layer70laterally surrounds, and overlies, each of the control gate electrodes42and the dielectric gate spacers46. The planarization dielectric layer70may contact a top surface of each erase gate electrode32.

A photoresist layer (not shown) may be applied over the planarization dielectric layer70, and may be lithographically patterned to form openings in areas that overlie the control gate electrodes42, the erase gate electrodes32, the axial active regions62, and the lateral active regions66. An anisotropic etch process may be performed to transfer the pattern of the openings in the photoresist layer through the planarization dielectric layer70. Via cavities vertically extending through the planarization dielectric layer70may be formed. The via cavities include control gate contact via cavities that extend to a respective one of the control gate electrodes42, erase gate contact via cavities that extend to a respective one of the erase gate electrodes32, axial contact via cavities that extend to a respective one of the axial active regions62, and lateral contact via cavities that extend to a respective one of the lateral active regions66.

Optionally, metal-semiconductor alloy regions (not illustrated) may be formed on physically exposed surfaces of the control gate electrodes42, the erase gate electrodes32, the axial active regions62, and the lateral active regions66. A metallic material that forms a metal-semiconductor alloy with a semiconductor material may be deposited on the physically exposed top surfaces of the control gate electrodes42, the erase gate electrodes32, the axial active regions62, and the lateral active regions66, and an anneal process may be performed to induce formation of a metal-semiconductor alloy material. In one embodiment, the metal-semiconductor alloy may include a metal silicide. The metallic material may include, for example, tungsten, titanium, cobalt, nickel, or a metallic alloy thereof. Other suitable materials are within the contemplated scope of disclosure. Unreacted portions of the metallic material may be removed selective to the metal-semiconductor alloy material using a selective wet etch process.

At least one metallic material may be deposited in the remaining volumes of the various via cavities. The at least one metallic material may include, for example, a metal nitride liner such as TiN, TaN, or WN, and a metallic fill material such as W, Cu, Co, Ru, or Mo. Other suitable materials are within the contemplated scope of disclosure. Excess portions of the at least one metallic material overlying the top surface of the planarization dielectric layer70may be removed by a planarization process, which may use a chemical mechanical planarization process and/or a recess etch process. Remaining portions of the at least one metallic material in the various via cavities comprise contact via structures (84,88,82,86). The various contact via structures (84,88,82,86) comprise control gate contact via structures84that contact a top surface of a respective one of the control gate electrodes42, erase gate contact via structures88that contact a top surface of a respective one of the erase gate electrodes32, axial active region contact via structures82that contact a top surface of a respective one of the axial active regions62, and lateral active region contact via structures86that contact a top surface of a respective one of the lateral active regions66.

Each flash memory cell comprises a control gate contact via structure84formed within the planarization dielectric layer70and contacting a control gate electrode42, a pair of active region contact via structures (such as a pair of lateral active region contact via structures86) formed in the planarization dielectric layer70and contacting top surfaces of a pair of active regions (such as a pair of lateral active regions66), and an erase gate contact via structure88formed in the planarization dielectric layer70and contacting a top surface of an erase gate electrode32.

In embodiments in which a two-dimensional array of flash memory cells may be formed, the lateral active regions66may be shared between a neighboring pair of flash memory cells. In one embodiment, the array of flash memory cells comprises a two-dimensional periodic array of unit flash memory cells UC. The unit flash memory cell UC may be repeated within the two-dimensional periodic array with the first pitch P1along the first horizontal direction hd1and with the second pitch P2along the second horizontal direction hd2. Each of the two-dimensional array of floating gate electrodes22, the two-dimensional array of erase gate electrodes32, the two-dimensional array of lateral active regions66, and the two-dimensional array of control gate electrodes42may have the same first pitch P1along the first horizontal direction hd1and the same second pitch P2along the second horizontal direction hd2.

Each unit flash memory cell UC in the two-dimensional periodic array comprises a floating gate electrode22in the two-dimensional array of floating gate electrodes22, an erase gate electrode32in the two-dimensional array of erase gate electrodes32, an active region (such as a lateral active region66) in a two-dimensional array of active regions (such as the lateral active regions66), and a control gate electrode42in the two-dimensional array of control gate electrodes42. Each active region (such as each lateral active region66) located between a pair of floating gate electrodes22that is laterally spaced apart along the second horizontal direction hd2may contact a pair of tunneling dielectrics20that contact a respective floating gate electrode22within the pair of floating gate electrodes22.

Each floating gate electrode22within the array of flash memory cells may be located within a respective first opening19that vertically extends from a top surface of the substrate semiconductor layer10toward a backside surface of the substrate semiconductor layer10, and each erase gate electrode32within the array of flash memory cells may be located within a respective second opening29that vertically extends from the top surface of the substrate semiconductor layer10toward the backside surface of the substrate semiconductor layer10.

According to various embodiments of the present disclosure, a flash memory device is provided, which comprises: a floating gate electrode22formed within a substrate semiconductor layer10having a doping of a first conductivity type; a pair of active regions (such as a pair of lateral active regions66) formed within the substrate semiconductor layer10, having a doping of a second conductivity type, and laterally spaced apart by the floating gate electrode22; an erase gate electrode32formed within the substrate semiconductor layer10and laterally offset from the floating gate electrode22(for example, along a first horizontal direction hd1); and a control gate electrode42that overlies the floating gate electrode22.

According to various embodiments of the present disclosure, an array of flash memory cells is provided, which comprises: a two-dimensional array of floating gate electrodes22that may be formed within a substrate semiconductor layer10having a doping of a first conductivity type; a two-dimensional array of erase gate electrodes32that may be formed within the substrate semiconductor layer10and is laterally offset from the two-dimensional array of floating gate electrodes22along a first horizontal direction hd1; a two-dimensional array of active regions (such as the lateral active regions66) that may be formed within the substrate semiconductor layer10, having a doping of a second conductivity type, and is laterally offset from the two-dimensional array of floating gate electrodes22along a second horizontal direction hd2that is different from the first horizontal direction hd1, wherein each of the floating gate electrodes22is located between a neighboring pair of active regions within the two-dimensional array of active regions; and a two-dimensional array of control gate electrodes42that overlie a respective one of the floating gate electrodes22.

Referring toFIG.13, a flowchart illustrates steps for forming the exemplary structure of the present disclosure. Referring to step1810, a first opening19may be formed in a substrate semiconductor layer10having a doping of a first conductivity type. Referring to step1820, a tunneling dielectric20and a floating gate electrode22may be formed in the first opening19. Referring to step1830, a second opening29may be formed in the substrate semiconductor layer10adjacent to the first opening19. Referring to step1840, an erase gate dielectric30and an erase gate electrode32may be formed in the second opening29. Referring to step1850, a control gate dielectric40and a control gate electrode42may be formed over the floating gate electrode22. Referring to step1860, a pair of active regions (such as a pair of lateral active regions66) may be formed within the substrate semiconductor layer10by implanting dopants having a doping of a second conductivity type, wherein the pair of active regions is laterally spaced apart by the floating gate electrode22.

Each flash memory cell may be programmed by providing an electrical bias across a pair of active regions adjacent to a floating gate electrode22. For example, a pair of lateral active regions66adjacent to a floating gate electrode22may be electrically biased to provide a potential difference therebetween, and a control gate electrode42that overlies the floating gate electrode22may be electrically biased to induce tunneling of charge carriers (such as electrons) from a channel portion of the substrate semiconductor layer10that underlies the floating gate electrode22through the tunneling dielectric20into the floating gate electrode22. Alternatively, a pair of an axial active region62and a lateral active region66may be used to provide a potential difference therebetween while a programming voltage is applied to the control gate electrode42to induce tunneling of charge carriers into the floating gate electrode22.

Each flash memory cell may be sensed by electrically biasing a pair of lateral active regions66adjacent to a floating gate electrode22to provide a potential difference therebetween, and by applying a sensing voltage to the control gate electrode42that overlies the floating gate electrode22. The sensing voltage has a lesser magnitude than the programming voltage, and is insufficient to induce tunneling of charge carriers (such as electrons) into the floating gate electrode22. The amount of electrical charges in the floating gate electrode22modulates the magnitude of electrical current through the channel portion of the substrate semiconductor layer10that underlies the floating gate electrode22. Thus, the state of the flash memory cell as represented by the amount of trapped electrical charges in the floating gate electrode22may be determined by the sensing operation. Alternatively, a pair of an axial active region62and a lateral active region66may be used to provide a potential difference for a sensing operation while a sensing voltage (with a lesser magnitude than the programming voltage) is applied to the control gate electrode42to measure the magnitude of the electrical current through the channel portion of the substrate semiconductor layer10that underlies the floating gate electrode22.

Each flash memory cell may be erased by electrically biasing the erase gate electrode32. For example, if electrons are trapped in the floating gate electrode22, a large positive bias may be applied to the erase gate electrode32to induce tunneling of the electrons from the floating gate electrode22into the erase gate electrode32. A negative bias voltage may be applied to the control gate electrode42to assist tunneling of the electrons from the floating gate electrode22into the erase gate electrode32.

The various structures and methods of the present disclosure may be used to provide a flash memory device in which each floating gate electrode22and each erase gate electrode32are buried within the substrate semiconductor layer10underneath a horizontal plane including the planar top surface of the substrate semiconductor layer10. Tunneling of charge carriers into the floating gate electrode22during a programming operation may be performed using vertical portions of the tunneling dielectric20that laterally extend along the first horizontal direction hd1and the horizontal bottom portion of the tunneling dielectric20. Tunneling of charge carriers out of the floating gate electrode22during an erase operation may be performed using a different vertical portion of the tunneling dielectric20that laterally extend along the second horizontal direction hd2. Thus, the life span of the tunneling dielectric20may be prolonged, and the flash memory device may be operated over more programming and erase operations.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.