Patent ID: 12224238

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As integrated circuit (IC) technology advances, IC features (e.g., transistor gate length) continue to decrease, thereby allowing for more circuitry to be implemented in an IC. One challenge with implementing OTP memory devices such as, for example, a fuse, an electronic fuse (eFuse), etc., in an IC is that eFuse size reduction has not advanced at nearly the same rate as the reduction in size of transistor features. The eFuse memory is a type of OTP memory that includes a one-transistor, one-resistor (1T1R) configuration. Typically, the resistor is connected to a bit line, and an access transistor is gated by the word line. The resistor includes a metal-insulator-metal (MIM) structure which includes a metal-based material whose resistance can change depending on the voltage difference across the MIM.

A typical eFuse memory cell requires a large programming voltage and/or current in order to adjust the resistance of the resistor of the eFuse memory cell, which often requires a greater cell area. Therefore, the “fuse” (i.e., (the resistor) has to be longer and/or thicker in order to properly program the memory cell. Furthermore, the typical resistor of the eFuse memory cell, which is disposed in a metallization layer, e.g., metallization layer M2, may not be scalable for future technology nodes because the M2parameters can change depending on the technology node. The resistor, which is typically formed during a back-end-of-line (BEOL) process in the M2layer, requires a high programming voltage which may not be satisfactory for advanced technology nodes. Accordingly, there is a desire to develop an eFuse memory cell that has a smaller cell area and requires a low programming voltage.

In the present disclosure, a novel eFuse memory cell structure can be formed to provide several advantages over the current technology. For example, the MIM fuse (e.g., the resistor fuse material) can be based on titanium nitride (TiN). TiN is sometimes used as a barrier material between a metal and a semiconductor to prevent harmful interactions between the metal and the semiconductor. In the present disclosure, the TiN can be used as the metal fuse for the eFuse memory cell. Furthermore, the MIM fuse can be formed during a back-end-of-line (BEOL) process or a middle-end-of-line (MEOL) process, and be located anywhere between the bit line and the active transistor of the eFuse memory cell. For example, the TiN layer can be formed between the M2and M3layers above the source/drain terminal of the access transistor. This can advantageously reduce a cell area of the eFuse memory cell. Furthermore, because of the favorable characters of the TiN material, the metal fuse can be advantageously shorter than the current technology. This can also advantageously help with reducing a programming voltage of the eFuse memory cell.

FIG.1Aillustrates a schematic block diagram of a memory device100, in accordance with some embodiments. A memory device is a type of an IC device. In at least one embodiment, a memory device is an individual IC device. In some embodiments, a memory device is included as a part of a larger IC device which comprises circuitry other than the memory device for other functionalities.

The memory device100comprises at least one memory cell103and a controller (also referred to as “control circuit”)102coupled to control an operation of the memory cell103. In the example configuration inFIG.1A, the memory device100comprises a plurality of memory cells103arranged in a plurality of columns and rows in a memory array104. The memory device100further comprises a plurality of word lines WL[0] to WL[m] extending along the rows, a plurality of source lines SL[0] to SL[m] extending along the rows, and a plurality of bit lines (also referred to as “data lines”) BL[0] to BL[k] extending along the columns of the memory cells103. Each of the memory cells103is coupled to the controller102by at least one of the word lines, at least one of the source lines, and at least one of the bit lines. Examples of word lines include, but are not limited to, read word lines for transmitting addresses of the memory cells103to be read from, write word lines for transmitting addresses of the memory cells103to be written to, or the like. In at least one embodiment, a set of word lines is configured to perform as both read word lines and write word lines. Examples of bit lines include read bit lines for transmitting data read from the memory cells103indicated by corresponding word lines, write bit lines for transmitting data to be written to the memory cells103indicated by corresponding word lines, or the like. In at least one embodiment, a set of bit lines is configured to perform as both read bit lines and write bit lines. In one or more embodiments, each memory cell103is coupled to a pair of bit lines referred to as a bit line and a bit line bar. The word lines are commonly referred to herein as WL, the source lines are commonly referred to herein as SL, and the bit lines are commonly referred to herein as BL. Various numbers of word lines and/or bit lines and/or source lines in the memory device100are within the scope of various embodiments. In at least one embodiment, the source lines SL are arranged in the columns, rather than in the rows as shown inFIG.1A. In at least one embodiment, the source lines SL are omitted.

In the example configuration inFIG.1A, the controller102comprises a word line driver112, a source line driver114, a bit line driver116, and a sense amplifier (SA)118which are configured to perform at least one of a read operation or a write operation. In at least one embodiment, the controller102further includes one or more clock generators for providing clock signals for various components of the memory device100, one or more input/output (I/O) circuits for data exchange with external devices, and/or one or more controllers for controlling various operations in the memory device100. In at least one embodiment, the source line driver114is omitted.

The word line driver112is coupled to the memory array104via the word lines WL. The word line driver112is configured to decode a row address of the memory cell103selected to be accessed in a read operation or a write operation. The word line driver112is configured to supply a voltage to the selected word line WL corresponding to the decoded row address, and a different voltage to the other, unselected word lines WL.

The source line driver114is coupled to the memory array104via the source lines SL. The source line driver114is configured to supply a voltage to the selected source line SL corresponding to the selected memory cell103, and a different voltage to the other, unselected source lines SL.

The bit line driver116(also referred as “write driver”) is coupled to the memory array104via the bit lines BL. The bit line driver116is configured to decode a column address of the memory cell103selected to be accessed in a read operation or a write operation. The bit line driver116is configured to supply a voltage to the selected bit line BL corresponding to the decoded column address, and a different voltage to the other, unselected bit lines BL. In a write operation, the bit line driver116is configured to supply a write voltage (also referred to as “program voltage”) to the selected bit line BL. In a read operation, the bit line driver116is configured to supply a read voltage to the selected bit line BL.

The SA118is coupled to the memory array104via the bit lines BL. In a read operation, the SA118is configured to sense data read from the accessed memory cell103and retrieved through the corresponding bit lines BL. The described memory device configuration is an example, and other memory device configurations are within the scopes of various embodiments. In at least one embodiment, the memory device100is NVM, and the memory cells103are OTP memory cells. Other types of memory are within the scopes of various embodiments. Example memory types of the memory device100include, but are not limited to, eFuse, anti-fuse, magnetoresistive random-access memory (MRAM), or the like.

FIG.1Billustrates a portion of the memory array104(FIG.1A), in accordance with some embodiments. As shown, the memory array104comprises a plurality of memory cells103, for example,103A,103B,103C,103D,103E,103F,103G, and103H. Although eight memory cells are shown inFIG.1B, it should be understood that the memory array104can include any number of memory cells103, while remaining within the scope of present disclosure.

Each of the memory cells103A to103H has a 1T1R configuration with the source line SL grounded, and comprises a transistor and a series coupled in series between a corresponding bit line and SL. For example, the memory cells103A to103H correspondingly comprise capacitors resistors R0, R1, R2, R3, R4, R5, R6, and R7, and transistors T0, T1, T2, T3, T4, T5, T6, and T7. The resistors R0to R3of the memory cells103A to103D are commonly coupled to a bit line BL0. Gate terminals of the transistors T0, T1, T2, T3are correspondingly coupled to word lines WL0, WL1, WL2, and WL3. The resistors R4-R7of the memory cells103E-103H are commonly coupled to a bit line BL1. Gate terminals of the transistors T4-T7are correspondingly coupled to the word lines WL0, WL1, WL2, WL3. The memory cells103A-103D commonly coupled to the bit line BL0correspond to a first string of memory cells, and the memory cells103E-103H commonly coupled to the bit line BL1correspond to a second string of memory cells. In at least one embodiment, each of the memory cells103A-103H corresponds to a memory cell103, each of the bit lines BL0, BL1corresponds to a bit line BL, and each of the word lines WL0, WL1, WL2, WL3corresponds to a word line WL in the memory device100. In at least one embodiment, one or more advantages described herein are achievable in the memory array104.

FIG.2illustrates an example configuration of the eFuse cell103(FIG.1A), in accordance with some embodiments. The eFuse cell103is implemented as a 1T1R configuration, for example, a fuse resistor202serially connected to an access transistor204. It, however, should be understood that any of various other fuse configurations that exhibit the fuse characteristic may be used by the eFuse cell103such as, for example, a 2-diodes-1-resistor (2D1R) configuration, a many-transistors-one-resistor (manyT1R) configuration, etc., while remaining within the scope of the present disclosure.

In accordance with various embodiments of the present disclosure, the fuse resistor202is formed of one or more metal structures. For example, the fuse resistor202may be one of a number of interconnect structures in one of a number metallization layers that are disposed above the access transistor204. Specifically, the access transistor204is formed over a major surface of a semiconductor substrate, which is sometimes referred to as part of front-end-of-line (FEOL) processing. Over the FEOL processing, a number of metallization layers, each of which includes a number of interconnect (e.g., metal) structures, are typically formed, which are sometimes referred to as part of BEOL processing. During the BEOL processing, or between the FEOL and BEOL processing, there can be processing steps where local electrical connections between transistors and metal gate contacts are formed during the MEOL processing.

With the fuse resistor202(of the eFuse cell103) embodied as a metal structure, the fuse resistor202may present an initial resistance value (or resistivity), for example, as fabricated. To program the eFuse cell103, the access transistor204(if embodied as an n-type transistor) is turned on by applying a (e.g., voltage) signal, corresponding to a logic high state, through a WL to a gate terminal of the access transistor204. Concurrently or subsequently, a high enough (e.g., voltage) signal is applied on one of the terminals of the fuse resistor202through a BL. With the access transistor204turned on to provide a (e.g., program) path from the BL, through the fuse resistor202and access transistor204, and to a SL, such a high voltage signal can burn out a portion of the corresponding metal structure (the fuse resistor202), thereby transitioning the fuse resistor202from a first state (e.g., a short circuit) to a second state (e.g., an open circuit). Accordingly, the eFuse cell103can irreversibly transition from a first logic state (e.g., logic 0) to a second logic state (e.g., logic 1), which can be read out by applying a relatively low voltage signal on the BL and turning on the access transistor204to provide a (e.g., read) path.

FIG.3illustrates a cross-sectional view of a memory cell300(e.g., eFuse cell103), in accordance with some embodiments. The memory cell300includes a transistor302(e.g., access transistor204) and a metal-based layer310(e.g., metal-based layer of the fuse resistor202).

The memory cell300includes a plurality of metallization layers and via structures that is stacked over the drain structure306. In this disclosure, a metallization layer (or interconnect structure) refers to a layer formed during the MEOL or BEOL process in which multiple metal or interconnect structures are formed and laterally separated from each other by interlayer dielectric (ILD). A top surface and a bottom surface of the ILD can define a boundary of the metallization layer. In the memory cell300, the metallization layers in the memory cell300includes interconnect structures MD, M0, M1, M2, M3, M3, M4, M5, M6and M7, which are each formed in their respective metallization layers. Although a certain number of interconnect structures are formed inFIG.3, embodiments are not limited thereto, and fewer or more metallization layers and interconnect structures can be formed. Furthermore, a plurality of vias structures VD, VIA0, VIA1, VIA2, VIA3, VIA4, VIA5, and VIA6are formed over the drain structure306and electrically connecting adjacent interconnect structures to each other. For example, the via structure VIA1electrically connects the interconnect structure M0to the interconnect structure M1, the via structure VIA2electrically connects the interconnect structure M1to the interconnect structure M2, and so on and so forth.

The transistor302includes an n-type transistor, but embodiments are not limited thereto. The transistor302is can be any suitable type of transistor including, but not limited to, metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductors (CMOS) transistors, P-channel metal-oxide semiconductors (PMOS), N-channel metal-oxide semiconductors (NMOS), bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, P-channel and/or N-channel field effect transistors (PFETs/NFETs), FinFETs, planar MOS transistors with raised source/drains, nanosheet FETs, nanowire FETs, or the like.

The transistor302includes a source structure304(e.g., source of access transistor204), a drain structure306(e.g., drain of access transistor204), and a gate structure308(e.g., gate of access transistor204). The source structure304can be electrically connected to a SL (e.g., SL ofFIG.2), and the gate structure308can be connected to a WL (e.g., WL ofFIG.2). The drain structure306can be electrically connected to a BL (e.g., BL ofFIG.2) through the via structures VD-VIA6and the interconnect structures MD-M7.

The metal-based layer310can include a metal-based layer formed of, but not limited to, TiN. Furthermore, the metal-based layer310can include material including tantalum nitride (TaN), alloy of Ti and TiN, alloy of Ta and TaN, or combinations thereof. Although the metal-based layer310is shown to be located between certain structures/layers inFIG.3(e.g., between via structure VD and interconnect structure M0), embodiments are not limited thereto, and the metal-based layer310can be located anywhere between the transistor302and the BL. For example, the metal-based layer310can be located anywhere between a source/drain terminal (drain ofFIG.2) of the transistor302and the BL.

FIG.4illustrates a cross-sectional view of a memory cell400(e.g., eFuse cell103), in accordance with some embodiments. The memory cell400includes an eFuse memory cell including a transistor402(e.g., transistor302) and a metal-based layer410(e.g., metal-based layer310). The memory cell400is similar to the memory cell300except that the metal-based layer410is located between a drain structure406of the transistor402and the interconnect structure MD. For example, the metal-based layer410is disposed on a top surface of the drain structure406, and the interconnect structure MD is disposed on a top surface of the metal-based layer410. Accordingly, the metal-based layer410can be formed during a MEOL process.

FIG.5illustrates a cross-sectional view of a memory cell500(e.g., eFuse cell103), in accordance with some embodiments. The memory cell500includes an eFuse memory cell including a transistor502(e.g., transistor302) and a metal-based layer510(e.g., metal-based layer310). The memory cell500is similar to the memory cell300except that the metal-based layer510is located between the interconnect structure MD and the via structure VD. For example, the metal-based layer510is disposed on a top surface of the interconnect structure MD, and the via structure VD is disposed on a top surface of the metal-based layer510. Accordingly, the metal-based layer510can be formed during a MEOL process.

FIG.6illustrates a cross-sectional view of a memory cell600(e.g., eFuse cell103), in accordance with some embodiments. The memory cell600includes an eFuse memory cell including a transistor602(e.g., transistor302) and a metal-based layer610(e.g., metal-based layer310). The memory cell600is similar to the memory cell300except that the metal-based layer610is located between the via structure VD and the interconnect structure M0. For example, the metal-based layer610is disposed on a top surface of the via structure VD, and the interconnect structure M0is disposed on a top surface of the metal-based layer610. Accordingly, the metal-based layer610can be formed during a BEOL process.

FIG.7illustrates a cross-sectional view of a memory cell700(e.g., eFuse cell103), in accordance with some embodiments. The memory cell700includes an eFuse memory cell including a transistor702(e.g., transistor302) and a metal-based layer710(e.g., metal-based layer310). The memory cell400is similar to the memory cell300except that the metal-based layer410is located between the interconnect structure M0and the via structure VIA0. For example, the metal-based layer710is disposed on a top surface of the interconnect structure M0, and the via structure VIA0is disposed on a top surface of the metal-based layer710. Accordingly, the metal-based layer710can be formed during a BEOL process.

FIG.8illustrates a cross-sectional view of a memory cell800(e.g., eFuse cell103), in accordance with some embodiments. The memory cell800includes an eFuse memory cell including a transistor802(e.g., transistor302) and a metal-based layer810(e.g., metal-based layer310). The memory cell800is similar to the memory cell300except that the metal-based layer810is located between the via structure VIA0and the interconnect structure M1. For example, the metal-based layer810is disposed on a top surface of the via structure VIA0, and the interconnect structure M1is disposed on a top surface of the metal-based layer810. Accordingly, the metal-based layer810can be formed during a BEOL process.

FIG.9illustrates a cross-sectional view of a memory cell900(e.g., eFuse cell103), in accordance with some embodiments. The memory cell900includes an eFuse memory cell including a transistor902(e.g., transistor302) and a metal-based layer910(e.g., metal-based layer310). The memory cell900is similar to the memory cell300except that the metal-based layer910is located between interconnect structure MX and via structure VIAX, where interconnect structure MX represents any interconnect structure formed over the drain structure906and via structure VIAX represents any via structure formed interconnect structure MX. For example, the metal-based layer910is disposed on a top surface of the interconnect structure MX, and the via structure VIAX is disposed on a top surface of the metal-based layer910. Accordingly, the metal-based layer910can be formed during a BEOL process.

FIG.10illustrates a cross-sectional view of a memory cell1000(e.g., eFuse cell103), in accordance with some embodiments. The memory cell1000includes an eFuse memory cell including a transistor1002(e.g., transistor302) and a metal-based layer1010(e.g., metal-based layer310). The memory cell1000is similar to the memory cell300except that the metal-based layer1010is located between interconnect structure MX+1 and via structure VIAX, where interconnect structure MX+1 represents any interconnect structure formed over the drain structure1006and via structure VIAX represents any via structure disposed below the interconnect structure MX+1. For example, the metal-based layer1010is disposed on a top surface of the via structure VIAX, and the interconnect structure MX+1 is disposed on a top surface of the metal-based layer1010. Accordingly, the metal-based layer1010can be formed during a BEOL process.

FIG.11illustrates a cross-sectional view of a memory cell1100(e.g., eFuse cell103), in accordance with some embodiments. The memory cell1100includes an eFuse memory cell including a transistor1102(e.g., transistor302) and a metal-based layer1110(e.g., metal-based layer310). The memory cell1100is similar to the memory cell300except that the metal-based layer1110is located within the via structure VD. For example, the metal-based layer1110is disposed on a first portion of the via structure VD, and a second portion of the via structure VD is disposed on the metal-based layer1110.

FIG.12illustrates a cross-sectional view of a memory cell1200(e.g., eFuse cell103), in accordance with some embodiments. The memory cell1200includes an eFuse memory cell including a transistor1202(e.g., transistor302) and a metal-based layer1210(e.g., metal-based layer310). The memory cell1200is similar to the memory cell300except that the metal-based layer1210is located within the via structure VIA0. For example, the metal-based layer1210is disposed on a first portion of the via structure VIA0, and a second portion of the via structure VIA0is disposed on the metal-based layer1210.

FIG.13illustrates a cross-sectional view of a memory cell1300(e.g., eFuse cell103), in accordance with some embodiments. The memory cell1300includes an eFuse memory cell including a transistor1302(e.g., transistor302) and a metal-based layer1310(e.g., metal-based layer310). The memory cell1300is similar to the memory cell300except that the metal-based layer1310is located within the via structure VIAX, where via structure VIAX represents any via structure disposed over the drain structure1306. For example, the metal-based layer1310is disposed on a first portion of the via structure VIAX, and a second portion of the via structure VIAX is disposed on the metal-based layer1310.

FIGS.14A-14Ceach illustrates a cross-sectional view of a portion of a memory cell (e.g., memory cell600,800,1000), in accordance with some embodiments. Referring toFIG.14A, the portion includes an interconnect structure1402a(e.g., interconnect structure MX+1), a metal-based layer1404a(e.g., metal-based layer610,804,1004), and a via structure1406a(e.g., via structure VIAX). Referring toFIG.14B, the portion includes an interconnect structure1402b(e.g., interconnect structure MX+1), a metal-based layer1404b(e.g., metal-based layer610,804,1004), and a via structure1406b(e.g., via structure VIAX). Referring toFIG.14C, the portion includes an interconnect structure1402c(e.g., interconnect structure MX+1), a metal-based layer1404c(e.g., metal-based layer610,804,1004), and a via structure1406c(e.g., via structure VIAX).

Each of the metal-based layers1404a,1404b, and1404chas a width W1. The interconnect structures1402a,1402b, and1402chas a bottom surface with a width W2. In theFIG.14Bembodiment, W2is substantially the same as W1. In theFIGS.14A and14Cembodiments, W1is less than W2. In theFIG.14Aembodiment, the ratio between the W1and W2is about 0.6, whereas the ratio is about 0.2 in theFIG.14Cembodiment. However, the ratios are not limited thereto. For example, the ratio can be any number between 0 and 1.

FIGS.15A-15Ceach illustrates a cross-sectional view of a portion of a memory cell (e.g., memory cell700,900), in accordance with some embodiments. Referring toFIG.15A, the portion includes a via structure1502a(e.g., via structure VIAX), a metal-based layer1504a(e.g., metal-based layer710,904), and an interconnect structure1506a(e.g., interconnect structure MX). Referring toFIG.15B, the portion includes a via structure1502b(e.g., via structure VIAX), a metal-based layer1504b(e.g., metal-based layer710,904), and an interconnect structure1506b(e.g., interconnect structure MX). Referring toFIG.15C, the portion includes a via structure1502c(e.g., via structure VIAX), a metal-based layer1504c(e.g., metal-based layer710,904), and an interconnect structure1506c(e.g., interconnect structure MX).

Each of the metal-based layers1504a,1504b, and1504chas a width W1. The via structures1502a,1502b, and1502chas a bottom surface with a width W3. In theFIG.15Bembodiment, W3is substantially the same as W1. In theFIGS.15A and15Cembodiments, W3is less than W1. In theFIG.15Aembodiment, the ratio between the W3and W1is about 0.6, whereas the ratio is about 0.2 in theFIG.15Cembodiment. However, the ratios are not limited thereto. For example, the ratio can be any number between 0 and 1.

FIGS.16A-16Ceach illustrates a cross-sectional view of a portion of a memory cell (e.g., memory cell500), in accordance with some embodiments. Referring toFIG.16A, the portion includes a via structure1602a(e.g., via structure VD), a metal-based layer1604a(e.g., metal-based layer510), and an interconnect structure1606a(e.g., interconnect structure MD). Referring toFIG.15B, the portion includes a via structure1602b(e.g., via structure VD), a metal-based layer1604b(e.g., metal-based layer510), and an interconnect structure1606b(e.g., interconnect structure MD). Referring toFIG.16C, the portion includes a via structure1602c(e.g., via structure VD), a metal-based layer1604c(e.g., metal-based layer510), and an interconnect structure1606c(e.g., interconnect structure MD).

Each of the metal-based layers1604a,1604b, and1604chas a width W1. The interconnect structures1606a,1606b, and1606chas a top surface with a width W4. In theFIG.16Bembodiment, W4is substantially the same as W1. In theFIGS.16A and16Cembodiments, W4is less than W1. In theFIG.16Aembodiment, the ratio between the W1and W4is about 0.6, whereas the ratio is about 0.2 in theFIG.16Cembodiment. However, the ratios are not limited thereto. For example, the ratio can be any number between 0 and 1.

FIGS.17A-17Ceach illustrates a cross-sectional view of a portion of a memory cell (e.g., memory cell400), in accordance with some embodiments. Referring toFIG.17A, the portion includes an interconnect structure1702a(e.g., interconnect structure MD), a metal-based layer1704a(e.g., metal-based layer410), and a drain structure1706a(e.g., drain structure406). Referring toFIG.17B, the portion includes an interconnect structure1702b(e.g., interconnect structure MD), a metal-based layer1704b(e.g., metal-based layer410), and a drain structure1706b(e.g., drain structure406). Referring toFIG.17C, the portion includes an interconnect structure1702c(e.g., interconnect structure MD), a metal-based layer1704c(e.g., metal-based layer410), and a drain structure1706c(e.g., drain structure406).

Each of the metal-based layers1704a,1704b, and1704chas a width W1. The drain structures1706a,1706b, and1706chas a top surface with a width W5. In theFIG.17Bembodiment, W5is substantially the same as W1. In theFIGS.17A and17Cembodiments, W1is less than W5. In theFIG.17Aembodiment, the ratio between the W1and W5is about 0.6, whereas the ratio is about 0.2 in theFIG.17Cembodiment. However, the ratios are not limited thereto. For example, the ratio can be any number between 0 and 1.

FIG.18illustrates a cross-sectional view of a memory cell1800, in accordance with some embodiments. The memory cell1800incudes a transistor1802(e.g., access transistor204) and a resistor (e.g., fuse resistor202) including a metal-based layer1810. The memory cell1800is similar to the memory cell300, except that the memory cell1800includes a backside power rail on a second side (e.g., backside) of a substrate1801in which the metal-based layer1810is disposed.

The transistor1802includes a gate structure PO, an S/D structure1804(e.g., drain of access transistor204), and an S/D structure [1802]1806(e.g., source of access transistor204). The gate structure PO is electrically connected to the word line WL, the S/D structure1806is electrically connected to the source line SL, and the S/D structure1804is electrically connected to the bit line BL through a plurality of via structures VB, BV0, BV1, etc. and a plurality of backside interconnect structures BM0, BM1, etc.

The metal-based layer1810is disposed between the backside interconnect structure BM0and the backside via structure BV0. Specifically, the metal-based layer1810is disposed below a bottom surface of the backside interconnect structure BM0and above a top surface of the backside via structure BV0. Accordingly, the resistor of the memory cell1800includes a first terminal, including the backside interconnect structure BM0and the backside via structure VB, a second terminal including the backside via structure BV0, the backside interconnect structure BM1, etc. disposed below the metal-based layer1810, and the metal-based layer1810disposed between the first and second terminals. The first terminal is electrically connected to the S/D structure1804, and the second terminal is electrically connected to the bit line BL.

AlthoughFIG.18shows that the metal-based layer1810is disposed between the backside interconnect structure BM0and the backside via structure BV0, embodiments are not limited thereto. For example, the metal-based layer1810can be disposed between any backside interconnect structure BMX and any backside via structure BVX that is the first backside via structure disposed below the backside interconnect structure BMX. For example, the metal-based layer1810can be disposed between backside interconnect structure BM1and backside via structure BV1, and so on and so forth.

FIG.19illustrates a cross-sectional view of a memory cell1900, in accordance with some embodiments. The memory cell1900incudes a transistor1902(e.g., access transistor204) and a resistor (e.g., fuse resistor202) including a metal-based layer1910. The memory cell1900is similar to the memory cell300, except that the memory cell1900includes a backside power rail on a second side (e.g., backside) of a substrate1901in which the metal-based layer1910is disposed.

The transistor1902includes a gate structure PO, am S/D structure1904(e.g., drain of access transistor204), and an S/D structure1906(e.g., source of access transistor204). The gate structure PO is electrically connected to the word line WL, the S/D structure1906is electrically connected to the source line SL, and the S/D structure1904is electrically connected to the bit line BL through a plurality of via structures VB, BV0, BV1, etc. and a plurality of backside interconnect structures BM0, BM1, etc.

The metal-based layer1910is disposed between the backside via structure BV0and the backside interconnect structure BM1. Specifically, the metal-based layer1910is disposed below a bottom surface of the backside via structure BV0and above a top surface of the backside interconnect structure BM1. Accordingly, the resistor of the memory cell1900includes a first terminal, including the backside via structure BV0, the backside interconnect structure BM0and the backside via structure VB, a second terminal including the backside interconnect structure BM1, etc. disposed below the metal-based layer1910, and the metal-based layer1910disposed between the first and second terminals. The first terminal is electrically connected to the S/D structure1904, and the second terminal is electrically connected to the bit line BL.

AlthoughFIG.19shows that the metal-based layer1910is disposed between the backside via structure BV0and the backside interconnect structure BM1, embodiments are not limited thereto. For example, the metal-based layer1910can be disposed between any backside via structure BVX and any backside interconnect structure BMX that is the first backside via structure disposed below the backside via structure BVX. For example, the metal-based layer1910can be disposed between the backside via structure BV1and the backside interconnect structure BM2, and so on and so forth.

FIG.20illustrates a cross-sectional view of a memory cell2000, in accordance with some embodiments. The memory cell2000includes a transistor2002(e.g., access transistor204) and a resistor (e.g., fuse resistor202) including a metal-based layer2010. The memory cell2000is similar to the memory cell300, except that the memory cell2000includes a backside power rail on a second side (e.g., backside) of a substrate2001in which the metal-based layer2010is disposed.

The transistor2002includes a gate structure PO, am S/D structure2004(e.g., drain of access transistor204), and an S/D structure2006(e.g., source of access transistor204). The gate structure PO is electrically connected to the word line WL, the S/D structure2006is electrically connected to the source line SL, and the S/D structure2004is electrically connected to the bit line BL through a plurality of via structures VB, BV0, BV1, etc. and a plurality of backside interconnect structures BM0, BM1, etc.

The metal-based layer2010is disposed between a first portion BV0_O of the backside via structure BV0and a second portion BV0_1of the backside via structure BV0. Specifically, the metal-based layer2010is disposed below a bottom surface of the first portion BV0_O and above a top surface of the second portion BV0_1. Accordingly, the resistor of the memory cell2000includes a first terminal, including the first portion BV0_0, the backside interconnect structure BM0and the backside via structure VB, a second terminal including the second portion BV0_1, the backside interconnect structure BM1, etc. disposed below the metal-based layer2010, and the metal-based layer2010disposed between the first and second terminals. The first terminal is electrically connected to the S/D structure2004, and the second terminal is electrically connected to the bit line BL.

AlthoughFIG.20shows that the metal-based layer2010is disposed between the first portion BV0_0and the second portion BV0_1of the backside via structure BV0, embodiments are not limited thereto. For example, the metal-based layer2010can be disposed in between two portions of a backside via structure BVX. For example, the metal-based layer2010can be disposed between a first portion VB_0and a second portion VB_1of the backside via structure VB, and so on and so forth.

In one aspect of the present disclosure, a memory device is disclosed. The memory device includes a transistor; and a resistor electrically connected to the transistor, the transistor and the resistor forming a first OTP memory cell, wherein the resistor includes a metal-based layer with a resistivity configured to irreversibly transition from a first resistance state to a second resistance state.

In another aspect of the present disclosure, a memory device is disclosed. The memory device includes a transistor; a resistor electrically coupled to the transistor, the transistor and the resistor forming an eFuse memory cell; a plurality of interconnect structures formed over a source/drain structure of the transistor; and a plurality of via structures formed over the source/drain structure of the transistor. The resistor is disposed between the source/drain structure of the transistor and a topmost one of the plurality of interconnect structures, and the resistor is formed of TiN.

In yet another aspect of the present disclosure, a memory array is disclosed. The memory array includes a substrate; and a memory array disposed over the substrate and comprising a plurality of OTP memory cells, each of the OTP memory cells comprising a transistor and a resistor electrically connected to each other. The resistor of each of the OTP memory cells is formed of a metal-based material configured to present a low resistance state prior to programming the corresponding memory cell and a high resistance state in response to programming the corresponding memory cell.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.