Patent ID: 12199214

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so as to fully convey the spirit of the present disclosure to those skilled in the art to which the present disclosure pertains. Accordingly, the present disclosure is not limited to the embodiments disclosed herein and can also be implemented in different forms. In the drawings, widths, lengths, thicknesses, and the like of elements can be exaggerated for clarity and descriptive purposes. It will be understood that, when an element such as a layer, film, region or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. Throughout the specification, like reference numerals denote like elements having the same or similar functions. Also, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising”, “includes” and/or “including”, “have” and/or “having” when used in this specification, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

In accordance with one exemplary embodiment of the present disclosure, a light emitting diode includes: a substrate; first to fourth light emitting cells disposed on the substrate; a first electrode pad; and a second electrode pad. In this exemplary embodiment, each of the light emitting cells includes a lower semiconductor layer, an upper semiconductor layer, and an active layer interposed between the lower semiconductor layer and the upper semiconductor layer, wherein the lower semiconductor layer includes a first lower semiconductor layer and a second lower semiconductor layer separated from each other; the first light emitting cell and the second light emitting cell share the first lower semiconductor layer; the third light emitting cell and the fourth light emitting cell share the second lower semiconductor layer; the first light emitting cell is connected in series to the third light emitting cell; the second light emitting cell is connected in series to the fourth light emitting cell; the first electrode pad is electrically connected to the upper semiconductor layer of each of the first light emitting cell and the second light emitting cell; and the second electrode pad is electrically connected to the lower semiconductor layers of the third light emitting cell and the fourth light emitting cell. Accordingly, the light emitting diodes include the light emitting cells connected to each other in series-parallel connection, and thus can reduce current density for driving and can achieve uniform current spreading to the light emitting cells, thereby improving luminous efficacy.

In addition, since the first and second light emitting cells share the first lower semiconductor layer and the third and fourth light emitting cells share the second lower semiconductor layer, the light emitting diode according to this exemplary embodiment allow a simple manufacturing process and can minimize reduction in luminous area due to isolation between light emitting cells.

Specifically, the first lower semiconductor layer and the second lower semiconductor layer may be isolated from each other by an isolation groove exposing an upper surface of the substrate, and the first light emitting cell and the third light emitting cell may be isolated from the second light emitting cell and the fourth light emitting cell by a mesa isolation grove exposing the first lower semiconductor layer and the second lower semiconductor layer, respectively.

In some exemplary embodiments, the light emitting diode may further include a transparent electrode layer disposed on the upper semiconductor layer of each of the light emitting cells.

The first electrode pad may be disposed on the mesa isolation groove and may straddle the first light emitting cell and the second light emitting cell. Here, the transparent electrode layer may be disposed between each of the first and second light emitting cells and the first electrode pad.

The light emitting diode may further include a current blocking layer disposed under the first electrode pad. The current blocking layer may have a larger area than the first electrode pad such that the first electrode pad is placed only in an upper region of the current blocking layer, and a portion of the current blocking layer may be disposed between each of the first and second light emitting cells and the transparent electrode layer.

The transparent electrode layer on each of the first and second light emitting cells may include an opening exposing the current blocking layer, and the first electrode pad may be connected to the current blocking layer through the opening.

The light emitting diode may further include upper extension portions disposed on the transparent electrode layer of each of the light emitting cells and electrically connected to the transparent electrode layer; and current blocking layers disposed between the transparent electrode layers and the light emitting cells under the upper extension portions. A width of each of the current blocking layers may be less than three times the width of each of the upper extension portions. The current blocking layers aid in uniform current spreading over a light emitting cell region. In addition, light loss by the current blocking layers can be reduced by adjusting the width of the current blocking layer.

The light emitting diode may further include a lower extension portion connected to the lower semiconductor layer of each of the light emitting cells. The lower extension portions may include linear regions extending in the same direction, the linear region of the lower extension portion of the first light emitting cell may be parallel to the linear region of the lower extension portion of the third light emitting cell, and the linear region of the lower extension portion of the second light emitting cell may be parallel to the linear region of the lower extension portion of the fourth light emitting cell.

The upper extension portions disposed on the transparent electrode layers of the first light emitting cell and the second light emitting cell are electrically connected to the first electrode pad, and the lower extension portions connected to the lower semiconductor layers of the third light emitting cell and the fourth light emitting cell are electrically connected to the second electrode pad. Thus, the light emitting cells are connected in series-parallel between the first electrode pad and the second electrode pad.

Each of the upper extension portions may include a primary upper extension portion configured to surround a portion of the corresponding lower extension portion and a secondary upper extension portion protruding from the primary upper extension portion.

The secondary upper extension portion on each of the first light emitting cell and the second light emitting cell may be disposed to connect the primary upper extension portion to the first electrode pad, and the secondary upper extension portions on the third light emitting cell and the fourth light emitting cell may be disposed to connect the primary upper extension portions on the third light emitting cell and the fourth light emitting cell to the lower extension portions of the first light emitting cell and the second light emitting cell, respectively.

The secondary upper extension portions on the first light emitting cell and the second light emitting cell may be connected to the primary upper extension portions closer to the mesa isolation groove than the corresponding lower extension portions. Thus, the lengths of the secondary upper extension portions can be reduced.

The light emitting diode may further include connecting portions which connect the lower extension portions on the first and second light emitting cells to the secondary upper extension portions on the third and fourth light emitting cells, respectively. The light emitting diode may further include an insulating layer insulating the connecting portions from the second lower semiconductor layers of the third light emitting cell and the fourth light emitting cell.

The lower extension portions of the third light emitting cell and the fourth light emitting cell may further include lower extension portions in a curved region connecting the lower extension portions in the linear region to the second electrode pad. Furthermore, the second electrode pad may be disposed on the second lower semiconductor layer exposed by the mesa isolation groove.

The light emitting diode may further include an insulating layer covering side surfaces of the upper semiconductor layer and the active layer around the second electrode pad. The insulating layer can prevent short circuit by a bonding material in a ball-bonding process.

The insulating layer covering the side surfaces of the upper semiconductor layer and the active layer may be separated from the transparent electrode layer.

In some exemplary embodiments, the first electrode pad and the second electrode pad may be disposed to face each other, wherein the first electrode pad may be disposed near one edge of the substrate and the second electrode pad may be disposed near the other edge of the substrate facing the one edge thereof.

Each of the primary upper extension portions on the third light emitting cell and the fourth light emitting cell may include an inner end disposed between the lower extension portion of the third light emitting cell and the lower extension portion of the fourth light emitting cell, and an outer end disposed outside the lower extension portion, and the outer end of the lower extension portion may be disposed closer to the other edge of the substrate than the inner end.

The light emitting diode may have a symmetrical structure with respect to an imaginary line passing through the first electrode pad and the second electrode pad.

In accordance with another exemplary embodiment of the present disclosure, a light emitting diode includes: a substrate; a semiconductor stack disposed on the substrate and including a lower semiconductor layer, an upper semiconductor layer and an active layer interposed between the lower semiconductor layer and the upper semiconductor layer, the semiconductor stack having an isolation groove exposing the substrate through the upper semiconductor layer, the active layer and the lower semiconductor layer; a first electrode pad and an upper extension portion electrically connected to the upper semiconductor layer; a second electrode pad and a lower extension portion electrically connected to the lower semiconductor layer; a connecting portion connecting the upper extension portion and the lower extension portion to each other across the isolation groove and having a greater width than the upper extension portion and the lower extension portion; a first current blocking layer interposed between the lower extension portion and the lower semiconductor layer; and a second current blocking layer interposed between the second electrode pad and the lower semiconductor layer, wherein the first current blocking layer includes a plurality of dots separated from one another, a width each of the dots is greater than the width of the lower extension portion, the second current blocking layer has a smaller width than the second electrode pad, and the shortest distance from the isolation groove to the first current blocking layer is greater than a separation distance between the dots.

A connection region in which the connecting portion and the lower extension portion are connected to the lower semiconductor layer between the isolation groove and the current blocking layer may have a greater length than a connection region in which the lower extension portion is connected to the lower semiconductor layer between two adjacent dots.

The upper extension portion may be separated from the lower extension portion and a distal end of the lower extension portion may be directly connected to the lower semiconductor layer. The upper extension portion may be disposed to surround the distal end of the lower extension portion.

In this structure, a diagonal distance from the distal end of the lower extension portion to the upper extension portion may be greater than a horizontal distance from the distal end of the lower extension portion to the upper extension portion. Here, the horizontal distance means a distance from the distal end of the lower extension portion to the upper extension portion in a horizontal direction that is parallel to the substrate, and the diagonal distance means a distance from the distal end of the lower extension portion to the upper extension portion in a slanted direction with respect to the horizontal direction.

The first current blocking layer and the second current blocking layer may include an SiO2layer or a distributed Bragg reflector layer.

The light emitting diode may further include a transparent electrode layer disposed on the upper semiconductor layer, wherein a part of the transparent electrode layer may be disposed between the upper semiconductor layer and the first electrode pad and between the upper semiconductor layer and the upper extension portion.

The light emitting diode may further include a third current blocking layer disposed between the upper semiconductor layer and the transparent electrode layer under the first electrode pad.

The transparent electrode layer may have an opening exposing the third current blocking layer and the first electrode pad may be connected to the third current blocking layer through the opening. The third current blocking layer may have a larger area than the first electrode pad such that the first electrode pad is disposed only on the third current blocking layer.

The semiconductor stack may include a plurality of light emitting cells defined by the isolation groove or the mesa isolation groove and each of the plurality of light emitting cells may include the lower extension portion and the upper extension portion.

The connecting portion may be disposed on the isolation groove and electrically connect the upper extension portion and the lower extension portion of two adjacent light emitting cells.

The plurality of light emitting cells may include first to fourth light emitting cells; the lower semiconductor layer may include a first lower semiconductor layer and a second lower semiconductor layer separated from each other by the isolation groove; the first light emitting cell and the second light emitting cell may share the first lower semiconductor layer; the third light emitting cell and the fourth light emitting cell may share the second lower semiconductor layer; the first light emitting cell may be connected in series to the third light emitting cell through the connecting portion; and the second light emitting cell may be connected in series to the fourth light emitting cell through the connecting portion.

The lower extension portions of the light emitting cells may include linear regions extending in the same direction; the linear region of the lower extension portion of the first light emitting cell may be coaxial with the linear region of the lower extension portion of the third light emitting cell; and the linear region of the lower extension portion of the second light emitting cell may be coaxial with the linear region of the lower extension portion of the fourth light emitting cell.

The first electrode pad may be disposed on the mesa isolation groove so as to straddle the first light emitting cell and the second light emitting cell, and the second electrode pad may be disposed on the mesa isolation groove so as to be electrically connected to the second lower semiconductor layer.

The upper extension portion disposed on the transparent electrode layer of each of the first light emitting cell and the second light emitting cell may be electrically connected to the first electrode pad, and the lower extension portion disposed on the lower semiconductor layer of each of the third light emitting cell and the fourth light emitting cell may be electrically connected to the second electrode pad.

The upper extension portion of each of the light emitting cells may include a primary upper extension portion configured to surround a portion of the corresponding lower extension portion and a secondary upper extension portion protruding from the primary upper extension portion.

The secondary upper extension portion on each of the first light emitting cell and the second light emitting cell may be disposed to connect the primary upper extension portion to the first electrode pad, and the secondary upper extension portions on the third light emitting cell and the fourth light emitting cell may be disposed to connect the primary upper extension portions on the third light emitting cell and the fourth light emitting cell to the lower extension portions of the first light emitting cell and the second light emitting cell, respectively.

The first light emitting cell and the third light emitting cell may be connected in parallel to the second light emitting cell and the fourth light emitting cell through the first electrode pad and the second electrode pad.

Each of the light emitting cells may include a step on a side surface of the substrate, and the side surface of the substrate may be exposed.

Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

FIG.1is a plan view of a light emitting diode according to one exemplary embodiment of the present disclosure,FIG.2is a cross-sectional view taken along line A-A ofFIG.1,FIG.3is a cross-sectional view taken along line B-B ofFIG.1, andFIG.4is a cross-sectional view taken along line C-C ofFIG.1.FIG.5is an enlarged plan view of a first electrode pad ofFIG.1andFIG.6is a cross-sectional view taken along line D-D ofFIG.5.FIG.7is an enlarged plan view of second electrode pads ofFIG.1andFIG.8is a cross-sectional view taken along line E-E ofFIG.7.

Referring toFIG.1, the light emitting diode according to this exemplary embodiment includes a first light emitting cell C1, a second light emitting cell C2, a third light emitting cell D1, and a fourth light emitting cell D2disposed on a substrate21. In addition, the light emitting diode includes a first electrode pad37, a second electrode pad35, upper extension portions37a,37b,37c,37d, lower extension portions35a,35b, connecting portions35c, current blocking layers31a,31d, insulating layers32a,32b, and a transparent electrode layer33. As best shown inFIG.2toFIG.4, each of the light emitting cells C1, C2, D1, D2includes a lower semiconductor layer23aor23b, an active layer25, and an upper semiconductor layer27.

The substrate21may be selected from any substrates suitable for growth of a gallium nitride-based semiconductor layer. For example, the substrate21may include a sapphire substrate, a silicon carbide substrate, a gallium nitride substrate, an aluminum nitride substrate, a silicon substrate, and the like. In this exemplary embodiment, the substrate21may be a patterned sapphire substrate (PSS).

The lower semiconductor layers23a,23b, the active layer25and the upper semiconductor layer27may be Group III-V based, particularly, gallium nitride-based compound semiconductor layers. These semiconductor layers may include, for example, a nitride semiconductor, such as (Al, Ga, In)N. The lower semiconductor layers23a,23bmay include n-type dopants (for example, Si) and the upper semiconductor layer27may include p-type dopants (for example, Mg), or vice versa. The active layer25may have a multi-quantum well (MQW) structure and the composition of the active layer25may be adjusted to emit light in a desired wavelength range. The first to fourth light emitting cells C1, C2, D1, D2may be formed by sequentially growing the lower semiconductor layers23a,23b, the active layer25and the upper semiconductor layer27on the substrate21, followed by patterning these semiconductor layers. These semiconductor layers may be grown by, for example, metal organic vapor deposition, molecular beam epitaxy, hydride vapor phase epitaxy, and the like.

The first light emitting cell C1and the second light emitting cell C2are isolated from the third light emitting cell D1and the fourth light emitting cell D2by an isolation groove30a, respectively, and the first light emitting cell C1and the third light emitting cell D1are isolated from the second light emitting cell C2and the fourth light emitting cell D2by a mesa isolation groove27a, respectively. That is, the first and second light emitting cells C1, C2are isolated from the third and fourth light emitting cells D1, D2, respectively, by an isolation process, in which the isolation groove30ais formed to expose the substrate21. Meanwhile, the first light emitting cell C1and the third light emitting cell D1are isolated from the second light emitting cell C2and the fourth light emitting cell D2, respectively, by a mesa etching process, in which the mesa isolation groove27ais formed to expose the lower semiconductor layers23a,23b. In this structure, the first light emitting cell C1and the second light emitting cell C2share a first lower semiconductor layer23a, and the third light emitting cell D1and the fourth light emitting cell D2share a second lower semiconductor layer23b. Further, the first lower semiconductor layer23aand the second lower semiconductor layer23bare separated from each other by the isolation groove30a.

Referring toFIG.2, other electrode portions are not disposed in the mesa isolation groove27aexcept for the first electrode pad37and the second electrode pad35, and the lower semiconductor layers23a,23bmay be exposed through the mesa isolation groove27a.

The first light emitting cell C1may have the same shape as the second light emitting cell C2and the third light emitting cell D1may have the same shape as the fourth light emitting cell D2. Here, due to the structure of the second electrode pad35, the third light emitting cell D1and the fourth light emitting cell D2may have a slightly different shape than the first light emitting cell C1and the second light emitting cell C2. These light emitting cells C1, C2, D1, D2may generally have an elongated rectangular shape.

The first electrode pad37is disposed near one edge21aof the substrate21and the second electrode pad35is disposed near the other edge21bof the substrate21facing the one edge21a. As shown inFIG.1, the first electrode pad37and the second electrode pad35may be disposed to face each other. The first electrode pad37and the second electrode pad35are disposed on the mesa isolation groove27a. In addition, the first electrode pad37may be formed to straddle the first light emitting cell C1and the second light emitting cell C2. The first electrode pad37and the second electrode pad35will be described in detail below with reference toFIG.5andFIG.7.

The transparent electrode layer33is disposed on each of the light emitting cells. The transparent electrode layer33is connected to the upper semiconductor layer27. The transparent electrode layer33may be formed of a light transmissive and electrically conductive material, for example, a conductive oxide such as ITO, ZnO and IZO or a light transmissive metal such as Ni/Au. The transparent electrode layer33has lower sheet resistance than the upper semiconductor layer27and thus serves to distribute electric current over a wide area. In addition, the transparent electrode layer33forms ohmic contact with the upper semiconductor layer27to input electric current to the upper semiconductor layer27.

The lower semiconductor layer23aor23bis exposed through the upper semiconductor layer27and the active layer25of each of the light emitting cells, and the lower extension portion35aor35bis disposed in an exposed region of the lower semiconductor layer23aor23b. The lower extension portions35a,35bare electrically connected to the lower semiconductor layers23a,23b.

The lower extension portions35adisposed on the first light emitting cell C1and the second light emitting cell C2may include linear regions, respectively, and the linear regions may be parallel to each other. In addition, as shown inFIG.1andFIG.4, the lower extension portion35aof the first light emitting cell C1may be coaxial with a linear region of the lower extension portion35bof the third light emitting cell D1.

Each of the lower extension portions35bdisposed on the third light emitting cell D1and the fourth light emitting cell D2may be connected to the second electrode pad35and may include the linear region and a curved region. The curved region of the lower extension portion may connect the linear region thereof to the second electrode pad35. The lower extension portions35bin the linear regions on the third light emitting cell D1and the fourth light emitting cell D2may be parallel to each other. Further, the lower extension portion35bmay extend along the center of each of the light emitting cells D1, D2.

The upper extension portions37a,37b,37c,37dare disposed on the transparent electrode layer33. A secondary upper extension portion37aand a primary upper extension portion37bare disposed on each of the first and second light emitting cells C1, C2, and a secondary upper extension portion37cand a primary upper extension portion37dare disposed on each of the third and fourth light emitting cells D1, D2.

The primary upper extension portion37bdisposed on each of the first light emitting cell C1and the second light emitting cell C2surrounds a distal end of the lower extension portion35aand a portion of a side surface thereof. Herein, the inside of the lower extension portion35ameans a side of the lower extension portion35athat is closer to the mesa isolation groove27a, and the outside of the lower extension portion35ameans the other side of the lower extension portion35a. In this structure, a portion of the primary upper extension portion37bis disposed outside the lower extension portion35a, another portion thereof is disposed inside the lower extension portion35a, and a third portion thereof is disposed between the distal end of the lower extension portion35aand the one edge21aof the substrate21. In addition, the primary upper extension portion37bhas two ends, which are placed inside and outside the lower extension portion35a, respectively. The primary upper extension portion37bmay have a symmetrical structure with respect to a straight line extending from the lower extension portion35a.

The primary upper extension portion37bextends from the one edge21aside of the substrate21, at which the first electrode pad37is disposed, towards the other edge21bside thereof, at which the second electrode pad35is disposed. As shown inFIG.1, the distance between the primary upper extension portion37band the lower extension portion35amay be variable. For example, the distance between the primary upper extension portion37band the lower extension portion35amay increase and then decrease along an imaginary line extending from the primary upper extension portion37b. The distance from the lower extension portion35ato the primary upper extension portion37bmay be generally greater than the distance from the primary upper extension portion37bto an edge of a first lower semiconductor layer23aor to the mesa isolation groove27a. Here, the distance from an inner end (on the inside of the lower extension portion35a) or outer end (the outside of the lower extension portion35a) of the primary upper extension portion37bto the lower extension portion35amay be shorter than the distance from the outer end thereof to the edge of the first lower semiconductor layer23aor the distance from the inner end thereof to the mesa isolation groove27a. With this structure, the light emitting diode can prevent current crowding at corners of the first light emitting cell C1or the second light emitting cell C2, thereby achieving uniform current spreading.

The secondary upper extension portion37adisposed on each of the first light emitting cell C1and the second light emitting cell C2connects the first electrode pad37to the primary upper extension portion37b. The secondary upper extension portion37amay have a linear shape and is connected at one end thereof to the first electrode pad37and at the other end thereof to the primary upper extension portion37b. A connection point at one end of the secondary upper extension portion37ais farther from the one edge21aof the substrate21than from the center of the first electrode pad37. In addition, a connection point at the other end of the secondary upper extension portion37amay be disposed inside the lower extension portion35aand may be closer to the one edge21aof the substrate than the distal end of the lower extension portion35a.

The primary upper extension portion37ddisposed on each of the third light emitting cell D1and the fourth light emitting cell D2surrounds a distal end of the lower extension portion35band a portion of a side surface thereof. Herein, the inside of the lower extension portion35bmeans a side of the lower extension portion35bthat is closer to the mesa isolation groove27a, and the outside of the lower extension portion35bmeans the other side of the lower extension portion35b. In this structure, a portion of the primary upper extension portion37dis disposed outside the lower extension portion35b, another portion thereof is disposed inside the lower extension portion35b, and a third portion thereof is disposed between the distal end of the lower extension portion35band the isolation groove30a. In addition, the primary upper extension portion37dhas two ends, that is, an inner end and an outer end, which are placed inside and outside the lower extension portion35b, respectively.

The primary upper extension portion37dextends from the isolation groove30ato the other edge21bof the substrate21, at which the second electrode pad35is disposed. As shown inFIG.1, the distance between the primary upper extension portion37dand the lower extension portion35bmay be variable. For example, the distance between the primary upper extension portion37dand the lower extension portion35bmay increase and then decrease along an imaginary line extending from the primary upper extension portion37d.

Although the primary upper extension portion37dmay generally have a symmetrical structure with respect to the linear region of the lower extension portion35b, the outer end of the lower extension portion35bis disposed closer to the other edge21bof the substrate21than the inner end of the primary upper extension portion37d. That is, as shown inFIG.1, a region of the primary upper extension portion37ddisposed outside the lower extension portion35bis longer than a region thereof disposed inside the lower extension portion35band may be curved along the curved region of the lower extension portion35b.

The distance between the distal end of the lower extension portion35aor35band the primary upper extension portion37bor37dsurrounding the distal end of the lower extension portion35aor35bmay be variable. That is, the upper extension portion37bor37dsurrounding the distal end of the lower extension portion35aor35bmay have a semi-circular shape having a variable radius. Referring toFIG.1, a diagonal distance d2between the distal end of the lower extension portion35aor35band the primary upper extension portion37bor37dmay be greater than a horizontal distance d1there in between. Here, the horizontal distance d1means a distance from the distal end of the lower extension portion35aor35bto the primary upper extension portion37bor37din a horizontal direction that is parallel to the substrate21. In addition, the diagonal distance d2means a distance from the distal end of the lower extension portion35aor35bto the primary upper extension portion37bor37din a slanted direction with respect to the horizontal direction. With the structure wherein the diagonal distance d2is greater than the horizontal distance d1, the primary upper extension portions37b,37dmay be disposed closer to upper corners of the light emitting cells, respectively. With the structure wherein the primary upper extension portions37b,37dare disposed closer to the upper corners of the light emitting cells, the light emitting diode allows efficient current spreading to the upper corners of the light emitting cells.

The secondary upper extension portion37cdisposed on each of the third light emitting cell D1and the fourth light emitting cell D2may extend from each of the primary upper extension portion37dtowards each of the lower extension portion35aon the first or second light emitting cell C1or C2. The secondary upper extension portion37cmay have a linear shape and may be collinear with the lower extension portion35a. The secondary upper extension portion37cis connected at one end thereof to the primary upper extension portion37dand at the other end thereof to the connecting portion35c.

Referring toFIG.1andFIG.4, each of the connecting portions35cconnects the secondary upper extension portion37cto the lower extension portion35a. That is, the lower extension portion35aon the first light emitting cell C1is connected to the secondary upper extension portion37con the third light emitting cell D1through the connecting portion35c, and the lower extension portion35aon the second light emitting cell C2is connected to the secondary upper extension portion37con the fourth light emitting cell D2through another connecting portion35c. Accordingly, the first light emitting cell C1may be connected in series to the third light emitting cell D1and the second light emitting cell C2may be connected in series to the fourth light emitting cell D2. Meanwhile, the first and third light emitting cells C1, D1are connected in parallel to the second and fourth light emitting cells C2, D2. The connecting portions35care separated from the third and fourth light emitting cells D1, D2by the insulating layer32a.

The first electrode pad37, the second electrode pad35, the upper extension portions37a,37b,37c,37d, the lower extension portions35a,35band the connecting portions35cmay be formed together using the same material by the same process, and may have a multilayer structure of, for example, Cr/Al/Cr/Ni/Au. However, it should be understood that other implementations are also possible and these components may be formed of different materials by different processes.

Meanwhile, the upper extension portions37a,37b,37c,37d, the lower extension portions35a,35band the connecting portions35cmay have symmetrical structures with respect to an imaginary line passing through the first electrode pad37and the second electrode pad35. In addition, the light emitting diode according to this exemplary embodiment may have a symmetrical structure with respect to the imaginary line passing through the first electrode pad37and the second electrode pad35. With this structure, the light emitting diode can achieve uniform current spreading.

Referring again toFIG.1toFIG.4, the current blocking layer31amay be disposed under the first electrode pad37and may be referred to as a third current blocking layer31a. In addition, the current blocking layer31dmay be disposed under the upper extension portions37a,37b,37c,37dand may be referred to as a fourth current blocking layer31d. The fourth current blocking layer31dis disposed between the transparent electrode layer33and the upper semiconductor layer27of each of the light emitting cells C1, C2, D1, D2under each of the upper extension portions37a,37b,37c,37d. Furthermore, the fourth current blocking layer31dmay be connected to the insulating layer32adisposed under the connecting portion35c.

The third and fourth current blocking layers31a,31dmay be formed of an insulating material and may be composed of a single layer or multiple layers. For example, the third and fourth current blocking layers31aand31dmay include SiOxor SiNx, and may include a distributed Bragg reflector (DBR) in which insulating material layers having different indices of refraction are stacked one above another. The fourth current blocking layer31dprevents current from directly flowing from the upper extension portions37a,37b,37c,37dto the light emitting cells C1, C2, D1, D2, thereby allowing current spreading over a wide area of the light emitting cells C1, C2, D1, D2. The fourth current blocking layer31dmay have a greater line width than the upper extension portions37a,37b,37c,37d. If the fourth current blocking layer31dis too large, the fourth current blocking layer31dcan cause light loss through absorption of light emitted from the light emitting cells, accordingly, preferably, the line width of the fourth current blocking layer31dis less than three times the line width of the upper extension portions37a,37b,37c,37d.

In addition, referring toFIG.3, the third current blocking layer31adisposed under the first electrode pad37to insulate the first electrode pad37from the first lower semiconductor layer23a. Furthermore, the third current blocking layer31amay also be interposed between the first electrode pad37and each of the first and second light emitting cells C1, C2. In this structure, the third current blocking layer31amay be interposed between the transparent electrode layer33and the upper semiconductor layer27.

FIG.5is an enlarged plan view of the first electrode pad37ofFIG.1andFIG.6is a cross-sectional view taken along line D-D ofFIG.5.

Referring toFIG.5andFIG.6, the third current blocking layer31ahaving a larger area than the first electrode pad37is disposed under the first electrode pad37. The first electrode pad37is placed only on the third current blocking layer31a. The first electrode pad37is disposed on the mesa isolation groove27ato straddle the first light emitting cell C1and the second light emitting cell C2. In this structure, the third current blocking layer31ainsulates the first electrode pad37and the first lower semiconductor layer23afrom each other on the mesa isolation groove27a. In addition, the third current blocking layer31ais interposed between the transparent electrode layer33and the upper semiconductor layer27on each of the first and second light emitting cells C1, C2. A part of the transparent electrode layer33is disposed under the first electrode pad37. Thus, the first electrode pad37is electrically connected to the upper semiconductor layer27through the transparent electrode layer33. The transparent electrode layer33has an opening33awhich exposes the third current blocking layer31a. The openings33aformed in the transparent electrode layer33on the first light emitting cell C1and the second light emitting cell C2may be symmetrical to each other with respect to the mesa isolation groove27a.

The opening33amay have a partial doughnut shape. Specifically, the opening33amay include a concave sidewall, a convex sidewall, and a flat sidewall connecting the concave sidewall to the convex sidewall. With the structure wherein the opening33ais formed in the transparent electrode layer33, adhesion of the first electrode pad37can be improved. Although the opening33ais formed in the transparent electrode layer33in this exemplary embodiment, the opening33amay be formed in the third current blocking layer31aso as to expose the upper semiconductor layer27.

FIG.7is an enlarged plan view of the second electrode pad35ofFIG.1andFIG.8is a cross-sectional view taken along line E-E ofFIG.7.

Referring toFIG.7andFIG.8, the second electrode pad35is disposed in the mesa isolation groove27ato be electrically connected to the second lower semiconductor layer23b, as described above. The third light emitting cell D1and the fourth light emitting cell D2are disposed near the second electrode pad35.

The insulating layer32bcovers side surfaces of the third light emitting cell D1and the fourth light emitting cell D2. As shown inFIG.7andFIG.8, the insulating layer32bcovers the side surfaces of the third and fourth light emitting cells D1, D2excluding a portion thereof through which the lower extension portion35bpasses. The insulating layer32bcan prevent a bonding material from contacting the upper semiconductor layer27of the third light emitting cell D1or the fourth light emitting cell D2and causing short circuit upon bonding of a wire to the second electrode pad35.

The insulating layer32bmay be separated from the transparent electrode layer33and thus may be formed to have a relatively very small area. As a result, it is possible to reduce light loss caused by the insulating layer32b.

The light emitting diode according to the exemplary embodiment can be operated at a relatively high voltage using the light emitting cells connected to each other in series. As a result, the light emitting diode according to the exemplary embodiment can reduce overall driving current. Furthermore, the light emitting diode according to the exemplary embodiment can achieve uniform current spreading using the light emitting cells connected to each other in parallel, and the lower extension portions and the upper extension portions. Furthermore, the light emitting diode according to the exemplary embodiment can be packaged by a typical packaging process, and a wavelength conversion layer containing phosphors may be disposed on the light emitting diode. As a result it is possible to provide a light emitting device that emits white light.

FIG.9is a plan view of a light emitting diode according to another exemplary embodiment of the present disclosure,FIG.10is a cross-sectional view taken along line F-F ofFIG.9,FIG.11is a cross-sectional view taken along line G-G ofFIG.9, andFIG.12is a cross-sectional view taken along line H-H ofFIG.9.FIG.13Ais an enlarged plan view of one exemplary embodiment of a connecting portion ofFIG.9andFIG.13Bis a cross-sectional view taken along line I-I ofFIG.13A.FIG.14Ais an enlarged plan view of another exemplary embodiment of the connecting portion ofFIG.9andFIG.14Bis a cross-sectional view taken along line I′-I′ ofFIG.14A. The light emitting diode according to this exemplary embodiment is substantially the same as the light emitting diode shown inFIG.1toFIG.8and further includes a first current blocking layer31cdisposed under each of the lower extension portions35a,35band a second current blocking layer31bdisposed under the second electrode pad35. Hereinafter, the following description will focus on different features of the light emitting diode according to this exemplary embodiment and detailed descriptions of the same components will be omitted.

Referring toFIG.9,FIG.10andFIG.12, the first current blocking layer31cmay be disposed under each of the lower extension portions35a,35b. As shown therein, the first current blocking layer31cdisposed under each of the lower extension portions35a,35bmay include a plurality of dots separated from one another instead of having a single continuous line shape. That is, as shown inFIG.9, the first current blocking layer31cmay include a plurality of dots separated from one another. Each of the dots is disposed between the lower extension portion35aor35band the lower semiconductor layer23aor23b. In this exemplary embodiment, the first current blocking layer31c, that is, each of the dots, has a greater width than the lower extension portions35a,35b. Accordingly, the lower extension portion35aor35bdoes not directly contact the lower semiconductor layer23aor23bin regions between which the first current blocking layer31cis interposed, and contacts the lower semiconductor layer23aor23bin a region between the dots. In addition, the dots may be arranged at regular intervals or at different intervals.

The first current blocking layer31cmay be disposed between the lower extension portion35aor35band the lower semiconductor layer23aor23bto assist in horizontal current spreading by preventing electric current crowding near the lower extension portions35a,35b. With the structure wherein electric current broadly spreads in the horizontal direction in a semiconductor stack, the light emitting diode can have improved luminous efficacy. Particularly, the first current blocking layer31cmay be formed to have a greater line width than the lower extension portions35a,35bsuch that the lower extension portion35aor35bcan be prevented from directly contacting the lower semiconductor layer23aor23bin the regions between which the first current blocking layer31cis interposed. In this exemplary embodiment, the first current blocking layer31cis formed to have a greater line width than the lower extension portions35a,35band includes the plurality of dots, thereby further improving current spreading, as compared with the structure wherein the first current blocking layer31chas a smaller line width than the lower extension portions35a,35b.

In this exemplary embodiment, the first current blocking layer31cis not disposed at a distal end of each of the lower extension portions35a,35b. That is, the distal end of each of the lower extension portions35a,35bmay be directly connected to the lower semiconductor layer23aor23b. As used herein, direct connection means that each of the lower extension portions35a,35bis connected at the distal end thereof to the lower semiconductor layer23aor23bwithout a material (for example, current blocking layer) interposed there in between. Referring toFIG.9, each of the upper extension portions37b,37dhas a structure surrounding the distal end of the lower extension portion35aor35b. If the first current blocking layer31cis disposed at the distal end of each of the lower extension portions35a,35b, the lower extension portion35aor35bcannot be directly electrically connected at the distal end thereof to the lower semiconductor layer23aor23b, thereby causing inefficient current spreading near the distal end of each of the lower extension portions35a,35b.

For the first current blocking layer31c, the number of dots may be determined in various ways depending upon relative lengths of the lower extension portions35a,35b. For example, referring toFIG.9, the first current blocking layers31cincludes five dots separated from one another between the lower extension portion35aand the first lower semiconductor layer23a. In addition, the first current blocking layer31cincludes six dots separated from one another between the lower extension portion35band the second lower semiconductor layer23b. This is because the lower extension portion35bon each of the third and fourth light emitting cells D1, D2includes a curved region to be connected to the second electrode pad35and thus has a greater length than the lower extension portion35bon each of the first and second light emitting cells C1, C2. For the first current blocking layer31c, the distances between the plural dots may be the same or different. It should be understood that the number of dots for the first current blocking layer31cis given by way of exemplary illustration only inFIG.9and does not limit other exemplary embodiments of the present disclosure.

Further, the second current blocking layer31bmay be disposed under the second electrode pad35. The second current blocking layer31bis disposed between the second electrode pad35and the second lower semiconductor layer23bto allow efficient horizontal spreading of electric current injected into the second lower semiconductor layer23b. The second current blocking layer31bmay have a smaller area than the second electrode pad35. That is, the second current blocking layer31bmay have smaller widths in the horizontal and vertical directions thereof than the second electrode pad35and thus may be restrictively disposed under some region of the second electrode pad35. For example, the area of the second current blocking layer31bmay be restricted to 90% or less the area of the second electrode pad35. If the area of the second current blocking layer31bexceeds 90% the area of the second electrode pad35, there is a problem of increase in forward voltage Vf. Thus, with the structure wherein the area of the second current blocking layer31bis set to be 90% or less compare to the area of the second electrode pad35, the light emitting diode can achieve high luminous efficacy without increase in forward voltage. As in the third and fourth current blocking layers31aand31d, the first and second current blocking layer31c,31bmay be formed of an insulating material and may be composed of a single layer or multiple layers. For example, the second current blocking layer31bmay include SiOxor SiNx, and may include a distributed Bragg reflector (DBR) in which insulating material layers having different indices of refraction are stacked one above another.

FIG.13Ais an enlarged plan view of one exemplary embodiment of a connecting portion ofFIG.9andFIG.13Bis a cross-sectional view taken along line I-I ofFIG.13A.

The connecting portion35celectrically connects two light emitting cells C1, D1that are isolated from each other by the isolation groove30a, and is connected at one end thereof to the lower extension portion35aon the first light emitting cell C1and at the other end thereof to the secondary upper extension portion37con the third light emitting cell D1. Referring toFIG.13A, a width w1of the connecting portion35cmay be greater than a width w2of the lower extension portion35a. In addition, the first current blocking layer31cmay not be disposed under the connecting portion35cand the portion of the lower extension portion35athat is connected to connecting portion35con the first light emitting cell C1, so that the connecting portion35cand the portion of the lower extension portion35athat is connected to the connecting portion35cmay directly contact the lower semiconductor layer23a. As such, with the structure wherein the connecting portion35chaving a relatively large width w1and the portion of the lower extension portion35athat is connected to the connecting portion35cdirectly contact the lower semiconductor layer23a, the light emitting diode allows efficient horizontal current spreading along an outer periphery of the first light emitting cell C1, in which the primary upper extension portion37bis not formed. In addition, the connecting portion35cis formed to have a relatively large width w1to reduce a risk of disconnection of the connecting portion35c, thereby improving reliability of the light emitting diode.

Referring toFIG.13AandFIG.13B, the first current blocking layer31cmay be disposed in the form of plural dots between the lower extension portion35aand the lower semiconductor layer23a. The first current blocking layer31cmay have a greater width than the lower extension portion35a, whereby the lower extension portion35acan directly contact the lower semiconductor layer23aonly between the dots of the first current blocking layer31c. That is, a contact distance between the lower extension portion35aand the lower semiconductor layer23amay be determined depending upon a separation distance d1between the dots.

Between the first current blocking layer31cand the isolation groove30a, that is, between the last dot of the first current blocking layer31cand the isolation groove30a, a contact distance d2may be greater than the separation distance d1between the dots of the first current blocking layer31c. That is, between the last dot of the first current blocking layer31cand the isolation groove30a, a contact area in which the connecting portion35cand the lower extension portion35athat is connected to the connecting portion35ccontact the lower semiconductor layer23amay be larger than a contact area in which the lower extension portion35acontacts the lower semiconductor layer23abetween the respective dots, thereby reducing resistance. With this structure, the light emitting diode can achieve efficient current spreading to the outer periphery of the first light emitting cell C1, C2. That is, the upper extension portion37bmay not be formed at the outer periphery of the first and second light emitting cell C1, C2, thereby providing a relatively large distance d3between the distal end of upper extension portion37band the connecting portion35c. In this structure, electric current often fails to reach of the outer periphery of the first light emitting cell C1, C2. Thus, the contact area, between the last dot of the first current blocking layer31cand the isolation groove30a, in which the connecting portion35cand the lower extension portion35athat is connected to the connecting portion35ccontact the lower semiconductor layer23acan be increased by increasing the separation distance d2to reduce resistance, thereby allowing efficient dispersion of electric current to the outer periphery of the first light emitting cell C1.

Referring toFIG.13B, the insulating layer32adisposed under the connecting portion35cmay extend from a portion of the side surface of the lower semiconductor layer23aof the first light emitting cell C1to side surfaces of the lower semiconductor layer23b, the active layer25and the upper semiconductor layer27of the third light emitting cell D1and to an upper surface of the upper semiconductor layer27thereof.

FIG.14Ais an enlarged plan view of another exemplary embodiment of the connecting portion35cofFIG.9andFIG.14Bis a cross-sectional view taken along line I′-I′ ofFIG.14A. The connecting portion35cshown inFIG.14AandFIG.14Bis substantially the same as the connecting portion shown inFIG.13AandFIG.13Bexcept for the shapes of the insulating layer32aand the upper extension portion37b. As a result, a contact area between the connecting portion35cand the lower semiconductor layer23acan be changed. The following description will focus on different features of the connecting portion according to this exemplary embodiment and descriptions of the same components will be omitted.

Referring toFIG.14AandFIG.14B, the insulating layer32afurther extends towards the first light emitting cell C1to cover the side surface and a portion of an upper surface of the lower semiconductor layer23aof the first light emitting cell C1, as compared with the exemplary embodiment ofFIG.13AandFIG.13B. In this structure, between the first current blocking layer31cand the isolation groove30a, a contact distance d4of the lower extension portion35aand the connecting portion35cbetween the last dot of the first current blocking layer31cand end of the insulating layer32awhich is on the first light emitting cell C1can be reduced, as compared with the exemplary embodiment ofFIG.13. That is, as compared with the exemplary embodiment ofFIG.13AandFIG.13B, between the first current blocking layer31cand the isolation groove30a, the contact area, between the last dot of the first current blocking layer31cand end of the insulating layer32awhich is on the first light emitting cell C1, on which the connecting portion35cand the lower extension portion35athat is connected to the connecting portion35ccontact the lower semiconductor layer23acan be reduced, thereby increasing current density. In this exemplary embodiment, the contact distance d4may still be longer than the separation distance d1between the dots of the first current blocking layer31c. Alternatively, the contact distance d4may be shorter than the separation distance d1between the dots of the first current blocking layer31c.

Referring toFIG.14A, a distance d5from the distal end of the upper extension portion37bto the connecting portion35ccan be reduced, as compared with the exemplary embodiment ofFIG.13A. That is, the upper extension portion37bfurther extends towards the connecting portion35csuch that the distance d5between the distal end of the upper extension portion37band the connecting portion35ccan be reduced, as compared with the exemplary embodiment ofFIG.13A. In the exemplary embodiment ofFIG.14AandFIG.14B, between the first current blocking layer31cand the isolation groove30a, the distance d5between the distal end of the upper extension portion37band the connecting portion35chaving a relatively large width w1is reduced corresponding to reduction in contact area in which the connecting portion35cand the lower extension portion35aconnected to the connecting portion35ccontact the lower semiconductor layer23a, in order to achieve efficient horizontal current spreading to the outer periphery of the first light emitting cell C1.

FIG.15toFIG.17are plan views of light emitting diodes according to other exemplary embodiments of the present disclosure. The light emitting diode shown inFIG.15toFIG.17is similar to the light emitting diode shown inFIG.9excluding structures of a first electrode pad37, a second electrode pad35, upper extension portions and lower extension portions, and the number of light emitting cells. Thus, the following description will focus on different features of this exemplary embodiment and descriptions of the same components will be omitted.

FIG.15is a plan view of a light emitting diode according to a further exemplary embodiment of the present disclosure.

Referring toFIG.15, the light emitting diode according to this exemplary embodiment includes first to third light emitting cells C1, C2, C3, fourth to sixth light emitting cells D1, D2, D3, and seventh to ninth light emitting cells E1, E2, E3disposed on a substrate21. The light emitting diode further includes a first electrode pad37, a second electrode pad35, upper extension portions37a,37b,37c,37d,37e,37f, and lower extension portions35a,35b,35d,35e.

The first to third light emitting cells C1, C2, C3may be isolated from the fourth to sixth light emitting cells D1, D2, D3by an isolation groove30a, respectively. In addition, the fourth to sixth light emitting cells D1, D2, D3are isolated from the seventh to ninth light emitting cells E1, E2, E3by an isolation groove30b, respectively. That is, a first lower semiconductor layer23amay be isolated from a second lower semiconductor layer23bby the isolation groove30a, and the second lower semiconductor layer23bmay be isolated from a third lower semiconductor layer23cby the isolation groove30b. Accordingly, the first light emitting cell C1, the second light emitting cell C2and the third light emitting cell C3may share the first lower semiconductor layer23a, and the fourth light emitting cell D1, the fifth light emitting cell D2and the sixth light emitting cell D3may share the second lower semiconductor layer23b. In addition, the seventh light emitting cell E1, the eighth light emitting cell E2and the ninth light emitting cell E3may share the third lower semiconductor layer23c. The isolation grooves30a,30bmay be formed by an isolation process and the substrate21may be exposed through the isolation grooves30a,30b. The first light emitting cell C1, the fourth light emitting cell D1, and the seventh light emitting cell E1may be isolated from the second light emitting cell C2, the fifth light emitting cell D2, and the eighth light emitting cell E2, respectively, by a mesa etching process in which a mesa isolation groove27ais formed to expose the lower semiconductor layers23a,23b,23c. In addition, the second light emitting cell C2, the fifth light emitting cell D2, and the eighth light emitting cell E2may be isolated from the third light emitting cell C3, the sixth light emitting cell D3, and the ninth light emitting cell E3, respectively, by a mesa etching process in which a mesa isolation groove27bis formed to expose the lower semiconductor layers23a,23b,23c. That is, the semiconductor stack including the lower semiconductor layers23a,23b,23c, an active layer25and an upper semiconductor layer27are divided into the first to ninth light emitting cells C1, C2, C3, D1, D2, D3, E1, E2, E3by the mesa isolation grooves27a,27band the isolation grooves30a,30b.

The first light emitting cell C1may be symmetrical to the third light emitting cell C3with respect to an imaginary line connecting the first electrode pad37to the second electrode pad35. The fourth to sixth light emitting cells D1, D2, D3may have the same shape. The fourth to sixth light emitting cells D1, D2, D3may have the same shape as the first light emitting cell C1excluding a secondary upper extension portion37a. In addition, the seventh light emitting cell E1may be symmetrical to the ninth light emitting cell E3with respect to an imaginary line connecting the first electrode pad37to the second electrode pad35.

In this exemplary embodiment, the second light emitting cell C2on which the first electrode pad37is formed and the eighth light emitting cell E2on which the second electrode pad35is formed have significantly different shapes than other light emitting cells. The first electrode pad37may be disposed near one edge21aof the substrate21and the second electrode pad35may be disposed near the other edge21bof the substrate21facing the one edge21athereof. As shown inFIG.15, the first electrode pad37and the second electrode pad35may be disposed to face each other.

The first electrode pad37may be formed on the second light emitting cell C2. A third current blocking layer31amay be disposed under the first electrode pad37. Specifically, the third current blocking layer31amay be interposed between the transparent electrode layer33and the upper semiconductor layer27under the first electrode pad37. The third current blocking layer31amay have a greater width than the first electrode pad37, whereby the third current blocking layer31acan insulate the first electrode pad37from the first lower semiconductor layer23a. A part of the transparent electrode layer33may be disposed under the first electrode pad37. The transparent electrode layer33may include an opening33awhich exposes the third current blocking layer31a. The opening33amay have a circular shape. With the structure wherein the opening33ais formed in the transparent electrode layer33, adhesion of the first electrode pad37can be improved. However, it should be understood that the opening33ais not limited to the circular shape and may have a variety of shapes so long as the opening can improve adhesion of the first electrode pad37.

The second electrode pad35may be disposed on a mesa groove27c. That is, for formation of the second electrode pad35, a lower end of the eighth light emitting cell E2near the other edge21bof the substrate21is partially removed by mesa etching to form the mesa groove27c. The second electrode pad35may be disposed in the mesa groove27cto be electrically connected to the third lower semiconductor layer23c.

A second current blocking layer31bmay be disposed under the second electrode pad35. The second current blocking layer31bis disposed between the second electrode pad35and the third lower semiconductor layer23cto allow efficient horizontal spreading of electric current injected into the third lower semiconductor layer23c. The second current blocking layer31bmay have a smaller area than the second electrode pad35. That is, the second current blocking layer31bmay have smaller widths in the horizontal and vertical directions thereof than the second electrode pad35and thus may be restrictively disposed under some region of the second electrode pad35. For example, the area of the second current blocking layer31bmay be restricted to 90% or less the area of the second electrode pad35.

The insulating layer32bcovers a side surface of the mesa groove27con which the second electrode pad35is disposed. As shown inFIG.15, the insulating layer32bmay also be formed at a portion through which the lower extension portion35bpasses while covering the side surface of the mesa groove27cto form an entirely closed curve. The insulating layer32bmay be first formed at the portion through which the lower extension portion35bpasses, and then the lower extension portion35bmay be formed thereon. Accordingly, the lower extension portion35bmay have a higher height at a portion thereof, on which the insulating layer32bis formed, than at other portions thereof. The insulating layer32bcan prevent a bonding material from contacting the upper semiconductor layer27of the eighth light emitting cell E2and causing short circuit upon bonding of a wire to the second electrode pad35.

The lower extension portions35ddisposed on the first, third, fourth, fifth, and sixth light emitting cells C1, C3, D1, D2, D3may include linear regions (in the vertical direction) and may be parallel to one another. Each of the lower extension portions35dmay be connected at one end thereof to the connecting portion35cand may have the other end separated from a primary upper extension portion37cand surrounded thereby. The lower extension portion35eis formed on the second light emitting cell C2, includes a linear region, and may have a shorter length than the lower extension portions35ddue to the first electrode pad37. As a result, the light emitting diode according to this exemplary embodiment may have a smaller number of first current blocking layers31cthan the light emitting diode according to the above exemplary embodiment. The lower extension portion35eformed on the second light emitting cell C2and the lower extension portion35bformed on the eighth light emitting cell E2may be placed on an imaginary line connecting the first electrode pad37to the second electrode pad35.

The lower extension portion35a(on both the seventh and ninth light emitting cells E1and E3) is connected to the second electrode pad35and includes two linear regions connected to each other. The two linear regions may be parallel to the horizontal and vertical directions of the substrate21, respectively, and may be orthogonal to each other. The linear region in the horizontal direction connects the linear region in the vertical direction to the second electrode pad35. As shown inFIG.15, in order to form the lower extension portion35a(particularly, the linear region in the horizontal direction), some regions of the seventh to ninth light emitting cells E1, E2, E3near the other edge21bof the substrate21may be removed by mesa etching.

The lower extension portion35bmay be formed on the eighth light emitting cell E2. The lower extension portion35bmay be connected at one end thereof to the second electrode pad35and may have the other end surrounded by a primary upper extension portion37e. The lower extension portion35bmay have a shorter length than the other lower extension portions35a,35ddue to the second electrode pad35, whereby the light emitting diode according to this exemplary embodiment may have a smaller number of first current blocking layers31cthan the light emitting diode according to the above exemplary embodiment.

The lower extension portions35a,35b,35d,35emay be parallel to one another and may pass through the centers of the corresponding light emitting cells. The first current blocking layers31cmay be disposed under each of the lower extension portions35a,35b,35d,35e. The primary upper extension portions37b,37c,37e,37fhave a structure surrounding the distal ends of the lower extension portions35e,35d,35b,35a, respectively. Accordingly, for the same reason as described in the exemplary embodiment ofFIG.1, the first current blocking layer31cmay not be disposed at the distal end of each of the lower extension portions35a,35b,35d,35e.

Meanwhile, the upper extension portions37a,37b,37c,37d,37e,37fmay be disposed on the transparent electrode layer33. The secondary upper extension portion37amay electrically connect the primary upper extension portions37b,37cto each other on the first to third light emitting cells C1, C2, C3. Specifically, the secondary upper extension portion37amay electrically connect the primary upper extension portions37b,37cof two light emitting cells adjacent to each other at the right and left sides of the secondary upper extension portion37a. The secondary upper extension portion37amay be formed to straddle the two light emitting cells adjacent to each other in the horizontal direction and may have a curved shape. For example, referring toFIG.15, the secondary upper extension portion37amay connect the primary upper extension portion37con the first light emitting cell C1to the primary upper extension portion37bon the second light emitting cell C2. As a result, the first light emitting cell C1may be electrically connected in parallel to the second light emitting cell C2.

Secondary upper extension portions37dmay connect the primary upper extension portions37c(on the fourth to sixth light emitting cells D1, D2, D3),37e,37fon the fourth to ninth light emitting cells D1, D2, D3, E1, E2, E3to the lower extension portions35d,35e. The secondary upper extension portion37dmay have a linear shape and may be coaxial with the lower extension portion35dor35e. Each of the secondary upper extension portions37dmay be connected at one end thereof to the primary upper extension portion37c,37eor37fand at the other end thereof to the connecting portion35c.

The primary upper extension portions37bmay extend from the first electrode pad37on the second light emitting cell C2. Specifically, the primary upper extension portions37bmay extend from one edge21aof the substrate towards the other edge21bthereof at which the second electrode pad35is disposed. Referring toFIG.15, two primary upper extension portions37bmay be formed symmetrical to each other with respect to an imaginary line connecting the first electrode pad37to the second electrode pad35. The primary upper extension portions37bmay have a curved shape, and thus, the primary upper extension portions37bare connected to the first electrode pad37so as to surround a distal end of the lower extension portion35eand a portion of the side surface thereof.

The primary upper extension portion37cmay be disposed on each of the first, third, fourth, fifth and sixth light emitting cells C1, C3, D1, D2, D3to surround a distal end of the lower extension portion35dand a portion of the side surface thereof. Accordingly, a portion of the primary upper extension portion37cmay be disposed at one side of the lower extension portion35dand another portion of the primary upper extension portion37cmay be disposed at the other side thereof facing the one side of the lower extension portion35d. The primary upper extension portion37cmay have a symmetrical structure with respect to an imaginary line extending from the lower extension portion35d.

The primary upper extension portion37fmay be disposed on each of the seventh light emitting cell E1and the ninth light emitting cell E3to surround a distal end of the lower extension portion35aand a portion of the side surface thereof. As described above, the lower extension portion35ahas a shape in which two linear regions in the horizontal and vertical directions are coupled to each other, and each of the primary upper extension portions37fmay be disposed to surround a distal end of the linear region of the lower extension portion35ain the vertical direction and a portion of the side surface thereof. A portion of the primary upper extension portion37fmay be disposed outside the lower extension portion35aand another portion of the primary upper extension portion37fmay be disposed inside the lower extension portion35a. Herein, the outside means a portion farther apart from the second electrode pad35with reference to the lower extension portion35a, and the inside means a portion disposed to face the outside and placed closer to the second electrode pad35. As shown inFIG.15, a portion of the primary upper extension portion37fdisposed inside the lower extension portion35amay have a shorter distance than a portion of the primary upper extension portion37fdisposed outside the lower extension portion35a. In this structure, a distal end of the primary upper extension portion37fdisposed inside the lower extension portion35ais separated a predetermined distance from a portion of the lower extension portion35adisposed therebelow, thereby preventing current crowding at the lower extension portion35a.

The primary upper extension portion37emay be disposed on the eighth light emitting cell E2to surround a distal end of the lower extension portion35band a portion of the side surface thereof. Although the primary upper extension portion37ehas a substantially similar shape to the primary upper extension portion37c, the primary upper extension portion37ehas a shorter length due to the second electrode pad35located at a lower end of the eighth light emitting cell E2.

InFIG.15, the first, fourth and seventh light emitting cells C1, D1, E1may define a first group, the second, fifth and eighth light emitting cells C2, D2, E2may define a second group, and the third, sixth and ninth light emitting cells C3, D3, E3may define a third group. In each of the groups, the light emitting cells may be electrically connected to one another in series through the secondary upper extension portions37dand the connecting portions35c(on the fourth to ninth light emitting cells D1, D2, D3, E1, E2, E3). In addition, the first group, the second group and the third group may be electrically connected to one another in parallel through the secondary upper extension portions37aand the linear region of the lower extension portion35ain the horizontal direction.

FIG.16is a plan view of a light emitting diode according to yet another exemplary embodiment of the present disclosure.

Referring toFIG.16, the light emitting diode according to this exemplary embodiment includes first to eighth light emitting cells C1, C2, D1, D2, E1, E2, F1, F2disposed on a substrate21. The light emitting diode further includes a first electrode pad37, a second electrode pad35, upper extension portions37a,37b,37c,37d, and lower extension portions35a,35b,35d.

The first and second light emitting cells C1, C2may be isolated from the third and fourth light emitting cells D1, D2by an isolation groove30a, and the third and fourth light emitting cells D1, D2may be isolated from the fifth and sixth light emitting cells E1, E2by an isolation groove30b. In addition, the fifth and sixth light emitting cells E1, E2may be isolated from the seventh and eighth light emitting cells F1, F2by an isolation groove30c. The isolation grooves30a,30b,30cmay be formed by an isolation process and may expose the substrate21there through. Meanwhile, the first light emitting cell C1, the third light emitting cell D1, the fifth light emitting cell E1, and the seventh light emitting cell F1may be isolated from the second light emitting cell C2, the fourth light emitting cell D2, the sixth light emitting cell E2, and the eighth light emitting cell F2, respectively, by a mesa etching process in which a mesa isolation groove27ais formed to expose the lower semiconductor layers23a,23b,23c,23d. In this structure, the first light emitting cell C1and the second light emitting cell C2may share a first lower semiconductor layer23a; the third light emitting cell D1and the fourth light emitting cell D2may share a second lower semiconductor layer23b; and the fifth light emitting cell E1and the sixth light emitting cell E2may share a third lower semiconductor layer23c; and the seventh light emitting cell F1and the eighth light emitting cell F2may share a fourth lower semiconductor layer23d. That is, the semiconductor stack including the lower semiconductor layers23a,23b,23c,23d, an active layer25and an upper semiconductor layer27is divided into the first to eighth light emitting cells C1, C2, D1, D2, E1, E2, F1, F2by the mesa isolation groove27aand the isolation grooves30a,30b,30c.

Other electrode portions are not disposed in the mesa isolation groove27aexcept for the first electrode pad37and the second electrode pad35, and the lower semiconductor layers23a,23b,23c,23dmay be exposed through the mesa isolation groove27a. With reference to an imaginary line connecting the mesa isolation groove27aor the first electrode pad37and the second electrode pad35, the first light emitting cell C1and the second light emitting cell C2, the third light emitting cell D1and the fourth light emitting cell D2, the fifth light emitting cell E1and the sixth light emitting cell E2, and the seventh light emitting cell F1and the eighth light emitting cell F2may have symmetrical structures, respectively. Thus, the following description will focus on the first, third, fifth and seventh light emitting cells C1, D1, E1, F1disposed at the left of the light emitting diode.

The first, third, fifth and seventh light emitting cells C1, D1, E1, F1may be electrically connected to one another in series. In addition, the second, fourth, sixth and eighth light emitting cells C2, D2, E2, F2may be electrically connected to one another in series. Furthermore, the first, third, fifth and seventh light emitting cells C1, D1, E1, F1may be electrically connected in parallel to the second, fourth, sixth and eighth light emitting cells C2, D2, E2, F2. With the structure wherein the plural light emitting cells are connected to one another in parallel, the light emitting diode can achieve uniform current spreading to each of the light emitting cells, thereby suppressing the droop phenomenon by reducing voltage increase during high current driving.

The first electrode pad37may be disposed near one edge21aof the substrate21and the second electrode pad35may be disposed near the other edge21bfacing the one edge21a. As shown inFIG.16, the first electrode pad37may be disposed to face the second electrode pad35. Furthermore, the first electrode pad37may be formed to straddle the first light emitting cell C1and the second light emitting cell C2.

The shape of the first electrode pad37ofFIG.16is similar to that of the first electrode pad ofFIG.1. A third current blocking layer31ahaving a larger area than the first electrode pad37may be disposed under the first electrode pad37. The first electrode pad37may be disposed only on the third current blocking layer31a. The first electrode pad37may be disposed on the mesa isolation groove27ato straddle the first light emitting cell C1and the second light emitting cell C2. Accordingly, the third current blocking layer31amay insulate the first electrode pad37from the first lower semiconductor layer23aon the mesa isolation groove27a. Further, the third current blocking layer31amay be interposed between the transparent electrode layer33and the upper semiconductor layer27on the first and second light emitting cells C1, C2. Meanwhile, a part of the transparent electrode layer33is disposed under the first electrode pad37. The transparent electrode layer33may include an opening33awhich exposes the third current blocking layer31a. The openings33aformed in transparent electrode layer33on the first light emitting cell C1and the second light emitting cell C2may be symmetrical to each other with respect to the mesa isolation groove27a.

The opening33amay have a semi-circular shape. With the structure wherein the opening33ais formed in the transparent electrode layer33, adhesion of the first electrode pad37can be improved. It should be understood that the opening33ais not limited to the semi-circular shape and may have any shape so long as the opening can improve adhesion of the first electrode pad37. Although the opening33ais formed in the transparent electrode layer33in this exemplary embodiment, the opening33amay be through the third current blocking layer31aso as to expose the upper semiconductor layer27.

The second electrode pad35may be disposed in the mesa isolation groove27anear the other edge21bof the substrate21to be electrically connected to the fourth lower semiconductor layer23d. Meanwhile, the seventh light emitting cell F1and the eighth light emitting cell F2may be disposed near the second electrode pad35. The second current blocking layer31bmay be disposed under the second electrode pad35. The second current blocking layer31bmay be disposed between the second electrode pad35and the fourth lower semiconductor layer23dto allow efficient horizontal spreading of electric current injected into the fourth lower semiconductor layer23d. The second current blocking layer31bmay have a smaller area than the second electrode pad35. That is, the second current blocking layer31bmay have smaller widths in the horizontal and vertical directions thereof than the second electrode pad35and thus may be restrictively disposed under some region of the second electrode pad35. For example, the area of the second current blocking layer31bmay be restricted to 90% or less the area of the second electrode pad35.

The insulating layer32bmay cover side surfaces of the seventh light emitting cell F1and the eighth light emitting cell F2near the second electrode pad35. Referring toFIG.16, the insulating layer32bmay also be formed at a portion through which the lower extension portion35apasses while covering the side surfaces of the seventh light emitting cell F1and the eighth light emitting cell F2to form an entirely closed curve. The insulating layer32bmay be first formed at the portion through which the lower extension portion35apasses, and then the lower extension portion35amay be formed thereon. Accordingly, the lower extension portion35amay have a higher height at a portion thereof, on which the insulating layer32bis formed, than at other portions thereof. The insulating layer32bcan prevent a bonding material from contacting the upper semiconductor layer27of the seventh light emitting cell F1or the eighth light emitting cell F2and causing short circuit upon bonding of a wire to the second electrode pad35. The insulating layer32bmay be separated from the transparent electrode layer33and thus may be formed to have a relatively very small area. With this structure, the light emitting diode can reduce light loss caused by the insulating layer32b.

The lower semiconductor layers23a,23b,23c,23dmay be exposed through the upper semiconductor layer27and the active layer25of each of the light emitting cells, and the lower extension portions35a,35b,35dmay be disposed on exposed regions of the lower semiconductor layers23a,23b,23c,23d. The lower extension portions35a,35b,35dmay be electrically connected to the lower semiconductor layers23a,23b,23c,23d.

Each of the lower extension portions35b,35ddisposed on the first to sixth light emitting cells C1, C2, D1, D2, E1, E2may include two linear regions (in the horizontal and vertical directions) and a curved region connecting the two linear regions to each other. The lower extension portion35bformed on each of the first and fifth light emitting cells C1, E1may be in mirror symmetry to the lower extension portion35dformed on the third light emitting cell D1. Each of the lower extension portions35b,35dis connected at one end thereof to the connecting portion35cto be electrically connected to a primary upper extension portion37cor37dof two light emitting cells adjacent to each other in the vertical direction, and has the other end surrounded by a curved region of the primary upper extension portion37b,37cor37d, which is formed near the center thereof. For example, one end of the lower extension portion35bformed on the first light emitting cell C1may be connected to a secondary upper extension portion37aof the third light emitting cell D1through the connecting portion35c. With this structure, the first light emitting cell C1can be electrically connected in series to the third light emitting cell D1.

In addition, referring toFIG.16, on the first light emitting cell C1, the lower extension portion35bmay vertically extend from a left lower end of the first light emitting cell C1rather than from the center thereof and then may be bent towards the right side. On the third light emitting cell D1, the lower extension portion35dmay vertically extend from a right lower end of the third light emitting cell D1and then may be bent towards the left side. Further, on the fifth light emitting cell E1, the lower extension portion35bmay vertically extend from a left lower end of the fifth light emitting cell E1and then may be bent towards the right side. That is, unlike the exemplary light emitting diodes ofFIG.9andFIG.15, the light emitting diode according to this exemplary embodiment may include the lower extension portions35b,35d, each of which extends from the left or right side of the lower end of the light emitting cell rather than from the center thereof.

The lower extension portion35amay be formed on the seventh and eighth light emitting cell F1, F2and may be connected to the second electrode pad35. The lower extension portion35amay include a linear region and a curved region. The curved region of the lower extension portion35amay connect the linear region thereof to the second electrode pad35. Unlike the exemplary light emitting diodes ofFIG.9andFIG.15, the linear region of the lower extension portion35amay be formed in the horizontal direction of the light emitting diode.

First current blocking layers31cmay be disposed under each of the lower extension portions35a,35b,35d. The first current blocking layers31cmay be separated from each other. The first current blocking layers31cmay be disposed between each of the lower extension portions35a,35b,35dand each of the lower semiconductor layers23a,23b,23c,23dto assist in horizontal spreading of electric current injected into the lower semiconductor layers23a,23b,23c,23d. Here, as in the exemplary embodiments ofFIG.9andFIG.15, the first current blocking layers31cmay not be disposed at the distal ends of the lower extension portions35a,35b,35d.

Meanwhile, the upper extension portions37a,37b,37c,37dmay be disposed on the transparent electrode layer33. A primary upper extension portion37bmay extend from the first electrode pad37towards a left side21cof the substrate21on the first light emitting cell C1in the horizontal direction. Referring toFIG.16, the primary upper extension portion37bmay include a round shape adjoining the first electrode pad37and two curved lines extending from the round shape in the horizontal direction. The primary upper extension portion37bincludes two distal ends and may be disposed to surround a distal end of the lower extension portion35band a portion of a side surface thereof. Thus, a region of the primary upper extension portion37bmay be disposed above the lower extension portion35band another region of the primary upper extension portion37bmay be disposed below the lower extension portion35b. Herein, a region above the lower extension portion35brefers to a region adjacent to one edge21aof the substrate21and a region below the lower extension portion35brefers to a region closer to the other edge21bfacing the one edge21aof the substrate21with reference to the lower extension portion35b. Although the primary upper extension portion37bmay have a substantially symmetrical structure with respect to the linear region of the lower extension portion35b, an upper end of the primary upper extension portion37bmay be closer to the left edge21cof the substrate21than a lower side thereof. That is, as shown inFIG.16, the region of the primary upper extension portion37bdisposed above the lower extension portion35bis larger than the region of the primary upper extension portion37bdisposed below the lower extension portion35band may be curved along the curved region of the lower extension portion35b.

A secondary upper extension portion37amay be formed at a left upper end or a right upper end of each of the third, fifth and seventh light emitting cells D1, E1, F1. The secondary upper extension portion37amay have a linear shape in the vertical direction. The secondary upper extension portion37amay be connected at one end thereof to the connecting portion35cand at the other end thereof to the primary upper extension portion37cor37d. For example, on the third light emitting cell D1, the secondary upper extension portion37amay be formed at the left upper end of the third light emitting cell D1and may be connected at one end thereof to the connecting portion35cto be electrically connected to the lower extension portion35bof the first light emitting cell C1. In addition, the other end of the secondary upper extension portion37amay be connected to the left upper end of the primary upper extension portion37cof the third light emitting cell D1. With this structure, the first light emitting cell C1may be electrically connected in series to the third light emitting cell D1and the third light emitting cell D1may also be electrically connected in series to the fifth light emitting cell E1.

A primary upper extension portion37cis formed on each of the third and seventh light emitting cells D1, F1and may extend from the left side21cof the substrate21towards the mesa isolation groove27ain the horizontal direction. The primary upper extension portion37chas a substantially similar shape to the primary upper extension portion37bformed on the first light emitting cell C1and may have a mirror symmetry structure thereto. There are differences in a contact area between the primary upper extension portion37band the first electrode pad37, and a contact area and contact location between the primary upper extension portion37cand the secondary upper extension portion37a. Referring toFIG.16, it can be seen that the contact area between the upper extension portion37band the first electrode pad37is larger than the contact area between the primary upper extension portion37cand the secondary upper extension portion37a. Also, the primary upper extension portion37cis disposed closer to the mesa isolation groove27a. A primary upper extension portion37dmay be formed on the fifth light emitting cell E1and may have a mirror symmetry structure with respect to the primary upper extension portion37c.

The upper extension portions and the lower extension portions on the second, fourth, sixth and eighth light emitting cells C2, D2, E2, F2may be symmetrical to the upper extension portions37a,37b,37c,37dand the lower extension portions35a,35b,35don the first, third, fifth and seventh light emitting cells C1, D1, E1, F1with reference to an imaginary line connecting the mesa isolation groove27aor the first electrode pad37to the second electrode pad35.

FIG.17is a plan view of a light emitting diode according to yet another exemplary embodiment of the present disclosure.

Referring toFIG.17, the light emitting diode according to this exemplary embodiment may include first to eighth light emitting cells C1, C2, D1, D2, E1, E2disposed on the substrate21. Further, the light emitting diode may include a first electrode pad37, a second electrode pad35, upper extension portions37a,37b,37c,37d,37e,37f,37g,37h, and lower extension portions35a,35b,35d,35e,35f,35g.

The light emitting cells C1, C2, D1, D2, E1, E2may be isolated from one another by isolation grooves30a,30b,30c. Specifically, the first and second light emitting cells C1, C2may be isolated from the third and fourth light emitting cells D1, D2by the isolation groove30a, and the third and fourth light emitting cells D1, D2may be isolated from the fifth and sixth light emitting cells E1, E2by the isolation groove30b. In addition, the first, third and fifth light emitting cells C1, D1, E1may be isolated from the second, fourth and sixth light emitting cells C2, D2, E2by the isolation groove30c. That is, the semiconductor stack including lower semiconductor layers23a,23b,23c, an active layer25and an upper semiconductor layer27is divided into the first to sixth light emitting cells C1, C2, D1, D2, E1, E2by the isolation grooves30a,30b,30c.

The isolation grooves30a,30bmay be formed by an isolation process and may expose the substrate21there through. Each of the light emitting cells has a rectangular shape, the longitudinal length of which is greater than the transverse length thereof. The first to sixth light emitting cells C1, C2, D1, D2, E1, E2may be electrically connected to one another in series. Referring toFIG.17, the first electrode pad37is formed at a right upper side on the second light emitting cell C2and the second electrode pad35is formed on a mesa groove27bformed at a left lower side of the fifth light emitting cell E1. That is, on the substrate21, the first electrode pad37and the second electrode pad35may be formed on a diagonal line. In addition, with reference to the isolation groove30c, the first light emitting cell C1may have a symmetrical structure with respect to the fourth light emitting cell D2, and the third light emitting cell D1may have a symmetrical structure with respect to the sixth light emitting cell E2.

Specifically, the first electrode pad37may be formed at the right upper side of the second light emitting cell C2. A third current blocking layer31amay be disposed under the first electrode pad37. Specifically, the third current blocking layer31amay be interposed between the transparent electrode layer33and the upper semiconductor layer27under the first electrode pad37. The third current blocking layer31ahas a greater width than the first electrode pad37and thus can insulate the first electrode pad37from the first lower semiconductor layer23a. A part of the transparent electrode layer33may be disposed under the first electrode pad37. The transparent electrode layer33may include an opening33awhich exposes the third current blocking layer31a. The opening33amay have a circular shape. With the structure wherein the opening33ais formed in the transparent electrode layer33, adhesion of the first electrode pad37can be improved. It should be understood that the opening33ais not limited to the circular shape and may have any shape so long as the opening can improve adhesion of the first electrode pad37.

The second electrode pad35may be disposed in the mesa groove27b. That is, in order to form the second electrode pad35, some region at the left lower side of the fifth light emitting cell E1is removed by mesa etching to form the mesa groove27b. The second electrode pad35may be disposed in the mesa groove27bto be electrically connected to a third lower semiconductor layer23c.

A second current blocking layer31bmay be disposed under the second electrode pad35. The second current blocking layer31bis disposed between the second electrode pad35and the third lower semiconductor layer23cto assist in efficient horizontal spreading of electric current injected into the third lower semiconductor layer23c. The second current blocking layer31bmay have a smaller area than the second electrode pad35. That is, the second current blocking layer31bmay have smaller widths in the horizontal and vertical directions thereof than the second electrode pad35and thus may be disposed in some region of the second electrode pad35. For example, the area of the second current blocking layer31bmay be restricted to 90% or less the area of the second electrode pad35.

The insulating layer32bmay cover a side surface of the mesa groove27b. As shown inFIG.17, the insulating layer32bmay also be formed at a portion through which the lower extension portion35apasses while covering the side surface of the mesa groove27bto have an entirely closed line shape. In addition, the insulating layer32bmay be first formed at the portion through which the lower extension portion35apasses, and then the lower extension portion35amay be formed thereon. Accordingly, the lower extension portion35amay have a higher height at a portion thereof, on which the insulating layer32bis formed, than at other portions thereof. The insulating layer32bcan prevent a bonding material from contacting the upper semiconductor layer27of the fifth light emitting cell E1and causing short circuit upon bonding of a wire to the second electrode pad35.

The lower semiconductor layers23a,23b,23cmay be exposed through the upper semiconductor layer27and the active layer25of each of the light emitting cells, and the lower extension portions35a,35b,35d,35e,35f,35gmay be disposed on exposed regions of the lower semiconductor layers23a,23b,23c. The lower extension portions35a,35b,35d,35e,35f,35gmay be electrically connected to the lower semiconductor layers23a,23b,23c.

The lower extension portion35gis formed on the second light emitting cell C2and has a linear shape. The lower extension portion35gmay be formed along a central line of the second light emitting cell C2. The lower extension portion35gmay be collinear with the linear region (horizontal direction) of the lower extension portion35fof the first light emitting cell C1. The lower extension portion35gmay be connected at one end thereof to the connecting portion35cto be electrically connected to a primary upper extension portion37cof the first light emitting cell C1. With this structure, the second light emitting cell C2may be electrically connected in series to the first light emitting cell C1. The other end of the lower extension portion35gmay be surrounded by the primary upper extension portion37b. In this exemplary embodiment, since the first electrode pad37is formed on the second light emitting cell C2, the lower extension portion35gmay have a relatively short length.

The lower extension portion35fis formed on the first light emitting cell C1and may include two linear regions (in the horizontal and vertical directions) and a curved region connecting the two linear regions to each other. The linear region of the lower extension portion35fin the vertical direction is disposed at a left lower side of the first light emitting cell C1, and may be connected at one end thereof to the connecting portion35cto be connected to a secondary upper extension portion37aof the third light emitting cell D1and at the other end thereof to the curved region thereof. With this structure, the first light emitting cell C1may be electrically connected in series to the third light emitting cell D1. In order to form the linear region of the lower extension portion35fin the vertical direction, some region at the left lower side of the first light emitting cell C1may be removed by mesa etching. In addition, the linear region of the lower extension portion35fin the horizontal direction may be formed along the central line of the first light emitting cell C1, and may be connected at one end thereof to the curved region thereof and may have the other end surrounded by a primary upper extension portion37c.

The lower extension portion35eis formed on the third light emitting cell D1and may include a linear shape. The lower extension portion35emay be formed along a central line of the third light emitting cell D1. The lower extension portion35emay be collinear with the linear region (horizontal direction) of the lower extension portion35dof the fourth light emitting cell D2. The lower extension portion35emay be connected at one end thereof to the connecting portion35cto be electrically connected to the secondary upper extension portion37hof the fourth light emitting cell D2. With this structure, the third light emitting cell D1may be electrically connected in series to the fourth light emitting cell D2. The other end of the lower extension portion35emay be surrounded by the primary upper extension portion37d.

The lower extension portion35dis formed on the fourth light emitting cell D2and may have a symmetrical structure to the lower extension portion35fformed on the first light emitting cell C1with reference to the isolation groove30c.

The lower extension portion35ais formed on the fifth light emitting cell E1and may include a curved region and a linear region. The curved region of the lower extension portion35amay be connected at one end thereof to the second electrode pad35and at the other end thereof to one end of the linear region of the lower extension portion35a. The other end of the linear region of the lower extension portion35amay be surrounded by a primary upper extension portion37g. In addition, the linear region of the lower extension portion35amay be formed at the center of the fifth light emitting cell E1.

The lower extension portion35bis formed on the sixth light emitting cell E2and may have a symmetrical structure to the lower extension portion35eformed on the third light emitting cell D1with reference to the isolation groove30c.

First current blocking layers31cmay be disposed under each of the lower extension portions35a,35b,35d,35e,35f,35g. The first current blocking layers31cmay be separated from each other. The first current blocking layers31cmay be disposed between each of the lower extension portions35a,35b,35d,35e,35f,35gand each of the lower semiconductor layers23a,23b,23cto assist in horizontal spreading of electric current injected into the lower semiconductor layers23a,23b,23c. Here, the first current blocking layers31cmay not be disposed at the distal ends of the lower extension portions35a,35b,35d,35e,35f,35g.

Meanwhile, the upper extension portions37a,37b,37c,37d,37e,37f,37g,37hmay be disposed on the transparent electrode layer33. A primary upper extension portion37bmay extend from the first electrode pad37towards the isolation groove30con the second light emitting cell C2. The primary upper extension portion37bmay be disposed to surround the distal end of the lower extension portion35gand a portion of a side surface thereof. Accordingly, a portion of the primary upper extension portion37bmay be disposed above the lower extension portion35g, another portion thereof may be disposed below the lower extension portion35g, and a third portion thereof may be disposed between the distal end of the lower extension portion35gand an edge21dof the substrate21. In addition, the primary upper extension portion37bhas two ends, which are disposed above and below the lower extension portion35g, respectively. Herein, a region above the lower extension portion35grefers to a region adjacent to one edge21aof the substrate21and a region below the lower extension portion35grefers to a region adjacent to the isolation groove30a. The distance between the primary upper extension portion37band the lower extension portion35gmay be variable. For example, the distance between the primary upper extension portion37band the lower extension portion35gmay increase and then decrease along an imaginary line extending from the primary upper extension portion37b.

The primary upper extension portion37cmay extend from the isolation groove30ctowards the left side21cof the substrate21on the first light emitting cell C1in the horizontal direction. The primary upper extension portion37cmay have a curved shape. The primary upper extension portion37cmay be disposed to surround a distal end of the lower extension portion35fand a portion of a side surface thereof (in the horizontal direction). Accordingly, a portion of the primary upper extension portion37cmay be disposed above the lower extension portion35f, another portion thereof may be disposed below the lower extension portion35f, and a third portion thereof may be disposed between the distal end of the lower extension portion35fand the isolation groove30c. In addition, the primary upper extension portion37chas two ends, which may be disposed above and below the lower extension portion35f, respectively. The primary upper extension portion37cmay have a symmetrical structure with reference to an imaginary line extending from the linear region of the lower extension portion35f.

The primary upper extension portion37cis formed on the first light emitting cell C1and is similar to a primary upper extension portion37fof the sixth light emitting cell E2excluding a region thereof to which the secondary upper extension portion37ais connected. In addition, primary upper extension portions37d,37eare formed on the third light emitting cell D1and the fourth light emitting cell D2, respectively, and may be substantially in mirror symmetry to the primary upper extension portion37cexcluding a region thereof to which the secondary upper extension portion37aor37his connected.

A primary upper extension portion37gmay extend from the isolation groove30ctowards the left side21cof the substrate21on the fifth light emitting cell E1in the horizontal direction. The primary upper extension portion37gmay be disposed to surround the distal end of the lower extension portion35aand a portion of a side surface thereof. Accordingly, a portion of the primary upper extension portion37gmay be disposed above the lower extension portion35a, another portion thereof may be disposed below the lower extension portion35a, and a third portion thereof may be disposed between the distal end of the lower extension portion35aand the isolation groove30c. The distance between the primary upper extension portion37gand the lower extension portion35amay be variable. For example, the distance between the primary upper extension portion37gand the lower extension portion35amay increase and then decrease along an imaginary line extending from the primary upper extension portion37g. Although the primary upper extension portion37gmay have a substantially symmetrical structure with respect to the linear region of the lower extension portion35a, an upper end of the lower extension portion35amay be disposed closer to the left side21cof the substrate21than a lower end thereof. That is, as shown inFIG.17, a region of the primary upper extension portion37gdisposed above the lower extension portion35ahas a greater length than a region of the primary upper extension portion37gdisposed below the lower extension portion35a, and the primary upper extension portion37gmay be curved along the curved region of the lower extension portion35a.

Meanwhile, the secondary upper extension portion37aformed on each of the third and sixth light emitting cells D1, E2may connect the lower extension portion to the primary upper extension portion between two light emitting cells adjacent to each other in the vertical direction. For example, the secondary upper extension portion37aformed on the third light emitting cell D1may be connected at one end thereof to the connecting portion35cto be electrically connected to the lower extension portion35fformed on the first light emitting cell C1. In addition, the other end of the secondary upper extension portion37aformed on the third light emitting cell D1may be connected to the primary upper extension portion37d. With this structure, the first light emitting cell C1may be electrically connected in series to the third light emitting cell D1. The secondary upper extension portion37aextends at an angle from one side of an upper end of the light emitting cell towards a right or left lower end thereof to be connected to the primary upper extension portion37dor37f.

Further, the secondary upper extension portion37hformed on each of the first, fourth and fifth light emitting cells C1, D2, E1may connect the lower extension portion to the primary upper extension portion between two light emitting cells adjacent to each other in the horizontal direction. For example, the secondary upper extension portion37hformed on the first light emitting cell C1may be connected at one end thereof to the connecting portion35cto be electrically connected to the lower extension portion35gformed on the second light emitting cell C2. In addition, the other end of the secondary upper extension portion37hformed on the first light emitting cell C1may be connected to the center of the primary upper extension portion37c. With this structure, the first light emitting cell C1may be electrically connected in series to the second light emitting cell C2. The secondary upper extension portion37hhave a linear shape and may be disposed collinear with the lower extension portion35b,35eor35g.

FIG.18A,FIG.18B, andFIG.18Care sectional views of the light emitting diodes according to the exemplary embodiments of the present disclosure, showing side surfaces thereof. Embodiments of a side surface of a substrate shown inFIG.18A,FIG.18B, andFIG.18Cmay be applied to side surfaces of the light emitting diodes shown inFIG.1,FIG.9andFIG.15toFIG.17.

Specifically, on the side surface of the light emitting diode shown inFIG.18A, a patterned substrate21is exposed and a semiconductor stack has steps formed thereon. The patterned substrate21is exposed through an isolation process and the steps are formed by mesa etching. That is, first, the patterned substrate21is exposed on the side surface of the light emitting diode through the isolation process, and a step is then formed on the lower semiconductor layer23bthrough mesa etching. The steps formed on the semiconductor stack can improve coupling force upon metal deposition.

On the side surface of the light emitting diode shown inFIG.18B, the patterned the substrate21is exposed and the semiconductor stack does not have a step, unlike the light emitting diode shown inFIG.18A. This structure is obtained by performing the isolation process subsequent to mesa etching, unlikeFIG.18A.

On the side surface of the light emitting diode shown inFIG.18C, the substrate21is not exposed and the semiconductor stack has steps formed thereon, unlikeFIG.18AandFIG.18B. This structure is obtained by mesa etching alone without performing the isolation process with respect to the side surface of the light emitting diode. Since the semiconductor stack, that is, a luminous area, is inevitably removed during the isolation process, the side surface of the light emitting diode shown inFIG.18Ccan secure as large a luminous area as possible by omitting the isolation process.

The light emitting diode according to the exemplary embodiments can be operated at a relatively high voltage using the light emitting cells connected to each other in series. As a result, the light emitting diode according to the exemplary embodiments can reduce overall driving current. Furthermore, the light emitting diode according to the exemplary embodiments can achieve uniform current spreading using the light emitting cells connected to each other in parallel, and the lower extension portions and the upper extension portions. Furthermore, the light emitting diode according to the exemplary embodiments can be packaged by a typical packaging process, and a wavelength conversion layer containing phosphors may be disposed on the light emitting diode. As a result, it is possible to provide a light emitting device emitting white light.

FIG.19is a top view of light emitting diodes according to exemplary embodiments of the present disclosure, showing a package mounting structure.FIG.19shows a package of the light emitting diode shown inFIG.9bonded to a lead frame through wire bonding. It should be understood that the light emitting diodes ofFIG.1andFIG.15toFIG.17may also be packaged instead of the light emitting diode shown inFIG.9.

Although certain exemplary embodiments have been described herein, it should be understood by those skilled in the art that these embodiments are given by way of illustration only, and that various modifications, variations, and alterations can be made without departing from the spirit and scope of the inventive concepts. Therefore, the scope of the inventive concepts should be limited only by the accompanying claims and equivalents thereof