Patent ID: 12261203

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The term “substantially” in the description, such as in “substantially flat” or in “substantially coplanar”, etc., will be understood by the person skilled in the art. In some embodiments the adjective substantially may be removed. Where applicable, the term “substantially” may also include embodiments with “entirely”, “completely”, “all”, etc. The term “substantially” may be varied in different technologies and be in the deviation range understood by the skilled in the art. For example, the term “substantially” may also relate to 90% of what is specified or higher, such as 95% of what is specified or higher, especially 99% of what is specified or higher, including 100% of what is specified, though the present invention is not limited thereto. Furthermore, terms such as “substantially parallel” or “substantially perpendicular” may be interpreted as not to exclude insignificant deviation from the specified arrangement and may include for example deviations of up to 10°. The word “substantially” does not exclude “completely” e.g. a composition which is “substantially free” from Y may be completely free from Y.

The term “about” may be varied in different technologies and be in the deviation range understood by the skilled in the art. The term “about” in conjunction with a specific distance or size is to be interpreted so as not to exclude insignificant deviation from the specified distance or size. For example, the term “about” may include deviations of up to 10% of what is specified, though the present invention is not limited thereto. The term “about” in relation to a numerical value x may mean x±5 or 10% of what is specified, though the present invention is not limited thereto.

Some embodiments of the disclosure are described. Additional operations can be provided before, during, and/or after the stages described in these embodiments. Some of the stages that are described can be replaced or eliminated for different embodiments. Additional features can be added to the semiconductor device structure. Some of the features described below can be replaced or eliminated for different embodiments. Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order.

The gate all around (GAA) transistor structures may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.

FIGS.1A-1Jare cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments.FIGS.1A-1to1D-1are perspective views of the semiconductor device structure ofFIGS.1A to1D, in accordance with some embodiments.

As shown inFIGS.1A and1A-1, a substrate110is provided, in accordance with some embodiments. The substrate110includes a lower portion112and a multilayer structure114, in accordance with some embodiments. The multilayer structure114is formed over the lower portion112, in accordance with some embodiments.

The lower portion112includes, for example, a semiconductor substrate. The semiconductor substrate includes, for example, a semiconductor wafer (such as a silicon wafer) or a portion of a semiconductor wafer. In some embodiments, the lower portion112is made of an elementary semiconductor material including silicon or germanium in a single crystal, polycrystal, or amorphous structure.

In some other embodiments, the lower portion112is made of a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, an alloy semiconductor, such as SiGe, or GaAsP, or a combination thereof. The lower portion112may also include multi-layer semiconductors, semiconductor on insulator (SOI) (such as silicon on insulator or germanium on insulator), or a combination thereof.

In some embodiments, the lower portion112is a device wafer that includes various device elements. In some embodiments, the various device elements are formed in and/or over the lower portion112. The device elements are not shown in figures for the purpose of simplicity and clarity. Examples of the various device elements include active devices, passive devices, other suitable elements, or a combination thereof. The active devices may include transistors or diodes (not shown). The passive devices include resistors, capacitors, or other suitable passive devices.

For example, the transistors may be metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high-voltage transistors, high-frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc. Various processes, such as front-end-of-line (FEOL) semiconductor fabrication processes, are performed to form the various device elements. The FEOL semiconductor fabrication processes may include deposition, etching, implantation, photolithography, annealing, planarization, one or more other applicable processes, or a combination thereof.

In some embodiments, isolation features (not shown) are formed in the lower portion112. The isolation features are used to define active regions and electrically isolate various device elements formed in and/or over the lower portion112in the active regions. In some embodiments, the isolation features include shallow trench isolation (STI) features, local oxidation of silicon (LOCOS) features, other suitable isolation features, or a combination thereof.

The multilayer structure114is also referred to a super lattice structure or a super lattice epitaxial growth structure, in accordance with some embodiments. The multilayer structure114includes sacrificial layers114a′, a thick sacrificial layer114a1, and channel layers114b′, in accordance with some embodiments. The thick sacrificial layer114a1is over the sacrificial layers114a′ and the channel layers114b′, in accordance with some embodiments.

The thick sacrificial layer114a1is thicker than the sacrificial layer114a′, in accordance with some embodiments. The thick sacrificial layer114a1is thicker than the channel layer114b′, in accordance with some embodiments. The thick sacrificial layer114a1and the sacrificial layer114a′ are used to reserve a space for a gate stack formed in the subsequent process, in accordance with some embodiments.

The sacrificial layers114a′ and the channel layers114b′ are alternately arranged as illustrated inFIG.1A, in accordance with some embodiments. It should be noted that, for the sake of simplicity,FIG.1Ashows three layers of the sacrificial layers114a′ and three layers of the channel layers114b′ for illustration, but does not limit the invention thereto. In some embodiments, the number of the sacrificial layers114a′ or the channel layers114b′ is between 2 and 10.

The sacrificial layers114a′ and the thick sacrificial layer114a1are made of a same first material, such as a first semiconductor material, in accordance with some embodiments. The channel layers114b′ are made of a second material, such as a second semiconductor material, in accordance with some embodiments.

The first material is different from the second material, in accordance with some embodiments. The first material has an etch selectivity with respect to the second material, in accordance with some embodiments. In some embodiments, the sacrificial layers114a′ and the thick sacrificial layer114a1are made of SiGe, and the channel layers114b′ are made of Si. The atomic percentage of Ge in the sacrificial layers114a′ or the thick sacrificial layer114a1ranges from about 5% to 40%, in accordance with some embodiments.

In some other embodiments, the sacrificial layers114a′ or the channel layers114b′ are made of other materials such as germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, an alloy semiconductor such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or combinations thereof.

The channel layers114b′ and the lower portion112are made of the same material such as Si, in accordance with some embodiments. The material of the sacrificial layers114a′ and the thick sacrificial layer114a1is different from the material of the lower portion112, in accordance with some embodiments. In some other embodiments, the sacrificial layers114a′, the thick sacrificial layer114a1, the channel layers114b′, and the lower portion112are made of different materials, in accordance with some embodiments.

The sacrificial layers114a′, the thick sacrificial layer114a1, and the channel layers114b′ are formed using an epitaxial growth process such as a molecular beam epitaxy (MBE) process, a metal-organic chemical vapor deposition (MOCVD) process, and/or another suitable epitaxial growth process. The epitaxial growth process is performed under about 350° C. to about 950° C. temperature and about 5 Torr to about 25 Torr pressure for about 10 seconds to about 40 seconds, in accordance with some embodiments.

As shown inFIGS.1A and1A-1, a mask layer120is formed over the multilayer structure114, in accordance with some embodiments. The mask layer120is made of an oxide material such as silicon dioxide (SiO2), a nitride material such as silicon nitride (Si3N4), or another suitable material, which is different from the materials of the substrate110(or the multilayer structure114), in accordance with some embodiments. The mask layer120is formed using a deposition process (e.g., a physical vapor deposition process or a chemical vapor deposition process), in accordance with some embodiments.

As shown inFIGS.1B and1B-1, portions of the mask layer120are removed to form trenches122in the mask layer120, in accordance with some embodiments. The trenches122pass through the mask layer120, in accordance with some embodiments. The removal process includes a photolithography process and an etching process (e.g., a dry etching process), in accordance with some embodiments.

As shown inFIGS.1B and1B-1, portions of the substrate110exposed by the trenches122are removed through the trenches122, in accordance with some embodiments. The removal process forms trenches111in the substrate110, in accordance with some embodiments.

After the removal process, the remaining portion of the substrate110includes a base113and fin structures116, in accordance with some embodiments. The fin structures116are over the base113, in accordance with some embodiments. The base113is formed from the lower portion112(as shown inFIG.1A), in accordance with some embodiments.

Each fin structure116includes a bottom portion115and a portion of the multilayer structure114, in accordance with some embodiments. The portion of the multilayer structure114includes portions of the sacrificial layers114a′, the thick sacrificial layer114a1, and the channel layers114b′, in accordance with some embodiments.

The bottom portion115is formed from the lower portion112(as shown inFIG.1A), in accordance with some embodiments. The fin structures116are separated from each other by the trenches111, in accordance with some embodiments.

As shown inFIGS.1C and1C-1, the mask layer120is removed, in accordance with some embodiments. As shown inFIGS.1C and1C-1, a liner layer132is conformally formed over sidewalls116sof the fin structures116and a top surface113aof the base113, in accordance with some embodiments. As shown inFIGS.1C and1C-1, a dielectric layer134is formed over the liner layer132and in the trenches111, in accordance with some embodiments. The liner layer132and the dielectric layer134together form an isolation structure130, in accordance with some embodiments.

The liner layer132is made of oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), or another suitable dielectric material, in accordance with some embodiments. The dielectric layer134is made of oxide (such as silicon oxide), fluorosilicate glass (FSG), a low-k dielectric material, and/or another suitable dielectric material. In some embodiments, the liner layer132and the dielectric layer134are made of different materials.

The removal of the mask layer120and the formation of the liner layer132and the dielectric layer134include: conformally depositing a liner material layer (not shown) over the substrate110; depositing a dielectric material layer (not shown) over the liner material layer; and performing a planarization process to remove the liner material layer and the dielectric material layer outside of the trenches111and the mask layer120, in accordance with some embodiments.

The liner material layer may be deposited by an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or another applicable process. The dielectric material layer may be deposited by a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition (PVD) process, or another applicable process.

As shown inFIGS.1D and1D-1, an upper portion of the isolation structure130is removed to expose sidewalls114cof the multilayer structure114, in accordance with some embodiments. The removal process includes an etching process such as a dry etching process or a wet etching process, in accordance with some embodiments.

As shown inFIGS.1D and1D-1, a cladding layer140is formed over the sidewalls114cof the multilayer structure114, in accordance with some embodiments.

The cladding layer140is used to reserve a space for a gate stack formed in the subsequent process, in accordance with some embodiments.

The sacrificial layers114a′, the thick sacrificial layer114a1, and the cladding layer140are made of the same first material, in accordance with some embodiments. The channel layers114b′ are made of a second material, in accordance with some embodiments. The first material is different from the second material, in accordance with some embodiments.

The cladding layer140is made of a semiconductor material such as SiGe, Si, and/or germanium, a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide, an alloy semiconductor such as GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or combinations thereof, in accordance with some embodiments.

The cladding layer140is formed using an epitaxial growth process such as a molecular beam epitaxy (MBE) process, a metal-organic chemical vapor deposition (MOCVD) process, and/or another suitable epitaxial growth process.

As shown inFIG.1E, a liner layer152is conformally formed over the isolation structure130, the cladding layer140, and the multilayer structure114, in accordance with some embodiments. As shown inFIG.1E, a dielectric layer154is formed over the liner layer152and in the trenches111, in accordance with some embodiments. The liner layer152and the dielectric layer154together form an isolation structure150, in accordance with some embodiments.

The liner layer152is made of oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), or another suitable dielectric material, in accordance with some embodiments. The dielectric layer154is made of oxide (such as silicon oxide), fluorosilicate glass (FSG), a low-k dielectric material, and/or another suitable dielectric material. In some embodiments, the liner layer152and the dielectric layer154are made of different materials.

The liner layer152may be deposited by an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or another applicable process. The dielectric layer154may be deposited by a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition (PVD) process, or another applicable process.

As shown inFIG.1F, an upper portion of the isolation structure150is removed, in accordance with some embodiments. The removal process includes an etching process such as a dry etching process or a wet etching process, in accordance with some embodiments.

As shown inFIG.1G, a dielectric layer160ais formed over the isolation structure150, the cladding layer140, and the multilayer structure114and in the trenches111, in accordance with some embodiments. The dielectric layer160ais made of a dielectric material, such as a high dielectric constant (high-k) material, in accordance with some embodiments. The term “high-k material” means a material having a dielectric constant greater than the dielectric constant of silicon dioxide, in accordance with some embodiments.

The high-k material includes metal oxides, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), aluminum oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, other suitable high-k dielectric materials, or combinations thereof, in accordance with some embodiments.

In some other embodiments, the high-k material includes metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, other suitable materials, or combinations thereof.

The dielectric layer160ais formed using a deposition process such as a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or the like, in accordance with some embodiments.

As shown inFIGS.1G and1H, portions of the dielectric layer160aoutside of the trenches111are removed, in accordance with some embodiments. After the removal process, the remaining dielectric layer160ain the trenches111forms dielectric fins160, in accordance with some embodiments. The removal process includes a planarization process such as a chemical mechanical polishing process, in accordance with some embodiments.

As shown inFIG.11, the thick sacrificial layer114a1and upper portions of the cladding layer140are removed, in accordance with some embodiments. After the removal process, trenches162are formed between the dielectric fins160, in accordance with some embodiments. The trenches162expose the multilayer structure114and the cladding layer140thereunder, in accordance with some embodiments. The removal process includes an etching process such as a wet etching process or a dry etching process, in accordance with some embodiments.

FIGS.1J-1is a perspective view of the semiconductor device structure ofFIG.1J, in accordance with some embodiments.FIG.1J-2is a top view of the semiconductor device structure ofFIG.1J, in accordance with some embodiments.FIG.1Jis a cross-sectional view illustrating the semiconductor device structure along a sectional line I-I′ inFIG.1J-1orFIG.1J-2, in accordance with some embodiments.

As shown inFIGS.1J,1J-1, and1J-2, a gate dielectric material layer172ais conformally formed over the dielectric fins160, the multilayer structure114, and the cladding layer140, in accordance with some embodiments. The gate dielectric material layer172ais made of an insulating material, such as oxide (e.g., silicon oxide), in accordance with some embodiments.

The gate dielectric material layer172ais formed by a deposition process, such as a chemical vapor deposition (CVD) process, a low-pressure chemical vapor deposition (LPCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a high-density plasma chemical vapor deposition (HDPCVD) process, a physical vapor deposition (PVD) process, or another applicable process.

As shown inFIGS.1J,1J-1, and1J-2, a gate electrode layer174ais formed over the gate dielectric material layer172a, in accordance with some embodiments. The gate electrode layer174ais made of a semiconductor material (e.g. polysilicon) or a conductive material (e.g., metal or alloy), in accordance with some embodiments.

The gate electrode layer174ais formed by a deposition process, such as a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or another applicable process, in accordance with some embodiments.

FIGS.2A-2Oare cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments.FIGS.2A-1to2O-1are top views of the semiconductor device structure ofFIGS.2A to2O, in accordance with some embodiments.

FIGS.2A-2Oare cross-sectional views illustrating the semiconductor device structure along a sectional line I-I′ inFIGS.2A-1to2O-1, in accordance with some embodiments.FIGS.2A-2and2B-2are cross-sectional views illustrating the semiconductor device structure along a sectional line II-II′ inFIGS.2A-1and2B-1, in accordance with some embodiments.

After the step ofFIG.1J, as shown inFIGS.2A,2A-1, and2A-2, mask layers M1and M2are sequentially formed over the gate electrode layer174a, in accordance with some embodiments. The mask layer M1has strip portions M1s, in accordance with some embodiments. The mask layer M2has strip portions M2s, in accordance with some embodiments.

The mask layers M1and M2expose portions of the gate electrode layer174a, in accordance with some embodiments. In some embodiments, the mask layer M1serves a buffer layer or an adhesion layer that is formed between the underlying gate electrode layer174aand the overlying mask layer M2. The mask layer M1may also be used as an etch stop layer when the mask layer M2is removed or etched.

In some embodiments, the mask layer M1is made of an oxide-containing insulating material (e.g., silicon oxide), a nitride-containing insulating material (e.g., silicon nitride, silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride), silicon carbide, or a metal oxide material (e.g., aluminum oxide).

In some embodiments, the mask layer M2is made of an oxide-containing insulating material (e.g., silicon oxide), a nitride-containing insulating material (e.g., silicon nitride, silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride), silicon carbide, or a metal oxide material (e.g., aluminum oxide). The mask layers M1and M2are made of different materials, in accordance with some embodiments.

The formation of the mask layers M1and M2includes: forming a first mask material layer (not shown) over the gate electrode layer174a; forming a second mask material layer (not shown) over the first mask material layer; and patterning the first mask material layer and the second mask material layer by a photolithography process and an etching process, in accordance with some embodiments.

In some embodiments, the first mask material layer is formed by a deposition process, such as a chemical vapor deposition (CVD) process, a low-pressure chemical vapor deposition (LPCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, or a high-density plasma chemical vapor deposition (HDPCVD) process, a spin-on process, or another applicable process.

In some embodiments, the second mask material layer is formed by a deposition process, such as a chemical vapor deposition (CVD) process, a low-pressure chemical vapor deposition (LPCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, or a high-density plasma chemical vapor deposition (HDPCVD) process, a spin-on process, or another applicable process.

As shown inFIGS.2A,2B,2B-1, and2B-2, portions of the gate dielectric material layer172aand the gate electrode layer174a, which are not covered by the mask layers M1and M2, are removed, in accordance with some embodiments.

After the removal process, the remaining gate dielectric material layer172aforms a gate dielectric layer172, and the remaining gate electrode layer174aforms a gate electrode174, in accordance with some embodiments. Under one of the strip portions M1sof the mask layer M1, the gate electrode174and the gate dielectric layer172thereunder together form a gate stack170, in accordance with some embodiments.

In some embodiments, the removal process further removes an upper portion of the topmost channel layer114b′ and therefore recesses114b1are formed in the topmost channel layer114b′. The removal process includes an etching process, such as an anisotropic etching process (e.g., a dry etching process), in accordance with some embodiments.

As shown inFIGS.2C and2C-1, a spacer layer180ais formed over the fin structures116, the cladding layer140, the dielectric fins160, and the mask layers M1and M2, in accordance with some embodiments.

The spacer layer180ais made of an oxide-containing insulating material, such as silicon oxide. In some other embodiments, the spacer layer180ais made of a nitride-containing insulating material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or silicon carbonitride (SiCN).

In some embodiments, the spacer layer180ais a single-layered structure. In some embodiments, the spacer layer180ais a multi-layered structure. The spacer layer180ais formed using a deposition process, such as a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, or a physical vapor deposition (PVD) process, in accordance with some embodiments.

FIG.2D-2is a perspective view of a portion of the semiconductor device structure in a region RE ofFIG.2D, in accordance with some embodiments.FIG.2Dis a cross-sectional view illustrating the semiconductor device structure along a sectional line I-I′ inFIG.2D-1orFIG.2D-2, in accordance with some embodiments.

As shown inFIGS.2C,2D,2D-1and2D-2, portions of the spacer layer180aand upper portions of the fin structures116and the cladding layer140, which are not covered by the gate stacks170and the spacer layer180aover sidewalls of the gate stacks170, are removed, in accordance with some embodiments.

After the removal process, the spacer layer180aremaining over opposite sidewalls of the gate stacks170and opposite sidewalls of the mask layers M1and M2forms a spacer180, in accordance with some embodiments. After the removal process, the cladding layer140remains under the gate stacks170and the spacer180, in accordance with some embodiments.

As shown inFIG.2D, the removal process forms recesses116ain the fin structures116, in accordance with some embodiments. In one of the fin structures116, the multilayer structure114is divided into multilayer stacks114S by the recesses116a, in accordance with some embodiments.

In each multilayer stack114S, the remaining sacrificial layers114a′ form sacrificial nanostructures114a, and the remaining channel layers114b′ form channel nanostructures114b, in accordance with some embodiments. Each multilayer stack114S includes three sacrificial nanostructures114aand three channel nanostructures114b, in accordance with some embodiments. The sacrificial nanostructures114aand the channel nanostructures114binclude nanowires and/or nanosheets, in accordance with some embodiments.

The sacrificial nanostructure114ais thinner than the channel nanostructure114b, in accordance with some embodiments. That is, the thickness T114aof the sacrificial nanostructure114ais less than the thickness T114bof the channel nanostructure114b, in accordance with some embodiments.

The thickness T114ais less than or equal to 5 nm, in accordance with some embodiments. The thickness T114aranges from about 1 nm to about 5 nm, in accordance with some embodiments. The thickness T114branges from about 7 nm to about 15 nm, in accordance with some embodiments. In some embodiments, a ratio of the thickness T114bto the thickness T114aranges from about 1.8 to about 3.

As shown inFIG.2D-2, the distance D114bbetween the channel nanostructures114b(or between the channel nanostructure114band the bottom portion115) is substantially equal to the thickness T114a, in accordance with some embodiments. The distance D114branges from about 1 nm to about 5 nm, in accordance with some embodiments.

The distance D114abetween the sacrificial nanostructures114ais substantially equal to the thickness T114b, in accordance with some embodiments. The distance D114aranges from about 7 nm to about 15 nm, in accordance with some embodiments. The distance D114bis less than the distance D114a, in accordance with some embodiments.

The embodiments are able to control an etching rate of the sacrificial nanostructures114ain a subsequent etching process by adjusting the thickness T114aor the distance D114b, in accordance with some embodiments. If the thickness T114aor the distance D114bis reduced, the structural obstruction caused by the channel nanostructures114bis increased, and therefore the etching rate of the sacrificial nanostructures114ais reduced, in accordance with some embodiments.

The removal process for forming the recesses116aincludes an etching process, such as an anisotropic etching process (e.g., a dry etching process), in accordance with some embodiments.

FIG.2E-2is a perspective view of a portion of the semiconductor device structure in a region RE ofFIG.2E, in accordance with some embodiments.FIG.2Eis a cross-sectional view illustrating the semiconductor device structure along a sectional line I-I′ inFIG.2E-1orFIG.2E-2, in accordance with some embodiments.

As shown inFIGS.2D-2,2E,2E-1, and2E-2, portions of the sacrificial nanostructures114aand the cladding layer140are removed from sidewalls S1of the sacrificial nanostructures114aand sidewalls142of the cladding layer140, in accordance with some embodiments.

Therefore, the removal process forms recesses R1in the multilayer stacks114S, in accordance with some embodiments. Each recess R1is surrounded by the corresponding sacrificial nanostructure114aand the corresponding channel nanostructures114b, in accordance with some embodiments.

In some embodiments, the removal process further removes portions of the channel nanostructures114badjacent to the recesses R1and therefore forms recesses R2in the channel nanostructures114b.

As shown inFIG.2E-2, the removal process forms recesses R3, in accordance with some embodiments. Each recess R3is surrounded by the cladding layer140, the corresponding gate stack170, and the corresponding multilayer stack114S, in accordance with some embodiments. The recesses R3are on opposite sides of the cladding layer140, in accordance with some embodiments.

FIG.2E-3is a cross-sectional view illustrating the semiconductor device structure along a sectional line II-II′ inFIG.2E-2, in accordance with some embodiments.FIG.2E-4is a cross-sectional view illustrating the semiconductor device structure along a sectional line III-III′ inFIG.2E-2, in accordance with some embodiments.

As shown inFIGS.2E-1,2E-2,2E-3, and2E-4, the recesses R3extend from opposite sides of the cladding layer140into the cladding layer140, in accordance with some embodiments. The cladding layer140has ends144e1and144e2, in accordance with some embodiments. The end144e1is connected to the multilayer stack114S, in accordance with some embodiments. The end144e2is connected to the isolation structure150, in accordance with some embodiments.

The removal speed (or the etching rate) of the ends144e1and144e2is lower than that of the middle portion of the cladding layer140because of the structural obstruction caused by the multilayer stack114S and the isolation structure150, in accordance with some embodiments. Therefore, the cladding layer140has a neck144nafter the removal process, in accordance with some embodiments.

The neck144nis connected between the ends144e1and144e2, in accordance with some embodiments. The neck144nis narrower than the end144e1, in accordance with some embodiments. The neck144nis narrower than the end144e2, in accordance with some embodiments. That is, as shown inFIG.2E-3, the width W140of the neck144nis less than the width W144e1of the end144e1as measured along a longitudinal axis A1of the fin structure116, in accordance with some embodiments. The width W140is less than the width W144e2of the end144e2as measured along the longitudinal axis A1, in accordance with some embodiments.

The width W144e1ranges from about 8 nm to about 17 nm, in accordance with some embodiments. The width W144e2ranges from about 8 nm to about 17 nm, in accordance with some embodiments. The width W140ranges from about 5 nm to about 14 nm, in accordance with some embodiments.

The width W140is also referred to as a minimum width of the remaining cladding layer140as measured along the longitudinal axis A1, in accordance with some embodiments. The width WR3of the recess R3ranges from about 5 nm to about 10 nm, in accordance with some embodiments. The depth DR3of the recess R3ranges from about 1 nm to about 3 nm, in accordance with some embodiments.

After the removal process, the sidewalls142become curved sidewalls, in accordance with some embodiments. The curvature radius of the sidewall142ranges from about 2.5 nm to about 6 nm, in accordance with some embodiments. The curvature radius of the sidewall142ranges from about 2.5 nm to about 4 nm, in accordance with some embodiments.

Since the distance D114bbetween the channel nanostructures114b(or between the channel nanostructure114band the bottom portion115) is small (≤5 nm), the removal speed (or the etching rate) of the sacrificial nanostructures114ais lower than the removal speed (or the etching rate) of the cladding layer140, in accordance with some embodiments.

Therefore, after the removal process is performed, the remaining cladding layer140is substantially narrower than the remaining sacrificial nanostructure114a, in accordance with some embodiments. That is, as shown inFIG.2E-3, the (minimum) width W140of the remaining cladding layer140is less than the width W114aof the sacrificial nanostructures114a, in accordance with some embodiments.

In some embodiments, a difference between the widths W1l4aand W140ranges from about 2 nm to about 6 nm. The difference between the widths W114aand W140ranges from about 2 nm to about 4 nm, in accordance with some embodiments. The width W114aranges from about 8 nm to about 17 nm, in accordance with some embodiments.

The removal process includes etching processes, such as dry etching processes and wet etching processes, in accordance with some embodiments. In some embodiments, the removal process includes a first dry etching process, a first wet etching process, a second dry etching process, and a second wet etching process, which are performed sequentially.

The first dry etching process includes a plasma etching process, in accordance with some embodiments. The first dry etching process uses He gas of about 300 sccm to about 2200 sccm, Ar gas of about 80 sccm to about 1100 sccm, and NF3gas of about 5 sccm to about 200 sccm under about 0° C. to about 30° C. temperature and about 0.5 Torr to about 15 Torr pressure for about 30 seconds to about 80 seconds, in accordance with some embodiments.

The first wet etching process uses a dilute hydrofluoric acid (HF) solution, in accordance with some embodiments. The volume percentage concentration of the dilute hydrofluoric acid solution ranges from about 0.5% to about 2%, in accordance with some embodiments.

The second dry etching process uses He gas of about 300 sccm to about 2200 sccm. Ar gas of about 80 sccm to about 1100 sccm, and NF3gas of about 5 sccm to about 200 sccm under about 0° C. to about 30° C. temperature and about 0.5 Torr to about 15 Torr pressure for about 10 seconds to about 50 seconds, in accordance with some embodiments.

The second wet etching process uses a dilute hydrofluoric acid solution, in accordance with some embodiments. The volume percentage concentration of the dilute hydrofluoric acid solution ranges from about 0.5% to about 2%, in accordance with some embodiments.

FIG.2Fis a cross-sectional view illustrating the semiconductor device structure along a sectional line I-I′ inFIG.2F-1, in accordance with some embodiments. As shown inFIGS.2E-2,2F, and2F-1, an inner spacer layer190ais formed over the spacer layer180, the mask layer M2, and the substrate110and in the recesses R1, R2, and R3, in accordance with some embodiments.

In some embodiments, the inner spacer layer190ais made of an oxide-containing insulating material, such as silicon oxide, or a nitride-containing insulating material, such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or silicon carbonitride (SiCN), in accordance with some embodiments. The inner spacer layer190ais formed using a deposition process such as an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, or another applicable process.

FIG.2G-1is a top view of the semiconductor device structure ofFIG.2G, in accordance with some embodiments.FIG.2G-2is a perspective view of a portion of the semiconductor device structure in a region RE ofFIG.2G, in accordance with some embodiments.FIG.2Gis a cross-sectional view illustrating the semiconductor device structure along a sectional line I-I′ inFIG.2G-1orFIG.2G-2, in accordance with some embodiments.

As shown inFIGS.2F,2G.2G-1, and2G-2, portions of the inner spacer layer190aoutside of the recesses R1, R2, and R3are removed, in accordance with some embodiments. The remaining inner spacer layer190aincludes inner spacers192and194, in accordance with some embodiments. The inner spacers192are in the recesses R1and R2of the multilayer stacks114S, in accordance with some embodiments.

The inner spacers194are in the recesses R3, which are surrounded by the cladding layer140, the corresponding gate stack170, and the corresponding multilayer stack114S, in accordance with some embodiments.

FIG.2G-3is a cross-sectional view illustrating the semiconductor device structure along a sectional line II-II′ inFIG.2G-2, in accordance with some embodiments.FIG.2G-4is a cross-sectional view illustrating the semiconductor device structure along a sectional line III-III′ inFIG.2G-2, in accordance with some embodiments.

As shown inFIGS.2G-1,2G-2,2G-3, and2G-4, the inner spacer194has a curved sidewall194s, in accordance with some embodiments. In some embodiments, a sum of a maximum width W194L of the left one of the inner spacers194and a maximum width W194R of the right one of the inner spacers194is greater than the minimum width W140of the cladding layer140as measured along the longitudinal axis A1of the fin structure116, in accordance with some embodiments.

The inner spacers192and194together form an inner spacer structure190, in accordance with some embodiments. The inner spacer structure190is a continuous structure, in accordance with some embodiments.

As shown inFIG.2G-2, the inner spacer194is wider than the inner spacer192, in accordance with some embodiments. That is, the width W194of the inner spacer194is greater than the width W192of the inner spacer192as measured along the longitudinal axis A1of the fin structure116, in accordance with some embodiments.

As shown inFIG.2G-3, a portion of the cladding layer140is between the inner spacer194and the sacrificial nanostructure114a, in accordance with some embodiments. As shown inFIG.2G-4, a portion of the cladding layer140is between the inner spacers194and the channel nanostructure114b, in accordance with some embodiments. The removal process includes an etching process, such as a dry etching process or a wet etching process, in accordance with some embodiments.

FIG.2His a cross-sectional view illustrating the semiconductor device structure along a sectional line I-I′ inFIG.2H-l, in accordance with some embodiments. As shown inFIGS.2H and2H-1, source/drain structures210are formed over the bottom portions115of the fin structures116, in accordance with some embodiments.

The source/drain structures210are connected to the sidewalls114b1of the channel nanostructures114b, in accordance with some embodiments. The source/drain structures210are also referred to as stressors, in accordance with some embodiments.

In some embodiments, the source/drain structures210are made of a semiconductor material (e.g., silicon germanium) with P-type dopants, such as the Group IIIA element, in accordance with some embodiments. The Group IIIA element includes boron or another suitable material.

In some other embodiments, the source/drain structures210are made of a semiconductor material (e.g., silicon) with N-type dopants, such as the Group VA element, in accordance with some embodiments. The Group VA element includes phosphor (P), antimony (Sb), or another suitable Group VA material. The source/drain structures210are formed using an epitaxial process, in accordance with some embodiments.

Since the etching rate of the sacrificial nanostructures114ais lower than the etching rate of the cladding layer140, the sacrificial nanostructures114aare able to keep enough width while the cladding layer140is greatly narrowed after the removal process ofFIG.2E, in accordance with some embodiments. Therefore, the distance D3between the neck144n(i.e., the main portion) of the cladding layer140and the source/drain structures210is increased, in accordance with some embodiments.

The cladding layer140is used to reserve a space for a gate stack formed in the subsequent process, in accordance with some embodiments. Therefore if the distance D3is increased, the distance between the gate stack and the source/drain structures210is increased. As a result, the parasitic capacitance between the gate stack and the source/drain structures210is reduced, which improves the performance of the semiconductor device structure with the gate stack and the source/drain structures210, in accordance with some embodiments.

Furthermore, if the distance D3is increased, the width W194of the inner spacer194is increased as well, which is able to avoid short circuit between the gate stack and the source/drain structures210and reduce the leakage current between the gate stack and the source/drain structures210, in accordance with some embodiments. Therefore, the yield of the semiconductor device structure with the (wide) inner spacer194is improved, in accordance with some embodiments.

As shown inFIGS.2I and2I-1, an etch stop layer220is formed over the source/drain structures210, the spacer layer180, and the mask layer M2, in accordance with some embodiments. The etch stop layer220is made of a dielectric material such as a nitride-containing material including silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbonitride (SiCN), in accordance with some embodiments.

Thereafter, as shown inFIGS.2I and2I-1, a dielectric layer230is formed over the etch stop layer220, in accordance with some embodiments. The etch stop layer220is between the dielectric layer230and the source/drain structures210to separate the dielectric layer230from the source/drain structures210, in accordance with some embodiments.

The dielectric layer230is made of an insulating material such as an oxide-containing material including silicon oxide, or a nitride-containing material including silicon nitride, silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride, in accordance with some embodiments.

FIGS.2J-2to2O-2are cross-sectional views illustrating the semiconductor device structure along a sectional line II-II′ inFIGS.2J-1to2O-1, in accordance with some embodiments.FIGS.2J to2Oare cross-sectional views illustrating the semiconductor device structure along a sectional line I-I′ inFIGS.2J-1to2O-1, in accordance with some embodiments.

As shown inFIGS.2I,2J,2J-1, and2J-2, top portions of the etch stop layer220, the dielectric layer230, the spacer layer180, and the gate stack170and the mask layers M1and M2are removed, in accordance with some embodiments. After the removal process, top surfaces222,232,182, and176of the etch stop layer220, the dielectric layer230, the spacer layer180, and the gate stack170are substantially level with each other, in accordance with some embodiments. The removal process includes a planarization process such as a chemical mechanical polishing process, in accordance with some embodiments.

As shown inFIGS.2K,2K-1, and2K-2, the gate stacks170are removed to form trenches184in the spacer layer180and trenches162between the dielectric fins160, in accordance with some embodiments. The removal process includes an etching process, such as a wet etching process or a dry etching process, in accordance with some embodiments.

As shown inFIGS.2L,2L-1, and2L-2, the sacrificial nanostructures114aand the cladding layer140are removed through the trenches184in the spacer layer180and the trenches162between the dielectric fins160, in accordance with some embodiments. As shown inFIG.2L, gaps G between the bottom portion115and the channel nanostructure114band between the channel nanostructures114bare formed after removing the sacrificial nanostructures114a, in accordance with some embodiments.

As shown inFIGS.2L-1and2L-2, through holes156are formed in the isolation structure150after removing the cladding layer140, in accordance with some embodiments. The through holes156expose the isolation structure130thereunder, in accordance with some embodiments. The removal process includes an etching process, such as a wet etching process or a dry etching process, in accordance with some embodiments.

As shown inFIGS.2M,2M-1, and2M-2, a gate dielectric layer242is formed over the channel nanostructures114band the bottom portions115of the fin structures116exposed by the trenches184in the spacer layer180and the trenches162between the dielectric fins160, in accordance with some embodiments.

The gate dielectric layer242is made of a dielectric material such as an oxide material (e.g., silicon oxide) or a high-K material, such as HfO2, ZrO2, HfZrO2, or Al2O3, in accordance with some embodiments. The gate dielectric layer242is formed using an oxidation process, a selective deposition process, an atomic layer deposition process or another suitable process.

As shown inFIGS.2M,2M-1, and2M-2, a work function metal layer244is conformally formed over the gate dielectric layer242, the spacer layer180, the dielectric fins160, and the isolation structure150and in the trenches184and162, in accordance with some embodiments. The work function metal layer244is made of titanium-containing material (e.g., TiN or TiSiN) or tantalum-containing material (e.g., TaN), or another suitable conductive material. The work function metal layer244is formed using an atomic layer deposition process or another suitable process.

As shown inFIGS.2M,2M-1, and2M-2, a gate electrode layer246is formed over the work function metal layer244, in accordance with some embodiments. The gate electrode layer246is made of W, Co, Al, or another suitable conductive material. The gate electrode layer246is formed using a physical vapor deposition process, an atomic layer deposition process, or another suitable process.

FIG.2N-3is a perspective view of a portion of the semiconductor device structure in a region RE ofFIG.2N, in accordance with some embodiments. As shown inFIGS.2N,2N-1,2N-2, and2N-3, the work function metal layer244and the gate electrode layer246outside of the trenches184and162and top portions of the spacer layer180, the etch stop layer220, and the dielectric layer230are removed, in accordance with some embodiments.

After the removal process, in one of the trenches184or162, the gate dielectric layer242, the remaining work function metal layer244, and the remaining gate electrode layer246together form a gate stack240, in accordance with some embodiments. The gate stack240is wrapped around the channel nanostructures114b, in accordance with some embodiments. In some embodiments, a portion of the gate stack240is between the channel nanostructure114band the bottom portion115.

As shown inFIGS.2N,2N-2, and2N-3, each gate stack240has an upper portion241, sidewall portions243, and lower portions245, in accordance with some embodiments. The upper portion241is over the channel nanostructures114b, in accordance with some embodiments. The lower portions245are between the channel nanostructures114band between the channel nanostructure114band the bottom portion115, in accordance with some embodiments.

FIG.2N-4is a cross-sectional view illustrating the semiconductor device structure along a sectional line III-III′ inFIG.2N-3, in accordance with some embodiments.FIG.2N-5is a cross-sectional view illustrating the semiconductor device structure along a sectional line IV-IV′ inFIG.2N-3, in accordance with some embodiments.

As shown inFIGS.2N-2,2N-3,2N-4, and2N-5, the sidewall portions243are over sidewalls114b2of the channel nanostructures114b, in accordance with some embodiments. The sidewall portion243has a neck243nand opposite ends243e1and243e2, in accordance with some embodiments. The end243e1is connected to the multilayer stack114S, in accordance with some embodiments. The end243e2is connected to the isolation structure150, in accordance with some embodiments.

The neck243nis connected between the ends243e1and243e2, in accordance with some embodiments. The neck243nis narrower than the end243e1, in accordance with some embodiments. The neck243nis narrower than the end243e2, in accordance with some embodiments. That is, as shown inFIG.2N-5, the width W243of the neck243nis less than the width W243e1of the end243e1as measured along the longitudinal axis A1of the fin structure116, in accordance with some embodiments. The width W243is less than the width W243e2of the end243e2as measured along the longitudinal axis A1, in accordance with some embodiments.

The width W243e1ranges from about 8 nm to about 17 nm, in accordance with some embodiments. The width W243e2ranges from about 8 nm to about 17 nm, in accordance with some embodiments. The width W243ranges from about 5 nm to about 14 nm, in accordance with some embodiments. The width W243is also referred to as a minimum width of the gate stack240as measured along the longitudinal axis A1, in accordance with some embodiments.

The sidewall portion243has opposite sidewalls243s, in accordance with some embodiments. The sidewalls243sare curved concave sidewalls, in accordance with some embodiments. The curvature radius of the sidewall243sranges from about 2.5 nm to about 6 nm, in accordance with some embodiments. The curvature radius of the sidewall243sranges from about 2.5 nm to about 4 nm, in accordance with some embodiments.

The inner spacers194respectively extend from opposite sidewalls243sof the sidewall portion243into the sidewall portion243, in accordance with some embodiments. In some embodiments, as shown inFIG.2N-5, a part of the sidewall portion243is between the inner spacer194and the channel nanostructure114b. The inner spacer194is surrounded by the channel nanostructure114band the gate stack240, in accordance with some embodiments.

In some embodiments, as shown inFIG.2N-4, a sum of a maximum width W194L of the left one of the inner spacers194and a maximum width W194R of the right one of the inner spacers194is greater than the minimum width W243of the sidewall portion243as measured along the longitudinal axis A1of the fin structure116.

Specifically, the maximum width W194L of the left one of the inner spacers194is the distance between the left sidewall S1Land the rightmost endpoint S1Rof the (left) inner spacer194, in accordance with some embodiments. The maximum width W194R of the right one of the inner spacers194is the distance between the right sidewall S2Rand the leftmost endpoint S2Lof the (right) inner spacer194, in accordance with some embodiments. The minimum width W243of the sidewall portion243is the distance between the rightmost endpoint S1Rof the (left) inner spacer194and the leftmost endpoint S2Lof the (right) inner spacer194, in accordance with some embodiments.

As shown inFIG.2N-4, the inner spacer194(the lower left one) is connected to the inner spacer192(the left one), and the inner spacers192and194together form a continuous structure having an L-like shape, in accordance with some embodiments.

As shown inFIG.2N-3, the inner spacer192is under the channel nanostructures114band beside the lower portion245of the gate stack240, in accordance with some embodiments. The upper portion241of the gate stack240is wider than the neck243nof the sidewall portion243of the gate stack240, in accordance with some embodiments.

As shown inFIGS.2N-3and2N-4, the lower portion245is wider than the sidewall portion243, in accordance with some embodiments. The lower portion245of the gate stack240is thinner than the channel nanostructures114b, in accordance with some embodiments.

As shown inFIGS.2N-1and2N-3, the inner spacers192are under the channel nanostructures114band between the lower portion245of the gate stack240and the source/drain structures210, in accordance with some embodiments. The inner spacer192separates the source/drain structures210from the lower portions245of the gate stack240, in accordance with some embodiments.

As shown inFIGS.2N-1and2N-3, the inner spacer194separates the source/drain structures210from the sidewall portion243of the gate stack240, in accordance with some embodiments. The inner spacers194are under the upper portion241of the gate stack240and beside the channel nanostructures114band the sidewall portions243, in accordance with some embodiments. The removal process includes a planarization process such as a chemical mechanical polishing process, in accordance with some embodiments.

As shown inFIGS.2O,2O-1, and2O-2, an etch stop layer250is formed over the spacer layer180, the etch stop layer220, the dielectric layer230, and the gate stack240, in accordance with some embodiments. The etch stop layer250is made of a dielectric material such as a nitride-containing material including silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbonitride (SiCN), in accordance with some embodiments.

Thereafter, as shown inFIGS.2O,2O-1, and2O-2, a dielectric layer260is formed over the etch stop layer250, in accordance with some embodiments. The etch stop layer250is between the dielectric layers260and the dielectric layer230to separate the dielectric layer260from the dielectric layer230, in accordance with some embodiments.

The dielectric layer260is made of an insulating material such as an oxide-containing material including silicon oxide, or a nitride-containing material including silicon nitride, silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride, in accordance with some embodiments.

As shown inFIGS.2O,2O-1, and2O-2, portions of the dielectric layer230, the etch stop layer220, the etch stop layer250, and the dielectric layer260are removed to form through holes272passing through the dielectric layer230, the etch stop layer220, the etch stop layer250, and the dielectric layer260, in accordance with some embodiments. As shown inFIGS.2O,2O-1, and2O-2, portions of the etch stop layer250and the dielectric layer260are removed to form through holes274passing through the etch stop layer250and the dielectric layer260, in accordance with some embodiments.

As shown inFIGS.2O,2O-1, and2O-2, contact structures282and284are respectively formed in the through holes272and274, in accordance with some embodiments. In this step, a semiconductor device structure200is substantially formed, in accordance with some embodiments. The contact structure282is in direct contact with and is electrically connected to the source/drain structures210thereunder, in accordance with some embodiments.

The contact structure284is in direct contact with and is electrically connected to the gate stack240thereunder, in accordance with some embodiments. The contact structure284is in direct contact with the etch stop layer250, the dielectric layer260, and the gate stack240, in accordance with some embodiments.

The contact structures282and284are made of tungsten (W), cobalt (Co), aluminum (Al), ruthenium (Ru), copper (Cu) or another suitable conductive material, in accordance with some embodiments. The formation of the contact structures282and284includes depositing a conductive material layer (not shown) over the dielectric layer260and in the through holes272and274; and performing a chemical mechanical polishing (CMP) process over the conductive material layer to remove the conductive material layer outside of the through holes272and274.

FIGS.3A-3Bare cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. As shown inFIG.3A, the semiconductor device structure ofFIG.3Ais similar to the semiconductor device structure ofFIG.2E, except that the distance D114b1between the channel nanostructure114band the bottom portion115is less than the distance D114b2between the channel nanostructures114b, in accordance with some embodiments.

Since the distance D114b1is less than the distance D114b2, the etching rate (or the removal speed) of the sacrificial nanostructures114a2is lower than the etching rate (or the removal speed) of the sacrificial nanostructures114a, in accordance with some embodiments. Therefore, after the removal process ofFIG.2E, the width W114a2of the sacrificial nanostructure114a2is greater than the width W114aof the sacrificial nanostructures114a, in accordance with some embodiments. The thickness T114a2of the sacrificial nanostructure114a2is less than the thickness T114aof the sacrificial nanostructures114a, in accordance with some embodiments.

As shown inFIG.3B, the steps ofFIGS.2F-2Oare performed to form the inner spacer structure190, the etch stop layer220, the dielectric layer230, the gate stack240, the etch stop layer250, the dielectric layer260, and the contact structures282and284, in accordance with some embodiments. In this step, a semiconductor device structure300is substantially formed, in accordance with some embodiments.

Each gate stack240has lower portions245aand245b, in accordance with some embodiments. The lower portion245ais thinner than the lower portion245b, in accordance with some embodiments. That is, the thickness T245aof the lower portion245ais less than the thickness T245bof the lower portion245b, in accordance with some embodiments.

The lower portion245ais wider than the lower portion245b, in accordance with some embodiments. That is, the width W245aof the lower portion245ais greater than the width W245bof the lower portion245b, in accordance with some embodiments. Therefore, the lower portion245amay control the channel in the bottom portion115more effectively, which reduces the leakage current between the source/drain structures210on opposite sides of the lower portion245a.

The inner spacer192beside the lower portion245bis thicker than the inner spacer192abeside the lower portion245a, in accordance with some embodiments. That is, the thickness T192of the inner spacer192is greater than the thickness T192aof the inner spacer192a, in accordance with some embodiments. The (thick) inner spacer192is able to avoid short circuit between the lower portion245band the source/drain structures210, in accordance with some embodiments. In some embodiments, sidewalls192sof the inner spacers192and192aare recessed from the sidewalls114bsof the channel nanostructures114b.

FIGS.4A-4Care cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. As shown inFIG.4A, after the step ofFIG.2K-2, a mask layer410is formed over a portion164of the dielectric fins160, in accordance with some embodiments. The mask layer410has an opening412exposing a portion166of the dielectric fins160, in accordance with some embodiments.

As shown inFIG.4B, the portion166of the dielectric fins160is partially removed through the opening412, in accordance with some embodiments. As shown inFIG.4C, the steps ofFIGS.2L-2Oare performed, in accordance with some embodiments.

In this step, a semiconductor device structure400is substantially formed, in accordance with some embodiments. The gate stack240extends across the isolation structure150and the portion166of the dielectric fins160, in accordance with some embodiments. The gate stack240is wrapped around the channel nanostructures114bof different fin structures116, in accordance with some embodiments.

FIGS.5A-5Bare cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. As shown inFIG.5A, after the step ofFIG.4Ais performed, the portion166of the dielectric fins160is removed, in accordance with some embodiments.

As shown inFIG.5B, the step ofFIG.4Cis performed, in accordance with some embodiments. In this step, a semiconductor device structure500is substantially formed, in accordance with some embodiments. The gate stack240extends across the isolation structure150, in accordance with some embodiments. The gate stack240is wrapped around the channel nanostructures114bof different fin structures116, in accordance with some embodiments.

Processes and materials for forming the semiconductor device structures300,400, and500may be similar to, or the same as, those for forming the semiconductor device structure200described above. Elements designated by the same reference numbers as those inFIGS.1A to5Bhave structures and materials that are the same or similar. Therefore, the detailed descriptions thereof will not be repeated herein.

In accordance with some embodiments, semiconductor device structures and methods for forming the same are provided. The methods (for forming the semiconductor device structure) form a thin sacrificial nanostructure under a channel nanostructure and form a cladding layer over sidewalls of the channel nanostructure and the thin sacrificial nanostructure. The etching rate of the thin sacrificial nanostructure is lower than the etching rate of the cladding layer because of the structural obstruction caused by the channel nanostructure. Therefore, after an etching process is performed on sidewalls of the thin sacrificial nanostructure and the cladding layer, the remaining cladding layer is narrower than the remaining sacrificial nanostructure. Since the cladding layer is used to reserve a space for a gate stack formed in the subsequent process, the distance between the gate stack and a source/drain structure is increased by narrowing the cladding layer, which reduces the parasitic capacitance between the gate stack and the source/drain structures. Therefore, the performance of a semiconductor device structure with the gate stack and the source/drain structures is improved.

In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.

In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer respectively extending from opposite sides of the sidewall portion into the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.

In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes providing a substrate including a base and a fin structure over the base. The fin structure includes a multilayer stack, and the multilayer stack includes a first nanostructure and a second nanostructure over the first nanostructure. The method includes forming a cladding layer over a first sidewall of the multilayer stack. The method includes forming a gate stack over the multilayer stack and the cladding layer. The method includes partially removing the multilayer stack and the cladding layer, which are not covered by the gate stack. The method includes partially removing the first nanostructure and the cladding layer from sidewalls of the first nanostructure and the cladding layer to form a first recess, a second recess, and a third recess. The first recess is in the multilayer stack, and the second recess and the third recess are on opposite sides of the cladding layer and surrounded by the cladding layer, the gate stack, and the multilayer stack. The method includes forming a first inner spacer, a second inner spacer, and a third inner spacer respectively in the first recess, the second recess, and the third recess. A sum of a first width of the second inner spacer and a second width of the third inner spacer is greater than a third width of the cladding layer as measured along a longitudinal axis of the fin structure.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.