Patent ID: 12198977

DETAILED DESCRIPTION

Embodiments, or examples, of the disclosure illustrated in the drawings are now described using specific language. It shall be understood that no limitation of the scope of the disclosure is hereby intended. Any alteration or modification of the described embodiments, and any further applications of principles described in this document, are to be considered as normally occurring to one of ordinary skill in the art to which the disclosure relates. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that feature(s) of one embodiment apply to another embodiment, even if they share the same reference numeral.

It shall be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are merely used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting to the present inventive concept. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It shall be understood that the terms “comprises” and “comprising,” when used in this specification, point out the presence of stated features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

FIG.1is a schematic cross-sectional view of a first semiconductor structure100in accordance with some embodiments of the present disclosure. In some embodiments, the first semiconductor structure100is a part of a die, a package or a device. In some embodiments, the first semiconductor structure100is a die, a package or a device. In some embodiments, the first semiconductor structure100includes a first wafer101, a first passivation layer102over the first wafer101, a first conductive via105extending at least partially through the first wafer101, and a first elastic member106surrounded by the first conductive via105.

In some embodiments, the first wafer101is a workpiece that includes various features formed in or over the first wafer101. In some embodiments, the first wafer101is in various stages of fabrication and is processed using various processes. In some embodiments, the first wafer101includes a variety of electrical circuits suitable for a particular application. In some embodiments,FIG.1illustrates a part of the first wafer101. In some embodiments, a top surface of the first wafer101has a circular shape or any other suitable shape.

In some embodiments, the first wafer101includes a first substrate101a, a first dielectric layer101band a first interconnect structure101csurrounded by the first dielectric layer101b. In some embodiments, the first substrate101ais a part of the first wafer101. In some embodiments, the first substrate101ais a semiconductive layer. In some embodiments, the first substrate101aincludes semiconductive material such as silicon, germanium, gallium, arsenic, or a combination thereof. In some embodiments, the first substrate101ais a silicon substrate.

In some embodiments, electrical devices or components (e.g., various N-type metal-oxide semiconductor (NMOS) and/or P-type metal-oxide semiconductor (PMOS) devices, capacitors, resistors, diodes, photodiodes, fuses, and/or the like) are subsequently formed in or over the first substrate101aand configured to electrically connect to an external circuitry.

In some embodiments, the first dielectric layer101bis disposed under the first substrate101a. In some embodiments, the first dielectric layer101bincludes dielectric material such as oxide, nitride, silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, polymer or the like. In some embodiments, the first dielectric layer101bincludes several dielectric layers stacked over each other. In some embodiments, each of the dielectric layers includes materials that are same as or different from materials in others of the dielectric layers.

In some embodiments, the first wafer101is defined with a first surface101gand a second surface101hopposite to the first surface101g. In some embodiments, the first surface101gis a front side of the first wafer101, and the second surface101his a back side of the first wafer101. In some embodiments, various features are formed in or over the first surface101gof the first wafer101.

In some embodiments, the first interconnect structure101cincludes a first conductive pad101f, a third conductive pad101dand a first via101ebetween the first conductive pad101fand the third conductive pad101d. In some embodiments, the first conductive pad101fis surrounded by the first dielectric layer101b. In some embodiments, the first conductive pad101fis at least partially exposed through the first dielectric layer101b.

In some embodiments, the first conductive pad101fextends laterally in the first dielectric layer101b. In some embodiments, a portion of the first dielectric layer101bis disposed between the first substrate101aand the first conductive pad101f. In some embodiments, the first conductive pad101fincludes conductive material such as gold, silver, copper, nickel, tungsten, aluminum, tin, alloys thereof or the like. In some embodiments, a top surface of the first conductive pad101fhas a circular or polygonal shape.

In some embodiments, the third conductive pad101dis disposed under the first conductive pad101fand surrounded by the first dielectric layer101b. In some embodiments, the third conductive pad101dis at least partially exposed through the first dielectric layer101b. In some embodiments, the third conductive pad101dextends laterally in the first dielectric layer101b. In some embodiments, the third conductive pad101dis disposed adjacent to the first surface101gof the first wafer101.

In some embodiments, the third conductive pad101dis configured to electrically connect to a die, a package or a circuitry external to the semiconductor structure100. In some embodiments, a width W1of the first conductive pad101fis substantially greater than a width W3of the third conductive pad101d. In some embodiments, the third conductive pad101dincludes conductive material such as gold, silver, copper, nickel, tungsten, aluminum, tin, alloys thereof or the like. In some embodiments, a top surface of the third conductive pad101dhas a circular or polygonal shape.

In some embodiments, the first conductive pad101fis electrically connected to the third conductive pad101dthrough the first via101e. In some embodiments, the first via101eis surrounded by the first dielectric layer101band is in contact with the first conductive pad101fand the third conductive pad101d. In some embodiments, the first via101eincludes conductive material such as gold, silver, copper, nickel, tungsten, aluminum, tin, alloys thereof or the like. In some embodiments, a top surface of the first via101ehas a circular or polygonal shape.

In some embodiments, the first passivation layer102is disposed over the first wafer101. In some embodiments, the first passivation layer102is disposed over the first substrate101a. In some embodiments, the first passivation layer102is disposed on the second surface101hof the first wafer101. In some embodiments, the first passivation layer102includes dielectric materials, such as spin-on glass (SOG), silicon oxide, silicon oxynitride, silicon nitride or the like. In some embodiments, the first passivation layer102includes polymer, BCB, PBO, PI or the like.

In some embodiments, the first semiconductor structure100includes a first opening107extending from the first conductive pad101fthrough the first substrate101aand the first passivation layer102and partially through the first dielectric layer101b. In some embodiments, the first opening107is above the first interconnect structure101c.

In some embodiments, the first conductive via105is disposed within the first opening107. In some embodiments, the first conductive via105is surrounded by the first dielectric layer101b, the first substrate101aand the first passivation layer102. In some embodiments, the first conductive via105extends from and is electrically connected to the first conductive pad101f. In some embodiments, the first conductive via105is substantially orthogonal to the first conductive pad101f.

In some embodiments, the first conductive via105is a through substrate via (TSV). In some embodiments, the first conductive via105includes conductive material such as gold, silver, copper, nickel, tungsten, aluminum, tin, alloys thereof or the like. In some embodiments, a top surface of the first conductive via105has a circular or polygonal shape. In some embodiments, the first conductive via105has a cylindrical shape. In some embodiments, the first conductive via105has a consistent width along a height H1of the first conductive via105.

In some embodiments, the first elastic member106is disposed within the first conductive via105. In some embodiments, the first elastic member106is surrounded by the first substrate101aand the first passivation layer102. In some embodiments, the first elastic member106extends toward the first conductive pad101f. In some embodiments, the first elastic member106is above the first interconnect structure101c. In some embodiments, the first elastic member106includes organic material.

In some embodiments, the first elastic member106includes polymer, resin, epoxy or the like. In some embodiments, the first elastic member106is flexible and compressible. In some embodiments, the first elastic member106is configured to absorb a force or a stress generated during a manufacturing process. In some embodiments, a height H2of the first elastic member106is substantially less than the height H1of the first conductive via105.

In some embodiments, the first semiconductor structure100includes a first dielectric liner103between the first wafer101and the first conductive via105. In some embodiments, the first dielectric liner103is between the first conductive via105and the first passivation layer102. In some embodiments, the first dielectric liner103surrounds the first conductive via105and the first elastic member106. In some embodiments, the first dielectric liner103is disposed conformal to the first opening107. In some embodiments, the first dielectric liner103is in contact with the first conductive pad101fexposed through the first dielectric layer101b. In some embodiments, the first dielectric liner103includes dielectric material such as oxide or the like.

In some embodiments, the first semiconductor structure100includes a first conductive barrier layer104surrounding the first conductive via105and the first elastic member106. In some embodiments, the first conductive barrier layer104is disposed within the first opening107, conformal to the dielectric liner103, and in contact with the first conductive pad101fexposed through the first dielectric layer101b. In some embodiments, the first conductive barrier layer104and the first conductive via105are electrically connected to the first interconnect structure101c. In some embodiments, the first conductive barrier layer104is in contact with the first conductive via105and the first conductive pad101f.

In some embodiments, the first conductive barrier layer104includes titanium, titanium nitride, tantalum, tantalum nitride, nickel or the like. In some embodiments, the first conductive barrier layer104serves as a diffusion barrier layer for preventing diffusion of the first conductive via105. In some embodiments, a first seed layer is disposed between the first conductive barrier layer104and the first conductive via105. In some embodiments, the first seed layer includes titanium, copper, nickel, gold or the like. In some embodiments, a top surface of the first passivation layer102, a top surface of the first dielectric liner103, and a top surface of the first conductive via105are substantially coplanar.

FIG.2is a schematic cross-sectional view of a second semiconductor structure200in accordance with some embodiments of the present disclosure. In some embodiments, the second semiconductor structure200includes the first semiconductor structure100ofFIG.1. In some embodiments, a semiconductor structure similar to the first semiconductor structure100is stacked on the first semiconductor structure100to form the second semiconductor structure200as shown inFIG.2.

In some embodiments, a second wafer201is disposed over the first semiconductor structure100. In some embodiments, the second wafer201has a configuration similar to that of the first wafer101. In some embodiments, a thickness of the second wafer201is substantially equal to a thickness of the first wafer101.

In some embodiments, the second wafer201includes a second dielectric layer201bbonded over the first passivation layer102, a second substrate201aover the second dielectric layer201b, and a second interconnect structure201csurrounded by the second dielectric layer201b. In some embodiments, the second substrate201a, the second dielectric layer201band the second interconnect structure201chave configurations similar to those of the first substrate101a, the first dielectric layer101band the first interconnect structure101c, respectively. In some embodiments, the second dielectric layer201bis bonded to the first passivation layer102. In some embodiments, the second dielectric layer201bis in contact with the first conductive via105.

In some embodiments, the second interconnect structure201cincludes a second conductive pad201f, a fourth conductive pad201dand a second via201ebetween the second conductive pad201fand the fourth conductive pad201d. In some embodiments, the second conductive pad201f, the fourth conductive pad201dand the second via201ehave configurations similar to those of the first conductive pad101f, the third conductive pad101dand the first via101e, respectively. In some embodiments, the fourth conductive pad201dis under the second conductive pad201f.

In some embodiments, the second conductive pad201fis vertically aligned with the first conductive pad101f. In some embodiments, a width W2of the second conductive pad201fis substantially greater than a width W4of the fourth conductive pad201d. In some embodiments, the fourth conductive pad201dis electrically connected to the second conductive pad201fthrough the second via201eand at least partially exposed through the second dielectric layer201b. In some embodiments, the fourth conductive pad201dis bonded to and in contact with the first conductive via105.

In some embodiments, a second passivation layer202is disposed over the second substrate201a. In some embodiments, the second passivation layer202has a configuration similar to that of the first passivation layer102. In some embodiments, a second conductive via205extends from the second conductive pad201fthrough the second substrate201aand the second passivation layer202and partially through the second dielectric layer201b.

In some embodiments, the second conductive via205is electrically connected to the first conductive via105through the second conductive pad201fand the fourth conductive pad201d. In some embodiments, the second conductive pad201fand the fourth conductive pad201dare disposed between the first conductive via105and the second conductive via205. In some embodiments, the second conductive via205is vertically aligned with the first conductive via105.

In some embodiments, a second elastic member206is disposed within the second conductive via205. In some embodiments, the second elastic member206has a configuration similar to that of the first elastic member106. In some embodiments, the second elastic member206is vertically aligned with the first elastic member106. In some embodiments, a height H3of the second conductive via205is substantially greater than a height H4of the second elastic member206.

In some embodiments, a second opening207extends from the second conductive pad201fthrough the second substrate201aand the second passivation layer202and partially through the second dielectric layer201b. In some embodiments, the second opening207is above the second interconnect structure201c. In some embodiments, the second opening207has a configuration similar to that of the first opening107.

In some embodiments, a second dielectric liner203is disposed conformal to the second opening207and surrounds the second conductive via205. In some embodiments, the second dielectric liner203has a configuration similar to that of the first dielectric liner103. In some embodiments, a second conductive barrier layer204is disposed between the second dielectric liner203and the second conductive via205. In some embodiments, the second conductive barrier layer204has a configuration similar to that of the first conductive barrier layer104.

FIG.3is a schematic cross-sectional view of a third semiconductor structure300in accordance with some embodiments of the present disclosure. In some embodiments, the third semiconductor structure300is similar to the second semiconductor structure200, except the second conductive via205and the second elastic member206are laterally offset from the first conductive via105and the first elastic member106. In some embodiments, the second conductive pad201fis not vertically aligned with the first conductive pad101f. In some embodiments, the second conductive via205does not overlap the first conductive via105from a top view. In some embodiments, a width of the first conductive pad101fis substantially less than a width of the second conductive pad201f.

FIG.4is a flow diagram illustrating a method S400of manufacturing the first semiconductor structure100in accordance with some embodiments of the present disclosure, andFIGS.5to17illustrate cross-sectional views of intermediate stages in the formation of the first semiconductor structure100in accordance with some embodiments of the present disclosure.

The stages shown inFIGS.5to17are also illustrated schematically in the flow diagram inFIG.4. In the following discussion, the fabrication stages shown inFIGS.5to17are discussed in reference to the process steps shown inFIG.4. The method S400includes a number of operations and the description and illustration are not deemed as a limitation to the sequence of the operations. The method S400includes a number of steps (S401, S402, S403, S404, S405, S406and S407).

Referring toFIG.5, a first wafer101is provided according to step S401inFIG.4. In some embodiments, the first wafer101includes a first substrate101a, a first dielectric layer101bunder the first substrate101a, and a first interconnect structure101csurrounded by the first dielectric layer101b. In some embodiments, the first substrate101ais a semiconductive substrate. In some embodiments, the first dielectric layer101bis formed under the first substrate101aby deposition, chemical vapor deposition (CVD) or another suitable operation.

In some embodiments, the first interconnect structure101cincludes a first conductive pad101f, a third conductive pad101dand a first via101ebetween the first conductive pad101fand the third conductive pad101d. In some embodiments, the first conductive pad101fis formed by removing a portion of the first dielectric layer101bto form a recess and disposing a conductive material to fill the recess to form the first conductive pad101fIn some embodiments, the conductive material is disposed by electroplating, sputtering or another suitable operation. In some embodiments, the third conductive pad101dis formed under the first conductive pad101f, electrically connected to the first conductive pad101f, and at least partially exposed through the first dielectric layer101b.

In some embodiments, the first wafer101, the first substrate101a, the first dielectric layer101b, the first interconnect structure101c, the first conductive pad101f, the third conductive pad101dand the first via101ehave configurations similar to those described above or illustrated inFIG.1. In some embodiments, the first wafer101has a first surface101gand a second untreated surface101h′ opposite to the first surface101g. In some embodiments, the second untreated surface101h′ becomes a second surface101hafter grinding of the first substrate101aas shown inFIG.6, so that a thickness of the first substrate101ais reduced. In some embodiments, the thickness of the first substrate101ais reduced by grinding, etching, chemical mechanical planarization (CMP) or another suitable operation.

Referring toFIG.7, a first passivation layer102is disposed over the first substrate101aaccording to step S402inFIG.4. In some embodiments, the grinding of the first substrate101aas shown inFIG.6is performed prior to the disposing of the first passivation layer102. In some embodiments, the first passivation layer102is formed by deposition, CVD or another suitable operation. In some embodiments, the first passivation layer102has a configuration similar to that described above or illustrated inFIG.1.

Referring toFIG.8, portions of the first dielectric layer101b, the first substrate101aand the first passivation layer102are removed to form a first opening107according to step S403inFIG.4. In some embodiments, the first opening107exposes a portion of the first conductive pad101fIn some embodiments, the portions of the first dielectric layer101b, the first substrate101aand the first passivation layer102are removed by etching or any other suitable process. In some embodiments, the first opening107has a configuration similar to that described above or illustrated inFIG.1.

In some embodiments, a first dielectric liner103is formed within the first opening107as shown inFIGS.9and10. In some embodiments, the first dielectric liner103is formed by disposing a dielectric liner material103′ over the first passivation layer102and the first conductive pad101fand within the first opening107as shown inFIG.9, and then removing the dielectric liner material103′ over the first passivation layer102and the first conductive pad101fto form the first dielectric liner103as shown inFIG.10. In some embodiments, the dielectric liner material103′ is disposed by deposition, atomic layer deposition (ALD), CVD or another suitable process. In some embodiments, the dielectric liner material103′ includes oxide or the like. In some embodiments, the first conductive pad101fis at least partially exposed through the first dielectric liner103.

In some embodiments, a first conductive barrier layer material104′ is disposed over the first passivation layer102, conformal to the first dielectric liner103and within the first opening107as shown inFIG.11. In some embodiments, the first conductive barrier layer material104′ is disposed by ALD, CVD or the like. In some embodiments, the first conductive barrier layer material104′ includes titanium, titanium nitride, tantalum, tantalum nitride, nickel or the like.

In some embodiments, after the disposing of the first conductive barrier layer material104′, a seed layer is disposed over the first conductive barrier layer material104′. In some embodiments, the seed layer is disposed by sputtering or another suitable operation. In some embodiments, the seed layer includes titanium, copper, nickel, gold or the like.

Referring toFIG.12, a first conductive material105a′ is disposed within the first opening107according to step S404inFIG.4. In some embodiments, the first conductive material105a′ is disposed conformal to the first conductive barrier layer material104′. In some embodiments, the first conductive material105a′ is disposed by electroplating or another suitable operation. In some embodiments, the first conductive material105a′ includes gold, silver, copper, nickel, tungsten, aluminum, tin, alloys thereof or the like. In some embodiments, the disposing of the first dielectric liner103conformal to the first opening107is performed prior to the disposing of the first conductive material105a′.

Referring toFIG.13, a first elastic material106′ is disposed within the first opening107and surrounded by the first conductive material105a′ according to step S405inFIG.4. In some embodiments, the first elastic material106′ is disposed over and surrounded by the first conductive material105a′. In some embodiments, the first elastic material106′ is disposed by deposition or any other suitable process. In some embodiments, the first elastic material106′ includes organic material. In some embodiments, the first elastic material106′ includes polymer, resin, epoxy or the like. In some embodiments, the first elastic material106′ is flexible and compressible.

In some embodiments, after the disposing of the first conductive material105a′ and the first elastic material106′, portions of the first conductive material105a′ and the first elastic material106′ disposed over the first passivation layer102are removed as shown inFIG.14. In some embodiments, the portions of the first conductive material105a′ and the first elastic material106′ disposed over the first passivation layer102are removed by planarization, chemical mechanical polishing (CMP), etching or any other suitable process. In some embodiments, the removal of the portions of the first conductive material105a′ and the first elastic material106′ disposed over the first passivation layer102is terminated when the first conductive barrier layer104′ is exposed.

Referring toFIG.15, portions of the first conductive material105a′ and the first elastic material106′ adjacent to an end of the first opening107are removed according to step S406inFIG.4. In some embodiments, a first elastic member106is formed after the removal of the portions of the first conductive material105a′ and the first elastic material106′ adjacent to an end of the first opening107. In some embodiments, the portions of the first conductive material105a′ and the first elastic material106′ adjacent to an end of the first opening107are removed by an etch-back process or any other suitable process.

Referring toFIGS.16and17, a second conductive material105b′ is disposed over the first elastic member106and the first conductive material105a′ according to step S407inFIG.4. In some embodiments, the second conductive material105b′ is disposed over the first passivation layer102, the first elastic member106and the first conductive material105a′ and within the first opening107as shown inFIG.16.

In some embodiments, the second conductive material105b′ is disposed by electroplating or another suitable operation. In some embodiments, the second conductive material105b′ includes gold, silver, copper, nickel, tungsten, aluminum, tin, alloys thereof or the like. In some embodiments, the first conductive material105a′ and the second conductive material105b′ include a same material.

In some embodiments, after the disposing of the second conductive material105b′ as shown inFIG.16, the second conductive material105b′ over the first passivation layer102is removed by planarization, CMP, etching or any other suitable process as shown inFIG.17. In some embodiments, the first conductive barrier layer material104′ over the first passivation layer102is also removed. In some embodiments, the first conductive via105surrounds the first elastic member106. In some embodiments, the first conductive via105and the first elastic member106have configurations similar to those described above or illustrated inFIG.1. In some embodiments, the first semiconductor structure100as shown inFIG.1is formed as shown inFIG.17.

FIG.18is a flow diagram illustrating a method S500of manufacturing the second semiconductor structure200or the third semiconductor structure300in accordance with some embodiments of the present disclosure, andFIGS.19to28illustrate cross-sectional views of intermediate stages in the formation of the second semiconductor structure200or the third semiconductor structure300in accordance with some embodiments of the present disclosure.

The stages shown inFIGS.19to28are also illustrated schematically in the flow diagram inFIG.18. In the following discussion, the fabrication stages shown inFIGS.19to28are discussed in reference to the process steps shown inFIG.18. The method S500includes a number of operations and the description and illustration are not deemed as a limitation to the sequence of the operations. The method S500includes a number of steps (S401, S402, S403, S404, S405, S406, S407, S408, S409, S410, S411, S412, S413, S414and S415). The steps S401to S407of the method S400are shown in the flow diagram inFIG.4and described above with reference toFIGS.5to17; repeated descriptions of such steps are omitted. In some embodiments, after completion of the method S400, the steps S408to S415are implemented.

Referring toFIG.19, a second wafer201is provided according to step S408inFIG.18. In some embodiments, the step S408is similar to the step S401. In some embodiments, the second wafer201includes a second substrate201a, a second dielectric layer201bunder the second substrate201a, and a second interconnect structure201csurrounded by the second dielectric layer201b. In some embodiments, the second interconnect structure201cincludes a second conductive pad201f, a fourth conductive pad201dand a second via201ebetween the second conductive pad201fand the fourth conductive pad201d.

In some embodiments, the fourth conductive pad201dis formed under the second conductive pad201f, wherein the fourth conductive pad201dis electrically connected to the second conductive pad201fand at least partially exposed through the second dielectric layer201b. In some embodiments, a width of the second conductive pad201fis substantially greater than a width of the fourth conductive pad201d.

Referring toFIG.20, the second dielectric layer201bis bonded over the first passivation layer102according to step S409inFIG.18. In some embodiments, the bonding of the second dielectric layer201bover the first passivation layer102is implemented after the formation of the first conductive via105and the first elastic member106. In some embodiments, the first passivation layer102is bonded to the second dielectric layer201b, and the first conductive via105is bonded to the fourth conductive pad201d. In some embodiments, the first wafer101and the second wafer102are bonded by an oxide-to-oxide bonding technique or another suitable operation.

In some embodiments, the second wafer201has a third surface201gand a fourth untreated surface201h′ opposite to the third surface201g. In some embodiments, the fourth untreated surface201h′ becomes a fourth surface201hafter grinding of the second substrate201aas shown inFIG.21, so that a thickness of the second substrate201ais reduced. In some embodiments, the thickness of the second substrate201ais reduced after the bonding of the first passivation layer102to the second dielectric layer201b.

Referring toFIG.22, a second passivation layer202is disposed over the second substrate201aaccording to step S410inFIG.18. In some embodiments, the step S410is similar to the step S402.

Referring toFIG.23, portions of the second dielectric layer201b, the second substrate201aand the second passivation layer202are removed to form a second opening207exposing a portion of the second conductive pad201faccording to step S411inFIG.18. In some embodiments, the step S411is similar to the step S403.

Referring toFIG.24, a second dielectric liner203is formed within the second opening207as shown inFIG.24. In some embodiments, the second dielectric liner203is formed by steps similar to those of the formation of the first dielectric liner103.

In some embodiments, a second conductive barrier layer material204′ is disposed over the second passivation layer202, conformal to the second dielectric liner203and within the second opening207as shown inFIG.24. In some embodiments, materials and formation of the second conductive barrier layer material204′ are similar to those of the first conductive barrier layer material104′.

In some embodiments, after the disposing of the second conductive barrier layer material204′, a seed layer is disposed over the second conductive barrier layer material204′. In some embodiments, the seed layer is disposed by sputtering or another suitable operation. In some embodiments, the seed layer includes titanium, copper, nickel, gold or the like.

Referring toFIG.24, a third conductive material205a′ is disposed within the second opening207according to step S412inFIG.18. In some embodiments, the step S412is similar to the step S404.

Referring toFIG.25, a second elastic material206′ is disposed within the second opening207and surrounded by the third conductive material205a′ according to step S413inFIG.18. In some embodiments, the step S413is similar to the step S405.

Referring toFIG.26, portions of the third conductive material205a′ and the second elastic material206′ over the second conductive barrier layer material204′ and adjacent to an end of the second opening207are removed to form a second elastic member206according to step S414inFIG.18. In some embodiments, the step S414is similar to the step S406.

Referring toFIGS.27and28, a fourth conductive material205b′ is disposed over the second elastic member206, the third conductive material205a′, and the second conductive barrier layer material204′ to form a second conductive via205according to step S415inFIG.18. In some embodiments, the step S415is similar to the step S407.

In some embodiments, after the disposing of the fourth conductive material205b′ as shown inFIG.27, the fourth conductive material205b′ over the second passivation layer202is removed by planarization, CMP, etching or any other suitable process as shown inFIG.28. In some embodiments, the second conductive barrier layer material204′ over the second passivation layer202is also removed. In some embodiments, the second conductive via205surrounds the second elastic member206. In some embodiments, the second semiconductor structure200ofFIG.2is formed as shown inFIG.28.

In conclusion, because an elastic member capable of absorbing force is disposed within a via, a bonding force generated and applied over the via during a wafer-to-wafer bonding process can be effectively absorbed by the elastic member. Further, the elastic member is also capable of absorbing thermal stress from adjacent components such as the via during the bonding process. Therefore, formation of cracks within a wafer's bonded structure or damages to the wafer's bonded structure can be minimized or prevented.

One aspect of the present disclosure provides a semiconductor structure. The semiconductor structure includes a wafer including a substrate, a dielectric layer under the substrate, and a conductive pad surrounded by the dielectric layer; a passivation layer disposed over the substrate; a conductive via extending from the conductive pad through the substrate and the passivation layer and partially through the dielectric layer; and an elastic member disposed within the conductive via.

Another aspect of the present disclosure provides a semiconductor structure. The semiconductor structure includes a first wafer including a first substrate, a first dielectric layer under the first substrate, and a first conductive pad surrounded by the first dielectric layer; a first passivation layer disposed over the first substrate; a first conductive via extending from the first conductive pad through the first substrate and the first passivation layer and partially through the first dielectric layer; a first elastic member disposed within the first conductive via; a second wafer including a second dielectric layer bonded over the first passivation layer, a second substrate over the second dielectric layer, and a second conductive pad surrounded by the second dielectric layer; a second passivation layer disposed over the second substrate; a second conductive via extending from the second conductive pad through the second substrate and the second passivation layer and partially through the second dielectric layer; and a second elastic member disposed within the second conductive via.

Another aspect of the present disclosure provides a method of manufacturing a semiconductor structure. The method includes steps of providing a first wafer including a first substrate, a first dielectric layer under the first substrate, and a first conductive pad surrounded by the first dielectric layer; disposing a first passivation layer over the first substrate; removing portions of the first dielectric layer, the first substrate and the first passivation layer to form a first opening exposing a portion of the first conductive pad; disposing a first conductive material within the first opening; disposing a first elastic material within the first opening and surrounded by the first conductive material; removing portions of the first conductive material and the first elastic material adjacent to an end of the first opening to form a first elastic member; and disposing a second conductive material over the first elastic member and the first conductive material to form a first conductive via, wherein the first conductive via surrounds the first elastic member.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein, may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods and steps.