Patent ID: 12236129

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Various exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some exemplary embodiments are shown. In the drawings, like numerals refer to like elements throughout. Repeated descriptions may be omitted as redundant.

FIG.1is a block diagram illustrating a memory system according to exemplary embodiments, andFIG.2is a flowchart illustrating a method of operating a memory system according to exemplary embodiments.

Referring toFIG.1, a memory system10includes a host device20and a memory module100. The host device20may include a memory controller25configured to control the memory module100.

The memory module100may include a control device500, a plurality of semiconductor memory devices MEM200, a serial presence detect (SPD) chip180, a power management integrated circuit (PMIC)185. In some exemplary embodiments, the control device500may be a registered clock driver (RCD). The semiconductor memory devices200may be referred to as semiconductor memory chips.

The control device500may control the semiconductor memory devices200and the PMIC185under control of the memory controller25. For example, the control device500may receive an address ADDR, a command CMD, a reset signal RST and a clock signal CK from the memory controller25. In response to received signals, the control device500may control the semiconductor memory devices200through a first control signal CTL1and may control the PMIC185through a second control signal CTL2.

In response to received signals, the control device500may control the semiconductor memory devices200such that data received through a data signal DQ and a data strobe signal DQS is written in the semiconductor memory devices200or such that data stored in the semiconductor memory devices200is outputted through the data signal DQ and the data strobe signal DQS.

For example, the control device500may transmit the address ADDR, the command CMD, the reset signal RST and the clock signal CK from the memory controller25to the semiconductor memory devices200as the first control signal CTL1.

The semiconductor memory devices200may store data received through the data signal DQ and the data strobe signal DQS under control of the control device500. Alternatively, the semiconductor memory devices200may output the written data through the data signal DQ and the data strobe signal DQS under control of the control device500.

The semiconductor memory devices200may include a volatile memory device such as a dynamic random-access memory (DRAM), a static RAM (SRAM), or a synchronous DRAM (SDRAM). In some exemplary embodiments, the semiconductor memory devices200may be DRAM-based volatile memory devices.

The SPD chip180may be a programmable read only memory (e.g., EEPROM). The SPD chip180may include initial information or device information DI of the memory module100. In some exemplary embodiments, the SPD chip180may include the initial information or the device information DI such as a module form, a module configuration, a storage capacity, a module type, an execution environment, or the like for the memory module100.

When the memory system10including the memory module100is booted up, the host device20may read the device information DI from the SPD chip180and may recognize the memory module100based on the device information DI. The host device20may control the memory module100based on the device information DI from the SPD chip180. For example, the host device20may recognize a type of the semiconductor memory devices200included in the memory module100based on the device information DI from the SPD chip180.

In some exemplary embodiments, the SPD chip180may communicate with the host device20through a serial bus. For example, the host device20may exchange a signal with the SPD chip180through the serial bus. The SPD chip180may also communicate with the control device500through the serial bus. The serial bus may include at least one of 2-line serial buses such as an inter-integrated circuit (I2C), a system management bus (SMBus), a power management bus (PMBus), an intelligent platform management interface (IPMI), a management component transport protocol (MCTP), or the like.

The PMIC185receives an input voltage VIN, generates a power supply voltage VDD based on the input voltage VIN, and provides the power supply voltage VDD to the semiconductor memory devices200and/or the control device500. The semiconductor memory devices200operate based on the power supply voltage VDD.

When the memory system10including the memory module100is booted up, the semiconductor memory devices200or the control device500may generate a power-up signal that is activated when the level of the power supply voltage VDD provided to the PMIC185increases to a higher level than a reference level.

The memory module100may include a module temperature sensor TSOD. In some exemplary embodiments, as illustrated inFIG.1, the module temperature sensor TSOD may be disposed in the SPD chip180that stores information on the memory module100. In some exemplary embodiments, the module temperature sensor TSOD may be disposed on a proper position of the memory module100outside the SPD chip180.

The plurality of semiconductor memory devices100may respectively include a plurality of temperature measurement circuits TMMS configured to measure a plurality of internal temperatures respectively corresponding to the plurality of semiconductor memory devices100. As will be described below with reference toFIGS.21and22, each temperature measurement circuit TMMS may measure an internal temperature of each semiconductor memory device and generate a temperature code TCODE corresponding to the internal temperature. The temperature measurement circuit TMMS may include an on-chip temperature sensor that is integrated in the same semiconductor die of the semiconductor memory device. Using the on-chip temperature sensor, the real internal temperature of the semiconductor memory device may be measured exactly and the thermal throttling of the memory system10may be performed efficiently by reflecting the exact internal temperature.

Referring toFIGS.1and2, a module temperature may be measured using the module temperature sensor TSOD that is mounted on the memory module100(S100). The plurality of internal temperatures respectively corresponding to the plurality of semiconductor memory devices200may be measured using the plurality of temperature measurement circuits TMMS that are respectively included in the plurality of semiconductor memory devices200(S200).

The memory system10may generate a reference offset value based on the module temperature and the plurality of internal temperatures (S300). A thermal manager THC in the host device20may perform the thermal throttling of the memory module100based on the reference offset value and the module temperature (S400). The thermal manager THC may be implemented as software, hardware or a combination thereof.FIG.1illustrates a non-limiting example in which the thermal manager THC is included in the memory controller25but exemplary embodiments are not limited thereto. The thermal throttling by the thermal manager THC will be further described below with reference toFIG.3.

FIG.3is a diagram illustrating an exemplary embodiment of thermal throttling of a memory system according to such exemplary embodiments.

Referring toFIG.3, a memory controller or a host device in a memory system may perform thermal throttling or temperature throttling based on several reference temperatures such as a low temperature TL, a middle temperature TM, a high temperature TH, and so on. A first temperature throttling level THRT_1, a second temperature throttling level THRT_2and a third temperature throttling level THRT_3may be applied for temperature ranges between the reference temperature TL, TM and TH. The semiconductor memory device may be controlled to lower the power consumption when the operational temperature To exceed the reference temperatures TL, TM and TH. The reduction of power consumption may be implemented by reducing an operational frequency of the semiconductor memory device and/or a bandwidth for transferring data between the semiconductor memory device and the memory controller. As the power consumption is lowered, the operational temperature To of the semiconductor memory device may be lowered.

The semiconductor memory device may perform a double speed (×2) refresh operation when the operational temperature To exceeds the low temperature TL, based on information from an internal sensor. Such control of the refresh operation is not for reducing power consumption of the semiconductor memory device but rather for preventing data loss stored in the memory cells.

In addition, the risk temperature TR, which is higher than the reference temperatures for the temperature throttling, may be set for preventing physical damage to the semiconductor memory device when the operational temperature To exceeds the risk temperature TR. For example, the risk temperature TR may be set to about 100° C. When the operational temperature To exceeds the risk temperature TR, the operation of the semiconductor memory device may be controlled to rapidly reduce power consumption of the semiconductor memory device, thereby reducing the operational temperature To.

However, the temperature throttling at the system level is performed based on information provided from an external temperature sensor such as the TSOD that cannot reflect the real operational temperature To of the semiconductor memory device.

Conventionally, to reflect the real temperature of the semiconductor memory device, the thermal throttling has been performed such that the operational temperature is corrected by applying offset values of the basic input and output system (BIOS) provided by a host device. In this case, such fixed offset values may not reflect the exact operational temperature that depends on thermal characteristics, such as memory capacity, cooling environments (e.g., airflow, interference) of a memory system. If the thermal throttling is performed based on inexact temperature information, the probability of physical damage to the semiconductor memory device may be increased.

In contrast, the reference offset value that is provided by comparing the module temperature and the internal temperatures of the semiconductor memory devices may reflect the real thermal environments. The operational temperature To for the thermal throttling may correspond to a sum of the module temperature and the reference offset value. In some exemplary embodiments, the reference offset value may correspond to the maximum internal temperature of the internal temperatures subtracted by the module temperature. In this case, the reference offset value may reflect the worst thermal environment and the safe operational environment may be implemented regardless of system dependency. Particularly, physical damage of the high-capacity memory module that is vulnerable to heat may be prevented efficiently.

As such, the memory module, the memory system and the method of operating a memory system according to exemplary embodiments may reduce physical damage to the semiconductor memory devices and enhance the performance and lifetime of the memory module and the memory system by dynamically generating the reference offset value based on the real internal temperatures of the semiconductor memory devices to perform thermal throttling based on the reference offset value.

FIG.4is a diagram illustrating a memory module according to exemplary embodiments.

Referring toFIG.4, a memory module100includes a control device500disposed (or mounted) in a circuit board101, a plurality of semiconductor memory devices201a˜201e,202a˜202e,203a˜203e, and204a˜204e, a plurality of data buffers (DB)141˜145and151˜155, module resistance units (MRU)160and170, the SPD chip180, and the PMIC185.

Here, the circuit board101, which is a printed circuit board, may extend in a second direction D2, perpendicular to a first direction D1, between a first edge portion103and a second edge portion105. The first edge portion103and the second edge portion105may extend in the first direction D1.

The control device500may be disposed on a center of the circuit board101. The plurality of semiconductor memory devices201a˜201e,202a˜202e,203a˜203e, and204a˜204emay be arranged in a plurality of rows between the control device500and the first edge portion103and between the control device500and the second edge portion105.

The semiconductor memory devices201a˜201eand202a˜202emay be arranged along a plurality of rows between the control device500and the first edge portion103. The semiconductor memory devices203a˜203e, and204a˜204emay be arranged along a plurality of rows between the control device500and the second edge portion105. A portion of the semiconductor memory devices201a˜201eand202a˜202emay be an error correction code (ECC) memory device. The ECC memory device may perform an ECC encoding operation to generate parity bits about data to be written at memory cells of the plurality of semiconductor memory devices201a˜201e,202a˜202e,203a˜203e, and204a˜204e, and an ECC decoding operation to correct an error occurring in the data read from the memory cells.

Each of the plurality of semiconductor memory devices201a˜201e,202a˜202e,203a˜203e, and204a˜204emay be coupled to a corresponding one of the data buffers (DB)141˜145and151˜155through a data transmission line for receiving/transmitting the data signal DQ and the data strobe signal DQS.

The control device500may provide a command/address signal (e.g., CA) to the semiconductor memory devices201a˜201ethrough a command/address transmission line161and may provide a command/address signal to the semiconductor memory devices202a˜202ethrough a command/address transmission line163. In addition, the control device500may provide a command/address signal to the semiconductor memory devices203a˜203ethrough a command/address transmission line171and may provide a command/address signal to the semiconductor memory devices204a˜204ethrough a command/address transmission line173.

The command/address transmission lines161and163may be connected in common to the module resistance unit (MRU)160disposed to be adjacent to the first edge portion103, and the command/address transmission lines171and173may be connected in common to the module resistance unit (MRU)170disposed to be adjacent to the second edge portion105. Each of the module resistance units (MRUs)160and170may include a termination resistor Rtt/2 connected to a termination voltage Vtt. In this case, the arrangement of the module resistance units (MRUs)160and170may reduce the number of the module resistance units, thus reducing an area where termination resistors are disposed.

In some exemplary embodiments, each of the plurality of semiconductor memory devices201a˜201e,202a˜202e,203a˜203e, and204a˜204emay be a DDR5 SDRAM.

The SPD chip180may be disposed to be adjacent to the control device500, and the PMIC185may be disposed between the semiconductor memory device203eand the second edge portion105. The PMIC185may generate the power supply voltage VDD based on the input voltage VIN and may provide the power supply voltage VDD to the semiconductor memory devices201a˜201e,202a˜202e,203a˜203e, and204a˜204e.

AlthoughFIG.4illustrates the PMIC185as being disposed to be adjacent to the second edge portion105, exemplary embodiments are not limited thereto, and in some exemplary embodiments, the PMIC185may be disposed in a central portion of the circuit board101to be adjacent to the control device500.

Exemplary embodiments of configuration and operations of the memory module associated with the dynamic thermal throttling according to such exemplary embodiments will be described in detail with reference toFIGS.8through17.

FIG.5is a block diagram illustrating a semiconductor memory device according to exemplary embodiments.

Referring toFIG.5, a semiconductor memory device400may include a command control logic410, an address register420, a bank control logic430, a row selection circuit460(or row decoder), a column decoder470, a memory cell array480, a sense amplifier unit485, an input/output (I/O) gating circuit490, a data input/output (I/O) buffer495, refresh controller100, a temperature measurement circuit TMMS and a chip offset generation circuit OSG. According to exemplary embodiments, the chip offset generation circuit OSG may be omitted according to some exemplary embodiments as will be described below.

The memory cell array480may include a plurality of bank arrays480a˜480h. The row selection circuit460may include a plurality of bank row selection circuits460a˜460hrespectively coupled to the bank arrays480a˜480h. The column decoder470may include a plurality of bank column decoders470a˜470hrespectively coupled to the bank arrays480a˜480h. The sense amplifier unit485may include a plurality of bank sense amplifiers485a˜485hrespectively coupled to the bank arrays480a˜480h.

The address register420may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller200. The address register420may provide the received bank address BANK_ADDR to the bank control logic430, may provide the received row address ROW_ADDR to the row selection circuit460, and may provide the received column address COL_ADDR to the column decoder470.

The bank control logic430may generate bank control signals in response to the bank address BANK_ADDR. One of the bank row selection circuits460a˜460hcorresponding to the bank address BANK_ADDR may be activated in response to the bank control signals, and one of the bank column decoders470a˜470hcorresponding to the bank address BANK_ADDR may be activated in response to the bank control signals.

The row address ROW_ADDR from the address register420may be applied to the bank row selection circuits460a˜460h. The activated one of the bank row selection circuits460a˜460hmay decode the row address ROW_ADDR, and may activate a wordline corresponding to the row address ROW_ADDR. For example, the activated bank row selection circuit460may apply a wordline driving voltage to the wordline corresponding to the row address ROW_ADDR.

The column decoder470may include a column address latch. The column address latch may receive the column address COL_ADDR from the address register420, and may temporarily store the received column address COL_ADDR. In some exemplary embodiments, in a burst mode, the column address latch may generate column addresses that increment from the received column address COL_ADDR. The column address latch may apply the temporarily stored or generated column address to the bank column decoders470a˜470h.

The activated one of the bank column decoders470a˜470hmay decode the column address COL_ADDR, and may control the I/O gating circuit490in order to output data corresponding to the column address COL_ADDR.

The I/O gating circuit490may include circuitry for gating input/output data. The I/O gating circuit490may further include read data latches for storing data that is output from the bank arrays480a˜480h, and write drivers for writing data to the bank arrays480a˜480h.

Data to be read from one bank array of the bank arrays480a˜480hmay be sensed by one of the bank sense amplifiers485a˜485hcoupled to the one bank array from which the data is to be read, and may be stored in the read data latches. The data stored in the read data latches may be provided to the memory controller200via the data I/O buffer495. Data DQ to be written in one bank array of the bank arrays480a˜480hmay be provided to the data I/O buffer495from the memory controller200. The write driver may write the data DQ in one bank array of the bank arrays480a˜480h.

The command control logic410may control operations of the semiconductor memory device400. For example, the command control logic410may generate control signals for the semiconductor memory device400in order to perform a write operation, a read operation, or a refresh operation. The command control logic410may generate internal command signals such as an active signal IACT, a precharge signal IPRE, a refresh signal IREF, a read signal IRD, a write signal IWR, etc., based on commands CMD transferred from the memory controller200inFIG.3. The command control logic410may include a command decoder411that decodes the commands CMD received from the memory controller200and a mode register set412that sets an operation mode of the semiconductor memory device400.

AlthoughFIG.5illustrates the command control logic410and the address register420as being distinct from each other, the command control logic410and the address register420may be implemented as a single integrated circuit. In addition, althoughFIG.5illustrates the command CMD and the address ADDR as being provided as distinct signals, the command CMD and the address ADDR may be provided as a combined signal, e.g., as specified by DDR5, HBM and LPDDR5 standards.

The temperature measurement circuit TMMS included in each semiconductor memory device400may measure an internal temperature Tj of each semiconductor memory device400to generate a temperature code TCODE corresponding to each internal temperature Tj. The chip offset generation circuit OSG may generate a chip offset value corresponding to each internal temperature Tj subtracted by the module temperature. Exemplary embodiments of thermal throttling using the chip offset generation circuit OSG will be described below with reference toFIGS.8through12.

FIG.6is a diagram illustrating an exemplary embodiment of a bank array included in the semiconductor memory device ofFIG.5.

Referring toFIG.6, a bank array310includes a plurality of word-lines WL1˜WL2m(where m is a natural number greater than two), a plurality of bit-lines BTL1˜BTL2n(where n is a natural number greater than two), and a plurality of memory cells MCs disposed near intersections between the word-lines WL1˜WL2mand the bit-lines BTL1˜BTL2n. In some exemplary embodiments, each of the plurality of memory cells MCs may include a DRAM cell structure as illustrated inFIG.6. The plurality of word-lines WL1˜WL2mto which the plurality of memory cells MCs are connected may be referred to as rows of the bank array310and the plurality of bit-lines BL1˜BL3nto which the plurality of memory cells MCs are connected may be referred to as columns of the bank array310.

FIG.7is a flowchart illustrating a method of operating a memory system according to exemplary embodiments.

Referring toFIGS.1and7, the memory controller25may receive the module temperature, that is, a present module temperature Tspd from the module temperature sensor TSOD (S11). In some exemplary embodiments, the memory controller25may periodically receive the module temperature from the module temperature sensor TSOD.

The memory controller25may compare a difference |Tspd′−Tspd| between the previous module temperature Tspd′ and the present module temperature Tspd with a reference value RV (S12).

When the difference |Tspd′−Tspd| is greater than the reference value RV (S12: YES), the memory controller25may update the reference offset value MOFS (S13). Exemplary embodiments for updating the reference offset value MOFS will be described below. The thermal manager THC in the host device20may perform the thermal throttling as described with reference toFIG.3based on the present module temperature Tspd and the updated reference offset value MOFS (S14).

When the difference |Tspd′−Tspd| is not greater than the reference value RV (S12: NO), the memory controller25may not update the reference offset value MOFS and the thermal manager THC may perform the thermal throttling based on the reference offset value MOFS that is determined previously.

As such, the memory controller25may monitor the module temperature Tspd in realtime and determine whether to update the reference offset value MOFS based on the change of the module temperature Tspd.

FIG.8is a diagram illustrating an exemplary embodiment of an offset circuit included in a memory system according to such exemplary embodiments.

Referring toFIG.8, an offset circuit600may include a temperature measurement circuit TMMS and a chip offset generation circuit OSG610that are included in each of a plurality of semiconductor memory devices, that is, first through n-th semiconductor memory devices MEM1˜MEMn. The offset circuit600may further include a selector SEL620. In some exemplary embodiments, the selector620may be included in the memory controller25.

Each chip offset generation circuit610may include a register REG and a calculation logic circuit CLG. The register REG may store each internal temperature, the module temperature Tspd and each chip offset value. The calculation logic circuit CLG may subtract the module temperature Tspd from each internal temperature to output each chip offset value.

For example, the chip offset generation circuit610in the first semiconductor memory device MEM1may generate the first chip offset value OFS1corresponding to the first internal temperature Ta subtracted by the module temperature Tspd. As such, the chip offset generation circuits610respectively included in the plurality of semiconductor memory devices MEM1˜MEMn may generate the plurality of chip offset values OFS1˜OFSn respectively corresponding to the plurality of semiconductor memory devices MEM1˜MEMn.

The selector620may receive the plurality of chip offset values OFS1˜OFSn from the plurality of semiconductor memory devices MEM1˜MEMn and select, as the reference offset value MOFS, the maximum chip offset value of the plurality of chip offset values OFS1˜OFSn.

FIG.9is a diagram illustrating a memory system according to exemplary embodiments, andFIG.10is a diagram illustrating an operation sequence of the memory system ofFIG.9.

Referring toFIG.9, a memory system10amay include a memory module100aand a memory controller25a. The memory module100amay include a module substrate, semiconductor memory device (or memory chips)401a˜401h, a control device RCD500aand a module temperature sensor TSOD that are mounted on the module substrate.FIG.9illustrates eight semiconductor memory devices as an example, and the number of the semiconductor memory devices mounted on the module substrate may be determined variously. Hereinafter the repeated descriptions withFIG.4may be omitted as redundant.

The control device500amay receive the command and address information CMD/ADD from the memory controller25avia the control bus1220, then buffers and re-drives the command and address information CMD/ADD. The command and address information CMD/ADD provided by the control device500amay be communicated to the respective semiconductor memory devices401a˜401hvia the first bus1230.

Each of the semiconductor memory devices chips401a˜401his connected to the memory controller25avia a corresponding one of a plurality of data buses1210a˜1210h, whereby each semiconductor memory device is directly wired to the memory controller25afor receipt and transfer of data signals DQ and data strobe signals DQS. Each of the semiconductor memory devices401a˜401hmay receive the write data signal DQ and the data strobe signal DQS from the memory controller25avia a corresponding one of the data buses1210a˜1210hrespectively connected to the semiconductor memory devices401a˜401h, and the read data signal DQ and the data strobe signal DQS retrieved from each of the semiconductor memory devices401a˜401hmay also be transferred to the memory controller25avia the data buses1210a˜1210hand1210.

As illustrated inFIG.9, each of the semiconductor memory devices401a˜401hmay include the temperature measurement circuit TMMS and the chip offset generation circuit OSG. The memory controller25amay receive the module temperature Tspd from the module temperature sensor TSOD and transfer the module temperature Tspd to the semiconductor memory devices401a˜401h.

The memory controller25amay receive the chip offset values OFSa˜OFSh respectively from the semiconductor memory devices401a˜401h. As described above, the memory controller25amay select the maximum chip offset value of the chip offset values OFSa˜OFSh where the maximum chip offset value corresponds to the reference offset value MOFS. The thermal manager THC may perform the thermal throttling based on the reference offset value MOFS.

Referring toFIGS.9and10, the memory controller25amay transmit a first request REQ1to request the transfer of the module temperature Tspd to the control device RCD (S21), and the module temperature Tspd may be transferred to the memory controller25aunder control of the control device RCD (S22).

After that, when the memory controller25amay update the reference offset value MOFS as described with reference toFIG.7, the memory controller25amay transmit a second request REQ2to request the transfer of the chip offset values OFSa˜OFSh to the control device RCD (S23). In addition, the memory controller25amay transfer the module temperature Tspd with the second request REQ2to the semiconductor memory devices401a˜401h(S24).

The chip offset generation circuits OSG respectively included in the semiconductor memory devices401a˜401hmay calculate the chip offset values OFSa˜OFSh (S25) and transfer the chip offset values OFSa˜OFSh to the memory controller25a(S26).

The memory controller25amay select, as the reference offset value MOFS, the maximum chip offset value of the chip offset values OFSa˜OFSh (S27). The thermal manager THC of the memory controller25amay perform the thermal throttling or thermal control based on the module temperature Tspd and the reference offset value MOFS (S28).

FIG.11is a diagram illustrating a memory system according to exemplary embodiments, andFIG.12is a diagram illustrating an operation sequence of the memory system ofFIG.11.

Referring toFIG.11, a memory system10bmay include a memory module100band a memory controller25b. The memory module100bmay include a module substrate, semiconductor memory device (or memory chips)402a˜402h, a control device RCD500band a module temperature sensor TSOD that are mounted on the module substrate.FIG.11shows eight semiconductor memory devices as an example, however the number of the semiconductor memory devices mounted on the module substrate may be determined variously. Hereinafter the repeated descriptions withFIG.4may be omitted as redundant.

The control device500bmay receive the command and address information CMD/ADD from the memory controller25bvia the control bus1220, then buffers and re-drives the command and address information CMD/ADD. The command and address information CMD/ADD provided by the control device500bmay be communicated to the respective semiconductor memory devices402a˜402hvia the first bus1230.

Each of the semiconductor memory devices chips402a˜402his connected to the memory controller25bvia a corresponding one of a plurality of data buses1210a˜1210h, whereby each semiconductor memory device is directly wired to the memory controller25bfor receipt and transfer of data signals DQ and data strobe signals DQS. Each of the semiconductor memory devices402a˜402hmay receive the write data signal DQ and the data strobe signal DQS from the memory controller25bvia a corresponding one of the data buses1210a˜1210hrespectively connected to the semiconductor memory devices402a˜402h, and the read data signal DQ and the data strobe signal DQS retrieved from each of the semiconductor memory devices402a˜402hmay also be transferred to the memory controller25bvia the data buses1210a˜1210hand1210.

As illustrated inFIG.11, each of the semiconductor memory devices402a˜402hmay include the temperature measurement circuit TMMS and the chip offset generation circuit OSG. The memory controller25bmay receive the module temperature Tspd from the module temperature sensor TSOD. In comparison with the exemplary embodiments ofFIGS.9and10, the module temperature Tspd may be transferred directly to the semiconductor memory devices402a˜402hthrough internal wirings without passing through the memory controller25b.

The memory controller25bmay receive the chip offset values OFSa˜OFSh respectively from the semiconductor memory devices402a˜402h. As described above, the memory controller25bmay select the maximum chip offset value of the chip offset values OFSa˜OFSh where the maximum chip offset value corresponds to the reference offset value MOFS. The thermal manager THC may perform the thermal throttling based on the reference offset value MOFS.

Referring toFIGS.11and12, the memory controller25bmay transmit a first request REQ1to request the transfer of the module temperature Tspd to the control device RCD (S31), and the module temperature Tspd may be transferred to the memory controller25bunder control of the control device RCD (S32).

After that, when the memory controller25bmay update the reference offset value MOFS as described with reference toFIG.7, the memory controller25bmay transmit a second request REQ2to request the transfer of the chip offset values OFSa˜OFSh to the control device RCD (S33). In this case, the module temperature Tspd may be provided directly to the semiconductor memory devices402a˜402hthrough internal wirings without passing through the memory controller25b(S34).

The chip offset generation circuits OSG respectively included in the semiconductor memory devices402a˜402hmay calculate the chip offset values OFSa˜OFSh (S35) and transfer the chip offset values OFSa˜OFSh to the memory controller25b(S36).

The memory controller25bmay select, as the reference offset value MOFS, the maximum chip offset value of the chip offset values OFSa˜OFSh (S37). The thermal manager THC of the memory controller25bmay perform the thermal throttling or thermal control based on the module temperature Tspd and the reference offset value MOFS (S38).

FIG.13is a diagram illustrating an exemplary embodiment of an offset circuit included in a memory system according to such exemplary embodiments.

Referring toFIG.13, an offset circuit601may include a temperature measurement circuit TMMS that is included in each of a plurality of semiconductor memory devices, that is, first through n-th semiconductor memory devices MEM1˜MEMn. The offset circuit601may further include a selector SEL611and a reference offset generation circuit MOSG621. In some exemplary embodiments, the selector611may be included in the reference offset generation circuit621, and the reference offset generation circuit621including the selector611may be included in the control device of the memory module. In some exemplary embodiments, the reference offset generation circuit621including the selector611may be included in the memory controller.

The selector611may receive the first through n-th internal temperatures T1˜Tn from the temperature measurement circuits TMMS respectively included in the first through n-th semiconductor memory devices MEM1˜MEMn. The selector611may select and output a maximum internal temperature MT of the first through n-th internal temperatures T1˜Tn.

The reference offset generation circuit621may generate the reference offset value MOFS by subtracting the module temperature Tspd from the maximum internal temperature MT.

FIG.14is a diagram illustrating a memory system according to exemplary embodiments, andFIG.15is a diagram illustrating an operation sequence of the memory system ofFIG.14.

Referring toFIG.14, a memory system10cmay include a memory module100cand a memory controller25c. The memory module100cmay include a module substrate, semiconductor memory device (or memory chips)403a˜403h, a control device RCD500cand a module temperature sensor TSOD that are mounted on the module substrate.FIG.14shows eight semiconductor memory devices as an example, however the number of the semiconductor memory devices mounted on the module substrate may be determined variously. Hereinafter the repeated descriptions withFIG.4may be omitted as redundant.

The control device500cmay receive the command and address information CMD/ADD from the memory controller25cvia the control bus1220, then buffers and re-drives the command and address information CMD/ADD. The command and address information CMD/ADD provided by the control device500cmay be communicated to the respective semiconductor memory devices403a˜403hvia the first bus1230.

Each of the semiconductor memory devices chips403a˜403his connected to the memory controller25cvia a corresponding one of a plurality of data buses1210a˜1210h, whereby each semiconductor memory device is directly wired to the memory controller25cfor receipt and transfer of data signals DQ and data strobe signals DQS. Each of the semiconductor memory devices403a˜403hmay receive the write data signal DQ and the data strobe signal DQS from the memory controller25cvia a corresponding one of the data buses1210a˜1210hrespectively connected to the semiconductor memory devices403a˜403h, and the read data signal DQ and the data strobe signal DQS retrieved from each of the semiconductor memory devices403a˜403hmay also be transferred to the memory controller25cvia the data buses1210a˜1210hand1210.

As illustrated inFIG.14, each of the semiconductor memory devices403a˜403hmay include the temperature measurement circuit TMMS and the control device500cmay include the reference offset generation circuit MOSG. The control device500cmay receive the plurality of internal temperatures Ta˜Th respectively from the semiconductor memory device403a˜403hand receive the module temperature Tspd from the module temperature sensor TSOD. In addition, the memory controller25cmay receive the module temperature Tspd from the module temperature sensor TSOD.

The reference offset generation circuit MOSG in the control device500cmay generate the reference offset value MOFS based on the internal temperatures Ta˜Th and the module temperature Tspd, and transfer the reference offset value MOFS to the memory controller25c. The memory controller25cmay perform the thermal throttling based on the reference offset value MOFS provided from the control device500c.

Referring toFIGS.14and15, the memory controller25cmay transmit a first request REQ1to request the transfer of the module temperature Tspd to the control device RCD (S41), and the module temperature Tspd may be transferred to the memory controller25cunder control of the control device RCD (S42).

After that, when the memory controller25cmay update the reference offset value MOFS as described above with reference toFIG.7, the memory controller25cmay transmit a second request REQ2to request the transfer of the reference offset value MOFS to the control device RCD (S43). Under the control of the control device500c, the semiconductor memory devices403a˜403hmay transfer the internal temperatures Ta˜Th to the control device500c.

The reference offset generation circuit MOSG in the control device500cmay calculate the reference offset value MOFS as described with reference toFIG.13(S45), and transfer the reference offset value MOFS to the memory controller25c(S46). The thermal manager THC of the memory controller25cmay perform the thermal throttling or thermal control based on the module temperature Tspd and the reference offset value MOFS (S47).

FIG.16is a diagram illustrating a memory system according to exemplary embodiments, andFIG.17is a diagram illustrating an operation sequence of the memory system ofFIG.16.

Referring toFIG.16, a memory system10dmay include a memory module100dand a memory controller25d. The memory module100dmay include a module substrate, semiconductor memory device (or memory chips)404a˜404h, a control device RCD500dand a module temperature sensor TSOD that are mounted on the module substrate.FIG.16shows eight semiconductor memory devices as an example, however the number of the semiconductor memory devices mounted on the module substrate may be determined variously. Hereinafter the repeated descriptions withFIG.4may be omitted as redundant.

The control device500dmay receive the command and address information CMD/ADD from the memory controller25dvia the control bus1220, then buffers and re-drives the command and address information CMD/ADD. The command and address information CMD/ADD provided by the control device500dmay be communicated to the respective semiconductor memory devices404a˜404hvia the first bus1230.

Each of the semiconductor memory devices chips404a˜404his connected to the memory controller25dvia a corresponding one of a plurality of data buses1210a˜1210h, whereby each semiconductor memory device is directly wired to the memory controller25dfor receipt and transfer of data signals DQ and data strobe signals DQS. Each of the semiconductor memory devices404a˜404hmay receive the write data signal DQ and the data strobe signal DQS from the memory controller25cvia a corresponding one of the data buses1210a˜1210hrespectively connected to the semiconductor memory devices404a˜404h, and the read data signal DQ and the data strobe signal DQS retrieved from each of the semiconductor memory devices404a˜404hmay also be transferred to the memory controller25dvia the data buses1210a˜1210hand1210.

As illustrated inFIG.16, each of the semiconductor memory devices404a˜404hmay include the temperature measurement circuit TMMS and the memory controller25dmay include the reference offset generation circuit MOSG. The memory controller25dmay receive the plurality of internal temperatures Ta˜Th respectively from the semiconductor memory device404a˜404hand receive the module temperature Tspd from the module temperature sensor TSOD.

The reference offset generation circuit MOSG in the memory controller25dmay generate the reference offset value MOFS based on the internal temperatures Ta˜Th and the module temperature Tspd, and the memory controller25dmay perform the thermal throttling based on the reference offset value MOFS generated in the memory controller25d.

Referring toFIGS.16and17, the memory controller25dmay transmit a first request REQ1to request the transfer of the module temperature Tspd to the control device RCD (S51), and the module temperature Tspd may be transferred to the memory controller25dunder control of the control device RCD (S52).

After that, when the memory controller25dmay update the reference offset value MOFS as described above with reference toFIG.7, the memory controller25cmay transmit a second request REQ2to request the transfer of the internal temperatures Ta˜Th to the control device RCD (S53). Under the control of the control device500d, the semiconductor memory devices404a˜404hmay transfer the internal temperatures Ta˜Th to the memory controller25d.

The reference offset generation circuit MOSG in the memory controller25dmay calculate the reference offset value MOFS as described with reference toFIG.13(S55), and perform the thermal throttling or thermal control based on the module temperature Tspd and the reference offset value MOFS (S56).

FIGS.18and19are diagrams illustrating a stacked memory device according to exemplary embodiments.

Referring toFIG.18, a semiconductor memory device900may include first through kth semiconductor integrated circuit layers LA1910through LAk920, in which the lowest, first semiconductor integrated circuit layer LA1is assumed to be an interface or control chip, and the other semiconductor integrated circuit layers LA2through LAk are assumed to be slave chips including core memory chips. The slave chips may form a plurality of memory ranks as described above.

The first through kth semiconductor integrated circuit layers LA1through LAk may transmit and receive signals between the layers by through-substrate vias TSVs (e.g., through-silicon vias). The lowest first semiconductor integrated circuit layer LA1, as the interface or control chip, may communicate with an external memory controller through a conductive structure formed on an external surface.

Each of the first semiconductor integrated circuit layer LA1910through the kth semiconductor integrated circuit layer LAk920may include memory regions921and peripheral circuits922for driving the memory regions921. For example, the peripheral circuits922may include a row-driver for driving wordlines of a memory, a column-driver for driving bit lines of the memory, a data input-output circuit for controlling input-output of data, a command buffer for receiving a command from an outside source and buffering the command, and an address buffer for receiving an address from an external source and buffering the address.

The first semiconductor integrated circuit layer LA1910may further include a control circuit. The control circuit may control access to the memory region921based on a command and an address signal from a memory controller and may generate control signals for accessing the memory region921.

The first semiconductor integrated circuit layer LA1910may include a temperature measurement circuit and a chip offset generation circuit according to exemplary embodiments. As described above, the chip offset generation circuit may generate the chip offset value based on the internal temperature provided from the temperature measurement circuit and the module temperature provided from the module temperature sensor or the memory controller.

FIG.19illustrates an example of a high bandwidth memory (HBM) organization. Referring toFIG.24, a HBM1100may have a stack of multiple DRAM semiconductor dies1120,1130,1140, and1150. The HBM of the stack structure may be optimized by a plurality of independent interfaces, i.e., channels. Each DRAM stack may support up to 8 channels in accordance with HBM standards.FIG.19shows an exemplary stack containing 4 DRAM semiconductor dies1120,1130,1140, and1150, with each DRAM semiconductor die supporting two channels CHANNEL0and CHANNEL1.

Each channel provides access to an independent set of DRAM banks. Requests from one channel may not access data attached to a different channel Channels are independently clocked, and need not be synchronous.

The HBM1100may further include an interface die1110or a logic die at the bottom of the stack structure to provide signal routing and other functions. Some functions for the DRAM semiconductor dies1120,1130,1140, and1150may be implemented in the interface die1110.

In some exemplary embodiments, each of the DRAM semiconductor dies1120,1130,1140, and1150may include the temperature measurement circuit and the chip offset generation circuit. In some exemplary embodiments, the temperature measurement circuit and the chip offset generation circuit that are common to the DRAM semiconductor dies1120,1130,1140, and1150may be included in the interface die1110.

FIGS.20aand20bare diagrams illustrating packaging structures of a stacked memory device according to exemplary embodiments.

Referring toFIG.20a, a memory device1000amay be a memory package, and may include a base substrate or an interposer ITP and a stacked memory device stacked on the interposer ITP. The stacked memory device may include a logic semiconductor die LSD (or a buffer semiconductor die) and a plurality of memory semiconductor dies MSD1˜MSD4.

Referring toFIG.20b, a memory device1000bmay be a memory package and may include a base substrate BSUB and a stacked memory device stacked on the base substrate BSUB. The stacked memory device may include a logic semiconductor die LSD and a plurality of memory semiconductor dies MSD1˜MSD4.

FIG.20aillustrates a structure in which the memory semiconductor dies MSD1˜MSD4except for the logic semiconductor die LSD are stacked vertically and the logic semiconductor die LSD is electrically connected to the memory semiconductor dies MSD1˜MSD4through the interposer ITP or the base substrate. In contrast,FIG.20billustrates a structure in which the logic semiconductor die LSD is stacked vertically with the memory semiconductor dies MSD1˜MSD4.

A temperature measurement circuit TMMS and a chip offset generation circuit OSG as described above may be included in the logic semiconductor die LSD. The chip offset generation circuit OSG may generate the chip offset value based on the internal temperature provided from the temperature measurement circuit TMMS and the module temperature provided from the module temperature sensor or the memory controller.

The base substrate BSUB may be the same as the interposer ITP or include the interposer ITP. The base substrate BSUB may be a printed circuit board (PCB). External connecting elements such as conductive bumps BMP may be formed on a lower surface of the base substrate BSUB and internal connecting elements such as conductive bumps may be formed on an upper surface of the base substrate BSUB. In some exemplary embodiments, the semiconductor dies LSD and MSD1˜MSD4may be electrically connected through through-silicon vias. In other exemplary embodiments, the semiconductor dies LSD and MSD1˜MSD4may be electrically connected through bonding wires. In still other exemplary embodiments, the semiconductor dies LSD and MSD1˜MSD4may be electrically connected through a combination of the through-silicon vias and the bonding wires. In the exemplary embodiment ofFIG.25, the logic semiconductor die LSD may be electrically connected to the memory semiconductor dies MSD1˜MSD4through conductive line patterns formed in the interposer ITP. The stacked semiconductor dies LSD and MSD1˜MSD4may be packaged using an encapsulant such as a resin RSN.

FIG.21is a block diagram illustrating an exemplary embodiment of a temperature measurement circuit included in a semiconductor memory device according to exemplary embodiments, andFIG.22is a circuit diagram illustrating an exemplary embodiment of a temperature detector included in the temperature measurement circuit ofFIG.21.

Referring toFIG.21, a temperature measurement circuit700may include a temperature detector (DET)710and an analog-to-digital converter (CNV)720. The temperature detector710may output at least one of a voltage signal VPTAT and a current signal IPTAT proportional to the operation temperature To. The analog-to-digital converter720may convert the output of the temperature detector710to a digital signal to generate a temperature code TCODE of multiple bits, where the temperature code may indicate each internal temperature Tj of each semiconductor memory device.

In some exemplary embodiments, the temperature detector710may be implemented with first and second PMOS transistors M1, M2, a feedback amplifier AMP, a resistor R and first and second bipolar transistors B1, B2, which are coupled between a power supply voltage VDD and a ground voltage VSS as illustrated inFIG.22. A voltage dVBE across the resistor R may be obtained as Expression 1
dVBE=VBE1−VBE2=VT*Ln(Ic1/Is1)−VT*Ln(n*Ic2/Is2)=VT*Ln(n)  (Expression 1)

In Expression 1, Is1and Is2indicate reverse saturation currents of the bipolar transistors B1, B2. Also, Ic1and Ic2indicate currents flowing through the bipolar transistors B1, B2. Additionally, n is a gain ratio of the bipolar transistors B1, B2, and VT indicates a temperature voltage that is proportional to an absolute temperature of the temperature detector710. Ln(n) is a constant value and thus the voltage dVBE across the resistor R and the current I2flowing through the resistor R are proportional to the temperature variation. The voltage signal VPTAT and the current signal IPTAT may be generated as an output based on the voltage dVBE and the current I2proportional to the operational temperature.

The on-chip temperature sensor described with reference toFIGS.21and22may be integrated in the same semiconductor die of the semiconductor memory device, and the on-chip temperature sensor is distinct from an external temperature sensor such as the module temperature sensor TSOD that is disposed at the memory module. Using the temperature measurement circuit700as described with reference toFIGS.21and22, the internal temperature Tj of the semiconductor memory device may be measured exactly.

FIG.23is a diagram illustrating a semiconductor package including a stacked memory device according to exemplary embodiments.

Referring toFIG.23, a semiconductor package1700may include one or more stacked memory devices1710and a graphics processing unit (GPU)1720.

The stacked memory devices1710and the GPU1720may be mounted on an interposer1730, and the interposer on which the stacked memory device1710and the GPU1720are mounted may be mounted on a package substrate1740. The package substrate1740is mounted on solder balls1750. The GPU1720may perform the same operation as the memory controller25ofFIG.1or may include the memory controller25. The GPU1720may store data, which is generated or used in graphic processing in the stacked memory devices1710.

The stacked memory device1710may be implemented in various forms, and the stacked memory device1710may be a memory device in a high bandwidth memory (HBM) form in which a plurality of layers are stacked. The stacked memory device1710may include a buffer die and a plurality of memory dies. The buffer die may include an interface circuit.

FIG.24is a diagram illustrating a memory system having quad-rank memory modules according to exemplary embodiments.

Referring toFIG.24, a memory system1800may include a memory controller1810and one or more memory modules1820and1830. Two memory modules1820and830are illustrated inFIG.24, but this is only an example.

The memory controller1810may control the one or more memory modules1820and1830so as to perform a command supplied from a processor or host. The memory controller1810may be implemented in a processor or host, or may be implemented with an application processor or a system-on-a-chip (SoC). For signal integrity, a source termination may be implemented with a resistor RTT on a bus1840of the memory controller1810. The resistor RTT may be coupled to a power supply voltage VDDQ. The memory controller1810may include a transmitter1811to transmit a signal to the one or more memory modules1820and1830and a receiver1813to receive a signal from the one or more memory modules1820and1830.

The one or more memory modules1820and1830may be referred to as a first memory module1820and a second memory module1830. The first memory module1820and the second memory module1830may be coupled to the memory controller1810through the bus1840. Each of the first memory module1820and the second memory modules1830may correspond to the memory module100aofFIG.9, the memory module100bofFIG.11, the memory module100cofFIG.14or the memory module100dofFIG.16. The first memory module1820may include one or more memory ranks RK1and RK2, and the second memory module1830may include one or more memory ranks RK3and RK4.

Each of the first memory module1820and the second memory module1830may include a control device disposed at the center of a circuit board, a first group of semiconductor memory devices disposed between the control device and a first edge portion of the circuit board and a second group of semiconductor memory devices disposed between the control device and a second edge portion of the circuit board.

FIG.25is a block diagram illustrating a mobile system including a memory module according to exemplary embodiments.

Referring toFIG.25, a mobile system1900may include an application processor (AP)1910, a connectivity module1920, a memory module (MM)1950, a nonvolatile memory device (NVM)1940, a user interface1930, and a power supply1970. The application processor1910may include a memory controller (MCT)1911.

The application processor1910may execute applications, such as a web browser, a game application, a video player, etc. The connectivity module1920may perform wired or wireless communication with an external device.

The memory module1950may store data processed by the application processor1910or operate as a working memory. The memory module1950may include a plurality of semiconductor memory devices MEM, a control device RCD and a module temperature sensor TSOD. Each of the semiconductor memory devices MEM may include a temperature measurement circuit as described above. In some exemplary embodiments, a chip offset generation circuit as described above may be further included in each of the semiconductor memory devices MEM. In some exemplary embodiments, the reference offset generation circuit as described above may be included in the control device RCD or the memory controller1911.

As will be appreciated by one skilled in the art, embodiments of the present invention may be realized as a system, method, computer program product, or a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon. The computer readable program code may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing devices. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

As described above, the memory module, the memory system and the method of operating a memory system according to the exemplary embodiments may reduce physical damage to the semiconductor memory devices and enhance the performance and lifetime of the memory module and the memory system by dynamically generating the reference offset value based on the real internal temperatures of the semiconductor memory devices to perform the thermal throttling based on the reference offset value.

The inventive concept may be applied to any electronic devices and systems. For example, the inventive concept may be applied to systems such as a memory card, a solid state drive (SSD), an embedded multimedia card (eMMC), a universal flash storage (UFS), a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a camcorder, a personal computer (PC), a server computer, a workstation, a laptop computer, a digital TV, a set-top box, a portable game console, a navigation system, a wearable electronic device, an internet of things (IoT) device, an internet of everything (IoE) device, an e-book, a virtual reality (VR) device, an augmented reality (AR) device, a server system, a standalone server/personal computer, a high-capacity memory server, a data center, a supercomputer, a high-performance computing device, an automotive device, etc.

The foregoing is illustrative of exemplary embodiments and is not to be construed as limiting thereof. Although a few exemplary embodiments have been described, those skilled in the art will readily appreciate that many variations and modifications are possible in the exemplary embodiments without materially departing from the present inventive concept as defined by the appended claims.