Patent ID: 12254214

DETAILED DESCRIPTION

When the electronic circuit as a verification target requires a large amount of memory, verification may be performed by connecting a DRAM (i.e., Dynamic Random Access Memory) to the FPGA. However, since the operating frequency of the DRAM is much higher than that of the FPGA, there is a difficulty that the performance of the electronic circuit cannot be verified correctly. There is also a method of performing verification using an SRAM (i.e., Static Random Access Memory) whose operating frequency is slower than that of the DRAM. However, the price of the SRAM is higher than the DRAM, so that the verification cost is increased.

The present disclosure can be realized as the following embodiments.

According to one aspect of the present embodiments, an input output control device is provided. The input output control device is connected between a verification circuit and a semiconductor memory device and controls an input and an output of data.

The input output control device includes: a first port that inputs a read transaction for requesting reading of data of the semiconductor memory device from the verification circuit, and outputs a read response, received from the semiconductor memory device in response to the read transaction, to the verification circuit; a second port that outputs the read transaction to the semiconductor memory device, and receives the read response output from the semiconductor memory device in response to the read transaction; and a buffer device that delays at least one of the output of the read transaction to the semiconductor memory device and the output of the read response to the verification circuit.

According to this aspect of the input output control device, at least one of the output of the read transaction to the semiconductor memory device and the output of the read response to the verification circuit is delayed. It is possible to suppress the difference between the operating frequency of the verification device and the operating frequency of the semiconductor memory device and to suppress the deterioration of the accuracy of the performance verification of the verification circuit.

A. First Embodiment

A-1. Device Configuration

As shown inFIG.1, the input output control device200is connected between the verification circuit100and the memory system300and controls an input and an output of data between the verification circuit100and the memory system300. More specifically, the input output control device200delays the output of the read transaction from the verification circuit100to the memory system300and the output of the read response from the memory system300to the verification circuit100by a predetermined number of cycles.

In this embodiment, the verification circuit100is implemented by an FPGA (i.e., Field Programmable Gate Array) and includes a calculation device110and a bus120. The calculation device110is connected to the input output control device200via the bus120and outputs transactions for requesting data access to the memory system300to the input output control device200. In the following description, a transaction for requesting reading of data from the memory system300is defined as a “read transaction”. In this embodiment, the read transaction output from the calculation device110has at least an ID, data amount, and an address as an access target.

The memory system300includes a memory controller310and a semiconductor memory device320. The memory controller310converts a transaction output from the input output control device200into a protocol for processing by the semiconductor memory device320and outputs the protocol to the semiconductor memory device320. In addition, the memory controller310converts the data output from the semiconductor memory device320according to the protocol into a read response to be processed by the calculation device110and outputs the read response to the input output control device200via the bus10. The read response has the same ID as the corresponding read transaction.

The semiconductor memory device320is configured to read and write data with an arbitrary storage unit designated by a protocol output from the memory controller310. In this embodiment, the semiconductor memory device320is configured as a DRAM having banks B0 and B1. Here, the semiconductor memory device320may have only one bank or three or more banks.

The input output control device200includes a slave port210, a band counter device220, elapse cycle counters231to234, a master port240and a buffer device250.

The slave port210is interconnected with the verification circuit100to receive transactions from the verification circuit100and output read responses to the verification circuit100. The slave port210corresponds to the “first port” in this disclosure.

The band counter device220counts the amount of access data, and suspends the output of the read transactions to the memory system300when the amount of access data within a predetermined time exceeds a predetermined target band. The “access data amount” means the total amount of the data in the read transaction output to the memory system300per unit time. A “target band” means a value that defines a target for the usage band of the bus10. Also, the band counter device220outputs the read transaction to the memory system300via the master port240when the amount of access data is equal to or less than the target band. Specific processing by the band counter device220will be described in the transaction output process described later.

The elapse cycle counters231to234hold the number of elapse cycles after the read transaction is output to the memory system300for each read transaction. Each of the elapse cycle counters231to234has a parameter (hereinafter also referred to as “busy”) indicating whether or not the number of elapse cycles is counted and held. Busy “0” indicates that the number of elapse cycles is not held, that is, not counted, and busy “1” indicates that the number of elapse cycles is held, that is, counted. Specific processing by the elapse cycle counters231to234will be described in the transaction output process and the response output process described later.

In the input output control device200of this embodiment, it may be preferable that the number of elapse cycle counters equal to the maximum number of outstanding read transactions is provided. The “maximum number of outstanding” means the maximum number of read transactions that can be output continuously without the calculation device110receiving read responses. With such a configuration, the input output control device200can process the read transactions continuously output from the calculation device110in parallel without excess or deficiency.

The master port240connects with the memory system300to output transactions to the memory system300and receive read responses from the memory system300. The master port240corresponds to the “second port” in this disclosure.

The buffer device250withholds the read response when the number of elapse cycles is less than a predetermined threshold. In this embodiment, the buffer device250holds the read response in FIFO (i.e., First-In First-Out) format. Also, the buffer device250outputs a read response to the verification circuit100via the slave port210when the number of elapse cycles is equal to or greater than the threshold. Specific processing by the buffer device250will be described in the response output process described later.

A-2. Transaction Output Process

When outputting a read transaction to the memory system300, the input output control device200executes the transaction output process shown inFIG.2. When a read transaction is output from verification circuit100, the band counter device220determines whether or not the amount of access data is equal to or less than the target band (at step S110).

If it is determined that the amount of access data is equal to or less than the target band (“YES” at step S110), the input output control device200determines whether at least one busy of the elapse cycle counters231to234is “0” (at step S120). When it is determined that at least one busy of the elapse cycle counters231to234is “0” (“YES” at step S120), the input output control device200receives a read transaction via the slave port210(at step S130).

On the other hand, if it is determined that the amount of access data exceeds the target band (“NO” at step S110), or if the busy of all cycle counters231to234are “1” (“NO” at step S120), the input and output control device200stops receiving read transactions via the slave port210. In this embodiment, the read transactions are held in the verification circuit100while the reception of read transactions is stopped.

In step S140, the band counter device220adds the data amount of the received read transaction (hereinafter also referred to as the “receive data amount”) to the holding access data amount to obtain a new access data amount. Also, in step S150, the band counter device220records the time when the receive data amount is added to the access data amount.

In step S160, the band counter device220outputs a read transaction via the master port240.

In step S170, one of the elapse cycle counters231to234whose busy is “0” (hereinafter also referred to as a “selection counter”) is changed to have the busy of “1”, and the ID and the data amount of the output transaction are recorded. Also, in step S180, the selection counter starts counting the number of elapse cycles. The selection counter newly holds a value obtained by adding “1” to the holding number of elapse cycles each time one cycle elapses.

The input output control device200repeatedly executes the above-described steps S110to S180each time the verification circuit100outputs a read transaction.

In parallel with steps S110to S180described above, the band counter device220subtracts, from the access data amount, the amount of data when a predetermined time has passed since the addition (at step S190). In this embodiment, the band counter device220can count and hold the amount of access data within a preset time frame by repeating this step.

A-3. Response Output Process

When outputting a read response to the verification circuit100, the input output control device200executes a response output process shown inFIG.3. When the input output control device200receives a read response via the master port240(“YES” at step S210), the buffer device250holds the received read response (at step S220). The buffer device250repeatedly executes steps S210and S220.

In parallel with steps S210and S220, the buffer device250determines whether or not the number of elapse cycles of the corresponding counter is equal to or greater than a preset threshold (at step S230). The “corresponding counter” means an elapse cycle counter among the elapse cycle counters231to234whose recorded ID matches the ID of the head data in the buffer device250. If it is determined that the number of elapse cycles of the corresponding counter is less than the threshold (“NO” at step S230), the buffer device250stands by while holding the data.

When it is determined that the number of elapse cycles of the corresponding counter is equal to or greater than the threshold (“YES” at step S230), the buffer device250outputs the head data via the slave port210(at step S240). Such a threshold value is set as a value specified in advance by conducting an experiment or the like so as to simulate the latency when the memory system300is connected to the electronic circuit simulated by the verification circuit100.

In step S250, the buffer device250determines whether or not the amount of data recorded in the corresponding counter has been output (at step S250). If it is determined that the amount of data recorded in the corresponding counter has not been output (“NO” at step S250), the buffer device250repeatedly executes steps S240and S250until the data with the data amount recorded in the corresponding counter is output.

If it is determined that the amount of data recorded in the corresponding counter has been output (“YES” at step S250), the buffer device250resets the busy of the corresponding counter to “0”, and deletes the ID and the data amount recorded therein (at step S260). After this step, the corresponding counter is again in a state of being able to count the number of elapse cycles of another read transaction. The input output control device200repeatedly executes steps S230to S260.

According to the input output control device200described above, the output of the read transaction to the memory system300and the output of the read response to the verification circuit100are delayed. It is possible to suppress the difference between the operating frequency of the verification circuit100and the operating frequency of the memory system300, and to suppress the reduction of the accuracy in the performance verification of the verification circuit100.

B. Second Embodiment

The input output control device200A of the second embodiment is different from the input output control device200of the first embodiment that the input output control device200A includes a target band generation device260as shown inFIG.4, and, as shown inFIG.5, executes the target band setting process (at step S1400) after step S140in the transaction output process. Other device configurations of the input output control device200A and other procedures in the transaction output process of the second embodiment are the same as those of the input output control device200of the first embodiment. The same reference numerals are given to the same configurations and the same procedures, and detailed description thereof is omitted.

As shown inFIG.4, the target band generation device260includes bank access counter devices261and262and a band setting unit263. The bank access counter devices261and262respectively count and hold the amount of bank access data for banks B0 and B1, and record the previous access page in each bank. “Bank access data amount” means the total value of the data amount of read transactions issued consecutively to the same page in each bank. The “previous access page” means the page address as an access target by the previously output read transaction in each bank. It is assumed that the number of bank access counter devices included in the target band generation device260is the same as the number of banks included in the semiconductor memory device320. Processing in the bank access counter devices261and262will be described later in the target band setting process.

The band setting unit263calculates the average value of the bank access data amounts held in the bank access counter devices261and262, respectively. Also, the band setting unit263sets the target band using the calculated average value of the bank access data amount.

As shown inFIG.5, after step S140, the target band generation device260executes the target band setting process (at step S1400), and updates the target band referred to in step S110described above.

In the target band setting process shown inFIG.6, the target band generation device260determines whether the bank address as the access target in the read transaction is “0” or “1” (at step S1410). If the bank address as the access target is determined to be “0”, it is determined whether the page address as the access target in the received read transaction (hereinafter also referred to as “current access page”) is the same as the previous access page in bank B0 (at step S1420).

If the current access page is the same as the previous access page (“YES” at step S1420), the bank access counter device261adds the received data amount to the holding bank access data amount as a new bank access data amount (at step S1430).

If the current access page is different from the previous access page (“NO” at step S1420), the bank access counter device261sets the received data amount as a new bank access data amount and records the current access page (at step S1432).

On the other hand, if it is determined that the bank address as the access target is “1”, it is determined whether or not the current access page is the same as the previous access page in bank B1 (at step S1422).

If the current access page is the same as the previous access page (“YES” at step S1422), the bank access counter device262adds the received data amount to the holding bank access data amount as a new bank access data amount (at step S1434).

If the current access page is different from the previous access page (“NO” at step S1422), the bank access counter device262sets the received data amount as a new bank access data amount and records the current access page (at step S1436). In step S1440, the band setting unit263calculates the average value of the bank access data amounts counted and held in the bank access counter devices261and262, respectively, and sets the target band based on the calculated average value. In this embodiment, the band setting unit263sets the target band using the table shown inFIG.7showing the relationship between the average value of the bank access data amount and the target band. In this embodiment, the table has a relationship that the target band increases as the average value of the bank access data amount increases. More specifically, the table has a relationship in which the slope of the amount of increase in the target band decreases as the average value of the bank access data amount increases. With this, the target band generation device260ends the target band setting process.

According to the input output control device200A of the second embodiment described above, the target band is set according to the average value of the bank access data amount counted and held in each of the bank access counter devices261and262, the output of the read transaction to the memory system300can be delayed according to the change in the amount of access data, and the deterioration of the accuracy of the performance verification of the verification circuit100can be further suppressed.

C. Other Embodiments

(C1) In the above embodiment, the number of elapse cycle counters equal to the maximum outstanding number is provided, alternatively, the present disclosure may not be limited to this feature. The elapse cycle counters may be provided with the number thereof less than the maximum outstanding number. This feature also provides the same effects as the above embodiment.

(C2) In the above embodiment, the input output control device200includes the buffer device250and the band counter device220, alternatively, the present disclosure may not be limited to this feature. The input output control device200may include only the buffer device250out of the buffer device250and the band counter device220. In this feature as well, the input output control device200can delay the output of the read response to the verification circuit100. Therefore, the difference between the operating frequency of the verification circuit100and the operating frequency of the semiconductor memory device320is suppressed, and the reduction of the accuracy of performance verification of the circuit100can be suppressed.

(C3) In the above embodiment, the table has a relationship in which the slope of the amount of increase in the target band decreases as the average value of the bank access data amount increases, alternatively, the present disclosure may not be limited to this feature. The table may have a relationship in which the target band increases linearly as the average value increases. This feature also provides the same effects as the above embodiment.

The input output control device200and the technique of the display device according to the present disclosure may be achieved by a dedicated computer provided by constituting a processor and a memory programmed to execute one or more functions embodied by a computer program. Alternatively, the input output control device200and the technique of the display device according to the present disclosure may be achieved by a dedicated computer provided by constituting a processor with one or more dedicated hardware logic circuits. Alternatively, the input output control device200and the technique of the display device according to the present disclosure may be achieved using one or more dedicated computers constituted by a combination of a processor and a memory programmed to execute one or more functions and a processor formed of one or more hardware logic circuits. The computer program may be stored in a computer-readable non-transitory tangible recording medium as an instruction to be executed by the computer.

The present disclosure should not be limited to the embodiments described above, and various other embodiments may be implemented without departing from the scope of the present disclosure. For example, the technical features in each embodiment corresponding to the technical features in the form described in the summary may be used to solve some or all of the above-described problems, or to provide one of the above-described effects. In order to achieve a part or all, replacement or combination can be appropriately performed. Also, some of the technical features may be omitted as appropriate.

The controllers and methods described in the present disclosure may be implemented by a special purpose computer created by configuring a memory and a processor programmed to execute one or more particular functions embodied in computer programs. Alternatively, the controllers and methods described in the present disclosure may be implemented by a special purpose computer created by configuring a processor provided by one or more special purpose hardware logic circuits. Alternatively, the controllers and methods described in the present disclosure may be implemented by one or more special purpose computers created by configuring a combination of a memory and a processor programmed to execute one or more particular functions and a processor provided by one or more hardware logic circuits. The computer programs may be stored, as instructions being executed by a computer, in a tangible non-transitory computer-readable medium.

It is noted that a flowchart or the processing of the flowchart in the present application includes sections (also referred to as steps), each of which is represented, for instance, as S110. Further, each section can be divided into several sub-sections while several sections can be combined into a single section. Furthermore, each of thus configured sections can be also referred to as a device, module, or means.

While the present disclosure has been described with reference to embodiments thereof, it is to be understood that the disclosure is not limited to the embodiments and constructions. The present disclosure is intended to cover various modification and equivalent arrangements. In addition, while the various combinations and configurations, other combinations and configurations, including more, less or only a single element, are also within the spirit and scope of the present disclosure.