Patent ID: 12198926

DETAILED DESCRIPTION

Techniques disclosed herein relate generally to semiconductor wafers having at least one deposited layer that has a coefficient of thermal expansion (CTE) mismatch with the bulk wafer material. More specifically, techniques disclosed herein relate to methods of forming one or more silicon nitride layers on silicon wafers with reduced strain. Various inventive embodiments are described herein, including methods, processes, systems, devices, and the like.

In order to better appreciate the features and aspects of depositing CTE mismatched layers on semiconductor wafers according to the present disclosure, further context for the disclosure is provided in the following section by discussing one particular implementation of a silicon nitride film deposited on a 300 millimeter silicon wafer, according to embodiments of the present disclosure. These embodiments are for explanatory purposes only and other embodiments may be employed in other types of deposited layers, different compositions of semiconductor wafers and/or different sizes (e.g., diameters) of semiconductor wafers. For example, embodiments of the disclosure can be used with any semiconductor wafer that can benefit from the deposition of a layer that has a mismatched coefficient of thermal expansion (CTE) with the bulk material of the wafer. In some instances, embodiments of the disclosure are particularly well suited for use with relatively large wafers (e.g., 300 mm and above) because of the difficulty of forming CTE mismatched layers on larger wafers, however the embodiments disclosed herein are in no way limited to any size or configuration of semiconductor wafer.

FIG.1depicts an isometric illustrative rendering of a semiconductor wafer100, according to some embodiments of the disclosure. As shown inFIG.1, semiconductor wafer100includes a plurality of individual die105that will be singulated along dicing lanes110shown by dashed lines. Wafer100can include a layer of silicon nitride, or other film, as described in more detail below.

FIG.2illustrates steps associated with a method200of forming a silicon nitride layer on silicon wafer100ofFIG.1, according embodiments of the disclosure.FIGS.3A-3Jillustrate simplified sequential views of cross-section A-A along dicing lane110shown inFIG.1, according to method200described inFIG.2. Method200describes a process involving selective removal of portions of the silicon nitride layer in-between silicon nitride deposition steps, resulting in reduced strain between the silicon nitride layer and the silicon, as described in more detail below.

In step205ofFIG.2an appropriate semiconductor wafer is provided. In some embodiments the wafer can be silicon, however in other embodiments the wafer may be, silicon on insulator (SOI), silicon with one or more pre-deposited layers, germanium, silicon germanium, gallium arsenide, silicon carbide, gallium nitride, CVD diamond or any other type of semiconducting or dielectric material. In some embodiments the wafer may be any suitable diameter, including but not limited to any of the common standards such as, 150, 200, 300, 450 millimeters. In some embodiments, the techniques disclosed herein may be beneficial for wafers having a generally larger diameter as film strain increases over larger distances, however the techniques disclosed herein are not limited to any particular size of wafer as film stresses are also determined by the CTE mismatch between the materials.

Referring toFIG.3A, a cross-section through dicing lane110(seeFIG.1) of wafer100is illustrated. This particular cross-section shows a portion of a first die305aand a portion of a second die305b. First die305ahas first die frame310aand second die305bhas second die frame310b. First and second die frames310a,310b, respectively, are inactive areas surrounding a periphery of each respective die that provide a predetermined setback for singulation operations, locations for wafer fabrication metrology structures and/or other features.

Dicing lane110is illustrated between first die frame310aand second die frame310band is typically a “kerf” width of a dicing blade that can be any suitable width. In some embodiments a width of dicing lane110is between 10 microns and 500 microns, while in other embodiments the dicing lane is between 50 microns and 100 microns. In some embodiments wafer100is between 0.1 and 10 millimeters thick, while in other embodiments the wafer is between 0.5 and 1 millimeter thick and in further embodiments the wafer is approximately 0.7 millimeters thick.

In step210ofFIG.2, a layer of silicon nitride is deposited on the wafer using any appropriate deposition technique. Referring toFIG.3B, first silicon nitride layer315is formed on a top surface320of wafer100. In some embodiment a simultaneous bottom layer of silicon nitride325is formed on a bottom surface330of wafer100to prevent bowing of the wafer due to unequal stress on each side. In some embodiments a simultaneous dual sided silicon nitride coating may be deposited using furnace deposition techniques while in other embodiments only first silicon nitride layer315may be deposited, for example when using a physical vapor deposition (PVD) or chemical vapor deposition (CVD) process. Any suitable deposition technique can be used to deposit first silicon nitride layer315on wafer100. In some embodiments first silicon nitride layer315is between 50 and 1000 nanometers thick, while in other embodiments the first silicon nitride layer is between 100 and 300 nanometers thick and in further embodiments the first silicon nitride layer is approximately 200 nanometers thick.

In step215ofFIG.2, portions of first silicon nitride layer315are selectively removed. Referring toFIG.3C, a first portion335aand a second portion335bof first silicon nitride layer315are removed. In this embodiment, first portion335ais directly over first die frame310aand second portion335bis directly over second die frame310b, however in other embodiments portions of the silicon nitride layer can be removed in different locations. In some embodiments first and second portions335a,335b, respectively, can be removed using a semiconductor wafer dicing saw that is set at a depth of first silicon nitride layer315, or deeper. However, in other embodiments any type of wet or dry etching process, laser ablation process or other suitable process can be used to remove first and second portions335a,335b, respectively. In some embodiments a width of first and second portions335a,335b, respectively, is between 10 microns and 500 microns, while in other embodiments the width is between 50 microns and 100 microns and in one embodiment the width is approximately 70 microns. In this particular embodiment strips of first silicon nitride layer315are removed along every dicing lane110(seeFIG.1) that exists between each die105, however in other embodiments the strips can be removed between every other die, every third, fourth or fifth die or at any other suitable spacing.

As appreciated by one of skill in the art having the benefit of this disclosure, selective removal of strips of first silicon nitride layer315reduces the accumulation of stress that builds up between CTE mismatched layers, such as first silicon nitride layer315and silicon wafer100. It will also be appreciated that strips oriented in a perpendicular relationship to each other will relieve stress across the entire surface of the wafer. In some embodiments, where the CTE mismatch is relatively large, the spacing between the strips of removed material may be reduced while in embodiments that have lower CTE mismatch the spacing between the strips may be increased. Further, in some embodiments the spacing between the strips located proximate a center of the wafer may be greater than the spacing at the edges of the wafer as the film strain can accumulate from the center (e.g., neutral axis) of the wafer. In yet further embodiments, the strips may not be aligned with the dicing lanes and may be positioned at other suitable locations on the wafer, for example, aligned with geometry of features formed on each die.

In step220ofFIG.2, a fill material is deposited on the first silicon nitride layer. Referring toFIG.3D, fill material340is deposited on first silicon nitride layer315. In some embodiments fill material340may be what is known as a flowable silicon dioxide that can flow at relatively low temperatures (e.g., approximately 400° C.), however in other embodiments it may be a “high quality” silicon dioxide material that flows at relatively higher temperatures (e.g., 600-650° C.). Any suitable silicon dioxide or other fill material, for example phosphosilicate glass (PSG) or borophosphosilicate glass (PBSG), can be used to fill first and second portions335a,335b, respectively.

In step225ofFIG.2, the wafer is planarized. Referring toFIG.3E, wafer100is planarized to remove excess fill material340such the fill material and first silicon nitride layer315are coplanar. In some embodiments, in which bottom layer of silicon nitride325(seeFIG.3B) was deposited on bottom surface330of wafer100, the bottom layer can also be removed during the planarization process. In some embodiments planarization can be performed using chemical mechanical polishing (CMP), however any other suitable process such as, for example, wet or dry etching can be used. An optional thermal treatment step that improves the quality of the deposited silicon nitride layer can be employed between the silicon nitride deposition and the silicon dioxide deposition. Alternatively, the thermal treatment step can be employed after the silicon dioxide deposition process or after the planarization step.

Depending upon the desired final thickness of silicon nitride layer315, the deposition, selective removal and planarization steps (e.g., steps210through225) can be repeated via loop230. In this embodiment these steps are repeated a second time, however the steps can be repeated any suitable number of times.

In a first repetition of step210ofFIG.2, a second layer of silicon nitride is deposited on the wafer using any suitable deposition technique. Referring toFIG.3F, second silicon nitride layer345is formed on first silicon nitride layer315. During the deposition process first silicon nitride layer315can bond to second silicon nitride layer345. In some embodiments appropriate cleaning and surface preparation of first silicon nitride layer315is performed prior to deposition of second silicon nitride layer345. In further embodiments a heat treatment or annealing process may be performed after deposition of second silicon nitride layer345to bond the second silicon nitride layer to first silicon nitride layer315. Portions of second silicon nitride layer345extend over fill material340that is deposited in first and second portions335a,335b, respectively. As shown inFIG.3F, in this embodiment a second bottom layer of silicon nitride355is deposited during the deposition of second layer of silicon nitride345to equalize stress on wafer100.

In step215ofFIG.2, portions of second silicon nitride layer345are removed. Referring toFIG.3G, a first portion350aand a second portion350bof second silicon nitride layer345are removed deep enough to expose fill material340.

In step220ofFIG.2, a fill material is deposited on the second silicon nitride layer. Referring toFIG.3H, a second layer of fill material375is deposited on second silicon nitride layer345. Second layer of fill material375may be the same material used for first layer of fill material340.

In step225ofFIG.2, the wafer is planarized. Referring toFIG.3I, wafer100is planarized to remove excess second layer of fill material375such the fill material and second silicon nitride layer345are coplanar. In some embodiments in which a second bottom layer of silicon nitride355was deposited on bottom surface330of wafer100, the second bottom layer can be removed during the planarization process.

In this particular embodiment first and second silicon nitride layers315,345, respectively form a homogeneous silicon nitride layer360that is approximately 400 nanometers thick. In other embodiments the homogeneous silicon nitride layer can be between 200 and 2000 nanometers thick and in some embodiments is between 400 and 1000 nanometers thick, depending on the number of depositions and the thickness of each deposition. As described above, loop230can be repeated any number of times. One or more annealing steps can be performed during the fabrication process to stabilize and relieve stresses in the one or more silicon nitride layers, shown inFIG.3Ias first and second silicon nitride layers315,345, respectively. Any appropriate annealing temperature, duration and atmosphere can be used and in one embodiment the annealing temperature is between 800° C. and 1200° C.

In step235ofFIG.2, one or more devices are formed on the homogeneous silicon nitride layer. Referring toFIG.3J, in this particular embodiment, two additional layers365and367are formed on top of homogeneous silicon nitride layer360and device structures370are formed on the two additional layers. In other embodiments a different configuration of additional layers and/or device strictures can be formed on homogeneous silicon nitride layer360.

It will be appreciated that method200is illustrative and that variations and modifications are possible. Steps described as sequential may be executed in parallel, order of steps may be varied, and steps may be modified, combined, added or omitted. For example, although the stress relieving features are illustrated as between each die (e.g., in the die frame area), in other embodiments the stress relieving features can also or alternatively be formed within each die. For example, each die can be separated into two, three, four or more separate sections which have stress-relieving features formed between each section. Some examples of process variants are illustrated below.

FIGS.4A-4Dillustrate steps associated with a method of depositing a film on a semiconductor substrate that is similar to method200illustrated inFIG.2, however, in this embodiment trenches are formed in the wafer before silicon nitride deposition and the fill/planarization processes are not employed, as described in more detail below. More specifically, as shown inFIG.4A, a plurality of trenches405are formed in a top surface410of silicon wafer415. In some embodiments a dicing saw, a photolithographic etching process or other suitable process can be used to form trenches405. As described above, in some embodiments trenches405may be formed in a perpendicular arrangement along either side of each dicing lane in the die frame area (seeFIG.3Aand associated discussion), however in other embodiments the trenches can be formed at other suitable locations.

InFIG.4Ba first layer of silicon nitride420is deposited on top surface410of wafer415where the silicon nitride layer is also deposited within trenches405. In some embodiments trenches405can be used to relieve the strain between silicon nitride layer420and wafer415so silicon nitride layers having an increased thickness and/or reduced strain can be deposited. InFIG.4Cportions of silicon nitride layer410are removed from trenches405using a dicing saw, a wet or dry etching processes or other suitable process. InFIG.4Da second layer of silicon nitride425is deposited on the first layer of silicon nitride420forming a homogeneous silicon nitride layer. The silicon nitride deposition and removal processes can be repeated to form a silicon nitride layer of any suitable thickness. In some embodiments one or more annealing processes can be employed in the process to relieve stresses within the silicon nitride layers and/or to improve bonding between the layers. In some embodiments the presence of trenches405may relieve strain in the deposited silicon nitride film enough so a silicon nitride layer of suitable thickness can be grown in one deposition step.

It will be appreciated that the process shown inFIGS.4A-4Dis illustrative and that variations and modifications are possible. Steps described as sequential may be executed in parallel, order of steps may be varied, and steps may be modified, combined, added or omitted.

FIGS.5A-5Dillustrate steps associated with a method of depositing a film on a semiconductor substrate that is similar to method200illustrated inFIG.2, however, in this embodiment the wafer is a silicon-on-insulator (SOI) configuration, trenches are formed in the SOI wafer before silicon nitride deposition and the fill/planarization processes are not employed. More specifically, as shown inFIG.5A, SOI wafer500includes a bottom layer of silicon505, a middle layer of silicon dioxide510and a top layer of silicon515, however other embodiments may use wafers of different materials and/or configurations. A plurality of trenches520are formed in top surface525of SOI wafer500. In some embodiments a dicing saw, a wet or dry etching processes or other suitable process can be used to form the trenches. As described above, in some embodiments trenches520may be formed in a perpendicular arrangement along either side of each dicing lane in the die frame area (seeFIG.3Aand associated discussion), however in other embodiments the trenches can be formed at other suitable locations.

InFIG.5Ba first layer of silicon nitride530is deposited on top surface525of SOI wafer500where the silicon nitride layer also covers trenches520. In some embodiments trenches520can be used to relieve strain between silicon nitride layer530and SOI wafer500so silicon nitride layers having an increased thickness can be deposited. InFIG.5Cportions of silicon nitride layer530are removed from trenches520using a dicing saw, a wet or dry etching processes or other suitable process. InFIG.5Da second layer of silicon nitride535is deposited on first layer of silicon nitride530forming a homogeneous silicon nitride layer. The silicon nitride deposition and removal processes can be repeated to form a silicon nitride layer of any suitable thickness. In some embodiments one or more annealing processes can be employed in the process to relieve stresses within the silicon nitride layers and/or to improve bonding between the layers. In some embodiments the presence of trenches520may relieve strain in the deposited silicon nitride film enough so a silicon nitride layer of suitable thickness can be grown in one deposition step.

It will be appreciated that the process shown inFIGS.5A-5Dis illustrative and that variations and modifications are possible. Steps described as sequential may be executed in parallel, order of steps may be varied, and steps may be modified, combined, added or omitted.

FIGS.6A-6Dillustrate steps associated with a method of depositing a film on a semiconductor substrate that is similar to method200illustrated inFIG.2, however, in this embodiment trenches are formed in the wafer before silicon nitride deposition and the fill/planarization processes are not employed. More specifically, as shown inFIG.6A, a silicon dioxide layer600is deposited on a top surface605of silicon wafer610, then trenches615are formed in the top surface of the wafer. In some embodiments a dicing saw, a wet or dry etching processes or other suitable process can be used to form trenches615. As described above, in some embodiments trenches615may be formed in a perpendicular arrangement along either side of each dicing lane in the die frame area (seeFIG.3Aand associated discussion), however in other embodiments the trenches can be formed at other suitable locations.

InFIG.6Ba first layer of silicon nitride620is deposited on silicon dioxide layer600where the silicon nitride layer also covers trenches615. In some embodiments silicon dioxide layer600can be used to relieve strain between silicon wafer610and first silicon nitride layer620. In one embodiment silicon dioxide layer600is configured to have a reduced modulus of elasticity when exposed to temperatures above 650° C. In one embodiment silicon dioxide layer600is formed with a flowable oxide, an HPD oxide, a TEOS, a thermal oxide or any other suitable process. In some embodiments trenches615can be used to relieve strain between first silicon nitride layer620and silicon wafer610so silicon nitride layers of relatively large thickness can be deposited. InFIG.6Cportions of first silicon nitride layer620are removed from trenches615using a dicing saw, a wet or dry etching processes or other suitable process. InFIG.6Da second layer of silicon nitride625is deposited on first layer of silicon nitride620forming a homogeneous silicon nitride layer having increased thickness. The silicon nitride deposition and removal processes can be repeated to form a silicon nitride layer of any suitable thickness. In some embodiments one or more annealing processes can be employed in the process to relieve stresses within the silicon nitride layers and/or to improve bonding between the layers. In some embodiments the presence of trenches615may relieve strain in the deposited silicon nitride film enough so a silicon nitride layer of suitable thickness can be grown in one deposition step.

It will be appreciated that the process shown inFIGS.6A-6Dis illustrative and that variations and modifications are possible. Steps described as sequential may be executed in parallel, order of steps may be varied, and steps may be modified, combined, added or omitted.

FIGS.7A-7Dillustrate steps associated with a method of depositing a film on a semiconductor substrate that is similar to method200illustrated inFIG.2, however, in this embodiment the wafer is a SOI configuration, a layer of silicon dioxide is first deposited, trenches are formed in the wafer before silicon nitride deposition and the fill/planarization processes are not employed. More specifically, as shown inFIG.7A, SOI wafer700includes a bottom layer of silicon705, a middle layer of silicon dioxide710and a top layer of silicon715, however other embodiments may use wafers of different materials and/or configurations. A deposited silicon dioxide layer720is formed on top surface725of SOI wafer700, then a plurality of trenches730are formed in top surface725of the SOI wafer700. In some embodiments a dicing saw, a wet or dry etching processes or other suitable process can be used to form trenches730. As described above, in some embodiments trenches730may be formed in a perpendicular arrangement along either side of each dicing lane in the die frame area (seeFIG.3Aand associated discussion), however in other embodiments the trenches can be formed at other suitable locations.

InFIG.7Ba first layer of silicon nitride735is deposited on deposited silicon dioxide layer720where the first silicon nitride layer also covers trenches730. In some embodiments deposited silicon dioxide layer720can be used to relieve strain between SOI wafer700and first layer of silicon nitride735. In one embodiment deposited silicon dioxide layer720is configured to have a reduced modulus of elasticity when exposed to temperatures above 650° C. In some embodiments the deposited silicon dioxide layer720is formed with a flowable oxide, an HPD oxide, a TEOS, a thermal oxide or any other suitable process. In various embodiments trenches730can be used to relieve the strain between first silicon nitride layer735and the SOI wafer700so silicon nitride layers having an increased thickness can be deposited.

InFIG.7Cportions of first silicon nitride layer735are removed from trenches730using a dicing saw, a wet or dry etching processes or other suitable process. InFIG.7Da second layer of silicon nitride740is deposited on first layer of silicon nitride735forming a homogeneous silicon nitride layer. The silicon nitride deposition and removal processes can be repeated to form a silicon nitride layer of any suitable thickness. In some embodiments one or more annealing processes can be employed in the process to relieve stresses within the silicon nitride layers and/or to improve bonding between the layers. In some embodiments the presence of trenches730may relieve strain in the deposited silicon nitride film enough so a silicon nitride layer of suitable thickness can be grown in one deposition step.

It will be appreciated that the process shown inFIGS.7A-7Dis illustrative and that variations and modifications are possible. Steps described as sequential may be executed in parallel, order of steps may be varied, and steps may be modified, combined, added or omitted.

FIGS.8A-8Dillustrate steps associated with a method of depositing a film on a semiconductor substrate that is similar to method200illustrated inFIG.2, however, in this embodiment the wafer is an SOI configuration. More specifically, as shown inFIG.8A, SOI wafer800includes a bottom layer of silicon805, a middle layer of silicon dioxide810and a top layer of silicon815, however other embodiments may use wafers of different materials and/or configurations. A first silicon nitride layer820is deposited on a top surface825of SOI wafer800. Optionally, a silicon dioxide layer (not shown inFIG.8A) can be first deposited before the silicon nitride layer. InFIG.8Ba plurality of trenches830are formed in the top surface of the wafer. In some embodiments a dicing saw, a wet or dry etching processes or other suitable process can be used to form the trenches. As described above, in some embodiments trenches830may be formed in a perpendicular arrangement along either side of each dicing lane in the die frame area (seeFIG.3Aand associated discussion), however in other embodiments the trenches can be formed at other suitable locations.

InFIG.8Ca fill material835that may be silicon dioxide is used to fill trenches830and SOI wafer800can be subsequently planarized using, for example, a CMP process. InFIG.8Da second layer of silicon nitride840is deposited on first layer of silicon nitride820forming a homogeneous silicon nitride layer. The silicon nitride deposition and removal processes can be repeated to form a silicon nitride layer of any suitable thickness. In some embodiments one or more annealing processes can be employed in the process to relieve stresses within the silicon nitride layers and/or to improve bonding between the layers. In some embodiments the presence of trenches830may relieve strain in the deposited silicon nitride film enough so a silicon nitride layer of suitable thickness can be grown in one deposition step.

It will be appreciated that the process shown inFIGS.8A-8Dis illustrative and that variations and modifications are possible. Steps described as sequential may be executed in parallel, order of steps may be varied, and steps may be modified, combined, added or omitted.

FIGS.9A-9Fillustrate sequential steps of an embodiment that can be used to form a silicon nitride layer on a wafer. As compared to the previous embodiments inFIGS.9A-9F, in this embodiment a silicon nitride layer is deposited at a surface of the wafer, which is removed, and a silicon nitride layer is also deposited on a lower layer, which is retained, as explained in more detail below.

As shown inFIG.9A, a wafer900is provided that has one or more recessed regions905formed in a top surface910. Recessed regions905can be formed with a wet or dry etching process or any other suitable process. Wafer900can be silicon, SOI, or any other configuration, some of which are described in more detail above. In further embodiments wafer900may include a tetraethyl orthosilicate (TEOS) layer on a top surface in which recessed regions905are formed.

InFIG.9Ba layer of silicon nitride915is deposited which is divided between a top layer915aand a lower layer915b(e.g., formed in the recesses). In some embodiments a PVD process can be used such that little or no silicon nitride is deposited on the sidewalls of the one or more recessed regions905. In other embodiments any suitable deposition process can be used. By depositing a silicon nitride layer915that is broken up into a top layer915aand a lower layer915b(e.g., the silicon nitride layer is not continuous) the strain between the silicon nitride layer and wafer900can be reduced. In some embodiments the silicon nitride layer915may be approximately 800 nanometers thick.

InFIG.9Ca sacrificial oxide layer920, such as silicon dioxide can be used to cover the entire top surface of the wafer including top layer915aand lower layer915bof silicon nitride. InFIG.9Dthe top surface of the wafer can be polished, for example with CMP, and sacrificial oxide920can be removed from a top surface of top layer915aof silicon nitride. InFIG.9Ethe top layer of silicon nitride can be removed. In some embodiments the removal can be performed with a hot phosphoric acid or other suitable process. InFIG.9Fthe top surface of the wafer can be polished, for example with CMP, exposing the lower layer of silicon nitride which is now coplanar with the other portions of the wafer. As described above, additional layers and/or devices can then be formed on the silicon nitride.

It will be appreciated that the process shown inFIGS.9A-9Fis illustrative and that variations and modifications are possible. Steps described as sequential may be executed in parallel, order of steps may be varied, and steps may be modified, combined, added or omitted.

In further embodiments selective deposition of silicon carbide can be used to pattern the growth of a silicon nitride layer. More specifically, silicon nitride grows markedly slower on silicon carbide than on other surfaces, such as silicon or silicon dioxide. In this embodiment regions where silicon nitride is not desired are covered with silicon carbide. For example, in one embodiment the growth of a layer of silicon nitride on silicon oxide and/or silicon is approximately 100 nanometers and the corresponding growth on the silicon carbide regions is approximately 10-20 nanometers. If a larger thickness of silicon nitride is needed, the silicon nitride deposited on the silicon carbide can be removed and the growth process can be repeated.

As appreciated by one of skill in the art having the benefit of this disclosure, other materials can be used in place of the example materials described above. For example, in some embodiments other dielectrics can be used to surround the silicon nitride such as, but not limited to, silicon dioxide, aluminum oxide, silicon oxynitride, silicon carbide, siliconoxycarbide (SiOC), or silicon-oxynitride-carbide (SiOCN). In another example in the place of silicon nitride other suitable materials such as silicon, SiON or SiOCN.

For simplicity, various process steps that include cleaning, drying, annealing and the like are not described but would be apparent to one of ordinary skill in the art having the benefit of this disclosure and are within the scope of this disclosure.

In the foregoing specification, embodiments of the disclosure have been described with reference to numerous specific details that can vary from implementation to implementation. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. The sole and exclusive indicator of the scope of the disclosure, and what is intended by the applicants to be the scope of the disclosure, is the literal and equivalent scope of the set of claims that issue from this application, in the specific form in which such claims issue, including any subsequent correction. The specific details of particular embodiments can be combined in any suitable manner without departing from the spirit and scope of embodiments of the disclosure.

Additionally, spatially relative terms, such as “bottom or “top” and the like can be used to describe an element and/or feature's relationship to another element(s) and/or feature(s) as, for example, illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and/or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as a “bottom” surface can then be oriented “above” other elements or features. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.