Patent ID: 12261157

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Like numeral references refer to like elements, and their repetitive descriptions are omitted.

FIG.1is a cross-sectional view of a semiconductor package having a package on package (PoP) structure according to an embodiment,FIGS.2A to2Care a cross-sectional view, a perspective view, and a plan view illustrating a stack structure of package substrates and a structure of a package substrate, in the semiconductor package ofFIG.1, andFIGS.3A and3Bare a perspective view and a plan view illustrating a structure of a gap filler, in the semiconductor package ofFIG.1.

Referring toFIGS.1to3B, a semiconductor package having a PoP structure (hereinafter simply referred to as a semiconductor package or a semiconductor device)100according to an embodiment may include a first package substrate110, a second package substrate120, a first semiconductor chip130, a first connection member140, a gap filler150, and an upper package160.

The first package substrate110may be a supporting substrate of the semiconductor package100and may include a first body layer111, a lower passivation layer113d, and an upper passivation layer113u. The first body layer111may include a wiring of at least one layer therein. In a case where the wiring is formed of a multilayer, wirings of different layers may be connected to each other through a vertical contact. According to an embodiment, the first body layer111may include a through via which directly connects a substrate pad, disposed on a top surface thereof, to a substrate pad disposed on a bottom surface thereof. The first body layer111may be formed based on, for example, a ceramic substrate, a printed circuit board (PCB), a glass substrate, or an interposer substrate. According to an embodiment, the first body layer111may be formed based on an active wafer such as a silicon wafer. The first body layer111may have a first thickness D1. The first thickness D1may be, for example, about 100 μm to about 200 μm. However, the first thickness D1is not limited to this numerical range. Terms such as “about” or “approximately” may reflect amounts, sizes, orientations, or layouts that vary only in a small relative manner, and/or in a way that does not significantly alter the operation, functionality, or structure of certain elements. For example, a range from “about 0.1 to about 1” may encompass a range such as a 0%-5% deviation around 0.1 and a 0% to 5% deviation around 1, especially if such deviation maintains the same effect as the listed range.

The lower passivation layer113dmay be disposed on the bottom surface of the first body layer111, and the upper passivation layer113umay be disposed on the top surface of the first body layer111. The lower passivation layer113dand the upper passivation layer113umay include or may be formed of, for example, solder resist (SR). However, a material of each of the lower passivation layer113dand the upper passivation layer113uis not limited to SR. Each of the lower passivation layer113dand the upper passivation layer113umay have a second thickness D2. The second thickness D2may be, for example, about 10 μm to about 15 μm. However, the second thickness D2is not limited to this numerical range.

A substrate pad may be formed on each of the bottom surface and the top surface of the first body layer111, and a connection member may be disposed on the substrate pad. For example, an external connection member115such as a bump or a solder ball may be disposed on the bottom surface of the first body layer111, and the first connection member140may be disposed on the top surface of the first body layer111. InFIG.1, although the external connection member115is illustrated as being disposed on the lower passivation layer113d, the external connection member115may be electrically connected to the substrate pad on the bottom surface of the first body layer111through the lower passivation layer113d. The first connection member140will be described below in more detail in describing the first connection member140.

As seen inFIG.2B, in the upper passivation layer113u, a center portion thereof may be removed, and only an outer portion thereof may be maintained (i.e., remain) on the top surface of the first body layer111. Based on a shape of the upper passivation layer113u, the first package substrate110may include a first trench T1in a top surface thereof. The first trench T1may be formed by removing part of the upper passivation layer113u, and thus, a depth of the first trench T1may correspond to the second thickness D2of the upper passivation layer113u. For reference, for convenience of illustration, the first connection member140is omitted inFIG.2B, and the first connection member140is illustrated inFIG.2C.

The first semiconductor chip130may be disposed in the first trench T1, and thus, a width of the first trench T1may be one which enables the first trench T1to sufficiently accommodate the first semiconductor chip130. For example, a width of the first trench T1in a first direction (an x direction) and a width of the first trench T1in a second direction (a y direction) may respectively be greater than a width of the first semiconductor chip130in the first direction (the x direction) and a width of the first semiconductor chip130in the second direction (the y direction). In some embodiments, the first semiconductor chip130may be disposed on a region of the first package substrate110where the first trench T1is formed. Depending on a size of a third connection member132which is formed on a bottom surface of the first semiconductor chip130, the bottom surface of the first semiconductor chip130may be lower or higher than a top surface of the upper passivation layer113u.

The second package substrate120may be a supporting substrate of the upper package160and may include a second body layer121, a lower passivation layer123d, and an upper passivation layer123u. In the semiconductor package100according to the present embodiment, the second package substrate120may be used for converting or transferring an input electrical signal between the first package substrate110and the upper package160. Therefore, the second package substrate120may not include elements such as an active element or a passive element. In terms of an arrangement position and a function of the second package substrate120, the second package substrate120may be referred to as an interposer. A PoP structure including an interposer may be referred to as an interposer PoP (iPoP).

The second body layer121may include or may be formed of, for example, one of silicon, an organic material, plastic, and glass. A material of the second body layer121is not limited to the materials. When the second body layer121includes or is formed of silicon, the second package substrate120may be referred to as a silicon interposer. For the second body layer121including or being formed of an organic material, the second package substrate120may be referred to as a panel interposer. In some embodiments, the number of panel interposers manufactured in a tetragonal disk including an organic material may be greater than the number of silicon interposers manufactured on one silicon wafer. For the second body layer121including or being formed of glass, the second package substrate120may be referred to as a glass interposer.

The second body layer121may include a wiring of at least one layer therein. In a case where the wiring is formed of a multilayer, wirings of different layers may be connected to each other through a vertical contact. According to an embodiment, the second body layer121may include a through via which directly connects a substrate pad, disposed on a top surface thereof, to a substrate pad disposed on a bottom surface thereof. According to an embodiment, the second body layer121may have a structure where a wiring layer is disposed at a lower portion thereof and a through via is disposed at an upper portion thereof. In such a structure, the through via may connect a substrate pad, disposed on the top surface of the second body layer121, to a wiring of a wiring layer, and the wiring of the wiring layer may be connected to a substrate pad on the bottom surface of the second body layer121. The second body layer121may have a third thickness D3. The third thickness D3may be, for example, about 80 μm to about 150 μm. However, the third thickness D3is not limited to this numerical range.

The lower passivation layer123dmay be disposed on the bottom surface of the second body layer121, and the upper passivation layer123umay be disposed on the top surface of the second body layer121. The lower passivation layer123dand the upper passivation layer123umay include or may be formed of, for example, SR. However, a material of each of the lower passivation layer123dand the upper passivation layer123uis not limited to SR. The lower passivation layer123dand the upper passivation layer123umay each have substantially the same thickness as that of each of the lower passivation layer113dand the upper passivation layer113u. For example, each of the lower passivation layer123dand the upper passivation layer123umay have a second thickness D2of about 10 μm to about 15 μm. However, the second thickness D2is not limited to this numerical range.

A substrate pad may be formed on each of the bottom surface and the top surface of the second body layer121, and a connection member may be disposed on the substrate pad. For example, the first connection member140may be disposed on the bottom surface of the second body layer121, and a second connection member162may be disposed on the top surface of the second body layer121. InFIG.1, although the second connection member162is illustrated as being disposed on the upper passivation layer123u, the second connection member162may be electrically connected to the substrate pad on the top surface of the second body layer121through the upper passivation layer123u.

The second package substrate120may include a second trench T2in a bottom surface thereof. The second trench T2of the second package substrate120may be formed by removing a center portion of the lower passivation layer123d. InFIG.2B, the first trench T1of the first package substrate110is illustrated, and in a case where a bottom surface of the second package substrate120is toward an upward direction, a shape of the second trench T2of the second package substrate120may be substantially the same as that of the first trench T1of the first package substrate110. The second trench T2may be formed by removing part of the lower passivation layer123d, and thus, a depth of the second trench T2may correspond to the second thickness D2of the lower passivation layer123d. The second trench T2may have substantially the same area as that of the first trench T1, and moreover, may be formed in the bottom surface of the second body layer121at a position facing the first trench T1with the first semiconductor chip130therebetween. In some embodiment, the first semiconductor chip130may be disposed between a region of the first package substrate110where the first trench T1is formed and a region of the second package substrate120wherein the second trench T2is formed.

The first semiconductor chip130may be mounted on a top surface of the first package substrate110. The first semiconductor chip130may be, for example, a logic chip. Here, the logic chip may include an application processor (AP), a microprocessor, a central processing unit (CPU), a controller, or an application specific integrated circuit (ASIC). The first semiconductor chip130may have a fourth thickness D4. The fourth thickness D4may be, for example, about 50 μm to about 150 μm. However, the fourth thickness D4is not limited to this numerical range.

As illustrated inFIGS.1to2A, the first semiconductor chip130may be disposed in the first trench T1in the top surface of the first package substrate110. In some embodiment, the first semiconductor chip130may be disposed on a region of the first package substrate110where the first trench T1is formed. The first semiconductor chip130may be electrically connected to the first package substrate110through a third connection member132, and an underfill134may be filled between the first semiconductor chip130and the first package substrate110and between third connection members132. According to an embodiment, instead of the underfill134, a first sealant136covering the first semiconductor chip130may be filled therein through a molded underfill (MUF) process.

The first semiconductor chip130may be sealed by the first sealant136. The first sealant136may include or may be formed of, for example, a resin such as an epoxy molding compound (EMC). A material of the first sealant136is not limited to the EMC. The first sealant136may fill at least a portion of each of the first trench T1and the second trench T2, cover a top surface and a side surface of the first semiconductor chip130, and cover the underfill134. The first sealant136may have a fifth thickness D5. The fifth thickness D5may be, for example, about 100 μm to about 200 μm. However, the fifth thickness D5is not limited to this numerical range.

A first gap G1may be maintained between the first semiconductor chip130and the second package substrate120. For example, a top surface of the first semiconductor chip130and a bottom surface of the second body layer121, which is exposed by the second trench T2, of the second package substrate120may be spaced apart from each other at the first gap G1. A portion corresponding to the first gap G1may be filled by the first sealant136. The first gap G1may be maintained between the first semiconductor chip130and the second package substrate120, and the first gap G1may be filled by the first sealant136, and thus, warpage of the semiconductor package100may be prevented. For example, the first sealant136may decrease stress caused by a difference in an expansion rate (e.g., a thermal expansion coefficient) between the first package substrate110, the second package substrate120, and the first semiconductor chip130. The first gap G1may have, for example, a size equal to the second thickness D2corresponding to a depth of the second trench T2. However, a size of the first gap G1is not limited thereto. For example, the first gap G1may be maintained in an appropriate size on the basis of reduction in a height of the semiconductor package100and the amount of warpage.

The first connection member140may be disposed between the first package substrate110and the second package substrate120and may electrically connect the first package substrate110to the second package substrate120. As seen inFIG.2C or3B, the first connection member140may be disposed on the top surface of the first package substrate110outside the first semiconductor chip130or the first trench T1. In terms of the second package substrate120, the first connection member140may be disposed on the bottom surface of the second package substrate120outside the first semiconductor chip130or the second trench T2.

The first connection member140may include a first pillar141, a second pillar143, and a solder145. The first pillar141may be connected to the substrate pad on the top surface of the first package substrate110, and the second pillar143may be connected to the substrate pad on the bottom surface of the second package substrate120. Each of the first pillar141and the second pillar143may have a cylindrical pillar or a polygonal pillar shape such as a tetragonal pillar shape or an octagonal pillar shape, which passes through a corresponding passivation layer of the first and second passivation layers113uand123d. Each of the first pillar141and the second pillar143may include or may be formed of, for example, nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), gold (Au), or a combination thereof. A material of each of the first pillar141and the second pillar143is not limited to these materials. In the semiconductor package100according to the present embodiment, each of the first pillar141and the second pillar143may include or may be formed of, for example, Cu.

The solder145may couple the first pillar141to the second pillar143and may have a spherical shape or a ball shape. The solder145may include or may be formed of, for example, tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and/or an alloy thereof. For example, the solder145may include or may be formed of Sn, Pb, Sn—Pb, Sn—Ag, Sn—Au, Sn—Cu, Sn—Bi, Sn—Zn, Sn—Ag—Cu, Sn—Ag—Bi, Sn—Ag—Zn, Sn—Cu—Bi, Sn—Cu—Zn, or Sn—Bi—Zn. However, a material of the solder145is not limited to these materials.

In the semiconductor package100according to the present embodiment, a plurality of first connection members140may be arranged at fine pitch. The plurality of first connection members140may be arranged at, for example, a fine pitch of about 30 μm to about 50 μm. According to an embodiment, the plurality of first connection members140may be arranged at a fine pitch of about 10 μm to about 30 μm. A fine pitch between the first connection members140will be described in more detail in describing an overall good characteristic of the semiconductor package100according to the present embodiment. A plurality of first connection members140, as illustrated inFIGS.2C and3B, may be arranged in three columns at opposite sides in the first direction (the x direction) with the first semiconductor chip130therebetween and may be arranged in one row at opposite sides in the second direction (the y direction). However, the arrangement form of the first connection members140is not limited thereto.

The gap filler150may be disposed between the first package substrate110and the second package substrate120and between adjacent first connection members140. The gap filler150may fill the second gap G2between the first package substrate110and the second package substrate120at portions where the first connection members140are disposed. Here, the second gap G2may correspond to a value obtained by subtracting a sum of the first and second trenches T1and T2from the fifth thickness D5of the first sealant136. For example, the gap filler150may fill a space between the upper passivation layer113uof the first package substrate110and the lower passivation layer123dof the second package substrate120and may surround at least some portions of the first connection members140. The gap filler150may fill spaces between two adjacent first connection members140.

As seen inFIGS.3A and3B, the gap filler150may be disposed on the upper passivation layer113uof the first package substrate110at opposite sides of the first semiconductor chip130or the first trench T1in the first direction (the x direction) and may extend in the second direction (the y direction). For example, the gap filler150may have a rectangular shape, which is long in the second direction (the y direction). However, a shape of the gap filler150is not limited to a rectangular shape. Various shapes of the gap filler150will be described below in more detail with reference toFIGS.4A to4C. As illustrated inFIG.2A or3A, a width of the gap filler150in the first direction (the x direction) may be substantially the same as a width of the upper passivation layer113uin the first direction (the x direction), at opposite sides of the first trench T1in the first direction (the x direction). However, according to an embodiment, a width of the gap filler150in the first direction (the x direction) may be less than a width of the upper passivation layer113uin the first direction (the x direction).

For reference, for convenience of illustration, the first connection member140is omitted inFIG.3A, and the first connection member140is illustrated inFIG.3B. The gap filler150is illustrated as being disposed on the upper passivation layer113uof the first package substrate110, and according to some embodiments, the gap filler150may be illustrated as being disposed on the lower passivation layer123dof the second package substrate120.

The gap filler150may not be disposed on the upper passivation layer113uof each of opposite end portions of the first package substrate110, outside the first semiconductor chip130or the first trench T1in the second direction (the y direction). Therefore, the opposite end portions of the first package substrate110may maintain an empty space. Each of the opposite end portions of the first package substrate110in the second direction may act as an injection path IP through which the first sealant136is injected. For example, the first semiconductor chip130may be mounted on the first package substrate110and the second package substrate120may be stacked on the first package substrate110through the first connection member140and the gap filler150, and then, the first sealant136may seal the first semiconductor chip130by injecting the first sealant136, such as an EMC, through the injection path IP of each of the opposite end portions of the first package substrate110in the second direction.

The gap filler150may include or may be formed of a material which differs from that of the first sealant136. For example, the gap filler150may include or may be formed of a nonconductive film (NCF), a nonconductive paste (NCP), or SR. However, a material of the gap filler150is not limited thereto. The gap filler150may be formed prior to forming the first sealant136. For example, an upper connection member of the first package substrate110and a lower connection member of the second package substrate120may be formed, and then, the gap filler150may be formed to cover a corresponding connection member in one of the first package substrate110and the second package substrate120. Here, the upper connection member may include the first pillar141, and the lower connection member may include the second pillar143and the solder145. However, according to an embodiment, instead of the lower connection member, the upper connection member may include a solder, or each of the lower connection member and the upper connection member may include a solder.

The gap filler150may perform the following function as well as a function of filling a region between the first package substrate110and the second package substrate120to support the first package substrate110and the second package substrate120. First, in a case where the second package substrate120is stacked on the first package substrate110through a temperature compression bonding (TCB) process, the gap filler150may prevent a short circuit between the first connection members140. Here, the TCB process may denote that the second package substrate120is stacked on the first package substrate110by applying certain pressure thereto at a high temperature (for example, about 200° C. to about 300° C.). Through the TCB process, the upper connection member of the first package substrate110may be coupled to the lower connection member of the second package substrate120, and thus, the first connection member140may be formed. In the TCB process, a solder may flow with fluidity on the basis of melting (i.e., the molten solder may be flowable), and thus, may contact an adjacent solder, causing defects such as a short circuit, deformation, and non-wetting. Here, non-wetting may denote that a solder is separated from a pillar, and an open defect may occur due to non-wetting. However, in the semiconductor package100according to the present embodiment, the gap filler150may be previously disposed on the upper connection member or the lower connection member, and thus, the flow of the solder145may be minimized in the TCB process, thereby preventing defects such as a short circuit, solder deformation, and non-wetting. It will be understood that when an element is referred to as being “connected” or “coupled” to or “on” another element, it can be directly connected or coupled to or on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as “contacting” or “in contact with” another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.).

Subsequently, in a process of injecting the first sealant136to seal the first semiconductor chip130, the gap filler150may prevent a short circuit, solder deformation, and non-wetting from occurring in the first connection members140due to the penetration of the first sealant136(i.e., flow of the first sealant136) into a region between the first connection members140. In a process of injecting the first sealant136, the first sealant136may maintain a high temperature (e.g., a temperature above the melting temperature of the first sealant136) so that the first sealant136is injected with fluidity. In a case where the first sealant136having a high temperature penetrates or flows into spaces between the first connection members140, flow based on melting of a solder may occur, and due to this, a defect such as a short circuit, solder deformation, or non-wetting may occur in the first connection members140. However, in the semiconductor package100according to the present embodiment, the gap filler150may previously fill a region between the first connection members140, and thus, the first sealant136may not penetrate the spaces between the first connection members140, thereby avoiding the problems described above. The first trench T1of the first package substrate110and the second trench T2of the second package substrate120may perform a function like a dam which blocks flow of the first sealant136, and thus, may more effectively prevent the first sealant136from penetrating or flowing into spaces between the first connection members140, along with the gap filler150.

For reference, as described above, the gap filler150may not be disposed at the opposite end portions of the first package substrate110in the second direction. However, as illustrated inFIG.2C or3B, the first connection members140of one row may be disposed at the opposite end portions of the first package substrate110in the first direction, and thus, defects of the first connection members140caused by the injection of the first sealant136may be minimized. For example, defects of the first connection members140caused by the injection of the first sealant136may occur in a direction (e.g., in the second direction) in which the first sealant136flows. However, the first connection members140of one row may be disposed at the opposite end portions of the first package substrate110in the first direction, and as seen through the arrow of the injection path IP ofFIG.3A, the first sealant136may be injected to be vertical to a direction (e.g., in the first direction) in which the first connection members140are arranged, thereby minimizing defects of the first connection members140caused by the penetration of the first sealant136.

The upper package160may be mounted on the second package substrate120by using the second connection member162. The upper package160may include an upper substrate161, a chip stack portion163, a third connection member165, and a second sealant169.

The upper substrate161may include a wiring substrate, and thus, may have a structure similar to that of the first package substrate110. The upper substrate161may be formed to have a size and a thickness, which are less than those of the first package substrate110. According to an embodiment, the upper substrate161may be formed based on an active wafer such as a silicon wafer.

The chip stack portion163may be stacked on the upper substrate161by using the third connection member165and may include at least one second semiconductor chip. In the semiconductor package100according to the present embodiment, the chip stack portion163may include four second semiconductor chips163c. However, the number of second semiconductor chips of the chip stack portion163is not limited thereto. For example, the chip stack portion163may include one to three or five or more second semiconductor chips. The second semiconductor chip163cmay include a volatile memory semiconductor chip, such as dynamic random access memory (DRAM) or static random access memory (SRAM), or a non-volatile memory chip such as flash memory, phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (RRAM). In the semiconductor package100according to the present embodiment, the second semiconductor chip163cmay include a DRAM chip.

The second semiconductor chip163cmay be stacked on a second semiconductor chip163cof a corresponding lower portion through an adhesive layer163p. A second semiconductor chip163cof a lowermost portion may be stacked on the upper substrate161through the third connection member165and the underfill167. According to an embodiment, instead of the underfill167, the adhesive layer163pmay be disposed between the upper substrate161and the lowermost second semiconductor chip163c. Although not shown, the second semiconductor chip163cmay include a through silicon via (TSV), except for the uppermost second semiconductor chip163c. Therefore, the second semiconductor chip163cmay be electrically connected to the upper substrate161or a second semiconductor chip163cof a corresponding lower portion through the TSV, a bump, and the third connection member165. The adhesive layer163pmay surround a bump between adjacent second semiconductor chips163c.

According to an embodiment, the upper package160may have a structure where at least one second semiconductor chip163cis mounted on the upper substrate161through a wire bonding structure. In a case where the upper package160has such a structure, the third connection member165may not be disposed between the upper substrate161and the second semiconductor chip163cof the lowermost portion. The second semiconductor chip163cmay not include a TSV. The second semiconductor chip163cmay be electrically connected to the upper substrate161through a bonding wire, and the adhesive layer163pmay attach the second semiconductor chip163cto the upper substrate161and may attach each second semiconductor chip163cto a corresponding second semiconductor chip163c. Furthermore, in the wire bonding structure, a plurality of second semiconductor chips163cmay be stacked in a staircase structure or a zigzag structure.

The second sealant169may cover a side surface and a top surface of the chip stack portion163on the upper substrate161. The second sealant169may cover a side surface of the underfill167. According to an embodiment, the second sealant169may not cover a top surface of the chip stack portion163, for example, a top surface of the uppermost second semiconductor chip163cof the chip stack portion163. Therefore, the top surface of the uppermost second semiconductor chip163cmay be externally exposed from the second sealant169. The second sealant169may include or may be formed of, for example, an EMC. However, a material of the second sealant169is not limited to the EMC.

In the semiconductor package100according to the present embodiment, the first semiconductor chip130may be disposed between the first and second trenches T1and T2formed in the first and second package substrates110and120, and the gap filler150including or being formed of a material which differs from that of the first sealant136may surround the first connection member140between the first and second package substrates110and120to implement a fine pitch of the first connection members140and to decrease a total height of a package. In the semiconductor package100according to the present embodiment, a defect such as a short circuit, solder deformation, or non-wetting in the first connection member140may be prevented by the gap filler150. Accordingly, a semiconductor package having a PoP structure with enhanced reliability may be implemented.

To provide a more detailed description on a fine pitch of the first connection member140in the semiconductor package100according to the present embodiment, a pitch of connection members connecting package substrates may be adjusted based on a size of a gap between the package substrates and a structure of the connection member. For example, when a gap between package substrates is relatively large and a connection member includes only a solder, a pitch of the connection members may be based on an aspect ratio and a size of the solder. For example, in order to prevent a short circuit defect between connection members and prevent an open defect caused by non-wetting, an aspect ratio and a size of a solder have to be ensured, and thus, there is a limitation in decreasing a pitch of connection members.

On the other hand, in the semiconductor package100according to the present embodiment, the first and second trenches T1and T2may be formed in the first and second package substrates110and120and the first semiconductor chip130may be disposed between the first and second trenches T1and T2, and thus, a gap (e.g., the shortest distance) between the first and second package substrates110and120may decrease by a sum of depths of the first and second trenches T1and T2at a region where the first semiconductor chip130is disposed. For example, when a gap between conventional package substrates including no trench is about 100 μm to about 200 μm and a depth of each of the first and second trenches T1and T2of the first and second package substrates110and120is about 10 μm to about 15 μm, a gap (the shortest distance) between the first and second package substrates110and120may be 70 μm to 180 μm, which corresponds to a size obtained by decreasing 100 μm to 200 μm by 20 μm to 30 μm. The gap between the first and second package substrates110and120may correspond to a distance between a top surface of the upper passivation layer113uof the first package substrate110and a bottom surface of the lower passivation layer123dof the second package substrate120.

In the semiconductor package100according to the present embodiment, the first connection member140may have a structure including the first and second pillars141and143and the solder145, and the gap filler150may be filled in spaces between the first connection members140. Therefore, comparing a structure of a conventional connection member including only a solder, defective problems of a short circuit and non-wetting may be considerably reduced. Here, as described above, a short circuit and non-wetting may occur in a process of stacking the second package substrate120and a process of injecting the first sealant136. As a result, in the semiconductor package100according to the present embodiment, the first connection members140may be disposed to have the fine pitch described above on the basis of the reduction in a gap between the first and second package substrates110and120, a structure of the first connection member140, and the presence of the gap filler150.

A total height of the semiconductor package100may decrease by a depth of a sum of the first and second trenches T1and T2. For example, when the depth of each of the first and second trenches T1and T2is about 10 μm to about 15 μm, the total height of the semiconductor package100may decrease by about 20 μm to about 30 μm, which is a sum of the first and second trenches T1and T2.

FIGS.4A to4Care plan views illustrating various embodiments of a structure of a gap filler, based on the semiconductor package ofFIG.1Descriptions, which are the same as or similar to descriptions given above with reference toFIGS.1to3B, are briefly given below or omitted.

Referring toFIG.4A, in a structure of a gap filler150a, a semiconductor package100aaccording to the present embodiment may differ from the semiconductor package100ofFIG.1. For example, in the semiconductor package100aaccording to the present embodiment, a width in a first direction (e.g., an x direction) of opposite end portions of the gap filler150ain a second direction (e.g., a y direction) may be greater than a width in the first direction of the central portions of the gap filler150ain the second direction. For example, the gap filler150amay have a ‘[’-shape or a recessed portion at the central portions in the second direction. A gap between the gap fillers150ain the first direction (e.g., the x direction) at a portion corresponding to an injection path IP (e.g., at the opposite end portions of the gap filler150a) may be narrower than a gap between the gap fillers150ain the first direction at the central portions or a width of a first trench T1in the first direction (the x direction). A width, in the first direction (e.g., the x direction), of the gap filler150aat the opposite end portions thereof in the second direction (e.g., the y direction) may be greater than a width, in the first direction, of the gap filler150aat the central portions thereof in the second direction, and thus, the gap filler150aat the opposite end portions thereof may surround and protect more first connection members140, thereby decreasing defects such as a short circuit, solder deformation, and non-wetting of the first connection members140.

Referring toFIG.4B, in a structure of a gap filler150b, a semiconductor package100baccording to the present embodiment may differ from the semiconductor package100ofFIG.1. For example, in the semiconductor package100baccording to the present embodiment, a width in a first direction (an x direction) in one end portion of the gap filler150bin a second direction (a y direction) may be greater than a width of another portion thereof. For example, the gap filler150bmay have a ‘L’-shape. Based on such a structure of the gap filler150b, in a portion corresponding to an injection path IP, a gap between the gap fillers150bin the first direction (e.g., the x direction) may be narrower than a width of a first trench T1in the first direction (e.g., the x direction). A width of the gap filler150bat the one end portion thereof (for example, the end portion corresponding to the injection path IP) in the second direction (the y direction) may be greater than a width of the gap filler150bat the other portions in the second direction, and thus, the gap filler150bmay surround and protect more first connection members140, thereby decreasing defects such as a short circuit, solder deformation, and non-wetting of the first connection members140.

Referring toFIG.4C, in a structure of a gap filler150c, a semiconductor package100caccording to the present embodiment may differ from the semiconductor package100ofFIG.1. For example, in the semiconductor package100caccording to the present embodiment, the gap filler150cmay be disposed on an upper passivation layer113uof a first package substrate110at opposite sides of a first semiconductor chip130or a first trench T1in a first direction (e.g., an x direction), and may be disposed in a lattice shape between a plurality of first connection members140. For example, it may be seen that the first connection members140are disposed between adjacent portions of the gap filler150chaving a lattice shape. As illustrated, the gap filler150cmay not be disposed at a portion corresponding to an injection path IP.

The gap filler150chaving a lattice shape may include or may be formed of NCP. For example, the gap filler150cmay be formed by dispensing NCP into spaces between the first connection members140in a lattice shape by using a dispenser. In a process of stacking the second package substrate120and a process of injecting a first sealant136, the gap filler150chaving a lattice shape may surround and protect the first connection members140, thereby preventing defects such as a short circuit, solder deformation, and non-wetting of the first connection members140.

FIG.5is a cross-sectional view of a semiconductor package100dhaving a PoP structure according to an embodiment. Descriptions, which are the same as or similar to descriptions given above with reference toFIGS.1to3B, are briefly given below or omitted.

Referring toFIG.5, in a structure of a first connection member140a, the semiconductor package100daccording to the present embodiment may differ from the semiconductor package100ofFIG.1. For example, in the semiconductor package100daccording to the present embodiment, the first connection member140amay include only a solder. In the semiconductor package100daccording to the present embodiment, a gap filler150may fill in spaces between two adjacent first connection members of a plurality of first connection members140a, and thus, although the first connection member140aincludes only a solder, defects such as a short circuit, solder deformation, and non-wetting of the first connection members140amay be prevented in a process of stacking a second package substrate120and a process of injecting a first sealant136.

InFIG.5, the first connection member140amay have a solder single-layer structure including or being formed of one solder, but according to embodiments, the first connection member140amay include or may be formed of a solder multi-layer structure where a plurality of solders are stacked. As shown inFIG.3A, the gap filler150may have a rectangular shape which is long in a second direction (e.g., a y direction). However, the gap filler150is not limited thereto and may have a shape of one of the gap fillers150ato150cofFIGS.4A to4C.

FIGS.6A to8Bare cross-sectional views, perspective views, and plan views illustrating semiconductor packages having a PoP structure according to embodiments.FIGS.6B,7B, and8Bare perspective views illustrating a structure of a gap filler in semiconductor packages ofFIGS.6A,7A, and8A, andFIG.6Cis a plan view illustrating a structure of a gap filler in the semiconductor package ofFIG.6A. Descriptions, which are the same as or similar to descriptions given above with reference toFIGS.1to3B, are briefly given below or omitted.

Referring toFIGS.6A to6C, in a structure of each of an upper passivation layer of a first package substrate110aand a lower passivation layer of a second package substrate120a, a semiconductor package100eaccording to the present embodiment may differ from the semiconductor package100ofFIG.1. For example, in the semiconductor package100eaccording to the present embodiment, the first package substrate110amay include a first upper passivation layer113u-1and a second upper passivation layer113u-2on a top surface of a first body layer111, and the second package substrate120amay include a first lower passivation layer123d-1and a second lower passivation layer123d-2on a bottom surface of a second body layer121. The first upper passivation layer113u-1, the second upper passivation layer113u-2, the first lower passivation layer123d-1, and the second lower passivation layer123d-2may each include or may be formed of SR. However, a material of each of the first and second upper passivation layers113u-1and113u-2and the first and second lower passivation layers123d-1and123d-2is not limited to SR.

A first trench T1of the first package substrate110amay be formed by removing a center portion of each of the first upper passivation layer113u-1and the second upper passivation layer113u-2. In some embodiments, the first body layer111may be exposed via the first trench T1of the first package substrate110a. A second trench T2of the second package substrate120amay be formed by removing a center portion of each of the first lower passivation layer123d-1and the second lower passivation layer123d-2. In some embodiments, the second body layer121may be exposed via the second trench T2of the second package substrate120a. The first trench T1and the second trench T2may each have an area which enables the first semiconductor chip130to be accommodated thereinto. For example, the area of each of the first and second trenches T1and T2may be greater than that of the first semiconductor chip130.

In the semiconductor package100eaccording to the present embodiment, the second upper passivation layer113u-2and the second lower passivation layer123d-2may perform a function of a gap filler. For example, the second upper passivation layer113u-2and the second lower passivation layer123d-2may be referred to as a gap filler. As illustrated inFIG.6B, the second upper passivation layer113u-2may have a rectangular shape which is long in a second direction (e.g., a y direction), on the first upper passivation layer113u-1. Widths of the second upper passivation layer113u-2and the first upper passivation layer113u-1in a first direction (an x direction) may be substantially the same, at opposite sides of the first trench T1in the first direction (e.g., the x direction). However, according to an embodiment, a width of the second upper passivation layer113u-2in the first direction (the x direction) may be less than that of the first upper passivation layer113u-1in the first direction (the x direction). Although not shown, the second lower passivation layer123d-2may have substantially the same structure as that of the second upper passivation layer113u-2. Terms such as “same,” “equal,” “planar,” or “coplanar,” as used herein when referring to orientation, layout, location, shapes, sizes, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but are intended to encompass nearly identical orientation, layout, location, shapes, sizes, amounts, or other measures within acceptable variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise. For example, items described as “substantially the same,” “substantially equal,” or “substantially planar,” may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes.

According to embodiments, an upper passivation layer of the first package substrate110aand a lower passivation layer of the second package substrate120amay each have a multi-layer structure of three or more layers. In a case where the upper passivation layer of the first package substrate110aand the lower passivation layer of the second package substrate120aeach have a multi-layer structure of three or more layers, the first trench T1and the second trench T2may be formed by removing all of such multilayer, or may be formed by removing a portion of the multilayer. Some of upper layers of a multilayer may perform a function of a gap filler.

Furthermore, without a gap filler, the upper passivation layer of the first package substrate110aand the lower passivation layer of the second package substrate120aeach have a single-layer structure. In such a structure, the upper passivation layer and the lower passivation layer may be formed to have a thickness, which is sufficient to cover a thickness of a gap filler, and an upper portion of at least one of the upper passivation layer and the lower passivation layer may perform a function of a gap filler.

Referring toFIGS.7A and7B, in a semiconductor package100faccording to the present embodiment, a second trench may not separately be formed, and thus, the semiconductor package100faccording to the present embodiment may differ from the semiconductor package100eofFIG.6A. For example, in the semiconductor package100faccording to the present embodiment, the first package substrate110amay include a first upper passivation layer113u-1and a second upper passivation layer113u-2on a top surface of a first body layer111, and the second package substrate120amay include a first lower passivation layer123d-1aand a second lower passivation layer123d-2on a bottom surface of a second body layer121.

The first trench T1of the first package substrate110a, like the first package substrate110aofFIG.6A, may be formed by removing a center portion of each of the first upper passivation layer113u-1and the second upper passivation layer113u-2. The first trench T1may have an area which enables the first semiconductor chip130to be accommodated thereinto. However, as illustrated inFIG.7B, a separate trench may not be formed in the second package substrate120b. Therefore, the first lower passivation layer123d-1amay be formed on a whole bottom surface of the second body layer121of the second package substrate120b. In the semiconductor package100faccording to the present embodiment, the second upper passivation layer113u-2of the first package substrate110aand the second lower passivation layer123d-2of the second package substrate120bmay perform a function of a gap filler and may have a rectangular shape, which is long in the second direction (e.g., the y direction). For example, the second lower passivation layer123d-2may be disposed in a rectangular shape, which is long in the second direction (the y direction), on opposite outer portions of the first lower passivation layer123d-1ain a first direction (e.g., an x direction).

Referring toFIGS.8A and8B, in a structure of each of an upper passivation layer of a first package substrate110a, a semiconductor package100gaccording to the present embodiment may differ from the semiconductor package100ofFIG.1. For example, in the semiconductor package100gaccording to the present embodiment, the second package substrate120may be substantially the same as the second package substrate120of the semiconductor package100ofFIG.1. Therefore, the second package substrate120may include a lower passivation layer123don a bottom surface of a second body layer121.

In the semiconductor package100gaccording to the present embodiment, like the semiconductor package100eofFIG.6A, the first package substrate110cmay include a first upper passivation layer113u-1aand a second upper passivation layer113u-2aon a top surface of the first body layer111. However, a thickness of each of the first upper passivation layer113u-1aand the second upper passivation layer113u-2amay be thicker than that of each of the first upper passivation layer113u-1and the second upper passivation layer113u-2of the first package substrate110aof the semiconductor package100eofFIG.6A. For example, a sum of the thicknesses of the first upper passivation layer113u-1aand the second upper passivation layer113u-2amay be substantially the same as a sum of thicknesses of the gap filler150and the upper passivation layer113uof the semiconductor package100ofFIG.1.

A first trench T1of the first package substrate110cmay be formed by removing a center portion of each of the first upper passivation layer113u-1aand the second upper passivation layer113u-2a. A second trench T2of the second package substrate120amay be formed by removing a center portion of the lower passivation layer123d. The first trench T1and the second trench T2may each have an area which enables the first semiconductor chip130to be accommodated thereinto.

In the semiconductor package100gaccording to the present embodiment, the second upper passivation layer113u-2amay perform a function of a gap filler. For example, the second upper passivation layer113u-2amay be referred to as a gap filler. Therefore, as illustrated inFIG.8B, the second upper passivation layer113u-2amay have a rectangular structure which is long in a second direction (e.g., a y direction), on the first upper passivation layer113u-1a. According to embodiments, the first upper passivation layer113u-1aof the first package substrate110cmay have substantially the same thickness as that of the upper passivation layer113uof the first package substrate110of the semiconductor package100ofFIG.1, and the second upper passivation layer113u-2amay have substantially the same thickness as that of the gap filler150of the semiconductor package100ofFIG.1.

FIGS.9A to9Care plan views illustrating various embodiments of a structure of a gap filler, in one of the semiconductor packages ofFIGS.6A,7A, and8A. Descriptions, which are the same as or similar to descriptions given above with reference toFIGS.6A to8B, are briefly given below or omitted.

Referring toFIG.9A, in a structure of a second upper passivation layer113u-2bor a second lower passivation layer, a semiconductor package100haccording to the present embodiment may differ from the semiconductor package100eofFIG.6A. For example, in the semiconductor package100haccording to the present embodiment, a width in a first direction (e.g., an x direction) of opposite end portions of the second upper passivation layer113u-2bin a second direction (e.g., a y direction) may be greater than a width of another portion thereof. For example, the second upper passivation layer113u-2bmay have a ‘[’-shape. Based on such a structure of the second upper passivation layer113u-2b, in a portion corresponding to an injection path IP, a gap between second upper passivation layers113u-2bin the first direction (e.g., the x direction) may be narrower than a width of a first trench T1in the first direction (e.g., the x direction). A width of the second upper passivation layer113u-2bat the opposite end portions thereof in the second direction (e.g., the y direction) may be greater than a width of the second upper passivation layer113u-2bat the central portions in the second direction, and thus, the second upper passivation layer113u-2bmay surround and protect more first connection members140, thereby decreasing defects such as a short circuit, solder deformation, and non-wetting of the first connection members140.

Referring toFIG.9B, in a structure of a second upper passivation layer113u-2cor a second lower passivation layer, a semiconductor package100iaccording to the present embodiment may differ from the semiconductor package100eofFIG.6A. For example, in the semiconductor package100iaccording to the present embodiment, a width in a first direction (e.g., an x direction) at one end portion of the second upper passivation layer113u-2cin a second direction (e.g., a y direction) may be greater than a width of another portion thereof in the second direction. For example, the second upper passivation layer113u-2cmay have a ‘L’-shape. Based on such a structure of the second upper passivation layer113u-2c, in a portion corresponding to an injection path IP, a gap between second upper passivation layers113u-2cin the first direction (e.g., the x direction) at the one end portion of the second upper passivation layer113u-2cmay be narrower than a width of a first trench T1in the first direction (e.g., the x direction) at another portion. A width of the second upper passivation layer113u-2cat the one end portion thereof (for example, an end portion corresponding to the injection path IP) in the second direction (the y direction) may be greater than a width of the second upper passivation layer113u-2cat another portion, and thus, the second upper passivation layer113u-2cmay surround and protect more first connection members140, thereby decreasing defects such as a short circuit, solder deformation, and non-wetting of the first connection members140.

Referring toFIG.9C, in a structure of a second upper passivation layer113u-2dor a second lower passivation layer, a semiconductor package100jaccording to the present embodiment may differ from the semiconductor package100eofFIG.6A. For example, in the semiconductor package100jaccording to the present embodiment, the second upper passivation layer113u-2dmay be disposed on a first upper passivation layer113u-1of a first package substrate110at opposite sides of a first semiconductor chip130or a first trench T1in a first direction (an x direction), and may be disposed in a lattice shape between a plurality of first connection members140. For example, it may be seen that the first connection members140are disposed between adjacent portions of the second upper passivation layer113u-2dhaving a lattice shape. As illustrated, the second upper passivation layer113u-2dmay not be disposed at a portion corresponding to an injection path IP. In a process of stacking the second package substrate120and a process of injecting a first sealant136, the second upper passivation layer113u-2dhaving a lattice shape may surround and protect the first connection members140, thereby preventing defects such as a short circuit, solder deformation, and non-wetting of the first connection members140.

FIG.10is a cross-sectional view of a semiconductor package200having a PoP structure according to an embodiment. Descriptions, which are the same as or similar to descriptions given above with reference toFIGS.1to3B, are briefly given below or omitted.

Referring toFIG.10, the semiconductor package200according to the present embodiment may include a first redistribution wiring layer210and a second redistribution wiring layer220, instead of a first package substrate110and a second package substrate120, and may also include two upper packages260and270and a passive element280, and thus, may differ from the semiconductor package100ofFIG.1. For example, the semiconductor package200according to the present embodiment may include the first redistribution wiring layer210, the second redistribution wiring layer220, a first semiconductor chip230, a first connection member240, a gap filler250, first and second upper packages260and270, the passive element280, and a second sealant290.

The first redistribution wiring layer210may be disposed under the first semiconductor chip230, and chip pads of the first semiconductor chip230may be redistributed in an outer region of the first semiconductor chip230through the first redistribution wiring layer210. For example, the first redistribution wiring layer210may connect the chip pads of the first semiconductor chip230to an outer connection pad on a bottom surface of the first redistribution wiring layer210through a redistribution wiring, and thus, may rearrange the chip pads of the first semiconductor chip230on an area which is greater than the first semiconductor chip230. The first redistribution wiring layer210may include a first body layer211including or being formed of an insulating material such as a photo imagable dielectric (PID) resin, an upper passivation layer213uon a top surface of the first body layer211, and a lower passivation layer213don a bottom surface of the first body layer211. A redistribution wiring having a single-layer or multi-layer structure may be disposed in the first body layer211. The first redistribution wiring layer210may include a first trench T1which is formed by removing a center portion of the upper passivation layer213u.

An outer connection member215may be disposed on a bottom surface of the first redistribution wiring layer210. As illustrated inFIG.10, the outer connection member215may be disposed on a first portion, corresponding to a bottom surface of the first semiconductor chip230, and a second portion which is the outside of the first portion in a first direction (e.g., an x direction) and a second direction (e.g., a y direction). A package structure, where the outer connection member215is widely disposed outside a bottom surface of the first semiconductor chip230, may be referred to as a fan-out (FO) package structure. On the other hand, a package structure where an outer connection member is disposed on only a portion corresponding to a bottom surface of a first semiconductor chip, may be referred to as a fan-in (FI) package structure.

The second redistribution wiring layer220may be disposed on the first redistribution wiring layer210and the first semiconductor chip230. The second redistribution wiring layer220may be electrically connected to the first redistribution wiring layer210through the first connection member240. The second redistribution wiring layer220may include a second body layer221, an upper passivation layer223u, and a lower passivation layer223d. The second redistribution wiring layer220may include a second trench T2which is formed by removing a center portion of the lower passivation layer223d. A material or a structure of the second redistribution wiring layer220may be substantially the same as that of the first redistribution wiring layer210.

The first semiconductor chip230may be mounted in the first trench T1of the first redistribution wiring layer210. In some embodiments, the first semiconductor chip230may be mounted on a region of the first redistribution wiring layer210wherein the first trench T1is formed. The first semiconductor chip230may correspond to the first semiconductor chip130of the semiconductor package100ofFIG.1. The first semiconductor chip230may be mounted on the first redistribution wiring layer210through a second connection member232and an underfill234and may be sealed by a first sealant236. According to embodiments, the first semiconductor chip230may have a structure where a chip pad is directly connected to a redistribution wiring of the first redistribution wiring layer210without the second connection member232. For reference, a structure where the first redistribution wiring layer210is first formed and the first semiconductor chip230is mounted on the first redistribution wiring layer210through the second connection member232may be referred to as a chip last structure, and a structure where the first redistribution wiring layer210is formed on the first semiconductor chip230may be referred to as a chip first structure. A package structure including the first redistribution wiring layer210may be referred to as a wafer level package (WLP), and a package structure which includes a fan-out structure through the first redistribution wiring layer210may be referred to an FO-WLP.

The first connection member240may have a shape such as a through via as illustrated. However, a structure of the first connection member240is not limited thereto. For example, like the semiconductor package100ofFIG.1, the first connection member240may have a structure including a pillar and a solder, or like the semiconductor package100dofFIG.5, the first connection member240may have a structure including only a solder.

The gap filler250may correspond to the gap filler150of the first semiconductor package100ofFIG.1. Therefore, the gap filler250may include or may be formed of a material (for example, NCF, NCP, or SR) which differs from that of the first sealant236and may fill a plurality of first connection members240disposed between the first redistribution wiring layer210and the second redistribution wiring layer220outside the first semiconductor chip230. The gap filler250may have a rectangular shape which is long in a second direction (e.g., a y direction). However, the gap filler250is not limited thereto and may have a shape of one of the gap fillers150ato150cofFIGS.4A to4C.

The first sealant236may correspond to the first sealant136of the first semiconductor package100ofFIG.1. The first upper package260may be mounted on the second redistribution wiring layer220through a third connection member262. The first upper package260may correspond to, for example, the upper package160of the first semiconductor package100ofFIG.1. Therefore, the first upper package260may include at least one second semiconductor chip, and the second semiconductor chip may include, for example, a DRAM chip. However, the second semiconductor chip is not limited to the DRAM chip.

The second upper package270may be mounted on the second redistribution wiring layer220through a fourth connection member272. The second upper package270may include at least one third semiconductor chip. The third semiconductor chip may include a memory chip which differs from the second semiconductor chip. The third semiconductor chip may include, for example, an SRAM chip or a flash memory chip. However, the third semiconductor chip is not limited to the SRAM chip or the flash memory chip.

Although not shown, an underfill surrounding the third connection member262may be disposed between the first upper package260and the second redistribution wiring layer220. An underfill surrounding the fourth connection member272may be disposed between the second upper package270and the second redistribution wiring layer220. However, in a case where a second sealant290is formed through an MUF process, an underfill may be omitted.

The passive element280may be mounted on the second redistribution wiring layer220. The passive element280may include, for example, a two-terminal element such as a resistor element, an inductor element, or a capacitor element. The second sealant290may seal the first and second upper packages260and270and the passive element280on the second redistribution wiring layer220. The second sealant290may be formed of EMC like the second sealant169of the semiconductor package100ofFIG.1. However, a material of the second sealant290is not limited to the EMC.

In the semiconductor package200according to the present embodiment, the first semiconductor chip230may be disposed between the first and second trenches T1and T2formed in the first and second redistribution wiring layers210and220, and the gap filler250including a material which differs from that of the first sealant236may surround the first connection member240between the first and second redistribution wiring layers210and220, whereby a fine pitch of the first connection member240may be implemented and a total height of a package may decrease. In the semiconductor package200according to the present embodiment, a defect such as a short circuit, solder deformation, or non-wetting in the first connection member240may be prevented by the gap filler250. Accordingly, a semiconductor package having a PoP structure with enhanced reliability may be implemented.

FIGS.11A to17are cross-sectional views illustrating a method of manufacturing a semiconductor package having a PoP structure, according to an embodiment. The method of manufacturing a semiconductor package having a PoP structure according to an embodiment will be described below with reference toFIGS.11A to17in conjunction withFIGS.1to3B, and descriptions, which are the same as or similar to descriptions given above with reference toFIGS.1to3B, are briefly given below or omitted.

Referring toFIGS.11A and11B, the method of manufacturing a semiconductor package having a PoP structure according to an embodiment may include an operation of preparing a first package substrate110and a second package substrate120, an operation of forming a first trench T1in the first package substrate110, and an operation of forming a second trench T2in the second package substrate120. The first package substrate110and the second package substrate120may be the same as the first package substrate110and the second package substrate120of the semiconductor package100ofFIG.1described above.

The first trench T1and the second trench T2may be formed through a photolithography process using a photomask500as illustrated inFIG.11B. For example, an exposure process using the photomask500including an open region OA corresponding to the first and second trenches T1and T2may be performed on passivation layers113and123of the first and second package substrates110and120, and by removing an exposed region through a development process using a developer, the first and second trenches T1and T2may be formed in the first and second package substrates110and120.

Referring toFIG.12, a first pillar141may be formed on a top surface of the first package substrate110, and a second pillar143and a solder145may be formed on a bottom surface of the second package substrate120. As seen inFIG.2C, the first pillar141may be formed at a portion of an upper passivation layer113uoutside the first trench T1. The second pillar143and the solder145may be formed at a portion of a lower passivation layer123doutside the second trench T2. According to embodiments, a solder may be formed on the first pillar141instead of being formed on the second pillar143.

Referring toFIG.13, a first semiconductor chip130may be mounted in the first trench T1of a top surface of the first package substrate110. For example, the first semiconductor chip130may be mounted on a region of the first package substrate110where the first trench T1is formed. The first semiconductor chip130may be mounted on the first package substrate110through a third connection member132and an underfill134. As described above, in a case where a first sealant136is formed through an MUF process, the underfill134may be omitted. The first semiconductor chip130may be the same as the first semiconductor chip130of the semiconductor package100ofFIG.1described above.

Referring toFIG.14, a gap filler150may be formed at a portion of an upper passivation layer113uof the top surface of the first package substrate110. The gap filler150, as illustrated inFIG.3A, may have a rectangular shape which is long in a second direction (e.g., a y direction). However, the gap filler150is not limited thereto and may have a shape of one of the gap fillers150ato150cofFIGS.4A to4C.

The gap filler150may be formed to cover the first pillar141disposed in the upper passivation layer113u. The gap filler150may be formed on the second package substrate120instead of the first package substrate110. In this case, the gap filler150may be formed on a lower passivation layer123dof the second package substrate120and may be formed to cover the second pillar143and the solder145each disposed in the lower passivation layer123d.

Referring toFIG.15, the second package substrate120may be stacked on the first package substrate110through a TCB process. The first pillar141and the second pillar143may be coupled to each other through the solder145by stacking the second package substrate120on the first package substrate110to form a first connection member140. For example, the first connection member140may include the first pillar141, the second pillar142, and the solder145disposed therebetween. As described above, the flow of the solder145may be minimized by the gap filler150in the TCB process, thereby preventing defects such as a short circuit, solder deformation, and non-wetting.

Referring toFIG.16, the first semiconductor chip130may be sealed by injecting the first sealant136(for example, an EMC) through an injection path IP (see,FIGS.3A and3B). The first sealant136may fill the first and second trenches T1and T2and may cover a top surface and a side surface of the first semiconductor chip130and the underfill134. As described above, the gap filler150may prevent the first sealant136from penetrating (i.e., flowing into) spaces between the first connection members140in a process of injecting the first sealant136, thereby preventing defects such as a short circuit, solder deformation, and non-wetting from occurring in the first connection members140.

Referring toFIG.17, an upper package160may be mounted on a second package substrate120through a second connection member162. The upper package160may be the same as the upper package160of the semiconductor package100ofFIG.1described above. Subsequently, an external connection member115may be disposed on a bottom surface of the first package substrate110, and thus, the semiconductor package100ofFIG.1may be finished.

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.