Patent ID: 12230539

DETAILED DESCRIPTION

In the drawings, like reference numerals refer to like elements throughout, and the various features are not necessarily drawn to scale. In the following discussion and in the claims, the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are intended to be inclusive in a manner similar to the term “comprising”, and thus should be interpreted to mean “including, but not limited to . . . ” Also, the term “couple” or “couples” is intended to include indirect or direct electrical or mechanical connection or combinations thereof. For example, if a first device couples to or is coupled with a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via one or more intervening devices and connections.

FIG.1shows a microelectronic device100that includes multiple electronic components101(e.g., metal oxide semiconductor (MOS) transistors) disposed on or in a semiconductor substrate102. Although the example device100is an integrated circuit with multiple components101, other microelectronic device implementations can include a single electronic component. The semiconductor substrate102in one example is a silicon wafer, a silicon-on-insulator (SOI) substrate or other semiconductor structure. Isolation structures103are disposed on select portions of an upper surface or side of the substrate102. The isolation structures103can be shallow trench isolation (STI) features or field oxide (FOX) structures in some examples. The device100also includes a multi-layer metallization structure104,106disposed above the substrate102. The metallization structure includes a first dielectric structure layer104formed over the substrate102, as well as a multi-level upper metallization structure106. In one example, the first dielectric104structure layer is a pre-metal dielectric (PMD) layer disposed over the components101and the upper surface of the substrate102. In one example, the first dielectric structure layer104includes silicon dioxide (SiO2) deposited over the components101, the substrate102and the isolation structures103.

The example device100ofFIG.1includes a 6 layer upper metallization structure106with a first layer108, referred to herein as an interlayer or interlevel dielectric (ILD) layer. Different numbers of layers can be used in different implementations. In one example, the first ILD layer108, and the other ILD layers of the upper metallization structure106are formed of silicon dioxide (SiO2) or other suitable dielectric material. In certain implementations, the individual layers of the multi-layer upper metallization structure106are formed in two stages, including an intra-metal dielectric (IMD, not shown) sub layer and an ILD sublayer overlying the IMD sub layer. The individual IMD and ILD sublayers can be formed of any suitable dielectric material or materials, such as SiO2-based dielectric materials. Tungsten or other conductive contacts110extend through selective portions of the first dielectric structure layer104. The first ILD layer108, and the subsequent ILD layers in the upper metallization structure106include conductive metallization interconnect structures112, such as aluminum formed on the top surface of the underlying layer. In this example, the first layer108and the subsequent ILD layers also include conductive vias113, such as tungsten, providing electrical connection from the metallization features112of an individual layer to an overlying metallization layer. The example ofFIG.1includes a second layer114disposed over the first layer108. The ILD layer108includes conductive interconnect structures112and vias113. The illustrated structure includes further metallization levels with corresponding dielectric layers115,116and117, as well as an uppermost or top metallization layer118. The individual layers115-118in this example include conductive interconnect structures112and associated vias113. The substrate102, the electronic components101, the first dielectric structure layer104and the upper metallization structure106form a wafer or die120with an upper side or surface121. The upper side121of the metallization structure106in one example forms an upper side of the wafer or die120.

The top metallization layer118includes two example conductive features119, such as upper most aluminum vias. The conductive features119include a side or surface at the upper side121of the wafer or die120at the top of the uppermost metallization layer118. Any number of conductive features119may be provided. One or more of the conductive features119can be electrically coupled with an electronic component101. The upper ILD dielectric layer118in one example is covered by one or more passivation layers123(e.g., protective overcoat (PO) and/or passivation layers), for example, silicon nitride (SiN), silicon oxynitride (SiOxNy), or silicon dioxide (SiO2). In one example, the passivation layer or layers123include one or more openings that expose a portion of the conductive features119to allow electrical connection of the features119to corresponding contact structures.

In the example ofFIG.1, the microelectronic device100includes two contact structures122. The contact structures122extend outward (e.g., upward along the “Y” direction inFIG.1) from the upper side121of the metallization structure106. The individual contact structures122are electrically coupled with a corresponding one of the conductive features119. The individual contact structures122include a conductive seed layer124and a conductive structure126(e.g., a copper post or pillar). In certain examples, the seed layer124can be omitted. The conductive structure126is coupled with the conductive feature119of the metallization structure106, and extends outward from the upper side121of the metallization structure106.

The microelectronic device100also includes a repassivation layer128(e.g., a printed polymer material) disposed on the side121of the wafer120proximate a side of the conductive contact structure122, and a solder ball structure130connected to the conductive structure126. The conductive seed layer124is disposed at least partially on the corresponding conductive feature119. In one example, the conductive seed layer124includes titanium (Ti) or titanium tungsten (TiW). The individual contact structures also include a copper structure126that extends at least partially outward (e.g., upward inFIG.1) from the upper side121of the wafer or die120. In one example, the copper structure126provides a copper pillar or post for subsequent soldering to a substrate or chip carrier using the solder ball130. In one example, the lateral dimensions of the conductive seed layer124and the copper structure126(e.g., along the X-axis direction inFIG.1) are approximately equal to one another.

In one example, the deposited (e.g., printed) polymer material128is disposed on (e.g., extends to) a lateral side of the copper structure126. In another example, the printed polymer material128is spaced from at least one lateral side of the copper structure126. The printed polymer material128in certain examples provides a repassivation layer that protects the copper structure126and passivates the copper surface thereof. In addition, the printed polymer material128in certain examples mechanically strengthens the base of the copper pillar structure126during assembly to a carrier substrate (not shown). In one example, the printed polymer material128is a thermally cured material that includes one or more of a polyimide, a polybenzoxazole (PBO), an epoxy, or a bismaleimide. In another example, the printed polymer material128is an ultraviolet (UV) curable material that includes one or more of a pre-imidized polyimide, an epoxy, an acrylate, a blend or copolymer of epoxy and acrylic crosslinkers, a blend or copolymer of epoxy and phenolic crosslinkers, or a blend or copolymer of epoxy and vinyl crosslinkers. As used herein, a blend is a mixture of components that may or may not react to each other, and a copolymer is a system derived from two or more monomer species that react together. As detailed further below in connection withFIGS.2-15, the material128can be printed using a variety of additive deposition and curing steps, such as inkjet printing and thermal and/or UV curing, to improve material usage, mitigate copper migration, reduce production costs, and to facilitate extension to higher copper density while reducing the number of masks in production. As shown further below inFIG.12, the device100can also include a conductive redistribution layer and a second printed polymer material.

Referring also toFIGS.2A-16,FIGS.2A and2Bshows a method200of fabricating a microelectronic device, such as the device100ofFIG.1. The example method200advantageously provides ball-first processing in which a solder ball structure (e.g.,130inFIG.1) is attached to a side of the conductive structure126, and thereafter forming a repassivation layer (e.g., layer128inFIG.1) on the side of the wafer120proximate the side of the conductive structure126. In certain examples, the repassivation layer128is formed using printing or other additive manufacturing processing. Compared with spin-coded repassivation layer formation techniques, the example method200reduces production cost through enhanced repassivation layer material usage. In addition, the example method200mitigates or avoids missing solder ball defects due to non-fusion of solder caused by ink bleed out, solder ball cracking and stress concentration delamination as well as bleed out and edge roughness, compared with other processes that provide solder ball attachment after repassivation layer deposition. The example method200also includes die singulation and packaging of the device100to provide an integrated circuit product.FIGS.3-15illustrate processing at various intermediate stages of fabrication to produce the device100ofFIG.1according to the method200, andFIG.16shows an integrated circuit (IC) in the form of a packaged microelectronic device.

The method200inFIGS.2A and2Bincludes fabricating one or more electronic components on and/or in a substrate at202(FIG.2A). Any suitable semiconductor processing steps can be used at202in order to fabricate one or more electronic components on and/or in a semiconductor substrate102. For example, the processing at202can include fabricating one or more transistors101on and/or in the semiconductor substrate102via processing300inFIG.3. In one example, the fabrication processing at202includes fabrication of additional structural features, such as isolation structures103shown inFIG.3. The method200inFIG.2Afurther includes fabricating a metallization structure above the substrate at204(e.g., first dielectric structure layer104and an upper metallization structure106above the substrate102inFIG.3).FIG.3shows processing300used to fabricate the electronic components101and the metallization structures104,106. In certain examples, the metallization structure construction at204includes fabrication of one or more additional electronic components (e.g., resistors, inductors, capacitors, transformers, not shown) at least partially in the metallization structure106.

The method200further includes forming a passivation layer at206inFIG.2A.FIG.3shows one example, in which the processing300includes forming the passivation layer or layers123with openings that expose the upper portions of the conductive features119of the metallization structure106to allow electrical connection of the features119to subsequently formed contact structures. The method200inFIG.2Aalso includes forming a conductive seed layer at least partially on a conductive feature of the wafer120at208.FIG.3shows one example, in which the processing300includes a sputtering or electroplating deposition process that deposits the conductive seed layer124on the upper side121of the wafer120. In one example, a sputter deposition process forms a titanium or titanium tungsten material conductive seed layer124on the wafer side121, which extends at least partially on the conductive features119of the wafer120as shown inFIG.3. The processing at202-208in one example provides a wafer120as shown inFIG.3. At this point in the fabrication process200, the deposited seed layer material124also extends over the previously deposited passivation layer or layers123as shown inFIG.3.

Continuing at210-218, the example method200inFIG.2Aincludes forming a conductive structure126(e.g., a copper post or pillar) above the deposited seed layer124. One example includes performing a damascene process at214that deposits conductive material into an opening of a patterned photoresist to form the conductive structure126above the conductive feature119. This example includes forming a photoresist layer at210, and patterning the photoresist layer at212to form openings for pillars.FIG.4shows an example deposition process400that deposits and patterns a photoresist material layer402. The photoresist layer402in one example is patterned at212using a photolithography process that selectively removes portions of the photoresist material402to expose portions above the conductive features119of the wafer120. The lateral (e.g., X-axis) width of the openings in the photoresist layer402in one example is generally coextensive with the lateral width of the conductive features119of the wafer120, although not a requirement of all possible implementations.

The method200further includes forming a conductive material (e.g., copper) in the patterned openings at214. The conductive structure formation in one example includes depositing copper material at214on the exposed portion of the seed layer material124(if included) above the conductive feature119. Where no seed layer124is used, the conductive material is deposited on the exposed portions of the conductive feature119.FIG.5shows one example, including performing an electroplating deposition process500that forms the copper conductive structures126in the openings of the patterned photoresist402. The process500forms the copper structures126on the exposed portions of the conductive feature119of the wafer120or any intervening seed layer material124. The method200continues at216inFIG.2Awith removing the remaining resist layer.FIG.6shows a photoresist removal process600(e.g., selective etch) that removes the photoresist material402from the wafer120.

Although the example method200is illustrated and described above using a damascene type process to form the copper structures126using a patterned photoresist402, other processing steps can be used to form a conductive copper structure126on the seed layer124over the conductive feature119of the wafer120, or directly on the conductive feature119without using a seed layer. Moreover, although the illustrated example wafer120includes multiple conductive features119and corresponding contact structures122, other implementations are possible in which only a single contact structure122is formed, and further examples are possible in which more than two contact structures122are formed. The method200continues inFIG.2Awith a seed etch at218that removes exposed portions of any included seed layer124.FIG.7shows an example in which an etch process700is performed that etches the exposed seed layer124to expose a portion of the passivation layer or layers123.

Continuing inFIG.2B, the example method200provides ball-first processing, including attaching a solder ball structure130to a side of the conductive structure126at220and, after attaching the solder ball structure to the side the conductive structure126, forming a repassivation layer128at230on a side of the wafer120proximate the side of the conductive structure126. In one example, the solder ball attachment processing at220includes depositing flux on at least a portion of a side (e.g., the top) of the conductive structure126.FIG.8shows an example flux deposition process800that deposits flux material804on at least a portion of the tops of the conductive structures126using a mask802supported above the upper surface of the wafer120. The flux mask802is then removed automatically by processing equipment used to deposit the flux material804. The solder ball attachment continues at224inFIG.2B, including ball drop or ball placement.FIG.9shows an example ball drop process900that drops solder balls structures130to portions of the flux804in openings of a ball drop mask902supported above the upper surface of the wafer120. The ball drop mask902is then removed automatically by processing equipment used to place the solder balls130. At226inFIG.2B, the solder ball attachment processing220continues with thermal processing at226to reflow portions of the solder structure130.FIG.10shows an example thermal process1000that heats or otherwise reflows the solder ball structures130. The reflow processing at226in one example consumes all or at least a portion of the previously deposited flux material804. In the example ofFIG.10, slight amounts of residual flux804may remain after the thermal processing1000. The example method200inFIG.2Aalso includes an optional flux cleaning operation at228.FIG.11shows an example cleaning process1100that removes all or at least a portion of residual flux material. The ball attach processing at220attaches solder balls130to the top surfaces of the exposed portions of the conductive copper pillar structures126as shown inFIG.11.

The repassivation layer128is formed at230inFIG.2B. Any suitable deposition process can be performed at230. In one example, the processing at230includes performing a printing process at232that forms a printed polymer material128on a side of the wafer120proximate a side of the conductive structure126, as shown inFIGS.12-15.FIGS.12and13show an example in which an inkjet printing process1200is performed using a print head1202. The process1200selectively prints or deposits the printed polymer material128on predetermined exposed portions of the passivation layer123. As shown inFIG.12, the printing processing1200in one example prints the polymer repassivation material128proximate to (e.g., slightly spaced laterally from or engaging) the lateral sides of the copper pillar structures126, although a spaced relationship is not a requirement of all possible implementations.

Any suitable repassivation material and printing process can be used at232. In one example, a printable material128is used which has a viscosity of 10-30 cP, a surface tension of 20-40 mN/m, and a solids particle size of less than 200 nm, although not strict requirement of all possible implementations In one example, thermal-based inks are used, such as polyimide, epoxy, bismaleimide, where the thermal-based inks are solvent-diluted systems with a solids contents range of 20-35 wt % for thermal in situ and/or post-curing. In another example, UV-based inks are printed at232, such as pre-imidized polyimide, epoxy, acrylate, blend or copolymer of epoxy and acrylic crosslinkers, blend or copolymer of epoxy and phenolic crosslinkers, blend or copolymer of epoxy and vinyl crosslinkers, where the UV-based inks include UV initiators to start the polymerization. In some examples, the UV-based inks are solventless systems. In other examples, UV-based inks can be used which are solvent-diluted systems with solids contents between 20-35 wt %. In certain examples, post-cured UV-based inks can be used. In other examples, UV-based inks can be printed using a print head with a UV light source (e.g.,1206inFIG.12) to at least partially thermally cure (e.g., “pin”) the printed material128to the printed surface during printing, alone or in combination with subsequent final curing (e.g., at236inFIGS.2A and2B).

The printing processing at232advantageously economizes consumption of the printed repassivation material128, thereby reducing production costs and enhancing material usage in the fabrication process200, particularly compared with conventional spin-coat deposition approaches.FIG.12illustrates one example using an inkjet printer apparatus programmed according to a design layout of the wafer120, where the print head1202moves along a programmed path1204to selectively print the material128in desired locations on the top side of the wafer120. In one example, an initial curing function is implemented concurrently with the printing at232to at least partially cure the repassivation material128during printing. One example implementation includes heating the wafer120while performing the printing process at232to at least partially cure the printed polymer material128. In another example, the print head1202is equipped with an ultraviolet light source1206that emits ultraviolet light1208as shown inFIG.12during the printing process at232. This example includes exposing the polymer material128to ultraviolet light while performing the printing process to at least partially cure the polymer material128.

A single printed repassivation layer128can be formed in certain examples. In other examples, the printing processing includes performing multiple printing passes to deposit multiple layers of the polymer material128proximate the side of the conductive structure126. In one example, the process200further includes determining at234whether further passivation layers are desired. Multiple repassivation material layers128can be printed, for example, in order to control the final thickness of the repassivation material layer128for a given design. If a further passivation material layer is desired (YES at234), another repassivation layer is printed and optionally partially cured at232.FIGS.12and13show one example implementation, including printing a first layer of the polymer repassivation material128inFIG.12, followed by printing one or more additional layers using the process1200in order to form a multilayer repassivation material structure128as shown inFIG.13.

If no additional repassivation layers are desired (NO at234), the example method200continues at236inFIG.2B, with a final curing process that thermally cures the polymer material128, after performing the printing process1200.FIG.14shows the wafer120undergoing a final curing process1400that cures the printed polymer material128. In one example, the final cure process1400is a thermal process, for example, that heats the wafer120for a suitable duration at an appropriate temperature to cure the polymer material128. As shown inFIG.14, the final cure processing at236in one example adheres at least some of the printed polymer material128to the lateral sides of the conductive copper pillar structures126, for example, through wicking action. In another example, the final cure processing at236includes exposing the wafer120to ultraviolet light, for example, to cure a UV curable printed polymer material128. The example method200continues with a plasma cleaning step at238.FIG.15shows an example plasma cleaning process1500that moves any residual uncured polymer material128.

The method200also includes die singulation (e.g., separation of the wafer120into two or more dies) and packaging at240inFIG.2Bto provide a completed microelectronic device, whether including a single electronic component101, or an integrated circuit that includes multiple electronic components101, that includes a package structure that encloses the die120and provides electrical connection to the conductive contact structure122. The device can be used in a variety of different product configurations, such as fine pitch flip chip packages (e.g., FCBGA), flip chip on lead packages (e.g., FCOL), and wafer level chip scale packages (WLCSP), etc.FIG.16shows an example packaged flip chip ball grid array (FCBGA) integrated circuit (IC) device1601resulting from packaging processing1600using a singulated die from the wafer120ofFIG.15. The flip chip implementation uses small print head tips to print the passivation material (e.g., print head1202inFIG.12above). Lower resolution printing equipment can be used to print the passivation material128for WLCSP devices. The example IC1601inFIG.16includes the die120soldered to a substrate or carrier1602using the solder balls130. In one example, at240inFIG.2B, the die120is soldered to the carrier substrate1602using a surface mount technology (SMT) process that solders the solder balls130to conductive pads1604on an upper side of the carrier substrate1602. The reflow of the solder balls130creates a solder joint between the conductive copper pillar structures126of the die120and the conductive pads1604of the PCB1602. The IC1601also includes conductive pads1606located on the bottom side of the carrier substrate1602, along with corresponding solder balls1608to allow the IC1601to be soldered to an end-user printed circuit board (not shown).

In this example, the carrier substrate1602also includes capacitors or other electronic components1610soldered to the upper or top side of the carrier substrate1602, as well as additional exposed (e.g., lower side) electronic components (e.g., capacitors)1614on the bottom side of the carrier substrate1602. The finished IC1601inFIG.16also includes an underfill adhesive material1616(e.g., epoxy) that seals the soldered connection between the die120and the carrier substrate1602. In one example, the carrier substrate1602is a multilayer printed circuit board structure including a printed circuit board material, such as polyimide, glass-reinforced epoxy laminate material (e.g., flame retardant FR-4 material compliant with the UL94V-0 standard) or substrate build-up technology with Ajinomoto build-up film (ABF) dielectric layers laminated between copper layers above and below a rigid core material. The substrate1602can be a single layer structure or a multi-layer substrate in other examples. The substrate1602in one example includes plated through holes and/or micro-vias, some or all of which provide electrical interconnection between dielectric layers of a multi-layer structure. The substrate1602also includes traces or conductive routing features on a top side, a bottom side, and/or within or between internal layers selectively connected by conductive vias structures. The illustrated example includes conductive connections1605(e.g., aluminum and/or copper). The individual connections1605electrically connect one or more of the conductive pads1604on the upper side of the substrate1602to one or more associated conductive pads1606on the bottom side of the substrate1602. The connections1605include one or more of the trace layers and vias structures. The example IC1601also includes a lid or heat spreader structure1620(e.g., nickel plated copper, AlSiC, Al, etc.) mounted to a top surface of the die120via a thermal interface material (e.g., silicone gel, etc.)1618, along with a conductive or nonconductive lid seal adhesive1622that holds outer portions of the lid1620to the carrier substrate1602.

In another example, a packaged wafer level chip scale package (WLCSP) IC is created at240inFIG.2that includes the die120soldered to a host printed circuit board (PCB) using SMT processing that solders the solder balls130to conductive pads on an upper side of the PCB. In this example, a surface mount technology process is performed at240inFIG.2to reflow the solder balls130to create a solder joint between the conductive copper pillar structures126of the die120and the conductive pads of the PCB.

FIG.17shows an example packaged flip chip on lead (FCOL) IC1700. The IC1700is a molded package lead frame assembly that includes the die120soldered to leads of a conductive metal lead frame structure1702. The die120and the leadframe are encapsulated in a ceramic structure or a molded material1704, such as plastic. The lead frame1702and the material1704encloses the die120. Portions of the lead frame1702are not covered by the material1704to allow electrical connection of user circuit board pads to the conductive contact structure122when the IC1700is soldered to a host printed circuit board (not shown). The above examples are merely illustrative of several possible embodiments of various aspects of the present disclosure, wherein equivalent alterations and/or modifications will occur to others skilled in the art upon reading and understanding this specification and the annexed drawings. Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.