Patent ID: 12261219

DETAILED DESCRIPTION

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, in order to clearly express the components of each device, the sizes of the components, such as width and thickness of the components, are enlarged. The terms used herein may correspond to words selected in consideration of their functions in the embodiments, and the meanings of the terms may be construed to be different according to the ordinary skill in the art to which the embodiments belong. If expressly defined in detail, the terms may be construed according to the definitions. Unless otherwise defined, the terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong.

In addition, expression of a singular form of a word should be understood to include the plural forms of the word unless clearly used otherwise in the context. It will be understood that the terms “comprise”, “include”, or “have” are intended to specify the presence of a feature, a number, a step, an operation, a component, an element, a part, or combinations thereof, but not used to preclude the presence or possibility of addition one or more other features, numbers, steps, operations, components, elements, parts, or combinations thereof.

Further, in performing a method or a manufacturing method, each process constituting the method can take place differently from the stipulated order unless a specific sequence is described explicitly in the context. In other words, each process may be performed in the same manner as the stated order, and may be performed substantially at the same time. Also, at least a part of each of the above processes may be performed in a reversed order.

FIG.1is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present disclosure. Referring toFIG.1, a semiconductor device1may include a substrate101, a ferroelectric layer110disposed on the substrate101, a gate insulation layer120disposed on the ferroelectric layer110, metal particles130disposed in an inner region of the gate insulation layer120, and a gate electrode layer140disposed on the gate insulation layer120. In addition, the semiconductor device1may further include a source region103and a drain region105, which are disposed in regions of the substrate101opposite to each other (e.g., in an x-direction) with respect to the gate electrode layer140.

The substrate101may include a semiconductor material. As an example, the semiconductor material may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. The substrate101may be doped with an N-type or P-type dopant to have electrical conductivity.

The source region103and the drain region105may be disposed to be spaced apart from each other in the x-direction. Each of the source region103and the drain region105may be a region of the substrate101doped with a dopant that is different from the dopant in the remainder of the substrate101. For example, when the substrate101is doped with a P-type dopant, the source region103and the drain region105may be doped with an N-type dopant. In another example, when the substrate101is doped with an N-type dopant, the source region103and the drain region105may be doped with a P-type dopant.

A channel region101cmay be disposed in a region of the substrate101between the source region103and the drain region105. The channel region101cmay be located adjacent to an upper surface of the substrate101and directly under the ferroelectric layer110. A conductive channel electrically connecting the source region103and the drain region105to each other may be formed in the channel region101caccording to a voltage applied to the gate electrode layer140. An electrical resistance of the conductive channel may vary depending on a magnitude and orientation of remanent polarization stored in the ferroelectric layer110.

The ferroelectric layer110may be disposed on or over the substrate101, for example in a vertical or z-direction. The ferroelectric layer110may include a ferroelectric material. The ferroelectric material may have spontaneous electrical polarization. The ferroelectric material may exhibit hysteresis behavior with respect to polarization based on a write voltage applied between the gate electrode layer140and the substrate101. The ferroelectric material may have predetermined polarization according to a polarization hysteresis curve in response to the write voltage. Even after the write voltage is removed, the ferroelectric material may maintain the remanent polarization corresponding to the predetermined polarization. The remanent polarization may function as signal information in the semiconductor device1and may be stored in a non-volatile manner in the ferroelectric layer110. That is, the ferroelectric layer110may function as a memory layer of the semiconductor device1.

In an embodiment, the ferroelectric layer110may include metal oxide having a crystal structure of an orthorhombic system as the ferroelectric material. The metal oxide may include, for example, hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination of two or more thereof. In an embodiment, the ferroelectric layer110may include a dopant that is doped into the ferroelectric material. The dopant may include, for example, carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), gadolinium (Gd), lanthanum (La), or a combination thereof. In an embodiment, the dopant may help the ferroelectric layer110maintain the crystal structure of an orthorhombic system, thereby stabilizing the ferroelectric properties of the ferroelectric layer110.

In another embodiment, the ferroelectric layer110may include metal oxide having a perovskite structure as the ferroelectric material. The metal oxide may include, for example, barium titanium oxide (BaTiO3), lead titanium oxide (PbTiO3), barium strontium titanium oxide ((Ba,Sr)TiO3, BST), lithium niobium oxide (LiNbO3), or the like.

Referring toFIG.1, the gate insulation layer120may be disposed on the ferroelectric layer110. The gate insulation layer120may include a dielectric material. The gate insulation layer120may have a non-ferroelectric property. Here, a non-ferroelectric property may mean an absence of ferroelectricity, and may mean, for example, paraelectricity or antiferroelectricity. The gate insulation layer120may include, for example, oxide, nitride, oxynitride, or a combination of two or more thereof. Specifically, the gate insulation layer120may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, yttrium oxide, or the like. The gate insulation layer120may be thinner than the ferroelectric layer110.

The hafnium oxide and the zirconium oxide used in the gate insulation layer120may each have a crystal structure of a monoclinic crystal system or a tetragonal crystal system, and as a result may exhibit non-ferroelectric properties. On the other hand, the hafnium oxide and the zirconium oxide used in the ferroelectric layer110may each have a crystal structure of an orthorhombic crystal system and thereby exhibit ferroelectricity.

In an embodiment, the permittivity of the gate insulation layer120may be lower than that of the ferroelectric layer110. For example, the permittivity of the dielectric material constituting the gate insulation layer120may be lower than that of the ferroelectric material constituting the ferroelectric layer110.

Referring toFIG.1, the metal particles130may be embedded in an inner region of the gate insulation layer120. The metal particles130may be distributed on an upper side of a plane120aspaced apart from an interface115S between the ferroelectric layer110and the gate insulation layer120by a distance d. The plane120aon which the metal particles130are distributed may be parallel to the interface115S between the ferroelectric layer110and the gate insulation layer120.

In an embodiment, the distance d may be, for example, greater than 0 and less than or equal to half (½) of a thickness t of the gate insulation layer120. Accordingly, the metal particles130may be disposed closer to the ferroelectric layer110than the gate electrode layer140with respect to the z-direction, or the metal particles130may be arranged equidistant from the gate electrode layer140and the ferroelectric layer110with respect to the z-direction. In some embodiments, the metal particles do not contact an interface between the gate insulation layer120and either the ferroelectric layer110or the gate electrode layer140. The metal particles may be entirely embedded within the gate insulation layer.

The metal particles130may have a form in which metal atoms are aggregated. The metal particles130may each have a spherical or sphere-like shape. However, the present disclosure is not necessarily limited thereto, and other three-dimensional shapes are possible. In an embodiment, a diameter of the metal particle130having a spherical shape may have a size of 0.1 nanometers (nm) to 5 nm, for example. The metal particles130may include, for example, cobalt (Co), nickel (Ni), copper (Cu), iron (Fe), platinum (Pt), gold (Au), silver (Ag), iridium (Ir), ruthenium (Ru), palladium (Pd), manganese (Mn), or a combination of two or more thereof. As will be described later with reference toFIGS.2A to2D, the metal particles130may function as trap sites that trap or de-trap electrons during an operation of the semiconductor device.

Referring toFIG.1again, the gate electrode layer140may be disposed on the gate insulation layer120. The gate electrode layer140may include a conductive material. The conductive material may include, for example, doped semiconductor, metal, conductive metal nitride, conductive metal carbide, conductive metal silicide, or conductive metal oxide. The conductive material may include, for example, silicon (Si) doped with an n-type or p-type dopant, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof.

In some embodiments, although not illustrated inFIG.1, an interfacial insulation layer may be additionally disposed between the substrate101and the ferroelectric layer110. The interfacial insulation layer may function as a buffer layer for alleviating a lattice constant difference between the substrate101and the ferroelectric layer110.

As described above, the semiconductor device1according to an embodiment of the present disclosure may be a nonvolatile memory device in the form of a field effect transistor including the ferroelectric layer110and the gate insulation layer120. The semiconductor device1may include the metal particles130disposed in an inner region of the gate insulation layer120. As will be described in connection withFIGS.2A to2D, and3, the embedded metal particles130may increase the operation voltage range of the semiconductor device1, that is, a memory operation window, by trapping or de-trapping electrons.

In addition, the metal particles130may generate strain inside the gate insulation layer120. The strain may generate a flexoelectric effect in the gate insulation layer120. The flexoelectric effect may improve the degree of polarization alignment of the gate insulation layer120along an external electric field when the external electric field is applied to the gate insulation layer120. As the alignment degree of the polarization is improved, the permittivity of the gate insulation layer120may increase. As a result, the capacitance of the gate insulation layer120may be improved.

Referring toFIG.1again, the ferroelectric layer110and the gate insulation layer120may be electrically connected in series to each other between the substrate101and the gate electrode layer140. Accordingly, when an operation voltage V is applied between the substrate101and the gate electrode layer140, the product of a capacitance C110 (not illustrated) of the ferroelectric layer110and a voltage V110 (not illustrated) applied to the ferroelectric layer110may be equal to the product of a capacitance C120 (not illustrated) of the gate insulation layer120and a voltage V120 (not illustrated) applied to the gate insulation layer120.
C110*V110=C120*V120  (1)

When Equation (1) holds, if the capacitance of the gate insulation layer120increases according to an embodiment of the present disclosure, the voltage V120 applied to the gate insulation layer120may decrease, and instead, the voltage V110 applied to the ferroelectric layer110may increase.

Accordingly, when the operation voltage V is applied between the substrate101and the gate electrode layer140, the magnitude of the voltage V120 distributed to the gate insulation layer120having a smaller thickness than the ferroelectric layer110decreases, so that a breakdown voltage of the semiconductor device1by the operation voltage V may be improved. In addition, when the operation voltage V is applied, the magnitude of the voltage V110 distributed to the ferroelectric layer110increases, so that the alignment degree of the polarization written in the ferroelectric layer110may be improved. Additionally, the magnitude of the voltage V120 applied to the gate insulation layer120decreases, so that charge injection (e.g., electron inflow) from the gate insulation layer120to the ferroelectric layer110may decrease. In a comparative example, electrons flowing into the ferroelectric layer110from the gate insulation layer120may be pinned to ferroelectric domains or defect sites inside the ferroelectric layer110, thereby preventing polarization switching of the ferroelectric layer110. Accordingly, the ferroelectric properties of the ferroelectric layer110may deteriorate. In an embodiment of the present disclosure, in contrast, the charge injection from the gate insulation layer120to the ferroelectric layer110is reduced, so the endurance of the ferroelectric layer110improves, thereby improving the reliability of the semiconductor device.

FIGS.2A to2Dare schematic cross-sectional views illustrating operations of a semiconductor device according to an embodiment of the present disclosure.FIG.3is a schematic graph illustrating hysteresis behavior of a ferroelectric layer during operations of a semiconductor device according to an embodiment of the present disclosure. The operations of a semiconductor device in connection withFIGS.2A to2D, and3may be described using a semiconductor device1described above with reference toFIG.1.

Referring toFIG.2A, a first write operation may be performed with respect to a semiconductor device1. The first write operation may be performed by applying a first write voltage V1 between the substrate101of the semiconductor device1and the gate electrode layer140using a power supply10. The substrate101may include a doped semiconductor material to have conductivity.

The method of applying the first write voltage V1 may be performed by applying a bias having a negative polarity to the gate electrode layer140while grounding the substrate101. Accordingly, polarization P in the ferroelectric layer110may be aligned in a direction and may have a polarization orientation toward the gate electrode layer140from the substrate101. In addition, when the first write operation is in progress, electrons e injected from the gate electrode layer140and moving to the ferroelectric layer110may be trapped by the metal particles130. Subsequently, after the first write operation is completed, the applied first write voltage V1 may be removed from the semiconductor device1.

Meanwhile, compared to a semiconductor device without the metal particles in a gate insulation layer, according to an embodiment of the present disclosure including the metal particles130, the first write voltage V1 applied to the semiconductor device1may be relatively greater in magnitude during the first write operation. When the first write operation is performed, the magnitude of the first write voltage V1 may increase to facilitate the trapping the electrons e in the metal particles130. When the magnitude of the first write operation voltage V1 increases, the memory operation window of a semiconductor device1may increase, as will be described later with reference toFIG.3.

Referring toFIG.2B, after the first write voltage V1 is removed, first remanent polarization Pa may be aligned inside the ferroelectric layer110. The first remanent polarization Pa as illustrated inFIG.2Bmay have substantially the same polarization orientation as the polarization P generated by the first write voltage V1 as illustrated inFIG.2A. Due to the first remanent polarization Pa in the ferroelectric layer110, negative charges110nmay be distributed in an inner region of the ferroelectric layer110adjacent to the substrate101, while positive charges110pmay be distributed in an inner region of the ferroelectric layer110adjacent to the gate insulation layer120.

Referring toFIG.2C, a second write operation may be performed to the semiconductor device1in which the first remanent polarization Pa is stored. The second write operation may be performed by applying a second write voltage V2 between the substrate101and the gate electrode layer140of the semiconductor device1using the power supply10. The method of applying the second write voltage V2 may be performed by applying a bias having a positive polarity to the gate electrode layer140while grounding the substrate101. Accordingly, a polarization P in the ferroelectric layer110may be aligned in a direction along an electric field formed by the second write voltage V2. Under the second write voltage V2, the polarization P may have a polarization orientation toward the substrate101from the gate electrode layer140, which is the opposite of polarization P under the first write voltage V1 with an opposite polarity. In addition, during the second write operation, the electrons e trapped in the metal particles130may detach from the metal particles130and move towards the gate electrode layer140. Subsequently, after the second write operation is completed, the applied second write voltage V2 may be removed from the semiconductor device1.

Referring toFIG.2C, when forming a polarization P inside the ferroelectric layer110by applying a second write voltage V2, the applied second write voltage V2 needs to overcome any potential formed by the electrons e trapped in the metal particles130before a second write operation can be accomplished. Accordingly, compared to a case in which metal particles are not present inside the gate insulation layer, according to the present embodiment in which metal particles130are present inside the gate insulation layer120, the second write voltage V2 applied to the semiconductor device1may have an increased magnitude in order to perform the second write operation. When the magnitude of the second write operation V2 increases, the memory operation window of the semiconductor device1may also increase, as will be described later with reference toFIG.3.

Referring toFIG.2D, after the second write voltage V2 is removed, second remanent polarization Pb may be aligned inside the ferroelectric layer110. The second remanent polarization Pb may have a polarization orientation substantially the same as that of the polarization P that resulted from application of the second write voltage V2. Under the second remanent polarization Pb, positive charges110pin the ferroelectric layer110may be distributed in an inner region adjacent to the substrate101, and negative charges110nmay be distributed in an inner region adjacent to the gate insulation layer120.

FIG.3illustrates a first hysteresis graph301and a second hysteresis graph302of different semiconductor devices, respectively. The first hysteresis graph301may be a graph obtained from a semiconductor device1ofFIG.1according to an embodiment of the present disclosure, in which a gate insulation layer120includes the metal particles130. The second hysteresis graph302may be a graph obtained from a semiconductor device in a comparative example that does not include metal particles inside an analogous gate insulation layer.

The first hysteresis graph301may include first and second remanent polarization Pr1 and Pr2 and first and second coercive fields Ec1 and Ec2. The second hysteresis graph302may include the first and second remanent polarization Pr1 and Pr2 and third and fourth coercive fields EcA and EcB. Here, the first and second remanent polarization Pr1 and Pr2 of the first hysteresis graph301and the first and second remanent polarization Pr1 and Pr2 of the second hysteresis graph302may be the same. The first remanent polarization Pr1 may correspond to the first remanent polarization Pa ofFIG.2B, and the second remanent polarization Pr2 may correspond to the second remanent polarization Pb ofFIG.2D.

The first hysteresis graph301may have a greater memory operation window. A memory operation window corresponds to a width between a pair of coercive fields. That is, the first memory operation window MWp of the first hysteresis graph301between first and second coercive fields Ec1 and Ec2 may be greater than the second memory operation window MWc of the second hysteresis graph302between third and fourth coercive fields EcA and EcB. The difference in the sizes of the first and second memory operation windows may be due to the greater magnitude of the first write voltage V1, which increases in order to additionally perform an operation of trapping electrons e in the metal particles130of the gate insulation layer120when the first write operation is in progress (seeFIG.2A). In addition, the difference in the sizes of the first and second memory operation windows may also result from the greater magnitude of the second write voltage V2, which increases in order to overcome the potential formed by the electrons e trapped in the metal particles130of the gate insulation layer120during the second write operation (seeFIG.2C). As a result, compared to the second hysteresis graph302, the first hysteresis graph301reflects a greater the operation voltage range of the semiconductor device because the memory operation window may be increased from the comparative example. As the memory operation window increases, in a semiconductor device that stores multi-level remanent polarization as signal information, a voltage interval between a plurality of write voltages may be increased. As a result, signal errors between the multi-level remanent polarization written by the plurality of write voltages may be reduced. Accordingly, the memory operation reliability of the semiconductor device may be improved.

FIG.4is a schematic cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure. Referring toFIG.4, a semiconductor device2may further include a channel layer202disposed between a substrate201and a ferroelectric layer210, compared to a semiconductor device1ofFIG.1. In addition, in the semiconductor device2, a source electrode layer203and a drain electrode layer205corresponding to the source region103and the drain region105of the semiconductor device1may be disposed on a substrate201.

The semiconductor device2may include the substrate201, the channel layer202disposed on the substrate201, the ferroelectric layer210disposed on the channel layer202, a gate insulation layer220disposed on the ferroelectric layer210, metal particles230disposed in an inner region of the gate insulation layer220, and a gate electrode layer240disposed on the gate insulation layer220. In addition, the semiconductor device2may include the source electrode layer203and the drain electrode layer205that are disposed to contact opposite ends of the channel layer202, for example in the ex-direction.

The structures, materials, and arrangements of the substrate201, the ferroelectric layer210, the gate insulation layer220, the metal particles230, and the gate electrode layer240may be substantially the same as those of the substrate101, the ferroelectric layer110, the gate insulation layer120, the metal particles130, and the gate electrode layer140ofFIG.1. In some embodiments, the metal particles230do not contact an interface between the gate insulation layer220and either the ferroelectric layer210or the gate electrode layer240. The metal particles230may be entirely embedded within the gate insulation layer.

Referring toFIG.4, the channel layer202may include a semiconductor material. The semiconductor material may include, for example, silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. As another example, the semiconductor material may include a two-dimensional semiconductor material. The two-dimensional semiconductor material may include transition metal dichalcogenide (TMDC), black phosphorus, or the like. The transition metal dichalcogenide (TMDC) may include, for example, molybdenum selenide (MoSe2), hafnium selenide (HfSe2), indium selenide (InSe), gallium selenide (GaSe), or the like. The semiconductor material may include, for example, metal oxide such as indium-gallium-zinc oxide (IGZO). The channel layer202may have conductivity. As an example, the channel layer202may be doped with an n-type or p-type dopant.

InFIG.4, the channel layer202is illustrated as in contact with the substrate201, but the present disclosure might not necessarily be limited thereto. In some embodiments, various functional layers may be disposed between the substrate201and the channel layer202. As an example, at least one conductive pattern and at least one insulation pattern may be disposed between the substrate201and the channel layer202.

InFIG.4, the channel layer202is disposed on an upper side of surface201S or a surface parallel to surface201S of the substrate201, but the present disclosure is not necessarily limited thereto. In some embodiments, the channel layer202may be disposed on a surface that is not parallel to the surface201S of the substrate201. A non-parallel surface may be, for example, an intersecting planar surface having a certain inclination angle with the surface201S of the substrate201. As an example, as described below with reference toFIGS.15and16, a channel layer350may be disposed on a surface (i.e., y-z plane) substantially perpendicular to a surface301S of a substrate301. That is, the channel layer350may extend in a direction (i.e., z-direction) perpendicular to the surface301S of the substrate301.

The source electrode layer203and the drain electrode layer205may be disposed at opposite ends of the channel layer202. Each of the source electrode layer203and the drain electrode layer205may include a conductive material. The conductive material may include, for example, doped semiconductor, metal, conductive metal nitride, conductive metal carbide, conductive metal silicide, or conductive metal oxide. The conductive material may include, for example, silicon (Si) doped with an n-type or p-type dopant, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof.

FIGS.5to10are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Referring toFIG.5, a substrate101may be provided. The substrate101may include a semiconductor material. As an example, the semiconductor material may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. The substrate101may be doped with an N-type dopant or a P-type dopant to have electrical conductivity.

Next, a ferroelectric layer110may be formed on the substrate101. The ferroelectric layer110may include a ferroelectric material. In an embodiment, the ferroelectric layer110may include metal oxide having a crystal structure of an orthorhombic system as the ferroelectric material. The metal oxide may include, for example, hafnium oxide, zirconium oxide, hafnium zirconium oxide, or a combination of two or more thereof. In an embodiment, the ferroelectric layer110may include a dopant that is doped in the ferroelectric material. The dopant may include, for example, carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), Calcium (Ca), barium (Ba), titanium (Ti), gadolinium (Gd), lanthanum (La), or a combination thereof.

In another embodiment, the ferroelectric layer110may include metal oxide having a perovskite structure as the ferroelectric material. The metal oxide may include, for example, barium titanium oxide (BaTiO3), lead titanium oxide (PbTiO3), barium strontium titanium oxide ((Ba,Sr)TiO3, BST), lithium niobium oxide (LiNbO3), or the like.

The ferroelectric layer110may be formed by, for example, applying a deposition method such as a chemical vapor deposition method or an atomic layer deposition method. The dopant may be implanted into the ferroelectric layer110using a deposition method while forming the ferroelectric layer110.

Referring toFIG.6, a first insulation layer122may be formed on the ferroelectric layer110. The first insulation layer122may have a first thickness t1 on the ferroelectric layer110.

The first insulation layer122may include a dielectric material. The first insulation layer122may have a non-ferroelectric property. The first insulation layer122may include, for example, oxide, nitride, oxynitride, or a combination of two or more thereof. Specifically, the first insulation layer122may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, yttrium oxide, or the like. The first insulation layer122may be formed by, for example, using a chemical vapor deposition method, an atomic layer deposition method, or the like.

A metal thin film1300may be formed on the first insulation layer122. The metal thin film1300may include, for example, cobalt (Co), nickel (Ni), copper (Cu), iron (Fe), platinum (Pt), gold (Au), silver (Ag), iridium (Ir), ruthenium (Ru), palladium (Pd), manganese (Mn), or a combination of two or more thereof.

The metal thin film1300may be formed to have a thickness t1300 of, for example, 0.1 nm to 3 nm. The metal thin film1300may be formed by, for example, using a chemical vapor deposition method, an atomic layer deposition method, or the like.

Referring toFIG.7, the metal thin film (1300ofFIG.6) formed on the first insulation layer (122ofFIG.6) may self-aggregate and convert into a plurality of metal particles130. In an embodiment, the self-aggregation of the metal thin film1300may occur simultaneously with the deposition of the metal thin film1300described with reference toFIG.6. Alternatively, the self-aggregation of the metal thin film1300may result from performing a subsequent process such as heat treatment after the deposition of the metal thin film1300described with reference toFIG.6.

The metal particles130may each have a shape in which metal atoms are aggregated. For example, each of the metal particles130may have a spherical or sphere-like shape. However, the present disclosure is not necessarily limited thereto, and other three-dimensional shapes are possible. In an embodiment, the diameter of a metal particle130having a spherical shape may have a size of 0.1 nm to 5 nm, for example. The metal particles130may be uniformly distributed on the first insulation layer122.

Referring toFIG.8, a second insulation layer124may be formed to cover the particles130on the first insulation layer122. The second insulation layer124may include a dielectric material having a non-ferroelectric property. The second insulation layer124may include, for example, oxide, nitride, oxynitride, or a combination of two or more thereof. In an embodiment, the second insulation layer124may be formed of the same material as the first insulation layer122. The second insulation layer124may be formed by, for example, using a chemical vapor deposition method, an atomic layer deposition method, or the like.

In an embodiment, the second insulation layer124may be formed to have a second thickness t2 on the first insulation layer122. The second thickness t2 of the second insulation layer124may be greater than or equal to the first thickness t1 of the first insulation layer122. Meanwhile, the first insulation layer122and the second insulation layer124that are sequentially formed on the ferroelectric layer110may constitute a gate insulation layer120.

Referring toFIG.9, a gate electrode layer140may be formed on the second insulation layer124. The gate electrode layer140may include a conductive material. The conductive material may include, for example, doped semiconductor, metal, conductive metal nitride, conductive metal carbide, conductive metal silicide, or conductive metal oxide. The conductive material may include, for example, silicon (Si) doped with an n-type or p-type dopant, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof. The gate electrode layer140may be formed by, for example, using a chemical vapor deposition method, an atomic layer deposition method, or the like.

Referring toFIG.10, the ferroelectric layer110, the gate insulation120, the metal particles130, and the gate insulation layer140may be patterned over the substrate101to selectively expose the substrate101. A photolithography process and an etching process may be used in a patterning method.

Next, a dopant I may be implanted into the exposed substrate101to form a source region102and a drain region103. The doping type of each of the source region102and the drain region103may be different from the doping type of the substrate101. As an example, when the substrate101is doped with a P-type dopant, the source region102and the drain region103may be doped with an N-type dopant. As a method of implanting the dopant I, an ion implantation method may be applied.

Although not illustrated, in some embodiments, an interfacial insulation layer may be additionally formed between the substrate101and the ferroelectric layer110inFIG.5. The interfacial insulation layer may function as a buffer layer for alleviating a lattice constant difference between the substrate101and the ferroelectric layer110. The interfacial insulation layer may include, for example, oxide, nitride, oxynitride, or the like. The interfacial insulation layer may be formed by, for example, using a chemical vapor deposition method, an atomic layer deposition method, or the like.

Through the above-described processes, semiconductor devices according to embodiments of the present disclosure may be manufactured. The above-described method of manufacturing a semiconductor device may be used in manufacturing a semiconductor device1ofFIG.1.

FIGS.11to13are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to another embodiment of the present disclosure. The methods illustrated inFIGS.11to13may be applied to a method of manufacturing a semiconductor device2ofFIG.4.

Referring toFIG.11, a substrate201may be provided. The substrate201may be substantially the same as the substrate101ofFIG.5. Alternatively, the substrate201may be an insulating substrate or a conductive substrate.

Next, a channel layer202may be formed on the substrate201. The channel layer202may include a semiconductor material. The semiconductor material may include, for example, silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. As another example, the semiconductor material may include a two-dimensional semiconductor material. The two-dimensional semiconductor material may include transition metal dichalcogenide (TMDC), black phosphorus, or the like. The transition metal chalcogenide may include, for example, molybdenum selenide (MoSe2), hafnium selenide (HfSe2), indium selenide (InSe), gallium selenide (GaSe), or the like. The semiconductor material may include, for example, metal oxide such as indium-gallium-zinc oxide (IGZO). The channel layer202may have conductivity. As an example, the channel layer202may be doped with an N-type dopant or a P-type dopant. The channel layer202may be formed by, for example, applying a chemical vapor deposition method, an atomic layer deposition method, or the like.

Subsequently, a ferroelectric layer210may be formed on the channel layer202. The ferroelectric layer210may be substantially the same as a ferroelectric layer110ofFIG.5. A method of forming the ferroelectric layer210may be substantially the same as the method of forming the ferroelectric layer110ofFIG.5.

Referring toFIG.12, a first insulation layer222, metal particles230, a second insulation layer224, and a gate electrode layer240may be sequentially formed over the ferroelectric layer210. Methods of forming the first insulation layer222, the metal particles230, the second insulation layer224, and the gate electrode layer240may be substantially the same as the methods of forming the first insulation layer122, the metal particles130, the second insulation layer124, and the gate electrode layer140described above with reference toFIGS.6to9. In this device, the first insulation layer222and the second insulation layer224may constitute a gate insulation layer220.

Referring toFIG.13, the channel layer202, the ferroelectric layer210, the first insulation layer222, the metal particles230, the second insulation layer224, and the gate electrode layer240may be patterned over the substrate201to selectively expose the substrate201. A patterning process may be, for example, a photolithography process and an etching process.

Then, a source electrode layer203and a drain electrode layer205may be formed on the exposed portions of the substrate201. The source electrode layer203and the drain electrode layer205may be formed to contact opposite ends of the channel layer202for example in the x-direction. The source electrode layer203and the drain electrode layer205may be formed by, for example, applying a chemical vapor deposition method, an atomic layer deposition method, or the like.

Each of the source electrode layer203and the drain electrode layer205may include a conductive material. The conductive material may include, for example, doped semiconductor, metal, conductive metal nitride, conductive metal carbide, conductive metal silicide, or conductive metal oxide. The conductive material may include, for example, silicon (Si) doped with an n-type or p-type dopant, tungsten (W), titanium (Ti), copper (Cu), aluminum (Al), ruthenium (Ru), platinum (Pt), iridium (Ir), iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or a combination of two or more thereof. Through the above-described methods, a semiconductor device according to another embodiment of the present disclosure may be manufactured.

In some embodiments, before forming the channel layer202illustrated inFIG.11, at least one conductive layer and at least one insulation layer (not illustrated) may be formed. The conductive layer and the insulation layer may form various functional layers in a semiconductor device. For example, the functional layer may include an interconnection layer.

FIG.14is a circuit diagram of a semiconductor device according to yet another embodiment of the present disclosure.FIG.15is a schematic perspective view of a semiconductor device corresponding to the circuit diagram ofFIG.14.FIG.15may be a structural view of a semiconductor device ofFIG.14.FIG.16is a schematic cross-sectional view of a semiconductor device ofFIG.15taken along the line I-I′.

Referring toFIG.14, a semiconductor device may include a memory element unit U. The memory element unit U may include transistor-type first to fourth memory cells MC1, MC2, MC3, and MC4. The first to fourth memory cells MC1, MC2, MC3, and MC4 may be connected in series to each other in the form of a string between a source line SL and a bit electrode BL. The memory element unit U may be a NAND type memory device in which the first to fourth memory cells MC1, MC2, MC3, and MC4 are electrically connected in series to each other.

The first to fourth memory cells MC1, MC2, MC3, and MC4 may be nonvolatile memory elements and may include first to fourth ferroelectric elements FL1, FL2, FL3, and FL4, respectively, corresponding to gate dielectric layers of the transistors. The first to fourth memory cells MC1, MC2, MC3, and MC4 may include first to fourth gate electrodes GL1, GL2, GL3, and GL4, respectively, connected to different word lines connected to the memory cells.

Referring toFIGS.15and16, the semiconductor device3may include the first to fourth memory cells MC1, MC2, MC3, and MC4, in which each memory cell has a shape of a three-dimensional transistor. The semiconductor device3may have a circuit configuration of the memory element unit U ofFIG.14.

The semiconductor device3may include a substrate301and a gate structure320disposed over the substrate301. The gate structure320may include a hole pattern31. The hole pattern31may expose a sidewall surface of the gate structure320. In addition, the semiconductor device3may include a gate insulation layer330disposed on the sidewall surface of the gate structure320, metal particles332disposed in an inner region of the gate insulation layer330, a ferroelectric layer340disposed on a sidewall surface of the gate insulation layer330, and a channel layer350disposed on a sidewall surface of the ferroelectric layer340. In addition, the semiconductor device3may include an insulator360disposed to contact the channel layer350and a channel lower contact layer310inside the hole pattern31.

The semiconductor device3may include a base insulation layer302. The base insulation layer302and the channel lower contact layer310may be disposed between the substrate301and the gate structure320. The channel lower contact layer310, which may be disposed on the base insulation layer, may contact an end of the channel layer350. In addition, the semiconductor device3may include a channel upper contact layer370disposed on the insulator360to be in contact with the other end of the channel layer350.

Referring toFIGS.15and16, the substrate301may include a semiconductor material. The base insulation layer302may be disposed on the substrate301. The base insulation layer302may electrically insulate the channel lower contact layer310from the substrate301. The base insulation layer302may include an insulating material. Although not illustrated, integrated circuits may be disposed between the substrate301and the base insulation layer302. The integrated circuits may include circuits for driving and controlling the plurality of memory cells of the semiconductor device3.

The channel lower contact layer310may be disposed on the base insulation layer302. The channel lower contact layer310may be electrically connected to the channel layer350. Although not illustrated, the channel lower contact layer310may be electrically connected to a source line. The channel lower contact layer310may include a conductive material.

The gate structure320may be disposed on the channel lower contact layer310. The gate structure320may include first to fourth gate electrode layers322a,322b,322c, and322dand first to fifth interlayer insulation layers323a,323b,323c,323d, and323e, which are alternately stacked along a first direction (i.e., z-direction) perpendicular to a surface301S of the substrate301. The first interlayer insulation layer323amay be disposed to contact the channel lower contact layer310. The fifth interlayer insulation layer323emay be disposed as an uppermost layer of the gate structure320. Each of the first to fourth gate electrode layers322a,322b,322c, and322dmay include a conductive material. Each of the first to fifth interlayer insulation layers323a,323b,323c,323d, and323emay include an insulating material.

The number of gate electrode layers of the gate structure320might not necessarily be limited to four as illustrated inFIG.16. The gate electrode layers may be disposed in various numbers, and the interlayer insulation layer may insulate the various numbers of gate electrode layers from each other in the first direction (i.e., z-direction or vertical direction).

Referring toFIGS.15and16, the hole pattern31may be formed to penetrate the gate structure320and to expose the channel lower contact layer310. The hole pattern31may be formed, for example, by a photolithography and etching process.

The gate insulation layer330may be disposed to cover the sidewall surface of the gate structure320inside the hole pattern31. The gate insulation layer330may include an insulating material. The material composition of the gate insulation layer330may be substantially the same as the material composition of the gate insulation layer120of a semiconductor device1described above with reference toFIG.1.

The metal particles332may be disposed in an inner region of the gate insulation layer330. The metal particles332may be configured to trap or de-trap electric charges (e.g., electrons) depending on a polarity of the voltage applied between the gate electrode layers322a,322b,322c, and322dand the channel layer350.

The ferroelectric layer340may be disposed on the sidewall surface of the gate insulation layer330. The material composition of the ferroelectric layer340may be substantially the same as that of the ferroelectric layer110of a semiconductor device1described above with reference toFIG.1.

The channel layer350may be disposed to contact the ferroelectric layer340. The channel layer350may extend in a direction substantially perpendicular to the surface301S of the substrate301inside the hole pattern31, for example, in the z-direction. The channel layer350may include a semiconductor material. The channel layer350may have electrical conductivity by being doped with a dopant. The material composition of the channel layer350may be substantially the same as the material composition of a channel layer202of a semiconductor device2described with reference toFIG.4.

Referring toFIGS.15and16, the channel upper contact layer370may be disposed on the insulator360. The channel upper contact layer370may be electrically connected to a bit line (not shown). The channel upper contact layer370may include a conductive material. The channel upper contact layer370may be made of the same material as the channel lower contact layer310.

As described above, the semiconductor device3may have a device structure corresponding to the circuit configuration of the memory element unit U ofFIG.14. As an example, the first memory cell MC1 may include a first gate electrode layer322a, a portion of the gate insulation layer330electrically controlled by the first gate electrode layer322a, a portion of the ferroelectric layer340electrically controlled by the first gate electrode layer322a, and a portion of the channel layer350electrically controlled by the first gate electrode layer322a. As another example, the second memory cell MC2 may include a second gate electrode layer322b, a portion of the gate insulation layer330electrically controlled by the second electrode layer322b, a portion of the ferroelectric layer340electrically controlled by the second electrode layer322b, and a portion of the channel layer350electrically controlled by the second gate electrode layer322b. As another example, the third memory cell MC3 may include a third gate electrode layer322c, a portion of the gate insulation layer330electrically controlled by the third gate electrode layer322c, a portion of the ferroelectric layer340electrically controlled by the third electrode layer322c, and a portion of the channel layer350electrically controlled by the third gate electrode layer322c. As further example, the fourth memory cell MC4 may include a fourth gate electrode layer322d, a portion of the gate insulation layer330electrically controlled by the fourth gate electrode layer322d, a portion of the ferroelectric layer340electrically controlled by the fourth electrode layer322d, and a portion of the channel layer350electrically controlled by the fourth gate electrode layer322d.

As described above, according to embodiments of the present disclosure, a semiconductor device including a ferroelectric layer and a gate insulation layer that are disposed between the gate electrode layer and channel layer may be provided. The semiconductor device may include metal particles disposed in an inner region of the gate insulation layer.

The metal particles may increase the operation voltage range of the semiconductor device, that is, the memory operation window, which results from trapping and de-trapping charges in the gate insulation layer during operations of the semiconductor device. In addition, as described above, the metal particles may induce strains in the gate insulation layer, and the strains may increase the permittivity and capacitance of the gate insulation layer. As a result, the operational performance of semiconductor devices according to embodiments may be improved, and the reliability of remanent polarization written into the ferroelectric layer may be improved. The durability of the ferroelectric layer may also be improved.

Embodiments of the present disclosure have been disclosed for illustrative purposes. Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the present disclosure and the accompanying claims.