Patent ID: 12191347

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

The following disclosure describes various exemplary embodiments for implementing different features of the subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Terms such as “attached,” “affixed,” “connected” and “interconnected,” refer to a relationship wherein structures are secured or attached to one another either directly or indirectly through intervening structures, as well as both movable or rigid attachments or relationships, unless expressly described otherwise.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Reference will now be made in detail to the present embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

The present disclosure provides various embodiments of a novel capacitor structure and methods to form the same. In some embodiments, the disclosed capacitor structure includes a plurality of MIM capacitors formed on an insulation layer. Each of the MIM capacitors includes two finger type metal contacts vertically extending on the insulation layer. The two finger type metal contacts serve as two electrodes separated by a dielectric insulator to form the MIM capacitor. The insulation layer is formed on a substrate and serves as a stop layer for the metal contacts to electrically isolate the two metal contacts. With this novel structure, the disclosed MIM capacitors can achieve a high area density. In addition, a method to form the disclosed MIM capacitors does not need an extra mask or etching process to form a capacitor top metal (CTM) electrode. The present disclosure is applicable to any semiconductor device including a capacitor.

FIG.1illustrates an exemplary layout of a semiconductor device100having vertical capacitor structures, in accordance with some embodiments of the present disclosure. As shown inFIG.1, there are multiple electrodes130arranged in parallel over an active region110. In one embodiment, the active region110serves as a substrate for the multiple electrodes130. Each of the multiple electrodes130may comprise a conductive material, e.g. a metal like tungsten, aluminum, copper, etc. In one embodiment, the multiple electrodes130are formed in a contact layer of the semiconductor device100, such that each of the multiple electrodes130is a contact (CT) comprising tungsten. Every two adjacent electrodes130are separated by an insulator (not shown inFIG.1) comprising a dielectric material to form a capacitor.

The active region110may comprise a semiconductor material, e.g. silicon. To electrically isolate the multiple electrodes130from each other, the multiple electrodes130are not formed directly onto the active region110comprising silicon. The semiconductor device100comprises an insulation layer120formed on the active region110and below the multiple electrodes130. The insulation layer120comprises a dielectric material, e.g. silicon oxide, silicon nitride, etc. In one embodiment, the insulation layer120comprises a resist protective oxide (RPO). In one embodiment, the insulation layer120comprises a plurality of sub-layers. For example, the insulation layer120comprises at least one nitride layer and at least one oxide layer. The insulation layer120serves as a stop layer for the multiple electrodes130to stop onto.

As shown inFIG.1, the multiple electrodes130are divided into two groups of electrodes: a group of first electrodes131and a group of second electrodes132. The group of first electrodes131and the group of second electrodes132are interlaced with each other. There are not two adjacent electrodes belonging to a same group. As shown inFIG.1, the group of first electrodes131are electrically connected to a logic high voltage; and the group of second electrodes132are electrically connected to a logic low voltage. There are not two adjacent electrodes electrically connected to a same voltage. As such, the group of first electrodes131and the group of second electrodes132form a plurality of capacitors connected in series. In one embodiment, each of the plurality of capacitors is a metal insulator metal (MIM) capacitor, since each capacitor is formed by: two adjacent electrodes made of a metal, and an insulator between the adjacent two electrodes.

As shown inFIG.1, the first and second electrodes131,132form an electrode array extending along the X direction, while each of the first and second electrodes131,132extends along the Y direction perpendicular to the X direction. As shown inFIG.1, each of the group of first electrodes131and the group of second electrodes132has a top surface with a rectangular shape. The rectangular shape has a first dimension A and a second dimension B. In one embodiment, the first dimension A is at least 0.22 micrometer. In one embodiment, the second dimension B is at least 0.19 micrometer. In one embodiment, the first dimension A is greater than the second dimension B, where the first dimension A extends along the Y direction and the second dimension B extends along the X direction perpendicular to the Y direction. In one embodiment, the first dimension A is longer than the second dimension B by more than 50%. In one embodiment, the first dimension A is longer than the second dimension B by more than 100%. In one embodiment, the first dimension A is longer than the second dimension B by more than 200%. According to various embodiments, the rectangular shape has an area that is between 0.04 and 25 square micrometers.

Every two adjacent electrodes130, i.e. a pair of first electrode131and second electrode132, have a distance C from each other. The distance C may be determined based on a design requirement related to a capacitance value of each of the capacitors. In one embodiment, the distance C is at least 0.19 micrometer. According to various embodiments, the plurality of capacitors following a layout shown inFIG.1can have a high area density, e.g. 5 to 225 capacitors per 100 square micrometers.

FIG.2Aillustrates a cross-sectional view of a semiconductor device200having vertical capacitor structures, in accordance with some embodiments of the present disclosure. As shown inFIG.2A, the semiconductor device200in this example includes: an active region or a substrate210; an insulation layer220on the substrate210; and a dielectric layer230on the insulation layer220.

The semiconductor device200in this example further includes a plurality of contacts240formed within the dielectric layer230. Accordingly, the dielectric layer230may also be called a contact layer. Each of the plurality of contacts240is made of a metal material, e.g. tungsten, aluminum, copper, etc., and stops onto the insulation layer220. In one embodiment, while the substrate210comprises a semiconductor material like silicon, the insulation layer220comprises a dielectric material like resist protective oxide. As such, the plurality of contacts240can stop onto the insulation layer220and be electrically isolated from each other. Other than the plurality of contacts240, the remaining portion of the dielectric layer230forms an insulating structure between every two adjacent contacts240.

As shown inFIG.2A, each of the plurality of contacts240has a left sidewall241, a right sidewall242, a bottom surface243, and a top surface244. The bottom surface243is in contact with the insulation layer220. An insulator, which is part of the insulating structure of the dielectric layer230, is coupled to opposite sidewalls of a pair of two contacts adjacent to each other, i.e. is coupled to a left sidewall241of a right contact in the pair and a right sidewall242of a left contact in the pair. As such, each pair of two adjacent contacts and the insulator there between form a capacitor. Accordingly, each contact240can be called an electrode of the capacitor. As shown inFIG.2A, each contact240is a finger type electrode extending vertically, i.e. along a vertical direction perpendicular to the substrate210.

FIG.2Billustrates a perspective view of vertical capacitor structures of the semiconductor device200, in accordance with some embodiments of the present disclosure. As shown inFIG.2B, each contact240stops on the insulation layer220which comprises oxide and/or nitride material that electrically isolates the contacts240from each other. In addition, each contact240is electrically connected to a logic high voltage or a logic low voltage, e.g. via at least one metal layer over the dielectric layer230. Every two adjacent contacts240are connected to two different voltages, i.e. a logic high voltage and a logic low voltage, respectively. That is, contacts connected to a logic high voltage and contacts connected to a logic low voltage are interlaced with each other. The contacts240separated by the insulating structure of the dielectric layer230form a plurality of capacitors connected in series. Each of the plurality of capacitors stores electrical energy in an electric field having a horizontal direction, i.e. a direction parallel to the substrate210. As shown inFIG.2B, each contact240is a finger type electrode of a capacitor and extends vertically, i.e. along a direction perpendicular to the substrate210. Accordingly, each of the plurality of capacitors is called a vertical capacitor herein.

Each contact240has sidewalls241,242and a bottom surface243in contact with the insulation layer220. As shown inFIG.2B, each sidewall241,242of each contact240has a rectangular shape with same dimensions. To be specific, each sidewall241,242has a first dimension A and a second dimension D, where the second dimension D is equal to a height of the dielectric layer230. In addition, every two adjacent contacts240have a distance C from each other. As such, a capacitance of the capacitor formed by two adjacent contacts240is proportional to A*D/C. By adjusting the area A*D of the sidewalls241,242and/or the distance C between two adjacent contacts240, a desirable capacitance can be achieved based on a design requirement. In addition, the plurality of capacitors can achieve a high area density based on the vertical capacitor structure and the adjusted dimensions. As shown inFIG.2B, the top surface244and the bottom surface243of each contact240also have a rectangular shape.

FIGS.3A,3B,3C,3D,3E,3F,3G,3H,3I, and3Jillustrate cross-sectional views of an exemplary semiconductor device during various fabrication stages, in accordance with some embodiments of the present disclosure. In some embodiments, the semiconductor device may be a device comprising MIM capacitors. The semiconductor device may be included in a microprocessor, memory cell, and/or other integrated circuit (IC). In addition,FIGS.3A through3Jare simplified for a better understanding of the concepts of the present disclosure. For example, although the figures illustrate the MIM capacitors, it is understood the IC, in which the MIM capacitors is formed, may include a number of other layers comprising metal layers, a polymer layer, a passivation layer, etc., and may include a number of other devices comprising resistors, capacitors, inductors, fuses, etc., which are not shown inFIGS.3A through3J, for purposes of clarity of illustration.

FIG.3Ais a cross-sectional view of the semiconductor device including an active region310, which is provided, at one of the various stages of fabrication, according to some embodiments of the present disclosure. The active region310inFIG.3Amay comprise a semiconductor material, e.g. silicon, and serve as a substrate for upper layers to be formed on.

FIG.3Bis a cross-sectional view of the semiconductor device including a first oxide layer322, which is formed on the substrate310at one of the various stages of fabrication, according to some embodiments of the present disclosure. According to some embodiments, the first oxide layer322may be formed by depositing an oxide material, e.g. silicon oxide, on the substrate310.

FIG.3Cis a cross-sectional view of the semiconductor device including a nitride layer324, which is formed on the first oxide layer322at one of the various stages of fabrication, according to some embodiments of the present disclosure. According to some embodiments, the nitride layer324may be formed by depositing a nitride material, e.g. silicon nitride, on the first oxide layer322.

FIG.3Dis a cross-sectional view of the semiconductor device including a second oxide layer326, which is formed on the nitride layer324at one of the various stages of fabrication, according to some embodiments of the present disclosure. According to some embodiments, the second oxide layer326may be formed by depositing an oxide material, e.g. silicon oxide, on the nitride layer324. The layers322,324,326all include dielectric materials and together form an insulation layer320to serve as a stop layer for contacts to be formed on. While the insulation layer320has three sub-layers as shown inFIG.3D, it may have more or less than three sub-layers in other embodiments. In some embodiments, each sub-layer of the insulation layer320may include at least one of: silicon oxide, silicon nitride, resist protective oxide (RPO), or other suitable dielectric material that can stop a contact to be formed on.

FIG.3Eis a cross-sectional view of the semiconductor device including a dielectric layer330, which is formed on the second oxide layer326at one of the various stages of fabrication, according to some embodiments of the present disclosure. According to some embodiments, the dielectric layer330may be formed by depositing a dielectric material on the second oxide layer326. In some embodiments, the dielectric material of the dielectric layer330may include a high-k dielectric material comprising: SiOx, SiNx, SiOxNy, ZrO2, Al2O3, HfOx, HfSiOx, ZrTiOx, TiO2, TaOx, etc., or any combinations thereof.

FIG.3Fis a cross-sectional view of the semiconductor device including a patterned mask340, which is formed on the dielectric layer330at one of the various stages of fabrication, according to some embodiments of the present disclosure. According to some embodiments, the patterned mask340may be formed by depositing a photoresist material on the dielectric layer330, and a patterning process to form a pattern or profile on the patterned mask340.

FIG.3Gis a cross-sectional view of the semiconductor device including a plurality of trenches350, which is formed in the dielectric layer330at one of the various stages of fabrication, according to some embodiments of the present disclosure. According to some embodiments, the plurality of trenches350may be formed based on a dry/wet etching process and a pattern of the mask340. For example, portions of the dielectric layer330that are not covered by the pre-defined pattern of the patterned mask340may be etched based on the pattern to form the plurality of trenches350.

As shown inFIG.3G, each of the plurality of trenches350stops within the insulation layer320. In this example, at a bottom of each of the plurality of trenches350, the second oxide layer326is completely removed; the nitride layer324is also completely removed; but the first oxide layer322is not removed. In another embodiment, at a bottom of each of the plurality of trenches350, the second oxide layer326is completely removed; the nitride layer324is partially removed; and the first oxide layer322is not removed. In yet another embodiment, at a bottom of each of the plurality of trenches350, the second oxide layer326is completely removed; the nitride layer324is also completely removed; and the first oxide layer322is partially removed. In any case, each of the plurality of trenches350stops within the insulation layer320, i.e. stopping at the second oxide layer326, the nitride layer324, or the first oxide layer322, without exposing the substrate310. In some embodiments, a cleaning process and a soft/hard baking process are also performed to form the plurality of trenches350.

FIG.3His a cross-sectional view of the semiconductor device, where the mask340is removed at one of the various stages of fabrication, according to some embodiments of the present disclosure. According to some embodiments, the mask340is removed by a cleaning process. As shown inFIG.3H, the plurality of trenches350divides the dielectric layer330into a plurality of stacks355. Each of the plurality of stacks355comprises a dielectric material, e.g. a high-k dielectric material comprising: SiOx, SiNx, SiOxNy, ZrO2, Al2O3, HfOx, HfSiOx, ZrTiOx, TiO2, TaOx, etc., or any combinations thereof.

FIG.3Iis a cross-sectional view of the semiconductor device including a plurality of contacts360, which is formed in the plurality of trenches350at one of the various stages of fabrication, according to some embodiments of the present disclosure. According to some embodiments, each of the plurality of contacts360is formed by depositing a conductive material to fill up the plurality of trenches350. In some embodiments, the conductive material may be formed of a metal material, e.g., copper (Cu), aluminum (Al), tungsten (W), etc. As such, every two adjacent contacts360are separated by an insulator355comprising a dielectric material, to form an MIM capacitor. Each of the plurality of contacts360is an electrode for the MIM capacitor. In one embodiment, the plurality of stacks or insulators355are coupled to each other to form an insulating structure in the dielectric layer330.

FIG.3Jis a cross-sectional view of the semiconductor device300including a metal layer370, which is formed on the plurality of contacts360at one of the various stages of fabrication, according to some embodiments of the present disclosure. As shown inFIG.3J, the plurality of contacts or electrodes360are divided into a group of first electrodes362and a group of second electrodes364that are interlaced with each other. According to some embodiments, the metal layer370is formed by depositing a metal material, e.g. aluminum, copper, etc., onto the first electrodes362and the second electrodes364. In one embodiment, as shown inFIG.3J, the first electrodes362are connected to a logic high voltage via the metal layer370; and the second electrodes364are connected to a logic low voltage via the metal layer370. In another embodiment, the first electrodes362are connected to a logic low voltage via the metal layer370; and the second electrodes364are connected to a logic high voltage via the metal layer370.

FIG.4is a flow chart illustrating an exemplary method400for forming a semiconductor device having vertical capacitor structures, in accordance with some embodiments of the present disclosure. At operation402, a first oxide layer is deposited on a substrate. A nitride layer is deposited at operation404on the first oxide layer. At operation406, a second oxide layer is deposited on the nitride layer. A dielectric layer is deposited at operation408on the second oxide layer. At operation410, a mask is formed with a pattern on the dielectric layer.

At operation412, the dielectric layer is etched based on the pattern to form a plurality of trenches. As discussed above, each of the plurality of trenches stops within the first oxide layer, the nitride layer, or the second oxide layer. The plurality of trenches are filled up at operation414with a conductive material to form first electrodes and second electrodes interlaced with each other. Every two adjacent electrodes, i.e. a first electrode and a second electrode, are electrically isolated by an insulator between them and by the oxide or nitride layer below them, to form a capacitor. All the electrodes form a plurality of capacitors connected in series.

At operation416, a metal layer is deposited on the first electrodes and the second electrodes. At operation418, the first electrodes are connected to a logic high voltage via the metal layer. At operation420, the second electrodes are connected to a logic low voltage via the metal layer. It can be understood that the order of the operations shown inFIG.4may be changed according to different embodiments of the present disclosure. The capacitors formed according to the disclosed method can achieve a high area density. The disclosed method does not need an extra mask or etching process to form a capacitor top metal (CTM) electrode.

In an embodiment, a semiconductor device is disclosed. The semiconductor device includes: an insulation layer, a first electrode with sidewalls and a bottom surface in contact with the insulation layer; a second electrode with sidewalls and a bottom surface in contact with the insulation layer; and an insulator formed between the first electrode and the second electrode. The insulator is coupled to a sidewall of the first electrode and coupled to a sidewall of the second electrode.

In another embodiment, a semiconductor device is disclosed. The semiconductor device includes: a substrate; an insulation layer on the substrate; a dielectric layer on the insulation layer; a plurality of first electrodes formed within the dielectric layer; and a plurality of second electrodes formed within the dielectric layer. The first electrodes and the second electrodes are interlaced with each other. The dielectric layer comprises an insulating structure formed between the first electrodes and the second electrodes.

In yet another embodiment, a method for forming a semiconductor device is disclosed. The method includes: forming an insulation layer on a substrate; depositing a dielectric layer on the insulation layer; and forming a plurality of electrodes within the dielectric layer. The plurality of electrodes comprises first electrodes and second electrodes that are interlaced with each other. The dielectric layer comprises an insulating structure between the first electrodes and the second electrodes.

The foregoing outlines features of several embodiments so that those ordinary skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.