Patent ID: 12191315

DETAILED DESCRIPTION

Hereinafter, technical solutions of implementations of the disclosure will be depicted clearly and completely with reference to accompanying drawings in the implementations. Apparently, implementations described below are merely some implementations, rather than all implementations of the disclosure. All other implementations obtained by those of ordinary skill in the art based on the implementations without creative efforts shall fall within the protection scope of the disclosure.

The disclosure provides an array substrate, which can solve a technical problem of a small light-transmitting region.

In a first aspect, the disclosure provides an array substrate. The array substrate includes multiple gate lines extending along a first direction, multiple data lines extending along a second direction, and multiple pixel units defined by intersections of the gate lines and the data lines. The multiple pixel units each include a pixel electrode, a drive circuit, and a sharing electrode. The pixel electrode includes a first pixel electrode and a second pixel electrode. The drive circuit is electrically connected to the pixel electrode. The drive circuit includes a first thin-film transistor, a second thin-film transistor, and a third thin-film transistor. The first thin-film transistor has a drain electrically connected to the first pixel electrode. The second thin-film transistor has a drain electrically connected to the second pixel electrode. The third thin-film transistor has a source connected to the drain of the second thin-film transistor and has a drain connected to the sharing electrode. The sharing electrode includes a first sharing electrode and a second sharing electrode electrically connected to the first sharing electrode. The array substrate further includes a base substrate, a first metal layer disposed on one side of the base substrate, and a second metal layer disposed on one side of the first metal layer away from the base substrate. The gate lines and the first sharing electrode are formed in the first metal layer, and the data lines and the second sharing electrode are formed in the second metal layer. The projection of the first sharing electrode on the base substrate at least partially overlaps the projection of the pixel electrode on the base substrate.

In some implementations, the array substrate further includes a first insulating layer. The first insulating layer at least partially covers the first sharing electrode and defines an adapter hole. The second sharing electrode is electrically connected to the first sharing electrode through the adapter hole.

In some implementations, the first pixel electrode is located on one side of the gate line, and the second pixel electrode is located on the other side of the same gate line.

In some implementations, the array substrate further includes a common electrode encircling the pixel electrode and a second insulating layer covering the second sharing electrode. The second insulating layer defines a via hole, and the pixel electrode is electrically connected to the drive circuit through the via hole.

In some implementations, the via hole includes a first via-hole and a second via-hole. The first pixel electrode is electrically connected to the first thin-film transistor through the first via-hole, and the second pixel electrode is electrically connected to the second thin-film transistor through the second via-hole. The first via-hole is close to the data line, the second via-hole is away from the same data line, and the adapter hole is away from the via hole relative to the same data line.

In some implementations, the first sharing electrode includes a first segment of the first sharing electrode disposed between the base substrate and the pixel electrode and a second segment of the first sharing electrode disposed between the pixel electrode and the gate line. The second segment of the first sharing electrode disposed on one side of the first pixel electrode is electrically connected to one end of the second sharing electrode. The second segment of the first sharing electrode disposed on one side of the second pixel electrode is electrically connected to the other end of the second sharing electrode.

In some implementations, the first thin-film transistor, the second thin-film transistor, and the third thin-film transistor are disposed along the first direction.

In some implementations, the second segment of the first sharing electrode is wider than the first segment of the first sharing electrode.

In some implementations, the first sharing electrode comprises a first segment of the first sharing electrode disposed between the base substrate and the pixel electrode and a second segment of the first sharing electrode disposed between the pixel electrode and the gate line; the first segment of the first sharing electrode passes through the pixel electrode along the second direction.

In some implementations, the first thin-film transistor and the second thin-film transistor form a common-gate and common-source structure.

In a second aspect, the disclosure further provides a method for manufacturing an array substrate. The method includes: providing a base substrate; forming a first metal layer on the base substrate, and forming gate lines, a common electrode, and a first sharing electrode by patterning the first metal layer; forming a first insulating layer on the first metal layer; defining an adapter hole in the first insulating layer; forming a second metal layer on the first insulating layer, and forming data lines, a source and a drain of a drive circuit, and a second sharing electrode by patterning the second metal layer, where the second sharing electrode is electrically connected to the first sharing electrode through the adapter hole; forming a second insulating layer on the second metal layer; defining a via hole in the second insulating layer; and manufacturing a transparent electrode layer on the second insulating layer, and forming a pixel electrode by patterning the transparent electrode layer.

In a third aspect, the disclosure further provides a display panel. The display panel includes a color-film substrate, a liquid-crystal layer, and the array substrate described in the first aspect. The array substrate is disposed opposite to and spaced apart from the color-film substrate to define a receiving space. The liquid-crystal layer is disposed in the receiving space.

Technical effects of the disclosure lie in that: an array substrate and a method for manufacturing the same, and a display panel are provided, on the one hand, the first sharing electrode is disposed in the first metal layer, and the projection of the first sharing electrode on the base substrate at least partially overlaps the projection of the pixel electrode on the base substrate, which can simplify a layout structure of the second metal layer; on the other hand, the second sharing electrode is disposed in the second metal layer, and the first sharing electrode is electrically connected to the second sharing electrode, which can prevent the sharing electrode from forming a jagged edge, thereby improving a display effect.

The disclosure provides an array substrate1. Referring toFIG.1andFIG.2,FIG.1is a schematic top view illustrating an array substrate provided in an implementation of the disclosure, andFIG.2is a schematic cross-sectional view along line I-I inFIG.1. An array substrate1includes multiple gate lines1aextending along a first direction D1, multiple data lines1bextending along a second direction D2, and multiple pixel units11. The pixel unit11includes a pixel electrode111, a drive circuit112, and a sharing electrode114. The pixel electrode111includes a first pixel electrode1111and a second pixel electrode1112. The drive circuit112is electrically connected to the pixel electrode111. The drive circuit112includes a first thin-film transistor1121, a second thin-film transistor1122, and a third thin-film transistor113. A drain1121bof the first thin-film transistor is electrically connected to the first pixel electrode1111. A drain1122bof the second thin-film transistor is electrically connected to the second pixel electrode1112. A source113aof the third thin-film transistor is electrically connected to the drain1122bof the second thin-film transistor. The sharing electrode114includes a first sharing electrode1141and a second sharing electrode1142. The first sharing electrode1141is electrically connected to the second sharing electrode1142. The sharing electrode114is connected to a drain113bof the third thin-film transistor.

The array substrate1further includes a base substrate12, a first metal layer13, and a second metal layer16. The gate lines1aand the first sharing electrode1141are formed in the first metal layer13. The first metal layer13is disposed on one side of the base substrate12. The data lines1band the second sharing electrode1142are formed in the second metal layer16. The second metal layer16is disposed on one side of the first metal layer13away from the base substrate12. The projection of the first sharing electrode1141on the base substrate12at least partially overlaps the projection of the pixel electrode111on the base substrate12.

Specifically, the pixel unit11includes the pixel electrode111, the drive circuit112, and the sharing electrode114. Light can pass through the pixel electrode111, but cannot or almost cannot pass through the drive circuit112, the third thin-film transistor113, and the sharing electrode114. It can be understood that, since display brightness is one of specifications for testing a display, in order to realize a better display effect, the proportion of an area of the pixel electrode111should be as large as possible.

Specifically, the source113aof the third thin-film transistor is connected to the drain1122bof the second thin-film transistor, and the drain113bof the third thin-film transistor is connected to the second sharing electrode1142. A sharing-electrode voltage is transmitted to the second sharing electrode1142through the third thin-film transistor113, and the second sharing electrode1142is electrically connected to the first sharing electrode1141, so that the sharing electrode voltage is transmitted to the first sharing electrode1141through the second sharing electrode1142, to realize signal transmission.

Specifically, the projection of the first sharing electrode1141on the base substrate12at least partially overlaps the projection of the pixel electrode111on the base substrate12, that is, a first segment1141aof the first sharing electrode; a first segment1141aof the first sharing electrode passes through the pixel electrode111along the second direction D2.

Specifically, the first sharing electrode1141is located in the first metal layer13, the second sharing electrode1142is located in the second metal layer16, and the second sharing electrode1142is disposed above the first sharing electrode1141.

It is to be noted that, in the related art, the sharing electrode114and the second metal layer16are formed by etching in a same process, which easily leads to uneven etching of the edge of the sharing electrode114. As a result, a jagged edge is formed, which leads to a phenomenon of light dark field at the jagged edge. Therefore, in the related art, a pad layer is generally added on the first metal layer13and a width of the pad layer is larger than that of the sharing electrode114, so as to shield the sharing electrode114, which, however, reduces the proportion of an area of the pixel electrode111of the array substrate1, resulting in a reduction of light passing through the pixel electrode111and a decrease in light transmittance.

It can be understood that, in this implementation, as illustrated inFIG.2, the first sharing electrode1141and the second sharing electrode1142electrically connected to each other are respectively disposed in different metal layers, and the first sharing electrode1141below the pixel electrode111belongs to the first metal layer13, which can avoid the jagged edge caused by etching in the same process as a semiconductor layer, and can further avoid adding of an additional pad-layer structure that is wider than the first sharing electrode1141in the related art, thereby reducing an area of a non-light-transmitting region, increasing an area of a light-transmitting region, increasing light transmittance, and improving a display effect.

It is to be noted that, a same filling pattern inFIG.1represents a same hierarchical structure, and some hierarchical structures are illustrated in perspective inFIG.1. For a specific hierarchical relationship, reference may be made to schematic cross-sectional views of the disclosure provided below. In this implementation, the array substrate1can be applied to a Liquid Crystal Display (LCD), that is, a backlight source is further provided at one side of the array substrate1, light emitted by the backlight source passes through the array substrate1and then is exited from one side of the LCD, and the array substrate1plays a role of adjusting the light emitted by the backlight source, to realize a function of image display.

In this implementation, referring toFIG.1again, it is to be noted that, the LCD further includes a liquid-crystal layer. The working principle of the liquid-crystal layer is that: a certain voltage is applied to upper and lower sides of the liquid-crystal layer to change a rotation angle of liquid crystal, so as to adjust transmittance of light passing through the liquid-crystal layer. In this implementation, the first sharing electrode1141is used to provide a voltage signal for one side of the liquid-crystal layer.

It can be understood that, there must be losses during transmission of a current/voltage in a line. In this implementation, the first segment1141aof the first sharing electrode passes through the pixel electrode111along the second direction D2, which can increase a line of the first sharing electrode1141, so that a voltage at the same side of the pixel electrode111is more uniform, thereby realizing a uniform display effect.

In a possible implementation, referring toFIG.1again, the array substrate1includes a first insulating layer14, where the first insulating layer14at least partially covers the first sharing electrode1141and defines an adapter hole15. The second sharing electrode1142is electrically connected to the first sharing electrode1141through the adapter hole15.

Specifically, the first sharing electrode1141is disposed in the first metal layer13, and the second sharing electrode1142is disposed in the second metal layer16. The first insulating layer14defining the adapter hole15is disposed between the first metal layer13and the second metal layer16. In other words, since the first insulating layer14defines the adapter hole15, the second sharing electrode1142in the second metal layer16can be connected to the first sharing electrode1141in the first metal layer13.

It can be understood that, the first sharing electrode1141is electrically connected to the second sharing electrode1142through the adapter hole15, which can avoid forming of the jagged edge on the sharing electrode114and adding of an additional pad-layer structure in the related art, reducing the space occupied by the insulating layer, and realizing transmission of the sharing-electrode voltage between the first pixel electrode and the second pixel electrode, thereby increasing transmittance of the array substrate and improving a display effect.

In a possible implementation, referring toFIG.1again, the first pixel electrode1111is located on one side of the gate line1a, and the second pixel electrode1112is located on the other side of the same gate line1a.

Specifically, the first pixel electrode1111is connected to the gate line1athrough the first thin-film transistor1121, and the second pixel electrode1112is connected to the same gate line1athrough the second thin-film transistor1122.

It is to be noted that, the first thin-film transistor1121and the second thin-film transistor1122form a common-gate and common-source structure. The gate line1aserves as a common gate of the first thin-film transistor1121and the second thin-film transistor1122, and a common source of the first thin-film transistor1121and the second thin-film transistor1122is an integral structure and connected to the data line1b.

It can be understood that, in this implementation, the first pixel electrode1111is connected to the gate line1athrough the first thin-film transistor1121and is located on one side of the gate line1a; the second pixel electrode1112is connected to the gate line1athrough the second thin-film transistor1122and is located on the other side of the gate line1a. Moreover, the first thin-film transistor1121and the second thin-film transistor1122form a common-gate and common-source structure, which can reduce the number of wiring, optimize a stacked structure, simplify layout of the array substrate and a corresponding manufacturing process, thereby increasing light transmittance and improving a display effect.

In a possible implementation, referring toFIG.1andFIG.3,FIG.3is a schematic cross-sectional view along line II-II inFIG.1. The array substrate1further includes a common electrode115encircling the pixel electrode111and a second insulating layer17covering the second sharing electrode1142. The second insulating layer17defines a via hole18. The pixel electrode111is electrically connected to the drive circuit112through the via hole18.

Specifically, the common electrode115is located in the first metal layer13and disposed around four sides of the pixel unit11.

It can be understood that, the common electrode115is disposed around the four sides of the pixel unit11, to provide a conductive path and transmit a voltage signal. The second insulating layer17defines the via hole18, and the pixel electrode111is electrically connected to the drive circuit112through the via hole18, which can reduce the number of wiring and optimize the stacked structure, thereby further increasing the light transmittance and improving the display effect.

In this implementation, as illustrated inFIG.3, the data line1bis formed in the second metal layer16, the second insulating layer17is formed in the second metal layer16, and the first sharing electrode1141and the first insulating layer14are formed in the first metal layer13. Planarization of a surface of the second insulating layer17in contact with one side of a transparent electrode layer19can be realized, thereby improving a display effect. The second insulating layer17is also used to provide electrical insulation between the second metal layer16and the first insulating layer14. Specifically, the second insulating layer17further defines the via hole18, so that the transparent electrode layer19and the drive circuit112are bridged.

It can be understood that, since an area of the non-light-transmitting region is relatively small, an area of the transparent electrode layer19that allows light to pass through is increased, thereby increasing the light transmittance and improving a display quality.

In a possible implementation, referring toFIG.1again, the via hole18includes a first via-hole181and a second via-hole182. The first pixel electrode1111is electrically connected to the first thin-film transistor1121through the first via-hole181, and the second pixel electrode1112is electrically connected to the second thin-film transistor1122through the second via-hole182. The first via-hole181is close to the data line1b, the second via-hole182is away from the same data line1b, and the adapter hole15is away from the via hole18relative to the same data line1b.

Specifically, the first via-hole181is close to the data line1b, the second via-hole182is away from the same data line1b, and the first via-hole181and the second via-hole182are aligned in a first diagonal direction. For a same data line1b, the adapter hole15is away from a via hole18which is on the same side of the data line1bas the adapter hole15, and adapter holes15are aligned in a second diagonal direction. The first diagonal direction and the second diagonal direction intersect each other.

It can be understood that, the first pixel electrode1111is electrically connected to the first thin-film transistor1121through the first via-hole181, and the second pixel electrode1112is electrically connected to the second thin-film transistor1122through the second via-hole182. The first via-hole181is close to the data line1b, the second via-hole182is away from the same data line1b, and the first via-hole181and the second via-hole182are aligned in the first diagonal direction. For the same data line1b, the adapter hole15is away from one side of the via hole18on the same side as the adapter hole15, and adapter holes15are aligned in the second diagonal direction, where the first diagonal direction and the second diagonal direction intersect each other. As such, an electrical signal interference between the adapter hole15and the via hole18can be reduced, the connection between the pixel electrode111and the drive circuit112can be realized through the via hole18, and transmission of a sharing-electrode signal between the first pixel electrode1111and the second pixel electrode1112can be realized through the adapter hole15, thereby increasing the light transmittance and improving the display effect.

In a possible implementation, referring toFIG.1again, the first sharing electrode1141includes a first segment1141aof the first sharing electrode disposed between the base substrate12and the pixel electrode111and a second segment1141bof the first sharing electrode disposed between the pixel electrode111and the gate line1a. The second segment1141bof the first sharing electrode disposed on one side of the first pixel electrode1111is electrically connected to one end of the second sharing electrode1142. The second segment1141bof the first sharing electrode disposed on one side of the second pixel electrode1112is electrically connected to the other end of the second sharing electrode1142.

Specifically, the projection of the first sharing electrode1141on the base substrate12at least partially overlaps the projection of the pixel electrode111on the base substrate12, that is, the first segment1141aof the first sharing electrode. The first segment1141aof the sharing electrode passes through the pixel electrode111along the second direction D2. The second segment1141bof the first sharing electrode encircles one side of a via hole18on the same side as the second segment1141b. The first segment1141aand the second segment1141bof the first sharing electrode are an integral structure.

It can be understood that, the first sharing electrode1141includes the first segment1141aof the first sharing electrode disposed between the base substrate12and the pixel electrode111and the second segment1141bof the first sharing electrode disposed between the pixel electrode111and the gate line1a. The second segment1141bof the first sharing electrode disposed on one side of the first pixel electrode1111is electrically connected to one end of the second sharing electrode1142through the adapter hole15. The second segment1141bof the first sharing electrode disposed on one side of the second pixel electrode1112is electrically connected to the other end of the second sharing electrode1142through the adapter hole15. As such, a stacked structure can be optimized, a pad layer of the first metal layer13in the related art can be removed, the space occupied by the insulating layer can be reduced, and transmission of the sharing-electrode signal between the first pixel electrode and the second pixel electrode can be realized, thereby improving the transmittance of the array substrate and the display effect.

In a possible implementation, referring toFIG.1again, the first thin-film transistor1121, the second thin-film transistor1122, and the third thin-film transistor113are disposed along the first direction D1.

Specifically, the first thin-film transistor1121, the second thin-film transistor1122, and the third thin-film transistor113are disposed in the first direction D1of the gate line1a. The first thin-film transistor1121and the second thin-film transistor1122form a common-gate and common-source structure. The common-gate and common-source structure is spaced apart from the third thin-film transistor113in the first direction D1. The first thin-film transistor1121is configured to drive the first pixel electrode1111, and the second thin-film transistor1122is configured to drive the second pixel electrode1112.

It is to be noted that, in other possible implementations, there may be other numbers of the drive circuits112and the third thin-film transistors113, which are not limited in the disclosure.

It can be understood that, the first thin-film transistor1121and the second thin-film transistor1122form a common-gate and common-source structure. The common-gate and common-source structure is spaced apart from the third thin-film transistors113in the first direction D1. The first thin-film transistor1121is configured to drive the first pixel electrode1111, and the second thin-film transistor1122is configured to drive the second pixel electrode1112. As such, an occupancy rate of a device space and an occupancy space of the insulating layer can be reduced, a stack structure can be optimized, and transmission of the sharing electrode signal between the first pixel electrode and the second pixel electrode can be realized, thereby improving the transmittance of the array substrate and the display effect.

In a possible implementation, referring toFIG.1again, a width of the second segment1141bof the first sharing electrode is greater than a width of the first segment1141aof the first sharing electrode.

Specifically, the width of the second segment1141bof the first sharing electrode is greater than the width of the first segment1141aof the first sharing electrode, and a length of the second segment1141bof the first sharing electrode is less than a length of the first segment1141aof the first sharing electrode.

It can be understood that, the second segment1141bof the first sharing electrode is wider than the first segment1141aof the first sharing electrode, which is beneficial to defining the adapter hole15in the first insulating layer14on the second segment1141bof the first sharing electrode. Moreover, while ensuring a function of the first segment1141aof the first sharing electrode, the width of the first segment1141aof the first sharing electrode should be as small as possible, and accordingly, an area of the first segment1141ashould be small, so that an area of a space occupied by the pixel electrode111is as large as possible, thereby optimizing a device layout structure, increasing the transmittance of the array substrate, and improving the display effect.

The disclosure further provides a method for manufacturing an array substrate. Also, referring toFIG.4,FIG.4is a schematic flowchart illustrating a method for manufacturing an array substrate provided in an implementation of the disclosure. The method includes operations from S401to S408, and the operations from S401to S408will be depicted in detail below.

At S401, a base substrate12is provided.

At S402, a first metal layer13is formed on the base substrate12, and gate lines1a, a common electrode115, and a first sharing electrode1141are formed by patterning the first metal layer13.

Specifically, referring toFIG.5andFIG.6,FIG.5is a schematic top view illustrating array substrate manufacturing provided in an implementation of the disclosure, andFIG.6is a schematic cross-sectional view along line I-I inFIG.5. In this implementation, the common electrode115and the first sharing electrode1141are formed by etching the first metal layer13through a mask. For details of the first metal layer13, the gate line1a, the common electrode115, and the first sharing electrode1141, reference can be made to the foregoing description, which will not be repeated herein.

At S403, a first insulating layer14is formed on the first metal layer13.

Specifically, the first insulating layer14at least partially covers the first sharing electrode1141.

At S404, an adapter hole15is defined in the first insulating layer14.

At S405, a second metal layer16is formed on the first insulating layer14, and data lines1b, a source and a drain of a drive circuit112, and a second sharing electrode1142are formed by patterning the second metal layer16, where the second sharing electrode1142is electrically connected to the first sharing electrode1141through the adapter hole15.

Specifically, referring toFIG.7,FIG.8, andFIG.9,FIG.7is a schematic top view illustrating array substrate manufacturing provided in another implementation of the disclosure,FIG.8is a schematic cross-sectional view along line I-I inFIG.7, andFIG.9is a schematic cross-sectional view along line II-II inFIG.7. In this implementation, the source and the drain of the drive circuit112and the second sharing electrode1142are formed by etching the second metal layer16through a mask, which can avoid adding of an additional pad layer in the related art, so that an area of a light-transmitting region of the array substrate1is increased, thereby increasing light transmittance. For details of the first insulating layer14, the adapter hole15, the second metal layer16, the data line1b, the source and the drain of the drive circuit112, the source113aand the drain113bof the third thin-film transistor, and the second sharing electrode1142, reference can be made to the foregoing description, which will not be repeated herein.

At S406, a second insulating layer17is formed on the second metal layer16.

At S407, a via hole18is defined in the second insulating layer17.

At S408, a transparent electrode layer19is manufactured on the second insulating layer17, and a pixel electrode111is formed by patterning the transparent electrode layer19.

Specifically, referring toFIG.1again, the second insulating layer17covers the second sharing electrode1142, so that planarization of a surface of the second insulating layer17in contact with one side of the transparent electrode layer19can be realized while the second insulating layer17can protect the second sharing electrode1142, thereby improving a display effect. Moreover, the second insulating layer17is also used for electrical insulation between the second metal layer16and the first insulating layer14. The via hole18is used to realize an electrical connection between the pixel electrode111and the drive circuit112. For details of the second metal layer16, the second insulating layer17, the via hole18, the transparent electrode layer19, and the pixel electrode111, reference can be made to the foregoing description, which will not be repeated herein.

It can be understood that, in this implementation, the first sharing electrode1141is electrically connected to the second sharing electrode1142through the adapter hole15, which can reduce a space occupied by the first insulating layer14. Moreover, the second sharing electrode wire1142is directly disposed on a side surface of the first insulating layer14away from the first sharing electrode1141, so that a thickness of the array substrate1in a stacked direction is reduced, which can reduce an area of a non-light-transmitting region and increase an area of a light-transmitting region of the array substrate1, thereby increasing the light transmittance and improving the display effect.

It is to be noted that, in the disclosure, forming of the first sharing electrode1141, the second sharing electrode1142, the source113aand the drain113bof the third thin-film transistor, and so on by etching the metal layer through a mask is exemplarily depicted, which, however, does not mean that forming of the involved lines is limited in the disclosure, as long as it does not affect that the second sharing electrode1142is electrically connected to the first sharing electrode1141through the adapter hole15, which is not limited in the disclosure.

The disclosure further provides a display panel2. Also, referring toFIG.10,FIG.10is a schematic cross-sectional view illustrating a display panel provided in an implementation of the disclosure. The display panel2includes a color-film substrate21, a liquid-crystal layer22, a backlight source23, and the above array substrate1. The array substrate1is disposed opposite to and spaced apart from the color-film substrate21to form a receiving space. The liquid-crystal layer22is disposed in the receiving space. Specifically, for details of the array substrate1, reference can be made to the foregoing description, which will not be repeated herein.

It can be understood that, in this implementation, the array substrate1has relatively high transmittance, so that light emitted by the backlight source23and passing through the array substrate1, the liquid-crystal layer22, and the color-film substrate21enables the display panel2to increase the display brightness by about 3%, compared to the related art.

While the principles and implementations of the disclosure have been depicted in connection with illustrative implementations, it is to be understood that foregoing implementations are merely used to help understand the core idea of the disclosure. As will occur to those skilled in the art, the disclosure is susceptible to various modifications and changes without departing from the spirit and principle of the disclosure. Therefore, the disclosure is not to be limited to the disclosed implementations.