Patent ID: 12254909

DETAILED DESCRIPTION

The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

The embodiments described below are not intended to limit the invention to the precise form disclosed, nor are they intended to be exhaustive. Rather, the embodiment is presented to provide a description so that others skilled in the art may utilize its teachings. Technology continues to develop, and elements of the described and disclosed embodiments may be replaced by improved and enhanced items, however the teaching of the present disclosure inherently discloses elements used in embodiments incorporating technology available at the time of this disclosure.

In some cases, the power large scale integrated circuit (PLSI) comprises a voice coil motor (VCM) driver (shown as VCM driver1002inFIG.10), where the VCM driver applies current to the VCM to actuate the VCM. During a seek operation, the VCM driver (also referred to as a power driver of the VCM) is primarily driven in a pulse width modulation (PWM) mode, which serves to reduce power consumption. However, as the actuator arm assembly comprising the disk heads approaches the target track, the control circuitry22switches the drive operation to a linear mode. While the linear mode consumes more power than the PWM mode, it allows for improved accuracy and less current ripple. This transition between the PWM and linear modes generally induces an offset (e.g., steady-state or transition offset), overshoot or undershoot, a steady-state error, or a transient error (e.g., an error in the delta current). In some circumstances, this offset is affected by one or more factors, such as, but not limited to, slew rate of the rise/fall of PWM square wave voltage and frequency of the PWM square wave that produces the effective current to the VCM motor, current level (e.g., of the VCM current), and/or direction (e.g., towards the inner diameter or ID, towards the outer diameter or OD of the disk). As noted above, currently used techniques attempt to pick an “optimum” PWM frequency and slew rate combination that minimizes the offset between the PWM and linear modes. In some circumstances, if the offset is still too high (exceeds a pre-defined threshold), the VCM may be operated for a longer time in the linear mode before the actuator arm assembly finally seeks over the target track. While this allows the servo controller more time to compensate for the position error signal (PES) and reduce the error, such a design is not without its drawbacks, namely, extra power consumption due to the longer time spent in the linear mode during the seek operation.

Aspects of the present disclosure are directed to a refined hardware/firmware (HW/FW) interaction technique for reducing or minimizing the offset between the PWM and linear modes. This may serve to (1) enhance the PES by reducing the offset between PWM and CCL modes, (2) reduce the time in linear mode, (3) reduce power consumption during seeking due to the reduced time in linear mode, and/or (4) allow more flexibility for VCM PWM frequency and/or slew rate settings.

Turning now toFIGS.2A and2B, which illustrate conceptual block diagrams of a top view and a side view of a data storage device in the form of a disk drive15, in accordance with aspects of the present disclosure. Disk drive15comprises control circuitry22, an actuator assembly19, and a plurality of hard disks16A,16B,16C,16D (“hard disks16,” “disks16”).FIG.2Cdepicts a flowchart for an example method80that control circuitry22of disk drive15may perform or execute in controlling the operations of disk drive15, including the operations of heads18(e.g., heads18A-18H) disposed on actuator assembly19, in accordance with aspects of the present disclosure, as further described below. Actuator assembly19thus comprises heads18and is configured to position the one or more heads18over disk surfaces17of the one or more disks16. Heads18may each comprise write and read elements, configured for writing and reading control features and data to and from a corresponding disk surface17of hard disks16.

Actuator assembly19comprises a primary actuator20(e.g., a voice coil motor or VCM, also shown as VCM1025inFIG.10) and a number of actuator arms40(e.g., topmost actuator arm40A, as seen in the perspective view ofFIGS.2A and2B). Each of actuator arms comprises a head18at a distal end thereof (e.g., example head18A comprised in topmost actuator arm40A, in the view ofFIGS.2A and2B). Each of actuator arms40is configured to suspend one of heads18in close proximity over a corresponding disk surface17(e.g., head18A suspended by topmost actuator arm40A over topmost corresponding disk surface17A, head18H suspended by lowest actuator arm40H over lowest corresponding disk surface17H). Various examples may include any of a wide variety of other numbers of hard disks and disk surfaces, other numbers of actuator arm assemblies and primary actuators besides the one actuator assembly19and the one primary actuator20in the example ofFIGS.2A and2B, and other numbers of fine actuators on each actuator arm, for example.

FIG.2Aalso depicts servo sectors32(e.g., servo sectors321through32N) written onto disk surfaces17. In some cases, when manufacturing a disk drive, servo sectors32may be written to disk surfaces17to define a plurality of evenly-spaced, concentric tracks34. As an example, each servo sector32may include a phase lock loop (PLL) field, a servo sync mark (SSM) field, a track identification (TKID) field, a sector ID, and a group of servo bursts (e.g., an alternating pattern of magnetic transitions) that the servo system of the disk drive samples to align the moveable transducer head (e.g., disk head18) with and relative to, a particular track34. Each circumferential track34includes a plurality of embedded servo sectors32utilized in seeking and track following. The plurality of servo sectors32are spaced sequentially around the circumference of a circumferential track34and extend radially outward from the inner diameter (ID) of disk surface17. These embedded servo sectors32contain servo information utilized in seeking and track following and are interspersed between data regions on disk surfaces17. Data is conventionally written in the data regions in a plurality of discrete data sectors. Each data region is typically preceded by a servo sector32.

In some examples, the control circuitry22is configured to control the actuation of the primary actuator (i.e., VCM). Further, the VCM is configured to actuate the head18over the disk surfaces17. In some embodiments, the VCM is configured to operate in a first mode and a second mode, the first mode and the second mode each comprising one of a pulse width modulation (PWM) mode and a linear or current control loop (CCL) mode, where the first mode is different from the second mode, and where the first mode corresponds to a first offset compensation value and the second mode corresponds to a second offset compensation value. The control circuitry22is also configured to cause the VCM to seek towards a target track in the first mode for a first duration (82), transition control of the VCM from under the first mode to to the second mode (84). In some examples, transitioning the VCM comprises switching, at or near an end of the first duration, an offset compensation value from the first offset compensation value to the second offset compensation value to compensate for a transition offset induced while transitioning the VCM from the first mode to the second mode (86), and seeking the VCM toward the target track in the second mode for a second duration (88).

In some embodiments, the control circuitry22provides a PWM control signal to digital transistor switches providing an idle current to the VCM. In one non-limiting example, the PWM modulation circuit includes a plurality of digital transistor switches which provide current in a single direction through the VCM. A sense resistor (shown as RsinFIG.10) provides a sensed voltage proportional to the current through the VCM. This sensed voltage is amplified by an amplifier, herein referred to as a current sense amplifier (CSA), shown as CSA1040inFIG.10. In some examples, a comparator circuit provides a comparator output when said amplified voltage exceeds a predetermined value. A delay circuit may be used to activate the transistor switches and turn of a transistor switch in response to the comparator indicating a peak value has been reached. The delay circuitry may also simultaneously start a delay timer, which keeps the switch off for a predetermined time delay until the control current has decayed to the lowest desired value.

It should be noted that, other techniques for generating a PWM drive voltage are contemplated in different embodiments. For example, the control circuitry22or the VCM driver24may form a drive current command (e.g., VCM control signal38inFIG.2A, drive command1008inFIG.10) for actuating the VCM based on the position error signal or PES. This drive current command may be converted into an analog signal (shown as VDAC inFIG.10) by a digital/analog conversion circuit (DAC). In some cases, an output side amplifier (e.g., in the control circuitry22or the VCM driver24) forms a drive voltage having a slew rate (e.g., 50 V/us, 200 V/us, etc.), where the drive voltage is used to drive the VCM. A switch may be used to toggle/transition between the linear and PWM modes. In the linear mode, the drive voltage may be used to directly drive the VCM. Further, in the PWM mode, the drive voltage may be converted into a pulse signal (e.g., by a linear PWM modulation circuit) and input to the VCM. In some cases, the actual measured current (ISENSEor IS1006inFIG.10) may be converted into a voltage signal by a sense resistor (Rs), where the voltage signal is amplified by the CSA and used as a feedback signal (e.g., for the amplifier forming the drive voltage). Further, the CSA output voltage (i.e., corresponding to the actual measured current) is subtracted from the commanded DAC voltage to determine an error signal. In some examples, this error is amplified (e.g., with a certain desired bode response) and the power driver (e.g., power driver1002inFIG.10) is used to drive that error signal. As a result, the drive voltage causes a drive current proportional to the analog signal to flow through the VCM. In some circumstances, an output offset (e.g., shown inFIG.8B) with respect to the drive current may occur between the PWM and the linear mode, which may lead to current oscillations/fluctuations during the transition between the two modes. In some cases, this output offset is a steady-state offset between the PWM and CCL modes.

As noted above, the VCM driver24is primarily in PWM mode during a seek to a target track, which serves to enhance power efficiency. However, as the disk head approaches the target track, the control circuitry22is configured to switch the VCM driver24to linear mode. While the linear mode utilizes more power than the PWM mode, the linear mode provides better accuracy and less current ripple, thus reducing the PES. Some aspects of the present disclosure are directed to enhancing accuracy (i.e., reducing PES, such as a track arrival PES) at the end of the seek operation, while simultaneously reducing the time spent in the linear mode. In some circumstances, the present disclosure may serve to reduce the power consumption (e.g., at least 100 mW, at least 200 mW, up to or around 500 mW, etc.) per seek operation, as compared to the prior art. This facilitates in reducing battery size and/or enhancing battery life for devices, to name two non-limiting examples.

In the embodiment ofFIG.2A, the control circuitry22may comprise a VCM driver24(also referred to as a VCM power driver24). The VCM power driver24may implement one or more aspects of the power driver1002described in relation toFIG.10. Further, the control circuitry22may process a read signal emanating from the head18to demodulate servo data written on the disk (e.g., servo sectors32) to generate a position error signal (PES) representing an error between the actual position of the head and a target position relative to a target track. The control circuitry22may process the PES using a suitable servo control system to generate the VCM control signal38applied to the VCM20which rotates an actuator arm40about a pivot in order to actuate the head18radially over the disk surface17in a direction that reduces the PES. In one embodiment, the disk drive may also comprise a suitable microactuator, such as a suitable piezoelectric (PZT) element for actuating the head18relative to a suspension, or for actuating a suspension relative to the actuator arm40.

In one embodiment, the servo data (e.g., servo sectors32) read from the disk surface17, i.e., in order to servo the head over the disk during access operations, may be self-written to the disk using the control circuitry22internal to the disk drive. In some examples, a plurality of spiral servo tracks are first written to the disk surface17, and then servo sectors32are written to the disk while servoing on the spiral servo tracks. In order to write the spiral servo tracks to the disk surface17, at least one bootstrap spiral track is first written to the disk without using position feedback from servo data (i.e., the actuator or VCM20is controlled open loop with respect to servo data on the disk). Before writing the bootstrap spiral track, feedforward compensation is generated by evaluating the back electromotive force (BEMF) voltage generated by the VCM20during a calibration seek (where the BEMF voltage represents an estimated velocity of the VCM). The bootstrap spiral track is then written to the disk using the feed-forward compensation.

Turning now toFIG.10, which illustrates a schematic diagram1000of a Voice Control Motor (VCM) driver circuit1002of a data storage device, such as a disk drive, in accordance with aspects of the present disclosure. In some cases, voice coil actuators work on the principle of a permanent magnetic field and a coil winding. When a current is applied to the VCM coil, a force is generated. This force, known as the Lorentz force, is directly proportional to the input current. By controlling the amount of current applied to the motor, accurate motor positioning may be achieved. In some examples, the current applied to the VCM may be controlled using a current control loop (CCL). In CCL, a sense resistor (Rs) is placed in series to the VCM and the voltage across that sense resistor is sensed. InFIG.10, circuitry1025represents an example representation of the VCM, where current1006corresponds to the current flowing through the windings of the VCM. As seen, the VCM driver circuit1002is connected to a digital to analog converter (DAC) that outputs a DAC voltage (VDAC). The VCM driver circuit1002further comprises a current sense amplifier (CSA)1040having a gain (Gs) that amplifies the voltage across the sense resistor (Rs), where the amplified voltage is shown as VSNS Specifically, the sensed current (ISENSEor IS1006) flowing through the VCM1025is converted into a voltage signal using the sense resistor (Rs) and amplified by the CSA1040. In this example, VDAC/Ri=VSNS/Rf, where VSNS=Gs×Rs×Is, and Gs=gain of CSA1040. Thus, the sensed current1006can be calculated as: Is=VDAC×(Rf/Gs×Rs×Ri).

FIG.3shows an example graph300of a current offset301(on the vertical or y-axis305) against a decimal value302(on the horizontal or x-axis310), where the decimal values302are stored in a register. In some embodiments, the PLSI circuitry (e.g., control circuitry22) is configured to introduce an offset (also referred to as offset compensation) in at least one of the PWM and linear/CCL modes via one or more hardware (HW) implementations, where the offset is used to compensate for a steady-state error between the two modes. In one non-limiting example of a HW implementation, an input offset of a current sense amplifier (CSA) may be trimmed, which results in the output of the CSA being trimmed, for instance, by a few millivolts (mV). In some cases, the amount of CSA offset trimmed may be constrained within a certain range (e.g., up to +/−1 mV, up to +/−5 mV, up to +/−10 mV, to name a few non-limiting examples). The trimming of the CSA offset by the control circuitry22may translate to a steady-state offset in the VCM current, i.e., a VCM current offset301, that compensates for the offset created in the PWM mode. As an example, if the CCL offset (i.e., offset in the linear mode) is 0 mA and the PWM offset (i.e., offset in the PWM mode) is 3 mA, the CSA offset may be set to −3 mA when operating in the PWM mode and 0 mA when operating in the CCL mode. In another example, the CCL offset is 2 mA and the PWM offset is 6 mA. Here, the CSA offset may be set to −2 mA for the CCL mode and −6 mA for the PWM mode. The offsets and corresponding offset compensation values listed herein are exemplary and not intended to be limiting. Aspects of the disclosure may support compensation of a wide variety of transient and steady-state offsets created during normal operations (e.g., seeking) of a disk drive.

In some other cases, the VCM DAC may be adjusted based on the steady-state offset/error between the PWM and CCL modes. For example, a pre-defined number of least significant bits (LSB) corresponding to the offset compensation (i.e., desired current offset) may be added or subtracted from the VCM DAC. While not necessary, in some embodiments, this adjustment of the VCM DAC may be hidden to the FW. In such cases, the firmware (FW) DAC receives the hardware (HW) DAC offset that has already been adjusted to compensate for the steady-state offset or error between the two modes.

In some cases, the VCM current offset301may be +/−10 mA, although other ranges of VCM current offsets are contemplated in different embodiments. The range of VCM current offset selected may be based on one or more factors, such as, the complexity of hardware design permissible for a certain use case. For instance, a larger range of current offset (e.g., +/−10 mA as compared to +/−1 mA) may serve to reduce the complexity of the hardware design (e.g., lower die, cost, etc.) but also reduce the granularity (e.g., mA resolution/bit) of the offset compensation in the PWM/CCL mode. In some use-cases, a lower offset difference (e.g., +/−1 mA) may be implemented, for instance, when higher accuracy (lower track arrival PES) is needed. In some examples, the present disclosure may support resolution control (e.g., using a register for storing decimal values) to have finer control of offset compensation in the PWM and CCL mode(s). In the example shown inFIG.3, six (6) bit decimal values are used in the register to control the offset. Specifically,FIG.3depicts an example of a lookup table/function, register, or another data structure, that may be used to control the offset in the PWM or CCL mode. Here, each current offset data point315corresponds to a six (6) bit decimal value (X-intercept). For example, when the decimal value is 11111, the current offset equals the positive Y-intercept (e.g., +10 mA current offset). Similarly, when the decimal value is 100000, the current offset equals the negative Y-intercept (e.g., −10 mA). Using these values (e.g., +/−10 mA offset and a 6-bit decimal value), the resolution/bit may be calculated to be about 0.31 mA resolution/bit. It should be noted that, the examples listed herein are in no way intended to be limiting. For example, a different number of bits (e.g., 4-bits, 8-bits, 16-bits, etc.) and/or a different current offset range (e.g., +/−1 mA, +/−5 mA, +/−20 mA) may be utilized in different embodiments.

In some examples, the control circuitry22is configured to trim the CSA offset based on selecting the specific decimal value (e.g., 111111) corresponding to the VCM current offset compensation. In some cases, two HW registers (e.g., one for the PWM mode offset and one for the CCL mode offset) may be utilized. WhileFIG.3shows one example of a register (e.g., for the PWM mode offset), it should be understood that a similar or substantially similar register may be used for the other mode. Further, the number of bits of decimal values used and/or the current offset range for the PWM and CCL offsets registers may be the same or different.

In some other cases, the control circuitry22automatically switches the offset compensation to the PWM mode offset or the linear/CCL mode offset when the mode of operation of the VCM is switched. In some cases, the control circuitry22or the firmware (FW) is configured to switch the VCM mode of operation and/or the offset compensation. In such cases, a different VCM offset (e.g., a PWM mode offset, a CCL mode offset) may be utilized depending on the current mode of operation, i.e., PWM mode or CCL mode, and the new mode of operation of the VCM. When the control circuitry22detects a transition of the VCM from one mode (e.g., PWM mode) to the other mode (e.g., CCL mode), the VCM driver24or the control circuitry22switches the VCM current offset/offset compensation, which allows for compensation of the steady-state offset between the two modes.

In some embodiments, aspects of the present disclosure may be implemented in both FW and HW. For example, the FW may utilize a tuning method to optimize the PES as the disk head arrives at the target track during a seek, while also optimizing power consumption by operating the seek in the PWM mode for a longer duration, as compared to the prior art. In some examples, the FW may utilize a calibration routine, where the calibration routine results in a lookup table/function, or another data structure, of different tunings recorded for different seek lengths (e.g., seek duration, seek distance), heads, and/or directions (e.g., from inner diameter or ID to outer diameter or OD, from OD to ID). In some aspects, utilizing different seek lengths (i.e., as opposed to a single static seek length) may help account for the variation in bias current to hold the VCM in place at different locations on the disk surface. In some cases, the calibration routine may comprise an initial calibration phase, where a binary search is used to sweep through different VCM current offset values during seeks to identify an optimal offset value that results in the lowest PES (i.e., the lowest PWM/CCL steady-state offset). As an example, a steady-state offset in each of the PWM and CCL modes may be determined using a first seek length and direction (e.g., ID to OD of disk). For instance, if the PWM offset is 3 mA and the CCL offset is 0 mA, a −3-mA offset may be set in the PWM offset register to compensate for the 3-mA offset created while operating in the PWM mode. In some cases, the FW may be configured to update this offset compensation value (−3 mA) in the PWM offset register for different seek lengths, heads, and/or directions. For example, if the PWM offset in a second direction (e.g., OD to ID of disk) is 4 mA, the −3-mA offset compensation value may be used while operating in the PWM mode and seeking in the first direction and a −4-mA offset compensation value may be used while operating in the PWM mode and seeking in the second direction.

FIG.4depicts a visual example demonstrating the binary search concept described above. As seen,FIG.4shows an example graph400of current offset401(on the vertical or y-axis405) against a decimal value402(on the horizontal or x-axis410), where the decimal values correspond to the values implemented in the register. The arrows460(e.g., arrows460-a,460-b,460-c,460-d) depict the flow of the binary search algorithm and the last arrow460-dshows the final data point415corresponding to the most optimal track arrival PES (or lowest PWM-CCL offset).

FIG.5illustrates example graphs for a calibration routine implemented in the FW, according to various aspects of the disclosure. In some cases, the calibration routine described in relation toFIG.5may be performed after an initial offset compensation value is obtained. Graph500-adepicts the linear mode time505(e.g., in ms) against PWM mode time511, where the linear mode time505refers to the “time spent in linear mode”. Further, graph500-bdepicts the PES510(e.g., as a percentage of servo track width) against the PWM mode time511, while graph500-cdepicts the power used515against the PWM mode time511. After determining a preliminary/initial offset compensation value, the control circuitry22incrementally decreases the time spent in linear mode, as shown in graph500-a. As seen, the power used decreases as the amount of time spent in linear mode decreases (i.e., as the amount of time spent in PWM mode increases). In contrast, the PES (e.g., track arrival PES) increases as the time spent in linear mode decreases. As shown in graph500-b, there is a negligible increase in the PES (i.e., when the PWM mode time is below time551), followed by a sharp increase (i.e., when the PWM mode time is above time551). In some examples, the FW determines the linear mode time based on this time551. Specifically, the FW selects time551as the PWM mode time and determines the y-intercept552in graph500-aas the linear mode time. In this way, the control circuitry22and/or the FW determines the lowest amount of time that the VCM can spend in the linear mode with minimal to no impact on the PES. By decreasing the linear mode time for the VCM, as compared to the prior art, the control circuitry22helps optimize the power consumption during seek operations.

FIG.6illustrates an example graph600of the CCL-PWM current offset642(e.g., steady-state offset between PWM and CCL modes) against VCM current641, according to various aspects of the disclosure. As described above, an offset is created between the linear mode and the VCM mode when the same VCM current is supplied to the VCM. In some circumstances, a transient current fluctuation may also be generated during the transition between the two modes, for example, by a voltage corresponding to the offset at the output stage of the VCM driver.

In some cases, the control circuitry22reapplies the binary search algorithm (e.g., described in relation toFIG.4) after each time step reduction in the linear mode, since the CCL-PWM current offset changes based on the VCM current level (or time spent in linear mode). For example, as seen in graph600, the offset shown on the vertical or y-axis varies based on the VCM current applied. Graph600also depicts the relation of the offset for each VCM current level (e.g., −300 mA, −250 mA, 100 mA, 150 mA, etc.) applied with respect to different PWM frequency and slew rate combinations. Specifically, the different bar graphs for each VCM current level correspond to different PWM frequency and slew rate combinations. In this example, the PWM frequency and slew rates are in units of kHz and V/uS, respectively. As seen, the CCL-PWM current offset at the same VCM current641level varies for different PWM frequency and slew rate combinations (e.g., 90 kHz, 50 V/uS; 90 kHz, 200 V/uS; 210 kHz, 200 V/uS, etc.).

FIG.7illustrates an example of a method700for determining an optimal linear mode time and/or an offset value, according to various aspects of the disclosure. The method700may be implemented by the control circuitry22, or alternatively, the VCM driver24. In other cases, the method700may be implemented in the FW. Further, the method flow700implements one or more aspects of the calibration routine and tuning method described above and elsewhere throughout the disclosure.

At step701, the method comprises setting an initial time in linear mode and/or setting an initial offset value (e.g., VCM current sense offset to compensate for the PWM-CCL modes steady-state offset). In one non-limiting example, the initial linear mode time and offset compensation value may be determined as described above in relation toFIGS.4and5. For example, the control circuitry22may perform a calibration routine to sweep through different offset compensation values to find the offset compensation value resulting in the lowest PES, which may be indicative of the lowest PWM-CCL transition offset (e.g., a steady-state offset between the PWM and CCL modes).

At step702, the method comprises decreasing the linear mode time by an interval amount (e.g., 1 μs, 3 μs, etc.). Next, at step703, the method comprises performing a search (e.g., a binary search) to optimize the initial offset compensation value based on the new linear mode time. As described in relation toFIG.5, the FW or the control circuitry22may be configured to incrementally reduce the time in linear mode and monitor the corresponding track arrival PES. This enables an optimal linear mode time to be determined, which helps reduce power consumption during seek operations. In this way, the present disclosure helps reduce the time spent in linear mode, without adversely impacting the track arrival PES.

At step704, the control circuitry22, or the servo control system, determines whether the PES (i.e., for the new linear mode time and offset value) is worse than the PES for the prior linear mode time/offset value. If yes, at step705, the method700comprises determining a final linear mode time and offset value to compensate for the PWM-linear mode transition offset (e.g., a steady-state offset between the two modes). That is, at step705, the control circuitry22(or the FW) determines the linear mode time and offset value combination corresponding to the lowest PES. If no, the method700returns to step702and continues until an optimum linear mode time and/or offset value is determined (i.e., when the decision at step704is Yes).

At step706(optional), the method comprises repeating steps701-705for different seek lengths or directions. As previously noted, the bias current to hold the VCM in place over a certain location on the disk surface may vary at different locations (e.g., for different seek lengths).

FIGS.8A-8Cdepict conceptual graphs800of VCM waveforms during a transition from PWM mode to linear mode in the prior art. Graph800-adepicts the VCM current against time for two different VCM PWM frequency/slew combinations. Currently, FW uses a 210 Khz PWM frequency and a 50 V/uS slew rate for the VCM PWM mode. Ideally, a higher slew rate (e.g., 200 V/uS) may help reduce power consumption. However, a higher slew rate leads to a larger transition/steady-state offset between the two modes, which needs to be compensated for to reduce the PES or random transient vibrations (RTV). Accordingly, to reduce PES, currently used techniques utilize a lower slew rate (e.g., 50 V/uS) while operating the VCM in the PWM mode. This adversely impacts the power efficiency of the HDD. As seen,FIG.8Bdepicts a zoomed-in view of the transition810inFIG.8A, including a first/baseline VCM current waveform830(e.g., for a 210 kHz PWM frequency and a 50 V/uS slew rate) and a second VCM current waveform831(e.g., for a 210 kHz PWM frequency and a 200 V/uS slew rate).FIG.8Balso depicts the offset820between the baseline vs the higher slew rate plot. In some circumstances, this offset820results in an oscillation in the VCM current as the servo control loop tries to correct the offset. For example,FIG.8Cdepicts averaged VCM current waveforms for both the baseline (shown as832) and the higher slew rate (shown as833). As seen, there is more oscillation when a higher slew rate is used as compared to the baseline.

FIGS.9A-9Cdepict conceptual graphs900of VCM waveforms during a transition from PWM mode to linear mode and after compensating for the PWM-CCL mode transition offset, according to various aspects of the disclosure. In some cases, the PWM-CCL mode transition offset, which may be a steady-state offset between the two modes, introduced from a higher slew rate (e.g., 200 V/uS vs 50 V/uS) may be compensated by trimming the VCM current sense offset. Similar to graphs800-a-c, graph900-adepicts the VCM voltage against time for two different VCM PWM frequency/slew combinations. Further, graph900-bdepicts a zoomed-in view of the transition910inFIG.9A, showing the reduction (as compared to graph800-b) in the transition/steady-state offset achieved by trimming the VCM current sense offset. As noted above, the CSA output voltage may be affected when the input to the CSA1040is trimmed. For example, the trimming of the CSA1040input may cause the output voltage at the CSA1040to also be trimmed. Since the output voltage at the CSA1040is subtracted from the VCM DAC to generate an error signal and the power driver is used to drive an amplified version of the error signal, the trimming of the VCM current sense offset helps compensate for the steady-state offset between the PWM and CCL modes. As an example, a higher slew rate may introduce a −5-mA offset between the two modes. In accordance with various aspects of the disclosure, the VCM current sense offset may be trimmed (e.g., to 0.4 mV, which may correspond to about a +5-mA offset in the VCM current), enabling compensation of the PWM-CCL steady-state offset introduced from the higher slew rate.

It should be noted that, frequency/slew rate combinations and/or offset values (e.g., VCM current sense offset, PWM-CCL transition or steady-state offset, offset compensation values) discussed above in relation toFIGS.8and9are exemplary only and not intended to be limiting. They are meant to elucidate the flexibility in the VCM PWM frequency and/or slew rate settings provided in accordance with aspects of the disclosure. Further, whileFIGS.8and9generally discuss varying the slew rate, this is in no way intended to be limiting. It is contemplated that the VCM PWM frequency may also be varied (i.e., in addition to, or in lieu of, the slew rate). In some cases, varying the PWM frequency may also introduce an offset that may be compensated, for instance, by trimming the VCM current sense offset.

Any suitable control circuitry may be employed to implement the flow diagrams in the above examples, such as any suitable integrated circuit or circuits. For example, the control circuitry may be implemented within a read channel integrated circuit, or in a component separate from the read channel, such as a data storage controller, or certain operations described above may be performed by a read channel and others by a data storage controller. In one example, the read channel and data storage controller are implemented as separate integrated circuits, and in another example, they are fabricated into a single integrated circuit or system on a chip (SoC). In addition, the control circuitry may include a preamp circuit implemented as a separate integrated circuit, integrated into the read channel or data storage controller circuit, or integrated into an SoC.

In some examples, the control circuitry comprises a microprocessor executing instructions, the instructions being operable to cause the microprocessor to perform the flow diagrams described herein. The instructions may be stored in any computer-readable medium. In some examples, they may be stored on a non-volatile semiconductor memory device, component, or system external to the microprocessor, or integrated with the microprocessor in an SoC. In some examples, the instructions are stored on the disk and read into a volatile semiconductor memory when the disk drive is powered on. In some examples, the control circuitry comprises suitable logic circuitry, such as state machine circuitry. In some examples, at least some of the flow diagram blocks may be implemented using analog circuitry (e.g., analog comparators, timers, etc.), and in other examples at least some of the blocks may be implemented using digital circuitry or a combination of analog and digital circuitry.

In various examples, one or more processing devices may comprise or constitute the control circuitry as described herein, and/or may perform one or more of the functions of control circuitry as described herein. In various examples, the control circuitry, or other one or more processing devices performing one or more of the functions of control circuitry as described herein, may be abstracted away from being physically proximate to the disks and disk surfaces. The control circuitry, or other one or more processing devices performing one or more of the functions of control circuitry as described herein, may be part of or proximate to a rack of or a unitary product comprising multiple data storage devices, or may be part of or proximate to one or more physical or virtual servers, or may be part of or proximate to one or more local area networks or one or more storage area networks, or may be part of or proximate to a data center, or may be hosted in one or more cloud services, in various examples.

In various examples, a disk drive may include a magnetic disk drive, an optical disk drive, a hybrid disk drive, or other types of disk drive. In addition, some examples may include electronic devices such as computing devices, data server devices, media content storage devices, or other devices, components, or systems that may comprise the storage media and/or control circuitry as described above.

The various features and processes described above may be used independently of one another or may be combined in various ways. All possible combinations and sub combinations are intended to fall within the scope of this disclosure. In addition, certain method, event or process blocks may be omitted in some implementations. The methods and processes described herein are also not limited to any particular sequence, and the blocks or states relating thereto can be performed in other sequences. For example, described tasks or events may be performed in an order other than that specifically disclosed, or multiple may be combined in a single block or state. The example tasks or events may be performed in serial, in parallel, or in another manner. Tasks or events may be added to or removed from the disclosed examples. The example systems and components described herein may be configured differently than described. For example, elements may be added to, removed from, or rearranged compared to the disclosed examples.

While certain example embodiments are described herein, these embodiments are presented by way of example only, and do not limit the scope of the inventions disclosed herein. Thus, nothing in the foregoing description implies that any particular feature, characteristic, step, module, or block is necessary or indispensable. The novel methods and systems described herein may be embodied in a variety of other forms. Various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit and scope of the present disclosure.

Method80and other methods of this disclosure may include other steps or variations in various other embodiments. Some or all of any of method80may be performed by or embodied in hardware, and/or performed or executed by a controller, a CPU, an FPGA, a SoC, a multi-processor system on chip (MPSoC), which may include both a CPU and an FPGA, and other elements together in one integrated SoC, or other processing device or computing device processing executable instructions, in controlling other associated hardware, devices, systems, or products in executing, implementing, or embodying various subject matter of the method.

Data storage systems, devices, and methods are thus shown and described herein, in various foundational aspects and in various selected illustrative applications, architectures, techniques, and methods for optimizing the VCM PWM-linear mode transition offset to minimize PES, such as track arrival PES, for data storage, and other aspects of this disclosure. Persons skilled in the relevant fields of art will be well-equipped by this disclosure with an understanding and an informed reduction to practice of a wide panoply of further applications, architectures, techniques, and methods for optimizing the VCM PWM-linear mode transition offset to minimize PES for data storage, and other aspects of this disclosure encompassed by the present disclosure and by the claims set forth below.

As used herein, the recitation of “at least one of A, B and C” is intended to mean “either A, B, C or any combination of A, B and C.” The descriptions of the disclosed examples are provided to enable any person skilled in the relevant fields of art to understand how to make or use the subject matter of the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art based on the present disclosure, and the generic principles defined herein may be applied to other examples without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

The present disclosure and many of its attendant advantages will be understood by the foregoing description, and various changes may be made in the form, construction, and arrangement of the components without departing from the disclosed subject matter or without sacrificing all of its material advantages. The form described is merely explanatory, and the following claims encompass and include a wide range of embodiments, including a wide range of examples encompassing any such changes in the form, construction, and arrangement of the components as described herein.

While the present disclosure has been described with reference to various examples, it will be understood that these examples are illustrative and that the scope of the disclosure is not limited to them. All subject matter described herein are presented in the form of illustrative, non-limiting examples, and not as exclusive implementations, whether or not they are explicitly called out as examples as described. Many variations, modifications, and additions are possible within the scope of the examples of the disclosure. More generally, examples in accordance with the present disclosure have been described in the context of particular implementations. Functionality may be separated or combined in blocks differently in various examples of the disclosure or described with different terminology, without departing from the spirit and scope of the present disclosure and the following claims. These and other variations, modifications, additions, and improvements may fall within the scope of the disclosure as defined in the claims that follow.