Patent ID: 12218265

NOTATION AND NOMENCLATURE

Various terms are used to refer to particular system components. A particular component may be referred to commercially or otherwise by different names. Further, a particular component (or the same or similar component) may be referred to commercially or otherwise by different names. Consistent with this, nothing in the present disclosure shall be deemed to distinguish between components that differ only in name but not in function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . .” Also, the term “couple” or “couples” is intended to mean either an indirect or direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections.

The terminology used herein is for the purpose of describing particular example implementations only, and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” may be intended to include the plural forms as well, unless the context clearly indicates otherwise. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order discussed or illustrated, unless specifically identified as an order of performance. It is also to be understood that additional or alternative steps may be employed.

The terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections; however, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer, or section from another region, layer, or section. Terms such as “first,” “second,” and other numerical terms, when used herein, do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer, or section discussed below could be termed a second element, component, region, layer, or section without departing from the teachings of the example implementations. The phrase “at least one of,” when used with a list of items, means that different combinations of one or more of the listed items may be used, and only one item in the list may be needed. For example, “at least one of: A, B, and C” includes any of the following combinations: A, B, C, A and B, A and C, B and C, and A and B and C. In another example, the phrase “one or more” when used with a list of items means there may be one item or any suitable number of items exceeding one.

Spatially relative terms, such as “inner,” “outer,” “beneath,” “below,” “lower,” “above,” “up,” “upper,” “top,” “bottom,” “down,” “inside,” “outside,” “contained within,” “superimposing upon,” and the like, may be used herein. These spatially relative terms can be used for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms may also be intended to encompass different orientations of the device in use, or operation, in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the example term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein interpreted accordingly.

DETAILED DESCRIPTION

The following discussion is directed to various implementations of the present disclosure. Although one or more of these implementations may be preferred, the implementations disclosed should not be interpreted, or otherwise used, as limiting the scope of the present disclosure, including the claims. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any implementation is meant only to be exemplary of that implementation, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that implementation.

The limitations of conventional silicon photovoltaic modules manufactured using silicon wafers demonstrates the need for a less equipment-intensive, less wasteful, and less expensive manufacturing process. The ability to utilize solar cells in applications where a rigid solar module would be inapplicable is also desirable.

The present disclosure describes implementations of enabling deposition of a material (e.g., SiO2, Al2O3, SiNx, TiO2, amorphous silicon, polysilicon etc.) on the silicon particles, also referred to as particles, (either before or after the particles are deposited on a substrate) for the purpose of electrically passivating the surface. In some implementations, passivation reduces the electronic carrier recombination at the surface of the silicon particles or interface between the silicon particles and other materials. This reduction can occur chemically by reducing the number of mid-gap electronic states available to electrons, e.g., by bonding the silicon atoms at the surface to other elements like oxygen or hydrogen, or by reducing bond strain in silicon-silicon bonds. Reduction can also occur due to a field effect due to fixed charges in the passivating layer. Reduction can also occur by changing the mobility of one carrier type near the surface or interface (e.g., by diffusing dopants into the region just below this surface or interface). Reduction can also occur through a combination of these effects.

Implementations of the present disclosure may provide photovoltaic devices with a solid electrode and silicon particle absorber that is flexible (i.e., to be repeatedly flexed or operated in a flexed position without degrading the conversion efficiency of light to electricity).

According to some implementations of the disclosure, the surface area to volume ratio of the small silicon particles used herein is very high compared to silicon wafers. Increasing this ratio emphasizes the impact of recombination at the surface vs. recombination in the bulk of the absorber, as shown by solar cells fabricated on very thin wafers.

According to another implementation, deposition of a semiconductor on the surface of the silicon particles before the particles are deposited on a substrate is performed in order to form a p-n junction or electron-selective or hole-selective layer for extraction of one type of electronic carrier and blocking of the other. Deposition of a semiconductor layer, in contrast, for example, with in-diffusion of dopants, result in higher efficiencies for some implementations. Deposition of this layer before the particles are deposited on a substrate allows an expanded range of processing techniques, including cleaning or otherwise preparing the particle surface before deposition and removing temperature limitations related to the substrate (e.g., formation of a Si—Al eutectic at 577° C.).

In some implementations, a semiconductor with thickness less than 50 nanometers is deposited in order to form a p-n junction or electron-selective or hole-selective layer for extraction of one type of electronic carrier and blocking of the other. This layer could be deposited on particles before the particles are deposited onto a substrate or afterward. The thin layers described herein can be deposited faster than conventional techniques, enabling the use of techniques like atomic layer deposition that create more uniform and conformal coverage. Thinner layers can also better optimize high carrier selectivity and low contact resistance.

According to another implementation, an interlayer is inserted between the silicon particle and the electrode in order to form an ohmic contact between the silicon particle and the electrode (e.g., a metal electrode). The interlayer can include, for example, LiF or MgF and, for example, can be inserted between n-type Si and an aluminum (Al) electrode. In this implementation, the insertion of the interlayer can avoid Fermi-level pinning at the Si-Al interface. The insertion of the interlayer can also reduce electronic carrier recombination at the contact by preventing the transport of one carrier type (either electrons or holes) to the contact. The interlayer can be formed in architectures in which the substrate is used as an electrode or an electrode is deposited on the substrate before the silicon particles are deposited on the substrate. The interlayer can also be formed in architectures in which the substrate is either transparent or removed before the device is finished and an electrode is deposited on top of the particles.

The interlayers can be deposited on the silicon particles before the silicon particles are deposited onto the substrate, or the interlayers could be deposited onto the substrate or electrode before the silicon particles are deposited. If the silicon particles are deposited on a different substrate and then an electrode is deposited or placed over them, the interlayer could be deposited onto the silicon particles before the electrode. Additionally, other combinations of these approaches could also be used. In contrast with direct contact designs, the use of the interlayer, for example, one or more interlayers provided in a laminated structure, between the silicon particles and the electrode can reduce contact resistance and recombination at contacts.

Moreover, the use of an interlayer prevents the transport of majority carriers to the contact (i.e., the interlayer prevents holes from reaching the contact if the silicon particles have p-type conductivity and electrons if the silicon particles have n-type conductivity). Using implementations of the present disclosure, minority carriers can be extracted at the electrode, thereby enabling independent optimization of each contact for carrier selectivity, contact resistance, optical properties, and processing compatibility with other layers as well as more flexibility in the conductivity type of the silicon particle.

In another implementation, the device structure utilizes an aluminum or an aluminum-containing paste as one of the electrodes (and optionally also the substrate) and a heat treatment process is performed after the silicon particles are brought into contact with the aluminum. The heat treatment process can create a region in the silicon particle with a concentration of Al (which acts as a p-type dopant in Si) greater than the background doping concentration in the silicon particle. Through the creation of a high-low junction or Back Surface Field (“BSF”) as well as differential mobility for electrons and holes, this region prevents transport of electrons to the Al electrode, while allowing transport of holes creating a contact with low contact resistance and low carrier recombination. This heat treatment and doping can be used either on a bare p-type particle or on a p-type particle with a region near the surface where an n-type dopant has been diffused into the particle. In the latter case, the Al dopant concentration can exceed the concentration of the n-type dopant in the B SF region. Accordingly, some implementations enable reductions in contact resistance and carrier recombination.

In another implementation, one or more layers are deposited as elements of the photovoltaic device structure to provide an anti-reflection (AR) coating functionality. For implementations in which silicon particles are deposited on a substrate and a p-n junction (or carrier-selective contacts) are formed (either before or after deposition on the substrate), deposition of one or more layers on top of the device structure with a refractive index and thickness selected to reduce or minimize reflection from the device structure can be used to form an AR coating. In implementations in which a transparent conductor is deposited over the top of the substrate/particles/junction structure, the refractive index and thickness of this transparent conductor could be selected, so that the transparent conductor also acts as an AR coating. By using another layer within a stack of materials with a different refractive indices, the thickness of this layer can be tuned such that thin-film interference reduces or minimizes reflection from the device.

FIGS.1A-1Iillustrate a method of forming a photovoltaic device using silicon particles according to some implementations of the present disclosure. InFIG.1A, silicon particles110are acquired. The particle size could be 20-100 micrometers. Smaller sizes (down to 1 micrometer) are also possible but may utilize additional light-trapping structures (e.g., waveguide structures or nano-patterning) to provide a desired efficiency. Although the silicon particles110are illustrated as spherical, the silicon particles110can be other shapes and are represented as spheres merely for purposes of clarity. The silicon particles110may be doped n-type (with a group V element like phosphorus, etc.) or p-type (with a group III element like boron, gallium, etc.). Resistivity of this layer could be between 1 and 150 ohm-cm (e.g., between 1 and 25 ohm-cm). In some implementations, the doping concentration of boron ranges between 1e14 cm−3and 1.5e16 cm−3. In some implementations, the doping concentration of phosphorus ranges between 3e13 cm−3and 5e15 cm−3. The silicon particles110could be monocrystalline such that no grain boundaries exist within them or the particles could have crystalline domains of a similar order of magnitude to the size of the particles such that few grain boundaries exist within them. The silicon particles110could be produced through metallurgical refining of silicon or silicon oxide to a purity greater than 99.99% (more likely 99.9999-99.9999999%). The silicon particles110could also be produced through crystallization of a silicon-containing gas like silane or trichlorosilane. This process can include the Siemens process, a fluidized bed reactor process, a CVD process (as in epitaxial growth), combinations thereof, or the like. The crystal grains could be enlarged by, e.g., applying a heat treatment to the particles (or to a piece of solid silicon that is later crushed to form particles). This heat treatment could also reduce the presence of other crystal defects (e.g., dislocations) and impurities (e.g., transition metals including Fe, Cu, Ni, Co, and Cr). If impurities are going to be removed during the heat treatment, it may be necessary to have sinks for these impurities on the surface that may then be etched off. These could include, e.g., a phosphorus-rich layer, an oxygen-rich layer, or oxygen precipitates. The silicon particles110could also be produced as kerf when sawing silicon (e.g., wire sawing a silicon ingot into wafers). The silicon particles110could also be produced by crushing larger pieces of silicon (either monocrystalline silicon or polysilicon with crystal grains significantly larger than 100 μm) into a powder. These silicon particles110could also be produced by crystallization from a liquid silicon source like cyclohexasilane or molten elemental silicon. The silicon particles110could also be produced by anodic etching of larger pieces of silicon to create a porous layer and mechanical removal of this porous layer. Silicon particles110could also be produced by crushing a larger block or blocks of solid silicon using a ball mill. In some implementations where the silicon particles110are grown from the gas phase, the particles could be grown such that there is an inner core that is lightly doped and an outer shell that is doped more heavily and with opposite conductivity. This could be accomplished by changing the composition of the gases during crystallization. In some implementations, silicon particles110could be grown as a thin wafer (10-100 microns thick) with crystal grain sizes similar or larger than the wafer thickness. In other implementations, the silicon particles110could be grown as a thin film (similar thickness and crystal grain size to wafer) on a non-silicon substrate (e.g. glass or quartz). In some implementations, this silicon wafer or film could be mounted onto a flexible substrate (e.g., stainless steel or aluminum sheet/foil) and run between rollers to crush the wafer or film, obtaining particles of appropriate size and shape. These rollers could be flat or have teeth. In some implementations, this crushing process could take place on a bare wafer/film or a silicon wafer/film that has had additional processing done (e.g., dopant diffusion, deposition of dielectric passivating or carrier-selective layers, deposition of metals). In the case that crushing takes place after additional processing on the wafer/film, the crushing process could be done in such a way that the crushed pieces remain oriented relative to the carrier. In some implementations, the method can include etching of the surface of the silicon particles in order to create surface texture that minimizes reflection. This etching could be wet etching with either acidic (combination of hydrofluoric and nitric acid, and in some implementations with additional buffering agents like water or acetic acid) or alkaline (e.g., KOH or NaOH) etching solution that produces surface texture on the order of 1-5 microns (3-5 microns for example) with texture feature aspect ratios close to one in some implementations. It could also be a reactive ion etch (e.g., SF6/O2process gases), laser ablation process (with or without process gases present), metal-catalyzed wet chemical etch, or plasma immersion ion implantation process that produces surface texture on the order of tens to hundreds of nanometers with texture feature aspect ratios of 2-10. The etching process can be performed prior to embedding of the silicon particles110, as well as after embedding, for example, after the particles are partially exposed after the step illustrated inFIG.1Eand at other appropriate steps in the process when the bare particle is partially or fully exposed.

InFIG.1B, a dopant is diffused to create a junction (i.e., layer112). In some implementations, layer112is a highly conductive doped silicon layer near the surface of particle10with opposite doping/conductivity to the particle10. The thickness of layer112could be 10 nm to 10 μm thick (e.g., 100 nm to 1 μm). The peak doping of layer112could be 1e17 to 1e20 cm−3(1e18 to 2e19 cm−3for example). The dopant source for layer112could be either a gas source (e.g., POCl3for phosphorus or BBr3for boron), a liquid source, or a plasma source. This dopant source could be deposited on the surface of the particles10by CVD in a tube furnace at or below atmospheric pressure, by plasma-enhanced CVD, by immersing the particles in a liquid, or by coating a liquid onto the particles. These sources typically create a silicate glass on the surface of the silicon particles110, which could either be removed by hydrofluoric acid (either in aqueous solution or in vapor form) or left in place to act as a passivating layer on the surface of the silicon particles110. During the in-diffusion process, metals and other impurities can be gettered to layer112to minimize their impact on device performance. After this process, the near surface region or the entire heavily-doped region could be removed (e.g., by chemical etching in acidic or alkaline solution). If layer112is thick (greater than 1 μm), the near-surface region could be removed to make the dopant profile more uniform and less heavily doped to reduce recombination in this layer while still providing carrier selectivity.

InFIG.1C, a passivating dielectric layer114is deposited onto the surface of the silicon particles110. Passivating dielectric layer114could be an oxide (e.g., stoichiometric or non-stoichiometric silicon oxide or a metal oxide like aluminum oxide or titanium oxide), a nitride (like silicon nitride), a fluoride like LiF or MgF, amorphous silicon, or an organic compound like PEDOT-pss. In some implementations the passivating dielectric layer114may include multiple layers (e.g., intrinsic, doped a-Si, SiO2, and doped polycrystalline silicon). In some implementations, any of these layers could be processed (either during deposition or afterward) to contain excess hydrogen in order to tie up unsatisfied valence electrons at the silicon surface. These materials could be deposited by atomic layer deposition (at or below atmospheric pressure), by CVD (at or below atmospheric pressure), by plasma-enhanced CVD, or by immersion or coating from a liquid source. The thickness of this layer could be 1-100 nanometers (e.g., 10-20 nanometers). In some implementations, passivating dielectric layer114is designed to have a large amount of “fixed charge” to provide field effect as well as chemical passivation of the silicon surface by creating a depletion, accumulation, or inversion layer (depending on the conductivity type of the particle and layer112, and the polarity of the fixed charge in passivating dielectric layer114).

In some implementations, a transparent conductor layer115is deposited onto the surface of the silicon particles110. In some implementations, the transparent conductor layer116could be an oxide such as tin oxide or zinc oxide. The transparent conductor layer115could be doped or alloyed with another element to increase its conductivity (e.g., with indium in the case of tin oxide or with aluminum in the case of zinc oxide). The transparent conductor layer115could be a low-dimensional carbon layer like graphene or a carbon nanotube mesh. The transparent conductor layer115could be a conductive polymer like PEDOT. It could be a diffuse metal mesh made of nanoparticles or nanowires (e.g., silver or copper). The transparent conductor layer115could be deposited by CVD (including using metal-organic precursors), laser or beam deposition, physical vapor deposition, spray pyrolysis, or immersion or coating from a liquid source. The thickness of the transparent conductor layer115could be 10-300 nm (e.g., 60-200 nm). Heavy doping of the transparent conductor layer115could provide additional field effect passivation of the surface of the silicon particle110and of layer112.

InFIG.1D, the silicon particles110are embedded on a carrier116. In some implementations, the carrier116could be a polymer film like PET coated with a soft polymer that could be curable with application of heat or radiation. Either the entire film or the soft polymer coating could be dissolved easily in a solvent that does not react with any of the active layers of the solar cell. The film and/or the coating could be impervious to exposure to materials that dissolve the active layers, including alkaline solutions like potassium hydroxide or sodium hydroxide or acidic solutions like nitric acid, hydrofluoric acid, acetic acid, hydrochloric acid or combinations thereof. The embedding process could be done by packing, shaking, depositing, or any other method of placing the particles onto the surface of the substrate and then running the carrier between two rollers (the particles10could also be deposited at the pinch point of the rollers with the foil making a right-angle turn just before the pinch point), or the like. In some implementations, instead of using two rollers, blade coating the particles or powder coating (i.e., aerosolize particles and direct the particle-laden fluid at the substrate) can be used. The process could leave from 10% to 90% of the particles exposed (e.g., 80-90%).

InFIG.1E, layer112and passivating dielectric layer114are partially removed. Layer112and passivating dielectric layer114could be removed mechanically (e.g., with abrasion by a fine grit material like silicon carbide or diamond either in a slurry solution or embedded on a film), optically (e.g., by laser ablation), chemically (e.g., by selective etching, including wet etching, dry etching, or reactive ion etching), or by ion bombardment. In some implementations where layer112and passivating dielectric layer114are removed chemically, the chemicals used could be selective such that the chemicals etch these layers much faster than the chemicals etch the underlying silicon particles110.

InFIG.1F, a passivating dielectric layer118is deposited. This process may be similar to the step illustrated inFIG.1C. The passivating dielectric layer118would be optimized for the doping concentration and type of the silicon particle rather than the heavily doped region. The passivating dielectric layer118would coat not only the silicon particles110but the spaces between the silicon particles110on the carrier116as well. In some implementations, an insulating layer (not shown) is optionally deposited. In some implementations, this insulating layer could be similar to passivating dielectric layer114or passivating dielectric layer118, and in others this insulating layer could be a polymer or a rubber. In some implementations where this insulating layer is identical to passivating dielectric layer118, then this insulating layer could be deposited in a manner similar to the one shown inFIG.1G. In some implementations where this insulating layer is deposited by coating, the coating process could result in greater thickness between the silicon particles110than on top of the silicon particles110(e.g., 1-100 microns between the silicon particles110and 10 nm to 1 micron on top of the silicon particles110). In some implementations, this insulating layer could be impervious to one or more of the solvents that dissolve the carrier116or a coating of the carrier116but do not react with the active layers. In some implementations, this insulating layer could completely cover the silicon particles110. In one implementation, this insulating layer could be negative photoresist deposited by a coating process such that the thickness between the silicon particles110is greater than the thickness on top of the silicon particles110(e.g., 1 micron between and 10 nm on top). The polymer does not need to be designed or used for photolithography as long as a negative resist is made in soluble in solvent/etching/solution/developer by light exposure and positive resist is made insoluble. The photoresist could then be exposed to light such that the thickness of resist exposed corresponds to the thickness on top of the silicon particle110and some of the resist between the silicon particles110remained unexposed. In another implementation, this insulating layer could be a positive photoresist illuminated either from both sides or from the substrate side (with a wavelength of light that has high transmission through the substrate but low transmission through the silicon particle110) such that areas between the silicon particles110receive a higher photon dose than areas above the silicon particle110.

InFIG.1F, a portion of passivating dielectric layer118is removed to expose the surface of the silicon particles110. The amount (e.g., surface area) of the silicon particle110exposed after this removal could be 5%-20%. If a photoresist is used as inFIG.1F, this process could be a solvent wash designed for photoresist removal. This process could result in pinholes rather than complete removal of the passivating dielectric layer118above the silicon particle110. If this was an optical process, the process could use interaction between two photons of a wavelength reflected more efficiently by the silicon particle110than the underlying substrate such that absorption by two photons (a primary incident and a reflected photon) is more likely above the particle than between silicon particles110.

InFIG.1G, a metal layer120is deposited. This could be a single metal (e.g., Al, Ag, or Cu) or a metal stack (e.g., Ti/Ni/Ag or Ti/Pd/Ag) or an alloy. The metal layer120could be contained in a paste or solution and printed onto the surface of the silicon particle110. In some implementations, the paste/solution could be an alloy (e.g., Ga, In, and Ti or Ga, In, and Sn) that is liquid at or near room temperature. In some implementations, the metal layer120could be deposited by a PVD process (e.g., evaporation or sputtering). In some implementations, this metal layer120could be a free-standing foil or sheet. This sheet could be flexible. With some of these processes, a high-temperature curing step could be used to create a “back-surface field,” achieve better adhesion or interface properties, improve the bulk metal properties (e.g., sinter nanoparticles). Heating of this type could also be achieved locally (e.g., by using a laser). Photonic curing could also be used. Curing could also remove non-metallic (e.g., organic) elements from a paste or ink. In some implementations where an alloy is used, some of the elements in this alloy could be dopants in Si (e.g., Ga or Al) and in-diffuse into the silicon particles110. In some implementations where an alloy is used, the alloy could be designed such that the electron transport layer (or hole transport layer) or components of the electron transport layer (or hole transport layer) are soluble in the alloy or form a eutectic with the alloy such that during the curing step, the electron transport layer (or hole transport layer) dissolves where it is in contact with the metal alloy. In some implementations, an interlayer like LiF, MgF, MoOx, or NiOxcould be deposited between the silicon particle110and the metal layer120to reduce the contact resistance between the silicon particle110and the metal layer120. The thickness of this interlayer could be 0.5-15 nm (e.g., 1-1.5 nanometers).

InFIG.1G, the carrier116is removed. In some implementations, the carrier116is dissolved to effectuate the removal process. The carrier116could be dissolved in a solvent that does not react with the active layers of the solar cell. InFIG.1H, a portion of layer114is removed, completely or in part, to expose the doped surface of the silicon particle110.

InFIG.1I, a transparent conductor layer122is deposited on the side of the silicon particle110where the carrier116was previously. In some implementations, the transparent conductor layer122could be a material similar to transparent conductor layer115. In some implementations, the transparent conductor layer122could be deposited in a similar manner to transparent conductor layer115. In some implementations, the transparent conductor layer122could be a diffuse conductor like silver nanowires. In some implementations, the transparent conductor layer122could be a combination of these conductors. In some implementations, the transparent conductor layer122could be deposited through a coating process like spin-coating, blade-coating, or slot-die coating or a non-coating process suitable for depositing diffuse conductors. According to some implementations, the transparent conductor layer122could be deposited onto the particles now embedded into a metal substrate. In some implementations, the transparent conductor layer122could instead or in addition, be deposited onto a laminate film that is subsequently laminated onto the substrate and particles. InFIG.1I, the cell is laminated (i.e., layer124). The substrate could be laminated with a barrier film like EVA or the like. The laminate could be attached to the substrate or it could surround the substrate. The laminate could have conductive wires embedded into it to enable efficient carrier extraction from the silicon particles110through the transparent conductor layer122.

FIG.2is a flow chart diagram illustrating a method200of forming a photovoltaic device using silicon particles according to some implementations of the present disclosure. In Step201, silicon particles are acquired. These particles could have similar properties to those described in relation toFIG.1. In some implementations, the particles could be doped p-type (with a group III element like boron, gallium, etc.).

In Step202, a dopant species is diffused into the particle (Layer 1). This is similar to Step102inFIG.1. In some implementations, an n-type dopant (e.g., a group V element like phosphorus, etc.) could be used. In some implementations, this step could be omitted.

In Step203, particles are embedded onto a metal foil. In some implementations, a hole transport layer is deposited on the particle before embedding on metal foil. In this case, particles could be either p-type or n-type (with electron transport layer deposited instead of a hole transport layer). In some implementations, the metal foil could be coated with a metal ink or paste containing the same metal or a different metal. In some implementations, the paste (and the foil) could be aluminum which also acts as a p-type dopant in silicon. In some implementations, this paste/solution could be an alloy (e.g., Ga, In, and Ti or Ga, In, and Sn) that is liquid at or near room temperature. The particles could be embedded on the metal foil by packing, shaking, depositing, or any other method of placing the particles onto the surface of the foil and then running the foil between two rollers (the particles could also be deposited at the pinch point of the rollers with the foil making a right-angle turn just before the pinch point) or the like.

In Step204, the particles and metal are fired to in-diffuse Aluminum (Al). The firing could take place in a belt furnace or optical furnace with a drying step (below 400° C.) to dry the ink/paste, and a step between 400 and 1000° C. (e.g., in two to three phases with one phase between 500 and 600° C., another between 600 and 1000° C., and potentially a third between 500 and 600° C. again). The total duration of the second step could be between 10 seconds and 300 seconds (e.g., 50-100 seconds with the time spent above 600° C. limited to less than 10 seconds). In some implementations, the firing could instead be performed by application of a laser. The firing would both form an ohmic contact between the silicon particles and the metal paste/foil and in-diffuse Al. The in-diffusion of Al would lower the mobility of electrons relative to holes and form a high-low junction at the back of the cell, creating a hole-selective contact between the silicon particles and metal paste/foil. In order to accomplish this second goal, the concentration of Al would have to exceed the concentration of the n-type dopant in Layer 1. In some implementations where an alloy is used, some of the elements in this alloy could be dopants in Si (e.g., Ga or Al) and in-diffuse into silicon particles. In some implementations where an alloy is used, the alloy could be designed such that the electron transport layer (or hole transport layer) or components of the electron transport layer (or hole transport layer) are soluble in the alloy or form a eutectic with the alloy such that during the curing step, the electron transport layer (or hole transport layer) dissolves where it is in contact with the metal alloy.

In Step205, a passivating dielectric (Layer 2) is deposited on the exposed surface of the particles. This material is similar to Layer 2 inFIG.1. Deposition techniques are also similar to Layer 2 inFIG.1.

In Step206, an insulating layer (Layer 3) is deposited. This layer is similar to Layer 5 inFIG.1. In some implementations, this step could be combined with Step205if the insulating layer also provides good surface passivation. In step206, some of Layer 2 and some of Layer 3 is removed to reveal the particle. This step is similar to Step106inFIG.1. Layer 2 does not need to be removed if it is not a barrier to electron transport (e.g., ultrathin SiO2that can be tunneled through). This is shown inFIG.2. Layer 3 does not need to be removed if it can be deposited so that it does not cover part of the particle.

In Step207, an electron transport layer (Layer 4) is deposited. Layer 4 could have excellent band alignment between its conduction band and the conduction band of the silicon particle. This alignment could be optimized when the conduction band of Layer 4 is slightly (about 10-30 meV) higher than the conduction band of the silicon particle. This layer could have a wider bandgap than the silicon particle to provide an energetic barrier to hole transport. In some implementations, this layer could have a higher electron conductivity than hole conductivity. In some implementations, this layer could be a metal oxide like TiO2or n-doped a-Si. This layer could be a stack of materials with a highly resistive or insulating material like undoped intrinsic a-Si or SiO2under a more conductive material like those listed above. This layer could be deposited by atomic layer deposition (at or below atmospheric pressure), chemical vapor deposition (at or below atmospheric pressure), physical vapor deposition, spray pyrolysis, sol-gel, or coating from a liquid source. This layer could be 0.5-20 nm thick (e.g., 1-3 nm).

In Step207, a transparent conductor (Layer 5) is also deposited. This step is similar to Step109inFIG.1. In Step207, the cell is also laminated. This step is similar to Step109inFIG.1.

FIG.3is a flow chart diagram illustrating a method300of forming a photovoltaic device using silicon particles according to some implementations of the present disclosure. In Step301, silicon particles are acquired. This step may be similar to Step201inFIG.2. In Step302, a dopant species is diffused into the particle (Layer 1). This step may be similar to Step202inFIG.2. In some implementations, this step may be omitted. In Step303, particles are embedded onto a metal foil. This step may be similar to Step203inFIG.2. In Step304, the particles and metal are fired to in-diffuse Al. This step may be similar to Step204inFIG.2. In Step305, a passivating dielectric (Layer 2) is deposited on the exposed surface of the particles. This step may be similar to Step205inFIG.2. In Step306, an insulating layer (Layer 3) is deposited. This step may be similar to Step206inFIG.2. In Step307, Layer 2 and Layer 3 are partially removed to reveal the surface of the particle. The removal of Layers 2 and 3 may be performed in a similar manner as Step106inFIG.1. In Step308, a selective carrier transport layer (Layer 4) is deposited. This step may be similar to Step207inFIG.2. In Step308a transparent conductor (Layer 5) is deposited. This step may be similar to Step207inFIG.2. In Step308, the cell is laminated. This step may be similar to Step207inFIG.2.

FIG.4is a flow chart diagram illustrating a method400of forming a photovoltaic device using silicon particles according to some implementations of the present disclosure. In Step401, silicon particles are acquired. This step may be similar to Step201inFIG.2. In Step402, particles are embedded onto a metal foil. This step may be similar to Step203inFIG.2. In Step403, the particles and metal are fired to in-diffuse Al. This step may be similar to Step204inFIG.2. In Step404, a passivating dielectric (Layer 1) is deposited on the exposed surface of the particles. This step may be similar to Step205inFIG.2. In Step405, an insulating layer (Layer 2) is deposited. This step may be similar to Step206inFIG.2. In Step406, Layer 1 and Layer 2 are partially removed to reveal the surface of the particle. The removal of Layers 1 and 2 may be performed in a similar manner as Step106inFIG.1. In Step407, a selective carrier transport layer (Layer 3) is deposited. This step may be similar to Step207inFIG.2. In Step407, a transparent conductor (Layer 4) is deposited. This step may be similar to Step207inFIG.2. In Step407, the cell is laminated. This step may be similar to Step207inFIG.2.

FIG.5is a flow chart diagram illustrating a method500of forming a photovoltaic device using silicon particles according to some implementations of the present disclosure. In Step501, silicon particles are acquired. This step may be similar to Step201inFIG.2. In Step502, particles are embedded onto a metal foil. This step may be similar to Step203inFIG.2. In Step503, the particles and metal are fired to in-diffuse Al. This step may similar to Step204inFIG.2. In Step504, a passivating dielectric (Layer 1) is deposited. In this implementation, the passivating dielectric also provides insulating properties allowing an insulating layer to be optional (Insulating layer is foregone inFIG.5.). This process of deposition in this step may be similar to that of Step106inFIG.1. In Step505, Layer 1 is partially removed to reveal the surface of the particle. The removal of Layer 1 may be performed in a similar manner as Step106inFIG.1. In Step506, a selective carrier transport layer (Layer 2) is deposited. This step may be similar to Step207inFIG.2. In Step506, a transparent conductor (Layer 3) is deposited. This step may be similar to Step207inFIG.2. In Step506, the cell is laminated. This step may be similar to Step207inFIG.2.

FIG.6is a flow chart diagram illustrating a method600of forming a photovoltaic device using silicon particles according to some implementations of the present disclosure. In Step601, silicon particles are acquired. This step may similar to Step101inFIG.1. In Step602, a dopant is diffused to create a junction (Layer 1). This step may be similar to Step102inFIG.1. In Step603, a selective carrier transport layer (Layer 2) is deposited. Layer 2 may be similar to Layer 4 inFIG.2. Layer 2 may be deposited similarly to Layer 4 inFIG.2. Because it is being deposited on particles, Layer 2 could also be deposited by an ALD or CVD-type process in a fluidized bed reactor. In some implementations, this layer may be deposited on top of an ultrathin (e.g., less than 1.5 nm) insulator like SiO2that provides excellent surface passivation and has a thin enough electronic barrier to carrier transport to allow efficient transport by quantum tunneling or through pinholes. In some implementations, this layer could instead be deposited on top of an undoped intrinsic semiconductor like a-Si for the same reason. This layer could be thin enough (e.g., less than 10 nm) that electronic carrier transport occurs through a combination of tunneling, hopping, and electronic drift. In Step603, a transparent conductor (Layer 3) is deposited. This step may be similar to Step103inFIG.1. In Step604, particles are embedded into a substrate. In some implementations, the substrate could be a polymer film like PET or silicone coated with a soft polymer that could be curable with application of heat or radiation. In some implementations, the substrate and the coating could be flexible. In some implementations, the substrate and the coating could be highly transparent to solar radiation. In some implementations, the film and/or the coating could be impervious to exposure to materials that dissolve the active layers, including alkaline solutions like potassium hydroxide or sodium hydroxide or acidic solutions like nitric acid, hydrofluoric acid, acetic acid, hydrochloric acid or combinations thereof. The embedding process could be performed as described in other implementations herein. The process could leave from 10% to 90% of the particles exposed (e.g., 40-60%). In Step605, part of Layers 1, 2 and 3 are removed to reveal the particles. This process may be similar to Step105inFIG.1. In Step606, a passivating dielectric (Layer 4) is deposited. This process may be similar to Step205inFIG.2. In Step606, an insulating layer (Layer 5) is deposited. This process is similar to Step206inFIG.2. In Step607, some of Layer 4 and some of Layer 5 are removed to reveal some of the particle. This process may be similar to Step307inFIG.3. In Step608, a metal layer (Layer 6) is deposited and then fired. This process may be similar to Step107inFIG.1.

FIG.7is a flow chart diagram illustrating a method700of forming a photovoltaic device using silicon particles according to some implementations of the present disclosure. In Step701, silicon particles are acquired. This step may be similar to Step101inFIG.1. In Step702, an electron transport layer or a hole transport layer (Layer 1) is deposited. This process may be similar to Step603inFIG.6. If Layer 1 is a hole transport layer rather than an electron transport layer, Layer 1 could be a metal oxide like MoOxor multiple layers like intrinsic and doped amorphous silicon or SiO2and doped polysilicon. In Step702, a transparent conductor (Layer 2) is deposited. This process may be similar to Step103inFIG.1. In Step703, particles are embedded onto a substrate. This process can be similar to Step604inFIG.6. In some implementations, this process can vary from other embedding processes because the particles are embedded in a transparent substrate that is part of the finished cell/module. In Step704, part of Layer 1 and part of Layer 2 is removed to reveal the particles. This process is similar to Step106inFIG.1. In Step705, a passivating dielectric (Layer 3) is deposited. This process is similar to Step205inFIG.2. In Step705, an insulating layer (Layer 4) is deposited. This process may be similar to Step206inFIG.2. In Step706, some of Layer 3 and some of Layer 4 is removed to reveal some of the particle. This process is similar to Step207inFIG.2. In Step707, a hole transport layer, electron transport layer, or tunnel interlayer (Layer 5) is deposited. If Layer 1 is conductive to electrons and blocks holes, Layer 5 is conductive to holes and blocks electrons and vice versa. In other respects, this process may be similar to Step702. In some implementations, instead of being carrier selective/blocking, this layer could be an interlayer like LiF, MgF, MoOx, or NiOxthat reduces the contact resistance between the silicon particle and a metal. In Step708, a metal layer (Layer 6) is deposited. This process may be similar to Step608inFIG.6.

FIGS.8A-8Hillustrate a method of fabricating a photovoltaic device using counter-doping according to some implementations of the present disclosure. InFIG.8A, silicon particles810are acquired. InFIG.8A, a tunnel oxide layer812is deposited. The tunnel oxide layer812could provide excellent chemical surface passivation for the silicon particle810. The tunnel oxide layer812could be one to four nanometers thick. In some implementations, the tunnel oxide layer812could be deposited by submersion of the particles in a heated nitric acid bath (T about 70° C.) or by surface treatment with ozone. In other implementations, other processes (e.g., CVD, ALD, etc.) can be utilized. InFIG.8C, a degenerately doped silicon layer814is deposited. This layer could be deposited by chemical vapor deposition. Because it is being deposited on particles, this layer could be deposited in a fluidized bed reactor. The degenerately doped silicon layer814could be 5-200 nm thick (e.g., 50-100 nm). The degenerately doped silicon layer814could be annealed between 600° C. and 1000° C. (e.g., between 800 and 900° C.). The annealing process could in-diffuse dopants through the tunnel oxide layer812into the silicon particles810to help passivate the surface of the silicon particles810. The annealing process could also change the crystal structure the degenerately doped silicon layer814, e.g., forming crystal grains in a previously amorphous layer. The annealing process could also create pinholes in the tunnel oxide layer812to enable more efficient carrier transport/reduce contact resistance. InFIG.8D, the silicon particles810are embedded on a metal foil layer816. This process could leave 1-90% of the particle exposed (e.g., 10-20%). InFIG.8E, the tunnel oxide layer812and the degenerately doped silicon layer814are partially removed exposing a portion of the silicon particle810. The tunnel oxide layer812and the degenerately doped silicon layer814could be removed mechanically (e.g., with abrasion by a fine grit material like silicon carbide or diamond either in a slurry solution or embedded on a film), optically (e.g., by laser ablation), chemically (e.g. by selective etching, including wet etching, dry etching, or reactive ion etching), or by ion bombardment. If the tunnel oxide layer812and the degenerately doped silicon layer814are removed chemically, the chemicals used could be selective such that the chemicals etch the tunnel oxide layer812and the degenerately doped silicon layer814much faster than the chemicals etch the underlying silicon particles810. A selective chemical process could proceed in two steps where one step is selective for silicon, removing the degenerately doped silicon layer814but not the tunnel oxide layer812and the other is selective for oxide (e.g., HF), removing the tunnel oxide layer812but not etching the underlying silicon particle. This process could also remove part of the degenerately doped silicon layer814but not the tunnel oxide layer812. InFIG.8F, a passivating dielectric layer818is deposited. InFIG.8F, some of passivating dielectric layer818is removed to reveal part of the silicon particle810. In some implementations, the passivating dielectric layer818is deposited before the tunnel oxide layer812and the degenerately doped silicon layer814are partially removed. InFIG.8G, a dopant layer820is diffused into the silicon particle810. This process could be a chemical vapor deposition (including with plasma enhancement), ion implantation, annealing after coating with a liquid dopant source. This dopant can be the opposite type from that in degenerately doped silicon layer814. In some implementations, the dopant layer820could also be an interlayer of intrinsic undoped a-Si under heavily doped a-Si or an interlayer of heavily doped silicon on an interlayer of SiO2. In the case of heavily-doped silicon on top of SiO2, the SiO2layer could be the tunnel oxide layer812if the tunnel oxide layer812was not removed as described above. InFIG.8G, a transparent conductor layer822is deposited. InFIG.8H, the cell is laminated (i.e. layer824).

FIGS.9A-9Hillustrate a method of fabricating a photovoltaic device using silicon particles according to some implementations of the present disclosure. InFIG.9A, silicon particles910are acquired. InFIG.9B, a tunnel oxide layer912is deposited. InFIG.9C, a degenerately doped silicon layer914is deposited. InFIG.9D, the silicon particles910are embedded on a metal foil layer916. This process could leave 1-90% of the particle exposed (e.g., 10-20%). InFIG.9E, the tunnel oxide layer912and the degenerately doped silicon layer914are partially removed exposing a portion of the silicon particle910. InFIG.9F, a passivating dielectric layer918is deposited. If the tunnel oxide layer912is not removed, the passivating dielectric layer918could be insulating but not passivating. InFIG.9F, some of the passivating dielectric layer918is removed to reveal part of silicon particle. InFIG.9G, an electron transport layer or a hole transport layer or a tunneling interlayer is deposited on the exposed silicon particle (i.e., layer920). If the degenerately doped silicon layer914is doped n-type, layer920is conductive to holes and blocks electrons. If the degenerately doped silicon layer914is doped p-type, layer920is conductive to electrons and blocks holes. In some implementations, instead of being carrier selective/blocking, the layer920could be interlayer like LiF, MgF, MoOx, or NiOxthat reduces the contact resistance between the silicon particle910and a transparent conductor. InFIG.9G, a transparent conductor layer922is deposited. InFIG.9H, the cell is laminated (i.e., layer924).

FIGS.10A-10Hillustrate a method of fabricating a photovoltaic device using silicon particles according to some implementations of the present disclosure. InFIG.10A, silicon particles1010are acquired. InFIG.10B, a tunnel oxide layer1012is deposited. InFIG.10C, a degenerately doped silicon layer1014is deposited. InFIG.10D, the silicon particles1010are embedded on a metal foil layer1016. This process could leave 1-90% of the particle exposed (for example 10-20%). InFIG.10E, a passivating dielectric layer1018is deposited and then a portion of the passivating dielectric layer1018is removed. InFIG.10F, the degenerately doped silicon layer1014is partially removed exposing a portion of the silicon particle1010. InFIG.10G, an electron transport layer or a hole transport layer or a tunneling interlayer is deposited (i.e., layer1020). If the degenerately doped silicon layer1014is doped n-type, layer1020is conductive to holes and blocks electrons. If the degenerately doped silicon layer1014is doped p-type, layer1020is conductive to electrons and blocks holes. In some implementations, instead of being carrier selective/blocking, layer1020could be interlayer like LiF, MgF, MoOx, or NiOx that reduces the contact resistance between the silicon particle and a transparent conductor. InFIG.10G, a transparent conductor layer1022is also deposited. InFIG.10H, the cell is laminated (i.e., layer1024).

FIGS.11A-11Gillustrate a method of fabricating a photovoltaic device using silicon particles according to some implementations of the present disclosure. InFIG.11A, silicon particles1110are acquired. InFIG.11B, an interlayer layer1112is deposited. The interlayer layer1112could be a material like LiF or MgF that unpins the Fermi level (i.e., reduces band bending in the silicon) at a silicon-metal interface or a material like MoOx or NiOx that reduces the contact resistance between the silicon particle and a metal. The interlayer layer1112could be 0.5-20 nm thick (e.g., 1-5 nm thick). The interlayer layer1112could be deposited by atomic layer deposition (at or below atmospheric pressure), chemical vapor deposition (at or below atmospheric pressure), physical vapor deposition, spray pyrolysis, sol-gel, or coating from a liquid source. The interlayer layer1112could be deposited on top of an ultrathin (e.g., less than 1.5 nm) insulator like SiO2that provides excellent surface passivation but whose electronic barrier to carrier transport is thin enough to allow efficient transport by quantum tunneling. The interlayer layer1112could instead be deposited on top of an undoped intrinsic semiconductor like a-Si for the same reason. The interlayer layer1112could be thin enough (e.g., less than 10 nm) that electronic carrier transport occurs through a combination of tunneling, hopping, and electronic drift. InFIG.11C, the silicon particles1110are embedded on a metal foil layer1114. InFIG.11D, the interlayer layer1112is partially removed to reveal part of the silicon particle1110. InFIG.11E, a passivating dielectric layer1116is deposited. If the interlayer layer1112is deposited on top of another layer, and this first layer is not removed, the passivating dielectric layer1116could be insulating but not passivating. InFIG.11E, some the passivating dielectric layer1116is removed to reveal part of the silicon particle1110. InFIG.11F, an electron transport layer or a hole transport layer or a tunnel interlayer is deposited on the exposed silicon particle (i.e., layer1118). InFIG.11F, a transparent conductor layer1120is deposited. InFIG.11G, the cell is laminated (i.e., layer1122).

FIGS.12A-12Hillustrate a method of fabricating a photovoltaic device using silicon particles according to some implementations of the present disclosure. InFIG.12A, silicon particles1210are acquired. InFIG.12B, a thin passivating dielectric layer1212is deposited (Layer 1). In other implementations, the thin passivating dielectric layer1212could be an undoped intrinsic semiconductor like a-Si for the same reason. The thin passivating dielectric layer1212be thin enough (e.g., less than 10 nm) that electronic carrier transport occurs through a combination of tunneling, hopping, and electronic drift. InFIG.12C, an interlayer layer1214is deposited. InFIG.12D, the silicon particles1210are embedded on a metal foil layer1216. InFIG.12E, the interlayer layer1214is partially removed. InFIG.12F, an insulator layer1218is deposited. InFIG.12F, some of the insulator layer1218is removed to reveal part of the silicon particle1210. InFIG.12G, an electron transport layer or a hole transport layer or a tunnel interlayer is deposited on the exposed silicon particle (i.e., layer1220). InFIG.12G, a transparent conductor layer1222is deposited. InFIG.12H, the cell is laminated (i.e., layer1224).

FIG.13Ais a sectional view of an example of a photovoltaic device1302. The photovoltaic device1302illustrated inFIG.13Aincludes a plurality of silicon particles1304(e.g., doped silicon particles), a coating layer1306, a substrate layer1308(e.g., a metal layer), an insulator layer1310(e.g., an oxide layer), and a selective carrier transport layer1312. The photovoltaic device1302may include fewer, additional, or different components in different configurations than the photovoltaic device1302illustrated inFIG.13A. For example, in some implementations, the photovoltaic device1302may include more than two silicon particles1304. Further, in some implementations, the photovoltaic device1302may further include a transparent conductor layer1314that is placed on the selective carrier transport layer1312, as illustrated inFIG.13B. The transparent conductor layer1314provides, e.g., lateral charge transport.

In some implementations, the coating layer1306is a single layer, as illustrated inFIGS.13A and13B. In other implementations, the coating layer1306may include more than a single layer. For example, the photovoltaic device1402illustrated inFIG.14includes a coating layer1306with two layers (i.e., layers1404and1406). In some implementations, the coating layer1306includes amorphous silicon. Alternatively, or in addition, the coating layer1306may include an oxide layer and a polysilicon layer. Alternatively, or in addition, the coating layer1306may include any coating previously described herein.

The coating layer1306and the selective carrier transport layer1312are designed to facilitate the flow of opposite polarity charge carriers. For example, in some implementations, the coating layer1306is highly-conductive for negative charge carriers and highly-resistive for positive charge carriers. Further, the selective carrier transport layer1312may be highly-conductive for the positive charge carriers and highly-resistive for the negative charge carriers. In other implementations, the coating layer1306is highly-conductive for positive charge carriers and highly-resistive for negative charge carriers. Further, the selective carrier transport layer1312may be highly-conductive for the negative charge carriers and highly-resistive for the positive charge carriers.

FIG.15is a flow diagram of an example of a method1500for fabricating a photovoltaic device using silicon particles. For simplicity of explanation, method1500is depicted and described as a series of operations. However, operations in accordance with method1500can occur in various orders and/or concurrently, and/or with other operations not presented and described herein. For example, the operations depicted in method1500may occur in combination with any other operation of any other method disclosed herein. Furthermore, not all illustrated operations may be required to implement method1500in accordance with the disclosed subject matter. In addition, those skilled in the art will understand and appreciate that method1500could alternatively be represented via a state diagram or event diagram as a series of interrelated states.

At block1502, a coating layer is applied to surround each of a plurality of silicon particles. For example, the coating layer1306is applied around the silicon particles1304, as illustrated inFIG.16A. At block1504, the plurality of silicon particles are implanted into a substrate layer such that an exposed portion of each of the plurality of silicon particles extends away from a surface of the substrate layer. For example, the plurality of silicon particles1304are implanted into the substrate layer1308such that an exposed portion of each of the plurality of silicon particles1304extends away from a surface1602of the substrate layer1308, as illustrated inFIG.16B. At block1506, a portion of the coating layer is removed. This portion of the coating layer1306is positioned around the exposed portion of each of the plurality of silicon particles1304, as illustrated inFIG.16C. At block1508, an insulator layer is placed on the surface of the substrate layer. For example, the insulator layer1310is placed on the surface1602of the substrate layer1308, as illustrated inFIG.16D. At block1510, a selective carrier transport layer is placed on the exposed portion of each of the plurality of silicon particles. For example, the selective carrier transport layer1312is placed on the exposed portion of each of the plurality of silicon particles1304, as illustrated inFIG.16E. After block1510, other layers may be placed on the selective carrier transport layer1312. For example, a transparent conductor layer1314may be placed on the selective carrier transport layer1312, as illustrated inFIG.13B. Alternatively, or in addition, a laminate layer (not shown) may be placed over the transparent conductor layer1314or over the selective carrier transport layer1312.

FIG.17is a flow diagram of an example of a method1700for fabricating a photovoltaic device using silicon particles. At block1702, a coating layer is applied to surround each of a plurality of silicon particles. For example, the coating layer1306is applied around the silicon particles1304, as illustrated inFIG.16A. At block1704, the plurality of silicon particles are implanted into a substrate layer such that an exposed portion of each of the plurality of silicon particles extends away from a surface of the substrate layer. For example, the plurality of silicon particles1304are implanted into the substrate layer1308such that an exposed portion of each of the plurality of silicon particles1304extends away from a surface1602of the substrate layer1308, as illustrated inFIG.16B. At block1706, an insulator layer is placed on the surface of the substrate layer. For example, the insulator layer1310is placed on the surface1802of the substrate layer1308, as illustrated inFIG.18A. At block1708, a portion of the insulating layer is removed. The removed portion of the insulator layer1310is positioned around a portion of the coating layer1306that is positioned around the exposed portion of each of the plurality of silicon particles1304, as illustrated inFIG.18B. At block1710, a selective carrier transport layer is generated by counter-doping a first portion of the coating layer to be an opposite polarity from a second portion of the coating layer.FIG.18Cillustrates an example implementation in which the selective carrier transport layer1312is generated by counter-doping a first portion1804of the coating layer1306to be an opposite polarity from a second portion1806of the coating layer1306. In some implementations, the first portion1804of the coating layer1306may be highly-conductive for negative charge carriers and highly-resistive for positive charge carriers. Further, the second portion1806of the coating layer1306may be highly-conductive for the positive charge carriers and highly-resistive for the negative charge carriers. In other implementations, the first portion1804of the coating layer1306may be highly-conductive for positive charge carriers and highly-resistive for negative charge carriers. Further, the second portion1806of the coating layer1306may be highly-conductive for the negative charge carriers and highly-resistive for the positive charge carriers.

Silicon particles are approximately three to seven times smaller than silicon wafers. For example,FIG.19illustrates an example of the size difference between a silicon wafer1902and a plurality of silicon particles1904. As illustrated inFIG.19, the surface area of the silicon particles1904is a much higher relative to their total volume than the surface area of the silicon wafer1902relative to its total volume. Because untreated silicon surfaces and the interface of silicon with metals and many other materials are highly recombination-active, without a coating as described herein, charge carriers will recombine at too high a rate at the surface of the silicon particles1904to enable efficient collection of photo-excited free electrons or a high enough steady-state concentration of photo-excited free electrons to produce high current and voltage, respectively, for efficient photovoltaic power conversion. Given the relatively small surface area to volume ratio of the silicon wafer1902, the loss of charge carriers at the surfaces does not affect the overall performance of photovoltaic devices with silicon wafers as greatly. The coatings described above (e.g., coating layer1306) reduce recombination of photo-excited free electrons at the surface of the silicon particles1904by five to seven orders of magnitude, enabling greater photocurrent, operating voltage, and power generation in photovoltaic devices with the silicon particles1904(which are very small).

In testing, the average photoluminescence intensity for silicon wafer-based photovoltaic devices with good passivation measured 292 counts whereas the average photoluminescence intensity for photovoltaic devices using silicon particles as described herein measured 329.15 counts (i.e., about a 9% improvement). For reference, the average photoluminescence intensity for silicon wafer-based photovoltaic devices with poor passivation measured 21.33 counts and the average photoluminescence intensity for photovoltaic devices using silicon particles with poor passivation measured 7.5 counts.

Consistent with the above disclosure, the examples of systems and methods enumerated in the following clauses are specifically contemplated and are intended as a non-limiting set of examples.

Clause 1. A method for fabricating a photovoltaic device, comprising:applying a coating layer that surrounds each of a plurality of silicon particles;implanting the plurality of silicon particles into a substrate layer such that an exposed portion of each of the plurality of silicon particles extends away from a surface of the substrate layer;removing a portion of the coating layer that is positioned around the exposed portion of each of the plurality of silicon particles;placing an insulator layer on the surface of the substrate layer; andplacing a selective carrier transport layer on the exposed portion of each of the plurality of silicon particles.

Clause 2. The method of any clause herein, wherein the coating layer is highly-conductive for negative charge carriers and highly-resistive for positive charge carriers, and wherein the selective carrier transport layer is highly-conductive for the positive charge carriers and highly-resistive for the negative charge carriers.

Clause 3. The method of any clause herein, wherein the coating layer includes amorphous silicon.

Clause 4. The method of any clause herein, wherein the coating layer includes an oxide layer and a polysilicon layer.

Clause 5. The method of any clause herein, wherein a major axis of each of the plurality of silicon particles is less than 100 micrometers.

Clause 6. The method of any clause herein, further comprising:placing a transparent conductor layer on the selective carrier transport layer for lateral charge transport.

Clause 7. The method of any clause herein, wherein the portion of the coating layer that is positioned around the exposed portion of each of the plurality of silicon particles is removed by etching.

Clause 8. A photovoltaic device, comprising:a substrate layer including a surface;a plurality of silicon particles implanted in the substrate layer such that an exposed portion of each of the plurality of silicon particles extends away from the surface of the substrate layer;a coating layer positioned between each of the plurality of silicon particles and the substrate layer;an insulator layer positioned on the surface of the substrate layer; anda selective carrier transport layer positioned on the exposed portion of each of the plurality of the silicon particles.

Clause 9. The photovoltaic device of any clause herein, wherein the coating layer is highly-conductive for negative charge carriers and highly-resistive for positive charge carriers, and wherein the selective carrier transport layer is highly-conductive for the positive charge carriers and highly-resistive for the negative charge carriers.

Clause 10. The photovoltaic device of any clause herein, wherein the coating layer includes amorphous silicon.

Clause 11. The photovoltaic device of any clause herein, wherein the coating layer includes an oxide layer and a polysilicon layer.

Clause 12. The photovoltaic device of any clause herein, wherein a major axis of each of the plurality of silicon particles is less than 100 micrometers.

Clause 13. The photovoltaic device of any clause herein, further comprising:a transparent conductor layer positioned on the selective carrier transport layer for lateral charge transport.

Clause 14. The photovoltaic device of any clause herein, wherein the portion of the coating layer that is positioned around the exposed portion of each of the plurality of silicon particles is removed by etching.

Clause 15. The photovoltaic device of any clause herein, wherein the coating layer is doped with an n-type dopant, wherein the coating layer surrounds each of the plurality of silicon particles, and wherein the portion of the coating layer that is positioned around the exposed portion of each of the plurality of silicon particles is doped with an p-type dopant.

Clause 16. A method for fabricating a photovoltaic device, comprising:applying a coating layer that surrounds each of a plurality of silicon particles;implanting the plurality of silicon particles into a substrate layer such that an exposed portion of each of the plurality of silicon particles extends away from a surface of the substrate layer;placing an insulator layer on the surface of the substrate layer and on the exposed portion of each of the plurality of the silicon particles;removing a portion of the insulator layer that is positioned around a portion of the coating layer that is positioned around the exposed portion of each of the plurality of silicon particles; andgenerating a selective carrier transport layer by counter-doping a first portion of the coating layer to be an opposite polarity from a second portion of the coating layer, wherein the first portion of the coating layer is positioned around the exposed portion of each of the plurality of silicon particles, and wherein the second portion of the coating layer is implanted in the substrate layer.

Clause 17. The method of any clause herein, wherein the first portion of the coating layer is highly-conductive for negative charge carriers and highly-resistive for positive charge carriers, and wherein the second portion of the coating layer is highly-conductive for the positive charge carriers and highly-resistive for the negative charge carriers.

Clause 18. The method of any clause herein, wherein the coating layer includes amorphous silicon.

Clause 19. The method of any clause herein, wherein the coating layer includes an oxide layer and a polysilicon layer.

Clause 20. The method of any clause herein, wherein a major axis of each of the plurality of silicon particles is less than 100 micrometers

No part of the description in this application should be read as implying that any particular element, step, or function is an essential element that must be included in the claim scope. The scope of patented subject matter is defined only by the claims. Moreover, none of the claims is intended to invoke 25 U.S.C. § 104(f) unless the exact words “means for” are followed by a participle.

The foregoing description, for purposes of explanation, use specific nomenclature to provide a thorough understanding of the described embodiments. However, it should be apparent to one skilled in the art that the specific details are not required to practice the described embodiments. Thus, the foregoing descriptions of specific embodiments are presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the described embodiments to the precise forms disclosed. It should be apparent to one of ordinary skill in the art that many modifications and variations are possible in view of the above teachings.

The above discussion is meant to be illustrative of the principles and various embodiments of the present disclosure. Once the above disclosure is fully appreciated, numerous variations and modifications will become apparent to those skilled in the art. It is intended that the following claims be interpreted to embrace all such variations and modifications.