Patent ID: 12229061

DETAILED DESCRIPTION

Below, embodiments of the present disclosure will be described in detail and clearly to such an extent that one skilled in the art easily carries out the present disclosure.

FIG.1is a block diagram illustrating an electronic device according to some example embodiments of the present disclosure. Referring toFIG.1, an electronic device100may include a memory controller110and a plurality of memory devices120.

The memory controller110may control the plurality of memory devices120. For example, the memory controller110may control the plurality of memory devices120through a plurality of channels CH1to CHn, respectively.

The plurality of memory devices120may operate based on signals received from the memory controller110through the plurality of channels CH1to CHn. For example, under control of the memory controller110, the plurality of memory devices120may store data received through the plurality of channels CH1to CHn or may send data stored therein to the memory controller110through the plurality of channels CH1to CHn.

In some example embodiments, the plurality of memory devices120may be respectively implemented with NAND flash memory chips or may be implemented with a multi-chip package including a plurality of NAND flash memory chips, but the present disclosure is not limited thereto. Each of the plurality of memory devices120may include one of various memory devices such as a static RAM (SRAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), and a ferroelectric RAM (FRAM).

In some example embodiments, at least two or more memory devices may communicate with the memory controller110through one channel (e.g., the first channel CH1). That is, the electronic device100may have a multi-rank structure. For example, a signal to be sent to a first memory device connected with the first channel CH1may be provided to the remaining memory devices connected with the first channel CH1. In this case, a reflection signal coming from the remaining memory devices may be introduced into the first memory device. In this case, a reflection signal coming from each branch point may be introduced into the first memory device. The reflection signal introduced to the first memory device may have an influence on the signal input to the first memory device. In this case, the first memory device may fail to receive a signal normally or may operate abnormally.

The electronic device100according to the present disclosure may reduce the influence of a reflection signal occurring between a plurality of memory devices connected with the same channel, by adjusting (e.g., extending or reducing) a length of a channel of a specific section between the memory controller110and the memory devices120or a length of a signal line of the specific section. A length of a signal line of the electronic device100according to the present disclosure will be described in more detail with reference to the following drawings.

The electronic device100according to the present disclosure may further include stubs between the memory controller110and the memory devices120. For example, a stub may refer to a dummy signal line. A first end of a stub may be connected with a branch point or a specific point, and a second end of the stub may be left open-circuit without connection with any other electrical path. Alternatively, the first end of the stub may be connected with a signal line (or a first end of the signal line), and the second end of the stub may be left open-circuit without connection with any other electrical path. The influence of the reflection signal may decrease by further adding a stub. A stub of the electronic device100according to the present disclosure will be described in more detail with reference to the following drawings.

In some example embodiments, each of the plurality of memory devices120may be a memory package including a plurality of memory chips (or dies). In some example embodiments, as each of the plurality of memory devices120includes a plurality of memory chips (or dies), a high-capacity electronic device100may be implemented. Below, for convenience of description, the term “memory device” is used. However, the term “memory device” used herein may be used to indicate a memory package including a plurality of memory chips.

FIG.2is a block diagram for describing a signal flow between a memory controller and a memory device. Below, for convenience of description, example embodiments of the present disclosure will be described with reference to first to fourth memory devices M1to M4connected with the first channel CH1and one signal line of a plurality of signal lines of the first channel CH1. However, the present disclosure is not limited thereto. For example, the first channel CH1may further include a plurality of signal lines. Alternatively, a memory controller11may be further connected with any other memory devices through the first channel CH1.

Referring toFIG.2, the memory controller11may be connected with the first to fourth memory devices M1to M4through signal lines S1to S7of the first channel CH1. In some example embodiments, the signal lines S1to S7of the first channel CH1may indicate one signal line for transferring a data signal DQ or one of various control signals to at least one of the memory devices M1to M4.

For example, one data signal DQ may be provided to the memory devices M1to M4through the signal lines S1to S7. That is, the first to fourth memory devices M1to M4may be configured to receive the same signal from the memory controller11through the signal lines S1to S7of the first channel CH1. To this end, the signal lines S1to S7may be classified based on a plurality of sections PR1to PR3.

The plurality of sections PR1to PR3may be classified based on branch points B11, B21, and B22. For example, the signal line S1from the memory controller11to the first branch point B11may be included in the first section PR1. The signal line S2from the first branch point B11to the second branch point B21and the signal line S3from the first branch point B11to the third branch point B22may be included in the second section PR2. The signal lines S4and S5from the second branch point B21to the first and second memory devices M1and M2and the signal lines S6and S7from the third branch point B22to the third and fourth memory devices M3and M4may be included in the third section PR3. That is, as a signal line is branched through the branch points B11, B21, and B22, the memory controller11and the first to fourth memory devices M1to M4may be electrically connected with each other.

In some example embodiments, the first section PR1may include one signal line (i.e., S1). The second section PR2may include two signal lines S2and S3. The third section PR3may include four signal lines S4, S5, S6, and S7. However, the present disclosure is not limited thereto. For example, the number of signal lines in each section may be changed depending on the number of memory devices connected with one channel.

In some example embodiments, in an electronic device10, the first branch point B11may be disposed adjacent to the memory devices M1to M4. As such, a length from a first end to a second end of the signal line S1of the first section PR1may be longer than a length from a first end to a second end of the signal line S2of the second section PR2.

In some example embodiments, the memory controller11may select a memory device, to which a signal is to be sent, by using a separate control signal (e.g., a chip select signal). For example, in the case where the memory controller11sends an input signal to the first memory device M1, the memory controller11may activate a chip select signal corresponding to the first memory device M1and may send an input signal through the signal lines S1to S7. In some example embodiments, chip select signals may be individually provided to the first to fourth memory devices M1to M4through separate signal lines different from each other.

In this case, because the same input signal is provided to the remaining memory devices M2to M4, a reflective wave or a reflection signal may come from the remaining memory devices M2to M4. For example, in the case where the memory controller11sends an input signal through the signal lines S1to S7for the purpose of sending the input signal to the first memory device M1, a reflection signal may be generated at an input terminal of the third memory device M3due to impedance mismatching.

In some example embodiments, each of the memory devices M1to M4may include an on-die termination (ODT) resistor for impedance matching. The ODT resistor may prevent or reduce a reflection signal by making impedance matching between a signal line and the memory devices M1to M4. However, in the case where an operating speed of the electronic device100is a specific speed or higher (e.g., in the case where the electronic device100performs a high-speed operation), it may be difficult to attenuate a reflection signal through a general ODT resistor.

Alternatively, a reflective wave or a reflection signal may come from each of the branch points B11, B21, and B22. For example, in the case where the memory controller11sends an input signal through the signal lines S1to S7for the purpose of sending the input signal to the first memory device M1, a reflection signal may be generated at the third branch point B22due to impedance mismatching. The reflection signal may cause the distortion of signal. This may mean that the first memory device M1fails to determine the input signal accurately.

For example, a reflection signal coming from the third memory device M3may be introduced into the first memory device M1through signal lines S6, S3, S2, and S4. Alternatively, a reflection signal coming from the third branch point B22may be introduced into the first memory device M1through signal lines S3, S2, and S4. That is, the first memory device M1may receive the reflection signal coming from the third memory device M3or the reflection signal coming from the third branch point B22, as well as the input signal sent from the memory controller11. In this case, the first memory device M1may fail to determine the input signal normally. The reflection signal may cause the distortion of signal. This may mean that the first memory device M1fails to determine the input signal accurately.

FIGS.3A to3Care block diagrams illustrating an electronic device according to some example embodiments of the present disclosure. Below, for convenience of description, additional description associated with the components described above will be omitted to avoid redundancy.

Referring toFIG.3A, the electronic device100may include the memory controller110and the first to fourth memory devices M1to M4. The memory controller110may be connected with the first to fourth memory devices M1to M4through signal lines SL11SL21, SL22, SL31, SL32, SL33, and SL34of the first channel CH1. As in the above description, the signal lines SL11to SL34of the first channel CH1may be classified into the first to third sections PR1to PR3based on branch points BP11, BP21, and BP22. This is similar to that described above, and thus, additional description will be omitted to avoid redundancy.

To remove or reduce the influence of a reflection signal occurring between memory devices or a reflection signal coming from a branch point, the electronic device100according to the present disclosure may adjust a channel length of a specific section or a length of a signal line of a specific section. For example, unlike the example illustrated inFIG.2, according to some example embodiments illustrated inFIG.3A, a length (e.g., a first length L1) of the signal line SL11in the first section PR1may be equal to a length (e.g., a second length L2) of the signal lines SL21and SL22in the second section PR2. That is, the signal lines SL21and SL22of the second section PR2may be extended.

For example, the first length L1indicates a length from a first end to a second end of the signal line SL11in the first section PR1. That is, the first length L1may correspond to a distance from the memory controller110to the first branch point BP11. The second length L2indicates a length from a first end to a second end of each of the signal lines SL21and SL22in the second section PR2. That is, the second length L2may correspond to a distance from the first branch point BP11to the second branch point BP21or a distance from the first branch point BP11to the third branch point BP22.

In other words, the length of the signal line SL11ofFIG.3Amay be shorter than the length of the signal line S1ofFIG.2A. Alternatively, the length of the signal lines SL21and SL22ofFIG.3Amay be longer than the length of the signal lines S2and S3ofFIG.2A.

In some example embodiments, compared toFIG.2A, as the first length L1decreases and the second length L2increases, a ratio of the first length L1to the second length L2may be 1:1. The length of each of the signal lines SL21and SL22of the second section PR2may be equal to the length of the signal line SL11of the first section PR1to such an extent as a reflection signal coming from the third or fourth memory device M3or M4or a reflection signal coming from the third branch point BP22has little to no influence on an input signal transferred to the first or second memory device M1or M2. Alternatively, the length of each of the signal lines SL21and SL22of the second section PR2may be equal to the length of the signal line SL11of the first section PR1such as a reflection signal is attenuated to a specific level or lower. In this case, the specific level may be a signal level that allows a reflection signal coming from the third or fourth memory device M3or M4or the third branch point BP22to have little to no influence on the input signal transferred to the first or second memory device M1or M2.

As described above, a reflection signal coming from a branch point may be attenuated to the specific level or lower by making the first length L1and the second length L2equally. That is, as the reflection signal is attenuated to the specific level or lower, the influence of the reflection signal on an input signal provided to an activated memory device may decrease.

Unlike the example illustrated inFIG.3A, referring toFIG.3B, a length (e.g., the second length L2) of each of the signal lines SL21and SL22in the second section PR2may be longer than a length (e.g., the first length L1) of the signal line SL11in the first section PR1.

In other words, the length of the signal line SL11ofFIG.3Bmay be shorter than the length of the signal line SL11ofFIG.3A. Alternatively, the length of each of the signal lines SL21and SL22ofFIG.3Bmay be longer than the length of each of the signal lines SL21and SL22ofFIG.3A.

In some example embodiments, compared toFIG.2A, as the first length L1decreases and the second length L2increases, a ratio of the first length L1to the second length L2may be 3/7. As such, the length of the signal lines SL21and SL22of the second section PR2(or a signal line length of the second section PR2) may be extended such that reflection signals coming from the branch points BP21and BP22in the second section PR2have little or no influence on an input signal transferred to the memory devices M1to M4.

Unlike the example illustrated inFIG.3A, referring toFIG.3C, a length (e.g., the second length L2) of the signal lines SL21and SL22in the second section PR2may be shorter than a length (e.g., the first length L1) of the signal line SL11in the first section PR1.

In other words, the length of the signal line SL11ofFIG.3Cmay be longer than the length of the signal line SL11ofFIG.3A. Alternatively, the length of the signal lines SL21and SL22ofFIG.3Cmay be shorter than the length of the signal lines SL21and SL22ofFIG.3A.

In some example embodiments, compared toFIG.2A, as the first length L1decreases and the second length L2increases, a ratio of the first length L1to the second length L2may be 7/3. As such, the length of the signal lines SL21and SL22of the second section PR2(or a signal line length of the second section PR2) may be extended such that reflection signals coming from the branch points BP21and BP22in the second section PR2have little to no influence on an input signal transferred to the memory devices M1to M4.

As described above, compared toFIG.2A, as the first length L1decreases and the second length L2increases, a ratio of the first length L1to the second length L2may be a given ratio. For example, a ratio of the first length L1to the second length L2may be about 3/7 to 7/3. Alternatively, the second length L2may be about 0.43 to 2.33 times the first length L1. Accordingly, the influence of the reflection signal on an input signal may decrease.

FIG.4is a block diagram illustrating an electronic device according to some example embodiments of the present disclosure. Unlike the example illustrated inFIG.3A, according to some example embodiments illustrated inFIG.4, a length (e.g., the second length L2) of the first signal line SL21of the second section PR2and a length (e.g., a third length L3) of the second signal line SL22of the second section PR2may be different from each other.

In some example embodiments, the length L2of the first signal line SL21of the second section PR2may be equal to a length (e.g., the first length L1) of the signal line SL11of the first section PR1. The length (e.g., the third length L3) of the second signal line SL22of the second section PR2may be shorter than the length L1of the signal line SL11of the first section PR1. That is, lengths of signal lines included in the respective sections PR1, PR2, and PR3may be equal to or different from each other.

In some example embodiments, even though the signal lines SL21and SL22of the second section PR2have the same length, the signal line SL11of the first section PR1and each of the signal lines SL21and SL22of the second section PR2may have a given ratio. For example, as described with reference toFIGS.3A to3C, a ratio of the length of the signal line SL11of the first section PR1to the length of each of the signal lines SL21and SL22of the second section PR2may be 3/7 to 7/3.

An example embodiment in which the length of the first signal line SL21of the second section PR2is longer than the length of the second signal line SL22of the second section PR2is illustrated inFIG.4, but the present disclosure is not limited thereto. The length of the first signal line SL21of the second section PR2may be shorter than the length of the second signal line SL22of the second section PR2.

FIGS.5A to5Care block diagrams illustrating an electronic device according to some example embodiments of the present disclosure. Below, for convenience of description, additional description associated with the components described above will be omitted to avoid redundancy. Referring toFIG.5A, an electronic device200may include a memory controller210and the first to fourth memory devices M1to M4. The memory controller210may be connected with the first to fourth memory devices M1to M4through the signal lines SL11SL21, SL22, SL31, SL32, SL33, and SL34of the first channel CH1. As in the above description, the signal lines SL11to SL34of the first channel CH1may be classified into first to third sections PR1to PR3based on the branch points BP11, BP21, and BP22. This is similar to that described above, and thus, additional description will be omitted to avoid redundancy.

In some example embodiments, a length of the signal lines SL31, SL32, SL33, and SL34of the third section PR3may be shorter than a length of signal lines SL11, SL21, and SL22of the first and second sections PR1and PR2. For example, the signal lines SL31, SL32, SL33, and SL34of the third section PR3may be micro signal lines.

The electronic device200may further include stubs ST1and ST2. A first end of each of the stubs ST1and ST2may be connected with a corresponding branch point, and a second end thereof may be left open-circuit without connection with any other electrical path. For example, the first end of the first stub ST1may be connected with the second branch point BP21, and the second end thereof may be left open-circuit without connection with any other electrical path. The first end of the second stub ST2may be connected with the third branch point BP22, and the second end thereof may be left open-circuit without connection with any other electrical path. For example, a stub may refer to a dummy signal line.

A length from the first end to the second end of each of the stubs ST1and ST2may be equal to a length of the signal lines SL31to SL34of the third section PR3. A fourth length L4indicates a distance or a length from a first end to a second end of each of the signal lines SL31to SL34in the third section PR3. That is, the fourth length L4may correspond to a distance from the second branch point BP21or the third branch point BP22to the memory devices M1to M4. A length of each of the stubs ST1and ST2may be equal to the fourth length L4.

As described above, the electronic device200may further include the stubs ST1and ST2at the branch points BP21and BP22to such an extent as a reflection signal has little to no influence on an input signal transferred to a memory device. Alternatively, the electronic device200may further include the stubs ST1and ST2at the branch points BP21and BP22to such an extent as a reflection signal is attenuated to the specific level or lower. As such, a signal reflected from an end of each of the stubs ST1and ST2may compensate for the distortion of signal due to the reflection signal. This may mean that a signal characteristic of an electronic device performing a high-speed operation is improved.

The electronic device200according to some example embodiments of the present disclosure may adjust a length of each of the stubs ST1and ST2to reduce the influence of the reflection signal. The length of each of the stubs ST1and ST2may be determined based on the length of the signal lines SL31to SL34of the third section PR3such that the influence of the reflection signal is removed or reduced.

Referring toFIG.5B, a length (e.g., a fifth length L5) of each of the stubs ST1and ST2may be different from a length (e.g., the fourth length L4) of the signal lines SL31to SL34of the third section PR3. The fifth length L5indicates a distance or a length from a first end to a second end of each of the stubs ST1and ST2.

In some example embodiments, the length from the first end to the second end of each of the stubs ST1and ST2may be shorter than a length from a first end to a second end of each of the signal lines SL31to SL34of the third section PR3. That is, the fifth length L5may be shorter than the fourth length L4. For example, the length of the stubs ST1and ST2may be at least 0.1 times the length of the signal lines SL31to SL34of the third section PR3. Alternatively, the length of the stubs ST1and ST2may be at least 1 mm.

Referring toFIG.5C, a length (e.g., the fifth length L5) of each of the stubs ST1and ST2may be different from a length (e.g., the fourth length L4) of the signal lines SL31to SL34of the third section PR3.

In some example embodiments, the length from the first end to the second end of each of the stubs ST1and ST2may be longer than a length from a first end to a second end of each of the signal lines SL31to SL34of the third section PR3. That is, the fifth length L5may be longer than the fourth length L4. For example, the length of the stubs ST1and ST2may be up to 5 times the length of the signal lines SL31to SL34of the third section PR3.

As described above, the length of the stubs ST1and ST2may be adjusted to such an extent as a reflection signal has little to no influence on an input signal transferred to a memory device. Alternatively, the length of the stubs ST1and ST2may be adjusted based on the signal lines SL31to SL34of the third section PR3such as a reflection signal is attenuated to the specific level or lower. The length of the stubs ST1and ST2may be equal to or different from the length of the signal lines SL31to SL34of the third section PR3. The length of the stubs ST1and ST2may be K times the length of the signal lines SL31to SL34of the third section PR3. In this case, “K” may be 0.1 to 5. Alternatively, the length of the stubs ST1and ST2may be 1 mm or more, and may be less than or equal to 5 times the length of the signal lines SL31to SL34of the third section PR3.

In some example embodiments, as illustrated inFIGS.5A to5C, the length of the first stub ST1may be equal to the length of the second stub ST2. However, the present disclosure is not limited thereto. The length of the first stub ST1and the length of the second stub ST2may be different from each other.

In some example embodiments, as illustrated inFIGS.5A to5C, in the electronic device200including stubs, a length of the signal line SL11of the first section PR1and a length of the signal lines SL21and SL22of the second section PR2may be equal. However, the present disclosure is not limited thereto. As described above, the length of the signal line SL11of the first section PR1and the length of the signal lines SL21and SL22of the second section PR2may be equal or different. A ratio of the length of the signal line SL11of the first section PR1to the length of the signal lines SL21and SL22of the second section PR2may be a given ratio. For example, the given ratio may be 3/7 to 7/3.

FIG.6is a block diagram illustrating an electronic device according to some example embodiments of the present disclosure. Referring toFIG.6, the electronic device200may include the memory controller210and the first to fourth memory devices M1to M4. The memory controller210may be connected with the first to fourth memory devices M1to M4through the signal lines SL11SL21, SL22, SL31, SL32, SL33, and SL34of the first channel CH1. As in the above description, the signal lines SL11to SL34of the first channel CH1may be classified into the first to third sections PR1to PR3based on the branch points BP11, BP21, and BP22. This is similar to that described above, and thus, additional description will be omitted to avoid redundancy.

The electronic device200may further include stubs ST3and ST4. For example, a first end of the third stub ST3may be connected with the first branch point BP11, and a second end thereof may be left open-circuit without connection with any other electrical path. A first end of the fourth stub ST4may be connected with the first branch point BP11, and a second end thereof may be left open-circuit without connection with any other electrical path.

A length from the first end to the second end of each of the stubs ST3and ST4may be equal to a length of the signal lines SL21and SL22of the second section PR2. That is, the length of each of the stubs ST3and ST4may correspond to the length of the signal lines SL21and SL22of the second section PR2.

Unlike the example illustrated inFIG.6, the length of the stubs ST3and ST4may be different from the length of the signal lines SL21and SL22of the second section PR2. The length of the stubs ST3and ST4may be shorter than the length of the signal lines SL21and SL22of the second section PR2. Alternatively, the length of the stubs ST3and ST4may be longer than the length of the signal lines SL21and SL22of the second section PR2. For example, the length of the stubs ST3and ST4may be K times the length of the signal lines SL21and SL22of the second section PR2. In this case, “K” may be 0.1 to 5. Alternatively, the length of the stubs ST3and ST4may be 1 mm or more, and may be less than or equal to 5 times the length of the signal lines SL21and SL22of the second section PR2.

In some example embodiments, the length of the third stub ST3may be equal to the length of the fourth stub ST4. However, the present disclosure is not limited thereto. The length of the third stub ST3and the length of the fourth stub ST4may be different from each other.

In some example embodiments, in the electronic device200including stubs, the length of the signal line SL11of the first section PR1and the length of the signal lines SL21and SL22of the second section PR2may be equal. However, the present disclosure is not limited thereto. As illustrated inFIGS.2to4, the length of the signal line SL11of the first section PR1and the length of the signal lines SL21and SL22of the second section PR2may be equal or different. A ratio of the length of the signal line SL11of the first section PR1to the length of each of the signal lines SL21and SL22of the second section PR2may be 3/7 to 7/3.

FIG.7is a block diagram illustrating an electronic device according to some example embodiments of the present disclosure. Referring toFIG.7, the electronic device200may include the memory controller210and the first to fourth memory devices M1to M4. The memory controller210may be connected with the first to fourth memory devices M1to M4through the signal lines SL11SL21, SL22, SL31, SL32, SL33, and SL34of the first channel CH1. As in the above description, the signal lines SL11to SL34of the first channel CH1may be classified into the first to third sections PR1to PR3based on the branch points BP11, BP21, and BP22. This is similar to that described above, and thus, additional description will be omitted to avoid redundancy.

Unlike the example illustrated inFIG.5A, the electronic device200ofFIG.7may further include a signal line SL0. The memory controller210may be connected with the first branch point BP11through the signal line SL0and the signal line SL11of the first section PR1. A first end of the signal line SL0may be connected with the memory controller210, and a second end thereof may be connected with a first point P1. A first end of the signal line SL11of the first section PR1may be connected with the first point P1, and a second end thereof may be connected with the first branch point BP11. For example, a length of the signal line SL0may be shorter than a length of the signal line SL11of the first section PR1. The signal line SL0may be a micro signal line.

The electronic device200may further include a stub ST5. For example, a first end of the stub ST5may be connected with the first point P1, and a second end thereof may be left open-circuit without connection with any other electrical path.

A length from the first end to the second end of the stub ST5may be equal to the length of the signal line SL11of the first section PR1. That is, the length of the stub ST5may correspond to the length of the signal line SL11of the first section PR1.

Unlike the example illustrated inFIG.7, the length of the stub ST5may be different from the length of the signal line SL11of the first section PR1. The length of the stub ST5may be shorter than the length of the signal line SL11of the first section PR1. Alternatively, the length of the stub ST5may be longer than the length of the signal line SL11of the first section PR1. For example, the length of stub ST5may be K times the length of the signal line SL11of the first section PR1. In this case, “K” may be 0.1 to 5. Alternatively, the length of the stub ST5may be 1 mm or more, and may be less than or equal to 5 times the length of the signal line SL11of the first section PR1.

In some example embodiments, in the electronic device200including stubs, the length of the signal line SL11of the first section PR1and the length of the signal lines SL21and SL22of the second section PR2may be equal. However, the present disclosure is not limited thereto. As illustrated inFIGS.2to4, the length of the signal line SL11of the first section PR1and the length of the signal lines SL21and SL22of the second section PR2may be equal or different. A ratio of the length of the signal line SL11of the first section PR1to the length of each of the signal lines SL21and SL22of the second section PR2may be 3/7 to 7/3.

FIGS.8A and8Bare block diagrams illustrating an electronic device according to some example embodiments of the present disclosure. Referring toFIGS.8A and8B, the electronic device200may include the memory controller210and the first to fourth memory devices M1to M4. The memory controller210may be connected with the first to fourth memory devices M1to M4through signal lines SL0, SL11SL21, SL22, SL31, SL32, SL33, and SL34of the first channel CH1. As in the above description, the signal lines SL11to SL34of the first channel CH1may be classified into the first to third sections PR1to PR3based on the branch points BP11, BP21, and BP22. This is similar to that described above, and thus, additional description will be omitted to avoid redundancy.

The electronic device200may further include stubs ST1to ST5. For example, a first end of the first stub ST1may be connected with the second branch point BP21, and a second end thereof may be left open-circuit without connection with any other electrical path. A first end of the second stub ST2may be connected with the third branch point BP22, and a second end thereof may be left open-circuit without connection with any other electrical path. A first end of the third stub ST3may be connected with the first branch point BP11, and a second end thereof may be left open-circuit without connection with any other electrical path. A first end of the fourth stub ST4may be connected with the first branch point BP11, and a second end thereof may be left open-circuit without connection with any other electrical path. A first end of the fifth stub ST5may be connected between the signal line SL0and the signal line SL11of the first section PR1(e.g., with a first point P1), and a second end thereof may be left open-circuit without connection with any other electrical path.

A length of each of the stubs ST1to ST5may be equal to or different from a length of a corresponding signal line(s). The length of each of the stubs ST1to ST5may be shorter or longer than the length of the corresponding signal line(s). For example, the length of each of the stubs ST1to ST5may be K times the length of the corresponding signal line(s). In this case, “K” may be 0.1 to 5. Alternatively, the length of each of the stubs ST1to ST5may be 1 mm or more, and may be less than or equal to 5 times the length of the corresponding signal line(s). The corresponding signal line(s) of each of the stubs ST1to ST5may indicate a signal line connected with a point or a branch point connected with one end of each of the stubs ST1to ST5. For example, the signal line corresponding to the first stub ST1may include the signal lines SL31and SL32connected with the second branch point BP21connected with the first stub ST1.

The electronic device200ofFIG.8Amay include the first to fifth stubs ST1to ST5. However, the present disclosure is not limited thereto. For example, unlike the example illustrated inFIG.8A, the electronic device200may include at least one of the first to fifth stubs ST1to ST5. For example, the electronic device200may include the first and fourth stubs ST1and ST4only.

The electronic device200ofFIG.8Bmay include the stubs ST1to ST5. UnlikeFIG.8A, the stubs ST1to ST5ofFIG.8Bmay be connected with any other place except for a branch point or a point between signal lines. For example, each of the stubs ST1to ST5may be connected between a first end and a second end of a corresponding signal line. That is, each of the stubs ST1to ST5may be connected with a middle part of the corresponding signal line.

For example, a first end of the first stub ST1may be connected between a first end and a second end of the signal line SL31, not the second branch point BP21, and a second end of the first stub ST1may be left open-circuit without connection with any other electrical path. A first end of the second stub ST2may be connected between a first end and a second end of the signal line SL34, not the third branch point BP22, and a second end of the second stub ST2may be left open-circuit without connection with any other electrical path. A first end of the third stub ST3may be connected between a first end and a second end of the signal line SL21, not the first branch point BP11, and a second end of the third stub ST3may be left open-circuit without connection with any other electrical path. A first end of the fourth stub ST4may be connected between a first end and a second end of the signal line SL22, not the first branch point BP11, and a second end of the fourth stub ST4may be left open-circuit without connection with any other electrical path. A first end of the fifth stub ST5may be connected between a first end and a second end of the signal line SL11, not the first point P1, and a second end of the fifth stub ST5may be left open-circuit without connection with any other electrical path.

A length of each of the stubs ST1to ST5may be equal to or different from a length of a corresponding signal line. The length of each of the stubs ST1to ST5may be shorter or longer than the length of the corresponding signal line. For example, the length of each of the stubs ST1to ST5may be K times the length of the corresponding signal line. In this case, “K” may be 0.1 to 5. Alternatively, the length of each of the stubs ST1to ST5may be 1 mm or more, and may be less than or equal to 5 times the length of the corresponding signal line. The corresponding signal line of each of the stubs ST1to ST5may indicate a signal line connected with a point or a branch point connected with one end of each of the stubs ST1to ST5. For example, the signal line corresponding to the first stub ST1may include the signal lines SL31and SL32connected with the second branch point BP21connected with the first stub ST1.

The electronic device200ofFIG.8Bmay include the first to fifth stubs ST1to ST5. However, the present disclosure is not limited thereto. For example, unlike the example illustrated inFIG.8B, the electronic device200may include at least one of the first to fifth stubs ST1to ST5. For example, the electronic device200may include the first and fourth stubs ST1and ST4only.

In the electronic device200ofFIGS.8A and8B, the length of the signal line SL11of the first section PR1and the length of the signal lines SL21and SL22of the second section PR2may be equal. However, the present disclosure is not limited thereto. As illustrated inFIGS.2to4, the length of the signal line SL11of the first section PR1and the length of the signal lines SL21and SL22of the second section PR2may be equal or different. A ratio of the length of the signal line SL11of the first section PR1to the length of the signal lines SL21and SL22of the second section PR2may be 3/7 to 7/3.

As described above, as stubs (e.g., dummy lines) are added to branch points or points and as lengths of the stubs, the number of stubs, and directions of the stubs are adjusted, the electronic device200may remove or reduce the influence of the reflection signal. That is the stubs may be oriented parallel to, perpendicular to, or at another orientation to the signal lines.

FIGS.9A to9Care block diagrams illustrating an electronic device according to some example embodiments of the present disclosure. Referring toFIG.9A, an electronic device300may include a memory controller310and first and second memory devices M1and M2. The memory controller310may be connected with the first and second memory devices M1and M2through signal lines SL11, SL21, and SL22of the first channel CH1.

The signal lines SL11, SL21, and SL22of the first channel CH1may be classified into first and second sections PR1and PR2based on a branch point BP11. For example, the signal line SL11from the memory controller310to the branch point BP11may be included in the first section PR1. The signal lines SL21and SL22from the branch point BP11to the first and second memory devices M1and M2may be included in the second section PR2. That is, as a signal line is branched through the branch point BP11, the memory controller310and the first and second memory devices M1and M2may be electrically connected with each other.

In some example embodiments, the first section PR1may include one signal line (i.e., SL11). The second section PR2may include two signal lines (i.e., SL21and SL22). However, the present disclosure is not limited thereto. For example, the number of signal lines in each section may be changed depending on the number of memory devices connected with one channel.

To remove or reduce the influence of the reflection signal occurring between memory devices or the reflection signal coming from a branch point, the electronic device300according to the present disclosure may adjust a channel length of a specific section or a length of a signal line of the specific section. For example, according to some example embodiments illustrated inFIG.9A, a length (e.g., a first length L1) of the signal line SL11in the first section PR1may be equal to a length (e.g., a second length L2) of the signal lines SL21and SL22in the second section PR2.

For example, the first length L1indicates a length from a first end to a second end of the signal line SL11in the first section PR1. That is, the first length L1may correspond to a distance from the memory controller310to the branch point BP11. The second length L2indicates a length from a first end to a second end of each of the signal lines SL21and SL22in the second section PR2. That is, the second length L2may correspond to a distance from the branch point BP11to the first memory device M1or a distance from the branch point BP11to the second memory device M2.

As described above, a ratio of the length of the signal line SL11of the first section PR1to the length of the signal lines SL21and SL22of the second section PR2may be 1:1. As such, a reflection signal coming from the second memory device M2may be attenuated to such an extent as to have little to no influence of the reflection signal on an input signal transferred to the first memory device M1.

Unlike the example illustrated inFIG.9A, referring toFIG.9B, a length (e.g., the second length L2) of the signal lines SL21and SL22in the second section PR2may be longer than a length (e.g., the first length L1) of the signal line SL11in the first section PR1.

In other words, the length of the signal line SL11ofFIG.9Bmay be shorter than the length of the signal line SL11ofFIG.9A. Alternatively, the length of the signal lines SL21and SL22ofFIG.9Bmay be longer than the length of the signal lines SL21and SL22ofFIG.9A.

In some example embodiments, a ratio of the first length L1to the second length L2may be 3/7. That is, the length L2of the signal lines SL21and SL22of the second section PR2may be I times the length L1of the signal line SL11of the first section PR1. Here, “I” may be “1” or more and may be “2.33” or less.

Unlike the example illustrated inFIG.9A, referring toFIG.9C, a length (e.g., the second length L2) of the signal lines SL21and SL22in the second section PR2may be shorter than a length (e.g., the first length L1) of the signal line SL11in the first section PR1.

In other words, the length of the signal line SL11ofFIG.9Cmay be longer than the length of the signal line SL11ofFIG.9A. Alternatively, the length of the signal lines SL21and SL22ofFIG.9Cmay be shorter than the length of the signal lines SL21and SL22ofFIG.9A.

In some example embodiments, a ratio of the first length L1to the second length L2may be 7:3. That is, the length L2of the signal lines SL21and SL22of the second section PR2may be m times the length L1of the signal line SL11of the first section PR1. Here, “m” may be “0.42” or more and may be “1” or less.

As illustrated inFIGS.9A to9C, the length of the first signal line SL21of the second section PR2may be equal to the length of the second signal line SL22of the second section PR2. However, the present disclosure is not limited thereto. Although not illustrated inFIGS.9A to9C, the length of the first signal line SL21of the second section PR2may be different from the length of the second signal line SL22of the second section PR2.

As described above, the first length L1and the second length L2may have a given ratio. For example, a ratio of the first length L1to the second length L2may be about 3/7 to 7/3. Alternatively, the second length L2may be K times the first length L1. Here, “K” may be “0.42” or more and may be “2.33” or less. As such, the influence of the reflection signal may decrease.

FIGS.10A to10Dare block diagrams illustrating an electronic device according to some example embodiments of the present disclosure. Below, for convenience of description, additional description associated with the components described above will be omitted to avoid redundancy. Referring toFIG.10A, an electronic device400may include a memory controller410and first and second memory devices M1and M2. The memory controller410may be connected with the first and second memory devices M1and M2through signal lines SL0, SL11, SL21, SL22, SL31, and SL32of the first channel CH1. A first end of the signal line SL0may be connected with the memory controller410, and a second end thereof may be connected with a first point P1. The signal lines SL11to SL32of the first channel CH1may be classified into first to third sections PR1to PR3based on a branch point BP11and points P1to P3.

For example, the signal line SL11from the first point P1to the branch point BP11may be included in the first section PR1. The signal line SL21from the branch point BP11to the second point P2and the signal line SL22from the branch point BP11to the third point P3may be included in the second section PR2. The signal line SL31from the second point P2to the first memory device M1and the signal line SL32from the third point P3to the second memory device M2may be included in the third section PR3.

For example, the signal line SL0may be shorter than the signal line SL11of the first section PR1. Each of the signal lines SL31and SL32of the third section PR3may be shorter than the signal line SL21and SL22of the second section PR2. The signal lines SL0, SL31, and SL32may be micro signal lines.

In some example embodiments, the electronic device400may further include stubs ST1and ST2. A first end of each of the stubs ST1and ST2may be connected with a corresponding point, and a second end thereof may be left open-circuit without connection with any other electrical path. For example, the first end of the first stub ST1may be connected with the second point P2, and the second end thereof may be left open-circuit without connection with any other electrical path. The first end of the second stub ST2may be connected with the third point P3, and the second end thereof may be left open-circuit without connection with any other electrical path.

A length from the first end to the second end of each of the stubs ST1and ST2may be equal to a length of the signal lines SL31and SL32of the third section PR3. That is, the length of each of the stubs ST1and ST2may correspond to the length of the signal lines SL31and SL32of the third section PR3. The length of each of the stubs ST1and ST2may be a fourth length L4. The fourth length L4indicates a distance or a length from a first end to a second end of each of the signal lines SL31and SL32in the third section PR3. That is, the fourth length L4indicates a distance from the second or third point P2or P3to the memory devices M1and M2.

In some example embodiments, the length of the stubs ST1and ST2may be different from the length of the signal lines SL31and SL32of the third section PR3. For example, the length of the stubs ST1and ST2may be shorter than the length of the signal lines SL31and SL32of the third section PR3. Alternatively, the length of the stubs ST1and ST2may be longer than the length of the signal lines SL31and SL32of the third section PR3. The length of the stubs ST1and ST2may be K times the fourth length L4. In this case, “K” may be 0.1 to 5. Alternatively, the length of the stubs ST1and ST2may be 1 mm or more, and may be less than or equal to 5 times the fourth length L4.

In some example embodiments, as illustrated inFIG.10A, the length of the first stub ST1may be equal to the length of the second stub ST2. However, the present disclosure is not limited thereto. The length of the first stub ST1and the length of the second stub ST2may be different from each other.

As described above, the electronic device400may further include the stubs ST1and ST2at the points P2and P3. As such, a signal reflected from an end of each of the stubs ST1and ST2may compensate for the distortion of signal due to a reflection signal. Accordingly, a signal characteristic of an electronic device performing a high-speed operation may be improved.

Referring toFIG.10B, the electronic device400may include the memory controller410and the first and second memory devices M1and M2. The memory controller410may be connected with the first and second memory devices M1and M2through the signal lines SL0, SL11, SL21, SL22, SL31, and SL32of the first channel CH1. As in the above description, the signal lines SL11to SL32of the first channel CH1may be classified into the first to third sections PR1to PR3based on the branch point BP11and the points P1to P3. This is similar to that described above, and thus, additional description will be omitted to avoid redundancy.

The electronic device400may further include stubs ST3and ST4. For example, a first end of the third stub ST3may be connected with the first branch point BP11, and a second end thereof may be left open-circuit without connection with any other electrical path. A first end of the fourth stub ST4may be connected with the first branch point BP11, and a second end thereof may be left open-circuit without connection with any other electrical path.

A length from the first end to the second end of each of the stubs ST3and ST4may be equal to a length of the signal lines SL21and SL22of the second section PR2. That is, the length of each of the stubs ST3and ST4may correspond to the length of the signal lines SL21and SL22of the second section PR2.

Unlike the example illustrated inFIG.10B, the length of the stubs ST3and ST4may be different from the length of the signal lines SL21and SL22of the second section PR2. The length of the stubs ST3and ST4may be shorter than the length of the signal lines SL21and SL22of the second section PR2. Alternatively, the length of the stubs ST3and ST4may be longer than the length of the signal lines SL21and SL22of the second section PR2. For example, the length of the stubs ST3and ST4may be K times the length of the signal lines SL21and SL22of the second section PR2. In this case, “K” may be 0.1 to 5. Alternatively, the length of the stubs ST3and ST4may be 1 mm or more, and may be less than or equal to 5 times the length of the signal lines SL21and SL22of the second section PR2.

In some example embodiments, the length of the third stub ST3may be equal to the length of the fourth stub ST4. However, the present disclosure is not limited thereto. The length of the third stub ST3and the length of the fourth stub ST4may be different from each other.

Referring toFIG.10C, the electronic device400may include the memory controller410and the first and second memory devices M1and M2. The memory controller410may be connected with the first and second memory devices M1and M2through the signal lines SL0, SL11, SL21, SL22, SL31, and SL32of the first channel CH1. As in the above description, the signal lines SL11to SL32of the first channel CH1may be classified into the first to third sections PR1to PR3based on the branch point BP11and the points P1to P3. This is similar to that described above, and thus, additional description will be omitted to avoid redundancy.

The electronic device400may further include a stub ST5. For example, a first end of the stub ST5may be connected with the first point P1, and a second end thereof may be left open-circuit without connection with any other electrical path.

In some example embodiments, a length from the first end to the second end of the stub ST5may be equal to the length of the signal line SL11of the first section PR1. That is, the length of the stub ST5may correspond to the length of the signal line SL11of the first section PR1.

Unlike the example illustrated inFIG.10C, the length of the stub ST5may be different from the length of the signal line SL11of the first section PR1. The length of the stub ST5may be shorter than the length of the signal line SL11of the first section PR1. Alternatively, the length of the stub ST5may be longer than the length of the signal line SL11of the first section PR1. For example, the length of stub ST5may be K times the length of the signal line SL11of the first section PR1. In this case, “K” may be 0.1 to 5. Alternatively, the length of the stub ST5may be 1 mm or more, and may be less than or equal to 5 times the length of the signal line SL11of the first section PR1.

Referring toFIG.10D, the electronic device400may include the memory controller410and the first and second memory devices M1and M2. The memory controller410may be connected with the first and second memory devices M1and M2through the signal lines SL0, SL11, SL21, SL22, SL31, and SL32of the first channel CH1. As in the above description, the signal lines SL11to SL32of the first channel CH1may be classified into the first to third sections PR1to PR3based on the branch point BP11and the points P1to P3. This is similar to that described above, and thus, additional description will be omitted to avoid redundancy.

The electronic device400may further include stubs ST1to ST5. For example, a first end of the first stub ST1may be connected with the second point P2, and a second end thereof may be left open-circuit without connection with any other electrical path. A first end of the second stub ST2may be connected with the third point P3, and a second end thereof may be left open-circuit without connection with any other electrical path. A first end of the third stub ST3may be connected with the branch point BP11, and a second end thereof may be left open-circuit without connection with any other electrical path. A first end of the fourth stub ST4may be connected with the branch point BP11, and a second end thereof may be left open-circuit without connection with any other electrical path. A first end of the fifth stub ST5may be connected with the first point P1, and a second end thereof may be left open-circuit without connection with any other electrical path.

A length of each of the stubs ST1to ST5may be equal to or different from a length of a corresponding signal line. The length of each of the stubs ST1to ST5may be shorter or longer than the length of the corresponding signal line. For example, the length of each of the stubs ST1to ST5may be K times the length of the corresponding signal line. In this case, “K” may be 0.1 to 5. Alternatively, the length of each of the stubs ST1to ST5may be 1 mm or more, and may be less than or equal to 5 times the length of the corresponding signal line.

The corresponding signal line of each of the stubs ST1to ST5may indicate a signal line connected with a point or a branch point connected with one end of each of the stubs ST1to ST5. For example, the signal line corresponding to the first stub ST1may include the signal line SL31connected with the second point P2connected with the first stub ST1.

In some example embodiments, unlikeFIG.10D, the stubs ST1to ST5may be connected with any other place except for a branch point or a point between signal lines. For example, each of the stubs ST1to ST5may be connected between a first end and a second end of the corresponding signal line. That is, each of the stubs ST1to ST5may be connected with a middle part of the corresponding signal line.

For example, the first end of the first stub ST1may be connected between a first end and a second end of the signal line SL31, not the second point P2, and the second end of the first stub ST1may be left open-circuit without connection with any other electrical path. The first end of the second stub ST2may be connected between a first end and a second end of the signal line SL32, not the third point P3, and the second end of the second stub ST2may be left open-circuit without connection with any other electrical path. The first end of the third stub ST3may be connected between a first end and a second end of the signal line SL21, not the branch point BP11, and the second end of the third stub ST3may be left open-circuit without connection with any other electrical path. The first end of the fourth stub ST4may be connected between a first end and a second end of the signal line SL22, not the branch point BP11, and the second end of the fourth stub ST4may be left open-circuit without connection with any other electrical path. The first end of the fifth stub ST5may be connected between a first end and a second end of the signal line SL11, not the first point P1, and the second end of the fifth stub ST5may be left open-circuit without connection with any other electrical path.

The electronic device400ofFIG.10Dmay include the first to fifth stubs ST1to ST5. However, the present disclosure is not limited thereto. For example, unlike the example illustrated inFIG.10D, the electronic device400may include at least one of the first to fifth stubs ST1to ST5. For example, the electronic device200may include the first and fourth stubs ST1and ST4only.

As illustrated inFIGS.10A to10D, in the electronic device400including stubs, the length of the signal line SL11of the first section PR1and the length of the signal lines SL21and SL22of the second section PR2may be equal. However, the present disclosure is not limited thereto. As illustrated inFIGS.3A to4, the length of the signal line SL11of the first section PR1and the length of the signal lines SL21and SL22of the second section PR2may be equal or different. A ratio of the length of the signal line SL11of the first section PR1to the length of the signal lines SL21and SL22of the second section PR2may be a given ratio. For example, the given ratio may be 3/7 to 7/3.

FIG.11is a block diagram illustrating a channel ofFIG.9Ain more detail. Referring toFIG.9A, the electronic device300may include the memory controller310and the first and second memory devices M1and M2. For brevity of drawing and convenience of description, additional description associated with components the same as or similar to the above components will be omitted to avoid redundancy.

In some example embodiments, the signal line SL11of the first section PR1may include a first sub signal line SL11aand a second sub signal line SL11b. The signal line SL21of the second section PR2may include a third sub signal line SL21aand a fourth sub signal line SL21b.

A signal corresponding to a bidirectional signal may be transferred through the first sub signal line SL11aand the third sub signal line SL21a. The signal corresponding to the bidirectional signal may include a data signal DQ and a data strobe signal DQS. For example, the memory controller310may send the data signal DQ corresponding to write data to the first memory device M1through the first sub signal line SL11aand the third sub signal line SL21a. The first memory device M1may send the data signal DQ corresponding to read data to the memory controller310through the first sub signal line SL11aand the third sub signal line SL21a.

Control signals CTRL corresponding to a unidirectional signal may be transferred through the second sub signal line SL11band the fourth sub signal line SL21b. The control signals CTRL may include a command latch enable signal CLE, an address latch enable signal ALE, a read enable signal RE, a write enable signal WE, and the like. For example, the memory controller310may send the write enable signal WE to the first memory device M1through the second sub signal line SL11band the fourth sub signal line SL21b.

As described above, each of signal lines included in the first channel CH1of an electronic device described with reference toFIGS.1to10Dmay include a sub signal line transferring a bidirectional signal and a sub signal line transferring a unidirectional signal.

The above example embodiments are described with reference to a write operation of the electronic device (i.e., an operation in which a memory controller sends a signal to one of a plurality of memory devices), but the present disclosure is not limited thereto. For example, in a read operation of the electronic device, one (e.g., a first memory device) of the plurality of memory devices may send an input signal (e.g., read data) to the memory controller. In this case, a signal line length of a specific section may be extended such that a reflection signal coming from another of the plurality of memory devices is not introduced into the memory controller or the first memory device or is attenuated.

FIGS.12A to12Gare views illustrating a printed circuit board according to some example embodiments of the inventive concept.FIG.12Ais a plan view illustrating a top surface of a printed circuit board PCB_1according to some example embodiments of the present disclosure, andFIG.12Bis a cross-sectional view of the printed circuit board PCB_1taken along line A-A′ ofFIG.12A.

An electronic device may include a printed circuit board, a memory controller, and a plurality of memory devices. The memory controller and the plurality of memory devices are described above, and thus, additional description will be omitted to avoid redundancy. According to the example embodiments of the present disclosures described with reference toFIGS.1to11, to reduce the influence of the reflection signal, signal lines included in the printed circuit board may have a given ratio, or a stub(s) may be added thereto. Signal lines formed in a metal layer will be described in detail with reference to the following drawings.

InFIGS.12A to12G, there is illustrated some example embodiments in which a signal line electrically connected with a part of a plurality of sockets SCK11to SCK4n. However, the present disclosure is not limited thereto. For example, the remaining sockets may also be electrically connected with the remaining signal lines. In some example embodiments, a signal line may be included in a metal layer of the printed circuit board PCB_1. The metal layer may be implemented with a multi-layer including a plurality of layers. In some example embodiments, a printed circuit board capable of being applied to the electronic device100ofFIG.3Awill be described with reference toFIGS.12A and12B.

Referring toFIGS.12A and12B, the printed circuit board PCB_1may include a controller socket SCK_CT and the plurality of sockets SCK11to SCK4n. InFIGS.12Aand12B, the controller socket SCK_CT may be located in one side region of the printed circuit board PCB_1. For example, the controller socket SCK_CT may be disposed in one side region of the printed circuit board PCB_1, and the plurality of sockets SCK11to SCK4nmay be disposed (or arranged) in the remaining region thereof. The controller socket SCK_CT may be a region, a component, or a device in which the memory controller is mounted. The plurality of sockets SCK11to SCK4nmay be regions, components, or devices in which plural memory devices are respectively mounted. Although not clearly illustrated in drawings, additional sockets may be further formed on a bottom surface of the printed circuit board PCB_1. The plurality of memory devices may be mounted in the additional sockets formed on the bottom surface of the printed circuit board PCB_1.

Each of the memory controller and the plurality of memory devices may be mounted in the corresponding socket, and the memory controller and the plurality of memory devices may communicate with each other through the signal line included in the printed circuit board. The printed circuit board may include the signal line. The signal line may be a signal transmission path between the memory controller and the memory devices. That is, the signal line may be configured to make electrical connection between the plurality of sockets SCK11to SCK4nand the controller socket SCK_CT. In some example embodiments, the signal line may be formed in a metal layer or a wire layer of the printed circuit board PCB_1.

The controller socket SCK_CT may be electrically connected with the first branch point BP11. The first branch point BP11may be spaced from the controller socket SCK_CT as much as a given distance. The first branch point BP11may be electrically connected with each of the second and third branch points BP21and BP22.

The second branch point BP21may be electrically connected with each of the sockets SCK11and SCK51, and the third branch point BP22may be electrically connected with the sockets SCK21and SCK61. In this case, as illustrated inFIG.12B, a length of the first section PR1may be equal to a length of the second section PR2. A ratio of the length of the first section PR1to the length of the second section PR2may be 3/7 to 7/3.

For example, the sockets SCK11, SCK21, SCK51, and SCK61may be electrically connected with the controller socket SCK_CT through the same channel (i.e., one signal line). In this case, the sockets SCK11and SCK51may be disposed to face each other with respect to the printed circuit board PCB_1, and the sockets SCK21and SCK61may be disposed to face each other with respect to the printed circuit board PCB_1. In other words, the sockets SCK11and SCK21may be disposed on a top surface PCB_TOP of the printed circuit board PCB_1, and the sockets SCK51and SCK61may be disposed on a bottom surface PCB_BOTTOM of the printed circuit board PCB_1.

In this case, the sockets SCK11and SCK21located on the top surface PCB_TOP may be sockets that are not adjacent to each other. For example, any other sockets (e.g., SCK12to SCK1n) may be interposed between the sockets SCK11and SCK21connected with the same channel (i.e., one signal line), and the other sockets (e.g., SCK12to SCK1n) may be electrically connected with the controller socket SCK_CT through a separate signal line. The sockets SCK51and SCK61located on the bottom surface PCB_BOTTOM may be sockets that are not adjacent to each other. That is, any other sockets (e.g., SCK52to SCK5n) may be interposed between the sockets SCK51and SCK61connected with one signal line, and the other sockets (e.g., SCK52to SCK5n) may be electrically connected with the controller socket SCK_CT through a separate signal line.

In some example embodiments, in a conventional electronic device, sockets adjacent to each other are electrically connected with a controller socket through one signal line. In this case, because branch points are defined in surrounding regions of the adjacent sockets, a length of a first section is relatively short. In contrast, according to some example embodiments of the present disclosure, a length of the second section PR2may be relatively long by connecting sockets (e.g., SCK11and SCK21), which are not adjacent to each other, with the controller socket SCK_CT through one signal line. Accordingly, the influence of the reflection signal occurring between memory devices respectively mounted in corresponding sockets may decrease.

The printed circuit board PCB_1illustrated inFIGS.12A and12Bis an example, and the present disclosure is not limited thereto. For example, in the printed circuit board PCB_1, a location of each of the branch points BP11, BP21, and BP22may be variously changed without departing from the scope and spirit of the inventive concepts.

For example, the first branch point BP11may be located in a region of the socket SCK11, a region of the socket SCK21, or any other region, and signal lines of the first and second sections PR1and PR2may be defined such that a length of the first section PR1and a length of the second section PR2are equal. Alternatively, the signal lines of the first and second sections PR1and PR2may be defined such that the length of the first section PR1and the length of the second section PR2have a given ratio.

In some example embodiments, a total length of signal lines respectively connecting the controller socket SCK_CT with a plurality of sockets may be variously determined within a range from about 50 mm to about 200 mm. For example, a length of a signal line connecting the controller socket SCK_CT and the socket SCK11may be 50 mm, and a length of a signal line connecting the controller socket SCK_CT and the socket SCK2nmay be 200 mm.

Below, for convenience of description, it is assumed that a length of signal lines of the third section PR3is relatively small compared to a length of signal lines of the first and second sections PR1and PR2. That is, it is assumed that the length of the third section PR3is small enough to ignore compared to the length of the signal lines of the first and second sections PR1and PR2.

For example, it is assumed that a length of a signal line connecting the controller socket SCK_CT and the socket SCK11is 50 mm. The length of the signal line SL11of the first section PR1and the length of each of the signal lines SL21and SL22of the second section PR2may be equal. That is, the length of the signal line SL11of the first section PR1may be 25 mm, and the length of each of the signal lines SL21and SL22of the second section PR2may be 25 mm.

Alternatively, the length of the signal line SL11of the first section PR1and the length of each of the signal lines SL21and SL22of the second section PR2may have a given ratio. A ratio of the length of the signal line SL11of the first section PR1to the length of each of the signal lines SL21and SL22of the second section PR2may be 3/7 to 7/3. For example, when the length of the signal line SL11of the first section PR1is 15 mm, the length of each of the signal lines SL21and SL22of the second section PR2may be 35 mm. When the length of the signal line SL11of the first section PR1is 35 mm, the length of each of the signal lines SL21and SL22of the second section PR2may be 15 mm.

For example, it is assumed that a length of a signal line connecting the controller socket SCK_CT and the socket SCK2nis 200 mm. The length of the signal line SL11of the first section PR1and the length of each of the signal lines SL21and SL22of the second section PR2may be equal. That is, the length of the signal line SL11of the first section PR1may be 100 mm, and the length of each of the signal lines SL21and SL22of the second section PR2may be 100 mm.

For example, when the length of the signal line SL11of the first section PR1is 60 mm, the length of each of the signal lines SL21and SL22of the second section PR2may be 140 mm. When the length of the signal line SL11of the first section PR1is 140 mm, the length of each of the signal lines SL21and SL22of the second section PR2may be 60 mm.

FIG.12Cis a plan view illustrating a top surface of a printed circuit board PCB_2according to some example embodiments of the present disclosure, andFIG.12Dis a cross-sectional view of the printed circuit board PCB_2taken along line B-B′ ofFIG.12C. An electronic device may include the printed circuit board PCB_2, the memory controller, and the first to fourth memory devices M1to M4. The memory controller and the first to fourth memory devices M1to M4are described above, and thus, additional description will be omitted to avoid redundancy. For a brief description, additional description associated with the components described above will be omitted to avoid redundancy.

Referring toFIGS.12C and12D, the printed circuit board PCB_2may include the controller socket SCK_CT and a plurality of sockets SCK1to SCK4. The controller socket SCK_CT may be a region, a component, or a device in which the memory controller is mounted. The first to fourth sockets SCK1to SCK4may be regions, components, or devices in which the first to fourth memory devices M1to M4are respectively mounted. Although not clearly illustrated in drawings, additional sockets SCK2and SCK4may be further formed on a bottom surface of the printed circuit board PCB. The second and fourth memory devices M2and M4may be respectively mounted in the additional sockets SCK2and SCK4formed on the bottom surface of the printed circuit board PCB_2.

For example, the controller socket SCK_CT and the first and third sockets SCK1and SCK3may be formed on a top surface PCB_TOP of the printed circuit board PCB_2, and the second and fourth sockets SCK2and SCK4may be formed on a bottom surface PCB_BOTTOM of the printed circuit board PCB_2. In some example embodiments, the second socket SCK2may be disposed to face the first socket SCK1with respect to the printed circuit board PCB_2, and the fourth socket SCK4may be disposed to face the third socket SCK3with respect to the printed circuit board PCB_2.

The controller socket SCK_CT may be located in one side region of the printed circuit board PCB_2. For example, the controller socket SCK_CT may be disposed in one side region of the printed circuit board PCB_2, and the first and third sockets SCK1and SCK3may be disposed (or arranged) in the remaining region thereof. The first socket SCK1may be disposed to be spaced from the controller socket SCK_CT in a first direction D1as much as a given distance. The second socket SCK2may be disposed to be spaced from the first socket SCK1in a second direction D2, which is perpendicular to the first direction D1, as much as a given distance.

For example, as in the above description, the signal line may be extended from the controller socket SCK_CT, and may be branched at the plurality of branch points BP11, BP21, and BP22. As such, the plurality of sockets SCK1to SCK4and the controller socket SCK_CT may be electrically connected. For example, the signal line SL11from the controller socket SCK_CT to the branch point BP11may be included in the first section PR1. The signal lines SL21and SL22from the branch point BP11to the branch points BP21and BP22may be included in the second section PR2. The signal lines SL31to SL34from the branch point BP22to the first to fourth sockets SCK1to SCK4may be included in the third section PR3.

In some example embodiments, the branch points BP11, BP21, and BP22may be located in regions associated with the controller socket SCK_CT and the first to fourth sockets SCK1to SCK4. For example, the branch point BP11may be located between the controller socket SCK_CT and the first and third sockets SCK1and SCK3. The branch point BP21may be located between the first and second sockets SCK1and SCK2and may be connected with the first and second sockets SCK1and SCK2through a via contact. The branch point BP22may be located between the third and fourth sockets SCK3and SCK4and may be connected with the third and fourth sockets SCK3and SCK4through a via contact.

Alternatively, the branch point BP11may be defined at a location spaced from the controller socket SCK_CT in a third direction D3as much as the first length L1. For example, the third direction D3may be a direction between the first direction D1and the second direction D2. An angle between the first direction D1and the third direction D3may be an acute angle. The branch point BP22may be defined at a location spaced from the branch point BP11in the third direction D3as much as the second length L2. The branch point BP21may be defined at a location spaced from the branch point BP11in a fourth direction D4as much as the second length L2. For example, the fourth direction D4may be a direction between the first direction D1and a direction facing away from the second direction D2. An angle between the first direction D1and the fourth direction D4may be an acute angle. In this case, the first length L1and the second length L2may be equal. However, the present disclosure is not limited thereto. For example, a ratio of the first length L1to the second length L2may be 3/7 to 7/3. An optimum ratio of the first length L1to the second length L2may be determined such that a noise of a reflection signal is canceled out.

The branch points BP21and BP22may be defined at locations spaced from the sockets SCK1to SCK4in a vertical direction as much as a given distance(s). In some example embodiments, the vertical direction may refer to a direction that is perpendicular to a top surface or a bottom surface of the printed circuit board PCB_2. In other words, the vertical direction may refer to a direction passing through the top surface or the bottom surface of the printed circuit board PCB_2. As described above, the example embodiments of the present disclosure described with reference toFIGS.1to11may be implemented by forming branch points at the printed circuit board PCB_2.

FIG.12Eis a plan view illustrating a top surface of a printed circuit board PCB_3according to some example embodiments of the present disclosure, andFIG.12Fis a cross-sectional view of the printed circuit board PCB_3taken along line C-C′ ofFIG.12E. An electronic device may include the printed circuit board PCB_3, the memory controller, and the first to fourth memory devices M1to M4. Referring toFIGS.12E and12F, the printed circuit board PCB_3may include the controller socket SCK_CT and the plurality of sockets SCK1to SCK4. For a brief description, additional description associated with the components described above will be omitted to avoid redundancy.

The controller socket SCK_CT may be located in one side region of the printed circuit board PCB_3. For example, the controller socket SCK_CT may be disposed in one side region of the printed circuit board PCB_3, and the first and third sockets SCK1and SCK3may be disposed (or arranged) in the remaining region thereof. Unlike the example illustrated inFIG.12C, the controller socket SCK_CT and the first and third sockets SCK1and SCK3may be arranged in the first direction D1. The first socket SCK1may be disposed at a location spaced from the controller socket SCK_CT in the first direction D1as much as a given distance. The third socket SCK3may be disposed at a location spaced from the first socket SCK1in the first direction D1as much as a given distance.

In some example embodiments, the branch points BP11, BP21, and BP22may be located in regions associated with the controller socket SCK_CT and the first to fourth sockets SCK1to SCK4. For example, the branch point BP11may be located between the controller socket SCK_CT and the first socket SCK1. The branch point BP21may be located between the first and second sockets SCK1and SCK2and may be connected with the first and second sockets SCK1and SCK2through a via contact. The branch point BP22may be located between the third and fourth sockets SCK3and SCK4and may be connected with the third and fourth sockets SCK3and SCK4through a via contact.

Alternatively, the branch point BP11may be defined at a location spaced from the controller socket SCK_CT in the first direction D1as much as the first length L1. The branch point BP22may be defined at a location spaced from the branch point BP11in the first direction D1as much as the second length L2. The branch point BP21may be defined at a location spaced from the branch point BP11in the first direction D1as much as a sixth length L6. For example, the sixth length L6may be shorter than the second length L2. The first length L1and the second length L2may be equal. However, the present disclosure is not limited thereto. For example, a ratio of the first length L1to the second length L2may be 3/7 to 7/3.

In some example embodiments, the signal line SL21connecting the branch point BP11and the branch point BP21may not be formed in a straight line or with the shortest distance. The signal line SL21may be formed in the shape of a zigzag pattern as illustrated inFIG.12E. For example, to provide a longer electrical connection path between the branch point BP11and the branch point BP21, the signal line SL21may include portions extending in the first direction D1and portions extending in the second direction D2. Ends of the portions extending in the first direction D1and ends of the portions extending in the second direction D2may be connected to each other. As such, a length of the signal line SL21connecting the branch point BP11and the branch point BP21may be equal to the second length L2. That is, the signal line SL21may have the second length L2that is longer than the sixth length L6being a straight distance between the branch point BP11and the branch point BP21in the first direction D1.

The branch points BP21and BP22may be defined at locations spaced from the sockets SCK1to SCK4in a vertical direction as much as given distances. In some example embodiments, the vertical direction may refer to a direction that is perpendicular to a top surface or a bottom surface of the printed circuit board PCB_3. In other words, the vertical direction may refer to a direction passing through the top surface or the bottom surface of the printed circuit board PCB_3. As described above, the example embodiments of the present disclosure described with reference toFIGS.1to11may be implemented by forming branch points at the printed circuit board PCB_3.

Referring toFIG.12G, the printed circuit board PCB_3may further include stubs ST1and ST2. In some example embodiments, a first end of the first stub ST1may be connected with the branch point BP21, and a second end of the first stub ST1may be left open-circuit without connection with any other electrical path. The first stub ST1may be formed to extend from the branch point BP21in a horizontal direction. A first end of the second stub ST2may be connected with the branch point BP22, and a second end of the second stub ST2may be left open-circuit without connection with any other electrical path. The second stub ST2may be formed to extend from the branch point BP22in the horizontal direction.

For example, the horizontal direction may refer to a direction that is parallel to the top surface or the bottom surface of the printed circuit board PCB_3. For example, the horizontal direction may indicate a horizontal axis direction of a plane defined by the top surface of the printed circuit board PCB_3, a vertical axis direction of the plane, or a direction in which horizontal and vertical axes are combined. However, the present disclosure is not limited thereto. For example, directions of the stubs ST1and ST2may be variable.

Although not illustrated in drawings, a stub may be further connected with the branch point BP11or a point between the controller socket SCK_CT and the branch point BP11. As described above, the example embodiments of the present disclosure described with reference toFIGS.1to11may be implemented by adding a stub(s) to the printed circuit board PCB_3.

FIGS.13A and13Bare timing diagrams for describing how a reflection signal is removed, according to some example embodiments of the present disclosure. In the timing diagrams ofFIGS.13A and13B, a horizontal axis represents a time, and a vertical axis represents an amplitude of a signal.FIG.13Ashows a signal waveform in an electronic device according to the related part, andFIG.13Bshows a signal waveform in an electronic device according to the present disclosure.

As illustrated inFIG.13A, in the case of the related art, a signal margin may correspond to a first time T1due to a reflection signal. Due to the distortion of an input signal due to the reflection signal, an amplitude change of a signal may not be sufficient. In this case, a signal that is input to a memory device may not be determined normally.

In contrast, the electronic device according to example embodiments of the present disclosure may provide a signal margin corresponding to a second time T2longer than the first time T1. That is, in the case where the first section PR1and the second section PR2have a given ratio or stubs are added thereto, the influence of the reflection signal coming from any other memory devices or a branch point may be reduced, thus increasing a signal margin or making an amplitude change of a signal sufficient. That is, the reliability of an input signal transferred to a memory device may be improved.

FIG.13Cis a graph for describing how a reflection signal is removed, according to some example embodiments of the present disclosure. In the graph ofFIG.13C, a horizontal axis represents a ratio of a length (e.g., the first length L1) of the signal line SL11of the first section PR1and a length (e.g., the second length L2) of each of the signal lines SL21and SL22of the second section PR2, and a vertical axis represents a signal margin.

In some example embodiments, when the ratio (e.g., L1/L2) of the first length L1to the second length L2is 3/7, the signal margin may have a second value v2; when the ratio of the first length L1to the second length L2is 1, the signal margin may have a first value v1; when the ratio of the first length L1to the second length L2is 7/3, the signal margin may have a third value v3. The first value v1 may be greater than the second value v2, and the second value v2 may be greater than the third value v3. That is, when the first length L1and the second length L2are equal, the signal margin may be the greatest.

Table 1 below shows signal margins according to a total length including the first length L1and the second length L2in the electronic device10or100described with reference toFIG.2or3A. Referring to Table 1 below, a first margin “Margin 1” indicates a signal margin of the electronic device10ofFIG.2, and a second margin “Margin 2” indicates a signal margin of the electronic device100ofFIG.3A.

It is assumed that a length of signal lines of the third section PR3is small enough to ignore compared to a length of signal lines of the first and second sections PR1and PR2. A total line of signal lines respectively connecting a memory controller with memory devices is referred to as a “total length TL”. For example, the total length TL means a length of a signal line of the first section PR1and lengths of signal lines of the second section PR2.

For example, when the total length TL is 73 mm, in the electronic device10ofFIG.2, a length of the signal line S1of the first section PR1may be 60 mm, a length of each of the signal lines S2and S3of the second section PR2may be 3 mm. In the electronic device100ofFIG.3A, a length (e.g., the first length L1) of the signal line SL11of the first section PR1may be 36.5 mm, and a length of each of the signal lines SL21and SL22of the second section PR2may be 36.5 mm.

TABLE 1TL73 mm93 mm113 mm133 mmMargin 1174 ps179 ps223 ps218 psMargin 2311 ps300 ps270 ps279 ps

When the total length TL is 73 mm, the signal margin of the electronic device10ofFIG.2may be 174 ps, and the signal margin of the electronic device100ofFIG.3Amay be 311 ps. When the total length TL is 93 mm, the signal margin of the electronic device10ofFIG.2may be 179 ps, and the signal margin of the electronic device100ofFIG.3Amay be 300 ps. When the total length TL is 113 mm, the signal margin of the electronic device10ofFIG.2may be 223 ps, and the signal margin of the electronic device100ofFIG.3Amay be 270 ps. When the total length TL is 133 mm, the signal margin of the electronic device10ofFIG.2may be 218 ps, and the signal margin of the electronic device100ofFIG.3Amay be 279 ps. The above numerical values are an example for describing embodiment of the present disclosure clearly, and the present disclosure is not limited thereto. As described above, an electronic device according to some example embodiments of the present disclosure may increase a margin of a signal by adjusting a length of a signal line of the first section PR1and a length of each of signal lines of the second section PR2.

FIG.14is a block diagram illustrating an SSD system to which an electronic device according to some example embodiments of the present disclosure is applied. Referring toFIG.14, an SSD system1000includes a host1100and an SSD1200.

The SSD1200exchanges a signal SIG with the host1100through a signal connector1201and is supplied with a power PWR through a power connector1202. The SSD1200includes an SSD memory controller1210, a plurality of flash memories1221to122n, an auxiliary power supply1230, and a buffer memory1240.

The SSD memory controller1210may control the plurality of flash memories1221to122nin response to the signal SIG received from the host1100. The plurality of flash memories1221to122nmay operate under control of the SSD memory controller1210. The auxiliary power supply1230is connected with the host1100through the power connector1202. The auxiliary power supply1230may be charged by the power PWR supplied from the host1100. When the power PWR is not smoothly supplied from the host1100, the auxiliary power supply1230may power the SSD1200.

In some example embodiments, the SSD1200may be a topology described with reference toFIGS.1to13C. For example, various components included in the SSD1200may be mounted on a printed circuit board and may be electrically connected with each other through various signal lines included in the printed circuit board. In this case, as described above, the influence of a reflection signal on a plurality of memory devices may be reduced by defining signal lines between the SSD memory controller1210and the plurality of flash memories1221to122nso as to have a given ratio or adding stubs thereto.

When the terms “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical value. Moreover, when the words “generally” and “substantially” are used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Further, regardless of whether numerical values or shapes are modified as “about” or “substantially,” it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical values or shapes.

The SSD system1000(or other circuitry, for example, the host1100, auxiliary power supply1230, buffer memory1240, SSD memory controller1210, memory controller110,210,310, electronic device100,200,300, or other circuitry discussed herein) may include hardware including logic circuits; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuitry more specifically may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a System-on-Chip (SoC), a programmable logic unit, a microprocessor, application-specific integrated circuit (ASIC), etc.

According to example embodiments of the present disclosure, the influence due to a reflection signal between a memory controller and memory devices may decrease by extending a specific section of signal lines between the memory controller and the memory devices. As such, the reliability of signal may be prevented from being reduced (or have reduced reduction) due to the reflection signal. Accordingly, a printed circuit board with improved reliability, an electronic device, and an electronic device including the printed circuit board are provided.

While the present disclosure has been described with reference to embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the present disclosure as set forth in the following claims.