Patent ID: 12249577

DESCRIPTION OF THE EMBODIMENTS

Cap structure for interconnect dielectrics and methods of fabrication are described. In the following description, numerous specific details are set forth, such as structural schemes and detailed fabrication methods in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as device operations, are described in lesser detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

In some instances, in the following description, well-known methods and devices are shown in block diagram form, rather than in detail, to avoid obscuring the present disclosure. Reference throughout this specification to “an embodiment” or “one embodiment” or “some embodiments” means that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. Thus, the appearances of the phrase “in an embodiment” or “in one embodiment” or “some embodiments” in various places throughout this specification are not necessarily referring to the same embodiment of the disclosure. Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

As used in the description and the appended claims, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term “and/or” as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

The terms “coupled” and “connected,” along with their derivatives, may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. “Coupled” may be used to indicated that two or more elements are in either direct or indirect (with other intervening elements between them) physical, electrical or in magnetic contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause an effect relationship).

The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example, in the context of materials, one material or material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material “on” a second material is in direct contact with that second material/material. Similar distinctions are to be made in the context of component assemblies. As used throughout this description, and in the claims, a list of items joined by the term “at least one of” or “one or more of” can mean any combination of the listed terms.

The term “adjacent” here generally refers to a position of a thing being next to (e.g., immediately next to or close to with one or more things between them) or adjoining another thing (e.g., abutting it).

The term “signal” may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.”

The term “device” may generally refer to an apparatus according to the context of the usage of that term. For example, a device may refer to a stack of layers or structures, a single structure or layer, a connection of various structures having active and/or passive elements, etc. Generally, a device is a three-dimensional structure with a plane along the x-y direction and a height along the z direction of an x-y-z Cartesian coordinate system. The plane of the device may also be the plane of an apparatus which comprises the device.

As used throughout this description, and in the claims, a list of items joined by the term “at least one of” or “one or more of” can mean any combination of the listed terms. Unless otherwise specified in the explicit context of their use, the terms “substantially equal,” “about equal” and “approximately equal” mean that there is no more than incidental variation between two things so described. In the art, such variation is typically no more than +/−10% of a predetermined target value.

The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “over,” “under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. For example, the terms “over,” “under,” “front side,” “back side,” “top,” “bottom,” “over,” “under,” and “on” as used herein refer to a relative position of one component, structure, or material with respect to other referenced components, structures or materials within a device, where such physical relationships are noteworthy. These terms are employed herein for descriptive purposes only and predominantly within the context of a device z-axis and therefore may be relative to an orientation of a device. Hence, a first material “over” a second material in the context of a figure provided herein may also be “under” the second material if the device is oriented upside-down relative to the context of the figure provided. In the context of materials, one material disposed over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material disposed between two materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material “on” a second material is in direct contact with that second material. Similar distinctions are to be made in the context of component assemblies.

The term “between” may be employed in the context of the z-axis, x-axis or y-axis of a device. A material that is between two other materials may be in contact with one or both of those materials, or it may be separated from both of the other two materials by one or more intervening materials. A material “between” two other materials may therefore be in contact with either of the other two materials, or it may be coupled to the other two materials through an intervening material. A device that is between two other devices may be directly connected to one or both of those devices, or it may be separated from both of the other two devices by one or more intervening devices.

Self-aligned vias are utilized in a variety of integrated circuit structure applications for eliminating shorting between metal lines (interconnects) and vias. As lateral width of metal lines and space between them continue to shrink, implementing self-aligned vias can be challenging. For example, when metal lines are scaled aggressively to a 1:1 line-space, margin for misalignment between vias and lines are also reduced. Issues arising from misalignment are multi-pronged. In embodiments, a plasma etch process is utilized to form via openings to expose metal lines. In most examples, the via openings have either a uniform width along a depth of the via opening with a narrow portion at the bottom, or the via openings are gradually tapered at the bottom to enable metal filling. Typically etch stop layers are implemented to prevent punch through during the via opening process and include materials that have slower etch rates compared to an ILD that is etched to form the via opening.

In examples where metal lines and intervening ILD are each 15 nm wide (1:1 line-space ratio for example), the lowermost portion of a via is typically less than 15 nm wide. In some such embodiments, misalignment between a via opening and a metal line may lead to variety of issues. Misalignment between via opening and via can lead to reduction in overlap area between via opening and the metal line. Consequently, a conductive via (herein via) formed in the opening can lead to increase in line resistance. Furthermore, when vias are misaligned with respect to metal lines, the distance between a misaligned via and a nearest neighboring metal line (not in contact with the via) can lead to cross talk. Another potential issue is that line edge roughness of metal lines can adversely promote shorting and increase cross talk. Because a lateral spacing between a via and a nearest neighboring line is dominated by a shortest distance between them, line edge roughness of the metal line can exacerbate the problem.

Solutions for reducing cross talk include recessing uppermost surfaces of metal lines with respect to an uppermost surface of an intervening interlayer dielectric (ILD). A recessed metal surface, for example, can increase a distance between a nearest neighboring metal line and a misaligned via. Increasing separation between a misaligned via and a neighboring metal line reduces an effective capacitance. However, selectively and controllably recessing metal lines requires not only recessing a fill metal component of the metal lines but also reducing an adjacent metal liner. In most examples, such recessing techniques produce non uniform results.

Solutions to eliminate shorting include selectively growing a liner on an uppermost surface of an intervening ILD and not on the metal lines. In some such examples, the etch stop layer is formed on the liner. When uppermost surface of the ILD is substantially co-planar with uppermost surface of the metal lines, a controlled liner growth can result in a uniform vertical separation between the uppermost surfaces of the metal lines and the ILD. In various implementations, the liner includes a dielectric material, such as an insulative metal oxide, that is primarily designed to provide etch selectivity during subsequent via etch. However, materials that provide etch selectivity, for example, oxides of metals such as hafnium, aluminum zirconium etc, also have high dielectric constants. Thus, while implementing a liner can sufficiently prevent etch punch through, the choice of materials selected can also adversely promote increased capacitance following formation of vias above the metal lines. While the liner increases a distance between uppermost surface of a nearest neighboring metal and a misaligned via, a higher dielectric constant material can lead to electric field enhancement in the vicinity of the via and the metal lines. In exemplary embodiments, the liner has a thickness between 1 nm-2 nm.

The inventors have devised a solution that can reduce capacitance, improve etch selectivity and lower electric field enhancement. The solution includes selectively growing a dielectric cap on the surface of the ILD separating the metal lines, followed by selectively growing a metal oxide liner on the dielectric cap (including on sidewalls of the dielectric cap). In exemplary embodiments, the structure including the dielectric cap and the metal oxide liner has a combined vertical thickness of least 4 nm but less than 6 nm.

In accordance with an embodiment of the present disclosure, the dielectric cap is confined within the ILD, and extends to an interface between the ILD and the metal lines, or extends over a portion of the metal lines. In embodiments, the metal oxide liner is aligned with an interface between the metal lines and the ILD, or extends over a portion of the metal lines to prevent the ILD from being etched during a via opening process. In embodiments, an etch stop layer is formed on the metal oxide liner for facilitating via opening process.

FIG.1Ais a cross-sectional illustration of an integrated circuit structure100that includes an interconnect level102above a substrate104. Substrate104may be a semiconductor substrate. In a particular embodiment, the substrate201includes monocrystalline silicon. Interconnect level102includes an ILD106between a pair of interconnect structures, such as interconnect structure108and interconnect structure110. Uppermost surfaces108A and110A of interconnect structure108and interconnect structure110, respectively, are substantially coplanar with uppermost surface106A of the ILD106, as shown. In exemplary embodiments, interconnect structures108and110are lines, as shown in the plan-view illustration ofFIG.1B. In embodiments, interconnect structure108and interconnect structure110each have a lateral width, L1. The interconnect structure108and interconnect structure110are spaced apart by a distance LD, which is also equal to a lateral width of the ILD106. In exemplary embodiments, L1and LDhave a 1:1 ratio, where L1and LDare each between 15 nm and 20 nm. In other embodiments, L1and LDare unequal. In other embodiments, interconnect structures108and110are vias (not shown). Referring again toFIG.1A, interconnect structure108and interconnect structure110each include a metal such as Co, Cu, Ru, Mo or W, or an alloy thereof.

The integrated circuit structure100further includes an interconnect level112above interconnect level102. The interconnect level112includes a cap structure114on ILD106. Cap structure114includes a top surface114A and sidewall surfaces114B. A liner116is on the top surface114A and on sidewall surfaces114B of the cap structure114. Collectively cap structure114and liner116are designed to mitigates adverse effects such as increased capacitance, electrical shorting between interconnects, and enhanced electric field effects.

In embodiments, cap structure114includes a dielectric material that is substantially similar to a dielectric material of the ILD106. For example, ILD106may include silicon and oxygen. In some embodiments, ILD106further includes trace amounts of carbon in addition to silicon and oxygen. In some such embodiments, the trace amounts of carbon is approximately 1 atomic percent or less. In other embodiments, ILD106includes silicon and one or more of oxygen, nitrogen or carbon. Cap structure114may include a material chosen for a low dielectric constant, for example less than 2, to minimize capacitance. In some embodiments, cap structure114includes silicon and oxygen. In other embodiments, cap structure114also includes trace amounts of aluminum in addition to silicon and oxygen, such as for example, approximately 1 atomic percent or less of aluminum. The liner116includes a material chosen to provide etch selectivity during fabrication of integrated circuit structure100. As such, in an embodiment, liner116includes oxygen and aluminum, (e.g., Al2O3). In embodiments, an Al2O3liner116has a dielectric constant that is greater than the dielectric constant of cap structure114. In other embodiments, the liner116includes oxygen and one or more of Al, Ti, Hf or Zr.

Collectively cap structure114and liner116are chosen to include materials and have a shape that mitigates adverse effects of capacitance, electrical shorting between interconnects, and enhanced electric field effects. As such, cap structure114and liner116may have some of the structural embodiments depicted inFIGS.2A-2C.

FIG.2Ais an enhanced cross sectional illustration of a portion inside dashed box118of the integrated circuit structure100illustrated inFIG.1A, in accordance with an embodiment of the present disclosure. As shown, cap structure114extends to an interface201between ILD106and the interconnect structure108and interface203between ILD106and interconnect structure110. In the illustrative embodiment, the cap structure114has a lateral thickness, LC, that is substantially the same as the lateral thickness, LD, of the ILD106. The cap structure114has a vertical thickness, VC, (along the z-axis) as measured from uppermost surface106A. In embodiments, VC, is between 3 nm and 6 nm. As shown, edges, or an apex where the top surface114A meets sidewall114B of cap structure114, are rounded. Rounded features are indicative of a process operation utilized to form cap structure114and will be discussed further below. When cap structure114extends to interface201and203, the liner116extends over interconnect structures108and110. In the illustrative embodiment, liner116is in contact with uppermost surfaces108A and110A. The liner116has a thickness TL. In embodiments, TLis between 0.7 nm and 2 nm. A combined vertical thickness of the liner116and cap structure114is chosen to provide mitigation against etch damage and provide appreciably low capacitance.

FIG.2Bis an enhanced cross sectional illustration of a portion inside dashed box118of the integrated circuit structure100illustrated inFIG.1A, in accordance with an embodiment of the present disclosure. As shown, cap structure114extends beyond interface201and interface203. In the illustrative embodiment, cap structure114is in contact with portions of uppermost surfaces108A and110A. In some such embodiments, cap structure114has a lateral thickness, LC, that is greater than LD. The liner116also extends over interconnect structures108and110. In the illustrative embodiment, liner116is in contact with portions of the uppermost surface108A and110A.

FIG.2Cis an enhanced cross sectional illustration of a portion inside dashed box118of the integrated circuit structure100illustrated inFIG.1A, in accordance with an embodiment of the present disclosure. As shown, cap structure114does not extend to interfaces201or203. In the illustrative embodiment, LCis less than LD. In the illustrative embodiment, portions of the liner116that is adjacent to sidewalls114B, extends to interfaces201and203. As shown, uppermost surface106A of the ILD106has a lateral thickness, LD, that is equal to a combined sum of the lateral thickness, LC, of cap structure114and two times a thickness, TL, of the liner116. In the illustrative embodiment, the liner116protects edges of ILD106at interfaces201and203during processing.

FIG.3Ais a cross-sectional illustration of an integrated circuit structure300. In the illustrative embodiment, integrated circuit structure300includes one or more features of the integrated circuit structure100, such as interconnect structures108and110, dielectric106, cap structure114and liner116. In the illustrative embodiment, cap structure114has one or more features of cap structure114that are described in association withFIG.2A.

Referring again toFIG.3A, interconnect level112further includes interconnect structures302and304separated by an ILD306. In embodiments, ILD306includes silicon and one or more of oxygen, nitrogen or carbon. In some embodiments, ILD306includes a material that is the same or substantially the same as the material of the ILD106. In examples, such as is shown, interconnect structures302and304are misaligned with interconnect structures108and110, respectively. In the illustrative embodiment, interconnect structures302and304are on least a portion of the interconnect structures108and110, respectively. As shown, lowermost portions of interconnect structures302and304are each in contact with approximately half of the lateral thickness, L1, of uppermost surfaces108A and110A, respectively. Furthermore, portions of interconnect structures302and304are also adjacent to a portion of liner116due to the misalignment.

It is to be appreciated that presence of liner116on uppermost surfaces108A and110A reduces an effective contact surface area for the interconnect structures302and304. However, a lateral thickness, of liner116, of less than 2 nm does not appreciably reduce an effective contact area between interconnect structure108and interconnect structure302, and between interconnect structure110and interconnect structure304. The lateral thickness of liner116, can be further reduced by either densifying liner116post etch and exposure of interconnect structures108and110.

The interconnect structures302and304each extend over a portion of individual cap structures114, as shown. In the illustrative embodiment, the interconnect structures302and304are not in contact with respective cap structure114or with ILD106.

In an embodiment, interconnect level112further includes an etch stop layer308between liner116and ILD306. For example, etch stop layer308is on a portion of the liner116that is on top surface114A. In the illustrative embodiment, etch stop layer308is also adjacent to liner116that is adjacent to sidewall114B. Also as shown, etch stop layer308continuously extends between interconnect structure302and interconnect structure304. In the illustrative embodiment, due to the misalignment, etch stop layer308is also on a portion of uppermost surfaces108A and110A. As such, etch stop layer308is between portions of interconnect structures108and110and ILD306. It is to be appreciated that the etch stop layer308is not between the liner116and interconnect structure302nor between liner116and interconnect structure304. In embodiments, the etch stop layer308includes silicon, nitrogen and one or more of oxygen or carbon. In exemplary embodiments, etch stop layer308includes a material that is different from a material of the ILD306or ILD106to provide etch selectivity. In some such embodiments, the etch stop layer308includes silicon and nitrogen and is doped with less than 15 atomic percent of carbon to provide etch selectivity against the material of the ILD306.

The cap structure114and liner116provide lateral and vertical separation between interconnect structure302and interconnect structure110. Such lateral and vertical separations reduces an effective capacitance that can develop between interconnect structure110and interconnect structure302, during operation. In embodiments, interconnect structure302and304each include a metal such as Co, Cu, Ru, Mo or W, or an alloy thereof.

FIG.3Bis a plan view illustration, though a horizontal line A-A′, of the structure inFIG.3A. In an embodiment, an outline of lowermost surfaces302A and304A of interconnect structures302and304are shown within dashed lines. Lowermost surfaces302A and304A interface with uppermost surface108A and110A, respectively. In the illustrative embodiment, the interconnect structures302and304are vias and have a circular plan view shape. Lower most surfaces302A and304A are partial circles. As shown, lower most surfaces302A and304A are each in contact with approximately half of the lateral thickness, L1, of uppermost surfaces108A and110A, respectively. In other embodiments, an overlap between lower most surfaces302A and304A and uppermost surfaces108A and110A vary depending on an extent of misalignment.

FIG.4is a flow diagram for a method to fabricate an integrated circuit structure, including a cap structure and a liner between two interconnect levels, in accordance with an embodiment of the present disclosure. The method400begins at operation410by receiving a work piece including a dielectric between a plurality of interconnects on a first level. The method400continues at operation420by selectively passivating an uppermost surface of the plurality of interconnects relative to uppermost surface of the dielectric. The method400continues at operation430by selectively growing a cap dielectric on the dielectric and not on the plurality of interconnects. The method400continues at operation440by selectively growing a liner on the cap dielectric. The method400concludes at operation450by removing the passivation from the plurality of interconnects and forming a second level of interconnect structures.

FIG.5Ais a cross-sectional illustration of a workpiece500that includes interconnect structures108and110formed between ILD106, in accordance with an embodiment of the present disclosure. In the illustrative embodiment, interconnect structures108and110and ILD106are formed above a substrate104. Substrate104may be a semiconductor substrate. In a particular embodiment, the substrate201includes monocrystalline silicon. In other embodiments, the substrate104includes silicon germanium, germanium, or a silicon on insulator (SOI) or group III-V materials.

In an embodiment, the fabrication process begins by passivating (indicated by arrows502) uppermost surfaces108A and110A of the interconnect structure108and interconnect structure110with a metal (or metal oxide) passivation layer504. The passivation process utilizes formation of a selective chemical bond between the passivation layer504and the material of the interconnect structures108and110and not between passivation layer504and the material of the ILD106.

In an embodiment, the passivation layer504includes self-assembled monolayers of thiols, silanes and phosphonates that are formed on uppermost surfaces108A and110A by a process of molecular layer deposition. In an embodiment, the molecular layer deposition results in a carbon rich surface on the metal of interconnect structures108and110, such as for example, copper, tungsten etc. The carbon rich surface may act as a hydrophobic barrier to ALD precursors and co-reactants which will be introduced during formation of dielectric and liner materials. In an embodiment, the passivation layer504, formed, is self-limiting and grows to a thickness of less than 2 nm.

In the illustrative embodiment, the interconnect structure108includes a single conductive material adjacent to ILD106. In some such embodiments, the interconnect structure108includes a conductive material, such as but not limited to, titanium nitride or tantalum nitride. In some such embodiments, the passivation layer504is formed over an entire surface108A as is shown. As shown, the passivation layer504is not formed on the ILD106.

In exemplary embodiments, the interconnect structures108and110include two or more materials, where a first material is a metallic liner, and a second material is a fill metal.FIG.5Bis a cross-sectional illustration of an interconnect structure506that includes a metallic liner508adjacent to the ILD106and a fill metal510adjacent to the metallic liner508, in accordance with an embodiment of the present disclosure. In embodiments, the metallic liner508includes titanium, tantalum ruthenium, nitrides of tantalum (for e.g., tantalum nitride) or nitrides of titanium (for e.g., titanium nitride). In some embodiments, fill metal510includes copper, cobalt, ruthenium, tungsten, molybdenum, or nickel, or an alloy thereof.

The passivation layer504may be formed on uppermost surface506A of the interconnect structure506. In the illustrative embodiment, the passivation layer504is formed on the metallic liner508as well as on the fill metal510. In other embodiments, the passivation layer504is formed on the fill metal510but not on the metallic liner508, such as is shown inFIG.5C. In some such embodiments, the passivation chemistry is chemically selective to the metal, but not to the metallic liner508and leaves the metallic liner508unpassivated.

FIG.6Ais a cross-sectional illustration of the structure inFIG.5Afollowing the formation of a cap structure114. In an embodiment, the cap structure114is formed by an atomic layer deposition (ALD) process, selectively on the surface106A of ILD106. In an embodiment, precursors for formation of the cap structure114do not adhere to the passivation layer504, but adhere to the material of ILD106. In an embodiment, the cap structure114includes silicon and oxygen.

As shown, in an exemplary example, the cap structure114is formed on the ILD surface106A directly adjacent to the passivation layer504. In some embodiments, ILD deposition process may form a cap structure114with rounded edges at top surface114A. In other embodiments, the corners are not rounded as indicated by dashed lines600. In some embodiments, the passivation layer504is removed after formation of cap structure114. In other embodiments, passivation layer504is not removed until a liner is formed on the cap structure114.

FIG.6Bis a cross-sectional illustration of the structure inFIG.5Cfollowing the formation of a cap structure114on the ILD106. In an embodiment, the cap structure114is formed by a process described in association withFIG.6A. In the illustrative embodiment, the cap structure114is formed on the surface106A of the ILD106, but not on the metallic liner508of interconnect structures506and512. In other embodiments, the cap structure114is also formed on the metallic liner508, as indicated by dashed lines602.

FIG.7Ais a cross-sectional illustration of the structure inFIG.6Afollowing the formation of a liner116on top surface114A and on sidewalls114B of the cap structure114. The liner116may be formed immediately after formation of the cap structure114in a same process chamber without breaking vacuum.

In an embodiment, the liner116is deposited by an ALD process. The ALD process forms the liner116on the cap structure114but not on the passivation layer504. In embodiments, the carbon rich surface of the passivation layer504act as a hydrophobic barrier to ALD precursors and co-reactants introduced during formation of the liner116. In an embodiment, the liner116includes oxygen and one or more of Al, Ti, Hf or Zr. The liner116may be deposited to a thickness between 0.7 nm and 2 nm. In some embodiments, the as deposited thickness of the liner116may depend on the choice of material to lower an effective capacitance.

In the illustrative embodiment, the liner116is over but not in contact with the metallic liner508, as illustrated in the enhanced cross-sectional illustration ofFIG.7B. In some such embodiments, the liner116, as shown, is over a portion of interconnect structure108. Liner116has a same or substantially the same features over other portions of interconnect structure108or over interconnect structure110(not shown).

In some embodiments, the passivation layer504is removed after formation of cap structure114. In some such embodiments, a new passivation layer is formed on the interconnect structures108and110prior to formation of liner116.

FIG.8is a cross-sectional illustration of the structure inFIG.6Bfollowing the formation of liner116. In an embodiment, the process to form liner116is the same or substantially the same as the process described in association withFIG.7A. In an exemplary embodiment, the liner116is formed on the cap structure114, including on the top surface114A and on sidewall114B. As shown in the illustration, while forming the liner116on the sidewall114B, the ALD process also form liner116on the metallic liner508.

FIGS.9A-9Drepresent cross-sectional illustrations depicting a series of operations to form interconnect structures above interconnect structures108and110.

FIG.9Ais a cross-sectional illustration of the structure inFIG.8following the formation of an etch stop layer308and ILD306on the etch stop layer308.

Prior to deposition of the etch stop layer308, the passivation layer504is removed from the surface510A of the fill metal510. The passivation layer504may be removed by a plasma etch process or a wet chemical process selective to the liner116and the fill metal510. In the illustrative embodiment, the etch stop layer308is deposited on the liner116and on uppermost surfaces510A of the fill metal510of each interconnect structure506and512. As shown, the etch stop layer308is not formed on the metallic liner508. The etch stop layer308, may be substantially conformal with the liner116. An ALD process, for example, may be utilized to conformally deposit a 3 nm-5 nm thick etch stop layer308. In the illustrative embodiment, the etch stop layer308includes silicon, nitrogen and one or more of oxygen or carbon. In some embodiments, the etch stop layer308includes silicon and nitrogen and is doped with less than 15 atomic percent of carbon.

ILD306may be blanket deposited on the etch stop layer308. In embodiments, the ILD306may be self-planarizing during the deposition process or is planarized by a chemical mechanical polish process after deposition. In an embodiment, the ILD306is deposited by a chemical vapor deposition process (CVD), physical vapor deposition (PVD) process or a plasma enhanced chemical vapor deposition (PECVD) process.

FIG.9Bis a cross-sectional illustration of the structure inFIG.9Afollowing the formation of a mask900on an uppermost surface306A of the ILD306. In an embodiment, the mask900is formed by a lithographic process and includes a photoresist material. The mask900includes openings901and903to expose portions of the ILD306to be etched. In some embodiments, the mask is designed to form via openings or line openings. The openings901and903are designed to have a width that facilitates a minimum dimension of an opening, formed by an etch process, in the ILD306and in the etch stop layer308. It is to be appreciated that the cap structure114and the liner116advantageously provide a step height, H1, relative to the surface510A or106A to enhance alignment (indicated by dashed lines904) between mask900and interconnect structures506and512.

FIG.9Cis a cross-sectional illustration of the structure inFIG.9Bfollowing the formation of openings905and907in the ILD306. In an embodiment, a plasma etch process is utilized to etch ILD306and form openings905and907. In the illustrative embodiment, the openings905and907each have tapered profiles. In the illustrative embodiment, the plasma etch process is halted after the etch stop layer308on surface510A is exposed. As shown, portions of the etch stop layer308adjacent to the liner116are substantially unetched during etching of the ILD306.

FIG.9Dis a cross-sectional illustration of the structure inFIG.9Cfollowing the process to etch exposed portions of the etch stop layer308within the openings905and907. In an embodiment, a plasma etch process is utilized to etch and remove the etch stop layer308adjacent to the liner116and from surface510A, to expose surface510A, as shown. In exemplary embodiments, the liner116is not etched laterally during the plasma etch process. In some embodiments, the mask900may be removed prior to etching the etch stop layer308to avoid exposing surface510A to an oxygen based chemistry for removal of photoresist material.

FIG.9Eis a cross-sectional illustration of the structure inFIG.9Dfollowing the formation of interconnect structure908and interconnect structure910in the openings905and907, respectively to form an integrated circuit structure920. In some embodiments, mask900is removed after exposing the surface510A. A conductive material to form interconnect structures908and910may be deposited into the openings905and907, on the surface510A, adjacent to liner116, portions of etch stop layer308, adjacent to ILD306, and on uppermost surface306A. In an embodiment, the conductive material includes electroplating copper after formation of a metallic liner (such as a metallic liner508described in association withFIG.5B) in the openings905and907. In other examples, one or more conductive materials, such as tungsten, cobalt or ruthenium are blanket deposited by a CVD or an ALD process after formation of a metallic liner (such as a metallic liner508described in association withFIG.5B). After deposition, the conductive material may be removed from uppermost surface306A by a CMP process to form interconnect structures908and910.

In some embodiments there is misalignment between mask900and the interconnect structure506and512. In some such embodiments, the openings905and907may expose portions of the liner116on top surface114A of cap structure114, as shown inFIG.10A. As shown, the process of etching etch stop layer308exposes liner116on the top surface114A of cap structure114. In some embodiments, portion of etch stop layer308that is masked by ILD306, remains on the uppermost surface510A. As shown, the remaining portion of etch stop layer116extends from opening905, under the ILD306to opening907. In exemplary embodiments, the liner116is not etched during the process to form openings905and907. As shown, liner116on top surface114A is exposed immediately after etching portions of etch stop layer308(indicated by dashed lines912). In some embodiments, during the process to over etch and remove etch stop layer308from portions adjacent to liner portion116A, the liner116is unetched. In the illustrative embodiment, liner116has an adequate thickness and provides sufficient etch selectivity to remain intact during the process to completely etch openings905and907, as shown.

In other embodiments portions of the liner116may be eroded after etching of etch stop layer308. In some such embodiments, the liner116remain sufficiently intact, adjacent to the cap structure114, as shown inFIG.10B.FIG.10Bis an enhanced cross sectional illustration of a portion909of the structure inFIG.10A, in embodiments where etching the etch stop layer308also etches portions of the liner116. In the illustrative embodiment, a portion116A of the liner116(within dashed lines914) that is not covered by etch stop layer308may have a reduction in thickness compared to portion116B of the liner116that are covered by etch stop layer308. In some such embodiments, it is to be appreciated that liner116adequately protects interface915between interconnect structure506and ILD106. In some embodiments, a rounded top edge portion114C of the cap structure114can be exposed if portions of the liner116A are etched. However in some such embodiments, liner portion116A directly adjacent to sidewall surfaces114B are not etched and ILD106is not exposed.

FIG.11is a cross-sectional illustration of the structure inFIG.10Afollowing the formation of interconnect structures302and304in the openings905and907, respectively. In an embodiment, the process of forming interconnect structures302and304is substantially the same as the process described to form interconnect structures908and910, in association withFIG.9E. In the illustrative embodiment, interconnect structures302and304have one or more features as described inFIG.3A, for example, interconnect structures302and304are adjacent to liner116and on at least a portion of interconnect structures108and110, respectively.

FIG.12illustrates a system1200which includes access transistor1201coupled with a memory device through an integrated circuit structure, discussed herein. Referring again toFIG.12in an embodiment, the transistor1201is on a substrate1202and has a gate1203, a source region1204, and a drain region1206. In the illustrative embodiment, an isolation1208is adjacent to the source region1204, drain region1206and portions of the substrate1202. In some implementations of the disclosure, such as is shown, a pair of sidewall spacers1210are on opposing sides of the gate1203.

The transistor1201further includes a source contact1212above and electrically coupled to the source region1204, drain contact1214above and electrically coupled to the drain region1206and a gate contact1216above and electrically coupled to the gate1203, as is illustrated inFIG.12. The transistor1201also includes dielectric1218adjacent to the gate1203, source region1204, drain region1206, isolation1208, sidewall spacers1210, source contact1212, drain contact1214and gate contact1216.

In an embodiment, the system1200further includes a battery and antenna1250coupled to the transistor1201.

In the illustrative embodiment, the integrated circuit structure1221includes one or more features of the integrated circuit structures100and920described above. Referring again toFIG.12, an interconnect structure506, within interconnect level102, is coupled with the drain contact1214. Interconnect level102may include other integrated circuit device structures (not shown). An interconnect structure302in an interconnect level112is coupled with interconnect structure506. The interconnect level112includes a cap structure114, liner116and an etch stop layer308on the liner116. Lowermost portions of interconnect structure302is adjacent to liner116. A memory device1220is coupled with interconnect structure302. In the illustrative embodiment, the memory device1220is above the interconnect structure302. In embodiments memory device1220includes a filamentary based resistive random access memory (RRAM) device, where the RRAM device includes a switching layer and an oxygen exchange layer between a pair of electrodes where a lower most electrode is in contact with the interconnect structure302. In other embodiments, the memory device1220includes a magnetic tunnel junction (MTJ) device that includes a free magnet and a fixed magnet and a MgO tunnel barrier in between. The MTJ device may further include one or more pinning layers and barrier layers between the fixed magnet and the interconnect structure302.

In other embodiments, one or more layers of interconnects exist between conductive interconnect506and the drain contact1214. The memory device1220is also electrically coupled with a conductive interconnect1222. The conductive interconnect1222includes a liner layer1222A and a fill metal1222B. In embodiments, the liner layer1222A and fill metal include materials that are the same or substantially the same as the material of the metallic liner508and fill metal510described in association withFIG.5B.

Referring again toFIG.12, in an embodiment, the underlying substrate1202represents a surface used to manufacture integrated circuits. Suitable substrate1202includes a material such as single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as substrates formed of other semiconductor materials. In some embodiments, the substrate1202may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates.

In an embodiment, the transistor1201associated with substrate1202are metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), fabricated on the substrate1202. In some embodiments, the transistor1201is an access transistor1201. In various implementations of the disclosure, the transistor1201may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors.

In some embodiments, gate1203includes at least two layers, a gate dielectric layer1203A and a gate electrode1203B. The gate dielectric layer1203A may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (SiO2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer1203A to improve its quality when a high-k material is used.

The gate electrode1203B of the access transistor1201of substrate1202is formed on the gate dielectric layer1203A and may consist of at least one P-type work function metal or N-type work function metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode1203B may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a conductive fill layer.

For a PMOS transistor, metals that may be used for the gate electrode1203B include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a work function that is between about 4.6 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a work function that is between about 3.6 eV and about 4.2 eV.

In some implementations, the gate electrode may consist of a “U”-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode1203B may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode1203B may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

The sidewall spacers1210may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers include deposition and etching process operations. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack. As shown, the source region1204and drain region1206are formed within the substrate adjacent to the gate stack of each MOS transistor. The source region1204and drain region1206are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source region1204and drain region1206. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate1202may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source region1204and drain region1206. In some implementations, the source region1204and drain region1206may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source region1204and drain region1206may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source region1204and drain region1206.

In an embodiment, the source contact1212, the drain contact1214and gate contact1216each include a multi-layer stack. In an embodiment, the multi-layer stack includes one or more of Ti, Ru or Al and a conductive cap on the one or more of Ti, Ta, Ru or Al. The conductive cap may include a material such as W or Cu.

In an embodiment, the interconnect1222includes a liner layer and a fill metal on the liner layer, as shown. In an embodiment, the liner layer includes one or more of Ti, Ta, Ru or Al. The fill metal may include a material such as W or Cu.

The isolation1208and dielectric1218may each include any material that has sufficient dielectric strength to provide electrical isolation. Materials may include silicon and one or more of oxygen, nitrogen or carbon such as silicon dioxide, silicon nitride, silicon oxynitride, carbon doped nitride or carbon doped oxide.

FIG.13illustrates a computing device1300in accordance with embodiments of the present disclosure. As shown, computing device1300houses a motherboard1302. Motherboard1302may include a number of components, including but not limited to a processor1301and at least one communications chip1304or1305. Processor1301is physically and electrically coupled to the motherboard1302. In some implementations, communications chip1305is also physically and electrically coupled to motherboard1302. In further implementations, communications chip1305is part of processor1301.

Depending on its applications, computing device1300may include other components that may or may not be physically and electrically coupled to motherboard1302. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset1306, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

Communications chip1305enables wireless communications for the transfer of data to and from computing device1300. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communications chip1305may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 1301.11 family), WiMAX (IEEE 1301.11 family), long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. Computing device1300may include a plurality of communications chips1304and1305. For instance, a first communications chip1305may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communications chip1304may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

Processor1301of the computing device1300includes an integrated circuit die packaged within processor1301. In some embodiments, the integrated circuit die of processor1301includes one or more, non-volatile memory devices, and transistors coupled with capacitors and memory devices and integrated circuit structures such integrated circuit structure100. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

Communications chip1305also includes an integrated circuit die packaged within communication chip1305. In another embodiment, the integrated circuit die of communications chips1304,1305includes one or more, non-volatile memory devices, and transistors coupled with capacitors and memory devices and integrated circuit structures such integrated circuit structure100. Depending on its applications, computing device1300may include other components that may or may not be physically and electrically coupled to motherboard1302. These other components may include, but are not limited to, volatile memory (e.g., DRAM)1307,1308, non-volatile memory (e.g., ROM)1310, a graphics CPU1312, flash memory, global positioning system (GPS) device1313, compass1314, a chipset1306, an antenna1316, a power amplifier1309, a touchscreen controller1311, a touchscreen display1317, a speaker1315, a camera1303, and a battery1318, as illustrated, and other components such as a digital signal processor, a crypto processor, an audio codec, a video codec, an accelerometer, a gyroscope, and a mass storage device (such as hard disk drive, solid state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth), or the like. In further embodiments, any component housed within computing device1300and discussed above may contain a stand-alone integrated circuit memory die that includes one or more arrays of NVM devices.

In various implementations, the computing device1300may be a laptop, a netbook, a notebook, an Ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device1300may be any other electronic device that processes data.

FIG.14illustrates an integrated circuit (IC) structure1400that includes one or more embodiments of the disclosure. The integrated circuit (IC) structure1400is an intervening substrate used to bridge a first substrate1402to a second substrate1404. The first substrate1402may be, for instance, an integrated circuit die. The second substrate1404may be, for instance, a memory module, a computer mother, or another integrated circuit die. Generally, the purpose of an integrated circuit (IC) structure1400is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an integrated circuit (IC) structure1400may couple an integrated circuit die to a ball grid array (BGA)1407that can subsequently be coupled to the second substrate1404. In some embodiments, the first substrate1402and the second substrate1404are attached to opposing sides of the integrated circuit (IC) structure1400. In other embodiments, the first substrate1402and the second substrate1404are attached to the same side of the integrated circuit (IC) structure1400. And in further embodiments, three or more substrates are interconnected by way of the integrated circuit (IC) structure1400.

The integrated circuit (IC) structure1400may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the integrated circuit (IC) structure may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials.

The integrated circuit (IC) structure may include metal interconnects1408and vias1410, including but not limited to through-silicon vias (TSVs)1412. The integrated circuit (IC) structure1400may further include embedded devices1414, including both passive and active devices. Such embedded devices1414include capacitors, decoupling capacitors one or more transistors coupled with memory devices through integrated circuit structure100, such as transistor1201having one or more features described in association withFIG.12. Referring again toFIG.14, the integrated circuit (IC) structure1400may further include embedded devices1414such as one or more resistive random-access devices, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radiofrequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the integrated circuit (IC) structure1400.

Thus, one or more embodiments of the present disclosure relate to integrated circuit structure including cap structure and a liner between two levels of interconnect structures such as integrated circuit structure100,300as described above. The integrated circuit structure100may be used in various integrated circuit applications.

In a first example, an integrated circuit structure includes a first interconnect level including a first dielectric between a pair of interconnect structures and a second interconnect level above the first interconnect level. The second interconnect level includes a cap structure including a second dielectric on the first dielectric, where the cap structure includes a top surface and a sidewall surface. A liner including a third dielectric is on the top surface and on the sidewall surface.

In second examples, for any of first examples, the first dielectric includes silicon, oxygen and less than 1 atomic percent of carbon and the second dielectric includes silicon and oxygen.

In third examples, for any of the first through second examples, the second dielectric further includes less than 1 atomic percent of aluminum.

In fourth examples, for any of the first through third examples, the third dielectric includes oxygen and one of aluminum, hafnium, zirconium or titanium and where the liner has thickness between 0.7 nm and 2 nm.

In fifth examples, for any of the first through fourth examples, liner is in contact with uppermost surfaces of individual ones of the pair of interconnect structures.

In sixth examples, for any of the first through fifth examples, the second dielectric has a vertical thickness as measured from an uppermost surface of the first dielectric, where the vertical thickness is between 3 nm and 6 nm

In seventh examples, for any of the first through sixth examples, the cap structure extends onto uppermost surfaces of individual ones of the pair of interconnect structures, and where the liner is in contact with an uppermost surface of each interconnect.

In eighth examples, for any of the first through seventh examples, the cap structure has a first lateral thickness, where the liner has a second lateral thickness, and where the first dielectric has a third lateral thickness and where the third lateral thickness is equal to a combined sum of the first lateral thickness and two times a sum of the second lateral thickness

In ninth examples, for any of the first through eight examples, the first pair of interconnect structures includes a conductive liner adjacent the first dielectric and a fill metal on the conductive liner and where liner is over the conductive liner.

In tenth examples, for any of the first through ninth examples, the pair of interconnect structures is a first pair of interconnect structures and the second interconnect level further includes a second pair of interconnect structures, where individual ones of the second pair of interconnect structures is on at least a portion of a corresponding individual ones of the first pair of interconnect structures. An etch stop layer including a fourth dielectric is on least a portion of the liner and a fifth dielectric is on the etch stop layer and between the pair of second interconnect structures.

In eleventh examples, for any of the first through tenth examples, the liner is in contact with the first pair of interconnect structures and the second pair of interconnect structures.

In twelfth examples, for any of the first through eleventh examples, the etch stop layer is between the liner and the fifth dielectric, but not between the liner and second pair of interconnect structures.

In thirteenth examples, for any of the first through twelfth examples, the liner includes a first portion between the cap structure and the etch stop layer and a second portion between the cap structure and at least one interconnect structure in the second pair of interconnect structures, where the first portion includes a first thickness and the second portion includes a second thickness and where the second thickness is less than the first thickness.

In a fourteenth example, for any of the first through thirteenth examples, the etch stop layer is between an individual one of the second pair of interconnect structures and the fifth dielectric.

In fifteenth example, a method of forming an integrated circuit structure includes receiving a workpiece including a first dielectric between a pair of interconnects. The method further includes passivating uppermost surfaces of the individual ones of the pair of interconnects by selectively forming a passivation layer on the uppermost surfaces but not on the first dielectric and selectively growing a second dielectric on the first dielectric. The method further includes selectively growing a liner on the second dielectric but not on the uppermost surfaces of the individual ones of the pair of interconnects and removing the passivation layer.

In sixteenth examples, for any of the fifteenth examples, forming the passivation layer includes forming the passivation layer on a fill metal of the individual ones of the pair of interconnects but not on a metallic liner laterally between the first dielectric and the fill metal.

In seventeenth examples, for any of the fifteenth through sixteenth examples, depositing the second dielectric includes depositing the second dielectric on the first dielectric and not on the metallic liner.

In eighteenth examples, for any of the fifteenth through seventeenth examples, growing the liner includes growing the liner on sidewalls of the second dielectric and over the metallic liner, but not in contact with the metallic liner.

In nineteenth example, a system includes a processor, a radio transceiver coupled to the processor, where the transceiver includes a transistor. The transistor includes a drain contact coupled to a drain, a source contact coupled to a source and a gate contact coupled to a gate. An integrated circuit structure is coupled with the drain contact. The integrated circuit structure includes a first interconnect level including a first dielectric between a pair of interconnect structures and a second interconnect level above the first interconnect level. The second interconnect level includes a cap structure including a second dielectric on the first dielectric, where the cap structure includes a top surface and a sidewall surface. A liner including a third dielectric is on the top surface and on the sidewall surface. The integrated circuit structure further includes a second interconnect structure on at least a portion of the first interconnect structure, an etch stop layer including a fourth dielectric on least a portion of the liner, and a fifth dielectric on the etch stop layer and adjacent the second interconnect structure. A memory device is coupled with the second interconnect structure.

In twentieth example, for any of the twenty first examples, system further includes a battery and an antenna coupled with the transistor, and where the memory device is a resistive random access memory device or a magnetic tunnel junction device.