Patent ID: 12190983

DETAILED DESCRIPTION

Embodiments provide a voltage generation circuit in which temperature-dependent characteristics are adjusted.

In general, according to one embodiment, a voltage generation circuit generates a first current indicating a first temperature-dependent characteristic in which a current value thereof changes with a predetermined change in temperature, and a second current indicating a second temperature-dependent characteristic different from the first temperature-dependent characteristic. The voltage generation circuit includes a first variable resistor and a second variable resistor connected in series. The second current flows through the first variable resistor, and a third current having a current value that is based on a difference between a current value of the first current and a current value of the second current, flows through the second variable resistor.

Hereinafter, a voltage generation circuit according to an embodiment will be described in detail with reference to the drawings. In the following description, elements having substantially the same functions and configurations are denoted by the same reference numerals, and the description will be repeated only when necessary. Each embodiment described below exemplifies an apparatus and a method for embodying the technical idea of this embodiment. The technical idea of the embodiments is not limited to the material, shape, structure, arrangement, and the like of the elements described later. The technical idea of the embodiments may be obtained by adding various modifications to the scope of the claims.

The following embodiments may be combined with one another as long as no technical contradiction occurs.

1. First Embodiment

A memory system in which a voltage generation circuit according to the embodiments is implemented will be described with reference toFIG.1. The memory system includes, for example, a nonvolatile memory, which is a semiconductor memory device, and a memory controller that controls the nonvolatile memory.

1-1. Configuration of Semiconductor Memory Device

A configuration example of a semiconductor memory device according to the first embodiment will be described with reference toFIG.1. As shown inFIG.1, a semiconductor memory device10includes a memory cell array21, an input/output circuit22, a ZQ calibration circuit23, a logic control circuit24, a temperature sensor25, a register26, a sequencer27, a voltage generation circuit28, a driver set29, a row decoder30, a sense amplifier31, an input/output pad group32, a ZQ calibration pad33, and a logic control pad group34.

The memory cell array21includes a plurality of nonvolatile memory cells associated with word lines and bit lines.

The input/output circuit22transmits and receives data signals (DQ<0> to DQ<7>), a data strobe signal (DQS), and an inversion signal (BDQS) thereof to and from the memory controller. The input/output circuit22transmits commands and addresses in the data signals to the register26. The input/output circuit22transmits and receives write data and read data to and from the sense amplifier31.

The ZQ calibration circuit23calibrates an output impedance of the semiconductor memory device10based on a reference resistance via the ZQ calibration pad33.

The logic control circuit24receives, for example, a chip enable signal (BCE), a command latch enable signal (CLE), an address latch enable signal (ALE), a write enable signal (BWE), a read enable signal (RE), an inversion signal (BRE) of the read enable signal, and a write protect signal (BWP) from the memory controller. The logic control circuit24transmits a ready busy signal (BRB) to the memory controller to notify a state of the semiconductor memory device10to the outside.

The temperature sensor25has a function of measuring a temperature inside the semiconductor memory device10. The temperature sensor25transmits information on the measured temperature to the sequencer27. The temperature sensor25is provided at any location inside the semiconductor memory device10within a range in which a temperature that can be deemed to be a temperature of the memory cell array21can be measured.

The register26stores the commands and the addresses. The register26transmits the addresses to the row decoder30and the sense amplifier31, and transmits the commands to the sequencer27.

The sequencer27receives the commands and controls the entire semiconductor memory device10according to a sequence based on the received commands. The sequencer27transmits information on the temperature received from the temperature sensor25to the memory controller via the input/output circuit22.

The voltage generation circuit28generates, based on an instruction from the sequencer27, a voltage necessary for operations on data such as a write operation, a read operation, and an erase operation. Details will be described later, and the voltage generation circuit28generates an appropriate voltage with respect to the temperature measured by the temperature sensor25when generating the voltage. The voltage generation circuit28supplies the generated voltage to the driver set29.

The driver set29includes a plurality of drivers, and supplies the voltage from the voltage generation circuit28to the row decoder30and the sense amplifier31based on the addresses from the register26. The driver set29supplies the voltage to the row decoder30based on, for example, a row address in the addresses.

The row decoder30receives the row address in the addresses from the register26, and selects a row of memory cells based on the row address. The voltage from the driver set29is applied to the selected row of memory cells via the row decoder30.

At the time of a data read operation, the sense amplifier31senses read data read from a memory cell to a bit line, and transmits the sensed read data to the input/output circuit22. At the time of a data write operation, the sense amplifier31transmits write data written via the bit line to the memory cell. The sense amplifier31receives a column address in the addresses from the register26, and outputs a column of data based on the column address.

The data signals DQ<0> to DQ<7>, the signal DQS, and the signal BDQS received from the memory controller are transmitted to the input/output circuit22via the input/output pad group32. The data signals DQ<0> to DQ<7> transmitted from the input/output circuit22are transmitted to the outside of the semiconductor memory device5via the input/output pad group32.

One end of the ZQ calibration pad33is connected to the reference resistance, and the other end thereof is connected to the ZQ calibration circuit23.

The signals BCE, CLE, ALE, BWE, RE, BRE, and BWP received from the memory controller are transmitted to the logic control circuit24via the logic control pad group34. The signal BRB transmitted from the logic control circuit24is transmitted to the memory controller via the logic control pad group34.

1-2. Configuration of Voltage Generation Circuit

FIG.2is a circuit diagram showing a configuration of the voltage generation circuit according to the embodiment. In the following description, a voltage having a temperature-dependent characteristic in which the voltage increases with an increase in temperature is referred to as a “voltage VPTAT”. A voltage having a temperature-dependent characteristic in which the voltage does not change with a change in temperature is referred to as a “voltage VFLAT”. A voltage having a temperature-dependent characteristic in which the voltage decreases with an increase in temperature is referred to as a “voltage VCTAT”.

A current that is generated based on the voltage VPTATand that has a temperature-dependent characteristic in which a current value thereof increases with an increase in temperature is referred to as a “current IPTAT”. A current that is generated based on the voltage VFLATand that has a temperature-dependent characteristic in which a current value thereof does not change with a change in temperature is referred to as a “current IFLAT”. A current that is generated based on the voltage VCTATand that has a temperature-dependent characteristic in which a current value thereof decreases with an increase in temperature is referred to as a “current ICTAT”.

In the following description, a current supplied to a circuit (e.g., a current input to an input terminal provided in the circuit) may be the current IPTATor the current ICTAT. Thus, when it is not necessary to particularly distinguish the current IPTATfrom the current ICTAT, the current may be referred to as a “current IP/C”.

The voltage generation circuit28includes a first current generation circuit G1, a second current generation circuit G2, a plurality of current mirror circuits, a first variable resistor R3, a second variable resistor R4, an output terminal VOUT, a first power supply line VDD, and a second power supply line VSS. The first current generation circuit G1, the second current generation circuit G2, and the plurality of current mirror circuits are provided between the first power supply line VDD and the second power supply line VSS.

A high voltage (which may be referred to as a first power supply voltage) is supplied to the first power supply line VDD. A low voltage (which may be referred to as a second power supply voltage) is supplied to the second power supply line VSS. In the following embodiments, the second power supply line VSS is shown as a ground potential, but any fixed voltage may be supplied.

When the voltage VFLATis input to an input terminal of the first current generation circuit G1, the first current generation circuit G1generates the current IFLAT. A voltage value of the voltage input to the input terminal of the first current generation circuit G1is V1. A resistance value of a resistance element of the first current generation circuit G1is R1.

When the voltage VPTATor the voltage VCTATis input to an input terminal of the second current generation circuit G2, the second current generation circuit G2generates the current IPTATor the current ICTAT(the current IP/C). A voltage value of the voltage input to the input terminal of the second current generation circuit G2is V2. A resistance value of a resistance element of the second current generation circuit G2is R2.

The configurations of the first current generation circuit G1and the second current generation circuit G2are merely examples, and are not limited to the configurations shown inFIG.2. The first current generation circuit G1may be any circuit as long as the circuit can provide a current (the current IFLAT) having a temperature-dependent characteristic in which a current value thereof does not change with a change in temperature, and may be replaced with another circuit. The second current generation circuit G2may be any circuit as long as the circuit can provide a current (the current IP/C) having a temperature-dependent characteristic in which a current value thereof changes with a change in temperature, and may be replaced with another circuit.

In other words, the voltage generation circuit28generates the current IPTATor the current ICTAThaving a temperature-dependent characteristic (which is referred to below as a first temperature-dependent characteristic) in which a current value thereof changes with a predetermined change in temperature, and the current IFLAThaving a temperature-dependent characteristic (which is referred to below as a second temperature-dependent characteristic) different from the first temperature-dependent characteristic. The first temperature-dependent characteristic is a temperature-dependent characteristic in which the current value increases (the current IPTAT) or decreases (the current ICTAT) with an increase in temperature. The second temperature-dependent characteristic is a temperature-dependent characteristic in which the current value does not change (the current IFLAT) with a change in temperature. The current IFLATmay have a temperature-dependent characteristic in which the current does not change at all with a change in temperature, and may have a temperature-dependent characteristic in which a change thereof is negligibly small as compared with those of the current IPTATand the current ICTAT.

Each current mirror circuit includes a pair of transistors to which respective gate terminals are connected. The plurality of current mirror circuits shown inFIG.2include transistors T1to T10. Sizes of the transistors are the same. The transistor T7is denoted by “×2” to indicate that two transistors are connected in parallel. The transistors T1to T3, T5, T7, and T9are p-type transistors. The transistors T4, T6, T8, and T10are n-type transistors.

The first current generation circuit G1and the transistor T1are connected in series between the first power supply line VDD and the second power supply line VSS. The second current generation circuit G2and the transistor T2are connected in series between the first power supply line VDD and the second power supply line VSS. The transistors T3and T4are connected in series between the first power supply line VDD and the second power supply line VSS. The transistors T5and T6are connected in series between the first power supply line VDD and the second power supply line VSS. The transistors T7and T8are connected in series between the first power supply line VDD and the second power supply line VSS. The transistor T9, the second variable resistor R4, and the first variable resistor R3are connected in series between the first power supply line VDD and the second power supply line VSS. The transistors T9and T10are connected in series between the first power supply line VDD and the second power supply line VSS.

A node between the first variable resistor R3and the second variable resistor R4is referred to as a first node N1. A node between the transistor T9and the second variable resistor R4is referred to as a second node N2. The first variable resistor R3and the second variable resistor R4connected in series with each other and the transistor T10are connected in parallel between the second node N2(or the output terminal VOUT) and the second power supply line VSS.

A pair of transistors T1and T5and a pair of transistors T1and T7each form a current mirror circuit. When a current generated by the first current generation circuit G1and flowing through the transistor T1is the current IFLAT, a current flowing through the transistor T5is also the current IFLAT. When a current flowing through the transistor T1is the current IFLAT, a current flowing through the transistor T7is a current (2×IFLAT) that is twice the current IFLAT.

In the present embodiment, the current flowing through the transistor T7is a current that is twice the current IFLAT, but the present disclosure is not limited to this configuration. For example, the current flowing through the transistor T7may be a current (n×IFLAT) that is n times the current IFLAT(n is a positive number excluding 1).

A value of n is not limited to an integer and may include a decimal. In the present embodiment, since the number of transistors T7is twice the number of transistors T1, the current flowing through the transistor T7is a current that is twice the current IFLAT. By adjusting a ratio of the number of transistors T7to the number of transistors T1, the value of n can include a decimal. For example, when two transistors are connected in parallel as the transistor T1and five transistors are connected in parallel as the transistor T7, n is 2.5, and the current flowing through the transistor T7is a current (2.5×IFLAT) that is 2.5 times the current IFLAT.

A pair of transistors T2and T3and a pair of transistors T2and T9each form a current mirror circuit. When a current generated by the second current generation circuit G2and flowing through the transistor T2is the current IP/C, currents respectively flowing through the transistors T3and T9are also the current IP/C.

When a current flowing through the transistor T3is the current IP/C, a current flowing through the transistor T4connected in series with the transistor T3is also the current IP/C. A pair of transistors T4and T8form a current mirror circuit. When the current flowing through the transistor T4is the current IP/C, a current flowing through the transistor T8is also the current IP/C.

When a current flowing through the transistor T5is the current IFLAT, a current flowing through the transistor T6connected in series with the transistor T5is also the current IFLAT. A pair of transistors T6and T10form a current mirror circuit. When the current flowing through the transistor T6is the current IFLAT, a current flowing through the transistor T10is also the current IFLAT.

FIG.3is a conceptual diagram showing the configuration of the voltage generation circuit according to the embodiment. InFIG.3, only the first variable resistor R3, the second variable resistor R4, and the output terminal VOUTamong circuit elements shown inFIG.2are shown, and other circuit elements are shown as input terminals and output terminals in the circuit shown inFIG.3.

The transistor T7inFIG.2corresponds to an input terminal VIN7inFIG.3, the transistor T8inFIG.2corresponds to an output terminal VOUT8inFIG.3, the transistor T9inFIG.2corresponds to an input terminal VIN9inFIG.3, and the transistor T10inFIG.2corresponds to an output terminal VOUT10inFIG.3. The current 2×IFLATis input from the input terminal VIN7, the current IP/Cis input from the input terminal VIN9, the current IP/Cis output to the output terminal VOUT8, and the current IFLATis output to the output terminal VOUT10.

As shown inFIG.3, the first node N1is a node between the first variable resistor R3, the second variable resistor R4, the input terminal VIN7, and the output terminal VOUT8. The second node N2is a node between the second variable resistor R4, the input terminal VIN9, the output terminal VOUT, and the output terminal VOUT10. Referring toFIG.2, since the second node N2is connected to the first power supply line VDD via the transistor T9, it can be said that the second node N2is a node between the second variable resistor R4, the output terminal VOUT, and the first power supply line VDD.

The voltage generation circuit28includes a first path PAS1, a second path PAS2, and a third path PAS3. The first path PAS1is a path from the input terminal VIN7(or the first power supply line VDD) to the first node N1without passing through the second variable resistor R4. The second path PAS2is a path from the second node N2to the output terminal VOUT10(or the second power supply line VSS) without passing through the second variable resistor R4. The third path PAS3is a path from the first node N1to the output terminal VOUT8(or the second power supply line VSS) without passing through the first variable resistor R3. A current flowing through the first path PAS1is 2×IFLAT, a current flowing through the second path PAS2is the current IFLAT, and a current flowing through the third path PAS3is the current IP/C.

1-3. Output of Voltage Generation Circuit

As described above, since the current flowing through the transistor T7(the current input from the input terminal VIN7) is “2×IFLAT”, the current flowing through the transistor T8(the current output to the output terminal VOUT8) is “IP/C”, the current flowing through the transistor T9(the current input from the input terminal VIN9) is “IP/C”, and the current flowing through the transistor T10(the current output to the output terminal VOUT10) is “IFLAT”, a voltage of the output terminal VOUTis calculated as in the following Equation (1-1).

VOUT=R3·(IP/C-IFLAT+2·IFLAT-IP/C)+R4·(IP/C-IFLAT)=R3·IFLAT+R4·(IP/C-IFLAT)(1-1)

Referring toFIG.2, “IP/C” and “IFLAT” can be expressed by the following Equation (1-2).

IP/C=V2R2,(1-2)IFLAT=V1R1

By substituting Equation (1-2) into Equation (1-1), VOUTcan be expressed as the following Equation (1-3).

VOUT=R3R1·V1+R4·(V2R2-V1R1)(1-3)

As shown in Equation (1-1), a current flowing through the first variable resistor R3is the current IFLAT, and a current flowing through the second variable resistor R4is a current based on a difference between the current IP/Cand the current IFLAT. As shown in Equation (1-3), when V2/R2=V1/R1(that is, when IP/C=current IFLAT) at a certain temperature Temp1, the term of R4is zero.

1-4. Electrical Characteristics of Voltage Generation Circuit

FIG.4is a diagram showing electrical characteristics of the voltage generation circuit according to the embodiment. As shown inFIG.4, at the temperature Temp1(for example, 25° C.), a value of VOUTchanges in proportion to a value of the first variable resistor R3, and a gradient of the output voltage VOUTwith respect to the temperature changes based on VOUT=(R3/R1)×V1by a value of the second variable resistor R4. InFIG.4, by increasing the value of the second variable resistor R4, the gradient of the output voltage VOUTis larger than a slope of “Initial”.

As described above, an absolute value of the output voltage VOUTat the temperature Temp1can be adjusted by the value of the first variable resistor R3, and a temperature gradient of the output voltage VOUTcan be adjusted by the value of the second variable resistor R4. Since the values of the first variable resistor R3and the second variable resistor R4can be independently controlled, the absolute value of the output voltage VOUTand the temperature gradient of the output voltage VOUTcan be independently adjusted.

In the present embodiment, the transistor T7has a configuration in which two transistors are connected in parallel, but the present disclosure is not limited to this configuration. For example, the number of transistors connected in parallel may be three or more. Alternatively, an L length of the transistor T7(a distance between a source and a drain) and an L length of the transistor T1are the same, and a W length (a width in a direction orthogonal to an L length direction) of the transistor T7may be n times a W length of the transistor T1. In the present embodiment, since n=2, a coefficient of “R3·IFLAT” in Equation (1-1) is 1, when the value of n is changed, only the coefficient changes, and the above-mentioned effect can be obtained.

In the present embodiment, the current IFLATgenerated by the first current generation circuit G1does not change with a change in temperature, but the first current generation circuit G1may generate a current varying as the change in temperature, such as the current IP/C. However, in this case, a temperature-dependent characteristic of a current generated by the first current generation circuit G1is different from a temperature-dependent characteristic of the current IP/Cgenerated by the second current generation circuit G2. In such a case as well, since IFLATis replaced with IP/C′ in Equation (1-1), the above-mentioned effect can be obtained.

2. Second Embodiment

A voltage generation circuit according to a second embodiment will be described with reference toFIGS.5and6. A voltage generation circuit28A according to the second embodiment is similar to the voltage generation circuit28according to the first embodiment. In the following description, a description of the same configuration as that of the voltage generation circuit28according to the first embodiment will be omitted, and differences from the voltage generation circuit28will be mainly described.

2-1. Configuration of Voltage Generation Circuit

FIG.5is a circuit diagram showing a configuration of the voltage generation circuit according to the embodiment. As shown inFIG.5, in the voltage generation circuit28A, transistors T11to T13are provided instead of the transistors T5to T10that are provided in the voltage generation circuit28shown inFIG.2. The transistors T11and T12are p-type transistors. The transistor T13is an n-type transistor.

The transistor T11is provided between the first power supply line VDD and the first node N1. The transistor T12, the second variable resistor R4, and the first variable resistor R3are connected in series between the first power supply line VDD and the second power supply line VSS. The transistors T12and T13are connected in series between the first power supply line VDD and the second power supply line VSS. The first variable resistor R3and the second variable resistor R4connected in series with each other and the transistor T13are connected in parallel between the second node N2(or the output terminal VOUT) and the second power supply line VSS.

A pair of transistors T1and T12, a pair of transistors T2and T11, and a pair of transistors14and T13each form a current mirror circuit. In this configuration, a current flowing through the transistor T11is the current IP/C, a current flowing through the transistor T12is the current IFLAT, and a current flowing through the transistor T13is the current IP/C.

FIG.6is a conceptual diagram showing the configuration of the voltage generation circuit according to the embodiment. The transistor T11inFIG.5corresponds to an input terminal VIN11inFIG.6, the transistor T12inFIG.5corresponds to an input terminal VIN12inFIG.6, and the transistor T13inFIG.5corresponds to an output terminal VOUT13inFIG.6. The current IP/Cis input from the input terminal VIN11, the current IFLATis input from the input terminal VIN12, and the current IP/Cis output to the output terminal VOUT13.

As shown inFIG.6, the first node N1is a node between the first variable resistor R3, the second variable resistor R4, and the input terminal VIN11. The second node N2is a node between the second variable resistor R4, the input terminal VIN12, the output terminal VOUT, and the output terminal VOUT13. Referring toFIG.5, since the second node N2is connected to the first power supply line VDD via the transistor T12, it can be said that the second node N2is a node between the second variable resistor R4, the output terminal VOUT, and the first power supply line VDD.

The voltage generation circuit28A includes the first path PAS1and the second path PAS2. The first path PAS1is a path from the input terminal VIN11(or the first power supply line VDD) to the first node N1without passing through the second variable resistor R4. The second path PAS2is a path from the second node N2to the output terminal VOUT13(or the second power supply line VSS) without passing through the second variable resistor R4. A current flowing through each of the first path PAS1and the second path PAS2is the current IP/C.

2-2. Output of Voltage Generation Circuit

As described above, since a current flowing through the transistor T11(a current input from the input terminal VIN11) is “IP/C”, a current flowing through the transistor T12(a current input from the input terminal VIN12) is “IFLAT”, and a current flowing through the transistor T13(a current output to the output terminal VOUT13) is “IP/C”, a voltage of the output terminal VOUTis calculated as in the following Equation (2-1).

VOUT=R3·(IFLAT-IP/C+IP/C)+R4·(IFLAT-IP/C)=R3·IFLAT+R4·(IFLAT-IP/C)(2-1)

As described above, “IP/C” and “IFLAT” can be expressed as in the Equation (1-2) described above.

By substituting Equation (1-2) into Equation (2-1), VOUTcan be expressed as in the following Equation (2-2).

VOUT=R3R1·V1+R4·(V1R1-V2R2)(2-2)

As shown in Equation (2-1), a current flowing through the first variable resistor R3is the current IFLAT, and a current flowing through the second variable resistor R4is a current based on a difference between the current IP/Cand the current IFLAT. As shown in Equation (2-2), when V2/R2=V1/R1is satisfied at a certain temperature Temp1(that is, when IP/C=current IFLAT), the term of R4is zero.

Therefore, as in the voltage generation circuit28according to the first embodiment, the voltage generation circuit28A according to the present embodiment can adjust an absolute value of the output voltage VOUTat a certain temperature by a value of the first variable resistor R3, and can adjust a temperature gradient of the output voltage VOUTby a value of the second variable resistor R4. Since the values of the first variable resistor R3and the second variable resistor R4can be independently controlled, the absolute value of the output voltage VOUTand the temperature gradient of the output voltage VOUTcan be independently adjusted.

3. Third Embodiment

A voltage generation circuit according to a third embodiment will be described with reference toFIGS.7and8. A voltage generation circuit28B according to the third embodiment is similar to the voltage generation circuit28according to the first embodiment. In the following description, a description of the same configuration as that of the voltage generation circuit28according to the first embodiment will be omitted, and differences from the voltage generation circuit28will be mainly described.

3-1. Configuration of Voltage Generation Circuit

FIG.7is a circuit diagram showing a configuration of the voltage generation circuit according to the embodiment. As shown inFIG.7, in the voltage generation circuit28B, a second current generation circuit G2provided in the voltage generation circuit28shown inFIG.2is divided into a positive characteristic second current generation circuit G2pand a negative characteristic second current generation circuit G2c. Similarly, the transistor T2inFIG.2is divided into transistors T2pand T2c. Also, in this configuration, the transistor T3inFIG.2is divided into transistors T3pand T3c. Similarly, the transistor T9inFIG.2is divided into transistors T9pand T9c.

When the voltage VPTATis input to an input terminal of the positive characteristic second current generation circuit G2p, the positive characteristic second current generation circuit G2pgenerates the current IPTAT. A resistance value of a resistance element of the positive characteristic second current generation circuit G2pis R2p. When the voltage VCTATis input to an input terminal of the negative characteristic second current generation circuit G2c, the negative characteristic second current generation circuit G2cgenerates the current ICTAT. A resistance value of a resistance element of the negative characteristic second current generation circuit G2cis R2c.

The transistors T2p, T2c, T3p, T3c, T9p, and T9care all p-type transistors.

A pair of transistors T2pand T3pand a pair of transistors T2pand T9peach form a current mirror circuit. When a current generated by the positive characteristic second current generation circuit G2pand flowing through the transistor T2pis the current IPTAT, currents flowing through the transistors T3pand T9pare also the current IPTAT.

A pair of transistors T2cand T3cand a pair of transistors T2cand T9ceach form a current mirror circuit. When a current generated by the negative characteristic second current generation circuit G2cand flowing through the transistor T2cis the current ICTAT, currents flowing through the transistors T3cand T9care also the current ICTAT.

The transistors T3pand T3care connected to the transistor T4via a switch SW3. The transistor T4becomes connected to either the transistor T3por the transistor T3cby controlling the switch SW3. That is, a state in which the transistor T3pand the transistor T4are connected in series and a state in which the transistor T3cand the transistor T4are connected in series are switched by the switch SW3.

When the transistor T3pis selected by the switch SW3, since a current flowing through the transistor T3pis the current IPTAT, a current flowing through the transistor T4connected in series with the transistor T3pis also the current IPTAT. Since the pair of transistors T4and T8form a current mirror circuit, a current flowing through the transistor T8is also the current IPTAT.

When the transistor T3cis selected by the switch SW3, since a current flowing through the transistor T3cis the current ICTAT, a current flowing through the transistor T4connected in series with the transistor T3cis also the current ICTAT. Since the pair of transistors T4and T8form a current mirror circuit, the current flowing through the transistor T8is also the current ICTAT.

As described above, the current flowing through the transistor T8is controlled to be the current IPTATor the current ICTATby the switch SW3.

The transistors T9pand T9care connected to the second variable resistor R4via a switch SW9. The second variable resistor R4becomes connected to either the transistor T9por the transistor T9cby controlling the switch SW9. That is, a state in which the transistor T9p, the second variable resistor R4, and the first variable resistor R3are connected in series and a state in which the transistor T9c, the second variable resistor R4, and the first variable resistor R3are connected in series are switched by the switch SW9.

The switch SW3and the switch SW9are interlocked with each other. The switches are controlled such that when the switch SW3selects the transistor T3p, the switch SW9selects the transistor T9p. The switches are controlled such that when the switch SW3selects the transistor T3c, the switch SW9selects the transistor T9c.

FIG.8is a conceptual diagram showing the configuration of the voltage generation circuit according to the embodiment. InFIG.8, only the first variable resistor R3, the second variable resistor R4, and the output terminal VOUTamong circuit elements shown inFIG.7are shown, and other circuit elements are shown as input terminals and output terminals in the circuit shown inFIG.8. The transistor T7inFIG.7corresponds to the input terminal VIN7inFIG.8, the transistor T8inFIG.7corresponds to output terminals VOUT8pand VOUT8cinFIG.8, the transistors T9pand T9cinFIG.7correspond to input terminals VIN9pand VIN9cinFIG.8, and the transistor T10inFIG.7corresponds to the output terminal VOUT10inFIG.8.

The input terminals VIN9pand VIN9care switched by the switch SW9. Since the switch SW3is connected to the transistors T3pand T3cinFIG.7, and the current flowing through the transistor T8is controlled by the switching of the switch SW3as described above, the output terminals VOUT8pand the VOUT8care shown to be switched by the switch SW3inFIG.8.

In the following description, a case in which the switch SW3is connected to the output terminal VOUT8pand the switch SW9is connected to the input terminal VIN9pis referred to as “during a PTAT operation”. Meanwhile, a case in which the switch SW3is connected to the output terminal VOUT8cand the switch SW9is connected to the input terminal VIN9cis referred to as “during a CTAT operation”.

As shown inFIG.8, the voltage generation circuit28B includes the first path PAS1, the second path PAS2, and the third path PAS3. The first path PAS1is a path from the input terminal VIN7(or the first power supply line VDD) to the first node N1without passing through the second variable resistor R4. The second path PAS2is a path from the second node N2to the output terminal VOUT10(or the second power supply line VSS) without passing through the second variable resistor R4. The third path PAS3is a path from the first node N1to the output terminal VOUT8por VOUT8c(or the second power supply line VSS) without passing through the first variable resistor R3.

When the switch SW3is connected to the output terminal VOUT8pand the switch SW9is connected to the input terminal VIN9p, a current 2×IFLAT(3) is input from the input terminal VIN7, a current IPTAT(1) is input from the input terminal VIN9p, a current IPTAT(4) is output to the output terminal VOUT8p, and a current IFLAT(2) is output to the output terminal VOUT10. Although the details will be described later, a current flowing through the first variable resistor R3is determined to be a current IFLAT(5) due to the above input and output.

The numbers described in parentheses attached after the reference numerals indicating the above currents are given to distinguish currents flowing through different paths. Therefore, the same reference numerals before parentheses indicate the same current value. That is, for example, IPTAT(1) and IPTAT(4) are currents that flow in different paths, but current values are the same.

When the switch SW3is connected to the output terminal VOUT8cand the switch SW9is connected to the input terminal VIN9c, the current 2×IFLAT(3) is input from the input terminal VIN7, a current ICTAT(6) is input from the input terminal VIN9c, a current ICTAT(7) is output to the output terminal VOUT8c, and the current IFLAT(2) is output to the output terminal VOUT10. Although the details will be described later, the current flowing through the first variable resistor R3is determined to be the current IFLAT(5) due to the above input and output.

“During the PTAT operation”, a current (IR3) flowing through the first variable resistor R3and a current (IR4) flowing through the second variable resistor R4are expressed by the following Equations (3-1) and (3-2), respectively.
IR4=IPTAT(1)−IFLAT(2)  (3-1)
IR3=2×IFLAT(3)+(IPTAT(1)−IFLAT(2))−IPTAT(4)  (3-2)

“During the CTAT operation”, the current (IR3) flowing through the first variable resistor R3and the current (IR4) flowing through the second variable resistor R4are expressed as in the following Equations (3-3) and (3-4), respectively.
IR4=ICTAT(6)−IFLAT(2)  (3-3)
IR3=2×IFLAT(3)+(ICTAT(6)−IFLAT(2))−ICTAT(7)  (3-4)

In the case of Equation (3-2), the term of IPTATdisappears and only IFLATremains. In the case of Equation (3-4), the term of ICTATdisappears and only IFLATremains. As described above, the remaining IFLATis referred to as IFLAT(5). That is, the current (IR3) flowing through the first variable resistor R3is IFLAT(5) both “during the PTAT operation” and “during the CTAT operation”.

In other words, “during the PTAT operation”, when a current flowing through the second node N2is the current IPTAT(1), a current flowing through the first path PAS1is the current 2×IFLAT(3), a current flowing through the second path PAS2is the current IFLAT(2), and a current flowing through the third path PAS3is the current IPTAT(4).

“During the CTAT operation”, when the current flowing through the second node N2is the current ICTAT(6), the current flowing through the first path PAS1is the current 2×IFLAT(3), the current flowing through the second path PAS2is the current IFLAT(2), and the current flowing through the third path PAS3is the current ICTAT(7). The current flowing through the first path PAS1may be a current (n×IFLAT) that is n times the current IFLAT(n is a positive number excluding 1).

3-2. Output of Voltage Generation Circuit28B

A voltage of the output terminal VOUTdiffers during the PTAT operation and during the CTAT operation. In each case, the voltage of the output terminal VOUTis calculated as follows.

3-2-1. Output of Voltage Generation Circuit During PTAT Operation

Based on Equations (3-1) and (3-2), the voltage of the output terminal VOUTis calculated as in the following Equation (3-5).
VOUT=R3·IFLAT(5)+R4·(IPTAT(1)−IFLAT(2))  (3-5)

3-2-2. Output of Voltage Generation Circuit During CTAT Operation

Based on Equations (3-3) and (3-4), the voltage of the output terminal VOUTis calculated as in the following Equation (3-6).
VOUT=R3·IFLAT(5)+R4·(ICTAT(6)−IFLAT(2))  (3-6)

As shown in Equations (3-5) and (3-6), the current flowing through the first variable resistor R3is the current IFLAT(5), and a current flowing through the second variable resistor R4is a current based on a difference between the current IPTAT(1) and the current IFLAT(2) or a current based on a difference between the current ICTAT(6) and the current IFLAT(2). As shown in Equation (3-5), when IPTAT=IFLATat a certain temperature Temp1, the term of R4is zero. As shown in Equation (3-6), when ICTAT=IFLATat a certain temperature Temp1, the term of R4is zero.

Therefore, as in the voltage generation circuit28according to the first embodiment, the voltage generation circuit28B according to the present embodiment can adjust an absolute value of the output voltage VOUTat a certain temperature by a value of the first variable resistor R3, and can adjust a temperature gradient of the output voltage VOUTby a value of the second variable resistor R4. Since the values of the first variable resistor R3and the second variable resistor R4can be independently controlled, the absolute value of the output voltage VOUTand the temperature gradient of the output voltage VOUTcan be independently adjusted. Further, by switching the switches SW3and SW9, it is possible to supply both the output voltage VOUTin which the voltage value increases with an increase in temperature and the output voltage VOUTin which the voltage value decreases with the increase in temperature.

4. Fourth Embodiment

A voltage generation circuit according to a fourth embodiment will be described with reference toFIGS.9and10. A voltage generation circuit28C according to the fourth embodiment is similar to the voltage generation circuit28B according to the third embodiment. In the following description, a description of the same configuration as that of the voltage generation circuit28B according to the third embodiment will be omitted, and differences from the voltage generation circuit28B will be mainly described.

4-1. Configuration of Voltage Generation Circuit

FIG.9is a circuit diagram showing a configuration of the voltage generation circuit according to the embodiment. As shown inFIG.9, in the voltage generation circuit28C, the transistors T11to T13are provided instead of the transistors T5to T10that are provided in the voltage generation circuit28B shown inFIG.7. Since the transistors T12and T13inFIG.9are the same as the transistors T12and T13inFIG.5, detailed descriptions will be omitted.

Transistors T11pand T11care connected to the first node N1via a switch SW11. A state in which the transistor T11pis connected to the first node N1and a state in which the transistor T11cis connected to the first node N1are switched by the switch SW11.

The transistors T11p, T11c, and T12are p-type transistors. The transistor T13is an n-type transistor.

A pair of transistors T2pand T11pform a current mirror circuit. Therefore, when a current generated by the positive characteristic second current generation circuit G2pand flowing through the transistor T2pis the current IPTAT, a current flowing through the transistor T11pwhen the transistor T11pis selected by the switch SW11is also the current IPTAT.

A pair of transistors T2cand T11cform a current mirror circuit. Therefore, when a current generated by the negative characteristic second current generation circuit G2cand flowing through the transistor T2cis the current ICTAT, a current flowing through the transistor T11cwhen the transistor T11cis selected by the switch SW11is also the current ICTAT.

When the transistor T3pis selected by the switch SW3, since a current flowing through the transistor T3pis the current IPTAT, a current flowing through the transistor T4connected in series with the transistor T3pis also the current IPTAT. Since a pair of transistors T4and T13form a current mirror circuit, a current flowing through the transistor T13is also the current IPTAT.

When the transistor T3cis selected by the switch SW3, since a current flowing through the transistor T3cis the current ICTAT, a current flowing through the transistor T4connected in series with the transistor T3cis also the current ICTAT. Since the pair of transistors T4and T13form a current mirror circuit, the current flowing through the transistor T13is also the current ICTAT.

As described above, the current flowing through the transistor T13is controlled to be the current IPTATor the current ICTATby the switch SW3.

The switch SW3and the switch SW11are interlocked with each other. The switches are controlled such that when the switch SW3selects the transistor T3p, the switch SW11selects the transistor T11p. The switches are controlled such that when the switch SW3selects the transistor T3c, the switch SW11selects the transistor T11c.

FIG.10is a conceptual diagram showing the configuration of the voltage generation circuit according to the embodiment. InFIG.10, only the first variable resistor R3, the second variable resistor R4, and the output terminal VOUTamong circuit elements shown inFIG.9are shown, and other circuit elements are shown as input terminals and output terminals in the circuit shown inFIG.10. The transistors T11pand T11cinFIG.9correspond to input terminals VIN11pand VIN11cinFIG.10, the transistor T12inFIG.9corresponds to the input terminal VIN12inFIG.10, and the transistor T13inFIG.9corresponds to output terminals VOUT13pand VOUT13cinFIG.10.

The input terminals VIN11pand VIN11care switched by the switch SW11. Since the switch SW3is connected to the transistors T3pand T3cinFIG.9, and the current flowing through the transistor T13is controlled by the switching of the switch SW3as described above, the output terminals VOUT13pand VOUT13care shown to be switched by the switch SW3inFIG.10.

As shown inFIG.10, the voltage generation circuit28C includes the first path PAS1and the second path PAS2. The first path PAS1is a path from the input terminal VIN11por VIN11c(or the first power supply line VDD) to the first node N1without passing through the second variable resistor R4. The second path PAS2is a path from the second node N2to the output terminal VOUT13por VOUT13c(or the second power supply line VSS) without passing through the second variable resistor R4.

When the switch SW3is connected to the output terminal VOUT13pand the switch SW11is connected to the input terminal VIN11p, a current IPTAT(3) is input from the input terminal VIN11p, a current IFLAT(1) is input from the input terminal VIN12, a current IPTAT(2) is output to the output terminal VOUT13p. Although the details will be described later, a current flowing through the first variable resistor R3is determined to be a current IFLAT(4) due to the above input and output.

Meanwhile, when the switch SW3is connected to the output terminal VOUT13cand the switch SW11is connected to an input terminal VIN11c, a first current ICTAT(6) is input from the input terminal VIN11C, the current IFLAT(1) is input from the input terminal VIN12, and a current ICTAT(5) is output to the output terminal VOUT13c. Although the details will be described later, a current flowing through the first variable resistor R3is determined to be a current IFLAT(4) due to the above input and output.

When the switch SW3is connected to the output terminal VOUT13pand the switch SW11is connected to the input terminal VIN11p, a current (IR3) flowing through the first variable resistor R3and a current (IR4) flowing through the second variable resistor R4are expressed by the following Equations (4-1) and (4-2), respectively.
IR4=IFLAT(1)−IPTAT(2)  (4-1)
IR3=IPTAT(3)+(IFLAT(1)−IPTAT(2))  (4-2)

In this case, since a current of a value based on IFLAT(1)−IPTAT(2) is output to the output terminal VOUT, the case of performing such an operation is referred to “during a CTAT operation”.

When the switch SW3is connected to the output terminal VOUT13cand the switch SW11is connected to the input terminal VIN11c, the current (IR3) flowing through the first variable resistor R3and the current (IR4) flowing through the second variable resistor R4are expressed as in the following Equations (4-3) and (4-4), respectively.
IR4=IFLAT(1)−ICTAT(5)  (4-3)
IR3=ICTAT(6)+(IFLAT(1)−ICTAT(5))  (4-4)

In this case, since a current of a value based on IFLAT(1)−ICTAT(5) is output to the output terminal VOUT, the case of performing such an operation is referred to as “during a PTAT operation”.

In the case of Equation (4-2), the term of IPTATdisappears and IFLATremains. In the case of Equation (4-4), the term of ICTATdisappears and only IFLATremains. As described above, the remaining IFLATis referred to as IFLAT(4). That is, the current (IR3) flowing through the first variable resistor R3is IFLAT(4) both “during the CTAT operation” and “during the PTAT operation”.

In other words, “during the CTAT operation”, when a current flowing through the first path PAS1to the first node N1is the current IPTAT(3), a current supplied to the second node N2is the current IFLAT(1), and a current flowing through the second path PAS2is the current IPTAT(2). “During the PTAT operation”, when the current flowing through the first path PAS1to the first node N1is the current ICTAT(6), the current supplied to the second node N2is the current IFLAT(1), and the current flowing through the second path PAS2is the current ICTAT(5).

4-2. Output of Voltage Generation Circuit

A voltage of the output terminal VOUTdiffers during the CTAT operation and during the PTAT operation. In each case, the voltage of the output terminal VOUTis calculated as follows.

4-2-1. Output of Voltage Generation Circuit During CTAT Operation

Based on Equations (4-1) and (4-2), the voltage of the output terminal VOUTis calculated as in the following Equation (4-5).
VOUT=R3·IFLAT(4)+R4·(IFLAT(1)−IPTAT(2))  (4-5)
4-2-2. Output of Voltage Generation Circuit During PTAT Operation

Based on Equations (4-3) and (4-4), the voltage of the output terminal VOUTis calculated as in the following Equation (4-6).
VOUT=R3·IFLAT(4)+R4·(IFLAT(1)−ICTAT(5))  (4-6)

As shown in Equations (4-5) and (4-6), a current flowing through the first variable resistor R3is the current IFLAT(4), and a current flowing through the second variable resistor R4is a current based on a difference between the current IPTAT(2) and the current IFLAT(1) or a current based on a difference between the current ICTAT(5) and the current IFLAT(1). As shown in Equation (4-5), when IPTAT=IFLATat a certain temperature Temp1, the term of R4is zero. As shown in Equation (4-6), when ICTAT=IFLATat a certain temperature Temp1, the term of R4is zero.

Therefore, the voltage generation circuit28C according to the present embodiment can obtain the same effect as the voltage generation circuit28B according to the third embodiment. Specifically, an absolute value of the output voltage VOUTat a temperature can be adjusted by a value of the first variable resistor R3, and a temperature gradient of the output voltage VOUTcan be adjusted by a value of the second variable resistor R4. Since the values of the first variable resistor R3and the second variable resistor R4can be independently controlled, the absolute value of the output voltage VOUTand the temperature gradient of the output voltage VOUTcan be independently adjusted. Further, by switching the switches SW3and SW11, it is possible to supply both the output voltage VOUTin which the voltage value increases with an increase in temperature and the output voltage VOUTin which the voltage value decreases with the increase in temperature.

5. Fifth Embodiment

A voltage generation circuit according to a fifth embodiment will be described with reference toFIGS.11and12. A voltage generation circuit28D according to the fifth embodiment is similar to the voltage generation circuit28according to the first embodiment. In the following description, a description of the same configuration as that of the voltage generation circuit28according to the first embodiment will be omitted, and differences from the voltage generation circuit28will be mainly described.

5-1. Configuration of Voltage Generation Circuit

As shown inFIG.11, the voltage generation circuit28D includes a first voltage generation circuit28Dp, a second voltage generation circuit28Dc, the output terminal VOUT, and a switch SW28. The switch SW28switches between a connection between the first voltage generation circuit28Dp and the output terminal VOUTand a connection between the second voltage generation circuit28Dc and the output terminal VOUT.

Each of the first voltage generation circuit28Dp and the second voltage generation circuit28Dc has the same configuration as that of the voltage generation circuit28according to the first embodiment. When the voltage VPTATis input to an input terminal of a second current generation circuit G2pof the first voltage generation circuit28Dp, the second current generation circuit G2pgenerates the current IPTAT. Meanwhile, when the voltage VCTATis input to an input terminal of a second current generation circuit G2cof the second voltage generation circuit28Dc, the second current generation circuit G2cgenerates the current ICTAT. When the voltage VFLATis input to a first current generation circuit G1pof the first voltage generation circuit28Dp and a first current generation circuit G1cof the second voltage generation circuit28Dc, the current IFLATis generated.

In the present embodiment, the first current generation circuits G1pand G1cthat generate the current IFLATare provided in the first voltage generation circuit28Dp and the second voltage generation circuit28Dc respectively, but the present disclosure is not limited to this configuration. For example, the current IFLATgenerated by the first current generation circuit G1pof the first voltage generation circuit28Dp may be supplied to the second voltage generation circuit28Dc. In this case, a pair of transistors T1pand T5cand a pair of transistors T1pand T7ceach form a current mirror circuit. In the case of the above configuration, the first current generation circuit G1cand a transistor T1cof the second voltage generation circuit28Dc are omitted. Contrary to the above configuration, the current IFLATgenerated by the first current generation circuit G1cof the second voltage generation circuit28Dc may be supplied to the first voltage generation circuit28Dp. In this case, a pair of transistors T1cand T5pand a pair of transistors T1cand T7peach form a current mirror circuit. In the case of the above configuration, the first current generation circuit G1pand the transistor T1pof the first voltage generation circuit28Dp are omitted.

In the present embodiment, for convenience of explanation, a current generated by the second current generation circuit G2pis referred to as a “first current IPTAT”, and a current generated by the first current generation circuit G1pis referred to as a “second current IFLAT”. A current generated by the second current generation circuit G2cis referred to as a “third current ICTAT”, and a current generated by the first current generation circuit G1cis referred to as a “fourth current IFLAT”. Variable resistors provided in the first voltage generation circuit28Dp are referred to as a first variable resistor R3pand a second variable resistor R4p. Variable resistors provided in the second voltage generation circuit28Dc are referred to as a third variable resistor R3cand a fourth variable resistor R4c. In the first voltage generation circuit28Dp, the first variable resistor R3pand the second variable resistor R4pare connected in series. In the second voltage generation circuit28Dc, the third variable resistor R3cand the fourth variable resistor R4care connected in series.

In other words, the first voltage generation circuit28Dp generates the first current IPTAThaving a temperature-dependent characteristic (the first temperature-dependent characteristic) in which a current value thereof changes with a predetermined change in temperature, and the second current IFLAThaving a temperature-dependent characteristic (the second temperature-dependent characteristic) different from the first temperature-dependent characteristic. The second voltage generation circuit28Dc generates the third current ICTAThaving a temperature-dependent characteristic (a third temperature-dependent characteristic) in which a current value thereof changes in reverse to the first temperature-dependent characteristic with the predetermined change in temperature, and the fourth current IFLAThaving a temperature-dependent characteristic (a fourth temperature-dependent characteristic) different from the third temperature-dependent characteristic.

In the present embodiment, the first temperature-dependent characteristic is a temperature-dependent characteristic in which the current value increases with an increase in temperature. The third temperature-dependent characteristic is a temperature-dependent characteristic in which the current value decreases with an increase in temperature. The second temperature-dependent characteristic and the fourth temperature-dependent characteristic are temperature-dependent characteristics in which current values do not change with a change in temperature. Alternatively, the second temperature-dependent characteristic and the fourth temperature-dependent characteristic may be temperature-dependent characteristics in which current values change with a change in temperature.

FIG.12is a conceptual diagram showing a configuration of the voltage generation circuit according to the embodiment. Each of the first voltage generation circuit28Dp and the second voltage generation circuit28Dc has the same configuration as that of the voltage generation circuit28inFIG.3.

The first voltage generation circuit28Dp includes the first path PAS1, the second path PAS2, and the third path PAS3. The first path PAS1is a path from an input terminal VIN7p(or the first power supply line VDD) to the first node N1without passing through the second variable resistor R4p. The second path PAS2is a path from the second node N2to an output terminal VOUT10p(or the second power supply line VSS) without passing through the second variable resistor R4p. The third path PAS3is a path from the first node N1to the output terminal VOUT8p(or the second power supply line VSS) without passing through the first variable resistor R3p.

As shown inFIG.12, in the first voltage generation circuit28Dp, a current 2×IFLAT(3) is input from the input terminal VIN7p, a first current IPTAT(1) is input from the input terminal VIN9p, a first current IPTAT(4) is output to the output terminal VOUT8p, and a second current IFLAT(2) is output to the output terminal VOUT10p. Although the details will be described later, a current flowing through the first variable resistor R3pis determined to be the current IFLAT(5) due to the above input and output.

The second voltage generation circuit28Dc includes a fourth path PAS4, a fifth path PAS5, and a sixth path PAS6. The fourth path PAS4is a path from an input terminal VIN7c(or the first power supply line VDD) to a third node N3without passing through the fourth variable resistor R4c. The fifth path PAS5is a path from a fourth node N4to an output terminal VOUT10c(or the second power supply line VSS) without passing through the fourth variable resistor R4c. The sixth path PAS6is a path from the third node N3to an output terminal VOUT8c(or the second power supply line VSS) without passing through the third variable resistor R3c.

As in the first voltage generation circuit28Dp, in the second voltage generation circuit28Dc, a current 2×IFLAT(8) is input from the input terminal VIN7c, a third current ICTAT(6) is input from the input terminal VIN9c, a third current ICTAT(9) is output to the output terminal VOUT8c, and a fourth current IFLAT(7) is output to the output terminal VOUT10c. Although the details will be described later, a current flowing through the third variable resistor R3cis determined to be a current IFLAT(10) due to the above input and output.

In the first voltage generation circuit28Dp, a current (IR3p) flowing through the first variable resistor R3pand a current (IR4p) flowing through the second variable resistor R4pare expressed as in the following Equations (5-1) and (5-2), respectively.
IR4p=IPTAT(1)−IFLAT(2)  (5-1)
IR3p=2×IFLAT(3)+(IPTAT(1)−IFLAT(2))−IPTAT(4)  (5-2)

In the case of Equation (5-2), the term of IPTATdisappears and only IFLATremains. As described above, the remaining IFLATis referred to as IFLAT(5). That is, in the first voltage generation circuit28Dp, the current (IR3p) flowing through the first variable resistor R3pis IFLAT(5). IFLAT(5) is equivalent to the second current IFLATgenerated by the first current generation circuit G1p.

In the second voltage generation circuit28Dc, a current (IR3c) flowing through the third variable resistor R3cand a current (IR4c) flowing through the fourth variable resistor R4care expressed as in the following Equations (5-3) and (5-4), respectively.
IR4c=ICTAT(6)−IFLAT(7)  (5-3)
IR3c=2×IFLAT(8)+(ICTAT(6)−IFLAT(7))−ICTAT(9)  (5-4)

In the case of Equation (5-4), the term of ICTATdisappears and only IFLATremains. As described above, the remaining IFLATis referred to as IFLAT(10). That is, in the second voltage generation circuit28Dc, the current (IR3c) flowing through the third variable resistor R3cis IFLAT(10). IFLAT(10) is equivalent to the fourth current IFLATgenerated by the second voltage generation circuit28Dc.

In other words, in the first voltage generation circuit28Dp, the current flowing through the first variable resistor R3pis the second current IFLAT(IFLAT(5)). A current flowing through the second variable resistor R4pis a current (IPTAT(1)−IFLAT(2)) based on a difference between the first current IPTATand the second current IFLAT. Similarly, in the second voltage generation circuit28Dc, the current flowing through the third variable resistor R3cis the fourth current IFLAT(IFLAT(10)). A current flowing through the fourth variable resistor R4cis a current (ICTAT(6)−IFLAT(7)) based on a difference between the third current ICTATand the fourth current IFLAT.

Furthermore, in the first voltage generation circuit28Dp, a current flowing through the first path PAS1is the current (2×IFLAT(3)) that is twice the second current IFLAT, a current flowing through the second path PAS2is the second current IFLAT(2), and a current flowing through the third path PAS3is the first current IPTAT(4). Similarly, in the second voltage generation circuit28Dc, a current flowing through the fourth path PAS4is the current (2×IFLAT(8)) that is twice the fourth current, a current flowing through the fifth path PAS5is the fourth current IFLAT(7), and a current flowing through the sixth path PAS6is the third current ICTAT(9). The current flowing through the first path PAS1and the current flowing through the fourth path PAS4may be currents (n×IFLAT) that are n times the second current IFLATand the fourth current IFLAT(n is a positive number excluding 1), respectively.

5-2. Output of Voltage Generation Circuit28D

A voltage of the output terminal VOUTdiffers when the switch SW28is connected to the first voltage generation circuit28Dp and when the switch SW28is connected to the second voltage generation circuit28Dc. The voltage output by each of the first voltage generation circuit28Dp and the second voltage generation circuit28Dc is calculated as follows.

5-2-1. Output of First Voltage Generation Circuit28Dp

Based on Equations (5-1) and (5-2), the voltage of the output terminal VOUTwhen the switch SW28is connected to the first voltage generation circuit28Dp is calculated by the following Equation (5-5).
VOUT=R3p·IFLAT(5)+R4p·(IPTAT(1)−IFLAT(2))  (5-5)

5-2-2. Output of Second Voltage Generation Circuit28Dc

Based on Equations (5-3) and (5-4), the voltage of the output terminal VOUTwhen the switch SW28is connected to the second voltage generation circuit28Dc is calculated as in the following Equation (5-6).
VOUT=R3c·IFLAT(10)+R4c·(ICTAT(6)−IFLAT(7))  (5-6)

As shown in Equation (5-5), the current flowing through the first variable resistor R3pis the second current IFLAT(5), and the current flowing through the second variable resistor R4pis a current based on a difference between the first current IPTAT(1) and the second current IFLAT(2). As shown in Equation (5-6), a current flowing through the third variable resistor R3cis the fourth current IFLAT(10), and the current flowing through the fourth variable resistor R4cis a current based on a difference between the third current ICTAT(6) and the fourth current IFLAT(7). As shown in Equation (5-5), when IPTAT=IFLATat a certain temperature Temp1, the term of R4is zero. As shown in Equation (5-6), when ICTAT=IFLATat a certain temperature Temp1, the term of R4cis zero.

Therefore, as in the voltage generation circuit28according to the first embodiment, the voltage generation circuit28D according to the present embodiment can adjust an absolute value of the output voltage VOUTat a certain temperature by values of the first variable resistor R3pand the third variable resistor R3c, and can adjust a temperature gradient of the output voltage VOUTby values of the second variable resistor R4pand the fourth variable resistor R4c. Since the values of the first variable resistor R3p, the second variable resistor R4p, the third variable resistor R3c, and the fourth variable resistor R4ccan be independently controlled, the absolute value of the output voltage VOUTand the temperature gradient of the output voltage VOUTcan be independently adjusted. Further, by switching the switch SW28, it is possible to supply both the output voltage VOUTin which the voltage value increases with an increase in temperature and the output voltage VOUTin which the voltage value decreases with the increase in temperature.

6. Sixth Embodiment

A voltage generation circuit according to a sixth embodiment will be described with reference toFIGS.13and14. A voltage generation circuit28E according to the sixth embodiment is similar to the voltage generation circuit28D according to the fifth embodiment. In the following description, a description of the same configuration as that of the voltage generation circuit28D according to the fifth embodiment will be omitted, and differences from the voltage generation circuit28D will be mainly described.

6-1. Configuration of Voltage Generation Circuit

As shown inFIG.13, the voltage generation circuit28E includes a first voltage generation circuit28Ep, a second voltage generation circuit28Ec, the output terminal VOUT, and the switch SW28. The switch SW28switches between a connection between the first voltage generation circuit28Ep and the output terminal VOUTand a connection between the second voltage generation circuit28Ec and the output terminal VOUT.

Each of the first voltage generation circuit28Ep and the second voltage generation circuit28Ec has the same configuration as that of the voltage generation circuit28A according to the second embodiment. The second current generation circuit G2pprovided in the first voltage generation circuit28Ep and the second current generation circuit G2cprovided in the second voltage generation circuit28Ec have the same configurations as those of the second current generation circuits G2pand G2caccording to the fifth embodiment, respectively. Therefore, detailed descriptions of the first voltage generation circuit28Ep and the second voltage generation circuit28Ec will be omitted.

In the present embodiment, as in the fifth embodiment, a current generated by the second current generation circuit G2pis referred to as the “first current IPTAT”, and a current generated by the first current generation circuit G1pis referred to as the “second current IFLAT”. A current generated by the second current generation circuit G2cis referred to as a “third current ICTAT”, and a current generated by the first current generation circuit G1cis referred to as a “fourth current IFLAT”. Variable resistors provided in the first voltage generation circuit28Ep are referred to as the first variable resistor R3pand the second variable resistor R4p. Variable resistors provided in the second voltage generation circuit28Ec are referred to as the third variable resistor R3cand the fourth variable resistor R4c. In the first voltage generation circuit28Ep, the first variable resistor R3pand the second variable resistor R4pare connected in series. In the second voltage generation circuit28Ec, the third variable resistor R3cand the fourth variable resistor R4care connected in series.

In the present embodiment, the first current generation circuits G1pand G1cthat generate the current IFLATare provided in the first voltage generation circuit28Ep and the second voltage generation circuit28Ec, respectively, but the present disclosure is not limited to this configuration. For example, the current IFLATgenerated by the first current generation circuit G1pof the first voltage generation circuit28Ep may be supplied to the second voltage generation circuit28Ec. In this case, a pair of transistors T1pand T12cform a current mirror circuit. In the case of the above configuration, the first current generation circuit G1cand the transistor T1cof the second voltage generation circuit28Ec are omitted. Contrary to the above configuration, the current IFLATgenerated by the first current generation circuit G1cof the second voltage generation circuit28Ec may be supplied to the first voltage generation circuit28Ep. In this case, a pair of transistors T1cand T12pform a current mirror circuit. In the case of the above configuration, the first current generation circuit G1pand the transistor T1pof the first voltage generation circuit28Ep are omitted.

FIG.14is a conceptual diagram showing a configuration of the voltage generation circuit according to the embodiment. Each of the first voltage generation circuit28Ep and the second voltage generation circuit28Ec has the same configuration as that of the voltage generation circuit28A inFIG.6.

The first voltage generation circuit28Ep includes the first path PAS1and the second path PAS2. The first path PAS1is a path from the input terminal VIN11p(or the first power supply line VDD) to the first node N1without passing through the second variable resistor R4p. The second path PAS2is a path from the second node N2to the output terminal VOUT13p(or the second power supply line VSS) without passing through the second variable resistor R4p.

As shown inFIG.14, in the first voltage generation circuit28Ep, a first current IFLAT(3) is input from the input terminal VIN11p, a second current IFLAT(1) is input from the input terminal VIN12p, and a first current IPTAT(2) is output to the output terminal VOUT13p. Although the details will be described later, a current flowing through the first variable resistor R3pis determined to be the current IFLAT(4) due to the above input and output.

The second voltage generation circuit28Ec includes the fourth path PAS4and the fifth path PAS5. The fourth path PAS4is a path from the input terminal VIN11c(or the first power supply line VDD) to the third node N3without passing through the fourth variable resistor R4c. The fifth path PAS5is a path from the fourth node N4to the output terminal VOUT13c(or the second power supply line VSS) without passing through the fourth variable resistor R4c.

As in the first voltage generation circuit28Ep, in the second voltage generation circuit28Ec, a third current ICTAT(7) is input from the input terminal VIN11c, a fourth current IFLAT(5) is input from the input terminal VIN12c, and the third current ICTAT(6) is output to the output terminal VOUT13c. Although the details will be described later, a current flowing through the third variable resistor R3cis determined to be a current IFLAT(8) due to the above input and output.

In the first voltage generation circuit28Ep, a current (IR3p) flowing through the first variable resistor R3pand a current (IR4p) flowing through the second variable resistor R4pare expressed by the following Equations (6-1) and (6-2), respectively.
IR4p=IFLAT(1)−IPTAT(2)  (6-1)
IR3p=IPTAT(3)+(IFLAT(1)−IPTAT(2))  (6-2)

In this case, since a current of a value based on IFLAT(1)−IPTAT(2) is output to the output terminal VOUTthe case of performing such an operation is referred to as “during a CTAT operation”.

In the case of Equation (6-2), the term of IPTATdisappears and only IFLATremains. As described above, the remaining IFLATis referred to as IFLAT(4). That is, in the first voltage generation circuit28Ep, the current (IR3p) flowing through the first variable resistor R3pis IFLAT(4). IFLAT(4) is equivalent to the second current IFLATgenerated by the first current generation circuit G1p.

In the second voltage generation circuit28Ec, a current (IR3c) flowing through the third variable resistor R3cand a current (IR4c) flowing through the fourth variable resistor R4care expressed by the following Equations (6-3) and (6-4), respectively.
IR4c=IFLAT(5)−ICTAT(6)  (6-3)
IR3c=ICTAT(7)+(IFLAT(5)−ICTAT(6))  (6-4)

In this case, since a current of a value based on IFLAT(5)−ICTAT(6) is output to the output terminal VOUT, the case of performing such an operation is referred to as “during a PTAT operation”.

In the case of Equation (6-4), the term of ICTATdisappears and only IFLATremains. As described above, the remaining IFLATis referred to as IFLAT(8). That is, in the second voltage generation circuit28Ec, the current (IR3c) flowing through the third variable resistor R3cis IFLAT(8). IFLAT(8) is equivalent to the fourth current IFLATgenerated by the second voltage generation circuit28Ec.

In other words, in the first voltage generation circuit28Ep, the current flowing through the first variable resistor R3pis the second current IFLAT(IFLAT(4)). A current flowing through the second variable resistor R4pis a current (IFLAT(1)−IPTAT(2)) based on a difference between the first current IPTATand the second current IFLAT. Similarly, in the second voltage generation circuit28Ec, the current flowing through the third variable resistor R3cis the fourth current IFLAT(IFLAT(8)). A current flowing through the fourth variable resistor R4cis a current (IFLAT(5)−ICTAT(6)) based on a difference between the third current ICTATand the fourth current IFLAT.

Furthermore, in the first voltage generation circuit28Ep, a current flowing through the first path PAS1is the first current IPTAT(3), and a current flowing through the second path PAS2is the first current IPTAT(2). Similarly, in the second voltage generation circuit28Ec, a current flowing through the fourth path PAS4is the third current ICTAT(7), and a current flowing through the fifth path PAS5is the third current ICTAT(6).

6-2. Output of Voltage Generation Circuit28E

A voltage of the output terminal VOUTdiffers when the switch SW28is connected to the first voltage generation circuit28Ep and when the switch SW28is connected to the second voltage generation circuit28Ec. The voltage output by each of the first voltage generation circuit28Ep and the second voltage generation circuit28Ec is calculated as follows.

6-2-1. Output of First Voltage Generation Circuit28Ep During CTAT Operation

Based on Equations (6-1) and (6-2), the voltage of the output terminal VOUTwhen the switch SW28is connected to the first voltage generation circuit28Ep is calculated by the following Equation (6-5).
VOUT=R3p·IFLAT(4)+R4p·(IFLAT(1)−IPTAT(2))  (6-5)
6-2-2. Output of Second Voltage Generation Circuit28Ec During PTAT Operation

Based on Equations (6-3) and (6-4), the voltage of the output terminal VOUTwhen the switch SW28is connected to the second voltage generation circuit28Ec is calculated as in the following Equation (6-6).
VOUT=R3c·IFLAT(8)+R4c·(IFLAT(5)−ICTAT(6)  (6-6)

As shown in Equation (6-5), the current flowing through the first variable resistor R3pis a second current IFLAT(4), and the current flowing through the second variable resistor R4pis a current based on a difference between the first current IPTAT(2) and the second current IFLAT(1). As shown in Equation (6-6), the current flowing through the third variable resistor R3cis a fourth current IFLAT(8), and the current flowing through the fourth variable resistor R4cis a current based on a difference between the third current ICTAT(6) and the fourth current IFLAT(5). As shown in Equation (6-5), when IPTAT=IFLATat a certain temperature Temp1, the term of R4pis zero. As shown in Equation (6-6), when ICTAT=IFLATat a certain temperature Temp1, the term of R4cis zero.

Therefore, the voltage generation circuit28E according to the present embodiment can obtain the same effect as the voltage generation circuit28D.

7. Seventh Embodiment

A voltage generation circuit according to a seventh embodiment will be described with reference toFIGS.15to17. A voltage generation circuit28F according to the seventh embodiment is similar to the voltage generation circuit28according to the first embodiment. In the following description, a description of the same configuration as that of the voltage generation circuit28according to the first embodiment will be omitted, and differences from the voltage generation circuit28will be mainly described.

7-1. Configuration of Voltage Generation Circuit

FIG.15is a circuit diagram showing a configuration of the voltage generation circuit according to the embodiment. As shown inFIG.15, in the voltage generation circuit28F, transistors T14to T17and switches SW10and SW14to SW17are provided instead of the transistors T7to T9that are provided in the voltage generation circuit28shown inFIG.2. The transistors T14to T16are p-type transistors. The transistor T17is an n-type transistor. In the present embodiment, when the voltage VPTATis input to an input terminal of the second current generation circuit G2, the second current generation circuit G2generates the current IPTAT.

The transistor T10and the switch SW10are connected in series between the output terminal VOUTand the second power supply line VSS.

The transistor T14and the switch SW14are connected in series between the first power supply line VDD and the second node N2. In a state in which the switch SW15is connected to a second node N2side, the transistor T15and the switch SW15are connected in series between the first power supply line VDD and the second node N2. The transistor T14and the switch SW14are connected in parallel with the transistor T15and the switch SW15between the first power supply line VDD and the second node N2. A state in which the transistor T14is connected to the second node N2and a state in which the transistor T15is connected to the second node N2are switched by the switches SW14and SW15.

In a state in which the switch SW15is connected to a first node N1side, the transistor T15and the switch SW15are connected in series between the first power supply line VDD and the first node N1. The transistor T16and the switch SW16are connected in series between the first power supply line VDD and the first node N1. The transistor T15and the switch SW15are connected in parallel with the transistor T16and the switch SW16between the first power supply line VDD and the first node N1. A state in which the transistor T15is connected to the first node N1and a state in which the transistor T16is connected to the first node N1are switched by the switches SW15and SW16.

In a state in which the switch SW17is connected to a first node N1side, the transistor T17and the switch SW17are connected in series between the first node N1and the second power supply line VSS. In a state in which the switch SW17is connected to the second node N2side, the transistor T17and the switch SW17are connected in series between the second node N2and the second power supply line VSS. A state in which the transistor T17is connected to the first node N1and a state in which the transistor T17is connected to the second node N2are switched by the switch SW17.

A pair of transistors T1and T14, a pair of transistors T1and T16, a pair of transistors T2and T15, and a pair of transistors T4and T17each form a current mirror circuit. Sizes of the transistors are the same. As the transistor T16denoted by “×2”, two transistors are connected in parallel. In this configuration, a current flowing through the transistor T14is the current IFLAT, a current flowing through the transistor T15is the current IPTAT, a current flowing through the transistor T16is the current 2×IFLAT, and a current flowing through the transistor T17is the current IPTAT.

FIG.16andFIG.17are conceptual diagrams showing the configuration of the voltage generation circuit according to the embodiment. The transistors T14, T15, and T16inFIG.15correspond to input terminals VIN14, VIN15, and VIN16inFIGS.16and17, respectively, and the transistors T10and T17inFIG.15correspond to output terminals VOUT10and VOUT17inFIGS.16and17, respectively. The current IFLATis input from the input terminal VIN14, the current IPTATis input from the input terminal VIN15, and the current 2×IFLATis input from the input terminal VIN16. The current IFLATis output to the output terminal VOUT10, and the current IPTATis output to the output terminal VOUT17.

An input terminal connected to the second node N2is switched to the input terminal VIN14or the input terminal VIN15, and a current supplied to the second node N2is switched to the current IFLATor the current IPTATby the switches SW14and SW15. An input terminal connected to the first node N1is switched to the input terminal VIN15or the input terminal VIN16, and a current supplied to the first node N1is switched to the current IPTATor 2×IFLATby the switches SW15and SW16.

The switches SW10and SW14to SW17are interlocked with one another. As shown inFIG.16, when the switch SW10is in an ON state (a conductive state), the switch SW14is in an OFF state (a non-conductive state), the switch SW15is connected to the second node N2side, the switch SW16is in the ON state, and the switch SW17is connected to the first node N1side. As shown inFIG.17, when the switch SW10is in the OFF state, the switch SW14is in the ON state, the switch SW15is connected to the first node N1side, the switch SW16is in the OFF state, and the switch SW17is connected to the second node N2side.

As shown inFIGS.16and17, the voltage generation circuit28F includes the first path PAS1, the second path PAS2, and the third path PAS3. The first path PAS1is a path from the input terminal VIN16(or the first power supply line VDD) to the first node N1without passing through the second variable resistor R4, and a path from the input terminal VIN15(or the first power supply line VDD) to the first node N1without passing through the second variable resistor R4. The second path PAS2is a path from the second node N2to the output terminal VOUT10or the output terminal VOUT17(or the second power supply line VSS) without passing through the second variable resistor R3. The third path PAS3is a path from the first node N1to the output terminal VOUT17(or the second power supply line VSS) without passing through the first variable resistor R3.

As shown inFIG.16, the current IPTAT(1) is supplied from the input terminal VIN15to the second node N2, a current 2×IFLAT(4) is supplied from the input terminal VIN16to the first node N1, the current IFLAT(2) is output from the second node N2to the output terminal VOUT10, and the current IPTAT(3) is output from the first node N1to the output terminal VOUT17. Although the details will be described later, the current flowing through the first variable resistor R3is determined to be the current IFLAT(5) due to the above input and output.

As shown inFIG.17, a current IFLAT(6) is supplied from the input terminal VIN14to the second node N2, a current IPTAT(8) is supplied from the input terminal VIN15to the first node N1, and a current IPTAT(7) is output from the second node N2to the output terminal VOUT17. Although the details will be described later, the current flowing through the first variable resistor R3is determined to be the current IFLAT(5) due to the above input and output.

In the state shown inFIG.16, a current (IR3) flowing through the first variable resistor R3and a current (IR4) flowing through the second variable resistor R4are expressed by the following Equations (7-1) and (7-2), respectively.
IR4=IPTAT(1)−IFLAT(2)  (7-1)
IR3=2×IFLAT(4)+(IPTAT(1)−IFLAT(2))−IPTAT(3)  (7-2)

In this case, since a current of a value based on IPTAT(1)−IFLAT(2) is output to the output terminal VOUT, the case of performing such an operation is referred to as “during a PTAT operation”.

In the state shown inFIG.17, a current (IR3) flowing through the first variable resistor R3and a current (IR4) flowing through the second variable resistor R4are expressed by the following Equations (7-3) and (7-4), respectively.
IR4=IFLAT(6)−IPTAT(7)  (7-3)
IR3=IPTAT(8)+(IFLAT(6)−IPTAT(7))  (7-4)

In this case, since a current of a value based on IFLAT(6)−IPTAT(7) is output to the output terminal VOUT, the case of performing such an operation is referred to as “during a CTAT operation”.

In the case of Equation (7-2), the term of IPTATdisappears and only IFLATremains. In the case of Equation (7-4), the term of IPTATdisappears and only IFLATremains. As described above, the remaining IFLATis referred to as IFLAT(5). That is, the current (IR3) flowing through the first variable resistor R3is IFLAT(5) even in the case of both “during the PTAT operation” and “during the CTAT operation”.

In other words, “during the PTAT operation” shown inFIG.16, when a current supplied to the second node N2is the current IPTAT(1), a current flowing through the first path PAS1is the current (2×IFLAT(4)) that is twice the current IFLAT, a current flowing through the second path PAS2is the current IFLAT(2), and a current flowing through the third path PAS3is the current IPTAT(3). The current flowing through the first path PAS1may be a current (n×IFLAT) that is n times the current IFLAT(n is a positive number excluding 1).

“During the CTAT operation” shown inFIG.17, when a current supplied to the second node N2is the current IFLAT(6), the current flowing through the first path PAS1is the current IPTAT(8), the current flowing through the second path PAS2is the current IPTAT(7), and the third path PAS3is cut off.

7-2. Output of Voltage Generation Circuit

A voltage of the output terminal VOUTdiffers during the PTAT operation and during the CTAT operation. In each case, the voltage of the output terminal VOUTis calculated as follows.

7-2-1. Output of Voltage Generation Circuit During PTAT Operation

Based on Equations (7-1) and (7-2), the voltage of the output terminal VOUTis calculated as in the following Equation (7-5).
VOUT=R3·IFLAT(5)+R4·(IPTAT(1)−IFLAT(2))  (7-5)
7-2-2. Output of Voltage Generation Circuit During CTAT Operation

Based on Equations (7-3) and (7-4), the voltage of the output terminal VOUTis calculated as in the following Equation (7-6).
VOUT=R3·IFLAT(5)+R4·(IFLAT(6)−IPTAT(7))  (7-6)

As shown in Equations (7-5) and (7-6), the current flowing through the first variable resistor R3is the current IFLAT(5), and a current flowing through the second variable resistor R4is a current based on a difference between the current IPTAT(1) and the current IFLAT(2) or a current based on a difference between the current IPTAT(7) and the current IFLAT(6). As shown in Equations (7-5) and (7-6), when IPTAT=IFLATat a certain temperature Temp1, the term of R4is zero.

Therefore, the voltage generation circuit28F according to the present embodiment can obtain the same effect as the voltage generation circuit28according to the first embodiment. Further, by switching the switches SW10and SW14to SW17, it is possible to supply both the output voltage VOUTin which the voltage value increases with an increase in temperature and the output voltage VOUTin which the voltage value decreases with the increase in temperature.

8. Eighth Embodiment

A voltage generation circuit according to an eighth embodiment will be described with reference toFIGS.18and19. A voltage generation circuit28G according to the eighth embodiment has substantially the same circuit configuration as that of the voltage generation circuit28F according to the seventh embodiment, and is different from the voltage generation circuit28F in a switching method of the switches SW10and SW14to SW17. In the following description, a description of the same configuration as that of the voltage generation circuit28F according to the seventh embodiment will be omitted, and differences from the voltage generation circuit28F will be mainly described.

FIGS.18and19are conceptual diagrams showing a configuration of the voltage generation circuit according to the embodiment. A correspondence relationship between each transistor shown inFIG.15and each input terminal and each output terminal shown inFIGS.18and19is the same as that of the seventh embodiment.

In the present embodiment, when the voltage VCTATis input to an input terminal of the second current generation circuit G2, the second current generation circuit G2generates the current ICTAT. Therefore, the current ICTATis supplied from the input terminal VIN15, and the current ICTATis output to the output terminal VOUT17.

As shown inFIG.18, the current IFLAT(1) is supplied from the input terminal VIN14to the second node N2, a current ICTAT(3) is supplied from the input terminal VIN15to the first node N1, and a current ICTAT(2) is output from the second node N2to the output terminal VOUT17. Although the details will be described later, a current flowing through the first variable resistor R3is determined to be a current IFLAT(4) due to the above input and output.

As shown inFIG.19, the current ICTAT(5) is supplied from the input terminal VIN15to the second node N2, the current 2×IFLAT(8) is supplied from the input terminal VIN16to the first node N1, the current IFLAT(6) is output from the second node N2to the output terminal VOUT10, and the current ICTAT(7) is output from the first node N1to the output terminal VOUT17. Although the details will be described later, a current flowing through the first variable resistor R3is determined to be a current IFLAT(4) due to the above input and output.

In the state shown inFIG.18, a current (IR3) flowing through the first variable resistor R3and a current (IR4) flowing through the second variable resistor R4are expressed by the following Equations (8-1) and (8-2), respectively.
IR4=IFLAT(1)−ICTAT(2)  (8-1)
IR3=IFLAT(1)−ICTAT(2)+ICTAT(3)  (8-2)

In this case, since a current of a value based on IFLAT(1)−ICTAT(2) is output to the output terminal VOUT, the case of performing such an operation is referred to as “during a PTAT operation”.

In the state shown inFIG.19, the current (IR3) flowing through the first variable resistor R3and the current (IR4) flowing through the second variable resistor R4are expressed as in the following Equations (8-3) and (8-4), respectively.
IR4=ICTAT(5)−IFLAT(6)  (8-3)
IR3=2×IFLAT(8)+ICTAT(5)−IFLAT(6)−ICTAT(7)  (8-4)

In this case, since a current of a value based on ICTAT(5)−IFLAT(6) is output to the output terminal VOUT, the case of performing such an operation is referred to as “during a CTAT operation”.

In the case of Equation (8-2), the term of ICTATdisappears and only IFLATremains. In the case of Equation (8-4), the term of ICTATdisappears and only IFLATremains. As described above, the remaining IFLATis referred to as IFLAT(4). That is, the current (IR3) flowing through the first variable resistor R3is IFLAT(4) even in the case of both “during the PTAT operation” and “during the CTAT operation”.

In other words, “during the PTAT operation” shown inFIG.18, when a current supplied to the second node N2is the current IFLAT(1), a current flowing through the first path PAS1is the current ICTAT(3), a current flowing through the second path PAS2is the current ICTAT(2), and the third path PAS3is cut off.

“During the CTAT operation” shown inFIG.19, when the current supplied to the second node N2is the current ICTAT(5), the current flowing through the first path PAS1is a current (2×IFLAT(8)) that is twice the current IFLAT, the current flowing through the second path PAS2is the current IFLAT(6), and a current flowing through the third path PAS3is the current ICTAT(7). The current flowing through the first path PAS1may be a current (n×IFLAT) that is n times the current IFLAT(n is a positive number excluding 1).

8-2. Output of Voltage Generation Circuit

A voltage of the output terminal VOUTdiffers during the PTAT operation and during the CTAT operation. In each case, the voltage of the output terminal VOUTis calculated as follows.

8-2-1. Output of Voltage Generation Circuit During PTAT Operation

Based on Equations (8-1) and (8-2), the voltage of the output terminal VOUTis calculated as in the following Equation (8-5).
VOUT=R3·IFLAT(4)+R4·(IFLAT(1)−ICTAT(2))  (8-5)
8-2-2. Output of Voltage Generation Circuit During CTAT Operation

Based on Equations (8-3) and (8-4), the voltage of the output terminal VOUTis calculated as in the following Equation (8-6).
VOUT=R3·IFLAT(4)+R4·(ICTAT(5)−IFLAT(6))  (8-6)

As shown in Equations (8-5) and (8-6), a current flowing through the first variable resistor R3is the current IFLAT(4), and a current flowing through the second variable resistor R4is a current based on a difference between the current IFLAT(1) and the current ICTAT(2) or a current based on a difference between the current ICTAT(5) and the current IFLAT(6). As shown in Equations (8-5) and (8-6), when ICTAT=IFLATat a certain temperature Temp1, the term of R4is zero.

Therefore, the voltage generation circuit28G according to the present embodiment can obtain the same effect as the voltage generation circuit28F according to the seventh embodiment.

While certain embodiments have been described with reference to the accompanying drawings, these embodiments are not intended to limit the scope of the disclosure, and may be embodied in a variety of other forms. For example, a device to which additions, omissions, or modifications of elements are made by those skilled in the art based on the voltage generation circuit according to the present embodiment falls within the scope of the present disclosure as long as the gist of the present disclosure is provided. Further, the embodiments may be appropriately combined if there is no contradiction with each other, and technical matters common to each embodiment are included in each embodiment even if there is no explicit description.

Even with other actions and effects different from the actions and effects brought about by the aspects of the above-described embodiments, it is understood that, as a matter of course, actions and effects apparent from the description of the present specification, or actions and effects that can be easily predicted by those skilled in the art are brought about by the present disclosure.