Patent ID: 12261140

DETAILED DESCRIPTION

The present disclosure includes one or more aspects or embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. Those skilled in the art will appreciate that the description is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the disclosure as defined by the appended claims and their equivalents as supported by the following disclosure and drawings. In the description, numerous specific details are set forth, such as specific configurations, compositions, and processes, etc., in order to provide a thorough understanding of the disclosure. In other instances, well-known processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the disclosure. Furthermore, the various embodiments shown in the FIGs. are illustrative representations and are not necessarily drawn to scale.

This disclosure, its aspects and implementations, are not limited to the specific equipment, material types, or other system component examples, or methods disclosed herein. Many additional components, manufacturing and assembly procedures known in the art consistent with manufacture and packaging are contemplated for use with particular implementations from this disclosure. Accordingly, for example, although particular implementations are disclosed, such implementations and implementing components may comprise any components, models, types, materials, versions, quantities, and/or the like as is known in the art for such systems and implementing components, consistent with the intended operation.

The word “exemplary,” “example,” or various forms thereof are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “exemplary” or as an “example” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Furthermore, examples are provided solely for purposes of clarity and understanding and are not meant to limit or restrict the disclosed subject matter or relevant portions of this disclosure in any manner. It is to be appreciated that a myriad of additional or alternate examples of varying scope could have been presented, but have been omitted for purposes of brevity.

Where the following examples, embodiments and implementations reference examples, it should be understood by those of ordinary skill in the art that other manufacturing devices and examples could be intermixed or substituted with those provided. In places where the description above refers to particular embodiments, it should be readily apparent that a number of modifications may be made without departing from the spirit thereof and that these embodiments and implementations may be applied to other technologies as well. Accordingly, the disclosed subject matter is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the disclosure and the knowledge of one of ordinary skill in the art.

Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of a plurality of die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components, which are electrically connected to form functional electrical circuits. Active electrical components, such as transistors and diodes, have the ability to control the flow of electrical current. Passive electrical components, such as capacitors, inductors, resistors, and transformers, create a relationship between voltage and current necessary to perform electrical circuit functions.

Passive and active components are formed over the surface of the semiconductor wafer by a series of process steps including doping, deposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process modifies the electrical conductivity of semiconductor material in active devices, transforming the semiconductor material into an insulator, conductor, or dynamically changing the semiconductor material conductivity in response to an electric field or base current. Transistors contain regions of varying types and degrees of doping arranged as necessary to enable the transistor to promote or restrict the flow of electrical current upon the application of the electric field or base current.

Active and passive components are formed by layers of materials with different electrical properties. The layers can be formed by a variety of deposition techniques determined in part by the type of material being deposited. For example, thin film deposition can involve chemical vapor deposition (CVD), physical vapor deposition (PVD), electrolytic plating, and electroless plating processes. Each layer is generally patterned to form portions of active components, passive components, or electrical connections between components.

The layers can be patterned using photolithography, which involves the deposition of light sensitive material, e.g., photoresist, over the layer to be patterned. A pattern is transferred from a photomask to the photoresist using light. In one embodiment, the portion of the photoresist pattern subjected to light is removed using a solvent, exposing portions of the underlying layer to be patterned. In another embodiment, the portion of the photoresist pattern not subjected to light, the negative photoresist, is removed using a solvent, exposing portions of the underlying layer to be patterned. The remainder of the photoresist is removed, such as by a stripping process, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.

Patterning is the basic operation by which portions of the top layers on the semiconductor wafer surface are removed. Portions of the semiconductor wafer can be removed using photolithography, photomasking, masking, oxide or metal removal, photography and stenciling, and microlithography. Photolithography includes forming a pattern in reticles or a photomask and transferring the pattern into the surface layers of the semiconductor wafer. Photolithography forms the horizontal dimensions of active and passive components on the surface of the semiconductor wafer in a two-step process. First, the pattern on the reticle or masks is transferred into a layer of photoresist. Photoresist is a light-sensitive material that undergoes changes in structure and properties when exposed to light. The process of changing the structure and properties of the photoresist occurs as either negative-acting photoresist or positive-acting photoresist. Second, the photoresist layer is transferred into the wafer surface. The transfer occurs when etching removes the portion of the top layers of semiconductor wafer not covered by the photoresist. The chemistry of photoresists is such that the photoresist remains substantially intact and resists removal by chemical etching solutions while the portion of the top layers of the semiconductor wafer not covered by the photoresist is removed. The process of forming, exposing, and removing the photoresist, as well as the process of removing a portion of the semiconductor wafer can be modified according to the particular resist used and the desired results.

In negative-acting photoresists, photoresist is exposed to light and is changed from a soluble condition to an insoluble condition in a process known as polymerization. In polymerization, unpolymerized material is exposed to a light or energy source and polymers form a cross-linked material that is etch-resistant. In most negative resists, the polymers are polyisopremes. Removing the soluble portions (i.e. the portions not exposed to light) with chemical solvents or developers leaves a hole in the resist layer that corresponds to the opaque pattern on the reticle. A mask whose pattern exists in the opaque regions is called a clear-field mask.

In positive-acting photoresists, photoresist is exposed to light and is changed from relatively nonsoluble condition to much more soluble condition in a process known as photosolubilization. In photosolubilization, the relatively insoluble resist is exposed to the proper light energy and is converted to a more soluble state. The photosolubilized part of the resist can be removed by a solvent in the development process. The basic positive photoresist polymer is the phenol-formaldehyde polymer, also called the phenol-formaldehyde novolak resin. Removing the soluble portions (i.e. the portions exposed to light) with chemical solvents or developers leaves a hole in the resist layer that corresponds to the transparent pattern on the reticle. A mask whose pattern exists in the transparent regions is called a dark-field mask.

After removal of the top portion of the semiconductor wafer not covered by the photoresist, the remainder of the photoresist is removed, leaving behind a patterned layer. Alternatively, some types of materials are patterned by directly depositing the material into the areas or voids formed by a previous deposition/etch process using techniques such as electroless and electrolytic plating.

Depositing a thin film of material over an existing pattern can exaggerate the underlying pattern and create a non-uniformly flat surface. A uniformly flat surface can be beneficial or required to produce smaller and more densely packed active and passive components. Planarization can be used to remove material from the surface of the wafer and produce a uniformly flat surface. Planarization involves polishing the surface of the wafer with a polishing pad. An abrasive material and corrosive chemical are added to the surface of the wafer during polishing. Alternatively, mechanical abrasion without the use of corrosive chemicals is used for planarization. In some embodiments, purely mechanical abrasion is achieved by using a belt grinding machine, a standard wafer backgrinder, or other similar machine. The combined mechanical action of the abrasive and corrosive action of the chemical removes any irregular topography, resulting in a uniformly flat surface.

Back-end manufacturing refers to cutting or singulating the finished wafer into the individual semiconductor die and then packaging the semiconductor die for structural support and environmental isolation. To singulate the semiconductor die, the wafer can be cut along non-functional regions of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor die are mounted to a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections can be made with solder bumps, stud bumps, conductive paste, redistribution layers, or wirebonds. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.

The electrical system can be a stand-alone system that uses the semiconductor device to perform one or more electrical functions. Alternatively, the electrical system can be a subcomponent of a larger system. For example, the electrical system can be part of a cellular phone, personal digital assistant (PDA), digital video camera (DVC), or other electronic communication device. Alternatively, the electrical system can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, application specific integrated circuits (ASIC), logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components. Miniaturization and weight reduction can be beneficial or essential for the products to be accepted by the market. The distance between semiconductor devices must be decreased to achieve higher density.

FIG.1Ashows a plan view of a semiconductor wafer or native wafer10with a base substrate material12, such as, without limitation, silicon, germanium, gallium arsenide, indium phosphide, or silicon carbide, for structural support. A plurality of semiconductor die or components14can be formed on wafer10separated by a non-active, inter-die wafer area or saw street16as described above. The saw street16can provide cutting areas to singulate the semiconductor wafer10into the individual semiconductor die14.

FIG.1Bshows a cross-sectional profile view of a plurality of semiconductor die14from the native wafer10, show inFIG.1A. Each semiconductor die14has a backside or back surface18and an active surface20opposite the backside18. Active surface20contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface20to implement analog circuits or digital circuits, such as DSP, ASIC, memory, or other signal processing circuit. Semiconductor die14may also contain IPDs such as inductors, capacitors, and resistors, for RF signal processing.

An electrically conductive layer22is formed over active surface20using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer22can be one or more layers of aluminum (Al), copper (Cu), Sn, nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive material. Conductive layer22can be, or operate as, contact pads or bond pads electrically coupled or connected to the circuits on active surface20. Conductive layer22can be formed as contact pads disposed side-by-side a first distance from the edge of semiconductor die14, as shown inFIG.1B. Conductive layer22can also be formed as contact pads that are offset in multiple rows such that a first row of contact pads is disposed a first distance from the edge of the die, and a second row of contact pads alternating with the first row is disposed a second distance from the edge of the die. Additionally, conductive layer22can be formed as contact pads that are arranged as a full array of pads distributed over the active area of the semiconductor die or chip. In some instances the contact pads can be arranged in an irregular or asymmetrical array with differing or various spacing among the contact pads.

FIG.1Balso shows an optional insulating or passivation layer26conformally applied over active surface20and over conductive layer22. Insulating layer26can include one or more layers that are applied using PVD, CVD, screen printing, spin coating, spray coating, sintering, thermal oxidation, or other suitable process. Insulating layer26can contain, without limitation, one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), polymer, polyimide, benzocyclobutene (BCB), polybenzoxazoles (PBO), or other material having similar insulating and structural properties. Alternatively, semiconductor die14are packaged without the use of any PBO layers, and insulating layer26can be formed of a different material or omitted entirely. In another embodiment, insulating layer26includes a passivation layer formed over active surface20without being disposed over conductive layer22. When insulating layer26is present and formed over conductive layer22, openings are formed completely through insulating layer26to expose at least a portion of conductive layer22for subsequent mechanical and electrical interconnection. Alternatively, when insulating layer26is omitted, conductive layer22is exposed for subsequent electrical interconnection without the formation of openings.

FIG.1Balso shows conductive bumps, conductive interconnects, or electrical interconnect structures28that can be formed as columns, pillars, posts, thick RDLs, bumps, or studs that are formed of copper or other suitable conductive material, which are disposed over, and coupled or connected to, conductive layer22. When formed as posts28, the posts will have a height greater than a thickness, whereas a pillar has a tin cap and a stud is wider than it is tall. Conductive bumps28can be formed directly on conductive layer22using patterning and metal deposition processes such as printing, PVD, CVD, sputtering, electrolytic plating, electroless plating, metal evaporation, metal sputtering, or other suitable metal deposition process. Conductive bumps28can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, palladium (Pd), or other suitable electrically conductive material and can include one or more layers. In some instances, one or more UBM layers of Al, Cu, Sn, Ni, Au, Ag, Pd, or other suitable electrically conductive material can optionally be disposed between conductive layer22and conductive bumps28. In some embodiments, conductive bumps28can be formed by depositing a photoresist layer over the semiconductor die14and conductive layer22while the semiconductor die14are part of the semiconductor wafer10. A portion of the photoresist layer can be exposed and removed by an etching development process, and the conductive bumps28can be formed as copper pillars in the removed portion of the photoresist and over conductive layer22using a selective plating process. The photoresist layer can be removed leaving conductive bumps28that provide for subsequent mechanical and electrical interconnection and a standoff with respect to active surface20. Conductive bumps28can include a height H1in a range of 5-100 micrometers (μm) or a height in a range of 20-50 μm, or a height of about 25 μm.

FIG.1Balso shows the semiconductor wafer10can undergo an optional grinding operation with a grinder29to planarize the surface and reduce a thickness of the semiconductor wafer10. A chemical etch can also be used to remove and planarize a portion of the semiconductor wafer10.

FIG.1Cshows attaching a die attach film (DAF)30to the semiconductor wafer10that can be disposed over, and in direct contact with, the backsides18of the semiconductor die14. The DAF30can comprise epoxy, thermal epoxy, epoxy resin, B-stage epoxy laminating film, ultraviolet (UV) B-stage film adhesive layer, UV B-stage film adhesive layer including acrylic polymer, thermo-setting adhesive film layer, a suitable wafer backside coating, epoxy resin with organic filler, silica filler, or polymer filler, acrylate based adhesive, epoxy-acrylate adhesive, a polyimide (PI) based adhesive, or other adhesive material.

FIG.1Calso shows semiconductor wafer10can be singulated through gaps or saw streets16using laser grooving, a saw blade or laser cutting tool32, or both to singulate the semiconductor wafer10into individual semiconductor die14with conductive bumps28. The semiconductor die14can then be used as part of a subsequently formed semiconductor component package as discussed in greater detail below with respect toFIGS.2A-4F.

FIG.2Ashows providing a carrier or substrate40, on which subsequent processing of the semiconductor devices, semiconductor component packages, or fully-molded peripheral PoP devices or packages100can occur, as described in greater detail herein. Carrier40may be a temporary or sacrificial carrier or substrate, and in other instances may be or a reusable carrier or substrate.

The carrier40can contain one or more base materials formed in one or more layers, which may comprise base materials such as metal, silicon, polymer, polymer composite, ceramic, perforated ceramic, glass, glass epoxy, stainless steel, mold compound, mold compound with filler, or other suitable low-cost, rigid material or bulk semiconductor material for structural support. When a UV release is used with a temporary carrier40, the carrier40may comprise one or more transparent or translucent materials, such as glass. When a thermal release is used with a temporary carrier40, the carrier40may comprise opaque materials. The carrier40can be circular, square, rectangular, or other suitable or desirable shape and can include any desirable size, such as a size equal to, similar to, or slightly larger or smaller than a reconstituted wafer or panel that is subsequently formed on or over the carrier40. In some instances, a diameter, length, or width of the temporary carrier can be equal to, or about, 200 millimeters (mm), 300 mm, or more.

The carrier40can comprise a plurality of semiconductor die mounting sites or die attach areas42spaced or disposed across a surface of the carrier40, according to a design and configuration of the final semiconductor devices100, to provide a peripheral area or space43. The peripheral area43can partially or completely surround the die attach areas42to provide space for subsequent vertical, through package interconnections, and an area for fan-out routing or build-up interconnect structures.

When a temporary carrier40is used, an optional release layer, interface layer or double-sided tape44can be formed over carrier40as a temporary adhesive bonding film or etch-stop layer. The release layer44may be a film or laminate, and may also be applied by spin coating or other suitable process. The temporary carrier can be subsequently removed by strip etching, chemical etching, mechanical peel-off, CMP, plasma etching, thermal, light releasing process, mechanical grinding, thermal bake, laser scanning, UV light, or wet stripping. While the release layer44is shown inFIG.2A, for convenience and simplicity, the optional release layer44has been omitted from subsequent FIGs. although a person of ordinary skill will understand that the release layer44can remain and be present in processing shown in the other FIGs.

FIG.2Aalso shows forming a seed layer46over the carrier40and the release layer44, when present, so that the seed layer46can be in direct contact with the surface of the carrier40, or in direct contact with the release layer44, when present. The seed layer46can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Titanium (Ti), Tungsten (W) or other suitable electrically conductive material. In some instances, the seed layer46will be, or may include, Ti/Cu, TiW/Cu, W/Cu or a coupling agent/Cu. The formation, placement, or deposition of the seed layer46can be with PVD, CVD, electrolytic plating, electroless plating, or other suitable process. The seed layer46can be deposited by sputtering, electroless plating, or by depositing laminated foil, such as Cu foil, combined with electroless plating.

FIG.2Aalso shows forming or depositing a resist layer or photosensitive layer48over the temporary carrier40. After formation of the resist layer48over the temporary carrier, the resist layer48can then be exposed and developed to form openings50in the resist layer48. As discussed in greater detail below, in some instances more than one photoresist layer48, such as a first photoresist layer48aand a second photoresist layer48bmay be used. Openings50may be formed in the photoresist48, and can be positioned over, or within a footprint of, the peripheral area43of the carrier40. As discussed in greater detail below, in some instances more than one opening or set of openings50may be formed, such as first openings50aformed in photoresist layer48a, and second openings50bformed in second photoresist layer48b. The openings50can extend completely through the resist layer48, such as from a first surface or bottom surface49of the resist layer48to second surface or top surface51of the resist layer48opposite the first surface49. An after development inspection (ADI) of the developed resist layer48and the openings50can be performed to detect the condition or quality of the openings50. After the ADI of resist layer48and openings50, a descum operation can be performed on the developed resist layer48.

FIG.2Bshows the formation of a plurality of conductive interconnects52within the resist layer48that can be formed as columns, pillars, posts, bumps, or studs that are formed of copper or other suitable conductive material. Conductive interconnects52can be formed using patterning and metal deposition processes such as printing, PVD, CVD, sputtering, electrolytic plating, electroless plating, metal evaporation, metal sputtering, or other suitable metal deposition process. When conductive interconnects52are formed by plating, the seed layer46can be used as part of the plating process. Conductive interconnects of posts52can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Pd, solder, or other suitable electrically conductive material and can include one or more layers.

After formation of the conductive interconnects52, the resist layer48can be removed, such as by a stripping process, leaving conductive interconnects52in the peripheral area43around the semiconductor die mounting sites42to provide for subsequent vertical or three dimensional (3D) electrical interconnection for the semiconductor devices100. Conductive interconnects52can include a height H2in a range of 80-300 μm or a height in a range of 100-150 μm, or a height thereabout. In other instances, conductive vertical interconnects52may include a height in a range of 10-600 μm, 60-100 μm, 70-90 μm, or about, 80 μm. As used herein, “thereabout,” “about,” or “substantially” means a percent difference in a range of 0-5%, 1-10%, 1-20%, or 1-30%.

After removal of the resist layer48, or at least one photoresist layer such as48b, the semiconductor die mounting sites42on or over the temporary carrier40can be exposed and ready to receive the semiconductor die14. The orientation of semiconductor die14can be either face up with active surface20oriented away from the temporary carrier40to which the semiconductor die14are mounted, or alternatively can be mounted face down with the active surface20oriented toward the temporary carrier40to which the semiconductor die14are mounted. After mounting the semiconductor die14to the temporary carrier40in a face up orientation, the DAF30can undergo a curing process to cure the DAF30and to lock the semiconductor die14in place over the temporary carrier40.

Alternatively, preformed conductive vertical interconnects52may be formed away from the carrier40, may be placed over the carrier40after formation, such as with a pick and place operation. In some instances, the conductive vertical interconnects52may be part of larger frame (whether integrally or separately formed with the conductive vertical interconnects) with connecting members to maintain a desired spacing or position of the conductive vertical interconnects. In some instances, the conductive vertical interconnects52may be in contact with, surrounded by, or encapsulated or molded with an encapsulant or mold compound that may the same, similar, or different than the encapsulant56disposed around the semiconductor die14.

FIG.2Cshows a top or plan view of a portion of the temporary carrier40and the conductive interconnects52taken along the section line2C fromFIG.2B.FIG.2Cshows that the conductive interconnects52can be formed within, and extend intermittently across, the peripheral area43and surround the semiconductor die mounting sites42without being formed within the semiconductor die mounting sites42.

FIG.2Dshows that after mounting the semiconductor die14to the carrier40, a mold compound or encapsulant56can be deposited around the plurality of semiconductor die14using a paste printing, compression molding, transfer molding, liquid encapsulant molding, lamination, vacuum lamination, spin coating, or other suitable applicator. The mold compound56can be a polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, PBO, polyimide, polymer with or without proper filler. Semiconductor die14can be embedded in mold compound56, which can be non-conductive and environmentally protect the semiconductor die14from external elements and contaminants. The mold compound56can be formed adjacent to and directly contact all lateral sides of the semiconductor die (such as four sides), as well as be formed over the active surface20of the semiconductor die14. The mold compound56can also be formed around and directly contact the sides of the conductive bumps28and the conductive interconnects52to form a reconstituted panel, reconstituted wafer, molded panel, or molded wafer58.

The reconstituted panel58can optionally undergo a curing process or post mold cure (PMC) to cure the mold compound56. In some instances, a top surface, front surface, or first surface62of the mold compound56can be substantially coplanar with first end53of the conductive interconnects52. Alternatively, the top surface62of the mold compound56can be over, offset, or vertically separated from the first ends53of the conductive interconnects52, such that the first ends53of the conductive interconnects52are exposed with respect to the encapsulant56after the reconstituted wafer58undergoes a grinding operation.

The reconstituted panel58can also undergo an optional grinding operation with grinder64to planarize the top surface, front surface, or first surface68of the reconstituted panel58and to reduce a thickness of the reconstituted panel58, and to planarize the top surface62of the mold compound56and to planarize the top surface68of the reconstituted panel58. The top surface68of the reconstituted panel58can comprise the top surface62of the mold compound56, the first ends of the conductive interconnects52, or both. A chemical etch can also be used to remove and planarize the mold compound56and the reconstituted panel58. Thus, the top surface68of the conductive interconnects52can be exposed with respect to mold compound56in the peripheral area43to provide for electrical connection between semiconductor die14and a subsequently formed redistribution layer or build-up interconnect structure70.

The reconstituted wafer58can also undergo a panel trim or trimming to remove excess mold compound56that has remained in undesirable locations as a result of a molding process, such as eliminating a flange present for a mold chase. The reconstituted panel58can include a footprint or form factor of any shape and size including a circular, rectangular, or square shape, the reconstituted wafer58comprising a diameter, length, or width of 200 millimeter (mm), 300 mm, or any other desirable size.

FIG.2Dalso shows that actual positions of the semiconductor die14within the reconstituted panel58may be measured with an inspection device or optical inspection device59. As such, subsequent processing of the fully molded panel58as shown and described with respect to subsequent FIGs. can be performed with respect to the actual positions of the semiconductor die14within the reconstituted panel58.

FIG.2Eshows forming a build-up interconnect structure70over the molded panel58to electrically connect, and provide routing between, conductive interconnects52and the conductive bumps28. While the build-up interconnect structure70is shown comprising three conductive layers and three insulating layer, a person of ordinary skill in the art will appreciate that fewer layers or more layers can be used depending on the configuration and design of the semiconductor device100. The build-up interconnect structure70can optionally comprise a first insulating or passivation layer72formed or disposed over the reconstituted panel58. The first insulating layer72can comprise one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, polymer, polyimide, BCB, PBO, or other material having similar insulating and structural properties. The insulating layer72can be formed using PVD, CVD, printing, spin coating, spray coating, sintering or thermal oxidation. Openings or first level conductive vias can be formed through the insulating layer72over the conductive interconnects52and the conductive bumps28to connect with the semiconductor die14.

A first conductive layer74can be formed over the reconstituted panel58and over the first insulating layer72as a first RDL layer to extend through the openings in the first insulating layer72, to electrically connect with the first level conductive vias, and to electrically connect with the conductive bumps28and the conductive interconnects52. Conductive layer74can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material formed using a patterning and metal deposition process such as sputtering, electrolytic plating, and electroless plating, or other suitable process.

A second insulating or passivation layer76, which can be similar or identical to the first insulating layer72, can be disposed or formed over the reconstituted panel58, the first conductive layer74, and the first insulating layer72. An opening or second level conductive via can be formed through the second insulating layer76to connect with the first conductive layer74.

A second conductive layer78, when desirable and when present, may be similar or identical to the first conductive layer74, can be formed as a second RDL layer over reconstituted panel58, over the first insulating layer72, over the first conductive layer74, over the second level conductive via, or within an opening of the second insulating layer72, to electrically connect with the first conductive layer74, the first level and second level conductive vias, and the semiconductor die14.

A third insulating or passivation layer80, when desirable and when present, may be similar or identical to the first insulating layer72, can be disposed or formed over the second conductive layer78and the second insulating layer76. An opening or a third level conductive via can also be formed in or through the third insulating layer80to connect with the second conductive layer78.

A third conductive layer or UBMs82can be formed over the third insulating layer80and the third level conductive via to electrically connect with the other conductive layers and conductive vias within the build-up interconnects structure70, as well as electrically connect to the semiconductor die14, the conductive bumps28, and the conductive interconnects52. UBMs82, like all of the layers, plating layers, or conductive layers formed by a plating process as presented herein, can be a multiple metal stack comprising one or more of an adhesion layer, barrier layer, seed layer, or wetting layer. The adhesion layer can comprise titanium (Ti), or titanium nitride (TiN), titanium tungsten (TiW), Al, or chromium (Cr). The barrier layer can be formed over the adhesion layer and can be made of Ni, NiV, platinum (Pt), palladium (Pd), TiW, or chromium copper (CrCu). In some instances the barrier layer can be a sputtered layer of TiW or Ti and can serve as both the adhesion layer and the barrier layer. In either event, the barrier layer can inhibit unwanted diffusion of material, like Cu. The seed layer can be Cu, Ni, NiV, Au, Al, or other suitable material. For example, the seed layer can be a sputtered layer of Cu comprising a thickness of about 2000 angstroms (e.g., 2000 plus or minus 0-600 angstroms). The seed layer can be formed over the barrier layer and can act as an intermediate conductive layer below subsequently formed bumps, balls, or interconnect structures94. In some instances, the wetting layer can comprise a layer of Cu with a thickness in a range of about 5-11 μm or 7-9 μm. Bumps94, such as when formed of SnAg solder, can consume some of the Cu UBM during reflow and forms an intermetallic compound at the interface between the solder bump94and the Cu of the wetting layer. However, the Cu of the wetting layer can be made made thick enough to prevent full consumption of the Cu pad by the solder during high temperature aging.

UBMs82may be formed as a PoP UBM pad, UBM structure, or land pad, such as for stacked PoP structure, an additional electronic component, as well as for a surface mount structure86, such as a any active or passive semiconductor devices, chip, or integrated circuit passive device, including, e.g., a capacitor. In some instances, the UBMs82can comprise Ni, Pd and Au. UBMs82can provide a low resistive interconnect to build-up interconnect structure70as well as a barrier to solder diffusion and seed layer for solder wettability.FIG.2Fshows an example of capacitors86coupled to UBMs82as part of the semiconductor device100.

FIG.2Fshows removing the temporary carrier40, to expose the second ends54of the conductive interconnects52. The carrier40can be removed, e.g., by grinding the carrier40, by exposing UV release tape44to UV radiation separate the UV tape44from the glass substrate40, by thermal release, or other suitable method. After removal of the carrier40, the reconstituted panel58can also undergo an etching process, such as a wet etch, to clean the surface of the reconstituted panel58exposed by removal of the temporary carrier40, including the exposed second ends54of the conductive interconnects52. The exposed second ends54of the conductive interconnects52can also undergo a coating or pad finishing process, such as by an Organic Solderability Preservative (OSP) coating, solder printing, electroless plating, or other suitable process, to form a PoP UBM pad, UBM structures, land pads, or other suitable structure, as desired.

Bumps, balls, or interconnect structures94, can be formed on the exposed second ends54of the conductive interconnects52. The bumps94can be formed by depositing an electrically conductive bump material over the exposed second ends54of the conductive interconnects52using an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, bismuth (Bi), Cu, solder, and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn/Pb, high-lead solder, or lead-free solder. The bump material can be bonded to the exposed second ends54of the conductive interconnects52using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form spherical balls or bumps94. In some applications, bumps94are reflowed a second time to improve electrical contact to conductive interconnects52. The bumps94can also be compression bonded or thermocompression bonded to the conductive interconnects52. Bumps94represent one type of interconnect structure that can be formed over the conductive interconnects52, and other desirable structures, such as conductive paste, stud bump, micro bump, or other electrical interconnects may also be used as desired.

FIG.2Falso shows singulation of the molded panel58and build-up interconnect structure70with saw blade or laser cutting tool88to form individual semiconductor devices or packages100. The final structure may be thinner than previous packages, comprising an overall height or thickness of, or on the order of, or about, 50-100, 50-80, or less than or about 100 μm. Stacks of multiple layers can be correspondingly thicker, and increase in multiples of the above ranges, resulting in an overall thickness in a range of 200-1,000 μm. As part of the reduced height of the structure, the final structure may be made without an interposer, comprising the build-up interconnect layers and conductive vertical providing the function of an interposer, and serving as s sort of embedded interposer.

FIG.2Gshows a cross-sectional profile view of a final semiconductor device100, similar to the view shown inFIG.2F, but with the view inFIG.2Gshown with the features of the device100more closely to scale.FIG.2Gshows the peripheral conductive interconnect structures52disposed around, and laterally offset from, the semiconductor die14and within the encapsulant material56. The peripheral conductive interconnect structures52can extend completely through the encapsulant56in a vertical direction from the top surface62of the encapsulant56to, or adjacent, the bottom surface66of the encapsulant56opposite top surface62to provide vertical electrical interconnection through the semiconductor device100, which can facilitate stacking of packages in PoP arrangements.

FIGS.2H and2Ishow close-up views of a portion of the cross-sectional profile view of the semiconductor device100shown inFIG.2G, taken at the section line2H-2I.FIG.2Hshows the device100with the surface mount device86exposed, andFIG.2Ishows encapsulant or mold compound96, which is similar or identical to mold compound or encapsulant56, disposed around the surface mount device86.FIG.2Hshows that the backside18of the die14can comprise the DAF30used to attach the die14face-up to the temporary carrier40during the encapsulation process with the mold compound56, the DAF30becoming a part of a final structure of the semiconductor device100. The DAF30can be exposed after removal of the carrier40, or with the removal of the carrier40. Keeping the DAF30as part of the semiconductor device100can balance a thermal expansion mismatch at both sides18,20of the semiconductor die14, thereby reducing warpage of the package100.

FIG.2Jshows a view of a semiconductor device100similar to the semiconductor device100shown inFIG.2I.FIG.2Jdiffers fromFIG.2Iwith the inclusion of recessed portion67of the bottom surface, back surface, or second surface66of mold compound56around the second ends54of the conductive posts52. A height Ho of the offset67may be in a range of 5-50 μm or about 25 μm, with the height Ho being the same as, or similar to, a height HDof the DAF30.

FIG.2Kshows a close-up view of a portion ofFIG.2Jshown within section line2K.FIG.2Kprovides additional detail of the structure of the offset67and the protrusion of the second ends54of the conductive posts52from the encapsulant56, which results in an exposed sidewall55of the post or conductive interconnect52that is not in contact with the encapsulant56, but may be in contact with, and disposed within the bumps94. With exposed sidewalls55and second ends54of conductive posts52within the bumps94, a structural strength of the bond between the bumps94and the posts or conductive interconnects52is improved, and an overall package height of semiconductor device100may be reduced.

FIG.2Kalso shows that a rim or edge65of mold compound or encapsulant56may contact, extend from, and wrap around the DAF30at the backside18of semiconductor die14, and comprise a width We in a range of 10-100 μm, 20-50 μm, or about 25 μm, with the width We being the same as, or similar to, the height Ho. The structure ofFIGS.2J and2Kis further discussed with respect to the structure, method, and process shown inFIGS.3A-3J.

FIG.2Lshows a view of a semiconductor device100similar to the view of the semiconductor device100shown inFIG.2J.FIG.2Ldiffers fromFIG.2Jwith the bottom surface66of the encapsulant56being level, flush, or co-planar with a bottom surface of the DAF30. Semiconductor device100ofFIG.2Lfurther comprises a recess57in mold compound56that extends from the bottom surface66of the encapsulant to the second end54of post52. Recess57comprises a depth that is in a range of 5-50 μm, or about 25 μm, with the depth of recess57being the same as, or similar to, the height HDof the DAF30. Recess57is thereby configured to receive a portion of the bump94within the recess57to reduce an overall package height of the semiconductor device100. The structure ofFIG.2Lis further discussed with respect to the structure, method, and process shown inFIGS.3A-3F and3J.

FIGS.3A-3Jshow a process or method of forming a semiconductor device, semiconductor component package, or fully-molded peripheral PoP devices or package100by using one or more photoresist layers, such as a first photoresist layer48aand a second photoresist layer48b. A conductive seed layer46or second conductive seed layer46bmay be disposed between the first photoresist layer48aand a second photoresist layer48b.

FIG.3Ashows an optional release layer44and an optional seed layer46formed over a carrier40, as described inFIG.2A. The seed layer46may serve as a protective barrier for the release layer44, when present, until the release layer is activated for removal of the carrier40. WhileFIG.2Adescribes the formation of openings50in photoresist layer48for the formation of conductive interconnects or posts52,FIGS.3B-3Gshow various instances in which the conductive interconnects or posts52may be formed with more than one photoresist48.

FIG.3Bshows a first planar photoresist layer48formed over the wafer40, and optionally over the release layer44and the seed layer46or first seed layer46a. A height of the first photoresist layer may be equal to a height HDof the DAF30, such as in a range of 5-50 μm or about 10, 15, or 25 μm. Each of the photo resist layers48, whether layer48,48a, or48b, may be made of materials similar or identical to each other and formed, placed, positioned, or made with methods similar or identical to those described for each other.

FIG.3Cshows the first photoresist layer48amay be patterned to form first openings50a, to provide for the subsequent offset67or recess57in the mold compound56. After patterning the first photoresist48a, a second conductive layer or seed layer46bis formed. The second seed layer46bmay be made of materials similar or identical to those described with respect to seed layer46, and with methods similar or identical to those described for seed layer46. The second conductive seed layer46bmay be non-planar and may be conformally applied over the patterned first photoresist layer48aand extend into the first openings50a. The second conductive seed layer46bcan provide a barrier between the first photoresist layer48athat will remain for subsequent processing, such as the formation of conductive interconnects or posts52, after the removal of the second photoresist layer48bthat will be formed over, and then stripped from, the second seed layer46b.

FIG.3Dshows the second photoresist layer48bmay be formed over, and conformally follow, the second seed layer46band the first patterned photoresist layer48a, together with the first openings50aformed in the first patterned photoresist layer48a. The second photoresist layer48bmay patterned to form second openings50b. The second openings50bmay be filled with conductive material to form the conductive interconnects or posts52. In some instances, the second openings50bmay be aligned with, and formed within the first openings50a, as shown, e.g., inFIG.3D. In other instances, the second openings50bmay be offset from, and not be formed within the first openings50a, as shown, e.g., inFIG.3Fto provide for the subsequent offset67or recess57in the mold compound56. The conductive interconnects or post52may be formed by a suitable process, such as by an electroplating process in which the second seed layer46bprovides the electrical current for the electroplating process.

FIG.3Eshows close up profile view of the conductive interconnect or post52formed within the first opening50aand the second opening50b, as taken from within the section line3E shown inFIG.3D.FIG.3Efurther shows the additional detail of a step, offset, or discontinuity52bin the sidewall52aof the conductive post52. A width Ws of the step52bat the interface of the first photoresists48aand the second photoresist48bwithin the second opening50bmay be in a range of 0-15 μm, or thereabout, and may further comprise a change in angle of the sidewall of the first opening50aand the second opening50b, which may further result in a change in angle of the sidewall52aof the conductive post52.

FIG.3Fdiffers fromFIG.3Eby showing that the second openings50bin the second photoresist layer48bmay be offset from, and not be formed within the first openings50a. The second openings50bmay instead be aligned with the tops of the patterned first photoresist48a. As such, when the second openings50bare filled with conductive material to form the conductive interconnects52, the conductive interconnects52are formed over the first photoresist48a, with the ends54of the conductive posts52offset from the lower surface66of the encapsulant56by the recess57, and at a distance of 5-50 μm or about 25 μm, to provide the structure shown inFIG.3K.

FIG.3G, continuing fromFIG.3D, shows that before removal of the carrier40, a thickness of photoresist48aaround, and in a periphery of, the lower ends54of the conductive vertical interconnects52is present, and provides for the recessed portion67of bottom surface66of mold compound56, as shown inFIG.3J. While not drawn to scale, as a point of reference the carrier40may have a height of about 350-400 μm while the semiconductor die may have a height of about 80-100 μm and the semiconductor device100a total height of about 100-150 μm, so that an overall height of the carrier40semiconductor device100together will be about 500 μm.

FIG.3H, similar toFIG.3G, shows that before removal of the carrier40, a thickness of photoresist48around, and in a periphery of, the lower ends54of the conductive vertical interconnects52is present, and provides for the recessed portion67of bottom surface66of mold compound56. However,FIG.3Hdiffers fromFIG.3Gin that the resist48is not the first resist48athat remains after the removal or stripping of the second resist48band removal or etching of the second seed layer46b. Instead, the resist40cmay be a liquid photoresist that is formed by spin coating or other suitable method, after the formation of the conductive posts or interconnects52, and after the removal of the resist layer48used in the formation of the conductive posts or interconnects52.

FIG.3I, continuing fromFIG.3G or3H, shows the encapsulant or mold compound56formed around the semiconductor die14, the conductive bumps28, the conductive posts52similar to what was shown and described with respect toFIG.2D. The semiconductor device ofFIG.3Idiffers from the semiconductor device ofFIG.2Bby the inclusion of the encapsulant or mold compound56being disposed around, and contacting, the first photoresist48a.

FIG.3Jcontinuing fromFIG.3G or3H, shows a structure of semiconductor device100similar to that shown in, and described with respect to,FIG.2K. The stackable fully molded flip chip semiconductor structure with vertical Interconnects100shown inFIG.3J, is shown with fine-pitch bumps or solder balls94coupled to the conductive posts52. The conductive bumps or solder balls94may comprise a width or diameter of about 50-100 μm, such as at or about 80 μm spacing.

After grinding to remove the carrier, a portion of the photoresist48aand a lower portion or end54of the conductive vertical interconnects52may also be removed, to leave a thickness Ho of photoresist48aequal to a thickness HD of the DAF30. After grinding and removal of a portion of the photoresist48, a remaining portion of the photoresist48may be removed to leave ends54of the conductive vertical interconnects52exposed, and the remaining portion of the photoresist48that may have small amounts of metal included in its surface after the grinding of the conductive vertical interconnects52may also be removed. The additional standoff, offset, or height Ho may provide improved access or clearance for cleaning processes, or for molded underfill (MUF) that may be used after mounting the semiconductor device100to a PCB or other substrate.

The DAF30may comprise a thickness greater than a final thickness of the encapsulant56disposed over the active surface20of the semiconductor die18, or in other words, greater than a height of the conductive bumps28. However, a portion of the DAF30may also be removed until a thickness or height HDof the DAF30is equal, or about equal, to a thickness of the encapsulant over the active surface of the semiconductor die. By retaining a layer of DAF30over the backside18of the semiconductor die14, portions of the conductive material from the conductive vertical interconnects52, such as copper, may be prevented from coming into contact or migrating into the base material of the semiconductor die14(such as silicon) of the and damaging performance of the semiconductor die14.

FIG.3K, continuing fromFIG.3F, shows conductive interconnects52, after the removal of the first photoresist48a. By removing the first photoresist48a, the ends54of the conductive posts52offset from the lower surface66of the encapsulant56by the recess57. The recess57comprises a distance of 5-50 μm or about 25 μm from the lower surface66the ends54of the conductive posts52, similar to the structure shown in, and described with respect to,FIG.2L.

FIG.3K, likeFIG.3J, is shown with fine-pitch bumps or solder balls94coupled to the conductive posts52. The conductive bumps or solder balls94may comprise a width or diameter of about 50-100 μm, such as at or about 80 μm spacing.

FIGS.4A-4Fshow various views and arrangements of Stackable Fully Molded BGA Semiconductor Structure with Vertical Interconnects similar to the semiconductor device100shown and described previously. In each instance, PoP semiconductor devices102,104,106,108and110are formed without solder balls or bumps94disposed between, or among, the vertically separated PoP layers that comprise the semiconductor die14.

FIGS.4A and4B, show a Stackable Fully Molded BGA Semiconductor Structure with Vertical Interconnects102and additional electronic components86mounted over the top or upper build-up interconnect structure70a at a top of the semiconductor structure102. Semiconductor device102differs from semiconductor device100, shown e.g. inFIG.2H, by the inclusion of a back side or lower build-up interconnect structure70b, which may be formed on the carrier before the mounting of the semiconductor die14to the carrier40and before the formation of the conductive vertical interconnects52. With the lower build-up interconnect structure70b, bumps94may be formed as part of a ball grid array (BGA) and be positioned within a footprint of the semiconductor die14. The bumps94may also be formed partially or completely within or without of the footprint of the semiconductor die14.

FIG.4Bdiffers fromFIG.4A, by further including the additional feature of a second layer of encapsulant or mold compound96that may optionally be formed over the additional electronic components86and the build-up interconnect structure70a. By including the second layer of encapsulant96, additional protection to the electronic components86is provided, as well as providing additional rigidity and structural strength to facilitate subsequent handling, such as removal from the carrier40and formation of the bumps94.

FIG.4C, shows another embodiment of a semiconductor device or a Stackable Fully Molded BGA Semiconductor Structure with Vertical Interconnects and Components104.FIG.4Cdiffers fromFIGS.4A and4Bby comprising more than one vertically stacked layer of encapsulated semiconductor die and conductive vertical interconnects disposed around the periphery of the semiconductor die. More specifically,FIG.4Cshows the lower layer of semiconductor device104formed of semiconductor device102coupled or vertically stacked in a PoP arrangement with a semiconductor device100disposed over the semiconductor device102. The POSA will appreciate that any desirable number of vertically stacked layers may be incorporated into the structure, such as three, four, or more layers. In some instances, additional electronic components86may be mounted or incorporated not only at the top of the package, but in one or more of the vertically stacked layers comprising semiconductor die14. For example, additional electronic components may be disposed around a periphery or outside a footprint of the semiconductor die, and also be encapsulated or covered by the encapsulant or mold compound.

FIG.4D, shows another embodiment of a semiconductor device or a Stackable Fully Molded BGA Semiconductor Structure with Vertical Interconnects and Components106. Semiconductor device106comprises two vertically stacked layers of face-up semiconductor die with the lower semiconductor die14bcomprising a larger footprint, and the upper semiconductor die14acomprising smaller footprints contained within the footprint of the larger lower semiconductor die14b.FIG.4Ddiffers fromFIGS.4A and4Bby omitting the additional electronic components86from the top of the structure, and by placing the bumps or solder balls94at the top of the semiconductor device106rather than at the bottom of the semiconductor device (as described with respect to a face up orientation of the semiconductor die14.) The bottom side or backside of the semiconductor device106also shows that a bottom side build-up interconnect structure may be omitted, and the balls can be reflowed while still coupled to the carrier40, and a second carrier may be disposed over the bumps94for the removing of the original carrier40used during processing, such as by grinding, or other suitable process.

FIG.4Eshows a stacked PoP arrangement or 3D embedded stackable component comprising a semiconductor device108in which, the lower single semiconductor die14bis oriented face-up, and comprises a large footprint. Above the lower, large-footprint semiconductor die14b, the upper layer comprises two additional semiconductor die14ain a side by side arraignment, both disposed over, and within a footprint of, the lower semiconductor die14b. The upper side by side semiconductor die14afurther comprise conductive vertical interconnects52disposed at a periphery of the die14a, included at a shared periphery between the semiconductor die14a. A thickness or height of the upper and lower semiconductor die14aand14bmay be equal or substantially equal. While two layers of vertically stacked semiconductor die14, such as semiconductor die14aand14bare shown being interconnected with conductive posts52and build-up interconnect layers70, any desirable number of layers may be used in forming the stacked PoP arrangement or 3D embedded stackable component. For example, in some instances three, four, or more layers of molded or embedded semiconductor die14may be used. In some instances, all of the layers within the semiconductor device108may be formed over a single carrier, such as to form a PoP structure without intermediate solder bumps or balls94. In other instances, layers of the stacked PoP arrangement or 3D embedded stackable component may be formed over different wafers and then later joined.

FIG.4Ealso omits the additional electronic components86from the top of the structure, and places the balls of solder bumps94at the top of the structure108rather than at the bottom of the structure. Additionally, the backside of the structure also shows that the bottom side build-up interconnect structure70may also be omitted, and the balls94can be reflowed while still coupled to the carrier40, and a second temporary carrier may be disposed over the bumps94for the removing of the original carrier40used during processing, such as by grinding, or other suitable process. A POSA will appreciate the additional electronic components86as well as various arrangements of build-up interconnect structures70and balls or bumps94may also be included according to a configuration, arrangement, or design of the semiconductor device108.

FIG.4Fshows a semiconductor device or Stackable Fully Molded BGA Semiconductor Structure with Vertical Interconnects110comprising a stacked PoP arrangement or 3D embedded stackable component.FIG.4Fdiffers fromFIG.4Eby disposing the semiconductor die14awith the larger footprint above or over the two semiconductor die14bwith smaller footprints. While two layers of vertically stacked semiconductor die14, such as semiconductor die14aand14bare shown being interconnected with conductive posts52and build-up interconnect layers70, any desirable number of layers may be used in forming the stacked PoP arrangement or 3D embedded stackable component. For example, in some instances three, four, or more layers of molded or embedded semiconductor die14may be used. In some instances, all of the layers within the semiconductor device110may be formed over a single carrier, such as to form a PoP structure without intermediate solder bumps or balls94. In other instances, layers of the stacked PoP arrangement or 3D embedded stackable component may be formed over different wafers and then later joined.

Like the semiconductor device108ofFIG.4E, the semiconductor device110ofFIG.4Falso omits the additional electronic components86from the top of the structure, and places the bumps or solder balls94at the top of the structure rather than at the bottom of the structure (as described with respect to a face up orientation of the semiconductor die14.) Additionally, the backside of the semiconductor device110also shows that the bottom side build-up interconnect structure may be omitted, and the bumps or solder balls94can be reflowed while still coupled to the carrier40. A second temporary carrier may be disposed over the bumps94for the removing of the original carrier40used during processing, such as by grinding, or other suitable process. A POSA will appreciate the additional electronic components86as well as various arrangements of build-up interconnect structures70and balls or bumps94may also be included according to a configuration, arrangement, or design of the semiconductor device110.

While this disclosure includes a number of embodiments in different forms, the particular embodiments presented are with the understanding that the present disclosure is to be considered as an exemplification of the principles of the disclosed structures, devices, methods, and systems, and is not intended to limit the broad aspect of the disclosed concepts to the embodiments illustrated. Additionally, it should be understood by those of ordinary skill in the art that other structures, manufacturing devices, and examples could be intermixed or substituted with those provided. In places where the description above refers to particular embodiments, it should be readily apparent that a number of modifications may be made without departing from the spirit thereof and that these embodiments and implementations may be applied to other technologies as well. Accordingly, the disclosed subject matter is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the disclosure and the knowledge of one of ordinary skill in the art. As such, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the inventions as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.