Patent ID: 12228833

DETAILED DESCRIPTION

The invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numbers indicate the same components throughout the specification. In the attached figures, the thickness of layers and regions is exaggerated for clarity.

It will be understood that, although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the teachings of the invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one,” unless the content clearly indicates otherwise. “Or” means “and/or.” As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Hereinafter, preferred embodiments of the invention will be described in detail with reference to the accompanying drawings.

FIG.1is a plan view of an exemplary embodiment of a pixel of a liquid crystal display (“LCD”) device according to the invention,FIG.2is a cross-sectional view taken along line I-I′ ofFIG.1,FIG.3is a cross-sectional view taken along line II-II′ ofFIG.1,FIG.4is a cross-sectional view taken along line III-III′ ofFIG.1, andFIG.5is an enlarged plan view of an area A ofFIG.1.

Referring toFIGS.1through5, the LCD device may include a first display substrate100, a second display substrate200, and a liquid crystal layer300.

Switching elements for controlling the alignment of liquid crystal molecules LC disposed in the liquid crystal layer300, such as, for example, first, second, and third thin-film transistors (“TFTs”) TR1, TR2, and TR3, may be disposed on the first display substrate100. The second display substrate200is a substrate disposed to face the first display substrate100.

The liquid crystal layer300may be interposed between the first and second display substrates100and200and may include a plurality of liquid crystal molecules LC having dielectric anisotropy. In response to an electric field being applied between the first and second display substrates100and200, the liquid crystal molecules LC may rotate in a particular direction between the first and second display substrates100and200and may thus transmit or block transmission of light therethrough. Hereinafter, the term “rotation” means not only the actual rotation of the liquid crystal molecules LC, but also the change of the alignment of the liquid crystal molecules LC by the electric field.

The LCD device includes a plurality of pixels PX, which are arranged in a matrix form. The plurality of pixels PX may be basic units for displaying colors, and the gray levels of the plurality of pixels PX may be independently controllable. Each of the plurality of pixels PX includes first and second light-transmitting areas PNA1and PNA2, which actually display colors by transmitting light incident thereupon from below the first display substrate100therethrough so as for the light to travel toward the top of the second display substrate200.

The first display substrate100will hereinafter be described.

The first display substrate100may include a first base substrate110. The first base substrate110may be a transparent insulating substrate. In an exemplary embodiment, for example, the first base substrate110may be a glass substrate, a quartz substrate, a transparent resin substrate, or the like.

In some exemplary embodiments, the first base substrate110may be curved in one direction. In some other exemplary embodiments, the first base substrate110may have flexibility. That is, the first base substrate110may be rollable, foldable, or bendable in the exemplary embodiments.

A gate line GL, a first gate electrode GE1, a second gate electrode GE2, a third gate electrode GE3, a first sustain electrode CST1, and a second sustain electrode CST2may be disposed on the first base substrate110.

The gate line GL transmits a gate voltage, which controls the first, second, and third TFTs TR1, TR2, and TR3. The gate line GL may extend in a first direction dr1.

The first direction dr1, which is a direction intersecting a second direction dr2(described later), may be a direction extending in parallel to one side of the first base substrate110on a plane where the first base substrate110is disposed, and may be defined as, but is not limited to, a direction indicated by an arbitrary straight line extending from the left to the right ofFIG.1. The second direction dr2may be defined as a direction indicated by an arbitrary straight line extending from the top to the bottom ofFIG.1. However, the first and second directions dr1and dr2are not limited thereto. In some exemplary embodiments, directions, indicated by two arbitrary straight lines extending to intersect perpendicular to each other over the plane where the first base substrate110is disposed, may be defined as the first and second directions dr1and dr2.

The gate voltage may be provided from outside of the LCD device and may have a variable level. The turning on/off of the first, second, and third TFTs TR1, TR2, and TR3may be controlled according to the level of the gate voltage.

The first, second, and third gate electrodes GE1, GE2, and GE3may be disposed to protrude from the gate line GL and may be physically connected to the gate line GL. The first, second, and third gate electrodes GE1, GE2, and GE3may be the elements of the first, second, and third TFTs TR1, TR2, and TR3, respectively.

In some exemplary embodiments, in a case where the first, second, and third gate electrodes GE1, GE2, and GE2are disposed adjacent to one another, as illustrated inFIG.1, the first, second, and third gate electrodes GE1, GE2, and GE2may be integrally disposed as a single protrusion from the gate line GL.

The first and second sustain electrodes CST1and CST2are disposed on the first base substrate110and may be positioned in the same layer as the gate line GL. The first and second sustain electrodes CST1and CST2generally extend in the first direction dr1, but may include portions extending to the boundaries of the first and second light-transmitting areas PNA1and PNA2.

The first sustain electrode CST1, unlike the second sustain electrode CST2, may be connected to a pair of adjacent two pixels PX arranged along the first direction dr1. That is, the first sustain electrode CST1may extend across multiple pixels PX along the first direction dr1, and a voltage may be transmitted to each of the multiple pixels PX via the first sustain electrode CST1. The second sustain electrode CST2may be electrically connected to the first sustain electrode CST1via a third contact hole CNT3, a fourth contact hole CNT4, and a third source electrode SE3(described later), and may receive a voltage from the first sustain electrode CST1.

The first sustain electrode CST1may provide a sustain voltage received from the outside to the third TFT TR3(described later). The sustain voltage may have a uniform level and may be lower than the maximum level of a data voltage, which is provided to a data line DL, and higher than the minimum level of the data voltage.

The first sustain electrode CST1may be disposed adjacent to, or overlap with a first sub-pixel electrode SPE1(described later), and a predetermined capacitance may be formed between the first sub-pixel electrode SPE1and the first sustain electrode CST1. Accordingly, a sudden drop of the voltage provided to the first sub-pixel electrode SPE1can be effectively prevented.

Similarly, the second sustain electrode CST2may be disposed adjacent to, or overlap with a second sub-pixel electrode SPE2(described later), and a predetermined capacitance may be formed between the second sub-pixel electrode SPE2and the second sustain electrode CST2. Accordingly, a sudden drop of the voltage provided to the second sub-pixel electrode SPE2can be effectively prevented.

The gate line GL, the first, second, and third gate electrodes GE1, GE2, and GE3, and the first and second sustain electrodes CST1and CST2may include the same material. In an exemplary embodiment, for example, the gate line GL, the first, second, and third gate electrodes GE1, GE2, and GE3, and the first and second sustain electrodes CST1and CST2may include an aluminum (Al)-based metal such as Al or an Al alloy, a silver (Ag)-based metal such as Ag or an Ag alloy, a copper (Cu)-based metal such as Cu or a Cu alloy, a molybdenum (Mo)-based metal such as Mo or a Mo alloy, chromium (Cr), tantalum (Ta), or titanium (Ti). The gate line GL, the first, second, and third gate electrodes GE1, GE2, and GE3, and the first and second sustain electrodes CST1and CST2may have a single-layer structure or may have a multilayer structure including at least two conductive films having different physical properties.

A first insulating layer120is disposed on the gate line GL, the first, second, and third gate electrodes GE1, GE2, and GE3, and the first and second sustain electrodes CST1and CST2. In an exemplary embodiment, the first insulating layer120may be formed of an insulating material such as, for example, silicon nitride or silicon oxide. The first insulating layer120may have a single-layer structure or may have a multilayer structure including at least two insulating films having different physical properties.

A semiconductor layer SM may be disposed on the first insulating layer120. The semiconductor layer SM may overlap at least partially with the first, second, and third gate electrodes GE1, GE2, and GE3. The semiconductor layer SM may include amorphous silicon, polycrystalline silicon, or an oxide semiconductor.

The semiconductor layer SM may overlap not only with the first, second, and third gate electrodes GE1, GE2, and GE3, but also with the data line DL, first, second, and third source electrodes SE1, SE2, and SE3, and first and second drain electrodes DE1and DE2(described later). The semiconductor SM and the data line DL may be disposed to overlap with each other because the layer in which the semiconductor layer SM and the data line DL are disposed is fabricated using a single mask (not illustrated). In a case where the semiconductor SM and the data line DL are disposed in different layers using different masks, the semiconductor layer SM may not overlap with the data line DL.

Although not specifically illustrated, in some exemplary embodiments, part of the region where the first, second, and third TFTs TR1, TR2, and TR3are disposed may be doped with a high concentration of n- or p-type impurities. This doped region may be omitted in a case where the semiconductor layer SM comprises an oxide semiconductor.

The data line DL, the first, second, and third source electrodes SE1, SE2, and SE3, and the first and second drain electrodes DE1and DE2may be disposed on the semiconductor layer SM and the first insulating layer120.

The data line DL may extend in the second direction dr2to intersect the gate line GL.

The data line DL may be insulated from the gate line GL, the first, second, and third gate electrodes GE1, GE2, and GE3, and the first and second sustain electrodes CST1and CST2by the first insulating layer120.

The data line DL may provide the data voltage to the first and second source electrodes SE1and SE2. The data voltage may be provided from the outside of the LCD device and may have a variable level. The gray levels of the plurality of pixels PX may vary according to the level of the data voltage.

The first source electrode SE1may be branched from the data line DL such that at least part thereof may overlap with the first gate electrode GE1. Accordingly, the first source electrode SE1may receive the data voltage from the data line DL.

The second source electrode SE2may be branched from the data line DL such that at least part thereof may overlap with the second gate electrode GE2, but the invention is not limited thereto. Alternatively, as illustrated inFIG.1, the second source electrode SE2may be branched from the first source electrode SE1to receive the data voltage from the first source electrode SE1.

The third source electrode SE3may be physically spaced apart, and electrically insulated, from the data line DL. As illustrated inFIG.1, the third source electrode SE3may be connected to the first sustain electrode CST1via the third contact hole CNT3, which passes through the first insulating layer120, and may partially overlap with the third gate electrode GE3. Accordingly, the third source electrode SE3may receive the sustain voltage from the first sustain electrode CST1.

As illustrated inFIG.1, the first drain electrode DE1may be spaced apart from the first source electrode SE1with the semiconductor layer SM disposed therebetween and may at least partially overlap with the first gate electrode GE1. A partial region, of the semiconductor layer SM, disposed between the first drain electrode DE1and the first source electrode SE1may be defined as a first active region AR1. In the first active region AR1, a first channel may be formed such that the first drain electrode DE1and the first source electrode SE1can be electrically connected to each other according to the gate voltage. The first channel may be controlled by the gate voltage provided to the first gate electrode GE1. The first drain electrode DE1may be disposed to be a predetermined distance apart from, and surrounded by, the first source electrode SE1having a U shape.

As illustrated inFIG.1, the second drain electrode DE2may be spaced apart from the second source electrode SE2with the semiconductor layer SM disposed therebetween and may at least partially overlap with the second gate electrode GE2. Also, as illustrated inFIG.1, the second drain electrode DE2may be spaced apart from the third source electrode SE3with the semiconductor layer SM disposed therebetween and may at least partially overlap with the third gate electrode GE3.

That is, the second drain electrode DE2may be supplied with voltages from both the second and third source electrodes SE2and SE3. Accordingly, the second drain electrode DE2may have a voltage level between the data voltage provided to the second source electrode SE2and the sustain voltage provided to the third source electrode SE3.

The second drain electrode DE2serves as the output terminal of the second TFT TR2, which has the second source electrode SE2as an input terminal and the second gate electrode GE2as a control terminal thereof. Also, the second drain electrode DE2serves as the output terminal of the third TFT TR3, which has the third source electrode SE3as an input terminal and the third gate electrode GE3as a control terminal thereof. In other words, the output terminals of the second and third TFTs TR2and TR3are integrally provided by the second drain electrode DE2. This means that the second drain electrode DE2functions not only as the output terminal of the second TFT TR2, but also as the output terminal of the third TFT TR3. In other words, the second and third TFTs TR2and TR3may share the same output terminal together. That the output terminals of the second and third TFTs TR2and TR3are integrally provided by the second drain electrode DE2may also mean that the second and third source electrodes SE2and SE3are disposed on opposite sides of the second drain electrode DE2.

The second drain electrode DE2may be a predetermined distance apart from each of the second and third source electrodes SE2and SE3and may be disposed in parallel to the second and third source electrodes SE2and SE3. Specifically, each of the second drain electrode DE2and the second and third source electrodes SE2and SE3may have one or more outer sides extending in the second direction dr2, and second and third active regions AR2and AR3may be disposed between the outer sides of the second drain electrode DE2and the second source electrode SE2and between the outer sides of the second drain electrode DE2and the third source electrode SE3, respectively. The third active region AR3includes a first part of the third active region AR31and a second part of the third active region AR32. In other words, as illustrated inFIGS.1and5, the second source electrode SE2, the second active region AR2, the second drain electrode DE2, the third active region AR3, and the third source electrode SE3, which extend along the second direction dr2, may be sequentially disposed in that order. In other words, the second and third active regions AR2and AR3may be disposed on opposite sides of the second drain electrode DE2.

As illustrated inFIGS.1and5, the second drain electrode DE2may be spaced apart from the second source electrode SE2with the semiconductor layer SM disposed therebetween and may at least partially overlap with the second gate electrode GE2. A partial region, of the semiconductor layer SM, disposed between the second drain electrode DE2and the second source electrode SE2may be defined as the second active region AR2. In the second active region AR2, a second channel may be formed such that the second drain electrode DE2and the second source electrode SE2can be electrically connected to each other according to the gate voltage. The second channel may be controlled by the gate voltage provided to the second gate electrode GE2.

Also, as illustrated inFIGS.1and5, the second drain electrode DE2may be spaced apart from the third source electrode SE3with the semiconductor layer SM disposed therebetween and may at least partially overlap with the third source electrode SE3. A partial region, of the semiconductor layer SM, disposed between the second drain electrode DE2and the third source electrode SE3may be defined as the third active region AR3. In the third active region AR3, a third channel may be formed such that the second drain electrode DE2and the third source electrode SE3can be electrically connected to each other according to the gate voltage. The third channel may be controlled by the gate voltage provided to the third gate electrode GE3.

In the exemplary embodiment ofFIGS.1through5, a floating electrode FE, which extends along the second direction dr2inside the third active region AR3, may be additionally disposed in order to improve the characteristics of the third TFT TR3.

The first drain electrode DE1may be electrically connected to the first sub-pixel electrode SPE1via a first contact hole CNT1(described later). The second drain electrode DE2may be electrically connected to the second sub-pixel electrode SPE2via a second contact hole CNT2(described later).

The third source electrode SE3may be electrically connected to the first sustain electrode CST1via the third contact hole CNT3and may also be electrically connected to the second sustain electrode CST2via the fourth contact hole CNT4. Accordingly, the sustain voltage provided to the first sustain electrode CST1may be transmitted to the second sustain electrode CST2via the third source electrode SE3.

The data line DL, the first, second, and third source electrodes SE1, SE2, and SE3, and the first and second drain electrodes DE1and DE2may include the same material. In an exemplary embodiment, for example, the data line DL, the first, second, and third source electrodes SE1, SE2, and SE3, and the first and second drain electrodes DE1and DE2may include an Al-based metal such as Al or an Al alloy, a Ag-based metal such as Ag or an Ag alloy, a Cu-based metal such as Cu or a Cu alloy, a Mo-based metal such as Mo or a Mo alloy, Cr, Ta, or Ti. The data line DL, the first, second, and third source electrodes SE1, SE2, and SE3, and the first and second drain electrodes DE1and DE2may have a single-layer structure or may have a multilayer structure including at least two conductive films having different physical properties.

The first gate electrode GE1, the first active region AR1, the first source electrode SE1, and the first drain electrode DE1may form the first TFT TR1which functions as a switching element. The second gate electrode GE2, the second active region AR2, the second source electrode SE2, and the second drain electrode DE2may form the second TFT TR2which functions as a switching element. The third gate electrode GE3, the third active region AR3, the third source electrode SE3, and the second drain electrode DE2may form the third TFT TR3which also functions as a switching element. That is, the second and third TFTs TR2and TR3may share the second drain electrode DE2as their output terminal.

In a case where the gate voltage provided to the first gate electrode GE1has an on-level capable of turning on the first TFT TR1, the data voltage provided to the data line DL may be provided to the first drain electrode DE1via the first source electrode SE1. Since the first drain electrode DE1is electrically connected to the first sub-pixel electrode SPE1, the data voltage provided to the data line DL may also be provided to the first sub-pixel electrode SPE1.

In a case where the gate voltage provided to the second gate electrode GE2has an on=level capable of turning on the second TFT TR2, the data voltage provided to the data line DL may be provided to the second drain electrode DE2via the second source electrode SE2. In a case where the gate voltage provided to the third gate electrode GE3has an on-level capable of turning on the third TFT TR3, the sustain voltage provided to the first sustain electrode CST1may be provided to the second drain electrode DE2via the third source electrode SE3.

As mentioned above, since the second drain electrode DE2is electrically connected to the second sub-pixel electrode SPE2via the second contact hole CNT2and the sustain voltage is lower than the data voltage, the voltage provided to the second sub-pixel electrode SPE2may have a level between the data voltage and the sustain voltage.

Even though a single voltage is provided to each of the plurality of pixels PX, the voltage finally provided to the first sub-pixel electrode SPE1may differ from the voltage finally provided to the second sub-pixel electrode SPE2, and as a result, the liquid crystal molecules LC may be tilted at various angles. Accordingly, the difference between the gray level of the LCD device as viewed from the front and the gray level of the LCD device as viewed from a side can be minimized. In other words, the visibility of the LCD device can be improved.

The voltage finally provided to the second sub-pixel electrode SPE2, i.e., the voltage provided to the second drain electrode DE2, may be calculated by Equations (1) and (2):
Vdr2=Rv×Vdata  (1); and

Rv=LEW⁢2/LEL⁢2LEW⁢2/LEL⁢2+LEW⁢3/(LEL⁢31+LEL⁢32)(2)
where Vdr2denotes the voltage applied to the second drain electrode DE2, Vdata denotes the data voltage, RV denotes voltage ratio, LEW2denotes the width of the second channel formed in the second active region AR2, LEL2denotes the length of the second channel formed in the second active region AR2, LEW3denotes the width of the third channel formed in the third active region AR3, and LEL31+LEL32denotes the length LEL3of the third channel formed in the third active region AR3.

The length of a channel corresponds to the degree to which two electrodes disposed on both sides of the channel are spaced apart from each other, and the width of a channel corresponds to the degree to which two electrodes disposed on both sides of the channel face each other.

The length of the three channels will hereinafter be described with reference toFIG.5. Referring toFIG.5, the floating electrode FE is disposed near the center of the third active region AR3. Accordingly, no channel is formed in the region where the floating electrode FE is disposed, and the region where the floating electrode FE is disposed may have conductivity. In other words, the region where the floating electrode FE is disposed may be excluded from the third active region AR3. Thus, the third active region AR3is divided into first and second areas on the left and right sides, respectively, of the floating electrode FE, and the length of the third channel LEL3may be defined as the sum of a length LEL31, in the first direction dr1, of the first area and a length LEL32, in the second direction dr1, of the second area.

In the exemplary embodiments ofFIGS.1through5, as illustrated inFIG.5, both the length LEL2of the second channel and the length LEL3of the third channel may be measured along the first direction dr1. In other words, the direction of the length LEL2of the second channel may be the same as the first direction dr1, and the direction of the length LEL3of the third channel may also be the same as the first direction dr1. In addition, the direction of the length LEL2of the second channel may be the same as the direction in which the gate line GL is extends, and the direction of the length LEL3of the third channel may also be the same as the direction in which the gate line GL extends. Accordingly, deviations in the length LEL2of the second channel between the plurality of pixels PX may be effectively minimized.

Both the length LEL2of the second channel and the length LEL3of the third channel are in the denominator of Equation (2). Thus, if the length LEL2of the second channel and the length LEL3of the third channel differ from each other, i.e., if there is a large deviation between the length LEL2of the second channel and the length LEL3of the third channel, the voltage ratio may considerably vary from one pixel PX to another pixel PX. As a result, even if the same data voltage and the same sustain voltage are provided to each of the plurality of pixels PX, the voltage provided to the second sub-pixel electrode SPE2via the second drain electrode DE2may vary from one pixel PX to another pixel PX. However, since both the direction of the length LEL2of the second channel and the direction of the length LEL3of the third channel are the same as the first direction dr1, deviations in voltage ratio between the plurality of pixels PX can be effectively minimized. This will hereinafter be described with reference toFIG.6.

FIG.6is a schematic view illustrating how to expose a mother substrate using an exposure apparatus.

A method of formation of various wirings (e.g., the data line DL, the first, second, and third source electrodes SE1, SE2, and SE3, and the first and second drain electrodes DE1and DE2) may include forming a metal layer, forming a photoresist layer on the metal layer, curing the photoresist layer by applying ultraviolet (“UV”) light using an exposure apparatus, removing part of the photoresist layer, removing (i.e., etching away) part of the metal layer that is exposed, and removing the rest of the photoresist layer.

Referring toFIG.6, the exposure apparatus may apply UV light to a mother substrate10to cure the photoresist layer to have particular patterns. The exposure apparatus uses a plurality of lenses LS1through LSn to form the particular patterns on the photoresist layer, and due to the use of the lenses LS1through LSn, the patterns formed on the photoresist layer may become more sophisticated. The mother substrate10may be a substrate yet to be divided or cut into an individual base substrate110.

The lenses LS1through LSn apply UV light to the photoresist layer while moving from one side to the other side of the mother substrate10. In the exemplary embodiment ofFIG.6, the lenses LS1through LSn apply UV light while moving from the left to the right ofFIG.6along the first direction dr1.

The lenses LS1through LSn, which are disposed adjacent to one another, may be trapezoidal, and each pair of adjacent lenses may be oriented in opposite directions. The amount of UV light applied to the mother substrate10via the lenses LS1through LSn may be substantially uniform in overlapping areas OA where two adjacent lenses overlap with each other and in non-overlapping areas NOA where the UV light is applied to the mother substrate10through only one lens. In other words, all the lenses LS1through LSn have the same height in the non-overlapping areas NOA, and the sum of the heights of the trapezoidal shapes of each pair of adjacent lenses in anywhere of the overlapping areas NOA may be the same as the height of the trapezoidal shapes of the lenses LS1through LSn in the non-overlapping areas NOA. The lenses LS1through LSn are illustrated inFIG.6as having a trapezoidal cross-sectional shape, but the shape of the lenses LS1through LSn is not particularly limited thereto as long as the amount of UV light applied via the lenses LS1through LSn is uniform anywhere. The width to which each of the lenses LS1through LSn applies UV light may be about 100 to about 110 mm, but the invention is not limited thereto. That is, various sizes of lenses may be used.

Since the lenses LS1through LSn form patterns on the photoresist layer by applying UV light while moving along the first direction dr1, the patterns formed in the first direction dr1may be more sophisticated than the patterns formed in the second direction dr2. Accordingly, in a case where the direction of the length LEL2of the second channel and the direction of the length LEL3of the third channel are identical to the first direction dr1, accuracy of the lengths LEL2and LEL3can increase, and deviations in the length LEL2of the second channel and the length LEL3of the third channel between the plurality of pixels PX can be effectively minimized.

The formation of patterns may be more difficult in the overlapping areas OA than in the non-overlapping areas NOA. However, even in the overlapping areas OA, if the direction of the length LEL2of the second channel and the direction of the length LEL3of the third channel are identical to the first direction dr1, deviations in the length LEL2of the second channel and the length LEL3of the third channel between the plurality of pixels PX can be effectively minimized.

Referring again toFIGS.1through5, in order to make both the second and third channels extend in the first direction dr1, the second source electrode SE2, the second drain electrode DE2, and the third source electrode SE3, which are disposed adjacent to the second and third active regions AR2and AR3, may have bar-shaped portions extending along the second direction dr2.

On the other hand, a width LEW1of the first channel formed in the first active region AR1is measured as a length of a U-shape contour of the first channel. The length of the first channel includes both a length LEL1vwhich is a distance to which a side of the first drain electrode DE1and a side of the first source electrode SE1facing each other are spaced apart in a vertical direction, and a length LEL1pwhich is a distance to which a side of the first drain electrode DE1and a side of the first source electrode SE1facing each other are spaced apart in a vertical direction. Since the first TFT TR1, including the first active region AR1, transmits only the data voltage to the first sub-pixel electrode SPE1, the voltage applied to the first sub-pixel electrode SPE1may not be affected considerably by any deviations in the length LEL1v, in the vertical direction, of the first channel. In other words, even though the first channel has both the length LEL1vin the vertical direction and the length LEL1pin the horizontal direction, the display quality of the LCD device may not be degraded according to the deviation.

On the other hand, in a case where the second and third TFTs TR2and TR3include bar-shaped second and third active regions AR2and AR3, the overlapping areas between the second source electrode SE2, the third source electrode SE3, and the second drain electrode DE2and the second and third gate electrodes GE2and GE3may be relatively small, compared to a case where the second and third TFTs TR2and TR3include U-shaped second and third active regions AR2and AR3. Accordingly, the capacitances formed between the second source electrode SE2, the third source electrode SE3, and the second drain electrode DE2and the second and third gate electrodes GE2and GE3may also be small. As a result, the charging rate of the second and third TFTs TR2and TR3can be enhanced, and driving margins can be improved.

In the case where the second and third TFTs TR2and TR3include bar-shaped second and third active regions AR2and AR3, a kickback phenomenon, i.e., the phenomenon in which the data voltage that the second drain electrode DE2is charged with suddenly drops in response to the transition of the gate voltage from an on-level to an off-level, may become severe, as compared to the case where the second and third TFTs TR2and TR3include U-shaped second and third active regions AR2and AR3. However, in the exemplary embodiment ofFIGS.1through5according to the invention, since the second and third TFTs TR2and TR3share the second drain electrode DE2as their output terminals, the overlapping areas between the output terminals of the second and third TFTs TR2and TR3and the second and third gate electrodes GE2and GE3can be effectively minimized, and as a result, the kickback phenomenon can also be effectively minimized.

A second insulating layer130is disposed on the first insulating layer120and the first, second, and third TFTs TR1, TR2, and TR3. The second insulating layer130may include an insulating material. In an exemplary embodiment, for example, the second insulating layer130may be an organic layer comprising an organic material. The second insulating layer130may planarize any height differences provided by elements disposed between the second insulating layer130and the first base substrate110on the top surface thereof. In other words, the top surface of the second insulating layer130may be substantially flat.

The first, second, third, and fourth contact holes CNT1, CNT2, CNT3, and CNT4may be defined in the second insulating layer130to penetrate the second insulating layer130.

Specifically, the first contact hole CNT1, which exposes part of the first drain electrode DE1along a vertical direction with respect to the top surface of the first base substrate110, may be defined in the second insulating layer130. Part of the first drain electrode DE1and the first sub-pixel electrode SPE1which is disposed above the second insulating layer130may be physically connected to each other via the first contact hole CNT1.

Also, the second contact hole CNT2, which exposes part of the second drain electrode DE2along the vertical direction with respect to the top surface of the first base substrate110, may be defined in the second insulating layer130. Part of the second drain electrode DE2and the second sub-pixel electrode SPE2which is disposed above the second insulating layer130may be electrically connected to each other via the second contact hole CNT2.

Also, the third contact hole CNT3, which exposes part of the first sustain electrode CST1and part of the third source electrode SE3along the vertical direction with respect to the top surface of the first base substrate110, may be defined in the second insulating layer130. A first bridge electrode BE1may be disposed on the second insulating layer130to overlap with the third contact hole CNT3and may electrically connect the first sustain electrode CST1and the third source electrode SE3.

Also, the fourth contact hole CNT4, which exposes part of the second sustain electrode CST2and part of the third source electrode SE3along the vertical direction with respect to the top surface of the first base substrate110, may be defined in the second insulating layer130. A second bridge electrode BE2may be disposed on the second insulating layer130to overlap with the fourth contact hole CNT4and may electrically connect the second sustain electrode CST2and the third source electrode SE3.

The first sub-pixel electrode SPE1, the second sub-pixel electrode SPE2, the first bridge electrode BE1, the second bridge electrode BE2, and a shielding electrode SDE are disposed on the second insulating layer130not to overlap with one another over the same plane.

The first sub-pixel electrode SPE1may be electrically connected to the first drain electrode DE1via the first contact hole CNT1and may receive the data voltage from the first drain electrode DE1.

The second sub-pixel electrode SPE2may be electrically connected to the second drain electrode DE2via the second contact hole CNT2and may receive a voltage having a level between the data voltage and the sustain voltage from the second drain electrode DE2.

The first sub-pixel electrode SPE1may be generally disposed within a first light-transmitting area PNA1but may include an extended portion overlapping with the first contact hole CNT1for connection with the first drain electrode DE1. Also, the first sub-pixel electrode SPE1may define openings in which no transparent conductive material is disposed. Due to the presence of the openings, regular patterns are provided on the first sub-pixel electrode SPE1, and the tilt direction and tilt degree of liquid crystal molecules LC disposed to overlap with the first sub-pixel electrode SPE1may be controlled by the shape and the patterns of the first sub-pixel electrode SPE1. In the exemplary embodiments ofFIGS.1through5, the first sub-pixel electrode SPE1may have patterns including a plurality of branches extending outwardly from the center of the first light-transmitting area PNA1, but the invention is not limited thereto.

Similarly, the second sub-pixel electrode SPE2may be generally disposed within a second light-transmitting area PNA2but may include an extended portion overlapping with the second contact hole CNT2for connection with the second drain electrode DE2. Also, the second sub-pixel electrode SPE2may define openings in which no transparent conductive material is disposed. Due to the presence of the openings, regular patterns are provided on the second sub-pixel electrode SPE2, and the tilt direction and tilt degree of liquid crystal molecules LC disposed to overlap with the second sub-pixel electrode SPE2may be controlled by the shape and the patterns of the second sub-pixel electrode SPE2. In the exemplary embodiments ofFIGS.1through5, the second sub-pixel electrode SPE2may have patterns including a plurality of branches extending outwardly from the center of the second light-transmitting area PNA2, but the invention is not limited thereto.

As described above, the first and second bridge electrodes BE1and BE2may be disposed to overlap with the third and fourth contact holes CNT3and CNT4, respectively.

The shielding electrode SDE may be a predetermined distance apart from the first and second sub-pixel electrodes SPE1and SPE2and the first and second bridge electrodes BE1and BE2so as not to overlap with the first and second sub-pixel electrodes SPE1and SPE2and the first and second bridge electrodes BE1and BE2. Accordingly, the voltages provided to the first and second sub-pixel electrodes SPE1and SPE2may not be provided to the shielding electrode SDE.

The shielding electrode SDE may be disposed to overlap with an entire region except for the areas where the first and second sub-pixel electrodes SPE1and SPE2and the first and second bridge electrodes BE1and BE2are disposed. However, the shielding electrode SDE does not necessarily overlap with the entire region except for the areas where the first and second sub-pixel electrodes SPE1and SPE2and the first and second bridge electrodes BE1and BE2are disposed, and may overlap with some of the areas where the first and second sub-pixel electrodes SPE1and SPE2and the first and second bridge electrodes BE1and BE2are disposed.

Specifically, the shielding electrode SDE may be disposed to overlap with the data line DL. The data line DL may be provided with the data voltage and may thus affect the liquid crystal molecules LC, and the shielding electrode SDE may shield the effect of the data voltage to the liquid crystal molecules LC. As a result, light leakage can be prevented.

In an exemplary embodiment, the first and second sub-pixel electrodes SPE1and SPE2, the first and second bridge electrodes BE1and BE2, and the shielding electrode SDE may include a transparent conductive material such as indium tin oxide (“ITO”), indium zinc oxide (“IZO”), indium tin zinc oxide (“ITZO”), or aluminum (Al)-doped zinc oxide (“AZO”).

A first alignment film (not illustrated) may be additionally disposed on the first and second sub-pixel electrodes SPE1and SPE2, the first and second bridge electrodes BE1and BE2, and the shielding electrode SDE. The first alignment film may control the initial alignment angle of the liquid crystal molecules LC injected into the liquid crystal layer300.

The second display substrate200will hereinafter be described.

The second display substrate200includes a second base substrate110, a light-shielding member BM, a color filter layer CF, an overcoat layer220, and a common electrode CE.

The second base substrate210is disposed to face the first base substrate110. The second base substrate210may be durable enough to withstand external shocks. The second base substrate210may be a transparent insulating substrate. In an exemplary embodiment, for example, the second base substrate210may be a glass substrate, a quartz substrate, a transparent resin substrate, or the like. The second base substrate210may have a flat plate shape, but may be curved in a particular direction.

The light-shielding member BM is disposed on a surface of the second base substrate210that faces the first display substrate100.

The light-shielding member BM may be disposed to overlap with the gate line GL, the data line DL, the first, second, and third TFTs TR1, TR2, and TR3, and the first, second, third, and fourth contact holes CNT1, CNT2, CNT3, and CNT4(i.e., to overlap with an entire region except for the first and second light-transmitting areas PNA1and PNA2). Accordingly, the transmission of light in the entire region except for the first and second light-transmitting areas PNA1and PNA2can be blocked by the light-shielding member BM.

A color filter layer CF is disposed on a surface of the light-shielding member BM that faces the first display substrate100.

The color filter layer CF may comprise a photosensitive organic composition containing a pigment for implementing a color, and may include any one of red, green, and blue pigments. In an exemplary embodiment, for example, the color filter layer CF may include a plurality of color filters, and one of the plurality of color filters may display one of three primary colors, i.e., red, green, and blue colors. However, the invention is not limited to this example. Alternatively, the plurality of color filters may display any one of cyan, magenta, yellow, and white colors.

In the exemplary embodiments ofFIGS.1through5, the color filter layer CF may be provided on the second display substrate200, but the invention is not limited thereto. That is, in some exemplary embodiments, the color filter layer CF may be provided on the first display substrate100.

The overcoat layer220is disposed on a surface of the color filter layer CF that faces the first display substrate100. The overcoat layer220can alleviate height differences provided by the light-shielding member BM and the color filter layer CF. In some exemplary embodiments, the overcoat layer220may be omitted.

A common electrode CE is disposed on a surface of the overcoat layer220that faces the first display substrate100.

The common electrode CE may be provided as an unpatterned plate over the entire surface of the second base substrate210. A common voltage supplied from the outside may be applied to the common electrode CE to form an electric field in the liquid crystal layer300together with the first and second sub-pixel electrodes SPE1and SPE2. However, in some exemplary embodiments, openings may be defined on the common electrode CE such that the common electrode CE can have particular patterns.

The common voltage may be provided from the outside, and the level of the common voltage may be uniformly maintained while the liquid crystal display is operating. Accordingly, an electric field may be formed by a voltage difference between the first sub-pixel electrode SPE1and the common electrode CE, which are disposed to overlap with each other, and between the second sub-pixel electrode SPE2and the common electrode CE, which are disposed to overlap with each other. The liquid crystal molecules LC may be rotated or tilted by the electric field.

On the other hand, in some exemplary embodiments, the shielding electrode SDE may be provided with a voltage having substantially the same level as the common voltage. Accordingly, during the operation of the liquid crystal display device, an electric field having a directionality may not be formed in part of the liquid crystal layer300between the shielding electrode SDE and the common electrode CE, which are disposed to overlap with each other. Since a voltage having the same level as the common voltage is provided to the shielding electrode SDE and the common electrode CE, no potential difference is generated therebetween. Accordingly, the liquid crystal molecules LC in the space between the shielding electrode SDE and the common electrode CE, which are disposed to overlap with each other, may not be rotated or tilted, and may be maintained in the same state with the state when the LCD device is turned off. In an exemplary embodiment, for example, the transmission of light can be blocked in the part of the liquid crystal molecules LC between the shielding electrode SDE and the common electrode CE.

A second alignment film (not illustrated) may be disposed on a surface of the common electrode CE that faces the first display substrate100. The second alignment film, like the first alignment film, may control the initial alignment angle of the liquid crystal molecules LC injected into the liquid crystal layer300. The second alignment film may be omitted.

The liquid crystal layer300will hereinafter be described.

The liquid crystal layer300may include the liquid crystal molecules LC having dielectric anisotropy and refractive anisotropy. The liquid crystal molecules LC may be aligned in a vertical direction with respect to the first and second display substrates100and200in the absence of an electric field in the liquid crystal layer300. In response to an electric field provided between the first and second display substrates100and200, the liquid crystal molecules LC may be tilted or rotated in a particular direction and may thus change the polarization of light.

FIG.7is a graph showing an exemplary embodiment of measurements of the lengths, in vertical and horizontal directions, of the first channel of the first TFT according to the LCD device ofFIGS.1through5.

Referring toFIG.7, the X axis represents the location of each lens (in mm), and the Y axis represents the length of the first channel (in μm). Specifically, the X axis represents the distance, in the second direction dr2, of each lens from a starting point SP ofFIG.6.

FIG.7shows that there are large deviations in the length LEL1v, in the vertical direction, of the first channel of the first TFT TR1between the plurality of pixels PX and there are relatively small deviations in the length LELlp, in the horizontal direction, of the first channel of the first TFT TR1between the plurality of pixels PX.

As described above, the first sub-pixel electrode SPE1may not be considerably affected by deviations in channel length because it receives only the data voltage provided to the data line DL.

On the other hand, if the second and third channels of the second and third TFTs TR2and TR3extend in the vertical direction, the difference between the lengths of the second and third channels of the second and third TFTs TR2and TR3may considerably affect the voltage provided to the second sub-pixel electrode SPE2. That is, even if the same data voltage and the same sustain voltage are applied, there are large variations in the voltage generated in the second sub-pixel electrode SPE2between the plurality of pixels PX, and thus, smudges may become visible. However, in the exemplary embodiments ofFIGS.1through5, since both the lengths LEL2and LEL3of the second and third channels of the second and third TFTs TR2and TR3can be measured in the first direction dr1, i.e., the horizontal direction, deviations in voltage between the plurality of pixels PX that may be caused by different channel lengths can be effectively minimized.

FIG.8is a plan view of another exemplary embodiment of a pixel of an LCD device according to the invention.

A pixel PX_a ofFIG.8differs from the pixel PX ofFIG.1in that no floating electrode FE is provided in a third TFT TR3_a. The pixel PX_a will hereinafter be described, focusing mainly on differences with the pixel PX ofFIG.1.

Referring toFIG.8, the pixel PX_a includes a gate line GL, a semiconductor layer SM, a data line DL, a first TFT TR1, a second TFT TR2, the third TFT TR3_a, a first contact hole CNT1, a second contact hole CNT2, a third contact hole CNT3, a fourth contact hole CNT4, a first sub-pixel electrode SPE1, a second sub-pixel electrode SPE2, a first bridge electrode BE1, a second bridge electrode BE2, and a shielding electrode SDE.

The third TFT TR3_aincludes a third source electrode SE3_a, a third gate electrode GE3_a, a third active region AR3_a, and a second drain electrode DE2. That is, the pixel PX_a may not include the equivalent of the floating electrode FE ofFIG.1, which is disposed near the center of the third active region AR3of the pixel PX ofFIG.1.

FIG.9is a plan view of still another exemplary embodiment of a pixel of an LCD device according to the invention.

A pixel PX_b ofFIG.9differs from the pixel PX ofFIG.1in that both a first source electrode SE1_band a first drain electrode DE1_bof a first TFT TR1_bare bar-shaped. The pixel PX_b will hereinafter be described, focusing mainly on differences with the pixel PX ofFIG.1.

Referring toFIG.9, the pixel PX_b includes a gate line GL, a semiconductor layer SM, a data line DL, a first TFT TR1_b, a second TFT TR2, a third TFT TR3, a first contact hole CNT1, a second contact hole CNT2, a third contact hole CNT3, a fourth contact hole CNT4, a first sub-pixel electrode SPE1, a second sub-pixel electrode SPE2, a first bridge electrode BE1, a second bridge electrode BE2, and a shielding electrode SDE.

The first TFT TR1_bincludes the first source electrode SE1_b, the first drain electrode DE1_b, a first active region AR1_b, and a first gate electrode GE1_b. Both the first source electrode SE1_band the first drain electrode DE1_b, which are adjacent to the first active region AR1_b, maybe provided as a bar shape extending along a second direction dr2. Accordingly, the length of a first channel formed in the first TFT TR1_bmay be measured along the first direction dr1. As a result, deviations in the length of the first channel between the pixel PX_b and other pixels PX_b can be effectively minimized.

FIG.10is a plan view of still another exemplary embodiment of a pixel of an LCD device according to the invention.

A pixel PX_c ofFIG.10includes a third TFT TR3_a, which has the same structure as the third TFT TR3_aofFIG.8, and a first TFT TR1_b, which has the same structure as the first TFT TR1_bofFIG.9.

That is, the pixel PX_c has a structure obtained by reflecting both the modifications made by the exemplary embodiments ofFIGS.8and9.

FIG.11is a plan view of still another exemplary embodiment of a pixel of an LCD device according to the invention.

A pixel PX_d ofFIG.11differs from the pixel PX ofFIG.1in that both the length directions of second and third channels are a second direction dr2. The pixel PX_d will hereinafter be described, focusing mainly on differences with the pixel PX ofFIG.1.

Referring toFIG.11, the pixel PX_d includes a gate line GL, a semiconductor layer SM, a data line DL, a first TFT TR1_d, a second TFT TR2_d, a third TFT TR3_d, a first contact hole CNT1, a second contact hole CNT2, a third contact hole CNT3, a fourth contact hole CNT4, a first sub-pixel electrode SPE1, a second sub-pixel electrode SPE2, a first bridge electrode BE1, a second bridge electrode BE2, and a shielding electrode SDE.

The length direction of the second channel of the second TFT TR2_dmay be the second direction dr2. In other words, both the second drain electrode DE2_dand the second source electrode SE2_d, which are adjacent to a second active region AR2_d, may extend in a first direction dr1.

Also, the length direction of the third channel of the third TFT TR3_dmay be the second direction dr2. In other words, both the second drain electrode DE2_dand the third source electrode SE3_d, which are adjacent to a third active region AR3_d, may extend in the first direction dr1. Here, the third active region AR3_dincludes a first part of the third active region AR31_dand a second part of the third active region AR32_d.

If the lenses of an exposure apparatus apply UV light while moving in the second direction dr2in the manufacturing process, deviations in the lengths of the second and third channels between the pixel PX_d and other pixels PX_d can be effectively minimized.

While the invention has been particularly illustrated and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the following claims. The exemplary embodiments should be considered in a descriptive sense only and not for purposes of limitation.