Patent ID: 12230544

DETAILED DESCRIPTION

As discussed above, nanowire devices can be formed using nanosheets. To increase the gate width of nanowire devices, a number of nanowire channels can be arranged vertically and a gate stack can be formed around the nanowire channels. The number of vertically arranged nanowire channels affects the effective gate width of the device such that each additional nanowire channel increases the effective gate width.

The effective gate width of the devices affects the performance characteristics of the nanowire devices. Embodiments of the present invention provide processes, using sacrificial spacers and block masks, for forming nanowire devices on a single wafer that have different numbers of nanowires arranged substantially vertically in the channel region of the devices to provide nanowire devices on a wafer that have different performance characteristics.

FIG.1illustrates a side view of a substrate102and a nanosheet stack101arranged on the substrate102. The nanosheet stack101includes alternating layers of dissimilar materials. In the illustrated embodiment, a nanosheet104is arranged on the substrate102and a nanosheet106is arranged on the nanosheet104. A second nanosheet104is arranged on the nanosheet106and a second nanosheet106is arranged on the second nanosheet104and so on. Any number of layers of nanosheet104and106can be arranged in such an alternating arrangement to form the nanosheet stack101.

Non-limiting examples of suitable materials for the semiconductor substrate102include Si (silicon), strained Si, SiC (silicon carbide), Ge (germanium), SiGe (silicon germanium), SiGeC (silicon-germanium-carbon), Si alloys, Ge alloys, III-V materials (e.g., GaAs (gallium arsenide), InAs (indium arsenide), InP (indium phosphide), or aluminum arsenide (AlAs)), II-VI materials (e.g., CdSe (cadmium selenide), CdS (cadmium sulfide), CdTe (cadmium telluride), ZnO (zinc oxide), ZnSe (zinc selenide), ZnS (zinc sulfide), or ZnTe (zinc telluride)), or any combination thereof. Other non-limiting examples of semiconductor materials include III-V materials, for example, indium phosphide (InP), gallium arsenide (GaAs), aluminum arsenide (AlAs), or any combination thereof. The III-V materials can include at least one “III element,” such as aluminum (Al), boron (B), gallium (Ga), indium (In), and at least one “V element,” such as nitrogen (N), phosphorous (P), arsenic (As), antimony (Sb).

In the illustrated exemplary embodiment the nanosheet104includes a semiconductor material such as, for example, Si, Ge, or another suitable semiconductor material. The nanosheet106includes a material dissimilar from the nanosheet106such as, for example, SiGe.

A hardmask layer108is arranged on the nanosheet stack101. The hardmask108can include, for example, silicon oxide, silicon nitride (SiN), SiOCN, SiBCN or any suitable combination of those. The hardmask108can be deposited using a deposition process, including, but not limited to, PVD, CVD, PECVD, or any combination thereof.

FIG.2Aillustrates a cut-away view along the line A-A (ofFIG.2B) following a lithographic patterning and etching process that removes exposed portions of the hardmask108and the nanosheet stack101(ofFIG.1) and exposing portions of the substrate102to form a nanosheet fin (fin)202. The etching process can include, for example, reactive ion etching.FIG.2Billustrates a top view of the fin202.

FIG.3Aillustrates a cut-away view along the line A-A (ofFIG.3C) andFIG.3Billustrates a cut-away view along the line B-B (ofFIG.3C), andFIG.3Cillustrates a top view following the formation of sacrificial gates302and sacrificial spacers306adjacent to the sacrificial gates302.

The sacrificial gates302in the exemplary embodiment are formed by depositing a layer (not shown) of sacrificial gate material such as, for example, amorphous silicon (aSi), or polycrystalline silicon (polysilicon) material or another suitable sacrificial gate material. The sacrificial gate302can further include a sacrificial gate dielectric material such as silicon oxide between the nanowires and aSi or polysilicon material.

The layer of sacrificial gate material can be deposited by a deposition process, including, but not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD, plasma enhanced chemical vapor deposition (PECVD), inductively coupled plasma chemical vapor deposition (ICP CVD), or any combination thereof.

Following the deposition of the layer of sacrificial gate material, a hard mask layer (not shown) such as, for example, silicon oxide, silicon nitride (SiN), SiOCN, SiBCN or any suitable combination of those materials, is deposited on the layer of sacrificial gate material to form a PC hard mask or sacrificial gate cap304. The hardmask layer can be deposited using a deposition process, including, but not limited to, PVD, CVD, PECVD, or any combination thereof.

Following the deposition of the layer of sacrificial gate material and the hardmask layer, a patterning and etching process such as, for example, lithography followed by reactive ion etching is performed to remove exposed portions of the hardmask layer and the layer of sacrificial gate material form the sacrificial gates302and the sacrificial gate caps304.

InFIG.3B, spacers306are formed adjacent to the sacrificial gates302. The spacers306in the illustrated embodiment are formed by depositing a layer of spacer material (not shown) over the exposed portions of the fins202and the sacrificial gates302.

Non-limiting examples of suitable materials for the layer of spacer material include dielectric nitrides (e.g., silicon nitride), dielectric oxynitrides, SiBCN, SiOCN, SiOC, dielectric oxides (e.g., silicon oxide), or any combination thereof. The layer of spacer material is deposited by a suitable deposition process, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD).

Following the deposition of the layer of spacer material, a suitable anisotropic etching process such as, for example, a reactive ion etching process is performed to remove portions of the layer of spacer material and form the spacers306.

FIG.4Aillustrates a cut-away view along the line B-B (ofFIG.4B) following an etching process that removes exposed portions of the fins202(ofFIG.3B). In this regard, a selective directional or anisotropic etching process such as, for example, reactive ion etching can be performed to remove the exposed portions of the fin202.FIG.4Billustrates a top view following the removal of the exposed portions of the fin202.

FIG.5illustrates a cut-away view following a selective isotropic etching process that removes exposed portions of the nanosheets104, which forms cavities501. The cavities501are partially defined by distal ends of the nanosheets104and the nanosheets106.

FIG.6illustrates a cut-away view following the formation of a sacrificial second spacer602in the cavities501(ofFIG.5). The second spacer602can include any suitable spacer material that can be deposited conformally in the cavities501.

FIG.7illustrates a cut-away view following the removal of portions of the second spacer602and the deposition of a dielectric material702over the sacrificial gates302and the substrate102. The dielectric material702can include, for example, silicon oxide, silicon nitride, silicon oxynitride, SiOCN or SiBCN material.

FIG.8illustrates a cut-away view following a directional etching process that removes portions of the low-k dielectric material702to form spacers802adjacent to the sacrificial gates302. The etching process is controlled such that the dielectric material702is reduced to a first thickness (t1) that exposes the nanosheets106c.

FIG.9illustrates a cut-away view following the patterning of a first mask902over the first sacrificial gate304a. Suitable masks include photoresists, electron-beam resists, ion-beam resists, X-ray resists, optical planarization layers, and etch resists. The resist can a polymeric spin on material or a polymeric material.

FIG.10illustrates a cut-away view following an etching process that removes exposed portions of the low-k dielectric layer702to reduce the thickness of exposed portions of the low-k dielectric layer702to a second thickness (t2) where t1>t2. The reduction of the thickness of the low-k dielectric layer702results in the exposure of the nanosheets106bbelow the sacrificial gates302band302c.

FIG.11illustrates a cut-away view following the patterning of a second mask1002over the first sacrificial gate302aand the second sacrificial gate302b.

FIG.12illustrates a cut-away view following an etching process that removes exposed portions of the low-k dielectric layer702to reduce the thickness of exposed portions of the low-k dielectric layer702to expose the substrate102. The resultant structure exposes the nanosheet106abelow the third sacrificial gate302c.

FIG.13illustrates a cut-away view following the removal of the masks902and/or1002, by for example, ashing (thereby leaving the low-k dielectric layer702which is now designated as1302and1304). The ashing process can be used to remove a photoresist material, amorphous carbon, or organic planarization (OPL) layer. Ashing is performed using a suitable reaction gas, for example, O2, N2, H2/N2, O3, CF4, or any combination thereof.

FIG.14illustrates a cut-away view following the formation of source/drain regions1402a,1402band1402c. The source/drain regions1402a,1402band1402care formed by an epitaxial growth process that deposits a crystalline overlayer of semiconductor material onto the exposed crystalline seed material of the exposed fin202to form the source/drain regions1402a,1402band1402c.

Epitaxial materials can be grown from gaseous or liquid precursors. Epitaxial materials can be grown using vapor-phase epitaxy (VPE), molecular-beam epitaxy (MBE), liquid-phase epitaxy (LPE), or other suitable process. Epitaxial silicon, silicon germanium, and/or carbon doped silicon (Si:C) silicon can be doped during deposition (in-situ doped) by adding dopants, n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium), depending on the type of transistor. The dopant concentration in the source/drain can range from 1×1019cm−3to 2×1021cm−3, or between 2×1020cm−3and 1×1021cm−3.

The terms “epitaxial growth and/or deposition” and “epitaxially formed and/or grown” mean the growth of a semiconductor material (crystalline material) on a deposition surface of another semiconductor material (crystalline material), in which the semiconductor material being grown (crystalline overlayer) has substantially the same crystalline characteristics as the semiconductor material of the deposition surface (seed material). In an epitaxial deposition process, the chemical reactants provided by the source gases are controlled and the system parameters are set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move about on the surface such that the depositing atoms orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, an epitaxially grown semiconductor material has substantially the same crystalline characteristics as the deposition surface on which the epitaxially grown material is formed. For example, an epitaxially grown semiconductor material deposited on a {100} orientated crystalline surface will take on a {100} orientation. In some embodiments, epitaxial growth and/or deposition processes are selective to forming on semiconductor surface, and generally do not deposit material on exposed surfaces, such as silicon dioxide or silicon nitride surfaces.

In some embodiments, the gas source for the deposition of epitaxial semiconductor material include a silicon containing gas source, a germanium containing gas source, or a combination thereof. For example, an epitaxial Si layer can be deposited from a silicon gas source that is selected from the group consisting of silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source that is selected from the group consisting of germane, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane and combinations thereof. While an epitaxial silicon germanium alloy layer can be formed utilizing a combination of such gas sources. Carrier gases like hydrogen, nitrogen, helium and argon can be used.

FIG.15illustrates a cut-away view following the formation of an inter-level dielectric layer1502over the source/drain regions1402a,1402band1402c.

The inter-level dielectric layer1502is formed from, for example, a low-k dielectric material (with k<4.0), including but not limited to, silicon oxide, spin-on-glass, a flowable oxide, a high density plasma oxide, borophosphosilicate glass (BPSG), or any combination thereof. The inter-level dielectric layer1502is deposited by a deposition process, including, but not limited to CVD, PVD, plasma enhanced CVD, atomic layer deposition (ALD), evaporation, chemical solution deposition, or like processes. Following the deposition of the inter-level dielectric layer1502, a planarization process such as, for example, chemical mechanical polishing is performed.

FIG.16illustrates a cut-away view flowing the removal of the sacrificial gates302(ofFIG.15) to form cavities1602that expose the channel regions of the fins202. The sacrificial gates302can be removed by performing a dry etch process, for example, RIE, followed by a wet etch process. The wet etch process is selective to (will not substantially etch) the spacers306and the inter-level dielectric material1502. The chemical etch process can include, but is not limited to, hot ammonia or tetramethylammonium hydroxide (TMAH).

FIG.17illustrates a cut-away view following the removal of the exposed nanosheets104. The nanosheets104can be removed, by a selective etching process. The nanosheets104can be etched selective to SiGe, for example, by an aqueous etchant containing ammonia. The removal of the nanosheets104forms nanowires1702.

FIG.18illustrates a cut-away view following the formation of a replacement metal gate stack (gate stacks)1801a,1801b, and1801c. The gate stacks1801a,1801b, and1801cinclude high-k metal gates formed, for example, by filling the cavity1602(ofFIG.17) with one or more gate dielectric1802materials, one or more workfunction metals1804, and one or more metal gate conductor1806materials. The gate dielectric1802material(s) can be a dielectric material having a dielectric constant greater than 3.9, 7.0, or 10.0. Non-limiting examples of suitable materials for the dielectric1802materials include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, or any combination thereof. Examples of high-k materials (with a dielectric constant greater than 7.0) include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The high-k material can further include dopants such as, for example, lanthanum and aluminum.

The gate dielectric1802materials can be formed by suitable deposition processes, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), evaporation, physical vapor deposition (PVD), chemical solution deposition, or other like processes. The thickness of the dielectric material can vary depending on the deposition process as well as the composition and number of high-k dielectric materials used. The dielectric material layer can have a thickness in a range from about 0.5 to about 2 nm, although greater or lesser thickness can also be employed.

The work function metal(s)1804can be disposed over the gate dielectric1802material. The type of work function metal(s)1804depends on the type of transistor and can differ between the nFET and pFET devices. Non-limiting examples of suitable work function metals1804include p-type work function metal materials and n-type work function metal materials. P-type work function materials include compositions such as ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, or any combination thereof. N-type metal materials include compositions such as hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), aluminides, or any combination thereof. The work function metal(s) can be deposited by a suitable deposition process, for example, CVD, PECVD, PVD, plating, thermal or e-beam evaporation, and sputtering.

The gate conductor1806material(s) is deposited over the gate dielectric1802materials and work function metal(s)1804to form the gate stacks1801a,1801b, and1801c. Non-limiting examples of suitable conductive metals include aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The gate conductor1806material(s) can be deposited by a suitable deposition process, for example, CVD, PECVD, PVD, plating, thermal or e-beam evaporation, and sputtering.

Following the deposition of the gate dielectric1802materials, the work function metal(s)1804, and the gate conductor1806material(s), planarization process, for example, chemical mechanical planarization (CMP), is performed to remove the overburden of the deposited gate materials and form the gate stacks1801a,1801b, and1801c.

The resultant gate stacks1801a,1801b, and1802care formed around nanowires1702. The source/drain regions1402a,1402b, and1402chave different thicknesses thus the gate stack1801ais formed around the nanowires1702, however gate stack1801ais formed around one nanowire1702that is connected to the source/drain regions1402a. The gate stack1801bis formed around the nanowires1702, but the gate stack1801bis formed around two nanowires1702that are connected to the source/drain regions1402b. The gate stack1801cis formed around three nanowires1702that are connected to the source/drain regions1402c. Thus, the performance characteristics of each of the devices is different due to the differences in the effective channel widths of the gate stacks1801a,1801b, and1802c.

After the gate stack1801a,1801b, and1801cis formed, additional insulating material (not shown) can be deposited over the device(s). The insulating material can be patterned to form cavities (not shown) that expose portions of the source/drain regions1402a,1402band1402cand the gate stack1801a,1801b, and1801c. The cavities can be filled by a conductive material (not shown) and, in some embodiments, a liner layer (not shown) to form conductive contacts (not shown).

The conductive material can include any suitable conductive material including, for example, polycrystalline or amorphous silicon, germanium, silicon germanium, a metal (e.g., tungsten, titanium, tantalum, ruthenium, zirconium, cobalt, copper, aluminum, lead, platinum, tin, silver, gold), a conducting metallic compound material (e.g., tantalum nitride, titanium nitride, tantalum carbide, titanium carbide, titanium aluminum carbide, tungsten silicide, tungsten nitride, ruthenium oxide, cobalt silicide, nickel silicide), carbon nanotube, conductive carbon, graphene, or any suitable combination of these materials. The conductive material can further include dopants that are incorporated during or after deposition.

As used herein, the terms “invention” or “present invention” are non-limiting terms and not intended to refer to any single aspect of the particular invention but encompass all possible aspects as described in the specification and the claims. The term “on” can refer to an element that is on, above or in contact with another element or feature described in the specification and/or illustrated in the figures.

As used herein, the term “about” modifying the quantity of an ingredient, component, or reactant of the invention employed refers to variation in the numerical quantity that can occur, for example, through typical measuring and liquid handling procedures used for making concentrates or solutions. Furthermore, variation can occur from inadvertent error in measuring procedures, differences in the manufacture, source, or purity of the ingredients employed to make the compositions or carry out the methods, and the like. In one aspect, the term “about” means within 10% of the reported numerical value. In another aspect, the term “about” means within 5% of the reported numerical value. Yet, in another aspect, the term “about” means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported numerical value.

It will also be understood that when an element, such as a layer, region, or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being “directly on” or “directly over” “on and in direct contact with” another element, there are no intervening elements present, and the element is in contact with another element.

It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments described. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments described herein.