Patent ID: 12223879

DESCRIPTION OF THE EMBODIMENTS

Hereinafter, embodiments consistent with the disclosure will be described with reference to the drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

As discussed above, a conventional LED back plane system for wearable devices is bulky and introduces energy loss into LED systems. As a result, the conventional LED back plane system is not suitable for wearable devices because a wearable device requires the system to be relatively small in size, to produce sufficient brightness and contrast for a user, to be energy efficient, and to provide a sufficient refresh-rate for the screen.

Consistent with embodiments of the present disclosure, a micro LED back plane system includes an LED array suitable for wearable devices and a combination of a data processor and color display panel that is smaller in size. This ensures the micro LED display system can be smaller in size than a conventional LED display, produce steady light with sufficient brightness and contrast, be energy efficient, and provide a sufficient refresh-rate for the screen.

Some embodiments consistent with the present disclosure include a micro display controlling system, including a data interface, a data decoder, a memory-write controller, a frame-memory controller, at least one color-display panels, a data processor, a data output interface, and at least one sensor. A micro display device applying micro display controlling system generates an image with better contrast, within shorter response times, with more energy efficiency, and with a higher refresh-rate. A display module includes a display control, a pixel driver array, and a single-color display panel. Consistent with some embodiments, the display control includes a data receiver, a scan controlling signal processor, a shift register, a register controller, a row driver, and a column driver. The micro display controlling system consistent with disclosed embodiments is capable of overcoming the drawbacks of conventional micro display controlling systems, including micro LED controlling systems.

FIG.1is a schematic block diagram of an exemplary micro display controlling system100for an LED display device consistent with embodiments of the present disclosure. The micro display controlling system100includes a data interface101and a data decoder105. In some embodiments, the data interface101and the data decoder105can both be provided as information exchange or decoding components such as installed software, internal hardware, or a peripheral device. The micro display controlling system100further includes a memory-write controller130coupled to the data decoder105. The micro display controlling system100also includes a register controller115and a frame-memory controller110. The register controller115is coupled between the data decoder105and the memory-write controller130. The frame-memory controller110includes frame memories111,112, and113. In some embodiments, the memory-write controller130, the register controller115, and the frame-memory controller110are provided as a portion of a random-access memory (“RAM”) of the micro display controlling system100.

The micro display controlling system100further includes a data processor140. The data processor140includes data processing and formatting modules141,142, and143. The data processor140is coupled to the frame-memory controller110. The frame memories111,112, and113of the frame-memory controller110are coupled to the data processing and formatting modules141,142, and143of the data processor140, respectively. In some embodiment, the data processor140, as well as the data processing and formatting modules141,142, and143, are installed with programs capable of conducting image processing.

The micro display controlling system100also includes a panel timing and synchronization control module120coupled between the register controller115and the data processor140. In some embodiments, the panel timing and synchronization control module120is provided as a portion of the RAM of the micro display controlling system100. The micro display controlling system100also includes a data output interface150. The data output interface150is coupled to the data processor140. The data output interface150further includes sub-output interfaces151,152, and153. In some embodiments, the data output interface150, as well as the sub-output interfaces151,152, and153, can be provided as an information exchange component such as installed software, internal hardware, or a peripheral device.

The micro display controlling system100also includes a color-display panel160coupled to the data output interface150. The color-display panel160further includes single-color display modules161,162, and163. In some embodiments, the color-display panel160, as well as the display modules161,162, and163can be LED display systems provided as sets of integrated LED circuits, chips, microchips, screens, or other electronic components or devices configurable to display graphical and frame data.

The micro display controlling system100further includes one or more sensors145. In some embodiments, the one or more sensors145include a temperature sensor configured to detect temperature of the micro display controlling system100. Each such temperature sensor detects and monitors temperature of the micro display controlling system100and provide the detected temperature value to a general purpose computer to which the micro display controlling system100is coupled. The general purpose computer can shut down power if the temperature of the micro display controlling system100reaches a threshold value, such as 80 degree Celsius, or any temperature that is preset by the user, the manufacture, or that meets industrial standards of LED system manufacture.

Consistent with the present disclosure, the data interface101is configured to receive and provide data for the micro display controlling system100. Specifically, the data interface101receives raw image data, converts the raw image data it receives into frame data, and provides the frame data to the data decoder105.

In some embodiments, the data interface101receives image data input from an image data providing electronic device inside or outside of the micro display controlling system100. For example, the data interface101may receive raw image data, pre-processed frame data, or both, from a ROM, a hard drive, or from a peripheral device such as a camera, a video recording device, a portable driver, a USB driver, a touch screen, or other device generating raw image data. The raw image data can be raster graphics data, vector image data, video data, or other forms of image data that are currently, or may become, available. In some embodiments, the data interface101connects with an external data-providing device through a physical connection, such as through an electronic cable. In some embodiments, the data interface101connects with the peripheral device wirelessly, such as through a Wi-Fi or a BLUETOOTH™ connection. In some embodiments, the data interface101processes the received raw image data to produce sets of corresponding frame data. In some embodiments, the data interface101stores decoding software and includes a processor that executes the software to process the raw image data. In some embodiments, the data interface101is coupled to the data decoder105. More specifically, when the image data is in video format, the data interface101provides the image data to data decoder105. The data decoder105includes decoding software/hardware or other software/hardware that are currently available or may become available, to process the image data and provides the processed image data as frame data. In some embodiments, the data decoder105, samples the video format image data, e.g., using a periodic sampling method, and creates sets of graphic format data and clock signal data corresponding to the video format image data. In some embodiment, the sampling interval is equal to or less than 1/24 second. In some embodiments, the sampling method can be interpolation, polling, convolution, deconvolution, or other methods of video format image data sampling that are currently, or may become, available. More specifically, when the raw image data is vector graphic data, the data decoder105converts the sets of vector graphic data into sets of raster graphic image data, or an LED-display-friendly dot matrix data structure that is currently, or may become, available.

In some embodiments, the data decoder105outputs the processed frame image data in a form suitable for LED display. For example, in some embodiments, the data decoder105further provides and stores, in decoder105, the processed frame data as at least two single-color data frames, each single-color data frame corresponds to a color channel. In some embodiments, the single-color data frame is provided as three single-color channels, i.e. a red color channel, a green color channel, and a blue color channel, commonly known as the RGB layers or RGB channels. Each pixel of the processed frame data is provided as a pixel data point that includes three 8-bit color scale values (i.e. a red scale value, a green scale value, and a blue scale value) and each value corresponds to the color scale value of the pixel in one of the three (RGB) color channels/layers. In some embodiments, each frame of the processed frame data is stored as one multi-dimensional matrix including the pixel data points of each pixel of the processed frame data. The raw image, such as a video clip, usually is large in size and cannot be displayed efficiently on a micro LED display on a smart wearable device. By providing the raw image data as multi-layer single-color data frame, such as the RGB layers, the processed frame data is smaller in size and more suitable for micro LED display on a smart wearable device to process and to display.

In some embodiments, the at least two single-color data frames are captured or provided by the data interface101. In some embodiments, an image enhancer125, coupled to the data interface101, produces luminance adjustment data by processing the frame data received from data interface101pixel by pixel. In some embodiments, the image enhancer125stores luminance adjustment software and includes a processor that executes the software to process the frame data. The processing by the image enhancer125, in some embodiments, includes brightening or dimming certain pixels by increasing or decreasing luminance of that pixel. The change of pixel luminance is stored as the luminance adjustment data. The image enhancer125transmits the luminance adjustment data to a data processor140.

In some embodiments, the at least two single-color data frame is provided as CMY (i.e. cyan, magenta, and yellow) layers/channels, YUV (luminance, chrominance, and chroma) layers/channels, HSV (hue saturation value) layers/channels, or other color layers/channels that are currently available or may become available, to process the frame data and provide the processed frame image data as multiple layers/channels. In some embodiments, a color channel is also referred to as a raster band. In some embodiments, the data decoder105further transmits the single-color data frames to the memory-write controller130.

More particularly, in some embodiments, the memory-write controller130receives frame data from the data decoder105one frame at a time. In some embodiments, the memory-write controller130receives the at least two single-color data frames in chronological order. In some other embodiments, the memory-write controller130receives the at least two single-color data frames in the order that the frame data is stored in a storage medium connected to the data decoder105. More specifically, the frame data received by the memory-write controller130can be frame data converted from raw image data by the data decoder105, or image data received by the data decoder105in frame data format. In some embodiments, the data interface101directly connects to the memory-write controller130.

Still with reference toFIG.1, in some embodiments, the memory-write controller130includes an image enhancement component. The image enhancement component is programmed to process the frame data received from the data decoder105. In some embodiments, the programming causes the image enhancement component to accentuate, or sharpen, image features of the image represented by the raw image data, such as edges of a specific shape in the image, boundaries between different areas in the image, or color contrast, not only to restore lost graphical information and remove graphical noise created during the process of raw data converting to frame data, but also to format the graphic display to be more suitable for LED display. In some embodiments, the image enhancement component is a chip, a microprocessor, or a graphic processing unit (“GPU”) that is programmed to perform the image enhancement.

In some embodiments, memory-write controller130receives the at least two single-color data frames, such as the three single-color (red, green, and blue) data frames, from data decoder105. In some embodiments, the memory-write controller130outputs the single-color data frames to the frame-memory controller110, one by one.

In the embodiment depicted inFIG.1, the frame-memory controller110receives the three single-color data frames and provides to each one of the frame memories111,112, and113a different one of the single-color data frames.

Consistent with the present disclosure, the data processor140, coupled to the frame-memory controller110, receives the single-color data frames from the frame-memory controller110. More specifically, in the embodiment depicted inFIG.1, three data formatting processors141,142, and143of the data processor140, are coupled to receive from the frame memories111,112, and113of the frame-memory controller110, respectively, the single-color data frames. The data processing and formatting modules141,142, and143are each programmed to process the received single-color data frames and create a display panel controlling signal to transmit to the data output interface150.

In some embodiments not shown in the figures, the frame-memory controller110receives the three single-color data frames and provides the single-color data frames only to the frame memories111and112. The data formatting processors141,142, and143of the data processor140, are coupled to receive from the frame memories111and112of the frame-memory controller110, respectively, the three single-color data frames.

In the embodiment depicted inFIG.1, the data output interface150includes three sub-output interface151,152, and153, each coupled to receive the single-color data frames from one of the three data processing and formatting modules141,142, and143, respectively.

In some embodiments, the data processor140outputs the processed single-color data frames so that the single-color data frames can more accurately reflect the chronological order of each frame. In some embodiments, the data decoder105further provides the clock signal data corresponding to the video format image data to the register controller115. The clock signal data is time series data generated by the data decoder105according to the time features of each frame in the raw image data. When the frame-memory controller110and the data processor140process and store the single-color data frames, some frames or some features may be lost during the process, such as chronological order and time interval features among frames. The register controller115provides the clock signal data to the panel timing and synchronization controller120. The panel timing and synchronization controller120, coupled to the data processor140and to the data output150, includes a processor and is configured to synchronize time features, such as chronological order and time interval features among frames, of the processed single-color data frames stored in data processor140and the data output interface150with the clock signal data. By comparing the stored frame data to the clock signal data of the raw image data, the panel timing and synchronization control module120generates a panel controlling signal to sort the processed and stored image represented by the frame data, so that the frame data can better represent the time features in the raw image data, when displayed on the LED display.

In the embodiment depicted inFIG.1, the color-display panel160, coupled to the data output interface150, includes three display modules161,162, and163. The display modules161,162, and163of the color-display panel160each couple to and receive the single-color data frames from each one of the three sub-output interfaces151,152, and153, respectively. In some embodiment, each one of the display modules161,162, and163comprises a display module as, for example, depicted inFIG.2and described more fully below.

FIG.2is a schematic block diagram of an exemplary display module200, consistent with embodiments of the present disclosure. The display module200includes a display control201. In some embodiments, the display control201is coupled to a pixel driver array220and at least one single-color display panel250, and is provided as an internal memory chip or circuit. The display control201further includes a data receiver210, a column driver215, a scan controlling signal processor225, a register controller230, a row driver235, and a shift register240. The data receiver210is coupled to the output interface150(FIG.1) and receives a color layer of the processed single-color data frames from the output interface150. The scan controlling signal processor225, the shift register240, and the register controller230are coupled to the data receiver210. The row driver235and the column driver215are both coupled to the scan controlling signal processor225and the shift register controller230. The pixel driver array220can be provided as a circuit, a chip, a microchip, or other electronic components or devices configurable to control pixels of an LED display. The single-color display panel250can be provided as sets of integrated LED circuits, chips, microchips, screens, or other optical or electronic components or devices configurable to display graphical and frame data.

Consistent with the present disclosure, the display control201is configured to receive and provide processed frame data for the display module200. In the embodiment depicted inFIG.1, the data receiver210receives processed frame data from one of the sub-output interfaces151,152, and153of the data output150. In some embodiments, the data receiver210further receives the panel controlling signal, generated by the panel timing and synchronization control module120, from the same one of the sub-output interfaces.

In some embodiments, the scan controlling signal processor225receives the processed, single-color data frame from one of the sub-output interfaces151,152, and153of the output interface150. The scan controlling signal processor225further generates the single-color data frames as a column controlling signal and a row controlling signal. The scan controlling signal processor225further provides the column controlling signal to the column driver215and provides the row controlling signal to the row driver235.

In some embodiments, the shift register240receives single-color data frames from the data receiver210. The shift register240provides the received single-color data frame to the row driver235and the column driver215. The register controller230, coupled to the data receiver210, receives both the one-color frame data and the panel controlling data generated by the panel timing and synchronization control module120. In some embodiments, the register controller230is programmed to compare and update the time feature of the single-color data frames, such as the chronological order and the time interval among frames, with the clock signal data collected by the first register controller115. In some embodiment, the register controller230is programmed to compare and update the time feature of the single-color data frames with the panel controlling signal received from the display control201. In some embodiments, the register controller230produces the time-feature updated frame data by processing the frame data pixel by pixel. The processing by the register controller230, in some embodiments, includes adding or subtracting certain values to the specific frame according to the clock signal data or the panel controlling signal.

In some embodiments, the column driver215, as well as the row driver235, are coupled to both the scan controlling signal processor225and the shift register240. The column driver215receives the column controlling signal from the scan controlling signal processor225. The row driver235receives the row controlling signal from the scan controlling signal processor225.

Consistent with the present disclosure, the column driver215, being coupled to the pixel driver array220, controls image display by controlling pixel scanning by column. The row driver235, being coupled to the pixel driver array220, controls the image display by controlling pixel scanning by row. The pixel driver array220receives frame data from the column driver215and the row driver235, together or separately. In some embodiments, the pixel driver array220is an integrated LED circuit.

In some embodiment, the pixel driver array220is further configured to control the single-color display panel250. The single-color display panel250is further configured so that multiple single-color display panel250can be formed as an LED display device, for example, the color display panel160inFIG.1. In some embodiments, the color-display panel160includes an image merger300configured to merge the at least two single-color data frames and create multi-color frame data suitable for display on the color-display panel160.

FIG.3is a schematic block diagram of an exemplary image merger300, consistent with embodiments of the present disclosure. In some embodiments, the image merger is provided as an optical image merger such as a square-shaped light combining prism305. Each display modules161,162, and163, through the respective single-color display panels250, configured to emit single-color LED lights, provides the respective single-color data frames toward the square-shaped light combining prism305as three single-color frame images. The light combining prism305directs and projects the three single-color images toward the same direction, i.e., toward a screen of the color-display panel160, combining the three single-color images as a multi-color image suitable for display. In some further embodiments, the color-display panel160includes an optical magnifier310configured to magnify the multi-color images so that the multi-color image is more suitable for display.

In some embodiments not shown in the figures, the image merger is provided as a digital frame data merger configured to receive the at least two single-color data frames from the data output interface150and combine the single-color data frames as multi-color frame data.

In some embodiments, multiple display module200depicted inFIG.2can be configured to form the color-display panel160depicted inFIG.1.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.