Patent ID: 12205899

DETAILED DESCRIPTION

The following disclosure provides different embodiments, or examples, for implementing features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not limiting. Other components, materials, values, steps, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

In some embodiments, a semiconductor device includes a semiconductor substrate including active regions, each active region having a long axis extending in a first direction. A first buried metal layer is below the semiconductor substrate. The first buried metal layer includes a first buried conductive rail having a long axis extending in the first direction. In some embodiments, the first buried conductive rail is configured to transmit a first reference voltage (e.g., a gated version of VDD referred to herein as VVDD). Furthermore, in some embodiments the semiconductor device includes a first set of buried conductive fingers, each of which extends from the first buried conductive rail and each of which has a long axis extending in a second direction that is substantially orthogonal to the first direction. Each buried conductive finger in the first set extends beneath more than one of the active regions. In this manner, VVDD is provided to appropriate locations/portions of corresponding ones of active regions. The first buried metal layer also includes a second set of buried conductive fingers. Each buried conductive finger in the second set has a long axis extending in the second direction and extending beneath more than one of the active regions. The second set of buried conductive fingers is interleaved with the first set of buried conductive fingers. In some embodiments, the second set of buried conductive fingers is used to distribute a second reference voltage (e.g., an ungated version of VVDD referred to herein as TVDD) to appropriate locations/portions of corresponding ones of active regions. According to another approach, a first buried metal layer is provided that includes only buried conductive rails, each of which has a long axis that extends in the first direction, and where the other approach does not include fingers extending in the second direction from the conductive rails. By using buried conductive fingers extending in the second direction in accordance with some embodiments, more locations/portions of corresponding ones of active regions are available for connection/coupling correspondingly to VVDD or TVDD as compared to the other approach. As such, using buried conductive fingers extending in the second direction in accordance with some embodiments makes it easier to distribute VVDD and/or TVDD throughout the semiconductor device, and in particular throughout a header circuit, because the increased number of locations/portions of corresponding ones of active regions are available for connection/coupling correspondingly to VVDD or TVDD reduces corresponding resistive loads.

FIG.1is a block diagram of a semiconductor device100in accordance with an embodiment of the present disclosure.

InFIG.1, semiconductor device100includes, among other things, a circuit macro (hereinafter, macro)101. In some embodiments, macro101is a header circuit. In some embodiments, macro101is a macro other than a header circuit. Macro101includes, among other things, a region102with a back-side metal architecture including a conductive rail from which conductive fingers extend substantially perpendicularly. As explained below, the conductive fingers increase the area available for making connections to conductive segments which provide different voltages in a power-gating scheme. The region102includes metal layers and interconnection layers (the latter including via structures) beneath the semiconductor substrate (where “beneath” is relative to the Z-direction-not shown inFIG.1), also referred to as “buried” metal layers and “buried” vias. In some embodiments, the region102has conductive fingers buried beneath the semiconductor substrate that are utilized to receive different reference voltages (e.g., VVDD, TVDD).

FIG.2Ais an integrated circuit (IC)200, in accordance with some embodiments.

IC200is an example of a circuit usable in region102described above. As such, IC200is one example of a circuit that benefits from using a back-side metal architecture (seeFIGS.2A-2E,3,4A-4B, or the like) including a conductive rail from which conductive fingers extend substantially perpendicularly.

IC200includes: a header circuit202; an ungated power circuit203; a gated power circuit205A; a gated power circuit205B; and a control circuit204. In general, power consumption by a circuit increases due to leakage currents. Power gating is a technique to reduce power consumption in circuits within an IC by turning off power supplied to circuits within the IC which are not being used. The power provided to each of gated power circuits205A &205B is gated by corresponding portions of header circuit202, hence each of circuits205A &205B is referred to herein as a gated power circuit. The power provided to ungated power circuit203is not gated by a corresponding header circuit, hence circuit203is referred to herein as an ungated power circuit.

Each of gated power circuits205A &205B is a type of circuit which is configured to operate in a normal mode, and in a sleep mode, standby more, or the like. In the normal mode, power is provided to each of gated power circuits205A &205B. In the normal mode, each of gated power circuits205A &205B is being used by IC200and is either active or inactive, with more power being consumed when active than when inactive. Though less power is consumed when each of gated power circuits205A &205B is in use albeit inactive, nevertheless significant power is consumed due to leakage currents. In the sleep mode, standby more, or the like, each of gated power circuits205A &205B is not being used and so power is temporarily cut off from each of gated power circuits205A &205B. Accordingly, in the sleep mode, standby mode, or the like, each of gated power circuits205A &205B not only is inactive, but each of circuits205A &205B also does not suffer leakage currents. A more detailed description of a header circuit and its relation to a gated power circuit and an ungated power circuit may be found in U.S. Patent Publication No. 2020/0019671 A1, entitled “Integrated Circuit and Method of Forming the Same,” which is incorporated herein by reference in its entirety.

Header circuit202includes a PMOS transistor P1and a PMOS transistor P2. A source of PMOS transistor P1and a source of PMOS transistor P2are both configured to receive an ungated version of a reference voltage, e.g., VDD. InFIG.2A, the ungated version of VDD is referred to as true VDD (TVDD). Furthermore, a body contact of PMOS transistor P1and a body contact of PMOS transistor P2are configured to receive ungated reference voltage TVDD. When transistors P1and P2correspondingly are turned on, a drain of PMOS transistor P1and a drain of PMOS transistor P2provide a gated version of TVDD correspondingly to gated power circuits205A &205B. The gated version of TVDD is referred to as virtual VDD (VVDD) inFIG.2A. Assuming that a source-drain voltage drop (Vsd) for each of transistors P1and P2is sufficiently small as to be regarded as negligible, VVDD=TVDD−Vsd≈TVDD, and thus VVDD is substantially similar to TVDD. When transistors P1and P2correspondingly are turned OFF, power is cut off correspondingly to gated power circuits205A and205B.

A gate of PMOS transistor P1and a gate of PMOS transistor P2are both connected to a node O1and are configured to receive a control signal NSLEEPin′. Header circuit202is, and more particularly each of transistors P1and P2are, configured to be turned on and off based on control signal NSLEEPin′. It should be noted that header circuit202may have a different configuration than the embodiment shown inFIG.2A. For example, in some alternative embodiments, header circuit202has a single PMOS transistor, e.g., P1, which provides VVDD to each of gated power circuits205A &205B. In such an alternative embodiment in which the current-sourcing capacity of the transistor P1is sufficient to source each of gated power circuits205A &205B, the use of single transistor P1reduces the area consumed by header circuit202.

Control circuit204includes a first inverter206and a second inverter208. First inverter206is configured to receive control signal NSLEEPin and to invert the same so as to generate control signal NSLEEPin′. Thus, if control signal NSLEEPin is received in a high voltage state (e.g., at or near TVDD), then first inverter206is configured to generate control signal NSLEEPin′ at a low voltage state (e.g., at or near VSS). If control signal NSLEEPin is received in a low voltage state (e.g., at or near VSS), then first inverter206is configured to generate control signal NSLEEPin′ at a low voltage state (e.g., at or near TVDD).

In this embodiment, first inverter206includes a PMOS transistor P3and an NMOS transistor N1. PMOS transistor P3has a source connected to receive ungated reference voltage TVDD and a drain connected to node O2. A body contact of PMOS transistor P3is connected to receive ungated reference voltage TVDD. Node O2is connected to node O1of header circuit202. NMOS transistor N1has a drain connected to node O2and a source connected to receive a reference voltage VSS (e.g., a ground voltage). A body contact of NMOS transistor N1is connected to receive a reference voltage VBB. A gate contact of PMOS transistor P3and a gate contact of NMOS transistor N1are both connected to node O3. Control signal NSLEEPin is received at node O3.

Accordingly, if control signal NSLEEPin is received in a low voltage state (e.g., at or near VSS), PMOS transistor P3turns on and NMOS transistor N1shuts off. PMOS transistor P3thus pulls the voltage at node O2up at or near TVDD so that control signal NSLEEPin′ is provided at or near TVDD. As such, the voltage at node O1is in the high voltage state at or near TVDD. Accordingly, PMOS transistor P1and PMOS transistor P2are shut off and thus power is cut off correspondingly to gated power circuits205A and205B.

On the other hand, if control signal NSLEEPin is in a high voltage state (at or near TVDD), PMOS transistor P3shuts off and NMOS transistor N1turns on. NMOS transistor N1thus pulls the voltage at node O2down at or near VSS so that control signal NSLEEPin′ is at or near VSS. As such, node O1is in the low voltage state at or near VSS. Accordingly, PMOS transistor P1and PMOS transistor P2are turned on to provide gated reference voltage VVDD to gated power circuits205A &205B.

Second inverter208is configured to generate control signal NSLEEPout from control signal NSLEEPin′. More specifically, second inverter208is configured to invert control signal NSLEEPin′ and generate control signal NSLEEPout. Thus, if control signal NSLEEPin′ is received in a high voltage state (e.g., at or near TVDD), second inverter208is configured to generate control signal NSLEEPout at a low voltage state (e.g., at or near VSS). If control signal NSLEEPin′ is received in a low voltage state (e.g., at or near VSS), second inverter208is configured to generate control signal NSLEEPout at a high voltage state (e.g., at or near TVDD).

In this embodiment, second inverter208includes a PMOS transistor P4and an NMOS transistor N2. PMOS transistor P4has a source connected to receive ungated reference voltage TVDD and a drain connected to node O4. A body contact of PMOS transistor P4is connected to receive ungated reference voltage TVDD. NMOS transistor N2has a drain connected to node O4and a source connected to receive a reference voltage VSS (e.g., a ground voltage). A body contact of NMOS transistor N2is connected to receive reference voltage VBB. A gate contact of PMOS transistor P4and a gate contact of NMOS transistor N2are both connected to node O1. Control signal NSLEEPin′ is provided at node O1.

Accordingly, if control signal NSLEEPin′ is in a low voltage state (e.g., at or near VSS), then PMOS transistor P4turns on and NMOS transistor N2shuts off. PMOS transistor P4thus pulls the voltage at node O4up at or near TVDD so that control signal NSLEEPout is at or near TVDD. As such, the voltage at node O4is in the high voltage state at or near TVDD. In this manner, control signal NSLEEPout indicates that header circuit202is turned on and is providing gated control voltage VVDD to gated power circuits205A &205B.

On the other hand, if control signal NSLEEPin′ is in a high voltage state (at or near TVDD), then PMOS transistor P4shuts off and NMOS transistor N2turns on. NMOS transistor N2thus pulls the voltage at node O4down at or near VSS so that control signal NSLEEPout is in the low voltage state at or near VSS. In this manner, control signal NSLEEPout indicates that header circuit202is turned off so that power is cut off to each of gated power circuits205A and205B.

FIG.2Bis a layout diagram, in accordance with some embodiments.

The layout diagram ofFIG.2Bis representative of a semiconductor device. Structures in the semiconductor device are represented by patterns (also known as shapes) in the layout diagram. For simplicity of discussion, elements in the layout diagram ofFIG.2B(and of other figures included herein) will be referred to as if they are structures rather than patterns per se. For example, pattern210represents an active region (also known as an oxide-dimensioned (OD) region). In the following discussion, element210is referred to as active region210rather than a pattern210.

FIG.2Billustrates one example of a buried contact-to-transistor-component layer (layer BVD) that is provided beneath a semiconductor substrate (not shown inFIG.2B). In some embodiments, buried layer BVD includes a plurality of buried conductive contacts212(not all labeled for the sake of clarity) wherein plurality of buried contacts are provided in rows and columns that are spaced apart in a checkered pattern. As explained in further detail below, buried layer BVD is provided below semiconductor substrate213. In some embodiments, buried layer BVD is provided below semiconductor substrate213.

Semiconductor substrate213includes active regions210, each active region210has a first long axis that extends in a first direction, which in this case is parallel to X-axis. In this embodiment, members of active regions210are substantially parallel to one another in first direction and members of active regions210are separated and substantially aligned relative to a second direction, which is substantially orthogonal to first direction and parallel to Y-axis. The term “substantially” is intended to allow for a parameter, in this case “orthogonal,” to be true within relevant semiconductor manufacturing error tolerances.

Long axes of buried conductive contacts212extend in direction of Y-axis. InFIG.2B, buried conductive contacts212are arranged relative to track lines (not shown). The track lines extend in the direction of the Y-axis. Relative to the X-axis, buried conductive contacts212are aligned with corresponding ones of the tracks.

In this example, rows extend in the direction of the X-axis such that there are five rows of buried conductive contacts212, one for each of active regions210. Other embodiments may have a different number of rows of buried contacts, depending on the number of active regions210. Rows may start with an empty slot followed by a buried conductive contact212and continue the pattern until the end of the row or may start with a buried conductive contact212followed by an empty slot until the end of the row. From top to bottom relative to the Y-axis, for odd numbered tracks, the first row, the third row, and the fifth row have empty slots, and the second and fourth rows have a buried conductive contact212. From top to bottom relative to the Y-axis, for even numbered tracks, the first row, the third row, and the fifth row have a buried conductive contact212, and the second and fourth rows have an empty slot. From top to bottom relative to the Y-axis, for even numbered tracks, the first active region210is connected to buried conductive contacts212in the first row of buried conductive contacts212, third active region210is connected to buried conductive contacts212in the third row of buried conductive contacts212, and fifth active region210is connected to buried conductive contacts212in the fifth row of buried conductive contacts212. From top to bottom relative to the Y-axis, for odd numbered tracks, second active region210is connected to buried conductive contacts212in the second row of buried conductive contacts212, and the fourth active region210is connected to buried conductive contacts212in the fourth row of buried conductive contacts212. In this embodiment, there are forty-three tracks. In some embodiments, number of tracks is different than43.

Buried conductive contacts212have a checkered arrangement which resembles a checkerboard pattern. In this embodiment, there are forty-three tracks.

FIGS.2C-2Dare corresponding layout diagrams220C and220D, in accordance with some embodiments.

Together, layout diagrams220C and220D represent a header circuit, which is one example of header circuit202shown inFIG.2Aand an example of region102inFIG.1. Active regions210inFIG.2Care connected to checkered buried conductive contacts212below active regions210as described above with respect toFIG.2B. In this example embodiment, there are five active regions210. Other embodiments may include any suitable number of active regions. A first metal layer, in this case a buried BM0layer, is provided below semiconductor substrate213and below buried layer BVD. Thus, layer BVD is provided between semiconductor substrate213and first buried metal layer BM0.

Layout diagrams220C and220D assume a corresponding semiconductor process technology node which includes various design rules for generating a layout diagram, and further assume that the design rules follow a numbering convention in which a first level of metallization (M_1st) and a corresponding first level of interconnect structures (V_1st) are referred to correspondingly as M0and V0. In some embodiments, the numbering convention assumes that the M_1st level and the V_1st level are referred to correspondingly as M1and V1.

First metal layer BM0includes first buried conductive rail222and a second buried conductive rail224. First buried conductive rail222has a long axis that extends in the first direction parallel to the X-axis and second buried conductive rail224has a long axis that extends in the first direction parallel to the X-axis. First metal layer BM0also includes a first set of buried conductive fingers226(not all labeled for the sake of clarity) and a second set of buried conductive fingers228(not all labeled for the sake of clarity). In this embodiment, there are 21 instances of buried conductive fingers226and 22 instances of buried conductive fingers228. Other embodiments may have any suitable number of buried conductive fingers226and buried conductive fingers228. Each buried conductive finger226and each buried conductive finger228has a long axis extending in the direction of the Y-axis and a short axis extending in the direction of the X-axis. In some embodiments, the buried conductive fingers226are configured to receive the gated reference voltage VVDD and the buried conductive fingers228are configured to receive the ungated reference voltage TVDD.

Each of buried conductive fingers226extends from first buried conductive rail222and from second buried conductive rail224so as to extend between first buried conductive rail222and second buried conductive rail224. In this embodiment, each of buried conductive contacts212(see alsoFIG.2B) in a given column amongst the even-numbered columns of buried conductive contacts212is connected to a corresponding one of buried conductive fingers226which is aligned with the given column. Furthermore, each of buried conductive fingers226in the first set of buried conductive fingers226extends beneath all of active regions210. As explained below, buried conductive fingers226in the first set of buried conductive fingers226may be connected to provide gated reference voltage VVDD.

Though each of buried conductive fingers228in the second set of buried conductive fingers228has a long axis that extends in the direction of the Y-axis, nevertheless each of buried conductive fingers228is not connected to first buried conductive rail222nor to second buried conductive rail224. In this embodiment, each of buried conductive contacts212(see alsoFIG.2B) in a given column amongst the odd-numbered columns of buried conductive contacts212is connected to a corresponding one of buried conductive fingers228which is aligned with the given column. Furthermore, each of buried conductive fingers228in the second set of buried conductive fingers228extends beneath all of active regions210. As explained below, buried conductive fingers228in the second set of buried conductive fingers228may be connected to provide gated reference voltage TVDD.

Furthermore, the second set of buried conductive fingers228is interleaved with the first set of buried conductive fingers226. Relative to the X-axis, the left most conductive finger is one of buried conductive fingers228and the right most conductive fingers is one of buried conductive fingers228. The left most conductive finger228has an adjacent one of buried conductive fingers226immediately to its right. Right most conductive finger228has an immediately adjacent one of buried conductive fingers226to its left. Other than left most buried conductive finger228and right most buried conductive fingers228at the ends, each one of buried conductive fingers228is between a pair of buried conductive fingers226. Each one of buried conductive fingers226is between a pair of buried conductive fingers228. This particular arrangement is the result of there being one more instance of buried conductive finger228than there are instances of buried conductive finger226. In other embodiments, there may be more instances of buried conductive finger226than there are instances of buried conductive finger228. As a result, there would be buried conductive fingers226at the left most and right most ends instead of buried conductive fingers228. If there were an equal number of buried conductive fingers226and buried conductive fingers228, one of buried conductive fingers226would be at one end (either left most or right most end) and one of buried conductive fingers228would be at the other end (either right most or left most end).

Again,FIG.2Dis a layout diagram220D, in accordance with some embodiments.

FIG.2Dillustrates additional features of header circuit220described above with respect toFIG.2C. In particular,FIG.2Dillustrates additional features of buried via layer BVIA0and another buried metal layer BM1. Buried via layer BVIA0is below first metal layer BM0and between first buried metal layer BM0and second buried metal layer BM1. Second buried metal layer BM1is beneath buried via layer BVIA0and thus beneath first buried metal layer BM0.

Second buried metal layer BM1includes a third set of buried conductive fingers230(not all labeled for the sake of clarity). Each buried conductive finger230in the third set of buried conductive fingers230is provided beneath a different one of the second set of buried conductive fingers228in first buried metal layer BM0. Layout diagram220D further includes a set of buried vias232that are in a first buried interconnection layer BVIA0and that connect buried conductive fingers230in the third set of buried conductive fingers230to buried conductive fingers228in second set of buried conductive fingers228. Buried vias232that connect buried conductive fingers230in third set of buried conductive fingers230to buried conductive fingers228in second set of buried conductive fingers228are rectangular and have a width (parallel to the X-axis) that is substantially equal to a width (parallel to the X-axis) of buried conductive fingers228. Buried conductive fingers230in third set of buried conductive fingers230have a width (relative to the X-axis) that is larger than the width of buried conductive fingers228in second set of buried conductive fingers228. Furthermore, each of buried conductive fingers230is centered beneath a corresponding one of buried conductive fingers228. This increases, if not maximizes, the contact area that connects buried conductive fingers230in third set of buried conductive fingers230to buried conductive fingers228in second set of buried conductive fingers228.

Furthermore, every other one of buried vias232is aligned with a corresponding buried conductive contact212in the second row of corresponding column of buried conductive contacts212that buried conductive finger228is connected to. More specifically, each of the odd numbered conductive fingers is connected to a buried via232that is aligned with a buried conductive contact212that is in the second row of buried conductive contacts212(SeeFIG.2Bto see the second row of buried conductive contacts212). Every other one of buried vias232is aligned with a corresponding buried conductive contact212in the fourth row of the corresponding column of buried conductive contacts212that buried conductive finger228is connected to. More specifically, of the buried conductive fingers228, each of the even numbered conductive fingers is connected to a buried via232that is aligned with a buried conductive contact212that is in the fourth row of buried conductive contacts212(SeeFIG.2Bto see the fourth row of buried conductive contacts212). Each of buried conductive fingers230is configured to receive TVDD. The arrangement ofFIGS.2C-2Ddescribed above increases the amount of surface area that provides connections to buried conductive contacts212and buried vias232through buried conductive fingers228. This reduces the resistance of the header circuit represented by layout diagrams220C and220D, and thus reduces the power consumption of the header circuit represented by layout diagrams220C and220D.

The buried metal layer BM1also includes a first set of conductors234(not all labeled for the sake of clarity). First set of conductors234each have a long axis that extends in the second direction parallel to the Y-axis. Each of conductors234is provided beneath first buried conductive rail222. Buried via layer BVIA0also includes a set of vias236(not all labeled for the sake of clarity) that connects conductors234to first buried conductive rail222. Conductors234are configured to receive gated reference voltage VVDD and thus first buried conductive rail222is provided at VVDD.

Buried metal layer BM1also includes a second set of conductors238(not all labeled for the sake of clarity). Second set of conductors238each have a long axis that extends in the second direction parallel to the Y-axis. Each of conductors238is provided beneath second buried conductive rail224. Buried via layer BVIA0also includes a set of vias240(not all labeled for the sake of clarity) that connects conductors238to second buried conductive rail224. Conductors238are configured to receive gated reference voltage VVDD and thus second buried conductive rail224is provided at VVDD. Note that first set of buried conductive fingers226, second set of buried conductive fingers228, and third set of buried conductive fingers230are all provided relative to second direction parallel to the Y-axis between first buried conductive rail222and second buried conductive rail224. In some embodiments, the arrangement ofFIGS.2C-2Dincreases the effective area for connecting to TVDD by 250% and the effective area for connecting to VVDD by 160% thereby significantly decreasing the resistive load in the header circuit represented by layout diagrams220C and220D.

FIG.2Eis a cross-section, in accordance with some embodiments.

More particularly,FIG.2Eillustrates a cross sectional area of a header circuit corresponding to cross-section indicator IIE-IIE′ shown in each of layout diagrams220C and220D of correspondingFIGS.2C and2D.

The cross-section ofFIG.2Eincludes the semiconductor substrate213, contact-to-transistor-component layer (layer BVD), buried metal layer BM0, buried via layer BVIA0, and buried metal layer BM1. Also shown are a metal-to-drain/source layer (MD layer), a via-to-gate/MD layer (VGD layer), a metal layer M0, via layer VIA0, and a metal layer M1. In some embodiments, the VGD layer is referred to as a via-to-MD layer (VD layer). From top to bottom relative to a Z-axis, metal layer M1, via layer VIA0, metal layer MO, VGD layer, MD layer, semiconductor substrate213, layer BVD, buried metal layer BM0, buried via layer BVIA0, and buried metal layer BM1form a stack of layers. The Z-axis is substantially orthogonal to both the X-axis (seeFIGS.2C and2D) and the Y-axis. As shown inFIG.2E, metal layer M1, via layer VIA0, metal layer M0, VGD layer and MD layer are stacked over semiconductor substrate213. Active (OD) regions210are provided by semiconductor substrate213. Metal layer M1, via layer VIA0, metal layer M0, VGD layer, and MD layer are used to form the contacts of transistors in the IC and for typical routing in an IC. Layer BVD, buried metal layer BM0, buried via layer BVIA0, and buried metal layer BM1are stacked beneath semiconductor substrate213in that order from top to bottom. Since layer BVD, buried metal layer BM0, buried via layer BVIA0, and buried metal layer BM1are stacked beneath semiconductor substrate213, they are referred to as “buried” layers. Utilizing the arrangement described above and below, the layer BVD, buried metal layer BM0, buried via layer BVIA0, and buried metal layer BM1are utilized to distribute VVDD and TVDD in a header circuit, such as header circuit220.

FIG.3is a layout diagram300, in accordance with some embodiments.

FIG.3represents another example of a header circuit, which is one example of header circuit202shown inFIG.2Aand an example of region102inFIG.1. Layout diagram300is similar to layout diagram220C and220D shown in correspondingFIGS.2C and2D. Accordingly, the discussion will concentrate on the differences between layout diagram300and layout diagrams220C-220D for the sake of brevity.

InFIG.3, layout diagram300includes a set of three active regions210instead of five active regions210as in layout diagrams220C-220D. Furthermore, in this embodiment, top most active region210and bottom most active region210are substantially equal in width (relative to the Y-axis) while intermediate active region210is wider than top most active region210and bottom most active region210. In this embodiment, intermediate active region210is approximately twice as wide as top most active region210and bottom most active region210. Other implementations may have other suitable ratios between active regions210. Furthermore, in other embodiments, all of active regions210may be provided in different sizes.

Layout diagram300has first buried metal layer BM0arranged in the same manner described above with respect toFIG.2CandFIG.2D. Thus, first set of buried conductive fingers226(not all labeled for the sake of clarity), second set of buried conductive fingers228(not all labeled for the sake of clarity), first buried conductive rail222, and second buried conductive rail224are provided in the same manner described above with respect toFIG.2CandFIG.2D. However, inFIG.3, layer BVD has a different arrangement than the arrangement shown inFIG.2B. Rather than being checkered, three rows of buried conductive contacts302(not all labeled for the sake of clarity) are provided in layer BVD. From top to bottom relative to the Y-axis, first row of buried conductive contacts302are connected to first active region210, second row of buried conductive contacts302is connected to second active region210, and third row of buried conductive contacts302is connected to third active region210. While there is spacing between buried conductive contacts302in each row, there are no empty slots within the rows. Thus, first layer BVD does not have a checkered pattern.

Relative to the Y-axis, a size of each of buried conductive contacts302is substantially equal to the size of active region210to which it is connected. Thus, relative to the Y-axis, buried conductive contacts302in the second row of buried conductive contacts302have a size that is substantially twice as long as a size of buried conductive contacts302in the first row of buried conductive contacts302. Additionally, relative to the Y-axis, buried conductive contacts302in the second row of buried conductive contacts302have a size that is substantially twice as long as the size of buried conductive contacts302in the third row of buried conductive contacts302. Relative to the Y-axis, the size of buried conductive contacts302in the first row of buried conductive contacts302and the size of buried conductive contacts302in the third row of buried conductive contacts302is substantially equal.

With respect to the columns of buried conductive contact302, each of the columns has a buried conductive contact302, an empty slot, a buried conductive contact302, an empty slot, and then a buried conductive contact302. Relative to the Y-axis, second buried conductive contact302in each of the columns has a size twice as long as the size of first buried conductive contact302and third buried conductive contact302in each of the columns. There are a total of43columns of buried conductive contacts302in this embodiment. From left to right relative to the X-axis, every even numbered column of buried conductive contacts302is connected to a different one of buried conductive fingers226in the first set of buried conductive fingers226while every odd numbered column of the buried conductive contacts302is connected to a different one of buried conductive fingers228. The even numbered columns of buried conductive contacts302and buried conductive fingers226are provided at VVDD while the odd numbered columns of buried conductive contacts302and buried conductive fingers228are provided at TVDD.

InFIG.3, relative to the X-axis, a width of buried conductive contacts302is substantially equal to a width of buried conductive finger226or buried conductive finger228to which it is attached. Also, in this embodiment, buried conductive fingers226and buried conductive fingers228all have widths that are substantially equal. Thus, buried conductive contacts302have substantially equal widths. In other embodiments, buried conductive fingers226and buried conductive fingers228have different widths. In still other embodiments, different subsets of buried conductive fingers226may have different widths and different subsets of buried conductive fingers228have different widths. Accordingly, different subsets of buried conductive contacts302may have different widths depending on the configuration of active regions210and buried conductive fingers226,228to which it is connected.

FIGS.4A-4Bare corresponding layout diagrams400C and400D, in accordance with some embodiments.

Together, layout diagrams400C and400D represent a header circuit, which is one example of header circuit202shown inFIG.2Aand an example of region102inFIG.1. Semiconductor substrate213includes a set of active regions210, each active region210in active regions210has a first long axis that extends in a first direction, which in this case is parallel to the X-axis. In this embodiment, members of active regions210are substantially parallel to one another in the first direction and the members of active regions210are separated and substantially aligned relative to a second direction, which is substantially orthogonal to the first direction and parallel to the Y-axis. Active regions210are arranged in semiconductor substrate213in the same manner described above with respect toFIG.2C.

FIG.4Aillustrates features of header circuit.

Active regions210inFIG.4Aare connected to checkered buried conductive contacts212below active regions210as described above with respect toFIG.2B. The first buried metal layer, in this case a buried BM0layer, is provided below semiconductor substrate213and below layer BVD. Thus, layer BVD is provided between semiconductor substrate213and first buried metal layer BM0. First metal layer BM0includes first buried conductive rail402and a second buried conductive rail404. First buried conductive rail402has a long axis that extends in the first direction parallel to the X-axis and second buried conductive rail404has a long axis that extends in the first direction parallel to the X-axis. First metal layer BM0also includes a first set of buried conductive fingers406(not all labeled for the sake of clarity) and a second set of buried conductive fingers408(not all labeled for the sake of clarity). In this embodiment, there are 21 of the buried conductive fingers406and22of the buried conductive fingers408. Other embodiments may have any suitable number of buried conductive fingers406and buried conductive fingers408. Additionally, the first buried metal layer includes a conductive trace409having a long axis that extends in the first direction.

Each of buried conductive fingers406in the first set of buried conductive fingers406has a long axis that extends in the second direction that is parallel to the Y-axis (substantially orthogonal to the first direction and the Y-axis). Each of buried conductive fingers406also extend from first buried conductive rail402but is unconnected to second buried conductive rail404. Furthermore, each of buried conductive fingers408in the second set of buried conductive fingers408has a long axis that extends in the second direction that is parallel to the Y-axis (substantially orthogonal to the first direction and the Y-axis). Each of buried conductive fingers408also extend from buried conductive trace409but is unconnected to first buried conductive rail402second buried conductive rail404.

In this embodiment, each of buried conductive fingers406is connected to each of buried conductive contacts212(shown inFIG.2B) in the even columns of buried conductive contacts212in layer BVD. Furthermore, each of buried conductive fingers406in the first set of buried conductive fingers406extends beneath the bottom four active regions210relative to the X-axis. As explained below, buried conductive fingers406in the first set of buried conductive fingers406may be connected to provide gated reference voltage VVDD.

Each of buried conductive fingers408in the second set of buried conductive fingers408has a long axis that extends in a second direction that is parallel to the Y-axis (substantially orthogonal to the first direction and the Y-axis). However, each of buried conductive fingers408also are not connected to first buried conductive rail402and second buried conductive rail404. Instead, buried conductive fingers408extend in the second direction from conductive trace409. In this embodiment, each of buried conductive fingers408is connected to each of buried conductive contacts212(shown inFIG.2B) in the odd columns of buried conductive contacts212in the layer BVD. Furthermore, each of buried conductive fingers408in the second set of buried conductive fingers408extends beneath the bottom four of the active regions210. As explained below, buried conductive fingers408in the second set of buried conductive fingers408may be connected to provide gated reference voltage TVDD.

Furthermore, the second set of buried conductive fingers408is interleaved with the first set of buried conductive fingers406. Relative to the X-axis, the left most conductive finger is one of buried conductive fingers408and the right most conductive fingers is one of buried conductive fingers408. The left most conductive finger408has an adjacent one of buried conductive fingers406immediately to its right. The right most conductive finger408has an adjacent one of buried conductive fingers406immediately to its left. Other than the left most buried conductive finger408and the right most buried conductive fingers408at the ends, every other buried conductive finger408is between a pair of buried conductive fingers406. Each of buried conductive fingers406is between a pair of buried conductive fingers408. This particular arrangement is the result of there being one more buried conductive finger408than buried conductive fingers406. In other embodiments, there may be one more buried conductive finger406than buried conductive finger408. As a result, there would be buried conductive fingers406at the left most and right most ends instead of buried conductive fingers408. If there were an equal number of buried conductive fingers406and buried conductive fingers408, one of buried conductive fingers406would be at one end (either left most or right most end) and one of buried conductive fingers408would be at the other end (either right most or left most end). Since buried conductive fingers408extend from conductive trace409and buried conductive fingers406extend from first buried conductive rail402, the interleaving of buried conductive fingers406and buried conductive fingers408provide a combed structure.

Buried conductive fingers406, buried conductive fingers408, and conductive trace409are provided between first buried conductive rail402and second buried conductive rail404relative to the second direction, which is parallel to the Y-axis. Conductive trace409is connected to the first row of buried conductive contacts212in layer BVD. Conductive trace409is provided at gated reference voltage TVDD.

FIG.4Billustrates additional features of header circuit described above with respect toFIG.4A.

In particular,FIG.4Billustrates additional features of buried via layer BVIA0and another buried metal layer BM1. Buried via layer BVIA0is below first metal layer BM0and between first buried metal layer BM0and second buried metal layer BM1. Second buried metal layer BM1is beneath buried via layer BVIA0and thus beneath first buried metal layer BM0.

Second buried metal layer BM1includes a third set of buried conductive fingers430(not all labeled for the sake of clarity). From left to right relative to the X-axis, each buried conductive finger430in the third set of buried conductive fingers430is provided beneath every odd numbered one of the second set of buried conductive fingers408in first buried metal layer BM0. Second buried via layer BVIA0includes a set of buried vias432that connect buried conductive fingers430in the third set of buried conductive fingers430to buried conductive fingers408in the second set of buried conductive fingers408. Buried vias432that connect buried conductive fingers430in the third set of buried conductive fingers430to buried conductive fingers408in the second set of buried conductive fingers408are rectangular and have a width (parallel to the X-axis) that is substantially equal to a width (parallel to the X-axis) of buried conductive fingers408. Buried conductive fingers430in the third set of buried conductive fingers430have a width (relative to the X-axis) that is larger than the width of buried conductive fingers408in the second set of buried conductive fingers408. Furthermore, each of buried conductive fingers430is centered beneath a corresponding one of buried conductive fingers408. This maximizes the contact area that connects buried conductive fingers430in the third set of buried conductive fingers430to buried conductive fingers408in the second set of buried conductive fingers408. There are two of buried vias432that are provided on every odd numbered buried conductive finger430. One of two buried vias432is aligned below second active region210and the other one of two buried vias432is aligned below fourth active region210.

Second buried metal layer BM1includes a fourth set of buried conductive fingers434(not all labeled for the sake of clarity). From left to right relative to the X-axis, each buried conductive finger434in the fourth set of buried conductive fingers434is provided beneath every even numbered one of the first set of buried conductive fingers406in first buried metal layer BM0. Each buried conductive finger434in the fourth set of buried conductive fingers434also extends from first buried conductive rail402to second buried conductive rail404. Second buried via layer BVIA0includes a set of vias436that connect buried conductive fingers434in the fourth set of buried conductive fingers434to first buried conductive rail402. Second buried via layer BVIA0includes another set of vias438that connect buried conductive fingers434in the fourth set of buried conductive fingers434to second buried conductive rail404. First buried conductive rail402and second buried conductive rail404are connected to provide gated reference voltage VVDD. In some embodiments, the arrangement increases the effective area for connecting to TVDD by 160% and the effective area for connecting to VVDD by 148% thereby significantly decreasing the resistive load in the header circuit400.

FIG.5is a flowchart of a method500of generating a layout diagram, in accordance with some embodiments.

Method500is implementable, for example, using EDA system700(FIG.7, discussed below) and an integrated circuit (IC) manufacturing system800(FIG.8, discussed below), in accordance with some embodiments. Regarding method500, examples of the layout diagram include the layout diagrams disclosed herein, or the like. Examples of a semiconductor device which can be manufactured according to method500include semiconductor device100FIG.1.

InFIG.5, method500includes blocks502-504. At block502, a layout diagram is generated which, among other things, includes patterns representing one or more BCL CFETs as disclosed herein, or the like. An example of a semiconductor device corresponding to a layout diagram generated by block502includes semiconductor device100ofFIG.1. Block502is discussed in more detail below with respect toFIG.6. From block502, flow proceeds to block504.

At block504, based on the layout diagram, at least one of (A) one or more photolithographic exposures are made or (B) one or more semiconductor masks are fabricated or (C) one or more components in a layer of a semiconductor device are fabricated. See discussion below ofFIG.7.

FIG.6is a flowchart of a method of generating a layout diagram, in accordance with some embodiments.

More particularly, the flowchart ofFIG.6shows one example of procedures that may be implemented in block502ofFIG.5, in accordance with one or more embodiments.

InFIG.6, block502includes blocks602-608. At block602, active region shapes are generated, wherein each active region shape of the active region shapes has a first long axis that extends in a first direction on a semiconductor substrate shape. An example of the first direction is the X-axis. Examples of the active region shapes would be active region shapes that correspond to the active regions210inFIGS.2C,2D,4A,4Bin a layout diagram. From block602, flow proceeds to block604.

At block604, a first buried conductive rail shape is generated that has a second long axis that extends in the first direction. Examples of the first conductive rail shapes are shapes that correspond with the first buried conductive rail222inFIGS.2C,2D,3and first buried conductive rail402inFIGS.4A,4Bin a layout diagram. From block604, flow proceeds to block606.

At block606, a first set of buried conductive finger shapes is generated that extends from the first conductive rail shape. Each buried conductive finger shape in the first set of buried conductive finger shapes has a third long axis that extends in a second direction, the second direction being substantially orthogonal to the first direction. Also, the first set of buried conductive finger shapes extends beneath more than one of the sets of active region shapes. An example of the second direction is the Y-axis. Furthermore, examples of the first set of buried conductive fingers shapes are shapes that correspond to the first set of buried conductive fingers226inFIGS.2C,2D,3and the first set of buried conductive fingers406inFIG.4A,4Bin a layout diagram.

At block608, a second set of buried conductive finger shapes is generated. Each buried conductive finger shape in the second set of buried conductive finger shapes has a fourth long axis that extends in the second direction. Also, the second set of buried conductive finger shapes extends beneath more than one of the sets of active region shapes and the second set of buried conductive finger shapes are interleaved with the first set of buried conductive finger shapes. Examples of the second set of buried conductive fingers shapes are shapes that correspond to the second set of buried conductive fingers228inFIGS.2C,2D,3and the second set of buried conductive fingers406inFIG.4A,4Bin a layout diagram.

FIG.7is a block diagram of an electronic design automation (EDA) system700in accordance with some embodiments. The EDA system700is configured to generate a layout diagram as described above with respect toFIG.6.

In some embodiments, EDA system700includes an APR system. Methods described herein of designing layout diagrams represent wire routing arrangements, in accordance with one or more embodiments, are implementable, for example, using EDA system700, in accordance with some embodiments.

In some embodiments, EDA system700is a general purpose computing device including at least one processor702, e.g., a hardware processor, and a non-transitory, computer-readable storage medium704. Computer-readable storage medium704, amongst other things, is encoded with, i.e., stores, computer program code706, i.e., a set of computer-executable instructions. Execution of computer program code706, i.e., instructions, by processor702, e.g., a hardware processor, represents (at least in part) an EDA tool which implements a portion or all of the methods described herein in accordance with one or more embodiments (hereinafter, the noted processes and/or methods). Computer-readable storage medium704, amongst other things, includes layout diagram(s)709.

Processor702is electrically connected to computer-readable storage medium704via a bus708. Processor702is also electrically connected to an I/O interface710by bus708. A network interface712is also electrically connected to processor702via bus708. Network interface712is connected to a network714, so that processor702and computer-readable storage medium704are capable of connecting to external elements via network714. Processor702is configured to execute computer program code706encoded in computer-readable storage medium704in order to cause EDA system700to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, processor702is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and/or a suitable processing unit.

In one or more embodiments, computer-readable storage medium704is an electronic, magnetic, optical, electromagnetic, infrared, and/or a semiconductor system (or apparatus or device). For example, computer-readable storage medium704includes a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or an optical disk. In one or more embodiments using optical disks, computer-readable storage medium704includes a compact disk-read only memory (CD-ROM), a compact disk-read/write (CD-R/W), and/or a digital video disc (DVD).

In one or more embodiments, computer-readable storage medium704stores computer program code706configured to cause EDA system700(where such execution represents (at least in part) the EDA tool) to be usable for performing a portion or all of the noted processes and/or methods. In one or more embodiments, computer-readable storage medium704also stores information which facilitates performing a portion or all of the noted processes and/or methods. In one or more embodiments, computer-readable storage medium704stores library707of standard cells including such standard cells disclosed herein.

EDA system700includes I/O interface710. I/O interface710is connected to external circuitry. In one or more embodiments, I/O interface710includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and/or cursor direction keys for communicating information and commands to processor702.

EDA system700also includes network interface712connected to processor702. Network interface712allows EDA system700to communicate with network714, to which one or more other computer systems are connected. Network interface712includes wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion or all of noted processes and/or methods, is implemented in two or more EDA systems700.

EDA system700is configured to receive information through I/O interface710. The information received through I/O interface710includes one or more of instructions, data, design rules, libraries of standard cells, and/or other parameters for processing by processor702. The information is transferred to processor702via bus708. EDA system700is configured to receive information related to a UI through I/O interface710. The information is stored in computer-readable storage medium704as user interface (UI)742.

In some embodiments, a portion or all of the noted processes and/or methods is implemented as a standalone software application for execution by a processor. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is a part of an additional software application. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a plug-in to a software application. In some embodiments, at least one of the noted processes and/or methods is implemented as a software application that is a portion of an EDA tool. In some embodiments, a portion or all of the noted processes and/or methods is implemented as a software application that is used by EDA system700. In some embodiments, a layout diagram which includes standard cells is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generating tool.

In some embodiments, the processes are realized as functions of a program stored in a non-transitory computer readable recording medium. Examples of a non-transitory computer readable recording medium include, but are not limited to, external/removable and/or internal/built-in storage or memory unit, e.g., one or more of an optical disk, such as a DVD, a magnetic disk, such as a hard disk, a semiconductor memory, such as a ROM, a RAM, a memory card, and the like.

FIG.8is a block diagram of the IC manufacturing system800, and an IC manufacturing flow associated therewith, in accordance with some embodiments. The IC manufacturing system800is configured to manufacture the semiconductor device100(SeeFIG.1) described above.

In some embodiments, based on a layout diagram, e.g., at least one of (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit is fabricated using the IC manufacturing system800.

InFIG.8, the IC manufacturing system800includes entities, such as a design house820, a mask house830, and an IC manufacturer/fabricator (“fab”)850, that interact with one another in the design, development, and manufacturing cycles and/or services related to manufacturing an IC device860. The entities in the IC manufacturing system800are connected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a variety of different networks, such as an intranet and the Internet. The communications network includes wired and/or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to and/or receives services from one or more of the other entities. In some embodiments, two or more of design house820, mask house830, and IC fab850is owned by a single larger company. In some embodiments, two or more of design house820, mask house830, and IC fab850coexist in a common facility and use common resources.

Design house (or design team)820generates an IC design layout diagram822. IC design layout diagram822includes various geometrical patterns designed for an IC device860. The geometrical patterns correspond to patterns of metal, oxide, or semiconductor layers that make up the various components of IC device860to be fabricated. The various layers combine to form various IC features. For example, a portion of IC design layout diagram822includes various IC features, such as an active region, gate electrode, source and drain, metal lines or vias of an interlayer interconnection, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design house820implements a proper design procedure to form IC design layout diagram822. The design procedure includes one or more of logic design, physical design or place and route. IC design layout diagram822is presented in one or more data files having information of the geometrical patterns. For example, IC design layout diagram822can be expressed in a GDSII file format or DFII file format.

Mask house830includes mask data preparation832and mask fabrication844. Mask house830uses IC design layout diagram822to manufacture one or more masks845to be used for fabricating the various layers of IC device860according to IC design layout diagram822. Mask house830performs mask data preparation832, where IC design layout diagram822is transformed into a representative data file (“RDF”). Mask data preparation832provides the RDF to mask fabrication844. Mask fabrication844includes a mask writer. A mask writer converts the RDF to an image on a substrate, such as a mask (reticle)845or a semiconductor wafer853. The IC design layout diagram822is manipulated by mask data preparation832to comply with particular characteristics of the mask writer and/or requirements of IC fab850. InFIG.8, mask data preparation832and mask fabrication844are illustrated as separate elements. In some embodiments, mask data preparation832and mask fabrication844can be collectively referred to as mask data preparation.

In some embodiments, mask data preparation832includes optical proximity correction (OPC) which uses lithography enhancement techniques to compensate for image errors, such as those that can arise from diffraction, interference, other process effects and the like. OPC adjusts IC design layout diagram822. In some embodiments, mask data preparation832includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

In some embodiments, mask data preparation832includes a mask rule checker (MRC) that checks the IC design layout diagram822that has undergone processes in OPC with a set of mask creation rules which contain certain geometric and/or connectivity restrictions to ensure sufficient margins, to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram822to compensate for limitations during mask fabrication844, which may undo part of the modifications performed by OPC in order to meet mask creation rules.

In some embodiments, mask data preparation832includes lithography process checking (LPC) that simulates processing that will be implemented by IC fab850to fabricate IC device860. LPC simulates this processing based on IC design layout diagram822to create a simulated manufactured device, such as IC device860. The processing parameters in LPC simulation can include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used for manufacturing the IC, and/or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and the like or combinations thereof. In some embodiments, after a simulated manufactured device has been created by LPC, if the simulated device is not close enough in shape to satisfy design rules, OPC and/or MRC may be repeated to further refine IC design layout diagram822.

It should be understood that the above description of mask data preparation832has been simplified for the purposes of clarity. In some embodiments, mask data preparation832includes additional features such as a logic operation (LOP) to modify the IC design layout diagram822according to manufacturing rules. Additionally, the processes applied to IC design layout diagram822during mask data preparation832may be executed in a variety of different orders.

After mask data preparation832and during mask fabrication844, a mask845or a group of masks845are fabricated based on the modified IC design layout diagram822. In some embodiments, mask fabrication844includes performing one or more lithographic exposures based on IC design layout diagram822. In some embodiments, an electron-beam (e-beam) or a mechanism of multiple e-beams is used to form a pattern on a mask (photomask or reticle)845based on the modified IC design layout diagram822. Mask845can be formed in various technologies. In some embodiments, mask845is formed using binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions. A radiation beam, such as an ultraviolet (UV) beam, used to expose the image sensitive material layer (e.g., photoresist) which has been coated on a wafer, is blocked by the opaque region and transmits through the transparent regions. In one example, a binary mask version of mask845includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask. In another example, mask845is formed using a phase shift technology. In a phase shift mask (PSM) version of mask845, various features in the pattern formed on the phase shift mask are configured to have proper phase difference to enhance the resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask(s) generated by mask fabrication844is used in a variety of processes. For example, such a mask(s) is used in an ion implantation process to form various doped regions in semiconductor wafer853, in an etching process to form various etching regions in semiconductor wafer853, and/or in other suitable processes.

IC fab850is an IC fabrication business that includes one or more manufacturing facilities for the fabrication of a variety of different IC products. In some embodiments, IC fab850is a semiconductor foundry. For example, there may be a manufacturing facility for the front end fabrication of a plurality of IC products (front-end-of-line (FEOL) fabrication), while a second manufacturing facility may provide the back end fabrication for the interconnection and packaging of the IC products (back-end-of-line (BEOL) fabrication), and a third manufacturing facility may provide other services for the foundry business.

IC fab850includes fabrication tools852configured to execute various manufacturing operations on semiconductor wafer853such that IC device860is fabricated in accordance with the mask(s), e.g., mask845. In various embodiments, fabrication tools852include one or more of a wafer stepper, an ion implanter, a photoresist coater, a process chamber, e.g., a CVD chamber or LPCVD furnace, a CMP system, a plasma etch system, a wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discus sed herein.

IC fab850uses mask(s)845fabricated by mask house830to fabricate IC device860. Thus, IC fab850at least indirectly uses IC design layout diagram822to fabricate IC device860. In some embodiments, semiconductor wafer853is fabricated by IC fab850using mask(s)845to form IC device860. In some embodiments, the IC fabrication includes performing one or more lithographic exposures based at least indirectly on IC design layout diagram822. Semiconductor wafer853includes a silicon substrate or other proper substrate having material layers formed thereon. Semiconductor wafer853further includes one or more of various doped regions, dielectric features, multilevel interconnects, and the like (formed at subsequent manufacturing steps).

Details regarding an integrated circuit (IC) manufacturing system (e.g., the IC manufacturing system800ofFIG.8), and an IC manufacturing flow associated therewith are found, e.g., in U.S. Pat. No. 9,256,709, granted Feb. 9, 2016, U.S. Pre-Grant Publication No. 2015/0278429 A1, published Oct. 1, 2015, U.S. Pre-Grant Publication No. 2014/0040838 A1, published Feb. 6, 2014, and U.S. Pat. No. 7,260,442, granted Aug. 21, 2007, the entireties of each of which are hereby incorporated by reference.

In some embodiments, a method of manufacturing a semiconductor device includes: forming active regions on a semiconductor substrate, wherein each active region of the active regions has a long axis that extends in a first direction; forming a first buried conductive rail having a long axis that extends in the first direction; forming a first set of buried conductive fingers that extends from the first buried conductive rail; each buried conductive finger in the first set of buried conductive fingers having a long axis that extends in a second direction, the second direction being substantially orthogonal to the first direction; and the first set of buried conductive fingers extending beneath more than one of the active regions; and forming a second set of buried conductive fingers; each buried conductive finger in the second set of buried conductive fingers having a long axis that extends in the second direction; the second set of buried conductive fingers extending beneath more than one of the active regions; and the second set of buried conductive fingers being interleaved with the first set of buried conductive fingers. In some embodiments, the method further includes: forming a plurality of buried contacts in rows such that the plurality of buried contacts are spaced apart in a checkered pattern; and wherein each of the active regions is connected to the buried contacts of a different row of the rows of the plurality of buried contacts. In some embodiments, the method further includes: forming a plurality of buried contacts in columns such that the plurality of buried contacts are spaced apart in a checkered pattern; and wherein each buried conductive finger in the first set of buried conductive fingers and each buried conductive finger in the second set of buried conductive fingers is connected the buried contacts of a different column of the columns of the plurality of buried contacts such that adjacent columns of the columns of the plurality of buried contacts have the buried contacts of one of the adjacent columns connected to one of the buried conductive fingers in the first set of buried conductive fingers and the buried contacts of another one of the adjacent columns connected to one of the buried conductive fingers in the second set of buried conductive fingers. In some embodiments, the first buried conductive rail and the first set of buried conductive fingers are formed in a same layer. In some embodiments, the method further includes forming a second buried conductive rail having a long axis that extends in the first direction; the first set of buried conductive fingers being between the first buried conductive rail and the second buried conductive rail. In some embodiments, the first buried conductive rail, the first set of buried conductive fingers and the second buried conductive rail are formed in a same layer. In some embodiments, the first set of buried conductive fingers is formed to create an electrical connection between the first buried conductive rail and the second buried conductive rail. In some embodiments, the first set of buried conductive fingers is formed to extend in the second direction under all active regions between the first buried conductive rail and the second buried conductive rail. In some embodiments, the first buried conductive rail, the first set of buried conductive fingers and the second set of buried conductive fingers are formed in a same layer; and the second set of buried conductive fingers is entirely spaced apart from the first buried conductive rail. In some embodiments, the method further includes forming a second buried conductive rail having a long axis that extends in the first direction; the second set of buried conductive fingers is entirely spaced apart from the second buried conductive rail. In some embodiments, the second set of buried conductive fingers is formed to extend in the second direction under all active regions between the first buried conductive rail and the second buried conductive rail. In some embodiments, the first set of buried conductive fingers is entirely spaced apart from the second set of buried conductive fingers. In some embodiments, the first set of buried conductive fingers is configured to provide a gated reference voltage; and the second set of buried conductive fingers is configured to provide an ungated reference voltage. In some embodiments, the first set of buried conductive fingers includes a first buried conductive finger and a second buried conductive finger; the second set of buried conductive fingers includes a third buried conductive finger and a fourth buried conductive finger; and the second set of buried conductive fingers is interleaved with the first set of buried conductive fingers such that, in the first direction, the third buried conductive finger is between the first and second buried conductive fingers, and the second buried conductive finger is between the third and fourth buried conductive fingers. In some embodiments, the first buried conductive rail, the first set of buried conductive fingers and the second set of buried conductive fingers are formed in a buried metal layer that is beneath the semiconductor substrate; and the method further comprises forming a metal-to-drain/source layer on an opposite side of the semiconductor substrate such that the semiconductor substrate is between the buried metal layer and the metal-to-drain/source layer.

In some embodiments, a method of manufacturing a semiconductor device includes: forming active regions on a semiconductor substrate, wherein each active region of the active regions has a long axis that extends in a first direction; forming a first buried conductive rail and a second buried conductive rail, each having a long axis that extends in the first direction; forming a first set of buried conductive fingers that extends between the first and second buried conductive rails; each buried conductive finger in the first set of buried conductive fingers having a long axis that extends in a second direction, the second direction being substantially orthogonal to the first direction; forming a second set of buried conductive fingers; each buried conductive finger in the second set of buried conductive fingers having a long axis that extends in the second direction; each buried conductive finger in the second set of buried conductive fingers having a length in the second direction that is less than a distance between the first and second buried conductive rails; and the second set of buried conductive fingers being interleaved with the first set of buried conductive fingers. In some embodiments, the first buried conductive rail, the first set of buried conductive fingers and the second set of buried conductive fingers are formed in a buried metal layer that is beneath the semiconductor substrate; and the method further comprises forming a metal-to-drain/source layer on an opposite side of the semiconductor substrate such that the semiconductor substrate is between the buried metal layer and the metal-to-drain/source layer. In some embodiments, the method further includes: forming a plurality of buried contacts in rows such that the plurality of buried contacts are spaced apart in a checkered pattern; each of the active regions being connected to the buried contacts of a different row of the rows of the plurality of buried contacts; and the plurality of buried contacts being formed in a contact-to-transistor-component layer that is between the semiconductor substrate and the buried metal layer.

In some embodiments, a method of manufacturing a semiconductor device includes: forming active regions on a semiconductor substrate, wherein each active region of the active regions has a long axis that extends in a first direction; forming a metal-to-drain/source layer on the semiconductor substrate; and forming a buried metal layer under the semiconductor substrate such that the semiconductor substrate is between the buried metal layer and the metal-to-drain/source layer; forming the buried metal layer includes forming a first buried conductive rail, a second buried conductive rail, a first set of buried conductive fingers and a second set of buried conductive fingers; the first and second buried conductive rails each being formed to have a long axis that extends in the first direction; each buried conductive finger in the first and second sets of buried conductive fingers being formed to have a long axis that extends in a second direction, the second direction being substantially orthogonal to the first direction; and the second set of buried conductive fingers being formed to be interleaved with the first set of buried conductive fingers. In some embodiments, the method further includes: forming a contact-to-transistor-component layer between the semiconductor substrate and the buried metal layer; forming the contact-to-transistor-component layer including forming a plurality of buried contacts in rows such that the plurality of buried contacts are spaced apart in a checkered pattern; and each of the active regions between the first buried conductive rail and the second buried conductive rail being connected to the buried contacts of a different row of the rows of the plurality of buried contacts.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.