Patent ID: 12260910

DETAILED DESCRIPTION

The present Applicant has realized that a more compact and efficient memory occupation, while maintaining the advantages of a differential memory architecture, can be achieved by storing information in the non-volatile memory cells in a coded manner.

In particular, a group of a determined number (greater than two) of non-volatile memory cells may store a codeword formed by the values of stored states of the cells of the group, taken according to a given order; the memory cells being of the type in which a stored logic state, which can be logic high (‘1’) or logic low (‘0’), can be changed through application of a current and the state in the memory cell is read by reading a current flowing through the same memory cell.

For instance, in case the group of non-volatile memory cells includes a number Ncof memory cells equal to four, a first exemplary stored codeword may correspond to a combination of states [0 0 1 0], i.e., where a first, a second and a fourth cells have a ‘0’ logic value (also referred to as ‘RESET’ state, in case of a PCM memory cell) and a third cell has a ‘1’ logic value (also referred to as ‘SET’ state, in case of a PCM memory cell); while a second exemplary codeword may correspond to a combination of states [0 0 0 1]. To each codeword, a symbol may correspond, i.e., a value or data label to which the codeword is mapped (for example, the symbols ‘2’ or ‘3’ for the first and second exemplary codewords).

A reading (sense amplifier) circuit, configured to implement a decoding of the information stored in the coded manner, may for example be configured to identify the position and/or the number of the “ones” in the group of memory cells. This can be obtained by comparing, between each other (e.g., with pairwise comparisons), the currents of the memory cells in the group of cells.

One aspect of the present solution therefore provides a sense amplifier architecture, which, by way of example, can be implemented in the read block7of a non-volatile storage device1such as the one illustrated inFIG.1, that is configured to allow reading of the information stored, in a coded manner, in the non-volatile memory cells, implementing, in particular, comparisons between cell currents of different memory cells.

As shown inFIG.2, the sense amplifier architecture, denoted in general with10, comprises: a reading stage11, coupled to the array of memory cells3of a non-volatile storage device1(e.g., of the PCM type), and including a plurality of sense amplifier reading branches, one for each memory cell3, configured to read the respective cell current Icell; a comparison stage12, which is configured to perform a comparison of the cell currents of different memory cells3of a group, for example by comparing them pairwise obtaining respective pairwise comparison results, i.e., binary values, in particular bits, which are zeros or ones depending on which current of the two memory cells being compared is greater; and a logic stage13, configured to determine, based on the comparison results provided by the comparison stage12, a read codeword corresponding to the group of memory cells3and a corresponding decoded symbol. As will be discussed in further detail below, each of the reading stage11, the comparison stage12, and the logic stage13may be implemented in circuitry.

In more details,FIG.3shows a sense amplifier reading branch, denoted with15, of the reading stage11of the sense amplifier architecture10.

As previously discussed, the sense amplifier reading branch15is coupled to a respective memory cell3(here denoted as Cell_A), for example a PCM cell formed by a storage element3a(represented as a resistive element) and by an access element3b(in the example an NMOS transistor, having a gate terminal receiving a selection and biasing signal SEL, e.g., from the row decoder5ofFIG.1); the sense amplifier reading branch15is configured to provide an output signal sCOMP_A, which is indicative of the cell current Icellflowing through the same memory cell3, in particular being related by an inverse relation to the same cell current Icell.

In detail, the sense amplifier reading branch15comprises a bias transistor TP and a precharge transistor TPRECH, which are P-channel enhancement-mode transistors and have, for example, similar characteristics.

The source terminals of the bias transistor TP and of the precharge transistor TPRECH are connected to a supply node Ndd, which is set at a supply voltage Vdd, for example, equal to 1 Volt. The gate terminal of the bias transistor TP is connected to a reference node Nref, which is set at a reference voltage Vrefp_sa; a signal sPRECH_N is provided to the gate terminal of the precharge transistor TPRECH (this signal sPRECH and the corresponding negation sPRECH_N can be generated for example by the control logic CL, seeFIG.1, and can vary between 0 V and the supply voltage Vdd). Moreover, the drain terminals of the same bias transistor TP and precharge transistor TPRECH are connected to one another and define an input node Nin.

The sense amplifier reading branch15further comprises an upper control transistor TC and a lower control transistor TC′, which are P-channel enhancement-mode transistors and have, for example, similar characteristics.

The upper control transistor TC and the lower control transistor TC′ are connected together in series. In particular, the source terminal of the upper control transistor TC is connected to the input node Nin, whereas the drain terminal of the upper control transistor TC is connected to the source terminal of the lower control transistor TC′, the drain terminal of which forms an output node Nout, on which the output signal sCOMP_A is provided. A signal sPRECH is present on the gate terminal of the upper control transistor TC, which is equal to the logical negation of the above signal sPRECH_N; the aforementioned reference voltage Vrefp_sa(or a different reference voltage with a fixed value) is present on the gate terminal of the lower control transistors TC′.

The sense amplifier reading branch15further comprises a sense transistor TS and an evaluation transistor TE, which are of the N-channel enhancement-mode type, have similar characteristics and have their source terminals connected to a reference potential, e.g., to ground GND.

The drain terminals of the sense transistor TS and of the evaluation transistor TE are connected to the output node Nout; the gate terminal of the sense transistor TS is connected to the same output node Nout, the same sense transistor TS being therefore diode-connected. Moreover, a signal sEVAL_N is present on the gate terminal of the evaluation transistor TE (the signal sEVAL_N and the corresponding negation sEVAL can also be generated by the control logic CL and may vary between 0 V and the supply voltage Vdd).

The input node Ninis coupled to the memory cell3through a first-level decoding transistor TYO and a second-level decoding transistor TYM, which are N-channel enhancement-mode transistors, have, for example, similar characteristics and are connected together in series.

In particular, the drain terminal of the second-level decoding transistor TYM is connected to the input node Nin, whereas the source terminal of the second-level decoding transistor TYM is connected to the drain terminal of the first-level decoding transistor TYO, which is coupled to a main bitline MBL. The source terminal of the first-level transistor TYO is coupled to a local bitline LBL and therefore also to the storage element3aof the first memory cell3. Corresponding first-level decoding and second-level decoding bias signals, designated by YO and YM and generated, for example, by the column decoder4(seeFIG.1), are provided to the gate terminals of the first-level transistor TYO and, respectively, of the second-level transistor TYM (in a known manner, to select and bias the corresponding local bit line at a desired voltage for the memory operations).

With reference toFIG.4, a comparison circuit, denoted with20, of the comparison stage12of the sense amplifier architecture10is now disclosed in more details.

As discussed above, the comparison stage12includes a number of these comparison circuits20, each one configured to implement a respective comparisons between signals indicative of the cell currents Icellflowing through respective different memory cells3of the non-volatile memory device1(e.g., pairwise comparison between respective pairs of memory cells3).

In the example shown inFIG.4, the comparison circuit20is configured to perform a comparison between output signals sCOMP_A and sCOMP_B, respectively associated with a cell current Icellflowing through a first and a second memory cell, Cell_A and Cell_B (the same output signals sCOMP_A and sCOMP_B being provided by two different sense amplifier reading branches15of the reading stage11of the sense amplifier architecture10).

The comparison circuit20comprises a first cross-coupled transistor22and a second cross-coupled transistor24and a first enable transistor26and a second enable transistor28, which are P-channel enhancement-mode transistors and have, for example, similar characteristics.

The source terminals of the first and second cross-coupled transistors22,24and of the first and the second enable transistors26,28are connected to the supply node Ndd, and are therefore set at the supply voltage Vdd. The gate terminals of the first and second cross-coupled transistors22,24are connected, respectively, to the drain terminal of the second cross-coupled transistor24and to the drain terminal of the first cross-coupled transistor22.

The drain terminals of the first and second enable transistors26,28form, respectively, a first output node Nout1and a second output node Nout2of the comparison circuit20and are connected, respectively, to the drain terminal of the first and of the second cross-coupled transistors22,24. Moreover, a signal sEVAL, equal to the logical negation of the above referenced signal sEVAL_N, is provided on the gate terminals of both the first and the second enable transistors26,28.

The comparison circuit20further comprises a first output transistor30and a second output transistor32, which are N-channel enhancement-mode transistors and have, for example, similar characteristics.

The drain and source terminals of the first output transistor30are connected, respectively, to the first output node Nout1and to the reference potential (ground GND). The drain and source terminals of the second output transistor32are connected, respectively, to the second output node Nout2and to the reference potential. Moreover, the gate terminals of the first and of the second output transistors30,32are connected to the output node Noutr of a respective sense amplifier reading branch15, therefore receiving, in this example, the output signal sCOMP_A and, respectively, sCOMP_B.

The voltages present on the first output node Nout1and on the second output node Nout2are referred to as the signal sCOMP_OUT_N_AB and, respectively, the signal sCOMP_OUT_AB. Moreover, the pairs of logic values (sCOMP_A,sCOMP_B) and (sCOMP_OUT_AB,sCOMP_OUT_N_AB) are referred to, respectively, as the input state and the output state of the comparison circuit20.

As illustrated inFIG.5, the comparison stage12of the sense amplifier architecture10further comprises a respective latch circuit35for each of the above-discussed comparison circuits20.

The latch circuit35comprises two NAND gates35a,35b, having a respective first input connected to the first and, respectively, the second output nodes Nout1, Nout2of the corresponding comparison circuit20, so as to receive, respectively, the signal sCOMP_OUT_N_AB and the signal sCOMP_OUT_AB (in the example, referred to the comparison between Cell_A and Cell_B). The second input of each NAND gate35a,35bis connected to the output of the other NAND gate35b,35a.

The output of NAND gate35amoreover constitutes here the output of the latch circuit35, which provides a read data DATA_AB, which has a low or a high value (in the range [0 Vdd]), as a function of the comparison between the cell currents Icell, in the example of Cell_A and Cell_B.

According to the above, the sense amplifier architecture10allows performing a comparison between the states in which any given couple of memory cells3are in, and correspondingly a comparison between the respective cell currents Icell. In particular, comparison between the output signals provided by the respective sense amplifier reading branches15(for example, sCOMP_A and sCOMP_B) determines the pairs of logic values (e.g., sCOMP_A, sCOMP_B and sCOMP_OUT_AB, sCOMP_OUT_N_AB) at the input and at the output of the corresponding comparison circuit20and thus the read data DATA_AB resulting from the comparison and provided at the output of the latch circuit35.

The logic stage13is then configured to process the read data associated with a group of a determined number of non-volatile memory cells3and thereby determine the corresponding stored codeword.

Operation of the sense amplifier reading branch15and of the corresponding comparison circuit20is now discussed in more details, also referring to the time diagram ofFIG.6.

It is assumed that the first-level decoding and second-level decoding bias signals YO, YM are equal to ‘1’ and are therefore equal to a voltage value such that the first-level decoding transistor TYO and the second-level decoding transistors TYM are in a condition of saturation. For instance, the voltages of the first-level and second-level decoding bias signals YO, YM are comprised in a range between 1.2 and 1.4 V, and are therefore higher than the supply voltage Vdd. Furthermore, it is assumed, once again by way of example, that a voltage of 0.6 V is present on the local bitline LBL. In addition, it is assumed that a signal SEL that enables the access element3b, i.e., that allows selection of the memory cell3a, is present on the gate terminal of the access element3b.

It is also assumed that the reference voltage Vrefp_sais such that, when the precharge transistor TPRECH is inhibited, the bias transistor TP operates in saturation and a bias current Ipolhaving a desired value flows therethrough.

Albeit not shown, the reference node Nrefand the bias transistor TP may form part of current mirrors that can be controlled, for example by the control logic CL, so as to impose the above value Ipol. Without this implying any loss of generality, in what follows it is assumed that the reference voltage Vrefp_sais such that the value Ipolis approximately equal to 20 μA. In general, the reference voltage Vrefp_sais comprised between ground and the supply voltage Vdd; e.g., the relation 0.1V<Vrefp_sa<(Vdd-0.3V) applies.

Initially, the sense amplifier reading branch15is controlled, e.g., by the control logic CL, so as to carry out a precharging step.

In particular, at an instant to (seeFIG.6), the signal sEVAL is low (equal to ‘0,’ e.g., has a null voltage), whereas the signal sPRECH is high (‘1,’ e.g., is equal to the supply voltage Vdd). Moreover, the signal sPRECH_N is ‘0’; therefore, the precharge transistor TPRECH operates in linear region and a precharge current Iprechpasses therethrough. The precharge current Iprechis, for example, of the order of 100 μA and is in any case higher than the value Ipol.

A current Ii, which is equal to the sum of the bias current Ipoland the precharge current Iprech, is therefore injected into the input node Nin.

At the same instant t0, the upper control transistor TC is inhibited and also the lower control transistors TC′ is inhibited.

All the current Iiflows in the memory cell3aand charges a capacitance formed by the main bitline MBL. In practice, the main bitline MBL, which is associated with a capacitance that is much higher than those associated with the local bitlines, is charged.

In addition, at the instant t0, the signal sEVAL_N is equal to ‘1,’ and therefore the evaluation transistor TE operates in linear region, and consequently discharges, i.e., forces to ground, the output node Nout. Consequently, the signal sCOMP_A (and analogously the signal sCOMP_B of the corresponding sense amplifier reading branch15) is equal to ‘0’; this means that the sense transistor TS is off.

The output transistors30,32of the comparison circuit30are also inhibited.

Moreover, since sEVAL is equal to ‘0,’ the first and the second enable transistors26,28are above the threshold and force the logic values of the signals sCOMP_OUT_AB and sCOMP_OUT_N_AB to ‘1.’ Consequently, the first and the second cross-coupled transistors22,24are below the threshold.

It is noted that in this step the latch circuit35operates in a condition of storage; i.e., the read data DATA_AB maintains the last value assumed.

At a subsequent instant t1, the signals sPRECH and sPRECH_N switch their values, causing the precharging step to end and an evaluation step to start.

In particular, the signal sPRECH_N goes to ‘1,’ and this leads to switching-off of the precharge transistor TPRECH, and therefore also of the corresponding precharge current Iprech. Instead, the signals sEVAL and sEVAL_N remain, respectively, equal to ‘0’ and to ‘1.’ Consequently, the output node Noutr remains at ground, and therefore the signals sCOMP_A remains equal to ‘0,’ while the signals sCOMP_OUT_AB and sCOMP_OUT_N_AB remain equal to ‘1.’

The fact that, at the instant t1, the signal sPRECH becomes equal to ‘0’ means that the upper control transistor TC switches on and starts to operate in saturation; also the lower control transistor TC′ switches on and starts to operate in saturation.

In the abovementioned conditions, the cell currents Icellthat flows in the memory cells (Cell_A and Cell_B) depend on the values of resistance of the respective storage elements3a, and therefore upon the data stored.

In particular, a branch current Ibranchequal to Ipol−Icellnow flows through the upper control transistor TC and the lower control transistor TC′ towards the sense transistor TS.

At a subsequent instant t2, the signals sEVAL and sEVAL_N switch their value, causing the evaluation step to end and a reading step to start.

In particular, at the instant t2, the signal sEVAL_N becomes ‘0,’ and this leads to switching-off of the evaluation transistor TE, which was keeping at ground the output node Noutr, the voltage (i.e., the signals sCOMP_A and sCOMP_B) of which therefore becomes free to vary.

Therefore, the signals sCOMP_A and sCOMP_B (corresponding to the gate to source voltage of the sense transistor TS) start rising from the initial zero value, with a speed and timing that is dependent on the value of the cell current Icell(in particular as a function of the above branch current Ibranch).

For example, in case Cell_A stores a ‘1’ logic value and Cell_B stores a ‘0’ logic value, the voltage signal sCOMP_B will increase more rapidly than voltage signals sCOMP_A (since the branch current Ibranchwill be higher for Cell_B).

Moreover, since the signal sEVAL has assumed the value ‘1,’ the first and the second enable transistors26,28of the comparison circuit20drop below the threshold, thus letting the output nodes Nout1, Nout2to be free to evolve, in particular based on the value of the signals sCOMP_A and sCOMP_B at the gates of the first and second output transistors30,32.

The fastest of signals sCOMP_A and sCOMP_B provides the flip direction to the comparison circuit30, that the following latch circuit35then defines in the [GND Vdd] range, providing the read data DATA_AB (which, in the example, will have a low value, ‘0’).

FIG.7shows a possible variant embodiment for the sense amplifier reading branch15, which differs from what discussed with reference toFIG.3for a different configuration of the sense transistor TS, which is again of a NMOS type, but here is not diode-connected.

In this case, the gate terminal of the sense transistor TS is connected to the output node Noutr and the source and drain terminals are connected to the reference potential (ground, GND), as is the source terminal of the evaluation transistor TE.

It is noted that a sense capacitive element could be connected between the output node Noutr and the reference potential (GND), instead of the sense transistor TS.

In this embodiment, the branch current Ibranch(equal to Ipol−Icell) therefore charges a capacitive node (i.e., the gate terminal of the sense transistor TS), thus causing the increase of the output signal (in this case, sCOMP_A) at the output node Noutr, again with a speed that is a function of the value of the same branch current Ibranchbut in this case with no saturation at a value defined by the gate-source voltage of the same sense transistor TS.

Another difference of this embodiment relates to the configuration of the latch circuit35for each of the comparison circuits20(which comparison circuits20instead do not differ with respect to what has been discussed above).

As shown inFIG.8, the latch circuit35here further comprises an output latch36, which provides at a latching output the read data (e.g., DATA_AB in case of a comparison between memory cells Cell_A and Cell_B) and has a latching input coupled to the output of NAND gate35a; the output latch36moreover has an enable input, which receives an enabling signal E defining a read window timing for latching of the read data DATA_AB.

The latch circuit35comprises a further NAND gate35creceiving at its input both signals sCOMP_OUT_AB and sCOMP_OUT_N_AB and providing, though a buffer37, the above enabling signal E for the output latch36.

The read window timing is therefore defined by the evolution of signals sCOMP_OUT_AB and sCOMP_OUT_N_AB (at the output nodes Nout1, Nout2of the comparison circuit20), which are both high when the reading step starts and evolve to low; once the enabling signal E is high, reading is concluded and the read data DATA_AB is latched by the output latch36.

A further aspect of the present solution is now discussed, regarding a possible coding of the stored data in the memory array (and a corresponding configuration of the logic stage13).

According to this coding, given a set of codewords obtainable by the stored values of a determined number Ncof non-volatile memory cells in a group, information can be stored in at least two subsets of this set of codewords comprising each at least a codeword, each codeword in a same subset having a same Hamming weight and each codeword belonging to one subset having a Hamming distance equal or greater than two with respect to each codeword belonging to another subset.

For instance, the number Ncof memory cells3in a group can be three, as shown in the Table 1 below. With three cells (Cell_A, Cell_B, Cell_C) and two subsets (SB1, SB2), four codewords can be defined: {000, 011, 101, 110}; thus, four symbols (or bit maps) can be obtained for coding of the stored data.

TABLE 1Cell_ACell_BCell_CSubsetSymbolBit map110SB1000101SB1101011SB1210000SB2311

In another example, the number Nccan be four as shown in Table 2 below. With four cells (Cell_A, Cell_B, Cell_C, Cell_D) and two subsets (SB1, SB2), eight codewords can be defined and eight symbols for coding of the stored data.

TABLE 2Cell_ACell_BCell_CCell_DSubsetSymbolBit map1000SB100000100SB110010010SB120100001SB130110111SB241001011SB251011101SB261101110SB27111

In this embodiment, when reading (or decoding) the data stored in the coded manner, the subset the data belongs to is determined first.

The reading stage11of the sense amplifier architecture10therefore further comprises a subset definition circuit40(for each group of memory cells3defining a codeword), configured to allow determination of the subset to which a codeword to be read belongs to.

This subset definition circuit40is implemented as a comparator, configured to compare a signal indicative of the sum of the cell currents Icellof all the memory cells3in the group (defining the codeword to be read) with at least a threshold signal, indicative of a reference or fixed current Iref, whose suitable value allows a correct discrimination between the subsets.

As previously discussed, the sum actually implemented is between each branch current Ibranch, i.e., the cell current Icellreferred to the bias current Ipol, i.e.: (Ipol−IcellA)+(Ipol−IcellB)+(Ipol−IcellC). Analogously, the threshold signal is referred to the same bias current Ipol(actually, to three times the same bias current Ipol), in order to implement the correct comparison and the subset discrimination.

In the example of Table 1, in which a codeword is defined by three memory cells, codewords in the first subset have two memory cells in the ‘SET’ (or ‘1’) state and one in the ‘RESET’ (or ‘0’) state, while codewords in the second subset have no memory cell in the ‘SET’ state and three in the ‘RESET’ state. In this example, the threshold signal may be indicative of a reference or fixed current Irefwhose value corresponds to that of a single reference memory cell in the ‘SET’ state: Iref=Iref_SET.

For example, current Irefcan be obtained as an average of the current of a certain number of non-volatile memory cells3programmed in the same state (in this case, the SET state); alternatively, the current Irefcan be obtained from a chosen typical cell in the SET state or from another fixed current of a suitable value.

In more details, and as shown inFIG.9A, the subset definition circuit40in this case comprises, analogously to the comparison circuits20discussed above: a first cross-coupled transistor, again denoted with22, and a second cross-coupled transistor24and a first enable transistor26and a second enable transistor28, of a P-channel enhancement-mode.

The source terminals of the first and second cross-coupled transistors22,24and of the first and the second enable transistors26,28are connected to the supply node Ndd, and are therefore set at the supply voltage Vdd. The gate terminals of the first and second cross-coupled transistors22,24are connected, respectively, to the drain terminal of the second cross-coupled transistor24and to the drain terminal of the first cross-coupled transistor22.

The drain terminals of the first and second enable transistors26,28form, respectively, a first output node Nout1and a second output node Nout2and are connected, respectively, to the drain terminals of the first and of the second cross-coupled transistors22,24. Moreover, a signal sEVAL, equal to the logical negation of the above referenced signal sEVAL_N, is provided on the gate terminals of the first and the second enable transistors26,28.

The subset definition circuit40further comprises a number Ncof first output transistors30(corresponding to the number of memory cells3in the codeword), coupled in parallel, between the first output node Nout1and the reference potential (GND), receiving at a respective gate terminal the output signal (in the example, sCOMP_A, sCOMP_B, sCOMP_C) provided by a respective sense amplifier reading branch15of the sense amplifier architecture10.

The subset definition circuit40moreover comprises, in this example (which is referred to the coding of Table 1), a single second output transistor32, which is a N-channel enhancement-mode transistor, connected between the second output node Nout2and the reference potential (GND) and receiving at a gate terminal a comparison signal sCOMP_SET indicative of the reference or fixed current Iref(whose value corresponds in this case to Iref_SET).

At the first and at the second output nodes Nout1, Nout2, a respective output signal sCOMP_OUT_N_REF and sCOMP_OUT_REF is present, indicative of the determined subset. In the example, the signal sCOMP_OUT_REF is ‘0’ for subset SB1and signal sCOMP_OUT_N_REF is ‘0’ for subset SB2.

The reading stage11of the sense amplifier architecture10further comprises a respective latch circuit for each of the above-discussed subset definition circuit40.

The latch circuit (in a corresponding manner as the circuit shown inFIG.5) comprises two NAND gates, having a respective first input connected to the first and, respectively, the second output nodes of the corresponding subset definition circuit40, so as to receive, respectively, the signal sCOMP_OUT_N_REF and the signal sCOMP_OUT_REF. The second input of each NAND gate is connected to the output of the other NAND gate.

The output of NAND gate moreover constitutes here the output of the latch circuit, which provides a subset data DATA_REF, which has a low or a high value, indicative of the determined subset. In the example, DATA_REF is ‘0’ for subset SB1and ‘1’ for subset SB2.

In case the encoding of Table 2 is implemented, as shown inFIG.9B, the subset definition circuit40comprises a certain number of second output transistors32, which are N-channel enhancement-mode transistors, connected between the second output node Nout2and the reference potential (GND) and receiving at a gate terminal a respective comparison signal sCOMP_SET or sCOMP_RESET indicative of a respective reference or fixed current Iref(whose value may correspond in this case to either Iref_SETor Iref_RESET, i.e., a reference or fixed current whose value corresponds to that of a single reference memory cell in the ‘RESET’ state).

Indeed, in case the codeword is defined by four memory cells, codewords in the first subset SB1have one memory cell in the ‘SET’ state and three memory cells in the ‘RESET’ state; while codewords in the second subset SB2have three memory cells in the ‘SET’ state and one in the ‘RESET’ state.

In this example, the threshold signal may thus be indicative of a reference or fixed current Irefwhose value corresponds to any suitable combination of reference memory cells in the ‘SET’ or ‘RESET’ state, for example: Iref=2·Iref_SET+2·Iref_SET.

Also in this example, the signal sCOMP_OUT_REF is ‘0’ for subset SB1and signal sCOMP_OUT_N_REF is ‘0’ for subset SB2.

FIG.10shows a possible implementation of a reference generation circuit50in the sense amplifier architecture10, configured to generate the above signals sCOMP_SET and, respectively, sCOMP_RESET for the subset definition circuit40.

This circuit largely corresponds to a sense amplifier reading branch15of the reading stage11of the sense amplifier architecture10(shown inFIG.3), so that similar elements will be denoted with the same reference numbers and will not be discussed again in detail.

Differently from the sense amplifier reading branch15, in this reference generation circuit50the local bit line (in this case being “dummy,” not being connected to a memory cell) is coupled to a reference generator52configured to generate the reference or fixed current Iref.

The reference generator52comprises a first enabling transistor53aand a first reference transistor54a, both of the NMOS type, connected in series between the (dummy) local bit line LBL and the reference potential (GND), the first enabling transistor53ahaving a gate terminal receiving a first enabling signal EN1 and the first reference transistor54ahaving a gate terminal receiving a first reference voltage VREF_SET (or VREF_RESET), being indicative of the current Iref_SETof a reference memory cell in the ‘SET’ state (or analogously of the current Iref_RESETof a reference memory cell in the ‘RESET’ state).

The reference generator52further comprises a second enabling transistor53band a second reference transistor54b, both of the NMOS type, connected in series between the (dummy) local bit line LBL and the reference potential (GND), the second enabling transistor53bhaving a gate terminal receiving a second enabling signal EN2 and the second reference transistor54bhaving a gate terminal receiving a second reference voltage VREF_IFIX, being indicative of a fixed value for the current Iref_SETor Iref_RESET, simulating the current circulating in a memory cell3in the SET or RESET state.

Depending on the values of the first and second enabling signals EN1, EN2, the reference generation circuit50thus generates the above signals sCOMP_SET, sCOMP_RESET, being indicative of a reference or fixed current Iref(whose value corresponds to Iref_SET, respectively to Iref_RESET).

An exemplary disclosure is now provided concerning operation of the logic stage13of the sense amplifier architecture10, configured to process the read data associated with a group of non-volatile memory cells3and thereby determine the corresponding stored codeword (as previously discussed, a majority logic may be implemented to identify the stored codeword).

Reference is first made to the exemplary coding of the above Table 1, assuming, as an example, that a codeword [0 1 1] has been stored, with Cell_A=‘0,’ Cell_B=‘1’ and Cell_C=‘1.’

The following table, Table 3, summarizes the results expected at the output of the comparison circuits20(considering that DATA_REF is ‘1’:

TABLE 3ComparisonResultDATA_AB, A vs BB winDATA_AC, A vs CC winDATA_BC, B vs CB or C either can win, X

It is noted that cell_A with value ‘0’ loses the three comparisons with the other two cells (Cell_B and Cell_C); the logic stage13thus determines that the stored codeword is [0 1 1].

In this example, if DATA_REF is ‘0,’ then the stored codeword is [0 0 0], independently by the comparison results.

Reference is now made to the exemplary coding of the above Table 2, assuming, as an example, that a codeword [0 0 0 1] has been stored, with Cell_A=‘0,’ Cell_B=‘0,’ Cell_C=‘0’ and Cell_D=‘1.’

Again, a majority logic may be implemented by the logic stage13to identify the stored codeword.

The following table, Table 4, summarizes in this case the results expected at the output of the comparison circuits20(considering that DATA_REF is ‘1’):

TABLE 4ComparisonResultDATA_AB, A vs BA or B either can win, XDATA_AC, A vs CA or C either can win, XDATA_AD, A vs DDDATA_BC, B vs CB or C either can win, XDATA_BD, B vs DDDATA_CD, C vs DD

It is noted that cell_D with value 1 wins the three comparisons with the other three memory cells3; the logic stage13thus determines that the stored codeword is [0 0 0 1]; in other words, it is sufficient to identify the position of maximum current, for the codewords in Subset SB1(it is analogously sufficient to identify the position with minimum current, in case of Subset SB2).

The advantages that the present solution allows to achieve are clear from the foregoing description.

In general, the sense amplifier architecture10allows to compare the data stored in any memory cell3of the non-volatile memory device1with any suitable number of other memory cells3, so as to decode the codewords used for storing information.

Accordingly, the solution here described allows to achieve a more compact and efficient memory occupation.

Also, the solution here described necessitates less memory cells3to compose the array, determining a possible yield improve.

Moreover, the disclosed solution provides similar access time as available solutions, with no timing penalty.

The resulting non-volatile storage device1can therefore find use in numerous contexts.

For instance,FIG.11illustrates a portion of an electronic apparatus70, which may, for example, be: a PDA (Personal Digital Assistant); a portable or desktop computer, possibly with capacity of wireless data transfer; a mobile phone; a digital audio player; a camera or a camcorder; or further devices capable of processing, storing, transmitting, and receiving information.

The electronic apparatus70comprises: a controller71(for example, provided with a microprocessor, a DSP or a microcontroller); an input/output device72(for example, provided with a keypad and a display), for input and display of data; the non-volatile storage device1; a wireless interface74, for example an antenna, for transmitting and receiving data through a radiofrequency wireless communication network; and a RAM75. All the components of the electronic apparatus70are coupled through a bus76. A battery77can be used as electrical power supply source in the electronic apparatus70, which may moreover be equipped with a camera, or video camera or camcorder68. Moreover, the controller71can control the non-volatile storage device1, for example co-operating with the control logic CL.

In addition, it is clear that modifications and variations may be made to what has been described and illustrated herein, without, thereby, departing from the scope of the present disclosure.

For instance, it is again underlined that the present sense amplifier architecture10can be used for memory cells3, which may be different from memory cells of a PCM type, e.g., for ST-RAM or RRAM memory cells.

A sense amplifier architecture (10) for a non-volatile memory device (1) may be summarized as including a plurality of memory cells (3), wherein groups of memory cells store respective codewords formed by stored logic states, logic high (‘1’) or logic low (‘0’), of the memory cells of the group; said sense amplifier architecture (10) including a plurality of sense amplifier reading branches (15), each sense amplifier reading branch (15) coupled to a respective memory cell (3) and configured to provide an output signal (sCOMP_A), which is indicative of a cell current (Icell) flowing through the same memory cell (3); a comparison stage (12), configured to perform a comparison between the cell currents (Icell) of memory cells (3) of a group; and a logic stage (13), configured to determine, based on comparison results provided by the comparison stage (12), a read codeword corresponding to the group of memory cells (3).

The output signal (sCOMP_A) of the sense amplifier reading branch (15) may be related by an inverse relation to the respective cell current (Icell).

The output signal (sCOMP_A) of the sense amplifier reading branch (15) may be a function of a branch current (Ibranch) flowing through the sense amplifier reading branch (15), given by:
Ibranch=Ipol−Icell,
wherein Ipolis a bias current provided to the sense amplifier reading branch (15) and Icellis said cell current.

The sense amplifier reading branch (15) may include a bias transistor (TP) coupled between a power supply node (Ndd) and an input node (Nin) and having a gate terminal receiving a reference voltage (Vrefp_sa), so that a bias current (Ipol) flows therethrough and to the input node; wherein the memory cell (3)may be coupled to the input node (Nin) via at least a selection transistor (TYM, TYO) enabling selection of the memory cell (3); the sense amplifier reading branch (15) may further include a current sensing element (TS) coupled to the input node (Nin) and configured to provide the output signal (sCOMP_A) as a function of a branch current (Ibranch), being a difference between the bias current (Ipol) and the cell current (Icell) flowing through the selected memory cell.

The current sensing element (TS) may be a sense transistor, diode-connected between an output node (Nout) on which the output signal (sCOMP_A) is provided and a reference terminal (GND); wherein the output node (Nout) is coupled to the input node (Nin) via a switch element (TC).

The sense amplifier reading branch (15) may further include a forcing transistor (TE) having a drain terminal coupled to an output node (Nout) on which the output signal (sCOMP_A) is provided, a source terminal coupled to a reference terminal (GND) and a gate terminal receiving an enabling signal (sEVAL_N) such as to, alternatively, couple the output node (Nout) to the reference terminal (GND) or enable an evolution of the voltage on the output node (Nout) as a function of the branch current (Ibranch); wherein the current sensing element (TS) is a sense transistor, coupled between the source terminal of the forcing transistor (TE) and the reference terminal (GND) and having a gate terminal coupled to the output node (Nout); wherein the output node (Nout) is coupled to the input node via a switch element (TC).

The comparison stage (12) may be configured to perform pairwise comparisons between the output signals (sCOMP_A, SCOMP_B) of the sense amplifier reading branches (15) coupled to respective memory cells (3) of the group, obtaining respective pairwise comparison results, depending on which cell current of the memory cells (3) being compared is higher; wherein the logic stage (13) is configured to determine the read codeword based on the pairwise comparison results.

The logic stage (13) may be configured to determine the read codeword based on a majority logic.

Given a set of codewords obtainable by the stored values in the memory cells (3) in a group, information may be stored in at least two subsets (SB1, SB2) of said set of codewords, may include each at least a codeword, each codeword in a same subset having a same Hamming weight and each codeword belonging to one subset (SB1) having a Hamming distance equal or greater than two with respect to each codeword belonging to another subset (SB2); wherein the sense amplifier architecture (10) may further include a subset definition circuit (40) for each group of memory cells (3), configured to allow determination of the subset to which a codeword to be read belongs.

The logic stage (13) may be configured to determine the read codeword corresponding to the group of memory cells (3) also based on the subset determination by the subset definition circuit (40).

The subset definition circuit (40) may include a comparator circuit, configured to compare a signal indicative of a sum of the cell currents (Icell) of all the memory cells (3) in the group with a threshold signal, whose value allows a discrimination between the subsets (SB1, SB2).

The threshold signal may be indicative of a reference or fixed current (Iref), being a combination of one or more cell currents in memory cells (3) being in a first logic state and/or of one or more cell currents in memory cells (3) being in a second logic state.

The subset definition circuit (40) may include a first cross-coupled transistor (22) and a second cross-coupled transistor (24) connected between a power supply node (Ndd) and a first (Nout1), respectively a second (Nout2), output and having gate terminals connected, respectively, to the second and first output nodes; a number of first output transistors (30), the number corresponding to the number of memory cells (3) in the codeword, coupled in parallel, between the first output node (Nout1) and a reference potential (GND), receiving at a respective gate terminal the output signal (sCOMP_A, sCOMP_B, sCOMP_C) provided by a respective sense amplifier reading branch (15); and at least an output transistor (32), coupled between the second output node (Nout2) and the reference potential (GND) and receiving at a gate terminal a comparison signal (sCOMP_SET, sCOMP_RESET) indicative of the reference or fixed current (Iref); wherein, at the first and at the second output nodes (Nout1, Nout2) a respective output signal (sCOMP_OUT_N_REF, sCOMP_OUT_REF) is present, indicative of the determined subset.

A memory device (1) may be summarized as including at least a sense amplifier architecture (10) according to any one of the embodiments described above, the memory device (1) may further include said memory cells (3), the memory cells (3) being of the type in which the stored logic state is changed through application of a current and the stored logic state in the memory cell is read by reading a current flowing therethrough.

The memory cells (3) may be PCM—Phase Change Memory—cells.

The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.