Patent ID: 12206430

DESCRIPTION OF EMBODIMENTS

Embodiment

(1) Overview

As shown inFIG.1, an A/D converter1according to an exemplary embodiment includes an input switching circuit2and a successive approximation register (SAR) A/D converting section3. Note that the A/D converting section3according to this embodiment is a noise-shaping SAR A/D converting section having a configuration in which an integrating circuit is provided as an additional constituent element for the SAR A/D converting section.

The input switching circuit2receives a plurality of analog input voltages (e.g., two analog input voltages V1, V2inFIG.1) and outputs, as a voltage V3to be converted, one analog input voltage selected from the plurality of analog input voltages. The A/D converting section3performs A/D conversion of converting the voltage V3to be converted, supplied from the input switching circuit2, into a multi-bit digital signal (D1or D2). The input switching circuit2selects, when a conversion operation of converting the voltage V3to be converted has been performed by the A/D converting section3, another analog input voltage, as the voltage V3to be converted, from the plurality of analog input voltages.

The A/D converting section3performs the conversion operation on a target bit basis from a most significant bit through a least significant bit. The A/D converting section3includes a control unit4, a D/A converting unit5, a comparison reference voltage generating unit6, and a comparator7.

The D/A converting unit5generates an analog comparative voltage with respect to a target bit in accordance with a control signal S1supplied from the control unit4. In other words, the D/A converting unit5generates an analog comparative voltage, corresponding to the target bit, in accordance with the control signal S1supplied from the control unit4. The analog comparative voltage corresponding to the target bit is an analog voltage corresponding to a digital signal. The values of the digital signal from the most significant bit thereof through a bit which is more significant by one than the target bit are determined by the comparator7. The value of the target bit of the digital signal is “1.” The value of the bit next to the target bit of the digital signal through the least significant bit thereof is “0.”

The comparison reference voltage generating unit6generates a comparison reference voltage V5corresponding to the analog input voltage that has been selected as the voltage V3to be converted.

The comparator7determines a value of the target bit by comparing a differential voltage V4between the voltage V3to be converted and the comparative voltage with the comparison reference voltage V5.

The control unit4determines, based on a result of comparison made by the comparator7with respect to the target bit, the control signal S1with respect to the bit next to the target bit. In other words, the control unit4determines, based on a result of comparison made by the comparator7with respect to the target bit, a comparative voltage to be generated by the D/A converting unit5with respect to the bit next to the target bit and also determines the control signal S1to generate the comparative voltage thus determined.

The comparison reference voltage generating unit6includes an integrator61, a plurality of (e.g., two in the example shown inFIG.1) capacitors C11, C12, and a switching circuit62.

The integrator61integrates the differential voltage V4in a state where the A/D converting section3has performed the conversion operation on the least significant bit. The plurality of capacitors C11, C12are provided in association with the plurality of analog input voltages V1, V2, respectively. The switching circuit62selectively connects a capacitor C11or C12, associated with the analog input voltage V1or V2selected as the voltage V3to be converted, out of the plurality of capacitors C11, C12to an output terminal of the integrator61. The capacitor C11or C12, connected to the output terminal of the integrator61via the switching circuit62, out of the plurality of capacitors C11, C12is charged with an output voltage of the integrator61. The comparison reference voltage generating unit6uses, as the comparison reference voltage V5, a charge voltage for the capacitor C11or C12, associated with the analog input voltage V1or V2selected as the voltage V3to be converted, out of the plurality of capacitors C11, C12.

In the A/D converter1according to this embodiment, the input switching circuit2selects, when a conversion operation of converting the voltage V3to be converted has been performed by the A/D converting section3, another analog input voltage, as the voltage V3to be converted, from the plurality of analog input voltages V1, V2. Thus, the A/D converter1may A/D convert the plurality of analog input voltages V1, V2time-sequentially. In addition, the A/D converter1according to this embodiment includes a plurality of capacitors C11, C12associated with the plurality of analog input voltages V1, V2, respectively. Furthermore, each of the plurality of capacitors C11, C12is charged with the result of integration performed by the integrator61in a situation where an associated analog input voltage V1, V2is used as the voltage V3to be converted. The charge voltage V51, V52for the capacitor C11, C12is used as the comparison reference voltage V5when the associated analog input voltage V1, V2is A/D converted next time. Thus, the conversion error may be reduced by using an integrated value of the conversion error involved with the A/D conversion as the comparison reference voltage V5for the next A/D conversion. This enables providing an A/D converter1with the ability to A/D convert the plurality of analog input voltages time-sequentially while reducing the conversion error.

In the exemplary embodiment to be described below, a situation where the input switching circuit2receives two analog input voltages V1, V2and the A/D converter1alternately A/D converts the two analog input voltages V1, V2time-sequentially will be described as an example. Note that the number of the analog input voltages supplied to the input switching circuit2does not have to be two. Alternatively, three or more analog input voltages may be supplied to the input switching circuit2and the A/D converter1may A/D convert three or more analog input voltages time-sequentially.

(2) Details

(2.1) Configuration

Next, a configuration for an A/D converter1according to this embodiment will be described in further detail with reference toFIGS.1and2. Note thatFIGS.1and2are schematic circuit diagrams of the A/D converter1, of which the circuit configuration is illustrated in a simplified form with illustration of some components thereof omitted.

The A/D converter1according to this embodiment is a noise-shaping successive approximation register (SAR) A/D converter. The A/D converter1includes the input switching circuit2and the A/D converting section3as described above. In addition, the A/D converter1according to this embodiment includes not only the input switching circuit2and the A/D converting section3but also input terminals TA1, TA2, a serial-parallel converting unit (abbreviated as “SP” inFIG.1)8, and a filter circuit9as well. As used herein, the “terminal” may naturally refer to a part (terminal) to which an electric wire, for example, is connected, but may also be a lead of an electronic component or a part of a conductor formed as wiring on a circuit board.

The input terminal TA1receives an analog input voltage V1and the input terminal TA2receives an analog input voltage V2. The analog input voltages V1, V2may be, for example, output signals of various types of sensors such as acceleration sensors, angular velocity sensors, or gyrosensors.

An output terminal TA3of the input switching circuit2is connected to one input terminal of the comparator7. The input switching circuit2includes a switch21connected between the input terminal TA1and the output terminal TA3and a switch22connected between the input terminal TA2and the output terminal TA3. The switches21,22may be, for example, semiconductor switches such as CMOS transistors and are turned ON and OFF in accordance with control signals φA, φB supplied from the control unit4. When the switch21turns ON and the switch22turns OFF, the analog input voltage V1is supplied as the voltage V3to be converted from the input switching circuit2to the A/D converting section3. On the other hand, when the switch21turns OFF and the switch22turns ON, the analog input voltage V2is supplied as the voltage V3to be converted from the input switching circuit2to the A/D converting section3.

The A/D converting section3includes the control unit4, the D/A converting unit5, the comparison reference voltage generating unit6, and the comparator7.

The control unit4may be implemented as a wired logic, for example. The control unit4makes the A/D converter1A/D convert the analog input voltages V1, V2alternately and time-sequentially by controlling the operations of the input switching circuit2, the D/A converting unit5, the comparison reference voltage generating unit6, and the filter circuit9. Alternatively, the control unit4may also be implemented as a computer system including one or more processors and a memory.

The D/A converting unit5may be a 12-bit D/A converting unit, for example, and may be implemented as a combination of a low-order D/A converting unit51for the least significant four bits and a high-order D/A converting unit52for the most significant eight bits.

The D/A converting unit5is a capacitive D/A converting unit including a plurality of capacitors C1, C2and a voltage switching circuit55. Each of the plurality of capacitors C1, C2has one terminal thereof connected to the output terminal TA3of the input switching circuit2. The voltage switching circuit55selectively connects the other terminal of each of the plurality of capacitors C1, C2to either a first voltage VH or a second voltage VL in accordance with the control signal S1supplied from the control unit4. The D/A converting unit5is a capacitive D/A converting unit including the plurality of capacitors C1, C2and the voltage switching circuit55. This achieves the advantage of making the D/A converting unit5implementable as a simple circuit. The first voltage VH and the second voltage VL are DC voltages each having a constant voltage value. The first voltage VH is set at a voltage higher than the second voltage VL.

The low-order D/A converting unit51includes a plurality of capacitors C1and a plurality of switches Q1provided for the plurality of capacitors C1, respectively. Each of the plurality of capacitors C1has one terminal thereof connected to the output terminal TA3of the input switching circuit2. The plurality of switches Q1may be implemented as, for example, semiconductor switches such as CMOS transistors. The plurality of switches Q1each selectively connect an associated one of the plurality of capacitors C1to either the first voltage VH or the second voltage VL in accordance with the control signal S1supplied from the control unit4.

On the other hand, the high-order D/A converting unit52includes a plurality of capacitors C2and dynamic element matching (DEM) circuits53,54. Each of the plurality of capacitors C2has one terminal thereof connected to the output terminal TA3of the input switching circuit2. The plurality of DEM circuits53,54each selectively connect an associated one of the plurality of capacitors C2to either the first voltage VH or the second voltage VL in accordance with the control signal S1supplied from the control unit4.

In this embodiment, the voltage switching circuit55is formed by the plurality of switches Q1and the DEM circuits53,54. The plurality of switches Q1and the DEM circuits53,54selectively connect each of the plurality of capacitors C1, C2to either the first voltage VH or the second voltage VL in accordance with the control signal S1supplied from the control unit4. This allows the D/A converting unit5to generate a comparative voltage with a desired voltage value. In this embodiment, the output terminal of the D/A converting unit5is connected, as well as the output terminal TA3of the input switching circuit2, to one input terminal of the comparator7. This allows the differential voltage V4between the voltage V3to be converted supplied from the input switching circuit2and the comparative voltage generated by the D/A converting unit5to be supplied to the one input terminal of the comparator7.

The comparison reference voltage generating unit6includes the integrator61, the plurality of (e.g., two in this embodiment which is as many as the analog input voltages V1, V2) capacitors C11, C12, and the switching circuit62.

FIG.2illustrates a specific exemplary circuit configuration for the integrator61. The integrator61according to this embodiment includes multiple stages of integrating circuits61A,61B,61C for performing integration operations sequentially. These multiple stages of integrating circuits61A-61C perform integration operations using operational amplifiers OP1-OP3, respectively.

The integrating circuit61A is an integrating circuit on the first stage. The integrating circuit61A includes the operational amplifier OP1, a capacitor C21, and a switch Q21. An inverting input terminal of the operational amplifier OP1is connected to an input terminal TA4of the integrator61via the switch Q21. The capacitor C21is connected between the inverting input terminal and output terminal of the operational amplifier OP1. A non-inverting input terminal of the operational amplifier OP1is connected to a reference voltage for the A/D converter1. In this embodiment, the integrating circuit61A is formed by the operational amplifier OP1, a capacitor of the D/A converting unit5connected to the input terminal TA4, and the capacitor C21. The output terminal of the operational amplifier OP1(i.e., an output terminal of the integrating circuit61A) is connected to an input terminal of the integrating circuit61B.

The integrating circuit61B is an integrating circuit on the second stage. The integrating circuit61B includes the operational amplifier OP2, capacitors C22-C24, and switches Q22-Q25. An inverting input terminal of the operational amplifier OP2is connected to the input terminal TA4of the integrator61via the switches Q22, Q23. In addition, the inverting input terminal of the operational amplifier OP2is also connected to the output terminal of the integrating circuit61A via the switches Q24, Q25. A non-inverting input terminal of the operational amplifier OP2is connected to a reference potential for the A/D converter1. In this embodiment, a node of connection between the switches Q22, Q23is connected to the reference voltage for the A/D converter1via the capacitor C22. A node of connection between the switches Q24, Q25is connected to the reference voltage for the A/D converter1via the capacitor C23. The capacitor C24is connected between the inverting input terminal and output terminal of the operational amplifier OP2. The output terminal of the operational amplifier OP2(i.e., an output terminal of the integrating circuit61B) is connected to an input terminal of the integrating circuit61C.

In this embodiment, a feed forward path FF1is formed between the input terminal TA4of the integrator61and the input terminal of the operational amplifier OP2included in the integrating circuit61B on the second stage. The differential voltage V4supplied through the input terminal TA4of the integrator61is sampled by the capacitor C22. As a result, the differential voltage V4thus sampled is supplied to the operational amplifier OP2of the integrating circuit61B on the second stage.

The integrating circuit61C is an integrating circuit on the third stage. The integrating circuit61C includes an operational amplifier OP3, capacitors C25-C27, and switches Q26-Q29. An inverting input terminal of the operational amplifier OP3is connected to the input terminal TA4of the integrator61via the switches Q26, Q27. In addition, the inverting input terminal of the operational amplifier OP3is also connected to the output terminal of the integrating circuit61B (i.e., the output terminal of the operational amplifier OP2) via the switches Q28, Q29. A non-inverting input terminal of the operational amplifier OP3is connected to the reference potential for the A/D converter1. In this embodiment, a node of connection between the switches Q26, Q27is connected to the reference voltage for the A/D converter1via the capacitor C25. A node of connection between the switches Q28, Q29is connected to the reference voltage for the A/D converter1via the capacitor C26. The capacitor C27is connected between the inverting input terminal and output terminal of the operational amplifier OP3.

In this embodiment, a feed forward path FF2is formed between the input terminal TA4of the integrator61and the input terminal of the operational amplifier OP3included in the integrating circuit61C on the third stage. The differential voltage V4supplied through the input terminal TA4of the integrator61is sampled by the capacitor C25. As a result, the differential voltage V4thus sampled is supplied to the operational amplifier OP3of the integrating circuit61C on the third stage.

An output terminal of the integrating circuit61C (i.e., an output terminal of the operational amplifier OP3) is electrically connected to an output terminal TA5of the integrator61via a switch Q30. That is to say, the output terminal of the integrating circuit61C is connected to the switching circuit62.

The plurality of switches Q21-Q30may be implemented as, for example, semiconductor switches such as CMOS transistors. The switches Q22, Q26are turned ON or OFF in accordance with a control signal φ0supplied from the control unit4. The switches Q21, Q24are turned ON or OFF in accordance with a control signal φ1supplied from the control unit4. The switches Q23, Q25, Q28are turned ON or OFF in accordance with a control signal φ2supplied from the control unit4. The switches Q27, Q29, Q30are turned ON or OFF in accordance with a control signal φ3supplied from the control unit4.

As can be seen, in the example illustrated inFIG.2, the three integrating circuits61A,61B,61C are cascade connected in the integrator61and these integrating circuits61A-61C on three stages perform integration operations sequentially, thereby realizing the noise shaping characteristic for shifting noise in a low-frequency band to a high-frequency band. In the integrator61according to this embodiment, the three integrating circuits61A,61B,61C are cascade connected. However, this is only an example and should not be construed as limiting. Alternatively, the number of stages of the integrating circuits may be changed as appropriate as long as there is at least one stage. In addition, in a situation where the number of stages of the integrating circuits is two or more, the feed forward path does not have to be formed between the input terminal TA4of the integrator61and the one or more integrating circuits to be connected from the second stage and on. The feed forward path may be omitted as appropriate.

The plurality of (e.g., two in this embodiment) capacitors C11, C12are provided in association with the plurality of (e.g., two in this embodiment) analog input voltages V1, V2, respectively. Each of the plurality of capacitors C11, C12has one terminal thereof connected to the reference voltage for the A/D converter1. The switching circuit62includes the plurality of (e.g., two in this embodiment) switches Q11, Q12, which are respectively connected between the other terminals of the plurality of capacitors C11, C12and the output terminal of the integrator61. That is to say, the output terminal of the capacitor C11is connected to the output terminal TA5of the integrator61and an input terminal of the comparator7via the switch Q11. The output terminal of the capacitor C12is connected to the output terminal TA5of the integrator61and the input terminal of the comparator7via the switch Q12. The switches Q11, Q12may be implemented as semiconductor switches such as CMOS transistors. The switches Q11, Q12are turned ON and OFF in accordance with the control signal supplied from the control unit4.

The comparator7compares, on a target bit basis, the voltage supplied from the D/A converting unit5(i.e., the differential voltage V4between the voltage V3to be converted and the output voltage of the D/A converting unit5) with the comparison reference voltage V5supplied via the switching circuit62. The comparator7determines the value (which is either 0 or 1) of the target bit by comparing the differential voltage V4between the voltage V3to be converted and the output voltage of the D/A converting unit5with the comparison reference voltage V5on a target bit basis.

When setting the analog input voltage V1as the voltage V3to be converted, the control unit4turns the switch Q11ON and turns the switch Q12OFF and uses the charge voltage V51for the capacitor C11as the comparison reference voltage V5and supplies the voltage V51to the other input terminal of the comparator7. Thus, when the analog input voltage V1is A/D converted, the result of integration, obtained by having the differential voltage V4, remaining when the least significant bit is converted during the A/D conversion last time, integrated by the integrator61, is used as the comparison reference voltage V5. As a result, the noise shaping characteristic for shifting noise in the low-frequency band to the high-frequency band is realized.

On the other hand, when setting the analog input voltage V2as the voltage V3to be converted, the control unit4turns the switch Q11OFF and turns the switch Q12ON and uses the charge voltage V52for the capacitor C12as the comparison reference voltage V5and supplies the voltage V52to the other input terminal of the comparator7. Thus, when the analog input voltage V2is A/D converted, the result of integration, obtained by having the differential voltage V4, remaining when the least significant bit is converted during the A/D conversion last time, integrated by the integrator61, is used as the comparison reference voltage V5. As a result, the noise shaping characteristic for shifting noise in the low-frequency band to the high-frequency band is realized.

In addition, the control unit4also generates, based on the result of comparison made by the comparator7on the target bit, a control signal S1to make the D/A converting unit5generate a comparative voltage for the bit next to the target bit and outputs the control signal S1to the D/A converting unit5when performing the comparison operation on the next bit.

The serial-parallel converting unit8converts a serial digital signal D11supplied from the A/D converting section3into a parallel digital signal D12and outputs the digital signal D12thus converted to the filter circuit9while A/D converting the voltage V3to be converted.

The filter circuit9attenuates RF components of the digital signal supplied from the A/D converting section3(in this embodiment, the digital signal D12that has been converted into a parallel signal). This filter circuit9includes a plurality of filters (which are abbreviated as “LPF” inFIG.1)91,92and a filter switching circuit93. The plurality of filters91,92are associated with the plurality of analog input voltages V1, V2, respectively. The filter switching circuit93supplies the digital signal D12to one filter, associated with the analog input voltage selected as the voltage V3to be converted, out of the plurality of filters91,92.

Each of the filters91,92is a digital filter having a low-pass filtering characteristic and attenuates RF components included in the digital signal D12. Each of these filters91,92may be a digital filter implemented as a wired logic, for example, but may also be implemented as a processor. The filter switching circuit93connects, in accordance with a control signal S3supplied from the control unit4, an output terminal of the serial-parallel converting unit8to one of the two filters91,92. When the analog input voltage V1is used as the voltage V3to be converted, the control unit4controls the filter switching circuit93such that the digital signal D12is supplied to the filter91associated with the analog input voltage V1. On the other hand, when the analog input voltage V2is used as the voltage V3to be converted, the control unit4controls the filter switching circuit93such that the digital signal D12is supplied to the filter92associated with the analog input voltage V2.

This allows, when the analog input voltage V1is supplied to the A/D converting section3, the digital signal D11output from the A/D converting section3to be converted by the serial-parallel converting unit8into a parallel digital signal D12which is then supplied to the filter91. Then, a digital signal D1, generated by having the RF components included in the digital signal D12attenuated by the filter91, is output from the A/D converter1.

In addition, this also allows, when the analog input voltage V2is supplied to the A/D converting section3, the digital signal D11output from the A/D converting section3to be converted by the serial-parallel converting unit8into a parallel digital signal D12, which is then supplied to the filter92. Then, a digital signal D2, generated by having the RF components included in the digital signal D12attenuated by the filter92, is output from the A/D converter1.

(2.2) Description of Operation

Next, it will be described with reference toFIG.3and other drawings how the A/D converter1according to this embodiment operates.

FIG.3is an exemplary timing chart illustrating how the A/D converter1shown in FIGS.1and2may operate. Note thatFIG.3is a timing chart illustrating the operation of some components of the A/D converter1. Next, it will be described with reference toFIGS.1-3how the A/D converter1operates.

A control signal φA is a control signal for the switch21. A control signal φ3is a control signal for the switch22. Also, control signals φ0, φ1, φ2, φ3are control signals for the switches Q21-Q30included in the integrator61. The control signals φA, φB and φ0-φ3are supplied from the control unit4.

The control unit4A/D converts the two analog input voltages V1, V2time-sequentially by alternately setting a first period TA in which the control unit4A/D converts the analog input voltage V1and a second period TB in which the control unit4A/D converts the analog input voltage V2.

First, it will be described how the A/D converter1operates in the first period TA. During a reset period T1of the first period TA, the control unit4controls the switch Q1to perform a reset operation on the capacitors C1, C2included in the D/A converting unit5. In addition, in the first period TA, the control unit4turns the switch Q11ON and turns the switch Q12OFF and uses the charge voltage V51for the capacitor C11as the comparison reference voltage V5and supplies the voltage V51to the comparator7. Also, in the first period TA, the control unit4switches the filter switching circuit93to allow the digital signal D12to be supplied from the serial-parallel converting unit8to the filter91.

When the reset operation is finished, the control unit4turns the switch21ON and turns the switch22OFF in a sampling period T2, thus causing the D/A converting unit5to be charged with the analog input voltage V1supplied to the input terminal TA1as the voltage V3to be converted. In addition, the control unit4also turns the switch Q11ON and turns the switch Q12OFF, thus having the charge voltage V51for the capacitor C11, corresponding to the analog input voltage V1, supplied as the comparison reference voltage V5to the comparator7. Note that in an initial state where the A/D converter1starts performing the A/D conversion, the value of the charge voltage V51is close to the reference voltage for the A/D converter1.

Thereafter, in an A/D conversion period T3, the control unit4makes the A/D converting section3perform the A/D conversion while turning the switches21,22OFF.

First, the control unit4outputs, to the D/A converting unit5, a control signal S1which generates a comparative voltage ((VH−VL)/2) corresponding to a 12-bit digital value such as “100000000000,” of which only the most significant bit is “1.” At this time, the comparator7determines the value of the most significant bit as the target bit by comparing the differential voltage V4between the voltage V3to be converted (analog input voltage V1) and the comparative voltage with the comparison reference voltage V5.

In this case, if the differential voltage V4is equal to or greater than the comparison reference voltage V5, the comparator7sets the value of the most significant bit (target bit) at “1” for example. On the other hand, if the differential voltage V4is less than the comparison reference voltage V5, the comparator7sets the value of the most significant bit (target bit) at “0,” for example. When determining the value of the bit next to the target bit, the control unit4generates, based on the result of comparison made by the comparator7, a control signal S1that determines the value of the comparative voltage to be generated by the D/A converting unit5and outputs the control signal S1to the D/A converting unit5.

For example, if the value of the most significant bit is “1,” the control unit4outputs a control signal S1, which generates a comparative voltage (3(VH−VL)/4) corresponding to a digital value “110000000000” to the D/A converting unit5when determining the value of the bit next to the most significant bit. At this time, the comparator7determines the value of the target bit by comparing the differential voltage V4between the voltage V3to be converted (analog input voltage V1) and the comparative voltage with the comparison reference voltage V5. When finding the differential voltage V4equal to or greater than the comparison reference voltage V5, the comparator7sets the value of the (MSB−1) bit as the target bit at “1.” On the other hand, when finding the differential voltage V4less than the comparison reference voltage V5, the comparator7sets the value of the (MSB−1) bit as the target bit at “0.”

On the other hand, if the value of the most significant bit is “0,” the control unit4outputs a control signal S1, which generates a comparative voltage ((VH−VL)/4) corresponding to a digital value “010000000000” to the D/A converting unit5when determining the value of the bit next to the most significant bit. At this time, the comparator7determines the value of the target bit by comparing the differential voltage V4between the voltage V3to be converted (analog input voltage V1) and the comparative voltage with the comparison reference voltage V5. When finding the differential voltage V4equal to or greater than the comparison reference voltage V5, the comparator7sets the value of the (MSB−1) bit as the target bit at “1.” On the other hand, when finding the differential voltage V4less than the comparison reference voltage V5, the comparator7sets the value of the (MSB−1) bit as the target bit at “0.”

The values of the respective bits are determined by making the A/D converting section3repeat such an operation from the most significant bit through the least significant bit. The comparison results of respective bits are converted by the serial-parallel converting unit8into a multi-bit parallel digital signal D12, which is output to the filter circuit9. In the filter circuit9, the digital signal D12is supplied by the filter switching circuit93to the filter91, which outputs a digital signal D1with noise in the high-frequency band reduced.

When the A/D converting section3has performed the operation of comparing the target bit through the least significant bit, the control unit4starts performing an operation for an integration period T4. In the integration period T4, the control unit4makes the integrator61perform an integration operation and then performs the operation of generating the comparison reference voltage V5for use when the analog input voltage V1is A/D converted next time.

In the integration period T4, the control unit4first outputs a control signal φ0to turn the switches Q22, Q26OFF to the integrator61, thereby turning the switches Q22, Q26OFF. In this case, the switches Q22, Q26are ON during the A/D conversion period T3. Thus, at the beginning of the integration period T4, the capacitors C22and C24have been charged with the differential voltage V4between the voltage V3to be converted and the comparative voltage at a point in time when the successive approximation processing is finished through the least significant bit.

In the integration period T4, the control unit4outputs a control signal φ1to turn the switches Q21, Q24ON substantially simultaneously with turning the switches Q22, Q26OFF, thereby turning the switches Q21and Q24ON. As a result, the differential voltage V4between the voltage V3to be converted and the comparative voltage at the point in time when the successive approximation processing is finished through the least significant bit is integrated by the integrating circuit61A and the integrated value thus obtained is stored in the capacitor C23.

Next, the control unit4turns the switches Q21and Q24OFF, samples and holds, in the capacitor C23, the integrated value calculated by the integrating circuit61A, and then outputs a control signal φ2to turn the switches Q23, Q25and Q28ON, thereby turning the switches Q23, Q25and Q28ON. As a result, the integrated value sampled and held by the capacitor C23is integrated by the integrating circuit61B on the second stage. In addition, the differential voltage for the least significant bit that has been sampled and held in the capacitor C22is supplied to the integrating circuit61B through the feed forward path FF1and integrated by the integrating circuit61B. At this time, the integrated value calculated by the integrating circuit61B is stored in the capacitor C25.

Next, the control unit4turns the switches Q23, Q25, and Q28OFF, samples and holds, in the capacitor C26, the integrated value calculated by the integrating circuit61B, and then outputs a control signal φ3to turn the switches Q27, Q29and Q30ON, thereby turning the switches Q27, Q29and Q30ON. As a result, the integrated value sampled and held by the capacitor C26is integrated by the integrating circuit61C on the third stage. In addition, the differential voltage for the least significant bit that has been sampled and held in the capacitor C25is supplied to the integrating circuit61C through the feed forward path FF2and integrated by the integrating circuit61C. At this time, the integrated value calculated by the integrating circuit61C is stored in the capacitor C11via the switching circuit62.

Next, the control unit4turns the switches Q27, Q29, and Q30OFF and samples and holds, in the capacitor C11, the integrated value calculated by the integrating circuit61C on the third stage. In this manner, a third-order integration operation is done by the comparison reference voltage generating unit6and the third-order integrated value sampled and held in the capacitor C11is fed back to the comparator7as the comparison reference voltage V5for use when the analog input voltage V1is A/D converted next time. In other words, the result of integration obtained by the integrator61after the analog input voltage V1has been A/D converted last time during the first period TA is set as the comparison reference voltage V5for use when the analog input voltage V1is A/D converted next time during the first period TA. Thus, a successive approximation register A/D converter1having a third-order noise shaping characteristic is provided.

Note that the operation of the A/D converter1during the second period TB is different from its operation during the first period TA in that the analog input voltage V2is subjected as the voltage V3to be converted to A/D conversion. In the sampling period T2of the second period TB, the switch21is turned OFF and the switch22is turned ON to have the analog input voltage V2sampled by the D/A converting unit5. Also, in the integration period T4, the switch Q11is turned OFF and the switch Q12is turned ON to make the capacitor C12integrate the integrated value calculated by the integrator61, and the integrated value sampled and held in the capacitor C12is fed back to the comparator7as the comparison reference voltage V5for use when the analog input voltage V2is A/D converted next time. Meanwhile, the digital signal D12output from the serial-parallel converting unit8is supplied to the filter92via the filter switching circuit93. In response to the digital signal D12received, the filter92outputs a digital signal D2with the noise in the high-frequency band reduced.

In this embodiment, two filters91,92associated with the two analog input voltages V1, V2, respectively, are provided. Then, the filter switching circuit93supplies the digital signal D12to the filter91or92associated with the analog input voltage V1or V2selected as the voltage V3to be converted, thereby reducing the noise in the high-frequency band. As can be seen, a plurality of filters91,92associated with the plurality of analog input voltages V1, V2, respectively, are provided. This achieves the advantage of allowing a plurality of filters91,92associated with the plurality of analog input voltages V1, V2, respectively, to be designed according to the respective frequencies of the analog input voltages V1, V2. Thus, even if the analog input voltages V1, V2have mutually different frequencies, digital signals D1, D2, generated by converting the analog input voltages V1, V2into respective digital values, may still be output.

In this embodiment, each of the plurality of capacitors C11, C12preferably has capacitance which is at least 100 times as large as the quantity of electric charge that would leak via the switch Q11, Q12during the holding period. As used herein, the “holding period” refers to an interval until an associated one of the plurality of analog input voltages V1, V2is A/D converted next time. If an electric charge leaks via the switch Q11, Q12during the holding period, the charge voltage of the capacitor C11, C12varies, thus causing a variation in the comparison reference voltage V5for the next A/D conversion. Thus, each of the plurality of capacitors C11, C12preferably has capacitance which is at least 100 times as large as the quantity of electric charge that would leak via the switch Q11, Q12during the holding period. This may reduce a variation in the charge voltage V51, V52even when an electric charge leaks, thus enabling reducing a variation in the comparison reference voltage V5. Note that each of the plurality of capacitors C11, C12has only to have capacitance which is at least 100 times as large as the quantity of electric charge that would leak via the switch Q11, Q12during the holding period. The upper limit value of the capacitance may be determined by, for example, the size of the capacitor C11, C12.

(3) Variations

Note that the embodiment described above is only an exemplary one of various embodiments of the present disclosure and should not be construed as limiting. Rather, the exemplary embodiment may be readily modified in various manners depending on a design choice or any other factor without departing from the scope of the present disclosure.

Next, variations of the exemplary embodiment will be enumerated one after another. Note that the variations to be described below may be adopted in combination as appropriate.

In the exemplary embodiment described above, the circuit configurations described for the D/A converting unit5, the integrator61, and other components are only examples and may be modified as appropriate.

In the exemplary embodiment described above, the analog input voltages V1, V2to be supplied to the input terminals TA1, TA2are output signals of various types of sensors such as acceleration sensors, angular velocity sensors, gyrosensors, or pressure sensors. However, this is only an example and should not be construed as limiting. Alternatively, the analog input voltages V1, V2may also be voltage signals other than the output signals of such sensors.

In the exemplary embodiment described above, the input switching circuit2may be implemented as, for example, a multiplexor.

In the exemplary embodiment described above, the serial-parallel converting unit8is provided separately from the filter circuit9. However, the serial-parallel converting unit8is not an essential constituent element. Alternatively, the serial-parallel converting unit8may be omitted if the filter circuit9is provided with the function of the serial-parallel converting unit.

Furthermore, in the foregoing description of embodiments, if one of two values being compared with each other (e.g., when the differential voltage is compared with the comparison reference voltage) is “equal to or greater than” the other, this phrase may herein cover both a situation where these two values are equal to each other and a situation where one of the two values is greater than the other. However, this should not be construed as limiting. Alternatively, the phrase “equal to or greater than” may also be a synonym of the phrase “greater than” that covers only a situation where one of the two values is over the other. That is to say, it is arbitrarily changeable, depending on selection of a reference value or any preset value, whether the phrase “equal to or greater than” covers the situation where the two values are equal to each other. Therefore, from a technical point of view, there is no difference between the phrase “equal to or greater than” and the phrase “greater than.” Similarly, the phrase “less than” may be a synonym of the phrase “equal to or less than” as well.

(Recapitulation)

As can be seen from the foregoing description, an A/D converter (1) according to a first aspect includes an input switching circuit (2) and a successive approximation register A/D converting section (3). The input switching circuit (2) receives a plurality of analog input voltages (V1, V2) and outputs, as a voltage (V3) to be converted, one analog input voltage selected from the plurality of analog input voltages (V1, V2). The A/D converting section (3) performs A/D conversion of converting the voltage (V3) to be converted, supplied from the input switching circuit (2), into a multi-bit digital signal (D11). The input switching circuit (2) selects, when a conversion operation of converting the voltage (V3) to be converted has been performed by the A/D converting section (3), another analog input voltage, as the voltage (V3) to be converted, from the plurality of analog input voltages (V1, V2). The A/D converting section (3) performs the conversion operation on a target bit basis from a most significant bit through a least significant bit. The A/D converting section (3) includes a control unit (4), a D/A converting unit (5), a comparison reference voltage generating unit (6), and a comparator (7). The D/A converting unit (5) generates an analog comparative voltage, corresponding to the target bit, in accordance with a control signal (S1) supplied from the control unit (4). The comparison reference voltage generating unit (6) generates a comparison reference voltage (V5) corresponding to the analog input voltage (V1, V2) selected as the voltage (V3) to be converted. The comparator (7) determines a value of the target bit by comparing a differential voltage (V4) between the voltage (V3) to be converted and the comparative voltage with the comparison reference voltage (V5). The control unit (4) determines, based on a result of comparison made by the comparator (7) with respect to the target bit, the control signal (S1) with respect to a bit next to the target bit. The comparison reference voltage generating unit (6) includes an integrator (61), a plurality of capacitors (C11, C12), and a switching circuit (62). The integrator (61) integrates the differential voltage (V4) in a state where the A/D converting section (3) has performed the conversion operation on the least significant bit. The plurality of capacitors (C11, C12) are provided in association with the plurality of analog input voltages (V1, V2), respectively. The switching circuit (62) selectively connects a capacitor (C11, C12), associated with the analog input voltage (V1, V2) selected as the voltage (V3) to be converted, out of the plurality of capacitors (C11, C12) to an output terminal of the integrator (61). The capacitor (C11, C12), connected to the output terminal of the integrator (61) via the switching circuit (62), out of the plurality of capacitors (C11, C12) is charged with an output voltage of the integrator (61). The comparison reference voltage generating unit (6) uses, as the comparison reference voltage (V5), a charge voltage (V51, V52) for the capacitor, associated with the analog input voltage selected as the voltage (V3) to be converted, out of the plurality of capacitors (C11, C12).

According to this aspect, the input switching circuit (2) selects, when a conversion operation of converting the voltage (V3) to be converted has been performed by the A/D converting section (3), another analog input voltage (V1, V2), as the voltage (V3) to be converted, from the plurality of analog input voltages (V1, V2). Thus, the A/D converter (1) may A/D convert the plurality of analog input voltages (V1, V2) time-sequentially. In addition, each of the plurality of capacitors (C11, C12) is charged with the result of integration performed by the integrator (61) in a situation where an associated analog input voltage (V1, V2) is used as the voltage (V3) to be converted. The charge voltage (V51, V52) for the capacitor (C11, C12) is used as the comparison reference voltage (V5) when the associated analog input voltage (V1, V2) is A/D converted next time. Thus, the conversion error may be reduced by using an integrated value of the conversion error involved with the A/D conversion as the comparison reference voltage (V5) for the next A/D conversion. This enables providing an A/D converter (1) with the ability to A/D convert the plurality of analog input voltages (V1, V2) time-sequentially while reducing the conversion error.

In an A/D converter (1) according to a second aspect, which may be implemented in conjunction with the first aspect, each of the plurality of capacitors (C11, C12) has one terminal thereof connected to a reference voltage for the A/D converter (1). The switching circuit (62) includes a plurality of switches (Q11, Q12) respectively connected between the other terminals of the plurality of capacitors (C11, C12) and the output terminal of the integrator (61).

This aspect enables providing an A/D converter (1) with the ability to A/D convert the plurality of analog input voltages (V1, V2) time-sequentially while reducing the conversion error.

In an A/D converter (1) according to a third aspect, which may be implemented in conjunction with the second aspect, each of the plurality of capacitors (C11, C12) has capacitance which is at least 100 times as large as a quantity of electric charge that leaks via an associated one of the switches during a holding period. The holding period refers to an interval until one analog input voltage (V1, V2), associated with the capacitor (C11, C12), out of the plurality of analog input voltages (V1, V2) is A/D converted next time.

This aspect enables reducing a variation, during the holding period, in charge voltages (V51, V52) to be stored in the plurality of capacitors (C11, C12).

An A/D converter (1) according to a fourth aspect, which may be implemented in conjunction with any one of the first to third aspects, includes a filter circuit (9) that attenuates an RF component of the digital signal (D12) supplied from the A/D converting section (3). The filter circuit (9) includes: a plurality of filters (91,92) respectively associated with the plurality of analog input voltages (V1, V2); and a filter switching circuit (93). The filter switching circuit (93) supplies the digital signal (D12) to one filter (91,92), associated with the analog input voltage (V1, V2) selected as the voltage (V3) to be converted, out of the plurality of filters (91,92).

This aspect achieves the advantage of allowing a plurality of filters (91,92), respectively associated with the plurality of analog input voltages (V1, V2), to be designed according to the respective frequencies of the plurality of analog input voltages (V1, V2).

In an A/D converter (1) according to a fifth aspect, which may be implemented in conjunction with any one of the first to fourth aspects, the D/A converting unit (5) includes a plurality of capacitors (C1, C2) and a voltage switching circuit (55). Each of the plurality of capacitors (C11, C12) has one terminal thereof connected to an output terminal of the input switching circuit (2). The voltage switching circuit (55) selectively connects, in accordance with the control signal (S1), the other terminal of each of the plurality of capacitors (C1, C2) to either a first voltage (VH) or a second voltage (VL).

This aspect achieves the advantage of allowing the D/A converting unit (5) to be implemented as a simple circuit.

In an A/D converter (1) according to a sixth aspect, which may be implemented in conjunction with any one of the first to fifth aspects, the integrator (61) includes multiple stages of integrating circuits (61A-61C) that perform integration operations sequentially. Each of the multiple stages of the integrating circuits (61A-61C) performs the integration operation using an operational amplifier (OP1-OP3).

This aspect realizes a noise shaping characteristic for shifting noise in a low-frequency band to a high-frequency band by performing integration operations in multiple stages using the multiple stages of integrating circuits (61A-61C).

Note that these are not the only aspects of the present disclosure but various configurations (including their variations) of the control unit (4) included in the A/D converter (1) according to the exemplary embodiment described above may also be implemented as, for example, a method for controlling the control unit (4), a (computer) program, or a non-transitory storage medium on which the program is stored.

Note that the constituent elements according to the second to sixth aspects are not essential constituent elements for the A/D converter (1) but may be omitted as appropriate.

REFERENCE SIGNS LIST

1A/D Converter2Input Switching Circuit3A/D Converting Section5D/A Converting Unit6Comparison Reference Voltage Generating Unit7Comparator9Filter Circuit55Voltage Switching Circuit61Integrator62Switching Circuit91,92Filter93Filter Switching CircuitC1, C2CapacitorC11, C12CapacitorD11Digital SignalOP1-OP3Operational AmplifierQ11, Q12SwitchS1Control SignalV1, V2Analog Input VoltageV3Voltage to Be ConvertedV4Differential VoltageV5Comparison Reference VoltageVH First VoltageVL Second Voltage