Patent ID: 12249636

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a feature on, connected to, and/or coupled to another feature in the present disclosure that follows may include embodiments in which the features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the features, such that the features may not be in direct contact. In addition, spatially relative terms, for example, “lower,” “upper,” “horizontal,” “vertical,” “above,” “over,” “below,” “beneath,” “up,” “down,” “top,” “bottom,” etc. as well as derivatives thereof (e.g., “horizontally,” “downwardly,” “upwardly,” etc.) are used for ease of the present disclosure of one features relationship to another feature. The spatially relative terms are intended to cover different orientations of the device including the features.

Furthermore, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range including the number described, such as within +/−10% of the number described or other values as understood by person skilled in the art. For example, the term “about 5 nm” encompasses the dimension range from 4.5 nm to 5.5 nm. Still further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

The present disclosure is generally related to semiconductor devices, and more particularly to field-effect transistors (FETs), such as three-dimensional, multi-gate nanostructure (NS) FETs (alternatively referred to as gate-all-around, or GAA, FETs), in memory and/or standard logic cells of an integrated circuit (IC) structure. Generally, NS FETs are configured with a plurality of vertically stacked sheets (e.g., nanosheets), wires (e.g., nanowires), or rods (e.g., nanorods) as channel regions engaged with a metal gate stack, thereby allowing better gate control, lowered leakage current, and improved scaling capability for various IC applications. The present disclosure includes multiple embodiments. Different embodiments may have different advantages, and no particular advantage is necessarily required of any embodiment.

An NS FET may generally include a stack of channel layers (such as Si layers) disposed over an active region (e.g., a fin), source/drain (S/D) features formed over or in the active region, and a metal gate stack interleaved with the stack of channel layers and interposed between the S/D features. With rising demand for portable applications, devices with high speed and low power consumption become more crucial at reduced length scales. Existing GAA FETs generally have a one-sized gate length. While such devices have been generally adequate, they have not been entirely satisfactory in all aspects. For example, designing devices with tunable gate lengths may provide more flexibility in optimizing performance of memory cells (such as static random access memory, or SRAM, cells).

Referring now toFIGS.1A,1B, and1Ccollectively, a flowchart of a method100of forming a semiconductor structure200(hereafter simply referred to as the structure200) is illustrated according to various aspects of the present disclosure. Method100is merely an example and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, and after method100and some operations described can be replaced, eliminated, or moved around for additional embodiments of the method. Method100is described below in conjunction withFIGS.2A-18D, which are various cross-sectional and top planar views of the structure200at intermediate steps of method100. For examples,FIGS.2A-2C and10A-10Care planar top views of a portion of the structure200;FIGS.3A,4A,5A,6A,7A,8A, and9Aare cross-sectional views of the structure200taken along line AA′ as shown inFIG.2A,2B, or2C;FIGS.3B,4B,5B,6B,7B,8B, and9Bare cross-sectional views of the structure200taken along line BB′ as shown inFIG.2A,2B, or2C;FIGS.3C,4C,5C,6C,7C,8C, and9Care cross-sectional views of the structure200taken along line CC′ as shown inFIG.2A,2B, or2C;FIGS.10D,12A,13A,14A,15A,16A,17A, and18Aare cross-sectional views of the structure200taken along line AA′ as shown inFIG.10A,10B, or10C;FIGS.10E,12B,13B,14B,15B,16B,17B, and18Bare cross-sectional views of the structure200taken along line BB′ as shown inFIG.10A,10B, or10C;FIGS.10F,11A,12C,13C,14C,15C,16C,17C, and18Care cross-sectional views of the structure200taken along line DD′ inFIG.10A,10B, or10C; andFIGS.10G,11B,12D,13D,14D,15D,16D,17D, and18Dare cross-sectional views of the structure200taken along line EE′ inFIG.10A,10B, or10C. In the present embodiments, lines DD′ and EE′ are each taken through an S/D region of a device included in the structure200.

The structure200may be an intermediate device fabricated during processing of an IC, or a portion thereof, that may comprise static random-access memory (SRAM) and/or other logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as NS FETs, FinFETs, metal-oxide semiconductor field effect transistors (MOSFETs), complementary metal-oxide semiconductor (CMOS) transistors, bipolar transistors, high voltage transistors, high frequency transistors, and/or other transistors. In the present embodiments, the structure200includes one or more NS FETs. The present disclosure is not limited to any particular number of devices or device regions, or to any particular device configurations. Additional features can be added to the structure200, and some of the features described below can be replaced, modified, or eliminated in other embodiments of the structure200.

At operation102, referring toFIGS.1A,2A-2C, and3A-3C, method100provides a substrate202and forms a SiGe-containing layer (or SiGe layer)205over a region202aand a region202bof the substrate202. In some embodiments, referring toFIGS.2A-2C, the regions202aand202bare disposed immediately adjacent to each other. In some embodiments, the regions202aand202bare separated by other region(s) of the substrate202. For embodiments in which layout areas of memory and/or logic cells are limited, separation between the regions202aand202bis minimized. In some examples, referring toFIG.2A, the regions202aand202bmay be arranged adjacent to each other along the Y axis; in some examples, referring toFIG.2B, the regions202aand202bmay be arranged adjacent to each other along the X axis; and in further examples, referring toFIG.2C, the region202amay be disposed adjacent to the region202balong both the X axis and the Y axis. The present disclosure does not limit the arrangement of the regions202aand202bto any particular example(s) depicted herein.

The substrate202may include an elemental (single element) semiconductor, such as silicon (Si), germanium (Ge), and/or other suitable materials; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and/or other suitable materials; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and/or other suitable materials. The substrate202may be a single-layer material having a uniform composition. Alternatively, the substrate202may include multiple material layers having similar or different compositions suitable for IC device manufacturing.

In the depicted embodiments, the SiGe layer205is a bottommost layer of a multi-layer structure (ML) in the region202b. In the present embodiments, forming the SiGe layer205includes performing an epitaxy process. The epitaxy process may be implemented by chemical vapor deposition (CVD) techniques (for example, vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), low-pressure (LP-CVD), and/or plasma-enhanced CVD (PE-CVD)), molecular beam epitaxy, other suitable selective epitaxial growth (SEG) processes, or combinations thereof. The epitaxy process may use gaseous and/or liquid precursors containing a suitable material (e.g., Ge), which interacts with the composition of the underlying substrate, e.g., the substrate202. In the present embodiments, the SiGe layer205includes about 20% to about 22% of Ge. In some examples, the SiGe layer205(and the additional layers of the ML) may be formed into nanosheets, nanowires, or nanorods.

At operation104, referring toFIGS.1A,1C, and4A-8C, method100replaces a portion of the SiGe layer205in the region202awith a different SiGe layer207, while a portion of the SiGe layer205remains in the region202b. In other words, method100removes the portion of the SiGe layer205from the region202aand subsequently forms the SiGe layer207having a different composition from that of the SiGe layer205. In the present embodiments, referring toFIG.1C, operation104may be implemented via Pathway A, which includes sub-operation150, or Pathway B, which includes sub-operations160-164.

In some embodiments, referring to Pathway A ofFIG.1Cand toFIGS.4A-4C, method100at sub-operation150selectively performs an implantation process (e.g., an ion implantation process)302to the region202awith respect to the region202b. Method100first forms a patterned masking element209aover the region202bto expose the region202a. The patterned masking element209amay be formed by a series of photolithography and etching processes. The patterned masking element209amay be a tri-layer structure that includes a photoresist layer, a middle layer (containing a metal, a polymer, and/or other suitable materials), a bottom anti-reflective coating (BARC) layer. Forming the patterned masking element209amay include exposing the photoresist layer, developing the photoresist layer, and etching the remainder of the masking element using the patterned photoresist layer as an etch mask.

Subsequently, method100performs the implantation process302to the region202aexposed by the patterned masking element209a. The implantation process302is configured to introduce Ge to the exposed portion of the SiGe layer205, thereby forming the SiGe layer207that includes a greater amount of Ge than the SiGe layer205. In other words, the implantation process302dopes Ge into the portion of the SiGe layer205in the region202a, while the portion of the SiGe layer205under the patterned masking element209ain the region202bremains un-doped. In the present embodiments, the resulting concentration of Ge in the SiGe layer207is about 23% to about 25%. After performing the implantation process302, referring toFIGS.8A-8C, the patterned masking element209ais removed from the structure200by a suitable method, such as plasma ashing and/or resist stripping.

In some embodiments, the implantation process302is implemented with a beam energy of about 20 keV to about 160 keV, and an ion dosage of about 1×1015ion/cm2to about 5×1016ions/cm2. The present embodiments are not limited to these implantation conditions.

In some embodiments, referring to Pathway B ofFIG.1Cand toFIGS.5A-5C, method100at sub-operation160selectively removes the portion of the SiGe layer205from the region202ato expose the underlying substrate202in an etching process304. Method100first forms a patterned masking element209bover the region202bto expose the region202a. The patterned masking element209bmay be substantially similar to the patterned masking element209a. Subsequently, method100performs the etching process304to remove the exposed portion of the SiGe layer205. The etching process304may be a dry etching process, a wet etching process, a reactive ion etching (RIE) process, other suitable processes, or combinations thereof. In the present embodiments, the etching process304selectively removes the SiGe layer205without removing, or substantially removing, the underlying substrate202in the region202a. After removing the portion of the SiGe layer205, the patterned masking element209bis removed from the structure200by plasma ashing and/or resist stripping.

Referring toFIGS.6A-6C, method100at sub-operation162deposits the SiGe layer207over the etched SiGe layer205in a deposition process306, such that the SiGe layer207directly contacts the SiGe layer205and the substrate202in the regions202band202a, respectively. The deposition process306may be an epitaxial growth process similar to that discussed above with respect to forming the SiGe layer205, resulting in an epitaxial crystalline SiGe layer207. Alternatively, the deposition process306may be a conformal deposition process implemented by a method such as CVD, atomic layer deposition (ALD), and/or other suitable methods to form an amorphous SiGe layer207. In the present embodiments, the deposition process306is controlled such that the SiGe layer207is formed to a thickness T2that is substantially similar to or the same as a thickness T1of the SiGe layer205, ensuring the uniformity of the subsequently-formed layers of the ML.

Subsequently, referring toFIGS.7A-7C, method100at sub-operation164selectively removes a portion of the SiGe layer207in the region202bin an etching process308, leaving behind a portion of the SiGe layer207in the region202a. Method100first forms a patterned masking element209cover the region202ato expose the region202b. The patterned masking element209cmay be substantially similar to the patterned masking element209a. Subsequently, method100performs the etching process308to remove the exposed portion of the SiGe layer207. The etching process308may be a dry etching process, a wet etching process, an RIE process, other suitable processes, or combinations thereof. In the present embodiments, the etching process308selectively removes the SiGe layer207without removing, or substantially removing, the underlying SiGe layer205in the region202b. After removing the portion of the SiGe layer207, referring toFIGS.8A-8C, the patterned masking element209cis removed from the structure200by plasma ashing and/or resist stripping.

At operation106, referring toFIGS.1A and9A-9C, method100completes the formation of an ML1 over the SiGe layers207in the region202aand an ML2 over the SiGe layer205in the region202b. Each ML further includes a stack of alternating Si-containing layers (or Si layers)206and SiGe layers207formed over the regions202aand202b. In the present embodiments, the Si layers206are free, or substantially free, of any Ge. The SiGe layers205and207in each ML are sacrificial layers configured to be removed subsequently, thereby providing openings between the Si layers206for forming a metal gate stack. Accordingly, the SiGe layers205and207may be collectively referred to as the non-channel layers and the Si layers206are referred to as the channel layers of each ML. In the present embodiments, forming the remainder of each ML includes alternatingly growing the Si layers206and the SiGe layers207in a series of epitaxy processes as discussed in detail above with respect to forming the SiGe layer205.

In the present embodiments, method100at operation106further forms a hard mask layer208over each ML, a Si layer210over the hard mask layer208, and hard mask layers211and212over the Si layer210. The hard mask layer208is a sacrificial layer configured to facilitate the formation of isolation features between the subsequently-formed active regions (e.g., fins). In some embodiments, the hard mask layer208may be formed to a thickness T3that is greater than the thickness T1or T2as defined above. The hard mask layer208may include any suitable material, such as a semiconductor material, so long as its composition is distinct from that of the isolation features and the Si layer206disposed thereunder to allow selective removal by an etching process. In some embodiments, the hard mask layer208has a composition similar to or the same as that of the SiGe layers207. For embodiments in which the hard mask layer208has the same composition as the SiGe layers207, the hard mask layer208may also be grown by an epitaxy process as discussed above.

The Si layer210acts as a buffer to facilitate the growth of the hard mask layer211, which may include an oxide material. In some embodiments the Si layer210is formed to a thickness T4that is less than the thickness T1or T2as defined above. In some examples, the thickness T4may be about 1 nm. The hard mask layers211and212are configured to protect the underlying hard mask layer208and the ML during subsequent fabrication processes and may each include any suitable dielectric material, such as silicon oxide (SiO and/or SiO2), silicon nitride (SiN), silicon carbide (SiC), oxygen-containing silicon nitride (SiON), oxygen-containing silicon carbide (SiOC), carbon-containing silicon nitride (SiCN), aluminum oxide (Al2O3), other suitable materials, or combinations thereof. In the present embodiments, the hard mask layers211and212include different dielectric materials. In one such example, the hard mask layer211may include silicon oxide and the hard mask layer212may include silicon nitride. The hard mask layers211and212may be formed by any suitable method, such as CVD, ALD, PVD, other suitable methods, or combinations thereof.

At operation108, referring toFIGS.1A and10A-10G, method100forms an active region protruding from the region202a(i.e., in the ML1) and an active region protruding from the region202b(i.e., in the ML2). In some embodiments, referring toFIG.10A, which corresponds to the example embodiment shown inFIG.2A, method100forms active regions204aand204bas fins each arranged lengthwise along the X axis and separated from each other along the Y axis. In some embodiments, referring toFIG.10B, which corresponds to the example embodiment shown inFIG.2B, the active regions204aand204bare portions of the same fin disposed adjacent to each other along the X axis (i.e., the lengthwise direction of the fin). In some embodiments, referring toFIG.10C, which corresponds to the example embodiment shown inFIG.2C, method100forms an additional active region204c(i.e., in the ML1) in the region202a, where the active regions204aand204bare arranged adjacent to each other along the X axis as portions of a first fin and the active region204cis a portion of a second fin separated from the first fin along the Y axis. In the present embodiments, the active regions204a-204care each configured to provide an NS FET. In one such example, each NS FET provided by the active regions204a-204cmay be a portion of an SRAM cell. While embodiments depicted inFIGS.10A,10B, and10Care equally applicable in the present disclosure, subsequent operations of method100are discussed in the context of the active regions204aand204bfor purposes of simplicity.

Method100forms the active regions204aand204busing a series of photolithography and etching processes similar to those discussed above with respect to forming the patterned masking element209a. For example, the photolithography process may include forming a masking element over each ML, exposing the masking element, and developing the exposed masking element to form a patterned masking element (not depicted). The hard mask layer212is then etched using the patterned masking element as an etch mask, followed by the etching of the hard mask layer211, the Si layer210, the hard mask layer208, and the ML1 and ML2 to form the active regions204aand204b, respectively. The etching process may include dry etching, wet etching, RIE, other suitable processes, or combinations thereof. The patterned masking element is subsequently removed using any suitable process, such as ashing and/or resist stripping.

Numerous other embodiments of methods to form the active regions204aand204bmay be suitable. For example, the active regions204aand204bmay be patterned using double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate202and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the active regions204aand204b.

Still referring toFIGS.10F and10G, method100at operation108subsequently forms isolation structures214in a trench adjacent to the active regions204aand204b. The isolation structures214may include SiO and/or SiO2, tetraethylorthosilicate (TEOS), doped silicon oxide (borophosphosilicate glass (BPSG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), etc.), a low-k dielectric material (having a dielectric constant less than that of silicon oxide, which is about 3.9), other suitable materials, or combinations thereof. The isolation structures214may include shallow trench isolation (STI) features. In one embodiment, the isolation structures214are formed by filling the trench adjacent to the active regions204aand204bwith a dielectric material described above by any suitable method, such as CVD, flowable CVD (FCVD), spin-on-glass (SOG), other suitable methods, or combinations thereof. The dielectric material may subsequently be planarized by a chemical-mechanical planarization/polishing (CMP) process and etched back to form the isolation structures214. The isolation structures214may include a single-layer structure or a multi-layer structure. In some embodiments, the CMP process also removes the hard mask layers211and212and the Si layer210from the structure200. In some embodiments, the hard mask layers211and212and the Si layer210are removed separately by one or more etching processes after forming the isolation structures214.

At operation110, referring toFIGS.1A and11A-11B, method100forms a cladding layer213over the active regions204aand204band the isolation structures214. In the present embodiments, the cladding layer213and the SiGe layers205and207are sacrificial layers configured to be replaced with a metal gate stack in a channel region of each active region204aand204b. In the present embodiments, the cladding layer213includes SiGe. In some embodiments, the cladding layer213is deposited epitaxially by a suitable method discussed above with respect to forming the SiGe layer205. In some embodiments, the cladding layer213is deposited conformally, rather than grown epitaxially, over surfaces of the structure200as an amorphous layer, such that the cladding layer213is also formed over the isolation structures214. Subsequently, method100performs a directional (or anisotropic) etching process to selectively remove portions of the cladding layer213, thereby exposing portions of the isolation structures214and a top surface of the Si layer210. The etching process may include a dry etching process, a wet etching process, an RIE process, or combinations thereof. The etching process may implement an etchant that selectively removes horizontal portions of the cladding layer213without removing, or substantially removing the isolation structures214or vertical portions of the cladding layer213.

At operation112, referring toFIGS.1A and12A-12D, method100forms a dielectric helmet232adjacent to each active region204aand204b. In the present embodiments, referring toFIGS.12C and12D, forming the dielectric helmet232includes first forming a dielectric layer230over the structure200, thereby completely filling the trench adjacent to the active regions204aand204b. The dielectric layer230is configured to isolate the active regions204aand204band to provide a substrate over which gate isolation features may be subsequently formed. The dielectric layer230may include a single-layered structure or a multi-layered structure. The dielectric layer230may include any suitable dielectric material, such as SiO and/or SiO2, SiN, SiC, SiON, SiOC, SiCN, TEOS, doped silicon oxide (e.g., BPSG, FSG, PSG, BSG, etc.), other suitable materials, or combinations thereof. The dielectric layer230may be deposited by any suitable method, such as CVD, FCVD, SOG, other suitable methods, or combinations thereof, and subsequently planarized by one or more CMP process to expose a top surface of the hard mask layer208. As depicted herein, the dielectric layer230is separated from each sidewall of the active regions204aand204bby the cladding layer213.

Subsequently, still referring toFIGS.12A-12D, method100forms the dielectric helmet232over the dielectric layer230. In some embodiments, the dielectric helmet232provides one or more gate isolation features configured to separate (or cut) a subsequently-formed metal gate stack over the active regions204aand204b. In the present embodiments, for purposes of enhancing etching selectivity, the dielectric helmet232is configured with a composition different from that of the dielectric layer230, and may include silicon oxide, SiN, SiC, SiON, SiOC, SiCN, Al2O3, a high-k dielectric material (e.g., hafnium oxide (HfO2), lanthanum oxide (La2O3), etc.), other suitable materials, or combinations thereof. In some embodiments, the dielectric helmet232includes a dielectric material having a higher dielectric constant than the dielectric layer230. For example, the dielectric helmet232may include a high-k dielectric material, such as HfO2, and the dielectric layer230may include silicon oxide. In some embodiments, method100forms the dielectric helmet232by first recessing the dielectric layer230to form trenches (not depicted), depositing a dielectric material in the trenches by a suitable method, such as CVD and/or ALD, and planarizing the dielectric material by a CMP process to form the dielectric helmet232.

At operation114, still referring toFIGS.12A-12D, method100forms dummy gate stacks220over channel regions of the active regions204aand204b. In the present embodiments, referring toFIGS.12C and12D, method100first removes the hard mask layer208to form trenches219, thereby exposing the topmost Si layer206of each ML. In the present embodiments, method100selectively removes the hard mask layer208without removing, or substantially removing, the dielectric helmet232or the topmost Si layer206of each ML. Subsequently, referring toFIGS.12A and12B, method100forms the dummy gate stacks220over channel regions of the active regions204aand204b, thereby filling the trenches219. Each dummy gate stack220may include a dummy gate electrode222disposed over an optional dummy gate dielectric layer (not depicted) and an interfacial layer221. In some embodiments, at least portions of each dummy gate stack220are to be replaced with a metal gate stack, which may be separated (or cut) by the dielectric helmet232.

The dummy gate stacks220may be formed by a series of deposition and patterning processes. For example, the dummy gate stacks220may be formed by depositing a polysilicon (poly-Si) layer over the active regions204aand204bseparated by the dielectric helmet232, and subsequently patterning the poly-Si layer via a series of photolithography and etching processes (e.g., an anisotropic dry etching process). The interfacial layer221may include silicon oxide and may be formed by any suitable method, such as thermal oxidation, chemical oxidation, other suitable methods, or combinations thereof.

Still referring toFIGS.12A-12D, method100at operation114subsequently forms top gate spacers224on sidewalls of the dummy gate stacks220. The top gate spacers224may be a single-layer structure or a multi-layer structure and may include silicon oxide, SiN, SiC, SiON, SiOC, SiCN, air, a low-k dielectric material, a high-k dielectric material (e.g., HfO2, La2O3, etc.), other suitable materials, or combinations thereof. In the present embodiments, the top gate spacers224includes a spacer layer224bdisposed over a spacer layer224a. Each spacer layer of the top gate spacers224may be formed by depositing the spacer layers224aand224bover the dummy gate stacks220via a suitable deposition method, such as CVD and/or ALD. In some embodiments, method100performs an anisotropic (or directional) etching process to remove portions of the dielectric layer, leaving the top gate spacers224on the sidewalls of the dummy gate stacks220. In some embodiments, as depicted herein, the anisotropic etching is performed at a later processing step.

At operation116, referring toFIGS.1B and13A-13D, method100forms S/D recesses240and242in the regions202aand202b, respectively, in an etching process310. In the present embodiments, method100removes portions of the active regions204aand204bas well as portions of the cladding layer213without removing, or substantially removing, the dummy gate stacks220, the dielectric layer230, the dielectric helmet232, and the isolation structures214. In some embodiments, the etching process310employs a suitable etchant capable of removing the Si layers206, the SiGe layers205, and the SiGe layers207. In some embodiments, the etching process310is a dry etching process implemented with radio-frequency (RF) pulsing using a suitable etchant such as a fluorine-containing gas (e.g., CHF3, CF4, CH3F, CH2F2, C4F8, C4F6, other fluorine-containing gases, or combinations thereof), a bromine-containing gas (e.g., HBr), an inert gas, other suitable gases, or combinations thereof. A cleaning process may subsequently be performed to remove any etching by-products from the S/D recesses240and242.

At operation118, referring toFIGS.1B and14A-14D, method100removes portions of the SiGe layers205and207exposed in the S/D recesses240and242in an etching process312. In the present embodiments, the etching process312is configured to selectively etch the SiGe layers without etching, or substantially etching, the Si layers206exposed in the S/D recesses240and242. In other words, the etching process312removes the Ge-containing layers at a higher rate than those without any Ge content. As depicted herein, the etching process312results in trenches244aformed in the SiGe layers207and trenches244bin the SiGe layer205, which includes less Ge than the SiGe layers207.

In the present embodiments, the etching process312includes a dry etching process followed by a wet etching process. In some embodiments, the dry etching process is implemented with RF pulsing using a suitable etchant such as a fluorine-containing gas (e.g., CHF3, CF4, CH3F, CH2F2, C4F8, C4F6, other fluorine-containing gases, or combinations thereof), a bromine-containing gas (e.g., HBr), an inert gas, other suitable gases, or combinations thereof. In some embodiments, the wet etching process is implemented with diluted hydrofluoric acid (e.g., dHF), hydrogen peroxide (H2O2), ammonium hydroxide (NH4OH), hydrochloric acid (HCl), other suitable wet etchants, or combinations thereof. In some examples, the wet etchant may be a standard cleaning solution-1 (or SC-1), which includes H2O2, NH4OH, and water, and/or a standard cleaning solution-2 (or SC-2), which includes H2O2, HCl, and water.

In the present embodiments, the selectivity of the etching process312toward Ge increases with increasing Ge content. In other words, because the SiGe layer205includes less Ge than the SiGe layers207, the extent of etching in the SiGe layer205is less than that in the SiGe layer207, resulting in a width W1of the trenches244abeing greater than a width W2of the trenches244b. Accordingly, a length L1of a remaining portion of each SiGe layer207is less than a length L2of a remaining portion of the SiGe layer205. As will be discussed in detail below, the widths W1and W2each corresponds to a thickness of an inner gate spacer formed between the metal gate stack and a S/D feature, and the lengths L1and L2each correspond to a gate length of the metal gate stack formed between the Si layers206within each ML. In this regard, the metal gate stack formed in the ML1 is defined by a uniform gate length, the length L1, between the Si layers206, and the metal gate stack formed in the ML2 is defined by a relatively longer gate length, the length L2, between the substrate202and the bottommost Si layer206, as well as by the length L1between the remainder of the Si layers206over the bottommost Si layer206. In some embodiments, a ratio of the gate length L2to the gate length L1is about 1.1 to about 1.6. In some examples, the gate length L1may be about 10 nm to about 18 nm, the gate length L2may be about 12 nm to about 20 nm, and the difference between them may be about 2 nm to about 6 nm.

Generally, nanosheet-based devices are formed with uniform gate length along a stacking direction of the ML. However, it may be beneficial for devices with different functions to have varying gate lengths, such that different aspects of device performance may be tuned or optimized for improvement. For example, in an SRAM cell, it may be desirable for pass-gate (PG) devices to have relatively longer gate length to reduce leakage associated with drain-induced barrier lowering (DIBL) effect, improve gate control, and increase threshold voltage, which leads to reduced current (Ion, PG) relative to pull-down (PD) and/or pull-up (PU) devices for enhanced performance in the memory device. The present disclosure is directed to NS FETs with varying gate lengths to allow functions of various devices formed on the same substrate to be tuned and optimized separately.

In the present embodiments, the ML1 provides devices having a uniform gate length and the ML2 provides devices with varying gate lengths, where the gate length L2of the bottommost device is longer than the gate length L1of the devices disposed thereover. In the present embodiments, the longer gate length L2is provided in at least the bottommost device to improve gate control and reduce leakage issues. In some examples, the long gate length L2may be additionally provided in at least one of the devices disposed thereover. In the present embodiments, a difference between the gate lengths L1and L2is achieved by adjusting the difference in the amount of Ge between the SiGe layers205and207. In some embodiments, the amount of Ge in the SiGe layer207is greater than that in the SiGe layer205by about 1% to about 5%, where the difference of less than about 1% may not be sufficient to provide etching selectivity between the SiGe layers205and207and the difference of greater than about 5% may result in the trenches244bto be too narrow to accommodate subsequent formation of the inner gate spacers. It is noted, however, that such difference may be greater than about 5%, so long as the resulting width W2of the trenches244bis large enough for forming the inner gate spacers to a desired thickness. In some embodiments, the amount of Ge in the SiGe layers207does not exceed about 50%. In some instances, if the amount of Ge in the SiGe layers207exceeds about 50%, structural defects may be introduced during the epitaxial growth of the SiGe layers207, while an amount of Ge in the SiGe layers207that is less than about 23% may not present sufficient etching selectivity with respect to the SiGe layer205as discussed in detail above.

At operation120, referring toFIGS.1B and15A-16D, method100forms inner gate spacers248aon sidewalls of the recessed SiGe layers207and inner gate spacers248bon sidewalls of the recessed SiGe layer205. The inner gate spacers248aand248bmay each be a single-layer structure or a multi-layer structure and may include silicon oxide, SiN, SiCN, SiOC, SiON, SiOCN, a low-k dielectric material, air, a high-k dielectric material (e.g., HfO2, La2O3, etc.), other suitable dielectric material, or combination thereof. In some embodiments, the inner gate spacers248aand248bdiffer from the top gate spacers224in composition. In the present embodiments, the inner gate spacers248aand248bhave the same compositions but differ in dimensions.

Forming the inner gate spacers248aand248bincludes performing a series of deposition and etching processes. Referring toFIGS.15A-15D, method100deposits one or more dielectric layers246along sidewalls of the S/D recesses240and242, as well as the exposed sidewalls of the top gate spacers224, thereby filling the trenches244aand244b. Subsequently, referring toFIGS.16A-16D, method100removes (i.e., etches back) excess dielectric layer(s) deposited on surfaces of the Si layers206and the top gate spacers224, thereby forming the inner gate spacers248aand248b. The one or more dielectric layers246may be deposited by any suitable method, such as ALD, CVD, physical vapor deposition (PVD), other suitable methods, or combinations thereof.

Accordingly, the inner gate spacers248aare defined by the width W1and the inner gate spacers248bare defined by the width W2. As discussed in detail above, the difference in the widths W1and W2is attributed to the etching selectivity between the SiGe layers205and207. In the present embodiments, the width W2is at least about 1 nm to maintain a thickness of the inner gate spacers248bcapable of providing sufficient insulation between the subsequently-formed metal gate stack and the S/D feature. In some examples, the width W1may be about 3 nm to about 6 nm, the width W2may be about 1 nm to about 5 nm, and the difference between them may be about 1 nm to about 3 nm.

At operation122, referring toFIGS.1B and17A-17D, method100forms S/D features250and252in the S/D recesses240and242, respectively. Each of the S/D features250and252may be suitable for forming a p-type FET (i.e., including a p-type epitaxial material) or, alternatively, an n-type FET (i.e., including an n-type epitaxial material). The p-type epitaxial material may include one or more epitaxial layers of silicon germanium (epi SiGe) each doped with a p-type dopant such as B, BF2, other p-type dopants, or combinations thereof. The n-type epitaxial material may include one or more epitaxial layers of silicon (epi Si) or silicon carbon (epi SiC) each doped with an n-type dopant such as As, P, other n-type dopants, or combinations thereof.

In the present embodiments, forming the S/D features250and252includes growing an epitaxial semiconductor material in each of the S/D recess240and242and over the inner gate spacers248aand248bin a process similar to that discussed above with respect to forming the SiGe layer205. In some embodiments, the epitaxial semiconductor material is doped in-situ by adding a dopant species discussed above to a source material during the epitaxial growth process. In some embodiments, the epitaxial semiconductor material is doped by an ion implantation process after performing the deposition process. In some embodiments, an annealing process is performed to activate the dopant species in the S/D features250and252. In some embodiments, each of the S/D features250and252includes one doped epitaxial semiconductor material. In some embodiments, each of the S/D features250and252includes multiple doped epitaxial semiconductor materials that differ in the amount of dopant present.

At operation124, referring toFIGS.1B and18A-18D, method100forms metal gate stacks in place of the dummy gate stacks220(and the interfacial layer221), the SiGe layer205, and the SiGe layers207. In the present embodiments, method100forms a metal gate stack260over the region202aand a metal gate stack262over the region202b, such that the metal gate stack260engages with the active region204ato form an NS FET300and the metal gate stack262engages with the active region204bto form an NS FET400. In some embodiments, the NS FETs300and400are devices of the same conductivity type, i.e., both are NFETs; though they may be configured as different devices in a memory cell (e.g., an SRAM cell). In some embodiments, the NS FETs300and400are devices of different conductivity types, i.e., one is an NFET and the other one is a PFET.

Method100first forms an etch-stop layer (ESL)256over the structure200to protect the underlying components, such as the S/D features250and252, during subsequent fabrication processes. The ESL256may include any suitable dielectric material, such as SiN, SiCN, SiON, Al2O3, other suitable materials, or combinations thereof, and may be formed by CVD, ALD, PVD, other suitable methods, or combinations thereof. In the present embodiments, the ESL256provides etching selectivity with respect to its surrounding dielectric components to ensure protection against inadvertent damage.

Subsequently, method100forms an interlayer dielectric (ILD) layer258over the ESL256, thereby filling the space between adjacent dummy gate stacks220. The ILD layer258may include silicon oxide, a low-k dielectric material, TEOS, a doped silicon oxide (e.g., BPSG, FSG, PSG, BSG, etc.), other suitable dielectric materials, or combinations thereof, and may be formed by any suitable method, such as CVD, FCVD, SOG, other suitable methods, or combinations thereof. Method100subsequently performs one or more CMP process to expose top surfaces of the dummy gate stacks220.

Method100then removes the dummy gate stacks220from the structure200to form gate trenches (not depicted) in an etching process. In the present embodiments, method100selectively removes the dummy gate stacks220(including the interfacial layer221) without removing, or substantially removing, the Si layers206and the surrounding dielectric components. The etching process may include any suitable process, such as a dry etching process, a wet etching process, an RIE, or combinations thereof.

In some embodiments, though not depicted herein, method100optionally patterns the dielectric helmet232remaining over the channel regions of the active regions204aand204bto form gate isolation features for separating the subsequently-formed metal gate stack. The patterning process may include forming a patterned masking element over the structure200to expose portions of the dummy gate stacks220, removing the exposed portions of the dummy gate stacks220, thereby exposing portions of the underlying dielectric helmet232, and removing the exposed portions of the dielectric helmet232. After removing the patterned masking element, the remaining portions of the dielectric helmet232become the gate isolation features for the subsequently-formed metal gate stacks260. In alternative embodiments, as will be discussed in detail below, the dielectric helmet232are removed in its entirety at a subsequent operation and gate isolation features are formed separately after forming the metal gate stack.

Subsequently, method100removes the SiGe layers205and the SiGe layers207from the MLs to form openings (not depicted) between the Si layers206in a sheet formation, or sheet release, process. In the present embodiments, the sheet formation process further removes the remaining cladding layer213. In some embodiments, the sheet formation process is implemented in a series of etching and trimming processes. In one example, a wet etching process employing an oxidant (or oxidizer) such as ozone (O3; dissolved in water), nitric acid (HNO3), H2O2, other suitable oxidants, and a fluorine-based etchant such as HF, ammonium fluoride (NH4F), other suitable etchants, or combinations thereof may be performed during the sheet formation process.

Thereafter, still referring toFIGS.18A-18D, method100forms the metal gate stacks260and262over the structure200, wherein the metal gate stack260includes a first portion260aformed in the gate trenches and a second portion260bformed adjacent to the inner gate spacers248a, and the metal gate stack262includes a first portion262aformed in the gate trenches, a second portion262bformed adjacent to the inner gate spacers248a, and a third portion262cformed adjacent to the inner gate spacers248b. Accordingly, referring toFIGS.18A and18B, the second portion260bof the metal gate stack260and the second portion262bof the metal gate stack262are each defined by the gate length L1and the third portion262cof the metal gate stack262is defined by the gate length L2, which is greater than the gate length L1. As discussed above, the difference in the gate lengths L1and L2is attributed to the etching selectivity between the SiGe layers205and207.

In some embodiments, though not depicted, the metal gate stacks260and262each include an interfacial layer, a gate dielectric layer over the interfacial layer, and a metal gate electrode over the gate dielectric layer. Composition of the interfacial layer may be similar to that of the interfacial layer221. In some embodiments, the gate dielectric layer includes a high-k dielectric material, such as HfO2, La2O3, other suitable materials, or combinations thereof, and the metal gate electrode includes at least one work function metal layer (not depicted separately) and a bulk conductive layer (not depicted separately) disposed thereover. The work function metal layer may be a p-type or an n-type work function metal layer. Example work function metals include TiN, TaN, WN, ZrSi2, MoSi2, TaSi2, NiSi2, Ti, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable work function metals, or combinations thereof. In some examples where the metal gate stacks260and262are configured to form FETs of different conductivity types, the work function metals included in the metal gate stack260may differ from those included in the metal gate stack262. The bulk conductive layer may include copper (Cu), tungsten (W), aluminum (Al), cobalt (Co), ruthenium (Ru), other suitable materials, or combinations thereof. The metal gate stacks260and262each may further include other material layers (not depicted), such as a capping layer, a barrier layer, other suitable layers, or combinations thereof. Various layers of the metal gate stacks260and262may be formed by various methods, including chemical oxidation, thermal oxidation, ALD, CVD, PVD, plating, other suitable methods, or combinations thereof. After forming the bulk conductive layer, one or more CMP processes are performed to remove excessive material formed on top surface of the ILD layer258, thereby planarizing the structure200.

FIGS.19A and19Beach depict an example embodiment of the structure200that provides the NS FET300formed in the region202aand the NS FET400formed in the region202b. As discussed above, PG devices in an SRAM cell may benefit from increased gate lengths, such as that of the NS FET400depicted inFIG.18B, relative to PD and/or PU devices. Generally, readability (or read margin) of an SRAM cell is related to a ratio (β ratio) of the current of the PD device (Ion, PD) and the current of the PG device (Ion, PG), and writability (or write margin) of the SRAM cell is related to a ratio (a ratio) of the current of the PU device (Ion, PU) and Ion, PG, where the current is generally inversely related to the gate length of each device. In this regard, independently adjusting the gate length of each device in the cell may offer design flexibility in improving the writability and/or the readability of the SRAM cell. For example, referring to FIG.19A, the NS FET300may be a PD device having the relatively shorter gate length L1and a higher Ion, PD compared to the NS FET400, which may be a PG device having the relatively longer gate length L2and a lower Ion, PG, which together results in an increased β ratio. In another example, referring toFIG.19B, the NS FET300may be a PU device having the relatively shorter gate length L1and a higher Ion, PU compared to the NS FET400, which may be a PG device having the relatively longer gate length L2and a lower current Ion, PG, which together results in an increased α ratio. Accordingly, the present embodiments provide methods of configuring various devices in the SRAM cell with different gate lengths to allow different aspects of the device performance to be improved independently.

Thereafter, method100at operation126performs additional fabrication processes to the structure200, such as forming various device-level contacts (e.g., S/D contacts and/or gate contacts; not depicted) and a multi-layer interconnect (MLI) structure (not depicted) thereover. The S/D contacts may include Co, W, Ru, Cu, Al, titanium (Ti), nickel (Ni), gold (Au), platinum (Pt), palladium (Pd), other suitable metals, or combinations thereof. The S/D contacts may include a metal silicide layer over the S/D features250and/or252, a barrier layer over the metal silicide layer, and a metal fill layer over the barrier layer, where the barrier layer may include Ti, TiN, Ta, TaN, WN, other suitable materials, or combinations thereof. The MLI may include various interconnect features, such as vias and conductive lines, disposed in dielectric layers, such as ESLs and ILD layers. In some embodiments, the vias are vertical interconnect features configured to interconnect a device-level contact with a conductive line or interconnect different conductive lines, which are horizontal interconnect features. The ESLs and the ILD layers of the MLI may have substantially same compositions as those discussed above with respect to the ESL256and the ILD layer258, respectively. The vias and the conductive lines may each include any suitable conductive material, such as Co, W, Ru, Cu, Al, Ti, Ni, Au, Pt, Pd, a metal silicide, other suitable conductive materials, or combinations thereof, and be formed by a series of patterning and deposition processes. Additionally, each via and conductive line may additionally include a barrier layer that comprises Ti, TiN, Ta, TaN, WN, other suitable materials, or combinations thereof.

Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to a semiconductor device and the formation thereof. For example, the present disclosure provides NS FETs with tunable gate lengths to provide more flexibility in optimizing performance of memory cells (such as SRAM cells). In the present embodiments, tuning the NS FETs to have different gate lengths includes changing concentration of Ge in different SiGe layers provided in an ML and recessing the SiGe layers after forming the S/D recesses. In the present embodiments, differences in the concentration of Ge leads to the different SiGe layers to be recessed to different depths, leading to different gate lengths as well as inner spacers of different thicknesses. In some embodiments, a lower concentration of Ge leads to less extent of recessing and thus a longer gate length. With respect to SRAM cells, the present embodiments provide methods of independent adjusting gate lengths of various devices for purposes of improving the readability and/or writability of the cells. In addition, the present embodiments provide methods of forming NS FETs that allow functions of various devices formed on the same substrate to be tuned and optimized separately. Embodiments of the disclosed methods can be readily integrated into existing processes and technologies for manufacturing NS FETs.

In one aspect, the present disclosure provides a method that includes providing a substrate having a first region and a second region and subsequently forming a fin protruding from the first region of the substrate, where the fin includes a first SiGe layer and a stack alternating Si layers and second SiGe layers disposed over the first SiGe layer and the first SiGe layer has a first concentration of Ge and each of the second SiGe layers has a second concentration of Ge that is greater than the first concentration. The method further includes recessing the fin to form an S/D recess, recessing the first SiGe layer and the second SiGe layers exposed in the S/D recess, where the second SiGe layers are recessed more than the first SiGe layer, and forming an S/D feature in the S/D recess. The method further includes removing the recessed first SiGe layer and the second SiGe layers to form openings and then forming a metal gate structure over the fin and in the openings.

In another aspect, the present disclosure provides a method that includes forming a first SiGe layer over a substrate that has a first region and a second region, treating the first SiGe layer to form a second SiGe layer in the second region relative to the first region, where the second SiGe layer includes a greater amount of Ge than the first SiGe layer, forming a stack of alternating Si layers and the second SiGe layers over the treated first SiGe layer, and subsequently patterning to form a fin from the stack and the first SiGe layer. The method further includes forming an S/D recess in the fin to expose the first SiGe layer and the second SiGe layers, etching the exposed first SiGe layer and the second SiGe layers to form first trenches and second trenches, respectively, where the first trenches are narrower than the second trenches, and forming an S/D feature in the S/D recess. The method further includes removing remaining portions of the first SiGe layer and the second SiGe layers to form openings and then forming a metal gate structure in the openings.

In yet another aspect, the present disclosure provides a semiconductor structure that includes a stack of semiconductor layers disposed over a substrate and a metal gate stack interleaved with the stack of semiconductor layers, where a first portion of the metal gate stack disposed between a first semiconductor layer and a second semiconductor layer of the stack has a first length, a second portion of the metal gate stack disposed between the second semiconductor layer and a third semiconductor layer of the stack has a second length, and the first length is greater than the second length.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.