Patent ID: 12218003

Throughout the drawings, same or similar reference numerals represent the same or similar elements.

DETAILED DESCRIPTION

Embodiments in accordance with the present invention provide methods and devices for constructing fully-aligned vias (FAVs) for low capacitance wiring in semiconductor devices. The FAVs are integrated with airgap structures at a same metallization level. With the 7 nm technology node in the development phase and the 5 nm node moving into development, transistor scaling gets ever more complex. On top of that, performance benefits gained at the front-end-of-line (i.e., the transistors) can easily be undone if the back-end-of-line (BEOL) can't come along. BEOL processing involves the creation of stacked layers of copper (Cu) wires that electrically interconnect transistors in a chip. With each technology node, this Cu wiring scheme becomes more complex, mainly because there are more transistors to connect with an ever tighter pitch. Shrinking dimensions also means the wires have a reduced cross-sectional area, which drives up the resistance-capacitance product (RC) of the interconnect system.

Cu-based dual damascene has been the workhorse process flow for interconnects. A simple dual damascene flow starts with deposition of a low-k dielectric material on a structure. These low-k films are designed to reduce the capacitance and the delay in the integrated circuits (ICs). In a next step, this dielectric layer is covered with an oxide and a resist, and vias and trenches are formed using lithography and etch steps. These vias connect one metal layer with the layer above or below. Then, a metallic barrier layer is added to prevent Cu atoms from migrating into the low-k materials. The barrier layers are deposited with, e.g., physical vapor deposition (PVD), using materials such as tantalum and tantalum nitride. In a final step, this structure is electroplated by Cu in a chemical mechanical polishing (CMP) step.

Embodiments in accordance with the present invention provide methods and devices for integrating airgap structures and selective-dielectric fully-aligned vias (FAV) at a same metallization level without using additional airgap masks during the fabrication process. The selective dielectrics can be employed as a mask for airgap formation. Moreover, self-aligned contacts and via patterning are employed for patterning multiple contacts or vias from a single lithographic feature. Self-aligned contact and via patterning makes use of the intersection of an enlarged feature resist mask and underlying trenches which are surrounded by a pre-patterned hardmask layer. This technique can be used in, e.g., dynamic random access memory (DRAM) cells and can also be used for advanced logic to avoid multiple exposures of pitch-splitting contacts and vias. In accordance with embodiments of the present invention, the formation of low capacitance selective dielectrics does not contribute to rise of Cu resistivity.

Examples of semiconductor materials that can be employed in forming such structures include silicon (Si), germanium (Ge), silicon germanium alloys (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), III-V compound semiconductors and/or II-VI compound semiconductors. III-V compound semiconductors are materials that include at least one element from Group III of the Periodic Table of Elements and at least one element from Group V of the Periodic Table of Elements. II-VI compound semiconductors are materials that include at least one element from Group II of the Periodic Table of Elements and at least one element from Group VI of the Periodic Table of Elements.

It is to be understood that the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps/blocks can be varied within the scope of the present invention. It should be noted that certain features cannot be shown in all figures for the sake of clarity. This is not intended to be interpreted as a limitation of any particular embodiment, or illustration, or scope of the claims.

FIG.1is a cross-sectional view of a semiconductor structure including a plurality of copper (Cu) regions formed within an insulating layer, in accordance with an embodiment of the present invention.

A semiconductor structure5includes a semiconductor substrate10. An insulator layer12is deposited over the substrate10. The insulating layer12is etched to form trenches thereon. A conductive fill material or liner14is formed or deposited around each of the trenches. In one example, the liner can be a tantalum nitride (TaN) liner14or in the alternative a tantalum (Ta) liner14. In one example embodiment, the conductive fill material14can be deposited, for example, by electroplating, electroless plating, chemical vapor deposition (CVD), atomic layer deposition (ALD) and/or physical vapor deposition (PVD).

The trenches are then configured to receive a conductive material16. The conductive material16can be a metal, such as copper (Cu)16. One skilled in the art may contemplate a plurality of Cu regions16defined within the insulator layer12. A top surface17of the Cu regions16can be exposed. In another embodiment, the conductive material16can be, for example, a metal or doped polysilicon (poly-Si). Non-limiting examples of metals include aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The metal can be deposited by a suitable deposition process, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), plating, thermal or e-beam evaporation, or sputtering.

As used throughout the instant application, the term “copper” is intended to include substantially pure elemental copper, copper including unavoidable impurities including a native oxide, and copper alloys including one or more additional elements such as carbon, nitrogen, magnesium, aluminum, titanium, vanadium, chromium, manganese, nickel, zinc, germanium, strontium, zirconium, silver, indium, tin, tantalum, and platinum. In embodiments, the copper alloy is a copper-manganese alloy. In further embodiments, in lieu of copper, cobalt metal (Co) or cobalt metal alloys can be employed. The copper-containing structures are electrically conductive. “Electrically conductive” as used through the present disclosure refers to a material having a room temperature conductivity of at least 10−8(Ω-m)−1.

FIG.2is a cross-sectional view of the semiconductor structure ofFIG.1where inter-layer dielectric (ILD) regions are formed over exposed top surfaces of the insulating layer, in accordance with an embodiment of the present invention.

In various exemplary embodiments, ILD regions18can be formed over the exposed top portions or sections of the insulating layer12. Suitable dielectric materials for forming the ILD regions18include but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, SiCO, SiCON, or any suitable combination of such materials.

FIG.3is a cross-sectional view of the semiconductor structure ofFIG.2where a dielectric is deposited over the ILD regions and over the Cu regions, in accordance with an embodiment of the present invention.

In various exemplary embodiments, a dielectric20is deposited over the ILD regions18. The dielectric20can include an oxide, nitride or oxynitride material layer. In one example, when the dielectric20includes an oxide, the dielectric20can include silicon oxide (SiO2). In some embodiments, the dielectric20can include a low-k dielectric material. The deposition process for forming the dielectric20can include chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), high-density plasma CVD or spin-on glass process. In one example embodiment, the dielectric20can have a thickness of about 10 nanometers (nm) to about 1000 nm, or about 100 nm to about 500 nm.

FIG.4is a cross-sectional view of the semiconductor structure ofFIG.3where the dielectric is planarized such that the top surface of the dielectric is flush with the top surface of the ILD regions, in accordance with an embodiment of the present invention.

In various exemplary embodiments, a height of the dielectric20can be reduced by chemical-mechanical polishing (CMP) and/or etching. Therefore, the planarization process can be provided by CMP. Other planarization process can include grinding and polishing. The planarization of dielectric20results in dielectric regions22formed between the ILD regions18having a top surface19.

FIG.5is a cross-sectional view of the semiconductor structure ofFIG.4where a hardmask is formed over the dielectric and ILD regions, in accordance with an embodiment of the present invention.

In various exemplary embodiments, a hardmask24is deposited. The hardmask24can be manufactured of silicon nitride (SiN), deposited using, for example, low pressure chemical vapor deposition (LPCVD). In other embodiments, the hardmask24can include, but is not limited to, hafnium oxide (HfO2) or tantalum nitride (TaN). The hardmask24disposed over the Cu regions16and the ILD regions18is a layer of sufficient thickness to protect the Cu regions16and the ILD regions18from damage during the removal of subsequent layers.

FIG.6is a cross-sectional view of the semiconductor structure ofFIG.5where a sacrificial layer is deposited over a portion of the hardmask, in accordance with an embodiment of the present invention.

In various exemplary embodiments, a sacrificial layer26is deposited over a portion of the hardmask24. A top surface25of the hardmask24is thus exposed. The sacrificial layer26can be, for example, amorphous carbon (a-C). The sacrificial layer26can be deposited by a suitable deposition process, for example, chemical vapor deposition (CVD), or other suitable process.

FIG.7is a cross-sectional view of the semiconductor structure ofFIG.6where the exposed hardmask is etched and the sacrificial layer is removed to expose a portion of the ILD regions, in accordance with an embodiment of the present invention.

In various exemplary embodiments, the exposed hardmask24is etched and the sacrificial layer26is completely removed. A section or portion of the hardmask24remains intact to cover a portion of the dielectric regions22and a portion of the ILD regions18. The etching can include a dry etching process such as, for example, reactive ion etching, plasma etching, ion etching or laser ablation. The etching can further include a wet chemical etching process in which one or more chemical etchants are employed to remove portions of the layers.

FIG.8is a cross-sectional view of the semiconductor structure ofFIG.7where the exposed ILD regions are selectively removed to expose a top surface of the insulating layer, in accordance with an embodiment of the present invention.

In various exemplary embodiments, the exposed ILD regions18are selectively removed resulting in the formation of recesses or gaps28. The regions where the recesses or gaps28are formed can be referred to as an airgap region defining a plurality of airgaps. The region or area maintaining the ILD regions18can be referred to as a non-airgap region or a FAV region.

Additionally, top surfaces13of the insulating layer12are exposed. The exposed ILD regions18can be removed by, e.g., dilute hydrofluoric acid (DHF). The remaining ILD regions18(under the hardmask24) are employed as a mask for airgap formation in the airgap region of the device. Stated differently, the removal of selective ILD regions18occurs in the airgap region subsequently defining a plurality of airgaps (FIG.13).

FIG.9is a cross-sectional view of the semiconductor structure ofFIG.8where the hardmask is removed to expose the remaining ILD regions, in accordance with an embodiment of the present invention.

In various exemplary embodiments, the remaining hardmask24is removed in the FAV region to expose the top surface19of the ILD regions18and the top surface23of the dielectric regions22. The remaining hardmask24can be removed by employing a dry etching process, for example, and anisotropic etching process.

FIG.10is a cross-sectional view of the semiconductor structure ofFIG.9where minimal ILD damage is caused to the dielectric and the exposed portions of the insulating layer, in accordance with an embodiment of the present invention.

In various exemplary embodiments, minimal ILD damage is caused to form dielectric regions22′ between the ILD regions18and to form insulating layer areas12′ with top surfaces13′. An ash process can be employed to cause the minimal ILD damage. As a consequence of such a chemically and physically “friendly” ash process, the original chemical and physical integrity of the remaining materials is maintained. The minimal ILD damage is caused in both the airgaps region and the non-airgap region or FAV region. The minimal ILD damage aids in the subsequent formation of airgaps in the airgap region.

FIG.11is a cross-sectional view of the semiconductor structure ofFIG.10where the minimally damaged dielectric and exposed portions of the insulating layer are selectively removed, in accordance with an embodiment of the present invention.

In various exemplary embodiments, the ILD damaged dielectric regions22′ and the ILD damaged insulating layer areas12′ are selectively removed to fully expose the remaining ILD regions18having top surfaces19and sidewalls30. Moreover, recesses32are formed resulting from the removal of the ILD damaged insulating layer areas12′. The recesses32are formed in the airgap region of the device. This also results in the exposure of top surfaces13of the insulating layer12, as well as the exposure of side surfaces of the conductive fill material or liner14.

FIG.12is a cross-sectional view of the semiconductor structure ofFIG.11where a conformal cap is deposited, in accordance with an embodiment of the present invention.

In various exemplary embodiments, the conformal dielectric cap34includes any non-oxygen having a dielectric capping material such as, for example, SiC, Si3N4, a carbon doped oxide, a nitrogen and hydrogen doped silicon carbide SiC(N,H), boron nitride, SiCBN, carbon boron nitride or multilayers thereof. The recesses32remain after formation of the conformal cap34.

FIG.13is a cross-sectional view of the semiconductor structure ofFIG.12where an ILD layer is deposited over the structure such that airgaps are formed at the exposed portions of the insulating layer, in accordance with an embodiment of the present invention.

In various exemplary embodiments, a dielectric layer36(e.g., an oxide layer) is then deposited over structure. The dielectric layer36can be an interlevel dielectric (ILD). In various embodiments, a height of the dielectric layer36can be reduced by chemical-mechanical polishing (CMP) and/or etching.

The deposition of the dielectric layer36causes the airgaps32to be maintained between the plurality of trenches16. The dielectric layer36is a non-conformal PECVD process which has poor step coverage in recess32with narrow metal lines and tends to “pinch off,” thus creating air gap structure in recess32.

Therefore, airgaps and selective-dielectric fully-aligned via (FAV) can be integrated at the same metallization level without using an additional airgap mask. The ILD regions18serve as the selective dielectric for the FAV. The selective ILD regions18are thus employed as a mask for formation of the airgaps32. Thus, a FAV with a selective dielectric guiding pattern can be created at the same metallization level with the airgaps32formed on a different part of the chip. The airgaps32formed in the airgap region of the device enable low capacitance wiring in semiconductor devices. The block mask24can be used so that only areas on the chip with minimum spaces and a need for low capacitance receives the airgaps. This maximizes the thermal conductance and mechanical stability of the chip.

Because of continuing decreases in size of circuit components in semiconductor chips, there are a number of interconnect wiring challenges facing the technical community over the next few technology generations. Among these challenges is the issue of undesirable capacitance in dielectric materials between circuit wiring. One avenue being pursued according to the exemplary embodiments of the present invention is to lower interconnect capacitance by developing airgaps integrated with selective-dielectric FAV at the same metallization level. Stated differently, the spin-on dielectric backfill with planarization and selective wet removal enable tone inversion to remove selective dielectric in an airgap region prior to etch back airgap (EBAG) schemes. Therefore, the low capacitance selective ILD regions18do not provide issues with porosity as Cu line widths decrease in semiconductor circuits and the low capacitance selective ILD regions18do not contribute to rise of Cu resistivity as Cu line widths decrease in semiconductor circuits.

FIG.14is a cross-sectional view of the semiconductor structure ofFIG.13where the ILD layer is etched to expose a top surface of at least one Cu region and top surfaces of ILD regions, in accordance with an embodiment of the present invention.

In various exemplary embodiments, the dielectric layer36is etched to form remaining dielectric layers36′. A recess38is formed exposing a top surface19of the dielectric regions18and a top surface17of a Cu region16. Additionally, conformal dielectric cap portions34′ remain adjacent sidewalls of the ILD regions18. The recess38can be, e.g., a via. The via38can be referred to as a fully-aligned via (FAV). The FAV can be aligned with the ILD regions18in the non-airgap region or FAV region.

FIG.15is a cross-sectional view of the semiconductor structure ofFIG.14where a metal fill takes place, in accordance with an embodiment of the present invention.

In various exemplary embodiments, a metal fill40takes place. The metal fill40can be, e.g., Cu or any other conductive material contemplated by one skilled in the art.

RegardingFIGS.1-15andFIGS.16-35described below, deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include, but are not limited to, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others.

Removal is any process that removes material from the wafer: examples include etch processes (either wet or dry), and chemical-mechanical planarization (CMP), etc.

Patterning is the shaping or altering of deposited materials, and is generally referred to as lithography

FIG.16is a cross-sectional view of the semiconductor structure ofFIG.2where a dielectric cap is deposited over the ILD regions, in accordance with another embodiment of the present invention.

In various exemplary embodiments, a dielectric cap50is deposited over the ILD regions18, as well as a top surface17of the Cu regions16. In some embodiments, the dielectric cap50is formed of a single dielectric cap layer. In other embodiments, the dielectric cap50is formed of multiple dielectric cap layers. The dielectric cap50includes any non-oxygen having a dielectric capping material such as, for example, SiC, Si3N4, a carbon doped oxide, a nitrogen and hydrogen doped silicon carbide SiC(N,H), boron nitride, SiCBN, carbon boron nitride or multilayers thereof.

FIG.17is a cross-sectional view of the semiconductor structure ofFIG.16where a dielectric is deposited over the dielectric cap, in accordance with an embodiment of the present invention.

In various exemplary embodiments, a dielectric layer52is deposited over the dielectric cap50.

FIG.18is a cross-sectional view of the semiconductor structure ofFIG.17where the dielectric is planarized such that a top surface of the dielectric cap is flush with a top surface of the dielectric, in accordance with an embodiment of the present invention.

In various exemplary embodiments, the dielectric layer52is planarized. A height of the dielectric layer52can be reduced by chemical-mechanical polishing (CMP) and/or etching. Therefore, the planarization process can be provided by CMP. Other planarization process can include grinding and polishing. The planarization of dielectric layer52results in dielectric regions54formed between the ILD regions18. A top surface51of the dielectric cap50is also exposed.

FIG.19is a cross-sectional view of the semiconductor structure ofFIG.18where a hardmask is deposited, in accordance with an embodiment of the present invention.

In various exemplary embodiments, a hardmask56is deposited over the dielectric regions54, as well as over the exposed portions of the dielectric cap50.

FIG.20is a cross-sectional view of the semiconductor structure ofFIG.19where a sacrificial layer is deposited over a portion of the hardmask, in accordance with an embodiment of the present invention.

In various exemplary embodiments, a sacrificial layer58is deposited over a portion of the hardmask56. A top surface57of the hardmask56is thus exposed. The sacrificial layer58can be, for example, amorphous carbon (a-C). The sacrificial layer58can be deposited by a suitable deposition process, for example, chemical vapor deposition (CVD), or other suitable process.

FIG.21is a cross-sectional view of the semiconductor structure ofFIG.20where the exposed hardmask is removed, the exposed dielectric is removed, the exposed dielectric cap is removed, and the sacrificial layer are removed to expose a portion of the ILD regions, in accordance with an embodiment of the present invention.

In various exemplary embodiments, the exposed hardmask56is etched and the sacrificial layer58is completely removed. A section or portion of the hardmask56remains intact to cover a portion of the dielectric regions54and a portion of the ILD regions18. Moreover, the ILD regions18are exposed such that the top surfaces19are fully exposed and the sidewalls30are partially exposed. Moreover, sections of the dielectric cap50are exposed between the ILD regions18.

FIG.22is a cross-sectional view of the semiconductor structure ofFIG.21where the exposed ILD regions are selectively removed, in accordance with an embodiment of the present invention.

In various exemplary embodiments, the exposed ILD regions18are selectively removed such that top surfaces13of the insulating layer12are exposed.

FIG.23is a cross-sectional view of the semiconductor structure ofFIG.22where the remaining hardmask is removed to expose remaining dielectric, in accordance with an embodiment of the present invention.

In various exemplary embodiments, the hardmask56is removed. The remaining hardmask56can be removed by employing a dry etching process, for example, and anisotropic etching process.

FIG.24is a cross-sectional view of the semiconductor structure ofFIG.23where minimal ILD damage occurs for the exposed dielectric and the exposed portions of the dielectric layer, in accordance with an embodiment of the present invention.

In various exemplary embodiments, minimal ILD damage is caused to form dielectric regions54′ and insulating layer areas12′ with top surfaces13′ between the Cu regions16. An ash process can be employed to cause the minimal ILD damage. As a consequence of such a chemically and physically “friendly” ash process, the original chemical and physical integrity of the remaining materials is maintained.

FIG.25is a cross-sectional view of the semiconductor structure ofFIG.24where the minimal ILD damaged exposed dielectric and exposed portions of the dielectric layer are selectively removed to form recesses between the Cu regions, in accordance with an embodiment of the present invention.

In various exemplary embodiments, the dielectric regions54′ and the insulating layer areas12′ are selectively removed by, e.g., DHF resulting in recesses60formed between the Cu regions16. The recesses60are formed in the airgap region of the device.

FIG.26is a cross-sectional view of the semiconductor structure ofFIG.25where a conformal cap is deposited within the recesses, in accordance with an embodiment of the present invention.

In various exemplary embodiments, a conformal cap62can be formed within the recesses60.

FIG.27is a cross-sectional view of the semiconductor structure ofFIG.26where an ILD layer is deposited over the structure such that airgaps are formed at the exposed portions of the insulating layer, in accordance with an embodiment of the present invention.

In various exemplary embodiments, a dielectric layer64(e.g., an oxide layer) is then deposited over structure. The dielectric layer64can be an interlevel dielectric (ILD).

The deposition of the dielectric layer64causes airgaps60to be maintained within the airgap region. Thus, an airgap and selective-dielectric fully-aligned via (FAV) can be integrated at the same metallization level without using an additional airgap mask. The ILD regions18serve as the selective dielectric for the FAV. The selective ILD regions18are thus employed as a mask for formation of the airgaps60. Thus, a FAV with selective dielectric guiding pattern can be created at the same metallization level with airgaps60formed on a different part of the chip. The airgaps60enable low capacitance wiring in semiconductor devices. The block mask56can be used so that only areas on the chip with minimum spaces and a need for low capacitance receive the airgaps60. This maximizes the thermal conductance and mechanical stability of the chip.

FIG.28is a cross-sectional view of the semiconductor structure ofFIG.27where the ILD layer is etched to expose a top surface of at least one Cu region and top surfaces of ILD regions, in accordance with an embodiment of the present invention.

In various exemplary embodiments, the dielectric layer64is etched to form remaining dielectric layers64′. A recess66is formed exposing a top surface19of the dielectric regions18and a top surface17of a Cu region16. Additionally, conformal cap portions50′ remain adjacent sidewalls of the ILD regions18. The recess66can be, e.g., a via. The via66can be referred to as a fully-aligned via (FAV). The FAV can be aligned with the ILD regions18in the non-airgap region or FAV region.

FIG.29is a cross-sectional view of the semiconductor structure ofFIG.28where a metal fill takes place, in accordance with an embodiment of the present invention.

In various exemplary embodiments, a metal fill68takes place. The metal fill68can be, e.g., Cu or any other conductive material contemplated by one skilled in the art.

FIG.30is a cross-sectional view of the semiconductor structure ofFIG.24where ILD damage occurs only to the exposed portions of the insulating layer, in accordance with another embodiment of the present invention.

In various exemplary embodiments, minimal ILD damage is caused to form only insulating layer areas12′ with top surfaces13′ between the Cu regions16. An ash process can be employed to cause the minimal ILD damage. As a consequence of such a chemically and physically “friendly” ash process, the original chemical and physical integrity of the remaining materials is maintained.

FIG.31is a cross-sectional view of the semiconductor structure ofFIG.30where the ILD damaged exposed portions of the insulating layer are selectively removed to form recesses or gaps, in accordance with an embodiment of the present invention.

In various exemplary embodiments, the insulating layer areas12′ are selectively removed to form recesses70between the Cu regions16.

FIG.32is a cross-sectional view of the semiconductor structure ofFIG.31where a conformal cap is deposited within the recesses or gaps, in accordance with an embodiment of the present invention.

In various exemplary embodiments, a conformal cap72can be formed over the dielectric regions54and within the recesses70. The conformal cap72can extend across the entire structure.

FIG.33is a cross-sectional view of the semiconductor structure ofFIG.32where a dielectric layer is deposited over the structure such that airgaps are formed at the exposed portions of the insulating layer, in accordance with an embodiment of the present invention.

In various exemplary embodiments, a dielectric layer74(e.g., an oxide layer) is then deposited over structure. The dielectric layer74can be an interlevel dielectric (ILD).

The deposition of the dielectric layer74causes airgaps70to be maintained within the airgap region. Thus, an airgap and selective-dielectric fully-aligned via (FAV) can be integrated at the same metallization level without using an additional airgap mask. The ILD regions18serve as the selective dielectric for the FAV. The selective ILD regions18are thus employed as a mask for formation of the airgaps70. Thus, a FAV with selective dielectric guiding pattern can be created at the same metallization level with airgaps70formed on a different part of the chip.

FIG.34is a cross-sectional view of the semiconductor structure ofFIG.33where the ILD layer is etched to expose a top surface of at least one Cu region and top surfaces of ILD regions, in accordance with an embodiment of the present invention.

In various exemplary embodiments, the dielectric layer74is etched to form remaining dielectric layers74′. A recess76is formed exposing a top surface19of the dielectric regions18and a top surface17of a Cu region16. Additionally, conformal cap portions72′ remain adjacent sidewalls of the ILD regions18. The recess76can be, e.g., a via. The via76can be referred to as a fully-aligned via (FAV). The FAV can be aligned with the ILD regions18in the non-airgap region or FAV region.

FIG.35is a cross-sectional view of the semiconductor structure ofFIG.34where a metal fill takes place, in accordance with an embodiment of the present invention.

In various exemplary embodiments, a metal fill78takes place. The metal fill78can be, e.g., Cu or any other conductive material contemplated by one skilled in the art.

Therefore, in summary, selective dielectric deposition is used to achieve both a fully aligned via (aligned to the metal above and below) and airgaps concurrently or simultaneously. Removing portions of selective ILD regions in airgap regions enables multiple airgap formation within the airgap region of the device. The vias are formed in a second interconnect level and are confined by the selective ILD regions to align with a first interconnect level (where the ILD regions were formed).

The interconnect structures disclosed herein can be incorporated into any electrical device. For example, the interconnect structures can be present within electrical devices that use semiconductors that are present within integrated circuit chips. The integrated circuit chips including the disclosed interconnects can be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, including computer products or devices having a display, a keyboard or other input device, and a central processing unit.

It is to be understood that the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps/blocks can be varied within the scope of the present invention.

It will also be understood that when an element such as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

The present embodiments can include a design for an integrated circuit chip, which can be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer can transmit the resulting design by physical mechanisms (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer to be etched or otherwise processed.

Methods as described herein can be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

It should also be understood that material compounds will be described in terms of listed elements, e.g., SiGe. These compounds include different proportions of the elements within the compound, e.g., SiGe includes SixGei_x where x is less than or equal to 1, etc. In addition, other elements can be included in the compound and still function in accordance with the present embodiments. The compounds with additional elements will be referred to herein as alloys. Reference in the specification to “one embodiment” or “an embodiment” of the present invention, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment.

It is to be appreciated that the use of any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This can be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, can be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the FIGS. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIGS. For example, if the device in the FIGS. is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein can be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers can also be present.

It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the scope of the present concept.

Having described preferred embodiments of a method for an integrated airgap and selective-dielectric fully-aligned via (FAV) at a same metallization level without an additional airgap mask (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments described which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.