Patent ID: 12206021

DETAILED DESCRIPTION

Hereinbelow, various example embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

Referring toFIGS.1,2A and2B, a negative differential resistance device according to example embodiments will be described.

FIG.1is a planar view schematically illustrating a negative differential resistance device according to example embodiments of the present disclosure.FIG.2is a side cross-sectional view taken along line I-I′ ofFIG.1, andFIG.2Bis a graph illustrating voltage-current characteristics of the differential resistance device ofFIG.1.

Referring toFIG.1, a negative differential resistance device100according to example embodiments may include a dielectric layer140, a first semiconductor layer150, a second semiconductor layer160and first to third electrodes170,180and130. In addition, depending on example embodiments, a support substrate110may further be disposed on a lower portion of the third electrode130, and an insulating layer120may further be disposed between the dielectric layer140and the support substrate110. The support substrate110may be a conductive substrate. Therefore, the first semiconductor layer150, the second semiconductor layer160and the dielectric layer140are disposed on the support substrate110to prevent damage of the first semiconductor layer150, the second semiconductor layer160and the dielectric layer140, and apply power to the third electrode130through the support substrate110.

Referring toFIG.2A, the dielectric layer140may have a first surface141and a second surface142located in an opposite direction. The dielectric layer140may be formed of a dielectric material or a ferroelectric material in the dielectric material depending on example embodiments.

The dielectric materials may include at least one of silicon oxide, aluminum oxide, titanium oxide, and hexagonal boron nitride (hBN). In particular, when the dielectric layer140is formed of hBN, the dielectric layer140can be plasma-treated to increase a doping concentration.

The ferroelectric materials may include at least one of, for example, hafnium oxide, hafnium zirconium oxide, zirconium oxide, barium strontium titanium oxide, barium titanium oxide and/or lead zirconium titanium oxide. At this time, hafnium zirconium oxide may be a material in which zirconium (Zr) is doped in hafnium oxide or a compound of hafnium (Hf), zirconium (Zr) and oxygen (O). In some embodiments, a case in which the dielectric layer140formed of a ferroelectric material is described as an example.

A first semiconductor layer150may be disposed in a first region A1on the first surface141of the dielectric layer140. In addition, a second semiconductor layer160may be disposed in a second region A2. A partial region A3of the first region A1may overlap the second region A2. That is, a partial region of the second semiconductor layer160may be disposed to overlap a top of the first semiconductor layer150, but is not limited thereto. Depending on example embodiments, side surfaces of the second semiconductor layer160and the first semiconductor layer150are disposed to be in contact with each other so that an upper surface of the second semiconductor layer160is in the same level as that of the first semiconductor layer150, with respect to the support substrate110. A source voltage Vs and a drain voltage Vd may be applied to the first and second semiconductor layers150and160through the first electrode170and the second electrode180, respectively.

The first semiconductor layer150has a first polarity and may be a degenerated semiconductor layer. The second semiconductor layer160has a second polarity different from the first polarity and may be a degenerated semiconductor layer. As used herein, the expression “degenerated semiconductor layer” refers to a semiconductor layer heavily doped with respect to a polarity thereof. The first and second semiconductor layers150and160may be p-type and n-type semiconductor layers, respectively, or n-type and p-type semiconductor layers, respectively. The p-type semiconductor layer may be formed of at least one of silicon (Si), germanium (Ge), III-V group semiconductor, organic semiconductor, oxide semiconductor, transition metal chalcogenide and phosphorene, but is not limited thereto. The n-type semiconductor layer may be formed of at least one of silicon (Si), germanium (Ge), III-V group semiconductor, organic semiconductor, oxide semiconductor, transition metal chalcogenide and disulfide (ReS2), but is not limited thereto. In some example embodiments, a case in which the first semiconductor layer150is formed of rhenium disulfide, and the second semiconductor layer160is formed of phosphorene is described.

A first electrode170may be coupled to an end of one side of the first semiconductor layer150. In some embodiments, a partial region of the first electrode170may be directly in contact with the first surface141of the dielectric layer140, depending on example embodiments. The first electrode170may be formed of at least one of titanium (Ti), aluminum (Al), erbium (Er), platinum (Pt), gold (Au) and/or palladium (Pd), but is not limited thereto.

The second electrode180may be coupled to an end of one side of the second semiconductor layer160. The partial region of the second electrode180may be directly in contact with the first surface141of the dielectric layer140, depending on example embodiments. The second electrode180may be formed of at least one of titanium (Ti), aluminum (Al), erbium (Er), platinum (Pt), gold (Au) and/or palladium (Pd), but is not limited thereto.

The third electrode130may be disposed on the second surface142of the dielectric layer140. The third electrode130may be a type of gate electrode for forming a channel region143on the dielectric layer140.

As shown inFIG.2A, when the dielectric layer140is formed of a ferroelectric material, a polarity of spontaneous polarization may be reversed and arranged in the channel region143. Further, as shown inFIG.3, when a dielectric layer140′ is formed of a dielectric material, a positive or negative charge may be trapped in accordance with a polarity of a voltage applied through the third electrode130in a channel region143′.

Referring toFIG.2A, a width of the channel region143formed on the dielectric layer140may be controlled by adjusting a width W of the third electrode130. The third electrode130may be disposed to overlap the first semiconductor layer150and/or the second semiconductor layer160. Referring toFIG.4, a width W of the third electrode130may be disposed to include at least one of a first sub-region W1, a second sub-region W2and a third sub-region W3of the region in contact with the first semiconductor layer150and the second semiconductor layer160. The first sub-region W1is in an area in which the third electrode130is overlapped with the first semiconductor layer150, but not the second semiconductor layer160. The second sub-region W2is in an area in which the third electrode130is overlapped with both the first semiconductor layer150and the second semiconductor layer160. The third sub-region W3is in an area in which the third electrode130is overlapped with the second semiconductor layer160, but not the first semiconductor layer150. The third electrode130may be formed to include any one of the first to third sub-regions A1to A3, two regions of the first to third sub-regions A1to A3or all sub-regions of the first to third sub-regions A1to A3.

The insulating layer120may be disposed in a region of the second surface142, in which the third electrode130of the dielectric layer140is not disposed, thereby preventing the dielectric layer140from contacting the support substrate110.

The negative differential resistance device100having such a configuration may shift a current-voltage characteristic curve of the negative resistance device100by adjusting a voltage applied to the third electrode130. This will be described with reference toFIGS.2A and2B.

Referring toFIGS.2A and2B, when the source voltage Vs and the drain voltage Vd are applied through the first electrode170and the second electrode180of the negative differential resistance device100, the negative differential resistance device100may have a current-voltage characteristic having a negative differential resistance area (NDRA).

Referring toFIG.2B, the negative differential resistance device100, in contrast to a conventional resistance device, may have a negative differential resistance area (NDRA) in which a current I is reduced despite an increase in a voltage V. That is, the negative differential resistance area (NDRA) is a region in which a voltage value increases from V1 to V2, but a current value is reduced from a peak current value Ip to a valley current value Iv. A position on the current-voltage characteristic curve G1, at which the negative differential resistance area (NDRA) occurs, is determined according to physical properties of the first semiconductor layer150and the second semiconductor layer160, and the negative differential resistance device has a current-voltage characteristic having only one peak current value Ip and one valley current value Iv. Therefore, positions of the peak current value Ip and the valley current value Iv of the negative differential resistance device are fixed values which cannot be changed without changing materials, concentrations, and/or amounts of the first semiconductor layer150and the second semiconductor layer160.

In some example embodiments, the positions of the peak current value Ip and the valley current value Iv of the current-voltage characteristic curve G1may be adjusted without changing the materials of the first and second semiconductor layers150and160, by disposing the first semiconductor layer150and the second semiconductor layer160on the first surface141of the dielectric layer140and disposing the third electrode130capable of adjusting the width of the channel region143on the second surface142of the dielectric layer140. By adjusting a gate voltage Vg applied through the third electrode130, the current-voltage characteristic curve G1may be shifted to another current-voltage characteristic curves G2and G3.

For example, as shown inFIGS.2A and2B, in the case in which the dielectric layer140is formed of a ferroelectric material, polarity-reversed spontaneous polarization increases in the channel region143increases as the gate voltage Vg increases to have a positive (+) value. Accordingly, the current-voltage characteristic curve G1shifts toward an S1 direction and moves to another current-voltage characteristic curve G2. In addition, as the gate voltage Vg decreases to have a negative (−) value, the polarity-reversed spontaneous polarization is reduced in the channel region143. Therefore, the current-voltage characteristic curve G1shifts toward an S2 direction and moves to another current-voltage characteristic curve G3.

For example, as shown inFIG.3, in the case in which the dielectric layer140is formed of a dielectric material, a number of electrons trapped in the channel region143increases as the gate voltage Vg increases have a positive (+) value. Accordingly, the current-voltage characteristic curve G1shifts toward the S1 direction and moves to another current-voltage characteristic curve G2. Further, as the gate voltage Vg decreases have a negative (−) value, a number of holes trapped in the channel region143increases. Therefore, the current-voltage characteristic curve G1shifts toward the S2 direction and moves to another current-voltage characteristic curve G3. Accordingly, the current-voltage characteristic curve G1of the negative differential resistance device100may be changed by controlling the gate voltage Vg applied through the third electrode130.

Referring toFIGS.5to8, a negative differential resistance device according to example embodiments is described.FIGS.5,7and8are diagrams illustrating various example embodiments of a negative differential resistance device according to some embodiments of the present disclosure.FIG.6Ais a circuit diagram of the negative differential resistance device ofFIG.5, andFIG.6Bis a graph illustrating voltage-current characteristics of the negative differential resistance device ofFIG.5.

In comparison to the negative differential resistance device100of the example embodiments previously described, a negative differential resistance device200ofFIG.5is different in that it configures an equivalent circuit to a circuit in which first and second negative differential resistance devices NDR1and NDR2are connected in parallel along first and second directions DR1and DR2and are electrically connected to a first electrode270and a second electrode280, respectively.

A first dielectric layer290may be disposed in the first negative differential resistance device NDR1, and a second dielectric layer240and a third electrode230may be disposed in the second negative differential resistance device NDR2. Accordingly, as shown inFIG.6A, the negative differential resistance device200may configure an equivalent circuit to a circuit in which the first negative differential resistance device NDR1and the second negative differential resistance device NDR2are connected in parallel between the first electrode270and the second electrode280.

As shown inFIG.6B, a current-voltage characteristic curve G4of the first negative differential resistance device NDR1has a fixed value, and a current-voltage characteristic curve G5of the second negative differential resistance device NDR2may be shifted in a S3 or S4 direction, depending on a voltage applied to the third electrode230. That is, the negative differential resistance device200of some example embodiments may have the same or similar characteristics as a circuit element in which the first negative differential resistance device NDR1having a fixed value and the second negative differential resistance device NDR2having variable values are connected in parallel. A current applied to the negative differential resistance device200flows along a region having a relatively lower resistance value, among the first negative differential resistance device NDR1and the second negative differential resistance device NDR2connected in parallel. As such, a current-voltage characteristic curve G6of the negative differential resistance device200overall follows a current-voltage characteristic curve connecting the current-voltage characteristic curve G4of the first negative differential resistance device NDR1and an upper portion of the current-voltage characteristic curve G5of the second negative differential resistance device NDR2.

As configurations of the first semiconductor layer250and the second semiconductor layer260, the first to third electrodes270,280and230, and the insulating layer220are the same as those of the previous embodiment, detailed descriptions thereof are omitted to avoid repetition.

A negative differential resistance device may be used to change a logic/memory element into a multi-valued logic circuit or reduce power consumption by reducing a connection wire area. However, the negative differential resistance device having one peak current value and one valley current value has a limitation in increasing a state value of the multi-valued logic circuit. The negative differential resistance device200according to example embodiments has the same characteristic as a circuit element in which having a plurality of negative differential resistance devices connected in parallel and thus can provide the current-voltage characteristic curve G6having the plurality of negative differential resistance areas NDR1and NDR2, as shown inFIG.6B. In this regard, the negative differential resistance device200of some example embodiments may be used to manufacture a multi-valued logic circuit having more state values than the negative differential resistance device100ofFIG.1.

In comparison to the negative differential resistance device200ofFIG.5previously described, a negative differential resistance device300ofFIG.7is similar thereto in that first and second negative differential resistance devices NDR11and NDR12of the negative differential resistance device300are connected in parallel in first and second directions DR11and DR12. However, in contrast to the negative differential resistance device200ofFIG.5in which the third electrode230is disposed only on the second negative differential resistance device NDR2, the negative differential resistance device300ofFIG.7is different in that a third electrode330is disposed on each of the first negative differential resistance device NDR11and the second negative differential resistance device NDR12. The third electrodes330disposed on the first negative differential resistance device NDR11and the second negative differential resistance device NDR12may be spaced apart and thus may not be connected to each other. In some example embodiments, in cases in which first and second insulating layers320A and320B are respectively disposed in the first negative differential resistance device NDR11and the second negative differential resistance device NDR12and spaced apart from each other, but the first and second insulating layers320A and320B are not limited thereto. The first and second insulating layers320A and320B may be disposed between third electrodes330spaced apart from each other such that the third electrodes330disposed in the first negative differential resistance device NDR11and the second negative differential resistance device NDR12are not connected to each other. As the configurations of the first semiconductor layer350, the second semiconductor layer360and the first to third electrodes370,380and330are the same as those described above, detailed descriptions thereof will be omitted to avoid repetition.

In comparison to the negative differential resistance device300ofFIG.7previously described, a negative differential resistance device400ofFIG.8is different in that first to third negative differential resistance devices NDR21, NDR22and NDR23are arranged in parallel in first to third directions DR21, DR22and DR33. In some example embodiments, three negative differential resistance devices NDR21, NDR22and NDR23may be disposed in parallel in a single negative differential resistance device300but the negative differential resistance is not limited thereto. When the third electrode330is divided into n regions in the first to third directions DR21, DR22and DR33, the same or similar characteristics as the one having n negative differential resistance devices are connected in parallel may be exhibited.

In some example embodiments, first to third insulating layers420A,420B and420C may be disposed on the first to third negative differential resistance devices NDR21, NDR22and NDR23, respectively, to be spaced apart from each other, but the insulating layers are not limited thereto. The first to third insulating layers420A,420B and420C may be disposed between the third electrodes430spaced apart from each other so as not to contact the third electrodes430disposed on the first to third negative differential resistance devices NDR21, NDR22and NDR23. As the configurations of first semiconductor layer450and second semiconductor layer460and the first to third electrodes470,480and430are the same as or similar to those of the previous embodiments, and detailed descriptions thereof will be omitted to avoid repetition.

As set forth above, a negative differential resistance device capable of changing a position of peak current value and a position of the valley current value by controlling the voltage applied to a third electrode layer, which is disposed along with a dielectric layer on a first and second semiconductor layers, is provided.

A plurality of third electrodes arranged in one negative differential resistance device may be arranged to provide a negative differential resistance device having a plurality of peak current values and a plurality of valley current values.

Various advantages and effects of the present disclosure are not limited to the description above, and may be more readily understood in the description of example embodiments in the present disclosure.

While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present invention as defined by the appended claims.