Patent ID: 12191272

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Other features and processes may also be included. For example, testing structures may be included to aid in the verification testing of the 3D packaging or 3DIC devices. The testing structures may include, for example, test pads formed in a redistribution layer or on a substrate that allows the testing of the 3D packaging or 3DIC, the use of probes and/or probe cards, and the like. The verification testing may be performed on intermediate structures as well as the final structure. Additionally, the structures and methods disclosed herein may be used in conjunction with testing methodologies that incorporate intermediate verification of known good dies to increase the yield and decrease costs.

FIGS.1A through1Care cross-sectional views schematically illustrating a fabrication process of semiconductor dies in accordance with some embodiments of the present disclosure.

Referring toFIG.1A, a semiconductor wafer W1is provided. The semiconductor wafer W1may include various doped regions (e.g., p-type doped regions or n-type doped regions) formed through front end of line (FEOL) fabrication processes of the semiconductor wafer W1. The doped regions may be doped with p-type and/or n-type dopants. The doped regions may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and/or combinations thereof. The doped regions may be configured for an n-type FinFET, a p-type FinFET or the combination thereof. In some other embodiments, the doped regions may be configured for an n-type MOSFET, a p-type MOSFET or the combination thereof. The semiconductor wafer W1may include a semiconductor substrate110and an interconnect structure120, wherein the interconnect structure120is disposed on the semiconductor substrate110. In some embodiments, the semiconductor substrate110includes a crystalline silicon substrate. In some alternative embodiments, the semiconductor substrate110is made of some other suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide.

The interconnect structure120may include interconnect wirings (e.g., copper interconnect wirings) and dielectric layer stacked alternately, wherein the interconnect wirings of the interconnect structure120are electrically connected to the active components and/or the passive components in the semiconductor substrate110. The interconnect structure120is formed through back end of line (BEOL) fabrication processes of the semiconductor wafer W1. The topmost interconnect wirings of the interconnect structure120may include conductive pads122, and the conductive pads122may be aluminum pads, copper pads, or other suitable metallic pads. The interconnect structure120may further include a passivation layer (not shown) disposed on a front surface or an active surface of the semiconductor wafer W1, wherein the conductive pads122are partially covered by the passivation layer. In other words, the conductive pads122are partially revealed from the openings defined in the passivation layer. The passivation layer may be a silicon oxide layer, a silicon nitride layer, a silicon oxy-nitride layer, or a dielectric layer formed by other suitable inorganic dielectric materials. The interconnect structure120may further include a post-passivation layer (not shown) formed over the passivation layer, wherein the post-passivation layer covers the passivation layer and the conductive pads122, the post-passivation layer includes contact openings, and the conductive pads122are partially revealed from the contact openings defined in the post passivation layer. The post-passivation layer may be a polyimide (PI) layer, a PBO layer, or a dielectric layer formed by other suitable organic dielectric materials. In some alternative embodiments, the post-passivation layer is omitted.

In some embodiments, a wafer level bumping process is performed on the interconnect structure120of the semiconductor wafer W1such that conductive terminals124are formed on the conductive pads122. The conductive pads122of the interconnect structure120may be bump pads, and the conductive terminals124may be micro bumps landing on the conductive pads122. The wafer level bumping process may include: forming a patterned photoresist over the front surface or active surface of the semiconductor wafer W1, wherein the patterned photoresist includes openings for revealing the conductive pads122; depositing (e.g., plating) conductive material on the conductive pads122to form the conductive terminals124in the openings defined in the patterned photoresist; and removing the patterned photoresist. In some embodiments, the conductive terminals124may include Cu/Ni/Au bumps, Cu/Ni bumps, Cu/Ni/Au/SnAg bumps, Cu/Ni/SnAg bumps, or the like.

As illustrated inFIG.1A, after forming the conductive terminals124, a bevel cutting process is performed to form V-shaped grooves G on the front surface of the semiconductor wafer W1. The V-shaped grooves G may be formed by a wafer dicing process performed along scribe lines of the semiconductor wafer W1. The V-shaped grooves G may be formed through a V-shaped dicing blade B1. In some embodiments, the depth of the V-shaped grooves G is smaller than the thickness of the interconnect structure120, wherein the depth of the V-shaped grooves G ranges from about 5 micrometers to about 20 micrometers, and the width of the V-shaped grooves G ranges from about 10 micrometers to about 100 micrometers. In some alternative embodiments, the depth of the V-shaped grooves G is greater than the thickness of the interconnect structure120, wherein the depth of the V-shaped grooves G ranges from about 20 micrometers to about 700 micrometers, and the width of the V-shaped grooves G ranges from about 100 micrometers to about 1000 micrometers.

Referring toFIG.1BandFIG.1C, after performing the bevel cutting process, a full cutting process is performed along the V-shaped grooves G on the front surface of the semiconductor wafer W1such that singulated semiconductor dies100are obtained. Each singulated semiconductor dies100includes a semiconductor substrate110a, an interconnect structure120adisposed on the semiconductor substrate110a, conductive pads122, and conductive terminals124in some embodiments. Each singulated semiconductor dies100includes chamfered edges CE, and the chamfered edges CE are distributed at a periphery region of the front surface of each semiconductor die100in some embodiments. In some alternative embodiments, the chamfered edges CE are distributed at side walls of the semiconductor die100facing a supporting substrate. The full cutting process may be performed through a dicing blade B2along the V-shaped grooves G1formed on the semiconductor wafer W1. The width of the dicing blade B2is smaller than the width of the V-shaped grooves G. In some embodiments, the semiconductor wafer W1is attached onto a dicing tape (not shown) before performing the full cutting process.

In top views of the semiconductor die100, as illustrated inFIGS.7A through7E, at least one chamfered edge CE are distributed at one or more side walls of the semiconductor die100. As illustrated inFIG.7A, only one chamfered edge CE is distributed along one side wall of the semiconductor die100. As illustrated inFIG.7B, two adjoined chamfered edges CE are distributed along two neighboring side walls of the semiconductor die100. As illustrated inFIG.7C, two chamfered edges CE are distributed along two opposite side walls of the semiconductor die100. As illustrated inFIG.7D, three adjoined chamfered edges CE are distributed along three neighboring side walls of the semiconductor die100. As illustrated inFIG.7E, four adjoined chamfered edges CE are distributed along four side walls of the semiconductor die100.

FIGS.2A through2Dare cross-sectional views schematically illustrating a fabrication process of semiconductor dies in accordance with some alternative embodiments of the present disclosure.

Referring toFIGS.2A through2DandFIGS.1A through1C, the fabrication process illustrated inFIGS.2A through2Dare similar to the fabrication process illustrated inFIGS.1A through1Cexcept that two bevel cutting processes are performed before the full cutting process. As illustrated inFIG.2AandFIG.2B, a first bevel cutting process is performed to form first V-shaped grooves G1on the front surface of the semiconductor wafer W1. After the first V-shaped grooves are formed, a second bevel cutting process is performed along the first V-shaped grooves G1to form second V-shaped grooves G2on the front surface of the semiconductor wafer W1. The first V-shaped grooves G1and the second V-shaped grooves G2may be formed by two wafer dicing processes performed along scribe lines of the semiconductor wafer W1. The first V-shaped grooves G1may be formed through a V-shaped dicing blade B1, and the second V-shaped grooves G2may be formed through another V-shaped dicing blade B1′. The depth of the second V-shaped grooves G2is greater than the depth of the first V-shaped grooves G1, and the width of the first V-shaped grooves G1is greater than the width of the second V-shaped grooves G2. In some embodiments, the depth of the first V-shaped grooves G1ranges from about 5 micrometers to about 700 micrometers, the width of the V-shaped grooves G1ranges from about 10 micrometers to about 1000 micrometers, the depth of the V-shaped grooves G2ranges from about 5 micrometers to about 700 micrometers, and the width of the V-shaped grooves G2ranges from about 10 micrometers to about 900 micrometers.

Referring toFIG.2CandFIG.2D, after performing the first and second bevel cutting processes, a full cutting process is performed along the first V-shaped grooves G1and the second V-shaped grooves G2distributed on the front surface of the semiconductor wafer W1such that singulated semiconductor dies100aare obtained. Each singulated semiconductor dies100aincludes a semiconductor substrate110a, an interconnect structure120adisposed on the semiconductor substrate110a, conductive pads122, and conductive terminals124in some embodiments. Each singulated semiconductor dies100aincludes chamfered edges CE′, and the chamfered edges CE′ are distributed at a periphery region of the front surface of each semiconductor die100ain some embodiments. The full cutting process may be performed through a dicing blade B2along the first and second V-shaped grooves G1and G2formed on the semiconductor wafer W1. The width of the dicing blade B2is smaller than the width of the first and second V-shaped grooves G1and G2. In some embodiments, the semiconductor wafer W1is attached onto a dicing tape (not shown) before performing the full cutting process.

FIGS.3A through3Gare cross-sectional views schematically illustrating a fabrication process of a Chip-on-Wafer-on-Substrate (CoWoS) package structure in accordance with some embodiments of the present disclosure.

Referring toFIG.3AthroughFIG.3C, a carrier C is provided and an organic interposer substrate210is formed over the carrier C. In some embodiments, the wafer form organic interposer substrate210is formed over a wafer form carrier C (e.g., a silicon wafer). The organic interposer substrate210may include stacked organic dielectric layers212and conductive wirings214between the stacked organic dielectric layers212. The stacked organic dielectric layers212are stacked over the carrier C. The conductive wirings214are embedded in the stacked organic dielectric layers212carried by the carrier C. In some embodiments, a coefficient of thermal expansion of the stacked organic dielectric layers212is greater than a coefficient of thermal expansion of a semiconductor substrate110of the semiconductor die100.

As illustrated inFIG.3A, a first organic dielectric layer212ais formed over the carrier C. The first organic dielectric layer212amay include openings and portions of the carrier C are revealed by the openings defined in the first organic dielectric layer212a. In some embodiments, the material of the first organic dielectric layer212aincludes polybenzoxazole (PBO), polyimide (PI) or other suitable polymer dielectric material. In some alternative embodiments, the material of the first organic dielectric layer212aincludes resin mixed with filler. The first organic dielectric layer212amay be formed by photo-patternable material and patterned by a photolithography process.

As illustrated inFIG.3B, a seed layer S is formed over the carrier C to cover the first organic dielectric layer212aand the portions of the carriers C which are revealed by the openings defined in the first organic dielectric layer212a. The seed layer S may be sputter Ti/Cu seed layer which entirely covers the first dielectric layer112a. After forming the seed layer S, a patterned photoresist layer PR is formed on the seed layer S. The patterned photoresist layer PR includes trenches, and portions of the seed layer S are revealed by the trenches defined in the patterned photoresist layer PR. After the patterned photoresist layer PR is formed on the seed layer S, a plating process may be performed by using the patterned photoresist layer PR as a mask such that first conductive wirings214aare plated in the trench and cover the revealed portions of the seed layer S.

After forming the first conductive wirings214a, the patterned photoresist layer PR is removed such that portions of the seed layer S that are not covered by the first conductive wirings214aare revealed, and a patterned seed layer S′ is formed under the first conductive wirings214a. An etching process may be performed to remove the portions of the seed layer S that are not covered by the first conductive wirings214auntil portions of the first organic dielectric layer212aare revealed. As illustrated inFIG.3B, the first conductive wirings214aand the patterned seed layer S′ may be considered as a layer of conductive wirings.

As illustrated inFIG.3C, after the first organic dielectric layer212aand the first conductive wirings214aare formed, a second organic dielectric layer212b, second conductive wirings214b, a third organic dielectric layer212c, third conductive wirings214cand a fourth organic dielectric layer212dmay be formed over the carrier C such that the organic interposer substrate210is formed. The fabrication process of the second organic dielectric layer212b, the third organic dielectric layer212cand the fourth organic dielectric layer212dmay be similar to that of the first organic dielectric layer212a. The fabrication process of the second conductive wirings214band the third conductive wirings214cmay be similar to that of the first conductive wirings214a. The number of the stacked organic dielectric layers212and the conductive wirings214in the organic interposer substrate210may be modified in accordance with design rule of products. The conductive wirings214may include conductive wirings and conductive vias electrically connected between conductive wirings, wherein the conductive wirings may transmit signal horizontally, and the conductive vias may transmit signal vertically. The material of the conductive wirings214may include copper or other suitable metallic materials.

Referring toFIG.3D, after the organic interposer substrate210is formed over the carrier C, at least one semiconductor die100(shown inFIG.1C) and at least one semiconductor device220are provided and mounted onto the organic interposer substrate210through, for example, a chip-on-wafer (CoW) bonding process. The at least one semiconductor die100and the at least one semiconductor device220are electrically connected to the organic interposer substrate210through bump joints. Conductive terminals124of the semiconductor dies100and conductive terminals222of the at least one semiconductor device220may be electrically connected to the third conductive wirings214cof the organic interposer substrate210. In some embodiments, the conductive terminals124include Cu/Ni/Au bumps, Cu/Ni bumps, Cu/Ni/Au/SnAg bumps, Cu/Ni/SnAg bumps, or the like, and the conductive terminals222include Cu/Ni/Au bumps, Cu/Ni bumps, Cu/Ni/Au/SnAg bumps, Cu/Ni/SnAg bumps, or the like. The structure of the conductive terminals124may be the same as or different from that of the conductive terminals222. The at least one semiconductor die100may include logic dies, and the at least one semiconductor device220may include memory device. In some alternative embodiments, the at least one semiconductor die100includes system-on-chip (SOC) logic die, and the at least one semiconductor device220includes a high bandwidth memory (HBM) cube, wherein the HBM cube at least includes stacked memory dies. In some alternative embodiments, the semiconductor die100may include system-on-integrated-chips (SoIC) structure or application specific integrated circuit (ASIC) die.

Referring toFIG.3E, an underfill230is formed over the organic interposer substrate210. The underfill230fills the space between the organic interposer substrate210and the semiconductor die100and the space between the organic interposer substrate210and semiconductor device220such that the conductive terminals124and the conductive terminals222are laterally encapsulated by the underfill230. The underfill230may serve as stress buffer to improve the reliability of the conductive terminals124and222. Accordingly, electrical connection between the organic interposer substrate210and semiconductor die100as well as electrical connection between the organic interposer substrate210and the semiconductor device220may be ensured.

As illustrated inFIG.3E, an insulating encapsulation240is formed on the organic interposer substrate210to cover the semiconductor die100, the semiconductor device220, and the underfill230. The insulating encapsulation240may be formed by an over-molding process or a film deposition process. After performing the over-molding process or film deposition process for forming the insulating encapsulation240, as illustrated inFIG.3E, a grinding process may be performed to partially remove the insulating encapsulation240. After performing the grinding process, the thickness of the insulating encapsulation240is reduced. After performing the grinding process, the semiconductor die100, the semiconductor device220and the underfill230are revealed. In some embodiments, the grinding process includes a mechanical grinding process, a CMP process, or combinations thereof. For example, the material of the insulating encapsulation240includes epoxy molding compound or other suitable dielectric materials.

Referring toFIG.3EandFIG.3F, a removal process is performed to remove the carrier C from the organic interposer substrate210such that a back surface of the organic interposer substrate210is revealed. In some embodiments, the removal process of the carrier C includes a mechanical grinding process, a CMP process, an etching process, combinations thereof or other suitable removal processes. After performing the removal process of the carrier C, a wafer level bumping process is performed on the organic interposer substrate210such that conductive terminals250are formed on the first conductive wirings214aof the organic interposer substrate210. The above-mentioned wafer level bumping process may include: forming a patterned photoresist over the back surface of the organic interposer substrate210, wherein the patterned photoresist includes openings for revealing the first conductive wirings214a; depositing (e.g., plating) conductive material on the first conductive wirings214ato form the conductive terminals250in the openings defined in the patterned photoresist; and removing the patterned photoresist. In some embodiments, the conductive terminals250may include controlled collapse chip connection (C4) bumps or the like.

As illustrated inFIG.3EandFIG.3F, a singulation process is performed along scribe lines SL to singulate the resultant structure illustrated inFIG.3E. During the above-mentioned singulation process, the organic interposer substrate210and the insulating encapsulation240are cut-off along the scribe lines SL.

Referring toFIG.3FandFIG.3G, after the singulation process is performed, a singulated structure including an organic interposer substrate210, a semiconductor die100having chamfered edges CE, a semiconductor device220, conductive terminals (e.g., bumps)124and conductive terminals (e.g., bumps)222, an underfill230, an insulating encapsulation240a, and conductive terminals250is obtained and flipped onto an upper surface of a circuit substrate270(e.g., printed circuit board). The organic interposer substrate210of the singulated structure is electrically connected to the circuit substrate270through the conductive terminals250. A reflow process may be performed to reflow the conductive terminals250and bond the organic interposer substrate210of the singulated structure with the circuit substrate270. Then, an underfill260is formed over the circuit substrate270. The underfill260fills the space between the organic interposer substrate210and the circuit substrate270such that the conductive terminals250are laterally encapsulated by the underfill260. The underfill260may serve as stress buffer to improve the reliability of the conductive terminals250. Accordingly, electrical connection between the organic interposer substrate210and the circuit substrate270may be ensured.

The insulating encapsulation240acovers the organic interposer substrate210and laterally encapsulates the semiconductor die100and the underfill230. In some embodiments, sidewalls of the insulating encapsulation240aare substantially aligned with sidewalls of the organic interposer substrate210. The top surface of the insulating encapsulation240amay be substantially level with the back surface of the semiconductor die100and the back surface of the semiconductor device220. In some embodiments, the circuit substrate270further includes conductive terminals272distributed on a bottom surface thereof. The conductive terminals272may be ball grid array (BGA) balls. The material of the conductive terminals272may include solder material or the like.

As illustrated inFIG.3G, the underfill230laterally encapsulates the conductive terminals124and the conductive terminals222, and the underfill230is in direct contact with the chamfered edges CE of the semiconductor die100. Since the semiconductor die100includes the chamfered edges CE (e.g., bevel surfaces), stress issue between the underfill230and the semiconductor die100may be improved. The details of the chamfered edges CE are described as followings in accompany withFIGS.4A through4D,FIGS.5A through5D, andFIGS.6A through6C.

FIGS.4A through4Dare cross-sectional views schematically illustrating various chamfered edges or rounded edges in accordance with some embodiments of the present disclosure.

Referring toFIG.4A, the width D of the chamfered edges CE may range from about 5 micrometers to about 500 micrometers, and the height H of the chamfered edges CE may range from about 5 micrometers to about 700 micrometers. In some embodiments, at least one chamfered edge among the chamfered edges CE includes a slanted surface or bevel surface SS extending between a root surface RS (the sidewall of the semiconductor die100) and a front surface FS of the semiconductor die100. The underfill230is in direct contact with a portion of the root surface RS, the slanted surface SS, and the front surface FS of the semiconductor die100. The slanted surface SS of the chamfered edge CE is spaced apart from the insulating encapsulation240a(shown inFIG.3G) by the underfill230. In other words, the slanted surface SS of the chamfered edge CE is not in contact with the insulating encapsulation240a(shown inFIG.3G). An exterior angle θ1between the slanted surface SS of the chamfered edge CE and the front surface FS of the semiconductor die100may range from about 5 degree to about 80 degree.

Referring toFIG.4B, the width D of the chamfered edges CE may range from about 5 micrometers to about 500 micrometers, and the height H of the chamfered edges CE may range from about 5 micrometers to about 700 micrometers. In some embodiments, at least one chamfered edge among the chamfered edges CE includes two connected slanted surfaces (e.g., bevel surfaces) SS1and SS2extending between a root surface RS (the sidewall of the semiconductor die100) and a front surface FS of the semiconductor die100. The underfill230is in direct contact with a portion of the root surface RS, the slanted surfaces SS1and SS2of the chamfered edge CE, and the front surface FS of the semiconductor die100. The slanted surfaces SS1and SS2of the chamfered edge CE are spaced apart from the insulating encapsulation240a(shown inFIG.3G) by the underfill230. In other words, the slanted surfaces SS1and SS2of the chamfered edge CE are not in contact with the insulating encapsulation240a(shown inFIG.3G). An exterior angle θ1between the slanted surface SS1of the chamfered edge CE and the front surface FS of the semiconductor die100may range from about 5 degree to about 85 degree, and an exterior angle θ2between the slanted surface SS2of the chamfered edge CE and a virtual plane VP1paralleled with the front surface FS of the semiconductor die100may range from about 5 degree to about 85 degree. The exterior angle θ2is greater than the exterior angle θ1.

Referring toFIG.4C, the width D of the chamfered edges CE may range from about 5 micrometers to about 500 micrometers, and the height H of the chamfered edges CE may range from about 5 micrometers to about 700 micrometers. In some embodiments, at least one chamfered edge among the chamfered edges CE includes three connected slanted surfaces (e.g., bevel surfaces) SS1, SS2and SS3extending between a root surface RS (the sidewall of the semiconductor die100) and a front surface FS of the semiconductor die100. The underfill230is in direct contact with a portion of the root surface RS, the slanted surfaces SS1, SS2and SS3of the chamfered edge CE, and the front surface FS of the semiconductor die100. The slanted surfaces SS1, SS2and SS3of the chamfered edge CE are spaced apart from the insulating encapsulation240a(shown inFIG.3G) by the underfill230. In other words, the slanted surfaces SS1, SS2and SS3of the chamfered edge CE are not in contact with the insulating encapsulation240a(shown inFIG.3G). An exterior angle θ1between the slanted surface SS1of the chamfered edge CE and the front surface FS of the semiconductor die100may range from about 5 degree to about 85 degree, an exterior angle θ2between the slanted surface SS2of the chamfered edge CE and a virtual plane VP1paralleled with the front surface FS of the semiconductor die100may range from about 5 degree to about 85 degree, and an exterior angle θ3between the slanted surface SS3of the chamfered edge CE and a virtual plane VP2paralleled with the front surface FS of the semiconductor die100may range from about 5 degree to about 85 degree. The exterior angle θ3is greater than the exterior angle θ2, and the exterior angle θ2is greater than the exterior angle θ1.

Referring toFIG.4D, the semiconductor die100includes rounded edges RE. The width D of the rounded edges RE may range from about 5 micrometers to about 500 micrometers, and the height H of the rounded edges RE may range from about 5 micrometers to about 700 micrometers. In some embodiments, each of the rounded edges RE extends between a root surface RS (the side surface of the semiconductor die100) and a front surface FS of the semiconductor die100. The underfill230is in direct contact with a portion of the root surface RS, the rounded edge RE, and the front surface FS of the semiconductor die100. The rounded edge RE is spaced apart from the insulating encapsulation240a(shown inFIG.3G) by the underfill230. In other words, the rounded edge RE is not in contact with the insulating encapsulation240a(shown inFIG.3G). Since the semiconductor die100includes the rounded edge RE, stress issue between the underfill230and the semiconductor die100may be improved.

FIGS.5A through5Dare cross-sectional views schematically illustrating various chamfered edges or rounded edges in accordance with some alternative embodiments of the present disclosure.

Referring toFIG.5A, the width D of the chamfered edges CE may range from about 5 micrometers to about 500 micrometers, and the height H of the chamfered edges CE may range from about 5 micrometers to about 700 micrometers. In some embodiments, at least one chamfered edge among the chamfered edges CE includes a slanted surface SS extending between a root surface RS (the sidewall of the semiconductor die100) and a front surface FS of the semiconductor die100. The underfill230is in direct contact with a lower portion of the slanted surface SS and the front surface FS of the semiconductor die100. The insulating encapsulation240ais in direct contact with an upper portion of the slanted surface SS and the root surface RS of the semiconductor die100. The slanted surface SS is in direct contact with both the underfill230and the insulating encapsulation240a. An exterior angle θ1between the slanted surface SS of the chamfered edge CE and the front surface FS of the semiconductor die100may range from about 5 degree to about 85 degree.

Referring toFIG.5B, the width D of the chamfered edges CE may range from about 5 micrometers to about 500 micrometers, and the height H of the chamfered edges CE may range from about 5 micrometers to about 700 micrometers. In some embodiments, at least one chamfered edge among the chamfered edges CE includes two connected slanted surfaces SS1and SS2extending between a root surface RS (the sidewall of the semiconductor die100) and a front surface FS of the semiconductor die100. The underfill230is in direct contact with the front surface FS of the semiconductor die100, the slanted surface SS1, and a lower portion of the slanted surface SS2. The insulating encapsulation240ais in direct contact with an upper portion of the slanted surface SS2and the root surface RS of the semiconductor die100. The slanted surface SS2is in direct contact with both the underfill230and the insulating encapsulation240a. An exterior angle θ1between the slanted surface SS1of the chamfered edge CE and the front surface FS of the semiconductor die100may range from about 5 degree to about 85 degree, and an exterior angle θ2between the slanted surface SS2of the chamfered edge CE and a virtual plane VP1paralleled with the front surface FS of the semiconductor die100may range from about 5 degree to about 85 degree. The exterior angle θ2is greater than the exterior angle θ1.

Referring toFIG.5C, the width D of the chamfered edges CE may range from about 5 micrometers to about 500 micrometers, and the height H of the chamfered edges CE may range from about 5 micrometers to about 700 micrometers. In some embodiments, at least one chamfered edge among the chamfered edges CE includes two connected slanted surfaces SS1and SS2extending between a root surface RS (the sidewall of the semiconductor die100) and a front surface FS of the semiconductor die100. The underfill230is in direct contact with the front surface FS of the semiconductor die100and a lower portion of the slanted surface SS1. The insulating encapsulation240ais in direct contact with an upper portion of the slanted surface SS1, the slanted surface SS2, and the root surface RS of the semiconductor die100. The slanted surface SS1is in direct contact with both the underfill230and the insulating encapsulation240a. An exterior angle θ1between the slanted surface SS1of the chamfered edge CE and the front surface FS of the semiconductor die100may range from about 5 degree to about 85 degree, and an exterior angle θ2between the slanted surface SS2of the chamfered edge CE and a virtual plane VP1paralleled with the front surface FS of the semiconductor die100may range from about 5 degree to about 85 degree. The exterior angle θ2is greater than the exterior angle θ1.

Referring toFIG.5D, the semiconductor die100includes rounded edges RE. The width D of the rounded edges RE may range from about 5 micrometers to about 500 micrometers, and the height H of the rounded edges RE may range from about 5 micrometers to about 700 micrometers. In some embodiments, each of the rounded edges RE extends between a root surface RS (the side surface of the semiconductor die100) and a front surface FS of the semiconductor die100. The underfill230is in direct contact with a lower portion of the rounded edge RE and the front surface FS of the semiconductor die100. The insulating encapsulation240ais in direct contact with an upper portion of the rounded edge RE and the root surface RS of the semiconductor die100. The rounded edge RE is in direct contact with both the underfill230and the insulating encapsulation240a.

FIGS.6A through6Care cross-sectional views schematically illustrating various chamfered edges in accordance with some other embodiments of the present disclosure.

Referring toFIG.6A, the width D of the chamfered edges CE may range from about 5 micrometers to about 500 micrometers, and the height H of the chamfered edges CE may range from about 5 micrometers to about 700 micrometers. In some embodiments, at least one chamfered edge among the chamfered edges CE includes three connected slanted surfaces SS1, SS2and SS3extending between a root surface RS (the sidewall of the semiconductor die100) and a front surface FS of the semiconductor die100. The underfill230is in direct contact with the front surface FS of the semiconductor die100and a lower portion of the slanted surface SS1. The insulating encapsulation240ais in direct contact with an upper portion of the slanted surface SS1, the slanted surface SS2, the slanted surface SS3, and the root surface RS of the semiconductor die100. The insulating encapsulation240aentirely covers the slanted surface SS2and SS3. The slanted surface SS1is in direct contact with both the underfill230and the insulating encapsulation240a. An exterior angle θ1between the slanted surface SS1of the chamfered edge CE and the front surface FS of the semiconductor die100may range from about 5 degree to about 85 degree, an exterior angle θ2between the slanted surface SS2of the chamfered edge CE and a virtual plane VP1paralleled with the front surface FS of the semiconductor die100may range from about 5 degree to about 85 degree, and an exterior angle θ3between the slanted surface SS3of the chamfered edge CE and a virtual plane VP2paralleled with the front surface FS of the semiconductor die100may range from about 5 degree to about 85 degree. The exterior angle θ3is greater than the exterior angle θ2, and the exterior angle θ2is greater than the exterior angle θ1.

Referring toFIG.6B, the width D of the chamfered edges CE may range from about 5 micrometers to about 500 micrometers, and the height H of the chamfered edges CE may range from about 5 micrometers to about 700 micrometers. In some embodiments, at least one chamfered edge among the chamfered edges CE includes three connected slanted surfaces SS1, SS2and SS3extending between a root surface RS (the sidewall of the semiconductor die100) and a front surface FS of the semiconductor die100. The underfill230is in direct contact with the front surface FS of the semiconductor die100, the slanted surface SS1, and a lower portion of the slanted surface SS2. The insulating encapsulation240ais in direct contact with an upper portion of the slanted surface SS2, the slanted surface SS3, and the root surface RS of the semiconductor die100. The underfill230may entirely cover the slanted surface SS1. The slanted surface SS2is in direct contact with both the underfill230and the insulating encapsulation240a. An exterior angle θ1between the slanted surface SS1of the chamfered edge CE and the front surface FS of the semiconductor die100may range from about 5 degree to about 85 degree, an exterior angle θ2between the slanted surface SS2of the chamfered edge CE and a virtual plane VP1paralleled with the front surface FS of the semiconductor die100may range from about 5 degree to about 85 degree, and an exterior angle θ3between the slanted surface SS3of the chamfered edge CE and a virtual plane VP2paralleled with the front surface FS of the semiconductor die100may range from about 5 degree to about 85 degree. The exterior angle θ3is greater than the exterior angle θ2, and the exterior angle θ2is greater than the exterior angle θ1.

Referring toFIG.6C, the width D of the chamfered edges CE may range from about 5 micrometers to about 500 micrometers, and the height H of the chamfered edges CE may range from about 5 micrometers to about 700 micrometers. In some embodiments, at least one chamfered edge among the chamfered edges CE includes three connected slanted surfaces SS1, SS2and SS3extending between a root surface RS (the sidewall of the semiconductor die100) and a front surface FS of the semiconductor die100. The underfill230is in direct contact with the front surface FS of the semiconductor die100, the slanted surface SS1, the slanted surface SS2, and a lower portion of the slanted surface SS3. The underfill230may entirely cover the slanted surfaces SS1and SS2. The insulating encapsulation240ais in direct contact with an upper portion of the slanted surface SS3and the root surface RS of the semiconductor die100. The slanted surface SS3is in direct contact with both the underfill230and the insulating encapsulation240a. An exterior angle θ1between the slanted surface SS1of the chamfered edge CE and the front surface FS of the semiconductor die100may range from about 5 degree to about 85 degree, an exterior angle θ2between the slanted surface SS2of the chamfered edge CE and a virtual plane VP1paralleled with the front surface FS of the semiconductor die100may range from about 5 degree to about 85 degree, and an exterior angle θ3between the slanted surface SS3of the chamfered edge CE and a virtual plane VP2paralleled with the front surface FS of the semiconductor die100may range from about 5 degree to about 85 degree. The exterior angle θ3is greater than the exterior angle θ2, and the exterior angle θ2is greater than the exterior angle θ1.

In accordance with some embodiments of the disclosure, a package structure including an organic interposer substrate, a semiconductor die, conductive bumps, a first underfill, and an insulating encapsulation is provided. The organic interposer substrate includes stacked organic dielectric layers and conductive wirings embedded in the stacked organic dielectric layers. The semiconductor die is disposed over and electrically connected to the conductive wirings of the organic interposer substrate, and the semiconductor die includes chamfered edges. The conductive bumps are disposed between the semiconductor die and the organic interposer substrate, and the semiconductor die is electrically connected to the organic interposer substrate through the conductive bumps. The first underfill is disposed between the semiconductor die and the organic interposer substrate, wherein the first underfill encapsulates the conductive bumps and is in contact with the chamfered edges of the at least one semiconductor die. The insulating encapsulation covers the organic interposer substrate and laterally encapsulates the least one semiconductor die and the first underfill. In some embodiments, a width of the chamfered edges ranges from about 5 micrometers to about 500 micrometers, and a height of the chamfered edges ranges from about 5 micrometers to about 700 micrometers. In some embodiments, at least one chamfered edge among the chamfered edges comprises at least one slanted surface extending between a root surface and a front surface of the semiconductor die, and the first underfill is in contact with the slanted surfaces of the chamfered edges. In some embodiments, the first underfill is further in contact with first portions of the root surfaces, and the insulating encapsulation is in contact with second portions of the root surfaces. In some embodiments, at least one chamfered edge among the chamfered edges comprises at least one slanted surface extending between a root surface and a front surface of the semiconductor die, the first underfill is in contact with first portions of the slanted surfaces of the chamfered edges, and the insulating encapsulation is in contact with second portions of the slanted surfaces of the chamfered edges. In some embodiments, at least one chamfered edge among the chamfered edges comprises a first slanted surface and a second slanted surface, the first slanted surface extends between a front surface of the semiconductor die and the second slanted surface, the second slanted surface extends between the first slanted surface and a root surface, the first slanted surface is entirely covered by the first underfill, the second slanted surface is in contact with the first underfill and the insulating encapsulation. In some embodiments, sidewalls of the insulating encapsulation are substantially aligned with sidewalls of the organic interposer substrate. In some embodiments, a coefficient of thermal expansion of the stacked organic dielectric layers is greater than a coefficient of thermal expansion of a semiconductor substrate of the semiconductor die. In some embodiments, the package structure further includes a circuit substrate; first conductive terminals disposed on and electrically connected to the circuit substrate; second conductive terminals disposed on and electrically connected to the circuit substrate; and a second underfill disposed between the organic interposer substrate and the circuit substrate. The organic interposer substrate is electrically connected to the circuit substrate through the first conductive terminals, and the first conductive terminals and the second conductive terminals are disposed on opposite sides of the circuit substrate. The second underfill encapsulates the first conductive terminals.

In accordance with some other embodiments of the disclosure, a package structure including an interposer substrate, a semiconductor die, conductive bumps, and an underfill is provided. The interposer substrate includes stacked dielectric layers and conductive wirings embedded in the stacked dielectric layers. The semiconductor die is disposed over and electrically connected to the interposer substrate, and a coefficient of thermal expansion of the stacked dielectric layers being greater than a coefficient of thermal expansion of a semiconductor substrate of the semiconductor die. The semiconductor die comprises chamfered edges, and at least one chamfered edge among the chamfered edges comprises bevel surfaces. The conductive bumps are disposed between the semiconductor die and the interposer substrate, and the semiconductor die is electrically connected to the interposer substrate through the conductive bumps. The underfill is disposed between the semiconductor die and the interposer substrate. In some embodiments, a width of the chamfered edges ranges from about 5 micrometers to about 500 micrometers, and a height of the chamfered edges ranges from about 5 micrometers to about 700 micrometers. In some embodiments, the underfill is in contact with the bevel surfaces of the chamfered edges and the root surfaces. In some embodiments, sidewalls of the insulating encapsulation are substantially aligned with sidewalls of the interposer substrate. In some embodiments, the package structure further includes a circuit substrate, wherein the interposer substrate is electrically connected to the circuit substrate.

In accordance with some other embodiments of the disclosure, a package structure including an organic interposer substrate, a semiconductor die, conductive bumps, and a first underfill is provided. The organic interposer substrate includes stacked organic dielectric layers and conductive wirings embedded in the stacked organic dielectric layers. The semiconductor die is disposed over and electrically connected to the conductive wirings of the organic interposer substrate, and the semiconductor die includes rounded edges. The conductive bumps are disposed between the semiconductor die and the organic interposer substrate, and the semiconductor die is electrically connected to the organic interposer substrate through the conductive bumps. The first underfill is disposed between the semiconductor die and the organic interposer substrate. In some embodiments, each of the rounded edges extends between a front surface of the semiconductor die and a side surface of the semiconductor die, and the first underfill is in contact with the rounded edges. In some embodiments, the package structure further includes an insulating encapsulation covering the organic interposer substrate and laterally encapsulating the least one semiconductor die and the first underfill, wherein the rounded edges of the semiconductor die being spaced apart from the insulating encapsulation by the first underfill. In some embodiments, the first underfill is further in contact with first portions of the side surfaces of the semiconductor die, and the insulating encapsulation is in contact with second portions of the side surfaces of the semiconductor die. In some embodiments, sidewalls of the insulating encapsulation are substantially aligned with sidewalls of the organic interposer substrate. In some embodiments, the package structure further includes a circuit substrate, first conductive terminals, second conductive terminals and a second underfill. The first conductive terminals are disposed on and electrically connected to the circuit substrate. The second conductive terminals are disposed on and electrically connected to the circuit substrate, wherein the organic interposer substrate is electrically connected to the circuit substrate through the first conductive terminals, and the first conductive terminals and the second conductive terminals are disposed on opposite sides of the circuit substrate. The second underfill disposed between the organic interposer substrate and the circuit substrate, wherein the second underfill encapsulates the first conductive terminals.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.