Patent ID: 12236838

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

For making the purposes, technical solutions and effects of the present disclosure be clearer and more definite, the present disclosure will be further described in detail below. It should be understood that the specific embodiments described herein are merely for explaining the present disclosure and are not intended to limit the present disclosure.

As illustrated inFIG.1, this embodiment provides a demultiplexing circuit, including at least an N−1th stage demultiplexing subcircuit100and an Nth stage demultiplexing subcircuit200. The N−1th stage demultiplexing subcircuit100includes at least M N−1th stage demultiplexing units10configured to respond to N−1th stage control signals to time-sharingly output corresponding N−1th stage data signals. The Nth stage demultiplexing subcircuit200includes at least M+1 Nth stage demultiplexing units20. An input terminal of the Nth stage demultiplexing subcircuit200is connected to an output terminal of the N−1th stage demultiplexing subcircuit100, configured to respond to Nth stage control signals to time-sharingly output corresponding Nth stage data signals. Wherein, an output terminal of one N−1th stage demultiplexing unit10is connected to at least two input terminals of the Nth stage demultiplexing units20, and M and N are both integers not less than 2.

It can be understood that one N−2th stage data signal is configured to be received by input terminals of at least two N−1th stage demultiplexing units10, and a corresponding part of the N−2th stage data signal is time-sharingly outputted as M N−1th stage data signals from corresponding N−1th stage demultiplexing units10sequentially under time sharing control of corresponding or different N−1th stage control signals. An output terminal of at least one of the N−1th stage demultiplexing units10is connected to output terminals of two Nth stage demultiplexing units20, and one of the N−1th data signals is time-sharingly outputted as at least two Nth stage data signals by at least two Nth stage demultiplexing units20under time sharing control of corresponding or different Nth stage control signals, that is, the corresponding Nth stage demultiplexing units20time-sharingly output at least M+1 Nth stage data signals in sequence. That is, after one N−2th stage data signal is processed by the demultiplexing circuit of this embodiment, at least M+1 Nth stage data signals are outputted time-sharingly. Compared to circuits of a same type in the prior art, the present disclosure can time-sharingly output a same input signal as more input signals and even effect fission, triggering geometric growth, which can further reduce a number of wirings for transmitting input signals, thereby reducing a space occupied thereof. Furthermore, when N is equal to 2, the N−2th stage data signal is an initial data signal; that is, the data signal before being inputted into the demultiplexing circuit provided by this embodiment. The initial data signal is correspondingly connected to an input terminal of a first-stage demultiplexing circuit. When a corresponding initial data signal is processed by the demultiplexing circuit provided by this embodiment, data signals DS outputted from the last stage demultiplexing circuit are required to be written into corresponding subpixels for display.

In one embodiment, the Nth stage demultiplexing subcircuit200includes at least 2M Nth stage demultiplexing units20. An input terminal of one N−1th stage demultiplexing unit10is at least connected to an input terminal of another N−1th stage demultiplexing unit10. Different N−1th stage demultiplexing units respond to different N−1th stage control signals. An input terminal of one Nth stage demultiplexing unit20is at least connected to an input terminal of another Nth stage demultiplexing unit20. Different Nth stage demultiplexing units20respond to different Nth stage control signals.

It can be understood that in this embodiment, after a same input signal is processed by the demultiplexing circuit, at least MNinput signals can be outputted time-sharingly in sequence, realizing fission of geometric growth of the input signals to further reduce the number of wirings of the input signals.

Furthermore, the N−1th stage demultiplexing units10include N−1th stage thin film transistors T1. Input terminals of at least two N−1th stage thin film transistors T1are correspondingly configured to receive one input signal. A control terminal of each N−1th stage thin film transistor T1is correspondingly configured to receive one N−1th stage control signal.

Wherein, the Nth stage demultiplexing units20include Nth stage thin film transistors T2. Input terminals of at least two Nth stage thin film transistors are connected to the output terminal of one N−1th stage thin film transistor T1. A control terminal of each Nth stage thin film transistor T2is correspondingly configured to receive one Nth stage control signal.

It should be noted that the input terminal of a thin film transistor can be one of a drain electrode or a source electrode of a corresponding thin film transistor. An output terminal of the corresponding thin film transistor can be another drain electrode or source electrode thereof, and the control terminals of the corresponding thin film transistor can be a gate electrode thereof.

It should be noted that a type of channels of the N−1th stage thin film transistor T1and the Nth stage thin film transistor T2can be, but are not necessarily, same. For example, the channel types of the N−1th stage thin film transistor T1and the Nth stage thin film transistor T2can both be N-channel type thin film transistors or P-channel type thin film transistors. The channel types of the N−1th stage thin film transistor T1and the Nth stage thin film transistor T2can be different. For example, the channel type of the N−1th stage thin film transistor T1can be one of N-channel type thin film transistor or P-channel type thin film transistor, and the channel type of the Nth stage thin film transistor T2can be the other one of the N-channel type thin film transistor or the P-channel type thin film transistor. It can be understood that regardless of the channel types of the N−1th stage thin film transistor T1and the Nth stage thin film transistor, through configuration of corresponding control signals, the corresponding thin film transistors can be controlled to time-sharingly output corresponding input signals in sequence.

In one embodiment, the N−1th stage control signals include at least M N−1th stage control subsignals that are sequentially time sharing and effective. Each of the N−1th stage control subsignals is configured to be received by a control terminal of one N−1th stage thin film transistor T1. It can be understood that each N−1th control subsignal correspondingly controls one N−1th stage thin film transistor T1, allowing it to realize time-sharing output in sequence of corresponding input signals.

In one embodiment, the Nth stage control signals include at least 2M Nth stage control subsignals being sequentially time sharing and effective. Each of the Nth stage control subsignals is configured to be received by a control terminal of one Nth stage thin film transistor T2. It can be understood that each Nth stage control subsignal correspondingly controls one Nth stage thin film transistor T2, allowing it to again realize time sharing output in sequence of corresponding input signals.

In one embodiment, a frequency of the Nth stage control subsignals and a frequency of the N−1th stage control subsignals are same, that is, their periods are same, but duty cycles in one same period are different. For example, a duration of an effective electric potential of the N−1th stage control subsignals can be longer than or equal to two times of a duration of an effective electric potential of the Nth stage control subsignals. The duration of the effective electric potential can be similar or same as a time of turning on a corresponding thin film transistor.

As illustrated inFIG.1andFIG.2, in one embodiment, when M and N are equal to 2, a first-stage demultiplexing subcircuit includes two N−1th stage demultiplexing units10; each N−1th stage demultiplexing unit10includes one N−1th stage thin film transistor T1. A first first-stage control subsignal MUX1controls a first N−1th stage thin film transistor, and a second first-stage subsignal MUX2controls a second N−1th stage thin film transistor. A second-stage demultiplexing subcircuit includes four Nth stage demultiplexing units20. Each Nth stage demultiplexing unit20includes one Nth stage thin film transistor T2. A first second-stage control subsignal MUX3controls a first Nth stage thin film transistor. A second second-stage control subsignal MUX4controls a second Nth stage thin film transistor. A third second-stage control subsignal MUX5controls a third Nth stage thin film transistor. A fourth of second-stage control subsignal MUX6controls a fourth Nth stage thin film transistor. Furthermore, an output terminal of the first N−1th stage thin film transistor and an input terminal of the first Nth stage thin film transistor are connected to an input terminal of the second Nth stage thin film transistor, and an output terminal of a second N−1th stage thin film transistor and an input terminal of a third Nth stage thin film transistor are connected to an input terminal of a fourth Nth stage thin film transistor. Correspondingly, when the input signals are the data signals DS, after they are processed by the demultiplexing circuit, the same data signals DS are time-sharingly and sequentially outputted by the first Nth stage thin film transistor, the second Nth stage thin film transistor, the third Nth stage thin film transistor, and the fourth Nth stage thin film transistor as a first data signal D1, a second data signal D2, a third data signal D3, and a fourth data signal D4. Correspondingly, when a same demultiplexing circuit exists, the demultiplexing circuit time-sharingly outputs a fifth data signal D5, a sixth data signal D6, a seventh data signal D7, and an eighth data signal D8in sequence.

As illustrated inFIG.2, it can be understood that a first first-stage control subsignal MUX1is in an effective electric potential state, when scanning signals S1of odd rows are in a high electric potential time period. For example, the first first-stage control subsignal MUX1is in a low electric potential state, which is able to control a corresponding thin film transistor to turn on. The first second-stage control subsignal MUX3and the second second-stage control subsignals MUX4time-sharingly control corresponding thin film transistors to turn on to time-sharingly output corresponding data signals DS. Then, while scanning signals S2of even rows are in a high electric potential, the second first-stage control subsignal MUX2is in an effective electric potential state—for example, in a low electric potential state. The third second-stage control subsignal MUX5and the fourth second-stage control subsignal MUX6time-sharingly control corresponding thin film transistors to turn on to time-sharingly output the corresponding data signals DS. When a plurality of demultiplexing circuits exist, it can also continue an aforementioned sequence of turning on sequentially and perform a sequential task.

As illustrated inFIG.3, in one embodiment, the present disclosure provides a display panel. A display region AA and a bezel region BB located on a side of the display region AA are disposed in the display panel. A demultiplexing circuit is disposed in the bezel region BB. The demultiplexing circuit includes at least the N−1th stage demultiplexing subcircuit100and the Nth stage demultiplexing subcircuit200. The N−1th stage demultiplexing subcircuit100includes at least M N−1th stage demultiplexing units10configured to response N−1th stage control signals to time-sharingly output corresponding N−1th stage data signals. The Nth stage demultiplexing subcircuit200includes at least M+1 Nth stage demultiplexing units20, and an input terminal of the Nth stage demultiplexing subcircuit200is connected to an output terminal of the N−1th stage demultiplexing subcircuit100for responding to Nth stage control signals to time-sharingly output corresponding Nth stage data signals. The Nth stage demultiplexing subcircuit200includes at least M+1 Nth stage demultiplexing units20, and an input terminal of the Nth stage demultiplexing subcircuit200is connected to an output terminal of the N−1th stage demultiplexing subcircuit100, configured to respond to Nth stage control signals to time-sharingly output corresponding Nth stage data signals. Wherein, an output terminal of one N−1th stage demultiplexing unit10is connected to at least two input terminals of the Nth stage demultiplexing units20, and M and N are both integers not less than 2.

It should be noted that in one embodiment, the bezel region BB is located on a bottom side of the display region AA; that is, when facing the display panel, the bezel region BB is located on the bottom side on the display region AA. At the same time, at least one pad PA can be configured on the bezel region BB for welding transmission lines for corresponding input signals.

It can be understood that by disposing at least two stages of demuxing subcircuits in cascade, the display panel of this embodiment can make one signal time-sharingly multiplex to a plurality of signals, which can exponentially reduce a number of the signal wirings correspondingly, thereby reducing a space occupied thereof.

In one embodiment, the present disclosure provides a driving method of the display panel. The display panel includes at least two demultiplexing circuits, a plurality of subpixels distributed in an array manner, and data lines connected between the demultiplexing circuits and the subpixels. The demultiplexing circuit at least includes the cascaded N−1th stage demultiplexing subcircuit100and Nth stage demultiplexing subcircuit200. As illustrated inFIG.2and/orFIG.4, the driving method includes at least following steps: step S10: synchronously outputting corresponding data signals DS using different demultiplexing circuits; step S20: temporarily storing the data signals in the data lines DS to charge corresponding subpixels in advance; and step S30: responding to corresponding scanning signals and writing the data signals to the subpixels in odd rows and even rows in sequence using the display panel; wherein, N is an integer not less than 2.

It should be noted that in this embodiment, the plurality of demultiplexing circuits work synchronously, being able to synchronously charge the corresponding subpixels in advance, reduce pre-charging time and a number of the transmission lines of control signals of corresponding stages, allowing the plurality of demultiplexing circuits to share a group of the control signals, reducing a number of wirings in bezels and a space occupied thereof, and reducing costs. The output terminals of the demultiplexing circuits are connected to corresponding data lines. One data line is connected to subpixels in a same column or two adjacent columns. Before an effective electric level of the scanning signals is present, the data signals DS are temporarily stored in the data lines. Because parasitic capacitors or coupling capacitors exist between the data lines or adjacent data lines, the data signals DS can be temporarily stored in corresponding capacitors. Until the effective electric level of the scanning signals is present, the data signals DS are written into the corresponding subpixels. The pre-charging function provided by this embodiment can improve charging efficiency of the data signals DS to remedy insufficient charging.

In one embodiment, the display panel responds to corresponding scanning signals; that is, the scanning signals S1of the odd rows sequentially turn on the subpixels of the odd rows. The N−1th stage demultiplexing subcircuit100responds to the N−1th stage control signals to time-sharingly output at least two first data subsignals. The Nth stage demultiplexing subcircuit200responds to the Nth stage control signals to time-sharingly output at least four second data subsignals to the subpixels of corresponding columns. The display panel responds to corresponding scanning signals; that is, the scanning signals S2of the even rows sequentially turn on the subpixels of the even rows. The N−1th stage demultiplexing subcircuit100responds to the N−1th stage control signals to time-sharingly output at least two first data subsignals. The Nth stage demultiplexing subcircuit200responds to the Nth stage control signals to time-sharingly output at least four second data subsignals to the subpixels of corresponding columns. Wherein, N is an integer not less than 2. Furthermore, in the time sequence, the effective electric potential periods of two adjacent Nth stage control subsignals are in the effective electric potential periods of one N−1th stage control subsignals.

It can be understood that by disposing at least two stages of the demuxing subcircuits in cascade, the driving method of the display panel of this embodiment can make one signal time-sharingly multiplex to a plurality of signals, which can exponentially reduce the number of signal wirings correspondingly, thereby reducing a space occupied thereof.

It can be understood, that for those of ordinary skill in the art, various other corresponding changes and modifications can be made according to the technical solutions and technical ideas of the present disclosure, and all such changes and modifications are intended to fall within the scope of protection of the claims of the present disclosure.