Patent ID: 12189894

DETAILED DESCRIPTION OF THE EMBODIMENTS

In this specification, when a component (or, a region, a layer, a part, etc.) is referred to as being “on”, “connected to” or “coupled to” another component, this may mean that the component is directly on, connected to, or coupled to the other component or that a third component is present therebetween.

Identical reference numerals refer to identical components throughout the specification. Additionally, in the drawings, the thicknesses, proportions, and dimensions of components may be exaggerated. As used herein, the term “and/or” includes one or more combinations of the associated components.

Terms such as first, second, and the like may be used to describe various components, but the components should not be limited by the terms. The terms may be used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, the second component may also be referred to as the first component. The terms of a singular form may include plural forms unless otherwise specified.

In addition, terms such as “below”, “under”, “above”, and “over” are used to describe a relationship of components illustrated in the drawings. These terms are relative concepts and are described based on directions illustrated in the drawings.

It should be understood that terms such as “comprise”, “include”, and “have”, when used herein, specify the presence of stated features, numbers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meanings as those generally understood by persons skilled in the art to which the present disclosure pertains. Such terms as those defined in a generally used dictionary are to be interpreted as having meanings equal to the contextual meanings in the relevant field of art, and are not to be interpreted as having ideal or excessively formal meanings unless clearly defined as having such in the present application.

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

FIG.1is a plan view of an electronic device1000according to an embodiment of the present disclosure.

Referring toFIG.1, the electronic device1000may be a device activated in response to an electrical signal. In other words, the electronic device1000may be an electrical signal-activated device. The electronic device1000may be applied to an electronic device such as a mobile phone, a tablet computer, a smart watch, a notebook computer, a smart television, or the like. InFIG.1, a mobile phone is illustrated as an example.

The electronic device1000may display an image IM on a display surface IS parallel to a first direction DR1 and a second direction DR2. The display surface IS, on which the image IM is displayed, may correspond to a front surface of the electronic device1000. The image IM may include a still image as well as a dynamic image. The normal direction of the display surface IS, in other words, the thickness direction of the electronic device1000is indicated by a third direction DR3. Front surfaces (or, upper surfaces) and rear surfaces (or, lower surfaces) of layers or units to be described below are distinguished from each other based on the third direction DR3.

The display surface IS of the electronic device1000may be divided into a display region DA and a peripheral region NDA. The display region DA may be a region on which the image IM is displayed. A user views the image IM through the display region DA. In this embodiment, the display region DA is illustrated in a rounded rectangular shape. However, this is illustrative, and the display region DA may have various shapes and is not limited to any one embodiment.

The peripheral region NDA is adjacent to the display region DA. The peripheral region NDA may have a predetermined color. The peripheral region NDA may be referred to as a non-display region or a bezel region. The peripheral region NDA may surround the display region DA. Accordingly, the shape of the display region DA may be substantially defined by the peripheral region NDA. However, this is illustrative, and the peripheral region NDA may be disposed adjacent to only one side of the display region DA, or may be omitted. The electronic device1000according to an embodiment of the present disclosure may include various embodiments and is not limited to any one embodiment.

FIG.2is a schematic block diagram illustrating an example of the use of the electronic device1000according to an embodiment of the present disclosure.

Referring toFIG.2, the electronic device1000may include a display layer100, a sensor layer200, a display driver100C, a sensor driver200C, a main driver1000C, and a power circuit1000P.

The display layer100may be a component that substantially generates an image. The display layer100may be an emissive display layer. For example, the display layer100may be an organic light emitting display layer, an inorganic light emitting display layer, an organic-inorganic light emitting display layer, a quantum-dot display layer, a micro-light emitting diode (LED) display layer, or a nano-LED display layer.

The sensor layer200may be disposed on the display layer100. For example, the sensor layer200may overlap the display layer100. The sensor layer200may sense an external input applied from the outside. The sensor layer200may be an integrated sensor continuously formed in a manufacturing process of the display layer100. Alternatively, the sensor layer200may be an external sensor attached to the display layer100.

The main driver1000C may control the overall operation of the electronic device1000. For example, the main driver1000C may control operations of the display driver100C and the sensor driver200C. The main driver1000C may include at least one microprocessor. The main driver1000C may be referred to as a host. The main driver1000C may further include a graphics controller.

The display driver100C may drive the display layer100. The display driver100C may receive image data and a control signal from the main driver1000C. The control signal may include various signals. For example, the control signal may include an input vertical synchronization signal, an input horizontal synchronization signal, a main clock, and a data enable signal.

The sensor driver200C may drive the sensor layer200. The sensor driver200C may receive a control signal from the main driver1000C. The control signal may include a clock signal of the sensor driver200C.

The power circuit1000P may include a power management integrated circuit (PMIC). The power circuit1000P may generate a plurality of drive voltages for driving the display layer100, the sensor layer200, the display driver100C, and the sensor driver200C. For example, the plurality of drive voltages may include a gate high-voltage, a gate low-voltage, an ELVSS voltage, an ELVDD voltage, an initialization voltage, and the like, but are not particularly limited to these examples.

The electronic device1000may sense inputs applied from the outside. For example, the electronic device1000may sense a passive input by a touch2000. The touch2000may include all input means, such as a part of the user's body and an input device (e.g., a pen), which are capable of causing a change in capacitance. In other words, the touch2000may encompass any input means capable of altering the capacitance of the touch surface.

FIG.3is a sectional view of the electronic device1000according to an embodiment of the present disclosure. For example,FIG.3may be a sectional view taken along line I-I′ ofFIG.1.

Referring toFIG.3, the electronic device1000may include the display layer100, the sensor layer200, and an anti-reflection layer300. The display layer100may include a base layer110, a barrier layer120, a buffer layer BFL, a circuit layer130, an element layer140, and an encapsulation layer150.

The base layer110may have a single-layer structure or a multi-layer structure. For example, the base layer110may include first, second and third sub-base layers111,112, and113. Each of the first sub-base layer111and the third sub-base layer113may include at least one of a polyimide-based resin, an acrylate-based resin, a methacrylate-based resin, a polyisoprene-based resin, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a celluose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin. A “˜˜”-based resin used herein may mean a resin including a “˜˜” functional group. For example, each of the first sub-base layer111and the third sub-base layer113may include polyimide.

The second sub-base layer112may have a single-layer structure or a multi-layer structure. For example, the second sub-base layer112may include an inorganic material and may include at least one of silicon oxide, silicon nitride, silicon oxy-nitride, and amorphous silicon. For example, the second sub-base layer112may include silicon oxy-nitride and silicon oxide stacked thereon.

The barrier layer120may be disposed on the base layer110. The barrier layer120may have a single-layer structure or a multi-layer structure. The barrier layer120may include at least one of silicon oxide, silicon nitride, silicon oxy-nitride, and amorphous silicon.

The barrier layer120may further include a first lower light blocking layer BML1. For example, when the barrier layer120has a multi-layer structure, the first lower light blocking layer BML1 may be disposed between layers constituting the barrier layer120. However, without being limited thereto, the first lower light blocking layer BML1 may be disposed between the base layer110and the barrier layer120, or may be disposed on the barrier layer120. In an embodiment, the first lower light blocking layer BML1 may be omitted. The first lower light blocking layer BML1 may be referred to as a first lower layer, a first lower metal layer, a first lower electrode layer, a first lower shielding layer, a first light blocking layer, a first metal layer, a first shielding layer, or a first overlap layer.

The buffer layer BFL may be disposed on the barrier layer120. The buffer layer BFL may prevent diffusion of metal atoms or impurities from the base layer110to a first semiconductor pattern. Furthermore, the buffer layer BFL may allow the first semiconductor pattern to be uniformly formed, by adjusting the speed at which heat is provided during a crystallization process for forming the first semiconductor pattern.

The buffer layer BFL may include a plurality of inorganic layers. For example, the buffer layer BFL may include a first sub-buffer layer including silicon nitride and a second sub-buffer layer that is disposed on the first sub-buffer layer and that includes silicon oxide.

The circuit layer130may be disposed on the buffer layer BFL, and the element layer140may be disposed on the circuit layer130. A pixel PX may include a pixel circuit PDC and a light emitting element ED electrically connected to the pixel circuit PDC. The pixel circuit PDC may be included in the circuit layer130, and the light emitting element ED may be included in the element layer140.

A silicon thin film transistor S-TFT and an oxide thin film transistor O-TFT of the pixel circuit PDC are illustrated as an example inFIG.3. However, transistors constituting the pixel circuit PDC may all be silicon thin film transistors S-TFT or oxide thin film transistors O-TFT.

The first semiconductor pattern may be disposed on the buffer layer BFL. The first semiconductor pattern may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon or polycrystalline silicon. For example, the first semiconductor pattern may include low-temperature poly silicon.

FIG.3illustrates only a portion of the first semiconductor pattern disposed on the buffer layer BFL, and the first semiconductor pattern may be additionally disposed in other regions. The first semiconductor pattern may be arranged across pixels according to a specific rule. The first semiconductor pattern may have different electrical properties depending on whether the first semiconductor pattern is doped or not. The first semiconductor pattern may include a first region having a high conductivity and a second region having a low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region that is doped with a P-type dopant, and an N-type transistor may include a doped region that is doped with an N-type dopant. The second region may be an un-doped region, or may be a region more lightly doped than the first region.

The first region may have a higher conductivity than the second region and may substantially serve as an electrode or a signal line. In other words, the first region may function as an electrode or a signal line. The second region may substantially correspond to an active region (or, a channel) of a transistor. In other words, one portion of the first semiconductor pattern may be an active region of the transistor, another portion of the first semiconductor pattern may be a source or drain of the transistor, and yet another portion of the first semiconductor pattern may be a connecting electrode or a connecting signal line.

A source region SE1, an active region AC1, and a drain region DE1 of the silicon thin film transistor S-TFT may be formed from the first semiconductor pattern. The source region SE1 and the drain region DE1 may extend from the active region AC1 in opposite directions on the buffer layer BFL.

InFIG.3, a portion of a connecting signal line CSL formed from the first semiconductor pattern is illustrated.

The circuit layer130may include a plurality of inorganic layers and a plurality of organic layers. In an embodiment, first, second, third, fourth and fifth insulating layers10,20,30,40, and50sequentially stacked on the buffer layer BFL may be inorganic layers, and sixth, seventh and eighth insulating layers60,70, and80may be organic layers.

The first insulating layer10may be disposed on the buffer layer BFL. The first insulating layer10may cover the first semiconductor pattern. The first insulating layer10may be an inorganic layer and/or an organic layer and may have a single-layer structure or a multi-layer structure. The first insulating layer10may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxy-nitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer10may be a single silicon oxide layer. Not only the first insulating layer10but also an insulating layer of the circuit layer130to be described below may have a single-layer structure or a multi-layer structure.

A gate electrode GT1 of the silicon thin film transistor S-TFT may be disposed on the first insulating layer10. The gate electrode GT1 may be a portion of a metal pattern. The gate electrode GT1 may overlap the active region AC1 with a portion of the first insulating layer10therebetween. The gate electrode GT1 may function as a mask in a process of doping the first semiconductor pattern. The gate electrode GT1 may include titanium, silver, an alloy containing silver, molybdenum, an alloy containing molybdenum, aluminum, an alloy containing aluminum, aluminum nitride, tungsten, tungsten nitride, copper, indium tin oxide, or indium zinc oxide, but is not particularly limited thereto.

The second insulating layer20may be disposed on the first insulating layer10and may cover the gate electrode GT1. The second insulating layer20may be an inorganic layer and may have a single-layer structure or a multi-layer structure. The second insulating layer20may include at least one of silicon oxide, silicon nitride, and silicon oxy-nitride. In this embodiment, the second insulating layer20may have a single-layer structure including a silicon nitride layer.

The third insulating layer30may be disposed on the second insulating layer20. The third insulating layer30may be an inorganic layer and may have a single-layer structure or a multi-layer structure. For example, the third insulating layer30may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer. One electrode (or a first electrode) Csta of a capacitor may be disposed between the second insulating layer20and the third insulating layer30. Furthermore, the other electrode (or a second electrode) of the capacitor may be disposed between the first insulating layer10and the second insulating layer20.

A second semiconductor pattern may be disposed on the third insulating layer30. The second semiconductor pattern may include an oxide semiconductor. The oxide semiconductor may include a plurality of regions distinguished from each other depending on whether metal oxide is reduced or not. A region where metal oxide is reduced (hereinafter, referred to as the reduced region) has a higher conductivity than a region where metal oxide is not reduced (hereinafter, referred to as the non-reduced region). The reduced region substantially serves as a source/drain of a transistor or a signal line. The non-reduced region substantially corresponds to an active region (or, a semiconductor region or a channel) of the transistor. In other words, one portion of the second semiconductor pattern may be an active region of the transistor, another portion of the second semiconductor pattern may be a source/drain region of the transistor, and yet another portion of the second semiconductor pattern may be a signal transmission region.

A source region SE2, an active region AC2, and a drain region DE2 of the oxide thin film transistor O-TFT may be formed from the second semiconductor pattern. The source regions SE2 and the drain regions DE2 may extend from the active regions AC2 in opposite directions on the third insulating layer30.

The fourth insulating layer40may be disposed on the third insulating layer30. The fourth insulating layer40may cover the second semiconductor pattern. The fourth insulating layer40may be an inorganic layer and may have a single-layer structure or a multi-layer structure. The fourth insulating layer40may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxy-nitride, zirconium oxide, and hafnium oxide. In this embodiment, the fourth insulating layer40may have a single-layer structure including silicon oxide.

A gate electrode GT2 of the oxide thin film transistor O-TFT may be disposed on the fourth insulating layer40. The gate electrode GT2 may be a portion of a metal pattern. The gate electrode GT2 overlaps the active region AC2. The gate electrode GT2 may function as a mask in a process of reducing the second semiconductor pattern.

A second lower light blocking layer BML2 may be disposed under the oxide thin film transistor O-TFT. The second lower light blocking layer BML2 may be disposed between the second insulating layer20and the third insulating layer30. The second lower light blocking layer BML2 may include the same material as the one electrode Csta constituting the capacitor and may be formed through the same process as that of the one electrode Csta of the capacitor.

The fifth insulating layer50may be disposed on the fourth insulating layer40and may cover the gate electrode GT2. The fifth insulating layer50may be an inorganic layer and/or an organic layer and may have a single-layer structure or a multi-layer structure. For example, the fifth insulating layer50may have a multi-layer structure including a silicon oxide layer and a silicon nitride layer.

A first connecting electrode CNE10 may be disposed on the fifth insulating layer50. The first connecting electrode CNE10 may be connected to the connecting signal line CSL through a first contact hole CH1 penetrating the first to fifth insulating layers10,20,30,40, and50.

The sixth insulating layer60may be disposed on the fifth insulating layer50. A second connecting electrode CNE20 may be disposed on the sixth insulating layer60. The second connecting electrode CNE20 may be connected to the first connecting electrode CNE10 through a second contact hole CH2 penetrating the sixth insulating layer60.

The seventh insulating layer70may be disposed on the sixth insulating layer60and may cover the second connecting electrode CNE20.

A third connecting electrode CNE30 may be disposed on the seventh insulating layer70. The third connecting electrode CNE30 may be connected to the second connecting electrode CNE20 through a third contact hole CH3 penetrating the seventh insulating layer70. The eighth insulating layer80may be disposed on the seventh insulating layer70and may cover the third connecting electrode CNE30. The first, second and third connecting electrodes CNE10-CNE30 may overlap each other in the third direction DR3.

The sixth insulating layer60, the seventh insulating layer70, and the eighth insulating layer80may be organic layers. For example, each of the sixth insulating layer60, the seventh insulating layer70, and the eighth insulating layer80may include a general purpose polymer, such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), Polymethylmethacrylate (PMMA), or Polystyrene (PS), a polymer derivative having a phenolic group, an acrylate-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a blend thereof.

The light emitting element ED may include a first electrode AE, a first functional layer HFL, an emissive layer EL, a second functional layer EFL, and a second electrode CE. The first functional layer HFL, the second functional layer EFL, and the second electrode CE may be commonly provided for pixels PX. The first functional layer HFL, the emissive layer EL, and the second functional layer EFL may be referred to as an intermediate layer CEL. The first electrode AE may be referred to as a pixel electrode or an anode, and the second electrode CE may be referred to as a common electrode or a cathode.

The first electrode AE may be disposed on the eighth insulating layer80. For example, the first electrode AE may be in direct contact with the eighth insulating layer80. The first electrode AE may be connected to the third connecting electrode CNE30, which is electrically connected to the pixel circuit PDC, through a fourth contact hole CH4 penetrating the eighth insulating layer80.

In an embodiment of the present disclosure, the third connecting electrode CNE30 may be omitted. In this case, the first electrode AE may penetrate the seventh and eighth insulating layers70and80and may be connected to the second connecting electrode CNE20. Furthermore, in an embodiment of the present disclosure, the third connecting electrode CNE30 and the eighth insulating layer80may be omitted. In this case, the first electrode AE may be disposed on the seventh insulating layer70. The first electrode AE may penetrate the seventh insulating layer70and may be connected to the second connecting electrode CNE20.

The first electrode AE may be a transparent electrode, a translucent electrode, or a reflective electrode. In an embodiment, the first electrode AE may include a reflective layer formed of silver, magnesium, aluminum, platinum, palladium, gold, nickel, neodymium, iridium, chromium, or a compound thereof and a transparent or translucent electrode layer formed on the reflective layer. The transparent or translucent electrode layer may include at least one selected from the group consisting of indium tin oxide, indium zinc oxide, indium gallium zinc oxide, zinc oxide, or indium oxide and aluminum-doped zinc oxide. For example, the first electrode AE may include a multi-layer structure in which indium tin oxide, silver, and indium tin oxide are sequentially stacked one above another.

A pixel defining layer PDL may be disposed on the eighth insulating layer80. The pixel defining layer PDL may have a property of absorbing light. For example, the pixel defining layer PDL may be black in color. The pixel defining layer PDL may include a black coloring agent. The black coloring agent may include a black dye or a black pigment. The black coloring agent may include carbon black, metal such as chromium, or oxide thereof.

The pixel defining layer PDL may have an opening PDLop for exposing a portion of the first electrode AE. In other words, the pixel defining layer PDL may cover the periphery of the first electrode AE. An emissive region PXA may be defined by the pixel defining layer PDL. For example, the emissive region PXA may be formed in the opening PDLop of the pixel defining layer PDL.

A spacer HSPC may be disposed on the pixel defining layer PDL. A protruding spacer SPC may be disposed on the spacer HSPC. The spacer HSPC and the protruding spacer SPC may be integrally formed with each other and may be formed of the same material. For example, the spacer HSPC and the protruding spacer SPC may be formed through the same process by a half-tone mask. However, this is an example, and the present disclosure is not limited thereto. For example, the spacer HSPC and the protruding spacer SPC may include different materials and may be formed by separate processes.

The first functional layer HFL may be disposed on the first electrode AE, the pixel defining layer PDL, the spacer HSPC, and the protruding spacer SPC. The first functional layer HFL may include a hole transport layer, may include a hole injection layer, or may include both the hole transport layer and the hole injection layer. The first functional layer HFL may be disposed in the entire display region.

The emissive layer EL may be disposed on the first functional layer HFL and may be disposed in a region corresponding to the opening PDLop of the pixel defining layer PDL. The emissive layer EL may include an organic material, an inorganic material, or an organic-inorganic material that emits light having a predetermined color.

The second functional layer EFL may be disposed on the first functional layer HFL and may cover the emissive layer EL. The second functional layer EFL may include an electron transport layer, may include an electron injection layer, or may include both the electron transport layer and the electron injection layer. The second functional layer EFL may be disposed in the entire display region.

The second electrode CE may be disposed on the second functional layer EFL. The second electrode CE may be disposed in the display region. The second electrode CE may further be disposed to overlap the pixel defining layer PDL, the spacer HSPC, and the protruding spacer SPC.

The element layer140may further include a capping layer CPL disposed on the second electrode CE. The capping layer CPL may be utilized to enhance the efficiency of light emission through the principle of constructive interference. The capping layer CPL may include, for example, a material having a refractive index of 1.6 or more for light having a wavelength of 589 nm. The capping layer CPL may be an organic capping layer including an organic material, an inorganic capping layer including an inorganic material, or a composite capping layer including an organic material and an inorganic material. For example, the capping layer may include a carbocyclic compound, a heterocyclic compound, an amine group-containing compound, a porphine derivative, a phthalocyanine derivative, a naphthalocyanine derivative, an alkali metal complex, an alkaline earth metal complex, or a combination thereof. The carbocyclic compound, the heterocyclic compound, and the amine group-containing compound may be selectively replaced with a substituent including oxygen (O), nitrogen (N), sulfur (S), selenium (Se), silicon (Si), fluorine (F), chlorine (Cl), bromine (Br), iodine (I), or a combination thereof.

The encapsulation layer150may be disposed on the element layer140. The encapsulation layer150may include a first inorganic encapsulation layer151, an organic encapsulation layer152, and a second inorganic encapsulation layer153that are sequentially stacked one above another. The first and second inorganic encapsulation layers151and153may protect the element layer140from moisture and oxygen, and the organic encapsulation layer152may protect the element layer140from foreign matter such as dust particles.

In an embodiment of the present disclosure, a low-refractive index layer may be additionally disposed between the capping layer CPL and the encapsulation layer150. The low-refractive index layer may include lithium fluoride. The low-refractive index layer may be formed by a thermal deposition method.

The sensor layer200may be disposed on the display layer100. The sensor layer200may be referred to as a sensor, an input sensing layer, or an input sensing panel. The sensor layer200may include a sensor base layer201, a first sensor conductive layer202, a sensor insulating layer203, a second sensor conductive layer204, and a sensor cover layer205.

The sensor base layer201may be directly disposed on the display layer100. For example, the sensor base layer201may be directly disposed on the second inorganic encapsulation layer153. The sensor base layer201may be an inorganic layer including at least one of silicon nitride, silicon oxy-nitride, and silicon oxide. Alternatively, the sensor base layer201may be an organic layer including an epoxy resin, an acrylic resin, or an imide-based resin. The sensor base layer201may have a single-layer structure, or may have a multi-layer structure stacked in the third direction DR3.

Each of the first sensor conductive layer202and the second sensor conductive layer204may have a single-layer structure, or may have a multi-layer structure stacked in the third direction DR3.

A conductive layer (e.g., the first sensor conductive layer202or the second sensor conductive layer204) having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum (Mo), silver (Ag), titanium (Ti), copper (Cu), aluminum (Al), or an alloy thereof. The transparent conductive layer may include transparent conductive oxide such as indium tin oxide, indium zinc oxide, zinc oxide, or indium zinc tin oxide. In addition, the transparent conductive layer may include a conductive polymer such as poly(3,4-ethylenedioxythiophene) (PEDOT), a metal nano wire, or graphene.

A conductive layer having a multi-layer structure may include metal layers. The meal layers may have, for example, a three-layer structure of titanium/aluminum/titanium. The conductive layer having the multi-layer structure may include at least one metal layer and at least one transparent conductive layer.

The sensor insulating layer203may be disposed between the first sensor conductive layer202and the second sensor conductive layer204. The sensor insulating layer203may include an organic film. The organic film may include at least one of an acrylate-based resin, a methacrylate-based resin, a polyisoprene-based resin, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a celluose-based resin, a siloxane-based resin, a polyimide-based resin, a polyamide-based resin, and a perylene-based resin. The first sensor conductive layer202and the second sensor conductive layer204may be connected to each other through a hole in the sensor insulating layer203.

Alternatively, the sensor insulating layer203may include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxy-nitride, zirconium oxide, and hafnium oxide.

The sensor cover layer205may be disposed on the sensor insulating layer203and may cover the second sensor conductive layer204. The second sensor conductive layer204may include a conductive pattern. The sensor cover layer205may cover the conductive pattern and may reduce or eliminate a probability of damage to the conductive pattern in a subsequent process. The sensor cover layer205may include an inorganic material. For example, the sensor cover layer205may include silicon nitride, but is not particularly limited thereto. In an embodiment of the present disclosure, the sensor cover layer205may be omitted.

The anti-reflection layer300may be disposed on the sensor layer200. The anti-reflection layer300may include a dividing layer310, a plurality of color filters320, and a planarization layer330.

The dividing layer310may overlap the conductive pattern of the second sensor conductive layer204. The sensor cover layer205may be disposed between the dividing layer310and the second sensor conductive layer204. The dividing layer310may prevent reflection of external light by the second sensor conductive layer204. A material constituting the dividing layer310is not particularly limited as long as can absorb light. The dividing layer310may be a black layer. In an embodiment, the dividing layer310may include a black coloring agent. The black coloring agent may include a black dye or a black pigment. The black coloring agent may include carbon black, metal such as chromium, or oxide thereof.

The dividing layer310may have a dividing opening310opdefined therein. The dividing opening310opmay overlap the emissive layer EL. The color filter320may be disposed to correspond to the dividing opening310op. In other words, the color filter320may be provided in the dividing opening310op. The color filter320may transmit light provided from the emissive layer EL overlapping the color filter320.

The planarization layer330may cover the dividing layer310and the color filter320. The planarization layer330may include an organic material and may provide a flat surface on an upper surface of the planarization layer330. In an embodiment, the planarization layer330may be omitted.

In an embodiment of the present disclosure, the anti-reflection layer300may include a reflection control layer instead of the color filters320. For example, the color filter320may be omitted inFIG.3, and the reflection control layer may be added at the place where the color filter320is omitted. The reflection control layer may selectively absorb light in a partial band of light reflected inside the display panel and/or the electronic device1000or light in a partial band of light incident from outside the display panel and/or the electronic device1000.

For example, the reflection control layer may absorb light in a first wavelength region of 490 nm to 505 nm and a second wavelength region of 585 nm to 600 nm, and thus the light transmittance in the first wavelength region and the second wavelength region may be 40% or less. The reflection control layer may absorb light outside the wavelength ranges of red light, green light, and blue light emitted from the emissive layers EL. Since the reflection control layer absorbs light outside the wavelength range of the red light, the green light, or the blue light emitted from the emissive layers EL as described above, a decrease in the luminance of the display panel and/or the electronic device1000may be prevented or minimized. In addition, deterioration in the light emission efficiency of the display panel and/or the electronic device1000may be prevented or minimized, and visibility may be improved.

The reflection control layer may be implemented with an organic layer including a dye, a pigment, or a combination thereof. The reflection control layer may include a tetraazaporphyrin (TAP)-based compound, a porphyrin-based compound, a metal porphyrin-based compound, an oxazine-based compound, a squarylium-based compound, a triarylmethane-based compound, a polymethine-based compound, an anthraquinone-based compound, a phthalocyanine-based compound, an azo-based compound, a perylene-based compound, a xanthene-based compound, a diimmonium-based compound, a dipyrromethene-based compound, a cyanine-based compound, and a combination thereof.

In an embodiment, the reflection control layer may have a transmittance of about 64% to about 72%. The transmittance of the reflection control layer may be adjusted depending on the content of the pigment and/or dye included in the reflection control layer.

In an embodiment of the present disclosure, the anti-reflection layer300may include a phase retarder and/or a polarizer. The anti-reflection layer300may include at least a polarizer film. In this case, the anti-reflection layer300may be attached to the sensor layer200through an adhesive layer.

FIG.4is a plan view of the display layer100according to an embodiment of the present disclosure.

Referring toFIG.4, the display layer100may have a display region100DA and a peripheral region100NDA. The display region100DA may display an image, and the peripheral region100NDA may be adjacent to the display region100DA. The display region100DA may correspond to the display region DA (refer toFIG.1) of the electronic device1000(refer toFIG.1), and the peripheral region100NDA may correspond to the peripheral region NDA (refer toFIG.1) of the electronic device1000(refer toFIG.1). The expression “one region/portion corresponds to another region/portion” used herein may mean that the regions/portions overlap each other and is not limited to having the same area.

InFIG.4, some components included in the display layer100are illustrated. The display layer100may include a plurality of pixels PX, a plurality of lines DLI to DLm, a plurality of first pads PD1, and a plurality of second pads PD2. The display layer100may further include components other than those illustrated inFIG.4. Furthermore, in an embodiment of the present disclosure, the display layer100may not include the second pads PD2.

The display region100DA and the peripheral region100NDA may be distinguished from each other depending on whether the pixels PX are disposed or not. The pixels PX may be disposed in the display region100DA and the pixels PX may not be disposed in the peripheral region100NDA. The plurality of lines DLI to DLm connected to the pixels PX may be disposed in the display region100DA and the peripheral region100NDA. The first pads PD1 and the second pads PD2 may be disposed in the peripheral region100NDA. In an embodiment of the present disclosure, a driver IC may be mounted on the peripheral region100NDA, or a flexible circuit film having the driver IC mounted thereon may be electrically connected to the first pads PD1.

FIG.5is a plan view of the sensor layer200according to an embodiment of the present disclosure.

Referring toFIG.5, the sensor layer200may include a plurality of first electrodes210and a plurality of second electrodes220. The first electrodes210may be arranged in the first direction DR1, and the second electrodes220may be arranged in the second direction DR2 crossing the first direction DR1. The first electrodes210may extend in the second direction DR2 and may cross the second electrodes220. The second electrodes220may extend in the first direction DR1 and may cross the first electrodes210.

The display region100DA and the peripheral region100NDA of the display layer100(refer toFIG.4) are illustrated in the sensor layer200ofFIG.5. The first electrodes210and the second electrodes220may overlap the display region100DA.

Although eight first electrodes210and twelve second electrodes220are illustrated as an example inFIG.5, the number of first electrodes210and the number of second electrodes220are not particularly limited thereto. For example, the number of first electrodes210and the number of second electrodes220may be changed depending on the screen aspect ratio of the electronic device1000(refer toFIG.1).

The sensor layer200may include a plurality of first trace lines210telectrically connected with the first electrodes210, respectively, and a plurality of second trace lines220telectrically connected with the second electrodes220, respectively.

In an embodiment of the present disclosure, the second trace lines220tmay extend to overlap the display region100DA. For example, the second trace lines220tmay not be disposed in the peripheral regions100NDA that are adjacent to the display region100DA in the first direction DR1. In other words, the second trace lines220tmay not be disposed on left or right sides of the display region100DA. Accordingly, the area of the peripheral region100NDA may be reduced. Thus, the area occupied by the peripheral region NDA (refer toFIG.1) on the display surface IS (refer toFIG.1) of the electronic device1000(refer toFIG.1) may be reduced, and a narrow bezel may be implemented.

The first electrodes210and the first trace lines210tmay be connected through a plurality of first contacts210ct. The second electrodes220and the second trace lines220tmay be connected through a plurality of second contacts220ct. In an embodiment of the present disclosure, all of the first contacts210ctand the second contacts220ctmay overlap the display region100DA. Accordingly, portions of the first trace lines210tand the second trace lines220tmay overlap the display region100DA, and the other portions thereof may overlap the peripheral region100NDA.

According to an embodiment of the present disclosure, the portions of the first trace lines210tand the portions of the second trace lines220tthat overlap the peripheral region100NDA may all extend in the second direction DR2 and may be electrically connected with the second pads PD2. For example, the portions of the first trace lines210tand the portions of the second trace lines220tthat overlap the peripheral region100NDA may be located at the lower side of the display region100DA. The second pads PD2 may be arranged in the first direction DR1. Portions of the first trace lines210tand the second trace lines220tthat extend in the same direction as the arrangement direction of the second pads PD2 may all overlap the display region100DA. Accordingly, the area of a portion of the peripheral region100NDA between the region where the second pads PD2 are disposed and the display region100DA may be reduced. In other words, the area of the peripheral region100NDA near the lower side of the display region100DA may be reduced.

According to an embodiment of the present disclosure, bent portions of the first trace lines210tand bent portions of the second trace lines220tmay overlap the display region100DA. Since the bent portions overlap the display region100DA, the area of the peripheral region100NDA between the display region100DA and the region where the second pads PD2 are disposed may be reduced. Thus, the area occupied by the peripheral region NDA (refer toFIG.1) on the display surface of the electronic device1000(refer toFIG.1) may be reduced, and a narrow bezel may be implemented.

FIG.6is a plan view of one sensing unit SU according to an embodiment of the present disclosure.

Referring toFIGS.5and6, the sensor layer200may be divided into a plurality of sensing units SU. Each of the sensing units SU may include a corresponding crossing region among crossing regions of the first electrodes210and the second electrodes220.

InFIG.6, the one sensing unit SU is representatively illustrated, and a portion of one first electrode210-1and a portion of one second electrode220-1are illustrated. The one first electrode210-1may be electrically connected with one first trace line210t-1, and the one second electrode220-1may be electrically connected with one second trace line220t-1. However, without being particularly limited thereto, the one first electrode210-1may be electrically connected with a plurality of first trace lines that provide the same transmission signal or output the same reception signal. Alternatively, the one second electrode220-1may be electrically connected with a plurality of second trace lines that provide the same transmission signal or output the same reception signal.

The one first electrode210-1may include a plurality of segmented electrodes210d1,210d2, and210d3. AlthoughFIG.6illustrates an example that the one first electrode210-1includes three segmented electrodes210d1,210d2, and210d3, the number of segmented electrodes210d1,210d2, and210d3is not particularly limited thereto. The segmented electrodes210d1,210d2, and210d3may be spaced apart from each other in the first direction DR1. Each of the segmented electrodes210d1,210d2, and210d3may extend in the second direction DR2.

Second trace lines220t-1aand220t-1bmay be disposed between the segmented electrodes210d1,210d2, and210d3. For example, the one second trace line220t-1amay be disposed between the two adjacent segmented electrodes210d1and210d2, and the one second trace line220t-1bmay be disposed between the two adjacent segmented electrodes210d2and210d3. The one second trace line220t-1aand the one second trace line220t-1bmay be electrically connected to second electrodes220included in sensing units SU other than the sensing unit SU illustrated inFIG.6.

According to an embodiment of the present disclosure, the second trace lines220t-1aand220t-1bmay not overlap the first electrodes210when viewed from above the plane, for example, when viewed in the third direction DR3. Accordingly, an influence of signal interference or parasitic capacitance between the first electrodes210and the second trace lines220t-1aand220t-1bmay be minimized.

The second electrode220-1may include sensing patterns221and bridge patterns222disposed on a layer different from the sensing patterns221. The sensing patterns221may be spaced apart from each other in the first direction DR1 (e.g., a segmented electrode210d1,210d2, or210d3may be located between adjacent sensing patterns211), and the bridge patterns222may electrically connect the sensing patterns221adjacent to each other. AlthoughFIG.6illustrates an example that two sensing patterns221adjacent to each other are electrically connected with each other by six bridge patterns222, the present disclosure is not particularly limited thereto.

Each of the segmented electrodes210d1,210d2, and210d3may include a sensing portion211and a bridge portion212. The sensing portion211and the bridge portion212may be integrally formed with each other and may be disposed on the same layer. The sensing portion211may be referred to as a pattern part or a first portion, and the bridge portion212may be referred to as a connecting portion or a second portion. Alternatively, the sensing portions211, the bridge portions212, the sensing patterns221, and the bridge patterns222may be referred to as first sensing patterns, first bridge patterns, second sensing patterns, and second bridge patterns, respectively.

The sensor layer200may further include first dummy patterns DM1 disposed between the segmented electrodes210d1,210d2, and210d3and the sensing patterns221. Each of the first dummy patterns DM1 may be disposed between a portion of the first electrode210-1and a portion of the second electrode220-1. Each of the first dummy patterns DM1 may be electrically floated or grounded.

FIG.7is an enlarged plan view of region AA′ illustrated inFIG.6according to an embodiment of the present disclosure.FIG.8is an enlarged plan view of region BB′ illustrated inFIG.6according to an embodiment of the present disclosure.

Referring toFIGS.3,7, and8, components illustrated inFIG.7may be components included in the second sensor conductive layer204, and components illustrated inFIG.8may be components included in the first sensor conductive layer202. In this case, the sensor layer200has a structure in which the bridge patterns222are disposed closer to the display layer100than the sensing patterns221. Accordingly, the sensor layer200may have a bottom bridge structure. However, the present disclosure is not limited thereto. For example, the components illustrated inFIG.7may be components included in the first sensor conductive layer202, and the components illustrated inFIG.8may be components included in the second sensor conductive layer204. In this case, the sensor layer200has a structure in which the sensing patterns221are disposed closer to the display layer100than the bridge patterns222. Accordingly, the sensor layer200may have a top bridge structure.

Referring toFIGS.6and7, the sensing portion211, the bridge portion212, the sensing pattern221, and the first dummy patterns DM1 may be disposed on the same layer. Each of the sensing portion211, the bridge portion212, the sensing pattern221, and the first dummy patterns DM1 may have a mesh structure. The sensing portion211and the bridge portion212may be electrically isolated from the sensing pattern221, and the first dummy patterns DM1 may be electrically isolated from the sensing portion211, the bridge portion212, and the sensing pattern221. InFIG.7, a boundary CL cutting the mesh structure is illustrated by a dotted line.

Furthermore, to prevent the boundary CL from being visible to the user by reflection of external light, a visibility cut obtained by removing a portion of the mesh structure may be additionally provided to each of the sensing portion211, the bridge portion212, the sensing pattern221, and the first dummy patterns DM1.

Referring toFIGS.5,6, and8, the sensor layer200may further include second dummy patterns DM2a, DM2b, DM2c, DM2d, and DM2e. The second dummy patterns DM2a, DM2b, DM2c, DM2d, and DM2e may be disposed on the same layer as the second trace lines220t-1aand220t-1band the bridge patterns222. Each of the second dummy patterns DM2a, DM2b, DM2c, DM2d, and DM2e may be electrically floated. The second dummy patterns DM2a, DM2b, DM2c, DM2d, and DM2e may be referred to as dummy patterns. In an embodiment of the present disclosure, the second dummy patterns DM2a, DM2b, DM2c, DM2d, and DM2e may be omitted.

InFIG.8, first, second, third and fourth boundaries CLa, CLb, CLc, and CLd cutting the mesh structure are illustrated by dotted lines. Portions of the first sensor conductive layer202other than the bridge patterns222and the second trace lines220t-1aand220t-1bmay all be constituted by the second dummy patterns DM2a, DM2b, DM2c, DM2d, and DM2e. The first boundary CLa may be a boundary for separating each of the bridge patterns222and the second dummy patterns DM2a, DM2b, DM2c, DM2d, and DM2e. The second boundary CLb may be a boundary for separating the second dummy patterns DM2a, DM2b, DM2c, DM2d, and DM2e and each of the second trace lines220t-1aand220t-1b. The third boundary CLc may be a visible cut obtained by removing a portion of the mesh structure to prevent the portion of the mesh structure from being visible to the user due to reflection of external light. The fourth boundary CLd may be a boundary for electrically isolating the second dummy patterns DM2a, DM2b, DM2c, DM2d, and DM2e.

In an embodiment of the present disclosure, the second dummy patterns DM2a, DM2b, DM2c, DM2d, and DM2e may have a size smaller than or equal to a predetermined size since the fourth boundary CLd is additionally provided. Accordingly, the capacitance between each of the second dummy patterns DM2a, DM2b, DM2c, DM2d, and DM2e and the first electrode210-1or the second electrode220-2may be less than or equal to a predetermined value. Thus, the signal to noise ratio of the sensor layer200may be increased so that the sensing sensitivity of the sensor layer200may be improved.

FIG.9is an enlarged plan view of region BB′ illustrated inFIG.6according to an embodiment of the present disclosure. In describingFIG.9, the following description will be focused on only the difference fromFIG.8, and identical components will be assigned with identical reference numerals and will be omitted from the description.

Referring toFIGS.5,6, and9, the sensor layer200may further include a second dummy pattern DM2-1. The second dummy pattern DM2-1 may be disposed on the same layer as the second trace lines220t-1aand220t-1band the bridge patterns222. The second dummy pattern DM2-1 may be electrically floated or electrically grounded. For example, the electronic device1000(refer toFIG.1) may further include a ground pad G-PD to which a ground voltage is applied, and the second dummy pattern DM2-1 may be electrically connected to the ground pad G-PD.

FIG.10Ais a plan view illustrating a portion of the sensor layer corresponding to region CC′ illustrated inFIG.5according to an embodiment of the present disclosure.FIG.10Bis a plan view illustrating a portion of the sensor layer corresponding to region CC′ illustrated inFIG.5according to an embodiment of the present disclosure.

Referring toFIGS.5,10A, and10B, two sensing units SUa and SUb are illustrated as an example inFIGS.10A and10B. The two sensing units SUa and SUb may be some of the sensing units overlapping the display region100DA and adjacent to the peripheral region100NDA among the plurality of sensing units SU.

Referring toFIG.10A, each of the first trace lines210tmay include a first portion210p1extending parallel to the first direction DR1 and a second portion210p2extending from the first portion210p1in parallel with the second direction DR2, and the first portion210p1may overlap the display region100DA. The second portion210p2may include a first sub-portion210s1overlapping the display region100DA and a second sub-portion210s2overlapping the peripheral region100NDA. A portion where the first portion210p1and the second portion210p2meet each other may be referred to as a bent portion of each of the first trace lines210t.

The first portion210p1may be referred to as a (1-1)th portion or a connecting portion. The second portion210p2may be referred to as a (1-2)th portion or an extending portion. The second portion210p2may extend from one end of the first portion210p1toward the peripheral region100NDA.

Portions of the first trace lines210tthat overlap the display region100DA may be disposed on the same layer as the sensing portion211and the sensing pattern221. For example, both the first portion210p1and the first sub-portion210-s1may be disposed on the same layer as the sensing pattern221. The first portion210p1and the first sub-portion210s1may have a mesh structure that is similar to those of the sensing portion211and the sensing pattern221, and description thereabout will be given below.

In an embodiment of the present disclosure, each of the first trace lines210tmay be integrally connected to a corresponding sensing portion211. Accordingly, each of the first contacts210ctmay be referred to as a portion where one first trace line210tmakes contact with one first electrode210. In other words, a first contact210ctmay be an area where a first trace line210tand a first electrode210meet.

In an embodiment of the present disclosure, each of the first trace lines210tmay not overlap the first electrodes210and the second electrodes220. For example, a portion of each of the first trace lines210tmay overlap the display region100DA and may not overlap the first electrodes210and the second electrodes220. Accordingly, the sensing units SUa and SUb may be spaced apart from the peripheral region100NDA with the first trace lines210ttherebetween. Thus, a non-sensing region NSA overlapping the display region100DA may be formed in the sensor layer200, and portions of the first trace lines210tand portions of the second trace lines220tto be described below may be disposed in the non-sensing region NSA.

Referring toFIG.10B, each of the second trace lines220tmay include a first portion220p1extending parallel to the second direction DR2, a second portion220p2extending from the first portion220p1in parallel with the first direction DR1, and a third portion220p3extending from the second portion220p2in parallel with the second direction DR2. The first portion220p1and the second portion220p2may overlap the display region100DA. The third portion220p3may include a first sub-portion220s1overlapping the display region100DA and a second sub-portion220s2overlapping the peripheral region100NDA. A portion where the first portion220p1and the second portion220p2meet each other and a portion where the second portion220p2and the third portion220p3meet each other may be referred to as bent portions of the second trace lines220t. In this case, the second trace lines220tmay include two bent portions.

The first portion220p1may be referred to as a (2-1)th portion or a contact extending portion. The second portion220p2may be referred to as a (2-2)th portion or a connecting portion. The third portion220p3may be referred to as a (2-3)th portion or an extending portion. The first portion220p1may extend from one end of the second portion220p2in a direction away from the peripheral region100NDA, and the third portion220p3may extend from an opposite end of the second portion220p2toward the peripheral region100NDA. For example, the first portion220p1may be connected to a first end of the second portion220p2and the third portion220p3may be connected to a second end of the second portion220p2.

Portions of the second trace lines220tthat overlap the display region100DA may be disposed on the same layer as the bridge patterns222. For example, the first portion220p1, the second portion220p2, and the first sub-portion220s1may be disposed on the same layer as the bridge patterns222. The first portion220p1, the second portion220p2, and the first sub-portion220s1may have a mesh structure that is similar to those of the bridge patterns222.

Each of the second trace lines220t-1aand220t-1billustrated inFIG.6may correspond to the first portion220p1. The first portion220p1may not overlap the first electrodes210. Accordingly, an influence of signal interference or parasitic capacitance between the first electrodes210and the first portion220p1may be minimized.

Referring toFIGS.10A and10B, the portions where the directions of the first trace lines210tand the second trace lines220tare changed may all overlap the display region100DA. For example, the bent portions of the first trace lines210tand the second trace lines220tmay overlap the display region100DA. Accordingly, all of the portions of the first trace lines210tand the second trace lines220tthat overlap the peripheral region100NDA may include a straight line extending in the second direction DR2. In other words, the second sub-portions210s2of the first trace lines210tand the second sub-portions220s2of the second trace lines220tmay all be straight lines extending in the second direction DR2.

FIG.11is a plan view illustrating a portion of the sensor layer corresponding to region DD′ illustrated in each ofFIGS.10A and10Baccording to an embodiment of the present disclosure.

Referring toFIGS.10A,10B, and11, the first sub-portion210s1or220s1overlapping the display region100DA and the second sub-portion210s2or220s2overlapping the peripheral region100NDA are illustrated. Hereinafter, the first sub-portion210s1and the second sub-portion210s2will be representatively described, and descriptions of the first sub-portion220s1and the second sub-portion220s2will be omitted.

The shape of the second sub-portion210s2may differ from the shapes of the first portion210p1and the first sub-portion210s1.

Each of the first portion210p1and the first sub-portion210s1may be a portion of a mesh structure. For example, each of the first portion210p1and the first sub-portion210s1may include mesh lines MSL extending in a first crossing direction CDR1 and a second crossing direction CDR2. The first crossing direction CDR1 may be a direction between the first direction DR1 and the second direction DR2, and the second crossing direction CDR2 may be a direction crossing the first crossing direction CDR1. However, without being particularly limited thereto, each of the first portion210p1and the first sub-portion210s1may include mesh lines extending in the first direction DR1 and the second direction DR2.

The second sub-portion210s2may be a bar-type electrode having a predetermined width WT1 and extending in the second direction DR2.

The width WT1 of the second sub-portion210s2may differ from the width WT2 of the first sub-portion210s1. For example, in the first direction DR1, the first sub-portion210s1extending in the second direction DR2 may have the maximum width WT2 greater than the width WT1 of the second sub-portion210s2in the first direction DR1. Furthermore, the width WTm of the mesh lines MSL of the second sub-portion210s2may be smaller than the width WT1 of the second sub-portion210s2. However, this is merely illustrative, and the maximum width WT2 of the first sub-portion210s1in the first direction DR1 may be smaller than or equal to the width WT1 of the second sub-portion210s2.

FIG.12Ais a sectional view taken along line II-II′ illustrated inFIG.11according to an embodiment of the present disclosure.FIG.12Bis a sectional view taken along line II-II′ illustrated inFIG.11according to an embodiment of the present disclosure.

Referring toFIGS.5,11, and12A, the second sub-portion210s2may have a multi-layer structure. For example, the second sub-portion210s2may include a first sub-conductive layer211pand a second sub-conductive layer212pdisposed on a layer different from the first sub-conductive layer211p. The first sub-conductive layer211pand the second sub-conductive layer212pmay be electrically connected with each other. For example, the first sub-conductive layer211pand the second sub-conductive layer212pmay contact each other through an opening in the sensor insulating layer203. Since a portion of the first trace line210thas a multi-layer structure, the resistance of the first trace line210tmay be decreased. However, the present disclosure is not limited thereto, and the second sub-portion210s2may include only the first sub-conductive layer211p, or may include only the second sub-conductive layer212p.

Referring toFIGS.5,11, and12B, the second sub-portion220s2may have a multi-layer structure. For example, the second sub-portion220s2may include a first sub-conductive layer221pand a second sub-conductive layer222pdisposed on a layer different from the first sub-conductive layer221p. The first sub-conductive layer221pand the second sub-conductive layer222pmay be electrically connected with each other. Since a portion of the second trace line220thas a multi-layer structure, the resistance of the second trace line220tmay be decreased. However, the present disclosure is not limited thereto, and the second sub-portion220s2may include only the first sub-conductive layer221p, or may include only the second sub-conductive layer222p.

The first sub-conductive layer211pand the first sub-conductive layer221pmay be disposed between the sensor base layer201and the sensor insulating layer203, and the second sub-conductive layer212pand the second sub-conductive layer222pmay be disposed between the sensor insulating layer203and the sensor cover layer205. In other words, the first sub-conductive layer211pand the first sub-conductive layer221pmay be included in the first sensor conductive layer202(refer toFIG.3), and the second sub-conductive layer212pand the second sub-conductive layer222pmay be included in the second sensor conductive layer204(refer toFIG.3).

In an embodiment of the present disclosure, when the sensor layer200has a bottom bridge structure, the first sub-conductive layer211pand the first sub-conductive layer221pmay be disposed on the same layer as the first sub-portion220s1of the second trace line220t, and the second sub-conductive layer212pand the second sub-conductive layer222pmay be disposed on the same layer as the first sub-portion210s1of the first trace line210t.

When the sensor layer200has a top bridge structure, the first sub-conductive layer211pand the first sub-conductive layer221pmay be disposed on the same layer as the first sub-portion210s1of the first trace line210t, and the second sub-conductive layer212pand the second sub-conductive layer222pmay be disposed on the same layer as the first sub-portion220s1of the second trace line220t.

FIG.13is a plan view illustrating some components of the sensor layer200according to an embodiment of the present disclosure.

Referring toFIG.13, portions of two first trace lines210taand portions of two second trace lines220tare illustrated as an example.

Each of the first trace lines210tamay include a first portion210p1aextending parallel to the first direction DR1 and a second portion210p2extending from the first portion210p1ain parallel with the second direction DR2, and the first portion210p1amay overlap the display region100DA. The second portion210p2may include a first sub-portion210s1overlapping the display region100DA and a second sub-portion210s2overlapping the peripheral region100NDA.

In an embodiment of the present disclosure, the first portion210p1amay include a first layer portion210p1-aand a second layer portion210p1-cdisposed on a layer different from the first layer portion210p1-a. The first layer portion210p1-amay be disposed on the same layer as the second trace lines220t. The second layer portion210p1-cmay be insulated from at least one second trace line220tamong the second trace lines220tand may cross the at least one second trace line220t.

In an embodiment of the present disclosure, the portions of the first trace line210tathat overlap the display region100DA may all be disposed on the same layer, and a second portion220p2of each of the second trace lines220tmay include a first layer portion and a second layer portion disposed on a layer different from the first layer portion. The first layer portion may be disposed on the same layer as the first trace line210ta. In this case, the second layer portion of the second trace line220tmay be insulated from the first trace line210taand may cross the first trace line210ta.

FIG.14Ais a plan view illustrating a portion of the sensor layer corresponding to region CC′ illustrated inFIG.5according to an embodiment of the present disclosure.FIG.14Bis a plan view illustrating a portion of the sensor layer corresponding to region CC′ illustrated inFIG.5according to an embodiment of the present disclosure.

Referring toFIGS.5,13,14A, and14B, two sensing units SUa1 and SUb1 are illustrated as an example. The two sensing units SUa1 and SUb1 may be some of the sensing units overlapping the display region100DA and adjacent to the peripheral region100NDA among the plurality of sensing units SU.

A first layer portion210p1-amay be disposed on the same layer as the bridge patterns222, and a second layer portion210p1-cmay be disposed on the same layer as the sensing patterns221.

In an embodiment of the present disclosure, portions of the first trace lines210tamay overlap the first electrodes210and the second electrodes220. For example, a portion of each of the first trace lines210tamay overlap the display region100DA and may overlap the first electrodes210and the second electrodes220. Accordingly, the areas of the sensing units SUa1 and SUb1 may be larger the areas of the sensing units SUa and SUb illustrated in FIGS.10A and10B. In addition, the distance between the sensing units SUa1 and SUb1 and the peripheral region100NDA may be smaller than the distance between the sensing units SUa and SUb illustrated inFIGS.10A and10Band the peripheral region100NDA.

As described above, the sensor layer includes the plurality of first electrodes, the plurality of second electrodes, the plurality of first trace lines, and the plurality of second trace lines. The bent portions of the first trace lines and the bent portions of the second trace lines may overlap the display region. Accordingly, the area of the peripheral region may be reduced. Thus, the area occupied by the peripheral region on the display surface of the electronic device may be reduced, and a narrow bezel may be implemented.

While the present disclosure has been described with reference to embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the present disclosure as set forth in the following claims.