Patent ID: 12237286

DETAILED DESCRIPTION

In some embodiments, a semiconductor package for high-speed die connections using a conductive insert includes: a die; a plurality of redistribution layers; a conductive insert housed in a perforation through the plurality of redistribution layers; and a conductive bump conductively coupled to an input/output connection point of the die via the conductive insert.

In some embodiments, the semiconductor package further includes an under bump metallization layer, wherein the conductive bump is applied to the under bump metallization layer. In some embodiments, the input/output connection point of the die includes a conductive pad of the die. In some embodiments, the plurality of redistribution layers include a plurality of back end of line redistribution layers. In some embodiments, the plurality of redistribution layers include a plurality of fabrication redistribution layers. In some embodiments, the semiconductor package further includes a power delivery layer applied to the plurality of fabrication redistribution layers, wherein the conductive bump is applied to the power delivery layer. In some embodiments, the semiconductor package further includes die, wherein the plurality of inorganic fabrication redistribution layers facilitate communication between the die and the other die.

In some embodiments, a method for high-speed die connections using a conductive insert includes: creating a perforation in a plurality of redistribution layers of a semiconductor package, wherein the perforation exposes an input/output connection point of a die; inserting, into the perforation, a conductive insert; and applying a conductive bump to the semiconductor package creating a conductive pathway between the conductive bump and the input/output connection point of the die.

In some embodiments, the method further includes applying an under bump metallization layer to the semiconductor package, and wherein the conductive bump is applied to the under bump metallization layer. In some embodiments, the input/output connection point of the die includes a conductive pad of the die. In some embodiments, the plurality of redistribution layers include a plurality of back end of line redistribution layers. In some embodiments, the plurality of redistribution layers include a plurality of fabrication redistribution layers. In some embodiments, the method further includes applying a power delivery layer on the plurality of fabrication redistribution layers, wherein the conductive bump is applied to the power delivery layer. In some embodiments, the plurality of inorganic fabrication redistribution layers facilitate communication between the die and another die in the semiconductor package.

In some embodiments, an apparatus for high-speed die connections using a conductive insert includes: a component; and a semiconductor package operatively coupled to the component, the semiconductor package including: a die; a plurality of redistribution layers; a conductive insert housed in a perforation through the plurality of redistribution layers; and a conductive bump conductively coupled to an input/output connection point of the die via the conductive insert.

In some embodiments, the semiconductor package further includes an under bump metallization layer, wherein the conductive bump is applied to the under bump metallization layer. In some embodiments, the input/output connection point of the die includes a conductive pad of the die. In some embodiments, the input/output connection point of the die includes a bonding pad of the die. In some embodiments, the plurality of redistribution layers include a plurality of back end of line redistribution layers. In some embodiments, the plurality of redistribution layers include a plurality of fabrication redistribution layers. In some embodiments, the semiconductor package further includes a power delivery layer applied to the plurality of fabrication redistribution layers, wherein the conductive bump is applied to the power delivery layer.

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “back,” “front,” “top,” “bottom,” and the like, are used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Similarly, terms such as “front surface” and “back surface” or “top surface” and “back surface” may be used herein to more easily identify various components, and may identify that those components are, for example, on opposing sides of another component. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.

The construction of a semiconductor device such as a system-in-package (SiP) or system-on-integrated chip (SoIC) generally includes a die fabrication process and a packaging process. The fabrication process, typically performed in a clean room at a foundry, includes fabricating system-on-a-chip (SoC) dies that implement a component, or functional circuit block, of the system on a wafer. For example, each SoC die includes a component such as a processor core, interface, memory, graphical processing unit, digital signal processor, and the like. These components are partitioned on the wafer. During the fabrication process, the device layers implementing the functional circuit blocks and the redistribution structures connecting those functional circuit blocks are created in a clean room with great precision. The wafer is then diced to create individual SoC dies (e.g., “chiplets”).

A given die includes various input/output (I/Os) connections. In order to interconnect the die with other components, solder bumps are used as part of a conductive pathway to the I/O connections of the die. For example, in the controlled collapse chip connection (C4) process, solder bumps are deposited on a top side of a semiconductor package, where the semiconductor package has a conductive pathway from an I/O connection of the die to the top side through the semiconductor package. The semiconductor package is coupled to other components (e.g., a chip, a motherboard, and the like) by facing the top side of the semiconductor package to the connection points of the other components, reheating the solder bumps to flow into the connection points of the other components, thereby forming a connection to these other components.

Existing solutions for forming a conductive pathway from the I/O connections of a die to a face of a semiconductor package require the use of a conductive pathway formed by a series of vias and conductive pads. For example, a semiconductor package will include a die with multiple redistribution layers (e.g., back end of line (BEOL) organic redistribution layers) deposited on the die. The top face of the semiconductor package will include a metallization layer of a conductive metal (e.g., copper, gold, or another layer of metal) with solder bumps deposited on the metallization layer. Between the metallization layer and an I/O connection point of the die, such as a conductive pad or plate bonded to the die at an I/O connection, a conductive pathway is formed in the redistribution layers by a series of conductive vias, with a conductive pad separating each via. For example, each redistribution layer will include either a via or a conductive pad that are each in conductive contact with the via or pad of the adjacent layers. Though this use of a series of alternating vias and pads provides a conductive pathway between the solder bumps at the top face of the semiconductor package and the I/O connections of the die, the use of this series of vias and pads provides considerable capacitance, series resistance, and inductance. As the number of redistribution layers increases, requiring more pads and vias, the capacitance, resistance, and inductance also increase.

To address these drawbacks, a semiconductor package100for high-speed die connections using a conductive insert is shown inFIG.1. The semiconductor package100ofFIG.1can be implemented in a variety of devices or apparatuses, including mobile devices, personal computers, peripheral hardware components, gaming devices, set-top boxes, and the like, or any other computing device as can be appreciated. The semiconductor package100includes a die102. The die102is composed of a bulk suitable material (e.g., silicon, germanium, or gallium derivatives) and device layers typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over the semiconductor bulk, and patterning the various material layers using photolithography and photomasking to form circuit components and elements (e.g., transistors, capacitors, resistors, etc.). In some embodiments, the circuit components are connected to form integrated circuits that implement a functional circuit block of a SoC die, such as a processor, interface, memory, and or other system component.

The surface of the die102includes multiple input/output (I/O) connections allowing for signals to travel to and from the die102, thereby allowing the die102to communicate with other components as desired. Conductive pads104are bonded to the surface of the die102at these I/O connections to provide a connection point for conductive pathways, such as wires, traces, and the like. For example, the conductive pads104are composed of aluminum, copper, gold, or another conductive material as can be appreciated. The conductive pads104bonded to the surface of the die102are also referred to as I/O pads, in contrast to other conductive pads described above to connect vias within redistribution layers.

The semiconductor package100also includes multiple redistribution layers106deposited on the die102. Although the redistribution layers106are represented by a continuous blocks of color for clarity, it is understood that the redistribution layers106as shown represent multiple layers deposited on top of each other on the die102. In some embodiments, the redistribution layers106include redistribution layers with inorganic passivation or redistribution layers with organic passivation

A redistribution layer generally is an extra metal layer on a chip that makes the I/O connections of an integrated circuit available in other locations of the chip for better access to the pads where necessary. Redistribution layers are also used to house connections between the I/O connections of a die. For example, in some embodiments, the redistribution layers106house traces (not shown) of conductive material (e.g., copper) to provide connections between various input/output connections of the die102. For example, these traces are conductively coupled to conductive pads104of the die102, to pins of the die102for carrying I/O signals, or otherwise coupling I/O connections of the die102. In some embodiments, such traces are placed or housed in the redistribution layers106in a fan out configuration.

Metallization layers108are deposited on the surface of the semiconductor package100. The metallization layers108are layers of a conductive material such as copper, gold, or another conductive metal to provide a conductive surface to which solder bumps110are applied. The solder bumps110are bumps of a solidified conductive alloy composed of tin, copper, silver, bismuth, indium, zinc, antimony, lead, or other metals. For example, the solder bumps110are bumps facilitating a controlled collapse chip connection (C4) connection with the semiconductor package100.

In contrast to the approaches described above where a series of vias and conductive pads would be housed in the redistribution layers106to provide a conductive pathway between the conductive pad104bonded to the die102and the solder bumps110(via the metallization layer108), the semiconductor package100uses conductive inserts112to conductively couple the conductive pads104to the metallization layer108on the surface of the semiconductor package100. The conductive insert112is a continuous (e.g., a single piece of) conductive material such as copper, gold, and the like, that traverses through the redistribution layers106. For example, the conductive insert112is a solid portion of conductive metal, such as a rod or pillar.

To insert the conductive insert112into the semiconductor package100, after application of the redistribution layers106but before application of the metallization layers108, the redistribution layers106are perforated to expose the conductive pads104. In some example, a drill or bore is used to perforate the redistribution layers106to create a housing (e.g., a hole) for the conductive inserts112. In another example, dry or wet etching is used to create the perforations in the redistribution layers106. The conductive insert112is then inserted into the perforations that traverse the redistribution layers, thereby making contact with the conductive pads104. One skilled in the art will appreciate that the conductive inserts112are placed and housed in the perforations with or without a conductive or non-conductive gap-filling material also present in the perforations. One skilled in the art will also appreciate that, in some embodiments, the conductive insert112is either formed prior to insertion or trimmed after insertion to be coplanar with a topmost redistribution layer106onto which the metallization layer108is applied.

After application of the metallization layers108and solder bumps110, a conductive pathway is formed between the solder bumps110and the conductive pad104via the conductive inserts112. One skilled in the art will appreciate that the use of a single, continuous portion of a conductive metal provides advantages over the use of multiple pads and vias in capacitance, resistance, and inductance, providing for a superior signal pathway to the die102.

In some embodiments, high-speed die connections using a conductive insert is used in semiconductor packages that include multiple interconnected dies. For example, as shown inFIG.2, a semiconductor package200includes dies202aand202b. The dies202aand202bare similar to the die102as described inFIG.1. Each of the dies202aand202binclude conductive pads204and redistribution layers206similar to the conductive pads104and redistribution layers106(e.g., organic or inorganic redistribution layers) ofFIG.1.

FIG.2differs fromFIG.1in that the dies202aand202bare deposited on a carrier208. The carrier208provides mechanical support to the semiconductor package200structure. In some embodiments, the carrier208provides a surface for attaching a thermal dissipation device such as a heat sink. The semiconductor package200also includes an encapsulating layer210that fills gaps between the dies202a,band provides additional structural support for the semiconductor package200. For example, in some embodiments, the encapsulating layer210is an epoxy or another polymer material.

The semiconductor package200also includes redistribution layers212. In contrast to the redistribution layers206that are deposited onto a single die202a,b, the redistribution layers212are deposited across both dies202a,b, by virtue of being deposited on the redistribution layers206and encapsulating layer210. In some embodiments, the redistribution layers212are inorganic fabrication redistribution layers (FAB RDLs) of silicon dioxide or another dielectric material. The redistribution layers212house traces214. The traces214are traces of conductive material such as copper, gold, and the like that provide a conductive signal pathway between the dies202a,b. In some embodiments, the traces214of a given redistribution layer212are each coupled to vias or other conductive components that provide conductive pathways between redistribution layers212, thus providing for conductive pathways between the dies202a,bthat traverse multiple redistribution layers212. In some embodiments, the traces214are housed in the redistribution layers212in a fan out configuration.

The semiconductor package200also includes conductive inserts215. The conductive inserts215are inserted into perforations that traverse the redistribution layers206,212and contact the conductive pads204. As withFIG.1, the conductive inserts215are inserted into perforations created through drilling, boring, dry etching, or other approaches as can be appreciated that serve to expose the conductive pads204via the redistribution layers206,212.

The semiconductor package200also includes a power delivery layer216. The power delivery layer216is a redistribution layer that includes components to provide power to various components of the semiconductor package200, such as the dies202a,b. Accordingly, the power delivery layer216includes, for example, connections to power sources, grounds, and the like, as well as traces or other conductive pathways to the components of the semiconductor package200. In this example, the power delivery layer216includes metallization layers218in conductive contact with the conductive inserts215via conductive pillars220of copper, gold, or another conductive material. The conductive pillars220provide a conductive connection between the metallization layers218and conductive inserts215where the metallization layers218are coplanar with the power delivery layer216. Solder bumps222are deposited on the metallization layers218to allow for the semiconductor package200to be installed or connected to other components using a C4 connection or another connection. One skilled in the art will appreciate that, in embodiments where a power delivery layer216is not required, a metallization layer218is applied on the redistribution layers212in contact with the conductive inserts215.

One skilled in the art will appreciate that, in some embodiments, the solder bumps110,222as described inFIGS.1and2are omitted at the time of manufacture and applied later. For example, the semiconductor packages100,200are manufactured without solder such that wires or other components are able to be soldered or otherwise attached to the metallization layers108,218as needed.

FIGS.3A-3Fdepict a fabrication process for a semiconductor package, such as the semiconductor package100as described inFIG.1. Beginning withFIG.3A, a die102is deposited on a carrier302. The die102is composed of a bulk suitable material (e.g., silicon, germanium, or gallium derivatives) and device layers typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over the semiconductor bulk, and patterning the various material layers using photolithography and photomasking to form circuit components and elements (e.g., transistors, capacitors, resistors, etc.). The carrier302provides mechanical support for the semiconductor package during manufacture. The die102includes conductive pads104providing for a connection point to the I/O connections of the die102. The conductive pads104are compose of aluminum, gold, copper, or another conductive metal.

AtFIG.3B, multiple redistribution layers106are applied to the semiconductor package. In some embodiments, the redistribution layers106provide connections between various I/O connections of the die102using conductive traces. In some embodiments, these conductive traces traverse multiple redistribution layers106. For example, these traces are conductively coupled to conductive pads104of the die102, to pins of the die102for carrying I/O signals, or otherwise coupling I/O connections of the die102. In some embodiments, such traces are placed or housed in the redistribution layers106in a fan out configuration. In some embodiments, the redistribution layers106include fabrication back end of line (FAB BEOL) redistribution layers composed of an organic material such as polyamide.

AtFIG.3C, perforations304are added to the semiconductor package. The perforations304traverse through the redistribution layers106and expose the conductive pads104. The perforations are created using drilling, boring, dry etching, or other approaches as can be appreciated.

AtFIG.3D, conductive inserts112are inserted into the perforations304. One skilled in the art will appreciate that the conductive inserts112are placed and housed in the perforations304with or without a conductive or non-conductive gap-filling material also present in the perforations304. One skilled in the art will also appreciate that, in some embodiments, the conductive insert112is either formed prior to insertion or trimmed after insertion to be coplanar with a topmost redistribution layer106of the semiconductor package.

AtFIG.3E, metallization layers108are applied to the semiconductor package. The metallization layers108are layers of conductive metal such as copper, gold, or another conductive metal. The metallization layers108provide a surface for applying solder bumps110, as shown inFIG.3F. Thus, a conductive pathway is formed between the conductive pads104and the solder bumps110via the conductive inserts112.

FIGS.4A-4Hdepict a fabrication process for a semiconductor package, such as the semiconductor package200as described inFIG.2. Beginning withFIG.4A, dies202aand202bare deposited on a carrier402. The dies202a,bare similar to the die102ofFIG.2andFIGS.3A-3Fin that the dies202a,binclude conductive pads204and redistribution layers206. For example, the conductive pads204providing connection points to the I/O connections of the dies202a,b. The redistribution layers206couple various I/O connections of the die202a,busing conductive traces. In some embodiments, these conductive traces traverse multiple redistribution layers206. In some embodiments, the redistribution layers206include fabrication back end of line (FAB BEOL) redistribution layers composed of an organic material such as polyamide.

The carrier402provides mechanical support for the dies202a,b. The dies202a,bare deposited on the carrier402such that the redistribution layers206contact the carrier402in a “face down” configuration. InFIG.4B, an encapsulating layer210is applied to the semiconductor package. The encapsulating layer210provides additional structural support for the semiconductor package, and fills any gaps between the dies202a,b. For example, the encapsulating layer210is applied and then portions of the encapsulating layer210removed such that the encapsulating layer210is coplanar with the dies202a,b.

AtFIG.4C, another carrier208has been attached to the dies202a,b, such that the carrier208is in contact with the dies202a,b. The carrier402has been removed. AtFIG.4Dthe view of semiconductor package has been rotated such that the carrier208is now shown at the bottom of the semiconductor package. Additionally, redistribution layers212have been applied to the semiconductor package. In some embodiments, the redistribution layers212are inorganic fabrication redistribution layers (FAB RDLs) of silicon dioxide or another dielectric material. The redistribution layers212house traces214. The traces214are traces of conductive material such as copper, gold, and the like that provide a conductive signal pathway between the dies202a,b. In some embodiments, the traces214of a given redistribution layer212are each coupled to vias or other conductive components that provide conductive pathways between redistribution layers212, thus providing for conductive pathways between the dies202a,bthat traverse multiple redistribution layers212.

AtFIG.4E, perforations404are added to the semiconductor package. The perforations404traverse through the redistribution layers206,212and expose the conductive pads204. The perforations are created using drilling, boring, dry etching, or other approaches as can be appreciated.

AtFIG.4F, conductive inserts215are inserted into the perforations404. One skilled in the art will appreciate that the conductive inserts215are placed and housed in the perforations404with or without a conductive or non-conductive gap-filling material also present in the perforations404. One skilled in the art will also appreciate that, in some embodiments, the conductive insert215is either formed prior to insertion or trimmed after insertion to be coplanar with a topmost redistribution layer212of the semiconductor package.

AtFIG.4G, a power delivery layer216is applied to the semiconductor package. The power delivery layer216is a redistribution layer that includes components to provide power to various components of the semiconductor package, such as the dies202a,b. Accordingly, the power delivery layer216includes, for example, connections to power sources, grounds, and the like, as well as traces or other conductive pathways to the components of the semiconductor package. In this example, the power delivery layer216includes metallization layers218in conductive contact with the conductive inserts215via conductive pillars220of copper, gold, or another conductive material. The conductive pillars220provide a conductive connection between the metallization layers218and conductive inserts215where the metallization layers218are coplanar with the power delivery layer216. Solder bumps222are deposited on the metallization layers218atFIG.4Hto allow for the semiconductor package to be installed or connected to other components using a C4 connection or another connection.

For further explanation,FIG.5sets forth a flow chart illustrating an exemplary method for high-speed die connections using a conductive insert that includes creating502a perforation in a plurality of redistribution layers of a semiconductor package, wherein the perforation exposes an input/output (I/O) connection point of a die. The die is composed of a bulk suitable material (e.g., silicon, germanium, or gallium derivatives) and device layers typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over the semiconductor bulk, and patterning the various material layers using photolithography and photomasking to form circuit components and elements (e.g., transistors, capacitors, resistors, etc.). In some embodiments, the circuit components are connected to form integrated circuits that implement a functional circuit block of a SoC die, such as a processor, interface, memory, and or other system component.

In some embodiments, the redistribution layers include redistribution layers106deposited on the die, including fabrication back end of line (FAB BEOL) redistribution layers106composed of an organic material such as polyamide. In some embodiments, such redistribution layers106house traces of conductive material (e.g., copper) to couple I/O connections of the die. In some embodiments, the die is one of multiple dies and the redistribution layers include redistribution layers212deposited across the multiple dies (e.g., over redistribution layers106each applied to one of the dies. In some embodiments, the redistribution layers212are inorganic fabrication redistribution layers (FAB RDLs) of silicon dioxide or another dielectric material. The redistribution layers212house traces214. The traces214are traces of conductive material such as copper, gold, and the like that provide a conductive signal pathway between the dies. In some embodiments, the traces214of a given redistribution layer212are each coupled to vias or other conductive components that provide conductive pathways between redistribution layers212, thus providing for conductive pathways between the dies that traverse multiple redistribution layers212. In some embodiments, the traces214are housed in the redistribution layers212in a fan out configuration.

In some embodiments, creating502the perforation includes drilling, boring, or dry etching through the layers of redistribution layers to expose the I/O connection point of the die. For example, the I/O connection point includes a conductive pad bonded to the surface of the die. For example, the conductive pads104composed of aluminum, copper, gold, or another conductive material as can be appreciated.

The method ofFIG.5also includes inserting504, into the perforation, a conductive insert. The conductive insert is a continuous (e.g., a single piece) of conductive material such as copper, gold, and the like, that traverses through the perforated redistribution layers. For example, the conductive insert is a solid portion of conductive metal, such as a rod or pillar. The conductive pillar, when inserted to the perforation, contacts the I/O connection point of the die (e.g., the conductive pad). One skilled in the art will appreciate that the conductive inserts are placed and housed in the perforations with or without a conductive or non-conductive gap-filling material also present in the perforations. One skilled in the art will also appreciate that, in some embodiments, the conductive insert is either formed prior to insertion or trimmed after insertion to be coplanar with a topmost perforated redistribution layer.

The method ofFIG.5also includes applying506a conductive bump to the semiconductor package creating a conductive pathway between the conductive bump and the I/O connection point of the die (e.g., via the conductive insert that is inserted into the perforation). The conductive bump includes a solder bump. The solder bump is an alloy composed of tin, copper, silver, bismuth, indium, zinc, antimony, lead, or other metals. For example, the conductive bumps, when applied, facilitate a controlled collapse chip connection (C4) connection with the semiconductor package.

For further explanation,FIG.6sets forth a flow chart illustrating an exemplary method for high-speed die connections using a conductive insert that includes creating502a perforation in a plurality of redistribution layers of a semiconductor package, wherein the perforation exposes an input/output (I/O) connection point of a die; inserting504, into the perforation, a conductive insert; applying506a conductive bump to the semiconductor package creating a conductive pathway between the conductive bump and the I/O connection point of the die.

The method ofFIG.6differs fromFIG.5in that the method ofFIG.6includes applying602an under bump metallization layer to the semiconductor package. The metallization layer is a layer of conductive material applied over the conductive inserts and the perforations. For example, the metallization layer includes layers of copper, gold, or another conductive metal. The metallization layer provides a suitable surface onto which the conductive bumps (e.g., solder bumps) are applied.

For further explanation,FIG.7sets forth a flow chart illustrating an exemplary method for high-speed die connections using a conductive insert that includes creating502a perforation in a plurality of redistribution layers of a semiconductor package, wherein the perforation exposes an input/output (I/O) connection point of a die; inserting504, into the perforation, a conductive insert; applying506a conductive bump to the semiconductor package creating a conductive pathway between the conductive bump and the I/O connection point of the die.

The method ofFIG.7differs fromFIG.5in that the semiconductor package includes a plurality of dies and the perforated redistribution layers include fabrication redistribution layers (FAB RDLs), such as inorganic fabrication redistribution layers. Accordingly, the method ofFIG.7includes applying702a power delivery layer on the plurality of fabrication redistribution layers. The power delivery layer is a redistribution layer that includes components to provide power to various components of the semiconductor package, such as the dies. Accordingly, the power delivery layer includes, for example, connections to power sources, grounds, and the like, as well as traces or other conductive pathways to the components of the semiconductor package. The power delivery layer also includes metallization layers in conductive contact with the conductive inserts to provide a surface for applying the conductive bumps.

In view of the explanations set forth above, readers will recognize that the benefits of high-speed die connections using a conductive insert include:Improved performance of a computing system by reducing capacitance, series resistance and inductance in conductive pathways from a solder bump to an I/O connection point of a die.

It will be understood from the foregoing description that modifications and changes can be made in various embodiments of the present disclosure. The descriptions in this specification are for purposes of illustration only and are not to be construed in a limiting sense. The scope of the present disclosure is limited only by the language of the following claims.