Patent ID: 12213320

DETAILED DESCRIPTION

As discussed above, the embodiments of the present disclosure are directed to a three-dimensional memory device employing finned support pillar structures and methods of manufacturing the same, the various aspects of which are described below. The finned support pillar structures permit the support pillar structures to be spaced farther apart due to the support for the insulating layers of a layer stack provided by the fins after sacrificial material layers are removed. By spacing the support pillar structures farther apart, more word line metal can be provided into the recesses between the insulating layers, which reduces word line resistance. Furthermore, the fins decrease the amount of deformation of the insulating layers due to compressive stress on the insulating layers after the sacrificial material layers are removed. Finally, the diameter of the core portion of the support openings in which the support pillar structures are located can be reduced. The reduced diameter of the core portion helps control the depth of the support openings during the etching process that forms the support openings.

The embodiments of the disclosure can be employed to form various structures including a multilevel memory structure, non-limiting examples of which include semiconductor devices such as three-dimensional monolithic memory array devices comprising a plurality of NAND memory strings. The drawings are not drawn to scale. Multiple instances of an element may be duplicated where a single instance of the element is illustrated, unless absence of duplication of elements is expressly described or clearly indicated otherwise. Ordinals such as “first,” “second,” and “third” are employed merely to identify similar elements, and different ordinals may be employed across the specification and the claims of the instant disclosure. The term “at least one” element refers to all possibilities including the possibility of a single element and the possibility of multiple elements.

The same reference numerals refer to the same element or similar element. Unless otherwise indicated, elements having the same reference numerals are presumed to have the same composition and the same function. Unless otherwise indicated, a “contact” between elements refers to a direct contact between elements that provides an edge or a surface shared by the elements. If two or more elements are not in direct contact with each other or among one another, the two elements are “disjoined from” each other or “disjoined among” one another. As used herein, a first element located “on” a second element can be located on the exterior side of a surface of the second element or on the interior side of the second element. As used herein, a first element is located “directly on” a second element if there exist a physical contact between a surface of the first element and a surface of the second element. As used herein, a first element is “electrically connected to” a second element if there exists a conductive path consisting of at least one conductive material between the first element and the second element. As used herein, a “prototype” structure or an “in-process” structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component therein.

As used herein, a “layer” refers to a material portion including a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer may be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer may extend horizontally, vertically, and/or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layer thereupon, thereabove, and/or therebelow.

Generally, a semiconductor die, or a semiconductor package, can include a memory chip. Each semiconductor package contains one or more dies (for example one, two, or four). The die is the smallest unit that can independently execute commands or report status. Each die contains one or more planes (typically one or two). Identical, concurrent operations can take place on each plane, although with some restrictions. Each plane contains a number of blocks, which are the smallest unit that can be erased by in a single erase operation. Each block contains a number of pages, which are the smallest unit that can be programmed, i.e., a smallest unit on which a read operation can be performed.

Referring toFIG.1, a first exemplary structure according to an embodiment of the present disclosure is illustrated, which can be employed, for example, to fabricate a device structure containing vertical NAND memory devices. The first exemplary structure includes a substrate (9,10), which can be a semiconductor substrate. The substrate can include a substrate semiconductor layer9and an optional semiconductor material layer10. The substrate semiconductor layer9may be a semiconductor wafer or a semiconductor material layer, and can include at least one elemental semiconductor material (e.g., single crystal silicon wafer or layer), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. The substrate can have a major surface7, which can be, for example, a topmost surface of the substrate semiconductor layer9. The major surface7can be a semiconductor surface. In one embodiment, the major surface7can be a single crystalline semiconductor surface, such as a single crystalline semiconductor surface.

As used herein, a “semiconducting material” refers to a material having electrical conductivity in the range from 1.0×10−6S/cm to 1.0×105S/cm. As used herein, a “semiconductor material” refers to a material having electrical conductivity in the range from 1.0×10−6S/cm to 1.0×105S/cm in the absence of electrical dopants therein, and is capable of producing a doped material having electrical conductivity in a range from 1.0 S/cm to 1.0×105S/cm upon suitable doping with an electrical dopant. As used herein, an “electrical dopant” refers to a p-type dopant that adds a hole to a valence band within a band structure, or an n-type dopant that adds an electron to a conduction band within a band structure. As used herein, a “conductive material” refers to a material having electrical conductivity greater than 1.0×105S/cm. As used herein, an “insulator material” or a “dielectric material” refers to a material having electrical conductivity less than 1.0×10−6S/cm. As used herein, a “heavily doped semiconductor material” refers to a semiconductor material that is doped with electrical dopant at a sufficiently high atomic concentration to become a conductive material either as formed as a crystalline material or if converted into a crystalline material through an anneal process (for example, from an initial amorphous state), i.e., to have electrical conductivity greater than 1.0×105S/cm. A “doped semiconductor material” may be a heavily doped semiconductor material, or may be a semiconductor material that includes electrical dopants (i.e., p-type dopants and/or n-type dopants) at a concentration that provides electrical conductivity in the range from 1.0×10−6S/cm to 1.0×105S/cm. An “intrinsic semiconductor material” refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material may be semiconducting or conductive, and may be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive depending on the atomic concentration of electrical dopants therein. As used herein, a “metallic material” refers to a conductive material including at least one metallic element therein. All measurements for electrical conductivities are made at the standard condition.

At least one semiconductor device700for a peripheral circuitry can be formed on a portion of the substrate semiconductor layer9. The at least one semiconductor device can include, for example, field effect transistors. For example, at least one shallow trench isolation structure720can be formed by etching portions of the substrate semiconductor layer9and depositing a dielectric material therein. A gate dielectric layer, at least one gate conductor layer, and a gate cap dielectric layer can be formed over the substrate semiconductor layer9, and can be subsequently patterned to form at least one gate structure (750,752,754,758), each of which can include a gate dielectric750, a gate electrode (752,754), and a gate cap dielectric758. The gate electrode (752,754) may include a stack of a first gate electrode portion752and a second gate electrode portion754. At least one gate spacer756can be formed around the at least one gate structure (750,752,754,758) by depositing and anisotropically etching a dielectric liner. Active regions730can be formed in upper portions of the substrate semiconductor layer9, for example, by introducing electrical dopants employing the at least one gate structure (750,752,754,758) as masking structures. Additional masks may be employed as needed. The active region730can include source regions and drain regions of field effect transistors. A first dielectric liner761and a second dielectric liner762can be optionally formed. Each of the first and second dielectric liners (761,762) can comprise a silicon oxide layer, a silicon nitride layer, and/or a dielectric metal oxide layer. As used herein, silicon oxide includes silicon dioxide as well as non-stoichiometric silicon oxides having more or less than two oxygen atoms for each silicon atoms. Silicon dioxide is preferred. In an illustrative example, the first dielectric liner761can be a silicon oxide layer, and the second dielectric liner762can be a silicon nitride layer. The least one semiconductor device for the peripheral circuitry can contain a driver circuit for memory devices to be subsequently formed, which can include at least one NAND device.

A dielectric material such as silicon oxide can be deposited over the at least one semiconductor device, and can be subsequently planarized to form a planarization dielectric layer770. In one embodiment the planarized top surface of the planarization dielectric layer770can be coplanar with a top surface of the dielectric liners (761,762). Subsequently, the planarization dielectric layer770and the dielectric liners (761,762) can be removed from an area to physically expose a top surface of the substrate semiconductor layer9. As used herein, a surface is “physically exposed” if the surface is in physical contact with vacuum, or a gas phase material (such as air).

The optional semiconductor material layer10, if present, can be formed on the top surface of the substrate semiconductor layer9prior to, or after, formation of the at least one semiconductor device700by deposition of a single crystalline semiconductor material, for example, by selective epitaxy. The deposited semiconductor material can be the same as, or can be different from, the semiconductor material of the substrate semiconductor layer9. The deposited semiconductor material can be any material that can be employed for the substrate semiconductor layer9as described above. The single crystalline semiconductor material of the semiconductor material layer10can be in epitaxial alignment with the single crystalline structure of the substrate semiconductor layer9. Portions of the deposited semiconductor material located above the top surface of the planarization dielectric layer170can be removed, for example, by chemical mechanical planarization (CMP). In this case, the semiconductor material layer10can have a top surface that is coplanar with the top surface of the planarization dielectric layer770.

The region (i.e., area) of the at least one semiconductor device700is herein referred to as a peripheral device region200. The region in which a memory array is subsequently formed is herein referred to as a memory array region100. A contact region300for subsequently forming stepped terraces of electrically conductive layers can be provided between the memory array region100and the peripheral device region200.

In one alternative embodiment, the peripheral device region200containing the at least one semiconductor device700for a peripheral circuitry may be located under the memory array region100in a CMOS under array configuration. In another alternative embodiment, the peripheral device region200may be located on a separate substrate which is subsequently bonded to the memory array region100.

Referring toFIGS.2A-2Ea stack of an alternating plurality of first material layers (which can be insulating layers32) and second material layers (which can be sacrificial material layer42) is formed over the top surface of the substrate (9,10). As used herein, a “material layer” refers to a layer including a material throughout the entirety thereof. As used herein, an alternating plurality of first elements and second elements refers to a structure in which instances of the first elements and instances of the second elements alternate. Each instance of the first elements that is not an end element of the alternating plurality is adjoined by two instances of the second elements on both sides, and each instance of the second elements that is not an end element of the alternating plurality is adjoined by two instances of the first elements on both ends. The first elements may have the same thickness thereamongst, or may have different thicknesses. The second elements may have the same thickness thereamongst, or may have different thicknesses. The alternating plurality of first material layers and second material layers may begin with an instance of the first material layers or with an instance of the second material layers, and may end with an instance of the first material layers or with an instance of the second material layers. In one embodiment, an instance of the first elements and an instance of the second elements may form a unit that is repeated with periodicity within the alternating plurality.

Each first material layer includes a first material, and each second material layer includes a second material that is different from the first material. In one embodiment, each first material layer can be an insulating layer32, and each second material layer can be a sacrificial material layer. In this case, the stack can include an alternating plurality of insulating layers32and sacrificial material layers42, and constitutes a prototype stack of alternating layers comprising insulating layers32and sacrificial material layers42.

The stack of the alternating plurality is herein referred to as an alternating stack (32,42). In one embodiment, the alternating stack (32,42) can include insulating layers32composed of the first material, and sacrificial material layers42composed of a second material different from that of insulating layers32. The first material of the insulating layers32can be at least one insulating material. As such, each insulating layer32can be an insulating material layer. Insulating materials that can be employed for the insulating layers32include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides that are commonly known as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the insulating layers32can be silicon oxide.

The second material of the sacrificial material layers42is a sacrificial material that can be removed selective to the first material of the insulating layers32. As used herein, a removal of a first material is “selective to” a second material if the removal process removes the first material at a rate that is at least twice the rate of removal of the second material. The ratio of the rate of removal of the first material to the rate of removal of the second material is herein referred to as a “selectivity” of the removal process for the first material with respect to the second material.

According to an aspect of the present disclosure, the sacrificial material layers42comprise at least two types of sacrificial material layers having different densities and different etch rates in an isotropic etchant, such as hot phosphoric acid. For example, the sacrificial material layers42may comprise at least one first sacrificial material layer having a first etch rate in the isotropic etchant, and at least one second sacrificial material layer having a second etch rate in the isotropic etchant that is greater than the first etch rate. The at least one second sacrificial material layer may overly the at least one first sacrificial material layer. In one embodiment, the sacrificial material layers42may comprise at least one third sacrificial material layer having a third etch rate in the isotropic etchant that is greater than the second etch rate. The at least one third sacrificial material layer may overly the second sacrificial material layer. Generally, the sacrificial material layers42may comprise a total of M types of sacrificial material layers having a respective sacrificial material composition. Each i-th type sacrificial material layer overlies each (i−1)-th type sacrificial material layer for each integer i in a range from 2 to M. Each i-th type sacrificial material layer has an i-th etch rate in the isotropic etchant that is greater than the (i−1)-th etch rate in the isotropic etchant of each (i−1)-th type sacrificial material layer for each integer i in a range from 2 to M. The integer M may be in a range from 2 to N, in which N is the total number of sacrificial material layers42. The number N may be in a range from 8 to 1,024, such as from 64 to 256, although lesser and greater numbers may also be employed. The integer M may be in a range from 2 to 1,024, such as from 8 to 256, and/or from 32 to 128.

In an illustrative example, the sacrificial material layers42may comprise at least one first silicon nitride layer having a first etch rate in hot phosphoric acid, and at least one second silicon nitride layer having a second etch rate in hot phosphoric acid that is greater than the first etch rate and overlying the at least one first silicon nitride layer. In one embodiment, the sacrificial material layers42may comprise a third silicon nitride layer having a third etch rate in hot phosphoric acid that is greater than the second etch rate and overlying the second silicon nitride layer. Generally, the sacrificial material layers42may comprise a total of M types of silicon nitride layers having a respective silicon nitride composition. Each i-th type silicon nitride layers overlies each (i−1)-th type silicon nitride layer for each integer i in a range from 2 to M. Each i-th type silicon nitride layer has an i-th etch rate in hot phosphoric acid that is greater than the (i−1)-th etch rate in hot phosphoric acid of each (i−1)-th type silicon nitride layer for each integer i in a range from 2 to M.

In one embodiment, the sacrificial material layers42may comprise silicon nitride layers having different densities in a range from 2.55 g/cm3to 2.80 g/cm3. As shown inFIG.2B, the greater density silicon nitride layers may have a lower etch rate than the lower density silicon nitride layers. The silicon nitride layers may be deposited by a plasma enhanced chemical vapor deposition process in which a lower plasma power leads to a higher density and a higher plasma power leads to a lower density. Therefore, the at least one first silicon nitride layer (e.g., lower silicon nitride layer) may be deposited at a higher plasma power to be more porous and thus have a higher etching rate in hot phosphoric acid. In contrast, the at least one second silicon nitride layer (e.g., upper silicon nitride layer) may be deposited at a lower plasma power to be less porous (i.e., be denser) and thus have a lower etching rate in hot phosphoric acid.

In a first exemplary configuration of the first exemplary structure, the sacrificial material layers42can be numbered with positive integers starting with 1 in the order of proximity from the substrate (9,10), and an overlying sacrificial material layer42can have a lower density and a higher etch rate in an isotropic etchant than an underlying sacrificial material layer42for each pair of sacrificial material layers42within the alternating stack (32,42), as illustrated inFIGS.2C and2D.

In a second exemplary configuration of the first exemplary structure, the sacrificial material layers42can be numbered with positive integers starting with 1 in the order of proximity from the substrate (9,10), and an overlying sacrificial material layer42can have a lower density than or have a same density as, and can have a lower etch rate in an isotropic etchant than or have a same etch rate in an isotropic etchant as, an underlying sacrificial material layer42for each pair of sacrificial material layers42within the alternating stack (32,42), as illustrated inFIGS.2E and2F. The topmost sacrificial material layer42(i.e., the N-th sacrificial material layer42) has a lower density and a higher etch rate in an isotropic etchant than the bottommost sacrificial material layer42(i.e., the first sacrificial material layer42).

In an alternative embodiment, all sacrificial material layers42may have the same density and the same etch rate in an isotropic etchant. For example, all sacrificial material layers may comprise silicon nitride layers having the same density and the same etch rate in hot phosphoric acid.

In one embodiment, the insulating layers32can include a first silicon oxide material, and sacrificial material layers can include silicon nitride sacrificial material layers. The insulating layers32can be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is employed for the insulating layers32, tetraethyl orthosilicate (TEOS) can be employed as the precursor material for the CVD process. The sacrificial material layers42can be formed, for example, by plasma enhanced chemical vapor deposition (CVD) or atomic layer deposition (ALD).

The thicknesses of the insulating layers32and the sacrificial material layers42can be in a range from 20 nm to 50 nm, although lesser and greater thicknesses can be employed for each insulating layer32and for each sacrificial material layer42. The number of repetitions of the pairs of an insulating layer32and a sacrificial material layer (e.g., a control gate electrode or a sacrificial material layer)42can be in a range from 2 to 1,024, and typically from 8 to 256, although a greater number of repetitions can also be employed. The top and bottom gate electrodes in the stack may function as the select gate electrodes. In one embodiment, each sacrificial material layer42in the alternating stack (32,42) can have a uniform thickness that is substantially invariant within each respective sacrificial material layer42.

Optionally, an insulating cap layer70can be formed over the alternating stack (32,42). The insulating cap layer70includes a dielectric material that is different from the material of the sacrificial material layers42. In one embodiment, the insulating cap layer70can include a dielectric material that can be employed for the insulating layers32as described above. The insulating cap layer70can have a greater thickness than each of the insulating layers32. The insulating cap layer70can be deposited, for example, by chemical vapor deposition. In one embodiment, the insulating cap layer70can be a silicon oxide layer.

Referring toFIG.3, stepped surfaces are formed at a peripheral region of the alternating stack (32,42), which is herein referred to as a terrace region. As used herein, “stepped surfaces” refer to a set of surfaces that include at least two horizontal surfaces and at least two vertical surfaces such that each horizontal surface is adjoined to a first vertical surface that extends upward from a first edge of the horizontal surface, and is adjoined to a second vertical surface that extends downward from a second edge of the horizontal surface. A stepped cavity is formed within the volume from which portions of the alternating stack (32,42) are removed through formation of the stepped surfaces. A “stepped cavity” refers to a cavity having stepped surfaces.

The terrace region is formed in the contact region300, which is located between the memory array region100and the peripheral device region200containing the at least one semiconductor device for the peripheral circuitry. The stepped cavity can have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity changes in steps as a function of the vertical distance from the top surface of the substrate (9,10). In one embodiment, the stepped cavity can be formed by repetitively performing a set of processing steps. The set of processing steps can include, for example, an etch process of a first type that vertically increases the depth of a cavity by one or more levels, and an etch process of a second type that laterally expands the area to be vertically etched in a subsequent etch process of the first type. As used herein, a “level” of a structure including alternating plurality is defined as the relative position of a pair of a first material layer and a second material layer within the structure.

Each sacrificial material layer42other than a topmost sacrificial material layer42within the alternating stack (32,42) laterally extends farther than any overlying sacrificial material layer42within the alternating stack (32,42) in the terrace region. The terrace region includes stepped surfaces of the alternating stack (32,42) that continuously extend from a bottommost layer within the alternating stack (32,42) to a topmost layer within the alternating stack (32,42).

Each vertical step of the stepped surfaces can have the height of one or more pairs of an insulating layer32and a sacrificial material layer. In one embodiment, each vertical step can have the height of a single pair of an insulating layer32and a sacrificial material layer42. In another embodiment, multiple “columns” of staircases can be formed along a first horizontal direction hd1such that each vertical step has the height of a plurality of pairs of an insulating layer32and a sacrificial material layer42, and the number of columns can be at least the number of the plurality of pairs. Each column of staircase can be vertically offset among one another such that each of the sacrificial material layers42has a physically exposed top surface in a respective column of staircases. In the illustrative example, two columns of staircases are formed for each block of memory stack structures to be subsequently formed such that one column of staircases provide physically exposed top surfaces for odd-numbered sacrificial material layers42(as counted from the bottom) and another column of staircases provide physically exposed top surfaces for even-numbered sacrificial material layers (as counted from the bottom). Configurations employing three, four, or more columns of staircases with a respective set of vertical offsets among the physically exposed surfaces of the sacrificial material layers42may also be employed. Each sacrificial material layer42has a greater lateral extent, at least along one direction, than any overlying sacrificial material layers42such that each physically exposed surface of any sacrificial material layer42does not have an overhang. In one embodiment, the vertical steps within each column of staircases may be arranged along the first horizontal direction hd1, and the columns of staircases may be arranged along a second horizontal direction hd2that is perpendicular to the first horizontal direction hd1. In one embodiment, the first horizontal direction hd1may be perpendicular to the boundary between the memory array region100and the contact region300.

A retro-stepped dielectric material portion65(i.e., an insulating fill material portion) can be formed in the stepped cavity by deposition of a dielectric material therein. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. Excess portions of the deposited dielectric material can be removed from above the top surface of the insulating cap layer70, for example, by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the retro-stepped dielectric material portion65. As used herein, a “retro-stepped” element refers to an element that has stepped surfaces and a horizontal cross-sectional area that increases monotonically as a function of a vertical distance from a top surface of a substrate on which the element is present. If silicon oxide is employed for the retro-stepped dielectric material portion65, the silicon oxide of the retro-stepped dielectric material portion65may, or may not, be doped with dopants such as B, P, and/or F. In one embodiment, the insulating layers32comprise a first silicon oxide material, and the retro-stepped dielectric material portion65comprises a second silicon oxide material.

Optionally, drain select level isolation structures72can be formed through the insulating cap layer70and a subset of the sacrificial material layers42located at drain select levels. The drain select level isolation structures72can be formed, for example, by forming drain select level isolation trenches and filling the drain select level isolation trenches with a dielectric material such as silicon oxide. Excess portions of the dielectric material can be removed from above the top surface of the insulating cap layer70.

Referring toFIGS.4A and4B, a lithographic material stack (not shown) including at least a photoresist layer can be formed over the insulating cap layer70and the retro-stepped dielectric material portion65, and can be lithographically patterned to form openings therein. The openings are formed over the contact region300. The pattern in the lithographic material stack can be transferred through the insulating cap layer70or the retro-stepped dielectric material portion65, and through the alternating stack (32,42) by at least one anisotropic etch that employs the patterned lithographic material stack as an etch mask. Portions of the alternating stack (32,42) underlying the openings in the patterned lithographic material stack are etched to form support openings19. As used herein, a “support opening” refers to a structure in which a support structure (such as a support pillar structure) that mechanically supports other elements is subsequently formed. The support openings19are formed through the retro-stepped dielectric material portion65and the portion of the alternating stack (32,42) that underlie the stepped surfaces in the contact region300.

The chemistry of the anisotropic etch process employed to etch through the materials of the alternating stack (32,42) can alternate to optimize etching of the first and second materials in the alternating stack (32,42). The anisotropic etch can be, for example, a series of reactive ion etches. The sidewalls of the support openings19can be substantially vertical, or can be tapered. In one embodiment, each of the support openings19can have a top periphery at a horizontal plane including a top surface of the retro-stepped dielectric material portion65, and can have a bottom periphery that adjoins a bottom surface of the support opening19. The maximum lateral dimension (i.e., the lateral dimension between a pair of points having a greatest lateral distance therebetween) of the top periphery of each support opening19can be a top width tw (which may be a diameter of the top periphery or a major axis of the top periphery), and the maximum lateral dimension of the bottom periphery of each support opening19can be a bottom width bw that is the same as or less than the top width tw. The patterned lithographic material stack can be subsequently removed, for example, by ashing.

Referring toFIGS.5A,5B and5C, fin cavities19F can be formed at levels of the sacrificial material layers42around the support openings19. Specifically, the sacrificial material layers42are laterally recessed selective to the insulating layers32around the support openings19by introducing an isotropic etchant that etches the sacrificial material layers42selective to the insulating layers32. For example, if the insulating layers32comprise silicon oxide and if the sacrificial material layers42comprises silicon nitride, a wet etch process employing hot phosphoric acid can be employed as a selective isotropic etch process. The fin cavities19F are formed in volumes from the sacrificial material layers42are etched. A subset of the fin cavities19F that do not border the retro-stepped dielectric material portion65can have a respective cylindrical annular shape.

Each support opening19can include a columnar volume19C that corresponds to the volume of the support opening19as formed at the processing steps ofFIGS.4A and4B, and a set of at least one fin cavity19F that is formed at the processing step ofFIG.5A,5B or5C, and laterally protrude from, and is adjoined to, the columnar volume19F. In one embodiment, a subset of the support openings19may include a combination of a respective columnar volume19C and a respective plurality of fin cavities19F.

In one embodiment shown inFIG.5A, the sacrificial material layers42have different etch rates. Specifically, the upper sacrificial material layers42have a higher etch rate than the lower sacrificial material layers42. In this embodiment, a bottom lateral protrusion distance 1pd_b between the columnar volume19C and a cylindrical sidewall of a bottommost fin cavity19F is smaller than a top lateral protrusion distance 1pd_t between the columnar volume19C and a cylindrical sidewall of a topmost fin cavity19F cavities due to the differences in the etch rate of the sacrificial material layers42. In other words, the fin cavities19F in the lower sacrificial material layers42are wider in the horizontal direction (e.g., have a greater diameter) than the fin cavities19F in the upper sacrificial material layers42.

According to the embodiment of the present disclosure shown inFIG.5A, a set of fin cavities19F may have a variable lateral protrusion distance as measured between the columnar volume19C and a cylindrical sidewall of a respective fin cavity19F, and the variable lateral protrusion distance increases gradually with a vertical distance from the substrate (9,10). In one embodiment, the variable lateral protrusion distance may decrease with a number associated with each of the sacrificial material layers42upon assigning each of the sacrificial material layers42with sequentially increasing integers beginning with 1 and incrementing by 1 in the order of proximity from the substrate (9,10). In another embodiment, the set of fin cavities19F may have a variable lateral protrusion distance as measured between the columnar volume19C and a cylindrical sidewall of a respective fin cavity, and the variable lateral protrusion distance increases stepwise with a vertical distance from the substrate (9,10). In one embodiment, a bottommost fin cavity19F has a bottom fin lateral extent bfle that is a maximum lateral dimension within the bottommost fin cavity19F, a topmost fin cavity19F has a top fin lateral extent tfle that is a maximum lateral dimension within the topmost fin cavity. The bottommost fin lateral extent bfle may be smaller than the topmost fin lateral extent tfle.

In an alternative embodiment shown inFIG.5B, all sacrificial material layers42have the same etch rate and the same density. In this embodiment, all fin cavities19F have the same lateral protrusion distance between the columnar volume19C and a cylindrical sidewall of each fin cavity19F, and the same fin lateral extent.

In another alternative embodiment shown inFIG.5C, the bottommost sacrificial material layer42E may have a different composition from the other sacrificial material layers42. In this embodiment, the bottommost sacrificial material layer42E acts as an etch stop during the etching of the support openings19at the step shown inFIGS.4A and4B. In this embodiment, the support openings19do not extend through the bottommost sacrificial material layer42E, and terminate above the bottom surface of the bottommost sacrificial material layer42E.

In one embodiment shown inFIGS.5A-5C, the columnar volume19C may have a variable lateral extent such that a topmost portion of the columnar volume that is not adjoined to any fin cavity19F has a greater width (such as the top width tw) than a bottommost portion of the columnar volume that19F is not adjoined to any fin cavity19F (such as the bottom width bw).

Generally, a first region, such as the memory array region100of the alternating stack (32,42), includes all layers of the alternating stack (32,42), and can be free of memory openings19. A second region, such as the contact region300, of the alternating stack (32,42) includes stepped surfaces of the alternating stack (32,42), and is referred to as staircase region. The support openings19can be formed in the staircase region. Lateral extents of the sacrificial material layers42decrease with a vertical distance from the substrate (9,10). The retro-stepped dielectric material portion65overlies the stepped surfaces, and the support openings19vertically extend through the retro-stepped dielectric material portion65. A total number of fin cavities per support opening19may differ among the support openings19.

Referring toFIGS.6A-6C, at least one fill material can be deposited in volumes of the support openings19(including the volumes of the fin cavities19F) by a conformal deposition process such as a chemical vapor deposition (CVD) process. In one embodiment, the at least one fill material may include, and/or may consist essentially of, a dielectric fill material, such as silicon oxide. In one embodiment, low pressure chemical vapor deposition may be employed to deposit a silicon oxide material derived from thermal decomposition of tetraethylorthosilicate (TEOS). In an alternative embodiment, the at least one fill material may include plural dielectric fill materials, at least one of which may comprise a metal oxide dielectric fill material, such as aluminum oxide, hafnium oxide, tantalum oxide, etc. For example, the at least one fill material may include a two layer stack of silicon oxide layer and a metal oxide dielectric material layer, or a three layer stack of a first silicon oxide layer, a metal oxide dielectric material layer, and a second silicon oxide layer. The first silicon oxide layer may be deposited conformally on the sidewalls of the support openings19(including the volumes of the fin cavities19F), the metal oxide dielectric material layer may then be deposited conformally on the first silicon oxide located in the support openings19(and optionally in the volumes of the fin cavities19F if they are not completely filled with the first silicon oxide layer), and the second silicon oxide layer may then be deposited on the metal oxide dielectric material layer to fill the remaining volumes of the support openings19. Excess portions of the at least one fill material can be removed from above the horizontal plane including the top surface of the retro-stepped dielectric material portion65. Remaining portions of the at least one fill material in each support opening19comprise an array of support pillar structures20, which can be located in the contact region300.

In one embodiment, each of the support pillar structures20comprises a central columnar structure21(which may be a central dielectric columnar structure) and a set of fins22(which may be a set of dielectric fins) laterally protruding from the central columnar structure21at levels of a subset of a respective subset of the sacrificial material layers42. In one embodiment, the insulating layers32comprise, and/or consist essentially of, a first silicon oxide material, the retro-stepped dielectric material portion comprises, and/or consist essentially of, a second silicon oxide material, and the at least one fill material deposited in the support openings and the fin cavities comprises, and/or consist essentially of, a third silicon oxide material. The first, second and third silicon oxide materials may have the same composition or different compositions.

If the support openings19of the embodiment ofFIG.5Aare used, then a bottom lateral protrusion distance 1pd_b between the central columnar structure21and a cylindrical sidewall of a bottommost fin of the set of fins22may be smaller than a top lateral protrusion distance 1pd_t between the central columnar structure21and a cylindrical sidewall of a topmost fin of the set of fins22due to the differences in the lateral recess distances of the sacrificial material layers42. The set of fins22may have a variable lateral protrusion distance as measured between the central columnar structure21and a cylindrical sidewall of a respective fin22, and the variable lateral protrusion distance increases gradually with a vertical distance from the substrate (9,10).

Alternatively, the set of fins22has a variable lateral protrusion distance as measured between the central columnar structure21and a cylindrical sidewall of a respective fin, and the variable lateral protrusion distance increases stepwise with a vertical distance from the substrate (9,10).

In one embodiment, a bottommost fin within the set of fins22has a bottom fin lateral extent bfle that is a maximum lateral dimension within the bottommost fin, a topmost fin within the set of fins22has a top fin lateral extent tfle that is a maximum lateral dimension with the topmost fin, and the bottommost fin lateral extent bfle is smaller than the topmost fin lateral extent tfle.

Since the lower sacrificial material layers42extend into the end portion of the staircase which contains less total layers (32,42) of the stack, the compressive stress may be lower on the lower sacrificial material layers42than on the upper sacrificial material layers42which are located only in the leading portion of the staircase which contains more total layers (32,42). Therefore, the bottommost fin lateral extent in the lower portion of the stack may be smaller than the topmost fin lateral extent since due to the smaller number of total layers at the end of the staircase. The smaller fin lateral extent permits more conductive material to be filled in the backside recesses in the steps described with respect toFIGS.11and12A-12Dbelow. The additional metal reduces the word line resistance.

In contrast, if the support openings19ofFIG.5Bare used, then the lateral protrusion distance between the central columnar structure21and a cylindrical sidewall of each of the fins22can be the same. Furthermore, all fins22have the same fin lateral extent.

In one embodiment, the central columnar structure21has a variable lateral extent such that a topmost portion of the central columnar structure21that is not adjoined to any fin within the set of fins22has a greater width (such as the top width tw) than a bottommost portion of the central columnar structure that is not adjoined to any fin within the set of fins22(which has the bottom width bw).

In one embodiment, each layer within the alternating stack (32,42) is present within a first region, such as a memory array region100. In one embodiment, a second region that is located outside the first region, such as the contact region300, comprises a staircase region in which lateral extents of the sacrificial material layers42decrease with a vertical distance from the substrate such that the alternating stack (32,42) comprises stepped surfaces. A retro-stepped dielectric material portion65overlies the stepped surfaces, and the support pillar structure20vertically extends through the retro-stepped dielectric material portion65. The support pillar structures20can consist essentially of at least one dielectric material, such as silicon oxide or a dielectric metal oxide. In this case, the support pillar structures20can be dielectric pillar structures.

A plurality of support pillar structures20can be provided as at least one array of support pillar structures20. Each of the support pillar structures20vertically extends through the second region of the alternating stack (32,42), and comprises a respective central columnar structure21and a respective set of fins22that laterally protrude from the respective central columnar structure21at levels of a respective subset of the sacrificial material layers42. A total number of fins22per support pillar structure20differs for at least one pair of support pillar structures20among the support pillar structures20.

Referring toFIGS.7A and7B, a lithographic material stack (not shown) including at least a photoresist layer can be formed over the insulating cap layer70and the retro-stepped dielectric material portion65, and can be lithographically patterned to form openings therein. The openings include a set of openings formed over the memory array region100. The pattern in the lithographic material stack can be transferred through the insulating cap layer70and through the alternating stack (32,42) by at least one anisotropic etch that employs the patterned lithographic material stack as an etch mask. Portions of the alternating stack (32,42) underlying the openings in the patterned lithographic material stack are etched to form memory openings49. As used herein, a “memory opening” refers to a structure in which memory elements, such as a memory stack structure, is subsequently formed. The memory openings49are formed through the insulating cap layer70and the entirety of the alternating stack (32,42) in the memory array region100.

The memory openings49can extend from the top surface of the alternating stack (32,42) to at least the horizontal plane including the topmost surface of the semiconductor material layer10. In one embodiment, an overetch into the semiconductor material layer10may be optionally performed after the top surface of the semiconductor material layer10is physically exposed at a bottom of each memory opening49. The overetch may be performed prior to, or after, removal of the lithographic material stack. In other words, the recessed surfaces of the semiconductor material layer10may be vertically offset from the un-recessed top surfaces of the semiconductor material layer10by a recess depth. The recess depth can be, for example, in a range from 1 nm to 50 nm, although lesser and greater recess depths can also be employed. The overetch is optional, and may be omitted. If the overetch is not performed, the bottom surfaces of the memory openings49can be coplanar with the topmost surface of the semiconductor material layer10.

Each of the memory openings49may include a sidewall (or a plurality of sidewalls) that extends substantially perpendicular to the topmost surface of the substrate. A two-dimensional array of memory openings49can be formed in the memory array region100. The substrate semiconductor layer9and the semiconductor material layer10collectively constitutes a substrate (9,10), which can be a semiconductor substrate. Alternatively, the semiconductor material layer10may be omitted, and the memory openings49can be extend to a top surface of the substrate semiconductor layer9.

FIGS.8A-8Hillustrate structural changes in a memory opening49, which is one of the memory openings49in the first exemplary structure ofFIGS.7A and7B.

Referring toFIG.8A, a memory opening49in the exemplary device structure ofFIGS.7A and7Bis illustrated. The memory opening49extends through the insulating cap layer70, the alternating stack (32,42), and optionally into an upper portion of the semiconductor material layer10. The recess depth of the bottom surface of each memory opening with respect to the top surface of the semiconductor material layer10can be in a range from 0 nm to 30 nm, although greater recess depths can also be employed. Optionally, the sacrificial material layers42can be laterally recessed partially to form lateral recesses (not shown), for example, by an isotropic etch.

Referring toFIG.8B, an optional pedestal channel portion (e.g., an epitaxial pedestal)11can be formed at the bottom portion of each memory opening49and each support openings19, for example, by selective epitaxy. Each pedestal channel portion11comprises a single crystalline semiconductor material in epitaxial alignment with the single crystalline semiconductor material of the semiconductor material layer10. In one embodiment, the pedestal channel portion11can be doped with electrical dopants of the same conductivity type as the semiconductor material layer10. In one embodiment, the top surface of each pedestal channel portion11can be formed above a horizontal plane including the top surface of a sacrificial material layer42. In this case, at least one source select gate electrode can be subsequently formed by replacing each sacrificial material layer42located below the horizontal plane including the top surfaces of the pedestal channel portions11with a respective conductive material layer.

The pedestal channel portion11can be a portion of a transistor channel that extends between a source region to be subsequently formed in the substrate (9,10) and a drain region to be subsequently formed in an upper portion of the memory opening49. A memory cavity49′ is present in the unfilled portion of the memory opening49above the pedestal channel portion11. In one embodiment, the pedestal channel portion11can comprise single crystalline silicon. In one embodiment, the pedestal channel portion11can have a doping of the first conductivity type, which is the same as the conductivity type of the semiconductor material layer10that the pedestal channel portion contacts. If a semiconductor material layer10is not present, the pedestal channel portion11can be formed directly on the substrate semiconductor layer9, which can have a doping of the first conductivity type.

Referring toFIG.8C, a stack of layers including an optional blocking dielectric layer52, a memory material layer54, a dielectric material liner56, and an optional sacrificial cover material layer601can be sequentially deposited in the memory openings49by a respective conformal deposition process.

The optional blocking dielectric layer52can include a single dielectric material layer or a stack of a plurality of dielectric material layers. The blocking dielectric layer52can be formed employing a conformal deposition process. In one embodiment, the blocking dielectric layer can include a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material that includes at least one metallic element and at least oxygen.

The dielectric metal oxide may consist essentially of the at least one metallic element and oxygen, or may consist essentially of the at least one metallic element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer52can include a dielectric metal oxide having a dielectric constant greater than 7.9, i.e., having a dielectric constant greater than the dielectric constant of silicon nitride.

Non-limiting examples of dielectric metal oxides include aluminum oxide (Al2O3), hafnium oxide (HfO2), lanthanum oxide (LaO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), silicates thereof, nitrogen-doped compounds thereof, alloys thereof, and stacks thereof. The dielectric metal oxide layer can be deposited, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), liquid source misted chemical deposition, or a combination thereof. The thickness of the dielectric metal oxide layer can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed. The dielectric metal oxide layer can subsequently function as a dielectric material portion that blocks leakage of stored electrical charges to control gate electrodes. In one embodiment, the blocking dielectric layer52includes aluminum oxide. In one embodiment, the blocking dielectric layer52can include multiple dielectric metal oxide layers having different material compositions.

Alternatively or additionally, the blocking dielectric layer52can include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In one embodiment, the blocking dielectric layer52can include silicon oxide. In this case, the dielectric semiconductor compound of the blocking dielectric layer52can be formed by a conformal deposition method such as low pressure chemical vapor deposition, atomic layer deposition, or a combination thereof. The thickness of the dielectric semiconductor compound can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed. Alternatively, the blocking dielectric layer52can be omitted, and a backside blocking dielectric layer can be formed after formation of backside recesses on surfaces of memory films to be subsequently formed.

Subsequently, the memory material layer54can be deposited as a continuous material layer by a conformal deposition process such as a chemical vapor deposition process or an atomic layer deposition process. The memory material layer54includes a memory material, i.e., a material that can store data by selecting a state of the material. For example, the memory material layer54may include a charge storage material such as silicon nitride, polysilicon, or a metallic material, or a ferroelectric material that can store information in the form of a ferroelectric polarization direction, or any other memory material that can store date by altering electrical resistivity.

The memory material layer54can be formed as a single memory material layer of homogeneous composition, or can include a stack of multiple memory material layers. In one embodiment, the memory material layer54may comprise an insulating charge trapping material, such as a continuous silicon nitride layer or discrete silicon nitride segments. The memory material layer54can be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing electrical charges therein. The thickness of the memory material layer54can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed.

The dielectric material liner56includes a dielectric material. The dielectric material liner56can be formed on the memory material layer54employing a conformal deposition process. In one embodiment, if the memory material layer54comprises a charge storage material, then the dielectric material liner56comprises a tunneling dielectric layer through which charge tunneling can be performed under suitable electrical bias conditions. The charge tunneling may be performed through hot-carrier injection or by Fowler-Nordheim tunneling induced charge transfer depending on the mode of operation of the monolithic three-dimensional NAND string memory device to be formed. The dielectric material liner56can include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicates, alloys thereof, and/or combinations thereof. In one embodiment, the dielectric material liner56can include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which is commonly known as an ONO stack. In one embodiment, the dielectric material liner56can include a silicon oxide layer that is substantially free of carbon or a silicon oxynitride layer that is substantially free of carbon. The thickness of the dielectric material liner56can be in a range from 2 nm to 20 nm, although lesser and greater thicknesses can also be employed.

The optional sacrificial cover material layer601includes a sacrificial material that can be subsequently removed selective to the material of the dielectric material liner56. In one embodiment, the sacrificial cover material layer601can include a semiconductor material such as amorphous silicon, or may include a carbon-based material such as amorphous carbon or diamond-like carbon (DLC). The sacrificial cover material layer601can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the sacrificial cover material layer601can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. A memory cavity49′ is formed in the volume of each memory opening49that is not filled with the deposited material layers (52,54,56,601).

Referring toFIG.8D, the optional sacrificial cover material layer601, the dielectric material liner56, the memory material layer54, and the blocking dielectric layer52overlying the insulating cap layer70are sequentially anisotropically etched employing at least one anisotropic etch process. The portions of the sacrificial cover material layer601, the dielectric material liner56, the memory material layer54, and the blocking dielectric layer52located above the top surface of the insulating cap layer70can be removed by the at least one anisotropic etch process. Further, the horizontal portions of the sacrificial cover material layer601, the dielectric material liner56, the memory material layer54, and the blocking dielectric layer52at a bottom of each memory cavity49′ can be removed to form openings in remaining portions thereof. Each of the sacrificial cover material layer601, the dielectric material liner56, the memory material layer54, and the blocking dielectric layer52can be etched by a respective anisotropic etch process employing a respective etch chemistry, which may, or may not, be the same for the various material layers.

Each remaining portion of the sacrificial cover material layer601can have a tubular configuration. The memory material layer54can comprise a charge trapping material, a floating gate material, a ferroelectric material, or a resistive memory material that can provide at least two different levels of resistivity (such as a phase change material), or any other memory material that can store information by a change in state. In one embodiment, each memory material layer54can include a vertical stack of charge storage regions (e.g., portions of a silicon nitride memory material layer) that store electrical charges upon programming. In one embodiment, the memory material layer54can be a memory material layer in which each portion adjacent to the sacrificial material layers42constitutes a charge storage region.

A surface of the pedestal channel portion11(or a surface of the semiconductor material layer10in case the pedestal channel portions11are not employed) can be physically exposed underneath the opening through the sacrificial cover material layer601, the dielectric material liner56, the memory material layer54, and the blocking dielectric layer52. Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity49′ can be vertically recessed so that the recessed semiconductor surface underneath the memory cavity49′ is vertically offset from the topmost surface of the pedestal channel portion11(or of the semiconductor material layer10in case pedestal channel portions11are not employed) by a recess distance. A dielectric material liner56is located over the memory material layer54. A set of a blocking dielectric layer52, a memory material layer54, and a dielectric material liner56in a memory opening49constitutes a memory film50, which includes a plurality of charge storage regions (as embodied as the memory material layer54) that are insulated from surrounding materials by the blocking dielectric layer52and the dielectric material liner56. In one embodiment, the sacrificial cover material layer601, the dielectric material liner56, the memory material layer54, and the blocking dielectric layer52can have vertically coincident sidewalls. The sacrificial cover material layer601can be subsequently removed selective to the material of the dielectric material liner56. In case the sacrificial cover material layer601includes a semiconductor material, a wet etch process employing hot trimethyl-2 hydroxyethyl ammonium hydroxide (“hot TMY”) or tetramethyl ammonium hydroxide (TMAH) can be performed to remove the sacrificial cover material layer601. Alternatively, the sacrificial cover material layer601may be retained in the final device if it comprises a semiconductor material.

Referring toFIG.8E, a semiconductor channel layer60L can be deposited directly on the semiconductor surface of the pedestal channel portion11or the semiconductor material layer10if the pedestal channel portion11is omitted, and directly on the dielectric material liner56. The semiconductor channel layer60L includes a semiconductor material such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel layer60L includes amorphous silicon or polysilicon. The semiconductor channel layer60L can have a doping of a first conductivity type, which is the same as the conductivity type of the semiconductor material layer10and the pedestal channel portions11. The semiconductor channel layer60L can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel layer60L can be in a range from 2 nm to 10 nm, although lesser and greater thicknesses can also be employed. The semiconductor channel layer60L may partially fill the memory cavity49′ in each memory opening, or may fully fill the cavity in each memory opening.

Referring toFIG.8F, in case the memory cavity49′ in each memory opening is not completely filled by the semiconductor channel layer60L, a dielectric core layer62L can be deposited in the memory cavity49′ to fill any remaining portion of the memory cavity49′ within each memory opening. The dielectric core layer62L includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer62L can be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD), or by a self-planarizing deposition process such as spin coating.

Referring toFIG.8G, the horizontal portion of the dielectric core layer62L can be removed, for example, by a recess etch process such that each remaining portions of the dielectric core layer62L is located within a respective memory opening49and has a respective top surface below the horizontal plane including the top surface of the insulating cap layer70. Each remaining portion of the dielectric core layer62L constitutes a dielectric core62.

Referring toFIG.8H, a doped semiconductor material having a doping of a second conductivity type can be deposited within each recessed region above the dielectric cores62. The deposited semiconductor material can have a doping of a second conductivity type that is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material can be in a range from 5.0×1018/cm3to 2.0×1021/cm3, although lesser and greater dopant concentrations can also be employed. The doped semiconductor material can be, for example, doped polysilicon.

Excess portions of the deposited semiconductor material having a doping of the second conductivity type and a horizontal portion of the semiconductor channel layer60L can be removed from above the horizontal plane including the top surface of the insulating cap layer70, for example, by chemical mechanical planarization (CMP) or a recess etch process. Each remaining portion of the doped semiconductor material having a doping of the second conductivity type constitutes a drain region63. Each remaining portion of the semiconductor channel layer60L (which has a doping of the first conductivity type) constitutes a vertical semiconductor channel60. The vertical semiconductor channel60is formed directly on the dielectric material liner56.

A dielectric material liner56is surrounded by a memory material layer54, and laterally surrounds a portion of the vertical semiconductor channel60. Each adjoining set of a blocking dielectric layer52, a memory material layer54, and a dielectric material liner56collectively constitute a memory film50, which can store electrical charges or electrical polarization with a macroscopic retention time. In some embodiments, a blocking dielectric layer52may not be present in the memory film50at this step, and a backside blocking dielectric layer may be subsequently formed after formation of backside recesses. Furthermore, if the ferroelectric memory material layer54is used, then the tunneling dielectric layer56may be omitted. As used herein, a macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device such as a retention time in excess of 24 hours.

Each combination of a memory film50and a vertical semiconductor channel60within a memory opening49constitutes a memory stack structure55. The memory stack structure55is a combination of a semiconductor channel, a dielectric material liner, a plurality of memory elements as embodied as portions of the memory material layer54, and an optional blocking dielectric layer52. An entire set of material portions (e.g., pedestal channel portion11(if present), a memory stack structure55, a dielectric core62, and a drain region63) that fills a memory opening49is herein referred to as a memory opening fill structure58.

Generally, a memory opening fill structure58can be formed in each memory opening49. The memory opening fill structure58comprises an optional blocking dielectric layer52, a memory material layer54, an optional dielectric material liner56, and a vertical semiconductor channel60. A dielectric material liner56may laterally surround the vertical semiconductor channel60. The memory material layer54can laterally surround the dielectric material liner56.

Referring toFIG.9, the first exemplary structure is illustrated after formation of memory opening fill structures58. An instance of a memory opening fill structure58can be formed within each memory opening49of the structure ofFIGS.7A and7B.

In an alternative embodiment, the memory openings49and the support openings19may be filled with the memory openings fill structures58and support pillar structures20, respectively, during the same deposition steps shown inFIGS.8A-8H. In this alternative embodiment, the step of forming the dielectric support pillar structures20shown inFIGS.6A and6Bis omitted. The support pillar structures20and the memory opening fill structures58contain the same layers and regions (i.e.,50,60and63). However, the support pillar structures20include fins22, while the memory opening fill structures58do not include fins22. Furthermore, the drain regions63of the memory opening fill structures58is electrically connected to bit lines, while the support pillar structures20include dummy drain regions63which are not electrically connected to the bit lines.

Each memory stack structure55includes a vertical semiconductor channel60and a memory film50. The memory film50may comprise a dielectric material liner56laterally surrounding the vertical semiconductor channel60, a vertical stack of charge storage regions (as embodied as memory material layer54) laterally surrounding the dielectric material liner56, and an optional blocking dielectric layer52. While the present disclosure is described employing the illustrated configuration for the memory stack structure, the methods of the present disclosure can be applied to alternative memory stack structures including different layer stacks or structures for the memory film50and/or for the vertical semiconductor channel60.

Referring toFIGS.10A and10B, a contact level dielectric layer73can be formed over the alternating stack (32,42) of insulating layer32and sacrificial material layers42, and over the memory stack structures55and the support pillar structures20. The contact level dielectric layer73includes a dielectric material that is different from the dielectric material of the sacrificial material layers42. For example, the contact level dielectric layer73can include silicon oxide. The contact level dielectric layer73can have a thickness in a range from 50 nm to 500 nm, although lesser and greater thicknesses can also be employed.

A photoresist layer (not shown) can be applied over the contact level dielectric layer73, and is lithographically patterned to form openings in areas between clusters of memory stack structures55. The pattern in the photoresist layer can be transferred through the contact level dielectric layer73, the alternating stack (32,42) and/or the retro-stepped dielectric material portion65employing an anisotropic etch to form backside trenches79, which vertically extend from the top surface of the contact level dielectric layer73at least to the top surface of the substrate (9,10), and laterally extend through the memory array region100and the contact region300.

In one embodiment, the backside trenches79can laterally extend along a first horizontal direction hd1and can be laterally spaced apart among one another along a second horizontal direction hd2that is perpendicular to the first horizontal direction hd1. The memory stack structures55can be arranged in rows that extend along the first horizontal direction hd1. The drain select level isolation structures72can laterally extend along the first horizontal direction hd1. Each backside trench79can have a uniform width that is invariant along the lengthwise direction (i.e., along the first horizontal direction hd1). Each drain select level isolation structure72can have a uniform vertical cross-sectional profile along vertical planes that are perpendicular to the first horizontal direction hd1that is invariant with translation along the first horizontal direction hd1. Multiple rows of memory stack structures55can be located between a neighboring pair of a backside trench79and a drain select level isolation structure72, or between a neighboring pair of drain select level isolation structures72. In one embodiment, the backside trenches79can include a source contact opening in which a source contact via structure can be subsequently formed.

A source region61can be formed at a surface portion of the semiconductor material layer10under each backside cavity79′ by implantation of electrical dopants into physically exposed surface portions of the semiconductor material layer10. An upper portion of the semiconductor material layer10that extends between the source region61and the plurality of pedestal channel portions11constitutes a horizontal semiconductor channel59for a plurality of field effect transistors. The horizontal semiconductor channel59is connected to multiple vertical semiconductor channels60through respective pedestal channel portions11. The horizontal semiconductor channel59contacts the source region61and the plurality of pedestal channel portions11. The photoresist layer can be removed, for example, by ashing.

Referring toFIGS.11and12A, an isotropic etchant that selectively etches the second material of the sacrificial material layers42with respect to the first material of the insulating layers32can be introduced into the backside trenches79, for example, employing an isotropic etch process. Backside recesses43are formed in volumes from which the sacrificial material layers42are removed. The removal of the second material of the sacrificial material layers42can be selective to the first material of the insulating layers32, the material of the retro-stepped dielectric material portion65, the semiconductor material of the semiconductor material layer10, and the material of the outermost layer of the memory films50. In one embodiment, the sacrificial material layers42can include silicon nitride, and the materials of the insulating layers32and the retro-stepped dielectric material portion65can be selected from silicon oxide and dielectric metal oxides. Cylindrical surfaces of the fins22of the support pillar structures20and cylindrical surface segments of the memory opening fill structures58are physically exposed to the backside recesses43.

The etch process that removes the second material selective to the first material and the outermost layer of the memory films50can be a wet etch process employing a wet etch solution, or can be a gas phase (dry) etch process in which the etchant is introduced in a vapor phase into the backside trenches79. For example, if the sacrificial material layers42include silicon nitride, the etch process can be a wet etch process in which the first exemplary structure is immersed within a wet etch tank including phosphoric acid, which etches silicon nitride selective to silicon oxide, silicon, and various other materials employed in the art. The support pillar structure20, the retro-stepped dielectric material portion65, and the memory stack structures55provide structural support while the backside recesses43are present within volumes previously occupied by the sacrificial material layers42.

Each backside recess43can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each backside recess43can be greater than the height of the backside recess43. A plurality of backside recesses43can be formed in the volumes from which the second material of the sacrificial material layers42is removed. The memory openings in which the memory stack structures55are formed are herein referred to as front side openings or front side cavities in contrast with the backside recesses43. In one embodiment, the memory array region100comprises an array of monolithic three-dimensional NAND strings having a plurality of device levels disposed above the substrate (9,10). In this case, each backside recess43can define a space for receiving a respective word line of the array of monolithic three-dimensional NAND strings.

Each of the plurality of backside recesses43can extend substantially parallel to the top surface of the substrate (9,10). A backside recess43can be vertically bounded by a top surface of an underlying insulating layer32and a bottom surface of an overlying insulating layer32. In one embodiment, each backside recess43can have a uniform height throughout.

Physically exposed surface portions of the optional pedestal channel portions11and the semiconductor material layer10can be converted into dielectric material portions by thermal conversion and/or plasma conversion of the semiconductor materials into dielectric materials. For example, thermal conversion and/or plasma conversion can be employed to convert a surface portion of each pedestal channel portion11into a tubular dielectric spacer116, and to convert each physically exposed surface portion of the semiconductor material layer10into a planar dielectric portion616. In one embodiment, each tubular dielectric spacer116can be topologically homeomorphic to a torus, i.e., generally ring-shaped. As used herein, an element is topologically homeomorphic to a torus if the shape of the element can be continuously stretched without destroying a hole or forming a new hole into the shape of a torus. The tubular dielectric spacers116include a dielectric material that includes the same semiconductor element as the pedestal channel portions11and additionally includes at least one non-metallic element such as oxygen and/or nitrogen such that the material of the tubular dielectric spacers116is a dielectric material. In one embodiment, the tubular dielectric spacers116can include a dielectric oxide, a dielectric nitride, or a dielectric oxynitride of the semiconductor material of the pedestal channel portions11. Likewise, each planar dielectric portion616includes a dielectric material that includes the same semiconductor element as the semiconductor material layer and additionally includes at least one non-metallic element such as oxygen and/or nitrogen such that the material of the planar dielectric portions616is a dielectric material. In one embodiment, the planar dielectric portions616can include a dielectric oxide, a dielectric nitride, or a dielectric oxynitride of the semiconductor material of the semiconductor material layer10.

Referring toFIG.12B, a backside blocking dielectric layer44can be optionally formed. The backside blocking dielectric layer44, if present, comprises a dielectric material that functions as a control gate dielectric for the control gates to be subsequently formed in the backside recesses43. In case the blocking dielectric layer52is present within each memory opening, the backside blocking dielectric layer44is optional. In case the blocking dielectric layer52is omitted, the backside blocking dielectric layer44is present.

The backside blocking dielectric layer44can be formed in the backside recesses43and on a sidewall of the backside trench79. The backside blocking dielectric layer44can be formed directly on horizontal surfaces of the insulating layers32and sidewalls of the memory stack structures55within the backside recesses43. If the backside blocking dielectric layer44is formed, formation of the tubular dielectric spacers116and the planar dielectric portion616prior to formation of the backside blocking dielectric layer44is optional. In one embodiment, the backside blocking dielectric layer44can be formed by a conformal deposition process such as atomic layer deposition (ALD). The backside blocking dielectric layer44can consist essentially of aluminum oxide. The thickness of the backside blocking dielectric layer44can be in a range from 1 nm to 15 nm, such as 2 to 6 nm, although lesser and greater thicknesses can also be employed.

The dielectric material of the backside blocking dielectric layer44can be a dielectric metal oxide such as aluminum oxide, a dielectric oxide of at least one transition metal element, a dielectric oxide of at least one Lanthanide element, a dielectric oxide of a combination of aluminum, at least one transition metal element, and/or at least one Lanthanide element. Alternatively or additionally, the backside blocking dielectric layer44can include a silicon oxide layer. The backside blocking dielectric layer44can be deposited by a conformal deposition method such as chemical vapor deposition or atomic layer deposition. The backside blocking dielectric layer44is formed on the sidewalls of the backside trenches79, horizontal surfaces and sidewalls of the insulating layers32, the portions of the sidewall surfaces of the memory stack structures55that are physically exposed to the backside recesses43, and a top surface of the planar dielectric portion616. A backside cavity79′ is present within the portion of each backside trench79that is not filled with the backside blocking dielectric layer44.

Referring toFIG.12C, a metallic barrier layer46A can be deposited in the backside recesses43. The metallic barrier layer46A includes an electrically conductive metallic material that can function as a diffusion barrier layer and/or adhesion promotion layer for a metallic fill material to be subsequently deposited. The metallic barrier layer46A can include a conductive metallic nitride material such as TiN, TaN, WN, or a stack thereof, or can include a conductive metallic carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metallic barrier layer46A can be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metallic barrier layer46A can be in a range from 2 nm to 8 nm, such as from 3 nm to 6 nm, although lesser and greater thicknesses can also be employed. In one embodiment, the metallic barrier layer46A can consist essentially of a conductive metal nitride such as TiN.

Referring toFIGS.12D and13, a metal fill material is deposited in the plurality of backside recesses43, on the sidewalls of the at least one the backside trench79, and over the top surface of the contact level dielectric layer73to form a metallic fill material layer46B. The metallic fill material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metallic fill material layer46B can consist essentially of at least one elemental metal. The at least one elemental metal of the metallic fill material layer46B can be selected, for example, from tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metallic fill material layer46B can consist essentially of a single elemental metal. In one embodiment, the metallic fill material layer46B can be deposited employing a fluorine-containing precursor gas such as WF6. In one embodiment, the metallic fill material layer46B can be a tungsten layer including a residual level of fluorine atoms as impurities. The metallic fill material layer46B is spaced from the insulating layers32and the memory stack structures55by the metallic barrier layer46A, which is a metallic barrier layer that blocks diffusion of fluorine atoms therethrough.

A plurality of electrically conductive layers46can be formed in the plurality of backside recesses43, and a continuous metallic material layer46L can be formed on the sidewalls of each backside trench79and over the contact level dielectric layer73. Each electrically conductive layer46includes a portion of the metallic barrier layer46A and a portion of the metallic fill material layer46B that are located between a vertically neighboring pair of dielectric material layers such as a pair of insulating layers32. The continuous metallic material layer46L includes a continuous portion of the metallic barrier layer46A and a continuous portion of the metallic fill material layer46B that are located in the backside trenches79or above the contact level dielectric layer73.

Each sacrificial material layer42can be replaced with an electrically conductive layer46. A backside cavity79′ is present in the portion of each backside trench79that is not filled with the backside blocking dielectric layer44and the continuous metallic material layer46L. A tubular dielectric spacer116laterally surrounds a pedestal channel portion11. A bottommost electrically conductive layer46laterally surrounds each tubular dielectric spacer116upon formation of the electrically conductive layers46.

Referring toFIGS.14A and14B, the deposited metallic material of the continuous electrically conductive material layer46L is etched back from the sidewalls of each backside trench79and from above the contact level dielectric layer73, for example, by an isotropic wet etch, an anisotropic dry etch, or a combination thereof. Each remaining portion of the deposited metallic material in the backside recesses43constitutes an electrically conductive layer46. Each electrically conductive layer46can be a conductive line structure. Thus, the sacrificial material layers42are replaced with the electrically conductive layers46.

Each electrically conductive layer46can function as a combination of a plurality of control gate electrodes located at a same level and a word line electrically interconnecting, i.e., electrically shorting, the plurality of control gate electrodes located at the same level. The plurality of control gate electrodes within each electrically conductive layer46are the control gate electrodes for the vertical memory devices including the memory stack structures55. In other words, each electrically conductive layer46can be a word line that functions as a common control gate electrode for the plurality of vertical memory devices.

In one embodiment, the removal of the continuous electrically conductive material layer46L can be selective to the material of the backside blocking dielectric layer44. In this case, a horizontal portion of the backside blocking dielectric layer44can be present at the bottom of each backside trench79. In another embodiment, the removal of the continuous electrically conductive material layer46L may not be selective to the material of the backside blocking dielectric layer44or, the backside blocking dielectric layer44may not be employed. The planar dielectric portions616can be removed during removal of the continuous electrically conductive material layer46L. A backside cavity79′ is present within each backside trench79.

Referring toFIGS.15A and15B, an insulating material layer can be formed in the backside trenches79and over the contact level dielectric layer73by a conformal deposition process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. The insulating material layer includes an insulating material such as silicon oxide, silicon nitride, a dielectric metal oxide, an organosilicate glass, or a combination thereof. In one embodiment, the insulating material layer can include silicon oxide. The insulating material layer can be formed, for example, by low pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The thickness of the insulating material layer can be in a range from 1.5 nm to 60 nm, although lesser and greater thicknesses can also be employed.

If a backside blocking dielectric layer44is present, the insulating material layer can be formed directly on surfaces of the backside blocking dielectric layer44and directly on the sidewalls of the electrically conductive layers46. If a backside blocking dielectric layer44is not employed, the insulating material layer can be formed directly on sidewalls of the insulating layers32and directly on sidewalls of the electrically conductive layers46.

An anisotropic etch is performed to remove horizontal portions of the insulating material layer from above the contact level dielectric layer73and at the bottom of each backside trench79. Each remaining portion of the insulating material layer constitutes an insulating spacer74. A backside cavity79′ is present within a volume surrounded by each insulating spacer74. A top surface of the semiconductor material layer10can be physically exposed at the bottom of each backside trench79.

A bottommost electrically conductive layer46provided upon formation of the electrically conductive layers46within the alternating stack (32,46) can comprise a select gate electrode for the field effect transistors. Each source region61is formed in an upper portion of the semiconductor substrate (9,10). Semiconductor channels (59,11,60) extend between each source region61and a respective set of drain regions63. The semiconductor channels (59,11,60) include the vertical semiconductor channels60of the memory stack structures55.

A backside contact via structure76can be formed within each backside cavity79′. Each contact via structure76can fill a respective cavity79′. The contact via structures76can be formed by depositing at least one conductive material in the remaining unfilled volume (i.e., the backside cavity79′) of the backside trench79. For example, the at least one conductive material can include a conductive liner76A and a conductive fill material portion76B. The conductive liner76A can include a conductive metallic liner such as TiN, TaN, WN, TiC, TaC, WC, an alloy thereof, or a stack thereof. The thickness of the conductive liner76A can be in a range from 3 nm to 30 nm, although lesser and greater thicknesses can also be employed. The conductive fill material portion76B can include a metal or a metallic alloy. For example, the conductive fill material portion76B can include W, Cu, Al, Co, Ru, Ni, an alloy thereof, or a stack thereof.

The at least one conductive material can be planarized employing the contact level dielectric layer73overlying the alternating stack (32,46) as a stopping layer. If chemical mechanical planarization (CMP) process is employed, the contact level dielectric layer73can be employed as a CMP stopping layer. Each remaining continuous portion of the at least one conductive material in the backside trenches79constitutes a backside contact via structure76.

The backside contact via structure76extends through the alternating stack (32,46), and contacts a top surface of the source region61. If a backside blocking dielectric layer44is employed, the backside contact via structure76can contact a sidewall of the backside blocking dielectric layer44.

Alternatively, the above described insulating material layer can be formed in the backside trenches79to completely fill the entire volume of a backside trench79and may consist essentially of at least one dielectric material. In this alternative embodiment, the source region61and the backside trench via structure76may be omitted, and a horizontal source line (e.g., direct strap contact) may contact a side of the lower portion of the semiconductor channel60.

Referring toFIGS.16A and16B, additional contact via structures (88,86,8P) can be formed through the contact level dielectric layer73, and optionally through the retro-stepped dielectric material portion65. For example, drain contact via structures88can be formed through the contact level dielectric layer73on each drain region63. Word line contact via structures86can be formed on the electrically conductive layers46through the contact level dielectric layer73, and through the retro-stepped dielectric material portion65. Peripheral device contact via structures8P can be formed through the retro-stepped dielectric material portion65directly on respective nodes of the peripheral devices.

If the vias filled with the word line contact via structures86are misaligned during their formation by photolithography and etching, then such vias may overlap with the support openings19filled with the support pillar structures20. The etching of the misaligned vias through the silicon oxide retro-stepped dielectric material portion65may also etch away the silicon oxide material of the support pillar structures20and expose portions of the support openings19. In such a case, formation of the word line contact via structures86in the exposed portions of the support openings19may cause a short circuit between several vertically separated electrically conductive layers46in the alternating stack. However, in the embodiment in which the support pillar structure20includes a stack including at least one silicon oxide layer and a metal oxide dielectric material layer, the metal oxide dielectric material layer acts as a lateral etch stop during the etching of the misaligned vias and prevents plural electrically conductive layers from being exposed in the misaligned vias. This prevents short circuits between several vertically separated electrically conductive layers46in the alternating stack even if the vias are misaligned and overlap with the support pillar structures20.

Referring to all drawings and according to various embodiments of the present disclosure, a three-dimensional memory device is provided, which comprises: an alternating stack of insulating layers32and electrically conductive layers46; memory openings49vertically extending through a first region100of the alternating stack; memory opening fill structures58located in the memory openings49and comprising a respective vertical stack of memory elements located levels of the electrically conductive layers46; and a support pillar structure20vertically extending through a second region300of the alternating stack and comprising a central columnar structure21and a set of fins22laterally protruding from the central columnar structure21at levels of a subset of the electrically conductive layers46.

In one embodiment, the vertical stack of memory elements comprises portions of a memory material layer54, each of the memory opening fill structures58lacks the fins22, and each of the memory opening fill structures58further comprises a respective vertical semiconductor channel60. The central columnar structure21and the fins22can have a circular horizontal cross sectional shape, with the fins having a larger diameter than the central columnar structure.

Although the foregoing refers to particular preferred embodiments, it will be understood that the disclosure is not so limited. It will occur to those of ordinary skill in the art that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the disclosure. Compatibility is presumed among all embodiments that are not alternatives of one another. The word “comprise” or “include” contemplates all embodiments in which the word “consist essentially of” or the word “consists of” replaces the word “comprise” or “include,” unless explicitly stated otherwise. Where an embodiment employing a particular structure and/or configuration is illustrated in the present disclosure, it is understood that the present disclosure may be practiced with any other compatible structures and/or configurations that are functionally equivalent provided that such substitutions are not explicitly forbidden or otherwise known to be impossible to one of ordinary skill in the art. All of the publications, patent applications and patents cited herein are incorporated herein by reference in their entirety.