Patent ID: 12261218

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “upper,” “on,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the terms such as “first,” “second” and “third” describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another. The terms such as “first,” “second” and “third” when used herein do not imply a sequence or order unless clearly indicated by the context.

As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation.

Along the development of semiconductor industry, it has been a trend to fabricate as many semiconductor devices as possible on a single chip. For example, different semiconductor devices operated at ranges of low voltages, medium voltages, and high voltages are manufactured in a single chip. Generally, these semiconductor devices with different operating voltages are manufactured using different processes. For example, semiconductor devices manufactured by the replacement gate technology, also known as high-k metal gate (HKMG) technology, may be applied in the low-voltage devices. However, there are concerns in integrating the processes of manufacturing high-voltage devices or medium-voltage devices with those of manufacturing low-voltage devices, especially for the 28-nm technology node and beyond. To increase the yield of device integration, various factors should be considered, such as various device dimensions, e.g., different gate dielectric thicknesses, channel lengths, and/or channel widths of devices with different operating voltages. Also, since planarization processes are needed when fabricating the devices (used for planarizing metals or interlayer dielectrics for example), the dishing effect (applied to the high-voltage devices or medium-voltage devices with large device areas) may degrade the device performance.

Embodiments of a semiconductor structure and a forming method thereof are therefore provided. The semiconductor structure may have a first-voltage device disposed in a first device region and a second-voltage device disposed in a second device region. In some embodiments, the method for forming the semiconductor structure includes forming the recessed gate electrodes of the high/medium-voltage devices with segments. The method further includes forming a protection structure prior to the forming of the low-voltage devices to provide structural support during the planarization processes.

FIG.1is a flowchart representing a method100for forming a semiconductor structure200according to aspects of one or more embodiments of the present disclosure. The method100for forming the semiconductor structure200includes an operation102where a substrate is received. The method100further includes an operation104where a recess is etched in the substrate. In some embodiments, the recess includes a plurality of first portions extending in parallel along a first direction. The method100further includes an operation106where a gate dielectric layer is deposited on sidewalls and a bottom of the recess. The method100further includes an operation108where a gate electrode layer is formed over the gate dielectric layer. The method100further includes an operation110where a planarization operation is performed to remove excess portions of the gate dielectric layer and the gate electrode layer. In some embodiments, the planarization stops on the surface of the substrate to form a gate structure. In some embodiments, the gate structure includes a plurality of first segments extending in parallel.

FIGS.2through26Bare schematic drawings illustrating the semiconductor structure200at different fabrication stages constructed according to aspects of one or more embodiments of the present disclosure.

FIG.2is a top view illustrating the semiconductor structure200at a fabrication stage constructed according to aspects of one or more embodiments of the present disclosure. Referring toFIG.2, a substrate202is received or formed. The respective step is shown as operation102of the method100shown inFIG.1. The substrate202may be a semiconductor wafer such as a silicon wafer. Alternatively or additionally, the substrate202may include elementary semiconductor materials, compound semiconductor materials, or alloy semiconductor materials. Examples of elementary semiconductor materials may be, for example but not limited thereto, single crystal silicon, polysilicon, amorphous silicon, germanium (Ge), and/or diamond. Examples of compound semiconductor materials may be, for example but not limited thereto, silicon carbide (SiC), gallium arsenic (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb). Examples of alloy semiconductor material may be, for example but not limited thereto, SiGe, GaAsP, AlinAs, AlGaAs, GaInA s, GaInP, and/or GaInAsP. The substrate202may also be a bulk semiconductor substrate or a Semiconductor-On-Insulator (SOI) substrate. In accordance with some exemplary embodiments, the substrate202is doped with p-type impurities. In alternative embodiments, the substrate202is doped with n-type impurities.

The substrate202may include various device regions. In some embodiments, the substrate202includes a first device region202aand a second device region202b. The first device region202aand the second device region202bmay include different devices with different operating voltage ranges. For example, the first device region202ais a first-voltage device region in which a first-voltage device210a(seeFIG.25B) is formed. The second device region202bis a second-voltage device region in which a second-voltage device210b(seeFIG.25B) is formed. The second-voltage device210bis configured to operate at operating voltages (or supply voltages) lower than the respective operating voltages (or supply voltages) of the first-voltage device210a. In accordance with some exemplary embodiments, the first device region202ais a high-voltage (HV) MOS device region or a medium-voltage (MV) MOS device region, while the second device region202bis a low-voltage (LV) MOS device region.

It is appreciated that the HV, MV, and LV MOS devices are related each other in their operating voltages. The HV MOS devices are configured to operate at a voltage range (or supply voltages) higher than that of the MV MOS devices, and the MV MOS devices are configured to operate at a voltage range (or supply voltages) higher than that of the LV MOS devices. Also, the maximum allowable voltages in the MV MOS devices are lower than the maximum allowable voltages in HV MOS devices, and the maximum allowable voltages in the LV MOS devices are lower than the maximum allowable voltages in the MV MOS devices. In accordance with some exemplary embodiments, the operating voltages (or the supply voltages) of the HV MOS devices are between about 25 V and about 30 V, the operating voltages (or the supply voltages) of the MV MOS devices are between about 3.0 V and about 20 V, and the operating voltages (or the supply voltages) of the LV MOS devices are between about 0.5 V and about 3.0 V.

FIGS.3through6andFIGS.7A through7Cillustrate the formation of shallow trench isolation (STI) regions. Referring toFIG.3, a pad layer204and a mask layer206are formed over the substrate202. The pad layer204may include a thin film formed of silicon oxide, which may be formed, for example, using a thermal oxidation process. The pad layer204may serve as an adhesion layer between the substrate202and the mask layer206. The pad layer204may also serve as an etch stop layer during etching the mask layer206. In accordance with some embodiments of the present disclosure, the mask layer206is formed of silicon nitride, which may be formed, for example, using Low-Pressure Chemical Vapor Deposition (LPCVD), thermal nitridation of silicon, Plasma-Enhanced Chemical Vapor Deposition (PECVD), or plasma anodic nitridation. The mask layer206may be used as a hard mask during subsequent photolithography process.

Referring toFIG.4, a photo resist layer208is formed on the mask layer206and is then patterned to form openings212. The mask layer206and the pad layer204are etched through the openings212, exposing the underlying substrate202. The exposed substrate202is then etched, forming trenches214. The photo resist layer208is then removed.

Referring toFIG.5, dielectric material(s)216is filled into the trenches214. In some embodiments, the dielectric material216includes a liner oxide lining the bottoms and the sidewalls of the opening212. The liner oxide may be a thermal oxide layer forming by oxidizing a surface layer of the exposed substrate202. In other embodiments, the liner oxide is formed using a deposition technique that can form conformal oxide layers. In some embodiments, after the formation of the liner oxide, the remaining portions of the trenches214are filled with another dielectric material. In some embodiments, the filling material includes silicon oxide, and other dielectric materials such as SiN, SiC, SiON, or the like, may also be used.

Referring toFIG.6, a planarization such as Chemical Mechanical Polish (CMP) is then performed to remove excess portions of the dielectric material216over the top surface of the mask layer206. The mask layer206may serve as a CMP stop layer. The remaining portion of the dielectric material216forms isolation structures218. In some embodiments, the bottom surfaces of isolation structures218are substantially level with each other.

Referring toFIGS.7A-7C, in subsequent steps, the mask layer206and the pad layer204are removed. In some embodiments, the mask layer206and the pad layer204are removed by etching processes. In some embodiments, the isolation structures218may have a ring-shaped. The isolation structures218may be interposed between the regions containing different device types. In some embodiments, the isolation structures218separates the first device region202afrom the second device region202b.

Referring toFIGS.8A-8C, a photo resist layer220is formed over the substrate202and patterned to form one or more openings222. Several portions of the substrate202may be exposed through the opening222. In some embodiments, one or more portions in the first device region202aof the substrate202are exposed through the opening222, while the second device region202bof the substrate202is covered by the photo resist layer220. The photo resist layer220may further cover the isolation structures218in the first device region202aand the second device region202b.

Referring toFIGS.9A-9C, the portion of the exposed substrate202is patterned, forming one or more recesses224in the first device region202a. The respective step is shown as operation104of the method100shown inFIG.1. The recess224includes one or more first portions224-1extending in parallel along a first direction D1. The recess224may further include one or more second portions224-4extending in parallel along a second direction D2.

The patterning operation may involve an etching operation using the photo resist layer220as an etching mask. The etching may be performed through a dry etching process using an etching gas. The etching may also be performed through a wet etching process using one or more suitable etchants. As a result of the etching, upper portions of the substrate202in the first device region202aare removed. In some embodiments, a depth of the recess224may be less than a depth of the isolation structure218. In alternative embodiments, the depth of the recess224may be substantially same as the depth of the isolation structure218. The depth of the recess224is determined by various factors, such as the thickness of the gate dielectric242and the thickness of the gate electrode244to be formed (seeFIGS.13B-13C). For example, the depth of the recess224is so selected that the thickness of the gate dielectric242may meet the voltage-sustaining requirement for HV MOS devices or MV MOS devices. The etching process may be adjusted to determine the maximum allowable voltage and the saturation current of the resulting HV MOS device or MV MOS device. After the etching, the photo resist layer220is removed.

FIGS.10A through10Cillustrate the formation of a plurality of doped regions through a plurality of implantation processes. The plurality of doped regions may include a deep well region232, at least two shallow doped regions234in the first device region202aand a deep well region236in the second device region202b. In some embodiments, the deep well regions232and236are p-type regions, and the shallow doped regions234are n-type regions. In alternative embodiments, the deep well regions232and236are n-type regions, and the shallow doped regions234are p-type regions. The implantation processes for forming the deep well regions232,236, and the shallow doped regions234may be arranged in any order.

In some embodiments, a photo resist layer (not shown) may be formed to cover the substrate202. The region in which the deep well region232and the shallow doped regions234are to be formed is exposed to the opening of the photo resist layer. In some embodiments, p-type dopants, such as boron and/or indium, are implanted into substrate202to form the deep well region232. In some embodiments, n-type dopants, such as phosphorous, arsenic, and/or antimony, are implanted to form the shallow doped regions234. The photo resist layer is then removed after the implantation operation is completed.

In some embodiments, another photo resist layer (not shown) is formed to cover the substrate202, with the region in which the deep well region236is to be formed exposed to the opening of the photo resist layer. An implantation may be then performed in order to form deep well region236. The deep well region236may be implanted with p-type dopants. In some embodiments, the deep well region236has an impurity concentration greater than that of the deep well region232. The photo resist layer is then removed after the implantation operation is completed.

FIGS.11A-11B,12A-12B and13A-13Cillustrate the formation of a gate structure240. The gate structure240may include a gate dielectric242and a gate electrode244in the first device region202a. Referring toFIGS.11A and11B, a gate dielectric layer243is formed over the substrate202. The respective step is shown as operation106of the method100shown inFIG.1. In some embodiments, the gate dielectric layer243is formed over the substrate202in a conformal manner. The gate dielectric layer243may be deposited within the recess224. In some embodiments, the gate dielectric layer243is formed to cover the sidewalls and the bottoms of the recess224. The thickness T1of the gate dielectric layer243may be configured based on different requirements for different semiconductor devices. For example, when the gate dielectric242to be formed is used as an HV MOS device or an MV MOS device, the thickness T1of the gate dielectric242is substantially in a range from about 100 angstroms (Å) to about 200 angstroms.

Referring toFIGS.12A and12B, a gate electrode layer245is formed over the substrate202. The respective step is shown as operation108of the method100shown inFIG.1. In some embodiments, the gate electrode layer245is formed over the substrate202in a gap-filling manner. The gate electrode layer245fills the recess224. The remaining portions of the recess224left by the gate dielectric layer243may be filled with the gate electrode layer245. The gate electrode layer245is formed from conductive material(s). The gate electrode layer245may include undoped polycrystalline silicon. In alternative embodiments, the gate electrode layer245is formed with doped semiconductive material e.g., doped polycrystalline silicon, or other suitable conductive materials e.g., metal.

Referring toFIGS.13A through13C, a planarization such as CMP is then performed to remove excess portions of the gate dielectric layer243and the gate electrode layer245, until the top surface of the isolation structure218or the top surface of the substrate202is exposed. The respective step is shown as operation110of the method100shown inFIG.1. The remaining portions of the gate dielectric layer243and the gate electrode layer245form a gate structure240. The gate structure240includes a gate dielectric242and a gate electrode244. The gate electrode244is disposed within the substrate202. The gate dielectric242is disposed within the substrate202and laterally surrounds the gate electrode244. In some embodiments, the top surface of the gate structure240is substantially level with the top surface of the isolation structure218, after the planarization. In some embodiments, the top surface of the gate structure240is substantially level with the top surface of the substrate202, after the planarization.

As shown inFIG.13A, the gate structure240has one or more first segments240-1extending along a first direction D1. The first segments240-1may extend parallel to each other. The gate structure240further has one or more second segments240-2extending along a second direction D2. The second segments240-2may extend in parallel. The first segments240-1may be physically or electrically connected to the second segments240-2. For example, a first segment240-1in a first row is physically or electrically connected to a first segment240-1in a second row through the second segment240-2. Also, the first segment240-1in the second row is physically or electrically connected to a first segment240-1in the third row through the second segment240-2. One or more portions (e.g., the deep well region232) of the substrate202may be exposed from the gate structure240. The layout of the gate structure240may be configured based on different requirements for different semiconductor devices. In some other embodiments, the first segments240-1may not be parallel to each other. For example, each of the first segments240-1has multiple sections forming a piece-linear segment240-1, in which each section may or may not be parallel to each other. In another embodiments, the first segments240-1may be in a serpent or meandered shape extending between the opposite shallow doped regions234.

The gate structure240may a width W1and a length L1. The width W1may be greater than or substantially equal to the length L1. In some embodiments, the length L1is greater than the width W1. The width W1may be in the range between about 0.2 μm and about 200 μm in accordance with some embodiments. The length L1may be in the range between about 0.2 μm and about 200 μm in accordance with some embodiments. The width W1and the length L1may be configured based on different requirements for different semiconductor devices.

The first segment240-1may have a width W2. In some embodiments, each of the first segments240-1has a substantially equal width W2. In alternative embodiments, the widths of the first segments240-1are different. The width W2may be in the range between about 0.2 μm and about 200 μm in accordance with some embodiments.

The second segment240-2may have a width W3. In some embodiments, each of the second segments240-2has a substantially equal width W3. In alternative embodiments, the widths of the second segments240-2are different. The width W3may be in the range between about 0.2 μm and about 200 μm in accordance with some embodiments.

A spacing S1is arranged between two adjacent first segments240-1. The spacing S1may be in the range between about 0.2 μm and about 200 μm in accordance with some embodiments. The width W2may be greater than the spacing S1. In some embodiments, a ratio W2/S1is greater than or equal to 4. The width W2, the width W3and the spacing S1may be configured based on different requirements for different semiconductor devices.

In some comparative embodiments, a gate structure240is formed without segments (e.g., a plate-shaped gate structure). A total area of the gate structure240of the present embodiment is defined as X. A total area of the gate structure240of the comparative embodiment is defined as Y. A ratio X/Y may be in the range between about 70% and about 90% in accordance with some embodiments. The ratio X/Y may be also referred to as a pattern density of the gate structure240. In other words, the pattern density of the gate structure240may be in the range between about 70% and about 90%. The pattern density of the gate structure240may be configured based on different requirements for different semiconductor devices.

As shown inFIG.13B, the bottom surface of the gate structure240may be higher than the bottom surfaces of the isolation structures218. In alternative embodiments, the bottom surface of the gate structure240is level with the bottom surfaces of the isolation structures218. The thickness T2of the gate electrode244may be configured based on different requirements for different semiconductor devices. For example, when the gate electrode244is used as an HV MOS device or an MV MOS device, the thickness T2of the gate electrode244is substantially in a range from about 700 angstroms (Å) to about 1,000 angstroms.

As shown inFIG.13C, at least a portion of the top surface of the substrate202may be exposed after the planarization process. For example, at least a portion of the top surface of the deep well region232is exposed after the planarization process. In some embodiments, at least a portion of the substrate202is interposed between the segments240-1or240-2of the gate structure240. For example, at least a portion of the deep well region232of the substrate202is interposed between two adjacent first segments240-1.

The proposed layout of the gate structure240provides advantages. In cases where the gate structure240is formed of a plate without connected segments (e.g., a plate-shaped gate structure240), the plate-shaped gate structure240may undergo severe dishing effect during the planarization. For example, when a planarization process is performed to remove excess portions of the gate dielectric layer243and the gate electrode layer245, the planarization process will remove portions of the gate dielectric layer243and the gate electrode layer245to expose underlying features (e.g., the top surface of the substrate202and the top surface of isolation structures218) for subsequent processing (e.g., forming the second-voltage device210b). However, due to the different etching rates of the various types of materials disposed within the plate-shaped gate structure240and the substrate202(e.g., dielectric, metal, polysilicon, etc.), the planarization process may cause dishing in the gate dielectric242or the gate electrode244. In some instances, the dishing may cause undesired removal of the gate electrode244or the gate dielectric242. Also, the dishing effects may affect the dimensions of the channel273of the first-voltage device210ato be formed subsequently. For example, in cases where the gate structure240is formed as a plate-shaped gate structure240, the channel dimension of the first-voltage device210amay be less than 20 μm times 20 μm.

The proposed layout of the gate structure240may help alleviating the dishing effect. The gate structure240of the present embodiment includes a plurality of segments240-1or240-2. At least a portion of the substrate202(or a least a portion of the deep well region232) is interposed between the segments240-1or240-2. The presence of the portion of the substrate202(or the deep well region232) between the segments240-1or240-2may provide structural support and serve as an etch stop layer during the planarization process. The presence of the portion of the substrate202(or the deep well region232) may mitigate the dishing effect in the gate structure240. Moreover, due to the structural support of the substrate202(or the deep well region232), the dimensions of the channel273of the first-voltage device210amay be increased. In some embodiments, the channel dimension of the first-voltage device210amay be increased to about 200 μm times 200 μm, but the present disclosure is not limited thereto.

FIGS.14A-14B and15A-15Cillustrate the formation of a protection structure253. Referring toFIGS.14A-14B, a protecting layer251is formed over the substrate202. The protecting layer251may cover the top surface of the gate structure240, e.g., the top surface of the gate electrode244and/or the top surface of the gate dielectric242. In some embodiments, the protecting layer251further covers the top surface of the shallow doped regions234, the top surfaces of the isolation structures218, and the top surface of the deep well region236.

The protecting layer251may include a monolayer structure or a multilayer structure. The formation of the protecting layer251may include depositing blanket dielectric layers. In some embodiments, the protecting layer251include silicon nitride, and other dielectric materials such as SiOx, SiC, SiON, or the like, may also be used.

Referring toFIGS.15A-15C, a photo resist layer (not shown) is formed over the protecting layer251and is then patterned to form openings exposing portions of the protecting layer251. The exposed portions of the protecting layer251are etched through the openings of the photo resist layer. The photo resist layer is then removed, the remaining portions of the protecting layer251form a protection structure253.

As shown inFIG.15A, the deep well region232extends in a first direction D1within the substrate202. In some embodiments, the gate structure240overlaps at least a portion of the deep well region232and extends in a second direction D2different from the first direction D1. The second direction D2may be perpendicular to the first direction D1. The protection structure253may cover the top surface of the gate dielectric242and the top surface of the gate electrode244. As illustrated inFIGS.15B and15C, the protection structure253may further cover a portion of the top surface of the shallow doped region234or a portion of the top surface of the deep well region232. In some embodiments, at least a portion of the substrate202is exposed from the protection structure253. For example, at least a portion of the deep well region232is exposed from the protection structure253.

The protection structure253overlaps the top surface of the gate dielectric242in a top-view perspective. The protection structure253may be electrically isolated from the gate structure240. In some embodiments, the protection structure253overlaps the entire top surface of the gate dielectric242. The protection structure253may resemble the configuration of the gate structure240. The protection structure253may have one or more first portions253-1extending in the first direction D1and one or more second portions253-2extending in the second direction D2. In some embodiments, the first portions253-1overlap the corresponding first segments240-1of the gate structure240from a top-view perspective. In some embodiments, the second portions253-2overlap the corresponding second segments240-2of the gate structure240from a top-view perspective. In alternative embodiments, the protection structure253has configurations different from the gate structure240. For example, the protection structure253is a plate-shaped protection structure253that cover the exposed portions of the substrate202(or the deep well region232) between the first segments240-1.

The gate structure240may a width Wpand a length Lp. The width Wpmay be greater than or substantially equal to the width W1. The length Lpmay be greater than or substantially equal to the length L1. The width Wpand the length Lpmay be configured based on different requirements for different semiconductor devices.

The first portion253-1may have a width W4. The width W4may be greater than or substantially equal to the width W2. In some embodiments, each of the first portions253-1has a substantially equal width W4. In alternative embodiments, the widths of the first portions253-1are different. The second portions253-2may have a width W4. The width W5may be greater than or substantially equal to the width W3. In some embodiments, each of the second portions253-2has a substantially equal width W4. In alternative embodiments, the widths of the second portions253-2are different. A spacing S2is arranged between two adjacent first portions253-1. The spacing S2may be less than the spacing S1. The width W4, the width W5and the spacing S2may be configured based on different requirements for different semiconductor devices.

As shown inFIG.15B, the protection structure253has a height H1. The height H1of the protection structure253may be configured based on different requirements for different semiconductor devices. For example, the height H1of the protection structure253may be configured based on the height of the second-voltage device210bto be formed in the second device region202b. In some embodiments, the height H1of the protection structure253is substantially in a range from about 300 angstroms (Å) to about 500 angstroms.

Next, referring toFIGS.16A-16B, one or more gate stacks360are formed in the second device region202b. The gate stacks360may be removed in subsequent steps and replaced by their respective replacement gates. Accordingly, the gate stacks360are dummy gates in accordance with some embodiments. The gate stack360includes a gate dielectric362and a gate electrode364. The gate dielectric362may be formed of silicon oxide, silicon nitride, silicon carbide, or the like. The gate electrode364may include conductive layers. The gate electrode364may include polysilicon in accordance with some embodiments. The gate electrode364may also be formed of other conductive materials such as metals, metal alloys, metal silicides, metal nitrides, and/or the like. In some embodiments, the gate stack360further includes hard mask366, respectively. The hard mask366may be formed of silicon nitride, for example, while other materials such as silicon carbide, silicon oxynitride, and the like may also be used. In accordance with alternative embodiments, the hard mask366is not formed.

In some embodiments, the top surface of the gate stack360formed in the second device region202bare substantially level with the top surface of the protection structure253. The gate stack360may have a height H2substantially equal to the height H1of the protection structure253. In some embodiments, the height H2of the gate stack360is substantially in a range from about 300 angstroms (Å) to about 500 angstroms. In some embodiments, the protection structure253may serve as a blocking layer for the gate structure240during the formation of the gate stacks360. Thus, the gate stacks360may only be formed in the second device region202bin some embodiments.

Referring toFIGS.17A-17B, gate spacers258and368are formed on the sidewalls of the protection structure253and the gate stack360, respectively. In accordance with some embodiments, each of the gate spacers258and368includes a multilayer structure, e.g., the gate spacers258or368may include a silicon oxide layer and a silicon nitride layer on the silicon oxide layer. The formation may include depositing blanket dielectric layers, and then performing an anisotropic etching to remove the horizontal portions of the blanket dielectric layers. The available deposition methods include PECVD, LPCVD, sub-atmospheric chemical vapor deposition (SACVD), and other deposition methods. In some embodiments, the gate spacers258and368may be formed during a same formation process, and thus are formed of the same materials.

Referring toFIGS.18A-18B, source regions and drain regions (collectively referred to as source/drain regions hereinafter)270and370are formed in the first device region202aand the second device region202b. In some embodiments, doped regions (not shown) may be formed in the first device region202a. For example, the doped region may be formed in the deep well region232. In some embodiments, a photo resist (not shown) is formed over the substrate202to define the location of the source/drain regions270and370, and the doped regions. In addition, the source/drain regions270and370, and the doped regions may be formed in a single formation process, and thus have the same depth, and are formed of the same materials. In some embodiments, the photo resist is formed to cover the entire protection structure253. Thus, doped regions are not formed in the deep well region232or the substrate202.

Referring to the first device region202a, the source/drain regions270may be formed in the shallow doped regions234. One of the source/drain regions270formed in the shallow doped regions234serves as the source region, and the other one of the source/drain regions270formed in the shallow doped regions234serves as the drain region. A channel273is formed directly underlying the gate dielectric242for conducting an electric current between the source/drain regions270. The source/drain regions270are arranged on opposite sides of the deep well region232. The channel273may be formed in the upper portion of the deep well region232. Referring to the second device region202b, the source/drain regions370are formed in the deep well region236.

In some embodiments, the source/drain regions270and370may be formed simultaneously in a same implantation process. In some embodiments, the source/drain regions270and370are of n-type, and are heavily doped, and thus are referred to as N+ regions. As shown inFIG.18A, the source/drain regions270may be spaced apart from the gate dielectric242by the protection structure253and the gate spacer258. Further, the source/drain regions270and370may have edges aligned with the edges of the gate spacers258and368, respectively. In alternative embodiments, the doped regions formed in the deep well region232have edges aligned with the edges of the gate spacers258.

Referring toFIGS.19A-19C, a pattering operation is performed on the protection structure253to form the protection structure250. In some embodiments, a photo resist layer (not shown) is formed over the protection structure253. The photo resist layer is then patterned to form openings exposing portions of the protection structure253. The exposed portions of the protection structure253are etched using the patterned photo resist layer as an etching mask. The photo resist layer is then removed. The un-etched portions of the protection structure253forms the protection structure250. The protection structure250includes openings252exposing the at least a portion of the gate electrode244. In some embodiments, at least a portion of the gate electrode244is covered by the protection structure250. In addition, the top surface of the gate dielectric242is covered by the protection structure250. In some embodiments, the protection structure250covers an entirety of the gate dielectric242. The protection structure250may contact and overlap the gate dielectric242. The protection structure250may further contact and overlap a portion of the gate electrode244and a portion of the shallow doped regions234.

As shown inFIG.19A, a top view of the protection structure250, the gate spacer258, the gate structure240, the deep well region232, the shallow doped regions234and the source/drain regions270are illustrated. The width Wpand the length Lpof the protection structure253may be kept unchanged during the patterning process. The protection structure250may have the width Wpand the length Lpsame as those of the protection structure253. In some embodiments, the protection structure250includes the opening252after the patterning process. The opening252may include a first dimension S3and a second dimension S4. The first dimension S3may be less than the width W2of the first segment240-1of the gate structure240. The second dimension S4may be less than the width W3of the second segment240-2of the gate structure240.

Referring toFIGS.20A-20B, silicide regions274and374are formed in the first device region202aand the second device region202b, respectively. The formation process may include forming a resist protective oxide (RPO) over portions of the substrate202that are not protected by the gate spacers258and368, and the protection structure250. The RPO may function as a silicide blocking layer during the formation of the silicide regions274and374. The silicide regions274and374may be formed using silicidation such as self-aligned silicide (salicide), in which a metallic material is formed over the substrate202, the temperature is raised to anneal the substrate202and cause reaction between underlying silicon of the substrate202and the metal to form silicide, and un-reacted metal is etched away. The silicide regions274and374may be formed in a self-aligned manner on various features, such as the source/drain regions270and370and/or the gate electrode244, to reduce contact resistance at the interface between these features and the conductive components subsequently formed on the silicide regions274or374.

Referring toFIGS.21A-21B, an inter-layer dielectric (ILD) layer276is formed over the substrate202. The ILD layer276is blanket formed to a height higher than the top surfaces of the gate stack360. In some embodiments, the ILD layer276is blanket formed to a height higher than the top surfaces of the protection structure250. The ILD layer276may be formed of an oxide using, for example, flowable chemical vapor deposition (FCVD). The ILD layer276may also be a spin-on glass formed using spin-on coating. For example, the ILD layer276may be formed of phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), tetraethyl orthosilicate (TEOS) oxide, TiN, SiOC, or other low-k dielectric materials.

Referring toFIGS.22A-22B,FIGS.22A-22Billustrate a planarization step, which is performed using, for example, CMP. The CMP is performed to remove excess portions of the ILD layer276, until the gate stack360is exposed. Since the top surface of the protection structure250is level with the top surface of the gate stack360, the protection structure250is also exposed from the ILD layer276, after the planarization step. The planarization may be stopped on the hard mask366, if it is present. Alternatively, the hard mask366is removed in the planarization, and the gate electrode364is exposed. The protection structure250may serve as a support element for the surrounding ILD layer276. The protection structure250may prevent unwanted dishing from occurring over the first device region202a. Accordingly, by reducing the dishing effect, the performance of the first-voltage devices210amay be improved and the cost of manufacturing may be reduced.

FIGS.23A-23B and24A-24Billustrate the formation of replacement gate stack(s)380in accordance with some embodiments. Referring toFIG.23A, the gate stack360(FIG.22A) is removed. In some embodiments, the gate stack360is removed to form a gate trench378in the ILD layer276. In some embodiments, a dry etching operation is performed to remove the gate stack360. In some embodiments, the dry etching operation uses F-containing plasma, Cl-containing plasma and/or Br-containing plasma to remove the gate stack360. In some embodiments, the protection structure250remains in place during the removal of the gate stack360.

In some embodiments, the substrate202may include various device regions, and the various device regions may include various n-type or p-type MOS devices and/or one or more passive devices such as a resistor. These different devices may include different types of elements. In some embodiments, when an I/O MOS device is used, the gate dielectric362(FIG.22A) can serve as an interfacial layer (IL). Thus, the gate dielectric362may not be removed. In alternative embodiments, when a core MOS device is used, the gate dielectric362is removed to thereby expose the substrate202to the gate trench378.

Referring toFIGS.24A-24B, the gate stack360(FIG.22A) are replaced by replacement gate stack380. The gate stack380includes a gate dielectric382and a gate electrode384. The gate dielectric382may include a high-k dielectric material such as hafnium oxide, lanthanum oxide, aluminum oxide, or the like. The gate electrode384may include conductive layers. In some embodiments, the gate electrode384may include at least a barrier metal layer, a work functional metal layer and a gap-filling metal layer. The barrier metal layer may include, for example but not limited to, TiN. The work function metal layer may include a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi or TiAlC, or a multilayer of two or more of these materials, but is not limited to the above-mentioned materials. In some embodiments, the gap-filling metal layer includes a conductive material such as Al, Cu, AlCu, or W, but is not limited to the above-mentioned materials. The formation methods include PVD, CVD, or the like. In addition, the gate electrode384may be formed in a single formation process, and are formed of the same dielectric materials.

A planarization operation (for example, a CMP) is then performed to remove excess portions of the gate dielectric382and the gate electrode384, leaving the structure shown inFIG.24A. Referring to the first device region202a, at least a portion of the protection structure250may be removed during the planarization operation. For example, the top portion of the protection structure250may be removed. The height of the protection structure250may be reduced. In some embodiments, the protection structure250has a reduced height less than the height H1of the protection structure253, after the planarization operation.

Based on the operations with reference toFIGS.23A-23B and24A-24B, an exemplary first-voltage device210aand an exemplary second-voltage device210bare thus formed. The first-voltage device210aincludes the gate electrode244, the gate dielectric242, and the source/drain regions270. The second-voltage device210bincludes the gate electrode384, the gate dielectric382, and the source/drain regions370. The protection structure250formed over the first-voltage device210amay protect the underlying gate dielectric242and the underlying gate electrode244during the planarization of the ILD layer276. The protection structure250may further serve as spacers for the gate structure240.

In accordance with some embodiments, the first-voltage device210ais a MV MOS device or a HV MOS device, while the second-voltage device210bis a LV MOS device. In some embodiments, the gate dielectric242of the first-voltage device210ais thick enough to sustain the medium voltages or high voltages. The thickness of the gate dielectric382is thinner than the thickness of the gate dielectric242.

The proposed structures provide advantages. In cases where the protection structure250is otherwise absent, the gate dielectric242and the gate electrode244may directly contact the ILD layer276. When a planarization process is performed on the ILD layer276, the planarization process will remove portions of the ILD layer276to expose underlying features of the gate stack360for subsequent processing (e.g., etching for the formation of replacement gate stack380). However, due to the various types of features formed in the level of the ILD layer276(e.g., dielectric, metal, polysilicon, etc.), the planarization process may cause dishing in the ILD layer276(as the various materials are removed at different rates during the planarization process). In some severe instances, the dishing may cause improperly removal of the underlying gate electrode244or the gate dielectric242. Also, the dishing effects may affect the dimensions of the channel273of the first-voltage device210a. For example, in cases where the protection structure250is otherwise absent, the channel dimension of the first-voltage device210amay be reduced to about 20 μm times 20 μm, which may not meet the design requirements.

The presence of the protection structure250may provide structural support during the planarization process. The presence of the protection structure250may mitigate the dishing effect in the ILD layer276. Moreover, due to the structural support of the protection structure250, the dimensions of the channel273of the first-voltage device210amay be increased. In some embodiments, the channel dimension of the first-voltage device210amay be increased, e.g., to about 200 μm times 200 μm, but the present disclosure is not limited thereto. Further, the presence of the protection structure250may serve as an additional spacer, in addition to the gate spacer258, between the gate dielectric242and the source/drain regions270.

FIGS.25A-25Cillustrates the formation of a dielectric layer290and contact plugs292and392. For the purpose of clarity,FIG.25Aonly illustrates the gate structure240, the protection structure250, the gate spacers258, the deep well region232, the shallow doped regions234, the source/drain regions270, and the contact plugs292. Initially, the dielectric layer290is formed over the protection structure250and the replacement gate stack380. The dielectric layer290may be formed of a material selected from the same candidate materials for forming the ILD layer276. The materials of the ILD layer276and the dielectric layer290may be the same or different from each other.

Referring toFIGS.25A and25B, contact plugs292and392are formed in the dielectric layer290and the ILD layer276. The formation process may include forming contact plug openings in the ILD layer276and the dielectric layer290to expose the source/drain regions270/370, the gate electrode244and the gate electrode384, and filling the contact plug openings to form the contact plugs292and392. In some embodiments, the contact plugs292on the gate electrode244may be referred to as gate vias of the first-voltage device210a. In some embodiments, at least one of the contacts plugs292on the gate electrode244is between two first segments250-1of the protection structure250. A bias voltage may thus be supplied through the contact plug292to the gate electrode244.

Referring toFIG.25A, the contact plugs292on the gate electrode244may be referred to as gate vias of the first-voltage device210a. In some embodiments, the gate vias292are configured over the gate electrode244at a location where the gate electrode244does not overlap the deep well region232. In alternative embodiments, at least a portion of the gate vias292lands on the gate electrode244at a location where the gate electrode244overlaps the deep well region232.

Referring toFIGS.26A-26B, an interconnect structure310is arranged over the dielectric layer290. The interconnect structure310may comprise one or more inter-metal dielectric (IMD) layers312. The IMD layer312may comprise, for example, one or more layers of an oxide, a low-k dielectric, or an ultra-low-k dielectric. The IMD layer312may surround conductive patterns (including metal wires and metal vias)314that comprise, for example, copper, tungsten, and/or aluminum. In some embodiments, the contact plugs292are configured to electrically couple the source/drain regions270of the first-voltage device210ato a first conductive pattern314of the interconnect structure310. In some embodiments, the contact plugs392are configured to electrically couple the source/drain regions370of the second-voltage device210bto the first conductive pattern314of the interconnect structure310.

The interconnect structure310may comprise one or more dielectric layers316and318disposed between the IMD layers312. The dielectric layers316and318may serve as etch stop layers. In some embodiments, the dielectric layers316include dielectric materials, such as SiN, SiCN, SiCO, combinations thereof, or the like. In some embodiments, the dielectric316includes a multilayer structure, e.g., formed of a nitride layer and an oxide layer. In some embodiments, the dielectric layers318include silicon nitride, silicon carbide, and the like. In some embodiments, the interconnection structure310further includes barrier layers, such as formed of Ta or TaN, between the IMD layers312and the conductive patterns314.

An under-bump metallization (UBM) stack320is arranged over the interconnect structure310. In some embodiments, the UBM stack320comprises a passivation layer322and a UBM layer324. In some embodiments, the passivation layer322comprises one or more layers of SiO2, silicon nitride (Si3N4), polyimide compounds, or other suitable materials. The passivation layer322may include a single-layered structure or a multiple layered structure. For example, the passivation layer322may be a bi-layered structure as shown inFIG.31, but the disclosure is not limited thereto. In some embodiments, the bi-layered passivation layer322may include a first dielectric layer322aand a second dielectric layer322b. The UBM layer324contacts an upper conductive feature (e.g., a conductive pattern314) of the interconnect structure310. The UBM layer324may comprise, for example, aluminum, titanium, tungsten, or some other suitable material. The UBM layer324is configured to provide an interface between an overlying solder bump (not shown) and an underlying conductive feature (e.g., a conductive pattern314) of the interconnect structure310.

The structures of the present disclosure are not limited to the above-mentioned embodiments, and may have other different embodiments. To simplify the description and for the convenience of comparison between each of the embodiments of the present disclosure, the identical components in each of the following embodiments are marked with identical numerals. For making it easier to compare the difference between the embodiments, the following description will detail the dissimilarities among different embodiments and the identical features will not be repeated.

FIG.27illustrates a top view of a semiconductor structure400at a fabrication stage according to aspects of one or more embodiments of the present disclosure. For the purpose of clarity,FIG.27is similar toFIG.13Ain many aspects, in which only illustrates the gate structure240, the deep well region232, the shallow doped regions234, and the contact plugs292according to aspects of one or more embodiments of the present disclosure. Referring toFIG.27, one or more third segments240-3are formed between the second segments240-2as discussed in previous paragraphs. The third segment240-3may include a width W3substantially equal to that of the second segment240-2as discussed previously. A spacing S5between two adjacent third segments240-3may be in the range between about 0.2 μm and about 200 μm in accordance with some embodiments. A spacing S6between the second segment240-2and an adjacent third segments240-3may be in the range between about 0.2 μm and about 200 μm in accordance with some embodiments. The spacing S5and the spacing S6may be configured based on different requirements for different semiconductor devices.

FIG.28illustrates a top view of a semiconductor structure500at a fabrication stage according to aspects of one or more embodiments of the present disclosure.FIG.28is similar toFIG.27in many aspects, andFIG.28only illustrates the gate structure240, the deep well region232, the shallow doped regions234, and the contact plugs292for the purpose of clarity. Referring toFIG.28, only a second segment540-2is formed instead of the two second segments240-2mentioned previously. The second segment540-2may include a width W3substantially equal to that of the second segment240-2as discussed previously.

FIG.29illustrates a top view of a semiconductor structure600at a fabrication stage according to aspects of one or more embodiments of the present disclosure.FIG.29is similar toFIG.28in many aspects, andFIG.29only illustrates the gate structure240, the deep well region232, the shallow doped regions234, and the contact plugs292for the purpose of clarity. Referring toFIG.29, at least one of the second segments240-2(FIG.13A) mentioned previously is divided into two or more sub-segments640-2. The sub-segments640-2may include a width W3substantially equal to that of the second segment240-2as discussed previously. The sub-segments640-2may include a length L2. The length L2may be greater than or substantially equal to a sum of the spacing S1and the two times the width W2. In some embodiments, each of the sub-segments640-2includes a same length L2. In alternative embodiments, the sub-segments640-2include different lengths. The length L2may be configured based on different requirements for different semiconductor devices.

The embodiments of the present disclosure have some advantageous features. It is desirable to incorporate the HV/MV MOS devices with the LV MOS devices in a single semiconductor substrate. However, the planarization for forming the recessed gate electrodes of the HV/MV MOS devices may result in loss of the recessed gate electrodes of the HV/MV MOS devices. Further, the planarization for exposing the dummy gate electrodes of the LV MOS devices may also result in loss of the recessed gate electrodes of the HV/MV MOS devices. By forming the recessed gate electrodes of the HV/MV MOS devices with segments, the planarization for the formation of the recessed gate electrodes may be performed without loss of the gate electrodes in HV/MV MOS devices. Further, by forming a protection structure to cover the HV/MV MOS devices, the planarization for exposing the dummy gate electrodes may be performed without causing the loss the gate electrodes of HV/MV MOS devices.

In accordance with some embodiments of the present disclosure, a semiconductor structure includes: a substrate; a doped region within the substrate; a pair of source/drain regions extending along a first direction on opposite sides of the doped region; a gate electrode disposed in the doped region, wherein the gate electrode has a plurality of first segments between the pair of source/drain regions; and a protection structure overlapping the gate electrode.

In accordance with some embodiments of the present disclosure, a semiconductor structure includes: a substrate comprising a first region and a second region, the substrate including a surface; a first gate structure arranged within the substrate in the first region; a protection structure arranged in the first region over the first gate structure and at least partially exposing the first gate structure; and a second gate structure arranged over the surface in the second region.

In accordance with some embodiments of the present disclosure, a method includes: receiving a substrate; etching a recess in the substrate, wherein the recess includes a plurality of first portions extending in parallel along a first direction; forming a doped region in the substrate covering a sidewall of the recess; forming two source/drain regions on opposite sides of the doped region in the substrate; and depositing a gate electrode layer in the recess to form a gate electrode, wherein the gate electrode includes a plurality of first segments extending in parallel between the two source/drain regions.

The foregoing outlines structures of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.