Patent ID: 12211586

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

The terms used in this specification generally have their ordinary meanings in the art and in the specific context where each term is used. The use of examples in this specification, including examples of any terms discussed herein, is illustrative only, and in no way limits the scope and meaning of the disclosure or of any exemplified term. Likewise, the present disclosure is not limited to various embodiments given in this specification.

It will be understood that, although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

As used herein, the terms “comprising,” “including,” “having,” “containing,” “involving,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to.

Reference throughout the specification to “one embodiment,” “an embodiment,” or “some embodiments” means that a particular feature, structure, implementation, or characteristic described in connection with the embodiment(s) is included in at least one embodiment of the present disclosure. Thus, uses of the phrases “in one embodiment” or “in an embodiment” or “in some embodiments” in various places throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, implementation, or characteristics may be combined in any suitable manner in one or more embodiments.

FIG.1is a schematic diagram illustrating a memory device100in accordance with various embodiments of the present disclosure. In embodiments illustratively shown inFIG.1, the memory device100includes a memory array120including several bit cells BC arranged on multiple rows and columns. As shown in the memory array120, these bit cells BC on the same column are connected to one bit line pair. For example, the bit cells BC on the 1stcolumn on the left are connected to one bit line pair, which includes one bit line BL1and one complement bit line BLB1, and the bit cells BC on the nthcolumn on the right side are connected to another bit line pair, which includes another bit line BLn and another complement bit line BLBn. In some embodiments, n is a positive integer. For example, n can be about 8, 16, 32 or other suitable numbers. For brevity, only two columns of the memory array120are illustrated inFIG.1for demonstrational purpose. However, the embodiments of the disclosure are not limited to a specific amount of columns in the memory array120.

As illustratively shown inFIG.1, in some embodiments, the bit cells BC on the same row are connected to the same word line. For example, the bit cells BC on the 1strow (started from the bottom side of the memory array120) are connected to the word line WL1; the bit cells BC on the kthrow are connected to the word line WLk; the bit cells BC on the k+1throw are connected to the word line WLk+1; the bit cells BC on the k+2throw are connected to the word line WLk+2; and, the bit cells BC on the 2k row are connected to the word line WL2k. In some embodiments, k is a positive integer. For example, in the memory array120with 2048 rows of bit cells BC, k is equal to 1024 and there are 2048 word lines distributed from the bottom side to the top side of the memory array120.

As illustratively shown inFIG.1, in some embodiments, the memory device100includes a local input/output circuit140, a main control circuit160and a word line decoder180. The main control circuit160is coupled with the local input/output (LIO) circuit140and the word line decoder180.

In some embodiments, the main control circuit160includes a control signal generator162, and the control signal generator162is configured to generate some control signals to control/activate/deactivate functions in the local input/output circuit140and the word line decoder180. As illustratively shown inFIG.1, in some embodiments, the control signal generator162is configured to generate a control signal BLEQB for precharging and equalization to the local input/output circuit140, a selection signal YSEL for column selection to the local input/output circuit140, and still another control signal DEC to the word line decoder180. In some other embodiments, the control signal generator162is able to generate other control signals for controlling other functions. The embodiments of the disclosure are not limited to these control signals.

In some embodiments, the local input/output circuit140includes modulation circuits142a˜142b, a selection circuit144and a read/write circuit146. During a write operation, the read/write circuit146is configured to generate a write signal and a complement write signal onto a bit line pair, which includes a bit line BL and a complement bit line BLB in the local input/output circuit140, and the selection circuit144is configured to couple the bit line pair (i.e., the bit line BL and the complement bit line BLB) to one of the bit line pairs in the memory array120accordingly to a selection signal YSEL, so as to write data into the bit cell BC on a target column.

For example, when the target column is the 1stcolumn, the selection circuit144is configured to couple the bit line BL and the complement bit line BLB in the local input/output circuit140with the bit line BL1and the complement bit line BLB1in the memory array120; when the target column is the nthcolumn, the selection circuit144is configured to couple the bit line BL and the complement bit line BLB in the local input/output circuit140with the bit line BLn and the complement bit line BLBn in the memory array120.

In some embodiments, during a read operation for reading data from a target column, the selection circuit144is configured to couple the bit line pair (i.e., the bit line BL and the complement bit line BLB in the local input/output circuit140) to one of the bit line pairs corresponding to the target column in the memory array120accordingly to the selection signal YSEL, the read/write circuit146is configured to sense voltage levels from the bit line pair, and, so as to read data from the bit cell BC on the target column.

As illustratively shown inFIG.1, the modulation circuits142aand142bare coupled with the bit line pairs on the columns of the memory array120. For example, one modulation circuit142ais coupled with the bit line BL1and the complement bit line BLB1on the 1stcolumn, and another modulation circuit142bis coupled with the bit line BLn and the complement bit line BLBn on the nthcolumn. For brevity, only two modulation circuits142aand142bon two columns of the memory array120are illustrated inFIG.1for demonstrational purpose. However, the embodiments of the disclosure are not limited to a specific amount of modulation circuits.

In some embodiments, the modulation circuit142ais configured to modulate voltage levels on the bit line BL1and the complement bit line BLB1when the memory device100is not accessing (e.g., writing into or reading from) the bit cells BC. For example, during the write operation or the read operation, one of the bit line BL1and the complement bit line BLB1will be charged to a higher level, such as a high reference voltage level VDD, and the other of the bit line BL1and the complement bit line BLB1will be discharged to a lower level, such as a low reference voltage level VSS or a ground level.

Outside the write operation or the read operation, in some embodiments, the modulation circuit142ais triggered by the control signal BLEQB and configured to couple the bit line BL1and the complement bit line BLB1together with each other, so as to equalize the voltage levels on the bit line BL1and the complement bit line BLB1. In some embodiments, outside the write operation or the read operation, the modulation circuit142ais configured to precharge the voltage levels on the bit line BL1and the complement bit line BLB1to a fixed level, such as the high reference voltage level VDD. In this case, the bit line BL1and the complement bit line BLB1are configured at the fixed level instead of being in floating levels, and it can secure the data stored in the bit cell BC and avoid these data to be affected by unexpected floating levels on the bit line BL1and the complement bit line BLB1.

On the other hand, during the write operation or the read operation, the modulation circuit142ais deactivated by the control signal BLEQB, such that the voltage levels of the bit line BL1and the complement bit line BLB1are released and not controlled by the modulation circuit142a. In this case, the bit line BL1and the complement bit line BLB1can be used in the write operation or the read operation by the read/write circuit146.

Similarly, outside the write operation or the read operation, the modulation circuit142bis configured to equalize the voltage levels on the bit line BLn and the complement bit line BLBn, and/or configured to precharge the voltage levels on the bit line BLn and the complement bit line BLBn to a fixed level.

As illustratively shown inFIG.1, the word line decoder180is coupled with the word lines WL1˜WL2k. In some embodiments, the word line decoder180is configured to generate word line signals to select a target row to be written or read in the write operation or the read operation. In response to that the 1strow is selected, the word line decoder180is configured to generate the word line signal to the word line WL1to activate the bit cells BC connected with the word line WL1. In this case, the memory device100is able to perform the write operation or the read operation onto the bit cells BC on the 1strow. In response to that the 2ndrow is selected, the word line decoder180is configured to generate the word line signal to the word line WL2to activate the bit cells BC connected with the word line WL2. In response to that the row on the top side is selected, the word line decoder180is configured to generate the word line signal to the word line WL2kto activate the bit cells BC connected with the word line WL2k. For the memory device100with a large data capacity, the memory device100may have 512 rows, 1024 rows or even more rows. In this case, a depth distance DPf between the first word line WL1and the last word line WL2kof the word lines WL1˜WL2kis relatively longer.

In some embodiments, the word line decoder180is controlled by the control signal DEC generated by the control signal generator162. In some embodiments, the word line decoder180includes several decoder units182, and each of the decoder units182is configured to provide one word line signal to one of the word lines WL1˜WL2k. The control signal DEC is used to control functions of addressing and gating on the decoder units182in the word line decoder180. In some embodiments, the memory array120may include a lot of rows of the bit cells BC. When the control signal DEC is transmitted from the side of the control signal generator162to the decoder units182the word line decoder180, the control signal DEC arrives different decoder units182at different time points. For example, for the decoder unit182at the bottom side closer to the control signal generator162, the control signal DEC arrives earlier. On the other hand, for the decoder unit182at the top side far from the control signal generator162, the control signal DEC arrives later. In other words, the control signal DEC will arrive different decoder units182at different timing points. Because aforesaid different arrival timings of the control signal DEC, the word line signals generated by the decoder units182in the word line decoder180to the word lines WL1˜WL2khave pulses with different timings.

When the depth distance DPf is longer, a time difference between pulses on the word line signals on the word line WL1and the word line WL2kis going to be larger. If the control signal generator162generates the control signal BLEQB without considering the time difference on the word line signals on the word line WL1and the word line WL2k, the control signal BLEQB may not be able to activate the modulation circuits142aand142bat the correct timing, and it may cause some issues, such as degrading of read/write margin, increasing a crowbar current, degrading of stability of bit cells. Further details will be discussed in following paragraphs.

In some embodiments, the control signal generator162is configured to generate the control signal BLEQB in reference with the depth distance DPf between the first word line WL1and the last word line WL2kof the word lines WL1˜WL2k, so as to avoid aforesaid issues.

Reference is further made toFIG.2andFIG.3.FIG.2is a schematic diagram illustrating internal structures of the modulation circuits and the control signal generator inFIG.1in accordance with various embodiments of the present disclosure.FIG.3is a signal waveform illustrating related signals generated in the memory device100inFIG.1andFIG.2in accordance with various embodiments of the present disclosure. With respect to the embodiments ofFIG.1, like elements inFIG.2andFIG.3are designated with the same reference numbers for ease of understanding. It is noticed that, for brevity,FIG.2illustrates structures related to the 1stcolumn of the memory array120. Structures related to other columns are similar and can be understood through the embodiments shown inFIG.2. The control signal generator162-1illustratively shown inFIG.2is one embodiment of the control signal generator162shown inFIG.1.

As illustratively shown inFIG.2, the modulation circuit142aincludes transistors T1, T2and T3. The gates of the transistors T1, T2and T3are controlled by the control signal BLEQB. Two terminals of the transistor T1is connected with the bit line BL1and the complement bit line BLB1.

When the control signal BLEQB is at a low voltage level (e.g., 0V, GND level, or VSS level), the transistor T1is switched on to couple the bit line BL1and the complement bit line BLB1(of the bit line pair on the 1stcolumn) together with each other, so as to equalize the voltage levels on the bit line BL1and the complement bit line BLB1. When the control signal BLEQB is at the low voltage level (e.g., 0V), the transistor T2is switched on to connect the bit line BL1to the high reference voltage level VDD, so as to fix the voltage level on bit line BL1at the high reference voltage level VDD. When the control signal BLEQB is at the low voltage level (e.g., 0V), the transistor T3is switched on to connect the complement bit line BLB1to the high reference voltage level VDD, so as to fix the voltage level on complement bit line BLB1at the high reference voltage level VDD. In this case, the bit line BL1and the complement bit line BLB1are configured at the fixed level instead of being in floating levels, and it can secure the data stored in the bit cell BC and avoid these data to be affected by unexpected floating levels on the bit line BL1and the complement bit line BLB1.

In some embodiments, outside the write operation or the read operation, the modulation circuit142ais also configured to precharge the voltage levels on the bit line BL1and the complement bit line BLB1to a fixed level, such as the high reference voltage level VDD. In this case, the bit line BL1and the complement bit line BLB1are configured at the fixed level instead of being in floating levels, and it can secure the data stored in the bit cell BC and avoid these data to be affected by unexpected floating levels on the bit line BL1and the complement bit line BLB1.

When the control signal BLEQB is at a high voltage level (e.g., 3V, 5V or VDD level), the transistors T1, T2and T3in the modulation circuit142aare all switched off, such that the modulation circuit142ais deactivated, and the voltage levels on the bit line BL1and the complement bit line BLB1are released from the modulation circuit142aand controlled by the read/write circuit146shown inFIG.1.

As illustratively shown inFIG.2andFIG.3, during a time duration DWL1, the word line signal to the word line WL1is switched to the high voltage level, the bit cell BC connected with the word line WL1shall be ready to read/write, such that a rising edge of the control signal BLEQB is required to arrive at the same time as (or before) a rising edge of the word line signal on the word line WL1. If the rising edge of the control signal BLEQB arrives later than the rising edge of the word line signal on the word line WL1, the modulation circuit142amay not release the bit line BL1and the complement bit line BLB1in time, such that a read/write margin to the bit cell BC will be degraded.

As illustratively shown inFIG.1,FIG.2andFIG.3, during a time duration DWL2k, the word line signal to the word line WL2kis switched to the high voltage level, the bit cell BC connected with the word line WL2kshall be ready to read/write, such that a falling edge of the control signal BLEQB is required to arrive at the same time as (or after) a falling edge of the word line signal on the word line WL2k. If the falling edge of the control signal BLEQB arrives before the falling edge of the word line signal on the word line WL2k, the modulation circuit142amay boost both of the voltage levels on the bit line BL1and the complement bit line BLB1to the high voltage levels while the word line WL2kstill activating an access to the bit cell BC, such that the data bit stored in the bit cell BC connected with the word line WL2kmay be damaged due to the wrong configuration of the voltage levels on the bit line BL1and the complement bit line BLB1(e.g., the voltage levels on the bit line BL1and the complement bit line BLB1are both charged to high levels by the modulation circuit142b). Similarly, if the falling edge of the control signal BLEQB arrives before the falling edge of the word line signal on the word line WL2k, other modulation circuits (e.g., the modulation circuit142b) may boost both of the voltage levels on their corresponding bit lines (e.g., the bit line BLn) and their corresponding complement bit lines (e.g., the complement bit line BLBn) to the high voltage levels while the word line WL2kstill activating the access to the bit cells BC on the corresponding row.

In addition, as shown inFIG.1, the bit lines BL1˜BLn and the complement bit lines BLB1˜BLBn are arranged across the word lines WL1˜WL2k, and coupling effect happen to signals between these signal lines. At the falling edge of the control signal BLEQB, the control signal BLEQB activates the modulation circuits142a˜142b, such that the voltage levels on the bit lines BL1˜BLn and the complement bit line BLB1˜BLBn are raised to the high voltage levels by their corresponding modulation circuits142a˜142b. Due to the coupling effect, the word line signals on the word lines WL1˜WL2kare boosted to a higher level according to the raised voltage levels on the bit lines BL1˜BLn and the complement bit line BLB1˜BLBn. In particular, if the falling edge of the control signal BLEQB arrives before the falling edge of the word line signal on the word line WL2k, the word line signal on the word line WL2kwill be raised further higher (e.g., over VDD level), and it may cause instability of the bit cells BC connected with the word line WL2k.

In other words, the time duration D1of the control signal BLEQB switching to the high voltage level is required to enclose the rising edge of the word line signal on the word line WL1and the falling edge of the word line signal on the word line WL2k. In some embodiments, the control signal generator162-1is able to generate the control signal BLEQB at the correct timing with reference to the depth distance DPf.

As shown inFIG.2, the control signal generator162-1in some embodiments includes a tracking wiring TR, two inverters INV1, INV2and two logic gates NAND1, NAND2. In some embodiments, the control signal generator162-1receives an input control signal PRE and an input clock signal CKP.

The tracking wiring TR has a tracking length positively correlated with the depth distance DPf of the word lines WL1˜WL2k. As shown inFIG.2, in some embodiments, the tracking wiring TR includes a first tracking segment S1and a second tracking segment S2. The first tracking segment S1extends from a bottom side edge of the word lines WL1˜WL2ktoward a half position (e.g., at a horizontal level between the word line WLk and the word line WLk+1) of the word lines WL1˜WL2k. The second tracking segment S2extends from the half position of the word lines WL1˜WL2ktoward the bottom side edge of the word lines WL1˜WL2k. In this case, the sum of lengths of the first tracking segment S1and the second tracking segment S2is similar or approximately equal to the depth distance DPf.

The logic gate NAND2and the inverter INV2are configured to generate the control signal DEC to the word line decoder180according to the input control signal PRE and the input clock signal CKP. In this case, the control signal DEC is generated with two gate delays (induced by the logic gate NAND2and the inverter INV2) relative to the input clock signal CKP.

The inverter INV1is configured to invert the input clock signal CKP into an inverted clock signal CKPB. The logic gate NAND1includes a first input terminal, a second input terminal and an output terminal. The first input terminal of the logic gate NAND1is configured to receive the inverted clock signal CKPB. The second input terminal of the logic gate NAND1is configured to receive an invert-delayed clock signal CKPBd (which is the inverted clock signal CKPB after being delayed through the tracking wiring TR).

The output terminal of the logic gate NAND1is configured to produce the control signal BLEQB. The logic gate NAND1is configured to perform a NAND Boolean function between two input terminals and generate the control signal BLEQB. A relationship between the inputs and the output of the logic gate NAND1is shown in Table 1.

TABLE 1first input terminalsecond input terminaloutput terminal(CKPB)(CKPBd)(BLEQB)HHLLHHHLHLLH

As shown inFIG.3and Table 1, the rising edge of the control signal BLEQB is triggered by the falling edge of the inverted clock signal CKPB. In the embodiments shown inFIG.2, the rising edge of the control signal BLEQB arrives with two gate delays (induced by the inverter INV1and the logic gate NAND1) relative to the input clock signal CKP.

It is noticed that the control signal DEC is generated with two gate delays relative to the input clock signal CKP, and the control signal DEC is transmitted into the word line decoder180(for triggering the decoder units182shown inFIG.1) to generate the word line signals on the word lines WL1˜WL2k. In this case, the rising edge of the word line signal on the word line WL1arrives with (or later than) two gate delays relative to the input clock signal CKP. As mentioned above, the rising edge of the control signal BLEQB arrives with two gate delays relative to the input clock signal CKP. Therefore, the rising edge of the control signal BLEQB is able to enclose the word line signal on the word line WL1.

In some embodiments, because the invert-delayed clock signal CKPBd is delayed by the tracking wiring TR corresponding to the to the depth distance DPf, a timing of the invert-delayed clock signal CKPBd will be similar to a timing that the control signal DEC arrives the decoder unit connected to the word line WL2kon the top side. As shown inFIG.3, the timing of the rising edge of the invert-delayed clock signal CKPBd is similar to the word line signal on the word line WL2k. As shown inFIG.3and Table 1, the falling edge of the control signal BLEQB is triggered by the rising edge of the invert-delayed clock signal CKPBd. As embodiments shown inFIG.3, the falling edge of the control signal BLEQB is decided by the rising edge of the invert-delayed clock signal CKPBd, and the falling edge of the control signal BLEQB arrives at a similar timing when the falling edge of the word line signal on the word line WL2karrives.

In other words, the time duration D1of the control signal BLEQB switching to the high voltage level is prolonged in accordance with the invert-delayed clock signal CKPBd which is delayed by the tracking wiring TR. With the help of the tracking wiring TR to track the delay about the depth distance DPf, the falling edge of the control signal BLEQB is able to enclose the falling edge of the word line signal on the word line WL2k. Since the falling edge of the control signal BLEQB is able to enclose the falling edge of the word line signal on the word line WL2k, it can avoid the modulation circuit142ato be activated too early before the access paths to the bit cells BC are turned off by the word line signals on the word lines WL1˜WL2k. Therefore, it can avoid data bits stored in the bit cells from being damaged, because the modulation circuits142ais activated (to charge the corresponding bit line BL1and the complement bit line BLB1) after the word lines WL1˜WL2kis pulled low to turn off the pass gates of the bit cells, such that it can enhance the stability of data bits stored in the bit cells.

It is noticed that the control signal generator162-1illustratively shown inFIG.2is one exemplary embodiment to achieve the control signal generator162shown inFIG.1. However, the disclosure is not limited thereto. Reference is further made toFIG.4, which illustrates internal structures of the modulation circuit and the control signal generator inFIG.1in accordance with various embodiments of the present disclosure. The control signal generator162-2illustratively shown inFIG.4is another embodiment of the control signal generator162shown inFIG.1. Compared to the control signal generator162-1illustratively shown inFIG.2, the control signal generator162-2inFIG.4utilize a different combination of logic gates and inverters to generate the control signal BLEQB. As shown inFIG.2, the control signal BLEQB is generated by the logic gate NAND1according to the inverted clock signal CKPB and the invert-delayed clock signal CKPBd. On the other hand, as shown inFIG.4, the control signal BLEQB is generated by a logic gate NOR1and an inverter INV3according to an input clock signal CKP and a delayed clock signal CKPd.

As shown inFIG.4, the control signal generator162-2in some embodiments includes a tracking wiring TR, two logic gates NAND2, NOR1and two inverters INV2and INV3. In some embodiments, the control signal generator162-2receives an input control signal PRE and the input clock signal CKP.

The tracking wiring TR has a tracking length positively correlated with the depth distance DPf of the word lines WL1˜WL2k.

The logic gate NAND2and the inverter INV2are configured to generate the control signal DEC to the word line decoder180according to the input control signal PRE and the input clock signal CKP. In this case, the control signal DEC is generated with two gate delays (induced by the logic gate NAND2and the inverter INV2) relative to the input clock signal CKP.

The logic gate NOR1includes a first input terminal, a second input terminal and an output terminal. The first input terminal of the logic gate NOR1is configured to receive the input clock signal CKP. The second input terminal of the logic gate NOR1is configured to receive a delayed clock signal CKPd (which is the input clock signal CKP after being delayed through the tracking wiring TR).

The output terminal of the logic gate NOR1is connected to the inverter INV3. The inverter INV3is configured to invert an output signal from the logic gate NOR1and accordingly produce the control signal BLEQB. The logic gate NOR1is configured to perform an NOR Boolean function between two input terminals and generate the output signal, which is further inverted by the inverter INV3into the control signal BLEQB. A relationship between the inputs and the outputs of the logic gate NOR1and the inverter INV3is shown in Table 2.

TABLE 2first inputsecond inputoutputoutput terminalterminalterminalterminalof INV3(CKP)(CKPd)of NOR1(BLEQB)LLHLLHLHHLLHHHLH

Based on the Boolean logic:

BLEQB generated by the output of the inverter INV3inFIG.4=NOT[the output of the logic gate NOR1inFIG.4]=NOT[NOT[CKP∪CKPd]]=CKP∪CKPd=NOT[CKPB∩CKPB d]=the output of the logic gate NAND1inFIG.2

In other words, the logic gate NOR1and the inverter INV3inFIG.4outputs the control signal BLEQB in a same logic as the logic gate NAND1discussed in embodiments ofFIG.2.

In a similar way, a rising edge of the control signal BLEQB generated by the logic gate NOR1and the inverter INV3inFIG.4is triggered by a rising edge of the input clock signal CKP. With the help of the tracking wiring TR to track the delay about the depth distance DPf, a falling edge of the control signal BLEQB generated by the logic gate NOR1and the inverter INV3inFIG.4is triggered by a falling edge of the delayed clock signal CKPd, which is equal to the input clock signal CKP after being delayed by the tracking wiring TR. In this case, the control signal BLEQB is able to enclose the rising edge of the word line signal on the word line WL1and the falling edge of the word line signal on the word line WL2k.

Reference is further made toFIG.5, which illustrates internal structures of the modulation circuit and the control signal generator inFIG.1in accordance with various embodiments of the present disclosure. The control signal generator162-3illustratively shown inFIG.5is another embodiment of the control signal generator162shown inFIG.1. Compared to the control signal generator162-1illustratively shown inFIG.2and the control signal generator162-2illustratively shown inFIG.4, the control signal generator162-3inFIG.5utilize a different combination of logic gates and inverters to generate the control signal BLEQB. As shown inFIG.2, the control signal BLEQB is generated by the logic gate NAND1according to the inverted clock signal CKPB and the invert-delayed clock signal CKPBd. As shown inFIG.5, the control signal BLEQB is generated by a logic gate NOR1and an inverter INV3according to an input clock signal CKP and a delayed clock signal CKPd. Compared to the control signal generator162-2shown inFIG.4, the control signal generator162-3inFIG.5includes extra inverters for converting clock signals.

As shown inFIG.5, the control signal generator162-3in some embodiments includes a tracking wiring TR, logic gates NAND2and NOR1and inverters INV1˜INV4. In some embodiments, the control signal generator162-3receives an input control signal PRE and an inverted input clock signal CKPB. The tracking wiring TR has a tracking length positively correlated with the depth distance DPf of the word lines WL1˜WL2k.

The control signal generator162-3shown inFIG.5is similar to the control signal generator162-2shown inFIG.4, except that the control signal generator162-3shown inFIG.5further includes two extra inverters INV1and INV4. The inverter INV1is configured to invert the inverted input clock signal CKPB into the input clock signal CKP, which is transmitted to the logic gate NOR1. The inverter INV3is configured to invert an output of the logic gate NOR1to generate the control signal BLEQB. The inverter INV4is configured to invert the inverted input clock signal CKPB into the input clock signal CKP, which is transmitted to the logic gates NAND2.

As shown inFIG.5, the logic gate NOR1receives the input clock signal CKP and the delayed input clock signal CKPd, and the output of the logic gate NOR1is further inverted by the inverter INV3into the control signal BLEQB. Based on the Boolean logic, the control signal BLEQB generated by the inverter INV3in embodiments shown inFIG.5is equal to the output of the inverter INV3in embodiments shown inFIG.4, and also equal to the output of the logic gate NAND1in embodiments shown inFIG.2.

In a similar way, a rising edge of the control signal BLEQB generated by the inverter INV3and the logic gate NOR1inFIG.5is triggered by a rising edge of the input clock signal CKP. With the help of the tracking wiring TR to track the delay about the depth distance DPf, a falling edge of the control signal BLEQB generated by the inverter INV3and the logic gate NOR1inFIG.5is triggered by a falling edge of the delayed clock signal CKPd, which is equal to the input clock signal CKP after being delayed by the tracking wiring TR. In this case, the control signal BLEQB generated by the inverter INV3and the logic gate NOR1inFIG.5is able to enclose the rising edge of the word line signal on the word line WL1and the falling edge of the word line signal on the word line WL2k.

Reference is further made toFIG.6.FIG.6is a schematic diagram illustrating another memory device200in accordance with various embodiments of the present disclosure. Compared to the memory device100shown inFIG.1including the bit cells BC arranged in one array without being divided into subarrays, the memory device200inFIG.6includes bit cells BC arranged in different subarrays and flying bit lines for transmitting signals across one of the subarrays. In embodiments illustratively shown inFIG.6, the memory device200includes a memory array220including several bit cells BC arranged on multiple rows and columns. As shown in embodiments ofFIG.6, the memory array220includes two a subarray222, another subarray224and a strap cell226located between these two subarrays222and224.

As illustratively shown inFIG.6, the bit cells BC located adjacent to the bottom side of the memory array220are grouped into the subarray222, and the bit cells BC located adjacent to the top side of the memory array220are grouped into the subarray224. As illustratively shown inFIG.6, in some embodiments, the bit cells BC on the same row are connected to the same word line. For example, the bit cells BC on the 1strow (started from the bottom side of the memory array220) are connected to the word line WL1; the bit cells BC on the 2ndrow are connected to the word line WL2; and the bit cells BC on the kthrow are connected to the word line WLk. The bit cells BC connected with the word lines WL1˜WLk are grouped into the subarray222.

On the other hand, the bit cells BC on the k+1throw are connected to the word line WLk+1; the bit cells BC on the k+2throw are connected to the word line WLk+2; and, the bit cells BC on the 2k row are connected to the word line WL2k. The bit cells BC connected with the word lines WLk+1˜WL2kare grouped into the subarray224.

In some embodiments, k is a positive integer. For example, in the memory array120with 2048 rows of bit cells BC, k is equal to 1024 and there are 2048 word lines distributed from the bottom side to the top side of the memory array120. In this example, the bit cells BC on the 1strow to the 1024throw are in the subarray222and the bit cells BC on the 1025throw to the 2048throw are in the subarray224.

The bit cells BC in the subarray222on the same column are connected to one bit line pair. For example, the bit cells BC in the subarray222on the 1stcolumn on the left are connected to one bit line pair, which includes one bit line BL1dand one complement bit line BLB1d, and the bit cells BC in the subarray222on the nthcolumn on the right side are connected to another bit line pair, which includes another bit line BLnd and another complement bit line BLBnd. As shown inFIG.6, the bit line BL1dand one complement bit line BLB1dextend along the 1stcolumn of the subarray222, from the bottom side edge of the memory array220, and terminating between the subarray222and the subarray224. In some embodiments, n is a positive integer. For example, n can be about 8, 16, 32 or other suitable numbers. For brevity, only two columns of the memory array220are illustrated inFIG.6for demonstrational purpose. However, the embodiments of the disclosure are not limited to a specific amount of columns in the memory array220.

The bit cells BC in the subarray224on the same column are connected to one bit line pair. For example, the bit cells BC in the subarray224on the 1stcolumn on the left are connected to another bit line pair, which includes one bit line BL1uand one complement bit line BLB1u, and the bit cells BC in the subarray222on the nthcolumn on the right side are connected to another bit line pair, which includes another bit line BLnu and another complement bit line BLBnu. As shown inFIG.6, the bit line BL1uand one complement bit line BLB1uextend, along the 1stcolumn of the subarray224, from the strap cell226of the memory array220to the top side edge of the memory array220. In some embodiments, the strap cell226is located at a gap space between the subarrays222and224. In some embodiments, the flying bit line BL1fand the complement flying bit line BLB1fare connected to the bit line BL1uand one complement bit line BLB1uat the strap cell226.

As illustratively shown inFIG.6, in some embodiments, the memory device200includes a local input/output circuit240, a main control circuit260and a word line decoder280. The main control circuit260is coupled with the local input/output (LIO) circuit240and the word line decoder280. Some functions and behaviors of the local input/output circuit240, the main control circuit260and the word line decoder280of embodiments inFIG.6are similar to the local input/output circuit140, the main control circuit160and the word line decoder180of embodiments inFIG.1andFIG.2, and can be referred to aforesaid embodiments discussed inFIG.1andFIG.2.

In some embodiments, the main control circuit260includes a control signal generator262, and the control signal generator262is configured to generate some control signals to control/activate/deactivate functions in the local input/output circuit240and the word line decoder280. As illustratively shown inFIG.6, in some embodiments, the control signal generator262is configured to generate a control signal BLEQBd (corresponding to the subarray222) to the local input/output circuit240, another control signal BLEQBu (corresponding to the subarray224) to the local input/output circuit240, the selection signal YSEL to the local input/output circuit240, and a control signal DEC to the word line decoder280. In some other embodiments, the control signal generator262is able to generate other control signals for controlling other functions. The embodiments of the disclosure are not limited to these control signals.

In some embodiments, the local input/output circuit240includes modulation circuits242a˜242b(corresponding to the subarray222), modulation circuits243a˜243b(corresponding to the subarray224), a selection circuit244and a read/write circuit246.

During a write operation to the subarray222, the read/write circuit246is configured to generate a write signal and a complement write signal onto a bit line pair, which includes a bit line BLd and a complement bit line BLBd in the local input/output circuit240, and the selection circuit244is configured to couple the bit line pair (i.e., the bit line BLd and the complement bit line BLBd) to one of the bit line pairs in the subarray222of the memory array220accordingly to a selection signal YSEL, so as to write data into the bit cell BC on a target column in the subarray222.

For example, when a target column of the write operation is the 1stcolumn in the subarray222, the selection circuit244is configured to couple the bit line BLd and the complement bit line BLBd in the local input/output circuit240to the bit line BL1dand the complement bit line BLB1don the 1stcolumn in the subarray222of the memory array220, so as to write data into the bit cell BC on the 1stcolumn in the subarray222.

During a write operation to the subarray224, the read/write circuit246is configured to generate a write signal and a complement write signal onto a bit line pair, which includes a bit line BLu and a complement bit line BLBu in the local input/output circuit240. As shown inFIG.6, the memory array220further includes some flying bit line pairs, which are configured to connect the bit line pairs in the subarray224on the top side with the selection circuit244and the read/write circuit246located under the bottom side of the memory array220.

For example, when a target column of the write operation is the 1stcolumn in the subarray224, the selection circuit244is configured to couple the bit line BLu and the complement bit line BLBu in the local input/output circuit240to the bit line BL1uand a complement bit line BLB1uon the 1stcolumn in the subarray224of the memory array220, via the flying bit line BL1fand the complement flying bit line BLB1f, so as to write data into the bit cell BC on the 1stcolumn in the subarray224.

There are a lot of the rows in the memory array, such that a resistance-capacitance loading on the bit line pair connected with the bit cells on the whole column is relatively large. By dividing the memory array220into two subarrays222and224, the resistance-capacitance loading on one bit line pair (e.g., BL1dand BLB1d; BL1uand BLB1u) can be reduced. As shown in embodiments ofFIG.6, each bit line pair in the memory arrays are connected to about a half of bit cells on the same column, such that the resistance-capacitance loading on each bit line pair can be reduced by about 50% (compared with connecting to all bit cells on the same column).

It is noticed that there are three bit line pairs corresponding to the 1stcolumn of the memory array220. These three bit line pairs include a first bit line pair (e.g., the bit line BL1dand the complement bit line BLB1d) connected the bit cells BC in the subarray222to the selection circuit244and the read/write circuit246, a second bit line pair (e.g., the bit line BL1uand the complement bit line BLB1u) connected the bit cells BC in the subarray224, and a third bit line pair (e.g., the flying bit line BL1fand the complement bit line BLB1f) connected from the second bit line pair to the selection circuit244and the read/write circuit246. Similarly, there are another three bit line pairs corresponding to the nthcolumn of the memory array220.

As illustratively shown inFIG.6, the modulation circuit242ais coupled with the bit line BL1dand the complement bit line BLB1d(i.e., the first bit line pair) connected the bit cells BC on the 1stcolumn in the subarray222. The modulation circuit242ais configured to modulate voltage levels on the bit line BL1dand the complement bit line BLB1din the subarray222according to the control signal BLEQBd.

The modulation circuit243ais coupled to the bit line BL1uand the complement bit line BLB1uin the subarray224(i.e., the second bit line pair) through the flying bit line BL1fand the complement bit line BLB1f(i.e., the third bit line pair). The modulation circuit243ais configured to modulate voltage levels on the bit line BL1uand the complement bit line BLB1uin the subarray224according to the control signal BLEQBu.

Outside a write operation or a read operation, in some embodiments, the modulation circuit242ais triggered by the control signal BLEQBd and configured to couple the bit line BL1dand the complement bit line BLB1dtogether with each other, so as to equalize the voltage levels on the bit line BL1dand the complement bit line BLB1d. In some embodiments, outside the write operation or the read operation, the modulation circuit242ais also configured to precharge the voltage levels on the bit line BL1dand the complement bit line BLB1dto a fixed level, such as the high reference voltage level VDD.

Outside a write operation or a read operation, in some embodiments, the modulation circuit243ais triggered by the control signal BLEQBu and configured to couple the bit line BL1uand the complement bit line BLB1utogether with each other, so as to equalize the voltage levels on the bit line BL1uand the complement bit line BLB1u. In some embodiments, outside the write operation or the read operation, the modulation circuit243ais also configured to precharge the voltage levels on the bit line BL1uand the complement bit line BLB1uto a fixed level, such as the high reference voltage level VDD. Functions and behaviors of the modulation circuits242aand243acan be referred to the modulation circuit142ain the embodiments discussed inFIG.2.

Similarly, the modulation circuit242bis configured to modulate voltage levels on the bit line BLnd and the complement bit line BLBnd in the subarray222according to the control signal BLEQBd, and the modulation circuit243bis configured to modulate voltage levels on the bit line BLnu and the complement bit line BLBnu in the subarray224according to the control signal BLEQBu.

In some embodiments, the word line decoder280is controlled by the control signal DEC generated by the control signal generator262. In some embodiments, the word line decoder280includes several decoder units282, and each of the decoder units282is configured to provide one word line signal to one of the word lines WL1˜WL2k. The control signal DEC is used to control functions of addressing and gating on the decoder units282in the word line decoder280. When the control signal DEC is transmitted from the side of the control signal generator262to the decoder units282in the word line decoder280, the control signal DEC arrives different decoder units282at different time points. Because aforesaid different arrival timings of the control signal DEC, the word line signals generated by the decoder units282in the word line decoder280to the word lines WL1˜WL2khave pulses with different timings.

In some embodiments, the control signal generator262is configured to generate the control signal BLEQBd in reference with a full depth distance DPf between the word line WL1and the word line WL2k, and also generate the control signal BLEQBu in reference with a half depth distance DPh between the word line WL1and the word line WLk.

Reference is further made toFIG.7andFIG.8.FIG.7is a schematic diagram illustrating internal structures of the modulation circuits and the control signal generator inFIG.6in accordance with various embodiments of the present disclosure.FIG.8is a signal waveform illustrating related signals generated in the memory device200inFIG.6andFIG.7in accordance with various embodiments of the present disclosure. With respect to the embodiments ofFIG.6, like elements inFIG.7and FIG.8are designated with the same reference numbers for ease of understanding. It is noticed that, for brevity,FIG.7illustrates structures related to the 1stcolumn of the subarray222and the subarray224. Structures related to other columns are similar and can be understood through the embodiments shown inFIG.7. The control signal generator262-1illustratively shown inFIG.7is one embodiment of the control signal generator262shown inFIG.6.

As illustratively shown inFIG.7, the modulation circuit242aincludes three transistors. The gates of the transistors in the modulation circuit242aare controlled by the control signal BLEQBd. The transistors in the modulation circuit242aare coupled to the bit line BL1dand the complement bit line BLB1din the subarray222. When the control signal BLEQBd is at a low voltage level (e.g., 0V, GND level, or VSS level), the modulation circuit242ais configured to couple the bit line BL1dand the complement bit line BLB1d(of the bit line pair on the 1stcolumn in the subarray222) together with each other, so as to equalize the voltage levels on the bit line BL1dand the complement bit line BLB1d. When the control signal BLEQBd is at the low voltage level (e.g., 0V), the modulation circuit242ais also configured to connect the bit line BL1dand the complement bit line BLB1dto the high reference voltage level VDD, so as to fix the voltage level on bit line BL1dand the complement bit line BLB1dat the high reference voltage level VDD. Behaviors and details about the modulation circuit242ais similar to the modulation circuit142adiscussed in aforesaid embodiments along withFIG.2.

In some embodiments, outside the write operation or the read operation, the modulation circuit242ais configured to precharge the voltage levels on the bit line BL1dand the complement bit line BLB1dto a fixed level, such as the high reference voltage level VDD. In this case, the bit line BL1dand the complement bit line BLB1dare configured at the fixed level instead of being in floating levels, and it can secure the data stored in the bit cell BC and avoid these data to be affected by unexpected floating levels on the bit line BL1dand the complement bit line BLB1d.

Similarly, the modulation circuit243aincludes another three transistors. The gates of the transistors in the modulation circuit243aare controlled by the control signal BLEQBu. When the control signal BLEQBu is at a low voltage level (e.g., 0V, GND level, or VSS level), the modulation circuit243ais configured to couple the bit line BL1u(via the flying bit line BL1f) and the complement bit line BLB1u(via the complement flying bit line BLB1f) together with each other, so as to equalize the voltage levels on the bit line BL1uand the complement bit line BLB1u. When the control signal BLEQBu is at the low voltage level (e.g., 0V), the modulation circuit243ais also configured to connect the bit line BL1u(via the flying bit line BL1f) and the complement bit line BLB1u(via the complement flying bit line BLB1f) to the high reference voltage level VDD, so as to fix the voltage level on bit line BL1uand the complement bit line BLB1uat the high reference voltage level VDD.

Similarly, outside the write operation or the read operation, the modulation circuit243ais configured to precharge the voltage levels on the bit line BL1uand the complement bit line BLB1uto a fixed level, such as the high reference voltage level VDD. In this case, the modulation circuit243ais able to avoid data stored in the corresponding bit cells BC to be affected by unexpected floating levels on the bit line BL1uand the complement bit line BLB1u.

When the control signal BLEQBd is at a high voltage level (e.g., VDD level), the modulation circuit242ais deactivated, and the voltage levels on the bit line BL1dand the complement bit line BLB1dare released from the modulation circuit242aand controlled by the read/write circuit246shown inFIG.6.

As illustratively shown inFIG.7andFIG.8, during a time duration DWL1, the word line signal to the word line WL1is switched to the high voltage level, the bit cell BC connected with the word line WL1shall be ready to read/write, such that a rising edge of the control signal BLEQBd is required to arrive at the same time as (or before) a rising edge of the word line signal on the word line WL1. If the rising edge of the control signal BLEQBd arrives later than the rising edge of the word line signal on the word line WL1, the modulation circuit242amay not release the bit line BL1dand the complement bit line BLB1din time, such that a read/write margin to the bit cell BC will be degraded.

As illustratively shown inFIG.7andFIG.8, during a time duration DWLk, the word line signal to the word line WLk is switched to the high voltage level, the bit cell BC connected with the word line WLk shall be ready to read/write, such that a falling edge of the control signal BLEQBd is required to arrive at the same time as (or after) a falling edge of the word line signal on the word line WLk. If the falling edge of the control signal BLEQBd arrives before the falling edge of the word line signal on the word line WLk, the modulation circuit242amay boost both of the voltage levels on the bit line BL1dand the complement bit line BLB1dto the high voltage levels while the word line WLk still activating an access to the bit cell BC, such that the data bit stored in the bit cell BC may be damaged due to the wrong configuration of the voltage levels on the bit line BL1dand the complement bit line BLB1d.

In other words, the time duration D1of the control signal BLEQBd switching to the high voltage level is required to enclose the rising edge of the word line signal on the word line WL1and the falling edge of the word line signal on the word line WLk. In some embodiments, the control signal generator262-1is able to generate the control signal BLEQBd at the correct timing with reference to the half depth distance DPh.

For similar reasons, the time duration D2of the control signal BLEQBu switching to the high voltage level is required to enclose the rising edge of the word line signal on the word line WLk+1 and the falling edge of the word line signal on the word line WL2k. In some embodiments, the control signal generator262-1is able to generate the control signal BLEQBu at the correct timing with reference to the half depth distance DPh and the full depth distance DPf.

As shown inFIG.7, the control signal generator262-1in some embodiments includes two tracking wirings TR1and TR2, three logic gates NOR1, NOR2and NAND2and six inverters INV1a, INV1b, INV2, INV3a, INV3band INV4. In some embodiments, the control signal generator262-1includes two sets of logic gates NOR1and NOR2coupled with two sets of tracking wirings TR1and TR2.

In some embodiments, the control signal generator262-1receives an input control signal PRE and an inverted input clock signal CKPB. In some embodiments, the logic gate NOR1and the inverter INV3ais configured to generate the control signal BLEQBd, transmitted to the modulation circuit242acorresponding to the subarray222, according to an input clock signal CKP and a first delayed clock signal CKPd1. Behaviors and functions of the logic gate NOR1and the inverter INV3ain the control signal generator262-1shown inFIG.7are similar to the logic gate NOR1and the inverter INV3in the control signal generator162-1shown inFIG.5. A relationship between the inputs of the logic gate NOR1and the output of the inverter INV3ais shown in Table 3.

TABLE 3first inputsecond inputoutput terminalterminalterminalof inverter INV3a(CKP)(CKPd1)(BLEQBd)LLLLHHHLHHHH

In some embodiments, the logic gate NOR2and the inverter INV3bis configured to generate the control signal BLEQBu, transmitted to the modulation circuit243acorresponding to the subarray224, according to the first delayed clock signal CKP and a second delayed clock signal CKPd2. Behaviors and functions of the logic gate NOR2and the inverter INV3bin the control signal generator262-1shown inFIG.7are similar to the logic gate NOR1and the inverter INV3in the control signal generator162-1shown inFIG.5. A relationship between the inputs of the logic gate NOR2and the output of the inverter INV3bis shown in Table 4.

TABLE 4first inputsecond inputoutput terminalterminalterminalof inverter INV3a(CKPd1)(CKPd2)(BLEQBu)LLLLHHHLHHHH

As shown in embodiments inFIG.7andFIG.8, the first delayed clock signal CKPd1is generated by delaying the input clock signal CKP with the tracking wiring TR1. The tracking wiring TR1has a tracking length positively correlated with a half depth distance DPh of the word lines WL1˜WL2kof the whole memory array220. In other words, the half depth distance DPh is about a full depth distance of the word lines WL1-WLk of the subarray222. As shown inFIG.7, in some embodiments, the tracking wiring TR1includes a first tracking segment S1and a second tracking segment S2. The first tracking segment S1extends from a bottom side edge of the word lines WL1˜WL2ktoward a quarter position of the word lines WL1˜WL2k. For example, when there are total 2048 word lines (k=1024) in the whole memory array220, the first tracking segment S1extends from the word line WL1to the 512thword line (not shown in figures). The second tracking segment S2extends from the quarter position of the word lines WL1˜WL2ktoward the bottom side edge of the word lines WL1˜WL2k. In this case, the sum of lengths of the first tracking segment S1and the second tracking segment S2is similar or approximately equal to the half depth distance DPh. The half depth distance DPh can be regarded as the full depth distance of the word lines WL1˜WLk of the subarray222.

A rising edge of the control signal BLEQBd generated by the inverter INV3aand the logic gate NOR1inFIG.7andFIG.8is triggered by a rising edge of the input clock signal CKP. With the help of the tracking wiring TR to track the delay about the half depth distance DPh, a falling edge of the control signal BLEQBd generated by the inverter INV3aand the logic gate NOR1inFIG.7is triggered by a falling edge of the first delayed clock signal CKPd1, which is equal to the input clock signal CKP after being delayed by the tracking wiring TR1. In this case, as shown inFIG.8, the time duration D1of the control signal BLEQBd switching to the high voltage level is able to enclose the rising edge of the word line signal on the word line WL1and the falling edge of the word line signal on the word line WLk.

As shown in embodiments inFIG.7andFIG.8, the second delayed clock signal CKPd2is generated by delaying the input clock signal CKP with the tracking wiring TR2. The tracking wiring TR2has a tracking length positively correlated with a full depth distance DPh of the word lines WL1˜WL2kof the whole memory array220. As shown inFIG.7, in some embodiments, the tracking wiring TR2includes a third tracking segment S3and a fourth tracking segment S4. The third tracking segment S3extends from a bottom side edge of the word lines WL1˜WL2ktoward a half position of the word lines WL1˜WL2k. For example, when there are total 2048 word lines (k=1024) in the whole memory array220, the first tracking segment S3extends from the 1stword line WL1to the 1024thword line WLk. The fourth tracking segment S4extends from the half position of the word lines WL1˜WL2ktoward the bottom side edge of the word lines WL1˜WL2k. In this case, the sum of lengths of the third tracking segment S3and the fourth tracking segment S4is similar or approximately equal to the full depth distance DPf.

A rising edge of the control signal BLEQBu generated by the inverter INV3band the logic gate NOR2inFIG.7andFIG.8is triggered by a rising edge of the the first delayed clock signal CKPd1. With the help of the tracking wiring TR2to track the delay about the half depth distance DPf, a falling edge of the control signal BLEQBu generated by the inverter INV3band the logic gate NOR2inFIG.7is triggered by a falling edge of the second delayed clock signal CKPd2, which is equal to the input clock signal CKP after being delayed by the tracking wiring TR2. In this case, as shown inFIG.8, the time duration D2of the control signal BLEQBu switching to the high voltage level is able to enclose the rising edge of the word line signal on the word line WLk+1 and the falling edge of the word line signal on the word line WL2k.

In embodiments discussed above, the control signal BLEQBd generated by the control signal generator262-1is determined according to the depth distance of the subarray222, such that the control signal BLEQBd is switched to the high voltage level in time before (or at the same time) the word line WL1is set to the high voltage level, the control signal BLEQBd is hold at the high voltage level long enough until the word line WLk is set to the low voltage level. On the other hand, the control signal BLEQBu generated by the control signal generator262-1is determined according to the depth distance of the subarray224, such that the control signal BLEQBu is switched to the high voltage level in time before (or at the same time) the word line WLk+1 is set to the high voltage level, the control signal BLEQBu is hold at the high voltage level long enough until the word line WL2kis set to the low voltage level.

It is noticed that the control signal generator262-1illustratively shown inFIG.7is one exemplary embodiment to achieve the control signal generator262shown inFIG.6. The logic functions of the logic gates NOR1and NOR2in the control signal generator262-1are similar to the embodiments of the logic gate NOR1of the control signal generator162-3shown inFIG.5. However, the disclosure is not limited thereto. In some other embodiments, the control signal generator262inFIG.6can be achieved with other equivalent structures, for example, each of the logic gates NOR1and NOR2in the control signal generator262-1can be replaced by structures of the logic gate NAND1of the control signal generator162-1shown inFIG.2, or replaced by structures of the logic gate NOR1of the control signal generator162-2shown inFIG.4.

In some embodiments, a device includes a first memory subarray, a first modulation circuit, a second memory subarray, a second modulation circuit and a control signal generator. The first modulation circuit is coupled to the first memory subarray. The second memory subarray is located between the first memory subarray and the first modulation circuit along a direction. The second modulation circuit is coupled to the second memory subarray. The control signal generator is configured to generate a first control signal to trigger the first modulation circuit according to a first length of the first memory subarray along the direction, and configured to generate a second control signal to trigger the second modulation circuit according to a second length of the second memory subarray along the direction.

In some embodiments, a device includes: a first bit line; a second bit line complement to the first bit line; a first switch configured to couple the first bit line to the second bit line; a third bit line longer than the first bit line along a direction; a fourth bit line complement to the third bit line; and a second switch configured to couple the third bit line to the fourth bit line. Each of the first switch and the second switch is controlled according to a length of the first bit line along the direction.

In some embodiments, a device includes: a memory array having a plurality of bit cells arranged in rows and columns, wherein the memory array comprises a first subarray of bit cells and a second subarray of bit cells; a first bit line pair, coupled to bit cells in the first subarray on a first column of the memory array; a second bit line pair, coupled to bit cells in the second subarray on the first column of the memory array; a plurality of word lines, extending along a plurality of rows of the memory array; a first modulation circuit coupled with the first bit line pair; a second modulation circuit coupled with the second bit line pair; a word line decoder coupled with the plurality of word lines; and a control signal generator coupled with the first modulation circuit and the second modulation circuit. The control signal generator is configured to produce a first control signal to the word line decoder for generating first word line signals to the first subarray and generating second word line signals to the second subarray, the control signal generator is configured to produce a second control signal to the first modulation circuit in reference with a first tracking wiring, a rising edge of the second control signal occurs before rising edges of the first word line signals, a falling edge of the second control signal occurs after falling edges of the first word line signals, the control signal generator is configured to produce a third control signal to the second modulation circuit in reference with a second tracking wiring, a rising edge of the third control signal occurs before rising edges of the second word line signals, a falling edge of the third control signal occurs after falling edges of the second word line signals.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.