Patent ID: 12190804

DETAILED DESCRIPTION

In order to make objects, technical details and advantages of the embodiments of the disclosure apparent, the technical solutions of the embodiments will be described in a clearly and fully understandable way in connection with the drawings related to the embodiments of the disclosure. Apparently, the described embodiments are just a part but not all of the embodiments of the disclosure. Based on the described embodiments herein, those skilled in the art can obtain other embodiment(s), without any inventive work, which should be within the scope of the disclosure.

Unless otherwise defined, all the technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. The terms “first,” “second,” etc., which are used in the description and the claims of the present application for disclosure, are not intended to indicate any sequence, amount or importance, but distinguish various components. Likewise, the terms such as “a,” “an,” or “the” do not indicate a limitation of quantity, but rather indicate the presence of at least one. The terms “comprise,” “comprising,” “include,” “including,” etc., are intended to specify that the elements or the objects stated before these terms encompass the elements or the objects and equivalents thereof listed after these terms, but do not preclude the other elements or objects. For the convenience of description, in some drawings, “top,” “bottom,” “front” and “rear” are used. In the embodiments of the present disclosure, the vertical direction is the direction from top to bottom, and the vertical direction is the direction of gravity. The horizontal direction is the direction perpendicular to the vertical direction, and the horizontal direction is from right to left or is from front to rear.

LTPO (Low Temperature Polycrystalline Oxide) is a technology that is capable of reducing the power consumption of the display panel but has not been widely used in the display industry at present. With the development of the market, LTPO is bound to have a very broad application market in the next few years. At present, it is necessary to combine new technologies, such as LTPO, to further reduce the power consumption of the display panel. Furthermore, while reducing the power consumption of the display panel, it is also necessary to ensure the high-resolution characteristics of the display panel.

At least one embodiment of the present disclosure provides a display substrate, and the display substrate includes a base substrate and a plurality of reset signal lines. The base substrate includes a display region, the display region includes a plurality of sub-pixels arranged in an array, each of the plurality of sub-pixels includes a pixel driving circuit and a light-emitting element, and the pixel driving circuit is configured to drive the light-emitting element to emit light. The plurality of reset signal lines extend in a first direction, the plurality of reset signal lines include a plurality of first reset signal lines for providing a first reset signal and a plurality of second reset signal lines for providing a second reset signal, one of the plurality of first reset signal lines and one of the plurality of second reset signal lines are respectively connected to pixel driving circuits of a plurality of sub-pixels located in a same row, and a layer where the plurality of first reset signal lines are located is different from a layer where the plurality of second reset signal lines are located.

At least one embodiment of the present disclosure further provides a display device including the display substrate mentioned above.

In the display substrate and the display device provided by the embodiments of the present disclosure, one of the plurality of first reset signal lines and one of the plurality of second reset signal lines are respectively connected to the pixel driving circuits of the plurality of sub-pixels located in the same row, and the layer where the plurality of first reset signal lines are located is different from the layer where the plurality of second reset signal lines are located, which is beneficial to improve the display quality of the display substrate and reduce the wiring layout space of the pixel driving circuit of the display substrate.

The embodiments of the present disclosure and examples thereof are described in detail below with reference to the accompanying drawings.

FIG.1is a schematic view of a display substrate provided by at least one embodiment of the present disclosure.FIG.2is a schematic layout view of a pixel driving circuit of the display substrate provided by at least one embodiment of the present disclosure.

For example, in some embodiments, as illustrated inFIG.1, the display substrate1includes a base substrate10including a display region101and a peripheral region102. The display region101includes a plurality of sub-pixels100. The peripheral region102includes a bonding region103. The bonding region103is located on one side of the display region101(e.g., the lower part in the figure). For example, the plurality of sub-pixels100are arranged in rows and columns along a first direction Y and a second direction X. The first direction Y and the second direction X are different, for example, they are orthogonal to each other.

Each sub-pixel100includes a light-emitting element120(for example, illustrated inFIG.15B) and a pixel driving circuit105(for example, illustrated inFIG.2) that drives the light-emitting element120to emit light. For example, a plurality of pixel driving circuits105are arranged in an array along the first direction Y and the second direction X. For example, the plurality of sub-pixels are arranged to constitute a conventional pixel unit of RGB pattern. In other embodiments, the sub-pixels constitute a pixel unit in a manner of sharing some sub-pixels (for example, pentile) to realize full-color display. The present disclosure does not limit the arrangement of the sub-pixels.

For example, as illustrated inFIG.1, the display substrate1further includes a plurality of gate lines12(e.g., first scanning signal lines, second scanning signal lines, light-emitting control lines, first reset control signal lines, second reset control signal lines, etc.), a plurality of data lines11and a plurality of pixel regions, and each pixel region is correspondingly provided with one sub-pixel100. For example, the gate lines12extend along the first direction Y, and the data lines11extend along the second direction X.FIG.2only illustrates the approximate positional relationship of the gate lines12, the data lines11and the sub-pixels100in the display substrate, which may be specifically designed according to actual needs.

The pixel driving circuit105is, for example, a 2T1C (i.e., two transistors and one capacitor) pixel driving circuit, or an nTmC (n and m are positive integers) pixel driving circuit such as 4T2C, 5T1C, and 7T1C. And in different embodiments, the pixel driving circuit105for example further includes a compensation sub-circuit, the compensation sub-circuit includes an internal compensation sub-circuit or an external compensation sub-circuit, and the compensation sub-circuit includes a transistor, a capacitor, and the like. For example, the pixel driving circuit105further includes a reset circuit, a light-emitting control sub-circuit, a detection circuit, and the like, as required.

For example, the display substrate1further includes a gate driving circuit13located in the peripheral region102and a data driving circuit14located in the bonding region103. The gate driving circuit13is electrically connected to the pixel driving circuit105through the gate line12to provide various scanning signals (e.g., a first scanning signal, a second scanning signal, a light-emitting control signal, a first reset control signal, a second reset control signal, etc.), and the data driving circuit14is electrically connected to the pixel driving circuit105through the data line11to provide a data signal. The positional relationship of the gate driving circuit13and the data driving circuit14, the gate line12and the data line11in the display substrate illustrated inFIG.1is just an example, and the actual arrangement position may be designed as required.

For example, the display substrate1further includes a control circuit (not illustrated). For example, the control circuit is configured to control the data driving circuit14to apply the data signal, and to control the gate driving circuit to apply the various scanning signals. An example of the control circuit is a timing control circuit (T-con). The control circuit may be in various forms, including, for example, a processor and a memory, and the memory includes executable code that is executed by the processor to perform the controlling process described above.

For example, the processor is a central processing unit (CPU) or other form of processing device with data processing capabilities and/or instruction execution capabilities, which includes, for example, a microprocessor, a programmable logic controller (PLC), or the like.

For example, the memory includes one or more computer program products. The memory may include various kinds of computer readable storage media, e.g., volatile memory and/or nonvolatile memory. Volatile memory, for example, includes a random access memory (RAM) and/or a cache memory. Nonvolatile memory, for example, includes read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions for example are stored in the computer readable storage medium, and the processor executes the program instructions to realize the desired functions. Various application programs and various data for example are also stored in the computer readable storage medium.

For example, in some embodiments, as illustrated inFIG.2, the display substrate1includes a plurality of reset signal lines. The plurality of reset signal lines extend along the first direction Y. The plurality of reset signal lines include a plurality of first reset signal lines RL1for providing a first reset signal and a plurality of second reset signal lines RL2for providing a second reset signal. Each of the plurality of first reset signal lines RL1is electrically connected to pixel driving circuits105of sub-pixels100in one row. Each of the plurality of second reset signal lines RL2is electrically connected to pixel driving circuits105of sub-pixels100in one row. One of the plurality of first reset signal lines RL1and one of the plurality of second reset signal lines RL2are respectively connected to pixel driving circuits of a plurality of sub-pixels located in a same row, and provide the first reset signal and the second reset signal to the pixel driving circuits105of the plurality of sub-pixels100in the same row, so as to improve the display quality of the display substrate1. The layer where the plurality of first reset signal lines RL1are located is different from the layer where the plurality of second reset signal lines RL2are located. That is, the layer where the first reset signal line RL1is located is different from the layer where the second reset signal line RL2is located, so as to reduce the wiring space of the pixel driving circuit.

For example, in some embodiments, as illustrated inFIG.1andFIG.2, the plurality of sub-pixels100are arranged in N rows, one of the plurality of second reset signal lines RL2(located in an (M−1)th row) is electrically connected to pixel driving circuits105of sub-pixels100in the (M−1)th row (an upper row inFIG.2), and one of the plurality of first reset signal lines RL1(located in an (M)th row) is electrically connected to pixel driving circuits105of sub-pixels100in the (M)th row. For example, 1<M≤N, and M and N are positive integers greater than or equal to 2. Referring to appropriately middle position inFIG.2A, the second reset signal line RL2is electrically connected to the pixel driving circuits105of the current row (i.e. the (M−1)th row), and the first reset signal line RL1is electrically connected to the pixel driving circuits105of the next row (i.e. the (M)th row). The orthographic projection of the second reset signal line RL2, that is electrically connected to the pixel driving circuits105of the sub-pixels in the (M−1)th row, on the base substrate10at least partially overlaps with the orthographic projection of the first reset signal line RL1, that is electrically connected to the pixel driving circuits105of the sub-pixels in the (M)th row, on the base substrate10, thereby reducing the wiring space in the pixel driving circuit105and improving the resolution of the display substrate.

For example, in some embodiments, as illustrated inFIG.2, in a region where one sub-pixel of the sub-pixels in the (M−1)th row is located (for example, the region where the pixel driving circuit of the one sub-pixel is located, illustrated as a dotted box in the figure), an area of an overlapping region between the orthographic projection of the second reset signal line RL2, that is electrically connected to the pixel driving circuits of the sub-pixels in the (M−1)th row, on the base substrate10and the orthographic projection of the first reset signal line RL1, that is electrically connected to the pixel driving circuits of the sub-pixels in the (M)th row, on the base substrate10is greater than 50% of an area of the orthographic projection of the second reset signal line RL2on the base substrate10, or greater than 50% of an area of the orthographic projection of the first reset signal line RL1on the base substrate10. Therefore, the overlapping portion between the first reset signal line RL1and the second reset signal line RL2is relatively large, thereby reducing the wiring space in the pixel driving circuit105and improving the resolution of the display substrate.FIG.14Ais a schematic layout view of a fourth metal layer of the display substrate provided by at least one embodiment of the present disclosure.

For example, in some embodiments, as illustrated inFIG.2andFIG.14A, the display substrate1further includes a plurality of first power supply voltage lines VDD1. Each of the first power supply voltage lines VDD1extends along the second direction X different from the first direction Y, and is electrically connected to the pixel driving circuits105of a plurality of sub-pixels in a same column and provides a first power supply voltage (e.g., a high level). Along the second direction X, the first power supply voltage line VDD1includes a bent portion VDD10between orthographic projections of two adjacent first reset signal lines RL1on the base substrate10. That is, the orthographic projection of the bent portion VDD10on the base substrate10overlaps with the orthographic projection of the pixel driving circuit105on the base substrate10. The bent portion of the first power supply voltage line VDD1forms a capacitance with a trace of other metal layers or serves as a shielding layer of other layers.

It should be noted that in the embodiments of the present disclosure, an orthographic projection of each trace or layer on the base substrate10is, for example, regarded as an orthographic projection of each trace or layer on the board surface S (as illustrated inFIG.4A, for example, the upper surface of the base substrate10) of the base substrate10.

For example, in some embodiments, as illustrated inFIG.2andFIG.14A, a partial line segment (for example, a part of the horizontal trace inFIG.14A) of the first power supply voltage line VDD1is routed along the first direction Y, and the line width W2of the partial line segment is smaller than the line width W1of at least a portion (for example, a part of the vertical trace inFIG.14A) of the first power supply voltage line VDD1that is routed along the second direction X. Thereby, the wiring space of the first power supply voltage line VDD1can be reduced.

It should be noted that, the line width of a trace described in the embodiments of the present disclosure refers to the width of the trace along a direction perpendicular to its extension direction.

FIG.3Ais a schematic view of a pixel driving circuit provided by at least one embodiment of the present disclosure.FIG.3Bis another schematic view of the pixel driving circuit provided by at least one embodiment of the present disclosure.

As illustrated inFIG.3A, the pixel driving circuit105includes a driving sub-circuit122and a compensation sub-circuit128.

For example, the driving sub-circuit122is electrically connected to a first node N1, a second node N2and a third node N3, and is configured to control the driving current flowing through the light-emitting element120under the control of the level of the first node N1. The driving sub-circuit122includes a control terminal (control electrode)122a, a first terminal (first electrode)122b, and a second terminal (second electrode)122c, and is configured to be connected to the light-emitting element120and to control the driving current flow through the light-emitting element120. The control terminal122aof the driving sub-circuit122is connected to the first node N1, the first terminal122bof the driving sub-circuit122is connected to the second node N2, and the second terminal122cof the driving sub-circuit122is connected to the third node N3.

For example, the compensation sub-circuit128is electrically connected to the first node N1and the third node N3, and is configured to receive a second scanning signal and perform threshold compensation on the driving sub-circuit122in response to the scanning signal. For example, the scanning signal is the second scanning signal provided by the second scanning signal line GL2(illustrated inFIG.2). The compensation sub-circuit128includes a control terminal (control electrode)128a, a second terminal (second electrode)128band a first terminal (first electrode)128c, and the control terminal128aof the compensation sub-circuit128is configured to receive the second scanning signal Ga2. The second terminal128band the first terminal128cof the compensation sub-circuit128are electrically connected to the second terminal122cand the control terminal122aof the driving sub-circuit122, respectively, and the compensation sub-circuit128is configured to perform threshold compensation on the driving sub-circuit122in response to the second scanning signal Ga2.

For example, the pixel driving circuit105further includes a data writing sub-circuit126, a storage sub-circuit127, a first light-emitting control sub-circuit123, a second light-emitting control sub-circuit124, a first reset sub-circuit125and a second reset sub-circuit129.

For example, the data writing sub-circuit126is electrically connected to the second node N2, and is configured to receive a first scanning signal Ga1, and write a data signal to the driving sub-circuit data122in response to the first scanning signal Ga1. The data writing sub-circuit126includes a control terminal126a, a first terminal (first electrode)126band a second terminal (second electrode)126c, the control terminal126ais configured to receive the first scanning signal Ga1, the first terminal126bis configured to receive the data signal Vd, and the second terminal126cis connected to the first terminal122b(i.e., the second node N2) of the driving sub-circuit122. The data writing sub-circuit126is configured to write the data signal Vd to the first terminal122bof the driving sub-circuit122in response to the first scanning signal Ga1. For example, the first terminal126bof the data writing sub-circuit126is connected to the data line11(as illustrated inFIG.2) to receive the data signal Vd, and the control terminal126ais connected to the first scanning signal line GL1(as illustrated inFIG.2) to receive the first scanning signal Ga1. For example, in a data writing and compensation phase, the data writing sub-circuit126is turned on in response to the first scanning signal Ga1, so that the data signal is written into the first terminal122b(the second node N2) of the driving sub-circuit122, and the data signal is stored in the storage sub-circuit127, so that the driving current for driving the light-emitting element120to emit light is generated according to the data signal in a light-emitting phase, for example.

For example, in some embodiments of the present disclosure, the first scanning signal Ga is different from the second scanning signal Ga2. For example, the first scanning signal Ga1and the second scanning signal Ga2are connected to different signal output terminals, respectively. For example, the first scanning signal Ga1and the second scanning signal Ga2are transmitted through different scanning signal lines (the first scanning signal line GL1and the second scanning signal line GL2), respectively.

For example, in other embodiments, the first scanning signal Ga1is the same as the second scanning signal Ga2. For example, the scanning signal Ga1is connected to the same signal output terminal as the scanning signal Ga2. For example, the scanning signal Ga1and the scanning signal Ga2are transmitted through the same scanning signal line.

For example, the storage sub-circuit127is electrically connected to the first node N1and is configured to store the data signal. The storage sub-circuit127includes a second terminal (also referred to as a second storage electrode)127aand a first terminal (also referred to as a first storage electrode)127b, the second terminal127aof the storage sub-circuit is configured to receive a first power supply voltage VDD, and the first terminal127bof the storage sub-circuit is electrically connected to the control terminal122aof the driving sub-circuit122. For example, in the data writing and compensation phase, the compensation sub-circuit128is turned on in response to the second scanning signal Ga2, so that the data signal written by the data writing sub-circuit126is stored in the storage sub-circuit127. At the same time, the compensation sub-circuit128electrically connects the control terminal122aand the second terminal122cof the driving sub-circuit122, so that the relevant information of the threshold voltage of the driving sub-circuit122is correspondingly stored in the storage sub-circuit127, so that, for example, in a light-emitting stage, the data signal and the threshold voltage that are stored are used to control the driving sub-circuit122, so that the output of the driving sub-circuit122is compensated.

For example, in the data writing and compensation phase, the compensation sub-circuit128is turned on in response to the second scanning signal Ga2, so that the data signal Vd written by the data writing sub-circuit126is stored in the storage sub-circuit127. For example, in the data writing and compensation phases at the same time, the compensation sub-circuit128electrically connects the control terminal122aand the second terminal122cof the driving sub-circuit122, so that the relevant information of the threshold voltage of the driving sub-circuit122is also correspondingly stored in the storage sub-circuit, so that, for example, in a light-emitting stage, the data signal and the threshold voltage that are stored are used to control the driving sub-circuit122, so that the output of the driving sub-circuit122is compensated.

For example, the first light-emitting control sub-circuit123is electrically connected to the second node N2, and is configured to apply the first power supply voltage VDD to the driving sub-circuit122in response to a light-emitting control signal. The first light-emitting control sub-circuit123is connected to the first terminal122b(the second node N2) of the driving sub-circuit122and the first power supply voltage terminal VDD, and is configured to apply the first power supply voltage VDD of the first power supply voltage terminal VDD to the first terminal122bof the driving sub-circuit122in response to the first light-emitting control signal EM1. For example, as illustrated inFIG.4B, the first light-emitting control sub-circuit123is connected to the first light-emitting control terminal EM1, the first power supply voltage terminal VDD and the second node N2.

For example, the second light-emitting control sub-circuit124is electrically connected to the third node N3and a fourth node N4, and is configured to enable the driving current to be applied to the light-emitting element120in response to a light-emitting control signal. The second light-emitting control sub-circuit124is connected to a second light-emitting control terminal EM2, the first terminal (first electrode)134of the light-emitting element120, and the second terminal122cof the driving sub-circuit122, and is configured to enable the driving current to be applied to the light-emitting element120in response to the second light-emitting control signal EM2.

For example, in the light-emitting phase, the second light-emitting control sub-circuit124is turned on in response to the second light-emitting control signal EM2provided by the second light-emitting control terminal EM2, so that the driving sub-circuit122is electrically connected to the light-emitting element120through the second light-emitting control sub-circuit124, thereby driving the light-emitting element120to emit light under the control of the driving current. And in a non-light-emitting phase, the second light-emitting control sub-circuit124is turned off in response to the second light-emitting control signal EM2, so as to prevent current from flowing through the light-emitting element120to emit light, thereby improving the contrast ratio of the corresponding display device.

For another example, in an initialization phase, the second light-emitting control sub-circuit124is turned on in response to the second light-emitting control signal, so as to be combined with a reset circuit to perform a reset operation on the driving sub-circuit122and the light-emitting element120.

For example, the second light-emitting control signal EM2is the same as the first light-emitting control signal EM1. For example, the second light-emitting control signal EM2is connected to the same signal output terminal as the first light-emitting control signal EM1. For example, the light-emitting control signal EM2is transmitted through the same light-emitting control line EML (as illustrated inFIG.2) as the light-emitting control signal EM1.

In other examples, the second light-emitting control signal EM2is different from the first light-emitting control signal EM1. For example, the second light-emitting control signal EM2and the first light-emitting control signal EM1are respectively connected to different signal output terminals. For example, the second light-emitting control signal EM2and the first light-emitting control signal EM1are respectively transmitted through different light-emitting control lines.

The embodiments of the present disclosure are described as examples in which the first scanning signal Ga1and the second scanning signal Ga2are respectively transmitted through different scanning signal lines (the first scanning signal line GL1and the second scanning signal line GL2), and the second light-emitting control signal EM2and the first light-emitting control signal EM1are transmitted through the same light-emitting control line EML (as illustrated inFIG.2).

For example, the first reset sub-circuit125is electrically connected to the first node N1and is configured to apply a first reset voltage Vinit1(e.g., a first reset signal) to the first node N1in response to a first reset control signal Rst1. The first reset sub-circuit125is connected to a first reset voltage terminal Vinit1and the control terminal122a(the first node N1) of the driving sub-circuit122, and is configured to apply the first reset voltage Vinit1(i.e., the first reset signal) to the control terminal122aof the driving sub-circuit122in response to the first reset control signal Rst1.

For example, the second reset sub-circuit129is electrically connected to the fourth node N4and is configured to apply a second reset voltage Vinit2(e.g., a second reset signal) to the fourth node N4in response to a second reset control signal Rst2. The second reset sub-circuit129is connected to a second reset voltage terminal Vinit2and the fourth node N4, and is configured to apply the second reset voltage Vinit2(i.e., the second reset signal) to the first terminal134of the light-emitting element120in response to the second reset control signal Rst2.

For example, the first reset sub-circuit125and the second reset sub-circuit129are respectively turned on in response to the first reset control signal Rst1and the second reset control signal Rst2, so that the second reset voltage Vinit2is applied to the first node N1and the first reset voltage Vinit1is applied to the first terminal134of the light-emitting element120, thereby performing a reset operation on the driving sub-circuit122, the compensation sub-circuit128and the light-emitting element120to eliminate the influence of the light-emitting phase performed before.

For example, the first reset control signal Rst1and the first reset voltage Vinit1of each row of sub-pixels100are provided by the first reset control signal line RCL1(as illustrated inFIG.2) and the first reset signal line RL1(on a row above the row of sub-pixels100) which are electrically connected to the row of sub-pixels100. For example, the second reset control signal Rst2and the second reset voltage Vinit2of each row of sub-pixels100are provided by the second reset control signal line RCL2(as illustrated inFIG.2) and the second reset signal line RL2which are electrically connected to the row of sub-pixels100.

For example, the light-emitting element120includes the first terminal (also referred to as a first electrode)134and a second terminal (also referred to as a second electrode)135, the first terminal134of the light-emitting element120is configured to be connected to the second terminal122cof the driving sub-circuit122, and the second terminal135(e.g., the second electrode) of the light-emitting element120is configured to be connected to a second power supply voltage terminal VSS. For example, in one example, as illustrated inFIG.3B, the first terminal134of the light-emitting element120is connected to the fourth node N4through the second light-emitting control sub-circuit124, and the embodiments of the present disclosure include but are not limited to this case.

For example, in the embodiments of the present disclosure, a second power supply voltage VSS provided by the second power supply voltage terminal VSS is supplied to the second terminal135of the light-emitting element120. The first power supply voltage VDD is at a high level, and the second power supply voltage VSS is at a low level.

It should be noted that, in the description of the embodiments of the present disclosure, the first node N1, the second node N2, the third node N3and the fourth node N4do not necessarily represent actual components, but represent the junctions of related circuit connections in the circuit diagram.

It should be noted that in the description of the embodiments of the present disclosure, the symbol Vd for example represents both the data signal terminal and the level of the data signal. Similarly, for example, the symbols Ga1and Ga2represent the first scanning signal and the second scanning signal, and also represent the first scanning signal terminal and the second scanning signal terminal. For example, the symbols Rst1and Rst2represent the first reset control terminal and the second reset control terminal, and also represent the first reset control signal and the second reset control signal. For example, the symbols Vinit1and Vinit2represent the first reset voltage terminal and the second reset voltage terminal, and also represent the first reset voltage and the second reset voltage. The symbol VDD for example represents both the first power supply voltage terminal and the first power supply voltage. The symbol VSS for example represents both the second supply voltage terminal and the second supply voltage. The following embodiments are the same and will not be repeated.

As illustrated inFIG.3B, the pixel driving circuit105includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and further includes a storage capacitor Cst. For example, the first transistor T1is used as a driving transistor, and the other second to seventh transistors are used as switching transistors.

For example, as illustrated inFIG.3B, the driving sub-circuit122is implemented as the first transistor T1. A gate electrode of the first transistor T1serves as the control terminal122aof the driving sub-circuit122, and is connected to the first node N1. A first electrode of the first transistor T1serves as the first terminal122bof the driving sub-circuit122, and is connected to the second node N2. A second electrode of the first transistor T1serves as the second terminal122cof the driving sub-circuit122, and is connected to the third node N3.

For example, as illustrated inFIG.3B, the data writing sub-circuit126is implemented as the second transistor T2. A gate electrode of the second transistor T2is connected to the first scanning signal line GL (the first scanning signal terminal Ga1) to receive the first scanning signal Ga1, a first electrode of the second transistor T2is connected to the data line11(the data signal terminal Vd) to receive the data signal Vd, and a second electrode of the second transistor T2is connected to the first terminal122b(the second node N2) of the driving sub-circuit122.

For example, as illustrated inFIG.3B, the compensation sub-circuit128is implemented as the third transistor T3. A gate electrode, a second electrode and a first electrode of the third transistor T3serve as the control electrode128a, the second electrode128band the first electrode128cof the compensation sub-circuit, respectively. The gate electrode of the third transistor T3is configured to be connected to the second scanning signal line GL (the second scanning signal terminal Ga2) to receive the second scanning signal Ga2, the second electrode of the third transistor T3is connected to the second terminal122c(the third node N3) of the driving sub-circuit122, and the first electrode of the third transistor T3is connected to the control terminal122a (the first node N1) of the driving sub-circuit122.

For example, as illustrated inFIG.3B, the storage sub-circuit127is implemented as the storage capacitor Cst, and the storage capacitor Cst includes a second capacitor electrode Ca and a first capacitor electrode Cb. The second capacitor electrode Ca is coupled, e.g. electrically connected, to the first power supply voltage terminal VDD, and the first capacitor electrode Cb is coupled, e.g. electrically connected, to the control terminal122aof the driving sub-circuit122.

It should be noted that, in the embodiments of the present disclosure, Ca represents both the second capacitor electrode and a second electrode plate, and Cb represents both the first capacitor electrode and a first electrode plate.

For example, as illustrated inFIG.3B, the first light-emitting control sub-circuit123is implemented as the fourth transistor T4. A gate electrode of the fourth transistor T4is connected to the light-emitting control line EML (the first light-emitting control terminal EM1) to receive the light-emitting control signal EM1, a first electrode of the fourth transistor T4is connected to the first power supply voltage terminal VDD to receive the first power supply voltage VDD, and a second electrode of the fourth transistor T4is connected to the first terminal122b(the second node N2) of the driving sub-circuit122.

For example, the light-emitting element120is embodied as a light-emitting diode (LED), for example an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or an inorganic light-emitting diode, such as a micro light-emitting diode (Micro LED) or a micro OLED. For example, the light-emitting element120is a top emitting structure, a bottom emitting structure, or a double-sided emitting structure. The light-emitting element120emits red light, green light, blue light or white light, and the like. The embodiments of the present disclosure do not limit the specific structure of the light-emitting element.

For example, a first electrode134(e.g., an anode) of the light-emitting element120is connected to the fourth node N4and is configured to be connected to the second terminal122cof the driving sub-circuit122through the second light-emitting control sub-circuit124, and a second electrode135(e.g., a cathode) of the light-emitting element120is configured to be connected to the second power supply voltage terminal VSS to receive the second power supply voltage VSS. The current flowing into the light-emitting element120from the second terminal122cof the driving sub-circuit122determines the brightness of the light-emitting element. For example, the second power supply voltage terminal is grounded, that is, VSS is at 0V. For example, the second voltage supply voltage VSS is a negative voltage.

For example, the second light-emitting control sub-circuit124is implemented as the fifth transistor T5. A gate electrode of the fifth transistor T5is connected to the light-emitting control line EML (the second light-emitting control terminal EM2) to receive the second light-emitting control signal EM2, a second electrode of the fifth transistor T5is connected to the second terminal122c(third node N3) of the driving sub-circuit122, and a first electrode of the fifth transistor T5is connected to the first terminal134(fourth node N4) of the light-emitting element120.

For example, the first reset sub-circuit125is implemented as the sixth transistor T6, and the second reset sub-circuit is implemented as the seventh transistor T7. A gate transistor of the sixth transistor T6is configured to be connected to the first reset control terminal Rst1to receive the first reset control signal Rst1, a first electrode of the sixth transistor T6is connected to the first reset voltage terminal Vinit1to receive the first reset voltage Vinit1, and a second electrode of the sixth transistor T6is configured to be connected to the first node N1. A gate transistor of the seventh transistor T7is configured to be connected to the second reset control terminal Rst2to receive the second reset control signal Rst2, a first electrode of the seventh transistor T7is connected to the second reset voltage terminal Vinit2to receive the second reset voltage Vinit2, and a second electrode of the seventh transistor T7is configured to be connected to the fourth node N4.

It should be noted that, the transistors used in the embodiments of the present disclosure for example are all thin film transistors, field effect transistors, or other switching devices with the same characteristics; and the thin film transistors are used as examples in the embodiments of the present disclosure. The source electrode and the drain electrode of the transistor used in the embodiments of the present disclosure for example is symmetrical in structure, so that the source electrode and the drain electrode is structurally indistinguishable. In the embodiments of the present disclosure, in order to distinguish the two electrodes of the transistor except the gate electrode, one electrode is directly described as the first electrode, and the other electrode is described as the second electrode.

In addition, the transistors is divided into N-type transistors or P-type transistors according to characteristics of the transistors. In a case where the transistor is a P-type transistor, turn-on voltage of the transistor is a low-level voltage (for example, 0V, −5V, −10V, or other appropriate voltage), and turn-off voltage of the transistor is a high-level voltage (for example, 5V, 10V, or other appropriate voltage). In a case where the transistor is an N-type transistor, turn-on voltage of the transistor is a high-level voltage (for example, 5V, 10V, or other appropriate voltage), and turn-off voltage of the transistor is a low-level voltage (for example, 0V, −5V, −10V, or other appropriate voltage). For example, as illustrated inFIG.3B, the first to seventh transistors T1-T7are all P-type transistors, such as low temperature polysilicon thin film transistors or low temperature polycrystalline oxide transistors, which will be described in detail later.

FIG.3Cis a timing signal view of the pixel driving circuit illustrated inFIG.3Bprovided by at least one embodiment of the present disclosure. The operation principle of the pixel driving circuit illustrated inFIG.3Bwill be described below with reference to the timing signal view illustrated inFIG.3C.

As illustrated inFIG.3C, the display process of each frame of image includes three phases, which are an initialization phase T10, a data writing and compensation phase T20, and a light-emitting phase T30.

During the initialization phase T10, the first reset control signal Rst1controls the sixth transistor T6to be turned on, so as to provide the signal transmitted on the first reset signal RL1(as illustrated inFIG.2) to the gate electrode of the first transistor T1to reset the gate electrode of the first transistor T1. The second reset control signal Rst2controls the seventh transistor T7to be turned on, so as to provide the signal transmitted on the second reset signal RL2(as illustrated inFIG.2) to the first terminal134of the light-emitting element120to reset the first terminal134of the light-emitting element120. And, during this phase, the first scanning signal Ga1controls the second transistor T2to be turned off. The second scanning signal Ga2controls the third transistor T3to be turned off. The first light-emitting control signal EM1or the second light-emitting control signal EM2controls both the fourth transistor T4and the fifth transistor T5to be turned off.

During the data writing and compensation phase T20, the first scanning signal Ga1controls the second transistor T2to be turned on, and the second scanning signal Ga2controls the third transistor T3to be turned on, so that the data signal transmitted on the data line11charges the control terminal of the first transistor T1, so that the voltage of the control terminal of the driving transistor T1becomes: Vdata+Vth, in which Vth represents the threshold voltage of the first transistor T1, and Vdata represents the voltage of the data signal. And, during this phase, the first reset control signal Rst1controls the sixth transistor T6to be turned off. The second reset control signal Rst2controls the seventh transistors T7to be turned off. The first light-emitting control signal EM1or the second light-emitting control signal EM2controls both the fourth transistor T4and the fifth transistor T5to be turned off.

During the light-emitting phase T30, the first light-emitting control signal EM1or the second light-emitting control signal EM2controls both the fourth transistor T4and the fifth transistor T5to be turned on. The fourth transistor T4that is turned on provides the voltage Vdd of the first power supply voltage terminal VDD to the first terminal of the first transistor T1, so that the voltage of the first terminal of the first transistor T1is Vdd. The driving transistor T1generates a driving current according to the voltage Vdata+|Vth| of the gate electrode of the driving transistor T1and the voltage Vdd of the first electrode. The driving current is supplied to the light-emitting element120through the fifth transistor T5that is turned on, thereby driving the light-emitting element120to emit light. Moreover, during this phase, the first reset control signal Rst1controls the sixth transistor T6to be turned off, and the second reset control signal Rst2controls the seventh transistor T7to be turned off. The first scanning signal Ga1controls the second transistor T2to be turned off, and the second scanning signal Ga2controls the third transistor T3to be turned off.

FIG.4Ais a schematic cross-sectional view along a section line A1-B1inFIG.2provided by at least one embodiment of the present disclosure.FIG.5Ais a schematic layout view of a first semiconductor layer of the display substrate provided by at least one embodiment of the present disclosure.FIG.5Bis a schematic layout view of a first metal layer of the display substrate provided by at least one embodiment of the present disclosure.FIG.5Cis a schematic layout view obtained by stacking the layers ofFIG.5AandFIG.5B.FIG.6Ais a schematic layout view of a second metal layer of a display substrate provided by at least one embodiment of the present disclosure.FIG.6Bis a schematic layout view obtained by stacking the layers ofFIG.5A,FIG.5BandFIG.6A.

For convenience of description, in the following description, Tng, Tns, Tnd, and Tna are used to represent a gate electrode, a first electrode, a second electrode and a channel region of an (n)th transistor Tn, respectively, where n is 1-7.

It should be noted that “provided in a same layer” described in the embodiments of the present disclosure refers to two (or more than two) structures, which are provided in a same layer, are formed by the same deposition process and patterned by the same patterning process, and materials of the two structures are the same or different. The “integrated structure” in the present disclosure refers to two (or more than two) structures, which are integrated, are formed by the same deposition process and patterned by the same patterning process and are connected to each other, and materials of the two structures are the same or different.

For example, in some embodiments, as illustrated inFIG.4AandFIG.5A, the display substrate1further includes a first semiconductor layer PL1, a first insulating layer142(a first gate insulating layer), a second insulating layer143(a second gate insulating layer) and a third insulating layer144(a first interlayer insulating layer) on the base substrate10. A plan layout view of the first semiconductor layer PL1is illustrated inFIG.5A. The semiconductor layer in each pixel driving circuit105is integrally provided. The first semiconductor layer PL1includes an active layer T1aof the first transistor T1, an active layer T2aof the second transistor T2, an active layer T4aof the fourth transistor T4, an active layer T5aof the fifth transistor T5, and an active layer T7aof the seventh transistor T7. Parts shown by small dotted boxes in the figure respectively are the channel regions of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5and the seventh transistor T7, for example, these parts are respectively at a position overlapping with a gate electrode layer. The active layers of the above transistors are connected into an integrated structure.

For example, the material of the first semiconductor layer PL1includes polysilicon.

For example, as illustrated inFIG.5BandFIG.6A, the display substrate1further includes a first metal layer GAT1(a first gate electrode layer) and a second metal layer GAT2(a second gate electrode layer).FIG.5Bis a schematic layout view of the first metal layer GAT1, andFIG.6Ais a schematic layout view of the second metal layer GAT2.

FIG.4Aillustrates a schematic cross-sectional view of a partial structure of the transistor T7. As illustrated inFIG.4A, the first insulating layer142is located on the base substrate10, the second insulating layer143is located on the side of the first insulating layer142away from the base substrate10, and the first semiconductor layer PL1is located between the first insulating layer142and the second insulating layer143. The third insulating layer144is located on the side of the second insulating layer143away from the base substrate10, the first metal layer GAT1is located between the first insulating layer142and the second insulating layer143, and the second metal layer GAT2is located between the second insulating layer143and the third insulating layer144.

For example, the material of the first semiconductor layer PL1includes polysilicon or an oxide semiconductor (e.g., indium gallium zinc oxide).

For example, the base substrate10is a glass plate, a quartz plate, a metal plate, a resin-based plate, or the like. For example, the material of the base substrate includes an organic material, for example, the organic material is a resin material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, polyethylene naphthalate, and the like. For example, the base substrate10is a flexible substrate or a non-flexible substrate, which is not limited in the embodiments of the present disclosure.

For example, materials of one or more of the first insulating layer142, the second insulating layer143and the third insulating layer144include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, and the like. The materials of the first insulating layer142, the second insulating layer143and the third insulating layer144are the same or different.

For example, the materials of the first metal layer GAT1and the second metal layer GAT2include metal materials or alloy materials, such as a metal single-layer or multi-layer structure formed by molybdenum, aluminum and titanium, for example, the multi-layer structure is a structure in which multiple metal layers are stacked (such as three-layer metal stack of titanium, aluminum and titanium (Ti/Al/Ti)).

For example, in some embodiments, as illustrated inFIG.5BandFIG.5C, the first metal layer GAT1includes the gate electrode T1gof the first transistor T1, the gate electrode T2gof the second transistor T2, the gate electrode T4gof the fourth transistor T4, the gate electrode T5gof the fifth transistor T5and the gate electrode T7gof the seventh transistor T7, which are respectively illustrated in the dotted boxes inFIG.5C. The position of the gate electrode of the transistor is the position where the first metal layer GAT1overlaps with the first semiconductor layer PL1. That is, the gate electrode of the transistor blocks the channel region of the transistor.

For example, as illustrated inFIG.5C, the first metal layer GAT1further includes the first capacitor electrode Cb of the storage capacitor Cst. For example, the display substrate1adopts a self-alignment process, and uses the first metal layer GAT1as a mask to perform conductive treatment (e.g., doping treatment) on the first semiconductor layer PL1, so that the part of the first semiconductor layer PL1that is not covered by the first metal layer GAT1is conductive, thus the part of the active layer of each transistor located on both sides of the channel region is conductive to form the first electrode and the second electrode of the transistor, respectively.

For example, in some embodiments, the first reset signal line RL1illustrated inFIG.2Ais located in the first metal layer GAT1, and the second reset signal line RL2is located in the second metal layer GAT2.

FIG.7Ais a schematic layout view of a second semiconductor layer of the display substrate provided by at least one embodiment of the present disclosure.FIG.7Bis a schematic layout view obtained by stacking the layers ofFIG.5A,FIG.5B,FIG.6AandFIG.7A.FIG.8Ais a schematic layout view of a third metal layer of the display substrate provided by at least one embodiment of the present disclosure.FIG.8Bis a schematic layout view obtained by stacking the layers ofFIG.5A,FIG.5B,FIG.6A,FIG.7AandFIG.8A.

For example, in some embodiments, as illustrated inFIG.8A, the display substrate1further includes a third metal layer GAT3. As illustrated inFIG.4A, the third metal layer GAT3is located on the side of the third insulating layer144away from the base substrate10.

For example, in some embodiments, the first electrode plate and the second electrode plate of the storage capacitor are respectively located in two of the first metal layer, the second metal layer and the third metal layer. For example, the first reset signal line is located in the second metal layer, and the second reset signal line is located in the third metal layer; or, the first reset signal line is located in the first metal layer, and the second reset signal line is located in the third metal layer; or, the first reset signal line is located in the first metal layer, and the second reset signal line is located in the second metal layer. Thereby, the above components are flexibly arranged according to the wiring space of the display substrate.

The embodiments of the present disclosure are described by taking an example in which the first electrode plate of the storage capacitor is located in the first metal layer, the second electrode plate is located in the second metal layer, the first reset signal line is located in the second metal layer, and the second reset signal line is located in the third metal layer, but the embodiments of the present disclosure are not limited thereto.

For example, as illustrated inFIG.5B, the first metal layer GAT1includes the first electrode plate Cb of the storage capacitor Cst.

For example, as illustrated inFIG.6A, the second metal layer GAT2includes the first reset signal line RL1. One first reset signal line RL1extending along the first direction Y is provided in each row of pixel driving circuits105.FIG.5Billustrates the first reset signal line RL1located in the pixel driving circuits105in the (M−1)th row and the first reset signal line RL1located in the pixel driving circuits105in the (M)th row.

For example, as illustrated inFIG.8A, the third metal layer GAT3includes the second reset signal line RL2. One second reset signal line RL2extending along the first direction Y is provided in each row of the pixel driving circuits105.FIG.8Aillustrates the second reset signal line RL2located in the pixel driving circuits105in the (M−1)th row and the second reset signal line RL2located in the pixel driving circuits105in the (M)th row. As illustrated inFIG.8A, the orthographic projections of the first reset signal line RL1and the second reset signal line RL2, which are located in the same row of pixel driving circuits105, on the base substrate10at least partially overlap with each other to reduce wiring space.

FIG.4Bis a schematic cross-sectional view along a section line A2-B2inFIG.2provided by at least one embodiment of the present disclosure, and the section line A2-B2passes through the sixth transistor T5inFIG.2.FIG.4Cis a schematic cross-sectional view along a section line A3-B3inFIG.2provided by at least one embodiment of the present disclosure, and the section line A3-B3passes through the first transistor T1inFIG.2.

For example, in some embodiments, as illustrated inFIG.4A,FIG.4BandFIG.4C, the display substrate1further includes a fourth insulating layer147(a second interlayer insulating layer), and the fourth insulating layer147is located on the side of the third insulating layer144away from the base substrate10.

For example, in some embodiments, as illustrated inFIG.14A, the display substrate1further includes a fourth metal layer SD2. The fourth metal layer SD2is located on the side of the fourth insulating layer147away from the base substrate10. The first power supply voltage line VDD1is located in the fourth metal layer SD2. It should be noted that the first power supply voltage line VDD1may be provided in other metal layers according to the needs of the wiring design of the display substrate, and the embodiments of the present disclosure are not limited to this.

For example, as illustrated inFIG.7A, the display substrate1further includes a second semiconductor layer PL2. A portion of the second semiconductor layer PL2where the orthographic projection of the second semiconductor layer PL2on the base substrate does not overlap with the orthographic projections of the second metal layer (as illustrated inFIG.6A) and the third metal layer (as illustrated inFIG.8A) on the base substrate10is conductive to form the first electrode T3sand the second electrode T3dof the third transistor T3, and the first electrode T6sand the second electrode T6dof the sixth transistor T6.

For example, the material of the second semiconductor layer PL2includes an oxide semiconductor material (e.g., indium gallium zinc oxide).

For example, as illustrated inFIG.5C, a portion of the first semiconductor layer PL1where the orthographic projection of the first semiconductor layer PL1on the base substrate10does not overlap with the orthographic projection of the first metal layer GAT1on the base substrate10is conductive to form the first electrode TIs and the second electrode T1dof the first transistor T1, the first electrode T2sand the second electrode T2dof the second transistor T2, the first electrode T4sand the second electrode T4dof the fourth transistor T4, the first electrode T5sand the second electrode T5dof the fifth transistor T5, and the first electrode T7sand the second electrode T7dof the seventh transistor T7.

For example, as illustrated inFIG.4BandFIG.4C, the display substrate1further includes a fifth insulating layer146(a third gate insulating layer). The second semiconductor layer PL2is located between the third insulating layer144and the third metal layer GAT3, and the fifth insulating layer146is located between the second semiconductor layer PL2and the third metal layer GAT3.

For example, as illustrated inFIG.6A, the second metal layer GAT2further includes the second electrode plate Cb of the storage capacitor Cst, a first gate electrode T3g1of the third transistor T3and a first gate electrode T6g1of the sixth transistor T6. As illustrated inFIG.7B, a portion of the second metal layer GAT2overlapping with the second semiconductor layer PL2constitutes the first gate electrode T3g1of the third transistor T3and the first gate electrode T6g1of the sixth transistor T6.

For example, as illustrated inFIG.7AandFIG.7B, the second semiconductor layer PL2includes an active layer T3aof the third transistor T3and an active layer T6aof the sixth transistor T6. A portion of the second semiconductor layer PL2overlapping the second metal layer GAT2or the third metal layer GAT3constitutes the active layer T3aof the third transistor T3and the active layer T6aof the sixth transistor T6.

For example, as illustrated inFIG.8AandFIG.8B, the third metal layer GAT3includes a second gate electrode T3g2of the third transistor T3and a second gate electrode T6g2of the sixth transistor T6. InFIG.8B, a portion of the third metal layer GAT3overlapping the second semiconductor layer PL2constitutes the second gate electrode T3g2of the third transistor T3and the second gate electrode T6g2of the sixth transistor T6.

For example, as illustrated inFIG.7A,FIG.7BandFIG.8B, the third transistor T3includes two gate electrodes. The first gate electrode T3g1of the third transistor T3is located on the side of the second semiconductor layer PL2close to the base substrate10, and the second gate electrode T3g2of the third transistor T3is located on the side of the second semiconductor layer PL2away from the base substrate10. The sixth transistor T6includes two gate electrodes. The first gate electrode T6g1of the sixth transistor T6is located on the side of the second semiconductor layer PL2close to the base substrate10, and the second gate electrode T6g2of the sixth transistor T6is located on the side of the second semiconductor layer PL2away from the base substrate10. The third transistor T3and the sixth transistor T6are transistors of TLPO type, so that they have better anti-leakage performance. For example, the third transistor T3is implemented as a dual gate structure, so as to improve the switching capability of the third transistor T3and prevent leakage current from occurring in an off state of the third transistor T3. For example, the sixth transistor T6is implemented as a dual gate structure, so as to improve the switching capability of the sixth transistor T6and prevent leakage current from occurring in an off state of the sixth transistor T6. The dual gate structure is adopted to improve the gate control capability of the third transistor T3and the sixth transistor T6, which is helpful to reduce the leakage current of the transistors, so as to maintain the voltage of N1node and improve the display uniformity of the display substrate in the light-emitting phase.

For example, in some embodiments, as illustrated inFIG.6BandFIG.8A, the orthographic projection of the first gate electrode T3g1of the third transistor T3on the base substrate at least partially overlaps with the orthographic projection of the second gate electrode T3g2of the third transistor T3on the base substrate, so as to reduce the wiring space of the display substrate1. The orthographic projection of the first gate electrode T6g1of the sixth transistor T6on the base substrate at least partially overlaps with the orthographic projection of the second gate electrode T6g2of the sixth transistor T6on the base substrate, so as to reduce the wiring space of the display substrate1.

For example, in some embodiments, as illustrated inFIG.14A, the bent portion VDD10of the first power supply voltage line VDD1includes a first portion VDD11and a second portion VDD12respectively extending along the second direction X, and a third portion VDD13extending along the first direction Y, the third portion VDD13connects the first portion VDD11and the second portion VDD12. For example, the first power supply voltage line VDD1is like an “S-shaped” bent line.

For example, in some embodiments, as illustrated inFIG.2andFIG.4B, the orthographic projection of the first portion VDD11on the base substrate10overlaps with the orthographic projections of the first gate electrode T3g1of the third transistor T3, the second gate electrode T3g2of the third transistor T3, the first gate electrode T6g1of the sixth transistor T6and the second gate electrode T6g2of the sixth transistor T6, so that the third transistor T3and the sixth transistor T6are shielded by the first power supply voltage line VDD to prevent the generation of leakage current.

FIG.9Ais a schematic layout view of via holes in at least one insulating layer of the display substrate provided by at least one embodiment of the present disclosure.FIG.9Bis a schematic layout view obtained by stacking the layers ofFIG.5A,FIG.5B,FIG.6A,FIG.7A,FIG.8AandFIG.9A.FIG.10Ais a schematic layout view of via holes in at least another insulating layer of the display substrate provided by at least one embodiment of the present disclosure.FIG.10Bis a schematic layout view obtained by stacking the layers ofFIG.5A,FIG.5B,FIG.6A,FIG.7A,FIG.8A,FIG.9AandFIG.10A.FIG.11Ais a schematic layout view of a fifth metal layer of the display substrate provided by at least one embodiment of the present disclosure.FIG.11Bis a schematic layout view obtained by stacking the layers ofFIG.5A,FIG.5B,FIG.6A,FIG.7A,FIG.8A,FIG.9A,FIG.10AandFIG.11A.FIG.12Ais a schematic layout view of via holes in at least still another insulating layer of the display substrate provided by at least one embodiment of the present disclosure.FIG.12Bis a schematic layout view obtained by stacking the layers ofFIG.5A,FIG.5B,FIG.6A,FIG.7A,FIG.8A,FIG.9A,FIG.10A,FIG.11AandFIG.12A.FIG.13Ais a schematic layout view of via holes in at least still another insulating layer of the display substrate provided by at least one embodiment of the present disclosure.FIG.13Bis a schematic layout view obtained by stacking the layers ofFIG.5A,FIG.5B,FIG.6A,FIG.7A,FIG.8A,FIG.9A,FIG.10A,FIG.11A,FIG.12AandFIG.13A.FIG.14Ais a schematic layout view of a fourth metal layer of the display substrate provided by at least one embodiment of the present disclosure.FIG.14Bis a schematic layout view of via holes in at least still another insulating layer of the display substrate provided by at least one embodiment of the present disclosure.FIG.14Cis a schematic layout view obtained by stacking the layers ofFIG.5A,FIG.5B,FIG.6A,FIG.7A,FIG.8A,FIG.9A,FIG.10A,FIG.11A,FIG.12A,FIG.13A,FIG.14AandFIG.14B.

For example, as illustrated inFIG.4BandFIG.4C, the display substrate further includes a first buffer layer141and a second buffer layer145. The first buffer layer141is provided on the side of the first insulating layer142close to the base substrate10. The second buffer layer145is provided between the second semiconductor layer PL2and the third insulating layer144. The first buffer layer141serves as a transition layer, which not only prevents harmful substances in the base substrate10from invading the interior of the display substrate, but also increases the adhesion of the layers in the display substrate1on the base substrate10. The second buffer layer145prevents harmful substances from invading the second semiconductor layer PL2.

For example, in some embodiments, as illustrated inFIG.2andFIG.14A, the second portion VDD12is electrically connected to the first electrode T4sof the fourth transistor T4(as illustrated inFIG.5C).

For example, as illustrated inFIG.11A, the display substrate1further includes a fifth metal layer SD1. For example, as illustrated inFIG.4B, the fifth metal layer SD1is located between the fourth metal layer SD2and the third metal layer GAT3. For example, the fifth metal layer SD1includes a seventh connection electrode TS7. The orthographic projection of the lower end of the seventh connection electrode TS7on the base substrate10corresponds to the orthographic projection of the first electrode T4sof the fourth transistor T4on the base substrate10.

For example, as illustrated inFIG.4B, the display substrate1further includes a sixth insulating layer149. The sixth insulating layer149is located between the fourth metal layer SD2and the fifth metal layer SD1. For example, the display substrate1further includes a passivation layer148. For example, the passivation layer148is located between the sixth insulating layer149and the fifth metal layer SD1. The passivation layer148protects the first and second electrodes of the transistors of the pixel driving circuit105from being corroded by water vapor.

For example, the material of the passivation layer148includes organic insulating material or inorganic insulating material, for example, silicon nitride material, because of its high dielectric constant and good hydrophobic function, it can well protect the pixel driving circuit105from being corroded by water vapor.

For example, as illustrated inFIG.9AandFIG.9B, the seventh connection electrode TS7is connected to the first electrode T4sof the fourth transistor T4through a fourth via hole VH4. For example, the fourth via hole VH4penetrates through the first insulating layer142, the second insulating layer143, the third insulating layer144, the second buffer layer145, the fifth insulating layer146and the fourth insulating layer147.

For example, as illustrated inFIG.12A,FIG.12B,FIG.13AandFIG.13B, the second portion VDD12of the bent portion VDD10of the first power supply voltage VDD1is connected to the seventh connection electrode TS7through a fifteenth via VH15and an eighteenth via VH18to realize the connection between the first power supply voltage VDD1and the first electrode T4sof the fourth transistor T4. In this case, the voltage drop during the transmission of the electrical signal is reduced by providing the seventh connection electrode TS7. For example, the orthographic projection of the fifteenth via hole VH15on the base substrate10overlaps with the orthographic projection of the eighteenth via hole VH18on the base substrate10. The fifteenth via hole VH15penetrates the passivation layer148, and the eighteenth via hole VH18penetrates the sixth insulating layer149.

For example, in some embodiments, as illustrated inFIG.2andFIG.14A, the orthographic projection of the first portion VDD11on the base substrate10and the orthographic projection of the first gate electrode T3g1of the third transistor T3on the base substrate include a first overlapping region (a lower half of the first portion VDD11in the figure), and the orthographic projection of the first portion VD11on the base substrate10and the orthographic projection of the first gate electrode T6g1of the sixth transistor T6on the base substrate10include a second overlapping region (an upper half of the first portion VDD11in the figure). A centerline X12of the first overlapping region extending along the second direction X does not coincide with a centerline X11of the second overlapping region extending along the second direction X. Thus, the first portion VDD11shields the first gate electrode T3g1of the third transistor T3and the first gate electrode T6g1of the sixth transistor T6.

For example, in some embodiments, as illustrated inFIG.2andFIG.14A, the centerline X12of the region (the lower half of the first portion VDD11in the figure), where the orthographic projection of the first portion VDD11on the base substrate10overlaps with the orthographic projections of the first gate electrode T3g1and the second gate electrode T3g2of the third transistor T3on the base substrate, along the second direction X does not coincide with the centerline X11of the region (the upper half of the first portion VDD11in the figure), where the orthographic projection of the first portion VDD11on the base substrate10overlaps with the orthographic projections of the first gate electrode T6g1and the second gate electrode T6g2of the sixth transistor T6on the base substrate, along the second direction X. In this case, the first portion VDD11does not extend straightly along the second direction X. Thus, the first portion VDD11shields the first gate electrode T3g1and the second gate electrode T3g2of the third transistor T3and the first gate electrode T6g1and the second gate electrode T6g2of the sixth transistor T6.

For example, in some embodiments, as illustrated inFIG.14A, the line width W1of the first portion VDD11is larger than both the line width W3of the second portion VDD12and the line width W2of the third portion VDD13. Accordingly, the width of a portion of the first power supply voltage line VDD1that does not serve as a shielding electrode is appropriately reduced to reduce the wiring space.

For example, in some embodiments, as illustrated inFIG.14A, the display substrate1further includes a plurality of data lines11extending along the second direction X, and each data line11is electrically connected to pixel driving circuits105of a plurality of sub-pixels located in a same column and configured to provide a data signal. A distance Y11(corresponding to the upper part of the first portion VDD11) or Y12(corresponding to the lower part of the first portion VDD11) between the orthographic projection of the first portion VDD11of the bent portion VDD10of the first power supply voltage line VDD1on the base substrate10and the orthographic projection of the data line11(the first portion VDD11and the data line11are electrically connected to the same pixel driving circuit105) on the base substrate10along the first direction Y is greater than a distance Y13between the orthographic projection of the second portion VDD12on the base substrate10and the orthographic projection of the data line11on the base substrate10along the first direction Y, thereby reducing the wiring space of the first power supply voltage line VDD1.

For example, in some embodiments, as illustrated inFIG.11AandFIG.11B, the pixel driving circuit105further includes a first connection electrode TS1located in the fifth metal layer SD1. The first connection electrode TS1is bent and extended, and is substantially in an “L” shape. The first connection electrode TS1connects the first reset signal line RL1electrically connected to the pixel driving circuits105of the sub-pixels in the (M)th row to the pixel driving circuits105of the sub-pixels in the (M)th row.

For example, in some embodiments, as illustrated inFIG.11AandFIG.11B, at least a portion of the first connection electrode TS1extends along the first direction Y. For example, the first connection electrode TS1includes a portion extending along the second direction X and a portion extending along the first direction Y, and the two portions are connected to form a substantially “L” shape.

For example, in some embodiments, as illustrated inFIG.4B,FIG.9A,FIG.9B,FIG.11A, andFIG.11B, a first end of the first connection electrode TS1(e.g., an upper end of the first connection electrode TS1inFIG.11A) is connected to the first reset signal line RL1through a first via hole VH1(as illustrated inFIG.9AandFIG.9B). The first via hole VH1is a via hole penetrating the third insulating layer144, the fourth insulating layer147, the second buffer layer145and the fifth insulating layer146. For example, in some embodiments, as illustrated inFIG.4B,FIG.10A,FIG.10B,FIG.11A, andFIG.11B, a second end of the first connection electrode TS1(e.g., a lower end of the first connection electrode TS1inFIG.11A) is connected to the first electrode T6s(as illustrated inFIG.7A) of the sixth transistor T6of the pixel driving circuit105of the sub-pixel in (M)th row through a thirteenth via hole VH13(as illustrated inFIG.10AandFIG.10B). For example, the thirteenth via hole VH13is a via hole penetrating the fourth insulating layer147and the fifth insulating layer146.

For example, in some embodiments, as illustrated inFIG.2,FIG.4B,FIG.6AandFIG.6B, the first reset signal line RL1includes a portion PP1protruding toward the first connection electrode TS1. The protruding portion PP1of the first reset signal line RL1is connected to the first connection electrode TS1through the first via hole VH1. The first reset signal line RL1is electrically connected to the first electrodes T6s(as illustrated inFIG.7A) of the sixth transistors T6of the pixel driving circuits105of the sub-pixels in (M)th row through the first connection electrodes TS1. The first reset signal provided by the first reset signal line RL1is transmitted to the first electrodes T6sof the sixth transistors T6of the pixel driving circuits105of the sub-pixels in (M)th row through the protruding portions PP1of the first reset signal line RL1and the first connection electrodes TS1.

For example, in some embodiments, as illustrated inFIG.11AandFIG.11B, the pixel driving circuit105further includes a second connection electrode TS2located in the fifth metal layer SD1. The second connection electrode TS2extends along the second direction X.

For example, as illustrated inFIG.4A,FIG.10A,FIG.10B,FIG.11A, andFIG.11B, a first end of the second connection electrode TS2(e.g., an upper end of the second connection electrode TS2inFIG.11A) is connected to the second reset signal line RL2(located in the (M−1)th row) through a twelfth via hole VH12(as illustrated inFIG.10AandFIG.10B). For example, the twelfth via hole VH12is a via hole penetrating the fourth insulating layer147.

For example, as illustrated inFIG.4A,FIG.9A,FIG.9B,FIG.11A, andFIG.11B, a second end of the second connection electrode TS2(e.g., a lower end of the second connection electrode TS2inFIG.11A) is connected to the first electrode T7sof the seventh transistor T7of the pixel driving circuit105of the sub-pixel in the (M−1)th row through a second via hole VH2(as illustrated inFIG.9AandFIG.9B). For example, the second via hole VH2is a via hole penetrating the first insulating layer142, the second insulating layer143, the third insulating layer144, the fourth insulating layer147and the fifth insulating layer146.

For example, in some embodiments, as illustrated inFIG.6A,FIG.8AandFIG.8B, the display substrate1further includes a first reset control signal line RCL1extending along the first direction Y. The first reset control signal line RCL1is configured to provide the first reset control signal Rst1to the pixel driving circuits105of a plurality of sub-pixels in a row corresponding to the first reset control signal line RCL1. The first reset control signal line RCL1includes a first sub-line RCL11located in the second metal layer GAT2(as illustrated inFIG.6A) and a second sub-line RCL12located in the third metal layer GAT3(as illustrated inFIG.8A). For example, the first reset control signal line RCL1is a double-layered line, and both the first sub-line RCL11and the second sub-line RCL12transmit the first reset control signal Rst1. The orthographic projection of the first sub-line RCL11on the base substrate10at least partially overlaps with the orthographic projection of the second sub-line RCL12on the base substrate10. The width of a portion of the first sub-line RCL11overlapping with the second semiconductor layer PL2is increased, and the portion also constitutes the first gate electrode T6g1of the sixth transistor T6. The width of a portion of the second sub-line RCL12overlapping with the second semiconductor layer PL2is increased, and the portion also constitutes the second gate electrode T6g2of the sixth transistor T6. That is, the portion of the first sub-line RCL11overlapping with the second semiconductor layer PL2in the direction perpendicular to the base substrate10serves as the first gate electrode T6g1of the sixth transistor T6, and the portion of the second sub-line RCL12overlapping with the second semiconductor layer PL2in the direction perpendicular to the base substrate10serves as the second gate electrode T6g2of the sixth transistor T6.

For example, as illustrated inFIG.2,FIG.5BandFIG.5C, the display substrate1further includes a second reset control signal line RCL2located in the first metal layer GAT1. The second reset control signal line RCL2extends along the first direction Y, and is configured to provide the second reset control signal Rst2to the pixel driving circuits105of a plurality of sub-pixels in a row corresponding to the second reset control signal line RCL2. A portion of the second reset control signal line RCL2overlapping with the first semiconductor layer PL1in the direction perpendicular to the base substrate10serves as the gate electrode T7gof the seventh transistor T7to reduce wiring space.

For example, in other embodiments, as illustrated inFIG.2,FIG.5B,FIG.5C,FIG.6AandFIG.8A, in the region where one sub-pixel of the sub-pixels in the (M−1)th row is located (for example, the region where the pixel driving circuit of the one sub-pixel is located, which is illustrated by a dotted box in the figure), the area of an overlapping region of the orthographic projection of the second reset signal line RL2, that is electrically connected to the pixel driving circuits of the sub-pixels in the (M−1)th row, on the base substrate10and the orthographic projection of the second reset control signal line RCL2, that is electrically connected to the pixel driving circuits of the sub-pixels in the (M−1)th row, on the base substrate10is less than 50% of the area of the orthographic projection of the second reset signal line RL2on the base substrate10. Therefore, the overlapping portion of the second reset signal line RL2and the second reset control signal line RCL2is small, and the load transmitted on the second reset signal line RL2is less affected by other electrical signals. For example, in the region where one sub-pixel of the sub-pixels in the (M−1)th row is located (for example, the region where the pixel driving circuit of the one sub-pixel is located, which is illustrated by a dotted box in the figure), the area of an overlapping region of the orthographic projection of the first reset signal line RL1, that is electrically connected to the pixel driving circuits of the sub-pixels in the (M)th row, on the base substrate10and the orthographic projection of the second reset control signal line RCL2, that is electrically connected to the pixel driving circuits of the sub-pixels in the (M−1)th row, on the base substrate10is less than 50% of the area of the orthographic projection of the first reset signal line RL1on the base substrate10. Therefore, the overlapping portion of the first reset signal line RL1and the second reset control signal line RCL2is small, and the load transmitted on the first reset signal line RL1is less affected by other electrical signals.

For example, as illustrated inFIG.2,FIG.5BandFIG.5C, the display substrate1further includes a plurality of first scanning signal lines GL1located in the first metal layer GAT1. Each of the first scanning signal lines GL1extends along the first direction Y, and is configured to provide the first scanning signal Ga1to pixel driving circuits105of a plurality of sub-pixels in a row corresponding thereto. InFIG.5C, a portion of the first scanning signal line GL1overlapping with the first semiconductor layer PL1in the direction perpendicular to the base substrate10serves as the gate electrode T2gof the second transistor T2to reduce wiring space.

For example, as illustrated inFIG.2,FIG.6A,FIG.6B,FIG.7AandFIG.7B, the display substrate1further includes a plurality of second scanning signal lines GL2. Each of the second scanning signal lines GL2extends along the first direction Y, and is configured to provide the second scanning signal Ga2to pixel driving circuits105of a plurality of sub-pixels in a row corresponding thereto. Along the second direction X, in each pixel driving circuit105, for example, in the pixel driving circuit105located at the upper left inFIG.8B, the orthographic projection of the second scanning signal line GL2on the base substrate10is located between the orthographic projection of the storage capacitor Cst on the base substrate10and the orthographic projection of the first scanning signal line GL1on the base substrate10. That is, along the second direction X, the second scanning signal line GL2is located below the first scanning signal line GL1. For example, the second scanning signal line GL2includes a third sub-line GL21located in the second metal layer GAT2(as illustrated inFIG.6A) and a fourth sub-line GL22located in the third metal layer GAT3(as illustrated inFIG.8A). The orthographic projection of the third sub-line GL21on the base substrate10at least partially overlaps with the orthographic projection of the fourth sub-line GL22on the base substrate10. For example, the second scanning signal line GL2is a double-layered line, and both the third sub-line GL21and the fourth sub-line GL22are used to transmit the second scanning signal Ga2. For example, a portion of the third sub-line GL21overlapping with the second semiconductor layer PL2in the direction perpendicular to the base substrate10(the line width of this portion increases) serves as the first gate electrode T3g1of the third transistor T3, and a portion of the fourth sub-line GL22overlapping with the second semiconductor layer PL2in the direction perpendicular to the base substrate10(the line width of this portion increases) serves as the second gate electrode T3g2of the third transistor T3. Thereby, the wiring space of the display substrate1is reduced.

For example, in some embodiments, as illustrated inFIG.5A,FIG.5B,FIG.6AandFIG.6B, the display substrate1further includes a first convex portion GL11(as illustrated inFIG.5A) located in the first metal layer GAT1and a first electrode portion GA1(as illustrated inFIG.6A) located in the second metal layer. The first convex portion GL11is connected to the first scanning signal line GL1, and the first convex portion GL11and the first scanning signal line GL1are integral with each other. That is, the first convex portion GL11is a widened portion of the first scanning signal line GL1in the second direction X. The orthographic projection of the first electrode portion GAT1on the base substrate10is located between the data line11and the first power supply voltage line VDD1along the first direction Y, and is located between the first reset control signal line RCL1and the second scanning signal line GL2along the second direction X. For example, the orthographic projection of the first electrode portion GA1on the base substrate10at least partially overlaps with the orthographic projections of the first convex portion GL11and the first scanning signal line GL1on the base substrate10, so that the second insulating layer143is provided between the first electrode portion GA1and the first convex portion GL11as well as the first scanning signal line GL1to form an auxiliary capacitor. Thus, the first scanning signal Ga1transmitted on the first scanning signal line GL1can be prevented from jumping.

For example, as illustrated inFIG.4C,FIG.11AandFIG.11B, the pixel driving circuit105further includes a third connection electrode TS3located in the fifth metal layer SD1. The third connection electrode TS3is substantially “L” shaped. For example, the orthographic projection of the third connection electrode TS3on the base substrate10partially overlaps with the orthographic projections of the first scanning signal line GL1, the second scanning signal line GL2and the second semiconductor layer PL2on the base substrate10to form an auxiliary capacitor, thereby preventing the electrical signals transmitted on the first scanning signal line GL1and the second scanning signal line GL2from jumping. For example, a portion of the third connection electrode TS3extending in the second direction X overlaps with the second scanning signal line GL2, and a portion of the third connection electrode TS3extending in the first direction Y overlaps with the first scanning signal line GL1and partially overlaps with the second semiconductor layer PL2.

For example, as illustrated inFIG.4C,FIG.6A,FIG.11AandFIG.11B, the second electrode plate Ca of the storage capacitor Cst includes a first opening K1. The first opening K1is configured to expose the first electrode plate Cb of the storage capacitor Cst (as illustrated inFIG.6A). The third connection electrode TS3includes a first sub-connection electrode T31extending in the second direction X and a second sub-connection electrode T32extending in the first direction Y (as illustrated inFIG.11A). A first end (a lower end in the figure) of the first sub-connection electrode T31passes through the first opening K1and is connected to the first electrode plate Cb through a seventh via hole VH7(as illustrated inFIG.9AandFIG.9B). The seventh via hole VH7is a via hole penetrating the second insulating layer143, the third insulating layer144, the second buffer layer145, the fourth insulating layer147and the fifth insulating layer146. A second end (e.g., an upper end) of the first sub-connection electrode T31is connected to the first electrode portion GA1through a ninth via hole VH9. For example, the ninth via hole VH9is a via hole penetrating the third insulating layer144, the second buffer layer145, the fourth insulating layer147and the fifth insulating layer146. For example, the second end of the first sub-connection electrode T31is further connected to the second sub-connection electrode T32, and an end of the second sub-connection electrode T32away from the first connection electrode T31(e.g., an end on the right side ofFIG.11A) is connected to the second electrode T6dof the sixth transistor T6and the first electrode T3sof the third transistor T3(i.e., connected to the second semiconductor layer PL2) through a tenth via hole VH10. For example, the tenth via hole VH10is a via hole penetrating the fourth insulating layer147and the fifth insulating layer146.

For example, in some embodiments, as illustrated inFIG.5BandFIG.5C, the first metal layer GAT1further includes a plurality of light-emitting control lines EML extending along the first direction Y, and each light-emitting control line EML is configured to provide the light-emitting control signal (the first light-emitting control signal EM1or the second light-emitting control signal EM2) to pixel driving circuits105of a plurality of sub-pixels in a row corresponding thereto. A portion of the light-emitting control line EML overlapping with the first semiconductor layer PL1in the direction perpendicular to the base substrate10serves as the gate electrode T4gof the fourth transistor T4and the gate electrode T5gof the fifth transistor T5. Thereby, the wiring space of the display substrate1is reduced.

For example, in some embodiments, as illustrated inFIG.2andFIG.14A, the data line11is located in the fourth metal layer SD2. As illustrated inFIG.11A, the pixel driving circuit105further includes a fourth connection electrode TS4located in the fifth metal layer SD1. The fourth connection electrode TS4is connected to the first electrode T2sof the second transistor T2through an eighth via hole VH8(as illustrated inFIG.9AandFIG.9B). For example, the eighth via hole VH8is a via hole penetrating the first insulating layer142, the second insulating layer143, the third insulating layer144, the second buffer layer145, the fourth insulating layer147and the fifth insulating layer146. The fourth connection electrode TS4is further connected to the data line11through a fourteenth via hole VH14(as illustrated inFIG.12AandFIG.12B) and a seventeenth via hole VH17(as illustrated inFIG.13AandFIG.13B) to receive the data signal. For example, the orthographic projection of the fourteenth via hole VH14on the base substrate10overlaps with the orthographic projection of the seventeenth via hole VH17on the base substrate10. For example, the fourteenth via hole VH14is a via hole penetrating the passivation layer148. For example, the seventeenth via hole VH17is a via hole penetrating the sixth insulating layer149.

For example, as illustrated inFIG.9A,FIG.9BandFIG.11A, the other end (e.g., an upper end) of the seventh connection electrode TS7is connected to the second electrode plate Ca of the storage capacitor Cst through a fifth via hole VH5illustrated inFIG.9A. For example, the fifth via hole VH5is a via hole penetrating the third insulating layer144, the second buffer layer145, the fifth insulating layer146and the fourth insulating layer147.

For example, as illustrated inFIG.9A,FIG.9BandFIG.11A, the fifth metal layer SD1further includes a fifth connection electrode TS5. The fifth connection electrode TS5extends along the second direction X. One end (e.g., a lower end) of the fifth connection electrode TS5is connected to the second electrode T1dof the first transistor T1through a sixth via hole VH6illustrated inFIG.9A. For example, the sixth via hole VH6is a via hole penetrating the first insulating layer142, the second insulating layer143, the third insulating layer144, the second buffer layer145, the fifth insulating layer146and the fourth insulating layer147. For example, the other end (e.g., an upper end) of the fifth connection electrode TS5is connected to the second electrode T2dof the second transistor T2through an eleventh via hole VH11illustrated inFIG.10A. For example, the eleventh via hole VH11is a via hole penetrating the fifth insulating layer146and the fourth insulating layer147.

For example, the fifth connection electrode TS5is not parallel to the second direction X, for example, intersects the second direction X at a certain angle. For example, the intersection angle is less than or equal to 20°.

For example, as illustrated inFIG.14A, the fourth metal layer SD2further includes an eighth connection electrode TS8. For example, the eighth connection electrode TS8extends along the second direction X. The eighth connection electrode TS8is configured to connect the light-emitting element120and the pixel driving circuit105.

For example, the eighth connection electrode TS8is not parallel to the second direction X, for example, intersects the second direction X at a certain angle. For example, the intersection angle is less than or equal to 20°.

For example, as illustrated inFIG.9A,FIG.9BandFIG.11A, the fifth metal layer SD1further includes a sixth connection electrode TS6. The sixth connection electrode TS6extends along the second direction X. One end (e.g., a lower end) of the sixth connection electrode TS6is connected to the first electrode T5sof the fifth transistor T5through a third via hole VH3illustrated inFIG.9A. For example, the third via hole VH3is a via hole penetrating the first insulating layer142, the second insulating layer143, the third insulating layer144, the second buffer layer145, the fifth insulating layer146and the fourth insulating layer147. For example, one end (e.g., a lower end) of the sixth connection electrode TS6is connected to an eighth connection electrode TS8located in the fourth metal layer through a sixteenth via hole VH16illustrated inFIG.12Aand a nineteenth via hole VH19illustrated inFIG.13A. For example, the sixteenth via hole VH16is a via hole penetrating the passivation layer148. For example, the nineteenth via hole VH19is a via hole penetrating the sixth insulating layer149.

For example, as illustrated inFIG.14B, the display substrate1further includes a seventh insulating layer150(e.g., a second planarization layer). The seventh insulating layer150is located on a side of the fourth metal layer SD2away from the base substrate10.

FIG.15Ais a schematic layout view of a pixel defining layer of the display substrate provided by at least one embodiment of the present disclosure.FIG.15Bis a schematic layout view obtained by stacking the layers ofFIG.5A,FIG.5B,FIG.6A,FIG.7A,FIG.8A,FIG.9A,FIG.10A,FIG.11A,FIG.12A,FIG.13A,FIG.14A,FIG.14BandFIG.15A.

For example, as illustrated inFIG.14B,FIG.14C,FIG.15AandFIG.15B, the eighth connection electrode TS8is connected to the first electrode134of the light-emitting element120through a twentieth via hole VH20in the seventh insulating layer150, for example, connected to the light-emitting element120a.

For example, the material of the first electrode134includes at least one transparent conductive oxide material, including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and the like. In addition, the first electrode134for example includes a metal having high reflectivity, such as silver (Ag), as a reflective layer.

For example, in the embodiments of the present disclosure, a schematic plan view of the pixel defining layer of the display substrate1, the second electrode135of the light-emitting element120, the encapsulation layer, and the like is not illustrated.

For example, as illustrated inFIG.15A, the light-emitting element120includes a red light-emitting element120a, a green light-emitting element120b, a blue light-emitting element120c, and a green light-emitting element120d. The above four kinds of light-emitting elements constitute a pixel unit.

For example, the materials of the third metal layer GAT3, the fourth metal layer SD2and the fifth metal layer SD1include metal materials or alloy materials, such as a metal single-layer or multi-layer structure formed by molybdenum, aluminum and titanium, for example, the multi-layer structure is a structure in which multiple metal layers are stacked (such as three-layer metal stack of titanium, aluminum and titanium (Ti/A1/Ti)).

For example, the materials of one or more of the fourth insulating layer147and the fifth insulating layer146include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and the like.

For example, the materials of the sixth insulating layer149and the seventh insulating layer150include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and the like, or include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, phenolic resin, and the like, which are not limited by the embodiments of the present disclosure.

It should be noted that, in the embodiments of the present disclosure, the size range of the first via hole VH1to the ninth via hole VH9illustrated inFIG.9Ais about 2-4 micrometers, for example, about 3 micrometers. The sizes of the first via hole VH1to the ninth via hole VH9are selected by the display substrate1in the actual manufacturing process.

FIG.16Ais another schematic layout view of some layers of the display substrate provided by at least one embodiment of the present disclosure.FIG.16Bis another schematic layout view of one metal layer of the display substrate provided by at least one embodiment of the present disclosure.FIG.16Cis another schematic layout view of some layers of the display substrate provided by at least one embodiment of the present disclosure.

For example, in some embodiments, as illustrated inFIG.16A, the sub-pixel of the display substrate includes a pixel driving circuit105a. For example, the pixel driving circuit105ais taken as an example of a 7T1C pixel driving circuit for description. For example, the circuit principle of the pixel driving circuit105ais referred toFIG.3AandFIG.3Band is not described in detail here. The difference between the pixel driving circuit105aand the pixel driving circuit105illustrated inFIG.2is that the pixel driving circuits105ain each row are connected to one reset signal line. For example, the reset signal line RL0in the middle position inFIG.16Ais connected to the seventh transistors T7of the pixel driving circuits105ain the (M−1)th row and the sixth transistors T6of the pixel driving circuits105ain the (M)th row. For example, the pixel driving circuit105further includes a first reset control signal line RCL10, a second reset control signal line RCL20, a first scanning signal line GL10, a second scanning signal line GL20, and an light-emitting control signal line EML0. In addition, for the detailed wiring structure of the pixel driving circuit105a, reference may be made to the wiring structure of the pixel driving circuit105, which will not be described in detail here.

For example, as illustrated inFIG.16B, a first power supply voltage line VDD1aand a data line11aelectrically connected to the pixel driving circuit105ahave different structures from the first power supply voltage line VDD1and the data line11illustrated inFIG.14A. The first power supply voltage line VDD1aincludes a first portion VDD1al, a second portion VDD1a2, a third portion VDD1a3, and a fourth portion VDD1a4.

For example, as illustrated inFIG.16BandFIG.16C, the first portion VDD1alextends along the second direction X, and the orthographic projection of the first portion VDD1alon the base substrate10overlaps with the sixth transistor T6(e.g., the gate electrode), so that the sixth transistor T6is shielded to prevent leakage current of the sixth transistor T6. The width of the second portion VDD1a2along the first direction Y is greater than the width of the first portion VDD1alalong the first direction Y. The orthographic projection of the second portion VDD1a2on the base substrate10at least overlaps with the orthographic projections of the third connection electrode TS3, the first scanning signal line GL10, the second electrode of the sixth transistor T6and the first electrode of the second transistor T2(a portion of the second semiconductor layer PL2) on the base substrate10to form an auxiliary capacitor, thereby preventing the electrical signal transmitted on the first scanning signal line GL10from jumping. The third portion VDD1a3crosses the second scanning signal line GL20, that is, the third portion VDD1a3intersects and overlaps with the second scanning signal line GL20. The width of the third portion VDD1a3along the first direction Y is smaller than the width of the second portion VDD1a2along the first direction Y. The first power supply voltage line VDD1ahas an opening K2, and the orthographic projection of the opening K2on the base substrate10partially overlaps with the second scanning signal line GL20, that is, the opening K2exposes the second scanning signal line GL20. The width of the fourth portion VDD1a4along the first direction Y is greater than the width of the third portion VDD1a3along the first direction Y. The orthographic projection of the fourth portion VDD1a4on the base substrate10partially overlaps with the second electrode plate of the storage capacitor to form an auxiliary capacitor, thereby reducing the jumping of electrical signals and improving the display effect of the display substrate.

For example, as illustrated inFIG.16BandFIG.16C, the data line11ais routed along the second direction X, and the data line11ais bent at a portion close to the fourth transistor T4to reduce the wiring space.

FIG.16Billustrates another wiring manner of the first power supply voltage line, in which the first portion VDD1al, the second portion VDD1a2, the third portion VDD1a3, and the fourth portion VDD1a4of the first power supply voltage line VDD1aform a bent line. The embodiments of the present disclosure are not limited to a specific bending manner or wiring manner of the first power supply voltage line.

At least one embodiment of the present disclosure further provides a display device.FIG.17is a schematic view of the display device provided by at least one embodiment of the present disclosure. As illustrated inFIG.17, the display device1000includes the display substrate1provided by any embodiment of the present disclosure, for example, the display substrate1illustrated inFIG.2.

It should be noted that the display device1000may be any product or component with display function, such as an OLED panel, an OLED TV, a QLED panel, a QLED TV, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, and a navigator. The display device1000may further include other components, such as a data driving circuit, a timing controller, etc., which are not limited in the embodiments of the present disclosure.

It should be noted that, for the sake of clarity and conciseness, the embodiments of the present disclosure do not provide all the constituent units of the display device. In order to realize the basic functions of the display device, those skilled in the art can provide or set other structures not illustrated according to specific needs, which are not limited by the embodiments of the present disclosure.

Regarding the technical effects of the display device1000provided by the embodiments described above, reference may be made to the technical effects of the display substrate1provided in the embodiments of the present disclosure, which will not be repeated here.

The following statements should be noted:

(1) The accompanying drawings involve only the structure(s) in connection with the embodiment(s) of the present disclosure, and other structure(s) can be referred to common design(s).

(2) In case of no conflict, features in one embodiment or in different embodiments can be combined to obtain new embodiments.

What have been described above are only specific implementations of the present disclosure, the protection scope of the present disclosure is not limited thereto. Any modifications or substitutions easily occur to those skilled in the art within the technical scope of the present disclosure should be within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.