Patent ID: 12237048

DETAILED DESCRIPTION

Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings.

As a memory device according to an example embodiment includes a clock repeater having intentional characteristic imbalance, a duty error of signals (clock, DQ, DQS, etc.) transmitted through a clock repeater path may be removed/corrected. In this case, the clock repeater may include at least two inverters that intentionally cause a characteristic imbalance between a P-channel metal oxide semiconductor (PMOS) transistor and an N-channel metal oxide semiconductor (NMOS) transistor. In this case, the directions of the imbalance in the driving capability of the at least two inverters are different from each other. By enabling the directions of the intentional characteristic imbalance to be different from each other, the directions (or tendency) of the process error may be opposite to each other. Therefore, the duty errors may cancel each other out inside of the clock repeater.

FIG.1is a diagram illustrating, by way of example, a memory system according to an example embodiment. Referring toFIG.1, a memory system10may include a memory device100(MEM) and a memory controller200(MCNTL).

The memory system10may be implemented to be included in a personal computer or a mobile electronic device. The mobile electronic device may be implemented, for example, as a Laptop Computer, a Mobile Phone, a Smartphone, a Tablet PC, a Personal Digital Assistant (PDA), an Enterprise Digital Assistant (EDA), a digital still camera, a digital video camera, a Portable Multimedia Player (PMP), a Personal Navigation Device or Portable Navigation Device (PND), a handheld game console, a Mobile Internet Device (MID), a wearable computer, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, or a drone.

The memory device100(MEM) may be implemented as a volatile memory device. The volatile memory device may be implemented as random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), or low power double data rate (LPDDR) DRAM. In another embodiment, the memory device100may be implemented as a non-volatile memory device. Illustratively, the memory device MD may be implemented as an Electrically erasable programmable read-only memory (EEPROM), flash memory, MRAM, STT-MRAM, ferroelectric RAM (FeRAM), phase change RAM (PRAM), resistive RAM (RRAM), nanotube RRAM, Polymer RAM (PoRAM), Nano Floating Gate Memory (NFGM), holographic memory, molecular electronic memory device, or an insulator resistance change memory.

The memory device100may include a clock buffer101, a memory cell array110(MCA), and a first error correction circuit180(ECC1).

The clock buffer101may be implemented to buffer a clock (CLK, WCK, etc.) received from the outside (e.g., from outside the memory device100). The clock buffer101may include sequential, serially connected clock repeaters. In this case, each of the clock repeaters may be implemented to have an intentional imbalance characteristic in order to remove a duty error. For example, the at least one clock repeater may include an inverter implemented with a PMOS transistor and an NMOS transistor having an imbalance characteristic. In an example embodiment, the clock repeaters may include at least one clock repeater pair including a first inverter implemented to have a characteristic that is imbalanced in a first direction and a second inverter implemented to have a characteristic that is imbalanced in a second direction. In this case, the second direction is different from the first direction.

The memory cell array110may include a plurality of memory cells connected to wordlines and bitlines.

The first error correction circuit ECC1may include first and second error correction units (also described as sub-circuits) that perform error correction in different ways according to a physical location (or address). When the occurrence location of a non-single bit error (NSB) inside of data is different for each fault according to a physical location inside the memory device100, the memory device100may be enabled to correct the error in the first error correction circuit ECC1of the On-die Error Correction Code (OD-ECC), or to generate mis-correction of OD-ECC in the correctable area in the second error correction circuit (ECC2, system ECC) of the controller200.

The memory controller200(MCNTL) may be implemented as an integrated circuit, a system on chip (SoC), an application processor (AP), a mobile AP, a chipset, or a set of chips. The memory controller200may include a random access memory (RAM), a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), or a modem. In an example embodiment, the memory controller200may perform a function of a modem and a function of an AP.

The memory controller200may be implemented to control the memory device100to read data stored in the memory device100or write data to the memory device100. The memory controller200may control a write operation or a read operation on the memory device100by providing a command CMD and an address ADDR to the memory device100in synchronization with the clock CLK. Also, the data DQ may be transmitted/received between the memory controller200and the memory device100in synchronization with the data transmission clock WCK.

Also, the memory controller200may include a second error correction circuit ECC2that corrects an error in the data DQ transmitted and received with the memory device100.

In a general memory device, by accumulating the duty error of the clock signal transmitted through the clock repeater path due to Process, Voltage, Temperature (PVT) fluctuations, the reliability of the clock is reduced.

On the other hand, the memory device100according to embodiments of the present inventive concept includes a clock repeater composed of inverters having characteristics that are imbalanced in different directions, thereby significantly reducing the duty error accumulated through the clock repeater path.

The memory system10according to an example embodiment includes the memory device100for removing a duty error with respect to a clock signal, and thus, the reliability of the clock signal may be improved, and overall system performance may be expected to improve.

FIG.2is a diagram illustrating a memory device100according to an example embodiment. Referring toFIG.2, the memory device100may include the clock buffer101, the memory cell array110, a row decoder120, a column decoder130, a sense amplifier circuit140, an address register150, a bank control logic152, a refresh counter154, a row address multiplexer156, a column address latch158, a control logic160, a repair control circuit (not shown), a timing control circuit (not shown), an input/output gating circuit170, an error correction circuit180, and an I/O buffer (190).

The clock buffer101may include a clock repeater path for receiving a clock signal and using it as an internal clock. In this case, the clock repeater path may include at least two inverters having different imbalance characteristics.

The memory cell array110may include first to eighth banks111to118. On the other hand, it should be understood that the number of banks of the memory cell array110is not limited thereto. Each of the first to eighth banks111to118may include a plurality of memory cells MCs connected between the wordlines WLs and the bitlines BLs. In this case, each of the plurality of memory cells may be implemented as a volatile memory cell or a non-volatile memory cell.

The row decoder120may include first to eighth bank row decoders121to128respectively connected to the first to eighth banks111to118.

The column decoder130may include first to eighth bank column decoders131to138connected to the first to eighth banks111to118, respectively.

The sense amplifier circuit140may include first to eighth bank sense amplifiers141to148respectively connected to the first to eighth banks111to118. On the other hand, the first to eighth banks (111to118) may comprise first to eighth bank row decoders121to128, first to eighth bank column decoders131to138, and first to eighth bank sense amplifiers141to148.

The address register150may receive an address (ADDR) having a Bank address (BANK_ADDR), a row address (ROW_ADDR) and a column address (COL_ADDR) from an external memory controller, and may store the address. The address register150may provide the received bank address BANK_ADDR to the bank control logic152, the received row address ROW_ADDR to the row address multiplexer156, and the received column address COL_ADDR to the column address latch158.

The bank control logic152may generate bank control signals in response to the bank address BANK_ADDR. A bank row decoder corresponding to the bank address BANK_ADDR among the first to eighth bank row decoders121to128may be activated in response to the bank control signals. A bank column decoder corresponding to the bank address BANK_ADDR among the first to eighth bank column decoders131to138may be activated in response to the bank control signals.

The row address multiplexer156may receive a row address ROW_ADDR from the address register150and a refresh row address REF_ADDR from the refresh counter154. The row address multiplexer156may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer156may be applied to the first to eighth bank row decoders121to128, respectively.

The bank row decoder activated by the bank control logic152among the first to eighth bank row decoders121to128may decode the row address RA output from the row address multiplexer156and may activate a wordline corresponding to the row address. For example, the activated bank row decoder may apply a wordline driving voltage to a wordline corresponding to a row address. Also, the activated bank row decoder may activate a wordline corresponding to the row address and simultaneously activate a redundancy wordline corresponding to the redundancy row address output from the repair control circuit.

The column address latch158may receive the column address COL_ADDR from the address register150and temporarily store the received column address COL_ADDR. Also, the column address latch158may gradually increase the received column address COL_ADDR in a burst mode. The column address latch158may apply the temporarily stored or gradually increased column address COL_ADDR to the first to eighth bank column decoders131to138, respectively.

The bank column decoder activated by the bank control logic152among the first to eighth bank column decoders131to138may activate the sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the input/output gating circuit170. Also, the activated bank column decoder may perform a column repair operation in response to the column repair signal CRP output from the repair control circuit.

The control logic160may be implemented to control the operation of the memory device100. For example, the control logic160may generate control signals so that the semiconductor memory device100performs a write operation or a read operation. The control logic160may include a command decoder161for decoding a command CMD received from the memory controller and a mode register set162for setting an operation mode of the memory device100. For example, the command decoder161may decode the write enable signal (/WE), row address strobe signal (/RAS), column address strobe signal (/CAS), chip select signal (/CS), and the like, thereby generating operation control signals ACT, PCH, WE, and RD corresponding to the command CMD. The control logic160may provide the operation control signals ACT, PCH, WE, and RD to the timing control circuit. The control signals ACT, PCH, WR, and RD may include an active signal ACT, a precharge signal PCH, a write signal WR, and a read signal RD.

Each of the input/output gating circuits of the input/output gating circuit170may include input data mask logic, read data latches for storing data output from the first to eighth banks111to118, and write drivers for writing data to the first to eighth banks111to118, together with circuits that gate input and output data. A codeword (CW) to be read from one of the first to eighth banks111to118may be sensed by a sense amplifier corresponding to one bank and stored in read data latches. The codeword CW stored in the read data latches may be provided to the memory controller through the input/output buffer190after ECC decoding is performed by the error correction circuit180. Data DQ to be written to one of the first to eighth banks111to118is subjected to ECC encoding in the error correction circuit180, and then, may be written to one bank through write drivers.

The error correction circuit180(ECC1) generates parity bits based on the data bits of the data DQ provided from the input/output buffer190in a write operation, and provides a code word including data DQ and parity bits to the input/output gating circuit170, and the input/output gating circuit170may write a codeword to the bank. Also, the error correction circuit180may receive the codeword CW read from one bank in a read operation from the input/output gating circuit170. The error correction circuit180performs ECC decoding on the data DQ using parity bits included in the read codeword CW to correct at least one error bit included in the data DQ and may provide corrected bit to the input/output buffer190.

The input/output buffer190may provide the data DQ to the error correction circuit180based on the clock CLK provided from the memory controller in a write operation, and may provide the data DQ provided from the error correction circuit180in a read operation to the memory controller.

The memory device100according to an example embodiment includes the clock buffer101having an intentionally imbalanced characteristic, thereby reducing or eliminating a duty error with respect to a clock signal and thus greatly improving the reliability of the clock signal.

FIG.3is a diagram illustrating a clock buffer101according to an example embodiment. Referring toFIG.3, the clock buffer101may include serially connected clock repeaters (CR1to CRk, where k is an integer greater than or equal to 2). In this case, each of the clock repeaters CR1to CRk may include at least two inverters having different imbalanced characteristics from each other. In some embodiments, different successive clock repeaters may have different imbalanced characteristics compared to each other. On the other hand, in some embodiments, each of the successive clock repeaters CR1to CRk may be implemented to have the same imbalanced characteristics as each other.

FIGS.4A and4Bare diagrams illustrating successive clock repeaters having the same imbalance characteristic. As illustrated inFIG.4A, each of the clock repeaters CR1to CR2includes a first inverter INV1having strong pull-up characteristics (e.g., such that the pull-up response, current, and/or voltage is greater than (e.g., higher than, or faster than) the pull-down response, current, and/or voltage) and a second inverter INV2having strong pull-down characteristics (e.g., such that the pull-down response, current, and/or voltage is greater than (e.g., higher than, or faster than) the pull-up response, current, and/or voltage). Two inverters INV1and two inverters INV2may be included. In the opposite case, as illustrated inFIG.4B, each of the clock repeaters CR1to CR2includes a first inverter INV1having strong pull-down characteristics and a second inverter INV2having strong pull-up characteristics. In this case, in the inverter with strong pull-up characteristics, since the driving capability of the PMOS transistor PM is stronger than the driving capability of the NMOS transistor NM (for example, the W/L value (e.g., width to length value) may be higher in the PMOS transistor PM than in the NMOS transistor NM, and thus, the current driving capability is high and the PMOS transistor PM is able to more quickly apply VDD to the inverter output node than the NMOS transistor NM is able to apply a ground voltage to the inverter output node, for example), at the output stage, the high-level to low-level switching operation takes longer than the low-level to high-level switching operation time. Accordingly, an inverter having strong pull-up characteristics operates to increase the duty ratio. In an inverter having strong pull-up characteristics, the driving capability of the PMOS transistor PM is relatively stronger than that of the NMOS transistor NM.

On the other hand, in the inverter with strong pull-down characteristics, since the driving capability of the NMOS transistor NM is stronger than the driving capability of the PMOS transistor PM, in the output stage, a low-level to high-level switching operation time takes longer than a high-level to low-level switching operation time. Accordingly, an inverter with strong pull-down characteristics operates to reduce the duty ratio. In an inverter having strong pull-down characteristics, the driving capability of the NMOS transistor NM is relatively stronger than that of the PMOS transistor PM. These intentionally imbalanced driving capabilities may improve operation of the clock buffer101, for example by reducing duty error.

In another embodiment, the adjacent clock repeaters CR1and CR2may be implemented to have characteristics that are imbalanced in different directions. For example, if the pull-up characteristic of the first clock repeater CR1is relatively strong, in the case of the second clock repeater CR2adjacent to the first clock repeater CR1, a pull-down characteristic may be strong. In this case, a repeater with strong pull-up characteristics is a repeater in which the duty ratio of the output signal increases compared to the duty ratio of the input signal, and repeaters with strong pull-down characteristics is the case opposite thereto. Accordingly, an increase in the duty ratio by the first clock repeater CR1may be offset by a decrease in the duty ratio by the second clock repeater CR2. According to an example embodiment, a clock repeater having strong pull-up characteristics may be implemented, as the inverter at the output stage among the two inverters in the clock repeater is configured so that the pull-up characteristics are strong (e.g., the driving capability of the PMOS is stronger than that of the NMOS). A clock repeater with strong pull-down characteristics may be implemented, as the inverter on the output terminal side from among the two inverters in the clock repeater has strong pull-down characteristics (that is, the driving capability of NMOS is stronger than that of PMOS).

It should be understood that the clock buffer101of the present inventive concept is not limited to the illustrated one. The clock buffer of the present inventive concept may include one or more clock repeaters having intentionally imbalanced characteristics. As discussed herein, an intentionally imbalanced characteristic refers to an imbalance characteristic that is selected and/or designed in the clock repeater, rather than an imbalance characteristic that occurs incidentally as a result of typical manufacturing variations.

FIGS.4C and4Dare diagrams illustrating an example embodiment of a clock buffer composed of continuous clock repeaters according to an example embodiment. In an example embodiment, a space between the clock repeaters (e.g., between INV12and INV21ofFIG.4C) may be implemented as a long metal line. Accordingly, the path between adjacent clock repeaters implemented with long metal lines may be longer than the path between the first inverter and the second inverter inside the clock repeater (e.g., between INV11and INV12and between INV21and INV22).

Referring toFIG.4C, the clock buffer101may include a first clock repeater CR1having strong pull-up characteristics and a second clock repeater CR2having strong pull-down characteristics.

The first clock repeater CR1may have strong pull-up characteristics.

The first clock repeater CR1may include a first inverter INV11and a second inverter INV12. The first inverter INV11may include a PMOS transistor PM11connected to the power terminal VDD and an NMOS transistor NM11connected to the ground terminal GND. A clock signal is input to the gates of the PMOS transistor PM11and the NMOS transistor NM11. The drain of the PMOS transistor PM11and the drain of the NMOS transistor NM11are connected to each other. The output clock of the first inverter INV11is output through the drain of the PMOS transistor PM11and the drain of the NMOS transistor NM11. In an example embodiment, the driving capabilities of the PMOS transistor PM11and the NMOS transistor NM11may be implemented identically, to be balanced so that a duty cycle of the input to the first inverter INV11is the same as the duty cycle of the output from the first inverter INV11.

The second inverter INV12may include a PMOS transistor PM12connected to the power terminal VDD and an NMOS transistor NM12connected to the ground terminal GND. The output clock signal of the first inverter INV11is input to the gates of the PMOS transistor PM12and the NMOS transistor NM12. The drain of the PMOS transistor PM12and the drain of the NMOS transistor NM12are connected to each other. The output clock of the second inverter INV12is output through the drain of the PMOS transistor PM12and the drain of the NMOS transistor NM12. In an example embodiment, driving capabilities of the PMOS transistor PM12and the NMOS transistor NM12may be implemented differently. For example, as illustrated inFIG.4A, the driving capability of the PMOS transistor PM12may be strong and the driving capability of the NMOS transistor NM12may be weak.

The second clock repeater CR2may have strong pull-down characteristics.

The second clock repeater CR2may include a first inverter INV21and a second inverter INV22. The first inverter INV21may include a PMOS transistor PM21and an NMOS transistor NM21connected between the power terminal VDD and the ground terminal GND. The output clock signal of the first clock repeater CR1is input to the gates of the PMOS transistor PM21and the NMOS transistor NM21. In an example embodiment, the driving capabilities of the PMOS transistor PM21and the NMOS transistor NM21may be identically implemented, to be balanced.

The second inverter INV22may include a PMOS transistor PM22and an NMOS transistor NM22connected between the power terminal VDD and the ground terminal GND. The output clock signal of the first inverter INV21is input to the gates of the PMOS transistor PM22and the NMOS transistor NM22. In an example embodiment, driving capabilities of the PMOS transistor PM22and the NMOS transistor NM22may be implemented differently. For example, as illustrated inFIG.4A, the driving capability of the PMOS transistor PM12is weak and the driving capability of the NMOS transistor NM12is strong.

As described above, the clock buffer101illustrated inFIG.4Cis implemented with a first clock repeater CR1having strong pull-up characteristics and a second clock repeater CR2having strong pull-down characteristics. However, the clock buffer of the present inventive concept need not be limited thereto.

As illustrated inFIG.4D, the clock buffer101amay be implemented with a first clock repeater CR1having strong pull-down characteristics and a second clock repeater CR2having strong pull-up characteristics. For example, the second inverter INV12of the first clock repeater CR1may be implemented with a PMOS transistor PM12having a weak pull-up characteristic and an NMOS transistor NM12having strong pull-down characteristics. Also, the second inverter INV22of the second clock repeater CR2may be implemented with a PMOS transistor PM22having strong pull-up characteristics and an NMOS transistor NM22having a weak pull-down characteristic.

FIGS.4C and4Dillustrate a clock buffer in which clock repeaters having imbalanced characteristics are continuously and consecutively connected. However, the clock buffer of the present inventive concept does not require imbalanced clock repeaters to be connected consecutively.

FIGS.5A and5Bare diagrams illustrating clock buffers to which clock repeaters having imbalanced characteristics are discontinuously connected.

Referring toFIG.5A, the clock buffer101bmay include a first clock repeater CR1, a second clock repeater CR2, and a third clock repeater CR3.

The first clock repeater CR1and the third clock repeater CR3may be implemented to have imbalanced characteristics. The second clock repeater CR2may be implemented to have balanced characteristics. In an example embodiment, the first clock repeater CR1may have strong pull-up characteristics, and the third clock repeater CR2may implement strong pull-down characteristics. For example, the second inverter INV12of the first clock repeater CR1may be implemented with a PMOS transistor PM12having strong pull-up characteristics and an NMOS transistor NM12having a weak pull-down characteristic. Also, the second inverter INV32of the third clock repeater CR2may be implemented with a PMOS transistor PM22having a weak pull-up characteristic and an NMOS transistor NM32having strong pull-down characteristics.

Referring toFIG.5B, the clock buffer101cmay be implemented by a first clock repeater CR1having strong pull-down characteristics and a third clock repeater CR3having strong pull-up characteristics, unlike the clock buffer101billustrated inFIG.5A.

On the other hand, it should be understood that the clock buffers illustrated inFIGS.5A and5Bare merely example embodiments of clock repeaters having discontinuously connected imbalanced characteristics. In the clock buffer of the present inventive concept, clock repeaters having imbalanced characteristics may be discontinuously connected in various other ways.

FIG.6is a view illustrating factors that may reflect imbalanced characteristics of driving capability according to an example embodiment. Referring toFIG.6, the imbalance factors may include doping concentration of a transistor, channel width/length of transistor, location of metal contact, various voltages (e.g., threshold voltage (Vth), bias voltage (VBB), supply voltage (VDD), ground voltage (VSS), or the like), and a layout. The driving capability of the PMOS transistor and the NMOS transistor constituting the inverter may be set differently depending on at least one imbalance factor described above. For example, in the channel implantation operation of the PMOS/NMOS transistor, the threshold voltage may be lowered by lowering the doping concentration to increase the driving capabilities, or the driving capability may be strengthened as the channel width/length value increases. In addition, the position of the gate metal contact may be disposed relatively close to the portion of the transistor for which the driving capability is to be strengthened. In some embodiments, the memory device according to example embodiments may be implemented to vary the clock repeater path according to the operation mode. In some embodiments, the imbalanced characteristic and/or the imbalanced driving capability of the different transistors or inverters of a clock buffer may be due to imbalances that are equal in type and equal in magnitude, but different in direction.

FIG.7is a diagram illustrating a memory device100aaccording to another embodiment of the present inventive concept. Referring toFIG.7, the memory device100amay include a normal clock repeater path101-1and an advanced clock repeater path101-2.

The normal clock repeater path101-1may be implemented as clock repeaters having balanced characteristics. In an example embodiment, the normal clock repeater path101-1may be activated in the normal mode.

The advanced clock repeater path101-2may include at least one clock repeater having an imbalanced characteristic. In this case, the clock repeater having the imbalanced characteristic may include inverters having different pull-up/pull-down characteristics as described with reference toFIGS.1to6. In an example embodiment, the advanced clock repeater path101-1may be activated in high-speed mode.

On the other hand, it is not necessary to limit the advanced clock repeater path101-1to be active only in the high-speed mode. The advanced clock repeater path101-1may be implemented to be activated when necessary or desired for precise duty-control according to the judgment of the controller (see200inFIG.1).

For example, to implement selection between a normal clock repeater path101-2and an advanced clock repeater path101-1a switching circuit may be used. For example, the memory device according to an example embodiment may add a bypass path to the imbalanced clock repeater path, connected to a switch, to switch between normal or advanced clock repeater mode.

FIG.8is a diagram illustrating a memory device100baccording to another embodiment. Referring toFIG.8, the memory device100bmay include a clock repeater path101b, a phase detector105, a switch106, SW, and an inverter107, INV.

The clock repeater path101bmay include an inverter having an imbalanced characteristic as described inFIGS.1to7.

The phase detector105may be implemented to detect the phase of the output stage of all clock repeaters. The phase detector105may output the switch signal SS according to the detected phase. For example, the phase detector105may detect a malfunction of the clock repeater and output the switch signal SS according to the detection result. In the case of a clock repeater (or inverter) in which a malfunction is detected, the normal path to which an imbalanced characteristic is not applied may be bypassed. Also, a corresponding clock repeater paired with a malfunctioning clock repeater (i.e., either the malfunctioning clock repeater and either clock repeater with the opposite direction of imbalanced characteristic) may be bypassed by the normal route. In response to the switch signal SS, the switch106may select whether the path of the clock signal is to be the original clock repeater path101bor the bypass path having the inverter107. In this case, the inverter107may be an inverter having a balanced characteristic. AlthoughFIG.8illustrates only bypass for one inverter for convenience of description, it should be understood that the present inventive concept is not limited thereto.

InFIGS.1to8, the clock repeater path according to an example embodiment includes an inverter having an imbalanced characteristic. However, the clock repeater path of the inventive concept will not be limited thereto. The clock repeater path of one embodiment of the inventive concept is implemented with inverters having a balanced characteristic, and may include an inverter having an imbalanced characteristic in the bypass path.

FIG.9is a diagram illustrating a memory device100caccording to another embodiment of the present inventive concept. Referring toFIG.9, the memory device100cincludes a clock repeater path101c, a phase detector105c, a first switch106-1, SW1, a second switch106-2, SW2, an inverter107-1, and a second unbalanced inverter107-2.

The clock repeater path101cmay include series-connected inverters. In this case, each of the series-connected inverters may be implemented with a PMOS transistor and an NMOS transistor with balanced characteristics.

The phase detector105cmay be implemented to detect a phase between a clock signal between an input end and an output end. The phase detector105cmay generate a switch signal according to the detected phase difference.

The first switch106-1(SW1) may select the clock signal path from the clock repeater path101cto the bypass path having the first inverter107-1in response to the switch signal. In this case, the first inverter107-1may be an inverter having imbalanced characteristics.

The second switch106-2(SW2) may select a path of the clock signal from the clock repeater path101cto the bypass path with the second inverter107-2in response to the inverted signal of the switch signal. In this case, the second inverter107-2may be an inverter having an imbalanced characteristic. In an example embodiment, an imbalanced characteristic of the second inverter107-2may be different from an imbalanced characteristic of the first inverter107-1. For example, the second inverter107-2may have strong pull-up characteristics, and the first inverter107-1may have strong pull-down characteristics.

The imbalanced clock repeater path according to some example embodiments may be used for a coarse/fine clock repeater path.

FIGS.10A and10Bare diagrams illustrating, by way of example, a memory device having a clock repeater path according to another embodiment of the present inventive concept.

Referring toFIG.10A, the memory device100dmay include a coarse clock repeater path108and a fine clock repeater path109. In an example embodiment, the coarse clock repeater path108may include series-connected inverters having balanced characteristics. In an example embodiment, the fine clock repeater path109may include at least one inverter having an imbalanced characteristic as described inFIGS.1to9.

Referring toFIG.10B, the memory device100emay include a coarse clock repeater path108aand a fine clock repeater path109a. In an example embodiment, the coarse clock repeater path108amay include at least one inverter having a first imbalanced characteristic. In an example embodiment, the fine clock repeater path109amay include at least one inverter having a second imbalanced characteristic, wherein the intensity corresponding to the second imbalanced feature is less than the intensity corresponding to the first imbalanced feature.

In either of these embodiments, the clock repeater path may be implemented as a coarse path and a fine path. Different degrees of coarse path and fine imbalance may be implemented. For example, the size of the tuning (the size of the resolution) may be different from each other. A coarse path may be used, and in the case in which the coarse path alone cannot completely cancel the duty error (i.e., when the duty error remains), the clock signal may be implemented to not pass through a portion of the coarse path but to be bypassed to a portion of the fine path (bypass).

The memory system according to an example embodiment may be implemented to monitor a duty error and adjust the duty according to the monitoring result.

FIG.11is a diagram illustrating, by way of example, a memory system20according to another embodiment of the present inventive concept. Referring toFIG.11, the memory system20may include a memory device300(MEM) and a memory controller400(MCNTL) for controlling it.

The memory device300may include a clock buffer301, a duty cycle monitor302, DCM, a register303and a duty cycle adjuster304, DCA.

The clock buffer301may include a clock repeater path with the intentional imbalanced characteristic described inFIGS.1-10.

The duty cycle monitor302(DCM) may be implemented to monitor the duty of a clock, for example, a data transfer clock (WCK). For example, the duty cycle monitor302may monitor the duty of the data transmission clock WCK passing through the write/read path in the DCA training period.

The register303may store the DCA code value DCA_CODE transmitted from the memory controller400.

The duty cycle adjuster304(DCA) may be implemented to optimize the duty of the clock buffer301using a DCA code value.

The memory controller400may include a duty controller410that controls the duty of the memory device300. The duty controller410transmits the data transfer clock WCK to the memory device300, receives training information T_INF related to DCA training from the memory device300, and receives the training information T_INF corresponding to the training information T_INF. A DCA code value (DCA_CODE) may be output to the memory device300.

The memory system20according to an example embodiment includes the memory device300that removes the duty error itself and the controller400that controls the duty of the memory device300, such that the transmission clock signal WCK may have greatly improved reliability.

FIG.12is a ladder diagram illustrating, by way of example, a method of operating a memory system according to an example embodiment. Referring toFIG.12, the operation method of the memory system may include the following.

The memory controller MCNTL may transmit a DCA training request to the memory device MEM (S10). The duty cycle monitor DCM of the memory device MEM may perform a training operation on the clock buffer301(refer toFIG.11) according to the DCA training request (S11). A result value for the DCA training result may be stored in the register303(S12). The DCA training result value stored in the register303may be output to the memory controller MCNTL (S13). The memory controller MCNTL may receive a DCA training result value from the memory device MEM, and output a DCA code value DCA_CODE corresponding to the received result value to the memory device MEM (S14). The duty cycle adjuster DCA of the memory device MEM may adjust the duty of the clock buffer301(refer toFIG.11) in response to the DCA code value DCA_CODE (S15). For example, the duty cycle can be set by using one of the implementations described previously for setting duty cycles using clock repeaters and/or inverters with imbalanced characteristics.

FIG.13is a flowchart illustrating, by way of example, an operation of a memory device according to an example embodiment.1to13, the memory device100may operate as follows. The memory device100may receive an operation mode from the memory controller200(refer toFIG.1) (S110). The memory device100may select a clock repeater path according to the received operation mode (S120). For example, when the operation mode is the special mode, the memory device100may select a path having an intentional imbalanced characteristic as the clock repeater path.

A memory device according to an example embodiment is applicable to a memory module.

FIG.14is a diagram illustrating, by way of example, a memory module500according to an example embodiment. Referring toFIG.14, the memory module500may include a plurality of memory chips (DRAMs) each including a memory cell array, a buffer chip (RCD) for routing transmission/reception signals with the memory controller or managing memory operations for the memory chips, and a Power Management Chip (PMIC). Each of the plurality of memory chips may include a clock repeater path having an intentionally imbalanced characteristic as described inFIGS.1to13.

The RCD may control the memory chips (DRAM) and the power management chip (PMIC) under the control of the memory controller. For example, the RCD may receive a command signal, a control signal and a clock signal from the memory controller.

Each of the memory chips (DRAM) is connected to a corresponding data buffer among the data buffers (DB) through a corresponding data transmission line. The data signal DQ and the data strobe signal DQS may be exchanged. The memory chips DRAM are respectively connected to the data buffer DB through corresponding data transmission lines to transmit and receive parity data PRT and data strobe signal DQS.

The SPD chip (not illustrated) may be a programmable read only memory (EEPROM). The SPD chip may include device information or initial information of the memory module1000. As an example, the SPD chip may include initial information or device information, such as module type, module configuration, storage capacity, module type, execution environment, the like of the memory module500. When the memory system including the memory module500is booted, the memory controller reads device information from the SPD chip and recognizes the memory module based on the read device information.

In an example embodiment, the rank may include 8 bank groups. Each of the bank groups may include four banks. In an example embodiment, the memory chips may be divided into first channel dedicated memory chips and second channel dedicated memory chips.

In some embodiments, the memory device of the present inventive concept is applicable to a computing device.

FIG.15is a diagram illustrating, by way of example, a computing system1000according to an example embodiment. Referring toFIG.15, the system1000may include a main processor1100, memories1200aand1200b, and storage devices1300aand1300b, and additionally, may include one or more of an image capturing device1410, a user input device1420, a sensor1430, a communication device1440, a display1450, a speaker1460, a power supply device (1470) and the connecting interface (1480).

The main processor1100may control the overall operation of the system1000, and more specifically, the operation of other components constituting the system1000. The main processor1100may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

The main processor1100may include one or more CPU cores1110and may further include a controller1120for controlling the memories1200aand1200bor the storage devices1300aand1300b. In an example embodiment, the main processor1100may further include an accelerator block1130that is a dedicated circuit for high-speed data operation such as artificial intelligence (AI) data operation. The accelerator block1130may include a graphics processing unit (GPU), a neural processing unit (NPU), a data processing unit (DPU), and the like, and may be implemented as a separate chip physically independent from other components of the main processor1100.

The memories1200aand1200bmay be used as the main memory device of the system1000and may include volatile memories such as SRAM or DRAM, and a non-volatile memory such as flash memory, PRAM or RRAM. The memories1200aand1200bmay be implemented in the same package as the main processor1100. In detail, the memories1200aand1200bmay include a clock buffer provided to have an intentionally imbalanced characteristic to reduce a process error internally as described with reference toFIGS.1to14.

The storage devices1300aand1300bmay function as non-volatile storage devices that store data regardless of whether power is supplied or not, and may have a relatively large storage capacity compared to the memories1200aand1200b. The storage devices1300aand1300bmay include storage controllers1310aand1310band non-volatile memory (NVM) storage1320aand1320bthat stores data under the control of the storage controllers1310aand1310b. The non-volatile memories1320aand1320bmay include a V-NAND flash memory having a 2D (2-dimensional) structure or a 3D (7-dimensional) structure, and may include other types of non-volatile memory such as PRAM or RRAM.

The storage devices1300aand1300bmay be included in the system1000in a state physically separated from the main processor1100, and may be implemented in the same package as the main processor1100. In addition, the storage devices1300aand1300bmay have the same shape as a solid state device (SSD) or a memory card, and may be detachably coupled to other components of the system1000through an interface such as a connection interface2480to be described later. The storage devices1300aand1300bmay be devices to which standard protocols such as universal flash storage (UFS), embedded multi-media card (eMMC), or non-volatile memory express (NVMe) are applied, but are not necessarily limited thereto.

The image capture device1410, also described as an optical input device, or a photographing device, may photograph a still image or a moving image, and may be a camera, a camcorder, or a webcam.

The user input device1420may receive various types of data input from a user of the system1000, and may be or may include a touch pad, a keypad, a keyboard, a mouse, or a microphone.

The sensor1430may detect various types of physical quantities that may be acquired from the outside of the system1000, and may convert the sensed physical quantities into electrical signals. The sensor1430may be, for example, a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor, or a gyroscope.

The communication device1440may transmit and receive signals between other devices outside the system1000according to various communication protocols. Such a communication device2440may be implemented including an antenna, a transceiver, or a modem (MODEM).

The display1450and the speaker1460may function as output devices for outputting visual information and auditory information to the user of the system1000, respectively.

The power supply device1470may appropriately convert power supplied from a battery built into the system1000or an external power source and supply it to each component of the system1000.

The connection interface1480may provide a connection between the system1000and an external device connected to the system1000to exchange data with the system1000. The connection interface1480may be implemented in various interface methods, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), external SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnection (PCI), PCI express (PCIe), NVM express (NVMe), IEEE 1394, universal serial bus (USB), secure digital (SD) card, multi-media card (MMC), embedded multi-media card (eMMC), Universal Flash Storage (UFS), embedded Universal Flash Storage (eUFS), compact flash (CF) card interface, or the like.

FIG.16is a block diagram illustrating a semiconductor package having a stacked structure including a plurality of layers according to an example embodiment. Referring toFIG.16, the semiconductor package2000may include a plurality of layers LA1to LAn. Each of the first layer LA1to the n−1 th layer LAn may be a memory layer (or a memory chip) including a plurality of memory cores MC. The memory core MC may include a memory cell array for storing data, a row decoder, a column decoder, a sense amplifier circuit, and an error correction circuit. In detail, the error correction circuit of the present inventive concept may be implemented to perform different ECCs according to physical locations. For example, different ECC operations may be performed for each layer. In detail, the memory cores MC may include a clock buffer provided to have an intentionally imbalanced characteristic to reduce a process error internally as described with reference toFIGS.1to13.

The n-th layer LAn may be a buffer layer (or a buffer chip). In the semiconductor package2000, the layers LA1to LAn of the stacked structure may be interconnected through a through silicon via (TSV)2300. The buffer layer LAn may communicate with the external memory controller and the memory layers LA1to LAn−1, and may route transmission/reception signals between the memory layers LA1to LAn−1 and the memory controller. Furthermore, the buffer layer LAn may queue signals received from the memory controller or the memory layers LA1to LAn−1. Also, the buffer layer LAn may include a training block2200. The buffer layer LAn may use the training block2200to perform a training operation on the memory layers LA1to LAn−1.

FIG.17is a diagram illustrating a semiconductor package including a stacked semiconductor chip according to an example embodiment. Referring toFIG.17, the semiconductor package3000may be a memory module including at least one stack of semiconductor chips3300and system-on-chip (SOC)3400mounted on a package substrate3100such as a printed circuit board. An interposer3200may be optionally further provided on the package substrate3100. The stacked semiconductor chip3300may be composed of a Chip-on-Chip (Co C package).

The stack of semiconductor chips3300may include at least one memory chip3320stacked on a buffer chip3310such as a logic chip. The memory chip3320may include a clock buffer having an intentional unbalance characteristic as described inFIGS.1to14.

The buffer chip3310and the at least one memory chip3320may be connected to each other by a through silicon via (TSV). The buffer chip3320may perform a training operation on the memory chip3320. The stacked semiconductor chip3300may be, for example, a high bandwidth memory (HBM) of 500 GB/sec to 1 TB/sec, or more.

According to an example embodiment of the present inventive concept, the situation in which the duty error of the clock signal transmitted through the clock repeater path is cumulatively increased may be prevented without adding an additional configuration. In two adjacent repeaters (1st repeater and 2nd repeater) in the path, an intentionally imbalanced characteristic between PMOS-NMOS is generated in the inverter (1st inverter) on the output side of the 1st repeater and the inverter (2nd inverter) on the output side of the 2nd repeater, and the direction of unbalance may be set to be different between the 1st inverter and the 2nd inverter. By setting the intentionally imbalanced characteristic in different directions for the 1st inverter and the 2nd inverter, the direction (trend) of the process error may also be opposite to each other between the 1st inverter and the 2nd inverter. Therefore, the duty error may be canceled and eliminated in the repeater.

For example, if the characteristic subject to the occurrence of imbalance is the doping concentration, in the 1st inverter, the doping concentration of the PMOS transistor may be greater than (e.g., in one embodiment, 10 times) the doping concentration of the NMOS transistor. In this case, the PMOS transistor has a stronger characteristic than that of the NMOS transistor, and in the 2nd inverter, the doping concentration of the NMOS transistor may be greater than (e.g., 10 times stronger than) the doping concentration of the PMOS transistor. In this case, an imbalance may occur in the direction where the NMOS transistor has stronger characteristics than the PMOS transistor. Other types of characteristics may be adjusted to have an imbalance to achieve the imbalanced clock repeaters as described herein.

In example embodiments of the present inventive concept, duty error correction may be performed using an inverter pair to which intentionally imbalanced characteristic is applied.

As set forth above, in a memory device, a memory system including the same, and a method of operating the same according to an example embodiment, a duty of a clock signal may be removed using clock repeaters having intentionally imbalanced characteristics.

While example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present invention as defined by the appended claims.