Patent ID: 12249679

Identical, similar or similar-acting elements are given the same reference signs in the Figures. The Figures and the proportions of the elements shown in the Figures are not to be regarded as true to scale. Rather, individual elements can be shown exaggeratedly large for better representability and/or for better comprehensibility.

DETAILED DESCRIPTION

The radiation emitting semiconductor chip1according to the exemplary embodiment ofFIG.1comprises a semiconductor layer sequence2having an active region3which is configured to generate electromagnetic radiation. The semiconductor layer sequence2has a first semiconductor layer4and a second semiconductor layer5. In this exemplary embodiment, the first semiconductor layer4is formed p-doped and the second semiconductor layer5is formed n-doped.

Furthermore, the radiation emitting semiconductor chip1comprises a first dielectric mirror layer6and a second dielectric mirror layer7, as well as a first current spreading layer10and a second current spreading layer11.

The second current spreading layer11is arranged on the first semiconductor layer4and is in direct contact therewith. The second current spreading layer11is formed here with a TCO, such as zinc oxide, tin oxide, cadmium oxide, titanium oxide, indium oxide or indium tin oxide.

The first dielectric mirror layer6is arranged above the second current spreading layer11. The first dielectric mirror layer6is in direct contact with the second current spreading layer11. Furthermore, the first dielectric mirror layer6comprises a first recess8. The first recess8completely penetrates the first dielectric mirror layer6and exposes the second current spreading layer11. A side surface of the first recess6includes an angle of about 60° with a main extension plane of the semiconductor layer sequence2.

In this exemplary embodiment, the first dielectric mirror layer6comprises SiO2. Furthermore, the dielectric mirror layer6has an extension in the vertical direction17which may be at least 200 nanometres and at most 2000 nanometres.

The first current spreading layer10is arranged above the first dielectric mirror layer6and in the first recess8. The first current spreading layer10completely covers the side surface of the first recess8. Furthermore, the first current spreading layer10extends on a top surface of the first dielectric mirror layer6in lateral direction18. In the region of the side surface of the first recess8and in the region of the top surface of the first dielectric mirror layer6, the first current spreading layer10is in direct contact with the first dielectric mirror layer6. Furthermore, the first current spreading layer10completely covers the exposed second current spreading layer11. In this region, the first current spreading layer10and the second current spreading layer11are in direct contact. Thus, the first current spreading layer10in the first recess8is electrically conductively connected to the second current spreading layer11.

In this exemplary embodiment, the second current spreading layer11may include ITO and has a thickness that is at least 5 nanometres and at most 30 nanometres, for example approximately 15 nanometres. Furthermore, the first current spreading layer10here may have an extension in the lateral direction18of at most 15 micrometres.

An intermediate layer12is arranged above the first dielectric mirror layer6and the first current spreading layer11. In this exemplary embodiment, the intermediate layer12is a planarization layer. The intermediate layer11is formed by a spin-on glass, such as comprising silicon dioxide doped with, for example, boron or phosphorus.

The intermediate layer12completely fills the first recess8. In this case, the intermediate layer12is in direct contact with the first current spreading layer10in the first recess8. Furthermore, the intermediate layer12projects beyond the first current spreading layer10and the first dielectric mirror layer6in vertical direction17. Furthermore, the intermediate layer12projects beyond the first current spreading layer10in lateral direction18. A top surface of the intermediate layer12facing away from the semiconductor layer sequence2may be substantially smooth. That is to say that the top surface of the intermediate layer12has an average roughness of at most 100 nanometres.

A second dielectric mirror layer7is arranged above the intermediate layer12. The second dielectric mirror layer7and the intermediate layer12are stacked on top of one another in vertical direction17and are in direct contact. In this exemplary embodiment, the second dielectric mirror layer7is a further Bragg mirror.

The second dielectric mirror layer7has a second recess9. Furthermore, the intermediate layer12also has the second recess9. The second recess9completely penetrates the second dielectric mirror layer7and the intermediate layer12, so that the second recess9extends up to the first current spreading layer10. A side surface of the second recess9includes an angle of about 60° with a main extension plane of the semiconductor layer sequence2.

A metallic contact layer13is arranged above the second dielectric mirror layer7. Furthermore, the metallic contact layer13is arranged in the second recess9. The metallic contact layer9completely covers the side surface of the second recess9. The metallic contact layer9is here in direct contact with the second dielectric mirror layer7. The metallic contact layer9is formed with silver in this exemplary embodiment.

In the second recess9, the metallic contact layer13is in direct contact with the first current spreading layer10. Thus, the metallic contact layer13in the second recess9is electrically conductively connected to the first current spreading layer10.

In plan view, the first recess8does not overlap with the second recess9in lateral direction18. That is to say that in plan view, the first recess8is arranged spaced apart from the second recess9in lateral direction18.

In the radiation emitting semiconductor chip1according to the exemplary embodiment ofFIGS.2and3, the second recess9completely surrounds the first recess8in lateral direction18. In this exemplary embodiment, the second recess9is configured as a continuous trench. As in the exemplary embodiment ofFIG.1, the first recess8does not overlap with the second recess9in lateral direction18in plan view.

In contrast to the exemplary embodiment ofFIG.1, the radiation emitting semiconductor chip1according to the exemplary embodiment ofFIG.4does not have a second current spreading layer11. The first recess8completely penetrates the first dielectric mirror layer6and exposes the semiconductor layer sequence2. Furthermore, in the exemplary embodiment ofFIG.4, in contrast to the exemplary embodiment ofFIG.1, the second semiconductor layer5is adjacent to and in direct contact with the first dielectric layer sequence. That is to say that the first recess8exposes the second semiconductor layer5.

In this exemplary embodiment, the first current spreading layer10is electrically conductively connected to the semiconductor layer sequence, in particular the second semiconductor layer5, in the first recess8. In the region of the second semiconductor layer5exposed by the first recess8, the first current spreading layer may be in direct contact with the second semiconductor layer5.

The radiation emitting semiconductor chip1according to the exemplary embodiment ofFIG.5, in contrast to the exemplary embodiment ofFIG.4, does not have an intermediate layer12. The second dielectric mirror layer7is arranged directly above the first current spreading layer10and the first dielectric mirror layer6.

In this exemplary embodiment, the second dielectric mirror layer7is arranged in a first recess8. A top surface of the second dielectric mirror layer7does not extend parallel to the main extension plane, but has a depression in the region of the first recess8.

In this exemplary embodiment, the second dielectric mirror layer7comprises SiO2. Furthermore, the dielectric mirror layer7has an extension in vertical direction17which may be at least 200 nanometres and at most 2000 nanometres. Furthermore, the first current spreading layer10here may extend in lateral direction18of at most 10 micrometres.

In this exemplary embodiment, the metallic contact layer9is formed with silver or aluminium.

In the method according to the exemplary embodiment ofFIGS.6,7,8,9and10, a semiconductor layer sequence2is provided, above which a first dielectric mirror layer6is applied, as shown inFIG.6. Furthermore, a sacrificial layer14is applied above the first dielectric mirror layer6, which has a third recess15.

In a further method step, a first recess8is generated in the first dielectric mirror layer6by a dry chemical or wet chemical etching process (FIG.7). The sacrificial layer14with the third recess15acts here as a mask for the first recess8.

Subsequently, the sacrificial layer14is partially removed by an oxygen plasma in such a way that a fourth recess16is generated in the sacrificial layer14(seeFIG.8).

In a next method step, a first current spreading layer10is applied above the sacrificial layer, the first dielectric mirror layer6and the semiconductor layer sequence2(FIG.9).

In a subsequent method step, the sacrificial layer14is removed by a lift-off process or an oxygen plasma (FIG.10). The first current spreading layer10, which covers the sacrificial layer14, is also removed in this method step in the region of the sacrificial layer14. The fourth recess16in the sacrificial layer14acts as a mask for the first current spreading layer10and predetermines the lateral dimensions of the first current spreading layer10.

In the exemplary focused ion beam microscope image of a radiation emitting semiconductor chip according to an exemplary embodiment ofFIGS.11and12, the radiation emitting semiconductor chip1has a first current spreading layer10and a second current spreading layer11. The dashed lines are of a virtual nature and are drawn only for better visualisation of the current spreading layers10and11. Here, an extension in lateral direction18of the first current spreading layer10is at most 10 micrometres.

This patent application claims the priority of German patent application 102019120444.5, the disclosure content of which is hereby incorporated by reference.

The features and embodiments described in connection with the figures may be combined with one another according to further embodiments, even though not all combinations are explicitly described. Furthermore, the embodiments described in connection with the figures may alternatively or additionally have further features according to the description in the general part.

The invention is not limited by the description on the basis of the exemplary embodiments. Rather, the invention encompasses any new feature as well as any combination of features, which in particular includes any combination of features in the claims, even if this feature or combination itself is not explicitly indicated in the claims or exemplary embodiments.

LIST OF REFERENCE SIGNS

1radiation emitting semiconductor chip2semiconductor layer sequence3active region4first semiconductor layer5second semiconductor layer6first dielectric mirror layer7second dielectric mirror layer8first recess9second recess10first current spreading layer11second current spreading layer12intermediate layer13metallic contact layer14sacrificial layer15third recess16fourth recess17vertical direction18lateral direction