Patent ID: 12248335

DETAILED DESCRIPTION

Aspects of the present disclosure relate to phase detection circuitry for high-frequency phase error detection.

Multi-phase systems use two or more clock signal phases (e.g., multi-phase clock signals) to transmit and/or receive signals. Example multi-phase systems include transceiver devices (e.g., serializer/deserializer (SerDes) transceivers, among others), radio frequency (RF) systems, and systems that process data using multi-phase clock signals. Multi-phase clock signals may be used in data conversion systems, such as time division multiplexed or time-interleaved data conversion in serial link data conversion systems. In one or more examples, multi-phase clock signals may be used to demodulate radio frequency (RF) signals using in-phase and quadrature (IQ) mixing processes. The multi-phase system may be a wireline or wireless system. In one or more examples, the multi-phase system may be used in electronically scanned array antennas, analog-to-digital converters, quarter rate transmitters and/or half rate transmitters.

In a multi-phase system, the multi-phase clock signals are generated by clock generation circuitry from a reference clock signal. In one or more examples, one or more of the multi-phase clock signals have the same frequency. Further, in one or more examples, ideally, the multi-phase clock signals are equally spaced in time. In one example, the frequency of the multi-phase clock signals may be the same as the frequency of the reference clock signal. The clock generation circuitry may be delay line circuitry (e.g., voltage controlled delay circuitry (VCDL) circuitry, among others), injection-locked oscillator (ILO) circuitry, delay-locked loop (DLL) circuitry, or ring oscillator circuitry, among others. The clock generation circuitry receives the reference clock signal and generates multi-phase clock signals from the reference clock signal.

In one example, the multi-phase system is a high-frequency multi-phase clock generator. The high-frequency multi-phase clock generator receives a reference clock signal, which is used to generate the multi-phase clock signals. High frequency multi-phase clock generator may include multi-phase oscillator circuitry operating in a phase-locked loop, a multi-phase oscillator operating in an injection-locked configuration, or a multi-phase delay line in a delay-locked loop configuration. In one example, high frequency refers to at least about 10 GHz. In other examples, high frequency may be less than or greater than about 10 GHz.

Errors (e.g., phase errors) may be present in the multi-phase clock signals. The errors correspond to the phase of one or more of the multi-phase clock signals deviating from the expected (or intended) phase, and may introduce errors within the downstream signal processing.

To mitigate phase error between the multi-phase clock signals, phase error detection circuitry is used to detect (or measure) phase error between pairs of the multi-phase clock signals, and generate a one or more signals based on the detected phase error. The one or more signals are provided to the clock generation circuitry, which generates adjusted multi-phase clock signals based on the control signal. The control signal is used by the clock generation circuitry to mitigate phase error between the multi-phase clock signals, generating adjusted multi-phase clock signals. Some phase error detection circuitry may include phase detection circuitry that includes mixer circuitries, which detect phase differences between pairs of the multi-phase clock signals. The mixer circuitry includes a combination of passive and active devices (e.g., resistors and transistors) that function to detect phase differences between pairs of the multi-phase clock signals. However, the use of passive devices increases the circuit area of the mixer circuitries, increasing the semiconductor manufacturing costs of the corresponding multi-phase system.

The multi-phase system described herein uses a phase detection circuitry that includes mixer circuitries that are formed from transistors and omits resistors. For example, the mixer circuitries as described herein are formed from n-type metal-oxide semiconductor (NMOS) transistors and/or p-type MOS (PMOS) transistors that used to detect phase differences between pairs of the multi-phase clock. Further, the mixer circuitries described herein include output transistors, having a power state controlled by respective bias voltages.

The technical advantages of the present disclosure include, but are not limited to mixer circuitries that are formed from active devices (e.g., transistors), omitting passive devices (e.g., resistors), reducing the circuit area of the corresponding multi-phase system. Reducing the circuit area reduces the semiconductor manufacturing cost of the corresponding multi-phase system. Additionally, the use of transistors, allows for easier integration within semiconductor devices that include other elements of a similar semiconductor technology (e.g., metal oxide semiconductors, among others) providing easier layout integration, and low loading and low routing complexity imposed on the multi-phase clock signals. The mixer circuitries as described herein may be referred to as being compact mixer circuitries due to the small circuit area, and as the mixer circuitries may be positioned (e.g., abutted) next to the corresponding clock generator circuitry within the circuit design. Further, the mixer circuitries described herein have differential outputs controlled via transistors. The output transistors are biased with corresponding bias voltage signals. Accordingly, the mixer circuitries may be placed in a powered down state using the bias voltage signals, reducing the power consumption of the corresponding multi-phase system. The output transistors provide the ability to independently shut down the mixer circuitries to save power. Further, the mixer circuitries as described herein provide increased robustness over process, voltage, and temperature (PVT) variations, providing a consistent performance over PVT variations as compared to other mixer circuitries that include both active and passive devices. As is described in further detail in the following the mixer circuitries described herein have low and balanced input loading, and low inherent offset that provides more accurate error detection based.

FIG.1illustrates a block diagram of an electronic system10, according to one or more examples. The electronic system10may be a system that operates using multiple clock signals. In one example, the electronic system10is a fast time-interleaved analog-to-digital converter (ADC) circuitry. In such an example, time-interleaved ADC circuitry utilizes multiple slower running ADC circuitries to implement a faster ADC circuitry. In another example, the electronic system10is a wireless communications system that implement beamforming using multi-phase clock signals. In one example, the electronic system10is at least a part of a transceiver system, an RF system, and/or a data processing system that processes a data signal at different phases.

In one example, a digital representation of the circuit design of the electronic system10is stored within a memory (e.g., the main memory604ofFIG.6and/or the machine-readable medium624ofFIG.6).

The electronic system10includes multi-phase clock generation circuitry100. The multi-phase clock generation circuitry100receives a clock signal102, and generates multi-phase clock signals104from the clock signal102. The clock signal102is the reference (e.g., a reference clock signal generated internally or externally) used to generate the multi-phase clock signals104. In one example, the frequency for each of the multi-phase clock signals104corresponds to the frequency of the clock signal102. In such an example, the multi-phase clock signal104have the same frequency. The multi-phase clock signals104includes two or more clock signals that are separated from each other by M degrees, where M is greater than zero. In one example, M is 45 degrees. In other examples, M is greater than or less than 45 degrees.

The multi-phase clock signals104may be received by downstream processing elements within and/or external to the electronic system10, and used to process data, or perform other processing tasks. For example, the multi-phase clock signals104may be provided to data processing circuit elements that process received data signals with the multi-phase clock signals.

In one example, the multi-phase clock generation circuitry100includes phase measurement circuitry110that is configured to measure (e.g., determine or detect) phase error between pairs of the multi-phase clock signals104. The phase measurement circuitry110generates one or more signals that are indicative of phase error within the multi-phase clock signals104. The one or more signals are used by the multi-phase clock generation circuitry100to mitigate phase errors between the multi-phase clock signals104. For example, one or more properties (e.g., a variable delay or an operating frequency, among others) is adjusted based on the one or more signals to mitigate phase errors within the multi-phase clock signals104.

In one example, a digital representation of the circuit design of the multi-phase clock generation circuitry100is stored within a memory (e.g., the main memory604ofFIG.6and/or the machine-readable medium624ofFIG.6).

The phase measurement circuitry110includes phase detection circuitry120. The phase detection circuitry120receives the multi-phase clock signals104and generates one or more phase error signals. The phase detection circuitry may be a quadrature phase detection circuitry that detects the phase differences between the multi-phase clock signals104that are in quadrature with each other. In other examples, the phase detection circuitry detects the phase differences between the multi-phase clock signals104that are not in quadrature with each other (e.g., differ by more or less than 90 degrees).

In one example, a digital representation of the circuit design of the phase measurement circuitry110is stored within a memory (e.g., the main memory604ofFIG.6and/or the machine-readable medium624ofFIG.6).

The phase detection circuitry120includes mixer circuitries122. The mixer circuitries122detect a phase difference between pairs of the multi-phase clock signals104. The phase difference may be referred to as a phase error. The mixer circuitries122includes mixer circuitries1221-122N, where N is two or more. In one example, N is at least four. Each of the mixer circuitries122receives a different two of the multi-phase clock signals104, determines whether or not a phase error is present between the multi-phase clock signals104, and outputs a signal indicative of the phase error.

In one example, a digital representation of the circuit design of the phase detection circuitry120is stored within a memory (e.g., the main memory604ofFIG.6and/or the machine-readable medium624ofFIG.6). In one or more example, a digital representation of the circuit design of one or more of the mixer circuitries122is stored within a memory (e.g., the main memory604ofFIG.6and/or the machine-readable medium624ofFIG.6).

FIG.2illustrates one example of a multi-phase clock generation system200, according to one or more examples. The multi-phase clock generation system200receives a reference clock signal102, and generates the multi-phase clock signals104. The multi-phase clock signals104are output from the multi-phase clock generation system200. The multi-phase clock generation system200ofFIG.2converts a phase error between pairs of the multi-phase clock signals104to a differential voltage to realign corresponding clock generation circuitry (e.g., clock generation circuitry240) to mitigate the phase error.

In one example, a digital representation of the circuit design of the multi-phase clock generation system200is stored within a memory (e.g., the main memory604ofFIG.6and/or the machine-readable medium624ofFIG.6).

In one example, the multi-phase clock signals104include multi-phase clock signals CKD_0, CKD_45, CKD_90, CKD_135, CKD_180, CKD_225, CKD_270, and CKD_315. Each of the multi-phase clock signals CKD_0, CKD_45, CKD_90, CKD_135, CKD_180, CKD_225, CKD_270, and CKD_315 has a different phase. In one example, the multi-phase clock signals104are separated in phase by 45 degrees. In other example, the multi-phase clock signals104are separated by more than or less than 45 degrees. The phase difference is consistent between pairs of the multi-phase clock signals104.

The multi-phase clock generation system200includes clock generation circuitry240and phase measurement circuitry210. The input of the phase measurement circuitry210is connected to the output of the clock generation circuitry240. The clock generation circuitry240may be VCDL circuitry, ILO circuitry, DLL circuitry, or ring oscillator circuitry, among others. In one example, the clock generation circuitry240includes one or more buffers that output the multi-phase clock signals104.

The clock generation circuitry240receives the reference clock signal102. In one example, the clock generation circuitry240generates each of the different multi-phase clock signals104based on the frequency of this reference clock signal102.

The phase measurement circuitry210receives the multi-phase clock signals104, detects a phase error within a group or subset of the multi-phase clock signals104, and generates one or more signals208indicative of an error among the multi-phase clock signals104. The one or more signals208provides an indication to adjust the clock generation circuitry240to mitigate phase error between two or more of the multi-phase clock signals104.

The phase measurement circuitry210includes phase detection circuitry120, and amplifier circuitry230. The phase detection circuitry120is configured similar to the phase detection circuitry120ofFIG.1. The phase detection circuitry120receives the multi-phase clock signals104and generates the phase error signals206aand206b. In one example, the phase detection circuitry may be a quadrature phase detection circuitry that detects the phase differences between pairs of the multi-phase clock signals104that are in quadrature with each other. In other examples, the phase detection circuitry detects the phase differences between two of the multi-phase clock signals104that are not in quadrature with each other. The phase error signals206aand206bmay be part of a differential phase error signal206in voltage form. The amplifier circuitry230amplifies the phase error signals206aand206b, and generates the one or more signals208from the phase error signals206aand206b.

The phase detection circuitry120includes mixer circuitries122. The mixer circuitries122detect a phase difference between pairs of the multi-phase clock signals104. The mixer circuitries122includes mixer circuitries1221-122N, where N is two or more. In one example, N is at least four. Each of the mixer circuitries122receives a different pair of the multi-phase clock signals104. Each mixer circuitry122outputs a signal indicative of a phase error between a respective two of the multi-phase clock signals104. The output signals of each of the mixer circuitries122is combined to form the phase error signals206. In an example where the mixer circuitries122detect phase errors between multi-phase clock signals that are in quadrature with each other, the mixer circuitry1221receives the multi-phase clock signals CKD_0 and CKD_90, the mixer circuitry1222receives the multi-phase clock signals CKD_180 and CKD_270, the mixer circuitry1223receives the multi-phase clock signals CKD_180 and CKD_90, and the mixer circuitry1224receives the multi-phase clock signals CKD_270 and CKD_0. In other examples, the mixer circuitries1221-1224receive other combinations of the multi-phase clock signals104.

In one example, the clock generation circuitry240receives the one or more signals208, and generates adjusted multi-phase clock signals. The adjusted multi-phase clock signals are received by the phase detection circuitry120to determine if a phase error is present within the adjusted multi-phase clock signals as described above. In one or more examples, using phase detection circuitry to receive and detect phase error between pairs of the adjusted multi-phase clock signals is continuously performed to mitigate the phase error between pairs of the adjusted multi-phase clock signals.

FIG.3illustrates a schematic circuit diagram of the mixer circuitry122, according to one or more examples. Each of the mixer circuitries1221-122Nis configured as described with regard to the mixer circuitry122ofFIG.3. In one example, a digital representation of the circuit design of the mixer circuitry122as illustrated inFIG.3is stored within a memory (e.g., the main memory604ofFIG.6and/or the machine-readable medium624ofFIG.6).

The mixer circuitry122includes transistors310and transistors320. The transistors310and320receive multi-phase clock signals301and302, and determine whether or not a phase error is present between the multi-phase clock signals301and302. The multi-phase clock signals301and302are two (e.g., a pair) of the multi-phase clock signals104. For example, the multi-phase clock signals301and302include two of the multi-phase clock signals104that are in quadrature with each other. In another example, the multi-phase clock signals301and302include two of the multi-phase clock signals104that are not in quadrature with each other. In such an example, the multi-phase clock signals301and302are separated by more or less than ninety degrees. As pairs of transistors in each of the transistors310and120receive the multi-phase clock signals301and302, respectively, the transistors310and320, and the mixer circuitry122has balanced input loading.

In one example, the size of the transistors310and320corresponds to the loading of the transistors, mismatch between the transistors, and/or phase-current-conversion gain and power of the transistors.

The transistors310includes transistors312,314,316,318, and319. The transistors312,314,316,318, and319are PMOS transistors.

The transistor312has a gate node coupled to the input node303and that receives the multi-phase clock signal301. Further, the transistor312has a source node coupled to a drain node of the transistor318, and a drain node coupled to the source node of the transistor319. The transistor314has a gate node coupled to the input node303and that receives the multi-phase clock signal301. Further, the transistor314has a source node coupled to the voltage node307, and a drain node coupled to the source node of the transistor316. The voltage node307receives a voltage V1. The voltage V1is received from a voltage source.

The transistor316has a gate node coupled to the input node305and that receives the multi-phase clock signal302. Further, the transistor316has a source node coupled to the drain node of the transistor314, and a drain node coupled to the source node of the transistor319. The transistor318has a gate node coupled to the input node305and that receives the multi-phase clock signal302. Further, the transistor316has a source node coupled to the drain node of the transistor314, and a drain node coupled to the source node of the transistor319. The transistor319has a gate node coupled to the voltage node304, a source node coupled to the drain nodes of the transistors312and316, and a drain node coupled to the output node208a.

The transistors312,314,316, and318function as part of a phase-to-current converter to determine whether or not a phase difference (e.g., phase error) is present between the multi-phase clock signals301and302. In one example, the transistors312,314,316, and318generate a current signal based on a phase difference between the multi-phase clock signals301and302.

The voltage node304receives a bias voltage signal (e.g., a PMOS voltage bias (PBIAS) signal). A PBIAS voltage bias signal is used in examples where the transistor319is a PMOS transistor. In other examples, other bias signals may be used. The PBIAS signal controls whether or not the transistor319is in powered on state, and outputs an output signal330via the output node308a. In one example, based on the PBIAS signal having a voltage magnitude greater than the turn-on voltage of the transistor319, the transistor319outputs output signal330via output node308a. Based on the PBIAS signal having a voltage magnitude less than the turn-on voltage of the transistor319, the transistor319is in a powered off state. In one example, placing the transistor319in a powered off state, places the mixer circuitry122in a powered off state, reducing the power consumed by the mixer circuitry122.

The transistors320includes transistors322,324,326,328, and329. The transistors322,324,326,328, and329are NMOS transistors.

The transistor322has a gate node coupled to the input node303and that receives the multi-phase clock signal301. Further, the transistor322has a source node coupled to a drain node of the transistor328, and a drain node coupled to the source node of the transistor329. The transistor324has a gate node coupled to the input node303and that receives the multi-phase clock signal301. Further, the transistor324has a source node coupled to the voltage node309, and a drain node coupled to the source node of the transistor326. The voltage node309receives a ground voltage signal. In one example, the voltage V1has a voltage value that is greater than that of the ground voltage signal.

The transistor326has a gate node coupled to the input node305and that receives the multi-phase clock signal302. Further, the transistor326has a source node coupled to the drain node of the transistor324, and a drain node coupled to the source node of the transistor329. The transistor328has a gate node coupled to the input node305and that receives the multi-phase clock signal302. Further, the transistor326has a source node coupled to the drain node of the transistor324, and a drain node coupled to the source node of the transistor329. The transistor329has a gate node coupled to the voltage node306, a source node coupled to the drain nodes of the transistors322and326, and a drain node coupled to the output node308b.

The transistors322,324,326, and328function as part of a phase-to-current converter to determine whether or not a phase difference (e.g., phase error) is present between the multi-phase clock signals301and302. In one example, the transistors322,324,326, and328generate a current signal based on a phase difference between the multi-phase clock signals301and302.

The voltage node306receives a NMOS voltage bias (NBIAS) signal. The NBIAS signal controls whether or not the transistor329is in powered on state, and outputs an output signal332via the output node308b. A NBIAS voltage bias signal is used in examples where the transistor319is a NMOS transistor. In other examples, other bias signals may be used. In one example, based on the NBIAS signal having a voltage magnitude greater than the turn-on voltage of the transistor329, the transistor329outputs output signal332via output node308b. Based on the NBIAS signal having a voltage magnitude less than the turn-on voltage of the transistor329, the transistor329is in a powered off state. In one example, placing the transistor329in a powered off state, places the transistors320in a powered off state, reducing the power consumed by the mixer circuitry122.

In one example, the output signals330and332form a corresponding differential signal. The output signals330and332are current signals. In one example, the magnitude of the output signal330differs from the magnitude of the output signal332based on a lack of balance in the overlap between the phase of the multi-phase clock signal301and the phase of the multi-phase clock signal302. The phases of the multi-phase clock signals are balanced when the spacing the between the phases of the multi-phase clock signals is equal. In one example, the magnitudes of the output signals330and332do not differ from each other based on the overlap of the phases of the multi-phase clock signal301and the multi-phase clock signal302being balanced.

FIG.4illustrates a block diagram of the phase detection circuitry120, according to one or more examples. As illustrated inFIG.4, the phase detection circuitry120includes mixer circuitries1221-1224. Further, the phase detection circuitry120includes capacitors410and412. The mixer circuitry1221includes transistors3101and3201. Further, the mixer circuitry1221receives the multi-phase clock signals3011and3021. The transistors3101outputs the signal3301, and the transistors3201outputs the signal3321. The signal3301and the signal3321correspond to a phase difference (e.g., phase error) between the multi-phase clock signals3011and3021.

The mixer circuitry1222includes transistors3102and3202. Further, the mixer circuitry1222receives the multi-phase clock signals3012and3022. The transistors3102outputs the signal3302, and the transistors3202outputs the signal3322. The signal3302and the signal3322correspond to a phase difference (e.g., phase error) between the multi-phase clock signals3012and3022.

The mixer circuitry1223includes transistors3103and3203. Further, the mixer circuitry1223receives the multi-phase clock signals3013and3023. The transistors3103outputs the signal3303, and the transistors3203outputs the signal3323. The signal3303and the signal3323correspond to a phase difference (e.g., phase error) between the multi-phase clock signals3013and3023.

The mixer circuitry1224includes transistors3104and3204. Further, the mixer circuitry1224receives the multi-phase clock signals3014and3024. The transistors3104outputs the signal3304, and the transistors3204outputs the signal3324. The signal3304and the signal3324correspond to a phase difference (e.g., phase error) between the multi-phase clock signals3014and3024.

In one example, the multi-phase clock signals3011and3021correspond to multi-phase clock signals CKD_0 and CKD_90, the multi-phase clock signals3012and3022correspond to multi-phase clock signals CKD_180 and CKD_270, the multi-phase clock signals3013and3023correspond to multi-phase clock signals CKD_180 and CKD_90, and the multi-phase clock signals3014and3024correspond to multi-phase clock signals CKD_270 and CKD_0. In other examples, the multi-phase clock signals3011,3012,3013,3014,3021,3022,3023, and3024may be other combinations of the multi-phase clock signals104. For example, the multi-phase clock signals3011and3021,3012and3022,3013and3023, and/or3014and3024may be in quadrature with other, or differ by more than or less than ninety degrees.

The capacitor410receives the signals3301,3302,3323, and3324and generates a phase error signal406abased on the signals3301,3302,3323, and3324. The signals3301,3302,3323, and3324are current signals and the phase error signal406ais a voltage signal. In one example, the capacitor410converts the current signals3301,3302,3323, and3324to a voltage signal, the phase error signal406a. The phase error signal406ais output via the node402. The value of the phase error signal406acorresponds to the value of the signals3301,3302,3323, and3324.

The capacitor412receives the signals3303,3304,3321, and3322, and generates the phase error signal406bbased on the signals3303,3304,3321, and3322. The signals3303,3304,3321, and3322, are current signals and the phase error signal406bis a voltage signal. In one example, the capacitor412converts the current signals3303,3304,3321, and3322to a voltage signal, the phase error signal406b. The phase error signal406bis output via the node404. The value of the phase error signal406bcorresponds to the value of the signals3303,3304,3321, and3322. In one example, the phase error signals406aand406bform a differential signal that represents the average phase error.

In one example, a digital representation of the circuit design of the phase detection circuitry120as illustrated inFIG.4is stored within a memory (e.g., the main memory604ofFIG.6and/or the machine-readable medium624ofFIG.6).

FIG.5illustrates an example timing diagram500of the multi-phase clock signals CKD_0, CLKD_90, CKD_180, and CKD_270, corresponding output signals530a,530b,532a, and532b, and output signal VOUTDIFF. The timing diagram500further includes a reference multi-phase clock signal CKD_90 (REF) waveform and a reference multi-phase clock signal CKD_270 (REF) waveform. The reference multi-phase clock signal CKD_90 (REF) waveform and the reference multi-phase clock signal CKD_270 (REF) waveform represent ideal signal waveforms (e.g., have ideal phase with no phase error) of the multi-phase clock signals CKD_90 and CKD_270, respectively, and are included as a reference for to illustrate the phase error with the multi-phase clock signals CKD_90 and CKD_270. As illustrated inFIG.5, the phase of the multi-phase clock signal CKD_90 is less than the phase of the reference multi-phase clock signal CKD_90 (REF). Further, the phase of the multi-phase clock signals CKD_270 is less than the phase of the reference multi-phase clock signal CKD_270 (REF).

The timing diagram500is one example of a timing diagram for multi-phase clock signals that are in quadrature with each other. In other example, a similar timing diagram may be applied to multi-phase clock signals that differ in phase by more than or less than ninety degrees.

In one example, the output signals530and532are generated based on a comparison of the multi-phase clock signals CKD_0 and CKD_90 and CKD_180, and CKD_270. In such an example, the multi-phase clock signals CKD_0, CDK_90, CKD_180, and CKD_270 are the inputs to corresponding mixer circuitries (e.g., mixer circuitries122ofFIG.1), which generate the output signals530and532from the multi-phase clock signals CKD_0, CDK_90, CKD_180, and CKD_270.

In an example, where no phase errors are present within the multi-phase clock signals CKD_0, CKD_90, CKD_180, and CKD_270, the output signals530aand532aare generated. The output signals530aand532ahave an average value of zero, indicating that no phase error is present within the corresponding multi-phase clock signals. Accordingly, the output signal VOUTDIFF, which is generated based on the output signals530aand532a, has a voltage value of 0. With reference toFIG.4, the output signal VOUTDIFFis the difference in voltage between the output signal406aand406b.

In an example, where a phase error is present within one or more of the multi-phase clock signals CKD_0, CKD_90, CKD_180, and CKD_270, the output signals530band532bare generated. The output signals530band532bhave an average value that is non-zero, indicating that a phase error is present within the corresponding multi-phase clock signals. In one example, the average value is a negative value, and corresponds to a relative phase error within the multi-phase clock signals CKD_90 and CKD_270 with respect to CKD_0 and CKD_180. Accordingly, the output signal VOUTDIFF, which is generated based on the output signals530band532b, has a voltage value that is less than zero.

FIG.6illustrates an example machine of a computer system600within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, may be executed. In alternative implementations, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the Internet. The machine may operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

The example computer system600includes a processing device602, a main memory604(e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), a static memory606(e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device618, which communicate with each other via a bus630.

Processing device602represents one or more processors such as a microprocessor, a central processing unit, or the like. More particularly, the processing device may be complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device602may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device602may be configured to execute instructions626for performing the operations and steps described herein.

The computer system600may further include a network interface device608to communicate over the network620. The computer system600also may include a video display unit610(e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device612(e.g., a keyboard), a cursor control device614(e.g., a mouse), a graphics processing unit622, a signal generation device616(e.g., a speaker), graphics processing unit622, video processing unit628, and audio processing unit632.

The data storage device618may include a machine-readable storage medium624(also known as a non-transitory computer-readable medium) on which is stored one or more sets of instructions626or software embodying any one or more of the methodologies or functions described herein. The instructions626may also reside, completely or at least partially, within the main memory604and/or within the processing device602during execution thereof by the computer system600, the main memory604and the processing device602also constituting machine-readable storage media.

In some implementations, the instructions626include instructions to implement functionality corresponding to the present disclosure. While the machine-readable storage medium624is shown in an example implementation to be a single medium, the term “machine-readable storage medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term “machine-readable storage medium” shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine and the processing device602to perform any one or more of the methodologies of the present disclosure. The term “machine-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the ways used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm may be a sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Such quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the present disclosure, it is appreciated that throughout the description, certain terms refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage devices.

The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may include a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMS, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various other systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the disclosure as described herein.

The present disclosure may be provided as a computer program product, or software, that may include a machine-readable medium having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as a read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.

In the foregoing disclosure, implementations of the disclosure have been described with reference to specific example implementations thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of implementations of the disclosure as set forth in the following claims. Where the disclosure refers to some elements in the singular tense, more than one element can be depicted in the figures and like elements are labeled with like numerals. The disclosure and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.