Patent ID: 12237114

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, multilayer ceramic capacitors according to preferred embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the following preferred embodiments, and can be applied by modifying where appropriate within a scope not changing the gist of the present invention. It should be noted that preferred embodiments of the present invention also includes combinations of two or more of the individual preferred embodiments described below.

Multilayer Ceramic Capacitor

FIG.1is a perspective view schematically showing an example of a multilayer ceramic capacitor according to a preferred embodiment of the present invention.FIG.2is a perspective view schematically showing an example of a multilayer body (for example, a laminate) included in the multilayer ceramic capacitor shown inFIG.1.FIG.3is a cross-sectional view taken along line A-A of the multilayer ceramic capacitor shown inFIG.1.FIG.4is a cross-sectional view taken along line C-C of the multilayer ceramic capacitor shown inFIG.1.

In the present disclosure, a stacking direction (for example, lamination direction), a width direction, and a length direction of the multilayer ceramic capacitor and the multilayer body are respectively defined by the arrows T, W, and L in the multilayer ceramic capacitor1shown inFIG.1and the multilayer body10shown inFIG.2. Herein, the stacking (T) direction, the width (W) direction, and the length (L) direction are orthogonal or substantially orthogonal to one another. The stacking (T) direction refers to a direction in which a plurality of dielectric ceramic layers20, and a plurality of pairs of a first internal electrode layer21and a second internal electrode layer22are stacked.

The multilayer ceramic capacitor1shown inFIG.1includes the multilayer body10, and a first external electrode51and a second external electrode52provided on both end surfaces of the multilayer body10, respectively.

As shown inFIG.2, the multilayer body10has a rectangular shape or a substantially rectangular shape. The multilayer body10includes a first main surface11and a second main surface12on opposite sides in the stacking (T) direction, a first side surface13and a second side surface14on opposite sides in the width (W) direction which is orthogonal or substantially orthogonal to the stacking (T) direction, and a first end surface15and a second end surface16on opposite sides in the length (L) direction which is orthogonal or substantially orthogonal to the stacking (T) direction and the width (W) direction.

In the present disclosure, a cross-section of the multilayer ceramic capacitor1or the multiplayer body10which is orthogonal or substantially orthogonal to the first end surface15and the second end surface16, and parallel or substantially parallel to the stacking (T) direction refers to the LT cross-section, which is a cross-section in the length (L) direction and the stacking (T) direction. Furthermore, a cross-section of the multilayer ceramic capacitor1or the multiplayer body10which is orthogonal or substantially orthogonal to the first side surface13and the second side surface14, and parallel or substantially parallel to the stacking (T) direction refers to WT cross-section, which is a cross-section in the width (W) direction and the stacking (T) direction. Furthermore, a cross-section of the multilayer ceramic capacitor1or the multiplayer body10which is orthogonal or substantially orthogonal to the first side surface13, the second side surface14, the first end surface15, and the second end surface16, and orthogonal or substantially orthogonal to the stacking (T) direction refers to LW cross-section, which is a cross-section in the length (L) direction and the width (W) direction. Therefore,FIG.3is an LT cross-section of the multilayer ceramic capacitor1, andFIG.4is a WT cross-section of the multilayer ceramic capacitor1.

The multilayer body10preferably has rounded corners and ridges. The corners are portions where the three surfaces of the multilayer body intersect, and the ridges are portions where the two surfaces of the multilayer body intersect.

As shown inFIGS.2,3and4, the multilayer body10has a multilayer structure including a plurality of dielectric ceramic layers20stacked in the stacking (T) direction, and a plurality of pairs of the first internal electrode layer21and the second internal electrode layer22provided along the interface between the dielectric ceramic layers20. The dielectric ceramic layer20extends along the width (W) direction and the length (L) direction, and each of the first internal electrode layer21and the second internal electrode layer22extends in a flat plate shape along the dielectric ceramic layer20.

The first internal electrode layer21extends to the first end surface15of the multilayer body10. On the other hand, the second internal electrode layer22extends to the second end surface16of the multilayer body10.

The first internal electrode layer21and the second internal electrode layer22are provided opposite to each other with the dielectric ceramic layer20interposed therebetween in the stacking (T) direction. Capacitance is generated by a portion where the first internal electrode layer21and the second internal electrode layer22are provided opposite to each other with the dielectric ceramic layer20interposed therebetween.

Each of the first internal electrode layer21and the second internal electrode layer22preferably includes a metal such as Ni, Cu, Ag, Pd, or Au, or Ag—Pd alloy, for example. Each of the first internal electrode layer21and the second internal electrode layer22may include the same dielectric ceramic material as that of the dielectric ceramic layer20, in addition to the metal.

The dielectric ceramic layer20includes a first dielectric ceramic layer20a, and a second dielectric ceramic layer20b. The first dielectric ceramic layer20ais disposed between the first internal electrode layer21and the second internal electrode layer22. The second dielectric ceramic layer20bis disposed in a region where the internal electrode layers (21and22) are not disposed, between the first dielectric ceramic layers20aprovided opposite to each other with the internal electrode layer (21and22) interposed therebetween.

The first external electrode51is provided on the first end surface15of the multilayer body10and, inFIG.1, includes a portion which extends over a portion of each of the first main surface11, the second main surface12, the first side surface13and the second side surface14. The first external electrode51is connected to the first internal electrode layer21at the first end surface15.

The second external electrode52is provided on the second end surface16of the multilayer body10and, inFIG.1, includes a portion which extends over a portion of each of the first main surface11, the second main surface12, the first side surface13, and the second side surface14. The second external electrode52is connected to the second internal electrode layer22at the second end surface16.

Each of the first external electrode51and the second external electrode52preferably includes a Ni layer including Ni and a ceramic material, for example. The Ni layer is a foundation electrode layer (for example, base electrode layer). Such a Ni layer can be formed by a cofiring method in which firing is performed simultaneously with the first internal electrode layer21and the second internal electrode layer22. The Ni layer is preferably disposed directly on the multilayer body10.

The first external electrode51preferably includes the Ni layer, a first plated layer, and a second plated layer in order from a side of the first end surface15of the multilayer body10. Similarly, the second external electrode52preferably includes the Ni layer, the first plated layer, and the second plated layer in order from a side of the second end surface16of the multilayer body10. The first plated layer is preferably formed by Ni plating, and the second plated layer is preferably formed by Sn plating, for example. Each of the first external electrode51and the second external electrode52may include a conductive resin layer including conductive particles and a resin between the Ni layer and the first plated layer. Examples of the conductive particles in the conductive resin layer include metal particles of Cu, Ag, and Ni.

It should be noted that the Ni layer may be formed by a so-called post-firing method which applies a conductive paste to the end surface of the multilayer body, and then performs firing. In this case, it may be unnecessary for the Ni layer to contain a ceramic material.

Alternatively, each of the first external electrode51and the second external electrode52may include a foundation electrode layer including a metal such as Cu. The foundation electrode layer may be formed by a cofiring method or a post-firing method. Furthermore, the foundation electrode layer may include a plurality of layers.

For example, the first external electrode51may have a four-layer structure including a Cu layer as a foundation electrode layer, a conductive resin layer including conductive particles and a resin, the first plated layer, and the second plated layer in order from a side of the first end surface15of the multilayer body10. Similarly, the second external electrode52may have, for example, a four-layer structure including a Cu layer as a foundation electrode layer, a conductive resin layer including conductive particles and resin, the first plated layer, and the second plated layer in order from a side of the second end surface16of the multilayer body10.

As shown inFIGS.3and4, the dielectric ceramic layer20includes the first dielectric ceramic layer20aand the second dielectric ceramic layer20b. The first dielectric ceramic layer20ais disposed between the first internal electrode layer21and the second internal electrode layer22. The second dielectric ceramic layer20bis disposed in a region where the internal electrode layer is not disposed, between the first dielectric ceramic layers20aprovided opposite to each other with the internal electrode layer interposed therebetween.

As shown inFIGS.2,3and4, the multilayer body10includes an inner layer portion30in which the first internal electrode layer21and the second internal electrode layer22are provided opposite to each other with the dielectric ceramic layer20interposed therebetween, outer layer portions31and32sandwiching the inner layer portion30in the stacking (T) direction, and a third dielectric ceramic layers41and42sandwiching the inner layer portion30, the outer layer portion31, and the outer layer portion32in the width (W) direction. Third dielectric ceramic layers41and42are also referred to as side margin portions. InFIGS.3and4, the inner layer portion30is a region sandwiched between the first internal electrode layer21closest to the first main surface11and the first internal electrode layer21closest to the second main surface12along the stacking (T) direction. Although not shown, each of the outer layer portion31and the outer layer portion32preferably includes a plurality of dielectric ceramic layers20stacked in the stacking (T) direction, and more preferably includes the first dielectric ceramic layer20a.

The thickness of each of the outer layer portions31and32is preferably about 15 μm or more and about 40 μm or less, for example. It should be noted that each of the outer layer portions31and32may have a single layer structure rather than a multi-layered structure.

As shown inFIG.4, each of the third dielectric ceramic layer41and the third dielectric ceramic layer42may include a plurality of dielectric ceramic layers stacked in the width (W) direction. Among the plurality of dielectric ceramic layers of the third dielectric ceramic layers, the innermost layer in the width direction is referred to as an inner layer, and the outermost layer is referred to as an outer layer. The inner layer and the outer layer have an interface therebetween. InFIG.4, the third dielectric ceramic layer41preferably has, as the dielectric ceramic layer, a two-layer structure including an inner layer41adisposed innermost of the multilayer body10, and an outer layer41bdisposed outermost of the multilayer body10. Similarly, the third dielectric ceramic layer42preferably has, as the dielectric ceramic layer, a two-layer structure including an inner layer42adisposed innermost of the multilayer body10, and an outer layer42bdisposed outermost of the multilayer body10. It should be noted that the third dielectric ceramic layer is not limited to a two-layer structure, and may have a structure including three or more layers. In a case in which the third dielectric ceramic layer includes three or more dielectric ceramic layers, the dielectric ceramic layer disposed innermost in the width direction is the inner layer, and the dielectric ceramic layer disposed outermost in the width direction is the outer layer. Furthermore, the number of layers of the third dielectric ceramic layer of the first side surface side of the multilayer body may be different from that of the third dielectric ceramic layer of the second side surface side of the multilayer body.

In a case in which the third dielectric ceramic layer is a two-layer structure including an inner layer and an outer layer, due to the difference in sinterability in the inner layer and the outer layer, it is possible to confirm the two-layer structure and the interface between the layers by observing with an optical microscope in a dark field. The same applies to a case where the third dielectric ceramic layer has a structure including three or more layers.

The first dielectric ceramic layer20a, the second dielectric ceramic layer20b, and the third dielectric ceramic layers41and42are, for example, made of a dielectric ceramic material mainly including BaTiO3or the like. The dielectric ceramic layer20of the inner layer portion30may further include a sintering aid element.

The dielectric ceramic layer of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer may include ceramic grains. Details of the diameter of the ceramic grains will be described later.

In the multilayer ceramic capacitor according to the present preferred embodiment, the composition of at least one dielectric ceramic layer among the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer is different from the composition of the other dielectric ceramic layers. The first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer each have a different arrangement purpose or different characteristics required for the manufacturing method. Therefore, by setting the composition of at least one dielectric ceramic layer among the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer to be different from the composition of the other dielectric ceramic layers, it is possible to achieve an optimum composition according to the location where the dielectric ceramic layer is disposed, making it possible to increase the reliability.

In the multilayer ceramic capacitor according to the present preferred embodiment, the composition of the first dielectric ceramic layer may be different from the compositions of the second dielectric ceramic layer and the third dielectric ceramic layer, the composition of the second dielectric ceramic layer may be different from the compositions of the first dielectric ceramic layer and the third dielectric ceramic layer, the composition of the third dielectric ceramic layer may be different from the compositions of the first dielectric ceramic layer and the second dielectric ceramic layer, and the composition of the first dielectric ceramic layer, the composition of the second dielectric ceramic layer, and the composition of the third dielectric ceramic layer may be different from one another.

In the multilayer ceramic capacitor of the present preferred embodiment, the composition of the second dielectric ceramic layer and the composition of the third dielectric ceramic layer are preferably different from each other, and the composition of the first dielectric ceramic layer, the composition of the second dielectric ceramic layer, and the composition of the third dielectric ceramic layer are preferably different from one another.

It should be noted that, in a case in which the third dielectric ceramic layer includes a plurality of dielectric ceramic layers, the plurality of dielectric ceramic layers of the third dielectric ceramic layer may be the same composition relative to each other, or may be different compositions from each other. In a case in which any one composition of the plurality of dielectric ceramic layers of the third dielectric ceramic layer is different from that of the first dielectric ceramic layer, it can be recognized that the composition of the third dielectric ceramic layer is different from the composition of the first dielectric ceramic layer. Furthermore, in a case in which any one composition of the plurality of dielectric ceramic layers of the third dielectric ceramic layer is different from that of the second dielectric ceramic layer, it can be recognized that the composition of the third dielectric ceramic layer is different from the composition of the second dielectric ceramic layer.

Among the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer, it is preferable for the dielectric ceramic layers having different compositions to have common main components and different types of additives. Examples of the main component include BaTiO3, CaTiO3, and SrTiO3. The additives preferably include elements such as Si, Mg, Mn, Sn, Cu, rare earth, Ni and Al, for example. The first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer may include two or more of the above elements.

It should be noted that “the same composition” means that the types of elements included in the dielectric ceramics included in each dielectric ceramic layer are the same, and the content (molar ratio) of all other elements based on Ti is within ±about 0.5%. It should be noted that the difference in diameter of the ceramic grains included in each dielectric ceramic layer, and the difference in porosity shall not be included in the difference in the composition of the dielectric ceramic layer.

The composition of each of the dielectric ceramic layers can be determined by performing an elemental analysis by wavelength dispersive X-ray analysis (WDX) or transmission electron microscopy-energy dispersive X-ray analysis (TEM-EDX) on an exposed cut surface of a dielectric ceramic layer made by cutting a multilayer ceramic capacitor. At this time, the composition of each dielectric ceramic layer is measured at five locations to determine the average value. The composition of the second dielectric ceramic layer is measured at five locations from the second dielectric ceramic layer exposed on the first end surface of the multilayer body, and at five locations from the second dielectric ceramic layer exposed on the second end surface of the multilayer body to determine the average value. In a case in which the third dielectric ceramic layer has a multi-layered structure, the composition thereof is the sum of the compositions obtained by multiplying the compositions obtained by measuring the composition of each of the layers at five locations with the ratio of the thickness of each of the layers occupied in the third dielectric ceramic layer. It should be noted that, when segregation of elements is observed in the vicinity of the interface with the other dielectric ceramic layer or the internal electrode layer, the portion where segregation of elements is observed shall not be the measurement target of WDX.

The element to be added to the first dielectric ceramic layer is preferably Mg, for example. The content of Mg in the first dielectric ceramic layer is preferably about 0.05 mol % or more and about 3.0 mol % or less, for example, with respect to 100 moles of Ti. The content of Mg in the first dielectric ceramic layer is more preferably less than the content of Mg in the second dielectric ceramic layer and the third dielectric ceramic layer. When the content of Mg in the first dielectric ceramic layer is small, since the relative dielectric constant of the first dielectric ceramic layer is increased, it is possible to improve the capacitance of the multilayer ceramic capacitor. It should be noted that the content of Mg in the first dielectric ceramic layer may preferably be as low as possible.

The element to be added to the second dielectric ceramic layer is preferably Sn, for example. The content of Sn in the second dielectric ceramic layer is preferably about 0.05 mol % or more, and about 3.0 mol % or less, for example, with respect to 100 moles of Ti. The content of Sn in the second dielectric ceramic layer is preferably greater than the content of Sn in the first dielectric ceramic layer and the third dielectric ceramic layer.

The element to be added to the third dielectric ceramic layer is preferably Si, for example. The content of Si in the third dielectric ceramic layer is preferably about 0.05 mol % or more, and about 5.0 mol % or less, for example, with respect to 100 moles of Ti. The content of Si in the third dielectric ceramic layer is preferably greater than the content of Si in the first dielectric ceramic layer and the second dielectric ceramic layer. When the content of Si in the third dielectric ceramic layer is large, since the sinterability of the dielectric ceramic layer is increased, it is possible to reduce or prevent the internal electrode layer from being deteriorated due to the intrusion of water or the like from the first side surface and the second side surface of the multilayer body.

The element to be added to the third dielectric ceramic layer is preferably Mg, for example. The content of Mg in the third dielectric ceramic layer is preferably about 0.05 mol % or more and about 5.0 mol % or less, for example with respect to 100 moles of Ti. The content of Mg in the third dielectric ceramic layer is preferably greater than the content of Mg in the first dielectric ceramic layer and the second dielectric ceramic layer. When the content of Mg in the third dielectric ceramic layer is large, it is possible to reduce or prevent the grain growth of the ceramic grains included in the third dielectric ceramic layer, and it is possible to reduce or prevent a short circuit between the internal electrode layers.

The element to be added to the third dielectric ceramic layer is preferably Mn, for example. The content of Mn in the third dielectric ceramic layer is preferably about 0.01 mol % or more, and about 3.0 mol % or less, for example, with respect to 100 moles of Ti. The content of Mn in the third dielectric ceramic layer is preferably greater than the content of Mn in the first dielectric ceramic layer and the second dielectric ceramic layer. When the content of Mn in the third dielectric ceramic layer is large, it is possible to reduce or prevent the grain growth of the ceramic grains included in the third dielectric ceramic layer, and it is possible to reduce or prevent a short circuit between the internal electrode layers.

In the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer, elements other than the main component included in each dielectric ceramic layer are preferably diffused into the other dielectric ceramic layers. Furthermore, a portion of the elements included as an additive in the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer is preferably diffused into the adjacent other dielectric ceramic layers and the internal electrode layers.

FIG.5is a cross-sectional view taken along line B-B of the multilayer ceramic capacitor shown inFIG.1. It should be noted thatFIG.5is an LW cross-section of the multilayer ceramic capacitor1. As shown inFIG.5, the second internal electrode layer22is exposed on the second end surface16of the multilayer body10, and the second dielectric ceramic layer20bis exposed on the first end surface15of the multilayer body10. Furthermore, the third dielectric ceramic layer41and the third dielectric ceramic layer42are respectively disposed on the first side surface13side and the second side surface14side of the multilayer body10.

As shown inFIG.5, there is an interface2220bbetween the second internal electrode layer22and the second dielectric ceramic layer20b. Furthermore, there are interfaces2241and2242between the second internal electrode layer22and the third dielectric ceramic layers41and42. Furthermore, there are interfaces20b41and20b42between the second dielectric ceramic layer20band the third dielectric ceramic layers41and42.

In addition, although not shown inFIG.5, the first dielectric ceramic layer20ais disposed on both sides in the thickness direction of the second internal electrode layer22and the second dielectric ceramic layer20b. Therefore, it can be recognized that the first dielectric ceramic layer20aincludes an interface in direct contact with the second dielectric ceramic layer20b, the third dielectric ceramic layers41and42, and the internal electrode layers21and22.

Furthermore, similarly to the second internal electrode layer22shown inFIG.5, the first internal electrode layer21also includes an interface in direct contact with the first dielectric ceramic layer20a, the second dielectric ceramic layer20b, and the third dielectric ceramic layers41and42.

In the first dielectric ceramic layer20a, elements derived from the second dielectric ceramic layer20bmay be segregated in the vicinity of the interface with the second dielectric ceramic layer20b. Furthermore, in the first dielectric ceramic layer20a, elements originating from the third dielectric ceramic layer41or42may be segregated in the vicinity of the interface with the third dielectric ceramic layer41or42.

In the second dielectric ceramic layer20b, elements originating from the first dielectric ceramic layer20amay be segregated in the vicinity of the interface with the first dielectric ceramic layers20a. Furthermore, in the second dielectric ceramic layer20b, elements originating from the third dielectric ceramic layer41or42may be segregated in the vicinity of the interfaces20b41or20b42with the third dielectric ceramic layer41or42.

In the third dielectric ceramic layers41and42, elements originating from the first dielectric ceramic layer20amay be segregated in the vicinity of the interface with the first dielectric ceramic layer20a. Furthermore, in the third dielectric ceramic layers41and42, elements originating from the second dielectric ceramic layer20bmay be segregated in the vicinity of the interfaces20b41and20b42with the second dielectric ceramic layer20b.

In the first internal electrode layer21and the second internal electrode layer22, elements originating from the first dielectric ceramic layer20amay be segregated in the vicinity of the interface with the first dielectric ceramic layer20a. In addition, in the first internal electrode layer21and the second internal electrode layer22, elements originating from the second dielectric ceramic layer20bmay be segregated in the vicinity of the interface2220bwith the second dielectric ceramic layer20b. Furthermore, in the first internal electrode layer21and the second internal electrode layer22, elements originating from the third dielectric ceramic layers41and42may be segregated in the vicinity of the interfaces2241and2242with the third dielectric ceramic layers41and42. In addition, both the element originating from the second dielectric ceramic layer20band the element originating from the third dielectric ceramic layer41or42may be segregated in the vicinity of the portion where the interface2220bbetween the second internal electrode layer22and the second dielectric ceramic layer20b, and the interface2241or2242between the second internal electrode layer22, and the third dielectric ceramic layer41or42are in contact with each other (the corner of the second internal electrode layer22on the first end surface15side).

The porosity of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer may be the same as, or may be different from one another. A multilayer ceramic capacitor is cut, and the cut surface, which exposes each dielectric ceramic layer, is observed by a scanning electron microscope (SEM) at 20,000 times magnification. An area having a visual field size of about 6.3 μm×about 4.4 μm is photographed at five locations so that the areas do not overlap each other, and the ratio of the area occupied by the voids to the entire visual field is calculated as the porosity by image analysis from each of the obtained SEM images, and an average value in the five visual fields is obtained. However, in a case in which the third dielectric ceramic layer includes a plurality of layers, the porosity of the third dielectric ceramic layer is calculated as the sum of the product of porosity of each layer and the value obtained by dividing the thickness of the layer by the thickness of the third dielectric ceramic layer after obtaining the porosity of each layer individually.

The first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer preferably include ceramic grains. When the dielectric ceramic layer includes ceramic grains, interfacial resistance occurs at the interface between the ceramic grains, a result of which the insulation resistance between the internal electrode layers increases, making it possible to reduce or prevent the occurrence of a short circuit.

A rare earth element is preferably present at the interface of the ceramic grains. The presence of a rare earth element at the interface of the ceramic grains can be confirmed by elemental analyses with TEM-EDX. Examples of the rare earth elements include La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and Y. The presence of a rare earth element at the interface of the ceramic grains allows for further increase of the interfacial resistance of the dielectric ceramic layer, as a result of which it is possible to further improve the reliability of the multilayer ceramic capacitor. It should be noted that Mg, Mn, Si or the like may also be present.

The rare earth element is preferably present in an amount of about 0.2 mol % or more and about 5 mol % or less, for example, with respect to 100 moles of Ti. Herein, 100 moles of Ti defines the amount of rare earth element with respect to 100 moles of Ti on the assumption that the dielectric ceramic material of the dielectric ceramic layers has a compound having a perovskite structure (structure represented by ABO3, B=Ti) as a main component. The amount of rare earth element can be confirmed by TEM-EDX.

In the multilayer ceramic capacitor, the thickness of each of the first internal electrode layer and the second internal electrode layer is preferably about 0.4 μm or less, for example. Furthermore, the thickness of each of the first internal electrode layer and the second internal electrode layer is preferably about 0.38 μm or less, for example. Furthermore, the thickness of each of the first internal electrode layer and the second internal electrode layer is preferably about 0.25 μm or more, for example.

The thickness of the first dielectric ceramic layer is preferably about 0.55 μm or less, for example. Furthermore, the thickness of the first dielectric ceramic layer is preferably about 0.4 μm or more, for example.

The thickness of the second dielectric ceramic layer is preferably the same or substantially the same as the thickness of the internal electrode layer.

The thickness of each of the third dielectric ceramic layers41and42is preferably about 5 μm or more and about 40 μm or less, and more preferably about 5 μm or more and about 20 μm or less, for example. The thicknesses of the third dielectric ceramic layers41and42are preferably the same or substantially the same. However, the outer layer41bis preferably thicker than the inner layer41a, while the inner layer41aand the outer layer41bsatisfy the above range. Similarly, the outer layer42bis preferably thicker than the inner layer42a, while the inner layer42aand the outer layer42bsatisfy the above range.

From the viewpoint of maintaining the shape and performance of the multilayer ceramic capacitor1, the inner layer41ais preferably thinner than the outer layer41b. Similarly, the inner layer42ais preferably thinner than the outer layer42b.

The thickness of each of the inner layers41aand42ais preferably about 0.1 μm or more and about 20 μm or less, for example. The inner layers41aand42apreferably have the same or substantially the same thickness.

The thickness of each of the outer layers41band42bis preferably about 5 μm or more and about 20 μm or less, for example. The outer layers41band42bhave preferably the same or substantially the same thickness.

The thickness of each ceramic layer of the side margin portion indicates an average value when the thickness of the third dielectric ceramic layer along the stacking (T) direction is measured at a plurality of locations.

Method for Manufacturing a Multilayer Ceramic Capacitor

A method for manufacturing a multilayer ceramic capacitor according to a preferred embodiment of the present invention includes preparing a green chip, the green chip including a multilayer structure including a plurality of first dielectric ceramic layers, a plurality of second dielectric ceramic layers, and a plurality of pairs of first internal electrode layers and second internal electrode layers in an unfired state, the first internal electrode layers and the second internal electrode layers being exposed on a first side surface and a second side surface on opposite sides in a width direction orthogonal or substantially orthogonal to a stacking direction; forming an unfired third dielectric ceramic layer on the first side surface and the second side surface of the green chip, and thus fabricating an unfired multilayer body; and firing the unfired multilayer body, in which the preparing of the green chip further includes stacking a ceramic green sheet obtained by forming an unfired first internal electrode layer or an unfired second internal electrode layer on a surface of the unfired first dielectric ceramic layer and forming an unfired second dielectric ceramic layer in a region where the first internal electrode layer and the second internal electrode layer are not provided, in which the fabricating the unfired multilayer body further includes forming an unfired side margin portion by forming an unfired inner layer on the first side surface and the second side surface and forming an unfired outer layer on an outermost side, and in which a composition of at least one dielectric ceramic layer among the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer is different from that of the other dielectric ceramic layers.

A non-limiting example of a method for manufacturing the multilayer ceramic capacitor1shown inFIG.1will be described below.

First, a ceramic green sheet is prepared which is to be provided with the first dielectric ceramic layer20a, the second dielectric ceramic layer20b, and the third dielectric ceramic layers41and42. The ceramic green sheet includes a binder, a solvent, and the like, in addition to a ceramic raw material including the dielectric ceramic material described above. Furthermore, an additive including a rare earth element may be added to the ceramic raw material. By changing the element included in the additive, the compositions of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer can be changed. The ceramic raw materials as a main component are preferably the same or substantially the same. The ceramic green sheet is molded using, for example, a die coater, a gravure coater, a micro gravure coater, or the like, on a carrier film.

FIGS.6,7, and8are plan views schematically showing an example of a ceramic green sheet.FIGS.6,7, and8respectively show a first ceramic green sheet101for forming the inner layer portion30, a second ceramic green sheet102for forming the inner layer portion30, and a third ceramic green sheet103for forming the outer layer portion31or32.

InFIGS.6,7, and8, the first ceramic green sheet101, the second ceramic green sheet102, and the third ceramic green sheet103are not separated into each multilayer ceramic capacitor1. InFIGS.6,7, and8, the cutting lines X and Y at the time of separating into each multilayer ceramic capacitor1are shown. The cutting line X is parallel or substantially parallel to the length (L) direction, and the cutting line Y is parallel or substantially parallel to the width (W) direction.

As shown inFIG.6, in the first ceramic green sheet101, an unfired first internal electrode layer121corresponding to the first internal electrode layer21is formed on an unfired first dielectric ceramic layer120acorresponding to the first dielectric ceramic layer20a. Furthermore, an unfired second dielectric ceramic layer120bcorresponding to the second dielectric ceramic layer20bis formed in a region where the unfired first internal electrode layer121is not formed. The unfired first dielectric ceramic layer120aand the unfired second dielectric ceramic layer120balso refer to an unfired dielectric ceramic layer120corresponding to the dielectric ceramic layer20.

As shown inFIG.7, in the second ceramic green sheet102, an unfired second internal electrode layer122corresponding to the second internal electrode layer22is formed on the unfired first dielectric ceramic layer120acorresponding to the first dielectric ceramic layer20a. Furthermore, the unfired second dielectric ceramic layer120bcorresponding to the second dielectric ceramic layer20bis formed in a region where the unfired second internal electrode layer122is not formed. The unfired first dielectric ceramic layer120aand the unfired second dielectric ceramic layer120balso refer to the unfired dielectric ceramic layer120corresponding to the dielectric ceramic layer20.

The method for fabricating the first ceramic green sheet101shown inFIG.6and the second ceramic green sheet shown inFIG.7is not particularly limited. However, examples thereof include a method for applying a dielectric paste as the mixture of a dielectric ceramic and a solvent, which becomes the second dielectric ceramic layer20bby firing, and a conductive paste, which becomes the internal electrode layer21or22by firing, respectively to predetermined regions of the surface of the unfired first dielectric ceramic layer120a. The order in which the dielectric paste and the conductive paste are applied is not particularly limited, and the conductive paste may be applied after the dielectric paste is applied first, or the dielectric paste may be applied after the conductive paste is applied first. In addition, the dielectric paste and the conductive paste may be applied so that a portion of the surface of the paste applied previously is covered with a portion of the paste applied later.

As shown inFIG.8, the third ceramic green sheet103corresponding to the outer layer portion31or32includes the unfired first dielectric ceramic layer120acorresponding to the first dielectric ceramic layer, and neither the unfired internal electrode layer121or122nor the unfired second dielectric ceramic layer120bis formed.

The first internal electrode layer121and the second internal electrode layer122can be formed using any conductive paste. For example, a screen-printing method, a gravure printing method, or the like can be used for forming the first internal electrode layer121and the second internal electrode layer122using the conductive paste.

The first internal electrode layer121and the second internal electrode layer122are disposed over two regions which are partitioned by the cutting line Y and are adjacent to each other in the length (L) direction, and extend in a strip shape in the width (W) direction. The regions partitioned by the cutting line Y of the first internal electrode layer121and the second internal electrode layer122are shifted from each other in the length (L) direction by one row. That is, the cutting line Y passing through the center of the first internal electrode layer121passes through a region between the second internal electrode layers122(i.e., the center of the second dielectric ceramic layer120b), and the cutting line Y passing through the center of the second internal electrode layer122passes through the region between the first internal electrode layers121(i.e., the center of the second dielectric ceramic layer120b).

Thereafter, the first ceramic green sheet101, the second ceramic green sheet102, and the third ceramic green sheet103are stacked, thus fabricating a mother block.

FIG.9is an exploded perspective view schematically showing an example of the mother block. InFIG.9, for convenience of explanation, the first ceramic green sheet101, the second ceramic green sheet102, and the third ceramic green sheet103are shown in an exploded manner. However, in an actual mother block104, the first ceramic green sheet101, the second ceramic green sheet102, and the third ceramic green sheet103are integrally crimped by hydrostatic pressing, or the like, for example.

In the mother block104shown inFIG.9, the first ceramic green sheet101and the second ceramic green sheet102corresponding to the inner layer portion30are alternately stacked in the stacking (T) direction. Furthermore, the third ceramic green sheets103corresponding to the outer layer portions31and32are stacked on the upper and lower surfaces in the stacking (T) direction of the first ceramic green sheets101and the second ceramic green sheets102which are alternately stacked. It should be noted that, although the third ceramic green sheet103is configured such that three pieces of the first dielectric ceramic layer120aare stacked inFIG.9, the number of first dielectric ceramic layers120ato be stacked can be changed as appropriate.

By cutting the resulting mother block104along the cutting lines X and Y (refer toFIGS.6,7, and8), a plurality of green chips are fabricated. For this cutting, a method such as dicing, push cutting, or laser cutting is applied, for example.

FIG.10is a perspective view schematically showing an example of a green chip. The green chip110shown inFIG.10has a multilayer structure including the plurality of first dielectric ceramic layers120aand the plurality of second dielectric ceramic layers120b, and the plurality of pairs of first internal electrode layers121and second internal electrode layers122in an unfired state. A first side surface113and a second side surface114of the green chip110are planes provided by cutting along the cutting line X, and a first end surface115and a second end surface116are planes provided by cutting along the cutting line Y. The first internal electrode layer121and the second internal electrode layer122are exposed on the first side surface113and the second side surface114. Furthermore, only the first internal electrode layers121and the second dielectric ceramic layer120bare exposed on the first end surface115, and only the second internal electrode layer122and the second dielectric ceramic layer120bare exposed on the second end surface116. The first dielectric ceramic layer120ais exposed on the first side surface113, the second side surface114, the first end surface115, and the second end surface116. However, the locations of the second dielectric ceramic layers that are exposed in a region to be disposed differ. In other words, the second dielectric ceramic layers120bdisposed at a side of the first end surface115is not exposed on the second end surface116, and the second dielectric ceramic layer120bdisposed at a side of the second end surface116is not exposed on the first end surface115.

An unfired third dielectric ceramic layer is formed on the first side surface113and the second side surface114of the resulting green chip110, as a result of which an unfired multilayer body is fabricated. The unfired third dielectric ceramic layer is formed, for example, by pasting a ceramic green sheet made of a dielectric ceramic on the first side surface and the second side surface of the green chip.

For example, in a case in which the third dielectric ceramic layer includes two layers of the inner layer and the outer layer, first, in order to fabricate a ceramic green sheet for the inner layer, a ceramic slurry is produced which includes a binder, a solvent, and the like, in addition to the ceramic raw material including a dielectric ceramic material mainly including BaTiO3or the like. Si as a sintering aid may be added to the ceramic slurry for the inner layer. The inner layer has a function of adhering to the green chip110. In addition, a liquid phase metal may be added to the ceramic slurry for the inner layer, and more rare earth elements, Mg, and Mn may be added to the ceramic slurry for the inner layer than to the ceramic green sheet for forming the inner layer portion. Thus, it is possible to reduce or prevent the grain growth of the ceramic grains included in the dielectric ceramic layer sandwiched by the width direction ends of the internal electrode layers.

Next, in order to fabricate a ceramic green sheet for the outer layer, a ceramic slurry including a binder, a solvent, and the like in addition to a ceramic raw material including a dielectric ceramic material including BaTiO3or the like as a main component is produced. In addition, Si as a sintering aid may be added to the ceramic slurry for the outer layer. Furthermore, Si included in the ceramic green sheet for the inner layer is preferably larger than Si included in the ceramic green sheet for the outer layer. The degree of the content is determined based on the size of the area of a region where Si is detected, by imaging the cross-section by WDX.

The ceramic slurry for the outer layer is applied to the surface of a resin film and dried, such that the ceramic green sheet for the outer layer is formed. The ceramic slurry for the inner layer is applied to the surface of the ceramic green sheet for the outer layer on the resin film and dried, such that the ceramic green sheet for the inner layer is formed. As described above, a ceramic green sheet having a two-layer structure is obtained.

It should be noted that the ceramic green sheet having the two-layer structure can also be obtained, for example, by forming the ceramic green sheet for the outer layer and the ceramic green sheet for the inner layer in advance, and then bonding them to each other. Furthermore, the ceramic green sheet is not limited to the two-layer structure, and may have a structure with three or more layers.

Thereafter, the ceramic green sheet is peeled from the resin film.

Subsequently, the ceramic green sheet for the inner layer of the ceramic green sheet and the first side surface113of the green chip110are made to face each other, and pressed and punched, thus forming the unfired side margin portion41. Furthermore, the ceramic green sheets for the inner layer of the ceramic green sheet and the second side surface114of the green chip110are also made to face each other, and pressed and punched, thus forming the unfired side margin portion42. At this time, an organic solvent defining and functioning as an adhesive is preferably applied to the side surface of the green chip in advance. As described above, an unfired multilayer body is obtained.

It is preferable to perform barrel polishing or the like, for example, on the unfired multilayer body obtained by the above method. By polishing the unfired multilayer body, the corners and ridges of a fired multilayer body10are rounded.

Thereafter, in the unfired multilayer body, a conductive paste for an external electrode including Ni and a ceramic material is applied on each end surface of the first end surface115and the second end surface116of the green chip110.

The conductive paste for the external electrode preferably includes, as a ceramic material, the same or substantially the same dielectric ceramic material as the first dielectric ceramic layer, the second dielectric ceramic layer, or the outer layer. The content of the ceramic material in the conductive paste for the external electrodes is preferably about 15% by weight or more, for example. Furthermore, the content of the ceramic material in the conductive paste for the external electrode is preferably about 25% by weight or less, for example.

Next, the unfired multilayer body to which the conductive paste for the external electrode is subjected to, for example, a degreasing treatment in a nitrogen atmosphere under a predetermined condition, and then the resulting multilayer body is fired at a predetermined temperature in a nitrogen-hydrogen-water vapor mixed atmosphere. Thus, the unfired multilayer body and the conductive paste for the external electrode are fired simultaneously, and the multilayer body10, the Ni layer connected to the first internal electrode layer21, and the Ni layer connected to the second internal electrode layer22are formed at the same time by a cofiring method. Thereafter, the first plated layer including Ni plating and the second plated layer including Sn plating are stacked in this order on the surface of each of the Ni layer. Thus, the first external electrode51and the second external electrode52are formed.

It should be noted that on the multilayer body10, the first external electrode51and the second external electrode52may be formed at separate timings by a post-firing method. Specifically, first, a multilayer body10is formed by performing a degreasing treatment on an unfired laminate under a predetermined condition in a nitrogen atmosphere, for example, and then firing the multilayer body at a predetermined temperature in a nitrogen-hydrogen-water vapor mixed atmosphere. Then, on each end surface of the first end surface15and the second end surface16of the multilayer body10, a conductive paste including Cu powder is applied and baked. Thus, a foundation electrode layer connected to the first internal electrode layer21and a foundation electrode layer connected to the second internal electrode layer22are formed. Then, on the surface of each of the underlying electrode layer, conductive particles (e.g., Cu, Ag, Ni, metal particles such as) and a conductive resin layer including a resin, a first plated layer including Ni plating, and a second plated layer including Sn plating are laminated in this order. Thus, the first external electrode51and the second external electrode52are formed.

Thus, the multilayer ceramic capacitor1is manufactured.

In the preferred embodiment described above, the unfired third dielectric ceramic layer preferably is formed on both sides of the green chip after obtaining the plurality of green chips by cutting the mother block104along the cutting lines X and Y, for example. However, the following modifications are also possible.

That is, it may be configured such that a plurality of rod-shaped green block bodies are obtained which are provided by cutting the mother block along only the cutting line X and in which the first internal electrode layer and the second internal electrode layer are exposed on the side surface provided by cutting along the cutting line X, and thereafter, the unfired third dielectric ceramic layer is formed on both sides of the green block bodies to obtain a plurality of unfired multilayer bodies by cutting along the cutting line Y, followed by the unfired multilayer bodies being fired. By performing the same steps as in the above-described preferred embodiment after firing, a multilayer ceramic capacitor can be manufactured.

Preferred embodiments of the present invention further include the following configurations of (1) to (7).

(1) Alloy Portion Between the Dielectric Ceramic Layer and the Internal Electrode Layer and the External Electrode

In a multilayer ceramic capacitor1according to a preferred embodiment of the present invention, as shown inFIG.11, a second alloy portion320is provided between the second dielectric ceramic layer20band the first internal electrode layer21, and between the second dielectric ceramic layer20band the second internal electrode layer22, respectively. Furthermore, in the multilayer ceramic capacitor1, a first alloy portion310is provided between the first dielectric ceramic layer20aand the first internal electrode layer21, and between the first dielectric ceramic layer20aand the second internal electrode layer22, respectively.

As shown inFIG.12, metal elements321aare segregated at the interface2220bwith the second dielectric ceramic layer20bin the second internal electrode layer22. The second alloy portion320includes a segregation layer321which is a layer segregation by the metal elements321a. Similarly to this, the metal elements321aare segregated to provide the segregation layer321also at the interface2220bwith the second dielectric ceramic layer20bin the first internal electrode layer21, and the second alloy portion320by the segregation layer321is provided. The second alloy portion320is provided on the surfaces of the first internal electrode layer21and the second internal electrode layer22closer to the second dielectric ceramic layer20b, respectively. The second alloy portion320is provided between the first internal electrode layer21and the second dielectric ceramic layer20b, and between the second internal electrode layer22and the second dielectric ceramic layer20b.

Furthermore, as shown inFIG.12, metal elements311aare segregated at an interface2220awith the first dielectric ceramic layer20ain the second internal electrode layer22. The first alloy portion310includes a segregation layer311which is a layer segregation by the metal element311a. Similarly to this, the metal elements311aare segregated to provide the segregation layer311at the interface2220awith the first dielectric ceramic layer20ain the first internal electrode layer21, and the first alloy portion310by the segregation layer311is provided. The first alloy portion310is provided on the surfaces of the first internal electrode layer21and the second internal electrode layer22closer to the first dielectric ceramic layer20a, respectively. The first alloy portion310is provided between the first internal electrode layer21and the first dielectric ceramic layer20a, and between the second internal electrode layer22and the first dielectric ceramic layer20a.

There are a plurality of types of segregated metal elements321ain the second alloy portion320. The plurality of types of metal elements321ain the segregation layer321includes a metal element provided in a greatest amount among the metal elements of the first internal electrode layer21and the second internal electrode layer22, and an element derived from the second dielectric ceramic layer20b. Furthermore, the same applies to the segregated metal element311aof the first alloy portion310. That is, the metal element311aincludes a metal element provided in a greatest amount among the metal elements of the first internal electrode layer21and the second internal electrode layer22, and an element derived from the first dielectric ceramic layer20a.

Examples of the metal element provided in a greatest amount among the metal elements of the first internal electrode layer21and the second internal electrode layer22include one of Ni, Cu, Ag, Pd, Au, and Pt. On the other hand, examples of the element derived from the second dielectric ceramic layer20band the first dielectric ceramic layer20ainclude a metal element as an additive. More specifically, examples thereof include any one or more metal elements among the metal group of Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, Y, and Ge, among which, Sn, Ga, and Ge is particularly preferred. Hereinafter, this metal group may be referred to as a metal group M.

The segregation of the metal element321aoccurs when the metal element included in the second dielectric ceramic layer20bmigrates to the first internal electrode layer21and the second internal electrode layer22during firing of the second dielectric ceramic layer20b. Furthermore, the segregation of the metal element311aoccurs when the metal element included in the first dielectric ceramic layer20amigrates to the first internal electrode layer21and the second internal electrode layer22during firing of the first dielectric ceramic layer20a.

In a case in which the first dielectric ceramic layer20aincludes BaTiO3as a main component, the second alloy portion320has a higher content of metal elements included in the second dielectric ceramic layer20b, i.e. any one or more of the above metal group M in terms of molar ratio relative to 100 moles of Ti, than the first alloy portion310.

FIG.13shows a plane of the multilayer body10including a central portion in the width (W) direction, and the length (L) direction and the stacking (T) direction. In the multilayer ceramic capacitor1, in the plane shown inFIG.13, the first internal electrode layer21includes a plurality of first interspersed internal electrodes210interspersed discontinuously in the length (L) direction at the end in the length (L) direction that is not connected to the second external electrode52. Furthermore, the second internal electrode layer22includes a plurality of second interspersed internal electrodes220interspersed discontinuously in the length (L) direction at the end in the length (L) direction that is not connected to the first external electrode51. Each of the first interspersed internal electrodes210and the second interspersed internal electrodes220is provided within the second dielectric ceramic layer20b. The plurality of first interspersed internal electrodes210may be connected to the first internal electrode layer21while extending in the width (W) direction. Furthermore, the plurality of second interspersed internal electrodes220may also be connected to the second internal electrode layer22while extending in the width (W) direction.

A fourth alloy portion340is provided around each of the first interspersed internal electrode210and the second interspersed internal electrode220. The fourth alloy portion340is defined by a segregation layer341which is a layer segregation by the metal element341a. The metal element341aincludes a metal element provided in a greatest amount among the metal elements of the first internal electrode layer21and the second internal electrode layer22, and one or more kinds of metal elements among the metal group M originating from the second dielectric ceramic layer20b.

The segregation of the metal element341aoccurs when the metal element included in the second dielectric ceramic layer20bmigrates to the first interspersed internal electrode210and the second interspersed internal electrode220during firing of the second dielectric ceramic layer20b. It should be noted that the segregation of the metal element341aoccurs around one or a plurality of the first interspersed internal electrodes210and one or a plurality of the second interspersed internal electrodes220. Alternatively, the segregation of the metal element341amay occur around the entire or substantially the entire periphery of the first interspersed internal electrode210and around the entire or substantially the entire periphery of the second interspersed internal electrode220.

As shown inFIG.14, in the multilayer ceramic capacitor1, a third alloy portion330is provided between the third dielectric ceramic layers41and42and the first internal electrode layer21, and between the third dielectric ceramic layers41and42and the second internal electrode layer22, respectively.

As shown inFIG.14, a metal element331ais segregated at an interface2220cbetween the first internal electrode layer21and the third dielectric ceramic layers41and42. Furthermore, the metal element331ais also segregated at the interface2220cwith the third dielectric ceramic layers41and42in the second internal electrode layer22. The third alloy portion330provided by a layer segregation by the metal element331a, i.e. a segregation layer331. The third alloy portions330are provided on the surfaces of the first internal electrode layer21and the second internal electrode layer22, closer to the third dielectric ceramic layer41and42, respectively. The third alloy portions330are provided between the first internal electrode layer21and the third dielectric ceramic layers41and42, and between the second internal electrode layer22and the third dielectric ceramic layers41and42, respectively.

The metal element331aincludes a metal element provided in a greatest amount among the metal elements of the first internal electrode layer21and the second internal electrode layer22, and one or more kinds of metal elements among the metal group M originating from the third dielectric ceramic layers41and42. Examples of the elements originating from the third dielectric ceramic layers41and42include a metal element as an additive. More specifically, examples thereof include any one or more of metal elements among the above metal group M.

The segregation of the metal element331aoccurs when the metal element included in the third dielectric ceramic layers41and42migrates to the first internal electrode layer21and the second internal electrode layer22during firing of the third dielectric ceramic layers41and42.

In the multilayer ceramic capacitor1, the first external electrode51and the second external electrode52each include a Ni layer as a foundation electrode layer, and, when formed by a cofiring method, as shown inFIG.15, a fifth alloy portion350is formed in the Ni layer.

FIG.15shows a state in which the fifth alloy portion350is provided at an interface51bwith the second dielectric ceramic layer20bin the first external electrode51. The fifth alloy portion350is a segregation layer351which is a layer segregation by a metal element351a. Similarly to this, the fifth alloy portion350due to the segregation of the metal element351ais also provided at the interface51bwith the second dielectric ceramic layer20bin the second external electrode52. The segregation of the metal element351aoccurs when the metal element included in the second dielectric ceramic layer20bmigrates to the first external electrode51and the second external electrode52during firing of the second dielectric ceramic layer20b.

It should be noted that, in the multilayer body10of the multilayer ceramic capacitor1of the present preferred embodiment, the ends of the first internal electrode layer21, the second internal electrode layer22, and the second dielectric ceramic layer20bwhich are adjacent to each other may overlap with each other. For example, as shown inFIG.16, the end of the second dielectric ceramic layer20bmay be superimposed on the end of the second internal electrode layer22. Furthermore, as shown inFIG.17, the end of the second dielectric ceramic layer20bmay overlap the end of the first internal electrode layer21. In such a configuration in which the ends overlap with each other, the first internal electrode layer21and the second internal electrode layer22may be superimposed on the second dielectric ceramic layer20b.

In the multilayer ceramic capacitor1of the present preferred embodiment, the second alloy portion320, which includes one metal element provided in a greatest amount among the metal elements of the internal electrode layer, and any one or more metal elements among the metal group M including Sn, In, Ga, Zn, Bi, Pb, Cu, Ag, Pd, Pt, Ph, Ir, Ru, Os, Fe, V, and Y, is provided between the second dielectric ceramic layer20band the first internal electrode layer21, and between the second dielectric ceramic layer20band the second internal electrode layer22, respectively.

The electric field is likely to be concentrated at the respective ends of the first internal electrode layer21and the second internal electrode layer22in contact with the second dielectric ceramic layer20b. For this reason, there is a possibility of lowering the reliability of a multilayer ceramic capacitor. However, according to the multilayer ceramic capacitor1of the present preferred embodiment, the second alloy portion320is provided between the second dielectric ceramic layer20b, and the first internal electrode layer21and the second internal electrode layer22, such that it is possible to reduce or prevent the electric field concentration, thus improving the reliability.

In the multilayer ceramic capacitor1of the present preferred embodiment, in a case in which the first dielectric ceramic layer20aincludes Ba and Ti, the first alloy portion310, which includes a metal element provided in a greatest amount among the metal elements of the internal electrode layer, and any one or more of metal elements among the above metal group M, is provided between the first dielectric ceramic layer20aand the first internal electrode layer21, and between the first dielectric ceramic layer20aand the second internal electrode layer22, respectively. The second alloy portion320has a higher content of the above metal group M in terms of molar ratio relative to 100 moles of Ti than the first alloy portion310.

Thus, it is possible for the second alloy portion320to reduce or prevent the electric field concentration occurring at a portion in the vicinity of the interfaces with the second dielectric ceramic layer20bin the first internal electrode layer21and the second internal electrode layer22, thus improving the reliability. Furthermore, by increasing the content of the metal group M of the second alloy portion320, which is provided at the ends of the first internal electrode layer21and the second internal electrode layer22in contact with the second dielectric ceramic layer20bwhere electric field concentration is likely to occur, in terms of molar ratio relative to 100 moles of Ti, more than the first alloy portion310provided closer to the first dielectric ceramic layer20a, it is possible to effectively reduce the electric field concentration on the second dielectric ceramic layer20bside, thus further improving the reliability.

By the amount of metal of the metal group M added to each of the first dielectric ceramic layer20aand the second dielectric ceramic layer20bbeing controlled, the thickness of the first alloy portion310and the second alloy portion320, and the concentration of the metal group M included therein can be controlled. For example, when the concentration of the metal group M added to the second dielectric ceramic layer20bis higher than that of the first dielectric ceramic layer20a, as shown inFIG.12, the thickness of the second alloy portion320increases, or the concentration of the metal group M increases as it approaches the second dielectric ceramic layer20b, or in some cases, the thickness of the second alloy portion320increases, and the concentration of the metal group M increases as it approaches the second dielectric ceramic layer20b.

In the multilayer ceramic capacitor1of the present preferred embodiment, in the plane of the multilayer body10including the central portion in the width (W) direction, the length (L) direction, and the stacking (T) direction, the first internal electrode layer21includes the first interspersed internal electrodes210that are discontinuously interspersed in the length (L) direction at the end in the length (L) direction that is not connected to the second external electrode52, the second internal electrode layer22includes the second interspersed internal electrodes220that are discontinuously interspersed in the length (L) direction at the end in the length (L) direction that is not connected to the first external electrode51, and the fourth alloy portion340, which includes a metal element provided in a greatest amount among the metal elements of the internal electrode layer, and any one or more of metal elements among the metal group M, is provided around each of the first interspersed internal electrodes210and the second interspersed internal electrodes220.

When the first intersecting internal electrode210and the second intersecting internal electrode220are respectively connected to the first internal electrode layer21and the second internal electrode layer22while extending in the width (W) direction, if the electric field is concentrated in the connecting portion, breakdown may occur which reduces reliability. However, according to the multilayer ceramic capacitor1of the present preferred embodiment, it is possible for the fourth alloy portion340provided around each of the first interspersed internal electrodes210and the second interspersed internal electrodes220to reduce or prevent breakdown due to electric field concentration, such that it is possible to improve the reliability.

In the multilayer ceramic capacitor1of the present preferred embodiment, the third alloy portion330, which includes a metal element provided in a greatest amount among the metal elements of the internal electrode layer, and any one or more of metal elements among the above metal group M, is provided between the third dielectric ceramic layer41and42and the first internal electrode layer21, and between the third dielectric ceramic layer41and42and the second internal electrode layer22, respectively.

Thus, the electric field concentration is reduced or prevented at the portion in the vicinity of the interfaces with the third dielectric ceramic layers41and42in the first internal electrode layer21and the second internal electrode layer22by the third alloy portion330, thus making it possible to improve the reliability.

In the multilayer ceramic capacitor1of the present preferred embodiment, the first external electrode51and the second external electrode52include Ni, and the fifth alloy portion350in which any one or more of metal elements among the metal group M is segregated in Ni is provided between the second dielectric ceramic layer20b, and the first external electrode51and the second external electrode52.

Thus, even when the interval between the first internal electrode layer21and the second external electrode52, and the interval between the second internal electrode layer22and the first external electrode51, i.e. the distance of the second dielectric ceramic layer20bin the length (L) direction is, for example, as narrow as less than about 15 μm, since the fifth alloy portion350is present, which causes breakdown due to electric field concentration to be less likely to occur between the internal electrode layer and the external electrode, reliability is improved.

Test Example 1

Next, Test Example 1 will be described which verifies the advantageous effects of the first alloy portion310, the second alloy portion320, and the third alloy portion330in the multilayer ceramic capacitor1of the present preferred embodiment.

Regarding TEM Analysis

In the manufacturing method for the multilayer ceramic capacitor of the present preferred embodiment described above, the multilayer body10obtained by firing the green chip110without cofiring the first external electrode51and the second external electrode52is polished from the first side surface13side and the second side surface14side, to obtain a polished body leaving the central portion in the width (W) direction as a test body, as shown inFIG.18. The type and the amount of metal (metal concentration) of the metal elements included in the first alloy portion310were analyzed as follows. As shown inFIG.18, in the central portion of the length (L) direction, an imaginary line OL1orthogonal or substantially orthogonal to the length (L) direction was assumed. Furthermore, the region in which the first dielectric ceramic layer20ain relation to the acquisition of the capacitance of the polished body, and the first internal electrode layer21and the second internal electrode layer22are stacked is equally divided into three regions along the imaginary line OL1in the stacking direction. The three regions include an upper region E1, a center region E2, and a lower region E3. The upper region E1, the center region E2, and the lower region E3are cut out from the polished body, and each of the upper region E1, the center region E2, and the lower region E3is thinned by Ar ion milling or the like, for example, to obtain three thin film samples from each region.

The three thin film samples of the upper region E1, the center region E2, and the lower region E3of the test body obtained as described above were subjected to TEM observation and elemental mapping by EDX attached to the TEM. As a result, since there was no significant difference between the upper region E1and the lower region E3, and the center region E2, the result obtained from the center region E2is regarded as the microstructure including the dielectric ceramic layer and the internal electrode layer. As a result, the type and the amount of metal (metal concentration) of the metal elements included in the first alloy portion310are known. In addition, the type and the amount of metal (metal concentration) of the metal elements included in the second alloy portion320can be analyzed by obtaining a thin film sample in the same or substantially the same manner as described above in the region of one end in the length (L) direction in which the second alloy portion320exists. That is, in the polished body shown inFIG.18, an imaginary line OL2orthogonal or substantially orthogonal to the length (L) direction is assumed at one end in the length (L) direction, to obtain thin film samples of three regions including an upper region E4, a center region E5, and a lower region E6which are provided by dividing into three equal portions along the imaginary line OL2in the stacking direction. Furthermore, the three thin film samples of the upper region E4, the center region E5, and the lower region E6were subjected to TEM observation and element mapping by EDX attached to TEM, to examine the type and the amount of metal (metal concentration) included in the second alloy portion320.

For the second alloy portion and the first alloy portion, the concentration of Sn was examined by analysis with EDX mapping image by a TEM observation image. The TEM measurement points were measured at intervals of about 5 nm to about 10 nm. At the interface between the internal electrode layer and the dielectric ceramic layer, the region obtained three times or more of the observed values than the other measurement points is regarded as the alloy portion, and the average value is regarded as the metal concentration of the alloy portion.

Eighteen multilayer ceramic capacitors were prepared for each of Test Examples 1-1 to 1-5 shown in Table 1. In Test Example 1-2, in the multilayer ceramic capacitor of the present preferred embodiment, the first internal electrode layer21and the second internal electrode layer22were made of Ni, and the same amount of Sn as an additive was added to the first dielectric ceramic layer20aand the second dielectric ceramic layer20b. In Test Examples 1-3 to 1-5, the amount of Sn added to the second dielectric ceramic layer20bwas gradually larger than that in Test Example 1-2. Furthermore, in Test Example 1-1, multilayer ceramic capacitors of the same conditions as those in Test Examples 1-2 to 1-5 were used, except that no Sn was added to the second dielectric ceramic layer20b.

For the multilayer ceramic capacitors of Test Examples 1-1 to 1-5, the determination was made by measuring the resistance value (kΩ) in a state in which a voltage of about 6.3 V was applied in an environment with a room temperature of about 150° C., to examine MTTF (mean failure time). MTTF was determined when the resistance value became about 10 kΩ or less, and if MTTF was about 15.3 hours (hr) or less, it was evaluated as fail, if MTTF was up to about 30 hours beyond about 15.3 hours (hr), it is evaluated as good, and if MTTF was beyond about 30 hours, it was evaluated as excellent. The results are listed in Table 1. It should be noted that, when the coverage of the internal electrode layer is less than about 80%, since the capacitance is difficult to be measured, it was evaluated as unmeasurable.

TABLE 1SnSnCONCENTRATIONCONCENTRATIONOF FIRST ALLOYOF SECOND ALLOYPORTION (at %)PORTION (at %)MTTF(hr)EVALUATIONTEST EXAMPLE1015.3FAIL1-1TEST EXAMPLE1121GOOD1-2TEST EXAMPLE11.121GOOD1-3TEST EXAMPLE11.323GOOD1-4TEST EXAMPLE11.435EXCELLENT1-5

According to Table 1, it is confirmed that, since the second alloy portion was provided, MTTF was beyond the prescribed time of about 15.3 hours, and thus it was evaluated as good, and it is further found that MTTF was better as the Sn concentration was higher. On the other hand, in Test Example 1-1 in which the second alloy portion including Sn was not provided, MTTF could not exceed the prescribed time. Thus, it was confirmed that the second alloy portion improved the reliability of the multilayer ceramic capacitor.

Next, eighteen multilayer ceramic capacitors were prepared for Test Examples 1-6 to 1-9 shown in Table 2, in addition to Test Example 1-1. In Test Example 1-6, Sn as an additive was further added to the third dielectric ceramic layer in the same amount as that added to the first dielectric ceramic layer and the second dielectric ceramic layer in Test Example 1-2. In Test Examples 1-7 to 1-9, the amount of Sn added to the third dielectric ceramic layer was gradually larger than that in Test Examples 1-6. In Test Example 1-1, Sn was not added to the third dielectric ceramic layer.

For Test Examples 1-1 and 1-6 to 1-9, MTTF was determined in the same manner as in Test Examples 1-1 to 1-5. The results are shown in Table 2.

TABLE 2SnSnSnCONCENTRATTONCONCENTRATIONCONCENTRATIONOF FIRST ALLOYOF SECOND ALLOYOF THIRD ALLOYPORTION (at %)PORTION (at %)PORTION (at %)MTTF(hr)EVALUATIONTEST10015.3FAILEXAMPLE1-1TEST11122GOODEXAMPLE1-6TEST11.11.225GOODEXAMPLE1-7TEST11.31.327GOODEXAMPLE1-8TEST11.41.441EXCELLENTEXAMPLE1-9

According to Table 2, it is confirmed that, since the third alloy portion together with the second alloy portion was provided, MTTF is beyond the prescribed time of about 15.3 hours, and thus it was evaluated as good, and it is further found that MTTF was better as the Sn concentration was higher. On the other hand, in Test Example 1-1 in which the second alloy portion and the third alloy portion including Sn were not provided, MTTF could not exceed the prescribed time. Thus, it was confirmed that the second alloy portion and the third alloy portion improved the reliability of the multilayer ceramic capacitor.

(2) Average Particle Size of the Dielectric Particles Included Near Intersection Region

FIG.19shows a plane including the length (L) direction and the width (W) direction of the multilayer ceramic capacitor1of the present preferred embodiment, and a plane including the second dielectric ceramic layer20band the second internal electrode layer22. As shown inFIG.19, both sides of the end closer to the first end surface15in the multilayer ceramic capacitor1in the width (W) direction each include an intersection400of the interface surrounded by the second dielectric ceramic layer20b, the second internal electrode layer22, and the third dielectric ceramic layers41and42. This intersection400is an intersection of the interface2220bbetween the second dielectric ceramic layer20band the second internal electrode layer22, and an inner surface401in the width (W) direction in the third dielectric ceramic layers41and42. Furthermore, similarly to this, both sides closer to the second end surface16in the width (W) direction each include the intersection400of the interface surrounded by the second dielectric ceramic layer20b, the first internal electrode layer21, and the third dielectric ceramic layers41and42.

An inner region of a circle400rhaving a radius of about 5 μm, for example, around the intersection400is defined as a second near intersection region420. An inner region of the circle400rhaving a radius of about 5 μm around the intersection400is defined as a third near intersection region430. The region inside the circle400ralso includes the line of the circle400r. In the following description, the second near intersection region420close to the second dielectric ceramic layer20b, and a third near intersection region430close to the third dielectric ceramic layers41and42may be collectively referred to as a near intersection region440. The inner region of the second near intersection region420includes a portion of the second dielectric ceramic layer20b. The inner region of the third near intersection region430includes a portion of the third dielectric ceramic layers41and42.

In the multilayer ceramic capacitor1of the present preferred embodiment, (A) the average particle size of the dielectric particles included in each near intersection region440is preferably smaller than the average particle size of the dielectric particles included in the first dielectric ceramic layer20a, the dielectric particles included in the second dielectric ceramic layer20b, and the dielectric particles included in the third dielectric ceramic layers41and42.

In addition, in the multilayer ceramic capacitor1of the present preferred embodiment, (B) it is preferable for the ratio of the average particle size of the dielectric particles included in each near intersection region440smaller than the average particle size of the dielectric particles included therein to be about 5% or more smaller, for example.

It should be noted that the average particle size of the dielectric particles included in the second dielectric ceramic layer20bin this case refers to an average particle size of the dielectric particles included in the second dielectric ceramic layer20bin a portion other than the second near intersection region420, and the average particle size of the dielectric particles included in the third dielectric ceramic layers41and42refers to an average particle size of the dielectric particles included in the third dielectric ceramic layers41and42in a portion other than the third near intersection region430.

The multilayer ceramic capacitor1of the present preferred embodiment having the above configuration (A) or (B) preferably further has any of the following configurations of (C) to (I).(C) The difference between the average particle size of the dielectric particles included in the second dielectric ceramic layer20band the average particle size of the dielectric particles included in the third dielectric ceramic layers41and42is within about 5%, for example; the average particle size of the dielectric particles included in the first dielectric ceramic layer20ais larger than the average particle size of the dielectric particles included in the second dielectric ceramic layer20band the average particle size of the dielectric particles included in the third dielectric ceramic layers41and42; and the average particle size of the dielectric particles included in the near intersection region440is smaller than the average particle size of the dielectric particles included in the second dielectric ceramic layer20band the average particle size of the dielectric particles included in the third dielectric ceramic layers41and42.(D) The difference between the average particle size of the dielectric particles included in the first dielectric ceramic layer20aand the average particle size of the dielectric particles included in the second dielectric ceramic layer20bis within about 5%, for example; the average particle size of the dielectric particles included in the third dielectric ceramic layer41and42is smaller than the average particle size of the dielectric particles included in the first dielectric ceramic layer20aand the average particle size of the dielectric particles included in the second dielectric ceramic layer20b; and the average particle size of the dielectric particles included in the near intersection region440is smaller than the average particle size of the dielectric particles included in the third dielectric ceramic layers41and42.(E) The difference between the average particle size of the dielectric particles included in the first dielectric ceramic layer20aand the average particle size of the dielectric particles included in the third dielectric ceramic layer41and42is within about 5%, for example; the average particle size of the dielectric particles included in the second dielectric ceramic layer20bsmaller than the average particle size of the dielectric particles included in the first dielectric ceramic layer20aand the average particle size of the dielectric particles included in the third dielectric ceramic layer41and42; and the average particle size of the dielectric particles included in the near intersection region440is smaller than the average particle size of the dielectric particles included in the second dielectric ceramic layer20b.(F) The difference between the average particle size of the dielectric particles included in the first dielectric ceramic layer20aand the average particle size of the dielectric particles included in the second dielectric ceramic layer20bis within about 5%, for example; the difference between the average particle size of the dielectric particles included in the first dielectric ceramic layer20aand the average particle size of the dielectric particles included in the third dielectric ceramic layers41and42is within about 5%, for example; and the difference between the average particle size of the dielectric particles included in the second dielectric ceramic layer20band the average particle size of the dielectric particles included in the third dielectric ceramic layers41and42is within about 5%, for example, and the average particle size of the dielectric particles included in the near intersection region440is smaller than the average particle size of the dielectric particles included in the first dielectric ceramic layer20a, the average particle size of the dielectric particles included in the second dielectric ceramic layer20b, and the average particle size of the dielectric particles included in the third dielectric ceramic layers41and42.(G) The average particle size of the dielectric particles included in the first dielectric ceramic layer20ais smaller than the average particle size of the dielectric particles included in the second dielectric ceramic layer20b; the average particle size of the dielectric particles included in the third dielectric ceramic layer41and42is smaller than the average particle size of the dielectric particles included in the first dielectric ceramic layer20a; and the average particle size of the dielectric particles included in the near intersection region440is smaller than the average particle size of the dielectric particles included in the third dielectric ceramic layers41and42.(H) The average particle size of the dielectric particles included in the first dielectric ceramic layer20ais smaller than the average particle size of the dielectric particles included in the third dielectric ceramic layer41and42; the average particle size of the dielectric particles included in the second dielectric ceramic layer20bis smaller than the average particle size of the dielectric particles included in the first dielectric ceramic layer20a; and the average particle size of the dielectric particles included in the near intersection region440is smaller than the average particle size of the dielectric particles included in the second dielectric ceramic layer20b.(I) The average particle size of the dielectric particles included in the near intersection region440is smaller than the average particle size of the dielectric particles included in the first dielectric ceramic layer20a; and the average particle size of the dielectric particles included in the third dielectric ceramic layers41and42or the average particle size of the dielectric particles included in the second dielectric ceramic layer20bis smaller than the average particle size of the dielectric particles included in the near intersection region440.

It is possible to control the average particle size of the dielectric particles included in the first dielectric ceramic layer20a, the second dielectric ceramic layer20b, and the third dielectric ceramic layer41and42by adjusting the amount of sintering aid such as Si, Mn, etc., for example, included in the dielectric ceramic slurry forming each dielectric ceramic layer, and further adjusting the firing temperature.

As described above, in the multilayer ceramic capacitor1of the present preferred embodiment, the average particle size of the dielectric particles included in the near intersection region440is smaller than the average particle size of the dielectric particles included in the first dielectric ceramic layer20aand the dielectric particles included in the second dielectric ceramic layer20baround the near intersection region440, and the average particle size of the dielectric particles included in the third dielectric ceramic layer41and42.

The electric field is likely to be concentrated in the near intersection region440, and the occurrence of the electric field concentration may degrade the reliability of a multilayer ceramic capacitor. However, in the multilayer ceramic capacitor1of the present preferred embodiment, the average particle size of the dielectric particles included in the near intersection region440is smaller than the average particle size of the dielectric particles included in each of the first dielectric ceramic layer20a, the second dielectric ceramic layer20b, and the third dielectric ceramic layers41and42therearound. Thus, since the average particle size is small, electric field concentration is reduced or prevented by the presence of many grain boundaries. As a result, it is possible to improve the reliability of a multilayer ceramic capacitor.

Test Example 2

Next, Test Example 2 will be described which verifies that it is superior in that the multilayer ceramic capacitor1of the present preferred embodiment having the average particle size of the dielectric particles included in the near intersection region440which is smaller than the average particle size of the dielectric particles included in each of the first dielectric ceramic layer20aand the third dielectric ceramic layers41and42therearound.

The average particle sizes of the dielectric particles included in each of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer are measured as follows.

Average Particle Size of the Dielectric Particles Included in the First Dielectric Ceramic Layer

In the non-limiting example of a manufacturing method for the multilayer ceramic capacitor of the present preferred embodiment described above, the multilayer body10obtained by firing the green chip110without cofiring the first external electrode51and the second external electrode52is polished from the first end surface15side or the second end surface16side, to obtain a polished body leaving the central portion in the length (L) direction as a test body, as shown inFIG.20. As shown inFIG.20, in the central portion of the width (W) direction, an imaginary line OS1orthogonal or substantially orthogonal to the width (W) direction was assumed. Furthermore, the region in which the first dielectric ceramic layer20ain relation to the acquisition of the capacitance of the polished body, and the first internal electrode layer21and the second internal electrode layer22are stacked was equally divided into three regions along the imaginary line OS1in the stacking direction. The three regions include an upper region F1, a center region F2, and a lower region F3. For each of the regions F1, F2, and F3, the first dielectric ceramic layer20awas imaged with a field size of about 4.3 μm×about 3.2 μm, and for each of the regions F1, F2, and F3, the area was measured by image processing for 20 pieces of dielectric particles. Then, the equivalent circle diameter was calculated from the measured area and averaged to obtain the average particle size. The average particle size was measured in each of the upper region F1, the center region F2, and the lower region F3, and no significant difference was found in the measured values. Therefore, the average particle size of the center region F2is regarded as the average particle size of the first dielectric ceramic layer.

Average Particle Size of the Dielectric Particles Included in the Third Dielectric Ceramic Layer

In the test body shown inFIG.20, an imaginary line is assumed which connects the ends of the plurality of first internal electrode layers21and the plurality of second internal electrode layers22closer to the first side surface13or the second side surface14in the stacking (T) direction.FIG.20shows an imaginary line OS3which connects the ends of the plurality of first internal electrode layers21and the plurality of second internal electrode layers22close to the second side surface14in the stacking (T) direction. As shown inFIG.21, the third dielectric ceramic layer42was imaged from the virtual line OS3at a field size about 4.3 μm×about 3.2 μm in the range of about 5 μm on the third dielectric ceramic layer42side, and for each of the regions F1, F2, and F3, the area was measured by image processing for 20 pieces of dielectric particles. The reference numeral42F inFIG.21indicates an imaging region. Then, the equivalent circle diameter was calculated from the measured area and averaged to obtain the average particle size. The average particle size was measured in each of the upper region F1, the center region F2, and the lower region F3, and no significant difference was found in the measured values. Therefore, the average particle size of the center region F2is regarded as the average particle size of the third dielectric ceramic layer.

Average Particle Size of the Dielectric Particles Included in the Second Dielectric Ceramic Layer

The multilayer body10is polished from the first end surface15side or the second end surface16side, until just before at least one internal electrode layer is exposed. For example, as shown inFIG.22, polishing is performed from the second end surface16side to a surface J immediately before the second internal electrode layer22appears. As shown inFIG.23, in the central portion in the width (W) direction, an imaginary line OS2perpendicular or substantially perpendicular to the width (W) direction was assumed. Then, along the imaginary line OS2, the second dielectric ceramic layer20bwas divided into three equal portions of an upper region G1, a center region G2, and a lower region G3in the stacking direction. For each of the regions G1, G2, and G3, the second dielectric ceramic layer was imaged with a field size of about 4.3 μm×about 3.2 μm, and for each of the regions G1, G2and G3, the area was measured by image processing for 20 pieces of dielectric particles. Then, the equivalent circle diameter was calculated from the measured area and averaged to obtain the average particle size. The average particle size was measured in each of the upper region G1, the center region G2, and the lower region G3, and no significant difference was found in the measured values. Therefore, the average particle size of the center region G2is regarded as the average particle size of the second dielectric ceramic layer.

Average Particle Size of Dielectric Particles Included in the Near Intersection Region

In the test body shown inFIG.23, an imaginary line OS4is assumed which connects the ends of the plurality of first internal electrode layers21and the plurality of second internal electrode layers22closer to the second side surface14in the stacking (T) direction. Then, along the imaginary line OS4, the region on both sides in the width (W) direction of the imaginary line OS4including the near intersection region440was divided into three equal regions in the stacking direction. The three equal region includes an upper region H1, a center region H2, and a lower region H3. As shown inFIG.24, the second dielectric ceramic layer20band the third dielectric ceramic layer42were imaged in a field size of about 4.3 μm×about 3.2 μm in the range of 5 μm in the width (W) direction on both sides of the virtual line OS4, and for each of the regions F1, F2, and F3, the area was measured by image processing for 20 pieces of dielectric particles. Reference numeral42H inFIG.24indicates an imaging region. Then, the equivalent circle diameter was calculated from the measured area and averaged to obtain the average particle size. The average particle size was measured in each of the upper region H1, the center region H2, and the lower region H3, and no significant difference was found in the measured values. Therefore, the average particle size of the center region H2is regarded as the average particle size of the near intersection region440.

Test Examples 2-1 to 2-24 shown in Table 3 were prepared as the multilayer ceramic capacitors corresponding to (C) to (I) described above. Furthermore, for Test Examples 2-25 to 2-27, the average particle size of the dielectric particles included in the near intersection region440was larger than the average particle size of the dielectric particles included in the first dielectric ceramic layer20a, the average particle size of the dielectric particles included in the second dielectric ceramic layer20b, and the average particle size of the dielectric particles included in the third dielectric ceramic layers41and42. The average particle sizes of Test Examples 2-1 to 2-27 were examined by the measurement method described above.

In Table 3, “first” in the item of comparison of the average particle size refers to the average particle size of the dielectric particles included in the first dielectric ceramic layer; “second” refers to the average particle size of the dielectric particles included in the second dielectric ceramic layer; “third” refers to the average particle size of the dielectric particles included in the third dielectric ceramic layer; and “intersection” refers to the average particle size of the dielectric particles included in the near intersection region.

On the other hand, for the multilayer ceramic capacitors of the Test Examples 2-25 to 2-27, the determination was performed by measuring the resistance value (kΩ) in a state in which voltage of about 6.3 V was applied in an environment with a room temperature of about 150° C., to examine MTTF (mean failure time). MTTF was determined when the resistance value became about 10 kΩ or less, and if MTTF was about 15.3 hours (hr) or less, it was evaluated as fail, if MTTF was up to about 30 hours beyond about 15.3 hours (hr), it is evaluated as good, and if MTTF was beyond about 30 hours, it was evaluated as excellent. The results are listed in Table 3. It should be noted that, when the coverage of the internal electrode layer is less than about 80%, since the capacitance is difficult to be measured, it was evaluated as unmeasurable.

TABLE 3AVERAGEAVERAGEAVERAGEPARTICLEPARTICLEPARTICLESIZE OFSIZE OFSIZE OFFIRSTSECONDTHIRDOMPARISON OFDIELECTRICDIELECTRICDIELECTRICAVERAGECERAMICCERAMICCERAMICINTERMTTFPARTICLE DIAMETERTEST EXAMPLELAYER (μm)LAYER (μm)LAYER (μm)SECTION(hr)EVALUATION(C) FIRST > SECOND =TEST0.420.320.330.1532.1EXCELLENTTHIRD > INTERSECTIONEXAMPLE2-1(C) FIRST > SECOND =TEST0.650.330.320.1333.9EXCELLENTTHIRD > INTERSECTIONEXAMPLE2-2(C) FIRST > SECOND =TEST0.710.310.330.1433.1EXCELLENTTHIRD > INTERSECTIONEXAMPLE2-3(D) FIRST = SECOND >TEST0.420.410.320.1234.1EXCELLENTTHIRD > INTERSECTIONEXAMPLE2-4(D) FIRST = SECOND >TEST0.650.660.330.1135.2EXCELLENTTHIRD > INTERSECTIONEXAMPLE2-5(D) FIRST = SECOND >TEST0.710.720.350.1333.8EXCELLENTTHIRD > INTERSECTIONEXAMPLE2-6(E) FIRST = THIRD >TEST0.420.320.410.1532.1EXCELLENTSECOND > INTERSECTIONEXAMPLE2-7(E) FIRST = THIRD >TEST0.650.330.660.1135.1EXCELLENTSECOND > INTERSECTIONEXAMPLE2-8(E) FIRST = THIRD >TEST0.710.350.720.1433.1EXCELLENTSECOND > INTERSECTIONEXAMPLE2-9(F) FIRST = SECOND =TEST0.420.430.420.1135.6EXCELLENTTHIRD > INTERSECTIONEXAMPLE2-10(F) FIRST = SECOND =TEST0.650.660.640.1322.9EXCELLENTTHIRD > INTERSECTIONEXAMPLE2-11(F) FIRST = SECOND =TEST0.710.720.710.1234.0EXCELLENTTHIRD > INTERSECTIONEXAMPLE2-12(G) SECOND > FIRST >TEST0.420.510.350.1532.1EXCELLENTTHIRD > INTERSECTIONEXAMPLE2-13(G) SECOND > FIRST >TEST0.650.730.570.1631.6EXCELLENTTHIRD > INTERSECTIONEXAMPLE2-14(G) SECOND > FIRST >TEST0.710.850.660.1333.7EXCELLENTTHIRD > INTERSECTIONEXAMPLE2-15(E) THIRD = FIRST >TEST0.420.320.430.1433.1EXCELLENTSECOND > INTERSECTIONEXAMPLE2-16(E) THIRD = FIRST >TEST0.650.560.660.1234.2EXCELLENTSECOND > INTERSECTIONEXAMPLE2-17(E) THIRD = FIRST >TEST0.710.650.720.1333.8EXCELLENTSECOND > INTERSECTIONEXAMPLE2-18(H) THIRD > FIRST >TEST0.520.420.330.1631.6EXCELLENTSECOND > INTERSECTIONEXAMPLE2-19(H) THIRD > FIRST >TEST0.720.660.620.1234.3EXCELLENTSECOND > INTERSECTIONEXAMPLE2-20(H) THIRD > FIRST >TEST0.860.70.750.1433.1EXCELLENTSECOND > INTERSECTIONEXAMPLE2-21(I) FIRST >TEST0.410.310.250.2427.6GOODINTERSECTION > SECONDEXAMPLE2-22or THIRD(1) FIRST >TEST0.650.450.320.3314.6FAILINTERSECTION > SECONDEXAMPLE2-23or THIRD(1) FIRST >TEST0.730.550.440.4313.1FAILINTERSECTION > SECONDEXAMPLE2-24or THIRDINTERSECTION > THIRD =TEST0.420.410.420.919.1FAILFIRST = SECONDEXAMPLE2-25INTERSECTION > THIRD =TEST EXAMPLE0.520.510.510.98.9FAILFIRST = SECOND2-26INTERSECTION > THIRD =TEST EXAMPLE0.710.720.710.98.7FAILFIRST = SECOND2-27

According to Table 3, it is confirmed that, when the average particle size of the dielectric particles included in the near intersection region was smaller than the average particle size of the dielectric particles included in each of the first dielectric ceramic layer, the second dielectric ceramic layer, and the third dielectric ceramic layer, MTTF was increased, which improved the reliability of the multilayer ceramic capacitor.

(3) Method for Manufacturing with the Addition of a Step of Removing the Side Surface of the Multilayer Body

In a non-limiting example of a method for manufacturing the multilayer ceramic capacitor1of the present preferred embodiment described above, in order to obtain the green chip110which is the unfired multilayer body10, the method includes the steps of: printing the unfired first internal electrode layer121and second internal electrode layer122on the unfired first dielectric ceramic layer120a; forming the unfired second dielectric ceramic layer120bin a region other than the region of the first dielectric ceramic layer120awhere the first internal electrode layer121and the second internal electrode layer122are printed; stacking the plurality of first dielectric ceramic layer120ato form the green chip110; exposing, by cutting the mother block104, the first internal electrode layer121and the second internal electrode layer122, the first dielectric ceramic layer120a, and the second dielectric ceramic layer120bfrom the first side surface113and the second side surface114of the individual green chips110; and bonding the unfired third dielectric ceramic layer (the side margin portions41and42) to the first side surface113and the second side surface114of the individual green chips110. Here, the green chip110is an example of a multilayer body. The first dielectric ceramic layer120ais an example of a dielectric layer. The first internal electrode layer121and the second internal electrode layer122are examples of internal electrode patterns. The second dielectric ceramic layer120bis an example of a dielectric pattern. The first side surface113and the second side surface114are examples of side surfaces. The side margin portions41and42which are the unfired third dielectric ceramic layer are examples of a dielectric gap layer.

In this manufacturing method, it is possible to add a step of removing a certain thickness of the first side surface113and the second side surface114after the step of exposing, by cutting the mother block104, the first internal electrode layer121and the second internal electrode layer122, the first dielectric ceramic layer120a, and the second dielectric ceramic layer120bfrom the first side surface113and the second side surface114of the green chips110; and before the step of bonding the third dielectric ceramic layer to the first side surface113and the second side surface114of the green chips110. Thus, the side surfaces of the first dielectric ceramic layer120a, the second dielectric ceramic layer120b, and the first internal electrode layer121and the second internal electrode layer122exposed on the first side surface113and the second side surface114are removed.

FIG.25shows a state in which the first side surface113and the second side surface114of the green chip110are flattened by removing a certain thickness (for example, about 1 μm or less) therefrom. InFIG.25, the diagram on the left side shows before the step of removing, and the diagram on the right side shows after the step of removing. When obtaining the plurality of green chips110by cutting the mother block104, the side surfaces of the first side surface113and second side surface114of the green chip110may be slightly bent downward, and thus, plastically deformed due to the stress applied to the lower side in the drawing which is a cutting direction, as shown inFIG.25. In addition, the cut surface may not be sufficiently smooth, or foreign matter may exist in the cut surface. For this reason, the thickness to the extent that the deformed portion is eliminated is removed. Although the method for removing the first side surface113and the second side surface114is not limited, for example, polishing by an appropriate polishing method, for example, is preferably used.

As shown inFIG.26, the first side surface113and the second side surface114after the step of removing are formed to be smooth surfaces from which foreign matter is removed. The third dielectric ceramic layer (the side margin portions41and42) is bonded to the first side surface113and the second side surface114after the step of removing.

In preferred embodiments of the present invention, each of the second dielectric ceramic layer20b, and the first internal electrode layer21and the second internal electrode layer22may include a resin. The resin can be included in the material by being added at the time of manufacturing. That is, the resin is included in the dielectric paste in the second dielectric ceramic layer20b, and the resin is included in the conductive paste in the first internal electrode layer21and the second internal electrode layer22.

The resin included in the dielectric paste and the conductive paste is added for the purpose of defining and functioning as a binder, improving viscosity of the material, and the like. Examples of such resins include polyvinyl acetal resins, such as polyvinyl butyral and polyvinyl acetoacetal, polyvinyl alcohol-based resins, such as polyvinyl alcohol, cellulosic resins such as methylcellulose, ethylcellulose, and cellulose phthalate acetate, (meth)acrylic resins, such as (meth)acrylic acid esters, imide resins such as polyamideimide and polyimide, ethylene-based resins, such as polyethylene oxide, nitrile resins, such as polyacrylonitrile and polymetallilonitrile, urethane resins, such as polyurethane, vinyl resins, such as polyethylene, polypropylene, and vinyl acetate, and rubber-based resins, such as styrene-butadiene rubber. However, the present invention is not limited thereto.

As the content of the resin, the content included in the second dielectric ceramic layer20band the content included in the first dielectric ceramic layer20aare preferably different from one another. The resin contents of the first dielectric ceramic layer20aand the second dielectric ceramic layer20bare preferably about 30 wt % or more and about 50 wt % or less, for example. The resin contents of the first dielectric ceramic layer and the second dielectric ceramic layer20bare preferably different from each other in this range.

In a non-limiting example of a method for manufacturing a multilayer ceramic capacitor according to a preferred embodiment of the present invention, the thickness of the first dielectric ceramic layer120ais preferably about 0.4 μm or more and about 0.8 μm or less, for example. In a non-limiting example of a method for manufacturing a multilayer ceramic capacitor according to a preferred embodiment of the present invention, the thickness of the first internal electrode layer121and the second internal electrode layer122is preferably about 0.4 μm or more and about 0.8 μm or less, for example.

Furthermore, in forming the green chip110, a portion of the second internal electrode layer122may overlap with a portion of the first internal electrode layer121and a portion of the second internal electrode layer122. More specifically, the ends of the second dielectric ceramic layer120b, and the first internal electrode layer121and the second internal electrode layer122adjacent to each other in the length (L) direction may be superimposed on each other. For example, as shown inFIG.27, in the length (L) direction, the end of the second dielectric ceramic layer120bmay be superimposed on the end of the first internal electrode layer121. Similarly to this, an end of the second dielectric ceramic layer120bmay be superimposed on an end of the second internal electrode layer122. In the configuration in which the ends of the length (L) direction are superimposed on each other, the end of the first internal electrode layer121and the end of the second dielectric ceramic layer120bmay be superimposed on the end of the second dielectric ceramic layer120b.

A non-limiting example of a method for manufacturing a multilayer ceramic capacitor according to a preferred embodiment of the present invention includes removing a certain thickness of the first side surface113and the second side surface114of the green chip110which is the unfired multilayer body10, following by pasting the unfired third dielectric ceramic layer to the first side surface113and the second side surface114. Thus, it is possible to form the unfired third dielectric ceramic layer with respect to the first side surface113and the second side surface114in a smooth and clean state.

In the non-limiting example of a method for manufacturing a multilayer ceramic capacitor according to a preferred embodiment of the present invention, by removing the first side surface113and the second side surface114by polishing, it is possible to remove the first side surface113and the second side surface114easily and accurately by a removal amount with a predetermined thickness.

In a non-limiting example of a method for manufacturing a multilayer ceramic capacitor according to a preferred embodiment of the present invention, the second dielectric ceramic layer120bincludes a resin, and the amount of the resin is preferably larger than the amount of the resin included in the first internal electrode layer121and the second internal electrode layer122. Thus, the viscosity of the second dielectric ceramic layer120bis relatively increased, and it is possible to reduce or prevent the occurrence of defects, such as cracks and chips, in the cut surface of the second dielectric ceramic layer20bwhen cutting the mother block104.

In addition, in a non-limiting example of a method for manufacturing a multilayer ceramic capacitor according to a preferred embodiment of the present invention, the thickness of the first dielectric ceramic layer120ais preferably about 0.4 μm or more and about 0.8 μm or less, for example, and the thickness of the first internal electrode layer121and the second internal electrode layer122is preferably about 0.4 μm or more and about 0.8 μm or less, for example. By the unfired dielectric layer and the internal electrode layer having such a thickness, it is possible to allow the first dielectric ceramic layer20a, the first internal electrode layer21, and the second internal electrode layer22after firing to be formed to have a suitable thickness.

Moreover, a non-limiting example of a method for manufacturing a multilayer ceramic capacitor according to a preferred embodiment of the present invention, a portion of the second internal electrode layer122may overlap the first internal electrode layer121and the second internal electrode layer122. Thus, after firing, it is possible to form the second dielectric ceramic layer20bwith a sufficient thickness without any gap.

(4) Defect Portion in the Second Dielectric Ceramic Layer

In the multilayer ceramic capacitor1of the present preferred embodiment, as shown inFIGS.28and29, there is a defect portion520provided by being partially missing in the second dielectric ceramic layer20bbetween at least one second dielectric ceramic layer20band one third dielectric ceramic layer42. Furthermore, similarly to this, there is a defect portion520provided by being partially missing in the second dielectric ceramic layer20bbetween the at least one second dielectric ceramic layer20band the other third dielectric ceramic layer41.

In the region where the second dielectric ceramic layer20bis disposed, i.e. in at least one of the region between the end of the first internal electrode layer21which is not connected to the second external electrode52and the second external electrode52and the region between the end of the second internal electrode layer22which is not connected to the first external electrode51and the first external electrode51in the length (L) direction of the multilayer body10, the defect portion520is included between the first dielectric ceramic layers20aat the position in the stacking (T) direction on the plane including the stacking (T) direction and the width (W) direction, and is included between the second dielectric ceramic layer20band the third dielectric ceramic layer41or42at the position in the width (W) direction.

When fabricating the green chip110which is the unfired multilayer body10, the side surface of the unfired second dielectric ceramic layer120bis subjected to processing followed by firing, to obtain the multilayer body10having the defect portion520on the side surface of the second dielectric ceramic layer20b. Any method can be used as the processing method for obtaining the defective portion520, and for example, the defect portion520can be formed by drilling with a suitable tool or the like.

Furthermore, in “Method for manufacturing with the addition of a step of removing the side surface of the multilayer body” described above, when the first side surface113or the second side surface114of the unfired green chip110is removed by polishing or the like, a portion of the side surface of the second dielectric ceramic layer20bmay be missing, and a fine hole may be formed. If such a hole occurs, the hole may be a defect portion520. The defect portion520may not be formed on the side surface of all the second internal electrode layer22, and it suffices if one or more of the defect portions520is formed on each of the first side surface13side and the second side surface14side at both ends of the length (L) direction.

Furthermore, as shown inFIGS.28and29, a segregation530of Si may be disposed in the defect portion520. The segregation530of Si is a segregation of Si added to the second dielectric ceramic layer20bas an additive.

The size of the segregation530of Si when viewed in the diameter of the equivalent circle diameter is preferably, for example, larger than about ⅓ of the thickness of the second dielectric ceramic layer20b. Furthermore, the size may preferably be about 100 nm or more and about 600 nm or less, for example.

The defect portion520is preferably disposed close to the first internal electrode layer21or the second internal electrode layer22. InFIG.29, the defect portion520is disposed close to the end of the second internal electrode layer22in the length (L) direction. Similarly to this, the defect portion520is preferably disposed close to the end of the first internal electrode layer21in the length (L) direction.

The dimension of the segregation530of Si is preferably about 0.1% or more and about 5% or less, for example, of the dimensions of the third dielectric ceramic layers41and42in the width (W) direction.

In the region where the second dielectric ceramic layer20bis disposed, i.e. in at least one region in the length (L) direction of the multilayer body10between the end of the first internal electrode layer21which is not connected to the second external electrode52and the second external electrode52and the region between the end of the second internal electrode layer22which is not connected to the first external electrode51and the first external electrode51, the multilayer ceramic capacitor1includes the defect portion520which is between the first dielectric ceramic layers20aat the position in the stacking (T) direction on the plane including the stacking (T) direction and the width (W) direction, and is between the second dielectric ceramic layer20band the third dielectric ceramic layer41or42at the position in the width (W) direction.

Thus, it is possible to alleviate the stress generated in the second dielectric ceramic layer20bat the time of firing by the defect portion520. As a result, it is possible to reduce or prevent cracking or chipping from occurring in the second dielectric ceramic layer20b.

In the multilayer ceramic capacitor1, the segregation530of Si may be disposed at the defect portion520. If the segregation530exists in the defect portion520, entry of moisture is reduced or prevented by the segregation530. Due to the segregation530being present in the defect portion520, the humidity resistance of the multilayer ceramic capacitor1is improved. The segregation530may be present in all of the defect portions520or may be present in a portion of the defect portion520. With the defect portion520in which the segregation530is present, it is possible to reduce or prevent cracking or chipping from occurring in the second dielectric ceramic layer20b, and the humidity resistance of the multilayer ceramic capacitor1can be improved.

In the multilayer ceramic capacitor1of the present preferred embodiment, the segregation530of Si is preferably about ⅓ or more (or less than about ⅓) of the thickness of the second dielectric ceramic layer20b.

In the multilayer ceramic capacitor1, the defect portion520is disposed close to the first internal electrode layer21and the second internal electrode layer22. The region close to the first internal electrode layer21and the second internal electrode layer22receives a relatively large stress generated at the time of firing. However, the stress is alleviated by the defect portion520, and as a result of which the occurrence of cracking or chipping can be effectively reduced or prevented.

In the multilayer ceramic capacitor1, in the width direction, the dimension of the segregation530of Si is preferably about 0.1% or more and about 5% or less, for example, of the dimensions of the third dielectric ceramic layers41and42. When the segregation530of Si is present in the defect portion520, it is possible to effectively reduce or prevent the occurrence of cracking and chipping, and it is also possible to improve the humidity resistance of the multilayer ceramic capacitor1.

(5) Segregation at the End of the Internal Electrode Layer Side of the Second Dielectric Ceramic Layer

As shown inFIG.30, in the multilayer ceramic capacitor1of the present preferred embodiment, a first segregation610may be present at the end in the length (L) direction of the first internal electrode layer21which is not connected to the second external electrode52. In addition, the first segregation610may be present at the end in the length (L) direction of the second internal electrode layer22which is not connected to the first external electrode51.

As shown inFIG.31, the first segregation610is generated due to a metal element610aoriginating from the second dielectric ceramic layer20bbeing segregated in a layered structure. Examples of the metal element610ainclude at least one among Mg, Mn, and Si. The segregation610due to the metal element610aoccurs when the metal element included in the second dielectric ceramic layer20bmigrates to the first internal electrode layer21and the second internal electrode layer22during firing of the second dielectric ceramic layer20b.

On the other hand, as shown inFIG.32, a second segregation620may be present at the end of the first internal electrode layer21in the width (W) direction. Furthermore, the second segregation620may be present at the end of the second internal electrode layer22in the width (W) direction.

The second segregation620is generated due to a metal element620aoriginating from the third dielectric ceramic layers41and42in contact with the first internal electrode layer21and the second internal electrode layer22being segregated in a layered form. Similarly to the first segregation610, examples of the metal element620ainclude at least one among Mg, Mn, and Si. The segregation620due to the metal element620ais generated is due to the metal element included in the third dielectric ceramic layers41and42migrating to the first internal electrode layer21and the second internal electrode layer22during firing of the third dielectric ceramic layers41and42.

In the multilayer ceramic capacitor1, the first segregation610segregated in the first internal electrode layer21, the first segregation610segregated in the second internal electrode layer22, the second segregation620segregated in the first internal electrode layer21, and the second segregation620segregated in the second internal electrode layer22are preferably different from one another in the metal element included in at least one set of segregations therein.

When the first dielectric ceramic layer20aincludes BaTiO3as a main component, the content of the metal element included in the first segregation610with respect to the first internal electrode layer21and the second internal electrode layer22is preferably, for example, about 0.3 mol % or more with respect to 100 moles of Ti. Similarly to this, the content of the metal element included in the second segregation620with respect to the first internal electrode layer21and the second internal electrode layer22is preferably, for example, about 0.3 mol % or more with respect to 100 moles of Ti.

In a preferred embodiment of the present invention, the length along the length (L) direction of the region in which the first segregation610is present in the first internal electrode layer21is preferably about 0.1 μm or more, for example. Furthermore, the length along the length (L) direction of the region in which the first segregation610is present in the second internal electrode layer22is preferably about 0.1 μm or more, for example. Furthermore, the length along the width (W) direction of the region in which the second segregation620is present in the first internal electrode layer21is preferably about 0.1 μm or more, for example. Furthermore, the length along the width (W) direction in the region in which the second segregation620is present in the second internal electrode layer22is preferably about 0.1 μm or more, for example. By having these lengths, electric field concentration can be reduced or prevented, and thus it is possible to reliably obtain the advantageous effect of improving the reliability.

With regard to the length of the first segregation610and the second segregation620, when a length becomes below the above length, it is difficult to reduce the electric field concentration. Furthermore, in the first segregation610, if it exceeds about 0.5% of the length (L) direction, or in the second segregation620, if it exceeds about 1.0% of the width (W) direction, the metal element to be segregated (at least one of Mg, Mn, and Si, for example) becomes excessive, and the function of storing the charge of the internal electrode layer is degraded.

The length of the first segregation610in the length (L) direction can be controlled by adjusting the content of the metal element610aincluded in the second dielectric ceramic layer20band migrating to the first internal electrode layer21and the second internal electrode layer22to be segregated. Furthermore, the length of the second segregation620in the width (W) direction can be controlled by adjusting the content of the metal element620aincluded in the third dielectric ceramic layers41and42, and migrating to the first internal electrode layer21and the second internal electrode layer22to be segregated.

In the multilayer ceramic capacitor1, the first segregation610by at least one metal element selected from the group consisting of Mg, Mn, and Si, for example, is present in each of the end in the length (L) direction which is not connected to the second external electrode52in the first internal electrode layer21, and the end in the length (L) direction which is not connected to the first external electrode51in the second internal electrode layer22.

The electric field is likely to be concentrated at the end in the length (L) direction of each of the first internal electrode layer21and the second internal electrode layer22in contact with the second dielectric ceramic layer20b, and when the electric field concentration occurs, the reliability of a multilayer ceramic capacitor may be reduced. However, in the multilayer ceramic capacitor1of the present preferred embodiment, the electric field concentration is reduced or prevented by the first segregation610, and thus it is possible to improve the reliability.

In the multilayer ceramic capacitor1, the second segregation620by at least one metal element selected from the group consisting of Mg, Mn, and Si, for example, is present in each of the end in the width (W) direction of the first internal electrode layer21, and the end in the width (W) direction of the second internal electrode layer22.

The electric field is likely to be concentrated at the end in the width (W) direction of each of the first internal electrode layer21and the second internal electrode layer22in contact with the third dielectric ceramic layers41and42, and when the electric field concentration occurs, the reliability of a multilayer ceramic capacitor may be reduced. However, in the multilayer ceramic capacitor1of the present preferred embodiment, since the electric field concentration is reduced or prevented by the second segregation620, it is possible to improve the reliability.

In the multilayer ceramic capacitor1, the first segregation610segregated in the first internal electrode layer21, the first segregation610segregated in the second internal electrode layer22, the second segregation620segregated in the first internal electrode layer21, and the second segregation620segregated in the second internal electrode layer22are different from one another in the metal element included in at least one set of segregations therein.

As a result, it is possible to provide an optimal metal element according to the position where the first segregation610and the second segregation620are provided, and thus it is possible to improve reliability.

In the multilayer ceramic capacitor1of the present preferred embodiment, the first dielectric ceramic layer20aincludes Ba and Ti, and the content of each of the metal element610aincluded in the first segregation610and the metal element620aincluded in the second segregation620with respect to the internal electrode layer is preferably about 0.3 mol % or more, for example, with respect to 100 moles of Ti.

Thus, the electric field concentration described above can be effectively reduced or prevented, and the reliability can be further improved.

In the multilayer ceramic capacitor1of the present preferred embodiment, the region where the first segregation610is present in the first internal electrode layer21is preferably about 0.3 μm or more, for example, in the length (L) direction; the region where the first segregation610is present in the second internal electrode layer22is preferably about 0.3 μm or more, for example, in the length (L) direction; the region where the second segregation620is present in the first segregation610is preferably about 0.3 μm or more, for example, in the width (W) direction; and the region where the second segregation620is present in the second segregation620is preferably about 0.3 μm or more, for example, in the width (W) direction.

Thus, the electric field concentration is reduced or prevented by the segregation, and thus the advantageous effect of improving the reliability is reliably obtained.

Test Example 3

Next, Test Example 3 will be described which verifies the advantageous effects of the first segregation610and the second segregation620in the multilayer ceramic capacitor1of the present preferred embodiment.

As shown in Table 4, Test Examples 3-1 to 3-18 were prepared for the multilayer ceramic capacitor including the second dielectric ceramic layer20bincluding any one of the elements of Mg, Mn, Si and the third dielectric ceramic layers41and42. Then, for each Test Example, the concentration of the element, and the length in the length (L) direction and the length in the width (W) direction of the first segregation generated at the end in the length (L) direction of the first internal electrode layer21and the second internal electrode layer22were examined. The concentrations of the metal elements of the first segregation and the second segregation were examined by using the same method as for the concentration of the second alloy portion and the concentration of the third alloy portion in “Test Example 1” described above. Furthermore, the length of each of the first segregation and the second segregation was measured by EDX analysis.

For the multilayer ceramic capacitors of Test Examples 3-1 to 3-18, the determination was performed by measuring, after being cooled to room temperature after being heated for about 1 hour in an environment with a room temperature of about 150° C., the resistance value (kΩ) in a state in which a voltage of about 6.3 V was applied, to examine MTTF (mean failure time). In addition, whether or not the capacitance was reduced was examined by an LCR meter (E4980 available from Keysight Technologies). When the decrease in the capacitance was about 3% or more, or MTTF was about 15.3 hours or less, it was evaluated as fail, when the decrease of the capacitance was less than about 3%, and MTTF was more than about 15.3 hours and less than about 30 hours, it was evaluated as good, and when the decrease in the capacitance was less than about 3% and MTTF was more than about 30 hours, it was evaluated as excellent. The results are listed in Table 4.

TABLE 4LENGTH INLENGTH INLENGTHWIDTHCONCENTRATIONDIRECTIONDIRECTIONMTTFCAPACITANCEELEMENT(MOLE %)(μm)(μm)(hr)DECREASEEVALUATIONTESTSi0.20.080.0714.10.1%FAILEXAMPLEDECREASED3-1TESTSi0.30.10.1229.70.13%GOODEXAMPLEDECREASED3-2TESTSi0.50.30.2730.80.38%EXCELLENTEXAMPLEDECREASED3-3TESTSi0.550.40.3431.50.45%EXCELLENTEXAMPLEDECREASED3-4TESTSi0.60.450.4232.30.5%EXCELLENTEXAMPLEDECREASED3-5TESTSi0.72.13.238.93.5%FAILEXAMPLEDECREASED3-6TESTMg0.20.070.0513.50.11%FAILEXAMPLEDECREASED3-7TESTMg0.30.10.1329.70.13%GOODEXAMPLEDECREASED3-8TESTMg0.50.30.2930.80.38%EXCELLENTEXAMPLEDECREASED3-9TESTMg0.550.40.4231.50.45%EXCELLENTEXAMPLEDECREASED3-10TESTMg0.60.450.5132.30.5%EXCELLENTEXAMPLEDECREASED3-11TESTMg0.72.33.038.93.2%FAILEXAMPLEDECREASED3-12TESTMn0.20.070.0214.90.15%FAILEXAMPLEDECREASED3-13TESTMn0.30.10.0529.70.13%GOODEXAMPLEDECREASED3-14TESTMn0.50.30.2630.80.38%EXCELLENTEXAMPLEDECREASED3-15TESTMn0.550.40.4231.50.45%EXCELLENTEXAMPLEDECREASED3-16TESTMn0.60.450.4232.30.5%EXCELLENTEXAMPLEDECREASED3-17TESTMn0.71.92.533.53.2%FAILEXAMPLEDECREASED3-18

By allowing the second dielectric layer to include Mg, Mn, and Si, so as to produce a segregated portion at the end in the length direction and the width direction of the internal electrode, it is possible to eliminate the reliability degradation factor which is likely to occur at the end thereof. However, if the content is too large, the region which defines and functions as a metal of the internal electrode becomes narrow, resulting in a decrease in capacitance.

(6) Segregation Formed in the Corner Region of the Internal Electrode Layer Side of the Second Dielectric Ceramic Layer

When the first segregation610and the second segregation620described above are included, a third segregation630is preferably present as shown inFIG.33. The third segregation630is present in each of a first corner region710and a second corner region720.

The first corner region710is a region in which the length (L) direction in which the first segregation610exists overlaps the width (W) direction in which the second segregation620exists, in the first internal electrode layer21. Furthermore, the second corner region720is a region in which the length (L) direction in which the first segregation610exists overlaps the width (W) direction in which the second segregation620exists, in the second internal electrode layer22. The third segregation630is generated by the segregation of the metal element610aof the first segregation610and the metal element620aof the second segregation620.

In a preferred embodiment of the present invention, it is preferable for the metal element610aincluded in the first segregation610and the metal element620aincluded in the second segregation620to be different from each other, and the metal element630aof the third segregation630include both the metal element610aincluded in the first segregation610and the metal element620aincluded in the second segregation620.

Furthermore, in a preferred embodiment of the present invention, the region where the first segregation610exists is preferably about 0.1 μm or more, for example, in the length (L) direction, and the region where the second segregation620exists is preferably about 0.1 μm or more, for example, in the width (W) direction.

FIG.33shows a plane including the length (L) direction and the width (W) direction in the multilayer ceramic capacitor1. The third segregation630is preferably segregated in a substantially right-angled triangular shape so that the region where the third segregation630exists becomes larger as approaching the end in the length (L) direction in the plane including the length (L) direction and the width (W) direction. A portion or all of the third segregation630is included in the near intersection region440inFIG.19.

Furthermore, in the multilayer ceramic capacitor1, it is preferable for the second dielectric ceramic layer20bto be arranged with respect to the first internal electrode layer21and the second internal electrode layer22so that a portion thereof is superimposed on the region where the third segregation630exists in the stacking (T) direction. More specifically, for example, as shown inFIG.34, the end of the second dielectric ceramic layer20bis superimposed, in the length (L) direction, on the end of the second internal electrode layer22in the region including the third segregation630. Similarly to this, the end of the second dielectric ceramic layer20bmay be superimposed on the end of the first internal electrode layer21. In such a mode in which the end in the length (L) direction is superimposed thereon, the end of the first internal electrode layer21or the end of the second dielectric ceramic layer20bmay be superimposed on the end of the second dielectric ceramic layer20b.

In the multilayer ceramic capacitor1, the first segregation610by at least one metal element selected from the group consisting of Mg, Mn, and Si is present in each of the end of the first internal electrode layer21in the length (L) direction which is not connected to the second external electrode52, and the end of the second internal electrode layer22in the length (L) direction which is not connected to the first external electrode51; the second segregation620by at least one metal element selected from the group consisting of Mg, Mn, and Si is present in each of the end of the first internal electrode layer21in the width (W) direction, and the end of the second internal electrode layer22in the width (W) direction; and the third segregation630by the respective metal elements of the first segregation610and second segregation620is present in each of the first corner region710where the end in the length (L) direction in which the first segregation610exists in the first internal electrode layer21overlaps the width (W) direction in which the second segregation620exists in the first internal electrode layer21, and the second corner region720where the end in the length (L) direction in which the first segregation610exists in the second internal electrode layer22overlaps the width (W) direction in which the second segregation620exists.

The electric field is likely to be concentrated at the first corner region710and the second corner region720, and when the electric field concentration occurs, the reliability of a multilayer ceramic capacitor may be degraded. However, in the multilayer ceramic capacitor1of the present preferred embodiment, since the electric field concentration to the first corner region710and the second corner region720is reduced or prevented by the third segregation630, the reliability can be improved.

In the multilayer ceramic capacitor1of the present preferred embodiment, the metal element610aincluded in the first segregation610and the metal element620aincluded in the second segregation620are different from each other, and the metal element included in the third segregation630includes both the metal element610aincluded in the first segregation610and the metal element620aincluded in the second segregation620.

As a result, it is possible for the third segregation630to reduce or prevent the electric field concentration to the first corner region710and the second corner region720, thus improving the reliability.

It should be noted that, in the third segregation630, Mg is preferably used as the metal element disposed on the side close to the third dielectric ceramic layers41and42. On the other hand, in the third segregation630, Si is preferably used as the metal element disposed on the side close to the second dielectric ceramic layer20b, from the viewpoint of the possibility of improving moisture resistance. Therefore, it is preferable for both Mg and Si to be segregated in the first corner region710and the second corner region720. In addition, there is a possibility that the short-circuit recovery is performed due to the first segregation610at the ends in the width (W) direction of the first internal electrode layer21and the second internal electrode layer22. Furthermore, it is more preferable for Sn to be a solid solution in the first internal electrode layer21and the second internal electrode layer22.

In the multilayer ceramic capacitor1of the present preferred embodiment, preferably, the region where the first segregation610exists is about 0.1 μm or more in the length (L) direction, and the region where the second segregation620exists is about 0.1 μm or more in the width (W) direction, for example. Thus, the electric field concentration is reduced or prevented by segregation, and the advantageous effect of improving the reliability is reliably obtained.

In the multilayer ceramic capacitor1of the present preferred embodiment, the region where the third segregation630exists becomes larger approaching the end in the length (L) direction in a plane including the length (L) direction and the width (W) direction.

Thus, the area of the third segregation630in the portion of the end of the second dielectric ceramic layer20bin the length (L) direction where the electric field concentration is likely to occur increases, and reduction or prevention of the electric field concentration by the third segregation630is achieved more effectively, thus making it possible to further improve the reliability.

In the multilayer ceramic capacitor1of the present preferred embodiment, the second dielectric ceramic layer20bis arranged with respect to the first internal electrode layer21and the second internal electrode layer22so that a portion thereof is superimposed on the region where the third segregation630exists in the stacking (T) direction.

Thus, the region where the third segregation630exists is likely to become larger approaching the end in the length (L) direction in the plane including the length (L) direction and the width (W) direction.

Test Example 4

Next, Test Example 4 will be described which verifies the advantageous effects of the third segregation630in the multilayer ceramic capacitor1.

As shown in Table 5, Test Examples 4-1 to 4-18 were prepared for the multilayer ceramic capacitors each including the second dielectric ceramic layer including any one of the metal elements of Mg, Mn, and Si, and the third dielectric ceramic layer including any one of Mg, Mn, and Si. Then, the concentration of the metal element included in the third segregation occurring in the first corner region and the second corner region of each of the multilayer ceramic capacitor, the length of the length (L) direction and the length of the width (W) direction were examined. The concentration of the metal element of the third segregation was examined by using the same method as the concentration of the second alloy portion and the concentration of the third alloy portion in “Test Example 1” described above. Also, the respective lengths of the third segregation were measured by EDX analysis.

For the multilayer ceramic capacitors of Test Examples 4-1 to 4-14, the determination was performed by measuring the resistance value (kΩ) in a state in which a voltage of about 6.3 V was applied in an environment with a room temperature of about 150° C., to examine MTTF (mean failure time). MTTF was determined when the resistance value became about 10 kΩ or less, and if MTTF was about 15.3 hours (hr) or less, it was evaluated as fail, if MTTF was up to about 30 hours beyond about 15.3 hours (hr), it is evaluated as good, and if MTTF was beyond about 30 hours, it was evaluated as excellent. The results are listed in Table 5. In addition, whether or not the capacitance was reduced was examined by an LCR meter (E4980 available from Keysight Technologies), and those showing the reduction of capacitance of about 3% or more were evaluated as fail. It should be noted that, when the coverage of the internal electrode layer is less than about 80%, since the capacitance is difficult to be measured, it was evaluated as unmeasurable.

TABLE 5SEGREGATIONSEGREGATIONLENGTH INLENGTH INCONCENTRATIONWIDTHLENGTHMTTFELEMENT(MOLE %)DIRECTIONDIRECTION (μm)(hr)EVALUATIONTEST EXAMPLESi0.20.070.0515.2FALL4-1TEST EXAMPLESi0.30.10.127.3GOOD4-2TEST EXAMPLESi0.51.11.132.1EXCELLENT4-3TEST EXAMPLESi0.551.31.333.4EXCELLENT4-4TEST EXAMPLESi0.61.51.535.6EXCELLENT4-5TEST EXAMPLESi0.72.122.1238.9FAIL4-6CAPACITANCEDECREASED 3%TEST EXAMPLEMg0.20.080.0714.8FALL4-7TEST EXAMPLEMg0.30.10.127.3GOOD4-8TEST EXAMPLEMg0.51.11.132.1EXCELLENT4-9TEST EXAMPLEMg0.551.31.333.4EXCELLENT4-10TEST EXAMPLEMg0.61.51.535.6EXCELLENT4-11TEST EXAMPLEMg0.72.112.1138.9FAIL4-12CAPACITANCEDECREASED 3%TEST EXAMPLEMn0.20.060.0713.5FALL4-13TEST EXAMPLEMn0.30.10.127.3GOOD4-14TEST EXAMPLEMn0.51.11.132.1EXCELLENT4-15TEST EXAMPLEMn0.551.31.333.4EXCELLENT4-16TEST EXAMPLEMn0.61.51.535.6EXCELLENT4-17TEST EXAMPLEMn0.71.71.642.5FAIL4-18CAPACITANCEDECREASED 3%

By allowing the second ceramic dielectric layer and the third ceramic dielectric layer to include Si, Mg, and Mn, it is possible to produce many segregation regions in the corners. In particular, electric field concentration occurs in the corner, which tends to degrade the reliability. However, it is possible to improve the reliability by producing a segregated region. However, if the content is too large, the region which functions as a metal of the internal electrode becomes narrow, resulting in a reduction in capacitance.

(7) Thickness of the Second Dielectric Ceramic Layer

FIG.35schematically shows the WT cross-section at the central portion in the length (L) direction of the multilayer body10in the multilayer ceramic capacitor1, and respectively shows, in this cross-section, the thickness of the first dielectric ceramic layer20aas T1and the thickness at the end in the width (W) direction as T2.

Furthermore,FIG.36shows a portion of the LT cross-section of the multilayer ceramic capacitor1of the present preferred embodiment, and T3refers to the thickness of the second dielectric ceramic layer20b. AlthoughFIG.36shows the second dielectric ceramic layer20bin contact with the second internal electrode layer22, the thickness of the second dielectric ceramic layer20bin contact with the first internal electrode layer21is also regarded as T3. In other words, the thickness T3of the second dielectric ceramic layer20brefers to each of the thicknesses between the end of the first internal electrode layer21in the length (L) direction which is not connected to the second external electrode52, and the second external electrode52, and between the end of the second internal electrode layer22in the length (L) direction which is not connected to the first external electrode51and the second external electrode52.

In a preferred embodiment of the present invention, the difference in thickness between T1and T2is relatively small and is within about 10% of T1. In contrast, the thickness of T3is larger than T1and T2, and the difference is preferably, for example, about 10% or more of T1and T2.

The method of increasing the thickness T3of the second dielectric ceramic layer20bmore than the thicknesses T1and T2of the first dielectric ceramic layer20ais not limited to the method described above and, for example, a method is also possible by causing the end of the unfired second dielectric ceramic layer120bin the length (L) direction to be superimposed on the ends of the unfired first internal electrode layer121and the unfired second internal electrode layer122in the length (L) direction, when fabricating the green chip110before firing, following which the green chip110is fired.

Among T1, T2, and T3, the thickness T1of the central portion of the first dielectric ceramic layer20ais preferably about 0.7 μm or less, for example. The thickness T3of the second dielectric ceramic layer20bis preferably about 0.4 μm or more, for example.

In the multilayer ceramic capacitor1, in a plane including the center portion in the length (L) direction, and the stacking (T) direction and the width (W) direction of the first dielectric ceramic layer20a, when the thickness at the center portion in the stacking (T) direction is defined as T1, the thickness at the end of the first dielectric ceramic layer20ain the width (W) direction is defined as T2, and the respective thicknesses between the end of the first internal electrode layer21in the length (L) direction which is not connected to the second external electrode52, and the second external electrode52and between the end of the second internal electrode layer22in the length (L) direction which is not connected to the first external electrode51, and the first external electrode51is defined as T3, the difference in thickness between T1and T2is within 10% of T1, the thickness of T3is greater than T1and T2, and the difference thereof is preferably, for example, about 10% or more of T1and T2.

Thus, the element thickness by the second dielectric ceramic layer20bdisposed for the purpose of level difference elimination is provided sufficiently between the first dielectric ceramic layer20asandwiching the first internal electrode layer21and the second internal electrode layer22, a result of which it is possible to improve the reliability.

While preferred embodiments of the present invention have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the present invention. The scope of the present invention, therefore, is to be determined solely by the following claims.