Patent ID: 12249581

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

With reference now toFIG.1, there is shown a first carrier substrate101with an adhesive layer103, a polymer layer105, and a first seed layer107over the first carrier substrate101. The first carrier substrate101comprises, for example, silicon based materials, such as glass or silicon oxide, or other materials, such as aluminum oxide, combinations of any of these materials, or the like. The first carrier substrate101is planar in order to accommodate an attachment of semiconductor devices such as a first semiconductor device201and a second semiconductor device301(not illustrated inFIG.1but illustrated and discussed below with respect toFIGS.2-3).

The adhesive layer103is placed on the first carrier substrate101in order to assist in the adherence of overlying structures (e.g., the polymer layer105). In an embodiment the adhesive layer103may comprise an ultra-violet glue, which loses its adhesive properties when exposed to ultra-violet light. However, other types of adhesives, such as pressure sensitive adhesives, radiation curable adhesives, epoxies, combinations of these, or the like, may also be used. The adhesive layer103may be placed onto the first carrier substrate101in a semi-liquid or gel form, which is readily deformable under pressure.

The polymer layer105is placed over the adhesive layer103and is utilized in order to provide protection to, e.g., the first semiconductor device201and the second semiconductor device301once the first semiconductor device201and the second semiconductor device301have been attached. In an embodiment the polymer layer105may be polybenzoxazole (PBO), although any suitable material, such as polyimide, a polyimide derivative, a Solder Resistance (SR), an Ajinomoto build-up film (ABF), or the like may alternatively be utilized. The polymer layer105may be placed using, e.g., a spin-coating process to a first thickness T1of between about 0.5 μm and about 10 μm, such as about 5 μm, although any suitable method and thickness may alternatively be used.

The first seed layer107is formed over the polymer layer105. In an embodiment the first seed layer107is a thin layer of a conductive material that aids in the formation of a thicker layer during subsequent processing steps. The first seed layer107may comprise a layer of titanium followed by a layer of copper, although any other suitable material or combination of materials, such as a single layer of copper, may also be used. The first seed layer107may be created using processes such as sputtering, evaporation, or PECVD processes, depending upon the desired materials.

FIG.1also illustrates a placement and patterning of a photoresist109over the first seed layer107. In an embodiment the photoresist109may be placed on the first seed layer107using, e.g., a spin coating technique to a height of between about 50 μm and about 250 μm. Once in place, the photoresist109may then be patterned by exposing the photoresist109to a patterned energy source (e.g., a patterned light source) so as to induce a chemical reaction, thereby inducing a physical change in those portions of the photoresist109exposed to the patterned light source. A developer is then applied to the exposed photoresist109to take advantage of the physical changes and selectively remove either the exposed portion of the photoresist109or the unexposed portion of the photoresist109, depending upon the desired pattern.

In an embodiment the pattern formed into the photoresist109is a pattern for vias111. The vias111are formed in such a placement as to be located on different sides of subsequently attached devices such as the first semiconductor device201and the second semiconductor device301. However, any suitable arrangement for the pattern of vias111, such as by being located such that the first semiconductor device201and the second semiconductor device are placed on opposing sides of the vias111, may alternatively be utilized.

In an embodiment the vias111are formed within the photoresist109. In an embodiment the vias111comprise one or more conductive materials, such as copper, tungsten, other conductive metals, or the like, and may be formed, for example, by electroplating, electroless plating, or the like. In an embodiment, an electroplating process is used wherein the first seed layer107and the photoresist109are submerged or immersed in an electroplating solution. The first seed layer107surface is electrically connected to the negative side of an external DC power supply such that the first seed layer107functions as the cathode in the electroplating process. A solid conductive anode, such as a copper anode, is also immersed in the solution and is attached to the positive side of the power supply. The atoms from the anode are dissolved into the solution, from which the cathode, e.g., the first seed layer107, acquires the dissolved atoms, thereby plating the exposed conductive areas of the first seed layer107within the opening of the photoresist109.

Once the vias111have been formed using the photoresist109and the first seed layer107, the photoresist109may be removed using a suitable removal process (not illustrated inFIG.1but seen inFIG.3below). In an embodiment, a plasma ashing process may be used to remove the photoresist109, whereby the temperature of the photoresist109may be increased until the photoresist109experiences a thermal decomposition and may be removed. However, any other suitable process, such as a wet strip, may alternatively be utilized. The removal of the photoresist109may expose the underlying portions of the first seed layer107.

Once exposed a removal of the exposed portions of the first seed layer107may be performed (not illustrated inFIG.1but seen inFIG.3below). In an embodiment the exposed portions of the first seed layer107(e.g., those portions that are not covered by the vias111) may be removed by, for example, a wet or dry etching process. For example, in a dry etching process reactants may be directed towards the first seed layer107using the vias111as masks. In another embodiment, etchants may be sprayed or otherwise put into contact with the first seed layer107in order to remove the exposed portions of the first seed layer107. After the exposed portion of the first seed layer107has been etched away, a portion of the polymer layer105is exposed between the vias111.

FIG.2illustrates a first semiconductor device201that will be attached to the polymer layer105within the vias111(not illustrated inFIG.2but illustrated and described below with respect toFIG.3). In an embodiment the first semiconductor device201comprises a first substrate203, first active devices (not individually illustrated), first metallization layers205, first contact pads207, a first passivation layer211, and first external connectors209. The first substrate203may comprise bulk silicon, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of a semiconductor material such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. Other substrates that may be used include multi-layered substrates, gradient substrates, or hybrid orientation substrates.

The first active devices comprise a wide variety of active devices and passive devices such as capacitors, resistors, inductors and the like that may be used to generate the desired structural and functional requirements of the design for the first semiconductor device201. The first active devices may be formed using any suitable methods either within or else on the first substrate203.

The first metallization layers205are formed over the first substrate203and the first active devices and are designed to connect the various active devices to form functional circuitry. In an embodiment the first metallization layers205are formed of alternating layers of dielectric and conductive material and may be formed through any suitable process (such as deposition, damascene, dual damascene, etc.). In an embodiment there may be four layers of metallization separated from the first substrate203by at least one interlayer dielectric layer (ILD), but the precise number of first metallization layers205is dependent upon the design of the first semiconductor device201.

The first contact pads207may be formed over and in electrical contact with the first metallization layers205. The first contact pads207may comprise aluminum, but other materials, such as copper, may alternatively be used. The first contact pads207may be formed using a deposition process, such as sputtering, to form a layer of material (not shown) and portions of the layer of material may then be removed through a suitable process (such as photolithographic masking and etching) to form the first contact pads207. However, any other suitable process may be utilized to form the first contact pads207.

The first passivation layer211may be formed on the first substrate203over the first metallization layers205and the first contact pads207. The first passivation layer211may be made of one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, combinations of these, or the like. The first passivation layer211may be formed through a process such as chemical vapor deposition (CVD), although any suitable process may be utilized.

The first external connectors209may be formed to provide conductive regions for contact between the first contact pads207and, e.g., a redistribution layer501(not illustrated inFIG.2but illustrated and described below with respect toFIG.5). In an embodiment the first external connectors209may be conductive pillars and may be formed by initially forming a photoresist (not shown) over the first passivation layer211to a thickness between about 5 μm to about 20 μm. The photoresist may be patterned to expose portions of the first passivation layers211through which the conductive pillars will extend. Once patterned, the photoresist may then be used as a mask to remove the desired portions of the first passivation layer211, thereby exposing those portions of the underlying first contact pads207to which the first external connectors209will make contact.

The first external connectors209may be formed within the openings of both the first passivation layer211and the photoresist. The first external connectors209may be formed from a conductive material such as copper, although other conductive materials such as nickel, gold, or metal alloy, combinations of these, or the like may also be used. Additionally, the first external connectors209may be formed using a process such as electroplating, by which an electric current is run through the conductive portions of the first contact pads207to which the first external connectors209are desired to be formed, and the first contact pads207are immersed in a solution. The solution and the electric current deposit, e.g., copper, within the openings in order to fill and/or overfill the openings of the photoresist and the first passivation layer211, thereby forming the first external connectors209. Excess conductive material and photoresist outside of the openings of the first passivation layer211may then be removed using, for example, an ashing process, a chemical mechanical polish (CMP) process, combinations of these, or the like.

However, as one of ordinary skill in the art will recognize, the above described process to form the first external connectors209is merely one such description, and is not meant to limit the embodiments to this exact process. Rather, the described process is intended to be merely illustrative, as any suitable process for forming the first external connectors209may alternatively be utilized. All suitable processes are fully intended to be included within the scope of the present embodiments.

A die attach film (DAF)217may be placed on an opposite side of the first substrate203in order to assist in the attachment of the first semiconductor device201to the polymer layer105. In an embodiment the die attach film217is an epoxy resin, a phenol resin, acrylic rubber, silica filler, or a combination thereof, and is applied using a lamination technique. However, any other suitable alternative material and method of formation may alternatively be utilized.

FIG.3illustrates a placement of the first semiconductor device201onto the polymer layer105along with a placement of the second semiconductor device301. In an embodiment the second semiconductor device301may comprise a second substrate303, second active devices (not individually illustrated), second metallization layers305, second contact pads307, a second passivation layer311, and second external connectors309. In an embodiment the second substrate303, the second active devices, the second metallization layers305, the second contact pads307, the second passivation layer311, and the second external connectors309may be similar to the first substrate203, the first active devices, the first metallization layers205, the first contact pads207, the first passivation layer211, and the first external connectors209, although they may also be different.

In an embodiment the first semiconductor device201and the second semiconductor device301may be placed onto the polymer layer105using, e.g., a pick and place process. However, any other method of placing the first semiconductor device201and the second semiconductor device301may also be utilized.

FIG.4illustrates an encapsulation of the vias111, the first semiconductor device201and the second semiconductor device301. The encapsulation may be performed in a molding device (not individually illustrated inFIG.4), which may comprise a top molding portion and a bottom molding portion separable from the top molding portion. When the top molding portion is lowered to be adjacent to the bottom molding portion, a molding cavity may be formed for the first carrier substrate101, the vias111, the first semiconductor device201, and the second semiconductor device301.

During the encapsulation process the top molding portion may be placed adjacent to the bottom molding portion, thereby enclosing the first carrier substrate101, the vias111, the first semiconductor device201, and the second semiconductor device301within the molding cavity. Once enclosed, the top molding portion and the bottom molding portion may form an airtight seal in order to control the influx and outflux of gasses from the molding cavity. Once sealed, an encapsulant401may be placed within the molding cavity. The encapsulant401may be a molding compound resin such as polyimide, PPS, PEEK, PES, a heat resistant crystal resin, combinations of these, or the like. The encapsulant401may be placed within the molding cavity prior to the alignment of the top molding portion and the bottom molding portion, or else may be injected into the molding cavity through an injection port.

Once the encapsulant401has been placed into the molding cavity such that the encapsulant401encapsulates the first carrier substrate101, the vias111, the first semiconductor device201, and the second semiconductor device301, the encapsulant401may be cured in order to harden the encapsulant401for optimum protection. While the exact curing process is dependent at least in part on the particular material chosen for the encapsulant401, in an embodiment in which molding compound is chosen as the encapsulant401, the curing could occur through a process such as heating the encapsulant401to between about 100° C. and about 130° C. for about 60 sec to about 3000 sec. Additionally, initiators and/or catalysts may be included within the encapsulant401to better control the curing process.

However, as one having ordinary skill in the art will recognize, the curing process described above is merely an exemplary process and is not meant to limit the current embodiments. Other curing processes, such as irradiation or even allowing the encapsulant401to harden at ambient temperature, may alternatively be used. Any suitable curing process may be used, and all such processes are fully intended to be included within the scope of the embodiments discussed herein.

FIG.4also illustrates a thinning of the encapsulant401in order to expose the vias111, the first semiconductor device201, and the second semiconductor device301for further processing. The thinning may be performed, e.g., using a mechanical grinding or chemical mechanical polishing (CMP) process whereby chemical etchants and abrasives are utilized to react and grind away the encapsulant401, the first semiconductor device201and the second semiconductor device301until the vias111, the first external connectors209(on the first semiconductor device201), and the second external connectors309(on the second semiconductor device301) have been exposed. As such, the first semiconductor device201, the second semiconductor device301, and the vias111may have a planar surface that is also planar with the encapsulant401.

By thinning the encapsulant401such that the vias111, the first semiconductor device201, and the second semiconductor device301are exposed, there is a first region403of encapsulant401that is located between the vias111and the first semiconductor device201. In an embodiment the first region403of the encapsulant401may have a first width W1of between about 150 μm and about 1600 μm, such as about 850 μm. However, any suitable dimensions may be utilized.

However, while the CMP process described above is presented as one illustrative embodiment, it is not intended to be limiting to the embodiments. Any other suitable removal process may alternatively be used to thin the encapsulant401, the first semiconductor device201, and the second semiconductor device301and expose the vias111. For example, a series of chemical etches may be utilized. This process and any other suitable process may alternatively be utilized to thin the encapsulant401, the first semiconductor device201, and the second semiconductor device301, and all such processes are fully intended to be included within the scope of the embodiments.

Optionally, if desired the vias111may be recessed within the encapsulant401. In an embodiment the recessing may be performed using an etching process such as a wet or dry etching process that selectively removes the exposed surface of the vias111without substantially removing the surrounding encapsulant401so that the vias111are recessed. In an embodiment the recessing may be performed so that the vias111are recessed between about 0.05 μm and about 2 μm, such as about 0.1 μm.

FIG.5illustrates a formation of a redistribution layer (RDL)501in order to interconnect the first semiconductor device201, the second semiconductor device301, the vias111and the third external connectors505. By using the RDL501to interconnect the first semiconductor device201and the second semiconductor device301, the first semiconductor device201and the second semiconductor device301may have a pin count of greater than 1000.

In an embodiment the RDL501may be formed by initially forming a second seed layer (not shown) of a titanium copper alloy through a suitable formation process such as CVD or sputtering. A photoresist (also not shown) may then be formed to cover the second seed layer, and the photoresist may then be patterned to expose those portions of the second seed layer that are located where the RDL501is desired to be located.

Once the photoresist has been formed and patterned, a conductive material, such as copper, may be formed on the second seed layer through a deposition process such as plating. However, while the material and methods discussed are suitable to form the conductive material, these materials are merely exemplary. Any other suitable materials, such as AlCu or Au, and any other suitable processes of formation, such as CVD or PVD, may alternatively be used to form the RDL501.

Once the conductive material has been formed, the photoresist may be removed through a suitable removal process such as ashing. Additionally, after the removal of the photoresist, those portions of the second seed layer that were covered by the photoresist may be removed through, for example, a suitable etch process using the conductive material as a mask.

FIG.5also illustrates a formation of a third passivation layer503over the RDL501in order to provide protection and isolation for the RDL501and the other underlying structures. In an embodiment the third passivation layer503may be polybenzoxazole (PBO), although any suitable material, such as polyimide or a polyimide derivative, may alternatively be utilized. The third passivation layer503may be placed using, e.g., a spin-coating process, although any suitable method may alternatively be used.

In an embodiment the thickness of the structure from the third passivation layer503to the polymer layer105may be less than or equal to about 200 μm. By making this thickness as small as possible, the overall structure may be utilized in various small size applications, such as cell phones and the like, while still maintaining the desired functionality. However, as one of ordinary skill in the art will recognize, the precise thickness of the structure may be dependent at least in part upon the overall design for the unit and, as such, any suitable thickness may alternatively be utilized.

Additionally, while only a single RDL501is illustrated inFIG.5, this is intended for clarity and is not intended to limit the embodiments. Rather, any suitable number of conductive and passivation layers, such as three RDL501layers, may be formed by repeating the above described process to form the RDL501. Any suitable number of layers may be utilized.

FIG.5further illustrates a formation of the third external connectors505to make electrical contact with the RDL501. In an embodiment after the third passivation layer503has been formed, an opening may be made through the third passivation layer503by removing portions of the third passivation layer503to expose at least a portion of the underlying RDL501. The opening allows for contact between the RDL501and the third external connectors505. The opening may be formed using a suitable photolithographic mask and etching process, although any suitable process to expose portions of the RDL501may be used.

In an embodiment the third external connectors505may be placed on the RDL501through the third passivation layer503and may be a ball grid array (BGA) which comprises a eutectic material such as solder, although any suitable materials may alternatively be used. Optionally, an underbump metallization (not separately illustrated) may be utilized between the third external connectors505and the RDL501. In an embodiment in which the third external connectors505are solder balls, the third external connectors505may be formed using a ball drop method, such as a direct ball drop process. Alternatively, the solder balls may be formed by initially forming a layer of tin through any suitable method such as evaporation, electroplating, printing, solder transfer, and then performing a reflow in order to shape the material into the desired bump shape. Once the third external connectors505have been formed, a test may be performed to ensure that the structure is suitable for further processing.

FIG.6illustrates a debonding of the first carrier substrate101from the first semiconductor device201and the second semiconductor device301. In an embodiment the third external connectors505and, hence, the structure including the first semiconductor device201and the second semiconductor device301, may be attached to a ring structure601. The ring structure601may be a metal ring intended to provide support and stability for the structure during and after the debonding process. In an embodiment the third external connectors505, the first semiconductor device201, and the second semiconductor device301are attached to the ring structure using, e.g., a ultraviolet tape603, although any other suitable adhesive or attachment may alternatively be used.

Once the third external connectors505and, hence, the structure including the first semiconductor device201and the second semiconductor device301are attached to the ring structure601, the first carrier substrate101may be debonded from the structure including the first semiconductor device201and the second semiconductor device301using, e.g., a thermal process to alter the adhesive properties of the adhesive layer103. In a particular embodiment an energy source such as an ultraviolet (UV) laser, a carbon dioxide (CO2) laser, or an infrared (IR) laser, is utilized to irradiate and heat the adhesive layer103until the adhesive layer103loses at least some of its adhesive properties. Once performed, the first carrier substrate101and the adhesive layer103may be physically separated and removed from the structure comprising the third external connectors505, the first semiconductor device201, and the second semiconductor device301.

FIG.7illustrates a patterning of the polymer layer105in order to expose the vias111(along with the associated first seed layer107). In an embodiment the polymer layer105may be patterned using, e.g., a laser drilling method. In such a method a protective layer, such as a light-to-heat conversion (LTHC) layer or a hogomax layer (not separately illustrated inFIG.7) is first deposited over the polymer layer105. Once protected, a laser is directed towards those portions of the polymer layer105which are desired to be removed in order to expose the underlying vias111. During the laser drilling process the drill energy may be in a range from 0.1 mJ to about 30 mJ, and a drill angle of about 0 degree (perpendicular to the polymer layer105) to about 85 degrees to normal of the polymer layer105. In an embodiment the patterning may be formed to form first openings703over the vias111to have a width of between about 100 μm and about 300 μm, such as about 200 μm. Once the first openings703have been formed with the laser drilling method, the first openings703may be cleaned to remove any laser drill residue.

In another embodiment, the polymer layer105may be patterned by initially applying a photoresist (not individually illustrated inFIG.7) to the polymer layer105and then exposing the photoresist to a patterned energy source (e.g., a patterned light source) so as to induce a chemical reaction, thereby inducing a physical change in those portions of the photoresist exposed to the patterned light source. A developer is then applied to the exposed photoresist to take advantage of the physical changes and selectively remove either the exposed portion of the photoresist or the unexposed portion of the photoresist, depending upon the desired pattern, and the underlying exposed portion of the polymer layer105are removed with, e.g., a dry etch process. However, any other suitable method for patterning the polymer layer105may be utilized.

FIG.8Aillustrates a cross-sectional view of a marking process (represented inFIG.8Aby the dashed cylinder labeled801) that is utilized to mark the polymer layer105with a desired identifying mark805(which mark805merely appears as second openings802in this cross-sectional view ofFIG.8A). In an embodiment the marking process may be, for example, a laser marking process which is used to mark the polymer layer105with, e.g., a run number, a manufacturer identifier, a date of manufacture, combinations of these, or the like, with one or more alphanumeric characters as the mark805. However, any other suitable desired identifying or information mark805may be used.

In an embodiment the marking process801is utilized to form second openings802(also known as kerfs) within the polymer layer105, wherein when each one of the second openings802is taken in combination with one or more of the other second openings802, the combination of second openings802collectively form the desired mark805in, e.g., a top down view. However, if the second openings802extend too far into the polymer layer105or even through the polymer layer105, there is a possibility that defects may occur from exposure of the underlying first semiconductor device201and the second semiconductor device301, or that, even if the second openings802do not extend all of the way through the polymer layer105, damage may occur due to induced heat spot effects, which could further damage the RDL501or the overall functions of the first semiconductor device201and the second semiconductor device301.

FIG.8Billustrates a top-down view of one embodiment of the marking process801which may be used to mitigate or eliminate these issues during the marking process801. For clarity,FIG.8Billustrates a formation of a single first line807in an embodiment in which the marking process801is a laser marking process, although the first line807may be utilized along with other lines (such as a second line901and a third line903, not illustrated inFIG.8Bbut illustrated and described further below with respect toFIG.9A) in order to form any desired shape for the mark805. In an embodiment the laser marking process may be performed by irradiating the polymer layer105with a series of laser pulses (two of which are represented inFIG.8Bby the dashed cylinders labeled8041and8042and the rest of which have been removed for clarity) to form the second openings (seeFIG.8A), wherein each one of the series of laser beam pulses804forms a laser beam pulse exposure (each of which is represented inFIG.8Bby the dashed circles labeled8091,8092,809n-1,809n, etc.).

For example, to begin the laser marking process, a portion of the polymer layer105that is desired to be marked may be irradiated with a first one of the laser beam pulses8041that has a first diameter D1of between about 20 μm and about 120 μm, such as about 50 μm, that is equal to the desired dot width Wdof the first line807. Additionally, the first one of the laser beam pulses8041may have an energy density of between about 1.0×10−3J/mm2and about 5.0×10−2J/mm2, such as about 1.5×10−2J/mm2. Once the polymer layer105has been irradiated, the first one of the laser beam pulses8041may be maintained for a time of between about 1.0×10−5sec and about 8.0×10−5sec, such as about 2.8×10−5sec, in order to pulse the laser beam and form the first laser beam pulse exposure8091on the polymer layer105. During this first one of the laser beam pulses8041, a portion of the polymer layer105is removed to form a first one of the first laser beam pulse exposures8091.

Once the first one of the first laser pulse exposures8091has been formed, the first one of the laser beam pulses8041is halted. At that time, the laser beam may be moved into position to irradiate the polymer layer105with a second one of the laser beam pulses8042in order to form a second laser beam pulse exposure8092which overlaps the first laser beam pulse exposure8091. In an embodiment the second laser beam pulse exposure8092is offset from the first laser beam pulse exposure8091by a first pitch Pi of between about 2 μm and about 70 μm, such as about 5.7 μm. The second one of the laser beam pulses8042may be similar to the first one of the laser beam pulses8041, such as by having the first diameter D1, although any other suitable parameters for the second one of the laser beam pulses8042may be utilized.

After forming the second laser beam pulse exposure8092overlapping the first laser beam pulse exposure8091, the second one of the laser beam pulses8042is halted. At that time, the laser beam may be moved into position to irradiate another portion of the polymer layer105in order to form a third laser beam pulse exposure8093, which overlaps both the first laser beam pulse exposure8091and the second laser beam pulse exposure8092. This process of using offset laser beam pulses804to form overlapping but offset laser beam pulse exposures809within the polymer layer105may be continued to form the first line807, wherein the desired length of the first line807is determined by the number of laser beam pulses804used to form a desired number of laser beam pulse exposures809.

However, by overlapping the laser beam pulse exposures809(e.g., the first laser beam pulse exposure8091is overlapped by at least the second laser beam pulse exposure8092and the third laser beam pulse exposure8093), there will be portions of the laser beam pulse exposures809that have been irradiated by multiple ones of the laser beam pulses804, with each exposure removing additional material from the polymer layer105and causing different kerf depths even within the same laser beam pulse exposure809(e.g., the first laser beam pulse exposure8091). For example, looking at a fully exposed laser beam pulse exposure811(one which is located within an interior of the first line807and not at a terminating end of the first line807such that there is a maximum overlap amount), there may be a total accumulated overlap within the fully exposed laser beam pulse exposure811of between about 100% and about 400%, such as about 376%.

However, when each one of the laser beam pulse exposures809is overlapped by a neighboring laser beam pulse exposure809, each one of the laser beam pulses804will remove additional material from the polymer layer105. For example, in making the first line807with a first pass of the laser beam pulses804, while the individual laser beam pulse exposure809may have different depths within the individual laser beam pulse exposures809, the laser beam pulse exposures809may be generally formed to have a deepest first depth D1that is less than the first thickness T1(seeFIG.1) of the polymer layer105, such as by being between about 2 μm and about 10 μm, such as less than about 7.52 μm.

Additionally, in order to help with the overlapping between the individual ones of the laser beam pulse exposures809, in an embodiment a path angle should be maintained low so that additional overlapping does not occur between a first portion of the first line807and a second portion of the first line807that is at an angle to the first portion of the first line807. For example, in an embodiment the marking path may be maintained to have a first angle α1of between about 20° and about 90°, such as less than about 30°. However, any suitable first angle α1may be used.

FIG.9Aillustrates one embodiment that may be used to reduce or eliminate the defects caused by the marking process801. In this embodiment, the first line807(illustrated with a curved portion) is utilized along with a second line901and a third line903to collectively form a letter “Q” within the polymer layer105. In an embodiment the second line901and the third line903may be formed using a similar process as the first line807. For example, a series of laser beam pulses804may be used to form overlapping laser beam pulse exposures809within the polymer layer105, wherein the combination of laser beam pulse exposures809collectively form the second line901and, separately, form the third line903.

However, in order to prevent any additional removal of the material of the polymer layer105beyond the material already removed during the formation of the individual lines (discussed above with respect toFIG.8B), the mark805(e.g., the character “Q”) is formed such that there is an overlap count (or a number of passes over a spot) less than one such that the mark805is formed to be cross free. For example, the first line807may be formed such that the first line807does not intersect or overlap either the second line901or the third line903. Similarly, the second line901is formed such that the second line901does not intersect or overlap either the first line807or the third line903.

Such a prevention creates regions of separation902(wherein a longitudinal axis of a first line intersects a longitudinal axis of a second line) wherein the lines that are used to form the desired character (e.g., the first line807, the second line901, and the third line903to form the letter “Q”) collectively form a discontinuous shape. By forming such a discontinuous shape, sections where the lines would have previously intersected and caused undesired and uncontrollable kerf depths may be prevented, and the first depth D1within the region of separation902is the same as the first depth D1outside of the region of separation902(whereas previously the depths have been different when there are multiple passes of the laser beams). As such, fewer defects may arise during the formation of the mark805. In an embodiment the separation between lines (e.g., between the second line901and the third line903) may be a first distance D1of between about 10 μm and about 50 μm, such as about 25 μm.

FIG.9Billustrates additional embodiments of other alphanumeric characters that may be used to form the mark805similar to the “Q” illustrated above with respect toFIG.9A. In particular,FIG.9Billustrates the lower case letters “r”905, “a”907, and “g”909that are formed with the cross-free methodology and design. As can be seen, each of these letters is designed and formed with regions of separation902in those areas where lines would otherwise intersect.

FIG.10illustrates additional embodiments of alphanumeric characters that may be utilized with the cross-free marking process801. In this collection of alphanumerical upper case and lower case characters, there can be seen regions of separation902within some of the individual letters (e.g., the letter “T”), although not every letter has a region of separation902(e.g., the letter “L”). In each of these regions of separation902, the laser marking process forms a separation between lines so as to prevent or mitigate the additional removal of additional material from the polymer layer105during the formation of intersecting lines.

By eliminating the overlap between lines, a more controllable kerf depth may be obtained, and package die damage from heat spot effects that can occur and damage the RDL501, the first semiconductor device201, and the second semiconductor device301when the polymer layer105becomes thinner during an uncontrolled marking processes may be reduced or eliminated. As such, a thinner polymer layer105may be used while maintaining an effective thermal control and an overall form factor reduction may be achieved while also improving the overall yield of manufactured devices.

For example, in a particular embodiment the first depth D1within an individual one of the laser beam pulse exposures809(seeFIG.8B) may vary between 6.87 μm to 8.03 μm, with an average of about 7.455 μm and a variation of about 1.16 μm. This is lower than in a multiple pass, non-cross-free method, in which the depth may vary from 13.25 μm and 15.92 μm, with an average of 14.757 μm and a variation of 2.67 μm. In another description, by using a cross-free method, the first depth D1is the depth of a single pass of the laser beam, such as about 7.52 μm, while multiple passes of the laser beam, such as two-passes of the laser beam with an overlap count of 2, may have a depth of 15.8 μm. By reducing the marking depth, the defects that may occur because of the undesired removal of additional material from the polymer layer105may be reduced or eliminated.

FIG.11illustrates another embodiment in which the lines within a desired identifying mark805may have a reduced overlap count (e.g., an overlap count of less than two) but in which the lines may still have an overlap count greater than one. In this embodiment, rather than having a cross-free character where the individual lines do not intersect, the individual lines within a character may have an overlap count of less than about 2 in an area of intersection between, e.g., the first line807with a fourth line1101. In an embodiment the fourth line1101may be formed using a similar process as the one described above with respect toFIG.8B. For example, a series of laser beam pulses804(not separately illustrated inFIG.11) are used to form laser beam pulse exposures809that overlap with each other within the fourth line1101to remove material from the polymer layer105and form the fourth line1101, although any suitable method may be utilized.

In this embodiment, however, instead of keeping the first line807and the fourth line1101from intersecting with each other (and having an overlap count less than one), a partial intersection between the first line807and the fourth line1101may be made, wherein the laser beam pulse exposures809may extend partially into the fourth line1101. However, instead of the first line807extending all of the way into the fourth line1101(wherein one of the laser beam pulse exposures809from the first line807is fully overlapped by the fourth line1101, thereby having an overlap count of 2), the first line807may partially extend into the fourth line1101so that the first line807has an overlap count of less than about 2.

In this embodiment, an intersecting laser beam pulse exposure8094(highlighted inFIG.11by the shaded region) is part of the first line807, but also extends at least partially into the fourth line1101. However, by limiting the intersection of the first line807and the fourth line1101, the amount of overlap may be kept small and defects may be minimized. In an embodiment the overlap count for the intersecting laser beam pulse exposure8094is less than two and has an accumulated overlap percentage (between overlapping laser beam pulse exposures809from both the first line807and the fourth line1101) greater than about 376% and less than 752%, such as about 564%.

Such a prevention also forms the first depth D1(seeFIG.8A) within the polymer layer105to have a different depth within the region of intersection than outside of the region of intersection (as there have been additional exposures of the material of the polymer layer105to the laser beams). As such, in an embodiment, the first depth D1within the intersecting laser beam pulse exposure8094may be between about 5 μm and about 18 μm, such as about 14 μm. However, any suitable depth may be used.

Additionally in the embodiment illustrated inFIG.11, in order to help with the overlapping between the individual ones of the laser beam pulse exposures809, in an embodiment the path angle should be maintained low so that additional overlapping does not occur between a first portion of the first line807and a second portion of the first line807. For example, in an embodiment the marking path may be maintained to have a second angle α2of between about 20° and about 90°, such as less than about 88°. However, any suitable second angle α2may be used.

By limiting the amount of overlap between intersecting lines (e.g., the first line807and the fourth line1101), defects that may occur due to the marking process801may be reduced without completely separating the intersecting lines. As such, defects may be reduced or mitigated while still forming an intersection between the lines used to form the mark805.

FIG.12illustrates yet another embodiment in which one or more of the marks805(formed using any of the methods described herein), instead of being formed within the polymer layer105over the first semiconductor device201and the second semiconductor device301, are formed within the polymer layer105over the first region403of the encapsulant401. By forming the marks805within the polymer layer105over the first region403of the encapsulant401and not over the first semiconductor device201and the second semiconductor device301, the deleterious effects of the laser beam pulses804will be primarily limited to the encapsulant401and away from the first semiconductor device201and the second semiconductor device301. As such, the first semiconductor device201and the second semiconductor device301may have a reduced instance of defects caused by the laser beam pulses804.

In an embodiment the marks805are formed over the first region403of the encapsulant401and do not extend beyond the first region403of the encapsulant401. As such, in an embodiment in which the first region403of the encapsulant401has the first width W1(as described above with respect toFIG.4), the marks805have a second width W2that is less than the first width W1, such as by being between about 100 μm and about 850 μm, such as about 450 μm, although any suitable dimensions may alternatively be utilized.

By forming the marks805over the encapsulant401and without extending over the first semiconductor device201or the second semiconductor device301, such that the marks805are over the fan out area, any damage that may occur because of an ill-controlled kerf depth during the marking process801may be mitigated. Additionally, any backside induced heat spot effects or other damage may be reduced or eliminated. All such improvements help to increase the yield and efficiency of the manufactured devices.

FIG.13illustrates another embodiment which uses a wobble marking process1300to form the first line807, and which may or may not be used with an overlap count greater than one or two. In this embodiment, rather than using the laser beam pulses804that had the first diameter D1which is equal to the dot width Wdof the first line807(as described above with respect toFIG.8B), a series of wobble laser beam pulses1301(only the first of which is illustrated inFIG.13for clarity) with a second diameter D2that may be similar to the first diameter D1are utilized to form an outline1303that extends from a first side1305of the first line807to a second side1308of the first line807, wherein the outline1303will extend across the dot width Wdto form the first line807. In an embodiment the wobble laser beam pulses1301have the second diameter D2, which may be between about 20 μm and about 120 μm, such as about 50 μm. Additionally, the wobble laser beam pulses1301may have an energy density of between about 1.0×10−3J/mm2and about 5.0×10−2J/mm2, such as about 1.5×10−2J/mm2, and the polymer layer105is exposed for a time period of between about 1.0×10−5sec and about 8.0×10−5sec, such as about 2.8×10−5sec.

In order to form the first line807using the wobble marking process1300, a scan trace path1307may initially be generated where the first line807is desired to be formed. While the scan trace path1307is not physically formed within the polymer layer105, the scan trace path1307may be used by the laser control machine to place a series of wobble scan laser beam pulse exposures (represented inFIG.13by the dashed circles labeled1309).

To begin the scan trace path1307, the dot width Wdis identified, and a line representative of the first side1305of the first line807and a line representative of the second side1308of the first line807are identified. In an embodiment the dot width Wdof the first line807in the wobble marking process1300is between about 200 μm and about 80 μm, such as about 150 μm. However, any suitable length for the dot width Wdmay be utilized.

Once the dot width Wdhas been identified, and the first side1305of the first line807and the second side1308of the first line807have been identified, the scan trace path1307may be identified. In an embodiment a series of points1313(labeled in order from 1-38 inFIG.13) may be placed in relation to a center line1311(between the first side1305and the second side1308of the first line807), the first side1305, and the second side1308of the first line807. The precise location of the series of points1313may be stored in, e.g., a computer readable storage medium such as a hard drive or other memory device. Once the series of points1313have been placed, individual arcs of the scan trace path1307may be formed to extend in order (e.g., from point “1” to point “2” and from point “2” to point “3”) between the points and form the scan trace path1307in preparation for the wobble laser beam pulses1301.

Overall, the individual arcs of the scan trace path1307may collectively form a circular path that “wobbles” through the center line1311from the first side1305of the first line807to the second side1308of the first line807. In an embodiment the scan trace path1307(after making at least a first full rotation) will, after crossing the center line1311, cross itself at least once, if not more, before again crossing the center line1311. In a particular embodiment, the intersection of the scan trace path1307with the center line1311as the scan trace path1307moves from point to point may be a crossing distance Dcof between about 50 μm and about 200 μm, such as about 100 μm.

However, while the scan trace path1307may maintain a relatively constant distance between intersections with the center line1311, a constant distance is not intended to be limiting upon the embodiments. Rather, the crossing distance Dcmay be variable along the scan trace path1307, such that the scan trace path1307may have varying distances of intersection along the first line807. Any suitable length may be used for the crossing distance Dcat any point along the scan trace path1307.

Once the scan trace path1313has been determined, the series of wobble laser beam pulses1301may be used to form the series of wobble laser beam pulse exposures1309(only a small number of which are illustrated inFIG.13) along the scan trace path1307, with individual ones of the series of wobble laser beam pulse exposures corresponding with a respective one of the points (e.g., point “1,” point “2,” point “3,” etc.) as the exposures follow the marking trajectory along the labels #1, #2, #3, etc. In an embodiment the wobble laser beam pulses exposures1309are formed at least partially overlapping each other in order to form the outline1303for the first line807. For example, the second wobble laser beam pulse exposure13092(at point “2”) may be offset from the first wobble laser beam pulse exposure13091(at point “1”) by an offset of between about 5 μm and about 100 μm, such as about 50 μm. However, any suitable offset between the second wobble laser beam pulse exposure13092and the first wobble laser beam pulse exposure13091may be used.

The series of wobble laser beam pulses1301is used to form the series of wobble laser beam pulse exposures1309along the scan trace path1307. As the series of wobble laser beam pulse exposures1309are formed the outline1303will create the first line807. By continuing the scan trace path1307and the formation of the wobble laser beam pulse exposures1309along the scan trace path1307, the first line807may be made in any desired length or shape.

Additionally, once the first line807is formed, it may be combined with other lines to form any desired characters. However, by forming the first line807using the wobble laser beam pulse exposures1309, the overall amount of material from the polymer layer105that is removed is reduced from within the first line807. As such, fewer defects may be caused.

FIG.14illustrates a mark805formed using the first line807formed with the wobble marking process1300(seeFIG.13). As illustrated, the outline1303formed using the wobble marking process1300can be used to form characters, such as the letter “T”, “S”, “M”, and “C.” However, by using the wobble laser beam pulses1301, the letters are not solid but are, rather, outlined using the wobble laser beam pulse exposures1309(not individually illustrated inFIG.14), and a smaller portion of the polymer layer105is removed for each line (e.g., the first line807). Such a reduction helps to mitigate or eliminate defects caused by the laser marking process.

Additionally, if desired, the first line807formed using the wobble marking process1300may be used by itself or else combined with the other processes described above with respect toFIGS.8A-12. For example, the wobble marking process1300may be used to make lines that are utilized in the cross-free characters as described above, or else may be used to make line that intersect with a reduced overlap count. Additionally, lines formed using the wobble marking process1300may be formed over the first region403of the encapsulant401without extending over the first semiconductor device201and the second semiconductor device301. All suitable combinations of the processes described herein are fully intended to be included within the scope of the embodiments.

FIG.15illustrates that, once the marks805have been formed within the polymer layer105, the structure may be bonded to a second package to form a first integrated fan out package-on-package (InFO-POP) structure1600(seeFIG.16).FIG.15illustrates a bonding of backside ball pads1501to a first package1500. In an embodiment the backside ball pads1501may be used to protect the exposed vias111and comprise a conductive material such as solder paste or an oxygen solder protection (OSP), although any suitable material may alternatively be utilized. In an embodiment the backside ball pads1501may be applied using a stencil, although any suitable method of application may alternatively be utilized, and then reflowed in order to form a bump shape.

The first package1500may comprise a third substrate1503, a third semiconductor device1505, a fourth semiconductor device1507(bonded to the third semiconductor device1505), third contact pads1509, a second encapsulant1511, and fourth external connections1513. In an embodiment the third substrate1503may be, e.g., a packaging substrate comprising internal interconnects (e.g., through substrate vias1515) to connect the third semiconductor device1505and the fourth semiconductor device1507to the backside ball pads1501.

Alternatively, the third substrate1503may be an interposer used as an intermediate substrate to connect the third semiconductor device1505and the fourth semiconductor device1507to the backside ball pads1501. In this embodiment the third substrate1503may be, e.g., a silicon substrate, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. However, the third substrate1503may alternatively be a glass substrate, a ceramic substrate, a polymer substrate, or any other substrate that may provide a suitable protection and/or interconnection functionality. These and any other suitable materials may alternatively be used for the third substrate1503.

The third semiconductor device1505may be a semiconductor device designed for an intended purpose such as being a logic die, a central processing unit (CPU) die, a memory die (e.g., a DRAM die), combinations of these, or the like. In an embodiment the third semiconductor device1505comprises integrated circuit devices, such as transistors, capacitors, inductors, resistors, first metallization layers (not shown), and the like, therein, as desired for a particular functionality. In an embodiment the third semiconductor device1505is designed and manufactured to work in conjunction with or concurrently with the first semiconductor device201.

The fourth semiconductor device1507may be similar to the third semiconductor device1505. For example, the fourth semiconductor device1507may be a semiconductor device designed for an intended purpose (e.g., a DRAM die) and comprising integrated circuit devices for a desired functionality. In an embodiment the fourth semiconductor device1507is designed to work in conjunction with or concurrently with the first semiconductor device201and/or the third semiconductor device1505.

The fourth semiconductor device1507may be bonded to the third semiconductor device1505. In an embodiment the fourth semiconductor device1507is only physically bonded with the third semiconductor device1505, such as by using an adhesive. In this embodiment the fourth semiconductor device1507and the third semiconductor device1505may be electrically connected to the third substrate1503using, e.g., wire bonds1517, although any suitable electrical bonding may be alternatively be utilized.

Alternatively, the fourth semiconductor device1507may be bonded to the third semiconductor device1505both physically and electrically. In this embodiment the fourth semiconductor device1507may comprise fourth external connections (not separately illustrated inFIG.15) that connect with fifth external connection (also not separately illustrated inFIG.15) on the third semiconductor device1505in order to interconnect the fourth semiconductor device1507with the third semiconductor device1505.

The third contact pads1509may be formed on the third substrate1503to form electrical connections between the third semiconductor device1505and, e.g., the fourth external connections1513. In an embodiment the third contact pads1509may be formed over and in electrical contact with electrical routing (such as through substrate vias1515) within the third substrate1503. The third contact pads1509may comprise aluminum, but other materials, such as copper, may alternatively be used. The third contact pads1509may be formed using a deposition process, such as sputtering, to form a layer of material (not shown) and portions of the layer of material may then be removed through a suitable process (such as photolithographic masking and etching) to form the third contact pads1509. However, any other suitable process may be utilized to form the third contact pads1509.

The second encapsulant1511may be used to encapsulate and protect the third semiconductor device1505, the fourth semiconductor device1507, and the third substrate1503. In an embodiment the second encapsulant1511may be a molding compound and may be placed using a molding device (not illustrated inFIG.15). For example, the third substrate1503, the third semiconductor device1505, and the fourth semiconductor device1507may be placed within a cavity of the molding device, and the cavity may be hermetically sealed. The second encapsulant1511may be placed within the cavity either before the cavity is hermetically sealed or else may be injected into the cavity through an injection port. In an embodiment the second encapsulant1511may be a molding compound resin such as polyimide, PPS, PEEK, PES, a heat resistant crystal resin, combinations of these, or the like.

Once the second encapsulant1511has been placed into the cavity such that the second encapsulant1511encapsulates the region around the third substrate1503, the third semiconductor device1505, and the fourth semiconductor device1507, the second encapsulant1511may be cured in order to harden the second encapsulant1511for optimum protection. While the exact curing process is dependent at least in part on the particular material chosen for the second encapsulant1511, in an embodiment in which molding compound is chosen as the second encapsulant1511, the curing could occur through a process such as heating the second encapsulant1511to between about 100° C. and about 130° C., for about 60 sec to about 3000 sec. Additionally, initiators and/or catalysts may be included within the second encapsulant1511to better control the curing process.

However, as one having ordinary skill in the art will recognize, the curing process described above is merely an exemplary process and is not meant to limit the current embodiments. Other curing processes, such as irradiation or even allowing the second encapsulant1511to harden at ambient temperature, may alternatively be used. Any suitable curing process may be used, and all such processes are fully intended to be included within the scope of the embodiments discussed herein.

In an embodiment the fourth external connections1513may be formed to provide an external connection between the third substrate1503and, e.g., the backside ball pads1501. The fourth external connections1513may be contact bumps such as microbumps or controlled collapse chip connection (C4) bumps and may comprise a material such as tin, or other suitable materials, such as silver or copper. In an embodiment in which the fourth external connections1513are tin solder bumps, the fourth external connections1513may be formed by initially forming a layer of tin through any suitable method such as evaporation, electroplating, printing, solder transfer, ball placement, etc. Once a layer of tin has been formed on the structure, a reflow is performed in order to shape the material into the desired bump shape.

Once the fourth external connections1513have been formed, the fourth external connections1513are aligned with and placed into physical contact with the backside ball pads1501, and a bonding is performed. For example, in an embodiment in which the fourth external connections1513are solder bumps, the bonding process may comprise a reflow process whereby the temperature of the fourth external connections1513is raised to a point where the fourth external connections1513will liquefy and flow, thereby bonding the first package1500to the backside ball pads1501once the fourth external connections1513resolidifies.

FIG.15additionally illustrates the bonding of a second package1519to the backside ball pads1501. In an embodiment the second package1519may be similar to the first package1500, and may be bonded to the backside ball pads1501utilizing similar processes. However, the second package1519may also be different from the first package1500.

FIG.16illustrates a debonding of the third external connectors505from the ring structure601and a singulation of the structure to form the first integrated fan out package-on-package (InFO-POP) structure1600. In an embodiment the third external connectors505may be debonded from the ring structure601by initially bonding the first package1500and the second package1519to a second ring structure using, e.g., a second ultraviolet tape. Once bonded, the ultraviolet tape603may be irradiated with ultraviolet radiation and, once the ultraviolet tape603has lost its adhesiveness, the third external connectors505may be physically separated from the ring structure601.

Once debonded, a singulation of the structure to form the first InFO-POP structure1600is performed. In an embodiment the singulation may be performed by using a saw blade (not shown) to slice through the encapsulant401and the polymer layer105between the vias111, thereby separating one section from another to form the first InFO-POP structure1600with the first semiconductor device201. However, as one of ordinary skill in the art will recognize, utilizing a saw blade to singulate the first InFO-POP structure1600is merely one illustrative embodiment and is not intended to be limiting. Alternative methods for singulating the first InFO-POP structure1600, such as utilizing one or more etches to separate the first InFO-POP structure1600, may alternatively be utilized. These methods and any other suitable methods may alternatively be utilized to singulate the first InFO-POP structure1600.

In accordance with an embodiment, a semiconductor device comprising a semiconductor device with an encapsulant and a via extending through the encapsulant and laterally separated from the semiconductor device is provided. A protective layer is over the encapsulant and the via. A marking is within the protective layer, the marking comprising a cross-free character.

In accordance with another embodiment, a semiconductor device comprising a semiconductor die and a conductive via laterally separated from the semiconductor die is provided. An encapsulant is located between the semiconductor die and the conductive via, and a protective material over the encapsulant. A marking character is within the protective material, wherein the marking character has an overlap count of less than two.

In accordance with yet another embodiment, a semiconductor device comprising a semiconductor die laterally separated from a conductive via and an encapsulant encapsulating both the semiconductor die and the conductive via is provided. A layer of material is over the semiconductor die, the encapsulant, and the conductive via. A character is marked into the layer of material, wherein the character comprises a plurality of laser pulse exposure regions, each of the laser pulse exposure regions having a diameter of less than about 100 μm and each of which is aligned along a circular trace path, the circular trace path outlining the character.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.