Patent ID: 12260161

DETAILED DESCRIPTION

FIG.1is a diagram of a circuit simulation system100according to an embodiment of the present invention. The circuit simulation system100may comprise at least one processor circuit (e.g., one or more processor circuits), which may be collectively referred to as the processor circuit110, at least one memory circuit (e.g., one or more memory circuits), which may be collectively referred to as the memory circuit120, a bus130, and at least one storage device (e.g., one or more storage devices), which may be collectively referred to as the storage device140, where multiple elements such as the processor circuit110, the memory circuit120, the storage device140, etc. in the circuit simulation system100can be coupled to each other through the bus130, but the present invention is not limited thereto. In some embodiments, the architecture shown inFIG.1may vary. In addition, the processor circuit110can be arranged to control the operations of the circuit simulation system100, the memory circuit120can be arranged to temporarily store information for the circuit simulation system100, the bus130can be arranged to perform internal signal transmission for the circuit simulation system100, and the storage device140can be arranged to store information for the circuit simulation system100.

For better comprehension, the circuit simulation system100may be implemented with a server, a personal computer such as a desktop computer and a laptop computer, etc. In particular, the processor circuit110may be implemented with a processor/processor core, etc., the memory circuit120may be implemented with a random access memory (RAM) such as a dynamic random access memory (DRAM), etc., and the storage device140can be implemented with a hard disk drive, a solid state drive (SSD), etc.

The memory circuit120can store a plurality of program codes120C. The circuit simulation system100(e.g., the processor circuit110) can load the program code140C stored in the storage device140into the memory circuit120to be the program code120C. The program code140C may comprise an operating system, drivers, applications, etc., for being executed by processor circuit110to control the operations of circuit simulation system100when loaded into memory circuit120. In particular, the processor circuit110may be arranged to execute the program code120C to establish a variation model related to circuit characteristics for performing circuit simulation. For example, the program code120C may comprise a variation model establishment procedure122, a performance simulation result expansion procedure124, and a circuit simulation procedure126, and the processor circuit110may execute the variation model establishment procedure122, the performance simulation result expansion procedure124and the circuit simulation procedure126to configure one or more sub-circuits (e.g., one or more processors/processor cores) of the processor circuit110into a variation model establishment module112, a performance simulation result expansion module114and a circuit simulation module116among a plurality of functional modules110M, respectively, for performing the variation model establishment, the performance simulation result expansion and the circuit simulation, respectively. The storage device140may store at least one netlist file (e.g., one or more netlist files), which may be collectively referred to as the netlist file142, predetermined process model data144and at least one variation model (e.g., one or more variation models), which can be collectively referred to as the variation model VM. The circuit simulation system100(e.g., the processor circuit110) can perform the variation model establishment, and more particularly, establish the variation model VM comprising a plurality of performance simulation results {PSR} according to the netlist file142and the predetermined process model data144, for performing the circuit simulation to generate at least one circuit simulation result such as a circuit simulation result CSR.

FIG.2is a flowchart of a method for establishing a variation model related to circuit characteristics for performing circuit simulation according to an embodiment of the present invention, where the method can be applied to the circuit simulation system100shown inFIG.1.

In Step S210, the processor circuit110may perform parallel processing, and more particularly, perform the respective operations of the sub-steps S211-S214of Step S210in parallel.

In Step S211, the processor circuit110may perform a plurality of first Monte Carlo simulation operations in parallel according to the netlist file142and the predetermined process model data144to generate a first performance simulation result such as a performance simulation result PSR(1, 1), where the netlist file142can be arranged to indicate a basic circuit in a circuit system, but the present invention is not limited thereto. For example, the basic circuit may represent any basic circuit of a plurality of basic circuits (such as a plurality of standard cells) in the circuit system, and the netlist file142may be arranged to indicate the plurality of basic circuits.

In Step S212, the processor circuit110may perform a plurality of second Monte Carlo simulation operations in parallel according to the netlist file142and the predetermined process model data144to generate a second performance simulation result such as a performance simulation result PSR(M1, 1), where the symbol “M1” can represent a positive integer greater than one.

In Step S213, the processor circuit110may perform a plurality of third Monte Carlo simulation operations in parallel according to the netlist file142and the predetermined process model data144to generate a third performance simulation result such as a performance simulation result PSR(1, M2), where the symbol “M2” can represent a positive integer greater than one.

In Step S214, the processor circuit110may perform a plurality of fourth Monte Carlo simulation operations in parallel according to the netlist file142and the predetermined process model data144to generate a fourth performance simulation result such as a performance simulation result PSR(M1, M2).

In Step S220, the processor circuit110may execute the performance simulation result expansion procedure124according to the first performance simulation result, the second performance simulation result, the third performance simulation result and the fourth performance simulation result, to generate a plurality of performance simulation results {PSR} to establish the variation model VM, where the number of the plurality of performance simulation results {PSR} in the variation model VM is greater than four.

For better comprehension, in the situation where the first performance simulation result, the second performance simulation result, the third performance simulation result and the fourth performance simulation result represent the performance simulation results PSR(1, 1), PSR(M1, 1), PSR(1, M2) and PSR(M1, M2), respectively, the plurality of performance simulation results {PSR} may comprise (M1*M2) performance simulation results {{PSR(1, 1), . . . , PSR(M1, 1)}, . . . , {PSR (1, M2), . . . , PSR(M1, M2)}}. For example, the performance simulation results PSR(1, 1), PSR (M1, 1), PSR(1, M2), and PSR (M1, M2) may represent boundary values corresponding to boundary conditions, and the processor circuit110may perform interpolation operations according to the performance simulation results PSR(1, 1), PSR(M1, 1), PSR (1, M2) and PSR (M1, M2) to generate corresponding interpolation results as the remaining performance simulation results (the performance simulation results except the performance simulation results PSR (1, 1), PSR(M1, 1), PSR(1, M2) and PSR(M1, M2)) among the (M1*M2) performance simulation results {{PSR (1, 1), . . . , PSR (M1, 1)}, . . . , {PSR (1, M2), . . . , PSR (M1, M2)}}, but the present invention is not limited thereto. In some embodiments, the processor circuit110may perform interpolation and/or extrapolation operations according to the performance simulation results PSR (1, 1), PSR (M1, 1), PSR (1, M2) and PSR (M1, M2) to generate corresponding interpolation and/or extrapolation results as the remaining performance simulation results (the performance simulation results except the performance simulation results PSR (1, 1), PSR (M1, 1), PSR (1, M2) and PSR (M1, M2)) among the plurality of performance simulation results {PSR}.

In addition, the plurality of basic circuits and the plurality of standard cells may be referred to as basic circuits #1, #2 . . . and #K and standard cells #1, #2 . . . and #K, respectively, and the any basic circuit may be referred to as any basic circuit #k, where the basic circuit index k may be a positive integer in the interval [1, K], and the total number K of basic circuits #1, #2 . . . and #K may be a positive integer greater than or equal to one thousand, but the present invention is not limited thereto. The plurality of performance simulation results {PSR} may represent a set of performance simulation results {PSRk} corresponding to the any basic circuit #k among the K sets of performance simulation results { {PSR1}, {PSR2}, . . . , {PSRK}} respectively corresponding to the basic circuits #1, #2 . . . and #K, and the number of performance simulation results in each set of performance simulation results (such as this set of performance simulation results {PSRk}) among the K sets of performance simulation results {{PSR1}, {PSR2}, . . . , {PSRK}} in the variation model VM is greater than four. For example, basic circuits #1, #2 . . . and #K (such as standard cells #1, #2 . . . and #K) may comprise an inverter, an AND gate, an OR gate, etc.

Regarding the any basic circuit #k among the basic circuits #1, #2 . . . and #K, the processor circuit110may perform the plurality of first Monte Carlo simulation operations, the plurality of second Monte Carlo simulation operation, the plurality of third Monte Carlo simulation operations, and the plurality of fourth Monte Carlo simulation operations in Steps S211-S214to generate the first performance simulation result, the second performance simulation result, the third performance simulation result and the fourth performance simulation result corresponding to the any basic circuit #k, respectively, and more particularly, in Step S220, execute the performance simulation result expansion procedure124according to the first performance simulation result, the second performance simulation result, the third performance simulation result and the fourth performance simulation result corresponding to the any basic circuit #k to generate the set of performance simulation results { PSRk} corresponding to the any base circuit #k to establish the variation model VM.

In Step S230, the processor circuit110may perform the circuit simulation to generate at least one circuit simulation result of the circuit system according to one or more performance simulation results among the plurality of performance simulation results. For example, regarding basic circuits #1, #2 . . . and #K in the circuit system, the circuit simulation may comprise:(1) selecting respective subsets of the K sets of performance simulation results {{PSR1}, {PSR2}, . . . , {PSRK}} from the K sets of performance simulation results {{PSR1}, {PSR2}, . . . , {PSRK}} according to a plurality of component parameters, and more particularly, selecting the performance simulation results that match the current values of the plurality of component parameters to be the above-mentioned respective subsets of the K sets of performance simulation results {{PSR1}, {PSR2}, . . . , {PSRK}}; and(2) generating the above-mentioned at least one circuit simulation result of the circuit system according to the above-mentioned respective subsets of the K sets of performance simulation results {{PSR1}, {PSR2}, . . . , {PSRK}};wherein, each subset of the respective subsets of the K sets of performance simulation results {{PSR1}, {PSR2}, . . . , {PSRK}} may comprise one or more performance simulation results, but the invention is not limited thereto. For example, the loop comprising Steps S230and S240allows the processor circuit110to re-perform the circuit simulation, and the processor circuit110can select the performance simulation results that match the latest values of the plurality of component parameters to be the latest versions of the above-mentioned respective subsets of the K sets of performance simulation results {{PSR1}, {PSR2}, {PSRK}}, for generating the latest version of the above-mentioned at least one circuit simulation result.

In Step S240, the processor circuit110may determine whether the above-mentioned at least one circuit simulation result (which is just generated in Step S230) meets a predetermined circuit design specification. If Yes (i.e., it meets the predetermined circuit design specification), end the working flow shown inFIG.2; If No (i.e., it does not meet the predetermined circuit design specification), the Step S230is entered to re-perform the circuit simulation. For example, the processor circuit110can selectively re-perform the circuit simulation according to the at least one circuit simulation result, where whether to re-perform the circuit simulation is determined according to whether the at least one circuit simulation result meets the predetermined circuit design specification.

Assuming that the determination result of Step S240is No, and therefore Step S230is entered to re-perform the circuit simulation. In this situation, regarding basic circuits #1, #2 . . . and #K in the circuit system, the circuit simulation may further comprise:(1) updating (e.g., modifying) the plurality of component parameters; and(2) selecting respective new subsets (which can be regarded as the latest versions of the above-mentioned subsets) of the K sets of performance simulation results {{PSR1}, {PSR2}, {PSRK}} from the K sets of performance simulation results {{PSR1}, {PSR2}, . . . , {PSRK}} according to the plurality of component parameters that have been updated, and more particularly, selecting the performance simulation results that match the latest values of the plurality of component parameters to be the above-mentioned respective new subsets of the K sets of performance simulation results {{PSR1}, {PSR2}, {PSRK}}, for generating at least one new circuit simulation result (which can be regarded as the latest version of the above-mentioned at least one circuit simulation result) of the circuit system;wherein, the processor circuit110can determine in Step S240whether the above-mentioned at least one circuit simulation result (which is just generated in Step S230), such as the latest version thereof, meets the predetermined circuit design specification, for determining whether to re-perform the circuit simulation (once again).

For better comprehension, the method can be illustrated with the working flow shown inFIG.2, but the present invention is not limited thereto. According to some embodiments, one or more steps may be added, deleted or changed in the working flow shown inFIG.2.

According to some embodiments, the processor circuit110executing the performance simulation result expansion procedure124may perform the performance simulation result expansion based on machine learning according to the first performance simulation result, the second performance simulation result, the third performance simulation result and the fourth performance simulation result to generate the plurality of performance simulation results {PSR} to establish the variation model VM. For example, the processor circuit110may perform the interpolation operations based on machine learning according to the performance simulation results PSR (1, 1), PSR (M1, 1), PSR (1, M2) and PSR (M1, M2) to generate the corresponding interpolation results as the remaining performance simulation results among the (M1*M2) performance simulation results {{PSR (1, 1), . . . , PSR (M1, 1)}, . . . , {PSR (1, M2), . . . , PSR (M1, M2)}}, where the distribution of the (M1*M2) performance simulation results {{PSR (1, 1), . . . , PSR (M1, 1)}, . . . , {PSR (1, M2), . . . , PSR (M1, M2)}} can be linear or nonlinear. For another example, the processor circuit110may perform the interpolation and/or extrapolation operations based on machine learning according to the performance simulation results PSR(1, 1), PSR(M1, 1), PSR(1, M2) and PSR(M1, M2) to generate the corresponding interpolation and/or extrapolation results as the remaining performance simulation results among the plurality of performance simulation results {PSR}, where the distribution of the (M1*M2) performance simulation results {{PSR (1, 1), . . . , PSR (M1, 1)}, . . . , {PSR (1, M2), . . . , PSR (M1, M2)}} can be linear or nonlinear.

According to some embodiments, M1=M2=M, where the symbol “M” may represent a positive integer greater than one, but the invention is not limited thereto.

FIG.3illustrates a first variation model establishment control scheme of the method according to an embodiment of the present invention. During performing the variation model establishment, the processor circuit110executing the variation model establishment procedure122may perform a set of operations310for generating random samples and a set of operations320for estimating standard deviation (which may be represented by the notation “σ”) from the sample data (labeled as “Generate random sample” and “Estimate σ from sample data” for brevity, respectively), and more particularly, perform the Monte Carlo simulation operations according to a set of corresponding parameter values for any random sample (e.g., each random sample) of these random samples to generate the performance simulation result corresponding to the any basic circuits #k, to establish the variation model VM, where the variation model VM may comprise at least one Liberty Variation Format library (LVF library)330such as a Monte Carlo (MC) LVF library, and the parameters Vth and Tox can be taken as examples of the plurality of component parameters, but the invention is not limited thereto. For example, a certain performance simulation result of these performance simulation results may comprise the simulation result of the distribution of the delay DELAY of the output signal to the input signal of the any basic circuit #k, such as the delay values DELAYNOMINAL, DELAYEARLYand DELAYLATEand the standard deviation σEARLYand σLATE, with respect to a nominal point.

For better comprehension, assume that a user of the circuit simulation system100has sufficient time (e.g., more than three months), and that it is permissible to spend a lot of time performing a large number of Monte Carlo simulation operations. The processor circuit110executing the variation model establishment procedure122can generate this set of performance simulation results {PSRk} corresponding to the any basic circuit #k according to the first variation model establishment control scheme to establish the variation model VM, and more particularly, generate all performance simulation results {PSRk} in this set of performance simulation results {PSRk}, such as the simulation results of all possible combinations {{(Index1_1, Index2_1), . . . , (Index1_M1, Index2_1)}, . . . , {(Index1_1, Index2_M2), . . . , (Index1_M1, Index2_M2)}} of the respective predetermined candidate values Index1_1-Index1_M1and Index2_1-Index2_M2(that is, M1predetermined candidate values {Index1_1, Index1_2, . . . , Index1_M1} and M2predetermined candidate values {Index2_1, Index2_2, . . . , Index2_M2}) of the circuit characteristic indexes Index1 and Index2 of the any basic circuit #k, and the simulation results can comprise:(1) a set of delay values331such as delay values {DELAYNOMINAL(Index1, Index2)}, comprising:{{DELAYNOMINAL(Index1_1, Index2_1), . . . , DELAYNOMINAL(Index1_M1, Index2_1)}, . . . ,{DELAYNOMINAL(Index1_1, Index2_M2), . . . , DELAYNOMINAL(Index1_M1, Index2_M2)}};(2) a first set of standard deviations332such as standard deviations {σEARLY(Index1_1, Index2_1)}, comprising:{{σEARLY(Index1_1, Index2_1), . . . , σEARLY(Index1_M1, Index2_1)},{σEARLY(Index1_1, Index2_M2), . . . , σEARLY(Index1_M1, Index2_M2)}}; and(3) a second set of standard deviations333such as standard deviations {σLATE(Index1, Index2)}, comprising:{{σLATE(Index1_1, Index2_1), . . . , σLATE(Index1_M1, Index2_1)},{σLATE(Index1_1, Index2_M2), . . . , σLATE(Index1_M1, Index2_M2)}};wherein, the delay value DELAYNOMINAL(Index1_i, Index2_j) and the standard deviations σEARLY(Index1_i, Index2_j) and σLATE(Index1_i, Index2_j) corresponding to the same combination (Index1_i, Index2_j) can be regarded as a performance simulation result PSRkin the set of performance simulation results {PSRk}.

For example, this set of performance simulation results {PSRk} corresponding to the any basic circuit #k may comprise (M1*M2) performance simulation results {{PSRk(1, 1), . . . , PSRk(M1, 1)}, . . . , {PSRk(1, M2) . . . , PSRk(M1, M2)}}, which can be collectively referred to as the performance simulation results {PSRk(i, j)|i=1, 2, . . . , M1; j=1, 2, . . . , M2}, and any performance simulation result PSRk(i, j) of these performance simulation results {PSRk(i, j)} may comprise a delay value DELAYNOMINAL(Index1_i, Index2_j) and standard deviations σEARLY(Index1_i, Index2_j) and σLATE(Index1_i, Index2_j). As a result, this set of performance simulation results {PSRk} corresponding to the any basic circuit #k can be expressed as follows:
{PSRk(i,j)=(DELAYNOMINAL(Index1_i,Index2_j),σEARLY(Index1_i,Index2_j),σLATE(Index1_i,Index2_j))|i=1,2, . . . ,M1;j=1,2, . . . ,M2};
which can be equivalent to:
{(DELAYNOMINAL(Index1,Index2),σEARLY(Index1,Index2)σLATE(Index1,Index2))|Index1=Index1_1,Index1_2, . . . ,Index1_M1;Index2=Index2_1,Index2_2, . . . ,Index2_M2};
but the present invention is not limited thereto.

Since it is very time-consuming to generate all performance simulation results {PSRk} in this set of performance simulation results {PSRk}, in the processor circuit110, the variation model establishment module112(e.g., the processor circuit110executing the variation model establishment procedure122) can generate only the performance simulation results PSRk(1, 1), PSRk(M1, 1), PSRk(1, M2) and PSRk(M1, M2) among this set of performance simulation results {PSRK} in steps S211-S214, and call the performance simulation result expansion module114(e.g., the processor circuit110executing the performance simulation result expansion procedure124) to perform the performance simulation result expansion (e.g., the performance simulation result expansion based on machine learning) according to the performance simulation results PSRk(1, 1), PSRk(M1, 1), PSRk(1, M2) and PSRk(M1, M2) in Step S220, to generate all performance simulation results {PSRk} in this set of performance simulation results {PSRk} to complete the establishment of the variation model VM, to allow the circuit simulation module116(e.g., the processor circuit110executing the circuit simulation procedure126) to refer to the variation model VM in Step S230to perform the circuit simulation. Therefore, the circuit simulation system100operating according to the method can simultaneously enhance circuit simulation speed and maintain circuit simulation accuracy without being hindered by the trade-off between circuit simulation speed and circuit simulation accuracy.

FIG.4illustrates some implementation details of the first variation model establishment control scheme as shown inFIG.3according to an embodiment of the present invention, where the horizontal axis may represent the voltage VOLTAGE, which can be measured in volts (V), and the vertical axis may represent the delay DELAY, which can be normalized inFIG.4. The variation model VM may comprise this set of performance simulation results {PSRk} corresponding to the any basic circuit #k, such as {PSRk(i, j)=(DELAYNOMINAL(Index1_i, Index2_j), σEARLY(Index1_i, Index2_j), σLATE(Index1_i, Index2_j))|i=1, 2, . . . , M1; j=1, 2, . . . , M2}, to indicate the distribution of the delay DELAY of the any basic circuit #k (e.g., the inverter) with respect to the voltage VOLTAGE applied to the any basic circuit #k, but the present invention is not limited thereto. For brevity, similar descriptions for this embodiment are not repeated in detail here.

FIG.5illustrates another variation model establishment control scheme. Assume that the processor circuit110executing the variation model establishment procedure122can generate this set of performance simulation results {PSRk} corresponding to the any basic circuit #k according to the other variation model establishment control scheme (i.e., the above-mentioned another variation model establishment control scheme) to establish the variation model VM, and more particularly, generate all performance simulation results {PSRk} in this set of performance simulation results {PSRk}. In this situation, the processor circuit110can perform the extrapolation/interpolation based on machine learning (ML) (hereinafter ML-based extrapolation/interpolation)520according to a reference corner LVF library511and a target corner list512, and more particular, generate the ML LVF library530. Typically, the term “corner” can represent a combination of process, voltage and temperature, such as a condition formed with a set of Process-Voltage-Temperature (P-V-T). The reference corner LVF library511may comprise the performance requirement information for a set of predetermined corners (e.g., a set of predetermined P-V-T conditions), and the target corner list512may comprise a set of target corners (e.g., a set of target P-V-T). Based on the other variation model establishment control scheme, since no Monte Carlo simulation operation is required, the speed of generating the ML LVF library530can be very fast. However, the accuracy of the ML LVF library530can be considerably low.

FIG.6illustrates a second variation model establishment control scheme of the method according to an embodiment of the present invention. For better comprehension, the reference corner LVF library611and the target corner list612may be equivalent to the reference corner LVF library511and the target corner list512, respectively, and the ML-based extrapolation/interpolation620can be the same as or similar to the ML-based extrapolation/interpolation520. The shrinkage index table LVF library613may represent at least one portion (e.g., a portion or all) of the LVF library330, and more particularly, a compact version of the LVF library330rather than a complete version of the LVF library330, where the complete version may comprise all performance simulation results {PSRk} in this set of performance simulation results {PSRk} corresponding to the any basic circuit #k, and the compact version may comprise the performance simulation results PSRk(1, 1), PSRk(M1, 1), PSRk(1, M2) and PSRk(M1, M2) in this set of performance simulation results {PSRk}.

For example, the variation model establishment module112may generate only the performance simulation results PSRk(1, 1), PSRk(M1, 1), PSRk(1, M2) and PSRk(M1, M2) in this set of performance simulation results {PSRk} in Steps S211-S214to establish the shrinkage index table LVF library613, and call the performance simulation result expansion module114to perform the ML-based extrapolation/interpolation620according to the performance simulation results PSRk(1, 1), PSRk(M1, 1), PSRk(1, M2) and PSRk(M1, M2) in the shrinkage index table LVF library613in Step S220to generate all performance simulation results {PSRk} in this set of performance simulation results {PSRk} to complete the establishment of the variation model VM, and more particularly, establish the variation model VM such as the high accuracy LVF library630to allow the circuit simulation module116to refer to the variation model VM such as the high accuracy LVF library630in Step S230to perform the circuit simulation. For brevity, similar descriptions for this embodiment are not repeated in detail here.

FIG.7illustrates some implementation details of the second variation model establishment control scheme as shown inFIG.6according to an embodiment of the present invention. The upper half ofFIG.7indicates the complete version of the LVF library330, where the complete version may comprise all performance simulation results {PSRk} in this set of performance simulation results {PSRk} corresponding to the any basic circuit #k, for example, the above-mentioned set of delay values331such as the delay values {DELAYNOMINAL(Index1, Index2)}, the first set of standard deviations332such as the standard deviations {σEARLY(Index1, Index2)}, and the second set of standard deviations333such as the standard deviations {σLATE(Index1, Index2)}. In addition, the lower half ofFIG.7indicates that the shrinkage index table LVF library613can be implemented as the compact version of the LVF library330, where the compact version can comprise the performance simulation result PSRk(1, 1), PSRk(M1, 1), PSRk(1, M2) and PSRk(M1, M2) in this set of performance simulation results {PSRk}, for example, the respective subsets of the above-mentioned set of delay values331, the first set of standard deviations332and the second set of standard deviations333in the complete version, such as the delay values331S, the standard deviations332S and333S. For brevity, similar descriptions for this embodiment are not repeated in detail here.

FIG.8illustrates the accuracy of the second variation model establishment control scheme as shown inFIG.6according to an embodiment of the present invention, where the horizontal axis may represent the voltage VOLTAGE, which can be measured in volts (V), and the vertical axis may represent the delay DELAY, which can be measured in nanoseconds (ns). As shown in the lower right part of FIG.8, a plurality of sets of curves respectively corresponding to a plurality of voltage ranges can indicate the performance requirements of the reference corners. The complete version of the LVF library330can be generated based on the first variation model establishment control scheme, and can be very accurate. For example, a data point belonging to the complete version of the LVF library330(labeled “Belong to330” for brevity) can be very accurate and can be suitable for being a reference for the circuit simulation, making the simulation results of the circuit simulation be very close to the test results of the circuit system in mass production. In addition, the ML LVF library530can be generated based on the other variation model establishment control scheme, and the accuracy thereof can be considerably low. For example, a data point belonging to the ML LVF library530(labeled “Belong to530” for brevity) may be inaccurate and not suitable for being used as a reference for the circuit simulation since the ML LVF library530may cause the tests of the circuit system in mass production to be unsuccessful. Additionally, the high accuracy LVF library630can be generated based on the second variation model establishment control scheme, and is more accurate. For example, a data point belonging to the high accuracy LVF library630(labeled “Belong to630” for brevity) can also be very accurate and also suitable for being used as a reference for the circuit simulation, making the simulation results of the circuit simulation be very close to the test results of the circuit system in mass production. For brevity, similar descriptions for this embodiment are not repeated in detail here.

FIG.9illustrates the accuracy of the second variation model establishment control scheme as shown inFIG.6according to another embodiment of the present invention, where the horizontal and vertical axes represent the slew rate SLEW and the standard deviation σ, respectively, which can be measured in nanoseconds (ns). Since the slew rate SLEW of a certain signal can be expressed with the change of voltage per unit of time to indicate the slope of a partial waveform of this signal, for a predetermined voltage variation amount, the slew rate SLEW can also be expressed with time to indicate the same slope. The predetermined voltage variation amount may represent a main range in the voltage range (e.g., the interval [VMIN, VMAX]) defined by the minimum value VMINand the maximum value VMAXof the voltage of this signal, such as the interval [VMIN+((VMAX−VMIN)+PSLOW), VMAX−((VMAX−VMIN)*PSLEW)]. For better comprehension, the range parameter PSLEWmay be equal to 30%, but the present invention is not limited thereto. The range parameter PSLEWcan be equal to any value in the interval (0, 1), such as 5%, 10%, 15%, 20%, etc., as long as the implementation of the present invention is not hindered.

For example, a set of curves belonging to the complete version of the LVF library330(labeled “Belong to330” for brevity) can be very accurate and suitable for being used as a reference for the circuit simulation, making the simulation results of the circuit simulation be very close to the test results of the circuit system in mass production. In addition, a set of curves belonging to the ML LVF library530(labeled “Belong to530” for brevity) may be inaccurate and not suitable for being used as a reference for the circuit simulation since the ML LVF library530may cause the tests of the circuit system in mass production to be unsuccessful. Furthermore, a set of curves belonging to the high accuracy LVF library630(labeled as “Belong to630” for brevity) is also more accurate, and is also suitable for being used as a reference for the circuit simulation, making the simulation results of the circuit simulation be very close to the test results of the circuit system in mass production.FIG.9clearly indicates that the set of curves belonging to the ML LVF library530is not equal to (or cannot be considered equal to) the set of curves belonging to the complete version of the LVF library330(labeled with “0” for brevity), and the set of curves belonging to the high accuracy LVF library630is approximately equal to (or can be considered equal to) the set of curves belonging to the complete version of the LVF library330(labeled with “≅” for brevity). For brevity, similar descriptions for this embodiment are not repeated in detail here.

FIG.10illustrates a working flow of the method according to an embodiment of the present invention. The circuit simulation module116(e.g., the processor circuit110executing the circuit simulation procedure126) can perform the operations of Steps S1011-S1014, and more particularly, can refer to a design margin provided by an LVF library1030to perform the operations of Steps S1011and S1013, where the circuit simulation mentioned in Step S230may comprise the operations of Steps S1011-S1013. For example, the LVF library1030may comprise the at least one LVF library such as the high accuracy LVF library630.

In Step S1011, the circuit simulation module116may perform synthesis operations according to the LVF library1030to convert the information used for describing the operations of the circuit system into at least one portion of basic circuits among the basic circuits #1, #2, . . . and #K (such as the standard cells #1, #2 . . . and #K), for example, the basic circuits #1, #2, . . . and #K0, where the symbol “K0” can represent a positive integer less than or equal to K.

In Step S1012, the circuit simulation module116may perform placing and routing operations to establish a circuit system model of the circuit system.

In Step S1013, the circuit simulation module116may perform static timing analysis (STA) to generate at least one STA result as the above-mentioned at least one circuit simulation result in Step S230.

In Step S1014, the circuit simulation module116may determine whether the above-mentioned at least one circuit simulation result such as the above-mentioned at least one STA result (which is just generated in Step S1013) matches the predetermined circuit design specification. If Yes, end the working flow shown inFIG.10; if No, Step S1011is entered to re-perform the circuit simulation.

Assume that the determination result of Step S1014is No, and therefore Step S1011is entered to re-perform the circuit simulation. In this situation, regarding the above-mentioned at least one portion of the basic circuits among the basic circuits #1, #2 . . . and #K in the circuit system, such as the basic circuits #1, #2, . . . and #K0, the circuit simulation module116may update (e.g., change) the plurality of component parameters (labeled as “Change” for brevity), and in Step S1013, select the respective new subsets of the K0 sets of performance simulation results {{PSR1}, {PSR2}, . . . , {PSRK0}} from the K0 sets of performance simulation results {{PSR1}, {PSR2}, . . . , {PSRK0}} according to the plurality of component parameters that have been updated, and more particularly, select the performance simulation results that match the latest values of the plurality of component parameters to be the above-mentioned respective new subsets of the K0 sets of performance simulation results {{PSR1}, {PSR2}, . . . , {PSRK0}} for generating the latest version of the above-mentioned at least one circuit simulation result (e.g., the above-mentioned at least one STA result) of the circuit system, where the circuit simulation module116may determine in Step S1014whether the above-mentioned at least one circuit simulation result (just generated in Step S1013), such as the latest version thereof, meets the predetermined circuit design specification, for determining whether to re-perform the circuit simulation (once again). For brevity, similar descriptions for this embodiment are not repeated in detail here.

For better comprehension, the method can be illustrated with the working flow shown inFIG.10, but the present invention is not limited thereto. According to some embodiments, one or more steps may be added, deleted or changed in the working flow shown inFIG.10.

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.