Patent ID: 12253780

DETAILED DESCRIPTION OF EMBODIMENT

The following embodiments when read with the accompanying drawings are made to clearly exhibit the above-mentioned and other technical contents, features and effects of the present disclosure. Through the exposition by means of the specific embodiments, people would further understand the technical means and effects the present disclosure adopts to achieve the above-indicated objectives. Moreover, as the contents disclosed herein should be readily understood and can be implemented by a person skilled in the art, all equivalent changes or modifications which do not depart from the concept of the present disclosure should be encompassed by the appended claims.

Furthermore, the ordinals recited in the specification and the claims such as “first”, “second” and so on are intended only to describe the elements claimed and imply or represent neither that the claimed elements have any proceeding ordinals, nor that sequence between one claimed element and another claimed element or between steps of a manufacturing method. The use of these ordinals is merely to differentiate one claimed element having a certain designation from another claimed element having the same designation.

Furthermore, the ordinals recited in the specification and the claims such as “above”, “over”, or “on” are intended not only directly contact with the other substrate or film, but also intended indirectly contact with the other substrate or film.

Embodiment 1

FIG.1is a schematic cross sectional view of a display device of the present embodiment. Therein, the display device comprises: a first substrate1; a second substrate2opposite to the first substrate1; and a display medium layer3arranged between the first substrate1and the second substrate2. In the present embodiment, the first substrate1and the second substrate2may be prepared by glass, plastic, a flexible material or a thin film; but the present disclosure is not limited thereto. When the first substrate1and the second substrate2is prepared by the plastic, the flexible material or the thin film, the display device can be a flexible display device. In the present embodiment, the display medium3may comprise a liquid crystal layer, a light emitting diode (for example, an inorganic light emitting diode or an organic light emitting diode) or quantum dots; but the present disclosure is not limited thereto. In addition, in other embodiments of the present disclosure, when the display medium3is the light emitting diode, the display device can be optionally made without the second substrate2.

FIG.2is a top view of a display device of the present embodiment. As shown inFIG.1andFIG.2, the display device of the present embodiment comprises: a display region AA and a peripheral region B, and the peripheral region B is adjacent to the display region AA. As shown inFIG.2, the display device of the present embodiment comprises: a print circuit board11partially disposed on the peripheral region B; an IC12disposed on the peripheral region B and electrically connecting to the print circuit board11; a demultiplexer13(indicated as DeMux inFIG.3andFIG.7) disposed on the peripheral region B and electrically connecting to the IC12; a driver circuit14(indicated as Gate Driver inFIG.4andFIG.6) disposed on the peripheral region B and electrically connecting to the IC12; and plural pixel units15disposed on the display region AA, wherein the pixel units15receive signals from the driver circuit14and the demultiplexer13.

In the display device of the present embodiment, the first substrate1is provided with plural pixel units15, and at least one transistor is contained in each of the pixel units15. In the present embodiment, one transistor including an oxide semiconductor layer is comprised in one pixel unit15, but the present disclosure is not limited thereto. Furthermore, the driver circuit14and the demultiplexer13may also comprise plural transistors. The transistors used in the driver circuit14and the demultiplexer13can be a transistor comprising a silicon semiconductor layer (for example, low-temperature polycrystalline silicon (LTPS) thin film transistor) for the narrow border design. Hereinafter, the process for preparing the transistor including an oxide semiconductor layer disposed on the display region AA and the transistor including a silicon semiconductor layer disposed on the peripheral region B (i.e. the driver circuit14and the demultiplexer13) are illustrated in brief.

FIG.3andFIG.4are respectively schematic cross sectional views of the display device along line L1-L1′ and L2-L2′ shown inFIG.2. First, a first substrate1is provided, followed by forming a first insulating layer111on the first substrate1. Herein, the material of the first substrate1is illustrated before, and not repeated again. The first insulating layer111may comprise silicon oxide. In the present embodiment, the first insulating layer111is a silicon oxide layer.

Next, an amorphous silicon layer is formed on the first insulating layer111, and then an annealing process is applied onto the amorphous silicon layer to obtain a first semiconductor layer21which is a low temperature polysilicon layer. Herein, regions of the first semiconductor layer21that a first source electrode23and a first drain electrode24to be formed thereon are doped. After forming the first semiconductor layer21, a second insulating layer112is formed. Herein, the second insulating layer112may comprise silicon oxide. In the present embodiment, the second insulating layer112is a silicon oxide layer.

Then, a first gate electrode22and a second gate electrode31are formed on the second insulating layer112, followed by sequentially forming a third insulating layer113and a fourth insulating layer114. Herein, the third insulating layer113may comprise silicon nitride, and the fourth insulating layer114may comprise silicon oxide. In the present embodiment, the third insulating layer113is a silicon nitride layer, and the fourth insulating layer114is a silicon oxide layer.

A second semiconductor layer32being an oxide semiconductor layer is formed on the fourth insulating layer114, and then a first source electrode23, a first drain electrode24, a second source electrode33and a second drain electrode34are formed on the second semiconductor layer32and the fourth insulating layer114. Then, a first passivation layer115and an organic layer116are sequentially formed on the first source electrode23, the first drain electrode24, the second source electrode33and the second drain electrode34, followed by forming a first conductive layer41thereon. Herein, the first passivation layer114may comprise silicon oxide. In the present embodiment, the first passivation layer114is a silicon oxide layer. In addition, the organic layer116may comprise any organic materials.

Then, a second passivation layer117is formed on the first conductive layer41, followed by forming a second conductive layer42, in which the second conductive layer42is electrically connected to the second drain electrode34through a contact via43. Herein, the second passivation layer117may comprise silicon oxide, silicon nitride, or silicon nitroxide; but the present disclosure is not limited thereto. In addition, the first conductive layer41and the second conductive layer42can comprise a transparent conductive oxide, such as ITO, IZO, ITZO and the like.

After the aforesaid process, the display device of the present embodiment is obtained. As shown inFIG.3andFIG.4, the display device of the present embodiment comprises: a first substrate1; a first transistor TFT1 disposed on the a first substrate1, wherein the first transistor TFT1 comprises a first semiconductor layer21; a second transistor TFT2 disposed on the first substrate1, wherein the second transistor TFT2 comprises a second semiconductor layer32; and a first insulating layer111disposed under the first semiconductor layer21.

Herein, the first semiconductor layer21is a silicon semiconductor layer, and the second semiconductor layer32is an oxide semiconductor layer. The silicon semiconductor layer can be a low temperature polysilicon layer. The oxide semiconductor layer can be an IGZO layer, an ITZO layer or an IGTZO layer. In the present embodiment, the oxide semiconductor layer is the IGZO layer. Therefore, the first transistor TFT1 is an LTPS transistor, and the second transistor TFT2 is an IGZO transistor. However, the present disclosure is not limited thereto, as long as one of the first semiconductor layer and the second semiconductor layer comprises a silicon semiconductor layer and the other comprises an oxide semiconductor layer.

In addition, as shown inFIG.2toFIG.4, the display device of the present embodiment comprises a display region AA and a peripheral region B, wherein the peripheral region B is adjacent to the display region AA. The first transistor TFT1 is disposed on the peripheral region peripheral region B (i.e. the driver circuit14and the demultiplexer13), and the second transistor TFT2 is disposed on the display region AA.

As shown inFIG.3andFIG.4, the first insulating layer111can comprise silicon oxide. In the present embodiment, the first insulating layer111is a silicon oxide layer. In addition, a thickness T1 of the first insulating layer111can be greater than or equal to 200 nm and less than or equal to 500 nm. In another embodiment, the thickness T1 of the first insulating layer111can be greater than or equal to 250 nm and less than or equal to 400 nm. In further another embodiment, the thickness T1 of the first insulating layer111can be greater than or equal to 250 nm and less than or equal to 300 nm. When the thickness T1 of the first insulating layer111is within the aforesaid range, the first transistor TFT1 has desirable electrical performance. If the thickness T1 of the first insulating layer111is less than 200 nm (even less than 250 nm), the negative-bias-temperature-stress (NBTS) stability of the first transistor TFT1 with the silicon semiconductor layer is reduced. Therefore, in the display device of the present embodiment, the specific thickness range of the first insulating layer111is one factor relating to the performance of the first transistor TFT with the silicon semiconductor layer.

As shown inFIG.3andFIG.4, the display device of the present embodiment further comprise a second insulating layer112on the first semiconductor layer21, and the second insulating layer112comprises silicon oxide and contacts the first semiconductor layer21. In the present embodiment, the second insulating layer112is a silicon oxide layer. In addition, the thickness T1 of the first insulating layer111is greater than or equal to a thickness T2 of the second insulating layer112. Herein, a thickness T2 of the second insulating layer112can be greater than or equal to 100 nm and less than or equal to 200 nm. In another embodiment, the thickness T2 of the second insulating layer112can be greater than or equal to 100 nm and less than or equal to 150 nm. If the thickness T2 of the second insulating layer112is within the aforesaid range, the first transistor TFT with the silicon semiconductor layer has desirable electrical charging ability and low current leakage properties.

In the present embodiment and other embodiments of the present disclosure, a ratio is the thickness T1 of the first insulating layer111to the thickness T2 of the second insulating layer112, and the ratio can be greater than or equal to 1 and less than or equal to 5. In another embodiment, the ratio can be greater than or equal to 1.25 and less than or equal to 4. In further another embodiment, the ratio can be greater than or equal to 1.5 and less than or equal to 3.

In the present embodiment and other embodiments of the present disclosure, the term “thickness” refers to a maximum thickness of the indicated layer.

As shown inFIG.3andFIG.4, the second semiconductor layer32is disposed above the first insulating layer111. In addition, the display device of the present embodiment further comprises a third insulating layer113and a fourth insulating layer114, wherein the third insulating layer113is disposed above the first semiconductor layer21, the fourth insulating layer114is disposed on the third insulating layer113, the third insulating layer113comprises silicon nitride, the fourth insulating layer114comprises silicon oxide, and the second semiconductor layer32is directly disposed on the fourth insulating layer114. Furthermore, both the first gate electrode22and the second gate electrode31are disposed between the second insulating layer112and the third insulating layer113. Moreover, the first source electrode23, the first drain electrode24, the second source electrode33and the second drain electrode34are disposed on the fourth insulating layer114.

In the present embodiment, the first semiconductor layer21being a silicon semiconductor layer is disposed on the first insulating layer111, the second insulating layer112is the gate insulating layer of the first transistor TFT1, and the third insulating layer113and the fourth insulating layer114are the interlayer dielectric layer of the first transistor TFT1. On the other hand, the second semiconductor layer32being an oxide semiconductor layer is disposed on the fourth insulating layer114, the third insulating layer113and the fourth insulating layer114are the gate insulting layer of the second transistor TFT2, and the first passivation layer115is the back passivation for the second transistor TFT2. Hence, in the present embodiment, the gate insulating layers and the interlayer dielectric layers/passivation layers of the first transistor TFT1 and the second transistor TFT2 are different; and the interlayer dielectric layer of the first transistor TFT1 (i.e. the third insulating layer113and the fourth insulating layer114) are used as the gate insulating layer of the second transistor TFT2.

In addition, the first gate electrode22and the second gate electrode31are formed by the same layer, and the first source electrode23, the first drain electrode24, the second source electrode33and the second drain electrode34are formed by the same layer.

FIG.5Ais one enlarged view ofFIG.3, which shows an enlarged view of the first gate electrode22of the first transistor TFT1. As shown inFIG.3andFIG.5A, the first gate electrode22has a double layered structure comprising a fourth metal layer221and a fifth metal layer222, and the fourth metal layer221is disposed between the first substrate1and the fifth metal layer222. The fourth metal layer221is used as a barrier layer, and the material thereof may be Mo, Ti or an alloy thereof. The material of the fifth metal layer222may be Al, Cu or an alloy thereof. However, the present disclosure is not limited thereto. In addition, in the present embodiment, the second gate electrode31and the first gate electrode22have the same structures, and the structure of the second gate electrode31is not repeated again.

FIG.5Bis another enlarged view ofFIG.3, which shows an enlarged view of the second source electrode33of the second transistor TFT2. Herein, the second source electrode33has a triple layered structure comprising a first metal layer331, a second metal layer332and a third metal layer333, the first metal layer331contacts the second semiconductor layer32, and the second metal layer332is disposed between the first metal layer331and the third metal layer333. The first metal layer31is used as a barrier layer, and the material thereof may be Mo, Ti or an alloy thereof. The material of the second metal layer332may be Al, Cu or an alloy thereof. The third metal layer333is used as a capping layer, and the material thereof may be Mo, Ti or an alloy thereof. However, the present disclosure is not limited thereto. In addition, in the present embodiment, the first source electrode23, the first drain electrode24, the second source electrode33and the second drain electrode34have the same structures, and the structures of other electrodes are not repeated again.

As illustrated above, the second source electrode33and the second drain electrode34have a triple layered structure, in which the first metal layer331is used as a barrier layer. The material of the second metal layer332can be Al, Cu or an alloy thereof, which may combine with the oxygen atoms in the oxide semiconductor layer (i.e. the second semiconductor layer32). Hence, when the second source electrode33and the second drain electrode34comprise the first metal layer31as a barrier layer, the aforesaid shortage can be overcome.

Embodiment 2

The structure of the display device of the present embodiment is similar to that of Embodiment 1, andFIG.6is a schematic cross section view of the display device of the present embodiment along a line L2-L2′ shown inFIG.2.

In the present embodiment, the second insulating layer112comprises silicon oxide and contacts the first semiconductor layer21, and the second semiconductor layer32is disposed on the second insulating layer112. In addition, a fifth insulating layer112′ is further formed on the second semiconductor layer32and the second insulating layer112, and the fifth insulating layer112′ may also comprise silicon oxide. In the present embodiment, the second insulating layer112is an silicon oxide layer and the fifth insulating layer112′ is another silicon oxide layer, wherein the hydrogen atom percentage in the silicon oxide layer of the second insulating layer112may be within 5% and 10%, and the hydrogen atom percentage in the silicon oxide layer of the fifth insulating layer112′ may be below 3%.

In the present embodiment, the third insulating layer113is only formed on the peripheral region B, and not on the active region AA. In addition, the second transistor TFT2 has a top gate structure, and the second gate electrode31, the first source electrode23and the first drain electrode24are formed by the same layer. Herein, the dashed line between the first drain electrode24and the second gate electrode31means that the first drain electrode24and the second gate electrode31are electrically connected in other cross section view of the display device of the present embodiment.

Furthermore, the display device of the present embodiment further comprises a light shielding layer35disposed below the second semiconductor layer32. Herein, the light shielding layer35and the first semiconductor layer21are formed by the same layer; and therefore, the light shielding layer35comprises silicon semiconductor layer.

Embodiment 3

The structure of the display device of the present embodiment is similar to that of Embodiment 1, andFIG.7is a schematic cross section view of the display device of the present embodiment along a line L1-L1′ shown inFIG.2.

In the present embodiment, the display device further comprises: a first buffer layer1111disposed on the first substrate1; a second buffer layer1112disposed on the first buffer layer1111; a third buffer layer1113disposed on the second buffer layer1112; and a fourth buffer layer1114disposed on the third buffer layer1113and below the first insulating layer111. Herein, the first buffer layer1111, the third buffer layer1113and the first insulating layer111respectively comprise silicon oxide; and in the present embodiment, the first buffer layer1111, the third buffer layer1113and the first insulating layer111are respectively a silicon oxide layer. In addition, the second buffer layer1112and the fourth buffer layer1114respectively comprises silicon nitride; and in the present embodiment, the second buffer layer1112and the fourth buffer layer1114are respectively a silicon nitride layer. In addition, the fourth buffer layer1114directly contacts the first insulting layer111.

In the present embodiment and the forging embodiment, the first insulating layer111is formed on the first substrate1before forming the first semiconductor layer21, to prevent moisture or water molecules from degrading the semiconductor performances. In order to further prevent moisture or water molecules from degrading the semiconductor performances, in the present embodiment, the first buffer layer1111, the second buffer layer1112, the third buffer layer1113and the fourth buffer layer1114are sequentially formed on the first substrate1in advance, and then the first insulating layer111is formed on the fourth buffer layer1114.

Silicon nitride (Si3N4or SiNx) film has better moisture and water resistance property than silicon oxide (SiO2) film. Which is, when films are deposited using the same method at the same temperature and thickness, the water vapor transmission rate (WVTR) of the Si3N4and SiNxfilms are lower than the WVTR of Si2N2O and SiO2films. Hence, in the present embodiment, the first buffer layer1111, the second buffer layer1112, the third buffer layer1113, the fourth buffer layer1114and the first insulating layer111are alternating silicon oxide-silicon nitride layers, which can be formed by plasma enhanced chemical vapor deposited (PECVD) method. This multi-layered structure of alternating silicon nitride and silicon oxide layers can provide vertically continuous different levels of energy barrier to the layers, enhancing the moisture or water resistance; and this advantage is more significant when the first substrate1is a plastic substrate.

As shown inFIG.7, in the multi-layered structure of alternating silicon nitride and silicon oxide layer of the present embodiment, the topmost layer is the first insulating layer111which is a silicon oxide layer, and the silicon oxide layer as the first insulating layer111can avoid any alteration to the performance of the first semiconductor layer21.

Moreover, in the present embodiment, the first buffer layer1111directly contacts the first substrate1, and the first buffer layer1111is a silicon oxide layer to provide better adhesion with the first substrate1.

Test Example

FIG.8is a schematic cross section view of a LTPS transistor used in the present test example. As shown inFIG.8, the transistor used in the present test example comprises: a first substrate1; a light shielding layer25on the first substrate; a first buffer layer1111on the light shielding layer25, wherein the first buffer layer1111is a silicon oxide layer; a second buffer layer1112on the first buffer layer1111, wherein the second buffer layer1112is a silicon nitride layer; a third buffer layer1113on the second buffer layer1112, wherein the third buffer layer1113is a silicon oxide layer; a fourth buffer layer1114on the third buffer layer1113, wherein the fourth buffer layer1114is a silicon nitride layer; a first insulating layer111disposed on the fourth buffer layer1114, wherein the first insulating layer111is a silicon oxide layer; a first semiconductor layer21on the first insulating layer111; a second insulating layer112on the first semiconductor layer21; a first gate electrode22on the second insulating layer112; a third insulating layer113on the first gate electrode22; a first source electrode23and a first drain electrode24disposed on the third insulating layer113and electrically connected to the first semiconductor layer21; a first passivation layer115on the first source electrode23and the first drain electrode24; and a planer layer116disposed on the first passivation layer115.

In the present test example, the I-V curves of the LTPS transistors comprising the first insulating layers111with various thicknesses (i.e. 1000 Å, 1500 Å, 2000 Å, and 2500 Å) are examined after 1 hour operation; and the results are shown inFIG.9.

As shown inFIG.9, the LTPS transistors comprising the first insulating layers111with various thicknesses have similar initial I-V curves. However, if the thickness of the first insulating layer111is less than 200 nm (even less than 250 nm), the negative-bias-temperature-stress (NBTS) stability of the LTPS transistor is reduced. Therefore, the thinner the thickness of the first insulating layer111(the silicon oxide layer), the worse the NBTS stability.

It should be noted that as the thickness of the first insulating layer111increases, the surface roughness of the first insulating layer111increases. When the thickness of the first insulating layer111is near ˜300 nm, the surface roughness is too rough, so that the mobility of the LTPS transistors decreases significantly, resulting in the LTPS transistors with lower ON current.

In the present test example, the I-V curves of the LTPS transistors comprising the second insulating layers112with various thicknesses (i.e. 700 Å, 1000 Å, 1200 Å, 1500 Å, and 2500 Å) are examined; and the results are shown inFIG.10and the following Table 1.

TABLE 1Second insulatinglayer thicknessION(@Vg = 18 V)IOFF(@Vg = −4 V)700 Å6.63E−052.95E−131000 Å3.90E−053.88E−141200 Å2.74E−052.53E−141500 Å2.53E−052.84E−142500 Å8.42E−062.11E−14

As shown inFIG.10and Table 1, as the thickness of the second insulating layer112is decreased, IOFFis increased; and this indicates that current leakage may be occurred in the LTPS transistor. As the thickness of the second insulating layer112is increased, IONis reduced and sub-threshold swing is increased; and this indicates that the charging ability of the LTPS transistor is decreased. Therefore, in order to make the LTPS transistor have optimum electrical charging ability and low current leakage properties, the thickness of the second insulating layer112should be within 1000 Å and 1500 Å because stable IONand IOFFperformance can be achieved.

Other Embodiments

A display device made as described in any of the embodiments of the present disclosure as described previously may be integrated with a touch panel to form a touch display device. Moreover, a display device or touch display device made as described in any of the embodiments of the present disclosure as described previously may be applied to any electronic devices known in the art that need a display screen, such as displays, mobile phones, laptops, video cameras, still cameras, music players, mobile navigators, TV sets, and other electronic devices that display images.

Although the present disclosure has been explained in relation to its embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the disclosure as hereinafter claimed.