Patent ID: 12225707

DETAILED DESCRIPTION

The disclosure relates to a method for manufacturing a semiconductor structure, a semiconductor structure and a semiconductor memory.

A clear and complete description of the technical solutions of the embodiments of the disclosure will be provided below with reference to the drawings in the embodiments of the disclosure. It could be understood that the specific embodiments described herein are intended only to explain the relevant disclosure and not to limit the disclosure. In addition, it should be noted that for convenience of description, only parts related to the relevant disclosure are shown in the drawings.

Unless otherwise defined, all technical and scientific terms used herein have the same meanings as are commonly understood by those skilled in the art of the present disclosure. Terms used herein are for the purpose of describing embodiments of the disclosure only and are not intended to limit the disclosure.

In the following description, reference is made to “some embodiments” that describe a subset of all possible embodiments, but it could be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

It should be pointed out that, the terms “first\second\third” involved in embodiments of the disclosure is used only to distinguish similar objects, without representing a particular sequence of objects, it could be understood that “first\second\third” may be interchanged in a particular order or priority order where permitted, so that the embodiments of the disclosure described herein can be implemented in an order other than that illustrated or described herein.

With the increasing integration of the DRAM, the size and area of the capacitor of the DRAM also decrease relatively. For example, with the development of semiconductor industry towards higher device density and higher performance, 3 Dimension (3D) semiconductor devices, such as 3D memory, have been developed. With the development of 3D semiconductor devices, it is necessary to develop capacitors for 3D semiconductor devices. However, the process for manufacturing capacitors in 3D memory is complex and costly, which often cannot meet the practical needs.

On the basis of this, embodiments of the disclosure provide a method for manufacturing a semiconductor structure. The basic idea of this method is that: a substrate is provided; the substrate is patterned to form a substrate layer and a plurality of silicon pillars; an oxide layer is formed on a surface of the substrate layer between the plurality of silicon pillars; an isolation structure is formed on the oxide layer, and gaps are provided between an upper part of the isolation structure and the silicon pillars; a first conductive layer is formed in the gaps; part of the isolation structure is removed, the isolation structure below the first conductive layer is retained to form an isolation layer; a dielectric layer and a second conductive layer are formed on surfaces of the isolation layer, the oxide layer, the first conductive layer and the silicon pillars. In this way, when manufacturing a semiconductor structure, a gap is formed between the silicon pillar and the isolation structure, and a first conductive layer is formed in the gap, then part of the isolation structure is removed to obtain the isolation layer, and then a dielectric layer and a second conductive layer are further formed. This manufacturing method has a simple process, is easy to implement, and can improve the manufacturing yield.

The embodiments of the disclosure will be described in detail below with reference to the drawings.

Before the detailed description, it should be noted that, in the description of the following embodiments, the corresponding relationship between the reference numerals used in the drawings and each component in the semiconductor structure is as follows:10: substrate;11: substrate layer;12: silicon pillar;131: first mask layer;1311: first trench;132: second mask layer;1321: second trench;133: intermediate structure;134: sub-mask;141: initial oxide layer;14: oxide layer;151: initial first isolation structure;15: first isolation structure;16: sacrificial layer;171: initial second isolation structure;17: second isolation structure;181: initial first conductive layer;18: first conductive layer;19: isolation layer;20: dielectric layer;21: second conductive layer.

In embodiments of the disclosure, referring toFIG.1,FIG.1illustrates a flow chart of a method for manufacturing a semiconductor structure provided by embodiments of the disclosure. As shown inFIG.1, the method includes the following operations.

In S101, a substrate is provided;

It should be noted that the embodiments of the disclosure provide a method for manufacturing a semiconductor structure; the semiconductor structure may be a capacitor that may be applied to a semiconductor device having a 3D structure (e.g. a 3D DRAM structure). The method can be applied to a transistor on the capacitor (TOC) architecture for forming capacitors in the architecture.

Referring toFIG.2,FIG.2is a schematic structural diagram of the substrate10provided by embodiments of the disclosure. Herein, (a) and (b) are cross-sectional views, and (c) is a top view; (a) is a cross-sectional view along AA′ direction in (c), and (b) is a cross-sectional view along BB′ direction in (c).

It should also be noted that the substrate10may be a silicon substrate or be made of other suitable substrate material such as silicon, germanium, silicon-germanium compound, or the like, for example, a doped or undoped monocrystalline silicon substrate, a polysilicon substrate, or the like, which is not specifically limited. In the embodiments of the disclosure, a silicon substrate is described as an example.

In S102, the substrate is patterned to form a substrate layer and a plurality of silicon pillars.

It should be noted that the substrate10is patterned and divided into two parts: a substrate layer11and a plurality of silicon pillars12. Herein, the upper part of the substrate10is patterned to form the plurality of silicon pillars12, and the lower part of the substrate10is not patterned and forms a substrate layer11.

Referring toFIG.3,FIG.3is a schematic diagram of a structure obtained after forming the substrate layer11and the silicon pillars12provided by embodiments of the disclosure, in which (a) and (b) are cross-sectional views, and (c) is a top view; (a) is a cross-sectional view along AA′ direction in (c), and (b) is a cross-sectional view along BB′ direction in (c).

That is, (a) is a cross-sectional diagram in which the silicon pillars12are formed in the first direction, and (b) is a cross-sectional diagram between two adjacent ones of the silicon pillars12in the first direction, that is, a cross-sectional diagram in which the silicon pillars12are not formed. In addition, same asFIG.3, in the figures related to the following operations, (a) in the figures are all cross-sectional views in AA′ direction, (b) in the figures are cross-sectional views in BB′ direction, and (c) in the figures are all top views, which will not be repeated hereafter.

As shown inFIG.3, after the substrate10is patterned, the upper part of the substrate10is partially removed to form a plurality of silicon pillars12, and the part of the substrate10remaining under the plurality of silicon pillars12forms the substrate layer11. As shown in (a) ofFIG.3, a gap is formed between two adjacent ones of the silicon pillars12in AA′ direction; as shown in (b) ofFIG.3, no silicon pillar12is presented on the substrate layer11in BB′ direction; as shown in (c) ofFIG.3, a plurality of silicon pillars12are formed in this structure as can be seen from a top view.

Herein, the thickness of the substrate layer11and the height of the silicon pillars12can be set according to the specific requirements of the actual process level, which is not limited by the embodiments of the disclosure.

For the plurality of silicon pillars12, in some embodiments, the plurality of silicon pillars12are arranged in an array.

It should be noted that the plurality of silicon pillars12can be arranged in a regular array. For example, as shown inFIG.3, the plurality of silicon pillars12are regularly arranged in a first direction and a second direction, and the included angle between the first direction and the second direction is 90°, and in this case, the silicon pillar12with a square cross section can be formed. In addition, the included angle between the first direction and the second direction may be another angle, for example, an angle of 60°, and in this case, the silicon pillar12with a diamond or another shape in cross section can be formed.

Since a plurality of silicon pillars12are formed in a regular array arrangement, the processing can be relatively simple and easy to realize when the substrate is patterned.

When the substrate10is patterned, in one possible implementation, patterning the substrate to form the substrate layer11and the plurality of silicon pillars12may include the following operations.

A first mask layer131is formed on the substrate10, in which the first mask layer131has a first pattern extending in a first direction.

The first pattern is transferred to part of the substrate10by taking the first mask layer131as a mask.

A second mask layer132is formed on the substrate10, in which the second mask layer132has a second pattern extending in a second direction.

The second pattern is transferred to part of the substrate10by taking the second mask layer132as a mask to form the substrate layer11and the plurality of silicon pillars12.

It should be noted that when the substrate10is patterned, the substrate10may be patterned twice to form the plurality of silicon pillars12. Specifically, the first pattern is transferred to the substrate10to obtain a substrate10having the first pattern, and then the second pattern is transferred to the substrate10already having the first pattern. The first pattern and the second pattern divide the substrate10into a plurality of silicon pillars12, and the remaining part of substrate10forms the substrate layer11.

Referring toFIG.4,FIG.4is a schematic diagram of a structure obtained after forming a first mask layer131provided by embodiments of the disclosure. As shown in (c) ofFIG.4, the first mask layer131has a first pattern extending in the first direction; as shown in (a) ofFIG.4, a mask material is formed on the substrate10in AA′ direction; as shown in (b) ofFIG.4, no mask material is formed on the substrate10in BB′ direction.

The first pattern is transferred to the substrate10to form a plurality of first trenches1311in the substrate10, and the first mask layer131is removed. Referring toFIG.5,FIG.5is a schematic diagram of a structure obtained after transferring the first pattern provided by embodiments of the disclosure. As shown inFIGS.4and5, the first pattern is transferred to part of the substrate10by taking the first mask layer131as a mask, and the part that the first pattern is transferred to is the part for forming a plurality of silicon pillars12. Here, part of the substrate10not covered with a mask material may be removed by etching to a certain height, thereby forming a plurality of first trenches1311in the substrate10. After the first pattern is transferred to the substrate10, the first mask layer131is removed.

As shown in (a) ofFIG.5, the height of the substrate10is unchanged in AA direction, or may be slightly reduced due to partial loss when the first mask layer131is removed; as shown in (b) ofFIG.5, the upper part of the substrate10is removed in BB′ direction, and the height thereof is significantly reduced.

In addition, as shown in (c) ofFIG.5, in order to distinguish between removed and non-removed parts in the substrate10, part of the substrate10with the first trenches1311formed will be shown in a non-filling pattern, but it will be understood that although shown with non-filling pattern, the material of this part is the same as that of the remaining part.

After the first pattern is transferred to the substrate10, the second pattern is formed on the substrate10. Referring toFIG.6,FIG.6is a schematic diagram of a structure obtained after forming a second mask layer132provided by embodiments of the disclosure. As shown inFIGS.5and6, when forming the second mask layer132, intermediate structures133may be formed in the first trenches1311, or the height of the intermediate structure133may also be higher than the height of the first trenches1311to completely fill the first trenches1311and cove the substrate10.

TakingFIG.6as an example, the intermediate structures133fill the first trenches1311. Next, the second mask layer132is formed on the intermediate structure s133and the substrate10, and the second mask layer132has a second pattern extending in the second direction. InFIG.6, the included angle between the second direction and the first direction is 90°, in practice, the included angle may also be set to other angles according to actual requirements, which is not limited by the embodiments of the disclosure.

As shown in (a) ofFIG.6, the second mask layer132is formed on the substrate10in AA direction; as shown in (b) ofFIG.6, the second mask layer132is formed on the intermediate structure133in BB′ direction.

The second pattern is transferred to the substrate10and the intermediate structure133by taking the second mask layer132as a mask, and the second mask layer132and the intermediate structure133are removed; herein, the transfer depth of the second pattern is the same as that of the first pattern. Thus, the substrate layer11and the plurality of silicon pillars12are formed.

As shown inFIG.3, the transfer of the second pattern in the substrate10forms the second trenches1321, and the first trenches1311and the second trenches1321together form a gap between the silicon pillars12.

It should be noted that the intermediate structure133may be a material that is easier to remove by etching than the substrate10, thereby ensuring that the intermediate structure133can be completely removed.

When the substrate10is patterned, in another possible implementation, patterning the substrate to form the substrate layer11and the plurality of silicon pillars12may include the following operations.

A third mask layer is formed on the substrate10; the third mask layer includes a plurality of sub-masks134arranged in an array, and the third mask layer has a third pattern composed of a first pattern extending in a first direction and a second pattern extending in a second direction.

The third pattern is transferred to part of the substrate10by taking the third mask layer as a mask to form the substrate layer11and the plurality of silicon pillars12.

It should be noted that the embodiments of the disclosure can also pattern the substrate10only once to obtain a plurality of silicon pillars12. First, a third mask layer is formed on the substrate10, the third mask layer having a third pattern composed of a first pattern extending in a first direction and a second pattern extending in a second direction; herein, the included angle between the first direction and the second direction may be 90° or other angles which are not specifically limited in the embodiments of the disclosure. The third pattern is transferred to the substrate10, in this way the substrate layer11and the plurality of silicon pillars12are obtained.

Referring toFIG.7,FIG.7is a schematic diagram of a structure obtained after forming a third mask layer provided by embodiments of the disclosure. InFIG.7, as shown in (c) ofFIG.7, the third mask layer is composed of a plurality of sub-masks134that may be arranged in a regular array, the included angle between the first direction and the second direction is 90°, and the position of each sub-mask134is the position where corresponding silicon pillar12is subsequently formed. As shown in (a) ofFIG.7, a plurality of sub-masks134are formed on the substrate10in AA′ direction; as shown in (b) ofFIG.7, no sub-mask134is formed on the substrate10in BB′ direction.

The third pattern is transferred to the substrate10to a certain height by taking the third mask layer as a mask. In this way, the substrate is divided into an upper part and a lower part, in which the upper part forms a plurality of silicon pillars12and the lower part forms the substrate layer10. The structure after forming the substrate layer11and the plurality of silicon pillars12is shown inFIG.3.

It should also be noted that as shown inFIG.3, when the substrate10is patterned, the surface of the substrate layer11between the silicon pillars12may be formed into an arc shape as shown in the figure.

It should also be noted that all the first mask layer131, the second mask layer132and the third mask layer may be formed by deposition. The material of the mask layer may be photoresist or the like, and the mask layer can be a single layer, or a composite mask material may be selected in combination with the actual situation. When performing operations such as pattern transfer and mask layer removal, the process adopted may be etching, which is not specifically limited in the embodiments of the disclosure.

In S103, an oxide layer is formed on a surface of the substrate layer between the plurality of silicon pillars.

It should be noted that after patterning, the substrate10is divided into a plurality of silicon pillars12in the upper part and a substrate layer11in the lower part, and then an oxide layer14is formed on the surface of the substrate layer11between the plurality of silicon pillars12.

In some embodiments, forming the oxide layer14on the surface of the substrate layer11between the plurality of silicon pillars12includes the following operations.

An initial oxide layer141is formed on surfaces of the plurality of silicon pillars12and a surface of the substrate layer11between the plurality of silicon pillars12.

The initial oxide layer141on the surfaces of the plurality of silicon pillars12is removed, and the remaining initial oxide layer141forms the oxide layer14.

It should be noted that during forming the oxide layer14, an initial oxide layer141is first formed. Referring toFIG.8,FIG.8is a schematic diagram of a structure obtained after forming an initial oxide layer141provided by embodiments of the disclosure. As shown inFIG.8, the initial oxide layer141is formed on the surfaces of the plurality of silicon pillars12(inFIG.8, the surface of the silicon pillars12include the top surface and four side surfaces of each silicon pillar12) and on the surface of the substrate layer11between the plurality of silicon pillars12. The initial oxide layer141covers the top surfaces and four side surfaces of each silicon pillar12.

As shown in (a) ofFIG.8, it can be seen that in AA′ direction, the initial oxide layer141is formed on the surface of the substrate layer11and on the surfaces of the silicon pillars12; as shown in (b) ofFIG.8, it can be seen that in BB′ direction, no silicon pillar is present, and the initial oxide layer141is formed on the surface of the substrate layer11; as shown in (c) ofFIG.8, in the top view direction, the initial oxide layer141completely covers the substrate layer11and the plurality of silicon pillars12, and in (c), the profile of the initial oxide layer141formed on the top surface of the silicon pillars12is shown with a box in order to better show the positions of the silicon pillars12.

It should be noted that the material of the initial oxide layer141may be an oxide, in the embodiments of the disclosure, the material of the initial oxide layer141may be silicon oxide, and the process of forming the initial oxide layer141may be deposition (Dep), such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like.

Part of the initial oxide layer141is removed, and the remaining part of the initial oxide layer141forms the oxide layer14. Referring toFIG.9,FIG.9is a schematic diagram of a structure obtained after forming an oxide layer14provided by embodiments of the disclosure. As shown inFIGS.8and9, the initial oxide layer141on the top surface and the side surfaces of each silicon pillar12is removed, leaving only the initial oxide layer141formed on the surface of the substrate layer11, and the remaining initial oxide layer141forms the oxide layer14. Herein, the initial oxide layer141may be removed by etching.

In S104, an isolation structure is formed on the oxide layer, and gaps are provided between an upper part of the isolation structure and the silicon pillars.

It should be noted that an isolation structure is formed on the oxide layer14, and gaps are provided between an upper part of the isolation structure and the silicon pillars12. That is, a “circle gap” is formed between the four sides of each silicon pillar and the isolation structure.

In some embodiments, forming the isolation structure on the oxide layer14includes the following operations.

A first isolation structure15is formed on the surface of the oxide layer14.

A second isolation structure17is formed on the first isolation structure15, gaps are provided between the second isolation structure17and the silicon pillars12, and the first isolation structure15and the second isolation structure17constitute the isolation structure.

It should be noted that the isolation structure may be composed of the first isolation structure15and the second isolation structure17. During forming the isolation structure, a first isolation structure15is first formed on the surface of the oxide layer14, and then a second isolation structure17is formed on the first isolation structure15. The second isolation structure17is formed between the plurality of silicon pillars12and gaps are formed between the second isolation structure17and the silicon pillars12. That is, the gaps between the isolation structure and the silicon pillars12refers to the gaps between the second isolation structure17and the silicon pillars12.

Further, for the first isolation structure15, in some embodiments, forming the first isolation structure15on the surface of the oxide layer14includes the following operations.

An initial first isolation structure151is formed on the surface of the oxide layer14and a surface of each of the silicon pillars12.

The initial first isolation structure151is partially removed, and the remaining part of the initial first isolation structure151on the surface of the oxide layer14forms the first isolation structure15.

It should be noted that during forming the first isolation structure15, an initial first isolation structure151is first formed. Referring toFIG.10,FIG.10is a schematic diagram of a structure obtained after forming an initial isolation structure151provided by embodiments of the disclosure. As shown inFIG.10, the initial first isolation structure151is formed on the surface of the oxide layer14and on a surface of each of the silicon pillars12. The initial first isolation structure151covers the top surfaces and four side surfaces of each of the silicon pillars12.

As shown in (a) ofFIG.10, it can be seen that in AA′ direction, the initial first isolation structure151is formed on the surface of the oxide layer14and on the surfaces of the silicon pillars12; as shown in (b) ofFIG.10, it can be seen that in BB′ direction, the initial isolation structure151is formed on the surface of the oxide layer14; as shown in (c) ofFIG.10, in the top view direction, the initial isolation structure151completely covers the oxide layer14and the plurality of silicon pillars12, and in (c), the profile of the initial first isolation structure151formed on the top surface of the silicon pillars12is shown with a box in order to better show the positions of the silicon pillars12.

It should be noted that the material of the initial first isolation structure151may be silicon nitride, and the process for forming the initial first isolation structure151may be deposition, such as CVD, PVD, or the like.

The initial first isolation structure151is partially removed, and the remaining part of the initial first isolation structure151forms the first isolation structure15.

Referring toFIG.11,FIG.11is a schematic diagram of a structure obtained after forming a first isolation structure15provided by embodiments of the disclosure. As shown inFIGS.10and11, the initial isolation structure151located on the top surface of each silicon pillar12is removed, and the part of the initial first isolation structure151located on the side surfaces of each silicon pillar12is removed, leaving only the initial first isolation structure151formed on the surface of the oxide layer14, and the remaining part of the initial first isolation structure151forms the first isolation structure15. That is, the first isolation structure15completely covers the oxide layer14and is in direct contact with the adjacent silicon pillars12.

Herein, the initial first isolation structure151may be removed by etching.

For the second isolation structure17, in some embodiments, forming the second isolation structure17on the first isolation structure15includes the following operations.

Sacrificial layers16are formed on surfaces the silicon pillars12.

An initial second isolation structure171is formed on surfaces of the sacrificial layers16and on the first isolation structure15.

The initial second isolation structure171above a plane where top surfaces of the sacrificial layers16are located is removed, and the remaining part of the initial second isolation structure171forms the second isolation structure17.

The sacrificial layers16are removed to form the gaps between the isolation structure and the silicon pillars12.

It should be noted that during forming the second isolation structure17, the sacrificial layers16are first formed on the surfaces of the plurality of silicon pillars12. Referring toFIG.12,FIG.12is a schematic diagram of a structure obtained after forming sacrificial layers16provided by embodiments of the disclosure. As shown inFIG.12, the sacrificial layers16are formed on the surfaces of each silicon pillar12, specifically on the top surface and four side surfaces of each silicon pillar12. That is, the sacrificial layers16are formed only on the surfaces of the silicon pillars12while covering part of the first isolation structure15adjacent to the silicon pillars12, but are not formed on entire surface of the first isolation structure15.

As shown in (a) ofFIG.12, it can be seen that in AA′ direction, the sacrificial layers16are formed on the top surfaces and the side surfaces of the silicon pillars12; as shown in (b) ofFIG.12, it can be seen that in BB′ direction, no silicon pillar12is present, and the sacrificial layers16are not formed on the surface of the first isolation structure15(except part of the surface adjacent to the position in contact with the silicon pillar12), so that the sacrificial layers16cannot be seen in BB′ direction; as shown in (c) ofFIG.12, in the top view direction, the sacrificial layers16completely cover the plurality of silicon pillars12, and the gaps between the sacrificial layers16exposes the first isolation structure15.

It should be noted that the material of the sacrificial layer16may be oxide, such as silicon oxide. In some embodiments, the sacrificial layers16may also be formed by thermal oxidation.

It should be noted that the sacrificial layers16and the oxide layer14may be of the same material, for example both of which are made of silicon oxide. Therefore, they both are represented by filling with the same pattern in the drawings. When the sacrificial layers16are formed in this operation, the process adopted may be thermal oxidation, so that the surfaces of the silicon pillars12can be directly oxidized to form silicon oxide, so as to obtain the sacrificial layers16, without complicated process treatment, which is beneficial to simplifying the process. In contrast, if the sacrificial layer is formed by deposition, the sacrificial layers will also cover the surface of the first isolation structure15, and it is thus necessary to try to remove this part of the sacrificial layer, thereby resulting in a complicated process.

After the sacrificial layers16are formed, the initial second isolation structure171is formed. Referring toFIG.13,FIG.13is a schematic diagram of a structure obtained after forming an initial second isolation structure171provided by embodiments of the disclosure. As shown inFIG.13, an initial second isolation structure171is formed on surfaces of the sacrificial layers16and on the first isolation structure15. InFIG.13, the initial second isolation structure171completely covers the sacrificial layers16and the first isolation structure15and fills the gaps between the sacrificial layers16.

As shown in (a) ofFIG.13, it can be seen that in AA′ direction, the initial second isolation structure171is formed on the surfaces of the sacrificial layers16and on the surface of the first isolation structure15; as shown in (b) ofFIG.13, it can be seen that in BB′ direction, the initial second isolation structure171is completely formed on the first isolation structure15; as shown in (c) ofFIG.13, in the top view direction, the initial second isolation structure171completely covers the sacrificial layers16and the first isolation structure15.

It should be noted that the initial second isolation structure171and the first isolation structure15may be of the same material, for example, they both are made of silicon nitride. Therefore, both of them are shown with the same filling inFIG.13, and a line segment is added at the boundary between the two for convenience of distinguishing. It could be understood that in practice, there is generally no obvious dividing line between the first isolation structure15and the initial second isolation structure171because the materials of the first isolation structure15and the initial isolation structure171are the same. The initial second isolation structure171may be formed by deposition, such as CVD, PVD or the like.

After the initial second isolation structure171is formed, the initial second isolation structure171above a plane where top surfaces of the sacrificial layers16are located is removed, and the remaining part of the initial second isolation structure171forms the second isolation structure17. Referring toFIG.14,FIG.14is a schematic diagram of a structure obtained after forming a second isolation structure17provided by embodiments of the disclosure.

As shown in (a) ofFIG.14, it can be seen that in AA′ direction, the top surface of the second isolation structure17is flush with the top surfaces of the sacrificial layers16; as shown in (b) ofFIG.14, it can be seen that in BB′ direction, the second isolation structure17is completely formed on the first isolation structure15; as shown in (c) ofFIG.14, in the top view direction, the sacrificial layers16completely covers the silicon pillars12, thus no silicon pillar12can be seen in the top view, and only the sacrificial layers16and the second isolation structure17in the gaps between the sacrificial layers16can be seen.

It should be noted that as shown inFIG.14, the first isolation structure15and the second isolation structure17together constitute an isolation structure. The first isolation structure15is formed on the surface of the oxide layer14and completely covers the oxide layer14. The first isolation structure15is the bottom of the isolation structure. That is, the bottom of the isolation structure completely covers the oxide layer14.

In addition, the side surfaces of the first isolation structure15are in direct contact with the side surfaces of the adjacent silicon pillars12. That is, the side surfaces of the bottom of the isolation structure are in direct contact with the adjacent silicon pillars.

In this way, the side surfaces of the bottom of the isolation structure is in direct contact with the adjacent silicon pillars12, so that the silicon pillar12can be insulated from other components in the structure to avoid electric leakage.

The sacrificial layers16are removed, so that the gaps between the isolation structure and the silicon pillars12are formed. Referring toFIG.15,FIG.15is a schematic diagram of a structure obtained after removing the sacrificial layers16provided by embodiments of the disclosure. As shown inFIGS.14and15, the first isolation structure15and the second isolation structure17together constitute the isolation structure, and the sacrificial layers16are completely removed, and the positions where the sacrificial layers16were located form gaps between the isolation structure and the silicon pillars12, as indicated by arrows in (a) ofFIG.15. Herein, the sacrificial layers16may be removed by etching.

As shown in (a) ofFIG.15, it can be seen that in AA′ direction, gaps are formed between the isolation structure and the silicon pillars12; as shown inFIG.15(b), in BB′ direction, no silicon pillar12is presented, and the cross section in BB′ direction is not a cross section in which the gaps are formed, so that the gaps are not visible in BB′ direction, and only the isolation structure on the oxide layer14can be seen; as shown in (c) ofFIG.15, in the top view direction, the silicon pillars12, the first isolation structure15, and the second isolation structure17can be seen, in which the gaps between the second isolation structure17and the silicon pillars12expose the first isolation structure15.

In this way, in the embodiments of the disclosure, gaps formed between the isolation structure and the silicon pillars12are obtained by forming sacrificial layers16first and then removing the sacrificial layers16, and the gaps are used for subsequently forming the first conductive layer18. Furthermore, an isolation structure for insulating has been formed below the gaps. This method is simple, easy to realize, and cost effective.

In S105, a first conductive layer18is formed in the gaps.

It should be noted that, after the gaps are formed between the isolation structure and the silicon pillars12, the first conductive layer18is formed in the gaps. Herein, the first conductive layer18is used to form a lower electrode of the semiconductor structure.

In some embodiments, forming the first conductive layer18in the gaps includes the following operations.

An initial first conductive layer181is formed in the gaps and on top surfaces of the plurality of silicon pillars12and the isolation structure.

The initial first conductive layer181above a plane where top surfaces of the plurality of silicon pillars12are located is removed, and the remaining part of the initial first conductive layer181forms the first conductive layer18.

It should be noted that during forming the first conductive layer18, an initial first conductive layer181is first formed. Referring toFIG.16,FIG.16is a schematic diagram of a structure obtained after forming an initial first conductive layer181provided by embodiments of the disclosure. As shown inFIG.16, the initial first conductive layer181is formed in the gaps between the isolation structure and the silicon pillars12, as well as the top surface of the isolation structure and the top surface of each silicon pillar12. That is, the initial first conductive layer181completely fills the gaps between the isolation structure and each silicon pillar12and covers the top surface of the isolation structure and the top surface of each silicon pillar12.

As shown in (a) ofFIG.16, it can be seen that in AA′ direction, the initial first conductive layer181completely fills the gaps between the isolation structure and the silicon pillars12, and the initial first conductive layer181is also formed on the top surface of the isolation structure and the top surfaces the silicon pillars12; as shown in (b) ofFIG.16, it can be seen that in BB′ direction, the initial first conductive layer181covers the isolation structure; as shown in (c) ofFIG.16, since the initial first conductive layer181completely covers the top surface of the isolation structure and the top surface of each silicon pillar12, only the initial first conductive layer181can be seen in the top view direction.

Herein, the material of the initial first conductive layer181may be titanium nitride, and the process for forming the initial first conductive structure181may be deposition, such as CVD, PVD, or the like.

The initial first conductive layer181is partially removed to obtain a first conductive layer18. Referring toFIG.17,FIG.17is a schematic diagram of a structure obtained after forming a first conductive layer18provided by embodiments of the disclosure. As shown inFIGS.16and17, the initial first conductive layer181above a plane where top surfaces of the plurality of silicon pillars12are located is removed, and the initial first conductive layer181in the gaps between the isolation structure and the silicon pillars12is retained to form the first conductive layer18.

It should be noted that the initial first conductive layer181located on the plane where the top surfaces of the silicon pillars12are located may be removed by etching or chemical mechanical polishing (CMP). When using CMP, the part of the second isolation structure17which is higher than the plane where the top surfaces of the silicon pillars12is also removed at the same time.

Thus, in some embodiments, during removing the initial first conductive layer181above the plane where the top surfaces of the silicon pillars12are located, the method further includes the following operation.

The isolation structure located above the plane where the top surfaces of the silicon pillars12are located is removed.

It should be noted that, as shown inFIGS.16and17, the initial first conductive layer181and part of the isolation structure above the plane where the top surfaces of the silicon pillars12are located (the second isolation structure17higher than the plane where the top surfaces of the silicon pillars12are located) are removed.

In this way, the initial first conductive layer181and the isolation structure higher than the plane where the top surfaces of the silicon pillars12are located are removed simultaneously by CMP, which simplifies the process and reduces the cost.

As shown in (a) ofFIG.17, it can be seen that in AA direction, the top surfaces of the isolation structure (mainly the second isolation structure17), the first conductive layer18, and the silicon pillars12are flush; as shown inFIG.17(b), it can be seen that in BB′ direction, there is no silicon pillars12, and the isolation structure after being partially removed can be seen; as shown inFIG.17(c), in the top view direction, it can be seen that the first conductive layer18surrounds the silicon pillars12, the remaining area is the isolation structure, and the isolation structure that can be seen in the top view is the second isolation structure17.

In S106, the isolation structure is partially removed, and the isolation structure below the first conductive layer is retained to form an isolation layer.

It should be noted that after the first conductive layer18is formed, the isolation structure is partially removed so that only the isolation structure below the first conductive layer18is retained, and the remaining isolation structure forms the isolation layer19.

In some embodiments, partially removing the isolation structure includes the following operation.

The second isolation structure17is removed, and the first isolation structure15below the second isolation structure17is removed, and the first isolation structure15below the first conductive layer18is retained.

It should be noted that referring toFIG.18,FIG.18is a schematic diagram of a structure obtained after forming an isolation layer19provided by embodiments of the disclosure. As shown inFIGS.17and18, the second isolation structure17and the first isolation structure15located below the second isolation structure17are removed, and the remaining first isolation structure15below the first conductive layer18forms the isolation layer19.

As shown in (a) ofFIG.18, in AA′ direction, both the second isolation structure17and the first isolation structure15located below the second isolation structure17are removed, and the first isolation structure15located below the first conductive layer18is retained to form the isolation layer19; as shown in (b) ofFIG.18, in BB′ direction, there is no silicon pillars12, and the isolation structures in this direction are removed, so that only the substrate layer11and the oxide layer14can be seen in BB′ direction; as shown in (c) ofFIG.18, in the top view direction, it can be seen that the first conductive layer18surrounds the silicon pillars12, and the remaining area is the oxide layer14exposed by the gap between the first conductive layer18.

It could be understood that under the first conductive layer18, the isolation layer19also surrounds the silicon pillars12. That is, on the side surfaces of each silicon pillar12, the lower part of the side surfaces is formed with the isolation layer19surrounding the silicon pillar12, and the isolation layer19is in direct contact with the lower part of the side surfaces of the surrounding silicon pillar12; the upper part of the side surfaces is formed with the first conductive layer18surrounding the silicon pillar12, and the conductive layer18is also in direct contact with the upper part of the side surfaces of the surrounding silicon pillar12. In this way, the isolation layer19insulates the first conductive layer18from the substrate, that is, the lower electrode is insulated from the substrate, thereby preventing the occurrence of electric leakage.

It should also be noted that, in embodiments of the disclosure, materials of the first isolation structure15and the second isolation structure17are the same. Since the first isolation structure15and the second isolation structure17are made of the same material, when the isolation structure is removed, for example, by etching, the same etching selective ratio can be selected to remove the second isolation structure17and the first isolation structure15located below the second isolation structure17at the same time without performing multiple etching processes and adjusting additional etching parameters, thus simplifying the process flow and saving the cost.

In S107, a dielectric layer20and a second conductive layer21are formed on surfaces of the isolation layer19, the oxide layer14, the first conductive layer18and the silicon pillars12

It should be noted that after the isolation layer19is formed, the dielectric layer20and the second conductive layer21are further formed.

In some embodiments, forming the dielectric layer20and the second conductive layer21on the surfaces of the isolation layer19, the oxide layer14, the first conductive layer18and the silicon pillars12includes the following operations.

A dielectric layer20is formed on surfaces of the isolation layer19, the oxide layer14, the first conductive layer18and the silicon pillars12

The second conductive layer21is formed on the surface of the dielectric layer20.

It should be noted that referring toFIG.19,FIG.19is a schematic diagram of a structure obtained after forming a dielectric layer20provided by embodiments of the disclosure. As shown inFIG.19, the dielectric layer20is formed on the surfaces of the isolation layer19, the oxide layer14and each of the silicon pillars12.

As shown in (a) ofFIG.19, it can be seen in AA′ direction that the dielectric layer20is formed on the surfaces of the oxide layer14, the first conductive layer18and each of the silicon pillars12; as shown in (b) ofFIG.19, there is no silicon pillar12in BB′ direction, and therefore the dielectric layer20is formed on the surface of the oxide layer14in BB′ direction; as shown in (c) ofFIG.19, in the top view direction, since the dielectric layer20completely covers the isolation layer19, the oxide layer14, the first conductive layer18, and the silicon pillars12, only the dielectric layer20can be seen. In (c), the dielectric layer20covering the top surfaces of the silicon pillars12and the first conductive layer18is shown in a box in order to distinguish the dielectric layer20formed on different surfaces.

Herein, the material of the dielectric layer20may be a high dielectric constant (High K) material, such as hafnium oxide, zirconium oxide, lanthanum oxide, alumina, hafnium silicon oxide, hafnium nitrogen oxide, and the like. The dielectric layer20may be formed by deposition, such as CVD, PVD or the like.

After the dielectric layer20is formed, the second conductive layer21is formed on the surface of the dielectric layer20. Referring toFIG.20,FIG.20is a schematic diagram of the composition of a semiconductor structure100provided by embodiments of the disclosure. As shown inFIG.20, the second conductive layer21is formed on the surface of the dielectric layer20.

As shown in (a) ofFIG.20, in AA′ direction, the second conductive layer21is formed on the surface of the dielectric layer20; as shown in (b) ofFIG.20, in BB′ direction, since there is no silicon pillar12in this direction, only the second conductive layer21can be seen on the dielectric layer20; as shown in (c) ofFIG.20, in the top view direction, it can be seen that the second conductive layer21completely covers the dielectric layer20.

In addition, the second conductive layer21and the first conductive layer18may be of the same material, for example titanium nitride. Therefore, they both are shown with the same filling inFIG.20. Further, the second conductive layer21may be formed by deposition, such as CVD, PVD or the like.

As shown inFIG.20, the second conductive layer21completely fills the gap of the dielectric layer20.

It should be noted that as specifically shown in (b) ofFIG.20, the second conductive layer21completely fills the gap of the dielectric layer20.

Herein, the second conductive layer21is used for forming an upper electrode.

It should be noted that the semiconductor structure100may be a capacitor, herein the first conductive layer18is used for forming a lower electrode of the capacitor, the second conductive layer21is used for forming an upper electrode of the capacitor, and the dielectric layer20is a dielectric layer between the upper electrode and the lower electrode.

For comparison, referring toFIG.21,FIG.21is a simplified diagram of a process for forming a semiconductor structure provided by embodiments of the disclosure, which differs from the aforementioned method for manufacturing a semiconductor structure. As shown inFIG.21, in this method, after the oxide layer14is formed, a titanium nitride layer182is formed on the side surfaces of a plurality of silicon pillars12by selective atomic layer deposition (Selective ALD) of titanium nitride, and then the part of the bottom of the titanium nitride layer182in contact with the oxide layer14is removed to form an isolation layer19and other components. The process implementation of this method is difficult and the cost is high.

In contrast, a substrate is provided; the substrate is patterned to form a substrate layer and a plurality of silicon pillars; an oxide layer is formed on a surface of the substrate layer between the plurality of silicon pillars; an isolation structure is formed on the oxide layer, and gaps are provided between an upper part of the isolation structure and the silicon pillars; a first conductive layer is formed in the gaps; the isolation structure is partially removed, the isolation structure below the first conductive layer is retained to form an isolation layer; a dielectric layer and a second conductive layer are formed on surfaces of the isolation layer, the oxide layer, the first conductive layer and the silicon pillars. In this way, when manufacturing a semiconductor structure, gaps formed between the silicon pillar and the isolation structure, and a first conductive layer is formed in the gaps, then the isolation structure is partially removed to obtain the isolation layer, and then a dielectric layer and a second conductive layer are further formed. This manufacturing method has a simple process, is easy to implement, and the cost of manufacturing a semiconductor structure can be saved. In practice, the process is easier to implement.

Based on the method for manufacturing a semiconductor structure above-mentioned, the embodiments of the disclosure also provides a semiconductor structure, which is prepared by the manufacturing method described in any of the preceding embodiments. For example, reference is made toFIG.20, which is a schematic diagram of the composition of the semiconductor structure100provided by embodiments of the disclosure.

In some embodiments, the semiconductor structure100includes a capacitor where the upper electrode of the capacitor is the first conductive layer18and the lower electrode of the capacitor is the second conductive layer20.

For this semiconductor structure100, since the semiconductor structure100is prepared by the method for manufacturing a semiconductor structure described in the foregoing embodiment, the cost of manufacturing the semiconductor structure100is low, and the semiconductor structure100can be applied to a 3D memory with a higher integration, which is beneficial to the integration of the memory.

In yet another embodiment, reference is made toFIG.22, which is a schematic diagram of the composition of a semiconductor memory200provided by embodiments of the disclosure. As shown inFIG.22, the semiconductor memory200includes the semiconductor structure100described in the foregoing embodiments.

In some embodiments, the semiconductor memory200may be a 3D DRAM.

For this semiconductor memory200, since it includes the semiconductor structure100provided in the foregoing embodiments, a semiconductor memory with higher integration and precision can be obtained, which is beneficial to the integration of the semiconductor memory.

The description above is only preferred embodiments of the disclosure, and is not intended to limit the protection scope of the present disclosure.

It should be noted that, in the disclosure, the terms “including”, “comprising” or any other variation thereof are intended to encompass non-exclusive inclusion, so that a process, a method, an article or a device that includes a set of elements includes not only those elements but also other elements that are not explicitly listed, or also elements inherent to such a process, method, article or device. In the absence of further limitations, an element defined by the phrase “includes a . . . ” does not exclude the existence of another identical element in the process, method, article or device in which the elements is included.

The above serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

The method disclosed in the embodiments of several methods provided in the disclosure can be arbitrarily combined as long as there is no conflict therebetween to obtain a new embodiment of a method.

The features disclosed in the embodiments of several products provided in the disclosure can be arbitrarily combined as long as there is no conflict therebetween to obtain a new embodiment of a product.

The features disclosed in the embodiments of several methods or devices provided in the disclosure can be arbitrarily combined as long as there is no conflict therebetween to obtain a new embodiment of a method or a device.

The descriptions above are only some specific embodiments of the present disclosure, and are not intended to limit the scope of protection of the embodiments of the present disclosure. Any change and replacement is easily to think within the technical scope of the embodiments of the present by those skilled in the art, and fall with the protection scope of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be subject to the scope of protection of the claims.